commit fedfd922705d411f1905dde944f13afe655bbb01 Author: muellerlu Date: Fri May 29 10:19:13 2026 +0200 Initial commit diff --git a/.cleanup_lukas.sh.swp b/.cleanup_lukas.sh.swp new file mode 100644 index 0000000..59a5a9d Binary files /dev/null and b/.cleanup_lukas.sh.swp differ diff --git a/atpg.log b/atpg.log new file mode 100644 index 0000000..a297983 --- /dev/null +++ b/atpg.log @@ -0,0 +1,301 @@ +charapallivenkatsaja@efiapps0:/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock$ tessent -shell +// Tessent Shell 2023.4-p1 Mon Feb 19 16:22:02 GMT 2024 +// Unpublished work. Copyright 2024 Siemens +// +// This material contains trade secrets or otherwise confidential +// information owned by Siemens Industry Software Inc. or its affiliates +// (collectively, "SISW"), or its licensors. Access to and use of this +// information is strictly limited as set forth in the Customer's +// applicable agreements with SISW. +// +// Siemens software executing under x86-64 Linux on Thu May 28 17:29:18 CEST 2026. +// 64 bit version +// Host: efiapps0.ads1.fh-nuernberg.de (12 x 3.5 GHz, 48014 MB RAM, 24575 MB Swap) +// +SETUP> source scri +scripts scripts_risc_v +SETUP> source scripts_risc_v/5_atpg.do +// sub-command: set_context patterns -scan +// sub-command: set_tsdb_output_directory /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/tsdb_outdir +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/PLL.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/PLL.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/PLL.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/IO.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/IO.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/IO.fslib +// sub-command: read_design cpu -design_id Scan_0 +// sub-command: add_black_boxes -modules " MemGen_16_10 " +// Command 'add_black_boxes' requires an elaborated design. Automatically elaborating the design ... +// Note: 36 duplicate cell library models were read. The last model read of the same name was kept. +// To see detailed messages per duplicate model, issue 'set_cell_library_options -report_duplicate_models on' +// before issuing 'read_cell_library'. +// Warning: 1 cell library model contained 2 floating model outputs. +// To see detailed messages per model, issue 'set_cell_library_options -report_floating_nets on' +// before issuing 'read_cell_library'. +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X1_SVT' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X2_SVT' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X4_SVT' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X8_SVT' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X1' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X2' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X4' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X8' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X1_HVT' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X2_HVT' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X4_HVT' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X8_HVT' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X1_LVT' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X2_LVT' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X4_LVT' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X8_LVT' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' +// Note: Top design is 'cpu'. +// Warning: 32 cases: Unused net in DFT library model +// Warning: 106 cases: Undriven net in netlist module +// Warning: 1 case: Floating input on instance in netlist +// Warning: 47 cases: Net in netlist not connected +// Note: Issue set_current_design with the -show_elaboration_warnings option to see more details about previous warnings +// Design elaboration successful. +// sub-command: add_black_boxes -modules " MemGen_32_11 " +// sub-command: add_black_boxes -modules " main_mem " +// sub-command: set_current_design cpu +// Warning: Undefined modules were found. +// Before using "set_system_mode" or "create_flat_model", you must either define +// the missing modules using "read_verilog" and/or "read_cell_library", or use the +// following command to treat them as black boxes: + add_black_boxes -modules { \ + MemGen_16_10 \ + } +// You can also use "add_black_boxes -auto" to black box all undefined modules but +// it is recommended that you do not add this command to your dofile. Doing so may +// unintentionally black-box new undefined modules in future runs. +// Warning: 106 cases: Undriven net in netlist module +// Warning: 1 case: Floating input on instance in netlist +// Warning: 47 cases: Net in netlist not connected +// Note: Issue set_current_design with the -show_elaboration_warnings option to see more details about previous warnings +// Note: Design level set to 'physical_block' from previous settings +// sub-command: set_design_level physical_block +// sub-command: import_scan_mode unwrapped +// Resetting design. +// Warning: The current mode name was not specified and will be set to 'unwrapped'. +// Different ATPG configurations should use different mode names, otherwise +// they will overwrite each other in the TSDB when 'write_tsdb_data -replace' is called. +// If you will have multiple ATPG configurations for this scan mode of this design, +// use the 'set_current_mode' command to change the current mode name. +// sub-command: set_system_mode analysis +// Warning: Rule FN1 violation occurs 152 times +// Flattening process completed, cell instances=4041, gates=16395, PIs=13, POs=12, CPU time=0.08 sec. +// --------------------------------------------------------------------------- +// Begin circuit learning analyses. +// -------------------------------- +// Learning completed, CPU time=0.04 sec. +// --------------------------------------------------------------------------- +// Begin scan chain identification process, memory elements = 1059. +// --------------------------------------------------------------------------- +// Begin simulation of load_unload procedure. +// Simulation of load_unload procedure completed, CPU time=0.0 sec. +// Chain = unwrapped_chain1 successfully traced with scan_cells = 256. +// Chain = unwrapped_chain2 successfully traced with scan_cells = 256. +// Chain = unwrapped_chain3 successfully traced with scan_cells = 256. +// Chain = unwrapped_chain4 successfully traced with scan_cells = 256. +// 1024 scan cells have been identified in 4 scan chains. +// Longest scan chain has 256 scan cells. +// --------------------------------------------------------------------------- +// Begin transparent latch checking for 35 latches. +// --------------------------------------------------------------------------- +// Number transparent latches = 35. +// --------------------------------------------------------------------------- +// Begin scan clock rules checking. +// --------------------------------------------------------------------------- +// 1 scan clock/set/reset lines have been identified. +// All scan clocks successfully passed off-state check. +// Capture clock is set to clk_25mhz. +// --------------------------------------------------------------------------- +// 35 non-scan memory elements are identified. +// --------------------------------------------------------------------------- +// 35 non-scan memory elements are identified as TLA. (D5) +// --------------------------------------------------------------------------- +// 64 gates may have an observable X-state. (E5) +// sub-command: report_clocks +User-defined Clock (1): +========================= + + Sync and Async Source Clock + ============================ + ----------- --------- -------- + Name Off State Internal + ----------- --------- -------- + 'clk_25mhz' 0 No + +// sub-command: report_drc_rules +D5: #fails=35 handling=warning (non-scan memory element) +E5: #fails=64 handling=note (X-state propagation) +// sub-command: set_fault_type stuck +// sub-command: add_faults -all +// sub-command: create_patterns +// | ------------------------------------------------------------------------------------------------------------------ | +// | Analyzing the design | +// | | +// | Current clock restriction setting: Domain_clock (edge interaction) | +// | (optimal) | +// | | +// | Current abort limit setting: 30 | +// | Calling: set_abort_limit 300 100 | +// | ------------------------------------------------------------------------------------------------------------------ | +// | | +// | Current sequential depth: 0 (optimal) | +// | | +// | ------------------------------------------------------------------------------------------------------------------ | +// ------------------------------------------------------------------------ +// Simulation performed for #gates = 16395 #faults = 4988 +// system mode = analysis pattern source = internal patterns +// ------------------------------------------------------------------------ +// #patterns test #faults #faults # eff. # test process RE/AU/AAB +// simulated coverage in list detected patterns patterns CPU time +// --- ------ --- --- --- --- 6.31 sec 0/27368/0 +// 16 25.95% 0 2239 10 10 6.32 sec +// ----------------------------------------------------------------------- +// Performing redundant fault identification for 27368 faults +// ----------------------------------------------------------------------- +// deterministic ATPG invoked with abort limit = 300 +// # red. # non-red. # abort # remn. progress test process +// faults faults faults faults coverage CPU time +// 20 27338 10 0 100.00% 25.96% 1903.57 sec + + Statistics Report + Stuck-at Faults +--------------------------------------- +Fault Classes #faults + (total) +----------------------- -------------- + FU (full) 39020 + --------------------- -------------- + DS (det_simulation) 2239 ( 5.74%) + DI (det_implication) 7351 (18.84%) + UU (unused) 2062 ( 5.28%) + RE (redundant) 20 ( 0.05%) + AU (atpg_untestable) 27348 (70.09%) +--------------------------------------- +Fault Sub-classes + --------------------- + AU (atpg_untestable) + BB (black_boxes) 24599 (63.04%) + Unclassified 2749 ( 7.05%) +--------------------------------------- +Coverage + --------------------- + test_coverage 25.96% + fault_coverage 24.58% + atpg_effectiveness 100.00% +--------------------------------------- +#test_patterns 10 +#simulated_patterns 16 +CPU_time (secs) 1925.7 +--------------------------------------- + +// sub-command: report_statistics + Statistics Report + Stuck-at Faults +--------------------------------------- +Fault Classes #faults + (total) +----------------------- -------------- + FU (full) 39020 + --------------------- -------------- + DS (det_simulation) 2239 ( 5.74%) + DI (det_implication) 7351 (18.84%) + UU (unused) 2062 ( 5.28%) + RE (redundant) 20 ( 0.05%) + AU (atpg_untestable) 27348 (70.09%) +--------------------------------------- +Fault Sub-classes + --------------------- + AU (atpg_untestable) + BB (black_boxes) 24599 (63.04%) + Unclassified 2749 ( 7.05%) +--------------------------------------- +Coverage + --------------------- + test_coverage 25.96% + fault_coverage 24.58% + atpg_effectiveness 100.00% +--------------------------------------- +#test_patterns 10 +#simulated_patterns 16 +CPU_time (secs) 1925.7 +--------------------------------------- + +// sub-command: report_faults -summary + Statistics Report + Stuck-at Faults +--------------------------------------- +Fault Classes #faults + (total) +----------------------- -------------- + FU (full) 39020 + --------------------- -------------- + DS (det_simulation) 2239 ( 5.74%) + DI (det_implication) 7351 (18.84%) + UU (unused) 2062 ( 5.28%) + RE (redundant) 20 ( 0.05%) + AU (atpg_untestable) 27348 (70.09%) +--------------------------------------- +Fault Sub-classes + --------------------- + AU (atpg_untestable) + BB (black_boxes) 24599 (63.04%) + Unclassified 2749 ( 7.05%) +--------------------------------------- +Coverage + --------------------- + test_coverage 25.96% + fault_coverage 24.58% + atpg_effectiveness 100.00% +--------------------------------------- +#test_patterns 10 +#simulated_patterns 16 +CPU_time (secs) 1925.7 +--------------------------------------- + +// sub-command: write_patterns cpu_patterns.stil -stil -replace +// sub-command: write_patterns cpu_patterns_serial.v -verilog -serial -replace +// sub-command: write_tsdb_data -replace +// Writing ./oasys.tessent.00/tsdb_outdir/logic_test_cores/cpu_Scan_0.logic_test_core/cpu.atpg_mode_unwrapped/cpu_unwrapped.tcd.gz +// Writing ./oasys.tessent.00/tsdb_outdir/logic_test_cores/cpu_Scan_0.logic_test_core/cpu.atpg_mode_unwrapped/cpu_unwrapped.flat.gz +// Writing ./oasys.tessent.00/tsdb_outdir/logic_test_cores/cpu_Scan_0.logic_test_core/cpu.atpg_mode_unwrapped/cpu_unwrapped_stuck.patdb +// Writing ./oasys.tessent.00/tsdb_outdir/logic_test_cores/cpu_Scan_0.logic_test_core/cpu.atpg_mode_unwrapped/cpu_unwrapped_stuck.faults.gz +// sub-command: exit + diff --git a/cleanup.sh b/cleanup.sh new file mode 100755 index 0000000..2e25f9a --- /dev/null +++ b/cleanup.sh @@ -0,0 +1,20 @@ +#!/bin/sh +rm -rf output +mkdir output +mkdir output/odb +mkdir output/db +mkdir output/logs +rm -rf `find . -type f -name "oasys.*"` + +# Gruppe setzen + volle Rechte + setgid (neue Dateien erben Gruppe) +chgrp -R projekt01 output +chmod -R 2775 output + +# Zusätzlich für alle Projekt-Dateien (falls Oasys außerhalb von output/ schreibt) +chgrp -R projekt01 . 2>/dev/null +find . -type d -exec chmod g+rwxs {} \; 2>/dev/null +find . -type f -exec chmod g+rw {} \; 2>/dev/null + +echo "\n-------------------------------------" +echo "\nCleanup Complete" +echo "\n-------------------------------------\n" diff --git a/commands.txt b/commands.txt new file mode 100644 index 0000000..3d501ad --- /dev/null +++ b/commands.txt @@ -0,0 +1,5 @@ +$OASYS_HOME/bin/oasys -log output/logs/synth.log + +source scripts_counter/1_read_design.tcl + +source scripts_counter/2_synthesize_optimize.tcl diff --git a/constraints/.riscv.sdc.swn b/constraints/.riscv.sdc.swn new file mode 100644 index 0000000..a6a73c9 Binary files /dev/null and b/constraints/.riscv.sdc.swn differ diff --git a/constraints/.riscv.sdc.swp b/constraints/.riscv.sdc.swp new file mode 100644 index 0000000..5c5f02f Binary files /dev/null and b/constraints/.riscv.sdc.swp differ diff --git a/constraints/counter.sdc b/constraints/counter.sdc new file mode 100644 index 0000000..c1747bd --- /dev/null +++ b/constraints/counter.sdc @@ -0,0 +1 @@ +create_clock -name clk -period 10 [get_ports clk] diff --git a/constraints/cts_constraints.sdc b/constraints/cts_constraints.sdc new file mode 100755 index 0000000..72e3110 --- /dev/null +++ b/constraints/cts_constraints.sdc @@ -0,0 +1,880 @@ +create_clock -name lfxt_clk -period 600 -waveform { 0 300 } [get_pins lfxt_clk_pad/C ] +create_clock -name sysclk_byp -period 600 -waveform { 0 300 } [get_pins sysclk_byp_pad/C ] +create_clock -name usbclk_byp -period 600 -waveform { 0 300 } [get_pins usbclk_byp_pad/C ] +create_clock -name vsysclk -period 15 -waveform { 0 7.5 } +create_clock -name vsysclk_ddr -period 7.5 -waveform { 0 3.75 } +create_clock -name sysclk -period 2 -waveform { 0 1 } [get_pins i_MAIN_PLL/PLLOUT] +create_clock -name usbclk -period 8 -waveform { 0 4 } [get_pins i_USB_PLL/PLLOUT] + + +#create_generated_clock -name sysclk -source i_MAIN_PLL/REF -master_clock lfxt_clk -multiply_by 40 -add [get_pins i_MAIN_PLL/PLLOUT] +#create_generated_clock -name usbclk -source i_USB_PLL/REF -master_clock lfxt_clk -multiply_by 6 -add [get_pins i_USB_PLL/PLLOUT] + +set_clock_uncertainty -setup 0.2 [get_clocks sysclk] +set_clock_uncertainty -setup 0.1 [get_clocks usbclk] +set_false_path -from [get_ports nmi] +set_false_path -from [get_ports reset_n] +set_input_delay -clock vsysclk 10.5 [get_ports reset_n] +set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[15] }] +set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[14] }] +set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[13] }] +set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[12] }] +set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[11] }] +set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[10] }] +set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[9] }] +set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[8] }] +set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[7] }] +set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[6] }] +set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[5] }] +set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[4] }] +set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[3] }] +set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[2] }] +set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[1] }] +set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_0[0] }] +set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[15] }] +set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[14] }] +set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[13] }] +set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[12] }] +set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[11] }] +set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[10] }] +set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[9] }] +set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[8] }] +set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[7] }] +set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[6] }] +set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[5] }] +set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[4] }] +set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[3] }] +set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[2] }] +set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[1] }] +set_input_delay -clock vsysclk 10.5 [get_ports { BS_data_1[0] }] +set_input_delay -clock vsysclk 10.5 [get_ports nmi] +set_input_delay -clock vsysclk 10.5 [get_ports scan_mode] +set_input_delay -clock vsysclk 10.5 [get_ports sysclk_byp] +set_input_delay -clock vsysclk 10.5 [get_ports usbclk_byp] +set_output_delay -clock vsysclk 4.5 [get_ports mclk] +set_output_delay -clock vsysclk 4.5 [get_ports BS_ren_0] +set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[16] }] +set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[15] }] +set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[14] }] +set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[13] }] +set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[12] }] +set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[11] }] +set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[10] }] +set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[9] }] +set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[8] }] +set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[7] }] +set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[6] }] +set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[5] }] +set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[4] }] +set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[3] }] +set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[2] }] +set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[1] }] +set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_0[0] }] +set_output_delay -clock vsysclk 4.5 [get_ports BS_ren_1] +set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[16] }] +set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[15] }] +set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[14] }] +set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[13] }] +set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[12] }] +set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[11] }] +set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[10] }] +set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[9] }] +set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[8] }] +set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[7] }] +set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[6] }] +set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[5] }] +set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[4] }] +set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[3] }] +set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[2] }] +set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[1] }] +set_output_delay -clock vsysclk 4.5 [get_ports { BS_addr_1[0] }] +set_output_delay -clock vsysclk 4.5 [get_ports ddr0_cke] +set_output_delay -clock vsysclk 4.5 [get_ports ddr0_cs_n] +set_output_delay -clock vsysclk 4.5 [get_ports ddr0_we_n] +set_output_delay -clock vsysclk 4.5 [get_ports ddr0_cas_n] +set_output_delay -clock vsysclk 4.5 [get_ports ddr0_ras_n] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_adr[12] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_adr[11] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_adr[10] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_adr[9] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_adr[8] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_adr[7] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_adr[6] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_adr[5] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_adr[4] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_adr[3] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_adr[2] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_adr[1] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_adr[0] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_ba[1] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_ba[0] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dm[3] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dm[2] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dm[1] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dm[0] }] +set_output_delay -clock vsysclk 4.5 [get_ports ddr1_cke] +set_output_delay -clock vsysclk 4.5 [get_ports ddr1_cs_n] +set_output_delay -clock vsysclk 4.5 [get_ports ddr1_we_n] +set_output_delay -clock vsysclk 4.5 [get_ports ddr1_cas_n] +set_output_delay -clock vsysclk 4.5 [get_ports ddr1_ras_n] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_adr[12] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_adr[11] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_adr[10] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_adr[9] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_adr[8] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_adr[7] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_adr[6] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_adr[5] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_adr[4] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_adr[3] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_adr[2] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_adr[1] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_adr[0] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_ba[1] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_ba[0] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dm[3] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dm[2] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dm[1] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dm[0] }] +set_output_delay -clock vsysclk 4.5 [get_ports ddr2_cke] +set_output_delay -clock vsysclk 4.5 [get_ports ddr2_cs_n] +set_output_delay -clock vsysclk 4.5 [get_ports ddr2_we_n] +set_output_delay -clock vsysclk 4.5 [get_ports ddr2_cas_n] +set_output_delay -clock vsysclk 4.5 [get_ports ddr2_ras_n] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_adr[12] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_adr[11] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_adr[10] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_adr[9] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_adr[8] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_adr[7] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_adr[6] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_adr[5] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_adr[4] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_adr[3] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_adr[2] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_adr[1] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_adr[0] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_ba[1] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_ba[0] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dm[3] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dm[2] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dm[1] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dm[0] }] +set_output_delay -clock vsysclk 4.5 [get_ports ddr3_cke] +set_output_delay -clock vsysclk 4.5 [get_ports ddr3_cs_n] +set_output_delay -clock vsysclk 4.5 [get_ports ddr3_we_n] +set_output_delay -clock vsysclk 4.5 [get_ports ddr3_cas_n] +set_output_delay -clock vsysclk 4.5 [get_ports ddr3_ras_n] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_adr[12] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_adr[11] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_adr[10] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_adr[9] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_adr[8] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_adr[7] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_adr[6] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_adr[5] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_adr[4] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_adr[3] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_adr[2] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_adr[1] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_adr[0] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_ba[1] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_ba[0] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dm[3] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dm[2] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dm[1] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dm[0] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[31] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[30] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[29] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[28] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[27] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[26] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[25] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[24] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[23] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[22] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[21] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[20] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[19] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[18] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[17] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[16] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[15] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[14] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[13] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[12] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[11] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[10] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[9] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[8] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[7] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[6] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[5] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[4] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[3] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[2] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[1] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr0_dq[0] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[31] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[30] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[29] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[28] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[27] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[26] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[25] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[24] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[23] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[22] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[21] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[20] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[19] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[18] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[17] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[16] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[15] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[14] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[13] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[12] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[11] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[10] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[9] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[8] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[7] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[6] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[5] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[4] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[3] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[2] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[1] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr1_dq[0] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[31] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[30] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[29] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[28] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[27] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[26] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[25] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[24] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[23] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[22] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[21] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[20] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[19] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[18] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[17] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[16] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[15] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[14] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[13] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[12] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[11] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[10] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[9] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[8] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[7] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[6] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[5] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[4] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[3] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[2] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[1] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr2_dq[0] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[31] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[30] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[29] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[28] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[27] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[26] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[25] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[24] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[23] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[22] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[21] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[20] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[19] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[18] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[17] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[16] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[15] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[14] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[13] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[12] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[11] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[10] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[9] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[8] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[7] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[6] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[5] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[4] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[3] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[2] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[1] }] +set_output_delay -clock vsysclk 4.5 [get_ports { ddr3_dq[0] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[31] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[30] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[29] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[28] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[27] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[26] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[25] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[24] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[23] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[22] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[21] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[20] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[19] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[18] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[17] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[16] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[15] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[14] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[13] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[12] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[11] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[10] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[9] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[8] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[7] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[6] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[5] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[4] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[3] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[2] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[1] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr0_dq[0] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[31] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[30] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[29] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[28] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[27] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[26] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[25] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[24] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[23] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[22] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[21] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[20] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[19] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[18] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[17] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[16] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[15] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[14] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[13] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[12] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[11] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[10] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[9] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[8] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[7] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[6] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[5] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[4] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[3] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[2] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[1] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr1_dq[0] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[31] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[30] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[29] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[28] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[27] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[26] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[25] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[24] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[23] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[22] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[21] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[20] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[19] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[18] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[17] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[16] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[15] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[14] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[13] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[12] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[11] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[10] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[9] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[8] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[7] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[6] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[5] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[4] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[3] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[2] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[1] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr2_dq[0] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[31] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[30] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[29] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[28] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[27] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[26] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[25] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[24] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[23] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[22] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[21] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[20] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[19] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[18] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[17] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[16] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[15] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[14] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[13] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[12] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[11] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[10] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[9] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[8] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[7] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[6] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[5] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[4] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[3] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[2] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[1] }] +set_input_delay -clock vsysclk_ddr 5.25 [get_ports { ddr3_dq[0] }] +set_load 10 [get_ports mclk] +set_load 10 [get_ports BS_ren_0] +set_load 10 [get_ports { BS_addr_0[16] }] +set_load 10 [get_ports { BS_addr_0[15] }] +set_load 10 [get_ports { BS_addr_0[14] }] +set_load 10 [get_ports { BS_addr_0[13] }] +set_load 10 [get_ports { BS_addr_0[12] }] +set_load 10 [get_ports { BS_addr_0[11] }] +set_load 10 [get_ports { BS_addr_0[10] }] +set_load 10 [get_ports { BS_addr_0[9] }] +set_load 10 [get_ports { BS_addr_0[8] }] +set_load 10 [get_ports { BS_addr_0[7] }] +set_load 10 [get_ports { BS_addr_0[6] }] +set_load 10 [get_ports { BS_addr_0[5] }] +set_load 10 [get_ports { BS_addr_0[4] }] +set_load 10 [get_ports { BS_addr_0[3] }] +set_load 10 [get_ports { BS_addr_0[2] }] +set_load 10 [get_ports { BS_addr_0[1] }] +set_load 10 [get_ports { BS_addr_0[0] }] +set_load 10 [get_ports BS_ren_1] +set_load 10 [get_ports { BS_addr_1[16] }] +set_load 10 [get_ports { BS_addr_1[15] }] +set_load 10 [get_ports { BS_addr_1[14] }] +set_load 10 [get_ports { BS_addr_1[13] }] +set_load 10 [get_ports { BS_addr_1[12] }] +set_load 10 [get_ports { BS_addr_1[11] }] +set_load 10 [get_ports { BS_addr_1[10] }] +set_load 10 [get_ports { BS_addr_1[9] }] +set_load 10 [get_ports { BS_addr_1[8] }] +set_load 10 [get_ports { BS_addr_1[7] }] +set_load 10 [get_ports { BS_addr_1[6] }] +set_load 10 [get_ports { BS_addr_1[5] }] +set_load 10 [get_ports { BS_addr_1[4] }] +set_load 10 [get_ports { BS_addr_1[3] }] +set_load 10 [get_ports { BS_addr_1[2] }] +set_load 10 [get_ports { BS_addr_1[1] }] +set_load 10 [get_ports { BS_addr_1[0] }] +set_load 10 [get_ports ddr0_cke] +set_load 10 [get_ports ddr0_cs_n] +set_load 10 [get_ports ddr0_we_n] +set_load 10 [get_ports ddr0_cas_n] +set_load 10 [get_ports ddr0_ras_n] +set_load 10 [get_ports { ddr0_adr[12] }] +set_load 10 [get_ports { ddr0_adr[11] }] +set_load 10 [get_ports { ddr0_adr[10] }] +set_load 10 [get_ports { ddr0_adr[9] }] +set_load 10 [get_ports { ddr0_adr[8] }] +set_load 10 [get_ports { ddr0_adr[7] }] +set_load 10 [get_ports { ddr0_adr[6] }] +set_load 10 [get_ports { ddr0_adr[5] }] +set_load 10 [get_ports { ddr0_adr[4] }] +set_load 10 [get_ports { ddr0_adr[3] }] +set_load 10 [get_ports { ddr0_adr[2] }] +set_load 10 [get_ports { ddr0_adr[1] }] +set_load 10 [get_ports { ddr0_adr[0] }] +set_load 10 [get_ports { ddr0_ba[1] }] +set_load 10 [get_ports { ddr0_ba[0] }] +set_load 10 [get_ports { ddr0_dm[3] }] +set_load 10 [get_ports { ddr0_dm[2] }] +set_load 10 [get_ports { ddr0_dm[1] }] +set_load 10 [get_ports { ddr0_dm[0] }] +set_load 10 [get_ports ddr1_cke] +set_load 10 [get_ports ddr1_cs_n] +set_load 10 [get_ports ddr1_we_n] +set_load 10 [get_ports ddr1_cas_n] +set_load 10 [get_ports ddr1_ras_n] +set_load 10 [get_ports { ddr1_adr[12] }] +set_load 10 [get_ports { ddr1_adr[11] }] +set_load 10 [get_ports { ddr1_adr[10] }] +set_load 10 [get_ports { ddr1_adr[9] }] +set_load 10 [get_ports { ddr1_adr[8] }] +set_load 10 [get_ports { ddr1_adr[7] }] +set_load 10 [get_ports { ddr1_adr[6] }] +set_load 10 [get_ports { ddr1_adr[5] }] +set_load 10 [get_ports { ddr1_adr[4] }] +set_load 10 [get_ports { ddr1_adr[3] }] +set_load 10 [get_ports { ddr1_adr[2] }] +set_load 10 [get_ports { ddr1_adr[1] }] +set_load 10 [get_ports { ddr1_adr[0] }] +set_load 10 [get_ports { ddr1_ba[1] }] +set_load 10 [get_ports { ddr1_ba[0] }] +set_load 10 [get_ports { ddr1_dm[3] }] +set_load 10 [get_ports { ddr1_dm[2] }] +set_load 10 [get_ports { ddr1_dm[1] }] +set_load 10 [get_ports { ddr1_dm[0] }] +set_load 10 [get_ports ddr2_cke] +set_load 10 [get_ports ddr2_cs_n] +set_load 10 [get_ports ddr2_we_n] +set_load 10 [get_ports ddr2_cas_n] +set_load 10 [get_ports ddr2_ras_n] +set_load 10 [get_ports { ddr2_adr[12] }] +set_load 10 [get_ports { ddr2_adr[11] }] +set_load 10 [get_ports { ddr2_adr[10] }] +set_load 10 [get_ports { ddr2_adr[9] }] +set_load 10 [get_ports { ddr2_adr[8] }] +set_load 10 [get_ports { ddr2_adr[7] }] +set_load 10 [get_ports { ddr2_adr[6] }] +set_load 10 [get_ports { ddr2_adr[5] }] +set_load 10 [get_ports { ddr2_adr[4] }] +set_load 10 [get_ports { ddr2_adr[3] }] +set_load 10 [get_ports { ddr2_adr[2] }] +set_load 10 [get_ports { ddr2_adr[1] }] +set_load 10 [get_ports { ddr2_adr[0] }] +set_load 10 [get_ports { ddr2_ba[1] }] +set_load 10 [get_ports { ddr2_ba[0] }] +set_load 10 [get_ports { ddr2_dm[3] }] +set_load 10 [get_ports { ddr2_dm[2] }] +set_load 10 [get_ports { ddr2_dm[1] }] +set_load 10 [get_ports { ddr2_dm[0] }] +set_load 10 [get_ports ddr3_cke] +set_load 10 [get_ports ddr3_cs_n] +set_load 10 [get_ports ddr3_we_n] +set_load 10 [get_ports ddr3_cas_n] +set_load 10 [get_ports ddr3_ras_n] +set_load 10 [get_ports { ddr3_adr[12] }] +set_load 10 [get_ports { ddr3_adr[11] }] +set_load 10 [get_ports { ddr3_adr[10] }] +set_load 10 [get_ports { ddr3_adr[9] }] +set_load 10 [get_ports { ddr3_adr[8] }] +set_load 10 [get_ports { ddr3_adr[7] }] +set_load 10 [get_ports { ddr3_adr[6] }] +set_load 10 [get_ports { ddr3_adr[5] }] +set_load 10 [get_ports { ddr3_adr[4] }] +set_load 10 [get_ports { ddr3_adr[3] }] +set_load 10 [get_ports { ddr3_adr[2] }] +set_load 10 [get_ports { ddr3_adr[1] }] +set_load 10 [get_ports { ddr3_adr[0] }] +set_load 10 [get_ports { ddr3_ba[1] }] +set_load 10 [get_ports { ddr3_ba[0] }] +set_load 10 [get_ports { ddr3_dm[3] }] +set_load 10 [get_ports { ddr3_dm[2] }] +set_load 10 [get_ports { ddr3_dm[1] }] +set_load 10 [get_ports { ddr3_dm[0] }] +set_load 10 [get_ports { ddr0_dq[31] }] +set_load 10 [get_ports { ddr0_dq[30] }] +set_load 10 [get_ports { ddr0_dq[29] }] +set_load 10 [get_ports { ddr0_dq[28] }] +set_load 10 [get_ports { ddr0_dq[27] }] +set_load 10 [get_ports { ddr0_dq[26] }] +set_load 10 [get_ports { ddr0_dq[25] }] +set_load 10 [get_ports { ddr0_dq[24] }] +set_load 10 [get_ports { ddr0_dq[23] }] +set_load 10 [get_ports { ddr0_dq[22] }] +set_load 10 [get_ports { ddr0_dq[21] }] +set_load 10 [get_ports { ddr0_dq[20] }] +set_load 10 [get_ports { ddr0_dq[19] }] +set_load 10 [get_ports { ddr0_dq[18] }] +set_load 10 [get_ports { ddr0_dq[17] }] +set_load 10 [get_ports { ddr0_dq[16] }] +set_load 10 [get_ports { ddr0_dq[15] }] +set_load 10 [get_ports { ddr0_dq[14] }] +set_load 10 [get_ports { ddr0_dq[13] }] +set_load 10 [get_ports { ddr0_dq[12] }] +set_load 10 [get_ports { ddr0_dq[11] }] +set_load 10 [get_ports { ddr0_dq[10] }] +set_load 10 [get_ports { ddr0_dq[9] }] +set_load 10 [get_ports { ddr0_dq[8] }] +set_load 10 [get_ports { ddr0_dq[7] }] +set_load 10 [get_ports { ddr0_dq[6] }] +set_load 10 [get_ports { ddr0_dq[5] }] +set_load 10 [get_ports { ddr0_dq[4] }] +set_load 10 [get_ports { ddr0_dq[3] }] +set_load 10 [get_ports { ddr0_dq[2] }] +set_load 10 [get_ports { ddr0_dq[1] }] +set_load 10 [get_ports { ddr0_dq[0] }] +set_load 10 [get_ports { ddr1_dq[31] }] +set_load 10 [get_ports { ddr1_dq[30] }] +set_load 10 [get_ports { ddr1_dq[29] }] +set_load 10 [get_ports { ddr1_dq[28] }] +set_load 10 [get_ports { ddr1_dq[27] }] +set_load 10 [get_ports { ddr1_dq[26] }] +set_load 10 [get_ports { ddr1_dq[25] }] +set_load 10 [get_ports { ddr1_dq[24] }] +set_load 10 [get_ports { ddr1_dq[23] }] +set_load 10 [get_ports { ddr1_dq[22] }] +set_load 10 [get_ports { ddr1_dq[21] }] +set_load 10 [get_ports { ddr1_dq[20] }] +set_load 10 [get_ports { ddr1_dq[19] }] +set_load 10 [get_ports { ddr1_dq[18] }] +set_load 10 [get_ports { ddr1_dq[17] }] +set_load 10 [get_ports { ddr1_dq[16] }] +set_load 10 [get_ports { ddr1_dq[15] }] +set_load 10 [get_ports { ddr1_dq[14] }] +set_load 10 [get_ports { ddr1_dq[13] }] +set_load 10 [get_ports { ddr1_dq[12] }] +set_load 10 [get_ports { ddr1_dq[11] }] +set_load 10 [get_ports { ddr1_dq[10] }] +set_load 10 [get_ports { ddr1_dq[9] }] +set_load 10 [get_ports { ddr1_dq[8] }] +set_load 10 [get_ports { ddr1_dq[7] }] +set_load 10 [get_ports { ddr1_dq[6] }] +set_load 10 [get_ports { ddr1_dq[5] }] +set_load 10 [get_ports { ddr1_dq[4] }] +set_load 10 [get_ports { ddr1_dq[3] }] +set_load 10 [get_ports { ddr1_dq[2] }] +set_load 10 [get_ports { ddr1_dq[1] }] +set_load 10 [get_ports { ddr1_dq[0] }] +set_load 10 [get_ports { ddr2_dq[31] }] +set_load 10 [get_ports { ddr2_dq[30] }] +set_load 10 [get_ports { ddr2_dq[29] }] +set_load 10 [get_ports { ddr2_dq[28] }] +set_load 10 [get_ports { ddr2_dq[27] }] +set_load 10 [get_ports { ddr2_dq[26] }] +set_load 10 [get_ports { ddr2_dq[25] }] +set_load 10 [get_ports { ddr2_dq[24] }] +set_load 10 [get_ports { ddr2_dq[23] }] +set_load 10 [get_ports { ddr2_dq[22] }] +set_load 10 [get_ports { ddr2_dq[21] }] +set_load 10 [get_ports { ddr2_dq[20] }] +set_load 10 [get_ports { ddr2_dq[19] }] +set_load 10 [get_ports { ddr2_dq[18] }] +set_load 10 [get_ports { ddr2_dq[17] }] +set_load 10 [get_ports { ddr2_dq[16] }] +set_load 10 [get_ports { ddr2_dq[15] }] +set_load 10 [get_ports { ddr2_dq[14] }] +set_load 10 [get_ports { ddr2_dq[13] }] +set_load 10 [get_ports { ddr2_dq[12] }] +set_load 10 [get_ports { ddr2_dq[11] }] +set_load 10 [get_ports { ddr2_dq[10] }] +set_load 10 [get_ports { ddr2_dq[9] }] +set_load 10 [get_ports { ddr2_dq[8] }] +set_load 10 [get_ports { ddr2_dq[7] }] +set_load 10 [get_ports { ddr2_dq[6] }] +set_load 10 [get_ports { ddr2_dq[5] }] +set_load 10 [get_ports { ddr2_dq[4] }] +set_load 10 [get_ports { ddr2_dq[3] }] +set_load 10 [get_ports { ddr2_dq[2] }] +set_load 10 [get_ports { ddr2_dq[1] }] +set_load 10 [get_ports { ddr2_dq[0] }] +set_load 10 [get_ports { ddr3_dq[31] }] +set_load 10 [get_ports { ddr3_dq[30] }] +set_load 10 [get_ports { ddr3_dq[29] }] +set_load 10 [get_ports { ddr3_dq[28] }] +set_load 10 [get_ports { ddr3_dq[27] }] +set_load 10 [get_ports { ddr3_dq[26] }] +set_load 10 [get_ports { ddr3_dq[25] }] +set_load 10 [get_ports { ddr3_dq[24] }] +set_load 10 [get_ports { ddr3_dq[23] }] +set_load 10 [get_ports { ddr3_dq[22] }] +set_load 10 [get_ports { ddr3_dq[21] }] +set_load 10 [get_ports { ddr3_dq[20] }] +set_load 10 [get_ports { ddr3_dq[19] }] +set_load 10 [get_ports { ddr3_dq[18] }] +set_load 10 [get_ports { ddr3_dq[17] }] +set_load 10 [get_ports { ddr3_dq[16] }] +set_load 10 [get_ports { ddr3_dq[15] }] +set_load 10 [get_ports { ddr3_dq[14] }] +set_load 10 [get_ports { ddr3_dq[13] }] +set_load 10 [get_ports { ddr3_dq[12] }] +set_load 10 [get_ports { ddr3_dq[11] }] +set_load 10 [get_ports { ddr3_dq[10] }] +set_load 10 [get_ports { ddr3_dq[9] }] +set_load 10 [get_ports { ddr3_dq[8] }] +set_load 10 [get_ports { ddr3_dq[7] }] +set_load 10 [get_ports { ddr3_dq[6] }] +set_load 10 [get_ports { ddr3_dq[5] }] +set_load 10 [get_ports { ddr3_dq[4] }] +set_load 10 [get_ports { ddr3_dq[3] }] +set_load 10 [get_ports { ddr3_dq[2] }] +set_load 10 [get_ports { ddr3_dq[1] }] +set_load 10 [get_ports { ddr3_dq[0] }] +set_load 10 [get_ports usb_plus] +set_load 10 [get_ports usb_minus] +set_input_transition 0.1 [get_ports { ddr0_dq[31] }] +set_input_transition 0.1 [get_ports { ddr0_dq[30] }] +set_input_transition 0.1 [get_ports { ddr0_dq[29] }] +set_input_transition 0.1 [get_ports { ddr0_dq[28] }] +set_input_transition 0.1 [get_ports { ddr0_dq[27] }] +set_input_transition 0.1 [get_ports { ddr0_dq[26] }] +set_input_transition 0.1 [get_ports { ddr0_dq[25] }] +set_input_transition 0.1 [get_ports { ddr0_dq[24] }] +set_input_transition 0.1 [get_ports { ddr0_dq[23] }] +set_input_transition 0.1 [get_ports { ddr0_dq[22] }] +set_input_transition 0.1 [get_ports { ddr0_dq[21] }] +set_input_transition 0.1 [get_ports { ddr0_dq[20] }] +set_input_transition 0.1 [get_ports { ddr0_dq[19] }] +set_input_transition 0.1 [get_ports { ddr0_dq[18] }] +set_input_transition 0.1 [get_ports { ddr0_dq[17] }] +set_input_transition 0.1 [get_ports { ddr0_dq[16] }] +set_input_transition 0.1 [get_ports { ddr0_dq[15] }] +set_input_transition 0.1 [get_ports { ddr0_dq[14] }] +set_input_transition 0.1 [get_ports { ddr0_dq[13] }] +set_input_transition 0.1 [get_ports { ddr0_dq[12] }] +set_input_transition 0.1 [get_ports { ddr0_dq[11] }] +set_input_transition 0.1 [get_ports { ddr0_dq[10] }] +set_input_transition 0.1 [get_ports { ddr0_dq[9] }] +set_input_transition 0.1 [get_ports { ddr0_dq[8] }] +set_input_transition 0.1 [get_ports { ddr0_dq[7] }] +set_input_transition 0.1 [get_ports { ddr0_dq[6] }] +set_input_transition 0.1 [get_ports { ddr0_dq[5] }] +set_input_transition 0.1 [get_ports { ddr0_dq[4] }] +set_input_transition 0.1 [get_ports { ddr0_dq[3] }] +set_input_transition 0.1 [get_ports { ddr0_dq[2] }] +set_input_transition 0.1 [get_ports { ddr0_dq[1] }] +set_input_transition 0.1 [get_ports { ddr0_dq[0] }] +set_input_transition 0.1 [get_ports { ddr1_dq[31] }] +set_input_transition 0.1 [get_ports { ddr1_dq[30] }] +set_input_transition 0.1 [get_ports { ddr1_dq[29] }] +set_input_transition 0.1 [get_ports { ddr1_dq[28] }] +set_input_transition 0.1 [get_ports { ddr1_dq[27] }] +set_input_transition 0.1 [get_ports { ddr1_dq[26] }] +set_input_transition 0.1 [get_ports { ddr1_dq[25] }] +set_input_transition 0.1 [get_ports { ddr1_dq[24] }] +set_input_transition 0.1 [get_ports { ddr1_dq[23] }] +set_input_transition 0.1 [get_ports { ddr1_dq[22] }] +set_input_transition 0.1 [get_ports { ddr1_dq[21] }] +set_input_transition 0.1 [get_ports { ddr1_dq[20] }] +set_input_transition 0.1 [get_ports { ddr1_dq[19] }] +set_input_transition 0.1 [get_ports { ddr1_dq[18] }] +set_input_transition 0.1 [get_ports { ddr1_dq[17] }] +set_input_transition 0.1 [get_ports { ddr1_dq[16] }] +set_input_transition 0.1 [get_ports { ddr1_dq[15] }] +set_input_transition 0.1 [get_ports { ddr1_dq[14] }] +set_input_transition 0.1 [get_ports { ddr1_dq[13] }] +set_input_transition 0.1 [get_ports { ddr1_dq[12] }] +set_input_transition 0.1 [get_ports { ddr1_dq[11] }] +set_input_transition 0.1 [get_ports { ddr1_dq[10] }] +set_input_transition 0.1 [get_ports { ddr1_dq[9] }] +set_input_transition 0.1 [get_ports { ddr1_dq[8] }] +set_input_transition 0.1 [get_ports { ddr1_dq[7] }] +set_input_transition 0.1 [get_ports { ddr1_dq[6] }] +set_input_transition 0.1 [get_ports { ddr1_dq[5] }] +set_input_transition 0.1 [get_ports { ddr1_dq[4] }] +set_input_transition 0.1 [get_ports { ddr1_dq[3] }] +set_input_transition 0.1 [get_ports { ddr1_dq[2] }] +set_input_transition 0.1 [get_ports { ddr1_dq[1] }] +set_input_transition 0.1 [get_ports { ddr1_dq[0] }] +set_input_transition 0.1 [get_ports { ddr2_dq[31] }] +set_input_transition 0.1 [get_ports { ddr2_dq[30] }] +set_input_transition 0.1 [get_ports { ddr2_dq[29] }] +set_input_transition 0.1 [get_ports { ddr2_dq[28] }] +set_input_transition 0.1 [get_ports { ddr2_dq[27] }] +set_input_transition 0.1 [get_ports { ddr2_dq[26] }] +set_input_transition 0.1 [get_ports { ddr2_dq[25] }] +set_input_transition 0.1 [get_ports { ddr2_dq[24] }] +set_input_transition 0.1 [get_ports { ddr2_dq[23] }] +set_input_transition 0.1 [get_ports { ddr2_dq[22] }] +set_input_transition 0.1 [get_ports { ddr2_dq[21] }] +set_input_transition 0.1 [get_ports { ddr2_dq[20] }] +set_input_transition 0.1 [get_ports { ddr2_dq[19] }] +set_input_transition 0.1 [get_ports { ddr2_dq[18] }] +set_input_transition 0.1 [get_ports { ddr2_dq[17] }] +set_input_transition 0.1 [get_ports { ddr2_dq[16] }] +set_input_transition 0.1 [get_ports { ddr2_dq[15] }] +set_input_transition 0.1 [get_ports { ddr2_dq[14] }] +set_input_transition 0.1 [get_ports { ddr2_dq[13] }] +set_input_transition 0.1 [get_ports { ddr2_dq[12] }] +set_input_transition 0.1 [get_ports { ddr2_dq[11] }] +set_input_transition 0.1 [get_ports { ddr2_dq[10] }] +set_input_transition 0.1 [get_ports { ddr2_dq[9] }] +set_input_transition 0.1 [get_ports { ddr2_dq[8] }] +set_input_transition 0.1 [get_ports { ddr2_dq[7] }] +set_input_transition 0.1 [get_ports { ddr2_dq[6] }] +set_input_transition 0.1 [get_ports { ddr2_dq[5] }] +set_input_transition 0.1 [get_ports { ddr2_dq[4] }] +set_input_transition 0.1 [get_ports { ddr2_dq[3] }] +set_input_transition 0.1 [get_ports { ddr2_dq[2] }] +set_input_transition 0.1 [get_ports { ddr2_dq[1] }] +set_input_transition 0.1 [get_ports { ddr2_dq[0] }] +set_input_transition 0.1 [get_ports { ddr3_dq[31] }] +set_input_transition 0.1 [get_ports { ddr3_dq[30] }] +set_input_transition 0.1 [get_ports { ddr3_dq[29] }] +set_input_transition 0.1 [get_ports { ddr3_dq[28] }] +set_input_transition 0.1 [get_ports { ddr3_dq[27] }] +set_input_transition 0.1 [get_ports { ddr3_dq[26] }] +set_input_transition 0.1 [get_ports { ddr3_dq[25] }] +set_input_transition 0.1 [get_ports { ddr3_dq[24] }] +set_input_transition 0.1 [get_ports { ddr3_dq[23] }] +set_input_transition 0.1 [get_ports { ddr3_dq[22] }] +set_input_transition 0.1 [get_ports { ddr3_dq[21] }] +set_input_transition 0.1 [get_ports { ddr3_dq[20] }] +set_input_transition 0.1 [get_ports { ddr3_dq[19] }] +set_input_transition 0.1 [get_ports { ddr3_dq[18] }] +set_input_transition 0.1 [get_ports { ddr3_dq[17] }] +set_input_transition 0.1 [get_ports { ddr3_dq[16] }] +set_input_transition 0.1 [get_ports { ddr3_dq[15] }] +set_input_transition 0.1 [get_ports { ddr3_dq[14] }] +set_input_transition 0.1 [get_ports { ddr3_dq[13] }] +set_input_transition 0.1 [get_ports { ddr3_dq[12] }] +set_input_transition 0.1 [get_ports { ddr3_dq[11] }] +set_input_transition 0.1 [get_ports { ddr3_dq[10] }] +set_input_transition 0.1 [get_ports { ddr3_dq[9] }] +set_input_transition 0.1 [get_ports { ddr3_dq[8] }] +set_input_transition 0.1 [get_ports { ddr3_dq[7] }] +set_input_transition 0.1 [get_ports { ddr3_dq[6] }] +set_input_transition 0.1 [get_ports { ddr3_dq[5] }] +set_input_transition 0.1 [get_ports { ddr3_dq[4] }] +set_input_transition 0.1 [get_ports { ddr3_dq[3] }] +set_input_transition 0.1 [get_ports { ddr3_dq[2] }] +set_input_transition 0.1 [get_ports { ddr3_dq[1] }] +set_input_transition 0.1 [get_ports { ddr3_dq[0] }] +set_input_transition 0.1 [get_ports usb_plus] +set_input_transition 0.1 [get_ports usb_minus] +set_input_transition 0.1 [get_ports reset_n] +set_input_transition 0.1 [get_ports { BS_data_0[15] }] +set_input_transition 0.1 [get_ports { BS_data_0[14] }] +set_input_transition 0.1 [get_ports { BS_data_0[13] }] +set_input_transition 0.1 [get_ports { BS_data_0[12] }] +set_input_transition 0.1 [get_ports { BS_data_0[11] }] +set_input_transition 0.1 [get_ports { BS_data_0[10] }] +set_input_transition 0.1 [get_ports { BS_data_0[9] }] +set_input_transition 0.1 [get_ports { BS_data_0[8] }] +set_input_transition 0.1 [get_ports { BS_data_0[7] }] +set_input_transition 0.1 [get_ports { BS_data_0[6] }] +set_input_transition 0.1 [get_ports { BS_data_0[5] }] +set_input_transition 0.1 [get_ports { BS_data_0[4] }] +set_input_transition 0.1 [get_ports { BS_data_0[3] }] +set_input_transition 0.1 [get_ports { BS_data_0[2] }] +set_input_transition 0.1 [get_ports { BS_data_0[1] }] +set_input_transition 0.1 [get_ports { BS_data_0[0] }] +set_input_transition 0.1 [get_ports { BS_data_1[15] }] +set_input_transition 0.1 [get_ports { BS_data_1[14] }] +set_input_transition 0.1 [get_ports { BS_data_1[13] }] +set_input_transition 0.1 [get_ports { BS_data_1[12] }] +set_input_transition 0.1 [get_ports { BS_data_1[11] }] +set_input_transition 0.1 [get_ports { BS_data_1[10] }] +set_input_transition 0.1 [get_ports { BS_data_1[9] }] +set_input_transition 0.1 [get_ports { BS_data_1[8] }] +set_input_transition 0.1 [get_ports { BS_data_1[7] }] +set_input_transition 0.1 [get_ports { BS_data_1[6] }] +set_input_transition 0.1 [get_ports { BS_data_1[5] }] +set_input_transition 0.1 [get_ports { BS_data_1[4] }] +set_input_transition 0.1 [get_ports { BS_data_1[3] }] +set_input_transition 0.1 [get_ports { BS_data_1[2] }] +set_input_transition 0.1 [get_ports { BS_data_1[1] }] +set_input_transition 0.1 [get_ports { BS_data_1[0] }] +set_input_transition 0.1 [get_ports lfxt_clk] +set_input_transition 0.1 [get_ports nmi] +set_input_transition 0.1 [get_ports scan_mode] +set_input_transition 0.1 [get_ports sysclk_byp] +set_input_transition 0.1 [get_ports usbclk_byp] +set_case_analysis 0 [get_ports scan_mode] +set_input_delay 0.7 [get_ports usb_minus] +set_input_delay 0.7 [get_ports usb_plus] +set_clock_groups -name CLOCK_GROUP__0 -asynchronous -group [get_clocks lfxt_clk] -group [get_clocks sysclk] -group [get_clocks usbclk] + + + diff --git a/constraints/define_regions.def b/constraints/define_regions.def new file mode 100755 index 0000000..48d4c24 --- /dev/null +++ b/constraints/define_regions.def @@ -0,0 +1,29 @@ +# +# Created by Oasys-RTL -- (c) Mentor Graphics Corporation +# +VERSION 5.8 ; +NAMESCASESENSITIVE ON ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN demo_chip ; +UNITS DISTANCE MICRONS 2000 ; + +PROPERTYDEFINITIONS +END PROPERTYDEFINITIONS + +DIEAREA ( 0 0 ) ( 2834850 2834850 ) ; + +REGIONS 2 ; +- __r__6 ( 64840 50430 ) ( 1549550 1203580 ) ; +- __r__7 ( 1254060 1513530 ) ( 2803620 2767590 ) ; +END REGIONS +COMPONENTS 352 ; +- i_cpu_sys cpu_sys ++ REGION __r__6 + ; +- i_usbf usb_sys ++ REGION __r__7 + ; +END COMPONENTS + +END DESIGN diff --git a/constraints/demo_chip_func.sdc b/constraints/demo_chip_func.sdc new file mode 100755 index 0000000..cffbacd --- /dev/null +++ b/constraints/demo_chip_func.sdc @@ -0,0 +1,89 @@ +###################################################################### +# Design : demo_chip +# SDC timing constraint file +###################################################################### +set clock_period 100.0 +set sysclk_multiplier 40 +set usbclk_multiplier 6 +set clock_margin 0.20 +set pad_load 10 +set transition 0.1 +set io_clock_period [ expr ${clock_period} / ${sysclk_multiplier} ] +set io_clock_period_ddr [ expr ${io_clock_period} / 2 ] + +# ------------------------------------------------------------------ +# Clock definitions +# ------------------------------------------------------------------ +# PLL input clock 10MHz +create_clock -name lfxt_clk -period ${clock_period} [ get_ports lfxt_clk ] + +# Main system clock - 400MHz +create_generated_clock \ + -name sysclk \ + -source [ get_pins i_MAIN_PLL/REF ] \ + -multiply_by ${sysclk_multiplier} \ + -add -master_clock lfxt_clk \ + [ get_pins i_MAIN_PLL/PLLOUT ] + +# USB clock - 60MHz +create_generated_clock \ + -name usbclk \ + -source [ get_pins i_USB_PLL/REF ] \ + -multiply_by ${usbclk_multiplier} \ + -add -master_clock lfxt_clk \ + [ get_pins i_USB_PLL/PLLOUT ] + +# Scan mode clocks +create_clock -name sysclk_byp -period ${clock_period} [ get_ports sysclk_byp ] +create_clock -name usbclk_byp -period ${clock_period} [ get_ports usbclk_byp ] + +# Virtual clocks for I/O and DDR timing +create_clock -name vsysclk -period ${io_clock_period} +create_clock -name vsysclk_ddr -period ${io_clock_period_ddr} + +# Apply uncertainties to clocks +set_clock_uncertainty -setup ${clock_margin} [ get_clocks sysclk ] +set_clock_uncertainty -setup ${clock_margin} [ get_clocks usbclk ] + +# ------------------------------------------------------------------ +# port timings +# ------------------------------------------------------------------ +set_input_delay 0.4 [get_ports usb_minus] +set_input_delay 0.4 [get_ports usb_plus] +set_input_delay -clock vsysclk [ expr 0.4 *${io_clock_period} ] \ + [ remove_from_collection [ all_inputs ] [ get_ports { lfxt_clk usb_plus usb_minus ddr*dq }] ] +set_output_delay -clock vsysclk [ expr 0.3 * ${io_clock_period} ] \ + [ remove_from_collection [ all_outputs ] [ get_ports { usb_plus usb_minus }] ] + +# DDR input timings +set_input_delay -clock vsysclk_ddr [ expr 0.4 * ${io_clock_period_ddr} ] \ + [ get_ports { ddr*dq* }] + +# ------------------------------------------------------------------ +# external conditions +# ------------------------------------------------------------------ +set_load ${pad_load} [ all_outputs ] +set_input_transition ${transition} [ all_inputs ] + +# ------------------------------------------------------------------ +# Exceptions +# ------------------------------------------------------------------ +# NMI and reset are asynchronous +set_false_path -from [ get_ports nmi ] +set_false_path -from [ get_ports reset_n ] + +# Power up/down will take long time --> set false paths +set_false_path -through [ get_pins {nova0/power_control nova0/power_ack nova1/power_control nova1/power_ack i_usbf/*power_control i_usbf/*power_ack }] + +# All clock domain crossings are async +set_clock_groups -asynchronous \ + -group lfxt_clk \ + -group sysclk \ + -group usbclk + +# Block scan clocks with case analysis +set_case_analysis 0 [get_ports scan_mode] +set_false_path -from SCAN_ENABLE + +set_input_delay 0.7 [get_ports usb_minus] +set_input_delay 0.7 [get_ports usb_plus] diff --git a/constraints/riscv.sdc b/constraints/riscv.sdc new file mode 100644 index 0000000..f1f17c2 --- /dev/null +++ b/constraints/riscv.sdc @@ -0,0 +1,76 @@ +# ============================================================================= +# Constraints File: cpu.sdc +# Project: BCDC Microtec Academy - RISC-V CPU +# Top Module: cpu +# ============================================================================= + +# ----------------------------------------------------------------------------- +# 1. Primary Clock - 25 MHz input clock +# ----------------------------------------------------------------------------- +create_clock -name clk_25mhz \ + -period 40.000 \ + -waveform {0 20} \ + [get_ports clk_25mhz] + +# ----------------------------------------------------------------------------- +# 2. Generated Clock - 12.5 MHz (divided by 2 inside always_ff) +# ----------------------------------------------------------------------------- +#create_generated_clock -name clk_12p5 \ +# -source [get_ports clk_25mhz] \ + # -divide_by 2 \ + # [get_pins thePC/clk] + +# ----------------------------------------------------------------------------- +# 3. Clock Uncertainty & Transition +# ----------------------------------------------------------------------------- +set_clock_uncertainty -setup 0.5 [get_clocks clk_25mhz] +set_clock_uncertainty -hold 0.2 [get_clocks clk_25mhz] + +set_clock_transition 0.1 [get_clocks clk_25mhz] + +# ----------------------------------------------------------------------------- +# 4. Input Delays (btn pins - relative to clk_25mhz) +# ----------------------------------------------------------------------------- +set_input_delay -clock clk_25mhz -max 2.0 [get_ports {btn[*]}] +set_input_delay -clock clk_25mhz -min 0.5 [get_ports {btn[*]}] + +# ----------------------------------------------------------------------------- +# 5. Output Delays (led pins) +# ----------------------------------------------------------------------------- +set_output_delay -clock clk_25mhz -max 2.0 [get_ports {led[*]}] +set_output_delay -clock clk_25mhz -min 0.5 [get_ports {led[*]}] + +# ----------------------------------------------------------------------------- +# 6. False Paths +# ----------------------------------------------------------------------------- +# Reset is async and driven from a button - no timing analysis needed +set_false_path -from [get_ports {btn[0]}] + +# LED outputs driven from combinational/slow logic - relax if needed +# set_false_path -to [get_ports {led[*]}] + +# ----------------------------------------------------------------------------- +# 7. Clock Domain Crossing +# ----------------------------------------------------------------------------- +# clk12p5 is derived from clk_25mhz via FF division - set as async crossing +# to prevent hold violations across the two domains +#set_clock_groups -asynchronous \ + -group [get_clocks clk_25mhz] \ + -group [get_clocks clk_12p5] + +# ----------------------------------------------------------------------------- +# 8. Drive Strength & Load (adjust to your target technology) +# ----------------------------------------------------------------------------- +#set_driving_cell -lib_cell [get_ports {btn[*]}] + +set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 [get_ports {btn[*]}] + +set_load 0.05 [get_ports {led[*]}] + +# ----------------------------------------------------------------------------- +# 9. Max Fanout & Transition +# ----------------------------------------------------------------------------- +set_max_fanout 20 [current_design] +set_max_transition 0.5 [current_design] + + diff --git a/cpu_patterns.stil b/cpu_patterns.stil new file mode 100644 index 0000000..eed3d82 --- /dev/null +++ b/cpu_patterns.stil @@ -0,0 +1,355 @@ +STIL 1.0; + +Header { +Title "cpu_cpu_patterns_stil" ; + Date "Thu May 28 18:01:24 2026" ; + Source "Tessent Shell 2023.4-p1" ; + History { + Ann {* Fault : STUCK *} + Ann {* Coverage : 25.96(TC) 24.58(FC) *} + Ann {* Begin_Verify_Section *} + Ann {* format = STIL *} + Ann {* serial_flag = OFF *} + Ann {* test_set_type = ALL_TEST *} + Ann {* pad_value = X *} + Ann {* pattern_begin = 0 *} + Ann {* pattern_end = 9 *} + Ann {* one_setup = ON *} + Ann {* no_initialization = ON *} + Ann {* pattern_checksum = 94986 *} + Ann {* End_Verify_Section *} + } +} + +Signals { + "btn"[6] In; "btn"[5] In; "btn"[4] In; "btn"[3] In; "btn"[2] In; "btn"[1] In; "btn"[0] In; "clk_25mhz" In; "scan_en" In; "SI_1" In; "SI_2" In; "SI_3" In; "SI_4" In; + "led"[7] Out; "led"[6] Out; "led"[5] Out; "led"[4] Out; "led"[3] Out; "led"[2] Out; "led"[1] Out; "led"[0] Out; "SO_1" Out; "SO_2" Out; "SO_3" Out; "SO_4" Out; +} + +SignalGroups { + _pi_ = '"btn"[6] + "btn"[5] + "btn"[4] + "btn"[3] + "btn"[2] + "btn"[1] + "btn"[0] + "clk_25mhz" + "scan_en" + "SI_1" + "SI_2" + "SI_3" + "SI_4"'; + _po_ = '"led"[7] + "led"[6] + "led"[5] + "led"[4] + "led"[3] + "led"[2] + "led"[1] + "led"[0] + "SO_1" + "SO_2" + "SO_3" + "SO_4"'; + input_time_gen_0 = '"btn"[6] + "btn"[5] + "btn"[4] + "btn"[3] + "btn"[2] + "btn"[1] + "btn"[0] + "scan_en" + "SI_1" + "SI_2" + "SI_3" + "SI_4"'; + input_time_gen_1 = '"clk_25mhz"'; + "_unwrapped_chain1_SI_1_" = '"SI_1"' {ScanIn 256;} + "_unwrapped_chain1_SO_1_" = '"SO_1"' {ScanOut 256;} + "_unwrapped_chain2_SI_2_" = '"SI_2"' {ScanIn 256;} + "_unwrapped_chain2_SO_2_" = '"SO_2"' {ScanOut 256;} + "_unwrapped_chain3_SI_3_" = '"SI_3"' {ScanIn 256;} + "_unwrapped_chain3_SO_3_" = '"SO_3"' {ScanOut 256;} + "_unwrapped_chain4_SI_4_" = '"SI_4"' {ScanIn 256;} + "_unwrapped_chain4_SO_4_" = '"SO_4"' {ScanOut 256;} +} + +Timing STUCK_timing { + WaveformTable tset_gen_tp1 { + Period '40ns' ; + Waveforms { + input_time_gen_0 { 01NZ { '0ns' D/U/N/Z; }} + input_time_gen_1 { 01 { '0ns' D; '20ns' D/U; '30ns' D;}} + _po_ { LHXT { '10ns' L/H/X/T;}} + } + } +} + +ScanStructures { + ScanChain unwrapped_chain1 { + ScanLength 256; + ScanInversion 0; + ScanCells "\thePC_CurrentPC_reg[30] " "\thePC_CurrentPC_reg[29] " "\thePC_CurrentPC_reg[28] " "\thePC_CurrentPC_reg[27] " "\thePC_CurrentPC_reg[26] " "\thePC_CurrentPC_reg[25] " "\thePC_CurrentPC_reg[24] " "\thePC_CurrentPC_reg[23] " "\thePC_CurrentPC_reg[22] " "\thePC_CurrentPC_reg[21] " "\thePC_CurrentPC_reg[20] " "\thePC_CurrentPC_reg[19] " "\thePC_CurrentPC_reg[18] " "\thePC_CurrentPC_reg[17] " "\thePC_CurrentPC_reg[16] " "\thePC_CurrentPC_reg[15] " "\thePC_CurrentPC_reg[14] " "\thePC_CurrentPC_reg[13] " "\thePC_CurrentPC_reg[12] " "\thePC_CurrentPC_reg[11] " "\thePC_CurrentPC_reg[10] " "\thePC_CurrentPC_reg[9] " "\thePC_CurrentPC_reg[8] " "\thePC_CurrentPC_reg[7] " "\thePC_CurrentPC_reg[6] " "\thePC_CurrentPC_reg[5] " "\thePC_CurrentPC_reg[4] " "\thePC_CurrentPC_reg[3] " "\thePC_CurrentPC_reg[2] " "\thePC_CurrentPC_reg[31] " "\thePC_CurrentPC_reg[1] " "\thePC_CurrentPC_reg[0] " "theRegisters.\registers_reg[16][31] " "theRegisters.\registers_reg[10][31] " "theRegisters.\registers_reg[12][31] " + "theRegisters.\registers_reg[11][31] " "theRegisters.\registers_reg[13][31] " "theRegisters.\registers_reg[15][31] " "theRegisters.\registers_reg[14][31] " "theRegisters.\registers_reg[16][30] " "theRegisters.\registers_reg[10][30] " "theRegisters.\registers_reg[12][30] " "theRegisters.\registers_reg[11][30] " "theRegisters.\registers_reg[13][30] " "theRegisters.\registers_reg[15][30] " "theRegisters.\registers_reg[14][30] " "theRegisters.\registers_reg[10][29] " "theRegisters.\registers_reg[13][29] " "theRegisters.\registers_reg[12][29] " "theRegisters.\registers_reg[15][29] " "theRegisters.\registers_reg[16][29] " "theRegisters.\registers_reg[14][29] " "theRegisters.\registers_reg[11][29] " "theRegisters.\registers_reg[15][28] " "theRegisters.\registers_reg[12][28] " "theRegisters.\registers_reg[14][28] " "theRegisters.\registers_reg[13][28] " "theRegisters.\registers_reg[10][28] " "theRegisters.\registers_reg[16][28] " "theRegisters.\registers_reg[11][28] " "theRegisters.\registers_reg[11][27] " + "theRegisters.\registers_reg[16][27] " "theRegisters.\registers_reg[10][27] " "theRegisters.\registers_reg[12][27] " "theRegisters.\registers_reg[13][27] " "theRegisters.\registers_reg[15][27] " "theRegisters.\registers_reg[14][27] " "theRegisters.\registers_reg[11][26] " "theRegisters.\registers_reg[16][26] " "theRegisters.\registers_reg[12][26] " "theRegisters.\registers_reg[13][26] " "theRegisters.\registers_reg[15][26] " "theRegisters.\registers_reg[14][26] " "theRegisters.\registers_reg[10][26] " "theRegisters.\registers_reg[12][25] " "theRegisters.\registers_reg[11][25] " "theRegisters.\registers_reg[10][25] " "theRegisters.\registers_reg[13][25] " "theRegisters.\registers_reg[15][25] " "theRegisters.\registers_reg[16][25] " "theRegisters.\registers_reg[14][25] " "theRegisters.\registers_reg[12][24] " "theRegisters.\registers_reg[11][24] " "theRegisters.\registers_reg[10][24] " "theRegisters.\registers_reg[13][24] " "theRegisters.\registers_reg[15][24] " "theRegisters.\registers_reg[16][24] " + "theRegisters.\registers_reg[14][24] " "theRegisters.\registers_reg[15][23] " "theRegisters.\registers_reg[14][23] " "theRegisters.\registers_reg[16][23] " "theRegisters.\registers_reg[11][23] " "theRegisters.\registers_reg[13][23] " "theRegisters.\registers_reg[12][23] " "theRegisters.\registers_reg[10][23] " "theRegisters.\registers_reg[11][22] " "theRegisters.\registers_reg[12][22] " "theRegisters.\registers_reg[10][22] " "theRegisters.\registers_reg[13][22] " "theRegisters.\registers_reg[15][22] " "theRegisters.\registers_reg[16][22] " "theRegisters.\registers_reg[14][22] " "theRegisters.\registers_reg[12][21] " "theRegisters.\registers_reg[11][21] " "theRegisters.\registers_reg[10][21] " "theRegisters.\registers_reg[13][21] " "theRegisters.\registers_reg[15][21] " "theRegisters.\registers_reg[16][21] " "theRegisters.\registers_reg[14][21] " "theRegisters.\registers_reg[10][20] " "theRegisters.\registers_reg[12][20] " "theRegisters.\registers_reg[15][20] " "theRegisters.\registers_reg[11][20] " + "theRegisters.\registers_reg[13][20] " "theRegisters.\registers_reg[16][20] " "theRegisters.\registers_reg[14][20] " "theRegisters.\registers_reg[12][19] " "theRegisters.\registers_reg[15][19] " "theRegisters.\registers_reg[11][19] " "theRegisters.\registers_reg[13][19] " "theRegisters.\registers_reg[16][19] " "theRegisters.\registers_reg[14][19] " "theRegisters.\registers_reg[10][19] " "theRegisters.\registers_reg[11][18] " "theRegisters.\registers_reg[16][18] " "theRegisters.\registers_reg[12][18] " "theRegisters.\registers_reg[13][18] " "theRegisters.\registers_reg[15][18] " "theRegisters.\registers_reg[14][18] " "theRegisters.\registers_reg[10][18] " "theRegisters.\registers_reg[12][17] " "theRegisters.\registers_reg[15][17] " "theRegisters.\registers_reg[11][17] " "theRegisters.\registers_reg[10][17] " "theRegisters.\registers_reg[13][17] " "theRegisters.\registers_reg[16][17] " "theRegisters.\registers_reg[14][17] " "theRegisters.\registers_reg[11][16] " "theRegisters.\registers_reg[10][16] " + "theRegisters.\registers_reg[16][16] " "theRegisters.\registers_reg[12][16] " "theRegisters.\registers_reg[13][16] " "theRegisters.\registers_reg[15][16] " "theRegisters.\registers_reg[14][16] " "theRegisters.\registers_reg[10][15] " "theRegisters.\registers_reg[12][15] " "theRegisters.\registers_reg[15][15] " "theRegisters.\registers_reg[11][15] " "theRegisters.\registers_reg[13][15] " "theRegisters.\registers_reg[16][15] " "theRegisters.\registers_reg[14][15] " "theRegisters.\registers_reg[10][14] " "theRegisters.\registers_reg[14][14] " "theRegisters.\registers_reg[16][14] " "theRegisters.\registers_reg[15][14] " "theRegisters.\registers_reg[12][14] " "theRegisters.\registers_reg[13][14] " "theRegisters.\registers_reg[11][14] " "theRegisters.\registers_reg[10][13] " "theRegisters.\registers_reg[16][13] " "theRegisters.\registers_reg[15][13] " "theRegisters.\registers_reg[12][13] " "theRegisters.\registers_reg[13][13] " "theRegisters.\registers_reg[14][13] " "theRegisters.\registers_reg[11][13] " + "theRegisters.\registers_reg[10][12] " "theRegisters.\registers_reg[16][12] " "theRegisters.\registers_reg[15][12] " "theRegisters.\registers_reg[12][12] " "theRegisters.\registers_reg[13][12] " "theRegisters.\registers_reg[14][12] " "theRegisters.\registers_reg[11][12] " "theRegisters.\registers_reg[10][11] " "theRegisters.\registers_reg[16][11] " "theRegisters.\registers_reg[15][11] " "theRegisters.\registers_reg[12][11] " "theRegisters.\registers_reg[13][11] " "theRegisters.\registers_reg[14][11] " "theRegisters.\registers_reg[11][11] " "theRegisters.\registers_reg[10][10] " "theRegisters.\registers_reg[13][10] " "theRegisters.\registers_reg[12][10] " "theRegisters.\registers_reg[15][10] " "theRegisters.\registers_reg[16][10] " "theRegisters.\registers_reg[14][10] " "theRegisters.\registers_reg[11][10] " "theRegisters.\registers_reg[13][9] " "theRegisters.\registers_reg[10][9] " "theRegisters.\registers_reg[12][9] " "theRegisters.\registers_reg[15][9] " "theRegisters.\registers_reg[16][9] " + "theRegisters.\registers_reg[14][9] " "theRegisters.\registers_reg[11][9] " "theRegisters.\registers_reg[13][8] " "theRegisters.\registers_reg[10][8] " "theRegisters.\registers_reg[12][8] " "theRegisters.\registers_reg[15][8] " "theRegisters.\registers_reg[16][8] " "theRegisters.\registers_reg[14][8] " "theRegisters.\registers_reg[11][8] " "theRegisters.\registers_reg[13][7] " "theRegisters.\registers_reg[10][7] " "theRegisters.\registers_reg[11][7] " "theRegisters.\registers_reg[12][7] " "theRegisters.\registers_reg[15][7] " "theRegisters.\registers_reg[16][7] " "theRegisters.\registers_reg[14][7] " "theRegisters.\registers_reg[10][6] " "theRegisters.\registers_reg[15][6] " "theRegisters.\registers_reg[11][6] " "theRegisters.\registers_reg[16][6] " "theRegisters.\registers_reg[12][6] " "theRegisters.\registers_reg[13][6] " "theRegisters.\registers_reg[14][6] " "theRegisters.\registers_reg[10][5] " "theRegisters.\registers_reg[16][5] " "theRegisters.\registers_reg[15][5] " "theRegisters.\registers_reg[12][5] " + "theRegisters.\registers_reg[13][5] " "theRegisters.\registers_reg[14][5] " "theRegisters.\registers_reg[11][5] " "theRegisters.\registers_reg[10][4] " "theRegisters.\registers_reg[13][4] " "theRegisters.\registers_reg[12][4] " "theRegisters.\registers_reg[11][4] " "theRegisters.\registers_reg[14][4] " "theRegisters.\registers_reg[15][4] " "theRegisters.\registers_reg[16][4] " "theRegisters.\registers_reg[10][3] " "theRegisters.\registers_reg[16][3] " "theRegisters.\registers_reg[15][3] " "theRegisters.\registers_reg[12][3] " "theRegisters.\registers_reg[13][3] " "theRegisters.\registers_reg[14][3] " "theRegisters.\registers_reg[11][3] " "theRegisters.\registers_reg[16][2] " "theRegisters.\registers_reg[15][2] " "theRegisters.\registers_reg[11][2] " "theRegisters.\registers_reg[10][2] " "theRegisters.\registers_reg[12][2] " "theRegisters.\registers_reg[13][2] " "theRegisters.\registers_reg[14][2] " "theRegisters.\registers_reg[13][1] " "theRegisters.\registers_reg[10][1] " "theRegisters.\registers_reg[12][1] " + "theRegisters.\registers_reg[15][1] " "theRegisters.\registers_reg[16][1] " "theRegisters.\registers_reg[14][1] " "theRegisters.\registers_reg[11][1] " "theRegisters.\registers_reg[13][0] " "theRegisters.\registers_reg[10][0] " "theRegisters.\registers_reg[12][0] " "theRegisters.\registers_reg[15][0] " "theRegisters.\registers_reg[16][0] " "theRegisters.\registers_reg[14][0] " "theRegisters.\registers_reg[11][0] " ; + ScanIn "SI_1"; + ScanOut "SO_1"; + ScanMasterClock "clk_25mhz"; + } + ScanChain unwrapped_chain2 { + ScanLength 256; + ScanInversion 0; + ScanCells "theRegisters.\registers_reg[1][31] " "theRegisters.\registers_reg[23][31] " "theRegisters.\registers_reg[19][31] " "theRegisters.\registers_reg[18][31] " "theRegisters.\registers_reg[22][31] " "theRegisters.\registers_reg[21][31] " "theRegisters.\registers_reg[17][31] " "theRegisters.\registers_reg[20][31] " "theRegisters.\registers_reg[17][30] " "theRegisters.\registers_reg[1][30] " "theRegisters.\registers_reg[23][30] " "theRegisters.\registers_reg[19][30] " "theRegisters.\registers_reg[18][30] " "theRegisters.\registers_reg[20][30] " "theRegisters.\registers_reg[22][30] " "theRegisters.\registers_reg[21][30] " "theRegisters.\registers_reg[20][29] " "theRegisters.\registers_reg[19][29] " "theRegisters.\registers_reg[23][29] " "theRegisters.\registers_reg[21][29] " "theRegisters.\registers_reg[18][29] " "theRegisters.\registers_reg[17][29] " "theRegisters.\registers_reg[22][29] " "theRegisters.\registers_reg[1][29] " "theRegisters.\registers_reg[22][28] " "theRegisters.\registers_reg[17][28] " + "theRegisters.\registers_reg[20][28] " "theRegisters.\registers_reg[1][28] " "theRegisters.\registers_reg[23][28] " "theRegisters.\registers_reg[21][28] " "theRegisters.\registers_reg[19][28] " "theRegisters.\registers_reg[18][28] " "theRegisters.\registers_reg[1][27] " "theRegisters.\registers_reg[22][27] " "theRegisters.\registers_reg[19][27] " "theRegisters.\registers_reg[21][27] " "theRegisters.\registers_reg[20][27] " "theRegisters.\registers_reg[18][27] " "theRegisters.\registers_reg[23][27] " "theRegisters.\registers_reg[17][27] " "theRegisters.\registers_reg[18][26] " "theRegisters.\registers_reg[22][26] " "theRegisters.\registers_reg[1][26] " "theRegisters.\registers_reg[19][26] " "theRegisters.\registers_reg[21][26] " "theRegisters.\registers_reg[20][26] " "theRegisters.\registers_reg[23][26] " "theRegisters.\registers_reg[17][26] " "theRegisters.\registers_reg[17][25] " "theRegisters.\registers_reg[21][25] " "theRegisters.\registers_reg[20][25] " "theRegisters.\registers_reg[22][25] " + "theRegisters.\registers_reg[1][25] " "theRegisters.\registers_reg[18][25] " "theRegisters.\registers_reg[19][25] " "theRegisters.\registers_reg[23][25] " "theRegisters.\registers_reg[17][24] " "theRegisters.\registers_reg[21][24] " "theRegisters.\registers_reg[20][24] " "theRegisters.\registers_reg[22][24] " "theRegisters.\registers_reg[1][24] " "theRegisters.\registers_reg[18][24] " "theRegisters.\registers_reg[19][24] " "theRegisters.\registers_reg[23][24] " "theRegisters.\registers_reg[18][23] " "theRegisters.\registers_reg[22][23] " "theRegisters.\registers_reg[1][23] " "theRegisters.\registers_reg[21][23] " "theRegisters.\registers_reg[20][23] " "theRegisters.\registers_reg[19][23] " "theRegisters.\registers_reg[23][23] " "theRegisters.\registers_reg[17][23] " "theRegisters.\registers_reg[17][22] " "theRegisters.\registers_reg[21][22] " "theRegisters.\registers_reg[20][22] " "theRegisters.\registers_reg[22][22] " "theRegisters.\registers_reg[1][22] " "theRegisters.\registers_reg[18][22] " + "theRegisters.\registers_reg[19][22] " "theRegisters.\registers_reg[23][22] " "theRegisters.\registers_reg[17][21] " "theRegisters.\registers_reg[21][21] " "theRegisters.\registers_reg[20][21] " "theRegisters.\registers_reg[22][21] " "theRegisters.\registers_reg[1][21] " "theRegisters.\registers_reg[18][21] " "theRegisters.\registers_reg[19][21] " "theRegisters.\registers_reg[23][21] " "theRegisters.\registers_reg[17][20] " "theRegisters.\registers_reg[21][20] " "theRegisters.\registers_reg[20][20] " "theRegisters.\registers_reg[22][20] " "theRegisters.\registers_reg[1][20] " "theRegisters.\registers_reg[18][20] " "theRegisters.\registers_reg[19][20] " "theRegisters.\registers_reg[23][20] " "theRegisters.\registers_reg[17][19] " "theRegisters.\registers_reg[21][19] " "theRegisters.\registers_reg[20][19] " "theRegisters.\registers_reg[22][19] " "theRegisters.\registers_reg[1][19] " "theRegisters.\registers_reg[18][19] " "theRegisters.\registers_reg[19][19] " "theRegisters.\registers_reg[23][19] " + "theRegisters.\registers_reg[22][18] " "theRegisters.\registers_reg[1][18] " "theRegisters.\registers_reg[18][18] " "theRegisters.\registers_reg[19][18] " "theRegisters.\registers_reg[21][18] " "theRegisters.\registers_reg[20][18] " "theRegisters.\registers_reg[23][18] " "theRegisters.\registers_reg[17][18] " "theRegisters.\registers_reg[17][17] " "theRegisters.\registers_reg[21][17] " "theRegisters.\registers_reg[20][17] " "theRegisters.\registers_reg[22][17] " "theRegisters.\registers_reg[1][17] " "theRegisters.\registers_reg[18][17] " "theRegisters.\registers_reg[19][17] " "theRegisters.\registers_reg[23][17] " "theRegisters.\registers_reg[18][16] " "theRegisters.\registers_reg[22][16] " "theRegisters.\registers_reg[1][16] " "theRegisters.\registers_reg[19][16] " "theRegisters.\registers_reg[21][16] " "theRegisters.\registers_reg[20][16] " "theRegisters.\registers_reg[23][16] " "theRegisters.\registers_reg[17][16] " "theRegisters.\registers_reg[17][15] " "theRegisters.\registers_reg[21][15] " + "theRegisters.\registers_reg[20][15] " "theRegisters.\registers_reg[22][15] " "theRegisters.\registers_reg[1][15] " "theRegisters.\registers_reg[18][15] " "theRegisters.\registers_reg[19][15] " "theRegisters.\registers_reg[23][15] " "theRegisters.\registers_reg[18][14] " "theRegisters.\registers_reg[21][14] " "theRegisters.\registers_reg[17][14] " "theRegisters.\registers_reg[23][14] " "theRegisters.\registers_reg[20][14] " "theRegisters.\registers_reg[1][14] " "theRegisters.\registers_reg[19][14] " "theRegisters.\registers_reg[22][14] " "theRegisters.\registers_reg[1][13] " "theRegisters.\registers_reg[23][13] " "theRegisters.\registers_reg[18][13] " "theRegisters.\registers_reg[22][13] " "theRegisters.\registers_reg[21][13] " "theRegisters.\registers_reg[20][13] " "theRegisters.\registers_reg[17][13] " "theRegisters.\registers_reg[19][13] " "theRegisters.\registers_reg[17][12] " "theRegisters.\registers_reg[1][12] " "theRegisters.\registers_reg[23][12] " "theRegisters.\registers_reg[18][12] " + "theRegisters.\registers_reg[20][12] " "theRegisters.\registers_reg[22][12] " "theRegisters.\registers_reg[21][12] " "theRegisters.\registers_reg[19][12] " "theRegisters.\registers_reg[17][11] " "theRegisters.\registers_reg[1][11] " "theRegisters.\registers_reg[23][11] " "theRegisters.\registers_reg[18][11] " "theRegisters.\registers_reg[20][11] " "theRegisters.\registers_reg[22][11] " "theRegisters.\registers_reg[21][11] " "theRegisters.\registers_reg[19][11] " "theRegisters.\registers_reg[20][10] " "theRegisters.\registers_reg[23][10] " "theRegisters.\registers_reg[21][10] " "theRegisters.\registers_reg[18][10] " "theRegisters.\registers_reg[17][10] " "theRegisters.\registers_reg[22][10] " "theRegisters.\registers_reg[1][10] " "theRegisters.\registers_reg[19][10] " "theRegisters.\registers_reg[21][9] " "theRegisters.\registers_reg[23][9] " "theRegisters.\registers_reg[20][9] " "theRegisters.\registers_reg[18][9] " "theRegisters.\registers_reg[17][9] " "theRegisters.\registers_reg[22][9] " "theRegisters.\registers_reg[1][9] " + "theRegisters.\registers_reg[19][9] " "theRegisters.\registers_reg[21][8] " "theRegisters.\registers_reg[23][8] " "theRegisters.\registers_reg[20][8] " "theRegisters.\registers_reg[18][8] " "theRegisters.\registers_reg[17][8] " "theRegisters.\registers_reg[22][8] " "theRegisters.\registers_reg[1][8] " "theRegisters.\registers_reg[19][8] " "theRegisters.\registers_reg[21][7] " "theRegisters.\registers_reg[18][7] " "theRegisters.\registers_reg[20][7] " "theRegisters.\registers_reg[17][7] " "theRegisters.\registers_reg[22][7] " "theRegisters.\registers_reg[19][7] " "theRegisters.\registers_reg[1][7] " "theRegisters.\registers_reg[23][7] " "theRegisters.\registers_reg[17][6] " "theRegisters.\registers_reg[18][6] " "theRegisters.\registers_reg[1][6] " "theRegisters.\registers_reg[20][6] " "theRegisters.\registers_reg[22][6] " "theRegisters.\registers_reg[21][6] " "theRegisters.\registers_reg[19][6] " "theRegisters.\registers_reg[23][6] " "theRegisters.\registers_reg[1][5] " "theRegisters.\registers_reg[23][5] " + "theRegisters.\registers_reg[18][5] " "theRegisters.\registers_reg[22][5] " "theRegisters.\registers_reg[21][5] " "theRegisters.\registers_reg[20][5] " "theRegisters.\registers_reg[17][5] " "theRegisters.\registers_reg[19][5] " "theRegisters.\registers_reg[21][4] " "theRegisters.\registers_reg[1][4] " "theRegisters.\registers_reg[18][4] " "theRegisters.\registers_reg[22][4] " "theRegisters.\registers_reg[23][4] " "theRegisters.\registers_reg[20][4] " "theRegisters.\registers_reg[19][4] " "theRegisters.\registers_reg[17][4] " "theRegisters.\registers_reg[17][3] " "theRegisters.\registers_reg[1][3] " "theRegisters.\registers_reg[23][3] " "theRegisters.\registers_reg[18][3] " "theRegisters.\registers_reg[20][3] " "theRegisters.\registers_reg[22][3] " "theRegisters.\registers_reg[21][3] " "theRegisters.\registers_reg[19][3] " "theRegisters.\registers_reg[1][2] " "theRegisters.\registers_reg[18][2] " "theRegisters.\registers_reg[22][2] " "theRegisters.\registers_reg[21][2] " "theRegisters.\registers_reg[17][2] " + "theRegisters.\registers_reg[20][2] " "theRegisters.\registers_reg[19][2] " "theRegisters.\registers_reg[23][2] " "theRegisters.\registers_reg[21][1] " "theRegisters.\registers_reg[23][1] " "theRegisters.\registers_reg[20][1] " "theRegisters.\registers_reg[18][1] " "theRegisters.\registers_reg[17][1] " "theRegisters.\registers_reg[22][1] " "theRegisters.\registers_reg[1][1] " "theRegisters.\registers_reg[19][1] " "theRegisters.\registers_reg[21][0] " "theRegisters.\registers_reg[20][0] " "theRegisters.\registers_reg[17][0] " "theRegisters.\registers_reg[23][0] " "theRegisters.\registers_reg[18][0] " "theRegisters.\registers_reg[22][0] " "theRegisters.\registers_reg[19][0] " "theRegisters.\registers_reg[1][0] " ; + ScanIn "SI_2"; + ScanOut "SO_2"; + ScanMasterClock "clk_25mhz"; + } + ScanChain unwrapped_chain3 { + ScanLength 256; + ScanInversion 0; + ScanCells "theRegisters.\registers_reg[28][31] " "theRegisters.\registers_reg[26][31] " "theRegisters.\registers_reg[29][31] " "theRegisters.\registers_reg[30][31] " "theRegisters.\registers_reg[24][31] " "theRegisters.\registers_reg[27][31] " "theRegisters.\registers_reg[25][31] " "theRegisters.\registers_reg[2][31] " "theRegisters.\registers_reg[28][30] " "theRegisters.\registers_reg[26][30] " "theRegisters.\registers_reg[29][30] " "theRegisters.\registers_reg[30][30] " "theRegisters.\registers_reg[24][30] " "theRegisters.\registers_reg[27][30] " "theRegisters.\registers_reg[25][30] " "theRegisters.\registers_reg[2][30] " "theRegisters.\registers_reg[28][29] " "theRegisters.\registers_reg[24][29] " "theRegisters.\registers_reg[29][29] " "theRegisters.\registers_reg[26][29] " "theRegisters.\registers_reg[25][29] " "theRegisters.\registers_reg[30][29] " "theRegisters.\registers_reg[27][29] " "theRegisters.\registers_reg[2][29] " "theRegisters.\registers_reg[26][28] " "theRegisters.\registers_reg[28][28] " + "theRegisters.\registers_reg[2][28] " "theRegisters.\registers_reg[29][28] " "theRegisters.\registers_reg[25][28] " "theRegisters.\registers_reg[30][28] " "theRegisters.\registers_reg[24][28] " "theRegisters.\registers_reg[27][28] " "theRegisters.\registers_reg[29][27] " "theRegisters.\registers_reg[2][27] " "theRegisters.\registers_reg[25][27] " "theRegisters.\registers_reg[30][27] " "theRegisters.\registers_reg[28][27] " "theRegisters.\registers_reg[24][27] " "theRegisters.\registers_reg[26][27] " "theRegisters.\registers_reg[27][27] " "theRegisters.\registers_reg[29][26] " "theRegisters.\registers_reg[2][26] " "theRegisters.\registers_reg[25][26] " "theRegisters.\registers_reg[27][26] " "theRegisters.\registers_reg[28][26] " "theRegisters.\registers_reg[24][26] " "theRegisters.\registers_reg[26][26] " "theRegisters.\registers_reg[30][26] " "theRegisters.\registers_reg[2][25] " "theRegisters.\registers_reg[30][25] " "theRegisters.\registers_reg[28][25] " "theRegisters.\registers_reg[26][25] " + "theRegisters.\registers_reg[24][25] " "theRegisters.\registers_reg[25][25] " "theRegisters.\registers_reg[29][25] " "theRegisters.\registers_reg[27][25] " "theRegisters.\registers_reg[2][24] " "theRegisters.\registers_reg[30][24] " "theRegisters.\registers_reg[28][24] " "theRegisters.\registers_reg[26][24] " "theRegisters.\registers_reg[24][24] " "theRegisters.\registers_reg[25][24] " "theRegisters.\registers_reg[29][24] " "theRegisters.\registers_reg[27][24] " "theRegisters.\registers_reg[28][23] " "theRegisters.\registers_reg[26][23] " "theRegisters.\registers_reg[29][23] " "theRegisters.\registers_reg[30][23] " "theRegisters.\registers_reg[24][23] " "theRegisters.\registers_reg[25][23] " "theRegisters.\registers_reg[27][23] " "theRegisters.\registers_reg[2][23] " "theRegisters.\registers_reg[2][22] " "theRegisters.\registers_reg[26][22] " "theRegisters.\registers_reg[28][22] " "theRegisters.\registers_reg[30][22] " "theRegisters.\registers_reg[24][22] " "theRegisters.\registers_reg[25][22] " + "theRegisters.\registers_reg[29][22] " "theRegisters.\registers_reg[27][22] " "theRegisters.\registers_reg[2][21] " "theRegisters.\registers_reg[30][21] " "theRegisters.\registers_reg[28][21] " "theRegisters.\registers_reg[26][21] " "theRegisters.\registers_reg[24][21] " "theRegisters.\registers_reg[25][21] " "theRegisters.\registers_reg[29][21] " "theRegisters.\registers_reg[27][21] " "theRegisters.\registers_reg[2][20] " "theRegisters.\registers_reg[30][20] " "theRegisters.\registers_reg[28][20] " "theRegisters.\registers_reg[26][20] " "theRegisters.\registers_reg[24][20] " "theRegisters.\registers_reg[25][20] " "theRegisters.\registers_reg[29][20] " "theRegisters.\registers_reg[27][20] " "theRegisters.\registers_reg[2][19] " "theRegisters.\registers_reg[27][19] " "theRegisters.\registers_reg[24][19] " "theRegisters.\registers_reg[26][19] " "theRegisters.\registers_reg[28][19] " "theRegisters.\registers_reg[30][19] " "theRegisters.\registers_reg[25][19] " "theRegisters.\registers_reg[29][19] " + "theRegisters.\registers_reg[24][18] " "theRegisters.\registers_reg[28][18] " "theRegisters.\registers_reg[27][18] " "theRegisters.\registers_reg[25][18] " "theRegisters.\registers_reg[26][18] " "theRegisters.\registers_reg[29][18] " "theRegisters.\registers_reg[2][18] " "theRegisters.\registers_reg[30][18] " "theRegisters.\registers_reg[2][17] " "theRegisters.\registers_reg[24][17] " "theRegisters.\registers_reg[26][17] " "theRegisters.\registers_reg[28][17] " "theRegisters.\registers_reg[30][17] " "theRegisters.\registers_reg[25][17] " "theRegisters.\registers_reg[29][17] " "theRegisters.\registers_reg[27][17] " "theRegisters.\registers_reg[29][16] " "theRegisters.\registers_reg[2][16] " "theRegisters.\registers_reg[25][16] " "theRegisters.\registers_reg[28][16] " "theRegisters.\registers_reg[24][16] " "theRegisters.\registers_reg[26][16] " "theRegisters.\registers_reg[30][16] " "theRegisters.\registers_reg[27][16] " "theRegisters.\registers_reg[2][15] " "theRegisters.\registers_reg[24][15] " + "theRegisters.\registers_reg[30][15] " "theRegisters.\registers_reg[28][15] " "theRegisters.\registers_reg[26][15] " "theRegisters.\registers_reg[25][15] " "theRegisters.\registers_reg[29][15] " "theRegisters.\registers_reg[27][15] " "theRegisters.\registers_reg[28][14] " "theRegisters.\registers_reg[29][14] " "theRegisters.\registers_reg[26][14] " "theRegisters.\registers_reg[30][14] " "theRegisters.\registers_reg[2][14] " "theRegisters.\registers_reg[24][14] " "theRegisters.\registers_reg[25][14] " "theRegisters.\registers_reg[27][14] " "theRegisters.\registers_reg[28][13] " "theRegisters.\registers_reg[26][13] " "theRegisters.\registers_reg[29][13] " "theRegisters.\registers_reg[30][13] " "theRegisters.\registers_reg[24][13] " "theRegisters.\registers_reg[25][13] " "theRegisters.\registers_reg[2][13] " "theRegisters.\registers_reg[27][13] " "theRegisters.\registers_reg[28][12] " "theRegisters.\registers_reg[26][12] " "theRegisters.\registers_reg[29][12] " "theRegisters.\registers_reg[30][12] " + "theRegisters.\registers_reg[24][12] " "theRegisters.\registers_reg[25][12] " "theRegisters.\registers_reg[2][12] " "theRegisters.\registers_reg[27][12] " "theRegisters.\registers_reg[28][11] " "theRegisters.\registers_reg[26][11] " "theRegisters.\registers_reg[29][11] " "theRegisters.\registers_reg[30][11] " "theRegisters.\registers_reg[24][11] " "theRegisters.\registers_reg[25][11] " "theRegisters.\registers_reg[2][11] " "theRegisters.\registers_reg[27][11] " "theRegisters.\registers_reg[28][10] " "theRegisters.\registers_reg[24][10] " "theRegisters.\registers_reg[27][10] " "theRegisters.\registers_reg[29][10] " "theRegisters.\registers_reg[30][10] " "theRegisters.\registers_reg[25][10] " "theRegisters.\registers_reg[26][10] " "theRegisters.\registers_reg[2][10] " "theRegisters.\registers_reg[29][9] " "theRegisters.\registers_reg[24][9] " "theRegisters.\registers_reg[26][9] " "theRegisters.\registers_reg[25][9] " "theRegisters.\registers_reg[28][9] " "theRegisters.\registers_reg[30][9] " "theRegisters.\registers_reg[2][9] " + "theRegisters.\registers_reg[27][9] " "theRegisters.\registers_reg[29][8] " "theRegisters.\registers_reg[24][8] " "theRegisters.\registers_reg[26][8] " "theRegisters.\registers_reg[25][8] " "theRegisters.\registers_reg[28][8] " "theRegisters.\registers_reg[30][8] " "theRegisters.\registers_reg[2][8] " "theRegisters.\registers_reg[27][8] " "theRegisters.\registers_reg[25][7] " "theRegisters.\registers_reg[28][7] " "theRegisters.\registers_reg[24][7] " "theRegisters.\registers_reg[27][7] " "theRegisters.\registers_reg[29][7] " "theRegisters.\registers_reg[26][7] " "theRegisters.\registers_reg[30][7] " "theRegisters.\registers_reg[2][7] " "theRegisters.\registers_reg[28][6] " "theRegisters.\registers_reg[29][6] " "theRegisters.\registers_reg[27][6] " "theRegisters.\registers_reg[26][6] " "theRegisters.\registers_reg[30][6] " "theRegisters.\registers_reg[24][6] " "theRegisters.\registers_reg[25][6] " "theRegisters.\registers_reg[2][6] " "theRegisters.\registers_reg[28][5] " "theRegisters.\registers_reg[26][5] " + "theRegisters.\registers_reg[29][5] " "theRegisters.\registers_reg[30][5] " "theRegisters.\registers_reg[24][5] " "theRegisters.\registers_reg[25][5] " "theRegisters.\registers_reg[2][5] " "theRegisters.\registers_reg[27][5] " "theRegisters.\registers_reg[28][4] " "theRegisters.\registers_reg[26][4] " "theRegisters.\registers_reg[30][4] " "theRegisters.\registers_reg[24][4] " "theRegisters.\registers_reg[27][4] " "theRegisters.\registers_reg[25][4] " "theRegisters.\registers_reg[29][4] " "theRegisters.\registers_reg[2][4] " "theRegisters.\registers_reg[28][3] " "theRegisters.\registers_reg[26][3] " "theRegisters.\registers_reg[29][3] " "theRegisters.\registers_reg[30][3] " "theRegisters.\registers_reg[24][3] " "theRegisters.\registers_reg[25][3] " "theRegisters.\registers_reg[2][3] " "theRegisters.\registers_reg[27][3] " "theRegisters.\registers_reg[28][2] " "theRegisters.\registers_reg[27][2] " "theRegisters.\registers_reg[30][2] " "theRegisters.\registers_reg[29][2] " "theRegisters.\registers_reg[26][2] " + "theRegisters.\registers_reg[24][2] " "theRegisters.\registers_reg[25][2] " "theRegisters.\registers_reg[2][2] " "theRegisters.\registers_reg[29][1] " "theRegisters.\registers_reg[24][1] " "theRegisters.\registers_reg[26][1] " "theRegisters.\registers_reg[25][1] " "theRegisters.\registers_reg[28][1] " "theRegisters.\registers_reg[30][1] " "theRegisters.\registers_reg[2][1] " "theRegisters.\registers_reg[27][1] " "theRegisters.\registers_reg[26][0] " "theRegisters.\registers_reg[25][0] " "theRegisters.\registers_reg[28][0] " "theRegisters.\registers_reg[24][0] " "theRegisters.\registers_reg[29][0] " "theRegisters.\registers_reg[30][0] " "theRegisters.\registers_reg[2][0] " "theRegisters.\registers_reg[27][0] " ; + ScanIn "SI_3"; + ScanOut "SO_3"; + ScanMasterClock "clk_25mhz"; + } + ScanChain unwrapped_chain4 { + ScanLength 256; + ScanInversion 0; + ScanCells "theRegisters.\registers_reg[4][31] " "theRegisters.\registers_reg[31][31] " "theRegisters.\registers_reg[6][31] " "theRegisters.\registers_reg[7][31] " "theRegisters.\registers_reg[5][31] " "theRegisters.\registers_reg[8][31] " "theRegisters.\registers_reg[9][31] " "theRegisters.\registers_reg[3][31] " "theRegisters.\registers_reg[31][30] " "theRegisters.\registers_reg[6][30] " "theRegisters.\registers_reg[7][30] " "theRegisters.\registers_reg[5][30] " "theRegisters.\registers_reg[8][30] " "theRegisters.\registers_reg[9][30] " "theRegisters.\registers_reg[4][30] " "theRegisters.\registers_reg[3][30] " "theRegisters.\registers_reg[8][29] " "theRegisters.\registers_reg[31][29] " "theRegisters.\registers_reg[7][29] " "theRegisters.\registers_reg[4][29] " "theRegisters.\registers_reg[5][29] " "theRegisters.\registers_reg[9][29] " "theRegisters.\registers_reg[6][29] " "theRegisters.\registers_reg[3][29] " "theRegisters.\registers_reg[5][28] " "theRegisters.\registers_reg[9][28] " "theRegisters.\registers_reg[4][28] " + "theRegisters.\registers_reg[6][28] " "theRegisters.\registers_reg[8][28] " "theRegisters.\registers_reg[3][28] " "theRegisters.\registers_reg[31][28] " "theRegisters.\registers_reg[7][28] " "theRegisters.\registers_reg[8][27] " "theRegisters.\registers_reg[9][27] " "theRegisters.\registers_reg[7][27] " "theRegisters.\registers_reg[6][27] " "theRegisters.\registers_reg[5][27] " "theRegisters.\registers_reg[4][27] " "theRegisters.\registers_reg[3][27] " "theRegisters.\registers_reg[31][27] " "theRegisters.\registers_reg[9][26] " "theRegisters.\registers_reg[7][26] " "theRegisters.\registers_reg[31][26] " "theRegisters.\registers_reg[6][26] " "theRegisters.\registers_reg[5][26] " "theRegisters.\registers_reg[4][26] " "theRegisters.\registers_reg[8][26] " "theRegisters.\registers_reg[3][26] " "theRegisters.\registers_reg[6][25] " "theRegisters.\registers_reg[8][25] " "theRegisters.\registers_reg[5][25] " "theRegisters.\registers_reg[4][25] " "theRegisters.\registers_reg[7][25] " "theRegisters.\registers_reg[9][25] " + "theRegisters.\registers_reg[3][25] " "theRegisters.\registers_reg[31][25] " "theRegisters.\registers_reg[6][24] " "theRegisters.\registers_reg[8][24] " "theRegisters.\registers_reg[5][24] " "theRegisters.\registers_reg[4][24] " "theRegisters.\registers_reg[7][24] " "theRegisters.\registers_reg[9][24] " "theRegisters.\registers_reg[3][24] " "theRegisters.\registers_reg[31][24] " "theRegisters.\registers_reg[9][23] " "theRegisters.\registers_reg[3][23] " "theRegisters.\registers_reg[31][23] " "theRegisters.\registers_reg[8][23] " "theRegisters.\registers_reg[7][23] " "theRegisters.\registers_reg[6][23] " "theRegisters.\registers_reg[5][23] " "theRegisters.\registers_reg[4][23] " "theRegisters.\registers_reg[6][22] " "theRegisters.\registers_reg[5][22] " "theRegisters.\registers_reg[31][22] " "theRegisters.\registers_reg[4][22] " "theRegisters.\registers_reg[7][22] " "theRegisters.\registers_reg[9][22] " "theRegisters.\registers_reg[8][22] " "theRegisters.\registers_reg[3][22] " "theRegisters.\registers_reg[6][21] " + "theRegisters.\registers_reg[8][21] " "theRegisters.\registers_reg[5][21] " "theRegisters.\registers_reg[4][21] " "theRegisters.\registers_reg[7][21] " "theRegisters.\registers_reg[9][21] " "theRegisters.\registers_reg[3][21] " "theRegisters.\registers_reg[31][21] " "theRegisters.\registers_reg[8][20] " "theRegisters.\registers_reg[5][20] " "theRegisters.\registers_reg[4][20] " "theRegisters.\registers_reg[6][20] " "theRegisters.\registers_reg[7][20] " "theRegisters.\registers_reg[9][20] " "theRegisters.\registers_reg[3][20] " "theRegisters.\registers_reg[31][20] " "theRegisters.\registers_reg[31][19] " "theRegisters.\registers_reg[4][19] " "theRegisters.\registers_reg[5][19] " "theRegisters.\registers_reg[6][19] " "theRegisters.\registers_reg[9][19] " "theRegisters.\registers_reg[8][19] " "theRegisters.\registers_reg[7][19] " "theRegisters.\registers_reg[3][19] " "theRegisters.\registers_reg[9][18] " "theRegisters.\registers_reg[7][18] " "theRegisters.\registers_reg[31][18] " "theRegisters.\registers_reg[6][18] " + "theRegisters.\registers_reg[4][18] " "theRegisters.\registers_reg[5][18] " "theRegisters.\registers_reg[8][18] " "theRegisters.\registers_reg[3][18] " "theRegisters.\registers_reg[31][17] " "theRegisters.\registers_reg[4][17] " "theRegisters.\registers_reg[5][17] " "theRegisters.\registers_reg[6][17] " "theRegisters.\registers_reg[7][17] " "theRegisters.\registers_reg[9][17] " "theRegisters.\registers_reg[8][17] " "theRegisters.\registers_reg[3][17] " "theRegisters.\registers_reg[9][16] " "theRegisters.\registers_reg[7][16] " "theRegisters.\registers_reg[31][16] " "theRegisters.\registers_reg[6][16] " "theRegisters.\registers_reg[5][16] " "theRegisters.\registers_reg[4][16] " "theRegisters.\registers_reg[8][16] " "theRegisters.\registers_reg[3][16] " "theRegisters.\registers_reg[8][15] " "theRegisters.\registers_reg[4][15] " "theRegisters.\registers_reg[5][15] " "theRegisters.\registers_reg[6][15] " "theRegisters.\registers_reg[7][15] " "theRegisters.\registers_reg[9][15] " "theRegisters.\registers_reg[3][15] " + "theRegisters.\registers_reg[31][15] " "theRegisters.\registers_reg[5][14] " "theRegisters.\registers_reg[8][14] " "theRegisters.\registers_reg[9][14] " "theRegisters.\registers_reg[3][14] " "theRegisters.\registers_reg[31][14] " "theRegisters.\registers_reg[4][14] " "theRegisters.\registers_reg[6][14] " "theRegisters.\registers_reg[7][14] " "theRegisters.\registers_reg[4][13] " "theRegisters.\registers_reg[8][13] " "theRegisters.\registers_reg[9][13] " "theRegisters.\registers_reg[6][13] " "theRegisters.\registers_reg[5][13] " "theRegisters.\registers_reg[3][13] " "theRegisters.\registers_reg[31][13] " "theRegisters.\registers_reg[7][13] " "theRegisters.\registers_reg[8][12] " "theRegisters.\registers_reg[9][12] " "theRegisters.\registers_reg[6][12] " "theRegisters.\registers_reg[3][12] " "theRegisters.\registers_reg[5][12] " "theRegisters.\registers_reg[31][12] " "theRegisters.\registers_reg[4][12] " "theRegisters.\registers_reg[7][12] " "theRegisters.\registers_reg[8][11] " "theRegisters.\registers_reg[9][11] " + "theRegisters.\registers_reg[6][11] " "theRegisters.\registers_reg[5][11] " "theRegisters.\registers_reg[3][11] " "theRegisters.\registers_reg[31][11] " "theRegisters.\registers_reg[4][11] " "theRegisters.\registers_reg[7][11] " "theRegisters.\registers_reg[8][10] " "theRegisters.\registers_reg[31][10] " "theRegisters.\registers_reg[7][10] " "theRegisters.\registers_reg[4][10] " "theRegisters.\registers_reg[5][10] " "theRegisters.\registers_reg[9][10] " "theRegisters.\registers_reg[6][10] " "theRegisters.\registers_reg[3][10] " "theRegisters.\registers_reg[7][9] " "theRegisters.\registers_reg[3][9] " "theRegisters.\registers_reg[31][9] " "theRegisters.\registers_reg[4][9] " "theRegisters.\registers_reg[8][9] " "theRegisters.\registers_reg[5][9] " "theRegisters.\registers_reg[9][9] " "theRegisters.\registers_reg[6][9] " "theRegisters.\registers_reg[7][8] " "theRegisters.\registers_reg[3][8] " "theRegisters.\registers_reg[31][8] " "theRegisters.\registers_reg[4][8] " "theRegisters.\registers_reg[8][8] " + "theRegisters.\registers_reg[5][8] " "theRegisters.\registers_reg[9][8] " "theRegisters.\registers_reg[6][8] " "theRegisters.\registers_reg[8][7] " "theRegisters.\registers_reg[31][7] " "theRegisters.\registers_reg[7][7] " "theRegisters.\registers_reg[4][7] " "theRegisters.\registers_reg[5][7] " "theRegisters.\registers_reg[3][7] " "theRegisters.\registers_reg[9][7] " "theRegisters.\registers_reg[6][7] " "theRegisters.\registers_reg[8][6] " "theRegisters.\registers_reg[9][6] " "theRegisters.\registers_reg[6][6] " "theRegisters.\registers_reg[5][6] " "theRegisters.\registers_reg[31][6] " "theRegisters.\registers_reg[4][6] " "theRegisters.\registers_reg[7][6] " "theRegisters.\registers_reg[3][6] " "theRegisters.\registers_reg[4][5] " "theRegisters.\registers_reg[8][5] " "theRegisters.\registers_reg[9][5] " "theRegisters.\registers_reg[6][5] " "theRegisters.\registers_reg[3][5] " "theRegisters.\registers_reg[5][5] " "theRegisters.\registers_reg[31][5] " "theRegisters.\registers_reg[7][5] " "theRegisters.\registers_reg[9][4] " + "theRegisters.\registers_reg[8][4] " "theRegisters.\registers_reg[3][4] " "theRegisters.\registers_reg[31][4] " "theRegisters.\registers_reg[7][4] " "theRegisters.\registers_reg[4][4] " "theRegisters.\registers_reg[6][4] " "theRegisters.\registers_reg[5][4] " "theRegisters.\registers_reg[8][3] " "theRegisters.\registers_reg[9][3] " "theRegisters.\registers_reg[6][3] " "theRegisters.\registers_reg[3][3] " "theRegisters.\registers_reg[5][3] " "theRegisters.\registers_reg[31][3] " "theRegisters.\registers_reg[4][3] " "theRegisters.\registers_reg[7][3] " "theRegisters.\registers_reg[4][2] " "theRegisters.\registers_reg[31][2] " "theRegisters.\registers_reg[6][2] " "theRegisters.\registers_reg[5][2] " "theRegisters.\registers_reg[8][2] " "theRegisters.\registers_reg[9][2] " "theRegisters.\registers_reg[7][2] " "theRegisters.\registers_reg[3][2] " "theRegisters.\registers_reg[7][1] " "theRegisters.\registers_reg[3][1] " "theRegisters.\registers_reg[31][1] " "theRegisters.\registers_reg[4][1] " "theRegisters.\registers_reg[8][1] " + "theRegisters.\registers_reg[5][1] " "theRegisters.\registers_reg[9][1] " "theRegisters.\registers_reg[6][1] " "theRegisters.\registers_reg[8][0] " "theRegisters.\registers_reg[7][0] " "theRegisters.\registers_reg[3][0] " "theRegisters.\registers_reg[31][0] " "theRegisters.\registers_reg[4][0] " "theRegisters.\registers_reg[5][0] " "theRegisters.\registers_reg[9][0] " "theRegisters.\registers_reg[6][0] " ; + ScanIn "SI_4"; + ScanOut "SO_4"; + ScanMasterClock "clk_25mhz"; + } +} + +MacroDefs { + "scan_grp1" { + W tset_gen_tp1; + Shift { V { "scan_en" = 1; "_unwrapped_chain1_SI_1_" = #; "_unwrapped_chain1_SO_1_" = #; "_unwrapped_chain2_SI_2_" = #; "_unwrapped_chain2_SO_2_" = #; "_unwrapped_chain3_SI_3_" = #; "_unwrapped_chain3_SO_3_" = #; "_unwrapped_chain4_SI_4_" = #; "_unwrapped_chain4_SO_4_" = #; "clk_25mhz" = 1; } } + W tset_gen_tp1; + } +} + +PatternBurst scanpats { + PatList { scan_test; } +} + +PatternExec { + Timing STUCK_timing; + PatternBurst scanpats; +} + + +Pattern scan_test { + Ann {* Begin chain test *} + //Chain Pattern:0 Vector:0 TesterCycle:0 + Ann {* Chain Pattern:0 Vector:0 TesterCycle:0 *} + "chain_pattern 0": + Macro "scan_grp1" { + "_unwrapped_chain1_SI_1_" = 0011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011; + "_unwrapped_chain1_SO_1_" = \r256 X; + "_unwrapped_chain2_SI_2_" = 0011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011; + "_unwrapped_chain2_SO_2_" = \r256 X; + "_unwrapped_chain3_SI_3_" = 0011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011; + "_unwrapped_chain3_SO_3_" = \r256 X; + "_unwrapped_chain4_SI_4_" = 0011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011; + "_unwrapped_chain4_SO_4_" = \r256 X; + } + V { + _pi_=ZZZZZZN011111; + _po_=\r12 X; + } + Macro "scan_grp1" { + "_unwrapped_chain1_SI_1_" = 0011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011; + "_unwrapped_chain1_SO_1_" = LLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHH; + "_unwrapped_chain2_SI_2_" = 0011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011; + "_unwrapped_chain2_SO_2_" = LLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHH; + "_unwrapped_chain3_SI_3_" = 0011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011; + "_unwrapped_chain3_SO_3_" = LLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHH; + "_unwrapped_chain4_SI_4_" = 0011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011001100110011; + "_unwrapped_chain4_SO_4_" = LLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHHLLHH; + } + Ann {* End chain test *} + //Pattern:0 Vector:3 TesterCycle:513 + Ann {* Pattern:0 Vector:3 TesterCycle:513 *} + "pattern 0": + Macro "scan_grp1" { + "_unwrapped_chain1_SI_1_" = 0011100000100001110010101100111011011010001011000111100111101111010010110111010011000010011101001110001000100011110110000100000111011011011101000100100001001111111101111111001111100111101000010001110010111011011100001010000000 \r24 1 001111; + "_unwrapped_chain1_SO_1_" = \r256 X; + "_unwrapped_chain2_SI_2_" = 1100100001001001011011110101011111011101010011011011110100011100010110100010111100111101011010101110111101001011100111101100111000101011000011010110110111001101001000111001100001110011110111011111010110001101001111010111101000101001001111110000110110001000; + "_unwrapped_chain2_SO_2_" = \r256 X; + "_unwrapped_chain3_SI_3_" = 0111011001010101010000101110010011010100000011011110001100110111011011101110000111011101101001111000011000010101101010110100100010100100101111110001010001011111000111001001110001100101100010010001011011011110000011101010100111111011111000011011111110001000; + "_unwrapped_chain3_SO_3_" = \r256 X; + "_unwrapped_chain4_SI_4_" = 11010110101111111011010001111011001001100101100110110110011001111010010100010100111000111110101101011100010 \r10 1 0001111000101111101100111011000111110111011101000110011111111010101000100111011100101000111010001011111000101100010011101000111000011100100; + "_unwrapped_chain4_SO_4_" = \r256 X; + } + V { + _pi_=0001110100011; + _po_=XXXXXXXXLHLH; + } + //Pattern:1 Vector:5 TesterCycle:770 + Ann {* Pattern:1 Vector:5 TesterCycle:770 *} + "pattern 1": + Macro "scan_grp1" { + "_unwrapped_chain1_SI_1_" = 001001001000111101101111111001101001011010000111001010101011100101110101011110111111000101001001011110100001111010010011110101100111001100010101100100101101111101010011111011101000111110011000111010011010100011110100000100010 \r13 1 011111110110111111; + "_unwrapped_chain1_SO_1_" = \r256 L; + "_unwrapped_chain2_SI_2_" = 1100101010001101111001111100101010001101101010001010011000111111110010000100011010101011111101110111011100010110000010111000000111110010001010001010010001010100011001100001100111110101000101011101001111000101111111011101101110001000101011110101010110011001; + "_unwrapped_chain2_SO_2_" = \r256 L; + "_unwrapped_chain3_SI_3_" = 1010101010101100011100011101011110110000010001110110100000011110101100100111001101001100011110000010001100110001111110010001111001101110010111011111101110111110100101100110011001011101000100101111011111001011100100100010111010101100101000101010001001011011; + "_unwrapped_chain3_SO_3_" = \r256 L; + "_unwrapped_chain4_SI_4_" = 1100 \r11 1 00010111010110111000011111100111110101111000111000111110100010101111101100110001110110111111110111110100010101110000000111001110000101110001100111110111000111100110101110100111110010001011010111010010000001001111010001011000001010 \r11 1; + "_unwrapped_chain4_SO_4_" = \r256 L; + } + V { + _pi_=1010010101011; + _po_=XXXXXXXXLHHH; + } + //Pattern:2 Vector:7 TesterCycle:1027 + Ann {* Pattern:2 Vector:7 TesterCycle:1027 *} + "pattern 2": + Macro "scan_grp1" { + "_unwrapped_chain1_SI_1_" = 11110001011011001111011010100111000110111000010000000010110010001111111101010110011111010101110011100001101011010111110010101000101011101110110011010100110000011010110011111001100111111010111011000110100110100110000011100100 \r30 1 01; + "_unwrapped_chain1_SO_1_" = \r256 L; + "_unwrapped_chain2_SI_2_" = 0010000010111001001111101101111010010000101101001111101100000101001101101101111100111110110011001101000111101111011010110111001010110011111010001111110111110010011000010111111001110000111111001111000101010100111101110101111011110011001011011101010011001011; + "_unwrapped_chain2_SO_2_" = \r256 L; + "_unwrapped_chain3_SI_3_" = 111110101011101001011101111001010101111011001111011110110011100100100111111011111010111101000101010 \r10 1 001100001010101101111011110100001111101100111100010000100011010111001101101100010011011111011010011111100100011010010110100001010011111101100011101; + "_unwrapped_chain3_SO_3_" = \r256 L; + "_unwrapped_chain4_SI_4_" = 0101010 \r10 1 0110001011001011111000011010001000010101111011111110011010011111111100111001111000101001000001111010010001011001110011111101101100101110111001111100011111110111111100100111011001100000101011110000001110 \r10 1 011011111110011111011110111; + "_unwrapped_chain4_SO_4_" = \r256 L; + } + V { + _pi_=1111100100111; + _po_=XXXXXXXXHLHL; + } + //Pattern:3 Vector:9 TesterCycle:1284 + Ann {* Pattern:3 Vector:9 TesterCycle:1284 *} + "pattern 3": + Macro "scan_grp1" { + "_unwrapped_chain1_SI_1_" = 000110100001110111001010100001111111110100000101100100101111000001001010001000001111101101010110001011000111010010010011000111111111001100011110011101111100111011010011110100110001011111110101110100010000001100101010100111100 \r24 1 0011101; + "_unwrapped_chain1_SO_1_" = \r256 L; + "_unwrapped_chain2_SI_2_" = 1111010110010011010001110101010110011110001110101101011010011000011010011001001111110010011100010000001010011001110110101000101110010011000001011101110100110011001100101101100110110011001110000111000100011110011100100001110001011111111011001101010001100010; + "_unwrapped_chain2_SO_2_" = \r256 L; + "_unwrapped_chain3_SI_3_" = 1101111110110001011010111111110000111010100010110111011011101000111011010010000111011110110111011110000010011101100110110111100100000110111010101100110111001100010110100100101001010111110001010001011110011111110000110011100010111010011011000101011010111000; + "_unwrapped_chain3_SO_3_" = \r256 L; + "_unwrapped_chain4_SI_4_" = 0111100011110101011111101000110100001111010111100101111100010010001111111110001011101110000110101100010010111110011111110110110110010101010101110100101011001011101001010001100001101110000100111110000011111001100100111011010101111011100110001011101011100000; + "_unwrapped_chain4_SO_4_" = \r256 L; + } + V { + _pi_=0101010101001; + _po_=XXXXXXXXLHHL; + } + //Pattern:4 Vector:11 TesterCycle:1541 + Ann {* Pattern:4 Vector:11 TesterCycle:1541 *} + "pattern 4": + Macro "scan_grp1" { + "_unwrapped_chain1_SI_1_" = 00100110101101100000001000011011001001111111011100111110110001011111001110011101111101001100111101111000111111001011010101011011011000101010 \r12 1 011110110000100001001111110000111011111000010110010101101011110111100111110 \r26 1 011; + "_unwrapped_chain1_SO_1_" = \r256 L; + "_unwrapped_chain2_SI_2_" = 00000110001001001001100011011000000010100101101110001100110011111111010001010101010 \r11 1 001100110101100010100110111100010110101111101111110101101101101110111001111001101101100001011011101111000010101011000101101111001110001001001111010101000011111111; + "_unwrapped_chain2_SO_2_" = \r256 L; + "_unwrapped_chain3_SI_3_" = 1101101000010010111111000111110110110011110011011011101111110011001011100000101001111111001000111111101111100111000001110100111101101110010001010111001110111111101101101010101101101100101011111101110111001011101111110111111100101111011010001100111011110001; + "_unwrapped_chain3_SO_3_" = \r256 L; + "_unwrapped_chain4_SI_4_" = 1111110000010010110100001111101111010110110101010110101111001010101111011111110111110110110101111110000011111001000000111010100111111101100111010000001001110011100111110101101111000001011101110001101111010001110101101111100110100100000011111010000111111001; + "_unwrapped_chain4_SO_4_" = \r256 L; + } + V { + _pi_=0000000101111; + _po_=XXXXXXXXLLHH; + } + //Pattern:5 Vector:13 TesterCycle:1798 + Ann {* Pattern:5 Vector:13 TesterCycle:1798 *} + "pattern 5": + Macro "scan_grp1" { + "_unwrapped_chain1_SI_1_" = 110001100001111000111101111001101011010110010001110101111100000111110010101110101000011011101011100011010001011111010000100000001101111110000100101101001111111001011010111111110101011111100100000000100101001110101001110111000 \r21 1 0010001011; + "_unwrapped_chain1_SO_1_" = \r256 L; + "_unwrapped_chain2_SI_2_" = 0001000000100000000010101110000010111101100100001101011000001011111001010100111101110111111001111101000101101100011101001011110101000010100111000110010000110010111110101101010111010111001110101101111010001101010111110111010010000101001011111000110111001111; + "_unwrapped_chain2_SO_2_" = \r256 L; + "_unwrapped_chain3_SI_3_" = 10100101001110001110100001101100101110001101000110100000101000110011010101101000010001 \r11 0 111100100100101001101001010111001000101111111010111000100111001011111101110011001001110111011010101010110111110001111100010111000011001100100010111011000111011; + "_unwrapped_chain3_SO_3_" = \r256 L; + "_unwrapped_chain4_SI_4_" = 1111000111111110011110110010010111000001111001110001111001110011011000111000110010000111010010101010010101110101011010100111010110100011000001111101111111101000101011011010010110101001100000111001101111110111101000111100000000100000111110110101001011101100; + "_unwrapped_chain4_SO_4_" = \r256 L; + } + V { + _pi_=1010100100101; + _po_=XXXXXXXXHLHH; + } + //Pattern:6 Vector:15 TesterCycle:2055 + Ann {* Pattern:6 Vector:15 TesterCycle:2055 *} + "pattern 6": + Macro "scan_grp1" { + "_unwrapped_chain1_SI_1_" = 11011011100110011001010101110000101010010101100111010101101011100010100110011101010100101111011011001100100011001001111111110110101100110111110111101100100011111000010101101010110 \r10 1 00001100110111011001001100010101111010 \r15 1 01110110111001; + "_unwrapped_chain1_SO_1_" = \r256 L; + "_unwrapped_chain2_SI_2_" = 1100011010011001011101011001000100111101110000100101010110110100010101101101011010001110011101011110100000000101111111101011101001000110111000000010000010101011101110101011111100110111011101100011110001100101110111001101111011011110101011110001010110111010; + "_unwrapped_chain2_SO_2_" = \r256 L; + "_unwrapped_chain3_SI_3_" = 0100000100011010110000101000011110011110001010010100000111011000111011100011011110100010001010111101111010101011011101101110100100011100111111011101101100001100100101110101101101001110111001101101110010111111100010000110111101011001110110101100011110000010; + "_unwrapped_chain3_SO_3_" = \r256 L; + "_unwrapped_chain4_SI_4_" = 1101010001001110110000000001100101111101000100001111101100010111111010110101100111100100001100110100100101101110111001011110110011101101101101010000011101011011101010010110000111111011000001110000100001000011010001111001001101101001111101111100011011111111; + "_unwrapped_chain4_SO_4_" = \r256 L; + } + V { + _pi_=1111110101000; + _po_=XXXXXXXXHHLH; + } + //Pattern:7 Vector:17 TesterCycle:2312 + Ann {* Pattern:7 Vector:17 TesterCycle:2312 *} + "pattern 7": + Macro "scan_grp1" { + "_unwrapped_chain1_SI_1_" = 01010110010101000100010101110011101110110001110110010100100110001100111100001011101100010101000001001100100010011011000100101111100000100000110101010000100110110010111001100001001011111011000001011100100000110010000001010100110 \r18 1 01110101101; + "_unwrapped_chain1_SO_1_" = \r256 L; + "_unwrapped_chain2_SI_2_" = 10111101111001011000101001101100 \r11 1 011110111110001111011101011110111101011110011110110001111000010111001001001111101100110000100010111110000000011100011001000101001011001100111000000001101010001100011100000010000100111101011011111110001101101000001; + "_unwrapped_chain2_SO_2_" = \r256 L; + "_unwrapped_chain3_SI_3_" = 1011010100001111111110001111010000110101000101011011000001101011011101110001000001110011000111100100110111101111010101011100111010111010011011000111011001010110110000101000011111001110100011010101010011011111010110111100111011111011111110110101111001101110; + "_unwrapped_chain3_SO_3_" = \r256 L; + "_unwrapped_chain4_SI_4_" = 1110111011000110000111011000010100100111011000110001101100000100111011110011001001011111100010111011011101110011100001100110000001001011110111000110111100001110101110110010001110001010110001111100111111001101001011011011100111111111001100010000110111010000; + "_unwrapped_chain4_SO_4_" = \r256 L; + } + V { + _pi_=0101010100110; + _po_=XXXXXXXXLHHH; + } + //Pattern:8 Vector:19 TesterCycle:2569 + Ann {* Pattern:8 Vector:19 TesterCycle:2569 *} + "pattern 8": + Macro "scan_grp1" { + "_unwrapped_chain1_SI_1_" = 101101101111110000111000001110110110001010010111111001101110011111111011011101011110101011111111101101010001100110010011001010011010111110011101010110100011110000101111011100011010001110000001011110111110000001110101011110010 \r22 1 011011101; + "_unwrapped_chain1_SO_1_" = \r256 L; + "_unwrapped_chain2_SI_2_" = 0101010011110010101001110111100101110110011011001110001011011001111110101111111001101010111001101110100111011101100100011010000100110111101101111101111001010010011101001101000001100110011010010001110101011010001100101100010000101001001011100110110111111101; + "_unwrapped_chain2_SO_2_" = \r256 L; + "_unwrapped_chain3_SI_3_" = 0000001111010000010011101001111101010001110110010110110111111100001011101010110111011111001011011101011011101001100011101100100001100011011100001110000110101001010011010010001101011110101100001011111010000110000111001011101101100000011111101101011011111100; + "_unwrapped_chain3_SO_3_" = \r256 L; + "_unwrapped_chain4_SI_4_" = 0101101011010001110111100000000110011111111100101011111000100100001111111010001011010101110000101110001001101011010110001111011010111101101101100110111000001000101101101010101111101000100000111110001011111111001100101110000100111110000010001100110111001111; + "_unwrapped_chain4_SO_4_" = \r256 L; + } + V { + _pi_=0000000100001; + _po_=XXXXXXXXHLLL; + } + //Pattern:9 Vector:21 TesterCycle:2826 + Ann {* Pattern:9 Vector:21 TesterCycle:2826 *} + "pattern 9": + Macro "scan_grp1" { + "_unwrapped_chain1_SI_1_" = 101110010101010111111101010010011110000110001100111000001010111100011 \r10 0 1001100011110011111001110001011101111010011010111011100101010011010110000101100001001001011011111100011111010001101000111101111101011000001110000100 \r24 1 01011; + "_unwrapped_chain1_SO_1_" = \r256 L; + "_unwrapped_chain2_SI_2_" = 1110111110101110100011101010001101111100010101101101101001111110100011111010001101011011010001010001111010000000111001110110001011010001011001100100101011110001101110000001111010111011011000101101111100011011100100011101000100100011111111010101100011111011; + "_unwrapped_chain2_SO_2_" = \r256 L; + "_unwrapped_chain3_SI_3_" = 1011011100100101011000100100011100110100001001010111110111001010011010011101001011100110111010111010010001010101000111101011100011001000000100010101010111111001111101000000110011001110010110011001110010110101001111000111111101010000010001111100001001001010; + "_unwrapped_chain3_SO_3_" = \r256 L; + "_unwrapped_chain4_SI_4_" = 1101111101100100110011010011111100111000101011101000001101101011111010111001010001110000101111011011111101101011101010100000000110111011011111001010011101111110100001111011000001100111110111110000100111111101110010101010101010110000001001110101001111011101; + "_unwrapped_chain4_SO_4_" = \r256 L; + } + V { + _pi_=1010100101010; + _po_=XXXXXXXXHHHH; + } + Macro "scan_grp1" { + "_unwrapped_chain1_SI_1_" = 101110010101010111111101010010011110000110001100111000001010111100011 \r10 0 1001100011110011111001110001011101111010011010111011100101010011010110000101100001001001011011111100011111010001101000111101111101011000001110000100 \r24 1 01011; + "_unwrapped_chain1_SO_1_" = \r256 L; + "_unwrapped_chain2_SI_2_" = 1110111110101110100011101010001101111100010101101101101001111110100011111010001101011011010001010001111010000000111001110110001011010001011001100100101011110001101110000001111010111011011000101101111100011011100100011101000100100011111111010101100011111011; + "_unwrapped_chain2_SO_2_" = \r256 L; + "_unwrapped_chain3_SI_3_" = 1011011100100101011000100100011100110100001001010111110111001010011010011101001011100110111010111010010001010101000111101011100011001000000100010101010111111001111101000000110011001110010110011001110010110101001111000111111101010000010001111100001001001010; + "_unwrapped_chain3_SO_3_" = \r256 L; + "_unwrapped_chain4_SI_4_" = 1101111101100100110011010011111100111000101011101000001101101011111010111001010001110000101111011011111101101011101010100000000110111011011111001010011101111110100001111011000001100111110111110000100111111101110010101010101010110000001001110101001111011101; + "_unwrapped_chain4_SO_4_" = \r256 L; + } + Ann {* Total count Patterns:10 Vectors:24 TesterCycles:3339 *} +} diff --git a/cpu_patterns_serial.v b/cpu_patterns_serial.v new file mode 100644 index 0000000..fefcf45 --- /dev/null +++ b/cpu_patterns_serial.v @@ -0,0 +1,1098 @@ +// +// Verilog format test patterns produced by Tessent Shell 2023.4-p1 +// Filename : cpu_patterns_serial.v +// Scan operation : SERIAL +// Idstamp : 2023.4-p1:05e1:d9b6:10:040e +// Fault : STUCK +// Coverage : 25.96(TC) 24.58(FC) +// Date : Thu May 28 18:01:24 2026 +// +// Begin_Verify_Section +// format = Verilog +// top_module_name = cpu_cpu_patterns_serial_v_ctl +// serial_flag = ON +// test_set_type = ALL_TEST +// pad_value = X +// pattern_begin = 0 +// pattern_end = 9 +// one_setup = ON +// no_initialization = ON +// pattern_checksum = 94986 +// End_Verify_Section + +`define SIM_INSTANCE_NAME cpu_inst + + +`timescale 1ns / 1ns + +module cpu_cpu_patterns_serial_v_ctl; + +integer _wrote_fail; +integer _write_DIAG_file; +integer _DIAG_file_header; +integer _diag_file; +integer _diag_chain_header; +integer _diag_scan_header; +integer _last_fail_pattern; +integer _fail_pattern_cnt; +integer _write_MASK_file; +integer _MASK_file_header; +integer _mask_file; +integer _par_shift_cnt; +integer _chain_test_; +integer _compare_fail; +integer _bit_count; +integer _report_bit_cnt; +integer _miscompare_limit; +integer _found_fail; +integer _found_fail_per_cycle; +integer _allow_bad_message_index; +reg[11:0] _found_fail_obus; +integer _end_vec_file_ok; +integer _cycle_count, _save_cycle_count; +integer _pattern_count, _repeat_count_nest[0:8], _repeat_count, _message_index; +integer _index, _scan_index, _file_cnt, _max_index, _vec_pat_count, _save_index[0:8]; +integer _repeat_depth; +integer _file_check; +integer _run_testsetup; +integer _in_testsetup; +integer _start_pat; +integer _end_pat; +integer _end_after_setup; +integer _no_setup; +integer _save_state; +integer _restart_state; +integer _in_restart; +integer _override_cfg; +integer _in_range; +integer _do_compare; +integer _in_chaintest; +integer _pat_num; +integer _skipped_patterns; +integer _end_simulation; +integer _config_file; +integer _fstat; +integer _max_file_cnt; +reg[256*8:1] _vec_file_name; +reg[256*8:1] _cfg_file_name; +integer _scan_shift_count; +reg[12:0] _ibus; +reg[11:0] _exp_obus, _msk_obus; +wire[11:0] _sim_obus; +reg[2:0] _pat_type; +reg _tp_num; +reg mgcdft_save_signal, mgcdft_restart_signal; +reg[45:0] vect; + +wire \btn[6] , \btn[5] , \btn[4] , \btn[3] , \btn[2] , \btn[1] , \btn[0] , + clk_25mhz, scan_en, SI_1, SI_2, SI_3, SI_4, \led[7] , \led[6] , + \led[5] , \led[4] , \led[3] , \led[2] , \led[1] , \led[0] , SO_1, + SO_2, SO_3, SO_4; + +event before_finish; +assign \btn[6] = _ibus[12]; +assign \btn[5] = _ibus[11]; +assign \btn[4] = _ibus[10]; +assign \btn[3] = _ibus[9]; +assign \btn[2] = _ibus[8]; +assign \btn[1] = _ibus[7]; +assign \btn[0] = _ibus[6]; +assign clk_25mhz = _ibus[5]; +assign scan_en = _ibus[4]; +assign SI_1 = _ibus[3]; +assign SI_2 = _ibus[2]; +assign SI_3 = _ibus[1]; +assign SI_4 = _ibus[0]; + +assign _sim_obus[11] = \led[7] ; +assign _sim_obus[10] = \led[6] ; +assign _sim_obus[9] = \led[5] ; +assign _sim_obus[8] = \led[4] ; +assign _sim_obus[7] = \led[3] ; +assign _sim_obus[6] = \led[2] ; +assign _sim_obus[5] = \led[1] ; +assign _sim_obus[4] = \led[0] ; +assign _sim_obus[3] = SO_1; +assign _sim_obus[2] = SO_2; +assign _sim_obus[1] = SO_3; +assign _sim_obus[0] = SO_4; + +// Change Path Variables & Get Argument +integer _change_path; +integer _change_out_path; +reg[512*8:1] _new_path; +reg[512*8:1] _new_out_path; +reg[512*8:1] _new_filename; +reg[512*8:1] _vcd_dump_file_name; +reg[512*8:1] _utvcd_dump_file_name; +reg[512*8:1] _fsdb_dump_file_name; +reg[512*8:1] _qwave_dump_file_name; +reg[512*8:1] _tmp_filename; +initial begin + _change_path = 0; + _change_out_path = 0; + if ($value$plusargs("NEWPATH=%s", _new_path)) begin + $display("Found New Path %0s\n", _new_path); + _change_path = 1; + end + if ($value$plusargs("NEWOUTPATH=%s", _new_out_path)) begin + $display("Found New Out Path %0s\n", _new_out_path); + _change_out_path = 1; + end + +`ifdef VCD + $sformat(_vcd_dump_file_name, "cpu_patterns_serial.v.dump"); + if(_change_out_path) begin + $sformat(_vcd_dump_file_name, "%0s/%0s", _new_out_path, _vcd_dump_file_name); + end + $dumpfile(_vcd_dump_file_name); + $dumpvars; +`endif + +`ifdef UTVCD + $sformat(_utvcd_dump_file_name, "cpu_patterns_serial.v.dump"); + if(_change_out_path) begin + $sformat(_utvcd_dump_file_name, "%0s/%0s", _new_out_path, _utvcd_dump_file_name); + end + $dumpfile(_utvcd_dump_file_name); + $vtDump; + $dumpvars; +`endif + +`ifdef debussy + $sformat(_fsdb_dump_file_name, "cpu_patterns_serial.v.fsdb"); + if(_change_out_path) begin + $sformat(_fsdb_dump_file_name, "%0s/%0s", _new_out_path, _fsdb_dump_file_name); + end + $fsdbDumpfile(_fsdb_dump_file_name); + $fsdbDumpvars; +`endif + +`ifdef QWAVE + $sformat(_qwave_dump_file_name, "cpu_patterns_serial.v.qwave.db"); + if(_change_out_path) begin + $sformat(_qwave_dump_file_name, "%0s/%0s", _new_out_path, _qwave_dump_file_name); + end + $qwavedb_dumpvars_filename(_qwave_dump_file_name); + $qwavedb_dumpvars; +`endif +end + +reg /* sparse */[47:0] _nam_obus[11:0]; +initial begin + if(_change_path) begin + $sformat(_new_filename,"%0s/cpu_patterns_serial.v.po.name",_new_path); + $display("Loading %0s\n", _new_filename ); + $readmemh(_new_filename,_nam_obus,11,0); + end + else begin + $display("Loading cpu_patterns_serial.v.po.name"); + $readmemh("cpu_patterns_serial.v.po.name",_nam_obus,11,0); + end +end + + +// Declare Wires for tracking Vector Type +reg[3:0] _MGCDFT_VECTYPE ; +reg[160:0] _procedure_string ; +reg mgcdft_test_setup, mgcdft_load_unload, mgcdft_shift, + mgcdft_single_shift, mgcdft_shift_extra, + mgcdft_shadow_control, mgcdft_master_observe, + mgcdft_shadow_observe, mgcdft_skew_load, + mgcdft_seq_transparent, mgcdft_launch_capture, + mgcdft_clock_proc, mgcdft_test_end, mgcdft_unknown; + +event set_vector_type; +always @(_MGCDFT_VECTYPE) begin + assign mgcdft_test_setup = 1'b0; + assign mgcdft_load_unload = 1'b0; + assign mgcdft_shift = 1'b0; + assign mgcdft_single_shift = 1'b0; + assign mgcdft_shift_extra = 1'b0; + assign mgcdft_shadow_control = 1'b0; + assign mgcdft_master_observe = 1'b0; + assign mgcdft_shadow_observe = 1'b0; + assign mgcdft_skew_load = 1'b0; + assign mgcdft_seq_transparent = 1'b0; + assign mgcdft_launch_capture = 1'b0; + assign mgcdft_clock_proc = 1'b0; + assign mgcdft_test_end = 1'b0; + assign mgcdft_unknown = 1'b0; + case (_MGCDFT_VECTYPE) + 4'b0001: begin + assign mgcdft_test_setup = 1'b1; + _procedure_string = "TEST_SETUP"; + _scan_shift_count = 0; + end + 4'b0010: begin + assign mgcdft_load_unload = 1'b1; + _procedure_string = "LOAD"; + _scan_shift_count = 0; + end + 4'b0011: begin + assign mgcdft_shift = 1'b1; + _procedure_string = "SHIFT"; + if(!(_scan_shift_count)) begin + _scan_shift_count = 1; + end + end + 4'b0100: begin + assign mgcdft_single_shift = 1'b1; + _procedure_string = "SINGLE_SHIFT"; + if(!(_scan_shift_count)) begin + _scan_shift_count = 1; + end + end + 4'b0101: begin + assign mgcdft_shift_extra = 1'b1; + _procedure_string = "SHIFT_EXTRA"; + _scan_shift_count = 0; + end + 4'b0110: begin + assign mgcdft_shadow_control = 1'b1; + _procedure_string = "SHADOW_CONTROL"; + _scan_shift_count = 0; + end + 4'b0111: begin + assign mgcdft_master_observe = 1'b1; + _procedure_string = "MASTER_OBSERVE"; + _scan_shift_count = 0; + end + 4'b1000: begin + assign mgcdft_shadow_observe = 1'b1; + _procedure_string = "SHADOW_OBSERVE"; + _scan_shift_count = 0; + end + 4'b1001: begin + assign mgcdft_skew_load = 1'b1; + _procedure_string = "SKEW_LOAD"; + _scan_shift_count = 0; + end + 4'b1010: begin + assign mgcdft_seq_transparent = 1'b1; + _procedure_string = "SEQ_TRANSPARENT"; + _scan_shift_count = 0; + end + 4'b1011: begin + assign mgcdft_launch_capture = 1'b1; + _procedure_string = "LAUNCH_CAPTURE"; + _scan_shift_count = 0; + end + 4'b1101: begin + assign mgcdft_clock_proc = 1'b1; + _procedure_string = "CLOCK_PROC"; + _scan_shift_count = 0; + end + 4'b1111: begin + assign mgcdft_test_end = 1'b1; + _procedure_string = "TEST_END"; + _scan_shift_count = 0; + end + 4'b0000: begin + assign mgcdft_unknown = 1'b1; + _procedure_string = "UNKNOWN"; + _scan_shift_count = 0; + end + default: begin + assign mgcdft_unknown = 1'b1; + _procedure_string = "UNKNOWN"; + _scan_shift_count = 0; + end + endcase +end + +event compare_exp_sim_obus; +always @(compare_exp_sim_obus) begin + _found_fail = 0; + if (_do_compare) begin + if (_exp_obus !== _sim_obus) begin + for(_bit_count = 0; + ((_bit_count < 12)&&(_found_fail==0)); + _bit_count =_bit_count +1) begin + if ((_msk_obus[_bit_count] === 1'b1) && + (_exp_obus[_bit_count] !== _sim_obus[_bit_count])) begin + _found_fail = 1; + _found_fail_per_cycle = 1; + _found_fail_obus[_bit_count] = 1'b1; + end + end + end + if (_found_fail == 1) begin + $write($realtime, "ns: Simulated response %b pattern %d cycle %d\n",_sim_obus,_pattern_count,_cycle_count); + $write($realtime, "ns: Expected response %b pattern %d cycle %d\n",_exp_obus,_pattern_count,_cycle_count); + for(_bit_count = 0; + ((_bit_count < 12)&&((_miscompare_limit==0)||(_compare_fail<=_miscompare_limit))); + _bit_count =_bit_count +1) begin + if ((_msk_obus[_bit_count] === 1'b1) && + (_exp_obus[_bit_count] !== _sim_obus[_bit_count])) begin + _found_fail_obus[_bit_count] = 1'b1; + $write($realtime, "ns: Mismatch at pin %d name %s, Simulated %b, Expected %b\n",_bit_count,_nam_obus[_bit_count],_sim_obus[_bit_count],_exp_obus[_bit_count]); + if (_write_MASK_file == 0) begin + if (_scan_shift_count != 0) begin + case (_bit_count) // Scan Chain Failure + 3: begin + $write($realtime, "ns: Mismatch on chain: unwrapped_chain1 cell: %d\n", (_scan_shift_count-1)); + end + 2: begin + $write($realtime, "ns: Mismatch on chain: unwrapped_chain2 cell: %d\n", (_scan_shift_count-1)); + end + 1: begin + $write($realtime, "ns: Mismatch on chain: unwrapped_chain3 cell: %d\n", (_scan_shift_count-1)); + end + 0: begin + $write($realtime, "ns: Mismatch on chain: unwrapped_chain4 cell: %d\n", (_scan_shift_count-1)); + end + endcase + end // _scan_shift_count + end + if (_write_DIAG_file == 1) begin + if (_DIAG_file_header == 0) begin + if ((_start_pat > -1) && (_end_pat > -1)) begin + $sformat(_tmp_filename, "cpu_patterns_serial.v_%0d_%0d.fail", + _start_pat, _end_pat); + end + else if (_start_pat > -1) begin + $sformat(_tmp_filename, "cpu_patterns_serial.v_%0d.fail", + _start_pat); + end + else if (_end_pat > -1) begin + $sformat(_tmp_filename, "cpu_patterns_serial.v__%0d.fail", + _end_pat); + end + else begin + $sformat(_tmp_filename, "cpu_patterns_serial.v.fail"); + end + if(_change_out_path) begin + $sformat(_tmp_filename, "%0s/%0s", _new_out_path, _tmp_filename); + end + _diag_file = $fopen(_tmp_filename); + if (_diag_file == 0) begin + $display("ERROR: Couldn't open .fail file %0s, simulation aborted\n", _tmp_filename); + ->before_finish; + #0; + $finish; + end + if(_change_out_path) begin + $fwrite(_diag_file, "// This File is simulation generated (%0s/cpu_patterns_serial.v)\n", _new_out_path); + end + else begin + $fwrite(_diag_file, "// This File is simulation generated (cpu_patterns_serial.v)\n"); + end + $fwrite(_diag_file, "format cycle\n"); + $fwrite(_diag_file, " failures_begin\n"); + $fwrite(_diag_file, "//cycle_number PO_name expected_value simulated_value "); + $fwrite(_diag_file, "pattern_id chain_name cell_number\n\n"); + _DIAG_file_header = 1; + end + if ((_pattern_count == _last_fail_pattern) && (_pattern_count == 0)) begin + _fail_pattern_cnt = 1; + end + if (_pattern_count > _last_fail_pattern) begin + _fail_pattern_cnt = _fail_pattern_cnt + 1; + _last_fail_pattern = _pattern_count; + end + + $fwrite(_diag_file, "%d %s ", _cycle_count, _nam_obus[_bit_count]); + case ( _exp_obus[_bit_count] ) + 1'b1: begin + $fwrite(_diag_file, " H"); + end + 1'b0: begin + $fwrite(_diag_file, " L"); + end + 1'bZ: begin + $fwrite(_diag_file, " Z"); + end + endcase + case ( _sim_obus[_bit_count] ) + 1'b1: begin + $fwrite(_diag_file, " H // Pattern %d ", _pattern_count); + end + 1'b0: begin + $fwrite(_diag_file, " L // Pattern %d ", _pattern_count); + end + 1'bZ: begin + $fwrite(_diag_file, " Z // Pattern %d ", _pattern_count); + end + 1'bX: begin + $fwrite(_diag_file, " X // Pattern %d ", _pattern_count); + end + endcase + if (_scan_shift_count == 0) begin + $fwrite(_diag_file, ", simulation_time=%.0f\n", $realtime); + end // EndIf _ScanShift_count + if (_scan_shift_count != 0) begin + case (_bit_count) // Scan Chain Failure + 3: begin + $fwrite(_diag_file, "chain: unwrapped_chain1 cell: %d, simulation_time=%.0f\n", (_scan_shift_count-1), $realtime); + end + 2: begin + $fwrite(_diag_file, "chain: unwrapped_chain2 cell: %d, simulation_time=%.0f\n", (_scan_shift_count-1), $realtime); + end + 1: begin + $fwrite(_diag_file, "chain: unwrapped_chain3 cell: %d, simulation_time=%.0f\n", (_scan_shift_count-1), $realtime); + end + 0: begin + $fwrite(_diag_file, "chain: unwrapped_chain4 cell: %d, simulation_time=%.0f\n", (_scan_shift_count-1), $realtime); + end + endcase + end // EndIf _ScanShift_count + end // EndIf _write_DIAG_file + if (_write_MASK_file == 1) begin + if (_MASK_file_header == 0) begin + if ((_start_pat > -1) && (_end_pat > -1)) begin + $sformat(_tmp_filename, "cpu_patterns_serial.v_%0d_%0d.mask", + _start_pat, _end_pat); + end + else if (_start_pat > -1) begin + $sformat(_tmp_filename, "cpu_patterns_serial.v_%0d.mask", + _start_pat); + end + else if (_end_pat > -1) begin + $sformat(_tmp_filename, "cpu_patterns_serial.v__%0d.mask", + _end_pat); + end + else begin + $sformat(_tmp_filename, "cpu_patterns_serial.v.mask"); + end + if(_change_out_path) begin + $sformat(_tmp_filename, "%0s/%0s", _new_out_path, _tmp_filename); + end + _mask_file = $fopen(_tmp_filename); + if (_mask_file == 0) begin + $display("ERROR: Couldn't open .mask file %0s, simulation aborted\n", _tmp_filename); + ->before_finish; + #0; + $finish; + end + $fwrite(_mask_file, "%s\n%s\n", "type mask", ""); + _MASK_file_header = 1; + end + _wrote_fail = 0; + if (_scan_shift_count != 0) begin + case (_bit_count) // Scan Chain Failure + 3: begin + $write($realtime, "ns: Mismatch on chain: unwrapped_chain1 cell: %d\n", (_scan_shift_count-1)); + if (_chain_test_ == 0) begin + $fwrite(_mask_file, "%d %s %d\n", + _pattern_count, "unwrapped_chain1", (_scan_shift_count-1)); + _wrote_fail = 1; + end + if (_chain_test_ == 1) begin + $fwrite(_mask_file, "// %d %s %d\n", + _pattern_count,"unwrapped_chain1", (_scan_shift_count-1)); + _wrote_fail = 1; + end + end + 2: begin + $write($realtime, "ns: Mismatch on chain: unwrapped_chain2 cell: %d\n", (_scan_shift_count-1)); + if (_chain_test_ == 0) begin + $fwrite(_mask_file, "%d %s %d\n", + _pattern_count, "unwrapped_chain2", (_scan_shift_count-1)); + _wrote_fail = 1; + end + if (_chain_test_ == 1) begin + $fwrite(_mask_file, "// %d %s %d\n", + _pattern_count,"unwrapped_chain2", (_scan_shift_count-1)); + _wrote_fail = 1; + end + end + 1: begin + $write($realtime, "ns: Mismatch on chain: unwrapped_chain3 cell: %d\n", (_scan_shift_count-1)); + if (_chain_test_ == 0) begin + $fwrite(_mask_file, "%d %s %d\n", + _pattern_count, "unwrapped_chain3", (_scan_shift_count-1)); + _wrote_fail = 1; + end + if (_chain_test_ == 1) begin + $fwrite(_mask_file, "// %d %s %d\n", + _pattern_count,"unwrapped_chain3", (_scan_shift_count-1)); + _wrote_fail = 1; + end + end + 0: begin + $write($realtime, "ns: Mismatch on chain: unwrapped_chain4 cell: %d\n", (_scan_shift_count-1)); + if (_chain_test_ == 0) begin + $fwrite(_mask_file, "%d %s %d\n", + _pattern_count, "unwrapped_chain4", (_scan_shift_count-1)); + _wrote_fail = 1; + end + if (_chain_test_ == 1) begin + $fwrite(_mask_file, "// %d %s %d\n", + _pattern_count,"unwrapped_chain4", (_scan_shift_count-1)); + _wrote_fail = 1; + end + end + endcase + end // _scan_shift_count + if (_wrote_fail == 0 ) begin // not Scan Chain Failure + if (_chain_test_ == 0) begin + $fwrite(_mask_file, "%d %s\n", _pattern_count,_nam_obus[_bit_count]); + end + if (_chain_test_ == 1) begin + $fwrite(_mask_file, "// %d %s\n", _pattern_count,_nam_obus[_bit_count]); + end + end + end// if MaskFile + end + end + _compare_fail = _compare_fail + 1; + end + end // if _do_compare +end + +reg[45:0] mem [0:2917775]; +cpu cpu_inst (.btn({\btn[6] , \btn[5] , \btn[4] + , \btn[3] , \btn[2] , \btn[1] , \btn[0] + }), .clk_25mhz(clk_25mhz), .scan_en(scan_en), .SI_1(SI_1), + .SI_2(SI_2), .SI_3(SI_3), .SI_4(SI_4), .led({\led[7] + , \led[6] , \led[5] , \led[4] , \led[3] , \led[2] + , \led[1] , \led[0] }), .SO_1(SO_1), .SO_2(SO_2), + .SO_3(SO_3), .SO_4(SO_4)); + +initial begin +_in_restart = 0; +while (_in_restart < 2) begin +_in_restart = _in_restart + 1; +_restart_state = -1; +if ($value$plusargs("RESTART=%d", _restart_state)) begin + $display(" Found RESTART %d", _restart_state); +end + +if ((_in_restart < 2) || (_restart_state == 1)) begin +mgcdft_save_signal = 1'b0; +mgcdft_restart_signal = 1'b0; +if (_restart_state == 1) begin + #0; + mgcdft_restart_signal = 1'b1; +// $display("Reading checkpoint cpu_patterns_serial.v.dat"); +// $restart("cpu_patterns_serial.v.dat"); +end + +#0; +mgcdft_save_signal = 1'b0; +mgcdft_restart_signal = 1'b0; +_compare_fail = 0; +_pattern_count = 0; +_cycle_count = 0; +_save_cycle_count = 0; +_write_DIAG_file = 0; // change to 1, to generate file +_write_MASK_file = 0; // change to 1, to generate file +_wrote_fail = 0; +_DIAG_file_header = 0; +_diag_file = 0; +_diag_chain_header = 0; +_diag_scan_header = 0; +_fail_pattern_cnt = 0; +_last_fail_pattern = 0; +_MASK_file_header = 0; +_mask_file = 0; +_chain_test_ = 0; +_par_shift_cnt = 0; +_report_bit_cnt = 0; +// Limit # of miscompares before aborting simulation (non-zero) +_miscompare_limit = 0; +_end_vec_file_ok = 0; +_scan_shift_count = 0; +_run_testsetup = 0; +_in_testsetup = 0; +_start_pat = -1; +_end_pat = -1; +_end_after_setup = -1; +_no_setup = -1; +_save_state = -1; +_override_cfg = 0; +_pat_num = -1; +_in_range = 1; +_do_compare = 1; +_in_chaintest = 0; + +_skipped_patterns = 0; + +_end_simulation = 0; + +if ($value$plusargs("STARTPAT=%d", _start_pat)) begin + if (_start_pat > -1) begin + $display(" Found Start pattern number %d", _start_pat); + _in_range = 0; + _do_compare = 0; + end + else begin + $display(" Ignoring negative Start pattern number %d", _start_pat); + _start_pat = -1; + end +end +if ($value$plusargs("ENDPAT=%d", _end_pat)) begin + if (_end_pat > -1) begin + $display(" Found End pattern number %d", _end_pat); + end + else begin + $display(" Ignoring negative End pattern number %d", _end_pat); + _end_pat = -1; + end +end + +if ($value$plusargs("CHAINTEST=%d", _in_chaintest)) begin + if (_in_chaintest) begin + $display(" Found ChainTest identifier %d", _in_chaintest); + end +end + +if ($value$plusargs("END_AFTER_SETUP=%d", _end_after_setup)) begin + $display(" Found End after setup %d", _end_after_setup); + if (_end_after_setup > 0) begin + _end_pat = 0; + _in_chaintest = 1; + end +end + +if ($value$plusargs("SKIP_SETUP=%d", _no_setup)) begin + $display(" Found Skip setup %d", _no_setup); + if (_no_setup > 0) begin + if (_start_pat == -1) begin + _start_pat = 0; + _in_chaintest = 1; + end + _run_testsetup = 0; + _in_range = 0; + _do_compare = 0; + end +end + +if ($value$plusargs("SAVE=%d", _save_state)) begin + $display(" Found SAVE %d", _save_state); +end + +if ($value$plusargs("CONFIG=%0s", _cfg_file_name)) begin + $display(" Found CONFIG identifier %0s", _cfg_file_name); + _override_cfg = 1; +end +else begin + _cfg_file_name = "cpu_patterns_serial.v.cfg"; +end + +if ((_end_pat != -1) && (_end_pat < _start_pat)) begin + _start_pat = -1; + _in_range = 1; + _do_compare = 1; + $display("STARTPAT less than ENDPAT, ignoring STARTPAT "); +end +_allow_bad_message_index = 0; +if ($value$plusargs("ALLOW_BAD_MESSAGE_INDEX=%d", _allow_bad_message_index)) begin + $display(" Found ALLOW_BAD_MESSAGE_INDEX %d", _allow_bad_message_index); +end + +// read vector config file +if(_override_cfg) begin + _config_file = $fopen(_cfg_file_name, "r"); +end +else begin +if(_change_path) begin + $sformat(_new_filename,"%0s/cpu_patterns_serial.v.cfg",_new_path); + _config_file = $fopen(_new_filename, "r"); +end +else begin + _config_file = $fopen("cpu_patterns_serial.v.cfg", "r"); +end + +end + +if (_config_file == 0) begin + $display("ERROR: Couldn't open configuration file, simulation aborted\n"); + ->before_finish; + #0; + $finish; +end +_fstat = 0; +if (_start_pat != -1) begin + if (_no_setup > 0) begin + $display("BEGIN pattern read loop Skip test_setup\n"); + end + else if (_in_chaintest == 0) begin + if (_end_pat != -1) begin + $display("BEGIN pattern read loop Start pattern (%d) End pattern (%d)\n", +_start_pat,_end_pat); + end + else begin + $display("BEGIN pattern read loop Start pattern (%d) \n", +_start_pat); + end + end + else begin + if (_end_pat != -1) begin + $display("BEGIN pattern read loop Start chain pattern (%d) End chain pattern (%d)\n", +_start_pat,_end_pat); + end + else begin + $display("BEGIN pattern read loop Start chain pattern (%d)\n", +_start_pat); + end + end +end +else if (_end_pat != -1) begin + if (_end_after_setup > 0) begin + $display("BEGIN pattern read loop End after test_setup\n"); + end + else if (_in_chaintest == 0) begin + $display("BEGIN pattern read loop End pattern (%d)\n", _end_pat); + end + else begin + $display("BEGIN pattern read loop End chain pattern (%d)\n", _end_pat); + end +end + +// begin pattern read loop +while (!$feof(_config_file) && (!_end_simulation)) +begin + _fstat = $fscanf(_config_file, "%s", _vec_file_name); + _fstat = $fscanf(_config_file, "%d", _max_index); + if (_fstat != -1) begin + _fstat = $fscanf(_config_file, "%d", _vec_pat_count); + if (_fstat == -1) begin + _vec_pat_count = -1; + end + // skip .vec file if _start_pat greater than this + if ((_start_pat != -1) && !_in_range && (_vec_pat_count != -1) && + !_in_testsetup && !_in_chaintest && + ((_pat_num + _vec_pat_count) < _start_pat)) begin + _max_index = -1; + if (_chain_test_) begin + _pattern_count = 0; + _pat_num = 0; + end + _pat_num = _pat_num + _vec_pat_count; + _skipped_patterns = _skipped_patterns + _vec_pat_count; + _end_vec_file_ok = 1; + _chain_test_ = 0; + $display("Skipping %0s\n", _vec_file_name); + end + else begin + if(_change_path) begin + $sformat(_new_filename,"%0s/%0s",_new_path, _vec_file_name); + $display("Loading %0s\n", _new_filename ); + $readmemb(_new_filename, mem, 0, _max_index); + end + else begin + $display("Loading %0s\n", _vec_file_name); + $readmemb(_vec_file_name, mem, 0, _max_index); + end + _end_vec_file_ok = 0; + end + end + else begin + _max_index = -1; + _vec_pat_count = -1; + end + _scan_index = 0; + _repeat_count_nest[0] = 0; + _repeat_count = 0; + _repeat_depth = 0; + _message_index = 0; + _save_index[0] = 0; + _found_fail_obus =12'b000000000000; + for (_index=0; _index <= _max_index; _index = _index+1) + begin + vect = mem[_index]; + _exp_obus=12'bXXXXXXXXXXXX; + _msk_obus=12'b000000000000; + _MGCDFT_VECTYPE = vect[3:0]; + _pat_type = vect[6:4]; + _tp_num = vect[7]; + // Range Check + if ((_start_pat != -1) && ((_start_pat != 0) || (!_in_testsetup)) && + ((!_chain_test_)||(_chain_test_ && _in_chaintest))) begin + if (!_chain_test_ && _in_chaintest && !_in_range && !_in_testsetup) begin + _in_range = 1; + _do_compare = 1; + end + if ((_pat_num == _start_pat) && !_in_range) begin + _in_range = 1; + _do_compare = 0; + _pattern_count = (_pat_num - 1); + if (_pattern_count < 0) begin + _pattern_count = 0; + end + end + if (_pat_num == (_start_pat + 1)) begin + _do_compare = 1; + end + end + + if ((_end_pat != -1) && (_pattern_count > _end_pat) && + ((!_chain_test_)||(_chain_test_ && _in_chaintest))) begin + // simulation complete, exit + _index = _max_index + 1; + _end_vec_file_ok = 1; + _end_simulation = 1; + end + if ((_index > 0) && (_end_pat != -1) && !_chain_test_ && _in_chaintest && + !_run_testsetup) begin + // simulation complete, exit + _index = _max_index + 1; + _end_vec_file_ok = 1; + _end_simulation = 1; + end + if ((_in_range) || (_run_testsetup)) begin + case (_pat_type) + 3'b000: begin // end vector + _index = _max_index + 1; + end // end vector + 3'b001: ;// skip scan vector, handled by shift vector + 3'b010: begin // broadside vector + _found_fail_per_cycle = 0; + _found_fail_obus =12'b000000000000; + if (vect[8] == 1'b1) begin + _pattern_count = _pattern_count + 1; + _par_shift_cnt = 0; + if ((!_do_compare) && (_pattern_count >= _start_pat)) begin + _do_compare = 1; + end + if ((_end_pat != -1) && (_pattern_count > _end_pat) && + ((!_chain_test_)||(_chain_test_ && _in_chaintest))) begin + // simulation complete, exit + _index = _max_index + 1; + _end_vec_file_ok = 1; + _end_simulation = 1; + _in_range = 0; + end + end + if (vect[8] === 1'bz) begin + _pattern_count = 0; + _par_shift_cnt = 0; + end + if(_scan_shift_count) begin + _scan_shift_count = _scan_shift_count + 1; + end + case (_tp_num) + 1'b1: begin // timeplate 1 - gen_tp1 + _ibus[5] = 1'b0; + _ibus[12:6] = vect[45:39]; + _ibus[4:0] = vect[37:33]; + + #10; // 10 ns + _exp_obus[11:0] = vect[32:21]; + _msk_obus[11:0] = vect[20:9]; + #0; + ->compare_exp_sim_obus; + if ((_miscompare_limit)&&(_compare_fail>=_miscompare_limit)) begin + $display("ERROR: exceeded miscompare limit(%d), exiting simulation",_miscompare_limit); + _end_vec_file_ok = 1; + if (_DIAG_file_header == 1) begin + $fwrite(_diag_file, " failures_end\n"); + $fwrite(_diag_file, " failure_buffer_limit_reached none\n"); + if (_diag_scan_header==1) begin + $fwrite(_diag_file, "last_cycle_applied %d\n", (_cycle_count-1)); + end + $fwrite(_diag_file, "total_cycles 3339\n"); + $fwrite(_diag_file, "// failing_patterns=%d simulated_patterns=%d", _fail_pattern_cnt, (_pattern_count+1)); + $fwrite(_diag_file, " simulation_time=", $realtime, ";\n"); + $fwrite(_diag_file, "failure_file_end\n"); + $fclose(_diag_file); + end + ->before_finish; + #0; + $finish; + end + + #10; // 20 ns + _ibus[5] = vect[38]; + + #10; // 30 ns + _ibus[5] = 1'b0; + + #10; // 40 ns + end // timeplate 1 - gen_tp1 + default: begin + $display("ERROR: corrupt timeplate number\n"); + ->before_finish; + #0; + $finish; + end + endcase // _tp_num + _cycle_count = _cycle_count + 1; + _par_shift_cnt = 0; + end // broadside vector + 3'b011: begin // status message vector + _message_index = vect[38:7]; + case (_message_index) + 0: begin + $display("Begin chain test\n"); + _chain_test_ = 1; + _diag_chain_header = 0; + end + 1: begin + _chain_test_ = 0; + if (_diag_chain_header) begin + $fwrite(_diag_file, " last_cycle_applied %d\n", _cycle_count); + end + _diag_scan_header = 0; + if ((_start_pat > -1) || (_end_pat > -1)) begin + if (_pat_num > -1) begin + $display("Simulated chain pattern %d\n",_pat_num); + end + end + _pat_num = -1; + _pattern_count = 0; + $display("End chain test\n"); + end + 2: begin + $display("Status update: simulated through pattern %d\n",_pattern_count); + end + 3: begin + _end_vec_file_ok = 1; + if ((_start_pat > -1) || (_end_pat > -1)) begin + if (_pat_num > -1) begin + if (!_chain_test_) begin + $display("Simulated pattern %d\n",_pat_num); + end + end + end + end + 4: begin // start of atpg pattern + if ((_start_pat > -1) || (_end_pat > -1)) begin + if (_pat_num > -1) begin + if (_chain_test_) begin + $display("Simulated chain pattern %d\n",_pat_num); + end + else begin + $display("Simulated pattern %d\n",_pat_num); + end + end + end + _pat_num = _pat_num + 1; + _run_testsetup = 0; + _in_testsetup = 0; + if (_end_after_setup > 0) begin + //simulation complete, exit + _index = _max_index + 1; + _end_vec_file_ok = 1; + _end_simulation = 1; + _in_range = 0; + end + end + default: begin + $display("ERROR: corrupt message index\n"); + if (_allow_bad_message_index != 1) begin + ->before_finish; + #0; + $finish; + end + end + endcase // _message_index + end + default: begin + $display("ERROR: corrupt vector number\n"); + ->before_finish; + #0; + $finish; + end + endcase + end // if in_range + else begin + case (_pat_type) // _pat_type = vect[6:4]; + 3'b011: begin // status message vector + _message_index = vect[38:7]; + case (_message_index) + 0: begin + _chain_test_ = 1; + _diag_chain_header = 0; + end + 1: begin + if (_pat_num > -1) begin + $display("Skipped chain pattern %d\n",_pat_num); + end + _chain_test_ = 0; + _pat_num = -1; + $display("End chain test\n"); + end + 3: begin + _end_vec_file_ok = 1; + if (_pat_num > -1) begin + if (!_chain_test_) begin + $display("Skipped pattern %d\n",_pat_num); + end + end + end + 4: begin // start of atpg pattern + if (_pat_num > -1) begin + if (!_chain_test_) begin + _skipped_patterns = _skipped_patterns + 1; + end + end + if (_pat_num > -1) begin + if (_chain_test_) begin + $display("Skipped chain pattern %d\n",_pat_num); + end + else begin + $display("Skipped pattern %d\n",_pat_num); + end + end + _pat_num = _pat_num + 1; + _run_testsetup = 0; + _in_testsetup = 0; + if (_end_after_setup > 0) begin + //simulation complete, exit + _index = _max_index + 1; + _end_vec_file_ok = 1; + _end_simulation = 1; + _in_range = 0; + end + end + default: begin + // Skip + end + endcase // _message_index + end + default: begin + // Skip + end + endcase + end // else !_in_range + end // index loop +end // file_cnt loop + +if (_save_state == 1) begin + #1; + mgcdft_save_signal = 1'b1; +// $display("Writing checkpoint cpu_patterns_serial.v.dat"); +// $save("cpu_patterns_serial.v.dat"); + if (_in_restart == 2) begin + _in_restart = 1; + end + #1; + $stop; +end +end +end // while _in_restart + if (_DIAG_file_header == 1) begin + $fwrite(_diag_file, " failures_end\n"); + $fwrite(_diag_file, " failure_buffer_limit_reached none\n"); + if (_diag_scan_header==1) begin + $fwrite(_diag_file, "last_cycle_applied %d\n", (_cycle_count-1)); + end + $fwrite(_diag_file, "total_cycles 3339\n"); + $fwrite(_diag_file, "// failing_patterns=%d simulated_patterns=%d", _fail_pattern_cnt, (_pattern_count+1)); + $fwrite(_diag_file, " simulation_time=", $realtime, ";\n"); + $fwrite(_diag_file, "failure_file_end\n"); + $fclose(_diag_file); + end + + +#1; +if (_end_vec_file_ok == 0) begin + $display("ERROR: Pattern file corrupted, simulation aborted\n"); +end +if ((_end_vec_file_ok) && (_compare_fail == 0)) begin + $display("No error between simulated and expected patterns\n"); +end + +if (_compare_fail != 0) begin + $display("Error between simulated and expected patterns\n"); +end + +#1; +->before_finish; +#0; +$finish; +end +endmodule diff --git a/cpu_patterns_serial.v.0.vec b/cpu_patterns_serial.v.0.vec new file mode 100644 index 0000000..a7bd8db --- /dev/null +++ b/cpu_patterns_serial.v.0.vec @@ -0,0 +1,3729 @@ +// +// Verilog format test patterns produced by Tessent Shell 2023.4-p1 +// Filename : cpu_patterns_serial.v.0.vec +// Scan operation : SERIAL +// Idstamp : 2023.4-p1:05e1:d9b6:10:040e +// Fault : STUCK +// Coverage : 25.96(TC) 24.58(FC) +// Date : Thu May 28 18:01:24 2026 +// +// Format of broadside vector: +// PI_bits PO_bits MASK_bits Increment_bit Timeplate_bits(1) PatType_bits(3) +// VecType_bits(4) +// Format of scan vector: +// SI_bits SO_bits MASK_bits PatType_bits(3) + +// Increment_bit - indicates when to increment pattern count +// Timeplate_bits - encodes timeplate number to use +// PatType_bits - encodes pattern type +// VecType_bits - encodes vector type + +// Chain test + +// Chain Pattern 0 +// Begin chain test +000000000000000000000000000000000110000 +000000000000000000000000000001000110000 // Start Pattern (0) MSG +// Simulation Cycle 0 Timestamp 0 ns +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 10 Timestamp 400 ns +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 20 Timestamp 800 ns +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 30 Timestamp 1200 ns +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 40 Timestamp 1600 ns +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 50 Timestamp 2000 ns +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 60 Timestamp 2400 ns +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 70 Timestamp 2800 ns +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 80 Timestamp 3200 ns +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 90 Timestamp 3600 ns +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 100 Timestamp 4000 ns +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 110 Timestamp 4400 ns +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 120 Timestamp 4800 ns +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 130 Timestamp 5200 ns +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 140 Timestamp 5600 ns +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 150 Timestamp 6000 ns +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 160 Timestamp 6400 ns +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 170 Timestamp 6800 ns +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 180 Timestamp 7200 ns +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 190 Timestamp 7600 ns +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 200 Timestamp 8000 ns +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 210 Timestamp 8400 ns +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 220 Timestamp 8800 ns +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 230 Timestamp 9200 ns +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 240 Timestamp 9600 ns +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 250 Timestamp 10000 ns +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX110000XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +XXXXXXX111111XXXXXXXXXXXX000000000000010100011 +ZZZZZZX011111XXXXXXXXXXXX000000000000010101011 +// Last unload +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +// Simulation Cycle 260 Timestamp 10400 ns +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +// Simulation Cycle 270 Timestamp 10800 ns +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +// Simulation Cycle 280 Timestamp 11200 ns +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +// Simulation Cycle 290 Timestamp 11600 ns +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +// Simulation Cycle 300 Timestamp 12000 ns +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +// Simulation Cycle 310 Timestamp 12400 ns +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +// Simulation Cycle 320 Timestamp 12800 ns +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +// Simulation Cycle 330 Timestamp 13200 ns +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +// Simulation Cycle 340 Timestamp 13600 ns +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +// Simulation Cycle 350 Timestamp 14000 ns +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +// Simulation Cycle 360 Timestamp 14400 ns +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +// Simulation Cycle 370 Timestamp 14800 ns +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +// Simulation Cycle 380 Timestamp 15200 ns +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +// Simulation Cycle 390 Timestamp 15600 ns +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +// Simulation Cycle 400 Timestamp 16000 ns +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +// Simulation Cycle 410 Timestamp 16400 ns +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +// Simulation Cycle 420 Timestamp 16800 ns +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +// Simulation Cycle 430 Timestamp 17200 ns +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +// Simulation Cycle 440 Timestamp 17600 ns +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +// Simulation Cycle 450 Timestamp 18000 ns +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +// Simulation Cycle 460 Timestamp 18400 ns +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +// Simulation Cycle 470 Timestamp 18800 ns +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +// Simulation Cycle 480 Timestamp 19200 ns +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +// Simulation Cycle 490 Timestamp 19600 ns +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +// Simulation Cycle 500 Timestamp 20000 ns +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +// Simulation Cycle 510 Timestamp 20400 ns +ZZZZZZX110000XXXXXXXX0000000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +ZZZZZZX111111XXXXXXXX1111000000001111010100011 +// End chain test +000000000000000000000000000000010110000 + +// Scan test block + +// Pattern 0 Cycle 513 Timestamp 20520 ns +000000000000000000000000000001000110000 // Start Pattern (0) MSG +ZZZZZZX110101XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110111XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111010XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111011XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111100XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110011XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110011XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 520 Timestamp 20800 ns +ZZZZZZX110000XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110001XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110110XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111001XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110011XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110101XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110011XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110001XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111111XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111001XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 530 Timestamp 21200 ns +ZZZZZZX111110XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110101XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110001XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111100XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110101XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111110XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110100XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111010XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111111XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110011XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 540 Timestamp 21600 ns +ZZZZZZX110101XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111001XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111110XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111101XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110101XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111110XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111110XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110001XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111110XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111100XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 550 Timestamp 22000 ns +ZZZZZZX110111XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111001XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110100XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110000XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110101XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111000XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110001XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111111XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111110XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110000XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 560 Timestamp 22400 ns +ZZZZZZX110111XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110111XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111010XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111111XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111101XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111100XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110101XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110011XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111110XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111000XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 570 Timestamp 22800 ns +ZZZZZZX111001XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111011XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110110XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111100XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111111XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111011XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111011XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110001XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111110XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110011XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 580 Timestamp 23200 ns +ZZZZZZX110100XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111110XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110011XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111110XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111001XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110010XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111010XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111110XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111001XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110100XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 590 Timestamp 23600 ns +ZZZZZZX111101XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110100XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110110XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111011XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111011XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110101XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110110XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110110XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110110XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111001XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 600 Timestamp 24000 ns +ZZZZZZX110111XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110011XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111101XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111111XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111000XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110101XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111010XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110111XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110011XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111110XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 610 Timestamp 24400 ns +ZZZZZZX111101XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111100XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110001XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110101XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110111XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111110XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110100XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110000XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110101XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111000XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 620 Timestamp 24800 ns +ZZZZZZX110011XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110101XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110011XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111101XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111111XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111111XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111001XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110011XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111101XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111111XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 630 Timestamp 25200 ns +ZZZZZZX110100XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110110XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110010XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110101XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111111XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110001XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110001XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110110XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110100XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110100XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 640 Timestamp 25600 ns +ZZZZZZX111001XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111010XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111001XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110111XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111001XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111101XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110011XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111100XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111101XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110011XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 650 Timestamp 26000 ns +ZZZZZZX111000XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111010XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111011XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110111XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111111XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110010XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110111XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110001XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111100XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110100XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 660 Timestamp 26400 ns +ZZZZZZX110010XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111101XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110111XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110001XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110101XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110101XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111110XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110001XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110011XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111111XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 670 Timestamp 26800 ns +ZZZZZZX111110XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111011XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111111XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111001XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111000XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111101XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111010XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110010XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111010XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111101XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 680 Timestamp 27200 ns +ZZZZZZX111101XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111110XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111000XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111001XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111111XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110111XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110011XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111001XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111001XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111001XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 690 Timestamp 27600 ns +ZZZZZZX111111XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111110XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110101XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110000XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111011XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111100XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111111XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111110XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110100XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111000XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 700 Timestamp 28000 ns +ZZZZZZX110101XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110110XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110100XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110001XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111111XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110101XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110100XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110101XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111111XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111001XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 710 Timestamp 28400 ns +ZZZZZZX111110XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110010XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110101XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111110XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110011XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111000XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111010XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111110XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110111XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111011XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 720 Timestamp 28800 ns +ZZZZZZX111101XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110000XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111001XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111100XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111100XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110110XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110111XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110010XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110101XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111011XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 730 Timestamp 29200 ns +ZZZZZZX110101XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111111XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110101XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110110XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110000XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110100XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110011XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110010XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110011XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111111XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 740 Timestamp 29600 ns +ZZZZZZX111010XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111110XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111000XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111011XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111110XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111010XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111011XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111111XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111101XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111100XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 750 Timestamp 30000 ns +ZZZZZZX111101XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111100XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111110XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111010XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111001XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111011XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111011XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111110XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111110XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111010XXXXXXXXXXXX000000000000010100011 +// Simulation Cycle 760 Timestamp 30400 ns +ZZZZZZX111110XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111111XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111001XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110001XXXXXXXXXXXX000000000000010100011 +ZZZZZZX110000XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111110XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111001XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111000XXXXXXXXXXXX000000000000010100011 +ZZZZZZX111000XXXXXXXXXXXX000000000000010100011 +0001110100011XXXXXXXX0101000000001111Z10101011 +// Pattern 1 Cycle 770 Timestamp 30800 ns +000000000000000000000000000001000110000 // Start Pattern (1) MSG +// Simulation Cycle 770 Timestamp 30800 ns +0001110110111XXXXXXXX0000000000001111010100011 +0001110110101XXXXXXXX0000000000001111010100011 +0001110111010XXXXXXXX0000000000001111010100011 +0001110110000XXXXXXXX0000000000001111010100011 +0001110110111XXXXXXXX0000000000001111010100011 +0001110111001XXXXXXXX0000000000001111010100011 +0001110110111XXXXXXXX0000000000001111010100011 +0001110110001XXXXXXXX0000000000001111010100011 +0001110111111XXXXXXXX0000000000001111010100011 +0001110110001XXXXXXXX0000000000001111010100011 +// Simulation Cycle 780 Timestamp 31200 ns +0001110110011XXXXXXXX0000000000001111010100011 +0001110110001XXXXXXXX0000000000001111010100011 +0001110111111XXXXXXXX0000000000001111010100011 +0001110111111XXXXXXXX0000000000001111010100011 +0001110111001XXXXXXXX0000000000001111010100011 +0001110111100XXXXXXXX0000000000001111010100011 +0001110110100XXXXXXXX0000000000001111010100011 +0001110111110XXXXXXXX0000000000001111010100011 +0001110111111XXXXXXXX0000000000001111010100011 +0001110110010XXXXXXXX0000000000001111010100011 +// Simulation Cycle 790 Timestamp 31600 ns +0001110111001XXXXXXXX0000000000001111010100011 +0001110111101XXXXXXXX0000000000001111010100011 +0001110111101XXXXXXXX0000000000001111010100011 +0001110111110XXXXXXXX0000000000001111010100011 +0001110111111XXXXXXXX0000000000001111010100011 +0001110111110XXXXXXXX0000000000001111010100011 +0001110111001XXXXXXXX0000000000001111010100011 +0001110110011XXXXXXXX0000000000001111010100011 +0001110110100XXXXXXXX0000000000001111010100011 +0001110111011XXXXXXXX0000000000001111010100011 +// Simulation Cycle 800 Timestamp 32000 ns +0001110111111XXXXXXXX0000000000001111010100011 +0001110110011XXXXXXXX0000000000001111010100011 +0001110111110XXXXXXXX0000000000001111010100011 +0001110110000XXXXXXXX0000000000001111010100011 +0001110110010XXXXXXXX0000000000001111010100011 +0001110111010XXXXXXXX0000000000001111010100011 +0001110110101XXXXXXXX0000000000001111010100011 +0001110111101XXXXXXXX0000000000001111010100011 +0001110111001XXXXXXXX0000000000001111010100011 +0001110110101XXXXXXXX0000000000001111010100011 +// Simulation Cycle 810 Timestamp 32400 ns +0001110111101XXXXXXXX0000000000001111010100011 +0001110110011XXXXXXXX0000000000001111010100011 +0001110110100XXXXXXXX0000000000001111010100011 +0001110110000XXXXXXXX0000000000001111010100011 +0001110110101XXXXXXXX0000000000001111010100011 +0001110111011XXXXXXXX0000000000001111010100011 +0001110111011XXXXXXXX0000000000001111010100011 +0001110111011XXXXXXXX0000000000001111010100011 +0001110110101XXXXXXXX0000000000001111010100011 +0001110110010XXXXXXXX0000000000001111010100011 +// Simulation Cycle 820 Timestamp 32800 ns +0001110111111XXXXXXXX0000000000001111010100011 +0001110110000XXXXXXXX0000000000001111010100011 +0001110111011XXXXXXXX0000000000001111010100011 +0001110110101XXXXXXXX0000000000001111010100011 +0001110111101XXXXXXXX0000000000001111010100011 +0001110110001XXXXXXXX0000000000001111010100011 +0001110111000XXXXXXXX0000000000001111010100011 +0001110110000XXXXXXXX0000000000001111010100011 +0001110111100XXXXXXXX0000000000001111010100011 +0001110111111XXXXXXXX0000000000001111010100011 +// Simulation Cycle 830 Timestamp 33200 ns +0001110111111XXXXXXXX0000000000001111010100011 +0001110110111XXXXXXXX0000000000001111010100011 +0001110110110XXXXXXXX0000000000001111010100011 +0001110111100XXXXXXXX0000000000001111010100011 +0001110110110XXXXXXXX0000000000001111010100011 +0001110111101XXXXXXXX0000000000001111010100011 +0001110111011XXXXXXXX0000000000001111010100011 +0001110111011XXXXXXXX0000000000001111010100011 +0001110110101XXXXXXXX0000000000001111010100011 +0001110111001XXXXXXXX0000000000001111010100011 +// Simulation Cycle 840 Timestamp 33600 ns +0001110110010XXXXXXXX0000000000001111010100011 +0001110111001XXXXXXXX0000000000001111010100011 +0001110110000XXXXXXXX0000000000001111010100011 +0001110111110XXXXXXXX0000000000001111010100011 +0001110111010XXXXXXXX0000000000001111010100011 +0001110111011XXXXXXXX0000000000001111010100011 +0001110111000XXXXXXXX0000000000001111010100011 +0001110110101XXXXXXXX0000000000001111010100011 +0001110111110XXXXXXXX0000000000001111010100011 +0001110111011XXXXXXXX0000000000001111010100011 +// Simulation Cycle 850 Timestamp 34000 ns +0001110111101XXXXXXXX0000000000001111010100011 +0001110111011XXXXXXXX0000000000001111010100011 +0001110111101XXXXXXXX0000000000001111010100011 +0001110111001XXXXXXXX0000000000001111010100011 +0001110110110XXXXXXXX0000000000001111010100011 +0001110110011XXXXXXXX0000000000001111010100011 +0001110110101XXXXXXXX0000000000001111010100011 +0001110111100XXXXXXXX0000000000001111010100011 +0001110110100XXXXXXXX0000000000001111010100011 +0001110111111XXXXXXXX0000000000001111010100011 +// Simulation Cycle 860 Timestamp 34400 ns +0001110110111XXXXXXXX0000000000001111010100011 +0001110110110XXXXXXXX0000000000001111010100011 +0001110111010XXXXXXXX0000000000001111010100011 +0001110110100XXXXXXXX0000000000001111010100011 +0001110110101XXXXXXXX0000000000001111010100011 +0001110111101XXXXXXXX0000000000001111010100011 +0001110110001XXXXXXXX0000000000001111010100011 +0001110111100XXXXXXXX0000000000001111010100011 +0001110111111XXXXXXXX0000000000001111010100011 +0001110111101XXXXXXXX0000000000001111010100011 +// Simulation Cycle 870 Timestamp 34800 ns +0001110111000XXXXXXXX0000000000001111010100011 +0001110110101XXXXXXXX0000000000001111010100011 +0001110111111XXXXXXXX0000000000001111010100011 +0001110110111XXXXXXXX0000000000001111010100011 +0001110110001XXXXXXXX0000000000001111010100011 +0001110110001XXXXXXXX0000000000001111010100011 +0001110110011XXXXXXXX0000000000001111010100011 +0001110111111XXXXXXXX0000000000001111010100011 +0001110111001XXXXXXXX0000000000001111010100011 +0001110111100XXXXXXXX0000000000001111010100011 +// Simulation Cycle 880 Timestamp 35200 ns +0001110111101XXXXXXXX0000000000001111010100011 +0001110110011XXXXXXXX0000000000001111010100011 +0001110111011XXXXXXXX0000000000001111010100011 +0001110110011XXXXXXXX0000000000001111010100011 +0001110110011XXXXXXXX0000000000001111010100011 +0001110111010XXXXXXXX0000000000001111010100011 +0001110110111XXXXXXXX0000000000001111010100011 +0001110110000XXXXXXXX0000000000001111010100011 +0001110111100XXXXXXXX0000000000001111010100011 +0001110111110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 890 Timestamp 35600 ns +0001110111101XXXXXXXX0000000000001111010100011 +0001110111000XXXXXXXX0000000000001111010100011 +0001110110001XXXXXXXX0000000000001111010100011 +0001110111010XXXXXXXX0000000000001111010100011 +0001110110011XXXXXXXX0000000000001111010100011 +0001110111011XXXXXXXX0000000000001111010100011 +0001110111011XXXXXXXX0000000000001111010100011 +0001110110100XXXXXXXX0000000000001111010100011 +0001110110100XXXXXXXX0000000000001111010100011 +0001110111110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 900 Timestamp 36000 ns +0001110111110XXXXXXXX0000000000001111010100011 +0001110111100XXXXXXXX0000000000001111010100011 +0001110110010XXXXXXXX0000000000001111010100011 +0001110110010XXXXXXXX0000000000001111010100011 +0001110111111XXXXXXXX0000000000001111010100011 +0001110111001XXXXXXXX0000000000001111010100011 +0001110110001XXXXXXXX0000000000001111010100011 +0001110110010XXXXXXXX0000000000001111010100011 +0001110110100XXXXXXXX0000000000001111010100011 +0001110111011XXXXXXXX0000000000001111010100011 +// Simulation Cycle 910 Timestamp 36400 ns +0001110110111XXXXXXXX0000000000001111010100011 +0001110111011XXXXXXXX0000000000001111010100011 +0001110110000XXXXXXXX0000000000001111010100011 +0001110111010XXXXXXXX0000000000001111010100011 +0001110111110XXXXXXXX0000000000001111010100011 +0001110110010XXXXXXXX0000000000001111010100011 +0001110110111XXXXXXXX0000000000001111010100011 +0001110111010XXXXXXXX0000000000001111010100011 +0001110110011XXXXXXXX0000000000001111010100011 +0001110110101XXXXXXXX0000000000001111010100011 +// Simulation Cycle 920 Timestamp 36800 ns +0001110111011XXXXXXXX0000000000001111010100011 +0001110110010XXXXXXXX0000000000001111010100011 +0001110111010XXXXXXXX0000000000001111010100011 +0001110111100XXXXXXXX0000000000001111010100011 +0001110110011XXXXXXXX0000000000001111010100011 +0001110111111XXXXXXXX0000000000001111010100011 +0001110111010XXXXXXXX0000000000001111010100011 +0001110111110XXXXXXXX0000000000001111010100011 +0001110111011XXXXXXXX0000000000001111010100011 +0001110111001XXXXXXXX0000000000001111010100011 +// Simulation Cycle 930 Timestamp 37200 ns +0001110110011XXXXXXXX0000000000001111010100011 +0001110111101XXXXXXXX0000000000001111010100011 +0001110110101XXXXXXXX0000000000001111010100011 +0001110111010XXXXXXXX0000000000001111010100011 +0001110110001XXXXXXXX0000000000001111010100011 +0001110110111XXXXXXXX0000000000001111010100011 +0001110111111XXXXXXXX0000000000001111010100011 +0001110111000XXXXXXXX0000000000001111010100011 +0001110111000XXXXXXXX0000000000001111010100011 +0001110111010XXXXXXXX0000000000001111010100011 +// Simulation Cycle 940 Timestamp 37600 ns +0001110111011XXXXXXXX0000000000001111010100011 +0001110110101XXXXXXXX0000000000001111010100011 +0001110111101XXXXXXXX0000000000001111010100011 +0001110111011XXXXXXXX0000000000001111010100011 +0001110111010XXXXXXXX0000000000001111010100011 +0001110110100XXXXXXXX0000000000001111010100011 +0001110111101XXXXXXXX0000000000001111010100011 +0001110110111XXXXXXXX0000000000001111010100011 +0001110110100XXXXXXXX0000000000001111010100011 +0001110110111XXXXXXXX0000000000001111010100011 +// Simulation Cycle 950 Timestamp 38000 ns +0001110111010XXXXXXXX0000000000001111010100011 +0001110111111XXXXXXXX0000000000001111010100011 +0001110111001XXXXXXXX0000000000001111010100011 +0001110111111XXXXXXXX0000000000001111010100011 +0001110111000XXXXXXXX0000000000001111010100011 +0001110110001XXXXXXXX0000000000001111010100011 +0001110110000XXXXXXXX0000000000001111010100011 +0001110111110XXXXXXXX0000000000001111010100011 +0001110111001XXXXXXXX0000000000001111010100011 +0001110110101XXXXXXXX0000000000001111010100011 +// Simulation Cycle 960 Timestamp 38400 ns +0001110110011XXXXXXXX0000000000001111010100011 +0001110110101XXXXXXXX0000000000001111010100011 +0001110111111XXXXXXXX0000000000001111010100011 +0001110111110XXXXXXXX0000000000001111010100011 +0001110111010XXXXXXXX0000000000001111010100011 +0001110110111XXXXXXXX0000000000001111010100011 +0001110111000XXXXXXXX0000000000001111010100011 +0001110110010XXXXXXXX0000000000001111010100011 +0001110110110XXXXXXXX0000000000001111010100011 +0001110111111XXXXXXXX0000000000001111010100011 +// Simulation Cycle 970 Timestamp 38800 ns +0001110111110XXXXXXXX0000000000001111010100011 +0001110110111XXXXXXXX0000000000001111010100011 +0001110111001XXXXXXXX0000000000001111010100011 +0001110110000XXXXXXXX0000000000001111010100011 +0001110111011XXXXXXXX0000000000001111010100011 +0001110110100XXXXXXXX0000000000001111010100011 +0001110110011XXXXXXXX0000000000001111010100011 +0001110110111XXXXXXXX0000000000001111010100011 +0001110111111XXXXXXXX0000000000001111010100011 +0001110111100XXXXXXXX0000000000001111010100011 +// Simulation Cycle 980 Timestamp 39200 ns +0001110111101XXXXXXXX0000000000001111010100011 +0001110111110XXXXXXXX0000000000001111010100011 +0001110110100XXXXXXXX0000000000001111010100011 +0001110111101XXXXXXXX0000000000001111010100011 +0001110110010XXXXXXXX0000000000001111010100011 +0001110110100XXXXXXXX0000000000001111010100011 +0001110110100XXXXXXXX0000000000001111010100011 +0001110110100XXXXXXXX0000000000001111010100011 +0001110110010XXXXXXXX0000000000001111010100011 +0001110111100XXXXXXXX0000000000001111010100011 +// Simulation Cycle 990 Timestamp 39600 ns +0001110110111XXXXXXXX0000000000001111010100011 +0001110110010XXXXXXXX0000000000001111010100011 +0001110110110XXXXXXXX0000000000001111010100011 +0001110111101XXXXXXXX0000000000001111010100011 +0001110110111XXXXXXXX0000000000001111010100011 +0001110111001XXXXXXXX0000000000001111010100011 +0001110111011XXXXXXXX0000000000001111010100011 +0001110111000XXXXXXXX0000000000001111010100011 +0001110111111XXXXXXXX0000000000001111010100011 +0001110111010XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1000 Timestamp 40000 ns +0001110111000XXXXXXXX0000000000001111010100011 +0001110111000XXXXXXXX0000000000001111010100011 +0001110111111XXXXXXXX0000000000001111010100011 +0001110111000XXXXXXXX0000000000001111010100011 +0001110111111XXXXXXXX0000000000001111010100011 +0001110111001XXXXXXXX0000000000001111010100011 +0001110111100XXXXXXXX0000000000001111010100011 +0001110111100XXXXXXXX0000000000001111010100011 +0001110110110XXXXXXXX0000000000001111010100011 +0001110111100XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1010 Timestamp 40400 ns +0001110111010XXXXXXXX0000000000001111010100011 +0001110111101XXXXXXXX0000000000001111010100011 +0001110111010XXXXXXXX0000000000001111010100011 +0001110111101XXXXXXXX0000000000001111010100011 +0001110111000XXXXXXXX0000000000001111010100011 +0001110111101XXXXXXXX0000000000001111010100011 +0001110110011XXXXXXXX0000000000001111010100011 +0001110111101XXXXXXXX0000000000001111010100011 +0001110111101XXXXXXXX0000000000001111010100011 +0001110110011XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1020 Timestamp 40800 ns +0001110111001XXXXXXXX0000000000001111010100011 +0001110111111XXXXXXXX0000000000001111010100011 +0001110111111XXXXXXXX0000000000001111010100011 +0001110111001XXXXXXXX0000000000001111010100011 +0001110111011XXXXXXXX0000000000001111010100011 +0001110111111XXXXXXXX0000000000001111010100011 +1010010101011XXXXXXXX0111000000001111110101011 +// Pattern 2 Cycle 1027 Timestamp 41080 ns +000000000000000000000000000001000110000 // Start Pattern (2) MSG +1010010111010XXXXXXXX0000000000001111010100011 +1010010111011XXXXXXXX0000000000001111010100011 +1010010111110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1030 Timestamp 41200 ns +1010010111011XXXXXXXX0000000000001111010100011 +1010010110010XXXXXXXX0000000000001111010100011 +1010010110001XXXXXXXX0000000000001111010100011 +1010010110010XXXXXXXX0000000000001111010100011 +1010010111001XXXXXXXX0000000000001111010100011 +1010010110111XXXXXXXX0000000000001111010100011 +1010010111001XXXXXXXX0000000000001111010100011 +1010010111111XXXXXXXX0000000000001111010100011 +1010010110111XXXXXXXX0000000000001111010100011 +1010010111111XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1040 Timestamp 41600 ns +1010010111001XXXXXXXX0000000000001111010100011 +1010010110011XXXXXXXX0000000000001111010100011 +1010010110101XXXXXXXX0000000000001111010100011 +1010010111001XXXXXXXX0000000000001111010100011 +1010010111010XXXXXXXX0000000000001111010100011 +1010010111101XXXXXXXX0000000000001111010100011 +1010010111111XXXXXXXX0000000000001111010100011 +1010010110110XXXXXXXX0000000000001111010100011 +1010010111110XXXXXXXX0000000000001111010100011 +1010010111100XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1050 Timestamp 42000 ns +1010010110011XXXXXXXX0000000000001111010100011 +1010010111110XXXXXXXX0000000000001111010100011 +1010010110111XXXXXXXX0000000000001111010100011 +1010010111011XXXXXXXX0000000000001111010100011 +1010010110100XXXXXXXX0000000000001111010100011 +1010010110100XXXXXXXX0000000000001111010100011 +1010010111111XXXXXXXX0000000000001111010100011 +1010010111100XXXXXXXX0000000000001111010100011 +1010010111011XXXXXXXX0000000000001111010100011 +1010010110101XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1060 Timestamp 42400 ns +1010010110011XXXXXXXX0000000000001111010100011 +1010010110001XXXXXXXX0000000000001111010100011 +1010010111111XXXXXXXX0000000000001111010100011 +1010010111010XXXXXXXX0000000000001111010100011 +1010010110010XXXXXXXX0000000000001111010100011 +1010010111010XXXXXXXX0000000000001111010100011 +1010010111000XXXXXXXX0000000000001111010100011 +1010010111111XXXXXXXX0000000000001111010100011 +1010010110011XXXXXXXX0000000000001111010100011 +1010010110100XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1070 Timestamp 42800 ns +1010010110101XXXXXXXX0000000000001111010100011 +1010010110010XXXXXXXX0000000000001111010100011 +1010010111110XXXXXXXX0000000000001111010100011 +1010010110010XXXXXXXX0000000000001111010100011 +1010010110011XXXXXXXX0000000000001111010100011 +1010010110100XXXXXXXX0000000000001111010100011 +1010010110110XXXXXXXX0000000000001111010100011 +1010010110110XXXXXXXX0000000000001111010100011 +1010010110110XXXXXXXX0000000000001111010100011 +1010010110111XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1080 Timestamp 43200 ns +1010010110000XXXXXXXX0000000000001111010100011 +1010010111111XXXXXXXX0000000000001111010100011 +1010010110110XXXXXXXX0000000000001111010100011 +1010010111001XXXXXXXX0000000000001111010100011 +1010010111001XXXXXXXX0000000000001111010100011 +1010010110011XXXXXXXX0000000000001111010100011 +1010010110011XXXXXXXX0000000000001111010100011 +1010010111010XXXXXXXX0000000000001111010100011 +1010010110101XXXXXXXX0000000000001111010100011 +1010010110001XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1090 Timestamp 43600 ns +1010010110111XXXXXXXX0000000000001111010100011 +1010010111001XXXXXXXX0000000000001111010100011 +1010010111001XXXXXXXX0000000000001111010100011 +1010010111111XXXXXXXX0000000000001111010100011 +1010010111101XXXXXXXX0000000000001111010100011 +1010010111000XXXXXXXX0000000000001111010100011 +1010010111110XXXXXXXX0000000000001111010100011 +1010010111111XXXXXXXX0000000000001111010100011 +1010010111011XXXXXXXX0000000000001111010100011 +1010010110110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1100 Timestamp 44000 ns +1010010111111XXXXXXXX0000000000001111010100011 +1010010110010XXXXXXXX0000000000001111010100011 +1010010111100XXXXXXXX0000000000001111010100011 +1010010110111XXXXXXXX0000000000001111010100011 +1010010111111XXXXXXXX0000000000001111010100011 +1010010111111XXXXXXXX0000000000001111010100011 +1010010110111XXXXXXXX0000000000001111010100011 +1010010110011XXXXXXXX0000000000001111010100011 +1010010111001XXXXXXXX0000000000001111010100011 +1010010111111XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1110 Timestamp 44400 ns +1010010111101XXXXXXXX0000000000001111010100011 +1010010111111XXXXXXXX0000000000001111010100011 +1010010111110XXXXXXXX0000000000001111010100011 +1010010110110XXXXXXXX0000000000001111010100011 +1010010111011XXXXXXXX0000000000001111010100011 +1010010110101XXXXXXXX0000000000001111010100011 +1010010111111XXXXXXXX0000000000001111010100011 +1010010110000XXXXXXXX0000000000001111010100011 +1010010111000XXXXXXXX0000000000001111010100011 +1010010111101XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1120 Timestamp 44800 ns +1010010111111XXXXXXXX0000000000001111010100011 +1010010110001XXXXXXXX0000000000001111010100011 +1010010110011XXXXXXXX0000000000001111010100011 +1010010111100XXXXXXXX0000000000001111010100011 +1010010111110XXXXXXXX0000000000001111010100011 +1010010111000XXXXXXXX0000000000001111010100011 +1010010110111XXXXXXXX0000000000001111010100011 +1010010110010XXXXXXXX0000000000001111010100011 +1010010110011XXXXXXXX0000000000001111010100011 +1010010110010XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1130 Timestamp 45200 ns +1010010111110XXXXXXXX0000000000001111010100011 +1010010111111XXXXXXXX0000000000001111010100011 +1010010110110XXXXXXXX0000000000001111010100011 +1010010111110XXXXXXXX0000000000001111010100011 +1010010110010XXXXXXXX0000000000001111010100011 +1010010111110XXXXXXXX0000000000001111010100011 +1010010111100XXXXXXXX0000000000001111010100011 +1010010110101XXXXXXXX0000000000001111010100011 +1010010111111XXXXXXXX0000000000001111010100011 +1010010110011XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1140 Timestamp 45600 ns +1010010111101XXXXXXXX0000000000001111010100011 +1010010111100XXXXXXXX0000000000001111010100011 +1010010111001XXXXXXXX0000000000001111010100011 +1010010111100XXXXXXXX0000000000001111010100011 +1010010111010XXXXXXXX0000000000001111010100011 +1010010110101XXXXXXXX0000000000001111010100011 +1010010110110XXXXXXXX0000000000001111010100011 +1010010111000XXXXXXXX0000000000001111010100011 +1010010110110XXXXXXXX0000000000001111010100011 +1010010111101XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1150 Timestamp 46000 ns +1010010110110XXXXXXXX0000000000001111010100011 +1010010111011XXXXXXXX0000000000001111010100011 +1010010110001XXXXXXXX0000000000001111010100011 +1010010110110XXXXXXXX0000000000001111010100011 +1010010110010XXXXXXXX0000000000001111010100011 +1010010111111XXXXXXXX0000000000001111010100011 +1010010110011XXXXXXXX0000000000001111010100011 +1010010111101XXXXXXXX0000000000001111010100011 +1010010110110XXXXXXXX0000000000001111010100011 +1010010111010XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1160 Timestamp 46400 ns +1010010111011XXXXXXXX0000000000001111010100011 +1010010111111XXXXXXXX0000000000001111010100011 +1010010110101XXXXXXXX0000000000001111010100011 +1010010111111XXXXXXXX0000000000001111010100011 +1010010111101XXXXXXXX0000000000001111010100011 +1010010111101XXXXXXXX0000000000001111010100011 +1010010110000XXXXXXXX0000000000001111010100011 +1010010111101XXXXXXXX0000000000001111010100011 +1010010111011XXXXXXXX0000000000001111010100011 +1010010110010XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1170 Timestamp 46800 ns +1010010110011XXXXXXXX0000000000001111010100011 +1010010111111XXXXXXXX0000000000001111010100011 +1010010111110XXXXXXXX0000000000001111010100011 +1010010110100XXXXXXXX0000000000001111010100011 +1010010111111XXXXXXXX0000000000001111010100011 +1010010110110XXXXXXXX0000000000001111010100011 +1010010111101XXXXXXXX0000000000001111010100011 +1010010110001XXXXXXXX0000000000001111010100011 +1010010110111XXXXXXXX0000000000001111010100011 +1010010111110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1180 Timestamp 47200 ns +1010010111111XXXXXXXX0000000000001111010100011 +1010010110111XXXXXXXX0000000000001111010100011 +1010010110101XXXXXXXX0000000000001111010100011 +1010010110000XXXXXXXX0000000000001111010100011 +1010010110000XXXXXXXX0000000000001111010100011 +1010010110111XXXXXXXX0000000000001111010100011 +1010010111001XXXXXXXX0000000000001111010100011 +1010010111001XXXXXXXX0000000000001111010100011 +1010010110101XXXXXXXX0000000000001111010100011 +1010010111101XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1190 Timestamp 47600 ns +1010010110010XXXXXXXX0000000000001111010100011 +1010010111000XXXXXXXX0000000000001111010100011 +1010010111000XXXXXXXX0000000000001111010100011 +1010010110001XXXXXXXX0000000000001111010100011 +1010010110111XXXXXXXX0000000000001111010100011 +1010010111011XXXXXXXX0000000000001111010100011 +1010010111101XXXXXXXX0000000000001111010100011 +1010010111111XXXXXXXX0000000000001111010100011 +1010010111101XXXXXXXX0000000000001111010100011 +1010010111111XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1200 Timestamp 48000 ns +1010010110110XXXXXXXX0000000000001111010100011 +1010010110111XXXXXXXX0000000000001111010100011 +1010010111001XXXXXXXX0000000000001111010100011 +1010010111001XXXXXXXX0000000000001111010100011 +1010010110111XXXXXXXX0000000000001111010100011 +1010010110111XXXXXXXX0000000000001111010100011 +1010010111101XXXXXXXX0000000000001111010100011 +1010010111011XXXXXXXX0000000000001111010100011 +1010010111010XXXXXXXX0000000000001111010100011 +1010010111000XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1210 Timestamp 48400 ns +1010010111011XXXXXXXX0000000000001111010100011 +1010010111110XXXXXXXX0000000000001111010100011 +1010010110100XXXXXXXX0000000000001111010100011 +1010010111101XXXXXXXX0000000000001111010100011 +1010010110101XXXXXXXX0000000000001111010100011 +1010010111111XXXXXXXX0000000000001111010100011 +1010010111100XXXXXXXX0000000000001111010100011 +1010010111001XXXXXXXX0000000000001111010100011 +1010010110011XXXXXXXX0000000000001111010100011 +1010010111110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1220 Timestamp 48800 ns +1010010111100XXXXXXXX0000000000001111010100011 +1010010110111XXXXXXXX0000000000001111010100011 +1010010110111XXXXXXXX0000000000001111010100011 +1010010110010XXXXXXXX0000000000001111010100011 +1010010111010XXXXXXXX0000000000001111010100011 +1010010111010XXXXXXXX0000000000001111010100011 +1010010110100XXXXXXXX0000000000001111010100011 +1010010111010XXXXXXXX0000000000001111010100011 +1010010110111XXXXXXXX0000000000001111010100011 +1010010110000XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1230 Timestamp 49200 ns +1010010111111XXXXXXXX0000000000001111010100011 +1010010111000XXXXXXXX0000000000001111010100011 +1010010110101XXXXXXXX0000000000001111010100011 +1010010111011XXXXXXXX0000000000001111010100011 +1010010110011XXXXXXXX0000000000001111010100011 +1010010110111XXXXXXXX0000000000001111010100011 +1010010111110XXXXXXXX0000000000001111010100011 +1010010111110XXXXXXXX0000000000001111010100011 +1010010110110XXXXXXXX0000000000001111010100011 +1010010110000XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1240 Timestamp 49600 ns +1010010110100XXXXXXXX0000000000001111010100011 +1010010110110XXXXXXXX0000000000001111010100011 +1010010110101XXXXXXXX0000000000001111010100011 +1010010111001XXXXXXXX0000000000001111010100011 +1010010111101XXXXXXXX0000000000001111010100011 +1010010111010XXXXXXXX0000000000001111010100011 +1010010110111XXXXXXXX0000000000001111010100011 +1010010110101XXXXXXXX0000000000001111010100011 +1010010111111XXXXXXXX0000000000001111010100011 +1010010110101XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1250 Timestamp 50000 ns +1010010110001XXXXXXXX0000000000001111010100011 +1010010111111XXXXXXXX0000000000001111010100011 +1010010111101XXXXXXXX0000000000001111010100011 +1010010111111XXXXXXXX0000000000001111010100011 +1010010111111XXXXXXXX0000000000001111010100011 +1010010111001XXXXXXXX0000000000001111010100011 +1010010111010XXXXXXXX0000000000001111010100011 +1010010111101XXXXXXXX0000000000001111010100011 +1010010111101XXXXXXXX0000000000001111010100011 +1010010111000XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1260 Timestamp 50400 ns +1010010111001XXXXXXXX0000000000001111010100011 +1010010111111XXXXXXXX0000000000001111010100011 +1010010111001XXXXXXXX0000000000001111010100011 +1010010111111XXXXXXXX0000000000001111010100011 +1010010111101XXXXXXXX0000000000001111010100011 +1010010111001XXXXXXXX0000000000001111010100011 +1010010111111XXXXXXXX0000000000001111010100011 +1010010111110XXXXXXXX0000000000001111010100011 +1010010111110XXXXXXXX0000000000001111010100011 +1010010111011XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1270 Timestamp 50800 ns +1010010111111XXXXXXXX0000000000001111010100011 +1010010111011XXXXXXXX0000000000001111010100011 +1010010111101XXXXXXXX0000000000001111010100011 +1010010111011XXXXXXXX0000000000001111010100011 +1010010111010XXXXXXXX0000000000001111010100011 +1010010111101XXXXXXXX0000000000001111010100011 +1010010111101XXXXXXXX0000000000001111010100011 +1010010111001XXXXXXXX0000000000001111010100011 +1010010111011XXXXXXXX0000000000001111010100011 +1010010111110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1280 Timestamp 51200 ns +1010010111011XXXXXXXX0000000000001111010100011 +1010010110101XXXXXXXX0000000000001111010100011 +1010010111111XXXXXXXX0000000000001111010100011 +1111100100111XXXXXXXX1010000000001111110101011 +// Pattern 3 Cycle 1284 Timestamp 51360 ns +000000000000000000000000000001000110000 // Start Pattern (3) MSG +1111100110110XXXXXXXX0000000000001111010100011 +1111100110111XXXXXXXX0000000000001111010100011 +1111100110101XXXXXXXX0000000000001111010100011 +1111100111111XXXXXXXX0000000000001111010100011 +1111100111011XXXXXXXX0000000000001111010100011 +1111100110110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1290 Timestamp 51600 ns +1111100111010XXXXXXXX0000000000001111010100011 +1111100110110XXXXXXXX0000000000001111010100011 +1111100110111XXXXXXXX0000000000001111010100011 +1111100110001XXXXXXXX0000000000001111010100011 +1111100110011XXXXXXXX0000000000001111010100011 +1111100111111XXXXXXXX0000000000001111010100011 +1111100111000XXXXXXXX0000000000001111010100011 +1111100111001XXXXXXXX0000000000001111010100011 +1111100110100XXXXXXXX0000000000001111010100011 +1111100111111XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1300 Timestamp 52000 ns +1111100111000XXXXXXXX0000000000001111010100011 +1111100111111XXXXXXXX0000000000001111010100011 +1111100110011XXXXXXXX0000000000001111010100011 +1111100110001XXXXXXXX0000000000001111010100011 +1111100111011XXXXXXXX0000000000001111010100011 +1111100110101XXXXXXXX0000000000001111010100011 +1111100111111XXXXXXXX0000000000001111010100011 +1111100110110XXXXXXXX0000000000001111010100011 +1111100111011XXXXXXXX0000000000001111010100011 +1111100110110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1310 Timestamp 52400 ns +1111100110010XXXXXXXX0000000000001111010100011 +1111100110110XXXXXXXX0000000000001111010100011 +1111100110011XXXXXXXX0000000000001111010100011 +1111100111111XXXXXXXX0000000000001111010100011 +1111100111000XXXXXXXX0000000000001111010100011 +1111100111101XXXXXXXX0000000000001111010100011 +1111100111100XXXXXXXX0000000000001111010100011 +1111100111000XXXXXXXX0000000000001111010100011 +1111100111010XXXXXXXX0000000000001111010100011 +1111100111110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1320 Timestamp 52800 ns +1111100111111XXXXXXXX0000000000001111010100011 +1111100111101XXXXXXXX0000000000001111010100011 +1111100110111XXXXXXXX0000000000001111010100011 +1111100111001XXXXXXXX0000000000001111010100011 +1111100110010XXXXXXXX0000000000001111010100011 +1111100110001XXXXXXXX0000000000001111010100011 +1111100110100XXXXXXXX0000000000001111010100011 +1111100110101XXXXXXXX0000000000001111010100011 +1111100110111XXXXXXXX0000000000001111010100011 +1111100111001XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1330 Timestamp 53200 ns +1111100110111XXXXXXXX0000000000001111010100011 +1111100111010XXXXXXXX0000000000001111010100011 +1111100111100XXXXXXXX0000000000001111010100011 +1111100110111XXXXXXXX0000000000001111010100011 +1111100110010XXXXXXXX0000000000001111010100011 +1111100111111XXXXXXXX0000000000001111010100011 +1111100110001XXXXXXXX0000000000001111010100011 +1111100110111XXXXXXXX0000000000001111010100011 +1111100111111XXXXXXXX0000000000001111010100011 +1111100110001XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1340 Timestamp 53600 ns +1111100111110XXXXXXXX0000000000001111010100011 +1111100111010XXXXXXXX0000000000001111010100011 +1111100111010XXXXXXXX0000000000001111010100011 +1111100111101XXXXXXXX0000000000001111010100011 +1111100110110XXXXXXXX0000000000001111010100011 +1111100110000XXXXXXXX0000000000001111010100011 +1111100110001XXXXXXXX0000000000001111010100011 +1111100110000XXXXXXXX0000000000001111010100011 +1111100110010XXXXXXXX0000000000001111010100011 +1111100111110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1350 Timestamp 54000 ns +1111100110111XXXXXXXX0000000000001111010100011 +1111100110001XXXXXXXX0000000000001111010100011 +1111100111111XXXXXXXX0000000000001111010100011 +1111100110011XXXXXXXX0000000000001111010100011 +1111100111001XXXXXXXX0000000000001111010100011 +1111100110111XXXXXXXX0000000000001111010100011 +1111100110101XXXXXXXX0000000000001111010100011 +1111100110001XXXXXXXX0000000000001111010100011 +1111100111011XXXXXXXX0000000000001111010100011 +1111100110100XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1360 Timestamp 54400 ns +1111100110000XXXXXXXX0000000000001111010100011 +1111100110000XXXXXXXX0000000000001111010100011 +1111100110101XXXXXXXX0000000000001111010100011 +1111100110110XXXXXXXX0000000000001111010100011 +1111100111111XXXXXXXX0000000000001111010100011 +1111100111111XXXXXXXX0000000000001111010100011 +1111100111101XXXXXXXX0000000000001111010100011 +1111100111110XXXXXXXX0000000000001111010100011 +1111100111011XXXXXXXX0000000000001111010100011 +1111100110011XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1370 Timestamp 54800 ns +1111100111111XXXXXXXX0000000000001111010100011 +1111100111000XXXXXXXX0000000000001111010100011 +1111100110010XXXXXXXX0000000000001111010100011 +1111100111110XXXXXXXX0000000000001111010100011 +1111100110100XXXXXXXX0000000000001111010100011 +1111100111111XXXXXXXX0000000000001111010100011 +1111100110011XXXXXXXX0000000000001111010100011 +1111100111010XXXXXXXX0000000000001111010100011 +1111100111001XXXXXXXX0000000000001111010100011 +1111100110110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1380 Timestamp 55200 ns +1111100110011XXXXXXXX0000000000001111010100011 +1111100110011XXXXXXXX0000000000001111010100011 +1111100111010XXXXXXXX0000000000001111010100011 +1111100110000XXXXXXXX0000000000001111010100011 +1111100111000XXXXXXXX0000000000001111010100011 +1111100111001XXXXXXXX0000000000001111010100011 +1111100110100XXXXXXXX0000000000001111010100011 +1111100110000XXXXXXXX0000000000001111010100011 +1111100110111XXXXXXXX0000000000001111010100011 +1111100111000XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1390 Timestamp 55600 ns +1111100111001XXXXXXXX0000000000001111010100011 +1111100111111XXXXXXXX0000000000001111010100011 +1111100110111XXXXXXXX0000000000001111010100011 +1111100111011XXXXXXXX0000000000001111010100011 +1111100110001XXXXXXXX0000000000001111010100011 +1111100110110XXXXXXXX0000000000001111010100011 +1111100111110XXXXXXXX0000000000001111010100011 +1111100110101XXXXXXXX0000000000001111010100011 +1111100110001XXXXXXXX0000000000001111010100011 +1111100111111XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1400 Timestamp 56000 ns +1111100110111XXXXXXXX0000000000001111010100011 +1111100110001XXXXXXXX0000000000001111010100011 +1111100111111XXXXXXXX0000000000001111010100011 +1111100111011XXXXXXXX0000000000001111010100011 +1111100110100XXXXXXXX0000000000001111010100011 +1111100110011XXXXXXXX0000000000001111010100011 +1111100110011XXXXXXXX0000000000001111010100011 +1111100111010XXXXXXXX0000000000001111010100011 +1111100111111XXXXXXXX0000000000001111010100011 +1111100111001XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1410 Timestamp 56400 ns +1111100111100XXXXXXXX0000000000001111010100011 +1111100111111XXXXXXXX0000000000001111010100011 +1111100111101XXXXXXXX0000000000001111010100011 +1111100111000XXXXXXXX0000000000001111010100011 +1111100111000XXXXXXXX0000000000001111010100011 +1111100111101XXXXXXXX0000000000001111010100011 +1111100110000XXXXXXXX0000000000001111010100011 +1111100110011XXXXXXXX0000000000001111010100011 +1111100111110XXXXXXXX0000000000001111010100011 +1111100111101XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1420 Timestamp 56800 ns +1111100110010XXXXXXXX0000000000001111010100011 +1111100110011XXXXXXXX0000000000001111010100011 +1111100110010XXXXXXXX0000000000001111010100011 +1111100111001XXXXXXXX0000000000001111010100011 +1111100111010XXXXXXXX0000000000001111010100011 +1111100111101XXXXXXXX0000000000001111010100011 +1111100111011XXXXXXXX0000000000001111010100011 +1111100110101XXXXXXXX0000000000001111010100011 +1111100110110XXXXXXXX0000000000001111010100011 +1111100111111XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1430 Timestamp 57200 ns +1111100111000XXXXXXXX0000000000001111010100011 +1111100111100XXXXXXXX0000000000001111010100011 +1111100110111XXXXXXXX0000000000001111010100011 +1111100111110XXXXXXXX0000000000001111010100011 +1111100111001XXXXXXXX0000000000001111010100011 +1111100111110XXXXXXXX0000000000001111010100011 +1111100111011XXXXXXXX0000000000001111010100011 +1111100111011XXXXXXXX0000000000001111010100011 +1111100110100XXXXXXXX0000000000001111010100011 +1111100110100XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1440 Timestamp 57600 ns +1111100111011XXXXXXXX0000000000001111010100011 +1111100111010XXXXXXXX0000000000001111010100011 +1111100111101XXXXXXXX0000000000001111010100011 +1111100110101XXXXXXXX0000000000001111010100011 +1111100111001XXXXXXXX0000000000001111010100011 +1111100111010XXXXXXXX0000000000001111010100011 +1111100110101XXXXXXXX0000000000001111010100011 +1111100111110XXXXXXXX0000000000001111010100011 +1111100110010XXXXXXXX0000000000001111010100011 +1111100110001XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1450 Timestamp 58000 ns +1111100111110XXXXXXXX0000000000001111010100011 +1111100111001XXXXXXXX0000000000001111010100011 +1111100111100XXXXXXXX0000000000001111010100011 +1111100111110XXXXXXXX0000000000001111010100011 +1111100110000XXXXXXXX0000000000001111010100011 +1111100111101XXXXXXXX0000000000001111010100011 +1111100110111XXXXXXXX0000000000001111010100011 +1111100110000XXXXXXXX0000000000001111010100011 +1111100111010XXXXXXXX0000000000001111010100011 +1111100111100XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1460 Timestamp 58400 ns +1111100110100XXXXXXXX0000000000001111010100011 +1111100110011XXXXXXXX0000000000001111010100011 +1111100110101XXXXXXXX0000000000001111010100011 +1111100111110XXXXXXXX0000000000001111010100011 +1111100110001XXXXXXXX0000000000001111010100011 +1111100111011XXXXXXXX0000000000001111010100011 +1111100111111XXXXXXXX0000000000001111010100011 +1111100111110XXXXXXXX0000000000001111010100011 +1111100111010XXXXXXXX0000000000001111010100011 +1111100111010XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1470 Timestamp 58800 ns +1111100111100XXXXXXXX0000000000001111010100011 +1111100111101XXXXXXXX0000000000001111010100011 +1111100110100XXXXXXXX0000000000001111010100011 +1111100111010XXXXXXXX0000000000001111010100011 +1111100110001XXXXXXXX0000000000001111010100011 +1111100111011XXXXXXXX0000000000001111010100011 +1111100111001XXXXXXXX0000000000001111010100011 +1111100111101XXXXXXXX0000000000001111010100011 +1111100110101XXXXXXXX0000000000001111010100011 +1111100111110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1480 Timestamp 59200 ns +1111100110000XXXXXXXX0000000000001111010100011 +1111100110010XXXXXXXX0000000000001111010100011 +1111100110010XXXXXXXX0000000000001111010100011 +1111100111110XXXXXXXX0000000000001111010100011 +1111100110011XXXXXXXX0000000000001111010100011 +1111100110001XXXXXXXX0000000000001111010100011 +1111100110001XXXXXXXX0000000000001111010100011 +1111100110111XXXXXXXX0000000000001111010100011 +1111100110111XXXXXXXX0000000000001111010100011 +1111100110110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1490 Timestamp 59600 ns +1111100111110XXXXXXXX0000000000001111010100011 +1111100111011XXXXXXXX0000000000001111010100011 +1111100110011XXXXXXXX0000000000001111010100011 +1111100110110XXXXXXXX0000000000001111010100011 +1111100111100XXXXXXXX0000000000001111010100011 +1111100110101XXXXXXXX0000000000001111010100011 +1111100111000XXXXXXXX0000000000001111010100011 +1111100110000XXXXXXXX0000000000001111010100011 +1111100111111XXXXXXXX0000000000001111010100011 +1111100110011XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1500 Timestamp 60000 ns +1111100111001XXXXXXXX0000000000001111010100011 +1111100110000XXXXXXXX0000000000001111010100011 +1111100110011XXXXXXXX0000000000001111010100011 +1111100111111XXXXXXXX0000000000001111010100011 +1111100111110XXXXXXXX0000000000001111010100011 +1111100111101XXXXXXXX0000000000001111010100011 +1111100111000XXXXXXXX0000000000001111010100011 +1111100110001XXXXXXXX0000000000001111010100011 +1111100110010XXXXXXXX0000000000001111010100011 +1111100111101XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1510 Timestamp 60400 ns +1111100111011XXXXXXXX0000000000001111010100011 +1111100111111XXXXXXXX0000000000001111010100011 +1111100111111XXXXXXXX0000000000001111010100011 +1111100111100XXXXXXXX0000000000001111010100011 +1111100111111XXXXXXXX0000000000001111010100011 +1111100111101XXXXXXXX0000000000001111010100011 +1111100111101XXXXXXXX0000000000001111010100011 +1111100111110XXXXXXXX0000000000001111010100011 +1111100111110XXXXXXXX0000000000001111010100011 +1111100111001XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1520 Timestamp 60800 ns +1111100111111XXXXXXXX0000000000001111010100011 +1111100111110XXXXXXXX0000000000001111010100011 +1111100111000XXXXXXXX0000000000001111010100011 +1111100111000XXXXXXXX0000000000001111010100011 +1111100111101XXXXXXXX0000000000001111010100011 +1111100111110XXXXXXXX0000000000001111010100011 +1111100111001XXXXXXXX0000000000001111010100011 +1111100111111XXXXXXXX0000000000001111010100011 +1111100111001XXXXXXXX0000000000001111010100011 +1111100111110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1530 Timestamp 61200 ns +1111100111011XXXXXXXX0000000000001111010100011 +1111100111000XXXXXXXX0000000000001111010100011 +1111100111011XXXXXXXX0000000000001111010100011 +1111100110101XXXXXXXX0000000000001111010100011 +1111100110111XXXXXXXX0000000000001111010100011 +1111100111010XXXXXXXX0000000000001111010100011 +1111100111010XXXXXXXX0000000000001111010100011 +1111100111000XXXXXXXX0000000000001111010100011 +1111100110100XXXXXXXX0000000000001111010100011 +1111100111000XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1540 Timestamp 61600 ns +0101010101001XXXXXXXX0110000000001111110101011 +// Pattern 4 Cycle 1541 Timestamp 61640 ns +000000000000000000000000000001000110000 // Start Pattern (4) MSG +0101010110011XXXXXXXX0000000000001111010100011 +0101010110011XXXXXXXX0000000000001111010100011 +0101010111001XXXXXXXX0000000000001111010100011 +0101010110011XXXXXXXX0000000000001111010100011 +0101010110011XXXXXXXX0000000000001111010100011 +0101010111101XXXXXXXX0000000000001111010100011 +0101010111110XXXXXXXX0000000000001111010100011 +0101010110000XXXXXXXX0000000000001111010100011 +0101010111000XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1550 Timestamp 62000 ns +0101010110000XXXXXXXX0000000000001111010100011 +0101010111100XXXXXXXX0000000000001111010100011 +0101010111011XXXXXXXX0000000000001111010100011 +0101010110000XXXXXXXX0000000000001111010100011 +0101010111100XXXXXXXX0000000000001111010100011 +0101010111011XXXXXXXX0000000000001111010100011 +0101010110000XXXXXXXX0000000000001111010100011 +0101010110111XXXXXXXX0000000000001111010100011 +0101010110011XXXXXXXX0000000000001111010100011 +0101010110010XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1560 Timestamp 62400 ns +0101010110111XXXXXXXX0000000000001111010100011 +0101010110110XXXXXXXX0000000000001111010100011 +0101010110010XXXXXXXX0000000000001111010100011 +0101010111000XXXXXXXX0000000000001111010100011 +0101010110000XXXXXXXX0000000000001111010100011 +0101010110101XXXXXXXX0000000000001111010100011 +0101010110111XXXXXXXX0000000000001111010100011 +0101010110011XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1570 Timestamp 62800 ns +0101010110010XXXXXXXX0000000000001111010100011 +0101010111001XXXXXXXX0000000000001111010100011 +0101010111011XXXXXXXX0000000000001111010100011 +0101010110011XXXXXXXX0000000000001111010100011 +0101010110001XXXXXXXX0000000000001111010100011 +0101010111010XXXXXXXX0000000000001111010100011 +0101010110011XXXXXXXX0000000000001111010100011 +0101010110100XXXXXXXX0000000000001111010100011 +0101010111001XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1580 Timestamp 63200 ns +0101010111010XXXXXXXX0000000000001111010100011 +0101010111011XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010111000XXXXXXXX0000000000001111010100011 +0101010111101XXXXXXXX0000000000001111010100011 +0101010110110XXXXXXXX0000000000001111010100011 +0101010111011XXXXXXXX0000000000001111010100011 +0101010111100XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010110110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1590 Timestamp 63600 ns +0101010110001XXXXXXXX0000000000001111010100011 +0101010111011XXXXXXXX0000000000001111010100011 +0101010111010XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010111100XXXXXXXX0000000000001111010100011 +0101010111011XXXXXXXX0000000000001111010100011 +0101010110011XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010110010XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1600 Timestamp 64000 ns +0101010110010XXXXXXXX0000000000001111010100011 +0101010110101XXXXXXXX0000000000001111010100011 +0101010111100XXXXXXXX0000000000001111010100011 +0101010110111XXXXXXXX0000000000001111010100011 +0101010111110XXXXXXXX0000000000001111010100011 +0101010111101XXXXXXXX0000000000001111010100011 +0101010111100XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010111101XXXXXXXX0000000000001111010100011 +0101010110011XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1610 Timestamp 64400 ns +0101010110111XXXXXXXX0000000000001111010100011 +0101010111010XXXXXXXX0000000000001111010100011 +0101010111001XXXXXXXX0000000000001111010100011 +0101010111001XXXXXXXX0000000000001111010100011 +0101010110101XXXXXXXX0000000000001111010100011 +0101010110001XXXXXXXX0000000000001111010100011 +0101010111101XXXXXXXX0000000000001111010100011 +0101010111011XXXXXXXX0000000000001111010100011 +0101010111101XXXXXXXX0000000000001111010100011 +0101010110010XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1620 Timestamp 64800 ns +0101010111101XXXXXXXX0000000000001111010100011 +0101010111001XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010111011XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010110110XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010110111XXXXXXXX0000000000001111010100011 +0101010110110XXXXXXXX0000000000001111010100011 +0101010111101XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1630 Timestamp 65200 ns +0101010111101XXXXXXXX0000000000001111010100011 +0101010110110XXXXXXXX0000000000001111010100011 +0101010110101XXXXXXXX0000000000001111010100011 +0101010111100XXXXXXXX0000000000001111010100011 +0101010111101XXXXXXXX0000000000001111010100011 +0101010111011XXXXXXXX0000000000001111010100011 +0101010111011XXXXXXXX0000000000001111010100011 +0101010110111XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010111011XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1640 Timestamp 65600 ns +0101010111010XXXXXXXX0000000000001111010100011 +0101010111110XXXXXXXX0000000000001111010100011 +0101010110100XXXXXXXX0000000000001111010100011 +0101010110010XXXXXXXX0000000000001111010100011 +0101010110110XXXXXXXX0000000000001111010100011 +0101010111011XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010111001XXXXXXXX0000000000001111010100011 +0101010111001XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1650 Timestamp 66000 ns +0101010111010XXXXXXXX0000000000001111010100011 +0101010110110XXXXXXXX0000000000001111010100011 +0101010110011XXXXXXXX0000000000001111010100011 +0101010111100XXXXXXXX0000000000001111010100011 +0101010110000XXXXXXXX0000000000001111010100011 +0101010111000XXXXXXXX0000000000001111010100011 +0101010111100XXXXXXXX0000000000001111010100011 +0101010110100XXXXXXXX0000000000001111010100011 +0101010111010XXXXXXXX0000000000001111010100011 +0101010110111XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1660 Timestamp 66400 ns +0101010111111XXXXXXXX0000000000001111010100011 +0101010110101XXXXXXXX0000000000001111010100011 +0101010111110XXXXXXXX0000000000001111010100011 +0101010110001XXXXXXXX0000000000001111010100011 +0101010111000XXXXXXXX0000000000001111010100011 +0101010111011XXXXXXXX0000000000001111010100011 +0101010110110XXXXXXXX0000000000001111010100011 +0101010111010XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010110101XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1670 Timestamp 66800 ns +0101010111011XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010110001XXXXXXXX0000000000001111010100011 +0101010110111XXXXXXXX0000000000001111010100011 +0101010110111XXXXXXXX0000000000001111010100011 +0101010111110XXXXXXXX0000000000001111010100011 +0101010110101XXXXXXXX0000000000001111010100011 +0101010111101XXXXXXXX0000000000001111010100011 +0101010110010XXXXXXXX0000000000001111010100011 +0101010111100XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1680 Timestamp 67200 ns +0101010110101XXXXXXXX0000000000001111010100011 +0101010111101XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010111100XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010111000XXXXXXXX0000000000001111010100011 +0101010111110XXXXXXXX0000000000001111010100011 +0101010111010XXXXXXXX0000000000001111010100011 +0101010111110XXXXXXXX0000000000001111010100011 +0101010111100XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1690 Timestamp 67600 ns +0101010111000XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010111110XXXXXXXX0000000000001111010100011 +0101010110010XXXXXXXX0000000000001111010100011 +0101010111101XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010111011XXXXXXXX0000000000001111010100011 +0101010111110XXXXXXXX0000000000001111010100011 +0101010110110XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1700 Timestamp 68000 ns +0101010111011XXXXXXXX0000000000001111010100011 +0101010110111XXXXXXXX0000000000001111010100011 +0101010110100XXXXXXXX0000000000001111010100011 +0101010110110XXXXXXXX0000000000001111010100011 +0101010110011XXXXXXXX0000000000001111010100011 +0101010111001XXXXXXXX0000000000001111010100011 +0101010110111XXXXXXXX0000000000001111010100011 +0101010110111XXXXXXXX0000000000001111010100011 +0101010110101XXXXXXXX0000000000001111010100011 +0101010110110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1710 Timestamp 68400 ns +0101010111001XXXXXXXX0000000000001111010100011 +0101010110010XXXXXXXX0000000000001111010100011 +0101010110101XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010111000XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010111001XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010110110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1720 Timestamp 68800 ns +0101010110000XXXXXXXX0000000000001111010100011 +0101010110010XXXXXXXX0000000000001111010100011 +0101010110010XXXXXXXX0000000000001111010100011 +0101010111000XXXXXXXX0000000000001111010100011 +0101010111101XXXXXXXX0000000000001111010100011 +0101010111010XXXXXXXX0000000000001111010100011 +0101010110101XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010111001XXXXXXXX0000000000001111010100011 +0101010111110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1730 Timestamp 69200 ns +0101010111111XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010110011XXXXXXXX0000000000001111010100011 +0101010110110XXXXXXXX0000000000001111010100011 +0101010110110XXXXXXXX0000000000001111010100011 +0101010110100XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010110011XXXXXXXX0000000000001111010100011 +0101010111010XXXXXXXX0000000000001111010100011 +0101010111001XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1740 Timestamp 69600 ns +0101010110011XXXXXXXX0000000000001111010100011 +0101010110111XXXXXXXX0000000000001111010100011 +0101010111011XXXXXXXX0000000000001111010100011 +0101010110100XXXXXXXX0000000000001111010100011 +0101010111001XXXXXXXX0000000000001111010100011 +0101010110110XXXXXXXX0000000000001111010100011 +0101010111000XXXXXXXX0000000000001111010100011 +0101010111110XXXXXXXX0000000000001111010100011 +0101010110111XXXXXXXX0000000000001111010100011 +0101010111011XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1750 Timestamp 70000 ns +0101010110001XXXXXXXX0000000000001111010100011 +0101010111010XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010111010XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010110111XXXXXXXX0000000000001111010100011 +0101010111010XXXXXXXX0000000000001111010100011 +0101010111101XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1760 Timestamp 70400 ns +0101010110111XXXXXXXX0000000000001111010100011 +0101010110011XXXXXXXX0000000000001111010100011 +0101010111010XXXXXXXX0000000000001111010100011 +0101010111110XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010111101XXXXXXXX0000000000001111010100011 +0101010111000XXXXXXXX0000000000001111010100011 +0101010110011XXXXXXXX0000000000001111010100011 +0101010111000XXXXXXXX0000000000001111010100011 +0101010111110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1770 Timestamp 70800 ns +0101010111011XXXXXXXX0000000000001111010100011 +0101010111010XXXXXXXX0000000000001111010100011 +0101010111110XXXXXXXX0000000000001111010100011 +0101010111000XXXXXXXX0000000000001111010100011 +0101010111010XXXXXXXX0000000000001111010100011 +0101010111110XXXXXXXX0000000000001111010100011 +0101010111100XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010111101XXXXXXXX0000000000001111010100011 +0101010111001XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1780 Timestamp 71200 ns +0101010111101XXXXXXXX0000000000001111010100011 +0101010111011XXXXXXXX0000000000001111010100011 +0101010111110XXXXXXXX0000000000001111010100011 +0101010111001XXXXXXXX0000000000001111010100011 +0101010111100XXXXXXXX0000000000001111010100011 +0101010111010XXXXXXXX0000000000001111010100011 +0101010111010XXXXXXXX0000000000001111010100011 +0101010111010XXXXXXXX0000000000001111010100011 +0101010111001XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1790 Timestamp 71600 ns +0101010111111XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010111101XXXXXXXX0000000000001111010100011 +0101010110100XXXXXXXX0000000000001111010100011 +0101010111100XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0000000101111XXXXXXXX0011000000001111110101011 +// Pattern 5 Cycle 1798 Timestamp 71920 ns +000000000000000000000000000001000110000 // Start Pattern (5) MSG +0000000111011XXXXXXXX0000000000001111010100011 +0000000111001XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1800 Timestamp 72000 ns +0000000110011XXXXXXXX0000000000001111010100011 +0000000110101XXXXXXXX0000000000001111010100011 +0000000110000XXXXXXXX0000000000001111010100011 +0000000111010XXXXXXXX0000000000001111010100011 +0000000111000XXXXXXXX0000000000001111010100011 +0000000110011XXXXXXXX0000000000001111010100011 +0000000110001XXXXXXXX0000000000001111010100011 +0000000110001XXXXXXXX0000000000001111010100011 +0000000110111XXXXXXXX0000000000001111010100011 +0000000111011XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1810 Timestamp 72400 ns +0000000111011XXXXXXXX0000000000001111010100011 +0000000111001XXXXXXXX0000000000001111010100011 +0000000111001XXXXXXXX0000000000001111010100011 +0000000110000XXXXXXXX0000000000001111010100011 +0000000110010XXXXXXXX0000000000001111010100011 +0000000110011XXXXXXXX0000000000001111010100011 +0000000111011XXXXXXXX0000000000001111010100011 +0000000111001XXXXXXXX0000000000001111010100011 +0000000111111XXXXXXXX0000000000001111010100011 +0000000111000XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1820 Timestamp 72800 ns +0000000110101XXXXXXXX0000000000001111010100011 +0000000111001XXXXXXXX0000000000001111010100011 +0000000111100XXXXXXXX0000000000001111010100011 +0000000111110XXXXXXXX0000000000001111010100011 +0000000111111XXXXXXXX0000000000001111010100011 +0000000110000XXXXXXXX0000000000001111010100011 +0000000110010XXXXXXXX0000000000001111010100011 +0000000111011XXXXXXXX0000000000001111010100011 +0000000111000XXXXXXXX0000000000001111010100011 +0000000110001XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1830 Timestamp 73200 ns +0000000111111XXXXXXXX0000000000001111010100011 +0000000110001XXXXXXXX0000000000001111010100011 +0000000111110XXXXXXXX0000000000001111010100011 +0000000111110XXXXXXXX0000000000001111010100011 +0000000110110XXXXXXXX0000000000001111010100011 +0000000111100XXXXXXXX0000000000001111010100011 +0000000110000XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +0000000111111XXXXXXXX0000000000001111010100011 +0000000110011XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1840 Timestamp 73600 ns +0000000110001XXXXXXXX0000000000001111010100011 +0000000111110XXXXXXXX0000000000001111010100011 +0000000110000XXXXXXXX0000000000001111010100011 +0000000110001XXXXXXXX0000000000001111010100011 +0000000110001XXXXXXXX0000000000001111010100011 +0000000111011XXXXXXXX0000000000001111010100011 +0000000111110XXXXXXXX0000000000001111010100011 +0000000111100XXXXXXXX0000000000001111010100011 +0000000110010XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1850 Timestamp 74000 ns +0000000110001XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +0000000111000XXXXXXXX0000000000001111010100011 +0000000111010XXXXXXXX0000000000001111010100011 +0000000111001XXXXXXXX0000000000001111010100011 +0000000110011XXXXXXXX0000000000001111010100011 +0000000110001XXXXXXXX0000000000001111010100011 +0000000110100XXXXXXXX0000000000001111010100011 +0000000110000XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1860 Timestamp 74400 ns +0000000110111XXXXXXXX0000000000001111010100011 +0000000111111XXXXXXXX0000000000001111010100011 +0000000111100XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +0000000111111XXXXXXXX0000000000001111010100011 +0000000111010XXXXXXXX0000000000001111010100011 +0000000110000XXXXXXXX0000000000001111010100011 +0000000110110XXXXXXXX0000000000001111010100011 +0000000111001XXXXXXXX0000000000001111010100011 +0000000110111XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1870 Timestamp 74800 ns +0000000111001XXXXXXXX0000000000001111010100011 +0000000110110XXXXXXXX0000000000001111010100011 +0000000111010XXXXXXXX0000000000001111010100011 +0000000111000XXXXXXXX0000000000001111010100011 +0000000111111XXXXXXXX0000000000001111010100011 +0000000110101XXXXXXXX0000000000001111010100011 +0000000111100XXXXXXXX0000000000001111010100011 +0000000110100XXXXXXXX0000000000001111010100011 +0000000111001XXXXXXXX0000000000001111010100011 +0000000110110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1880 Timestamp 75200 ns +0000000110100XXXXXXXX0000000000001111010100011 +0000000110100XXXXXXXX0000000000001111010100011 +0000000110000XXXXXXXX0000000000001111010100011 +0000000111111XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +0000000110101XXXXXXXX0000000000001111010100011 +0000000111100XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +0000000111100XXXXXXXX0000000000001111010100011 +0000000110000XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1890 Timestamp 75600 ns +0000000111001XXXXXXXX0000000000001111010100011 +0000000110100XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +0000000111100XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +0000000110110XXXXXXXX0000000000001111010100011 +0000000110011XXXXXXXX0000000000001111010100011 +0000000110110XXXXXXXX0000000000001111010100011 +0000000111010XXXXXXXX0000000000001111010100011 +0000000111001XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1900 Timestamp 76000 ns +0000000110000XXXXXXXX0000000000001111010100011 +0000000111111XXXXXXXX0000000000001111010100011 +0000000110000XXXXXXXX0000000000001111010100011 +0000000110101XXXXXXXX0000000000001111010100011 +0000000110111XXXXXXXX0000000000001111010100011 +0000000111001XXXXXXXX0000000000001111010100011 +0000000110100XXXXXXXX0000000000001111010100011 +0000000111111XXXXXXXX0000000000001111010100011 +0000000111000XXXXXXXX0000000000001111010100011 +0000000111011XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1910 Timestamp 76400 ns +0000000111000XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +0000000110111XXXXXXXX0000000000001111010100011 +0000000111110XXXXXXXX0000000000001111010100011 +0000000110001XXXXXXXX0000000000001111010100011 +0000000110110XXXXXXXX0000000000001111010100011 +0000000110001XXXXXXXX0000000000001111010100011 +0000000110000XXXXXXXX0000000000001111010100011 +0000000111110XXXXXXXX0000000000001111010100011 +0000000110001XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1920 Timestamp 76800 ns +0000000110111XXXXXXXX0000000000001111010100011 +0000000110101XXXXXXXX0000000000001111010100011 +0000000110110XXXXXXXX0000000000001111010100011 +0000000110111XXXXXXXX0000000000001111010100011 +0000000110010XXXXXXXX0000000000001111010100011 +0000000110101XXXXXXXX0000000000001111010100011 +0000000111001XXXXXXXX0000000000001111010100011 +0000000111110XXXXXXXX0000000000001111010100011 +0000000110001XXXXXXXX0000000000001111010100011 +0000000111000XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1930 Timestamp 77200 ns +0000000111000XXXXXXXX0000000000001111010100011 +0000000111010XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +0000000111011XXXXXXXX0000000000001111010100011 +0000000111110XXXXXXXX0000000000001111010100011 +0000000110010XXXXXXXX0000000000001111010100011 +0000000110010XXXXXXXX0000000000001111010100011 +0000000110110XXXXXXXX0000000000001111010100011 +0000000110110XXXXXXXX0000000000001111010100011 +0000000111111XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1940 Timestamp 77600 ns +0000000110001XXXXXXXX0000000000001111010100011 +0000000110011XXXXXXXX0000000000001111010100011 +0000000111001XXXXXXXX0000000000001111010100011 +0000000110111XXXXXXXX0000000000001111010100011 +0000000111110XXXXXXXX0000000000001111010100011 +0000000111011XXXXXXXX0000000000001111010100011 +0000000110001XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +0000000110001XXXXXXXX0000000000001111010100011 +0000000110011XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1950 Timestamp 78000 ns +0000000111001XXXXXXXX0000000000001111010100011 +0000000111001XXXXXXXX0000000000001111010100011 +0000000111111XXXXXXXX0000000000001111010100011 +0000000111110XXXXXXXX0000000000001111010100011 +0000000111011XXXXXXXX0000000000001111010100011 +0000000111000XXXXXXXX0000000000001111010100011 +0000000111100XXXXXXXX0000000000001111010100011 +0000000110010XXXXXXXX0000000000001111010100011 +0000000110101XXXXXXXX0000000000001111010100011 +0000000111110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1960 Timestamp 78400 ns +0000000110111XXXXXXXX0000000000001111010100011 +0000000111110XXXXXXXX0000000000001111010100011 +0000000111111XXXXXXXX0000000000001111010100011 +0000000110011XXXXXXXX0000000000001111010100011 +0000000111110XXXXXXXX0000000000001111010100011 +0000000110001XXXXXXXX0000000000001111010100011 +0000000111111XXXXXXXX0000000000001111010100011 +0000000111110XXXXXXXX0000000000001111010100011 +0000000111011XXXXXXXX0000000000001111010100011 +0000000111100XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1970 Timestamp 78800 ns +0000000111000XXXXXXXX0000000000001111010100011 +0000000111111XXXXXXXX0000000000001111010100011 +0000000111010XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +0000000110101XXXXXXXX0000000000001111010100011 +0000000111110XXXXXXXX0000000000001111010100011 +0000000110001XXXXXXXX0000000000001111010100011 +0000000111100XXXXXXXX0000000000001111010100011 +0000000110011XXXXXXXX0000000000001111010100011 +0000000111110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1980 Timestamp 79200 ns +0000000111110XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +0000000111011XXXXXXXX0000000000001111010100011 +0000000111010XXXXXXXX0000000000001111010100011 +0000000111110XXXXXXXX0000000000001111010100011 +0000000110100XXXXXXXX0000000000001111010100011 +0000000110110XXXXXXXX0000000000001111010100011 +0000000111010XXXXXXXX0000000000001111010100011 +0000000110101XXXXXXXX0000000000001111010100011 +0000000110011XXXXXXXX0000000000001111010100011 +// Simulation Cycle 1990 Timestamp 79600 ns +0000000110101XXXXXXXX0000000000001111010100011 +0000000110110XXXXXXXX0000000000001111010100011 +0000000110000XXXXXXXX0000000000001111010100011 +0000000110111XXXXXXXX0000000000001111010100011 +0000000110101XXXXXXXX0000000000001111010100011 +0000000110110XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +0000000110011XXXXXXXX0000000000001111010100011 +0000000110111XXXXXXXX0000000000001111010100011 +0000000111001XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2000 Timestamp 80000 ns +0000000110011XXXXXXXX0000000000001111010100011 +0000000111011XXXXXXXX0000000000001111010100011 +0000000110110XXXXXXXX0000000000001111010100011 +0000000110111XXXXXXXX0000000000001111010100011 +0000000111011XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +0000000111001XXXXXXXX0000000000001111010100011 +0000000110100XXXXXXXX0000000000001111010100011 +0000000111011XXXXXXXX0000000000001111010100011 +0000000110110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2010 Timestamp 80400 ns +0000000111110XXXXXXXX0000000000001111010100011 +0000000110110XXXXXXXX0000000000001111010100011 +0000000110111XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +0000000111001XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +0000000110110XXXXXXXX0000000000001111010100011 +0000000111100XXXXXXXX0000000000001111010100011 +0000000111010XXXXXXXX0000000000001111010100011 +0000000111110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2020 Timestamp 80800 ns +0000000110010XXXXXXXX0000000000001111010100011 +0000000110000XXXXXXXX0000000000001111010100011 +0000000110100XXXXXXXX0000000000001111010100011 +0000000111000XXXXXXXX0000000000001111010100011 +0000000111001XXXXXXXX0000000000001111010100011 +0000000111010XXXXXXXX0000000000001111010100011 +0000000111010XXXXXXXX0000000000001111010100011 +0000000111100XXXXXXXX0000000000001111010100011 +0000000111000XXXXXXXX0000000000001111010100011 +0000000111110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2030 Timestamp 81200 ns +0000000111011XXXXXXXX0000000000001111010100011 +0000000111001XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +0000000111011XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +0000000111100XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +0000000111111XXXXXXXX0000000000001111010100011 +0000000111100XXXXXXXX0000000000001111010100011 +0000000111011XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2040 Timestamp 81600 ns +0000000111010XXXXXXXX0000000000001111010100011 +0000000111011XXXXXXXX0000000000001111010100011 +0000000111100XXXXXXXX0000000000001111010100011 +0000000111110XXXXXXXX0000000000001111010100011 +0000000110011XXXXXXXX0000000000001111010100011 +0000000110100XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +0000000110101XXXXXXXX0000000000001111010100011 +0000000110011XXXXXXXX0000000000001111010100011 +0000000110010XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2050 Timestamp 82000 ns +0000000111111XXXXXXXX0000000000001111010100011 +0000000110101XXXXXXXX0000000000001111010100011 +0000000111110XXXXXXXX0000000000001111010100011 +0000000111110XXXXXXXX0000000000001111010100011 +1010100100101XXXXXXXX1011000000001111110101011 +// Pattern 6 Cycle 2055 Timestamp 82200 ns +000000000000000000000000000001000110000 // Start Pattern (6) MSG +1010100111101XXXXXXXX0000000000001111010100011 +1010100111111XXXXXXXX0000000000001111010100011 +1010100110000XXXXXXXX0000000000001111010100011 +1010100111001XXXXXXXX0000000000001111010100011 +1010100111000XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2060 Timestamp 82400 ns +1010100110101XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +1010100111010XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +1010100110001XXXXXXXX0000000000001111010100011 +1010100110000XXXXXXXX0000000000001111010100011 +1010100111110XXXXXXXX0000000000001111010100011 +1010100111111XXXXXXXX0000000000001111010100011 +1010100110001XXXXXXXX0000000000001111010100011 +1010100110011XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2070 Timestamp 82800 ns +1010100111100XXXXXXXX0000000000001111010100011 +1010100111011XXXXXXXX0000000000001111010100011 +1010100110111XXXXXXXX0000000000001111010100011 +1010100110100XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +1010100110000XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +1010100110010XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +1010100110110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2080 Timestamp 83200 ns +1010100111000XXXXXXXX0000000000001111010100011 +1010100111000XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100110001XXXXXXXX0000000000001111010100011 +1010100110010XXXXXXXX0000000000001111010100011 +1010100110010XXXXXXXX0000000000001111010100011 +1010100110111XXXXXXXX0000000000001111010100011 +1010100111010XXXXXXXX0000000000001111010100011 +1010100110001XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2090 Timestamp 83600 ns +1010100110111XXXXXXXX0000000000001111010100011 +1010100111111XXXXXXXX0000000000001111010100011 +1010100110111XXXXXXXX0000000000001111010100011 +1010100110010XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100110100XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +1010100110010XXXXXXXX0000000000001111010100011 +1010100111001XXXXXXXX0000000000001111010100011 +1010100111010XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2100 Timestamp 84000 ns +1010100110000XXXXXXXX0000000000001111010100011 +1010100110100XXXXXXXX0000000000001111010100011 +1010100111010XXXXXXXX0000000000001111010100011 +1010100111001XXXXXXXX0000000000001111010100011 +1010100111111XXXXXXXX0000000000001111010100011 +1010100110001XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100110001XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +1010100110001XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2110 Timestamp 84400 ns +1010100111111XXXXXXXX0000000000001111010100011 +1010100111110XXXXXXXX0000000000001111010100011 +1010100110010XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +1010100110111XXXXXXXX0000000000001111010100011 +1010100111010XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100111001XXXXXXXX0000000000001111010100011 +1010100110001XXXXXXXX0000000000001111010100011 +1010100110011XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2120 Timestamp 84800 ns +1010100110111XXXXXXXX0000000000001111010100011 +1010100111011XXXXXXXX0000000000001111010100011 +1010100110100XXXXXXXX0000000000001111010100011 +1010100111011XXXXXXXX0000000000001111010100011 +1010100110110XXXXXXXX0000000000001111010100011 +1010100110111XXXXXXXX0000000000001111010100011 +1010100111001XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +1010100110101XXXXXXXX0000000000001111010100011 +1010100110010XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2130 Timestamp 85200 ns +1010100111111XXXXXXXX0000000000001111010100011 +1010100111001XXXXXXXX0000000000001111010100011 +1010100111110XXXXXXXX0000000000001111010100011 +1010100110110XXXXXXXX0000000000001111010100011 +1010100111011XXXXXXXX0000000000001111010100011 +1010100110111XXXXXXXX0000000000001111010100011 +1010100111001XXXXXXXX0000000000001111010100011 +1010100110011XXXXXXXX0000000000001111010100011 +1010100111000XXXXXXXX0000000000001111010100011 +1010100110100XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2140 Timestamp 85600 ns +1010100110101XXXXXXXX0000000000001111010100011 +1010100111110XXXXXXXX0000000000001111010100011 +1010100110000XXXXXXXX0000000000001111010100011 +1010100111000XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +1010100111111XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100110010XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +1010100111011XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2150 Timestamp 86000 ns +1010100110111XXXXXXXX0000000000001111010100011 +1010100111110XXXXXXXX0000000000001111010100011 +1010100111111XXXXXXXX0000000000001111010100011 +1010100110100XXXXXXXX0000000000001111010100011 +1010100110010XXXXXXXX0000000000001111010100011 +1010100111111XXXXXXXX0000000000001111010100011 +1010100111010XXXXXXXX0000000000001111010100011 +1010100110010XXXXXXXX0000000000001111010100011 +1010100110001XXXXXXXX0000000000001111010100011 +1010100111010XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2160 Timestamp 86400 ns +1010100110001XXXXXXXX0000000000001111010100011 +1010100110011XXXXXXXX0000000000001111010100011 +1010100110000XXXXXXXX0000000000001111010100011 +1010100111011XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100110011XXXXXXXX0000000000001111010100011 +1010100110110XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100110111XXXXXXXX0000000000001111010100011 +1010100110111XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2170 Timestamp 86800 ns +1010100111110XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +1010100111111XXXXXXXX0000000000001111010100011 +1010100111110XXXXXXXX0000000000001111010100011 +1010100111001XXXXXXXX0000000000001111010100011 +1010100111111XXXXXXXX0000000000001111010100011 +1010100111011XXXXXXXX0000000000001111010100011 +1010100111111XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +1010100110111XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2180 Timestamp 87200 ns +1010100111001XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +1010100110010XXXXXXXX0000000000001111010100011 +1010100111001XXXXXXXX0000000000001111010100011 +1010100110101XXXXXXXX0000000000001111010100011 +1010100111001XXXXXXXX0000000000001111010100011 +1010100111010XXXXXXXX0000000000001111010100011 +1010100110011XXXXXXXX0000000000001111010100011 +1010100110111XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2190 Timestamp 87600 ns +1010100111001XXXXXXXX0000000000001111010100011 +1010100110111XXXXXXXX0000000000001111010100011 +1010100111110XXXXXXXX0000000000001111010100011 +1010100111111XXXXXXXX0000000000001111010100011 +1010100111011XXXXXXXX0000000000001111010100011 +1010100111010XXXXXXXX0000000000001111010100011 +1010100111011XXXXXXXX0000000000001111010100011 +1010100110000XXXXXXXX0000000000001111010100011 +1010100111011XXXXXXXX0000000000001111010100011 +1010100111010XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2200 Timestamp 88000 ns +1010100111010XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +1010100110010XXXXXXXX0000000000001111010100011 +1010100111010XXXXXXXX0000000000001111010100011 +1010100111001XXXXXXXX0000000000001111010100011 +1010100110011XXXXXXXX0000000000001111010100011 +1010100110011XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +1010100110001XXXXXXXX0000000000001111010100011 +1010100110100XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2210 Timestamp 88400 ns +1010100110001XXXXXXXX0000000000001111010100011 +1010100111111XXXXXXXX0000000000001111010100011 +1010100111010XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100111111XXXXXXXX0000000000001111010100011 +1010100110000XXXXXXXX0000000000001111010100011 +1010100110101XXXXXXXX0000000000001111010100011 +1010100110110XXXXXXXX0000000000001111010100011 +1010100110101XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2220 Timestamp 88800 ns +1010100111010XXXXXXXX0000000000001111010100011 +1010100110110XXXXXXXX0000000000001111010100011 +1010100111011XXXXXXXX0000000000001111010100011 +1010100110100XXXXXXXX0000000000001111010100011 +1010100111011XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100110110XXXXXXXX0000000000001111010100011 +1010100111110XXXXXXXX0000000000001111010100011 +1010100110100XXXXXXXX0000000000001111010100011 +1010100111110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2230 Timestamp 89200 ns +1010100110111XXXXXXXX0000000000001111010100011 +1010100111001XXXXXXXX0000000000001111010100011 +1010100111011XXXXXXXX0000000000001111010100011 +1010100110101XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100111011XXXXXXXX0000000000001111010100011 +1010100111110XXXXXXXX0000000000001111010100011 +1010100111111XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100111010XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2240 Timestamp 89600 ns +1010100111110XXXXXXXX0000000000001111010100011 +1010100111110XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +1010100111000XXXXXXXX0000000000001111010100011 +1010100110111XXXXXXXX0000000000001111010100011 +1010100110111XXXXXXXX0000000000001111010100011 +1010100110001XXXXXXXX0000000000001111010100011 +1010100110010XXXXXXXX0000000000001111010100011 +1010100111010XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2250 Timestamp 90000 ns +1010100110110XXXXXXXX0000000000001111010100011 +1010100110111XXXXXXXX0000000000001111010100011 +1010100111110XXXXXXXX0000000000001111010100011 +1010100111000XXXXXXXX0000000000001111010100011 +1010100110000XXXXXXXX0000000000001111010100011 +1010100111010XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100111110XXXXXXXX0000000000001111010100011 +1010100110010XXXXXXXX0000000000001111010100011 +1010100111010XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2260 Timestamp 90400 ns +1010100111110XXXXXXXX0000000000001111010100011 +1010100110011XXXXXXXX0000000000001111010100011 +1010100110111XXXXXXXX0000000000001111010100011 +1010100111110XXXXXXXX0000000000001111010100011 +1010100110101XXXXXXXX0000000000001111010100011 +1010100110000XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +1010100111110XXXXXXXX0000000000001111010100011 +1010100110101XXXXXXXX0000000000001111010100011 +1010100110001XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2270 Timestamp 90800 ns +1010100110001XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100110110XXXXXXXX0000000000001111010100011 +1010100111010XXXXXXXX0000000000001111010100011 +1010100110101XXXXXXXX0000000000001111010100011 +1010100111110XXXXXXXX0000000000001111010100011 +1010100111110XXXXXXXX0000000000001111010100011 +1010100111111XXXXXXXX0000000000001111010100011 +1010100111011XXXXXXXX0000000000001111010100011 +1010100110100XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2280 Timestamp 91200 ns +1010100111111XXXXXXXX0000000000001111010100011 +1010100110001XXXXXXXX0000000000001111010100011 +1010100111110XXXXXXXX0000000000001111010100011 +1010100111111XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +1010100111011XXXXXXXX0000000000001111010100011 +1010100111111XXXXXXXX0000000000001111010100011 +1010100111011XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2290 Timestamp 91600 ns +1010100111011XXXXXXXX0000000000001111010100011 +1010100111110XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100111111XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100111011XXXXXXXX0000000000001111010100011 +1010100111011XXXXXXXX0000000000001111010100011 +1010100110000XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +1010100111000XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2300 Timestamp 92000 ns +1010100111111XXXXXXXX0000000000001111010100011 +1010100110011XXXXXXXX0000000000001111010100011 +1010100111110XXXXXXXX0000000000001111010100011 +1010100111111XXXXXXXX0000000000001111010100011 +1010100110001XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100110001XXXXXXXX0000000000001111010100011 +1010100110111XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2310 Timestamp 92400 ns +1010100111001XXXXXXXX0000000000001111010100011 +1111110101000XXXXXXXX1101000000001111110101011 +// Pattern 7 Cycle 2312 Timestamp 92480 ns +000000000000000000000000000001000110000 // Start Pattern (7) MSG +1111110110111XXXXXXXX0000000000001111010100011 +1111110111001XXXXXXXX0000000000001111010100011 +1111110110111XXXXXXXX0000000000001111010100011 +1111110111110XXXXXXXX0000000000001111010100011 +1111110110101XXXXXXXX0000000000001111010100011 +1111110111111XXXXXXXX0000000000001111010100011 +1111110111001XXXXXXXX0000000000001111010100011 +1111110110110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2320 Timestamp 92800 ns +1111110110101XXXXXXXX0000000000001111010100011 +1111110111101XXXXXXXX0000000000001111010100011 +1111110110100XXXXXXXX0000000000001111010100011 +1111110111000XXXXXXXX0000000000001111010100011 +1111110110010XXXXXXXX0000000000001111010100011 +1111110111111XXXXXXXX0000000000001111010100011 +1111110110011XXXXXXXX0000000000001111010100011 +1111110110110XXXXXXXX0000000000001111010100011 +1111110110110XXXXXXXX0000000000001111010100011 +1111110111010XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2330 Timestamp 93200 ns +1111110110010XXXXXXXX0000000000001111010100011 +1111110110011XXXXXXXX0000000000001111010100011 +1111110110111XXXXXXXX0000000000001111010100011 +1111110111001XXXXXXXX0000000000001111010100011 +1111110110100XXXXXXXX0000000000001111010100011 +1111110111001XXXXXXXX0000000000001111010100011 +1111110110011XXXXXXXX0000000000001111010100011 +1111110111110XXXXXXXX0000000000001111010100011 +1111110111110XXXXXXXX0000000000001111010100011 +1111110111010XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2340 Timestamp 93600 ns +1111110110100XXXXXXXX0000000000001111010100011 +1111110110111XXXXXXXX0000000000001111010100011 +1111110111000XXXXXXXX0000000000001111010100011 +1111110111001XXXXXXXX0000000000001111010100011 +1111110111100XXXXXXXX0000000000001111010100011 +1111110110100XXXXXXXX0000000000001111010100011 +1111110111111XXXXXXXX0000000000001111010100011 +1111110111110XXXXXXXX0000000000001111010100011 +1111110111100XXXXXXXX0000000000001111010100011 +1111110110111XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2350 Timestamp 94000 ns +1111110111101XXXXXXXX0000000000001111010100011 +1111110111111XXXXXXXX0000000000001111010100011 +1111110110100XXXXXXXX0000000000001111010100011 +1111110110101XXXXXXXX0000000000001111010100011 +1111110110101XXXXXXXX0000000000001111010100011 +1111110111010XXXXXXXX0000000000001111010100011 +1111110111100XXXXXXXX0000000000001111010100011 +1111110111110XXXXXXXX0000000000001111010100011 +1111110110101XXXXXXXX0000000000001111010100011 +1111110111111XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2360 Timestamp 94400 ns +1111110111010XXXXXXXX0000000000001111010100011 +1111110110100XXXXXXXX0000000000001111010100011 +1111110110110XXXXXXXX0000000000001111010100011 +1111110111111XXXXXXXX0000000000001111010100011 +1111110110101XXXXXXXX0000000000001111010100011 +1111110111100XXXXXXXX0000000000001111010100011 +1111110110001XXXXXXXX0000000000001111010100011 +1111110110001XXXXXXXX0000000000001111010100011 +1111110111000XXXXXXXX0000000000001111010100011 +1111110110110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2370 Timestamp 94800 ns +1111110110110XXXXXXXX0000000000001111010100011 +1111110111100XXXXXXXX0000000000001111010100011 +1111110111110XXXXXXXX0000000000001111010100011 +1111110110001XXXXXXXX0000000000001111010100011 +1111110110110XXXXXXXX0000000000001111010100011 +1111110110110XXXXXXXX0000000000001111010100011 +1111110111101XXXXXXXX0000000000001111010100011 +1111110111011XXXXXXXX0000000000001111010100011 +1111110110111XXXXXXXX0000000000001111010100011 +1111110110010XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2380 Timestamp 95200 ns +1111110111101XXXXXXXX0000000000001111010100011 +1111110111111XXXXXXXX0000000000001111010100011 +1111110111111XXXXXXXX0000000000001111010100011 +1111110111111XXXXXXXX0000000000001111010100011 +1111110110000XXXXXXXX0000000000001111010100011 +1111110110100XXXXXXXX0000000000001111010100011 +1111110110101XXXXXXXX0000000000001111010100011 +1111110110111XXXXXXXX0000000000001111010100011 +1111110111100XXXXXXXX0000000000001111010100011 +1111110110000XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2390 Timestamp 95600 ns +1111110111101XXXXXXXX0000000000001111010100011 +1111110111000XXXXXXXX0000000000001111010100011 +1111110111100XXXXXXXX0000000000001111010100011 +1111110110111XXXXXXXX0000000000001111010100011 +1111110111110XXXXXXXX0000000000001111010100011 +1111110111111XXXXXXXX0000000000001111010100011 +1111110110001XXXXXXXX0000000000001111010100011 +1111110110001XXXXXXXX0000000000001111010100011 +1111110110111XXXXXXXX0000000000001111010100011 +1111110111111XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2400 Timestamp 96000 ns +1111110110101XXXXXXXX0000000000001111010100011 +1111110111100XXXXXXXX0000000000001111010100011 +1111110110000XXXXXXXX0000000000001111010100011 +1111110111110XXXXXXXX0000000000001111010100011 +1111110110111XXXXXXXX0000000000001111010100011 +1111110110010XXXXXXXX0000000000001111010100011 +1111110110011XXXXXXXX0000000000001111010100011 +1111110110001XXXXXXXX0000000000001111010100011 +1111110110101XXXXXXXX0000000000001111010100011 +1111110111110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2410 Timestamp 96400 ns +1111110110101XXXXXXXX0000000000001111010100011 +1111110110101XXXXXXXX0000000000001111010100011 +1111110111010XXXXXXXX0000000000001111010100011 +1111110111011XXXXXXXX0000000000001111010100011 +1111110110001XXXXXXXX0000000000001111010100011 +1111110110011XXXXXXXX0000000000001111010100011 +1111110111110XXXXXXXX0000000000001111010100011 +1111110110011XXXXXXXX0000000000001111010100011 +1111110110111XXXXXXXX0000000000001111010100011 +1111110110101XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2420 Timestamp 96800 ns +1111110111110XXXXXXXX0000000000001111010100011 +1111110110010XXXXXXXX0000000000001111010100011 +1111110110011XXXXXXXX0000000000001111010100011 +1111110111111XXXXXXXX0000000000001111010100011 +1111110111001XXXXXXXX0000000000001111010100011 +1111110110010XXXXXXXX0000000000001111010100011 +1111110111100XXXXXXXX0000000000001111010100011 +1111110111010XXXXXXXX0000000000001111010100011 +1111110110000XXXXXXXX0000000000001111010100011 +1111110110111XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2430 Timestamp 97200 ns +1111110110101XXXXXXXX0000000000001111010100011 +1111110111110XXXXXXXX0000000000001111010100011 +1111110110110XXXXXXXX0000000000001111010100011 +1111110110111XXXXXXXX0000000000001111010100011 +1111110111001XXXXXXXX0000000000001111010100011 +1111110110100XXXXXXXX0000000000001111010100011 +1111110111110XXXXXXXX0000000000001111010100011 +1111110111010XXXXXXXX0000000000001111010100011 +1111110111010XXXXXXXX0000000000001111010100011 +1111110111100XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2440 Timestamp 97600 ns +1111110111110XXXXXXXX0000000000001111010100011 +1111110110001XXXXXXXX0000000000001111010100011 +1111110110010XXXXXXXX0000000000001111010100011 +1111110110010XXXXXXXX0000000000001111010100011 +1111110110011XXXXXXXX0000000000001111010100011 +1111110110100XXXXXXXX0000000000001111010100011 +1111110111011XXXXXXXX0000000000001111010100011 +1111110110001XXXXXXXX0000000000001111010100011 +1111110110001XXXXXXXX0000000000001111010100011 +1111110110111XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2450 Timestamp 98000 ns +1111110110010XXXXXXXX0000000000001111010100011 +1111110110101XXXXXXXX0000000000001111010100011 +1111110111111XXXXXXXX0000000000001111010100011 +1111110111111XXXXXXXX0000000000001111010100011 +1111110110100XXXXXXXX0000000000001111010100011 +1111110111100XXXXXXXX0000000000001111010100011 +1111110110000XXXXXXXX0000000000001111010100011 +1111110111011XXXXXXXX0000000000001111010100011 +1111110110011XXXXXXXX0000000000001111010100011 +1111110111010XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2460 Timestamp 98400 ns +1111110110001XXXXXXXX0000000000001111010100011 +1111110110011XXXXXXXX0000000000001111010100011 +1111110110011XXXXXXXX0000000000001111010100011 +1111110110001XXXXXXXX0000000000001111010100011 +1111110111100XXXXXXXX0000000000001111010100011 +1111110110110XXXXXXXX0000000000001111010100011 +1111110110100XXXXXXXX0000000000001111010100011 +1111110111010XXXXXXXX0000000000001111010100011 +1111110111001XXXXXXXX0000000000001111010100011 +1111110110011XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2470 Timestamp 98800 ns +1111110111111XXXXXXXX0000000000001111010100011 +1111110111100XXXXXXXX0000000000001111010100011 +1111110110011XXXXXXXX0000000000001111010100011 +1111110110010XXXXXXXX0000000000001111010100011 +1111110111101XXXXXXXX0000000000001111010100011 +1111110110001XXXXXXXX0000000000001111010100011 +1111110111001XXXXXXXX0000000000001111010100011 +1111110111000XXXXXXXX0000000000001111010100011 +1111110111111XXXXXXXX0000000000001111010100011 +1111110110001XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2480 Timestamp 99200 ns +1111110110110XXXXXXXX0000000000001111010100011 +1111110111000XXXXXXXX0000000000001111010100011 +1111110111001XXXXXXXX0000000000001111010100011 +1111110110100XXXXXXXX0000000000001111010100011 +1111110110000XXXXXXXX0000000000001111010100011 +1111110110110XXXXXXXX0000000000001111010100011 +1111110110111XXXXXXXX0000000000001111010100011 +1111110111011XXXXXXXX0000000000001111010100011 +1111110110011XXXXXXXX0000000000001111010100011 +1111110110110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2490 Timestamp 99600 ns +1111110111100XXXXXXXX0000000000001111010100011 +1111110110000XXXXXXXX0000000000001111010100011 +1111110111011XXXXXXXX0000000000001111010100011 +1111110111110XXXXXXXX0000000000001111010100011 +1111110111111XXXXXXXX0000000000001111010100011 +1111110111100XXXXXXXX0000000000001111010100011 +1111110111011XXXXXXXX0000000000001111010100011 +1111110110001XXXXXXXX0000000000001111010100011 +1111110111000XXXXXXXX0000000000001111010100011 +1111110111000XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2500 Timestamp 100000 ns +1111110110010XXXXXXXX0000000000001111010100011 +1111110110011XXXXXXXX0000000000001111010100011 +1111110110001XXXXXXXX0000000000001111010100011 +1111110110011XXXXXXXX0000000000001111010100011 +1111110110101XXXXXXXX0000000000001111010100011 +1111110111111XXXXXXXX0000000000001111010100011 +1111110110000XXXXXXXX0000000000001111010100011 +1111110111110XXXXXXXX0000000000001111010100011 +1111110111001XXXXXXXX0000000000001111010100011 +1111110111111XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2510 Timestamp 100400 ns +1111110110001XXXXXXXX0000000000001111010100011 +1111110110001XXXXXXXX0000000000001111010100011 +1111110111011XXXXXXXX0000000000001111010100011 +1111110110111XXXXXXXX0000000000001111010100011 +1111110110100XXXXXXXX0000000000001111010100011 +1111110110010XXXXXXXX0000000000001111010100011 +1111110110011XXXXXXXX0000000000001111010100011 +1111110110011XXXXXXXX0000000000001111010100011 +1111110111110XXXXXXXX0000000000001111010100011 +1111110111111XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2520 Timestamp 100800 ns +1111110110100XXXXXXXX0000000000001111010100011 +1111110110010XXXXXXXX0000000000001111010100011 +1111110111001XXXXXXXX0000000000001111010100011 +1111110110010XXXXXXXX0000000000001111010100011 +1111110110011XXXXXXXX0000000000001111010100011 +1111110110001XXXXXXXX0000000000001111010100011 +1111110110010XXXXXXXX0000000000001111010100011 +1111110110111XXXXXXXX0000000000001111010100011 +1111110110011XXXXXXXX0000000000001111010100011 +1111110111010XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2530 Timestamp 101200 ns +1111110110001XXXXXXXX0000000000001111010100011 +1111110111001XXXXXXXX0000000000001111010100011 +1111110110111XXXXXXXX0000000000001111010100011 +1111110111010XXXXXXXX0000000000001111010100011 +1111110110010XXXXXXXX0000000000001111010100011 +1111110110101XXXXXXXX0000000000001111010100011 +1111110111111XXXXXXXX0000000000001111010100011 +1111110111111XXXXXXXX0000000000001111010100011 +1111110110111XXXXXXXX0000000000001111010100011 +1111110111011XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2540 Timestamp 101600 ns +1111110111111XXXXXXXX0000000000001111010100011 +1111110111001XXXXXXXX0000000000001111010100011 +1111110111111XXXXXXXX0000000000001111010100011 +1111110111111XXXXXXXX0000000000001111010100011 +1111110111010XXXXXXXX0000000000001111010100011 +1111110111110XXXXXXXX0000000000001111010100011 +1111110111111XXXXXXXX0000000000001111010100011 +1111110111111XXXXXXXX0000000000001111010100011 +1111110111110XXXXXXXX0000000000001111010100011 +1111110111100XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2550 Timestamp 102000 ns +1111110111110XXXXXXXX0000000000001111010100011 +1111110111111XXXXXXXX0000000000001111010100011 +1111110111000XXXXXXXX0000000000001111010100011 +1111110111010XXXXXXXX0000000000001111010100011 +1111110111000XXXXXXXX0000000000001111010100011 +1111110111110XXXXXXXX0000000000001111010100011 +1111110111111XXXXXXXX0000000000001111010100011 +1111110110011XXXXXXXX0000000000001111010100011 +1111110111110XXXXXXXX0000000000001111010100011 +1111110111101XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2560 Timestamp 102400 ns +1111110111001XXXXXXXX0000000000001111010100011 +1111110110111XXXXXXXX0000000000001111010100011 +1111110111010XXXXXXXX0000000000001111010100011 +1111110110001XXXXXXXX0000000000001111010100011 +1111110111010XXXXXXXX0000000000001111010100011 +1111110111010XXXXXXXX0000000000001111010100011 +1111110110010XXXXXXXX0000000000001111010100011 +1111110111100XXXXXXXX0000000000001111010100011 +0101010100110XXXXXXXX0111000000001111110101011 +// Pattern 8 Cycle 2569 Timestamp 102760 ns +000000000000000000000000000001000110000 // Start Pattern (8) MSG +0101010111000XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2570 Timestamp 102800 ns +0101010110101XXXXXXXX0000000000001111010100011 +0101010111000XXXXXXXX0000000000001111010100011 +0101010111101XXXXXXXX0000000000001111010100011 +0101010110001XXXXXXXX0000000000001111010100011 +0101010111100XXXXXXXX0000000000001111010100011 +0101010111011XXXXXXXX0000000000001111010100011 +0101010110010XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010111100XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2580 Timestamp 103200 ns +0101010111111XXXXXXXX0000000000001111010100011 +0101010111000XXXXXXXX0000000000001111010100011 +0101010111000XXXXXXXX0000000000001111010100011 +0101010110100XXXXXXXX0000000000001111010100011 +0101010110001XXXXXXXX0000000000001111010100011 +0101010110101XXXXXXXX0000000000001111010100011 +0101010110011XXXXXXXX0000000000001111010100011 +0101010111100XXXXXXXX0000000000001111010100011 +0101010111001XXXXXXXX0000000000001111010100011 +0101010111011XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2590 Timestamp 103600 ns +0101010110111XXXXXXXX0000000000001111010100011 +0101010110111XXXXXXXX0000000000001111010100011 +0101010110100XXXXXXXX0000000000001111010100011 +0101010110010XXXXXXXX0000000000001111010100011 +0101010110100XXXXXXXX0000000000001111010100011 +0101010111100XXXXXXXX0000000000001111010100011 +0101010111110XXXXXXXX0000000000001111010100011 +0101010111110XXXXXXXX0000000000001111010100011 +0101010110010XXXXXXXX0000000000001111010100011 +0101010111010XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2600 Timestamp 104000 ns +0101010111111XXXXXXXX0000000000001111010100011 +0101010110001XXXXXXXX0000000000001111010100011 +0101010111110XXXXXXXX0000000000001111010100011 +0101010111100XXXXXXXX0000000000001111010100011 +0101010110111XXXXXXXX0000000000001111010100011 +0101010110001XXXXXXXX0000000000001111010100011 +0101010110101XXXXXXXX0000000000001111010100011 +0101010111101XXXXXXXX0000000000001111010100011 +0101010110011XXXXXXXX0000000000001111010100011 +0101010111011XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2610 Timestamp 104400 ns +0101010110111XXXXXXXX0000000000001111010100011 +0101010110101XXXXXXXX0000000000001111010100011 +0101010111011XXXXXXXX0000000000001111010100011 +0101010110110XXXXXXXX0000000000001111010100011 +0101010111100XXXXXXXX0000000000001111010100011 +0101010111001XXXXXXXX0000000000001111010100011 +0101010111010XXXXXXXX0000000000001111010100011 +0101010111101XXXXXXXX0000000000001111010100011 +0101010111110XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2620 Timestamp 104800 ns +0101010110001XXXXXXXX0000000000001111010100011 +0101010110011XXXXXXXX0000000000001111010100011 +0101010111011XXXXXXXX0000000000001111010100011 +0101010111101XXXXXXXX0000000000001111010100011 +0101010110010XXXXXXXX0000000000001111010100011 +0101010111110XXXXXXXX0000000000001111010100011 +0101010111110XXXXXXXX0000000000001111010100011 +0101010111011XXXXXXXX0000000000001111010100011 +0101010110110XXXXXXXX0000000000001111010100011 +0101010110110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2630 Timestamp 105200 ns +0101010111011XXXXXXXX0000000000001111010100011 +0101010111000XXXXXXXX0000000000001111010100011 +0101010111100XXXXXXXX0000000000001111010100011 +0101010111100XXXXXXXX0000000000001111010100011 +0101010111100XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010111101XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010110011XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2640 Timestamp 105600 ns +0101010111001XXXXXXXX0000000000001111010100011 +0101010110111XXXXXXXX0000000000001111010100011 +0101010111100XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010111100XXXXXXXX0000000000001111010100011 +0101010110110XXXXXXXX0000000000001111010100011 +0101010111110XXXXXXXX0000000000001111010100011 +0101010110101XXXXXXXX0000000000001111010100011 +0101010111010XXXXXXXX0000000000001111010100011 +0101010111011XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2650 Timestamp 106000 ns +0101010111111XXXXXXXX0000000000001111010100011 +0101010111100XXXXXXXX0000000000001111010100011 +0101010110011XXXXXXXX0000000000001111010100011 +0101010111110XXXXXXXX0000000000001111010100011 +0101010110011XXXXXXXX0000000000001111010100011 +0101010111110XXXXXXXX0000000000001111010100011 +0101010110011XXXXXXXX0000000000001111010100011 +0101010111101XXXXXXXX0000000000001111010100011 +0101010111101XXXXXXXX0000000000001111010100011 +0101010111110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2660 Timestamp 106400 ns +0101010111000XXXXXXXX0000000000001111010100011 +0101010111010XXXXXXXX0000000000001111010100011 +0101010111110XXXXXXXX0000000000001111010100011 +0101010111101XXXXXXXX0000000000001111010100011 +0101010111010XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010110111XXXXXXXX0000000000001111010100011 +0101010111101XXXXXXXX0000000000001111010100011 +0101010111010XXXXXXXX0000000000001111010100011 +0101010110100XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2670 Timestamp 106800 ns +0101010111010XXXXXXXX0000000000001111010100011 +0101010110011XXXXXXXX0000000000001111010100011 +0101010111100XXXXXXXX0000000000001111010100011 +0101010110110XXXXXXXX0000000000001111010100011 +0101010110111XXXXXXXX0000000000001111010100011 +0101010110011XXXXXXXX0000000000001111010100011 +0101010111100XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010110100XXXXXXXX0000000000001111010100011 +0101010110001XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2680 Timestamp 107200 ns +0101010111111XXXXXXXX0000000000001111010100011 +0101010111110XXXXXXXX0000000000001111010100011 +0101010110001XXXXXXXX0000000000001111010100011 +0101010110000XXXXXXXX0000000000001111010100011 +0101010111101XXXXXXXX0000000000001111010100011 +0101010110011XXXXXXXX0000000000001111010100011 +0101010110010XXXXXXXX0000000000001111010100011 +0101010111010XXXXXXXX0000000000001111010100011 +0101010111100XXXXXXXX0000000000001111010100011 +0101010110111XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2690 Timestamp 107600 ns +0101010110011XXXXXXXX0000000000001111010100011 +0101010111101XXXXXXXX0000000000001111010100011 +0101010110001XXXXXXXX0000000000001111010100011 +0101010111010XXXXXXXX0000000000001111010100011 +0101010110001XXXXXXXX0000000000001111010100011 +0101010110001XXXXXXXX0000000000001111010100011 +0101010111100XXXXXXXX0000000000001111010100011 +0101010111001XXXXXXXX0000000000001111010100011 +0101010110010XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2700 Timestamp 108000 ns +0101010110101XXXXXXXX0000000000001111010100011 +0101010111001XXXXXXXX0000000000001111010100011 +0101010111101XXXXXXXX0000000000001111010100011 +0101010111110XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010111101XXXXXXXX0000000000001111010100011 +0101010110010XXXXXXXX0000000000001111010100011 +0101010110111XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010111000XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2710 Timestamp 108400 ns +0101010111101XXXXXXXX0000000000001111010100011 +0101010110101XXXXXXXX0000000000001111010100011 +0101010111100XXXXXXXX0000000000001111010100011 +0101010110110XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010110011XXXXXXXX0000000000001111010100011 +0101010111100XXXXXXXX0000000000001111010100011 +0101010111101XXXXXXXX0000000000001111010100011 +0101010110101XXXXXXXX0000000000001111010100011 +0101010111101XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2720 Timestamp 108800 ns +0101010110010XXXXXXXX0000000000001111010100011 +0101010110010XXXXXXXX0000000000001111010100011 +0101010110100XXXXXXXX0000000000001111010100011 +0101010111010XXXXXXXX0000000000001111010100011 +0101010111100XXXXXXXX0000000000001111010100011 +0101010111011XXXXXXXX0000000000001111010100011 +0101010111000XXXXXXXX0000000000001111010100011 +0101010110100XXXXXXXX0000000000001111010100011 +0101010110010XXXXXXXX0000000000001111010100011 +0101010110001XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2730 Timestamp 109200 ns +0101010110110XXXXXXXX0000000000001111010100011 +0101010111101XXXXXXXX0000000000001111010100011 +0101010110101XXXXXXXX0000000000001111010100011 +0101010111010XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010111001XXXXXXXX0000000000001111010100011 +0101010111010XXXXXXXX0000000000001111010100011 +0101010110101XXXXXXXX0000000000001111010100011 +0101010111100XXXXXXXX0000000000001111010100011 +0101010111011XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2740 Timestamp 109600 ns +0101010111100XXXXXXXX0000000000001111010100011 +0101010110001XXXXXXXX0000000000001111010100011 +0101010110000XXXXXXXX0000000000001111010100011 +0101010110011XXXXXXXX0000000000001111010100011 +0101010111011XXXXXXXX0000000000001111010100011 +0101010111001XXXXXXXX0000000000001111010100011 +0101010110111XXXXXXXX0000000000001111010100011 +0101010111101XXXXXXXX0000000000001111010100011 +0101010110010XXXXXXXX0000000000001111010100011 +0101010110011XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2750 Timestamp 110000 ns +0101010110110XXXXXXXX0000000000001111010100011 +0101010111110XXXXXXXX0000000000001111010100011 +0101010111000XXXXXXXX0000000000001111010100011 +0101010111011XXXXXXXX0000000000001111010100011 +0101010110100XXXXXXXX0000000000001111010100011 +0101010110110XXXXXXXX0000000000001111010100011 +0101010110010XXXXXXXX0000000000001111010100011 +0101010110100XXXXXXXX0000000000001111010100011 +0101010110000XXXXXXXX0000000000001111010100011 +0101010110001XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2760 Timestamp 110400 ns +0101010111101XXXXXXXX0000000000001111010100011 +0101010110011XXXXXXXX0000000000001111010100011 +0101010111001XXXXXXXX0000000000001111010100011 +0101010111011XXXXXXXX0000000000001111010100011 +0101010111110XXXXXXXX0000000000001111010100011 +0101010111110XXXXXXXX0000000000001111010100011 +0101010110110XXXXXXXX0000000000001111010100011 +0101010111011XXXXXXXX0000000000001111010100011 +0101010111100XXXXXXXX0000000000001111010100011 +0101010111011XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2770 Timestamp 110800 ns +0101010111101XXXXXXXX0000000000001111010100011 +0101010111001XXXXXXXX0000000000001111010100011 +0101010110101XXXXXXXX0000000000001111010100011 +0101010110101XXXXXXXX0000000000001111010100011 +0101010110011XXXXXXXX0000000000001111010100011 +0101010110111XXXXXXXX0000000000001111010100011 +0101010110001XXXXXXXX0000000000001111010100011 +0101010110000XXXXXXXX0000000000001111010100011 +0101010111000XXXXXXXX0000000000001111010100011 +0101010111101XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2780 Timestamp 111200 ns +0101010111111XXXXXXXX0000000000001111010100011 +0101010110010XXXXXXXX0000000000001111010100011 +0101010111010XXXXXXXX0000000000001111010100011 +0101010110101XXXXXXXX0000000000001111010100011 +0101010111000XXXXXXXX0000000000001111010100011 +0101010110111XXXXXXXX0000000000001111010100011 +0101010111101XXXXXXXX0000000000001111010100011 +0101010111011XXXXXXXX0000000000001111010100011 +0101010111010XXXXXXXX0000000000001111010100011 +0101010111010XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2790 Timestamp 111600 ns +0101010110100XXXXXXXX0000000000001111010100011 +0101010110010XXXXXXXX0000000000001111010100011 +0101010111011XXXXXXXX0000000000001111010100011 +0101010110000XXXXXXXX0000000000001111010100011 +0101010111010XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010111001XXXXXXXX0000000000001111010100011 +0101010111101XXXXXXXX0000000000001111010100011 +0101010111001XXXXXXXX0000000000001111010100011 +0101010111001XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2800 Timestamp 112000 ns +0101010111100XXXXXXXX0000000000001111010100011 +0101010111000XXXXXXXX0000000000001111010100011 +0101010111010XXXXXXXX0000000000001111010100011 +0101010111110XXXXXXXX0000000000001111010100011 +0101010111010XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010111110XXXXXXXX0000000000001111010100011 +0101010111110XXXXXXXX0000000000001111010100011 +0101010111000XXXXXXXX0000000000001111010100011 +0101010111011XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2810 Timestamp 112400 ns +0101010111111XXXXXXXX0000000000001111010100011 +0101010111100XXXXXXXX0000000000001111010100011 +0101010111010XXXXXXXX0000000000001111010100011 +0101010111101XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010111010XXXXXXXX0000000000001111010100011 +0101010110101XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010110110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2820 Timestamp 112800 ns +0101010111110XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010111111XXXXXXXX0000000000001111010100011 +0101010110001XXXXXXXX0000000000001111010100011 +0101010111101XXXXXXXX0000000000001111010100011 +0000000100001XXXXXXXX1000000000001111110101011 +// Pattern 9 Cycle 2826 Timestamp 113040 ns +000000000000000000000000000001000110000 // Start Pattern (9) MSG +0000000111111XXXXXXXX0000000000001111010100011 +0000000110101XXXXXXXX0000000000001111010100011 +0000000111110XXXXXXXX0000000000001111010100011 +0000000111011XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2830 Timestamp 113200 ns +0000000111101XXXXXXXX0000000000001111010100011 +0000000110111XXXXXXXX0000000000001111010100011 +0000000110111XXXXXXXX0000000000001111010100011 +0000000111111XXXXXXXX0000000000001111010100011 +0000000110100XXXXXXXX0000000000001111010100011 +0000000111001XXXXXXXX0000000000001111010100011 +0000000110111XXXXXXXX0000000000001111010100011 +0000000111000XXXXXXXX0000000000001111010100011 +0000000110100XXXXXXXX0000000000001111010100011 +0000000111111XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2840 Timestamp 113600 ns +0000000110100XXXXXXXX0000000000001111010100011 +0000000111010XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +0000000111011XXXXXXXX0000000000001111010100011 +0000000111010XXXXXXXX0000000000001111010100011 +0000000111000XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +0000000110110XXXXXXXX0000000000001111010100011 +0000000111001XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2850 Timestamp 114000 ns +0000000110100XXXXXXXX0000000000001111010100011 +0000000111010XXXXXXXX0000000000001111010100011 +0000000110101XXXXXXXX0000000000001111010100011 +0000000110001XXXXXXXX0000000000001111010100011 +0000000111001XXXXXXXX0000000000001111010100011 +0000000110011XXXXXXXX0000000000001111010100011 +0000000110111XXXXXXXX0000000000001111010100011 +0000000111111XXXXXXXX0000000000001111010100011 +0000000111000XXXXXXXX0000000000001111010100011 +0000000111100XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2860 Timestamp 114400 ns +0000000111111XXXXXXXX0000000000001111010100011 +0000000110111XXXXXXXX0000000000001111010100011 +0000000110101XXXXXXXX0000000000001111010100011 +0000000110110XXXXXXXX0000000000001111010100011 +0000000110000XXXXXXXX0000000000001111010100011 +0000000111000XXXXXXXX0000000000001111010100011 +0000000111001XXXXXXXX0000000000001111010100011 +0000000110100XXXXXXXX0000000000001111010100011 +0000000110011XXXXXXXX0000000000001111010100011 +0000000110100XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2870 Timestamp 114800 ns +0000000111001XXXXXXXX0000000000001111010100011 +0000000111111XXXXXXXX0000000000001111010100011 +0000000110101XXXXXXXX0000000000001111010100011 +0000000110010XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +0000000111110XXXXXXXX0000000000001111010100011 +0000000111010XXXXXXXX0000000000001111010100011 +0000000110110XXXXXXXX0000000000001111010100011 +0000000110110XXXXXXXX0000000000001111010100011 +0000000110010XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2880 Timestamp 115200 ns +0000000110101XXXXXXXX0000000000001111010100011 +0000000110011XXXXXXXX0000000000001111010100011 +0000000111010XXXXXXXX0000000000001111010100011 +0000000110111XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +0000000110100XXXXXXXX0000000000001111010100011 +0000000111111XXXXXXXX0000000000001111010100011 +0000000111100XXXXXXXX0000000000001111010100011 +0000000111111XXXXXXXX0000000000001111010100011 +0000000111001XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2890 Timestamp 115600 ns +0000000110101XXXXXXXX0000000000001111010100011 +0000000110011XXXXXXXX0000000000001111010100011 +0000000110011XXXXXXXX0000000000001111010100011 +0000000111000XXXXXXXX0000000000001111010100011 +0000000111111XXXXXXXX0000000000001111010100011 +0000000110100XXXXXXXX0000000000001111010100011 +0000000110101XXXXXXXX0000000000001111010100011 +0000000110111XXXXXXXX0000000000001111010100011 +0000000110111XXXXXXXX0000000000001111010100011 +0000000110010XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2900 Timestamp 116000 ns +0000000110100XXXXXXXX0000000000001111010100011 +0000000110011XXXXXXXX0000000000001111010100011 +0000000110000XXXXXXXX0000000000001111010100011 +0000000110001XXXXXXXX0000000000001111010100011 +0000000110110XXXXXXXX0000000000001111010100011 +0000000111100XXXXXXXX0000000000001111010100011 +0000000110010XXXXXXXX0000000000001111010100011 +0000000110111XXXXXXXX0000000000001111010100011 +0000000111011XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2910 Timestamp 116400 ns +0000000110100XXXXXXXX0000000000001111010100011 +0000000110010XXXXXXXX0000000000001111010100011 +0000000110110XXXXXXXX0000000000001111010100011 +0000000111100XXXXXXXX0000000000001111010100011 +0000000111011XXXXXXXX0000000000001111010100011 +0000000111110XXXXXXXX0000000000001111010100011 +0000000111011XXXXXXXX0000000000001111010100011 +0000000110001XXXXXXXX0000000000001111010100011 +0000000110011XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2920 Timestamp 116800 ns +0000000111010XXXXXXXX0000000000001111010100011 +0000000111111XXXXXXXX0000000000001111010100011 +0000000111011XXXXXXXX0000000000001111010100011 +0000000111000XXXXXXXX0000000000001111010100011 +0000000110011XXXXXXXX0000000000001111010100011 +0000000110101XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +0000000111111XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +0000000110001XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2930 Timestamp 117200 ns +0000000110100XXXXXXXX0000000000001111010100011 +0000000110011XXXXXXXX0000000000001111010100011 +0000000111001XXXXXXXX0000000000001111010100011 +0000000110010XXXXXXXX0000000000001111010100011 +0000000111001XXXXXXXX0000000000001111010100011 +0000000111010XXXXXXXX0000000000001111010100011 +0000000111001XXXXXXXX0000000000001111010100011 +0000000110011XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +0000000111100XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2940 Timestamp 117600 ns +0000000111101XXXXXXXX0000000000001111010100011 +0000000111010XXXXXXXX0000000000001111010100011 +0000000110011XXXXXXXX0000000000001111010100011 +0000000111110XXXXXXXX0000000000001111010100011 +0000000110111XXXXXXXX0000000000001111010100011 +0000000110100XXXXXXXX0000000000001111010100011 +0000000111010XXXXXXXX0000000000001111010100011 +0000000111100XXXXXXXX0000000000001111010100011 +0000000110110XXXXXXXX0000000000001111010100011 +0000000111010XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2950 Timestamp 118000 ns +0000000110010XXXXXXXX0000000000001111010100011 +0000000111000XXXXXXXX0000000000001111010100011 +0000000111100XXXXXXXX0000000000001111010100011 +0000000111001XXXXXXXX0000000000001111010100011 +0000000110111XXXXXXXX0000000000001111010100011 +0000000111110XXXXXXXX0000000000001111010100011 +0000000111001XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +0000000110011XXXXXXXX0000000000001111010100011 +0000000110000XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2960 Timestamp 118400 ns +0000000111001XXXXXXXX0000000000001111010100011 +0000000110101XXXXXXXX0000000000001111010100011 +0000000111000XXXXXXXX0000000000001111010100011 +0000000110101XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +0000000110011XXXXXXXX0000000000001111010100011 +0000000110001XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +0000000111100XXXXXXXX0000000000001111010100011 +0000000110010XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2970 Timestamp 118800 ns +0000000111001XXXXXXXX0000000000001111010100011 +0000000110110XXXXXXXX0000000000001111010100011 +0000000111001XXXXXXXX0000000000001111010100011 +0000000111010XXXXXXXX0000000000001111010100011 +0000000110100XXXXXXXX0000000000001111010100011 +0000000110011XXXXXXXX0000000000001111010100011 +0000000110101XXXXXXXX0000000000001111010100011 +0000000110011XXXXXXXX0000000000001111010100011 +0000000111110XXXXXXXX0000000000001111010100011 +0000000110111XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2980 Timestamp 119200 ns +0000000111111XXXXXXXX0000000000001111010100011 +0000000111111XXXXXXXX0000000000001111010100011 +0000000110011XXXXXXXX0000000000001111010100011 +0000000110001XXXXXXXX0000000000001111010100011 +0000000110001XXXXXXXX0000000000001111010100011 +0000000110110XXXXXXXX0000000000001111010100011 +0000000111111XXXXXXXX0000000000001111010100011 +0000000110010XXXXXXXX0000000000001111010100011 +0000000110110XXXXXXXX0000000000001111010100011 +0000000111110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 2990 Timestamp 119600 ns +0000000110100XXXXXXXX0000000000001111010100011 +0000000110011XXXXXXXX0000000000001111010100011 +0000000111001XXXXXXXX0000000000001111010100011 +0000000110001XXXXXXXX0000000000001111010100011 +0000000111001XXXXXXXX0000000000001111010100011 +0000000111000XXXXXXXX0000000000001111010100011 +0000000110001XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +0000000111110XXXXXXXX0000000000001111010100011 +0000000111110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 3000 Timestamp 120000 ns +0000000111100XXXXXXXX0000000000001111010100011 +0000000111000XXXXXXXX0000000000001111010100011 +0000000111110XXXXXXXX0000000000001111010100011 +0000000110011XXXXXXXX0000000000001111010100011 +0000000110101XXXXXXXX0000000000001111010100011 +0000000110100XXXXXXXX0000000000001111010100011 +0000000111110XXXXXXXX0000000000001111010100011 +0000000111011XXXXXXXX0000000000001111010100011 +0000000111111XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +// Simulation Cycle 3010 Timestamp 120400 ns +0000000111001XXXXXXXX0000000000001111010100011 +0000000110111XXXXXXXX0000000000001111010100011 +0000000111100XXXXXXXX0000000000001111010100011 +0000000110011XXXXXXXX0000000000001111010100011 +0000000110011XXXXXXXX0000000000001111010100011 +0000000110001XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +0000000111011XXXXXXXX0000000000001111010100011 +0000000110110XXXXXXXX0000000000001111010100011 +0000000111100XXXXXXXX0000000000001111010100011 +// Simulation Cycle 3020 Timestamp 120800 ns +0000000110000XXXXXXXX0000000000001111010100011 +0000000110110XXXXXXXX0000000000001111010100011 +0000000110111XXXXXXXX0000000000001111010100011 +0000000111110XXXXXXXX0000000000001111010100011 +0000000111100XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +0000000111011XXXXXXXX0000000000001111010100011 +0000000110001XXXXXXXX0000000000001111010100011 +0000000111011XXXXXXXX0000000000001111010100011 +0000000111111XXXXXXXX0000000000001111010100011 +// Simulation Cycle 3030 Timestamp 121200 ns +0000000111101XXXXXXXX0000000000001111010100011 +0000000111011XXXXXXXX0000000000001111010100011 +0000000111100XXXXXXXX0000000000001111010100011 +0000000110111XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +0000000110001XXXXXXXX0000000000001111010100011 +0000000111010XXXXXXXX0000000000001111010100011 +0000000111110XXXXXXXX0000000000001111010100011 +0000000110011XXXXXXXX0000000000001111010100011 +0000000110010XXXXXXXX0000000000001111010100011 +// Simulation Cycle 3040 Timestamp 121600 ns +0000000110001XXXXXXXX0000000000001111010100011 +0000000110100XXXXXXXX0000000000001111010100011 +0000000110101XXXXXXXX0000000000001111010100011 +0000000111110XXXXXXXX0000000000001111010100011 +0000000111011XXXXXXXX0000000000001111010100011 +0000000111110XXXXXXXX0000000000001111010100011 +0000000110011XXXXXXXX0000000000001111010100011 +0000000110010XXXXXXXX0000000000001111010100011 +0000000110011XXXXXXXX0000000000001111010100011 +0000000110110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 3050 Timestamp 122000 ns +0000000111001XXXXXXXX0000000000001111010100011 +0000000110010XXXXXXXX0000000000001111010100011 +0000000110101XXXXXXXX0000000000001111010100011 +0000000111011XXXXXXXX0000000000001111010100011 +0000000111000XXXXXXXX0000000000001111010100011 +0000000111000XXXXXXXX0000000000001111010100011 +0000000111100XXXXXXXX0000000000001111010100011 +0000000111100XXXXXXXX0000000000001111010100011 +0000000111100XXXXXXXX0000000000001111010100011 +0000000111110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 3060 Timestamp 122400 ns +0000000111101XXXXXXXX0000000000001111010100011 +0000000111100XXXXXXXX0000000000001111010100011 +0000000111100XXXXXXXX0000000000001111010100011 +0000000111111XXXXXXXX0000000000001111010100011 +0000000111011XXXXXXXX0000000000001111010100011 +0000000111111XXXXXXXX0000000000001111010100011 +0000000111010XXXXXXXX0000000000001111010100011 +0000000111111XXXXXXXX0000000000001111010100011 +0000000111000XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +// Simulation Cycle 3070 Timestamp 122800 ns +0000000111100XXXXXXXX0000000000001111010100011 +0000000111000XXXXXXXX0000000000001111010100011 +0000000111011XXXXXXXX0000000000001111010100011 +0000000111001XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +0000000111111XXXXXXXX0000000000001111010100011 +0000000111100XXXXXXXX0000000000001111010100011 +0000000110101XXXXXXXX0000000000001111010100011 +0000000111111XXXXXXXX0000000000001111010100011 +0000000110001XXXXXXXX0000000000001111010100011 +// Simulation Cycle 3080 Timestamp 123200 ns +0000000111110XXXXXXXX0000000000001111010100011 +0000000111101XXXXXXXX0000000000001111010100011 +1010100101010XXXXXXXX1111000000001111110101011 +// Last unload +1010100111111XXXXXXXX0000000000001111010100011 +1010100110101XXXXXXXX0000000000001111010100011 +1010100111110XXXXXXXX0000000000001111010100011 +1010100111011XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100110111XXXXXXXX0000000000001111010100011 +1010100110111XXXXXXXX0000000000001111010100011 +// Simulation Cycle 3090 Timestamp 123600 ns +1010100111111XXXXXXXX0000000000001111010100011 +1010100110100XXXXXXXX0000000000001111010100011 +1010100111001XXXXXXXX0000000000001111010100011 +1010100110111XXXXXXXX0000000000001111010100011 +1010100111000XXXXXXXX0000000000001111010100011 +1010100110100XXXXXXXX0000000000001111010100011 +1010100111111XXXXXXXX0000000000001111010100011 +1010100110100XXXXXXXX0000000000001111010100011 +1010100111010XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +// Simulation Cycle 3100 Timestamp 124000 ns +1010100111011XXXXXXXX0000000000001111010100011 +1010100111010XXXXXXXX0000000000001111010100011 +1010100111000XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100110110XXXXXXXX0000000000001111010100011 +1010100111001XXXXXXXX0000000000001111010100011 +1010100110100XXXXXXXX0000000000001111010100011 +1010100111010XXXXXXXX0000000000001111010100011 +1010100110101XXXXXXXX0000000000001111010100011 +// Simulation Cycle 3110 Timestamp 124400 ns +1010100110001XXXXXXXX0000000000001111010100011 +1010100111001XXXXXXXX0000000000001111010100011 +1010100110011XXXXXXXX0000000000001111010100011 +1010100110111XXXXXXXX0000000000001111010100011 +1010100111111XXXXXXXX0000000000001111010100011 +1010100111000XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +1010100111111XXXXXXXX0000000000001111010100011 +1010100110111XXXXXXXX0000000000001111010100011 +1010100110101XXXXXXXX0000000000001111010100011 +// Simulation Cycle 3120 Timestamp 124800 ns +1010100110110XXXXXXXX0000000000001111010100011 +1010100110000XXXXXXXX0000000000001111010100011 +1010100111000XXXXXXXX0000000000001111010100011 +1010100111001XXXXXXXX0000000000001111010100011 +1010100110100XXXXXXXX0000000000001111010100011 +1010100110011XXXXXXXX0000000000001111010100011 +1010100110100XXXXXXXX0000000000001111010100011 +1010100111001XXXXXXXX0000000000001111010100011 +1010100111111XXXXXXXX0000000000001111010100011 +1010100110101XXXXXXXX0000000000001111010100011 +// Simulation Cycle 3130 Timestamp 125200 ns +1010100110010XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100111110XXXXXXXX0000000000001111010100011 +1010100111010XXXXXXXX0000000000001111010100011 +1010100110110XXXXXXXX0000000000001111010100011 +1010100110110XXXXXXXX0000000000001111010100011 +1010100110010XXXXXXXX0000000000001111010100011 +1010100110101XXXXXXXX0000000000001111010100011 +1010100110011XXXXXXXX0000000000001111010100011 +1010100111010XXXXXXXX0000000000001111010100011 +// Simulation Cycle 3140 Timestamp 125600 ns +1010100110111XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100110100XXXXXXXX0000000000001111010100011 +1010100111111XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +1010100111111XXXXXXXX0000000000001111010100011 +1010100111001XXXXXXXX0000000000001111010100011 +1010100110101XXXXXXXX0000000000001111010100011 +1010100110011XXXXXXXX0000000000001111010100011 +1010100110011XXXXXXXX0000000000001111010100011 +// Simulation Cycle 3150 Timestamp 126000 ns +1010100111000XXXXXXXX0000000000001111010100011 +1010100111111XXXXXXXX0000000000001111010100011 +1010100110100XXXXXXXX0000000000001111010100011 +1010100110101XXXXXXXX0000000000001111010100011 +1010100110111XXXXXXXX0000000000001111010100011 +1010100110111XXXXXXXX0000000000001111010100011 +1010100110010XXXXXXXX0000000000001111010100011 +1010100110100XXXXXXXX0000000000001111010100011 +1010100110011XXXXXXXX0000000000001111010100011 +1010100110000XXXXXXXX0000000000001111010100011 +// Simulation Cycle 3160 Timestamp 126400 ns +1010100110001XXXXXXXX0000000000001111010100011 +1010100110110XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +1010100110010XXXXXXXX0000000000001111010100011 +1010100110111XXXXXXXX0000000000001111010100011 +1010100111011XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100110100XXXXXXXX0000000000001111010100011 +1010100110010XXXXXXXX0000000000001111010100011 +1010100110110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 3170 Timestamp 126800 ns +1010100111100XXXXXXXX0000000000001111010100011 +1010100111011XXXXXXXX0000000000001111010100011 +1010100111110XXXXXXXX0000000000001111010100011 +1010100111011XXXXXXXX0000000000001111010100011 +1010100110001XXXXXXXX0000000000001111010100011 +1010100110011XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100111010XXXXXXXX0000000000001111010100011 +1010100111111XXXXXXXX0000000000001111010100011 +1010100111011XXXXXXXX0000000000001111010100011 +// Simulation Cycle 3180 Timestamp 127200 ns +1010100111000XXXXXXXX0000000000001111010100011 +1010100110011XXXXXXXX0000000000001111010100011 +1010100110101XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100111111XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100110001XXXXXXXX0000000000001111010100011 +1010100110100XXXXXXXX0000000000001111010100011 +1010100110011XXXXXXXX0000000000001111010100011 +1010100111001XXXXXXXX0000000000001111010100011 +// Simulation Cycle 3190 Timestamp 127600 ns +1010100110010XXXXXXXX0000000000001111010100011 +1010100111001XXXXXXXX0000000000001111010100011 +1010100111010XXXXXXXX0000000000001111010100011 +1010100111001XXXXXXXX0000000000001111010100011 +1010100110011XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100111010XXXXXXXX0000000000001111010100011 +1010100110011XXXXXXXX0000000000001111010100011 +// Simulation Cycle 3200 Timestamp 128000 ns +1010100111110XXXXXXXX0000000000001111010100011 +1010100110111XXXXXXXX0000000000001111010100011 +1010100110100XXXXXXXX0000000000001111010100011 +1010100111010XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +1010100110110XXXXXXXX0000000000001111010100011 +1010100111010XXXXXXXX0000000000001111010100011 +1010100110010XXXXXXXX0000000000001111010100011 +1010100111000XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +// Simulation Cycle 3210 Timestamp 128400 ns +1010100111001XXXXXXXX0000000000001111010100011 +1010100110111XXXXXXXX0000000000001111010100011 +1010100111110XXXXXXXX0000000000001111010100011 +1010100111001XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100110011XXXXXXXX0000000000001111010100011 +1010100110000XXXXXXXX0000000000001111010100011 +1010100111001XXXXXXXX0000000000001111010100011 +1010100110101XXXXXXXX0000000000001111010100011 +1010100111000XXXXXXXX0000000000001111010100011 +// Simulation Cycle 3220 Timestamp 128800 ns +1010100110101XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100110011XXXXXXXX0000000000001111010100011 +1010100110001XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +1010100110010XXXXXXXX0000000000001111010100011 +1010100111001XXXXXXXX0000000000001111010100011 +1010100110110XXXXXXXX0000000000001111010100011 +1010100111001XXXXXXXX0000000000001111010100011 +// Simulation Cycle 3230 Timestamp 129200 ns +1010100111010XXXXXXXX0000000000001111010100011 +1010100110100XXXXXXXX0000000000001111010100011 +1010100110011XXXXXXXX0000000000001111010100011 +1010100110101XXXXXXXX0000000000001111010100011 +1010100110011XXXXXXXX0000000000001111010100011 +1010100111110XXXXXXXX0000000000001111010100011 +1010100110111XXXXXXXX0000000000001111010100011 +1010100111111XXXXXXXX0000000000001111010100011 +1010100111111XXXXXXXX0000000000001111010100011 +1010100110011XXXXXXXX0000000000001111010100011 +// Simulation Cycle 3240 Timestamp 129600 ns +1010100110001XXXXXXXX0000000000001111010100011 +1010100110001XXXXXXXX0000000000001111010100011 +1010100110110XXXXXXXX0000000000001111010100011 +1010100111111XXXXXXXX0000000000001111010100011 +1010100110010XXXXXXXX0000000000001111010100011 +1010100110110XXXXXXXX0000000000001111010100011 +1010100111110XXXXXXXX0000000000001111010100011 +1010100110100XXXXXXXX0000000000001111010100011 +1010100110011XXXXXXXX0000000000001111010100011 +1010100111001XXXXXXXX0000000000001111010100011 +// Simulation Cycle 3250 Timestamp 130000 ns +1010100110001XXXXXXXX0000000000001111010100011 +1010100111001XXXXXXXX0000000000001111010100011 +1010100111000XXXXXXXX0000000000001111010100011 +1010100110001XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100111110XXXXXXXX0000000000001111010100011 +1010100111110XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +1010100111000XXXXXXXX0000000000001111010100011 +1010100111110XXXXXXXX0000000000001111010100011 +// Simulation Cycle 3260 Timestamp 130400 ns +1010100110011XXXXXXXX0000000000001111010100011 +1010100110101XXXXXXXX0000000000001111010100011 +1010100110100XXXXXXXX0000000000001111010100011 +1010100111110XXXXXXXX0000000000001111010100011 +1010100111011XXXXXXXX0000000000001111010100011 +1010100111111XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100111001XXXXXXXX0000000000001111010100011 +1010100110111XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +// Simulation Cycle 3270 Timestamp 130800 ns +1010100110011XXXXXXXX0000000000001111010100011 +1010100110011XXXXXXXX0000000000001111010100011 +1010100110001XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100111011XXXXXXXX0000000000001111010100011 +1010100110110XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +1010100110000XXXXXXXX0000000000001111010100011 +1010100110110XXXXXXXX0000000000001111010100011 +1010100110111XXXXXXXX0000000000001111010100011 +// Simulation Cycle 3280 Timestamp 131200 ns +1010100111110XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100111011XXXXXXXX0000000000001111010100011 +1010100110001XXXXXXXX0000000000001111010100011 +1010100111011XXXXXXXX0000000000001111010100011 +1010100111111XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100111011XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +// Simulation Cycle 3290 Timestamp 131600 ns +1010100110111XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100110001XXXXXXXX0000000000001111010100011 +1010100111010XXXXXXXX0000000000001111010100011 +1010100111110XXXXXXXX0000000000001111010100011 +1010100110011XXXXXXXX0000000000001111010100011 +1010100110010XXXXXXXX0000000000001111010100011 +1010100110001XXXXXXXX0000000000001111010100011 +1010100110100XXXXXXXX0000000000001111010100011 +1010100110101XXXXXXXX0000000000001111010100011 +// Simulation Cycle 3300 Timestamp 132000 ns +1010100111110XXXXXXXX0000000000001111010100011 +1010100111011XXXXXXXX0000000000001111010100011 +1010100111110XXXXXXXX0000000000001111010100011 +1010100110011XXXXXXXX0000000000001111010100011 +1010100110010XXXXXXXX0000000000001111010100011 +1010100110011XXXXXXXX0000000000001111010100011 +1010100110110XXXXXXXX0000000000001111010100011 +1010100111001XXXXXXXX0000000000001111010100011 +1010100110010XXXXXXXX0000000000001111010100011 +1010100110101XXXXXXXX0000000000001111010100011 +// Simulation Cycle 3310 Timestamp 132400 ns +1010100111011XXXXXXXX0000000000001111010100011 +1010100111000XXXXXXXX0000000000001111010100011 +1010100111000XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +1010100111110XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +// Simulation Cycle 3320 Timestamp 132800 ns +1010100111111XXXXXXXX0000000000001111010100011 +1010100111011XXXXXXXX0000000000001111010100011 +1010100111111XXXXXXXX0000000000001111010100011 +1010100111010XXXXXXXX0000000000001111010100011 +1010100111111XXXXXXXX0000000000001111010100011 +1010100111000XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +1010100111000XXXXXXXX0000000000001111010100011 +1010100111011XXXXXXXX0000000000001111010100011 +// Simulation Cycle 3330 Timestamp 133200 ns +1010100111001XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +1010100111111XXXXXXXX0000000000001111010100011 +1010100111100XXXXXXXX0000000000001111010100011 +1010100110101XXXXXXXX0000000000001111010100011 +1010100111111XXXXXXXX0000000000001111010100011 +1010100110001XXXXXXXX0000000000001111010100011 +1010100111110XXXXXXXX0000000000001111010100011 +1010100111101XXXXXXXX0000000000001111010100011 +// Total count SimulationCycles:3339 Timestamp:133560 ns +// end of Vec file MSG +000000000000000000000000000000110110000 diff --git a/cpu_patterns_serial.v.cfg b/cpu_patterns_serial.v.cfg new file mode 100644 index 0000000..8edfaa3 --- /dev/null +++ b/cpu_patterns_serial.v.cfg @@ -0,0 +1 @@ +cpu_patterns_serial.v.0.vec 3352 11 diff --git a/cpu_patterns_serial.v.info.dict b/cpu_patterns_serial.v.info.dict new file mode 100644 index 0000000..47edfcc --- /dev/null +++ b/cpu_patterns_serial.v.info.dict @@ -0,0 +1,22 @@ +# +# Information Dictionary File produced by Tessent Shell 2023.4-p1 +# Date : Thu May 28 18:01:24 2026 +# +# : (interface) | scan_graybox | full | ijtag_graybox +# : (verilog_2001) | verilog_sv31a + +set pattern_info_dict { + version 1 + pattern_type scan + ssn off + current_mode unwrapped + simulation_design_view { + testbench_language verilog_2001 + testbench_name cpu_cpu_patterns_serial_v_ctl + dut_inst cpu_inst + current_design_block { + module_name cpu + view full + } + } +} diff --git a/cpu_patterns_serial.v.po.name b/cpu_patterns_serial.v.po.name new file mode 100644 index 0000000..37410a2 --- /dev/null +++ b/cpu_patterns_serial.v.po.name @@ -0,0 +1,12 @@ +6c65645b375d +6c65645b365d +6c65645b355d +6c65645b345d +6c65645b335d +6c65645b325d +6c65645b315d +6c65645b305d +0000534f5f31 +0000534f5f32 +0000534f5f33 +0000534f5f34 diff --git a/demo_chip_rtl/demo_chip.odb b/demo_chip_rtl/demo_chip.odb new file mode 100644 index 0000000..68db4d3 Binary files /dev/null and b/demo_chip_rtl/demo_chip.odb differ diff --git a/demo_chip_rtl/rtl/demo_chip/cpu_sys.v b/demo_chip_rtl/rtl/demo_chip/cpu_sys.v new file mode 100755 index 0000000..040a07a --- /dev/null +++ b/demo_chip_rtl/rtl/demo_chip/cpu_sys.v @@ -0,0 +1,85 @@ + +// +// Wrapper for CPU + memory + + +module cpu_sys ( + + + input clock, + input reset, + input [4:0] Interrupts, // 5 general-purpose hardware interrupts + input NMI, // Non-maskable interrupt + // Data Memory Interface + input [31:0] per_dout, // + output DataMem_Read, + output [3:0] DataMem_Write, // 4-bit Write, one for each byte in word. + output [29:0] DataMem_Address, // Addresses are words, not bytes. + output [31:0] DataMem_Out + + ); + +// Instruction Memory Interface +wire [31:0] pmem_dout; +wire [29:0] pmem_addr; // Addresses are words, not bytes. +wire pmem_cen; + +wire dmem_cen; +wire [31:0] dmem_dout; // Data Memory data output +wire [31:0] DataMem_In; + +// --------------------------------- +// MIPS processor +// --------------------------------- + +Processor MIPS_CPU ( + .clock(clock), + .reset(reset), + .Interrupts(Interrupts), // 5 general-purpose hardware interrupts + .NMI(NMI), // Non-maskable interrupt + // Data Memory Interface + .DataMem_In(DataMem_In), + .DataMem_Ready(1'b1), + .DataMem_Read(), + .DataMem_Write(DataMem_Write), // 4-bit Write, one for each byte in word. + .DataMem_Address(DataMem_Address), // Addresses are words, not bytes. + .DataMem_Out(DataMem_Out), + // Instruction Memory Interface + .InstMem_In(pmem_dout), + .InstMem_Address(pmem_addr), // Addresses are words, not bytes. + .InstMem_Ready(1'b1), + .InstMem_Read(pmem_cen), + .IP() // Pending interrupts (diagnostic) +); + +// --------------------------------- +// Program Memory RAM // +// --------------------------------- +MemGen_32_12 program_memory ( + .chip_en(pmem_cen), + .clock(clock), + .addr(pmem_addr[11:0]), + .rd_data(pmem_dout), + .rd_en(pmem_cen), + .wr_data(32'h00000000), + .wr_en(1'b0) + ); + +// --------------------------------- +// Program Memory RAM // +// --------------------------------- + +assign DataMem_In = DataMem_Address[29] ? per_dout : dmem_dout; +assign dmem_cen = !DataMem_Address[29]; + +MemGen_32_12 data_memory ( + .chip_en(dmem_cen), + .clock(clock), + .addr(DataMem_Address[11:0]), + .rd_data(dmem_dout), + .rd_en(DataMem_Read), + .wr_data(DataMem_Out), + .wr_en(DataMem_Write[0]) + ); + +endmodule diff --git a/demo_chip_rtl/rtl/demo_chip/demo_chip.v b/demo_chip_rtl/rtl/demo_chip/demo_chip.v new file mode 100755 index 0000000..90ec8ce --- /dev/null +++ b/demo_chip_rtl/rtl/demo_chip/demo_chip.v @@ -0,0 +1,856 @@ +//////////////////////////////////////////////////////////////////// +// Design : demo_chip +// Author(s) : +// Creation date : August 9,2013 +// Copyright (C) ... +//////////////////////////////////////////////////////////////////// +// Description: demo_chip instantiates the following modules: +// 1 MIPS 32r1 CPU +// 2 nova decoder wrapper +// 3 4 * HPDMC DDR controllers +// 4 USB controller + PHY +// +//////////////////////////////////////////////////////////////////// + + +module demo_chip( + + output mclk, // Main system clock (used by external memories) + input reset_n, + + + // + // First H264 Decoder Pins + // + + input [15:0] BS_data_0, + output BS_ren_0, + output [16:0] BS_addr_0, + + + // + // Second H264 Decoder Pins + // + + input [15:0] BS_data_1, + output BS_ren_1, + output [16:0] BS_addr_1, + + + // + // Microcontroller pins + // + input lfxt_clk, // Low frequency reference (typ 10MHz) + input nmi, // Non-maskable interrupt (asynchronous and non-glitchy) + + + // DDR0 + output ddr0_cke, + output ddr0_cs_n, + output ddr0_we_n, + output ddr0_cas_n, + output ddr0_ras_n, + output [12:0] ddr0_adr, + output [1:0] ddr0_ba, + + output [3:0] ddr0_dm, + inout [31:0] ddr0_dq, + inout [3:0] ddr0_dqs, + + // DDR1 + output ddr1_cke, + output ddr1_cs_n, + output ddr1_we_n, + output ddr1_cas_n, + output ddr1_ras_n, + output [12:0] ddr1_adr, + output [1:0] ddr1_ba, + + output [3:0] ddr1_dm, + inout [31:0] ddr1_dq, + inout [3:0] ddr1_dqs, + + // DDR2 + output ddr2_cke, + output ddr2_cs_n, + output ddr2_we_n, + output ddr2_cas_n, + output ddr2_ras_n, + output [12:0] ddr2_adr, + output [1:0] ddr2_ba, + + output [3:0] ddr2_dm, + inout [31:0] ddr2_dq, + inout [3:0] ddr2_dqs, + + // DDR3 + output ddr3_cke, + output ddr3_cs_n, + output ddr3_we_n, + output ddr3_cas_n, + output ddr3_ras_n, + output [12:0] ddr3_adr, + output [1:0] ddr3_ba, + + output [3:0] ddr3_dm, + inout [31:0] ddr3_dq, + inout [3:0] ddr3_dqs, + + // USB + inout usb_plus, usb_minus, + + // + + input scan_mode, + input sysclk_byp, + input usbclk_byp + +); + + + +// Internal chip side pad connections + + wire lfxt_clk_i; // Main system clock (used by external memories) + wire reset_n_i; + wire nmi_i; // Non-maskable interrupt (asynchronous and non-glitchy) + wire mclk_i; // Main system clock (used by external memories) + + wire scan_mode_i; + wire sysclk_byp_i; + wire usbclk_byp_i; + + // DDR + wire ddr0_cke_i, ddr0_cs_n_i, ddr0_we_n_i, ddr0_cas_n_i, ddr0_ras_n_i, + ddr1_cke_i, ddr1_cs_n_i, ddr1_we_n_i, ddr1_cas_n_i, ddr1_ras_n_i, + ddr2_cke_i, ddr2_cs_n_i, ddr2_we_n_i, ddr2_cas_n_i, ddr2_ras_n_i, + ddr3_cke_i, ddr3_cs_n_i, ddr3_we_n_i, ddr3_cas_n_i, ddr3_ras_n_i; + wire [12:0] ddr0_adr_i, ddr1_adr_i, ddr2_adr_i, ddr3_adr_i; + wire [1:0] ddr0_ba_i, ddr1_ba_i, ddr2_ba_i, ddr3_ba_i; + wire [3:0] ddr0_dm_i, ddr1_dm_i, ddr2_dm_i, ddr3_dm_i; + + + wire [15:0] BitStream_buffer_input_0_i; + wire BitStream_ram_ren_0_i; + wire [16:0] BitStream_ram_addr_0_i; + wire [15:0] BitStream_buffer_input_1_i; + wire BitStream_ram_ren_1_i; + wire [16:0] BitStream_ram_addr_1_i; +// wire [15:0] BS_data_0; //added by sudhish for missing declarations on pads +// wire [15:0] BS_data_1; + + + wire [31:0] dmem_din; // Data Memory data input + wire [29:0] dmem_addr; // Data Memory address + wire [3:0] dmem_wen; // Data Memory write enable (low active) + wire dmem_cen; // Data Memory write enable (low active) + + wire [31:0] power_control; // Power switch powerdwon control + wire [31:0] power_iso; // Power switch isolation control + wire [31:0] power_ack; // Power switch acknowledge + wire power_control_0; + wire power_ack_0; +// QSG wire power_ack_2; +// QSG wire power_control_2; + + wire smclk; + wire pll_clk, pll_clk_o; + wire aclk; + wire dco_clk; + reg enable_nova0, enable_nova1; + wire mclk_nova0, mclk_nova1; + + wire ext_frame_RAM0_cs_n; + wire ext_frame_RAM0_wr; + wire [13:0] ext_frame_RAM0_addr; + wire [31:0] ext_frame_RAM0_data; + wire [63:0] fml_do_ddr0; + + wire ext_frame_RAM1_cs_n; + wire ext_frame_RAM1_wr; + wire [13:0] ext_frame_RAM1_addr; + wire [31:0] ext_frame_RAM1_data; + wire [63:0] fml_do_ddr1; + + wire [31:0] dis_frame_RAM_din_0; + + wire ext_frame_RAM2_cs_n; + wire ext_frame_RAM2_wr; + wire [13:0] ext_frame_RAM2_addr; + wire [31:0] ext_frame_RAM2_data; + wire [63:0] fml_do_ddr2; + + wire ext_frame_RAM3_cs_n; + wire ext_frame_RAM3_wr; + wire [13:0] ext_frame_RAM3_addr; + wire [31:0] ext_frame_RAM3_data; + wire [63:0] fml_do_ddr3; + + wire [31:0] dis_frame_RAM_din_1; + + // USB + wire usb_clk, usb_clk_o; + wire usb_txdp, usb_txdn, usb_txoe; + wire usb_rxd, usb_rxdp, usb_rxdn; + wire [7:0] usb_DataOut; + wire usb_TxValid; + wire usb_TxReady; + wire [7:0] usb_DataIn; + wire usb_RxValid; + wire usb_RxActive; + wire usb_RxError; + wire [1:0] usb_LineState; + wire usb_inta, usb_intb; + wire [4:0] Interrupts; // 5 general-purpose hardware interrupts + + + // Define clocks - all from PLL + + assign smclk = pll_clk; + assign mclk_i = pll_clk; + assign mclk_n = !pll_clk; + assign dqs_clk = pll_clk; + assign dqs_clk_n = !pll_clk; + assign aclk = pll_clk; + assign mclk_i = pll_clk; + assign dco_clk = pll_clk; + + +// --------------------------------- +// External pads (non-DDR) +// --------------------------------- + + + +PADBID lfxt_clk_pad ( .I(1'b0), .OEN(1'b1), .PAD(lfxt_clk), .C(lfxt_clk_i) ); +PADBID reset_n_pad ( .I(1'b0), .OEN(1'b1), .PAD(reset_n), .C(reset_n_i) ); +PADBID nmi_pad ( .I(1'b0), .OEN(1'b1), .PAD(nmi), .C(nmi_i) ); +PADBID mclk_pad ( .I(mclk_i), .OEN(1'b0), .PAD(mclk), .C() ); + +PADBID BS_ren_0_pad ( .I(BitStream_ram_ren_0_i), .OEN(1'b0), .PAD(BS_ren_0), .C() ); +PADBID BS_ren_1_pad ( .I(BitStream_ram_ren_1_i), .OEN(1'b0), .PAD(BS_ren_1), .C() ); + +PADBID scan_mode_pad ( .I(1'b0), .OEN(1'b1), .PAD(scan_mode), .C(scan_mode_i) ); +// PADBID sysclk_byp_pad ( .I(1'b0), .OEN(1'b1), .PAD(sysclk_byp), .C(sysclk_byp_i) ); +//PADBID usbclk_byp_pad ( .I(1'b0), .OEN(1'b1), .PAD(usbclk_byp), .C(usbclk_byp_i) ); +PADCLK sysclk_byp_pad ( .PAD(sysclk_byp), .C(sysclk_byp_i) ); +PADCLK usbclk_byp_pad ( .PAD(usbclk_byp), .C(usbclk_byp_i) ); + +genvar i, ddr; + +// Data buses +generate + for (i = 0; i <= 15; i = i + 1) begin + PADBID BS_data_0_pad ( .I(1'b0), .OEN(1'b1), .PAD(BS_data_0[i]), .C(BitStream_buffer_input_0_i[i]) ); + PADBID BS_data_1_pad ( .I(1'b0), .OEN(1'b1), .PAD(BS_data_1[i]), .C(BitStream_buffer_input_1_i[i]) ); + end +endgenerate + +// Address buses +generate + for (i = 0; i <= 16; i = i + 1) begin + PADBID BS_addr_0_pad ( .I(BitStream_ram_addr_0_i[i]), .OEN(1'b0), .PAD(BS_addr_0[i]), .C() ); + PADBID BS_addr_1_pad ( .I(BitStream_ram_addr_1_i[i]), .OEN(1'b0), .PAD(BS_addr_1[i]), .C() ); + end +endgenerate + +PADBID i_usb_pad_plus ( .I(usb_txdp), .OEN(usb_txoe), .PAD(usb_plus), .C(usb_rxdp) ); +PADBID i_usb_pad_minus ( .I(usb_txdn), .OEN(usb_txoe), .PAD(usb_minus), .C(usb_rxdn) ); +assign usb_rxd = usb_rxdp && usb_rxdn; + +// --------------------------------- +// DDR output pads (data pads are in the PHY module +// --------------------------------- +PADBID ddr0_cke_pad ( .I(ddr0_cke_i), .OEN(1'b0), .PAD(ddr0_cke), .C() ); +PADBID ddr0_cs_n_pad ( .I(ddr0_cs_n_i), .OEN(1'b0), .PAD(ddr0_cs_n), .C() ); +PADBID ddr0_we_n_pad ( .I(ddr0_we_n_i), .OEN(1'b0), .PAD(ddr0_we_n), .C() ); +PADBID ddr0_cas_n_pad ( .I(ddr0_cas_n_i), .OEN(1'b0), .PAD(ddr0_cas_n), .C() ); +PADBID ddr0_ras_n_pad ( .I(ddr0_ras_n_i), .OEN(1'b0), .PAD(ddr0_ras_n), .C() ); +PADBID ddr1_cke_pad ( .I(ddr1_cke_i), .OEN(1'b0), .PAD(ddr1_cke), .C() ); +PADBID ddr1_cs_n_pad ( .I(ddr1_cs_n_i), .OEN(1'b0), .PAD(ddr1_cs_n), .C() ); +PADBID ddr1_we_n_pad ( .I(ddr1_we_n_i), .OEN(1'b0), .PAD(ddr1_we_n), .C() ); +PADBID ddr1_cas_n_pad ( .I(ddr1_cas_n_i), .OEN(1'b0), .PAD(ddr1_cas_n), .C() ); +PADBID ddr1_ras_n_pad ( .I(ddr1_ras_n_i), .OEN(1'b0), .PAD(ddr1_ras_n), .C() ); +PADBID ddr2_cke_pad ( .I(ddr2_cke_i), .OEN(1'b0), .PAD(ddr2_cke), .C() ); +PADBID ddr2_cs_n_pad ( .I(ddr2_cs_n_i), .OEN(1'b0), .PAD(ddr2_cs_n), .C() ); +PADBID ddr2_we_n_pad ( .I(ddr2_we_n_i), .OEN(1'b0), .PAD(ddr2_we_n), .C() ); +PADBID ddr2_cas_n_pad ( .I(ddr2_cas_n_i), .OEN(1'b0), .PAD(ddr2_cas_n), .C() ); +PADBID ddr2_ras_n_pad ( .I(ddr2_ras_n_i), .OEN(1'b0), .PAD(ddr2_ras_n), .C() ); +PADBID ddr3_cke_pad ( .I(ddr3_cke_i), .OEN(1'b0), .PAD(ddr3_cke), .C() ); +PADBID ddr3_cs_n_pad ( .I(ddr3_cs_n_i), .OEN(1'b0), .PAD(ddr3_cs_n), .C() ); +PADBID ddr3_we_n_pad ( .I(ddr3_we_n_i), .OEN(1'b0), .PAD(ddr3_we_n), .C() ); +PADBID ddr3_cas_n_pad ( .I(ddr3_cas_n_i), .OEN(1'b0), .PAD(ddr3_cas_n), .C() ); +PADBID ddr3_ras_n_pad ( .I(ddr3_ras_n_i), .OEN(1'b0), .PAD(ddr3_ras_n), .C() ); + +generate + for (i = 0; i <= 12; i = i + 1) begin + PADBID ddr0_adr_pad ( .I(ddr0_adr_i[i]), .OEN(1'b0), .PAD(ddr0_adr[i]), .C() ); + PADBID ddr1_adr_pad ( .I(ddr1_adr_i[i]), .OEN(1'b0), .PAD(ddr1_adr[i]), .C() ); + PADBID ddr2_adr_pad ( .I(ddr2_adr_i[i]), .OEN(1'b0), .PAD(ddr2_adr[i]), .C() ); + PADBID ddr3_adr_pad ( .I(ddr3_adr_i[i]), .OEN(1'b0), .PAD(ddr3_adr[i]), .C() ); + end +endgenerate +generate + for (i = 0; i <= 1; i = i + 1) begin + PADBID ddr0_ba_pad ( .I(ddr0_ba_i[i]), .OEN(1'b0), .PAD(ddr0_ba[i]), .C() ); + PADBID ddr1_ba_pad ( .I(ddr1_ba_i[i]), .OEN(1'b0), .PAD(ddr1_ba[i]), .C() ); + PADBID ddr2_ba_pad ( .I(ddr2_ba_i[i]), .OEN(1'b0), .PAD(ddr2_ba[i]), .C() ); + PADBID ddr3_ba_pad ( .I(ddr3_ba_i[i]), .OEN(1'b0), .PAD(ddr3_ba[i]), .C() ); + end +endgenerate +generate + for (i = 0; i <= 3; i = i + 1) begin + PADBID ddr0_dm_pad ( .I(ddr0_dm_i[i]), .OEN(1'b0), .PAD(ddr0_dm[i]), .C() ); + PADBID ddr1_dm_pad ( .I(ddr1_dm_i[i]), .OEN(1'b0), .PAD(ddr1_dm[i]), .C() ); + PADBID ddr2_dm_pad ( .I(ddr2_dm_i[i]), .OEN(1'b0), .PAD(ddr2_dm[i]), .C() ); + PADBID ddr3_dm_pad ( .I(ddr3_dm_i[i]), .OEN(1'b0), .PAD(ddr3_dm[i]), .C() ); + end +endgenerate + +// --------------------------------- +// Peripheral Interface bus +// --------------------------------- + + wire [15:0] per_dout; // Register data output to microcontroller + wire [15:0] per_dout_nova0; // Register data output from nova0 + wire [15:0] per_dout_nova1; // Register data output from nova1 + wire [31:0] per_dout_ddr0; // Register data output from ddr0 + wire [31:0] per_dout_ddr1; // Register data output from ddr0 + wire [31:0] per_dout_ddr2; // Register data output from ddr0 + wire [31:0] per_dout_ddr3; // Register data output from ddr0 + wire [31:0] per_dout_usb; // Register data output from USB + wire [31:0] per_dout_pctl; // Register data output from USB + wire [13:0] per_addr; // Register address + wire [31:0] per_din; // Register data input + wire [1:0] per_we; // Register write enable (high active) + wire per_en; // Register enable (high active) + wire per_rd; // Register read +assign per_din = dmem_din; +assign per_dout = {15'h0000,per_dout_nova0} || + {15'h0000,per_dout_nova1[15:0]} || + per_dout_ddr0 || + per_dout_ddr1 || + per_dout_ddr2 || + per_dout_ddr3 || + per_dout_usb || + per_dout_pctl || + 32'h00000000; +assign per_en = dmem_addr[29]; +assign per_we[0] = dmem_addr[29] && dmem_wen[0]; +assign per_we[1] = dmem_addr[29] && dmem_wen[1]; +assign per_rd = per_en && !per_we[0]; +assign per_addr = dmem_addr[13:0]; +//assign DataMem_In = dmem_addr[29] ? per_dout : dmem_dout; + + wire NMI; // Non-maskable interrupt + wire DataMem_Ready; + wire DataMem_Read; + wire [3:0] DataMem_Write; // 4-bit Write; one for each byte in word. + wire [29:0] DataMem_Address; // Addresses are words; not bytes. + wire [31:0] DataMem_Out; + // Instruction Memory Interface + wire [31:0] InstMem_In; + wire [29:0] InstMem_Address; // Addresses are words; not bytes. + wire InstMem_Ready; + wire InstMem_Read; + wire [7:0] IP; // Pending interrupts (diagnostic) + +assign Interrupts = { 3'b0, usb_inta, usb_intb } ; + +// --------------------------------- +// MIPS CPU +// --------------------------------- + +cpu_sys i_cpu_sys ( + .clock(smclk), + .reset(reset_n_i), + .Interrupts(Interrupts), // 5 general-purpose hardware interrupts + .NMI(nmi_i), // Non-maskable interrupt + // Data Memory Interface + .per_dout(per_dout), + .DataMem_Read(dmem_rd), + .DataMem_Write(dmem_wen), // 4-bit Write, one for each byte in word. + .DataMem_Address(dmem_addr), // Addresses are words, not bytes. + .DataMem_Out(dmem_din) + +); + + + +// --------------------------------- +// Powerdown register +// --------------------------------- + +// Tie off pre-layout - will connect to power switches +// assign power_ack = 32'hffff_ffff; + +powerdown_control powerdown_control ( + .clk(mclk_i), + .reset_n(reset_n_i), + .per_addr(per_addr), + .per_din(per_din), + .per_en(per_en), + .per_we(per_we[0]), + .per_rd(per_rd), + .per_dout(per_dout_pctl), + .power_control(power_control), + .power_ack(power_ack), + .power_iso(power_iso) +); + +//dummy_connector dummy_connector (.power_control(power_control), .power_iso(power_iso), .power_ack(power_ack) ); + +// NOVA 0 clock gate +always @(negedge mclk_i ) enable_nova0 <= power_iso[0]; +AND2_X1_HVT i_nova0_cg (.A1(mclk_i), .A2(enable_nova0), .ZN(mclk_nova0) ); + + /////////////////// + // NOVA decoders // + /////////////////// + nova_wrapper nova0 ( + .clk(mclk_nova0), + .clk_reg(smclk), + .reset_n(reset_n_i), + .per_dout(per_dout_nova0), + .per_addr(per_addr), + .per_din(per_din[15:0]), + .per_en(per_en), + .per_we(per_we), + .BitStream_buffer_input(BitStream_buffer_input_0_i), + .BitStream_ram_ren(BitStream_ram_ren_0_i), + .BitStream_ram_addr(BitStream_ram_addr_0_i), + .ext_frame_RAM0_cs_n(ext_frame_RAM0_cs_n), + .ext_frame_RAM0_wr(ext_frame_RAM0_wr), + .ext_frame_RAM0_addr(ext_frame_RAM0_addr), + .ext_frame_RAM0_data(ext_frame_RAM0_data), + .ext_frame_RAM1_cs_n(ext_frame_RAM1_cs_n), + .ext_frame_RAM1_wr(ext_frame_RAM1_wr), + .ext_frame_RAM1_addr(ext_frame_RAM1_addr), + .ext_frame_RAM1_data(ext_frame_RAM1_data), + .dis_frame_RAM_din(dis_frame_RAM_din_0), + .power_ack(power_ack_0), + .power_control(power_control_0) + ); + +// DDR port 0 + +// Dummy register to create control signal +reg [7:0] fml_sel_ddr0; +always @ (posedge mclk_nova0 ) + begin + if ( ext_frame_RAM0_cs_n == 1'b0 ) + if ( ext_frame_RAM0_wr ) + fml_sel_ddr0 <= dis_frame_RAM_din_0[7:0]; + else + fml_sel_ddr0 <= dis_frame_RAM_din_0[15:8]; + end +// Create to get a 2 bit pll_stat for DDR +wire sys_pll_lock; +reg sys_pll_lock_sync; +always @ (posedge pll_clk_o ) sys_pll_lock_sync <= sys_pll_lock; + +// Dummy register to expand DDR bus to 64 bits +reg [31:0] nova0_data_extend; +wire [63:0]nova0_fml_di; +always @ (posedge mclk_nova0 ) nova0_data_extend <= dis_frame_RAM_din_0; +assign nova0_fml_di = { nova0_data_extend, dis_frame_RAM_din_0 }; +assign ext_frame_RAM0_data = ext_frame_RAM0_addr[13] ? fml_do_ddr0 [63:32] : fml_do_ddr0 [31:0] ; + +hpdmc #( + .csr_addr(4'h0), + .sdram_depth(14), + .sdram_columndepth(9) +) nova0_ddr0 ( + .sys_clk(mclk_nova0), + .sys_clk_n(!mclk_nova0), + + .dqs_clk(mclk_nova0), + .dqs_clk_n(!mclk_nova0), + + .sys_rst(!reset_n_i), + + /* Control interface */ + .csr_a(per_addr), + .csr_we(per_we[0]), + .csr_di(per_din), + .csr_do(per_dout_ddr0), + + /* Simple FML 4x64 interface to the memory contents */ + .fml_adr(ext_frame_RAM0_addr), + .fml_stb(ext_frame_RAM0_cs_n), + .fml_we(ext_frame_RAM0_wr), + .fml_ack(), + .fml_sel(fml_sel_ddr0), + .fml_di(nova0_fml_di), + .fml_do(fml_do_ddr0), + + /* SDRAM interface. + * The SDRAM clock should be driven synchronously to the system clock. + * It is not generated inside this core so you can take advantage of + * architecture-dependent clocking resources to generate a clean + * differential clock. + */ + .sdram_cke(ddr0_cke_i), + .sdram_cs_n(ddr0_cs_n_i), + .sdram_we_n(ddr0_we_n_i), + .sdram_cas_n(ddr0_cas_n_i), + .sdram_ras_n(ddr0_ras_n_i), + .sdram_adr(ddr0_adr_i), + .sdram_ba(ddr0_ba_i), + + + .sdram_dm(ddr0_dm_i), + .sdram_dq(ddr0_dq), + .sdram_dqs(ddr0_dqs), + + /* Interface to the DCM generating DQS */ + .dqs_psen(), + .dqs_psincdec(), + .dqs_psdone(1'b0), + + .pll_stat({sys_pll_lock,sys_pll_lock_sync}) +); + +// DDR port 1 + +// Dummy register to create control signal +reg [7:0] fml_sel_ddr1; +always @ (posedge mclk_nova0 ) + begin + if ( ext_frame_RAM1_cs_n == 1'b0 ) + if ( ext_frame_RAM1_wr ) + fml_sel_ddr1 <= dis_frame_RAM_din_0[23:16]; + else + fml_sel_ddr1 <= dis_frame_RAM_din_0[31:24]; + end +assign ext_frame_RAM1_data = ext_frame_RAM1_addr[13] ? fml_do_ddr1 [63:32] : fml_do_ddr1 [31:0] ; + +hpdmc #( + .csr_addr(4'h1), + .sdram_depth(14), + .sdram_columndepth(9) +) nova0_ddr1 ( + .sys_clk(mclk_nova0), + .sys_clk_n(!mclk_nova0), + + .dqs_clk(mclk_nova0), + .dqs_clk_n(!mclk_nova0), + + .sys_rst(!reset_n_i), + + /* Control interface */ + .csr_a(per_addr), + .csr_we(per_we[0]), + .csr_di(per_din), + .csr_do(per_dout_ddr1), + + /* Simple FML 4x64 interface to the memory contents */ + .fml_adr(ext_frame_RAM1_addr), + .fml_stb(ext_frame_RAM1_cs_n), + .fml_we(ext_frame_RAM1_wr), + .fml_ack(), + .fml_sel(fml_sel_ddr1), + .fml_di(nova0_fml_di), + .fml_do(fml_do_ddr1), + + /* SDRAM interface. + * The SDRAM clock should be driven synchronously to the system clock. + * It is not generated inside this core so you can take advantage of + * architecture-dependent clocking resources to generate a clean + * differential clock. + */ + .sdram_cke(ddr1_cke_i), + .sdram_cs_n(ddr1_cs_n_i), + .sdram_we_n(ddr1_we_n_i), + .sdram_cas_n(ddr1_cas_n_i), + .sdram_ras_n(ddr1_ras_n_i), + .sdram_adr(ddr1_adr_i), + .sdram_ba(ddr1_ba_i), + + + .sdram_dm(ddr1_dm_i), + .sdram_dq(ddr1_dq), + .sdram_dqs(ddr1_dqs), + + /* Interface to the DCM generating DQS */ + .dqs_psen(), + .dqs_psincdec(), + .dqs_psdone(1'b0), + + .pll_stat({sys_pll_lock,sys_pll_lock_sync}) +); + +// NOVA 1 clock gate +always @(negedge mclk_i ) enable_nova1 <= power_iso[1]; +AND2_X1_HVT i_nova1_cg (.A1(mclk_i), .A2(enable_nova1), .ZN(mclk_nova1) ); + + + + nova_wrapper nova1 ( + .clk(mclk_nova1), + .clk_reg(smclk), + .reset_n(reset_n_i), + .per_dout(per_dout_nova1), + .per_addr(per_addr), + .per_din(per_din[15:0]), + .per_en(per_en), + .per_we(per_we), + .BitStream_buffer_input(BitStream_buffer_input_1_i), + .BitStream_ram_ren(BitStream_ram_ren_1_i), + .BitStream_ram_addr(BitStream_ram_addr_1_i), + .ext_frame_RAM0_cs_n(ext_frame_RAM2_cs_n), + .ext_frame_RAM0_wr(ext_frame_RAM2_wr), + .ext_frame_RAM0_addr(ext_frame_RAM2_addr), + .ext_frame_RAM0_data(ext_frame_RAM2_data), + .ext_frame_RAM1_cs_n(ext_frame_RAM3_cs_n), + .ext_frame_RAM1_wr(ext_frame_RAM3_wr), + .ext_frame_RAM1_addr(ext_frame_RAM3_addr), + .ext_frame_RAM1_data(ext_frame_RAM3_data), + .dis_frame_RAM_din(dis_frame_RAM_din_1), + .power_ack(power_ack[1]), + .power_control(power_control[1]) + ); + +// DDR port 2 + +// Dummy register to create control signal +reg [7:0] fml_sel_ddr2; +always @ (posedge mclk_nova1 ) + begin + if ( ext_frame_RAM2_cs_n == 1'b0 ) + if ( ext_frame_RAM0_wr ) + fml_sel_ddr2 <= dis_frame_RAM_din_1[7:0]; + else + fml_sel_ddr2 <= dis_frame_RAM_din_1[15:8]; + end +// Dummy register to expand DDR bus to 64 bits +reg [31:0] nova1_data_extend; +wire [63:0]nova1_fml_di; +always @ (posedge mclk_nova1 ) nova1_data_extend <= dis_frame_RAM_din_1; +assign nova1_fml_di = { nova1_data_extend, dis_frame_RAM_din_1 }; +assign ext_frame_RAM2_data = ext_frame_RAM2_addr[13] ? fml_do_ddr2 [63:32] : fml_do_ddr2 [31:0] ; + +hpdmc #( + .csr_addr(4'h2), + .sdram_depth(14), + .sdram_columndepth(9) +) nova0_ddr2 ( + .sys_clk(mclk_nova1), + .sys_clk_n(!mclk_nova1), + + .dqs_clk(mclk_nova1), + .dqs_clk_n(!mclk_nova1), + + .sys_rst(!reset_n_i), + + /* Control interface */ + .csr_a(per_addr), + .csr_we(per_we[0]), + .csr_di(per_din), + .csr_do(per_dout_ddr2), + + /* Simple FML 4x64 interface to the memory contents */ + .fml_adr(ext_frame_RAM2_addr), + .fml_stb(ext_frame_RAM2_cs_n), + .fml_we(ext_frame_RAM2_wr), + .fml_ack(), + .fml_sel(fml_sel_ddr2), + .fml_di(nova1_fml_di), + .fml_do(fml_do_ddr2), + + /* SDRAM interface. + * The SDRAM clock should be driven synchronously to the system clock. + * It is not generated inside this core so you can take advantage of + * architecture-dependent clocking resources to generate a clean + * differential clock. + */ + .sdram_cke(ddr2_cke_i), + .sdram_cs_n(ddr2_cs_n_i), + .sdram_we_n(ddr2_we_n_i), + .sdram_cas_n(ddr2_cas_n_i), + .sdram_ras_n(ddr2_ras_n_i), + .sdram_adr(ddr2_adr_i), + .sdram_ba(ddr2_ba_i), + + + .sdram_dm(ddr2_dm_i), + .sdram_dq(ddr2_dq), + .sdram_dqs(ddr2_dqs), + + /* Interface to the DCM generating DQS */ + .dqs_psen(), + .dqs_psincdec(), + .dqs_psdone(1'b0), + + .pll_stat({sys_pll_lock,sys_pll_lock_sync}) +); + +// DDR port 3 + +// Dummy register to create control signal +reg [7:0] fml_sel_ddr3; +always @ (posedge mclk_nova1 ) + begin + if ( ext_frame_RAM3_cs_n == 1'b0 ) + if ( ext_frame_RAM0_wr ) + fml_sel_ddr3 <= dis_frame_RAM_din_1[23:16]; + else + fml_sel_ddr3 <= dis_frame_RAM_din_1[31:24]; + end +assign ext_frame_RAM3_data = ext_frame_RAM3_addr[13] ? fml_do_ddr3 [63:32] : fml_do_ddr3 [31:0] ; + +hpdmc #( + .csr_addr(4'h1), + .sdram_depth(14), + .sdram_columndepth(9) +) nova0_ddr3 ( + .sys_clk(mclk_nova1), + .sys_clk_n(!mclk_nova1), + + .dqs_clk(mclk_nova1), + .dqs_clk_n(!mclk_nova1), + + .sys_rst(!reset_n_i), + + /* Control interface */ + .csr_a(per_addr), + .csr_we(per_we[0]), + .csr_di(per_din), + .csr_do(per_dout_ddr3), + + /* Simple FML 4x64 interface to the memory contents */ + .fml_adr(ext_frame_RAM3_addr), + .fml_stb(ext_frame_RAM3_cs_n), + .fml_we(ext_frame_RAM3_wr), + .fml_ack(), + .fml_sel(fml_sel_ddr3), + .fml_di(nova1_fml_di), + .fml_do(fml_do_ddr3), + + /* SDRAM interface. + * The SDRAM clock should be driven synchronously to the system clock. + * It is not generated inside this core so you can take advantage of + * architecture-dependent clocking resources to generate a clean + * differential clock. + */ + .sdram_cke(ddr3_cke_i), + .sdram_cs_n(ddr3_cs_n_i), + .sdram_we_n(ddr3_we_n_i), + .sdram_cas_n(ddr3_cas_n_i), + .sdram_ras_n(ddr3_ras_n_i), + .sdram_adr(ddr3_adr_i), + .sdram_ba(ddr3_ba_i), + + + .sdram_dm(ddr3_dm_i), + .sdram_dq(ddr3_dq), + .sdram_dqs(ddr3_dqs), + + /* Interface to the DCM generating DQS */ + .dqs_psen(), + .dqs_psincdec(), + .dqs_psdone(1'b0), + + .pll_stat({sys_pll_lock,sys_pll_lock_sync}) +); + +usb_sys i_usbf ( + // WISHBONE Interface +// QSG .power_ack(power_ack_2), +// QSG .power_control(power_control_2), + .clk_i(mclk_i), + .rst_i(reset_n_i), + .wb_addr_i(dmem_addr[17:0]), + .wb_data_i(per_din), + .wb_data_o(per_dout_usb), + .wb_we_i(per_we[0]), + .wb_stb_i(per_en), + .inta_o(usb_intb), + .intb_o(usb_inta), + + // UTMI Interface + .phy_clk_pad_i(usb_clk), + .phy_rst_pad_o(phy_rst_pad), + .DataOut_pad_o(usb_DataOut), + .TxValid_pad_o(usb_TxValid), + .TxReady_pad_i(usb_TxReady), + + .RxValid_pad_i (usb_RxValid), + .RxActive_pad_i (usb_RxActive), + .RxError_pad_i (usb_RxError), + .DataIn_pad_i (usb_DataIn), + .LineState_pad_i (usb_LineState) + ); + + +usb_phy i_usb_phy( + .clk(usb_clk), + .rst(phy_rst_pad), + .phy_tx_mode(1'b0), + .usb_rst(), + // UTMI Interface + .DataOut_i (usb_DataOut), + .TxValid_i (usb_TxValid), + .TxReady_o (usb_TxReady), + .RxValid_o (usb_RxValid), + .RxActive_o (usb_RxActive), + .RxError_o (usb_RxError), + .DataIn_o (usb_DataIn), + .LineState_o (usb_LineState), + + .txdp(usb_txdp), + .txdn(usb_txdn), + .txoe(usb_txoe), + .rxd(usb_rxd), + .rxdp(usb_rxdp), + .rxdn(usb_rxdn) + ); + + // -------------------- + // Main PLL + // DIVR = 1, DIVF = 80. DIVQ = 2 + // Overall Multiply by 40 + // -------------------- + PLL i_MAIN_PLL ( + .REF(lfxt_clk_i), // Reference clock + .FB(dco_clk), // Feedback clock + .FSE(1'b1), // Selects source of feedback input + .BYPASS(1'b0), + .RESET(!reset_n_i), + .DIVF7(1'b0), .DIVF6(1'b1), .DIVF5(1'b0), .DIVF4(1'b0), .DIVF3(1'b1), .DIVF2(1'b1), .DIVF1(1'b1), .DIVF0(1'b1), + .DIVQ2(1'b0), .DIVQ1(1'b0), .DIVQ0(1'b1), + .DIVR5(1'b0), .DIVR4(1'b0), .DIVR3(1'b0), .DIVR2(1'b0), .DIVR1(1'b0), .DIVR0(1'b0), + .RANGE2(1'b0), .RANGE1(1'b0), .RANGE0(1'b1), + + .LOCK(sys_pll_lock), + .PLLOUT(pll_clk_o) + ); + + //assign pll_clk = scan_mode_i ? sysclk_byp_i : pll_clk_o; + MUX2_X2_HVT i_sys_clk_mux ( .A(pll_clk_o), .B(sysclk_byp_i), .S(scan_mode_i), .Z(pll_clk) ); + + // -------------------- + // USB PLL + // DIVR = 1, DIVF = 96. DIVQ = 16 + // Overall Multiply by 6 + // -------------------- + PLL i_USB_PLL ( + .REF(lfxt_clk_i), // Reference clock + .FB(1'b0), // Feedback clock + .FSE(1'b1), // Selects source of feedback input + .BYPASS(1'b0), + .RESET(!reset_n_i), + .DIVF7(1'b0), .DIVF6(1'b1), .DIVF5(1'b0), .DIVF4(1'b1), .DIVF3(1'b1), .DIVF2(1'b1), .DIVF1(1'b1), .DIVF0(1'b1), + .DIVQ2(1'b1), .DIVQ1(1'b0), .DIVQ0(1'b0), + .DIVR5(1'b0), .DIVR4(1'b0), .DIVR3(1'b0), .DIVR2(1'b0), .DIVR1(1'b0), .DIVR0(1'b0), + .RANGE2(1'b0), .RANGE1(1'b0), .RANGE0(1'b1), + + .LOCK(), // ??? Will it be used? + .PLLOUT(usb_clk_o) + ); + + //assign usb_clk = scan_mode_i ? usbclk_byp_i : usb_clk_o; + MUX2_X2_HVT i_usb_clk_mux ( .A(usb_clk_o), .B(usbclk_byp_i), .S(scan_mode_i), .Z(usb_clk) ); + +endmodule + diff --git a/demo_chip_rtl/rtl/demo_chip/nova_wrapper.v b/demo_chip_rtl/rtl/demo_chip/nova_wrapper.v new file mode 100755 index 0000000..6ebabc5 --- /dev/null +++ b/demo_chip_rtl/rtl/demo_chip/nova_wrapper.v @@ -0,0 +1,160 @@ +//////////////////////////////////////////////////////////////////// +// Design : nova_wrapper +// Author(s) : +// Creation date : August 13,2013 +// Copyright (C) ... +//////////////////////////////////////////////////////////////////// +// Description: Includes nova module and associated registers +// +//////////////////////////////////////////////////////////////////// + + +module nova_wrapper( + input clk, + input clk_reg, + input reset_n, + input power_control, + output power_ack, + + //---register access--- + output [15:0] per_dout, + input [13:0] per_addr, + input [15:0] per_din, + input per_en, + input [1:0] per_we, + + input [15:0] BitStream_buffer_input, + output BitStream_ram_ren, + output [16:0] BitStream_ram_addr, + + //---ext_frame_RAM0--- + output ext_frame_RAM0_cs_n, + output ext_frame_RAM0_wr, + output [13:0] ext_frame_RAM0_addr, + input [31:0] ext_frame_RAM0_data, + + //---ext_frame_RAM1--- + output ext_frame_RAM1_cs_n, + output ext_frame_RAM1_wr, + output [13:0] ext_frame_RAM1_addr, + input [31:0] ext_frame_RAM1_data, + + output [31:0] dis_frame_RAM_din + ); + + //assign power_ack=power_control;//To ask RnD how to declare control + //and acknowledgement of power switch chains in RTL + // nova pins stored in registers + wire slice_header_s6; + wire [5:0] pic_num; + wire freq_ctrl0, freq_ctrl1, pin_disable_DF; + + /////////////// + // Registers // + /////////////// + // Code copied and modified from Opencores openMSP430 periph/template_periph_16b.v + + // 1) PARAMETER DECLARATION + + // Register base address (must be aligned to decoder bit width) + parameter [14:0] BASE_ADDR = 15'h0190; + + // Decoder bit width (defines how many bits are considered for address decoding) + parameter DEC_WD = 3; + + // Register addresses offset + parameter [DEC_WD-1:0] CNTRL1 = 'h0, + CNTRL2 = 'h2; + + // Register one-hot decoder utilities + parameter DEC_SZ = (1 << DEC_WD); + parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1}; + + // Register one-hot decoder + parameter [DEC_SZ-1:0] CNTRL1_D = (BASE_REG << CNTRL1), + CNTRL2_D = (BASE_REG << CNTRL2); + + // 2) REGISTER DECODER + + // Local register selection + wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]); + + // Register local address + wire [DEC_WD-1:0] reg_addr = {per_addr[DEC_WD-2:0], 1'b0}; + + // Register address decode + wire [DEC_SZ-1:0] reg_dec = (CNTRL1_D & {DEC_SZ{(reg_addr == CNTRL1 )}}) | + (CNTRL2_D & {DEC_SZ{(reg_addr == CNTRL2 )}}); + + // Read/Write probes + wire reg_write = |per_we & reg_sel; + wire reg_read = ~|per_we & reg_sel; + + // Read/Write vectors + wire [DEC_SZ-1:0] reg_wr = reg_dec & {DEC_SZ{reg_write}}; + wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}}; + + // 3) REGISTERS + + // CNTRL1 Register + wire [15:0] cntrl1; + assign cntrl1 = {slice_header_s6, 9'b0, pic_num[5:0]}; + + + // CNTRL2 Register + reg [15:0] cntrl2; + wire cntrl2_wr = reg_wr[CNTRL2]; + always @ (posedge clk_reg or negedge reset_n) + if (!reset_n) cntrl2 <= 16'h0000; + else if (cntrl2_wr) cntrl2 <= per_din; + + // Reset sync + reg reset_n_sync; + always @ (posedge clk_reg or negedge reset_n) + begin + if (!reset_n) + reset_n_sync <= 1'b0; + else + reset_n_sync <= reset_n; + end + + assign freq_ctrl0 = cntrl2[0]; + assign freq_ctrl1 = cntrl2[1]; + assign pin_disable_DF = cntrl2[2]; + + // 4) DATA OUTPUT GENERATION + + // Data output mux + wire [15:0] cntrl1_rd = cntrl1 & {16{reg_rd[CNTRL1]}}; + wire [15:0] cntrl2_rd = cntrl2 & {16{reg_rd[CNTRL2]}}; + + assign per_dout = cntrl1_rd | cntrl2_rd ; + + + ////////////////// + // NOVA decoder // + ////////////////// + + nova nova ( + .clk(clk), + .reset_n(reset_n_sync), + .freq_ctrl0(freq_ctrl0), + .freq_ctrl1(freq_ctrl1), + .BitStream_buffer_input(BitStream_buffer_input), + .BitStream_ram_ren(BitStream_ram_ren), + .BitStream_ram_addr(BitStream_ram_addr), + .pic_num(pic_num), + .pin_disable_DF(pin_disable_DF), + .ext_frame_RAM0_cs_n(ext_frame_RAM0_cs_n), + .ext_frame_RAM0_wr(ext_frame_RAM0_wr), + .ext_frame_RAM0_addr(ext_frame_RAM0_addr), + .ext_frame_RAM0_data(ext_frame_RAM0_data), + .ext_frame_RAM1_cs_n(ext_frame_RAM1_cs_n), + .ext_frame_RAM1_wr(ext_frame_RAM1_wr), + .ext_frame_RAM1_addr(ext_frame_RAM1_addr), + .ext_frame_RAM1_data(ext_frame_RAM1_data), + .dis_frame_RAM_din(dis_frame_RAM_din), + .slice_header_s6(slice_header_s6) + ); + +endmodule diff --git a/demo_chip_rtl/rtl/demo_chip/powerdown_control.v b/demo_chip_rtl/rtl/demo_chip/powerdown_control.v new file mode 100755 index 0000000..6ce0a67 --- /dev/null +++ b/demo_chip_rtl/rtl/demo_chip/powerdown_control.v @@ -0,0 +1,67 @@ + +// -------------------------------------------------- +// Simple CPU writable register +// Outputs can be used to control power down signals +// -------------------------------------------------- + + +module powerdown_control ( + input clk, + input reset_n, + + //---register access--- + input [13:0] per_addr, + input [31:0] per_din, + input per_en, + input per_we, + input per_rd, + input [31:0] power_ack, + output reg [31:0] per_dout, + output reg [31:0] power_control, + output reg [31:0] power_iso +); + +parameter [13:0] BASE_ADDR = 14'h400; + + + + +always @(posedge clk or negedge reset_n) + begin + if ( reset_n == 1'b0 ) + begin + power_control = 32'h00000000; + power_iso = 32'h00000000; + end + else + begin + // Write reg + if ( per_en == 1'b1 && per_we == 1'b0 && per_addr[13:4] == BASE_ADDR[13:4]) + begin + case (per_addr[3:0]) + 4'h0 : power_control = per_din; + 4'h1 : power_iso = per_din; + endcase + end + + end + end + +// read_reg +always @(*) + begin + if ( per_en == 1'b1 && per_rd == 1'b1 && per_addr[13:4] == BASE_ADDR[13:4]) + begin + case (per_addr[3:0]) + 4'h0 : per_dout = power_control; + 4'h1 : per_dout = power_iso; + 4'h2 : per_dout = power_ack; + default : per_dout = 32'h00000000; + endcase + end + else + per_dout = 32'h00000000; + end + + +endmodule diff --git a/demo_chip_rtl/rtl/demo_chip/usb_sys.v b/demo_chip_rtl/rtl/demo_chip/usb_sys.v new file mode 100755 index 0000000..7d3332b --- /dev/null +++ b/demo_chip_rtl/rtl/demo_chip/usb_sys.v @@ -0,0 +1,115 @@ +module usb_sys (// WISHBONE Interface + clk_i, rst_i, + wb_addr_i, wb_data_i, wb_data_o, + wb_we_i, wb_stb_i, inta_o, intb_o, + + // UTMI Interface + phy_clk_pad_i, phy_rst_pad_o, + DataOut_pad_o, TxValid_pad_o, TxReady_pad_i, + + RxValid_pad_i, RxActive_pad_i, RxError_pad_i, +// QSG DataIn_pad_i, LineState_pad_i, power_control, power_ack + DataIn_pad_i, LineState_pad_i + + ); + +//QSG input power_control; +//QSG output power_ack; +input clk_i; +input rst_i; +input [17:0] wb_addr_i; +input [31:0] wb_data_i; +output [31:0] wb_data_o; +input wb_we_i; +input wb_stb_i; +output inta_o; +output intb_o; + +input phy_clk_pad_i; +output phy_rst_pad_o; + +output [7:0] DataOut_pad_o; +output TxValid_pad_o; +input TxReady_pad_i; + +input [7:0] DataIn_pad_i; +input RxValid_pad_i; +input RxActive_pad_i; +input RxError_pad_i; + +input [1:0] LineState_pad_i; + +wire [13:0] usb_buf_addr; +wire [31:0] usb_buf_dout; +wire [31:0] usb_buf_din; +wire usb_buf_wen; +wire usb_buf_ren; + +usbf_top i_usbf ( +//QSG .power_control(power_control), +//QSG .power_ack(power_ack), + + // WISHBONE Interface + .clk_i(clk_i), + .rst_i(rst_i), + .wb_addr_i(wb_addr_i), + .wb_data_i(wb_data_i), + .wb_data_o(wb_data_o), + .wb_ack_o(), + .wb_we_i(wb_we_i), + .wb_stb_i(wb_stb_i), + .wb_cyc_i(1'b0), + .inta_o(inta_o), + .intb_o(intb_o), + .dma_req_o(), + .dma_ack_i(16'b0), + .susp_o(), + .resume_req_i(1'b0), + // UTMI Interface + .phy_clk_pad_i(phy_clk_pad_i), + .phy_rst_pad_o(phy_rst_pad_o), + .DataOut_pad_o(DataOut_pad_o), + .TxValid_pad_o(TxValid_pad_o), + .TxReady_pad_i(TxReady_pad_i), + + + + + + .RxValid_pad_i (RxValid_pad_i), + .RxActive_pad_i (RxActive_pad_i), + .RxError_pad_i (RxError_pad_i), + .DataIn_pad_i (DataIn_pad_i), + .XcvSelect_pad_o (), + .TermSel_pad_o (), + .SuspendM_pad_o (), + .LineState_pad_i (LineState_pad_i), + + .OpMode_pad_o(), + .usb_vbus_pad_i(1'b0), + .VControl_Load_pad_o(), + .VControl_pad_o(), + .VStatus_pad_i(8'b0), + + // Buffer Memory Interface + .sram_adr_o(usb_buf_addr), + .sram_data_i(usb_buf_dout), + .sram_data_o(usb_buf_din), + .sram_re_o(usb_buf_ren), + .sram_we_o(usb_buf_wen) + + + ); + + +MemGen_32_14 usb_buffer_mem ( + .chip_en(1'b1), + .clock(clk_i), + .addr(usb_buf_addr), + .rd_data(usb_buf_dout), + .rd_en(usb_buf_ren), + .wr_data(usb_buf_din), + .wr_en(usb_buf_wen ) + ); + +endmodule diff --git a/demo_chip_rtl/rtl/hpdmc/trunk/csr.pdf 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b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/doc/hpdmc.tex @@ -0,0 +1,232 @@ +\documentclass[a4paper,11pt]{article} +\usepackage{fullpage} +\usepackage[latin1]{inputenc} +\usepackage[T1]{fontenc} +\usepackage[normalem]{ulem} +\usepackage[english]{babel} +\usepackage{listings,babel} +\lstset{breaklines=true,basicstyle=\ttfamily} +\usepackage{graphicx} +\usepackage{moreverb} +\usepackage{url} +\usepackage{float} +\usepackage{tabularx} + +\title{High Performance Dynamic Memory Controller} +\author{S\'ebastien Bourdeauducq} +\date{December 2009} +\begin{document} +\setlength{\parindent}{0pt} +\setlength{\parskip}{5pt} +\maketitle{} +\section{Specifications} +This controller is targeted at high bandwidth applications such as live video processing. + +It is designed to drive 32-bit DDR SDRAM memory (which can be physically made up of two 16-bit chips). + +The memory contents are accessed through a 64-bit FML (Fast Memory Link) bus with a burst length of 4. FML is a burst-oriented bus designed to ease the design of DRAM controllers. Its signaling resembles WISHBONE, but basically removes all corner cases with burst modes to save on logic resources and aspirin. + +HPDMC provides high flexibility and savings on hardware by implementing a bypass mode which gives the CPU low-level access to the SDRAM command interface (address pins, bank address pins, and CKE, CS, WE, CAS and RAS). The SDRAM initialization sequence is assigned to the CPU, which should use this mode to implement it. Timing parameters are also configurable at runtime. These control interfaces are accessed on a 32-bit CSR bus, separate from the data bus. The CSR bus is a proprietary bus designed for Milkymist that helps reduce the FPGA resource usage and avoid failed timing paths on the system bus. + +Due to the use of \verb!IDDR!, \verb!ODDR! and \verb!IDELAY! primitives, HPDMC currently only supports the Virtex-4 FPGAs. + +\section{Architecture} + +\begin{figure}[H] +\centering +\includegraphics[height=100mm]{blockdiagram.eps} +\caption{Block diagram of the HPDMC architecture.}\label{fig:blockdiagram} +\end{figure} + +\subsection{Control interface} +The control interface provides a register bank on a low-speed dedicated CSR bus, which is used to control the operating mode of the core, set timings, and initialize the SDRAM. + +The interface can access directly the SDRAM address and command bus in the so-called \textit{bypass mode}. In this mode, the memory controller is disabled and the CPU can control each pin of the SDRAM control bus through the bypass register. + +This mode should be used at system boot-up to perform the SDRAM initialization sequence. HPDMC does not provide a hardware state machine that does such initialization. + +The mapped registers are the following (addresses are in bytes to match the addresses seen by the CPU when the CSR bus is bridged to Wishbone) : + +\subsubsection{System register, offset 0x00} +\begin{tabularx}{\textwidth}{|l|l|l|X|} +\hline +\bf Bits & \bf Access & \bf Default & \bf Description \\ +\hline +0 & RW & 1 & Bypass mode enable. Setting this bit transfers control of the SDRAM command and address bus from HPDMC to the system CPU. This bit should be set during the SDRAM initialization sequence and cleared during normal memory access. \\ +\hline +1 & RW & 1 & Reset. This bit should be cleared during normal operation and set while reconfiguring the memory subsystem. \\ +\hline +2 & RW & 0 & CKE control. This bit directly drives the CKE pin of the SDRAM and should be always set except during the first stage of the initialization sequence. The core does not support SDRAM power-down modes, so clearing this bit during normal operation results in undefined behaviour. \\ +\hline +31 -- 3 & --- & 0 & Reserved. \\ +\hline +\end{tabularx} + +\subsubsection{Bypass register, offset 0x04} +The bypass register gives the system CPU low-level access to the SDRAM. It must be used at system power-up to initialize the SDRAM, as the controller does not provide this initialization. Such software initialization of the SDRAM provides greater flexibility and saves valuable hardware resources. + +Writing once to this register issues \textbf{one} transaction to the SDRAM command bus, ie. the values written to the CS, WE, RAS and CAS bits are only taken into account for one clock cycle, and then the signals go back to their default inactive state. + +The values written to this register have an effect on the SDRAM only if the controller is put in bypass mode using the system register.\\ + +\begin{tabularx}{\textwidth}{|l|l|l|X|} +\hline +\bf Bits & \bf Access & \bf Default & \bf Description \\ +\hline +0 & W & 0 & CS control. Setting this bit activates the CS line of the SDRAM during the command transaction that results from writing to the bypass register. As the SDRAM control bus is active low, setting this bit actually puts a '0' logic level to the CS line. \\ +\hline +1 & W & 0 & WE control (same as above). \\ +\hline +2 & W & 0 & CAS control (same as above). \\ +\hline +3 & W & 0 & RAS control (same as above). \\ +\hline +16 -- 4 & RW & 0 & Address. Defines the current state of the address pins. \\ +\hline +18 -- 17 & RW & 0 & Bank address. Defines the current state of the bank address pins. \\ +\hline +31 -- 19 & --- & 0 & Reserved. \\ +\hline +\end{tabularx}\\ + +\textit{NB. When this register is written, the address pins change synchronously at the same time as the command pins, so there is no need to pre-position the address bits before issuing a command. Commands like loading the mode register can therefore be performed with a single write to this register.} + +\subsubsection{Timing register, offset 0x08} +This register allows the CPU to tune the behaviour of HPDMC so that it meets SDRAM timing requirements while avoiding unnecessary wait cycles. + +The controller must be held in reset using the system register when the timing register is modified.\\ + +\begin{tabularx}{\textwidth}{|l|l|l|X|} +\hline +\bf Bits & \bf Access & \bf Default & \bf Description \\ +\hline +2 -- 0 & RW & 2 & Number of clock cycles the scheduler must wait following a Precharge command. Usually referred to as $t_{RP}$ in SDRAM datasheets. \\ +\hline +5 -- 3 & RW & 2 & Number of clock cycles the scheduler must wait following an Activate command. Usually referred to as $t_{RCD}$ in SDRAM datasheets. \\ +\hline +6 & RW & 0 & CAS latency : 0 = CL2, 1 = CL3. CL2.5 is not supported. \\ +\hline +17 -- 7 & RW & 740 & Autorefresh period, in clock cycles. This is the time between \textbf{each} Auto Refresh command that is issued to the SDRAM, not the delay between two consecutive refreshes of a particular row. Usually referred to as $t_{REFI}$ in SDRAM datasheets, which is often 7.8$\mu$s (64ms is an improbable value for this field). \\ +\hline +21 -- 18 & RW & 8 & Number of clock cycles the controller must wait following an Auto Refresh command. Usually referred to as $t_{RFC}$ in SDRAM datasheets. \\ +\hline +23 -- 22 & RW & 1 & Number of clock cycles the controller must wait following the last data sent to the SDRAM during a write. Usually referred to as $t_{WR}$ in SDRAM datasheets. \\ +\hline +31 -- 24 & --- & 0 & Reserved. \\ +\hline +\end{tabularx}\\ + +\textit{NB. The default values are example only, and must be adapted to your particular setup.} + +\subsubsection{Delay register, offset 0x0C} +This register controls the amount of delay that is introduced on the data lines when reading from memory. It directly controls the \verb!IDELAY! elements that are inserted between the pins and the \verb!IDDR! registers. + +Writing once to the register toggles the \verb!IDELAY! control signals \textbf{once}, that is to say, the signals will be active for one clock cycle and then go back to their default zero state. + +This register also controls the amount of phase shift that is introduced between the system clock and DQS (typically 90 degrees). HPDMC provides three signals, \verb!dqs_psen!, \verb!dqs_psincdec! and \verb!dqs_psdone! that should be connected to the DCM used to generate the DQS clock which is controlled by this register. + +The enable and incrementation bits work the same as for \verb!IDELAY!. They should only be used when the ready bit (5) is set.\\ + +\begin{tabularx}{\textwidth}{|l|l|l|X|} +\hline +\bf Bits & \bf Access & \bf Default & \bf Description \\ +\hline +0 & W & 0 & Resets delay to 0. If this bit is set, the others are ignored. \\ +\hline +1 & W & 0 & Increments or decrements delay by one tap (typically 78ps). If the bit 2 is set at the same time this bit is written, the tap delay is incremented. Otherwise, it is decremented. \\ +\hline +2 & W & 0 & Selects between incrementation and decrementation of the input tap delay. \\ +\hline +3 & W & 0 & Increments or decrements the phase shift on DQS. If the bit 4 is set at the same time this bit is written, the phase shift is incremented. Otherwise, it is decremented. The phase shift is typically between -255 and 255 and is expressed in 1/256ths of the clock period. \\ +\hline +4 & W & 0 & Selects between incrementation and decrementation of the DQS phase shift. \\ +\hline +5 & R & 0 & When this bit is set, the DCM used to generate DQS is ready for phase shift. \\ +\hline +7--6 & R & 0 & Retreives the values of the pll\_stat inputs of the core. These inputs are internally double-latched so that they can directly accept asynchronous signals. They are intended to monitor the lock status of the DCMs used to generate the SDRAM and DQS clocks. \\ +\hline +31--8 & --- & 0 & Reserved. \\ +\hline +\end{tabularx} + +This register can be written to at any time. + + +\subsection{SDRAM management unit} +The SDRAM management unit is a state machine which controls sequentially the SDRAM address and command bus. Unless the core is in bypass mode, the management unit has full control over the SDRAM bus. + +This unit is responsible for precharging banks, activating rows, periodically refreshing the DRAM, and sending read and write commands to the SDRAM. + +It has inputs connected to the control interface registers to retreive the $t_{RP}$, $t_{RCD}$, $t_{REFI}$ and $t_{RFC}$ timing values, as well as the row idle time. + +It handles read and write requests through a port made up of four elements : +\begin{itemize} +\item a strobe input +\item a write enable input (which tells if the command to send to the SDRAM should be a read or a write) +\item an address input +\item an acknowledgement output +\end{itemize} + +The protocol used on these signals is close to the one employed in Wishbone. The strobe signal indicates when a new command should be completed, and remains asserted (with other signals kept constant) until the acknowledgement signal is asserted. At the next clock cycle, a new command should be presented, or the strobe signal should be de-asserted. + +In HPDMC, those signals are driven by the bus interface. + +The management unit also signals the data path when it has sent a read or a write command into the SDRAM. The signal is asserted exactly at the same time as the command is asserted. + +It receives \verb!read_safe!, \verb!write_safe! and \verb!precharge_safe! signals from the data path, whose meanings are explained below. + +\subsection{Data path controller} +The data path controller is responsible for : +\begin{itemize} +\item deciding the direction of the DQ and DQS pins +\item delaying read, write and precharge commands from the management unit that would create conflicts +\end{itemize} + +The delaying of the commands is acheived through the use of three signals : +\begin{itemize} +\item \verb!read_safe! : when this signal is asserted, it is safe to send a Read command to the SDRAM. This is used to prevent conflicts on the data bus : this signal is asserted when, taking into account the CAS latency and the burst length, the resulting burst would not overlap the currently running one. +\item \verb!write_safe! : same thing, for the Write command. +\item \verb!concerned_bank[3..0]! : when the management unit issues a Read or Write command, it must inform the data path controller about the bank which the transfer takes place in, using this one-hot encoded signal. +\item \verb!precharge_safe[3..0]! : when a bit in this signal is asserted, it is safe to precharge the corresponding bank. The management unit must use this signal so as not to precharge a bank interrupting a read burst or causing a write-to-precharge violation. +\end{itemize} + +The data path controller is also connected to the control interface, to retreive $t_{WR}$ and the CAS latency. + +\subsection{Data path} +Data is captured from or sent to the SDRAM using \verb!IDDR! and \verb!ODDR! primitives, in order to limit timing nightmares with ISE. + +When writing to the DDRAM, the \verb!ODDR! primitive puts out data synchronously to the rising and falling edges of the system clock. This was chosen to ease timing between the FML (which is clocked by the system clock) and the I/O elements without introducing additional latency cycles. The data should therefore be strobed by DQS after a short time following each system clock edge. A delay corresponding to a 90 degrees phase shift gives the best margins, and can be controlled using the delay register. + +When reading from the DDRAM, the \verb!IDDR! element is also clocked by the system clock for the same reason. The data must therefore be delayed by typically one quarter of the clock cycle so that it becomes center-aligned with the system clock edges. \verb!IDELAY! primitives are used for this purpose. DQS lines are not used for reading. + +\verb!ODDR!, \verb!IDDR! and \verb!IDELAY! are only supported on Virtex-4 FPGAs, but have equivalents in other families. + +\subsection{Bus interface} +The bus interface is responsible for sending commands to the SDRAM management unit according to the request coming from the FML, and acknowledging bus cycles at the appropriate time. + +\section{Using the core} +\subsection{Connecting} +The differential clock going to the SDRAM chips should be generated using a dedicated FPGA clocking resource, such as a DCM. It is bad practice to simply add an inverter on the negative clock line, as the inverter will also add a delay. + +This DCM can also introduce a 90 degree delay on the clock and the resulting signal be used to generate DQS by connecting it to the \verb!dqs_clk! input of the HPDMC top-level. + +HPDMC uses \verb!IDELAY! elements internally, but does not include the required \verb!IDELAYCTRL! primitive. You must instantiate an \verb!IDELAYCTRL! in your design, generate the 200MHz reference clock and connect it to the \verb!IDELAYCTRL! through a \verb!BUFG!. The other signals of \verb!IDELAYCTRL! can be left unused. + +\subsection{Programming} +When the system is powered up, HPDMC comes up in bypass mode and the SDRAM initialization sequence should be performed from then, by controlling the pins at a low level using the bypass register. + +The SDRAM must be programmed to use a fixed burst length of 8\footnote{It might seem surprising that the burst length of the SDRAM and FML are not the same. This is because DDR SDRAM counts the words on both clock edges. Here, a burst of 8 32-bit words sent at double data rate on the SDRAM side corresponds to a burst of 4 64-bit words at single data rate on the FML side.}, and a CAS latency of 2 (preferred) or 3. CAS latency 2.5 is not supported. + +HPDMC's timing registers may also have to be reprogrammed to match the memory chip's parameters. If a DIMM is used, it is possible to read those parameters from the serial presence detect (SPD) EEPROM and program HPDMC accordingly. + +Once the SDRAM is initialized and the timing registers are programmed, the controller can be brought up by clearing the bypass and reset bits from the system register. + +You may also need to tune the data capture delay. Reset the tap count to 0 by writing bit 0 to the delay register, then increment the delay to the desired value by repeatedly writing bits 1 and 2 simultaneously. + +The DQS phase shift may also be adjusted. The procedure is the same, except that the delay cannot be reset and that the ready bit should be set when writing the enable and incrementation bits. The memory is now ready to be accessed over the FML interface. + +\section*{Copyright notice} +Copyright \copyright 2007-2009 S\'ebastien Bourdeauducq. \\ +Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the LICENSE.FDL file at the root of the Milkymist source distribution. + +\end{document} diff --git a/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/hpdmc.v b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/hpdmc.v new file mode 100644 index 0000000..3a6b77d --- /dev/null +++ b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/hpdmc.v @@ -0,0 +1,298 @@ +/* + * Milkymist VJ SoC + * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 3 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +module hpdmc #( + parameter csr_addr = 4'h0, + /* + * The depth of the SDRAM array, in bytes. + * Capacity (in bytes) is 2^sdram_depth. + */ + parameter sdram_depth = 26, + + /* + * The number of column address bits of the SDRAM. + */ + parameter sdram_columndepth = 9 +) ( + input sys_clk, + input sys_clk_n, + /* + * Clock used to generate DQS. + * Typically sys_clk phased out by 90 degrees, + * as data is sent synchronously to sys_clk. + */ + input dqs_clk, + input dqs_clk_n, + + input sys_rst, + + /* Control interface */ + input [13:0] csr_a, + input csr_we, + input [31:0] csr_di, + output [31:0] csr_do, + + /* Simple FML 4x64 interface to the memory contents */ + input [sdram_depth-1:0] fml_adr, + input fml_stb, + input fml_we, + output fml_ack, + input [7:0] fml_sel, + input [63:0] fml_di, + output [63:0] fml_do, + + /* SDRAM interface. + * The SDRAM clock should be driven synchronously to the system clock. + * It is not generated inside this core so you can take advantage of + * architecture-dependent clocking resources to generate a clean + * differential clock. + */ + output reg sdram_cke, + output reg sdram_cs_n, + output reg sdram_we_n, + output reg sdram_cas_n, + output reg sdram_ras_n, + output reg [12:0] sdram_adr, + output reg [1:0] sdram_ba, + + output [3:0] sdram_dm, + inout [31:0] sdram_dq, + inout [3:0] sdram_dqs, + + /* Interface to the DCM generating DQS */ + output dqs_psen, + output dqs_psincdec, + input dqs_psdone, + + input [1:0] pll_stat +); + +/* Register all control signals, leaving the possibility to use IOB registers */ +wire sdram_cke_r; +wire sdram_cs_n_r; +wire sdram_we_n_r; +wire sdram_cas_n_r; +wire sdram_ras_n_r; +wire [12:0] sdram_adr_r; +wire [1:0] sdram_ba_r; + +always @(posedge sys_clk) begin + sdram_cke <= sdram_cke_r; + sdram_cs_n <= sdram_cs_n_r; + sdram_we_n <= sdram_we_n_r; + sdram_cas_n <= sdram_cas_n_r; + sdram_ras_n <= sdram_ras_n_r; + sdram_ba <= sdram_ba_r; + sdram_adr <= sdram_adr_r; +end + +/* Mux the control signals according to the "bypass" selection. + * CKE always comes from the control interface. + */ +wire bypass; + +wire sdram_cs_n_bypass; +wire sdram_we_n_bypass; +wire sdram_cas_n_bypass; +wire sdram_ras_n_bypass; +wire [12:0] sdram_adr_bypass; +wire [1:0] sdram_ba_bypass; + +wire sdram_cs_n_mgmt; +wire sdram_we_n_mgmt; +wire sdram_cas_n_mgmt; +wire sdram_ras_n_mgmt; +wire [12:0] sdram_adr_mgmt; +wire [1:0] sdram_ba_mgmt; + +assign sdram_cs_n_r = bypass ? sdram_cs_n_bypass : sdram_cs_n_mgmt; +assign sdram_we_n_r = bypass ? sdram_we_n_bypass : sdram_we_n_mgmt; +assign sdram_cas_n_r = bypass ? sdram_cas_n_bypass : sdram_cas_n_mgmt; +assign sdram_ras_n_r = bypass ? sdram_ras_n_bypass : sdram_ras_n_mgmt; +assign sdram_adr_r = bypass ? sdram_adr_bypass : sdram_adr_mgmt; +assign sdram_ba_r = bypass ? sdram_ba_bypass : sdram_ba_mgmt; + +/* Control interface */ +wire sdram_rst; + +wire [2:0] tim_rp; +wire [2:0] tim_rcd; +wire tim_cas; +wire [10:0] tim_refi; +wire [3:0] tim_rfc; +wire [1:0] tim_wr; + +wire idelay_rst; +wire idelay_ce; +wire idelay_inc; + +hpdmc_ctlif #( + .csr_addr(csr_addr) +) ctlif ( + .sys_clk(sys_clk), + .sys_rst(sys_rst), + + .csr_a(csr_a), + .csr_we(csr_we), + .csr_di(csr_di), + .csr_do(csr_do), + + .bypass(bypass), + .sdram_rst(sdram_rst), + + .sdram_cke(sdram_cke_r), + .sdram_cs_n(sdram_cs_n_bypass), + .sdram_we_n(sdram_we_n_bypass), + .sdram_cas_n(sdram_cas_n_bypass), + .sdram_ras_n(sdram_ras_n_bypass), + .sdram_adr(sdram_adr_bypass), + .sdram_ba(sdram_ba_bypass), + + .tim_rp(tim_rp), + .tim_rcd(tim_rcd), + .tim_cas(tim_cas), + .tim_refi(tim_refi), + .tim_rfc(tim_rfc), + .tim_wr(tim_wr), + + .idelay_rst(idelay_rst), + .idelay_ce(idelay_ce), + .idelay_inc(idelay_inc), + + .dqs_psen(dqs_psen), + .dqs_psincdec(dqs_psincdec), + .dqs_psdone(dqs_psdone), + + .pll_stat(pll_stat) +); + +/* SDRAM management unit */ +wire mgmt_stb; +wire mgmt_we; +wire [sdram_depth-3-1:0] mgmt_address; +wire mgmt_ack; + +wire read; +wire write; +wire [3:0] concerned_bank; +wire read_safe; +wire write_safe; +wire [3:0] precharge_safe; + +hpdmc_mgmt #( + .sdram_depth(sdram_depth), + .sdram_columndepth(sdram_columndepth) +) mgmt ( + .sys_clk(sys_clk), + .sdram_rst(sdram_rst), + + .tim_rp(tim_rp), + .tim_rcd(tim_rcd), + .tim_refi(tim_refi), + .tim_rfc(tim_rfc), + + .stb(mgmt_stb), + .we(mgmt_we), + .address(mgmt_address), + .ack(mgmt_ack), + + .read(read), + .write(write), + .concerned_bank(concerned_bank), + .read_safe(read_safe), + .write_safe(write_safe), + .precharge_safe(precharge_safe), + + .sdram_cs_n(sdram_cs_n_mgmt), + .sdram_we_n(sdram_we_n_mgmt), + .sdram_cas_n(sdram_cas_n_mgmt), + .sdram_ras_n(sdram_ras_n_mgmt), + .sdram_adr(sdram_adr_mgmt), + .sdram_ba(sdram_ba_mgmt) +); + +/* Bus interface */ +wire data_ack; + +hpdmc_busif #( + .sdram_depth(sdram_depth) +) busif ( + .sys_clk(sys_clk), + .sdram_rst(sdram_rst), + + .fml_adr(fml_adr), + .fml_stb(fml_stb), + .fml_we(fml_we), + .fml_ack(fml_ack), + + .mgmt_stb(mgmt_stb), + .mgmt_we(mgmt_we), + .mgmt_address(mgmt_address), + .mgmt_ack(mgmt_ack), + + .data_ack(data_ack) +); + +/* Data path controller */ +wire direction; +wire direction_r; + +hpdmc_datactl datactl( + .sys_clk(sys_clk), + .sdram_rst(sdram_rst), + + .read(read), + .write(write), + .concerned_bank(concerned_bank), + .read_safe(read_safe), + .write_safe(write_safe), + .precharge_safe(precharge_safe), + + .ack(data_ack), + .direction(direction), + .direction_r(direction_r), + + .tim_cas(tim_cas), + .tim_wr(tim_wr) +); + +/* Data path */ +hpdmc_ddrio ddrio( + .sys_clk(sys_clk), + .sys_clk_n(sys_clk_n), + .dqs_clk(dqs_clk), + .dqs_clk_n(dqs_clk_n), + + .direction(direction), + .direction_r(direction_r), + /* Bit meaning is the opposite between + * the FML selection signal and SDRAM DM pins. + */ + .mo(~fml_sel), + .do(fml_di), + .di(fml_do), + + .sdram_dm(sdram_dm), + .sdram_dq(sdram_dq), + .sdram_dqs(sdram_dqs), + + .idelay_rst(idelay_rst), + .idelay_ce(idelay_ce), + .idelay_inc(idelay_inc) +); + +endmodule diff --git a/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/hpdmc_banktimer.v b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/hpdmc_banktimer.v new file mode 100644 index 0000000..dbfad4b --- /dev/null +++ b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/hpdmc_banktimer.v @@ -0,0 +1,57 @@ +/* + * Milkymist VJ SoC + * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 3 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +module hpdmc_banktimer( + input sys_clk, + input sdram_rst, + + input tim_cas, + input [1:0] tim_wr, + + input read, + input write, + output reg precharge_safe +); + +reg [2:0] counter; +always @(posedge sys_clk) begin + if(sdram_rst) begin + counter <= 3'd0; + precharge_safe <= 1'b1; + end else begin + if(read) begin + /* see p.26 of datasheet : + * "A Read burst may be followed by, or truncated with, a Precharge command + * to the same bank. The Precharge command should be issued x cycles after + * the Read command, where x equals the number of desired data element + * pairs" + */ + counter <= 3'd4; + precharge_safe <= 1'b0; + end else if(write) begin + counter <= {1'b1, tim_wr}; + precharge_safe <= 1'b0; + end else begin + if(counter == 3'b1) + precharge_safe <= 1'b1; + if(~precharge_safe) + counter <= counter - 3'b1; + end + end +end + +endmodule diff --git a/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/hpdmc_busif.v b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/hpdmc_busif.v new file mode 100644 index 0000000..e053913 --- /dev/null +++ b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/hpdmc_busif.v @@ -0,0 +1,58 @@ +/* + * Milkymist VJ SoC + * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 3 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Simple FML interface for HPDMC */ + +module hpdmc_busif #( + parameter sdram_depth = 26 +) ( + input sys_clk, + input sdram_rst, + + input [sdram_depth-1:0] fml_adr, + input fml_stb, + input fml_we, + output fml_ack, + + output mgmt_stb, + output mgmt_we, + output [sdram_depth-3-1:0] mgmt_address, /* in 64-bit words */ + input mgmt_ack, + + input data_ack +); + +reg mgmt_stb_en; + +assign mgmt_stb = fml_stb & mgmt_stb_en; +assign mgmt_we = fml_we; +assign mgmt_address = fml_adr[sdram_depth-1:3]; + +assign fml_ack = data_ack; + +always @(posedge sys_clk) begin + if(sdram_rst) + mgmt_stb_en = 1'b1; + else begin + if(mgmt_ack) + mgmt_stb_en = 1'b0; + if(data_ack) + mgmt_stb_en = 1'b1; + end +end + +endmodule diff --git a/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/hpdmc_ctlif.v b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/hpdmc_ctlif.v new file mode 100644 index 0000000..56ff6be --- /dev/null +++ b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/hpdmc_ctlif.v @@ -0,0 +1,157 @@ +/* + * Milkymist VJ SoC + * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 3 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +module hpdmc_ctlif #( + parameter csr_addr = 4'h0 +) ( + input sys_clk, + input sys_rst, + + input [13:0] csr_a, + input csr_we, + input [31:0] csr_di, + output reg [31:0] csr_do, + + output reg bypass, + output reg sdram_rst, + + output reg sdram_cke, + output reg sdram_cs_n, + output reg sdram_we_n, + output reg sdram_cas_n, + output reg sdram_ras_n, + output reg [12:0] sdram_adr, + output reg [1:0] sdram_ba, + + /* Clocks we must wait following a PRECHARGE command (usually tRP). */ + output reg [2:0] tim_rp, + /* Clocks we must wait following an ACTIVATE command (usually tRCD). */ + output reg [2:0] tim_rcd, + /* CAS latency, 0 = 2 */ + output reg tim_cas, + /* Auto-refresh period (usually tREFI). */ + output reg [10:0] tim_refi, + /* Clocks we must wait following an AUTO REFRESH command (usually tRFC). */ + output reg [3:0] tim_rfc, + /* Clocks we must wait following the last word written to the SDRAM (usually tWR). */ + output reg [1:0] tim_wr, + + output reg idelay_rst, + output reg idelay_ce, + output reg idelay_inc, + + output reg dqs_psen, + output reg dqs_psincdec, + input dqs_psdone, + + input [1:0] pll_stat +); + +reg psready; +always @(posedge sys_clk) begin + if(dqs_psdone) + psready <= 1'b1; + else if(dqs_psen) + psready <= 1'b0; +end + +wire csr_selected = csr_a[13:10] == csr_addr; + +/* Double-latching on pll_stat (asynchronous) */ +reg [1:0] pll_stat1; +reg [1:0] pll_stat2; +always @(posedge sys_clk) begin + pll_stat1 <= pll_stat; + pll_stat2 <= pll_stat1; +end + +always @(posedge sys_clk) begin + if(sys_rst) begin + csr_do <= 32'd0; + + bypass <= 1'b1; + sdram_rst <= 1'b1; + + sdram_cke <= 1'b0; + sdram_adr <= 13'd0; + sdram_ba <= 2'd0; + + tim_rp <= 3'd2; + tim_rcd <= 3'd2; + tim_cas <= 1'b0; + tim_refi <= 11'd740; + tim_rfc <= 4'd8; + tim_wr <= 2'd2; + end else begin + sdram_cs_n <= 1'b1; + sdram_we_n <= 1'b1; + sdram_cas_n <= 1'b1; + sdram_ras_n <= 1'b1; + + idelay_rst <= 1'b0; + idelay_ce <= 1'b0; + idelay_inc <= 1'b0; + + dqs_psen <= 1'b0; + dqs_psincdec <= 1'b0; + + csr_do <= 32'd0; + if(csr_selected) begin + if(csr_we) begin + case(csr_a[1:0]) + 2'b00: begin + bypass <= csr_di[0]; + sdram_rst <= csr_di[1]; + sdram_cke <= csr_di[2]; + end + 2'b01: begin + sdram_cs_n <= ~csr_di[0]; + sdram_we_n <= ~csr_di[1]; + sdram_cas_n <= ~csr_di[2]; + sdram_ras_n <= ~csr_di[3]; + sdram_adr <= csr_di[16:4]; + sdram_ba <= csr_di[18:17]; + end + 2'b10: begin + tim_rp <= csr_di[2:0]; + tim_rcd <= csr_di[5:3]; + tim_cas <= csr_di[6]; + tim_refi <= csr_di[17:7]; + tim_rfc <= csr_di[21:18]; + tim_wr <= csr_di[23:22]; + end + 2'b11: begin + idelay_rst <= csr_di[0]; + idelay_ce <= csr_di[1]; + idelay_inc <= csr_di[2]; + + dqs_psen <= csr_di[3]; + dqs_psincdec <= csr_di[4]; + end + endcase + end + case(csr_a[1:0]) + 2'b00: csr_do <= {sdram_cke, sdram_rst, bypass}; + 2'b01: csr_do <= {sdram_ba, sdram_adr, 4'h0}; + 2'b10: csr_do <= {tim_wr, tim_rfc, tim_refi, tim_cas, tim_rcd, tim_rp}; + 2'b11: csr_do <= {pll_stat2, psready, 5'd0}; + endcase + end + end +end + +endmodule diff --git a/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/hpdmc_datactl.v b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/hpdmc_datactl.v new file mode 100644 index 0000000..d0ce96a --- /dev/null +++ b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/hpdmc_datactl.v @@ -0,0 +1,216 @@ +/* + * Milkymist VJ SoC + * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 3 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +module hpdmc_datactl( + input sys_clk, + input sdram_rst, + + input read, + input write, + input [3:0] concerned_bank, + output reg read_safe, + output reg write_safe, + output [3:0] precharge_safe, + + output reg ack, + output reg direction, + output direction_r, + + input tim_cas, + input [1:0] tim_wr +); + +/* + * read_safe: whether it is safe to register a Read command + * into the SDRAM at the next cycle. + */ + +reg [2:0] read_safe_counter; +always @(posedge sys_clk) begin + if(sdram_rst) begin + read_safe_counter <= 3'd0; + read_safe <= 1'b1; + end else begin + if(read) begin + read_safe_counter <= 3'd4; + read_safe <= 1'b0; + end else if(write) begin + /* after a write, read is unsafe for 5 cycles (4 transfers + tWTR=1) */ + read_safe_counter <= 3'd5; + read_safe <= 1'b0; + end else begin + if(read_safe_counter == 3'd1) + read_safe <= 1'b1; + if(~read_safe) + read_safe_counter <= read_safe_counter - 3'd1; + end + end +end + +/* + * write_safe: whether it is safe to register a Write command + * into the SDRAM at the next cycle. + */ + +reg [2:0] write_safe_counter; +always @(posedge sys_clk) begin + if(sdram_rst) begin + write_safe_counter <= 3'd0; + write_safe <= 1'b1; + end else begin + if(read) begin + write_safe_counter <= {1'b1, tim_cas, ~tim_cas}; + write_safe <= 1'b0; + end else if(write) begin + write_safe_counter <= 3'd3; + write_safe <= 1'b0; + end else begin + if(write_safe_counter == 3'd1) + write_safe <= 1'b1; + if(~write_safe) + write_safe_counter <= write_safe_counter - 3'd1; + end + end +end + +/* Generate ack signal. + * After write is asserted, it should pulse after 2 cycles. + * After read is asserted, it should pulse after CL+3 cycles, that is + * 5 cycles when tim_cas = 0 + * 6 cycles when tim_cas = 1 + */ + +reg ack_read3; +reg ack_read2; +reg ack_read1; +reg ack_read0; + +always @(posedge sys_clk) begin + if(sdram_rst) begin + ack_read3 <= 1'b0; + ack_read2 <= 1'b0; + ack_read1 <= 1'b0; + ack_read0 <= 1'b0; + end else begin + if(tim_cas) begin + ack_read3 <= read; + ack_read2 <= ack_read3; + ack_read1 <= ack_read2; + ack_read0 <= ack_read1; + end else begin + ack_read2 <= read; + ack_read1 <= ack_read2; + ack_read0 <= ack_read1; + end + end +end + +reg ack0; +always @(posedge sys_clk) begin + if(sdram_rst) begin + ack0 <= 1'b0; + ack <= 1'b0; + end else begin + ack0 <= ack_read0|write; + ack <= ack0; + end +end + +/* during a 4-word write, we drive the pins for 5 cycles + * and 1 cycle in advance (first word is invalid) + * so that we remove glitches on DQS without resorting + * to asynchronous logic. + */ + +/* direction must be glitch-free, as it directly drives the + * tri-state enable for DQ and DQS. + */ +reg write_d; +reg [2:0] counter_writedirection; +always @(posedge sys_clk) begin + if(sdram_rst) begin + counter_writedirection <= 3'd0; + direction <= 1'b0; + end else begin + if(write_d) begin + counter_writedirection <= 3'b101; + direction <= 1'b1; + end else begin + if(counter_writedirection == 3'b001) + direction <= 1'b0; + if(direction) + counter_writedirection <= counter_writedirection - 3'd1; + end + end +end + +assign direction_r = write_d|(|counter_writedirection); + +always @(posedge sys_clk) begin + if(sdram_rst) + write_d <= 1'b0; + else + write_d <= write; +end + +/* Counters that prevent a busy bank from being precharged */ +hpdmc_banktimer banktimer0( + .sys_clk(sys_clk), + .sdram_rst(sdram_rst), + + .tim_cas(tim_cas), + .tim_wr(tim_wr), + + .read(read & concerned_bank[0]), + .write(write & concerned_bank[0]), + .precharge_safe(precharge_safe[0]) +); +hpdmc_banktimer banktimer1( + .sys_clk(sys_clk), + .sdram_rst(sdram_rst), + + .tim_cas(tim_cas), + .tim_wr(tim_wr), + + .read(read & concerned_bank[1]), + .write(write & concerned_bank[1]), + .precharge_safe(precharge_safe[1]) +); +hpdmc_banktimer banktimer2( + .sys_clk(sys_clk), + .sdram_rst(sdram_rst), + + .tim_cas(tim_cas), + .tim_wr(tim_wr), + + .read(read & concerned_bank[2]), + .write(write & concerned_bank[2]), + .precharge_safe(precharge_safe[2]) +); +hpdmc_banktimer banktimer3( + .sys_clk(sys_clk), + .sdram_rst(sdram_rst), + + .tim_cas(tim_cas), + .tim_wr(tim_wr), + + .read(read & concerned_bank[3]), + .write(write & concerned_bank[3]), + .precharge_safe(precharge_safe[3]) +); + +endmodule diff --git a/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/hpdmc_mgmt.v b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/hpdmc_mgmt.v new file mode 100644 index 0000000..047acd8 --- /dev/null +++ b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/hpdmc_mgmt.v @@ -0,0 +1,371 @@ +/* + * Milkymist VJ SoC + * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 3 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +module hpdmc_mgmt #( + parameter sdram_depth = 26, + parameter sdram_columndepth = 9 +) ( + input sys_clk, + input sdram_rst, + + input [2:0] tim_rp, + input [2:0] tim_rcd, + input [10:0] tim_refi, + input [3:0] tim_rfc, + + input stb, + input we, + input [sdram_depth-3-1:0] address, /* in 64-bit words */ + output reg ack, + + output reg read, + output reg write, + output [3:0] concerned_bank, + input read_safe, + input write_safe, + input [3:0] precharge_safe, + + output sdram_cs_n, + output sdram_we_n, + output sdram_cas_n, + output sdram_ras_n, + output [12:0] sdram_adr, + output [1:0] sdram_ba +); + +/* + * Address Mapping : + * | ROW ADDRESS | BANK NUMBER | COL ADDRESS | for 32-bit words + * |depth-1 coldepth+2|coldepth+1 coldepth|coldepth-1 0| + * (depth for 32-bit words, which is sdram_depth-2) + */ + +parameter rowdepth = sdram_depth-2-1-(sdram_columndepth+2)+1; + +wire [sdram_depth-2-1:0] address32 = {address, 1'b0}; + +wire [sdram_columndepth-1:0] col_address = address32[sdram_columndepth-1:0]; +wire [1:0] bank_address = address32[sdram_columndepth+1:sdram_columndepth]; +wire [rowdepth-1:0] row_address = address32[sdram_depth-2-1:sdram_columndepth+2]; + +reg [3:0] bank_address_onehot; +always @(*) begin + case(bank_address) + 2'b00: bank_address_onehot <= 4'b0001; + 2'b01: bank_address_onehot <= 4'b0010; + 2'b10: bank_address_onehot <= 4'b0100; + 2'b11: bank_address_onehot <= 4'b1000; + endcase +end + +/* Track open rows */ +reg [3:0] has_openrow; +reg [rowdepth-1:0] openrows[0:3]; +reg [3:0] track_close; +reg [3:0] track_open; + +always @(posedge sys_clk) begin + if(sdram_rst) begin + has_openrow = 4'h0; + end else begin + has_openrow = (has_openrow | track_open) & ~track_close; + + if(track_open[0]) openrows[0] <= row_address; + if(track_open[1]) openrows[1] <= row_address; + if(track_open[2]) openrows[2] <= row_address; + if(track_open[3]) openrows[3] <= row_address; + end +end + +/* Bank precharge safety */ +assign concerned_bank = bank_address_onehot; +wire current_precharge_safe = + (precharge_safe[0] | ~bank_address_onehot[0]) + &(precharge_safe[1] | ~bank_address_onehot[1]) + &(precharge_safe[2] | ~bank_address_onehot[2]) + &(precharge_safe[3] | ~bank_address_onehot[3]); + + +/* Check for page hits */ +wire bank_open = has_openrow[bank_address]; +wire page_hit = bank_open & (openrows[bank_address] == row_address); + +/* Address drivers */ +reg sdram_adr_loadrow; +reg sdram_adr_loadcol; +reg sdram_adr_loadA10; +assign sdram_adr = + ({13{sdram_adr_loadrow}} & row_address) + |({13{sdram_adr_loadcol}} & col_address) + |({13{sdram_adr_loadA10}} & 13'd1024); + +assign sdram_ba = bank_address; + +/* Command drivers */ +reg sdram_cs; +reg sdram_we; +reg sdram_cas; +reg sdram_ras; +assign sdram_cs_n = ~sdram_cs; +assign sdram_we_n = ~sdram_we; +assign sdram_cas_n = ~sdram_cas; +assign sdram_ras_n = ~sdram_ras; + +/* Timing counters */ + +/* The number of clocks we must wait following a PRECHARGE command (usually tRP). */ +reg [2:0] precharge_counter; +reg reload_precharge_counter; +wire precharge_done = (precharge_counter == 3'd0); +always @(posedge sys_clk) begin + if(reload_precharge_counter) + precharge_counter <= tim_rp; + else if(~precharge_done) + precharge_counter <= precharge_counter - 3'd1; +end + +/* The number of clocks we must wait following an ACTIVATE command (usually tRCD). */ +reg [2:0] activate_counter; +reg reload_activate_counter; +wire activate_done = (activate_counter == 3'd0); +always @(posedge sys_clk) begin + if(reload_activate_counter) + activate_counter <= tim_rcd; + else if(~activate_done) + activate_counter <= activate_counter - 3'd1; +end + +/* The number of clocks we have left before we must refresh one row in the SDRAM array (usually tREFI). */ +reg [10:0] refresh_counter; +reg reload_refresh_counter; +wire must_refresh = refresh_counter == 11'd0; +always @(posedge sys_clk) begin + if(sdram_rst) + refresh_counter <= 11'd0; + else begin + if(reload_refresh_counter) + refresh_counter <= tim_refi; + else if(~must_refresh) + refresh_counter <= refresh_counter - 11'd1; + end +end + +/* The number of clocks we must wait following an AUTO REFRESH command (usually tRFC). */ +reg [3:0] autorefresh_counter; +reg reload_autorefresh_counter; +wire autorefresh_done = (autorefresh_counter == 4'd0); +always @(posedge sys_clk) begin + if(reload_autorefresh_counter) + autorefresh_counter <= tim_rfc; + else if(~autorefresh_done) + autorefresh_counter <= autorefresh_counter - 4'd1; +end + +/* FSM that pushes commands into the SDRAM */ + +reg [3:0] state; +reg [3:0] next_state; + +parameter IDLE = 4'd0; +parameter ACTIVATE = 4'd1; +parameter READ = 4'd2; +parameter WRITE = 4'd3; +parameter PRECHARGEALL = 4'd4; +parameter AUTOREFRESH = 4'd5; +parameter AUTOREFRESH_WAIT = 4'd6; + +always @(posedge sys_clk) begin + if(sdram_rst) + state <= IDLE; + else begin + //$display("state: %d -> %d", state, next_state); + state <= next_state; + end +end + +always @(*) begin + next_state = state; + + reload_precharge_counter = 1'b0; + reload_activate_counter = 1'b0; + reload_refresh_counter = 1'b0; + reload_autorefresh_counter = 1'b0; + + sdram_cs = 1'b0; + sdram_we = 1'b0; + sdram_cas = 1'b0; + sdram_ras = 1'b0; + + sdram_adr_loadrow = 1'b0; + sdram_adr_loadcol = 1'b0; + sdram_adr_loadA10 = 1'b0; + + track_close = 4'b0000; + track_open = 4'b0000; + + read = 1'b0; + write = 1'b0; + + ack = 1'b0; + + case(state) + IDLE: begin + if(must_refresh) + next_state = PRECHARGEALL; + else begin + if(stb) begin + if(page_hit) begin + if(we) begin + if(write_safe) begin + /* Write */ + sdram_cs = 1'b1; + sdram_ras = 1'b0; + sdram_cas = 1'b1; + sdram_we = 1'b1; + sdram_adr_loadcol = 1'b1; + + write = 1'b1; + ack = 1'b1; + end + end else begin + if(read_safe) begin + /* Read */ + sdram_cs = 1'b1; + sdram_ras = 1'b0; + sdram_cas = 1'b1; + sdram_we = 1'b0; + sdram_adr_loadcol = 1'b1; + + read = 1'b1; + ack = 1'b1; + end + end + end else begin + if(bank_open) begin + if(current_precharge_safe) begin + /* Precharge Bank */ + sdram_cs = 1'b1; + sdram_ras = 1'b1; + sdram_cas = 1'b0; + sdram_we = 1'b1; + + track_close = bank_address_onehot; + reload_precharge_counter = 1'b1; + next_state = ACTIVATE; + end + end else begin + /* Activate */ + sdram_cs = 1'b1; + sdram_ras = 1'b1; + sdram_cas = 1'b0; + sdram_we = 1'b0; + sdram_adr_loadrow = 1'b1; + + track_open = bank_address_onehot; + reload_activate_counter = 1'b1; + if(we) + next_state = WRITE; + else + next_state = READ; + end + end + end + end + end + + ACTIVATE: begin + if(precharge_done) begin + sdram_cs = 1'b1; + sdram_ras = 1'b1; + sdram_cas = 1'b0; + sdram_we = 1'b0; + sdram_adr_loadrow = 1'b1; + + track_open = bank_address_onehot; + reload_activate_counter = 1'b1; + if(we) + next_state = WRITE; + else + next_state = READ; + end + end + READ: begin + if(activate_done) begin + if(read_safe) begin + sdram_cs = 1'b1; + sdram_ras = 1'b0; + sdram_cas = 1'b1; + sdram_we = 1'b0; + sdram_adr_loadcol = 1'b1; + + read = 1'b1; + ack = 1'b1; + next_state = IDLE; + end + end + end + WRITE: begin + if(activate_done) begin + if(write_safe) begin + sdram_cs = 1'b1; + sdram_ras = 1'b0; + sdram_cas = 1'b1; + sdram_we = 1'b1; + sdram_adr_loadcol = 1'b1; + + write = 1'b1; + ack = 1'b1; + next_state = IDLE; + end + end + end + + PRECHARGEALL: begin + if(precharge_safe == 4'b1111) begin + sdram_cs = 1'b1; + sdram_ras = 1'b1; + sdram_cas = 1'b0; + sdram_we = 1'b1; + sdram_adr_loadA10 = 1'b1; + + reload_precharge_counter = 1'b1; + + track_close = 4'b1111; + + next_state = AUTOREFRESH; + end + end + AUTOREFRESH: begin + if(precharge_done) begin + sdram_cs = 1'b1; + sdram_ras = 1'b1; + sdram_cas = 1'b1; + sdram_we = 1'b0; + reload_refresh_counter = 1'b1; + reload_autorefresh_counter = 1'b1; + next_state = AUTOREFRESH_WAIT; + end + end + AUTOREFRESH_WAIT: begin + if(autorefresh_done) + next_state = IDLE; + end + + endcase +end + +endmodule diff --git a/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/spartan6/hpdmc_ddrio.v b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/spartan6/hpdmc_ddrio.v new file mode 100644 index 0000000..a05f3e1 --- /dev/null +++ b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/spartan6/hpdmc_ddrio.v @@ -0,0 +1,137 @@ +/* + * Milkymist VJ SoC + * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 3 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +module hpdmc_ddrio( + input sys_clk, + input sys_clk_n, + input dqs_clk, + input dqs_clk_n, + + input direction, + input direction_r, + input [7:0] mo, + input [63:0] do, + output [63:0] di, + + output [3:0] sdram_dm, + inout [31:0] sdram_dq, + inout [3:0] sdram_dqs, + + input idelay_rst, + input idelay_ce, + input idelay_inc +); + +/******/ +/* DQ */ +/******/ + +wire [31:0] sdram_dq_t; +wire [31:0] sdram_dq_out; +wire [31:0] sdram_dq_in; + +hpdmc_iobuf32 iobuf_dq( + .T(sdram_dq_t), + .I(sdram_dq_out), + .O(sdram_dq_in), + .IO(sdram_dq) +); + +hpdmc_oddr32 oddr_dq_t( + .Q(sdram_dq_t), + .C0(sys_clk), + .C1(sys_clk_n), + .CE(1'b1), + .D0({32{~direction_r}}), + .D1({32{~direction_r}}), + .R(1'b0), + .S(1'b0) +); + +hpdmc_oddr32 oddr_dq( + .Q(sdram_dq_out), + .C0(sys_clk), + .C1(sys_clk_n), + .CE(1'b1), + .D0(do[63:32]), + .D1(do[31:0]), + .R(1'b0), + .S(1'b0) +); + +hpdmc_iddr32 iddr_dq( + .Q0(di[31:0]), + .Q1(di[63:32]), + .C0(sys_clk), + .C1(sys_clk_n), + .CE(1'b1), + .D(sdram_dq_in), + .R(1'b0), + .S(1'b0) +); + +/*******/ +/* DM */ +/*******/ + +hpdmc_oddr4 oddr_dm( + .Q(sdram_dm), + .C0(sys_clk), + .C1(sys_clk_n), + .CE(1'b1), + .D0(mo[7:4]), + .D1(mo[3:0]), + .R(1'b0), + .S(1'b0) +); + +/*******/ +/* DQS */ +/*******/ + +wire [3:0] sdram_dqs_t; +wire [3:0] sdram_dqs_out; + +hpdmc_obuft4 obuft_dqs( + .T(sdram_dqs_t), + .I(sdram_dqs_out), + .O(sdram_dqs) +); + +hpdmc_oddr4 oddr_dqs_t( + .Q(sdram_dqs_t), + .C0(dqs_clk), + .C1(dqs_clk_n), + .CE(1'b1), + .D0({4{~direction_r}}), + .D1({4{~direction_r}}), + .R(1'b0), + .S(1'b0) +); + +hpdmc_oddr4 oddr_dqs( + .Q(sdram_dqs_out), + .C0(dqs_clk), + .C1(dqs_clk_n), + .CE(1'b1), + .D0(4'hf), + .D1(4'h0), + .R(1'b0), + .S(1'b0) +); + +endmodule diff --git a/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/spartan6/hpdmc_iddr32.v b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/spartan6/hpdmc_iddr32.v new file mode 100644 index 0000000..241b138 --- /dev/null +++ b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/spartan6/hpdmc_iddr32.v @@ -0,0 +1,522 @@ +/* + * Milkymist VJ SoC + * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 3 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* + * Verilog code that really should be replaced with a generate + * statement, but it does not work with some free simulators. + * So I put it in a module so as not to make other code unreadable, + * and keep compatibility with as many simulators as possible. + */ + +module hpdmc_iddr32 #( + parameter DDR_ALIGNMENT = "C0", + parameter INIT_Q0 = 1'b0, + parameter INIT_Q1 = 1'b0, + parameter SRTYPE = "ASYNC" +) ( + output [31:0] Q0, + output [31:0] Q1, + input C0, + input C1, + input CE, + input [31:0] D, + input R, + input S +); + +IDDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT_Q0(INIT_Q0), + .INIT_Q1(INIT_Q1), + .SRTYPE(SRTYPE) +) iddr0 ( + .Q0(Q0[0]), + .Q1(Q1[0]), + .C0(C0), + .C1(C1), + .CE(CE), + .D(D[0]), + .R(R), + .S(S) +); +IDDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT_Q0(INIT_Q0), + .INIT_Q1(INIT_Q1), + .SRTYPE(SRTYPE) +) iddr1 ( + .Q0(Q0[1]), + .Q1(Q1[1]), + .C0(C0), + .C1(C1), + .CE(CE), + .D(D[1]), + .R(R), + .S(S) +); +IDDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT_Q0(INIT_Q0), + .INIT_Q1(INIT_Q1), + .SRTYPE(SRTYPE) +) iddr2 ( + .Q0(Q0[2]), + .Q1(Q1[2]), + .C0(C0), + .C1(C1), + .CE(CE), + .D(D[2]), + .R(R), + .S(S) +); +IDDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT_Q0(INIT_Q0), + .INIT_Q1(INIT_Q1), + .SRTYPE(SRTYPE) +) iddr3 ( + .Q0(Q0[3]), + .Q1(Q1[3]), + .C0(C0), + .C1(C1), + .CE(CE), + .D(D[3]), + .R(R), + .S(S) +); +IDDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT_Q0(INIT_Q0), + .INIT_Q1(INIT_Q1), + .SRTYPE(SRTYPE) +) iddr4 ( + .Q0(Q0[4]), + .Q1(Q1[4]), + .C0(C0), + .C1(C1), + .CE(CE), + .D(D[4]), + .R(R), + .S(S) +); +IDDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT_Q0(INIT_Q0), + .INIT_Q1(INIT_Q1), + .SRTYPE(SRTYPE) +) iddr5 ( + .Q0(Q0[5]), + .Q1(Q1[5]), + .C0(C0), + .C1(C1), + .CE(CE), + .D(D[5]), + .R(R), + .S(S) +); +IDDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT_Q0(INIT_Q0), + .INIT_Q1(INIT_Q1), + .SRTYPE(SRTYPE) +) iddr6 ( + .Q0(Q0[6]), + .Q1(Q1[6]), + .C0(C0), + .C1(C1), + .CE(CE), + .D(D[6]), + .R(R), + .S(S) +); +IDDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT_Q0(INIT_Q0), + .INIT_Q1(INIT_Q1), + .SRTYPE(SRTYPE) +) iddr7 ( + .Q0(Q0[7]), + .Q1(Q1[7]), + .C0(C0), + .C1(C1), + .CE(CE), + .D(D[7]), + .R(R), + .S(S) +); +IDDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT_Q0(INIT_Q0), + .INIT_Q1(INIT_Q1), + .SRTYPE(SRTYPE) +) iddr8 ( + .Q0(Q0[8]), + .Q1(Q1[8]), + .C0(C0), + .C1(C1), + .CE(CE), + .D(D[8]), + .R(R), + .S(S) +); +IDDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT_Q0(INIT_Q0), + .INIT_Q1(INIT_Q1), + .SRTYPE(SRTYPE) +) iddr9 ( + .Q0(Q0[9]), + .Q1(Q1[9]), + .C0(C0), + .C1(C1), + .CE(CE), + .D(D[9]), + .R(R), + .S(S) +); +IDDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT_Q0(INIT_Q0), + .INIT_Q1(INIT_Q1), + .SRTYPE(SRTYPE) +) iddr10 ( + .Q0(Q0[10]), + .Q1(Q1[10]), + .C0(C0), + .C1(C1), + .CE(CE), + .D(D[10]), + .R(R), + .S(S) +); +IDDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT_Q0(INIT_Q0), + .INIT_Q1(INIT_Q1), + .SRTYPE(SRTYPE) +) iddr11 ( + .Q0(Q0[11]), + .Q1(Q1[11]), + .C0(C0), + .C1(C1), + .CE(CE), + .D(D[11]), + .R(R), + .S(S) +); +IDDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT_Q0(INIT_Q0), + .INIT_Q1(INIT_Q1), + .SRTYPE(SRTYPE) +) iddr12 ( + .Q0(Q0[12]), + .Q1(Q1[12]), + .C0(C0), + .C1(C1), + .CE(CE), + .D(D[12]), + .R(R), + .S(S) +); +IDDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT_Q0(INIT_Q0), + .INIT_Q1(INIT_Q1), + .SRTYPE(SRTYPE) +) iddr13 ( + .Q0(Q0[13]), + .Q1(Q1[13]), + .C0(C0), + .C1(C1), + .CE(CE), + .D(D[13]), + .R(R), + .S(S) +); +IDDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT_Q0(INIT_Q0), + .INIT_Q1(INIT_Q1), + .SRTYPE(SRTYPE) +) iddr14 ( + .Q0(Q0[14]), + .Q1(Q1[14]), + .C0(C0), + .C1(C1), + .CE(CE), + .D(D[14]), + .R(R), + .S(S) +); +IDDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT_Q0(INIT_Q0), + .INIT_Q1(INIT_Q1), + .SRTYPE(SRTYPE) +) iddr15 ( + .Q0(Q0[15]), + .Q1(Q1[15]), + .C0(C0), + .C1(C1), + .CE(CE), + .D(D[15]), + .R(R), + .S(S) +); +IDDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT_Q0(INIT_Q0), + .INIT_Q1(INIT_Q1), + .SRTYPE(SRTYPE) +) iddr16 ( + .Q0(Q0[16]), + .Q1(Q1[16]), + .C0(C0), + .C1(C1), + .CE(CE), + .D(D[16]), + .R(R), + .S(S) +); +IDDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT_Q0(INIT_Q0), + .INIT_Q1(INIT_Q1), + .SRTYPE(SRTYPE) +) iddr17 ( + .Q0(Q0[17]), + .Q1(Q1[17]), + .C0(C0), + .C1(C1), + .CE(CE), + .D(D[17]), + .R(R), + .S(S) +); +IDDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT_Q0(INIT_Q0), + .INIT_Q1(INIT_Q1), + .SRTYPE(SRTYPE) +) iddr18 ( + .Q0(Q0[18]), + .Q1(Q1[18]), + .C0(C0), + .C1(C1), + .CE(CE), + .D(D[18]), + .R(R), + .S(S) +); +IDDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT_Q0(INIT_Q0), + .INIT_Q1(INIT_Q1), + .SRTYPE(SRTYPE) +) iddr19 ( + .Q0(Q0[19]), + .Q1(Q1[19]), + .C0(C0), + .C1(C1), + .CE(CE), + .D(D[19]), + .R(R), + .S(S) +); +IDDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT_Q0(INIT_Q0), + .INIT_Q1(INIT_Q1), + .SRTYPE(SRTYPE) +) iddr20 ( + .Q0(Q0[20]), + .Q1(Q1[20]), + .C0(C0), + .C1(C1), + .CE(CE), + .D(D[20]), + .R(R), + .S(S) +); +IDDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT_Q0(INIT_Q0), + .INIT_Q1(INIT_Q1), + .SRTYPE(SRTYPE) +) iddr21 ( + .Q0(Q0[21]), + .Q1(Q1[21]), + .C0(C0), + .C1(C1), + .CE(CE), + .D(D[21]), + .R(R), + .S(S) +); +IDDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT_Q0(INIT_Q0), + .INIT_Q1(INIT_Q1), + .SRTYPE(SRTYPE) +) iddr22 ( + .Q0(Q0[22]), + .Q1(Q1[22]), + .C0(C0), + .C1(C1), + .CE(CE), + .D(D[22]), + .R(R), + .S(S) +); +IDDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT_Q0(INIT_Q0), + .INIT_Q1(INIT_Q1), + .SRTYPE(SRTYPE) +) iddr23 ( + .Q0(Q0[23]), + .Q1(Q1[23]), + .C0(C0), + .C1(C1), + .CE(CE), + .D(D[23]), + .R(R), + .S(S) +); +IDDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT_Q0(INIT_Q0), + .INIT_Q1(INIT_Q1), + .SRTYPE(SRTYPE) +) iddr24 ( + .Q0(Q0[24]), + .Q1(Q1[24]), + .C0(C0), + .C1(C1), + .CE(CE), + .D(D[24]), + .R(R), + .S(S) +); +IDDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT_Q0(INIT_Q0), + .INIT_Q1(INIT_Q1), + .SRTYPE(SRTYPE) +) iddr25 ( + .Q0(Q0[25]), + .Q1(Q1[25]), + .C0(C0), + .C1(C1), + .CE(CE), + .D(D[25]), + .R(R), + .S(S) +); +IDDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT_Q0(INIT_Q0), + .INIT_Q1(INIT_Q1), + .SRTYPE(SRTYPE) +) iddr26 ( + .Q0(Q0[26]), + .Q1(Q1[26]), + .C0(C0), + .C1(C1), + .CE(CE), + .D(D[26]), + .R(R), + .S(S) +); +IDDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT_Q0(INIT_Q0), + .INIT_Q1(INIT_Q1), + .SRTYPE(SRTYPE) +) iddr27 ( + .Q0(Q0[27]), + .Q1(Q1[27]), + .C0(C0), + .C1(C1), + .CE(CE), + .D(D[27]), + .R(R), + .S(S) +); +IDDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT_Q0(INIT_Q0), + .INIT_Q1(INIT_Q1), + .SRTYPE(SRTYPE) +) iddr28 ( + .Q0(Q0[28]), + .Q1(Q1[28]), + .C0(C0), + .C1(C1), + .CE(CE), + .D(D[28]), + .R(R), + .S(S) +); +IDDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT_Q0(INIT_Q0), + .INIT_Q1(INIT_Q1), + .SRTYPE(SRTYPE) +) iddr29 ( + .Q0(Q0[29]), + .Q1(Q1[29]), + .C0(C0), + .C1(C1), + .CE(CE), + .D(D[29]), + .R(R), + .S(S) +); +IDDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT_Q0(INIT_Q0), + .INIT_Q1(INIT_Q1), + .SRTYPE(SRTYPE) +) iddr30 ( + .Q0(Q0[30]), + .Q1(Q1[30]), + .C0(C0), + .C1(C1), + .CE(CE), + .D(D[30]), + .R(R), + .S(S) +); +IDDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT_Q0(INIT_Q0), + .INIT_Q1(INIT_Q1), + .SRTYPE(SRTYPE) +) iddr31 ( + .Q0(Q0[31]), + .Q1(Q1[31]), + .C0(C0), + .C1(C1), + .CE(CE), + .D(D[31]), + .R(R), + .S(S) +); + +endmodule diff --git a/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/spartan6/hpdmc_iobuf32.v b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/spartan6/hpdmc_iobuf32.v new file mode 100644 index 0000000..5bab43b --- /dev/null +++ b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/spartan6/hpdmc_iobuf32.v @@ -0,0 +1,225 @@ +/* + * Milkymist VJ SoC + * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 3 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* + * Verilog code that really should be replaced with a generate + * statement, but it does not work with some free simulators. + * So I put it in a module so as not to make other code unreadable, + * and keep compatibility with as many simulators as possible. + */ + +module hpdmc_iobuf32( + input [31:0] T, + input [31:0] I, + output [31:0] O, + inout [31:0] IO +); + +IOBUF iobuf0( + .T(T[0]), + .I(I[0]), + .O(O[0]), + .IO(IO[0]) +); +IOBUF iobuf1( + .T(T[1]), + .I(I[1]), + .O(O[1]), + .IO(IO[1]) +); +IOBUF iobuf2( + .T(T[2]), + .I(I[2]), + .O(O[2]), + .IO(IO[2]) +); +IOBUF iobuf3( + .T(T[3]), + .I(I[3]), + .O(O[3]), + .IO(IO[3]) +); +IOBUF iobuf4( + .T(T[4]), + .I(I[4]), + .O(O[4]), + .IO(IO[4]) +); +IOBUF iobuf5( + .T(T[5]), + .I(I[5]), + .O(O[5]), + .IO(IO[5]) +); +IOBUF iobuf6( + .T(T[6]), + .I(I[6]), + .O(O[6]), + .IO(IO[6]) +); +IOBUF iobuf7( + .T(T[7]), + .I(I[7]), + .O(O[7]), + .IO(IO[7]) +); +IOBUF iobuf8( + .T(T[8]), + .I(I[8]), + .O(O[8]), + .IO(IO[8]) +); +IOBUF iobuf9( + .T(T[9]), + .I(I[9]), + .O(O[9]), + .IO(IO[9]) +); +IOBUF iobuf10( + .T(T[10]), + .I(I[10]), + .O(O[10]), + .IO(IO[10]) +); +IOBUF iobuf11( + .T(T[11]), + .I(I[11]), + .O(O[11]), + .IO(IO[11]) +); +IOBUF iobuf12( + .T(T[12]), + .I(I[12]), + .O(O[12]), + .IO(IO[12]) +); +IOBUF iobuf13( + .T(T[13]), + .I(I[13]), + .O(O[13]), + .IO(IO[13]) +); +IOBUF iobuf14( + .T(T[14]), + .I(I[14]), + .O(O[14]), + .IO(IO[14]) +); +IOBUF iobuf15( + .T(T[15]), + .I(I[15]), + .O(O[15]), + .IO(IO[15]) +); +IOBUF iobuf16( + .T(T[16]), + .I(I[16]), + .O(O[16]), + .IO(IO[16]) +); +IOBUF iobuf17( + .T(T[17]), + .I(I[17]), + .O(O[17]), + .IO(IO[17]) +); +IOBUF iobuf18( + .T(T[18]), + .I(I[18]), + .O(O[18]), + .IO(IO[18]) +); +IOBUF iobuf19( + .T(T[19]), + .I(I[19]), + .O(O[19]), + .IO(IO[19]) +); +IOBUF iobuf20( + .T(T[20]), + .I(I[20]), + .O(O[20]), + .IO(IO[20]) +); +IOBUF iobuf21( + .T(T[21]), + .I(I[21]), + .O(O[21]), + .IO(IO[21]) +); +IOBUF iobuf22( + .T(T[22]), + .I(I[22]), + .O(O[22]), + .IO(IO[22]) +); +IOBUF iobuf23( + .T(T[23]), + .I(I[23]), + .O(O[23]), + .IO(IO[23]) +); +IOBUF iobuf24( + .T(T[24]), + .I(I[24]), + .O(O[24]), + .IO(IO[24]) +); +IOBUF iobuf25( + .T(T[25]), + .I(I[25]), + .O(O[25]), + .IO(IO[25]) +); +IOBUF iobuf26( + .T(T[26]), + .I(I[26]), + .O(O[26]), + .IO(IO[26]) +); +IOBUF iobuf27( + .T(T[27]), + .I(I[27]), + .O(O[27]), + .IO(IO[27]) +); +IOBUF iobuf28( + .T(T[28]), + .I(I[28]), + .O(O[28]), + .IO(IO[28]) +); +IOBUF iobuf29( + .T(T[29]), + .I(I[29]), + .O(O[29]), + .IO(IO[29]) +); +IOBUF iobuf30( + .T(T[30]), + .I(I[30]), + .O(O[30]), + .IO(IO[30]) +); +IOBUF iobuf31( + .T(T[31]), + .I(I[31]), + .O(O[31]), + .IO(IO[31]) +); + +endmodule diff --git a/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/spartan6/hpdmc_obuft4.v b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/spartan6/hpdmc_obuft4.v new file mode 100644 index 0000000..f196ce7 --- /dev/null +++ b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/spartan6/hpdmc_obuft4.v @@ -0,0 +1,52 @@ +/* + * Milkymist VJ SoC + * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 3 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* + * Verilog code that really should be replaced with a generate + * statement, but it does not work with some free simulators. + * So I put it in a module so as not to make other code unreadable, + * and keep compatibility with as many simulators as possible. + */ + +module hpdmc_obuft4( + input [3:0] T, + input [3:0] I, + output [3:0] O +); + +OBUFT obuft0( + .T(T[0]), + .I(I[0]), + .O(O[0]) +); +OBUFT obuft1( + .T(T[1]), + .I(I[1]), + .O(O[1]) +); +OBUFT obuft2( + .T(T[2]), + .I(I[2]), + .O(O[2]) +); +OBUFT obuft3( + .T(T[3]), + .I(I[3]), + .O(O[3]) +); + +endmodule diff --git a/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/spartan6/hpdmc_oddr32.v b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/spartan6/hpdmc_oddr32.v new file mode 100644 index 0000000..cf5011e --- /dev/null +++ b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/spartan6/hpdmc_oddr32.v @@ -0,0 +1,489 @@ +/* + * Milkymist VJ SoC + * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 3 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* + * Verilog code that really should be replaced with a generate + * statement, but it does not work with some free simulators. + * So I put it in a module so as not to make other code unreadable, + * and keep compatibility with as many simulators as possible. + */ + +module hpdmc_oddr32 #( + parameter DDR_ALIGNMENT = "C0", + parameter INIT = 1'b0, + parameter SRTYPE = "ASYNC" +) ( + output [31:0] Q, + input C0, + input C1, + input CE, + input [31:0] D0, + input [31:0] D1, + input R, + input S +); + +ODDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT(INIT), + .SRTYPE(SRTYPE) +) oddr0 ( + .Q(Q[0]), + .C0(C0), + .C1(C1), + .CE(CE), + .D0(D0[0]), + .D1(D1[0]), + .R(R), + .S(S) +); +ODDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT(INIT), + .SRTYPE(SRTYPE) +) oddr1 ( + .Q(Q[1]), + .C0(C0), + .C1(C1), + .CE(CE), + .D0(D0[1]), + .D1(D1[1]), + .R(R), + .S(S) +); +ODDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT(INIT), + .SRTYPE(SRTYPE) +) oddr2 ( + .Q(Q[2]), + .C0(C0), + .C1(C1), + .CE(CE), + .D0(D0[2]), + .D1(D1[2]), + .R(R), + .S(S) +); +ODDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT(INIT), + .SRTYPE(SRTYPE) +) oddr3 ( + .Q(Q[3]), + .C0(C0), + .C1(C1), + .CE(CE), + .D0(D0[3]), + .D1(D1[3]), + .R(R), + .S(S) +); +ODDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT(INIT), + .SRTYPE(SRTYPE) +) oddr4 ( + .Q(Q[4]), + .C0(C0), + .C1(C1), + .CE(CE), + .D0(D0[4]), + .D1(D1[4]), + .R(R), + .S(S) +); +ODDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT(INIT), + .SRTYPE(SRTYPE) +) oddr5 ( + .Q(Q[5]), + .C0(C0), + .C1(C1), + .CE(CE), + .D0(D0[5]), + .D1(D1[5]), + .R(R), + .S(S) +); +ODDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT(INIT), + .SRTYPE(SRTYPE) +) oddr6 ( + .Q(Q[6]), + .C0(C0), + .C1(C1), + .CE(CE), + .D0(D0[6]), + .D1(D1[6]), + .R(R), + .S(S) +); +ODDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT(INIT), + .SRTYPE(SRTYPE) +) oddr7 ( + .Q(Q[7]), + .C0(C0), + .C1(C1), + .CE(CE), + .D0(D0[7]), + .D1(D1[7]), + .R(R), + .S(S) +); +ODDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT(INIT), + .SRTYPE(SRTYPE) +) oddr8 ( + .Q(Q[8]), + .C0(C0), + .C1(C1), + .CE(CE), + .D0(D0[8]), + .D1(D1[8]), + .R(R), + .S(S) +); +ODDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT(INIT), + .SRTYPE(SRTYPE) +) oddr9 ( + .Q(Q[9]), + .C0(C0), + .C1(C1), + .CE(CE), + .D0(D0[9]), + .D1(D1[9]), + .R(R), + .S(S) +); +ODDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT(INIT), + .SRTYPE(SRTYPE) +) oddr10 ( + .Q(Q[10]), + .C0(C0), + .C1(C1), + .CE(CE), + .D0(D0[10]), + .D1(D1[10]), + .R(R), + .S(S) +); +ODDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT(INIT), + .SRTYPE(SRTYPE) +) oddr11 ( + .Q(Q[11]), + .C0(C0), + .C1(C1), + .CE(CE), + .D0(D0[11]), + .D1(D1[11]), + .R(R), + .S(S) +); +ODDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT(INIT), + .SRTYPE(SRTYPE) +) oddr12 ( + .Q(Q[12]), + .C0(C0), + .C1(C1), + .CE(CE), + .D0(D0[12]), + .D1(D1[12]), + .R(R), + .S(S) +); +ODDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT(INIT), + .SRTYPE(SRTYPE) +) oddr13 ( + .Q(Q[13]), + .C0(C0), + .C1(C1), + .CE(CE), + .D0(D0[13]), + .D1(D1[13]), + .R(R), + .S(S) +); +ODDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT(INIT), + .SRTYPE(SRTYPE) +) oddr14 ( + .Q(Q[14]), + .C0(C0), + .C1(C1), + .CE(CE), + .D0(D0[14]), + .D1(D1[14]), + .R(R), + .S(S) +); +ODDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT(INIT), + .SRTYPE(SRTYPE) +) oddr15 ( + .Q(Q[15]), + .C0(C0), + .C1(C1), + .CE(CE), + .D0(D0[15]), + .D1(D1[15]), + .R(R), + .S(S) +); +ODDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT(INIT), + .SRTYPE(SRTYPE) +) oddr16 ( + .Q(Q[16]), + .C0(C0), + .C1(C1), + .CE(CE), + .D0(D0[16]), + .D1(D1[16]), + .R(R), + .S(S) +); +ODDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT(INIT), + .SRTYPE(SRTYPE) +) oddr17 ( + .Q(Q[17]), + .C0(C0), + .C1(C1), + .CE(CE), + .D0(D0[17]), + .D1(D1[17]), + .R(R), + .S(S) +); +ODDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT(INIT), + .SRTYPE(SRTYPE) +) oddr18 ( + .Q(Q[18]), + .C0(C0), + .C1(C1), + .CE(CE), + .D0(D0[18]), + .D1(D1[18]), + .R(R), + .S(S) +); +ODDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT(INIT), + .SRTYPE(SRTYPE) +) oddr19 ( + .Q(Q[19]), + .C0(C0), + .C1(C1), + .CE(CE), + .D0(D0[19]), + .D1(D1[19]), + .R(R), + .S(S) +); +ODDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT(INIT), + .SRTYPE(SRTYPE) +) oddr20 ( + .Q(Q[20]), + .C0(C0), + .C1(C1), + .CE(CE), + .D0(D0[20]), + .D1(D1[20]), + .R(R), + .S(S) +); +ODDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT(INIT), + .SRTYPE(SRTYPE) +) oddr21 ( + .Q(Q[21]), + .C0(C0), + .C1(C1), + .CE(CE), + .D0(D0[21]), + .D1(D1[21]), + .R(R), + .S(S) +); +ODDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT(INIT), + .SRTYPE(SRTYPE) +) oddr22 ( + .Q(Q[22]), + .C0(C0), + .C1(C1), + .CE(CE), + .D0(D0[22]), + .D1(D1[22]), + .R(R), + .S(S) +); +ODDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT(INIT), + .SRTYPE(SRTYPE) +) oddr23 ( + .Q(Q[23]), + .C0(C0), + .C1(C1), + .CE(CE), + .D0(D0[23]), + .D1(D1[23]), + .R(R), + .S(S) +); +ODDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT(INIT), + .SRTYPE(SRTYPE) +) oddr24 ( + .Q(Q[24]), + .C0(C0), + .C1(C1), + .CE(CE), + .D0(D0[24]), + .D1(D1[24]), + .R(R), + .S(S) +); +ODDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT(INIT), + .SRTYPE(SRTYPE) +) oddr25 ( + .Q(Q[25]), + .C0(C0), + .C1(C1), + .CE(CE), + .D0(D0[25]), + .D1(D1[25]), + .R(R), + .S(S) +); +ODDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT(INIT), + .SRTYPE(SRTYPE) +) oddr26 ( + .Q(Q[26]), + .C0(C0), + .C1(C1), + .CE(CE), + .D0(D0[26]), + .D1(D1[26]), + .R(R), + .S(S) +); +ODDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT(INIT), + .SRTYPE(SRTYPE) +) oddr27 ( + .Q(Q[27]), + .C0(C0), + .C1(C1), + .CE(CE), + .D0(D0[27]), + .D1(D1[27]), + .R(R), + .S(S) +); +ODDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT(INIT), + .SRTYPE(SRTYPE) +) oddr28 ( + .Q(Q[28]), + .C0(C0), + .C1(C1), + .CE(CE), + .D0(D0[28]), + .D1(D1[28]), + .R(R), + .S(S) +); +ODDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT(INIT), + .SRTYPE(SRTYPE) +) oddr29 ( + .Q(Q[29]), + .C0(C0), + .C1(C1), + .CE(CE), + .D0(D0[29]), + .D1(D1[29]), + .R(R), + .S(S) +); +ODDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT(INIT), + .SRTYPE(SRTYPE) +) oddr30 ( + .Q(Q[30]), + .C0(C0), + .C1(C1), + .CE(CE), + .D0(D0[30]), + .D1(D1[30]), + .R(R), + .S(S) +); +ODDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT(INIT), + .SRTYPE(SRTYPE) +) oddr31 ( + .Q(Q[31]), + .C0(C0), + .C1(C1), + .CE(CE), + .D0(D0[31]), + .D1(D1[31]), + .R(R), + .S(S) +); + +endmodule diff --git a/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/spartan6/hpdmc_oddr4.v b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/spartan6/hpdmc_oddr4.v new file mode 100644 index 0000000..e84f0ee --- /dev/null +++ b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/rtl/spartan6/hpdmc_oddr4.v @@ -0,0 +1,97 @@ +/* + * Milkymist VJ SoC + * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 3 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* + * Verilog code that really should be replaced with a generate + * statement, but it does not work with some free simulators. + * So I put it in a module so as not to make other code unreadable, + * and keep compatibility with as many simulators as possible. + */ + +module hpdmc_oddr4 #( + parameter DDR_ALIGNMENT = "C0", + parameter INIT = 1'b0, + parameter SRTYPE = "ASYNC" +) ( + output [3:0] Q, + input C0, + input C1, + input CE, + input [3:0] D0, + input [3:0] D1, + input R, + input S +); + +ODDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT(INIT), + .SRTYPE(SRTYPE) +) oddr0 ( + .Q(Q[0]), + .C0(C0), + .C1(C1), + .CE(CE), + .D0(D0[0]), + .D1(D1[0]), + .R(R), + .S(S) +); +ODDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT(INIT), + .SRTYPE(SRTYPE) +) oddr1 ( + .Q(Q[1]), + .C0(C0), + .C1(C1), + .CE(CE), + .D0(D0[1]), + .D1(D1[1]), + .R(R), + .S(S) +); +ODDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT(INIT), + .SRTYPE(SRTYPE) +) oddr2 ( + .Q(Q[2]), + .C0(C0), + .C1(C1), + .CE(CE), + .D0(D0[2]), + .D1(D1[2]), + .R(R), + .S(S) +); +ODDR2 #( + .DDR_ALIGNMENT(DDR_ALIGNMENT), + .INIT(INIT), + .SRTYPE(SRTYPE) +) oddr3 ( + .Q(Q[3]), + .C0(C0), + .C1(C1), + .CE(CE), + .D0(D0[3]), + .D1(D1[3]), + .R(R), + .S(S) +); + +endmodule diff --git a/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/test/Makefile.spartan6 b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/test/Makefile.spartan6 new file mode 100644 index 0000000..356a0e7 --- /dev/null +++ b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/test/Makefile.spartan6 @@ -0,0 +1,3 @@ +SOURCES_HPDMC=tb_hpdmc.v ddr.v oddr2.v iddr2.v obuft.v iobuf.v $(wildcard ../rtl/*.v) $(wildcard ../rtl/spartan6/*.v) + +include common.mak diff --git a/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/test/common.mak b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/test/common.mak new file mode 100644 index 0000000..682372d --- /dev/null +++ b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/test/common.mak @@ -0,0 +1,14 @@ +SOURCES_MODEL=tb_model.v ddr.v + +all: hpdmc + +model: $(SOURCES_MODEL) + cver $(SOURCES_MODEL) + +hpdmc: $(SOURCES) + cver $(SOURCES_HPDMC) + +clean: + rm -f verilog.log hpdmc.vcd + +.PHONY: clean model hpdmc diff --git a/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/test/ddr.v b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/test/ddr.v new file mode 100644 index 0000000..6c1fd37 --- /dev/null +++ b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/test/ddr.v @@ -0,0 +1,1452 @@ +/**************************************************************************************** +* +* File Name: ddr.v +* Version: 6.00 +* Model: BUS Functional +* +* Dependencies: ddr_parameters.v +* +* Description: Micron SDRAM DDR (Double Data Rate) +* +* Limitation: - Doesn't check for 8K-cycle refresh. +* - Doesn't check power-down entry/exit +* - Doesn't check self-refresh entry/exit. +* +* Note: - Set simulator resolution to "ps" accuracy +* - Set DEBUG = 0 to disable $display messages +* - Model assume Clk and Clk# crossing at both edge +* +* Disclaimer This software code and all associated documentation, comments or other +* of Warranty: information (collectively "Software") is provided "AS IS" without +* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY +* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES +* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT +* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE +* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. +* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR +* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, +* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE +* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, +* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, +* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, +* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, +* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE +* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH +* DAMAGES. Because some jurisdictions prohibit the exclusion or +* limitation of liability for consequential or incidental damages, the +* above limitation may not apply to you. +* +* Copyright 2003 Micron Technology, Inc. All rights reserved. +* +* Rev Author Date Changes +* --- ------ ---------- --------------------------------------- +* 2.1 SPH 03/19/2002 - Second Release +* - Fix tWR and several incompatability +* between different simulators +* 3.0 TFK 02/18/2003 - Added tDSS and tDSH timing checks. +* - Added tDQSH and tDQSL timing checks. +* 3.1 CAH 05/28/2003 - update all models to release version 3.1 +* (no changes to this model) +* 3.2 JMK 06/16/2003 - updated all DDR400 models to support CAS Latency 3 +* 3.3 JMK 09/11/2003 - Added initialization sequence checks. +* 4.0 JMK 12/01/2003 - Grouped parameters into "ddr_parameters.v" +* - Fixed tWTR check +* 4.1 JMK 01/14/2004 - Grouped specify parameters by speed grade +* - Fixed mem_sizes parameter +* 4.2 JMK 03/19/2004 - Fixed pulse width checking on Dqs +* 4.3 JMK 04/27/2004 - Changed BL wire size in tb module +* - Changed Dq_buf size to [15:0] +* 5.0 JMK 06/16/2004 - Added read to write checking. +* - Added read with precharge truncation to write checking. +* - Added associative memory array to reduce memory consumption. +* - Added checking for required DQS edges during write. +* 5.1 JMK 08/16/2004 - Fixed checking for required DQS edges during write. +* - Fixed wdqs_valid window. +* 5.2 JMK 09/24/2004 - Read or Write without activate will be ignored. +* 5.3 JMK 10/27/2004 - Added tMRD checking during Auto Refresh and Activate. +* - Added tRFC checking during Load Mode and Precharge. +* 5.4 JMK 12/13/2004 - The model will not respond to illegal command sequences. +* 5.5 SPH 01/13/2005 - The model will issue a halt on illegal command sequences. +* JMK 02/11/2005 - Changed the display format for numbers to hex. +* 5.6 JMK 04/22/2005 - Fixed Write with auto precharge calculation. +* 5.7 JMK 08/05/2005 - Changed conditions for read with precharge truncation error. +* - Renamed parameters file with .vh extension. +* 5.8 BAS 12/26/2006 - Added parameters for T46A part - 256Mb +* - Added x32 functionality +* 6.00 JMK 05/31/2007 - Added ddr_184_dimm module model +* 6.00 BAS 05/31/2007 - Updated 128Mb, 256Mb, 512Mb, and 1024Mb parameter sheets +****************************************************************************************/ + +// DO NOT CHANGE THE TIMESCALE +// MAKE SURE YOUR SIMULATOR USE "PS" RESOLUTION +`timescale 1ns / 1ps + +module ddr (Clk, Clk_n, Cke, Cs_n, Ras_n, Cas_n, We_n, Ba , Addr, Dm, Dq, Dqs); + `include "ddr_parameters.vh" + + // Port Declarations + input Clk; + input Clk_n; + input Cke; + input Cs_n; + input Ras_n; + input Cas_n; + input We_n; + input [1 : 0] Ba; + input [ADDR_BITS - 1 : 0] Addr; + input [DM_BITS - 1 : 0] Dm; + inout [DQ_BITS - 1 : 0] Dq; + inout [DQS_BITS - 1 : 0] Dqs; + + // Internal Wires (fixed width) + wire [31 : 0] Dq_in; + wire [3 : 0] Dqs_in; + wire [3 : 0] Dm_in; + + assign Dq_in [DQ_BITS - 1 : 0] = Dq; + assign Dqs_in [DQS_BITS - 1 : 0] = Dqs; + assign Dm_in [DM_BITS - 1 : 0] = Dm; + + // Data pair + reg [31 : 0] dq_rise; + reg [3 : 0] dm_rise; + reg [31 : 0] dq_fall; + reg [3 : 0] dm_fall; + reg [7 : 0] dm_pair; + reg [31 : 0] Dq_buf; + + // Mode Register + reg [ADDR_BITS - 1 : 0] Mode_reg; + + // Internal System Clock + reg CkeZ, Sys_clk; + + // Internal Dqs initialize + reg Dqs_int; + + // Dqs buffer + reg [DQS_BITS - 1 : 0] Dqs_out; + + // Dq buffer + reg [DQ_BITS - 1 : 0] Dq_out; + + // Read pipeline variables + reg Read_cmnd [0 : 6]; + reg [1 : 0] Read_bank [0 : 6]; + reg [COL_BITS - 1 : 0] Read_cols [0 : 6]; + + // Write pipeline variables + reg Write_cmnd [0 : 3]; + reg [1 : 0] Write_bank [0 : 3]; + reg [COL_BITS - 1 : 0] Write_cols [0 : 3]; + + // Auto precharge variables + reg Read_precharge [0 : 3]; + reg Write_precharge [0 : 3]; + integer Count_precharge [0 : 3]; + + // Manual precharge variables + reg A10_precharge [0 : 6]; + reg [1 : 0] Bank_precharge [0 : 6]; + reg Cmnd_precharge [0 : 6]; + + // Burst terminate variables + reg Cmnd_bst [0 : 6]; + + // Memory Banks +`ifdef FULL_MEM + reg [DQ_BITS - 1 : 0] mem_array [0 : (1<= 2) begin + if (DEBUG) $display ("%m: at time %t MEMORY: Power Up and Initialization Sequence is complete", $time); + power_up_done = 1; + end else begin + aref_count = 0; + @ (aref_count >= 2) begin + if (DEBUG) $display ("%m: at time %t MEMORY: Power Up and Initialization Sequence is complete", $time); + power_up_done = 1; + end + end + end + end + end + end + end + + // Write Memory + task write_mem; + input [full_mem_bits - 1 : 0] addr; + input [DQ_BITS - 1 : 0] data; + reg [part_mem_bits : 0] i; + begin +`ifdef FULL_MEM + mem_array[addr] = data; +`else + begin : loop + for (i = 0; i < mem_used; i = i + 1) begin + if (addr_array[i] === addr) begin + disable loop; + end + end + end + if (i === mem_used) begin + if (i === (1<= burst_length) begin + Data_in_enable = 1'b0; + Data_out_enable = 1'b0; + read_precharge_truncation = 4'h0; + end + + end + endtask + + // Manual Precharge Pipeline + task Manual_Precharge_Pipeline; + begin + // A10 Precharge Pipeline + A10_precharge[0] = A10_precharge[1]; + A10_precharge[1] = A10_precharge[2]; + A10_precharge[2] = A10_precharge[3]; + A10_precharge[3] = A10_precharge[4]; + A10_precharge[4] = A10_precharge[5]; + A10_precharge[5] = A10_precharge[6]; + A10_precharge[6] = 1'b0; + + // Bank Precharge Pipeline + Bank_precharge[0] = Bank_precharge[1]; + Bank_precharge[1] = Bank_precharge[2]; + Bank_precharge[2] = Bank_precharge[3]; + Bank_precharge[3] = Bank_precharge[4]; + Bank_precharge[4] = Bank_precharge[5]; + Bank_precharge[5] = Bank_precharge[6]; + Bank_precharge[6] = 2'b0; + + // Command Precharge Pipeline + Cmnd_precharge[0] = Cmnd_precharge[1]; + Cmnd_precharge[1] = Cmnd_precharge[2]; + Cmnd_precharge[2] = Cmnd_precharge[3]; + Cmnd_precharge[3] = Cmnd_precharge[4]; + Cmnd_precharge[4] = Cmnd_precharge[5]; + Cmnd_precharge[5] = Cmnd_precharge[6]; + Cmnd_precharge[6] = 1'b0; + + // Terminate a Read if same bank or all banks + if (Cmnd_precharge[0] === 1'b1) begin + if (Bank_precharge[0] === Bank_addr || A10_precharge[0] === 1'b1) begin + if (Data_out_enable === 1'b1) begin + Data_out_enable = 1'b0; + read_precharge_truncation = 4'hF; + end + end + end + end + endtask + + // Burst Terminate Pipeline + task Burst_Terminate_Pipeline; + begin + // Command Precharge Pipeline + Cmnd_bst[0] = Cmnd_bst[1]; + Cmnd_bst[1] = Cmnd_bst[2]; + Cmnd_bst[2] = Cmnd_bst[3]; + Cmnd_bst[3] = Cmnd_bst[4]; + Cmnd_bst[4] = Cmnd_bst[5]; + Cmnd_bst[5] = Cmnd_bst[6]; + Cmnd_bst[6] = 1'b0; + + // Terminate a Read regardless of banks + if (Cmnd_bst[0] === 1'b1 && Data_out_enable === 1'b1) begin + Data_out_enable = 1'b0; + end + end + endtask + + // Dq and Dqs Drivers + task Dq_Dqs_Drivers; + begin + // read command pipeline + Read_cmnd [0] = Read_cmnd [1]; + Read_cmnd [1] = Read_cmnd [2]; + Read_cmnd [2] = Read_cmnd [3]; + Read_cmnd [3] = Read_cmnd [4]; + Read_cmnd [4] = Read_cmnd [5]; + Read_cmnd [5] = Read_cmnd [6]; + Read_cmnd [6] = 1'b0; + + // read bank pipeline + Read_bank [0] = Read_bank [1]; + Read_bank [1] = Read_bank [2]; + Read_bank [2] = Read_bank [3]; + Read_bank [3] = Read_bank [4]; + Read_bank [4] = Read_bank [5]; + Read_bank [5] = Read_bank [6]; + Read_bank [6] = 2'b0; + + // read column pipeline + Read_cols [0] = Read_cols [1]; + Read_cols [1] = Read_cols [2]; + Read_cols [2] = Read_cols [3]; + Read_cols [3] = Read_cols [4]; + Read_cols [4] = Read_cols [5]; + Read_cols [5] = Read_cols [6]; + Read_cols [6] = 0; + + // Initialize Read command + if (Read_cmnd [0] === 1'b1) begin + Data_out_enable = 1'b1; + Bank_addr = Read_bank [0]; + Cols_addr = Read_cols [0]; + Cols_brst = Cols_addr [2 : 0]; + Burst_counter = 0; + + // Row Address Mux + case (Bank_addr) + 2'd0 : Rows_addr = B0_row_addr; + 2'd1 : Rows_addr = B1_row_addr; + 2'd2 : Rows_addr = B2_row_addr; + 2'd3 : Rows_addr = B3_row_addr; + default : $display ("%m: At time %t ERROR: Invalid Bank Address", $time); + endcase + end + + // Toggle Dqs during Read command + if (Data_out_enable === 1'b1) begin + Dqs_int = 1'b0; + if (Dqs_out === {DQS_BITS{1'b0}}) begin + Dqs_out = {DQS_BITS{1'b1}}; + end else if (Dqs_out === {DQS_BITS{1'b1}}) begin + Dqs_out = {DQS_BITS{1'b0}}; + end else begin + Dqs_out = {DQS_BITS{1'b0}}; + end + end else if (Data_out_enable === 1'b0 && Dqs_int === 1'b0) begin + Dqs_out = {DQS_BITS{1'bz}}; + end + + // Initialize dqs for Read command + if (Read_cmnd [2] === 1'b1) begin + if (Data_out_enable === 1'b0) begin + Dqs_int = 1'b1; + Dqs_out = {DQS_BITS{1'b0}}; + end + end + + // Read latch + if (Data_out_enable === 1'b1) begin + // output data + read_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_out); + if (DEBUG) begin + $display ("%m: At time %t READ : Bank = %h, Row = %h, Col = %h, Data = %h", $time, Bank_addr, Rows_addr, Cols_addr, Dq_out); + end + end else begin + Dq_out = {DQ_BITS{1'bz}}; + end + end + endtask + + // Write FIFO and DM Mask Logic + task Write_FIFO_DM_Mask_Logic; + begin + // Write command pipeline + Write_cmnd [0] = Write_cmnd [1]; + Write_cmnd [1] = Write_cmnd [2]; + Write_cmnd [2] = Write_cmnd [3]; + Write_cmnd [3] = 1'b0; + + // Write command pipeline + Write_bank [0] = Write_bank [1]; + Write_bank [1] = Write_bank [2]; + Write_bank [2] = Write_bank [3]; + Write_bank [3] = 2'b0; + + // Write column pipeline + Write_cols [0] = Write_cols [1]; + Write_cols [1] = Write_cols [2]; + Write_cols [2] = Write_cols [3]; + Write_cols [3] = {COL_BITS{1'b0}}; + + // Initialize Write command + if (Write_cmnd [0] === 1'b1) begin + Data_in_enable = 1'b1; + Bank_addr = Write_bank [0]; + Cols_addr = Write_cols [0]; + Cols_brst = Cols_addr [2 : 0]; + Burst_counter = 0; + + // Row address mux + case (Bank_addr) + 2'd0 : Rows_addr = B0_row_addr; + 2'd1 : Rows_addr = B1_row_addr; + 2'd2 : Rows_addr = B2_row_addr; + 2'd3 : Rows_addr = B3_row_addr; + default : $display ("%m: At time %t ERROR: Invalid Row Address", $time); + endcase + end + + // Write data + if (Data_in_enable === 1'b1) begin + + // Data Buffer + read_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_buf); + + // write negedge Dqs on posedge Sys_clk + if (Sys_clk) begin + if (!dm_fall[0]) begin + Dq_buf [ 7 : 0] = dq_fall [ 7 : 0]; + end + if (!dm_fall[1]) begin + Dq_buf [15 : 8] = dq_fall [15 : 8]; + end + if (!dm_fall[2]) begin + Dq_buf [23 : 16] = dq_fall [23 : 16]; + end + if (!dm_fall[3]) begin + Dq_buf [31 : 24] = dq_fall [31 : 24]; + end + if (~&dm_fall) begin + if (DEBUG) begin + $display ("%m: At time %t WRITE: Bank = %h, Row = %h, Col = %h, Data = %h", $time, Bank_addr, Rows_addr, Cols_addr, Dq_buf[DQ_BITS-1:0]); + end + end + // write posedge Dqs on negedge Sys_clk + end else begin + if (!dm_rise[0]) begin + Dq_buf [ 7 : 0] = dq_rise [ 7 : 0]; + end + if (!dm_rise[1]) begin + Dq_buf [15 : 8] = dq_rise [15 : 8]; + end + if (!dm_rise[2]) begin + Dq_buf [23 : 16] = dq_rise [23 : 16]; + end + if (!dm_rise[3]) begin + Dq_buf [31 : 24] = dq_rise [31 : 24]; + end + if (~&dm_rise) begin + if (DEBUG) begin + $display ("%m: At time %t WRITE: Bank = %h, Row = %h, Col = %h, Data = %h", $time, Bank_addr, Rows_addr, Cols_addr, Dq_buf[DQ_BITS-1:0]); + end + end + end + + // Write Data + write_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_buf); + + // tWR start and tWTR check + if (Sys_clk && &dm_pair === 1'b0) begin + case (Bank_addr) + 2'd0 : WR_chk0 = $time; + 2'd1 : WR_chk1 = $time; + 2'd2 : WR_chk2 = $time; + 2'd3 : WR_chk3 = $time; + default : $display ("%m: At time %t ERROR: Invalid Bank Address (tWR)", $time); + endcase + + // tWTR check + if (Read_enable === 1'b1) begin + $display ("%m: At time %t ERROR: tWTR violation during Read", $time); + end + end + end + end + endtask + + // Auto Precharge Calculation + task Auto_Precharge_Calculation; + begin + // Precharge counter + if (Read_precharge [0] === 1'b1 || Write_precharge [0] === 1'b1) begin + Count_precharge [0] = Count_precharge [0] + 1; + end + if (Read_precharge [1] === 1'b1 || Write_precharge [1] === 1'b1) begin + Count_precharge [1] = Count_precharge [1] + 1; + end + if (Read_precharge [2] === 1'b1 || Write_precharge [2] === 1'b1) begin + Count_precharge [2] = Count_precharge [2] + 1; + end + if (Read_precharge [3] === 1'b1 || Write_precharge [3] === 1'b1) begin + Count_precharge [3] = Count_precharge [3] + 1; + end + + // Read with AutoPrecharge Calculation + // The device start internal precharge when: + // 1. Meet tRAS requirement + // 2. BL/2 cycles after command + if ((Read_precharge[0] === 1'b1) && ($time - RAS_chk0 >= tRAS)) begin + if (Count_precharge[0] >= burst_length/2) begin + Pc_b0 = 1'b1; + Act_b0 = 1'b0; + RP_chk0 = $time; + Read_precharge[0] = 1'b0; + end + end + if ((Read_precharge[1] === 1'b1) && ($time - RAS_chk1 >= tRAS)) begin + if (Count_precharge[1] >= burst_length/2) begin + Pc_b1 = 1'b1; + Act_b1 = 1'b0; + RP_chk1 = $time; + Read_precharge[1] = 1'b0; + end + end + if ((Read_precharge[2] === 1'b1) && ($time - RAS_chk2 >= tRAS)) begin + if (Count_precharge[2] >= burst_length/2) begin + Pc_b2 = 1'b1; + Act_b2 = 1'b0; + RP_chk2 = $time; + Read_precharge[2] = 1'b0; + end + end + if ((Read_precharge[3] === 1'b1) && ($time - RAS_chk3 >= tRAS)) begin + if (Count_precharge[3] >= burst_length/2) begin + Pc_b3 = 1'b1; + Act_b3 = 1'b0; + RP_chk3 = $time; + Read_precharge[3] = 1'b0; + end + end + + // Write with AutoPrecharge Calculation + // The device start internal precharge when: + // 1. Meet tRAS requirement + // 2. Write Latency PLUS BL/2 cycles PLUS tWR after Write command + + if ((Write_precharge[0] === 1'b1) && ($time - RAS_chk0 >= tRAS)) begin + if ((Count_precharge[0] >= burst_length/2+1) && ($time - WR_chk0 >= tWR)) begin + Pc_b0 = 1'b1; + Act_b0 = 1'b0; + RP_chk0 = $time; + Write_precharge[0] = 1'b0; + end + end + if ((Write_precharge[1] === 1'b1) && ($time - RAS_chk1 >= tRAS)) begin + if ((Count_precharge[1] >= burst_length/2+1) && ($time - WR_chk1 >= tWR)) begin + Pc_b1 = 1'b1; + Act_b1 = 1'b0; + RP_chk1 = $time; + Write_precharge[1] = 1'b0; + end + end + if ((Write_precharge[2] === 1'b1) && ($time - RAS_chk2 >= tRAS)) begin + if ((Count_precharge[2] >= burst_length/2+1) && ($time - WR_chk2 >= tWR)) begin + Pc_b2 = 1'b1; + Act_b2 = 1'b0; + RP_chk2 = $time; + Write_precharge[2] = 1'b0; + end + end + if ((Write_precharge[3] === 1'b1) && ($time - RAS_chk3 >= tRAS)) begin + if ((Count_precharge[3] >= burst_length/2+1) && ($time - WR_chk3 >= tWR)) begin + Pc_b3 = 1'b1; + Act_b3 = 1'b0; + RP_chk3 = $time; + Write_precharge[3] = 1'b0; + end + end + end + endtask + + // DLL Counter + task DLL_Counter; + begin + if (DLL_reset === 1'b1 && DLL_done === 1'b0) begin + DLL_count = DLL_count + 1; + if (DLL_count >= 200) begin + DLL_done = 1'b1; + end + end + end + endtask + + // Control Logic + task Control_Logic; + begin + // Auto Refresh + if (Aref_enable === 1'b1) begin + // Display DEBUG Message + if (DEBUG) begin + $display ("%m: At time %t AREF : Auto Refresh", $time); + end + + // Precharge to Auto Refresh + if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) || + ($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin + $display ("%m: At time %t ERROR: tRP violation during Auto Refresh", $time); + end + + // LMR/EMR to Auto Refresh + if ($time - MRD_chk < tMRD) begin + $display ("%m: At time %t ERROR: tMRD violation during Auto Refresh", $time); + end + + // Auto Refresh to Auto Refresh + if ($time - RFC_chk < tRFC) begin + $display ("%m: At time %t ERROR: tRFC violation during Auto Refresh", $time); + end + + // Precharge to Auto Refresh + if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin + $display ("%m: At time %t ERROR: All banks must be Precharged before Auto Refresh", $time); + if (!no_halt) $stop (0); + end else begin + aref_count = aref_count + 1; + RFC_chk = $time; + end + end + + // Extended Mode Register + if (Ext_mode_enable === 1'b1) begin + if (DEBUG) begin + $display ("%m: At time %t EMR : Extended Mode Register", $time); + end + + // Precharge to LMR/EMR + if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) || + ($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin + $display ("%m: At time %t ERROR: tRP violation during Extended Mode Register", $time); + end + + // LMR/EMR to LMR/EMR + if ($time - MRD_chk < tMRD) begin + $display ("%m: At time %t ERROR: tMRD violation during Extended Mode Register", $time); + end + + // Auto Refresh to LMR/EMR + if ($time - RFC_chk < tRFC) begin + $display ("%m: At time %t ERROR: tRFC violation during Extended Mode Register", $time); + end + + // Precharge to LMR/EMR + if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin + $display ("%m: At time %t ERROR: all banks must be Precharged before Extended Mode Register", $time); + if (!no_halt) $stop (0); + end else begin + if (Addr[0] === 1'b0) begin + DLL_enable = 1'b1; + if (DEBUG) begin + $display ("%m: At time %t EMR : Enable DLL", $time); + end + end else begin + DLL_enable = 1'b0; + if (DEBUG) begin + $display ("%m: At time %t EMR : Disable DLL", $time); + end + end + MRD_chk = $time; + end + end + + // Load Mode Register + if (Mode_reg_enable === 1'b1) begin + if (DEBUG) begin + $display ("%m: At time %t LMR : Load Mode Register", $time); + end + + // Precharge to LMR/EMR + if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) || + ($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin + $display ("%m: At time %t ERROR: tRP violation during Load Mode Register", $time); + end + + // LMR/EMR to LMR/EMR + if ($time - MRD_chk < tMRD) begin + $display ("%m: At time %t ERROR: tMRD violation during Load Mode Register", $time); + end + + // Auto Refresh to LMR/EMR + if ($time - RFC_chk < tRFC) begin + $display ("%m: At time %t ERROR: tRFC violation during Load Mode Register", $time); + end + + // Precharge to LMR/EMR + if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin + $display ("%m: At time %t ERROR: all banks must be Precharged before Load Mode Register", $time); + end else begin + // Register Mode + Mode_reg = Addr; + + // DLL Reset + if (DLL_enable === 1'b1 && Addr [8] === 1'b1) begin + DLL_reset = 1'b1; + DLL_done = 1'b0; + DLL_count = 0; + end else if (DLL_enable === 1'b1 && DLL_reset === 1'b0 && Addr [8] === 1'b0) begin + $display ("%m: At time %t ERROR: DLL is ENABLE: DLL RESET is required.", $time); + end else if (DLL_enable === 1'b0 && Addr [8] === 1'b1) begin + $display ("%m: At time %t ERROR: DLL is DISABLE: DLL RESET will be ignored.", $time); + end + + // Burst Length + case (Addr [2 : 0]) + 3'b001 : $display ("%m: At time %t LMR : Burst Length = 2", $time); + 3'b010 : $display ("%m: At time %t LMR : Burst Length = 4", $time); + 3'b011 : $display ("%m: At time %t LMR : Burst Length = 8", $time); + default : $display ("%m: At time %t ERROR: Burst Length not supported", $time); + endcase + + // CAS Latency + case (Addr [6 : 4]) + 3'b010 : $display ("%m: At time %t LMR : CAS Latency = 2", $time); + 3'b110 : $display ("%m: At time %t LMR : CAS Latency = 2.5", $time); + 3'b011 : $display ("%m: At time %t LMR : CAS Latency = 3", $time); + default : $display ("%m: At time %t ERROR: CAS Latency not supported", $time); + endcase + + // Record current tMRD time + MRD_chk = $time; + end + end + + // Activate Block + if (Active_enable === 1'b1) begin + if (!(power_up_done)) begin + $display ("%m: %m: at time %t ERROR: Power Up and Initialization Sequence not completed before executing Activate command", $time); + end + // Display DEBUG Message + if (DEBUG) begin + $display ("%m: At time %t ACT : Bank = %h, Row = %h", $time, Ba, Addr); + end + + // Activate to Activate (different bank) + if ((Prev_bank != Ba) && ($time - RRD_chk < tRRD)) begin + $display ("%m: At time %t ERROR: tRRD violation during Activate bank %h", $time, Ba); + end + + // LMR/EMR to Activate + if ($time - MRD_chk < tMRD) begin + $display ("%m: At time %t ERROR: tMRD violation during Activate bank %h", $time, Ba); + end + + // AutoRefresh to Activate + if ($time - RFC_chk < tRFC) begin + $display ("%m: At time %t ERROR: tRFC violation during Activate bank %h", $time, Ba); + end + + // Precharge to Activate + if ((Ba === 2'b00 && Pc_b0 === 1'b0) || (Ba === 2'b01 && Pc_b1 === 1'b0) || + (Ba === 2'b10 && Pc_b2 === 1'b0) || (Ba === 2'b11 && Pc_b3 === 1'b0)) begin + $display ("%m: At time %t ERROR: Bank = %h is already activated - Command Ignored", $time, Ba); + if (!no_halt) $stop (0); + end else begin + // Activate Bank 0 + if (Ba === 2'b00 && Pc_b0 === 1'b1) begin + // Activate to Activate (same bank) + if ($time - RC_chk0 < tRC) begin + $display ("%m: At time %t ERROR: tRC violation during Activate bank %h", $time, Ba); + end + + // Precharge to Activate + if ($time - RP_chk0 < tRP) begin + $display ("%m: At time %t ERROR: tRP violation during Activate bank %h", $time, Ba); + end + + // Record variables for checking violation + Act_b0 = 1'b1; + Pc_b0 = 1'b0; + B0_row_addr = Addr; + RC_chk0 = $time; + RCD_chk0 = $time; + RAS_chk0 = $time; + RAP_chk0 = $time; + end + + // Activate Bank 1 + if (Ba === 2'b01 && Pc_b1 === 1'b1) begin + // Activate to Activate (same bank) + if ($time - RC_chk1 < tRC) begin + $display ("%m: At time %t ERROR: tRC violation during Activate bank %h", $time, Ba); + end + + // Precharge to Activate + if ($time - RP_chk1 < tRP) begin + $display ("%m: At time %t ERROR: tRP violation during Activate bank %h", $time, Ba); + end + + // Record variables for checking violation + Act_b1 = 1'b1; + Pc_b1 = 1'b0; + B1_row_addr = Addr; + RC_chk1 = $time; + RCD_chk1 = $time; + RAS_chk1 = $time; + RAP_chk1 = $time; + end + + // Activate Bank 2 + if (Ba === 2'b10 && Pc_b2 === 1'b1) begin + // Activate to Activate (same bank) + if ($time - RC_chk2 < tRC) begin + $display ("%m: At time %t ERROR: tRC violation during Activate bank %h", $time, Ba); + end + + // Precharge to Activate + if ($time - RP_chk2 < tRP) begin + $display ("%m: At time %t ERROR: tRP violation during Activate bank %h", $time, Ba); + end + + // Record variables for checking violation + Act_b2 = 1'b1; + Pc_b2 = 1'b0; + B2_row_addr = Addr; + RC_chk2 = $time; + RCD_chk2 = $time; + RAS_chk2 = $time; + RAP_chk2 = $time; + end + + // Activate Bank 3 + if (Ba === 2'b11 && Pc_b3 === 1'b1) begin + // Activate to Activate (same bank) + if ($time - RC_chk3 < tRC) begin + $display ("%m: At time %t ERROR: tRC violation during Activate bank %h", $time, Ba); + end + + // Precharge to Activate + if ($time - RP_chk3 < tRP) begin + $display ("%m: At time %t ERROR: tRP violation during Activate bank %h", $time, Ba); + end + + // Record variables for checking violation + Act_b3 = 1'b1; + Pc_b3 = 1'b0; + B3_row_addr = Addr; + RC_chk3 = $time; + RCD_chk3 = $time; + RAS_chk3 = $time; + RAP_chk3 = $time; + end + // Record variable for checking violation + RRD_chk = $time; + Prev_bank = Ba; + read_precharge_truncation[Ba] = 1'b0; + end + end + + // Precharge Block - consider NOP if bank already precharged or in process of precharging + if (Prech_enable === 1'b1) begin + // Display DEBUG Message + if (DEBUG) begin + $display ("%m: At time %t PRE : Addr[10] = %b, Bank = %b", $time, Addr[10], Ba); + end + + // LMR/EMR to Precharge + if ($time - MRD_chk < tMRD) begin + $display ("%m: At time %t ERROR: tMRD violation during Precharge", $time); + if (!no_halt) $stop (0); + end + + // AutoRefresh to Precharge + if ($time - RFC_chk < tRFC) begin + $display ("%m: At time %t ERROR: tRFC violation during Precharge", $time); + if (!no_halt) $stop (0); + end + + // Precharge bank 0 + if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b00)) && Act_b0 === 1'b1) begin + Act_b0 = 1'b0; + Pc_b0 = 1'b1; + RP_chk0 = $time; + + // Activate to Precharge Bank + if ($time - RAS_chk0 < tRAS) begin + $display ("%m: At time %t ERROR: tRAS violation during Precharge", $time); + if (!no_halt) $stop (0); + end + + // tWR violation check for Write + if ($time - WR_chk0 < tWR) begin + $display ("%m: At time %t ERROR: tWR violation during Precharge", $time); + if (!no_halt) $stop (0); + end + end + + // Precharge bank 1 + if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b01)) && Act_b1 === 1'b1) begin + Act_b1 = 1'b0; + Pc_b1 = 1'b1; + RP_chk1 = $time; + + // Activate to Precharge Bank 1 + if ($time - RAS_chk1 < tRAS) begin + $display ("%m: At time %t ERROR: tRAS violation during Precharge", $time); + if (!no_halt) $stop (0); + end + + // tWR violation check for Write + if ($time - WR_chk1 < tWR) begin + $display ("%m: At time %t ERROR: tWR violation during Precharge", $time); + if (!no_halt) $stop (0); + end + end + + // Precharge bank 2 + if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b10)) && Act_b2 === 1'b1) begin + Act_b2 = 1'b0; + Pc_b2 = 1'b1; + RP_chk2 = $time; + + // Activate to Precharge Bank 2 + if ($time - RAS_chk2 < tRAS) begin + $display ("%m: At time %t ERROR: tRAS violation during Precharge", $time); + if (!no_halt) $stop (0); + end + + // tWR violation check for Write + if ($time - WR_chk2 < tWR) begin + $display ("%m: At time %t ERROR: tWR violation during Precharge", $time); + if (!no_halt) $stop (0); + end + end + + // Precharge bank 3 + if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b11)) && Act_b3 === 1'b1) begin + Act_b3 = 1'b0; + Pc_b3 = 1'b1; + RP_chk3 = $time; + + // Activate to Precharge Bank 3 + if ($time - RAS_chk3 < tRAS) begin + $display ("%m: At time %t ERROR: tRAS violation during Precharge", $time); + if (!no_halt) $stop (0); + end + + // tWR violation check for Write + if ($time - WR_chk3 < tWR) begin + $display ("%m: At time %t ERROR: tWR violation during Precharge", $time); + if (!no_halt) $stop (0); + end + end + + // Prech_count is to make sure we have met part of the initialization sequence + Prech_count = Prech_count + 1; + + // Pipeline for READ + A10_precharge [cas_latency_x2] = Addr[10]; + Bank_precharge[cas_latency_x2] = Ba; + Cmnd_precharge[cas_latency_x2] = 1'b1; + end + + // Burst terminate + if (Burst_term === 1'b1) begin + // Display DEBUG Message + if (DEBUG) begin + $display ("%m: At time %t BST : Burst Terminate",$time); + end + + if (Data_in_enable === 1'b1) begin + // Illegal to burst terminate a Write + $display ("%m: At time %t ERROR: It's illegal to burst terminate a Write", $time); + if (!no_halt) $stop (0); + end else if (Read_precharge[0] === 1'b1 || Read_precharge[1] === 1'b1 || + // Illegal to burst terminate a Read with Auto Precharge + Read_precharge[2] === 1'b1 || Read_precharge[3] === 1'b1) begin + $display ("%m: At time %t ERROR: It's illegal to burst terminate a Read with Auto Precharge", $time); + if (!no_halt) $stop (0); + end else begin + // Burst Terminate Command Pipeline for Read + Cmnd_bst[cas_latency_x2] = 1'b1; + end + + end + + // Read Command + if (Read_enable === 1'b1) begin + if (!(power_up_done)) begin + $display ("%m: at time %t ERROR: Power Up and Initialization Sequence not completed before executing Read Command", $time); + end + // Check for DLL reset before Read + if (DLL_reset === 1 && DLL_done === 0) begin + $display ("%m: at time %t ERROR: You need to wait 200 tCK after DLL Reset Enable to Read, Not %0d clocks.", $time, DLL_count); + end + // Display DEBUG Message + if (DEBUG) begin + $display ("%m: At time %t READ : Bank = %h, Col = %h", $time, Ba, {Addr [11], Addr [9 : 0]}); + end + + // Terminate a Write + if (Data_in_enable === 1'b1) begin + Data_in_enable = 1'b0; + end + + // Activate to Read without Auto Precharge + if ((Addr [10] === 1'b0 && Ba === 2'b00 && $time - RCD_chk0 < tRCD) || + (Addr [10] === 1'b0 && Ba === 2'b01 && $time - RCD_chk1 < tRCD) || + (Addr [10] === 1'b0 && Ba === 2'b10 && $time - RCD_chk2 < tRCD) || + (Addr [10] === 1'b0 && Ba === 2'b11 && $time - RCD_chk3 < tRCD)) begin + $display("%m: At time %t ERROR: tRCD violation during Read", $time); + end + + // Activate to Read with Auto Precharge + if ((Addr [10] === 1'b1 && Ba === 2'b00 && $time - RAP_chk0 < tRAP) || + (Addr [10] === 1'b1 && Ba === 2'b01 && $time - RAP_chk1 < tRAP) || + (Addr [10] === 1'b1 && Ba === 2'b10 && $time - RAP_chk2 < tRAP) || + (Addr [10] === 1'b1 && Ba === 2'b11 && $time - RAP_chk3 < tRAP)) begin + $display ("%m: At time %t ERROR: tRAP violation during Read", $time); + end + + // Interrupt a Read with Auto Precharge (same bank only) + if (Read_precharge [Ba] === 1'b1) begin + $display ("%m: At time %t ERROR: It's illegal to interrupt a Read with Auto Precharge", $time); + if (!no_halt) $stop (0); + // Cancel Auto Precharge + if (Addr[10] === 1'b0) begin + Read_precharge [Ba]= 1'b0; + end + end + // Activate to Read + if ((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) || + (Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) begin + $display("%m: At time %t ERROR: Bank is not Activated for Read", $time); + if (!no_halt) $stop (0); + end else begin + // CAS Latency pipeline + Read_cmnd[cas_latency_x2] = 1'b1; + Read_bank[cas_latency_x2] = Ba; + Read_cols[cas_latency_x2] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]}; + // Auto Precharge + if (Addr[10] === 1'b1) begin + Read_precharge [Ba]= 1'b1; + Count_precharge [Ba]= 0; + end + end + end + + // Write Command + if (Write_enable === 1'b1) begin + if (!(power_up_done)) begin + $display ("%m: at time %t ERROR: Power Up and Initialization Sequence not completed before executing Write Command", $time); + if (!no_halt) $stop (0); + end + // display DEBUG message + if (DEBUG) begin + $display ("At time %t WRITE: Bank = %h, Col = %h", $time, Ba, {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]}); + end + + // Activate to Write + if ((Ba === 2'b00 && $time - RCD_chk0 < tRCD) || + (Ba === 2'b01 && $time - RCD_chk1 < tRCD) || + (Ba === 2'b10 && $time - RCD_chk2 < tRCD) || + (Ba === 2'b11 && $time - RCD_chk3 < tRCD)) begin + $display("%m: At time %t ERROR: tRCD violation during Write to Bank %h", $time, Ba); + end + + // Read to Write + if (Read_cmnd[0] || Read_cmnd[1] || Read_cmnd[2] || Read_cmnd[3] || + Read_cmnd[4] || Read_cmnd[5] || Read_cmnd[6] || (Burst_counter < burst_length)) begin + if (Data_out_enable || read_precharge_truncation[Ba]) begin + $display("%m: At time %t ERROR: Read to Write violation", $time); + end + end + + // Interrupt a Write with Auto Precharge (same bank only) + if (Write_precharge [Ba] === 1'b1) begin + $display ("At time %t ERROR: it's illegal to interrupt a Write with Auto Precharge", $time); + if (!no_halt) $stop (0); + // Cancel Auto Precharge + if (Addr[10] === 1'b0) begin + Write_precharge [Ba]= 1'b0; + end + end + // Activate to Write + if ((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) || + (Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) begin + $display("%m: At time %t ERROR: Bank is not Activated for Write", $time); + if (!no_halt) $stop (0); + end else begin + // Pipeline for Write + Write_cmnd [3] = 1'b1; + Write_bank [3] = Ba; + Write_cols [3] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]}; + // Auto Precharge + if (Addr[10] === 1'b1) begin + Write_precharge [Ba]= 1'b1; + Count_precharge [Ba]= 0; + end + end + end + end + endtask + + task check_neg_dqs; + begin + if (Write_cmnd[2] || Write_cmnd[1] || Data_in_enable) begin + for (i=0; i Q0) = (100, 100); + if (C0) (C0 => Q1) = (100, 100); + if (C1) (C1 => Q1) = (100, 100); + if (C1) (C1 => Q0) = (100, 100); + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // IDDR2 + diff --git a/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/test/idelay.v b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/test/idelay.v new file mode 100644 index 0000000..b9afcc7 --- /dev/null +++ b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/test/idelay.v @@ -0,0 +1,23 @@ +/* + * Simplified IDELAY model. + * Only fixed delay type is implemented and assumed. + */ + +`timescale 1ns / 1ps + +module IDELAY #( + parameter IOBDELAY_TYPE = "DEFAULT", + parameter IOBDELAY_VALUE = 0 +) ( + input C, + input CE, + input I, + input INC, + input RST, + output reg O +); + +always @(I) + # (IOBDELAY_VALUE*0.078) O = I; + +endmodule diff --git a/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/test/iobuf.v b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/test/iobuf.v new file mode 100644 index 0000000..5bf3dfa --- /dev/null +++ b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/test/iobuf.v @@ -0,0 +1,74 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// Modified for HPDMC simulation, based on Xilinx 04/22/09 revision +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + + +module IOBUF (O, IO, I, T); + + parameter CAPACITANCE = "DONT_CARE"; + parameter integer DRIVE = 12; + parameter IBUF_DELAY_VALUE = "0"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IFD_DELAY_VALUE = "AUTO"; + parameter IOSTANDARD = "DEFAULT"; + parameter SLEW = "SLOW"; + + output O; + inout IO; + input I, T; + + bufif0 T1 (IO, I, T); + + buf B1 (O, IO); + + initial begin + + case (CAPACITANCE) + + "LOW", "NORMAL", "DONT_CARE" : ; + default : begin + $display("Attribute Syntax Error : The attribute CAPACITANCE on IOBUF instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE); + $finish; + end + + endcase + + case (IBUF_DELAY_VALUE) + + "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on IOBUF instance %m is set to %s. Legal values for this attribute are 0, 1, 2, ... or 16.", IBUF_DELAY_VALUE); + $finish; + end + + endcase + + case (IBUF_LOW_PWR) + + "FALSE", "TRUE" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUF instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR); + $finish; + end + + endcase + + case (IFD_DELAY_VALUE) + + "AUTO", "0", "1", "2", "3", "4", "5", "6", "7", "8" : ; + default : begin + $display("Attribute Syntax Error : The attribute IFD_DELAY_VALUE on IOBUF instance %m is set to %s. Legal values for this attribute are AUTO, 0, 1, 2, ... or 8.", IFD_DELAY_VALUE); + $finish; + end + + endcase + + end // initial begin + +endmodule + diff --git a/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/test/obuft.v b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/test/obuft.v new file mode 100644 index 0000000..6966489 --- /dev/null +++ b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/test/obuft.v @@ -0,0 +1,38 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// Modified for HPDMC simulation, based on Xilinx 05/23/07 revision +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + + +module OBUFT (O, I, T); + + parameter CAPACITANCE = "DONT_CARE"; + parameter integer DRIVE = 12; + parameter IOSTANDARD = "DEFAULT"; + parameter SLEW = "SLOW"; + + output O; + input I, T; + + bufif0 T1 (O, I, T); + + initial begin + + case (CAPACITANCE) + + "LOW", "NORMAL", "DONT_CARE" : ; + default : begin + $display("Attribute Syntax Error : The attribute CAPACITANCE on OBUFT instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE); + $finish; + end + + endcase + + end + +endmodule + diff --git a/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/test/oddr.v b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/test/oddr.v new file mode 100644 index 0000000..fb570e3 --- /dev/null +++ b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/test/oddr.v @@ -0,0 +1,99 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2005 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// Modified for HPDMC simulation, based on Xilinx 05/29/07 revision +/////////////////////////////////////////////////////////////////////////////// + +module ODDR #( + parameter DDR_CLK_EDGE = "OPPOSITE_EDGE", + parameter INIT = 1'b0, + parameter SRTYPE = "SYNC" +) ( + output Q, + input C, + input CE, + input D1, + input D2, + input R, + input S +); + +reg q_out = INIT, qd2_posedge_int; + +wire c_in; +wire ce_in; +wire d1_in; +wire d2_in; +wire gsr_in; +wire r_in; +wire s_in; + +buf buf_c(c_in, C); +buf buf_ce(ce_in, CE); +buf buf_d1(d1_in, D1); +buf buf_d2(d2_in, D2); +buf buf_q(Q, q_out); +buf buf_r(r_in, R); +buf buf_s(s_in, S); + +initial begin + if((INIT != 0) && (INIT != 1)) begin + $display("Attribute Syntax Error : The attribute INIT on ODDR instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT); + $finish; + end + + if((DDR_CLK_EDGE != "OPPOSITE_EDGE") && (DDR_CLK_EDGE != "SAME_EDGE")) begin + $display("Attribute Syntax Error : The attribute DDR_CLK_EDGE on ODDR instance %m is set to %s. Legal values for this attribute are OPPOSITE_EDGE or SAME_EDGE.", DDR_CLK_EDGE); + $finish; + end + + if((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin + $display("Attribute Syntax Error : The attribute SRTYPE on ODDR instance %m is set to %s. Legal values for this attribute are ASYNC or SYNC.", SRTYPE); + $finish; + end +end + +always @(r_in, s_in) begin + if(r_in == 1'b1 && SRTYPE == "ASYNC") begin + assign q_out = 1'b0; + assign qd2_posedge_int = 1'b0; + end else if(r_in == 1'b0 && s_in == 1'b1 && SRTYPE == "ASYNC") begin + assign q_out = 1'b1; + assign qd2_posedge_int = 1'b1; + end else if((r_in == 1'b1 || s_in == 1'b1) && SRTYPE == "SYNC") begin + deassign q_out; + deassign qd2_posedge_int; + end else if(r_in == 1'b0 && s_in == 1'b0) begin + deassign q_out; + deassign qd2_posedge_int; + end +end + +always @(posedge c_in) begin + if(r_in == 1'b1) begin + q_out <= 1'b0; + qd2_posedge_int <= 1'b0; + end else if(r_in == 1'b0 && s_in == 1'b1) begin + q_out <= 1'b1; + qd2_posedge_int <= 1'b1; + end else if(ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) begin + q_out <= d1_in; + qd2_posedge_int <= d2_in; + end +end + +always @(negedge c_in) begin + if(r_in == 1'b1) + q_out <= 1'b0; + else if(r_in == 1'b0 && s_in == 1'b1) + q_out <= 1'b1; + else if(ce_in == 1'b1 && r_in == 1'b0 && s_in == 1'b0) begin + if(DDR_CLK_EDGE == "SAME_EDGE") + q_out <= qd2_posedge_int; + else if(DDR_CLK_EDGE == "OPPOSITE_EDGE") + q_out <= d2_in; + end +end + +endmodule diff --git a/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/test/oddr2.v b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/test/oddr2.v new file mode 100644 index 0000000..3c26010 --- /dev/null +++ b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/test/oddr2.v @@ -0,0 +1,131 @@ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// + +// Modified for HPDMC simulation, based on Xilinx 01/12/09 revision +/////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ps / 1 ps + +module ODDR2 (Q, C0, C1, CE, D0, D1, R, S); + + output Q; + + input C0; + input C1; + input CE; + input D0; + input D1; + + input R; + input S; + + parameter DDR_ALIGNMENT = "NONE"; + parameter INIT = 1'b0; + parameter SRTYPE = "SYNC"; + + pullup P1 (CE); + pulldown P2 (R); + pulldown P3 (S); + + reg q_out, q_d1_c0_out_int; + wire PC0, PC1; + + buf buf_q (Q, q_out); + + + initial begin + + if ((INIT != 1'b0) && (INIT != 1'b1)) begin + $display("Attribute Syntax Error : The attribute INIT on ODDR2 instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT); + $finish; + end + + if ((DDR_ALIGNMENT != "NONE") && (DDR_ALIGNMENT != "C0") && (DDR_ALIGNMENT != "C1")) begin + $display("Attribute Syntax Error : The attribute DDR_ALIGNMENT on ODDR2 instance %m is set to %s. Legal values for this attribute are NONE, C0 or C1.", DDR_ALIGNMENT); + $finish; + end + + if ((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin + $display("Attribute Syntax Error : The attribute SRTYPE on ODDR2 instance %m is set to %s. Legal values for this attribute are ASYNC or SYNC.", SRTYPE); + $finish; + end + + end // initial begin + + initial begin + assign q_out = INIT; + assign q_d1_c0_out_int = INIT; + end + + always @(R or S) begin + + deassign q_out; + deassign q_d1_c0_out_int; + + if (SRTYPE == "ASYNC") begin + if (R == 1) begin + assign q_out = 0; + assign q_d1_c0_out_int = 0; + end + else if (R == 0 && S == 1) begin + assign q_out = 1; + assign q_d1_c0_out_int = 1; + end + end // if (SRTYPE == "ASYNC") + + end // always @ (GSR or R or S) + + assign PC0 = ((DDR_ALIGNMENT== "C0") || (DDR_ALIGNMENT== "NONE"))? C0 : C1; + assign PC1 = ((DDR_ALIGNMENT== "C0") || (DDR_ALIGNMENT== "NONE"))? C1 : C0; + + always @(posedge PC0) begin + + if (R == 1 && SRTYPE == "SYNC") begin + q_out <= 0; + q_d1_c0_out_int <= 0; + end + else if (R == 0 && S == 1 && SRTYPE == "SYNC") begin + q_out <= 1; + q_d1_c0_out_int <= 1; + end + else if (CE == 1 && R == 0 && S == 0) begin + q_out <= D0; + q_d1_c0_out_int <= D1 ; + end // if (CE == 1 && R == 0 && S == 0) + + end // always @ (posedge C0) + + + always @(posedge PC1) begin + + if (R == 1 && SRTYPE == "SYNC") begin + q_out <= 0; + end + else if (R == 0 && S == 1 && SRTYPE == "SYNC") begin + q_out <= 1; + end + else if (CE == 1 && R == 0 && S == 0) begin + + if (DDR_ALIGNMENT == "NONE") + q_out <= D1; + else + q_out <= q_d1_c0_out_int; + + + end // if (CE == 1 && R == 0 && S == 0) + + end // always @ (negedge c_in) + + + specify + + if (C0) (C0 => Q) = (100, 100); + if (C1) (C1 => Q) = (100, 100); + specparam PATHPULSE$ = 0; + + endspecify + +endmodule // ODDR2 + diff --git a/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/test/subtest.vh b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/test/subtest.vh new file mode 100644 index 0000000..61d7d36 --- /dev/null +++ b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/test/subtest.vh @@ -0,0 +1,236 @@ +initial begin : test + +cke <= 1'b0; +cs_n <= 1'b1; +ras_n <= 1'b1; +cas_n <= 1'b1; +we_n <= 1'b1; +ba <= {BA_BITS{1'bz}}; +a <= {ADDR_BITS{1'bz}}; +dq_en <= 1'b0; +dqs_en <= 1'b0; +cke <= 1'b1; +power_up; +$display("Powerup complete"); +precharge('h00000000, 1); +nop(trp); +load_mode('h1, 'h00002000); +nop(tmrd-1); +load_mode('h0, 'h0000013A); +nop(tmrd-1); +precharge('h00000000, 1); +nop(trp); +refresh; +nop(trfc); +refresh; +nop(trfc); +load_mode('h0, 'h0000003A); +nop(tmrd-1); +nop('h000000C8); +activate('h00000000, 'h00000000); +nop(trcd-1); +write('h00000000, 'h00000000, 1, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h30003000, 32'h20002000, 32'h10001000, 32'h0}); +nop(BL/2+twr); +activate('h00000001, 'h00000000); +nop(trcd-1); +write('h00000001, 'h00000000, 1, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h30013001, 32'h20012001, 32'h10011001, 32'h10001}); +nop(BL/2+twr); +activate('h00000002, 'h00000000); +nop(trcd-1); +write('h00000002, 'h00000000, 1, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h30023002, 32'h20022002, 32'h10021002, 32'h20002}); +nop(BL/2+twr); +activate('h00000003, 'h00000000); +nop(trcd-1); +write('h00000003, 'h00000000, 1, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h30033003, 32'h20032003, 32'h10031003, 32'h30003}); +nop(BL/2+twr); +activate('h00000000, 'h00000000); +nop(trrd-1); +activate('h00000001, 'h00000000); +nop(trrd-1); +activate('h00000002, 'h00000000); +nop(trrd-1); +activate('h00000003, 'h00000000); +read('h00000000, 'h00000000, 1); +nop(BL/2-1); +read('h00000001, 'h00000000, 1); +nop(BL/2-1); +read('h00000002, 'h00000000, 1); +nop(BL/2-1); +read('h00000003, 'h00000000, 1); +nop(BL/2+twr-2); +activate('h00000001, 'h00000000); +nop(trrd-1); +activate('h00000000, 'h00000000); +nop(trcd-1); +$display("%m At time %t: WRITE Burst", $time);write('h00000000, 'h00000004, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h30403040, 32'h20402040, 32'h10401040, 32'h400040}); +nop(BL/2+4); +$display("%m At time %t: Consecutive WRITE to WRITE", $time);write('h00000000, 'h00000008, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h30803080, 32'h20802080, 32'h10801080, 32'h800080}); +nop(BL/2-1); +write('h00000000, 'h0000000C, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h31203120, 32'h21202120, 32'h11201120, 32'h1200120}); +nop(BL/2-1); +$display("%m At time %t: Nonconsecutive WRITE to WRITE", $time);write('h00000000, 'h00000010, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h31603160, 32'h21602160, 32'h11601160, 32'h1600160}); +nop(BL/2+4); +write('h00000000, 'h00000014, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h32003200, 32'h22002200, 32'h12001200, 32'h2000200}); +nop(BL/2+twr+4); +$display("%m At time %t: Random WRITE Cycles", $time);write('h00000000, 'h00000018, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h32403240, 32'h22402240, 32'h12401240, 32'h2400240}); +nop(BL/2-1); +write('h00000000, 'h0000001C, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h32803280, 32'h22802280, 32'h12801280, 32'h2800280}); +nop(BL/2-1); +write('h00000000, 'h00000020, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h33203320, 32'h23202320, 32'h13201320, 32'h3200320}); +nop(BL/2-1); +write('h00000000, 'h00000024, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h33603360, 32'h23602360, 32'h13601360, 32'h3600360}); +nop(BL/2-1); +$display("%m At time %t: WRITE to READ - Uninterrupting", $time);write('h00000000, 'h00000028, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h34003400, 32'h24002400, 32'h14001400, 32'h4000400}); +nop(BL/2+1); +read('h00000000, 'h00000028, 0); +nop(CL+BL/2-1); +$display("%m At time %t: WRITE to READ - Interrupting", $time);write('h00000000, 'h0000002C, 0, { 4'h1, 4'h1, 4'h0, 4'h0}, { 32'h34403440, 32'h24402440, 32'h14401440, 32'h4400440}); +nop(BL/2+1); +read('h00000000, 'h0000002C, 0); +nop(CL+BL/2-1); +$display("%m At time %t: WRITE to READ - Odd Number of Data, Interrupting", $time);write('h00000000, 'h00000030, 0, { 4'h1, 4'h1, 4'h1, 4'h0}, { 32'h34803480, 32'h24802480, 32'h14801480, 32'h4800480}); +nop(BL/2+1); +read('h00000000, 'h00000030, 0); +nop(CL+BL/2-1); +$display("%m At time %t: WRITE to PRECHARGE - Uninterrupting", $time);write('h00000000, 'h00000034, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h35203520, 32'h25202520, 32'h15201520, 32'h5200520}); +nop(BL/2+twr); +precharge('h00000000, 0); +nop(trp-1); +$display("%m At time %t: WRITE with AUTO PRECHARGE", $time);activate('h00000000, 'h00000000); +nop(trcd-1); +write('h00000000, 'h00000040, 1, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h36603660, 32'h26602660, 32'h16601660, 32'h6600660}); +nop(BL/2+twr+trp); +activate('h00000000, 'h00000000); +nop(trcd-1); +$display("%m At time %t: READ Burst", $time);read('h00000000, 'h00000000, 0); +nop(BL/2-1); +$display("%m At time %t: Consecutive READ Bursts", $time);read('h00000000, 'h00000004, 0); +nop(BL/2-2); +read('h00000000, 'h00000008, 0); +nop(BL/2-1); +$display("%m At time %t: Nonconsecutive READ Bursts", $time);read('h00000000, 'h0000000C, 0); +nop(BL/2); +read('h00000000, 'h00000010, 0); +nop(BL/2); +$display("%m At time %t: Random READ Accesses", $time);read('h00000000, 'h00000014, 0); +read('h00000000, 'h00000018, 0); +read('h00000000, 'h0000001C, 0); +read('h00000000, 'h00000020, 0); +nop(BL/2); +$display("%m At time %t: Terminating a READ Burst", $time);read('h00000000, 'h00000024, 0); +burst_term; +nop(BL/2-2); +$display("%m At time %t: READ to WRITE", $time);read('h00000000, 'h00000028, 0); +burst_term; +nop(CL); +write('h00000000, 'h0000002C, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'h34C034C0, 32'h24C024C0, 32'h14C014C0, 32'h4C004C0}); +nop(BL/2+1); +$display("%m At time %t: READ to PRECHARGE", $time);read('h00000000, 'h00000030, 0); +nop('h00000001); +precharge('h00000000, 0); +nop(trp-1); +$display("%m At time %t: READ with AUTO PRECHARGE", $time);activate('h00000000, 'h00000000); +nop(trcd-1); +read('h00000000, 'h00000034, 1); +nop(CL+BL/2+twr); +$display("%m At time %t: WRITE to READ - Mask byte 0 of Burst 0", $time);activate('h00000000, 'h00000000); +nop(trcd-1); +write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF}); +nop(BL/2); +write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h1}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0}); +nop(BL/2+1); +read('h00000000, 'h00000064, 0); +nop(CL+BL/2-1); +$display("%m At time %t: WRITE to READ - Mask byte 1 of Burst 0", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF}); +nop(BL/2); +write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h2}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0}); +nop(BL/2+1); +read('h00000000, 'h00000064, 0); +nop(CL+BL/2-1); +$display("%m At time %t: WRITE to READ - Mask byte 2 of Burst 0", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF}); +nop(BL/2); +write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h4}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0}); +nop(BL/2+1); +read('h00000000, 'h00000064, 0); +nop(CL+BL/2-1); +$display("%m At time %t: WRITE to READ - Mask byte 3 of Burst 0", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF}); +nop(BL/2); +write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h8}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0}); +nop(BL/2+1); +read('h00000000, 'h00000064, 0); +nop(CL+BL/2-1); +$display("%m At time %t: WRITE to READ - Mask byte 0 of Burst 1", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF}); +nop(BL/2); +write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h1, 4'h0}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0}); +nop(BL/2+1); +read('h00000000, 'h00000064, 0); +nop(CL+BL/2-1); +$display("%m At time %t: WRITE to READ - Mask byte 1 of Burst 1", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF}); +nop(BL/2); +write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h2, 4'h0}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0}); +nop(BL/2+1); +read('h00000000, 'h00000064, 0); +nop(CL+BL/2-1); +$display("%m At time %t: WRITE to READ - Mask byte 2 of Burst 1", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF}); +nop(BL/2); +write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h4, 4'h0}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0}); +nop(BL/2+1); +read('h00000000, 'h00000064, 0); +nop(CL+BL/2-1); +$display("%m At time %t: WRITE to READ - Mask byte 3 of Burst 1", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF}); +nop(BL/2); +write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h8, 4'h0}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0}); +nop(BL/2+1); +read('h00000000, 'h00000064, 0); +nop(CL+BL/2-1); +$display("%m At time %t: WRITE to READ - Mask byte 0 of Burst 2", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF}); +nop(BL/2); +write('h00000000, 'h00000064, 0, { 4'h0, 4'h1, 4'h0, 4'h0}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0}); +nop(BL/2+1); +read('h00000000, 'h00000064, 0); +nop(CL+BL/2-1); +$display("%m At time %t: WRITE to READ - Mask byte 1 of Burst 2", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF}); +nop(BL/2); +write('h00000000, 'h00000064, 0, { 4'h0, 4'h2, 4'h0, 4'h0}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0}); +nop(BL/2+1); +read('h00000000, 'h00000064, 0); +nop(CL+BL/2-1); +$display("%m At time %t: WRITE to READ - Mask byte 2 of Burst 2", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF}); +nop(BL/2); +write('h00000000, 'h00000064, 0, { 4'h0, 4'h4, 4'h0, 4'h0}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0}); +nop(BL/2+1); +read('h00000000, 'h00000064, 0); +nop(CL+BL/2-1); +$display("%m At time %t: WRITE to READ - Mask byte 3 of Burst 2", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF}); +nop(BL/2); +write('h00000000, 'h00000064, 0, { 4'h0, 4'h8, 4'h0, 4'h0}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0}); +nop(BL/2+1); +read('h00000000, 'h00000064, 0); +nop(CL+BL/2-1); +$display("%m At time %t: WRITE to READ - Mask byte 0 of Burst 3", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF}); +nop(BL/2); +write('h00000000, 'h00000064, 0, { 4'h1, 4'h0, 4'h0, 4'h0}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0}); +nop(BL/2+1); +read('h00000000, 'h00000064, 0); +nop(CL+BL/2-1); +$display("%m At time %t: WRITE to READ - Mask byte 1 of Burst 3", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF}); +nop(BL/2); +write('h00000000, 'h00000064, 0, { 4'h2, 4'h0, 4'h0, 4'h0}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0}); +nop(BL/2+1); +read('h00000000, 'h00000064, 0); +nop(CL+BL/2-1); +$display("%m At time %t: WRITE to READ - Mask byte 2 of Burst 3", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF}); +nop(BL/2); +write('h00000000, 'h00000064, 0, { 4'h4, 4'h0, 4'h0, 4'h0}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0}); +nop(BL/2+1); +read('h00000000, 'h00000064, 0); +nop(CL+BL/2-1); +$display("%m At time %t: WRITE to READ - Mask byte 3 of Burst 3", $time);write('h00000000, 'h00000064, 0, { 4'h0, 4'h0, 4'h0, 4'h0}, { 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF, 32'hFFFFFFFF}); +nop(BL/2); +write('h00000000, 'h00000064, 0, { 4'h8, 4'h0, 4'h0, 4'h0}, { 32'h33333333, 32'h22222222, 32'h11111111, 32'h0}); +nop(BL/2+1); +read('h00000000, 'h00000064, 1); +nop(CL+BL/2-1); +test_done = 1; +end + diff --git a/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/test/tb_hpdmc.v b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/test/tb_hpdmc.v new file mode 100644 index 0000000..451b412 --- /dev/null +++ b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/test/tb_hpdmc.v @@ -0,0 +1,390 @@ +/* + * Milkymist VJ SoC + * Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, version 3 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +`timescale 1ns / 1ps + +//`define ENABLE_VCD +`define TEST_SOMETRANSFERS +//`define TEST_RANDOMTRANSFERS + +module tb_hpdmc(); + +/* 100MHz system clock */ +reg clk; +initial clk = 1'b0; +always #5 clk = ~clk; + +/* DQS clock is phased out by 90 degrees, resulting in 2.5ns delay */ +reg dqs_clk; +always @(clk) #2.5 dqs_clk = clk; + +wire sdram_cke; +wire sdram_cs_n; +wire sdram_we_n; +wire sdram_cas_n; +wire sdram_ras_n; +wire [3:0] sdram_dm; +wire [12:0] sdram_adr; +wire [1:0] sdram_ba; +wire [31:0] sdram_dq; +wire [3:0] sdram_dqs; + +ddr sdram1( + .Addr(sdram_adr), + .Ba(sdram_ba), + .Clk(clk), + .Clk_n(~clk), + .Cke(sdram_cke), + .Cs_n(sdram_cs_n), + .Ras_n(sdram_ras_n), + .Cas_n(sdram_cas_n), + .We_n(sdram_we_n), + + .Dm(sdram_dm[3:2]), + .Dqs(sdram_dqs[3:2]), + .Dq(sdram_dq[31:16]) +); + +ddr sdram0( + .Addr(sdram_adr), + .Ba(sdram_ba), + .Clk(clk), + .Clk_n(~clk), + .Cke(sdram_cke), + .Cs_n(sdram_cs_n), + .Ras_n(sdram_ras_n), + .Cas_n(sdram_cas_n), + .We_n(sdram_we_n), + + .Dm(sdram_dm[1:0]), + .Dqs(sdram_dqs[1:0]), + .Dq(sdram_dq[15:0]) +); + +reg rst; + +reg [13:0] csr_a; +reg csr_we; +reg [31:0] csr_di; +wire [31:0] csr_do; + +reg [25:0] fml_adr; +reg fml_stb; +reg fml_we; +wire fml_ack; +reg [7:0] fml_sel; +reg [63:0] fml_di; +wire [63:0] fml_do; + +hpdmc dut( + .sys_clk(clk), + .sys_clk_n(~clk), + .dqs_clk(dqs_clk), + .dqs_clk_n(~dqs_clk), + .sys_rst(rst), + + .csr_a(csr_a), + .csr_we(csr_we), + .csr_di(csr_di), + .csr_do(csr_do), + + .fml_adr(fml_adr), + .fml_stb(fml_stb), + .fml_we(fml_we), + .fml_ack(fml_ack), + .fml_sel(fml_sel), + .fml_di(fml_di), + .fml_do(fml_do), + + .sdram_cke(sdram_cke), + .sdram_cs_n(sdram_cs_n), + .sdram_we_n(sdram_we_n), + .sdram_cas_n(sdram_cas_n), + .sdram_ras_n(sdram_ras_n), + .sdram_dm(sdram_dm), + .sdram_adr(sdram_adr), + .sdram_ba(sdram_ba), + .sdram_dq(sdram_dq), + .sdram_dqs(sdram_dqs), + + .dqs_psen(), + .dqs_psincdec(), + .dqs_psdone(1'b1) +); + +task waitclock; +begin + @(posedge clk); + #1; +end +endtask + +task waitnclock; +input [15:0] n; +integer i; +begin + for(i=0;i 32'h80000000) begin + writeburst(addr); + //writeburst(addr+32'h20); + //writeburst(addr+32'h40); + end else begin + readburst(addr); + //readburst(addr+32'h20); + //readburst(addr+32'h40); + end + end + + $display(""); + $display("======================================================="); + $display(" Tested: %.0f reads, %.0f writes ", reads, writes); + $display("======================================================="); + $display(" Average read latency: %f cycles", read_clocks/reads); + $display(" Average write latency: %f cycles", write_clocks/writes); + $display("======================================================="); + $display(" Average read bandwidth: %f MBit/s @ 100MHz", (4/(4+read_clocks/reads))*64*100); + $display(" Average write bandwidth: %f MBit/s @ 100MHz", (4/(4+write_clocks/writes))*64*100); + $display("======================================================="); + +`endif + + $finish; +end + +endmodule + diff --git a/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/test/tb_model.v b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/test/tb_model.v new file mode 100644 index 0000000..5b8642f --- /dev/null +++ b/demo_chip_rtl/rtl/hpdmc/trunk/hpdmc_ddr32/test/tb_model.v @@ -0,0 +1,556 @@ +/**************************************************************************************** +* +* File Name: tb.v +* Version: 5.7 +* Model: BUS Functional +* +* Dependencies: ddr.v, ddr_parameters.v +* +* Description: Micron SDRAM DDR (Double Data Rate) test bench +* +* Note: - Set simulator resolution to "ps" accuracy +* - Set Debug = 0 to disable $display messages +* +* Disclaimer This software code and all associated documentation, comments or other +* of Warranty: information (collectively "Software") is provided "AS IS" without +* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY +* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES +* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT +* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE +* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. +* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR +* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, +* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE +* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, +* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, +* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, +* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, +* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE +* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH +* DAMAGES. Because some jurisdictions prohibit the exclusion or +* limitation of liability for consequential or incidental damages, the +* above limitation may not apply to you. +* +* Copyright 2003 Micron Technology, Inc. All rights reserved. +* +* Rev Author Date Changes +* -------------------------------------------------------------------------------- +* 2.1 SPH 03/19/2002 - Second Release +* - Fix tWR and several incompatability +* between different simulators +* 3.0 TFK 02/18/2003 - Added tDSS and tDSH timing checks. +* - Added tDQSH and tDQSL timing checks. +* 3.1 CAH 05/28/2003 - update all models to release version 3.1 +* (no changes to this model) +* 3.2 JMK 06/16/2003 - updated all DDR400 models to support CAS Latency 3 +* 3.3 JMK 09/11/2003 - Added initialization sequence checks. +* 4.0 JMK 12/01/2003 - Grouped parameters into "ddr_parameters.v" +* - Fixed tWTR check +* 4.1 JMK 01/14/2001 - Grouped specify parameters by speed grade +* - Fixed mem_sizes parameter +* 4.2 JMK 03/19/2004 - Fixed pulse width checking on Dqs +* 4.3 JMK 04/27/2004 - Changed BL wire size in tb module +* - Changed Dq_buf size to [15:0] +* 5.0 JMK 06/16/2004 - Added read to write checking. +* - Added read with precharge truncation to write checking. +* - Added associative memory array to reduce memory consumption. +* - Added checking for required DQS edges during write. +* 5.1 JMK 08/16/2004 - Fixed checking for required DQS edges during write. +* - Fixed wdqs_valid window. +* 5.2 JMK 09/24/2004 - Read or Write without activate will be ignored. +* 5.3 JMK 10/27/2004 - Added tMRD checking during Auto Refresh and Activate. +* - Added tRFC checking during Load Mode and Precharge. +* 5.4 JMK 12/13/2004 - The model will not respond to illegal command sequences. +* 5.5 SPH 01/13/2005 - The model will issue a halt on illegal command sequences. +* JMK 02/11/2005 - Changed the display format for numbers to hex. +* 5.6 JMK 04/22/2005 - Fixed Write with auto precharge calculation. +* 5.7 JMK 08/05/2005 - Changed conditions for read with precharge truncation error. +* - Renamed parameters file with .vh extension. +* 5.8 BAS 12/26/2006 - Added parameters for T46A part - 256Mb +* - Added x32 functionality +* 6.0 BAS 05/31/2007 - Added read_verify command +****************************************************************************************/ + +`timescale 1ns / 1ps + +module tb; + +`include "ddr_parameters.vh" + + reg clk ; + reg clk_n ; + reg cke ; + reg cs_n ; + reg ras_n ; + reg cas_n ; + reg we_n ; + reg [BA_BITS - 1 : 0] ba ; + reg [ADDR_BITS - 1 : 0] a ; + reg dq_en ; + reg [DM_BITS - 1 : 0] dm_out ; + reg [DQ_BITS - 1 : 0] dq_out ; + reg [DM_BITS-1 : 0] dm_fifo [0 : 13]; + reg [DQ_BITS-1 : 0] dq_fifo [0 : 13]; + reg [DQ_BITS-1 : 0] dq_in_pos ; + reg [DQ_BITS-1 : 0] dq_in_neg ; + reg dqs_en ; + reg [DQS_BITS - 1 : 0] dqs_out ; + + reg [12 : 0] mode_reg ; //Mode Register + reg [12 : 0] ext_mode_reg; //Extended Mode Register + + wire BO = mode_reg[3]; //Burst Order + wire [7 : 0] BL = (1< $rtoi(number)) + ciel = $rtoi(number) + 1; + else + ciel = number; + endfunction + + task power_up; + begin + cke <= 1'b0; + repeat(10) @(negedge clk); + $display ("%m at time %t TB: A 200 us delay is required before CKE can be brought high.", $time); + @ (negedge clk) cke = 1'b1; + nop (400/tck+1); + end + endtask + + task load_mode; + input [BA_BITS - 1 : 0] bank; + input [ADDR_BITS - 1 : 0] addr; + begin + case (bank) + 0: mode_reg = addr; + 1: ext_mode_reg = addr; + endcase + cke = 1'b1; + cs_n = 1'b0; + ras_n = 1'b0; + cas_n = 1'b0; + we_n = 1'b0; + ba = bank; + a = addr; + @(negedge clk); + end + endtask + + task refresh; + begin + cke = 1'b1; + cs_n = 1'b0; + ras_n = 1'b0; + cas_n = 1'b0; + we_n = 1'b1; + @(negedge clk); + end + endtask + + task burst_term; + integer i; + begin + cke = 1'b1; + cs_n = 1'b0; + ras_n = 1'b1; + cas_n = 1'b1; + we_n = 1'b0; + @(negedge clk); + for (i=0; i>10)<<11; //ADDR[ N:11] = COL[ N:10] + a = atemp[0] | atemp[1] | (ap<<10); + + for (i=0; i<=BL; i=i+1) begin + dqs_en <= #(WL*tck + i*tck/2) 1'b1; + if (i%2 === 0) begin + dqs_out <= #(WL*tck + i*tck/2) {DQS_BITS{1'b0}}; + end else begin + dqs_out <= #(WL*tck + i*tck/2) {DQS_BITS{1'b1}}; + end + dq_en <= #(WL*tck + i*tck/2 + tck/4) 1'b1; + for (j=0; j>((i*DM_BITS + j)*DQ_BITS/DM_BITS); + dm_out[j] <= #(WL*tck + i*tck/2 + tck/4) &dm_temp; + end + dq_out <= #(WL*tck + i*tck/2 + tck/4) dq>>i*DQ_BITS; + case (i) + 15: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[16*DM_BITS-1 : 15*DM_BITS]; + 14: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[15*DM_BITS-1 : 14*DM_BITS]; + 13: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[14*DM_BITS-1 : 13*DM_BITS]; + 12: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[13*DM_BITS-1 : 12*DM_BITS]; + 11: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[12*DM_BITS-1 : 11*DM_BITS]; + 10: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[11*DM_BITS-1 : 10*DM_BITS]; + 9: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[10*DM_BITS-1 : 9*DM_BITS]; + 8: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 9*DM_BITS-1 : 8*DM_BITS]; + 7: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 8*DM_BITS-1 : 7*DM_BITS]; + 6: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 7*DM_BITS-1 : 6*DM_BITS]; + 5: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 6*DM_BITS-1 : 5*DM_BITS]; + 4: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 5*DM_BITS-1 : 4*DM_BITS]; + 3: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 4*DM_BITS-1 : 3*DM_BITS]; + 2: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 3*DM_BITS-1 : 2*DM_BITS]; + 1: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 2*DM_BITS-1 : 1*DM_BITS]; + 0: dm_out <= #(WL*tck + i*tck/2 + tck/4) dm[ 1*DM_BITS-1 : 0*DM_BITS]; + endcase + case (i) + 15: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[16*DQ_BITS-1 : 15*DQ_BITS]; + 14: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[15*DQ_BITS-1 : 14*DQ_BITS]; + 13: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[14*DQ_BITS-1 : 13*DQ_BITS]; + 12: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[13*DQ_BITS-1 : 12*DQ_BITS]; + 11: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[12*DQ_BITS-1 : 11*DQ_BITS]; + 10: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[11*DQ_BITS-1 : 10*DQ_BITS]; + 9: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[10*DQ_BITS-1 : 9*DQ_BITS]; + 8: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 9*DQ_BITS-1 : 8*DQ_BITS]; + 7: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 8*DQ_BITS-1 : 7*DQ_BITS]; + 6: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 7*DQ_BITS-1 : 6*DQ_BITS]; + 5: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 6*DQ_BITS-1 : 5*DQ_BITS]; + 4: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 5*DQ_BITS-1 : 4*DQ_BITS]; + 3: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 4*DQ_BITS-1 : 3*DQ_BITS]; + 2: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 3*DQ_BITS-1 : 2*DQ_BITS]; + 1: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 2*DQ_BITS-1 : 1*DQ_BITS]; + 0: dq_out <= #(WL*tck + i*tck/2 + tck/4) dq[ 1*DQ_BITS-1 : 0*DQ_BITS]; + endcase + dq_en <= #(WL*tck + i*tck/2 + tck/4) 1'b1; + end + dqs_en <= #(WL*tck + BL*tck/2 + tck/2) 1'b0; + dq_en <= #(WL*tck + BL*tck/2 + tck/4) 1'b0; + @(negedge clk); + end + endtask + + task read; + input [BA_BITS - 1 : 0]bank; + input [COL_BITS - 1 : 0] col; + input ap; //Auto Precharge + reg [ADDR_BITS - 1 : 0] atemp [1:0]; + begin + cke = 1'b1; + cs_n = 1'b0; + ras_n = 1'b1; + cas_n = 1'b0; + we_n = 1'b1; + ba = bank; + atemp[0] = col & 10'h3ff; //ADDR[ 9: 0] = COL[ 9: 0] + atemp[1] = (col>>10)<<11; //ADDR[ N:11] = COL[ N:10] + a = atemp[0] | atemp[1] | (ap<<10); + @(negedge clk); + end + endtask + + // read with data verification + task read_verify; + input [BA_BITS - 1 : 0] bank; + input [COL_BITS - 1 : 0] col; + input ap; //Auto Precharge + input [16*DM_BITS - 1 : 0] dm; //Expected Data Mask + input [16*DQ_BITS - 1 : 0] dq; //Expected Data + integer i; + reg [2:0] brst_col; + begin + read (bank, col, ap); + for (i=0; i> (i*DM_BITS); + dq_fifo[2*RL + i] = dq >> (i*DQ_BITS); + end + end + endtask + + task nop; + input count; + integer count; + begin + cke = 1'b1; + cs_n = 1'b0; + ras_n = 1'b1; + cas_n = 1'b1; + we_n = 1'b1; + repeat(count) @(negedge clk); + end + endtask + + task deselect; + input count; + integer count; + begin + cke = 1'b1; + cs_n = 1'b1; + ras_n = 1'b1; + cas_n = 1'b1; + we_n = 1'b1; + repeat(count) @(negedge clk); + end + endtask + + task power_down; + input count; + integer count; + begin + cke = 1'b0; + cs_n = 1'b1; + ras_n = 1'b1; + cas_n = 1'b1; + we_n = 1'b1; + repeat(count) @(negedge clk); + end + endtask + + function [16*DQ_BITS - 1 : 0] sort_data; + input [16*DQ_BITS - 1 : 0] dq; + input [2:0] col; + integer i; + reg [2:0] brst_col; + reg [DQ_BITS - 1 :0] burst; + begin + sort_data = 0; + for (i=0; i> (brst_col*DQ_BITS); + sort_data = sort_data | burst<<(i*DQ_BITS); + end + end + endfunction + + // receiver(s) for data_verify process + always @(dqs_in[0]) begin #(tDQSQ); dqs_receiver(0); end + always @(dqs_in[1]) begin #(tDQSQ); dqs_receiver(1); end + always @(dqs_in[2]) begin #(tDQSQ); dqs_receiver(2); end + always @(dqs_in[3]) begin #(tDQSQ); dqs_receiver(3); end + always @(dqs_in[4]) begin #(tDQSQ); dqs_receiver(4); end + always @(dqs_in[5]) begin #(tDQSQ); dqs_receiver(5); end + always @(dqs_in[6]) begin #(tDQSQ); dqs_receiver(6); end + always @(dqs_in[7]) begin #(tDQSQ); dqs_receiver(7); end + + task dqs_receiver; + input i; + integer i; + begin + if (dqs_in[i]) begin + case (i) + 0: dq_in_pos[ 7: 0] <= dq_in[ 7: 0]; + 1: dq_in_pos[15: 8] <= dq_in[15: 8]; +/* 2: dq_in_pos[23:16] <= dq_in[23:16]; + 3: dq_in_pos[31:24] <= dq_in[31:24]; + 4: dq_in_pos[39:32] <= dq_in[39:32]; + 5: dq_in_pos[47:40] <= dq_in[47:40]; + 6: dq_in_pos[55:48] <= dq_in[55:48]; + 7: dq_in_pos[63:56] <= dq_in[63:56];*/ + endcase + end else if (!dqs_in[i]) begin + case (i) + 0: dq_in_neg[ 7: 0] <= dq_in[ 7: 0]; + 1: dq_in_neg[15: 8] <= dq_in[15: 8]; +/* 2: dq_in_neg[23:16] <= dq_in[23:16]; + 3: dq_in_neg[31:24] <= dq_in[31:24]; + 4: dq_in_pos[39:32] <= dq_in[39:32]; + 5: dq_in_pos[47:40] <= dq_in[47:40]; + 6: dq_in_pos[55:48] <= dq_in[55:48]; + 7: dq_in_pos[63:56] <= dq_in[63:56];*/ + endcase + end + end + endtask + + + // perform data verification as a result of read_verify task call + always @(clk) begin : data_verify + integer i; + reg [DM_BITS-1 : 0] data_mask; + reg [8*DM_BITS-1 : 0] bit_mask; + + for (i=0; i<=14; i=i+1) begin + dm_fifo[i] = dm_fifo[i+1]; + dq_fifo[i] = dq_fifo[i+1]; + end + dm_fifo[13] = 'bz; + dq_fifo[13] = 'bz; +// dm_fifo[30] = 0; +// dq_fifo[30] = 0; + data_mask = dm_fifo[0]; + + data_mask = dm_fifo[0]; + for (i=0; i>> Shamt; + AluOp_Srav : Result <= Bs >>> As[4:0]; + AluOp_Srl : Result <= B >> Shamt; + AluOp_Srlv : Result <= B >> A[4:0]; + AluOp_Sub : Result <= AddSub_Result; + AluOp_Subu : Result <= AddSub_Result; + AluOp_Xor : Result <= A ^ B; + default : Result <= 32'bx; + endcase + end + + + always @(posedge clock) begin + if (reset) begin + HILO <= 64'h00000000_00000000; + end + else if (Div_Commit) begin + HILO <= {Remainder, Quotient}; + end + else if (HILO_Commit) begin + case (Operation) + AluOp_Mult : HILO <= Mult_Result; + AluOp_Multu : HILO <= Multu_Result; + AluOp_Madd : HILO <= HILO + Mult_Result; + AluOp_Maddu : HILO <= HILO + Multu_Result; + AluOp_Msub : HILO <= HILO - Mult_Result; + AluOp_Msubu : HILO <= HILO - Multu_Result; + AluOp_Mthi : HILO <= {A, LO}; + AluOp_Mtlo : HILO <= {HI, B}; + default : HILO <= HILO; + endcase + end + else begin + HILO <= HILO; + end + end + + // Detect accesses to HILO. RAW and WAW hazards are possible while a + // divide operation is computing, so reads and writes to HILO must stall + // while the divider is busy. + // (This logic could be put into an earlier pipeline stage or into the + // datapath bits to improve timing.) + always @(Operation) begin + case (Operation) + AluOp_Div : HILO_Access <= 1; + AluOp_Divu : HILO_Access <= 1; + AluOp_Mfhi : HILO_Access <= 1; + AluOp_Mflo : HILO_Access <= 1; + AluOp_Mult : HILO_Access <= 1; + AluOp_Multu : HILO_Access <= 1; + AluOp_Madd : HILO_Access <= 1; + AluOp_Maddu : HILO_Access <= 1; + AluOp_Msub : HILO_Access <= 1; + AluOp_Msubu : HILO_Access <= 1; + AluOp_Mthi : HILO_Access <= 1; + AluOp_Mtlo : HILO_Access <= 1; + default : HILO_Access <= 0; + endcase + end + + // Divider FSM: The divide unit is either available or busy. + always @(posedge clock) begin + if (reset) begin + div_fsm <= 2'd0; + end + else begin + case (div_fsm) + 1'd0 : div_fsm <= (DivOp & HILO_Commit) ? 1'd1 : 1'd0; + 1'd1 : div_fsm <= (~Div_Stall) ? 1'd0 : 1'd1; + endcase + end + end + + // Detect overflow for signed operations. Note that MIPS32 has no overflow + // detection for multiplication/division operations. + always @(*) begin + case (Operation) + AluOp_Add : EXC_Ov <= ((A[31] ~^ B[31]) & (A[31] ^ AddSub_Result[31])); + AluOp_Sub : EXC_Ov <= ((A[31] ^ B[31]) & (A[31] ^ AddSub_Result[31])); + default : EXC_Ov <= 0; + endcase + end + + // Count Leading Ones + always @(A) begin + casex (A) + 32'b0xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd0; + 32'b10xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd1; + 32'b110x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd2; + 32'b1110_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd3; + 32'b1111_0xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd4; + 32'b1111_10xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd5; + 32'b1111_110x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd6; + 32'b1111_1110_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd7; + 32'b1111_1111_0xxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd8; + 32'b1111_1111_10xx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd9; + 32'b1111_1111_110x_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd10; + 32'b1111_1111_1110_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd11; + 32'b1111_1111_1111_0xxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd12; + 32'b1111_1111_1111_10xx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd13; + 32'b1111_1111_1111_110x_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd14; + 32'b1111_1111_1111_1110_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd15; + 32'b1111_1111_1111_1111_0xxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd16; + 32'b1111_1111_1111_1111_10xx_xxxx_xxxx_xxxx : CLO_Result <= 6'd17; + 32'b1111_1111_1111_1111_110x_xxxx_xxxx_xxxx : CLO_Result <= 6'd18; + 32'b1111_1111_1111_1111_1110_xxxx_xxxx_xxxx : CLO_Result <= 6'd19; + 32'b1111_1111_1111_1111_1111_0xxx_xxxx_xxxx : CLO_Result <= 6'd20; + 32'b1111_1111_1111_1111_1111_10xx_xxxx_xxxx : CLO_Result <= 6'd21; + 32'b1111_1111_1111_1111_1111_110x_xxxx_xxxx : CLO_Result <= 6'd22; + 32'b1111_1111_1111_1111_1111_1110_xxxx_xxxx : CLO_Result <= 6'd23; + 32'b1111_1111_1111_1111_1111_1111_0xxx_xxxx : CLO_Result <= 6'd24; + 32'b1111_1111_1111_1111_1111_1111_10xx_xxxx : CLO_Result <= 6'd25; + 32'b1111_1111_1111_1111_1111_1111_110x_xxxx : CLO_Result <= 6'd26; + 32'b1111_1111_1111_1111_1111_1111_1110_xxxx : CLO_Result <= 6'd27; + 32'b1111_1111_1111_1111_1111_1111_1111_0xxx : CLO_Result <= 6'd28; + 32'b1111_1111_1111_1111_1111_1111_1111_10xx : CLO_Result <= 6'd29; + 32'b1111_1111_1111_1111_1111_1111_1111_110x : CLO_Result <= 6'd30; + 32'b1111_1111_1111_1111_1111_1111_1111_1110 : CLO_Result <= 6'd31; + 32'b1111_1111_1111_1111_1111_1111_1111_1111 : CLO_Result <= 6'd32; + default : CLO_Result <= 6'd0; + endcase + end + + // Count Leading Zeros + always @(A) begin + casex (A) + 32'b1xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd0; + 32'b01xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd1; + 32'b001x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd2; + 32'b0001_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd3; + 32'b0000_1xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd4; + 32'b0000_01xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd5; + 32'b0000_001x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd6; + 32'b0000_0001_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd7; + 32'b0000_0000_1xxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd8; + 32'b0000_0000_01xx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd9; + 32'b0000_0000_001x_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd10; + 32'b0000_0000_0001_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd11; + 32'b0000_0000_0000_1xxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd12; + 32'b0000_0000_0000_01xx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd13; + 32'b0000_0000_0000_001x_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd14; + 32'b0000_0000_0000_0001_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd15; + 32'b0000_0000_0000_0000_1xxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd16; + 32'b0000_0000_0000_0000_01xx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd17; + 32'b0000_0000_0000_0000_001x_xxxx_xxxx_xxxx : CLZ_Result <= 6'd18; + 32'b0000_0000_0000_0000_0001_xxxx_xxxx_xxxx : CLZ_Result <= 6'd19; + 32'b0000_0000_0000_0000_0000_1xxx_xxxx_xxxx : CLZ_Result <= 6'd20; + 32'b0000_0000_0000_0000_0000_01xx_xxxx_xxxx : CLZ_Result <= 6'd21; + 32'b0000_0000_0000_0000_0000_001x_xxxx_xxxx : CLZ_Result <= 6'd22; + 32'b0000_0000_0000_0000_0000_0001_xxxx_xxxx : CLZ_Result <= 6'd23; + 32'b0000_0000_0000_0000_0000_0000_1xxx_xxxx : CLZ_Result <= 6'd24; + 32'b0000_0000_0000_0000_0000_0000_01xx_xxxx : CLZ_Result <= 6'd25; + 32'b0000_0000_0000_0000_0000_0000_001x_xxxx : CLZ_Result <= 6'd26; + 32'b0000_0000_0000_0000_0000_0000_0001_xxxx : CLZ_Result <= 6'd27; + 32'b0000_0000_0000_0000_0000_0000_0000_1xxx : CLZ_Result <= 6'd28; + 32'b0000_0000_0000_0000_0000_0000_0000_01xx : CLZ_Result <= 6'd29; + 32'b0000_0000_0000_0000_0000_0000_0000_001x : CLZ_Result <= 6'd30; + 32'b0000_0000_0000_0000_0000_0000_0000_0001 : CLZ_Result <= 6'd31; + 32'b0000_0000_0000_0000_0000_0000_0000_0000 : CLZ_Result <= 6'd32; + default : CLZ_Result <= 6'd0; + endcase + end + + // Multicycle divide unit + Divide Divider ( + .clock (clock), + .reset (reset), + .OP_div (Div_Start), + .OP_divu (Divu_Start), + .Dividend (A), + .Divisor (B), + .Quotient (Quotient), + .Remainder (Remainder), + .Stall (Div_Stall) + ); + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/Add.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/Add.v new file mode 100755 index 0000000..859cd40 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/Add.v @@ -0,0 +1,26 @@ +`timescale 1ns / 1ps +/* + * File : Add.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 7-Jun-2011 GEA Initial design. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * A simple 32-bit 2-input adder. + */ +module Add( + input [31:0] A, + input [31:0] B, + output [31:0] C + ); + + assign C = (A + B); + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/CPZero.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/CPZero.v new file mode 100755 index 0000000..84d18c9 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/CPZero.v @@ -0,0 +1,529 @@ +`timescale 1ns / 1ps +/* + * File : CPZero.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 16-Sep-2011 GEA Initial design. + * 2.0 14-May-2012 GEA Complete rework. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * The MIPS-32 Coprocessor 0 (CP0). This is the processor management unit that allows + * interrupts, traps, system calls, and other exceptions. It distinguishes + * user and kernel modes, provides status information, and can override program + * flow. This processor is designed for "bare metal" memory access and thus does + * not have virtual memory hardware as a part of it. However, the subset of CP0 + * is MIPS-32-compliant. + */ +module CPZero( + input clock, + //-- CP0 Functionality --// + input Mfc0, // CPU instruction is Mfc0 + input Mtc0, // CPU instruction is Mtc0 + input IF_Stall, + input ID_Stall, // Commits are not made during stalls + input COP1, // Instruction for Coprocessor 1 + input COP2, // Instruction for Coprocessor 2 + input COP3, // Instruction for Coprocessor 3 + input ERET, // Instruction is ERET (Exception Return) + input [4:0] Rd, // Specifies Cp0 register + input [2:0] Sel, // Specifies Cp0 'select' + input [31:0] Reg_In, // Data from GP register to replace CP0 register + output reg [31:0] Reg_Out, // Data from CP0 register for GP register + output KernelMode, // Kernel mode indicator for pipeline transit + output ReverseEndian, // Reverse Endian memory indicator for User Mode + //-- Hw Interrupts --// + input [4:0] Int, // Five hardware interrupts external to the processor + //-- Exceptions --// + input reset, // Cold Reset (EXC_Reset) +// input EXC_SReset, // Soft Reset (not implemented) + input EXC_NMI, // Non-Maskable Interrupt + input EXC_AdIF, // Address Error Exception from i-fetch (mapped to AdEL) + input EXC_AdEL, // Address Error Exception from data memory load + input EXC_AdES, // Address Error Exception from data memory store + input EXC_Ov, // Integer Overflow Exception + input EXC_Tr, // Trap Exception + input EXC_Sys, // System Call Exception + input EXC_Bp, // Breakpoint Exception + input EXC_RI, // Reserved Instruction Exception + //-- Exception Data --// + input [31:0] ID_RestartPC, // PC for exception, whether PC of instruction or of branch (PC-4) if BDS + input [31:0] EX_RestartPC, // Same as 'ID_RestartPC' but in EX stage + input [31:0] M_RestartPC, // Same as 'ID_RestartPC' but in MEM stage + input ID_IsFlushed, + input IF_IsBD, // Indicator of IF exception being a branch delay slot instruction + input ID_IsBD, // Indicator of ID exception being a branch delay slot instruction + input EX_IsBD, // Indicator of EX exception being a branch delay slot instruction + input M_IsBD, // Indicator of M exception being a branch delay slot instruction + input [31:0] BadAddr_M, // Bad 'Virtual' Address for exceptions AdEL, AdES in MEM stage + input [31:0] BadAddr_IF, // Bad 'Virtual' Address for AdIF (i.e. AdEL) in IF stage + input ID_CanErr, // Cumulative signal, i.e. (ID_ID_CanErr | ID_EX_CanErr | ID_M_CanErr) + input EX_CanErr, // Cumulative signal, i.e. (EX_EX_CanErr | EX_M_CanErr) + input M_CanErr, // Memory stage can error (i.e. cause exception) + //-- Exception Control Flow --/ + output IF_Exception_Stall, + output ID_Exception_Stall, + output EX_Exception_Stall, + output M_Exception_Stall, + output IF_Exception_Flush, + output ID_Exception_Flush, + output EX_Exception_Flush, + output M_Exception_Flush, + output Exc_PC_Sel, // Mux selector for exception PC override + output reg [31:0] Exc_PC_Out, // Address for PC at the beginning of an exception + output [7:0] IP // Pending Interrupts from Cause register (for diagnostic purposes) + ); + + `include "MIPS_Parameters.v" + + + /*** + Exception Control Flow Notes + + - Exceptions can occur in every pipeline stage. This implies that more than one exception + can be raised in a single cycle. When this occurs, only the forward-most exception + (i.e. MEM over EX) is handled. This and the following note guarantee program order. + + - An exception in any pipeline stage must stall that stage until all following stages are + exception-free. This is because it only makes sense for exceptions to occur in program order. + + - A pipeline stage which causes an exception must flush, i.e. prevent any commits it would + have normally made and convert itself to a NOP for the next pipeline stage. Furthermore, + it must flush all previous pipeline stages as well in order to retain program order. + + - Instructions reading CP0 (mtc0) read in ID without further action. Writes to CP0 (mtc0, + eret) also write in ID, but only after forward pipeline stages have been cleared + of possible exceptions. This prevents many insidious bugs, such as switching to User Mode + in ID when a legitimate memory access in kernel mode is processing in MEM, or conversely + a switch to Kernel Mode in ID when an instruction in User Mode is attempting a kernel region + memory access (when a kernel mode signal does not propagate through the pipeline). + + - Commits occur in ID (CP0), EX (HILO), MEM, and WB (registers). + + - Hardware interrupts are detected and inserted in the ID stage, but only when there are no + other possible exceptions in the pipeline. Because they appear 'asynchronous' to the + processor, the remaining instructions in forward stages (EX, MEM, WB) can either be + flushed or completed. It is simplest to have them complete to avoid restarts, but the + interrupt latency is higher if e.g. the MEM stage stalls on a memory access (this would + be unavoidable on single-cycle processors). This implementation allows all forward instructions + to complete, for a greater instruction throughput but higher interrupt latency. + + - Software interrupts should appear synchronous in the program order, meaning that all + instructions previous to them should complete and no instructions after them should start + until the interrupts has been processed. + + Exception Name Short Name Pipeline Stage + Address Error Ex (AdEL, AdES) MEM, IF + Integer Overflow Ex (Ov) EX + Trap Ex (Tr) MEM + Syscall (Sys) ID + Breakpoint (Bp) ID + Reserved Instruction (RI) ID + Coprocessor Unusable (CpU) ID + Interrupt (Int) ID + Reset, SReset, NMI ID + ***/ + + + // Exceptions Generated Internally + wire EXC_CpU; + + // Hardware Interrupt #5, caused by Timer/Perf counter + wire Int5; + + // Top-level Authoritative Interrupt Signal + wire EXC_Int; + + // General Exception detection (all but Interrupts, Reset, Soft Reset, and NMI) + wire EXC_General = EXC_AdIF | EXC_AdEL | EXC_AdES | EXC_Ov | EXC_Tr | EXC_Sys | EXC_Bp | EXC_RI | EXC_CpU; + + // Misc + wire CP0_WriteCond; + reg [3:0] Cause_ExcCode_bits; + + reg reset_r; + always @(posedge clock) begin + reset_r <= reset; + end + + /*** + MIPS-32 COPROCESSOR 0 (Cp0) REGISTERS + + These are defined in "MIPS32 Architecture for Programmers Volume III: + The MIPS32 Privileged Resource Architecture" from MIPS Technologies, Inc. + + Optional registers are omitted. Changes to the processor (such as adding + an MMU/TLB, etc. must be reflected in these registers. + */ + + // BadVAddr Register (Register 8, Select 0) + reg [31:0] BadVAddr; + + // Count Register (Register 9, Select 0) + reg [31:0] Count; + + // Compare Register (Register 11, Select 0) + reg [31:0] Compare; + + // Status Register (Register 12, Select 0) + wire [2:0] Status_CU_321 = 3'b000; + reg Status_CU_0; // Access Control to CPs, [2]->Cp3, ... [0]->Cp0 + wire Status_RP = 0; + wire Status_FR = 0; + reg Status_RE; // Reverse Endian Memory for User Mode + wire Status_MX = 0; + wire Status_PX = 0; + reg Status_BEV; // Exception vector locations (0->Norm, 1->Bootstrap) + wire Status_TS = 0; + wire Status_SR = 0; // Soft reset not implemented + reg Status_NMI; // Non-Maskable Interrupt + wire Status_RES = 0; + wire [1:0] Status_Custom = 2'b00; + reg [7:0] Status_IM; // Interrupt mask + wire Status_KX = 0; + wire Status_SX = 0; + wire Status_UX = 0; + reg Status_UM; // Base operating mode (0->Kernel, 1->User) + wire Status_R0 = 0; + reg Status_ERL; // Error Level (0->Normal, 1->Error (reset, NMI)) + reg Status_EXL; // Exception level (0->Normal, 1->Exception) + reg Status_IE; // Interrupt Enable + wire [31:0] Status = {Status_CU_321, Status_CU_0, Status_RP, Status_FR, Status_RE, Status_MX, + Status_PX, Status_BEV, Status_TS, Status_SR, Status_NMI, Status_RES, + Status_Custom, Status_IM, Status_KX, Status_SX, Status_UX, + Status_UM, Status_R0, Status_ERL, Status_EXL, Status_IE}; + + // Cause Register (Register 13, Select 0) + reg Cause_BD; // Exception occured in Branch Delay + reg [1:0] Cause_CE; // CP number for CP Unusable exception + reg Cause_IV; // Indicator of general IV (0->0x180) or special IV (1->0x200) + wire Cause_WP = 0; + reg [7:0] Cause_IP; // Pending HW Interrupt indicator. + wire Cause_ExcCode4 = 0; // Can be made into a register when this bit is needed. + reg [3:0] Cause_ExcCode30; // Description of Exception (only lower 4 bits currently used; see above) + wire [31:0] Cause = {Cause_BD, 1'b0, Cause_CE, 4'b0000, Cause_IV, Cause_WP, + 6'b000000, Cause_IP, 1'b0, Cause_ExcCode4, Cause_ExcCode30, 2'b00}; + + // Exception Program Counter (Register 14, Select 0) + reg [31:0] EPC; + + // Processor Identification (Register 15, Select 0) + wire [7:0] ID_Options = 8'b0000_0000; + wire [7:0] ID_CID = 8'b0000_0000; + wire [7:0] ID_PID = 8'b0000_0000; + wire [7:0] ID_Rev = 8'b0000_0001; + wire [31:0] PRId = {ID_Options, ID_CID, ID_PID, ID_Rev}; + + // Configuration Register (Register 16, Select 0) + wire Config_M = 1; + wire [14:0] Config_Impl = 15'b000_0000_0000_0000; + wire Config_BE = Big_Endian; // From parameters file + wire [1:0] Config_AT = 2'b00; + wire [2:0] Config_AR = 3'b000; + wire [2:0] Config_MT = 3'b000; + wire [2:0] Config_K0 = 3'b000; + wire [31:0] Config = {Config_M, Config_Impl, Config_BE, Config_AT, Config_AR, Config_MT, + 4'b0000, Config_K0}; + + // Configuration Register 1 (Register 16, Select 1) + wire Config1_M = 0; + wire [5:0] Config1_MMU = 6'b000000; + wire [2:0] Config1_IS = 3'b000; + wire [2:0] Config1_IL = 3'b000; + wire [2:0] Config1_IA = 3'b000; + wire [2:0] Config1_DS = 3'b000; + wire [2:0] Config1_DL = 3'b000; + wire [2:0] Config1_DA = 3'b000; + wire Config1_C2 = 0; + wire Config1_MD = 0; + wire Config1_PC = 0; // XXX Performance Counters + wire Config1_WR = 0; // XXX Watch Registers + wire Config1_CA = 0; + wire Config1_EP = 0; + wire Config1_FP = 0; + wire [31:0] Config1 = {Config1_M, Config1_MMU, Config1_IS, Config1_IL, Config1_IA, + Config1_DS, Config1_DL, Config1_DA, Config1_C2, + Config1_MD, Config1_PC, Config1_WR, Config1_CA, + Config1_EP, Config1_FP}; + + // Performance Counter Register (Register 25) XXX TODO + + // ErrorEPC Register (Register 30, Select 0) + reg [31:0] ErrorEPC; + + // Exception Detection and Processing + wire M_Exception_Detect, EX_Exception_Detect, ID_Exception_Detect, IF_Exception_Detect; + wire M_Exception_Mask, EX_Exception_Mask, ID_Exception_Mask, IF_Exception_Mask; + wire M_Exception_Ready, EX_Exception_Ready, ID_Exception_Ready, IF_Exception_Ready; + + assign IP = Cause_IP; + + /*** Coprocessor Unusable Exception ***/ + assign EXC_CpU = COP1 | COP2 | COP3 | ((Mtc0 | Mfc0 | ERET) & ~(Status_CU_0 | KernelMode)); + + /*** Kernel Mode Signal ***/ + assign KernelMode = ~Status_UM | Status_EXL | Status_ERL; + + /*** Reverse Endian for User Mode ***/ + assign ReverseEndian = Status_RE; + + /*** Interrupts ***/ + assign Int5 = (Count == Compare); + //assign EXC_Int = ((Cause_IP[7:0] & Status_IM[7:0]) != 8'h00) & Status_IE & ~Status_EXL & ~Status_ERL & ~ID_IsFlushed; + wire Enabled_Interrupt = EXC_NMI | (Status_IE & ((Cause_IP[7:0] & Status_IM[7:0]) != 8'h00)); + assign EXC_Int = Enabled_Interrupt & ~Status_EXL & ~Status_ERL & ~ID_IsFlushed; + + assign CP0_WriteCond = (Status_CU_0 | KernelMode) & Mtc0 & ~ID_Stall; + + + /*** + Exception Hazard Flow Control Explanation: + - An exception at any time in any stage causes its own and any previous stages to + flush (clear own commits, NOPS to fwd stages). + - An exception in a stage can also stall that stage (and inherently all previous stages) if and only if: + 1. A forward stage is capable of causing an exception AND + 2. A forward stage is not currently causing an exception. + - An exception is ready to process when it is detected and not stalled in a stage. + + Flush specifics per pipeline stage: + MEM: Mask 'MemWrite' and 'MemRead' (for performance) after EX/M and before data memory. NOPs to M/WB. + EX : Mask writes to HI/LO. NOPs to EX/M. + ID : Mask writes (reads?) to CP0. NOPs to ID/EX. + IF : NOP to IF/ID. + ***/ + + /*** Exceptions grouped by pipeline stage ***/ + assign M_Exception_Detect = EXC_AdEL | EXC_AdES | EXC_Tr; + assign EX_Exception_Detect = EXC_Ov; + assign ID_Exception_Detect = EXC_Sys | EXC_Bp | EXC_RI | EXC_CpU | EXC_Int; + assign IF_Exception_Detect = EXC_AdIF; + + /*** Exception mask conditions ***/ + + // A potential bug would occur if e.g. EX stalls, MEM has data, but MEM is not stalled and finishes + // going through the pipeline so forwarding would fail. This is not a problem however because + // EX would not need data since it would flush on an exception. + assign M_Exception_Mask = IF_Stall; + assign EX_Exception_Mask = IF_Stall | M_CanErr; + assign ID_Exception_Mask = IF_Stall | M_CanErr | EX_CanErr; + assign IF_Exception_Mask = M_CanErr | EX_CanErr | ID_CanErr | EXC_Int; + + /*** + Exceptions which must wait for forward stages. A stage will not stall if a forward stage has an exception. + These stalls must be inserted as stall conditions in the hazard unit so that it will take care of chaining. + All writes to CP0 must also wait for forward hazard conditions to clear. + */ + assign M_Exception_Stall = M_Exception_Detect & M_Exception_Mask; + assign EX_Exception_Stall = EX_Exception_Detect & EX_Exception_Mask & ~M_Exception_Detect; + assign ID_Exception_Stall = (ID_Exception_Detect | ERET | Mtc0) & ID_Exception_Mask & ~(EX_Exception_Detect | M_Exception_Detect); + assign IF_Exception_Stall = IF_Exception_Detect & IF_Exception_Mask & ~(ID_Exception_Detect | EX_Exception_Detect | M_Exception_Detect); + + + /*** Exceptions which are ready to process (mutually exclusive) ***/ + // XXX can remove ~ID_Stall since in mask now (?) + assign M_Exception_Ready = ~ID_Stall & M_Exception_Detect & ~M_Exception_Mask; + assign EX_Exception_Ready = ~ID_Stall & EX_Exception_Detect & ~EX_Exception_Mask; + assign ID_Exception_Ready = ~ID_Stall & ID_Exception_Detect & ~ID_Exception_Mask; + assign IF_Exception_Ready = ~ID_Stall & IF_Exception_Detect & ~IF_Exception_Mask; + + /*** + Flushes. A flush clears a pipeline stage's control signals and prevents the stage from committing any changes. + Data such as 'RestartPC' and the detected exception must remain. + */ + assign M_Exception_Flush = M_Exception_Detect; + assign EX_Exception_Flush = M_Exception_Detect | EX_Exception_Detect; + assign ID_Exception_Flush = M_Exception_Detect | EX_Exception_Detect | ID_Exception_Detect; + assign IF_Exception_Flush = M_Exception_Detect | EX_Exception_Detect | ID_Exception_Detect | IF_Exception_Detect | (ERET & ~ID_Stall) | reset_r; + + + /*** Software reads of CP0 Registers ***/ + always @(*) begin + if (Mfc0 & (Status_CU_0 | KernelMode)) begin + case (Rd) + 5'd8 : Reg_Out <= BadVAddr; + 5'd9 : Reg_Out <= Count; + 5'd11 : Reg_Out <= Compare; + 5'd12 : Reg_Out <= Status; + 5'd13 : Reg_Out <= Cause; + 5'd14 : Reg_Out <= EPC; + 5'd15 : Reg_Out <= PRId; + 5'd16 : Reg_Out <= (Sel == 3'b000) ? Config : Config1; + 5'd30 : Reg_Out <= ErrorEPC; + default : Reg_Out <= 32'h0000_0000; + endcase + end + else begin + Reg_Out <= 32'h0000_0000; + end + end + + /*** Cp0 Register Assignments: Non-general exceptions (Reset, Soft Reset, NMI...) ***/ + always @(posedge clock) begin + if (reset) begin + Status_BEV <= 1; + Status_NMI <= 0; + Status_ERL <= 1; + ErrorEPC <= 32'b0; + end + else if (ID_Exception_Ready & EXC_NMI) begin + Status_BEV <= 1; + Status_NMI <= 1; + Status_ERL <= 1; + ErrorEPC <= ID_RestartPC; + end + else begin + Status_BEV <= (CP0_WriteCond & (Rd == 5'd12) & (Sel == 3'b000)) ? Reg_In[22] : Status_BEV; + Status_NMI <= (CP0_WriteCond & (Rd == 5'd12) & (Sel == 3'b000)) ? Reg_In[19] : Status_NMI; + Status_ERL <= (CP0_WriteCond & (Rd == 5'd12) & (Sel == 3'b000)) ? Reg_In[2] : ((Status_ERL & ERET & ~ID_Stall) ? 0 : Status_ERL); + ErrorEPC <= (CP0_WriteCond & (Rd == 5'd30) & (Sel == 3'b000)) ? Reg_In : ErrorEPC; + end + end + + /*** Cp0 Register Assignments: All other registers ***/ + always @(posedge clock) begin + if (reset) begin + Count <= 32'b0; + Compare <= 32'b0; + Status_CU_0 <= 0; + Status_RE <= 0; + Status_IM <= 8'b0; + Status_UM <= 0; + Status_IE <= 0; + Cause_IV <= 0; + Cause_IP <= 8'b0; + end + else begin + Count <= (CP0_WriteCond & (Rd == 5'd9 ) & (Sel == 3'b000)) ? Reg_In : ((Count == Compare) ? 32'b0 : Count + 1); + Compare <= (CP0_WriteCond & (Rd == 5'd11) & (Sel == 3'b000)) ? Reg_In : Compare; + Status_CU_0 <= (CP0_WriteCond & (Rd == 5'd12) & (Sel == 3'b000)) ? Reg_In[28] : Status_CU_0; + Status_RE <= (CP0_WriteCond & (Rd == 5'd12) & (Sel == 3'b000)) ? Reg_In[25] : Status_RE; + Status_IM <= (CP0_WriteCond & (Rd == 5'd12) & (Sel == 3'b000)) ? Reg_In[15:8] : Status_IM; + Status_UM <= (CP0_WriteCond & (Rd == 5'd12) & (Sel == 3'b000)) ? Reg_In[4] : Status_UM; + Status_IE <= (CP0_WriteCond & (Rd == 5'd12) & (Sel == 3'b000)) ? Reg_In[0] : Status_IE; + Cause_IV <= (CP0_WriteCond & (Rd == 5'd13) & (Sel == 3'b000)) ? Reg_In[23] : Cause_IV; + /* Cause_IP indicates 8 interrupts: + [7] is set by the timer comparison, and cleared by reading 'Count'. + [6:2] are set and cleared by external hardware. + [1:0] are set and cleared by software. + */ + // If reading -> 0, Otherwise if 0 -> Int5. + Cause_IP[7] <= ((Status_CU_0 | KernelMode) & Mfc0 & (Rd == 5'd9) & (Sel == 3'b000)) ? 0 : ((Cause_IP[7] == 0) ? Int5 : Cause_IP[7]); + Cause_IP[6:2] <= Int[4:0]; + Cause_IP[1:0] <= (CP0_WriteCond & (Rd == 5'd13) & (Sel == 3'b000)) ? Reg_In[9:8] : Cause_IP[1:0]; + end + end + + /*** Cp0 Register Assignments: General Exception and Interrupt Processing ***/ + always @(posedge clock) begin + if (reset) begin + Cause_BD <= 0; + Cause_CE <= 2'b00; + Cause_ExcCode30 <= 4'b0000; + Status_EXL <= 0; + EPC <= 32'h0; + BadVAddr <= 32'h0; + end + else begin + // MEM stage + if (M_Exception_Ready) begin + Cause_BD <= (Status_EXL) ? Cause_BD : M_IsBD; + Cause_CE <= (COP3) ? 2'b11 : ((COP2) ? 2'b10 : ((COP1) ? 2'b01 : 2'b00)); + Cause_ExcCode30 <= Cause_ExcCode_bits; + Status_EXL <= 1; + EPC <= (Status_EXL) ? EPC : M_RestartPC; + BadVAddr <= BadAddr_M; + end + // EX stage + else if (EX_Exception_Ready) begin + Cause_BD <= (Status_EXL) ? Cause_BD : EX_IsBD; + Cause_CE <= (COP3) ? 2'b11 : ((COP2) ? 2'b10 : ((COP1) ? 2'b01 : 2'b00)); + Cause_ExcCode30 <= Cause_ExcCode_bits; + Status_EXL <= 1; + EPC <= (Status_EXL) ? EPC : EX_RestartPC; + BadVAddr <= BadVAddr; + end + // ID stage + else if (ID_Exception_Ready) begin + Cause_BD <= (Status_EXL) ? Cause_BD : ID_IsBD; + Cause_CE <= (COP3) ? 2'b11 : ((COP2) ? 2'b10 : ((COP1) ? 2'b01 : 2'b00)); + Cause_ExcCode30 <= Cause_ExcCode_bits; + Status_EXL <= 1; + EPC <= (Status_EXL) ? EPC : ID_RestartPC; + BadVAddr <= BadVAddr; + end + // IF stage + else if (IF_Exception_Ready) begin + Cause_BD <= (Status_EXL) ? Cause_BD : IF_IsBD; + Cause_CE <= (COP3) ? 2'b11 : ((COP2) ? 2'b10 : ((COP1) ? 2'b01 : 2'b00)); + Cause_ExcCode30 <= Cause_ExcCode_bits; + Status_EXL <= 1; + EPC <= (Status_EXL) ? EPC : BadAddr_IF; + BadVAddr <= BadAddr_IF; + end + // No exceptions this cycle + else begin + Cause_BD <= 1'b0; + Cause_CE <= Cause_CE; + Cause_ExcCode30 <= Cause_ExcCode30; + // Without new exceptions, 'Status_EXL' is set by software or cleared by ERET. + Status_EXL <= (CP0_WriteCond & (Rd == 5'd12) & (Sel == 3'b000)) ? Reg_In[1] : ((Status_EXL & ERET & ~ID_Stall) ? 0 : Status_EXL); + // The EPC is also writable by software + EPC <= (CP0_WriteCond & (Rd == 5'd14) & (Sel == 3'b000)) ? Reg_In : EPC; + BadVAddr <= BadVAddr; + end + end + end + + + /*** Program Counter for all Exceptions/Interrupts ***/ + always @(*) begin + // Following is redundant since PC has initial value now. + if (reset) begin + Exc_PC_Out <= EXC_Vector_Base_Reset; + end + else if (ERET & ~ID_Stall) begin + Exc_PC_Out <= (Status_ERL) ? ErrorEPC : EPC; + end + else if (EXC_General) begin + Exc_PC_Out <= (Status_BEV) ? (EXC_Vector_Base_Other_Boot + EXC_Vector_Offset_General) : + (EXC_Vector_Base_Other_NoBoot + EXC_Vector_Offset_General); + end + else if (EXC_NMI) begin + Exc_PC_Out <= EXC_Vector_Base_Reset; + end + else if (EXC_Int & Cause_IV) begin + Exc_PC_Out <= (Status_BEV) ? (EXC_Vector_Base_Other_Boot + EXC_Vector_Offset_Special) : + (EXC_Vector_Base_Other_NoBoot + EXC_Vector_Offset_Special); + end + else begin + Exc_PC_Out <= (Status_BEV) ? (EXC_Vector_Base_Other_Boot + EXC_Vector_Offset_General) : + (EXC_Vector_Base_Other_NoBoot + EXC_Vector_Offset_General); + end + end + + //assign Exc_PC_Sel = (reset | (ERET & ~ID_Stall) | EXC_General | EXC_Int); + assign Exc_PC_Sel = reset | (ERET & ~ID_Stall) | IF_Exception_Ready | ID_Exception_Ready | EX_Exception_Ready | M_Exception_Ready; + + /*** Cause Register ExcCode Field ***/ + always @(*) begin + // Ordered by Pipeline Stage with Interrupts last + if (EXC_AdEL) Cause_ExcCode_bits <= 4'h4; // 00100 + else if (EXC_AdES) Cause_ExcCode_bits <= 4'h5; // 00101 + else if (EXC_Tr) Cause_ExcCode_bits <= 4'hd; // 01101 + else if (EXC_Ov) Cause_ExcCode_bits <= 4'hc; // 01100 + else if (EXC_Sys) Cause_ExcCode_bits <= 4'h8; // 01000 + else if (EXC_Bp) Cause_ExcCode_bits <= 4'h9; // 01001 + else if (EXC_RI) Cause_ExcCode_bits <= 4'ha; // 01010 + else if (EXC_CpU) Cause_ExcCode_bits <= 4'hb; // 01011 + else if (EXC_AdIF) Cause_ExcCode_bits <= 4'h4; // 00100 + else if (EXC_Int) Cause_ExcCode_bits <= 4'h0; // 00000 // OK that NMI writes this. + else Cause_ExcCode_bits <= 4'bxxxx; + end + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/Compare.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/Compare.v new file mode 100755 index 0000000..6ec671a --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/Compare.v @@ -0,0 +1,41 @@ +`timescale 1ns / 1ps +/* + * File : Compare.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 15-Jun-2011 GEA Initial design. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * Compares two 32-bit values and outputs the following information about them: + * EQ : A and B are equal + * GZ : A is greater than zero + * LZ : A is less than zero + * GEZ : A is greater than or equal to zero + * LEZ : A is less than or equal to zero + */ +module Compare( + input [31:0] A, + input [31:0] B, + output EQ, + output GZ, + output LZ, + output GEZ, + output LEZ + ); + + wire ZeroA = (A == 32'b0); + + assign EQ = ( A == B); + assign GZ = (~A[31] & ~ZeroA); + assign LZ = A[31]; + assign GEZ = ~A[31]; + assign LEZ = ( A[31] | ZeroA); + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/Control.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/Control.v new file mode 100755 index 0000000..058d937 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/Control.v @@ -0,0 +1,509 @@ + `timescale 1ns / 1ps +/* + * File : Control.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 7-Jun-2011 GEA Initial design. + * 2.0 26-May-2012 GEA Release version with CP0. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * The Datapath Controller. This module sets the datapath control + * bits for an incoming instruction. These control bits follow the + * instruction through each pipeline stage as needed, and constitute + * the effective operation of the processor through each pipeline stage. + */ +module Control( + input ID_Stall, + input [5:0] OpCode, + input [5:0] Funct, + input [4:0] Rs, // used to differentiate mfc0 and mtc0 + input [4:0] Rt, // used to differentiate bgez,bgezal,bltz,bltzal,teqi,tgei,tgeiu,tlti,tltiu,tnei + input Cmp_EQ, + input Cmp_GZ, + input Cmp_GEZ, + input Cmp_LZ, + input Cmp_LEZ, + //------------ + output IF_Flush, + output reg [7:0] DP_Hazards, + output [1:0] PCSrc, + output SignExtend, + output Link, + output Movn, + output Movz, + output Mfc0, + output Mtc0, + output CP1, + output CP2, + output CP3, + output Eret, + output Trap, + output TrapCond, + output EXC_Sys, + output EXC_Bp, + output EXC_RI, + output ID_CanErr, + output EX_CanErr, + output M_CanErr, + output NextIsDelay, + output RegDst, + output ALUSrcImm, + output reg [4:0] ALUOp, + output LLSC, + output MemWrite, + output MemRead, + output MemByte, + output MemHalf, + output MemSignExtend, + output Left, + output Right, + output RegWrite, + output MemtoReg + ); + + `include "MIPS_Parameters.v" + + wire Movc; + wire Branch, Branch_EQ, Branch_GTZ, Branch_LEZ, Branch_NEQ, Branch_GEZ, Branch_LTZ; + wire Unaligned_Mem; + + reg [15:0] Datapath; + assign PCSrc[0] = Datapath[14]; + assign Link = Datapath[13]; + assign ALUSrcImm = Datapath[12]; + assign Movc = Datapath[11]; + assign Trap = Datapath[10]; + assign TrapCond = Datapath[9]; + assign RegDst = Datapath[8]; + assign LLSC = Datapath[7]; + assign MemRead = Datapath[6]; + assign MemWrite = Datapath[5]; + assign MemHalf = Datapath[4]; + assign MemByte = Datapath[3]; + assign MemSignExtend = Datapath[2]; + assign RegWrite = Datapath[1]; + assign MemtoReg = Datapath[0]; + + reg [2:0] DP_Exceptions; + assign ID_CanErr = DP_Exceptions[2]; + assign EX_CanErr = DP_Exceptions[1]; + assign M_CanErr = DP_Exceptions[0]; + + // Set the main datapath control signals based on the Op Code + always @(*) begin + if (ID_Stall) + Datapath <= DP_None; + else begin + case (OpCode) + // R-Type + Op_Type_R : + begin + case (Funct) + Funct_Add : Datapath <= DP_Add; + Funct_Addu : Datapath <= DP_Addu; + Funct_And : Datapath <= DP_And; + Funct_Break : Datapath <= DP_Break; + Funct_Div : Datapath <= DP_Div; + Funct_Divu : Datapath <= DP_Divu; + Funct_Jalr : Datapath <= DP_Jalr; + Funct_Jr : Datapath <= DP_Jr; + Funct_Mfhi : Datapath <= DP_Mfhi; + Funct_Mflo : Datapath <= DP_Mflo; + Funct_Movn : Datapath <= DP_Movn; + Funct_Movz : Datapath <= DP_Movz; + Funct_Mthi : Datapath <= DP_Mthi; + Funct_Mtlo : Datapath <= DP_Mtlo; + Funct_Mult : Datapath <= DP_Mult; + Funct_Multu : Datapath <= DP_Multu; + Funct_Nor : Datapath <= DP_Nor; + Funct_Or : Datapath <= DP_Or; + Funct_Sll : Datapath <= DP_Sll; + Funct_Sllv : Datapath <= DP_Sllv; + Funct_Slt : Datapath <= DP_Slt; + Funct_Sltu : Datapath <= DP_Sltu; + Funct_Sra : Datapath <= DP_Sra; + Funct_Srav : Datapath <= DP_Srav; + Funct_Srl : Datapath <= DP_Srl; + Funct_Srlv : Datapath <= DP_Srlv; + Funct_Sub : Datapath <= DP_Sub; + Funct_Subu : Datapath <= DP_Subu; + Funct_Syscall : Datapath <= DP_Syscall; + Funct_Teq : Datapath <= DP_Teq; + Funct_Tge : Datapath <= DP_Tge; + Funct_Tgeu : Datapath <= DP_Tgeu; + Funct_Tlt : Datapath <= DP_Tlt; + Funct_Tltu : Datapath <= DP_Tltu; + Funct_Tne : Datapath <= DP_Tne; + Funct_Xor : Datapath <= DP_Xor; + default : Datapath <= DP_None; + endcase + end + // R2-Type + Op_Type_R2 : + begin + case (Funct) + Funct_Clo : Datapath <= DP_Clo; + Funct_Clz : Datapath <= DP_Clz; + Funct_Madd : Datapath <= DP_Madd; + Funct_Maddu : Datapath <= DP_Maddu; + Funct_Msub : Datapath <= DP_Msub; + Funct_Msubu : Datapath <= DP_Msubu; + Funct_Mul : Datapath <= DP_Mul; + default : Datapath <= DP_None; + endcase + end + // I-Type + Op_Addi : Datapath <= DP_Addi; + Op_Addiu : Datapath <= DP_Addiu; + Op_Andi : Datapath <= DP_Andi; + Op_Ori : Datapath <= DP_Ori; + Op_Pref : Datapath <= DP_Pref; + Op_Slti : Datapath <= DP_Slti; + Op_Sltiu : Datapath <= DP_Sltiu; + Op_Xori : Datapath <= DP_Xori; + // Jumps (using immediates) + Op_J : Datapath <= DP_J; + Op_Jal : Datapath <= DP_Jal; + // Branches and Traps + Op_Type_BI : + begin + case (Rt) + OpRt_Bgez : Datapath <= DP_Bgez; + OpRt_Bgezal : Datapath <= DP_Bgezal; + OpRt_Bltz : Datapath <= DP_Bltz; + OpRt_Bltzal : Datapath <= DP_Bltzal; + OpRt_Teqi : Datapath <= DP_Teqi; + OpRt_Tgei : Datapath <= DP_Tgei; + OpRt_Tgeiu : Datapath <= DP_Tgeiu; + OpRt_Tlti : Datapath <= DP_Tlti; + OpRt_Tltiu : Datapath <= DP_Tltiu; + OpRt_Tnei : Datapath <= DP_Tnei; + default : Datapath <= DP_None; + endcase + end + Op_Beq : Datapath <= DP_Beq; + Op_Bgtz : Datapath <= DP_Bgtz; + Op_Blez : Datapath <= DP_Blez; + Op_Bne : Datapath <= DP_Bne; + // Coprocessor 0 + Op_Type_CP0 : + begin + case (Rs) + OpRs_MF : Datapath <= DP_Mfc0; + OpRs_MT : Datapath <= DP_Mtc0; + OpRs_ERET : Datapath <= (Funct == Funct_ERET) ? DP_Eret : DP_None; + default : Datapath <= DP_None; + endcase + end + // Memory + Op_Lb : Datapath <= DP_Lb; + Op_Lbu : Datapath <= DP_Lbu; + Op_Lh : Datapath <= DP_Lh; + Op_Lhu : Datapath <= DP_Lhu; + Op_Ll : Datapath <= DP_Ll; + Op_Lui : Datapath <= DP_Lui; + Op_Lw : Datapath <= DP_Lw; + Op_Lwl : Datapath <= DP_Lwl; + Op_Lwr : Datapath <= DP_Lwr; + Op_Sb : Datapath <= DP_Sb; + Op_Sc : Datapath <= DP_Sc; + Op_Sh : Datapath <= DP_Sh; + Op_Sw : Datapath <= DP_Sw; + Op_Swl : Datapath <= DP_Swl; + Op_Swr : Datapath <= DP_Swr; + default : Datapath <= DP_None; + endcase + end + end + + // Set the Hazard Control Signals and Exception Indicators based on the Op Code + always @(*) begin + case (OpCode) + // R-Type + Op_Type_R : + begin + case (Funct) + Funct_Add : begin DP_Hazards <= HAZ_Add; DP_Exceptions <= EXC_Add; end + Funct_Addu : begin DP_Hazards <= HAZ_Addu; DP_Exceptions <= EXC_Addu; end + Funct_And : begin DP_Hazards <= HAZ_And; DP_Exceptions <= EXC_And; end + Funct_Break : begin DP_Hazards <= HAZ_Break; DP_Exceptions <= EXC_Break; end + Funct_Div : begin DP_Hazards <= HAZ_Div; DP_Exceptions <= EXC_Div; end + Funct_Divu : begin DP_Hazards <= HAZ_Divu; DP_Exceptions <= EXC_Divu; end + Funct_Jalr : begin DP_Hazards <= HAZ_Jalr; DP_Exceptions <= EXC_Jalr; end + Funct_Jr : begin DP_Hazards <= HAZ_Jr; DP_Exceptions <= EXC_Jr; end + Funct_Mfhi : begin DP_Hazards <= HAZ_Mfhi; DP_Exceptions <= EXC_Mfhi; end + Funct_Mflo : begin DP_Hazards <= HAZ_Mflo; DP_Exceptions <= EXC_Mflo; end + Funct_Movn : begin DP_Hazards <= HAZ_Movn; DP_Exceptions <= EXC_Movn; end + Funct_Movz : begin DP_Hazards <= HAZ_Movz; DP_Exceptions <= EXC_Movz; end + Funct_Mthi : begin DP_Hazards <= HAZ_Mthi; DP_Exceptions <= EXC_Mthi; end + Funct_Mtlo : begin DP_Hazards <= HAZ_Mtlo; DP_Exceptions <= EXC_Mtlo; end + Funct_Mult : begin DP_Hazards <= HAZ_Mult; DP_Exceptions <= EXC_Mult; end + Funct_Multu : begin DP_Hazards <= HAZ_Multu; DP_Exceptions <= EXC_Multu; end + Funct_Nor : begin DP_Hazards <= HAZ_Nor; DP_Exceptions <= EXC_Nor; end + Funct_Or : begin DP_Hazards <= HAZ_Or; DP_Exceptions <= EXC_Or; end + Funct_Sll : begin DP_Hazards <= HAZ_Sll; DP_Exceptions <= EXC_Sll; end + Funct_Sllv : begin DP_Hazards <= HAZ_Sllv; DP_Exceptions <= EXC_Sllv; end + Funct_Slt : begin DP_Hazards <= HAZ_Slt; DP_Exceptions <= EXC_Slt; end + Funct_Sltu : begin DP_Hazards <= HAZ_Sltu; DP_Exceptions <= EXC_Sltu; end + Funct_Sra : begin DP_Hazards <= HAZ_Sra; DP_Exceptions <= EXC_Sra; end + Funct_Srav : begin DP_Hazards <= HAZ_Srav; DP_Exceptions <= EXC_Srav; end + Funct_Srl : begin DP_Hazards <= HAZ_Srl; DP_Exceptions <= EXC_Srl; end + Funct_Srlv : begin DP_Hazards <= HAZ_Srlv; DP_Exceptions <= EXC_Srlv; end + Funct_Sub : begin DP_Hazards <= HAZ_Sub; DP_Exceptions <= EXC_Sub; end + Funct_Subu : begin DP_Hazards <= HAZ_Subu; DP_Exceptions <= EXC_Subu; end + Funct_Syscall : begin DP_Hazards <= HAZ_Syscall; DP_Exceptions <= EXC_Syscall; end + Funct_Teq : begin DP_Hazards <= HAZ_Teq; DP_Exceptions <= EXC_Teq; end + Funct_Tge : begin DP_Hazards <= HAZ_Tge; DP_Exceptions <= EXC_Tge; end + Funct_Tgeu : begin DP_Hazards <= HAZ_Tgeu; DP_Exceptions <= EXC_Tgeu; end + Funct_Tlt : begin DP_Hazards <= HAZ_Tlt; DP_Exceptions <= EXC_Tlt; end + Funct_Tltu : begin DP_Hazards <= HAZ_Tltu; DP_Exceptions <= EXC_Tltu; end + Funct_Tne : begin DP_Hazards <= HAZ_Tne; DP_Exceptions <= EXC_Tne; end + Funct_Xor : begin DP_Hazards <= HAZ_Xor; DP_Exceptions <= EXC_Xor; end + default : begin DP_Hazards <= 8'hxx; DP_Exceptions <= 3'bxxx; end + endcase + end + // R2-Type + Op_Type_R2 : + begin + case (Funct) + Funct_Clo : begin DP_Hazards <= HAZ_Clo; DP_Exceptions <= EXC_Clo; end + Funct_Clz : begin DP_Hazards <= HAZ_Clz; DP_Exceptions <= EXC_Clz; end + Funct_Madd : begin DP_Hazards <= HAZ_Madd; DP_Exceptions <= EXC_Madd; end + Funct_Maddu : begin DP_Hazards <= HAZ_Maddu; DP_Exceptions <= EXC_Maddu; end + Funct_Msub : begin DP_Hazards <= HAZ_Msub; DP_Exceptions <= EXC_Msub; end + Funct_Msubu : begin DP_Hazards <= HAZ_Msubu; DP_Exceptions <= EXC_Msubu; end + Funct_Mul : begin DP_Hazards <= HAZ_Mul; DP_Exceptions <= EXC_Mul; end + default : begin DP_Hazards <= 8'hxx; DP_Exceptions <= 3'bxxx; end + endcase + end + // I-Type + Op_Addi : begin DP_Hazards <= HAZ_Addi; DP_Exceptions <= EXC_Addi; end + Op_Addiu : begin DP_Hazards <= HAZ_Addiu; DP_Exceptions <= EXC_Addiu; end + Op_Andi : begin DP_Hazards <= HAZ_Andi; DP_Exceptions <= EXC_Andi; end + Op_Ori : begin DP_Hazards <= HAZ_Ori; DP_Exceptions <= EXC_Ori; end + Op_Pref : begin DP_Hazards <= HAZ_Pref; DP_Exceptions <= EXC_Pref; end + Op_Slti : begin DP_Hazards <= HAZ_Slti; DP_Exceptions <= EXC_Slti; end + Op_Sltiu : begin DP_Hazards <= HAZ_Sltiu; DP_Exceptions <= EXC_Sltiu; end + Op_Xori : begin DP_Hazards <= HAZ_Xori; DP_Exceptions <= EXC_Xori; end + // Jumps + Op_J : begin DP_Hazards <= HAZ_J; DP_Exceptions <= EXC_J; end + Op_Jal : begin DP_Hazards <= HAZ_Jal; DP_Exceptions <= EXC_Jal; end + // Branches and Traps + Op_Type_BI : + begin + case (Rt) + OpRt_Bgez : begin DP_Hazards <= HAZ_Bgez; DP_Exceptions <= EXC_Bgez; end + OpRt_Bgezal : begin DP_Hazards <= HAZ_Bgezal; DP_Exceptions <= EXC_Bgezal; end + OpRt_Bltz : begin DP_Hazards <= HAZ_Bltz; DP_Exceptions <= EXC_Bltz; end + OpRt_Bltzal : begin DP_Hazards <= HAZ_Bltzal; DP_Exceptions <= EXC_Bltzal; end + OpRt_Teqi : begin DP_Hazards <= HAZ_Teqi; DP_Exceptions <= EXC_Teqi; end + OpRt_Tgei : begin DP_Hazards <= HAZ_Tgei; DP_Exceptions <= EXC_Tgei; end + OpRt_Tgeiu : begin DP_Hazards <= HAZ_Tgeiu; DP_Exceptions <= EXC_Tgeiu; end + OpRt_Tlti : begin DP_Hazards <= HAZ_Tlti; DP_Exceptions <= EXC_Tlti; end + OpRt_Tltiu : begin DP_Hazards <= HAZ_Tltiu; DP_Exceptions <= EXC_Tltiu; end + OpRt_Tnei : begin DP_Hazards <= HAZ_Tnei; DP_Exceptions <= EXC_Tnei; end + default : begin DP_Hazards <= 8'hxx; DP_Exceptions <= 3'bxxx; end + endcase + end + Op_Beq : begin DP_Hazards <= HAZ_Beq; DP_Exceptions <= EXC_Beq; end + Op_Bgtz : begin DP_Hazards <= HAZ_Bgtz; DP_Exceptions <= EXC_Bgtz; end + Op_Blez : begin DP_Hazards <= HAZ_Blez; DP_Exceptions <= EXC_Blez; end + Op_Bne : begin DP_Hazards <= HAZ_Bne; DP_Exceptions <= EXC_Bne; end + // Coprocessor 0 + Op_Type_CP0 : + begin + case (Rs) + OpRs_MF : begin DP_Hazards <= HAZ_Mfc0; DP_Exceptions <= EXC_Mfc0; end + OpRs_MT : begin DP_Hazards <= HAZ_Mtc0; DP_Exceptions <= EXC_Mtc0; end + OpRs_ERET : begin DP_Hazards <= (Funct == Funct_ERET) ? DP_Eret : 8'hxx; DP_Exceptions <= EXC_Eret; end + default : begin DP_Hazards <= 8'hxx; DP_Exceptions <= 3'bxxx; end + endcase + end + // Memory + Op_Lb : begin DP_Hazards <= HAZ_Lb; DP_Exceptions <= EXC_Lb; end + Op_Lbu : begin DP_Hazards <= HAZ_Lbu; DP_Exceptions <= EXC_Lbu; end + Op_Lh : begin DP_Hazards <= HAZ_Lh; DP_Exceptions <= EXC_Lh; end + Op_Lhu : begin DP_Hazards <= HAZ_Lhu; DP_Exceptions <= EXC_Lhu; end + Op_Ll : begin DP_Hazards <= HAZ_Ll; DP_Exceptions <= EXC_Ll; end + Op_Lui : begin DP_Hazards <= HAZ_Lui; DP_Exceptions <= EXC_Lui; end + Op_Lw : begin DP_Hazards <= HAZ_Lw; DP_Exceptions <= EXC_Lw; end + Op_Lwl : begin DP_Hazards <= HAZ_Lwl; DP_Exceptions <= EXC_Lwl; end + Op_Lwr : begin DP_Hazards <= HAZ_Lwr; DP_Exceptions <= EXC_Lwr; end + Op_Sb : begin DP_Hazards <= HAZ_Sb; DP_Exceptions <= EXC_Sb; end + Op_Sc : begin DP_Hazards <= HAZ_Sc; DP_Exceptions <= EXC_Sc; end + Op_Sh : begin DP_Hazards <= HAZ_Sh; DP_Exceptions <= EXC_Sh; end + Op_Sw : begin DP_Hazards <= HAZ_Sw; DP_Exceptions <= EXC_Sw; end + Op_Swl : begin DP_Hazards <= HAZ_Swl; DP_Exceptions <= EXC_Swl; end + Op_Swr : begin DP_Hazards <= HAZ_Swr; DP_Exceptions <= EXC_Swr; end + default : begin DP_Hazards <= 8'hxx; DP_Exceptions <= 3'bxxx; end + endcase + end + + // ALU Assignment + always @(*) begin + if (ID_Stall) + ALUOp <= AluOp_Addu; // Any Op that doesn't write HILO or cause exceptions + else begin + case (OpCode) + Op_Type_R : + begin + case (Funct) + Funct_Add : ALUOp <= AluOp_Add; + Funct_Addu : ALUOp <= AluOp_Addu; + Funct_And : ALUOp <= AluOp_And; + Funct_Div : ALUOp <= AluOp_Div; + Funct_Divu : ALUOp <= AluOp_Divu; + Funct_Jalr : ALUOp <= AluOp_Addu; + Funct_Mfhi : ALUOp <= AluOp_Mfhi; + Funct_Mflo : ALUOp <= AluOp_Mflo; + Funct_Movn : ALUOp <= AluOp_Addu; + Funct_Movz : ALUOp <= AluOp_Addu; + Funct_Mthi : ALUOp <= AluOp_Mthi; + Funct_Mtlo : ALUOp <= AluOp_Mtlo; + Funct_Mult : ALUOp <= AluOp_Mult; + Funct_Multu : ALUOp <= AluOp_Multu; + Funct_Nor : ALUOp <= AluOp_Nor; + Funct_Or : ALUOp <= AluOp_Or; + Funct_Sll : ALUOp <= AluOp_Sll; + Funct_Sllv : ALUOp <= AluOp_Sllv; + Funct_Slt : ALUOp <= AluOp_Slt; + Funct_Sltu : ALUOp <= AluOp_Sltu; + Funct_Sra : ALUOp <= AluOp_Sra; + Funct_Srav : ALUOp <= AluOp_Srav; + Funct_Srl : ALUOp <= AluOp_Srl; + Funct_Srlv : ALUOp <= AluOp_Srlv; + Funct_Sub : ALUOp <= AluOp_Sub; + Funct_Subu : ALUOp <= AluOp_Subu; + Funct_Syscall : ALUOp <= AluOp_Addu; + Funct_Teq : ALUOp <= AluOp_Subu; + Funct_Tge : ALUOp <= AluOp_Slt; + Funct_Tgeu : ALUOp <= AluOp_Sltu; + Funct_Tlt : ALUOp <= AluOp_Slt; + Funct_Tltu : ALUOp <= AluOp_Sltu; + Funct_Tne : ALUOp <= AluOp_Subu; + Funct_Xor : ALUOp <= AluOp_Xor; + default : ALUOp <= AluOp_Addu; + endcase + end + Op_Type_R2 : + begin + case (Funct) + Funct_Clo : ALUOp <= AluOp_Clo; + Funct_Clz : ALUOp <= AluOp_Clz; + Funct_Madd : ALUOp <= AluOp_Madd; + Funct_Maddu : ALUOp <= AluOp_Maddu; + Funct_Msub : ALUOp <= AluOp_Msub; + Funct_Msubu : ALUOp <= AluOp_Msubu; + Funct_Mul : ALUOp <= AluOp_Mul; + default : ALUOp <= AluOp_Addu; + endcase + end + Op_Type_BI : + begin + case (Rt) + OpRt_Teqi : ALUOp <= AluOp_Subu; + OpRt_Tgei : ALUOp <= AluOp_Slt; + OpRt_Tgeiu : ALUOp <= AluOp_Sltu; + OpRt_Tlti : ALUOp <= AluOp_Slt; + OpRt_Tltiu : ALUOp <= AluOp_Sltu; + OpRt_Tnei : ALUOp <= AluOp_Subu; + default : ALUOp <= AluOp_Addu; // Branches don't matter. + endcase + end + Op_Type_CP0 : ALUOp <= AluOp_Addu; + Op_Addi : ALUOp <= AluOp_Add; + Op_Addiu : ALUOp <= AluOp_Addu; + Op_Andi : ALUOp <= AluOp_And; + Op_Jal : ALUOp <= AluOp_Addu; + Op_Lb : ALUOp <= AluOp_Addu; + Op_Lbu : ALUOp <= AluOp_Addu; + Op_Lh : ALUOp <= AluOp_Addu; + Op_Lhu : ALUOp <= AluOp_Addu; + Op_Ll : ALUOp <= AluOp_Addu; + Op_Lui : ALUOp <= AluOp_Sllc; + Op_Lw : ALUOp <= AluOp_Addu; + Op_Lwl : ALUOp <= AluOp_Addu; + Op_Lwr : ALUOp <= AluOp_Addu; + Op_Ori : ALUOp <= AluOp_Or; + Op_Sb : ALUOp <= AluOp_Addu; + Op_Sc : ALUOp <= AluOp_Addu; // XXX Needs HW implement + Op_Sh : ALUOp <= AluOp_Addu; + Op_Slti : ALUOp <= AluOp_Slt; + Op_Sltiu : ALUOp <= AluOp_Sltu; + Op_Sw : ALUOp <= AluOp_Addu; + Op_Swl : ALUOp <= AluOp_Addu; + Op_Swr : ALUOp <= AluOp_Addu; + Op_Xori : ALUOp <= AluOp_Xor; + default : ALUOp <= AluOp_Addu; + endcase + end + end + + /*** + These remaining options cover portions of the datapath that are not + controlled directly by the datapath bits. Note that some refer to bits of + the opcode or other fields, which breaks the otherwise fully-abstracted view + of instruction encodings. Make sure when adding custom instructions that + no false positives/negatives are generated here. + ***/ + + // Branch Detection: Options are mutually exclusive. + assign Branch_EQ = OpCode[2] & ~OpCode[1] & ~OpCode[0] & Cmp_EQ; + assign Branch_GTZ = OpCode[2] & OpCode[1] & OpCode[0] & Cmp_GZ; + assign Branch_LEZ = OpCode[2] & OpCode[1] & ~OpCode[0] & Cmp_LEZ; + assign Branch_NEQ = OpCode[2] & ~OpCode[1] & OpCode[0] & ~Cmp_EQ; + assign Branch_GEZ = ~OpCode[2] & Rt[0] & Cmp_GEZ; + assign Branch_LTZ = ~OpCode[2] & ~Rt[0] & Cmp_LZ; + + assign Branch = Branch_EQ | Branch_GTZ | Branch_LEZ | Branch_NEQ | Branch_GEZ | Branch_LTZ; + assign PCSrc[1] = (Datapath[15] & ~Datapath[14]) ? Branch : Datapath[15]; + + /* In MIPS32, all Branch and Jump operations execute the Branch Delay Slot, + * or next instruction, regardless if the branch is taken or not. The exception + * is the "Branch Likely" instruction group. These are deprecated, however, and not + * implemented here. "IF_Flush" is defined to allow for the cancelation of a + * Branch Delay Slot should these be implemented later. + */ + assign IF_Flush = 0; + + // Indicator that next instruction is a Branch Delay Slot. + assign NextIsDelay = Datapath[15] | Datapath[14]; + + // Sign- or Zero-Extension Control. The only ops that require zero-extension are + // Andi, Ori, and Xori. The following also zero-extends 'lui', however it does not alter the effect of lui. + assign SignExtend = (OpCode[5:2] != 4'b0011); + + // Move Conditional + assign Movn = Movc & Funct[0]; + assign Movz = Movc & ~Funct[0]; + + // Coprocessor 0 (Mfc0, Mtc0) control signals. + assign Mfc0 = ((OpCode == Op_Type_CP0) && (Rs == OpRs_MF)); + assign Mtc0 = ((OpCode == Op_Type_CP0) && (Rs == OpRs_MT)); + assign Eret = ((OpCode == Op_Type_CP0) && (Rs == OpRs_ERET) && (Funct == Funct_ERET)); + + // Coprocessor 1,2,3 accesses (not implemented) + assign CP1 = (OpCode == Op_Type_CP1); + assign CP2 = (OpCode == Op_Type_CP2); + assign CP3 = (OpCode == Op_Type_CP3); + + // Exceptions found in ID + assign EXC_Sys = ((OpCode == Op_Type_R) && (Funct == Funct_Syscall)); + assign EXC_Bp = ((OpCode == Op_Type_R) && (Funct == Funct_Break)); + + // Unaligned Memory Accesses (lwl, lwr, swl, swr) + assign Unaligned_Mem = OpCode[5] & ~OpCode[4] & OpCode[1] & ~OpCode[0]; + assign Left = Unaligned_Mem & ~OpCode[2]; + assign Right = Unaligned_Mem & OpCode[2]; + + // TODO: Reserved Instruction Exception must still be implemented + assign EXC_RI = 0; + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/Divide.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/Divide.v new file mode 100755 index 0000000..8a2e617 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/Divide.v @@ -0,0 +1,100 @@ +`timescale 1ns / 1ns +/* + * File : Divide.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Neil Russell + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 6-Nov-2012 NJR Initial design. + * + * Description: + * A multi-cycle 32-bit divider. + * + * On any cycle that one of OP_div or OP_divu are true, the Dividend and + * Divisor will be captured and a multi-cycle divide operation initiated. + * Stall will go true on the next cycle and the first cycle of the divide + * operation completed. After some time (about 32 cycles), Stall will go + * false on the same cycle that the result becomes valid. OP_div or OP_divu + * will abort any currently running divide operation and initiate a new one. + */ +module Divide( + input clock, + input reset, + input OP_div, // True to initiate a signed divide + input OP_divu, // True to initiate an unsigned divide + input [31:0] Dividend, + input [31:0] Divisor, + output [31:0] Quotient, + output [31:0] Remainder, + output Stall // True while calculating + ); + + + reg active; // True if the divider is running + reg neg; // True if the result will be negative + reg [4:0] cycle; // Number of cycles to go + + reg [31:0] result; // Begin with dividend, end with quotient + reg [31:0] denom; // Divisor + reg [31:0] work; // Running remainder + + // Calculate the current digit + wire [32:0] sub = { work[30:0], result[31] } - denom; + + // Send the results to our master + assign Quotient = !neg ? result : -result; + assign Remainder = work; + assign Stall = active; + + // The state machine + always @(posedge clock) begin + if (reset) begin + active <= 0; + neg <= 0; + cycle <= 0; + result <= 0; + denom <= 0; + work <= 0; + end + else begin + if (OP_div) begin + // Set up for a signed divide. Remember the resulting sign, + // and make the operands positive. + cycle <= 5'd31; + result <= (Dividend[31] == 0) ? Dividend : -Dividend; + denom <= (Divisor[31] == 0) ? Divisor : -Divisor; + work <= 32'b0; + neg <= Dividend[31] ^ Divisor[31]; + active <= 1; + end + else if (OP_divu) begin + // Set up for an unsigned divide. + cycle <= 5'd31; + result <= Dividend; + denom <= Divisor; + work <= 32'b0; + neg <= 0; + active <= 1; + end + else if (active) begin + // Run an iteration of the divide. + if (sub[32] == 0) begin + work <= sub[31:0]; + result <= {result[30:0], 1'b1}; + end + else begin + work <= {work[30:0], result[31]}; + result <= {result[30:0], 1'b0}; + end + + if (cycle == 0) begin + active <= 0; + end + + cycle <= cycle - 5'd1; + end + end + end + +endmodule diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/EXMEM_Stage.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/EXMEM_Stage.v new file mode 100755 index 0000000..99d3c7b --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/EXMEM_Stage.v @@ -0,0 +1,116 @@ +`timescale 1ns / 1ps +/* + * File : EXMEM_Stage.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 9-Jun-2011 GEA Initial design. + * 2.0 26-Jul-2012 GEA Many updates have been made. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * The Pipeline Register to bridge the Execute and Memory stages. + */ +module EXMEM_Stage( + input clock, + input reset, + input EX_Flush, + input EX_Stall, + input M_Stall, + // Control Signals + input EX_Movn, + input EX_Movz, + input EX_BZero, + input EX_RegWrite, // Future Control to WB + input EX_MemtoReg, // Future Control to WB + input EX_ReverseEndian, + input EX_LLSC, + input EX_MemRead, + input EX_MemWrite, + input EX_MemByte, + input EX_MemHalf, + input EX_MemSignExtend, + input EX_Left, + input EX_Right, + // Exception Control/Info + input EX_KernelMode, + input [31:0] EX_RestartPC, + input EX_IsBDS, + input EX_Trap, + input EX_TrapCond, + input EX_M_CanErr, + // Data Signals + input [31:0] EX_ALU_Result, + input [31:0] EX_ReadData2, + input [4:0] EX_RtRd, + // ------------------ + output reg M_RegWrite, + output reg M_MemtoReg, + output reg M_ReverseEndian, + output reg M_LLSC, + output reg M_MemRead, + output reg M_MemWrite, + output reg M_MemByte, + output reg M_MemHalf, + output reg M_MemSignExtend, + output reg M_Left, + output reg M_Right, + output reg M_KernelMode, + output reg [31:0] M_RestartPC, + output reg M_IsBDS, + output reg M_Trap, + output reg M_TrapCond, + output reg M_M_CanErr, + output reg [31:0] M_ALU_Result, + output reg [31:0] M_ReadData2, + output reg [4:0] M_RtRd + ); + + /*** + The purpose of a pipeline register is to capture data from one pipeline stage + and provide it to the next pipeline stage. This creates at least one clock cycle + of delay, but reduces the combinatorial path length of signals which allows for + higher clock speeds. + + All pipeline registers update unless the forward stage is stalled. When this occurs + or when the current stage is being flushed, the forward stage will receive data that + is effectively a NOP and causes nothing to happen throughout the remaining pipeline + traversal. In other words: + + A stall masks all control signals to forward stages. A flush permanently clears + control signals to forward stages (but not certain data for exception purposes). + ***/ + + // Mask of RegWrite if a Move Conditional failed. + wire MovcRegWrite = (EX_Movn & ~EX_BZero) | (EX_Movz & EX_BZero); + + always @(posedge clock) begin + M_RegWrite <= (reset) ? 0 : ((M_Stall) ? M_RegWrite : ((EX_Stall | EX_Flush) ? 0 : EX_RegWrite)); + M_RegWrite <= (reset) ? 0 : ((M_Stall) ? M_RegWrite : ((EX_Stall | EX_Flush) ? 0 : ((EX_Movn | EX_Movz) ? MovcRegWrite : EX_RegWrite))); + M_MemtoReg <= (reset) ? 0 : ((M_Stall) ? M_MemtoReg : EX_MemtoReg); + M_ReverseEndian <= (reset) ? 0 : ((M_Stall) ? M_ReverseEndian : EX_ReverseEndian); + M_LLSC <= (reset) ? 0 : ((M_Stall) ? M_LLSC : EX_LLSC); + M_MemRead <= (reset) ? 0 : ((M_Stall) ? M_MemRead : ((EX_Stall | EX_Flush) ? 0 : EX_MemRead)); + M_MemWrite <= (reset) ? 0 : ((M_Stall) ? M_MemWrite : ((EX_Stall | EX_Flush) ? 0 : EX_MemWrite)); + M_MemByte <= (reset) ? 0 : ((M_Stall) ? M_MemByte : EX_MemByte); + M_MemHalf <= (reset) ? 0 : ((M_Stall) ? M_MemHalf : EX_MemHalf); + M_MemSignExtend <= (reset) ? 0 : ((M_Stall) ? M_MemSignExtend : EX_MemSignExtend); + M_Left <= (reset) ? 0 : ((M_Stall) ? M_Left : EX_Left); + M_Right <= (reset) ? 0 : ((M_Stall) ? M_Right : EX_Right); + M_KernelMode <= (reset) ? 0 : ((M_Stall) ? M_KernelMode : EX_KernelMode); + M_RestartPC <= (reset) ? 32'b0 : ((M_Stall) ? M_RestartPC : EX_RestartPC); + M_IsBDS <= (reset) ? 0 : ((M_Stall) ? M_IsBDS : EX_IsBDS); + M_Trap <= (reset) ? 0 : ((M_Stall) ? M_Trap : ((EX_Stall | EX_Flush) ? 0 : EX_Trap)); + M_TrapCond <= (reset) ? 0 : ((M_Stall) ? M_TrapCond : EX_TrapCond); + M_M_CanErr <= (reset) ? 0 : ((M_Stall) ? M_M_CanErr : ((EX_Stall | EX_Flush) ? 0 : EX_M_CanErr)); + M_ALU_Result <= (reset) ? 32'b0 : ((M_Stall) ? M_ALU_Result : EX_ALU_Result); + M_ReadData2 <= (reset) ? 32'b0 : ((M_Stall) ? M_ReadData2 : EX_ReadData2); + M_RtRd <= (reset) ? 5'b0 : ((M_Stall) ? M_RtRd : EX_RtRd); + end + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/Hazard_Detection.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/Hazard_Detection.v new file mode 100755 index 0000000..b719664 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/Hazard_Detection.v @@ -0,0 +1,175 @@ +`timescale 1ns / 1ps +/* + * File : Hazard_Detection.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 23-Jul-2011 GEA Initial design. + * 2.0 26-May-2012 GEA Release version with CP0. + * 2.01 1-Nov-2012 GEA Fixed issue with Jal. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * Hazard Detection and Forward Control. This is the glue that allows a + * pipelined processor to operate efficiently and correctly in the presence + * of data, structural, and control hazards. For each pipeline stage, it + * detects whether that stage requires data that is still in the pipeline, + * and whether that data may be forwarded or if the pipeline must be stalled. + * + * This module is heavily commented. Read below for more information. + */ +module Hazard_Detection( + input [7:0] DP_Hazards, + input [4:0] ID_Rs, + input [4:0] ID_Rt, + input [4:0] EX_Rs, + input [4:0] EX_Rt, + input [4:0] EX_RtRd, + input [4:0] MEM_RtRd, + input [4:0] WB_RtRd, + input EX_Link, + input EX_RegWrite, + input MEM_RegWrite, + input WB_RegWrite, + input MEM_MemRead, + input MEM_MemWrite, // Needed for Store Conditional which writes to a register + input InstMem_Read, + input InstMem_Ready, + input Mfc0, // Using fwd mux; not part of haz/fwd. + input IF_Exception_Stall, + input ID_Exception_Stall, + input EX_Exception_Stall, + input EX_ALU_Stall, + input M_Stall_Controller, // Determined by data memory controller + output IF_Stall, + output ID_Stall, + output EX_Stall, + output M_Stall, + output WB_Stall, + output [1:0] ID_RsFwdSel, + output [1:0] ID_RtFwdSel, + output [1:0] EX_RsFwdSel, + output [1:0] EX_RtFwdSel, + output M_WriteDataFwdSel + ); + + /* Hazard and Forward Detection + * + * Most instructions read from one or more registers. Normally this occurs in + * the ID stage. However, frequently the register file in the ID stage is stale + * when one or more forward stages in the pipeline (EX, MEM, or WB) contains + * an instruction which will eventually update it but has not yet done so. + * + * A hazard condition is created when a forward pipeline stage is set to write + * the same register that a current pipeline stage (e.g. in ID) needs to read. + * The solution is to stall the current stage (and effectively all stages behind + * it) or bypass (forward) the data from forward stages. Fortunately forwarding + * works for most combinations of instructions. + * + * Hazard and Forward conditions are handled based on two simple rules: + * "Wants" and "Needs." If an instruction "wants" data in a certain pipeline + * stage, and that data is available further along in the pipeline, it will + * be forwarded. If it "needs" data and the data is not yet available for forwarding, + * the pipeline stage stalls. If it does not want or need data in a certain + * stage, forwarding is disabled and a stall will not occur. This is important + * for instructions which insert custom data, such as jal or movz. + * + * Currently, "Want" and "Need" conditions are defined for both Rs data and Rt + * data (the two read registers in MIPS), and these conditions exist in the + * ID and EX pipeline stages. This is a total of eight condition bits. + * + * A unique exception exists with Store instructions, which don't need the + * "Rt" data until the MEM stage. Because data doesn't change in WB, and WB + * is the only stage following MEM, forwarding is *always* possible from + * WB to Mem. This unit handles this situation, and a condition bit is not + * needed. + * + * When data is needed from the MEM stage by a previous stage (ID or EX), the + * decision to forward or stall is based on whether MEM is accessing memory + * (stall) or not (forward). Normally store instructions don't write to registers + * and thus are never needed for a data dependence, so the signal 'MEM_MemRead' + * is sufficient to determine. Because of the Store Conditional instruction, + * however, 'MEM_MemWrite' must also be considered because it writes to a register. + * + */ + + wire WantRsByID, NeedRsByID, WantRtByID, NeedRtByID, WantRsByEX, NeedRsByEX, WantRtByEX, NeedRtByEX; + assign WantRsByID = DP_Hazards[7]; + assign NeedRsByID = DP_Hazards[6]; + assign WantRtByID = DP_Hazards[5]; + assign NeedRtByID = DP_Hazards[4]; + assign WantRsByEX = DP_Hazards[3]; + assign NeedRsByEX = DP_Hazards[2]; + assign WantRtByEX = DP_Hazards[1]; + assign NeedRtByEX = DP_Hazards[0]; + + // Trick allowed by RegDst = 0 which gives Rt. MEM_Rt is only used on + // Data Memory write operations (stores), and RegWrite is always 0 in this case. + wire [4:0] MEM_Rt = MEM_RtRd; + + // Forwarding should not happen when the src/dst register is $zero + wire EX_RtRd_NZ = (EX_RtRd != 5'b00000); + wire MEM_RtRd_NZ = (MEM_RtRd != 5'b00000); + wire WB_RtRd_NZ = (WB_RtRd != 5'b00000); + + // ID Dependencies + wire Rs_IDEX_Match = (ID_Rs == EX_RtRd) & EX_RtRd_NZ & (WantRsByID | NeedRsByID) & EX_RegWrite; + wire Rt_IDEX_Match = (ID_Rt == EX_RtRd) & EX_RtRd_NZ & (WantRtByID | NeedRtByID) & EX_RegWrite; + wire Rs_IDMEM_Match = (ID_Rs == MEM_RtRd) & MEM_RtRd_NZ & (WantRsByID | NeedRsByID) & MEM_RegWrite; + wire Rt_IDMEM_Match = (ID_Rt == MEM_RtRd) & MEM_RtRd_NZ & (WantRtByID | NeedRtByID) & MEM_RegWrite; + wire Rs_IDWB_Match = (ID_Rs == WB_RtRd) & WB_RtRd_NZ & (WantRsByID | NeedRsByID) & WB_RegWrite; + wire Rt_IDWB_Match = (ID_Rt == WB_RtRd) & WB_RtRd_NZ & (WantRtByID | NeedRtByID) & WB_RegWrite; + // EX Dependencies + wire Rs_EXMEM_Match = (EX_Rs == MEM_RtRd) & MEM_RtRd_NZ & (WantRsByEX | NeedRsByEX) & MEM_RegWrite; + wire Rt_EXMEM_Match = (EX_Rt == MEM_RtRd) & MEM_RtRd_NZ & (WantRtByEX | NeedRtByEX) & MEM_RegWrite; + wire Rs_EXWB_Match = (EX_Rs == WB_RtRd) & WB_RtRd_NZ & (WantRsByEX | NeedRsByEX) & WB_RegWrite; + wire Rt_EXWB_Match = (EX_Rt == WB_RtRd) & WB_RtRd_NZ & (WantRtByEX | NeedRtByEX) & WB_RegWrite; + // MEM Dependencies + wire Rt_MEMWB_Match = (MEM_Rt == WB_RtRd) & WB_RtRd_NZ & WB_RegWrite; + + + // ID needs data from EX : Stall + wire ID_Stall_1 = (Rs_IDEX_Match & NeedRsByID); + wire ID_Stall_2 = (Rt_IDEX_Match & NeedRtByID); + // ID needs data from MEM : Stall if mem access + wire ID_Stall_3 = (Rs_IDMEM_Match & (MEM_MemRead | MEM_MemWrite) & NeedRsByID); + wire ID_Stall_4 = (Rt_IDMEM_Match & (MEM_MemRead | MEM_MemWrite) & NeedRtByID); + // ID wants data from MEM : Forward if not mem access + wire ID_Fwd_1 = (Rs_IDMEM_Match & ~(MEM_MemRead | MEM_MemWrite)); + wire ID_Fwd_2 = (Rt_IDMEM_Match & ~(MEM_MemRead | MEM_MemWrite)); + // ID wants/needs data from WB : Forward + wire ID_Fwd_3 = (Rs_IDWB_Match); + wire ID_Fwd_4 = (Rt_IDWB_Match); + // EX needs data from MEM : Stall if mem access + wire EX_Stall_1 = (Rs_EXMEM_Match & (MEM_MemRead | MEM_MemWrite) & NeedRsByEX); + wire EX_Stall_2 = (Rt_EXMEM_Match & (MEM_MemRead | MEM_MemWrite) & NeedRtByEX); + // EX wants data from MEM : Forward if not mem access + wire EX_Fwd_1 = (Rs_EXMEM_Match & ~(MEM_MemRead | MEM_MemWrite)); + wire EX_Fwd_2 = (Rt_EXMEM_Match & ~(MEM_MemRead | MEM_MemWrite)); + // EX wants/needs data from WB : Forward + wire EX_Fwd_3 = (Rs_EXWB_Match); + wire EX_Fwd_4 = (Rt_EXWB_Match); + // MEM needs data from WB : Forward + wire MEM_Fwd_1 = (Rt_MEMWB_Match); + + + // Stalls and Control Flow Final Assignments + assign WB_Stall = M_Stall; + assign M_Stall = IF_Stall | M_Stall_Controller; + assign EX_Stall = (EX_Stall_1 | EX_Stall_2 | EX_Exception_Stall) | EX_ALU_Stall | M_Stall; + assign ID_Stall = (ID_Stall_1 | ID_Stall_2 | ID_Stall_3 | ID_Stall_4 | ID_Exception_Stall) | EX_Stall; + assign IF_Stall = InstMem_Read | InstMem_Ready | IF_Exception_Stall; + + // Forwarding Control Final Assignments + assign ID_RsFwdSel = (ID_Fwd_1) ? 2'b01 : ((ID_Fwd_3) ? 2'b10 : 2'b00); + assign ID_RtFwdSel = (Mfc0) ? 2'b11 : ((ID_Fwd_2) ? 2'b01 : ((ID_Fwd_4) ? 2'b10 : 2'b00)); + assign EX_RsFwdSel = (EX_Link) ? 2'b11 : ((EX_Fwd_1) ? 2'b01 : ((EX_Fwd_3) ? 2'b10 : 2'b00)); + assign EX_RtFwdSel = (EX_Link) ? 2'b11 : ((EX_Fwd_2) ? 2'b01 : ((EX_Fwd_4) ? 2'b10 : 2'b00)); + assign M_WriteDataFwdSel = MEM_Fwd_1; + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/IDEX_Stage.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/IDEX_Stage.v new file mode 100755 index 0000000..3cdaaee --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/IDEX_Stage.v @@ -0,0 +1,159 @@ +`timescale 1ns / 1ps +/* + * File : IDEX_Stage.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 9-Jun-2011 GEA Initial design. + * 2.0 26-Jul-2012 GEA Many updates have been made. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * The Pipeline Register to bridge the Instruction Decode + * and Execute stages. + */ +module IDEX_Stage( + input clock, + input reset, + input ID_Flush, + input ID_Stall, + input EX_Stall, + // Control Signals + input ID_Link, + input ID_RegDst, + input ID_ALUSrcImm, + input [4:0] ID_ALUOp, + input ID_Movn, + input ID_Movz, + input ID_LLSC, + input ID_MemRead, + input ID_MemWrite, + input ID_MemByte, + input ID_MemHalf, + input ID_MemSignExtend, + input ID_Left, + input ID_Right, + input ID_RegWrite, + input ID_MemtoReg, + input ID_ReverseEndian, + // Hazard & Forwarding + input [4:0] ID_Rs, + input [4:0] ID_Rt, + input ID_WantRsByEX, + input ID_NeedRsByEX, + input ID_WantRtByEX, + input ID_NeedRtByEX, + // Exception Control/Info + input ID_KernelMode, + input [31:0] ID_RestartPC, + input ID_IsBDS, + input ID_Trap, + input ID_TrapCond, + input ID_EX_CanErr, + input ID_M_CanErr, + // Data Signals + input [31:0] ID_ReadData1, + input [31:0] ID_ReadData2, + input [16:0] ID_SignExtImm, // ID_Rd, ID_Shamt included here + // ---------------- + output reg EX_Link, + output [1:0] EX_LinkRegDst, + output reg EX_ALUSrcImm, + output reg [4:0] EX_ALUOp, + output reg EX_Movn, + output reg EX_Movz, + output reg EX_LLSC, + output reg EX_MemRead, + output reg EX_MemWrite, + output reg EX_MemByte, + output reg EX_MemHalf, + output reg EX_MemSignExtend, + output reg EX_Left, + output reg EX_Right, + output reg EX_RegWrite, + output reg EX_MemtoReg, + output reg EX_ReverseEndian, + output reg [4:0] EX_Rs, + output reg [4:0] EX_Rt, + output reg EX_WantRsByEX, + output reg EX_NeedRsByEX, + output reg EX_WantRtByEX, + output reg EX_NeedRtByEX, + output reg EX_KernelMode, + output reg [31:0] EX_RestartPC, + output reg EX_IsBDS, + output reg EX_Trap, + output reg EX_TrapCond, + output reg EX_EX_CanErr, + output reg EX_M_CanErr, + output reg [31:0] EX_ReadData1, + output reg [31:0] EX_ReadData2, + output [31:0] EX_SignExtImm, + output [4:0] EX_Rd, + output [4:0] EX_Shamt + ); + + /*** + The purpose of a pipeline register is to capture data from one pipeline stage + and provide it to the next pipeline stage. This creates at least one clock cycle + of delay, but reduces the combinatorial path length of signals which allows for + higher clock speeds. + + All pipeline registers update unless the forward stage is stalled. When this occurs + or when the current stage is being flushed, the forward stage will receive data that + is effectively a NOP and causes nothing to happen throughout the remaining pipeline + traversal. In other words: + + A stall masks all control signals to forward stages. A flush permanently clears + control signals to forward stages (but not certain data for exception purposes). + ***/ + + reg [16:0] EX_SignExtImm_pre; + reg EX_RegDst; + assign EX_LinkRegDst = (EX_Link) ? 2'b10 : ((EX_RegDst) ? 2'b01 : 2'b00); + assign EX_Rd = EX_SignExtImm[15:11]; + assign EX_Shamt = EX_SignExtImm[10:6]; + assign EX_SignExtImm = (EX_SignExtImm_pre[16]) ? {15'h7fff, EX_SignExtImm_pre[16:0]} : {15'h0000, EX_SignExtImm_pre[16:0]}; + + always @(posedge clock) begin + EX_Link <= (reset) ? 0 : ((EX_Stall) ? EX_Link : ID_Link); + EX_RegDst <= (reset) ? 0 : ((EX_Stall) ? EX_RegDst : ID_RegDst); + EX_ALUSrcImm <= (reset) ? 0 : ((EX_Stall) ? EX_ALUSrcImm : ID_ALUSrcImm); + EX_ALUOp <= (reset) ? 5'b0 : ((EX_Stall) ? EX_ALUOp : ((ID_Stall | ID_Flush) ? 5'b0 : ID_ALUOp)); + EX_Movn <= (reset) ? 0 : ((EX_Stall) ? EX_Movn : ID_Movn); + EX_Movz <= (reset) ? 0 : ((EX_Stall) ? EX_Movz : ID_Movz); + EX_LLSC <= (reset) ? 0 : ((EX_Stall) ? EX_LLSC : ID_LLSC); + EX_MemRead <= (reset) ? 0 : ((EX_Stall) ? EX_MemRead : ((ID_Stall | ID_Flush) ? 0 : ID_MemRead)); + EX_MemWrite <= (reset) ? 0 : ((EX_Stall) ? EX_MemWrite : ((ID_Stall | ID_Flush) ? 0 : ID_MemWrite)); + EX_MemByte <= (reset) ? 0 : ((EX_Stall) ? EX_MemByte : ID_MemByte); + EX_MemHalf <= (reset) ? 0 : ((EX_Stall) ? EX_MemHalf : ID_MemHalf); + EX_MemSignExtend <= (reset) ? 0 : ((EX_Stall) ? EX_MemSignExtend : ID_MemSignExtend); + EX_Left <= (reset) ? 0 : ((EX_Stall) ? EX_Left : ID_Left); + EX_Right <= (reset) ? 0 : ((EX_Stall) ? EX_Right : ID_Right); + EX_RegWrite <= (reset) ? 0 : ((EX_Stall) ? EX_RegWrite : ((ID_Stall | ID_Flush) ? 0 : ID_RegWrite)); + EX_MemtoReg <= (reset) ? 0 : ((EX_Stall) ? EX_MemtoReg : ID_MemtoReg); + EX_ReverseEndian <= (reset) ? 0 : ((EX_Stall) ? EX_ReverseEndian : ID_ReverseEndian); + EX_RestartPC <= (reset) ? 32'b0 : ((EX_Stall) ? EX_RestartPC : ID_RestartPC); + EX_IsBDS <= (reset) ? 0 : ((EX_Stall) ? EX_IsBDS : ID_IsBDS); + EX_Trap <= (reset) ? 0 : ((EX_Stall) ? EX_Trap : ((ID_Stall | ID_Flush) ? 0 : ID_Trap)); + EX_TrapCond <= (reset) ? 0 : ((EX_Stall) ? EX_TrapCond : ID_TrapCond); + EX_EX_CanErr <= (reset) ? 0 : ((EX_Stall) ? EX_EX_CanErr : ((ID_Stall | ID_Flush) ? 0 : ID_EX_CanErr)); + EX_M_CanErr <= (reset) ? 0 : ((EX_Stall) ? EX_M_CanErr : ((ID_Stall | ID_Flush) ? 0 : ID_M_CanErr)); + EX_ReadData1 <= (reset) ? 32'b0 : ((EX_Stall) ? EX_ReadData1 : ID_ReadData1); + EX_ReadData2 <= (reset) ? 32'b0 : ((EX_Stall) ? EX_ReadData2 : ID_ReadData2); + EX_SignExtImm_pre <= (reset) ? 17'b0 : ((EX_Stall) ? EX_SignExtImm_pre : ID_SignExtImm); + EX_Rs <= (reset) ? 5'b0 : ((EX_Stall) ? EX_Rs : ID_Rs); + EX_Rt <= (reset) ? 5'b0 : ((EX_Stall) ? EX_Rt : ID_Rt); + EX_WantRsByEX <= (reset) ? 0 : ((EX_Stall) ? EX_WantRsByEX : ((ID_Stall | ID_Flush) ? 0 : ID_WantRsByEX)); + EX_NeedRsByEX <= (reset) ? 0 : ((EX_Stall) ? EX_NeedRsByEX : ((ID_Stall | ID_Flush) ? 0 : ID_NeedRsByEX)); + EX_WantRtByEX <= (reset) ? 0 : ((EX_Stall) ? EX_WantRtByEX : ((ID_Stall | ID_Flush) ? 0 : ID_WantRtByEX)); + EX_NeedRtByEX <= (reset) ? 0 : ((EX_Stall) ? EX_NeedRtByEX : ((ID_Stall | ID_Flush) ? 0 : ID_NeedRtByEX)); + EX_KernelMode <= (reset) ? 0 : ((EX_Stall) ? EX_KernelMode : ID_KernelMode); + end + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/IFID_Stage.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/IFID_Stage.v new file mode 100755 index 0000000..f6c7435 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/IFID_Stage.v @@ -0,0 +1,75 @@ +`timescale 1ns / 1ps +/* + * File : IFID_Stage.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 9-Jun-2011 GEA Initial design. + * 2.0 26-Jul-2012 GEA Many updates have been made. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * The Pipeline Register to bridge the Instruction Fetch + * and Instruction Decode stages. + */ +module IFID_Stage( + input clock, + input reset, + input IF_Flush, + input IF_Stall, + input ID_Stall, + // Control Signals + input [31:0] IF_Instruction, + // Data Signals + input [31:0] IF_PCAdd4, + input [31:0] IF_PC, + input IF_IsBDS, + // ------------------ + output reg [31:0] ID_Instruction, + output reg [31:0] ID_PCAdd4, + output reg [31:0] ID_RestartPC, + output reg ID_IsBDS, + output reg ID_IsFlushed + ); + + /*** + The purpose of a pipeline register is to capture data from one pipeline stage + and provide it to the next pipeline stage. This creates at least one clock cycle + of delay, but reduces the combinatorial path length of signals which allows for + higher clock speeds. + + All pipeline registers update unless the forward stage is stalled. When this occurs + or when the current stage is being flushed, the forward stage will receive data that + is effectively a NOP and causes nothing to happen throughout the remaining pipeline + traversal. In other words: + + A stall masks all control signals to forward stages. A flush permanently clears + control signals to forward stages (but not certain data for exception purposes). + ***/ + + + /*** + The signal 'ID_IsFlushed' is needed because of interrupts. Normally, a flushed instruction + is a NOP which will never cause an exception and thus its restart PC will never be needed + or used. However, interrupts are detected in ID and may occur when any instruction, flushed + or not, is in the ID stage. It is an error to save the restart PC of a flushed instruction + since it was never supposed to execute (such as the "delay slot" after ERET or the branch + delay slot after a canceled Branch Likely instruction). A simple way to prevent this is to + pass a signal to ID indicating that its instruction was flushed. Interrupt detection is then + masked when this signal is high, and the interrupt will trigger on the next instruction load to ID. + ***/ + + always @(posedge clock) begin + ID_Instruction <= (reset) ? 32'b0 : ((ID_Stall) ? ID_Instruction : ((IF_Stall | IF_Flush) ? 32'b0 : IF_Instruction)); + ID_PCAdd4 <= (reset) ? 32'b0 : ((ID_Stall) ? ID_PCAdd4 : IF_PCAdd4); + ID_IsBDS <= (reset) ? 0 : ((ID_Stall) ? ID_IsBDS : IF_IsBDS); + ID_RestartPC <= (reset) ? 32'b0 : ((ID_Stall | IF_IsBDS) ? ID_RestartPC : IF_PC); + ID_IsFlushed <= (reset) ? 0 : ((ID_Stall) ? ID_IsFlushed : IF_Flush); + end + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/MEMWB_Stage.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/MEMWB_Stage.v new file mode 100755 index 0000000..5c22049 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/MEMWB_Stage.v @@ -0,0 +1,74 @@ +`timescale 1ns / 1ps +/* + * File : MEMWB_Stage.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 9-Jun-2011 GEA Initial design. + * 2.0 26-Jul-2012 GEA Many updates have been made. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * The Pipeline Register to bridge the Memory and Writeback stages. + */ +module MEMWB_Stage( + input clock, + input reset, + input M_Flush, + input M_Stall, + input WB_Stall, + // Control Signals + input M_RegWrite, + input M_MemtoReg, + // Data Signals + input [31:0] M_ReadData, + input [31:0] M_ALU_Result, + input [4:0] M_RtRd, + // ---------------- + output reg WB_RegWrite, + output reg WB_MemtoReg, + output reg [31:0] WB_ReadData, + output reg [31:0] WB_ALU_Result, + output reg [4:0] WB_RtRd + ); + + + /*** + The purpose of a pipeline register is to capture data from one pipeline stage + and provide it to the next pipeline stage. This creates at least one clock cycle + of delay, but reduces the combinatorial path length of signals which allows for + higher clock speeds. + + All pipeline registers update unless the forward stage is stalled. When this occurs + or when the current stage is being flushed, the forward stage will receive data that + is effectively a NOP and causes nothing to happen throughout the remaining pipeline + traversal. In other words: + + A stall masks all control signals to forward stages. A flush permanently clears + control signals to forward stages (but not certain data for exception purposes). + + Since WB is the final stage in the pipeline, it would normally never stall. + However, because the MEM stage may be using data forwarded from WB, WB must stall + when MEM is stalled. If it didn't, the forward data would not be preserved. If + the processor didn't forward any data, a stall would not be needed. + + In practice, the only time WB stalls is when forwarding for a Lw->Sw sequence, since + MEM doesn't need the data until its stage, but it does not latch the forwarded data. + This means WB_Stall is probably identical to M_Stall. There is no speed difference by + allowing WB to stall. + ***/ + + always @(posedge clock) begin + WB_RegWrite <= (reset) ? 0 : ((WB_Stall) ? WB_RegWrite : ((M_Stall | M_Flush) ? 0 : M_RegWrite)); + WB_MemtoReg <= (reset) ? 0 : ((WB_Stall) ? WB_MemtoReg : M_MemtoReg); + WB_ReadData <= (reset) ? 32'b0 : ((WB_Stall) ? WB_ReadData : M_ReadData); + WB_ALU_Result <= (reset) ? 32'b0 : ((WB_Stall) ? WB_ALU_Result : M_ALU_Result); + WB_RtRd <= (reset) ? 5'b0 : ((WB_Stall) ? WB_RtRd : M_RtRd); + end + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/MIPS_Parameters.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/MIPS_Parameters.v new file mode 100755 index 0000000..7a994ef --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/MIPS_Parameters.v @@ -0,0 +1,631 @@ +/* + * File : MIPS_Parameters.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 26-May-2012 GEA Release version. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * Provides a language abstraction for the MIPS32-specific op-codes and + * the processor-specific datapath, hazard, and exception bits which + * control the processor. These parameter names are used extensively + * throughout the processor HDL modules. + */ + + +/*** Exception Vector Locations *** + + When the CPU powers up or is reset, it will begin execution at 'EXC_Vector_Base_Reset'. + All other exceptions are the sum of a base address and offset: + - The base address is either a bootstrap or normal value. It is controlled by + the 'BEV' bit in the CP0 'Status' register. Both base addresses can be mapped to + the same location. + - The offset address is either a standard offset (which is always used for + non-interrupt general exceptions in this processor because it lacks TLB Refill + and Cache errors), or a special interrupt-only offset for interrupts, which is + enabled with the 'IV' bit in the CP0 'Cause' register. + + Current Setup: + General exceptions go to 0x0. Interrupts go to 0x8. Booting starts at 0x10. +*/ +parameter [31:0] EXC_Vector_Base_Reset = 32'h0000_0010; // MIPS Standard is 0xBFC0_0000 +parameter [31:0] EXC_Vector_Base_Other_NoBoot = 32'h0000_0000; // MIPS Standard is 0x8000_0000 +parameter [31:0] EXC_Vector_Base_Other_Boot = 32'h0000_0000; // MIPS Standard is 0xBFC0_0200 +parameter [31:0] EXC_Vector_Offset_General = 32'h0000_0000; // MIPS Standard is 0x0000_0180 +parameter [31:0] EXC_Vector_Offset_Special = 32'h0000_0008; // MIPS Standard is 0x0000_0200 + + + +/*** Kernel/User Memory Areas *** + + Kernel memory starts at address 0x0. User memory starts at 'UMem_Lower' and extends to + the end of the address space. + + A distinction is made to protect against accesses to kernel memory while the processor + is in user mode. Lacking MMU hardware, these addresses are physical, not virtual. + This simple two-part division of the address space can be extended almost arbitrarily + in the Data Memory Controller. Note that there is currently no user/kernel space check + for the Instruction Memory, because it is assumed that instructions are in the kernel space. +*/ +parameter [31:0] UMem_Lower = 32'h08000000; + + + +/*** Processor Endianness *** + + The MIPS Configuration Register (CP0 Register 16 Select 0) specifies the processor's + endianness. A processor in user mode may switch to reverse endianness, which will be + the opposite of this parameter. +*/ +parameter Big_Endian = 1; + + + +/*** Encodings for MIPS32 Release 1 Architecture ***/ + + +/* Op Code Categories */ +parameter [5:0] Op_Type_R = 6'b00_0000; // Standard R-Type instructions +parameter [5:0] Op_Type_R2 = 6'b01_1100; // Extended R-Like instructions +parameter [5:0] Op_Type_BI = 6'b00_0001; // Branch/Trap extended instructions +parameter [5:0] Op_Type_CP0 = 6'b01_0000; // Coprocessor 0 instructions +parameter [5:0] Op_Type_CP1 = 6'b01_0001; // Coprocessor 1 instructions (not implemented) +parameter [5:0] Op_Type_CP2 = 6'b01_0010; // Coprocessor 2 instructions (not implemented) +parameter [5:0] Op_Type_CP3 = 6'b01_0011; // Coprocessor 3 instructions (not implemented) +// -------------------------------------- +parameter [5:0] Op_Add = Op_Type_R; +parameter [5:0] Op_Addi = 6'b00_1000; +parameter [5:0] Op_Addiu = 6'b00_1001; +parameter [5:0] Op_Addu = Op_Type_R; +parameter [5:0] Op_And = Op_Type_R; +parameter [5:0] Op_Andi = 6'b00_1100; +parameter [5:0] Op_Beq = 6'b00_0100; +parameter [5:0] Op_Bgez = Op_Type_BI; +parameter [5:0] Op_Bgezal = Op_Type_BI; +parameter [5:0] Op_Bgtz = 6'b00_0111; +parameter [5:0] Op_Blez = 6'b00_0110; +parameter [5:0] Op_Bltz = Op_Type_BI; +parameter [5:0] Op_Bltzal = Op_Type_BI; +parameter [5:0] Op_Bne = 6'b00_0101; +parameter [5:0] Op_Break = Op_Type_R; +parameter [5:0] Op_Clo = Op_Type_R2; +parameter [5:0] Op_Clz = Op_Type_R2; +parameter [5:0] Op_Div = Op_Type_R; +parameter [5:0] Op_Divu = Op_Type_R; +parameter [5:0] Op_Eret = Op_Type_CP0; +parameter [5:0] Op_J = 6'b00_0010; +parameter [5:0] Op_Jal = 6'b00_0011; +parameter [5:0] Op_Jalr = Op_Type_R; +parameter [5:0] Op_Jr = Op_Type_R; +parameter [5:0] Op_Lb = 6'b10_0000; +parameter [5:0] Op_Lbu = 6'b10_0100; +parameter [5:0] Op_Lh = 6'b10_0001; +parameter [5:0] Op_Lhu = 6'b10_0101; +parameter [5:0] Op_Ll = 6'b11_0000; +parameter [5:0] Op_Lui = 6'b00_1111; +parameter [5:0] Op_Lw = 6'b10_0011; +parameter [5:0] Op_Lwl = 6'b10_0010; +parameter [5:0] Op_Lwr = 6'b10_0110; +parameter [5:0] Op_Madd = Op_Type_R2; +parameter [5:0] Op_Maddu = Op_Type_R2; +parameter [5:0] Op_Mfc0 = Op_Type_CP0; +parameter [5:0] Op_Mfhi = Op_Type_R; +parameter [5:0] Op_Mflo = Op_Type_R; +parameter [5:0] Op_Movn = Op_Type_R; +parameter [5:0] Op_Movz = Op_Type_R; +parameter [5:0] Op_Msub = Op_Type_R2; +parameter [5:0] Op_Msubu = Op_Type_R2; +parameter [5:0] Op_Mtc0 = Op_Type_CP0; +parameter [5:0] Op_Mthi = Op_Type_R; +parameter [5:0] Op_Mtlo = Op_Type_R; +parameter [5:0] Op_Mul = Op_Type_R2; +parameter [5:0] Op_Mult = Op_Type_R; +parameter [5:0] Op_Multu = Op_Type_R; +parameter [5:0] Op_Nor = Op_Type_R; +parameter [5:0] Op_Or = Op_Type_R; +parameter [5:0] Op_Ori = 6'b00_1101; +parameter [5:0] Op_Pref = 6'b11_0011; // Prefetch does nothing in this implementation. +parameter [5:0] Op_Sb = 6'b10_1000; +parameter [5:0] Op_Sc = 6'b11_1000; +parameter [5:0] Op_Sh = 6'b10_1001; +parameter [5:0] Op_Sll = Op_Type_R; +parameter [5:0] Op_Sllv = Op_Type_R; +parameter [5:0] Op_Slt = Op_Type_R; +parameter [5:0] Op_Slti = 6'b00_1010; +parameter [5:0] Op_Sltiu = 6'b00_1011; +parameter [5:0] Op_Sltu = Op_Type_R; +parameter [5:0] Op_Sra = Op_Type_R; +parameter [5:0] Op_Srav = Op_Type_R; +parameter [5:0] Op_Srl = Op_Type_R; +parameter [5:0] Op_Srlv = Op_Type_R; +parameter [5:0] Op_Sub = Op_Type_R; +parameter [5:0] Op_Subu = Op_Type_R; +parameter [5:0] Op_Sw = 6'b10_1011; +parameter [5:0] Op_Swl = 6'b10_1010; +parameter [5:0] Op_Swr = 6'b10_1110; +parameter [5:0] Op_Syscall = Op_Type_R; +parameter [5:0] Op_Teq = Op_Type_R; +parameter [5:0] Op_Teqi = Op_Type_BI; +parameter [5:0] Op_Tge = Op_Type_R; +parameter [5:0] Op_Tgei = Op_Type_BI; +parameter [5:0] Op_Tgeiu = Op_Type_BI; +parameter [5:0] Op_Tgeu = Op_Type_R; +parameter [5:0] Op_Tlt = Op_Type_R; +parameter [5:0] Op_Tlti = Op_Type_BI; +parameter [5:0] Op_Tltiu = Op_Type_BI; +parameter [5:0] Op_Tltu = Op_Type_R; +parameter [5:0] Op_Tne = Op_Type_R; +parameter [5:0] Op_Tnei = Op_Type_BI; +parameter [5:0] Op_Xor = Op_Type_R; +parameter [5:0] Op_Xori = 6'b00_1110; + +/* Op Code Rt fields for Branches & Traps */ +parameter [4:0] OpRt_Bgez = 5'b00001; +parameter [4:0] OpRt_Bgezal = 5'b10001; +parameter [4:0] OpRt_Bltz = 5'b00000; +parameter [4:0] OpRt_Bltzal = 5'b10000; +parameter [4:0] OpRt_Teqi = 5'b01100; +parameter [4:0] OpRt_Tgei = 5'b01000; +parameter [4:0] OpRt_Tgeiu = 5'b01001; +parameter [4:0] OpRt_Tlti = 5'b01010; +parameter [4:0] OpRt_Tltiu = 5'b01011; +parameter [4:0] OpRt_Tnei = 5'b01110; + +/* Op Code Rs fields for Coprocessors */ +parameter [4:0] OpRs_MF = 5'b00000; +parameter [4:0] OpRs_MT = 5'b00100; + +/* Special handling for ERET */ +parameter [4:0] OpRs_ERET = 5'b10000; +parameter [5:0] Funct_ERET = 6'b011000; + +/* Function Codes for R-Type Op Codes */ +parameter [5:0] Funct_Add = 6'b10_0000; +parameter [5:0] Funct_Addu = 6'b10_0001; +parameter [5:0] Funct_And = 6'b10_0100; +parameter [5:0] Funct_Break = 6'b00_1101; +parameter [5:0] Funct_Clo = 6'b10_0001; // same as Addu +parameter [5:0] Funct_Clz = 6'b10_0000; // same as Add +parameter [5:0] Funct_Div = 6'b01_1010; +parameter [5:0] Funct_Divu = 6'b01_1011; +parameter [5:0] Funct_Jr = 6'b00_1000; +parameter [5:0] Funct_Jalr = 6'b00_1001; +parameter [5:0] Funct_Madd = 6'b00_0000; +parameter [5:0] Funct_Maddu = 6'b00_0001; +parameter [5:0] Funct_Mfhi = 6'b01_0000; +parameter [5:0] Funct_Mflo = 6'b01_0010; +parameter [5:0] Funct_Movn = 6'b00_1011; +parameter [5:0] Funct_Movz = 6'b00_1010; +parameter [5:0] Funct_Msub = 6'b00_0100; // same as Sllv +parameter [5:0] Funct_Msubu = 6'b00_0101; +parameter [5:0] Funct_Mthi = 6'b01_0001; +parameter [5:0] Funct_Mtlo = 6'b01_0011; +parameter [5:0] Funct_Mul = 6'b00_0010; // same as Srl +parameter [5:0] Funct_Mult = 6'b01_1000; +parameter [5:0] Funct_Multu = 6'b01_1001; +parameter [5:0] Funct_Nor = 6'b10_0111; +parameter [5:0] Funct_Or = 6'b10_0101; +parameter [5:0] Funct_Sll = 6'b00_0000; +parameter [5:0] Funct_Sllv = 6'b00_0100; +parameter [5:0] Funct_Slt = 6'b10_1010; +parameter [5:0] Funct_Sltu = 6'b10_1011; +parameter [5:0] Funct_Sra = 6'b00_0011; +parameter [5:0] Funct_Srav = 6'b00_0111; +parameter [5:0] Funct_Srl = 6'b00_0010; +parameter [5:0] Funct_Srlv = 6'b00_0110; +parameter [5:0] Funct_Sub = 6'b10_0010; +parameter [5:0] Funct_Subu = 6'b10_0011; +parameter [5:0] Funct_Syscall = 6'b00_1100; +parameter [5:0] Funct_Teq = 6'b11_0100; +parameter [5:0] Funct_Tge = 6'b11_0000; +parameter [5:0] Funct_Tgeu = 6'b11_0001; +parameter [5:0] Funct_Tlt = 6'b11_0010; +parameter [5:0] Funct_Tltu = 6'b11_0011; +parameter [5:0] Funct_Tne = 6'b11_0110; +parameter [5:0] Funct_Xor = 6'b10_0110; + +/* ALU Operations (Implementation) */ +parameter [4:0] AluOp_Add = 5'd1; +parameter [4:0] AluOp_Addu = 5'd0; +parameter [4:0] AluOp_And = 5'd2; +parameter [4:0] AluOp_Clo = 5'd3; +parameter [4:0] AluOp_Clz = 5'd4; +parameter [4:0] AluOp_Div = 5'd5; +parameter [4:0] AluOp_Divu = 5'd6; +parameter [4:0] AluOp_Madd = 5'd7; +parameter [4:0] AluOp_Maddu = 5'd8; +parameter [4:0] AluOp_Mfhi = 5'd9; +parameter [4:0] AluOp_Mflo = 5'd10; +parameter [4:0] AluOp_Msub = 5'd13; +parameter [4:0] AluOp_Msubu = 5'd14; +parameter [4:0] AluOp_Mthi = 5'd11; +parameter [4:0] AluOp_Mtlo = 5'd12; +parameter [4:0] AluOp_Mul = 5'd15; +parameter [4:0] AluOp_Mult = 5'd16; +parameter [4:0] AluOp_Multu = 5'd17; +parameter [4:0] AluOp_Nor = 5'd18; +parameter [4:0] AluOp_Or = 5'd19; +parameter [4:0] AluOp_Sll = 5'd20; +parameter [4:0] AluOp_Sllc = 5'd21; // Move this if another AluOp is needed +parameter [4:0] AluOp_Sllv = 5'd22; +parameter [4:0] AluOp_Slt = 5'd23; +parameter [4:0] AluOp_Sltu = 5'd24; +parameter [4:0] AluOp_Sra = 5'd25; +parameter [4:0] AluOp_Srav = 5'd26; +parameter [4:0] AluOp_Srl = 5'd27; +parameter [4:0] AluOp_Srlv = 5'd28; +parameter [4:0] AluOp_Sub = 5'd29; +parameter [4:0] AluOp_Subu = 5'd30; +parameter [4:0] AluOp_Xor = 5'd31; + + +// Movc:10->11, Trap:9->10, TrapCond:8->9, RegDst:7->8 + +/*** Datapath *** + + All Signals are Active High. Branching and Jump signals (determined by "PCSrc"), + as well as ALU operation signals ("ALUOp") are handled by the controller and are not found here. + + Bit Name Description + ------------------------------ + 15: PCSrc (Instruction Type) + 14: 11: Instruction is Jump to Register + 10: Instruction is Branch + 01: Instruction is Jump to Immediate + 00: Instruction does not branch nor jump + 13: Link (Link on Branch/Jump) + ------------------------------ + 12: ALUSrc (ALU Source) [0=ALU input B is 2nd register file output; 1=Immediate value] + 11: Movc (Conditional Move) + 10: Trap (Trap Instruction) + 9 : TrapCond (Trap Condition) [0=ALU result is 0; 1=ALU result is not 0] + 8 : RegDst (Register File Target) [0=Rt field; 1=Rd field] + ------------------------------ + 7 : LLSC (Load Linked or Store Conditional) + 6 : MemRead (Data Memory Read) + 5 : MemWrite (Data Memory Write) + 4 : MemHalf (Half Word Memory Access) + 3 : MemByte (Byte size Memory Access) + 2 : MemSignExtend (Sign Extend Read Memory) [0=Zero Extend; 1=Sign Extend] + ------------------------------ + 1 : RegWrite (Register File Write) + 0 : MemtoReg (Memory to Register) [0=Register File write data is ALU output; 1=Is Data Memory] + ------------------------------ +*/ +parameter [15:0] DP_None = 16'b000_00000_000000_00; // Instructions which require nothing of the main datapath. +parameter [15:0] DP_RType = 16'b000_00001_000000_10; // Standard R-Type +parameter [15:0] DP_IType = 16'b000_10000_000000_10; // Standard I-Type +parameter [15:0] DP_Branch = 16'b100_00000_000000_00; // Standard Branch +parameter [15:0] DP_BranchLink = 16'b101_00000_000000_10; // Branch and Link +parameter [15:0] DP_HiLoWr = 16'b000_00000_000000_00; // Write to Hi/Lo ALU register (Div,Divu,Mult,Multu,Mthi,Mtlo). Currently 'DP_None'. +parameter [15:0] DP_Jump = 16'b010_00000_000000_00; // Standard Jump +parameter [15:0] DP_JumpLink = 16'b011_00000_000000_10; // Jump and Link +parameter [15:0] DP_JumpLinkReg = 16'b111_00000_000000_10; // Jump and Link Register +parameter [15:0] DP_JumpReg = 16'b110_00000_000000_00; // Jump Register +parameter [15:0] DP_LoadByteS = 16'b000_10000_010011_11; // Load Byte Signed +parameter [15:0] DP_LoadByteU = 16'b000_10000_010010_11; // Load Byte Unsigned +parameter [15:0] DP_LoadHalfS = 16'b000_10000_010101_11; // Load Half Signed +parameter [15:0] DP_LoadHalfU = 16'b000_10000_010100_11; // Load Half Unsigned +parameter [15:0] DP_LoadWord = 16'b000_10000_010000_11; // Load Word +parameter [15:0] DP_ExtWrRt = 16'b000_00000_000000_10; // A DP-external write to Rt +parameter [15:0] DP_ExtWrRd = 16'b000_00001_000000_10; // A DP-external write to Rd +parameter [15:0] DP_Movc = 16'b000_01001_000000_10; // Conditional Move +parameter [15:0] DP_LoadLinked = 16'b000_10000_110000_11; // Load Linked +parameter [15:0] DP_StoreCond = 16'b000_10000_101000_11; // Store Conditional +parameter [15:0] DP_StoreByte = 16'b000_10000_001010_00; // Store Byte +parameter [15:0] DP_StoreHalf = 16'b000_10000_001100_00; // Store Half +parameter [15:0] DP_StoreWord = 16'b000_10000_001000_00; // Store Word +parameter [15:0] DP_TrapRegCNZ = 16'b000_00110_000000_00; // Trap using Rs and Rt, non-zero ALU (Tlt, Tltu, Tne) +parameter [15:0] DP_TrapRegCZ = 16'b000_00100_000000_00; // Trap using RS and Rt, zero ALU (Teq, Tge, Tgeu) +parameter [15:0] DP_TrapImmCNZ = 16'b000_10110_000000_00; // Trap using Rs and Imm, non-zero ALU (Tlti, Tltiu, Tnei) +parameter [15:0] DP_TrapImmCZ = 16'b000_10100_000000_00; // Trap using Rs and Imm, zero ALU (Teqi, Tgei, Tgeiu) +//-------------------------------------------------------- +parameter [15:0] DP_Add = DP_RType; +parameter [15:0] DP_Addi = DP_IType; +parameter [15:0] DP_Addiu = DP_IType; +parameter [15:0] DP_Addu = DP_RType; +parameter [15:0] DP_And = DP_RType; +parameter [15:0] DP_Andi = DP_IType; +parameter [15:0] DP_Beq = DP_Branch; +parameter [15:0] DP_Bgez = DP_Branch; +parameter [15:0] DP_Bgezal = DP_BranchLink; +parameter [15:0] DP_Bgtz = DP_Branch; +parameter [15:0] DP_Blez = DP_Branch; +parameter [15:0] DP_Bltz = DP_Branch; +parameter [15:0] DP_Bltzal = DP_BranchLink; +parameter [15:0] DP_Bne = DP_Branch; +parameter [15:0] DP_Break = DP_None; +parameter [15:0] DP_Clo = DP_RType; +parameter [15:0] DP_Clz = DP_RType; +parameter [15:0] DP_Div = DP_HiLoWr; +parameter [15:0] DP_Divu = DP_HiLoWr; +parameter [15:0] DP_Eret = DP_None; +parameter [15:0] DP_J = DP_Jump; +parameter [15:0] DP_Jal = DP_JumpLink; +parameter [15:0] DP_Jalr = DP_JumpLinkReg; +parameter [15:0] DP_Jr = DP_JumpReg; +parameter [15:0] DP_Lb = DP_LoadByteS; +parameter [15:0] DP_Lbu = DP_LoadByteU; +parameter [15:0] DP_Lh = DP_LoadHalfS; +parameter [15:0] DP_Lhu = DP_LoadHalfU; +parameter [15:0] DP_Ll = DP_LoadLinked; +parameter [15:0] DP_Lui = DP_IType; +parameter [15:0] DP_Lw = DP_LoadWord; +parameter [15:0] DP_Lwl = DP_LoadWord; +parameter [15:0] DP_Lwr = DP_LoadWord; +parameter [15:0] DP_Madd = DP_HiLoWr; +parameter [15:0] DP_Maddu = DP_HiLoWr; +parameter [15:0] DP_Mfc0 = DP_ExtWrRt; +parameter [15:0] DP_Mfhi = DP_ExtWrRd; +parameter [15:0] DP_Mflo = DP_ExtWrRd; +parameter [15:0] DP_Movn = DP_Movc; +parameter [15:0] DP_Movz = DP_Movc; +parameter [15:0] DP_Msub = DP_HiLoWr; +parameter [15:0] DP_Msubu = DP_HiLoWr; +parameter [15:0] DP_Mtc0 = DP_None; +parameter [15:0] DP_Mthi = DP_HiLoWr; +parameter [15:0] DP_Mtlo = DP_HiLoWr; +parameter [15:0] DP_Mul = DP_RType; +parameter [15:0] DP_Mult = DP_HiLoWr; +parameter [15:0] DP_Multu = DP_HiLoWr; +parameter [15:0] DP_Nor = DP_RType; +parameter [15:0] DP_Or = DP_RType; +parameter [15:0] DP_Ori = DP_IType; +parameter [15:0] DP_Pref = DP_None; // Not Implemented +parameter [15:0] DP_Sb = DP_StoreByte; +parameter [15:0] DP_Sc = DP_StoreCond; +parameter [15:0] DP_Sh = DP_StoreHalf; +parameter [15:0] DP_Sll = DP_RType; +parameter [15:0] DP_Sllv = DP_RType; +parameter [15:0] DP_Slt = DP_RType; +parameter [15:0] DP_Slti = DP_IType; +parameter [15:0] DP_Sltiu = DP_IType; +parameter [15:0] DP_Sltu = DP_RType; +parameter [15:0] DP_Sra = DP_RType; +parameter [15:0] DP_Srav = DP_RType; +parameter [15:0] DP_Srl = DP_RType; +parameter [15:0] DP_Srlv = DP_RType; +parameter [15:0] DP_Sub = DP_RType; +parameter [15:0] DP_Subu = DP_RType; +parameter [15:0] DP_Sw = DP_StoreWord; +parameter [15:0] DP_Swl = DP_StoreWord; +parameter [15:0] DP_Swr = DP_StoreWord; +parameter [15:0] DP_Syscall = DP_None; +parameter [15:0] DP_Teq = DP_TrapRegCZ; +parameter [15:0] DP_Teqi = DP_TrapImmCZ; +parameter [15:0] DP_Tge = DP_TrapRegCZ; +parameter [15:0] DP_Tgei = DP_TrapImmCZ; +parameter [15:0] DP_Tgeiu = DP_TrapImmCZ; +parameter [15:0] DP_Tgeu = DP_TrapRegCZ; +parameter [15:0] DP_Tlt = DP_TrapRegCNZ; +parameter [15:0] DP_Tlti = DP_TrapImmCNZ; +parameter [15:0] DP_Tltiu = DP_TrapImmCNZ; +parameter [15:0] DP_Tltu = DP_TrapRegCNZ; +parameter [15:0] DP_Tne = DP_TrapRegCNZ; +parameter [15:0] DP_Tnei = DP_TrapImmCNZ; +parameter [15:0] DP_Xor = DP_RType; +parameter [15:0] DP_Xori = DP_IType; + + + + +/*** Exception Information *** + + All signals are Active High. + + Bit Meaning + ------------ + 2: Instruction can cause exceptions in ID + 1: Instruction can cause exceptions in EX + 0: Instruction can cause exceptions in MEM +*/ +parameter [2:0] EXC_None = 3'b000; +parameter [2:0] EXC_ID = 3'b100; +parameter [2:0] EXC_EX = 3'b010; +parameter [2:0] EXC_MEM = 3'b001; +//-------------------------------- +parameter [2:0] EXC_Add = EXC_EX; +parameter [2:0] EXC_Addi = EXC_EX; +parameter [2:0] EXC_Addiu = EXC_None; +parameter [2:0] EXC_Addu = EXC_None; +parameter [2:0] EXC_And = EXC_None; +parameter [2:0] EXC_Andi = EXC_None; +parameter [2:0] EXC_Beq = EXC_None; +parameter [2:0] EXC_Bgez = EXC_None; +parameter [2:0] EXC_Bgezal = EXC_None; +parameter [2:0] EXC_Bgtz = EXC_None; +parameter [2:0] EXC_Blez = EXC_None; +parameter [2:0] EXC_Bltz = EXC_None; +parameter [2:0] EXC_Bltzal = EXC_None; +parameter [2:0] EXC_Bne = EXC_None; +parameter [2:0] EXC_Break = EXC_ID; +parameter [2:0] EXC_Clo = EXC_None; +parameter [2:0] EXC_Clz = EXC_None; +parameter [2:0] EXC_Div = EXC_None; +parameter [2:0] EXC_Divu = EXC_None; +parameter [2:0] EXC_Eret = EXC_ID; +parameter [2:0] EXC_J = EXC_None; +parameter [2:0] EXC_Jal = EXC_None; +parameter [2:0] EXC_Jalr = EXC_None; +parameter [2:0] EXC_Jr = EXC_None; +parameter [2:0] EXC_Lb = EXC_MEM; +parameter [2:0] EXC_Lbu = EXC_MEM; +parameter [2:0] EXC_Lh = EXC_MEM; +parameter [2:0] EXC_Lhu = EXC_MEM; +parameter [2:0] EXC_Ll = EXC_MEM; +parameter [2:0] EXC_Lui = EXC_None; +parameter [2:0] EXC_Lw = EXC_MEM; +parameter [2:0] EXC_Lwl = EXC_MEM; +parameter [2:0] EXC_Lwr = EXC_MEM; +parameter [2:0] EXC_Madd = EXC_None; +parameter [2:0] EXC_Maddu = EXC_None; +parameter [2:0] EXC_Mfc0 = EXC_ID; +parameter [2:0] EXC_Mfhi = EXC_None; +parameter [2:0] EXC_Mflo = EXC_None; +parameter [2:0] EXC_Movn = EXC_None; +parameter [2:0] EXC_Movz = EXC_None; +parameter [2:0] EXC_Msub = EXC_None; +parameter [2:0] EXC_Msubu = EXC_None; +parameter [2:0] EXC_Mtc0 = EXC_ID; +parameter [2:0] EXC_Mthi = EXC_None; +parameter [2:0] EXC_Mtlo = EXC_None; +parameter [2:0] EXC_Mul = EXC_None; +parameter [2:0] EXC_Mult = EXC_None; +parameter [2:0] EXC_Multu = EXC_None; +parameter [2:0] EXC_Nor = EXC_None; +parameter [2:0] EXC_Or = EXC_None; +parameter [2:0] EXC_Ori = EXC_None; +parameter [2:0] EXC_Pref = EXC_None; // XXX +parameter [2:0] EXC_Sb = EXC_MEM; +parameter [2:0] EXC_Sc = EXC_MEM; +parameter [2:0] EXC_Sh = EXC_MEM; +parameter [2:0] EXC_Sll = EXC_None; +parameter [2:0] EXC_Sllv = EXC_None; +parameter [2:0] EXC_Slt = EXC_None; +parameter [2:0] EXC_Slti = EXC_None; +parameter [2:0] EXC_Sltiu = EXC_None; +parameter [2:0] EXC_Sltu = EXC_None; +parameter [2:0] EXC_Sra = EXC_None; +parameter [2:0] EXC_Srav = EXC_None; +parameter [2:0] EXC_Srl = EXC_None; +parameter [2:0] EXC_Srlv = EXC_None; +parameter [2:0] EXC_Sub = EXC_EX; +parameter [2:0] EXC_Subu = EXC_None; +parameter [2:0] EXC_Sw = EXC_MEM; +parameter [2:0] EXC_Swl = EXC_MEM; +parameter [2:0] EXC_Swr = EXC_MEM; +parameter [2:0] EXC_Syscall = EXC_ID; +parameter [2:0] EXC_Teq = EXC_MEM; +parameter [2:0] EXC_Teqi = EXC_MEM; +parameter [2:0] EXC_Tge = EXC_MEM; +parameter [2:0] EXC_Tgei = EXC_MEM; +parameter [2:0] EXC_Tgeiu = EXC_MEM; +parameter [2:0] EXC_Tgeu = EXC_MEM; +parameter [2:0] EXC_Tlt = EXC_MEM; +parameter [2:0] EXC_Tlti = EXC_MEM; +parameter [2:0] EXC_Tltiu = EXC_MEM; +parameter [2:0] EXC_Tltu = EXC_MEM; +parameter [2:0] EXC_Tne = EXC_MEM; +parameter [2:0] EXC_Tnei = EXC_MEM; +parameter [2:0] EXC_Xor = EXC_None; +parameter [2:0] EXC_Xori = EXC_None; + + + + +/*** Hazard & Forwarding Datapath *** + + All signals are Active High. + + Bit Meaning + ------------ + 7: Wants Rs by ID + 6: Needs Rs by ID + 5: Wants Rt by ID + 4: Needs Rt by ID + 3: Wants Rs by EX + 2: Needs Rs by EX + 1: Wants Rt by EX + 0: Needs Rt by EX +*/ +parameter [7:0] HAZ_Nothing = 8'b00000000; // Jumps, Lui, Mfhi/lo, special, etc. +parameter [7:0] HAZ_IDRsIDRt = 8'b11110000; // Beq, Bne, Traps +parameter [7:0] HAZ_IDRs = 8'b11000000; // Most branches, Jumps to registers +parameter [7:0] HAZ_IDRt = 8'b00110000; // Mtc0 +parameter [7:0] HAZ_IDRtEXRs = 8'b10111100; // Movn, Movz +parameter [7:0] HAZ_EXRsEXRt = 8'b10101111; // Many R-Type ops +parameter [7:0] HAZ_EXRs = 8'b10001100; // Immediates: Loads, Clo/z, Mthi/lo, etc. +parameter [7:0] HAZ_EXRsWRt = 8'b10101110; // Stores +parameter [7:0] HAZ_EXRt = 8'b00100011; // Shifts using Shamt field +//----------------------------------------- +parameter [7:0] HAZ_Add = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Addi = HAZ_EXRs; +parameter [7:0] HAZ_Addiu = HAZ_EXRs; +parameter [7:0] HAZ_Addu = HAZ_EXRsEXRt; +parameter [7:0] HAZ_And = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Andi = HAZ_EXRs; +parameter [7:0] HAZ_Beq = HAZ_IDRsIDRt; +parameter [7:0] HAZ_Bgez = HAZ_IDRs; +parameter [7:0] HAZ_Bgezal = HAZ_IDRs; +parameter [7:0] HAZ_Bgtz = HAZ_IDRs; +parameter [7:0] HAZ_Blez = HAZ_IDRs; +parameter [7:0] HAZ_Bltz = HAZ_IDRs; +parameter [7:0] HAZ_Bltzal = HAZ_IDRs; +parameter [7:0] HAZ_Bne = HAZ_IDRsIDRt; +parameter [7:0] HAZ_Break = HAZ_Nothing; +parameter [7:0] HAZ_Clo = HAZ_EXRs; +parameter [7:0] HAZ_Clz = HAZ_EXRs; +parameter [7:0] HAZ_Div = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Divu = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Eret = HAZ_Nothing; +parameter [7:0] HAZ_J = HAZ_Nothing; +parameter [7:0] HAZ_Jal = HAZ_Nothing; +parameter [7:0] HAZ_Jalr = HAZ_IDRs; +parameter [7:0] HAZ_Jr = HAZ_IDRs; +parameter [7:0] HAZ_Lb = HAZ_EXRs; +parameter [7:0] HAZ_Lbu = HAZ_EXRs; +parameter [7:0] HAZ_Lh = HAZ_EXRs; +parameter [7:0] HAZ_Lhu = HAZ_EXRs; +parameter [7:0] HAZ_Ll = HAZ_EXRs; +parameter [7:0] HAZ_Lui = HAZ_Nothing; +parameter [7:0] HAZ_Lw = HAZ_EXRs; +parameter [7:0] HAZ_Lwl = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Lwr = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Madd = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Maddu = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Mfc0 = HAZ_Nothing; +parameter [7:0] HAZ_Mfhi = HAZ_Nothing; +parameter [7:0] HAZ_Mflo = HAZ_Nothing; +parameter [7:0] HAZ_Movn = HAZ_IDRtEXRs; +parameter [7:0] HAZ_Movz = HAZ_IDRtEXRs; +parameter [7:0] HAZ_Msub = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Msubu = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Mtc0 = HAZ_IDRt; +parameter [7:0] HAZ_Mthi = HAZ_EXRs; +parameter [7:0] HAZ_Mtlo = HAZ_EXRs; +parameter [7:0] HAZ_Mul = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Mult = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Multu = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Nor = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Or = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Ori = HAZ_EXRs; +parameter [7:0] HAZ_Pref = HAZ_Nothing; // XXX +parameter [7:0] HAZ_Sb = HAZ_EXRsWRt; +parameter [7:0] HAZ_Sc = HAZ_EXRsWRt; +parameter [7:0] HAZ_Sh = HAZ_EXRsWRt; +parameter [7:0] HAZ_Sll = HAZ_EXRt; +parameter [7:0] HAZ_Sllv = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Slt = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Slti = HAZ_EXRs; +parameter [7:0] HAZ_Sltiu = HAZ_EXRs; +parameter [7:0] HAZ_Sltu = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Sra = HAZ_EXRt; +parameter [7:0] HAZ_Srav = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Srl = HAZ_EXRt; +parameter [7:0] HAZ_Srlv = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Sub = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Subu = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Sw = HAZ_EXRsWRt; +parameter [7:0] HAZ_Swl = HAZ_EXRsWRt; +parameter [7:0] HAZ_Swr = HAZ_EXRsWRt; +parameter [7:0] HAZ_Syscall = HAZ_Nothing; +parameter [7:0] HAZ_Teq = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Teqi = HAZ_EXRs; +parameter [7:0] HAZ_Tge = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Tgei = HAZ_EXRs; +parameter [7:0] HAZ_Tgeiu = HAZ_EXRs; +parameter [7:0] HAZ_Tgeu = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Tlt = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Tlti = HAZ_EXRs; +parameter [7:0] HAZ_Tltiu = HAZ_EXRs; +parameter [7:0] HAZ_Tltu = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Tne = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Tnei = HAZ_EXRs; +parameter [7:0] HAZ_Xor = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Xori = HAZ_EXRs; + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/MemControl.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/MemControl.v new file mode 100755 index 0000000..6f4f4c4 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/MemControl.v @@ -0,0 +1,233 @@ +`timescale 1ns / 1ps +/* + * File : MemControl.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 24-Jun-2011 GEA Initial design. + * 2.0 28-Jun-2012 GEA Expanded from a simple byte/half/word unit to + * An advanced data memory controller capable of + * handling big/little endian, atomic and unaligned + * memory accesses. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * A Data Memory Controller which handles all read and write requests from the + * processor to data memory. All data accesses--whether big endian, little endian, + * byte, half, word, or unaligned transfers--are transformed into a simple read + * and write command to data memory over a 32-bit data bus, where the read command + * is one bit and the write command is 4 bits, one for each byte in the 32-bit word. + */ +module MemControl( + input clock, + input reset, + input [31:0] DataIn, // Data from CPU + input [31:0] Address, // From CPU + input [31:0] MReadData, // Data from Memory + input MemRead, // Memory Read command from CPU + input MemWrite, // Memory Write command from CPU + input DataMem_Ready, // Ready signal from Memory + input Byte, // Load/Store is Byte (8-bit) + input Half, // Load/Store is Half (16-bit) + input SignExtend, // Sub-word load should be sign extended + input KernelMode, // (Exception logic) + input ReverseEndian, // Reverse Endian Memory for User Mode + input LLSC, // (LLSC logic) + input ERET, // (LLSC logic) + input Left, // Unaligned Load/Store Word Left + input Right, // Unaligned Load/Store Word Right + input M_Exception_Stall, + input IF_Stall, // XXX Clean this up between this module and HAZ/FWD + output reg [31:0] DataOut, // Data to CPU + output [31:0] MWriteData, // Data to Memory + output reg [3:0] WriteEnable, // Write Enable to Memory for each of 4 bytes of Memory + output ReadEnable, // Read Enable to Memory + output M_Stall, + output EXC_AdEL, // Load Exception + output EXC_AdES // Store Exception + ); + + `include "MIPS_Parameters.v" + + /*** Reverse Endian Mode + Normal memory accesses in the processor are Big Endian. The endianness can be reversed + to Little Endian in User Mode only. + */ + wire BE = KernelMode | ~ReverseEndian; + + /*** Indicator that the current memory reference must be word-aligned ***/ + wire Word = ~(Half | Byte | Left | Right); + + // Exception Detection + wire EXC_KernelMem = ~KernelMode & (Address < UMem_Lower); + wire EXC_Word = Word & (Address[1] | Address[0]); + wire EXC_Half = Half & Address[0]; + assign EXC_AdEL = MemRead & (EXC_KernelMem | EXC_Word | EXC_Half); + assign EXC_AdES = MemWrite & (EXC_KernelMem | EXC_Word | EXC_Half); + + /*** Load Linked and Store Conditional logic *** + + A 32-bit register keeps track of the address for atomic Load Linked / Store Conditional + operations. This register can be updated during stalls since it is not visible to + forward stages. It does not need to be flushed during exceptions, since ERET destroys + the atomicity condition and there are no detrimental effects in an exception handler. + + The atomic condition is set with a Load Linked instruction, and cleared on an ERET + instruction or when any store instruction writes to one or more bytes covered by + the word address register. It does not update on a stall condition. + + The MIPS32 spec states that an ERET instruction between LL and SC will cause the + atomicity condition to fail. This implementation uses the ERET signal from the ID + stage, which means instruction sequences such as "LL SC" could appear to have an + ERET instruction between them even though they don't. One way to fix this is to pass + the ERET signal through the pipeline to the MEM stage. However, because of the nature + of LL/SC operations (they occur in a loop which checks the result at each iteration), + an ERET will normally never be inserted into the pipeline programmatically until the + LL/SC sequence has completed (exceptions such as interrupts can still cause ERET, but + they can still cause them in the LL SC sequence as well). In other words, by not passing + ERET through the pipeline, the only possible effect is a performance penalty. Also this + may be irrelevant since currently ERET stalls for forward stages which can cause exceptions, + which includes LL and SC. + */ + reg [29:0] LLSC_Address; + reg LLSC_Atomic; + wire LLSC_MemWrite_Mask; + + always @(posedge clock) begin + LLSC_Address <= (reset) ? 30'b0 : (MemRead & LLSC) ? Address[31:2] : LLSC_Address; + end + + always @(posedge clock) begin + if (reset) begin + LLSC_Atomic <= 0; + end + else if (MemRead) begin + LLSC_Atomic <= (LLSC) ? 1 : LLSC_Atomic; + end + // XXX GEA Bug for Ganesh: remove "& ~IF_Stall" from below, then SC will always fail: + else if (ERET | (~M_Stall & ~IF_Stall & MemWrite & (Address[31:2] == LLSC_Address))) begin + LLSC_Atomic <= 0; + end + else begin + LLSC_Atomic <= LLSC_Atomic; + end + end + assign LLSC_MemWrite_Mask = (LLSC & MemWrite & (~LLSC_Atomic | (Address[31:2] != LLSC_Address))); + + wire WriteCondition = MemWrite & ~(EXC_KernelMem | EXC_Word | EXC_Half) & ~LLSC_MemWrite_Mask; + wire ReadCondition = MemRead & ~(EXC_KernelMem | EXC_Word | EXC_Half); + + reg RW_Mask; + always @(posedge clock) begin + RW_Mask <= (reset) ? 0 : (((MemWrite | MemRead) & DataMem_Ready) ? 1 : ((~M_Stall & ~IF_Stall) ? 0 : RW_Mask)); + end + assign M_Stall = ReadEnable | (WriteEnable != 4'b0000) | DataMem_Ready | M_Exception_Stall; + assign ReadEnable = ReadCondition & ~RW_Mask; + + wire Half_Access_L = (Address[1] ^ BE); + wire Half_Access_R = (Address[1] ~^ BE); + wire Byte_Access_LL = Half_Access_L & (Address[1] ~^ Address[0]); + wire Byte_Access_LM = Half_Access_L & (Address[0] ~^ BE); + wire Byte_Access_RM = Half_Access_R & (Address[0] ^ BE); + wire Byte_Access_RR = Half_Access_R & (Address[1] ~^ Address[0]); + + // Write-Enable Signals to Memory + always @(*) begin + if (WriteCondition & ~RW_Mask) begin + if (Byte) begin + WriteEnable[3] <= Byte_Access_LL; + WriteEnable[2] <= Byte_Access_LM; + WriteEnable[1] <= Byte_Access_RM; + WriteEnable[0] <= Byte_Access_RR; + end + else if (Half) begin + WriteEnable[3] <= Half_Access_L; + WriteEnable[2] <= Half_Access_L; + WriteEnable[1] <= Half_Access_R; + WriteEnable[0] <= Half_Access_R; + end + else if (Left) begin + case (Address[1:0]) + 2'b00 : WriteEnable <= (BE) ? 4'b1111 : 4'b0001; + 2'b01 : WriteEnable <= (BE) ? 4'b0111 : 4'b0011; + 2'b10 : WriteEnable <= (BE) ? 4'b0011 : 4'b0111; + 2'b11 : WriteEnable <= (BE) ? 4'b0001 : 4'b1111; + endcase + end + else if (Right) begin + case (Address[1:0]) + 2'b00 : WriteEnable <= (BE) ? 4'b1000 : 4'b1111; + 2'b01 : WriteEnable <= (BE) ? 4'b1100 : 4'b1110; + 2'b10 : WriteEnable <= (BE) ? 4'b1110 : 4'b1100; + 2'b11 : WriteEnable <= (BE) ? 4'b1111 : 4'b1000; + endcase + end + else begin + WriteEnable <= 4'b1111; + end + end + else begin + WriteEnable <= 4'b0000; + end + end + + // Data Going to Memory + assign MWriteData[31:24] = (Byte) ? DataIn[7:0] : ((Half) ? DataIn[15:8] : DataIn[31:24]); + assign MWriteData[23:16] = (Byte | Half) ? DataIn[7:0] : DataIn[23:16]; + assign MWriteData[15:8] = (Byte) ? DataIn[7:0] : DataIn[15:8]; + assign MWriteData[7:0] = DataIn[7:0]; + + // Data Read from Memory + always @(*) begin + if (Byte) begin + if (Byte_Access_LL) begin + DataOut <= (SignExtend & MReadData[31]) ? {24'hFFFFFF, MReadData[31:24]} : {24'h000000, MReadData[31:24]}; + end + else if (Byte_Access_LM) begin + DataOut <= (SignExtend & MReadData[23]) ? {24'hFFFFFF, MReadData[23:16]} : {24'h000000, MReadData[23:16]}; + end + else if (Byte_Access_RM) begin + DataOut <= (SignExtend & MReadData[15]) ? {24'hFFFFFF, MReadData[15:8]} : {24'h000000, MReadData[15:8]}; + end + else begin + DataOut <= (SignExtend & MReadData[7]) ? {24'hFFFFFF, MReadData[7:0]} : {24'h000000, MReadData[7:0]}; + end + end + else if (Half) begin + if (Half_Access_L) begin + DataOut <= (SignExtend & MReadData[31]) ? {16'hFFFF, MReadData[31:16]} : {16'h0000, MReadData[31:16]}; + end + else begin + DataOut <= (SignExtend & MReadData[15]) ? {16'hFFFF, MReadData[15:0]} : {16'h0000, MReadData[15:0]}; + end + end + else if (LLSC & MemWrite) begin + DataOut <= (LLSC_Atomic & (Address[31:2] == LLSC_Address)) ? 32'h0000_0001 : 32'h0000_0000; + end + else if (Left) begin + case (Address[1:0]) + 2'b00 : DataOut <= (BE) ? MReadData : {MReadData[7:0], DataIn[23:0]}; + 2'b01 : DataOut <= (BE) ? {MReadData[23:0], DataIn[7:0]} : {MReadData[15:0], DataIn[15:0]}; + 2'b10 : DataOut <= (BE) ? {MReadData[15:0], DataIn[15:0]} : {MReadData[23:0], DataIn[7:0]}; + 2'b11 : DataOut <= (BE) ? {MReadData[7:0], DataIn[23:0]} : MReadData; + endcase + end + else if (Right) begin + case (Address[1:0]) + 2'b00 : DataOut <= (BE) ? {DataIn[31:8], MReadData[31:24]} : MReadData; + 2'b01 : DataOut <= (BE) ? {DataIn[31:16], MReadData[31:16]} : {DataIn[31:24], MReadData[31:8]}; + 2'b10 : DataOut <= (BE) ? {DataIn[31:24], MReadData[31:8]} : {DataIn[31:16], MReadData[31:16]}; + 2'b11 : DataOut <= (BE) ? MReadData : {DataIn[31:8], MReadData[31:24]}; + endcase + end + else begin + DataOut <= MReadData; + end + end + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/Mux2.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/Mux2.v new file mode 100755 index 0000000..a2eb1d8 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/Mux2.v @@ -0,0 +1,26 @@ +`timescale 1ns / 1ps +/* + * File : Mux2.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 7-Jun-2011 GEA Initial design. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * A 2-input Mux of variable width, defaulting to 32-bit width. + */ +module Mux2 #(parameter WIDTH = 32)( + input sel, + input [(WIDTH-1):0] in0, in1, + output [(WIDTH-1):0] out + ); + + assign out = (sel) ? in1 : in0; + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/Mux4.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/Mux4.v new file mode 100755 index 0000000..38083f3 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/Mux4.v @@ -0,0 +1,33 @@ +`timescale 1ns / 1ps +/* + * File : Mux4.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 7-Jun-2011 GEA Initial design. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * A 4-input Mux of variable width, defaulting to 32-bit width. + */ +module Mux4 #(parameter WIDTH = 32)( + input [1:0] sel, + input [(WIDTH-1):0] in0, in1, in2, in3, + output reg [(WIDTH-1):0] out + ); + + always @(*) begin + case (sel) + 2'b00 : out <= in0; + 2'b01 : out <= in1; + 2'b10 : out <= in2; + 2'b11 : out <= in3; + endcase + end + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/Processor.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/Processor.v new file mode 100755 index 0000000..46c2b85 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/Processor.v @@ -0,0 +1,679 @@ +`timescale 1ns / 1ps +/* + * File : Processor.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 23-Jul-2011 GEA Initial design. + * 2.0 26-May-2012 GEA Release version with CP0. + * 2.01 1-Nov-2012 GEA Fixed issue with Jal. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * The top-level MIPS32 Processor. This file is mostly the instantiation + * and wiring of the building blocks of the processor according to the + * hardware design diagram. It contains very little logic itself. + */ +module Processor( + input clock, + input reset, + input [4:0] Interrupts, // 5 general-purpose hardware interrupts + input NMI, // Non-maskable interrupt + // Data Memory Interface + input [31:0] DataMem_In, + input DataMem_Ready, + output DataMem_Read, + output [3:0] DataMem_Write, // 4-bit Write, one for each byte in word. + output [29:0] DataMem_Address, // Addresses are words, not bytes. + output [31:0] DataMem_Out, + // Instruction Memory Interface + input [31:0] InstMem_In, + output [29:0] InstMem_Address, // Addresses are words, not bytes. + input InstMem_Ready, + output InstMem_Read, + output [7:0] IP // Pending interrupts (diagnostic) + ); + + `include "MIPS_Parameters.v" + + + /*** MIPS Instruction and Components (ID Stage) ***/ + wire [31:0] Instruction; + wire [5:0] OpCode = Instruction[31:26]; + wire [4:0] Rs = Instruction[25:21]; + wire [4:0] Rt = Instruction[20:16]; + wire [4:0] Rd = Instruction[15:11]; + wire [5:0] Funct = Instruction[5:0]; + wire [15:0] Immediate = Instruction[15:0]; + wire [25:0] JumpAddress = Instruction[25:0]; + wire [2:0] Cp0_Sel = Instruction[2:0]; + + /*** IF (Instruction Fetch) Signals ***/ + wire IF_Stall, IF_Flush; + wire IF_EXC_AdIF; + wire IF_Exception_Stall; + wire IF_Exception_Flush; + wire IF_IsBDS; + wire [31:0] IF_PCAdd4, IF_PC_PreExc, IF_PCIn, IF_PCOut, IF_Instruction; + + /*** ID (Instruction Decode) Signals ***/ + wire ID_Stall; + wire [1:0] ID_PCSrc; + wire [1:0] ID_RsFwdSel, ID_RtFwdSel; + wire ID_Link, ID_Movn, ID_Movz; + wire ID_SignExtend; + wire ID_LLSC; + wire ID_RegDst, ID_ALUSrcImm, ID_MemWrite, ID_MemRead, ID_MemByte, ID_MemHalf, ID_MemSignExtend, ID_RegWrite, ID_MemtoReg; + wire [4:0] ID_ALUOp; + wire ID_Mfc0, ID_Mtc0, ID_Eret; + wire ID_NextIsDelay; + wire ID_CanErr, ID_ID_CanErr, ID_EX_CanErr, ID_M_CanErr; + wire ID_KernelMode; + wire ID_ReverseEndian; + wire ID_Trap, ID_TrapCond; + wire ID_EXC_Sys, ID_EXC_Bp, ID_EXC_RI; + wire ID_Exception_Stall; + wire ID_Exception_Flush; + wire ID_PCSrc_Exc; + wire [31:0] ID_ExceptionPC; + wire ID_CP1, ID_CP2, ID_CP3; + wire [31:0] ID_PCAdd4; + wire [31:0] ID_ReadData1_RF, ID_ReadData1_End; + wire [31:0] ID_ReadData2_RF, ID_ReadData2_End; + wire [31:0] CP0_RegOut; + wire ID_CmpEQ, ID_CmpGZ, ID_CmpLZ, ID_CmpGEZ, ID_CmpLEZ; + wire [29:0] ID_SignExtImm = (ID_SignExtend & Immediate[15]) ? {14'h3FFF, Immediate} : {14'h0000, Immediate}; + wire [31:0] ID_ImmLeftShift2 = {ID_SignExtImm[29:0], 2'b00}; + wire [31:0] ID_JumpAddress = {ID_PCAdd4[31:28], JumpAddress[25:0], 2'b00}; + wire [31:0] ID_BranchAddress; + wire [31:0] ID_RestartPC; + wire ID_IsBDS; + wire ID_Left, ID_Right; + wire ID_IsFlushed; + + /*** EX (Execute) Signals ***/ + wire EX_ALU_Stall, EX_Stall; + wire [1:0] EX_RsFwdSel, EX_RtFwdSel; + wire EX_Link; + wire [1:0] EX_LinkRegDst; + wire EX_ALUSrcImm; + wire [4:0] EX_ALUOp; + wire EX_Movn, EX_Movz; + wire EX_LLSC; + wire EX_MemRead, EX_MemWrite, EX_MemByte, EX_MemHalf, EX_MemSignExtend, EX_RegWrite, EX_MemtoReg; + wire [4:0] EX_Rs, EX_Rt; + wire EX_WantRsByEX, EX_NeedRsByEX, EX_WantRtByEX, EX_NeedRtByEX; + wire EX_Trap, EX_TrapCond; + wire EX_CanErr, EX_EX_CanErr, EX_M_CanErr; + wire EX_KernelMode; + wire EX_ReverseEndian; + wire EX_Exception_Stall; + wire EX_Exception_Flush; + wire [31:0] EX_ReadData1_PR, EX_ReadData1_Fwd, EX_ReadData2_PR, EX_ReadData2_Fwd, EX_ReadData2_Imm; + wire [31:0] EX_SignExtImm; + wire [4:0] EX_Rd, EX_RtRd, EX_Shamt; + wire [31:0] EX_ALUResult; + wire EX_BZero; + wire EX_EXC_Ov; + wire [31:0] EX_RestartPC; + wire EX_IsBDS; + wire EX_Left, EX_Right; + + /*** MEM (Memory) Signals ***/ + wire M_Stall, M_Stall_Controller; + wire M_LLSC; + wire M_MemRead, M_MemWrite, M_MemByte, M_MemHalf, M_MemSignExtend; + wire M_RegWrite, M_MemtoReg; + wire M_WriteDataFwdSel; + wire M_EXC_AdEL, M_EXC_AdES; + wire M_M_CanErr; + wire M_KernelMode; + wire M_ReverseEndian; + wire M_Trap, M_TrapCond; + wire M_EXC_Tr; + wire M_Exception_Flush; + wire [31:0] M_ALUResult, M_ReadData2_PR; + wire [4:0] M_RtRd; + wire [31:0] M_MemReadData; + wire [31:0] M_RestartPC; + wire M_IsBDS; + wire [31:0] M_WriteData_Pre; + wire M_Left, M_Right; + wire M_Exception_Stall; + + /*** WB (Writeback) Signals ***/ + wire WB_Stall, WB_RegWrite; + wire [31:0] WB_ReadData, WB_ALUResult; + wire [4:0] WB_RtRd; + wire [31:0] WB_WriteData; + + /*** Other Signals ***/ + wire [7:0] ID_DP_Hazards, HAZ_DP_Hazards; + + /*** Assignments ***/ + assign IF_Instruction = (IF_Stall) ? 32'h00000000 : InstMem_In; + assign IF_IsBDS = ID_NextIsDelay; + assign HAZ_DP_Hazards = {ID_DP_Hazards[7:4], EX_WantRsByEX, EX_NeedRsByEX, EX_WantRtByEX, EX_NeedRtByEX}; + assign IF_EXC_AdIF = IF_PCOut[1] | IF_PCOut[0]; + assign ID_CanErr = ID_ID_CanErr | ID_EX_CanErr | ID_M_CanErr; + assign EX_CanErr = EX_EX_CanErr | EX_M_CanErr; + assign M_CanErr = M_M_CanErr; + + // External Memory Interface + reg IRead, IReadMask; + assign InstMem_Address = IF_PCOut[31:2]; + assign DataMem_Address = M_ALUResult[31:2]; + always @(posedge clock) begin + IRead <= (reset) ? 1 : ~InstMem_Ready; + IReadMask <= (reset) ? 0 : ((IRead & InstMem_Ready) ? 1 : ((~IF_Stall) ? 0 : IReadMask)); + end + assign InstMem_Read = IRead & ~IReadMask; + + + /*** Datapath Controller ***/ + Control Controller ( + .ID_Stall (ID_Stall), + .OpCode (OpCode), + .Funct (Funct), + .Rs (Rs), + .Rt (Rt), + .Cmp_EQ (ID_CmpEQ), + .Cmp_GZ (ID_CmpGZ), + .Cmp_GEZ (ID_CmpGEZ), + .Cmp_LZ (ID_CmpLZ), + .Cmp_LEZ (ID_CmpLEZ), + .IF_Flush (IF_Flush), + .DP_Hazards (ID_DP_Hazards), + .PCSrc (ID_PCSrc), + .SignExtend (ID_SignExtend), + .Link (ID_Link), + .Movn (ID_Movn), + .Movz (ID_Movz), + .Mfc0 (ID_Mfc0), + .Mtc0 (ID_Mtc0), + .CP1 (ID_CP1), + .CP2 (ID_CP2), + .CP3 (ID_CP3), + .Eret (ID_Eret), + .Trap (ID_Trap), + .TrapCond (ID_TrapCond), + .EXC_Sys (ID_EXC_Sys), + .EXC_Bp (ID_EXC_Bp), + .EXC_RI (ID_EXC_RI), + .ID_CanErr (ID_ID_CanErr), + .EX_CanErr (ID_EX_CanErr), + .M_CanErr (ID_M_CanErr), + .NextIsDelay (ID_NextIsDelay), + .RegDst (ID_RegDst), + .ALUSrcImm (ID_ALUSrcImm), + .ALUOp (ID_ALUOp), + .LLSC (ID_LLSC), + .MemWrite (ID_MemWrite), + .MemRead (ID_MemRead), + .MemByte (ID_MemByte), + .MemHalf (ID_MemHalf), + .MemSignExtend (ID_MemSignExtend), + .Left (ID_Left), + .Right (ID_Right), + .RegWrite (ID_RegWrite), + .MemtoReg (ID_MemtoReg) + ); + + /*** Hazard and Forward Control Unit ***/ + Hazard_Detection HazardControl ( + .DP_Hazards (HAZ_DP_Hazards), + .ID_Rs (Rs), + .ID_Rt (Rt), + .EX_Rs (EX_Rs), + .EX_Rt (EX_Rt), + .EX_RtRd (EX_RtRd), + .MEM_RtRd (M_RtRd), + .WB_RtRd (WB_RtRd), + .EX_Link (EX_Link), + .EX_RegWrite (EX_RegWrite), + .MEM_RegWrite (M_RegWrite), + .WB_RegWrite (WB_RegWrite), + .MEM_MemRead (M_MemRead), + .MEM_MemWrite (M_MemWrite), + .InstMem_Read (InstMem_Read), + .InstMem_Ready (InstMem_Ready), + .Mfc0 (ID_Mfc0), + .IF_Exception_Stall (IF_Exception_Stall), + .ID_Exception_Stall (ID_Exception_Stall), + .EX_Exception_Stall (EX_Exception_Stall), + .EX_ALU_Stall (EX_ALU_Stall), + .M_Stall_Controller (M_Stall_Controller), + .IF_Stall (IF_Stall), + .ID_Stall (ID_Stall), + .EX_Stall (EX_Stall), + .M_Stall (M_Stall), + .WB_Stall (WB_Stall), + .ID_RsFwdSel (ID_RsFwdSel), + .ID_RtFwdSel (ID_RtFwdSel), + .EX_RsFwdSel (EX_RsFwdSel), + .EX_RtFwdSel (EX_RtFwdSel), + .M_WriteDataFwdSel (M_WriteDataFwdSel) + ); + + /*** Coprocessor 0: Exceptions and Interrupts ***/ + CPZero CP0 ( + .clock (clock), + .Mfc0 (ID_Mfc0), + .Mtc0 (ID_Mtc0), + .IF_Stall (IF_Stall), + .ID_Stall (ID_Stall), + .COP1 (ID_CP1), + .COP2 (ID_CP2), + .COP3 (ID_CP3), + .ERET (ID_Eret), + .Rd (Rd), + .Sel (Cp0_Sel), + .Reg_In (ID_ReadData2_End), + .Reg_Out (CP0_RegOut), + .KernelMode (ID_KernelMode), + .ReverseEndian (ID_ReverseEndian), + .Int (Interrupts), + .reset (reset), + .EXC_NMI (NMI), + .EXC_AdIF (IF_EXC_AdIF), + .EXC_AdEL (M_EXC_AdEL), + .EXC_AdES (M_EXC_AdES), + .EXC_Ov (EX_EXC_Ov), + .EXC_Tr (M_EXC_Tr), + .EXC_Sys (ID_EXC_Sys), + .EXC_Bp (ID_EXC_Bp), + .EXC_RI (ID_EXC_RI), + .ID_RestartPC (ID_RestartPC), + .EX_RestartPC (EX_RestartPC), + .M_RestartPC (M_RestartPC), + .ID_IsFlushed (ID_IsFlushed), + .IF_IsBD (IF_IsBDS), + .ID_IsBD (ID_IsBDS), + .EX_IsBD (EX_IsBDS), + .M_IsBD (M_IsBDS), + .BadAddr_M (M_ALUResult), + .BadAddr_IF (IF_PCOut), + .ID_CanErr (ID_CanErr), + .EX_CanErr (EX_CanErr), + .M_CanErr (M_CanErr), + .IF_Exception_Stall (IF_Exception_Stall), + .ID_Exception_Stall (ID_Exception_Stall), + .EX_Exception_Stall (EX_Exception_Stall), + .M_Exception_Stall (M_Exception_Stall), + .IF_Exception_Flush (IF_Exception_Flush), + .ID_Exception_Flush (ID_Exception_Flush), + .EX_Exception_Flush (EX_Exception_Flush), + .M_Exception_Flush (M_Exception_Flush), + .Exc_PC_Sel (ID_PCSrc_Exc), + .Exc_PC_Out (ID_ExceptionPC), + .IP (IP) + ); + + /*** PC Source Non-Exception Mux ***/ + Mux4 #(.WIDTH(32)) PCSrcStd_Mux ( + .sel (ID_PCSrc), + .in0 (IF_PCAdd4), + .in1 (ID_JumpAddress), + .in2 (ID_BranchAddress), + .in3 (ID_ReadData1_End), + .out (IF_PC_PreExc) + ); + + /*** PC Source Exception Mux ***/ + Mux2 #(.WIDTH(32)) PCSrcExc_Mux ( + .sel (ID_PCSrc_Exc), + .in0 (IF_PC_PreExc), + .in1 (ID_ExceptionPC), + .out (IF_PCIn) + ); + + /*** Program Counter (MIPS spec is 0xBFC00000 starting address) ***/ + Register #(.WIDTH(32), .INIT(EXC_Vector_Base_Reset)) PC ( + .clock (clock), + .reset (reset), + //.enable (~IF_Stall), // XXX verify. HERE. Was 1 but on stall latches PC+4, ad nauseum. + .enable (~(IF_Stall | ID_Stall)), + .D (IF_PCIn), + .Q (IF_PCOut) + ); + + /*** PC +4 Adder ***/ + Add PC_Add4 ( + .A (IF_PCOut), + .B (32'h00000004), + .C (IF_PCAdd4) + ); + + /*** Instruction Fetch -> Instruction Decode Stage Register ***/ + IFID_Stage IFID ( + .clock (clock), + .reset (reset), + .IF_Flush (IF_Exception_Flush | IF_Flush), + .IF_Stall (IF_Stall), + .ID_Stall (ID_Stall), + .IF_Instruction (IF_Instruction), + .IF_PCAdd4 (IF_PCAdd4), + .IF_PC (IF_PCOut), + .IF_IsBDS (IF_IsBDS), + .ID_Instruction (Instruction), + .ID_PCAdd4 (ID_PCAdd4), + .ID_RestartPC (ID_RestartPC), + .ID_IsBDS (ID_IsBDS), + .ID_IsFlushed (ID_IsFlushed) + ); + + /*** Register File ***/ + RegisterFile RegisterFile ( + .clock (clock), + .reset (reset), + .ReadReg1 (Rs), + .ReadReg2 (Rt), + .WriteReg (WB_RtRd), + .WriteData (WB_WriteData), + .RegWrite (WB_RegWrite), + .ReadData1 (ID_ReadData1_RF), + .ReadData2 (ID_ReadData2_RF) + ); + + /*** ID Rs Forwarding/Link Mux ***/ + Mux4 #(.WIDTH(32)) IDRsFwd_Mux ( + .sel (ID_RsFwdSel), + .in0 (ID_ReadData1_RF), + .in1 (M_ALUResult), + .in2 (WB_WriteData), + .in3 (32'hxxxxxxxx), + .out (ID_ReadData1_End) + ); + + /*** ID Rt Forwarding/CP0 Mfc0 Mux ***/ + Mux4 #(.WIDTH(32)) IDRtFwd_Mux ( + .sel (ID_RtFwdSel), + .in0 (ID_ReadData2_RF), + .in1 (M_ALUResult), + .in2 (WB_WriteData), + .in3 (CP0_RegOut), + .out (ID_ReadData2_End) + ); + + /*** Condition Compare Unit ***/ + Compare Compare ( + .A (ID_ReadData1_End), + .B (ID_ReadData2_End), + .EQ (ID_CmpEQ), + .GZ (ID_CmpGZ), + .LZ (ID_CmpLZ), + .GEZ (ID_CmpGEZ), + .LEZ (ID_CmpLEZ) + ); + + /*** Branch Address Adder ***/ + Add BranchAddress_Add ( + .A (ID_PCAdd4), + .B (ID_ImmLeftShift2), + .C (ID_BranchAddress) + ); + + /*** Instruction Decode -> Execute Pipeline Stage ***/ + IDEX_Stage IDEX ( + .clock (clock), + .reset (reset), + .ID_Flush (ID_Exception_Flush), + .ID_Stall (ID_Stall), + .EX_Stall (EX_Stall), + .ID_Link (ID_Link), + .ID_RegDst (ID_RegDst), + .ID_ALUSrcImm (ID_ALUSrcImm), + .ID_ALUOp (ID_ALUOp), + .ID_Movn (ID_Movn), + .ID_Movz (ID_Movz), + .ID_LLSC (ID_LLSC), + .ID_MemRead (ID_MemRead), + .ID_MemWrite (ID_MemWrite), + .ID_MemByte (ID_MemByte), + .ID_MemHalf (ID_MemHalf), + .ID_MemSignExtend (ID_MemSignExtend), + .ID_Left (ID_Left), + .ID_Right (ID_Right), + .ID_RegWrite (ID_RegWrite), + .ID_MemtoReg (ID_MemtoReg), + .ID_ReverseEndian (ID_ReverseEndian), + .ID_Rs (Rs), + .ID_Rt (Rt), + .ID_WantRsByEX (ID_DP_Hazards[3]), + .ID_NeedRsByEX (ID_DP_Hazards[2]), + .ID_WantRtByEX (ID_DP_Hazards[1]), + .ID_NeedRtByEX (ID_DP_Hazards[0]), + .ID_KernelMode (ID_KernelMode), + .ID_RestartPC (ID_RestartPC), + .ID_IsBDS (ID_IsBDS), + .ID_Trap (ID_Trap), + .ID_TrapCond (ID_TrapCond), + .ID_EX_CanErr (ID_EX_CanErr), + .ID_M_CanErr (ID_M_CanErr), + .ID_ReadData1 (ID_ReadData1_End), + .ID_ReadData2 (ID_ReadData2_End), + .ID_SignExtImm (ID_SignExtImm[16:0]), + .EX_Link (EX_Link), + .EX_LinkRegDst (EX_LinkRegDst), + .EX_ALUSrcImm (EX_ALUSrcImm), + .EX_ALUOp (EX_ALUOp), + .EX_Movn (EX_Movn), + .EX_Movz (EX_Movz), + .EX_LLSC (EX_LLSC), + .EX_MemRead (EX_MemRead), + .EX_MemWrite (EX_MemWrite), + .EX_MemByte (EX_MemByte), + .EX_MemHalf (EX_MemHalf), + .EX_MemSignExtend (EX_MemSignExtend), + .EX_Left (EX_Left), + .EX_Right (EX_Right), + .EX_RegWrite (EX_RegWrite), + .EX_MemtoReg (EX_MemtoReg), + .EX_ReverseEndian (EX_ReverseEndian), + .EX_Rs (EX_Rs), + .EX_Rt (EX_Rt), + .EX_WantRsByEX (EX_WantRsByEX), + .EX_NeedRsByEX (EX_NeedRsByEX), + .EX_WantRtByEX (EX_WantRtByEX), + .EX_NeedRtByEX (EX_NeedRtByEX), + .EX_KernelMode (EX_KernelMode), + .EX_RestartPC (EX_RestartPC), + .EX_IsBDS (EX_IsBDS), + .EX_Trap (EX_Trap), + .EX_TrapCond (EX_TrapCond), + .EX_EX_CanErr (EX_EX_CanErr), + .EX_M_CanErr (EX_M_CanErr), + .EX_ReadData1 (EX_ReadData1_PR), + .EX_ReadData2 (EX_ReadData2_PR), + .EX_SignExtImm (EX_SignExtImm), + .EX_Rd (EX_Rd), + .EX_Shamt (EX_Shamt) + ); + + /*** EX Rs Forwarding Mux ***/ + Mux4 #(.WIDTH(32)) EXRsFwd_Mux ( + .sel (EX_RsFwdSel), + .in0 (EX_ReadData1_PR), + .in1 (M_ALUResult), + .in2 (WB_WriteData), + .in3 (EX_RestartPC), + .out (EX_ReadData1_Fwd) + ); + + /*** EX Rt Forwarding / Link Mux ***/ + Mux4 #(.WIDTH(32)) EXRtFwdLnk_Mux ( + .sel (EX_RtFwdSel), + .in0 (EX_ReadData2_PR), + .in1 (M_ALUResult), + .in2 (WB_WriteData), + .in3 (32'h00000008), + .out (EX_ReadData2_Fwd) + ); + + /*** EX ALU Immediate Mux ***/ + Mux2 #(.WIDTH(32)) EXALUImm_Mux ( + .sel (EX_ALUSrcImm), + .in0 (EX_ReadData2_Fwd), + .in1 (EX_SignExtImm), + .out (EX_ReadData2_Imm) + ); + + /*** EX RtRd / Link Mux ***/ + Mux4 #(.WIDTH(5)) EXRtRdLnk_Mux ( + .sel (EX_LinkRegDst), + .in0 (EX_Rt), + .in1 (EX_Rd), + .in2 (5'b11111), + .in3 (5'bxxxxx), + .out (EX_RtRd) + ); + + /*** Arithmetic Logic Unit ***/ + ALU ALU ( + .clock (clock), + .reset (reset), + .EX_Stall (EX_Stall), + .EX_Flush (EX_Exception_Flush), + .A (EX_ReadData1_Fwd), + .B (EX_ReadData2_Imm), + .Operation (EX_ALUOp), + .Shamt (EX_Shamt), + .Result (EX_ALUResult), + .BZero (EX_BZero), + .EXC_Ov (EX_EXC_Ov), + .ALU_Stall (EX_ALU_Stall) + ); + + /*** Execute -> Memory Pipeline Stage ***/ + EXMEM_Stage EXMEM ( + .clock (clock), + .reset (reset), + .EX_Flush (EX_Exception_Flush), + .EX_Stall (EX_Stall), + .M_Stall (M_Stall), + .EX_Movn (EX_Movn), + .EX_Movz (EX_Movz), + .EX_BZero (EX_BZero), + .EX_RegWrite (EX_RegWrite), + .EX_MemtoReg (EX_MemtoReg), + .EX_ReverseEndian (EX_ReverseEndian), + .EX_LLSC (EX_LLSC), + .EX_MemRead (EX_MemRead), + .EX_MemWrite (EX_MemWrite), + .EX_MemByte (EX_MemByte), + .EX_MemHalf (EX_MemHalf), + .EX_MemSignExtend (EX_MemSignExtend), + .EX_Left (EX_Left), + .EX_Right (EX_Right), + .EX_KernelMode (EX_KernelMode), + .EX_RestartPC (EX_RestartPC), + .EX_IsBDS (EX_IsBDS), + .EX_Trap (EX_Trap), + .EX_TrapCond (EX_TrapCond), + .EX_M_CanErr (EX_M_CanErr), + .EX_ALU_Result (EX_ALUResult), + .EX_ReadData2 (EX_ReadData2_Fwd), + .EX_RtRd (EX_RtRd), + .M_RegWrite (M_RegWrite), + .M_MemtoReg (M_MemtoReg), + .M_ReverseEndian (M_ReverseEndian), + .M_LLSC (M_LLSC), + .M_MemRead (M_MemRead), + .M_MemWrite (M_MemWrite), + .M_MemByte (M_MemByte), + .M_MemHalf (M_MemHalf), + .M_MemSignExtend (M_MemSignExtend), + .M_Left (M_Left), + .M_Right (M_Right), + .M_KernelMode (M_KernelMode), + .M_RestartPC (M_RestartPC), + .M_IsBDS (M_IsBDS), + .M_Trap (M_Trap), + .M_TrapCond (M_TrapCond), + .M_M_CanErr (M_M_CanErr), + .M_ALU_Result (M_ALUResult), + .M_ReadData2 (M_ReadData2_PR), + .M_RtRd (M_RtRd) + ); + + /*** Trap Detection Unit ***/ + TrapDetect TrapDetect ( + .Trap (M_Trap), + .TrapCond (M_TrapCond), + .ALUResult (M_ALUResult), + .EXC_Tr (M_EXC_Tr) + ); + + /*** MEM Write Data Mux ***/ + Mux2 #(.WIDTH(32)) MWriteData_Mux ( + .sel (M_WriteDataFwdSel), + .in0 (M_ReadData2_PR), + .in1 (WB_WriteData), + .out (M_WriteData_Pre) + ); + + /*** Data Memory Controller ***/ + MemControl DataMem_Controller ( + .clock (clock), + .reset (reset), + .DataIn (M_WriteData_Pre), + .Address (M_ALUResult), + .MReadData (DataMem_In), + .MemRead (M_MemRead), + .MemWrite (M_MemWrite), + .DataMem_Ready (DataMem_Ready), + .Byte (M_MemByte), + .Half (M_MemHalf), + .SignExtend (M_MemSignExtend), + .KernelMode (M_KernelMode), + .ReverseEndian (M_ReverseEndian), + .LLSC (M_LLSC), + .ERET (ID_Eret), + .Left (M_Left), + .Right (M_Right), + .M_Exception_Stall (M_Exception_Stall), + + .IF_Stall (IF_Stall), + + .DataOut (M_MemReadData), + .MWriteData (DataMem_Out), + .WriteEnable (DataMem_Write), + .ReadEnable (DataMem_Read), + .M_Stall (M_Stall_Controller), + .EXC_AdEL (M_EXC_AdEL), + .EXC_AdES (M_EXC_AdES) + ); + + /*** Memory -> Writeback Pipeline Stage ***/ + MEMWB_Stage MEMWB ( + .clock (clock), + .reset (reset), + .M_Flush (M_Exception_Flush), + .M_Stall (M_Stall), + .WB_Stall (WB_Stall), + .M_RegWrite (M_RegWrite), + .M_MemtoReg (M_MemtoReg), + .M_ReadData (M_MemReadData), + .M_ALU_Result (M_ALUResult), + .M_RtRd (M_RtRd), + .WB_RegWrite (WB_RegWrite), + .WB_MemtoReg (WB_MemtoReg), + .WB_ReadData (WB_ReadData), + .WB_ALU_Result (WB_ALUResult), + .WB_RtRd (WB_RtRd) + ); + + /*** WB MemtoReg Mux ***/ + Mux2 #(.WIDTH(32)) WBMemtoReg_Mux ( + .sel (WB_MemtoReg), + .in0 (WB_ALUResult), + .in1 (WB_ReadData), + .out (WB_WriteData) + ); + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/README b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/README new file mode 100644 index 0000000..7fd340f --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/README @@ -0,0 +1,28 @@ +MIPS32-R1 Standalone +-------------------- + +The files in this directory create a complete MIPS32 processor. The top-level +module is "Processor.v". The interface includes 5 general-purpose hardware +interrupts, a non-maskable hardware interrupt, the 8 pending ISA interrupts +(for diagnostics--this can be removed), and a memory interface for both +instructions and data. + +The memory interface is implemented as a four-way handshake: + + 1. Read/Write request goes high. + 2. Ack goes high when data is available. + 3. Read/Write request goes low. + 4. Ack signal goes low. + ____ + R/W: __| |____ + ____ + Ack: _____| |____ + +This interface is simple and robust but can limit the performance of the +system. In the SoC design this is currently the case, since the instruction +memory fetches only once per handshake. This greatly increases the maximum +theoretical IPC from 1 to between 3 and 4. + +If your application requires maximum performance out of this processor, +you should modify the memory handshake accordingly. + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/Register.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/Register.v new file mode 100755 index 0000000..ae073d6 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/Register.v @@ -0,0 +1,34 @@ +`timescale 1ns / 1ps +/* + * File : Register.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 7-Jun-2011 GEA Initial design. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * A variable-width register (d flip-flop) with configurable initial + * value. Default is 32-bit width and 0s for initial value. + */ +module Register #(parameter WIDTH = 32, INIT = 0)( + input clock, + input reset, + input enable, + input [(WIDTH-1):0] D, + output reg [(WIDTH-1):0] Q + ); + + initial + Q = INIT; + + always @(posedge clock) begin + Q <= (reset) ? INIT : ((enable) ? D : Q); + end + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/RegisterFile.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/RegisterFile.v new file mode 100755 index 0000000..ac0c0ab --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/RegisterFile.v @@ -0,0 +1,58 @@ +`timescale 1ns / 1ps +/* + * File : RegisterFile.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 7-Jun-2011 GEA Initial design. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * A Register File for a MIPS processor. Contains 32 general-purpose + * 32-bit wide registers and two read ports. Register 0 always reads + * as zero. + */ +module RegisterFile( + input clock, + input reset, + input [4:0] ReadReg1, ReadReg2, WriteReg, + input [31:0] WriteData, + input RegWrite, + output [31:0] ReadData1, ReadData2 + ); + + // Register file of 32 32-bit registers. Register 0 is hardwired to 0s + reg [31:0] registers [1:31]; + + // Initialize all to zero + integer i; + initial begin + for (i=1; i<32; i=i+1) begin + registers[i] <= 0; + end + end + + // Sequential (clocked) write. + // 'WriteReg' is the register index to write. 'RegWrite' is the command. + always @(posedge clock) begin + if (reset) begin + for (i=1; i<32; i=i+1) begin + registers[i] <= 0; + end + end + else begin + if (WriteReg != 0) + registers[WriteReg] <= (RegWrite) ? WriteData : registers[WriteReg]; + end + end + + // Combinatorial Read. Register 0 is all 0s. + assign ReadData1 = (ReadReg1 == 0) ? 32'h00000000 : registers[ReadReg1]; + assign ReadData2 = (ReadReg2 == 0) ? 32'h00000000 : registers[ReadReg2]; + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/TrapDetect.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/TrapDetect.v new file mode 100755 index 0000000..5b5884b --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone/TrapDetect.v @@ -0,0 +1,28 @@ +`timescale 1ns / 1ps +/* + * File : TrapDetect.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 15-May-2012 GEA Initial design. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * Detects a Trap Exception in the pipeline. + */ +module TrapDetect( + input Trap, + input TrapCond, + input [31:0] ALUResult, + output EXC_Tr + ); + + wire ALUZero = (ALUResult == 32'h00000000); + assign EXC_Tr = Trap & (TrapCond ^ ALUZero); + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/HOWTO b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/HOWTO new file mode 100644 index 0000000..4201308 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/HOWTO @@ -0,0 +1,88 @@ +MIPS32-R1 SoC HOWTO +------------------- + +This document is a step-by-step procedure for building the MIPS32 hardware +and software and running it on the XUPV5-LX110T FPGA development board. With +minimal changes, other hardware platforms may be used as well (see FAQ). + +Procedure +--------- + + 1. Build the software toolchain. Instructions for doing this are located + in the "Software/toolchain" directory. + + 2. Open the project file "MIPS32-Pipelined-Hw.xise" located in the + "Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw" directory. This is + a Xilinx ISE 14.1 project file. + + 3. Build the Block RAM core by using the Block Memory Generator in + the Core Generator. See details below. + + 4. Build the hardware project and generate the programming .bit file. + Send the programming file to the board through Impact (you may need + to create a new Impact project file for your system, but no options + are needed other than the configuration .bit file targeted for the + Virtex-5 device). A default program built into the BRAM will print + a hello message to the LCD screen. + + Alternatively, a pre-built .bit file is located in the + "Hardware/XUPV5-LX110T_SoC" directory. It is timed conservatively + at 33 MHz (66 MHz bus). + + 5. Compile any of the software demos located in "Software/demos" using + the Makefile included with the demo. One of the output files from + the compilation will have a .xum extension. This is a binary file that + contains the code and data for the program. Use the XUM Bootloader + software (Windows) to send the .xum file over a serial port to the + FPGA. When the program is sent, the CPU will reset and run it. + +Rebuilding the Block RAM +------------------------ + The following settings will allow you to build the Block RAM module + and add a default program to it assuming Xilinx Block Memory Generator + version 7.1): True Dual Port RAM, Common Clock, Byte Write Enable of 8 + bits, Write/Read width of 32 bits, Write depth of 151552 (for full + 592 KB), Always Enabled, same options for port B, Register Port A Output + of Memory Primitives AND Memory Core (for 2R version, this can be + customized), same settings for Port B, fill remaining locations with + 0x00000000, optionally load a .coe file with initial memory contents, + use RSTA and RSTB. The file 'Boot.coe' provides the simple hello message + program. + +FAQ +--- + + Q: What if I don't have the XUPV5-LX110T board? + A: If you have the same Virtex 5 FPGA but a different board, all you need + to do is update the pin locations in the User Constraints File (.ucf) + and either make sure your clock input is 100 MHz or adjust the PLL + in the clocking module of the design accordingly. Note that some + hardware such as the LCD screen or piezo speaker may not be present + on your board, in which case you should remove them from the design. + + Q: What if I don't have a Virtex 5 FPGA? + A: Any FPGA can implement this design if it has enough logic resources. + There are only two Xilinx-specific modules in the MIPS32 SoC design; + the clocking module and BRAM module. Replace these with whatever suits + your hardware. Note however that the MIPS32 memory interface uses + byte-width write enables to memory (4 bits per 32-bit word), so if you + use Block Memory or equivalents they must either support this or + you must fake it somehow. You must also update the UCF. + + Q: What if I don't have or use the Xilinx development tools? + A: If you only care about the MIPS32 processor and not the full SoC, start + with the "Hardware/MIPS32_Standalone" directory which contains only + Verilog files. The top-most module is "Processor.v". For the full SoC, + copy the "Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src" directory + to whatever development environment you use. This directory contains + all of the Verilog files with "Top.v" as the head. The "Clocks" and + "BRAM" directories will need to be customized for your environment, + as well as the pin constraints. + + Q: Is there a non-Windows version of the bootloader? + A: No, but the boot protocol is simple and can be implemented for any OS. + See "Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/UART/ + uart_bootloader_v2.v" for a description of the protocol. If you + implement another version of the bootloader, please contribute it back + to the project. + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw.bit b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw.bit new file mode 100755 index 0000000..933f0a5 Binary files /dev/null and b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw.bit differ diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/BRAM_592KB_2R.mif b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/BRAM_592KB_2R.mif new file mode 100755 index 0000000..4981303 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/BRAM_592KB_2R.mif @@ -0,0 +1,1033 @@ +00001000000000000000000000100010 +00000000000000000000000000000000 +00001000000000000000000000100010 +00000000000000000000000000000000 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xf64nOIB9W58NB4K2/jCeJeTT1HYBk8F+BGTIo2HijZKrLCBNB4q2uBhAL8/UgzjXU6Rj0I3SuyPy0ks1L8RcYH6NyIuUDHm5sPI0zM2JBL03HxXLDGEPy4nf4jlB/pD4B6hWQQhJjSLIMSEZrESIDSLlQDpseDh5C2rDH6XVrZVAr9LK/gdD75BJmKrUyXcl1b+51jB/agiPe38bhPcj+oZ8CMiA1AlXIQqViK2usS72OrSidjaQk87v909fu2jo1QJJUC79njp8OsH/AhIR6kaEnIPKZGJe0iJTNz5lTr53a74dY2OcoWKpuSH8Jdf9+BHNzpK4Ru6tR/CX04rNTRxIXxDE8erAfzIRjcgHdBsP1I1lIDx1VjhcHKiVgJ8meyIPD0GgwgJevCIhF+dKFI6JOTBIoOflyhG1FxOTuzIACwy+DmJYnyKDDBD6MvvZsbPSXSUOgzseNYe/G6kjhkPQwcWmW0JOq7qnN86vi1Ph1ksQfMEvS1B8wS9LSHzBL0tE7eIh8vJ8BMZgNef9jOnybtB/HpJcccch1NMTSSCFkJDFZ4P8AMkReqAEjB7mPZyijitBPhumagrLCZofOmAf5RyREJehQ8j867IxM5JaGTixUyMbxcUGUQ4eSyr0P8C4BYdTQ==###5920:XlxV32DM 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8K8++FmQgQf6og6iWmk7sWfV8yDqFuAxdYag9eKISgAomx782PQWVzXOSB0uO+htFRkEeCbNG42oR1RwIVBZ6+DrQAo+Q+qwAo9Ns/G4oiqzSdXtIT4H1Mfs4Lq4N5Py+9DsKJi7ckAm43fVfsJPrXGLmxqzAKp5cjOLa+BmRtMs8cve/WNrq0g4+HaAjPd2pagMU3elqMw1Xcz6lWs6XXXmbNyn5JfZhPWp6XCo2KemM4175Y8Hv+5xiWXEaUytgSk3+tTA5pfnuCwX87CzCcrFXOtsbzL31QtqPQ6+DV+oK/rZ0GVutUnEgrhH9l/tRaii+OBbB94Kr6QVBdFBLsYFddR/BhZkWbKsdfDjNbdY02M3qj8LLIgBFOMl28CyFoWE/jCaua9e0EfY+A4mrrGXVANylqJ/SeRivF00wgqXBTVCpYI6h+25wN962J6L+bS3bRjN25qLF3nLwY8T3WLvGhOrUi/drKRfIeruSwxRd19iKFh/A8jcV0f/G4DwHVtcYy+pDG9c6+Mb1xb3mo3vCp3LbkqxA/mnbjzntgsygvYi1Tz/HEwuyLJoT1QtEPSfQ+HHeLe4qrHxZRQ0hTWwMbKmVY2Bqz42rtVOhRvoBX3Aje9tFhfTUc+bczUK1oau8g/VWOWmB985sCYs7vawp5huDwqaLlKpFDT6H2uu5vgq9Kt5vP7eLPwa7xJr8uxGe3DYGCkJ2sCaB9mlaSNXyS5NW7RqxzG+RTv49hpunKP+optrg760LaoN+lJ2rQ3TKrtyH7sqdFlpEoHRf2UtVbJVY2Iv2Q5+eOoWe9c4kerNZt6rcrwZMescRvjmumaVQvA+rMsoSHzoTEn4dhNua5fUISHX+j9u+LMq0VdyW73ZP0aaz3hjzfh/an3/xA==###5340:XlxV32DM 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ca4eNqtW1lu5DgMvU7K/knZkpNgMEDnBHOGStI5hcGzjxctXB5lO90/hcQWF5EURT3R8/zf9O/TE73fu/V32H7HbvkJ/dN77N+n2+22/DVuL0K3PPtF68Pl2fZft43YBxXqfSgt9GLsr33szi4P6ShzWF/c7Yv57fHPfF7N7RFVxXa9xMAsiXNKVJzTTiL5iGGrcp9DW7k6EWnFvhpGGEGIKY+5vpatngQQWJ5mX5QZrJO4P98PZ2FCYWW3+DdC5y+P8wx56MhJVxWsP4qdZAQRD6Hk1VWVRYuuvhNcthHrq1UpHnwi9pYwGxs2qNbbzNxp76Sh2/v3sCkT0cSYPTYTLUNvhfXm3HVI6HfqRavw4Wm10PaScpNcZJZB72NWZx6/XG7xVpTfOWZ/L+Pyf/Pk2mgNBkn/tHNF3gWD14mnSc/xd0vKSpRXSScXqFgjydvIqC/eot202oy6W4zHEomwzXFUF1I2Vb+Pp9X01Qb+rPbw5a5kK0C82kOPlMD8ZH6ZfAF5qQIB7JV4WBaWtK59O09OVLGlR8ob68vMXDpu7HhCz494upjD2JJHfK2vL3YdehaLy4pYuCB/5OVdV7cINZmP5cP57ctnqFM15SWA8zOJBN1IIlSziEoiedrFhfPr3dEvZaNqsBS9KIfx8b0OWar7mtk5kg7PDR1IKVEf9sUXQpNNSx3WVgelwscFFap9pXCRxuokN430lsxXrzXIw9VG7fAlTe/53BgEFVUmf6nigHg+WVLUhJVhKZeFsxFvh+XQG75PMM7htio0xxeHIgoZuESy45guL04IsmDOOw0Mf7kHVS9HWTdyJ4+fPxGZlZ7jcESebCFNsY1L29CwsSpUK9PXM0zJd7Yax/JzdFYYGYUd55FVgmrFHSD3Hh5QSNT8RweUXh1Q1Gq1VWrRDK7vPIPe1PPrbhFb08j1Myrve5KHlJLhQRXNN4G2jun/efLMu0ma+BEFJqE+x7/aP/mzdRV+OGLUZlRqt6nhAmMVKhTMB7yCmHzpvdn81cNdiS3T+9bKFSgzcETGImitUVlrwKVFzUNZ1H2b4zw9O+MnFZVw/fWqAmNOrfH7cETAMpMVZiROYb2qZvUR0FaQwLu5pCp7Y0gx9vBUnJzS3u6NYGkpDrWeE8K9yCDjA/KdQNgLfMuO58RELcbuDn2h80AXniVlYuqeLHaCwB0AuXQynXVPJjlpXnP4dpQjbTMN4bCZrw4bbttZwPNW6MSxhdcRwlmqsGKjJcjgi5n4QYO8Q605SxCHI66IoUYhp465vpgADxQKLhpqTZ3HLOzy4cKpxkIvF1jIVRfCVXidzRWGhK51YqezQn3EqmcDVtYTqhxwQgzBsi0DGPWVOAcrNU6JaeAk40kxOJfGTubSIJ5JoLHIHcWg8ZBwmeProXBqVJTkLVACKxRWBrE3GF3EeTuYvE1O4v44ISj4gmIjxS+7M4oKBSuZNC6P7x4+f4C/2+JprWk54skS+WtTTYbtmrXNa2S7dfrUBRqpxIvTB08NsQ4OV61dtHUcPtHyzNpruxk8d+Bnlm3zCtva/G5wFoiGeIhAlYIZR3v00H7uD6oQQqAK4bsflU1TFTWPrw7frfBNSibUldetLZXU1DLwnQs3lqbyK34KxglC8m3mdYu3ORkX3keI45C+d5hupf60YBWx2eQQ1TBGxdueLOLdKL2IH53M4teWkA/nV2+eUjt+tTK5qGi9e1GJrXV/44K3JI5MNeUpvFxnGjdVAjJG1XDnYiUne/QEzESHV1BULdkwFCFL/UiT6VCTeF0TCKspTYgBizn60mXW4+6SR+TzCfh8ut26Bv5CAv4FB1pgsHjS7bFN6xg7YrcHaeyooeEfajIdahIONAFuD8/HmtSTrNgg8r4yvbksJjCZfKFkcnlj/BkXHtA6hnNvJ1Hq5oab8G4aOtROwItEcM+gxhf8Je+Sj78hiqAs0sJewhVhNe3SBYnlKrdYdH79csQi37R6DzCoaSlURwuvJBqViQQxwl+oTOKnJ2iy2lnoReaAjBGMeR/EkIBm37r671B+axzlGytDiaQj201OoXtYKhvUhLVfKLSY+EXFUMqo3w5fA2soW/ROzRJS/WsvryULO7SZ99addDTrcfc/rljkCAU3mIvz8XTeizZefSyGPJREIW+fjigCsqgljFxpdBhMZ8RRg7FrMY05UAMGIQe/JomDjB8/FLXfv5xRNDQUHU8rGr//TBQBFEmIgKfdAtCrdLAvuGGHrxflwBaYh+j+J8DFA6mgRtHRaEzP09H97TopXaflu8cGhkRQ1e+NGupuS2owte660AX8RZ50kWk4YkpQU+iwiTkGOSz6Rj8gzR1gl8TKyG2SxnaIXSENUurbeVK6QEtHRn5coCVN/PETYjolOh6syCvExmAfPyGmRI16hxB1AUznEVAUc8jbY5hdMMq1cviVzqs6qlIRNNYqpNcV5hviGJyuFNgcjmHKISN77fQpbnpRQmkEN51N+Y8Grb8yJjdIGPHRjnGJmrTinz+iLmgCFD7p4g3UX/yiksT1iHuMn8PQkLYvGlV2sGqQmq46m8Q+rxCfSkR0mImajj6dxi5RnwuTQ2r6IbnKg+P9JHm9QEFNfjkoa8fqaA+zCkCViSkltBfMeivFdM+Ghs3A+9KpaTrlANzAJInqvd0MYq/anCqisk8Lx2wTu0fjA5NSMkI9z+u76N65imYGDi9N5sRugZzXpT//ccjJWtBp2wL3swIDR61nUhhyFyF/ofa+3TJfLRGk9ui6y7qh7KocWiqPf0XlANYgL1awyraBEXd7YjelBsYBguka0lHtWXxF7yzim8dCf73SwNBEfVbCCbjG+3CFlG6t71/4bjxP0RFhvyYZ4dckT3rHFx2B+epgnn7/sRxxZEedNDJGHkCgvCYooED5zss2U6by7NtjhoFACdUMcC/SH2s0ENY6zvbIOUFs795yTSdR6bQOBocFeTzIMhmAkWp/Af+eLt1EzcEaRXqyq9lMff8jRqysPh1W9usUy0yNWd01Ynby4u7aTSDqVgu8Wy10on9NfndmutVCB7rYnJ6CfWyfEm3Q+7zOHGBA5JQGZUW4c5CZRfbLyi8JxY1f/QwCnufwN5sa1s0n2TumLZ8nqmtS07azXsiMkAf/wqosB3O+bAzFHwUWNPTLSAVNtUlv+wJZn3UYH4HhtTlMZT5VSWpFBvtmHifIgTCL+kRncBBnfAMqdY6qoVOL8/jyz/8IHJOP###3636:XlxV32DM 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125ceNrNW1uP3bYR/jP7kMQvvF8kBLDRpEgAt0azQQL4wYVEkYBf4hZGixa769/eGZKiSFE6e+zdBE2Qc7gzo9HMkJrvI3Vyf/9GffvVp1f8BXyIF1+9kt+8Ul9//fU9ncb7ne7TK/kiK3lRim/WazrpiyQVO+mnJJa1GFx/cyJf7SvnLw5v+WK75SaVcEvxMkp9JQTBfaj+/rQTxJve6yQg64DemzR4JcpI3ds0ggi2obpnaHD/3U8//vL9QNnw5vbnV3/97tVP3w2vf/nTX97cMjncvv7+V/h48+sjppxvprE69z92Fnv57e3Pr6n5+49J/qaTP7x8+Q8+Ty6ML1/+Rwg2D38e5EDvbo0NA5vDPHC/mIFyThT1AxdKs7vfxKT1QEf8NoMab+BbDvDBxwe4cD680Cg33lK2zINiTg6kVmk1xut6jfMnGkvcuMSAQfpIwBCgYGSADzreGEbR2zz+BsGEQZLJSqUgCfjTJw0MPY1+xhseNMUr3fjvn7kPFm8G/3LGyeP31IOmbPwbD8pBiA84mHAAXhXqOISjVTRCc5FvD0OOQxeHbBAL8XEosegQkUhha+7H/4IruKU3cbTE0WsIlA387sYyjxeH8TdjIYLxxsIa4m6S48MPYEPH15D0Mvi7G7BaBj3eMLzvBGnjt4Cb5r8l1gC+FfiDtXRj0S8Zb6ZsZ/Ab0lnyt8/fLt3/hsaiQ5ph0PA33D6oeXwLTs3A7sw0DQbSj2Ie458HkaOi5MDNDEUT48OcVwBURgU3MD25u3+CDzrCp1xG9MfGt4ZhOTSVcBWF/9Tw8NYYvLMOfMD/Ht7C8hUwN3AfNjy8gCwZ+P0B/KvxX+DFDoyM4weQk16Oq4RjiBRMYDwfXPoeAtdHcrjMHconMR2GMIkj+w9ByWOxOBbzYzE7FtNjMTkUy3AkpmziJ3J2IqcncnIst2f3dSfy+UQ+ncjtidycyPWJXJ3I5YlcnOTrDxcOM/pErk7k8kQuTuT8RM5O5PREfjSPs3Qe6+8HBp0J2p0Kg4FVjE+Z9AOdCPZCCsKZjB+MwNjH90ZgzthYzQBK9G8kq0UyipZaxFCkTCXyAUWa1lY0ihpfHMpvZpbuPPNa5dF6FpuIkehglrWViyJVi+Kd5yaLJYrq+MKcCoRpoCm5S1UBjUJoUAp64cxircKghJdrsTgf32s+VXExTF8LWYsUiiSpRSKKaC2iUcRqEY8iXoskNkPv8JmETp1ntQmaEbYFTUrQ81SCtl3QoQua0z7opQuakz5o3wft6qA/QtARXu6+jeGjYnwHE59UtlKBG9SYqFlco2Go0aiZ9NRoKGpU1MTuvWkIagCnP0LTDLVGSNQI1FjW3IdPqAEO9lE4snlb1rCFTGFPlSqFrXNCrtFg2JqCRhG9NBoMW8VUJzM3GgwbcBeDW3ytiWFLvA+T0taaGLaA8jzM1EAIQK/kADRpffYBni0Cuba5Awjnqw7QLga6hP1ioMu2GHYrgC7bCoBvXzvy8VHw9SPqbRTVjyiwLRSZ7MCmjiBzZ2i7Db+q27DSbaDF2CW3GLHrAef9ZG0ia+cYZ2oJupNNu/Drk8dd6RY88VAsLDwHu6eMmO4pI+qssIzo9Bz59PBTE7DGqg1BlBD4GoIKooSwdCEsfQjzeQhum9uqD0E1eF+NuYQij6oR9qHQvufQvlFSXnrOrhq2r8ZSQlAH1eCkC6Hv1dT2IZgthONq2K4aYZsYc1ANztZQurZL+vu7ru3SsF8bU1eNgmbc2aNq8NMQ5FVwJY7XhoktcGpD0eNb6D6wDbsDPewRDHRQ+JiHaP6Q4gzpn9KZuMDHd0oP4pTWp3Hrd+4PLvcLl+ygH5l1YNdBUc0pRkEiu6NtjBti6vED7LDK7E772WWwbVtLOx/NrulIge7x1XSP3W5K5/2UbljPcWPbT6nt7usu4fqFVf0x3x8gJk4RFm/8NgojFIJBKsxqABMAepRhDhHxGN6W3yUpYmG6vgJzsFGNDS02BdYZcPTGhhSbDeApk7UNIGW22aAeJt3U8U5wr7gQ4mb6Y163RW0RUu2SKlESDZnAlKJMqRIZjeMo5r8WxUYqERctz/q1ElPLD9jS2NBiU5gCZMkaG1JsNs5AaeMnV2Kq2UPunSkhu0vIpoR4SYi3CbGUEC834SWhlNo7gPJkIxsbWmwo2ugUrGpsSLEhaJOmn+jaJieUUgMbmRLiJSG+S8ikhFhJiLUJperzLRBWEuI5IZmTNo0NLTaYkEQ/jHjW2JBigwnBB9rMc22TE+I5ocgwZ5byeYfccvXAo0JkBRCptVZJkdhqJKLrqkgKlRVArNcHh2emqJApqsE2THGOTNG0fHEh53zRk44verqHkJUnsp5oHlJH01NH1VPHqVDHIoqd9iKLTJSxYZGJWJ6yyPfGTE9mkwdb0kgswwViuUwFXoi4QCxtz+qmDsSJ7kAcGWkNOpaQCxxzma/jmL6PJvTR9Kwmk9OeYMUDwzO6CXuTq+gm77ke7bmW7LkW29eIXmCesMyvYp79VoCqPpqpj0afUXJxgYR68lkkNDNO2vPSyyRUXCCh0BI+i4T2c8PkZ5BQdZmEBmh8JjDkn3KI5ucktHr6p+cjoTBj8gKx9PwZiWVR2f2MyQsc04tn5JgHB0Y7uikL/VIb3ZQV3awNVropN7o5b3xDFgiXLd2cp8aGFpuNbpJAGxtSbDa6SbyvbTKEy5puwt+kjtcgnzRTYpqq1jRMUxQeIzYeoyqmKQqPERuPUZlpQoJbYKIUQbRM07HGhhabjWkSPzc2pNhsTJN4W9vkIoiGaaZemeKlu4QS06RrlXDUJMRSsIWYgT4lhK4qpgk2trGhxWZjmmRZGhtSbDamSZbGT0wo2lRMMwFkSojsEspMMxSD0CaUq+9K1UJJiLRMs2KIoSREWqa5iMaGFJuKaS60tskJkZZp6pppJg+JN5qaaaZaJYVtmaYoiqllmrJimvGlL7gYqN6YpstMc+WY9MkcM/Qcc/ksjmm/kGO2rPGxQ8v0buXsFUkNOHplieoCS/TquuPH61ii6XmZ2sOGusASoTrPyBKXPpr5jAHpCyzR2y9mieJLWKIJ+gJL9NMXs0T7NJZoLrFEd5El1rzvilPLfuao39fIXCKMy0XCuKOAjx1gskvv23bcER9sc8wdOR5gamSMZoiWV9FGe5E2ntPFHVmwOxpha421SCN0ohHlpAtGBaRsRSNMASmzgZQtNMJuIGUKjTAtjZhYY0OLTXVgRXhjQ4pNRSNCqG0yjTC7AytdEtK7hPKBlS4J6TahRCOm7RBJl4R0SyOmubGhxaaiEcE1NqTYVDQi2NomJ6R3B1ZlVoPaJZRphCoJqTahXP2taqokpGoaAWSQNTa02FQ0IqjGhhSbikYEUdvkhFRLI+b2wEoVUuDaAytdFEtLI0xhC57jz8MWfIGpNrKwNAdSTM8NWTjF/A960Rn7TX+YZJNJyA/mpdeIencApPsDoPgUf7A0ep25j7/9oHvQxjS27fiiK8Cum6PncRkdgywlqpzFaLE0KHsNWHK3sD62eR+bqoCyjs0l8rkHN7xajvuGuEY5NzjXAoM6i5L372nEaZQAVU2U8TU938PLtVHyaw8bcL3ib20OAcPcgR5fxVM8ZQXkgiUg4AMAC0YBR3yILp7vLRgGVwbzOnDrYPmsN2WunwFbYlP4psyX2erWOx5onM6WaWcr7pf5/izi2tmy3Wy544MGV/blWPR80IDCfNAAKYfKIB40xNTyQQMsq1WPV1XHC3DlUl+Z3zC5AUqEF3rNKzVOxPgOmkVSkVblCpj79Vctq2qGphtoVMmpVQE5gHYXVZzWoVRnDOXHK7T8HKeUYkpZ5Bd/8fHL0JNKYZMDWzmoKEFuC1GziJ1rm1xPxTVrXbPkgFcOKnAGI1PysTvXJrnOUcW227hOsc2+clDB5Mx8DV1JmxAq1NCVIooKTmroWn+6hApa74DT8siYRmd4Mjy+aqkwLRy8amF6OUe2vA2+iGz6FNlON5hnsOaOYM3FdvEYrKkTWHNhOoK1Kx/zA4DzZ9AxPwXgEs97PoDTZ1G6pwCcI88CcMeoRufLqCYN4pZCBENo4xo/ZkQ6hDvuhuji+Y7Vnw/VoOzLU5AqHaA+H1ItJ0jl1pfWWMgVqRzbkMryymBFqmVDKreCAF5VIRVMj6yvrHaVXrpK04KUnFtVBVLatqoKpLRpVRVI0dphA1KOlMjLMWuuQgIpywqSuNLuYxUSSM2hctCAVHAFvt3OdQIpS4vruXWdQKr8MAYd1CDlyg9F3PZDkew6gZQlxbVtXefYbOWgBinOapBy2+t9zhuQihElhWhAypWDXS4bkIorYwWp0IOUIIcg5Z+2/dKPb7/IeC1eHYKUfwpIOfG8IHW6CwtPAan0buT3BylPngRS5nl3YexkF0bDI7uwBREJYYl7HOGfHDdgFP8UuB8DF/+feOXpk/Bqeha8OgGpsgcB6wJS0yFIhRWk4v8buIJU6XluakGqgofQgpQilWYHUqFVVSAlfauqd1JLq6pBqnbYgpQpkZut3YcjkPJka/ehgJTTlYMGpJwqGrVz3YFUaF0nkHKyctCAlCubNCd2rjuQ8q3rHBuvHDQgpRqQctuGSTcg5crpYN7VFZAyRWFbkJo2kGL8AKToIUiF3wuknoJMnj0Jmdwfg0yePwmZ/B+ETOIpyLQ86/bpf3cuvIw=###4076:XlxV32DM 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fd4eNrNm0uu2zoShjdzF8CnSFnIvNfQgwASH0AmfQc9DO7em0VSVBUpKk7O6SABYsv+qXIVRfH/SPu8tr9lcPHFXts/Bw9CpqOQ/rPvf8mow0vxaLZ/y2jEy37nQfFXasTSgxJwBC+VhCN4qdQrh/jnPzIuyyuWf2H7S6UwLyvV9s3aHT7rb7vm52/W8fos6vNan0u7lFw7OM4Ddx743FZxb8+D9TzYz4Oj1CZdWNIRx7UJxrZ/pdrYBm/E1yL90pK1+RNC7RnnIT9Jzxb5bL315ZZgRh0t2Lp9M7pUaLQ80y/d/t8aXHz/knsPct6+5DehTWqg2CpRg9Q325dcDyRYAvCqw1npk7av9jCgBB7xmXZPSnoAZVFIgc7cvq58LZKkkktnrSXeIqh0bF9N5EXiVEqfZXw5S5D8V8hi9SVz1jJnpd7WC3spvX5gKliVgs9eyLk6F1GAUrrhRQmnko5o6LWE5i20pKFFCeBRgBzaBFsU1xTXhbYlNGuhBQ1dcztQgBJaw4cecs9Ceim3U5VZOKoQ1u3MqAgll1S22M5eKIKvwmG3c2QkId/nNt0J4bW++PIdRm98majKcLb5cd3KKBeWnYP4YOcgTtJiodawXeM5XeoyvoNFTVJ/wVtraRLrzW7O53rTt0nB1OdyY6cxjEJF+LRUS26SRio8w21t+ts6lTe9rYXrbuulv63TNPbubS181yOCue3mDocs7ZjlMc8ydlnaMUv/9uTTXzfB7SzLdcgyqvkUKbos9yHLuLydpXyYIsuIfXamBbxHgwsZOIKXysIRvFTrK4f4Q51p/5AzuU9xpnNwpLE3MSnX5nB7mZS7NSnbTGpHJtXmPO+oSQlyJjGpFSmdSVkqYZMyVMImtVAJmxQOSE1qb5nv13Rvb01qvaZ720zKrygAMSlvm2K70INJWRq6mJQ3KAAxKb80ZelCDyZlaOiam0YBiEkFYlJZLZYTiUnljLKgGDWpvQmcmpRDJuVuTEremhT/JZOaOVNzHLb9tEn5e5M6PmRS4TeZlPuISQX2KSY1Sc1/xJmC+BRnalOk2CYm5X5gUjvYEHiROuAIXioHR/BS+VcO8YeaVPiISQX1uSYVJiYVrkWNayZVFg6DSblmUuEyqXDqcBY1KYvPJCblkdKZlKMSNqmDStikdiphk8IBiUkF0TIX13Tvbk3KX9O9ayYVOApATCq0RVpgXejBpBwNXU0qogDUpNoizYcu9GBSBw1dTcqjANiklKAm1RZMShKTCm3BpBQxqSCaoIlJ5ZFRTSrd2fyVsnlxeZmUqiZ12pP4f62hWpM4d6pqR3gZhZ0pfsSZwm9aPuWif92ZftPyKYoPmZT7XJPiE5PKrdy9SRkwqQA2BF6kIhzBSw0bfRL2/dLZP/anmS99nh/x4kfiyVGOIFtPHZqaiexWPNREzjkJqm0mEk4T4YVGynRWZpU8M9DpOZ1KTMIIpFCTMJxK2CQilbBJBCpdJlGGUsnv2p4qtVQrWM5JNV7bU5DxaQUHCkCtoK1Xgu1CVyvQLTSnoYsVBIMCECsIbb0Sli50tQLVrCDS0DU3jQIQK1iIFYS2XlGGWsG1XrHUCq5lidzhHhfstbyEvqZ8XSd7bQKZ7GUZuSZbCIw8Vp/J9C233hcC27pxykO+o+s9YfJyHHxB4yZ7toqlSnhlEvLcSo3FNGNpb60b8pi8Lk/PiixxNHgNSTaK/JbHb0FJdrHjcoqssHjzLWxl4yJrZ9XK8I3L8tmHGtdfuE/ikd9a8Ftue9hdbG/Fyym/rSJncqQZHQ5M73llyuFsUeeco4UgTvfOSBCcbYMphn4kCEZmrDQm87Roeoc7c0qu3XLSxNdITi2HPIju0zuG9LgZ0uNrl14eT6a3tpaev9JTxNByem2aXrY+09T8zLS9pbc+6bpcI+Yoh6TBL0nSecj5qU9KC8x3JGOUaU2RjhwcBThKtglnz33yWr/t/N113IfsMs2d4zZ5XFtKS7rpWWiXS/eXC6y1Xa7GH5o74qrkckk+Xq4wXi43Xi6/PexJtvCMmPYqTzeEnod13dd0x4IryKiQUt0cSqxurtneGqR3kZtrth5EaYvBpFiicFAWUOIRicJA0UlJ4zdgJTlGUhQoXJPPkUANhyyWZ3FZO9++5EuZLhYUbSUpek3n7QyK1m3fFBRCG7rtgFbpog195VGkizbK3dA+Cq07ZWxKMXyw7drVe+lfiRqU/jWi9GIkSsMM3QClKtC/S74msW1KFgX6V/vSvx4ruX+z/af+tVjJ/atMHjWKdCAkIGSuqm35wtxKq1pLVQI1yFUBROTcA1Ea4ejGRlXhoJhSFSMKA2UpVTmsQFXJ8ktVCisy85+DqnZaFXxMTjp51xkMXIxWVTLcOWpQqspAlHJfidLgSl9bKkWBj9P5Kka3EwWq0ixXpXEipSpVqyLRclXpoZCXAvISL/0SaEd4aeQV5+TVkRYbV+C82h3eg2xNwG/b4vyZwGwjsI687naeMYn9AnbxAbvKRgDFLjlilxiwq8DZbI+b4NfAXKFnrpPMfsRc/k3mSp77xFzJHka+GZmrYyw2bjw8jAHBfA816xNzSXYHNXPmskNOlbWecgL2ojkdT6CVLPmGA98CLTk6Nx+dW4/OrUbQEj1oqcddc+kY8BSAloOHNPGmI3jYgbscPKQQf+Kuebog/gmlpLgbJOtskFQMYgNl/ZCfwg/5SV2eoTp+ckhp/OQRP13u6jt+ckTB/KSIgvhp10RB/GQMVgg/kc+5+Gm1gVR1ARLmGUU2avSFEbvq0clRCaHTclDpQifddvOrdG3UyJ30OqGqdlJE/KEQVRnUgFDVVVo8Oqqi5yCqOhaiIKpqm1NZIVS1YgVRVfuNWOl1RFXxGiprV1WlqgU1mFBVVm6pKiuIqhyNhqjKMKzcUxUoiKokvUMuqkp3VDvFdFVVqtKowT1VFeWOqoqCqUoQBVHVErFyS1VZIVSVJscbqjInVXU/AMNOkbmoB6zBXOu+Fdnw8n7c8BqW5JnMJtjVbWH9PIE1aRn3wPYfw5gYYUyOe2D6A3tgb8JYB2E/2guLb3DZSW+220S747L4xGVS3tjbxWWYrDqnY+NOAYuD07Gb3Sg2bpY5yhuK8UdwU4/gRre9foHhmrSM+2Z7R0bOPOKcfg/n1IhzesS55bP2zfKwfcI5BcCmAd3gIc346cGkB7vCEeyqpRB/Js659RHnlkecoxj3o50xyd4hO8nHC+JmZJf6jZCds0g5yc6tiOwa77h1RnZunZGdWzHZLYwtRME7Yxwr92Tn1gnZ5aow2ZF6MdlpgRRKdppTCZNdpBImu0AlRHZ2x1lgsrugxF20UC5AJbsDNZiQnTMzsnMGk13qdUcURHbaY+We7JyZkF3u9YvsFDtTg+mVVlXJbkcN7smuKHdkV5RGdgvjkiiI7CxRbskuK7dkl6vCZHdBZ+yqqmS3ogYzsotTsouY7FJVhiiI7IzDyoTsYk924Y7sbCM7/kB2YSC7ymwTsnsH5+Jn4dw+xzk34tzyW3EO/RSHEt4Hce6ksp/GufMLUNuh4Q3OueMR58x7OOdGnDuecO4dhus335x/ZDj7mQy3zzM9RoZb+kzjI8Otv5/hbpBB9gwXnhluB1SzB/DaDkfw3ecOL62HI3iZQvyZDOf5I8PtdxfkHYarKPbzDCfceEHClOECZbjriyMbGsN5fjHccX2zxGcM5/mM4Tynu3NREAUznMbKPcN5PmO4QBkO0VPoGG5BSsdwmkr4i01FJcRwl38WCTMcyY8wXFMc4oKAGC6iBjOGi1OGi3R3LlIFf+epsDJhuDhjuEB359yFir6rqjJcQA0mu3POz3bnnKe7c9ETBX/nKbFyvzvn/IzhAmW49iUk2ButqjKcRw0mDOeOGcO5gzIcE0TBu3NEuWc4d3QMt8Lvi5NR25dgF8Ot5O9fdPcDY0JygW8/9yUo3dyjP1b244/S2B3UvY1ry91Pm3UloxlqvfNHObo+T9ho/COdNDvJR/o5Hr9kpFzzE9830l0w+suvES8YMYZD+rza/dVfRsv/Adoq5Bg=###4100:XlxV32DM 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feceNrNm82S5KYShV/GD8CvgFLM3s9wFxMhJIiYzfXiLjv87iZBgkyEVNXVtm87wlWUjkBHKYn8OtFs+sEe8D/7+E1GHR6Kh23+r4zT9OCMuRm2xsdkmJp/U4rHh5Vs/mV06vFI2mQfSvBlhk08bYJvgaUpSxKkP2RYIzT+9HJbYBMnB45q/l1Gw45jym2qxxS5dyi9udzMyXacmu1lZFsetg+vh0ch5sP2yCuXDqRAj2bm/ySv4mE/uFy2B5c2po8lpA/HoAU/HU8fHn6mIf4s9mL5L1Rfav5l7ZIPal3+/mVXvn+L/dvt38thrjb80ViPxpb3VXyzR8MdjeVo+HodRH8dBGPX18F218H110Ew0a6DH10Hd3kdtrvr8L90NDgh8fEjhxNOYv6RLcA+aQfFnEc7pGDNP/IJguOkT2xVh556pSPNP603SRFiWojCQZlA4doRhYGisx0b8NHskpT0kRStF6TAFZl/Ou6K5Ki0pl7OFMlSyc8/TeRFMlRKxzJb7lVuzurCgQu3lXBN1bkpMaqRW0q4dpv5acxBOiLnSrgMGqCEy/ASLkcUCNdkS7hoHwiX3u204OvOjit2XLWjqB1R7CxogGzHBFvsWKJwUEyxo4jCQIHr6qQitwp0yTbSjjWgm+x8wtE08xztkO7T1DV9gOIcUcChFkWRRIHDaQiljsEQBRymj3xWE1aUTorS5azIaBLuBgmX1KtiIJ2km49zllkosUsXUMzHtSmC3wVv5+MeT0Ke9kyaGPj0cA8ePuCZjg8T1ZInB5s/S3oID23l8Xj7PjvwwObuSedbHDzpJk/q6XeYcG8Hu+Yg1U02b7L73q70jvuUqcv0Z/M9cXSJMnVJNy/exPKmfYKtE7DZv/dRvMZdVujisb0Y8yZsL/q8Kdv7Iz328A0TLT8lvCAuJ1qxdhPtds7Tqk2062CiTdNpl6dZ6K+EYLdzLthmZ9v+2nbsbMdbvNhewwt3ss3tE9sufgUvAr/Fi/A5vNBzT0U7cQxIw9yThhfAEgqoQkJLQwt+ugla8DMN8T1JIz9Sb5NGkLekEW9JoyMMfHUkO1+ddR7zR2ip1lT+CBLxR0Q77PyRTrvyh6/zdpBX/BHkFX8ESfnDYTuUP7CPjj8ClTB/bFTC/LFSCfOHwS4wfwRWnfOWSA3ij3Ak/BS4mvBN5Q9v0QAX/JGVIX9kBfNHPfMtdnZ2/tgqfzBqp/CHX9EAV/wRL/kjYv5Iv9toW2fHFjtrtcOpHV5wiKEBEGwQcNgwbBBw2DBseLXu4JCS/6EWPtgoUcQqBEIUOdpFiIQogkRE4UdE4YdEoc5E0WNE4P2zy7dtfkoU05kolkoUHWS8BBfsBBchfh4u4hkutjNcrEO4yPfK23AR9B1ccHYLFyeiiKcJlfmLIkD+e+1tuAjmDi44fw0upjNcLKcz2HljcAbLlzjD3XEGF++WMeomfsUZ/glnAE44C0xhoOWgBT/T+aYW/ExDfFPOcF/iDH/HGVy+xBny9CePEOF8dbYrzmjlA984ww85w1fOcI0zFl2ToL/kDH/JGb7jDIOPhjljkkihnDEJKiHOmDiVEGdMjEqYMzx2QTijYYJrmdQPOWNpmdRXzlgcGuCKM9wlZzjKGaFm32A6Oz1nlJNsdgpnLBsa4IIzgrnijGAoZ4Sm6M5OzxmpRewUzvAMDXDBGUFfcUbQhDM0I5wRaoFCc8IZoRYotKCc4aogKWf4yhk6xSlxhnqkL984Y9054yAM/f+pWXQcMiIMShZPKxn8GjZ6olh7ohCMV6LAKILhwn4JLm4rF1z9Y5WLHID34eK2csH131C5eLpG4qavwEWUt3Ax3cJFBxXP6hnygjM8uFnHnGGAMwAn0rSTWh5asJDi4cPB8knq/RwxrtDi70OKiTmYQ9UYCoRVFQomJSkUXCxvVE5ofIbRAcHAfuw8lfqww0DeuMPAxOyeLvLWXI6GGREn+11pGFCT/a5UDMBpNh2OJnuLlC7ZGyrhZK+phJO9ohJK9rHSQ2w1+HL+JaUvoiatqSYtcLyndKfRABcpPcqrlB5ll9Jr6SDEzk5J6Quvdgy1U1K6W9AAVyn9snQQutJBqKWDsHV2SkpfWLVjqZ2S0heGBrhK6Zelg0BLB7vPmtJr6UBrmtJr6UBPJKXHViEwASY8Hh7puZItc2+0NqAEydxyOWVupc81AZzft/DJ/L7PDibggUMuFD4tLphz6nc19WNAaBQg5E4D4pT6KSDoEyDspQcCCKICAiaLc0FiYTszqHOB4gCF6bzUQQoU4RYnfjmRj+UFy9O1GGGF3qdWaWXLcx4BRo8Cdiapr8TfjJkjLvWlhikIghz4RtqRQ+lzHYOAyfpZMOEmT27TGC3iUt9d0J4TsiBW+NnKqJJhzrDhTimH27kzuJ0MVnKIix8ZlL3BnRIIS5wNCn5mCXUyCBBCDObK8nX5wrJEOGZN9G95mk3MJqG1QitAK7EFDHHNFq1ssfB/t3yRgh/74DfWiMs6Cr47gn+qQ/BzxNdzxOMzChGcH2kKAgcVh5/pQYZkVPweyl6sgI1HsWKNR/KErZhPOJ+IUvmES7YSBZcpPFFqmSLdXeQ4sFye5rHcp42WzbukLJC6uIhYIUwjoqVSYxoRNio1phF1iWiXGtOYuhySXaACRnneivOaz/doLjlfS4F2KCE0opyaIUrlnBTChSiYcxxRKuekEGIjJYSFC1gtapQQwnGELOabN9GZLygmNdqhvC4RXBlUEKVSUTJviYKpaCJKpaJkfsVKfl0ilAIW09j80t71MPXlC9NqNbv5HKs9SX38yK2dpEoICknJBQ2ASYp5uFHl3hNO4dinMlUyJknv9u5Ho62soHc/hF6xgt792PF15zBzVFDyfKkKVemHEI2qwmjdRdE3OQhIBTm/Uig55z/MWG8w1aCcMp2ZyrzFVHx+peiiX2KqzGdXiz2ErbpFn/uXTA7yeoZZfoBZKReyM200FtoG+SSzEKUNNr9SkfFXFz4zEc7glvE7BgpvM9Cg4DKdGcg8ZSDLxB0DxdcYSM6v1FOmlxhI9wyk7hlIMKCc9NhbAQyU5trUEtACGkoPQx7iOy7hpODLGwby7JaBujWYZ69/8FdwCKCJ4JCoFJJiiHHIoildHTgEG2u5hh+YAlsJDglHlBEOFWWEQ0VBOGQMVjAOCUvMNxzCiKJI8UcyrHSgFKmEQKmhX5EQKDXmKRIGJYVdIFAqD2U5J8QaqoGSUGgHAkpCE2UESkUZgVJRECgZjhUESlwQ8wiUypRX+vDOfAGlel1gBwxKXAiijECpKCNQKgoCJcOw0kApAXkg5hsoWdb6sM68LeY92gG9FJsG3YhSEQnhT1FGxaai4JdiI1YqGMGMmKafAeXEIeWoM+W8twaEqecCbU48s5x5Zr17AQVTzzOe0fOXF5FoJelzPLPNr7w0+37ZKF12dcMznt/yzHvLSphvKCPoG4jx4hZibv4NTcc3F++hYL6hYGBvyMXL18hlmr+8EoRrPMRgxoQ7clHAJhooRUNrSq30d27q6KBlH3mIb0ku5Xm9JBf1Ernsr4o8IZf3Cjnt33RADEkhJzikHIWc4Bq5tFrDvgh/kAtbJ6IMCznBXRVygusKORwriFzYqol5TC4KK4hcBFEouQRJpUYuspLGLjVykTWP7xIil/ovVLILXOIJjblszZ8lzoVcWEA7YHJhqyTKsMSTlWGJJyuIXPSGFUIukQQXk0tjJ92ZL+TCFdqBkksgyphc9CW5aEouVmIFk4vYiHlMLs2b6swXcuEO7UDIRaxEGZOLuiQXRcnFkNEouYQBuWg2JBf9T9ZnwvP6jP1kfWbwjsvLlRhxV4kZLWl9Flf8J8svJ0YJI0Yx+QW+S0bR/1LNZe3BwN/hyvRazcV+suYyXgLLK9iXjGLerq6ou+rK02WlvIB4t6zkAD08QMgCrRVaHlobtGCBaQ3fFUy2OzCxr4HJ+smSyinisaORrZYV1tDRyIaUSiPbQSM6xpYWt45GIlHGNLJd0sjW0YjGCqGRQMwjGkEcEDoasUjpaMRQCS84TVTCC06aSphGiD9CI0cc/gKxDqGz###4392:XlxV32DM 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e2ceNrVm8uSnjoOgF/mPIDvF6js5xnOoquwjauymSyyTOXdxzeEZX7oTkG6erIABQvJlkH+fqOeyMR+vRnN5m9M2jBpyeffP510U21wJjcspDb8dkwIN9GJyilMNPz6L48qTjpKO//Do1wntsT5HyFonIwj83ctWTKUmpSZBA3rnC/xdGn+oYNuZ5PP3/W6nW29Hmk7s3LdaNqZimzOl7YmX89maefy/x/G6nYO7bzWdqfbubj8YWl1aVm9X6QRZ8HxQPKd2TH5VQco6Mrm//CoSRlxnBQPahsy8/MPvvriJcVKLrl/HN8tyt1yzqFTU6z/1s2YFg6MhSF+jPgufslPbH6Eyv2X2M/mwbu4GWeBg/G1D5tr4Sjh/CGo5ygOv3Mg/DEQ7jwQcQiEOAYifDQQHB6kk9Evx9GvMPp1H/0CFumfjt4dRh/F6eg5G0avDqOP6sOj5+NjwMTrx0CWN2fFfvT8b/LDJvOLKaKmpJQOiugs6SyZLJks2amY+D12qfVDwAuWXqT2onnazu1F9Ladl61zILhN8JsQaphpSwBJsJuwbIKDSXaHSY4GJjnAJK8EOiz/dJKXcZIZIeeTbIZJtuMkM8I+PMn2nUfcj6NnhMPo/T76vXvLn4z+p/Cx5JBf30o2yQ3zt/Jqgeh20VfxrRx//yyLQl4vWlsyP7+lZJqbalxyU3628oyWBcVOeXjZMXGkU0hPzvytTEWObTWgt/Z0VwrSnFYlne8MhHddToNsPd4kB5Iv0ltaF4rFVfYezZJb2jgsjMO1caRFIzVJyWnvTPvNWZMcSL5Ib/mQTYY8PN6c5ad+U3JpJGnlKUplpjslsJmV0jJWldamVPy6smRX9TS2tFxWpQBKFiulYaY1twagn5P0MmcfoQZbQbBVnSKYuKXM1hKrQsmJZY62ibPVgOwM1NnStWdCQ2yXFtu0ttebBNwkBq+2el3Bq8demwHeGSheE05UrxK82s1rMPUmBjexwaupXgN4DdgrrQZoZ6B6lazgk6/4lKFpa61cFVrDauets7VhnXoSK7GrDRGTmN1JjOpXJLZsJObILRLbVFNP34OyuyQGUOfmj0GZvQNlyn4OlIl4BWXuESgzd6CsLKn3oWwLBLUngZDkis+WR/hM3+EzFR7hs9dQVvL/OZTJ1SfsSlk7SfmQepWkfEgmkpQPycTXhDJJr6DMPgJl8g6UqfgIlAF5n73rReuUz8yzfJYSy0Zi6dUCke4iG/mMwtqb2xCfqbgtYukx2/gsXXzBZ0lh4zO585lat/a8AL3ms9TlxmKpx5tEQWIDn9neY89nFFbzPNwTPsvOKotlZ02iIDHMZ05t6JWcbXyWlXo+cxIrgc2ez5zY0Cv7rehV1Ts+c3xTyt3slTo+CyjkPZ+pAMEOwCx14g58poFZysRVPlO+M4D4jHKILRn4TDm4yQ1eD3xmsNdmYOkMID6jG0OVxxrxmYLHQNnB64HPLPZa+UzpzkDPZ4ogPlN2oy1FEZ+VztYGhvhMwU6Z4ojPyiuw8Vl8xWcO+Ixe8Fn4v+YzcYfPSpcf5DN3lrP5FZ/pR/iM3+EzzT+Jz8QVn6lH+Izd4TMt/yafiWs+iyQTGE2HmA+BZSkfAs9SPiQTX5TP5BWfyUf4jN7hM60/ic/UFZ+JZ/ks+QcSE7sod1Ed+CzC2qsGPtOwiKXHbOMzrV/ymQA+ozufadjSSXed8Fnq8sZiAiQJksJ8FpBHxGcBxiFP+Sw7aywmQJIgqYHPFkAvsfOZGvjMYiWwifjMAJ8JQC8x8pkGJY6Vej4TfQB6PtOw/aXlziziJZ+xnVkE8JkWnQHMZ7DHmp8qxGcatr+ShL0e+Ixjr80A6wxgPoMd0fxYIz7TsP2l6eD1wGcCe618pklnAPGZQHxWWittScRnpbO1QSE+K7GrDRrxWXkFGp8x84rPPPAZO/LZV4Sy8EEoI7eg7JlNs5PsrK9IjD9AYj7GWyTmP4nEzBWJsQdIzMf1DokZ+jdJzLxDYiKzlszUlQ8hf82M+RDy18yYD8nEFyWx5YrE6AMk5mO4Q2KGP0ti69kj7q5IjDxMYnpnLrOL+0dN6UYSYwbWOzeQmIFVNhggMcNfkphpJJZnBUjMwCpr+CmJaaAuAxJ805RuIDHRe+xJjCkYx3JOYhqoy4AE3zSlG0hsBcgyO4m5gcQCVgKbiMQ8QJYByDIjiTlQ0lipJzHTB6AnMQN0Yjo6MS9ILOdEoBMDJGZIZwCRGNt3ysxIYrC9pv3gdSCxvCQhr83A0hlAJMZgpyw/1pjEYKdM28HrgcQI9tpIzHQGEIkZTGL7TpnFJOahYUEkZnZ2wzVlhu8kxskrEgtAYvzPSezDhWRk/mQS89HfITEj/yaJ+QsSW+IjJLbcITGj/2IhWfk6f4Zfy/oIftlb+GWfLSRjJ4Vkwb9DYrloLOR6sZgPiXeSlA8JeJKUD8nEFyWx9YLElvAIiZlbJOY+icTiBYktD9eUSb8zV9jFdRfjSGKcwHoXRxKD71HB7yTmXpKYBxIzHYnBKmvcKYl5oK4A0gpSHEjM9B4Ria0wjvWcxDxQVwBpBSliEitvCW/OgMTiUFNGsRLYRDVlBCArAGT5kcQiKHms1JOY7wOASAzoxHR04l+SWPcdz+8kZjoDmMQ8xDYMJGZg39ToweuBxBbstRlQnQFMYgt49QOJGdj/M3LwOpBYxgDktZKYEZ0BRGK4pszsO1y4psxoaMA1ZWZnN1xTZlxHYi/3xFYgMXHrm+VHoWyN8yd/s/RR34Ky8DnfLBW54jP3CJ+pO3xmyd8s9KdXfLY8wmfyDp9Z9iyf0bNC/3dqymKuKQu5nCzmQ8jlZDEfQi4ni6Ww7KvWlCl2xWf2ET4Td/jMis/5Zqn4FZ89XFOm9kIytReSKbaL/MBnsFOm+MBnFhaxda8ps+JlzT8BPhM7n1nYarPitOYfKskUVJIpBhIf+Mz3Hns+47BTpth5zT9UkimoJFMMJD7wGdSUrXtNmeIDn0msBDYRn0FNmaJQzj/WlHmoKVMEK/U1/yjkPZ9Z2Ja0XR08eclncq+D32vKLO0MID7jAmJLBz6z0B9LBq8HPlPYa+OztTOA+Iwz8EpGPoP6ORMGrwc+09hr4zPfGej5TOOaMgMVYhrXlFkCDbimzMJfCWhcU2ZFx2drSlxuUtO601kEOpMXdBYv6cz29KXmV4D2ksIQQvE7CGX1swgVztKqvEKoB8q+0lDKD54rCHIr1JzofdYq//D+S2GeCtR7dYVAD9RqMVVqtdRruOD5rwhzGdTKpqL5PkNs7HBkhCMRwJpUk9leMaOGipm2DmxqW84f6lQg5eWedjm/JXa4uyXxofDE7x1RLauqWrPRp17TG+qV9tSbX9otH6kxC8JvYwu/jbOBlgXTZdMp5DRQ8kixCr99lRyynIXfvlYPVmuWcxSyHNSDlCC1LGdVZwBlOVyZYaGcgkZWyl1DenQYg+SkSEtOcl1QcuLL4c+Ryp9qQRKq7Ev6S6Rcoses1ie6lc/DW9R+mTbo1MG3nIfcLaVgQ/WXCpit/Y/JtL4cKj30fMif+fO+YfXNMkIf/mwd9Tfycikcfv6q3k2U88WXC7iUgrb9Hv5uFtJe9taTUp8OqsXH/wD4L+qK###3984:XlxV32DM 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f78eNrNm8uy26oShl9mP4C4CuzK/DzDHqSKa9WenAz2MJV3PzQI6Ea21zrRclUyWKb4RdPdyPRnpHh1225/iazNTfKN3e//GK9nF8uhdu24K9Yug7tS6bI8lq67Z1mABRiy/SxXqFSuSPL+33Kxvqno79CZb1qKeP9LltE3w+P9n1047AtMvEviXoYuteGuVLsY7oq1i6MuttUuga/y9/sPkUIGl3+Bz/vZ5zh8Tg98Flv3eXWUuZOjzJ8cZebs6H5ylNnVUXNyNOvuaGKPHBVrcrk8JZerk8+cnXzm+uQz5yefuVh85tBy1Of9/rfIO7/Jn0UPt/Inwp90q5f/agHl9i+NUOT9h7Et58ax9hn6Jz8+7fHZrpMsmt6wvTEk33yUm5OlxaiPbsy733/s21wDu64B3/hYA/loDeyzm0Vsp8SLB4k/39U8nROfceL/tQp85D+/1ZSWfNy/ly9pEY4IugJpuH+rnTAYLkjJ9wtKb5nl/r185etQ5YjCQdnbGKowUHQbY4iygaKqsmmsSAWKbGOIIhwooijHUo2wHLt/q31lgSBoGUjQtoxzW7VYb8OhWLBoj3RM/0zLwciMa24qdEFLx86bm4IokI6dtTGSKJAO3VLoDVEgHao5shFrNR2qzeM1Vmo6JKTdCkXiBQe4aFGN5S8tGpVts3F0QY1qT03xkigclOb7xojCQNnbGGptA6Ut/7ZhBaLaU1t+TxSIao+hRkXWOMA0h9NiJkIvUVUPU87oghaVaglxkSgQVctuypIoMJ1qq+gMUSAqtbXb3WKlRiVbVFZhpUZV/vyqW4comwxLN3Xj/CfsGPm2Z83u/ymbob233UQl3/cNvy17N0vbunezGMcWsuwbLKZ132BJrPsGS3XDOXbHsgDtM6njUx+fmAJSrc8JU0C5daDL4i6ohOV2bBuyJBgBBccQz3LlDxVxF1SX8rXBXeB/+Y7haXLtIrYgTcbUHbeUjHiUjJajspGs9GLqHb+QEE5y9mc4igOOTkQUKBG5F0RUvj6fIqJ0JiL/bOEPfvoQg/JKF/4FBpXV/AwGPXPpYCC+0M0KPG51KbwCnvg54NFn4BFn4JHnuqvOdZed6y5ffRavgUcU1MiCwR9+q5c/Bx50F7uvA54yaXwBMeXr8wpiMHCsPMPOeQ3nvM596ZTM+AxiSpooxESkDIiJE2Ly3LsjhRjDiYIgJu9EQRBjGFEmxKSssYIhxmxYmRCDKKVG9ZBSQDEwxDQIEQIrhF+mtTBqYkuKax4qdAHhlz0TZfJLyoIoiF/2SJTJLylzrGB+2T1WHvJLzQTmlznEL1HZNhtDFxB+2aky+SXljSiIX7QnyuSXlDJWML9og5WH/FKjwvwyKdktUTUPU0IXEH7RiiiIX1IkCuIXvREF80vACuYXRRTEL3Iri8du+VZ+poWJL4LgS7nrCb4ohr7l5XfUsTs1nujEUPrzsZ3pprd6DttfwEW8fKaj4GpUeO8/LD/2OF5/ody9SPU+pb/pEq++ju1NxH2U3FD3ndQ2SJEdZFs8Ltps06Nq7zKQqr3EO+uC3KokqUl1mIy8G+RRDIMJEuCPQGtCfkgWBIm0OBt5OIfq11D1MJtxqHKre45Yyz6M7t7NwtSDdoQAXgXNz0GnHjSbQU+D7LNB8/Nvdvk0aMFp0HV7EStYfDZo8SpokevNmh4TgPlZbq7y2yWbUquyZ+WPNdCy0ArQcrdq4uuOQcC50fC9EXoj/j9HJZXQ6YKWr/yxoCPzvPxS6f6qTy2o3CpxLwtqhxUNhzD96xmZXa/l2/Z88c2y+GldfKCfzy6+fX3H69MdzzdxmC37/UjQ9M59JkH/SlfXUP38VrcSEODso3zBRjOOpj56v9e/cG7SealpxTyg1CEdNafedQ2laueBUmVlDLoAKOxbXQFIaTMQuu0yCmFTGanxyHZaU9a5rCTIsZ6S9IhKDo6Aeiv2lm59BYZCm9D1CSHmGkypDEUSOeIZ4ebu4z1vuqJ66DN1fRum26Bxpa96UENnVHdVtxFHPDnt2HJaljrR9Iy3dejnLnVvq8ntGbfNgEUGEJOVLTwhp1s+SkVtUu5SadFZm1UvxqyBznoYiMgAYia5bQml4pi1YkzZ4XooUEjprM3jfl5U6zSZlTXbERlATOP3lv+KRV0VVdCHUCiwO9uEBvUVenvummAOofwu6PeuaKQjDZzUbLdIUKeVF7MAj/1a4HEXwScy8Qnw0Y/Bp0TOHoHPJ/fGjxBIi+cIFNIVBGLsCgJJ+UYE0vI5AoV4BYHq+flvI1A9kXsXAlUweYFA3gPkJMAdYB6boQVE5DZogVBMfN3ByFciUP0l9gSBSj35bQQSIfsrWCPdO7FGv8Aa/zVYU7aHATByNtVs6hVr5KiJoBGskW6UEDawRjqENQFd0LAGVmBgjTTdtnQEaxC3aDEYRY6WGi2NuQXDAcw4j3fKDHrEoVaiwXEMotGTWCzVQ/eh6yMMcLERS7uyEU3chy6o3ojGMew0Jho5Rsp9VPmW7INofGeLTY8qX5Pd2EMqZIAQjRTIaUo0Uo5Bcpn1IJqeMKgKZNbDAEcGCNHIDaUCE81RF9sgtsx6EI0dswo6ayMakZEBQjQWEc2hNj5xhGiqs03whGjkPoRAiEa6STSMPyIa9ZBo3J9FNKEe2/0+0cR3Es3+gmjcBaIJSV0hmnoG/zaiMS+Ixl4gmlD3ut8mGsbeSDQmf0A0gDCu/HDLARDGCfizw0FPhRk44zH5DyUaJV4QjblCNJFdIRom30g0Sr4gmv2LiGaf7GLmQc3kHCVXomGj8im5EA0bv6pNHkTD5COiMbkTTWSTaNiofEw+JZp90IsZJzGDcpSkRDPhAGbERMPmQYpYiCbsaFAnGiUHsQRN9dB96EQzzpvAxUYs7cqDaMZJCwSD9UY0JmOnMdGwUeXZrPImPyAa2Kp6lTd5EM2WkQFKNBk5TYlGzVRty6wL0UBVILMeRJOQAUo0AaViIZpxsCPjMutCNFCAyayNaKRHBgjRREo0cfBJIkRTnW1CJkTDBgMdz1A70TCJiCY9Ihr9kGj8H0Y0dYv7baJh+xuJRqkXRKOvEE2IV4iGuXc+ptIviEZdIZoQLhFNfOdjKvHBY6r6SKrCTH0kBc+qXD23Acpx9dxG/KlEs78gGnmFaMKlMxq+vZNozAuiEV/06Gmexig9m5NzlDkRzah8yixEw7fxtEQMouHbI6KxohNNQGc0bFQ+vj0jGjXOY5QerUE5ylCimXBgxUI0o5aqfSUajwYNojGTaBzVQ/eh6+MYS+nxVEmgp07jDEcpqh9PnQR2mhDNqPJsVnkrHhFNQM9/xCAa5pEBQjQMO02Jho0HdMwts65EEyKd9TBgkAFCNEyjVFCiYeM8iu3LrCvRhERnbUTDFDKAieZ4/asTDRsnLse7ZJ1omBuCoEQzGMhIQjR8m0RTOOEB0ewPiSb8aUTjrhBNfUv4bURjXxANv0Q0+tKLN/qdRONeEM2VF2+C91eIhtt3Es3+AdHAEyYrgV7gUMYqaMG5jYU3cjygTjHxhxKNf0E02xWi8dslognvJJrwnGj8V71MYye7uNn0sxlWouGjJoJGiWYCyz6JJjwkmr0Tjd8m0fBROnl4SjR20IsbLT9aYXnqJPCMmGj4xAq/Ek1GgwbRhEksieqh+9D1wR3g4kEsOyKaCVOW6gfR7NhpTDR8YAe3s8rvj4jG+1nl90E0fEcG6Hs0Cjm9vEczsIPrZdYT0Wg662FAIgOEaDhHqaBEw8dhIBfLrCeicXTWRjScIQOEaBQhmqo2Plneo9FDoO/RcDsE+h4ND51oBPzHNVY25HBjdgKNOYCmo0x8L8oQhHmELvV/ef02ugj+TnRJz9HFX3lhJrj9CroI9U50yc/RxV96YcamS+8MmzeiS337NTxGlx0eL8GZi4UTGQ9PliycyHggGQsnMmX0x9Sy0Mr/AOxoAs4=###4464:XlxV32DM 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ff0eNrNm02SpDgShS/TB9C/RIT1fs7QizQDAWa9mVrUsqzuPu6SEO6SICK702qqFqDkgZC7C/jiQZkQt4d8KPmYH2r+8V+9u/3hdz89/6Nx+Yfe7fYwW3j+YYzcH2ERz7+9lQ/xwLWCNeziwsPIdX3iJo3SN7+GvMs6lXUku24ed90s3eTSJkc3xbTJ5w62QKWQpIlump9w2l2lvYPSeW082WUXcFRgg95t2rTSjnbc5PL4g5dlzY6SuIuPWQpp/S1Ma1lvefss8nrR56FKpEMXUySagn1JkiuSL2sa9w45/japOUmTSif82yibNiwmRBwtjlT8KJWTm0qltE+srXusi01F3R9Or8tRVRVrVb/pLaYAfkJ/BjOseX+G9bfnf9vRqTdnp2szRZRYyBSB8+zHeTY8teXnOUdcO1errp1vtAJLyVWq/jcjo2aZSaFgy/NTrOUUUlh/nANOcpxD41zXMwlApolrLN2UJq4VdFMOc3CRKBlqBuomnLgsGapPxlaTsZ7JmOtA5WeTsXTJ2N2ZjDBKhm6ToVSXDNUnQ8kuGW0GlG4yYFDd+PD88y+YduoRfpgAvcFOAhbQH7TwT+gRWvinNY/Uxc92hpZADF6jc7lGy+Udj3W5f8SprOdjrtbGcjTi0SiXoSz3PGhMR2M+Gkutru6qu4da3Viru4k6YPvZ6sa2ukqos7rTqLpTW10ta3W7ksbXJd3aSW3asJXQNezlDNvVIc2fCfu7UxHvnPbHn+l2gsLzz3Qx1aY+myY3P9Ly53cTVgxQ4cEwc6Dszw+4vWZFHgoeBSdGKR+UEn0chEXGvmEjBo5DEtted4gPyNDzA+7nSdkNUxQqPnUa+TESFZeUZWWKQMXmY1hvxqJisjJRBXIKis7KyiKeQJkFKqswJJGQ+pLHo6Vry6TWBzwBc49zzZQumYKHIUh2C5Z26ePRZWnp2jKp9YEL7HKmg8RL7dhpUVmfuV67O3Rfh6TSxrrnkvWaOBwX1UuFNU3ShOmb8rRIt9CsLLngdRrMucKC7JBr71VWLFOw9l7mDEamYO1dyArvDWtv80Cip0qqvc3Br4oqqfamzDHHao8jUGVWWJKwXEOAqhzxmeu5iXjKs30lO6SIAdFyxJopCpUSl2KKRCWPcYlMEajk6yAGqmDEwJJZ2aiCEQN4ojL5iUY843nSqOE8G5kCJeI1D86cB01NxGX09d4ALQSn55HSXE8TSAc57lKbZSFH5rgtHrPM+ZAPzN9xHJQG76HA0PIh7WN6yPVE9TnxWGiAfRoDu6bAvj8HoF55e2p4u4frysiMjTVj4/lNRnYj2t3vadesIzo9nnNC1OfcajiTDrKhxNo+sewdk85fwqRbH8DJpPBToQ9AX5UzoSUPwN1x5PQlHLl3ARCOBOgYBKCvAlC2xUD/AgMtgh7SnnXYwj+txxb+acMjdXGNgcf0PHHwF2Kgv8PA8BUYmJhNX2Eg0NegONNVcWDeNbMr3AGd/2Kgsye6ubPpz2bogO58FPgG6OpjCo9iQGcFOegAOthYgW6vTwTYSoAu3ZypQrBtXdhIxqBlK1S52vK1FThoESrBffDBHkrUJ4L5awSzFbdcbfnaChzBlomcrCJYqIi1OK7X7g69DhbPVhDLnwi21JzjuKheEMzTYBmCnaS8n49nTxAskB0IgkGeJqYQ0FrZ6SgarYEE0qDROdm2ZiQFgDzZgaAR9OqYQgBoNWwkBFlWS1LWIMvJYGszkvLDw5Ed8khsiU8z5UCSn4s0cs4moXsod5JHPGhj4rSh8+2OWQNyk9UauHIQN/3sGGVLjOI/aSbOvZk4VTOx8Rdf+YouoY+88xVV7yvq6iseoMT9xeQrcmPSq/Iw8pSVxj6ihAfZGz4iJaliKVIrsfAWQJacKGQtSky9Q0TYylUTEciasdWo9krsr2qvpOiMMRHZI0ca6+4sPFkfmlYun7Pw5t7Cm6rF0bh6r9w81wzaxTurTU6jQfdWm+mtNtvltLHcVOfVdc5rurJvGEtCQA9phIKFithaYaE9LGTA1vxIXfyWVptImuSx1TuVdnBZi+3Igxd3npmcR2XqPDO1v+OZUaRqy7SNyvR90uX5kpJNYAam106UTCwpmEosRhw7eMEtKGeZUi0ou2+aKZVl5F5+nR5KtaBgzm1UOS0ouCLYMcSCEget5LDgR/mfqWhQFgw6aBZ05SZpN3pcQpIPuINlyXMJQWbySToI7ZAWfH7LLEkuJeMgHZUvkDqKEz8g9cuhuGL51Spk/DCG7MAcIOeZUh0gSL1gSgUTmLmWKdUBgtTTgRAHCFLvqHI6QJM2LLeVcuAmW08Dt1seVUYZo8gOzOVxE1Oqy2P3dWdKhRy41zimVJcHohJUOV0eiEpT5XR5pplHVYkJHmeliunBxqPKF4PeyQ4EiyCqhSnVw4GoVqZUD0fBLyGmYFQ2Td39IMWspKhMiUpRJUUFi4xf6R2tgp9bFL/Wil9zj1+cqa5IrHl3O3ytu/8jKIt3UHb5Wtd/Br865lKXzFUAS3ZvfgfWVfUE7jDsYK/mta7tCY1hWLzDMG57NUQGN091R2RyGTyhTiLjmHUFZ8172hGnifU1p3lzy2nxPU5b7jjtEiP9ayLz7pbI1lsi6zDMXGOY6p/v7vnC9UoX+y2R6QWZCxcaiUziQiOWycRm2yN18Tu6XpD6cEtZ2y1ltanXsn/ZvHeUpdY7yhrbW9+n89ENuWTA5T1RKnAFAlyVJWArAy67MYUA18oVAlyLYQoBLqWowoBrosoJXFPYWFQnUVHK2aijBEBFj2lYa+USYa0tcomw1rZwibIWGx9lLX+yKqGSjbAW3YGzlmAKZS3JFMJai2IKYS3FjmGs5alCWMsplnXCWv7kbNNE1bIW7MBZSzJlyFpJIay1CKYQ1lJMGbMWKoS1NL9CKmvBjufQVBMVZ620A2ctzZQBaxWlshb8JOFKZS0oFTvPiLWywlhLmBFrbZW1lhvWElc//w7mkr3bdfEJXfOS7pcZYO558e7vLQKT3dd0GbNewpj6NzB244l1BLa0BHag2zsENt8S2P4WgYnt0iMQ/dNL9h4B+Yju4t0ljDTeEZgSv94p68GneV8pjVF3XKbk57hM93Dgnu8gmnmNaOm9zR2i7QhhuDACnbO0QA8NfhdCCxfQxe+JaMbcIZpS/9QI61Ifu9QXoHuPyyCBjMuMJsrBZcaMuMyYhsscU4ZcZgznsuYYwmXCUmXMZcZccFmKinIZUyiXrTRezmWr4hLhsl1wiXLZziXCZYJlnXIZSer5rM8FaLnMKM5lNjBlyGVGcS6zmimEy84hGnXFZUZdcFnKOuWyiqg+NlF1XBY5l9mZKWMuiw2XBaZQLjNUueCyeMFlKSrKZefPgrmJquOymXOZjUwZc9nMuWxxTCFcpjRVLrhsbrksjLhsr1wWr7ls3d/xwAqPvfivDV/mgTX0NrTD/h2M/UI7rDG4Xjlj/X90+LwdZtwdjCn9Hoyt79hhBcKGdtjy2g4z4RbGzBfYYY39NXTG3iGw+ZbA7P/ZGRPhxbtKg2BlEbFwIRy2cCHwhaXCBXTxm2LX7Tf7kJ23sKufziOTLF5Okk85Y5BLTmALUSqBxSGBNV/Dm50pYwKLnMBOX4d/DQ8sMFPlgsDiFYEFTmCCxcsIzBOlITDHJfoW0nKJvoU0XKIEFugoGIGdIZGnehgS2NwQmGTKmMDmhsAiUyiB0YFcEdh8RWCBE5g5DwlNVC2BmdAQGFeGBGYCJ7CT2kzgBHYm3oQrAjPhisACJzBSCtdE1RKYcQ2BGaYMCcw4TmCEsB0nMOGpMiYw41oCiwMCC6IS2Pr6I7B1fwe7vugjsNizlus9sPmtj8Cmf/QRmH2HwFrsyt+H/UvsOkDK9iR2YYd12LWNsWu7xS5/i10da63vsNbr78LEHWDp+r7RhE/+186lH17vIRUMe/Vd2NQO+tbt0uto0G99F+bewa6OtWTLWvEFa+HnX3DLhxYuBH4IpnAh8M2kwgV08Xuylr21uPQ2Sv07rFXoSfT4dWF8dVXYOWudX0BBLhlrWaocrGWJ2+Xr88I2btdpbljzP8EreQg=###4212:XlxV32DM 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d54eNrV28uSozYUBuCXyQMgCXSxK/s8QxZTBbpUZZNZZDk17x4dZMN/JJBpp1PpzMLG/DYcH2zzjVBP4v7zLzGncBtu8sevwhpxM9Nw/0Y3OdHzgsk45STf/Py5CKvcTdxEvE03KX/8qZJON5OcuP+mkrHrrbv/otIUb1ro+y/jKNLNLsP9j7yFvNEcaXsbRQj3vGoaYFUc1lUCnxXXVTKvonuFUbrfv5tgShRcuY+4j+jp1VHjKreuMrjKrqvsYwMOI037SGKNrFTlfi3n+ZQk77Qq4Cp6H1ZbXDXRKoNvLYl1FduWolV2pt18t8487kPZ7TyU+2XEl1CD7ILvOvl1Fb7rlNZV+K7Tsq5iReZD8t2J0kkn193mA25o47S14Uc5rrkv452OvL6lMKwHO920XrajLUN1tOWw1EdbDrE+2nLwZ0dbDlSbij5RRh9Do9uqwlaVOKhK1Z9BKdqqhGuqEva0KqHrqkxTVdJbVfKoKlVXJcemKimbqqTeqtpWqXtdoJyqAhUd3cgLNPff87dW3uwPQR+u/CSdb/JnKi8ZWqKHytISPcyb+Pl4R+Vf3N7LiB/fuXxc/ePb4+Xj3j3uy/NycdvC8lzwz4Xy0c9fdvtccM+F+bmwbM23dfPlILfmq6Pmu6b5qW1+aJqvhrb5vm1+xObnX1U/PH9Vcw9zA+7f8reMklL6M6H3dP91XUmvpicYb7YfZJt/qtX9W/7u5mRMg2OJpMSsP+9+ZImgRFOyDDwZKJnWEpeECf3w549ESSIr3uVkXk8WVk2Y2Py26IaqNpjQ4czvOH/D1mjkkc+vcqZEikdLPvskUSLJo7yvfAooVTiswlEV7tHcvXemdHTrcynTa3hCaa6RpbmWJdRcU86dXrGEmqttaS5PqLlTKC30mKzNnWRJZtZc2k/+Nq/F77XpqvjSSD/BE9bi8zmsFG9YIimxpXjJEkGJKcXzhEgQdSnRYbKSID4+M4YVT1srtdn9+OclXrwtxUt4Qil+UqV4zRIqvvRqXn9Q9oR2N4lSPE/AMwvbGvdMPPKMPPSM+V94xpx7xr70TExf3zNyEK1nQuuZdOwZ1/PM+F95Zu55ZvpMz5hzz9i6Kt/zjL7mGfFveia+8AyxRc1kF0dLCy3RjQq05G/rJr6oZ0LPM+YzPSPa5sem+aQe7pmdBLHyTIBk80w49Ew49UyoPMMT9AxPwDM+YIKe8Z4Vj55xmDDPzJBUnnE8Qs8YHqFnNI/QM6y5zDM7I/x+Vo2HnvGnnvGVZ3iCnuEJeMbPmKBnvGbNRc/sr5mr4hvPzKeemSvPaJagZ3gCnuH7Qc/stFuLR8/snzNXFd94xp16xlWemViCnuEJeIbvh3lmlEeeUYeeseeeeeBleJwlREudQ8TE14iZW8ToDTFPuVSDM67yzRuImVrEDBtiGrnIj8tl2eTSDL/4mitPwVzhSuxxxe5nAdPhSjw7mE/JHBrF1xpIPaO4g1IOjDK3RtHbCak+Cz3GXlTFF1aVHTpGsf6oqktG0a1R5GmvaNCGVTXKFzAhf6hECMn/AbHjQEv0cMzfXuvpYd7E14SJFR2Y2HDU8RYm/vQjKUOjkQdQuhoJ2y9sbhzTiBWQPDWSVx5oxIozjazJrpFlCCzZNTJ7noBGwoQJaiSMrHjUSMSEaQSTSiOBR6gRzyPUyMIj0MgosQrUiN0GtfLS85xY+lxrJD/hRCNrsmtkGTxLdo3MniegkaAwQY0EVjzTyD7clariG42kU40kppFlWFiya2T2PAGNBIEJaiQMrHjUyHb8TayKbzQSTzUSmUaWYWbJrpHZ8wQ1kjDhGtFHGhkPNeI6Gml+n59DKQdnjSdQPmF0pYXJJw2pyJ5GqlGWTx9Seeqjb5QPDKlY2TGKjdeM0v5P9TF+cgSDB1u6QypWdbhi0zWuLFe48nIcxY4do7jhbaOMPaNUkumOo4y6zxVPKhkV0UTSEl0m8vRwpMtEnh7mTXxRrkwdrjhxjSvtp/NhkhdyuTKOEvYTua7kMkGyyWU6lMt0KpeJy0UIloBcAk9QLgETJhfPige5gBk0l4vFhMsFrKYruezSKBHKJfEI5aKxCiaXzVx5aTt/6kO5jKdyGblcxMASkEvgCcplwYTJZWbNBbnYXTuqKr6WS37CiVzWBOWSWIJy4QnKxWHC5GJZ8SCX/fhbWRVfyyU/4UQua4JyiSxBufAE5BIMJlwuy5FcpkO5zB+TSziVS1QfkctHxlH8/Q25lGs6b8ilkOe/k8tyWS6mIxcn35bLcj6kMVyQi+3IxamuXD4yutIiqpWL68llvCYX9a5cxAW5LC/kQrNXRroM5Gn2ykiXgTw9HOmqkKeHeRNfVC5zTy7TvywX/1oucfvxzz3kcpkh2eQyH8plPpXLXMlFswTlwhOQS7SYoFyiYcWjXDQmTC74mkoumkcol4lHIJcdISVCuSxYBZPL3qH9OkTpcyMXdyoXV8llYgnKhScgl8j2g3KJE2suymWvwFbFN3Kxp3KxXC5iZAnIJfAE5BJZgnKJihWPctkrMFXxjVzMqVwMl4tQLAG5BJ6AXCLbD5dLOpKLPpTLckkunStAHbnQJaRXYy6uN+ZS4cW2k1z+Z54J7eSWeGlyy3XPLD3P6I96pnO1qOeZWCPC9zxjro3EuN5ITEUa2c536Ssn9JRjv4By0gvlEGZGms7iaXbLSFeXPD0c6eqSp4d5E19UObGnHHdNObFtfro0z+WCctI+JpEq5URINuXEQ+XEU+XESjkzS1A5PAHlpAETppzEikflLJgw5WBSKWfmESrH8QiVY3mEymH1MeXsY05hP9emQ+WEU+WESjmOJagcnqByIiZMOYE1F5WzX6fyVfGNcvypcnylHMsSVA5PUDlYCFcOO/5MOfuA1FIV3yhnOVXOUinHsASVwxNUzowJU840HinHHCrHd+btpnberurN260myKiKRW/MfvG9KbyVlC7+ddIV5Yhm9stneCZdGp+Jm2cOEZN6iJmvISa0XBh6M3SruTKqUg87G7uh55nl7YkwS2+ybgWh7t8hOdnzTH9OzBXEqGYiDN//NL7gCqlkokkunua8THR1KdDNRNeUAl1iypv4mlxxqseV8C5X1HBpUCbdDzpOANh+5nPjmFGcguRpFKeOjOLUmVGcqoySWIJG4QkaZcEEjZJmVjwaJWGCRnEDJJVREo/QKIFHaBTPIzDKNGIVaBS3nQjdfiWj9Lk2ipNnRnGyMkpkCRqFJ2CU5DBBo6SJNReMsrfQDVXxtVHccGYUN1RG8SxBo/AEjJJGTNAoSbHi0Sj7FalUFd8YJZ0aJVVGWViCRuEJGCWx/XCj2COj2EOjhPdGYj4NJh8diXljWm4ZMnkFk8dYy8nfFn3YKOkTZ7/EwzEXN/a4Ev/xmMubRplOjfI3H9iBVQ==###4292:XlxV32DM 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f08eNrNm02O3TgOgC/TB7D+rfeQ/ZxhFgFsSwJ6M73IMsjdh9Qv6We7KuXKTDVQeoppURJt8SMl919ai/SYlXz+o+IWH9Pj+WsVahZQU/A3/fxLJRMfcJd9/kclax9i8uKJV9PDOh2ef1UV6vm3MxLagMzODy2lfuIlVJO1p6ZdeqhFrt09/62Sk4/5p1AaOlESC+2whoWesYaF9o+s4lcZTir/xT4O/fx7npfc6ezz79/zJuqvrL++/i5tcL2ytsrWKiHfq0WYW8W3ytIqa5mb2nIPgs5NTtPzXzC3qRlNBdsHO+/srvZ2l5Mcdp+O7O5f7B6P7P4DtONd8ue3bD4c9PNb7hLvgRv0FDW5AYzz/JYnhCNEBWbZmhxaQafP7/PqsmppaMt5AQkUINFpJRK05vO7F76IFi7aoJV3ReS5aH1+d0kU0cxF0JcLdRS0FTx81BfK1Kc+clHm262wlKmrcgNMWJUJNyv4MvWFKChTd3k8ysUmcWmn2hfVsqvWXLUsqmeiIKt2cS6qu71d2Kmei2rRVRuuWhTVligoqg12um7lecE/1bNJVRbYKoj+2UZUBK4IZiefzQpFMFfBOj/bmwECfJ2nBEshPmDB2p/4EoOytMx5NZTSP8trbtatvc/rtHufRUjkfYZHndccmIjcAvbCS77ckupqd4LcAm8PXqoOoDsIV3/LIofXmTbBhQTTyrfAS4u/uMTFfomLKE+XuNx2S9y8uNao+xKf08ESl2G/xKdw6FphbNPr2NbzsaXd2Nzr2MIYWzxyP/vHJcV8MrY1vYwt6XPXuEOSDldImsP7kKROkDSlN5C0IHSw0CvWchGgmCLWsAAVXxNJa7yDJJ2ukDRv70NSOkGS7s4TzNeQpNMRkuCGiiSYUEfScJE67ZDkaUuKpDgRCUdSSFxEkRS4iCJp4yKCpIkqZEjSY+TDuRcr7JG0pu7csxUKktxCFDAkzd3tw4rmql+QNHHVFUmJKGBImvvzmM1O9QuSBFddkRSIAoYkz5CUpQUwC0NSHlERrAxJekBsY0jSaSBJqAMk+UMkhQskhVMkvcmh6bM4tIY7HDLikkPr+zi0nvn67Q6HjLrk0HLJoZMBLXfgY8wlfPz74CNP4CPUNXwkhFFKwPCVwkIIrGEhJNawABVfFD7+DnyMu4TPfA8+prtJMF+Dj3FH8IEbGnz8gM+smtw4Dp/h9rElgw/VyeETFRcR+ETJRQQ+zeE2EYGPoAoZfEwfhRluvFjhBT5Ld+PZCgU+syAKGHxMH6pRO9V7+ICXYKoLfFwiChh8TAe3ETvVe/isgasu8HGBKGDwCQw+ZmQ3kcHHqC5IDD6m4ypMDD7GEfi4A/gsh/CJr/B5MwnybydB8tPgM9+Cj7+Ej7uEz4mDd7eIs14Sx74v8/FnNLS34HOd+Zh7m3HCXcNHKcSLRtBgIQzWsBC4QaewABVfFD7mFnyuMx99Ez498wHzdfgcZj5wQ4OPIfDp4b/ZZT7E7bsdfGYi2cHHcRGFj+UiCh/DRRQ+VCGHT898zMh8ihVe4GOHG3cDPjNRwOEzjLLuVL/Ax3HVBT4jdQIFHD6jU79T/QKfmasu8BmpEyig8AmCw8d3lEgOn7ULFIdPz3yC5vChmc92AJ/1ED7pPPOJ0/MzOPRpm3GrvsMhqy45pN6XBMUzt6/uIMmaSyTJm0iSd5Bk3SWSxL3NOLG9gSQ8BhJ4DKSwELgtp7AQuC2nsAAVXxRJ4g6SrL9E0nQPSXbQYetIsv4QSVtHkhhI8h081u+Q5GhLhqRAJDskbVxEkbRyEUXSwkUUSVQhQ5Ltbt+OHbNihRckyeHct44kL4gChiTbjWbNTvULkhRXXZGUiAKGJNtTLat2ql+QpLnqiqRAFDAk8fMh29OewM+H7Eh7+PmQ7bt0gZ8PWT+QJKcDJG1HSNqmD23G/V+QtKRbSFqvkOTSvX25Jd5CUrhCkov3kLSEW0hKV0hyN8+H5PQGkjaEDh4IKSwEHggpLATu3SksQMXXRNKy3UGSE1dIcjfPh1zf8QHzNSQ5cfjJwtSQtGwESZ0GTuyQtNGW7JMFQSS7TxYmLqJISlxEkRS5iH6yQBVyJPVGlnxXMB0haRmbXdkKFUkzUcCR1Kduw071HklL5KoLkrwlCjiSur3tulO9R9KSuOqCJK+JAoYkfj5kRzLEz4fsSIb4+ZDt3zIEfj7kREeSTvDWPgCQsGAHkkJFUoORuAcjdwtGlTj9Vlg6FD7rHfi4y3zI3TwUWpY78HGX+ZBb3gcfdzY2fwc+zl/Cx9+Dj8YlsR3Dx+HHCXgqJPFASGMh8UBI47adxB07aP02d85483mc0Uv+NkUek0LOeuyngYNmpFDESPBIKSH0sna3CxMthMhdVUIIs1Rflq/iOs/LnvteaMoJYIlkRwDDRfQLAcVF9AsByUWEAG58/jX2lcpcqp933WP67jFxxO3TNEEU8E/Tui91Zqe6+nnbVS9cdfXzgSjgn6b1CTm1U139vOmqV666+vmVKGB+nh/FuJF68KMYN1IPfhTjeoYR8ZQUFiBEbiIMdx5ZbqHV7tszsTtraaf6bne6XxeKnasDr//OX6Tgwtpo6gC/sXpvS7w4uG5ZV4rMe5fgw+M8vcOHu2MfHrS9cuGWuMmNu3BxcrQSNQ7HcI2mrdu1K5RBdYWR2mGt8832+UeLTbEJg/cN3nycDFFuR2DAxm2Uw/G1uS8cEedzF69zj33ufsx9KBS/O3f9cfJENR2B571zV1dzD3nupzlP0O4RIMUJeobfBL8e/ib4Wx7Y9Jw5I8dZxP8214lavjzONPfH2T8nkLFvNyjzW49TT9vrOWTyXZsFxzHF/ujVxzOvqPRR4vXeR++vX3u1t5OcVLeTG3Yag1t+x04/9Cryo/j5Dd0LXn9+w8XWarLXVKl9z+WvH1FVyGYJKAYyyyKosMOXr8QBeKknivWbsCwueSKav+aJCIqiFZqAXTBGsKUZ0QrvKwQX+IThGaI0THpMAmZd5lArslVUrkBssWFPMrbxyzp+IAMqi/k78KYMEueirFRkq6hc+Y7Frx9hWcfocphS7lhlFs5M2PRUoWnDEPlSu2vNQtmEExOinYtbaBYZCWtxRdmENfhqT6JEMVtLKdHhlXigPAqfrRJG42J/O+fryxhmsRZwNwvq48QK660ENpvovRnWW2nsR+PcG8A9X3dj3rW3HM0EbdqcLe+txDpbnXpGN+1NZK12NC69Gby+1s9QS6BThDmciYLEOWWI5bokYU4xVLmuSDZbXuAc/QSNn98nyBzEMoKfxHJZrcKfCX6WXRDEgp+DoCd4+fHENar5KOh5py98K/zRV+GP/ZTwR9wIf9SfDH/MVfhjPiX8me6EP+kPhj/xKusOeoUwR8LfBn8K/gL86Qc2+wrpdsx5wGmoo++HOiGbTl4FIJJsu2OXL7EHe9fcVcyhPjfm0D2+ML1me83xmCO07w6zhMQc1QTo2mONOYLpm9NB162JkD8nHEEFCRt0CxJMq9hWcTRsINSNdKsiqh5O2NNwQrfgwbSKbRXHwonVjU5aOOFaxLBqJmx6qrDFT9hHiRjiCCf6GDUTlgmkRv7U0RpJ2JA6yAdaYwsbVBiNadig1jEcFjaoFjaojfdWw4bYexOst9LYj8Y0bFB2zI+GDQVLucHMe6thQ+i9SdZbDhuUGY1Z2KBJ2FCEJQwwNGxQI2ywLGzoXwRpF6aD3ZF1YrsjElp9sd2R8PHdEe3E5ZenTv329giYMZ0HCGEcit4JEGT4eICg3bb+sQhBuzidhwhh+P87IYK88f9uwOz/XIwAr5O+2iMB+fKAQmCxYiGx2LBQWIRHVvF/2yv5L43/+kc=###4388:XlxV32DM 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f78eNrNm82u2zoOgF/mPoB+bStG9/MMd1FAliygm+miy4O++4iiRFF24p5OEuAUaMIj2vyRHOsLzTix/mOMTLdlE+uP2cqbuMG7hvefc1zw732u7w7Hkyp/LxPql7n+PQd8X3x9L3//XFys7zuOb1N9L+f/dAqPN8oWYdNxgkjgv/j4Rye734zc1fofneYccR5Itykf1IJXYf2p91Cs/96M20DS49mmnG3X/+o0TbeE//ZmbDaejMXzTGTjqRmPEKMdjTez+zI1iypqsrjzudlq7mXOfhoZ9JD8b8henLPfHmefxuyDPGcfP5u9Fn/Ifjtnv1P2tmffLcq/zN6mU/bJPMxeq0P25pR9mj6dvb7M3kbIfB+Nz+u/2bi6LR/G5g9IPkjll92DpEHaQDIghVsx8fsYR3Vu6KOTPyr1IxRkfa8fseDqu2/BkbA1ITQh4tzK+jnOgmuCb8JGKxtOK5sWWllDK7vTPUPbv13Z/biySojHK7scVnY+rqwS6tMr6/5wXcdj9kpoyl737Ht4/m+y/2W8hMm3H9/KLQQU67fyeSIxdDGi+L285pNdgFum+qi6bH79nm+bqJqrCq4tWFGwkAchPThApJ0dkK+c9VtZCphbNGCb7XxWnqT1e75DgyYKw0LOSdaImxRIikX6nu/4cJ6NkntcPGhqsJryCDWPvC2U+RETdzaH5qxKgaRYpO/wks+byrw2Z3DVt4M2hfp51JO5pqf0wVsepCM31PeQ/aj3mKzlyTpI1kVM1tDEGlwOWiSPKxPxgHLTK+vRFsmhAcUM4MpMC2oECxrnMW/LqJJ0kjx4deg1NK95oxm8ooEtMQPFayYA1EQ2FdVrxIC2dpGBNHpd0OtGXuXoVaKBwAygVwuaIJaiyH/qtWl1Ubiq2N3agkWFR0UGk7XNHSq2qtiWtV3uWQE3AC/znUnKW7zJ+AGf+3SbU8D7y1Je3Yp3Bu3kF6UmG5+hprKTvI2a9itqUq+gJhueoqb4TmpKV9QkX0JN2zPU5MUbqakwyxU1ReCiCQhpB2mGF6CmsIAE1JRNfFFqElfUJF5CTf4ZavL6ndQkL6hpTi+mpr3zUeqi6KI8UpOn/RN0AzX5tqvDtdWoKQ/eoaZ8QKMm36nJ0zabz3pETTsRUiJJkCQP1GS5R05NjnZkSPcRNe1ESIkkQZIcqMkmw5wRNclGRTapUU/mGjV1FEiNivDISk0b6fdRj9QUHE+WU5MntPGCSAIX6URNG5FEWSSkJrczAyM1BRb0gZoonyyNXo/UlDeawWs1sDEDAzVRquUSHqgpeDrJH7weqcnG0StSU1iYgYGawkBNRYsMFEdqiqTYB2oqc4eKNFBTudwbNcV71KTvUpP6qtTknqEmP72TmtQFNc37S6hpeYaavHsnNekLaprjS6hpfoqawjupKV5TE9QBbChlJqCmUMpMCSQApl3ciokvSk3mgpryBvUKapqeoqb0TmqyV9S0vZiaVOcj3UXTRXuiJto/y/f3gZoS7dqxU1O6S02RqGli1ETbbD7rETUpIiRNkiHJjtTEQCKO1OQ7gpjH1KSIkDRJhiR7oKbAnBE12U5NftSTuaan7Rq8VSqKRE029TKfGvWVmiJPdqAmQhsfOknEu9Q0d5KIRE3eMwMDNXke9EhNntDGu4PXEzUto9dqYGYGBmrylk3FSE2eZslPB68nanKjV6Qmb5gBTk1SDNRUtIWBpByoqQSLCjVSUyCFHqkpNWrKdyCApnibbkp1aLIDLk0pDbikYXWyKmNQ3gXFmoeMrXcYwVV6bTefNhRTGVJ8KK7t1kQnShiqN+25PAwglQPVbvnQVIYmPuTXhm80NJehhQ8tK8Hdj0XhnWsx/KwEkSxDvHsqQ5EfpdZGhTQE07LMkoNiA8IfS/laAbfN6nMz/NTiYOMp5lt7w0caCmWIBatECXYbwoDJdaq4zYsN7uYjH+LNXk60F5mMyxwK+XorsT9abyXFcb2ViMf1VmI7rrcSOWO2K6XZnOOMFKfqcU4Dvg1xSkdx0lC5UMaQ/SlkOZ9Clst6b/fMG/ApzsxcGKeaRbwXqD4GqvQpUCVPgSpzClQpCvR+dHC+vw9t5iNN8Zam/QafeDj0MZx1KPPyM3D2SfAS6c6z1c4tc/6+JSiV6TjRgEB1ooFI2kT3O1UBH41ex9nV4jy76Ty75ytXy9OVm7/isDn/5WzdQmBGgTgyrMCWiAnUcUQVGGqkstutqfEmX27Uv3/pvT3JQIUCxYyKyBWELlLIQSFAYVFhmMJYUBhUOKbQsI1vsGkYKQRLxsu8c8Ca5VWBTE3gmbp8lhclU35ShwL8rJRxW7fJOheFCPZJdDXOwKxwajxXwAzMEhWOKwgR0i75OEyALQHExMZL/laV8cjGS/oGpthpyxMEx0qXRGgezZiIw7CWri6JwC5dFDNXKFAsqJi4gqgjxY2PCxifyrhj45BI3g7LOHcAieSdsyRieCJgv4SKu0EZ12MiNSzb1ZhIYYms0FwBidi6VIorCGRSHCxBIrZcKpEbKomYkki/6HVNJL9AicckC7QCX0V5iWceaWWL7ynu/L9Fnd19poFoflDUsffKGrRpi3nqX/rCJ0s5Vly1Dfn5JaUc80Qpx8TpfaUcK67ahvz0klKOfqKUY9I724bKHn5RyvFQxVmgbJMJ1FgHD8A2KOX4UsWBl2zidbTwwlKOldNFKcfb50s5RoQ7jzYdWZsAWna6CtQTZR+T3thiZJW4KPt483zZZ1KhlTXgdlMLPPDZa2JerCYqcSj7GKo9FB0v++C8FJWXrewDg1T2oQcrcEAr+ygq+8Amgno4i5d9BPXIlDORePKC5yUdq0KQEVaAIKEq5XyqpMRQFTKJHu9Bzrz2E8qmQiZLnaeYRAlMoqTEoc9IsEhr7accVJ+IiX3Uk7mmp5AE9RnhkVj72am2Jvyox9oPPXAsM8VqP4ae5YHU6iG4Ulj7aX1E5S7Z6iFlpRwaUMwAr/2Y/kxSHPqMcMMoJ8Xp4BVrP60RqexMg9dqwDADvPZjNsumYqj9WCpGWVZxQq9Y+2mdUYUBBq8SbRtmYKj9GF77sazEY3ntB4NFxcRrPzh3qJh57QeveXxiZsXdPqPlzhOzadu/6hOzZ7qzTXpjn5FV8gqz9Esw65nubJPe2GdklbrCLPUKzDLPdGdb8c4+I/+H7ux8P8oHQXd2gBcP3dkBXjx0Zwd48V+0O9sqfYVZ8hVPzMwz3dlW6Heik7lCJ/FadFKyQ5Lqou6iOaCTFdQso8yITrbv+p66s2HwzhMzT93Zpndnw4bR9sJHfUYQcuMgRZImyYxPzBhIjN3ZJhGCKP2QmpQkQlIkaZLMgZoW5oyoyfQ+omnUk7mmp+1a0RMxz7uz+9TLUV+pyfJkGTVZQTwnep+Rv9udbXp3tredmnZmYKCm/phQqQM1NaNFGr2enpiJ0Ws1sDEDAzUlx6ZioCZDzyVBGr2enpjJ0StSEz24BAMDNQ3d2ahFBhq6szFYVAzd2Th3qBi6s/FyR2oym7tHTe4uNaUvSk3mme5sK6Z3UpO9oCaXXkFN5pnubCvcO6lpuqAmt7+Emp7pzjblmnoXNS37H6gJSlIeurMDvHgoTnloNlqgAclD1Sqb+JrUJK5+0+biS6jpme5ss21vpCZx9Zs2F15MTbbzUa8yidDF42/azEbNMuLwmzacl6Jadio4bds9asoHNGrq3dmwYdT9Kp/1iJosERLVkUQg6fCbtg4S4JFT00bVMREeU5MlQqIKkwgkxUOfkWbOGjWJ2PuI5Kgnc42aOoBMjYrwyEpNNPXKjnqkpmWYXl5r2ggEtoVIAhfpRE29O7ssElLTNjEDnJqsWFjQAzVZQWgj3MHrkZpMGL1WAzMzwKnJCsumYqw1CWJTMR28HqnJxNGrRAOGGRioaejORi0y0NCdjcGiYujOxrlDxdCdjZd7paZg71GTJ2r6H/X8Fm0=###3996:XlxV32DM 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f84eNrNm8uS4yoSQH/mfoB4Cyt6P99wFxUhXhGzmV70sqP/fUgeSSLL6q5re6YqwlaKFJkkIDgGKhm7/SWSijftl+0vKVm6rW7Z/m0Uuy03uAq4fjdhrffRtKut6YmX+1VX/WravfH1uu7tWu6/rza0a6zpTrdryf/d8vq85KoITgQJnqA0y89aVMki3/4lkllK2dNNi6B74bnfvovoi/VfTkoHkphzy5Jbbf8RSetbqn+xGzNyR2Phviay8dSMqwWMq9l4Nxut6xZ5EGgx0rpxLfZSZ98l82IK/hdEv95H7x5Hn+boPbuPPvxp9GL5TfTpPvqI0e8j+mGRfTZ6cxd9kg+jF/wQvbyLPuk/jl5cR2+h2HE2bra/s3F+W39KtYebVGvKX3vWKbuABLeW5S8Ht9nEr2M5mnOJr05+Vdor5Fm7tlfM23bde+FQcF3wXQi1bll7j7Ngu7B3wfXY2HLXsmnFlrXYshHHDKE+27L62LJ8WR637HpoWXNsWb7wP25Ze92yjB2j54vA6NcR/Sje/pnof2juIXr181sZQkCxfSvvUxdzA6DIqvhRvn/9yMFDZv6z6bL57SMPm1Vluir3LWjRbAESITx4YEmRPJB7zvatNAXUbTWgmh5y5UraPvIIDZqwSFLkHGQrcZNygbvEivSRR3zIp9bJ47qDphVWYBxLiyNPC6DyZbZAZ8Z3Z1UCZ01iRfqAL3CWHHEGvb4/5HjV21mP5roe6w+85UR80lW9Qn2c9SWkOihgsBaCtaEGK7FiZW0ObKS9tkyoD5RBr7RHbyRbDXBioLaMXqtmIYWu9Zin5apimIkdvNrq1aPXdfZaDbhEDBSvmQCqJpCqaF5DLZDrTQ7S7HWtXh16tbNXVg14YqB6VaDxvIaab8XWtaIoWFNEu/XCVkWtttxD+NbrripEU7h16909K2B0CSyPTLnXhBsLP+G9TzeTfJ111/I9qIl9VWpSz1BTmUneRU2MX1GTeQk1yaeoKbyRmpi4oib9EmoSz1BTWN5JTfqamhzAkRVASBwkCRLcWgUS3GYTX5Sa5BU1qZdQE3+GmoJ4JzWpK2qSr6WmPIQgH4khyiGqIzUFnJpBN1FTQBDJfatTU048oyaN1MQHNQWcZnOuB9TEOBKSQEmipGZqIiChD9SUMA75kJrAWSMkgZJESU3UpBfqDKlJdSrSC5v1aK5T0yiSQCrShJoQFaBcVN+oSdNgKTWFBSt2GSShT6lJDJLQg5oiMTBTkyeFPlBTQOgJB6931CRnr82AIwYmavKWVMVMTWUcqpn2g9c7alKz10pNfiUGJmqSEzUVbWUgNVNTQIWeqKnUXVWYiZpKd2/UFJczavKn1MS/KjWxZ6ipTA5voyZzRU3iJdS0PENNwb+TmtYrauKvoCaRnqKm9E5qcr+hJg1ctAIhGZAsSHCbIShLcJtNfFFqslfUxF5BTSI+Q02Rv5Oa9itqWl5MTWbw0TpEO8T9SE0Rp37QTdQUBzU4pKbIT6nJdWoScVBTxMk953pETQYJaUXJorQfqElTj5SaApYFwn1ETQYJaUXJorQfqGklzpCa9kFNZtajua4fy3grUpFDatILrjVBuai+UZOjwU7UhIs2WUKScGfUJNIgCYfUFAIxMFFTcKTQMzUFXLTJ0uz1jpqW2WszsBMDEzWFlVTFTE3BYiZ78HpHTWz2WqkpGGJgoqZ1oqairQxkJ2oqha2KfaamhAo3UVPp7p2a/Bk1hVNqEl+UmkR4hpqieic1uQtqWtMrqEn4Z6gpru+kJn9BTWt8CTW5Z6gpundSU/oNNQEcWQ+E5ECCDTsHtxY27BzcZhNflJrCBTWt4SXUtD9FTfGd1BQvqCmzwGupyQ0+8kMMQ4x31DQWPOKRmgYUpUFN8ZSaElLTTqgJp9kYH1KTQ0LyKAWU4oGaHPVIqSnuGEd4TE0OCcmjFFCKB2ryxBlSUxxU5GY9muv6USSPVJQINY0FFjfrGzUlGiylpoiLNtENkkin1OQGSSSkpmiJgYmaoiGFnqkp4qJNXA9ej9Qk/Oy1GdDEwERNUZKqmKkp4jZvVAevR2oSYfZaqSkKYmCiJj9RU9FWBgoTNZXCVkWcqKnUXVWkmZpip6bgJUCTuu03Fgc0pQmX5L7e41JWaeDWEDZI4jQpbicw1cbgGap6lrhuhK+4OOGs/mhaNjoAPUCtfTlBLjTht0FfloeZwkLdjz2DsD7g8p0M3I7g2Fw5fNEbHctDWXuRR0DrNvEXuuHunsrQpjtWOF/8dja6h5AeIxvf9+eRLTB7xlzNg8UJSQ8P96DVo2DrNpU+Lo+Ri+/2eeQKbD9jpl56d1Z68aj0nM+lL5uTD5Ep8OUWWP7w/HsFfrNwnq/5k7s+ZH2MSgORdva/RaUQ2WNS4vv6PCkF5s5QpzfIetYg9mGDhEN34o9Jh+/medKRrm7H//wGL15FGujEXWIo8ZlyQj+GBC0PnJIRJ5T0NreUHIR9aj21DJV8IKmBT5S+a+sEUIZ9MCdpOuJO6KeHqnub0/PwRjEI4inEA+E0gXWBUwQK/WxNCZdiTtwNMQZEU4xVgXWBU8QJexgFq4BTnij8EvZ9UnY7TWl6MeqJpP6UK8peDyFNylq1tDIG1NSxoqT3LaVW+Xupcje0tcpNKUc/NVTTkWNCPwxUq5zndC7K88soN6WbOtCWDHZ2b4v7fWiLe0ADcBNpOgJNlJa43yE91Of9qBmKOXXiKhnW2X2NpreT64RT42LFF8mapy3AmxKRK+96zQRlaw8M/hH0hFJVVmYJKjNLHjhtHhOQWcJystAjYZr4g4WezibBNzZR7aopo+wbxZf1gC/3y0QdY8rR2xlfJl5KqiSFA/SwE/iJafvEehNCEB0XFwYmnKQFCCVJHRCJ0JM5oyh3SVHMny1G9bFcnYzl1ytQIYormtGvoBmIwZzTDFv4mH8y6VGcEbUOjGzdRi0Ua0q3wbD4gXhOI5VX5KNeQT7xLlIknxypPYtU9Egp8rSgMUlvPf5j0HfzMzsAk7kGJpnBKH+4ytf84Tpf84ebG2T9imtLIaorYJKvAKZ0bMcBTLkd97N2tMd2FOy+HeN27Mc8bL9tUn9ALn2FXOKlyBUF4pVESaGkD8jV9yqg71Dk6vsjJceEXGlk6MiVOnKpNFAlUeZSyS1UATO9M8WRpukExhxNXyBdleepHakgXZZ06lgAr7hCEkHSAM+gLoqOcLILqgt6grrBRIauaoV+WKtU9DnsRdHRTnZBdUFPsOfscNJhT3eec3pSdjtN2YsXZec5g7CH9R/FpKyNSnsBhT3kpoi4Yzrs5cYmakJ7ubElVUBjG1YqStD0gYF+MgSNrWovtCS9NHZlpkCfL40tS2fygTY2wUk/ambGScwQ5gBtDdANNeHJrEhUATAXayA7TUfQDH56foH00suDIukQYEaukk4dQ4AZyYqdlQY4gLUfAiuv/wSs+BvIzwGuM5P6Fp+q9WVoekdRWCfPdMby7GRvTA/klCfIKZiZkXNaGUvTyhhFScqP7IQA6TxmKO41OjuAW9thLD8bYGNRP7WxqMznNxYPS1jTelU45Z5cgKc2AJX9/Aagm9el+AP4zF6f2p0T/+AkuJsXnfjDPZzyy+Fid87AJpyGLToD/zWnYYtOg6Rgi87A/89lE1+RoHKNPrV1Jv7BgSM3Ly3xewQ6tMCP5qfsD6iAW1GCHOCxgjzQtqI02YoSeOxZcIoJuaEszUm2lOy6E02ZMT/y+15VdlbBLGuLPTu2qKrKwZzAqupgsAy/tRQq0FLQvR6BR4/EOFdca6Hu9fTz1+UV6vsfpRbqXg9PxACZNNv7XDTKHkzXDR3L0LSfTdcNHbUSA2S6agNa1ZiD6bprYxc0HWbTrWyaGCDLGl6waddGmb4H0/pI37VReAhGiGnXRuAJYSGnXRsxzroozU6mI3U6Ha0X01H4v01HT/0nupCvnY7co+noz/9j/L8cOyBe###4028:XlxV32DM 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c94eNrtmkmS5DgORS+TB9BIiRHW+z5FmpEazGpTvehlWt69iQ/IXT/qRw2xqEW1bwTSX0oAIbnkoZfprXsbfvxrrMf6lvvh/bttfv43jxOB3kDfwLSncifd0UjbgFQiu5HdyUZkM7I52YlUI9XJQWQ1sjo5b2Q9Wx7bGFl6IoORwclApDcS6yFytPXYBmQkYnmOWM9EZDMS65mJVCOxnkRkNRLrWe5ktzx75FmJ2Hp2X0/KRGw9u6+no6PlrpG2AaEK1rORtgGhqlfrweo96Gilq9W2Wm39We95lr3lsQ3I/WjL1vLYBmQkchg5nPREdiOepxxENiObk0KkGqkgOREpRgrIXImsRlYnmchiZHFCK92SkeSEVzobmX09fLTJyOSEa+uN9E4mItbRLTp6v0aXah2t0dGOiHW0ekfLTsQ6WqOjKxHraPWOZlpPtY5W6+h2UtE1G8jeAjoJ1Rpao6Gcxhpao6F8NGtojYbSBVKtoTUaykezhlZraBpGLtoaWnsndOKqNbR2Tuj0FGtoOZ3QBVKsoeVwQg0t1tCyOzmJWEPLBjLRZV2soQW3g+2g9RTraMnYZ+A81tGyOuE81tGyeAWcxzpakhPqaLGOltkJXW5lMDI4ofNTrKMlOspVW0dLdJSug2wdzdHRjYh1NEdH6audraPZOzrRZZ2to9k6mgsVne2bnYs3lE52tobmaCgXYA3N0VAuwBqao6FcgDU0R0Ppu5itoW3z82cd624lrMNb3zY/fh3P9qBau+V4/zae8/G2rO/fpqlvn7VL7ZcF3zWLKeIScY2YI5aIW8Q94hHx9Fi6iH3EIWLkKZGnRJ4SeUrkKTVi5CmRp0SeEnlq5KmRB3cti5GnRp4aeWrkqZGnRp4aeWrkqZGnRp4t8myRZ4s8W+TZIs8WebbIs0W/tsizRZ4t8myRZ4s8u+dpj7WIR0Tn7eHpce8jDhHj3x9rxBpxi3jxON4Z+5+x/+m8/aiJWCNuES/u+7efXxGHiHNE9OE/uS8Ra8Qt4h7xiHh6HLqIfcQh4hhxijhHjDzDEnGN6Oc1D96vPHYRo97R6536OHFtkK7Bcg3Wa5CvQbkG9Rp4X6Zhrtfg8cl+DbxXU5nna5CuwXIN1muQr0G5BvUabNdgvwaPI58xSN016K/BcA3GazBdg6uedNWTrnrSVU+66klXPemqB7+f3687zGZ5uh9+V2mNmd7tXpPehtwe1t/sJ854bHaz6fet/TIbcP8539Jw5OsONFS7c1iZ/+6Ho3u32USzv3J3eu5VafbVOxbVVaiuP303o7q+fG8b7kepVNdfuu8996K6vnwvpLo2qutP3yeprr/trnmvdd0nms00SzRbaLbSLNOs0KzSbKNZ1L4f9Ol5nx0dzXqaDTSjlR20soNWdtDKDlrZ42lCazpoTX/0pDloBSet4DdPIar6pKpPqvqkqk+q+qTzcVLtJ9V+0vk46XzEE3E96Xyc99XkrqNZT7OBZiPNJprNNEs0W2h2PZ0zfVpo9gdP7o5W0NMK6Kn+/JRq76l2eu4/P6Wq+9v5eP0y+Of/Mmh//5Tn2512r7R1vn/Htv3RlAi17jRkW0MLox1oB1oZHUB4LVSGnpMtSLY4G5llsOyv4T4UuYPFy7uF2QHmr6GWldkJ5i+vlkwsdcaS/VWal4lRD9R7mR0fMuGQyQ9ZeT+wFKwwQ58T+vxhdWkEGoF4cWkCmoBmRgPQ4EXyAuaCIouzD73cwDZnfMy5glVnA7MVzF9FLhvXgvOaFlwOM18OFZeDHTKv3MqEShKur+VkhEIS9loORlhbKkA7I1xCKS6hDwzlJy+/o/PW28tCbMEKswrm72a7zKyAFWcrswyW8VbswyFXoBXowxEXoAXowwETUAJaGM1Adm21cP/KtXvr+3fbgHRE7E35gH709SSyGFmcHESSkeRkJzIb8QrqRmQyMjmpREYjo5NCxATDMDjJRMwwDL2TlUhnpHNy7097XpmVOJ0kImYl+sPJTMSsRL87mYiYleg3JyMRsxJ9dTIQKUYK3gtlWs9oKx39dVqm9Yy20tFfp2Vaz2grHf11Wqb1DLbSwVaaZ0rT24nrEwBl6e289bgrzdwa5XgApOMxoh0PiHQ8INLxgEjHAyIdTyOfOB4Q6XhApOMxoh0PiHQ8INLxgEjHAyIdjxHteECk4wGRjseIdjxGtOMBkY4HRDqeRj5xPEa04wGRjgdEOh4Q6XhApOMBkY4HRDoeEOl4QKTjAZGOB0Q6HhDpeECk4zGiHQ+IdDwg0vGASMcDohwPgHQ8INLxgEjHAyIdD4h0PCDS8YBIxwMiHY8R7XhApOMBkY4HRDoeEOl4QKTjAZGOB0Q6HhDpeECk4wGRjgdEOh4Q6XiMaMcDIh0PiHQ8IMrxAEjHAyIdD4h0PCDS8YBIxwNydzz4E/U3jucMx7NPL8fzcjwvx/N6k/N1x4PW/Y7jyS/H83I8L8fzcjwvx/NyPC/H8//peFoXP3M8hj5xPI6k43GkHY8n047H2dPxtL/rBmZPx9PYh/2ejqexidnT8TQ2E9OOx5F2PH7Ip+Nph1x4v6fjaYz7rB2PI+l4HEnH40g7Hi9SOx5n2vE4047H2dPxtMWtXIt0PH45SMfje0nH40g6HkfS8Th6Op5WYmamHY+xzxyPM+14nGnH40w6HkfS8TiSjseRdDyOtONp7BPHAyIdD4h0PCDS8YBIxwMiHQ+IdDwg0vGASMcDIh2PEe14QKTjAZGOB0Q6HhDpeEBujmeh83N3PAudn7vjSXR+7o4n8flRjgcFKMcDoBwPgHI8AA/HM5+Fdnk6nvnkc/N0PPO50bl5Op5GqJtPx9MIdebpeOZzv1dwczyNDEQejqcdbSPycDxpoEfSzfE0MhF5OJ5GZiIPx9MI1fZ0PI0sRB6Op5F7326Op5FM5OF4GilEpOMxoh2PEe14QKTjAZGOp5FPHI8R7XhApOMBkY4HRDoeEOl4QKTjAZGOB0Q6HhDpeECk4wGRjgdEOh4Q6XiMaMcDIh0PiHQ8INLxgCjHAyAdD4h0PCDS8YBIxwMiHQ+IdDwg0vGASMdjRDseEOl4QKTjAZGOB0Q6HhDpeECk4wGRjgdEOh4Q6XhApOMBkY4HRDoeI9rxgEjHAyIdD4hyPADS8YBIxwMiHQ+IdDwg0vGA3B0PbnwfHc/aheOx/2T/cjwvx/NyPK83OV91PPiS/Y7jWf4mx/M/BTxvRg==###3056:XlxV32DM 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c68eNrtmUGSpDgSRS9TBwABAmVa7/sUbSYJMJtNz2KWZXX3wb87lfGzflh317TNYiY2uBQvA3c5BJC8lN5/Kym9f/vXPLbyNrylr79MrUxvJY1GRicbkcHI4GR9JON5kWsDkokcRg4nC5HdyO5kJtKNdCcTkWakOUlEqpF6kZy2/ZFMttIpOelEbKXT6KQRsZVOg5NKPbCVJltpWahtY7YCMgB1bVwMLADcGitstMLKxOu3ukYcgT1T9sG6ORxOqOLBujnsTmiVg3Vz6E6oM4N1c2hODiKbkc3J+UC288pjGyPrSCQZSU4SkdFIrIfIca3HNiATEctzxHpmIt1IrGch0ozEejKRzUis5/HM3XbLs0eejYitZ/f15ELE1rP7egbaW7nOG9uAUAXbdd7YBoSq3qwHm/dgoJVuVttmtY0n/d7W/cpjG5DHva39ymMbkInIYeRwMhLZjXieehDpRrqTSqQZaSAlE6lGKsjSiGxGNieFyGpkdUIr7dlIdsIrXYwsvh7e22xkdsK1jUZGJzMR62iPjj6eo2uzjrbo6EDEOtq8o3UnYh1t0dGNiHW0eUcLradZR5t1tJ9UdCsGireADkKzhrZoKKexhrZoKO/NGtqioXSCNGtoi4by3qyhbcblcOKiraHNL6ETHbhmDW1+CZ3o8FRraD2d0AlSraH1cEINrdbQujs5iVhDaweZ6bSu1tCKy0E/aD3VOloLvpM4j3W0bk44j3W0rl4B57GO1uyEOlqto3VxQqdbTUb8pjTR8anW0Rod5aqtozU6SudBsY6W6GgnYh0t0VH6aRfraPGOznRaF+tosY6WSkUX+2WX6g2lg12soSUaygVYQ0s0lAuwhpZoKBdgDS3RUPotFmvotfn2rU1tM3Rtxmvz9ffpvG5U27BN71+mczmudr1/mefx+uw61f6x4rdmMUdcI24RS8QasUfcIx4RT491iDhGTBEjT408NfLUyFMjT20RI0+NPDXy1MjTIk+LPLhqWYw8LfK0yNMiT4s8LfK0yNMiT4s8LfL0yNMjT488PfL0yNMjT488PfrVI0+PPD3y9MjTI8/uebZtj3hEdH7dPD3uY8QUMf7+2CK2iD3izWN/Z3z/jO+fzq+HmogtYo94c//+9fgVMUVcIqIP/7weNSO2iD3iHvGIeHpMQ8QxYoo4RZwjLhEjT1ojbhH9uJbk/SrTEDHqnbzeeYwDdw3yPVjvwXYPyj2o96DdA+/LnJZ2D75/st8D79Vcl+Ue5Huw3oPtHpR7UO9Buwf9Huz34Puezxjk4R6M9yDdg+kezPfgriff9eS7nnzXk+968l1PvuvB8/P7fYXpthm++lXlasz8btea/JbKdd/7Yo8403E91HyZx71fT2YJ15/zLaej3Feg1OzKYWX+OqZjeLfZTLO/cnX6+Faj2c9esaiuSnX96asZ1fXT17b0uJdGdf2l697Ht6iun74WUl2d6vrT10mq67921Xysddtnmi00yzRbabbRrNCs0qzRrNMsat8P+vR8nB0DzUaaJZrRyg5a2UErO2hlB63s+92E1nTQmv7oTnPQCk5awQ93Iar6pKpPqvqkqk+q+qTjcVLtJ9V+0vE46XjEHXE76Xicj6spw0CzkWaJZhPNZpotNMs0W2l2350LfVpp9gd37oFWMNIK6K7+8SnVPlLtdN//+JSqHh+Ox+vJ4H//yeD6/6d+vN25HhJsne+/YXv905QJXd25kG0NrYx2oB1oY3QA4bVQTSMnW5FsdTYxK2DFX8N9KnIHi5d3K7MDzF9DrRuzE8xfXq2FWB6MZfuvtKwzoxFo9DIH3mXGLrPvsvH3wHKwygx9zujzp9XlCWgC4sXlGWgGWhgloORF8gKWiiKrs0+97GDdGe9zaWDNWWK2gfmryLVzLTiuecXpsPDp0HA62C7Lxq3MqCTj/FpPRigk41vrwQhryxVoZ4RTKMcp9Imh/OzlD3TcRntZiC1YZdbA/N3sUJhVsOpsY1bACt6KfdrlBrQBfdrjCrQCfdphBspAK6MFaIFd6I8/uevaam/9i5OBiL0pT5sbiZPIamR1chAxVZCyk52IuYLkFbROZDYyO2lEJiOTk0pEOh4Q6XhApOMxoh0PiHQ8INLxgEjHAyIdD8ij46H1kOOh9ZDjofWQ46H1SMeDApTjAVCOB0A5HgDpeIxoxwMiHQ+IdDwg0vGASMdzkSeOB0Q6HhDpeIxoxwMiHQ+IdDwg0vGASMdjRDseEOl4QKTjMaIdjxHteECk4wGRjuciTxyPEe14QKTjAZGOB0Q6HhDpeECk4wGRjgdEOh4Q6XhApOMBkY4HRDoeEOl4jGjHAyIdD4h0PCDS8YAoxwMgHQ+IdDwg0vGASMcDIh0PiHQ8INLxgEjHY0Q7HhDpeECk4wGRjgdEOh4Q6XhApOMBkY4HRDoeEOl4QKTjAZGOB0Q6HiPa8YBIxwMiHQ+IcjwA0vGASMcDIh0PiHQ8INLxgDw6Htx+fnA8czie9nI8L8fzcjyvNzn/gePBFea547kuLC/H83I8L8fzcjwvx/NyPC/H83/peK6HhGeOx9ATx+NIOh5H2vF4Mu14nGnH40w7Hmfa8TjTjgdMOx5H2vH4LrXj8e9px+NMOh5H0vE4ko7HkXY8XqR2PM6043GmHY8z7Xi8Ful4/HSQjse/JR2PI+l4HEnH40g7Hmfa8Rh75nicacfjTDseZ9LxOJKOx5F0PI6k43GkHc/FnjgeEOl4QKTjAZGOB0Q6HhDpeECk4wGRjgdEOh4Q6XiMaMcDIh0PiHQ8INLxgEjHA/LoeCgPOR7KQ46H8pDjoTzS8aAA5XgAlOMBUI4HQDoeI9rxgEjHAyIdD4h0PCDS8VzkieMBkY4HRDoeI9rxgEjHAyIdD4h0PCDS8RjRjgdEOh4Q6XiMaMdjRDseEOl4QKTjucgTx2NEOx4Q6XhApOMBkY4HRDoeEOl4QKTjAZGOB0Q6HhDpeECk4wGRjgdEOh4j2vGASMcDIh0PiHQ8IMrxAEjHAyIdD4h0PCDS8YBIxwMiHQ+IdDwg0vEY0Y4HRDoeEOl4QKTjAZGOB0Q6HhDpeECk4wGRjgdEOh4Q6XhApOMBkY7HiHY8INLxgEjHA6IcD4B0PCDS8YBIxwMiHQ+IdDwgj44H/9z94HiWcDxlezmel+N5OZ6/903OvwFXHTTJ###2984:XlxV32DM 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s8gcH8/iF8bHsvhF8XEsfkF8DItfDB+/4hfCx674RfBxK27eSwi/zIqjcIxfXsUx+Hv8siryA/TmVORX1s2oyE+J/wWm7dlF###4308:XlxV32DM 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1208eNqtm0uS3KoShjdzFsD7URVnK45AAiI8uWfgocN7v7yUZIqSurrdkzalX0KQksiPH/xgv/+RWaeH4tk8/yezMQ8eXX7Wo/lhVFbPf1QRH07K508rw4M9imbcQwkhnuWQ0viQrIc0w4d0O8TxIdMOCXxItUMSH+LP538y7bkce/7ZhAuxlOrdUKPdaLSP7mizSAzarJ8/nd1rBT+d2/q/W73v8z/Fd9kOKKFDv4U2IZWSxbcQTEBcSodfxMWf4yL5Gpe0xmWHuBzBWCIQzxFI5wgIJiECfkbAQOvCZyLwSwThS0n8/ldvOT1Kv54/6p+iWKewonRRyp96jY5Y0awo5c+fXzrQazSvCm+KyUQRVRFd0USRVZFVqb+nUuNSJG5rE1wIXWql2rEilVfizy+1ZY6k0veq+HqRtGLU55kbfY17UxzHSutran31ilzT+lqiXRTDNVFqX1NrnLWZKLUFybXasiNKbXWqbWu/pzL6GkPv6w4d2o++ZtH7KpDU+uqEbD3ydtRnykNvfXXKdiVhpfbVtSdRnitRal+djq1HjBGl9NUZ1xtHr6ktsPWJi00ZosiqtCdu2mt4KL2vrr1a5QWqodPHw7P7c3RtlCKUUiv9qH9aMyIEIo4YOZ9qjCKTuEq3HVWOUoRSaqUfzu09thJV2WMbWI/g8c3U8aPHdutRDxwrLbab6u+RxEqL7Va7rPbsUfvqpzkaCMU4i6kXf7S/rd8ZGplGv70Ivf0aSa39XsT+5hrSlvo0N9O/eUaU2ufN9jeX9Lk9zc21pznfgHB8pfVuf8oAtvUvzjxc+fO7jlv54Y22zz6a6RK1MW5t7Plf+bb7oIiHUl5G99NQypM8pxge8znF8JjOKYanmmLKONFvE30bFstnNn7v+NQ2XCfSEtcOGXzItkOj3clhqSW95PGhUG+f+9BfPtR2e9d6W34ri07NNdc60p+U26HYzzb4XrkGpHx3+JBuh3AFmT1xctj77dtwUH4H1n9vo3mbHP+q8S8ORa6xLS8NPtSat6FOCMbbIdLSmuLKG9rqLO8jyUeb3mK9myE5P6mR8YRKkPT1no5Xp7zUp+zL1uzL2UIlLC5UwvaFSlimOXkzS07mJVX0FtoCVUdOjvBuFxj4FJVsUZyphKc4g2CBSvYIeZ+dqYRvC5Vwt8bFLlQCklmCwcM5GHkNRoJg2BmMAA3lnwxGVkswAF2FyhNdt3CDrmpFNA7BWHhVr7y6BqPiMAlG+/4ueNXm7+DVzjYXvFqCEV+9GcCrRwQWMs3LtyHZEoFOuTQC6RwBcc2rNn8Hr5p4ZKg6VGAqtcJhBVMpkEhXEJXKjSiTSvs3OBVEpVEhhVBpHxtqyq2lCyqtEqZSz2e7BaHSTSmsICqdhNmUSaWYs5sCVKqDCEQBKtXBUmVS6RYlUgiVbseNWumCSquEqTS4OXNQhEoB4LoyqXQgISiTSku7DVGASjWw21CASjU8h6FMKu0DzaGcqNQMRGsPrxFo61ovle/+KAlCpX1EaIEopQsqbVU2Am1V9lKtcpTEBZW2cxCV+jDbzwmVhuSwgqjUao2VSaXlbbFEAUYs3wwnCjBiUch9ECPCG9EUxIi/DkT83bt6QbAtCpNgETO3D63TcXsPR7GG+ygKwsxlmDK8sayuVKonlTqgUvWSSnFCGXBJQHUgKDvx5glUB7sSUI0rqLI7UE1jFKco6gFFTwg6akmjliv+JG3qRNlgkxIl5U6+cGen1L/lzhNUvoug8YygPG+AoHfc6ZldkevgTl7eLEisCOvimTI6PlIUjQtysTXd8jXdsm1F0VO6NVxdo6iT34GiJtiVxyMYZHwHHi+Bxij6EjS4X3s+rcGju6c+6mvCdPI7CNOztPRxmqOb0cc9jPeEMClO6tXxM6sTKley5B+SpWlD0AVZOvkdZLk3h+eKLDVzt2RJsfFdyBwmqVhN0hevgb8my9qQvyZLxEc1Ftj7GPmiZJtawilqhO24CCc2HTStD7Ihymu1PuzMYB/SEjdWGo8VxL3Y1bSYexERdwW4d8LbUIB7RdgSUSb39iHyUAj39oGod0hdcW+ViBs7fchgCd0i7zJY4rlulhEF6BYRQWtCz/118ICinUV/dtGSINVOw9YKT5SJxn1kPBSCxuAM9wa8RuMqEcPW7BDeRGxZ6TRWkC0rrSUKsmUVVaYta3wiygTgPg4eCgVgm1B0O+y2DoyShZInANwHrt5dewXArcoGu63KUbJQ8hcA3M7BAKw0/uAQAE8ruikIgF0iCgZgMMO7cgBwGYzGyoit/GgnP3rgR/01foxXhsTBkWLlyPehkbqbfnU3w+pumhUp7XMxOvfV6HTvG538+Q57ipU92Tue58DRL7FnBPY80STB0P2MoYftaVdYdSe0vXNCU7gmUqHyKxPwPSLdLn0vtpjoB5neYai18RpD/bdgqBfs2hHlm1SAoTbdOKJ+dUTD6oiu1DZMUrG4q9Qcdee43Jij/lvQ1WV7bY4WdGXvrevL5zs0q1aAE2/5pKd1fetufFL/LTTr+X6zrr9J9ta6vkhrXPY1LnF1T/kal7zEpcIyjYu6We3/DsZFybM+BLKmOVGixI6saTqikDVNhZWZPEtqdkTBK4ySKHiFMRBlukf9aR4KcY9gk0IrXbhHVXrtHtWha1Bh/VqPouOzqE6saJ1AIbxAmlpvx5da7Sg5DiWFkabQlcDXNZJq1/WS41BShK58Pp5MHQcwyjmiYJQrD42TiyZNAsUPZdJkH+GnMmkSjOgev9eo2/qCUdeSG+G9CY4oCIJdAggWjOy2MJYqE94d34iCdlsIhhQC72iiJRjdJDInWoLRCcuctglG7XigyJrPyTJCCkgh0ylrE0QuXk2n2quCplOA2v1OeGEEWtfbgBZG5mJBU9DCiKXtnhNElxRWYIraRt36mpSg6wePk4sDcLH5mIsTv+Pi09L+i1XLV1xcjdmTefoCehfS3VfStSvpVqb4kGjR0v0d0b69il8I1mKCPZNrWsk1vkGuB9+OurtrWulL3pmjYgP6UuEGRfMdip5W4F+uR79AUbphbryB5pIT534+YVe78gUULiS4rSRoVxL0NLOLXd5gGvdxBlB/DtP4W5j2peVssYsbhuJ+n5Z4umGo/NbeyJWhBmldGsNir2cr2jw9mzft6L1cz/qEz7I86on9HS+Dgxv+n/WDWVrPsRXgObhl5f06ZQuFJJRiimKgOrIBr3xOAitoQdMLjhW0CNo/wXnNXOrsr/xUkJ8jHFEga8ukPFJah/5tAS3xIUuJPRQYBs1sR6WfkpWAIA2J3+TE0sREIgtkNx7iUV19KhWmbG8jro60MfVKA6l0LlBCch/KRExpOHlacwkcI2Yky+Z+QkRTphkpTcDK5IHSAngrhKS53XOPJAQEwu+JKMiThfXbrkwfF8OKJN4vRhJ55RcLSRK46pYsl2UE5Wi73jYSuHEbSuDHKI0cp4/2z/nVYQpvOUxuzbsGO0wfbZ175SixJf8Or4ivC5zjNhc2Epg2KjTTTV6YNvX7H2OmnSzUMuUI5TG+HQNefSabuHZX+FyX+bq7omION+5K5rAApvX2uf1mfnVXwlvuiltzqiHpqcRFXrsrnH2Du1Li4m/SduZqugjpc1vPXrgrYs2AL1wE+XJ5rARDXVsqnJm/tlR+lVd7zC/a69LH4/YQ+ky8jB0jD7WDZCYofYBLPU6FSgSGlZnwyjUGKzNJKhkkUSAVFsUTBRJe+U1rgyRZuoUV6JaCbjUIVq1bfXPP6PUokRl5aQGDIKizOaBwRdUI6BWNErEEjNgNOrubET2wR/HkSyjYlN6eD14ag4W2oUDWK78VUYBeyjVEmbNgJXzGysx6pfO0NsiUpbbjkdUBEiWw8tshBcIv5lvlIKACT4XrS9/uV95l/xB8ZqsdstX+telm/sx0E+3dgUx4teYSnpd7d8z1NvKZ+2rC46/28HxtAiohAS5Zj32c9dCiiV0nlect3yhHxvZ/YE5zNDFHVQmDVYY5mtiX2WRYZ5Pr7mZ2vbuZjXySYLAXN5PczDnsAknpc5Pc+JlJLtr2cxrh7R0G6Jnu1NcxgK232GYEwDSXEr6sMr07Y4C+3ALC5244GvqU7viDweYrWzL4NX+E6xuba1PBXcXb3OGF/Ba8sLd4AWZFSdt/7QroywgM8ngRAX3HFOrvl2lG/pEXFsM+jSUTNbEYaAfiBxvTa6LjkJqa35sqnPCetfQhpUSyY890clxUE9Zxzjm3znMYnIOzn8fnlIw5zsG5s2VIOEeG4xyUeeU24cJSWzjmyUSCTDjHcNsl17veKxgZtn/1cui1/70SNAEtMUrkHA7nzEzes/E8h8E5MCkdHzqc0yORBZ6elnoCPqdHIgu8GYrQkZ1IZGZRn+goZnjKc3P3QXgcSXifljz2pA8FjAQCcxYQzkBJky0rMhh4cJpSIcZLC1BpoKQJXsY8GdxOWtLzWSqkY8yFLVVDmWgsgyMKwmm/EWUiOMZ2S7E9cKwg1I/HclDv31wOKtdsSCEzh5gy+jix87bLjrvNPTneNNmEMIRCssfHKNu+nf7/lnk5UP5MYIwAjPElML7ckRPTuiOH/dX/N/waHb639+YYlf8PESCW+w==###4444:XlxV32DM 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1174eNqtm0ty5KoShjdzFsAb4YqzlY4ACSJ6cnvQw47e+00egkwhyXIdD2xj/QIyEwRfJaoP9vGPTGb5UDym1+vnorcP9gF/4dKQEsuS5fiSKJdEvduu9e9S/v5aXKz/e1b/D+2+oEYTgvHcRNC41bVcMvjSVi5ZfCmWS8TC8Hr9csKXbpyoTiihy4Wg1yU3mX/YH6iiY/ZXvf4Htc2H0GZ55avpw+g1vv5R0N7HIrbXT6s0Njj3azXDl9ZyieNLW7kk0CXOyiWJ74Jo/5JxTdnAv0FYnUOmqYW6Weh43A0Um+wGRhz50CJcIv1L8VWSGPzNQVBzELYRBHsSBMmOQeBhCgL3UxD4MgfBTkHg7hiENAch9iCkEQTfDeRfDUK23JIukhlBUHsfKow+JBguPTJc6NcxLoL3uByDIcQUDKF6MGgEDJsikJY9AoL1CETWrdNfjICNx2kgmBgRkGfTwB3dlXyaBmKbpoGIs+dpmgZiPUwDw49BEEz2IPARBNMN9F8Jwm/hU9bEn3/L0gCuvX7kX6AEu2FFM1Dg19/f2pdFZCg8K7wokhNFZEVkpT5zQ5FZkVXBrWXvQYJnBEyoawFIpZTNB2lbQFIhrUgCD7PicqUlpt6eah7F4pHTHCvFI4hctrvEYyjZo2irEomS+4lLtVsSJdsWXVU0UppH8KQWj1I3O+0eJVE92pBUPFqELCPh194ePLIwxD8WVQMkFVayr0uNt1cGK9lX2NKqR6RO9hU2uWK39UTJFlhelUgUmZU2rgwp1delTCCo1AcCqjcpiGK34buvUKphgE0rh2FlDEklDLCNFcNFXq30PuR2fbVQ1RIsGHuJl9KP/Cu3mByql+d+q7gXoWYv8lr8UX4XS4c5rFkKu3pud2MS27OE3Z5ayva0Ei+lH0AFdaAjarIOtGflYWQKRawOZ1Bl6o7JlpUynKFE2RdAGUoezlAn9cKJkvsJto7MRpTsU4ApAEuO0TnIQnws8OtPXmnShzOLe9X1B7bJttAE9voFj2ld5fGKyLftuCLyLfYV8bAM8iiPyyDfMhLAc17v3lxZvOABqv9HDEWx7KURQ1EsJBIxFMFjmS85fMnnPlLDMVH3n6X4keGvXS8QSLmQ8qCceZD/Vx4sDHfkwTjz4Drz4NZ58BYCzS0EavkMAsMdBD4hv43udqZUuCC/RX8L+Rk1dzHIDx6R1ofhlPwo5tkZ88KMeW7GPH/0WF1j3qK/BfOMn8YaYZ7WZ5Aj97GeyIbPZKNnspHnTGe0uWa6xXwL05XH85LptHrEdGKdmS7Nns+fbxrmnXhur0FuMd8BcvXpKWs6DDlCAQQWeb5hsDA7CpQSphFopDOMoQyjvZVIwuDji51D6bAk3KaJ0gFLBE7rdChDiJd9w4hntEQK5kJoxPbmKE22h3+XMIJ6k4gysNUvtE5HXeGNI0rHY2GXFSsDqRHb5AmB2AYxSvGo0kgZlL1oRtEeGMUNPoRZSOBALkRBcKAkURAcGEOUHQ6y4pBCgK5hQ/MMA52wYcPtDagBoEvI6QpvZYq2kukli4GurSO1M3PFZKXJwl+lyVYyvWQvmKzcg5jM+AU/VxiklSfKAGkvIlEQSBvaGgJpg1tDIA3LR6jPqcxQJgeU+R3K4imUPSWwxmvPCWxbZ7bSM4F9xmlL57QJzswtnG1T+u0qSfcOick5M6ea1AwoGDaxV5hzcek2F+eCnXf/HcO4Tx14DDx+GMOeMlcjtDvmCipdM5fdvoO5XAmbPWcucHPriaakCHORRFOlqU8TcPYuATfhmDkEQ/NrHLPbd+CYcycIZHow8vY/jXnBMQoj6nWTWjslkHAC1529bPwO9nJOHgd6sBf4ps4G2h0HuubTCH1eze+GaXhIYeIc3FbX4GXjd4CXNDvA5MHF24BzmihjG6ihGkrfBtoczBtRLl0kiLKEOU4a2lHfo9qwFwUeQ8xqLhikkCSVNxup1JFMWOaJMjBuCYEoHf0QxuXFBmOctMS4nNeCvaUoPXVRlJHDa4tmVSzNFgbNUEeYCiFADtXCGUsXFFEG+tV1aygdF6E1WqejH8K4YkIFtjKQe1GMojpgXF2L6yhKAl7OKaQQ8Aod4UNH+CmTFnbur7QJg+VITx3+ED+VwSqsVGZbK4leUhf8FHZWb/wkrcZ9leRlqGFciIKyXYOtq30daGECLkQZQFtX1v0ZIIlIX7bg7lRhyuJUK4leUoQzQ/+YEfrHjMKZf4OSa3aYxw/3IdhAsrAjWfquPNlYzRuPfYHDlpnD/MxhZs6X2Z4vyxzG21/CYz8XZVGyjGbEKKKxjmjvJMsQmtk5/bVQqFJbDPMe3jehBLTUVnzJ+ooP+8gxt2Xm3JadhybvNLHuNNDxTVINOvZ9Z0/6vybVznZ4JSO7RrmE4EW9SXLg4sm5aRguuh5bGXofaSI5NZOcnElOzyTH5xybeB0GQdywZmL9eNsCZnyJNZdHh73m7rCXjtZ2c8I7mPh91IRY+OsDXohF6BNSxPmAd0qJ6TklJi4/eVxkAMHreE2h4wPP+xAKXmeP5QWErqI//2bTBEKp/duZ/b+NWPPsV3/+LU9b3cnLUPZipJs62NM2rGIZ3rrhZocktN+DYoiC92eFDCh7cel/L0WyK8u1EUU1DCdKZOS4obz/1YZaKZIjNL/xblBLTrSbqis16ruOeBZMYETpDAzVOVE6N0MdTZSOs6AErKAkp/ASK+OMVHkUBHKuCv8rpBDW3uJoThA6hgvDupIZjblWdaksRLJJ2dlaH+Ow8ILcw/s9HaahnYXcw/o9Izsqy9zv90Ao2j0DlpUMK75H+v2egdrgut+DEBk9Y/fbGDuaS23bbJVCDUKbSfuEGF6GHgmSW4WeLbmH93s6nrctZ9zD+j0DuuUm8T0tEiTzuso6BwrB7y3kObAq1gTgpz3IsiTdUgFKvsKGhwlvbYQHH2EG4dENpJ1pEtiL/CuHoluaU3JbSclZnJI7IqB/NxV3goDLfGSat8UL6uOvJ4k5PZ+Wsg6AmCCB/SxOz9G03H7O+caZaXrdcSQMegozQHSKU56NHIYkFEcBgk0AwdJXTkvZNmfuAs1spORvUEe5dGLpCer4d9NqJ6izfPpeW/LbDZMoZc6MvmaSGRvPMmOzpY1c5IFvqKXrTTJLKX1m6ZTMqueBb5wtSvZ6xiR5IuSHVFFLx5R1A+4C1Gc17W1Zau20FQUWmGVvsCx8hwb1cH0k79YnDf5uDebP0al8NN9sxpCSs6nGFwlKVYJFLkur3FMKeSwqc5QGoEvQpRMc6QifpNvTYU3p+CTdYonS0wfS7edhTekpB8k06WekKSRTDisjtQGKRB7nUPR8yL4V/VseBuJWKoZIgXSEUtL1VE9VOkpJ5x1ROkpJZw1ROkqBiQtWBkqBErGCXjfrL4iV1We3HQauDwlDOso2wpAoonQegiExROkUBEMiiNLZByzcsDKIBxSNlcE5oAg00+qQ1DwkSKFLoVWSvioKKwMoILAaKwNHYDAWonSYgQGUROkoBIPOiTJyjavFtpGQp4wpknt7hinbjin+BlOmbWoHjwtMOWSujumpr7KJe735OpeZ2WTpbELRgr5rNr/ZP50UPkePiTfCI96IiDek0Osdb6hnvMHmbYZtj17RD7enRmBeuIMM+T5kuNebb1WZGTIWsnXDE+FuIEPGdAsZlBE+e7P9Nnq8rARXDCFj/CpDTOCwPgKH9LoYXH8HDvKr4NCWoitwkOPd0Yfg0BqExa+UMDg047OUSxQc9rdoywDUJbM00HepFekEHCwjCgIHJ4iCwSESZYCDCKQOAgfhPVYQOAivkMcUHJjukqNuNXDYkE7BIREFgUNQREHgsJ/ANWWAg9hhoyoIHIQn/WBwkGO09l2sDFwfkgXpFBxWomBwiETB4OCJMsBBeFIHgYPwBisIHHpmqRhMwEH4YdxKwEF4jRUCDhtWMDgERhQMDoEoGBwcURA4SFyHhDzV/EZJfUzgEHdwCNfgUCnhs/xGxQsCDu1l78/ePopvpTpOTrvcI5ywr7MXkI44oV9XL4bXMy+S6qikcXXWhXMkn/HG+nrydcFnqY7t9OuCsBOUtfiKQmQ0zyhke5T1iPM2P+9ZZ68u0S9HgdHbDZvIqN9mk5OzHveITU6+2Hd4xSgpcZsAWZ+xiblGgvncTPC7N7Rx5oRaym8TIOEZvMxz4uwLc88SIPGzL8xJnuwN0siovpwLKYvkdS7EfzkXovpHZMUo0lTjy/aZ7AFpxodXGJb9UyA00PdPiXSaC7FEwbkQRxSMNJooKBeiElZILoT0Q3IhAnlMkWakSZSgbjWkUUinSGOIgnMhgSg4F7IQBedCSD8kF0JaQ0jT33gpC9GOYwlRpkM6RZqNKBhpElEw0gSinCIN266Qhm0XSJMNvkIamM0XSMPiAWkiVgjScKJgpCH9EKTxRBlIE1JCCgn5ngvhZ0iTdqRZL5Hm/xJulpI=###4656:XlxV32DM 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1218eNqtm0uS5CgMhi8zB+BtnBl9lYowtomYzfSilx199xEvIRnbmdVVi+6i/NsgBEafBSV3+Xz+Oxn7EI9/dHT+YeQu0iUr4FL6KYm07VlS9NKWL+l0989pm8pT21x/rrTiOd26s7bWfMnRS0u+NNFLLl/y9JLPl2Z6aYJL3tAHo06Xsr3p51Z+OlZRTLdMtJfR5ku0l1E9nz/9XHrnl+IbHzS9JXXFB0Mv5bqDrXeTXiohs8SM3fMlalwMz2dQ0abb0j/xGxS7J7PN8z+4yT2ksfaZrsaHM9Dffww89vBqA/fohbYYjyOtxH410kqsx5FWIpCR1vsaU+FPMs+N5m3dPHNinhZH8+Q8mCcDmoeX8uRglko3WCo9WoqXYHIQo7Vc9GB0dM1ouPHMaH00Wlk0+sqRSg7mKTeYp8zRPHU0TwnVzQtn5s2DedvgU335cit9YmkcLV2fh9FP1RtuKZmc3bwAVYm9NCxinUV1wYB1xGPX5Vih7V1fsML1nQp/1QrV7x+5lO54fsCrDFI1HqRcKhKsYUlahcKn1CN1+FkqgCZTrbMKRAcfQaXBZ8VFpqikTFmZJVNkUlxWzMYUkRSbFBUEVYxNisnK4qmil6ToomjS4+QKkBZRutUlzbsVsyF6JXrp1qSyYnempG5NMitBMyV1yxVXeMGU1C27FRMtVXK3rCoKsyB3y5QhMR5Hy1Xb88DhkDiiZ9shQpQhWZiiklItXJkik1IGi7WWbYdAlRTRBqsoyXaIakWxVEm2QwgsiiIzrQwJRMkiBZSm+hD8lxVDldyQyQ3NE3smG2dFVpadKalDtgyTnZmSnFBcPuuJKclxVheX02eYy2G6/AlGi9RjuT/mhxK/00saH7ObxbO8utG0tzUIwANZ8YDzhhyWpAEydgYZvv5cCGQMZDGPZDGNZOGRLBpOQMVR1p8VHJQuP6/YglJCxQy8lNZbThxRDsRRIaQ2N5X++Dw1E3bs5WeoOqeG9ZQa/jXKZvcEs+eVyvL4jLEkwhpfYwmMJeLDOrDC8mqUlKgxdi8rOTScKnAX3BIhOtWGHUReyi284fi64fWUTIyWbuw5hhKJ7asNp6na6QCE6vDs+J9GrmUiNN/mPuqxj6H3ETlCQ/xrbcQWqAfiMSPxqJF4NAbqg7/lDYhFhdAwQagfQGywZR5tmUZbfLflfAjsOAQ7DkHoQ9DjuvzsECw3KBdhRNs0S8U3UI5C2cEDahwNpUdsklfz0QzOiB6dgXNFwSdYM9R+1hnJEfoCHFc1oTM2y8CRd2B7wX2/YOFPTerfP/L6ksLSj/zCkyhVJyTeAwGq3tPjlVNrenkM3JPe1tST5488a7BoSvEj/w+1LnsN5nnkS0zKt4FfimUVA8qz4KTEe4kQzCYMaQz8WdtqJZNLH7DylopWbGiiIAe/e6JkEz5q62UAmnUEoIyKM1MQoOB3hYqs1UF0KzYE7IytnYG4VJ6yRErNf0Ckyi3NgrbUEQqq01Tp2AXW7cw6RDV4hvcI8Q6UnY2vxPFF6qgLZL9H4T3IHzVCqXpPWtGedYSaTx3qtvlHlg5JgU5wzT+bLz0y2HIByeJfgmVwT6D31FksKdRBLwW9p85iSZHQKB/ZPRLvQaCsqNTvUXgP4ij8brCnungChluWnk507k5rm7u1ZHLpI/2XG4ts7uLnyWrKN0gmvDYUOguqCoBOzTKdIU9l4pDzwz9k6JAnG+TZU8ijy6vc4vClfMgg0cB+A3t7rSKTXcO5TzAcpzM10pke80FizAcVhjsFNYpexo100NFLI4FoZRh68cyNv/KdEm70HUMCI29SR1Fj/HW7u0kdbdcGhJvBI6GvLPNXKKbm70AxvY9NdBSDt74520SGYqf5m3N36jCOZycsPXfCCoyw7ps4d9gdOPU4/hVwMmMTBJw08ohLHSPgxJHIjEhkRyRSI1Ho56HHd3Sk/Jfp6FddyPISbFxb7o1k0KJCoPeUsGEk/TCHebC11VUHHrBVaFIaQRawl2iIRAP2rnG1NpYFXxU8U3rw3Q0GeZj4LFQo71sXQKrRSAcWjdSys3sE3kOi2irQ4GNwXVgTxZM6sMCp8kj0JhQ2QQKe3qm3ixlGUkSEevg9Eu8hmKHZqJW2jGSYsUQEGeMaZqSeVcxYokVdcszYjWLDQNhNr0zpvLdER5TKqWmS1+bU2gJ6tiGH8TwxaokHdBUWHItLqs0VZZbNFdUSo1oC3HlQC2XnudqKB+BejWbEYCQSg2HEkIe2EkNOw0rAxYfcOjGoRgzuU8RwIAUxJo9eJY0aJ3Qe4LkcO+wT8dTMVQLnbJ/okgsO+0Vx3C/acL/okN55tXUUxiQQ9P7nrBZOJNb7OyAIS99Y2PRbQHAAATFmbj6TsVmiPn6+9gCrvMGQNAXHAmxpBatqdaepmD8XLwOp+45Aqm8zEBpDl7XhJgPhLilLybu0w4vNJPBAuAus9jvSDnq+2a+Keur7Vfv1flXZnOI5mH3MwWzPd7au1hE44tEv69EvSmj0i+l+6XNt+RRwKO3rjk9+8QhCKO1mqnQAUXpSVOmBUE0yMgXDnwpuYgoGPbUEyxTM7deloCks3Km1fZCnF5JiwxIVUVpQg1esBbVNtjAFFxn+qBUjpeZZCeUDVWhWYtuoQsFoU0zpYFRiT1dorDZMobFaEgW7FbBbUbSgmfpaInSSa2nlsXpz6IRwGatTRSVCp4pqaWUZKLVhugZeMLLFBy7bqNK3BeGZlSp9kxEGYGcKbjLC744pmC0AiyRTeg5siYIo6LK1z4QZnbBWJ0A8OiBImiSVO5KrWnFlCPInqMnkXk0PD/91oNANKKbXQLHru6MuJ0Dx3qkXyistXdEOwBz2qA4bUa+2q9Z3tqvoGZljtuOnr9HkQDti3LnSzzdyI2dnZeTrnat2YIbsYOnx3Iup0slpmcY300hB/kBUiDyz2gb0mW7RB9nCTvs1+khxd4zmBH3eO1FDyYoer5jyYYKLvMks9k4v+i/zJtblT6erbaPNk+NF5ub8zvR8ZwcpvLODRI/2MGdM4hrlZhG/jnLWO3eDcmHTOEnMcoNyagQZ+3wnc3ICMvr82NVklmuqm6X4OtWBM/QN1YXt7I05OYUUXx+SGt8NLYd3I+Eh98ANv81Sfge/EUpjZzNM2NvJiDQQJZmTj9hAiE/V2KTAy5sDe565tWQWLLFgb5e8c4TPJbIoz5WSWbDEaKNOhGYJpQ01a93Md44Cj5r3mSkISfUNaErd26pk6i19qHMaMCtTyKEd7XbWEBKcCkIwBQmurkhJcYf0GkFgV9MN9YxPXRyyG6DEyDPsnkgk8abmeWHVYe5L6XmiSk9rKS+4CQjHwGSOKT3NFfZ2NCmPbbKgnP6BdiR9pu9N1aW/PUOzbzWUtWlJ0R2s2+mMJWd5nAtM6d8IfrNM6d8V9PuFnTNiXynsbFJDtd9lplLwAzcEImU3QJzOAyEMTgZNqVU5dFBRkECV1zNTkFrrwtUUuj8L8zHShzpSQ49YdR2pwQu8oQ7Oa97Tbe9swdcy/2rRLL04QK1z2VMuQa3rUGsa1PpPQe3LQ1QjsybYfZdZ1+dx9+1wPHsaD3G/OrE9f4lZ7fNzybpDkm7k37fx1Yxsakc2dWNq79V573uCddLfEOwaMZdlpHmLYF8erDoBVJ5Eqa/nBaB69y2AKu8OmK8RAdXqeAOo4TK9Jt1Ipctbp8rnozP0NaB69x2AGvKpjwtAVcb1BG74JKC65+fSjgeM1QfYZX5xNxlIP30Hq4bxIF5nVfAL7v7albMqd8I6OEGfOGF/56T8EVfLan+Bqwm+voyrJByl17IGnjQpW9GFXlwP56p6cE4aDc41TlWFRnS7tFPheQBo3J6FZQoGTajEUYXkrjpUJ0sJVAMc83aQAuB3xZROAaEdpskKpYC6kmbqghIFqLraNIkCFEHCrBCAQhIpSgeoyWimEIDq4JcUmgCed6rQpHHHVcnOsRN+KkqHUje3k+d5ThCMhOoifYici+q8mh7ivKrpM4SLkS/LNGPfIWFl1iFm26Uc2mgN5Q+cNGFryQUssY8eqGciNbJPBEccy/4MgHxxpFWUZqD7F0JunHwhuNbf8h6RzwqwXdLqyAfMoj1T+kfP3I4HFKV/QtWFvSn0u6uubb06/IyD37kJPdfdv0KzY/MXZ+5bKbmAJfoVCsvUsicnweozwX8dSm2D0vn6RP+QSxVDLnWXr/6C8C0YXcYEqn8rgXryl4TTl7hU/uVfAZBc6vsJ1Gs0DPmAwsVZe2W8PAl//az9kL7cx/RlfPsPAstrdoGEk/8OJAz58MsFEkJ3kSgMifYjEi5jztK/lbM8+ZvD6SUdBiGv6XDy30GHTt2lLzetcBqI7YYO9d+ehZe3fw2gli1ec+A0fwMH1uXrgrKm+XspK830ylNpcGsx9bIVd3FJWUmjlFUsb8ohb9K4KNV9nmxMtpQlPZlSSvnuUtoFTTbWkWg10mBdwxpWmcNvrjKXcpWltAsekhWCkzokDkM7kJ4lmod0s2EKBjCIlDtTMLoC60xM6dGVMJU6JChnVttp6M+dJKG/vK9NYaE/GIy7sBJR/KhE0ySCH3bxhilIb/BMYAqhtyiY0hOUCCZFISC2ePbMKdbloQ3/AxuQc6c=###4444:XlxV32DM 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11dceNq1W0uS7KgO3UwvgJ/5ZEZv5UaADRE96RrcYUft/fFHAtuVVTffJIvysUHIQjoS+EEe7L+/WRD+obh9/tJCPT9/s53IR0Y4tf7B/R6eqXk8FPER54YdAFcbf/5S3mREUYSwhOiMGI4QmhCVEREQQhIiE8Li/wARW0K2gkAJs+zq2Asyxjkegh46QaZAe4dCfSj+ZGSDSB5I5IGMZhDJwsWfhDj0TJ5Q/EmIJAhJSog/CeEeIUlx8SerXAEEqTw8Pz8dpy7NmO4P+WDkv395kOFhpJXPv3jY/CPw519C0PDQjjz/idOKN0dE6qSC8IyXxAYueZoubQReIvkShQ8e+RKDd/F8icO7/PP5oY4kf4QOU//u8CmbnvJIAp0vSXhpz5dqR15DSGbIwEsqXooGCy6FJJxG8gaaLx3w0pYuSZ2H0QpOOCQdaIUmHJX3oU0RSltS/jqogJDUpJ2Al0K+BCccXL4EJsxIFs6hKfh8Cc49RLU4zvLLSreS/8orj7KJZzIE+aA8Lr90NTykGKbAjskUGDlmU2AkzKbAiJ9NgRE3mwKjZDYFRqKoH8l4k5ai0bK8tCehjyG0PhGaz/bLqF2EpnoRmrou9CKpXCSlCktKs8qxpEF2SaPNnEjKZ0nZtkjK+CIpk5eSMrZIyugsqZolZYQNScWZpGaR1C+ScrJKui+GwOliCCysQh+TIfC0dAUWGliv6pK62BXxRTUkPx77qc4lefOuBbl2uA0tjKnvr3T4u3aYHXBspTtiODQ5QBXhE5RaBYr+rrht3Z9S3W3HDnqk9ADPDj8u7hIpGUJYQko8NAIhNCE5HpqNIIQkpMRDh3pLASw6pBLaLERylHe8IALMuETK6ODKtEyHNJ5WKHEsALxMS5UIJylC0rRUiYpAwbpOSxZVaI6QNK3tKCJCOcq0SiRlFkmAyEtTUvI+Vfb04vorsQBH5EV6hEDyQhACycuOkDPykpFT8pKRU/KSBL4gLykSnJOXjEDyogJEEHlhCAHkZTsQAsmLQwgkLxQgSOWZvAi2p/V2PPgjDOqiKnWhRCHugohKpSBk5S50oiAzUSErUQlfE5V9JSp2JSqmE5WJoOiZoEycJYatpI1kgfIilNP4VqsHV8ahUI7jtlvjdljj9r646xrd+UQLgLuOEpqbuE15j9tSHzdx261x265x2yxC13jNpng9h3A9C61vYgzl8nsx5rdgrq7grA+wTiOiOqLxOvXNdebXXNZCvqu4TsG0BjhYRYJZjPSVJ7orqUhfraL7/Yr0FS68QMjwCnUxNuFhOIvCazBjJLwvwluokeE7RXdPFem+M4pIENJ9Z0Q4QrrvjIiDSPedn465TNyZfOj4M5yJ7s5EA2fyoWhd7dkwlyxocLMbjzK7keRZohvR0I3E/+2ZO9HdnSw+xK4+ZF99iFl9iEzDhyKZZjwPr0UZY0p++Jr8sJ784BQJ5UE+LHlQTY32Mozey7DGw7zoQzt2lh+FNT/yc37UkiE5ZT5zfuTW/Cg5rxLVn/+U0kRcxmzLF9wWyed14sSEkp0v78eaOC0OjFyZDHS1i3/1yFUxp5PeNixTY6/K+yYSO0Yu56H6XVVzHuxD0J2jWX+6rbz2KxfuDtenfdylXrq78MVv29VvnySJZvXbclJGJleTMnxXRhjKsF1Q+j1lSLYtEXdkd0fsro6xBYeyO5zKbWuCJBYl1ISPTSncnCCxSQlSLUoIuikhLr6mhOh9moDbNy0i09urxNGZcGYRS+JYskSsl7WCwOmql2PVy77qZV4p2VVtWGje9UKHXkZ4t9/Ry2+mRM2DsqsAMbRaZkdGDGXGKIgMNs64br0lfYN8SzhfmUF+2VGilm6JgyShtoRExxBlfv6dx66tdHdt6dz6Ff1vfG6zWiLJO2Oo5tTGSrNO2WyK4dUftodyjP8Vw2R+Sof2lPb1qRjo8lACDzUoiPOuD6XLtKITLkJogJTuop9O3emWauVWESI9Gp+yh4MKHClzVAlDSE+Z4yuUCOkpM+NKIaSnzIzLAyIjZd5sk7vOtVO06kcSklpV7GIRZUk0CKTETHOLkJ4Sx6lipKfEMXeiCOkpcUQ8REZKHF9EV3eynWxfjBfFUYDU9xpYfhFb10JsVWs4bLEuDa1S7c0qSytZZW3p3PqVfrIcElhRlqNwY7EHA3pMS7B22ZrJVltTl+av/JvfJAOSArYY36SByMi042KkEBkMvkbg0Vvnq/GloN4Gx42vmCOkMdnopnQp7PPESvlgpaazUnPKSq/Y6JT90qWYj2jesSR0OUe+5qg4v93X/Fat3FT//7lpYZ3nhXnaCel3WKhYq/TbSky/opwnJXl3TznzBpC8opymU85t99cJPl3rscStCf4aVskaVlNlAIZVLfk1ATX6HQTUbX5VwjGUsJ0ogZNFCWuVo5YC6Lod8E3iqaW4Jp5Gv4N4OimviWdUgj1TwkvEk17vIYwtOjxdflxTTGPeQTFd1qg8p5hxuuZsumaZrl/5JHmJT55sROzTO+f+mk8a8wY+CaJcWmU1niVba834HnrT4ygHuceGtsmZ6XylICP+KSUhMuIfCMVJFBCKqwNoCKJ6TnbWKwkiiHVNNwgyI7sJhHQqGmfkENKZYwuaHYHEW0JkEO8oQQBzRXylrLXykMTkrJh+nm1SPqTDVgak1kEEtBWgP8jBNCUQGRws/s87IiB5jf9vAEGMV7fdlGIPgCcDcp0gQK43yzwaqZPhyNscQgYZNrtAyCDDkgeIADJclvTQQue1cZyAkM5eQaaT1A0ynajtHayNwh/T0qitdHdt+YlT6m6uAnLb2CNFUnR2DbKqPFbOoPLTpZXGqi0Ps6oaFtpYiC27Da/Bxg2jY6m6nRmg7QzQ/qguOXG8E3/fGOFP6Z95/rA0eX4k40X6V7geLk2Shf79hPPV0b48aLGvrM5/UUjcbwuJR6+fOPutQuLE285iemV5d5TO5FdxQemsfQul4/aO0sWl2sL7oW4onXn+sJb45TGOqAR3TemsfQulY+aO0kn/GqWjK6Vjy+s/5XFmZ9c8zrq38DimVpY0eJzspi4p5nGnhfGzIyOrPbPZnndxzdSsewNTi9PsZIspFJM3qziAYCC3vXJQkFGFMi3sVWQEXsdxbz3wglCZXut5UTD1W0JVMu/aSnfXlkDhq5hH6xFzHX3ALnOkzV2WVuqytgSMvpvthY/kAQBHiv87gGA6xjvhiY4TMkLXC2IFGSyyuNiGoNqk8bZNy5upNsmGdg0kIpAKcQs5c13F7RlIFgHXyLoBdTTjcXeDnKteNMrIKQXPOgcU3PgdjAN5BtNmRzMC1JNYiADqablAz3QiVFfzQDqFA6lKVmpJSrI0tZksqDUFTlUAN832Arip40gboITWGWjpD1DdODMHrQKU1C01EAHZgO31vWJJPYOI2uAIaVlHdCzqyLxVJaamBlNznam5a6aGGdrVSZX3bia/UrA7OZCiVsamV8Zm7xgbPlzLXjpcS9b95e0587lpn/lHm8p+3lRuLO+rCt/xEhe8r/BJfnca9xhHeEQ6j3l1Gpeue2ngVM8f7C8XL3G1v0zewQVl3nK52l8+jlHjJCdHhF4p852cC1IrJ9QrJ7SzMm44YTqV8+ecUJvj5vSwG7xzE/bm9LB46fQwW0th8tIyptPD0fndFAEVfQt5zDNQV+RRi5MDFycHlMN6QJm+VBf0L7HNfdZLuNlnpu9gm3ZUgMSGKSWnCBnE0dIDImM3ub7IjoyKDaw/RjfQKo2kB/X0ZG+GJag3PppuA3yU2SMgITuHjeJLhIB92fZMGem8spUgxB4E1BOqlJleeEsrDhajygpsCORzlQo0fdT6EmmsN0+ztgJkvfF/D1QBiTQsLaUuSxmJNG6eu6ytMHHzDckPtoI9nhnYCh67m+bAW8Fjd9MckAvCvVJzwNPRsJBGMLnt/KvYCix7yb69nlqQ5TPVzj9nCFK9Ud0tyCisjjJkQUCNmwSEgD3e9vlYQeAer9EQAac0QfU7vSVY/W4suiwRmEyUyJ6747j6zZSCEDwAbTr3Lsg4iNGLiRUZ1e+RTBRkVL95P1ySEXDsBBwL4PAQeD7ilFRHxYPHn8Fq985q9z9ltX9UijwtPZ58AiZfKj2enKw2z9eZ4ulesLvbC270MFI/rdQN9XNGncT671K/t1QEo6TbdbkuStp3YKUxN+W6k0+t5EvlupMj2wZLWIz26kjawc0JjX6JKpxsIZ58ywS2EE8qbciNKjWd8qIQgUt0uGul8KYWQc+cuoKCDPcxHEtBRqlEj4NNSmE/xaXt0Dadh+EQgf5VbQgZPnl4sIIMPy6dR0j3/dXyGoICBjzZFBCjAW6PBcho4kABImDfyhGGEFBy2wlCBikZhYaCDB5WzLEhgHl8OsFZeor6h0Hf3x7dvx5fn/B5zZkOU6x1gavD5ebuW5XvfaCSigC0/kXFgK+/sAU7OS98VnuZ7gPnfZGag/xbeHpygLo7jsD6ByqcdL7O9sXjytXjqvV9JJfg60cmnpqbb3cC62mvTJ+Mfufbnf2l6r/gJ6c4empPqRrZrPgytf8fPqmEJw==###4512:XlxV32DM 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1210eNq9m8mS5CwOgF/mfwCzQ2b8r1IR4CWiL1OHPnb0uw+ITTIml5qMuWRRllksjPRJYCP8bbn9Iw5tb5Lz7X7/ZaRCl8SSLqkF37XCJRYvpb8ci3YQiST6Fvt6pMLfIPma7krtLn/ivWqP9y7i/p9YTd8YD/d08bhpvuv7P1Ky42aFv/+yZoVOrA35b+DQsmQrdPFLcuWhi9+arzqW5J9/Y2filgT3VGS9yHPxC37//pb+cLEGjzV2aW9ptOW22E2Sc38UOdSNfd6/HIeqPChUNerg/mWDSZJdCiIRSWJzHUYkLEk0SCweSNR/kshch0jUkiQqSbZFoseNCipPW0scSl/WrvlRAm4n6ja2I0CyGtyOWWs7pcSh9JV+oB3fVMKKSqzbs6gO1R+hPJ62Wc8eSZqeWdNz6IPjWZlmLyrbiUQkictqlkgCbX6ZrUyrbSLTuxO9O92eQZRnMJvNrXJUNfenspoClbAkYVliiCSNXpX3Z8eSpPT0AxOOhwgTnn6gDpGkCU8/f/+G+CqkcbP9ZuLPn7R0jpvTYbvnBcXYVpdOWO7fhpm8PmE1n5Yw25e2hNsldj+tZraLtprrpS1aiO+ordzm5mA5RsWX/1dc26Tau8KXLFzS+JKHSwZfAvuyW3xJwyWHL7k0koNnw8CzPegGA/5+x3cz/++X/H8o9weJmjrCPV3CIz12uIRHemxwyZQG8PCOOOLvaBpA5PhGbFNQVqfeNLZ+bJfV+oWNVfOnnatzGE3x9dzxZT/PHV+O89xxtpznji/xMZFRjstuPxtltqsyLBu7qUZ5E21U+ztGOT15at7QLrb+5Lz2YVR78uhxfhnilpgZ3BKzg1tiftALC6Ne9KAX5k56WZdRL3vTy9H14tuY2Vt6iWtZDV0ctnYR5675w6V1od5TvRbH+aXjC6+q36ytfaj4+tc+3FnPxdcT938Mei5un5e3VZyQgigXrNiEBCxj/zsJcKuLC4aFhywyj9aSSJp958JwImn2nQvtsKTbai4sI3Wqrf4tVyAL9edfWGMZQOC1qsU4/a2oKZaUiUvNplJ2bdl1FeXxP6UaJpKwByRK90fJBg+tA2oPsUp0hIZIGqtEXFBE0liFC0fqdFaJEkbqYFYRSB1AKKCNUorKqCVNqCXsrj2Tys8UDXnSkVcSt5hYJbeYS+nuUtKYX8q6qy0Sfgm7raLUEHTG4d0w+mjzrDCFFPNWJZhCihGpzRXKOGAW7eJJe+ld2/OEVN4pkkZC8f1URJLetT1PiCatAWVsa34/BZbAm7urPG6J3twyblaGcNRxp1cX01HYNRKBhiIBAJu4BWqZm40/nU32xib7JZtgK19oQ6qRSZ6QyzZ4P7btnyaXdSQXPZKLHcnFjeTiR3L5tsXXW4kbjC9MvEQe7RBwacMNJgVE2MZ3JTVZg9V0KLhE2mL3d5iJwARUpRi1jxi1jhgV5hi1PcSoILYRJipGcWkasMh1IxhFYWIZYKLg0zPI2gaYWNankOWEmEOW/whkBYiFJpDFpRUXenkNssIIWXqELDtClhshy5/1IueQ5T8BWcpCWE31cugGn/4SPsVZL1wOeuFqhCI2QhEf9MJH+Iwuhupl2eZk6D9DhmyAckSG6yEbGS4bIUOiF8FGvYzrKGeUqF7WOSzuZ2Ucc1j0H4FF1/AumRcUpEdusliCwM9sDSPjK4ZSHZ0viiRBhAGMNNITSQIPw0/oCZLETWqjSJJWC0YSBKWpDuRzpDlBaZIAnwH8RmaqkmQwEFxEyUokHXBCTbNAiQBOXsB1cARw9IFrIfDgVmykp4Yxyms6hg5FThgs6YBTHEKdIYIx2ezm0YkZxiRRx5gUOEg84x3o4+gCkbTwQHm+E0kLNqJWPZG0YKMsQCBlpijhF5BKg4slTPgIG1MtTOs9rMmSTuthWYiksz/ieKZwRhBzPFOE8Due5tY64feAB9SdQxt4L0oxWrVWPE552B66JBkKXVDgAFMFQQIshVyKjdbSMQkc4B4cOBiPW4QgAVrMpXR3KR0kcMhmubaIA4fiZuqKK7OZDAUE4akaW28y/nQuPhoXHy9wcTe0r8Dw9lIa77hP4Xcd4de/BL/mJfiNtDCDXTbAbiZbArsZY2ewOxAuv79DsJ9IBCYgE49A1TbwUCkLMwPVTKUvpwDDSylAmo2Jlml/hI6mYZgM/gE6hhEd/UvoaF5CR0sHreXygOs26zq/sAdcJ0Z+YSO/6EdcN/CLPI10jFhIDs409Sboeoe0PpuWw0ijq7PKziX+vyPJKR2lSKXuXTTKEm3YU5D80Ua8i98OUqd5saJGkMSpR+xUXoUqQbaXpqM24uBaagZefwQUemGioYbAyBfv5FiC0CAIRiQdDYKkdToahKbTLOn7TA35QEKQRimHK3VSjQ8YiH4aQUbJSiSNVHGWESSdVIX1WIIIMrTWQHGYE1trSUI4UbgdN4dQ1XiNm0P5Ka8P0hHCRCWJpGEigcEd4W0MI7RLSg3RCYfmg9el+mC+EB98zhC9ucM0TV8USpttt9gPZAJiF/uDnQv7iZ2LvLJnOxfuA/Fpma7ZFoH7RNSnK8lCCQcvKOjSNctZgq6G2VCaxBRJhGIKRMZQKTOw7rsCSZ+taKdknGQkqe8skpx2AlwTGQy/CKdhlIDOumXk4e5SshinuzXPo8Xw66XHTQI765aShyZLySKehuRMeoBob0X86auStVXJ3iLjE/4uI/5eHFe5TBMTMv4JBq/vY7Aak7LPmDeTMU3wLmOCVyQetUbPeZQFpy8SYQ959ASdywidV4eDrrKlJx61Low75X2/2G8XO+XAoz+Bz/AT+MzvrZ4mFa/28gE+Kb+Jl0iTjRlEPmYQFUU5u1QaSPOOtzI7+GRJ3xhFOSiQNLzBmaYkQfkxlGlKEpQf61mepC3MFp0Ls6STnK1HYqCESa68FCBy4QQXmvTUWSWOTpOeGhPFZ7VE0rN3aCstdoTzVmgrLUkQkOS1VbVAgK3Z6FKp4RLezXOBJLtsI8Ms6TuAxtDJq8wYHaaBMZz4hjdLyv8/fGO8mvON45/gm0yME75x/BN8Y4yc840Tn+CbPF0TvnHiE3zT0BpKE75JIrLP7VWTqBnfJNE130ClTDLQaSka2Yt6yjdJhvnGGI0kE75JbV/zDYwSWAYeMpeMbCVyzqDMeW2R8g1EIq1JYBloMpeMbCVN+EYKWMgxYL4dfU2KtiYFWpPnTe/uG145o7fMdroNXucv7HDrRjcD0vhHSHOPDyvZgwNu6HyvcWE84HZCh4sHvzrgtuzP9l7jsJYHp88Yb4kibd/cGNXTkRb2mFAFHR4EzZLaAaQ108YUYv0l22EDGwSpnTLBcb5tXvWxwXooVtRQOyc2pOD1iG3qNFWpC1jsi2iVWD0um+6KPcGJVIflOFchWCCSfvJVcE4k/bSs4IZI+pmpnXksQWdiRfWJMKz04GnwJg+eoycmg8+HkuuBqawRdIBYsI1I+qFjwQWRNOccJZZIGgXELhcsaeQQgdELm7cAFN4CWGUzBXJ+bPe0yJcxdJmcg5mYhMt8v2um4IfRjb0+4fL0RMsrx1jEGOWwFuVMMvs1Z08y+8dLZ1N6Zv+0JWAz/LBs8JR22wODtzF5cbhyNHjFhC1jjDQ5d/LE4KkVEoGzdL4SL54EcdONhxfDKPvs+IdaFzHP4XO1+KuRPjqb8cqBDDWGU+LSNCsPOzinw7NLHZ7Y2w6OMD3Ks8Pw/Ji4HyNmbseRunGkJitwryMEszLZWuBia5GyWcJ8a4EfL33wsz3aWjjtSZx0GRFK1KgqjRlvIEQ11zjI52z3HimPuZztTk8qiihZ4Vwf724rFcg9vN3TdyIUmJh2T7TM5R6086CAm3s7S2un7VuUFzYNNZXIToOC4xOtenS7pXrfc0CHL1J1FBKXieySHhL7dvgiS3qgatq2PkhQ2Gvawd1cp28FeNkeQJBotFiNKqGHPDxpDp8z6dsrjpyV4L6fRnDkrATXRhBJzz8EvRMJOivhcGskvjbB4ydCJ1+9k1iCAnnTjrpkLaCdhUomRdJjcrRl5chBIOVb8J/rNIhYZY5RYBOtvkwQrKuVpbljNh0JsJ0HVOMB9ZwHrrKcF0cB9jkPPNj/92No4H6a+DSvJD6HbKdoHHB2/iXreXb+anTYenT+ZvT04969A1qZfqsjH3+r8yAxerVnPz8Jd06M6u2BZ2cb3652kkfPPjqkEpz8wMmbp7nSlfF5rpQrREnrPuZKBy+k5p+dsms3nteamjhJxRoP6X5AHZzk7HvXk5OcfPo62WQvkwiGZDsZ2pzcAUsSlYYtuquBSpZgi248kfTNXc8FkXRvkzXSJf0You8GfaP+IS+JJHH1g8pqgpFp3KgJRtu+GzXBrj1q7qh/yhBhj0i6CTbBEgn6MKLlpx39lBLlpx35lBJnux39mJNbGYgEfTrkaZ3uofJbXlVKyEDLPncLOQahvSCSftjBS08kDWXQUcMs6Wc0VsaQBCFWWgMyvX4xuI7+xnd/o5u/0c832rIneeqC2PhRqRg/zTiGhFXyXW98ijEmqga/sz4JSZ9uuImXvqjgl95Ijn5Gjd5Ij0fRJnEndVArHMKYHS5TQl4c2brYzAMNyf8CEW91uA==###4372:XlxV32DM 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1248eNqtm0uS5CgShi8zB+D9yLC6SpuBEGazmVr0sqzvPjwddxGKjKqOTSahX0jIQfiHO/qySj/+clE9/vlbBMu+2Jf49UNbFb6sZlXRVbHsIAqviqmK9BYrMlRFFkUlJouif/0QPukv5+KjlgyULJRcK/3l3FHrxXz2K/ZzoihKYEXRwUV8RXvMK46ShZJrpb/qn9LGqqwrKn7IIvmzSi7OB/OHKQ9Wb2Z5VaJWRKl1rKjN8IdFijyPXCQ17BRJpWon45qdLLlcs5OyTXFEaf2hResPk8nVan/o1JtgQPG9cfb0XfFI6Y2zKXQzGDCDGWawWXSbJyR1mwvZDKT5vJ5n3UC2t84ER5R6NS1bGzxDymgD7w9rBanEa6Vmb2k8VqoZbDeqdLQJrNYpA+KfOC1UOr78+fU/mctvb47z8R+Z9fnFRSkpxXN5JPb4WdpQzn78t1i//C+nGFfMkPKjHFIaHTplPaQZPsTbIY4rnu2QwIdSOyRxRfYod06u3znVh6y/w/h94FNdrX3qLp0GS6ZJFh8K7ZDDh452yONDvt4+i3bN0qft9k71e5QR2P+Th8j16ctA65LBN8isShZbIet2iFxAtENHv4A7+j392X8H1n/H0aaIrZVrZ5TpCB+K7RDun3y2Q9hA+WiHsIFyaoea5X960S3uRX8uJXQ7ELUV9Yxakf3qw6ZYTT3qYDJf/CgTYD2av4zKao4mkS6jSLB0HUWCs+soEixfR5Fgx3UUCRavo0iw8sQ/65tU29wGfu1kTRutR6ODP2ebRZLQ5hN3ShzGb53ws04GxCz/RH1Ys9sljVsIXSaiaZcjzXtIdrULd2CXqzG42YzBw2YMvhuD+6sx4m6ME4yRlzECNJT/njEsD5sxspmDJCm4h2bLGHIa4zoyhIaRcbWAEJsFhNksINTVAmmzQHbTAsV7TguU2Wi2Tv+mBSS/WkAwARYwz14T6a/DQbLtNRHH9pqI/TURabfLCXa5GCNfjSGYBGPwZQwDDQ2/Y4y/1ZH9IJH6Ilbh8aMNQyimVcy9+Ff7Wyuz4R6b1pxtmZWIw++1mocuE1djH2CB+l52x3napshIlOqhT7d4aSmLEvq7PRVCCcEc0IZIKEFYl8j1qiM+KwWOObRRYCkRjx9MgOv5eb3kOnUcSGqGKA6SoEq/U6Wl4iobdaQDKw0TTn0h0dKGXkeGrpxYQWjRZw5QAC0qyXmiLFBxMRBlEVEEVurKIqLQGG+Ol06p9d6zlKCUCbkGc4KFEiHXMSO1m5USodAAKFUlTKGWOaIg3FWZKIC7iA1bixEbSk/qYKb1pAWIaV2kbQOmLQr0RZlqetui7XYVRKlti22E90lpKsMIsQ9WFkglvGQhylqyCBnIjfDSyCRyNVgaoWVO69q2pGmGGqUEpXyzzGnnwDLnn6hEqjfj55f/EmxRbQaqzU+pliDsINEbhN24FU+lA1YvkDrJ9AKr5sKab0CqBUitZMrHf0Kog0yB5PhjQuokUwqrpuP1t2R65nsyRURqd7B0lBrVKd3OHOAOszTTy0imgcCOq+9jZkfEcNdLgtnu9c/u6EobqmpuyDVLNdtgsiHkStsQX2Hq1objqdNV4sz3QMrLfAEMpv4QSMvjsv1x43pcuIeUEe6R7xiMb2s8wdUOpHoHUnHpBXHec3JplpjNKjPHzslbs9zeLP8WJ9u7jjnv4ZgL/u/huHSMfQHHWQIamrUeX3AMOCdvVwqDl5+Nx2dwzB8XC7yAYy7Ev4fjYoHq3+UNHB8CZgOTNIFj+izpWRf+XR6gniV//WizTnVLP9q7j0hmjEI4pziocc5iGiNa1EiVc+rb2vm0jQ8opguqhnN4+NbHzb/207qTLZ5qOLFeF/FJ8YsK3az5wHavWUrEG4rmW/qNFHb+5TdWsIsfVp+tw8wijkwU4JxiJ1CKxTD5ljZIeJiTxsf6TDslxEBKuAPfaTFQsU3AymKgotB2AwOVqzOiALkVxZD+5dC/QKZjglznCDgHGHX4LTHOqdPYY/TQtKkEXRCSL2d5MEKmJC+OCHdmzQrdvojcy1MLfE4fxfWcxfDlHIvP6aO4nrPWGsXi5F7dEu0cWBMNglrnCDgHVkdF4fCkrFuidHczpMgMj92K5r3jRylhSC+/HRm7gKeH6iOgrQJmV8gmxCEUZJotk5X9dGyt4rHMVzwB+yU22U+y7yOap9wjmnzHQfZWRDNvEc2KlncRzOPxDic+CWZa4MRnEcz7CCWNTD7lwAF9YsCexWHIb8OPgvE9/HhA+HGjxQi0iMOQpV+FuY8yCmWOJ9G0PcrI9/DJYDV2CRa+EWVMe5QxEs85BuNdCFBZ/V4IMD7eoZwn0UALjf4mBFjeWLmx4UIQvhDE+kgQ5C4ud4nHPUUPfkNcbS1zFynji1ONS78VKZN8b166b96xk9F5tVqtqGhL9Wrp4tW6cmE9gG9ZHk+c+qtUZgTXSUVYPtfwcS6TR4QoQGwkzuX4jF+pRJQVv+rvTFOEuUSVaCUUIArT7XZlORcdRECXQ06xNI4qELgR0QisoNCRM5LUAczSK6jUlRU68sZhZYWoigNN07dmQfhHuJMo4F3kyQxSJpyVLi09tbARaq5oRnGPjlxzRTNEkkSBqMlwqV3h1Qu4mZcdbAKVUA64c0FXJOEw4agC7FYeyyKFPFam1NdqEq6y5JqIq5IgCnBV6SxNRt+KkUaJRywlxcyQLeqLULHXtpSkl42STE1JmuXAOThw/kZK8twceMq7A5f38ZwneUj+fh7S7l7c7F78eCva4/eUpHuVkvzW0evHO1lJ/tGs5LFnJdNbWcl4zUpOnnAX6niRoDRtUr1NUJal7PRtJrxIUB47OqTdC7P7yM+TrGSmaag+v91lJcUnspKG+xfRliNbQBKWXyCJ3ZFkD8WN1ON3gRe/Jyjd1S7+RYJSfCJBGdv6/waACqot6Ajq9wBo57JnOUr5bY7StyjRXY5SfiJHGdsC+Ia8ihEgIKqduycvsafyR6rxuxzlDtmSb3apYEft4l+kK+UH0pXTJ9XtPdKTvKKKZ0QSSkaiHKdv7W7ZTL/SnbU/oehp4Eho7cF5MowEhnGLlUUlZQgzrCwq0ZFnogCVlDqaKMBN44VYCnBTeWTcAhxRKrPLBLQ6z2AaMJBuqwrdV2XAuivD2TOmK/NYJ3EEiaURDlVCEaXScEDbGR3pfFN+e6wgvoknbO0qfYUzqdJz/EQElD1WnmZSuxWA4kV0J1GA4lEusCuL4g3XxAaAw+W3IsoC8j7LL2VlUg2sMGqJrAmArvuARfEpISFz3a6Hc8MuYAVFVNH+RePmXkVI8dXRP0ueJvbO9bKR/YtjBpwKyeZGkVHX4mzuWJxAO/oOR8git3uMksdhKbJ6OkkW2HtNFKDyQsOOKJPK6zTlm+F15Vq9uFYA14o3AlP8LsQ/iZXvyCt25H1/fx2F2LBDrN0h1r0FseZbiN3IVezkKl+R6+c20T2NYsX7KNbxNIr1ilFVeMGoqcxFsDtIv2DUfJsCYjuLsX1L0MDXVzvnfNvxe8eo5iOMqtyeqEzLGADsOkfCqBRIww6kdgdS9xaQmqsRXiQFg/kIkLaxfwukfrHYce5AutHWnpoV+hWF0sdtOz7u0NN+BD11fIWeXj4Llf5p0O+4D/ql74J+YyK/4037Ed6cu+pbCXvi8W40f6sC9ezKEGUF1IzSREGbxpf3VoGE58zcxtbuiPM+iJVK4xArlTMtuc/a2YUoSjlCRIjw5vcPgyxCNKQOZiWLFRSiNAo/D8m+IRyvNh3gHU8oljEOxUhxfOw/a35dR7KDKuoDKWQHlffQiz7erhp8JFsY7YJ4HQnEB+jfriyID/DUXVk7v4x3WEEhTERntRc7icVzlooxZine0Vk9B9FZgF1m7V5ryaKDxKYftBXPWarXGaVIvzuZG8165xDe0xAjLvMk/rqkz5tToSRoT1Jp7d4zjChov93ANqizviEJ0hFl8WE0joxctApSHil0FRThs514yZ6jtU7E2fMyGY2GXz7gSBKoUv4RVV5RcnDjBz/VCG+FSJ9siDt2unQ7Xdrf/2pD3H+1oXfKZHt8VH40Prp9tTEZFAPnb1Jm1P5VEtXzt5KoTyhzoyr2Jx9lGPki/Ok+Ev50+tVms5jss134e/gzvBX+fLLvLO606XbatFe7hHvadB8Jf7rmq+62oMUAtrfav/F9hrr/PsPs1Cl25tIXC7DjHkDdZ2Kf4mXs09i3APRZ7HP/PkPuO4m/o84+0d9Qp/tElHO4x+qm64vYXXIdeqPEDiidxE2b+XFrKxE37SYCtRL91DNlJBH36Q1Rlpu2kLXuCnj9ArICK8iBrw9He521YX59MdkUtP2+v3DtiWS488XNNPhLz/WsmuyUEnHuCRvK4oE+HU2Ffkei6OUWMpszEwWBMXzp2RS0MWxBe+tbHOCEL0pbnRXg1EFAhl57stSIKzqtPQ0iGgiV1xuRTW6LwJvUWbsZeBTZsYrnZSflIuY2/BYxY/oVjLL5YmlBA9UL+PqtyJdCwpLHXvFWtAFCe7K+seogyvoOxhlSB61voiTKWnuV1QYjT4RI3xqiINJfNCpI8F+YmLCCPtcIIWPl6eqgDZe2EmjjvZfYAaXzZnXQzkEfZUxDXElVAamqe1LdduOxxy2p8neCnnWDwLuk6ndSPSap/h/ukYvO###4436:XlxV32DM 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11c0eNqtm0uSpDoSRTfTC9D/k2G1lTKTEJj1pGvwhmW193b93VFARNaLSSbJTUByCfxwXSi+ycdP5/fHn39UYvKLfenfP4SL/su5+MhbYWzFsbWVrZ/Obfm4eCQ4Tvxu/x0FKEKCInw4qqK3EL6sDKAom5XgN6woDYoWWbGeYUWzrCRQdDDkbJqDYlxRrCFKboHlRZGOKLm3tlzHa94UK2K9jt1NVoxQROFZKa22LhFFZMWV/jB6jMyKzy2wYkOK3LcDpBTyQTlcM3CqjIU9oHV/oohCZM1+Ofjx+3/ygM57s8vHf+Sh9y+uYEspfkC82eOX5Rb++/FfCDH8hn8xDs6X9gfsUhrvOvIuzdCunZVdHO+SZZeo59QSnyA94HLJVSn5/Bv+Du3vDZ/F5rPs+PIQrLzL4F2m7LJ4Vyi7HN61lV0e7/K5JUdtJEy40hJXegt/K3zCI/fHtf7AbKq/DblADgxMGnyUKLvaUXarv91WL+T3+ndg9e/Y/i+iaAnG8ymiwmctF4qtmRGH4ohFIi3fyi7c0gNG9ZcXNeJe1M4oocuOqL2PsJHPwX7XuQKdU488g8wXD0edQceXUYfqU0ik09QRbDtPHcHSeeoItp+njuDsauoIBt37lW+ArOUpznNLNW2pbi21ce8NFWnMdbHjkYgthuViv/L9Q2LxB4LhwhqMNIIBM3QNhmTnYHC7BIO7JRjcrMEIIxhjV3yc48L9OS5pjcs+4nLMuITRZv69uFjhl7gcpsdli+ZZXOQ5LkKPuPRgnCMg+BIBoUYEaLcFW7p9uN7tjY1uwwOrN0l/czqE5d4QTMx743jWbX/utuTLdJDscRmBbY1AWuaAOE5zoDz+NW2pHMHgMxhmNDR8Jxg5afZ0n29EOPLxo0y9tgWj0bdE2fqZf+Ss5fRIaB4nWzj6IMpItm2+daUmQXhUl8wp6elGvhcmJaKMfI+IozQYEYf0Fh+DiEOWB/ZQEHHU51BW8uMC5+76+OgKyd2R76gJKHfndtPzTX5wThBl8IPaDo8GI49SG42+CcMxNkXd/Fl+5maGccHQESMHJTdTiN7MfFhpJuSOcknGkFSCCNmkNtOg89URjraejhElj3AsACTLbBpdy4EHGiiKI0oOPEBBHXqiTARrSawofkATr03g2wh87IFPbVpgqfQICKX2SKHz1cD3wU9EyWfTdSo5j/taJkxUtd00PnnKRl2HfidKnrLRULgubSsgXSZv3cp3W9sSJ7ge8yz/T5nqgdWIk/aVqR5lHSWOjlGI8aFTHHe3DEa/D2mI8mBoVju1ESXPZ81rEwRWyqDDD+BX7UyeKdBV/cXT5Fc1+FW95tdKppRf08qvcuHXCr7P+fV4IF6lcLoNOF2I1KxEalcizen+RJ58kOcJRhPelTtKefTQdzyKqRVQ1GIUpQjaCVKtnKlXKiU0mlYa3QeNAmlGEa5JUygzs+mWbkhzX0kzrnC1vKQ0RH1Omolk0zYZzQUGxsxRraXCEgykzBcvk3xjP7FAIwW9QJO85PqGwrgdqK7hFr2mMLkEsIIZCaAQSwCFuWMzTHC00eqGoTjk+x5LuAsvGaoiEG30tjRarqMu9rXRx3OglDzvUrSleraUj+ZtcDyr73OWHe08qd5V8Mhwg5g6DuSpj3KFDioRZeQXHYbNUJXx8Gy3T1dIjgvJ44PQU9qPlFmU8cT9R1hOjpnPb5j97Zgydiidg8KJMtK53LtrUZTSuB8loBCn8uTn85zyKwcrp5jSeB/xoTgvSWOxMjOqtt6RhoyMquuDciojo7abuioa0yY0PiGFNP6o7RCo8XmAe1KFkyp80kmJoGhyuelLOWOIMn0pZzxRJirLHvnSDewkyd6Cpkwadb3ZRSE0KmnjMPb2JtTTTfqCyO7kQpO+nD6I0gEW7qlQUoRQ2ZZSM63rkdb107ROcvh++bKEE/cp4+OUtvP3PSj/uEnzp1z+yoNya8Y3dx4UMZxoFqe5Xq65nv+V93SR5Xtqf8ddOm7dJcilayadOd+Pt3QdGMn5NMHvl5mUra/LbLVM2Ol1uT4wr6wk8wkrKWpzbSUJ5SbtxHBjJfnHDVac2OGVleRWwjDnuIQbK8l8wkqKWi0zYkAMxGXEXm87gRjiG50AhK8wIxbkWTN+KLP9ykKyn7CQYmmIeY4/0N30rLv+hnV6d98wiTIO0e6aG5PIfsIkirq7M3mciXFjwwAOuDVwZqk0lN91831ZXaQ8E9sWDFLfMsRZqsOXs1jeIu+t3myoHdglih0qqjIztop7h4py8ekS6WAcORuqJA3royqzklQHfirT3ApK4kCgRDorVlUZTlC7a6Yy8r+OEyWLMvN/1BYpJP/X+7x3lbhRLWP/ruEmDlDcI5KQAwQXmF0SxFFCFbUsYSCbVbiqTM6ME4KLMjgT2SJlqhQLpIxW3cpTpW0ZaovsHk0VbIsEh5uObRvvA2nFtG0Gb5ct6intBknYU7KWDOF0vOCYeSFHyB7ml0ISeh0wjG1Ema8QNfNMZVpUWnusYDcHRdzhtwHkNJa+Vk+xzJq2mW+9vmmI0/gnKllYhyd4Ago2+c8M/jOI/852Dn9cPPaf1SAb94m1eCkb7xH+O3PftnJfuOO+BfbMCnvucYY7Wj3815zX+e5ZLbFbNKpJekU9s1YeL9wb4vEMuoOBcze1Q7YPn8S4O0fnuBrnZwXDRndirTSe0ztcT51f6CflcXFJea/TOvyzvSkUMhj63nNjbugurnQX7uhuQTqzIp2jXlY08Y63fLrlrVNd7mPoBc3y17YQNGt7YgY+Ka2xy6nTkIkvhbgrLwg7RnQWmdUWQpN8jm98yxaCf27YUiZoThE/ykWKK5Kf32akA+NJMjViM+hQWtUJGh+Gay0uDRAwkS6RGe/0VXkKNiZSsBkOQVUm2NSp1hUMf5C3Fe7zzMzCS4+bjeyfQSJVQZnZBtrVaf8gtjKe0sbkJOMxbSgZ7GibxWAKyoaVSWqgCKIMUlPS02NmzW7UGpsySE2m3SClGlBlSjT3LE7+NJEw66hSlmcxztvSe6IMcgBFEmWQA/SKnm2QA7TQIoW08ChHHhJPTExEFQGqZJp7VpEIrnfgiCAkkkHhlkzfEpSAlcEw+f2m1ljPa6DsgA37Rg3pW9CBFj7d+E+thvRN/2mBj7CaTtvjXQ65X/i01Jz047zwaSERtlSXGq/8xcKnp1WntFad9re4JX7XpTLK3nBMSmPZj2Yf4xi08OnOuEqnV3i1XRtXYfuIcVVenS+NKz8NGufeMq4WnglrMFaoe402ovkGz92qsH3ErTL2uuQGwYjPXLxRclsoyry2ccQKJPrU7SfrvYZrFdInXCvn74p2Mc51cHOevVe021eOPN4Cte21vVUe/xf2VkgfsLeEP8ZrsrGkbuLZgRVUCEJVQGMpfTlyNkRfyKSCuxGhgor7hhRq6nTCKVvY1MHWliILoOB1P5ArTTMqTrOgKMiMQpy3kWJU9B3Z8iOVLArpFbumzEUhYWdEmWttpOdYQXbFXLZVFIQHyCBSWzeDVF83E/jc2q8MorFErK2bGaOU7woEqDqUKtq4VvUoVV8RF/jc2qlvyRO6FvYtIaCMTAmM3YYoGLsdUgh2I8cut2E6dtjWgbZ3A0eNBWSBo82dvmogHi0hQQu+JrNXZbyEtEdKV8iiszDWxpVLIcsRlyM9KQGjtUT1StOds2PRWVXGO0DLnqJ3+sK3y2OJfDtN74MJqYYxgxW0Us2mg8zpWfmvqNEV5PXBA6w9Xc786ga/umt+vSma3i18OlZ+3f+mfvpO0dT/bdHUvr9wnz1uUJa6b9+w2k4rqj61sj++AbjdxntVhk33gCv5HeDKgTHa6xVwb8qxd+ut0gq42+vKbLEUryqz4hOAa0p4rry7JId3V8rTZ8B9pxzr/7Yca8/B8DflWPEJwHXe3Kwpi1G9t7JfPG5Y92Qivu8YYqsRx8Xvx03dVn6mbhtu/Unxnj/J31m29oyA2VtfAeynuJQEclXglR8gYMRJeRAwJ0VmR9o15NM5TFCG2FeI1uC+72TWC3vlCnULOkZMw/1ArSAEVaF6nLIBWC8rl1PWrXzKCWXtRuiNJJVrs2nSs8Hpk1yaMsvMbpi4VRkgh1mce/oxAkIaQz9/5B4dg9G+fZZRK3eBLCFHiMfdhLlRxCuha5sQjJObLOlpZ3E2yEiUiXjoXUIHinjjxale6nlVuQwJ+q4gMkeuhBAvHVhBWGg2gxVE60aO9wzIhnhlpREHUWYp1fSVgU3Bq/2pMt905PgIpChoyeX8pKQo830GrtNnWL4iLu+b8TloVWZ5H+5ipOA3QdhhyEHzixLpIlbIZxcHVhDMopetcrb5ilixoneILknlc5a7S9TOd+hAbXiAtTtNZwLWk4D9IGD/hoO7rG9upu7LCvJ+V0H+mw9a/V1R+XvfDLxaNkgRlVaW9Yq7fMHd9kHrv/Bz1QqyeqXWVx+wpvnJwK1jG28d2/DWV6ucrd8SHO98tfps1eGans8fsJon2DLY1oVPsK3z+oZtY5TvfcDqn9el/w9kjYe7###4460:XlxV32DM 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10f0eNq9m8mOJCkShl+mH4DF2TI0r1IS4LjUl6lDHUv97gPGZuaEe0RWh+bQWaT/yWZg8GHQyn+xr0cQTrGcUPk/9vsveaj0tfGkHv+Vh9ZfXqZH+Xh8abHLx1/bxo8vK9Ljb2tiyf+3taH+G0T59+fGo4QPm1BQwz+lCr5WkUYVx6zC9yok/24VYqnisL2KjY0qEhtVqO9WsZ2rEEyOKvisQo8q/Heq+NUMJX7/B1LlLx4/zCGytIVjR1Iu5PHDClkzsaGwnmm3NVNEEmQyuytKPFzpTM+Um/BolfakmMmtJn/Az5KZzRq3WqwTe23LhpTaFid8bUsakmgd8KwoO5OoLdlOrSk9JUZqg9QPa2OtTKASa2XWpSwpDyYdRZrYi2wpMVIbpH6UH//kQfbS5ozha/sKv8vIHl/OMP+o4831mJ+BPX5mI8MAZpPCiOaRqiMs6sDOkYd/f+a21d89g9+zYeD3bDsyEUor5I1P7p/wSS+3G5/cP+GTXuobn0yf8Mk6XFc+mT7hk9VQZZaV1IVPFgn7ZB3AqsgrnyzSc5+ETNX7oNKe1DNpL32yaNgnq426cuGTpeznPgmtBP+DTraUHilLfLKOeS+R+qRWuEjwPyiypfRIWeqT+lCrT4bhk/v/xycNd9c+aeMnfNLwcO2TNn7CJ/WxXfuk3T/hk3W4LnzS7p/wyWqoMstKivpkskjCPlkHsCru5JNJI+m5T0Km6n1QaU0We46kOvlkSL2ZRcM+WW3UFeqTyQ1pu/BJaCX4H3QSUvDXLaWIT9Yx7yWe9kmOiwT/gyIhBUW2lKI+GWQZC5EHNP+YXhmHVybildxUr4Rc+U90WYjy8pw/bQp/kuUTAE3/tO/wieNPB3wSOCODTxL/VXo8WQ/26t8mkWpjyQ2ToPxrsGRAsviTg08Of/KPZa35aaFr+fet9t6SFh+l91bt+JMqnzSu6yj9soa3xYsUIB6v17PmRdmbsGmOYlMbNvwpwSdsleOATxp/CvAJG+iI8MneL59Ki+ILhq5tW1sV+C51XxYUGwt69hU6ZQQ7zlNGcHaeMoKF85QRbD9PGcHSecqIPH8fP2WKR1vKghbXa775xJqvNC+VaVrF3u0Sj9Dr0G4ul2wxQhhGOPecm6Xn3C095/7c8xs8NJ/YinLP4zIjDj177nod27GNOmSfEWcLiGXlEEIv00CIYYyzBcR2soB01zul+cROqaqrG7pTim6BsKsnPiHd2SdEWnxCHIsxJFuNEZeZIfYxM07G8Nd7uvnInl5nXNmlSupiTy8S3tOlawrMpmyXrGym7GzVr6pyfJWulD3dQybrkZRtkpXUMiWiFA5ItiqRKKVxydV2i9E4cYUVRUJYkZuw4+I2VYpTtUecVMSKomGvFv1MC6XBvgz2qCnpRsqjvfpXm8jQCunI9i+8P7D5Sq/yHlP7uyOlmi/vZ9BCz3Cm0va8s8GB3ClSHCtK5R2tiZJNnic/UNluiFLG1vBqiTEYee+AsS0/QDFYAevVttVtfihgPcVq20geGHTFa9ssUcoo1f74wIlSRlZJMI8ISGmzixtKjDAfKhvClG5J6WbSL8SIx+o5/MHoA+jB6NeUdCPlCfxVACotLatNHZNQx9EIrMA4hq32m5E8ZVoEW62oiVLGMeg6ozlWwBMD2Mpq3II2lYKoU9OP7nqCwXlUDKmpWCIYStXQ10HVZUG1ZQ3J/KoyUkwq3QeVHq+pdE8rlfKFShuo/gGV7o9LCvWDQk+oSYBUr0BqViC1jw6elBfb3vcaPOUAz1Em8KA5Q2xmToOZ88ya8Q3WFIyvrHmsrBkGa2KUzQMPa8UVXYbA3qPLuOykbN1JOftTugyEMNpsvUK/4P0AIGFu0M+vLXRLC7leKdCsFGgpAwlvbxCNm4GBKq8eC6JhsmqNfgfR1EolfGlpwT3aUnODUtwMVN/2dINS+1soxZdGN7oSK13JE6nRRpfB32ij1Wz0hL6Yi2L1ZGfY0ehsr26X1xTbGKoWWJbGkip/Ubb6smrKNMKYxVSwCte/yuXCKm0V0tGanxVDlLESZ4UTZewGynQuawradTQpDe06znmszB0k5xGoW6W/fVvM3ZrNtrRbR23ihnRMONYmogzwyIonyoCVrDiiDMDJisUKgiKpcQsxolo7NtPcSoqoHYZBwrgpNSfKRFRrBVEm1loriTKYMpfmsDI5tK2ooOQUJpzcjQ1JCIuElgdRJko5vRNl4pfxnigT2RCgFAVhHoKNogw0/Cdsu6hLFv8yEwBSBwDDMADQAA3d+eg+foxYzU2A5hSYgY12Nuj5GmrDOOCbSSdP1lC1rkz88syPjrl0ET6f7H7lprTpCQ1Fk50fnduaMiY7PwzHypzSOU/AynSDZoau4ANFzsRIRcNHM5dEonQfLSdSAdJWApDbHOljjDR/inqE61poEVtwITi5EFyhwe/HFU+sZlbuexVi1C9DjE9I7zSp92Xm0snM76DvO9HGV6HF8BbuvRdajEmsHNXhL//V8DAVE4E/Snrh1WTo5CdPfEgCJWK7ixiKD0QMY2LX2Jj/zD/p7m3E8ASEfIXLV8FDfTaCugseyg8ED+POrldVodzkveDfItMTfrJ1NeVrtPECUk/GuIsjxu0DccQY9/OMmPCbjRGfzQj3Buk2hn1FuldBQ1iir4KGUX0iaKg6v5RFACNCCBorEyuU729UmjJQpEXYpjLwpfncVGYkqC4+XSGcVNcCCFSIjUYGIxNIwpFBy2ZNjEQG60QaCo4MGkmUSX7jHUJTJi3G/SDKIMz8O0cKwdIgRkBTKBqjjWxDEo7R1tUAystOi2hBuD1gZdKC8pYoCLS92Ygy4TzGgygT6Kt/TGUeAuoy0hVMJTlTB+CSnYatRBx9jfT2NjKNJHTlmxvenz/AkNdQrVAjNcK3Jd8M3+J4ophBRKFmcsYTS2twPDF/GQE2QWO/OKAoRhhRqJEaAcXSnhlQzD1UqEgUohSeeWQxElA8NFbmcTBPUE6UeYT0lirz2BljJEo/qpa3BzV+agoVTv7nbFCh+LNrafbOtXRaNoUeE3z/WnqPKwW+Ikr/eOfSWj+NEb5LlPzuTPQkjHh5ac0+eml9rGSZzmTZY4sXZImR9AYyjYo3EcZ4sCe3lW/dX7dA4Yv7a75uu2x/eX+tE797s/QJGjWwA5ur++uUnt3isrNdKlS+BFT/eOd2W7+Ma+q03T20+gSguphujv1+3qA/vd2mnHl17H8SRb283RZnC5ibd2AfoVKX3E1I1u9mBo/9t2635frio7ErX6O0F6CKCZfaxd08XvsEs2aP6dtk8R3CV3VewkuttF3xVZEwX2mBy0P0J4wTRBn0l7dqRxQUXxxxP1AQfzqlSZ7BnwgJyrTCSCAHmZbZQGK6ligTFhCYlOWrPWlL43FbqaGlHAaTjBIB56vv1tJ4wVbytZQj9+PVFXrryf34IHhwZwyObtBhSZH7cd8vNVsmdAs+yLoq8xbcDt6tCroFH0FQUBA9zyAoKCjWNpGx1NifJ6b5UrH0syfdCRlnSBgGBoXuJ65XZRAZ4ruqTIpzCZdGKNoJWtG8ZdbzCWRyV3wNw4ieVM6HE2WrJs8FrMfKPCTm3w1W0CHRKEcUFONOcrSAk1NdY4SeCZ8F84dAyptHS6MsUWZkfD5zAIeDHu2RHh9hqo/jY17AbG3D6WEm54OA5XVc9CKc3Fn3xc32fVyUgm1cwda+FSqdl98Lzbr3aXaN8LeQ6atL8TU+2oB2JeN/y7h/+BozvRcyPeRdyDSY25Dp1bVD49ZX1+CnkKlV+hpSnf9IyPTg15Cauzsen25xv4HUsEKqfSuKqi9fHRbwpcaw12Tq/EdCpynehU4Df2aMty6ktreeYD4JnYqVy/jZLv6aV53/BK8aw254dVfbd19j/uETzON5NLUu7Bdk6vwnyHT8n0IwR0icLEWkENwx46FWzYRCdYIWN0N1KLaT6KM/FyRWEO54lrCCgoXxGCHY7OcEqG3fXCF1AdRFQkCtvEmoPBpO5USZ4VS/aaJMoPaHwwoCai0ZyTOv5W1HbUhdRI6LhCPHRu64uIkLeSDGEOV1n8S1D04UFNc+JFJIXNs6STKh0LqgCrrl1w4rk8HQ4aH4ODk8TP4xDB8eEAUWr0AUiNAXLFchF8a+J/1MnqOlCCENo29TRMQKgeJElPki0s5znmEEl814EVmV+damrkFdIbhsO1zWhiMoVl4H1Ol6yoFJ3VJ+pEhoOf8ekOkvosNQJBy4oMiW8iOFo8Pl/8jc+LMIrBj8uf1RBBZd1dOHmi+fYD65wGf/ClTdW6Bqr0H1Gxf56h1Qrbz56vXmCVT/B6EHi/U=###4352:XlxV32DM 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1258eNq9W0uS5CgSvcwcgK+ADOurlBkIZNabqUUty/ruA87PXUjKyOq0WVQWEU8gx5Hc38OJzX4oIfnr9bfR4oN9lP9l/v8/8tgKJNLr9VOm/SjYP0HJw+aWyv/Y73yNTvkapl7/zZdvH5zn5n+U4seHlSEPxVIdkkH3PE408IXi0bYBFRPrgLoPyA4/BtzfGfCXEkfILfH7rzy0+jCav37YzVZkG4jMiMxIKIiMKSGkTPf1F1iWb1h6ysM0PJv1YYN4/QWeKPcvuGJ89GcNL90bvom93Fm2/kpo/6qXQvMH/AUDFTFdZAMNBwNYIkgx3Yhq+oEQYvoBPZNHpim+l64OZhWZQlZZG5pRpfXD2r12d6O7+ChuzpBn1aYDu1P64k5ZEYcRpQuiKhLJErCC6IoIgpRlC1v1yk6Q4pUAbhchjWXx1SvlT/HKIRHSvFJWbHhlQwtavWJifUq8JYOKMqiotwsYKdMqfwARpA8rfVgdjZrIC8JrH4OR4r7yB1yh8WKDY5WpiMcIOLbaJvO64QekOFbH6oppm6OuSNUOhfBqYWru5QQpnkjNR5EgxXvJVcfqgdj2vJjo6nAH7gQTjntFLEbAsak5dic3Ko5N+an4JwjrwW75YfOf3yVeHB/O8BwvIIpws/fIEdjrp+GmRTfW/uczyvEkRwDsX8X4OsVCnnKY/GlqoPk7TwpCkIm+fd7xpab0Bl+Mrzx8tdWrk8HQDpDFXzn4yuGvtnL7o0ZpKyTc3ipdP+uILj3KfHLUw72P8pXBsz4YfNUGNHv93+51YFdDbX7Z6+fQrgvYJUcqQ8ATNL4K8FUzK2wYAhsCnvqxw1fg059OVF86EWtUz3GxNIK2tlijcZbgaaSd4DdY9eNj23JAb8su4s1yC87Oyy1YOC+3yJECpz5h9wsbeqZye+omiCiHCQk7NjSXgCN/lqBDZvlPmWa5xtBbxDlN1e+hjploWTZcejw9ePiUxl/Bw3ftjLA4g7vFGXw7OSOy1RlpOOOYzpgJnH/RGSYstzi24QznL9Zcyj7NQWD06zxjwZcZCzFmTKfpxWqD7dOMbEwzsWGC/uo07XnNBRNzmvZqzd15zcWxrLnYb9dcri+AiHceUGcPCCaHB/j0wDas81/xwC8ht5ZXYckRY8ufPUEGIWpem8ggRPnJbFkLntGW2g9IkiFZBBWa9iPH0WqCJsON9CmCdB2xAac6XSNlRyCx5oRWMrjwmpNOPW39EluneA0Z2bY9ahOZ2TZ0sgIhCMyuKVVIQ/rMlCqkJRbMlNpCaUVSN5tXE/aEboRZUXaQQ70Qj8mfI0EGX2rRbCKDnuXRFEEmX9qPch/dTQCmXBeyNbOXRlNR/izCHDY/Hojg588OIXXSxZHgd9UnXQaESedEVB0fEASOz6mpPmSM3Gly0sgkmgCQ6vq01VY2v7cUIdqhE+16DTybwLPzImt8r8mz8yITZPLszGGpfYNnC8MDQQbPbvG2vwPNR8BvtbcHnlSmVm1StVUMbi0FrR/lD/hWokkh8ZEDi7fF7yFLvzDZWxjsLRL2diZdlAV9Sl5uiYXw/rhP6kZ9Q1IXHmj0Tao06htSZfalvE9TZfX/dZpqy3WTB8pj9O/zgO96A1o3kbtAOHLXBQQkt4iSm3GzQChuoigDnWo8gZu2ZvbnaJ6iDIoKBcNRofqoI6dQ4gYk8euNAgZYCcEBJllb5erWIgGjrXkfEQt77c2Gh4RXE4asrTJka+HXtXARV5zJfX4puZ9v5T7eynSpqTAT4TGdmUjXUuykpRopWZTXgZjIjbxyT/IKC6Y3lJZZlZZ93SorsSirKraIsmpiS1wop0UuxSGXTproM+WUpnIKehP7qhyGQIrS9PdTZ6WDBRJhkWxfWGQTRuwkjK7XTrBrFpnNcw/CJuZg9JawcU/CBkuVNzSOWTWOJRpHW8+fBEh+h4cAcQ8CRK0CRK/0m187rr6Rt+og8LmucVUHiyRIi7ca7/9MHRxX5hU6OxhINhTxoMybPUEQF/MMIYSLeS1Ip0FOMJ8tCCZBhvRBJGgwuzbaJEGIzeY1JorDJYIgxeEOggzF0Z6TjmDiJKTrUHlB0ZZh/hwwMilwnqrHyNwYzJ8N6TNIuPDcDYRsyOXPHiFEpSAWDjOaosf4jQw3tEieUMLI1BXCbdQEpHmkJ8jQPPmzJROa2qEGjIkM7dAiXUeIfpHO4BsNOZTpS2BmZZtx5LXj/8M2g5QPbNN/B9sMUj2wTf8dbDOw7YFthu9gm3W57thm+A62WR1V+FNp3bDNAmG2WRewIvKObRbomm1Cp8or4aatybbZNLdss2CYbVYfdeSGbZaxr9kmWAnMEiZZW2wbLUPYZl3zPuKJbZIhgVnCkLVVhmwtQ9mmlyU48lL942y+lam/lZZd7+CLhW2eyeIdDfwy91OmcUB8z6Pk6hMtZIMWdi6ICCCEpUzSdlUChLwmaUJPkrZFTXexxULSVqoQ5PpaDo4llHFjdJ4Ix7pjT39AmTy8HxsNDWOGMoZug9ST54k7usJXusLjYh4YkIYBfCGag7NlA8amsRGJcLZrviRXviRWA66YkdZ7La6CT0o6/AuMw2lWwzM0r+HjmkFI8jUJX5OjXLtmlgXzNR5fk5Nyu2YWCJtjSm4szwlmCPW56QhmCO3Vnp0mD9A6ENPFMH0yJt8jLFxTFqnEDFMhMaATZQqMGjp5xIjYDZk8or5YBSktwglMrwQDhCmGlxQZFGPX9T7A7/q0JNAIp4D+bKXouM2QdYyQxT8XyFX6UoF8rAJZnnl5l9E4FCW2VClLRPykSrloZ7tqZ7dqZzO0cw+aD/VIZRbVTC0/noIoDbU0nn6hVKlw2OSr0D5WoR1XoR2G0Mba+6FaWY+p3Irxw021+yTG15IOi2tAZIt+Y6vaZWktb+60oueUu+emXvpvKG8a9lTejIe5ErPsNjvY1Rlulf7m9RCny7T9PV/2MnxDIXNXTzlJy1nhS3zNSXQfgaYn/pSeTknswQPhns57uX9DjXOX6UwL5i5G9sAo3+s9kV0MMl25TleuT3/b4xBrJVSeNjSoE9K94PAyfoPgcKrvVJebUb5+eAQhkp8913cdig/xZon2dkMQ2nvJnyNBxt6LCKOgCgjaLKlPwewzNku01xSZJ7OmmCjBowqH8j71VhitRGtdhxvTDVie5Ht5PCLoBhixtcJoJVJociqiEYk8qW9fTfOUauR41DcZSsS+3oMBZO7BoB0dQNCODiYhlAjVx38ic+toEqyKTN7nxYERzORGrbr2mXyyxrLqBX+StIdFEJG03OLhJq1saaxPFbOq/AXxD2JVNcZPZBZ9a4IRbW2xds6XRtIJbWz1Y4EwMKathu0IIRtbm+Ck06StxgaCTHLZmN1A5jG40A9/1mcSl98d6YPL72MnChB0om1uBoAXquyH5erNMJuJbAbkMHVAQTUvBlbMgg36KRD9fKMus9LOuGwH48Nxy4k4BlzTYK55LtXYL5ZqFo2+rxo95/TiC/3AspDeVYf8WsljZVmNUt0cIluoFT00nS1VD7xHGXth6UX1w36x+rHo9/WMW2FH1FL5cLxbGfO1492/xL71mm5Zrnr6FO5SD+JKpsTAJTkvmiE9IIXfroxEjMy3S2YGhZH5fkvdVW5DxvstNVcEGdEi3ycg41EWyIjCyMwCUguNkZlTpFaGICPISc0kQUY0laqfM2nIPOGs+mnaZvUIjNnlDCHE5SUhtjXuLocj6tmxBrbkHPiP72VLbp8Bho8AI9/Qt2wJNEm+E2hiej3Ugk+ncC/Lwn6NNftb0nZ7/dnW4IXAfeMs7qGfKsZY+37h2O1SR+6K97M68oW8zU7Lak3bh/i6p3hRs72Ir2mNWuyd+Nq2OW+qyzeHdPUOc7sJtULbIWPVHh9CrV+NDm+pze1PCs1ms/cCMb9Px1V1/EkgvnMIdnuqQWPtiC2t8eGuHO3n/u6XD6uuW72Sv1WZvtB28UW2YkMPyWA+rirPImxFZvl6S4ogUw7VxQJqt9lTtXeUQKETKlKbUWotnbACcD1jQYtWwwfJrjZMGTdr3oBMGafnydPyJmC+vPffm0CLFoKnptks2VmWzmFkqhDhYiAzmirEakuQqWmcIKPhrWKzEbMnY5+HSEs8QrkxL6siyCwRm2mBtqft4KE04EaIsvtR3wcEVba3JIhxg1RoLwNB5mleJAC0PQnIhJFJHYQfdfI6oSlHt/GQVKRTh3I+28m6I+3wjrQQI2OrP9qRTmzN2OmdHenT6S3T/r/Zjv40V6+64DIr3/8sRix599PzXGzZcz5l6e/6pcx7R7/COWX3xG5Pif1pRxoO8J4qjyNu73acv5JupEWxL7l8TYvMvUj9zdinre/djl+wbCl+bet7TRCNIXy29X33wwYbnn7OI75hv3uPazUUkRHPrrY92TvMY7stQt5wDFGf1tsf7Mjv2OeGX15sd/vc7riarlyYwPZ65widuP/JMj/N3PGH3/Ds6hv2t2t6v6NFiYXHU3pfo0UXB/bESpXlyuUKeaJ+kQ+/7Nn1d5yxGcyreAgzmJk5K4I4WVIEmdvamEQpQpXwz0bs2D8rj3xvOj6b8vSzkZZCfzcMb8zv49hLgcgvQMavf6qZ6HAhpP5SGi9Rt1bsS1jEJ/n2OGhalJSmRYkQQtPGL23qzND2rkD7yFFSitLPpDdkFs19Zgr/A8T1jA8=###4592:XlxV32DM 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11d8eNq9m0uy3CoShjdzFyBACKgKb8URPERET9qDO3R47528M4Wko7IdPanDqV9AKkHwZaJaXvznN+mDeCnJ39/Vrt+//l39wl9LUrjW7qVdUoIBhSuzFqXUWWWqI0GRSu9VSSWx+wgSU6lSamQ0tzIvUnupJ765FdVSkoECH6DYaIiSbICP3FPsSkw97am53JMwDCRRpWRerZ4NXZOh3DlFGl5Sw0tq2Iel3xwDBczUiheFI6XcnC7NGalJJWhOy5AqWWmJAvemN52VzRGFp45Y8fzaXeWL5zUX2Ym0n3RDOvsD6shWB26/1LFLcUcfk219KWFBcaIoGiu5Nbem1sIiQJFt7LV7V1tKKfVQSyKXvoOY74mTesq3eqWU6tWSyKXv6SPdVx6yZn2ZHNrsIHlZ7ut7Gok2WmD9L8c3kUdKvTR8/PyviFt8GQWO+kdEub+Ylu9/1pVF8Mby/gHTEK5+/wccUP6uqWG4dNPQ4b684Su5FEkyJIU9SxxfLfJXAn/F3tBH0KWBkKZt+r/2FTy+VKfauyzSvmHJZ6laumssbVky+Cub+ow8X62z698/9Foa1qtCl8ZksSY3EXn+KpSrN9xXTN6AyYj7ivmr2pfy5a/2pc88xeB/u5T/Xb3OIRfxhaUm8rPeO9rzV3gkos9fYa/EkL9StU1iqQMXGF7cbHi5mZXnh+7tpPfpGUsVl59lVsCdrO80V7YXl8bmuRJf2+psmyw8XEwSvuxXk4Qv/jhJOFuOk4Qv4MQfaeFILaQZnA2X1DxZzdMrb9bxILp1O3a/qy7J7v6RnhvigF/JA3r2QBge0N0DPrQ+xNI80O8lT9k6s4oHuuTezRmTB7bJA8wePeBmD+zdA2J4oI+PYJ95ICxs8kDcugc8a31IrXsf4ugBLt/H6cDXy+nA+TQdOOvOOHhgnzwQdffA2j0AS1SzTn44B6I/eoAvvHvA7eMp2Hof5ugBwWYPxPdxOvDwnpwxFtDjdOD+MB3yki6ppaI7Qw5nDEPtJ86AXXxv22GaGHhDDstClL4hVwcOpTMBl9JgJW+ua6KQbdkCVsZWDRZE0lqHhfo0pG0wlSojRU6ZIEmICaRdRWMCeNYRwQFhSKKk1naTTfAGKZXT4BFLcOcVrjTgjmsXSXOJmWAcUkeaKgngdkUhMq11GCKtcLhO8hxsk8W4DjmwfBezpSiKQwrBy7KUto4wXoIbaHuD9azaiNLBE/63ROngya1dsJLtFtlzRmPrEG0inMpeyOiUh7GW9laC6Y9wCkFdvmZAHVi+4xYzVOUWa2lvpdQiAq2y2rQWMWhBZwpNS4K3lbR+lvZKLdh0S60NSdlE2IbLQ9PdAY9PedBcmS5iJ0q6LadKHUuUZJ3TRQlIqda5PCKbJh0hwB2BRVYG4MJDQztKz6DLY+VzyNE8mxaO6tpe3HsxOSMVv+fPxKTK5HZlYlI5mHTtTLqdMileQhtwshk4Mb6F8EcMajuD9q/Mu+FoY9ADlhIcVTOObs9xVM44yjqOUgzddGVOVv/yGUt/A0cbVa5VkjOWEgaNnUEPPPsBjpo9zLTTcJTZ0HF0c5rgKNliK2uymTUxbyzuS/xUhl/jp/kr+Gl2d42fcMemo0dcb/DTTujBzCV8VSIlJKpmEt2OzlivSdT8FRJVyl2TKAvAAI1EIdK4JtFt5jAxcxifsHyCL3b0gLomUfNXSNREeU2izFp3Nh0mEi1AeRqNVCLF00HMz4Zg769ItCzkFyRq/gaJcrU0akpPCaImRFpF6UjHYRIRZSCd2T1SKNK1fF0uXWBlknCqCaWNlMNkC4rCyiBbbqTDCiJbResM6uZiW7vdAdMZKIYog87Mboky0oJlvRnKYMey9jaFsGNZB4sTOGFHxK9JwvwqFMcjMfiVC82wggjaKkFGrxM0IsTcT6bBPCK1pHrJXhBivgan/UZf8NAhKgIejrivzIm5r1pSvWQJOypjUF+YHQdW1uHtoRO3C1VGOrWshk0hvKl6YjLbPgAROopE6VAJc88TpRMdjAfxxKDARms/y71irq0rVatEeNMu1IYOqQiGs+8GDCOqzFOs8GN+GltRjaI9UGWd78zBesTcoErZqVJdZzpphpMkPcMUvjfQZAeq/Jo9E7QO1qRJTfWegHKbgVLPQAl7/BVA8hkgxQSQhQ6/Sm0W8iypTWBHdceMcU5hup7CPDBjA0Q1Zzf1ATZdDTivM5XmJE83MpU0Q0mTlmFig0qL7ICGDwCSbpLS5xVBXiUXVd8lN7YTuqPmqJlntxnh9IxwhppTwvmNAkz3IXzRzBGed3P4BJtx5qtl9uEJhIfZ6L1YuDcLc1R0lYsUoVuowPvXBLjOFsqZANn7SVpSnKYl65JzSWpBD1YNNznDZbbUX4K7YLN5YSY1EsUkjOqhPExHhFHSSkYUlBkbiZ+sdIzi1tDWUJKLj5SQJdBRRnUoOGGF6xzOQz2uhPJIg/GyQk4tV9IRymRJqpyzkj1sZD2VlSS0kfFNOqKMDXgkuYoyNuCROCwK2oARKlmShvHGIG8TaJV5P0+nuGmwkmu+ZUdjEpXZzH5NPunN1yAmlXlH6NeAWfUaRKdS7uQa1q8ZnCozt49reL9m5Imtai5I15RDadhQyhxpPJEqEdrBvGgxqXlZZmkmptZbPfsMafq71/pCPLB1HtCEB44ZIZqi+TJ9cpnPACvczfnVOFf4/QQCdOFvDohc/POwHLq4O4Hxy5/HvXW4rs41xhHUH0STxVE5EQslEuS5ljvNEg7yygAWhb6UAZU8klDkgzOkYaRFU6etODKkcN+YZRMi91RyiBiRq4+aQpLMLvasdSB5cJxZDz2fHnwv9cx66mzETXXMW4s4lpHlYKI3WdLowfdST62nJnt49Mtt3JajVvZCbyOo/kwa/Ez+Dl7eZSfDo+wkbL3DzPOdXY8z8Q0Wtd/c2W/SMXx/lI4JZJOvRsN45RLexYCfFiShXYzFFhJWpe9iLG6aKH0XY1ExovRdDOpIrIxdDBSHlb6Aw4MfdbpR5oFK+TJmhW6zQuFZcYzYxBSx1Vjs4rRgCtPiHKaFHKYpvCE8OBrw09HAk9dTEteXsO1Jsl9Oyf5DzHYM9lqs1jaq6/z+hw9TfPww8ZhzVBdhG1vlOFqP4jpsY/PDtMxH6yjvP8VqMyan8A0nNMuUv8rEryP5jCx9lol3E9A/eRFEHczT601ufN3smXni6k2ds4T4dum9GhaJQzxFzRM3i+a6mTPz7hLXny2aD3PY4TjkyeCVGo0mp++WOmhqKdRXstKpnbpKwKKhuxf43KAcXhjvz/gnDf5bG0zbcCqlKxowV+OzBKUi1Rc8Gxd/y8OSN4PSAHQJunAhIB3tCBD3M6L0HUH49hZFVfqOIFyMROk7glgkaW3sCGJZDVYG0oMi0B0nV/SMrZf9juFhILcVsyHtzZWso1Sq8GwhSo9IhG9xYVV6PCO84ETp0RCYqLEyYilQiAUoEvND2XS3HQauD4lFOgq4wfadKD1IhyFZiNIDezHYtCg9SAcLA1ZG7h0UiZWRrweFo5lWhqSgLkiuSwYH6aCsWBlBOsyxiJURpMNgMKL0IF34JRCl5xZg0IkFI7cALsf9EJfHyh76jD1MZw/7GXssM3tML3vht2Un9ohfs4eZ2UO/P0soNwy5eQX2+N7rBBzyffaiwVfA4WfgiEfgaChxT+8NS47vFsCgmuUOONTy28Cxz8Dh3jfvuU7Acdx98kthl8CxxWfAYWbg0O/PUsin711GbW+BI9wCx8lroV9BEJ8h6HgCH7W5pQz/jDLC5DIxJ7AFexKa8fjlSXnMv/m4pIxt/5wy9C1luM8pY2xo+kAZeuxo+5EyRq2xvkIDfUvbkU4pgxMFU8ZKlEEZIy9SlHPKMJeUYS4pQx8pY1Sy9LYqZUSkU8pgRMGUIYmCKUMQ5Zwy7CVlWEoZslNE+dFPsX0fQxKRTiiDC6JgypBEGZThF0aUU8qovzA6oYyknFOG3i8pA1b3C8pICqYMQRRCGRtREGUwThREGXEhCqIMiW0jLs+UIZa8zE+UYRtlGHlNGWGfKUPcUcaDDEd9CfKWMvz1D3DsH5xVf31GXQ6kz39zI94PMCSlQi4w5Ovf1pyyR5zZI5wnO8Ri7B17RPWIPQpC0B19uWOPJ8kO+mYjWGru2CNuz9jDXf/qxf6dM2uwlN1hyL4/w5CTE2F2/esU+X4CJ/xo6XIHJ3u4hZMHPx05IZKTvEeFlJu8B1iq74gkyg+JpK5xl0Sy+w+JpDYIq2ouYSKpxmfJ6AOR2L1LbS3ODdTtr5+EZx0TiVp3ogwiUe3wsSqDSBT3RBlEwh3HCiISbokFiEi4XdEdUyKx3RmG0dvKRKKYQzomEiUCUQaR9Ff6qjKIRMlIlEEk3BqsICLhxEJCJK7fVjvALgPXhyQgHROJkowog0iUXokyiETxSJRBJBxNDUOIhNsNK4hIuBVophEi4XaMPXk5ARSJFUQkauNYQUSiDKmDiES1FE9VBpEothMFEYnDrRGXl7yHzevF4Wzc9XM49/85G7cqXp+NW/03zsatXq7Pxq1+ejb+P2KBl/U=###4332:XlxV32DM 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119ceNq1m0ly7DgOQC9TB+AgTlb0VRzBSRG16b+o5Y++e3MmIKaUmf5ZC9u0IFIgSAGPIOW+yNf+t3Ys//21Uc/LhY0Jmwv/c8LZkEoq/ZDff/FDxK+NEbb/lx9SfrHN+z1fPb7kFsn+17bR40tzs/+teG4hyaRONTjZ06VNgEvM50uClAcqQdtfBm8J5Zai0y8e/VF1Ym7LtQTWiTedVBBdJRblUMmmbipfu6vdk27/s7kYU4n9/g9zPHylO/dvzXiSMG5slQiZn5Ya/tabKhLLoGQTSSJYlih7dIk+vlIn929VJVYIWEeQXCdkiTwUktAkkTpLtMWSrJuiWWJkHBJSW1PJBrm1YrIpoVmiqm4OSbJusTzHaoEkPEtMkpT/pySPTBIFmys5Dg2XTZtER+2rNsgKWSJ4aU9D+7T2qKrtudGe6+0FXccoAFEZIxVMHSMNNc9jpIKvY4TskMdIRVEfFJBVebYqq61FqHeps5U6RjHUo2zv9KvYe0OSbG9Ba2sKSopuPJtu80e2j+hdTZNxb1bsxWMU03CW4nf5ndXfaDdGlhU7GVbadQcBomInw/IcE1bxpkt+zetMctXsJEJJmctuqw8iqE6el06W1phHkjyXnaizXEFJeWdcGXmrN1QnW93l0W2Op0vqnMi6l+knwVA1URmRdO+cLkd7by2p2llg3eQLmnF76eilbKNU+s6/yrw4QIvVsNrEbNhAOGxSu95kKx29lJtMpW+tU5PJgcmj+JDsVxn5nf3W8WXU5vbqzah13W85sv9Kb0J1jtCl0siHS+1+tItC9ZsUXjr2k3elkQzvOi7RPT0u6NpmMMU9phe7/e/hrTrXju3xUUKRLCIFLxVnHzW8ZMolAy/Z/PiDVe/Mqt/XrYvJyda/oslFqH9lVTe5wPa3yYe397Wd8han/4sH2H8ZVruVXgXk/F16L5eQR+PWwgv1gY+Qd2x9nNL7dAp5lFyNDyPuPD6MhPP4MBLP48NIGkUYCOUhz4GQJm9WNdWBjUCYdW6KxncCoRPai9UYoRvDadKfIVIXerAlizH0pTGoXIxB3WIMahZjUHs2hlqNEYcx+DSGHYrS94whlVmMcchujODlg5nBeTfG2QJn7HnIOvLQS68OPXq1TdaZ+CXe6lXzRhc4pT+BU+kRLfSX/iAnOkkrDyAkrUFApYRQQh5uiCyKdm2MSnBIJRgcpisvIhjitdVIMpGq2n9KJoYByMgSAIJWSFRnQh3AjyyZiAhiSX6pa9woBmklPUoWxBIY8Mo9MOCVyTVaLMGttNhKepQsDHgAF4pk4gIAlNxiQ5EyNr2oZ9GeAMXqbpTsUiBNVhfTJYgmZaeaVmnCqbIeSSbqGnkgyUBdAIzFIhAYNXoOBMaBeEUygbGFiQpyAUNr9cv9QRBaAT7lWgCCOxQMyURGbQ2SzOUDhMkAYRJBa0DQOmGsttahNfs3m81AQ3IGNEwu8YNL/L/IJQuMkP0SPuyfwode4SNFmBNsdFHyOZ07xiW6dwQZl3LHK42MNnPvKpiMu8TeGWVcyh1t3jN5UWiDI1ssgXcTCSiKRQT7frhyqXGS05VzqKlY48obc4E1aSXvRvDy4V/AmoVlIgrfySGSG9AIm3wNNOyfgoZeQcOcNDXHHQVQQAFmpYCR3NjWlAjfz0ozsSjN6KI0k4vSjJ3NmytsOMiTaV7VlebJAl1pvShtLs3LGo7F/sDiS8TjxFGy0nigPA6UOMKtHmv//X5DTP+04Sn+LakAFrXNBjX6suyxYwpttGY0LAWV8GpTEVALLoV5iQC8S5IT7c8cS9+kjUXazOWynB7aHJA50v8BSQanpDYIkKCVr5QOqgnW2NI41NzAkVRnPEihrFC606M6AHs0kkyESa1F1NqI8CkYHbDORKV0JwV1YOxPzXnU3Iz9xs4UhEdRb8bQIoEJGe+hZMbDxkmzzoi7wvbcU5OAuKst1A3ygkFGALzgLNQA8kLq6oG6OmAmqaCRCgMXvKgalHRJn1y8RHHLsm+iCTzSrxnFw4ji4UdRfAnd4Y2Uws9TCEvo9o/zBhehmy6huwZlHLrJfplI+KULY6UA6v1dABXmxwF0iZruB8kA4Qi7DqBsS1N6Ve+nK/Ularpny3NhZa4ocdQc1uMxjABk5tqZLerFJWpSv0RNGhZNUWyqb8hFBGc8jAiuWLyJ4HyN4HSN4Gx/YaGf3nTZg1O2VA1OaerV1GXn/6w4WtIK4VoIyrWyd6o3wSWsEAHek5xVuwf44Tp5ip8hDPvhOnBdBBduVmPJ8NBiLvaqZG43iOK3hjKpF00ZsF0iRESdIqNTcyUthEf30HHPDFUy9uRyfnVBNACevUqgz+dIMnx+mzRTMrcv/IgtuYRWgpojQ4BAYamAErgToR0y3lzaKok6BAKfOgKUzPDmhWtxQs25UeJEaq1Mq7QSTr9mnIgjThxvxYlTEEALv/hKQjqEP0pIqxFNTinmZ8tDe7c8vElI4wWheCWq4LCk1rD0JGmNV4l9aXhaEqJV4nFeJTJCxyrxtMyEJjiSV73JkZtir6scuQUeVJiXYuEp0KF1pX8pXe6epstVcbEX6XLDPpEuN8d2s4q11j7KEK9BWK1RzuyvLGjt3YL2ZIztOl1u2CfS5aa8Z/JioWxnZlkavFDGMVW+ElNPa2h+Csq45+o6pW7YB1LqQq0bBXDxK9yjZIY5bxScFsFkOVCBxp4/yAus1JjPVGBjmOvkv2GfSP5Xe+dsaC7B5H+LqaKIWMtH54nZS2qUDMxRt5mVw10uISLSQgMRSuWPUxhVAnb4x1KzSACK8HEGotYBqXylkGRgR/MBRZJKKJ+tpBim2NCWxubJBkRwH0QbCtqDC2E3wLBKBpqBVH02bEvKl2f2oppFg1P1SRU5VDHowIAamytqbq64esZFGlAJbskkI3KoJkAdO3ZkagfAgZU5wkUCDqx0UK5dgydCPIEilOBXSAXAYZOpckyDWFdjXJcgrLMji6/GrpBremskAUcqmEOScdQB5AzU2ElyHOf31dgvqrknbRhqbWScwE5SMULZNSpTqpXUKBm4k5SMJ8BrCnaSwB5INdHMqkzsrJK5Z+EcNivInUgDJXDPYqwnimRAbHJTpjRHY/KpNE5WPTqrOvKQVRGYNr58H0z/8KSEX8HUrmCqVjDVLx2akOuhiTc4clv3D8QJAxs/nqCxc6Q+0eYNNAZCFh4ACRQ/zxL4iKARE6L7KSE+P1BhHLkmRKs/QYj+iDdpGuGO19I0biVEuxKiWglRv3S2Qp7tQq9h0eoPwGJ6BL+mMqs/QWWWuPP8A1RmHX3Eo+bm4OrpoOojHm1Uxk/sho27XSOY1Z84zjpxIM/wFvjzoI4in8XttHNfB5/9bjUeQ0sWAWgRlsMnVoor97QSH6UNHber06C2yBEsMkV7GMqOBKZz/NExIr9diLjMiENZhAnDQAmgEhNgcwAWQDq+tjY3TEBGqUhgLgxLQP5s7DzUDoEslNiQZGahqvuYkokr1bt2CcKV6tZYH/7HyFTGCSCTHJbL7w08mlnfoy5BFGicGM1t+BjqpMoy5pMqARGUJ6EdNop0mEdKJ5NUySQwLTySDAIDZFT6WiiozMlW4qO0XZBRuQeQkXMKjgYkluS0s0jk7JoYxCLIIBZ6nV1byGVZAHYmoScmOafUIlj8X+LK06SZfYlNHmzMqMkmnz5bUbNrKKvWUmjsTQSCqbSb/Nkr/BOeJM3kXdIsTv5RcU2aLRwUVg6KKwcdKwf5xxkhzcxNeuwz8FOmnryCHzuifHp3Efw8zYXZl0jnwTaV2k9GsDdpsU+QTjLC3e5TiiSDAJ39N86PsDVPRK9mRLzJlH2IycRNpsw69Shhaq6O1D5Ij70AZCye5gC/+b7IfALImmVzSMmli68K8gtZI1Kelb0Ue4kTdBK07tONeoWuSr1Wir3E0QcOaTr2Lao8MeFpEx80kKDTJlZEVGmeKbEMS2ZezHuFJPPAC8CqYCBWSaIikkysqm/RlIDcV4FS3iRF7WaJSje2DoAbA2BPh4uFg3qCg71Sz5yfREmN6jamBGaRJJDgzcGeviulCywrgwmwTAgD+w2xtXN6s8hEXZhykTjlAlI7Eh0ThckYiZI+euY3o4TYCpYZpUN1QVHs24txFPn5CyZLyeA2ceJNASSINxtl/W4NPubNMuPhOebBc+WtgJku6aAOMBOnoA6QUec6ouo9GdUxjyQgS8hxX2eWUB8CTr6Ris7n9OtCQmWiVJMo6SBK9sJ+LVn3a+kKl3x/4bRPo1J+4s33PyB6Ez3VS+gpn35LhEnyKYKynx7v5W9v7J42dCGY3pz5/XliTpXjbJdfPGn6YLtq3c0l69kcsu5c0XXn6tF5p7Dm6vzpex999/HTR3DVktvdXDdPfM1n3B6pepNg1UsEK892ufsO6iMEa4m9OQFtnX+wkHlAsOwlgt1+egJanO1ibr6k+gjMGh/uYBZ8OQjmy/KxfN3uvT0hCM5Av5ForAEEWOD/1wGGpQ==###4548:XlxV32DM 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11c8eNq9W0uy3CoS3cxbAB/xu4reiiMASRFv0h54+MJ7b75JppDkutXVPamLdQQkCeKcTPDCjy8r4/q3YfsX+8p/j/z3p9w3Ux4sfLO58PuXFlGnkvjnX8vC3dcilF9/lN/fv9ITjzAbxJpL4Su3k3C57QvgMT2NR3shdZzry8gRbpRcf9hgK6IJIjJiKhIJwjOiC7IpgrCMqIowjCwqI0tFLEakz4gsyDFsD1/ZIQnyLEMbW/CwbUiIjbWSws7iMY/I7dUXA9qoL45qiUF49YURBQmRINkXhldfSIJkX+jmP0uQ7Au11X5IneILVfuJO0aKL5bk899B8j1XSh7SX4L982956OPLGS3Wv9KI9y+enPlXqpWWVWBpOUlfl9WSh5xe0Tb5YudreqQYfsTKI44ebXt5JPCjozySZYmatkLN5trfiBv0+dWddOvKI40fxfLI4Ee2PLL4kS6PHH5k0qPkE/ToyEOwxN6Dl0cbfiTyI02az6NK81hGkWa6jM66Orq00OrfIHErW64SlgbhUR57gfAoj9JBQMYKViwL2IwjrGua35gbza+yf+qUJgOXNU+0/uIyvZSfHl96OWSfabHdzLRgx3mmBdvPMy1YPM+0YBua6fyJlD0omydn87Zhnr8wT8JC7K3zsjiIpdxNlvIwWcrtZCnXYCk8SouDGF2WITX60N3ohV0aLc9GCzEZLeRktFgmowUHo699uk9TLpgY5rkr89xk3g7mTTYdk02STY6UfHKkiCdHxlxhoZaixenAvPAKpfXd7NSgGkO30OBrHNkaTDtnKRX2S9t+ocBqfIFSqUKmsKOIXEOtpTFCaaCyowydMQqO2FFG4QgC7CjjEggC7CgjMwQBdpQiCIwMdpTCe4wMdkzIgkaM2TENa3Sk6LCOMqxDIxwRXVIDliBAdDKqSBAgusSAniBAdMlEh5FBdAk5MAJEl2xn0E+UYHuaOJgSjvBie2KIOiWKICIj1cLFEIRnpE4WkwRhGdHVwh0j2fbEahXRGMm2JwqsiEQrrU5JYskKjWG1ecw/BVEYKR0tqjpWY6QYp1idDEuQPCBVp4kvBMlOqC4PhyBIdpyS1eUbQojLj6w9lFe50fStLOlnaA/ZtUfE2iPpA3+lC+xLukDPusDPusCALkiE3ba+kyhQIAq6Euj03zn/JAOIfkj7+08bxJUCiKAATqLg22KgMH8TA+tPx8t4ggrLfk+1YrGDteL2QLX2JarVM9X6mWrNpShQoewzN/wqFs2uLJ35VU8E1m06GyIuqEoRqlLe5pKmzMK6TTLNQrNJph2v22Qnm2bvidl7ws+cHybviaZK9m6heqB9IXegfZOo/Z72t9nCfX1PAYh4Nb+/kqVtAyo2l43hRw4xM+RYh5LD8+jWH2kF5+1EqUyAskF596n1EUmmdyJ5h8M7QJfpnY28w+AdIM70jsfvpH2zvTMoNL2z43fSrtveGWTaVnIeTi61kZZduC2oDiGyVF5KggBZKq8DQYAshdWCIECWwjKLkUGWwsYNI4Ms21ZRkFSqZqftt87dgiDEk2lAnCDAk8oLTxDgSRGkIwjwpHD7gZHBkyI4hZHBk1HV8RQt1edUVqY5cms5cE8/g2kWYBpFmIabiyh3O16Kcrc5yt3Pu0uJmAehUfbSwF4TZRmgrD/y1EvBa6Uowl4oYgWeWuZAs/VJmSjMTBTnsDT1mbZ4ps7b6QhLxaJk36xU3ElYSsPR7aVwdN47WZw2/BzaEhIqEk7f0aUSFxYWuqTcqNcz+ZzY7y6MSwbwJxZUgwWD/6+jTL6eufHSpvod6RuOWZbjyinubIDkt04Rc+pAbNNcZa4hhHLAZpGchvfSwIBPjoNSTfVvr4T35rQzRlQLb/rOSYwMykh7syUIEA7a6SsCdJX+vRME4sBkEmyzTJIdWARFBotiHB0CRsZWr/ziiYOAHvDeXBCglGQSRQYNBSaQcZgDAgPqYgoHA+2D70gbEC9mm03i5tBW73ZFOgJ6SD4NBAFKSUMlrQ0aElov2LgREQlvIjEbIqLUD6kzIqLkuJ0gPSJKX4k6XM2pJraJg20UsI2+ZBv83Ta2oWlWNhFQYxsSdsjvExCNqMwcUcV3Iyo7Z1rdektaYiKtylA04yqnjGtlOxJ9VbabqOxPIVeY2K1TGkRUQW08PuRU44gFFsvnnColL8pns9JmF0lL9g6faSEeMq0xRZY9gNnDQ/hn5vAvvBv+2TnT6qjR6ggPmdYtQPZasadIcJk5kM8cqOaoS8xsJK9j1vrN3yVdt4Bywsv3oq+43oWvl8GVFp3W8ozjPVMLRpCxZ2p+EGRI97rUM7L1c76+bUvrcaWhw4V0O0bGhq6U2VFzKI2klPMEGWkk07Nfxcc42vNcEWTQpwLuygimfSE9w5Uwt2tNmhvhoJa0o8HtdYFWJFARIZ3BlVBUeASNxzqIqH2kwwuDiBREPVs/HK1ExE+tjRRg6lcj4zC3q8MQZHB7XccDASmV5hsPFesO6ThGkO5QhyWtDd2heSBLbmgILSRCkPT5HYSLeV5DItYweFUDrxqaL7T4PPGnORoJlPYzOcT618Z2QrfjE7qfTlR2dKJm+fLReNn/kxXZr4pupf2UwQeIDMQ2jtR23GFofFLZaamHYKOHMlAzd7FDF3J0MbQ//24XburisNDFAl0k3dG7UN/twp+7EExCF2p0AYooLatvdPGrOSqtllKq5/JppvOpd9h3BOXP/0ea+1pJA6J7pc3WShuCSqWaal9i+TJUr5QvSrROe9GNoj/dpwgHg2Z9bTatq2qLR0i1JS29opl9AMi1AfR7ChLZku8ptEG2koOSx7cY2pz3FvEthqaooUkTe5Ot5KDkS+lH/snfpLelTf3l0s/4Kg18lfZS7dJEiny6LjCJV7ZefN5EzE4K1r90V8DMCtbNCtau025yp2jlm2mYk7IVNzuWudy53pG7TycM2zqJ4PvdUYUSMqm71I4Hdaw5Te1QCcmerhVMYncnujGtSXW/Qxv1gR06hcfh6ThliY/HKZOI9i9dVzCziHaziLZnZ+h7LjHqA1zSkh80WXYs43SEjdMRyLRKMalfNgcXc0TE43p3jsO305GIfrioIeQOS9GwpxSaejOFdgojzjFDmhhzz8BGfYCBlVb7Q1gS3faBsOThUEjsjznOxh03AsGoDwgERNt5U2gEnT8JKJpRdLe0nTFM24F1nZxdjGOP6vKOkNijUWVrDnO90F3HtPbGeZWFQ5+K4PjnIMgIWEbsUZARe+DYTO3kwuTQFNlRVT9kP/WSgRK5GYlUSnlnqBTljcYtFvlQWmwlAyWHJMWv9l30FqlK0X1g+dsm8RY6H0xrr50PanU6QPNQ3bbjxXqdBx/nleocqo9TNnQsWN5h8M44b0PHi/mdenSoyTUVpEyLO5AyRQeYuXY9VNTkKgvKNGeqJUnWka20C43WKyOK/hlcS94yTUPyCr84yE8HEuJbZjCCc7b6INZBCCs8ZCYqgnKpWhFkpAU8xOS+h6P9uBEibw+Rd8uQV8Lr7sUxgXCBjAhnlKUlCMooS0kQyI7E9qWXCLmvhHLgKKwpG0da4elniGILotj9OQVcRfHVDbx+45bPx5Nizg5/UzqflG/r/vpA8iLjG2e9rF/Xy29ngNX6IJ1PSeHnuP919XzM6jms57zxSUX/ST3rskPd5Za3hV0Q9pxb5uz28iabWZptc0I5rH/S2JWXbjS2+0QWRGnzoLH5Fu2Veplz1u72ItBTdnr2QE5rUw9s98LafSJJo0JwT4fA2/LaVai3E+B6fRCzWA1Tv+z3utZ9IrOk7PaUbg82Xh0MvKJrJZv9ch9wiP1a2dft/0bXuo8kvvTSU8X5K8GXaozfCDJOQEFYNQTYVDjDCAK8iNRB/uCxOpDO4jr4AMCT1pA6MP2+atnoENMP0m7IUDUaRFsuEVUD2riUsKoR0nT/5LWChe6ICEqlqv3ztwzFHYrJLSQiSGZa3CzS/XVJdoToftttqQ0i3Y8ijAzhCMP0m8Ktp6HuneEEGbGChsPvioxYAen+7F50+D0EW3X8EGx64QQBwYbji4yMMwckbbNHsbStu2VHsCpr+3xfL0TLOZjGvBUSGQznBAXBl+FgMVdkiHPNSR0kyUf0U5Z5iXTKCFpp76U8S5fRT3lnRD9CWjJL6PzHC437KjFQ6auV9l7KfaG4qO6rvS8aF8HBWh0yDnksQdDdGNDCuYRiqbSB6XoD5qxfHehX/4J+5fMVBjlfYdj/D1LWv3ulwbx8peETAvfhXsNTFvh/mf3tF/5upCzWwg+q1u5P/wstjFTXo6plx5wfnOmaxQ8JXH11BtcFrv2MwLX706WMbXlN4Pp3L2WYNy5lJL/Ye9lrPyJ7tTZP9z7kfuWXb8reh8sel5pOz4eZQ9Xaj6ja4MLDFf4lbFdq/3PZWsnXB4F7ffmyU8WN1rWf0LrNL4WpXKDSSvf/2lzsuJFWGULSqi2vKl/otXwkDvU42s0rHop+FONJHA7lne0kd0uGJHGB/hcBEBC6nww3AWHHTUYXTndNA0G6APwP+y2Q/w==###4624:XlxV32DM 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11f8eNqdW0mSpDAS/Mw8QAvaKq2/UmZoM5vL9KGPbf33CUkgRSAgybpkUXgCoQDCPZb8o9ZFfrEv8feX8s5/GSVe39ab178/atWWILIgtiLSA6L+/hI6mC9rwqts2b619q1Qt77Lx78/FalnrFsLD+WULgG0RCbxKa3fT7ltrX0r1K1va+sppUubkdqmL7Oo17dJqiCrUBhRrCC6mREJwgti2tkMRuQKSCzXUTYtG1K2ZAoZIG7a6UxfldlWZWJx1OJTRJD1oiCuWYfP16yDj3q6QJBiHXwAYg0jSDkbfADiWSJIsQA+6tn2m6i1aWez2taz6UiQcuMNb2fzBCl3yYhmNScIWG1VbCtNfaW2rdQK2Xwa8DHFp3Zp3l4XjJR7Z9t6wBByh8pKk222ZYKUlabi0fr/QLY7FNfmBIeM2+5QrleSRmDP1Tsu60HScozUJws+/v3zsNhiONdfC3z8/Z/MOn85o9fXf2RW6YsH//rPsvAMfmCv32AEfPv1X3iS4C98RRcbwGjYlRTetdZdGu/SdZfBu0LdZfEuW3c5vMu8Xr/touqVwd8IyhK+DY7G3851V8TfUmVXDQHwt96PDvECGXyCzMrlvGjf9nL7u+CvxHKUxwvOoe7S27fN9rde87fjZT0vr4Ioj30B2d/mYDA4vorb9ZdQPFe35y+9+HX3u2TgELmOawle/b0ovKv6WzG8q/pbcbzL110C76r+VhLvKv4uD12x+Z9XnrnJ6Kx3oxelz4yWR6OFmowWfDJaDKOPlgo5WSoEtTSIcsCCLRWMdfcKtlsqeeyW2t3SyTw3m2fbBVN3TWUPekExXGP2Cxom+wXddNY4LXpfKVren+1drSwG121hoYSnAuU92hcfFAtf3/DUlWDSbt9+FGbFXB/XgZSA6iutKFWOkdvpSnDcv1PCpC+ktD3L+yVbyPMLIJpZh5EaJr1stqz9im5fwaIaxBGEIjX8bwnSozsQfiRIZwS1mkSQHt2FlgojKFKvUWNkRHdYBu8LYiQeq8AdgnAQDzwTpAd+UCOcIJ20QY1YggyidytBkDiw9DqD6INqQJU6+/2TJepLnot7ePiCp5SNqO971A8o6tMXmSfeX+TDg8yTPIYcHuMx5PCYjy8yTyXmmmg2cnFnJBMekYybScbOJGNmkimB50AufCKXxiSEXBrfnJMLm8lFFnJxGz2sDJHMHg1YvexbvvGdbw4URJaQXjsL9V1gr5dAGDMRLVvg4hCSekzPPXBBmDrEdJavHgXB2cQ+bGYfFqeYzhKJ6WCpu6ZMsJSfWHpCmf4RZbqZMu1MmWamTH0wmrFryuQL12dGz5QpZ8rUMyfxa8oUM2Uqaik8D0dLB4OBperMUne0VPLZ0jRbGib3iik8CDGFByHZ8ZmwM8+jp5d1Sz2cqiYU5W/eCHWLMxCJbPdCmk+ohheWfsLw5IR/thNCUK5b5RslPSwxfjO+QGWrQRD6SigPfByVG8+0E8Aly6FL0AhHaaxU3BOkk7xUMhKkk7xckiVIp3YpvMDIoHYp1hUjg9oBWdCKiysAWllbVt5XzBhdVq6GRINwRP1S7XphQzr1S7UkgnTql0oEgnTqBxMdRgb1A4ItxIldELrfLbfbXm5cvyUrwhH/wy3JBOn8D7ZzgnT+h1sSCNL5HyxMGBn8Dwi2EPE/IBI9ae2WtJwdoHGhFeeKgCiM9FyxPEkMIyPPl0oJgvQ8H25gIkjP8+Gme4KMPD8IgxDi8lzUi3KxrIurLwkfQ72Erl4iyVn5JiuoimHHiLXrEjarFyJo0iRokpwFDX99ki2HWciYR0JGz0Jmvc6W2Sxo+JNs+ahiiubxCjx+oyES7xpCMXOjIdJEHZsqYLN2IHIizMzMZjmRaYpo9HojJxLvckJBBPooA/eznDCP5ISe5cRKjW4P/JWcWOMyjE43ckLMJC2fZOCThuDYPMhAxJ4DFUNxkU1bTZBRmLNZEmSkbm2xO4JzROHtDpXbiKud2hqCjGTLaEeQkaBBvoMQUmWTmqwIF/p6ka0iKH0cRba2os4724vSLhRowXVUaat1I3gDkjGCEj7pOFlRJwn4X6MLoQgN/1uC9AgN/xuC9Ai9vSoDGRF6VKorQiqN5BhUaVTBF3dDRFcQoUfUjj1qp+uofQzVLXortj2cfA7GYg7Z1/H5bQqp58gb5shr5xRSPIq4skdcmlXSbFJdlCrvssk9dVzmpFDNOac+5InHbNLP2WSoTFBXeMUEARzTk4hlZoIp/Kerm7sHeDHTwF3Mb0+euqq62ribp3kiMf9tcqjnaO7naG6JOSK7fJccmofJ4fIomqs55eJzyqXflVbB6HSXJ5pneaKYyV5MqmvLJonRcr7xYr7xJZukRse7tM58mtYJsydg9Zmi7bYelJUgIdF5hhHUHkPBXwkstbcXakcIY3griAmjRGh68bBdaMTrQdANQX24TsMNGX24oPYuWLn1TYVXh7bEZ/NtwyPJcMVeePxVH3VyaM332CLQoThVBEihq+L8ki0RIygnXRLDCMpjlSRnQ7mv4pIgI19efCIIahX39nLzPCroWvpYoCKw9wjBGgMW5JGXkMYAZMEIylOVIAjKbdWiCYLyYSYIMnLoJWSC7LqtKM5cTsd9Ies4yDp1ss4/SrGSvOTts0LxW95WM2/rmaTNXDP+QTVYPWo1ionKG7u/LQzz91QeZirPd1T+hL9j5W+Zb/g7mt43W+DB+SST45c67bQa/J7K23OpL9K3de1UvghDqJyaNXf2+JxgbgXiz0q/wGfxht25Tz1Xg/f6mt31o27pMrO7ej2pAsuj0eGG3bkfbo3pht3jZLRkd+z+hNLT0VJ/Q+nch08rtanzXHHCRlblKo3n4IkzCEd8sJnSEE8YUBlnyUGja+p2wt2QTkmAOIJ0SoJslJgwqA+O2Sm/vBiHFFb1gyLpZrq8YmTQCyAeIyiFdTkQBHVaGSPI6M62d3Ugo6ybukAoCPF5brYL5FlSS3ae+G8IBDhoQb5AJAxJ6d4mLoEOaTPNupiqCFZgUmMEp9IyEWSk0sopgoxUWhl6TJdmW+jdEVobGEWIsqBRAYD/6VJHBcBlRRAkUHvTuSG7eoF3yrQWgf6y8DHIPu9kH9l7so9prqdOZbyzBnHiHzSILW4QX+mAk2LqOusA82j0qAR3k7dZINEmMmhxdcrv5SwK2CwK+CwKRBcF5W9of21o13QJK4PDfNKdQvBz6zhfK4T4QlNLornXidiCplBrG2MyxtzpBeU6XSz6Ri+EufJ7UkQ9aSTnHzSSt/ToUAXYmcOxXq0WcXS8E74TfnNY9fzvMnpH3FKKy0bdqJOoeh1E5fVGnZw4YZ3ViXk0y6WPTnCzE1J3ghxOGAbyz5zQeOyyWO3ZbbF6Uj1qVj1iVj1yVj3L62SIqnhgLgZl2z3QS+kijS6y+tQD8kZNreuY8ovyIzW16SM2C6xTNZWuPBDnoTXZPaCGB/rLC2z5gQfKKNUgG0mSaDfq/lmSGbadhoDay1YbbYUYVMbbAtMIqiO5EJUqUp82VZGyaLW+ftWnvG/6sRnb5nf9rJyYsZlDWAlpHFlAF3Db8zOQMTTnR7MjSyzg0ER4MbJNfxcb9y3ftyKeCIdlq75sv00iNxkk6bXQiN1aCwH9WnV4vV5r2/J9K5KBdiMDuhYeaBe6F/XLu026OCITZAztdTVbt0gXB+sad9Vcye6quZLpPJ9FEpjOABrTJRzEZSKOWxhsi3Vkihp8viAIT3/rPtZYzoe1VRelGzJmvIFCCNJFKVxH9OtYMk+POj/lGNL5oRagzo/ppUTYIjKylwXbG4Jm+nEB0hjaFTILQVBXyCiC4K4Qxwgqga6RYWTIbNxJMgbJ7FK8rQcdZxS3WkRRpfx6RvFEjSY5q1H203FF/sm44hM1+qy17x7NKIqfNphGVeptKSrdlaLeDybuVSp7UKpe8nA3VCCTfDaYGO5KUYdG0w9mFPNhiC74m6ECmcSnM4pP9N+zSQJ36IhEcdd7sunHg4nLT3tP4lyl5CohLhtOo2l333DKdyWpB9OIW7VKHlQYufv1ob+aRpSJfziNuEW+y7aV/bTGtZ2wFvojo9OIzfg6tufVYRpR904I3Iu9jQMn2Ebf9M7jFcfTiNongozuih69moqMjoy2niCji8OWjBHU+WGLwQjpFgm0YjqNqMfpBF1W7U5psyIcl630/vOvDRmdFJ05QUb3RYdMkNGxQV2eKEiXB3WGoiACye9luBpy9klKuHH9liSE42lEHSRBxjSiToogYxpRO0aQs2nEipxOI1bkdBqxGHwxjVjC//k0YkXQNKKOC0bQNKLOmiBjGlGvnCBjGlGbTJChanyOCCEuz5tOyWc6hXedImadcjPPcqiLvRk9ROLkrSKx89yhviuVPRl5MY8UyaOS2MORF/G+T5Yf/IDidOTFP/oBRag6pQbXyx9QjDrCqU65GXk5FLneTDwicUI5KZq7X00w+UyR2FlG6bvi1JNpGHNQJInfKRK3/FiRPKscPZuGWY5Gsztx4uSzX02wJ7+aOJmGEeHJryYO0zDwTOi7X00w8blOyXc6xYnPdcogy3zQKbEH9agPOqUGiP8Dkmhweg==###4448:XlxV32DM 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11e4eNq1m0mO5LgOhi/TB9AsOQPvKgV4kIDedC16Wai7P2qiSMt2RhayN5mK+G2ZlGzqE+n48Fa+foTNvX7/q1brPsSH+vU/G471w1uRFZsVHSRVjM2KKYpXVNFrVjQodlu3qqjFi4+wKVBWAYo5hAbFZsXFjxC2V26l3spHt5YqrR8h7PlaWRk9GrlrkJaYL7a6QLv0e++ytnKXraVK60f+A+eFY0fz9w8d9wSSsVVaieRtvphXVVmYkj3zsoyG40oeWxeqYpiSx9YeeTS2GLtX2eAyTkoXf+HzUKq/PhUTHF7IgefVbn+s5axkiFTs9nHJivcrU1RWinVOSqbIrPjSmz6YIrJS7ha9RKrke8LHercsnir5nvDHXn090KNYffXHUn2NRGm+HqH6umF3W/dV+ioFIlVfra6KZ0q+km1D55iSfbWyKitTsq9WVI8kVYqvpj0Z7JziK/z5/XtTqyoTATcc/Pn1j04wiYv32+svnWz8kDAkfxkj85yL10/wCI5+/Q39wn84BFwz8jhe8JUVVbKSSrFIinwVdflK06/kC/o+Qu2g3Lj581o/R0cPXfLZ0dOv9vJVoF+58tVCv/L5GkmVPuHeLdcIxQ/4bNv39qCnJOglONpxkvkrL+vRvp3l9/o/7LXXctPB51XUz1s7bjOjKyVKV1szYKNOpr1IvknMgA3cWFQdmkUd5b9Rtnyx2S3kS+e+xK86g+CGeeV5dR/KQKDM36YPZ/fYJ1YdpwlVYrubUCX284QqKc4TqgSM3M/8EOQe8l0mc8tys2wzaz1Ut0odGq2KdGC3NhRlIH/mJ485/jt7vs+XOIbnpl/DSfRci+4m+lJuL+ax3GaP3eSx9CePlZzNieixHh6vaI38oseLmuY6ueGxv5hrrftcnz1XcvJcafS8u3vyUU0+poA+4oirKPD69qs+irOPSqjho7vycTnfz1re3s/qmHxEaT9PqTm7q4RGd+1w16Ep61fchSVu70tFntyKMGVBIAtwvrPoAlzvtK6wBXgLfV3MTwddgO3qNZHIAmzXsDFlLMDL7pkyFuBN8HNwASaL6SoTW0xrTOgKW0y3kLC7yBfT+ph3iS6mq0tMGYvpGgxTcDEFmLRMGYvpwJCijMXUbEngeJvqEcThrOxpaXxXPIJpfbVJ6U01mqY2f5S/eXCRVPI9T7jWrjowBVnYrlYyJd8UWxsm3lvmwq2O7ULPaTC5qXonGeJZnRFYasqNmTztb7A1DLslTleALbdoaylsGQq1LXjUiynGyQS9S5cFs0uXraWwZSh6E5gvxwyYV37d6XM1wNauRjMFYRiGfWMKAnQLSkMZ0F1DclcIqUP4SAU44Xb+kGKA1o6gdRDQ+jsYT8CE0wdjlGSRUTqYoCRenVHwK4jogCee4gkEJMpi6XidSKUwRyOVE6EwaEkILfhVfHV+eeUByI+Hv16vpPG4Jpqk2Xql1xk6++LEljCHS9h5xVZqWrGV5eE9LeFs3lhqwDx1Zd7SzcNeC/ByS/fZ0mNabLWYMEOl1+W6W+8kwy21w1KJ5u1wvqgw6kVq/Rx1+gHOQ1t2Ut8LlVY+Ij+LJbLvdkep7eHqUdAv6NpsB9FJoNFWKqZgcNJWG6ZgQNPmSEzBIKiFYdcZAQgUS5WxuQdFEbeyvxgQdju6W7hbqRiyR6KTR1xbIZmCYUFbYshCQ4m2SjMFww+YaKgyFnxQNqoUt4wvkWQLebo2uAO2EUgODCSR7djOuyq+A/p073K71QAr1D3TB/ENTA+X0PcQHcQ3QDRcwt0zbBDfwLBtum64MYjv4MY6UPlmyS3KgGYXhkgUHOsEVkUxAIOTqESojTBOOanSTLlob7rR9JxxoFuH3XqKTm2MukLRA06yKLmbFF2xsjBBcbK1HLY8S9HVOe898hRdvR16l4VcSpet5bDlCc3ARmWJ+XmR+aGU5KmM+FSmyzwKXTvyMefUSpTntaNnW+ScUlFz4oVlWcSLZlXYZcJrSrSsc6LFzYmW5TrRgokV4ydYucy1ZDK54xg5cUzOzJC0ip6Z44Zf3si0vDbrC9P66ywKjOM+UOBgWRSGAuKYUECkCQVarkXOCRU1p11YjiUyfgGj5Zz6OYbRCyZAFp4AYRbKMFko19lCN+dEls9yImDhEwBGcLtv5s0yAyCnvOschr0HQD0DoOTm1Uf4DgDX/AS3WT+eADA9AeAb6Qdi07/NpryhyC2+W9sPIhHyGqtBU5C8lNcLU0ZZZRRPijIoipQLinJZVqm9jS2rx3Nyi1YswOydSLT6sGySKaNiEbBaUJWx4fJOoSJ5iUGvgp6EAJUT5StVBnSBYtmFxj6xhoSqWJaSgJOoDbTGUJkblcu6RFVGKmXUJaqC6Rf4LJgyUjb10e/GkaQIyfwXhdYEFnYO1gRyb5r1hkkR621iyqhKeGeY0pMvgD+hEMOJVlNfFwdW/be0GpJ+yEB/C63Wu/Qu5fsttBpSeMi4fgut1um6y3J+C63i41xaN7SaJUqrdQKrou9oNUvXtFpOqlxaLtqbYTSXW1rNGqXVOkZduaHV3Pc1rRYrC5kWJ1srYGthtFrnvPfIadVG2mUh09JlawVsLZxWV59PlDrTqsanMgh8KiV/Ki+Z0b3+sDgXPmFGWx/eU+VNvCYwtHOCS92DYZrB8JgTW3FObG1zYmsfia2fi1waNnrzQGCHHQUZgMl7AnOvP6xKhU8JbN/nOtwoGdnluCqS6Vt4UXPKaq6MKcNtqFusU0lHdBt0QrjW1qINYcKsbcasZc6zzeiq/Gx0qBbGbmF5Om5AECwM3UKv4j0I1oQetzDOFqbZwrnE2jBxwsPV9wU528zw0JbEnc4SDHheputBFPqs3dgxAo8Zb9XYErbHMQqPGdWGte/eyzF5JCEeyoomHsEAWgzQBqbm25LAlnJqYwpJyvvIlJGUX/umvimDEetN3xUGo7YEUHQOFrLmHOFfW8IRHgMntmMoCQ+cAy8ZAmIVoSgE9DCuN2XU2TA/0ZTxcgyBw6IgUO6NDcsWoE+QzrHeqcJG8UN9xBHpJUZ6RSP9zbZdv6ZKhH197W2Jp6LEQ8y+KEbEOWanc8zuL1f4OYyHUxjPA2QetqU5D94fd78/bEvt/LjPkfy5yv5UreBRtM3q3WY1LON1B1IOeKtaMacoWmlCzhV1NYctfQpbJFzBqLbbt5hPIggoK1MwRsnU9xxNwW1uG4Ku0OAH3e30pPE0g6KoMp5hmXqkahfCEAjnbKgYGo7AuJ0pGI7gHMEUDEftdusKDUdggqQnjS2rTP0dsqqMLSsoll2oR1FA+VhKFXKHxVaNkmNQ+OxbWnLkuciaeOS5SDHlIlviUc7pyU9ykTnVCVzp6W4P/u9XnLnOnLnPnBlmzvQzZ2ZEOAU3eZ+TVHNE01NEq3Gvvgr2XFvtUekzBE1vIWi8DmcqlkX9LnlpxVWZ9SJ5OaexxEwvco4MYnsreXnw4msslOFv0NmKy+KruKsNt4ylmHlZzrysTrx8RujlZGnZxt2tFlaZxyo2D/rXSUwzLxF2jrbyujYcy174bl2wSr9VxdbyHXa9WBeu2DV9si5s6kj7XNAmt+xYwbZ3Cto98t1VyK1SX62QR6z65harkFfjs5RbVYLIVqrMh8KzVK8y5w5a8dwLQXRaPPdYF67KKJ5775kyiudeKaaQ4rmVVGHF84UqrHiuice8eH4MSXO3SvHcS0l0Wjz3WjNlFM99CEwZxXPf39FqCi2es3NY8TxSheR+963PVg45zfY8cW1KXEpEJ+wNU6KZgrwOU+KYgowPUyKZgrxO3mcoytgxkPcZijJeTCfvM2SD65TURBd5WyCHf5LNJW8YFGVkgGFgmTLyvDAZnimY54UJVEzBl+xg0gVTRg563w6isCFPlVPK+yATp+jOKUndc8oRZ07RM6fItzgl3dVMrzjlxCf2zZfV3VM+bIITNe28Km5cp8js65veAdvf2HZ1mvmMU46ZU1LhFK2fOMXK9zhln1YqKeYia3qLU47PiqxgtHriFCseOYXzyeXqf5Xqc0+pvpN57glO7JtwYubV/+ENavf6g7ftorZPnGLf4xR1vLV/lW9xyrRLKYDDjZZPnGLSlzmlRL5bTrFf5xR8tS63GKdU46skT5ySMKpriws6dICcYojOOSUwhXLKxhTKKY4pl5yi7R2naHvHKdqcOCUNyXG3GqdYonNO8UyhnLIzhXLKwpRLTtHujlO045yCb5nnkIO2E3TUROec4plCOWVlCuUUy5RLTtHqjlO0uuGUbPAdp2h9xylanzglUIVxCuuNcYpjCuUUdh3KKUkShQ154RSt9GU+xWA+xcyc8gAn7/xWTtz9Vu6RSPbXQ7FuIpL13be67t/meoCT88/lKJncYMjDL+WeynTpqUxHcQRm0qgH9jDaPLLHA3C88XM5ET/7uRyYJx8ow2j9HmXMJTJSW5woY/2DV7rgkXjKhhgV3wMO9w5w3P5OS51tekqBGHU8osXDb8ceanZXb+/PNKnieZ7FA08Yrb7IEy1C3f4yQO1f5InWIcTE0qI80YwvkhEnnlARz+qLV+mgb7K9JDrlCbc7puSF9/8j5XWf###4484:XlxV32DM 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fa0eNq1m0uSpDoSRTfzFqD/J7DeyjPTD7OedA5q+Kz23pIAyR2BgojqnmRmcQJwpIB7r/Ba/jaaLb9/cWn8i7zYP/9iiZqXlmzJhFaSCCI0E2Uq8QkRkomMhRBhIBGyELYRtA93mQidCQtJHISRF09hXcqH1pcmqZ5NOsC15MvfOtlKbEKEFbJVGCkitBBdiQ6IkELUVmGEpNSuk9yIhKTUrmPYCGtXtb4EjaYgu6E2sIzuO+UflQhI6olEPZEMBJJaXP5RJ4MhUi5IbtNkIiJlELYhlwpVUAcu/6hDLgFBQ74uv397TgzPH6DhpV6M/PMfvqr1ZbUJy198lelFU1z+EiLvYDxZ/p2vK386I2XyGCSy5E11yNomXjZJAjbFWDdRuCnVTeVCy28O0bosPzrqDUW7/w7wHKHsndBpbd2ktk8nDZGryMBNqm6ycJPOm/LXtB7A7JXlrzr4yMrKRxQ80FquNt9EcBOtm+oBfozdD+jI9tvDS13LdRgv4CZfN4FLY6Qe0Cv4qVg3watcU92Eissj6fNcl4OVj5J/tinNFyuWMtHqRSVXdaLXlxL5YvaZZvE004yk80wzSs4zzYg/zzQj4W6mGclX8VO+kYX9LpWKsdLYK5UXlfLzd5JRP1ZqW6Xn8qhr5bVN9cuBKqUaVZrvmXFMV3VUKhK7qpQflR7lnUePiWH0mBzKY7yVd6ppGD1GWK+JXtVkz6PH4jB6LAzzzOlYaRorXYeBzNN1mvJCBS4afDlFq9TnQ5G0jRpZ94vfnxLlYdxG4eKAso8CaQcMTw74az9gfn7Wv8onsprZqmZb8ZsiHCg/uOpT16m2l9ifuvUAh9ApDnh9Xud7txKnESki7Tc5iw6RItJebbogESki7avKME8gqSLtRSXOQFJF2vONwCvehC4/v7bL6sVJfFnrprgC8O2ydu9hFSLQe3hEgPcIFpHuPZiTkADvwVyABHqP2F2J6ELYp0RqwLH38IgA7xESItB7WEQuvQcVd96DilvvwW+9B5V33oNK7D18hAR6j7giAr2HQwR6D4MI8B7oaGjIq/eQXpfxo+4lswHp3iM275HuvUdM33qP9dZ7FD9z4z3+0HCES8PxY3YhuDEcshmOw2Uc1gK6jR/j972xlVgfWQk/Wok4Wolcf3m4+omVEPmeeGQlwrdWIt5biXQWaDexEiKP/cxK/KF/8O/8g/SmHEtd+wcmnD/Kyw8Y5B+ufYNqQ3U3PsU0oALqjaeuzUIuwF0VYM/jwskjZxBGZ5CGIWLxPIN24gxEfpZ+5Ax+7QfclMEitc6jsT+n6rjU51QWQ7ahCBAQ6qzTHJEm1NIZgUgT6ixbeJ8m1FmnLSRdqPfvSiWGHMXV5/g+iwcCcivdkQd30uRWuiNi76TJLbMc79PklhkBSwBymw1B9ySuGwLbfY4AHIkq8B/uFOg9IkBUjUKkiypzCRIgqsyhfYCoQp9jkajmy+oleHxZu8+RgAPJy15BIwJkMgVEgLQGh0iXY+hzPJJw6HM8kP1ybzu2iarIP7qopiaqKxDVH013tXsrruTuIXjoLht1F4krreLqrgK9GwN9aPqKIvpJas0otXaUWnUrtXf6eiuq6Syqh86qMdjrUWfrubxUSkyUNLgeIF34SEm3nH4tVWR4DpNRqsiKlUIpNlHS4FqslERMQrkbNd8P4kH1IB7UjPpqR31VJ3lzYqavQTzS1ztRPZ2KzZQ08H6qeK+ke1Qmo7jSIZxjJQ1XqwFZGlxTmlwgkjTHE0BQ0ryjiEBJWxHpkmaO5/hOuqQpTSCBkuaaQDpxkjTHAEKSxikiQNK0QwRIGhWIdElzCZEuafkLf4xc+epvxeWnVkUyAQTULP+bItLULO+zItLULP+bINLUjHGLjtbVjPEjhW2kq9n+RNnIMab52b4hBhBQq1ycR6SpVSYBkaZWmUREmlrlshMkXa1y2WgfrFblPqC+RMDY1Wo91GolYwR8kvvSO0/87UKzGnXJLk8ioB51yUBdEnpYa5ZsWFi+C4htE1nusmJa77NiHGUtzbLiXUBks4AY12lAfJIKw9uoQ4YgQWdRMKavV5XVKGB2eRIQ9Shg5ixg+n6BOatKW7TXMowLzHhBGQvNcKvA+Ng2sdukzei5UjnVP/koSbI0lrXOkuT7+Ehm8THGz+NjX0klp/h4RIw6GDg+AqWTOD5KigjQ2p7QnERaa/mKCNDa1UCCtFY3os9aKwFCWiscIkBrWUKka60SDJGutcp6SEB8lNJCAldrXQ+OtCcw0oMlAxwHS4UIDJYWERgsBSLXwZLeBkt6GyzJOVj2QMfwZe3BkgOOg6VEBAZLhwgMlgaR62DJboMlw1Jt6t1FQwmWfbXWkibV9LtgOV21HYLl+n8IlhcCrkYBN2/WcLGA00HA07o8eaU8CjhUbT4PpZMkCuOnnel0iLqHuvg/XMgd4md8Hz8tmcXPCN5e/3n8vFBvNaq3ebu8q7SbvB6OQV8VPao3H9WbLk9eGo/qjcrb7uO7N8XerFfl2TuXBqLrJK9ehVRm1KFnpSSggcyTiEjXza34g0CxzSmDwp26CDLHODocEM7gEeliy12LZ9oh1XKMQQKVLjhEujoalRBpipovNSDSVVhpeDQo3YxrBsvub29zCDPwcEBS+bE0WW8qIFgwuFnUDsVsW/mtBGRURTkiTUyZ1gGRJsDMrgoRkJ974rUEhW4YeS0UJBSTLRIxqdpyRSVd+DKJiIBcaxIiIAtbggjIz5YBAkL3b89WZy/6qixtasknfVV0uXnZc6jlQ2ksQvou4+pRIt23EhkuM+5X2XZTyztpxAkYvxIt77reNF7F5f3C7uXb0unCLm68Wuspb8OwXp+9LV3vvgqH2D5VVo9bb1Y/W9gV+mEu1qOyum+V1b/Lxfmm8rPGKx2mjVcf5mI6U9ZTeuanpi1ctJt1Zmn/rDNr7MC7WjWmH64a33VmrZ7OArT+MEAfz8PbziztPuzM2g9YukvKX6gzayu+Ik9PnVlHcKzTsveklAPswVK0vtzCUWcWlYiAziyuEemdWSIxRHpnFpEUEtCZRYSFBHRmEcHBFePOLNWRx5dVg6WIFHDUmUUEIqAzq3V4bwR0ZjGFyFVXeCWXXeGVwKyvWgWetdrzxLUpoYCjrE8VIiDrc4NIz/oicUSuOrMquezMquSyM6sUfNOZVZTgujOrEtiZxTQksDOrfysqASmfSET6yoCIDBHQmaXgPmjIt65wVr8Vg3thzb2IzzqzyJPOLPAe+ZvF+p71B/cSmnt5kurV8iDNb84Dp3ky9GthN/OhTzkcyBcr9Z/4lKBmPsV83dVF0pOuLvBa+l2D+BrkzLIY/cyyuHtHdb9WcRX78VvnfM+omTnJJuiRObmI/eObht2JXFW6+5aJI8mVypkjoeaRI+F0+XId/ztHEsTMkRj1aa/49oy7dSTZ2n7YK84OKa1/YUcS2iM/iJMjYaTt1ZqqywGa/GnAsSMJiEBHkhCBjsQictUrXsllr3gll73ipWDsSBhtSOHL2h2JARw7Eo8IdCQrItCRRESuesUruewVrwQ5EtdmqzUul4lrU8IBx47EIAIdiUMEOhKJyKUjCfLOkQR550iCuHUkQd05kqBOjsRCghwJOhpyJBoR6EjQeZAjgUdDQ745ElpfcQ2OhDdHIj/7f2p01jNw0St+0dn2gSO5aBuftbVN3z4M5oQ86hXgT8zJBysnk+WSp96Ds3rb3noP5r/9z2lknfUOXHSUX7TEYclkYeY9mPvUe1w0l8/64KYvIlCldHVTG8Kf2RD2aI1EPrEhp/Ls1HuwT1dDJksgn7uMPM9+5jKY/dRlbM+te5dBP3UZ9HjXX/+CLmMvvioa8yeX0bxCmYBdjssBmqRJwLHLcIhAlxEQgS5DIwJdBoMEuQx0HuQyBLhi7DJobMjhy9pdhgIcuwyLCHQZERHoMjwi0GWgoyGXsUICXQZr/iP/dTikfIo2JZAjl9G9VSXAZQiOCF3+C7fgdAU=###4400:XlxV32DM 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1118eNrNm0uS5CgShi8zB+ANCllfpcwAgdlspha9bKu7Dy+BO0jKiOyytt5kKvSHkAOS++cO8UMHvf/6k4sQXuTF/vqDM+ZfWpL9hw4qK8wiRcisyKooqHCblMNXhXfFvQQ9TJa2KvkuHe2i9KcoEirlRqLcSHIGlWJc+pMVKZBCs0KLQglSWFZY6epxIIVnhSeFeQYVHnzcaw80ifuvX05qpdMXqH3JF/V//Y9HFV+b3sT+Hx5leNGo9v8IQePLOLL/1DR/e/9v6l/6n76iTB6LsKdTQoJTgedTksBvHeUUrQ1IBqVYJA4boHu63WHrt4OCks7fDhqeMuWUgadUObXBU1s6ZQS8MLJ8qhiT/x9QkllSsM1I8yldu2A07EJIXfhptjo8xpL634EuMVKudgI2GMop2b4NexljkZCxrpxCFvl9T5OY5oe88lfJX3XekkFiz7OpXvRIj0I+G19KHH062TFNIyN+nkZGyTyNjLi7aWTkmKeRkTws+bHLX++Pm8SWHqelgYTTUr3501JOZhuo7jb0U+UJQOZQtZhDN2QOZ1QsA5ee+GZOOu4DF3k3h88Dx0QfuNlSphZLGe+WzuYxOpvHZ/MYYcO8cGXeNpvH6TKvLPZ5nc3jZBlI5peBTE/PZGm+QGBL5bD06Ob51BQJ9cakXJ7aOep7k91qaTA7ru4G0yCcjivdJV1cXCvtDjQd5Rb2H+n1q47fgUuLb02vWPGggiCFZkVV3xqQwrJSW/MbUnhWzBQSkgk1JKQ3v1rfHX96wpD1cYozudEcMpKvmGJTVnLISC6jBgYK2qzGq2KIJAdSsvGa1sBgkZKN1zlkML611sorWcNMiZvMMIuUHGZCvg/TfENKDjMhh8D2Wp9K6W+KjnaKjtmE0lWhp+iYldLVGs8ki8jsPIPyqGZrZEIP6oyb41TScwaiMI2GQmVE4fQ5QGVE4fTZIKVHYSk3iZQehaXUuLUehZt/PpU2PMmJpQCs2GbKO05feoRf2cOvRuH3jIeHX+OhXIOfatEThUq7hsqth8p9GHTtoo3pTkfpA7lo5HSqi8bBRN06HWpX7711pwM8TZpN1d7uYihAtDRWFCoD62hUBirjqUmKREp/DVL490jpr0G6hiClvwZt6E4FvAbJQ0afrUvo+AKYpc55DvwSszBAhTmWFEq6Z6n8wDQg0b7+Nx6gxv5zY/WBEkyWA5dIMn+D49nvIScSec4+N7SjhF8gYQ3QxNaIEWrESDdyc8QAzBKJ6CTADGIW3GrcHygEhihh/dKzEUyZEb1n2ikUTCvr9KbOtvucStwkb00enbpYGA1aOBmuTUZhgZ+Ceo5m49ef4iBnGMz3SlckT2hKQlLvnZTSMRDL0mcHlBZ8yuWO1Ss5bFP7HBR8vbK5/jI7wE9lKXSpNBryo10kojYgAS+qmM+PGe8K3WvLMKuJnoF7wqwmetj3PDr7j/TAVmsOKKXx2n+Uv7/+9Kq2V3zv2SjPryALJSpT/0rzTcZLqNtLmAF4vIRTjhPomuOQ/Z1XlO9vpDs5Oepva8orr9y8X928vXfz+u9nRDC3acnRkhHxnhHhvAklR5HcJkefZER+zojOlMpMeZPjZDseMiIR7QU5X2REcQliJKwZkV+zEbK/kxw5DNFk8w+RV8TtCvfXyOvWyGvvI6/+Rt6U3iT9kDfJ4UvfzZtgBnRjKZNrYrJaythsqXpIoaQQjynUB3kTOxbzauKFzMvZFZ5yt+ZN4DntoY+7d/Km08fdJWJS8E8TsXCmMuUIJVrV+OyF81GVakxgPph+lWoxqDTQ0jdNKNBhVlUHfCgjE9PaIGVkb5pxpIyMj4gIFZBOEaGhAlIwIhjoMc7rwtYljbtV8jpNGdBBvsU1F0gZOZo2G1JGXqelQkpPg5KJqDWQOhHhoDLSLead6rPVsSBPXJ+SAHSAtbw+1UPpKJxsl0jp+Jz6S5ByVX0tymX1tSiX1dds8E31Nfv86+prUUD1VSsOFVB9TUiOlMEpWlCkDE7p2V1TQPXVaaCgIS/VVxZLsXchEtPTv/BAJOTDqusEKe8VYD8lkm3/feVau8IJ+QhO5AonbIUT/j6cHB1OJl5RK5S0BtdyLYsl9bmFk42+Byfhw3LtxCufVW6T0fYJTjbybTjZ9t9X37WT0co91XcFf49T2EecolZOESunyNlS+1TqFewzTlkptaELXfnkshJ9zLO/PXGKiZ9ySvV8twVjQT/llHium5UjyCnN+CKlI8wp3J9SmoAW0HMDLSgqpYAOOUU5h5TBKepcjWvK4BRlDFIAp5zF3aogTtmggjiFgx5jTuHDBIe7VThFaQ10yClq25AyOEWd66lNGZyivEcK5BQDFcQpqDXIKZr02RpTkiauT4kFOuQU5SJSBqeoQJEyOEUZj5TBKUQcUAGcQjqiFgVwykDHbDDilAFm2f1DThkwVxTAKeogUAGcoiJDyuAUtR1IGZyiNLIAcoqmQEFD3jglXFZOts4pceWUN+CkVVD+MThRH5VLtreIRC5EUleJ8VoyWdaSK7dcriVnSHleSz5J5KZyMpHIV8vKfi2iuFxEYdw/cQp/5pR34CT8HjhJlronOOHfhxP1UeVk+5pIwlPlRLRi5JdEolYi4WvIZ+vi80PIF7OlT5UT0dYuvlp8ZuFp8Xkika/WodcHIS9N4wfBPnEK+5xTwlM9ReSVug85JfTgEaZ6SjW+LHtyO3GK7jEi9HpKbqAHRQ90xCmeIgVwSuBIgZwSkHJVTynKZT2lKJf1lGww5hQ9BkPjbjVOOYCOOSUiBXBKFEgBnHIwpFzVU4pyWU8pCuSUXuHI3udc408Td06JZkBHnOI1UiCnbEgBnLIJpFzuZuPubjcbd3e72ZLBd7vZuL/bzcb9xCkGKohTLFIAp+DWIKcYjhTAKZwCBQ155RRTK5LZbUFOsX2Fh3y9m+2fqasYiC53C/vv1VfU/g7NmEua+alj2/vG6oKpaduYKuXMe+NOiHlnzaeuDKF15wQ1AUJNX3/e2IHXoaWM+mlLmzMj+oh/TY3ElL0h0+62M1hsti86sWPwUvhkQdhJw8UD6ThPLsbl22WYdfPaFfSYL6Gnsuw0LqGPixvjYrvN9MNxIdsDV7l4OS58ZtWZ9d5ZcJJzX83S12h6X/3YFNB9EZcf9bV5uZttB5s9/v6+gzacecdSPqo7AUzdNGWLp5ApIubHPe8c+KNM8Hlk+pGDmwuYPbPm0iTc1KWCRUqP2O2FGkqP8syxgJROBsKFM8oXq1y+hpXwwc+qR70GxHJukDLif2qjDwQXaDecO4NRU8ZuOHOu9ZQjuBuuvQmncXVPQ3LB1ToG2xvROlmH7jQifBpTi2wY2+FUOJDSSaJ51qzkI7jJI9mkunXytO4wdVQpkMqoVmAQPm7geSi7MFrvzkMzDh3erJHO2N6saXdMQaJufUHPmXHnc9aOTD9ycGNMslSAJuv8V9o053plNQRuKHGdyktz+aIUk+pAejBcgGDamz6UTjDp0SBIGQQz9i8WZdBVUgJUBl2lSd5QayddJU/g6s8IxMukP4N3XOcd+i/nnbv6zMQ7Xy0e6bGB8Z5oJFu3uXxRpLna3kI76nzNN83FfmcZ6YNKzQNG2UPcYxSDhRFn/zUYVX37DUbp34JRtqSC6hqjWKkT1HtIHxBG3VWHJoz6aulKX+5RTD2P96Ckfwso2ZKRqWtQYkK4q57zpYYj3qo2XWzZ4Tc9Ly7zBpv078Cm1HMz9xxsABXCXvV8++bS2neqV82d34Cd/h1gx6xtMbAMByjgMK0OqIyiD4ioeZZARAUxOr+zNR7nZ7gd5W+3IwZjtLQaXVd4sVxXj/J17YghhuyBtRxBXGjPdTXfTsQaDZAAK0orA1I6eUorFFI6eQK+LBYDvuxbROo1gCI3QlBrnX2TI+KncjDMiu78FUQ5gqyYvkvBVZA9rcTK4D7bf9dRlU6ygO3KbAy2Y+7cBF+vAeSpqUCtdfJsIacqAvNlh/ZyBPmyOeTzKvjjCcsdUsZPMexBkDIAbGQURQGYtSkKFfBjECvRNeDHIJZp9GaMrdaDfUuHKuWW2WqH+Sk9Dxlm3/QSKNRsr8ymz/iGvZqbPm9AaU+5a9DZn8t8q2u6LS9Up9viFH39/adIfwZB+k6Q7O/+/nPBxmWj5LkOeP/7z8Nf4aJfcdF2XHxgREiSEx7OTFhX6b6z5bms4V3jX3xroc6v+BeuF+qkDfqR8sJ7lPf4+88F7dyKduHL33/a8FC+Spb2OC8m7rpeUnQrf9nbn6cC6IJohsyL4RGOwiMcLVxA929uYhazWf6RXI63yIWTd9bdLvYxs/gFucAsOQ8hCH3p8wAOj32Z5kgB/o9hpTvc9PkACvJ/pnr2/wOu7ISb###4484:XlxV32DM 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116ceNqtm1uSpaoShiezByB3XMaeSkWAYMR+Of3Qjx0995NchExRl6urX6os/xITUPIzyfz1r3JbfBk1LV9WheX3T+W0f00v/mtXGCjaZkVQhYNiWFa2lSgiKbwoESkirhtIUoHEvZiatL4MnPyyXibFzhYr2Tifr9G2NRdlucbEoniLlXSNiTqbIB1RWFJMVgxVeFJqV8l9UodMnLMSFVJKh0xwZeS6ZKoJ8CMp3BElmaDKyEVNlGSCKiMHzWMlmQA/smKQUk1gqUd87mOa7BYuGbfm0VYBN5cVkczmTuLmypimGfrtuRbZOvmy8OPX/8Smt9ds5rD8IzYVX3wSyz9Ssu1l/bT8ABvgv5f/oF34Df+i7UuyyBY4JRU+JdIpNZX/VgxJIWSJ41MxnxK4gWmB2wVbGghz+g1/u/r3iv/Vpasjuf2cT+ny33kwm7RmyeJTOp+a8SmTbr/x3IDlIt/e5i7C33mg4bcmrWzQCrwt6NSm8inc1U3kU2tpwK6l4TmWv91U/vb1xl7W36hzfErDbb2uEu7c5rOEzdrArB8zLwM382K55Cqf8EqzdMvUxvSrTDn0RC7pQdAvts4yPwjbS6vJ7U8CD4cngE/b8QngbLp6Avjkj08An9bjE8AneCh+pEc/tZCf1HSBopaqaqnlbjeUh/bI8ojH2tcBy2P7Q7JVkLH4DYMxxXEwQh8M0Qcj7PcQ03EwmBsHY74cDDYOBtPDYDBzHAw5DkZsg+H7YLRZE+yzwXCbHm6x6XoLLqXd76G5bPcQV93kbOgmH7vJ1bGbarTBtm6urZuwXOwmqE+7mUZS41vwifdumjbna2z3mPcJ3ru7d0CUbrIqke6Oj7iYjt0dhjwtwHt3Q++ubqa4T7r7k4uZVVeQ3vzuCkCxDivdfch1S0uj+vVvfgdTY8u/+Qlsh6of6nL4lX9mPBDN01c/CwtUURRSKjh4nl29qA6rNAj9WL5gDUvG+N07Zyn9PyghM4WQ5E6NKcBtM6Ik4PGFHARVEvD45GdlmATqNAxt7fN+pNqRzkdfsJgX+2SzTxX7YFnPXngL+F6Ihspjvl9Tugs+oQBMxGaYdTejHql2pPPRV/qRB7cPhqYkFwNRGsmB6QIphOSUmslFHSa3VROlw6Setv2BmiLhqLp8lQ7L2mHwtsUIjqQyflxk8tEGtYcob4eYpjTK445RpVEevAikNcSZxklyTePM6oL4/iIUs4MtZjMkZbOBWsqNIm6uAxv87fEbh8iwOKKudDIs/npXMBnCRYFc1OFUTytRdjiF5c9PaYDY/JLwo/NfbPwn3/Nfwbdv8F+cRv5jC+K9WNfaTHQHkqsWUaKzI9GBV0YER5iMLzvUtVPJIsp3ldwI37HGd0dow/hF+W2HND0iHUG5dUQ5GGeYMSaviY1LFXcvIf0dsa3fJbY4EttG3BlYyo+uteMUWBq6a6U4depaKyiduVZmR2ByB1smO9iCaEapMzcvjkMEpHM0i/NlYB01so5oFh7M0nf0oeQtfWCOOJq1DmaJEwQLI4KRSfwJFu7rZLIVe2k4oZBEXLuSRGluFX2QF6W5YviwZUTpIQHvV6x0x1lntSiWeKw6srtEAhZiIwpyjZoqzZeBTxBEaf6Pa0uuycaVRdyzdg28CDSO0IIPScLBB88YUVDAQluidPc3z5IoyGHNE1a6k6urSFEk9SPltd0l7Hw8m4iCQhkt/FEUFP6QmijNK3EjyX0QinrNsNJQFBA58nQRW+Gd4VP3V1vzVwr5qwdxiuHN2f0TG73Zm5BF2LLLMjhkcQxVzGOowi2DYzPLELXQy42PA0chzeCXFEfRCurr3jm2Gsuojm02ODoBTkmMfor4vDD6vHj0ebsbrG1nR7fA/OaH7yoeoUT7BJeb+CgeUf3VNHo1NvrAd6GJQL/bYn5pr+IGSvATo0/iBvPokt1gNDOj0Xq58YjUUj7CQ3ODTMlTS8XR0uLNTr109ZDv3CG7Mk8czevuEMxjZ+bNg3lhGEg+zj7fRkvXZum5eXn9k9Q89HCyZpOH66cS1DP5Myi1U5cGWCls6y8fG1S9vz2qsT5p8GdtMH2GpKP0H+lLMnuJuC/e+ahIsFolad1D1HkCsjMoDcAtQRdKeaQjRy/UvBGlOXqhAidKc/RCmUCU5ujFpBhWuqMXk5yxkjwCLENFEajHaSjaB/e6R9HzY0+6tWVD9Ip0hAhC7ZsQVWmIIFQURGmIINTKiNIQAUy0WOmIAAq5T+6WLFMSmm2wuOy2p6+3fUo00hFBwJQ4ojSCAAsDURpBwJRYojSCAAvJNZ0gQFFY6d+1oHD0pJUpKR/DILUnKQFJDzKBIrHSaUAov2KlEwQ8Y5EojTpgAmeiNFKBSTdEaXQDQx6QQoZ8q+zhT9gDnrWdPfQNe4gn7BHZ8mfbJX/IHuvIHm5kD7M8+b5OTuiAIdNy/NQuYEGJRIxEou4+tTHKXMDJB1snw0c2jLcXk403GCKjf4QhhSbeYsjoiB7ukFAMAaPDDYbI6P4YQ/yIIW7EELM8+TDXB3bi4ZZI/DMi4aPLZ6PLV6PL13ff6phqqNHrLae4W075YPNgMCQep3y9IRIJ7/zHROJviWT+nEg6O3hCJNV4kPLRgUi6a1676/bd/QWkEyJxjCiYSCRRMJFsREFEIolCiMRghRAJRz0+EEk3O9BuVSKJSCdEMk9EwUSiiIKJRBAFE4nECiESjxVMJK7P1m57nrh9SvbciKwTInEzURCRhJUoiEisIUonEu4iVhCRcKexgoiE7+GbbDAhEo66FQmRcKewgolk9VjBRLJPcFUQkewZL1VBRGI0URCRONwaGfJMJGLKPnIgEtaIxFwTSdjuovYn0ZCLNSnjyDv2WEf2sCN7zI/iHuY0tn9kD/WIPZ6F+fnIHuwtexyYQ40xk9MMjnCawZEWZncXGOnb8feBkXAX9j8JjFw5ooQj1CPOdyGQvo1+zx5+NM+O7DE/CoGYd5sC8PqIG/aQQTxjD/2IPZ7tE8iRPcTRaH7DHjLwR+xxYI5p3BQ4zWGIb3MYIrd3MRKpPySSusZdEYkM7EMiqQ3mVdWwQ4yE9y91eyCSufkJw9taDA00IolIp0TCiYKJRBEFEYmdiNKJhHuiICLhzmIFEQlyf2AwJZK5uRgjaLcqkWxIp0TCiIKJRBMFE4kkSicS5GyNIESCHLQRlEhii3TA6tNoyvYpWZFOiWQiCiYSQRQcI4lEOY2RJOU8RpKU8xgJt5cxEljzL2IkSSFEwrFCiIRcQ2IkG1FwjCQQBRFJxLaRId9KPoHPMRKX8glcJxLeiMSe5hMQDClkQjEkLn89j+CGNQbAmHHywNVeC0UIAhqFPShoTHeggfMJxJhPIMe9lYs4x4E53mWLhpxi4OW4cd9TDAI72ZXOrEFDHWEEi3X5S6kF/ja1IExn++ZDasENRQzoMB8NuAlbgAE9bdDaRxspByiYRppgI01coMPBUn/NC2CpPskXGfdUxBjK4sNriiMYB5p4kwlJ4xo/Fdry9/6QdeAdknDWgfeaKDjrgCpnCYBF6VkHvQwgKyhdz+3B5aJ0Ryv91jbIfTjkI3iPJJyP4P1ElJ6PUN7DrvTcOu9WoqB8vI1jpTtSlMOXle5I4e+WqeAPmQreMySRMond61UFZSpYTxSUqbA6ovRMBYcm/JCp4Ps8HDMVPEcSKaDoGQT+kKmgPVGaP+RWKqL0TAXLDFZw/cQs8+TpVD+hu78Tzd/N1/lzF3HAs12AswyE7VtFE+tfzESYxy9ye1s/8cZblo/3t9UV51sCH1RXiPHD+2TX4GnCXvy09qKsZJeZfEHdZvJdRZFPthPOshrC24KLOReDXRRcuJ7U8I2CC59H0Fy68f4BvobPogZ/nDgxj1EDexyXcF174XqGyjdqL3wOYl9mK678WbbiCUro5UllxvsdkDkn0V1UZjgh/0Jlhs+5BZfgsrKzh2NMBonXuSrPciS3tzGP4gQu6jacUN+v20A1GOm1rNUW6Ulsh1s7BGtIDUbHkqzhmonqvqqCCy3gGWxYAhNBEMypDUkk8bPnAWblrJ4idaDUTiT796NtP0oW9noKMGP/4sz/0+spwIqWROkNye23IWIrOqBxL4jlCOp854JsOaoesZooCB5N4ybHKLnNG1EQ7TmGFIKILs92G6Jc15GHqB5t+1Eaol7rUd/FfYhI+YhvNbNpjEgNRlnGylXhWIMRkYRrMHyrJMj9QnQ5rzPpMSo37jjoGC037vm23tC63Z5A7A2p6DBmJUqvAva+8y2JZ1Q30xWU0Yo+Jtyx0LY/eP5Y7BGQhIs9bCA9wtW5s8cKrmuWEluH6naN27DS4z0A34L0CBciR6KgWg+dh46tsFKx2FlVNlZ1N/kr09UyepYwW9mUjwR7Epu53Tgyd7W9d0kr9q7M9xjMeVIR8ixNZbrYKjpnziF39nS36CR3dluebBwBF/0fuTOMZg==###4348:XlxV32DM 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10e4eNrFW8uy7KgR/Jn5AN6PVsyvOIKXIrzxXcxyYv7dgBBUCUmHHjvsxT23W9lCBUKVmQXyLFH/IR+d/5E/f+O7TB9Bk9j+xXelPlTysJWj+0eJnW+/CUH3j2Fx+6fmLp+TMWU+gpG05UNC5kP5f0kg5AskKTwU6yEGDlFSD3H4q33bfvEU9tLoXz5H6uZI44jU30TKyTVSqnuk/ZDdrkFTNwVNzRy06kHDSKXSaYp0V2ekMbgzUplH4oyUn5Few2NiCo/JKTympvAYm8aU8e0SabhGyggbkdoxpqJHaq9jyuI0ppzOQe9T0JzMQac56HCdCDZ/EjhoMGVdj9Tnpkg6xpTs7TZFXQ8IGk1t8A9ORHkG2J+/16ch9237R/lTEQERITOS/2RE+h0ikmQk/ylIogihBaEVMQEhrCCsIsohhBeEZ4RZ3q5T71W9jvElAqYoQwgtiCqI1h4hrCC6trZLhPCCmIzk7xEgZbQLVIJr430EZz9lAHN0sbbHbYLtlfExXlTEuI6kY0yNaOdQiNRz6ijk7x4ita8yHohFSOmranGj69S+anogASGlr7pdJwGk9bXe1hychh2qYft6I0Li4BbVk44ByTPrmCoMjFKZXWWU7AHJDrk2v2I4kAiROr/SMb+0h0idX0lVJBKElPmVdEUsaq3Or2QqIi1CyvxK9ugWAwjqVtr+yinC1H7T8JEfmv4sD9n+sdrJ7Xj0Sn5vj5u/JluayDUx0DQlBpr4NTHQODEEjVNioLEwhG7Pcx7r9n+AbYdyVkIR1HSfFDxUk2fS8FBlgGTgocoAycJDmU1+mcZ7eX4DaC+9MqgLO6uHImygJMU8leGvygjlOQwPkXqI1QyWn8rjch6OxV4b8gIeSvUQ7Pse6iEFabZezqPQfT2Egso3xHOi1YtYEFF9KxYg118pmMy6wU90QcKsGyKiixy0fNENIso13eCXdIOadYObdYOZgi6yBBKz8eFFQngj7oiZT8QstxU1QWc1wd/UBI605ocnCeFzqlmREJzMkc5z4hAaWELQOdJ5ThRVgeeEeJEQIoovJUQbhcIb5ROkz3atDNVPiD6tIOAsTO4cIZDcA0IguSuEDHI/ZlNFfLgQnpbwJEB43CAEcLsnHjQHmJU5RhHSGZypYBDSGZwZFRHSGTyz1t5HTmLWOnVHRQ7WqsNbWav0isE2ofowKMKhPnKb42oKt1kJnjkO7iMieOYUDBQQPHMwUETwZyCtc5DgUWuQ4EEIEhE8cwEEDyUscxIiUMIGhCAJqxECJKxlCAESVhOEnBI2p4jjWcyqKUuIOCSE6hIiAgnxS9NG6EhKxDRLCT5JiTgSxJkVHkRDc1qpWVYsB9wsB9SSHCiMcJEBbJYBdJIBu5xkwKEM9NGVg/uhHPhl7DFMxpE7ORCX5IC/yoFTIbS2qwbYvIiMvBB/yVktyWvtXog/zBxKtpeCwcM9vFJ8m2DqgeJD6jZWJoEo/rZicWf+1RKJW2xUd29fSFwYdqc8ZhIXMzXymRpn5cEGNU58yK6RmhcSF4beRTrXAdISiYc50jhFeglPz3QtR3ikxxSW6Lo1WFxP+XRwcn6gah6jAzKQX7kIDCGdX1lQCiDNRJWWDzriIvKOW0SYQWmAoDMvrrIcPEgnP/G4NlEbHUzGJTPocp2FuRQOIZ2FuSQKIYCFuUXd7lKEiyQQ0uUL8LUVGdoBeOGKQL3RrXeZAYAqQcWgIoMqmTcMIZ0qmTIKIZ0qM1N6hHRV0dLIiRwyKTMFLhHV4RmCoqXGjNRP7SRaILprCiBAyjkLwJMAKdNdGYgMUs6IREgn5cweASGdlPM5HiGDlHk2B4evV5mABynrTspp9vUTA4/sfXXwib45+B9tu51tu5ttu555OizxtJp5mqzw9J1dl7NdZ9tE2fwbyp54Ov1d257jzekzhDfbbvyrbZ+8enq66aeNfzDoOKUH/+bKjVtz5XZWFG525XomdL9E6ArbRsb0G6Ezs0bobInQ6VKNX8xeV16DVm/czvS33L5S2F9y5cX04znh3ly5sd+58jPHPeqGPJ7f6YbWYDE55RPUDS34yhDBYZsfmOtndWdZGjjlwclIFQfCIjM5QcgQI/IUBg2BrBwRMlg5G3eIAFZmzkBksDJwvSVgKEByt0bYGndrP1RPADhQPVls7AiBlp8jBAgUThEyRM1wuBUBQmi44oqAMkBQod+tXs0vN67fEgFwIBKyPrQIAUV27hEyfLtICiHD6wOhFDyqDwChFPxl0YCBmXZZaRghhIeVrIrAMgBzEIFlABEQAsoAxCBklAFElAgZK1lBRYCgId+LIlGsFnXih39AkcB0PbLDIsFyzf1gbGy2yVLNnd3W3B+q6RMXx87F2y9bp8yWe/ha1TXODhsdvqvq3iy3sqWqrrilZ3XUrS6Zk/RIbToj5Vr3SM0Ug5msfIeaV07nBevNlw8sZWz3ypoRxFJPBeKXhWXQ0z8Uq9sK+J+/1z6XWfx7DQYkW8Vqi+M3pP+mJ1cRXES/of03PTW3+8/Kby51WNULhfVTGZjtH3neVMh2yCZUWx4+ojYIkuJQ/g3piXS4hYb05Du8R0N6wh5O5kBGIh2u5EBG8g3qyOSVys6h4MeDXkWu/tCPHg+6PR90SlA18KzUYX/gtsfi3VjLm5xAmJ1AnqEjoHsxahy/KW/diFH3KJHAutAkO/0sOw3URXiMBSQWdP8FpCl0lwWkqdbZE4EuF91mATkHTQ0BeQpNNAG4rayyVA8+WUx33mmmFywmfbaYUzo7DSm/uM6f3Kab3aZacptmdpu2z7GJneRSKfiGnfiKxSxM9z+tCnNi9Zuv3MV3vnJ/9JV03idE5n1CJFwW+ax6s5g7X7OYbraYasli3mwYs7dsmx8U8+Yrk1zzlWrJV97oArnkK+lleI1+85VJ/F9rxvnuyzczmR+gL83kkc0ezWTi35pJYvo6n1G4CH0EXyErL2ayW7VyA85lytxAcy6aWIBDM6lPr9GQYSa1IQgZZlJ3j3cg0EwyiCAz6SCCzKQAPcZm0o2wDe5WNZOaOoBDM6l5QMgwk9pShAwzqWVCCDSTMA5sJneIQDM5hsKOlWMrxy0JAIdm8pjlAxlmUhuOkGEmNUsIGWYSLDZbhcwkWKC26rJAzcFMu6xqj7D105qy1chMakUhAsyktgIhw0xqviNkmElNI0KAmfQcIGjI92PbGmN3a86+q0z385rzoT2+WHO+VLrZZdn5okyKWLmsRF+UqmrQTyvReta1bq5w05UNaTcr0W33GZ0Xp7+tcKdZfsRZfuxv8uOm2L156elLhZsJNag+xJf16f3L9elLkZvNe9z5RbKgnVN1ij6tWvu9e2wxhPJYtb74h1vZdLNqrWe34XAVlpO3IgVVY/d6fuSfxQhf2np2s2rNZjFCfypy56D9ixihamxkj+lFjMwTgKUpaE7exMhNvfsSqXuRETTz03cyQjrTEmt9CkCSlI5phPTEKl3fNX0gPRm3J+lE4HIm0yrBk0bWZ65vHq/IYApmOUMX6nyQZ/9ZKCz3DqiRjHCEDAWTmAJIKyGWAT23fRHXcYfL89Yb2Chcd+5L8BUZQkZqi84Z4kcauiOkC6b2UB8IqqHk4DVAUPD7EQcDwUNxlBtVsFGwZd6gRuGWecMMQsaWecMCQrpgyiH0zXG5G3DRnCuBkLFobhhEYDkhnyThheAuPGVhc0Op5O84hK5u8neCkFMRlUxKC5QVosh/BtmHTvb+luzvSjW3u9H3mc7jTOd0hc5v9phNdK5uy1RPNW+6VPPmK7Te1rKvEuFpy/lNNcFvf3PtOtyvXUsX95kkB7PzvuQqQ0LMfl+HIysvoxH/08toOaz4zN05LH0T1it332w+e3nd7L5S6NvT87htfA9r28b50gKDXOLuOeiiA1DQlLztIE9+CA73XSEhbH9zrTr+sFad+ST1HcaU4G3YbEcI2IZNCUDQO1bZBMGT0DZshMBXrEYSpQTtHnd7QMjYPQ62P+epArc/O6EhArduJ4+QsXXbm3NTd3lMoSIwFrc2OMaP4anIeC0Lpn6Kd6nb8526+uBBVnDGI6T75IzgczqZ5e8BIYPMXEwAwWQ2tpSXuAGZaeXhKACNMwTYgQyZ5fr2tAMB0ixGhAA5F3eAIGnm+ruAtUedT8vTVTXRZIRj58awYIRf3+NacL+NVPmFQZ/o0m3frOroW7p83of9H26+pv+tMnuYfe7+g8813L1U3L3v3kxL+3dfwFowt3dva/tLUq/T7tncsjVz67ZvltL0TwSZ07h9NbdxzdyK581Q3+3D5tfwzKuNDWs2Ni2+TPVvADhc2w==###4516:XlxV32DM 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f68eNrNm0uO3DYQhi+TA/AhvqaRqwQQX0A28SJLw3dPkZLIKlHiqMcO4M24rX/ELpJS/R+LHP7BPv6QWduPhSf5ev1tlMCXWL0k0aUYX69vJq5wCaSk8G+v5beTxpdcvWTwJV0vWXzJ1ksOXzJwyS74xszLJRJflvVSxJdKyFaT5nO5ZDj+LVEvlbZe36wztTd2Zdu/Hnc4p/Krftkltf+Le5l9/ZW9FV++++WV9WWQykX2HX5TpRLK8voHbtIf3FvzKlfzh16ifP2xQDMfVkQYCLn2tgWLZWwWhS/lOisMXwr1Euqi4Ow8nYKl83QKBqF/kynkEvMPCLrOqKZBxxa00i1oYY6gJTtHyNchQu7GCPUQIbdDhNyQCIW4GNasjwi5W44I1aJahPI8rEIOwyrUELQQQ9CCD0GLpQV9itSdIxVM9EhlfwBSi9QNkeYW6RHeEFNoMd0EUh7JhQaieiCifXuA+1na2mF5byduDza8+/XJ/vGvMKJ8l/j+Z33IIZjXX+UHKNJyrMgVFPhRFEPvYeUeVhXtsALT9lf58ePf/RU6lNIjkOCBgJvW2qfenCzNyXpTzUCg1AmoCryToMi0CKTU5v6sgwN9Lm2Ko836qXQcbnVma1QeXwdvyNbjZLboV6zU6FOJXni9khBFCVFsrS2ktTIWkBerIkjwvAS/K5Yooig1NuOowopSI3A1ozWlzAYkty1qck+JGnLc9j2qKfvAQqLchk8ihQxf3tqUaPjK4wK3rmxr1JNGS7e03ZRMlNItwzdlJUrplorbF2ms1G4t+zQ5rNRu1SGHezgZ8jIZyW4KnYzyJIFv1dYMUvbHL8LTXBJlKHdxuAw/vpdXKX8447f8mD5KNtlfKs+QYcZwNrlbDz2Mc3BL3dwSvGtPDCerFKNV8tEq5SOrZNgqvbiyyNws8uSal24ZmlueDPQwzvoOmFsPujLO6kEkb3LzmtjSkUIHA9KXuVxpHSeuE5eWyxUY9r3rLKPryNF11CPXEdeRbg/mnet4k7s/rveuI9kYaX7dGlAcwwtX4RXr0O2dEiSR+jrEXelv6OoDUfAbKpCC3lB4rd3x8pa5Q0kCFI4VnCSMIF/U8jL2taJUX4vh5F5F6fl/n4mqwKctOHiBao963CChNC9csERpaV44LonSfA1CCERpBrA/tkdX9xCqt0JfSXPYGyxRujdACAKPHErJLpDR7gle2IXe0xK82J6lrhxOU163WCCExw8FP3p2NS27apJd+Z4n8SO8L17wI8zjQM48pvPLdrUQinFYCCX+us3rbszrdlwbhXFtZNraaFgQQWJ6I9uPC6MttZNsv3nCJNtvC6PrrC8YH7N+bFn/5A16b+Am62NvgASv1GTlFJJvBpDdZOWUxpVT/OrKyY8rp0xXTtr6iWuFKLpDsIlrudG17LiY8mPQZlgDYE/DkZr6XCzUy/rwwlOxRyp5e82kGCLNo0OwMdKwfXc6RsmVyNSNjwZAxv27DTxe2EepQ/LRIeVjh9ySy51DRpiUxhd24pB87H8a+r/56CVqIIfEPorMcp+pkiHLpzKMbUGyDWRNnvCJZnbX8ir0FGV2zazDCqJ+HSNWsIVEQ5S+IlFOEaWvSJRJRGlWtY/9oWBPhBfocLHyKmEvhwsrkjAAaKuJ0qAB/m+I0kAD/q+Igl0eh4C9XDuBhhsvU4wKaI7wYmRLY03BnGHLaMtDgQiOdpuj7vmkf2N3VOlSa1fRNXYbp6qglfT26DWlr77V9nB2pa3l4f8LUfr6dXtqu9IX30ZppJAVu3QZD25HqLAvwKr7H92VhQNEUmUSefjQH4J1DrAHB3COOODs/8MLejj7BcIeDv9Z9TNV099xI7or819H8w/Dom5WDXVfrIZuDv/ZEm93eGL6qpk+ZorPCqMXqz5/t+o7aMGMC0F7WjaWWZcT/1fcdv+fVU5Hg+LsdgmzO/xn5dJAi5FJzZaqipuLSC9Mfx0j9beRXpVN3adl06TcZAGreLqK9FHZlD9awIrRnvXof8s5aDtxasXjVdCP1rLhdnjlxVI7jpHmc6R8LLGiR7aDlH9SYj0y313NVgFXvVmz3RospbHyCRc39+A3ie8SJLkihZCaZI+aX2lgK5nKoAXScbFVRKo0OpCAlURpRCFFXojSKESyZcVKJxfJjlXkpnTagXsk6jGuR0K3cpMc7Vau3TIS6bgIKhJVGghIKQxRmmFLiJEozeQhRIuVjgigJKyg8kUIfShEj533KWFIR7AEU0KVBkswJQtRGizBlAiiNFiCCDVWOiyBErDSnR4UgZ60bUrARjfJN0liqgFlwUqnGhhYiZVONTAZiiiNamACOVEa1cCkU6VRDQw5jo0Med44hV1yimucIn4bTnkHTtb/F076Vu1BJA83ZS9rD36sPaTXUHzOjzAkVgxhbIYhgv82GBJznmGIYFMMeYc91i+xB5uyh1h/JXuIYcF9uSea2BQthHuGFnyGFqfKOR/rAp9RRjrPc5pSRn6bMtiUMoR9mzJYM0F2oowt+CKVT5QyYrMS1imDIcpQSKeUQRVMGY4omDIMUS4pg91SBrulDHamjNi/yNFu7ZShkU4pgyqYMlaiYMqwRLmkDHZLGexEGY0VSnLZYy8T16ZEIp1SBlUwZRiiYMpQRLmijKpcUkZVLimjBHxHGZDdbyijKIQyNFYIZViiYMogrRHKoAqijMiRQoa8UgbE4a8oY22UIb9KGZPdkH3P5NmxsDeBY3ZMzN5vhVwAh3oEHGKshsjZFgjmmd+ASCSrv3ZHJIv3v4BIJhsjLH7hSBkErSdwsvj1q3AyO1pm73dDzCm86c7+EuIzONGP4GQZCyNqtm+B2YcGHSb0soTwG9ILPAhqQi+Ld2/Sy54P7+hlCf5NetkbhAxcP2F62YOvklcnejnOX9Vp2fJ2baBZZUI6pReqIHo5TtjtSqcXyRhROr2I1WMF0YvwHCuIXsS6oB5TenGuSZF2a6eXjHRKL1RB9CIlURC9cE6UTi9ixXFgehEr+R5ML8dGTs0+R+wwcW1KHNIpvVAF00skCqYXT5ROL2I1WEH0IlbSGqIXsUr0pBF6EWvvliH0IlaFFUIv5B5CL4komF5WomB6oQqiFxuRQob8qJHEK3rxjV6WCb2wR/QSx7McfDzLkX+qXLK+eZBjVjmxI8iwRyf3noHMuK1ToOizbZ3w5rGOi1PwJ9zZzvVJZmb1lCWyZ/SSHtHLeEKC5ZFe4melFcgss9LKEvJ79LK+eZZjVmWx5ypLnlVZJHsGMuLREcVnIHOxw8PPQadpGSY/AhkR3zyLcXFy/oQ754IRPAiz2ssS0vu1lzitvaT3ay+xrR/jiV4Qggy1l15QSL1IEbtVGqRTeqEKrr14ouDaiyMKrr1YrODaCypSpFPtRaAen2ovPYRMu7XTi0U6pReq4NpLIAquvaxEwbWXBSuk9oIjJPTimsnq3MkL1V4y0im9UAXRi5BE6fQiGSfKJb3ofEcvOt/Ri0639GLYHb2YU+2FC6xgepELURC9ZEYURC+WKohenEcKGfKDXtYregmNXtSEXuRIL/xR7eXZZk/+KXoxs9rLBb38OmRRA7Lsf39wPsp6gyyTPzq455SnJ1H2LSA93QIyj5CFsy/+Dd/D3aB49lQ13Q3SP40sZlZwuUCWU3hhuhsU/2dOGY/P7JUaeaIZGrSfcsq84DL5U4oJnDw8iZLOkS6zPaL+d0nPOWWdcop/n1O6Wa6nkyisu+Vy5pRuy74b+tpNUSOdcgpVMKesRMGcYolyvUfkb/eI/O0e0XrmlA5EgXZr5xSDdMopVMGc4omCOcUR5XqPKNzuEYXTHlGfLdVjX/qUYJ1yClVwlcUSBVdZNFEuT6IwdXcSham7kygQ8O0ekb7dI9KnKovBCqmyOKLgKosiCq6yUAXvEWGFDPm2R5QrAXp4X32nlNgohf7dzH9gl28y###4240:XlxV32DM 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1228eNrtW8uyHCkO/Zn+AJ4JWRX9K45ISIjwZrzoZUf/+4iXkJLKctmeRTtiFn0vzbkICUjpIOEU80M8nv8EGYOHloX/xN9/6GzTwyihn//RedseQcRn6cyPTaXt+YcxMj+8Pp5fvYtFwFfvQ/sdVPn9zcioa4dR9qhT/GVi3ssUf/8Jk4VHAZ6leczmPpu+Nb/Un//8JWOWMFiVwVk9nFXPL+UHiBVbbIiOp33oFBMISNo+fJRtpCIjAc8dN/L09Q/2Y/xB0Qs0B9kVsl5GhPwDjHt+2dXZpPqOdFGhqA2ddYIq1ZGhTequui0IwYBqiw+u2ZKJVB9hLcAq36wC/BSaLCEsel/B0dqx5Wvri/exjDu8QWX2Zoc/RFPTE6Sp6fcyGaggqTL+KOKKAfZ0iarh4lCjt3Zs+dr6Un4Uic4SiWAUaOiybNDGoTJqdw1yHDphJeXeVnLDldwue3s0G+iMfi827GeTarjUo+x634WEJ8rxE9Vm3Xdcs2McmKzqgTGGQG2hlW6qWqJq23Qn23QnTrfx6VQbiTKhxY3c2+46coDrpO7s66PJ0PbVpHKyYz9o8BHp5/imip7RiQ6k/TmGNaCdBtBaPYcRDVAdCP45jjQAxamcxSvI/bE9ZPi7+JL82L2wz+ZhlNfDlwTx/OpsmRqgrXwvZ3qWLkm6kq5d1cPAb00h8Xx+g4+2Oh93Hu1Pzkj/5Cijk6VdvnZttCvWLke7XO3ytGuvXTvt2qDL25N0wZGAro0NzKXLUauyrV2KdonS5atr/QZfY/vdXCu4WGp4PsufBjO7lJC1ixqaQ+3augDXf1PNMhge5CnDNQzIZHoYUG7PIw64PY69A4fI906JeN07JcXd3ikBO/2tHOseik5Ztk9zHSzqAH5rxKJToQ7pPgb9E+xel9dxkWcXCbvphkgzj6QuR1If1IZ6goylXfUEMeNlWI13aDx21RPE1kFu13U4l73I21wH+WIvtL6qo8yijpKLOmpb1FHqqk5ctiX7qY6a25JRHft+W7y/bosSam4Lsg5jThS5X7dFpWVbtFy2Rc0zeXcQ4SATi8GvHoMYlK0gLhs+9p0hJWi66qzbpg2kO+uydMUtF49cXWLDI4u3PbjrCo2QXkfOQA4L3tzzn3XtYB0KdSheGJT3A3HFmYvi6rcSk/buuQciC1ICnXWRj8HwAIhlSIlwaW/SNEGqgRBtjkrwNr5eoAI4xDJohuGGgArgF9uYuZKhq21FG6MZUtS2sqmgGIJcEPbFM6SoXYNUd2wDwX055r5MPQ5GAmV2ma6FrkSh7MYmRuBtiLFllWw7OoHsU1ulNhMs7UG3sJ6d0Bd9YwjyQpjIUqRMBD6/bXtmY8qaB1tXaSpXkbLmYWtx2ddBwDDgx4zLG8ZlQ+LyNydd/1jEGoxpJDvz1a+MKM5CtZyhGkL0/oMhe8OQPeL0EpwdBmcQnHvUVLpF0eon4P+NWyI107yF5RrPr0E86zWIiyWI91A/7kcsmH8F9v3rQT1iUMeuOmdgpqXnEuohQn2Du0idGe4z7KIWur+44QDglbfhlbfwhgP0gE/jjjiXuNOZAqMDmcedeORVnUEHgiJsQDM28PHNFCwO/h09ONBiC07rh+jBhnHoGnwu3KCdTmp2EKvZCc2W0+wDVZI/aPYmFrORYMBG6zGHhuNNCQYPv2YxW61mI2RX7qFW7iEvZyCsRxK5R1CTeiTBqMePLIZJ77iIT6/OwM9ykXP5NrRY1yWv6xKv66LeZG2U/vWsjfXWjDACx4WQIOvlxhAkQf1gDaRHP1OjUnPwcxByBHlaR5Ea42wTZzMbM9nDEQTefAW7bp8zypYxlSiZmk6IEqUFz0nPcTKEkJ7gCUJJD8TSSFSgyQCljaHyJnEAJFJkEgcZk2Q6II2Dibh2k8ZRgieHdrIZ6wftKW6U0hqgKCeBSNZAn5O8gDzCvGBVOYLMC/aVI8i84JhYhiDDownBotxI/YnZlLOprglBn3HdFcuvwanQBGJZO7kPXeBzJwzLuqAYMllZcwwDoVQOttHRQYSNaysoMgmbLElKOhESNrCISUPCxtJ+Zat6ik9gS2JL0dsCHJSZ2ZQ07UczeEViz9YJbElsKZbBiz4RieT6As4ouTIbsGv7kHGySoes0r5klcZe8jjXRND5LhF04Z5XonnPHi+pHLfSTr9mihin/JxLNirIc0N2yQ11DslopVxzQ5rmhhh9/IQzppUzxpUznitnBBMgSKby0W131DBgwLHxYNSQRUSRlogowruM0YVAvmOLqYa27TWVU25quGme6bnjbZeEjVwIH2dz/jWba9+Gfs3mQC0z6VxkdO5N8qRWRG7Z2xSps/sx9vaCsGxrEkmthEWvhMWy7QHPlt+yrPyKciLL+oRa5VXT9dqhlmtpJWAk+QNkYIaKfAkImSD8bj/ZTR1EbuMkimTq3CnBqgjGJIi2TIUZXoArWYrM8AJqI1PJkpOyLAlCSVmPL7UW4g4eQVJm4mZKhwT8LCkpgzGJITNtdp6KIpOUUepVEEL+zlkYgk+bkLL+qQ9k1EUcpnSSC8QqVqY52VDKstqHOhFkWZ2tTGTyxj1jsE+Z8S+SqqqDKNHbFRlESVZMjiEzvRUVH4MkixLK1A+Eq3tLSWjKhH6V20PSr8ozHgP2tpZn7nKoP1N9iWswds/brI7/qOSiPwqrL0ou8vOSS7xmZ0Z9xa6pGFpyucRlf4m4QZ41SXVbfTnc2+rL/dbQLH49QvfFFf8TxZXKMu+zJ/6niythjcLueZtI8d+vqCj7tqKyf1ZRsR8FwxcVFX1Vx7ytqBw/UVGJ8V18PT6sqJwrKYjLXmhxuxc9MOtLyGXFFbyklV3hxZWTIaS4oixBRhIfVnEk8dOUaW6LK0qN4koZyYorGFVhGVlxJc37+sGLK2FnyMviSkVeFlcqQvMMgSB3xZW6Ki+LKxV5WVwBz3JTXKkIKa6EgyG0uBIZQoorikrDfVFzXyTi6lJc8ZquBSuuKIrQ4kowZJ/uiisx3hVXYrwUVwRFaHFlsp8YOZ2biZAYL8WVekhleuwPJWZU3TGqupfXYPoB9qsruxn3C+7NzfhN3eW7kdl99C5iWyLz9y7ES0VFLxWVj99CfKeMcl/MSKpsoeHBaThEtTkMTloi2wFfd3GIYg1OYq38ix5uUnfGSaU34XxzGM63nN88pgi3bpZUT3ha2Ng3JRP/vyiZtMdhl3UN07bj1brmJeirNejrNejLy7rqF6WRc869v1hXLRap2/MjxhSNf1OI8erXCzGmEYG7q3xxYIOXuGO9yi+h2n636PTBc49Y7w13JReXf73kAlO4N9ULL3+9egGr2P10XWP66o4kn2H1RprZ+Nk0s+l48pkmZI0dyVfjsWWw5dg7zLhhvcIY/g4TqU2djaaz46YJRNPZeYjr1iFT6idqIOyyH3Wkurc0r/HYMthyPPWrJNGdvRSNCp9hGs9u2nBkxmW2eEN6zc2jatGUJxWabCNFZjJA5vG+oxs8q0d5swyhJGiwheI3WO0mCdlIYXVnRVz7I5oQyOOxZ0eQ4Cm7bwxBggdTWkTkeNFZ17jVDewu2aLMx8xxU4jkOdL2kYDTkbzUo/CdcznQjGTtiehDC1F2PP9tyCRZgGiiCckoABPJY9VUHqumEuWXsO2Jjq4z6qO+FtXk4Wkf156RGvLwtC9pfUZqnK4fsYRwo2RnVF7KExkVFmSDvDKq4Ry/e0m+eYoyqNHdoxMkQTcvTAYJumM+g+4sHGdwm0tuf6QZ7p5zIgcKxouyT1Iw/6qR+xzlDYFL56Ocn+Fp47wVnj++hKh6VCyKfjWHSaMxerosaMjRUKOhR8P0COmrGVdbjmmL6Lac5NI8o0b+d9kiV1uMQFtkbrYUf4224L4Y+e+ypWCZm+KnKambEsgTDeScRv+yKb9qwV9mG5nn+r2UJ/e9DA5uZycI9bUGq8UVIldh45g46tqxoNARjISAWIbMCrk7JEWmEzZuuPSGTAdrtoBj4KBVgxrHMC3vsPUxZeWef9YvC5tyNttLx9aqnT0XYlpeg0jJU0qeUvKQAvqilDyu1iAlMiklinQpvSlns71nHVLmNdy4U3ApckqRU4pEKXJKmeV1dxouRU0pakpRKEVNKfPf7rRbNpGipxQ9pWiUoqcUTFPs2uDmqbZ5jevBhmdEBI3hcEgURUiixB0bRSarASQwZJY53HhS05HJalywDMG0lWkf8UBY2mpj4tppVP1LEeScEv4HiKbI5H+AOIpM/gfIwZDJ/9yRGTKvAC6weQh97oyjI5Q+byKpRp/HNpu5zWZus5mbawaFhmuDIWPLnaAvS29JbKnaateGyoD8KwYUkQHt/2dALxlQeMuAygL+NgxIxLcMSIbfiAGJ8z0DOn4jBiTSWwa0/1YMKFwY0EaQWwYUbhlQuGVA4ZYBhVsGFG4ZULhjQHDQ7hhQQK4DXxY2z9lMgwFB65YBBeQ6TUqeUvKQ0hhQk/KaAQXkOlVKb56zmQYDqlJuGFBArtOkyClFohQ5pbxmQAG5TpOiphSFUtSU8poBBeQ6TYqeUjRK0VPKKwYEyA0DEvGOAYl4x4BEvGNAIt4xIBHvGJCIFwbkCHLHgAC6YUCwMjcMqCCvGZA47xiQOO8YkGD/ju2/q4uqrA==###3836:XlxV32DM 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ee4eNrtmkuO5SoShjdzFwAY2zitu5WSeEp30jmoYan23kBAROA0llJ1ujpL3ZN06PzHv3kF8Zk8enfLm3hTP/7WRoS3fV3Ob2ZX58/vel8MU5boU5b0mqVNxHLTWiX3pu2qzxJ6CgOFEcJs64ttEJrda4xvt/YoYBRr9K38+fnT6V2LfKPMdvnPj38taUtvRipz/rWkNb4pY8+/tJb5QyfP913u+dvnP/ti4apXuK6iXWW7qnZd4Bo8XGP7ftzatflF065HvRpV73s3zd9o+J5pvmYNcN3gPrPLdm36Ds/LvYSrW9pVt2vzdVu7Nn8Hfoeq/nl4Yglk6Z34AUOi1aLOMlDbm7LbWgcqvW3Khz5SS/j8CGFLff38vayM+oG2Ovagf9K8ciB7oHqw9KD2tMxwLPensQeWerBhD8KGPUi/3INXNNx9HHstqOWSWo5jr+XXGnv/Yey1oR4o7EFcsAfLf33sv+utJsyS95MyC9n2/Lt2pkTfcnbUrSyUZN3qd+rOtNQvRQodhb7ughDVD7/lXAOXbXRR5KLIRaGLIhdVXHZwkaOLJBdJLhJdJLnI4rJVFx9HF0EuglwEughyEcVlBRc7uOiELi10FGaXvPt3F12qgdPgso8ukVwiucTuklMaXWJxWca6UFygBhSTHjmMPKsLvBa1kdA0EppGQlP/qRZBSVFt7fASp/e673ZpqItODEqZ2l1WxbpBKdO1wdKx26CUKVhhaVrFlfzwrMBzjsSVPGq5bTss+RWXfMAlH2HJ54IEy8zg3RHan0sWKHpQVFHaAheDIosCi9b7QRFFaQtxeE5pfy6doKxcKe3PxRWGXaLSySLXaxhcxSRo9godsmFQSrPbQNljUEqz1zYh66CUZuc/VeFNgGa3iT8iV2qz8x8gkOWOQDYkEPc/TiDpkUDW9PUJJIlHAhFflkCSfCSQvNl8eQJJ6olA1vh1CQS34zwLbTvOnZkRSELWyKsNQ0mh6gSSoymBJGQNcFHkotBFkcs9gSRkDXCR5CLRRZLLPYEkZA1wEeQi0EWQyz2BJGSN6tJCSaHqBFJdJgSSkDXAJZJL7C5AIOByTyCp00Y26ZHESF0IRLH7OmvASGgaCU395wTSX7/Lt2YEkqUJgVTllkCqcksgVbklkKLcE0hRBgIh6E645MWMQLIyIZCq3BJIVW4JpCq3BFKUewIpykAghBlpTiBpSiBpSiBpSiBpSiBpSiDpQiCqjkJeT/kPEoikMxD/GgKpZPG+B/s1iMSKXyST5B7JROQBrLSXl8DXRxR/0xdiFLG3vgT7n4GVl/YlPFKL2KAvZUf8+vgSn/BFrK0r7uuepNBeleAkJW+XsGEry5TZdpncbLtMbrZdJjfbLpObbZfJzbbL5Nh2WTpEzQ6tNllBlWFr9yAaeArpICNFBIY4AgNUHuaSyCWRS+ouDV7iFV784NJAyVNIBzwpIkjFC0jVyslcJLlIcpHoIsmFQV2tzMxFkYsiF4Uuilw4YI7j0mDWU0iHcCki7MYBdo+FICGOLM2wxI9lnaGMH1GA4Y8f8YEhkx+Rg2GWHzGFoZkf0UZxt5Ypoa3GnUkDKVnB1innrN0uXOFsxtzChefsoHAGTIPCuNENz+GsqTxTJv8FatOsaZo1TbOmyb37L1DdaxpXe4zwBDBd/wuk0h0BHUhA4f8EdEtAz2czIvw5BGSEeCYg/+cQkBHP5zbC/TkEZMTjAY6wfxQBpQsBBaZMCWj6wpimL4xp+sKYpi+MafrCmNKEgMpCmxEQHpmUzMJQUtiPTEo0JSA8vmkuiVxSd6kE1FzuCQiPksClhZLCfpQELhMCwmOt5iLJRaKLJJd7AsIjtuaiyEWhiyKXewLC477mspDLgi4LudwQUFHuCah43hNQVW4JqCq3BATKHQGBckdAoHACikyZEFCR7gmojMw9AVXlloCqcktAoNwRECh3BAQKJyB+z4WA8OQvJfrFi6BQUqjmBJTwNy8CI4mRGghI2aUMsDzetvynEdBhhEUCikhAYkZA+auZPLTM++91m0VJnn3H7R+FePbNF78lzkJJZqSmpDgFXWnm3RyRU827ceqGbtojlCgNGUGnPz3588o8KOW2vh/Kcgz6R6u1fuDWtW45O69VMupWq6TfdS9ROuk+nCpMhlFJMRtGJdJ1GJXw12FUorS2V+Iyx7I8Zh2bt7bmWc9+CIMFVEU+0K4NCdR4Lf0yDEB9hP/4iIiPIAwM+LuqRX7yEfVlaHxEMvgIQxgg8BHrpx6xrnV7GOZRiY61Mhz4L8dVEM0es3lc5HQe8+RfAQSldJm8mqDr2KYFu31QtwlK7We6/b2tj7wn1ah8o2yyZYtrKztLNRpIxYWId/nKYX3/dSEwv6oA+OQ5tOye9qRUNka1HDt7EsOOrESuEKqoLW5cIfBRTplBQYxS5hCDghjVRpoUgiUXRW92/k7tUKudPh2w78LQ5TE9W99amBdtD5cI4bf6tzTfL/2BeeHtVPGVE+ugYBVvS7QrrX44aL/WrJUwuHnPqp3e9sEPOaclLinILnnYE1dqFa2clpWDK7WKAnu5kHoTcsdhTQAhBrGwgcqrso1Ti8q3ISoDnKP277DVbiu/L1e7dh9E5T6Iyn277wWx7Ra9JTAYuVLUmteWTcl0JajmOax5aV7zxuo1lj/Kd17QLpUwhI+VMOEWflP+hkMDNK67/nB+gNJ2Xo8SUDJnP1XAj+z5qyX2Ulr1pW62aosfufMzhTc8Ft79cE+FV+yPhXcsocPe3QqtuFTVazl2H8txYHPJtvHNi3kNNvYFNXhdzc1gBByMnAE31UtcB0O68/rOjNJ2Xl+fUTIfKETa8zICyxwRjH0FImxhnSOCsS9BBGMfEMF79YgIIxoMK059XHHKn58Bhwv1wS43AQdjXwAOrPqV5d3qXJnnHub56GFuzaX69eINGitXrN4WidVbte+yl548EUNhNJYpQ2HcPN3k+CtprrN6UPCVVG3CDgq+4HJQMY6/LmdleA69Lrd9qigl4hiVG6d6X8sYMvhiHFWkgaOkG4aBqrbZtkEhpjiWdVCIAZaDD91Y6Yd7WKWnel7bVmt3mfkW5YlvUZlAqueMEOp3iBByy1c2RhzMnFgGhWAOdlVSCAAXI7nCoBFpt92DmKeWXXGFEDRjjuO9rcRRewtR6QlEpbeMQmBD6r1lFMLxuRoRPqsjhmHp4WlI2+G7wk9DiCUh/4is804Av0/JFPTmiHZ8p51DDLTzi2/f01qt9iU9VMBoX/AWCr/AnpWY6F5QYuDXxrMSE/2vl5g2XbONO4YXvPHhT9VrxN/D8t6rmMTXJUxgVXI07lRRMontVKxE1JugGNSH9lBSqMYSkW1XbIsa64BWTLkUD42SnLyD1FbW/al2skUSI8X3LIW/MIfWsixerd64Zd0EqmWLJEaKbQylOtfX0EtOBsxJ+XtycjPhISe3V+TkZuJDTm6vyMnNpIec3F6RkzBds5zcXpGTMFB1BzdxlpNF4jkJEwhKmOVkke5zst7UAM1ECjFTS79nOVk0npPbIZgyycnifZ+TtZXADCZi1PO0PozlJMx5dxxzEk7MuiUUZhMx6nlaLcec9B9zMmJOqt+Uk/V0ZZaTh3pFTh72ISeP5RU5eTyc1ppDvyQn/UNOHusrcrKTcY0uORmZNORkPx6r0SUnA5MmOVlu6tlnKXQU+mtOJso8f8lJzxSek6vr/6ir3pOcLK1s+Wcxchj5MScP7nipk5ZbtvyzGDmM/JiTtm43l5xMmJPL78lJG+U8J/eX5KSNap6T+0ty0tZdeJKT+6/n5L8ByrLEZA==###4412:XlxV32DM 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1294eNqlW82SrSgTfJl5APmXc2L231N0BApEzGbuYpYT992/ArSoEvXYPZvTtqkCBVYmCar3lzPq/fsf40J8TS/5759SxvXljCyIBERE4xkiCiIKss4cmQoyASKV1hTRBhD4+f17EWtyAAn/si+x/Pu3yja//Cz8+w+VTXpJH99/aC3ya16m91/wPLi6/BXwFy6x80uLGN/llNwgRaH0fv9ycS4Q/A3tEqhEvyS5cncy9NRcT1l6aq2nHD0V6qmZnrL1lKenPJyaTSSnsiqnLL0xm3LK0VblqZ6S9JQsp+a1tmb2qf1dWsPnhTY853LpoumpVE+Z7WraurxUiLROTqKeYpWEGCwiynJZecr0b+skaKR+l66zL+nCUrsuv6zz6953Ml70nZyWq76TExT3S6U1F+x3KbhUWfGCTS943QuWUWLBqQRs2ZpcS/mlxaraI42P5eGOPzJujxQJhtz2SK1xHKoyDlUgFRV1BGlDT9URVFuMp1pLaeNFwMbjqTqCWBzgZTjEwQ8dkG2PQzzpAKWO1ZFmqI60Q3WkHKoj9bE689Atee7VSb1bMlbH3HdLlsdukZPs3WLOusUfu0VNQ7fI/L4aiHIdGq/E2PhIGw95cg0ts9U6l+T5Be8MIDosFCm3FKim0JbzAKqxK+0GyKdyV5xKaapC9gUhereLytEXvPnl9jwnWqYK5cEla9vJMaTkWUgBJQPLbFg9p4KY0gKfBUNEQWxrm2WILIhryLwj8ALVVkPSa612BGmthrRboNUGbLXfqmBieVxShiGlCnYLomdIqYKrZJNsZkgJoWsEJek9tQpbDGv0IUiZVr6SUTItSJI1qxBYqqHwMTGkkF7aQmEYUogyza1VCuvhKFFCJDxDkCihVYkhaidkGDM9RnYbM8BrrcGO3IQNtluDIYiWPbRzeZ5pb9WRBNzYeNmX8uDFcvDTeTkgLyfCy7+ccO2VUhvDakan6pgMKy8fWDyJ4wso0vQeCD13Qgci95zYOYuHkcXdyOLryOJ+ZHFbis0b00rVmFdvXKrdQOWsHVk80QApjxpAjhqgyYK1lcy1wF9zqKntl5ctIF7G+ldLU08s20h25+wNIct7alXZMfY+61kppoHmpnXglSkPqXVKQ2qdIueVteoZc073C7AQ0opibI+hOacXjEWl/3KtvaL/Tl1mDYz+eRDCyPVu5Ppl5Ho/cr09BkGPQUgYBNOD0CsovhUEHcU8jAiUE2LuI8K5wOQEI9umHTjZDq/9qegQo+jQI+/KY1zsqIFmjIvFuEAKoZrjeVygiEHnyklhEa4XYbGI8J0igAhyVXKQmctgL8D7z9rleGj7oWuHX/UX+CWIPa0XrOT6L3jdK1d4Q5DGFZARGhesCDWC+IKc0ZXHXpemPEpV9iOLR46pkdVr8kQqZkyscgQf6db9kduRxSNXj77KT6mK2ORFPdqkU5kvAmPZiUCU9rNZGdKlQrYLQ1BeiGxnhqAkAcRQpCqpjTOdoEhVX9pxsVIbWWMrG3l7SZCNvLNsyiIiBa9MMIlVCgIRldXFwIag6ICSJoagUOlz8A1BcQPISpEuiIhyqB1YWgSU28oRBKFyhGmltLdINLEUZgIReQP/LwxBjWLcAUEZtWXvjqCM6u5FQ9BvAK0UBUWq4oGf5kTEMydiQcWTRyfim3JGjXImfvYnwk/9CfdU2Ry1iRz9CTFqE3OhTZ75E2n0Jxb0Jw4mBLMq4tGqqL7E0arIzaqIt1ZFvrUqvqdoxDQqmuU4U17vDIzuNjw3MELN2tcGhn9mYISfGhjuJ6ImynxnYCzimYGhRy2hRi1hP2qJKNOdgQFZ79sGRuPmawMDLRo9q2sDo7kVXFOtQ7dsLgWLQxrjEIc4FH+EeBki+z1xl+ozX8FGijBfgd1DfIUgFEOor+AZQn0Fx5DuplBfZEVfJFElwgyGfGkwZKoAiIhqCDEYnGQINRgyQXC+nV5o70TEE1NEAC0IrXwWnz1GBdra5+LFsIgUYYbFQhFiWIRJMuTMsGhINyy6q9MQ6urQGlCRAgGkXcZsrrQrpZqHqZnR8vKOYATX7lis7E5UA8w6iYzzqd0SiU74vdgpFUiA8oKfzuzrzuxBXnsZnLu5rTFMfnfSv1icoB7G+TrFKf+vj/g/IP8/WZSAvE2I2YzEfL86QCn3/cuLasMs2vl4Yy5MHvlWezGaC5xJWdrb7IJppOCLtQRqKtwvK0CllxsKncJ0UukTCl0eUWjASj8x/h2rKYzjIpc0Z5Vpr6lzyJtq7VPSeeDNMPLFSONybmUnLFuNs2HZy8YoOZUYo/Gyx0478d0JV1GC2uoAr3g9orlmC02DdIESTHmFr1Cdj6gNKnmk3U+IRzu1Tx7LaCCpT8VlIQgztNtr2h884YORBbWTkl0j8BrkQyg8YhEsT0LhgSB0KqXdtNKb+hRHu92C3x6HKRIKygzpjrTTiiE94TotKIITplLOzGKG5APlJIYg+cDTJEOQfKA9kSJkEur0RJFOjKtr3F01wh5WVTK+tm0CKF/rS84940fM+IrN5T6l9S2Hf5jexUSGrYtu+8us6ge5/cS19o/mdvMj1/poTath+td8aD79m+6s6TM/2p350sc54Ho3BxxYKI8slCgLcc+7DIKqFXhil+//qez2SVdUKO5V9EhJ68A/nmVDGIniemIJnNGXYEW8mVguj6zy9SwbQvNqKPT5bJI07DiZ/OBP1tZNt4y4/JgRT5xy/2hSOX+aVEI45jEcCcMhejj8d5zymkzyMI6yPoyj6WQcQR8cp2/TYRzVUi9mwhBpfTKOTmbCJzNAeeeqHwLnh8Dh9Jc07Dj7fTCO5nAzC56CPBtH4yw43s2Cjw1vi/684fmq4WGUU7vBD1O7bvCb7xj8teF5fDJJD30dZYGaTS1HuilvNWzU8RcwyowP9OMDTX9gD9/65IH/7LkRSLUcVb30Z80oTU+puHZBILYZWm0WPLTdb/f7cYmhTWT1LPZHl+tLmbtrDGqoi5aJz3GjIOVRAWKDIzWlQmfNlt3ThY4NgSFE6EiUGTA4mQTc/fENQe8BVNhKEIwFVGZKrbSEsQh8ucUuE4HIGo0OXdXMxUSIrsSirSN0+TT7DQJCbSops0pSoRkYQuSldBTptg4oOHZPt3V0nHRbuWljotgtNcHuRx6PArNgYFJNqt76fltfsmHFUHi+TpSco6WVNaFW2nbk8SjQdSLomN6ZC++Y3AaVITgxd/aUXgdV7sPf7wbEmmd2J1pJcD1/Zt+rYsOCDZzp8s+uRrfSyGISvGaSvBDsNduG1kyeSReOoFstfZeIW+OkZwiR3zIzhMpv9mZS+U2mExOV+atrQJ2s7G+aqsC86XIn33ucqi43oRp8AiZv8NN1eUJdrr/lxFxtCH24laSsveAejk+quElgO296V4yLI/Kw3KFH8WpGqWvH5Q43LncM2zCNqVL7ymtZV5QOOutHXsvlDs1nuzf4Wgf0tB+2VnSPX8u5b61ITNlwojfjFgJ5aaFIdUr026iz5zoE6uLO6uKPdVHjXhc5rgypk+0M6dM2Qqn87qKWbiWzbEASRTr9wbuSKUK2W1vcx9YQpD/Z5mEdQZqVi7IM6UuzbaDtCDUhpBP740qI6boA8fhXx9cFtGJIXxcIRjCkrwsE3InYEORm+H8mCLWEpE39Jk+zrvSLpAhZKAhqZghZKFALQ5BLttHVEVwo2N6BHSH7GMqYrC/+kAkzZkJzmgnZm3rIbZ/sifwhA2p3lgklZsIbU+Bj+ktj+svf9JlpRlxMMzrsVfoTuPBpvWfp7yyCe0L7lPbi57S33GymklrgHnW9nGymGtKfvt6uLId984eK2LucJ5ZHOY/slz6kwecWLk2DdOt0WHAharH8pcZNxAWhL7XBHSk10uxlW2aC0E1DcnYLLYmkKc8RmqbszBCSpqRiCElTi2aVwxwhbdhTWxm3NLu2cbwjPLvOrK19p5H0caJIT20mzAurAklt+4bpDcHUJpWlVaAUo2ZebfJFz746uiGEYnRgyE4xMCbb8pBYXuYlIuY8OWHOsw/Un3hfpkH1ZPHtek/x0z3EJ27s/H646HbcKyzHvcLmTnqe7BUeNuGINxqwV8ZrfH/O0Kebb0482OVCoAbnrwWqhF9MhWu8FqhTvurvfcfNpxXAjzuNt3F5tQ14nQLWVLrvbQM+MTfn9/dX/qSss86rPbrCdgWrzc0eXT06afZOYJ/s0R2yujrWVN94fsL2Xo/pxvNL7ydUNPqeZ/bf+kF+l0qrG3tNWPNNe40mW8fzfXCWIX2jY3CKIX2jY3uTdoRxRMAMXW8iuds5hpApxTLxgui+yWn/TjNovjNnn4ZsSHfHktQEaRZGDWizMLbYNlwxN0t6P9OHdmcKKMlRpDM2VITdQxjb+cAQsuHI48es8B4R0QCVNwRhlc+tHpJUnvpZECtBH0o42AXJiusc7EgsDJteuOAY0qWDssjBuDSbNt7WDEEHCP7PBKGL1nATbTEVFUQG4Ipy2iK7sIL6NiPnV4bsVhMkVbvtTBQv16leINW7z1Qf8/vBl0TPttycsX4qLGXPNlDiPCKufY0iuhuWGtcozj6NyT8lrPWwUw8nsBZ3hNW33hjcEWZxR1h7t+3E7iHpxeyfC2xIT0kGvye0uCOspTGLOcT2HWEtJak50pvIFmtpqqxZINP2DdZS4piY2Zg4fuN1XMb+6SdQUIt8/WGRWcx//7BImvqZwsVnO2ax//2zHShCXH8BYxb3gy9g/g/JP4sf###4872:XlxV32DM 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12f0eNqtW0sS3KqS3cxbAH9QVfRWHAEIRXjSHnh4w3tvvkmmkFTl13dgW64jQZKCczIT9GKv908ltH/liz9BaCPylc5/2D//kYdOLyWYfP+vPIx56eDe5cfjZUQy7/8oxY+Xk/7909lYGvjpXGj/htLM+5fiUb5IF7+F1uUe8c//5M7Yq9zx/mEPUSDmEoJyI+8fTsj2kB9I7r4/tLv20I6g+pDdt4yoeGxlMOOhbMK7dzou+bwU7fJH/bs0uzGwRbRmN7E3W3aENFs20R5yB0C8D8CzYsvOJLIl+6mbMq44XIl69cO52DqLqMXWmdtShjQ7NG7SxtFkv+JwJerVj/LXn/KSdfELly/14uqf8m6P11Yc3d648Nt4t4G9f1pdHJEh43L/+/4uP3H8U6o/CfzTUX+S6KfE3+9f+ZXVeWH3Oht+2mT6v7b/6/AjtrSSNvyTz604pdssI30e+l1+2htkSEPFHGd5gyx5ir3x9I1ktgbNw3ZeDzypvh4Ed3osCLsdw2l5llCnCRbOThMsnp0m2H52mmDZ8F8yxWMsT31hjh7Lc5OwPHcJ1qS/WZ5B27CvXey9C55EhBF7DhQA02QM8zw2bpexcU/Gph0vJhjS8WGgY2VGxzp66FjmVutsGK0K8z7bAhAHl59tEQLb8ptHsbVVV63K95bFUyiqWzmQ8kiGlJ7rsRHRhlbcbyGVIs2xjOi9drRZgvCMGFeRgxOkUInltbXYCbS+q2pcXiTFgvbuBtKMy0utmRBxc9nibIKYzARmT+7p/DkQSo9tJgKGCVk6T+xjxT7TkJ0gvCC2Il4TpJB4Kq31FViQclXH1C0N1fwUPMKbN3TVDKYcQUqbdciZERVBioW60nRKiSDFwvzXnzI/fZk5PBTWDJM1FbCmR6z5y/LOaHh2Dl5kK3viRXOmzsK5kzL32KkSN5zf/2BTTJWdWOEn937gWESsyiKCHawKlCnfg2AHq1IOpgRbeL8TTiYewm5lQbqg8N2p/oSHdoT6Ex7aUfk84KEdsf6Eh3Zkt2U+i2qhFWBwniRwptksYXBCK52b2crgDy+u8j6mOBvLXfaOWyUftii5E26Vfp1Mgm+LTdwvQsPd+4GMKQPXRWjvGNhswzx5WMLAxLyzTUK/71ShkzVhYnlSBb+4TDAxbbLgMq3Apm3YNFqVlfqpUCxLUYi4eE+yxXtilemssUQ+dgXcnc1vrB5MlQ8PSpCdTZTAGPJM4ftgG6tbghQxCq61JhHSxSg0nQJCLVdYp7AalfZy/J4fkieRKEgViaCKdckFYkOxO1TVs3sgIwIF669uIqBgWYI0Qaa8thVSdSCv22qB7VYDZ5d7sKpAQtERpCqOEwRUJT+TCAIaOqP7ZsHUk84kA+nqyltHhnRUXJp5miQuDakDSn1AG+kIRGjG/B0ZIpSfscQ9U9K09Tt26dR3vocDI/V1qzaxokS2oXDhT+DRlsHmUEHnv6baaVC7cKl2JCJPDPHMDPmJIsX3N1G/KwJ4dA0R8kKssNzcJwYXEnaRI5xyA9KWWNOFa3UbUqZOikTVbWigWaWsSzCVtKKFMzvJ6pUv5E12Yi3oidk1zU5I3pEu5UDFOkHVtVoJO6nXyEQzAaI/4f1NMuAI7ffpd8pCUu87aDUTnZkL8L9KdFSKT2q3JQHKEvdV7bBe3acgFxp4kY3gLOSsLOokh3Wm3Mth+EoOm/ZRo9NidBNNavR+n0JFooEzeajzCDFsn1cDwVlKf+0Zqle4NpRD50TamxmCloN8y3rAjJ2kRghm7L50ZnMgGhlRpDngWOW9R9ah8pTePcPITP1mdtUQVNlBMpxf6o0MFwTJ8HRdmb0kXRzhQ0dAbDPiCQJi21fAQHCMkBk34YemaMxIoCFIaNLI7npHENvgCKYMaEYweZZgl5IUs8/18RSObvKYHGkQgqUcekmCQOiVzSNehRCmsE2sBbEtpwk4tTMgdvGrgtht/nZclb5qHncSPb3mb2bN8oiAmlVA46WAniVQLxLY9Y6veicW7RzSt6UnCdxBApes7jjr3pBCu+Z+7iSrge/sqS5n3THrcvGrutxtCrdTYdqZWyVXQ8cbm8okSAnuRpEKpyf+lBVaKLordZEVUlGlCaJfE8RtTRDNKtDho0DvLCwvANQz+4FfvICqnlQXzSoxYtVFteqiPpvjl9dyuGmOmK8F6rRSP7+WQz1Jrd2vXssqtel9lxj33JKvkivWpFSe5BtJbY7eoSZ5KEKvfksIoRQau5RU3+GNha5ZskKu7UvUm5B65XfNcJ9TvfRxCIxM9RIiOGLnTCLdIQkyE2YbDUFQWhyhtbyAcIDht4AQHGAoEMM6gbFGQazQEZDW3NxOkCmtaTihIyCtfXkMpFUtmw9ben4cFhuP0kIRBBkW5Ln5/4wgM2SxURNkxkYQ5lTGRKnkjMI6AulnprODIBBP5TljAXGk6NsJeTwEA3ajTOs3TxqFqCoLUcTGQ+5cdJnXEatXyGt46rIFXd4vk1C8AHsS+rEK+7ithbPYf0HFzVeF2Q0VZnvue5fziiXnbdnsp5y3Jct3Oe9Fovuk9t+Wc+Oa8O6PCe+vTTRnb2I/bc8lntYUdXC0MDNFlRz2qzOhnjiabYt0MrfWe01j3dT1IfH9IQQxBvarzPFfbw1e5eV51cn7TcBgjn9hEzAJtvo1zLFtV349lpBErCGJXkMSfvbrcb8Bmft2F36VbGnVfFUJ3943LtYP5YdZV/nvyw/ZxXxx8YGmj79wsRSLi9dMnse1/MDOLo4PwZsx+srF8puihnwqapxcbFYbHLh4BmyZwHHA9hcudjXEuY/g+L+5d7CvzkhfFkuKM9T9sZtg2f//2E3WUjEy7ez5i3hPV0j2eK+sgHFl4OpcwQDlzp5GkZ6KMuIWyzGU1mK/MnBFqiVCmxEWlSmKQi0V1ahil4VT5vJoqMUXUW3oSVzLyNAO0HGqN3EOTtG03jQD3NIhqoAIDUX4iuAKCBMtcG5IDqfGQOY+z6ElGSLEmbggVNw5Q+p5kKm6sx1ZahaPSzMvT2WUWZZpzc6om+9KE2TWSiA47MjlZlTc6GZUxM/QXINDeUwqcmIqv5yIIHLMys4XwHCInN3Mwc0M3HzgYDm72aOXjoLl3GNC7cJM0n0moXi0tj73cjJioM2d7Mto4wkya4ZRBUDS7E3OeYufxCVKHtkBrpE02j60Q602G2U7l2EiRuYGWo56j+G1gnSv7XTnySTiNUgkom0vt2YC4zlZAd+BHLCOxxrQBl4zojHZZQvrq7fUi7/Q6TM3gvpgcLFthJ63MSCPdTmqG+7U+o47P3PmrGHXTsiyUvJQCEMTdxZc21N4tuNqMD7n9ycYlurxEnU6lLeBWyzJda7zDwf5x0PS8U29kByz+5RstMyCJBst//iYbFwcF2HkuMhzyRBvlZ1SjpambbzmT0HZbXuosTEPAa3a+EONzd0Wc1C8+U01jZ59M2xPD3tR1iQIyJx42ItSa6SyxtuCfxW2XRzNECej60Q7LTwGRs8QToa5P+gWc9YESKyBuvAkgu2rRd+EdnYmQZbT4tynChza4TpFe6cI9ne3IS/meoUFr7umQbqx/o88FwsFtBUrO1Qotj2PRFZZIcg9HO4Bie5TZt7D4B4Q+HzPMczYEw2KrLUIwrtC1kaCzBjMmp0gs0RmrSAIhDv5/xtGZrCU/88xMgMsuceO1GVL6ndWCgThop+VgSAgXRnRBJmhAAQzHYHwQVkWMTKDj9yaw8gMD2L3W42Hxruogqd8PQ/ETdlfQocpPHC7o/tLmCOTfH/YV+qcXh39oAhPFam4VqTsU0WKqMrncxT8chPpl9t6ycez582jU4Xp0+nAh/MTZfMovzi7VjfgSCAL89hE3GjlhpQT2PvLTaPcoXlUn+Nv1edph2fl037e4qbwgRWMGq3WAgVoEtvShZdakeDTMQf5aTsn9y0fMne2xSuHPe29nDZYPpz6ezrmcJwtvRDBOZf8VL6Qm2KpNVkj+9JOX7x5LTto8CKc1XPocO5Kxm8a/N3JpxFWkandlsTfNkgCpDuU+aRycJg0149OtAZyl40GGcLxnpOVG0GQrElJEBCzTMSeICBhqo0QEFRjsNJgBKXLjgc04uKK8RlOHtY0TtFhHU2UFMKxLJpxwK4jqDRxWIKALGYhm62Z2ZueTuQIp2rmCYLVTBHkWs3MrZqZk5qRZ6aaZSduaG40J7bvqvKwpqBaOqyDKHvF0QaSMoERBOXJhyHIPHivvCyTO7zka5/aGUA7t6+08+JMIt7o+SSjFxs78avjGX6VUXcpo3nlu/QkS979rSxdHPDDewyExmqR6F6hzHcKdXEGIXx1BsGvCuU+K1StDdxzr/477v3dZ1qdhC6e+RB4yO0w5/NdYykLjXCylEUiCFrKwhHkcim7/W4pFwQvZREwcr2Us8GnpQwL0iU6rPNSdokuZW8JcrmUXaLf0PgaU/DMvKTIEWEx+8six3VFw99XNMz1EeLvKxr8q/NS8psjwyUgvjsfFdcd0wAh7ohrTxWOEQW7U2kke7eelTA3O2dKoC/o6IHd64qGv69omE/ng7It6r6ikW3R352uvahoyPc3p4j0V6dr+cno7eHIj1Ds8kjwGnbuq9Hx/ekLyR6ZylN5Ap/zaeaV6qzf6Gke7eFApN/IESDtLUVmKd9bRRAIx0RgmiAQjgnvBEbQ4Z7NBIygA0EeTqd4+G6ifzLphUQQ/hDEO0OQ+fGIt4kgcwPFiJ0gUIXICTY2AVUhhBufeTcEfR3h47TAkCpEn9wDwl9gemsIMk/ieCsJMr9SCcIRZH7Z4j3HCJB9+ZTM9+8zFCkp7MCk4fPRmD39H+5vhFs=###4652:XlxV32DM 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1204eNq9W1uS5KgO3cwswLyhMnorHYFfEf1z+2M+O2bvVyAsJGNnZU1lzMfU0D5lEAJ0DpLLJ/P4y+xu//DGr4+/rFX7R9TL41dw08f0AZiPH1ZP4VEeaf4oPR6/zbZs8Ozxz+w2W1oW/pv+lC63D6s2+/gf/Lr/0D5ux0BBBxpoLb0q3us8DrTVR6aMUwbccUBt9vJbTg7o2oDLmo/x9GpovO3xK4aldPArxhn/P+vas1VLHeKX1S4fc6qjGjnETHNK+sp5++G880SUPXmszvzksbX3ri48Zqazx9S4NCrdecyMHtvIY6l7LNN46qsemwaP7X0XpOnCY0aft5vaxzmt5+22D87bfd9u+5XzzNl52gwDaX3nPDc4b4/kvEDO2yYaz33NebsfjpCepjaESpa2tAEHHWNEsNZkPoFcJmAdf4SnirsYvCL8ufv5PD096T52JH9OlsZOQ6/LY3DxOrr49kTb0QZDLo7dxZ5MyF9x8d+wP8sQ+s+P2irzf/yokQReqniNYhWHVrHt8TPAEfvnb23sglD9/dI5QGAUQPO6sV7BJYDAj4JshvUHnimIqiOZWE4KvaMfx+/o8jvFGrtO9cC2IWF+1VhDLUctW1s/Y1zgPZNjbqOWLQXbA5DZVMRHjlhXEFuQydpmT0XA/B91U9TZxNkVm51R3J6wHPa0lqOWra2f5UdxnVvJda65LqYNHaTIdVMbzK2IaHLdjq6LPqLrMrluItft6LoY0L11Xx790kK7vtA76x0XOtoyS7vsic2ybJ42TWq63rTY/Fl/1qkmmqptU006o0mKQcUOQFZcr5lWZW5TnT2uVxJImeBctmMLFsdK1gn+TBD5K8S7a3Nr03bkVLCm7e+1WW7JPHPs7x3fMokcbg6Hw/u4VzdcFEc7HVrkcNMcDmdkZziekc3jQk/MJjwjW5njEnHycBwMnQ5TgdyALZEpCODMYRf0TYHA0oA50sYG4J/Z2lA25wxxd/5TQs3+kaJFtbJ96I2i3Tw9fsN5R2JfUw0xoWoQCDkaI00PRfX/v2GT479zFQS/YSfUf8O6i8gEVqT9Xs1sm/6+mrG2GnFD/9s2fZ/+YQh1T5Lbpr5PkjCEvieJbTPfJwnYEe38VJfxk2Bz5dUDqmcY1h5fygcCS8npAV4yDKovwQYCxOvFY6jBl2pQwUGPpupNLUMNdJvIFs3jSdvSB8KDELwUCFJtAnlCsrHMlkosOMnWUtTSnGxgsIX1yIO722bDuyzcgF22lqKWZnwBi7xWmlrgTC79TO7HmVyiPJN4piCadI2htqqCtsAfxfoo8kdVPG/HYVZ4aOsawxaprEW/WjRp9PztvahH4Bv+aKqPdDv9AQ/36sP9PUJFOOeHsAvzeI8gCewGcaWMUHEwkL+/UsBA9rUrRRzld7iUbDBgutf7MGC4mNmF3r+QjdN5ZvFe78NA/jW9717U+6ACNoecV+dYWOlHNYIJEdj6RzRAhOQHIJaQxGVNWyJEvGBgGNLSkIGG9JwSoePAXmcE3DaZbm+jIIAtjVBi1iAEmxP78+wtRsvN48fkuEJa4srotxmCLLsx+m1OqSyrvVsGlnUTsaz7T1hWezPfs2y0/vssC0Ms9ywbbfg+y2pv53uWjTZ+n2Xbct2wbLTp+yzbHFX0ZmkJlqX7VIUYy7YFRGSWLDuvK4MYyzJBX19C6V4HbU3bn7rlxLKkTivGWLb56EAEy5LYrX1LljXMFry+1Uliy9Izt3CWbWt+9ChYNuuNd1lvYLVLbFl65hbBsi5s5UWV4VCq3E+lolPpxalUoSW1WOhW63YO3WodsjdqXSnIEp+WAE/cvS4jdzv+qDJEZfiB1sNI64lonR75B2N2GxrDcyMhVp5Jf9dfJ/25Bau5BavZ8l8tjoDbNH9UhcXsecqzWjLzWe5LfSQsAdfDIu4Xqp4YeFGUd/VzlHlXkeAdGXgaEzctO2tO2VkmCGBPlZUMNwpkAaZv5tjdCgUiclhqzGGpnsP6WgqUHvmTpZVdwo2iWBRdVty0CkVh2p6VKTYzptjs41/rj+NwhpuE3KLWK/PSrXnbYJ6ZBvOMGs0bTq4GZcqVkk7HdanazLIXPWg1hLIXOqdJICWazTWPELadITx50Rmjrh2TWzpHLZDSXaipC1zlA+Eqpm3VCu0TvoQyRptouXU9f6bNIZcQ6fkzHeYgZkRZMz3bSMjSxtkSWrAyRGZj5IyqCRbzkMFypJpQ04U65Ci80HNpiTJCiPRcGoaPwwky4Rk0t7uYAHEajVMcKSZAuK4L4QXCsjxhEr11SavjLN8hSauNt2KFel7VUF4MkZ5XxXPTkSObCqImYRIofET40flOE9+FS77jkanxnXUnJjuz4jqw4jacLbWZgRULd47695oll5El8z1L+pdYslQFTnL7xJonttTDFVkSqBsJdCICPVhT0u0n6l4S7IlY7ciibmRR3zoQ85lHgi2LcXuZcLHu6HDDvHPP2fmilxnzCqpD5hXBehqDdWNewc8XRbJp5OdVsB5Egnx/A8rvuAGBX6YnEmDeLol1lADzKAHyvQTwL0mAcHbGfH9Xy++4qzlXB7tVGcFf6SEz1PTMWNNTo+Dwo+DQ5JeBxu3JGeHJrTK/41bpXLZPNM2apytnpMEZQwg+hMs0Chd1UYhvVUpzEkPCGfHJ/Te/4/7LbqXlTLb7Z9mRRzP0ZjzdSnU69BNi4u65cYhdWJv7CzWW1o20KhDXcF1UIMI0HEkUREjDsetvmQS7/mqTxDhcWQnjuLLq4gXHIWXFLtPFhXhxLr/dWoFaUVymHVZB6b16O67vYStQKy6ijklKFxeH1zFzPoRhOfFcgWIEOBCuQOFGvouXSJbpsGwC6VI3RflOF3kmBY5wyZhEb10yQqw+tFeJ2kKBpqOggZvyOj9TvcbzM0dOpPbHtVzOSiCkgg9ZRkhXhl2BVoTpzLAk8U7XmUhw+jhW1xmiuuw9Q8QEbe2uS10XUiRE80tCo/8D4coZlOcuXqKKvs5HxrghpGgba3aEFC1TwRWpxpksVXBFqn/KzoIAhgNBXArwo2tdQ1o3XmpdIWxbIudG2L6gZovm/bqaHUo5/lkpZ5Cw6XUJqx+v5ICmV3JAqH2D/l6CGq5nxUB/m80hhnSrF5pSCsj1mYB8RTXukg6zfVKdzvEdqtFl/UQ1rmnr2sC8pBqHItOojliha5CK6eQB96R4nuM7pCIejPuE1NV94kIq2scruSn9Um5KXX+ohbf8O6kY31GAwPh1J8DiewVY2d5NapV1PppeUTO427JAwXhZgEI8vnVdFih9X5cFii2oWoopreXV0QpOlAUo34LWirJAtLzLKmhql9jy6mgFx0VO24aYK8qnjFmKDJJptiCQ/iEWT8BloXEyqR9EmJLx4h2W4mIZoYJ0jcM0SZ0k0yTZTwwRHzZh0EFpqaX8mW1gENcrwJgCYRrHSaQrmUA6C5GuV5g2y1poHKbnsuaihAmZurRMyGS7M4SrH4c8jK4LMtMXSZsViGdCZxMF0pUMywGuQegVvxuBsKxdzygWhOuV2cWxPmxJraT/pj48G3/Pc2F5R30YPXpDJGF5R30YE8434Tks7wjPuFw34RnE+Rvqw7T1auvm/lEgftZxARHxd+q/QNf14foShvw6aGva3nTxlggKxokAfXQgN0RQ+r4mgmplDfp1ktiy1HJREAEVGdBaWR/OvMsa9GuX2LLUclHWh3NNzA/1YUenMn+eL8fk+GfXinZ3UGNh+bMqsuJVZJkMT49XPgrzzz8Ku7k5mPHmoB+vfDI2jdVjdVk9/qxqPJ+rxkchOYwp8HhKgcPSpnyfu9Z26mnJOT/JXY+ZuIurhxoLja3c/FltWd5CwOg4Xo7WbjR9RueWTVwRZBY5jRbmxysJ5etv4OCYmHvdrq2KF7680O1u1O121O3qWYr3JPgvLFVnB/b8K1garhyYXqglX/zdRysv6zFLa05ZWlZLBgsPhVBsFZ+uZ5JdBeIl42yUQPpH8tlJhKU1Jy2QXq7NW+ZIT0S2hUbESGWcZ8UgroxzzgLpyhjjckd6UTZTxhORroyjFe8wZdyrzBXpyhiOzaGmywHiIhceBAbx0nQv5CLSP/TPIQuki9w0LQLpIjdOK0e6yG2BCJEss2iZbhsF4qm3nKxASJXCpUcJpNeFszYC6ao0+sARUqUwIaolV4QybzUW1fxaKtyYOjd64sb5X9WS13XkxumVL6zus2+X2bZ4n21bRo7MX//C6tPC8EtZtVYQPnNjG0Oy30zsd1Be4bmL8hvjOU2fI7kYv1ajHf+kbtpe+Ybq82wbGJ3vU2FgdLoilDEVFu9TYWM1uVHgF7+hwvjh76hvsleEYl4pZb6Wn7I3PJfc/R8zgln0RyJebeMfMw4DL0OWUHJW8hQl3ImzOjMBJDlrFkgvq/nFCKRzVl43gfQ/zONxPJyYKTkGCWYyRiCcmYJAWF3KJoF0ZsIAQwirMeWFprrkE//0uS5Z8g8VeBBh/GNXgRD/AOIFwj4+Mpkj/IMlqs5VhCdZ6M/SMtXtDmZaMoMEM1HdLh91u4OZ5kUgjJnmVSC9JrTPO0cYMzmXOMKZCfxfmKn88Yzqfz3jAjHTQsz0f/oUpSs=###4620:XlxV32DM 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11f4eNq1W0my5CgSvUwdgFFAhNW+z9CLNJMAmeWma9HLtLp7O7O7kPQVnb9yEanPC5AzvufuBHv/Zbh5sdf7p5Er/P+H3Bf7UjzENxQpjYoiS0WalW9rjiGZIYEbCLlI4m/xN7wurKWB4DFk0rcjeZ3PRQsuWnORwUVLLrK4yOYih4scvNnm3rx/WoUb2JPpNpue/g+41p6gBbe961RkcN93kYtw3/fUUbvVNjc8BnsaFrspXBRzEe777nMR6rtgPBcR07dcROwDkze9rqksfZX9AkTH1Bn1/g98aXkJxdk7le6vRUX9/kNBtZcV4bAEBPPHJSBYvFoCgrPjEhBsOy4BwcC+v2T0e2rh72TpMlsauqXw9WbptjZLJTtays1kKd+6pb0orx5q9DIZze1kNHcHozc/Gb0vY3iH0T50o+XRaKG70UdLBZ8sFbOlQk2WCkkt1as7WiqYqJbysKpu6a66pW6ydDoLhNin4RVhMlry2Wg/GQ3ziYz+bzVa/PozPyXg/QM2E0DC8IggaCYhNiE2KIKIhJiMsEAQnpAlIS4vvoGwhOiESGcwonRCVEE4RuSaEJnMLqsiIempmq10hnREUDHbiIyIlSDJbMMzsnCCJLOX0lURCJLM1iEhm7YYyWbrPHB2NxjJZiuT37N2BIajmA1ndIE0grLZcKwWhBNEJMSWDkWC8ISUF9mdICwheR4sbS2ZDVSQkEV6jCSzgTcAUVsY77HNbF57tCComK3LFLlAkGR2Hh+9B0aQZLYu8yAtQZLZ8JGWj3MYyWbn+RZaEySbDR9/w440eZ1y/1Lw8SttxP3lrLbvsj1F7CfGxq64OfKrk6OxLuansE/cXOlaHsj9ipvtzM3LzM2+c3Mj5ImFzTUL887CB2LGhLyzTshHFi5cnVn4knrjTL3bkXobzy4HUj1Sb5ip1yfq1XfUCyeuPDlxT6h3v+SGSqr4mGVhZjE2U2+k3GCCuKZe7rltlmoTb6jXztS7zNQ7jG6WTiRrjtS1XZMsDORyRl0zycqZuvRMXWIy70DFMq8rMnrqhlk9DHY1z2h3w6z7bJ6fzJOzHJCz2iosTeVAIMwq5NKO02Q+Ii8hrcYIJjxjMDJIss5QocKNEJ5YQ0QQJq/NKYJ0whPl0BnIIMmyUosJglAU0LHAlQavAeIwgrhwcQt50eDPISLSixB5iWVZCdIJD8mLgnSShDHlBOmEVw+JYgElL5gihysNxoOJwKOAWdJ5jprDFGWlJ0inNeEYRToVCqMcQTp9Eu2DaY3qJUKFdZ+05UPFnKYra4i5bRUEGWLOxEiQJuZgRwaRmXVLzLoNZnWdWeNHzHpgVDb5xt9MsuZDkj2w8ynfEq+XGrd/Qq7V633q4p7wbPhuF9cyfcOzUfF2/srdPOLZA7+yyRH+Dsrd5Q3lRhlOjH7m7d5S7sG1PWXfg4urY6q4XLGv6ZYapwn7Ui7jH1Ht8qU/W/b4pT9rxwDGD1k3/nP+bDE6nVnpCR+BMMydvmDAic+onUYQYimtw0qQQa7SBoIMb1JHRpBBrjpKZB1yj/WiBEH6KVxXx0D6yQ1/09a6WoAzhCDIcdbGY2RoDzh7G1On7Y4IR5s1YAQRjmUKI4MMgTE2ggwfz6yd3WGHYke37NiGEO8YZDEe0iEw4KucNDe8Y7NGjAwOh78FqTPEggmBIMOjtkySDg131nSBUZDhApdzsyFYesBo474O6fH3xr3IVC1f7iXU4Na1c+t+za2fhJH5HEaOSH+bYOv/tWHKl/b/dkrL6APTiPKic9IsNEhJU16TJp9JM1NsXu7wv/XlXS6Wv1d2cF7VzI16dkuX+u2v3FPgg7+cKAPncgjp/VMJnQs2WMLpbYpSUztZxaLHyQpc0/jUX8yxYG7McToKYz2/I0/jqy8C04v27S3LvhPWPg05s30OOftTd417uc0v1vXF26Lbe0WQ/b0Rz9VWR7kEGBQ0SAYwkfu2TZSJyF2snTKtI+ROmdx+g/MM+3Wfuxt7d+Xo7oiq8w+7m7fMlUKIsk+l9uuNQpiFS/XPTxWCnBWCOPRcsqnnu+097wFvAcdQs0p/1vPCMMuFCImKjZ5LIkJIz+WsjapTf9rzE+feH3qulmPPBZO958voed/AcMR/0HPg8K5J0nGB+Fj5PZ2p+tefeaelKu8/8ypsjzAt7RHszI8/8ic0W9klcxKRIMqrKltyrSSafsDRleu4hdTp4oT7uBNkiBMsDagQAxMselHqe3pT6Vr2oVvXYLhqz+oTdKw+JQvh6Uf6SE3y3mTqfG4SzvrUZMjE3Zu0W2uyPKUmy1NqEp5+AFcUUwJqMg8HsEZWfiriTuP4jaKDO+I3WHIIIj7BGIkgJBdh3CnSxSeMuyNIF5+qHL7Z7NTJbLYoEQXlcR0UpJFKk9aG/C3nbEa2jUgy7ltQoyy9PORQnQrGVAtJPKi0EWToK7MZgnQdB82rPhFbe1EoGlwpXGlIPNAnmjTXJR4MUOz7ShJRBtCOtlyi0nddNWXh7mZBVXGEB4QjQUaER9NtPMQzD3t6m2wImNhqdxntaxonC8qGyqwSYz5CBKxZ+BgqcWsqcWdfR2DC/iQCE/nVSXkWdkkasmnHnya4Ow05Yi5ToGWdbxq4ftPgRkNeXTegFwh0UWRfXzdgk6ysuY+nsvK7ryN8qDRtDqVeRm5qwC4F9vVd5CY8itzsl4x6Fq45MGp07EY0qvUbRKPN6dJL0TjegVUUuwn/TDGfdQ5UuXONHHN490o0qu0bRKPld0mdqMxZAOzu5sThLsTZCJzdnBCzmuLHuRc3OlL579CRWaqaSx25nQ3GP3I54ytpGZ28kZYq/L60RAIy7boqFdOK7I9iPMqDgKzE86tiWL2tTa9kCClIHCOBiSA6UTKEkIDduHtRKo2YmO0XHwqCdFbYCTLk7doSKrl7SM8B5xHjULTMbNg4pPSQqkxDWBRkGsH2JPqTxKpSB+NxvSxmc736JPqTJAI3WoesxwIX9nmPMnGayysnQENIxBPF5zhJGsLfjiAjrmn5SpAuE2EEDUbQjRcUO+QkMwhz2GcKZpNIy2ht7ywn0lKtNiIIyVsQyxa1h6Ql9z2uWBAsLVeCoHyiWgjS9SMYZ7oFjMhRMG5FUDYOFFBpLuDmiFDtLwKuRpqS+4URBEUcu1YuCIo49tRpeqLJzq6VcyWcUOyOQUawRDWOvKgJ0xSS8Gm4QVbqF3dDf/quPznSnxcXaCJ7ktu7vtxqsMh8kON7FLM8qFN3UKUoXPlQRKLbMliFIpF4L/+abjSzIpxSdcAm+6xxuuATelw0GSnaLPjO77/EJ8m4r6+eAiWym2ScQDp0FZ8l4x6F8A7aTR40G7JUxTALs6GaXOz8u3h6FeaxHuKzHlKH1GXeW/pKrEg9EoKRiJWvZEiNbIlZmVzn1NLk8WO4WjC0poZC3aApVlwhw/aqees2hY1sa5Ku9C87594SzpehCYX81lQ5naHlAFsrYeQ5wrdZZLs7WZHOgHU2G0IZcIvICHIhVTqCjCyd6Zc/CoKydP2KR0GGwDHN7LwJCPu0HFBFBmNFKwgy2KcHugqCk1qbI3UGl5UzoSF5EMrwwlyRCyV1+MYdHekiQVD2s7FJbh1zhm+EVpARzOBBS4LgnGAgyAnVVWRckBE+IoT0aieslgvT6kNsrPFQoeSbDtq9eLoyurwEG7QWOq0pQmtX4ZSJ6eTMdGG+xcJOme4Dhjv5GYe7+xnHxHDpOK1BlQe3WMT8mw3e+a9fEQWfZK1hEvO74ZGnV0b9aU4OvKuNXwdEvBk/1jDuUTxkIh82M+Y2M2b8ijHB0Jsbo37pVx6VDL/9Ww1391uNiTAtMVQGnr7FKWGq97/Ake6jKcPwVQVOUoKkcteZLb9sI0cpP7v6ombyk1OfDo53MspSU8z739AR8ZK/wNREvqt55W/+XUzcy79Bwwov97Jtra/bwddl7x1hxPTQS1rAIuibX5MIHcRYqfvvBiwe3nkNX6TFwAFq53jeZzhntTZPuiDoDkno9/fTEwkABCkRRK6+9CB+QQYRL5zWQQGAbekmkMujda81pFBJnuQ0MfAFJ3X36+ILprE5nar/DiUvZHIvxQmMoJzKyheCdFKF1jaCjKwOM3X48narmYliTOnB6lBN2oPi40mLu+BcCh8UrbGSztnku9tSJ2o8lPgGsyQIyoApTyemqyronCDDPzIy6yYJ0nUQIJogXTsBYjGCHeqNo5VGh8LmyVRkMnmTBdCmw22O68DabStevUPTwIr3BOmaBpCdIEjTKLIXhqbxrgBZvbZFUNM9JcGUjkohhi6JXZfoBxdu5Zzu2d8PftVyclXoRKrcZ36Cf3iL6ORnp/4uGUTk0CHZwx9JFvZ+cAf3Iu9jcN7ngaDZ3k8c/v2Rw5/O9pHqCfrud6g68EEY8VraFP1CUz3h/eR3MfsjlXMMdudlfZn1sd+Q9QnqRkgJ7c3JuAwl9STecPJT1+0uEXRxkUiI9e6WT9pyTQyt/EYMyUdiSLyfXAnmRwv5TRYlnQAtuqTiZ6LEP8qisCfhC3GMPeXNeQhf6GG075b6R+GLmj7J5zcsX5IdkWHtXvjKavyiEK38Hwvtgag=###4564:XlxV32DM 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11bceNq1W0mSnTgQvUwfQLPEJ3wVR6Apwpv2wkuH796akDIRUPxy9cK/ZB6gzBQon16KoOmLvNjvb4xt9MWDi2tukpcmYf3zi3HJAK4lX78baypiEcIyohNCnZYIoRlR5RphEEIyIvM1nnuICJkRUftREOFbRnhFxjXkJag3CdpIgoQnvEI0aP8yxibEuIRIrx1EtEuIzggPerjKcChiNV4AvIZCs2oIRnIoNC1uWY+QHApVwyccQnIopK93WyBSQiFZsV00C0urWPhd+61AXACoGKfDUpGIEJaRbILYNEZoRnQxgQWEkIyUERROQyQbp4OsDhGI5HHS3pV+rIIht9kCn20r/x+IoC6b7U0xW5r9dqnVfKW6esQBVH2VvCIBIbmnEjqxGYWQ7Kukxe4RuYJkXyWpvnqIFF9F9TVQiBRf08+fPzYdyEGl+iXTz+9/eVTxtRgZ1394lOHFolr/EYLGFAey/kwepbPXH+nq9DedokwKQ6BrOiQkOOR9PiRJPVtSCIUCMXgDUg7lMKU+vG5/t3q1d/DUJZ8aYF9ppPMhBQ9t5ZCGh3Q5ZOAhUw4ttbtIy19T/Fh/GAGvjiydapDRkZZDHh6S+ZBCfcR8SMMARFIOoXvxdbXSlPcy/yO/a/jT9WzNg6JeNKQnIx+NL8W3sI8Kc4fRYGQ7jgYjaozGz/Rs5qduTYNvWLZe4w5F71Ase4eayN6hnzqMc4f2avgZccfhZySA4c+vzm5ezGdJbJ7t5umtx4Pzbl48mkfFZB6l3bx+SE5m0TQoMFra6tkcv5uzMdqjxfvwcDJ1VIYHhYTquW9zHpL6uuIRS69otYHJNBc1G4QeNvBjSNgcEsankDA1WcroZClj3dJ+SK7A6F/N6Dr9xDY3mjIzobkxwiSF5sYIk5TYFoMQkKSoR8hIUsIqiIwklfKAhEjJ16LM29ru/eSRR+mrPpkZyq38jCQo0pEOeYOy3fV6kMlGAm4IyGRlPhlXk351z2nUUdg5yGnp/xQiI6e1N70gqYXSk+nG5FbzxVdmtHOmchXIT9RrjhCQnwrt4O121YN6zshUlUz0c5IH7ZyRs9rb1s9JvrRzevb65Zbqbkmney+8AKwBKV3sAeQt3+VApMT2Cj3bKdKznf4429X8dZXtcE5EiS/wu8TX75Vm06vctz3KfXrOfW7OfUvPfTAd5gC565yQZhh5MsOc5AR3lxNw5sBzIblLD/2QXw/T4kki88NoNYyOaGrGmWLOnFTNmULPRtt5Al8mo/OcjqfFMVv5S3os/RU9lh5OKlJJiZAxqQiL7zboMacWIpAeB2gcnErqA1IRd8103SXTdZjpLgQhYCahG0IA07WoH8R0oXGQ6VLvchSoey0vGse7T/u7b67f/emFj/MLT9Ybpgvpran/x2/oNr+han5Dlzw3xHpDzDMrG8U8U848s1JPV29gXGW8S6h/bbuxRa9auXF5gvpdfDkEAxJtOQTnoViYr0Us2pVDyO4Uo58Lq0FeSpZafwgmy4H0YpeZ/IISM0VEp4BUzZR4moLMPAUtmOT58jjKi+lPkc7BVYxo+sN3DesN7z1jdulhOWGXsnVseee6zA+uG+Bg2jZ4pYefeXGKYll8o3Mw/fCNd99yd5DA0pnAsnmW5If5D7unZvdCd28Z7o2u6bvu8cm9wY0VkWfu8Yni8pnizu5l1ovdM5N7aULZ3bPdvTRN7F3LN92T4ZjjGGEjx+kz6r8ccxynM/UPM/V30/PL58TM/ByXeIyLPMaFpedsj4sZcemvbxqcN+LyS7iYp0j5+1t5hTKwfiuPW2+a0ZS1+b385otZE68KVrSeNAkVhusEQKrWk+apmgFHMgv7esayYwYMUH9EGTBA/TFlQIkQoD9Sh5CuP6YMiK6B+qNAFgz9sYmMe6CyyFjjtLdMb0koQaZI6B4J0yKRckYNn4C31G6/ZWuZ3pJQu2yvajEytap2WU9vYdQG4GBZKLaNI6QvC5k4XNOXhckB2R1Qu2wXa0dLV8YWOgxRwxANcEDE0qhFhIzVndAKIZ2IJUNUN0Qj/TBFspOdlIEgq0pQJ2lLW2y2eFcbFyLBpYBbJUsw0rlV8ku11VW+Z12l1XM6y5JLXzOWcwDLEiAqDK/IOFyR1Tu2hZeSlX6J9DPoF+v0a/nU0ivwR0zMT8n3Zr01LbKWNxdZZyurN4RFOQmLVUXEhI/MhI+eCosHYjexuXBkczvnUzN10zMNNAfOl4da3y0hA/nsErItDj9iWvZqsOd1oxK360Z/llPJFb1sa77ni8X7FWI2T92qffHTat+8rGV0VvvYnPL5B2rf/qJf85Rwy1MmS6eVVqMw2FI/WzqrBpnCoAW46tNjah3yuAYQyuOCIgTk8Y0hBORxxhEC87iDCMzjSkBk5PH2VFREHeVUCCE5dZS7CgLk1E0iBMipTCAEyqkeIlBOVQtEgJzqgUPiUu5Q4kruKAioBm4UIbAayBACqoHWQgTKHQrdDcodajwJ+lLuUPpK7lAayx2bQQiQO5hECJQ70N2g3KEZRIDcwaTJUH65XoyPfMt7vt1Avn2QZ8llQS/QWdfks67pVyB+YF1Trzcp94lU4mapREGpBKdcMqXcml9xLY+tNxrLnmcv1RSsouxJVsz6yEcqir9TUYZ00iUT4ehd9tWyKwmCqPcE3HBd1IuzJkBm1daiTMFkiceF5LFF8/eSRwqGuUnwWtqTYJwIw3q9yfVPBBI7CyTqGAx5LZBs8QsEkhSM5YZOaOnOgjHTCTbTibmeWknHlbJypoClCOhrDWWL299rKCkC2w030dKfRWDSUNhc8ObkiYbCwp2GcgiGuRZOtmi/UjgpL2KVSMpj2Jt6NA0WTlp6Yb8bBuSRFuQElVbbmJTP2rnVvpWo4Ihb7bm2IZ1bSU8lQjq3SmvqDSFgj5ZEdxvcKq3HKETONJISk6KHlJDsLd1bBmokKRykh0MjjURKTuEtsx5Sb9laurcM1Eja21qNXEYY9QijBTjiejtBbEjneimMAiFQI1kQ0rleCqOEyOB6KYwEIoPrMam3Hg6JFJc2I9eLzHBLDrcWgCMuqCRCRunLU44QqLhohIwqupcUIoMLJjoSITK4YHLLdLfEQb+hoyM93BLDLQNwxBWVQEjniskthpDOFYeQ1JDOFakXESKDKya3AkRgacxVnZG/lhcTgyuKzhXt89LYe0TRh3UqjV1Vv09Yonm080vdVb8BS2Qc7wDD5I//bYHth9nIdaFtp3UfFdrCg0LbLuCYA7e8KbQFZu4KbZq+V2hbzjecBabvqmua3FbXHrDOVmWbqmuuLMiuqmt6+YrqmrJ3WlIQt1rSHdWcq5Znm8jU3R6EQzDcTS1O6y+oxW30phZHg+38Rbm7Wpz8TC3Olb3ZV7U4bb6gFrdRcc0jk3udSStFbnikf1SLi09qcU0U4wcCiuMSb2pxevvSWlx+4VrVLT9uvelHM2JKSV3fcpLDCziecLLRiXIVrNK5Xjur14Bd/UwhZLDMjcJroOy3J8LWEWS1tLPa6gSsgo3CWva6FtGy03vL91aEpDG5pcEti1v1e4BEn1Ao4EcE+67+iqDCn0MODyIc+8b5PMuDck2irQIigC34GFuBqCClQJRnb8g14r4dviFDy+qrg4YM/cvtXwuU+7ZiVgmbbbgBV0K5LY2A7eEKB/ZVZ7R9BErNsYxAa/neiqgOue3EsbSQlLpRASBYaOSEIqQTb9ope33mEe3dPwupdpWxZoX/GfA4orolUhEtJrxAebQHkmwBAlVWxketM18EeK1wDCJQF2UL6qjzZ7FtESGdc7tFwBpgfQD2GmB2KL1IIv0Mnik7z3T/4/ZLHz/67qAxmXPV8aa6t1xX9/hc3WNPPht4Vt3LsuUVmxyC45PqXnxU3bOlule2/l5X9+z/u0GU+MffDyybudmwH7ax38m6ecP+O3W75VgCc3d1uyDPtqPOQpuc6YF4tEv/Wd2OHo2+3V8Unu0vAtrYg7rd2aai8AGR+dUsrVPPcf8NKHMFrCCB0ljAXwYyhxBQncPXgDQsnITISMNiswgZLEZqYJs7TPQRIUCwAZUxdxB5HEBg6koTvYYXAV2Gj10myqG6nXAcddT1n+RQzyiaHypWESHwUzQDEbitv9e/8tsJEoocnxTk1lWhTfOrQpvmSDxZUEeo3Ki9RTb07Em9CwjpGZf7zSEE7K7mDpoAdBXFyneJ1LzSdGNGvlM93/nPfVw37z5uKZC21+5GYnn4cd2kq6j1SSHu9Iu6jxLUofwl58T0fCfK+nMpJGxN0ed3n9MZEYakId/7nO5kG7FC24hT3+xa6Eh9+yF0hJttxPZqVK+EDsXKJCMuvpkzUpw5fffN3CQ90KOn6ibJGhFPPD35Km7OYmdlNHPhNJ+cZoQMG9yJ09xMqWseaabnfGsP/rMwr6rBU2bP/F+m3Eje3NMCE2KzIU1BpQUTonChbfQrQSrruHISTHNSbeByuPAW+2qsIT2dtpCzdt/61Vh68+pFCkAgN7ZnpSIKL07kXvqpF4GSjCvzUfFA/AdEipMy###4688:XlxV32DM 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1238eNq1W0tyJKsO3cxdAH8yq6K30hH8MqIn7w566Oi9P75CSjLLdtt3UqZQgUCAdHTA7GE1e/4wQppa+mmTef75LbSTD/YQb0PCi8RmiVIqEokoki1LjFBsSHJJppCy6OBVJAU0EkV0ZBG3VdOuUSsrXZbEUDWJiCVKF026jc6i7troNK9ttCSSMrr8UYegQKLG6GIbgtNI1IaQP2p3DEvqEFQZggqpdCeHpBtRdCPmjz+/Q59Z/ipBKqvAdEHawfZN0Ob1c/NbEYjUBH981ldEnD1U/nj7nzzM8dg3Y5//yEOnhzjS8x+l+PHYPHv+u6mi+vlrU6VV/onZHlkon7lKC1SVjloV8a9EqcpFVMVKleW4iteq0ldWV8ed/3rR1HqJfxrLT73qIo1FqYoMrvK1yvZfb7Xjne/lr8+2So9ig7wsb23muYV6FnuYB9+ysUrt8TCS62EQKZ6/8npOHUKU+ViFRiJ4KFV1uaEq2+bfslGK6j9Fd8glTXWbqVsM3WYuhpTnXoWqijiuErVK4CpZq2SdfTkvYwwinOcvGIMxKHc1/22Z/w7zX4bnTpMW/jxpwcRUuF9Nel96PdZJB5j0xUx/9w1fj14eQnMZeX/V82oSEtXjn/dQPa+SE4koEluPfzVck4R+/POuap4BRDIMTeOU63HKc6t+ymvPrPTcnJHBPVfvkfd/c2AHlhTvkY9Bc3pYZZuB2Zp7VURSZmC7D4VZ51KbQT54rTuHRG0IqntrjiV1CNUfEgeWwIGFPjUdqzvaujuyAqTNT+3UT/nhp4SsLkGIR3gIOf3UBn7qwH4qx4B1D/IYz7uFx3Q+Ijwe6IjYuPW/rnUYA/Zyrvw0Yc+T6hFI2PPk+FaqsMfMga1UYV+Y42Op2pu6g/e/3fGJNhzwv9SNcnCj4Dvz39D+boH60j21esdOvpU40GN1oBEc6MnNEl/67y6aqfYaZp+/VI6D1cnqVEO8JI4ujTMvzBbByZg4VjMf59OZZ2bxamwjziUr8os3T2oqCkORFRYUxbMnYWFVFC/dp5DHtrjwDCmawhDV0CeiBH0Jr5Hva9DinuJBEtvlOR3WrXPyw2HuM0pIDkchu8eTh87ee4lQao1QgtrzsHadXpy6GdiTKXDWbOnVLs6ab4uJubkzsVnHkMDEZprYwRD4p0xshLbL/kQgwMA0pQ0EBNA5TZdCI97FpsRhfgMjKk3DPF8D+E14K2Zal+rYwEwazJQYKNGfNNN6jDFW0BC65RYJVqCh26/g5IwR+LGCkokRZLo4xg0jEIulVdFxt8f2FZRIMJ6cxjOgz33GeDna8m0EztwcY4zQlL/9qN6kNHn+qLseinYW91b8WT///O4eT7w1WcEzP7P/bQrjiMd53UrgH6oRiJm5Vy5REMMPNF4Cl3pI7jrLZIvSmt9EJtFcsl36VEbJQmmvpZ85SrVpJOjStmnkONWG6NEQMU6SRqE2bRg5yJXudIVtMIx8avsweslCaa+ln+WjKgMYpTxBbt1HVFEuYbSUDSSHpbOoLG1rj2BY/u7IbwT8BgBZ97ZZRS31pDa6NlcOczV9rhkjNNMdSNRMJ2Trz0F/juTPkqkO1qqogrWqFKXs0m14OChll85oIoGUPbcxSCVKvnMbhSUz+c4T6Eavm5nk8tLsMLdtTDsWTcInBa0izpKzRKP+UDKvk9z6rNM4Ev03kNZ3rDL6rUbru6hu/tCRccvBe+sGYT3KwbthmiAQ0ItaRAJ669lsybmpmMxlF+gm5N075JWMEcjbkGpGqPsVdLzAgxQHnmBbUX4BogamiSLNgCs+g2nqtMLac4Ke4+x5/0worz3HNcZu0HOYPR+fiX6157TGIgk9+xka9GdCQ/aVpu+YH1UHct35u0GSk4NVzbPVZarOtJp1lCKUEnawfUe1LiN2sPm7QhLiRlODf0NZcZlNWS9FKCXsRvN3AV0G4q1yhUQi5K3ydwYST856ruBIVBvl3V5PSqxuJSt5hHlSHJwUfp8cfiAjTIxkhJZmhDTX29dcz0KutyR4ZeDyPifiW+ITc/o1J1pSFksQVO5d3CdCuXf214lQukRQWaFep+OnQnk1nWPJFFYu65SS9AVXNynJlsQVNmRLr/Y1WaRsj0l1nVB06fqbRJEgPcmdao2KA+qPCNttPWqOQmdfsiahlHZu5ECkcYyepEsfZ1N5orBtRB2jWNf34JglprD7eg6VGDuEPaEI2Pts8exAEbDPr5E4jtUhZNiVP+Y59XBOxeU5xRlsp2eUXs8npnqSXKmeuKw1PvNrAL2mfMJK+ZiV8nGv3MDJWewnYuie9VGdvSbeqbE/lGrXQLUv/DoDfp3S9+/AgxsKPgEFf6KJ3iOTwplMEowDmYQ5+xd8kk1lLPbGu4XCgzQfoA5FvBuhRBqnQyiR7t2IS2KLS2L+bkNVj4kTyz3Fe37ICvMN/JD2x2oMcIjRQ+avkicOkfJDfuWHzGoM93zhSaFqf57twrezXdI9qVM991dJnWyXuNhl0i7RAzenWSS0i+zHnxij0y+EyDBgjIVnEIsFhD5Z4Ij3fI0V29f5mmwBf7YAolGil1cW2Je7ncXvDmYFG0Oux0TEZWdIvtrldGJaqLihYqzYv07FKB9HxlwWAWFhIXsI+1Fth65esmTHknn1giiPctgbvVG2dy8do65MDFMebuO4XeUjartWOkZdbTfBdf4e0OgxXhduZzDIWINvTToLIeITkmBiQ1hvSSO4rRH7wCpdAmyGMIpKgMPIdsKK0M1RlhA98+aoe7AmOSjv0fxEnWxKNJPwEYsw76G9Q/0h9NVPxJQA+ureYkqKnrTXcW+kN0RcaL+TNvO1Q3P7oq8tyWV8xKKZyxQDcdzd5E6EBValRD6E4LoXmZKip4KxHiOHhLAqu9pIo0mdGO6JZILISVLWGTU6sq5JLx5QWzYsISmFHU8y2uFBHN6uybGarKgw4361S4C0zP17Iim73PdFxG0IZ9kR6FsfHk6pfWJIhPLwvPQcm2O+1pgUaJPAC4/i2OsF94J1A2Bd+T7WTWzFuvz5mcxVPhesGz+Odf/6ejO8ut78BNZ98cKkYdz3Xpi0dyjvImD+9wg4fAgB+xUBH+9cp97CXre9gL1CHvBWw0j2AvamFfYez1tiYaUAOFuCeEHEBNyw/R72OvY9sFe+gr0uXIGbFfa6Ffbuz49cYPpXF5i3sJeFe9jr2HfAXuvEC9gb2ORH9L7CXoxWz6BvTQeunh7x50fAsDzZhYd7MOzYt4DhbXsBhkNgFznjBRiOHwHD/SkSX/HxRy4j96sXUhKM8R0IGEVztkMIz5tzFPks5tHQK8dmyRplc4lE2R773nqz6yhbRDjK7hP+5f4wOtikJ5KJDnbmiGSiA6s2IgF0gIE62wc8Z2GUOJSEJ9Q5Shd4OKULEusi6QIZ30wXtKugGkbRwD4Lo8ShJDyB/S0sjFEQmr4d+QpGnDiB++iQCEN4D2NvkgnhrbJEAlkExkNFMiE8xkNO0CRipiss3CJ4Ru4C5r1f6w5lEZuaaFxiBC+s3ogEEHwPFUNC8wseSCME4SMjkknhIgTP9hOCt7gNQvAY20uSRDi4pC3hHSP4Fu6HhCJ45tEQyL1oC72zv3n76WD1mgRlESNdaZL5XlkYRkY3EXAedyK9jSSipPD1KYowBQGbiYAjIGB1iYCvno8OipevSFisFK880cX/ObW7fYjatR+Hu2yFuwLg7vL8Ty8Yt8Pe72J5F4w7yNovYVyMl1/B3VDGZm7gbo6fgPBCInD38h1yp3b5CnvFSu3KE01MCKoYXlC623dgW1fZmhtsm2cOd4Mq6v+C0t0+ROnas11eUbrbt2DbI73Atj4C76+Ve4FtxYrh1G0CJNZXp4K/y+665F6wu9t3ANr2oOYG0AqZ4J2GCvFTgFbyrwNaDI6JXdZXiojd3b4B22oHb7/KSe0cahy8almYXuqvwIBXTQNglRLhVQHW1h2IedW2I4eEQC+EYY5EIFGPjyCZoGwfILlLEK86AdaRKK86QdlBX+RPfFXnjxhSB5C7uBqCiBxpRF6aOZFQK8yrus0TyeRVnaRtJq+a3TaWoP/GMpBgtDYYlEUsQQCreWXRV/2Gca0bYuI17fR4Q1ZiDX4F5oAvbxKEygJDEorKtCONgFfNiqgEQJnw411Ok+B/CIMcrc6oc6sRGNe6S3txvBCFHM1N4/Zr+MGROsOJBDKn3CYRCWRber7dc/DmYfCqx0CiDh5hrrzqeNPZ3zfNTKyuSLseiePKpB7RVurvRddMrP4GZWK71HjsKBPbGLEE+p+ZLQoy35F3Zjdlj6pIFwSrJ4JNgGD1lxBsPO5fJLxkad+lZC8wqlkxqiX/cfIhYKpXYCr/8j/9rjDqF3jYuPKwxxmjDthqegd2BbmfeH7g9CtgKpP9MjCN9w8MTkxr2xp3aPRbmFZXGRVzg0ZlUhfTrWj0XVr1AnquaKuTrwtNZuMLLtV+D5daWZx7LtVPHC5f4E2z4k39/Mt/4+Tvcqk2HS+g57dwqfbQL7hUPw8AtssKPdeLCMnWhwX8/pVFfPc1QXPkd3iTfQ/eHMGsnMWGLS0gz7IavXQcBG+2dSrBrJToPT4QVmUHErwJvGIpUbw5EeLuCN60PBIJIgHhIX+TILw5UeXuKN6cuHZ3Z7z5f/afn2g=###4788:XlxV32DM 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12f0eNq9W0uSJCkOvcwcwPk74db7OcMsygz/mdVmalHLsrr7gARCcsIjozpzus06g3IFAgTSexIey7+sVedjNvPywxzb8Zgey+/VWhtzy+T/p1//Mqc7HlZPevm3OYNb/mtO7x8n/ncsRX4+fLDr0pTF5XtwOvfOMj/nvvpcyqOiEMY52zgu5ZaT45g6wnFsTbk+PClPy/c5bEXB93le8XPVoNmqDYb4bjUoXn7/9HrzZYhff1nr3aMIltK01HRrbyZsfoO/v3/aLSrWOQ9b+9ZW7tpaCVrfyp/cz9oyIf2rqs/TyqJ4FNE+Wa5yXptKbBWVtZWg9W2eN5wKV5lXnCVpKpIpuCpxRWNSufcU7CNMB84ltI55V/O+5I5rwI6ed9yyDcwe9KMcBOwZmdyqHeaVH5YdhC/og+aU6jKjrpabmAimG/VeJDEapjWrymsMp0KRlaJi0RhQ5KRozwpVxGl6WqDHudGMYS6lzdYZU9GKc5lnqTWLwl6NU6eZTWLQJM1OddSmFA4TrD2cGtdumAi3ShvsZNlUcS+CwuE0DWflcBp7kk5rLouMOCipLr3KoGGvM1WsKwwajhkNs9Hy94vSGbvOTGldZBXpnfVFrU7jUup45ogXy5WlbgkNl79ultbbgMBXwRGXNlkU4AnOttJLMx0K5ipY56Wd7yyACLY/1EPFx/7Q6lcJKOcjzuFcMMwYRQFlnS7RSu07i1b5ONTPGUJLNip+HjPrcoTS5Yj41VPVT43hSWNUmj2qmEN9TmEs1U/494985OvnXj8PlKephrvAhs4huDwC1T+yS+CnRpURdqkHxDUfrzI5xUOuOjC0Ty3cmp2so7cLMGxXYFCHfRcYcgC4AMO03gCDj1dgUEcb4TgNAcNuSPnxJ8BQDDGNhljvDXFeDHGOhtjfRsjrmdMq3BnCj4Y4yBC6GyKRcvWHhvDnYIjT3hrCaGkIWIY0xOk/MESfqymrVuhR4+odHINDKg/Lf7Jy/Zh/WRcy7Lg8RG6tpRVKayutubT2B6j4fZ1HHdyS72Ufqz64qfpZfXSL9TO1yVFjbY2tNaqzqRorSmxujdQaK+3sPOzsOdPOqs59Jpqw+9OdPa47q6fpfmcvJNC5f4YE+vCCBJ7T50lg9taVcMxfwTowEQfrKcQGydlDCMciMQDXGZnu6BmJdxQMasB7CuC1NpFku4BnIB6g5KAKe26spxx0RgUzKZikAiQSrvOEKCF9izMTSQpxspXIUastJmaL7NHZin6+8u/Y+bfvzbk3w8C/O8kKgkXi4UT6EYmbOte5qT1YV8FNrSMulTtIRpyY1sqIsxM1RszJeyTy7qk1UytcyDtR1PIdRt6tU0wiMgVOW8tghbbOQ1oSKS3x1JqpFURaEumsF40X6j1LEafeUYo69cb4TFPkzDp62YmY9ZYi53/oAMjmkuR/JwlWwf/ghKFgE/wPdrPyP7MW/mce80MF4n/zRPwvvuB/58j/KrnjfK/xvBc87srbKg9cLedvJ/A3V0X+GcXbXlA8Ru3gwPxtamf2r6V2+024txAqXjGnw3kaYnWSNJkLaRJ0ARJa/5wumEIXXCEE+gHf/JgVNDYwov6I8QBk5hWi759HdHcAHbFXRMchtD8T7bPisP49GFxQgKyVEBnZ99SWdtAofkRk3UcJbRSfD6/A+6kyucboBP7fHQivX+H/+hX4bwj/jUxWrSE8LedClDASMFsQGYqomkfUim7tO4Rj+oJjaapfgw3MZlr+AiOXVg5eDoerSACSirEw3qqxVnEyOULs6kG7OYSk41nLtXFcQDGqmhiC9DJzCTwNk4qbcOBB/COTVKzTEuuSZYo51sWo2GzykSzzNLiCk0usKxKLfSY2F1GhiVQRq6KOZhjL2n43vhJ8L2wYYgc5HBXQANQB3jAxiewakSOsRAsdEaxiqFre2AW8mV7eOBhY1a0CsHKnK4dQFcdWUwcrRWCVGFj9CKoiEvg0IZJaLu6tcphpPknQdizNPS9o92EBpPrXBcUadF3QzPNH+/JOzSKbAfDLXvELA4GK1vbgdjIQk4bQU7oaQk/xagg9VehoIe8cg1BBPxqbEu0wWYl5Qut2NW+DwTeKHq7ovw3ueQ7Tk/WPwf06pxLkxUrhsN0EdxXN9mSlPbg3rWYaVqqP5b2U72edQ/H30gIn+4ZhrhoBRacIWca0LA56sThnjN+FhGKjmcAmpqrDyIvfocib9SY2JIs+We/GJT1i1fMCEl+Tv2/ZMbHTykQwmfIHBopCQjBUjz5KalCpYS6vwLYVeNdWAN2n0n3CIRPrDvMsf2DImUvK2sqfEo5OFqeqRohT68TjFBoL41Q4gGCu+fSovccpTXFqeyNOmSFO1Qj0UZzqjnThgRDocpyqXnCIGDhDYZbHowMCxMHj0QF+e1fRpUe+RC0rApkrj0TwPDU82nlHCIqeqz+LGebAF3hOS6sN06Mc1Fs5+JJGUDBRyxsZxSWTuInF9CiHjLzbUI8PNyFxm1wLFC7HOB4SRThW0xiO9+WdwLne7beeDsH767n015SizVRT8LY6iGxCTEvNw7RUGqal1uVF7ZYeeTHDHAjTYMvTtxkqT9U+Z52ojQpbaj/YUtth0lqNodmNoVkPk9bmOul4nTRDCuUJj+x+CKQQkzYDMWngwZOFS5JwAyL0aLvOdB6R09FMXYfLQhcmTMvDdFZcqil+y+l+/6wKc9iEVvlGK4eYQ08kqleh+C28b3UYbJocqGWJpCCZhYTwK0u0kBB+uRBlH0ItbXzgko5aOiYh6aiV+2i2LCDDlZznZSkSJbmsE6fomByXFQC7wjkJCV1q5j6rkFBVMEuSkJRluR0lkUtgWYCRefJiBrAsW81XFwyzrGAMNdjcyTIRI/pZooSEqrP530ZICoAfdSCprSDw4VFb5BLA2cNBn3qt+Re0OFPQaVZMhJMDDNa+JaxVQkxBR4J6lBC70CEFISF6oE27XEZJJwHayBkQccg+FaDUsGavWjvUG4L6XUC9vBwdbz4pV39aGbu/rqyLurkIjNZ//iIwDzHfX7FFGz5/xabDGu4rQ9HOn68M1e26qaJEGz9fRamGKg5YWuIWZd0PJmK3KP1UQkvcN6z7zkT8vmED5HGtE5RVcNDaXPvTLV6KLevR4lGRsUuDaqMmEcWedT+baA2iarFPhs0Fah64SGyt9GyLvA5S97xp5AUWl6xQWSpLqBJbKz3bIqs25U324B8Xn7Tkk8c/45N+Svc+Oeuv8Ek/rfc+Oeuv8Emv1nufnPVX+CRu141PzvorfBINVU5Zad34ZBFxn8QNREm688kieu6T0Am9DwatTdWbed13Pllk3Ce93pnkxieL7uc+CbME/4NFYktRqwzGfBL3vGmUPhkOrhL8D1RiS1GrqOQ+GdFieUPzn+6Vjrzy/FvFu31fPiio11RaZMIlbx49v2XG+8Z7Q1FMJsv+rWQ5jMnyNibL8zLEnB9zrVBdkmg1JtFuSKIxPRZJNObVMonWYxKNqfbraNerm3bMjd2Yb98UOJ9l0veRNJMu8zLFNj0tXO9T7OkcU+z1o9NTE3OZV1/Sqrie94E+pS8I9DURCHepu6ILreCiSN1lkSEOFlD+rWw+jNn8Ombz88UucC14g04pfQE61dTprmCwqfXJyXhSMDBjwWC0Sy0FqLGGoMdKg7mUFYRd9ukeUlP6AkjNHqOupR5Wk9gmKqT4GEVNQhphqDjWMsVdQfujAgSCwA3Sp/QVSG9myjCzDUQlIKxCQtWDLJm4hN2rdQQtTo5oWY51beWNbC2BoAyT4Tsdk/O/NyaR2ArLo8EAR2EwbBVFtcWxldUPoFWvCTBxTUdiIlZ00FFtQkKFimxBzyWitHCKPlSOqEe6S6iEwegVLIXRKxPEOL1QUQNH68PZmg5upk6JFyp6rQRasrrRXv2vnXo9IhynkFANQ6/JCAnVPXS/RQAJFAP2DS0n+vTqBuOLsLWdL1Zsw7NnZN0jbhPrxPlnhZzWi5c30r4JCSuJTFFIqIzCaCccLfb+WGezMAXkrbAptVnOcGte2KyejXQ4KuRpH52QsOJfUkzCr7wag6yz5BRY1GeMrNx4uejn1R4jazoRool2hau6zlV946p6espV74jphYiq8QLn5rUqznvv6arkptvITcPITdPITeOnuKkeual5h5siqZXc1A3ctDLYd7mpGVmnvbDN6338tty8VdaY7Hy5OXpBVxNcDfrndFVbRYTQbYegq3fc9MJF1XgjdPNGGae+AoeNe8FYv6I04RK8x3Fz2ZSN4J4Y4cll0xMjhJGeppGexo/pqXnxm4H0FcUT52b/ip6u9IqgPe0LempHeureoqdmpKd+pKfqYhf74o379BUVH5dMuL8y02anlyvstt9fmSHxlHbZRrvsy11uV8msudy5CWO8+ull+oraFEffy28AGfoaRzhrPDUtlXrj9UeZLrVfHYK1Ocai9ZtEYqxLbC43ZaYyLKe0/RYGRmIXaWEXEnb5lhqY19kRTc//VkLSL/mScULSX+BjNN24RsmNby3bytBR/lq0+mfRWFqcObuEG99UIvE2vrVsK0NH+ZvW6j3NTJzfa0Mv9pXROOE17Y1zlDDK3ZkSSBjl7kQPJUS59dp+WFklnfQjZ+iSfjuZUiOUJXAL9oxxElZk/F3tFEzTyX0+fYHp45eD/TYPJf1CMaVdSPolZDyFpBNrlg9gH6L2FYVBsk4XYt0OEvrV88IubDsj6qn9tBT0McqdT6OU9PeVUjqEpN9c9sQDJIyx0oVI7dMYa7m8wl8L2MJLbeelgXipuq+h3rz39pSUnh+9QvQWE00jE43/lyqp5Jj6rfrn9Cf1z/8BO8+lpA==###4620:XlxV32DM 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11f4eNq9m8uS5KgOhl9mHsDcoRz9Kh2BDUT05vRilhPz7oeLEZKxXVnVGbOpIv0nIGSMPgty/WX98rF8rL/txsv/X3YT+f9fImn7IVmKa7kk8aVQL6lxiS+sXtL4W3u9ZPClrV6y+FJa19+O+9qz46H+l1zVC5vyW7lS2lj+yVVUzFWiXP+Xa+sPnvtdy9X0oeUe1r9kbu/D8rD+MqK1aKRq/9WCrGXLWi4xPIBQL/Hj2wJL2QO/RdxT0f7duDGloqI2qcMmx3U3iQcBJsU8brM399rtcHPt7LdkuyCj/ndTypYha9pFOLpg+5Z6H8rvvQ+x9OHCMP06jdxNI2cGRg6XtvXsBGbPThCzEyI4wQwneDCQfdUJfOoi6eGEvfehWYI+xHnEXE4j5mwaMefTiLk6jdjq2RwLI7Yw4riANeprIzZuP892vnAY8QJ9yCShD9dnOxie1vNM4HGaCYLNfgmzX/bJL3meUb+4yS98EeAXN/yiwWb/Fb/8ffiF//Ojlkrf68/8/SwdvWeplkrl9WdeTrIkt7ggqXw/K6Eoe3LF5KLkZ7l0tP6oM7oX863uRXcUf9a/uUcnFDImO7XYoooiLMOKVEWRVTEcK3n8WRFF0YsnrbGi6DoyQ1pTvCimWhADUURRbHGU1wkNLLv4GNdRysM6Sq6VfpY/pS8LXrTdi9bF4quwCNyk3XqTrVSabCXXSj+t3av3Q0JNVu/nQFPNd/YwvzzhzXxTbmb+LJBy3GepWnOxN1c6r83x6kHhOGmu3A8VmhKJUnyri5+4DbROac2wZsJQTDPORNcUg5RmnAm+3SqBjGvuM6nOT7vspD1e2qs2GEaVpSi62c2IwopiWkccOmK9o2CbgwKSqoNMcK05bHidliaqOl1Mn3wlzrbBKlGVLSDlGCyrNvhkSKVit1pqJcGIUuxWrCmCKMU4Vf3j+IaV8mSUP2WsKWGlml3mQl5ybDPBfNj855+y0qQPZ21bHuOHyKv5sdJsy/o7292i+hMTsDgxAQtpYoLcWrDtc3DH56PVsOPWapyNCl+qS2nEiBRr6I0YkfLcKJeOPqLDks4Lb55WbbnkzRx7DMZKAlolnFm8krOk6qUGWPkxwFIZujV46DHVS6QBseJVe2/d10ds/TJDdmA8jKfguAE4TrS4P9Ki2eM9LbKdyYv4+TktLvEVWiQxsa0vd4gY34GI3vN5rAHIeAE6kkERRCSs0HiQUuM2U6OZqdHe8jLT68kZ8gEV4ztQ0aRtcsZAxS0COCkTCSpScJIzOGlwxkRLfKYl9ilF2vq031FkfAtF1mfxniL3K2e8QpEHMl46Y7+dDoUqiQeSeeDF+AZexCCWV4QROgiIFWWEG8SE5eE96K9M3V7MN64Xkzkx4YjyxfmYyNrN6ApBV5uO0NcavEbXIiF0zUMzpKdBn4NpmjJIUmtHFCBJBGlleBjShA64DiJWYYgFg3IRKhZbGhYWDx6l0kMrJYNRUXkVcb1KqLVeK5V6rZQModb2LHXrMbVyy8H87GXMmKZ7vZYwY2bfSlJpkKQF5mnKIEltLVGAJLMHHVaqB6VpHiT9VA9WGjoW9co8nlPGbKtoHWyZlIgxERtXrw02Vl4G1B4iyexzTxTg0sxqkShAwNxvEisDJPMMo60NlrVBgG38jljrbUfE6qTBzdWnNOyEtNvzi0EyRqIMlm1U0BXCsk5oUglYNr+XbUTpLJsXMNZ4WhT6FIM+HdCnuKdPipaS8KFYJyZlM5PGc9Tp5IqBK5Q19yDVO0L1QKgdSzuLdgDF4HmwaAFQ9gSeagZPDuBJ6fIzBk3sSwz6LfY8JStvMPSU+LzNXw4S1Uw8kagDAhTxgkQpZlI6WyY6W9LMp/vEJgfFksTmRiMzqy65oVbt4xuoVbOL3Ok2/KLALw7e4TKJnKlVrWdY7x6oA4o9g1jvgrxJo7odaMtwTxi5NXXOiur1CvaV5vIBPqMaWbtdPsCnnuFTTveaX2TtLjhUfMqhbHvIZmqf3sChWvAHDg1ivKG47bscekpd3iDpKQ36lM1k2wOd6m15QzazPQMltJRVAkcqxTVRILopZXaijNSKgvRXU0Y6JnmFlUHBeWmTWEEU7OuaKooiDgD5UX3SqKKBK+sJpaoQcG0ULaukOi+XuQbFEzpn+zuilB4xOiuniQJAmz8zogAE55FZrAxs1QsTWBnYqpRdSGsDj7113Rv5GQdv9HRmy0zGCpR9yI1U63eOEmVWBvnq6pU50woNVVSuDR0lAs15PJ2Rim0YIpVTWBkYmz9zogDG5vkViYISos4TBUg6+1pjZQBunlVjTrLit1hYtVGxDd2lWSom/KjLNGLTDIZ9eip4DBqbKriJpYT5+Ii44pjTcK/UAZaN91h3TZueiEaV2hdkM2LO/JkoKH86kvdtMIC9+9YmaCXnPgzR6NGU6VLWjfxn0KMHepSX9EggMLIZAsUMgfEKAj/NSer1lgPNOuUky7bgDQour6BgIzqKguwpHXnFf+ZbHNgJ7zMODFM68pL4jJpZA4gvGogcZmzZVuKj4JbmzdhlBrf9FLTqGnoHbpt8B7jVF6+7HekgR4YtiYcd6Yvcol5vgct8tg2ttJ1ziwm8HvbBMWnsEfOJJy84O82MMZ8aYMfRAADOOi3kDQq6wGASSEW3rNmMbzeZxdOdjw8Yt6l3YJxWT+lELwbeLl/blN5fwrj4nGpndW/4FtjEG9KJrMNXfdBIDsPXvcwadfLz36NO/haKOji45i8h4Muvy54oA/g0JDqaAsB3BJBmzU7py9fwVq3RyJod01ueowAOWmHgwvBWxnkQm4ujuFN4w8hSxtxAJVfopR0jSx6txT1jOFs4VhCcaS2JtYB6GHy1IniIYFkrCnQOgM7KBiaHwdVBrt0u3m9KKZFdaMR6ZbyN8Er1o7RT1jMB7lQkrHeQfjfkwKDcG2YybYCvLCU8DfvkVUHkhSjGUvZTXKJRYcJLCQjcCMo3kC2vyuAbzJiGwFt2fiIKgrdBkkaQrXUNCdGiYKzbt2ZBZc5u+gFSFduZz0GJ+QFSG4CUIiBF+GeCHv+0EXuRB8P7vH1P9vW92IYz13uxCuBnSn4tX09+hRl64kuH99Kc/Nrn5Nd2nfxy8un0WoAtHrVdsMIECP5p8/EiOYP3NmmkSPf7kHrTb9iH1BebsiP+BzZSQfaL+5APW2/6fuuNnzxQN6NuacG8gxa2x6QPV1cemGkhzh5IrxxhE8uMTmFOhp352bMnhrDvSPpUrS7420iseEYTKz0TUZW7xEqexj0g5/sJRTYlViDOb6f0ycaIgmKqpQpEztxaIsqgBhwTU4+E2bBeYqeYmGCIy23+ozTUEKI0dJQYhQltsUEYJuyOFZzpGVHL81P+IxEF5z92ooydxPawi0OBW7rg7JBK0eDqOIh7RhpGoXoESidpCB0k6SQOoZlsIHHnRqqq+LHtq/nm/AhAksgeYnYncc1AiqwsuE+EBylxYs3AA+0EUToe5AUi1KwwM/ktiaGzWzuEbf15/iOEp00wHOzxttYpjXF7xOr1I1XspZ0tNe9sLZc7W/9F5iLfABaeEhUMorMOy0OiYnvaYSLv6MHM76jjpJJKkBnR22kX5ircoePqnxw8ylNtedqYGdHYWP61aCxe2pjR3zhmfjwfdwE0sm2c3mH/+ev234d55ckOgtPzLEJYJOFMfrsRQxlhJTBNlBGkAryFldp4rQ4sEWWs1W1qD2Ws1QF2DIpCT31sxAR80sUnrODz3LC1EugGBBeyv8qUaY9PTwi5E2Ws6sYHooyXqQDrfSmRfLdxHI8VvQMGTvyDQk7gpM4IOdJDMCo+xPtLgW1EgRRFrpOIMvaxAotIwScu8jg8GWuPGWXmq5oZz9Er/xmRIUBkMJeRgR6imLYGe7C4SDBeJs3T+pUzvXp95VXSzK+SFh2puFz2+1vZN5b99NLBhfygb8eM0DfBIGhIHWu/kWBAlpZlZvMjPlymdS8S2uG0CPLl/nBrNouDWZp97XCrXl95v7z4SZS9CW5qu1+uuQrjyPHTYcv2JvON5frqfWfe5C7RAC3ieaXuUFrMR8uX9DYQBa3HcCysKWgNh8P9TUHrvtqQQoJFpn1cCZ0i9IDvZRaQdXIs/HyhSScg5qYgEoU8alNG0ilwhhRy1k5EbDcKCUoH8ALnZLddb5woaIc+KaKgJK+nddAKyrFCVlBjiBfGRmV+8ZFYQaTenifoCP+WQtbc25aBcBtrboQ119Ik2um3D/THCJ/+OuD25D6XztzvYO3O/fkOVu7C3qd/dmf/PP2Tu3D3+ZXdvSG/krvw96kKdK7sD7Y7JPzIqLiM/JpJ6Ygk/Css2X+tVm8l3iPJlXYkoXOe6Mx1rdQyGbXTXnSj6E9nrhUy05Mz0rKnk1stlEbJlRaQHD7wjA4vVytrzqEO8ig5KHmch8idCdQiSfLHusxCkzUfUps8Sg5KHuVIamq7TFW257jC9vFUJngq3eckdGDPMp8dvfmJ0wMUFaq6OElwc2zgZey5fs9mLx0bWNYvZM6P4wOfZc71TF+XP0K6znqbeqzrDqXiWGDUph5Qat4hPw5z3vz+6Imq0jnNOa+A/wfsM3K5###4700:XlxV32DM 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1244eNqtW8uS3aoO/ZnzAbzBvSu/kirb4KozuRmcYSr/fsXDQgLb2Z30IN3EywYkY2lpQSf7+p8+nPtwW3r9ow97fDgV9esfY+TxEVR6/Rv8/iE+4HfY6u9N5d8/jNx1uWCUXXPj12a9OKBl4Z/4mXtLH0am2IaQ8VjPMYx25xhavP71Fp74AMyFD6Oke+VLkl7y5ZKil0K5VObwQ6f9wDnkvjybw+HOOezJ4RyCxDlo6EqvpHelc+/G0kvmNc5UqWmmyuFMz+khJF90pkqufvLWEfCFRHwhSeBE7SdfiMrTNXQIJdTpjLTgS3f7gWMso01a3tu0jzYto01KaLTp6Db1BbB+xqb/4MUHaKmf38pg+Y7X90WtAJl1zd3on9+K4Xlar3oX9Pf6nn/8+s/aJdXny01gTkZCRrw8GCIz4gBxIhiGlN58HnI/ssGmzCY7xK5lSN+bS21+Lz/z+EGcfYmzLy/rzCJD8sx8mXNd1LohaJhvhhmbp5KOjUwFXHre01pLaX3PP4obHbrRNzcGWBDQURSadhS2s6PWWkrrewh79Vq356hz++5jNlUe/qAGwZuGufrqUE8RMOB7sMVUd7BnrMhIrO6xDMmvx4WKbGQKxXE+LXVFLKfjpOyOC9VxXvrqCo+uCM0VPuaelQ6R9Sxyz66+ksQQmRFfkcCQPFAKxR/91cNsitW+vDvwh6VIGQd+ZNt8Ykgex7blsjIkj2PbcjkYku2BH7/gA7U+v/b83X0o/TN/l8fHEhbxql+rhg+pfZebGIIiBHAMikMklEliJBwCtYyRBGpwa70l7vTpEsuTpZfWcsnRSyUJJF87SIFCJeqmpY5x1EgFS43ccli4JbCZHbJcivRSjuiwquglkS/5ahp8j3TY40VjV/n9I5T4kmMYDZSijLUZ2nEql2y7m5p67AXyDWLT2SDiQrxjYXEzu9RT2kumBV7lbU97AiOvimPaE/HuDStx3L1hJbbLVKzsJmY6cDKO9TB/zzjAbDObHbvZ/sJsPS7sxiVYtpfrlO0bCbnyQKMsFx6QswcSesB2D+BnB8n2kx6w93wHPBCuPDDzHTfzHT3zHTPzHfU237HFihu+sx7u7/kOOMONzuh8B5yxXDljGZ1R+Q53xoHOmDwQ32ZHtoSEG3a0Hv7v2VHjIxZyWf76GgnJyxCbqjc1pyYtOaifDaPUqnoWoNJqiTTf1VhVNDvBKauKTjMEuZON0jIE+ZaMO0cyCdhsQUykSCEOm8lICpIihWxsuvOZ0yeVxWSXnC2FLU2ZDbjDoDsUo0jWakm7LAyrdNlaCluasq72tdZJ2u5G1d24EZxSwOgUQzptjNIwBHkRuJEjyKXkME7nX+BGQZHO2cAdCt0hT5p0qGpWH8h0s2Q3ayE4IWhglmQIkiUwSzMECRaYxREkZXIYpxCsVNZNOqloRbJZwEGqWQLNEoz9taRaH9LdLNHNCgTvPCubJRjSuVmUiiHI58AsjiAHBLM8RTpvBLMSRYpZ8CMzPVmihdwhHMq9Mz2JTG8jTO8HUOEawDjjS2MkPOkcI39iTAsnH2RkSb+G+FgI5UkJ4ffamB0jfQuSvoEHNiJZSB/lgT9C4y8DjbNI4wb6pmayd8nofrS4O9K4baJxJ3cb6Fy1c+Ju1mtxz93kvm09a5kH7rZPWasRM0bj0pTCG7NjfEaM76pQQ17pr/fkzu3iK+QklR7kpH0jcpJ/kJOWJzlpNDMzOSYnmUlBIXJSWpHC+XVh9OpOFaLsaKQLanTx9iAQ7fIrBKLiKncnEK1ImOxmGGHi7Gif2NFkbrxmyLJINneC0a6+gBJRXWRFNWTD1s4y9Fp6KoqBJVLLTjWkFlurYrAPRIkIQmtXgbbe3AfWJcOKnW33SsyK+suGrZ3yFVgbKCJYQbmRE114sILyKVjfB0OQg1nrOdJ5GxEeLFfQiFhhBgXLoIJliFs3qmCBAZo93jmO1wdDiPazo2kQLii18MozpFMLrw6CUMnKrOtxzlOTea6DYLTgG1tvBaMyKBGMFEeQz8DbQbO1oOkdPK0owmShnSFEFlKOIUQWUokhSFfA8WwcTiP2KhhBPDg6jVBII/Y/ohFJ/yGNqCIUpxHxRekDG2Z/kpEGsSnMvGMZVKpTXOokw86CEFeU7Kwo6YmKNN4xq1MjFUEK8r64hJfK5LjOtL0mrhJfk+S0X0lOwHHXB8nJwhs+07NPn6ItjX18nraIONOWbcjn7hgTHuEUaZM94QXGKfgMtyd1aNCQ1ExG9CA+8YyY7jUjt5u/14zACXFyAiE1sr85yUkNz/pyFojmrTtlZ+qjZuqjh9dk072QI/cDeYFZtj8VcvAuMU96nyed5klPlDg+cRn991zGRn2mivz1sYpTJ4Zg2G+7Yh3BVKG0CgzB9KKgnKRIT0kkwRUEU8XJfHTJiqnTncjpDuQaTMvgIaLTOEEYR6L8Bf4fKUL4i11Yb5S/nHpQQyh/YeN0/gLkzyL5Sz37x4H87Zj9IyN/dG8PPjHGf1wiSKUcbN/u9NvJSiNjpZUI4j2N/kW2EUf2x8rgyJ7ArHCa5Y5uVmqkJjYaGtGsxOQdeOd08nS3zrudjdl367zjs+mMreaNcwU19lWIFayNPtBB9RtYGwwhvMoOSN+IIzzVHZwAusiQkzT+ylktQ1mcgx+d72jkO/HP+I54PeyZDeLKDd8hJIdvn63z9pn71PZZINtnyGz49pmct8/sF2yfZYeHRxohO404Pqd+pNfDJtagkdzQCJaUolseNptsUheE52KzaZ0Jj/vUZlO4m1582Amy5OQLmd5bJ1/cl+4E5VzlMALEQeWOBKFhElKSoQ/1IARpbGPdYRBqxXxHSBAygiFETtd9nIVr1ViEVoRo1W4hCC0olV4SHYjo6WYXtLse7MAgzwbCYNfOM3SEnjrovQWW5c12MKRnea0cRViWlxTpWR6Qlc6gC+ntQz6foXGd0ZZwS1sCoS2/NhnLepHhI3zIrUdig5E4saMK14cP5moxh91+DoHXgfvr4WQBDbf9kMGXVXaTyKznqux3Fd42VnhnaXijRtPSECu8pQgVrNJbwiSC9hDtBAqxTq8sRF8fF7io0g7GpCGBpntxeTNfIS7HZZltit2m7cImLaYSb84e5CwADfncvOO+xNuM/IISL5YjUTe6NZgXr8zTX1K8wUcn73Xrzegv0K1XoR7qw7ThqQd9iPv6UKV36sNWDN6ciLwQuGlhyf0i7uvDzXyF1r2umD8XGk4hC2BpUpEuGNYvoSIteX0rS7TWOxCHW4guF2lhYKP35FGSK2E4yRBMVJCTBUNIFvWOTZFkiSUQBKeY+hQjTjExQbZlkQIdYpDqFYVKLQSxj52iqP2VUrZa35qH7E0xHPBcxWl6XqW0JA3WMKSXpOE8F9CQLqnXlX4ijREVq/u5huqKXBTW91Zbh8SWYPsEMbJp9ApcRrdRhFbgkSG9AgcvGjqLXL7WWdTWIbElaEkLsxDofcm2PWDxIF2AMEZoGywejhDa5gNDCKfE06G5dS6eox1O+LU54DRwA7zcDyJwW6QZx2XBxw7JvVHHJcHqOP+U7Pc52R9vJPuTJfiZJbStZ1lKPLDYXSR0DJ/BYXbQDsMnhMELq1liX2q8SzXewShmTnOmj4K0wUsuEF+es7oq1NJlJQQvdJ2PvQsc2GKC1dJipA1TdphPBapZ91V+MLosJnuTmYJF7uKOxI/c/ybnNAFSzclqsP+/NgdY8aVFY0ZzTYWK+JIg6MlyVtqYlTxFohPENckQjGgKD9OX7uihK3OeWakI2Yysy6IgzrA6wQFTqkJVWaF5CvUmksja2lXtnmoBfE8Fsp5ApJ4xe8mLvWOBHWM1BE9LMi+SIc2ezPm0Xs+ndaBhcG+BqWSsswddgGptiefnY+UsdpsUFDgefvTI487Io8Vl5GEiUos0v9s0SxfB52bHLMzK0TrvmLm5UvLsDLbkYhKviSTWRLcx8JhjYJxjYHo9HJ0eIuUYA20RRW9jYA8SfmMxkCtK846HWIeIUPxu7sKgxWDrlZ+rp6ftrv0m/NmLU8dbH3BHy3YMfxBKRlFqPv8r7bzHNTNhqQb7ZXjYcssU97Rfbw9bbmGezjpPZz5o05S02UsyTu+/b4IF3V/LJniFpOZT0he9P6Ygvb+XgrY5BS1zChoXnFyeUpDe3ktBs1aq4pyCLtcghH+NoVguNJnA/3dEhgy0n6VBeYhxXaM38hRJJ/2UbhuJJCcf6DNkp0lJTFty2I3ZzwqqQIRH0iwgMQvIhZPhdTvvsfUvfL6V9U/UPbBS0ntaP4HqfPB/y+6ReE8/NqKkZvcovAdLKkDUaY2VZ7I8ZH28eycwzbIt3u4DZNnnR1P6C+e8LDvHSvOo1Tx1WxzSTqlbk4c4KehZ3TL9ct8sy7lWY851DYBi9HRKBTxLxnI5k3HzZjYXfvRk7DEZyzf2fY539n2+JGW7ORn/dmdnSsp8h0fhDs+0raPnbR35dJz2MzLm8ZVZ3dStBXeX1Xc8r6ltYlmd7ybN1F/Mcfcm949ZmhcIMEP1cNo39COPXixv/aXW037X9vobHrG6mbh0HrF0kS1sjEfwLC3vd7L0kLgW93DgN6sXc8H4+Pfjb26dOWXWhz8aD/3PyKx7+iMqc/vXc2pmTo053JwJHsiEfSQTy3tkYhmXzP8BlaJsiA==###4628:XlxV32DM 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11fceNrNm0my5CgShi9TB2AUEGF1lTQDhMxq07WoZVndvRkddyEpIzNftfUiX5ByBsfF8PEHIUR4v/8wmr3Y6zd5bPalhPDv958yxZSfvf8Jm+Ayp3T+x/7OeXTKeZh4/ydn317cSvsuT4/Xth3p/ZtS/HhZ6ZZaj9oQx4/2+kjgR7E+Kg1WH47qw1/Zhz2n5N+/q11uLyP9u6RETX0rf2oek/OIv3/PKf0qHXh/c9w1kwKTLKbj/c0GkU0qpq3VXEtln98tU0nlPDrnEdoIVDx3oli2UlpJTSyiWEwr45E31U8bZHVGgSWnujNKt+oSLpQf5kKq9WBDhZpFi9YQw5bqtt6bhZSpbm+2tSOJpbhteLM4YpHFIqoHHmrLqRZec/BqcmByW++R2ftLsSO8uVTxoWWq3phkWh5P8jDIw0qeGujod5JHQB5R8tiWJ+BBUtpqg6S2pWv/YuAkj4A8pZ4a0Wqp3amp3tPdNJMAkxg95aYNJIUjV1+46v2TpE0GbZb+5T81j8Z58vvtecqbNnV0xGBrA9/KWxk1yGpw3ZAchKUZ2kjLg8jCsM6Gf4Lysk4W8Yovof8uc/l4OevaXE4vKcWYyoHlGSn9nKR8r1NZFYdPs5wnDrP8NLX5vqOpncPZP23/9K1I0rg2X4rUCQqPTH1kem6LTbaaXKvwEPXTdjct8eWQ7/Job6bNtk/DcW2lk7ZO/PxpY6vNpfYZ+vMgca2lh3m+dhPuSV4ZyyPck6M2EAx+FOqjFpK8dLVP0ULjRHNXCV0fBJ1qfQovzDyNhVlsOVR9YZbbMd5mXmDp2xTMLjsA88vCzDayKejkSx2Gtq2g7T3AppA0tL0vbe93I0mw424kCRauNokypvkaD9192pMcLoldgkupvNzQ31gbMopHSSJdu+vWqsPsrodQMwd1H6Nvw3Gul1BzMbtJ46vPmy5P+2zQzE0XGpRsadCvDZrl3XJ7F0+1djpBPMWMpwcX+KfxtEvVBxo+7iKeeUk6dU8w6N5NEM0SxGObrdirIMqlFU1aIbjC7yK3DpfDQuQ4RC4xaFd/FrnDLC9FMDZozKkEkeMw6TOinSaecLcT74R/uUH+gH9OxdGgYeqH8E+yD/Fv7FanTssRz7wfQTw3cMF/Es+/ejzztl1TmBp7z5uJE2rs07NwQHGtPPyW1+eKAbZb6hiv9f1ex0MrKb11qFLEkpIp1RCgelIxoecBEpV+25C3CBBzvRZbJm/mMoa0CIyafVXgq6Ek6mWADrpXCVw2uVQZiJVSupr4K8e4dlBBykHK1NS3vHu2Ki2KWasyb27FZOteV7pe9rSK93WHIXgfN9RseYO9XUi6mTQt+a3+rQ2E0UB+KxWvap8RSOdSEeep8a95JlIrzwyKGAZnP8C5jg2MpR5wsnpb+53xpA2jWcjNwaJeMMw2VCkG6/zupqmfIvoLCb03Alrlo9XdtmB46KiDYPTzRiawVtzgPD0YmjC5lxp5j4g+WzyaBPjk0fYUeNOFv9ubRvwd3Zh3JQ/hb882UpxBcUDpjgEjMhj+vdyxBaN1QGjdyzWCjgitewSaYe9obQSMk2ZIiLn7lGvM3c4neSSa/GcytwPmloi5/zTcPAM2gHV6f8jag7G3/mlWsCZAvRGg5hSoFSFX/T4zdgPoytiQq6z4DbfhEX+fyfsQQN6Y1++g+wDoPsG2Xsma8Hdc+Xtf+Tuonad7zOZlkR07rjEEs6+YGm+AzHwPszdRT3D6GrO59YCBRjCC2XcsDY/i+1Os3utyccO+vIzVi/4fZzA7AS/hT37u9HbPvrnT6qLTlX2vG7wA3u2mp3I91AAvchuBSo0RhBcpW23vBSH5qrKJVQ+TKxAp8BTjKHI6n+rFAxBaOU+BXD8AYVidXg8PwpylQf4oDW6fSYPxI2kw3UiDdaWoykmeqF09CnRLQKoWPyFQmNKeIPiXl+uIClHR0O+kTQ5tIqXJB5CKqMbWNKhpAY2tD8BhwUCGZT4uMN9hMY8LzIRdkpLD0rVNQpR9stXSgWp3feJXb7g/KX4cpDbuhxwXiBzXJa3ZTYCAbInYMqWyHBqGLZPOuog2awMmm/JhfxkCXgaS9HiCriSCFH2JbQHwRNLbxBZJLxn0EguTieThkAdwCAuxnDB/DAfiju51pYjIiKQXQNKLnEp6Ey9U5Z48xeJLyIkXHvBCXeKF0iteEOJgK3EcK3EkQhxXqt4i5bn3AiHb+1dUPfGDxIEEPhO/I/SplSb0ShPbShNmJRNLhD0s6KVHQe+YS7knpEHWbbau28ytu705CXpB35NGbhst5ccDaaSVNNalnN0c89V2QTtDwEuHuhPw4OV9IDxF8STkHfIqxMedVsLVyhbyHFfzJOQlexHXCTNQq1vi2iHmEyFPbWH1IUFczZ2Q90NxZU+C3sEv4roKevxY9co5fE5xtU/aXnJXcZU/RmHXwdRxbdhCMPWdtvdDweT3SJeDKa6CaRd+Myu/2RWr/Hm8unuky3H1V3FdkW5f45rWto+b8VrXcH0t96Vju5P7Pg4xVpPKotN1ozJPRjK/ZUjuJzUpujh0hMiHbFOyDTx0oKsFR8lRDXGiVYtFsKmrFZeahlY86qns0EjtRFdz1iNvMP95fgy1JPKhlgSH+U85p5Gv+LttrzgpLaA0wmcnobSlCmJ0HnfHxNGdlird6am9pr6VP9XpBM0ycNoSGc6hAJ/0JcVIaQGlEX+7AAFj8/XFKZ3NsAmow9Dvmh1ISVFAHaV7YwgI8NBQrFZ66KB1vCE9ML9KhzzD4qQSB4ybSPXY6Bg0pel30kpv0JSnIqBDQRBE+nPonRoq6yH1LcGr0eSo5UCHbhasviVSWkBpLP1BAEKaYfUjrM55ZEcKXh42O3lpDF4asHqMgqh8AcS8KInKF0DMi4qofHUgNYPGKl+bFgPD3RWGB8Bw/W9i+P7FGP4pe3+F2vd/g+F1ONxi+OTQr8Dw8/fqIT5i+P6VGB7utt/0hOH2SzBcPWK4/lkMPwXTP7J3+AL2vong8QTc7kuA+/Eb9NnGM3DHJ+DGWE7jGh7ZO34Be18ooKczDXvC8PglGK4fMXz7VzF8f8Tw9L/A8I0/Ybj/Wgyv1XfgPiaRs5nkZwz3AD5RT1jgk8EmiuxnDHcARvwWw7NLA7kPAHIGKX7C8IS8ucNwDWiynzDcIV8phjtSWkBpjOHwZXCemncYXrrTkfsAIGeQ4rcYDt+G58ophlvULMVwQ0oLKI0w3ANnRjtfHwMMVxrqUFCHP2H4AXWoifLHHALzdONPGD6+vW7jjWL4jjwjGC4NjBt2xnC4GpD3cIrhQ6Fvo5xguI2oAxTDDXL9BsOjhFcTKYajEREphitJSgsojTF8jmU5w5oAw21A9jsMV+Cbpxi+UQyPANWGYvhUwy3F8AAGRzF8nxhuSmX5fPVCX7XHAeE8EAjfO+ruBHX/sEI+Yekfti5AD1c0lXJPiua8JfnzKJWbeBL39vjrrJGbeJK89vTre21u4knyub/h9flek0cETHh3One3E/8w1etc+d23QgospxO0H5f1q6kWygPotKu5KS65KS65KS65s7jUZJdW7U6ulrUhPSxk02qyRzPF3gHPTtuZA1XJgarkQFVyVFVSZkM14pUuTzOJq2zbhwNlx4Gy47Cyk6FGx/KSy48z8p85K3c4Gns6K/uxdY/rPZXvXRPf1kNtfPpuCZ+G7+648Pcn3zjp9dQr11MvW+64lBP03R2XtN5x2c9nX8H4evYNcPYdB158Ug7aHNt6jRuuWoR5Z1odipyQyOWBdsXiuzePt/UcFZ6+w8AHMMSlWu/s4ZpGNObK6fWahlxvPKgV1Ven+31gsR5l5OnKB3G6jn1zc1UiGn3ltFucPlan0+K05KvTcTmx4kMCulAhPB/354rP7XpCKCte/n9CFgzUQjpsQvQr3MZIdfNnVZukDQHzCgMCe7MA6fYwVsvO8N2JPiqGhdydkIBStbp5d0J4NqorM6FWV+AjV9dmxrBgcszVcezDvL4gJEjx1TLBMTcciN8A0dkSiQUgOlsOYgF0zvHZiNsAxEKOn6o1S70/u8fmG8eWSZrCaU9qA1ITm6DhGQz6TxBtXIoypAWba3mCtTxcypz0h0Tp/YHyue+3vylK8jzvqij6PaC7W+DFusDzdYGX6wLP3s8/H/oOP/7Szcb4tOpf32y8/UWRrjx986uevEjxi0Xq4lc9cVmk2PrFblcfr37gw9mynDKySOXhx+M9WNt5W+HnwTo3ke7B2qav+NZcW/e0k0WIt879v9/J1LopyHUn0+umsN7FvPlFizBivz8C2HmL4RfkNl1/jXC7QwaQvvNyeL9Dtl+V0GCsg+9KGIsfXjkca9/NYcXOqwc/f1jBe0yek+h3ECqkvs9VN8hPTw7XuLzOjnbAqKN4JMUOSenpsSNHfygl5T2Qvd2MW4mtGDp35LwClUKsILbNEcvc3H2gZeZvpiXoSdWC9mkJ30lWC8KLsGlS25TUdiZROOopp0ajp8Q+UtKTk0/Yj9FdseOzlPZqwzWWQ06rsaXEPlLSYy2tT55RIzlLaTvD5Ai15AcGmdD232fKtCAIspZYACYwoFk30OS/K5yfSw==###4684:XlxV32DM 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1278eNrNW8mO5DgO/Zn5AC22lgz0j8yhAFkL0JepQx0b9e9DbRRl2c7Izh5gLpWueCGJpGQ9ik/xp472g338SyZlPjYe9ev1p4FH9gF/NadQypAW5KPE8kfG52//NDbWv4eorY+t/d3bX9X+6va3jPLTclv+v4nd5YdjDyHAQ/42+wuG2mMefXv9B0ZVH0JJ/cqfpg+1u/j61wZ2fBgRXn/qbR/GCXaAcXpn9CNfPuL0o1A+qibrXRaTZPQpP/zOthzwpGdbwrBFdVs2b7stkkFX0pFRuHmdzeOreVwt5nGH5uFH9tUtxY9g1ojRPLj8tE1GJ9WN1unoRivp0WjZxz4PKPgyoBDnAeM6oMEBw9YHFJHhgHteO0dbC2UCfm7cy2kx/D4UzNq5b8FY65sbyXvfUuBqkKaHu8cYnctmR+xar10L7Fr43jX0hV3bc5wu1s0vses8qvjrj7Kac/sf+Z/fv9qggJSn3OT1A/wHaPPJVqgENMfg9aP8+/sX9+WlrM187RDesIwIryiys4zsBQk5iBIR/qqD5if4jqqtD2IOeJQRXQ31pN8cttcPeFkBAp88enc0H3QodgYV0IfURlImN4qcTUgeSfPit1QTIjMiSm9lJXekDFSDUyMGo0UaMVg+0NTG3GlgkkCw0gAxvljPdmJ9MVFHXZE4ISIjxfiwyQmRGcmx2Jx1E8IyomqUAlkDLUo8DyQ2PXUnXY5fNk4IZilSFk7MsynYluiSKgPBPzkKaUayQzsvJjgxIdmhXVTjjgnJDsE/v3/5UKcJloHB9QJAfs2LBVx8mA+u/sqvSfqw5nCv+vLIXfe35GA3uwmP8rybgPmwm+hQSQdmov01tFXZuWeqMrlVamTzNmXJlbJO1IRfzWNWlsKPsqVWuJmweCjb2HZDWDpe7beFsC73W86W/Taz1LTfGrcOuOOAfuy3QeKA8a39FvoOa99hOOOvyIPdOnOsbGXOzvh1wDic2YczDgfk7zrzyITg13eZcD8788iEXv19JuTB8nu6AmfilTP21pmwOAPTODtj2TqgHM7o4YzCAd07zsD+E3F7NoFutbDLHBOC2zMgDhHXdnvYNwpkRqMDiQK+1al1UIw56HYHhrAJwS0ShrMTgtsqDzu2gRBVQ2BbGBy+dxsze/9Rljg+RnzMbSeSDxvSHcw1oWmw0k4I0jR4NiOZAY8ak7JeOtJjAoO2mFSG7KZmhqyW9qfYn3KTwZ9gJZKumUkXzBxhPnO8mRDC8SYRBKcujqnT03pA6m1bVUewpcfsYPOI+75eUoPCZE5PU2DVe17s2T/8hzCD5Q5kOUNY7icQen25aMJfKG1O+HkI54SfR3ZO+Hnk54Sfh/gaKWajSfhbSUiXTCxzY8t2ywRgb+WsECmrxXKimMnVILkio/40LX0228SJ2TwzmQfxzB+F5VyozErFvLF0Y21djb8/QtI0IYVXP1VSPm4HzBNrXxL68VqOncjmVoTTMTSKC5LF7VZpiQcPjrsfHBlORz+2Hv2YWk+m9kVPJjB22UXujsDw4vStHkIwZRRTr3E976blQNlOxeejL/cbW23oScahj7scAyf1U0YDNy8Sp2O4uV2FOPUQn894mGBs52Cq1ZFxhlfpIpg1o2Hrufuz07m5CyZfbYgYTH+X43wpmGvilsiaURfBlGIpVcS1VJHWUkU4h9gv7o08S+n9KsTy3GsuK5xCLPhjfQbiKteBDcY13qVbX4hrUOm+ACF22D0v4mrOcRV2iatYS0DCzHGtCcF+U6HwO7+Kq116Da/bLPD25RfrwBLjGu4yv7fj+qvFtZxAVTrVF8ZRd0tTjaSzMxB3NnFOvfZAoPx9QMKclOVNraVf+ZXERzkexZyUQbe92JG3q2Jnbdzzk10hruZiiOcRLeJzApLMjq1CrQAA1ZbSkWGkP5oZez4cZHP+m4wgRtKCwm4cRUZBAdIPXstDFdnZqw+JNQye9DEZg8k49GsQcbTC1coRsiOtXzuVLBJx0tLcGvpVE4L5OAT6ICPiRLAxEY60pPUWSL4EWWs12oesFSRNEVJXizo2NwpS3MjLkVbYQlBkodK6GlndW5oS9pF2F9tLil2WU3uS+CRo2g15sKftgDNau/Yk8UmUpx/5n7xqBMNVI6d0HWId6SIsztezT2QC5zDgHPby4h7qHEps7WmpD/r1E0KOAXsiI+IcyjGHkbRsb35dVslwuuDKEpeuVKwqUE50fdnUUpZoACTCfQVXQLYaF2RS3cgKbKT41aauFL/2kHIYOZzp4J9xLPB4LLCXx4JPzwDybm9uh4ipVJaPB5/k/ucS2kjtMaWfC3IJ8/dz0l7z+Dlpv0vO0zk5F4yvyXnE5PyUr+s10Ten1B2mIKYnYWiTf1cY4uyWINlaJsk59KQRxfCkEW3iUSO6VSoeZalySlN3+da2X0Si5FtzAsJf51FPqdiDAezsM6lFqW278tmekyLJlqRI8jUpSmtaGJbMW8S1OOdfkyizaSzIg/mEBSASgiKDBXarOEXG3t9WY0FimuhmD0xPjUgdh6UJQVqAvWafEKzjwP+pCTQbgpFRsIhhyj1gDx4uCbq3C7YbipAdvWYEAxniTXByQnBHbythIFjYaYu0I3Qvh5nwxO5J/+CcIiNd2ZxTFKFCyxB0YrgTdGK4E3TiVFUi+VeeV5LYQOA0Ra4VmJjuFJiYZgUmhgnpJclceC2LbhFaAnKN+58JLfr/Wmix4UloSfIfF1qsfxRa/HeEFpuehJa0fU1o0Z8LLTY+Ci3hO0KL449XDvZ/XGhx7FFoid8RWspmdyu0JPWPCy1lk7gXWtJ3hJaEyohNs9CC5+WKEKFlx8K59SehxY5Go+Zu/YXQYsMstCQzIURo2Y8JIUKLEijii1uhxQ51xQ51xbHxKM5Ci0JpBOaaEjRSYEMuhZaCEKHFSYLgLQVxIbRYlFcsyiuO4ZOYhRY1bkywk9CSxsUHfie0OH66TMEJgmayC6HFpllosYkgOOnjGsaO1th4Elr2NJlDhJagjiuWi8hyx+csd3FGyoesG5ZbqE19hdre5rNAdYaVxNz+SGL6SyR2dT45zrvL9kRigX2HxJx+JDHzFoktzKXOHqgn5gr8W8xlH5nL/l3mOnlgHm/IiW/RVXikK/c1uop3HvgnjgryGxwVGe48Ts8cpfYJIRylNkS2E0e50WgfG912wVGAU46KbJsQwlFKTgjlKCRL5285KtvY2UiNRzMe/cJRyIounDgqTMg1R4UTR9E2GBN/wVE5UI2PFD4ZfPInjhp0Y2aOigyvazh7y1H2xFGWIGimueAop2eOchTBlmpcFRyTrk4cpfRkzuAoJY6803ObOcoOjkrIUf6y6jeV+MIiw3bamssrOuhZ27/W9N2q6avPNH1+KgC+X+2z+lT121dF/aaet4jtEM5SlJDXmjo3Q1eS+pg09VnX1quuPQtnSmh/T7IwEO7qWuiVZN+8HQ7uXEjkxxgFj4fSy0m/vtat91Vh5qvCLM+e2rUoGoYNyMCaz9XHaxvcaoN6V+VWwrl7CZobe4zp1ZMEfVmD5CT6k8flxu2N2MyNSWNu2So2f7HSuQUhnu6fH+rKJ7PUMNclK8yNe2XLudN8jXNX7q2ar38qml7dWVeC+6r5FJ/zfv1HMWa6FH7Efikcnubb6y5NzTk2R+ZqU1eaWzeVBNvaKZBr6h4QSR2U4z1257ph1lFKgdfATaMzHB0rttDP3vsxrFuoLU0rwItj+o7A72BSAgjvphrWTIU9tpqB1+m1nQqySmzH5AVDL7AAC6OH6Tscv4Ol2LYgRfOU6ubgoKTGQ2Cb8aOM2nbGaqGfytZtd65+9Z6BlCrECERKnzAmmmxw2rWnKVLbo/qYk6Z78CncDMON5V0fdiLvtR6qWKeIvNeaVUATea8FsAJmutte1kcpuW4auuUfAg7DH0Ig0XuGRJ+mw+h0269e2puVvuXOTBf/Lk+xn1/xO92E/8ZtP3Vd4b1WB9+73VeLvQ/nZrwW4k7naH3xm7HTOXpfZUa15iA3BeWr35dFnVa9DlkqilHey9IdyQ3mi31pvdgX1ot9x72yeH31ZtPlYsXNvTvIYr9/724z3NwrlpztWDzVZnv4Vdvxuk0j3rsspz6rWe+x7Dvy7lLbgXkc0URKRvHFG2yKhYcyANfq8rdgcqHY/fVmRWBTya2e6de/ZYKXhv9V8N9t0vcx5IZvUe6s1ZZ43TJyvLx+uKymRj1Garb+Wm6+rDbnE8eaT+jTJcDj4bIajM1G4rLfJy6SrQP510NRneYwsI23cmN5jWhVYHMarwfpXsQsUc7hyyzFAidfIGWBtjgGMvhLo5BZEeQ8QPSEIGMCIigyBMZN9x/PVWRccYHEANt4PZH+5iQOdMw3jTz+NC0jNFlT+KPBGqfpwlvoRZCC0StITlpiBZHJN8dUvy+UkXpf6JguS8GuY6fvcPzOSBBZ/81ciTlNEDfd5YpqFvhRpy+/BqXc0FOUio8bUJvqP54o34fXJzvU2uCUYybXkk4WNLGEVi+0chMyUjOtW+Gp7LD0V4KGa4JMeSELkdhAhHrF4kERkidqzaeBRv6qewLaEMxaAYkTggkWWDC1Icki6/fmKjJ0et/eiJZi1UDUFMvRG1R1fkuKJY5SaOcKtghSS/G8p1hKTrWUd6sgbyY4518y7G/9kkG+HsokT/I3v5K/HSNXpx7uS71zSSpeiuYkzUkyPRQGbK57yP8CIcnDEQ==###4744:XlxV32DM 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1270eNq1W0ty5LgOvMwcgH9SrvBVOkIiqYjZTC962TF3f+AfECWV3J63sC0rSxQIUcgEwNr1/mH0trz+UorvH06y199W6Q/2AX81g79/yd24DyX4+kqneIUEhkyGJD7lXq+fMvo9ffzfTcTFw5GFH/YbPqPjB9zOvP6Bj5sPLgN7pbPJFq27LRJGlSsaVeQbZfP6KfU6Wip0t7SfEq+j0YJPRgtJjJaMp5srarTrRjPRjBaRdaP162/ntuwlt6Ubvn4q7mU+oYRem0P85BABA9axBdymjq122cdemkOOXpC8e2Gaepinvk9Th+dOn5fxx6kLpvvU9dpt8jAUi+XGLF8O4wRb5suDywP+MsIbOBK/P7NXkyNeP/Lvf39JJheEgdden9mANA7g1VeA56NkZf0A3DjhO48Ih4m9frjNZcRzgoiElDGFIwhPiCnXKIKwhOhsZ3ZZR5ROiCqIxohcEyILYhoCBieHALQygFRgCk/bbYA4n0zYdoGdBcsHoCXPNS5bG285+GIv9xMIL76woiCKIMkXlgOid7kTJPnCuIJEgiRf6JBHUx4j2Re63EcRC7IvlM2jKVaQfMds+w8b8hIwbQlkKJtt45IRbgkiEpKMk3rXBOEJscUERRCWEFOQDSPJbBvh4f67acfS0wV/a/j1O630/WNxvrzk8UMa1db8xl4/LS9LnAQoDnHgIn7yEI5RiYe9v5rtfYSBQ33Bgy9/o8Y3yFE4GnzK51MWn3L5lMOnbD614FMLvPOuGguPtfw1+CqIPXDKYqN3lk+VyOYWW/6WSAcRT6GgwlJUgncHXx3zKWz/7vMpbP8e8iliCfhq01qoiUaiamFpgQVVo6YZTwsC4IFGWLx6SoJtE3ewcPKURqjUOke9g01h2MRObMo0exrJK80S5p1t4m4K6tzOJLyQoK5tjoaS8ln3XhTde9Ju3VJxSSyVMmLzg/UzW3aK98a00a2whOLpqHqmK/E6dXx5Yc0FhUbZp6ODJxR6RZ0HfnzHovENi/4S0oUabdLCLXFIsxwKw4aRHIdUIhn4X2Ikhc/0C5Ay34SkoxI+E1kCZDeLIMSAdXUmJD19FMHBhGSc7Ah/feZniON/ed+yMZZyhm3Mmo/SMkgUlcN8WQjtompnnpyQjTWKnYNBAVFkBp11eTA7QTpTc68Xggx2l1Y0ExghDcEWTpBONFpzhhDMToKN58gI04ATPUY6nyTHR4zk5xgyuwOlkdE6Owm5WLJektmZVMFsRpBktpblEWmEVLO5LWZHclEyW6en5+vqy9KgPVuZWFBsMV3DPbxXfB8sKDsL6lMWVISk5OsJ+8XjK9UIUR4YdXBirDGbEqCZCXCdCdB1AgRuUXaiNGLJrl+NE/upFIYO9Mgneox7p0dKos5XxixaGTRgZUw506OqEGHO7cicjV8fMGfPPDYd8jzNOYUK7bdOV6skFEppir2eUKefomZlU3mgYxzXd+VmCwehDpp6lreamT3XmT3dKceAhBV3eat3z/JWMeetZqYdNdOOfJS36mPeam7zVv2tvNXe5q3qNm+lDHv6vISfvFAp+kvkm1JYe5vCyi+msJCm6p6VmZ6m2pamkhTXHFNclHwJTKQkYRM4YYP/OUJ6qmdrqldDdb8fyhJJamlwaknyUUvyUZLE2kMSKzGCaHtfF4wM2haRUwQl2KshyKDtvVFwRUYiX5ZdQ4gv8oRjbPyY4huiOqFtIMjgVG00QQanhvZM8hHmVJxAQphChI+TzoSgpFO3dL4iI1E1nF4zklsjDUGGTtnVghCSRePUW+DUm6TrAqfrMIgl6w8JROUI0mWhijvHnhvqVcm4EZ82xQvvoypChUNkF3woC9WVhXmgLCaxXlNuoiyifKIskv4AZeFqtr2cZN+H5FnPcsLMosPO0sQdsu6mQ37avebNojBPz8bf6hP5uszZ9Zyzi0mUVJ1SagxdnJA0/qBAmtwwsyixs4RxR1GCFIiK1wqEezWS+HW7ViBsnxVInKmePVIgnlKHUsmxmlrYqMP7wZ9hSKSI3fmWR7UI8bpqAILBdifYk6oBTfqpMnOvm9L9QRWJQ7XgTAKp/LgOzojdGWo4YxSF+VedcdMdEEnf9BKK/JrK0td18dkDVYDJg9rC2jTkMS5qDqCe164HdzbXHI4PpgobPsufN+V6QSQzoT94WiggY5JLCCpBCNWCeHI/zu0DG8TIMQ1DGN0J0qkbRpcE6XRfXdYQXLZQfl9KCSK/cVkrfeb1RsQT2LcRS7tEgv8DQnCpQWvJ0diwGuvQ6ehH+pVlksSfAZlUPzMEE9ECHGsfcBNBkPZhTQkWgwfbAiLJVDrbCi4iQTrbNuL8XV2TdR4QRxE3O4KSV38AlZQbOTzckAIQ/5aORFobCYogQ3OUaNUQrDnqu9svGoIIhuNkuFHnYOixRVJPEYoYh6omqmvDvFaKF4Iray+iNU5KINoYdFV2EFD9QReqiBUj/E+RrhhB91iCNMWY6yZpjYLY1pCiDnWju7qxRN3cFzSWRwUNc13QEF0wHKsYhfffVTGqhvjTKkZ4HVoBTRX8gZzw7woa+xyScblA6q+VC5ZH5QJzUS5wt21uL56VC9R1dswf1QjMgxqBvK0RuG/VCNRtjYA/qxHEmc5nzfeQQsODcoG6LRew73S85dTxFghrpQSFOt6jB61Guqt6x5tZhJOO9ygaeEU73ii5VjQhX+ho5x1vddnxVpcdb3Xd8Za0493yxuIs0vF2vePtPPXFsePtLjve7tDx1pwgqOOtGUFOO97usuPtDh3vLh72rn16x1siiHa8OUFQxzvuBDnteDctMne8m36pHW8VZJorJNrAWXZwlumc5U4zcpp+86ttQS0Nl4c0HJGfm9vYyyHHPqTEUx7M5zq97Az3xd71f8Nh+8xh28xhPrWzA1vn1KpnwqvquZXZAsmEadq7X+/MYnOuG2hGE7mYmsIjEQXS7DYES+iT3mh7twUMJutvu8+dFaQ2pPtM09s4180Pjeiw3tXsV6VHIzrMJDxxjrzbYPawV11ftStKdJ6PdJ//HyhRzmWQypLywJIoq6zLM3WI07NLQeUzOxdFRXgpWp5REFwktATB+WVLGdIR6R2HVaKLcEIHmrRelZ2JGIfvlmNksJTyst0pLXOSt5RV0iAUf1GSW5Aef8HcXt0E1xwSDY0gVEzGiUZGejoxUtTiX7C7+gqVZwML2IuDWyDn38i4PbNX0S8E6akNvAYb9hTqsu/GEWR02fc2s4p0RQEII0hXIXW5NwTn/L6mi7X1XJZGTqGUcvnZ648Ffg06sp2OlvcF4tpnZjMN8Zm0xFxGPiGruwLxVBX2vSrcMrjGcxO52ddN/ZcyGrtmND4YbS7nNoaj2dqB8SaaC/OuLd9p7sBtjQGP+dnPRRQ/LSKQ9ADCc5bKVw1okEU9R1rjTfl3m8ucbG5A73P5N76jRKVyELoo/8ao/oPybwj6pvxrZE8UlV8ebBrbpjLnccsarhjTuarr6m6M9vvVXRWcviH+hcnbbWfd8LGDBLM9jK5utp0tY5P26baziRXlOX+rVU9u6ulyjJcd9S8siT3v7L2SCCYiiSDe7wgXJzopXMoWyd/lx+ABc/SAgEfXPGCGB4Z6W7/igV+NAIA10s1KEghxJEFrK1ZnKNfxILKMNFtnpKbZn3lV90M9Dg9t+erznBzBEeYpofvmsgQhuQHIihHUDdcaD4crwrqJl4qM5FvrSJCRsGsdCDI29cUcsNucc207T7kd6X5kSL1bOdG9qM92DPQhUym8DFmPdD8i+wngIwwNWSrQNdl3XTfAEVZ59Z0tkCIqT/moiibKV+VdiflDWFkqx9DlSFkCMpaJIqVymNWOIFQqV8pGZCjugKOmRtCkIB6CQQgVln3jX7moy0e1LoYgPUnHHZegcWIPZsdutiQFbGU5vgaVygWzGEGbEgv3FsQSAQte2NGNaH09aHQV0ra4HxQsLaJ3eV0QvO3CYwT1qtgovAeLFa2v/YIiGutTz6JRh8jLrn1Fdu27LhrXPxON7IlovN5VcLqLwL2+uYURbx0YUlHMlf/nFX9UDzmrgzR9d18HaUUPM8vId7X8LddBsjOuJWH4U0l4siPgTBK+3REAFqpbveZv9RrtzX9nm+J5jx7Mm7bCowa6kduJA7MIevtdutt+w4Ut/FrHgC3rmaumUkdRJG9LHbPkF/FJ9V94ulNf2R7iwHzM9mIUKyLt/y6MXDPYvq7nghgSZiHSW3IR6pP3nfoFwb11eqMhBEIUCCFfCQhxXKTodnZtVYckbU+PZneUpM4TGSfIqJijkk2UtM4T6TWjb1/Wa0PIVwSUNchuSmsBI4PWgFh3jJwTa1Sk04xoOipa5RmsHxVmfXAcfq6EurTEyKAuTJEZOaXIjIzCUIk2Axl95tqf4Cnj4Wzw3dL5bnvwLbXp3Wp89/wLa4dd/O27a/ZuF91yzX/ro++wGbJ1jtf+r9ymBDCKsV28p+uS7508/PSdsHWKN2yZ+cTQUvNuw00Bf+HjO09M3RTwb790dthMP8XbXc+d3LiN/rc5m/8+UdN1z5nrw6Qzqi8b7upk0qVj8G5TmnvYaP8lZd/ykaZPt+HqWlTNSC5aJ4txT0xahq8eMUaupnfl4NHid7Iss/LN0a2mMzaULl+v8KYjsl3YiAVdhb7NJQ2zGBmxpPbyZEPKDLI1ParI1WliZ48qcMfRcmR0szFjBIG5/Q+1uI3H###4540:XlxV32DM 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11e8eNq9W0uS5KoO3cxdAH9MZvRWKsIYHPEmrwY97Oi9X75CMrYr6xN3UJWkTwJCRjpCsv/80tHsD6vl822x4vn3t9qse7CH+JMQyx8ybvvzlzJBPxZfcBM8wq0Wzzcbl4pYgvCM2IQYtu0EkRlxtY+pSJlC8S1De53IwURZRLkmEVUbLiREluFEESG3WBNG594F6VOKvIxYlsH7Mja7AM7qMt8st1UmCTLxLlNoS4xkISwvxCRki3W4t7y4Lo18/v3rlYtZEv9QD//n/3JPa3FLCM9/5K7jQ9rUUorvSS72fE/TpN8+/2dDvgnp+y7K90XI+mm3+rmUz/fFxfp9ZeW7E2v57kQon0rocsGrlanU0OmP/alTKx71MwtkHnETRZ79YUSQXSAR8YS+fvoi0HvWCpnhb55Cz1NEmEKPKdY+heSfm8LtZppiX2AKCVNEBlPoz05hj1MIJmEKNaYwMMX6mSl+pyn6BssqI5t+lTuC8l59S/e+dhKAKLorVxkRVDqlDZQtRWxFX71TEuHZJq3NrE9o2tp8K//zsIq3YTNWhk37qsgSBUKqLGnr1U4MINMWsLKMhLoDu5SLb6LUVvl1a9nSekubvE7G0Yh1srTvi5F7hoe0Wx+ytMqQrWVL6y3/qzZpZpuMYJPxv7FJty93Nml+wCbd7u5s0v6ITa53Nrn+iE36O5tcfsImo4Jd5g42qTSCiE1GCchysEmFoXObLJ269bnRXEfTTzbpYFh/sEmDkINNWoDWC5ssUjb7c9BaoeUPNqnRiBc2WYZs9uegtULLU5tUZp9tcgebFP+NTaoq/oVNBvUDNqk8v7HJ8BM8qZy6scmw/IBNKqdvbDKYH7BJ5brnzyq74MkMYZtUjgHCrngyQ+c2WTpV6yuTtqZTo6kveTJj2Cbrlu7IBU/msc9tskhZ7K8ssracgpYmNqlMRCMebFLgIYv9lSFryyloaWKTwsd8t7hJ95k7sMq8aapVLpxaZbUqW7xD/sxaTT812TmmfZAvWXxpK5cWfMmVSw5fWtOlReGOu86XtMCXRLkU8CWZLxk8/M7zJcvx8Hu5RMZiz0vfkXZs8zFetU89ugpWJvB44XuZwBP5Q7lEJItP5If0rvKshjqJ0MyLOwmhrvYO7Isl1amme82QVLzoXnN8yZdLAl8qutcSX0q6f8+no2r1Ii5ZLEsdi+liyREea61BLJlGlSsaVRRxFNabUM+j0EJPQgs5CS34JLQQRGjJeL5T6twbcsnslTv82A2KdK45KkQw0ccWOxys1A6EIV1XyNX9knxaumTz0uO89P1wv4w+Ll0wDUvXCmTa0lCs7nTLSvc0TjnRp/XyyrfgKZOXKVoljlAyKRGWfdqvIkAeJ+FNVwkvrZpaKD9IE2d8ZyvCa1LCLwVxFMne0tcxuSQIz4ipfQJBWEZ0kVOTPkpnRFUES1hzDl5WxHTEZFeeGIU6bFj2cMnNfYKykEtOhgTSJZMiutjrfALhKEGTEEWQrAvLs5uvPmMgWRdmqUggSNaFDmU0tWGk6ELXeRSRYORf0mg9nZNnbLmTULaAkQpBKNMjDRcEgbyR1DsjCOSNkgh0NEi3JMRjJIudWKdyVhlu4iwOnCU+wVkbcNZEVGYmqmUmKj4TlZ6JigFRvcJO8mV2OlDQR0QVZqKKM1FtB6ISd0Ql/OeIyoPjm9jJzOy0HLydW27ZaXuNneTMTmZmJ3Ep6Rkl6SMlLbeUJL9FSestJZmXKOnAOx+wU6MicaCioxbCkZ3WW3bS32GnZWIni7DOTitip8Ex6/DIK7ATXxBO2MkrgiB2EoIgiJ28Jcg5O62X7LRestN6zU4LZafud6uyCDs5GC+ZFNHFkZ0SfsFOBcHsRPtgduIEOWWnjJyzU0YIO0mgBnFkpwVBlJ0MQTA7KYKcs5O4ZCdB2EmHct/DQzzC4CYB3CQJN3E7GySPk0HyEI4GycNkkDzKo0HyxIqIAsOGqJCQ2iUrwiX76kkuq8DNjKGa1QvDd/DSKyRik+c4+CUWJ7/E/OSX2DafctjklxiNmttNsuecliSM4EE3ymmnHpQvzxuag0v28+ex34lq+k7LMo+d9lutC8PI2J06ME0Q2NEJiQQBK9ABjKoiYDnp+4IQbG5CuzGRa8KpLJxghmOkCKezu+Jh3wmShdPFf4RVEGTU+kL3pQ3JwuXi2++21TqCq3xCLRavKDuQZAAlgqzmm26qTf+GlUqwUvWClcrZSuNspWGy0rBfWekh5Ums9mCt+pg+ORiwnQ3YzAa8zQbsnlOy9X1pkdwh8pUQ+U7hrvhkXuYbCV0dgrrzNpK/5G34HAU118JnB4RtmIWPvI1gi7tOORu2fj/lnJQg7hyaZLcOjToyqpd19m129m1m9m1+9m3uqJf1Ok9umP9+nlzrkhm6OjC4rIymFxNvDgz6eXWeaWmt13NYVAMmXKfxDdu+n8ZPU8TrNL5h4ftp/LT5gDsCDcjS7D3mzjcbZ/gx4wRBGWfwVxBX/BVIFCeUZRgBb58YlI6GGdRRCYBBk9gOxHakxpCOhQqtCBUmEiJRJ1R9aC6qTqQIS2HSSxAhvUARID2hu1IrgmkX4tLa55R2CwK0q7ZaQe5rLUWQerdaM+1RaEZ65krKBW2kn6EqhxiRfemFSiOpk0EQrqcEJpEspQxS1VxbeYrWiviko9mucb9c66j9aiv3a62I6h9ZyBWJT05IUnYlZx+CTkDNp3Sk3s2l6F/5oEknOOgkxBJkHI50T3A2BA5UQvbyWEXGESghZDQ4NmWPJ7JyU8hCs2MKYht9HdscA5oW43w5oFnP0mrj1DBFFOyu6DNFFHKKKGrmjeTScpCRggl7kkMj+S6STuu5Mz0nykg6zb9U99nzmUiXJwkuohQeLJw4tPNzlDJRMPuZ0KTtFnmV3AsQN1jPSNxwdY7Bo/Po/Q37CrOORfMb9hV3xaSJffXMvnNiMRMylXS7S6kZiEWMWueUGk5/HbNrfE4s7nPIsL1S+8mZOiL0xm+ya8Jsn8yuCembKyr6wHkuuXqCQG6s3eOO1ExSkaxl1aR0Hd94zcUlF1sH9RG6euxi0/cVIWTQkp4Ka0SD4nSYkN0FV0lHDi1Nt2Bk5N2E7I+vttVBri4hiiCQ30uW00+e2YZI0CPlhiAU2WBSKciIX2RQWBfY128eIyNFlm7KTvQHbJMQTRBgm6QEQxBgG76vocuWfBWKKvS+CYyMqEJrR5FxmNd2I8iIa6rLGcg4zOsoEYLCpLTXt5oaFY81/Ru0poHWzNcSa/ORPfI7hsu0ZtvncndOt/M53c3n9HU+py/Pm0pUPpxzeijXc+no1dpTO5RfncDrOlvkfyw4+ZcY8qTgtAFDplM9d+R0Px7TiuGEmMAhux2ISa5w58U25RDdfKq31YnG9phT3OYj2CBmF+FRKssDIeYPcwX7HSETR75pc50gSIf7H3gmrRY/aD0q+rFMeERCovhjnxIEYs4GzA9xcElUrDXb7iqIHo652e1NFcRDkMHm5ASfc7EXdUWaBNZ6LtFB4khvEJJJuYBYYgpF5sQRD7MMkaoklCfV1EVkFEcC2gpLIqPzeqS8WKFc5rM/G7PAxpJmZIWWaYV2DmFmxQs3hzDL0dROUhHDpqM7MbUSZH0YPp0UJy9N7ebpf6/j99MhnaoSxebJyEOBVQPyz6/SanFN/lU9Oft68JeQ05ZLfbPlLTnKyt6ivRiTofJiTBmJhGplreM3HH4DwUs788siYn9BoEqLT/daS8jiS/q8Sd1ZZRKt2xs69TejHhg0JF60buuokV/b/n1gcoTeyjNGXbRybK8aGsf2liaA3+SUQP0NSgnonmSoahjRXlKGJwpioCAU95VwrN6oWr39VdwYLrNo1pMtFRkvSsWtBT+qVZpjznrVuIhtqBMOG1PQo5C+SKAnBUZwoOcZlmEkt5I+FOxCQx+Tjf31qtKCXdje5mgvSUV4cSu32hqCJdFl6Y9iu8YysnXqqg04ZhzxbEMgZhyxqYLyd8vhQaRbx0UZr3qGGDeKw42CrOEWHXp1q80qC7A2ILme3q0CVcRyHOkbuwJbA9Lhp++a8hZYD+B5DlDlCFANBKj2NEDF9NrizI9i1si/WAzOuZvrMhMNTN0XAlNxCExfLwl9WAdCUeh96ua1wLQneF5I3dxUnqKcn0ZClScLdW5rOQkdSUzF5qTBWel7/2rp29Oii7p7T3AbBZFvFKOiDHPs7kEvCx9hRyCxJo2i1Lw8TqOoKP0c1I6q18LOoij29ZAxKc9cV6w29J7S1ytWsbw3IC+iUrPIE+WVqJQqbxw+Dhq7iTvT6OI27jypcF2oSV6XtbYfeWMsLP4mYefYeILDi08l7Foq7oOIU/IvJOySXm6Czw29rPfl4HM881VuNQ7ZotwRgmOudMH1960V6+9bH6K5qGBgxdr71uVGt6i1Gn0dPgzcNFz4uKP+KIZJv9+gpz9k0nqsUEYi5cMIqbQoF/rkB+QVi7PDoU/b/x1CNbqkOIHkx8VA39/mLfLhcmSEKLj2qXrzOBZMHNLfE8xbFmdO9xZ+dARC+La5O9JuVVUj5AnLZsKHi+YNO1TW9i+KuqmR###4816:XlxV32DM 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1270eNrFW0uu3LgO3UwvQF9LvoVsJYCtD9CTl0EPg+z9UZJFkZbtWzcdoCdVLh/rR8nkEXXKfIgP8fMvnW36MErY1/90XpYPqbV5/WWMzB9eh9ffTiR4sHzn8v1Dp+jqDSOjLxe//llUWOBK/fymlfNQmd1e3+vnr3+0Wh3B/K5e37QI60epp+BSbQdernQK+XgAGq64WwjurH5997uvNdceDUQVpNYpvGCILMhSy0jFEFEQW5HdUMTYgpiGsB7orSC6IX1spcPFIABtAiAThaHD9jsgPgDiRaC2kqEMaK1DFdn26vLCTZFbc5rgzRRONcQypJjCSUBsShwpplh8QwxDiilsrLVtkSLVFLa1s7EeVFMY12o7jFRbrH3/7mJdAYvOBKrddmmtiIwMUQWpc2vzzhBZENe6YBkiCtLmdgsUKd12Ceb2166ML4sMlrSDj59loeePdRXbqy1/DYvjWPK7eP1wsq1wqAK+4ZGlTFQSL7hlRYOsJFBMFVL0aV1vaXpLvqDu9tL87eJaXyew0fE7tO/E2txKLdW0eCvUW0cPk6eQq9BKb/nSZlb1aa90bdPXccFv48ijGbr3t7fHozZSSBVooW1lW245aoWU6y1qhazrrTY0WP+t+bV5FHhT6u9VNROsKjbHAp6jXOw21jdvoY5KJnM4KgWrp85f/ljslvoEqniaOCXS3cQpEc4Tp6Q4Txz4mVfxe6E6wLKa1oJa3q3uP8Nme69U1NirRO2wt++92vpH8QFs4L/KyMvL6XgTcYw89DYWldFbC+i43ualq+SGFsBb+6sbY7KAmywg/dkCZrZAQguYYYENeye/ZAGTop4skJcepFZYbN0CLmIbulugd1zV1/BY79wCyrzOy0Et03JQcjKGsmdj5MkY2aMxNBoDPEjvqP2SMZTZtnMTSmhsQo0m0JGBb/5CEyVg1UX981td3iVgfavT3K9yv4KukHAGrvWIgfUZGs9s0o5W6UKv8rjK/apUCVffywdUqTtlqIuAxLljUXSkRRnwZrWQC6wQhjOl/cYQDIGARIZg2FTWJRyVqazlO3jP1rlEy4wQqLQRFBlhE97mHrPKe02DozJuJw0184G/btBGSpEYaKNIDMG4aaPRDMFYCwtZUKT0G2JOMermIkUwbpZ2LKsNY60yS8Ru697tWI1qF0ugajoIdrW6TWF1B0tx3UCGIaU2qxuyEOQwnXRtjiItVPvd1oKwC6uu9NsWWiZjzgwpNrVtxldL1nGb8UrlDvJQEViobawQs1ohCtVCEMWKUUNeydqvZPiY4n6Z8bLUSjhzdf+Vr+zwyss4+MqOfMV9ia+cSMkn1CXmO+pCqcqJdNgT6TizlhVZy4nIMAKzzASmhK5bosJ5xmec5SAodPhZIGcpxMRRYgLuktogF0v5ulDx1l5vMbJRO7fTsefa7M6GEOotRqjiqzKe8MR4IBp9kfGcaM0n5EfEz8jPsTRvmYkSvYcmrDMz4RyDkxQ/d3qdOn3wFsZXlpmvbDxE72F9IBMibqPT7i0yQbnAG7xCzrxCYadPPfXnniqhRk9XXAAeF4Bep57muadh6qmWU0+1mHs6rwlgs6dOlw6bm4SCgLjwtYSCjrGH32KPthOurbSkwNFgw11LJQDpKFHBWKNIUZIvkHldSSG6Wwco00Jjiw+IoMhIC0TB28FMAnC/lSGYffCS1TUSFlBkjGelpEKqYCgySAX0LFFkEB6ojSNIeLzIDEC+Y3RaGTJSCzHSMmwqMouO1TMQXgGrPlFk8AqzeUWRwSsY49huOc92y3k2ynng904QyrsOR9ugcOIV60YgxisWQ5EbXhEor2CkJ5xID2sHSU/NV9Tq7IeHjxH/A8Z//5/E/6fUxRMfuMhiLPdZjPDFLAZnAnJmAgKZQA//GPM/TU4cW6Y3uEB8iwuEmQvsMxcoMfcpLaIf0yL7f00SgNLGpwyJ/CMZEvmYIdl+m4dcJEuW+2TJ/nmyZEtPyRLx75MlNgY1rQjkN0DK7MWKqPyGUwQ9kxk1jfyStpjtKQey5n+fA4ExintmBGM0VxP+FjNK7zCjgwapmVLpE39idtnFQ+JmTX8gcbO5EeTkbTCVNJgqJTRFRmiG4BdwRxvp7n1s+VuZEeiPV7Eh+rR71wRhUdb4nTREMwgsmOrbYKppMFXCrAzB0DzyEQ0Z4Zzu0UsX+m48jcuxR4d5ZOdaYFzfq4WFSViejSPTUhGkecBUFoYgN4XfkiBHYmtvaSDfCVjtBEs/9OOYCtH0A8nmlWk8MncJrzCbV8qNbB5jWZKyLGhL4nyd8yOBjmqQZ/AezBKDPAMDNMwSyJ6htkTaoflEYDQ4++Dv6FlW3AxDxvlX8xoDQWJ7+MyO0FwiTVwW6x1JyoRXmLgs1huJS8ZE5YmJKoLwDKDHVFpZejQDaNdEIJqFtGumwxrbAuCoCxtw3xb82oFGlU7IBXZq0g1WGZFVrpeskvrPgxxeJdRljBO7THI+GBNk43tDIdeZQi4zhdzeSildn4mdWaOdWaOeWONF0ojTzhOHRMZmUtxnsmLwMCNj7HLOM8bGYlcjXpeHGWKfmVuemVu6TDpA9/w9l4Lu4fnCsvgHLrXOXGqZudT2Vk7n0zMomEbzwHlcRBa8aPXAeeYeHjmdK7ZHsjaUNPFuqXMuZDAh5YoBr6nQ56EeFvM4r9hp+DtmcCAYMuG3YAgGRpMCq40ExhQSRWqo11vtQffb9aplA+qQW7CCS424Yt77CEkdIkHniMNYiIZZE7QmDdIsR+pJhAPBaDAONA6ERIN+SHQg9GRpxSF77qD1KglEY6IOO0MGwdKJl6GRQNAuDM9t9hjYTCGNOtxHRyiNYidinh3rpLhQhKRfUjSsc50x/tp9JTUQISy89iNCJIwQG4sQ3XunwyW9LVRYbpyycVdbejU7ZzsLEuTrHT+tX7d7/fMeP8x7/HTe4/fd+zJv+92cHDjv8cmePmU57+mHC3ZjB7fz7exlOHg63V8+86xapPiQLdcew4G1ds6WTx7WzB52mbdX+vWOs+VH71o5c+9spQq/72x3LZV9yMSrHZMYJuuH/Wac95t5NkiYM/EXZwbps/2mFsE+ZOK11v9G2mcmaZ8mWJf2WSLtsyics0PPZlHat3iCU2mfzIohRNrnJEOGtA8mniHX0j57K+2zt9I+ey/tM1za56mtmLQvddVfebmYKc7SPsBvpH0VIdK+LBlCpH1ZMORS2leQa2lfQai0r09GbfEk7dsJxKV9K0OotM8x5FLal+WdtC9LJu0zsWo9A6z5MAJWxoC1X25prlV8cU6FJ7ZZcaeUsJ3DxTJ7/SOmVe//+rFWw8CeILry1mnu8dG/+IziNu1wECrcKtmW5gjSQeljFbCYmx2Hzyggc8qxHQevdWbmIlzvIaKX5+EoIUaD+WI42k+O0M+RYT2NrE64ufHLPqeLkVW/zGsd5x4Xw/nnmJ3CkcpVab4s+kq5jPcEooza9JO/an7Kz0MV22osI1/9mcHUY9cc1SvG8kyn3dXMxLdBxbZX7GWv2LOEFJS2WJolpI5J6/W2UcICbZAghWhGao3NH1R22oehK9BcSPXivbF6oGWlKC+GDIVYJnxPpcD3NJD39JxySK/pbGvKVH89+0AzGv3d7mdbd3Jc/1YWws1ZiBUJ71l+e6u5tbenVpTyng6o3mGs4Q2FSiexk0JF7dE8pDJElBdSiotURphzBdN55dezGjRTwgQKF2LSwa5FFFeqins5rX8rq+HmrMZ66Tvh7fD3hBuGjBJSK7d7wv3Ass+u7iZ5cbymd2csIuPkFvcycd53iG58R3Ki5eeSk6jmKDCWYRiq6P0tontUWHUOUR2SkubwwSqdsRT7UFd4zFyDPE8it11UL0W5ZYwotogGJRXQaiOD8LylJUnaPFpDESo6wdRzQ9D7y7zxMuj9vdgYgPR7yGvqqKiStfztgyCDJcKgPA5K80GlNihWkspVDEeQx4L3kgxB7gtlBEOQL1OVT1QHcW8nWFTl06W7LVdCVT5duttyJXiE1oBBSanKp6uKG431kgPIfI01vDJky1T/Ew1LuKnAkJGko/qfaJgYheh/oqEUw0vPgMFPdBYMoVqU+q6o9WODjxG6JYbu+KVTgwd5ylUI168b31VpwZ/VpFxoVP2TRrVoUuTx/fQPm3c0KhcJLf1WQku9flvEEucEV36iCw/KFdzXPMlWVHpgDkmOFNf4B+LjIciDkuWCOUhxt5QqG6HBxUpzL1+xa/z38pVFeDvvz/ZujPJW9u2SRGUAxNPzkYuaadSsSJWG7aCW9vdIe8OGnFnw5CTzPxd9Ks71T+Lck4ntvSjGEmHE7/+DKGrzkMb0wYx/EMk30pj6rTSmfSuNaU4qkZq6ulHP2D+hnlmEuOBLuD13QzNG1lvdnvNs5nzEp/bX1SaerDebc5xFMGq07a/W2/pAHR+EOCe7rvfqG0uUV7+tvrHO4EE8uDcSuYm6pLiTQ0dSln2XlGQ/LleeWoXnXNvW14krcf1bNSNTSnTG1Z4ZNBFKB4oM6nksg47QDT9U1zN2rSHkiVBdZAjhlv2PNnUIRIDSWcOBUNXKsRx6dVzr0v+tXP0j0yUpTxEiMzZdulz9GpOsqMCQcTxn5dLN61uuuD+DBA9+S1Kapj3hxkI6cySHck3KOsHWA9EuuaGfqgjyNUsExwUZHO+IEqMMHgku+Bf3AyGyYpUIQtNIELD7dFn5f7+woEs=###4872:XlxV32DM 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12f0eNq9W0uy5KgO3UwvgD/4ZtRWKsLYOKInXYMedtTen/gJydiuvH3r9SST9LFByCAdSaT5CFG9vvt9ef38W5nDfIgP9c83ZaX5MHLTGQoAmV1ogGyDQoiv3LKtZY6AraW0voewwXPysLp1We7Jg4VVAGLFYWmPfus9lla5u7WW0vqeP7KQuyM9ViHDkoqQuslfWjptB0DGFjlcIJC3EhAXKmIZkiX0ssq+MSQP5FVBvKSIXvM4vvYmKAKDfw+2PuMi601kZK9qt6h229V+1IdiIFBVn9KALHud6nefltc3J4IoAmagdvY9xPD6Zo9jr8DPqIRNAMUP8xH/+Usf7vhYFqlef+gDAB3T6w9j5AGjiNcPeO1w7+tPWBn5+wfIU37D6PXbb/U7lO8f8Abq71WU34tay+9F7eXbKFsugBTlySyk+KcObWSyryyQ+3ByLfIcH07tugukEh0w1u9YBPqR1cVGyBP1+zxEwiHiGGLtQ2j52SHSNMQRcIgNh0gCh7CfHeI4D6GExiH2MYTDIdbPDPE3rIi2wovK6MpTSjoCkZUHD0VENmYl4CFLIGJazHYsbbeXh0CEVxu0N9NoHrX5vXyWbgN2e9RuYV1VWRJBqiyw9OpDHqFELQ+xZUXKYrfKJFsrYeugtgwG20mP1PIQY1a6LIardNlaCVsHMWY/o0xL1gtsqvCh7NiVGnflQXbln2Bp4G6AXLZ8e3rBJWPJJVhtcMkKekmXS5I+uJdLdUf7YqEROl5583u6+eF7ox1u+enEhnXlkqt3J08hX6BmTdJCoQXGCkV+WKamjhmaWMFWwxFcaAZHtm91Y4D8pSFqyx+2AZ3mAdOES6ZBTYTo6C2x3ELncqRyKVQLJ5eTZYt7FtFzs2PahpViN33Hms2jadtPb1WJ7fxWlUjnt6qkOL9VJeLdW1UCXviP7A+baYm7mCXdh6S6S2oDegV9Xn9KxklS6VDSs3jS34onFyYeeLOsYsONKyrS29DF03KYPtXF6zKhILnr1LsWbrbbDruWqXftDtx5Wp/ndJ4Ilb5t6RvXEM3yddcAClrOClJCDAXFKwWF8/tT4/1d6yr42QGpMYq90tVy9/7Vhu8fLx2vKw2qWFqn6ZGNpHC0CM+LuuG9OFo/zXqBMQvVz7WZgOUurUYMY/Fzdaxs1HMrP5x9lh8+C6DySrlLsor2WPlkdIXNJcOQ7Heir1IsiCxZigTOShb3uEZBhiLOCnhfnoRuD2Xa2DvOBDLaKowlHVc6GnUVRlGk0NFoijDCdQRalCvb3W9UmMG9u7fqGmHcW2j6EHGbVuFIsK8JWQbpNEUGWYZZO5x16LMGOSlttjKSGRBKDyGCZwhS+mZZ+oj1FYDnKFS7z60shLx4OnkBCNcIGM4yA3CJFREUyTMAzwjILgwFstjgH8sjYWGIzEiWICBhqUAmT6kEX9bwzjLhSlkyve8rQcpbrPLDrqiDjT5lk1znBSzV5ihSJG+h0pIoUkS3ovbGkSy6lUV01lkRvbxIoxN/JIte4hQQPRKEiX6UOMa1OAZCrv4ia4DjSYDT9kINcKzM2pDpw30oMciU6WRqE/dkqjInRqb24x0yleTZrnV+pU9crQdV8L1e8aow86oNedWJTzWCVnjViYUxirVSisWEBJrfWRZeyrOrhAs7KETJ0wkf9tVpGF6Sr4mRnRnXhowLL+2vTr5OpMvNVM1TOiORh1FqhkEnUjIImu09JVNSeSQ6i3qgZGmmZPtblOyYfF5jafrE+Kj7szbcR8jWb1+PkEEv6p4Agl6QqlpnHwhgmAlgnPXiX2fedKKLjAuuTBkgaZbSXRM2kBSpjj0WRtiYWDChs1jKTq9LyZmizBJCFHyScDnrctAkkHAbZHplNImTsX3SpZppfyNRVGgtJqG1nIU+TmtMx/vkgvW/IbkAemlOoWiIUCQrTWQIUqT2tgeS+UUsPjAuG0Gau8izaDyu2v6SKYOLNBPQeJzOkA09y1DuopQOYvghr2W+8lglIp4mAuF3IAhjUTUl0Edt+c0s7+BTjTThPTWrmu8Z9An6WahKCLmLG1PWIHegYMXUiFTRHwebCTIj+K0RUW0m4KcY/SkQoR9BLAxAxgJC80eQ/oBoO0OQ/lipmWyDDQKyM6mRA5qdrCRPOSA8s9G3OfgN/DYUGfymWcWBIL8ZnKghSHD8sTMA+Q0s2EiQvmBtwAWrMbVrA0ujgewr1dHgm6A9TxHkm9kMla0JHNLCxyA/FsmPZPld2RjEr0hQozcXER1NI/GUVIvoWhrpRHcmjrM+cZwTOQqn9FGjOzk/LWu6h6WTTlxnpiyc/ti36I+Y6Q94hBwur1PWIpFwOV0E5WDPz1xjmbnG+rqOzy9y0CPf5I24iM8LubmMz0n6iKeipvgcTK2afHKK6PE8Dqw1LjpwQKf8DHp8O1MGNbk5qSfxgNhTfcAOWJ9IjTlQHyTzIm7FWp+YDKdAXKzlRmtlg/o7JgOGpvMEbxmT4TzBzDxBzzzBvUVu1MwTLOUJfzehi8GBFnVwQUSCsErXMJYZISF73DaGoLk2+zDKBSGOSfNniPNd0VyvqgXzYAeq2GhBoUW9WfOauj2VZag3EVfkZAkkxj0C7yFxvHfsHoX3oBtsJqGmG9Yu4V6TQT51CFpNQlkzESbRnsH8t56pIxCW3gPab/eMFATERJJqjiReaHpl7ekVEIM4Q2UVFZA4Q2VSZAg6Q2X2g8yXOF3oTVNkkKtlD62QCW+291jj/IVUOJtqe5yfzTZ8eBbnO3R16iHO12/F+eL/GOc/1k9ObvGmlHLhA5mnfK6iPEXy+vVQ3OXh+/E6106mgslGCyZzdO7kU3Su3VvRuRTvROethvIbonO9P0Xnx2+JztOTI9OjPKOXf1ueObm5m0rNhU+jno+HwftToK7RvfklzIH6XYXlKQ635xez3dddrE9fr7vAgnXnOdJQX8erOS7nt6DF65fT3a8rI1anh7A9iK+H7RC3YBjm3Ai00wi0dwy001WgbQq0j0B7G800xdyWPNGD5A1biR39wYx/7XQuP2BHLZLesJVYTC37mZ8yRx45R4qMyBnWt2AIpjPksbLeRjojiJ0BmM0IYgSniTIGFmsnGmvDb4pQSgMXRnc7j5zNQpFBxQBJDCEHogatKghSMcL47E6ZGKyZnSC4ZraxZjZ8cfsp1pWSTphSHBIFJ0psWBScbrMLiWcX3Hh98hT1J4ZcRv2OlTWC0AygUT99BDWxN03QJJNjBRnKcx0tyPyMUm3LfHDLI9vR/8nBLanKkbMbx3eEr/s9GMHen9s6/NePbcEI7t5HHO7rLgJG8PcW+rBfN9CwGtrqL/qih7bswSByaGuU+8prZDvw2DSByKEtVx+y/aFixOugvelG059M+7GOET09tNWWc0eoB7F43rH0zQ9tGSJLMet1kq3lsOXZAVS10R65z0iCdpldTu2ytRy2PDu0ZWry/LQfA+5H85/sR2Ptcr8fU5Rf35AwxHq/IVMUX9+RxpoH1pbW4+tbEobY77dkWtNvIE22+9miMronjXeSQGRPwkMBkYUft/bdJxXock/Wh8ruq4O2ptlGc+d7EmTxvVuz0z3ZlnRHGKvzziC0Xe/JKmXef3WStWU2bO10T8JgK+mR7clV0umV/Ve7rC2zYWvne9IVowIEcfmQ+9iVC+5Ke5n+fmLh52z2m8X7h0j+oWJPLMMvLMLNicb9XF/vZXI7B+Q0Vp8q6fE1WZ1oU812XSe3lRvWRm8rS25zBdN0bfL2Pn0NXaJ18cbcp6/fzFnD+ohzdr5by12RY+fqM9ayzOOCF2E23A0Tppdjzoaf8ttiToxfFs7l66RL/ZAxcMPGea3equc/pAkeivgnje+zxhNqnBDG7TPOo/S8zedDA/ZMTliqz/iMokf/UMt3UWEJwdiHWv58XkTLOUe/v+7Ok9JyP1dpmg9Gapz4YMgpfMaTgd11ew+csgpIdAuIZQg5z7jxZzC8bWrsCD1vCVPotj9PhqcPPIWodxqOJm/j6lTy8uqtDVsszoced+yRuy7XOWjZOiS4NA4rEWVWo94OmlgoMrIG0Jsj4zCH5qymohfnVURvrQ1bLNcBvwN2yf+aARd67j+bnlqdKLMYgTDc49k9Eu/BkBjuUewehfeMo4cb1n/yPaWC0eSvr3PzkeiRZiVAXZItD0ylACLowKXAUQYe0T+MoXH+kZOjrZdOiguhpRO41xCIROzNgVXEjYn08yPQlCiTQ4WxUwBwz8HuEXgPZhOWdiCzljMaWssZkZYzqp5rOSOWOg0QH/shl0Fd1k5d1oUHFOtVFT3MFYRlriCsrycKcq6a63eq5rVE/nZ9oVTPr5kNZzSdvtyUHC4YzYkK3fxzgx01HLWIw21zTRv/ErGMY/s28pw7T7CH2Ysvc4J9fb3pRFWK9r5oLPVw7NY+FY3tW0Vj+fpM+l0x36SFWO6dstRS3kVyb/wVLhXufeOWpUro+Myh791y9cF3qfgLt3w6iHfz14UbZ62qEzw5a4sKMSPY3N77FwPmcIquWWSnhQoEyzbtm6q+t5SbmwZzBja3Wl6y2OVyUFyl5AhOfLk6zMEQ9P8q9RRyQ8Z/IA5rGYKmXwv8P3BBhg8FhD0z/C4gKJv37WQ+i0Bx2uRfB7EXv6uyiEuGPdWP0+fdxXRx1PEUwUmeGxDDkHFKoZqPgYyDaPi/34ZgCl4Lw54ZaXtAmASjcg+9dc6VR6T+FtzERiD6L4EVT0NUBN27XjGTXhEkByCCYQhSC0AiRcgZNFC6vvJkET3Z+u882Xzmfap6ZwP1a/elntzX6TT7b/Nk9N+GJ4dkZ3/nZufmZ+f26Mncoyezw5P9Dyvrisc=###4144:XlxV32DM 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1230eNq9W1tu5TgO3cwsQG/JueitFGBbMjA/Ux/5LNTeh3pRpGU7CRJ0A32j8rEkWhZ5SIoOWr/+6419E2/w1wr4+x99uPBmlJKvfEk2SLW/Ov/9rdN+5MbfzcbdQcvD/+IP9LUJ+gr1+h8M496UU+GVrx5vzuzL6z/GyOMt6AWG0iud7Xh1QfBSep1l0kMmvCu+unh4aX91SbGjeBGh35UJuaX+/FPEB1Fev8KmMwL/UcTYjBhAzBo8RazIiAUE/m0RsW95mtcvL32BBO8kcydXESaCVRmpfYxliM5IqBPR0epEYVMVMgjpLkNc8yPZVSMU2iPZ3EkJWByClEeyERCZhGRIlttVGfhoRW4vqwiOIVlu34Sj8zS5ja1vIhG5y5vwca9vQlIki+1TWe9g6LMWsX1qi2oZIjPSXgSbJ4vtU30goxmiM7LUhZPkvVYJqtTCeYoUCeAHFi4eB0OyBLYuz6oYkiWwbXk0Q7IE8PP37xZEBES6N/smlz9Zp463ZVH2VTVN73tXqU28fsP7rlqamkInN3RApjWrRfINChRyBVropQCXgql3B6pf8lAZspFeEvmSo2MeWVdhZ9QBfLUfIezFfoQl1X+vov7dNO2aNR+0jl6K5ZKll/ZyiT7icZRLnmi+KGJsTLINLhl4u3nqzaaUZXPUgMkUmwGTi9u6AbPbMGDizmzKdTKbCLnJLslA7dKmxbGcjak8XJdFhx1lsRZl0d2YThbUTBZUqdmC6teTgdfKZ5kMlyl0mdSuu0wqCZTJ5ne9tXdbhv5tZNnmY+lhbKm2e/IA0CF5HPq75NGYQp5o4fSSGsXoE5+wl7Rv5wVRwuJL0uPN7DCUqDvdF3Ofx4lVp4yMobKRU91wlrXOy/P6VX7/vmu1BIJlY/9PESCPk/G6ghnPrWJa6w0wccHL2+s4IROtpGUIEpAWQTMESQv6BIYgB2q1GYoM3gTEUWRwLSDNihaB84IAtGYzaqIw9LHDBkjItFAtIq4V7ClAlvKo4sDhQI3YUhx1Ok1wwk+AWIYMTqvGYSCDB1OSDEHu1GqNFBl8CwiToCyF8XW0TgF5Rkrf2hlBIMJP2snEEOQ0bY+dIciDIIJlCHInIKwP8i2wkJRXLOSQheI9C50ohhGSR0JirHPipn3mpgW56cRJjKYs0tTETQK5Cccs1OHZANkwfpKx9pmxDmSsE011TvJnTjrRVOI0FY9HmvKPNHXiIMZYfrKLMkx2UW4zeS1n8opP5LWIR/LipMWN+RB6Ii81u/8XFty+TpS2PVKa+halxUdKC5+jtDitQiOrq1VopPVBEJRpkvNYfOQx/x0e2yYeWwnWeSwSHovIEnEY7zh47CA447EesTWE8tjCEMJjyjLkmsfiLY/FWx6L9zy2MR6Tkq4V57EdWeK0FBOPxVsei5zH4sEQwmMxMeSax+Itj8UTjyFZwYwnHpME4jx2MITyWGTIJY8V5JLHMkJ4zIajEBlchZ9BZB6JLDEiky1WopopkzxrJgTLZ6Mq4+RsypjOSgrB4mu43L4q1ODPuM/R22Vg5z7FowvyKMxRFgJYrcUwJzIVT2TK6ZHxaiNROREz51VYwd/NhJ559PhU5JfmyG+bKXVHSn39XuRSabTmAU40iumqoI9unrUJfTOo/WyexTqZZ7FMzCrcxKzCT5ZatBgw9YRa8XBPEppulleD5OT1hhLGSZw5ABLbLM4+ixNfl3k+qy4WbhsLh6Ga3g2KdZwXTtrXbeQ8J/eknv0Qw1fLqpnKiVt0LLhaxjK36EOHZ7lZB+vuvRyl14hejtofvBz15OVQv+Xs8FxQvZmpXr9OQpvzy1NCDKExr6CXwfphEnqbhZ53vVpnoeddr067vppme+M2reEY71Ext4nPfcxzz1tcXW7xd6V9trgamCOvV+ahf4pcNDlb5czskls0Bat0cX9Gd4nd0fFQugRz4x6B96ALonTsBFbuGS4I/NsSJK/e6xdYtgKpHgvmVoXAylcIx+spgp4a1usY0FEiV7p7OxUhSWO9HhQZDgMswMYQdDKUTmwe4pjUnTmQkTSuitYRljTWPfauKzRcsWY8SypVRJaKNykGskIk0wyIoMjINCu9SIoML8OkfekvsiD5ZdueLak+CgRba7sns0592Vkski9u9gvvgbnbPSPbDHwX2DgSx8HsMhjWyO5ReA/JM48cuMA9Utxva7UkUF0cvZYHTYI9qMIHRTdtiXXRS9a6T6sLkBoA3kfvVoG6h4oP3zWgZLyNLel4cInftuGhBfTQDp5qCM1V6m5NcyqUbmnn/Snt/HtR1dVaVGRhXJZiPZsjmXpslDZkFRUxiFOJTvhhoAhTbPMUCacIY4oVDZ784hTFxtnrODdt/i7M/dIUZrbbGqdwYwqHU6xfmeIdFqrtzbJkNVSCN13O5PRBoGyHf8G7L530gsjaO8VQOyUClU6wgUYAa3unHLq2SVsT1hObhke4Zh1iAlaGhX1VH0ATpMoCW692Egjp9gA0cuyy5MixPWRt5btby9C4Eu5RZEQaWJpV0seDV9CHrK08ZGuZ0vqVf7JOmhJIn3Ry6ToZxb+jk2b1DzqZwg/opFnDg06m5Qd00qzrg06m7Qd00qzbg05CJPl9nTShEXpZMq6ThkJUJ00wiPiTTqKKZOhaJ0unqn1l0t5cR3ObdHLBYTemkyZQ5KSTHqH1RieLlEX/ykO21ootluuByQIZkeqkTRsbsuhfGbK1VmxtTCeViduskyvqpPxXdFKZ44En7Sq/r5MwxQNP2lV9Xydhiv1eJ+2qv6+TMEW810m7mu/rJOyItqXLklGdlIddCUR0EjoFRDhPQicKEZ00ezmmtr1T0b46aW/uoxm5TkKwLHDYSHWybemOUJ0EWXaE9pNOaiJL0b/6kK21YytSnYTJVjIi00lxWDpk1r86ZGvt2IqcJ2OJtCSEZvAztHJDrVSX+UWeTNRTmn9KG8ZzwF+ykneZw/01HcateBh3WxLi52M3d5e36ydapkEfJesiJuuuajM2G8u8Nykw5UaSzq7pPgUmxUcr2VNi7FH4KQnI4qd8DyaYQJZ0Vd8mprzXnDpplSJP4rWjOX06wCPitS13d9wUNhTP+Xh/3KTlbVruKqWSpoqR61qJ9yZeZr7c4hVrCYvCYIlpWkIeXpJeJL4H47FRZORG5NFr2Soy8imAWIZgNmZYlYZgmmcYqYaQGry0oNgLyzAo4z15IlbLNiLvjJBatkVFilzXshXkspatIJe1bAUhtWw+ELFZLRtmYApyXcuWlrtatrTwHEPyDBm1bBBqFMi8LfAzrOOO1lFfWscvHKKcrOHJ6bm2jv7JOp4OT/x86hLmUxd+xHLytcaRi1VTtRw/X1Gvr9UtfOzHfWi8T0b7onjhosaOnrRQO37vNtpYzl/NzRlHXDAK8uvKDPwXTi9uDLqpSdTb1I79vsvqhIvz4/WzEpkNQ0+3S/dwVjKfEdTjE35swg9EnJAXUTIeiHiFSR93HPxARMynH3IuHVHzscn5jMTU1O1tast832W3tUDZ3RzDOHPlIoxi91Pto5hPUz5fZHJ6cv+UcfuBSMJWq3xbcG/SpwrutZzPco77AhPxdIhyUygJixGecoPqB/IQI9mQ9xwNbGzAMgDYKuQAA3iI9qFxEihPY8miRryKXnsC0TS/OQxDkI6bHSiIi+xQRpmUCETPHKxsx0gVyacGbeBx+mB7BXyxZjeZlAyRqE1hjr8OPNyTZjMKaStagP7eDHVHTp82IHQcp08bEkPopw2aIehWKRMURegXGUO442DHYcu2stHQ5aPJ07wILVHqsOWxFViiZqR+yj0kzLTGEeQurZonaylUhy2PrUDCxXc7vrHILXrARfyrsnnpRxbok1UEz8vAj4sMGR9znPuQ4h8hyApS97x7a3+q3KcE2UIgEsHTBHrelz1V7kbTj2bgiQEnfGK7EN1NJ8LKEHQ3l1ZuVA+YmpoUb9MJsWPRahjeZkRv0xBv81zjo6canxZzi9kXlbMvehEZlSKhXuPTfdJP+KLh9VDu0x3Q4XXygp6f+3IDXElfM35bvIiH0XUTO6Efz1w37tuIuYBmmytW9rliJd7GnrnkhdAPSOruI3eQdFRqhPQQufvZCwuzF+Y+9bUc7FA9V56a4Z2ZC89Qq7sPPOQxCxJP7qC4SG26MaG8cgf19z8bgdW3c3Up2SejOGb7XHVpfZJCX2Ln9QCEMqXulCl2Vpxg5Uq60+IEEx1D0Ni2t6XauJW/QRFyp/p4OX2YW6WKtZ2lR+EQcZS1wRFcGIIuRJAbA9CDGLTTkFE0GSNFapVokaUWzALbByI7Le0wh6XI8IzksQg623BKpOpf8BX9Z8UJS6IISR8cgSNoz0N/FQ1Ac270oRiCjgg8ricIe9yjirGQ91FrcKvfA9BBn2r4PSAhHZRUPSytwKRwa98Xup671FIWIHr4GbySkFfsxzneOOltT/vKmXLUXGn6xVzHZxIc3/kW45M5jpqq+DDHIecaUnHzbcaX0h2nHEdPe9g5t+Ha3X7OWYdT2uMpx1HOrW6T2Gb7VBJbxNnEi5kVtzkTkj7KhCgr9NPh3Q8UucAiLE/Zc7M+Zs8fUuY//fUKLIZ5OmZcfyBnIUta5C5nIRUuuD3CQ85CfipnMZfONhIni/B/U/+YaA==###4924:XlxV32DM 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122ceNrNm0ty5SoShjdzF8BLIHzibqUihAQRPWkPalhRe+/koSQTjnSOHR70xJaVBiUPkR9/IqXth5G7fvxyx/r4+3uRSn2ID/XnX7iSHzru6fFrNQuYTEwBTMuff5WCUqvbH/nK4dWKV75c/co//v5WSrpaZfmf+rTVx2wyq0QTVBQUWJSuhSyxNBeTqi5qdFE3F92xZZOIB/He6S0777Lzx2KoBVr0a11qdTJRyyKy5QCLTEYyiwSLXavfAr2z1W93+OJBssS54oE7SjeEY6GW7IGLS22QpJbsgYu2esBqyx646Iol8jLZg7jWMoJZcsfF4ps0OLbQG7VM7YPkE7PkMosuZXq/wVXrbOmKSfNC2Tn4AU0VylFL6QSdB8gKqamldEKZXSrshtWWOwF+wNDtyZN5Z9SytYmHl2u/9PXyV/mZWxZOJ/NVm89B1Sm24iD6NsW82ur4amIq4+vVURqwhmopV1BfBJPM3auWMmV1M2Xn60PrlAqllYtWxJ06pYItj4yJWfKrEFwpc76Std4yqUN5ScwRqaVM6mDKdBeavqtrON/VdrXilS9Xv9Z1rw1X5F2tL+SWR8E39+ABK7YLnPgbwL/cj/L4sB8y/fmvTjZ9eG+2xz86LfHDCPH4xxh4y9YgHv8B/+G/4bfJrwP8i81rQhQPuLUIekuWW5LcOmK5peitVG7l1j4+YQ1rv9szInvGnv81WnrLlVuO3rLl1kpv+XLL01sr3IKlhdyCxQluMeeSLreO4gwsHdS0ZJOjrUui3KIVxFRu7bWCtfz+hLWz/g6q3g+mF1EidxvMtmairU2hmJjTe7nFPMvPzK9PriEscs0Dn8uIP21AZTSPPMz2A1ZpWYY5fViYwOc4w6vyfJyViOM4K5HGcVZiH8dZiYOMc36N80WefCb7vnD3lubesvrTO3Vo9C7SPg2to0pffuZVoNw4O+Bv7oH8P5Y/4sAeWOL5DJcfV5+hxdhyGaaWSze1XNqp5dJjy/EWzD7SCYv0ZhqjZPsYLU/GSOtzjM5alXmMTqsFnR49VbOnSk2eKvkYhstPw5VWHK4NhyvioqGXLw6XF+NwQUDqnaGeDZcfW67ldcvn2amOqeUwA0jLIVp6DNjgIA1EEEg9MZXom1fZv79XYZkBo8UqFTNggIG6IrNgGJFpY2VIsKgBFgJXeZtaKM0jxUOp9Bi7vaGg1Lq8WxCU4G/FLNkdJyumbMySG+1yd5iweWIpPVXdad0l0kLcrcxZzIQ5a0xSf1o7CHO20IjFSxgsxXsYlMljL56BtbLaKiU1dFRbxcIMSGowIjuzIKmBhZchpLbSMhRxAfxYj3bEhX5ZqaUjLvSGw95YGe9TjoSFnqAaJdls6agGf0dq6ajWlspuQSSEvw9mQfaEibAyC7InTARqwYlQuQTIA6gn94WMmTxiJ4+A5CEJeXy6sg8ZVr3GFAxGjmOGEY1L9fnuDy98IZFOHsdOS2+Pb8LI+haMwFL8uZoW8jmUaISSKxJpjCEnlHGq4YYbcEMT7DhZg9FDxY6JNQ5kjccnMHPji7LFueQLmc7leoFVaOILTgwcNZ4EXPFqFAtnsNBadlPuKvjLA0PrFlnwZ+7J7fFNHljf4gE7OF2WHMOjLOnTcDqtPVKRVhMPCHQaQ2F+SmxPEdFMXNSpQxxIHU5ujDp4lWN0lXN0NU/ZD15/PTZTwWajOiCd2bGZ0EGnA+uIpuMoqPCgzWyLzPKcJ+ApiJg2JcYTrFY9Tz18YHzWvN+teXV3p9lWs/lUTWqECVxoYRbUUvAK1y3mSkrRLaaJjjyKsAHb1FZt4ixNNrUqsHoRU9oUyc7kK6omQaGNPrLvauGVw5BkBAt+VMWBxpHgp0SJmPq0wDPqM0kYbLEO/6ds0Mv/dJSB+aOIxxRliEZiBI3WVkhHLZ0WYJ5YaulqUFv2qsVyXUUkQUxUjBFxZy4gfVAtxogr/DCC4QcJ8Pk5PfSrsEtqoaG/S0jFNxL69cYsJPQb3h4S+o+DdTbSoW9dUJDwtOpikESGaPNNVxhwuTK5DzCwIwyoWYbg4f0KAt6QIZp+oQf9AnigMcfh31Qk7AwB7i0I2K4h4IkysaAywVHhJRrISaTIusXX6WCgAuZvfAIKMkZzDQpSSVztF30DClLcgcI7QkScwm9WMEhcAk+Xa8EAPEVmWI74NcHAzoDg3gKEjXloDhuvBQOA7S7qBPU1wcBOTjcN4VWM17N2oB5DuDe34T79TLgvy8hluNfHV8P9EOZZo9NTsIEJZOeWkqneZ02A8iLWZonU6mlrDixUa0WJVbR1trxEZD3v279qoUr9ajA+Gy50mzPLUjqLagwxaqwuR7XD5YDnSn2OFqLIAqtCK1XmJZUC6jw9LQM/eOIfU8WjpZYLmDEnzJQmUIVesMYhzEBfbczNrmXUF742e2kb1dIDMDY1xRSInW309cosGJ2VOCWe+rSOOuA784OkshBRmoddoUm7YBbEmi511BnQI7qVKjELieh6YZaeSJJyYxZkl7Z8nxbWR6mmxxSZOnnunjm1LnnUTiJqjIis90jibJPMgjzkk2IAUcb4zGOEqiY42L10gDgQIDQDiLtdzEkP7yHCkLR4KR2sMzX4mRr2mRrsTA0ue5Ba7Fb6GT3Iu7wGZ4yX9LA8pYc3Uhwv8hlTEiPyJEapz14mMXpEDoGxw+1WtYHD1+hALSbcZSz2n8hY+HAnWljc/y+r/pposc5M4mcmmfulkYseyIUGvRoFhn6JZ7+ko/dLVxPkF/tl03d5Eiffy5PouzzJIFq8wh77Cntgvux3KZPjJ1Imm7hmHhg7JCsr5cw8N/mRqW3sXYAQ0xXwjWUr6G57YzkR+FsSCwWJlsgwRecOLZFR5hXmNHae06BZiE0PWYidWFB83nkW4nxWyUKUR535iH3IRwRU4Pdn+QisKOcjakUtM7GzBL2QG+sXBJeuCTULAZeTr2pfkLM0MLY7MZEDODTPsOmrPMOm+VGajZVhGaLELCRDtAlmQaqCMjgCnidBYHAwz+BjH5zQBqeLS3UiXCQ8fGAHdMRKn0dlHHI2xbOsT2ekZkHOMEdPkvgh7SOYB50GadrJR6a7EK3GR667+INZkNJoYsVHTmk+MMtJabAUpAIRwKuw0Tg6BEWEIDND0HBiQ8xSiZxPbKg5u6IHWprVE45G/vFNQeVJVsW9EFRYCuUGep6c62gcNALUIJkM4oeZOecbQsr+XEgR1zAklcMkvNFxhqHh2IaY1RI5H9tQcxJGD9TE97/yml/AQ+QXt6QbfvGPb2oqT5Iu7pWmAsuXu0mHSGeenTvQl7LEE3x4cuJCzviwjKrJfqeaWHOrmmCtMwsq93ihpbTF5FJLEdtPainHlZai7rQUCM9f01Jao8pBPbhiQkY8+o5ZMfmDSQ9n7iGX53kUQWpmhwOPnVmQkywGrXJFZZo2IWtkdaN4IkkpfqTwoJYuntBTKpujqLQKwQwY9VcRmIEE/Z5G2BwP+kQQkSw4RiJVyS4gqCaywJZf0zqnvM85LFxa8Ik+rtOAS5EaqObgmYPIAp0fmoWwwGKZpR/WrWtxtQjeqMTIo9gJEfRUWLWwTMzCLEgELh3MQBIxRAQSVLbxDR3PY5/RdbmknJue8i0JSWH5br7lBh6ifEdXaUcxbnWVDg8nMbxzEnR/gQmcBeR3z3iOTLDPTBBHJjhPfl4wwaSQ5LXaq43tBSGK2e3uOIYRKB149d0syx0vpLcklWPYIpfs56WkIn9CUrHuTlLpaYFF+7eQ5Gr3/OwEaHgNH0WyMxcJnc06hI/NMfjgYVV/40wndM10QpiqB6afPt0Ci/KcMI6ZMGbE1PKOBSZP91FKeaJzaJwnqkspHYW2r8yTvPhizLPsgD8M0cYsXeuQNjILah2wz5XEgvtcgfvc89uVcpN+wkAPdcLbgQKIGA51ksOU8G+neCGoeAGe9yMEHCR6TqSY2PnOlJiFJHX6Acz8yCZzCCpzUI3BJn46RC3UQgHF8q5HsIJuREKB5e3sxvzwsxvj2Y25r9j3UP3rIFgB2AmOfuDBOv49j3HUQo9pmINZEBHIuVLr+Oc8njlAc0d2JRb2HZTUmnV+Jy8iJEBX0POe5KBIttBDH9ZTC0UN65iFiA9dyigWZA1yULYYuvbQUm8jUSwCicJeE0VVFbgcoWeiON4hiiNeyRG3n5dsb6Vl3FtQYefPS5YfTMPMFNJY5Z00zJ0Gsd8d5mB6BkGOIO6Qw/WDHWu4OQE6xw8pZuQIbyHH/kqigAXrDjm8+Ank2OLddydEp1Hy5hjJ9lbKxr1FHeM50zIfLvMpq3gvn2J/MJ/yBFf0MHKljqt8ipc/kU8J+i6f4u7zKXe6x3F3huQ59vxu7pQlNyzDRxieWTBI0zgRBI0TJgRBypzBFNx88nkGEkU203TIeciiWC4/z0A6yMUJHcigmNvkNENX97OFZC3k1jMQkUdLmmuKNPiy/FRk39/iSZdmIadBXWSWHv1FctQ5mjgJzG2aOOlKSRD86E6X98MgAGyRWZ5G5SB4VDbMQD/CSMSCCNrZSSE7Gc5OsCE9aE/Qc7GdqoLmWSx3MAvyM4yFYxaSK+zKT9A8VxgMsTzJFZ7z7OTjPBsJHxcoyZWDv/nN7VAiEUrc/xmUcJnDPe445X8k3G6R###4596:XlxV32DM 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1370eNqtW8mS5agO/Zn+AGZw3uhfqQgPENGbV4taVvS/PzEJydjOW525qLqkxSAw6BxJ2IUPo5R9vf7xVn6Ij790cuWRLI8UfWTKIw2PXj913FMu/LtZa/IjB//Eb6hrI9QV4vU/aOY+lF62V36aPpw2++svY2T6CDpAV3qlvS+5d2PpI18GFPTROmu6zZqGV9Ewdg3dMmuomoZyXVzX0EuJGi6TOvusTprU0WJW57hauF9t4dTvv0sp6/v6sciliIrGRQSl3Ob1I2wKREqbPJxurWCkV62US1DHlzpxYXUE1hG5ji11gmB1JNaRuY4rdfaVaAgvLEt0UVAH2trY3hpKUMeU1kfqrX1o/bpQJH5nkqy5l0WybkyisyTP28Q1VgmUjrYk/ljrdDVrlCdpj9qIqVCUs3UZo+rdQalIfKwLE22dWpXkxStDln59rAtjBKsjsY7MdepL2B2ro7COynVC0Y9pUbeAT7KssA9E9bYFjK2zwtfiXdO9Sw4qKRrDf+Vl7EyS9bR1yaNkkqxdW6PVMonOkvr6vSOS9jJknfZx0IXNe8YfO0iWVNvA3BdcCl0EvgrCFnATguDfDexIbuM/oKPf+bimj2Vxy6sdYpn6ad3E66c/8oLBSTuW8hvKJoPfUH5/Lmotfy/qKL9G2fJgU1bmUSy1DxL2QrUPdjHdPKhD9wFVpANs9XdTZSAjd81GwIlYboJ0HyKtOATsr26B1j8Z4pfZUzv0ZT5Z8Pq7jFuKP8r/8H7qZFWvBh3lF5R3oxXJkh5g7NZBLv3I/0HzOpHePNskaJ1tlpJeNElpkyWw1LWNJ5I6JLyNrPQhNB0ybH1IKP2AN1d2Qe1ZajDh0o59sL5wJck+4FZbRolW+2SqZdRnUy2PiKYaH4H17nvrp0+qvgdVrXkoY8Hfxtdf2+S27jGwd20vyvarLvdmWCLfk3Cu/BmzZDSIqnvoO8atC27K44xZIt3NXskZqMR+nr0S24uCPcD0fn9U3Kq/4ajIsnanISIOYccQKx4V+UdDwOLm7g0bIpHFNYOyKBxDdcrSFxlXlnGNUoVrn9xgQx65hkbrpfX5JfU3c0W42nE4DRH6AgUxbAmeC23/zJbElOsYOJb5hVdLkN9LK4EC1CaMk59L9XzDjh7nGzsq57t0VEu5Izzpv9p7qbBiKxy2So377Ag7sMyEN+hjAH2RINdoL6RLGI5Wi9mVaxYza9eLeTbUeIJaa59pnkS2cWAKqkQT1StVMr4qIKmEcpDDdBKVJZWmFfWRwbQDp7qO1FxXE1E79nVmbZnbam2RyAmwAzJrJkFgb4evT7ANl1SdB+tusA7GBjxlHdbajUmQdSwpNMz3CmfdML/YTBkB9mUc1n5Day8Z6ktPjiQ12pyrdyCgpwtrJ0LQTzQC/m5nvhAo7K04IpEhTfFgoqu1o6eiYlhjoI9cebTQR/71gDAMWXqTlD23CjL4KM+T4w0OkF730BNW8UyTYNes95AkV3EMSNoeIGmb3CiR7l6NEpe+E2ySYB9wSLiv4xBM1xbuyYY4xnQXtOQ2op0VZ79WrpNfK5d7UJ6dWekmUJb+dVoM94CYwn8dMZ0wbnr3CGtQH1HZZYQjsMaQEj1iN7vxg4ydp5tjEXy6/gH/RPgy/uUhwj1dd+PVf4GuV2S0mRTDXm7MNyAHhjn2UqAYqWA5OpnOdQoErcXFq4azSgKj2dBIERHh5g0DuxrdawjDgYBBsBhOcFgdBpxDdRgCug5Zv1YK3IlwnsyBEoa20UBUShSulTKBiEhsQFm7MgmBT+OZZMQgEJqaZMQglEJHJjgK8gCukbYhUC6cI20obgIMO3SIbQPbuFQYphIa0hgI3Rph6IGFDCwPOHR3vUkwzACSRCXDJx8coUpIGETJhDOy1NFrOFDbrNz5F86SRpStDGZRWtEAhHQrkyBPkSkGJkGeAn8vVEJDINGyNp2MZOelnAJgFoExix2ZhbpkFpxG6LPp6vRBzfyD+pFgjN4mF2EmFyuSixPf8DOpCCdS0XhGJhfyyo39lBM0Owb2zLRfhuiFcWxUt1SYxkZ1S1t5xKgKeNv3fMNaMdt5wjfMAOBVMr7BsKb5uXImFWpmJcz1jSfXV6cHyhG+gXIADbYzw9qG84jutd6G058myqFnymEn0iXNtC5yDvpLdQqlF6tp7kiRwUCWN46RIj6Qmwfy10RPGfHAbcI3cBsYQj7509/AJ4CQiocMxG5TH8Mey5yBOL86Ld9KO8zRnJyv4IurHmhO+Aaa02ZeIBNKLJMxSEnWg/IVgNeFtKpQv4UTPygSTFbYtHHJSIeYEHEgySiTXAxtM5IXNi0b6w0TJ4S4ZYtQSVrepb0ksaQocWsxFWxXiFFp10oSS4qRpUH4ch1KlghTyR0x1mHCTkQsUjF8cihR1tHsT42VWJaOaCxGN1FLF0F7TkASq6OwDqEiQZIhWN5ldVRCsi0mbH0ueeUGFWkQgW0IsRn0JbdhTISkNYTnaQ0RiISnNZxhjUhmZeTqhOeZFa+YZGRWTEhk61/z8aJ3Zd7l7faiHEXF+fiSFpJhaUtfgipyN3lAaXMIPQzqcyD10TyV0mhJbObnOqqxzmxjmdnGKQiO4C9e5/hEC108chEwNvpEIRotOdERO9MRxlD2txhKZgojArJrPaMf4rNvTDLjsz8YPvN48RkNLcfYY7WPGDvS1XB67jF2nTF2ucRYwB85h8PRuVcmonO/n2LWVyEbYNET7ugXH9Cke8Td7P51xIU5qXP0hiCuMoi4xlmGuPxWQpqolJYTldIzxVTHW3gcT+tip/2lhEWl7ViNHboS9WB4kdoLParDAu5HqOjbVgHsTCnVEHEZBRpXuehyUy1rFee+hjXqcu78Hz0TWPqmVwuMiFRCrgRIyyTjQkFDVdRk4GbbLKgDwT/wqSR2p7PbFTqyw1FVtL+Bp6A304EwiGNdmAQZBEj4XJGP2KNf4ijGgeAZjGOpZOAZOIwNJ5skY2k+9ARL4e+OHVUy7gxUI9T7ZXcGjtWTRhTawZJtOAPJEiTHGpgEAyHNEA0JBlyaxegStq9SAaKVAlGdQQWiVO8h5NOvxACiiEBkLn1weiqLK/15wL/lcm88dRrwp2B34XB33Ht0rXkmGPEju2LBzkF4HsVXcxTfvv4zYKKzrmdUvPDfO+65M+6d0DHO6Jie/feS+PJ3/rvEmLH33H9nJljE1zsphP3Jy7+8t1bPp7uGWRU0op7PLiCBWe5Zr6+75O0nrq2JcZ/WZ8DuKjGR67xgsMshys4X52aIUrO3r2Yn/HPoBqXjA66u+QJdJyfxHlcriF7nBuY3qeKsaZo0zShMwbRamjvnVumvO7fKDqdAS0bwpRZMgk4BuIGOSdCRaEuLEppgVYlKipujm1lvbl4psZi/tImIZh8DG1FUb5uyhk8jRTpQXBAJ9eRbHgCHGmBLYL1IBqzrfdV0oEEFpEoblQz6YKI5mHKDckipmARB3cTdMAmCOvw9ettPN+yiICIS6DdxW6mE5PkR70vpFM3faCN6QXFfmITkJ/zBJCM/YZ1lEnJHMq1sbxHPVtOdSj3bEWQvehMGAy9ipRLikUspmAR5C0xIMwnyFnIPokp6HqTw3qKC+tg+FLnglZAU2O8iBVG+Fb6P84UAwhM+i8KH/xSFv7lMdqISx3su9YMf/Yn/3OnAZxH+wRAmWrATWjDoQL2ic8LbjhzKSYw2aoVeptonOjDfExdupgPzPXER5qC/Z453O9t3CYflGIzAiPuEg0hvJRz2O1/8IcuwOfUNWQa55Tr6JoohR0xdu51FMT7NH2geyEjlKvBdIMOPiwnPyYLwbrIAFu/h6uDmxDdcHTzKNXR7c3XQScwW6MPcXx1EGiMYe2RzPM5Rof0+SAMD+6uo0DtBmtMKxofIjJNfj8zARLZ7BgkTwfCWPX2N8Vlk5uIDjYtMCSGTE9c9zuGYBwa5jaTNF9IjUjn02LfrNEMxCSWlUPZ3L0UsMV6lhNC0R8KrUopUQnlV6t+U5O1dA/d5vxHWYXbMDeQ69W5mVaNwwBaWQH1zKqPq20oRSzsPx+AnC3lEysKg6ojHnC4j1tPQRfSOBvKmOpdB0AZvqhJK6vATiDp/ws962KStB/IzGHdFDSK/9Iox/LIUNVpfp9CLcRQnAt7JedsRg4DvyOGyBIMu/b5nZ1G/W6/0mn3ceKc05rUyCdJj2C572xQZMGqUKlt0mvERokepqmSwvQoyqrVmUaoUaSNOlAe73vjVEjtu+OYS7r/UZt/ARjd5+9xm4/dJdjuCYDwpJFP/bKXNlly4SZ4MTJyv4SVUCb2EsgWmjEBl0N2Do29ZHYl1yC3ZrcXRYBt0af1kZqcBtrr4VXDQe7V105bImznKLV2553u1O5JsL5Bku89vvzRGLWdGrSYqzr+iiK/b2y5+vu3iXn/Gs2dyze/NXgTfbj/OAKbs7wNpPZd0w5jfSTONQBrQZLlUdrwVVLzhnsrseLHCKf/APbeZe6aZe8b5ssvOoM+msulvMl3Sj9idlu7hJoqab6LIy5sojDYmNS/FoI0SObBLidNGMSe7bpjkdUBu8ffcDsjWMYixY9yOz3C/jQhyb2ORD1dqkyNfioT5Su1FrO+dj0dMDOn+a10YFdmXXuzD17rb09e6E+WaGXz+kJcuRjVO5iasGNJ2xW6Xd7Ju6fLjW2U7tygnj4AE/L0yCVpju/VvMZpkhO6O/gVEKdHYGLBnvGEZEudj60Elg4/JVHx13SUFGo7+2WaLax3esDoK6xAIX0Ovs/iOiQtL8rRtWLRY5CkKtgiiIP1AGWblqe6Et9ZDpNqYtRFY1ALRCYE/qVN6almopvl74qopZWkhsdkInA3yNejHsjoS64yE14bfGG/rxm95WBlRQ8/uk5hjpRJyb6V+UKm7pHzFk+dH42W230ZpksGgDBLMKhkMKqVARuQMCinJ1jlih//IeEFSyAsS4QVtSfTr/wmsnzM=###4776:XlxV32DM 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e70eNrFm0uS5CgMhi8zB+ANzoy5SkUYAxGzmV70sqPvPoANSGDcrsrs6U1lBX8aCxnrQ6A0D0E3/vwwi3/+/C4cEQ/yYD/+5kyZhzE2KmaLCmdWHwpxMl7kTJRWskvqkCjXD83XqFieulvZuivSW/bQkjw/0p+oGLpEhVeFPtN/JP/3kf6kq4muVyeFJYVFJV/T+uV+81FyepcIuChKIUpUZzvX7ZACjfcUMipe7oqESrbTq6SswiElWedzb6shSEnWeZOVlSGFJ2VJxgXKgXIY59YorSRk5SN9vQw4+vCnNdRHhaqHfNDlx788qPBYFkOff/Eg/UOQ7fmXEDQ8jCXPb7G3+O3nP3Fg8TN+JT5GQaNdqUnBpjU3adi05SYDm1RuWmCTjk1GwAsDS02SwSaemxy8MKQmBbsPNDVpCptkbkJ9kdRk0sN7fosTNQ8wzr3903L41XwPKw5JHp9w4MHmryD7fW4y+duCyexCKwNLhqVryY/D2dS7Z3oEKj4LueRHEB5K2qU8A06ivwTwPaPZ95LApux7SWGTzU0MNmXfSw6bou+/pWmTDPxpOSXJKRpZGFSxkMd3ulgoZbWQx175Cnpl4tkbzeRgNKOD0YwPRrPRaMaw0cykPgQ22hSjWQwsh9HMk2q0TDPAHo+T5ZmQAhd6YskhXPYOYYTVvm0ofYs4QUvfS+8QTqpDiheGoW/j0EMdOhovcaIfLyOyPiTuqyFbvJ7s01vneJD6cXofZIy4ucPvim0l3iZXptE/P/LfHMko0KKrnn9nA1I/Sd8dtMdquUeg/QvxxllfNNBz7IovRu5ZUqSwpOQ+yYoVmhS1XyOQQpKyR1yLlBSL42vb00RCmiAECYQgyK007MatPXpWXwHWxZfHlhvF1wi5Iuy340DfXaHZrkikJFdomgM8o0hJrlBmVwhSkiuk2x+Zg0p2hdzvsyILsiuE3nuriIl3hCDh6+KABOjDV22RAoglDFIa5QAZs9LICGialErTRKxwRixWieXeRiw1EmupxCqYusGmHTFfYRN7hU0dk8BoGaEjplzFFCIXIFae7XNi6XcSS43EWs4jIM1BbYqp+ApfYeoOm9hX2SR6NrFLNumX2KSu2LSRr7KpYxL0AqejF/zohfDsiKWuiCXYK8RiA7EY0AqxFCBW44FqYVo1Yq1Ax8TSSIHEEkiBxMK9nRNLTYmlpsRSc2IxTKwAfYWJ1UjhsSsGYvkpsTwmVgXkrgBiUYeUc2L5KbE8JlYZVr5jRywPJEysDSmQWAtSTolF/YxY1CNi6ZCeE11j6KSuEYtXYnlELKrHFSF1vn/VqOf9q0Z9fCFnyFO3kKdH5G1jkmbGJI2MSZocQcjugHBP5fQI1TsgLGg7BWGoIBzoZ0f6OUy/HG9w8PaihC1NaAmwiofyPJnrQyYZV/aUDCGT4JAZZ5S5Iu9C75FX3SKvHi20Y65ouqAezBWElbqXK7IxVxyN3jPKX/KYjiSSHY+VuuSxfIXHbLni8crv8ZhOebyjOnthGPo2Dt13z8uGKwizz0I4hsy6/I+TdRYyzTRkGrhlJjZbtvbSawf32WKDAtIez9Ne1ndfEHoIdUMv8AUJdQ8QrhzisLuVQ4VamtsAagCEu9JASIIASkFodPWO0B0E9XazrVE12xqNHc22RuNsw0sDARW4nCjO2BWwBCE6IAUsW1remZW21KHGIKUtj/b5XxTkirzaYEbCAe8LsygfC7M4IzRycl0fHMGwKXVNAVYOWWkrh3jNAmYaWh+0RUW+qC0q4vrAo4kL92AJUsqaIrHenGWnorI+/Pn91Huo5l9F9a9z1sLnjstypPgpqk8S1a1LVOUVLk3481urlFzi0rwTl/KruOzTV6UvcSleSl/FJS7FJS57LxxsJGOueorLk5zVdbjc1ktc8hdy1ujVjjwGakdojAa0nLXliqKG1viFkrNyB3QUlBePFJizEqS04E/B/quY5qximrOKWc4aDZ7lrGnYDYF7TK2+wjlrTagpwa7oc1ZKZjkrJV3OihWYswqknOasSTnPWZOCcta6kKGyy1mLz7OEc9aAFJizbkg5X4DJ6QJMdjmrPeOYLByj5AbHlpFj261dVvO+c8F7e6+AY7c3XN1z4Jh/Dinn9rw4Ijw9F8ynbnN43TwXXEZ42Vu7rOYGvNQlvN56Lsg+Ca+OWOslsehLxLpO8PStBG9nD/ZCGL3gnhdHhJNzQXNJLPUKsdaBWAvQyi6rAcSqyQBvyUBKxg5iCQ10RCxLkAKJFZACiAXos0yJtUyJtUx3Wc2cWCsmloW+QsQCdFHYFQOx1JRYChOLbEgBxGqnkFRNiaWmxFKYWKQe/pUzzUYsASRELMOQAokVkHJKrHKcORKrHGdWYp2eC6pKLPq1zOuSWAOmludnzgXlyCYyngvSl84FtxuYgunWBaZmO6OEXxKLfznduiTWgKmlx9Rl+YoWL58LqjEqs5FN/EZi5a4wtfmXMLVdYmq9hyl3B1Oc3sHUdEvS2UtiLa8Qyw3E2oBWiGUBsWpI5aB8w1ZiSQJ0RKxNIgUQyxqkAGJtWDkn1jYl1jYllp0Ty2FiBegrTKzGkM4VA7GmlSy0q2Qh+BpILIaUc2JNK1loV8lCGpY4JhZfJJAgsbhiSGnE4oIg5ZxYfEosjitZshMGYulKLPY2Yq1jjqXHHEv93tpL8kqO9TlindReos3GBi8f3BW8tHsnvNYx3dJjuqW6uOjlJcfW/78Mk03SLU0uOba9dJ5GLznmPptufQ5eJ2WYcLMR7xXSS45tL3AsOrjnWABa2SukjWPg6Ia2DTLaOGaBjjjmFqQAjimJFMAxtyHllGOlnm/kWFIme4V0yrE0bFDfUsGSfQU5Rnw9nPMSu6LjWNLPObYrjWN79GhK45gPG1LOOJaVU45lBXDMh3IUle7YcUwDCXNMIAVyjCHljGO7csaxrCCOqTOOmcoxfoNjJ+Upy1V5Sl+G2R1lvXtX8E2ZVxg3CP3IMddzrNDO9LSDHBOXHNNfLhFZrkpEzveevL0iliH3iKV+ywbhNAnT/BJey0vwujzdsuSrSdjJQddBKDoecLGRdryjHebY5S8LWHiFY7zn2MKAVjgGflnAGj/AmVf7ZYGCOuKY35ACOeaRAjjmA1LOOTY982LzM6/5LwvSsCHHkK8wx9ZKCYtdMXDMTjlmO44JpECO4d7OOWanHLMdxxpeRM+xFUiYYxopkGMSKeccE1OOCcQxFmQu3thiGGWkgWypINMAZPjlzKWX+OUsBZrkXjmnc2M5J8nlnEc9qFuOz21M9uSY7KkDksfVbyoUaSgd+CnHjI8N/ExIjdzU70v6wq2kL8IyhmE7cqmVcEptTsJwLuFEYZiEIQxTMnvSZwWfZCynJN1eGM31b3pCc6lPD5f6OXmkoNjSdbD08+Ur8UVZLwAv3Zkj75WvyKkj2XhWeRSC8g702NKrUzrp9G9IGw8o/yJt7HFL7TLiFkzOdmBn7+C2RLMZv6X77Ang0WGMnPm/TObIpB3PtiaLdjmk/SfTzIm1XlXO/nIHB7ktD0CH5LaGI6WR25bofiiN3FZRpIDyRoHuA8hNyunjrgByk5InZYMhueOwbJVWPKxMYVs2iLMOKWw1Q0orLLVlCXEorbLRLgIpjcJEIAVQmCALAYWZa1UzttieH1x5JO041q4IxdZYpDQU27Y7aw/b9X8Fd2w9###4292:XlxV32DM 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12c4eNq9W0uO5DgOvUwfQH/JafRVCrAsCZjN1KKWjb776EuRlsMZWZWYTYTDz5aoLx+fGIzHD+fF/reIln/IGOz+7y8RA/9gH+Kfv+uVjGfqD1gWC55ERLjVcv/hvKtIFAQRBWllSksQXhDT3tEEYQXRGZFMS4woXRDVEPKOPAoiG2IGkg1WPLgMHSxDKjDVIMlKs53PiDuLCT5ZhCh+lhZtta3xgJoOQ/sitfoEwltfWNEQRZDSF5ZnRCdnCVL6wriGGIKUvtChlqZOjNS+0K0eRSyofaFsK801pNZYbf9hw1FesmOgKlTNtnGryMkIIgriKrJFgvCC2GaCIggriGmIx0gx28Y8uP96GY6UofNDfsR//iuTSR/bdqT9L5l0HgOj9r+U4ilPT7b/J7cqP5sh48qYxj3fUhrdiqzc0sX08s3x06FCokNlSu0/bbDtd9jadzS4tKO8Ei2+Zesth2+ZemvDt9y+ex7PYm15m/3Tm8Oj2ksjzQcXJtRGpg+jpR2tFOHSSsHOaysFi69aKZi/aWUZ8nLxb7GpDISmNoVpUxo2GR+HTZKN2kYtvHYMqZhbqBhu1Y6pNsCt3DHUnDKdFTZHsNlFloENPhfFYmsWS71ZffTK8q4F/hJS9Wlbe79N27o+tJaOIGWq67JX5N8bQtrarpa1tS3k6QE/+16SJ0yFbADI4xkvpDcEgVUi5FhzHYGVld+JBIHV2KfSQIiJZXvqi2iYWDfwbGKvTuN2l32hfFTjT4zURal0RQJBarM0a6VxgpRm5Y+8kIXgxXqfR9PDQs6LdixkjRZyXncOr7ufNrUZ64Rs39W0/O3q90+3taHPW3j9vYmj/t5EaDNA6HojWyH0OsF1n1HGiTG/RZCw5iKu0LdvXw36WZwAqaE0VJi1ighVyFnFAdOXf7EKyZcqkoMqFFQR5wrRX63ivFYhmIQq9KzCQBXHV6r4lWdEX4y1y5o/zSNdIGUPBBXu8SOPfX2JSUD0eCnU9aFMQFB9qa1DdaYyj/R4KZuw90r7Ze5PuDzb5Y/6WYp1YEvGarF5XrUGRIQ0W/LUay9ZgHhvwOAXEtlS+EVvZLsqT/erk7APwT0qEbMPFZPHRdpzFNmuSpH96qxXP8pHXZOsLn75seWPuSo5rEpDViXv3hBv9t3NEl8a5XWz5yFdN/vqcdeVHo7++1w9rV7dqlmdr7142qs/Pld/vO3LHvPTVZ+af+uAHs3TM98yuMDEyy3L+84kXuxQ9nan6usjrxPVv4knr0VXV1G+bf8mtZdefLnfqRjUuhmBB938NtaxPTghGcShN5JBHTpbHDoLi0MvfAM5dCGUfNp+jz/ffrVmfqVVYbbYA61SgVAYQqsahSG0qvMVtrIafqEwV6LjV6KzXftFPfkM/+c+I/eLuXIpnmAmHDkW6HVIP52GWFqc1hbHySlLmyJUuK1OysyBgMG2cnJJea1QqKVCIR9JbN767JN3PP/cOxomSysN9Y4C2paAu5sNuLvcxoy6tlFyaOO1YdDmeJkwwj255/AN7lmenaLWTYSwvBHtdmSwPMQmOwL8Oo9jd4i173Bkz1wiyFQDmAsEgZg/u3rwvHmwkXsVYoSf7Z2pBmDHm3eh7mTzuhsu2MKVw44Xe9fyXvOk5b3uZy1cOeRdC1NRyEbssPPS6JSiLpIWcrvOresIyQo1PaA9hJWBtpRFf6YsuVKynQR8vs7gdRAJuk+Yz3B4ZkoMbRdtVXgiCuTWQLtyL1DatnEEYdomD4PKQ1FN3yYmAlHNjJEaAqpARkY9/R0UV4H60JAZVwkBxDEPIyWOG0MQIo4ztmvF1egonCQG6jMd4sX8G6+B3nXcNlo7Ga/DVBIz1GJd56KlfwdZtfPSXRhqbgBZJ6C09X1qIH2i+bYgmUa2YPJ6dKZZJaoxNWQhjDxVKpVpr/3gaRJGAYTRfk4YuwjDV3YoVlo5dBj3HjtcKOEJlPBNXWbyPoWJZCpGO2JhkvvCDvXCDmMCdnghjGKhlVfOSLghJnyUJvLkgSbCrVqtJ02I+yCPmTHyjTLFPMxlkCSlIMOl5XUFobE0wJvEuTDFbaWFdie8gJ92ISJASTMzAiJiBdW9qJIV1orO/VbUapP2FemcxOcPSKcID6Sz7JjAB5x+i3QuvMsvFOF9HU2L+qK9p2KirLVhnrKEihHzhFg4sdALJxZmJWx8GavO4eSF6RGjw7ZSHDb7FIQUaR0Y7RYLt9XClbULv1p40GkrVHpN+USJZse05edK+TCPu5qzBldyDa5Eupvcv3IvDSpR+qtxgby4K32qSqLsUKMSpRWEYnlPnuHwDBC0PHuG1l8Q7ES62yp6X1lkxCv1NdEsu1AILsBozfFhREYkRuYBRkYYRiafyYglyGQxQkWCTArVRnMicCDT18pAMDfTLGnUWsT1OrcEBMk2nBvcwbmg3sGTmeZY2pJBYDAIk/FysaHexGSIC40RRIa4EAQBMtTX1kSAdHU30BgPa/OpN8r3YTjxm5MR9X29IOUK856+A8M0wdyLmwPVh6MMsZ2oPBRlqFS1egnvlIndnpnxBueBtBAI58FbsZWujfdkBUKnPZk7jQGQTSdT1UhTdDIzaY8E2uNuaY/sbIWeQfH9+xjRZ7qZXXWzc9XNtlU3O1bdzK18yTzqZmKhQZ9KaXIlS2wlS3z//AjgUVi7ZUxhv2psQJNeC2w6RfVwimcZCGzG3JziLUd3aXEPbNFXv8B98swND9wnuW/gPumJ++QeMNADeYN9zX3sKrj5VXDbVvnpWAU3tzIicxXc4oPglrY/F9xy9HdeCQPWvxL0i3VU/6KEge/vSGJ6JQxiZVjy2gnpQShLx58LZTocxwOJM1zPqOKGxL3D3LZb9VHFyNaKkULnZpTBCV37jJuJ+In6qNmDMpf8nytzvW1VYYjsEtUrOKzKdpAjKblZBL0SH8IUH+K8THBZSiU0r41wcbTlihBQOG2vEGY8EglFiRyPxTAIaX2ncKHaSsSF8jORPMPhGSCtffXNZwQ8A+Q3PxNAqTkJ1SOiXwDRL8JVGlelK7HoN6SY1mn4lA7rjwH0xwhXaVyVIhGDhDP1aiWit0SDOjG9JTrsiemtkA4OSVWkEp0lpSHqjZXgE1PvvPcPjpauHF8ohyoiMiEovvUtLNKxTRBkJj+wjRFkyoRMOYwgjQ7044YgzsxcJKVNzgw6dVsLmKrKeRBcBhDJhNyOqKXQASJ7b4kgIBN24jAQTJezTRt+aWZeZCSQ4oAtdy88EWDLGTkwMjM8jn583QhvXx2N8HJTxiEzZf3BwyS8Cgjv9jrvqrFZwnlDWjkvf+vYOKzHxnG/EQQpezUre92+pPbp/TcJLH+LwMpHtU+uop1apb1uN+Ww56r6+an6YbWvJlq+oK15e9aTtvqH5LO4Jp+FlcGmt06P11PSQmqxa22z8hWZNfE7yGw8VnESkdmplJ0bTYDjqyQnVub6pNKl6F+rdLxkm/W61RyTG5XO7L/JIeVbHFJfjXZXoxHPsgxOW5UMhGdRo9NitHyZqynEGv+I814eS3Fupe6FdlXnFT1R0Tqi1zBzESOnuCFIodE6EGSecAotCTLlN609QWaOtBgZyg2Zucv5N/jc6OnhodACQdjta30QBKhCZzqjG25FrYZMStJnaivtIPJRWz8DoYQAuUJPRD+tcYsw8xBaEbOR6Idcrr8cXcKxobTE5eqRXV6vepZ2bVvXtozAMwL5fg0KVm/xlNLSRvsCnWxKTQyZrAAyOTsCbjw7YYkR5Pq15BiZbjz/pg2eSZe8sQJuy3mdnX5cgx8/fuu8Lq4ZGNjV37jnz/Smc/XY9lFvepWfxd4RlfqhnHhKJn3QfDTjT0lVJ59O4impKj65xcUXBuoL2faUSWXct2RSiYdk8O2UN828SQa/kWzW05aeSfUk2bDtKUfKbN+SIyWfUpZOfdfiNWVJvKXP8HvFjm36QZQx3yDK9F3hlUQh1DdIFFNSKBO1iwdlBOFy5OFWa6j35cP7Vgxn3ELk2Aq4D69LjS2ULhWOq55r24qcvoxD4NQMwYrJ9D5lYiB3qnzN8ZAd6Z6k1lEDanxcBBZVvaBa1K96qm6zCPldj/JzxCxcjZDzIBFs61UcXnOjidnIaaZAkCklCCMJMqUEjhBBj5fSSRCUazMcaUdmGD+pUENmGC/MzOnhNIbWgiAz1cYHAT3FZ0+NHB5Os8jaVKSHT7TkefjEkycI+iNDd+tF2hV8+lQDPtW/PgyiDpTGyGHhuy99bPUcn570uP2dfyydb/1jabvzvMqik57FE8vVE+tvyIWRa7z7f0iPUcE9/VtrQ3GOF68DZs7WgNm/O+7XeFhzoR6yTjhnM2CUXzt5cfs7/+nyb/2n65LqrLV+7ca1/Y6Tl2COh0Daxe1mrGYg/fLwQa9u3fxOYkuqk0zdn4lwE+GIQHJDzkRoyOz2N3NdcBZLOszDsYiJkAxl8hL5yrHIF1JW0jHCsDT+LLvG5GWaEFaQF+hQ68v4IheVV7MlyPTTYWQX1Kv7ZI5a1X3cWxEc90JGahlDFJTnPlQYmYJBbqPsPqoiNbkjwd92fZN1D416hCRHC4qAdNBHcjYafDlPkANbNggSnXtHEPDYbiSDdmAGsSwajEwNPXegx8jU3fteWU1zxyUTJEkE4eB8Zv40E4BnKL9hq7uXr0PTwnaIs9ukIScNnMyMqTkY5jRGpuaQO5aRjp30ifETGz9DcMNswghW7DeCoFD/nPPZ4f9Klpl+EGT+SzX5A00zfNh28ISzV1L/m3kVAVKFMn8k2SsWCMv5IObn7ex/mvCPEA==###4828:XlxV32DM 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12c4eNqtW0uy3aoOncwdAH/ssytTSZUxUJXOSyPNVOb+xMdCMvY+zqeT7GPZIARmLS3hb97YD/Hxn85u+TAyxtfrm7eCXEqyXpL0rlQvKXop10uaPiher+8+ergEprj2/3d6y1aeStSD5OolRy/t9ZKnl5Z6aaGX1npppZc8eLDUAb6+LYY2kDXcvbAhZFUvRdpAGdXiaDdZlEuehiPbeom1JeulvfW81P+/L2tqf2+i/R1U+zvQsOUyBUsw3URjk1M10djk6mFgQwv10lL7WOXa/ldbbXBVsf5vlK0Xgkx1RkoD4ic0YVMZt3n9D1pzH1LJ5VWu5g9nxPb6z0D7H4uKEGq9jU6VLGFha0mJcF5LSuTzWlJiP68lJeJ5LSkBI/+u056Lz7+K03F2Og6nt8Npt4rDaS0mp7fJaekmp2WYnJbL5LRcJ6elZ05bUVc1dzq77jSM2h1O62TRaX12WtnJaWUmp9X01iqlJqeVm5xWmjmtRF28lju9dKcdtNl9VmkE2tK1H/pCrmv9u5G7ZguwxqVMpqFdKCFGXHAF6pCxj2WKyzoHYZuDENrwUuvbxKUM1PG+1bGQVonjc9lj3+sxAVOH8/rWYo76jlFnizrnfA61EvoINUQEQ+3Qle23Qg3vSJpDTV72gA0HcFG0/cqL3F3tmzls93V3+fVDZlN+qZ9fatPljtdX2PPBZPZcth7980tdQ8WJ15c6xvrza/331w9441JvodjA+ddX2KRaA7JZ6iyVQL2+FvuvH33JgKn+KvMJT8ErCO0JIUh7JQilwdKViSaRBmEKS3umDiPb5mttDyb11e+BX3CPrfeknd0j8R5Z7nG1h4X1YFWxlGjAO+qapUajDhNwoI3FkrHAoi7P6Nqa0CSCML89gOXXV0CV+vThebvH78c98Otr+aeEpL7DR98tJABGYHJSG+zcgcPF4nuIHbH06JsaiQYZbdJjM7X5hxXTpkASe20UgLnFeWUWVSxLtXjaXZsbq9ozklpqfIxviy8x58tc2dic58Mq0faytRaYpcydax5kjb7t3Wur23gDsbDx5jLesG/kJShvR3kJyoCtJO9Hn1ygQNWiPLWUAQMTanOiWJBEsbi2BDOzyGLx7RlJna/96K31Y6ml9lOnEXzzbMClHytaKDKzlH5sC1/amKVMYJ2mTbXXDtbugi8GRK/sa6n4BrsKbDH5Z9lr8se6hratQ7xcPHadIIAxys4YdWMsfKc9U9GkcXu94Z+9Fc4o/SNG6ZBR3tJIMdNIOdHIxiw5jdQTjWxk03dOOHFHf+KMZmaB77miEnLmijtyRUof7+ki7Dfyni4CWO8HSnkXZrr4yXR2Gnk1nRcUcJuIyaCAAsjXgdyFwhIKyMmdf0Tu3CViwxukZnKEwZAyIXPRyJ21mmhonDnnTCTUTCTkzsgMzE14RzATEkwv3BuCqWaCqWduZWYP7Ux15E3glvWedilpcRVZeHcm2nXiVp8xMDm7NWcYaufLq21at2RM/jUZOwhSZSrQGWNFcMVTG2ExPXYFwcovSotgnUryFOFSTqpIHiKURYWomAUpi5VyYZbCDcIySAf2M6hGpyxoGUQFsmRJWxvkq79F1QK/GpmD/a65vXXOVUzFuS91lRNE76u+Ijr8YkSlTSI+DhPUHx8kAv525HFGPLxnnQvsHIkGjEqweyTeQ4iFX1kckVL2zbT1LbvrgH+MD9WNjpGAg/V0C5IAYHeBWQi7Ioxt44zMGGLpLsSy0BaxEOcIHzLRGmohlILw8mIhNERkwVojZMNwCyEba2IWQjZkJxt+rIhKNsyeSgxkgFdXxkE2ViQb6Z5sUObw7SSM5VkY05MwluQsjKVJGCsiGyEm9oqgbI8Iyj5LXiULbhzlCTERSEyeiFpFGuhE5BCxunh1q1hlZCET9YhDpip5+PpGhVoFCjomqHsVSqRZhboAVzGrUHlWofZZhQoMIyCfnFCMUJBlCDp2C4yCXIoHcntERcKsM61nZmTvaYAsP49Yrhc60xPsV+jpE0XJnt0zZ/eI5FIWHrpnGPZfMsgTF7j0KV3rLSnqWQyxw5HR+/5IDGFJmKXJtE5rJBbMIHXPIOE9GWmi7hlkkwcAw0b+Zqg8ABZBLUyqSMwRxCIA1MwsCKOQtLN+mDiiWD/IHSBEjrjd1J+G3Dr5nTzERtyFB+48kosO2ugizfcjjSKBanBesWEhQA/to/eD9KZvOU2rWU/gm8JhMivNzaGjnVoGLNucI7MgLNu8SWZBWLZ598yCsAwwRvuhsDx0iuo3wWVI8CK1DPR1widqIYid18xaQ1zuSDosFyJAtxy4/Csoq9Yj11diwO+G8Jsv4fezIlRH0ZvMn+M2FwEqIvOi0/KnRSf/qOi0FXTP6kI1mBDZPkHkZ7Wl61rS/pqkgvh6UlYKKBVMtSQiBsjVzgA48l83cnBAU4ranxaK9tcbaYDDPYfozGsuct3uC0Xg4eAVMJX3haLlTwtF/lGhaOM1F2supI3UnbaQUx25ZxyqgvzNmktV+O6lAowLvNAPOIJ7whE+KTXBXC1zyi3GXK047uze1IHmuXpYGvJcTZFVxTY3GoVIOA3eOMZTeKv7pGiRQZNUus76ZSrdLCOVVmHHVBpCRigBybKqZYD4AP5mGWShZ3MaLSWFLWMnQN+XS31aSC4SrCtpl1ZiegCPh6hQMaSPOraT9LF4zPoyT8gPrGqWwQxM2Db0omexPWytXtSW1mEnQNsBCz2pQgvs3qy21R8auC1XzywD66UQxEUqRvTNcjw0Mnq1BzquwV4WyQY8eJyJMTELlUO4ZVR0iM6y2lPavlPLIAFWasssSAKGOtAMmJuTrL1ZkJ/A345YToxL0uCQOsnQZ6plcLFNKVJx6AuzVRxU14blhx0cJBwcxAvCQT47pUFOSqgLxRlL4Sn9dSX8h1P7wadLX+y1AB7oiY0UEGGjMNRCNLfmMbZHCn8mYvJQH8J9B9JaWwWZU/R2jJ78o+gZa9Wb6G3rvwxf7YyHzx/5SLVdhq9ZRvh6ILA9Gr5N0q5o+PrLFD/0B9GfIoZPMQJ8qEB3DHWipQ5p6cFFR43KVzmRkkE7k8HPTg8lIsvYlKcUWQLwHbKMH0dWJBJ7lSf6pF+3oofkoJuyeFPVWb0ZJQzzpqrjbsnH6UTOPjOOAfGR1JAEh3gxVxM+O/WRr1SIH1r7YyMtwSY7n887Vqp3hrkiLcxChPlEn2GQa4fMmnYG7ulIKOuvBuGwlJpJoEmc0tAhzqadEgqtraMjGju2VttxzKJaqqJeGiZgqJ3aSJcEW7UTC7MgHm+qDaBi+mFtcnDaliYHw+oJ43VMx+to9wdysHz9sxT1/pzk9ucysH9d7AFH5vlvNeBSpL5LNtP9wcUwbz3xPsMMqTKvGzU4DzHYLeGNGJxf/y7T/PRIos0hvdkqHQQOT7EZtlXyncvO7ug5h1R818w12ne7pksIrl6nN7vmMwHaX6qp8KbJSQsYqnPaESrctrGM8h+rzfJ06LLS4bukUozQ6OXd4cLtFsHUSPHZycK289ykjzL77Vn6mD5LHwfbTyz96g4UilJ+seNzeet5RXnRaJUub4EYRoYQd/rAIPsxWnods4MYaTtEVEybQqfkqViLmWQZChO6FzpIktUCqLFnSGk1B01GT+Au7pF4QA+N5W2nlpF49verdFN+URiMB8PurWG2hQlaN2DqFqNiBszc4nGKrMUM06Zk4rhOk6a2S+rqVepoWvwjaBpNZrdIvAVhNenIblF4C9GpQ8LxJ8YQ+muvcQbg8R5x5CubMhSeW+O6Giw9M9Yeq7itQiXEEogFOzOWEbevz4zxAq149OVCJPtZ/1zhVJ09wbGbBWA/U/Q7hD6fILNPPkRox8X4CTI5f4ggLvH6Njk74Xc+i8XHibHPxOL47hsEln4M6TiHOMOlGpA1jk7BHnDA5T6h9zqXcmfJVbgzXM5n2kex2aU44DIzfsH7To8+ZgjXJ6CyD29qxyu8BocAG9a5dnyCbDHry3JOhx6guEqLfFM71hvmX9a++0bBPfpGYeY6auY6Hf7fYLwWNYM319KC1NLdaQufC+UqhfimWq0SfiBgsp6r1Twf5IfX5JPDayq9+3yAZqBsFm18U9nWRv5mZVuLnmF9qbEuLOJL7aSWfKnyUu38gH+LYFFYy6+uzZaHWyVYi+M0UV18BBDBopgFwVUlH4mFtdlOZB/nnZo/TPg65J42lCH3QHfHEf3SEi3Cg8mSMRBuAhZNLYObqLw6ahncRMUcmWUcxstHnbZbxvcDWfDWMOen+B0Rv9nZ7L7Zqn5Px+/YitNhR9PO6IUW5pCly2ZF83hxHBprFpK9b6gxN8vI3jdvmQXZhd5QTW8WFOfh751YKO8CF9jaGLUAsOzUQmmc39h6ItTPB2ZBtkY5VkSOxU7LU44VkWOxY/Obcp0BweAO60F0ytPSFb11RaKzCyQ66VIv/JSXPCtfL+8OkL37VvJCR7BPvpUkh9w53XlGUW4lhoOqfFLEZpSFkJHq0C0Ym/jHYPysJLx8dqYLXvr3uLw9w2X76Gi3e/TtoJxhyJxx2b/FZf03uBzdW1y2j3BZ5du8Xl98Qbnffp2g0mm+vHmLwL99towirOcIC+hMbR2dvTnQuceq7m7RIVrCDf17rRQzsRNsUdloZhl4lI7iaLcQDDOOWYYwTLAyOoqVFF+jO+ErtuYNA2WG5J4XyI8BtWAR+IcXSSCOSh6LfOIcgXEOylMC4yl9+xgWRA+wSGZBxKEoFRhKUWQLDNmgNY1wqDgcbutGTARDAXcXZiG4a+z/Aa6XqPM=###4292:XlxV32DM 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12f0eNq1W0mS5DgO/Ew/gLvIDKuvlJnExawvk4c6ltXfB9wBUVJG9vRcqrPlEgWBJOBwItjrc+PbB/t4/b3JHf77l0zGfige4gsuKY0uRZ4vaYYvsXKJ4wdTuSTwpVAuyfyaT1vGfP1tdUC3JAm3WPgTXdL50obHjqlcwmMnMOrTHqKOeagJCZbttQf+hBTLJYMvhXJpw5d8uUSMgTcfKpgDruVb2W9AdMw2qdd/4CbzwW08Xvlq+jDqEK+/FDz2YUU4uVYwf3atYOnsWsHi2bWChbNrBTuQa2X0Kf/xByy12UpNLE2mW+qY6ZYaLrulUp5tEHqxQZjFBsGHDeMSTCcxR2WXG2yOYGI4Lqhujt6PYY47e0kuC1CItFoYVwvDYqFk2MJfsDLyFInfP8okw+Ovn/mfP790KgthIjwjvCAuEYRlhNXRYkfgy+ErXj9hbQLSJqYg8Fc2ACDAy0MBQWAuIJuoDxmCwItg+2TER0cQMA52URktKYKIPBqvz+zIuGbCUb91N9juYsJhKyIJkoc7toIkQZBswmEAEYwRLxSzD10+qGyk7rlqAsSharckTpXZqRIQw6brMpKduhXPwU43GJE7IPDPnz+HEGXlibz4BP+dF1z6cC74V1uGu+nr7WB3sbAGvha3aABsoY03CEemKM+LrsTGzy3s9e7g8d0u3x1JvC1bLeJgFfdyCQeraMslHKziVi65EhS2Mj0o7ioS6kQOdcTuGndLdF5CMhsh+RyHW2j2FbK+vnPEZbkGYdUgvYbsm/i8BOUc/JTQxZ8QZBx7iM6Oq/eic7qb7B5sLyZbcLZEmBytUQzUurjSUPOOZp6QXnTz5DbWJIS3k3nwFeewyNewyNfAzeUSFrmoFsZh4bY6MEwLebdwgxjbozRbLHSrhWa1cF8ttKuF22V6a7uaprcYm6Vmi91QEfZhKMfr82jLqe4NxX15xVhMOWWVZb7dZFALu2RdTSWDEmeIdbrEdMaSusTwwJJR+SmjmnA2D2dU2I4X5rnFvPvF3pLtTWZdzPOndJpmOg04kTTDO4Kzj/KpJbMyv3kuXj/Lv/kxJhEGEwhPWV+Dv8KvysEf4k1NGA4jMwvjbFbMG5kJDGcEGXmuLYiCwF80c6cNQShz45xekJGFwQRGkJHTdQqCICOnq5gO7ITN59GKE2SJmfL3jxJm8jM/ynaudCVu5R5/kHvEuCeTnVjSfA1Sot2TY8OrvawShBoiKt7pCyS0PHzLtH32YEsBlESdIvKtZYrUVqfIY6RMUaNdnk7RoBUq6OEfiPg3hKwgg5DBexRGCHewGBncIS9H/B5KUiaFKi8aJAXTl4IMHinknoj72XB/NjMWxiSDwveAhe2eYnDUdRyN7wFb2z3F9JCXwy6r5fCIG2+RmQ9Jv+c3qA/+oSYbCoMNbYgNzTTuYg2XOyNRco5GgqTtUQjiTY/DUCj2IKTfib+/1MHayigvIcHA7QpBeWX+BNNqlCDIjBLN0jFcWZ3wXdkncc9hgkvIJ1xOp8TuFKcIRez07Utitq3EzBFixh8K4sqn7tgXpW+0IJaPROyNOvfTifqJTgQ63yoWL8prDsPTtk0OkwiH+ZKdUCqiQpDLwhpUBJzjJxWxhIrQUbeVUbhLRgHh2D0UzB52T3/hLh4K5oukKdZyVK0Fs36dzDnOjkbp3Ws1zUkkvX+v7m1rX9P3yE6k5Ny/g5JClPkGj/qldt/ia34V2cb13R0pOxJWHt7fGSjbG1YiXA++J5/sHlKD9qEaguvWAyGYbgTPB+Jw0ob/3xGCM33iG7Js5t8ZeAow4044InnJyOXhOAgwS/rdD9YCmwCn2OAVeWaQCSN8S/9lh5b0X55G6T9JiYZFOV8dvOe5/HDJ+ZC4eXlmQwhKVHsbrCaYNmJJMHBnXk3g6o9jxtI0YqnGsfSmJuVrTSpfDwFyiYpsRMWcvLZvhkCo8g7DBVsz2ygmSxBokU7N1CaWWiiu9J+ttZCnwS/u2/puM6Osm8HvoLHoqjRtAWiRCOtE3YWYtNnxloN9K8ScaoEk2vIqPkUrPaaAgcn9okoYQHSxzkpH6lKFCS4QM2OtakLcqzsrQiU3uIAfwtEh6Y0MNyJKVBaNRth5cehExvbcZd23Jb50tO4WK7LneIRKDslTmS01QuYxITvp8ctKaqo90eObai9Wib6uiC3YJke5K1nKr7LUvspS22A/C+Wxg/JgXeu09Zf9zpf9Xjc1JUTyiRBdsKAlFEh0bLCcFaShRZ2iRpep7EmmgulMcdV4RtTgio2qHPYNlqDoaUBcTwP8ehqQ1tOAcL3VrThWNqWbWYH7KZdMYSx+nebzyCncS0acyylDOP4gGR2rZLSvYXK7l9/sEoWy5oR8APFBPwV0O6krN2tAX8xbp4gHEsXhheqBUW52HsGk9MAoxcoo9ROjpJqjtvcqUa5Ix/TsblWJbqUhdjsR8uIsKFLlyiZ/ngjB5h6RU1o8YChWS8+NpfZtocYLiGK25hcomn3XJLTFYo6QkWMEH8N0vlb2BiJsOpqIEayxRI1Hm0KTcpbjZ44c5fNnZmvLkxu1cB6RAHsgyMhaQnpDkElp66R2hChoNZ10Q5oGE2y1sWenbFl2X4ZcecqFAQWsIyg7zmkKMlUI2M4EmdQQRqPIYKCAJIIMCiojmxbE+knVTpj3wok77y44km/gsyRGpuSjtAgEGTKRYZEiQ6NRuyLvmboO2O6I7RmJrtruEUJsj9UO1zkLhCDEZuBtDCOTAMH32srnK5K1ohJPcJ2ghR1PK0JEdpkIgo7++lYp42L+BNCBHsIsaZca0Zc2Zqcv+Qu4P9EXPuhLIvTl3VO1dnT2flsBpkTAaDbKaL48VfNvnaq5lclsa6Ui3mIufDlIu6IrVHY7naKF16nhoR+s6bW+MedTs6/5TG544LEMdnekxvVoeNg2+Y+O1Dj7ZpcD5kgoq4ClamVek4joWTM5QYjIlwdVx1sHVW4lINs57+nFwskHuJIX3LDwAVo+qtc7FEEuJzUnQmjvddvA0ySEiei27xBC9XAuxZW4IoTrudRF3by2yIiwfrh/vUFJTiIYLB75REn09j1Kkr1wMaCeXpif7t/iOLCUW6oothZeATm6BG63TcJiB/mQnXxAfhp4UjM/yZ6fbK+py/NIGacsyWKWRNiEbGyiafDWSfQ+TJMwm1CEjmE2oUiniHWMIPMYyDpDkFnwWxsIMqgTkKo43KgwAxHyoAjK79wjpPqvzELzH+YmNItjbqJPuXsnyMjdhJtokrt3xQky9EqY4YQQMsPpTGktpbSbGN+m6WmVPwgymBD4IyCE+CPN86m+VAnR9L0nqToZH2oFguAjsT0RZNJJ34/aqono5C4GgxF02ic7U2+fNeiikIYinS6WKqocEO352GyfLEd0ljP1MdJD9FXz5IVYc8FyrtqIwn0b0b7qNe5Jr3kiPAadVs1Tqn/AduRTJ+dtm9AFwTmeCM67rMawEofuVBovh/Kpg3tQadJbKs3KZq56hQ6SkARz+72skmCSexL1T6rKvqoq7klVeeI35k5E3h9IjdtHl8xmj/+Z1Oin1tOT7uGedI9j6nAqfY+F+CcW8m3q8atZWot5R4r5mZIKhBIpxESDkZlIZ7SsCNZCDvLMTKRET3An5XwnyOziibsfWvdOqsUZSAuEst4MvhWZmRLWf29sySuftJVI48hwI1XORNOQkSpnWmvISJWw9XsBzE6Np0KMDqNsA1JBeFIRIyhtcSMwMtOWTiEQZKQtw3p13pDBQVpcmsjgILBJLTIbJTSdutpSEdzy0vtxGoLaZPxOkJH14RlHkJ71S8tdeZHIpf7skohyJEH+Vql/Kt5v8uH7vbS2HWLgZPhwYvH9Jo2WmoR86qLlT120/++WDrn+9uFdKWDtrX19Ou5o14feywnejQqQqdvIl0a9pQKc6vqbFPr9HlshisKorw86Njb7GYL8zkEH6guF7esfTjzc7ExRSqy5+eGY4583r0Bm5A/tsMn/C+2wMZmHdtidjd5gpdNDO6x8aof9t7towGi1luFsGs1mu9JYuMD+buZKrC3LwtEznxrb9Y364dJoTN54oGfqX+ka8UnQyX2ZLRGVzYprodo4K3NbJmyOXMP/KOsFn3mkMHIsLdkB2TEymQZ8auypAj4aMQ145ujNKK1k7/cMztF20XwacY6k0RurRA0hqWYniR66aB3uX1kajOpn0i7iuorr4ObUCpAO7Ceoj5ufZrk8k3p5nJTtPak3ZJbtcfwOpyKDi8AGlxhBwkFMBEEUitnpdY8pAvx/QMipM9f3ztzsEdyZK11EUG2lFKWR9Tg4tmEeW8BwltgwRRTWxZqGzCpeqB0jiEKJfihUZw4dWcFwAj80GVknI+NFg13B8md4IyCmpPuCrQgu/QdprshgSpNiNgTpI12waMjQR1q27EjVR+qaKkt1l6adpgCT7su/Uixenlx0BjUolvhaZwjp9cZvlBYyFd9RFBYZwbzT9nGnHVQ6RLUD/RZD4itDEq8bGaGrADfk6OFwZNEOfNUO5JN2YPh72kF4vfHjooXt+JNKcHU6M1SCkCYtY2+pBIs0YN5puCBdFqwUf3d6gDfswj0XesDFDz3NW5xArpxAnZ1m7qWBFOKV0xZlQPKn84mHQ4nFOkJgc4pTvQQ8yM8sm2cnMkVtLgRCcFqEh0YENfQ3K/CmA0Gk/dUbgsy6WvTgWm1AigQ3BiOTJ8COIs9gnhApgtnBKJGHLN1LZEkQVCLzgBCS/7iT+IPwj0ycJ586Ei24ZyPISPXgnulTeVs9S/rTVaMQQmUHTr4VJTkkLgwVO9bfG+2BeOFSdhgqdv31D3fE7JoY/wu4eoee###4916:XlxV32DM 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db4eNrtWs3O3KgSfZk8AL8F/qy8SiTbgJTNzSLL0bz75bcK3K6WRrOZlrJIuj6fdkGBgdPH56ez4kt8fdMJ/JdRAvb9l45XzNf2v08b45Ejm/+Jv/J3bPwyMpr9f/nr8CU3J/ZyNX2BE2b/ZoxMX16F/ect67mXS7IkzZ9qhq4K6QKVhhM2XL5t1oZPbBiO0bCWCRtOOZU+puzSlOzG9obnPkl5qzTE10oDNQgPlWrxkhWwUrx07PeipeeKdveilRDUh/hQtPb3otWGReMlt997qs77TJt7/Uooavt6qn+7Z80jcq8/Pw73+vNEPdT/W4O4cqT++l57k+/Zf/jTZaSPTEPcV+n2/mOTW71JhQnKQ1Fu0g2JSzpZEGgNnfM9xhbEFEQdpSE9ECv2cbco37HtbsybH5raTRd966bEvLJ30yVZoTDfVIrOUDjaXWbqZ4P8qVp3ALsjR3dqo6I02orRYumOLIhrHQ1Td2qZLtrW5IHIMXoj200qzTeV8XThaunmm1rdVrV01FAYdQfXKrBYQcABPXoF+b/a5LUkLhVY2ZBzStw6o4/WmW1Gam2m1HboNtA5hca2dAVSB+KGw1gB0wYwD7rH6c7A36fxvoy/knlRKvlXWQz5sZdl9bUlcumxFk65/8oj2Haauh7vO899C8Ql8NOFrS6F/Dz0v6/2Gfv9Efpnzx99/6z3/fSqLSXf2/Omfc/3drwN7RPafd7J/tlx19rzvn8erb95HfVP0z97/hP6Z2/nbHm3uhT302y2dEyKZTfRYzdRR958vrkybfmR69uKugJuK+GfDyF2/VLLrvLTHCaOYFzpuXIgR6BGoEdg2saYazkeajmolqPXEvBMUgGwlvTfquV8rcUIqmVrteQHiWrBeTHyv1VLyZzWUjyV4nspeSMdpURcrUb/61L+bQW/zRX6flrXS05bNs1ypuVtx0zIvD2bTcIElX3qR9vFMiIXBLdns41zoCO4v2ZkWxDckzNiZ4T214yoGaE9ORd0IXK2gvJWUu9RZaeAfk8Zuf17XVkYnhReNWmL6sV+oOcsx5olUZZEWdLIkvuLWdI44nOWuGQpR1LP0sOTwqsdWT0LkQCzabVmkZRFUhaJWSRlQSKSs8CaRVEWRVkUZlGUBdlRzrKOSzn4RhZNWTRm0ZRF7/XY+/v3pumZu9rk5f28TbhG5JgZQUZgRohgZOSYEaIrGUkLgnQlP8BmQZBXZWRbkPLQx75S7ITMtCo/jecEtadRtedImOk5bZTRtC4INyOVGI41dM5IfRJsH564IGV2oXdbL0jpgWvrTi7t1FlwqhUEE9LJYF14IFL9iULTbGiaDU2zock1JW2dqVBLHvfmrazfOqITo6tGP8p/jQFdDwxISWRA5g8DemJAIN8yIG0/iAGBesuAtPkgBgT6LQPS+oMYEJh3DCg/bR/EgPJ6WRnQjHAMCCTHgCryyIAq8siAQHIMCCTHgEByDCg/aAwDyvcMrpNXFoaaQjMYUI44BtSyJMqSKEsaWRoDalkeGVDN0hhOzdJDTaEZDKhmeWZALYukLJKySMwiKcsjA2pZFGVRlEVhFkVZHhlQy6Ipi6YsGrNoyvLEgDLCMKCck2FABXlmQAV5ZkAVeWRAFXlkQBWZGdA5IRwDyhDDgPLIMAyoIM8MqCDPDKgijwyoIo8MqCIzA5rX0I0BnYPFtGk2NM2GptnQ5D4yoLLXNLZThqVHGiNzZ0DbEwMSyIDsHwb0qAGF9wxIfJIGFN9rQOmTNKD0XgOKn8SAxFsNKHyUBhRuDMhNCKsBBVYDCqwGFFgNKLAaUGA1oMBqQInVgAKpPZHCRAxIIAMSvAYUSO2JFCZiQAIZkOA1oEBqT6QwEQMSyIAErwEFUnsihYkYkEAGJHgNKJDaEylMxIAEMiDBa0CB1J5IYSIGJJABCZYBCVYDiqwGFFkNKLIaUGQ1oMhqQPHGgPyEsBpQZDWgxGpAidWAEqsBJVYDSqwGlG4MaJuQGwMKqOMEUnsihYkYkOA1oIB6T8QoIQMSNwYk65FxfcGXTJ0BbVtSyIDwqDvFxIDmV9Ayiv2+vQ4oxPsbYpl36bHp4qXywn5lRwjVN95xaa6+iK+cCS9Vq0GlT3ipvohfmBRC5ZW5XzqVC77zKPx2eaPdKBV+2+6DXeElvb8QrV9+iw+EC/0Rch/cC7PEfdAwvHTtg5HhpXMf5AwvhX3wNLyU+32CrNMCjMvDnds4Pe0VF5fHYjIQkZvh4fJYPBDiPsNKpH22Q4CsZ6tjLBku71i9W2bijeLFA/Jqh+gujcW4cb4aN/x+JwAIuaWnxif1MoAJRk+lRfphFPVUv7g0DDuASr6aKOBlAJW9dUu9+ElkGvQoKEH8juwkdn5Cz/5ENt5m5KWxYHmfmsktIq3Egje5uEWWqdHy1amSXp0q4dVT8vo8qfgyHMWMss6SeLXXWOq0wJ5eOZVoy9LVo6rkCW1by/uV7+SNfqmW8Zj8KhnRC4InrI7ST0jd27/XnuUG66ngBk8rs1eYa4NL+9VqAXHG3YXbe9ulB1ImK0NbpJ0fb/Jn39tzc/j+pDRSakO+RqdQrYGMNcbDOSNkn8mzvSATV6L3Gg0h/uN1R+qCn4/8/CtwQfDIz3+nCVmO/AOP1bIql+N7mhS1HN9WbQuCxzeIGBaEju/hGhkIHt95iudsyxSnWpYyo/NWLLS6/YhHZKLiXi/3TPTda7UgSPn7/kkI/kzoG/5Alt8WXsZ5zCei55WakYnoeSWXeSKi57VfkEH0qqyin6w1EUmF+yOrPMoq9r21Bj5JVoH3sor9JFnFvZdVzCdZa/xbWUV/lKxiV1nlkBPCyiqWlVUsK6tYVlaxrKxiWVnFsrKKY2UVS1oKUOgo9Git8bysYklLAQodhR6tNZ6XVSxpKUCho9CjtcbzsoolLQUodBR6tNZ4XlaxpKUAhY5Cj9Yaz8sqlrQUoNBR6NFa41lrjWdlFWBlFWBlFWBlFWBlFWBlFbjJKmpCWFkFWFnFsbKKY2UVx8oqjpVVHCuruJusMt9zk1USSiOWtBSg0FHoeVnFopgCGDmM/E1W2dTTiyWNDMj/YUCP1pr35mKdPsla895crOMnWWvem4t1+KQXS2/Nxfr6AAZE79dv5uJNTAhrrWHNxcCai4E1FwNrLgbWXAx3czFlY83FQOZiIHMxkLkY0FwMvLkYyFwMZC4GMhcDmouBNxcDmYuBzMVA5mJAczHw5mIgczGQuRjIXAxoLgbeXAxkLgYyFwOZiwHNxcCbi4HMxUDmYiBzMaC5GFhzMbDmYmDNxcCai4E1FwNrLgbWXAw3c/EmJ+TGgPwEcdYa1lwMrLkYWHMxsOZiYM3FcDMXb2pCOHMxkLkYyFwMZC4G3lwMaC4GNBcDmovhxVycnhgQvVja/jCgRwb0XgPSxycxoPcakN4+iQG914C0/yQG9FYD0u6jGNBNA/JhQlgGxGpAwGpAwGpAwGpAwGpAYFkGxGpAQBoQkAYEpAEBakA5+j/rYXNw###4980:XlxV32DM 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11b4eNrtW0uSJacO3YwXwP9TN7wVRyQJRPTk9cBDh/f+QIAQSebtrvbEFeFJXQqlQAhS50AK4z4UT/n1+uaM+2Af5dfy8vubzKaKMq8iK6rouwuiPRJU/9X00VAfDYZWQcPB0qoEVdDXd899/Q0qulpRn2N/lSd1qlap1/+KkvngnrlXrc0fRgXx+k2VZj6ciK9vVh6zbcFZadsqDcZZzfovGY9g1SKrBa1KUCVpVRnKd5nOXFv4u5inqmlmNS8O81zUwzx9hGGeZMMWNO94DbOwyr+uFvKwWcjdZiE3Fwt1tVAvFmYzLYzDQsMtWiiv5giO5lxtEBJtoB0bLsO1Y8FY71g4ia6RLGLH7jpN2Ivd/CF2f4ijDT6hDVVBrTaIMXh7pGGDFXN6/LUjyfaO8t2g/ywd1irx1+/QdRW8/igvRxH1iSgiKHWR0kVU3gaLWuGjOKAqKZAkRSWaVUnTsXXVSZTwV+uzlsozBqwRx/KMwGdEfcY2iwPpofru9Ud5+1rnYVhcljmYZVM3WA5JeT+hufoHdI5FIqtE1vGfmRFJG7/l1QadD047guaSa9Zx4jRorsScNra8SOqILC8Swdy5SKo/jGvGra1Vb+oIk6McsaAbFw8wLrjFuDqi5JuSXcbK61g56Pi8SFiVsGo2s5FKwKewCATji448ikQ2C7JdLKj9JAs6LC6S2k+qU3/08ZRZdjjpZRr+DpHVqeOuBC1+/FXfhPzhfT5e/f2IarwIgb2+lwlqLyONV7wEjcv7ydNjgOCRvis2tgbd8kgDEx1plUDowSr5uqJQAyi7tMWg6mzdwFooAOVt/02t/mAdqCRVPV8Dwy6opPvT7zGszCFi2AJ+SugD8MwI5q8RiSeMSE5gRJK12PHsvAIGMxtgsGNOAA2B5XXYO1SzQ4z/dRlSAL0N9izeBvsI8cA8gAw7GaJ0GQsFmWVUHUmWsK/2sK/3aMw3GBRigcHIwo6Crhuo8zBPJIbmabqKQp//RncUP8EDOK/VA+LKUwjSsIBdKM8XpFl4ioivzSn59URZbnBJ3njiXD2RbyBRT0Nx1cm66lh7XSzLfcb761veatchT5ymxaDq4+qQ1x/w9+8/E1grm6Si4O+189pGibu+BrA8MLEKaptFcNQ4GQ0bAtFiYXlTa5PAC0f9BMooD1I/YTIaSesRGqMxtB7hMOpI6yvchAodMsIL1QWAD2BzcRD4gHWMgBLFtizRYNkNBqBMEFJG/USigoWZChC8DGeGChDvdD4ZFSBEFptJU9TmDIYdc9rKQq9aZ/UAk2Q6y0Kvc5UA7pgiGi4Ugasa/DQBR+8ppnFxeiqZOMhFHNSkSSp9qb4jKFq0D+JVwjJ6FB3tNtJSkAWAr0mAdQzFBnwavFHWWfnTgc9xLgbwBWShgRPgAzc9bR7G64cx8ZuNvuNc14sthBTi1H9N/+3tJ9d/fQsxosVW1/tziuLlAMnrpgx3YlfguwDddYc2IG3gGG7AvnkB/YTo6rrnbIkXcgQ24VMhDjbFj7raRxA9J5+Pn/cgWn6KBWW+qUOlURg1va1S4KMgRkGOguqRz+WboRxzKL4PJR44lGhwKPnfNBTP9qEoNofi2lDq/gKHgrOi+L9qKPWZvI7EzZHYPpIgJkhLHIn8xyP5pwMoGxsM5eVdKa3WUOQXLCn1FBMSV1NAtkiJZVqP4S6xQOsxQCZmaT0G14QhvNbPcJwYI/Vzg1FGMBoq6wpG0FA4iRocTFOofioAUl6iXirPjhKH5qAAVQOthV/0M+pn1M9dv1g49PNA9QRBCPXL4Lo+lEC/lTgMv+tP9E+we5z6HPU56vOhz1EfWUKSetEXqC9QXwx9gfrIJpJcxl8RqetL1JdDX6I+sg4vx0IpApiXEpZhIvmYyNwnMp5Qr0j93K+nQU+gfu4SE4u0HveViQtaj9vxxC2tx51w1GnW081zWVlmStrKEm2pi7niGr9T0DPTpJ7QpQH4UD/pUmInrUe2lDin9UiWEqftT67UyUGrp2czZftfx6ZxDhXOocI5VDh1atCozpa6XiVKzQVQqG9ZK3AoNCJVYiGA+kZRNFKU9B9FuaEo/nhLUbL/OhTFh7cUJbsvRFHOtxQl2y9EUeI7ipLNF6Io5V2hFAW3waX+nqIUwS1FgfobigL1NxQF6m8oSq2/oyi1/p6inPcUpSgMOhKwdGIpDooSHyhK08+on1E/d/1GUeIDRQH9xkIClk4sxUFR4gNFafoc9Tnq86HPUf+GojR9gfoC9cXQF6h/Q1GavkR9ifpy6EvUv6Mo8Z6ilNZuKYoP9xTFh3uK4sM9RfHhnqJA/aQohtQ/UJQiuaco5wNFOR8oyvlAUc4HinI+UJRzoSjGzfoLRdGdarQ5VDiHCudQ4dTdUZQaFRohCaNwjkK8UBR9R1EUUpT8H0W5oyjmPUVRX4ii2PcURX4hiuLeUxTxhSiKf0tR+FeiKGalKHLWP1AU80BRzANFMQ8UxTxQFPNAUcwTRXEPFMUgHbFYcljyg6L4J4pikI5YLDks+UFR/BNFMUhHLJYclvygKP6JohikIxZLDkt+UBT/RFEM0hGLJYclPyiKf6IoBumIxZLDkh8UxT9RFP9AUewDRbEPFMU+UBT7QFHsA0WxK0Uh/T5RFPtAUdwDRXEPFMU9UBT3QFHcA0VxK0Uh9ReKcg6qYZCOWCw5LPlHimIGIbGj4EbBLxQlAfjqD170ML8hDIJysiW/IQtKGDbgxw/36eTbB+SUeoC1M6pW1OtQxz/zAbkMNfbJqV2RD3LzuxsI5ne3+eW1CtYvryNnBSTwEa+MtH4TbOMYjYWxlKrX1O61E73GF69FR2naG6+FuHttfGw2aXoNsUikT3mNjCc0eOuwUdypieDWnVVw684iuLiTqHR3Rle9phyvIyzvQ02mmI6LmE7jb9Np1gSZLc8Q0mkm+000oSRBJhwQXawyryu3xfQT/TNpNCSZc82/2dJo0hs+fMmCuc2ZOV9XlkwzbYJOrqrJ+3QVYULAdMXp2ZausqSpnHvmZl7SIEpHcu8ozo6QvdojL5mbawKm/WECpkvnm9wYrszMjYl7bsyWEGN+KiFG7mkg6mKW0FteEGbEREEiWv5MSgwMOLxJheGTTN+mwlzzX3pGy13+S8uWWYgpzZpZJ+F4k/XClfpk1os6BojD/BKMLQurBwtYYguOeyeJiKYSeqcXCZKF/kI0iV7TJhNpTlMKbFg2iwRJsEycod39IOR38E7LZFHOHUROMmOUwyTNJkF+VaYxLBJkjsqZRTLzdUo/atFBtqi8RZ2yRCFtCAyEvCFwlaKeJ0mcWixzQnJnWIqLBJmMOmRaJDN7BskPSBZPZfC+SdROgjANE4bkPoemKU30KcMy2N2x5EIVX1nqK8yGAviB9Ixi+QfPE34Sws9B4Oc+pPDEriGFJ/naQCpuIFUTOzcu0I5qsCHISkw0eTRBznoyV/xqZzkXlFuA79yBz7+uhzwr8C1DaMmiKzzKHR7Zr8MjXoPQewrpAoNxg0Fy58GlvF8qUDNYnTeIARh4ixj9FgPfrkOsiBl2xIxXxDB7JqlGxOATMcRn2BxE57Rf8ohzwOEOMdh2yePYkif7/Qh2geerO+x+sWJ3R72RQd3h7bEZTXJeDfrDuDXndc34NHvGJ9/TYPWO+uIXUL8AQ95xkOGFCIdGy8CWSxmrOcdujp9YTNOPWU77LZB5A8NhZrCVab2BwfYk2KXDtIH/BfHjPlLyEs19Wvi5PNc2kppzWEvL1Q5vT4zqBiErTsgCkJGgmvs9jNoIvYfRZkb0Z+g9jAU0zAIazualYYYNIwZ3LjCf4fjMxFwXBubWVU1QsPzviWTZ01MANCsAugn7ibKZIhGLBBmQxOM8kCDcxpFiy1KiJs7DjjIYSSWTiil3LjqEKrjTLRKkCqodaE4JUoWFRGRKqgqJyIsEiZjEkxKQLKPKjSpQH5KtJaGE8HwjBH1v65yjXpxHVwvhSvTwaiFpiR5fldb0IsEDrIXkZnoGOplsHzGemhYS5hYJnrMe6qBXUtoSBBZTYnJPzXUfQk0Wk5HFhNtNNA2k/QLKzxKcGF8/uKbi3nyAekdl/Dsqg1+ovtvM70iLeP3M1Zh9T9/vwfCdx4h95397NebpSkx8dyXmUzc8b2/HnPR2jNZw2P9wO0bIufuXMi+3YxZMZceyFBaa45YLglpDz/rhuEEGfgNP7bjhBxSL7ZcTH+7O9NX/dEhm/T8+JQuGw0Hxxa9horBCv3L8VCfy05ac7/d0uLpcvGQ3x6VxdiiRHOXL6cqPLsHat7AvspdvWJnO2LHK8g0rU6+fuZx0cxbDd1YmdlamXxej310e0lncGb1fHkrvLg/R60C/do8oXo1+d5FIZ/7ZI5Uzd6oBb8RyANs7q7JaoleIJFMaRctdoSKJVDJPH6Qa946aZLIlqXxYJMiRpBpMqEuQukkl1CLBkxER9UkkDf5hBI3UCEwRh3W7yIEepByIS9ZTbEklkxNKpQxpk55oqHG20yVIh6Q6zkXCX/8H8jnH1g==###4892:XlxV32DM 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1214eNrNW0mO5LgOvUwfQLPkCPRVEvAgAb3pWvSyUHf/1GCKtGynsysb+IvKcsSTZYqWHh8phZLh/f7LW/ESrz90cuFllHTlKwlf5f8VhXyBdIZ+6LimfPFrMW6a4MrAP/ET2tr4MjLG999wm3ttwr3zl+nl1Da9/zBGplfQ8v1X8Gt5SAhL/X9RpWcjV916Xr2FK816Tq71rILFrv3isGuN9qORu9XFWDcYmwIaO3VjE/ZoHxnrpnDsWQmNPXvsOVrseX7Q8z9mE7lX+/NPeIZ/QcP3n8Xp+5XDq1CuPkJY831uyl2pnxXJHb4/JjVnaPWSQPDMjGwVMQ3J3s8e3J8BjXKn1lJj/Lob064cXoVy9ZH/5PvCSvqFNwSIC9VMi7ZMzUyf8sNsdK5C5aoY8+G3ud6V3aMLFKA/9a6N8tWHj6GOReDtId8ed2PrWFavEJ/27mGal+4FGuV3o7Zqb5lMu1EeXiIgbYwLtcnY3Sa4AptsbZOY3QLtFrmNqw83rI3ENjK3qQaGDQ10zcAwxQrNePuMrpmaa2wbeh/E3F3j8TVPkrimGgd/Su+R9S6x92wc/Pn1z9z8Dh81oroAsgFxwjEBAMsnLnkWSAMrSLqfedWk1zSb+V3XkgXKaKtmEbCg9dyZSW4xM5Ox9Kt0pDYZ5RW1yW0j1OY3X5tsU/t/pb0Uzoy2QtFRaC1QuzsGChVajRP9an6/fwRTOwrMnKTf+auNts7jgQVTWxc3YmubIc86gKEuGugHvvOcmE1jJGknJDsDD2zOBRLgzlViPTpXiW2IGyJdxg2xnMYNME+N5m3dvHBinj6+e1VjWHPjIZYt17HMoU34VX4fJKzVCenOg4+cYMo08xysGBp8mKuUHVylLuehUqNZSr8PXpNjmCEv1aMtC3QlYn2KSM37bW7DlA81umg1N2Iu86XSmZ4rYilSSMwUEqu+yeSTrypxhgI1++pN8pUfmOkxU5ZMPpG78sKH4JDZRhvyJEVpTpugGYLkro2KDMkEDazy6x+1KUGQGsKKNeCOYodbqB15XKGwIlgomYUiI1tBFsMQDF+gHgRDVB6VLBZOhvqvc6g2i2MIMqc2e0hqCDK2NlYwJI+3kCqMVxKEjTfV96jJK8mvPr+SqUKOOrHHMkCYe3sE08ZJ5vg9buXJKfN7jCDZpOgcviCHqxsOT1frWEaNC+ZA2JTzojiuncL4n9H5jHR+YHg30vcps3tk9ky50t9R7qyeUe52zWni6IudXxnlxoFHMkEzHpHujn1n+Yx95yE4fEtS0WbSJc3N4os0B4vE77MW3tG+SOAp4yKBL68WiXRXi0S6wyIxFOniDrguMIRyHXsO4TrC0WD8BUdnpHM0sA8dMGefiSGUfVhvjH00Q5B9tNGSWU15mI6HuTwW26UlLieh4tcCzFJ61a8AfzqVrEglmlDJDy/b0vxUFm6jLBxW1K4U1chB+sBYwC6hicb5jF2mkV3cyC4zssuBVcKoLqcDU/2AVKlYgFLS0I6SeP+mupSoLmmyutZnljkG/y8NX6iDUvZ/KIETv1rKV83ShXohFRsWZvxavqoenmTlb6NscfXihFY3ZOu1wfKAtV/Tt8uob+PIu2ngXSlG3t0Y70KELsk8N9o2o13Ld0oBogeI+HmZAN3yK/tF3FC71xiEXAg31D6N1O5Gap8HvzRKV6MS14cwwf2SRr9E9MvS/TJ/pYrE/WLG2g+ZL3Z/hpa9nKQGv2yDX5QY/bLW4UV8thyG17MJn+msvZOUeCnraeqgTwOpVToe0xglxF5Dkys6Vs89jQnHQasxziuPgz7OADUqEhWYPyw8+DhHgfPRrAnXgYcFtJs1DWal0az10iwtRrO2M6+BqN+DdFlMJHzD69cU6SEfVgdDukwA1d1kQln9tJgETVsZq7BZjZGlVanJ1WKUTdFgz4oGX0BmhmDAtmmzDMEgL9PEERQGMDZBkS4mYGyKIl2A2LQk5imUM+0V5xJSvmpJYqkutUmZoXxVqk8fwO/lSXqvfWWolpfy/TXlWuo7MJK1EdgmJ2xLtdiwfkotrrQp6d5i6rM22gYG1Nrk8UEsq20m9iyFz8qJ3lJqcWtqber7BcYpLzHVy4/yt7ysjbkK9R0gliGooaDrhPND9PmR2vwotdBdLP1sDyUVVKVcf6ZpAzO+zjxFkZ4Fgxjrc9JU9xb+Ivkw9BvxbsnKuWviCObDZl0teWJ966AgKqTJTbSgYEWyxLmluFwdQIrLm9C0Ta6G1za9Gj63xLqUHHbbak1SN2AJ+G5LTdKKOb9X0K68JrmhCDWfi9CqJZkIbVpSjLpUDur1sxS3iVAqPgfFuY6K04+Kcx4VZxgV5/S+VHvbqPYiqr2DpPtM+C2j8INQtqVrvaeUwnqms+uN3htjhhzjt1hGvbc+yrO53rMqymsxpnJgbUZbn0YxNlg6KtMmt+QoytSYleuDwKOWivlkA2tXCnI1vsujdKMURtlYxQMXMgc5UFeaPZcD8Oy+0ycMkwO812EVncb89TTmNxtyUMpXLF6JXQ6UKxqvrJj2+JChGovy/SwWbYH0TCJZLyvWu3tsgsnu9xAZJQsWdRl0BINFm2s7QrfLwARPH0QDnBS0uy5brGTdEaljIboyE4g8EhtDUA7AUB1zAoZPuGffi8pDI+IC1qqhSBckEIwTRbqIgc+RISh8qOooCIoleA7vrQssFQVB6Bbh3DZKW9yog9K1eCHms+JFxLhhr+PGECzE+0E99KRi0XbA9CGkXFQsvhY0nkSK+bI28aAgUcsW31WQuIlL31CFKMXHyyqEUrdViKH0EN9PSr5j6UFsYyhaDym2mm9KD1Z9R+lB+LvSQw4cgzP+bbR7EuLmoweWmyKD1d9RZCh0ellkUPq2yPCksrAdKgtiuqssQA+PKgvqy5UFUYrf13pB3uqFG5HAlcEi75SBjmfDm36/BACTD1Nr4a8SfeF5oi+mPRGDtcYTfYGJnIiYyEGri0RfxKtEX0Qau+DzyhCS6FvNEJLo7zsAFTlP9EVksZhkhVLsWaGYDlmhxLsnmhU2YugIZoVtwajWL80KG7XuEElRAQnoTd+9ufC0WMz4NpZDWmw32nNPi8Fpjr7cLm3gM0d6pYMk9sJfJfbCU63mcKqUq6uMN8+PmvHmsZ1nvLlNzXhzm57xwlteUXFFqvlgkDNFiOykcnYvreQlyOTsuuvCihA56yxDUOM1stifyBX0QrujupsWVvJ6aoWV/DJpYWVuu1Z7ai/6cSPHJNoiu0RLGZIhp/ahS7SEEs2dSrR/sXNEdNjlNpF/tAl9sk20jkn7NEoxx04aXeisw3GiC8lFd4y+UAhYxkJAwkLAneCCAFBOc9iLrF/YHt9UYPrqX+zfiNNYALNljteyJskV98qDuNlQ8Y/2yk82VMZyet2c4VrHHdJ5Ga51gRImnPjtVhccDildSAS6VcFduF4X/JOMZy4c6/3xrt5/CPKnWuYi2NfTECVUgJ2EEGUKiiKdBp3YjyY1BGnQCc/vQRoEZGZIPgK1hJqCBoIwFiRFAhlYvK0s1pF+KsmLwJBehU3zxhA8hdVmzI7QkAQTdaJ2k/KBkt3uSGUSeM5ShEbS/chUQzCSOuESQzCSguccQ/oxA5EiQXjVIyz0JnJUNy17zSHzC9VGIq0M6XrKC47007RpXhjSdZvYz6KVK1I/KGWCYriCVaEUxqBGaDkG+QflZfHo6OujE1RbvDpBdXvGYR2D14zB68GxKRam/v8rBhgr5PtrxQMWH7F+YFPROJf1A+menWKIT07pPjw9tn52egyYO96VEtzvlxLAL/q2lKBvSwk8dvKgOw87xDen0i7CK3jg7ryC9b9fSgAPLHelBOm/uZQAD7R3pQRp/qtSgnLT3WmA2AVWnEd1MIw0jZJAvr9WCqCKg1UF9ty/zE+e+2+YbUaW+0PT/QcZebFjthrPc//S6DT3bwjZ5E+eITT3XxlCc/+NIme5f0XIJj/NSCNmpJd7sLlNy0jZHiyQzR4n8xunMkJERZEuwCCdExTpAqxN146gADMrZr7Ksb2GtqY6ggKszcEduUxDY09DD/v74NlE5waVQk5QpEsh+KwYclJUaMhJUaEhfQMoJYMTTfeJdjgtIFAvqeG0QJ+DCy2LtCiFyNlpgYqUikF+M7wu1C1mp+cby3cEdSp8XskTaV0IvnDkJipUZ+9JKaD1WTJ+p8oP1/JBU/jT1ZZEtRW+pLYe7OA31aXITxBvtu1PfmB0txkznkgf9JR/X54KVXgq9OYo6ElF4PSHRlYVfrvcmNdbP0tuHkmYB7vxUlw597gF75S62YKXwWAFwd+m7+H9ZH9iPOo+KAl/MK9MTH8RdYPFPRPnNxZ1eWpsLr2n5F0Of/+DI+DfFZk5zTTGOLFEhpAcqvN8RkiMITyfkR5jYMh7hTg7hDCBzIOnCGaszXU7QolApv0HjvUm+iMfPBJVuyM/8nEzQ8iPfPZwWiYTIeNO7Q3pFV61n8oqVzQvhZskfRAtP3t6E9EX/VdLFWHRJTATMLr0emxDSKK9OvbuyH7COjGE7IWnmSCHXLbsi8r5BVN27uyqkF2n39vylnfs+k1b3tP75hedXzwn5c9y2f84h6Wb0ou4SypLjeF/fhxkhA==###5008:XlxV32DM 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11aceNq1W8lyrTgM/Zn+AA94yq3+lVRhwFW96Sze8tX795YHZAkD92boTeJwYiML43Mkiz+/tJrDm3hTv//W0rg3N5nHuzfq8ScjiSJ6BmRygKg1WETSm96W9MjN7c2JLfecoya4M/rx7rZQkOQYojLiMxLVzBCZEVf6rIYhIiO2WrhRJNvuNlMRamGx3a1LRbpt29skV5+hUKFlh6xoneBHQQxFyo2mcqMoPEWKcfAjIzoyJE8IfuQJbZYh2QnV5fMyMSQ7Dn4UlzuCMJenx58/URqf5yXTm39T+ve/Otn0Fma7Pf7SCf7NmOXx1zRlPIrHPzAv+G+ArM8+SA+4NBl6ac2XjCCXNlEuSXpJl0uKdtzKJU3/Sz4eH27NjgJoXervjd5um3Ov4pf821FoKZCnl1y5FOilkO+RVBkAlimBUrbbMyOTLJdWesnkS5bdJrvFOzrhpMolNpYul+qsvC+/P3zY6t+ROiJlp/o49UtKFEsi9UUqt42WXorlEpvVVi5RexN46iOU9+jxz6RMaUQjSiP3Fb/rYoCpTY+8ROybEi6VJZLe7BTmfY2o9bBGlFiPa0SJeFwjSmzHNaKkOK4RJZbjGlGwih8feVlnm/NyLi4x3GjTjDZq2m1Wq0abN/ocYvN/WREfk1w0c8uf7Jcw+mXtftlO/KLx3Tk6Q87ojMEDcfCAdIMHZDh6wI4e2NADunugWyc/6wE/eCDZ7oH1zAP6uDKUGlaG0sPKUHZYGUoOfoEHe/SLMke/uMEvyaNfFPoF9qvdZvNZv7ijX5RQ3S/LmV/C4Jdt8IuWg1+0GP2yjH5Jo1/Wo1/80S9KaPSL7H6xaPP8Gb/8ahwDJFRulv/j8Q77DUDTkvLLZApk3nKfx99lCWPT9aavzffys4wr67jF81WDxCnTnlgSRTK9wmYJiBGTY4jMSFYFUxITQ1RGXO2jGaIzktXHFK0nSKXXYii4o1qocOauzRz2+Nx1FZrMHNzYJr63HLZ8ab0DR5QhVzaBIq+iLsaU1xJHhOXWRmwthy1fWu/5R5mexRF9c4n11SWaIdklTtY+kiF5Xk5VlwSCoEtccwn0FIgHKvKg50wQ7Gm7MwU60zZnAnVXp7ApdM0JEjRRpOtUWCMLm0JeI2atoxlqYleBMNpKka4cYbSZTQvVJkyYjdYVKrhXMgRVLYzW19VM5SGMNjEE5SGMJhiC8tAInRiC8hBcHgmCLjfocrehy83u8tVXJzFDuuqFTgtFUPUWtTmfqc2EanO9VptVR16pzf9PYobvSsz5MxKzisdnErMK0Z+UmOkliRlHibl+S2LaW4kZX5OY253E/CldGe50pfgRXWludeX8OV0Zvqsr56MH5htdKdOP6MrpVleGL+tK+ZKu1F/TlfFGV8rtR3SlvtWV/iVdqcUrurKJSDkI0s/ryuVGV8r1R3TljOy0XOvK0BXk3JuxN5dBV3b21VxXritFLnSlvtSV+lJX6oOupH2Ql5cuhQLOPF7ryoAacsZWxNZy0JWRGnOhKwNqyBlbEVvLpa6cLnXldKkrp4OuNARBl8QzXWkOutISBHvO3ZkOnTkfdeVMzaG60rPJUV25BjYFqisDNZHqSj9RhOrKlSEXutJc6krDdeXaEXupK+2lrrSXutIedKUjCLo8dJcbdHk46kpPB6W60muKUF25hbxrSNhY4AfqSidQV25EV3446RotqlExnsjDxq9c6PlR6Lku9D58eTq74BsSiXpUeeollWdGlVdE5K7uoiLq7iDpdpVnRrH2TNItKOmybCtW6ivZ5nFvt6tjso1rDvFMdU3btIw32iURPJ10cqMiifiN/ChuHCerun70ubiJwnZxE5i4uSCpbHq5dKFlZFgNmu7WUcsMAsaMRD29JGDsSNTq4OQortUFWIoZQ+fFqC4GSSFGS9NLkmJFS4l5O5/lrSI/JMpYKbTgtEyBMBYggSKdwEGZsT6dwAFxDEECB0QxBAkcEMOQTuD18VdE1Q0QmKPeyFgCEeZoTwIRwjZ1fe5OYBSV9hRU7UToJhnNEORfmfY0RkOQfwGJDOn8S2jAekoDTWt1hNCA8wSpXoDNFyCrFvQCvOSEo6ZlmxjSiXxJecXphjRWKasi5u7rXJ0oyTNpns+sk5d6eT3lkmli6TQhkSbSKU2cLfSdLk5zD/Kl3IOg5FJyD4fEghn5xo6ZCZaRsC9nJJCgODGZkZjEHTENbJR3lycstL10drWMLLR2FvoIMlQ2Ust6k0TI0e4eHSU9JhGGuFlcxs0ivZQ52Nj2alSSN2G90njwYGDTHcJ6HrNzS/2w07agnwX79gvBPrwoeQx7yV5IvGYLjL04a9mRC9Qdaw1UNR18ueW3ZOJUJdCXCs3SuusBf0mq80hC7TBtQz/oMYjt3Lhh3sfpxLjx6VnNOt57OyfAakPZ0BZNNzTYEHeovARUmqtt33mzz2g0ty3ITPCQKTPBcDOByOavpBQMQcJQcpoYgiQDN16JCdmpEJ3LUKFIrev83BbePlnCz0rqiSHIz4CESgt1NDBu/x9kapiaYZ5Cjmrbx45QjlIKA478EpN4TSlMcRekx2tgwkYREq+pvXyjIRivwd+CIciFbcF3BLmwbSs70swuDAj+WOkjIaGpnCR7WKgVYEKO+qdHXYBIivQaFivUynyKwSR4m/XpweTs63yKTNqfks7cDJtFdlyEtzt2ZlY7M1vBmBkz9oUDenZdNb65ynnPonJHy0SHMgOSkYZHHq/zvBYe17fzvHCL5TqRajf//UQqbGPTdU7SbuH7OUm4hblO79lt/n56D1ZEW/zFZVT0Ku0oVOQfPPvSyXQkssyC0nuGqEBNMwaWLaydSl6w3rQ1wZ/YNDxbqPSKdwz14Owd1lWdwEYQmp9Uepe/Zew6gVmw/F21Mufq6iRrK/93axkaDcHNVjIiSwluKdIhc7KuDllbecjWMiSBV7RL9pic4aWUc38rNb6V8jytIkbl+0wfJ0J+F6I4oCgelPAyKuH58UrKxj6OqZq78q8Tcay/Wv4lB518OHj7QuLmRDLH8SwOpEc0OpyUCXXVHHpqRXmewxGj/n2mkk9D+2zDdCeNQ68jStONNA4ojQc9HEc9PIq+s/yQ5cJTi7uKJzW5M0tfOpk6kcjmqxVP+hh53CR2VD78OTF6PDaSjy/meE4k7hguKRYugahYukpiyRZAAkMw2cL0Ewv5f5mUdqWZHyGRtPB3IAjVwVQMJZZYomIoscSSFXFj1qFwBbsVQ1C4gnGGGddVtdgURXomCN4Z7BMmpvvgXx2BiFhUIjIvdEVoexFMNQEV4bTwPkTY672Mu7SYYpbcBKKYpbQUoYo5zczsrpi14EhXzHovn25IV8x1T9mNI9JTqpQY0oMleJUZ0oMDLXifXeLmLcHlTtLnXBLhxgm5UbFSllfrVtYhM7oXUO/c6Kj0PWaJljFL5JAbB0K0IyH6y9QQqUwZ8kHijvIoz03td7vBJ6qVH1FGrYesBHKWVBJTKZMKjLNerQ0RYwWlOI3Ksy1qtGXttsgTW7QYcjhjKXTLzsjxhGrP5egDdzGicuE6cZPlXzdL3yRu5KWLWgLngooOttijLZR/PIYhJi2MfxiXf67K9fCM5JguIuulBz8R+osaI7ryyudx2puWv/VoBQd1wJyGz638H3l/qzG83IPhPG1aGaD0RpHOGUYbw/r0lAbyTLkR/doE/nVinXo5gZq4CZ0gNRJaRhhBakzR56XD8jfItxUhyYK9ELMinU6M6uzkAjvYr4uhI4SIHb3PgYg9ukGxY3GFhYkF6aQBxlmG9GPxZWGj0SOHPTvUkP7h0TbT+7Qjh/xM6idLXSqUzYlkR3qKqCI9O9LTSg1BirJCW4aQM5aF90GKAgsTQZiF9QufVDZdWObw0slOVAaJSt984TOU1tFzj5svfNb1LsQ7K7+8ivrc44bkXon67OlHP88P5j9JcldJp/Mgb4/VpvF4w4yhoB1DwWcFl5lYeqGlDrdnJDMecE89XXNSaLk8bo5Lbr7lEfEuJryquUyru8nFqeUHai61n28j0F5ZF+ebCNQ9boj9lQjUPvusx+h4Vxupou6Wyk/VE3yd4OEB+Zs0o1p/oPRRl93tMoaNeAADZt18UjN+hNZOW8RYDSnHSPdZ6ePCYljQAkjRc2JaQCvLkB4L6lkypNO6njeGEFqPgiD8ZCi1M5HyFrVKx/y8WO4SRthPOPL6Ynw9J4aQQrwYCNIIJw+9F+KVqHa/dS0NLHAvDWycpH43m8b6RexeahVLd5LrJGHmnFiATsLMOXGx5TGe9fMhcMbquwyxaNIHhvTzF4knMxXpUavs8ayf+TmPWalPyZfRUm4U6YpKxsD6dBUGezp/QvTkDZ9q4Ic5sqvUwA5z4G9PEVIZqMPCEJQr8LdjSI+otZ8ZQkpCIr0Prp798yBYGQpXhuOVgU6yh0HKJ+1Kn23XiXmPKloV3OuY+rGofqabL07kN7842YYSt6Konkke/7j5zvmga9yolfyYNA9nCW750scnY4I7/QctnW2X###4516:XlxV32DM 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11d8eNq1W8uSpDoO/Zn5AL9tMqN/pSPAxhGzmVrcZUf/+8g2yBIGiuquu8miOPilNDpHkjO9f/8jbVpf4qV+/bDCypfX8/unT7EiIVHEWEBWC4gS60IRKwriALHCWIbIgnhATBaSIaogofU2IaK23uCj9mYYUnqDj9qbYEjpDT5KG50ZoguiS5vFaYLoNeb3D2mX9RUW1da7WaLeNDKWpik0IyXaaTUSfNRGM0WqkeDj9+9F2qlAMr/CS+lf/9PZ5dc0+/X9H53t+rIOrowp+CLe/4X+4GmAXICxU37DrWrM/dYqyy0r6C1Rb0nacK23FH1K11uaPpXe7w9YG9wCKEX6dChPr2zkqd5y9Jartzy95eutQG/Femuit+YyclZ15GBoB7msJrCpZ11vJXrLlluuTT14uva1GC141oGst2J7OtS/H2Fa2/8LtUkukw2Lobdqh4vdnnbbXzbppT5Sp/Mxqbk+YpStFwvs4DJUaSB+ta8dpmneZTO4lxJe182QX85M874bVDrsBiXScTcokY+7Ad6j425QIh53g5LiuBuUgDV8lPehzLls3FgaWD5pu03ayrDPWSWNc16pmZfNUPVb/ihvEjPL72KXNNoldbuoE7vo41uiZBjsIqfBLtINdpF+tMsy2EXOR7vo0S4r2sV3u/Q5y6/aJQ52ya7bRZ7ZRR/totRgF2UHu6hul6MxlByMofTRGGYwRg5oDIfGACe1T9R+1RjL0RhKqG4McWaMaTDG+PJogca4tEBECxyWbY/LVkLjsm1ftsMpzV9Z9j8bb1QegsEaD4FnKRQWc/GltkLqVdoUCoMu8NL0S9suf9bP2m/YqQoMW6kK3F1l4BwpUhgYvF5jYM8QWRDXGNgwRBXEtzaaIbogoTKwpePsDAwT3Rl4mnDlZls5OOvSNAlNVg5m3Ba+Xxm8svXqJzj72uXKplmYG9x+m0ygPfq497hdGbyy9epn+ajLc9hj3EziQjOJZkgxiZetjWRIWZdXbRaJIGgSs5kE7qLQAZfZ5AzwcW25EgRb6m5Mj8bUu5zJDVrZRKtRjG+N2OLqHqm6CvbIxJZQ9ohNrTdFp0gV5GQoQhVkdmxZpwqyIqcKsiJEQeY+znqlICtyqiArcqogK0IUpKUImlx1k1s0uTooyFXSTqmCnDRFiIK0okJyfjn46Aoyo4LMREF+eOk3RyZG9SdHJalG2XiiEeczjRgfaUQ/asQwakR3rhGDsWcaUY0aUY4aUaBGPGhDuclGtQlB3/4umx5d6JLy+t5V30EQ+lE2bgJQTlX3mZzDKBW67lPTzhNOBab7uHIRo6LLg3IR8TNFp8Ssr+VWVkjWJogbtbU8Ult+VFthVFvuM7VlxVwaGC4wdhPKaNI+aS071aph0nmc9DpOOrWxVxxbjuLG4dh62cf2wjAZxgWWGkyh+qt3Ji/gjS8bSHN5IfrAMy4auHYfOAwDz+PAy2GFkx51jOoD4Qb1RjJtxQfKw0CbtlKDAjsuFhzthNwHyy6TA6EjC7nZvGJYDROl6iJXQtdbo+LM92dQm8DuUuwZgc8QZdPdLlxVX/6zuXElI1LQrBg9Zu8o0ulx/+J2pA05S0qU8AKhAJslVQ6wr1eGEOUwKzJisxG4rQZJ0mhbgan0ChFjg+qbT4hXZhco0onXiRAZgsTrhMsMQeJ1YrfHhqA6gQlYgrTJAZlU5l02y1cvSdgaGhmGIFtLlzmCbG3yvDCks3XzwTuyTUH6+k0EQefdJcu85YCqPNu/DV2BvAEgZffdpCtLq1yWKg28ttIgSwexs7QXpyzN8j0tk8PyPSkN+Z60jlyuB4dCc0idRj/lzK/lVcSb0ibjHjnmUdJ7INf4iFxXJFeacAGbB3WdV5GzQnIw611eZR3zKsuYV4kjo4krq9dcDfXoKpdZuouIXnWPDp6NUQkP3/Xfhu/qOC17E1srjUke0ATXsbWWY6JhZNfN/3/GEnmcdHwzwlCo88v0SWQJ/zuCUG++fQEN8sxNWhkX2l8PDuE7DxRhsTKfQ2cUGRNDkI/gf82QzmaSzNvTwNCqVVOEUE3b+xUJivk1J5QgEHGG0IlkAyErbTuhI52VVA4MQVaCt2Sh4/RoBl4pOrkezZS5OTY3dPtOSNYbCdJilAzZ3T5sYFkDKmhp4aN7XYleVz7wunr0uvmR1z2JoNIQQRWn3iMoHi6Fb0ypT9d+XqGfvwmIeNi0x0Znzv00Sb6Ozn155NzTSeRktbA3GXNlMMNmsr727FKMnj098exn8dWYGS7EQb2prnrLXaSzlelOPloWYPHAJHxj7nriM5RVNl/RkJy73p/EDQ2ZIXF6Etkc4p8hyNHVgbnzIEepCYsiWlkW5PC87pj83+Iexj3+NBQ6znTi0VFzLuYiOppD6tGR49HRZyS3noZC4Bx37ij7n2lidLUV6Q6VuNqKECcsxbIFI3pzmz/qkijzaGQRHRQPviRST2nEyFQHSVoR9lNSzmxMiWMSHmRjElbdDN6GNIwHJSZwyxWjbxUM7Y7Qt1SKdkfSmFImNlCPzsQSGYI8CIY2DOnRWXNW7StgKUn4PzIEI6PNV+wIjYzghmeNMASDaTuK9IAO/ndkF/Ao59AdxnqEV9t2o4yrGdIDrRgtQ1BbzJOgoVH70mtoBG9fnUF4TfDRSVohSasHJC3HUrj4Ymh0Q9I1Suql8MpCV2nP6f2Ex+PI4/PI437kcUdL46r5iIs0qMY06BDHqfcTqrdfLJXP4kQVfC3O2/l/IH2sm08qHernutasLtXAjHViZ8VNnDcmAcX6xTjvTg3wkA/YxF3Xz926fEP9XIv5pn6uTOgqydxkdKf3Ew2yjHaZRw3iRw3ijnbx1/VzB+/N39fPlfM39XPZbU/tMtbPLdpl0BPm/UT5uM/q52CMcF0/d2v6hvp54yBzpbPMdJZBR501iKsx118kGJVNys3XSWUl+6JczjdJ5TQkNs5kJExoui7Fu3X9+1I8LGgvepalMSnjPEOIsCLMH7mwavbZG7Gc88aUv37UZdGiv9L7absKlecBSew4QHU5rfBf3zK8DP1y4scBNheyz5OKMS0CRaiuqopC70jNcrf1oxDslfo6qVqVr3ParwJeTbRSD8uccZmhLRNYp/S45oX2WKryrcftKuDVRCv1YFNJeqTHCZyQmKZwLLVBkxHukJFxgSAs394VYm3U9aYTYmbdod40cVkZ0vWmXi3O22+WUJpr1NqmVyZg2gK/s/mgNxeCUL0JBhJkIHpEAObN+yPacYkMIXUCMTGEHvFUFOn5dhbezFzY4nGVcsWErcKCRN33pM4OtpMEqrYDUdcSaivpj2heQBxD+lEAtQaGoOYF16cpQsIy5SNr00M5qSeK9IBtniRV0O2N2ooLqR4BiCXNFbuC1qig9R8p6JPiwslBgZTHw6RiVNDr9UGBeVTM8dFBATcq5mlUzGE4KPCk0jEq5KanP1XIvOjxPUmweJoEk/42CZaRuWGUL8nesbxxdsggjbJ3HWVvPJQUkrzTpBIJ2Qp7o0nnUZMuj04ZuFGTTqMmDYdJ16srwVgOBtwJxidlmhPBaB8JxkPFRtetf6nmkuhqbmJq7g9TZEzYpZvTAqocssDzEOJG2MW/OS0AK9y5D+7xRFB34GAkWq1pblrvSBMsiZ8EaFugPyPxGSL3EhYiEj+PoPHXC+WKy72kSSOWR8t5IYthKiOhMkmS0TWVJklSjqe1lcR+XEFVRpKcrXutKLEfccCGCHRyXWUAoilCdU6MbEFU5/Clos4BI1iG9PoSSXdJf0hteop03gX9kClCDgFqKRnSmV931SQ9Y34tLUN6Ja355h3husRLalIic1DeN6TLnHlSjPpTP1ega5JOzoX6++m/YJD67efUn9ZH1C8eVbgyeTGfl7WmL6bDSg5M3uW+5HAEsCW4/hWSp7/9ODD7BY1TSQCec8p3BxV0PuGXEyaPjw4qrI/KWemiKlPfen7ebl3Qx4d+9EziQQWVB64eGVCakZjVgV9OztuhdJCzEWf8IoaBpi8mqvj6o75TAgtmS8wsblJHeqxKyX9RFER5R8xLP8ahTo7xDXOId2xMD2owYpZYhonHeg+6ZB94cNeDyHioSy2ZIf2Mh46KILws1esZUfMKDZ65a0hnH704hpATESpThB69wOpRm1wXEXrxrLdO6LpXVKI+HNPr6sSHXZ3M/BeVakICnxmBb66lt1bYmpShkMrLVVMn4F5rczw+qGZ5yAvYRBfDBAA2mjI/3oHfTkXo8Y7oGIL0C8jEEKRfKiemzA+yzIIgB/r1tBGNr9tXUOXSbqRWodpUkOY/0gwWSdZdk+yDX2g+LEvlq7Mj4aQctZPuzrQ7ve6c+phIH/3esnErJ1I5EqnqR0euikhXR0rW8UjJ8r7k3vi+rCP1upET080pEuk1xqLe2pF2n/zY8lmxKH12dES1H/hcFYuc+4ZikanbxV0wu/a91pAlY3ZmjKtfzFEiB7uHGyL3Xe7QCoC47PqEp50I6ZqnYYjl5Kv9459IypGn9ciR5lRRqParr6sSj/PfUOJRtTZweZRG4T6H6OhY4vk/bWBIjQ==###4708:XlxV32DM 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124ceNqtm0mS5SgPgC/TB2Awg/NFXaUibAwRvfl70cuOuvsvJiEZ2/mysjZZLguDEIM+JJ74+Esn6z8WpbbX62+3mA8xXrn8ygh4lf+VVOSLSGXRPzqGmB9+7VasGp5yJeI/KGsilBXq9T/4zH5Ip8Mrv00f1qb0+mtZZPrwer1t5RitwL+6t5ZKa/+aFBd4Uv/9gHbNBxR4/cx/imRjEpUlCiRWuINJZJZIkMi0rkwiskSARMlDUsliQAJ/ssQqKtEbSOAPSIRMVaLEIj4WGbJyhy8qrA5Eun2U+/Oqpfye9ZQOCi0hrbVQ/V6ZrRSS9fFn+VvqsrUZo+JeVfP7UlQzrYIqgZ78KMNTOub3or6yGysjsYzMZWxpwR+sjMIyKpfJyhbJ0CLPh9fPVa5VtFIFs4X8XsZIJEN66F1oHcxPP/OfMo6m2xfUKCPsnaqSg0myMk5Wk6huXpCgeWU1ry8DZ4Xln+f+Wl+nQWSSbC1zlCFVAodUtiH1a8yjdQhN++L33iQ8/fS+9AW+b5ZYYp8rR5MYKinzK9b5ZVq9VdIG0bfZGW0dRMvKSCyT53Z01SaGlVFYJs+4mDteJEOLOoguNZN6nOa+mhR03+oK0NRcZXwXV1eNopIyNcsaXEIYq1O36vLg/Pp3W+uKBp1WVFEXQVUOynmcgCD4tcNKC1kkPiz8+S9vNelj3bx91Q3IONd3ml28/oHlVbcTvY2dRkZ93v3kkXD3w1Ly1beovi9h6fjqWxS+gt3rH7BSLX0EWlHZPiNtLobyytJXZUuOjr4qW3L09NVaXq30lc0tp7o7+9Kr198wKvXftp/CpCafJAW1wAqgr7JNYE3RV7K8ahW4UP/1oTZUtjX4d2/yfaGf5r0cth36KpVXpMswluUV7XIK5RXTbIdXeQfM7exmCbknjjodGZfmdJS2R3c6i/d9KoBr4VNASTE5QHGcp4AS6W4KKBHOU0AJUHQ4LHCPm5g1PdA9LkvX1BmD7lFMmvpJU7lPmsrtdfan0r3OSst1UlpaprQS+jj7dBljU9pa1FnBhtB1lnR67G061PmY983yog/grzyCuYxlTSQygogNCmZgb0N1u3RjTBZIkwWUmC0QXxxhNjV1N9kxRuYKYfS5bbXMbZupbaVfF2AD9ljT2R4Do5ReVtRBbAyjOL/FaVJoMaml5azWMU0KFeikgM09oJeEOc1c1kCiLCFurq7T4mDC0b1IoZ02AbqIkFwbjiFBkoOlmJgESY7603BQkjMwCFQySA6+8VQySM7oXXcJDEtlkN1XiWQSBKLh4ZoEccoos1LJALbGEAUvYMURclBSWlYbAlxjKPxmkBPYDdkYLNh8bO1qnV29Oup+G3X2+hhqyuQdHdhBIMDUiUmQOyiHF8mgDcLuRZJHPK5Vc9n5DSSd33L3Ch4fDa8DVbTidVInzgo7JRKQWCoZREI5KyAsg90o/hHOCgjLpQzCY9vgRxmFZZBPQRKIFpWzwHcWyLENctz4sENOWTsyQ44ckOMQcvw95JzJJoqJbBq+yAmJ2OGLotEd2axvkY2byWabycbOZOM/JRtONBxy9Aw54ruQo2d8YdwTkXtOsNP554uwc6xPsOPsI+xMhDO7iIYxckKjq6lQEIkRzro9Eo58j3DWtwjHzZpus3+3M+H4M+HEJ8Ixf4JwDvdEOM68RTgnshEz2TBjHJ/DzhoeYUe9Bztmhh31Nuwo589ThsSMNjVmNBiMwg6bMhVjOP+k2/iVFr8FPSTas3G0OdCrwxNHm8MREUObNTDJQBspNJNcok2RXKJNllyjTZYMtAENkOJAFwYJlCwiJQvGKZFxiojd8+YxJbEeOAjtVDKox4rAvhlsAxLLJCQkFVYmQe4CSWCSwWp1lnXJLfREDj3AuYkO+eBcwKFIJQyHuOQSh4rkEoeKhODQumO0cBs4FE84dNAu3OAQzMQbHMqSaxzKkhZ2Cnc4VMpILENwaN1YGYVlCA4dnmjBccgxHCofFhyCMcyrWZoPDX8GDnnEofW3Yj4twCNOUZwvxHweyCggGXUc+k0GAuf4GfvI1zsBHjOzj0D2odAEBtfuATtkuNqk34uxzK5M7F+KsXACAU3DPYGApnh2NvDlPYHsr3NY4TdZYz2pV+ztrj2uyiN3oZ6+A4HmUz+LPNjZ26nZ2xnm7azY+xk2Dz5xQiAxTDIyJbV3KCGZEuUclVAnRHyD5JH8oJlkRP9JO/BEHRdzQpLuatBQYtXhXgYSyyT0QIff6EB3bPhGMQnu2G0GdgmLlp/6SqLlxD/l6gZbgERTyXBBoNzOVCAuaHNMQjIBe2RjRzJjwxMXycim1cXfJYRufu2xWM58yA+yDa99G7Z0G57OUquqU3pVB8NlqDTNWUTd1ogTiMrQ175Ctq/g+L9WdbbITTGPD72TQ1R8LOgHgrjTT4qHhQ5UIFrIF4OHlqOjXxEgQoHVjjwI+8fysQ+rbWi1jTmv4h+zN1lLd9rp92+v9M0JNdb/l1DEk5Wjnk89pp969nHo0bihxy8demJhmrtj1fb9U1Us3vR0evG9gXXME4ENmC82YO8novXfn4jxaFtFthXDttSzZ1lSM5dKly/2/l6ztLJJIQxJg8N1THbTPimZ5NJcezL4ZPlSgBpFr9GypXDE8Z4uBdC6LxKotmq9ibFGmg4lP1r6VR9Mf7B0+cTjGHXRbGvSpD8lb1zqqg+mP1i24lJxdVLnrWoZa27HNbdfAuNd+u+UJFRz3Ow+E8gQ8CnX52caDJc0ONY+RqVs+/cmuPSwLVgpxbxsF4wJrBiqcJtiqHeXKDul09QcWXrKmUkpp8gJiSitSJ52V4znrnNCF1kxP6u1f8px9UnzrUF0jnMCvZQ+hlr+jmuVZ3GZ5jmWm5hIGrU75fg9msvaj8vIS10TN7tbMupue7vd1mpSiO5vCQ+SudVySCx9I6f55dgiK6OwzLhgEvsxvDyVQ+KPXHc9wcfOiWWyEEiLwTDBOFVLqYiEMtpw56UBsh8Fh58ISk6xJ6+aYER46lLqEhoWwg5VzQbUxZ4kayoj00W8hFQFiHSxR0Na84PT69IZEuR0sK8ffczj1rf2QUZFQt3BwJnyREMoySysOnQIW7s4Uq9ttGEtR3hptjw2eVJ9KD125IBHeEpB56O7fOu6hr4/uh/zJh1fFLY+u66xzUmNgFv4O6d49yIst7gpTcGdSsID/TsZDDOf4svx/w4VaRKjpyWWcw7iJokRzkmMngXxpywIupyRzBAlhnQXVRAeIXRx5j6qUF3NZzc3pLiPKszbvWChX5itJdV7A8tGi+/TMhjDPAQuhEdgXtbta5dDttkY9yGWqxiGOxtD3YO9UekP5EuEXR7CJMKvV8bQZ2PUxASPmMj7S60XOYvZGDm+wo1x3B9CDEyCb59CwBj6PkMCxvBXxpgzJHPwTYXXG3dvTzdF9CnFwowR/D1SGHV8/8RkxNJ8Tdk9iLsjwZUqQXcnrdioZISlpOletUpGWGrZ3WinXVL8UfpXXV7zXyAvL1lAoCYUTBbt7cLuj7Jo8PHAx/wt87JJ0HYpBIlFM8lIbojFMQmBq5Ks6aqUY1bRpD8d/Sl3bLCONHGjNY5UjjR4e6RI6I1jvKZStSDXVJZh5YUG8sDKhki6lfejWXnZjaf656Nd1b89Hf0p6z+SVDA6oo/OfrDTI3TNUWVGDE4av1MJTYgI9s0IHULXLJNg6BAGUjMJxjWhnYDKKXbsJ9HL7A4I/kFDhkmQ/6AhySQjq5QvI1MJ8i/Y3RIJ2l11u8MRg60lhF0jdGISpF2o0xEJ1ilxxfQQZ10WJHYByzBQRUf0Ez5yVIKgXAgyXBHkgQS5PxCkmAnyeCLIhxP/RR4oA+oJJt8hyHUOAoQ5COAer8WcYVJ8CSYv7vyqx+swlwQZZoJM5+u/HRPtzJluvj/jT1eJL2FSPcKku/CSFzAZZ5jcn2DyIbpxla2aHOb+wJUq/BGulI9caR+58h2YXOeYyj7HVNxn93DAGOGJK/c/wpXikSvNe1ypvsSVFxd/l8uIDFjgESa3PwGTJj3C5PIWTFY8ZBbQYr5uLOdcZJiNkWaujOeZEZ+4cv0+VzZvUnku3vIcLFcktzAeCc+dbpBAvUhSJnFeUiuVMF5yTDJ4jtChSXd0aNg1ZfDLgkiQZOMg2R17flz9rqn3vKNiwKeBj/GEj5EqM/CRAl2uscFbwKcBdOzWEeMscctZgl0todgpTthJJWiSjp0MnOQJnBSR4JdhGHNFYwbGdmCUg6pDwXPzVELBUxnWBQRPqC1QFSkybZZK6N18pVi3rulS3tIlC64C74/+KHYXjZ7RFD2jMa5Ut1ypTlypiQRNvg+TOzT5fuLKuNNKx/FuHN+qBI+EebMp60W6nCvygysjcmWYufIm3/BuzkgQd9CwkSSMPmPEi2tD/vJHYTO/XV1j7r/VurnGfIK1m2AgyTTJ9Uxq8ZHUDsw8LDrc32H+vYyTiDee14kHEHPy+yC2xHRxzRgzWcnFkViTDMQ+pa2Lm0j+s991wVK084+MegZLhnHtWQfJMlgcBOar2mpGRDVf1b75CTlY6SHYJdeE0UUb5QOfxKfrwCcY+cJvzsdl0TJjeOimqp4TJPmJJkiU1L4muYrZa5IrFyIeHMoEVkZgmfGLbbkYVkZiGWQEqCfSMrCrtTLkx0Z18P8PSkN3Kw==###4632:XlxV32DM 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1254eNqtW1uypDgO3cwswA/84BK1lYrAgCP6Z+qjPytq7yO/ZAkDye3pj7pJ5QEsC6NzJCuVksvylzPyS3z9R0frvyaldP5K0a9s/krTr9Sy/NLHFuG75U+QcZ/hyMA/8RvOMcfXJKNf/gun2y+rjiV9GdORWP4zAfbltVn+8m5LN/jL+1A+Qxp3+TXJTecvJmXWMoTRNt3e0iGUUHUIpbxoY5iw4xgzGD4ZYrgWeS6CzmUfnKDl6IRjdEKkTvjbKOvgSP3+kW2FOy4/fbAFUQxRCXEJ0VYzRCfEJ0TEZLf+/QOcu36Bp5Yf2c3p6Gf68+dvGYMtV2ckeQ2g+QBo2oWml/vQLoejn96ny5WUzODJpMGnjAg+FZEQkw3eTEM2WxGzF+RAZP9Kfll+un3N8zeRXpQHAifkiwK5KHvGHb4gG0N0QuaCaGZC8rNN10gtJEOSn51M18hoGZIc5ZIFUwgrQbLZ1VMhW6gcWgiOzBNOfxLiPUNkQvJoOr8OHUmzavPdGZJmBX+yHXQctGOtdsCz9vis1/qs3V5d5air9JqQLZt4aIokx7vDlGe/M/emaR223M0zJE3rSIt12uJM1lR6N6ur8uHP/DevaUMWT1kIZRIwqqXTz5bqcpGIFMmWwp8/KbiE9LrC++y+lPydXvj4Na+zW0oYMB7f9yCWXy4vanhX9drfVXnksEZDgdzjORTI/cBQcHr/5b6f3395QJT4BSu8nL2XUAburZ+2flZzDl8/5xziXFQl5LFRYgo88D7Rr1LEgvVNv0qTgYVNv1L5q3pPDKv58xeEhPIZKh50/ZzqJ/VLTE7wObK0SCeyWcHVs5ktyS8tTKconfzpGBEcE0Zpt7co7axpTw0CMH9aEH7OT0uJfQjcYrt7WkqEIVoLFq2Tpe7MJ/IInU9Us1RDQG2WxmZpM6/ZdDYkD3W0ofLanvhQOw41beiUySJ1ieGWdUIn4jUD8R4HEu+KxAuBuN1ZfpN4vR4cFS1aP0+dePsY+vz8qq4QJxFxVh9mJN5puZm5fZIc4d+QHDn0u1vJgYt5CoZJjsslQmXDvd4YRMbBRYYmUkI0lpXuxHEAEW6RKu4MIXxkHEMIh5nAEMJ7kt0NQ3UyTlKkh3cmRwzKEUvlCCUrcHy+GiJVRtZAkS5U4P8rRahQcZIhXY1p6xlC1JibGYJqrHJQYV/LlFZdJfkieFOItID/C4agHAEejAzpKkpZdg2VSl6xa7rsieuOxpkmDWJVN45chKrCNnVDVaZBlWmpyqwxvTxVx+SFtpYiXV4wDeCovKjCQyMilx85QBKhUfViP0fhOagPYWZ07BRtlzqJMjMiKOCIyVHtNvKYqUBhEsd0iWO5xFnnInWzIm2m6SRWQBSmG8gAkUmGLlY8ipXjs1gpMoSJlUOOYmXIW5qkoYriECR8crGCp/il6Rb8al6ahMGvMttmNYNf5cTwoHIAnl/TOPjVChHM11B4kjvqldyRKHdQ44CmcSdNM51VySdZI+OGsuakdNjwoCXguc76XtjIVXtkQdAet8KmSBYubOIobMLAEFX+MI1zXBIjWHohwfZuqUPWOlamNrgE84Olch4slaOl0g6WSjeoMbme1NjuB4kUu27cLKoxUA3NaDVYOPpSjtm9rJR6oMNGDYUCBxw2ozwTggmcj2pGL0/ircaKm5IGDIwS1GzmvqRRKxMfJIYaF1BVHUxtbExtWCEbt6X1T+WBmhVDUB6AyHcU6fIAEEkRkv2puSPiVDvwjZPTEQ3WJAFPEC2eqBllASwswqKg2nSjloSAyT/yAmAcnN+gfo7Ec5BzazwoFhtWaihLuY2diQmkQuG12ZCL6lwmwzPjPJfLWkyZZZc4ChVBQUjByWuGoMSZthCIpwnpWiEEQ3opJkZ+DZZi4Il6inRpAIimCJEGMRp2N5QGVijB1hTK1Gnb2Mrp0hb+PxGE6uF1LgIgq7H2mApJiy1XFLZE0lsn6RlJOr4g6fiGpCv9yrHIcFNcuCVpN5K0f0XS60jS80jSdiDpgZk1MvNQfZDLEzPrkYYZWceRrLenGgRl5otyRDCT2J+qELAOGwVK+0DW+yuyPkay3paHggSnABvvyVolNfSKrN1I1v4VWa8jWc8jWdtz6UQ/kbWLnazFSNYDWYnRhjND52Byw9AqychXDG1u60WVqYfHUwLFXQVAQHZaB7bACkMFgNPxv7QPsS0fSgRK6hYSk/lsT2ETBOFc6pBLnOZMZ3sypmsyVs4hnGcnTMb0ifM6ETjNOG86kFeyoT3hB0RSpLOhFX5nk0M2hGsOhiAbWrEht9rIOQ83GQrS01RxKIqQyrnoDJoQkg6XsJOQdES5CEjcMycKdCLKDkrNluW6YObMkL4XopwgCBdOdibPhGqgrjWSnUSHEa2REVrawXQ6I7QchKquIEQj2sAQUnbCba+CIJ/D4p3ZU0Tlsq6C0bnTSOelDDHk3Guj81lc0jkr3P6f7LyN7LyO7OxepdAX7OwpO09u3DFQA1Fz7lZjVi2GTYQjUhq/pu99eb9v0Jj9hrOXX7Ocy7bB5C/K2MgouqdgdtOMsK+e4ff4d3/i3yO+498w8u868q97lSxf8K9fTkYPdWlKh8fRaxE7o0POSsOWWGNIMZbf5ZjpMlaS1+7V23RWCgoouimFgPsTGp5Zs9RTpcAGDuPAjiuFEgruS/YSFxK8jPeE3Qtwb6r34omlTy0CnW/CXQKY5kDIsAblzB3gzhSP6zmkDt6DcEZokpgXC15d6q3WnvoTdnaOwnNIbXxDioejQvHw/mZ6CorMilbAlT0Q4T0BVswbgQinWbEqhvSa77atDCFEPnuGECInrLqfiJw+jOLxyRXynyjSqRNsi2yqyN6AOIaggAIkMARlkwwGBYM3lFRlwJp7QZBUpToiQzqp9v2fgvQkuYTXhjBhQnXOflvct0wsrqusVAyysq2USsV6v8qsA1Kx/GflbzFm1nrIrA+5vNi2T4n7zbb9U/l7Hbnbjdy9feDuT+XvQsEfd/tf59stbb4k7PCKsPcxyT5Skq2Dfkqyg+q5kfpeRXwsaEoxJtlxebPrv59SV+2fiuNmvqJOcd7SfaqIryPJu5Hkw0eS10E+JdlB/uOK+DYyujixqA4P+baytufb00O+LV/t79+k3iWS3DK5db2TZL5n8pJBXzP59orJP/b9UeYOrOBtFMb3jNBES2JypnfO5L1XTu9sF1xr3LbUXDzA7XFvGJYNzb/h1Vnp/egOOdYJCkJ2yLVjCFEBOjCk1xbK82oIqy1o3SfrT1ux2hLDWZLaM+aE5Iw5jc5aDvOz7udIPKeXL8ob37xG2Bdky0rMYmoiHAyhmbhlCFEtm2IIaagLmqwCzr696S9dROrnnZczQjv3em9m0KfGDLYQu2ggwqkgJBMPkiEoGtaqwmq+XZyXSV7CGi35tvuSRyf5DUleEZL/fxvxTkx+s7d96snzPFf/yNEpDSt59cDR5lUyfcHRAjn6RNuXzXnfKpMPtB1G2t5onq1W1tuUCpvmgbxF6E1dSv6LfXonpr7Zzr5p2ZMmP6FTlcBUo43RvdmtFwmO77V8lZigb+oBorOuWyNv1ftE76causg9u3c5vAj24gH0HH5I3O2rxP2CfdVIb/rsdXPfaGeM+Rca7UpUvS+zmytnfLPMPjhjLBKp/brV0ExDq6ESGj0wdQ/09s31Ox5ofUfT7x95kde+o+R5PDy1IEFW2Wv5PJsX2B8vNp7Dd14T2AUfSjcV9tGJ3gWfBq3d5yXkq9/VktxiBlGlt/Y100trX7K8HVn+mwMzUxNImUNZagKRRNLYiZndJUwn3fQ+0R0JEXaGkIZ/FwiCU22NY1PM++A4n9wSl+F6xJrjwDETOsbwxsBeFklRhVbtRYgEoYII/DNRu0lRQmHbYka6VAL/aDZXWpQwDOmyiG4F8TJCl0UFIT9RcDNB0HOuLxKLvnDsJwpgomO+QEUFE9Z0OKKRFRYgMtJ1NdzNMBNRAlkxc+ObBPoTbOkWAcny5bpm2VGzOFqYuO6Uf+oui682rLfrXBptu+4E8r0Z3Tp532n80BGkxavNxf1TsmOx5yYfUZkP9CUIxLpnzcYQjEhwTWAIRjEZW0WzIvjSwzWGIiRQREuN68HlT5hifkfkBBm1nPrzP/D5+/s9oodmjueSE5WgdqwvfWrTsEv/vUivIH2/W5IWl8jSfm64eFsLSt2R4F13v3+T+pNxG0VP4/7NUytFfLuVM0UzFi16aSeu04UNRbqJsaTzqUnC3tkQH1oJ4+qubPiHrYS0zMJssHpUK6rbsF7ZML/pRnhXHeEthNK4ynXZMNqKFqVkSFcjsRFaPmJBxjjDLuphYWoZc0UwlNSnkhETWeEEbrcTiAgIkAGRIV1AxPbLiHxE2Rtup9lFyMRgnWRI7943rRs9345ud0SxMwQFBNxNMKT/Ri82os1HtNgAA0l2EVYo4HaaXER3G4yXDOktebHVlSrSf21inGBIY+e0c5lLjBLEA/zpUThiFJ5f/JRPLHe/vnqIyoceNwL25XY/fx7387dXewL+KYzTnYPP+/kPDXinHfu7XwIGo2V8KtL33IXUuy+K9Mcnl18FainGjD6ci9z2Yftd9cRPx+Nh+30et9/Dq8q8f4rstH7Ptt/zIr5L3VN9/Zvb7w+Naqda+ucfxv1dzcs7enBEo50VUhDof2BpWao=###4516:XlxV32DM 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129ceNqtm8mO3DgShl+mH4CrKGWiX2QOBrgCvowPczT63Se4R4iSKtu2AVep9Kek4Pp/CjK3l/D+/ZdMOr02Eez7L6V4eu2Sv7/vxr/YC37vrv52Iv/+obiX5YQS2uaDf5xKWsGRgf/sZ75bfMFttvd/Zdq2F09H6s/QSoxnyPd3I/MdQNv2lxJCvuGU0uXuRjMs6Sxpjk/xckrgU1s5JfEp9X7/kNGnGik3W76HppHuLVLhw6iMyEag+t9Uxv9UUvlh4uffUC38BeG8v5l4ZCWw/GH5828Ig73gXu+/S0D56Nu+e/gMN4LVq4uS7w/SEfPljmt8ufH9cjj6ln+Uz8TxcPXKBe8fciLr3mG9BLebqqQD3T2Xp11ZDr+Vn+UBAZVuPIC1B3DTA6i3KfGbVCXL8bMl3HVXplRZabOhKA2KLlElcZB4WVZCVRJROCjbXu8miCJyGXlVWFegkUrw3wzPIXAnSKvlEEzUNWxG2pNlZash7EThWakFEpwoIit7udtsAAihXqNzcNzGRJR8TasELomSqxR+/AP9eTtyx4Q2yePsZ+7G6XXYUPtxfGkItHVjx/p464OsjREey7jD441D7z+NNx7iebzxkM7jjUcYlT9M2MvoMKE9Lnj8EZ+vim2Yx639Nvgjtnxkx6eOcurAp/Jw30lESZZTAZ/KRYGeUcetwUVKeQqB7t+kPsTL7x8w6Opv13Sn0LzCyqUOV2NK5dTWPo3Lk0KRcHlSroU+a8AMWgKkM2hUYwa1sU9Myo2JSYSbFhWcnVtUsLjMoMwvMygLywzK0mkGLZ2ezqAwUNoMGsS0EzkCjf/STja9VkaYlTEsS8PY7bM0O9sJd4udnGuA26UG+LHUAN9IDUB4uSjbnds5PtpKMOJ2pI2apRGXE6ONFmuTI6xTaxwPfpab4Df9LBfXnosrmJjFZaM1fBzPOM7FlXwprmT3xY2rkwfcCmT+h+6CplidkiPKNOAc8VTa/B+yr3EV1ZA8tiCuDcPKtCCud0kUZEHMEgVZ0EaVYcDcOhxcsUeYOIvnivmcfXgujMPmudthu+eKvXtu2E9GBJcSUymDbCrdVPLtDhzItEIwIlqzyAqnRRVlWCG3acPPKcWSpcrNZrBSnqPqc6hSngM/qOUWZdgn/D1js61tO/RMtMn109AGRs4JbQTuAqOaj85OiL9y3Vf+yvLkr+bHtSkOim+I/vLllf7y5Yj+rDOoELUXOlUra8dK6YVOnxCpKLkXutYomii5F7rKJxu9Jkfp9koUNrcXNDQM7jCJIg6iMIQoKElM3znjQ4MMsRLF1/gQ9QoC20oU5swGlSAWbNjhGXvzhRM+8AUfYhr4QCGDkgS7JwlKDjBhruQQBzmc+OIriMjefAhLpmyYsc2+GBSCCWcvDKrABJmxGzFc+iZbycF/QA7+iRy2P0EOZltLPsnBHVdexRZ8OhavqjBBK2EblbAQw34iBmMfiWG8duooHohBrsTA1/divb4Xi0t4gLD8o7PHK5BZnF34Nay0hCUvXtdXk89IQLtMOHcZweToMmbizXjPAW/5d6/rZkyFxlJ7N+M90ng85YLxW6KgKZdFoqAp19Br+pSbfWdHyvCdMOzdbsNTQvMUGPRnZ/PT2QJ1to35jZRxgArYiicKAhVB62VmCpJxSGlOW40bW6QfFhlIigL7oB8+GIgPqoirBPugisMhDYEGzGmGQAM0106U+c5tJjTAzHHzbl+Uy3f7ogzwhL81URB4GoMUDJ6YY42luY8JkebEbmYjymA36Eu4ekZf8rMvqdGXPEFFADWLox/YB8MwxlJN2+uAH5MJ0mCCHTHBD8PNRZahJQvYygT4BeAMBJkROhB8N+F4yivs74UV7EesYNZsw7ZmG44cSWoWL+pkSjGis8MnwCAeUw8GpyC+7yUDhVMRcuWCZ8boQHGZnfDPYHGIQAFDyy3dA4YQu7nwswvACKvNsq96RAENbBGpNMUNVWgvf58qtCxNd5OPgOLuMzljH/IR+3sBDfsRaJg1S7FmujO00HpRa73EUS/q99P+msncPyXFmtEN2DZoS+oxQUixJGVy1LHdUqnc19Q1KQFEjNyKEYaQ0pcMpK4TKIk9JFC017+fQNGylMlcY5YQZuaL8voDwiy6OhLfH5CX5Pc5lfAlblXHucEt7bffxy0NE3B1mTKJkLRDOIgy7A7+ptcM/4a/I1GG52vBFVYQJ2xHvyZ3NgRDmvfEUVMQDLHGFqXPY0hMusNZHnDZZb+BORRSSRFfM429TZ8lNkNWiNpM0xWSoEoMPwgvrEDcnNxvsAo86SDKTJLx7vZNGeTDbWevqsw8FDcsYmUmhuBvhmqbLKwkpkfckhLHWPYpUqk7sPhyPxX6/eAIJ3M6i+SLoLdiGob7WSSV+4F3TU7WPYjKyaUe2yE75qGl9AxV5VEwiPZBUUQZtA/dPBFl0D7fej6sKfOtIul9hH+0rmRZHRoGX1NWzlzpZDbgisKgHKNFd7vIRPXaqAReem89Ysc4spjKNXcOX1fovlxXj9gxjiwm/jap93FFXxh6mcsgyUaQo8xVaNtCWXnr6COyLHppGURNUWmcoops4OhxiaN4Om04erXYfLX4FZe31w6vBFbD+xZOzQqnfoXT4ymRdQLd4wy6p1yWeFoKG6f0gqY142XOebFOpZ1GzxQaVwoNa6bLnzNdnVXNyqpnIAU6KPn7m1UyIQVy0n1dJaPcebnP4GqVLK30xdZclyNO2rro3RKWNQO/VHxCRrMio1uR8XjKTVH8pMhoqf07+bSwJdjgue1QD2kq9bSwddqrIdZkljylvGiE7h6lIMJB4ptKDyiVVpSKa9BhDXpdMZX8S6py5eGKBq1n0BNkPdyK1Xc+w1JD1VCHHUwve2Uo7lT3+zwgCPX4AyuTeoCHiIKWYZxS5G6DrmS03ZByvbdkQi4NBFmulHboOREUTJ+8BecbknLs3czgrseQPL1rKt4fBNJR4gnYwhJl8Bk8LhBlMh1IqAzIOkFIWJnWCePbYmVatFZ9maspEwWUJs9BKCCcJspAAahvTWp+Eq9ItIUHJbcpsCuYtGAO6viaqxCBG0xrAisT3DbGyTUTAzcmNqLMBNjYQ9SUAZVwDSMKAtsgkYLBFlqI4babnAyCIa3aqTuPKXO8+IvHV36DmgjABwL4+30vi9/fvjPhHS4j/dSc/cHOHxJMN1kljrNK33dl1kUpnGCi7n25t+XKxUsaqqSuv3TzNNz8IZF0b+GXi1UwxcIrZskZ3Fi4TiNdo2S43+ey2Ha6fetFO1roq65M9wat03YRh2S3+23c/VKZuV8lOmVsnHEPuyizzw1zi7+2i3K7Tw5ceK8+JQekXunAvP8jE/Qy8RN09Sof+qdGnOq/GarCva/1Wd96vhfE5PLBMarFPno+v6qWxfPrZpPLapH8E6O/2pKSzg14PBo9+5dGD1bZs/Wur7T8XZ5SDVjLyJBOrEUnogw7akFW5SCmrZWYt3PYX2HSjkQZngwhaqSQEFN9De1zeO4a0O45a1HWXpKUWNmzM+/2NO+bg8ADmIXA5cJ2LkhdYDvvHtfqAtn5tGZDtk7A9BlHcAk7WZs4utIKnEuQuyx84JAaF8uPhBA2OuPw/leML8ZRC5wcZRxOPGm1U2Wu6aWDxj43n6Z9NkbEwAHldUSZabk6YXeFlncv5VWkvLwnceBpJA6USIo9o1IVtNk29b1HLfaZloopEGXuMEq7xLEjtI3pwApKAqZdk/LOxcKYLFE6DucZsOSXuM9bY+KEDjGgIzxsjVn2v/X9L/yUQXhAkK+2xlxkFOyaUdg/3Vx7s0umosWXmQW+LnrpGyZZNszIq40z8f0Ji/hf3zijVZmTb9e14ljX2px6WNdK6+5bv+YV3PtjVnHpfolrk39gyy2UPN1vnIGSzxdrmx42zlwkJ+yanNh/YdctvHo9JCfAiuc21Mn+F8kJ/lFyQn703RJ9jjA+rfOkmZ1yF8mJJdL0/gRUwq9sq0me3a/zbFL+/joPF3G8p3Lyrq4BGoky3+8VD0jBeWLNUt9YkgdDSzN7drOxpHymprA9wylsIYwfj4iYH3DqhEfMD/C3JQHP5IJi426MUoKzlihz4WUuTFVlLtYoFrCCllcEJ8p0RYiIIYW+V0eJw0brT2q89NcCIahgadyOGCb8fWAF5ZwUU0SZu2tE1ESZ+Q0+FkGqgjawjORCVjpu5Pasyz9okQRO4uUkLSzHLYg4T4adKChtwzVRZtqmzjdTQfu1XEJKD9GzGeIgCM/u9muV6NuKk2dkxSkP0II0MO4MSW/IQRrxg6/1fEQcF/tyI1tXNtLt13o+2Z9rP9pz499XW3XP2RDxyZd+rnbtfsYj7H37VaD7HMnFt4JuN9u4y68CXcGIdU+LHVrOL1VuX38l6DMoudrYu9oJC2c78U98Ev8En9j9YQuO1PxxC84nG3ztR/tu3PuLvb7wTinvszgQqZ3NZh6yOOr9yReG+K+iizi3YLjfBbPJ9Ad2wSiXHuhIbqg7q4/SOBffLLrNbvkvvk6UayA+IJFif2CncZ38VfEFPyf/MA8j3XmA32yzhpwEHHT4sUvUnrxHyrCn2OypoVQPo6NUGEeRfKEl7WKEEK62EYwbNd4K4ygS8hrLLTVgtIfBmQ0riLzkWLeohcSZm0iUmbkRY09GVZCju3k3SbBHoiqTJJcikiQKxtiNKHN/tPMOKaMBxn5utyV8JQYzOxrV7pTmlDVIwksrc/dPVRBQ2o0oA0KhMXL1/R/gX5W1###4832:XlxV32DM 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12c8eNq9W0uy5CoO3cxbAH9wZtS8V1ERNoaIN+ka1PBF7b2FMCAZO29mV3VP7iV8EpAEQscSVv98s2bTD6/X5/dg/PPXT2vW8BAPVZB1e3irn9/Ln18/zRZXgugU8/ObzDE+wqYAlznIiuNDI2PpuocCrVH2rqFO5/dYELc5ihgLSLJFEJlXilhREAeIknKnIuJo8AdG21ykCI5mbEUWplYZDf4UhVVmiCyIrKZYGaIKAqr+2uTmi9gyPtxDiX/+rbPLj2VN5vmXzjY9bMrPv4yRGWwjnn+DdPBrgFwAuyTxhEfGkkd7Lo+soL+S+EjSRxofKdpxx0eaPkrP5w+/e3gE0L4c/yMdaCm9EpUgBXzk6COHjzx9FPFRqGOmhUIeINhD5FFW5RGTN2t8tNOORffgAv1V0T14qnu2+IiNBXb8EZaqaFhF/b9RW+RUem2GPsLpNqp73vAR1T3v+IhoowQKtTE5wRywF2zZQOWn4p+6/KCUeZZN4R6wVyVuivxwzuxtV6j9tCuUSOddocR+3hVK5POuUFKcd4US23lXKAGi/ig+W6xUNjCIOQm9D6HFhdD6vJWVXCahZZiElm4WeutCnyWV/iSpD5Ok2XVJYT0PSTVsriapPkuqzCSpspOkanI6pSanU8pN5lXqLLQ/C62EGkKnIfTahV4mofMktBaz0HEWOk1CazkLvZ/3RPFLw4UeGzn2M01vMJRIdfEEdodxjiMHTqDQreDmAe2wwthZ8Z0B4URGVy4hphgYz2rwW0RCYogqCAY0nRxDdEFKVNJpVQQ5AlqRGUTBmGH3hkOryFPClkfIj0HdAcFRVOZTMrL5RJnPVmTpyBHR4ChE6Z1gSNHLBURkZkjRy8uql2FI0curqpcmCNMrl/ipgibCF/NC11UgRATxBy/YdO1EjYWhFQ7WqpbsZko0uAOQKTKCOyArRUZwt8azPhiOU2UmUjOkhOOERtJuZ0ghHhDjiikcnaeZAlazLjGcATs14uBBSvlIEdS3BP+ib7cReDChH4OYVGTQD0AcRSj9sJIhg37oXTGk0Y+ib2RI52ig70YQpi8uvRSebOm69MARKqcJvnEauQ9OYxungXg7OM0PLw+GwbmNnLjNwVrEzFrkzIDUicicuE2hTsBt1jc5zdo5zURkXCcyjMBUTgNzZFnpBJOoUhXGXiqh4exFzOxFdfYyUZYfQJ8P6mJmUmJn6uJODITzlEZd8MjcrMZJ78jJsqwtEFlwiHtyMgciOQeig3bImcKoExM5k5PEAhEIXSxhudBbE3pdVY+ei+xC54mczCFfjpB/FkseETw1GXbxgiCtdhAk2HkfEaSVySBnoqRObOiwFo/VoWwDd8OKFISiQzyjFsaKOAWSM5uwM5tQMwUyN2It61kswntUSFdiLZNYcRLr4D3yRF/OYqU7a4UXREQt4UMiAgPado6GwOI/BI6VQDy6+t4L7ERiKI2uBRmkAZCVIZ3yOLHyPp3yAOIZ0ikPSNBpEmwgQkEAURQh8a56QnkNLi2MKRAz6vt2cKRTCzegdmcajk3XeQ2IuDGk8xpAMkM6r4FjQTdBQNhDEOkHpdEIGYzJVVrCRqzCc7b/BjQ8fkN4SY36/Tdgn+M3hKHomIk9KEOph+3orXpvwlW86UqYokQCKMtqTV+747Ixa6aygqpKKIkRKPtQ3lNksA8To6XIYB9OqJ0hnX1AH82Qzj4AYRIM9rFu1TBIvprmGrmFM7iL1SM+lB/cwnVuIb/mFnua8yb7q7zJRCgyOR189eU7NuHfypAszxfEgrKJI8Ibf8EqLnIilS98ySrkYBXwP9b/IVKWAf/TKUFyQykmHrHN+Y7ywrioarAFtw6cisqulWsIl8+nrEzt8FdiGWEbAl0L23HiGn5OhLiZa6w8XAt8BbDXPAfmHkmYnBnPuUuvTLRlvw4tDk/U08QttABTb/OqvWcnIEqR5doO21dyWNKmzKyoW5ztug3dxJVdZzqkZiqi51yNOdvVz+rtfe4QL+yKNIiPujxfcJ1ruwYxT5y6Xc2w60igyA/tWo9SzqHM8186+7GAnUjpfbAE1YxLbSU3nV5ysk5+3L694GQXaSnzFifTdzt0do0cZgVV6i942n5kSdA8n6egtG/pOToDI1Pad8fxJt3mlwbFXxpAzQsZdFfTDjW7k0Dc/ExNI17RyFV8ms+qJ2YJpaWFZOAbnihHScUJ0/GdBmEIqJ4hPXBDn/UgIWXMSmHqb3rYh99oMi+tkzhjKMLoRU866EQJIk2i6MTyWp0qHcjIa9Vzpc7jOal0pg1XzoCjjpSRAQrfqGjxXVq2Er3yU1rNktC/W3LrVondKp4SO+msJTIRYge9F4Z0OteITRuXVraEpQipbAmXyNpRHgvDtRRh2QW0hmbNSLPpTEn94X0NabwR9uqRx3Qm9kHzMShE8SrKTqBiK0D2OmhfVCN4htNYzSTpLx5mx31lD/HBpdoi1BYcRK2VsfUd2MopI2nE+Z0pscnIm5HNDBnJYD3eZXRiSVPR2XNpdYfb2zapR3jryUxZXmikyYkq6GNTsLbKQEcrY+t7+YNL4Lqd92MJgJlhWRXrG23IctocY7Zm6dCauTa/419g3FEcjBu2Q3NzpOIHRz+oeN21FaimwXeqZp/K0Tcsd8odzlCZBkf3naOrN/J/c20zybt8R6Pvas4WXhQ036Xpy33Sb52TfvE5FTJdKSuiCreMXc2M3b5VxRRzFVPfVjGnlGDqKcEpD5jnPGCkeUAj5Ks84GZHHvDDImW+TWeJbU5nia8qk9agq9wl3mBDdi6R1heJt/kt4iChl4m3dZZ0rqEWysqySpjDuKlMZimHScNcmJxon5lpn3urGqlmamRPgmIO6bYamYZJ4eVrqkZOkt6vuJ5r0Wq/S8ktr2qDaf88Jdera9CiAUsnPyCSWFmOAHlsuYaT0GrNyLEFlmOzxvM+Pfqw3OA5lycowvJ/bDRadxvkCgSmofE4sDFfNC7kVLVyIUZINqrjq+NHLJ1mA0NIaXFbGTJom7YLQ2j+MFKE0sMR3Nt1nXbXqJPYsgKUBNqcNwKRkp6JG0c6F3NCCIaMxFzOliHjLpHyC0VYKlBRhCQSjeiIkIy/gXCRQCQ35oQUDCH5tC0xpFN5UGhhSCfwJNeHCKk0jvwgIp3Al5MVQ4aEXQR/RoAPPcDr+wD/oqp3m267qN/J+1Ae51DuPgrly/PqTtIplPNIzKO6fCsPZ3tUP4fyUh4k1bz363Q0isMyRX8fqpV2IyMxAuAI1S/qdLeprYuKXD4FZcwg3wRlkKmnuUx4VQ3b5qDsPgrKy/OL60Kwydf7oKy07bHOqvTiutCcLFP6rbyMu73YVIptXNKL2zFqSLr1dJHmd4Q+qILRwDzm/mlVfzktUvDaUWQIiYWbJ0g99uprEzzol0a39brOcyAjyJhx83NbWWAy20qQY6IazSAcMul61IUdu7DhyOWa2CeCXcyijImGQCTKjBLagYwCjhJMVxrONiYCKaGZXoApzk3CwuHsDaGxBCZSVARayVKBIiS1oMTGxB6BTuTIEFK1MpoJ1yOTknqhyEgGgQSCIiP+WBVZnxGzTBz3h6Mnce7X5hQuEXCYRxxxaelxybDLtG9egK3lnZvTXz9f3O1oR/6bd1BbyWUz+1J01zcvWWnvL1l+k7wI8dntzcNe+rrooEZqXLGSw02Gs4zn04s7lsGPo8jLF4emfb64YHCb2v3qNuVPMPyxd1FQclS4nh3CFj0qjlwUQmAtkm0CzQQdbvipzI08HRP1QwT6bAzpJxwgliH9hDMt1/INN0bl51WYrQrfDiZssQvz2QU66DhkdG7MDwcl3gqDBIa0QwbXt3RKD/UgiZ21+5d9o/g6bgC9cZuL3FT/5ApX/Cib4+/vosOWAqXRLe9SHiEMb/TxRcpjv1P86r4TuYz9xSWnY03u8hzB+yufe4tSvchz+Ptr1yy58dP1NwxssQR9doZAJGoC4hky8uTZJYaM3Hr2fLSRj8/tm42KjDAHB8JOkREaj0VHJESeWyduHyIrhxAXRmQUU8jJg8gowBAPRaSHdHqIhMg+TyGHSIgkav7apJIGI6B5bMNDt+6hjnnoHujHHeN6gdI3VwHYFYD7Cr6sd5dvitnSpd8vZsMU+31dV7r8+3VdWenRTcFTevEHCp5K6/tio/Tyt4uNP6USLSVUTMbKYLnfDC4QVm1g7Uun/tEULiWrH5WPsgaEnfDmb4tDtnWqtQac9Giq0JugN6tAwLAtp1UwWkGqW7ohrOyU964bjF0VwJwWRG1DZKnVIlSytsqva6tMRmL6uISO0tICS8Iiax8S6zM4ZG2VIWurDNlrNrDIctezT8buk/7/45MSY+WdT4Y/4ZNy3174ZPgTPikxht/55PInfFLine07n1z+hE/KxujQZDc+WSDmk5vtyHrnkwW69knsVL0PJz2aYM/WBL3vfLJg1Cfrlm7IjU+Wsa99EqVE/0Mlayu51iqTEZ+UvfqP0jKf9BsdEv0Ph6ytMmRtlSGJT5qM39DIrRQpyUcKe/fKcMll/8e5y5ffHrz6njK8/Azh67fWi5zl1feU4q3vKdX7lch9/jghPr8uSl5+RAmmhnVVfro7Nch6Dj3BaCP/TuHPJzuPPXbHzHPQPdlp9//26v+rbyPD218B+NW/eG8vWb8mqfOfvbfrt76NVG99G2meJ6HDi2pk+VDxQuj7amSaJZ1eSK8Kk1cfROazpK9qlEqrD2uUJrZsHxqB3uHx7bN7bB21vDL/cYfHr67jvLop13xQH3QiepnLr2M6zwctt1n+A3jueE8=###4604:XlxV32DM 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11e4eNqtW0my5CoSvMw/ADNSptVVygyEMOtNv8VfltXdO5gjhKRUva7NG+SJCEb3cEiurXyxl/j1g1u3vhQPy/vn4tj7979cr7FDy8tKB4iXCTHbghGlE6IAUZEzjGiWEF0Q8jbNE2IyIjVBREJsQrZtIBYQCYgVuQxzBYH3rqWM3ZdSjySITMhaEFxG7lsEKLjUIBUVrig3VdnSVIuR3FRdQ/AkuNRUHUpFgSCpqaYEJyJBUlMtz/UsvgUn6tvSj/w2ivCE8PI2TpDUCTU2aCBGUidoWcpYhNRO4LmpznPcc6kTbNjyTLAMI6kT7K5zx4Wd9HYKezeljCVICnuHen57FXWC+PLSL+5+/VdGE1+r2/f3PzLq/aXj+v5HKZgvi2fvL4gOPv3+D7y8/k5hwkfNkuZreKdHokJp7KFIcOX/3aCPwixIjyx+tOVHC3605EcrfuTgEcwH9CjK9ChX2x/p/CjggjE9Mvj1kaVHFjchivyIvIu/31/LWhoOy7H89nJ8RDCeSnmFS+XqvMaPfH6EuyFu+RFpzZ4fkTihX9NIpSrTC9mvMjjQKPVOQ2ZePK5lyOLLKKnamIlwMVaC+ZOxSlMw/dHnxaG20Gtz/KQ2yVptrRaeh5lUzEfF/VEeZo17lMMwo3C4zX1kSTjRtHCE3Ho4xvZwJLxVOvRWkaYFLBn8yLyPQQs+BS3EFLRQU9BCHoNejkELJkbQ4Szo9Ri05FPQks1Bb3PQYQ46zkHvx6DTclM0aD2C3nukG7yK7WUCsVgnUCjrJJFXfiGhB6gY7X9cu0iQvmcCBwSC9H0Wb38ZQXuz6HTnj6RmCNJJzTBhCZJIzSd2qGPXkLw3/8h9A00u+HhnIrBgoehqCUnkWXtBOZ5QDgRiCNLZtc78hpBAYukQhQKhosE53DokGiwnCBENnPQIEg1aop4nbKVtZyttCfOoEAnSmCeVcQRBqoEFgiDVoC1CDqrB4Q5EqsE2/i0IUQ076fSmGtIqyIX4DqtXsEGLsdOiO6VFvHD5zo4LtzEkw5+adhse9uPC5bs8Llwe8loOG/6UzXypZ1b9xL3uEffCXvllY+GMAweLiYML4RIOLrRMOZh3Dp6It9DzVqAl/wYi3stvX8OgFLvNFOtnig2dYt9fax5p2LGEzkIFqM+sE9cgonWxbduaW0K0ZNtm+7RtV87F2zaL07bNtpkg2bRts/CmfK32OejB1+vaucYFwtckaG6noPkc9Bmru0esbg5co+MsMvYatNh8i1mEvtyADdGc8HUO5LnwpfgmyVjmfvE3wiHCjn3SL7NwULNw4DMHm5mD5SSzsKagneGmzohL7wzXOwP2lRao/tPOSJ+VlNvZ6Iyl1SGt73UsUzOXuZm2tGXvFZ2ICDEqMq0iK6jyoW+dV4LY3ydyNTFrWs0yMQO0MfHMjxwEkgHcrj0/UivJbaPqjAOlUzveP2FfKJBDhQrlQBfnjDiupc48j1M3J2aGzs5//sw/Kf8kDIYlKYUkIpQf6SRM08bt8KlSwxAZGcc5t+ca1Q1zoBWEv36mH7lPFCnd1UYdnoH0dJm7PWAEkyXXpExXNdwLUgZT7xpRvyIxAZ2y9U6JtVOAWVJFgUnctMW3psFfP4EGcpixCwHT0mOZe9usG0Zyeqz0IXc360E5coLgrD4SpCtUHaMmCMrqzYoQopO8GDNwJ1k9ZNwYGVl9XbMdGdoKuysZ6doKwhYE6doKZpQjyNBWnuN6+lyMdS66rVSW9XFbQTJrpWKXgFaCbYp3rQTs3bSSR1qpbqxtN53UkJzVUJzV0MSHWUZ92Zp92LDW39usaPSZHbHNksjMkmi9sCPq/n4QO/JO7JwYDk/EzifXwc+uQ5wlUXjkOqQ+6aqIWydvVFFKNudkdqiii/FuyoYflM1h12f7rH/igT2dutE/iTdOcu1Z/yzvy0j9LHrMLHrWT1YGZKMpSnOlSJau1HRURJGchlUsjSvNcWJW0F7LG8Wl5lB/Q3OIOxMkLl2AWR3+yASp6oDNvgifBcMnEyQcZ5Oe9Qua7LFH6h+aIGPnFwuREYLLFUFElnBBkO5OQJlAkE6sgCiCIPnjRPe7dXUsYMMcSiZDMCGIfFFbO1/IExfzvjWCIEhfCFoG6xaFkMYyUGnVVJ5rFAlSM8OULzFiGVUUQy80dILgivTGcEAA4RjBDggbJwbqQLg7QRDhSkGQTriGyYUgnXDrjtWQ1hUwNMVhgnfiriJSbJwbSHLawY1bcW3ocECP7kvI2YFCrrwYSECgJcRxICVpiLE0ziAcW3vGLRjBMow5UubkcKUiJzKsIsgo3FeMdCGYZIlLIwyLlMoS3mXJNsuSE+vmwWHHjUlTZclCj0KoLFkfmTZmVihLVyiTLLHzKQmbT0n47NCIWbTISbQUa+c7oqUJjXvR0qTNhWi5Vyoq5gl96d/4zmrKs0f+zYMzlDun5qhUxJzn781gF2FwbpA9uv0POdeEOzMIttruYJkbMbQ+MoNm06M6P2emB7cHMWTVnT3j7clYndgzYlYHcrZn1KwO9KwO+JVU8jdSKei/IZXyIruUSl6fGI+zVCry5qNU4ndS6V4fpQ25axar6BGH7aIAWkP8kiglgqjQsQTposWwbSNIl0CDjCsyDiqQLyNc92Vg+KiwiUKSNiD5Mo4zrKLyRRiEdPniqXxpVVdbJsFYyAxSTTHNQqYXL9ZHKo6tD7/iduObII5jhBzqDOsjUEmDDI5w8BA4Qcb5zObp29D5jNkRQs5nXCQzBptExmEE6xxLRwjpnBVXhHWO8116Ag1gZ8gOXyYhWJKYiBHiDJG3YUkyzJeMoPseJhBkOENeaIT02dPtPuO6EhPNKQTtULpvwQ3u8u231zLPJwhHwo+hc0TXOYEcVZ1rkBtrZH1kjWyn1sjXUgn0szWiZ2uEXdzF+OSG3Fggk+/hz29baNjRrylUJJZoxLSF7/kJ6yM/wX/2E9aTHH5Q6BbPbmrIJz7CHE69B3Fz6aFOxwsSE8LZs467y/dvkvwpvO3D9YZ/a3iwkPJfmJ80bx5shhDXaJiwBOnMBYgnyEi3HX3b2I2H913LDFfchICRsbfjSxQw3OT23SoQUhuk9OGuRC409k+1R4KMpF6vhiCdFaGplRDy2kCEAB23EaQTQl1FDcGEAK9zpNC4GWCCxAh2ydsFwIKgbd9QpDNcmpCiqCqgxLE7yr477nh3pFvLkztd29XW0jakeWtpAV2sEG1uV8iTu0DhcoVI/nmFNOLPfx1WyIYgukI4QfAKcQQZK8S0uyEVGevABYERtHZMn1AZ6Ssk5fv5gioPr7TrjZFWfaTj9THE4TIGm88a+Jzni/nKxvF+xkXqP+X76/vJiYR9fkHy04nExLX8jzJ6Nc/zT2cOt9cwiDuAMvl8fniZyYf1NpOfrl/E+frFPpMwm48ftk/XL7iV9iap39nfSOrzyeZlUh/sWXZ4NdOb/Ph0wmG/cVlTxcyxlyccYVzWFOyPTjgmvpcXuXo2Xa9y9Z3/jVw9J1vmKlcP/e6K3nayidPNmz86w7i9B4HzfpqjD47fqCftBEFQArcGhBwu2PWEp+uZ4sEimdH1TJEZeryuq6NqEww90xVVTb5HFttVWLkJ6TaNwx66QHnZy8CO0RIrWJItsdq61Q4PcWKF01woSvK4cZMgI8jc3kj/4cP6kWiv29Vh/boRueOZxvXgjNUajOCMdeS/ObbTjDUjKGMdo+745U2W1D/VMZHLwTHxUqCh6d28nLgfqe+L+5Fg7H6Mr5Gk91+4H6l4cT9SceR+eGZQI4iqHt9xcNQPQmaV4/Ri8LCA3MGRcowgTemAngR2SzpjfSn4MXSGrjrDMPb5amjYH10NPZEe/OnV0M+nDU1yPLkMarrOwDn9/yEyri5w7rNyiLNy2K6+I+H8nWDYZb/gtssb6397dHVz1g4sfuPqppb+1mpA5xW3VsP68bzi7JKmOWVQDarumsJBKegzevuLFF5Xmb5IkvjoFMMpv9KK5+u1ctZ3NV+6SYrG6XMODOcqYhcE6bsL/G8IgnOiQJCRRwnGEEKSrzIkOcVlnCb6/dtiGcLcbLaIkcHNkMsFgnRuRm5HQbAFQN+GuHnvuZynmbnlO0YGJeLM0BMHAGeT/spqKMiwGsoqagiWLvis33nMifi2hPOYR/ENC+cx9+L7Gs7Tu4d9KuTgkEAp+1Irg+8EEiXksczAlxecR9IkbRnZy+Zb4qBtcJDpHMQffD1BzhwUv8lBIcwctL+v0t4j8RxPsRHF0CNs/uhLBmwioDPWkTPFfLpJt13byOgbBV4rtV2zEGj+ng1qc/MFAs5mFgrfZCE228iJ5PCGq9R6w0KSjft93l2nl0fqufuOoZbLzeGvEGsnGbW4m8Nf+ehuvng/i2n+8gc25xZ1FtNsX7MnZ7A3Pt3FPfcaXt5izPE6+sYRhEhlfLks9zjatusINARzCuzwuCbkRWsxXteuWBcNDmUsCaGzJCCKIJ0lBReCIIMlhdA47MFq8DaCIFaDsSJIZzWoh5YZrKZUTZnyGsBso1oKXZHBNqp9LSAjxNgWbMEV4e+vR4FfN0gy09r/AFGHi9I=###4852:XlxV32DM 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12dceNrNm02S5CoOgC/zDsC/cWb0fs4wi44AYyJmM73oZUfdfcSfkGynq6qr38SrRRZppbEQIH0IIx7q1zdrzPpYrHh+X3b3fPtpZZYPQSSySJYiUVKgZAOJAgl8vP2UURsm0UWiyz3l+5TofcsgkqU6GaKnD9IBJGlrN0VaXZXAR5UkKjEWJPDx9tNsm2cqlAbBR71nZZLSIPh4e4syi6q3fXj4+PVfnV1+rCEvz790tvvDCfX8yxiZHz6K5w/QG379/A/o0v4b2/7bYhe4xfmHkbt+lkuSXEq5XlL0V6Je0vSSfMIzkm91pqJ0+d6flTb607XcvVt6KdRLjl7a6qWFXvL1kqeXlnpppZdc0SSr+mSvdNXE99Z6m8hPs4W7vWtK+4W2Opcm+oW1OtdLW/u131rF696+B9G+x/7gSK2TU7k1Gnppr5eoFfJWLxErKCHrJWqFHOslaoUMmv1YVTP2qlL9b5StF6LVuTy41CF+tbEBjTHPMmLcQ6nURkx+OOPDGDIqvTNUYD4dh4oS6ThUlNiPQ0WJom2ZTKXSMo5lKVmunu3q2ZiHdipp1G6nPRG7xavlfxi5aWaAt2iV388WSP0RMmg7nmGFHc/QYlgAW1wHrrH0Uh243C7xZBfpT3aRy8ku0h3sosTZLvuwyyamXbDXtPyUXUzez4/IbowMIdV4hpM7PkMfW6wctvjYTKVOzVTy2Ex51sFjMyU2E7zOUMF+svujOHa/Au84JoAwFxNAr8fuV/up+1U+db9Kp+7X8tT9ajvZBcbbwS7qaBclNNpFTbs41Dl8xi4/wZX0yFfHGvzy+R0cZg1vyTVJHSI1IIHrLBK3eyaBgAQetAUx20NVmW4tjoKvL7G3Tr8h6XE0haqCUESFoiSIconLEL8Sqw9juRPaMUmJ5XvRQalloZIZlkEiqaQG370HX81qmzTRHGeRlBKL/1nIoTdYvuudfLOqIqJqVQiIRQexOVIfYRAnxMokk0GUslQyocEqwSQEGtQwapcMaCgSTyUTTkBrjx2hmtYQSap9ctHNjqbC8Hn23hpFOYuqFb/Xz9pV44FlEtaGQeyqxtgVk5TBFxuqRUEkzexFoWp2Q7RsZofA1wzlaH3FUBBxW6MX9qQymGM3oWGSMphj6XqThCaNhsnU2zxKEkuqlr4DEDQzOlRQ9ikVRFNdE0lTHeihPKy54TGneoNbJ8sYqR7LNvToJYklVUvfy0epMkQ2TYsei6wSqZmkqLGoZo2VWqMMDsCYypp7Fg/5gKftD7VO1vTImpqw5oEp034KD8P3FURc+n+GjkcYdAiDJwL0SIAF+2T/z/DvgH0N5N7DPupKw4H5lv4/XTHga6o7oVxClAN+k60NLzlO5qW6UQ4E6vkvnRfEpW0fcUFPLIBoc4hSYmnBZu/BxtSmmGtEBA85Kl1UZIT4olcZ3akbupvq/j7dgV22s13iwS7pyi75BG/yYJfgz3ZJaJf1wi6VGy9hqGPghYnkHeilr4MemMieTJTNwUTbhYm0OploO5iornTMNUOazV2ZSH+AF5mJzFrmT+YPWZ7/Bv3B7/0CJdJDmqV8wFJaGl8+koaPtXyAk6lVvDWtcvubSGtwksNk7pM9NP38Nv53p7Ct/X8YSmIhjsI2Cn0Ky+7doLCOQhiFiMNA3IHw9nUQNqJ6EMkfMft6Ac8pcFQu4jhklBCHIROvhow/MbE/Dhl3HDKTxw0Exoshs74cMvuLWSXyHT/Hr/MzC85qBGKJIVlimBaZBmdpc88r1UFZBk6BXlnxerDKEJW71qWJDnclYB9ZwLJPjyGCIVxuSu1Rkt9Uibgh7GIHkECpdM9QurFWm9j1VihVKmm1lMHbKpCkArZI0IrcShYJ0qqFSZBLICpPbJZsJSCdtLR521yndNdfVdhmGyS2IQyqLSXehrVVEEkFBP7hoZrcSpYf0sqNSXD5AW1AxpOKrwps0KwNcqwKRlivKuyzDQrbsCa8Mx3a0BYcSyIVkIUAPFSRW8lCANogmQSXIgz3FYK9nIwvJ/mLzHFfOmtYK8NYRYBp5oJJcPylrK0GV0skbInULTJjbae5SdfB2uDnMpUE+fxWfR94t2owNzudLQhA/zlwHV0QwMANTILLleEoe22j/0Se84hOzuLwn62S2pXVNFiByGxRE7ZmzroYHF2lq8B2AaywxzhsgvawyvRjkjXB0gWw/BqNGHAPcfMh42MFwp9wvyLcGw7376SCS8J4cD3h+RdpW4T2F7CeNcL6AdIZt6s/xu1HWP8MoZt6h36F0Ziyc4knWt9NmSaeGzJVI/0CS2O6eI4WNylIHjjD8i4rJv8hVlTiGPjXG1aM4ZYVD4zIGMC8wsbSMftrbEyFE9dChzBOoVSxMZRS+QpoVqv4DDb+H3Ex3eDi7KDfx0WZW+S5RcC5e3CJgIfuDzfcF5cPcd+LJdR2A3tTxy8kS53dMQCsjGnyigEcpg7jIDuRLTBwMZhuKyUM6gHBxKqN/IBkU6HSyCQTP5xd2eMmYzTH1O5ZDo/rXBbJD0gCEir1TDI3Tq1KzCKT5VpHD0Uw5AUMeRmZJjemacyzjZhp1TR2YNHWOckkM0LndSV18qiemV0QFGroG1SysdALD9LspnBIiOp6U5pYtB1YqPvRPiywjWlywUrMx/skNPCjVqRU70QiEkb1TuxcRNcWmYvI2mLsjg8Rri36Ime0dixtNrag2TPOgGIRAndsaQKN8KURPkzsw4o77G0U8ULfF0eaWZFmVk4zgdDM2lKViaUqA9KMvUlVnjZv6sb2gXn6jvhHEpinLezlvIXtPpzAPGYt/y7kudhq/lB+cjXv5ieT+1h+0h3BId7kJ6O5zU/Sjecja6VXKbl4k7WcjfhK1tKnd7OWyd5mLQ8m2m5SlVHepioPTKgO29LXJgo3Wcup+Veylt69T6LmlkQPWe79Bj/D/qFU5TVo1gXnHWhuBSULT6aSpFzL17iXnGX5iPlRq/iHguZ6B5rmT4CmN++Dpv4EaK75BjRD/FyCcXs1Afwdc+o/wZxuAt3OmdNj8s47zpwOeQ1GFGXOPWPaQwaeYWvOo7HIhiyy5Jkn8whKngBbQGDTglTAoNQtTDLzaNkvpE6We3OWtWGC7I6p0+KiWYatxYj2oHhoQ+d03DxezWxDnNCZSQWUdJ0zTDLzaNnvpE6ae3NyYW0IlxvqcfJjmMV1Fv2BKgkUlmpPPDWqHTwVsLRiyfM0mmM1EjrOHtOZ3nCilpPqMs+TzbRplZA8mTekNjS/n3nOTPQYiwa4OPNkCPjFLBTWrVRsosylSI8hfaLgU9f51J3cyUdNM/hC1WIUPnOoSz5Q+NSniSaF23wQTQq3mD7uoiOFY+d2Cg9YWrHkD2Qe0GYrI/OwBZZbrAO7sXVkucW4oWBjNL7uKEiMxmvHVxpXdRPuUZR6yH3SeEQad+fc4gmu388i0hdJzwnFv3Or/5KbtzM3X2ULayWvsoXB32YLrzGkblq+ygsG+9m8IH3NkTxHJ2nO+4gNzMSM0o7gGN9UV3cYpv7MjnH1XTdEtomyT1w+gKSgVD6ApaBUPraybQxV/BOJrE4q8XDXRLZ5+9tEJlsfUTRzdRLdohk4gtnpkaOZPKFZ0DdotubPodnl8q2EA4zXQfBsllyZhMR4hc4X+r3E62/1Wg0ZdSuRykd4ChrDk50BP2ies5KZVT0jrKsvv5YcSHlUiaPjboyovbfh7lriyZWFVXyCgXETDffN6wwLjIDXmlTf4xS+/6BO8xYxWy1jTxUDGJR4BS1iemZJthttiIRFTJstF9GI6biIRsyFizBimn3fqQXo9vuEF2gAhQUnA+uoyZ2O7PlKxrd2bk5XyUzUNm88JNxQvdLEHjdR3cmdqYjgb/fx7usYDfuBK1FEsTFsOwvdtdIWujML3UGP0G2NWEroNrDEkeR8yYahO7LzJZgH64cG+AEP/6EDHrfZMXp+ZB7oMMtpG5Al69r+4av3/+62FCXlg+Hr8XiHPZy/+EAKLerd63PO5xA3l6hJtEevNtxc6Zg64tx1lFdqx7fS6i4QCfP86IL/0NGF24QQPRlBgi8MnfV03mKeK1A7ro1NMizE8xfuzfmFe3t+4V4+P7JDqF9gQn3RXV9jgvxV5Z0BjNuuwv8I6xi7+9Q5pQbmgYN9nqsQmUc5cTgR8KmcxE+rHB4xEwt7qVpbyST4IjZ890RCX7fu7Wiilb0rbPBd4VKiryxLJ9CJpsMrR2a1RETiFSjO1ZvvaEt8T7xJMDDCd8u0Qz8OwyRRSX2T2VQzGIn3SMuOIli9JCJi5xdGYqBVV18tr9Cg5PDTXQVMw8B3xyTznITwvanVHYywkPB9HqtsporMowrwOK4iOfi4SyaZBx+1FUwyIlcZpvXl/B0cElmaJfTvG/fvl2f5lvNZPvd8ufsRzv59JbsfL5y6Pjn15sH5eyLq7NTtnVOnrr+YIrw+IQYzcR4RyvHmhNhyPiHm0GOdfGs4+9b10k31nnrhUGVwiM1mDzcO1Z4dqjw7VHN2qO7OoVK3S51RzngSVns6OcgxnSohE2oe06mSOXPNFjdW20SinC2ToB9wQggmIf5Lr0RC/ZdSA1/roOBniDYqmRPTai2ohJ4hCpFJyMTcM5MgUvbenpLpidowHRLiviCUyXrqJ8LaKs7ZvONsTnw2H07qHvcb3znm+noTUF4c58Ods7Kv9/WdM6nU652ncrTh6ztPstrhxZ6HEn/i5RqpzOvtAyXWP7B9IMfwryajCX9YK0giokf/RM4okSzDDjcpIiIn25yqrx3acVNLXkulZlHPouFrE5N8xGoNPXrWh/SQ0Izv/wCGrLuK###4544:XlxV32DM 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11a8eNq9m0mO6zgPgC/TB9A8xOirPECyLaA3fy16+fDu/msyRVqxK1UV9KIqihlroEXxI2Wpza0P9hC//+ZcyIeLYvnlAlv+/Ks2prJEVwl/OBeXUhJQklBStfTLuTXfxznjqEbFV5lFfi9V7p5Uadejyl6SUFK19Kv8+/Mnci5FvjE+1CP+/p9MJj18SGn5Sya9Pwzbl7+U4il3ny0fdnP5t8s/dvPl88MmUb+7XH39tGv7rCNfPnLf2vfA6ncvQv3uxVY/ldD1Qu6FLb/Q+Y/9bk0rvuuldMg8+GZqf9LDiE0eHRI7bjC2z1g79FFUQ1ooA7V8bmKHJuxoIhxNSP7FJrSamkgOmnDQxM6gCf3VJvS5CcEkNOFHEwaaCF9pIs8yDbMsq6zNsvyk68RVOxK1KS1ku4mBhB035RGXm7RAonpTnkBZYsRqjklbbspdWHqjvZj1CUXdir/q/1ztukNfsqxWm+dV7YsUSNL6kqdeuymBSF3ZZOllsz8L1qkVlDS1SclRjdQmncZVNvuzYJ1aQUlTm2SqDoA9bP53WGVkDKwyEavktlmlLE8w/8S4MrXlki8pjS/xcqk+qOPSttdLHF9K9ZLAl7Z6SeK62PLpevDhavP5u7Lo1pRv/ceRBhKvlzZ8SZRLxuE2S8+cxZ1Nul4idcnl85Woz/9sB3hQqYzTRYUv1TYjUqNgtbPR9ArI0GIV4U6ndblZ+AwP5Yqlq5I67LmYXTdotW6w8m2nhy04Oz9swdL5YQu2nh+2YNv5YQsWzw9bZC+wfMh9TX0RYipcr9ZC7W9YrZmK16u1UOnnq7VpDoGqPhlQfdH3pHopz6oXYlK9kJPqhZpUL/ikemEm1Qt9Ur021y5GaPZzF2N4tWZLXYw4mrBSgV7saMNPetknvUg26UVy0MukjHVWxnZShuHXzlBo/nNniNxCmfTNBZS52Uv5afSS4cQtMGGbW6jqzKrJklg8pU6b6Q6j3o1c0O433Fb1DbWtViq/biXDkb/IbcmEasQuqM/x2o1cKqrLIqXLXUJbJMq6L/XxKnGCSEp1VlSJUUTCs8Q44nObJDfxKy/xtXeJk3tYkWyt3/Lodx4lBo2sJIFEGDS6bzyqq4pVtqncwT2BIIhO64pEGEHa+lury6WmoOxQm4IMElUF2TYkYQORlIa0JOzUJEUNtqmbM0buYeUe1pTqiIQXSX0QzAosKWMt/+qADtyqk2HAD2KqqoVGT1W/vVimSC8aTpkqN8jxrK1zIjZl2JVIypyIRbdyCwZJ+hSL7dEriXqJQSzPMYnrq/MlqqqouJOWynyJbcb6QCRl9kVTicmIagLqsT6EGcTED2IS7HNi2qYV6wAfNkPUkxXrIKfGPp2N8mfojLTiWmz56U7ozNVLBl8K9VLv7E5YqLqKnXDX4C1KUvIlkmJAUs/wyX6CUffMxNMOzHRiJTvzV1Oc5/4+aNSsmqGijACOivlwrP+Sw/qfvcrJUTE7s5OZ2Sk017M315PbdjOfqNE2BGImJcJttNZ06f7YhiYT8nnG6mv20vIN7JXHZme9xjE290yvaWLSGYz4DEZcn/U6882+jbbtE71mrjjXGi71ys2VXt01cGq5/hw4dfOekrIbsH7w0Ia0EdoQE0qyCSX5SpUotZse4CBbHwGMrLCEbD8FVHGlvJvEh5bp51Sqxe5m1mPHxChoeChvXaENN6F5nNE8zGhu55F7qmJRl171HJKzigHErTIEkmlD69zQfqVic826Wm4/Z91se77517q6ERYyomNSXX8wW3GdIroLYVJfn5sklPr2pd3f8cCwIpddXjz9UceAo8wzpPYBR0Z4VDuCowMGqsR2yba2vuIeITzrJlMkpURAWaW9E1Xte0XwslocJQUlQ7DciAg6o5mhvsq1fphD01vrvLRwl6NQDPRdS1WfuUJbRdwgEYJsta6uK7lJ+NKGiOC9T+Zj8DgUyCCOVVkVtuv28CI8PAsPz/SHlydhHYtGw2wPb7et3p1IyqTZXVONRS3CpHF90qjY1uljJjaSrao6imoUDeXbbNj2UMbeBvp3HTwi3e7Z2wMwGK37EiT63U3/mVKaKIDoBMEGEoS1PzgbuTGJZ1YNJOtQe0lByeDgMncRzywUQprsnFEXEVbneRCwZGB1VgonSuGglAOw/w1bCzdqmHOYoqwC3gW7hwnQBC10qZHjMa+aQHZBDh+OhmSDeFUr04/wEHZAvACI59+D+HQH8SfUF6cc56s8H17ieftNnqf5U/lS/pRN1N+TpXwOBMSUeP1O/vTIjKou+iwA2CAAmJKmcbkHf30L/ubb4O9eAH92C/7yq+B/yruKU971OQuEuxggvCUGULcxgH4tBtAvxQDirGJxGwOo12IA+40YIN7FAP4NMYAM9jrpnFkUnp1K603SWb+UdBYz2ZoZOPmcZ1XLSS/+Du/jG/Beyv0m6SyMG3pR10nnlk7uq+ZJGbPFddQW/dfyBOZUA+sdfbu30DcD8GEn+pYr+Hua2cyiQd+KsK5hAtVHuXxgmR6IFZ5xuQa0Y5TLFSe1Iy6XDtWOuVynhCUoOWoYw6MYmElwLwywi6PoR3GluJcR9RhomV4oaZm/JyShvAZJy1oh4jUN+dgqQmhISC4AtUUoeSitJ5IzUKPHJNdRFfo+NhA6r4FkMF5+bpGMFxgvSxKRANllHQkiGSDclqoqCfY6JAoQ/kQoeSitNCSSAQ0Xh0QCEsK1NZTX70sDSMZ2hICkdJOMTYf83ZB7cDwUiGREQVKRHqAoCMc6CgxCnGKdEdEIEusYxokExzoKTXswxNgNMV+V6E4aJioGmqR7J2FTlNUZkLemrC4O8tbKFxH3eYXjcZC3BPIWiLyfL7AHLV8w9fn9gQLlmaUtfn+gA/REzR6o+UTLbsZtf4LyK4bmE0M3FP6UoeVL7yAUoqHJ8QmI0/VbBNvyDIgjj77UaC5eFhB+vCwgPGHPpx6R7XcMOr0DcNp7jV7OfdlGX+STvsirySO4n5OaM6pwN6EKD6RbeSa7G76SCrhVS3PDV3LmK/4SX+mXNvXVudP6rEsEP3ldgk4HS+DnqS4lu95T35fPSCd6NSc20Rwb9BVzVayFhZalztLdorOBu/46WfRH/qNUXX5RFrG6sit/rNJFA9gLd5U0kcOLfn/ChwS7JS0AecrtyDNqIRyWDM+Y74lEAp5RwMZ1l4BnRFzRJMAV3SraYGXrXBt31lTtvIp4WMjLKW+xBG2gR2OIKsCXZcJjRDJ8mYIUaJOAL8skIFAP29717gk91HUG72q3deeQkFElwir1Ynn2x/56FpHmBtllyU46Aq40PytDJOBKDfMrkYArHVDUOj/YckBCHxYw7ECOLgGGzaqwRHKwc7HV6nX4WlzlOlylAlcpX0hSpfndPDYnqeTsUPeX3s3jy1f2nc3yiscNs8ddZ4/rli9kre497uRm+digHhvSzzegt3kDOs75p3XKPy3l+YbrF/KEdLB3pmK8fiGv7d7S3NI+Jz7mrTy2vvRCXjo7kH3u9DYcyIieOSPOmGZr5oQYn3fCn7nqMLvqudPFe5NO7+u8S4k0DTQjFSfbodRVz68+8lmHfKcpJuWfZDQQJpixQ8rpDukFAEyeVj5NMfXl49LVO9g31BkrJ1d/8uNs3krkp9flTjSH+lJcTgAn4aknRX6K7iNkf+mwBO0jcLYRCYoxPb1nxJgpkXZQhK5gT0rt7sQG+wqile6DNUNoQ9pJxNQf+SFCji9/34hkBGgyUAl4Ip3nPJGA9+oLyNE74uJ3gyUoXMVM47GLR0F4k6BNu9X3oLTWVvey2m9G4Go5gMpO9khz/z2WoJ1QjrQbSM4n+kgk4C/7rB6SkWtSuyUSgIr8HdeG812ZoonaR1ILZQmqZOBE6G9V9v2mpoi2rcSdPZ9wiUyDv1b/0QmXYG5OuKxvOeFS58rVCZf1LSdcgrs54bK+5YRL8DcnXNa3nHBx+jizkVVGTrisiSMROeHiFEgMPeGyJoFEFydcArx3WRs9im4U/emEy+YiVOvpCRdnkYTuKY9TZ8FdnXAJx2vLdZC95KDk6QkXwPHaW3rCReIq22mWUmUvOSj506mzmvk62aQBm9T/kU3W3csrm4xvscmobmwyvsUmvb2xyfgWm/TuxibjW2zSg3lFdXnqLCpqkxBul0d5deosyiubLDd164vjqJkf5und9akz76hNWoUkV6fOvL2yyQinPiOcNfNgnd5Rm7QS1XiySYarbPYX4ayZB+v07mSTqa4cWU5ev7BgleaFU2d8jmzHxuQL4Sx65wJHuPMi8HJ4G+bwdp3DWzeHt34Ob83y2SG36c0M/crJtv7y9UW4+46Tbfv0ZsYUDqfl5jjb3Rk2UT3j1Rk2Z+H1T2vXm5A5zYEcu5o6T+PkOblZQmec3BTy5sUJbt+w4Bvu03Uozu2+PjtV9lIoHuZQPM6huJtjXz+H4uasl5sXH7i17zhtt929+FCC60Mv5klifgqAzUtH7MRyE5dfHbETfL/xp/ZFf/p/9VFTPg==###4540:XlxV32DM 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10a0eNrNm0uu5CoShjdzF8D7cay7lZJ42FJPugY9LN29N2AMEWCTeUpZ6h5Uniz/fgSBzf85IAVjZtt+8j3sX+Rr+8eLQ/D0TaR/5Ndf/JD7l2CEbf/mh1Jf9LBsy1uPL6WZ3v4Sgh5fhtvtX1rSdEzSlElHsLjlTSyfNP3NpyxXOcpV/kO1tekb+/V3up760pJsP4yXSREHM0nhTaHb3yWm/C3to8rRZm9HZ4VlRZejhQbnzc3aflhqT0mAg3Is+SiWpXDY85pUiyNFL92Wv4rz64/ymXbz1LUzmPMM5xH1NJFwcBpjfD1L/vbDmFBCJzX081I08O2HPvLh1NPYTi+/NE9XNiK3irqIFCGTItnZKA6VkkcZi0IVUnL2lDkzLJGSs6dpCc7tSOFZYWfTLVBa08XVdE8lbLoOl5y+/cgf6ezqUK3pojbd2L1I/cKGnk3PH7npB1Jy0/NHVjxSctPzR2m6RwrNCj0VjhSWlTORjCIld0v6yIqBynnfaFr6xZd79bohzrBjaavbkVLC3s/7WyiolLB3dQYnkJLD3s+7mnGk5LB3U3rMM6TksPd8u7t4dli6xU17glJ7/vFU2RxBem7VF6O/8oN9fFlPju183BXbr+fak/Twctefa7qT/FwLWZ9rUv+CR5/G/ui3o/h2jQJtE03Djo6mDAw6uvNEMcBdXD5qr9faVf2r4S6q7GLgJls22bK3EXDvIwdvUGSHLJsi3JSDTY8K3ETzJg1buR9lEzoXK5vCeWVT/v5MN/j5159jofEgC4yUE3sBz+LLJgk3lWt5BTfFsgm1LpRNKO49bcqjV750GtpV7i8Nh3a6iza0O3MN7SJ1fL0F0kCObwFG9le3ACN+vAUYJeMtwNIdBzzBU81yCyUOT9bwWCRXdCzyFt0OM+5rhkumf+YBpmy4EpDNrfT0kIHYM6Cua8jkGZe5jQ8Bo+5lBqiaM2C3GyvMvSKmmA7VY/I3vcL5GBNjLaa26YyBwE1ym5yaT5EyOvUVE2Nf6amvDtP6ira+2nvM8pt9peiYFwgizva+wiCC8sLpnJcw5YWTOS/7nJc45wXdw2k8Vm10T90KnFoRQppSDSYPzXl05xwpgGbojpRGSXUMb0q5jhfnMRod06nJeQmVwhf+tDjFgPKERunxvNAo9T5Go0Nx2G7IIcwiBXIIPqZxSO36rgAOYQwoF4ekcGYOSeFWDsky5BBrLg7J7QAcAgkuH34SXD4cEJyyLew0miDT9wIq0PQ7kWQFmT46GzL9AynN9EXwASnN9EV+SrpSWSVWkJIwp4AulZUtH+pC0mjOg1qLkndALtNKQqVzmcjPJFAgl3VcKgrgsk5fRQFcJiNSOpd5dEy7FdR5K2TOKVA5cg4ljXOO/xPO0Y1z2iazXcgzcA2inzDTj2r0gzBqACHZQGiiH7ainxF5KgX9AeQJDXkmzokz5xyYc8yScwL9X3POseIc8wnO0UvO8cedd86coyfvpGbyzso1iH5u8qKmvGSMQiBk+AqEgmhBC7YAITV1G4SYZ/qZrJ0O3cbJCnnsJ5BHyxXyePNB5KkwQ2vL2Yw+fAAkwDkIC3rFJGVowIIOI1pCGIHQoyWEHkWCRQoAJS2BgjDFs1aaMbyZQYrnhgtafSLLgAu06gUFZGm9PHE28YkYWs0nnxgQg/MOtqiDVzqxgArCuB1loaGfIqDuwREcAZbQjyyhEUukbDOkAJbQO1AQS2h1wBA6S6T/M6jASlXnwBI2IEROkQII0WAFEKI+YF/dQ4Z5hAwzQIaOSIGQYYHSIOMq+aUOjI2djoGdfISZBZyonIfKPSdqxImJxFCIjcQy5/jjjnPoxTmcPHNO3MexoqIPHCsurkH0c0z0E+On6Md9kH7M9k4ZiE9loBNtCgiNtZ8KRJVuvkM/Z0VmoJ+4op+BkXQ9p0HWkZzD6hXyZJJ4B3nC5BwnBWHDn1+WycTCFxstQYjLFQjtnwAhK1Yg1AsV3wYh90EQMgMIWb8Coah+uyIkZwygzxjAbwtWqdvUCoSOT4BQeUV/BKEo3gIhdswZ2FcgNODS0+wV9LLUVcCxFOlDuxXYTrs5W/Fkzlag6r7qL/pWPBmFFbigYCVQkG17ImDYoASgO1llBdq2daipzbbT2XqDNK4NaAEVWBvoZaus3Nt2UW5tuyjAti26DrLtAygNB2Wzbd9sO23Eth1QP3XbhvWqkgpAIx1zrXnCXGsw5jp8DMDcPjdqzWM1Lsd9YbcasdsaFCmon3EClJYYdcPJOVuVkxWunwXakqceaTgfXmlYYRoOAjYc0rA/oHJPw9YAGi70Y+/ohzX6oYsqD398xf9zcGNnuHFvwY2Z4UZtH5vjqqWcB875/Tmua/ZKVEnOtaDbKo+fqzxxqPIcyypPfAt5KHn3FniPaPiKaMIniKYk/ZFogv9torEz0bi3iMbMRKNGolmWdvrc3h+a46LbAm4e57i4WHFO/AjnkBXnhP29gg95LHnxBd6FOQP79sg5HHNOX3eQ7scHzinKLecUBXKOgso955RjAOeYCJSBcxgMG3EOhwriHHQM4pxeNjgGzmFQgZzTFyhl5aE8cTyWJw7MOSYgBXJOBEqzc945p011pY0D51CY2QfO4Y+cQx45hwyccyAFcg4FyiPn8M45YuIcgiKF84Q7UFpi7tYr5WxVzhnWK3nfkieeOYc3zhED5zDYcMQ5FioPnEMGzilPZdI14hzeOIe9NZsF4WWo8sQ4V3n2d+a4ci3oAYTeKe2EmX70alnPqrRDJ/o5ueblCh8y0w97XeV5o5Szr0o5AwiZoQb00zI3FnrcutBzfHduC6LMYB4VeOhUIXo54xVHJ3ULLNrZJ7DIrQs9cYlF71R35mScEPW0yOexuuPcioV6NtbTXHxmIfoWC7GZhcRToccvAGjnnwCg8hioJwDa+yKfQyAAelnVOVZVnQGP+FAOwkkIYxIY4S0JoidBtQDdd5KQOaJBjtd4ARDDSjdPzyVQmsGF5vzhaOYVqnml0aSbqyiS6+bq+9cw+Oxpd9cRl9359i1A40sBcRg0tLdOjV7DSa001OCGArJwDZjSgwNpJASHFFjlEEBpyfHY/Vt7qvv79i0M9Y5eLPKIAxTphRY3lPucBAqePdMobjh75ixU7mfPSltvZ8+K0hg9xe1gcPdU7cTTciT3WKV0uErpAkoCIEnfqdCBm9Rd/QCQ1w2lvY7JbigH9ilTh4p+qb2d1xyGXU/Q6RDDW6hAhncKXehi+DJq5YebpuEifXQWE43FOGCxn5rq2WIu2iLzzNv3AaxWom4rUHZaRL0qO6lV2SlhT33JfI1Y7J1F1JW62FA9Wk+FXbD0qlqUMuelKOsS1T0upeG/L4TZGcIlzEZ+ZqP9d9kIl4xShPIZXBhnvTRiVkuS7WMJ4K6Io1ZFHEwrZbWBeqSVnsCwI1p5iSbiraXI7CmsG1cG3NAKJ4ru+FdKL6Z++E2pKLxc9utCe0P3AS269QQr4IdOfR1H+lZff+vQ00dhHwYgoEgBb9N9uYEP6G26PgRJKjcbcKl6810KcikVOQgPeBFVkkEFehFxSAErOfq8WFFATaHPcRWluXgKSbTgOPrhjWRXhedsUbccyS7jOJVueukYj7LQTC+9rlikNNPra5Gq0kxPCuFBcMA30v8ZVEDtJwSJlGZqfYVQVZoRyjRsIuWyu/wMxJyfZOUyfXQXks2FxK0L4coAfWf9R5wGu8uFXkyR1MrAC2NarXrVK4+6MSZcDuCrcsA3awDpnV+vjMqvfqRz93bvJQ+Ll3nGfBvFRJ7NeHyZP95ZtVHdic7u9GqOA78QSebpwrAYkTdBLw1rtbZUr7zrzhnqgzkYVnd80nLKdaM0zqbXazKH19dQTjHNy1/ogX5WK+kent/6GfWk/6x2X7z1y9Vb/++/6tex5MFPGSG6+SkzCz8Nq5/RrN+081B3DYL5uYDDo2YEKW1Ipe5AClyzuQuodOSvbS2OEwWuOwObigLaazodQ0qzZEZZQErzfkbLayjPY7c4V1X8Xe4DYKaMCgr3Sa2q+3RbTeeJaB/a9mkGm/axaB/W9mlWCz1L+Prj6DSoldzv9e2uHIRhpL/ORwEJJu1aCaaMCZArzjHiUiBXpAajpKQuqYH29+B0J3B0YvCuedHCqXR7p+qqE9Rjmr2ns3mkNHsH5nreV8B294CU9pZZx+xLQT8HVhG2GlCJi67+GFf3fikmLkUxE+qyibtu4qqZuHz9KnlTy79bsTn/XiX+F299lw8=###4700:XlxV32DM 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1244eNrNW0uSoDgOvcwcwH9DZtRVKgKDHdGb6UUvO/ruI/9kCQNJVtdiNpkkDxtZxn5PkjN9fv7hrf4QH//RyS0fRh7x8/NPf2xwC6DoCBTX/HT09NZebi301lJurfSWgz4XY0ufi6EdJA1PL1bRW6rcOugtkW859pqUb3lJn5LlVu4LXrf6+juo+tpAR5mO/Ggw45YSpXWw9Km93HKtA2Z3KBC1KIFFwZotwb3cRPwNiI3ZVvP5X3jIfSht3We+mz6cjerzPwaafSzqAI8ZS41JZWIEuSVFuSXpU6HcUvTWcZ5RJWAUf+q4Z7s+/wELXW5guYUHWiiPbqGTsVuoxWTOOpkjZ3PkMpkjHTdHpm1yWEKHyaC7OXo70BwFveqN9KqKd5gP5YUPj9nofTY6VgsjWpgbeG6hGxbKbqEXG1qoJwvtZKEyk4VKTRYqOVmoNLqVT2352JmlSqjx8S348bkdLV0nS+NkqZazpcOXk3n7NOvwARFL/2qWqr9/lKsMfP6EpQqQkjrvHRqg/GlAz58/yhTkq5+w4nNzWJqteX4mzxVAq6+QQUj2no3NkNpX8lIYdH6nBkQGrykCjwNiqqGSIlZkpPRmVGKIzIgryMaRbHcoxuk9MERnZKmjPuiowbY26mKlKa3ryi2tXXcabNV11BuBSsewBxck7gxRGamvNJK+EgbdXlmGb+tkGMMmQ+BkZEfYo5rOn5H4THaJW4rpBgcOzilv8HVSzBYpkvvNP/75y+yBIzIjefrltiuG5DEVe9taHUj2g9V1IgVBmvNk9qt0m2EuyiZEV5C0MiSbEHOb7ajjgQ9yfJ/wnrwIfV6AMsAWK8Pfee2ljzXAm+qKdNr1pRcEUK30bQWJEwvzbUBGfd4G5HHM9J0ofR/7TN/2RMxnkt9nkvdI8hOzL/fMLmZmlzOz61fMrn6F2Sc6j0jnJ9J/xex6WWfeRKJSq0feVAtjdrZtin2mIDHTeJhp/OC8qePMSoPG1R5wrzea0Tjb6yuNc950M2+G2WiPRk8Mv5wsXdzkOGR4uW1iMPx6z/CVu7mlcWal2ZdZB1A610e8p3O5+aF/YnigczXTuZ7Nsa/o3NzQedlJbukcaLZZavbjFZ1P5qXJPH1h3td0Duu475NgM2U8Qj8FQcZro+sIlQCw7R60ESHqLTBkEDVs4oG9aBA14caCDKLWSzchf6NMRuijc3j+XriMOHzju9yqCpT8EBUo+jhIc8KESkreWmBrZFRALH2mMHN5ZjCzVeijvBMQXm8f+ECGFqh7RkeYgNBiZ42Q6Qil5h2QUKrc4sGQQcN1yQ8EqduComAI0n3bXztCCRoaCWpc/h6A2wpiE0WKroi2+tmxASGpQ2dsBorUKt4dUms7dkrvdX4qvavCKXKDkEXug94XpHf/Nb3HKZbrXK5mEVC3Bc7pE5Fvn2+i9WWO1j1G6/COVNU8Z+3Kx1/F4y34bh1wqv5j2QSh6lPk3Sn7JvKmJHym6ohUDfwstHzgZ2HTRVx7wc/xVZi9X+/YdWs4Rf9hcMuGVAek321Ifcee+M3OTGxmJtYz5SlOefWbdddaAcxC6eK1ZVqBm7N9vskCLLM5/tJbMhg9h/7IxDKtOGOrYUzMaVe+iqL1pFdOtjyEzmALhs7OpJlrJ5viU7xMWfTMtenOVbmh4ebZYR5uOnqH9iJWm0Rq/Rx1HcKeslTGNkl2xs7rhuzdsKvvDBlhV1Acwb27mQdIucrv60QK+3BCiIfWAFFksPzYu0t32WqAtvwmHdfRna4sUZ+CwTLiLXjVG14NUh0IkjUQwkYNYTG+YAiJ8S0bFlE8dQ8YCCoesD0ShNkey5woyfw7gte6t3WEcqPZ9zas8mLCjbCVqcZzBSkqIu8ElCVFCPSZokbKM4MvndCOPSPxGRQJYMXCnlH4zNAlqnx83dKqtoByChRwEHDFhAlyf502mpsQnk0oyUhI/hGg+tra11EEUbew8DpoTlPDdlhPx+D1FXl9Ibx+0tMvYvVG+TRUjbLE6gvn92hfpt7dFJVP8baemLuS+R1zc373Lb72VXEsy95IPZ7i76/S6GEm830m8+My7v7DKFs8E0xK/iG1LhSymN3knFq/mavL6DvO0XdiMa305pjFRt+PFUS3zRR1YPANnEB8GZrvqlAycq/KqI/2nzzcB9KG4Y5Kwh5n0n7D1O6REsGAcE/PYEC48PcFPc8ipjH2DT2fSHyiQm/inE5Y0PUWXR9RYoGq+abr1/PISeAt1Hbl+vVN0nzO/qhjHnn8KuCWQTYqLrbSOLiHLg0ZZAaU7xiCZAbEYxmCZAZ/LwxBMoO/N4LQ8N3sqWXwyzLJfv38UaatXP4sP3MPImAPge7SYM/GEKTqNjMDQXo3wTiCNHLNL21GBWmJUfA1dBiufuYfJe/QgtNqLXwZWcYUbj6Eps2X0JvD1U/YGuukjAExmpU9XdyQQa5DhzVkUCqqgYYgkcLfhiEY4MPfjiCUR6VTzHODR6VfDuZT5FFo4xHxNGsPbXaKkKx9EhtDUD7CgBaGoORsW91AUPjArFIEZ/X4wEyRwhk72owBpVZGr2vEfOwfyg1G35DR18tInSbPSj6dL+vO5F+l6+VTuv6C93mu3s+5+mUO8R2qgkkKQDDfYvCenf8yXL9gek8Zv4fxp8z7m3A+vVIAJJz/c5V1GKuq/lnVwXZpiPdL8s5wfhyb9DYKxxIrLmo/Z0fFMuVxxTrt28LzgFqUWOI217ApjBZT+lYtoBX+b2oBjAfdst1LEGv8v5cgMEwzuziMYcorF6cpcz+nyuWcKpfy7OKnYwpiVA2Iiy+OKbipSn3tTDeLihjRmUNUHKPEL7/nTBULg9wcdFBDTmm/szIIF21xiDaW4im1bXMj1pREyZI3cCrWvpUlce64117WuH+vvVq8d9JeAnNVDhMx2gzttdwmYua1rOZilppzVqDxuH9VupeEctN6pNCWe0l4kRfS4pUkvMkLwdd/nhAlNE7IiEMiLlC9fWdCgGILoefQPu+4NUWQ9z+a/3Gu5+4rMvL9Akss+aoE/T/K1tUI3HYCby1HHso52rImNnSVMlJRZMgSCDb6KYq82lqqYl/ZUYQ6k+MZhc+M8k1dq6o9wwpD4xBJvqKFIbBreIGdFoBRGoaMpEjdYiti0D+uy1a4q0lLrui63CzPN+2TWitHvMoPO7ie7MqzQBRT7tARW0gqCezXFCHK1omAX4fBr4OdoiDlm3xVvQn8XiCNkEqnImAPccpHXg0FNVCHpwiUnwfk4OdV8qva5KpEY5p2wKibw/KOeAinIDVjphKNr8ipmfoGgW/ASIuciKnPSHwGYy5pUmGcNg81Hinz3q4OvEo8RpELjv24ilGwyxKjlC7b1YFXicYtTc30Los7a7bVBL+QHlskV762fnmMy8Tju62VIYuU78tbFyDRJFz9WgoQBa261UVZAdkAiD27K1varoYoPov8dYj8gCJ/uxf5d6mhmQK/UOvbK7XuJ7V+EvI3wv0bB2bfnKV5zu39kuKPrwp4Byr+78l8+STz1/Qo86cpZhLTpycVD4vqScW/05VePIl0/TtEuo9PIn093ol0+0qknwqLoth5K9LX/Z1I97dHSZt+v/CretLr8jfodb25WVEPvb5hdVIH+dXB5OvM8346mFQSm3f5VuUxqPRSPeRbze0Lr44eqTv/yiehr36D0NdGzdJV4HDdqJUv9oXQn4vTRNVzKV+MM7dS3lyFSuvkzPhFqFSOFN8qc/HvlTlsjV085Z2Mq7xRSvSRSTmHJc28N530XyT90cqvTY4h46RP3Z6rMpSoX6Fn1PeW4DSFSOMK2ZWjTzyukDttPWIAmNyuSPOyYUevNjz4s50PdZlIGlHtDstr74eCNtckW+15RA7CH+iF/ZxddehVxbW4iiuxhxwyMvu+0THQw11LYNYItGYkZ23ydIqvNbmP6Nmdn2xWhoyFxyoLQ0is4iN5I8616rGK6onkYj8X8z2TXNYFF/N+JxAR81R95k+16czs334px6Xm6tNqPeaanzvQRlCE6faVDICW+0fQqFu5vz9DDvcbRfqlYQ4V+3lpVGGfHdeuJF5pLvYVBjp5rDdiP3dZhX3usl1JvNJc7PtEuiRiH5YA89iIi7aomJL3CXW5Zkq+fC8VMOz8nIkIWKbkl4BK3pcTiFMBfkclH+YC/KngflWLvzhY971a/C8flj8V79dzxHBS8fbVMTv99G9vJ9n/pm7/dar+8pB8nIv14ZPJdvn0f3DCxMdi/ak4fyVmrk7lvajb2+Wpbh9/hx4vh09u6/bmeKzb//Ip/FOhX58O7tFTikLpp8K+RXVn1/ggNN2rc3f26b/XqDLl07Q+1fjTb5Cfoiik2xq/lY81/hdZ3KuT9Gke+c4L+850TZANZOV7ERlCyvfSM2RQklCCIeP0vVCKIHfle7tg+R5mhBOsGBJTaV6Kt4IgvWgLHcyleHhBK8VnmDCf7+fR65tvSvG5eS3F5+akFL9F5pLB/iYpzcxG4QhtUOTCEr4s0jfkokjfECKWhnQtyDiFL4bMBoTJyKA8NY4W6deFmY06EExYGYJ6Fb4l7E0mXr5fGXJVvm/IRfm+ISQGkAdDaPk+EQS/hKVHBx5PXpZPjQYjQbHZQHmbdwfpr5TCgUph/zWlEP9PlcJIBf7K8T57/+90/wP7GF/B###4524:XlxV32DM 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124ceNqtW0uy5KgO3UwvgI/5+Dp6KxVhjInoyetBDzt670/8hGTSvplVNbnl4tggCYyODk6//ffPkuL5Jb7Uv3/CVfzS55G2Hz6oDB1pBUj/+6d0i/1alNm3fOnq5Y/yN/cgAvaQvpyR0IH1BVE7QxQgTtZRI0N0RsqgQSeCFHvqoM2oIA0xyrujw3D1I//57x9pT1v7qNbKI3e/nvnxKDR93If+OFz98L48HuSCJqxfbjHbD3eajOyRIUZkxBaHpGaIzIirQZAMURmp4YmeIToja0V2gtRJcXEvvklLI5eN8yZHRjrPkGycN7E8Y1dEQnNoMfUZQ5HiEPwps7ozJDtk6twpz5DsULGgGEuR7BD8KbN6EgRn1bZZhRlbcMZsmzEXIUr/BWlNWV/mK3wp9+//dLLpaw3q3P7QyZxfdonbH8siE/Qltr+ddHD39pfT2X64xXroL54bNC2GNJ0iNxlBm2RpkvTBVJoUbYqlKc83DFfmMP+712HjQTt0+daTDWtLk6VNe2lqdp+eQr5Aax0jqfKvL35sf3lmVlJbboq0KbsI7yJt0rnJUReTLE20rzOVpqMO44867HrW/++i/j+o+v+gaW85Oj4stOksTTQKqQwQaBRSKE2ONh2lqUZ4lTUKq6qRXlUs/+ZtKF8EI9ZsWB5Z/FvXBniitrxi7JcS+15WTPqyWtq+ZNRxWSpKuOtSUWK9LhXobdv+hnVcQvIfjF2CZPjYyxjb9bEtuN7HjlOv6boAlYjXBahEIAswv0vVBmmdm20wzQaznN0EFTWacNJ5Dm0+6zLLbyGLcHEzzSEOw831VYjTNcRSTSGWcgqxNNcQx9m9OMb2L0KsxdTrjiG+xlX6m7h6NQ98YlzjiOuO48oP41oWtWVDJIu+GfTNHMM3fQ2iWqYgKjWtKGWmFaU0eo5NcuNBsPMCTx6DkDAIsK92A82nQfDXIZQQIwj4DinYK/oY/rq41DotLrXPcQlzXBxbb0vS63WtK9G3E/A9dHOc8mjOOvV6zNGOd+vMzP5rDPExQozvlt4/CfE/bZuCPFuuGrGQrqRg0xhM2UdICgZInOQpkvHbllsQuMrB2+rzPa8XFqEbnqlF7wOZRs/v2DsyDWm1Ir3DNAOiKwsyiMCOVJFYuZ9w9JnBddo7VhC4aky30qAlZQdN872SyvzWtytY+r3NUKI5uF3pktBYMGuELF4YnNl7oGGIFuhUwhWYiZTc7SdDBrlrb81ACP3unLQhSL8hSAcNH2G4tpB53ZE2YZFyXXDAE98I14WnI0OQ67bE0UfsCyWHuC0U3Qlgjjaj7MF5MjmtDCmha5f5gd5qrsWJRrKqG/sGjlEtijgNppjxAyhFjeiKcfPV1h/APkb10buj1RJEhfZXPQCuMooOXF6l6Ci+16u8vFqboYUIrGBJglJMBPJVeDuZWl/XP9CwYsaSKFKWUFhKKPZAkbKEghlcXyMitx6uvJhCnvT9rHEshL6/qboAawOgdOnzXoG6YqEDj/3pyuhTtkQGSHgyDkafkNGfhNFfaHsj5GJm8nLm6GoqAWiOK3x/ZvCcrq9PdP3C8xlzP5C5M+p/Ie3mHdLe6HjlLJypV9b/mqkThr7MRJsRXDnT8Yh0vHNwxueRdi8ppYm7EOqrkHeaXTLqyzl2nDn2ObPhMLPhY+IumUbTxFq7vSHGCnjWLxNjCEKcgzDIqUKSaKJi5JSz4LnQIHwVm9wUBBmmIAABp0EwomxCtxRTqxfT9IJi2rcopkQLJ165XOdG3vNKldzv4JVCXj0fRA48l4Ncn4zIcc+PyXMtZ8/Pe8/ZqmRSFPTapCjojEtRuJuDE2Q3l3tkCN3NR24oCO7hQFcWhpBkKARDcvYNNXELRZA7fRAc6PogeMBSsHSDI4LHhLoM5bAhL5TDhiB1aZM5EKIcLp4gXWPKAZ2UwxzvqhxmmCqHKXQdKvtBaIiEqoMOPLgZDOw6KUhDssxjNGaQVuxUcGYdJOpisIEQIrakoClCpcYhKKbIpcZ0MATpF+yuK0OI1JioBZyoqoP4xWXDRJHXsmFKd7JhSlw2TJEhXTYsVaer2t9BtT/YODtTSD+l/cX4Dok45Uwi0u/W/taZTOzbhzJgFcK+F/oECn2vOIP7ROU7twdaMXGJ9MvSXtnm76U9+9PS3pzPstrHdCcXnqS9Nbwn7b0gM2kmM7fSwKO0t/8WaW9/lPbM75T2lqu05x+lveU9aW+dqdK+va/y+SeVb/0NKp8qW6DmXAdXkgwooukxjcDLmpuTI5EHUYn5HRkETwb0wC2WEbxv1UF1FzH7JAmG30DdwJyZuonhE9YW2ugHSXCfJUG30bjKWRpkEfDXUOeJdDeMUgaUa50IjFFys9L2QDKvZmnxgZC4PgmJ/teFRGnF0HP4kSKR/HzoCpILF8nvpE9TYU+hfOfYsSPEvFPCHH0uvViH0svKpJe2s3SIqDxUVvJEVvLj0o7LlXNaJYtclZ3MK7QoJsUswrbhnsjuUXjP4N0K3c33UKkJ9kjJHhf4+KD6RFjyQ1jyeGXxauXCUpeB6z1DWIJRmWMwKW3UITGBYyu9B6a93TPKk7YZ1dkKt2KrH2KrxyuLVyvn5lYQozk3txYhzyTVtoPUCHsmnCphiImk+mj7dH+mzgrwoxo51Aa9v9BlIp3uKJ16Lp3ahTzOpFMpGUKlU6yF/D6kU9/LC5NW9soQdd4H8prhk12db8ymP8lPA6zCiF5PA6wk9jDtXQqKjGqmbZgaZ6G+C4FWdvsZmMLoAgqJB1cYPQKxKYxu9FeBk0iP7a2pBUXY80qREXZHeY6CQvaCwojvC4pTbz+nSr4qKOKkSuZ65a6mOLZ3BEo71xQea4pJlczHXlhLLG4qGLhgqSfBsqqTvPgwc/Ghpq8M8ocHve7o9ca1zjjmOiNNdcaluOhypr9UJ8Esp7zm7UHl5e6RTizGMyrPOa7YflK9TE9n+VTQpMIdtMxGRzTaDaOBS1JyzI0O2ztqo50ptL9VtKTjWl7Y3WQpMtAk9TBUMALKWdFcQTROKmaFUc7SpJoPxPXlqJvZvK73VE7md6kbLcwDlYuT0VpMVO5qXtMP9YUAcvP8fAhthnnDplztilq7u0LOcj+xvlywqfhG3GqHeWPPV/mOntv06QxCa9ex8l3Qb97E69vTcSoSLiYxZBCcpX+U1hCkR1AfGIYgq4GCMVBksAp483aKUE4iI3Er+4tnZXXLz7pfXp/MLSQl7SVT7SZ6kquiY8iQIrU3DBkEQsfIECQdYKelyFARwTc2TvFtqTHEU+ZsJeUcJnW9skBE17ND0a3I+OzwCAdDkIPAMytDkLfANhUpMjI7bHOaIoMNwHLpynFeOIxdBK8JRD4UtKIvz4YgmQHkYMioDOQpGYJ1BpgdKDKqFDCbGjcqkLzf+tydXDNFCIMiKKQI8v508hR39Vs/f1QTkXh1JNloR1FtHzL+wznkq8PHuzQv30nz5Fzymtvb+aT66NCRfgP4TgKHHRa2w1K43Jw1SuVRQVnU+nDWeN5W2WL+XKem+8cDxuAfTv+kWsULsx5P/x6O/L4751vKu3WThJXWI6H59SEL67eysLr9mE7Jl9pEe7vuDuO0RpnRnPKzwzixfZJnz+sMnnOeHQtrHbaEt/Is7IZdIMke02Spl5MhmCyX45AMIcnSK4Iw8SN4zJbgQ03osIHwIjwvCpqGxMkRTF1QxJ4MGemuztxARopcxnbuNSv2zbIE6hJRCBYvmLM0/2OW598XjRzQEExqVuyKIZgI27vZkZ7+IVSN1SihqFsk7w4ZoCAsV69sNEyUYMeYjYNntt0xBDMb5QT8AzjKCS4fzQV/EIR5lVh+K42VD0E6qUmRBZHm8sCMx3RZqP1ZP9mBpHiMpKgxKaqXdfPd5/UP52oPZfCUCY+59nUf1b7rfVJUT0lxKnjFXPCal5/V/1LB+/S9zovP58/XWRT2JvtwokU+iLHKv/Wx+sMx1m1Ve+qnqtYfL0rxUdVOqTPMpaz7qJRdr6VseihlxeAZyT8k0eUpiU71q5rrV/vtd9mhbIn39asf9av/2fr16XuXF583p++z7Roeq1r3eVU7SsZwrWpHBTp2SrgLq1pNcFbVouBcEVLVhoUhNFGfDBlZTTmGkKpWedYbqWqVicQtXtUGgVVt4m6R7CuxLt8Tr2pHftgTr2pHPPbEq1r8HLUig04od1CEZErlWW+0qu0/+SozwJT04B2BWFVLykPNCQApDzUlDZDGBUNGVaucpAjJhMoxC2hVqyzWu5ZVtVCHHgQiuV/a82QI5v6WVwdCzrtkZEjP/UURzElMHvAG0WS8YDLW9yJ2f82n5Kw/Sc6tTH2pUa+zRr1/mKe/+Yj2LmXrt76vVbNcLbeHkpbm+A9+9Jbmgjdcs3ZP5N9l7aNk7SIq3YjXSjs831/CPovXN/Peq9t3s3i6ZPEY7rM42DSyTzAP2vT8kx25f5jQP/gSdjndU4XsRnIPT8ndbO98HLvMKVNvD8UyZQP8FOBBp4acO34h5sVDnj/fyfMtqcs59X+X5yP7xHWosiXmJJcMGbohpMzEX19UhJSZpyMIKzOVGcolE4YNptCKkAKUyIaKCdC0dsffMU+qKv72uZ7SLv0n2w0Z+WeJB0FYolOJ+UprTykpMjKqgaXK4jN+5h38MDuyXLLElSEl//wferJq5A==###4472:XlxV32DM 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12aceNq1W0mS3TgOvUwdgLOo/OGrOELiEFGb9sJLh+/e4CAQEKWfcrZ7UWV9PQ4gSOE9gsxvUkr14f3++gZPuj599z68fv80IeUP8aF+fWtldgXIJgqSfALEFkSlD7+EUlvl46mU7k+6Pn0v//v9U4osSItGBg3QmkqT0W4Nqk86hQyQsQ1aAdIApUV8LFa9WqHyBC3LatGievVSBqqn0vJSOs1+IdBiBSA2VmRNrGGJDUso43yrnWhtvRWzWrtbpAjYCu2qZoxGRPexLHErlcAFhwfAX80DS661okkEau5WuvUUDju97Q4oLVcHLMm3KbFHn/DUHLBk2YbpWXWJ1WWp3gazbrQMDKaXKcNakm3Dkqwdge2IUsa1MgGHHo6hy6UNfYwvHUOPvs2wIlAd+hLXNiyBwzrmdYndZIvmCPRK6F6pM7Hl5hT4qRHVFXAdSCuOogFtscC6GssMgN+7VL4OTXysH0r++o/OLn+su91e/+hs04db1tc/xsgydeL171KHBJDzMNaYXuVVWRavHzDo/m/xObyPgRQFg+BVsvSVr68cfbXUVwt95eorT1+F+mqlr7YX9JxV7RnWV7UEPrT229AGs4Dano0DVmp5FekrW1452i0sO3hVV0v5lzaQcoVCg6pHofv6HcLvTbTfezdvp17ItepOvZBDfcWM3uur5uFVru1f1Ty9qlj/NapGm9duU6yxBf4Tv9o8go3mVWbXfahF7HV284dzsOj69Kp4ml4lApnesujLQ10yxQ7LW7e99ezk0biKGhtP1D9790P1x4/yzTD7f+9OrQaeFt5F7F3IEs57H8uyHX3osj71RgYg66Izlr6qi84K+qouOivpq7romDPkjs7AV2XRMb+42S8J/aKHX4bN8o/8YpKLk1+yO/ySzZhYF7APffaLUpNflJn8otzkFwjch1/OzlDy7Ixtckb26AyBzkgCDbV/6AxfFomhXSgh0Bk2HH3oPWEffhrmPg/TT9Ovlja8hBORz8NTQo2JwL4XGbHv9dy3FnPfce779jsMsw36cDGIAXSxQxO2P3HxT+iiq4HaWWM3CDsNSgSq7AaBCBCngus6qkSK0trrW/048HEbj6E9fq//r9RokBpNp0YIeBVy+YDgqYupXZ1Z0xxiAAo1zbO7pjc8K6OwTNEk+9K6iKyMwDJFX+1NuAlDhtdEZhnd8bThU6DC82DaX73MEJ4Qrj1tsYrM2mJ/2vApMOGp6gweLVLhCUGhC6caSpkmsoEhKLagjmBIUTJprUhlPUSKXAR6b3V2igxdJXMlz9HaUFNhWxtSearOYx95m0zlVxyWZ5KqR5WjKtFEUpmdIaWO1SetC7NbkSKD6mxThKpzWFArq4SavMvrgRBRPaRzQYZ0pmK91kGx3onu8BIT1Y1OmhscE9WdgQ+IiGonNbN7CPst+y4Bd4+LukpA2BGV715uEErkNiTgjhJwIxLwB+jeFv4ppciYz5QiYzxTikxTvJNJvj6RlV1OcqHoZqEYZqHoZ6FY4jgKQ64C5aQCm67jKlCjCuRacTkrSiL4NIVSlXJmVnd21oBMFkaUhZMW3J2s87vcSD6vhjLwkUk+pgxEnJSB2CdlINJEWyK/HspHsHSfZVIclia0NBim7bhqm9VJl2hqlnv6JPe4OcUB7lpSqeKjg8l9ZpKK6yc96yc5k7udyd1NFhYtxi3MZwuHzlGLRGGp7cJ0Dhd92yz6ltloPxu9DtFHJBCYlc4rjkggr3AfsGjNJBA3K89mhdmsOJuVJi1KvAYx0vV0Rf00GgNa2RDPkMJMVlRkYXUqmzU+UIulSGVA3cO0apKhzlOVHtU1VHqoKmpGGYVlUHqA5QJ7yFz4tADdoMSEj057QIjljgBZGYI8Bb8dQwYbtU8TkcFg/SvBEcDQ+wgqw+yNe3IktSmd6rSyhgcHg2sEc41A16DiAucvtExJ47Qy1cDd1DKrwh52Kl7gdyAIp9h1Y5WGFlILR1C9AJIZMpSVsitbV0ScWMMQFCcwSxtBaGZpyysh7O6TRtg5FG9KCTt8SXI2AQl7vyTs+kWd+TfGd/xLifsunyIf5VPEEybteRT1Ll9yQYz7nC+JI18C/opiZhzkRiEwgDoIfywdcuGxgxBvqI5yJAni1tTN1c3OXWlnDhtMiG927vrRzl09Yh55yc99dd1ubTMSotH5fmt7FbHDbEO6suFnt6HI2PJEI57JyhOIhokFs6oNGfHX2cSQseHLYmNICUx7iQAWFnbfUJSpI5HVgtRkCAazPskHwjYUWzC0EtkcuD2z5jAc2xZ0B4Ih3OQN/RMFDSh9rR8IS1Uvgtk99gYKAiFrbnCli5EhGNNM3jVDDhYtK6juZ2XJQEox4lPE+BQu4xPbPST9ZPcQ86PoVXJTNxuJL2ec19dNiFJCvgtRR1yi+4Hd6hQnFTpCVM2kto/OBh6ieHZTPNLq8VEAy6cAtqU3sl1bDGBOpjey/cvJ1vXFo1T091EKYvp+EdMvEnDyXZSahDlzCf8KPQ0e0iXDEBJwoicIjWzdw/X73BITKuxj8zToqXK0RBEMejRMbYmKGxpXtsQSPYvwDEFx0xdoQcoTiyvuUJq9Emolq9JOKpG4YkLYGIJxBeokhmBog72JpshQ57CRCawOjUX1cHaKRQljUXwQi6bP6pBNn2Uy8ueZjIsA5B8FIMcyGZ8dXok5baHmtAUMAVxWZ+AuFgkZRyzK97GoBx4xK6fP8gbxRpek8CYACRm+HID8owDkTgEoz6JyCDoxtr80AOknhyxqlklmThLoUyzKyPtZMOkBwT0TiGYsHatEbx60w/mBjKQpCUWZXTygWioFtptySjJk7JlcSgwZWWISXFOgQQp+R4KwDd0uUcikxDbwW2TI2PT3dTWQEaSy1Awh4ocMKHH9RQaUaJwsFFrTtjKWRGscsShjLEoPEq3pUaJVPpFKPa7pd+f2Hs/tp8i1zpFrmyOXw8hVTujln53Mtw0hD2763cn8RXA7J2KP7Ou0s0zvUq4ncedPR/ig4Nx2n4CV24IKzmT9JgEbHiVg8yNRd7m5AkujmeP7jpZuGLm0lGhpng7Xx1Z0irFmjrHz/lNKdqQKDgyzWXjmv6155BMdi+/XNqyzDdtsg7t2kfHbu926Rq4xSf7ZObucd+v23Tn7BQWcLPX3WViwFHWw8euchb3znsrv8q0n9axPJ9qElsA81Ib+JHeV8gQiuTwLA6DISDH2eWkITzFCpZ1WIhJZoKJsCEpkJ/aNISjT4ffCkJEXaMu0ak13Yp9t7OTBOnqrzu2CImP3T7W43067f8mQQdu70wwZqQnjPUOQtuFrcy2HWj//mkOtAyBHtrB9XGiZkottZaik3y0rI7EM2Su4jZVRWGbsQVoQUr0MvdkHewOLHt4oITuhIkOQxGGOFUXI3kDsO0VG5h46VsQEcqoNFmjWzyD+ECRDkPjhN+2HZ3I3ci2ve0I3RaDr0WsoiiCgIui3Y4oiyF9TBPmLR68966JP6uIkDm4VwfZoL7M+VwRqzi3rR6e0dlYEct7uCJbDeX8ke5nWyXPmObzuMjzvDmhVQHqzIz32TB/ELx7QSjEnffZT0qfe/zHXUgHYJQ2psDKpcM3JM9NJfRIB6d3Fv82PXVW6uPh32/H2aNO33lCstu/EALAtHq27N2LAzGLAPjo0nvNjSs/7QXWauRpZ3J0uEHgBz4md6YLPjmIvUmb9Gpua0/9vsmcw9UjYWjP+N1pRZFC5VckyZGS7lNIMGRm3EDJDBpUbbQjCxYl0CFm2yx2Zq4oQKm8uR2TQv4VQy1pDKrfKRoYglQNhc4ScMmhLELbVb4kwXfk/Hgye2PUrq1fJykgsQ7N9I9XGLon1iKB6bcrbUNSSSlQZ9c+6QewwXuGFpY4g1bJ0n+dUmzxBKNUq5Q01fHA6LB1Fh90EUGJ31uD3wrpEfQHrIVKEqAiVmJlDeWz9MP2g/WQO2lemKY8SVMil+35zGmjfiy/R/l/OU/JEwDJf4F9fT+5lbe/uZaECODO/RuZ/QvfvEwDkSv5Cr+Zf39A6iN48vK0fZw2QZg1Q9MS4oG98fiMGtB5iQJg/EwN/OetqTY0W7k4BGOQRPcjvIlkw74TlfG4t5aO8wUkytE/T3OSF5T6uYsNnyfLCnyUH/LVLRLsAzPXAyI/rcdE/jy23mvSAuM+fhNkPid8/D+2i8t2tNWvHoPl1gidJhR6fzPXl/QCfL94sl+zy/ueX9q2x+c2tsc2LkSYz97fGmgi5dN7Vnfo5daHyrE/CKXWxjj17Zixji1UDotRkfGLIONcalNoQpEBrnGDI2NUOCqzI5YlXRQYfOREQsexyOyArQ4gQspkg7LpF6NeQvtVFwe7qk013bXDkacimuyJE2+VsmRHjXn3gdYa2g8V+ZOjDcU+7mdNsPOj0sJH9AabQBCLX8XXYNGmUJlHa910MKU/sry63JAhE/zoSzwoaQo9FjrOCjhDxh6KiPPGDDMU6IlqyBeTqJnhiAkzJ9ZA4ALW8S2mZ6DcikGqZIZBUk6KjtsTaQxcS9VfKEOnUGA2RoTe3fv2uy6DWYvujxEj/KDH0y/klLaLrQGSAEETTIgr1kfxraZFBOV/Lhfzf9dFNZmTWR2dR1C/TPTwVOeUvzKyH7Jwe+SwXcqGDYs2FZP0uFxIdksBi/udcSL6b4ScJEF3V6U0+AixFnjX23R8iLrP8WV9PrrQ/VyWm/rnI3Z8GbuXveGdinbMUdiLWiU3l48OJ9h3fHU4oKx+RvZr/KEFfHKMM0fRfEB55Lw==###4836:XlxV32DM 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12cceNq1W8uS5CoO/Zn7ATwNzoy7n6+oCNtARG+mF73s6H8f8RKSSbuyK2o2WZRljMCgc3TA/+i0+IdRWjyfP5xVD/H4p11SqVzS9FJ8Pn/qeCS49vzzSykboKR+/2t10g+nt+dH/vnzyxz73i1yfTgrnx9+X8CyiONgFpUtDiw2JcssOlt8tmi5EUt2IJtUccFr6oKx4AL8ZIuT9HHZOb/ranHUkuv43VTnVuaCyJb8NGv80iy51FwoDS1ij8RU+7r4+jjFLLmvTtY6G7PkvjpV+poUdki2hlzIg6oEDmqpVHpkXLFE1lDpkVXVhYU1lHtkQx3UlTRU3HbRVUtiFpUt9UUYyyw6W9ZsgenCLCJbltoh+oZah6Sr8yfSSmX+hKO+ooNaymuN5UUo4rZuDcHPn19y3zyz5A5ZWd1WzJI7ZNtoS2bJHYKfP392qJT9lvvDwM/v/8ISSI91X/QTVgP4vXj1/McYGCq/i+dP6FFeFD9cGaG2YGQIZQ0JeimWS5JcihoX32nFyQCL8Ce8/moKB6215VqRNgevIl9a6CVXLjl66SiXPL20lEsrveShZV968/wB04yYkoS7PQ0WMulyKdBLNl9aWDM5pHhH+55EucSepXLLex0OWLLUlAcP1iq9tJdLdBhSaWanw5BCuUR6oUTpxU79SzAyuzU6D3OuLX7Xdw2em2eeAcsDIuVSZkB6LPY4+hRQ4fTqYbGeX70Sx/nVKymuXr0SgQbb7FZ2yXG3wnBLd7eMX7tbENZ/wLKiDZZZwzyV6+SpdLOn+4QQcpkQQnrudA0Y3Om0dKfVcnSnF7uh0/rstNKT08pOTqtlclrJGdbUDGvm7LQ+O62EGk7vOAHgHXWn18npNDt9TE434JUnlD05reXsNJseEOhXjH5Gc8RdD2ZBUKMQaTQHwk2xOojSYHHMQlDaGGLhKD3COQwIwSeKG9lC8EnFlVkQVs1xbMyCsNre3LAQWB3IBSWK35QOGE2JAjjXxzQvPoZCYqeWAXewyBOzDFgd/KZaBqwazS0DVo12xMLYgNRsfAYbAOcUfdyAVauQ3+QgR8ATYDVQy+BR8P/O6gxYNXpjlgGrNVYNS4fVXy24dgthA392aUWuJZfH9pDbQFyDiKtfIi6H14Dr6bSIOvLmGZIx1be/FFs7oE4ouiGKTtDpETrhaamhVoG9DGz1qd6Xvz/9Ghuq+ROE/VxVdWRVofw1ypYLuxVlmDUP/BiOxIJ4pMcAQaR5PQpKuBo3Ygt2oswwe4F2YrEYoRNHOw5t+/OywYMM+4iy8LbDDLO2NWxF6u2qMHoV6ZDubSjLkP808tB14GTtG45g6eQyd3IfnTQ4hGrHxlIP3xM62svOSn0eXXsD2mLRY3TlDNqXDmzXDvir0U7zaEcc7TBGe+Cw/Npom90u04QdoO8tdtoBQFHQrz1Ct3s/ivszJ0u+uw8sqrsfBT7RfnmylCB5hv//6OTG9IyjD5ZxAA7Sx/P0FuK5GwqI2/RQFcfAbF/qxi9pUr5kf/9bVho84vlvmQW9dGApltJH/snomlZSLz+wVcTiMYqxFj/KL1ROQtDK4Fav3IvHKMZa/ICQlx22Hbb6XRm915gfG4SmffF770srHViKpfQBATejjUD4zC+VkhWB6JlLBYda9cJYoOjRmdicgRBdq1qsahkmw70b1kqtFmBCNTWuVZYHpTO7tcSCrhzDlTymurRXeUNtmTAIuGdl90i8B/kH3OPoPYDu7Z7Ba+Aew54j8DkjoRcI7qJykv6O0V+Nz9jQF0epA0zOxO5ReM8gEQLpRS5hO6G1A1c92h0TFuAui+8h9PcQ2kjt5O0RctToR38eIUdbqjJF4TDdqoshNQOwtT5QRT1YlMsvLUIYiYPJWGQy5iWToflDoytcTkjPG77zhpwA0fEite7psGkmO6fYy5xiuzk396esG+Jp1DMGDoYREHwXFxjDYOlUpRE8xQ7PGx7yTorN9Mz+0i4SP+mdfuHpnPjVZO0lcKtZAfiS8to8hblaSjTXAqSlJhLzZOrpXrWMdA/q7KwOpohgscyCaaVM9mAWTBHpEotMbmthalhGXlAnSbewxZwWTxsa+VmLIvi4kbS0GDQaGiohWeVRn2JSpBZUs4HRhDWPnIRUBn7Gel5wPdvr9XxexFFMizjKaRGHSQTo6/paHnw7ZVlYylJJF0p9V7reWcxryp08KXdNzMu5jqt/Xyt5YVby4vOdyHNg5OnhBpKnIgo/dxNXdR1rYCatYwUfc6yZAkycA0yaVnBLcNQcc27kPPA0u25epyTgKXJBvQeWkrydikiWikCDZs6BwmhwQ0YrA0tF3k49lpeph4l+zjDTeCcWMz29ISxqNWlnY9lMET7MLyCdOu+2OX9Yhg8jJdGepSRXouMk2qk5jJuL8XB+TgLE8EWNfH7kYn6SF9dZXtxmTXQWcpUfeEiHqMY4cwF+q0QhIIdYlvHIkyx5QlsKXK2VTHZziQOXb4BSRoiB0GYrW2wWYJSlOlU5pQ7sHoX3IDCBZSUtFEb5AaGjNLG6Xt271kSeNISogxs7u0fhPahAtsmu2j21CYiEtfUNW9+YBAmtK9p1AnFpS9RCMbtsdxVv1t7hvMZJWtCCjGr3VG8g4FeTQZPhWUxaN9rPnCjUfg7dtk3iMRYCxwIVXHiOZR5K9BCTEvhfoxvqhPvrSkyELIAlMssgGGkLzDLQPXleBxlBw4zhpkA3MeeB2XXQ2mOnG57rqGVwkF0Ikhy0J+piqEugSNN91KpBNQPwtT57Szqh457bDw/9CIN+OKQfy18JoyfaoeYMo2ukjlMDvgtocRdw2vpT09ZfJRKMLbTdQHXaWYQAuYkZGjESJTcEz8NxwZMh9bwdJLYpSAt/RsnjWg6FttUAiviWHHoiDmrOX84AsUAzN5tmTqIPiw83m2bLdRpiZlSwM3692HTSLA1p0zJT8+wzC2nKRGIiWzFSWcksGDylWg9mGaFXWc0sI8gow+qMEAV1FmoZGyTtJdc1yzYhWDDYBEZVtrvR5qdq97SoGtwpKG8CYwnbaqFhcRMYFtnWyt7Sl6o4NGuJBFLsefDzqQRyKMFjJHAsEtRNjh8unLYnlL7fnigdvNmTkCKkeZnYsUX6ZfEeZVgpopibiNiE+7JiTZuQMzP12IT/sqpMm1DnJobim0ncVxXfIfSKvWFeGTIqOpqjH28ppsyzPuDd10pHt4TEFDKopIipVIIJVFSHcpjI9kpVBC6N9qIcRXWShoPf0RdVH9uE3zqlu4VqrVAJ3YRn1w5sokrChvhS5d/SyVaSWFJUEpZ4Wqt6S1XmypbwkUUdL49sJYklRRRzeMnKlw4A/MPPWJUrrkr/udxXZYHvlfuyiHB1esjPp4eO+fTQOp8e2t46PeSuTw/p+fSQvDs99MaRoUYl7qPZECI+Oyx03ImbqDZch8dF7suNDOESBq9luZM84/9B8uQ7UossgHWxQSldxOTcHOHmVJGfTxXN55/aQSM5ywmfnSpyJ+3E+2uCBCX5QuV5QZDsnEHru1NF7xwlknzDT5Ws4wJhiPTxdYSBqGXnvH3ICeO0EhGSipzAu7nfCQVUYWBs2W8zug2mvqhXmtL6zhmocKeKn4Y4XSMs/DuG2H0RYRvuAWMr77MhXG6XIRzLd20ndn7jqjnJ2m3nl35jR6zktnbiunmWmreXrVp1qmC0d1GVh40rK2pthLU6TQB21YZYKCirni/XPhOctDF4MhwVE0t1sosc+kZivadAcbmHQHGDzX4PAfe6wMcoCRwlFIUWPP9U7ib0nqbk3rOUgIgA3nOtYggH3nPVZ+V1RrpCBIpiwRQH/qcWnheN7GfzbA9XecMseApMKqeZZezpyq4pVQvZyUVW2OqgliGlSN2yL1RXabDVLUyMEYbOSbJt2hBkPG5ILmoxzDJkGmUEs2ByBE9jzg2hBf631EKFFkNlkzpPWrJUEFqZxwY/g5htSMzWz4WTKObNmfRC5OxqyZR0fca/JtK1vHVke51JV47Opxzval9HXe/rzEpNJWNcqRFfZ1z79zMuE12604ysH5pRvNGMZoYiLuTy6PY7ocia94SiODd4q6DDnC5v6yr1tt+QesMivDu15hXhV/YtUjgxweWt8+XrzAS352kw1huRwH6DSACDoa63jiAyI4dz/rjZOjLXW0cvpLeZA2eyyXpujhvtwvpvYZbhjlmO4xBEh33BLN2XmOW63jLL9GJ5zczyxXmLv2CWwoQb7cZ+g3ZDFZXiStVOYFL3ojlGMZwUlUg2SPhncR34frdqVFI5YiQmQvkY6wqofbKP9Og+WblH4j2U467sHoH3IHsDL1DzMQfnfmskQ9IUFxiRVjIHlgJlnNDllTzxdHzQ0EdWXSg/spbMgaVACWpbAKp1hLJtiAqDkin+PaBcEzHR7wHlGphlfA8oN8EsSCV12NnTyKd9co2sDpLZFr+r5XRCEXlcnWVULAwmEhMRC6ElT55H+CdYHLMgmwXLwizIZnXcmWVwVqizszqDswrj0TfP5cpgFTFRuVL2j1jq4wZnbWyh7qompuA3XK+m/bQ3sIwt5oR7xDvfZhz5XblH4T1kk3LkieUegfcgD97bAca+AVCsdY9wYWR3XZHsyhJ3chSCn0F2dyS72+3ewGuaerz1keELxuqQsb78svCSpl7tMb5grlz9+/RwkpxJrP5rEjsx131mrsffMFdZg8IFn5N7/A4+59SdyHfE90S+/a1PB19QO3cpR56+F5Q1pl3wObmn7+Bz5Xz79e6q+Nvd1RcU77SF+tlBIT2zPXsel3TN9uTx1e8f/gemuW8J###4636:XlxV32DM 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11eceNq1m0nS2zwOhi/zH4CkOEh2Zd9n6EWqxKmqN51FlqncvcFBICBaHpKvN7as1xRBUiIegtBy/75u6f77p45C38TN/Pom1WJv6+rv5cjh0YpHWz36vq4BykllJJRTv75ZababMxIUu1Zlc0xRoDgJCvzmylIUVcrIdWGKAMVEUEwOvUyzyperqaXWoz0ts+ygaFevFlk92pSrqVYmoKKbbS41q1fBlKUoW7NaE2VJIYMU91pIWmKclqGUyrUm4TZ2PVGuZ2sh55kii9Ls3hRVit0umdYLC1ZkWy+4uNV6SM/p1gsuthFy+6Ek1VtkltqipIjSWyRda5EhFfUWxT6uhl2v2G1kqykzpVjX+ltGzZTSC/BR+8dSpdq91E6VOVKl9gJ8/P7toYmlIulv5ibjr/8u2ebb5td0/2fJJt2st/d/tJYZekjcf0CT4N/3/8B14Rv+YldoUVrucEqbJhlBJVGkemPjKVlPKXIq5npqoafiHaqLe7tmDPQCa/l3MvTUVk9ZesrVU46eCvXU2q6ZNipZkOBer9JajSvfsX3bVgSeuf5d9R/r1v+/i/btdf82/ZsalH2pwlODcqqnVnoKugJGxZYrlL+KX20gwER9L8Njb2qFG6uczTdr1/0YHxVP46KkuBoXJdJ5XJTI53FRIp7HRQloxY9yf5eL4v1zsjR2S6WDm71bqkM8LF3EZOmKluKpOqTMaOkmo6VHo8+WSssshYnKTZZme1iqZB596tDS5bD03JGHIefaT1WWobW0SiUUVqnEUaXZFVa5XVV1NEyFaaDU9AAp6OSTLeV+19wWM2yRaECAS4nUKha5tym2Wx0ezPosVHeFkwrcrXS6UVZTBacbmKKyocqYvPp9NJQxFUrP6iFTodpWpuB0vCRPLeDTsUYHAz1SGlYcd5+pV5TW7kx9m6g1Ver1WnnoqDZdJ1ayOFtvWi9lphSn7qvTEotjSnHDvtmxrsTE0uUg7aJJrFD1w143E4fiuIm5NY7qhCGk0IIpgyHUaqlCvb5dWBmkC2gWKzMoBoZi8EA+eX2TaCECHspspBCBCBj9nSnD6RPnWZWBJFJTE5hrF0wZoCBlcOxqB3bAMyVqn3t4qvxwnRldp2OuM3a/E7f6SAHUNCehlu5UQvteQ3cuiTqXH5tq09CmmlPSytQTYEV93Ayfgo8nW0Hr+ySj4oK+ItEKffdWzasVQmE1lIZWf3SqImEVy6jC4zQiP63CTlXkFavQWAUgxVGF+bQKd65CiQWrMKMKhB64Qz6o4qdVwXb2L6NShPu32nt4aMeha4ff62dB0v14dIpWkRRGuz2ijiiNIeGG4KuNUmNbWZQKjyOLR46uNkz2K16y82+fY4S2RGmV9aVN2iKtzIWjsn5k8cjVo+/lgy056r/HkoNgeL0ixXBtSBm+EtCaFCJI/dubtJXnRcK8CR/4VG4Cn8r1GmhPDHLQq5hYlwFtzDPQpgloC/ZeAa17C2jDDLQ7Au0Jjs9s+2PtSNGYFmmztKbhLf67tKaRLv7L3A/oxVOqXNMrwr0oxfuBwHgq3F/TsBLyMQ3DkKonNGyDGeSWZho+g2VHXzGBMqfhONNwmGk4M8gyqU4RFzQMluJcbJ17QsPuLRr2Mw3vk9GNrJ+BMRid5pnXDqPHYqP0NAFjZo4ykzlKzqBqJ3OUPplTH+ALaAZzVjTHP4BmvOo8yire30DpRb5A6Z9ax04e1VbCifBbEqUhTpnTSqGcDgn6m/BXb3ArxNbtUFFkZZDM4HcmSq+oMnYfTrRuICKYYJjdSKla+40pSKlaJ8sUpFS42sqMQ9CDqw3jPCUzuBpXMIQDvwNVBn9BPZ6VQZrTRkimIBvC70gUippwOcXMRnIFswMdh7FsgXHQVBnLFihjmYLLFvi9MAWXLX2SGAouW3RYqQV02QKFdtpWJFfAGlkbC4+Bg4/h8SR6vO2hx3vp6eRbnm6ECF4y7nBC2p18SY+5cCfEXZWYXFXzXtxVSXRVr5F6+K9lDso8d2mHs3oV4AkPXdo1zMPjNoUMaOQHFudHyCBH5ute+bge3nnl4/z9YSRD7vv1GkOG/QvWGHL312sMGfzfrzEsXOVJCGgV6OmMWecQEHVYZ28jZ2+jZm9jZn+4XPV3vF4NyRD+fjUEnRHPnUGCU6tAP6vtyvws74x8f8P1LvId16viyyiW3NP1Ek6WEONfL+Hk4XTrs0gmezBDMAUneyutZQpO9lZ6pgyn0m/GGleAkSAU0UfmUChF9Lm+rHxKT/CFIIaGikRWj2RRWh7jvvwsjxsexnGY+KJUCrUwMxEarDyCXl1BaIBGO6YMaAhZoJGRrzqlpmVqCMgvTZFUITEvefjL1gS6Uh3L4tLmtgQuTT6OIh4luizWqW7+YLm6mq3l+lHEo0RXuNBNuAEUPA+vyY0pCHHwOxCFQpwUnhci8TUZmTKwK64b9oani2z4507L0PCaY2aTCJ/EIGS9aci2FVS0E4mu2SUzga7Z4W4J7BGhwdpMFEI95XmvUWtV5iklBtsoZJv9je0pcZ6iDmr5yoX9iXweL/Q3XOhPq3v74er+bboSE101SOJ0Zd6iKzUFAnq44A9jl1amcL20l6scTsg/2ehquMMJyP/fVvlSznFEAkPpC2AI+mV7sq22whJ+7pcHgYTtcgNQ2g+jB6ceWJ+wWvoSVrPyCau5oB9tLM6spmY8WWZWs2+xmp5jF/J8Z+xPsC2lLwhiS+ufEFAKf09AUmR07DAILA1ksVSh7kJEqgyHBbfySJrY+LaPxEizrJPJcBfUmYHEnFlayPVIPAB+r0wZe0UysDJkd4fsIqWNJ5VYXg9JKsHItMRo/OwajxB+d42YBtIuN7ae+rPelHDKKglEofEAynTHPkLvxeNwkJ71nOkohdmdUVj3t796qQu+tJ7yJWUte6Q51VHrR8hf1vOEp7FPXBs+UlnUSNupCiHt5JlCdoOFowrZjxaZXY0EdlJtE1reyK5Y3o+QAK1ntCdxP7j2MwFPaBR7RCjuWUkUhntqbI3WQiT1y/DLHVxZ2ahyk7mt8DHYaEE28h+l7nwYCorvsFEhqM/Z6ARArzZB7FubIO7+hJhebYr0HRA5g8/MVX8WdIpz0MnP+yhpDjrlZ0Gnp+hVV7NX6OUyOitnwls5Rh8Gn/xb6BXPDjY8Qa+ovgK96mLpEr2E+RS9Tnz1ag/HvrWH4879Ep8AWVy+JHgmr7eJ4H7B/Cm3f7hNNLdYzZswBdt4i9MT1Ir6KyJkfn8SIXN5e4Sgc4RsXpz02JeYM7jkKfZ1HSE7dUZ+AoXxCzIbyBZ+udcYkJFYBUM/8FCRlOHhgIAeD543lhxMghX7OU0osEIE1oabrArCGvzemEKSgRZNFZIMhFzalIdZw2UmInxnCWIGwVPO5JFWXQvxDOCBQEHwDOCRGxzEKaSYmYK8KGGkqcIS7xZWhiTeBUkVmsY3srSD5FnnfmcKyfEKiiiMceRIFA8MjIDCBj8GJC6MtNmER/lEYQn7NXEKEw5h0O80aknyXuqFB/syjA2IrBgotAmPMsNYEVZaF4lPYgpLU0ZMk+F7GKA+4rA2jcN8mSdUTSF5QmpVrNkkpuw9UXhMWWdyOcr8NOHd7yx7UVnPlCPEWyajlrCpC5fqwaUauTS85tKYZi5d7m9klz/i0vxhzI5D6DpD6D5DqJsh1M4Quj2FUDVB6Msd0Pe4VH3EpY+S2N/J1fH3p7hZ98MvcTPJ9yJ9YcYqcX8nu92/ld1+jvTF9AQ3ty+J9NWUEXuVQJ9GjnhIDDd5J6wzW+4zW7qZLeeEnIKuvBPyE7bcviTYV12avWTL8KgTlgmrzFu7sO/hpj51QhJPcHP7kg3ZOm/aS9z0jzphe/ViwpO8poKhvI3yCUVuX7C5Cr4Bd+ygQ3ngxAxfc95ODEwhefnbxpSRQy+XxJSR60TcfESXHvNxBGYdR5K5eYK5nm1D6ojZubX0QAr4J7WCe12PbAwVsUhbSBuRLnZy4wCEmPGwdOpxKDk2UG70+RR/WjWRGNCNty985i8HmIUpZMdTBaaMFKtUbxXs+0Z1MR9Hpff6kaSkBz2CBB0ze2URdxxbXTQi7XdShi8+Nlx8bJIvPkbgcZOnYPWSWSG6+NiYQt5EGG+obJLlroWEwx8T30MdpLZJ/ibCQNeY2Dqie5FWaOEx5G0hCn8VZoQqayESfx3xyKqQ+OvKy5AXE0WgCou/RqqQ1w9rQqC8AfbeSOaaOUixbPIgKR7zGnLbmHd2TjZvR9jSHGHzc4QtvJupTNK4dC62Lmfa+deS3YEPMeHmpvOaIU9v6DE1Hyt+6C8j8zWQpNX/PZBoU+csbnp293+D6eomf1X9N2lCdwQaB6LYvfO3xXzPX3SXWb2IOc7mz2IpeXb6YXb68Q8Sfft0WzITSr/zRRhNyNxPqb5pIRLxV6AEppBs2iSYQjJwo2QKydoNiSrEI5ljL6QpY+E5Ukxrk+gca7YjDaOMMIxl8XzkFRMsQ7Jl7LHr1xRofitd7oCWbNttr0ftpbT6h/pSW/2DoD1Mt9IwV7iWHXPQ75IkWd/xiPyl5c3ivGH+bIX5pzsfsDT9H6XkhPY=###4264:XlxV32DM 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10c8eNq9m0mO5LgOhi/TB9BsOQJ9lQI0WEBvOhe9LNTdHzVYIi3bGRFIvEVnuf2HJUq2yU8U/c+i2YM9/pLJ2IcSQj+f/yya41O8nBL4lCynJJx6fsktpHzwx4vEVzha4D/2G36rN/gtE89/4TLz4CbwZz6bHkYl+fxLKZ4eVq7QlHS49ZRbVxqdktUGbKlks6VxtjR0S/up7XkwOvekqNGqG+1jt9RDU2zLl8G/qQ0+LuWE4tH2Bu3coB6zwHqD4ZUG/2sNit9/l6P8i+cvuy5V0l3STVpikeJmurQ+8oCftQHoEnQpHUc6zBE06m1RNk0UkZXcplRsIQrPiinXBEkUlhWdFaZJP0pnRRVFrViRLiuyKhKNOE8FSI7VYQ0THB1WKoZ4gfQ6rEUUJSqi5GEtvAwLTbBrwzJ1KpIhSh6WjtVEck0ZlhZV2bBShqXaLRkWmGG7HreEIb3YvmxrvSWKKCIrtt4SQxSelaXeEkEUlhVTLYxYybYvW71ZSmMl277EUBWBnrR6S5a4Vsl3aWkXwZ+iKKyUjpSuE6uxUozTrN6MhSh5QJrXGyiJkiehTrn0nCh54rSsU477IVMOj0t+W1n2PTw8zEOw3/klTY/Vw7NWX12z8f119ezgqfjGj56Kb/Loqfg2eSoeJ0/F43b0VDyCI/xamj+AuW7/Btx28W8bscCVUwafWsupBZ+y5ZTFp5ZyasWnDJyChxedSiKfIqYnXU5FfCqPGd4hfCpPFrxwuPlUTpG2YP6+wLmVsdryPsC/HjtwVhryCl+1lVO6/RqPPfkitQY9sQgmz0tu1TFo8W34f+NPghZEmkPQYnPQ4mwKWmybghbzU9Bic9BikQQtMFrORsdhtDuLtMfnV3A/G+0mo/k6Gc3tZDRfJqO5OURaFiajkxmR1pwZLSc8UJPRwkxGCzHjgZzxgM94oI9G+zumgRj3CtNIPhudutGTpaFbOpk3PQjijl7M+ja9FH94SS8Qud+ll9Jg8cDMEXppxoNUjii9xB5E4Qbsfhsa2EPlGpFO6YUTBdOLJAqiF5+IguhFEYXQy4IVQi8CjZjSSxzNBTqsSi9uQzqlF0YUTC+KKJheBFEwvZBrCL14rGB6caHfLdlsLzeu04tHOqWXRBREL5wTBdNLJMqgF7HPUVUQvQhnsILoRTiJnjRCLwINSxF6EU5jBdGLYgwrmF6EIAqml40omF6IBZheXEQKmfJCL5KXeDrRC+/0Iq7ppRLHFb3sPunCERWE+QBO1hlOzAwn7iU4sa/ASWUMCidyhhM2wUnjlTL2CyK5wRDMGJRIdn45JZJYiMTEOyLR5jUiCXdE8s3tLVhC4owJd8Ch9cfAsc7AYWbgcC8Bhz0Yvcg74NDhY+CY8xFnmRPxauYELBV3lKH9LWXcoMUhN8LnpMopZWzHu+/vKEOrNymj+a1LytDuTcpoDRZPCUeUMkyPS8YfKMN1b72I7l+hgR7SFqRTyvBEwZQRiYJzJCtRBmUIj+3AlCGcwwqiDOEUGjGljBHtFkmH1XIkFumUMhxRMGVsRMGUEYgyKEO4FSuIMoRLWMGUsfZ+TOi2w43rt0QjnVLGShScI/FEwZSxEOWUMky4ogwTrigDDL6iDPDuF5SRFZIjcVghORLSGqEMSxRMGYYoiDLWhBQy5TtlrGeUITplyLcoo2U/TlY+LaNCA7icEiM5o3LBHhNwhBk43KfZkHUGDtmB40gZFTwKZUxooee8B/8u77GjBAGONOU9drQ45D+KGbC6E/IOLYL/FC1aGuNsNVtTIzR2sznDcUzLC3EHHOE+wzFRhp8pw32a1liPlOHvKMOI1yhD9zmdYjd/HnHtkPmQB8Sg5rk7tDAvbsrEeVPmmiZPtl8ON5ff8URY3+eJ9Y4nDHufJ0boWg97LqInGAQ/8kT3sYsbgXcdwWtFOuWJSBTME4komCc8UTBPMKwQnrBYITwh0YgPPDEwyNNhNZ5wSKc8EYiCeEIwomCe2IiCeUJjhfAE6YfsuYR+t0TPuAiEeBLplCcWomCeWImCeUIT5XTPRYirPRchrvZcBL/ccxHyas9FyANPWKwQnnBEwTxhiIJ5gvRD9lwiUsiUF57gQtUco3joQROy04TCNGFtOFso52ixiurqldDlwCtf00nnvk7kZ6X5ugXeLezrqAdNxIN2c0mrsjuXuDcqttGoy5b7ZnnNIQC0SWLvn/+MCG16SydZeP4qf//817rtGlz9/AVDBgnG2V6eMuI6w+VX0Bfoaef7IiM3oyJTqE2wEBQbyk1h1Zvoh4U/47aofls0ui1fC2/0RcLtK1tf6SXC44XwLCY8+H/39hbYRHrmVdL7WlLDOlHjl21DPBAgf2U/7AQGJwKsKaj2tNenHohww0T41Z6lY5Ip3SWZDvxoD3DYX6NVRPo6GZ7utsYs70++THymxSucOdsEiy8h4uG9ZOU2amreHvQF7y+7iINlNzzH372feQbuKNTykUHy7tN9tolCzQcUCpOxzpOx9cmQYzJ8N5S/ORl2vQFdeDv3PoxkN6ArX9q/m5l3ctPiOANumoFk+wyo4aaHdfrdx4Edu0AsbXlfPhm+0fjyTemSPCmyijPah+OI/WyO7CPWY8SGBKaXR7wHKA0BI79tJTT9XZ61fujGoacRTKcdh4uWYxMEsFhim2mxrUwpilDw/xwpJbT9qlFtj1CtORwQdY94xaDSU2VXzvdNv9ZTh2RozhClgzVYF4jSYbzFz306cvyss7EfuX7kUXTNfTlkXzUdfHtucls1bnIJe5PtyPUjX45+5T/FSL8baVcM3e093ZU2hQUB4SJLLupsDRauROk8zoWWROkMr9OePasGl1kXssy6DfiaweNwPwxWBsPDXI871Uj9V3YqxTiLOqrTB+G5UlJAVyEWby/rUDq/w8uZiNKZH+wmymBxzpLHyuB3mFNDWuvMD2aP+bG72dHWqZNIKlNXyR6MG2aTfcIWjIbSiVuFDStt6niZb8YjvmgsB0BZSXN9OcCZoB315QBco7DSlx3ZGZVlG7yXDz/oUXd6NIQej2RHUetbDLpEFs7LcK+YgP0AE0AX202kZT8QaaGLdBPK2A+EMs4Fu4kd7GdjR74rLUrk2euHqR+CNSR2qLhHiKLh2MH2/EC9Cq+LhnvOPVZXnDvcj9J+lJsc7hk62yNL+Q0KHyxFpBwcN8edFSddOmtHaT/KnQ3HDZ2F3uSGvSYoo7OInQKYga8hDrA7pjrLw8nkm1zKxESGNpy4N/2tXK7XdHQNR8sEpu3PvXzxuyLHhPKB3ziBq/XWx1v8c/1hW3KJl3zOWHqdbv2n6wrEMC/FtpGUv1t/hdv1F2N99RHiTbZ+m7P18wZxKzr8rjQxniZ0OS8bqRdul4cfcbslUXfhdvNT/xMLHHe7wPFnq70frBc4KVAUV/OtrgMEPDY/sdaxy82+QfZL88N3XZJwsllw99lGuhq2vg5aPPxw0IJneg9P8Oz1QzUO9SFobZaji5v7h2v3I9WPNGF5vn8yUGYdL1KEVkRBixTNidIXKVwsjChocWUtUsjiqoWK321YJKqOUJztRqG4F3DWacHREYXiPBU17OapaEeqH+mrUJx/g0OxJwMeWxdgBlHGdkd7iKviDoskhxS8SCLrJ/KhCJiAL0KLF5hzQa4ZCyuhIlH6wgqH+zxFKNyDb++KJOEe00OeTbzmWjnuaKy5WhwpSjgsD/iSkA14icKFNegqtNyAFc9GlLE+QKuxQBYvsAzXWBkbFmA3wwpeoXii9BXKHy/r0z+VJCw72cT15rMNdleScIAcPieqP/9s45VyyJPqhPBpOaSec9PilW812ocZp2nqFwoVtmOhwp6Ovq+MxN9q4IrIY9IajPMinWVmxxbyyE3fVzJsd5UMB1zic3r6vc82wGh+V9TAw3tFDetLRQ3+k9LJmvS5QiHt42tFDWZGIfXStxo3tYnyaOld6aT24Qc/Oj2pokTfauDqyYPRGX/og8DuCiC4f7cAovrDqwII7f27BRAdL8oRLYBI/VOEkqLFBRDS9qt6QWVuoO22W7shHRdA2CiIMgogVqaJMgogbC9zqMpZAURRTgsginJaAJENpgUQcu2SpMMqBRC2V9BlHRdA2MCJMgogVm6IMgogbFJEOSuAKMppAURRcAHE0nf9E++78Tmvvd8Sg3RcAGGDI8oogLApEmUUQFhniXJaAJGV8wKIrJwXQCR2WQDRM7VTAUTP1NYCCDtqQXqmthZArGwjyiiAsH4lyiiAqEFwKKgAYsHXkClvH53KeEYvttOL+z/Ry/8Apn93lQ==###3696:XlxV32DM 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e58eNrVm0uOJCkShi/TB+DtTobmKiPxlHozvZhlqe8+gHuAGTiEe1aONLOpSvGHEwZEwBe/GfH1+nOT/It8/cGj2r8E9eH1+mvzW2pKktfn/+74P0jw0qDz00HBpq00bbDJlab97EBDaU/SLuCrI8lNksEmWZo8bGK5Se2wieamjcLuY2lCffE0ul0fo9sNOf63YAIYKR1ZcUpwwLF0aNUpobh9kVBE9vWyLIrcQ34p+ZUUGXJg4vWv9CL1RaWLr9wav5RIsf0h0mNfO/NppriBQYU8iULCJlvWjsCmWJrAHDBKShODr/L9ojOS1ugvHlzMI/s7By3GoH0LOlwEzck76D5SqodI6TZGamukfXh078LjcQgvqhaeuwqP93PK2DCnTA2RMjFEyvgwp4wOc8pkH3Tog2aEtaDtVdC6D5rTGnQfKSc10iG8MIY3LHlWBQ4PfE59jcmmrkg43oWUx1M/54aR9o+9jtePHcrWoakdujsd/vvskP36R/krv+L1z/RVLlIJvkjpr0NKe1iWvGD1qfCVB/w6OkhvmXS+7wboaY5Sp3YvigtIYVnJfXJNKFJoVlR5xjikkKzIrBCJnhEyK6IoQkOFm6zwQ+FgxHkqkmTIMawmRTysWALRFujHsDZWFOuRkoe10TIsypCSh6WOqYgEKXlY0h8h7lApw5LsUAJUyrDEuSSirpaosacB1SWxQC+xp3PjWJKIFJaV/VgShhSale1YEo8UkhV1RIiUHHs64A5FQiXHno7AQ2Hgk3YsSTolD6mFLc+H0j9FEVApbyTkMbEUKiU4SY7F4EjJA5L0WMCAlDwJx5Tv2iElT5zkx5RLoKApTx+Xvy2nJn8NqPtSX4z8yl/S+KWt0a/jq6u8fX9dLen2pIIMeCOlgdSNtNs9aRh2T+qHE4kGOsWQDj/OrRBjiPpdDGEVQ97s0QPHSRfHdntQxgO0qG8UXm/KeKNFldzrTRmXaMGpZSu02OQ9tHAjWoTZ6l3yhB15IqLDJUVKVzyxiSVPYI64PPuo+g2eSB9+t+KJtG/e4gkxhDeQAx1i6gKxK0ZI2/RDRqhvHKcryvx0njpGSMtIVoyw8YeMcO46U0bYyENGODtM+1z5CzLCGXyR0l+YEYiqT9lzdywdvA8kLYCOGMHvSIGMYJECGMEqpDRGYJZBBTACA+OyiBGYEWDEmBHIViWHh3UwgpFAR4zgNqRARnBIgYxgkNIYgRkNFcAIzESoQEYgdWLT3vGOPS1cXRIJdMQIXiMFMoJDCmAEuyGlMQIzASqAEZhRUAGMwAwHnzTECMy0EBhiBNYWIyuIESxUECN4pABGcDtSACOAsBlmBKKBgqb8YAQmtytGMJUR3JwRAl0xQgcCEBd8HHDhJIibrsUFLnRM8IkctkoOiBg6iDAjRMgBIhYGxgVPQG9jjRZvWBAjbUC0GFwLO7oW8XAt7AotPLuHFnGFFh0/0NGiYCN4rF0Ls6IMT59SRocSn4BjG4Peh6CpwWcqk3rpZZB77KGmaHRlYND5kc/78PYVkdh4i0gOxkBzekAKIpLBtXDD7GWPAy+5XhGJJ0+J5NjjpkRiw1MiOTrMu2r+q3Mt6g//9BcmEm7qU/t7L84d1J/IEeiYSDhSIJEopEAioUiBREKggohkhwoiEg5GjImE2yppPKyTSAjQMZEwpEAi2ZACiUQiBRIJUhCROKgg10LV1TLtJ7RuS+KAjomEIAUSCUcKdC0CUq5dCzN1LczUtdBz18JOXQvbEQmDCiIS9AxyLSJSoGvhkQJdiw0oaMpPIiku2EAk9k0kwT1zLehAJCdrXGxPbzLhHb98wpBtxBBVMeSJa6FXwNEZGb7LgczZAydiHmLIB4ejww41pla2EWn2LsuSNn3rFnCiyPd9jzie83NT/SqPYrvjydoFkShy0/fYRiJRc4dm4Xvo7nC/yE0B9kjHxkP26JiDdOmQOYbgnMyaSMbcFCIS9QMeSUcgdMyysNFB4V3CBX8QzIJTFHnsnLCrdA3gFPmYU0Q9tWsK5c0ptqZIrOk5RdSnRD3Qm5VvvQQ65JR0XiKlcYqSDCmNU0QMSAGcUi0G9rbyK6dEqFxzSrXyK6e0sCUeVuEUpwnQIacIMI0ScYpSWGmcIq1GyiWnvBMHI6e8kw1vTlE1I2PboWmrmWWdBjrkFL45pDROUY19rEWcIhoKWNtxCnoGcQp6n2tOsWbKKdbNOMU6xCmypX6sQ5yi5IaUximCY6VxitvR+0BOURooaMrP7EpBnIFTXOUUf8s5WcBJ56B84JRsvXziFDPPrrjqkQzGiHrdya7wW5wi/2uc8saNNae8aUaN6HKPU/yq9ENR+tREWcBJZ6Z84pT+ePKreg9FyT1OMfNI7RSjTpRZ5mesWHGK4vc4Rd7iFPVDnELLB27KKYrd4xRyh1NOM4WO6PKUUzxfckp8nOHRyyoQRR9neHT1vHVfBeLrr2nfVYG42Hx3Xr1t7duhGIGOOYUhBXCKcEiBnLIj5YpTinLJKUW55JQcMOIUF1sCQOBhHZyyG6AjTuEeKYBTJFYgp3CkXHFKUS45pSiQU7bqivhWBeIbOjoLdMwpASmQU3akQE4RSLnkFC9mnOKnVSB+XgXip1UgXnacEqGCOEUjBXIKViCnKKQATtkoUNCUn34Kv+QUXzklfLcKZIUscfaD9ff9lC75M7FWHqZ12KpE9Ulah3zmlDByShz9FHeDU940M3BKWnW1SvZY+gN1JCtkmRcgdH5KilSuMjyW/ICf0lWtTqyVJxmedbWqFU+rSy6qVZ9keFgf3rIu1fJ7GZ4x1cfJCFf+Dqdw+olTUtBilfcxjzmFratVLXvsp9QDlnXVqmfwhyR6P6V6H7VatXRQ/RQBdMwpG1Kgn0KRAjnFIwVyioUK5BSLerusRGFDtSqv3ketVj2HdXJKBDr2UxhSoJ+CFcgpO1KuKlFYV60KbKK+WpVXr4c3LygtXF0SDnTEKbtCCuAUSZACOcUhBVaibFBBlSgeKpeVKDngSSVK3v6vK1GKAjnFblCBnKIoUgCnCKxATglIAZzC4TNoygunsEguK1FC5ZQ4csqH2jxYl/odu+QehpgRQ/YRQ9zr/yHZcwEnsObk4tLMt0wUElcmitVLOPlUkAnKWT96JCSsPJK0C/8ge5iRPfaRPcbC2y7Dk4JeVZcoy/8HMzwp6FXNibLs20RCX4tLM7/pnBC/ck5yLu3h/RmyqkRRlj6+P0Oqs036ShRSjXLiOyLx9Ucw2etvRlIrUbiGOiKSQJDSiES0yxoEV6LwdreB7LP7M2Sf3Z8h++z+DOkrUXwbscbDKkTCDdQhkfB2B4XgShTRrmwQXInC2zUPomf3Z4ie3Z8hXSUKmNh2pYn4tiQB6IhIAkNKIxJBBFIakXBHkHJZiULCrBKFhJlzQvzUOSFx5pyQiIiERw4VQCSCSqQ0IuGeIqURCW8+DImYSAJ8Bk35meEpR+xAJPFNJJE8ck7ONM7N+zOBPLk/06d1BiIxI5HoSiQDhtABQw7A+JTLOZnj0hhhU/a444aEETj8LTfEFeCgbAkc7ttuiH10qyZ8ulWTIqVLIrG3bulOYzIjcOjX9bUVZVaUIW9SBh8pg97Kz7C52SG6pIzSK7SQa7S443CMV7DPy7efHA7fLy5Z8oR5nIkp3z7c4X8Aerxv2w==###4412:XlxV32DM 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GNHBIozodYBFKDm3UCQmxYoi0de6JBlG6ZGAyY4DoGcCxANOs4rq9FLApBavyw5BnBolqum5AE6VmJQKQy8GvIPRckJFYkd2CLeUFfFOkWzJYluCU+npANktc+0hWM5YArxI7aMHBHaJlcplJAOk4NEjAu/gtOwrtUSqJz0koKZKgB8hd6RptmKQVLlcxCVdKhdsoxcFkBIPkvP0qIATuuWMJY+raOaxWRHVswhOcpr0uIBEl35xSRnUEvbxluQ9Goro0MWKIPqKZklcEuSMk8RklXpGTw2oXFIJjsSRgkfPDdBXbJNGlSVS6ckBnUzUOSy2t2gmri6SvJLdWboTPT3whCS1Ws6tSHPP0nHiEVxasltqST0yQNI/u6O3SCD2IKVN6oMkZD42a4IUusSkdCd6jUDPkuzWUkCk/tKLBIJLvF4lC5P4V/pxQRGb7xKbbCjQ8z0CESVeb6LkUQarmCkBTq8SqL9GqpG4T0BDAMiZDxJMJok+qVzVyIQcZW6HFbGsv0KZzw2oVtI2xQ304oDmJCGZj34tGYLImA8Li/SZvg/oz2/mGwP0wiovhY0eEmCkW3+CMym4XMmZFFnVYJjYeCET5isCUkUC55LedUAgLxCzSsJXg82qiDBiL9r5fDuAn9v8X73r8WDvZQ8JUumzBCF9SaBcykmixcw3BEi4xUpkKz0jwGXY1x4FQUk8mgNLSjxK2iWp6fScwGSyQnrRAVF6i5k+yVnl/V+RJoWSLh4RYfSxg94nxVtwUxJ1dRZSgKAWoOIQRPN9gbURjKXTsewSe6TxS9suGNX/B2/KT7k=###6264:XlxV32DM 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tJxUMw3XNByBPbABoSlkmkrLSTXlx5HQNByBPbABoSlkmkrLSTSH/KbNNIEjsAc2oGkqqabRclJN+aEuNA1HYA9sQGgKmabSclJN+VkbNA1HYA9sQGgKmabSclLNN7um4QjsgQ0ITSHTVFpOqin/nQGahiOwBzYgNIVMU2k5qWa/XdNwBPbABoSmkGkqLSfVlN+rQtNwBPbABoSmkGkqLSfVlP8TAE3DEdgDGxCaQqaptJxUs3j9BI7AHtiA0Cysn0bLSTWz10/gCOyBDQjNzPpptJxU8/b6CRyBPbABoXmzfhotJ9W8vH4CR2APbEBoXqyfRstJNU+vn8AR2AMbEJon66fRclLN5PUTOAJ7YANCM7F+Gi0n1Ty8fgJHYA9sQGgerJ9Gy0k0++f1EzgCe2ADmqaSahotJ9VcXj+BI7AHNiA0F+un0XJSzen1EzgCe2ADQnOyfhotJ9V8vX4CR2APbEBovqyfRstJNYfXT+AI7IENCM3B+mm0nFSze/0EjsAe2IDQ7KyfRstJNZvXT+AI7IENCM3G+mm0nCa+cKlZvX4Ce2DjQYlpVtZPo+U08a1MzeL1E9gDG49cTLOwfhotp4mvbmpmr5/AHth4eGOamfXTaDmp5uP1EzgCe2ADQvNh/TRaThNnAtS8vH4Ce2Dj0ZJpXqyfRstp4nSBmqfXT2APbDykMs2T9dNoOU2cU1Azef0E9sDG4y7TTKyfRstp4sSDmofXT2APbDw4M82D9dNoOU2cnUATOAJ7YOMRnGoqqabRcpo4haHm8voJ7IGNh3mmuVg/jZbTxHkONafXT2APbDwWNM3J+mm0nCZOhqj5ev0E9sDGA0bTfFk/jZbTxBkTNYfXT2APbDyqNM3B+mm0nCZOq6jZvX4Ce2DjoadpdtZPo+Wkms3rJ3AE9sAGhGZj/TRaThNnadSsXj+BPbDxSNY0K+un0XKaOJWjZvH6CeyBjYe7pllYP42W08T5HjWz109gD2w8JjbNzPpptJwmTgqp+Xj9BPbAxgNn03xYP42W08SZIzVvr5/AHth4dG2aN+un0XKaOL2k5un1E9gDGw/BTfNk/TRaThPnoNRMXj+BPbDxON00E+un0XKaOFGl5uH1E9gDGw/mTfNg/TRaThNns9AEjsAe2HjEr5pKqmm0nCZOeam5vH4Ce2DjHwtMc7F+Gi0n1ZxeP4EjsAc2IDQn66fRcpo4g6bm6/UT2AMb/5Rhmi/rp9H66/9ygzOm###5332:XlxV32DM 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TvwG/ZtmpDpFKjr5p8frKez3vdh9X/jgqu/7mEN/AnzfbO2N+5z8eavFx1FBvkvr+n1fYq/7Xqq+SyvoNTwJTjGidf5O6zSfI79at5kb0e73xMeIJuHZmX+udZ/1En0JihpLzsY2/0TvI3eKGv5T4ZLk87zNPxPO3xHr3nDIqJGn82nbvtTDfTvelXWfGzzWf99zHB2vxaCoUS37Mv8bgt+3z5Xx+ybhCZwJ4e0ua67g7m+rObY6/4GBz/j+vWd8ZYLGCYqr28y17mObv1r7E+0UI59txMi9tcPbOH8Rdsn8K8tn+R8u6fT1###6632:XlxV32DM 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v4WKH0eUuBKKt9RzS7+XW5HIS9bYER9pft6ltyQbJI7scivq6q3SrrRChujN1a60qCrZiiUPUXdJfRY9Dk499X3PdRd3R9d7KNKNULiSbHpEtMutqKs+ukZa9Vra9a5rl1vRsiSbXW7F+HqTrh0hdcq7OWKPpRYZmf/s3X+3telXQLYD48fZvfMH6Sd/TO1V+KMv34z4/bX/cNqLE3+TvfAD+Q17tdR3GUthrlPKELoDbZl5Zn4O2somVIQmUeV3+WoqZXtln0KXamTVUG93EdKo0tfyI1sXWmpZpccmpNFvVf1G3f25TvX2CGnMSQwdu1BTaWYrtzgYSfxxfNt+qMY3vixbFWIfW19q+RupZnkU2vjLofc7jS8NzTextGnmu/rY1YpWehvq7TnVr1Zrj5nDifBXh7RpZfynwyd/HxcjUCsf4029ffPdxN8m/9s1D3rO24r8b3tUqlkurUffiIbaS6q7n0KXatxCjWhqzKsKqeWiUfVDNv/u//73fmj7dT+ybURbdhNqe97iB5TvJn43+ZmJFpD9qOEUclt5aDPkNvstwCnkNos4p5DbLE6fQm6z65hTyG0v/WEzBJu95LkNyG2vM4bNkNverR42Q247K22G3GaXYqeQ2yxin0Jus/PhFHKbKaxTyG2N/AG5rZI/ILdl8gfktoP8AbktkT8gt+3kD8htG/kDgm0+5A/IbTf5A3LbRf6A3HaSPyC3LfIH5LZJ/oDcNsgfkNs6+QNyWyN/QG6r5A/IbYX8AbntIH9AbkvkD8htO/kDcttG/oBgwzXkKeS2m/wBue0if0BuO8kfkNsW+QNy2yR/QG4b5A/IbZ38AbmtkT8gt1XyB+S2Qv6A3JbJH5DbEvkDcttO/oDctpE/INj6Q/6A3HaTPyC3XeQPyG0n+QNy2yJ/QG6b5A/IbYP8Abmtkz8gtzXyB+S2Sv6A3FbIH5DbMvkDcttB/oDctpM/ILdt5A8ItvaQPyC33eQPyG0X+QNy20n+gNy2yB+Q2yb5A3LbIH9AbuvkD8htjfwBua2SPyC3FfIH5LZM/oDcdpA/ILcl8gfkto38AcFWH/IH5Lab/AG57SJ/QG47yR+Q2xb5A3LbJH9AbhvkD8htnfwBua2RPyC3VfIH5LZC/oDclskfkNsO8gfktkT+gNy2kz8g2MpD/oDcdpM/ILdd5A/IbSf5A3LbIn9AbpvkD8htg/wBua2TPyC3NfIH5LZK/oDcVsgfkNsy+QNy20H+gNyWyB+Q23byB+S2jfwBwWZptduA3HaRPyC3neQPyG2L/AG5bZI/ILcN8gfktk7+gNzWyB+Q2yr5A3JbIX9AbsvkD8htB/kDclsif0Bu28kfkNs28gcE2/GQPyC3XeQPyG0n+QNy2yJ/QG6b5A/IbYP8Abmtkz8gtzXyB+S2Sv6A3FbIH5DbMvkDcttB/oDclsgfkNt28gfkto38AcGWHvIH5Lab/AG57SR/QG5b5A8I/4Y8cZ1l/806t/jXbNpHi/9FQtDi8WZP8Vf5fC8+q2x4tqiUPmgP4vvq8S89v9x5pXv71eb2N7j8XDl+clTSbRfP938uZfhPyxL/sEOVm/+Lj//LFf8zz/8DZgT56w==###7324:XlxV32DM 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St5kc38tc497DqYv1yRQqu1gZoXrwxnvyAqknXKRFVuwlJqhuUGiXu4E+HE7nhoy37av3JlYTA48R588W4ssEs9mwLhcbAGKgCKns9LMe2e/jTILCpfjLj52zswuBhXSzyNgSsqb+ODDh5m+eQTDfr1GJkSwEtdoyjv4ajdmQhoeBx5y2gjDlMZCTr8bbcL9RVGpbIQhqPM+E23iMpMYuhuPmv+UO7uLZqb+381LoLZL6TvMrZC21hdVW63wGb3cacfPZYc3vuqJWZ7Mgpd2I6LT9AacYAnL10ir6Za2z0rqYm2x1kx83xrrvPsdU5xIPtDobU219QEQZ+3dimRoe7eOtL3bRgnPrL3bkuYH0FDOubOVO9BMHgrpvNavxMwy7Cnph/b3aQO3NTQHBKo5ngm+Rpq6jV/HseBLD2WDOMa4ULWPsQSu90YNhtgkaf3CdxnPpKl7a+9WnYqVtUwZ2Y0drGS/FKAwEd5ICWmgdAkDFZKR7ntcBykobHyWkZ3jlDqvvc3RR0i4rfnbUtfDuXGQG9IGjt1i2Zq/0e7cT+4hnQR6XmkDtz20IdxAh4tlqiQ8tbnSMq8zzg5LaSONQw+/o3SyPp60AqY8rayKJWmyTD56OMLK8yFVTvN5gwehXPwlQaTXYCqRXrSQDz8le81spM8OAdqN9wGxSZDSIFrXJcDVNnUd2TkKi/YCWJh0Jja7v/LXycn7ZiR4WHFoUVcUelNd0ZuTkbYAQ2su15rLteZyrblcaw7XGpW2J1oeor89mAVX/VFTYPqTqD+QhLRpzadJuJsTPztAf07Xn9P1J1F/VN5Vf2y9vsjp4fq48qY1nyYZpao/ipWr/pi2hk9OEGKY/hjUyFK5jew2r2PTmk+T8CuES6DqD0b8+UT1x36oOJwbB7mhWgOr4ysvjlR/bA/VH/5GAblLbOg5CaKY/thc1Z9EXXEN+bSGNmRRB0RD7u4aklxDEjXE6LsjfyU50MoKDcn4UcIsr2oIpNxPJBqie6iGuK7gZ6Hn4a8aI7meOfXlcD1jO4NpyEkN2byJ+MhyKDgR3tjPdOB0fyGjGCbAvXwsJgHHgaZhWP9KmVVtMHvcKU+wXoQ448XYSiTBIG65f1jmhR80Qg5sGjZOm50dBDv7QTAuN5ei5vaYmm6cUZkFTIazfyMEF7X96T+yxOXx1q65g3bI5crY+4+0dGz9R5Exn1oj60RCNM/Ko/xI8HVgf/kWYJsr+xTvdtXYdus1qoxZNS0f1Xv4Z3XCKtuVrROpetfRFyJboFS8pXhDPu79fwTDY2Jx5NBbVwsrGQi1g3cdNZBI6KzOjbC96yh611H1yB5M9s6gQDcvzwAxXMTarRMJx7/2/iNc4PJqU/G2+eFoW3k26AwpfyWmZ51IwfuPLOir9/Y/wta08/UfGQwwF1tXZ/GMsRK/s04kH1mVOGWvO2uYLImZ9sAiTageWw7vIXouwnJ3JjnDk6vh0E9h2KRxsCUbJ5MmzSGs318NdkX/0QbVGZDX+a+T9mYYBewDQjoW0JT/dR1t/x4YZDZZE7aRg3GW3nlLxcg71mWA30jeaXqUrWKMq72Z3lnPaaBC+r8H3JfJ2uxMU1vmPRhAV9B/hH4KCXjs5PNLzLqnTJ0pUz/ItkJttYNY04pUR7f+I6OmojcEyXDyniQTnxr+9B95tdl0NBdYees/sizLW7L1js3KdCZP+h8KavKPY0f1E1J2hFgefnBk+dYKnstVb5WP5J2BB8k7kUgsLYE3sasYmgIMwunaiWT2bXx15143gA4/Zj3sJZD+I+zSp09pDmm2SdGdk6B9w99K6D+ys4zyp/+okAjTj/GneAOOeUe6dh2pcJiwyW20ebtyTfYfTf7AkvvNNhgl5+s/AhTyoNr5itte24GCz/qn/+hgbQf3Mj6flmnVhpdsqNdWDwGi2wmc6h8H9h9F77yh7/enPtl/NNkfjK4jEoacnn/wZv1ZC5I8+tYY1Zy1zOkJnSmJOEvfHRS6nLz3vtEy6XcuY+4Gx/rTf5TZ5GH4y1ncDXaHNAd7TtWe6gms/yii/4jg/Lj2/iMTy+WY0lhbJxJhwP7su2z9R4X9R9bJ81wgLKfgv7C2x38Cblb+xK/kIiYhamNEfD+sUvVcga+V2hy0QijVXf0bG3+il8Y6b2X9dtW5PWPVNvFZOXzuwV0KMGlNS/C27SPUn/vj3xHw0ENhVH1G9epz8RF/7jn9v9sYmkMknd+Rm+HRSmDxKjVHqN8StlMebf/lV//h9xt5vRphqVg4081oEYf8eX+2QUDmYlod+W/W/wEFL1S0###5012:XlxV32DM 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FJ8K3E1NHA/f3sYpDRdy9YfXHjQNy6V1onj8XnJ5hqxcPplBBymxpMVjlJlvS5DCn2ryPm67dW+3hruLJyBxDYzZ0zuSbVdsN/gspOZjkKHnHiwX79KqnmygZfk8wweg7fEmNx5gLPGwAgMVDyvYNnhiga3Ks8b7WyLe3923Uty3UviDLPYjt7RQjzFjcrfy6DUmHxWUfFRQ8olAy0cAI2ewHpf2nDTWM14ZA3GmxptAtCsu8jvUNUWAV4TO9ec5FR8eR3RdxrPVW87EvcUFy9spLl4VM0PK4b5eWWEAW4MBPMIAZl26D3270gC2NIAtDeBE5GAAJyIHAzgRORjAicjBAE5EDgZwInIwgBOBowGciBwM4ETkYAAnIgcDOBE5GMCJyMEATkQOBnAicjCAE5FbpR8NYEsDOBG5Lv1oAFsawInIVelHA9jSAE5EbpF+NIAtDeBE5G7pRwPY0gBORO6UfjSALQ3gROR26UcD2NIATkRuSj8awJYGcCJyQ/rRALY0gBORa9KPBrClAZyIXJF+NIAtDeBE4GgAJyJ3Sz8awJYGcCJyp/SjAWxpACcit0s/GsCWBnAiclP60QC2NIATkRvSjwawpQGciFyXfjSALQ3gROSK9KMBbGkAJwJHAzgRuVv60QC2NIATkTulHw1gSwM4Ebld+tEAtjSAE5Gb0o8GsKUBnIjckH40gC0N4ETkuvSjAWxpACciV6QfDWBLAzgROBrAicjd0o8GsKUBnIjcKf1oAFsawInI7dKPBrClAZyI3JR+NIAtDeBE5Ib0owFsaQAnItelHw1gSwM4Ebkq/WgAWxrAicDRAE5E7pZ+NIAtDeBE5E7pRwPY0gBORG6XfjSALQ3gROSm9KMBbGkAJyI3pB8NYEsDOBG5Lv1oAFsawInIVelHA9jSAE4EjgZwInK39KMBbGkAJyJ3Sj8awJYGcCJyu/SjAWxpACciN6UfDWBLAzgRuSH9aABbGsCJyHXpRwPY0gBORK5KPxrAlgZwInKL9KMBbGkAJyJ3ST8awJYGcCJyh/SjAWxpACcit0k/GsCWBnAicqv0owFsaQAnImfSjwawpQGciFyTfjSALQ3gROSK9KMBbGkAJwJHAzgRuUv60QC2NIATkTukHw1gSwM4EblN+tEAtjSAE5FbpR8NYEsDOBE5k340gC0N4ETkmvSjAWxpACciV6QfDWBLAzgROBrAicjd0o8GsKUBnIjcIf1oAPsJ6vQ3+TSA/f+2+V6qhotCuw5ODRDfE/lZD3bu47sWmiM4oazxDxA87t9bvNfEU3LYyDwyXHzKd+9xjqCnoINJ2Ijtnt9jRpxlWxwz3p9LPFjFs8pP6sg83qHyMSJ/lg9a9J9Vbqm0ix/y0WgeXOMQuBedayreoXo8qz9Rvn4/5LsXvOFriFfnp/fUE5ZLv+qkFsPfe36Qn+peFObRqFs8k3y5cOeIyG1xtjaskYZnS35S5mOeIxyBfsHqwVOfYvru0GvQs8bL3LftL7W9P3WmBev/JIkT4WX/B/04EBE=###7084:XlxV32DM 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awj79/lS9X911aD7j/6o3/u/H/O8ibLvi/D2UfYLEBvhqiNeXKeFtC9Lvfo/FfJhLCZEhFcVmkDbdl+OKCuvZBtRtj3t5YiybbsvR5TtS1qXI8p2rH45omyfAi5HkM2dLLgcUbZvKlyOKFtRu8k2ouyqkm1E2SySbUTZ9uaXI8p2nHA5omzHO5cjypr4A6Ksij8gyrL4A6IsiT8gyqL4A6IsiD8gyg7xBwTZ+Yo/IMoe8QdE2S3+gCi7xB8QZVP8AVF2ij8gyob4A6Ksiz8gypr4A6Ksij8gyor4A6IsiT8gyqL4A6IsiD8gyg7xBwTZPq1SBkTZI/6AKLvFHxBll/gDomyKPyDKTvEHRNkQf0CUdfEHRFkTf0CUVfEHRFkRf0CUZfEHRFkUf0CUBfEHRNkh/oAg66/4A6LsEX9AlN3iD4iyS/wBUTbFHxBlp/gDomyIPyDKuvgDoqyJPyDKqvgDoqyIPyDKsvgDoiyJPyDKgvgDouwQf0CQtVf8AVH2iD8gym7xB0TZJf6AKJviD4iyU/wBUTbEHxBlXfwBUdbEHxBlVfwBUVbEHxBlWfwBUZbEHxBlUfwBUXaIPyDI6iv+gCh7xB8QZbf4A6LsEn9AlE3xB0TZKf6AKBviD4iyLv6AKGviD4iyKv6AKCviD4iyLP6AKEviD4iyKP6AKAviDwiy8oo/IMoe8QdE2S3+gCi7xB8QZVP8AVF2ij8gyob4A6Ksiz8gypr4A6Ksij8gyor4A6Isiz8gypL4A6Isij8gyoL4A6LsEH9AkOVH/AFRdos/IMou8QdE2RR/QJSd4g+IsiH+gCjr4g+Isib+gCir4g+IsiL+gCjL4g+IsiT+gCiL4g+IsiD+gCg7xB8QZMhpXI4ou8UfEGWX+AOibIo/IMpO8QdE2RB/QJR18QdEWRN/QJRV8QdEWRF/QJRl8QdEWRJ/QJRF8QdEWRB/QJQd4g8IsviKPyDKHvEHRNkl/oAom+IPCGeBS6fQgGwn8iG4JYjzzR30W2YXyO3z1IrqHyv3QZmRlXxFO+iER7/mw/NMK5DA4WEdiFB9kbz6QocVq764vFjI28zE6ovDqy9UGbcRh4MmVn1xqFKtVCvdKOlNKuEqVprCa+ss4UqvXa3Agcqq2/AirlZsHbXCLf2WspK3qAIGK146eW2D1/0bq75y/atx98ZBjR+vF7pPrxXorPQpf1X68Gp6MGSVPs0rfaLqe3LxSp/qlT7N63uCakV4MfzWxWtcQ/9VgrH+q+uXDCt9WO90+mXs+1vvhKcNlXVe+WS1Y/bDwap6VPHGpM+uJbDr7/vU7Fe6dwtUfaHeqe+1f3T9nHwE5yN41Ve3ikqrfXutDtFm3FQTw8vze+6sUvSfN5zxfu+4lMzj3LvmTtlbv2uHp/yTPVSNMb26zd7LqvOo9o/X5l597lW1Xs9AbeJ5uuaeTiHv/2zNLcN2ErWrqcqGlS1lflbH7hElXDP6KWS1F6F81iS5Xgc15i2j5XtZ7GgvVld2LwnAwJZm2nUkPh7NCzI7yqEKdty0cijaiqZ/BuHVvygUnjL/xHJGlTlhs6N8yUpju0pekTuxkhfdSMNMUegSgxezncqIYzuyPKjo71/SFQfbokVlSSx4HVYKZOVGXnhE5pQXJmKLpn8a0e96s8w1qrSIxTlN5Ua8knUL/ahmwY7/+EahEO3m/o/KuokiE4nyICtGehxd+kpVkS7LT7OXyLqF5DwCecHCFi1sZ4msLBYUMrdKhbRS4O4MohfMs3gTFBzntRDUKTZpVnDyfREFFvFIprk5qMg1d2Vrj32K2MVbMe5z5Y27hkXjXsLj2xhNdqLQlGs1hptiY6QRjyea81nC+WlsXnG2T8/gE42Z9AtH+/X8fBvz4r3fiNiN4cPwHi7U5x6D3N5eP+2jrm0dhtVMLSvp3I3Hd2GzMiu+GJll3MXH57+2tx4V/9kOwF64peM0kqo/oF7x0/hT7/U9Pz9K/78TgGZkguwS6/aq5wyjN2lu85iERHk0NOeWmUSZKTwqPsNy4DDMiqwOVcXJ7V+9WMpnT/R/Qq7oHg==###7524:XlxV32DM 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43uWPgDOoUvA6x03Ozv+QGMAIcME3BEVID+2sR1h7U0dLzBX2LxR7s+rl3nTSJ4Cw8damgJmTwzwmvkuogvU/Vb8oNcY55aHpq3AemSHPDQG5UbslS2379yc9aHbZDZH61aUZRSZxzbV+2fmDBfaKIava8T9a2ZZwCELmF9ZwPyGBRRQuyzg+WUBnaUPV8s1Tf1amI+9q7vPFub9U/UIO3uExMb2JTEvmVRFvLBYH7zbtaOoWlHKphzouAPlliDOYwr/K8ep7KQIxQcL9elQwYHMQ8yMSsrzfjN/zTL9Q7VITfmtHsxVrsdnzsG8O4U1kNmLMdOrNhD3x2/RA4NiyQfuSLGx64vX+XEsx5eeO7NRZIZ+Xk6ReWyXUNkWZQijeMtR36cFKRcwvBNRuxp3QT2iGEOAwi05r6zvjHpE+XdG+Xc9vuvxXY/v1Cc5o9ZEbGMPHMMwt/sQQtWywE9Q0MSrNQFP6Hfo3qNBLAKdGTD6rUvqz8xu6q3jgno4dvUmGuX9ZLuySKCNSLJAIYh+HpXfQZ0jujWmujXoRIwi9vLKd7eoXRlFVwSKlrW7J85pKDwyCrxLGq8aqTf30/W5H0YPoHy8pq4sUOx0rR5R1Jk35wDFOZqcJigE/qYxDPebomrqTmiRP+tqZ0v9Vm233GitvkyzrlOoVPNqKjtfgK3wbDZRmA9nA+04lJZB0pDMTALcKMAcAsRSuzcwkkIoY5Rn9clb09aW2pd4MR7Fy0PfvNhJyArlf+s48YOL5l1QWN6y3lpBFZDRakQOteoYOt2ziehA16UllZfVejHiuBRcG9ROIVD171D9IdWvcQmeFpdgeCsSbEFr4/kSL+0WKJb8XzUVH+lSO7Wp/n1J4bF3qDlgfSp8DzVPoeY1mpKG1JxRWJ8aL+e4InHotemCV+9/p8JTbkahDEw1z6IY6fmfKaTcPVQaK2gC33MUP6HcPRSeK61V51qr3kb5HCrNlqPyoCp5Q6Vfb2F/hhsZtHXB8FCRYZNpbvZQ6SKVfmQ8cJ2h0k3WgaraonzXok+yKSOkSvvBiaJKd6l0C4vxoSA2U27vl9c/XVy5h1SaB9Lcvrty11BuWQc//lrVDzC4ISi3RWel/Mquz1DuHModdp07FhLqdj2rpy7shFtQqG/YcFxnWG7ICBRGhkqDg8otG04ZUblz2PUWNmaTmjNje4Zi3X6Gepx69sq2UeFLnJcozoFLQOkDMov/szwfq190htSE2nSpRijtUM8LDVQS9XyuSJInYJH7Cc1qWb6t9jBam2MNLWqxvDY1rk34BNexKj2pVV6u3CpB9i284S2Qtu/v99+JCNLK9Xn3XlH3HoPJukXyaOAyG1m3EVXg4uE32068pJuUSb2ypTUscTkfJaa5OACR3j36Zo6k/HekLyjfcZFTDRWLWV39ltJ7fbYIomfQkII5xxqcWV39nK9o5mD+dGYTVGojqW8SsBCslD0jmJJ3ZU1tP4sbGr5GzSt7K1E7xqGe+P1uf1jwN7fm5SBn7ujvmOrtnGoJ4SIwIj8c+pB9k/PRLKM9X7NQTYY1C30xY+ZZ3bquSx2lGgP406fG1fi6q9MleeXfKwH8Z1yNRs3kzQl45sh8jepAVW8QPvx0kFJk9uybZQRLx7am/n+HKkNt/he6b5YZLOjhu97Ceqm3G/M6edZf+/lGIavoEg03tryeKEfTqzVdxfEJ1FC9f17XLA5dDu8A/ur2xRVLXsUzlsdO6JJ5hilB6Ax/imEY5jUvTHKtiDMwYBXFzgUOTfxFjWIGhXnDlmoHTO/HxVX371WzEn5f4dJP5Sv30N9BEtJIcypodd6HVkh4875011r2Hkt/HWJHhocPGae2Xr3QSDnE7vkHtVtRDBfRtT9YGuyP6GHLT/zXMxFZ9vl8q8m14HyeP5JtOio6B4vgPKqbcq9qNkhtvyNF05+U8Ncz9MAum3twK1wDt2KgFP+dgulG9IYPeSVvQYk/maam8iGHCdF9Vsj4z0orbzg3bwp5prf43oIKfZiQCGq0OTx81t8efZgQO1XtkRmqx+H/u2CLCl1j/BXq7reAIcO7odroS+F/SGry8Ctdt+dk7fbmJR+GYk+veukfh5Ia/CWbbdJQpHCqj8RmY9qNf8Wgut03tNwev5oYpid7tOpLiPVjaGsp4SUFBQVqJf4MU90Z9U3/nPLFoExqQf7SPoMM26tgcXc34o0JoNiOMNVSwL9ktD9NAzzvoZZuColtAeqcs0L8p3WGLnR8dGUf+m6P5HicMkEj0uSp1k2jNHIEEFN/ZjZKbyOxnmd8d0UrwxVvFSCiWYF/Gkvjqz3AeffIAYa6J9O+xT42jbyrhb2ZEWcO4JL+SHBIbl9tFyFBb1EI2w2wNEuCH6ky59iHvttH5ETnl7Q+EtR4W6TYnzYOOWY2eewhSz3zkecZ1BUjK0OkBJNLS5IpsdJN57p/Go6HSi5jCys8pz6cah6nyic2/Aw1/KT0fSkRL0D7+UeSsdHO/j+nztLy###7324:XlxV32DM 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4mn07LKIQkQC8lTcjJlfRgFF0IiTjRkHWHo5lq7E0qDTBuOG4mbcDYffxt2bFEHjXE6v8tfOuFu71xL9BsIXIcDSxVE1Iuv2O190f+bd5mQ6R/gPHwQp5kY0y+srwZZhfzG3WZqzzF8moZec0+P49UdQk15KYzJriGRxaOevhBGRdSSgeSf5iiN3rLQzeityR7Ro60vtATM+RGxA7oV4XUEKkHt15J4cuVdH7sWReyZyL47cEQ8Wq2CK4eFhvNMDwyOeBsZdxfCI3jcjgyJ3jN2NcXeTEAVyr47Xm+P1QpReHLkju3AEUDpitkjGKpCSHeStDK83x+uVeN1QC7O44nXoYAbqYNJaiuFN43xxpMgd69v0EsXwsMJlL+YUuRsOv4ivgdw1Csh8enNUDI8Y8TCvKnJ3DE860iP6cEzT+ZZb0TwoVOdsruARODkyevsXuSPmuEd0+hqQe3E077iemZN+1Wf7oHmyI/Rs4HotoDfefOrD+RTrA28MktGK9VVDWVCa3ECAzZO/9qyO9btj/WV4faZF1I9XfHz5AfyvZU0dQvy/v/g/O/4fNjNeNIRiT/RB0/bk+H+QnD3mkKLcZFHOXvxrUW5r8XCxeLjWr5NX7tQS0oTK3cHp9qLdbgCL2F3pakXsiNuGfuUhx4rfIU4Hf4bA4ez19Bkyev8O6c4W/4boNx2CLW6rT0px07eoa5EaKLZ4cHqx1y6KR9dluBB15dT8lYo2qxYVmuLRWLc3OqlXvrKtJUxWVSvLkvruDc1n/XjMUJP/A0YWmKUF1Nwa/8VCqzwqyVsve4b22mpRnxdLlHcPFnRTyjZ3nva+BM16+5NQYm+3IqryZ+6cbe6za7fjZS8a7fmcxrXav5wmngrVVPiGjTpB7SB2k+yfIqouzKu7epKyPc07zXIvxbq1GeksMLUmLw+opCYST7aHRGGGzx0ZxwoFDC9l6ENIOSSoUeCQVF6c8bC2XHyoXW57CF9rsIeCVpS+uCtVRAn7K2E1ualr3/+ygDBYgb5+defBajO+ZT4U1BqzfkPZYLCyfP1qwoOVYHxrjd/Ec/Bt+u9O/93BF91a4cVvNL4+0Lou+t38lxat5uLb5fNdnA+k7mDl9vqRuoP1WvTrkf2kSot+9hLTarPoxzcMqMii3+L6tB6q3wC9Bqug6LddL9v18rpeXuoFlOVgJRPf3B7D7QHKcrBqiW9KGQ3WKvEt+7fs35bvd3G/IAcHq5H4dlOnWnnUb93t1t1umqRBfblHdPcIEGiDFUX9JsQYHyabwxvhNVgptJ1n/rfKDJ6Xqj2YrCx0IWvhBXtNfICfgj+75796pTDW5xxiGvyIP0EDMVXtdaSRVcPJKj/su7KmuAaeput/kaWbZBUuB3clBC1ewCkEcUpWAXpsPulHybEx2wDqr8zWwguIklW4znaSCsNfDg3+/4ORVZEJDxR59stB5pu35sAOBcnmZFV2smqRrDKaljRY41N4I6sqKSoAokHAptEGRFJ1KrN45fz1ckLhRQpkVSZZVbw0iWubJFKQN74+pahwrZxO2E1/MTJIAihZhRVE0jhKVnnh0goaF8t8SlahAHvnzzfTvZccQVYVJ6uKk1XZyarsxczmZFUnWQWipprWQFY5RfUra5p2Cy/omv1xidjXp6xpJErn5QpkVSJZpTtSsqpUL3U2J6sqySo9X0pRgRBLfHOpFFVxCReLxfeaF+lmI6uSk1XFyapOigqWSY0rmCxYgaxqTlYtUlS4Jth/txpZhVJxDCy88XUIyCqVABAiyarCoqd5tmdNJauw+kb/A1mVSVEZpWn/6WBkVSZFBaI68p9GNBc6RWWXv+FXpcEylZJVaPV/zph8NwGKClA/8doGsio7WVVJVmFvPyuU188WL6eXF/wuL9ZcLCqCrMK35/q+rUKZ9Ekf2urztgq2lHOEK98k5apkFUZ4DANZVZysyiSrsMt8fd9HFS+7Ym8eO7UAu1mKNTr5YiFPCSzowK+QILCKl2ILqSyQPNMLydsJypuXYlBZJLBMf+/8Elg/UkvfGiuVVSqpLFxOFWl0p7IqqSx4Ip+3g8oyGmf4hXV9JD5L8NyzeEFXKku1oVQWZn6vD21l8aXND73FCzVP8nBKE2Xh4mXh5qRWclKrktQy4pulcSW1nMr60Vs2trC1Fb/mB49/0X28D8+DvpaH/7g1vcwDAssl0ELBr/7dC+eb2W/+sgu9BAQWSKPM/1QDgZVJYGEt0x/I+Fs3EFiZtBW+RZLSiu3sCZFTCZ0RXWkrRJC2OGJXRr2HJAUIrOwElt5x/h/ntNtu###7008:XlxV32DM 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M+E8IJklWp1ZmZh2GZ/cgJANMm0VwvdbQ3xh7vepJmTluFpWNAsf1T9dEyF9bBXxDLB6HlVp27d/s/TE7KbHvIhgfxQOZFwjdWtkffhmnnX3tzBvAzf+FqGilnLNTJSlq3+/ZCo12nI8dySiNn82MsHZlnz5vwfM3GbQt11tuT1hm4cI0GgeJ2g6CID80lpmUTbf1T65VozBuhyJi0biI+a79jYeouPxLLVaL+U1nlfymqG2r/LHrYGoY41meVIG64Mbm/5q4PGBzhHzRvqcPRFCGaLyQJfiaw/EW7qKjCNS0s/PQQgU5kEIVsye44NsejYOOI4T5L2jfYZC7yG9a1GqvJLEgXyQbYeKnCN5kX7cnopgJwwYovNMjC8z+L1iSePgsFWYnax1b/SZmhcZNiLU/BgHUxXrt8bBdTT10O39rViOceCJQKzOGwcZOHQw67JIUqo0T0tEdZhn/Spx4rpujYOxXZ+KeQe+X39Ly6/nGYwxPHc2n8emUFrGHsJWr/OvExZD/YAd5kxVbbE/2RD9+h6fKvIxw7I30JayZ+swx3//AHHyN8QuD2RFFro8VcwQ09H2XQsHEK8+flKDCEO65MNGU18vyWP/me/zR6+regn+NONLul5CDi/Z4yUHa53/qnXXA9+sB5YeD6zxwDsemOKBXXVli1HrzpdYzEa8pOnRSFrgo4ce3QJRrt1z8fjAEi/B5Ft2rIWnHs3aZJ/sHc2Q5tbrnLtUhV3/NrIlUX9exesQ5CedTBX2lhzRkhwPDHTFA9F1AbH+e5HfOsxoKPXaN2ZrsrJFsisol+83WNkanSVHZf195fuYGmLfIfE14s0z2vz7GM4eZ/qMaz+CtDiuQTyWdGhca/hoI4DRzPk2aSPQ9liNbiVh5/PKn/XNV7VXeVq2vnHjcc5XJxvOM6borvSitnlyJpDmxDuKJM23V750QKydmv5fTZ6jp5g8L81RPLMVJ5woxNTUU6/mxxPWCw+15a5exHz1pzqvELO1V8WO77TGk1evJs9xKNVsHK8P3fXqpOZPbSKAkKtn1WH7eMzKQ3l9K8YYnLEinloRrz1HXLRzxO6GGXc8Jjb8fVrePm+5P2/5bbSfRUsR/dS8q9Zy3Nol2H/fTJZuIzYRh9e7lrcpmRL5mlXZ0tg5okjngYk2OFJxTIIJ0SzconCLIkok932lnb/iTt0ycb2wpeLRctTTY1Bz886xHEn2FNVlnZXGvZ1KV7d1iWeUdiTZ22mDK/LHUQSJcqUoIRqFW+SFs2J246cwT6eU84t4nKKUb7Vdku2vwtSu6NxgjjOMLBLoYge945zDq700Nqo1tsMttsh+NOKWOLZM+nj57Tq3P4abG584Tu1ymw65rc6oTTcQC9s/yr7/TEmBPpV4mLsnX6ZWvMhq8/STVYbcfpS6fwt7Cr+yG1lYRZg5h8JYDKqdr/QTFqPr2cPXfhZGDiCKwIfVjFnOQvC8OuxXsUj9FkZY6vhUm/FLFzL1uJVWqi0uo2Oty0mXMVKjqT7EunbaOE+B8ULFuhr9xAvpvsrpw8Avdx0++CjBCe/Ws3GaFTLCDF1xNhWdA13n9f5UY1N2a7d4+8ZjzVnTI83DvZzwLi1E16759wrjgy7BBfKRV6j2T9TvsSkfEffpx6balm3aSReOf3iKZTqepAMvScc60qVDq/hwevB4RRz/2Isy/eeubOMn6TgMDuky0nHgxWYLHuKyQ6ucBKpOBlpWsl9V911XLw3KXvQvyKF/N7qOwxCxxOnZt+xXaNGr46l+4Aq9/IlDQWPoROJevrOUj6o0dAIF+8KqMze/svoC8JxaMy5lFOO48cfoav7wvw7O23cM5Xp0OAS7AxThqe/Du4NWprd/ZqTfDvbxxjyMvp/hBO6uHpTOz1tksnxLB+Qm+pIjXkN36D+ER5saGmvYreN27VYl5l/zXnNr9TmT75X93crcWv6vNrSf2sN32vdW2smrqcgFG/x/Kg6G0w==###4728:XlxV32DM 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iM7JRCzRC5FOK1xaP8pXRH2piSgFPEKER4p4zan4qZi1+e5q9YwKTg+9N6LgPdW9Zebu+QHN9YTe3IPEWsOEhhB5QsRLS632XyIZIinU0ZH7fXkCtzdLsFQlyMrXjElrbbiFEvZZnRl7Id74s7EGaedMmuOO0UXUkShJkVWVr7ZjxQH4RfVIwTOvwzNZ/c0aWjcFI7PxzPvDM72UJzzT7D1gCZmraasN7XK3khdeR2V4Ib5x63wE27/jBLXT/ah3o8bjkkKJVZzDy1St5rlhhm1LXEpX9pKTzuY1/SvtK8Ml6hcspRib4RspuMAN9/GVtvyBywrWfIOHl+L13yxR9FVNE7HNFVPkLp11bF3EFMVAo/FQQ9F4gkHps01DrQViyI4rJOIij3g+gc5otzWJ33r0vFWO34Kk0xiBOK4eySIBeahz9IQulhORl50d1SiSjpsCFaAV445zxl2WXh7lQGr1MRe+AsEu/YrSqNjAHN/ZKXrxcXXF/NLZUqN1wtC+mdr3oH4+G6kdsZmqPnvQ1BlReXvuHKSWhpeSFCmr78LwtLRT1+n5cvVILaw1K2vtzlr9tkBYqz9zd0Rp+u12PrJXfjZDdfZIJaXgaw9FbXR5/WWjuFWm7Df7m0rl+JpG9EJer9qUHj1z+tQIHC2/sKyP0DW961ZkX72Eb9cjH3PZwe5thLH3NL8XBXp6+PPa5MItkxM7E9EwyR/CQgOvTS7QK69258ElqoiN44xyRpqqfY8QMR+W15fYGXXpuBi1hvrsCLda0rdtQEVGi3qCI418wNiexbWewo90Jc/v6x7L53FFp6m0GSrIkL3zsXicO+IaHZ/Cqy2liRzRUG0ihz1KFzlC+BlXti6SQp13FDVevU+/U9iMJzi68iHt28j1cO7jj0duLxBtBhUXWEQRWxTNEazFjixF3LIOVRslWBjEdoRSKOXotbCX32uZw+9lFOkrhwK9SnRjSPLMWs4a7U6vRtby5Ojlyc5f6o4Ye5B9Xmse7ed67hhEn93YcIzhKAaxh0inn0MbxMq8hfmX1gnddHQD9OTosHZ0SOhwQesErfUaSD5/BlmvhmEa3fnWoU35rGGus4a5zhrmevzxgg9CNpNi+ZzPJGMmYWvXi+PW1NAFI60Y2H47a6j1ZLzlyvGWaz3V/K4NUglzYswpoxugaVaffqfjBukQeUe+zHKnvTHwqYSxffZnjUU5vUJmKpo2T/bDvD/f324wP7fIWcMi/qwi5lwCaZFn73anPfY0QnlWPe4wyVyRuiV2ImkN1WUeeGr9rBmHZq5gc3Jb4W8o2Jm5i5RAVl6llL5KqMs8OOIh0XF9X2Wob+3XiBsoinsLE84+AxtPkUXdnqPcI8muinhWrBfKPPCQsQWX0IbqjhTZ04nRwEKpfh2qMc4RJQ8TzhC2bGU+32upB581wlrD4chfWHIUdi2FQTJjOREvP7FWrzZP3+pXxDIhybKMN1hD1IdtlB6PMVxEiwtzQiTIkgnbyzuOJH3tmK601ZC+tb694CDv+4pf+pSne+abqfhLv3ykIBjHQ7aoT1ysp1ziQlx71jOyOPmabhWq1xGT3PjrWdOG9oZQSKadupvHV1ct0R4zHhIdVxzPLO+a3vBlm+iMukw+33cFY4bpGna8fn4L85a/jbiEka6jEN7j5bKW49++7emLCOtmM+FuSVSkGOO8g1MeZ/TINZJW/Wyvb8/bV20uiv1S8ZirJfol0iHSoqpvSeud48lY788vkQGRHpcDrneNK9IzdnxSto5/Kiv3U7VmHOVR5cKaY+4f8VxGZIwBC1IGbCIjkG5+FbZy+2ye3ddH3n2vHp+NqR337Y8Y7fGAPo2RJwNGMRXpMPZ4YODxAP6L9ca/xhjd1ccDJYqcMsF2xC22oTsKmlY6frLvc30o4HXFdUb5199MK7Xlbw1RS0Za57PyHc+El+l4+VKOIF235/EmYrMfT/1VdkwuYiVSxnOn8SDX7vF2J58c1672rKHGBbnVZLxgq740/xLp+AwPaiKHPQ/9938wVOXg###7576:XlxV32DM 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3Oa4zcbA1WBcrd25Goyr3MNxp+MuH1ufMcddjtuYoFBIhfUevsdw+pzmx2mej+/7+B4+tnxsOu5M9Ib5RHpJugfWWTw5Xli1weGaHxMiP28WDMpcVkxGjAI1CKtGugHUAR5HhvpWLSLtt5rafvgdpAqdrRrrqJWVOOnZjENtAA9ptY+IDzQOD8GcNKyd5rpUU10VWYLgq0iFRk86fezxUsVz+TxP4E8fW15CEKEhrjUOQmh0zJoGVGguFxqdd0/fo9k8e4Kp0CyDbN/pY9PXG77HcFqcvsfpm4/v8fh6PrZ8DL4+mqgsExrL0979m6vDueqquLpz1VWR1HgJZDqnp48t328lx3UuPM6Z22XUKhLk6kd6XBV5cx8O+tj6cNpvZPmN3MP3GE6L0/c4fdP9y3x8PR9b1kUjbHtzdThXVQFPqxggc1Os+qOqMROrRNrMF7QftEdtoUIkpVTnYEUkpcZRUHO9gzWB5sWK7I7eratPen/UmyOKuLRy2/nueXpiYnIrb1LnqtuBQjTUfawPlfdid7L0eEF56yHPTWQ/dePqGyOzGvqg/9elqy2DipaiaJ9WbJbUvS0W10ZHra6iTytaQRaftZCsCdweXo2AGnZJqxUrPghmvC2+aRb5DO9+BFidwdSIFA6SdfC0zTJ2ZqDzFPUQbw8ZzHgIEcOaAurl7fXPY21LltOIo1hJJ69WyB558uOhphAK6aHZ42dPzHz6Id2J6k3cManeJVBgiPdEvhFDPIqmb7iiSGBEPQiJ4tWrbZ3O10Rtgd9mnBOfIgvOzYhjMeKeR0TwBABvwXlUA5p9asyNiQPCweeRdEiaNHCF6NbQT8XwswJPsFx0eU7K0DrZzAZA8HQlIXPebFOYk24dgFyCAsPQGtFQXpQyLEQfk0Q8BYDXAiCBOQAQJwDCzGWNboAgb7pmxZrne81GCkQUsYKo6WSLENcsvmayNeXjeqxfZc7rtaaoPBBzsxWSr3DYCnqIy7hBpdM1O9YsbzqLUWV0XuQGUrkKTN8l+NmjrSnR9Hr4EvWWHADCRr3spJeNBXDHyDmkdQeVsv2Gi5qhXhelbMkLTpi25KGHEevyWfIY00+nAk9gdWFdxaSNEfATqFjrarZyZYpcJn3olpM/B3uhlsWOAISFKptC9xNYK4RoiQ4JPvgkn3BuAHS1ab2bUbXAixKcmqQ0vnpVtf3MWqT24PX6rFlKdAM+xI5Wb5UUm9Z/Ty9Yncn/wLGmSp0I66TNqvgDJ/kfOHWur+ZYQVHk6siwtKy8itns37s0nxgJaSIPna7o+y71OZ1u2oU9Nr2C27zom83bYaI2iPbDSnxHNEN8WrWeExuO9T2xsJOULQN1eg9GYM6LyN1RvItRG2daN7pR1dbGBPfmsT/ehFCsZQKftQzZL++FH+yWisP7IsfFxCkgKCCRJSRG/xHcJpoF2QiSrTdVxt4o1krIPtuW5qu+rQzVickg/uY1rY1LBUFKx1ocjlZkxllQmoXl23HBsGeABfBoKGE/AZCzB3IFocl4PwOQqkSCCMzROpkmSYs9A+qyPzy0swStPSUb40c+rZOh1lenh649/E879BHznwjrvSWK9wxr+IDO1ejIQfuIKTDsisVnr+W1T+cm/7kD3cl7TIrVrXlDaEX3htS2rO/AHgXaoIMVgczfP85Pj0l5ySpF53wTQYGp7Xzt8mqdAZe7hctcEAmSkZzfl/3ad7LkicZOqz1WSbTD7khIZa25wTY807K/IVc1PVgMGjXMStCDejsnll/Hqm9kxKhnjta+0mvxttfja5fou4CwM3OXkke3LPgoliRf3TIUebT3Z/2DR9LJmpC6KgNS/SlE/9sZ1ve7I1vxZ+HwH0A0id68/NC+yg/Dk+jDk+jDk+jDig6a2JVSAyHjtz6cJdV3VK9tR/rwUNBPUfxnD/najuy5govlreJF5lhG90aOm2fesf7SgmYolmHXbuXXozYbiv730diolEumF40l0XhrfZ3FLRaeQwvJEtMNLZNSdgv2a562i2hdjckuPDI4kXRVo+GJvqI+MmqxHqh1vLuxK1urTZKlWfn9Dyvaj9qwxiB8ZmPyab0h43x1FdGtjHK9nQAm4qdZvJiaFTyIrP1u3nRX3WXhs7axDasVYRc9VsnsJdpQtrdTmt75k7oa5a2WxW61XvbTpjdhlmotC/hfTo6f5vlYUDqtWiqNCqpN2M7a0pfxLkRjLXp2Dv2c3s5yeM+OtfS0Nzb/yrImp1jNzm2I16rvQP5O8bjzytacpr8wY0VJYqntP29vROzl9bc2u9Fva3JCyyyuf/Tq0VCpXyjN/tZma5CVAtHVq72L7Y5fKMUmquzc2ZAP+y0BaX5VRv3lKzJhzh9xmmlt0eJp5E8UagY0bOIBj3cPJLbBRPjDypZhBlVa96vleP2WYb1PRCZKp2ugmWvX+YUS2Wn5RkGTY+p8p20arU8asesnOMvs706vX3oYsd0s5iA4U0UACn+iOOv7zxlsjWOpdAS+FRWl8mcby85I4KeuSNe2oJo7p8PzBdno1p/nT/txUOTt/22tZ+E=###6772:XlxV32DM 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w0pEZRKwFGzECuTh/U8nAW0pk+WAv3IVijyT5e93ZBJImARsXWSriChrz/qZPtFthe79GQMOFKyfgPWBavZnJkCzetmsXjYrNrXCphZYpAKLVGCRCiysm0mxmRTE8Is/GFbUX4j1CxF+Ia4vRPMFyN3KKXb2LBuerxmC3BOQO9oWNX2gqSB3lS1mDUXuUuoUw1/eTowIR1Dg2KwcQYEjKIhsBrHDLpzlFM1HYHiNnG3FWzG8aKBoPgLDJ2B4symb6ZosUovNYLEZ8KVB0bzcKNiv2RTNqwaJrzwsnYulc7F0LpRORfMqS/giaD4R4ZMHDWgNTqyK6yPQvO4H2JR364j21u1vtUI9RP2JlKLHl6DlnR+e+eOdnO4JoCrfdSsBVA18f1tsdOuD8E3Wt88kYLKe1YKNaTvesrJaVLOQYv1E/G9VgPeI88NDXMELITMr8BaoWD8R/ytK7xPn9vlB+Ijn+pkEoHOlZxo90zBFoL4oZfVl0abrw4NNF0F4IghnhibWpqTxfFB/jE3/VnGo+1vvl52pyuc88Pnc/fu5yec28bmN/3zuOlLcPx4OThSzY3oYDjPDcJwUOuYD+0qJ9JN4QRVKXLSvPEmSDmSvPMHznSgelH0VxN6B04Un6Fy/CibvQOKXp/hbv05Hats9wk/ni6t1PwdNBUMrT5BzB15WnoesYGPZTxFxJw4GZac57nKRrtkg0QbYWbCs3S1QIpD34LRqmhoy7cCjepqg0M4ncVC4JXnux5ukBr8O4ylq7MCKZpdNu2zw0uJXnhF5Bm5pKK8D25ksvCrPyzLyyqOyUQ+pRIrrdiEV+fUlz/4opFhMf7S/KtdNUp0SnlTjV/LW74xMapDCwC4PtLYLd548ba7vw+sgyFKqNuTbZDSF50PZusjciojYZ/2sQVvtn37u89hpsnUzV1/mKvM3ME4DM2DTv7vSb7QGHzblcdIo2mWZTQ26dAAWy2Se9uA0gSSS0wJEBuGHrnOsOfg5qcIKtd+2PFIIoV8nY3cydhfzbQXIJuYCM2AhA6zRd7Z3ULDQwDrUP3uO63yEAwWfs+rVwExe4Pn2oWADnlFNA2uana0SlO2HemBPYJ0PX52NDxS0b1j3iZf1odAX6LekNv33n7wLfpIiI5lnAsuvek8+yg9IbtORpNcfj+9AnL/AW4u8h7yHPP7wfCXyuN/ifrvwjEJeJC9S9qXsy3WO69znV6+fcmISxPRrkjfJ6+R17uy5Myec3chrlOW69ZuEqP36aZ/Jy+QN8gZ5mzxgZilZypu07qbOmzpP3m3ybpPemuszqeGMn8XprU1vbeq3f/rR4st95iSs4902bf+bpyY9OOlB/kfWwxlBSpGd0YCznP5M8heVgVGZGJWBUZkYlYFRmRiVgVGZGJWBUZkYlYFRmRiVgVGZGJWBUZkYlYFRmazJ6a+kNCoDozIxKgOjMjEqA6MyMSoDozIxKgOjMjEqA6MyMSoDozIxKgOjMjEqA6MyMSoDozIxKgOjMjEqA6MyMSoDozIxKgOjMjEqA6MyMSoDozIxKgOjMjEqA6MyMSoDozIxKgOjMjEqA6MyMSoDozIxKgOj8r75SxDpz7fkncvekZL9IPR4XX4bxqA1JLBIPaQSKa7bhVTk15c8YH8peJsBZesmqU4JYpFNVLd++OR3RiY1SKEji7MH3q3A42lzffGOrePd9m8/98UnRlH7yVsSCYjRpX8dEGS/R7ORhP1Lf7h7MbV+Xvn/YBxknQ==###7512:XlxV32DM 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f0RZYOg+QKk9uDftlYzsql6ZK2lGemEI0ZN7hQplj3oC4ZKbQxyyXWCoY9zwaS90x/PcvNPXu2hG3TWFEoCCKKYuKKhuoI67wqAPWwYKqsFoOHp2xX/gMExCRbLHnJ+sbFdOY8OOpiJyTjXSNAM64NjWbtvasa10/KkXvQgSlJnY5fgFjPAxI3w0mcFZVIDjHJznKMrKN4Epm2GC/nnSF0HpbkkxmwwlyCoBugDnyUlTt69FMKW83hIrDxO4CaEkJavY9R/iKXL6ByN/3pnacPV4jXyGDno/z5W1Hj8GkhTsNeKq/bGnVPWyFVpKUgrifl8y2ZuhV1w33Bu7kaIRNLoaqpsAksfr5GesgKYJoxce1P8BwmdqKWjwjCXxjZgl5TH3rSE4pqqkXyaoGK3PL8BH9JdpKZl5RzJJGPPB+k4w3y1Cow9kso2p/ABTVbLOw+Ako0QePQNZjvnerfuxBfZimRySYQ1Q7iTh7YEtiAqPkOgmsYq7Arr6rR8Y5KhbbSGMAA6qBsy+IA7PABUronBAe6m8nxsrx6GjjKgAr+tAEE5IA/VjCvauT/jZTqP0SpIVThCBX0CvmpauDuca2XQS1RA7yo/tp+62svH8ArsgK3OtYsPiqwalhLbUxBRYLUscTmD7EIv3CqLyyypOgTvqM25i5GneldTcgWsACVkiAMfq3zlzZYq6MprYNRqgn6S3yKiR03BXNYBYXVm5/7aNKvYOpbxfXDorztrEupWsQXg5xbz6cooLTjGPuiz8hyAsjjhEBdY/7fYYeMzYbKW3kdBbdPD3lj16C0zYrAWzRK7H1YUtjtpgHUjLZkmCZ+PY3fJoLkUuyGW8J1ux0V38gJXmgGHHzomdPMBQnN8jZ8AjxazaGWDqWVPHOKtOfvPQTC7/ECLV3zyi/eYRNQNiLTiFqSHYuJumSQY/G+fH828eGb95EDd5rBn85gG2losZnW6nznOuD9IyWYWBmj+VPG9PuXbJq7funwC/SMbI6XlNM/HkPw+OqxrVk3I8mrFOkgY3CV/wa0hEqmwjEamS0uS74meWZLGdV28oraLtXY2EjL2j8QVmNvXbVoJUJGkFV48SqdnoU8n7U/Ix7anp8UKfJhCpsqGUgi1ucz58BdOGxqFuouz3a4kSlkjyQLeGH1iSpDGHPGQZoET9wmOB2UeJO21QsONGGk8g++d4tBQzBgmnoPggXYvT8eWBTyu/c/QlMlAT+NEC54FdFAFUwuZ2ldTf6AOgZzYPQFVxQzIvKGG0xHEyThVEkjR/E/BIkuYzjADasCYbbVUgrMpWkU+pVAyQBGSWak5WVT9PLi2hsPcCvh3zyxkjmMKk8CsLU3CyxXolF7JpxqVSZHnpldc1EsyvrXunVFqxIqEIaC1ZmAJl+/jppRuIyabMSO/Wk1784v8WiDPuTn8O4X/C5PHPtegE/UoLjKVLiJpxMYW2Fv4QEkmctcah1fmP/jdDasquSgBoM0El+cbeFu9GfyZKH3XiWZJ6Kx81y/XAwV6l209fOcL6c4QbyBRvlCg6fvpigsCIXbnOOi5SUd7KpI4fJpV9CIpzCnPZu3ulSQgtyrynHPTeYd4ctpBcjoboQKafOr7F6hE1RAJucYHDlNNbW4+6uTf8UY/6N4+kWcCYyPdv41OLz1tbshWeAca2OjjUZPXqUIypDsUtVgZRiiVngqQ1UJFD+AzDv+wAQN0xGjPAmDWZnjmI+aPS1LWUeFmvcP+pHo5MVR9cAWPWc6ttbyQuNP0JhTym9PWi3U+EXm4CePVSzGtfgt5lLGkvvVkGi4N1iXfk4SfxieJmJD16gyC94MJQcvGGkhkRR00v1naQ+cktKmoouFBKwQ+V0ot4TIac9gJyauXtHc1q5E9Rn0iQM6+24KpjGAVB9hRPAJ5DKiWH7xUvhaHvEyeWC57/jiUCM8q5C4a6pB5iGRT+0H4HLh3KqVBUmxxwVdJ/NXJLHe0tw6DrYOYO3mCnqCiPlD0m5p7GAdZmlFyMTVeULLlQ5NfODR9AvBpLDBe8N+AX8APICJE5OmErQDbrLgXskuD4hmAfcTDaSm9oBfFI8XW/x0jCRt1iHB2xG/F0bJdkvzRvX14otZOZXr7MFznLK0m+DHzd/cbBPNLpgN05GUO8mmOI2IPGaf4nGUP8R8Pz4uHymJGxfUvNtqd/7ZzmH53z8mv1xI7m3if25dc682Z56vT3oZzY8v15YeEHYzpLrxO7M06sXLrl/PQiLkxBTIuk79GQXq6TleyQm+NOuTdfd0tph4yDOsrXeTJSYquTIAly0kuzRDPkN7MkZs3H/WUgjAqKHYmO486pcHLNzmIwA3ed/Enh9R8ONf6M4zROB77LGJW4W3wdVcxo4qBe3fp2t8R1tQ0dIRkJAxKgxahjIUkyTqa5kg2/8IkrzDidHWCJ+HuYvEQMC4zLYpB6yHvAe8CbZCEzPNWh2XPRX1mZBrvtoaeP+hZ7e4uJLf0/FTQ58g==###7228:XlxV32DM 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JThHl2yxEpyjU7ZYCc5Rl1VWgnNUZZWV4BxlWWUlOEdBtlgJjshKcI5uMWQlOEdTVlkJztFwq/JRvTDLMgmSxHDEXWRru8imEly4popx6VLR7tDlUCtMOZrvpxjXPRNlzUa1GBXjFKXUo2cvxuXgVzQ413w3eJU2484OU4Tu5SXrGTcyvZOgTphKzHcX44ZHOPl9Hl+lcUGHN/xexf1hhuEH6RZXslJgZfz03PtNrMjhvH/exH5mxf3vNzF90JEXx/GmfRcQzhXn+ei64vOoGu/7nW067dB2b9krj2/MiZnljHp/P8bKh8t6zLAYAkYsr8ODBWh7NaG07wyLpzvvjt3OpjtuJkTxxR/jMCZERRV21YVbaNvhHm55falUV9HxXfST2mX489WLL8C3nxPEfpUflYZBLNpqkXXw2qeV/zmIJnTCoy6l4B4ezmegwtOIS6cI7501WjMdGteoGzz2Lel5u3TcA95DByWx73t4v2/y1vGdXWeFoudPtGwDUmbVFlo/IbsutTHMRZSPF72y0D9xrDLVejYNcU4eqS04vh/v4z+eky34yZLPryhY7pWr/McqJh9tpsFn/QlfmVfc/RvRQarCV9y/5Bdep1/wgcyvWt66p0lld5BLvdz96/ImXcWeuvL5erC5AmLRzFtqNOfWtGjP/H7sHd66HNDeYz9+vm+78epnfLtqcM93AsaS2IL9u3FssMVTDCtbHMkXRkNs/I5KLFASTCcqrYgnQzIHe6OuXmYlvunqy4GuR2i+huzeP2WGKLNbMZQZoiw/khmiLN2SGaLMrjpQZoiylfK7zBBlxymZIcimrRmQAVFm9W/KDFFmITRlhii7qmSGKJtFMkOUWbhCmSHKjELKDFFmpyiUGaKsiT8gyqr4A6Isiz8gypL4A6Isij8gyoL4A6LsEH9AkJ2v+AOi7BF/QJTd4g+Iskv8AVE2xR8QZaf4A6JsiD8gyrr4A6KsiT8gyqr4A6KsiD8gypL4A6Isij8gyoL4A6LsEH9AkCEVgAyIskf8AVF2iz8gyi7xB0TZFH9AlJ3iD4iyIf6AKOviD4iyJv6AKKviD4iyIv6AKMviD4iyKP6AKAviD4iyQ/wBQdZf8QdE2SP+gCi7xR8QZZf4A6Jsij8gyk7xB0TZEH9AlHXxB0RZE39AlFXxB0RZEX9AlGXxB0RZEn9AlAXxB0TZIf6AIGuv+AOi7BF/QJTd4g+Iskv8AVE2xR8QZaf4A6JsiD8gyrr4A6KsiT8gyqr4A6KsiD8gyrL4A6IsiT8gyqL4A6LsEH9AkNVX/AFR9og/IMpu8QdE2SX+gCib4g+IslP8AVE2xB8QZV38AVHWxB8QZVX8AVFWxB8QZVn8AVGWxB8QZVH8AVEWxB8QZJbCUgZE2SP+gCi7xR8QZZf4A6Jsij8gyk7xB0TZEH9AlHXxB0RZE39AlFXxB0RZEX9AlGXxB0RZEn9AlEXxB0RZEH9AlB3iDwgyHAtDBkTZLf6AKLvEHxBlU/wBUXaKPyDKhvgDoqyLPyDKmvgDoqyKPyDKivgDoiyLPyDKkvgDoiyKPyDKgvgDouwQf0CQWVmAMiDKbvEHRNkl/oAom+IPiLJT/AFRNsQfEGVd/AFR1sQfEGVV/AFRVsQfEGVZ/AFRlsQfEGVR/AFRFsQfEGWH+AOCLL7iD4iyR/wBUXaJPyDKpvgDMlm4LE+7WbJLXxcj/FzffnuwhD8eh5cj/WoBzvqjn98UcID7z6/u7Yb3yF5WKeVV5lIsWUZChu5YwK2HDjV6aj+P+dNa2ScU0eupTIuI9gm3XR/lGWRe6SfL9gvFP9dr5QmcR+PuDU+mh86jn32YnZsfZuvc+vCaAyCuSXgzx26m7maE/DD70K+JaKZuhFoJD73vfeiNK34RNH06CbuTtjspu5N7d7KtftWxf8kz1LHfMcKXFN7b8ZP8Dw1dTdeNaOtx7K/zugUb/HTCw5L4elHM7Y/bfjXICzW8OBDUdNno7hvtawUfkj4d4xpDfmJjwYSd7AsG/EGXFww+IzG2/T6gz/c9hW2XrCnbGr/n5jZ87ikkXujd9/nxewYOwEbWaUbTBXp/jArUrT9cWCQ/HHmePkb4UalqcauwMDDnrXOtWo8fFZTn608vT5EyKyjzvXeJze9nRfy/yQrKfFWBq7en+zxSb36fRzewcM6CWqwh/y9g1K8fJHBz4f8BFi1n0w==###7644:XlxV32DM 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48fqdsGT73DSsIe55+1saytRDQUr9VSU8/Yrc5hk8fz47TZ8786YtPthkheS76/OmEwZYer5EQ5WT/bSsB9mt99ArnERTvIP+0JYQ4SkVoVW2qUS3QoB3yx0N6A6WLZuyWf7j2HFRXTnBPBk7tDQ1GU549R76WSHkFeRnhRPw/adsnCBYmx6al3+Icbi1fhkX8WiitAWOCIfVV+pQx5YhlJ0Pl0Td0mWpPzcC2CWI8vVxKJmtpXNuvSu8f1b47w1ztIYmjQlsdC4bY2rNGYgDbsXYIrXNc5b4ySNoV3JCj9d/aLQOEtjNwYTFbgsNE5b47E17lvjII2RBtb4s8fzt8Zla1z3HkdpjN2OU35Gl5jQmGlC2F2aU89yFUd8NtWkXVHrFzS+t8ZNGruXKYIboLEjovfddA3Z1VR2VB5L7nGSxogIxYGOj8Zta9ykMfauJUkTp3ZM15606iiN2cYhLAYat61xlsZYj6LkxjXmGXq4+q6xy+8av3Fr3LbGdWtcpDHWKPKSm3vcofHzW+O6NU7bqvcewwqjIBJoXKQxRk1jp1xjrJZrnLbGZe/xvTVWkqH1lfVD4x89B7ug0WUFjfdtq6+bW7Xbsmvc9jlGSXMONTM4kOi3DXfbtUTdYGe9LvmNiy4VlK+RM+OWZ/dbgcUDF4aBZo5XwfUO1MqGcVbHFMJjxa96NOpOM9rxFcLNAUI0TYP71Ltf377a/t7sqyVlAdkp66slZdcfoKwwAmUagDpPUfYVUJYTgbKrb1AGx4Oytn1QOYuy7QMVJZX11ZI6JJX11ZK6JIv11ZKaksX6akl1SWV9taSqpLK+WlJZUllfLakgWayvFpT11ZK6tULWV0vqlFTWV0tqUKp4lINVqfXVAl2yvlpSthqgVjoDyvpqQVlfLZ8JXfe+WlzXxCNM9tXiI+7fo86djfKa2SDn9WJkoytEtEZXUk0qG+xJKklRP5egghS1RldQVs6QerT81uhK6tLyW6Mrqanlt0ZXUk2yWKMrqSJZrNGVVJRU1uhK6pBU1uhK6pFU1uhK6pQs1uhKakgWa3Ql1SSVNbqSKpLKGl1JJUllja6grNGV1CNZrNEV/4XwXfK8wxtdHa2K3E5vdAWGaf2ttIm0LaZtO3llHdbfSmpuO9E9rve3wk7KqOf3fsz9fM/v7n4sUSjZoRsXu5HX9Vncf3fw1HP/K6bget3hLVxHhm/f6qeDdSpBdMn8ryO56IbD/da9u8yCbZPfdK4XD11HpqB7vUf3Ot4SgrvFNImf8nKlsCiCYwZm5fjTUAAyXvWIvwwxQX238YiB7rYeHhIcJ+7q/yKmem9M9d74qXPb5m4K6wn81KrgdASGuah+GCKpcSOpbSOpwlQRWICp5o2pejvs0N9vgJ86HtvDfkaUJr+2RucPfupVx9lVVxmF9n+wDBiO7rTOoHreTQjduaPuFobn/g7zJi+pr9Jxps+NWEdfpUpsH87q1ERheSb2g+b0qApasW/3VSZVoIaTQOuqVnFM6DG7TNi+IzRH0IWh2rwdoeH1Zi7qpc1joz9CJ/x7ng534Q9xWMcSeGMV1VUeDHUuEGUDfiO03VEbXNSUW8BAGIIN8rsluD5oDLVTKzRSq9HY/4t05iyEIj21Isf9CiMqkhn5iKcrbSfh5lv8zJwn8aV4VsnXK/E21Pq76mdvZS6/cJkoDAZI2BmEFp4qbRxHQ0VpMYa7dD6X8MxDWFjNRASju9W28UxgkkV4JqhLbbm8362iipCtKo1j7SoUfV+Ryt/5i4/6ucTf7ICyFsp/DWGXlcARW42xX1EX5/XkjQ/25tlpL0aL8CwPtCiaIv8kFj3I4L1aJH3OGymTfEDZOrE1rJDjnrTtQ2hhUBkOXAurRhtbRZ0uXOfbhDSXue/euy4/3ATvvu96y248L1IJ0FstXxYWh1FdCPYim9+L2m1iu+ovlqZh9FFcF6u56zx3j8ZP05jFEb9ncwqnJKoAbBbVeC+wL3LwYicLwgNeDDo6N2DEfZdtp/I7YxT1c9rYUVHj9yt+uP0r5w+zhZ5WB7+yTp7ufhwvtRjlp5Gt5QaY/tQg7I+72N1IlovAKm/wy6n47sCkz1jO7cV7Uf+LN4oAWrduS/ZvOsTtSOi9rXw9I/QY6gdRZxnVrvvT2oa40H4wynbpZggPBceyH6fd6sy2hlFHwvxFYC3eJ/rDjTKx8b9rPjy/w4DDW9n/27l2l8apy6/Gws2545fbCymbnFc/bf8HA819fpfR5O1sFKvid4xokDFSXZPEB8ly7BfV679bIMO+lnzUMWv/gnTYBsxhMyMSn/nzTw+4jpOm6U369VeTfmVXiNTK8dtx/2nSV/sIZLT3IGPIj3qqkuVC3rfq92/4W5P9q5ZtxIHXNaF0/kUFlPcrOAvuC3tQmml/BWZz2dAfCZzkP6rM7b5xD5f911fHa+/G1VtUEfjRyi8W80L5kEGGq8zdpLsh3tLZ2LHi2fVF6QnURK1el4vDQ7RAlKG+2FMXfmcv2yuq74MsY79YSIG5pak8psf6AfZx8WxdOjT7rn8wcfjm8O5x699hBIWn/XDvPK8GtZLFDX0lXaPjIfLwV0lk6eH9DjOayrrWw/JruPHvHv3/cWlIVQ==###7368:XlxV32DM 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227vyZbFyI7W6IW9Qb6a4mM/ZIct5nOl50q1+BUECnFMvyqmw7VpbA2fc5MEGHH6C1vJh29OJdktnzNtP/1TvWDHUR4b7SMqZd2mSg+XXiXf5NMUeig/wZ6th+qa2WYjndlirriElvYj1DAHwc+gwxV+sV/vL10RlEraXlGEoiQWrpT+7MEf6VeRujNCDmLnpKRIWaqbq3ry9VZ/zC6XXIF4Xv7IDJkH+xprerak10XQyyY9MBAUzTV1ibLqcLkUdJ4uxTWnESpYU51gIfoHH2p7+paV7/5XiaCREZtUTVVSm/5swa/5NcjYstRbQHP3hV6PeUr+mgyjFE3S+yTJvIYP4UJp7HbHrZuJW+/z5m8R7FL1LVJLe2yB7Hgso29CEbB3rdmU3vt4JdQDT5SD5fYRRnmyRdQoR8jTBzhY+AweL3UL2GLgRvD5PoUfh4J7gzsUFHeMWzq+ViUIMIHD54vksQ3NqDZ8wpXTVvJDkbRo5kO/zfow2ynty93bVyTdJCLgwXVbe1xEEMav78CHDVti116xgoAMfFjquFDNHB57Ss+ps8ts5DlaQBdv/vm8bJF2VROTv/m70OHxLlBE4N6qJFTPK50qPo0LiMkJGPvL84pfvQC6aj6a9ALQ8d2mFkg64HNgCEvuelKn4Y0+uG0zguhrAkIGtDqGQ2rAIxT/HqrjSdn9HwKBN3SomGYTx9OkAW+QJptnuEGXfgSPYkHa6e2qQ5INK8K/DaQgUd2qVjeP99Lc6W0LPl5X9sZS5t6NxrN3I9d78i8ZLm0LW6cW9qJvLtFhEcRurYgraFuTo1/l9bIIC0c/bFiYF4+671Zn19Xrcl/B9uCgbZvJtuivQ3FJQ7SdMftUXvtN+1VEf7rAnadczf8s4IUrt8TrVxH5A7wmoT4MNYs0bmD7Dw12f/ENLOoU2ZFhU0jyPy5hL2WIhLjSoSEC3+GKvzVE9Uen1rbaKEEOhxAtpHZDSnEgiHJqlrcH9MZdOPOPOPsqd7ofT002TwdT9PkQnlK4d5v1WAmUPjdX/slJuu9vkVy2nxO2n9Mcqch7fv6I4xlfyT3xGf7LIf/ck6+9Q/nN0oVT2AixT3z+u4RVbTbXTQ8FTfGfpM9/l3CMFFcL8x9L/neQheTSvc/nnxjs4Dg01oYY2hp+LbUO9vmdHqjl6loTyNjQ6XHIIe8pbw9FbyBDMRT/NhwPC6dwW74PHQ63OW1oGCVbncnpm4x/kJx2Oroc/jy34CuxdH6aLvVruaZ9eFYd9XhGmHvVJ20Z/i+XUr//r4Lvax729/9VP3/84nQc87MJff8XxseKR7o7PFEw0mijNf2PSu8Of8inRUYXQd9ZH8cxMpBctsq196/omG6dvVOBKWTkzOx9/ynpjop0XHLHzOYq5x5uP9/mGfzaR/X+Iyk+5XIQ5Z/uy9I25VoC+SljqZTL1Zg/+lpf9L1p0Uf9WQAIix4BI+lr5WT3/MrJmFNr4sJ/EpInf7eeZyonCA/n8zvnj9DxkxPrtTRF5OLwl5dS6vDJl6f+8Zbn9KcaJPO+AfTI5kG8euzzytSlUHAyCMUQ1pQDcOagKN1M+195ZQ929sWwbI827OFOgYejDsrF868iyuiabRuvTwSLbZTGMl7pVBfeoRVZw/wmQwuLt2h6xbXu9VP9egu338+hpBg6kCtP37j1sRIRUx/7XPAk9YeZ5Wim7Wh2aayH/hyz7qDu4gFxciKZ7F5bXQsH+kLL5/wRjN/fGwJDfPXW3wSGhL9pTzqo6J3dIMH8ePXGSR38oSL+0Pj6PYRGLFizuQ5+/FyQJFtd92i51++Yuoe+UgUvn0xnMv47QxHqm1yEGtOxbwPHuR0szamyKeUU+PxjhvPn2H9RwtpumpH840GImj/z2KtGqle/QHbfiPyGaNo//+Ij75S3uKr/JXwuUIMXmv5dNfv/LR6bHXVfxKpu1WeQ5F1ErnPD5ei4pu7n3qCDgRm7I44H/t/Cdtu5+XOCfmtBRCWlX/Xh7SjiuXdtpTlevjnnePv7JhGexywfY26GsHcBoZI1T4aXAOJLcuweXF5o3Qne+Y8qabuStCsZqgQHJCvJbGHnvy29cNmF4y7cVRhTGYWrbBgq/2DabY27rbgxRVxrfmjou5JjV1J3JUHo2ZXYgvBPH/vTjZ9u30+ze1dTC6+mFt5+ynglcX+66INpc81/Ukz8N7v4p/lvQHxmc+gMn/4i4h/k8FxTw3Pt8b6aOoXW3CqM4WH3NocMCF3X/Hg//vf5eGnHOuO+3lj8BtOvHce+TwzfdVEkeTRwz+Kov72bVt4zdkUpx3FuJ6qkbxHWYqIn/pEmXIrPtOp7zrpX/x9NQHFO###7012:XlxV32DM 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ELki/bD9J5elHywQuST9YIHIndIPFohclH6wQOSC9IMFIndIP1ggcLRFQRaI3CP9YIHI3dIPFojccP1yfpUper9DqTm2ujAHtfsfyJiw3+2wRfcvW9T9fzH29/mwzEv8yzMnIFuUPDd2VXH3wLTVf80gCye8SCM94S5O/YhNh6cJpBn9zEOJl/8yJrILLtSE+k0Pt7hj1ziY17FKm6feYKkxB7O4R3Hyemna5td+OC1OPyjv/SPuRsZI8OwtFy54ykc6H/+Zn6cNJSQLz9OTPxbye14vwl57cIGZ0Zjst6SlmKzn9bgMV4qc+nU5/y0ZhueFUUGmLA23XPhxD/2YIWYvp8SclUmWPd8lvOXwFL50BdYtsel58xUVdyiJ5XmYJ7rils1BaYm1SsmqDK9gmzfkt6fiioejKTEjKjt41VCOIXrKx1ziL6hx+tO2c7hQjPt6sDF0U12+xbDAKOYxkVKOT+o48354JIBZz8oeZfHO7+df2WEiQuJeo18wlnQohTkp24mVqyojDa0kGf9Yr6Fsp0unP1hFRwL4mnEkAEcwYtVVVhVPFYr9iJ6l1E7/QR+xSfITMVHZv3Vm/8k5zO94lnzVTVx1emoaij35KunURho7tzbknQDXflVpuwpOcnheE/IydRUG9h2IxOxbVy7P4+dusn268JzXQ8ebylOU4N33TSCtEUoMzCO4ieCnFnCcxLNW7ZjIp8pTdnHzQySsgkMknhM8lPTd3qCk3/F6ZnV4mNXNE0o+URLxKE/xRCwi3KMhjkogfF2yM00e16LiWlRc8wQSHgjAbWelghF5jWvXuNRyV/YuELlaVLcW1a1FcbXsuLlL525lP0ffd2+pkWyvh10aVMMsFUsvvSdD/0r5bJgbMS/giAP6XDr8F3sMWQfXwizKCqYc+7bwAc5KmWdiyOcKy6DUWbegqyzOjxL0u+/Mfj8zxpeM1O1sRttz8/u9T6E0ZfvmnT6Pgwie2h58sKxiNb5U8GIE4lvcKm7f2nkf5/Lc7Di/xxiYaL0476iv1gmegWD2qlLJ1yym006W3MpM3JynpoOrTk9uRSDSJFaxOrwN+G8xb3cfRCiWDPYp5qAsynMFiUEAxMmk6GzHOKN/v4xFuf0eWHdg+fHTAliRrrkTS2ufv6roKuxSrFw1/zCTNc+0k/cfv+/rfT23P5ahg3YohsxleD47EaasMXQYLpewz1yEQ73i7FuJcyfVB+WuW06rH1Q4XuXKl2PPkeV3FRxnOjWXjF50QuxUKvJ6CToXYCeXeGSh+MFGrHJTb+vyoZLbndS5uk7frXX69j0biv3AXvpMplxM1mZKZ6r6PrBpp/0+bTNL+E77rECKe+r3CYXFzElP2c+hWWb0nqi1ljIw6iYwe9hE7VVsm+95OdOTjVMZSmM3jued3scXnRLi5ZM35hTffy7kgagycQK2hX2S0o+s8Dhr9Y/oz/6I7kmT/hH9xVHKV1/oc7+C9hrXq8Mbfepcybjv7+kMnk60b3sqrt9ibMWHHYfUMqhjhTzbgQEZhsaeIfRcfEXg4b03eovpVdZTKE2nDkMt+h2xxpNOefr5MztB2nwlZ7HN7GwHaWUIxMnP8O6jxqP8O72yB194fEZCb//X731mm/uo1qx7d/NovDYcP05q0Q9qJh0I6r6AZEwfPH9i+eafKjhhYZxXaX6ML+LTCg+T9PvXVXgq7U7aWMxXm62514qR9yEh2yRytg/PPp5SlN+OYiyLxvlZpFdnFcqdfcbFpPEvJf57abxW7eeBfIpP785R634VcH6YKL3nt5iHBEfQsfKkU+dejE27nz+1jPnZtZb+m0lr1lEt+yroq/OeSXF+jxs95STiJJ/mlDK0c+5JOx2rXHRe0M9YtHsfpj2/Rww5GaDKPgTPowU4T8Fj3NebNV6jHy0IfU0L5zPNl5Ze/FByqOqujMTJCxT78Cmnhk85/ZgMi3FoqZQ9qdp2G/LZLwIuTuhdr/pZ+3/9SGYj###7320:XlxV32DM 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JjZx92jPDcDR1Qc5VL1lhwaFj7P6kjyL3hEtQyRf9bh+mof3r7zYsB8p7k9oysmR5BK+sH3GimelW3l8s2H2GHLbqhcFH4YZaDdVN5kis60VFOS0UH+ltifL1/m7BMJnObBHX7tJbfNYEI2s97DYPFxAmJKjXF78PrJvA4N7xbQjoPkrVoKgVbsoy8il9ryDruleofo9WrPcz++NfkKpn41g4/MR9o3dSz0PDuOY7O6h6hOe0oPnxY+upNTTd+S+P/3lqeperkGlE5MGtRf3KZoY04BiItP32Y6vlEMGOMy6TJSIsCWJ9sDdVTqYUZsbE0ebcTOTwxm+3+zrHbd+xuTKFPq5SzD3+CoTXhITqYp3VOmJq6OnGJ6L3fH8NSw5tkqnuZAUv29xVU9VPO+sYxdCzo2FX1pQIcR9lj52PMevQgh9TVXCOIrKsXMZFj+m9dafMjSPaWSZkzTQYDR3MQ7v44IHK0EKpnoE75+wLgH3dL6Kc0FxIodhjOPpw860qMR4bkRKUXmszPmryMD+WdSFgNG67hDMudtLycNylLXUP9s50dwXRuZUJ81OIe8lbi7KblTX47uExs8KJqlqCduU/VTX6DpU9e6nA8XGJ3Owp8pm9RF1wu/lcmb1hD18bpNWvsMUwz52HXGm7zDfJ8qfkMm26f2qQGqt4R89pTJgoncxym5ydD0bBQVPZg/ljNcZlcJaGMjSy6HmvlHMfpYReL/4QOIuVDDOvQQwW5uSS9qpeiQusFhk4UvCXnK6C/Ic632qwsUe9QvKbB4GT7tSxyCxHYoiHo/U0l2jv1eOKiIcZl3wUcfx6veNnvZR73iotrTvEGVv5/VDv8aU44i7aKFIBm0fdjVm1ntVBXTp9uZITI8SGVy6whvGUn5dumLRou3/b/w+kB4SWdOQ/8XtJd78GMeOEdKjOsCjrqhRNI8165oGljAzHsiHdhcJMZT7HPTZXpVEc5Mx82yyePFnh747xW479N3Z63I/e5+omzqcyPht3+lqd/0WWVgcvKt66soNWdTxbu8uCRv1GWbfd2bJ5dRliVj1p5JPzMrziNkYKn/bDV06tlYUnlynOkG1tx06qrqBeJkSFY/sVt8oV/p87BQiZ5dMTHQXd+hjQlGYE14VmTARRgg7etiFclrxHSlnuT7yR/vSQDokt1jc4bcKVdDsSTm+ZReqmyOPf8jG5x8yZvy3YqSYW1Q8dGfVZzCR6ohhq4egdo68AhR0fmX8qqwxQMfe56uJ586gRtWtq9b2rZDmXQScoO6z7FAUd4k+w7zP0vZ1l7avu7QdH7S27/sY0yvUSTJqJfrPMA3zDPs+Swsq+t/1u7n3MH+6R2n+Gq6wM/iwseBLwTO5ZTyH7MzthSUviaKq3fxCHIujPNdD/9DBzuD7Q9NdsyNscZw71uFDEHGlfR9w6lZRLDJInOjRXpzfcC7sl2VFuISw74/olihi6LLr+9TMcKpDcbWfsOZSzBT2b3nXLtDQhefdJ3D7ubGt87uaxaH+5k9g7N3cV92akORww4lLWfWvCjS8adDSvmmg+hb+nbybKPMAvoRO+OifO1suhignFP5FmHeGNt09Wu7o/0EmqX3r1w6FHiUoGAaQGAZlvpxXLMuzy4mt/3oKhrGYct31PGwDmNO4Ti/vsTV9q5vNcuKjC2amw66uU+KYrPHC+v1y1royULbVXyLjVwYe3Yhdoc77SUlco3ZbM/e5Y5khbeaVV4ZZcx/rcX2Hi1+5iDvtal6+QgLvte4Ytgts/jWevyXN9NLa83tm+XGWPzMhKs8uYT9hf4/9vQRTu8hdwg4OGyrTXjNth6jZFVS/b/2EH3TUGIbIoQhjb75iDr9ESQq1s+y9t6X4ySvmS+PCDj92IyHunKLd4fvabtie7SHmrmofz08Fo/+qYESFlN41f9qvm6VZsaCbknuXXvdtkGEtXjcl7f5VzGjaHA4NxYwdfEru97/FuH1i2uWL614c911DvsQuZU7rLnncpK5gtmTJ1aLnrRb3Vov7oxbuu+xSAQTy2RdNwh1/btJINI2SWtyuFiBdTior3H7RgjcybCIrYWG6kSoHFK391+9lU4yee1+58dtZKadK6Vgr3NGi1w03w653YXn7UEoVX3lFlK1cSW8p6Qjnro3equmGXVovsty51Fd1WYuV2R4tsvuoxtCTYOLjw7vq3/uvYaacdaec4fwMq+i728c16k4Whv1f77ovDHt3XcOMJcb7vf1LmcGdxcEq0/HrL4Q9/Oi2upvXJKcbthfL6fA2Q7hGUSSW0M+z+v9V/w/WRIf4###7516:XlxV32DM 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Ev4uCDYfkJvMBo9fa013pjwVqVgFeEVq8ixFPAUD/3Z0GXPrSDyix4EVeCjNhe+KiKs4FvviVW/HQtYzkJopJKmkohinUBvYrTwS2K1WLITXkKBTjUMkMSI4BlQpSfHDZAbZsJdl7lus3Fh36BwAi+k95cZ8b7dY1YXDNa8tGg+8wI01uHWnaFmjFj8VsVCL0IPHhwB5Q/0oXJwFkJbRJLNFRD7ISyXpl9mpNmH49wagQsd7gKqDKeD/+aQ5sD4R+oqSggMbrsFJmi7jEAnolTYu10v2orjyuV7v5VCJXtZbuVATrtdPTWHo2v/VzEJm25CuQKGOBUvxPt7Ypqb3VylF4QwbAoKlBKMUG/Dv26AyNzRzCl2dexXLOxne1FX7UVffOKJxXg9T0Xe7mLB7blOCO87mZiwS15S5kVjnhqlzSRSWiJVtMZJJ+Z2jxTJIpjBh77jEhyZiQb2TGQFmb/NSS01EmTB3cwChpYcBAYfTQlCSiUrsnBzpBDtGNIlQWSFqPmUKSZXqXmAT0rM0aVM6ZAOSACZON7Cf0nVE1yuha6kXNF3U7Y1Hm9wDFE2pIWKbpDFdqsKeRaKBHbBf8qCVUtCQP1VT4tBvNdFclJ73TGjhsUn+cV/GDWL6j0fqHhdvcYFYUVM0hD0SsIf3FlbNiDBTSen1EpHl6oSR/5s9Z/wGaZKvJsKlUEluSe0ewfgSLQSf+53bKQHvjEgjEZX3KEIbRWMLXUOeS1zGFJhT3INDbnRcZgoDVt26AnURi2V54bRwSeJ9HAXX+xss5z0js4Y4VNWRAa4wlVQJdgcUVhWSagxQNiBzaiyzU5RJyPtDJXEcKL9NCC0pMVX0RFBbpZmaIdgjKvKJn4r0V1rCj4rMqAkV+VPzVpFfTWGnynv/mcDWkZGGqodpkaO33Cl+EOdLfMUaxTq2CRjDH/mtFOfNOsINELGmzpr2bjPcYiZT6JtejOlgrGbwSIomNS+oICErSj4yg8slSyxFIOYLCT6aDSgVdYMsB5Lje3z/XLNMaWIZLyMs4tI/G50v+CBjNw3esDjdFl4gvQZveOz3ip3p4QRjyoelPWeOgbCfNL29nG0kWkIwm8VobQ77i7AAixXZvO72dLL9aiBnV/K889TkL4dH48BHun4Cl0piG5QaeIu91C9r3DDvwsOqlj/hojnDwauZE2sr6CK1bL8FPOqhUOaGaC3J4fBoov/DxHCjHclx2cV0w1QLrGxc0iQGSW5iJCWHWLPlFucKmFac/WHSioknFJhLlohTDQPWhjwdzu9V2ilfmR28bDXk8jdEzVdmhy672rKrLlubyN8QlrK0/LB/BDY4CSoi72rcOReSYjfVrAkekBWuEK98f03yKabBK3MFmd6xpkGqmKPdlKkoaTOFOFG6xOdbAUe93edGfjGQpfkBZVS77QAyp+SxzX2bnejPLZZI53bmMhmOZ7Gk2JX9UQ7L/ocAUKcfHkBG5nV7c9MUmXApY6U7jUV85vwqquOKEiRscOaPnrPkpYX/IVisUVbLdm+l6dsls6ZWryL/RlPM+GZn/G7mJIHEiGTJ3S8VwxQjzsa7r6w0PbmnKLwjR0YnXuqXvfWTlSbZW8+yAFSzhPOYYY8fsyfD0vRb0uQU0W0an1o/8SmJmadhVwAktor5lFb/Ihbw9DhOweoSLiHdL9Y/DFGTclb6PwR5Tj5pJjKXNP+EGJBoP73xlXtcshQy+ClxBs11V9JkgvfgPPowEEkQMbsCnnhiasJShk+Sd6hZxMHW4vFjCFsGVd4D28zZ858uVc030hUGlFPgivA95pVqIRNXv4hJ+r6+FIh1pVrIxWexpkCUbSkQG35RX6Y4h5mYAYeRZwk22wJnT7MsqWKLwF9dKXtEmVntIjMT6RdhY4c4a0Vw2vsYdxHWzxoZlDGTgHQSI0Gopqxx2CmbU8wl9a9Gwltb1np8DMCGajimLhp3MXBQC3xi3Oad0a+N8gBz/5icp12LuNMlJFelGwEzomUpzXg7BwI0RnxNvyEtTsTycpIREW/BSXiPP1hGcreYoRZrR/zEtK6fmGRsUVbKz3hLc3DQQdkbjfGuK5tCODoWiw+Z7Tb1B0qP/E4J14XaLelwvZcSVgovv6AwFxKdQ+1f9m688hQFRTPXJz/hVLgwnGCIRI6kj1XEAgIbAtqs6r6UaDUu9vNRjw75GcF0Yg77St6SV8JPXQ2b/dzWOFm7o7VySO97oQ/lr94JkBMt7kdhK/3ZMm9DVXVeUS392bIF/GzZAn62zGZok6G8ZkmQ/GqRTLYvRkwvfHE2H4sMxJ0xn7YM7jQcIot1PtOibNOibMuu1zKUtwKUzErGDhqVSh+FFejvsD9hV/8RT/3NFv/Rrp/dtc6xWDtZ0q66+cv+FPZI8JGPyg42YweRjCpicbpH/Ma2H0lcuTt/FbJEe9IJHLFrdulCvb1uSQzzhofe72e84u83K9pzpfcKHn28pmi1o7YQmUpd8oP+B7KZ4xY=###7360:XlxV32DM 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Ot6Os95pcgS7bemszyOFRN7EuFqW3ktzpwKt7466kiDqlonhTJWcPYO7NLvrjfe63EfiXjGCig9DX7EhUaP0IZki9LF00u03S1ORGKgH5JZmQ0Qm7ZWkIMW0qBR31LAWWmhP5O8Q2CSnkb+gC7v+L1z/9wdZZeMmwYdch8Ymqpv5OqSe6ylLQUKZhi9CIEN8zLirBEACiYcmm4hH/loL1Gs9ThN9oieqQJ2BKkPCKRxpcEzdBspX7N6J39VMe3K/EpeX46rWm/uU2zHgE/TprB3ssaxv14aPULXBldHvD5pmH9BKhhYONWtFG1qvYDT8hvL8oJnyEy3Fqx1cul/YAxNvILO/lIDmaiZ9E1YkSPqneErRbl/r1YtLY1NxNebESA6Qfa3WHhjXvbe4CAtpMw54tEj+Ihl+3H34Sy3CtlMIoOrxCfVuGbyjl0dbBvWMtberS1F9QvciDBrrd6H8BTe2kAT8LqCYxwkjXw2tHpw91Fg/yU8NK8rt4JnJRxhpSZRWrbVuN+t7tPpqbcmCEjSdHtByEaFfaDXvbU+Ll5Aw7v6xzru9bjQrckKjIRHd/BwlfaRpVjc8zz1bOw7nR7m9Y/oh7VH0c4VyuLVm/ySY1pnutaXl7DdNOCbyO8WhX/GJwYQj4Nx1JPj7nML1wsr+KoGKO6sl0MJFzP6VQMNVAuXoRtBaAkWTbdp9WeN6R1zRQKXqmWEKqUoprN9dfwtdf+ySc9efKEoaJ54bQ9wTcM6w7+ZCqc2xHGxnI5M4778jizH6NZKP07wyW6qlisueakUsUhy755vQVcuqDLEfIRD7B+TkSgMOQawWi1tqLdNIHio+eZ1LBXp80/ySbMzfhISXTYGWIZkWaW9qAX37xfGFNiOwGYHeCGQuLZpnFbJysO0MYkeuVjS3M+j+DCzN1PCCfCZZOmJp8Q9WsI3RGCYnsdPRU5xx3dqVnDaBnfuf0uSuJ8EmnIyU7UIElL/rT0aCAwnfZZITqxtX29jDjQtRzll/Ni62ybRN8E3iN4GmbRzt7N+1Otu42cZRN5aepiSS9m2csV2xV+RiAkPDGTHZNjY2U1K13KMbd9vY4cS46iH/jJKNM1gF73QLAhMjy/DS7OWxR3p4T82JDFSmF0Wi0JT/NiX8g0g60Iu1qidtctB2zIQummP+YCNYeCwrppq2II8pdkX+89AQkh8DNG704qTZ29QNOYQvXPx00p2RagiASoVYFJP5YjJfIPNyd/L22tKlMm9i9phIsZLmj3wRqVKiXLZL0UiQtjlMZheU6NIpIYATQ0CllHcuNoVb8iobEpsi3BQCisJLgyidIjeyshFm9xCnEVYuwiQDd+yRpZILkjxsjzSt2SzJ47VjJ/TwmCeIZqJct/oAMlDSmqOHe7Z0u+QOY9fwvwHJlrORl9yN/F/m1cxGcF67XSSu6BU9aqL9Z9Xy8YEKevaKpssY0nqdh7fqNCHIiQR3RxYcV7u1lBs5cuYU+LZqpkQ5ZKGax/F5BukI+qSZmYDcE2NFNjiIIPmczv66Mbyl66kGzbEtfVMFvh8z1fqXJe0xkQRimfHKW0nxhCGu78ehuQeZrFa5ov1H+vOQWxOflCBWizqFfeT8aEZcoFcM+Xvl1u5/y7Da4dmPNtn8jLz+LXONlFrJWletRFoZ2UPBfybSVSsRJ4P/KSF/BuVey2xT5I8xDokryQh8wXUWtAWlFeUjSboUC4Et/GfCJfoLHNA+Nve1zMiUJySkRJMUW3+vL841l9i+YpvELLJylHra/qmn2WwjS7J6FV62Yo8mrtbEmCZryGLBa7RVmgWvASKSUNUSKWcu1z/wzHbLKSdBSrU/DzUrePYa4C9P/81GZYRVqAW38JeDs4RghA2oEZkdagiTl8rxlcOEOBOqzU77/UPghgibnIMtk63TWfOK+rcbQXOiISS0b3NGTfJC6UEw8lrESolwLbdN++9ws4iV07LfP7wkGGk7mBXTFEeeeWvxMETO2swz+3nwr8BmjcmcoE0VEHtqQSNSbdHkKu+qEw3HzMYRm7DR5KbtZBBnhmbxSD+VrE7Usc3jqmJp5dDZv6nKsD96+Y5/7r3NFNncd+jD9zSmNeQOYwQ2MB8aavC91SAnoIPJ8dE26e7+vP6zOx/t37T/7OYr9MF/drf9Z7ff/9lVfarSTbPRNnx01YPe0VWsBumzqbLnR+ltG6nRy/wZeSm9a6RoeAiQfqSHj3OimXGhJYCLAkg7dPs/0Duuv2GjKXSYiUbFIYyhfxc6zthnwZcZeAo4WQiKmr/jUQTuXOnUTHwcwR4PWqHDa7HNod8E4m/H0dNvDNG3eBhDvjH0PyiGkzE=###6916:XlxV32DM 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mfiYXQUhbU57yQaCPCGs9aUpvwmcfhM4/SZw+k0gnzaOfJrVsPVAUgvrc/DqHMR3qBUiSTkQvWYgnXu32Ifr6nCLffhJm4eVy8PK5WHlssqr5i/4KfNW+0GS3EW60ki0ydFWH4i2IrXvVYxaK5ev3Mt6VbxXxXtVvFfFR1nNToNoo97LNPnaWRqb37Na9Lq+O6rvjuq7o1YbuTijZc7XCvPbgRAscYq3j9JODyFdTfG2cmn6CaUu6AR/BddB8J52O/VBnqbtdu9993Xf/WZW/XZQvdx1+e3U27hc49fldX0H1O43vew3FRtvPH0WzmFj8zUEmkZ2U7Fy0U88kI7DbVn3dd/dlnW3Zd3Nefcbq59k0U+yePpt7fTb2um3tdNva8VvZsX+Y1gfBe3XR0G1hYoXu+ujoPz6KPBseoFe+8NCzpnPKqfro45sLkZx+MBLIA/v6QKPOyAyUrcYRLKwRdQXY+K8Pu1hLBLxWPhIUb9M6mFvV9PRAz/H09mT97EGe/or3/LsZA36IZlz1+ycm4wwejb0k827s6h9s+FkzC2pAvDk64yXZ+ObqgUTLi+svtkHu5btMaAkvnT+XOrIqzE/+osG3jPqY+R42R8Q/bGoUBz+VDmbohEpMuJ7Rr57PJT4dwviSKjLt5D4kSU1r9vsN5Cku5SvIsU66BvNwiecNgkQCJ8+n1Qm/MVT/S+eQ59eslz2AFbgdYMRL4bDDr6anl/J+FgfunGgpOvz5pMnC/SB2ypefzYbsQbE4ms/xkR7hs1/fOzNJ1/Jw+GDT+caiyzQ2xqZPhFUTRwelBv+L9CgsdfmLGSnbqq4/64xLyS8T4gUgOjlmac+fY14kyn+kDzvR59J40tHH11ewQrm51twoKD8aMCC7/NYoGjYQ3lJ80BRtUDRMe2/pz7VfUiSgJmGjE4PGZ0eMjo9ZHR6oAiOtnmYe20e6lv1G4wGirqGh+hcBNGhfOliYaAIt4F66XqtuambREfCQNG4PVCkxpWE7r+3fqhQDQwUPY86deso9r8ADBajopg0Gqy2s/XSgWwarPUFMM2B9CyjkeUkBSWJD995WpoQ0o51M2UaKNk7CKaBJA3fFlyTLXV12PODAw+bk21hEB/cPvIQHw7AZaLEF9bV2azrvem/b6ug/gYJOrjXZW4zQlUI6kZzTCJKhsq7D/xvCwSf6KM/ZOpvKzhRVrer6uY5oo4PRN0svatuhKib03QISvb2RHVT6lc3OHlaitqI9qbY8Ga3QfnwMLmgrS+aDAxZaqwPObnRTxu8TkDManmgTVZBc9WbO6w52suYP6rRibqnffXW9G2EPlspuA41H0lz0T49OmW3bgEQn9BD9KGijye46AjR+Ktui+4uurlo72s3gpJUdLNeD18XdBZexVyN8mPTGV852MQdxGPx6odlL819s3Hp8D9CF5Vf2fD7vz1aRCV3Pe8lm6cmUCMqVT/RmM1X7m+xN/JCPAORDZc9PvKZLfTNbqxtHv3bvMnpxVcE3udPb5vZcoTO4b9G3PPxq8ijJx1DLoHZw7PHr2xcZGpRtZQ5NOac8LXCjRVQ+xVH96OvLkCcOtB96J9ZXClH0hgP/9Gip15Iy9kCOOS3SdaIr9eNlhuH505Pm3Ar09VOB/PqoIYM8cea/pOW9O9tNowZLFfsGvRCzExLxqT/L+O/M/xXcVlImL+bIUaA4VUP2DCCkIoFIqQVHUC2NPmxGG90MFAdgLV72L2HA/Xh2Z3p1fhlqUkDnSCeKNKFj4bxXyOQ84iJ2tk3s++bZkWzo86ehimeaUN+pnUbc7tnL9sMYOYR7IAUzIX24ZnfRhBwghhMGgVaI3rhBg1vpFgj6AIbSd5IZCPHtxH8jgjRzUbCf/dA+A2SDWdvpGoj/wddsT3f###7480:XlxV32DM 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RirHay5Wb97Gkk+1kLWuqlomOR/bQtlG9c6Mt5jh1YoLcy7DyKV9ybBEz5j71+jHyKhSOWPmr9E/ZA0PmPl9TMT0YyLaA7kjk6GoepTF7MhXSABdAVRJag1ouK2Gcv2qodSCmkJ53awj0RJHvfTva7VfL2IbUkl7xWaR1GgRmXTT+yzpakwXy2b2n20VlJ+5KN/HGxHxfxD2fc3cTizhULdSTzZrWNAcbgjZvd2ZZNSavs+gE6vObqTNQWZQxydekPoLh1z1dcbE9JlzcFcruB9taVBBVGQ3Ix3qaiEhCrR/ptP9TV0d6fJaPu98uuhBKMJzqUOm38Jh26UVGxIRp3+RLbmwi9W5YIiWPB/lwPngaGI34V1CMKW0VuNWKLKljVYoMfgMjqdWPH7neFKaTHqk45tT3IA0+dhpxSJtoMWL0ZLAKWazNoHkdgHBLlCEI5PIpaXiXpY/4DOqOSRvoLzi03Ck8lUYvs3X2fcpQnKcVKtPzlfvRu7pF1lHTxNBCf5+ydBa20tJkWuQRxtk3WRAOsiVZWFKVk9zF0ZsgTS0AjLMl7SyLUzQlwyLemfzvrVRyNKmFXBpue+uZNk/9RxgDa5N8rBKvqNaGo3BYwuXr2JK1chUazV9FdMPmWrNCkA5uhmZaq3mX6N/yEk528ZZ+HIGvuNbuhWHB5qBiPTrgyJUVTWC1GPfiyuV8kCIk0Q0Ndy3r2Y1hFudEnTCMjYSTjGwVo9R6GjJaq2xE2U6Wd2732rVipXR/pf1QQK0HPzh7QdQeyPSbz9mTWL1+JOsV7IvMaS8XWHvy2r2+61XTz8ue7yfSt3fKWOgwfTALNqULBW2l+UOdmBIK7Z1WY2Q1kvZjwTfGO9GjlHG4MafQcMjt7dHbm9aQqe7BaNkSBs2jWZa8qIs1ny9FoHLVtd3yMUDa80Da1bAoB2jIRZMWgwcBgvLQNNl1XzBJEyNK5hK6IhrHmO/v6O1vrM/blsGty3Dr9FqkieU+//YcJF5lE+KQx/FwJyDGo/Vsgo0pRr/dVEDSs0wJiTVif8gLV87zjsn1k8nS2IIUkNRcytjmynYzdaTsUxs1MjERrKclaZtmMqxlE90tyaqG+upnO5WK66BZJM4SWBNEo1HM41ptQ5PT6X1SeXQGC3bDMpidV/HzrW4RcnDMovJM4tzsAR5SXxNA3pDjWQMjt/BmkVMnkWckcGMYmYrBmvApMXYfrJ/8CZhbUGBrEX387VaF+2U7c+SSIDbv/albMD8gnxa8QgqUTUWxFpfABi8y11J/JjyM867DwVUhikxga3dX+vOXmSKf1oB0K62f4kQBxF1Zcn3A17/xeWt1qtYr9d6bRpUqDJnwvXhglh5Dm0jgQWNtE8vA5I23EZN66qyeQs3mB2LkxFqLpb0A+IyzOGjmZUs4B1phVmZImyhqn+ObDVJgFTaUjYjvV53tfRw91rSu1EYW7w8K4uq8mTuq2Y/w71+keFh3vsnads9aXuZVOxo9cKplq+kq9ELz6zQDabruJn/oYox55Aqpk7z1swBVzGjc2iF79FjHsdYzToxNdqw6dZP/by7w+rqDTuN1C0EmfhTiLrInC43+4r90aII27mv8fNewyLSdxTv9dU/b/mORut4D1lLi3GdLzI4QydcjtwtoqHR6yi1XPcuZir2+zWyBLw/ZJiK3fIGGiP/kNVUHGbNSSPtmmHJXDTSVOx0t7UjTcXXTcXXTUUh01S0pATQl6ym4vN+51ZT8XFTcafyiyymorTxR5FrX3bDN3dPQ4iavHqRwcT/PCiQkMPLlxyZomNWE0meR5HYs4qEXUViYymSMjGgefwHIiljUiTlSYqeYejuho5BRzSMl9mNl9mMl1mNlynPiKJkXM1oXM1gXI1tXI1lXI3HeJHILNFlvIxpvIxRDXXjajTjShJXRMW4Qu2womC89G289EVe9Mcu1b2lecaomKdWmqkSwC85kazvwmnMv07xfe0UFckpKpJTVCSnqEhOUZGcoiI5RSCcoiI5RUVyiorkFBXJKSqSU1Q0jBecoqJmvOAUFckpKkrGFU5RUTCucIqKlnGFU1R0Gy84RUXTeMEpKurGFU5RUTWucIqKsnGFUwTCKSpa5EVPhFH6ZaLaL/P+W258Lw75+pIRbbhve3/rHc2Cvqqlpm/WJUrSMK1vNgMvwmW/LmrR2m2I9+JKl1W8pWVFcsn+xAb6KZITo6NvC0ofnzh+q+Vg4wKpMXZbfO6yyhl+RTdi+lJuJuZPW3Wt0+DVbf5FOMPDvwiJyjKUX0NSoKUo3obCRSR/ERKtYejthu5q6CqGZjY0kiHJ2ihqxpX8RUiUjSv5B4coGldIdCtaxov8RUj0GC9iXRBdxpX8RUjUbIT8RUhUbIT8RUiUbB3yFyFRsHXIX4REy9YhfxEqEpcaxromLOFWoeoDBnzoFoBGBZa23be1iaRq2+bP+/8DDzRakg==###7136:XlxV32DM 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IXerEbaGjx/X1VTGbuIBIIpWPGQHQulmNdnDfPuJiDfpnAVJl2XCo36b2eIaH+bII9P6DRCfffNM9dGgQqOuqDFwHaqPcuZjL8cmhC2KaC0W1Ud12c62KC8vFl2Xs7Kab2Dh0WZ1n+2TwCjoORUTnX180h/EEzR7THQev5KnbWayafEhzYgUcShqx5q8BrjiwyBzCl8zIyq7LavW7y8zQtOe/ZIlSRwV9rxj2Pwojer5/D6I0MvMHl3mR0ehPb+/Hkxu9vgYp/+dMax6dpX7T573qa4NnpPV8Ok5j0BpxjScqBae//HIklUwi5WF8kZBKL6bi5t7NlItzX6Exc/K2gAmLpyIuZN87tqWXbykf8IktaXM1YPzanMdmHA4l/DGtqLKj5vL2z9hodi2wAnOBdfc7N0J77Pj1qILa++j07Hw+l7NOyqxbTPOBl8s3H3/uttmjfvXjsJwZPeviez+NZHdv3ZkMgJZvc/RLauVCB1dXcjOWom6fs3uXzuy9UZUs5CFyURZPbX7146CemD3rx3NR+i5hW71zwoZji71z+5fO+rqn92/dnSof3b/2lFR/+z+NZHdv3aU9ZzdvyZClQYIpVq/f139hrW15REc3nL+jNfhGSKfs1AHHv4JOnFMxV3TfPZ7Y9kXq/c1/ZL2tesu1Oe+sl32Bey6L2pfXtxvmGwHLjf5gWONur1brZDMAwsgq35aAzgY/wieOF9tH0j7TRTeomQmFq7jY+a5Jcx+NrHPPZDRYG+DLy5+Tv+9gAOJeAwDv7vg/JpRT8XOIPP5y6zrO15uCCN9zajvGqf6bu6/zIf/K2Lfzzk+t6D9Lg5O7ZRC+Z2dV5UO3MpBLRendjwI60XXr9P83sXZJ066N+THul7zzSwxu2/nq2ve16r7/lIe7z3tU1jxa07PvmoUe/5lfvxndopYlSK+t+4fHZ6o+iUGnbJ5J0LwqhMTw1Po3UUi/Ejyiqv/ME80y+uVTdS2fqpcPxV2nUqm7+h/zSzA9/KtcmH8UNviz9xRpdmZddTXfbmira6DF+XUd1MBvmfVyuKp0v54dgE+H7iDcbofbgMlWUOXVXEtUXLOEDmb1OQMkVvJk3OGyNk+TM4QOTuSI2eI3EqtnDNEzkqF5AyBs3SLHBA580bkDJGzyHPoKMG5tbM4Z4jcStCcM0TOFj45Q+RWeuGcIXJ2SZScIXJN+gGRO6QfELki/YDIZekHRC5JPyByUfoBkQvSDwicJYbkgMhN6QdE7pF+QORu6QdEbkg/IHKX9AMid0o/IHJd+gGRa9IPiNwh/YDIVekHRC5LPyBySfoBkYvSD4hckH5A4M5X+gGRm9IPiNwj/YDI3dIPiNyQfkDkLukHRO6UfkDkuvQDItekHxC5Q/oBkavSD4hckX5A5JL0AyIXpR8QuSD9gMD1V/oBkZvSD4jcI/2AyN3SD4jckH5A5C7pB0TulH5A5Lr0AyLXpB8QuUP6AZGr0g+IXJF+QOSy9AMiF6UfELkg/YDAWQhCDojclH5A5B7pB0Tuln5A5Ib0AyJ3ST8gcqf0AyLXpR8QuSb9gMgd0g+IXJV+QOSK9AMil6UfELkk/YDIBekHBM5iZ3JA5Kb0AyL3SD8gcrf0AyI3pB8QuUv6AZE7pR8QuS79gMg16QdE7pB+QOSq9AMiV6QfELks/YDIJekHRC5KPyBw9ZV+QOSm9AMi90g/IHK39AMiN6QfELlL+gGRO6UfELku/YDINekHRO6QfkDkqvQDIlekHxC5LP2AyCXpB0QuSj8gckH6AYFDpgMOiNwj/YDI3dIPiNyQfkDkLukHRO6UfkDkuvQDItekHxC5Q/oBkavSD4hckX5A5LL0AyKXpB8QuSj9gMgF6QcELr/SD4jcI/2AyN3SD4jckH5A5C7pB0TulH5A5Lr0AyLXpB8QuUP6AZGr0g+IXJF+QOSy9AMil6QfELko/YDIBekHBM4K4OSAyE3pB0Tuln5A5Ib0A7pwh8MiGT/4SH4dgKSlf+B4C8WQn8WW8vtBSxpQyNvI/y6SSvgd+F9Dgf9573B/CJ33Dvd1auIcwn2dnziHcF8nKc4h3NeZinMI93W64hzCfZ2zkGO4rxMXcv8PyzlJMw==###6700:XlxV32DM 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GqR9oD67jykjjsLj0Tg77ZYcdETJjt1lOd2b73ivPc3B+DbCMMv2WzBuxzru5zU0AdHTmLT+SGxo329b4bF83h53bsWfUcTSubjZ057mpzUWsac9ebP/H4xYguQDITU/reVkT5WsL72IjZjU9JYjb7p7hhpRdrTgmuNtLKLb3Ma1b+J28OIt3KXXe/bPCA90u949WGrUY9Ckdw92fewxaK0KdO9Xga4RnylcGjoj0J0PLqICWFBSCt0rMWIlt54NghjoRr2jAM1K+IInlqjR/dhC9eKpVJyDP79fNU9JUHNFiG2f5wEOOx7WuXvkGCNDWdxlYgH2Dysek3XvcyOO2TynU7LtHjski2Aq5/P1yHqQv1EZpBcFA33NTifip1NqPJ55L59s74jCsLrhXIQw5D23dbDyXTB7zPciaNst+tlPVgoLXLejR6r4HmvCi9HhBzGsCNg1bd3BR91fnHlr8M4MQzWd9+sjeSxamvoIBrgqmT0/3a4914QMQ2vX89JY42fZaVSjNVy05vkUt9sfdWKQ83yNY+M0mW99VmaV9vMLtnHGE3nFE3587VO3L50fX/s8vr4r1pjHVywP+AjH13zpXJ5PW/Kw+xn5ALjU8tz2Q041NZeHvG965VcONi7Fret4e6p52f70xYfB2d5w0ngPCkC7pTpsEKc9aCtsb3TvZztFY8BQiFM0yAZkSvb4Hw8MjfxMaPH+ivxXMDJPlP0TjDA2MplCmZmOoDp7bEj1aI5Kv7XMNVpvCobaTx0UIip93qZfk65Da6qpsZLu9jgeq76RT8503L8+rPPDTR/6I4a5utqHPKHxBOdnwzu6IawMDLLvpPB30wYIIT6M6fJEEz9kSmW7/YQyapwPxs/4q0acCbd+1k82yGebzTs/9NX+nYyM0etyf98+IYJPCHzIbNCMP4w+aj/0vccn1/BR+6Gvvb76UNi8bg+Lh3aRJuhbv6cQDAfEoZ5+qr+OOHxAY/OXicy3a2kp49jHzOBrRwkm/Map+ldUAeuIJbBrG/FwwqjinFHFOaOKc0YVnA+FMQLjCwTajC8UaXC/QHyBOcn4Is+oIs6owiINxkLBowq277V3V3iciV+C7WkEGJ3B8NjGik+qtntSNW/npkfEjw89L8zdufuseGwrsIexlq/BUvo8t8fb4ys/3JoSdh9bT+xz5HCw078aH2+9/HRmY9hPZ+Wjw750J53Ono0jAzoODJ2MX00XA8+Y3zrFv2XOujA7dhzy55biP9N2t12RbGzvV41NIR5pHgK19fqxk2NO6e/87F46bfnwSMFODHy7vd+5fJLMjEqR6sWCgJzwJ8mMR8wm42S5PY3+k/u7fdLNtD0+DCqc2sxQew4eqWW+Qb+VMB9mggKgW1n9sUTcPkbwoaZS+ob3OFrgGO954DyzQduM/vc0jxYhfBKBHzXvKDqyBXjheFe9uLyzXlzeu15c3pteXN5JLy7vqHegd9A70OvVO1B7Wu/U9Q7U/hTudOpNqv3vxanpHaj92dupqFX2x26nTa2yP3E7RbXK/pzt9Kgt9kdsp1ttwf5LOtUq+2OUU1EJe0TstKuE/bnJKel3WOzrFPQ77E9LTo9+hwXi/k61NB99+16VYoUQdzN7rboh2mv9pW6u9vuTXuqvXsRLSvQiadeLS/QiKenFJXqRZL3Y/w/g22kB###6936:XlxV32DM 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1cHIaDpuNZ2r+V81/8tWnWRr17tVxzZGt3Xu3WTNd3O1SjNapYT5+sfW/lmYm/kGI1kD8w1GIms7LiOdh+Wvav5cLX9Vy1/VdolqFbPtpN520nuItdiyavGxavGxajFZZZjwdTjmg1NH3nRXl5DE+NBRcA11kXtzG3MjbjwLP9g07iMHFrp76HZeoYOunE34yQ6fSJTmQaPTB9HkzCFcOmkY4nZyqmAanyWYxicIabf11Y6cFpjGZwS+oeOTgUjQeUAk6BQgtPEZF+0cjulS3bOmXNPraPGFtJdj3LMxt+Uwt3VMK5sR1eBCo8rbkOjMVbbOPIJWdQypo0WCqhfVwOZ2dG5SH6v2GbpsIK6AZZYV4zabG9e4qkGxtTfti8mWgTG4Yn1QpwrKydq1F9JehtGG0cw3uMIUbk8vhHbmEf2YBPqjepHvxrhMpLDg6lDABGgAGmJc+RHggk9YCyz/KuB0oeGKXMFJK3TprcuAngb6tkEKWBmUCYBhqc6ySgpeZ/68LVJ2gdc1+AbXSoZU4sNtsC/XQELTF2xS8Ij6tlimNRbUb4ADVgVoADZprJCLADqE1CDim9V8eFlEO/VhqS1UY8suj2WX+MDnPqtiDwe5PuCLN64KdC1stGbZIC7QoraTPV6RxZ3/rHKHbDLZZGNki46DeOc9WbnWSzZrLOQU2Wsf7LBCC5ZdnPVX/QtpL9XWLxutm0Tvxq2WOS2XPdA+2GqEaDOy6OW9TMc1/6qWnS1SeY9Sa5n2SYKIPs5uvWKTCpou4PbGQ/IbyHQ9z3dgYdTPGZC/YzKgXZeDWygelAnKBKWB0kBJoCSl4AspA6JwJqhegUgtSC1IYXRvox+0OWiD0T1G9xjd2+gBlIB+BvoZ0KdDH9OwgFIglSGV0WaizQRlgYJZUKoRKQd9CvRBzx6r6m1VsWLO9HnQM6zjN6Q2KFgffyBVIVVBaaA0UAYothoHFKyzi9AngoJZuIJ7W9oezKuifKATrwrwqgSvCvCqBK8K8KoErwrwqgSvCvCqBK8K8KoErwrwqgSvCvCqBK8K8KoErwrwqgSvCvCqBK8K8KoErwrwqgSvCvCqBK8K8KoErwrwqgSvCvCqBK8K8KoErwrwqgSvCvCqBK8K8KoErwrwqgSvCvCqBK8K8KoErwrwqgSvCvCqBK8K8KoErwrwqgSvCvCqBK8K8KoErwrwqgSvCvCqJF7Fz4OQqz5eJTWCB5gADSBh29W8zG4hrAWWf9UaQoG4N3Fs326gH+uwgJVBmQAYgixku78AU9X6wXT8BjhgVYAGYGpYoRQBir6+4RJWzhRczD4oNvgTVLQnV1ISf7hFZP1r7xjV9mjeOzw+Xwm32Z5V+YVBwwsD/MTHbxtf/0lGPK7TvyjtffuueJzBu7U8pQgdT91WtccZ+M7kfdvvhvydjssteXMx8EzlIn3YnvvC8/5MP/cKu+kzRW2oj+enbqEHdtpcQNIKbv4zINPDev378XgNpX3kJai0pu/0DOTr3V0NfZhFfwzLI1xG/DC3ObwIZiSPeukduzzqJcS0SG+amcZIH/Au3d0LlR/82TU/feqfqfwwi+xcQmzy3VRE5DUW1TMsUgKfczMa8osDaRiA5JlwyA1TWQ1TISRTiQ5TISQ0j4fRjGQqE1Nm9JkKu1P2Ob1/1+SpBLrQ9eJtD7ztsfcs+oRMH29Ee4pR8B2VPyRf6+qfrnvoux2rdU/Cg+vs+nj9ciJu7ELFqwt5Kk3PRzz9Y8YaCJtGc1RMyqdR1/v71xV5D3Ebyr8pngJIv9rWhq+2Sa5z+GV6s9fM/c3W1wn26ICJWX65wdvOtJr9vEn3C23xKz/67ViQd4oyJRRB9FZSEBX2guhLrqAxgOiHbUFU7AuqFagUICrEBdGPvIJiBArQil6DKHLQ6n8v+CoV###6324:XlxV32DM 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wYth0YtE3t833gL08XkqILtx19jmSUxfsURfL5l5pxFZDzq96BPWXvTAVIec785BR2+1+QUfDjpMfNBZjx50mCit3rekgfigc2nwCcRh2t7t4rbqNlejujJ0R4J5UNa25y10XUvGCI6HXcYjZMLX8nxKeusl9vKtlwRkazT/rkZ5X4Za4ILV+F0QYtSiLoh9F40kIx6FmC/b0q2XJvsSvxEy+bb3Uyv8ucgPYOUtW/t5jfbKFoCofb5b+XmNZmKu+JTpP6WnieH4tPpT2sUXXizYIp56YAXx2OagY8vEaVFD8CAOIr5Lg4hM5OPtEGzwuj7oik/HfI9hR3kfTNsZZn5ZfGWW5Qbik5GDBhSb0CUS42eJ4CZ4tq1LhLcpXJhEs4BRKuxnKmFmnx5b377jR96cD1c5d3u/fefiIj2/f0pXFcPw33q6ltIulpbd35ZNblmTllWLyGDl834Gc4YnnFE6Con8wpPfArKx4O/Hlf1S5/IK+lgzrFdf0Oeu/iG/gk3DxDzzsq5JeWFl4iVXWfdPgCyZGPdkejEnATIXS8v0IWJo35axe3FsgMbQ8Vzklq0J3VNuuwped5RDxeJjQbcYMkeOhz4eOIZv2ftocXZSDN1ehvT3cxWsW6U+6G9kV2SdvBrEAfGaCDr/QRyAbxrYAfE6eTQoD2IbWN3IDZ/VTcM1e9hCWLZORv9mZHtHN3WS8Xk04+TwfUxDnn2Xm2aSYndsjtUxGNbtuBynPCJXvcDu2ByrYzCEXuBynPIkXfUCu2NzrI7BEHqBy3HKA3fVC+yOzbE6BkPoBS7HKc/lVS+wOzbH6hgMoRe4HKc8vle9wO7YHKtjMIRe4HKc8pRf9QK7Y3OsjsEQeoHLccqPAaJXsDs2x+oYDFmv4HKc8puB6gV2x+ZYHYMh9AKX45SfFlQvsDs2x+oYDKEXuByn/AKheoHdsTlWx2AIvcDlOOWHCtUL7I7NsToGQ+gFLscpLp3qBXbH5lgdgyH0ApfjlBt91Qvsjs2xOgZD6AUuxymxdtUL7I7NsToGQ+gFLscpP6Ko3mZ2UrA5VsdgCL3N7KTglN9aVG8xOynYHKtjMITeYnZScMpPMqo3m50UbI7VMRhCbzY7KTjlKl31JrOTgs2xOgZD6E1mJwWnvANQvdHspGBzrI7BEHqj2UnBKQ9aRa9gd2yO1TEYsl7B5TjlAa/qXWbPBJtjdQyG0LvMnglOcbNV7zR7Jtgcq2MwhN5p9kxwiluiel+zZ4LNsToGQ+h9zZ4JToltqV5gd2yO1TEYQi9wOU4JzKne2+ykYHOsjsEQem+zk4JT4gmiV7A7NsfqGAzrdlyOU34YU73Nxk2wOVbHYAi9zcZNcMrvZ6q32rgJNsfqGAyht9q4CU75O0L1Fhs3weZYHYNh3Y7LccqvHao327gJNsfqGAzrdlyOU360U73J9jfB5lgdgyH0JtvfBKf8tqd6o+1vgs2xOgZD6I22vwlO+QlQ9Qbb3wSbY3UMhtAbbH8TnPJLoegV7I7NsToGQ9YruByn/KCoepftb4LNsToGQ+hdtr8JTvndUfW+tr8JNsfqGAyh97X9TXD+I0ccjpTEJ6bPn2H8w4P8Gbb5v7K3259hM33+DONwkvwZtvm+n8NpRcvon2H63JdIHiq83f4Mm/vzZxhKE+FHTC7CJzYmuvCSWqqqwZ9hT+jfb+Brc3zD0pxy/36//fsNfDWGb4D2O+vfbVRGfizT9zJlx6HvBUjcWYw3FPYNcrcrF0cowlFEJrw2ubP+3UZq8AS+X/nz+5q8+Hi73O3ErmEF6PZGPLiy4mtSevySNNp6aPz9HzWPavw=###6472:XlxV32DM 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116ceNpV21mS5DgOBNAriRS1VVsdRltcoD/b5u4jCQ53+p+snoHBTBCggsz6s9X1n79jbeOfdV7/+d+/4zzXP8Of+t/fcZ7an60uL4+XuBjP4GUqwYPx9HK9GT39jNvL5RDfxuPD5dLUpsu4vrxpatNpXBCdU5sO4wFTI+89l98/f+vv1A82bcY3Ppu8Gl+I5tQW4xO/c0bPxscbvVRFT8Y7mNFj8jPkVjf8Upd7Ca7GzPcxBxdj5jt5MGa+MXj7GTPfiG63MfOdfBkz38mnMfOdfBgz3zm13Zj5Tt56Vr6TV2PmO3kxZr5zarMx853RkzHzndHNmPn+otu1fjO/Xx/rn214R59ryacy4Gn6/fLpvvPpuvLpPPPpOPJp2/JpXfNpWfJpnvPpWZF4euaKp3HMp5qzmkrOahpyVu3KubQz59KOnEvbcy5t2/NpzVm1JWfV5pxVm3JWreWsWs25tJJzaUPOZfzlXMYrf0PjmbMaj5zVuOesxg2zauf9FFZ5iqQMrfxZ3yVbahnxVK78t+Fs+bRS1yufnsWHp2H5np60T3dWw5ekt47rXY8s8+k+jZ86no7lFh/Gbx1/Hx09ZLp34/mN3idFb8ZvHQ/LLl6N2xt9FA2+GD8/2LTeo6Jn4/oN3kVPxgU/N7kZD4jm4GPPXx3ftSq6Gt8vl1nRxfip42leTvFgfCI6B79+xgd+5xl93cY7pkZmQt9SVL6jSUzXYcx8J+/GzHf0kOnajJnvjF6Nme/kxZj5zsFnY+Y7oydj5jujmzHznTwaM985eO1Z+c7oYsx8Z/RgzHyDz58x843Bz9uY+c7oy5j5TmZC34bb1fcQvBurvsGbMfM9XcGrseob0Yux6hs8GzPfOfhkrPpGdDNmvjN6NGa+k6ux6huDl56V74wejFXfEX38jFXf4NuY+cbgx2Ws+kb0aaz6frncG1LyPS2/59cybcO7WmIxHcz3vvevbTn4ZszXtpzaaszXtuTFWK/pGHw25mtbRk/GfG1LbsZ8bUsejfnallyN9ZqOqRVjvaaDh5671/Tg/Wes13TwbczXNkxtv4z1mo7o05ivbRl9GOs1HdFM6PuW1bX72Ev21VjtHrwYq91Hb9lnY7V7RE/GavfgZqx2j8FHY7V7RFdjtXtEF2O1e/BgrHYfg2+/nrt2H9Hbbax2j+jLWO0efBqr3WPww1jtHtG7sdo9mAl936W7dl+DF2O1e/BszHwv8e6wTcZq94huxmr34NGY+c7Bq7HaPaKLMfOd0YMx8w1ef8Zq9zH4evesfGf0Zax2j+jTWO0efBgz3zn4bqx2j+jNWO2+Rrt/P3v87+/TZ9v3j39rG37x9Om7BXzjMPPvV6uuEcS+sM7GagTgyViNYApuxmoEiB6N1QjA1ViNAIMXYzUCRA/GagQRvfyM1QjAt7EaQQy+XD13jQDRp7EaAaIPYzUC8G6sRoDBN2M1AkSvxmoEYCb0/QLdNYL42rdMxmoE4GasRhCLaRmN1QgQXY3VCMDFWI0Agw/GagQRPf+M1Qgier6N1QjAl7EaAQY/e+4aAaIPYzUCRO/GagTgzViNAIOvxmoEiF6M1QjATOh7TNLV9xbcjFXf4NFY9R27Co9ng1XfiC7Gqm/wYKz6jsF5PBus+o5oHs8Gq74RfRmrvsGnseobgx89d/WN6N1Y9Y3ozVj1DV6NVd8YfDFWfSN6NlZ9g5nQ9zDse5Evv5Vf83k8G/y9yNeJZwg8ng1evmgd6/B4NvjN9/KsP0YPxtP7HeN3knk8G/y9yA9NfBuP+GzyZVzxg5FP44IfLGfO49ngAZ9N3nt+8/10Qp1X8Xg2+M3373mDZvRqfIEZvRifH+tghsezwU++ny/nOnHi8Wzw9yK/6XfemNBx7PONr/mtGjPfOENoxZj5zujBmPlG9PgzZr6Tb2PmO/kyZr6TT2PmO/kwZr4x83E3Zr6Tt56V7xx8NWa+M3oxZr4zejZmvjN6Mma+M7oZM9/JTOh7sN3Vd3yvG4sx841vheNgrPqO6PozZr4RXW9j5jv5Mma+k09j5jv5MGa+k3dj1TdmvhmrvsFrz8p3Dr4Yq74RPRsz3xk9Gau+Ed2Mme+MHo2Z749rycOw5+mZ0PUktA7lXefxMliZ7/d2oyv/6A51MFb5x1IsP2OVf0SX21jlj+jLWOUPPo1V/uDDWOUP3o1V/uDNWOWPma/GKn/w0nNX/hh8Nlb5I3oyVvkjuhmr/BE9Gqv8EV2NVf5gJvS9w+rKP94Vh58x843vlMNtrPJH9GXMfGf0acx8Jx/GzHfybsx8J2/GzHfyaqzyx8wXY5U/eO5Z+c7BJ2OVP6KbMfOd0aOxyh/R1Zj5zuhizHx//BT90pf/e2z7lf8ag7df5rvdP7ttn4NvY922T8GXsW7bwaexbtsx+GGs23ZE78a6bQdvxrptB6/Gum0HL8a6bcfUZmPdtoOnnrvbdnAz1m07eDTWbTumVo11247oYqzbdkQPxrptj+ibCX0vrrt2D76M1e5jcF7aBqvdI/owVrtH9G6sdg/ejNXuwaux2j14MVa7B8/GaveY+WSsdg9uPXftHoOPxmr3iK7GaveILsZq94gejNXuI5qXtsFq99NX/nmB+Dw9a2R7pzY8e/rSEM18n5ftBmPwaazdIJoH73SDtRsgejfWboDozVi7AXg11m4AXoy1G4BnY+0G4MlYuwFm3oy1G4DHnrvdAINXY+0GiC7G2g0QPRhrN4ho3ukGazeIaN7pBms3qLEbrN1ugOXwvMvgZbCdzPdxWnfYgg9jdYc1eDdWd0D0ZqzugOjVWN0BvBirO4BnY3UH8GSs7gBuxuoOmPlorO4Arj133QGDF2N1B0QPxuoOEc0r32B1h4jmlW+wugOiL2N1BzATuuMOv/wu/hlg451u8JPvp8XzvKXxTjf42/3LpOjVeMbgjF6Mv91/WMSzcfs+uxt8Mn7P9spZFN2MI99VPBqXL3oVV+MBU+Nnl55j9+9/LYPxm+/S/WC80w2+EJ2D8043+MTMyZfxm+/x+dLNwU/jN99lTv72AO0GW92xG+TL4M58b3u/HOLcofHKN5jLIQ4WGq98g7kcMnox5nLI6NmYyyF5MuZyyMGbMZdDRo/GXA7J1ZjLIbkYcznkZw89azkgmle+wVwOybcxlwMG55VvMJdD8mnM5ZCDH8ZcDh9/e4B2AyyH8k6tRTTzvW7WHYbg1ZjLIY4lGm+Eg9UdED0bczlk9GTM5ZDcjNUdMPhozOWQ0dWYyyG5GHM5JA/G6g7x2bwR/ljLAdG8EQ7mcki+jNUdMPhprO4APoy5HHLw3ZjLIZkJXVYr/+gtvOgNVvnHUuRFb7DKH9GTscof0c1Y5Q8ejVX+GLwaq/wRXYxV/uDBWOUfzIveYJV/fDYvej/uyh/Rl7HKH3waq/wx+GGs8gfvxip/DL4Zq/zBTOi8WH3HbsCL3mDmO84dGi96g1XfiG7GzHdGj8bMd3I1Vn1j8GLMfGf0YMx8g3nRG8x8J9/Gqu/4bF70fqx8Z/RpzHwnH8aqbwy+G6u+wZsx852Dr8bMdx4F7Wz3F0+CN34XnJnvabbyj72E98DBKn9EN2OVP6JHY5U/oquxyh9cjFX+GHwwVvlHNO+Bg1X+4NtY5Q++jFX+8dm8B/64K39EH8Yqf/BurPLH4Juxyh+8Gqv8MfhirPIHM6FtsvKPL5q8Bw5W+cdS5D1wsMof0dVY5Y/oYqzyBw/GKv8YnPfAwSr/iOY9cLDKH3wZq/zBp7HKH5999NyVP6J3Y5U/eDNW+WPw1VjlD16MVf4YfDZW+eO7/9GXP06CN37353/TaWOzP+DF4KMxT4LRenhNHMyT4ORirD/gxeCDMU+CEc1r4mCeBCffxjwJTr6MeRKcfBrrD3hjarwmDtYf8IL3nrs/4AVvxvoDXvBqzJPgnNpirD/gRfRszJPgjJ6M9Qe8WA78Lng2LofC3WBkvutou0GcO/AWOVi7QbyY8BY5WLsBogdj7QYRzVvkYO0G4NtYu0EMzlvkYO0GiD6NtRuAD2PtBuDdWLsBPnvrudsNEL0aazcAL8baDTD4bKzdADwZazfA4M1Yu0EcDeTR39cd8mRw53KozHfBXw3U38D/UdV4ixz8doey6FiCt8jB38ngwr9vabxFDp4/nsW38fSxznp4ixzcEJ1T4y1y8Iho8mH8LYdZR0G8RQ4umDmjN+MBPzd57TmWQ+kGX4xvMKNn4wtTI0/G38lgd0rFW+TgAxnjZ4/GO6LzpCiPPL/ukMuhcLMozPdQ+uWAYwleMgdzOeBYgpfMwVwOybcxl0PyZczlkHwaczlgarxkDuZySN6NuRxy8M2YyyGjV2Muh+SlZy2HHHw25nLI6MmYyyG5GXM5JI/GXA752dWYyyFPiq6uO+Ck6P1rcHSHIfP9/WfUrjt8xxIjL5mDuRzi3GHkJXMwl0PyZczlkJz5Hv8PF2RnZw==###5192:XlxV32DM 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c2j9UIyOSyMcy7S86ByR8Rz58WDl9F5zvtNBBX1Pb5KEt7w9qfzcsx5u/gfMjfcL3kR/Gb3lJLcvd7T1d93lqeWE+k/tvFA/5JC4zu1s9zLtetnZrb3AzGHfx7C3c1j/ikYnzDnsfg57KJYCUz0qXXFma93DdqJNDf8HRDaHbQ==###6628:XlxV32DM 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un3Ume1D7sBD7uC3NpWDtv0wcGwsun4vDprb2K3HQcPcGPelazJESYxg0m59H7Ted0o7ne+Oy3Zx07n2pnOlg7Zlu3brjpH3buViQXY837s/ae18n7t1nrt1nrv1fe7WO0u298W4bx8P1PegEfddez9kpSZj1QQpvap5FpRbXU+RRZ+eAUODTseCKEyRGStPsQtPsQtPscs+xS645h1xcqvIXrxZv+qO9ylcw5q6BgfYXTtoWzTXtjyh5+3J0KVnmyA2ckGmS0/eVsKjB4f/QwiChbIw97Ic/B4RSjhprRm+u8LCiJQeWRH8Gj1yRoIiCOJmyJlQWhOEjTxieWfE8k5YuiBz/JHF+MdO9wRZXJxKP2kNoxatGh0fRpcvK3hr69Pr23H+oSVW0T3SaXzIQQYOMnCQgYNszAQpRX9IsV/joM2JH1Lk+WZ1vDLi9pUR1gXkoYrJRYqJmYE8VDE5esrC6yrlsVtvgmz9ysOywcOywcOywbPLBvxMuVid+FB1EsZH7nLroWWUV9kxBh1uGUhACtPV+F4HbQ63bONvsILS4LYW0v8HCLQ5WC3GaJ2DvKhzYMqdeQEm7wswvSIQ6rWiwlJRRLpHxF9khrOjYEHrOqzQ4aTXKAR9GaLe648HrRc+lba9lltOR3wjCH6gHbRd3O/7MI03mkrgrYRwuAkmjy4gal4Irpe5RsZdtoVQPPMM4eR80/0zZNERbyUnRshpH0lF3jovg/o3HAy04ND4S6dwYWwhC8QXNNF21BmFVtH2Z7trBELlxp9kBFmFDxen9I64w21xO0AfiaL1FK3fok3hpFW0HqKNlT68XjeqiwtpzbXiLqAb1e4IKDLRDrr4QRc/uH6rpm006tzxqHNnlvczy/uZ5f28y/t5L3TTv84YMn/cTlpvtRWGY/e4OQfbSxXZCrTBiKja1RNBpkGZ114yyk2KbA68D5V5HJt5Hyrv+1Al8y8K0arFipCvYydeyG5lRZ6BDVx4cuOaEPKFeyKfr3sOWi82C7IUrPBmY8k8HsE/GD4YD1rzdaX12x7r96AsL0jXz5dhV9IF6b/mxEjUkheSv6EtBIeBO1LWJBiN0J7x82f9FlcIMqXjUW+WKEnzzZ03lHrQSEcZq7V9R4p/fBRkrWs/aJtDZELZxq50YeSC0Po9aHNWnbctMvezPF6cvo8X/iQPnGDkgRMMoVWXBk8wvmHwZBB+aSHEFTyPFtrOFeG2Pl3aHqHbjf+FzB5KgbsZSW+QG9IpThaWgq2aImudkbUJ0gv6C2EF5vhDB6MZ4V48xcc/cnGiJ+vHk6+MC/oLWcjT+M/BBuEoMuF0d9DwRm6LttEP4Py8Ha6uxoO21pWhSuPlue8pdLZBre4RnuOfcXDS2Zz0B8NJy7/ThNb/qAxUpZWeaK3/W3U8QNI2uj37DGsrOHVz0w47FNG8K837pnnfJtAvNGDnbjByGDby2Nx90OZ5HKOfyZuYIaNCupBpS+z7SsiDc9KLoUHszx+6grZSYGeF4GXk+u78g4fzmfFzPipLLfDOAsouZVfEH88/z/vX9hxB9pcyOEV5WEgjWuv7n88IiwVZaxRQ5f8++HcdamJ3hQne/w9rbuqJ###6420:XlxV32DM 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W2h7eaOehxuaGu6dcVHmmQY8kTa6imem6R4EKvfsxjFiqDy0MPdsPceh0Qyc1tEWhBB7pR86Gm1R0NWT1liykKYWPuD+7kRZz3gFwSuiM5ykOJXWmpapqkxoIyWWqWmXqbOYozo0RoO2owGL+/VQehaKzDsERkFPG/NsQo2+reShnj98ec8HDT3fJVNgvlZxuz/tPpFz26cm+tS0qxp/0OYVF1JtcW4Hi0YzaPvl+aCtdFjIDhnQF5z+CKMFwa8xrfmQIwuCULklj0N+/uwd+9DPHN+HDf0YLGJn3yGza5F312L0g7a2RN6pxdhbwtRiF5rJMxp4RgPPv5z0yy5EebcuuqqVDG/+cSF1n951hEt92EFL+3EuARXK1+3QTZC2GIpHPau0nDMIndXacIFRH0pvU5D+YWqwMzoGDWL3NlPlEiuXWHfAw00zQZLnK0LzkvcUm6UoivSgMw72+FB6KbJvR3Y/EnonghDJkUxnB/eZXaHWsaYM1a5CKTKte1ihhEe6VIrUCXnPFGUhpb1cFbaDisCDisyDisyDimxhV6B06O2HgfQFNPDM/uH2ovKyN+KH9fqUTsencfSRRVkU4RCkVztNSXIpXfRGkFxLXEibNYUX2vz6S4l2RBaCQ2YIdQlVqiBz5zyL8xE2JMhoFhZO/lklo0Pny5EDGx2NxjblcND27bBDCYOB/xBhF9KFTZgPWqO7IKmY5uhw0jpzlkSeCZcgbb0vpDowp/adtCzszMfy80NHo1HMfT+jpYCW0fKnpekf6TNrZIzUfzetlzMYODZMHBsmhbexfcD1fkWY2kAmmc00FNk/D9htXUjWLQiHYNAWpfVPS/f+30LtB609Sx2dVFteFrGIFYLMaplo+oQIK8gWhmDg140btXlBYm3Ff/6kdcfSoFGzlyO05AY+4fxq5t/PQZu2pEGp3Xw5DmT9PpCd8D3pno1WXZvwPmn99qJNLPwriTy8Nq3f5qHDOp+0b7v9bcZnfViN1ggxrXGv24FObkcI2tiHJFeQJVy0b31YjVZ3NUe7k+6b1kbRdx+0ClUQTPCiOiAn8vy7lefdJn0okVFplRpreznm0ZpnIVOHUkkzk/RIesZjGzbsj7sCdFUDnRh5dF/g1lcHcoZVt+gZ6ASa0w8IY5j8BGjZG/u3XV2gq9tHmCWftAoy4B6IZwY3PgulC+irJxkxJ5PDAiTrQeqE7TD8//47ZjRI/juuf0r4FMa//xdXq3nugND5h47hD11+6fiHvn5o//6h60HXP9z9O7T9oZ/fD+c/9PtLX3/o75e+/9Dtl/477f5L/53a+KX/SNTucINO/g/tf+k/ArfEhXT6Q8dfuvyhfzc7/ZH587vZ6flD/252+v7Qv5ud+h+6/tDZ/aF/9/v/Ax1LC9A=###2528:XlxV32DM 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c68eNqtW0uW5SYM3RI/Gbuyjiyg+n2GPcuoTvYeDBiEkAC/9Kiry1whhBDSFWWNMw6ct1opd7gXOHjDbo094LCbBaXAuocNv3Yv585RYMGH/8sob1UY5cG0qCiFQ1nrCirJrqgkhUdtERVg7uHezodvFt7uDRBG2KCLXdB1syb8FoJurR2eQcoepAUp9lDq339/281sry/1ZczPb/veti/t1OOvf8KP8GX++jv8676eb/tjdRBt7He3wM3uZapn+Ori1JvT7mU3xiBpfP0efzpVOpcYDBQGzXDM6NO65tRBROIR+WciZ4plx2OTUr1VlLAVNyn2gYjPW0Pn1chFz1HJbWSrlvE3rUpw7Oi6ukNys7i2S0tF3E4tOafqLOmJrglnC64cJQfnoWCPgsv2N2VUReHZTGeZHa0NGlyysJPGo++cTSc4djTSUwwUL6IlhPAieZcvqDSqnlk8l+52QD7rGAcEZa8T0Ow3RbluNn3N1nhXj4tnPwTKcDrP89naJWAPcGGdb7Lfp42e4WcX9b3wT8azObyN/nribZR0F+/izj7i/LbDt2vn8VvBOwZvUdTh8b7gOfu5Cd5Gq6X1y3hZf8iz68Z6q2hbVm/E2fOly+L3jLas7f3Ed9K5eKafmdn3yd6bsnbo0CheiZ675dl5vI3am4H2uqz+lBTCBqiI1dFrIXp2/i1BhiQkWix+DXOF31uVvzlWFvwxWZuolw9IJ0jytyTpgaTtnqTwXV4f3JR131bwx2wFf8xW8Adt9blf3Y/0vsQa90Gk1uW8ppPP40HEH+W0AhNrzCRW2RJrrHhLtLoHiaAKNkZ42BksRKwf3DC62E0LUXa0blvnZ1c+jbLRck/xjtmvbFLUH8oNyWc0p1WitaKmrd340TgDNQ26jr88vI5PWZbqsrNPcQeLO2J+9mqy+Ab3EcqzKEsyyNW1zXH82hzJ4tfWNkNxa4MuO15bG2RPHOjYnOD2/F8ZRevNHHWgSTW2mmVrtnL0mciwWOssJ2b5Afvqqg+kM6vhXmTWynCy7qTpwur3FRu2Mjvdo9dn+qVWQLgGvbtiReic9Sqvr2kwDsq8p3aXtrrI4cmnBW2zPB4vx7u+/ltABcvIlawjtSVfkVq5Js3S13Qsd17DQPQVKW8RX2ZDXiPOhjL5XKVLJ5MyHrrZdYN2XeYEUt1RZ4MldmXkYTCgN8vd3zE5fQbQ2x+yHRsdO5qT6li9FtO9so47e+Pobq+BXZslnjXTUbRI4/16da6GW6S3296wOIDuqXSTc6ydzraPlbPbcyQFRHwr+TwTHz/xal0nchP0qOoPBdWsf3muxh94lCW+N+Y6EwrS7Yp2aAW1oVuh1dDc1bC5W3gNXR5lbtgQupOoipRP1gUzvrhjmXtGrse53GpBJxhnKJ3fKpT71eaQKVL4k6hIXoBuL3RGjMiEJ85YCyywXrZIlTOYh5VOuUm2ibXUJdjH6Fsdn4R7LfVAbK1I0L1nSLZjbvHv0OVYx4T3h6Gk9f4CsFlZzAHROe3uzA9yuRc6sbo0BN9f6gtyP9D4x5P0A7V1Zz9QNd3A3jP5fMyRvVvHqRGTkPj8hSoAxNtXHA++nuOAsl3cMCWj9ChuqFzLjGObK6NWq6hVi9mPOK9xd2EFrwr3Yz7i3FzhftzlkV4Fj7SXRz71m3jkQ/0Eod8dIQ4lLKTm7Wqp6EmCXNNIZnzcopMSjbimt6/YRJu+Ixg7ytWUqKNqgvSq1xJbbvsaRgfNvhTY+FaIWiXZ8kbpdqN+kY365Ucb5T/mMhoJYp2Nt8awvWJPtibe/WdEHnRT092fRtV7ikRWcVvkeJ5Ypvvb4su22LItBm1LsBTZlT3Ec9ftysU9XN3SVaZF6lRr8UmLGWac7Zpllsww3dwVe0GxV403Ntjrke21747Ya/tlfkIKfJDnMH4UJWJYg5XYkEetJMjYbbsySEzGcZPUI5RuI4qA0iSaqEJmO3F8/V6o8sGzCIKbPIuwwnMhT57daJLG85e4L6N4J6OXuGlis1mOzReyWpOneICgfGnxekIWeJGqMfUANoStJl5CUdC8XzPk/Zr0xMc2vmXIHSehKrlKKWU/saMqJLYndkxet0nj0XfOzya4SSGkWa/GjQVUkg6uCosK+9U9uHzZkvKXL5vbgOnQOfjs+YuaNkVdaYr2zT2DCdMbDzge3Snm0ao0ReXHI/r245O2MWr+l+72Y8ubifajhzc4snAN4dIigV18uLIJ2GJz0lJBuHwWVdNMVdJoSlchNBsr83fTSDfiaKmEr1LEJCMlEqCnSZITU0I5d1ioECT04MUxOvFN+2VGsrnaPuyanjJx61AchbbsHdCizcki1PqIfgK2mTuj1p38RnzQOhNzKumNePAncFusH68zuBcf7Mbk+z5KpY1rfpQwwjRv2s2HUgbatNKbwkiXvGXUfuTe2eMiTDMZR/LflZt5H6OX8wHbZJnzvEPOi2Z0D4lMizQjxnlKMg/GcpItkTHSzg5kLGWyVU4uxlwoxtzFKTy+oaMjTU9HXqW5RAjskRqeNeWOMqpqN2qfe0Jb84W9ZnOHSiUsFaq3C136GI1fLbNz0Sc9W2z3Muofd3jBD7yIo3VQlXNzX5mKgbf2RTjN7+u9eCM03ni8qDdq9cMyA9fetj6XYoUX96N+52KSF/2PGc3uox48gx75ki2+xPniMashmqeJ/MoHz2WIDcWT9PHDqIN97DFruHj2RmDa/9mTtjau7Z0nbT8yx0Tr5Hxa5MywfudOpboXEUoTRGKRHw2rdVGIemEvjMiLsdz7hcF5Bduk2SsH0jZOB7zEyN7teTAfnSJTTtFnNwLHwHvkVfrpKQH/SgR8XSPEzGSX6dnhnXehzeTO66NEM2+sLOfeYdi5R5rP7l2kv9TQKrHKjNawduvmPdpxl+R90Abr4/snOA7l4yGWGHspxc3UXAcxF8LzowekEjYUJZW40IMd407owZs6Cj21GOexUsm/soEC7ZE372haXOqbhm31SmGbJ9bgf4RCM+lVm2H7Eb+7J+3HmDLBpJGYLsQXKm6vPhcM3kzWPpfUHeNRmnTH5ISwjr+XeMKo5GGTJcumGzD5qytbO2goBHwjL9K7oi2m4312mL7ZP/FCjdJbj5/pA9NRu3Qf3osOP3mgT8DFvhNy4I7BmzXyGuy0PvoP7e5qbw==###2928:XlxV32DM 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d10eNqtW0ua4zgIvpLesqvPMQeoxMmyd7Oqr+8+siQjhEB2PL2Yr2sS0AMQjx/iolVKudW9vPNvv1hrtV9tsEv69OneLqbvrH+7t/eJwubPvTfWO+O8G7lN5o5KeZvId5qXczuVt4nLTLk8UAFX+uspctmDq1Jt6VtXqbZ03iWd21ht109vWM/+4Q27Xe1O8emuPoq76rZrpuLvarI0bNrBpP+2cedEpY9/C985/UGX7rt6l7T/Zm+gbfjoxgd9O/165ewnp1jIGULij3a/8ytrq8ht//+kR6+GMzf69n3+K5+wp06Wlah9WX2wbmyBluVLq/mYzoxPdc4XMl1IenntVPvN0912W3QX+cNH/IdGnoz9H5oYLf+Z/95XTAvv0kP7+/Yp3c+/8+3yt9bZ9Lltkh9XUn9pJf/XzuRvn4nKGSwRybm3xPRG0sfjC96VWV+NoKNQNWTzefqdXfarcde9wG3yHfPunYUcbzYeVirwO9jfZQuhN3d5fzXht8BvZj5D4F/h9v4Gt4Xb99LbRk8tSM9Xfs3entP7J9K3LZay/CUebiA97P2a5opfKrHNEL/gBq+5ZD6T+Qz4MwPrFL9Idytv2Nao71tMq6tkrrTjS+AMORdJFyZZBp+bJLmB17V9LOhOqVkuGu81yRI06+GPXMJf4hqiT++fsyTiEPEVu4aCCBb51Yb8pPFxscF36034MqW0As/3ytkbSAitQ+kDyj9b3vVCOaK+vMtrogfwQG7fyJRoRjRhh1dhmVVCyWrKKuW9citOeF8ot9VkrZGjyadliEQ+f/78tiEd4Et9uZ/f9h3C17cxv/5Nf/kv8+uf9K/70m79SWas7Xf3GCwIhku+VjYRotwGqJoKi2k5kb59z5nyCd9pmmMGN9zddKc6TTxXcQ0zccWmuuI+Bdgqv2kOUghFAVKtQGTQeLErH8uUwMgu7DKqjgs7ZTvV7FGe9K68rDKzh4k1UXdeTTck031U09VOvYjt+sfjJz3HlbVdzUikOBz+dLr7nnNs8q0Y6kRjBy04tsiM2VKfbil2kiT5BFlotihdgQqFm1QuzrkCULWAiIt1fVKsj65J5OgoeEd4ysvS4zcVxaJllhRFeIljSqyrTv3tl6xOU9pZSoxsSuQHT8V6s3jGfxTYTEJtcjITJylxKRQ3WIlKX53wW9hdKifi1AsucHfPlDPnsncge0veMpabx4ntIL2RS9fXiNLoLvkzLJcT4RID6/WJMa9rdxQZF4AbehLQd02S+NjRwQsp0noXkkd4ezOsMtBgMCavpc6oBIrjzsu1vc73oadBq0eSRCqSRPJcjkjR9AkZigfUEixvCZlD13Vka3KQe0RSIs3i+BUbLOvxMCW89JyESsCWvWxvXoxD2KfG/SVIb3PIcHTjQ1mogXV4eYrZw0mxamoJ4sg5FcT25Y4O0EkVKT1brIrEWseIhfl8s9cMMWO5zOxV1xvaeq5qa0D5QrC2YcrkCMBBZ6V5Jd5KZ7YttyZQHJnZ5gAhN334IbeaZ0kkg6v8HD2OUti+9GDNjvBpFGuughoHlyEAyhk8sXR3avALLS0jKi3Nt/UkP9+2n7TMJ4WlZgqX9UaaZAH7Mwy2fZ4mGcDONJMm0qLRXgi9Sko4OgdqBtRnZZ2MApU048Yu1HxUgGm0HlXx0qEHlqIHUe3oge2UbLOHORpCh/0YsTpZWEBDj0caLPvg6gUhAz4H1zq2iSYxwQ0RSIJLPRPvmhw0ZIaSJDSqXjowMd/xtE6rVFKT6V7O7CFn9rfqLQ8Vg2WxhIVpBvPx8sSImdbzCdbjL+TM8BDW9BAs+DpDsQitwk9GIvqqRtcY5m82Njv+SRPbCzlCQMiU78BUHKOUFK0rVctkvJgTmhoJ1QjWT5r7WCe0uV+wQC3St+859O+E7wRduBN0unZTtZpvbDXrshKreaw/6Ql8DzBECdvhdnzpVhDpMV5sWP5IcGnTxxk2SbSkNLgyGXJwBcYZjDAmD9qEq/BpVc0jqcZX1Wya5i7axj2yqS6ynYnVDD6XXtMAvydiLdhjFOnb9xw2yfNFCZtkGkx2aG2d39WfGlBgqXB8iYxCiflf8NNmtooY2yLEtnCDX7cEsEPDNqoD0Sw1NJgNmOUTmeVLb9QsQzZLQ8xSwVaxd6ITEGCF69FCV55PWhs8SqaTvLjPcTqaoMxhFWwEM3BKNp9ZZx5As1uKj6D2e2Y3g4DxvbeLxh8+erjhBDjB8otD4KZS/GhfDmCoZr8hs3+qwezNJnvjSPqM82II+0ZSenUBSuRiqLBQZD/4mqARXHZ98PoP/eC4u5/48JeIbVw9+3rjEcxGc849p4EuzMkTulbVVBN84VxtCwuxwUXvzcZvdorJw3s1F3I1rqPvJ7maJeCaZvkjUPFq4hpeiFcUtQZRN1G9k6i+j8bsstKhAhdzY1YRWEAdE3g0x5tEHFMnbBxQ8XHAsc2NIhVeqp7AEkaUKp5DmbsJpMsOfDTiHGrTPTOHihK8Ez6WmpbhI4BfnkE4YMsJ4A+zguMk1mSG2nbl57W85IBU9clIwzjVxk9wzbOTArocer6anRxcCwGSRvDdXT3jdG5esVZFd1M3XsALwQCGha8MUOHGlhdfgDoGUoZ22G5pSmg7u0njV0O+xs29o3uKibaHRDuI/G4SLgyEC2kS1E/b5vz5n4O9f7b/c/Q5l0A4vu3vPxwaeI62yXIr4A4z3ZUYcyF6esnKBx/DNdFHzkVqvyYODWDsLDqVcYJrftjN+S/6f8x35fcOB/2R8F2DywvX0UsJtcknAfm9JkbJlzizsC1hT5qRejp4cUQvB+dB056TPEkB+L+fJVy9zdQOiZcp+dGmetjvQfKj99ZjxQOQdRMrttMCbJmG3SPr9kzY5fF4jEwvEJwkcaJh/15lk46IqcPAkRuvnkwMBPZnZvOu58Hlxg5rnxAzTgxzskk0uMBmIro3EZpCL6avNrYBEMzx7OJvtoxQzorgXoX3Xud4baWSM5JP0douXlRhmV5YFKx9xB5G73sv4faEFF7h/8xoBGYmpOC5WhRr+57De0/4Trob9g6Ijmf3qlosBm3CY4DQH+No+d4aXpCnRiNWYg1YeAypb+djQwF46IAStuqeJzYepCwqvIXZR2pK+um9ApGFUEMMDqftuV1sY3phDf3xqOdFbjCWEZ4BKQu8C0BD9o60kHm6zmusmo6nmDKewh3P3m69If7JqIUUJwtYvtRCm0xDiIZbEK/KRUy3+BEj0rfvOc9xwsdSz39xgda4NmNdlelxX8R+D4Mo6ziIAqrofq3WhGIFxbVvuUtOuVjaHvZsvMvUVMIUaVraC+yHGwl6V341+h9Sl31G###3200:XlxV32DM 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bf8eNqlW0m62zYMvpI4idLLOXqAxtZbZtdVvty9NCmBIAhApLJpHZs/B8zT84d3Prh1Wfzu3yGELXx764wL+Zsj+PAdNmfToj39d1+W4IJ11r/Tr94tHW5jcC6vCy3u3Mf64OO5T0W567SEcoCysEtGpbWOIE3C5S/TN3V3c/M6QIXoD5e+9Md5Wr/LhfEZYz6YBA31huceBWMbTEQYi8859+AwNmM8oZ8lLyq0oi/y8IKCMi39yEkOMKs36du0r/8OnzteEhLLL4QSBJdXSjtwqHKjSvO6S129Zynymbovcn9MBSuhOh69BCqYTPGYJeRQzqIytCXUlilTULx++CybLSqect5yF53NyHkE3IGox/D3z59fbvXf76/ly/3+5b7X9cu+j/jjv/QxfNkf/6T/+699/52Y8W9i0ytBX/6FyPfZNP3bf8TW+T34dMR3WvOdxGH3Ln1OLE7XckT1EZpfmxWFNwDbhT3X5OcBGY4QBebFjHOw5sR99iCMKDu17wU0emePeafP+W4naY9E2nCS9hV/Esoa//N3khWTiEtJswqkKbYxgj1Y+Ceeawrnl9OmgMTAk3scv0624QO3TR94Rhq3ZHSAVXDf9syOGejUj/CFe/FbZm8t+p+93ln1dRbd+s28lxMiUKds++YEsHDmI4BepJhycr7vO39eQXy/sfi6nYrvT/cR39CIb9Uyzsw70VFUHP69fPLCyvord5aKYtdibY6SgiCzX2/o1Btq1JihnObOKloSaXpzQbymVGrWRsZzfysKuBXRHtA+q+7c2RYE3LOS8fk1OfewtHTPfsV3jlqQjrJDXs/sJUqkRF3YLatjUt6kjvZfcCeW6qN7HR+F3FiPEiBervFA+yjPuNkA8Wgbw2ouNsCainE3btnDGj6G9cRcmBxje8gdQhPFOiEuT8YKoVwT+x7IT/Gouqqimjsy3i0WoWUYbGC/oMSaWwlq8iqUeajx34V0sLL6VRwecWHVR7EC4p1Oz+pHKTU5w11XzxvucMbpTRSM3sI5kxXWoLcg2eVytiyHiGaGRDAcxsEa+n7Hr55yCwR16xY2Br1C5om0GHGVy/UqxavcFYO08qvRr5zxU1HsWuw4xl8l5eS2Ytqs6OQ3W2tgZWIBDhohGycBDHld73yxHPHO64rt2rjy1Uku73Y3cLth2u3aLGPvh27X5Dy0oK2A9orLN3BzPmRZNTRE030svmVsUGjmIZ3zLHp78GqMXqZfPXZ2zYssw6/9hmYm+6u3mncF5eYeQjQn5D/ZIz7it8mVq6i8/Q7vsh/X+LbC662AD8r7LfDdiOdHlfoOzvcM/UrMs4v4S89dQ/0XjWKm9KVFW+XuBk5fmbtvmXZ2mvYY7xWtgdSFebvNkpP1QdQaC/ou4zdF8gJIfuhub7NvsArnHHDeMTbaMhb+ExBaJOsZ6yWspjMr3LyXuTuJ130LRHzCvZdLYnwQrMVKbn7/6lFbI8mrZmtGaV7Qm8Ix/uWtndF88gp2Jgh2guLHKedvTt+Bbhw63tjYIifvrsrV4pdHMmMz16mejqPtpJbjrhScfJ1XCiTkbBZBM45mB5zXAW0Gz8AImtVJZwD3YYUhZxgJ0VRNDdkBI0A7ht9REah431GCImKx5YPvqAhaJ5HeARZq+IyKwGVOfv+aL49RieTXTFbN06rmLWOvsGov8I5epSISlO6ZV3ByJYXuKPqDor+35U3z6Ba9h6FdwIV0ju9ej3qHtacDvZlD7esM1qBQP4nH0+rcXZVtubqkfS1FrNkM3bXJ1Tk6CXWSTJvY8Wdndqhd5ihIeBRQB9urjn95S0cqJyhzVXr+jqnmriUSy9zGlVmp518wO+kmWtKB5CXm2nkOdcP7vB+Hh6z2tAI8TQzDizMXJpwLygRAteBzkxAdcnAWoomDSYWcm4a41nuBA/q7dkFCJL7h/CA0NFQnUFA1rrsjqrZyFfEVarLty6wqWwI9lOo7jsFfYtfEdtR3KFcLbQ9EtF0KHRV6xKai2UwMiVNGGuWjSEO53nr/JgerwHcoFfU2+wgi3Xe2G7QzlXhaH+nPWogFeHzDLv7FKKh/NNFlb6NWJoIvdf6A5NASD2yZjhXuTIzZNk9kd0wrcVXtNfGyglvBLtVpFYf7W0xUU7gd+7p8Y+GWURlROgCo7nXjW/j+pJ3kgEhLlQNoRhHJccl1125mR9PMKM69JP6RjiuaKxO7auVuHqLeQKbRgoJyZ7a9IrSsW3xXl1YIx3JjObZVuuKKNnavUWytPaeElikPcqGu24961DqEQFDnv2U7cU4UpBuFZgJXRvU8LWieClBxbfSun1oIw1WVoFDPktOkGYnAZMJUj/qMbmVQodfWG7vnUYwwqrViV1vtr9aRGM3mUY1aUSeRSIVo8VaiT1hqX8qktPurTK++bybTk6nCZXqx5iSKv/cdNa7cLpLJdqdQEGd2Y9E+rm7LcbtUiamxNLZNeoQQpYqRwDHH7uEmeYZxoY4Li1y7JrwtF2+Jc09K1qt6e6iV42oboUw/4RHYXXDFVtxR8IGWUMeQvfoooM5CjUQBTf+N/M1B34XrcXEq1lZ8gBLXox5dR4u+UzfmqQhFzjE+04zxuYWO8Vm/fMb4klI3Y3wXs7gLHjdCFtCqsRT9+jObjYRHesnoQsWb8hRNBiIYsSi0Qgy/XipZk4K0gmRXy06u+fMjYlA000lDjNY9HjcmYmOCVL0MscA7+YKa73bgmg+0rDkyQuj6Jk03e9yHhYtQkNAGD5d+mKsprS/CqJSZHvsZQ5vaXhTRTwd37se02vnmuUGr+8nsVRmekMZ+KnpTbu6goWwfoKXBizqAoKFX4JcR/1zDT4/lvakOingDPJNGGLRBMYlrb/rHapPjSi0+PhwNRKGXgA8wsmMeDBzpcnPhn45F3uP5Yas3tdsPRzjizaiXgTEKK56v2ao73t+NW2lDIJevWx8OyjVRxINBPeSjHw0K3g/U3ltq9xcDtbrNmB3HHR07iox/msGu04NesoUfxe6oIcRTy4OcyUNe4aF3uSzc+nBILNT2wxSvNRszNyrlNbr/D42KYRs=###3252:XlxV32DM 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bfceNqlW8uW5CYM/SXzENg935EP6FRXL2eXVZ/591DmJYQk45pFTjopLgIhJHEl+y/4ht0ZZ+Fw0cVtA+cP8B7g2x/+CwD29JdNI9y2pf9+/e3TX84/vE3/PAoeEh6cEfGu4Z0DAe+dVfBpba/RRH5dfzzxTsHbJt8x+D3hnTsGvAMPtsjcinTnYUKnX0/p76JfurduV3Tvm+5X8Vi6qTv3s+aTZk70IUq3LhS8OaUf/pnmJpKrvFMWlc0iwEH6Lw/+6T1GTYim2zZiIzI2EZFmTzK+0q+jjBGBTn9RxmAv5z6uZeQbFpZ1hRFPD03GJuoqr8kv76KNhwiOPYt5fDjv0doO+vi19Yc0fp9+l+fv458Q2/rl+d3po9yyftr4dDMeaf6XhDjMT8/YVS+U7te3j+k3l+b9TnfJvzR8/jLfbOoL+yyvW+fz+OF+arP31fjqUxPGDfoZPeM7u8gzdo1gPBC5/dxnj762Xk1a8/zTbZ/9P8aFjiOeKM+TpRl2jY7ZW55FRkG21NOS+DUerKyj3Z+ujyeyR8Oe3n7eCvsyVIQCUYsrZ57nk8/8jP/DWudTcMuawaule9xOzxXKzYQuLXkyK+4xxwVT/B1G5Vk0faqaKfNx+ONcKZxxIop6sexa+R3meThZsfmrqFjZPvloQKfbrKXMwcnZq4WdY9DaVAsR7bLMIkkKxRoei7acdxRKVAB0Q59IzramhTKHhOGjG9a2Pz38HNVts3jhprCounNY9AXbucYo6A+Ue9J3RmVpGjzaGKx1WZK+Kx0Ft6wi7yoW+4uLlq7KUi0jtvthsXcSI0s8MUcbg+9UFPYUSf4zWrqwo57TEMz82qMo3zKhrjsnrs7Ue0i9xJRNjRkdvrsrPsLVtaXfHmKWY2h0lXZUZuFWlyXZNka68aPubEUNLx5dkiV7apLKHPLq3C19694fREvdL/3XwdyIo8hZzQjFe1Rm4XZ0tDdQ8Cb93zTvK1YnZEo1ii+WrYKgL+aZUMOdMsMsCxmBEtlNibnUAsxFtFk7K5qV5cjm3jgtHDWQNxJPa01SkvPnz28Xgvn62D7g57f7DuHjGf799V/6Cz7sr3/Sv/2H8fCTVGXc56A6cyrcMs9EPVDnFMzNLllx490UZsxDcf0Vox3SPj0VO1IivfZGmgFDem1VMxL1U9CGpezMBTpr9IX3bDrjzj1ySTUwYY+uvc9wEmNgLh/IwJ6vbWfFp8v02ShaE7WKYrJPZLIP90lM9vn8SRf0k7MG9aloyeVbQx0MRnrYGDWNWJNXKLVbNpt3lulG94bFH83i76MrlqOokbYW7a3bwDe2gfigbmv7/HHHYARHe/3NboMyswxKWs6lEwpMzipnD1idD4VfCm8cY2jHOKMP9DZeYazvoaVKwYPqeN0Mbp/suYZsPHZLxmM/W9Az1HqSn31FvZgC6SdDH23keCxJPC1L3m0k9bQk8RBRzCicbgWVNoIubfD/liWN3OiDk4TnOTInXZuI6b9zqR2Ps/zoNMbNmQSfxNInjfKww+ny+EhLUQ82Esn66P7r+RfZmYpix+JYziVuQEjXplOWxoHhV073KoodKxO82MUMljVQhGImpibZtOCUS2iREG+W5ARWLIXhXNFeRHp7WqQtlMQqLVxRcX4KDI6IX2MkYWFeo2U14ok0naKpKJgpNSXjrmsMDHWiEgDltA+GOMAFALlUSC3/AeH1OzM+F65ev1e/CoK+XRsN6BFvx7NFXmdJ46KfqbqDi7eRE/y9F0lxS0h1rlxQy+0jrSaTItqJjdYIb6w2KiWmVvQZCqWbGmv8m7HG34o1c9FopJfX4k1FOSbiqLQgeg3B6B/UbMHUt9tQPL/KTPqLj2QmRctBHN9/507hAseMjmyUO/p7GBF9+q5kjJxR5FsQi0cJLcLJ8/couHI+R+M96Onk/CLyo9GvXEYRBaKNGXtmcnGpRIYzq5VCT0bt2dLH+3HxOApsxJUjhZwhjbvyEwHOE2Jy3Myr88zqCIlGML6VGwATzDjOlIyaw3HjuAh4DCU8e0Pf5lYBJVT6kSmgWKXcUDRHqHlZ2741uiE5zTdnvxB5BPqV8ywcSowF7A3x6kolGnfcHyDUQ+S37uhEfsk59R2HVxkmBhA353DP+NC4HDM94v1ls+LWKAAJrbCmrV3PvEF9+NYsmLPqGR0UdGy75rG7ytfaxteaSd/Nn93c9Rpab8/cq89+Gx2VBkdd48clX1ltxQt0UVAsTW+rPa4Y9sbP2zfYfV9eJbWxjsNDiQkcfmvSg8DPR+XMpJ2vNiRLDcVftHlS3D00a+fw/qIhOWfe2d6NgIfbZ/eY+TRBe6FpT8b7v2rn9sqdyVH+S/AV6KUmag+a9rzQjq15aN/8u2fw6F37lsfAnIK0/6Pt377R0q1XOTxz81bbyQPjaVebwa8ihH5qnJe+XjWuJka1JKB/AGD7m/L2vmtz2t+gNU9pezMvkxHw+HXNOcZT3v34ICprt23tqzdNls5zT6uN/TJbpTVkn7pZbuzvCKlpnUPANOJKRkZgJkFvKjc3PhxwqNGV/zjBiJzHnY8TMoLbw8zk7zca77snoR0RvI6az7vx4UDgeGZh/f7mCffxUuVimEeK3cXjrLb/8xztQV7aM6e3szjaqGvHeRgOeolnxS3CDL+gSB8aSS3DsgNq3u+c1Zw1UEYZ1x8xZ/cUmcieGUeFh+Y4Vk9bPKseL3XryGmuv8u3m3W3nn3wbLdZ5QtERj0i/T2r1pc1sQ2aAKIJUD9KkawaRHkif6Uy48e5w52xK72OkzUDt6w/DuzLyPjrd8229vDO3F01XosW3Opb0idscp+Qnyo2qO2a4Xb1Zm17q1m7RvzQ7vxaO7m8Qq16uBHUajs5Hw31Gt1GajOSTzRMdSYWVjTe+HzLkBrSncpTvNmiWt/nvUFppb6vVPIueG+cs2GtzJVwJ/nt4cSvOlyytwrtDo99MVIUdGreIVeuJuRyrUzWCl+T6xnCU2l/muuMS5mFWk/Y0ac6a3Xj/HmpuVUdCOgzDvI5m1iFiKTbZ7VCsrcqu/wpgmVQ/ROBr/8BQYJiGA==###2680:XlxV32DM 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ba4eNq1W12S9KYO3ZIBAfZkHVnApMf9+L3laSp7DwYMAiR+umfqVupO0jpICCHEEYYDlH7CU2sNWqlt20BrqSRI0GCVcP9+wOl+e+pdOVF9KKMgSX25X8FLGRBwKs3K59/9X06nvLTCCcopHuBI6S9n8379otz/Kjwk/AOeYKGZpbbOfh1nuRVopY4bHaUuveClzoxy452V3hu5J8mAlNdI8Li96mRVo9N65JEks048U9HMVGVbL3viitS4oE85b0j3z1frJScltFtHreDQ4Fb3yXlu1c/eKsrPyHZqlZOXpD70dv3JYPPv/q8wXzTbR+OpPMcS4fzi7N8JrCawbQReePA2lZ7Gq0vjRcJLZSZtb9fX29/s2YBNO89LUrtq43AxInNk5XHoWDhRbhjH/kQUxRGLfffff3+UOWH/2D7U9x/1NOZDOMRf/7o/9Yf862/3//BxPr/Vrj6rBZFR5RFDH4aBLyq3FiNw8i5T5SQjSTwkqZwqlLZpy9AolaSykxVK2zRKJKmki9xcSJ7aXChkBjhSGge9aLZKYSuzVURcNXVtlRgGBwoD+VTPKgw+xbfS4zAIaiaC4VgMhuuXM+8CcoFCfjzRXpM+8vlgUB6VpfyyonMJ5ydosgrCs1kNYlYRyNWfztWft6uNqHecBft9BbbzdrbVKBcQzg86WFudcHiOZW7IOJXkch46nXNHOEhyCIe2CoczSQ7ZyerTSqQI0M7YYjtfFQu5gjrmWJOk8sbUzkccytyoKFUmgT5KUAmnY+GF0mpPUkjXwEId0pSXWtG1vaAL/Dm1qgtLlbro+vdGbUkq6BJxlB5KxdNf46q50LWRKFvp2nyO2V2M7kTkevn4e+0BQcpD5YG+VTdKElaFqkBw8uh3qvq49F4Z6oh1mXQyX8UYoRaM/x2uhZY+a7sjQT+9Rf43N6pxoxh4Ooxxv18aXGXwxvjbxPjSnR7XX4+Bniu36F+dSV/DT89l+/W5/Ni6FONrP7593/7FUVdtxhlBpvM+jhhudXh0FmHR/sPo/viiGl8sjS+Ys3V+BgUG3yM686D19Gcyp4fD2BfmY4m6ZDQf+8J8enr4XL0yG5Td25zenZNaXqE5XXyUUkhTRW8H6WW5MWhc8H2u6/I4dfUYYi1Uj6j+R3VFzf3sGVVWPnEUGqUS6qFNYPzY6ipI7/GGZGLVcdUXW3UX0bdcsXu4auWW39sbz4AtuJE22o1qsO4NSyUUfUODNB7a98R9KYzhs/rEPRE6mam6BTVZp8VBvEeWEXV2/WV8bF3Y29e6wHLRlXEKrfg5iJQkX8RKvfq3rPR1yh2FGdNKbmHlhpI5Urdsdby3/uPurTrfW211b31Gpmg+aGTDaLBB54nksqTG5J0cBtssNSEbTmZiDoR1q3OgaEuM5WhLmWhL9QJe3tS1D6RltLf568bHMHm4MNnvMNHnZxUm8hDfF91LRopi08tNH9CXsTupmSSVk5ru8Ho2oXTF64VjxrLy+XfqOKNxliPqkybE0hHMnvSj8CQ2eMseDYk+H02JxO/Eg3ormjoUfEIrhtVcRz9q/3OcaEIDuXtVxQ+LqbzVjeZmPNbbgaudOCzpzAMV8VfbrtZtLwjHeifKSmveiW2s1hTujuhGGveStSy1hLN710eM3prkFAPfqGqOWdtZRkPMpV/lkQtVLhW7/nZzVGQu1US3Qg8odI+KUrmEpkpuLL9S2jc4Uro+4ejztO7YhF6LYVc4/051Vwa4oZ3HSxkXUsYFNuvpXzv/VWrddOoeojNWz2DloqCJEQe120Tuy/XHWbZX9mrPmP15tbLKShXihVOkhwd5Z2rUEqhbwxZdOyWuOopGAoWKTYsaxVY4EJ9GqKrV0UfdbZVtEaV8I8FSKHZeN0pS83I5sYeCQO57KUSjD3RB0/0V3Vo8eAPSw5SiJUBciYK8jFXV6Kqv/W6VVFtpcMW8kfVlvn+pDT7wqOKBQfCBKlAtxSrfJ9EXR32HbIZ4mdY/TDfPjPs+SS5Cy+vHvd0f931/21/x9u+Q+/fY8+QrQsRWXM75NOlK6eiTrjM6KMpUhNbqUpvixlBVFQyaFrW+mbbFrD7KI2tNjBKzRpTT+mZWbVYf5Ru50NJAiJi3812it2ZyoZ0xo4OOXFWdLv0G/11HqeoBp6hOMkmgwrPP+5w9O/WTTHevPqUOiN1RwwcAY6ZPppFydTGguKdZRzmKwF7jn0PGN279JwaAnwgV1dRWvaXbGNyOV6Ko2mhErrh4MlpGgltOSm7xGe5Ici+quTZqiNzGPqOGDlJXrEAeCSM2jLied6O16j0jt8iPunpiHcaZ83/wkS5XLN6jnvgepU9T3aPUvn+r6+b1yTAcvYd8Ix7XvsTjWpbHNX0+dpq76PK4DSfAt9DqhjJG7VNMU/85XU9XmDHf5ci/U3Mc4AYvVmW/Lcj2GUR6HP4KLw2J3+3ph0l2eNX6Pb22fYXXHtluf6DDw2u3yXZJ2G4IdipFQX6QD/VjX1Mxh0WV1ewag3jJk/hkRnZYb77fxjOznbxVjcd6883H0HMzsCwTTvCVnnWAhoPnvRC4UmDYT5i2OI9Dc/26/NRh2j7ek71zQudYqs5njT6zobXq6sMM4owOJ6feypOzfuAtT3t1QHV1chr0LKOMc12xOdzJpxZ7PJZ4Ss5XHcXDkWXvUbrG0Qy9r0MGrNqs5t7+43XjGUs+utFKttG9revtfqVS9yp/Uq/txEXuS9vqo8b6HBxkzBe+IppZK2yFJk8XO326mKpOas+u1RO63/c2BJo7Y9driy3VFvKFyoauDmZrC53mLV6q6d6zPez6UFPKF95aFFVdzPvC5f0j531V5/2vf6i8jy19sC8MOt39hY8iSr9SHyUKtqpYYSEaHCk91z1V093L1Qh87/WTSBHY693Cy9aP8kb67Pil+O9/cDvKO/lV3THIj8XNsDnlDVm98O+v6Ld0YvA5+7gnTZ1wPLOHzqr/AXi7ZTA=###3220:XlxV32DM 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c78eNrFW1mSJCcMvRI7ZPscPkB1VtXn/PmrY+5ukkxACAnImgg7HI7u6dJjEdqlssa+bdBGG7vpTSshrLdaK2PNyxgthDCbeVprg30bpbV26S8vm3E24fSBM6+Ie8ZPE+5a51jJX+tUlMuo+Defd4s7vM4TpJVopE9IeSDNXs6pykonShGooLf41928jY+f6bjbO97LxFP6slpB//79S7vXLr7El/n5pd/OfUm973/9E3+1X+qvv+NP8yWN+NEy/vcAu6nEy6ADs5s8Tt/csT1t5HI+7UVV7+iMjH8xHD34PP12vNmxb8THQ6W/63gmFf9/9meN1JEikm02Pkb8F3v6+7e1qtxWkqcPheqUoINKR5p4ViQDANFQXL8nORVjDlF8Ge61TfbKXN27F6zcxJjjt7g7iw5r6EtSZZRUXSXVI0l9PH+0i2LKHvRcOv88VX50sZZuKjSeZStLbzUQGl5FMJWymxXITMH96ufpt8RQt/iELeJ5KMxx++sJVPMEFj9BMD/REtFPcFq05w2WKlKPznVY+lssrVYHegCzLO896pTeal11wzD3xgwLPMPOt/xzhvEyeNLbyrCI0gPzQFNCFsiPGCcL42RhnGnckrXYLWl5uCWB3NJE566Ht6TjzWhTqEqAAI17duEMkqaEt1X37MTBdzZYUFdQIwpVDWpeET5GyUIFQhqwF6t+TSAk0Q1l44T3nreMFGTLzEvRuTeNP3dN2qLt3KpbObfoRRYtUGL1LTsltpQSn3GjSxHgcayFDbuY7lxB0aKRVFBe0eQ+UOEz8nVXBLvD50aRr+iiJ4ilGX+ijhtCljmovuZ7w+q720N9TaO+kGMWKCC26pLkkiap6jlPh3bwTSSc1FvC2fzXuFKk1MenIqEvWvKt3EFZz3H+PE6doi99cAntMaCkX/dywTdxKCyAJ+CobfxpGY+pwIvo8iJqgrIIdcqbWnA2PiFNoazmzLK5lorvBveDqN0cPAhIYkShPz53Rd5o+dJIKovZG0qlXpTKPtZoJJrUuRqcScLYNXsz+Kyz5qC6dNa3OvvAOvvYD53VSGdb7jQvNshxTUW1OfXgnQ2SK86OyUSBNd3+B5pu/3dNtyNNn/iJvAKiZPVIJ21N9OnzHHTQVkFfq2+FCtQ1WFTUs+IDMWpsS0aS2UrL9oEGyuLXFRHuzDVQluDegGwhRA10lwYaYbACPv2hgA4poAHGjH52DR5TkoooC1V1ubCggVmrCsoPWGu6x9QgEKlqX3Nalh58XjJUUN6Y4Ehq+BjhoycM5QnlRyLkiwjJxf2Z7LwL2hR41ZVoe8Tzvo5w50Uda/h5I9WWDdmA9Aw6FyJ5t+RGeqnwd8/eOK+q1hvIH7YHTh+2759oFh9d2fI0l1lG5MI9cdG0rsBRv1gdV9BcIx3nM0t9hVaViiuy9xIPsGyqIUuqUbn7ANwNr9AVCkyuX48ZvJIS2lsMtsizYVbJhlW2YfA+QdlCBVDWs6WNMwsIhQqi1BB1uowXiHxXRMAXj63QvWhHlFEGdT0k2osTG39whDSUPhs6G8gdbTFVvjF0nqWGJRMJ0ZdAfjflgg1LZJBUuSBvED4uF8AVWPpByyo/t580yFpv+eywS97yYtUeWRVyymGfuPmknq+fo3aDqnxbquXgBlkffWjufheu2n2+sZZRoVAB1DCcXj2n7upsYEfcAASqQJ9zQwI6Lw/lcwoi7O8LPYv8ZM8JpRSaB9Ulxhu5m0OVTtk3Nhd5Oa9c+6LyhwGRy50gRxQ1PJuYyS5ykER548TDeAVXhgEqmiRrXEot926Nnma+CqAo8WpHZVXDc/v5StyJJnLQSuvGuoowKIxspbAiGSsXhnG1LnG1Yq1kWO2FMHg3iJBKhTud5O75UYTF4MXNYvAzWnlZPWJw2CMqcbRuQ2Pm82O5YfU73DTezRQGenpDGirPqm16RrA3HQe5QlWbLJoNu0Ec1PQoxXCvfE9dqGhXw90xINNP186ZUKHtKMBiA9kq2+r9kEGmSgCA/lYJoMNNSgBm6KZ21CLbWePk6zugcopGUWyPUoWKbqyZLsErjqUJ2BRR8qFd26fFjfbEtCEzxRDqkWtl8a7gDWsI5cCQl8SZNYR+WCE3Be8+MsSNIbztCNb2v99OfWIX/Uf89x+2c4FtZe8vi/zZjxz5qEMyx+vCf03UdzOeH2ooQeMgjBC3T7+KHzfD59zHYQDtFe0wWZD3vWm3InvuazZsNSAPq95rySdMI5JJwnUjsllI3E4rNJ5oFR9ENvNCgaVnDZnRIMeG8edEp2AmF9fvXNchk1sYARKRkSN5tBHJ+2sSh813k+uefMLFALjRTLQ176cWUkNHpnRg1TzZNqZiKFT36p+sMjjNDblWC/GpZKRRd3Ljx/iE4FcicN2McF2nv6tEw2pqOIm8ZHnsu+Q2iu3l1uiYiq5tZ4HMGF+rsORKC1E5WIeMx8k3oBuBA3ydUJ9kH2weANahJZdavc/H5BjPyi+L60p/dR3aKq68ux2jb746ZYvLOlep4fUlvnwuKG8e197V63EUlB1Zadiu1wLzSimbHuuAK1QANZiCEEAyLELNuiOVqs4g+UkLzwObwM3LUJ2RAG7SnnF8M5KLK+XgJvftqzOBK673ue+kHhRANYXeje70kbuhU3JFM3lNjOyLLWvq3GUNhp4vIZ9cllfLCM7IjafYKq7Sgek3tqJRcaKvaTRyLkicuOSh1fXdOkZWt/K5WJDRcOW9e+M1ZzpL6wMTZd2SmfBRodWWDM19lB+XRuOg0Duqr6iSn5uP8PP9R/Ulup34BhOMm8ffTpGeGGDUaVbmajyjkJ0OvCr9nQCvw00Dy54tOk2u+PpFk7Up9uYUYAWGmh8j0Gnax5cvNdpBUoQFUk0KVpxArQq0LCUTNXAxeEapXwGPWnTNg8lXG/NNfY9qeCRJzjpq/GGKMqg3TYxanAryFHA0Yd9wv/3bUl+hy0NeuSI4F7pADokxWUepmFjmkiGjLyr6GSQxm+quyBa1iwfdlxNFDT31059YOQt2bWb0epLjW402R6x+V53RSt+/VeQ3JTyan65dFE2OvPnmcyrynuCmRmtj8faG6s0kJvf9Rpk8XOMFIpfxeEIe8vPEeIJlBhNpLfm0Orl2d8g9/hsEftlc3sVzjfKOFwxelPq4K5qggPdWu+2+f+BVrwlAzxlu/QuiEI9M###3184:XlxV32DM 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cb0eNrNW0ma5KgOvhKTPFSfow+QaTuWvXur/PrujQGDkCXArkW9VUVl6GfQLKFYrLMWVjtZUMpNTrsDPs64D4A7nHVgjf+7gRWU1f7T6r938IGlwpXvw6dzhfA/6za/1ua2CuGUAutWcA485ep2AFgCxoXVPLWLn3g8VPh6x91/0rAg7J6wJmCtuLe1c9rbnCcc2hvjjZ2u/cPZMafcdW+/3sfN/jvr6TyPPYU9cTC7wxq/H7g5cJznc5BP+F6SFI+bE1JVazT2ICs7skbrdK6xBotLdz/pXLnbSf/vv//Y2Wzfv9Qv+/OP/UzTL/P9tf71P/8Rfpm//vb/ul/r8WPBfhGB2SDw+RR4FEolOE4MmjAFryDSwwzmEpz/7ritocIahTJf0//fCiI3dkWok2r337pEhVVuvik6xkqKOmdFtZnJG2Ly4jTh8bH9eGF9yXslw+tz2Uk3lagxh7HyecMHN4GnBnNb604TV4l8VD2KwCeWKmmXscvYXvJK0onC6jOrNYrIX9vl5qgwlpd/RO3Byeos/x0b2WYMNbKv2shqr5q99oCR0SiCVpDoKxWgeF38CGKoJj6VolRATcT7aMpgJg4UpMDexAuNPNiBmAtmJ7z9/qqN63JgU9gpCyvu0eWwCQ4Lu6CyjkgPp4cGllc2qPoV+U6qwitALoyi1ixXQC4soEbkkqh4ufjVX0gmomKEL47vUyn+bqlwVs7z2WRl+jeiS1xB8WLxNB4Dn4Q7mQFCeqDyOpEqx4pKqIZl9JypMGobMJtIVYSKGb28EM6SRGOLaHblRQNJNHpRNPDrxf54/lgvHap4s+hQFsIXxbiTGXEve17/H9NEJW4GKoyauehFeRKoeC8/MYY1xyT6FkGwlze33KDizZDWLuzeTd6SaM2fwDWi05VNxJs/1aMp65F+sbucxCMsm97qW242tfEBIa80Iu+8TrIXjVyZ9vGC2Mv++fEL3ZM495sxvFpBpJddWExZgvkkqlILHGddI6CWHNciVUHVNeUc/uIFfcOlv8r07nTAqosnVP7mH4hn9bwAf7KRNVoYv4PKYjZezC6LeaZe0XyfXlFVXtGUeMV6KN6vebrrmIkKoUqUYOqeCwmZEtc9UjKHFIkmc0RETsx7p9+oRcoKUi0ix4ALbTNVttNGDKiy9UDFe3NTtUNuhiu2U1xup9gXlULcda+T2d1WXgao/nnQj0eqvqMZTGh1SNueuJs1pPWb4G50SU0TVdFN20WpTFVrtIRyGTUju+vtdaIgW0+FQtZKUSagDLHW9gnnjBk/34lxKXccPR0EjGPOJmNswGgOI57txNicoQ5yLmDso31OjEnZ5Og+KmBoIWWIX+EwhngVQ7wKh9HEp/QCY0a9Cot39NOgyKwwHBId9knzQbsX+1xnPpcDtFdPODg5O1xh02BX1hHpQ59BCh2q6oWiMOtpsmKwYTYi10xZciDAjUmwtz11KRtJWonrc4oyuezF9TkNV1xb0pQEhA02c07cTRYroEznY271n9Y/diV5jsoH5ERhmzZ9sbNY9Yi1XZFhJnVcu8erUwo4ZSo+fbVVrrPfsFKrw11KzeD7wnBZHI7UMbUKbN20+4Fk0nqFW/TUaIXzZAMZXuklTF6VpqvNA+77lrVsV9aCa6/TsM9cWjcq3lnsl8QXhIRPdKg92Wie6YRTRDu08IBTIR49Ew3d8fTAgksY4xHNgGldXq3xqjMxdIuGpG78G3wGrZHSQyh3UsXk/PwO9uUOmrlzewf9cAeTdWP0DmbguXi/Yx4/+FZ3+g20eoXWT9DJQ80o2H3dejdbzGAEodHAU7ti5oBzwrpnzvTWwM5rCMH2dF5Coh6KnEu8ka5Ook0H10twLTNDQNBC8IQcPKdhxaIcj29AJZdZsHi/b02b/d60IQYwXgIF3CoWaKaJmu5crZq6PApIe3IkjbGhKDzvl/k9oIW0rYrXkKYrGiVmm8cdbo1oIbzSoNyiFx3j2mj8kPQvaeBap0AbTYFMeE5ZH6ZAGqWw7SSISWaauLGdrdhOpKG2bijyaZR9lEZ105jhFtf05u6h5pPSsnsKWe4eA7DrJjKuCtGuxysxZXLdhGZsJ83cub2DfriDyTvQhMZ1E5r7Dk8TmstqzauEZgytXqH1E3TyN1/4ZR1W6m8WX727W1PGhWp6zRmSHTAeOlpWVpDpQawFINSZK6pw+VcIrs2BsE+mr/ZqxA0OOoPATl9de6mrcTIQPA17UyU1rjqDiZnPtxG+M4qak3eiZDBF+twZZ7xhWXocBBXzfrx25BNR+/WCnOSzVfJxQwM8ca8lD/A8T27wChL1gd/hbm0+zLUDdWuKWwORvnyfzRxxu4NjqbEVmBeyMXk2wKG0pppcs9TLrN/cdKgLxcvv2E61gkAtj0e50MFbU/u1Ds74yVs3pAnieBQ/uNbnrs7chcxdPLrm96M+3NQ+fL/d7q3mL03uTt0GN+YVNOdk1he8iqjIq1Li4VEy/W2pm/DLxX41N0UbX2jf9L4qvNi/M83X+vV6nUuUxZNvbrk9AthMfX57eSEQ3vQj9Zqpis4e4tBhnB+APAJSo7YOaub2QqUcj1pIL+s+dMi9oWesGE/y81KxqkNhq5q+qFnp+XOWYtrrivGRTme7ii+VZxIW/upPMvndJvcJY57nm/pZdLhT9ikxTWipiIAPbuvEf097CQm9PW+D9u1Q8nOMwVqm58hbUYRP0S6JWlN6xR6qZ7bORCDW1zLXMYuaGIduXe77Ay550UMgV7Biqvq1QEKpggpUeAR6E7V+rU5YRSCxrMS+5mhNpgu/S3CNH+Awg9OHru1konbiluhROSuBP2Qly/+FlSyddo1pam562UJW0tNBi1BUB4+O5iry8K2bdnyhbKaqLbKt75bR9yoLeqG5Jmtu8fCm0tz11vCd1NXwfenh/R1sV3d9tK9+fdLWXPVSc+cXejuzWivle3NzhunSWWbKqtIjXtOBxAPdnB6zyLuQ6bHmXvrSdLpXyDmgp7OJqj5h69djWNMxVetZqK/pzMPGYWtN355pOvwRTYc/runQ0vSG9k2S9lV+1rDeeSZ+todSAbUKqLb2KaYr1MrB15JlkRz8GNH0qrvRf4Lpa3r1AJM03dX1naKaDvkRr1PhvXwW6FV6vQz4wj/LgCMKuAy4uxegE5XZcSFKC7/ohCovQr+fvEXxBgWdYhB+0Tmwl7ySdKI8aw3pB4fb4BOYCdYO6IFNqky5fLtgpcpUq/8AbfyZJQ==###3036:XlxV32DM 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c3ceNrFW0ma5KgOvhIgwHb2Od4BImNY9q5X+fXdH2YUAgHhrOzcVIZtiUm/ZkqaAwxIIQxoA0Y/9KF1fL67Z6WN3s5n9/5ptHmZHdx3z6UzldHPzGUmXMeFuSyoC3NZ2C7MtYHIVJjLTLjgpDIbWSE/F3gu697e9Utv7huYl34Z4yggnJIfrXC70dzTXd/bERxnOKHDaG3cEzMmWoGJ8nBn5DgAr9s/K2bde5Ki+3pvuEa7xbJHXPUZ/fvv37Cp1/YhPuDrb3hZ+6E2c/z1j/tpPtRf/3N/9YfU9gsOuGlllJb6gSQBXn7+rRvVulVY/XJvrTsJ7U5Fnf+6pTqqwt09r928zsHSPsJft8tzVOmkYapZJ5S9GU6pwf4+H+YhK2CozcYi8TyZyB2pimyeRmUu0eXaM1XgEv55Y7m040pjb4RLTbh0pgp6KeKKFbMvSFyRKmuz+/twZ7P781deg5JuPRreolMt14kcCSajdq9Re6OotfsXSBAMbs2v4Hb/ddzuI9yuIDBSdbHkxnue3qPh1P4txq6KqEx4olzGc0GmylwYhY4WmpVSJJaVnuf15JGLvvtf58mf5+P4Tzs64etSYwxvl5C/ZeRDRv5RI183yFcj5C9YbHducop86ZAvlpEvLiJfXkC+7CJfMMiXSxZbtBbbPT9ZLvBcKlOt2fnAtfXsPIqJ+ogvVNliT+dKGqYIV9FLVrsiVeGqcWsuod1ktOuM9luNdtOgXX/Tzv8A2s2vo918C+3mQnyCEfdOfALd+GQdgdS+w8S+A2Ox4S37Dg3i90uI3zPiVUb8J0b854vG4w8X2GwO7nSykIZlFZqmKLJxumEE3YeOd7Zy6rjLKrCB8FwTxx0490xZBKvMYQRWKkJfvvtfRFQTvi41FhF0BJvHYAULUQ76DF6jYO+VKROfTaJ1bxMtA26V3sCNTZlcNmV6yZRV814yZvqCMdMkbcZrYOh9QNo3FiHtTmcX6GrnqNjAtfDqmtbT3fXeNUyJ/vwuYzL4ZA2giByWhAnz1RVe01kdRqLulDMqbgbBge+e3FJE8KNG8J0ieLudzlh2nbEMLuI/xHA17y9huF4Dh2FgMVyfHaW7Gxtw1uFQAamOYkYZMRsoqzSwl8xF+ioR9IEuKkkpXjciXfYLHvmcN8G2L9B1E8GRdlRpYKsd4qJ2iKwdxXE/a+14UO04xJeXy82ccx5+VKwnNu73v9aTat5f0pN6De/behulpjOGcQTRQ3/iIHrSWHbjA9VM575bZsREWelT11fYvq8YhNiS0TxBNIjzMbrWoBSBTcsprSbheYpGQFXaW9ckKEV1FCm9kCbJT7ETTXoeX7A3IbDyENrj4Z9hnZ9mIRDeqk2ncQwXCJ9VIt/v4A9eeYHt1HDlI07goBznYUEFrwyPrkGFAskqr+MMYqk8o8AcKZWchhklI8RiPC4J/4iSglzXdevDoj9uTb6vdQox6vk2tNLTHMKi9BU5q20ScgZ63Emp5SiroBX3bYR/frJ8puJ7VjUZfj5VyYjMNwgsVIUJoAazizrVoq6qTEmG3pLalJy4fUkCY5RG+k7dituHum5M3Le96PaTsdK5QgVC1oi1FLHiFtK62lrJiLRgD76D2HoklsN3SPmUohqlS9tzeYlLNk6UUjptx5TRZgFyebJLL0JnGbk8SVDA8dlMV7pRfLe1tnWBrm/rQlXoCnp0Rg9k9KgaPVuDnmeNnnuVnqociMKyt9u7ia7iK+Q5OJmnywqFX3P0lCRbTQImwHQZXbPeE5AUvk475uWoXgqxGnAZYrtEgyJ1EUUqo0hmFEGNIhowPXRdM7yjEuzhAf4dA4TH4c3P6NAg8S8GSyQA8tBSk9I2FwJJEgKJxRCoFShcFChkgaosUI0E+jqoVTicPA0TAIcLI9dqwGmEfVYDrgILdoyGKlRqN3bO8j3XZjuN02qGvL+aw5/nieV4ngbn5o+npAd6qw+0xJQlQZHLFtY2ESWwt49k9oN9vxS4NYnRxj5wy7dMqP+rgWcawCJOBqwmg7XE7NYdrk7Wx6kW9WG355ePLG7NPaXQbsDeVhEvrUjJShOukseE/o5l6cv3XkdnwtelxmksMLfG7ED1VVHVqkz7oGtgk+fUZgDS5kBzN+fUrgDzKcRX39fgpQIeNzbmTMF7G7aMKH2Els7FVB6yFzkmel6DVB6pMeFMyQuPealTi/e03qv1XL7LRE8ivPV3/l5wfg1ZU6TlRnO0JQbA9/j0Jw0BducydGPhME4eb9g41ZSpASGAoa9kxOp1pOpnbtC5WbCiJ7kqkItMIPbaajX3aD4Vb7WSfuBgAOuHmFitfggRkE/xYb6LjyVdML+iC1TLzVjLJ22xNMZGQrV5vJ84906Zs18L2VCgtDd3dKh9DHouMxW6BcdyadSQp1wGn0OzmxFK+Xs6616ruqfztjbKfOsBZzDnrbZbCtCsEkQbrXicEZqutFHFE7KT2gNUHmRn6Uz0Y7apwIoOnQ5fB/PaeAOk1HFV5645ppee3rx1vz1xCebevmK4lI/1DmJx5TAaVblpIheq1DumHZ67XaY8CKVs6rGyI4PIUbVOaBVSdhtSOHnFfHf2hFDlH0VeYtIvEG/3CwRJgblGVyuzGSXEyvyc0iAcjBPwVCk06A5avxpM+WzkW5EDTRR17uR477+Qu2myTz3qBQX6QVsS9ZJoUzKiY9Q90plq3Mrs2MFBGz+cqA3V9eZOthrKwSLfWrLKkFlplr587+VSeihvIl9HpWLrm+GpaOJvertyeR6xMI8g84ihHVnZT8WzuJ+1ecTCPCv7gVyVx1Xy0W7CveZ39jKeQ0znGO+jwWcHlSO02Tf2885cYjpXb1/4GkniMdX1kIrD5QWKvWJyrkqa8270+ev+9uhyYfTTHo4uwcCfW/3lef7EPlJf5ed3Mp5pcS8dSZ/WTvwgksbjL6475hC3OoegnVhz81VeWeUQJv5/SRN9p2U6UKZQ5biU78prHx8Z9g7A6LJfyIENinRSdjni2vMO+NgZUCwzusYE2eaMYkATs5tjiQ5w9FllM6pDrUJVHJ2cGtaPEhetKZK+N7HLiQsyFV9d713KNt+3Hm+P+x2NS+PLH1q3/NF1/2n7Nh/1O2tOupxn/T+I43jQ###2828:XlxV32DM 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c50eNrFW0l2IzcMvRIJcKhyzpEDyBqWvctKr+8eFkdwZpXt7pdFyxE+QIIAiIHaEBkTUjwRxEPsQpg/mbiLDTlu5tMunlLIl9xQoJA7bpb++P6gkxJQCjB4jVBQ75HaURkZhjt4aW2URLAoGakS6inuZo0WZWjRyq+ROlLG3UidkMiLVXKD4uY/i5NmPV7iwf0QDwY7wlAa/1m+BFySwxbksEJOG6OPXRutByl8upvzexnJYFMZ432Q06xOr70Pev5r+1iRwaYyVvYhia6cVc72IU/vYyyDTWW09gHmLy4eGUbS/58j5OvwU/ed0aUyEpV4IaIy3x82ws13wn66n+bOF7jLJtftR9e8ffOag6/8zJrn3L+y5p9e9Tes+/fvX6hRbx/sQ75/4Uupj/3x+Oc/80l+wD//mn/FB7+/3kaYwBtxGnOFmUVof/29hDbfoWH9ktJQoHU3erHlLge4RbSjSpetJMGHoMxGpVDykHGveNQ0cy6SXqB5qEpUErysfU1Wn1NvRWu6NBxgjm5QPQyPzZmETRvQSDBGEnXosIepoNilMThDS1FoV2XNy5pbG49dvJP6sJ8VwT9KvRK8CSSSWcQh0Rq03Io9p/Ow1N4VKK5NLfNkiKC7O/Mr4NkaezZfn4vVrU1x0kVUa/isNWh6QXs33o0bY3Dj7bNw4/3zbYL0rTgBTKu8uM+MQ2e9umu9BzxoiaZPLlF9dlGQUJbKokginPRbny1Ft6022B0n2r1R7e660O6Dvw1RrV1tJXHPDxe0C8VOCYc2tdVbu4AIO+WRihQQ5Ex4T7ueKlmuMhfKs/AvSp++t58ObR5rNVJNvTTDNanTqYgLJyniSUI8yU9zksKfJCjNi6N83d4mj7llC2VWjIy58YqRhrAjF4zUVwPN4CgHwVXH4MobymETvIhuLyoT6O64waE+UhHrzmhwtKpoVKzUGJphxF4fpOptXGcZj+PQ3UrnAe3g7Y3jbozjFo2DycI4tMI3KhtIaQVxBDHlNJ27mQ3VvereoRKVczOIXPooV9+clSWPczktS+B+QZY4dHpBFr8gC3G7IAtjynROFrsgCy7ZBlyyDX7aNlw9kWyDoLq9ooDCSBUvCXkE716H6fDQ3XewZBZXngRVdkzQorCBkt346zp0+3JHT9qYt8eOHo8XYLuICfRbpMr30kOB1RuzmnF0FHef4lSkOydvj3RJD6Pdga8yxcn9CdrbO7E/h4PY3TwnzyVtxf7svSuH9gu+45W6q3yiF2/3xDqINRZJVd0h4S6CdOp2nNbt0OnrjPnCAl+TIA76Dfs3r3rO9Strjlb/I5r+yTWrQVfn+ppHXM+uuYwRKuucQtE5hS6ilfJjwWksCwtZeFkWNmMfnNwX93embE4BYCpjZT9jGdiYNOwn9kER586nJWu8nzOy2prACyfkMLIzGYAFOWunNJYzsVT7fU8nTVw160h86ooj5Ycpq9TddoD0LRqWJp2DHDS0g1iePZp9PH1tV2deBNOpz6DDrd3MYr4qXmhlzex/8SQozmWoKcdqnUSg5zHXITnZIA/mdsay2fpWeT32cypHr0nGCx7JYr37IG0tBCjL3efbNv5zPQvbend3t62zF9pa5coIhw71KLPfI7rM7Gl3glUdAoLs9ETinkhP4El0BHib6ChI0l/WkZ7rqOu1mY6KuXTWfr6gI4w6wqijF9WRvBc62ljLjkIFdV1HGYc29aBDR3d6vo0811OjjbwxMmu7MVHN2p7HrE0WszbXvNnbm7TLPQZ+dTiAoiHpwr8oCiyIjzBGKBmp4qUxeYQSkFvRDExzF9GlT9/HqQ4JvhNck7o3CQvNVkjNuHlgqKZF8YS6rVqMrVrRwSvcludoTevI5kx1ixmbWutfulsxaWLddQfd4HLDtZznRe3T50Dxmi/Pob0LevGu2PTEo7zdSsrDOzEnwe5W9Yg5gJsgTJR1ehg0OzLwA86e+28RLQv3lwe6RnWG7qo34p5yIRRljt4Zui/I6nPqrajg7qiS4dDMAxpzEVVlHlA5m+rMY9TgvnCoR9iPNzYgxqYeW3mzinaG5hxqD/OdZcfcG/1a1XMUT/8c9HtT7fAsatZ8CL437lcklUT7cULYH6RMZMNMX3hCXzoF+TOTo0pfo0pGFVkbdPVFa0eo5m78gr5EHEQDyUgEzdyUrqLZ7fa2fdJbuxdmJxvt3pEQhybFsfuiZ9apxUwSQ5/Y2H8PPdgaCo/9ZJK3MW07tMfL9CSyqhXzdQzqVjJ5aWWvQYd09sKKsX6Zt0qC03kP2vyNXVxYMUa6FXnuEULCFfK6z7zQ9+ZZnIHLxecdWOCy98vJe0iCkLDcY0XxpAQKma3InstM92MepWUntseT7ER3GaN7ilYy9z5VeB8w+/hOFd4X3gA6jfxJ70uS8a96X76OK96HNgMIOmx538jKtO/y7S0r62Ydx8k43Bbp8hktDLpqB05HujWc8Dh1EoceJxs4PXg6xAmueA+fTZNZB5fmyalYTL2uGsF9la2mlMxnCypaRj/e8TRrzTqlK5bBith8PkecxZFWlqjyOFK+T+Pa3uIcb/KQufuHlimiKH83/PmIkiT/3YiSr+NcH7rDpd0Bb9hoQMHUmlW8wzWlbP5CSVNK/xulfv+dUvIYx+TgiWCycqTT8+Fzz9o72i/LePN914p3ZI0S7x2aeAf/FFXbTYq35XvrPAO+PlGAldkGfYzZsKnAg0fKlJkECyiptxjtepYE+alHCtnNH1317/Xv6ehLnDMP9wOXP/N0f0napcf7mU16urZFY/eN5tiiHc49wU/xfqMWfVPVjzbEZ6jaBhL9W4C5VavBnjv0wxlhwLNTL9XQd/v1qVdxAQUNWf1MBnx3H+rZ6iCPgWwmMM9iwhtfKGJ5q8mp4/xUFb81LVeuIrUkuUv5M5IuqkGVrLHVOleTR9jxPS7G3xxte2a/+FlF5Gc7IuvCelc7NWXjWE8sGOJ7tXaGrIvXeEBn6cOxCLmVs19a9m5nqG5nVkRpWIzSUERp+KYoDUuRFb4xSsOZNQ2jdJmVtyaiK1Ea4oBHkLzjllv5vZoUYGnlzqd4rC/ZF+0859RFDCJD4AB+IJTXdP1cj3u7BV/r5rleOw/FhCDxso6IgZLHyMomNwcnXle+co71+v+7lnE6###3240:XlxV32DM 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e94eNptm0uyZCkIQLfk//NqNQo4rFmPOnrvbUZN8mDNKt4prgqICGb4if/+zqe1nxjr/vXP/Wf9Sb/++532OD/hmxroDKAtkkbSQpr5ZSEtP/HSP3+Kf/7UKXAoML4Ewp8/bY6fKCCPgC0IFIWA7UfgcP2FUzpcf+X4J5FWUqedQVpJA2l7JzopkCmwXgGlQKOAeetI5pTK/BaQ3EgHKS1bhPSxrGRnqEaB/QoYBRYFziPgnO1whMnPHS5ncs8cLmfBZ1IIpJG0kNIrDpexBqmRKr+cSI0U3qiR+jZoQxONa4OUmjQhdXMOpHTbU0i5vw3a0FxIjZT+faANHQIaOOcbuZz366QKAgdz7hK5yEXZiCCqhwqiQ1hgEAmNlGYLMIxFJwv1WeN+joTiNWCNTs+JdPrAJnTbBVC/9wN3kinsT4c2w1YJnZCS+OwpsEfKm7T7WHHKfP/EzZaV3+BmK4H0kCJWn8rwUSpp4rhGmp+JVi62RAq8i62LAoUC2zvGcXEnwb5nZ06Y4+9CysF2Je2kzoyLtJMm0ufIOXtTgHrf8grQjBmb70hwAjlEBLscvwUuXa+APH9K8I5cEr6RImkhTaSNNJNydgmmyCmTtneiXGyKFHgXm5Tjdwr4hCSH0alOqmKMZ4SBXZnhMJceUgFlIpyx7y51eg+k1Gx0tDwTnW5lbirvypgI58iVzdeNmF/mwBHOa84jXD+VzWQyZ/rdcXqn3x2nd/hdDNQszrBLk59oDG5l7nPtFXC7slDgcdTYGNEOR2jlFVjcClxDo+2SkFLvyUid3gMpNRu4sv4EqNjpqDhwL31XxmM/B47fH0eN8q2KFCf+/00F3B6PWvD/O/+/AFZAoyRmljJDNxLLfI9rP+9U0vsnHj9Iey/l8WOHdNCFEukkLaQ8p0xJ5Z0oF3uoivoutjoHzxTwF/fr0MwAFE6alj0juGPfOCV37BvHd8c+riqXOr1PUmrWIul6J8qVGU2x35UJr3cGj03yuFGONKfCFfKbAWSe4kkxpcxTPGknpd51kVLvqqTUrFbS8U7UrWxQ4C8ro6PqhkB+HDUPmlPgCnk85sw8xZNwSjzFk3D8Sb2LkTq9R1JqViZpeyfqViYU+MvK6KhyKPA4aj4056YrnNecPMXT5pR4iqeN8Utwek+kTu+VlJrdSvocSiVwZRIoMF4BOqpkCjyOWnh1vgEOAq29AsI1cEo8xdPm+M3pvZE6vcOzSqdmdyR9olHpXNkuFHhX1umou1PgcdSiNOeiK+hrTuV9dHFKLBGkxfGVel+LlHpf9CylZhe90p5oVMytbFDgXZnRUdemwOOotXyHoBtUvv9/RdaQZydcgJtwAx7CbxVmmquiznGDFiDSiBugCAc+GwmxlIX9UOXbRfOAO1RUk/JohFDfWISY7TDCgqVQCdogOQgPIIJmNShhIio0d5dH2+bSZ++2xGsGOjmX7leAtwc0dy59zoyWeQlGv+fS+Ai4+wnaJ5e+I/TGNUDTrfdXgLc3NFkuXa8AL1Tou1yqTiC2UBETGy4hHyzEDTjzcOm4wF0cI7ESYyewwXVpg3ALjkL5MNal2Axs+30ogh9ad7E5pbfj8FjEm3gbl5yJpRFz3p1JYqe2Oy92fZCOxok5ink1WqJPLKpHUhbx2wQdgZT6mA2W6OjMfDAHDlzxdsqOVJdr0bZIZW9xzruIEfcu5rrUqE9nSTUqNNJN9FA6qsOcWqLvG1uKXRylH3BZxit0h+/3ymsQYtalHLdGUtYkBSfFBx/iTMwmk243sVWI3cyo7t0cprp3Dw4jWkiHNXpjGBOns8YYKas5zI8jS7u4YWHbKfXueWIq9Tox112JhR9vbmrChUkh1knMj3e2vSd12lkics7QN7bmEkehUWSuN64FKHRxViNSNjsKJ1xU9uSeHpuULx5GdxTKGogW3QZka3UUspVzNl6gK8c1C9wYxeFB7EY2bsruhvYbgx8/LPTJDg7z45vadt05mXSCw40hk5vysKcvm07iGmSyt8PKgEBzHW6MzRg6An1sj+wwP440/eLkdvwmzm7HC3HtPBqmwzx3ErKAkdkhcBPPEd8e8JUxuGdncxQ+PLnmgYtLnJzVZBuCbjSm03ZyFLIoR9wdzDpcS/z0pq4b2vNxKLXVmSEMjczWmCHMwPSW/jtduxIXz0u7SwAq8WBukmCLWelhHY3Si/maqaMtHmdnJ6QztZ59IKL0ypl35ta9LWJzH6fOZqL7MkDPyZm3xYUtVr82tbJYba7M3OeiQW5OAHz4Sqgz/M/DZ0IdN+GLGW965dSO8FrA82EFHsQNraYPxtQYCVdwiWqASlfMTJKF346FO4R514o89ToamHElvtHpeMQQV6GnNc0Oc/Oi2h9XK86NhZjHSy8Is2vwDWJDWfqDObZQqUpPEx0O8+RTftwFDnX2VG5fdRZTFkUFxfiLWUYQOQ7zSDdqTQdTQnTYLjZ36y4Ow1tQ6v5QqHy7ebMi2HgVXHrcyE6lzl5ofd8ThbFY8WTpgw8xlLLTcQZZDgsxPG1nFvHFEjGnJuj4XVyxMOUdd2c25BWN4A9exEbcmR3y/NtZYE4TN3M0tC92M0c9MhoanR98iOHlN6diCsbYcHMq+hJjw8UMiUp7D1RgL6ZaxqIb85C6eBHTHVyeJMnNnE+nhDWePWPmMWQOM3kcjvKCfmjP2ViLwbvBi7vDzWFeB2nO3Zmuc/tezIDpvq0l8AiLDtNePPcvhko3D6mtvIFvN3NdzBqGOsyPDxpEedHYi5tf3Q2cN91tAbHcMtViPCiM5+fFyg3oPs7k1wQLk9K+150CXrx88CHOxDxmFO3ki5mhKo9XKUx4lAVaKcqPs6whrnkleL9+MR/AyoHWpC/mDSznXMy8gcUgcdXOPuGpMgJTb9Y9ZLikhPfti5km8r4tkzWy7anb/It4ufx2E/N83c5grryxmQ/JYpN7z+4wy3O8/4myjbAPdaquRHaSwzQ3r2GiLmzxEidGg2lODtMTMw1mvI33SaW6d+adJQ45hVnJSA5PYo7tHkvv0hymzgtNcvh7Cp1OerOs5AzqXhhvlpXk8Lq/eRO7+S6PQF4hb77Ls4IX0IsZO1ge1JCYjTEga+SzAOM97mJmJYMzz3QmZXlFM8t8yuLMPaaglsMGzsVKzKlVeuphiquVv3g4TJC1Yo+lwFadVuyxi93Y2GP3MBBiqOViJRZmwCw4XMwNzHKFsnV9vaUSswAqvFrr4G3J2CzRwWPMGO11CE2ynbTSoNtJ8wnGUTry4C/yjlItk7/xsbkcFmL6+WSCfFg201kjcSbmkypjWU0nj1Bb3MCLPxAxtgZ0sWFiPEJvvsX9zbim20VkxrWLMbZWjr1ZBFK2W24yx8DFQ/JiZpIsIanLge9FnXgkYmrN9SO3uYWxH7ltOMxNlJ208RRkoUaFv1STcBxmwI5UqrBayWKlikD44B3pxdqJnbRy/xp3gRh3gdFgyh6VuGiv/OWksGqnygqTDppb+VZYeXFQ5R7SRaUp95DyynOxMCi6hW3eQVn8ssBr4sFj1w92gWkT8yHtwWuui1kyPGsSs2x3jpMe/Phx0uzp23bScxA7aRagrDlpRlxrTpo58MGvKj/YOTI2iSXWro90YrriwYPdi9k9t54c5sx5cbDEErDW5TBzIracLPP3osKHOJa5DYTPeC7mx/nwxDJ/U6dstVlmYDI8cbyYJjF2ey3zNmZKpZZ7VvwPrhnFTQ==###3800:XlxV32DM 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ec0eNptm0mSZKcSRbdED15aDY0z1Ewjmfb+SavBj3OjZmlxDB443kOGX/Hfv/Nt7Vf00//65/1Zf6W//vs7eqnhV/g/biML7sSF+F7iA1zDInbieoDnIm6FeAOPgpX3cAVv4BiAjaNvS4IHcRaMfd/CjRk3dguXZhNCvWMK5uSDYrHVuDSKxXYh5pHM4J/YKw90xkZcBWNjHgdxWsRG3CuWZi6YUjNKbY7CpcloS8Qy+mxOLvt2Ss1k3754JFSmeY04Aq+Opd2YBE9i6toa8QOnkF3wJea+1+HSUiP2SNwF0wwidW1dqmKkrm2xsVIEc/JSBcMMjnPlmzZ2nCvfsLEUUhBMqSWe2IaNPUwL3bCxh2mhPum4FlfuqxJj3+/4IdR2nLjQaZ5DfCnzOgRT5tUEQ+Ye+O0UaP50uTcxWHiZgjl5WcSNridt4k7zT9x3WvRrKRFvmTwL5sZKID70awXacnPDgfotgjn55XnnTmXKMnokYhm96dcyZZ4P/VpegrGxcyjz7EZMmZecuTEXTKldaksp8IrnUuaSmJxLmbfDxESxZ2Kqw+ifUrud+xq+f8VHf/8Wfv92IcgQeAzjVmITfIm5V0Pku6uTIvDdRdU90WiTVJ+TInEVPChlqs+hLzr3U32e38MZpbsVG/EEzgGK/z5GHDNxIh6Q+MAZ/uBDvIHLYszNgXgzYucoWOyCSyvUzSMbaxBLbIhcD9ObNB/Ea1GoRszQdDdH96Kq/fMbtO/wEDvO+HoQmr/nqzCuc2XE/R7R/jALsv97eH59UgqHMuw43ocb8DCqlmxqnMvRlMhwJ6ZaW/u0uLuv0AzKqb1z3Zvb8iEGxW05ctyHaRKOZO5hivQFQW6LOn+zSBwyi2GIzCqxyehCDJHGMRIx88wx+O1YKBaEqYdrIsa+Ywqy70scKTWkYw9vBJqIGvYHI2zU2QRj39UoFsk7qlXBh982Yk/8NkfniW+3ztFZstQOLY+lfG5sVC68FgkMV7DoMWVa16f/vFMG7wV6hF5Qbqo1hLs6uKnWA/ESLIepeBNTz5pdHqZ8m02Bapy8D+Y71gXzMA1u/1lMpMCpCsPkuHia1inxTHq4L/raaCwhKz11nP1z4bcKRRRntfKoVVCua6VOw+XglbnnQ4l5E+ugy3GqQmvU0Rv57c2lvUKKmO7uIgO4qDZ+6GeMuFm+jIW9BF8oLCtTx+79dBjXTCjOwuS7yHAvtfe5Cziygmw9pZQ/N+z0wI9e0ENaOugSyrFGaoNxpRFPwVUw8rjwNfoQ89uZ3c2YM3FnXGGC+vAlhgYlpkfsZqU0YM8vN+bKxsjEnZglZQxB8NRc7v2GD4bLIxxeOSM3Yxm5emf8ToZI9DAnnyhhbo1CIagiYwtSuUK9nPdzrDvpCtBpP0IPKLV2RY7l+awBB7A4874IFBF9kpSDS4YZiS8z443DzSmx5+6KBzEnT4zrxYSibCidFA0c9gp/qIHCljJrwXTRn3nYGnEXzNT1NsEyOVeW76e8XeYuKIFdxhZkpn65qxI5lrIuDYodZCwjepCxaDmxb/Nc9UunxcDfb+UPv8Gqn0OTaRZxE+zfM7Y/fBn11JuGSlXZVMxsAzxsHzPG379t+/7KhgvKbXKaff4wxPnlIEPu95CT+BWa7susiLvg73U3GmRmJyK3DNeZyxbMD4rBtty/P7gS8yKaWmPbpTUq/EJ32tkYyTtALb0KhaE5d7ojx1LhD5OmeoTC39ZFOuC2GmdmzR2TCebF0Qt1ghcxt3xR68TMMipfXnlltgMepoKyRsvXqfLsVJRQqRtsgZUgZsl2wMP0Dew1lNAjMWynJDaY2Jwrif2XdIXC8zE6PopqBNc+jyJPudmEYuZchWLmDNUuGQlwXFsoaz/mRyXzmq3R15eMXNC3fHkFUNhrKTQbqsijMFfq16MOSmmVxjzEueXSpUMnX+5syrgLlsm5soo2ml+hhoKCLe9HGc+5K+ndJhO8aO7sL5S2A3EXvIk5+ZhMRNg3LoNXmpcp58PMcnwKlsn5bYuQCmv8YgmZivgCQ9/RGaKKZY6lrVtnne0yuMumaDg2RMlk8oPDrMkFN+g35Wkug6nAEx2XzAuhh48klYJdMtYsWDLWJFgm57YXrmmldVEWLjOlfCiLeaX4mi03OncIZiNWLG8n9rDuFCyTU0N3473I3YJFJjyu3dlCvi5YJqdHOQmxMoqWyiVbZGJTzoBXmCUJRqycsQtGCjEXheo5cfIhuHE0w4Mz8kyJPM5SdBYXjNzIWJaVG7i0BVWrMaDkYzL8KLOyKhQqjsddjyKs3Wak6qQ5dZqw+1mnYAjU6M9qWhTolNG8B5l4AvWDIW+j+dUcqClzEA8cx8Sjlh+M2DV7IbbC04J91ZIlYHN0KbRtZv4PS+xqgmVyHkkxHkmUpbEvPxfPu0xKDU9DUq3omcbCArM2ZrKRCf7DRsx9N5p+ZDpRO7uqk+Vb7XwBaVdGV7FtSq3b5uRF8KHpH2LeZszFExuDF3oWBBsbr/DGL0Gj1FIQjMolynnPljh6CGYzMplgaa/RSiZK+GdxUbATJ2IE7ofl2y6jufKF51cPU5kWSrKHufLVmZHEKVhGU6gLtebD1HO+I3yYurbweubhIlhGU5k2rSQnxeyqyHlvXqwlJgYPswRn1vHw13uKutksmlXWg/vLaOyh1s2sc/J+sx5ERWMqUU+mLytc7WG8NqYxD3Phi5M7m0mWFMMqTQKEs4id7IRU56vmyENsgS/JI71wk35CZcb7sBFnYt611Cvflntd9nBbivQILPwfprPKMtqofh2urmW+x05XcJrEXHmWyFeTYCYjrPlankxGlox2xo8uo53nHWX0ZVhdFEsRbWH3tDGdiFNkLk8LJ6uUViRHYxneysLSzLZgTG5Bvs2NxUyxVC4t5i2Y0Yf3t61W0TWqQz2RV2Hcd+Vzzs62WmuooKI1F4wMz3jl+LDTvgsxv11dJmctUNnvaX3xddHi6IHe73M9VTA9bpTRkerAHK3xsdhbmmK+0WGPoRnf6FSmrs34fweViW+b6H4Mhq428XBviMuceAk+2L1oK2TQKZQzU0kX+86viiHmPcUzfeAdWSm0ILiyiEmCGeEmBbabeLwtmB5vC+5SfgleUn4NwSy/+BCm7S3lF73OCRzdFTP4BhrIifR4TKjbqfSXVTFDt1jfYTN/LhnNdxDGIuZhGicr4nYW1YHvSpozuk4+/WsuPktU0emzBm9ImjdprTTBPLEwBEtrhfhyY8bbvIep55IX3EU959VPD4Gj2xJMPecToh4i980T65KyVD557CnxXSGf6/SMd1eD8a/nDM+SB2mXt2QyeMhbMu6a9+UxMn/thZ4lUo1ftYxHWdkVD+IoGBEqz0LMhm7mW8xeRcu7C6bxy+SVBzInV1756NH4NqtXJsfGjKRXJseTPYhelxj/ECzGL/veYvxcWpO4zieTDzOuFxmtcZ0ba02aDIeY/7Q3mCT2Tn/cAk+sx0h8BX9ubJoMbtDjwcS7d1x6PExN7FtsvwlmnOFThofF7/A8R2RPiXn5w4clImU6ktSAXNpAT8lYEvQxUfmyTdd5+2WTEjUokk0K1JCRmPgFi1wVtcjQ2zemd11aUUMs09h7GIx9/auZxNFMhQbvBfpGZ38UGct3CZIdPiXgE0A5x4PO4uClQT91glIkh1nSmIovMV2do3M/WIN0h1kNvpnsDk82qlD8P9HgXUV33JkNdr+6M9Vm62y8spwJrxNnBuMso7M0ZS6x3A61Ifj5of8B9/W5EA==###3848:XlxV32DM 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Top Project Status
Project File:MIPS32-Pipelined-Hw.xiseParser Errors:
Module Name:TopImplementation State:New
Target Device:xc5vlx110t-1ff1136
  • Errors:
 
Product Version:ISE 14.1
  • Warnings:
 
Design Goal:Balanced
  • Routing Results:
 + 
Design Strategy:Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: 
  • Final Timing Score:
  
+ + + + + + + + + + + + 
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Detailed Reports [-]
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
+ 
+ + +
Secondary Reports [-]
Report NameStatusGenerated
+ + +
Date Generated: 11/18/2012 - 13:58:40
+ \ No newline at end of file diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/iseconfig/MIPS32-Pipelined-Hw.projectmgr b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/iseconfig/MIPS32-Pipelined-Hw.projectmgr new file mode 100755 index 0000000..1b2c542 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/iseconfig/MIPS32-Pipelined-Hw.projectmgr @@ -0,0 +1,168 @@ + + + + + + + + + 2 + /Automatic `includes + /FIFO_Clear C:|root|Work|Gauss|Final|Hardware|XUM_Singlecore|MIPS32-Pipelined-Hw|src|Common|FIFO_Clear.v + /Top C:|root|Work|Gauss|Final|Hardware|XUM_Singlecore|MIPS32-Pipelined-Hw|src|Top.v + /Top C:|root|Work|Gauss|Final|Hardware|XUM_Singlecore|MIPS32-Pipelined-Hw|src|Top.v/I2C - I2C_Controller + /Top C:|root|Work|Gauss|Final|Hardware|XUM_Singlecore|MIPS32-Pipelined-Hw|src|Top.v/LCD_Screen - LCD + /Top C:|root|Work|Gauss|Final|Hardware|XUM_Singlecore|MIPS32-Pipelined-Hw|src|Top.v/MIPS32 - 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uart_bootloader/UART - uart_min/tx_buffer - FIFO_NoFull_Count + + + Top (C:/root/Work/Gauss/opencores_svn/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Top.v) + + 0 + 0 + 000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000000ae000000020000000000000000000000000200000064ffffffff000000810000000300000002000000ae0000000100000003000000000000000100000003 + true + Top (C:/root/Work/Gauss/opencores_svn/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Top.v) + + + + 1 + Design Utilities + + + + + 0 + 0 + 000000ff000000000000000100000001000000000000000000000000000000000000000000000000ed000000010000000100000000000000000000000064ffffffff000000810000000000000001000000ed0000000100000000 + false + + + + + 1 + + + 0 + 0 + 000000ff000000000000000100000000000000000100000000000000000000000000000000000002f2000000040101000100000000000000000000000064ffffffff000000810000000000000004000000420000000100000000000000240000000100000000000000660000000100000000000002260000000100000000 + false + Add.v + + + + 1 + work + + + 0 + 0 + 000000ff00000000000000010000000000000000010000000000000000000000000000000000000109000000010001000100000000000000000000000064ffffffff000000810000000000000001000001090000000100000000 + false + work + + + + 1 + Configure Target Device + Implement Design + Synthesize - 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+ 2012-11-18T13:58:40 + Top + 2012-11-18T13:55:48 + C:/root/Work/Gauss/opencores_svn/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/iseconfig/Top.xreport + C:/root/Work/Gauss/opencores_svn/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw\ + 2012-09-08T00:01:22 + false +
+ + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/BRAM/BRAM_592KB_Wrapper.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/BRAM/BRAM_592KB_Wrapper.v new file mode 100755 index 0000000..294cb37 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/BRAM/BRAM_592KB_Wrapper.v @@ -0,0 +1,79 @@ +`timescale 1ns / 1ps +/* + * File : BRAM_592KB_Wrapper.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 6-Jun-2012 GEA Initial design. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * Provides access to Block Memory through a 4-way handshaking protocol, + * which allows for multi-cycle and variably-timed operations on the + * data bus. + */ +module BRAM_592KB_Wrapper( + input clock, + input reset, + input rea, + input [3:0] wea, + input [17:0] addra, + input [31:0] dina, + output [31:0] douta, + output reg dreadya, + input reb, + input [3:0] web, + input [17:0] addrb, + input [31:0] dinb, + output [31:0] doutb, + output reg dreadyb + ); + + /* Four-Way Memory Handshake Protocol: + 1. Read/Write request goes high. + 2. Ack goes high when data is available. + 3. Read/Write request goes low. + 4. Ack signal goes low. + ____ + R/W: __| |____ + ____ + Ack: _____| |____ + + */ + + + // Writes require one clock cycle, and reads require 2 or 3 clock cycles (registered output). + // The following logic controls the Ready signal based on these latencies. + reg [1:0] delay_A, delay_B; + + always @(posedge clock) begin + delay_A <= (reset | ~rea) ? 2'b00 : ((delay_A == 2'b10) ? delay_A : delay_A + 1); + delay_B <= (reset | ~reb) ? 2'b00 : ((delay_B == 2'b10) ? delay_B : delay_B + 1); + end + + always @(posedge clock) begin + dreadya <= (reset) ? 0 : ((wea != 4'b0000) || ((delay_A == 2'b10) && rea)) ? 1 : 0; + dreadyb <= (reset) ? 0 : ((web != 4'b0000) || ((delay_B == 2'b10) && reb)) ? 1 : 0; + end + + BRAM_592KB_2R RAM ( + .clka (clock), // input clka + .rsta (reset), // input rsta + .wea (wea), // input [3 : 0] wea + .addra (addra), // input [17 : 0] addra + .dina (dina), // input [31 : 0] dina + .douta (douta), // output [31 : 0] douta + .clkb (clock), // input clkb + .rstb (reset), // input rstb + .web (web), // input [3 : 0] web + .addrb (addrb), // input [17 : 0] addrb + .dinb (dinb), // input [31 : 0] dinb + .doutb (doutb) // output [31 : 0] doutb + ); + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/BRAM/Boot.coe b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/BRAM/Boot.coe new file mode 100755 index 0000000..d649310 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/BRAM/Boot.coe @@ -0,0 +1,1035 @@ +memory_initialization_radix=16; +memory_initialization_vector= +08000022, +00000000, +08000022, +00000000, +3c080000, +25081011, +3c090000, +25291012, +3c1d0009, +27bd4000, +3c1c0001, +279c9010, +11090004, +00000000, +a1000000, +0800000c, +25080001, +3c1a0000, +275a0078, +409af000, +401a6800, +3c1b0080, +035bd025, +409a6800, +401a6000, +3c1b0fff, +377b00ee, +035bd024, +409a6000, +42000018, +0c000024, +00000000, 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diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Clocks/PLL_100MHz_to_33MHz_66MHz.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Clocks/PLL_100MHz_to_33MHz_66MHz.v new file mode 100755 index 0000000..9703612 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Clocks/PLL_100MHz_to_33MHz_66MHz.v @@ -0,0 +1,90 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version : 14.1 +// \ \ Application : xaw2verilog +// / / Filename : PLL_100MHz_to_33MHz_66MHz.v +// /___/ /\ Timestamp : 11/18/2012 13:35:59 +// \ \ / \ +// \___\/\___\ +// +//Command: xaw2verilog -st C:\root\Work\Gauss\delclk\ipcore_dir\.\PLL_100MHz_to_33MHz_66MHz.xaw C:\root\Work\Gauss\delclk\ipcore_dir\.\PLL_100MHz_to_33MHz_66MHz +//Design Name: PLL_100MHz_to_33MHz_66MHz +//Device: xc5vlx110t-1ff1136 +// +// Module PLL_100MHz_to_33MHz_66MHz +// Generated by Xilinx Architecture Wizard +// Written for synthesis tool: XST +// For block PLL_ADV_INST, Estimated PLL Jitter for CLKOUT0 = 0.186 ns +// For block PLL_ADV_INST, Estimated PLL Jitter for CLKOUT1 = 0.162 ns +`timescale 1ns / 1ps + +module PLL_100MHz_to_33MHz_66MHz(CLKIN1_IN, + RST_IN, + CLKOUT0_OUT, + CLKOUT1_OUT, + LOCKED_OUT); + + input CLKIN1_IN; + input RST_IN; + output CLKOUT0_OUT; + output CLKOUT1_OUT; + output LOCKED_OUT; + + wire CLKFBOUT_CLKFBIN; + wire CLKIN1_IBUFG; + wire CLKOUT0_BUF; + wire CLKOUT1_BUF; + wire GND_BIT; + wire [4:0] GND_BUS_5; + wire [15:0] GND_BUS_16; + wire VCC_BIT; + + assign GND_BIT = 0; + assign GND_BUS_5 = 5'b00000; + assign GND_BUS_16 = 16'b0000000000000000; + assign VCC_BIT = 1; + IBUFG CLKIN1_IBUFG_INST (.I(CLKIN1_IN), + .O(CLKIN1_IBUFG)); + BUFG CLKOUT0_BUFG_INST (.I(CLKOUT0_BUF), + .O(CLKOUT0_OUT)); + BUFG CLKOUT1_BUFG_INST (.I(CLKOUT1_BUF), + .O(CLKOUT1_OUT)); + PLL_ADV #( .BANDWIDTH("OPTIMIZED"), .CLKIN1_PERIOD(10.000), + .CLKIN2_PERIOD(10.000), .CLKOUT0_DIVIDE(12), .CLKOUT1_DIVIDE(6), + .CLKOUT0_PHASE(0.000), .CLKOUT1_PHASE(0.000), + .CLKOUT0_DUTY_CYCLE(0.500), .CLKOUT1_DUTY_CYCLE(0.500), + .COMPENSATION("SYSTEM_SYNCHRONOUS"), .DIVCLK_DIVIDE(1), + .CLKFBOUT_MULT(4), .CLKFBOUT_PHASE(0.0), .REF_JITTER(0.005000) ) + PLL_ADV_INST (.CLKFBIN(CLKFBOUT_CLKFBIN), + .CLKINSEL(VCC_BIT), + .CLKIN1(CLKIN1_IBUFG), + .CLKIN2(GND_BIT), + .DADDR(GND_BUS_5[4:0]), + .DCLK(GND_BIT), + .DEN(GND_BIT), + .DI(GND_BUS_16[15:0]), + .DWE(GND_BIT), + .REL(GND_BIT), + .RST(RST_IN), + .CLKFBDCM(), + .CLKFBOUT(CLKFBOUT_CLKFBIN), + .CLKOUTDCM0(), + .CLKOUTDCM1(), + .CLKOUTDCM2(), + .CLKOUTDCM3(), + .CLKOUTDCM4(), + .CLKOUTDCM5(), + .CLKOUT0(CLKOUT0_BUF), + .CLKOUT1(CLKOUT1_BUF), + .CLKOUT2(), + .CLKOUT3(), + .CLKOUT4(), + .CLKOUT5(), + .DO(), + .DRDY(), + .LOCKED(LOCKED_OUT)); +endmodule diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Clocks/PLL_100MHz_to_50MHz_100MHz.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Clocks/PLL_100MHz_to_50MHz_100MHz.v new file mode 100755 index 0000000..0b87740 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Clocks/PLL_100MHz_to_50MHz_100MHz.v @@ -0,0 +1,90 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version : 14.1 +// \ \ Application : xaw2verilog +// / / Filename : pll2.v +// /___/ /\ Timestamp : 06/15/2012 18:19:44 +// \ \ / \ +// \___\/\___\ +// +//Command: xaw2verilog -intstyle C:/root/Work/Gauss/XUM/delz/ipcore_dir/pll2.xaw -st pll2.v +//Design Name: pll2 +//Device: xc5vlx110t-2ff1136 +// +// Module pll2 +// Generated by Xilinx Architecture Wizard +// Written for synthesis tool: XST +// For block PLL_ADV_INST, Estimated PLL Jitter for CLKOUT0 = 0.171 ns +// For block PLL_ADV_INST, Estimated PLL Jitter for CLKOUT1 = 0.149 ns +`timescale 1ns / 1ps + +module PLL_100MHz_to_50MHz_100MHz(CLKIN1_IN, + RST_IN, + CLKOUT0_OUT, + CLKOUT1_OUT, + LOCKED_OUT); + + input CLKIN1_IN; + input RST_IN; + output CLKOUT0_OUT; + output CLKOUT1_OUT; + output LOCKED_OUT; + + wire CLKFBOUT_CLKFBIN; + wire CLKIN1_IBUFG; + wire CLKOUT0_BUF; + wire CLKOUT1_BUF; + wire GND_BIT; + wire [4:0] GND_BUS_5; + wire [15:0] GND_BUS_16; + wire VCC_BIT; + + assign GND_BIT = 0; + assign GND_BUS_5 = 5'b00000; + assign GND_BUS_16 = 16'b0000000000000000; + assign VCC_BIT = 1; + IBUFG CLKIN1_IBUFG_INST (.I(CLKIN1_IN), + .O(CLKIN1_IBUFG)); + BUFG CLKOUT0_BUFG_INST (.I(CLKOUT0_BUF), + .O(CLKOUT0_OUT)); + BUFG CLKOUT1_BUFG_INST (.I(CLKOUT1_BUF), + .O(CLKOUT1_OUT)); + PLL_ADV #( .BANDWIDTH("OPTIMIZED"), .CLKIN1_PERIOD(10.000), + .CLKIN2_PERIOD(10.000), .CLKOUT0_DIVIDE(8), .CLKOUT1_DIVIDE(4), + .CLKOUT0_PHASE(0.000), .CLKOUT1_PHASE(0.000), + .CLKOUT0_DUTY_CYCLE(0.500), .CLKOUT1_DUTY_CYCLE(0.500), + .COMPENSATION("SYSTEM_SYNCHRONOUS"), .DIVCLK_DIVIDE(1), + .CLKFBOUT_MULT(4), .CLKFBOUT_PHASE(0.0), .REF_JITTER(0.005000) ) + PLL_ADV_INST (.CLKFBIN(CLKFBOUT_CLKFBIN), + .CLKINSEL(VCC_BIT), + .CLKIN1(CLKIN1_IBUFG), + .CLKIN2(GND_BIT), + .DADDR(GND_BUS_5[4:0]), + .DCLK(GND_BIT), + .DEN(GND_BIT), + .DI(GND_BUS_16[15:0]), + .DWE(GND_BIT), + .REL(GND_BIT), + .RST(RST_IN), + .CLKFBDCM(), + .CLKFBOUT(CLKFBOUT_CLKFBIN), + .CLKOUTDCM0(), + .CLKOUTDCM1(), + .CLKOUTDCM2(), + .CLKOUTDCM3(), + .CLKOUTDCM4(), + .CLKOUTDCM5(), + .CLKOUT0(CLKOUT0_BUF), + .CLKOUT1(CLKOUT1_BUF), + .CLKOUT2(), + .CLKOUT3(), + .CLKOUT4(), + .CLKOUT5(), + .DO(), + .DRDY(), + .LOCKED(LOCKED_OUT)); +endmodule diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Clocks/PLL_100MHz_to_50MHz_100MHz_66MHz.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Clocks/PLL_100MHz_to_50MHz_100MHz_66MHz.v new file mode 100755 index 0000000..a2ea8c6 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Clocks/PLL_100MHz_to_50MHz_100MHz_66MHz.v @@ -0,0 +1,97 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version : 14.1 +// \ \ Application : xaw2verilog +// / / Filename : pl3.v +// /___/ /\ Timestamp : 06/15/2012 18:39:50 +// \ \ / \ +// \___\/\___\ +// +//Command: xaw2verilog -intstyle C:/root/Work/Gauss/XUM/delz/ipcore_dir/pl3.xaw -st pl3.v +//Design Name: pl3 +//Device: xc5vlx110t-2ff1136 +// +// Module pl3 +// Generated by Xilinx Architecture Wizard +// Written for synthesis tool: XST +// For block PLL_ADV_INST, Estimated PLL Jitter for CLKOUT0 = 0.171 ns +// For block PLL_ADV_INST, Estimated PLL Jitter for CLKOUT1 = 0.149 ns +// For block PLL_ADV_INST, Estimated PLL Jitter for CLKOUT2 = 0.162 ns +`timescale 1ns / 1ps + +module PLL_100MHz_to_50MHz_100MHz_66MHz(CLKIN1_IN, + RST_IN, + CLKOUT0_OUT, + CLKOUT1_OUT, + CLKOUT2_OUT, + LOCKED_OUT); + + input CLKIN1_IN; + input RST_IN; + output CLKOUT0_OUT; + output CLKOUT1_OUT; + output CLKOUT2_OUT; + output LOCKED_OUT; + + wire CLKFBOUT_CLKFBIN; + wire CLKIN1_IBUFG; + wire CLKOUT0_BUF; + wire CLKOUT1_BUF; + wire CLKOUT2_BUF; + wire GND_BIT; + wire [4:0] GND_BUS_5; + wire [15:0] GND_BUS_16; + wire VCC_BIT; + + assign GND_BIT = 0; + assign GND_BUS_5 = 5'b00000; + assign GND_BUS_16 = 16'b0000000000000000; + assign VCC_BIT = 1; + IBUFG CLKIN1_IBUFG_INST (.I(CLKIN1_IN), + .O(CLKIN1_IBUFG)); + BUFG CLKOUT0_BUFG_INST (.I(CLKOUT0_BUF), + .O(CLKOUT0_OUT)); + BUFG CLKOUT1_BUFG_INST (.I(CLKOUT1_BUF), + .O(CLKOUT1_OUT)); + BUFG CLKOUT2_BUFG_INST (.I(CLKOUT2_BUF), + .O(CLKOUT2_OUT)); + PLL_ADV #( .BANDWIDTH("OPTIMIZED"), .CLKIN1_PERIOD(10.000), + .CLKIN2_PERIOD(10.000), .CLKOUT0_DIVIDE(8), .CLKOUT1_DIVIDE(4), + .CLKOUT2_DIVIDE(6), .CLKOUT0_PHASE(0.000), .CLKOUT1_PHASE(0.000), + .CLKOUT2_PHASE(0.000), .CLKOUT0_DUTY_CYCLE(0.500), + .CLKOUT1_DUTY_CYCLE(0.500), .CLKOUT2_DUTY_CYCLE(0.500), + .COMPENSATION("SYSTEM_SYNCHRONOUS"), .DIVCLK_DIVIDE(1), + .CLKFBOUT_MULT(4), .CLKFBOUT_PHASE(0.0), .REF_JITTER(0.005000) ) + PLL_ADV_INST (.CLKFBIN(CLKFBOUT_CLKFBIN), + .CLKINSEL(VCC_BIT), + .CLKIN1(CLKIN1_IBUFG), + .CLKIN2(GND_BIT), + .DADDR(GND_BUS_5[4:0]), + .DCLK(GND_BIT), + .DEN(GND_BIT), + .DI(GND_BUS_16[15:0]), + .DWE(GND_BIT), + .REL(GND_BIT), + .RST(RST_IN), + .CLKFBDCM(), + .CLKFBOUT(CLKFBOUT_CLKFBIN), + .CLKOUTDCM0(), + .CLKOUTDCM1(), + .CLKOUTDCM2(), + .CLKOUTDCM3(), + .CLKOUTDCM4(), + .CLKOUTDCM5(), + .CLKOUT0(CLKOUT0_BUF), + .CLKOUT1(CLKOUT1_BUF), + .CLKOUT2(CLKOUT2_BUF), + .CLKOUT3(), + .CLKOUT4(), + .CLKOUT5(), + .DO(), + .DRDY(), + .LOCKED(LOCKED_OUT)); +endmodule diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Clocks/PLL_100MHz_to_66MHz.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Clocks/PLL_100MHz_to_66MHz.v new file mode 100755 index 0000000..dc7348a --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Clocks/PLL_100MHz_to_66MHz.v @@ -0,0 +1,82 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version : 14.1 +// \ \ Application : xaw2verilog +// / / Filename : clk3.v +// /___/ /\ Timestamp : 06/06/2012 16:09:06 +// \ \ / \ +// \___\/\___\ +// +//Command: xaw2verilog -intstyle C:/root/Work/Gauss/XUM/del/ipcore_dir/clk3.xaw -st clk3.v +//Design Name: clk3 +//Device: xc5vlx110t-ff1136-2 +// +// Module clk3 +// Generated by Xilinx Architecture Wizard +// Written for synthesis tool: XST +// For block PLL_ADV_INST, Estimated PLL Jitter for CLKOUT0 = 0.162 ns +`timescale 1ns / 1ps + +module PLL_100MHz_to_66MHz(CLKIN1_IN, + RST_IN, + CLKOUT0_OUT, + LOCKED_OUT); + + input CLKIN1_IN; + input RST_IN; + output CLKOUT0_OUT; + output LOCKED_OUT; + + wire CLKFBOUT_CLKFBIN; + wire CLKIN1_IBUFG; + wire CLKOUT0_BUF; + wire GND_BIT; + wire [4:0] GND_BUS_5; + wire [15:0] GND_BUS_16; + wire VCC_BIT; + + assign GND_BIT = 0; + assign GND_BUS_5 = 5'b00000; + assign GND_BUS_16 = 16'b0000000000000000; + assign VCC_BIT = 1; + IBUFG CLKIN1_IBUFG_INST (.I(CLKIN1_IN), + .O(CLKIN1_IBUFG)); + BUFG CLKOUT0_BUFG_INST (.I(CLKOUT0_BUF), + .O(CLKOUT0_OUT)); + PLL_ADV #( .BANDWIDTH("OPTIMIZED"), .CLKIN1_PERIOD(10.000), + .CLKIN2_PERIOD(10.000), .CLKOUT0_DIVIDE(6), .CLKOUT0_PHASE(0.000), + .CLKOUT0_DUTY_CYCLE(0.500), .COMPENSATION("SYSTEM_SYNCHRONOUS"), + .DIVCLK_DIVIDE(1), .CLKFBOUT_MULT(4), .CLKFBOUT_PHASE(0.0), + .REF_JITTER(0.005000) ) PLL_ADV_INST (.CLKFBIN(CLKFBOUT_CLKFBIN), + .CLKINSEL(VCC_BIT), + .CLKIN1(CLKIN1_IBUFG), + .CLKIN2(GND_BIT), + .DADDR(GND_BUS_5[4:0]), + .DCLK(GND_BIT), + .DEN(GND_BIT), + .DI(GND_BUS_16[15:0]), + .DWE(GND_BIT), + .REL(GND_BIT), + .RST(RST_IN), + .CLKFBDCM(), + .CLKFBOUT(CLKFBOUT_CLKFBIN), + .CLKOUTDCM0(), + .CLKOUTDCM1(), + .CLKOUTDCM2(), + .CLKOUTDCM3(), + .CLKOUTDCM4(), + .CLKOUTDCM5(), + .CLKOUT0(CLKOUT0_BUF), + .CLKOUT1(), + .CLKOUT2(), + .CLKOUT3(), + .CLKOUT4(), + .CLKOUT5(), + .DO(), + .DRDY(), + .LOCKED(LOCKED_OUT)); +endmodule diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Clocks/PLL_100MHz_to_66MHz_133MHz.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Clocks/PLL_100MHz_to_66MHz_133MHz.v new file mode 100755 index 0000000..6d8d3c9 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Clocks/PLL_100MHz_to_66MHz_133MHz.v @@ -0,0 +1,90 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version : 14.1 +// \ \ Application : xaw2verilog +// / / Filename : PLL2.v +// /___/ /\ Timestamp : 06/07/2012 10:56:40 +// \ \ / \ +// \___\/\___\ +// +//Command: xaw2verilog -intstyle C:/root/Work/Gauss/XUM/del2/ipcore_dir/PLL2.xaw -st PLL2.v +//Design Name: PLL2 +//Device: xc5vlx110t-ff1136-2 +// +// Module PLL2 +// Generated by Xilinx Architecture Wizard +// Written for synthesis tool: XST +// For block PLL_ADV_INST, Estimated PLL Jitter for CLKOUT0 = 0.162 ns +// For block PLL_ADV_INST, Estimated PLL Jitter for CLKOUT1 = 0.141 ns +`timescale 1ns / 1ps + +module PLL_100MHz_to_66MHz_133MHz(CLKIN1_IN, + RST_IN, + CLKOUT0_OUT, + CLKOUT1_OUT, + LOCKED_OUT); + + input CLKIN1_IN; + input RST_IN; + output CLKOUT0_OUT; + output CLKOUT1_OUT; + output LOCKED_OUT; + + wire CLKFBOUT_CLKFBIN; + wire CLKIN1_IBUFG; + wire CLKOUT0_BUF; + wire CLKOUT1_BUF; + wire GND_BIT; + wire [4:0] GND_BUS_5; + wire [15:0] GND_BUS_16; + wire VCC_BIT; + + assign GND_BIT = 0; + assign GND_BUS_5 = 5'b00000; + assign GND_BUS_16 = 16'b0000000000000000; + assign VCC_BIT = 1; + IBUFG CLKIN1_IBUFG_INST (.I(CLKIN1_IN), + .O(CLKIN1_IBUFG)); + BUFG CLKOUT0_BUFG_INST (.I(CLKOUT0_BUF), + .O(CLKOUT0_OUT)); + BUFG CLKOUT1_BUFG_INST (.I(CLKOUT1_BUF), + .O(CLKOUT1_OUT)); + PLL_ADV #( .BANDWIDTH("OPTIMIZED"), .CLKIN1_PERIOD(10.000), + .CLKIN2_PERIOD(10.000), .CLKOUT0_DIVIDE(6), .CLKOUT1_DIVIDE(3), + .CLKOUT0_PHASE(0.000), .CLKOUT1_PHASE(0.000), + .CLKOUT0_DUTY_CYCLE(0.500), .CLKOUT1_DUTY_CYCLE(0.500), + .COMPENSATION("SYSTEM_SYNCHRONOUS"), .DIVCLK_DIVIDE(1), + .CLKFBOUT_MULT(4), .CLKFBOUT_PHASE(0.0), .REF_JITTER(0.005000) ) + PLL_ADV_INST (.CLKFBIN(CLKFBOUT_CLKFBIN), + .CLKINSEL(VCC_BIT), + .CLKIN1(CLKIN1_IBUFG), + .CLKIN2(GND_BIT), + .DADDR(GND_BUS_5[4:0]), + .DCLK(GND_BIT), + .DEN(GND_BIT), + .DI(GND_BUS_16[15:0]), + .DWE(GND_BIT), + .REL(GND_BIT), + .RST(RST_IN), + .CLKFBDCM(), + .CLKFBOUT(CLKFBOUT_CLKFBIN), + .CLKOUTDCM0(), + .CLKOUTDCM1(), + .CLKOUTDCM2(), + .CLKOUTDCM3(), + .CLKOUTDCM4(), + .CLKOUTDCM5(), + .CLKOUT0(CLKOUT0_BUF), + .CLKOUT1(CLKOUT1_BUF), + .CLKOUT2(), + .CLKOUT3(), + .CLKOUT4(), + .CLKOUT5(), + .DO(), + .DRDY(), + .LOCKED(LOCKED_OUT)); +endmodule diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Clocks/PLL_100MHz_to_66MHz_133MHz_266MHz.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Clocks/PLL_100MHz_to_66MHz_133MHz_266MHz.v new file mode 100755 index 0000000..188f67d --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Clocks/PLL_100MHz_to_66MHz_133MHz_266MHz.v @@ -0,0 +1,95 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version : 14.1 +// \ \ Application : xaw2verilog +// / / Filename : pll.v +// /___/ /\ Timestamp : 06/12/2012 10:24:28 +// \ \ / \ +// \___\/\___\ +// +//Command: xaw2verilog -intstyle C:/root/Work/Gauss/XUM/delz/ipcore_dir/pll.xaw -st pll.v +//Design Name: pll +//Device: xc5vlx110t-ff1136-2 +// +// Module pll +// Generated by Xilinx Architecture Wizard +// Written for synthesis tool: XST +// For block PLL_ADV_INST, Estimated PLL Jitter for CLKOUT0 = 0.174 ns +// For block PLL_ADV_INST, Estimated PLL Jitter for CLKOUT1 = 0.152 ns +// For block PLL_ADV_INST, Estimated PLL Jitter for CLKOUT2 = 0.133 ns +`timescale 1ns / 1ps + +module PLL_100MHz_to_66MHz_133MHz_266MHz(CLKIN1_IN, + CLKOUT0_OUT, + CLKOUT1_OUT, + CLKOUT2_OUT, + LOCKED_OUT); + + input CLKIN1_IN; + output CLKOUT0_OUT; + output CLKOUT1_OUT; + output CLKOUT2_OUT; + output LOCKED_OUT; + + wire CLKFBOUT_CLKFBIN; + wire CLKIN1_IBUFG; + wire CLKOUT0_BUF; + wire CLKOUT1_BUF; + wire CLKOUT2_BUF; + wire GND_BIT; + wire [4:0] GND_BUS_5; + wire [15:0] GND_BUS_16; + wire VCC_BIT; + + assign GND_BIT = 0; + assign GND_BUS_5 = 5'b00000; + assign GND_BUS_16 = 16'b0000000000000000; + assign VCC_BIT = 1; + IBUFG CLKIN1_IBUFG_INST (.I(CLKIN1_IN), + .O(CLKIN1_IBUFG)); + BUFG CLKOUT0_BUFG_INST (.I(CLKOUT0_BUF), + .O(CLKOUT0_OUT)); + BUFG CLKOUT1_BUFG_INST (.I(CLKOUT1_BUF), + .O(CLKOUT1_OUT)); + BUFG CLKOUT2_BUFG_INST (.I(CLKOUT2_BUF), + .O(CLKOUT2_OUT)); + PLL_ADV #( .BANDWIDTH("OPTIMIZED"), .CLKIN1_PERIOD(10.000), + .CLKIN2_PERIOD(10.000), .CLKOUT0_DIVIDE(12), .CLKOUT1_DIVIDE(6), + .CLKOUT2_DIVIDE(3), .CLKOUT0_PHASE(0.000), .CLKOUT1_PHASE(0.000), + .CLKOUT2_PHASE(0.000), .CLKOUT0_DUTY_CYCLE(0.500), + .CLKOUT1_DUTY_CYCLE(0.500), .CLKOUT2_DUTY_CYCLE(0.500), + .COMPENSATION("SYSTEM_SYNCHRONOUS"), .DIVCLK_DIVIDE(1), + .CLKFBOUT_MULT(8), .CLKFBOUT_PHASE(0.0), .REF_JITTER(0.005000) ) + PLL_ADV_INST (.CLKFBIN(CLKFBOUT_CLKFBIN), + .CLKINSEL(VCC_BIT), + .CLKIN1(CLKIN1_IBUFG), + .CLKIN2(GND_BIT), + .DADDR(GND_BUS_5[4:0]), + .DCLK(GND_BIT), + .DEN(GND_BIT), + .DI(GND_BUS_16[15:0]), + .DWE(GND_BIT), + .REL(GND_BIT), + .RST(GND_BIT), + .CLKFBDCM(), + .CLKFBOUT(CLKFBOUT_CLKFBIN), + .CLKOUTDCM0(), + .CLKOUTDCM1(), + .CLKOUTDCM2(), + .CLKOUTDCM3(), + .CLKOUTDCM4(), + .CLKOUTDCM5(), + .CLKOUT0(CLKOUT0_BUF), + .CLKOUT1(CLKOUT1_BUF), + .CLKOUT2(CLKOUT2_BUF), + .CLKOUT3(), + .CLKOUT4(), + .CLKOUT5(), + .DO(), + .DRDY(), + .LOCKED(LOCKED_OUT)); +endmodule diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Common/Decoder_2to4.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Common/Decoder_2to4.v new file mode 100755 index 0000000..4f3845b --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Common/Decoder_2to4.v @@ -0,0 +1,39 @@ +`timescale 1ns / 1ps +/* + * File : Decoder_2to4.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 14-Aug-2012 GEA Initial design. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * A simple 2-to-4 line single bit decoder. Accepts a two bit number + * and sets one of four outputs high based on that number. + * + * Mapping: + * 00 -> 0001 + * 01 -> 0010 + * 10 -> 0100 + * 11 -> 1000 + */ +module Decoder_2to4( + input [1:0] A, + output reg [3:0] B + ); + + always @(A) begin + case (A) + 2'd0 : B <= 4'b0001; + 2'd1 : B <= 4'b0010; + 2'd2 : B <= 4'b0100; + 2'd3 : B <= 4'b1000; + endcase + end + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Common/FIFO.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Common/FIFO.v new file mode 100755 index 0000000..e749dd1 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Common/FIFO.v @@ -0,0 +1,80 @@ +`timescale 1ns / 1ps +/* + * File : FIFO.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 4-Apr-2010 GEA Initial design. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * A synchronous FIFO of variable data width and depth. 'enQ' is ignored when + * the FIFO is full and 'deQ' is ignored when the FIFO is empty. If 'enQ' and + * 'deQ' are asserted simultaneously, the FIFO is unchanged and the output data + * is the same as the input data. + * + * This FIFO is "First word fall-through" meaning data can be read without + * asserting 'deQ' by merely supplying an address. However, when 'deQ' is + * asserted, the data is "removed" from the FIFO and one location is freed. + * If the FIFO is empty and 'enQ' and 'deQ' are not asserted simultaneously, + * the output data will be 0s. + * + * Variation: + * - None. This is the basic FIFO module. + */ +module FIFO(clock, reset, clear, enQ, deQ, data_in, data_out, empty, full); + parameter DATA_WIDTH = 8; + parameter ADDR_WIDTH = 8; + parameter RAM_DEPTH = 1 << ADDR_WIDTH; + input clock; + input reset; + input enQ; + input deQ; + input [(DATA_WIDTH-1):0] data_in; + output [(DATA_WIDTH-1):0] data_out; + output empty; + output full; + + reg [(ADDR_WIDTH-1):0] enQ_ptr, deQ_ptr; // Addresses for reading from and writing to internal memory + reg [(ADDR_WIDTH):0] count; // How many elements are in the FIFO (0->256) + assign empty = (count == 0); + assign full = (count == (1 << ADDR_WIDTH)); + + wire [(DATA_WIDTH-1):0] w_data_out; + assign data_out = (empty) ? ((enQ & deQ) ? data_in : 0) : w_data_out; + + wire w_enQ = (full) ? 0 : enQ; // Mask 'enQ' when the FIFO is full + wire w_deQ = (empty) ? 0 : deQ; // Mask 'deQ' when the FIFO is empty + + always @(posedge clock) begin + if (reset) begin + enQ_ptr <= 0; + deQ_ptr <= 0; + count <= 0; + end + else begin + enQ_ptr <= (w_enQ) ? enQ_ptr +1 : enQ_ptr; + deQ_ptr <= (w_deQ) ? deQ_ptr +1 : deQ_ptr; + count <= (w_enQ ~^ w_deQ) ? count : ((w_enQ) ? count +1 : count -1); + end + end + + SRAM #( + .DATA_WIDTH (DATA_WIDTH), + .ADDR_WIDTH (ADDR_WIDTH), + .RAM_DEPTH (RAM_DEPTH)) + RAM( + .clock (clock), + .wEn (w_enQ), + .rAddr (deQ_ptr), + .wAddr (enQ_ptr), + .dIn (data_in), + .dOut (w_data_out) + ); + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Common/FIFO_Clear.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Common/FIFO_Clear.v new file mode 100755 index 0000000..326c467 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Common/FIFO_Clear.v @@ -0,0 +1,81 @@ +`timescale 1ns / 1ps +/* + * File : FIFO_Clear.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 4-Apr-2010 GEA Initial design. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * A synchronous FIFO of variable data width and depth. 'enQ' is ignored when + * the FIFO is full and 'deQ' is ignored when the FIFO is empty. If 'enQ' and + * 'deQ' are asserted simultaneously, the FIFO is unchanged and the output data + * is the same as the input data. + * + * This FIFO is "First word fall-through" meaning data can be read without + * asserting 'deQ' by merely supplying an address. However, when 'deQ' is + * asserted, the data is "removed" from the FIFO and one location is freed. + * If the FIFO is empty and 'enQ' and 'deQ' are not asserted simultaneously, + * the output data will be 0s. + * + * Variation: + * - Input 'clear' empties the FIFO exactly like 'reset' does. + */ +module FIFO_Clear(clock, reset, clear, enQ, deQ, data_in, data_out, empty, full); + parameter DATA_WIDTH = 8; + parameter ADDR_WIDTH = 8; + parameter RAM_DEPTH = 1 << ADDR_WIDTH; + input clock; + input reset; + input clear; + input enQ; + input deQ; + input [(DATA_WIDTH-1):0] data_in; + output [(DATA_WIDTH-1):0] data_out; + output empty; + output full; + + reg [(ADDR_WIDTH-1):0] enQ_ptr, deQ_ptr; // Addresses for reading from and writing to internal memory + reg [(ADDR_WIDTH):0] count; // How many elements are in the FIFO (0->256) + assign empty = (count == 0); + assign full = (count == (1 << ADDR_WIDTH)); + + wire [(DATA_WIDTH-1):0] w_data_out; + assign data_out = (empty) ? ((enQ & deQ) ? data_in : 0) : w_data_out; + + wire w_enQ = (full) ? 0 : enQ; // Mask 'enQ' when the FIFO is full + wire w_deQ = (empty) ? 0 : deQ; // Mask 'deQ' when the FIFO is empty + + always @(posedge clock) begin + if (reset | clear) begin + enQ_ptr <= 0; + deQ_ptr <= 0; + count <= 0; + end + else begin + enQ_ptr <= (w_enQ) ? enQ_ptr +1 : enQ_ptr; + deQ_ptr <= (w_deQ) ? deQ_ptr +1 : deQ_ptr; + count <= (w_enQ ~^ w_deQ) ? count : ((w_enQ) ? count +1 : count -1); + end + end + + SRAM #( + .DATA_WIDTH (DATA_WIDTH), + .ADDR_WIDTH (ADDR_WIDTH), + .RAM_DEPTH (RAM_DEPTH)) + RAM( + .clock (clock), + .wEn (w_enQ), + .rAddr (deQ_ptr), + .wAddr (enQ_ptr), + .dIn (data_in), + .dOut (w_data_out) + ); + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Common/FIFO_NoFull_Count.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Common/FIFO_NoFull_Count.v new file mode 100755 index 0000000..3647418 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Common/FIFO_NoFull_Count.v @@ -0,0 +1,82 @@ +`timescale 1ns / 1ps +/* + * File : FIFO_NoFull_Count.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 24-May-2010 GEA Initial design. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * A synchronous FIFO of variable data width and depth. 'enQ' is ignored when + * the FIFO is full and 'deQ' is ignored when the FIFO is empty. If 'enQ' and + * 'deQ' are asserted simultaneously, the FIFO is unchanged and the output data + * is the same as the input data. + * + * This FIFO is "First word fall-through" meaning data can be read without + * asserting 'deQ' by merely supplying an address. However, when 'deQ' is + * asserted, the data is "removed" from the FIFO and one location is freed. + * If the FIFO is empty and 'enQ' and 'deQ' are not asserted simultaneously, + * the output data will be 0s. + * + * Variation: + * - There is no output to indicate the FIFO is full. + * - Output 'count' indicates how many elements are in the FIFO, from 0 to 256 + * (for 8-bit ADDR_WIDTH). + */ +module FIFO_NoFull_Count(clock, reset, enQ, deQ, data_in, data_out, empty, count); + parameter DATA_WIDTH = 8; + parameter ADDR_WIDTH = 8; + parameter RAM_DEPTH = 1 << ADDR_WIDTH; + input clock; + input reset; + input enQ; + input deQ; + input [(DATA_WIDTH-1):0] data_in; + output [(DATA_WIDTH-1):0] data_out; + output empty; + output reg [(ADDR_WIDTH):0] count; // How many elements are in the FIFO (0->256) + + reg [(ADDR_WIDTH-1):0] enQ_ptr, deQ_ptr; // Addresses for reading from and writing to internal memory + + assign empty = (count == 0); + wire full = (count == (1 << ADDR_WIDTH)); + + wire [(DATA_WIDTH-1):0] w_data_out; + assign data_out = (empty) ? ((enQ & deQ) ? data_in : 0) : w_data_out; + + wire w_enQ = (full) ? 0 : enQ; // Mask 'enQ' when the FIFO is full + wire w_deQ = (empty) ? 0 : deQ; // Mask 'deQ' when the FIFO is empty + + always @(posedge clock) begin + if (reset) begin + enQ_ptr <= 0; + deQ_ptr <= 0; + count <= 0; + end + else begin + enQ_ptr <= (w_enQ) ? enQ_ptr +1 : enQ_ptr; + deQ_ptr <= (w_deQ) ? deQ_ptr +1 : deQ_ptr; + count <= (w_enQ ~^ w_deQ) ? count : ((w_enQ) ? count +1 : count -1); + end + end + + SRAM #( + .DATA_WIDTH (DATA_WIDTH), + .ADDR_WIDTH (ADDR_WIDTH), + .RAM_DEPTH (RAM_DEPTH)) + ram( + .clock (clock), + .wEn (w_enQ), + .rAddr (deQ_ptr), + .wAddr (enQ_ptr), + .dIn (data_in), + .dOut (w_data_out) + ); + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Common/Mux2.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Common/Mux2.v new file mode 100755 index 0000000..a2eb1d8 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Common/Mux2.v @@ -0,0 +1,26 @@ +`timescale 1ns / 1ps +/* + * File : Mux2.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 7-Jun-2011 GEA Initial design. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * A 2-input Mux of variable width, defaulting to 32-bit width. + */ +module Mux2 #(parameter WIDTH = 32)( + input sel, + input [(WIDTH-1):0] in0, in1, + output [(WIDTH-1):0] out + ); + + assign out = (sel) ? in1 : in0; + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Common/Mux4.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Common/Mux4.v new file mode 100755 index 0000000..38083f3 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Common/Mux4.v @@ -0,0 +1,33 @@ +`timescale 1ns / 1ps +/* + * File : Mux4.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 7-Jun-2011 GEA Initial design. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * A 4-input Mux of variable width, defaulting to 32-bit width. + */ +module Mux4 #(parameter WIDTH = 32)( + input [1:0] sel, + input [(WIDTH-1):0] in0, in1, in2, in3, + output reg [(WIDTH-1):0] out + ); + + always @(*) begin + case (sel) + 2'b00 : out <= in0; + 2'b01 : out <= in1; + 2'b10 : out <= in2; + 2'b11 : out <= in3; + endcase + end + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Common/SRAM.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Common/SRAM.v new file mode 100755 index 0000000..0cd433c --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Common/SRAM.v @@ -0,0 +1,38 @@ +`timescale 1ns / 1ps +/* + * File : SRAM.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 4-Apr-2010 GEA Initial design. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * A simple memory of varying width and depth. Reads are asynchronous, + * writes are synchronous. Defaults to 8-bit width and 8-bit depth for + * a total of 8-bit * 256 entry or 256 bytes of storage. + */ +module SRAM(clock, wEn, rAddr, wAddr, dIn, dOut); + parameter DATA_WIDTH = 8; + parameter ADDR_WIDTH = 8; + parameter RAM_DEPTH = 1 << ADDR_WIDTH; + input clock; + input wEn; + input [(ADDR_WIDTH-1):0] rAddr; + input [(ADDR_WIDTH-1):0] wAddr; + input [(DATA_WIDTH-1):0] dIn; + output [(DATA_WIDTH-1):0] dOut; + + reg [(DATA_WIDTH-1):0] mem [0:(RAM_DEPTH-1)]; + assign dOut = mem[rAddr]; + + always @(posedge clock) begin + if (wEn) mem[wAddr] <= dIn; + end + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/I2C/I2C_Clock.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/I2C/I2C_Clock.v new file mode 100755 index 0000000..a1ad581 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/I2C/I2C_Clock.v @@ -0,0 +1,55 @@ +`timescale 1ns / 1ps +/* + * File : I2C_Clock.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 21-Jun-2012 GEA Initial design. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * Generates a 100 kHz clock signal and an indicator which pulses + * in the middle of the high and low periods of the clock. + */ +module I2C_Clock( + input clock, // 100 (66) MHz + input reset, + inout scl, // A 100 (66) kHz clock + output scl_tick_90 // A pulse indicating the middle of the +/- scl levels + ); + + reg [7:0] count_4x; + + + always @(posedge clock) begin + //count_4x <= (reset) ? 8'h00 : (scl) ? count_4x + 1 : count_4x; + count_4x <= (reset) ? 8'h00 : count_4x + 1; // XXX SIMULATION ONLY + end + + // A single pulse once every 250 cycles + wire tick_4x = (count_4x == 8'hFA); + + reg [1:0] state; + always @(posedge clock) begin + if (reset) begin + state <= 2'b00; + end + else begin + case (state) + 2'd0 : state <= (tick_4x) ? 2'd1 : 2'd0; + 2'd1 : state <= (tick_4x) ? 2'd2 : 2'd1; + 2'd2 : state <= (tick_4x) ? 2'd3 : 2'd2; + 2'd3 : state <= (tick_4x) ? 2'd0 : 2'd3; + endcase + end + end + + assign scl = ((state == 2'd0) || (state == 2'd1)); + assign scl_tick_90 = tick_4x & ((state == 2'd0) || (state == 2'd2)); + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/I2C/I2C_Controller.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/I2C/I2C_Controller.v new file mode 100755 index 0000000..34d6d36 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/I2C/I2C_Controller.v @@ -0,0 +1,98 @@ +`timescale 1ns / 1ps +/* + * File : I2C_Controller.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 25-Jun-2012 GEA Initial design. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * A top-level I2C controller which bridges the I2C physical layer with + * the data memory bus. This controller accepts the following commands: + * + * Clear : [Bit 8] Empties the I2C FIFO of all data. + * EnQ : [Bit 9] Enqueues a byte of data to the FIFO for transmission. + * Tx : [Bit 10] Transmits all bytes within the FIFO. + * Rx : [Bit 11] Transmits the first byte in the FIFO (bus address), + * then receives a requested number of bytes into the FIFO. + * RxN : [Bit 12] Sets the number of bytes to receive on an 'Rx' command. + * + * To read data from the FIFO, the data memory bus issues a Read command. The received + * data is arranged as follows: + * + * Bit 10 : 'Nack' which indicates if the last Tx/Rx command did not receive + * an acknowledgment from the slave device. + * Bit 9 : Indicates if the FIFO is currently full. + * Bit 8 : Indicates if the FIFO is currently empty. + * Bit 7-0 : The first byte in the FIFO. + */ +module I2C_Controller( + input clock, + input reset, + input Read, + input Write, + input [12:0] DataIn, + output [10:0] DataOut, + output Ack, + + inout i2c_scl, + inout i2c_sda + ); + + // I2C Physical layer signals + wire I2C_Read, I2C_Write; + wire I2C_ReadCountSet; + wire I2C_EnQ, I2C_DeQ, I2C_Clear; + wire [7:0] I2C_DataIn, I2C_DataOut; + wire I2C_Ack, I2C_Nack; + wire I2C_FifoEmpty, I2C_FifoFull; + + + wire Cmd_Clear = DataIn[8]; + wire Cmd_EnQ = DataIn[9]; + wire Cmd_Tx = DataIn[10]; + wire Cmd_Rx = DataIn[11]; + wire Cmd_RxN = DataIn[12]; + + + assign I2C_Read = Write & Cmd_Rx; + assign I2C_Write = Write & Cmd_Tx; + assign I2C_ReadCountSet = Write & Cmd_RxN; + assign I2C_EnQ = Write & Cmd_EnQ; + assign I2C_DeQ = Read; + assign I2C_Clear = Write & Cmd_Clear; + assign I2C_DataIn = DataIn[7:0]; + assign DataOut[7:0] = I2C_DataOut; + assign DataOut[8] = I2C_FifoEmpty; + assign DataOut[9] = I2C_FifoFull; + assign DataOut[10] = I2C_Nack; + assign Ack = I2C_Ack; + + + // I2C Physical layer + I2C_Phy PHY ( + .clock (clock), + .reset (reset), + .Read (I2C_Read), + .Write (I2C_Write), + .ReadCountSet (I2C_ReadCountSet), + .EnQ (I2C_EnQ), + .DeQ (I2C_DeQ), + .Clear (I2C_Clear), + .DataIn (I2C_DataIn), + .DataOut (I2C_DataOut), + .Ack (I2C_Ack), + .Nack (I2C_Nack), + .Fifo_Empty (I2C_FifoEmpty), + .Fifo_Full (I2C_FifoFull), + .i2c_scl (i2c_scl), + .i2c_sda (i2c_sda) + ); + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/I2C/I2C_Phy.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/I2C/I2C_Phy.v new file mode 100755 index 0000000..c60f9a6 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/I2C/I2C_Phy.v @@ -0,0 +1,237 @@ +`timescale 1ns / 1ps +/* + * File : I2C_Phy.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 25-Jun-2012 GEA Initial design. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * I2C Master controller made for a single-master I2C bus. + * Uses a FIFO to store transmit and receive data, and is made + * to be generic enough to use with a wide variety of I2C slave devices. + * A Read command sends a bus address byte then receives a requested number + * of bytes, while a Write command writes all bytes that are presently in + * the FIFO. + */ + +module I2C_Phy( + input clock, + input reset, + input Read, + input Write, + input ReadCountSet, + input EnQ, + input DeQ, + input Clear, + input [7:0] DataIn, + output reg [7:0] DataOut, + output Ack, + output reg Nack, + output Fifo_Empty, + output Fifo_Full, + inout i2c_scl, + inout i2c_sda + ); + + localparam [5:0] IDLE=0, ENQ=1, DEQ=2, START=3, ADDR6=4, ADDR5=5, ADDR4=6, ADDR3=7, ADDR2=8, + ADDR1=9, ADDR0=10, RWBIT=11, A_DEQ=12, A_ACK=13, WDWAIT=14, WDATA7=15, + WDATA6=16, WDATA5=17, WDATA4=18, WDATA3=19, WDATA2=20, WDATA1=21, WDATA0=22, + W_DEQ=23, W_ACK=24, RDATA7=25, RDATA6=26, RDATA5=27, RDATA4=28, RDATA3=29, + RDATA2=30, RDATA1=31, RDATA0=32, R_ENQ=33, R_ACKW=34, R_ACK=35, NACK=36, + STOPW=37, STOP=38, BUSW=39, CLEAR=40, RNSET=41; + + // FIFO signals + wire Fifo_Clear, Fifo_EnQ, Fifo_DeQ; + wire [7:0] Fifo_In, Fifo_Out; + + wire scl, scl_tick_90; + reg [5:0] state; + reg [7:0] Rx_Data; + reg sda; + reg [7:0] Rx_Todo, Rx_Remain; + + // The I2C bus is high-impedance instead of a driven 1. + assign i2c_sda = (sda) ? 1'bz : 1'b0; + assign i2c_scl = (scl | (state == IDLE)) ? 1'bz : 1'b0; + + // Control logic : 4-way handshaking + assign Ack = (state == BUSW); + + always @(posedge clock) begin + Rx_Todo <= (reset) ? 8'h00 : ((state == RNSET) ? DataIn : Rx_Todo); + Rx_Remain <= (reset) ? 8'h00 : ((state == IDLE) ? Rx_Todo : ((state == R_ENQ) ? Rx_Remain - 1 : Rx_Remain)); + end + + always @(posedge clock) begin + DataOut <= (reset) ? 8'h00 : ((state == DEQ) ? Fifo_Out : DataOut); + end + + always @(posedge clock) begin + Nack <= (reset | (state == START)) ? 0 : ((state == NACK) ? 1 : Nack); + end + + assign Fifo_EnQ = (state == ENQ) || (state == R_ENQ); + assign Fifo_DeQ = (state == DEQ) || (state == A_DEQ) || (state == W_DEQ); + assign Fifo_In = (state == R_ENQ) ? Rx_Data : DataIn; + assign Fifo_Clear = (state == CLEAR); + + // Main state machine + always @(posedge clock) begin + if (reset) begin + state <= IDLE; + end + else begin + case (state) + IDLE: begin + if (EnQ) state <= ENQ; + else if (DeQ) state <= DEQ; + else if (Clear) state <= CLEAR; + else if (ReadCountSet) state <= RNSET; + else if ((Read | Write) & scl & scl_tick_90) state <= START; + else state <= IDLE; + end + ENQ: state <= BUSW; + DEQ: state <= BUSW; + CLEAR: state <= BUSW; + RNSET: state <= BUSW; + START: state <= (~scl & scl_tick_90) ? ADDR6 : START; + ADDR6: state <= (~scl & scl_tick_90) ? ADDR5 : ADDR6; + ADDR5: state <= (~scl & scl_tick_90) ? ADDR4 : ADDR5; + ADDR4: state <= (~scl & scl_tick_90) ? ADDR3 : ADDR4; + ADDR3: state <= (~scl & scl_tick_90) ? ADDR2 : ADDR3; + ADDR2: state <= (~scl & scl_tick_90) ? ADDR1 : ADDR2; + ADDR1: state <= (~scl & scl_tick_90) ? ADDR0 : ADDR1; + ADDR0: state <= (~scl & scl_tick_90) ? RWBIT : ADDR0; + RWBIT: state <= (~scl & scl_tick_90) ? A_DEQ : RWBIT; + A_DEQ: state <= A_ACK; + A_ACK: state <= ( scl & scl_tick_90) ? ((i2c_sda) ? NACK : ((Read) ? RDATA7 : WDWAIT)) : A_ACK; + + // Writes + WDWAIT: state <= (~scl & scl_tick_90) ? WDATA7 : WDWAIT; + WDATA7: state <= (~scl & scl_tick_90) ? WDATA6 : WDATA7; + WDATA6: state <= (~scl & scl_tick_90) ? WDATA5 : WDATA6; + WDATA5: state <= (~scl & scl_tick_90) ? WDATA4 : WDATA5; + WDATA4: state <= (~scl & scl_tick_90) ? WDATA3 : WDATA4; + WDATA3: state <= (~scl & scl_tick_90) ? WDATA2 : WDATA3; + WDATA2: state <= (~scl & scl_tick_90) ? WDATA1 : WDATA2; + WDATA1: state <= (~scl & scl_tick_90) ? WDATA0 : WDATA1; + WDATA0: state <= (~scl & scl_tick_90) ? W_DEQ : WDATA0; + W_DEQ: state <= W_ACK; + W_ACK: state <= ( scl & scl_tick_90) ? ((i2c_sda) ? NACK : ((Fifo_Empty) ? STOPW : WDWAIT)) : W_ACK; + + // Reads + RDATA7: state <= ( scl & scl_tick_90) ? RDATA6 : RDATA7; + RDATA6: state <= ( scl & scl_tick_90) ? RDATA5 : RDATA6; + RDATA5: state <= ( scl & scl_tick_90) ? RDATA4 : RDATA5; + RDATA4: state <= ( scl & scl_tick_90) ? RDATA3 : RDATA4; + RDATA3: state <= ( scl & scl_tick_90) ? RDATA2 : RDATA3; + RDATA2: state <= ( scl & scl_tick_90) ? RDATA1 : RDATA2; + RDATA1: state <= ( scl & scl_tick_90) ? RDATA0 : RDATA1; + RDATA0: state <= ( scl & scl_tick_90) ? R_ENQ : RDATA0; + R_ENQ: state <= R_ACKW; + R_ACKW: state <= (~scl & scl_tick_90) ? R_ACK : R_ACKW; + R_ACK: state <= (~scl & scl_tick_90) ? ((Rx_Remain != 8'h00) ? RDATA7 : STOP) : R_ACK; + + // Termination + NACK: state <= STOPW; + STOPW: state <= (~scl & scl_tick_90) ? STOP : STOPW; + STOP: state <= ( scl & scl_tick_90) ? BUSW : STOP; + BUSW: state <= (Read | Write | EnQ | DeQ) ? BUSW : IDLE; + default: state <= 6'bxxxxxx; + endcase + end + end + + // Incoming data capture + always @(posedge clock) begin + if (reset) begin + Rx_Data <= 8'h00; + end + else begin + Rx_Data[7] <= ((state == RDATA7) & scl & scl_tick_90) ? i2c_sda : Rx_Data[7]; + Rx_Data[6] <= ((state == RDATA6) & scl & scl_tick_90) ? i2c_sda : Rx_Data[6]; + Rx_Data[5] <= ((state == RDATA5) & scl & scl_tick_90) ? i2c_sda : Rx_Data[5]; + Rx_Data[4] <= ((state == RDATA4) & scl & scl_tick_90) ? i2c_sda : Rx_Data[4]; + Rx_Data[3] <= ((state == RDATA3) & scl & scl_tick_90) ? i2c_sda : Rx_Data[3]; + Rx_Data[2] <= ((state == RDATA2) & scl & scl_tick_90) ? i2c_sda : Rx_Data[2]; + Rx_Data[1] <= ((state == RDATA1) & scl & scl_tick_90) ? i2c_sda : Rx_Data[1]; + Rx_Data[0] <= ((state == RDATA0) & scl & scl_tick_90) ? i2c_sda : Rx_Data[0]; + end + end + + // I2C data line assignment + always @(*) begin + case (state) + IDLE: sda <= 1; + ENQ: sda <= 1; + DEQ: sda <= 1; + CLEAR: sda <= 1; + START: sda <= 0; + ADDR6: sda <= Fifo_Out[6]; + ADDR5: sda <= Fifo_Out[5]; + ADDR4: sda <= Fifo_Out[4]; + ADDR3: sda <= Fifo_Out[3]; + ADDR2: sda <= Fifo_Out[2]; + ADDR1: sda <= Fifo_Out[1]; + ADDR0: sda <= Fifo_Out[0]; + RWBIT: sda <= Read; // 0 is write, 1 is read + A_DEQ: sda <= 1; + A_ACK: sda <= 1; + WDWAIT: sda <= 1; + WDATA7: sda <= Fifo_Out[7]; + WDATA6: sda <= Fifo_Out[6]; + WDATA5: sda <= Fifo_Out[5]; + WDATA4: sda <= Fifo_Out[4]; + WDATA3: sda <= Fifo_Out[3]; + WDATA2: sda <= Fifo_Out[2]; + WDATA1: sda <= Fifo_Out[1]; + WDATA0: sda <= Fifo_Out[0]; + W_DEQ: sda <= 1; + W_ACK: sda <= 1; + RDATA7: sda <= 1; + RDATA6: sda <= 1; + RDATA5: sda <= 1; + RDATA4: sda <= 1; + RDATA3: sda <= 1; + RDATA2: sda <= 1; + RDATA1: sda <= 1; + RDATA0: sda <= 1; + R_ENQ: sda <= 1; + R_ACKW: sda <= 1; + R_ACK: sda <= (Rx_Remain == 8'h00); // Low for more data, high for done + NACK: sda <= 1; + STOPW: sda <= 1; + STOP: sda <= 0; + BUSW: sda <= 1; + default: sda <= 1; + endcase + end + + // I2C Clock Generation + I2C_Clock I2C_Clock ( + .clock (clock), + .reset (reset), + .scl (scl), + .scl_tick_90 (scl_tick_90) + ); + + FIFO_Clear FIFO ( + .clock (clock), + .reset (reset), + .clear (Fifo_Clear), + .enQ (Fifo_EnQ), + .deQ (Fifo_DeQ), + .data_in (Fifo_In), + .data_out (Fifo_Out), + .empty (Fifo_Empty), + .full (Fifo_Full) + ); + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/LCD/LCD.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/LCD/LCD.v new file mode 100755 index 0000000..8b94b95 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/LCD/LCD.v @@ -0,0 +1,204 @@ +`timescale 1ns / 1ps +/* + * File : LCD.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 16-Jun-2012 GEA Initial design. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * The top-level LCD controller. This module bridges the underlying 16x2 LCD + * hardware controller and the data memory bus. It caches 32 bytes of data which + * each correspond to a location on the LCD screen. The LCD screen is continuously + * updated with these 32 bytes as quickly as possible. + */ +module LCD( + input clock_100MHz, + input clock_Mem, + input reset, + input [2:0] address, + input [31:0] data, + input [3:0] writeEnable, + output reg ack, + output [6:0] LCD + ); + + localparam [5:0] INIT_1=1, INIT_2=2, INIT_3=3, INIT_4=4, LOC_0=5, LOC_1=6, LOC_2=7, + LOC_3=8, LOC_4=9, LOC_5=10, LOC_6=11, LOC_7=12, LOC_8=13, LOC_9=14, LOC_10=15, + LOC_11=16, LOC_12=17, LOC_13=18, LOC_14=19, LOC_15=20, LOC_16=21, LOC_17=22, + LOC_18=23, LOC_19=24, LOC_20=25, LOC_21=26, LOC_22=27, LOC_23=28, LOC_24=29, + LOC_25=30, LOC_26=31, LOC_27=32, LOC_28=33, LOC_29=34, LOC_30=35, LOC_31=36, + LINE_2=37, HOME=38; + + + wire clock = clock_100MHz; + reg [31:0] a0, a1, a2, a3, a4, a5, a6, a7; + reg [5:0] state; + wire bell; + + // LCD driver signals + reg [8:0] lcd_command; + reg lcd_write; + wire lcd_ack; + + assign bell = ~(lcd_write | lcd_ack); + + always @(posedge clock_Mem) begin + ack <= (reset) ? 0 : (writeEnable != 4'b0000); + end + + /* 32 bytes of LCD memory held on the FPGA fabric. The following is BIG ENDIAN */ + always @(posedge clock_Mem) begin + a0[31:24] <= (reset) ? 8'h20 : (((address == 3'd0) & writeEnable[3]) ? data[31:24] : a0[31:24]); + a0[23:16] <= (reset) ? 8'h20 : (((address == 3'd0) & writeEnable[2]) ? data[23:16] : a0[23:16]); + a0[15:8] <= (reset) ? 8'h20 : (((address == 3'd0) & writeEnable[1]) ? data[15:8] : a0[15:8]); + a0[7:0] <= (reset) ? 8'h20 : (((address == 3'd0) & writeEnable[0]) ? data[7:0] : a0[7:0]); + a1[31:24] <= (reset) ? 8'h20 : (((address == 3'd1) & writeEnable[3]) ? data[31:24] : a1[31:24]); + a1[23:16] <= (reset) ? 8'h20 : (((address == 3'd1) & writeEnable[2]) ? data[23:16] : a1[23:16]); + a1[15:8] <= (reset) ? 8'h20 : (((address == 3'd1) & writeEnable[1]) ? data[15:8] : a1[15:8]); + a1[7:0] <= (reset) ? 8'h20 : (((address == 3'd1) & writeEnable[0]) ? data[7:0] : a1[7:0]); + a2[31:24] <= (reset) ? 8'h20 : (((address == 3'd2) & writeEnable[3]) ? data[31:24] : a2[31:24]); + a2[23:16] <= (reset) ? 8'h20 : (((address == 3'd2) & writeEnable[2]) ? data[23:16] : a2[23:16]); + a2[15:8] <= (reset) ? 8'h20 : (((address == 3'd2) & writeEnable[1]) ? data[15:8] : a2[15:8]); + a2[7:0] <= (reset) ? 8'h20 : (((address == 3'd2) & writeEnable[0]) ? data[7:0] : a2[7:0]); + a3[31:24] <= (reset) ? 8'h20 : (((address == 3'd3) & writeEnable[3]) ? data[31:24] : a3[31:24]); + a3[23:16] <= (reset) ? 8'h20 : (((address == 3'd3) & writeEnable[2]) ? data[23:16] : a3[23:16]); + a3[15:8] <= (reset) ? 8'h20 : (((address == 3'd3) & writeEnable[1]) ? data[15:8] : a3[15:8]); + a3[7:0] <= (reset) ? 8'h21 : (((address == 3'd3) & writeEnable[0]) ? data[7:0] : a3[7:0]); + a4[31:24] <= (reset) ? 8'h20 : (((address == 3'd4) & writeEnable[3]) ? data[31:24] : a4[31:24]); + a4[23:16] <= (reset) ? 8'h20 : (((address == 3'd4) & writeEnable[2]) ? data[23:16] : a4[23:16]); + a4[15:8] <= (reset) ? 8'h20 : (((address == 3'd4) & writeEnable[1]) ? data[15:8] : a4[15:8]); + a4[7:0] <= (reset) ? 8'h20 : (((address == 3'd4) & writeEnable[0]) ? data[7:0] : a4[7:0]); + a5[31:24] <= (reset) ? 8'h20 : (((address == 3'd5) & writeEnable[3]) ? data[31:24] : a5[31:24]); + a5[23:16] <= (reset) ? 8'h20 : (((address == 3'd5) & writeEnable[2]) ? data[23:16] : a5[23:16]); + a5[15:8] <= (reset) ? 8'h20 : (((address == 3'd5) & writeEnable[1]) ? data[15:8] : a5[15:8]); + a5[7:0] <= (reset) ? 8'h20 : (((address == 3'd5) & writeEnable[0]) ? data[7:0] : a5[7:0]); + a6[31:24] <= (reset) ? 8'h20 : (((address == 3'd6) & writeEnable[3]) ? data[31:24] : a6[31:24]); + a6[23:16] <= (reset) ? 8'h20 : (((address == 3'd6) & writeEnable[2]) ? data[23:16] : a6[23:16]); + a6[15:8] <= (reset) ? 8'h20 : (((address == 3'd6) & writeEnable[1]) ? data[15:8] : a6[15:8]); + a6[7:0] <= (reset) ? 8'h20 : (((address == 3'd6) & writeEnable[0]) ? data[7:0] : a6[7:0]); + a7[31:24] <= (reset) ? 8'h20 : (((address == 3'd7) & writeEnable[3]) ? data[31:24] : a7[31:24]); + a7[23:16] <= (reset) ? 8'h20 : (((address == 3'd7) & writeEnable[2]) ? data[23:16] : a7[23:16]); + a7[15:8] <= (reset) ? 8'h20 : (((address == 3'd7) & writeEnable[1]) ? data[15:8] : a7[15:8]); + a7[7:0] <= (reset) ? 8'h20 : (((address == 3'd7) & writeEnable[0]) ? data[7:0] : a7[7:0]); + end + + /* The LCD continuously writes the memory locations as fast as possible */ + always @(posedge clock) begin + lcd_write <= (reset) ? 1 : ~lcd_ack; + end + + /* LCD commands for initialization and looping through 32 locations */ + always @(*) begin + case (state) + INIT_1 : lcd_command <= 9'b000101000; // 0x28 'Function Set' Not sure what this means + INIT_2 : lcd_command <= 9'b000000110; // Entry mode: set auto increment and no shifting + INIT_3 : lcd_command <= 9'b000001100; // Turn LCD on, disable cursor/blinking + INIT_4 : lcd_command <= 9'b000000001; // Clear display + LOC_0 : lcd_command <= {1'b1, a0[31:24]}; + LOC_1 : lcd_command <= {1'b1, a0[23:16]}; + LOC_2 : lcd_command <= {1'b1, a0[15:8]}; + LOC_3 : lcd_command <= {1'b1, a0[7:0]}; + LOC_4 : lcd_command <= {1'b1, a1[31:24]}; + LOC_5 : lcd_command <= {1'b1, a1[23:16]}; + LOC_6 : lcd_command <= {1'b1, a1[15:8]}; + LOC_7 : lcd_command <= {1'b1, a1[7:0]}; + LOC_8 : lcd_command <= {1'b1, a2[31:24]}; + LOC_9 : lcd_command <= {1'b1, a2[23:16]}; + LOC_10 : lcd_command <= {1'b1, a2[15:8]}; + LOC_11 : lcd_command <= {1'b1, a2[7:0]}; + LOC_12 : lcd_command <= {1'b1, a3[31:24]}; + LOC_13 : lcd_command <= {1'b1, a3[23:16]}; + LOC_14 : lcd_command <= {1'b1, a3[15:8]}; + LOC_15 : lcd_command <= {1'b1, a3[7:0]}; + LINE_2 : lcd_command <= 9'b011000000; + LOC_16 : lcd_command <= {1'b1, a4[31:24]}; + LOC_17 : lcd_command <= {1'b1, a4[23:16]}; + LOC_18 : lcd_command <= {1'b1, a4[15:8]}; + LOC_19 : lcd_command <= {1'b1, a4[7:0]}; + LOC_20 : lcd_command <= {1'b1, a5[31:24]}; + LOC_21 : lcd_command <= {1'b1, a5[23:16]}; + LOC_22 : lcd_command <= {1'b1, a5[15:8]}; + LOC_23 : lcd_command <= {1'b1, a5[7:0]}; + LOC_24 : lcd_command <= {1'b1, a6[31:24]}; + LOC_25 : lcd_command <= {1'b1, a6[23:16]}; + LOC_26 : lcd_command <= {1'b1, a6[15:8]}; + LOC_27 : lcd_command <= {1'b1, a6[7:0]}; + LOC_28 : lcd_command <= {1'b1, a7[31:24]}; + LOC_29 : lcd_command <= {1'b1, a7[23:16]}; + LOC_30 : lcd_command <= {1'b1, a7[15:8]}; + LOC_31 : lcd_command <= {1'b1, a7[7:0]}; + HOME : lcd_command <= 9'b010000000; + default : lcd_command <= 9'bx_xxxx_xxxx; + endcase + end + + /* Main state machine */ + always @(posedge clock) begin + if (reset) begin + state <= INIT_1; + end + else begin + case (state) + INIT_1 : state <= (bell) ? INIT_2 : INIT_1; + INIT_2 : state <= (bell) ? INIT_3 : INIT_2; + INIT_3 : state <= (bell) ? INIT_4 : INIT_3; + INIT_4 : state <= (bell) ? LOC_0 : INIT_4; + LOC_0 : state <= (bell) ? LOC_1 : LOC_0; + LOC_1 : state <= (bell) ? LOC_2 : LOC_1; + LOC_2 : state <= (bell) ? LOC_3 : LOC_2; + LOC_3 : state <= (bell) ? LOC_4 : LOC_3; + LOC_4 : state <= (bell) ? LOC_5 : LOC_4; + LOC_5 : state <= (bell) ? LOC_6 : LOC_5; + LOC_6 : state <= (bell) ? LOC_7 : LOC_6; + LOC_7 : state <= (bell) ? LOC_8 : LOC_7; + LOC_8 : state <= (bell) ? LOC_9 : LOC_8; + LOC_9 : state <= (bell) ? LOC_10 : LOC_9; + LOC_10 : state <= (bell) ? LOC_11 : LOC_10; + LOC_11 : state <= (bell) ? LOC_12 : LOC_11; + LOC_12 : state <= (bell) ? LOC_13 : LOC_12; + LOC_13 : state <= (bell) ? LOC_14 : LOC_13; + LOC_14 : state <= (bell) ? LOC_15 : LOC_14; + LOC_15 : state <= (bell) ? LINE_2 : LOC_15; + LINE_2 : state <= (bell) ? LOC_16 : LINE_2; + LOC_16 : state <= (bell) ? LOC_17 : LOC_16; + LOC_17 : state <= (bell) ? LOC_18 : LOC_17; + LOC_18 : state <= (bell) ? LOC_19 : LOC_18; + LOC_19 : state <= (bell) ? LOC_20 : LOC_19; + LOC_20 : state <= (bell) ? LOC_21 : LOC_20; + LOC_21 : state <= (bell) ? LOC_22 : LOC_21; + LOC_22 : state <= (bell) ? LOC_23 : LOC_22; + LOC_23 : state <= (bell) ? LOC_24 : LOC_23; + LOC_24 : state <= (bell) ? LOC_25 : LOC_24; + LOC_25 : state <= (bell) ? LOC_26 : LOC_25; + LOC_26 : state <= (bell) ? LOC_27 : LOC_26; + LOC_27 : state <= (bell) ? LOC_28 : LOC_27; + LOC_28 : state <= (bell) ? LOC_29 : LOC_28; + LOC_29 : state <= (bell) ? LOC_30 : LOC_29; + LOC_30 : state <= (bell) ? LOC_31 : LOC_30; + LOC_31 : state <= (bell) ? HOME : LOC_31; + HOME : state <= (bell) ? LOC_0 : HOME; + default : state <= 6'bxxxxxx; + endcase + end + end + + lcd_ctrl LCD_Driver ( + .clock (clock), + .reset (reset), + .command (lcd_command), + .write (lcd_write), + .ack (lcd_ack), + .LCD_D (LCD[6:3]), + .LCD_E (LCD[2]), + .LCD_RS (LCD[1]), + .LCD_RW (LCD[0]) + ); + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/LCD/lcd_ctrl.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/LCD/lcd_ctrl.v new file mode 100755 index 0000000..12230ca --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/LCD/lcd_ctrl.v @@ -0,0 +1,139 @@ +`timescale 1ns / 1ps +/* + * File : lcd_ctrl.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 16-Jun-2011 GEA Initial design. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * A controller for the common 16x2-character LCD screen based on the + * Sitronix ST7066U, Samsung S6A0069X / KS0066U, Hitachi HD44780, SMOS SED1278, + * or other compatible device. This controller uses a 4-bit data bus, is write-only, + * and requires a total of 7 output pins to the LCD. The timing must be adjusted for + * different input clock frequencies where noted. The primary version is based on a + * 100 MHz clock. + */ +module lcd_ctrl( + input clock, + input reset, + input [8:0] command, + input write, + output reg ack, + //--------------------------------- + output reg [3:0] LCD_D, // 4-bit LCD data bus + output reg LCD_E, // Enable + output LCD_RS, // Register Select (0->Register; 1->Data) + output LCD_RW // Read/Write (0->Write; 1->Read) + ); + + localparam [4:0] INIT_1=1, INIT_2=2, INIT_3=3, INIT_4=4, INIT_5=5, INIT_6=6, INIT_7=7, INIT_8=8, + CMD_WAIT=9, NOP=10, U_SETUP=11, U_ENAB=12, U_HOLD=13, UL_WAIT=14, L_SETUP=15, + L_ENAB=16, L_HOLD=17; + + reg [18:0] count; + reg [18:0] compare; + reg [4:0] state; + wire bell; + wire long_instr; + + assign LCD_RW = 0; // There is no reason to read from the LCD screen. + assign LCD_RS = command[8]; + assign bell = (count == compare); + assign long_instr = ((command == 9'b0_0000_0001) || (command[8:1] == 8'b0_0000_001)); + + + /* The count register increments until it equals 'compare' */ + always @(posedge clock) begin + count <= (reset | bell) ? 19'b0 : count + 1; + end + + /* Time delays for various states */ + always @(*) begin + case (state) + INIT_1 : compare <= 19'd410000; // 15ms (4.1ms OK due to power-up delay) + INIT_2 : compare <= 19'd24; // 240 ns + INIT_3 : compare <= 19'd410000; // 4.1 ms + INIT_4 : compare <= 19'd24; // 240 ns + INIT_5 : compare <= 19'd10000; // 100 us or longer + INIT_6 : compare <= 19'd24; // 240 ns + INIT_7 : compare <= 19'd4000; // 40 us or longer + INIT_8 : compare <= 19'd24; // 240 ns + CMD_WAIT : compare <= (long_instr) ? 19'd164000 : 19'd4000; // 40 us or 1.64 ms + NOP : compare <= 19'hxxxxx; + U_SETUP : compare <= 19'd4; // 40 ns + U_ENAB : compare <= 19'd23; // 230 ns + U_HOLD : compare <= 19'd1; // 10 ns + UL_WAIT : compare <= 19'd100; // 1 us + L_SETUP : compare <= 19'd4; // 40 ns + L_ENAB : compare <= 19'd23; // 230 ns + L_HOLD : compare <= 19'd1; // 10 ns + default : compare <= 19'hxxxxx; + endcase + end + + /* The main state machine */ + always @(posedge clock) begin + if (reset) begin + state <= INIT_1; + end + else begin + case (state) + INIT_1 : state <= (bell) ? INIT_2 : INIT_1; + INIT_2 : state <= (bell) ? INIT_3 : INIT_2; + INIT_3 : state <= (bell) ? INIT_4 : INIT_3; + INIT_4 : state <= (bell) ? INIT_5 : INIT_4; + INIT_5 : state <= (bell) ? INIT_6 : INIT_5; + INIT_6 : state <= (bell) ? INIT_7 : INIT_6; + INIT_7 : state <= (bell) ? INIT_8 : INIT_7; + INIT_8 : state <= (bell) ? CMD_WAIT : INIT_8; + CMD_WAIT : state <= (bell) ? NOP : CMD_WAIT; + NOP : state <= (write & ~ack) ? U_SETUP : NOP; + U_SETUP : state <= (bell) ? U_ENAB : U_SETUP; + U_ENAB : state <= (bell) ? U_HOLD : U_ENAB; + U_HOLD : state <= (bell) ? UL_WAIT : U_HOLD; + UL_WAIT : state <= (bell) ? L_SETUP : UL_WAIT; + L_SETUP : state <= (bell) ? L_ENAB : L_SETUP; + L_ENAB : state <= (bell) ? L_HOLD : L_ENAB; + L_HOLD : state <= (bell) ? CMD_WAIT : L_HOLD; + default : state <= 5'bxxxxx; + endcase + end + end + + /* Combinatorial enable and data assignments */ + always @(*) begin + case (state) + INIT_1 : begin LCD_E <= 0; LCD_D <= 4'b0000; end + INIT_2 : begin LCD_E <= 0; LCD_D <= 4'b0011; end + INIT_3 : begin LCD_E <= 0; LCD_D <= 4'b0000; end + INIT_4 : begin LCD_E <= 1; LCD_D <= 4'b0011; end + INIT_5 : begin LCD_E <= 0; LCD_D <= 4'b0000; end + INIT_6 : begin LCD_E <= 1; LCD_D <= 4'b0011; end + INIT_7 : begin LCD_E <= 0; LCD_D <= 4'b0000; end + INIT_8 : begin LCD_E <= 1; LCD_D <= 4'b0010; end + CMD_WAIT : begin LCD_E <= 0; LCD_D <= 4'b0000; end + NOP : begin LCD_E <= 0; LCD_D <= 4'b0000; end + U_SETUP : begin LCD_E <= 0; LCD_D <= command[7:4]; end + U_ENAB : begin LCD_E <= 1; LCD_D <= command[7:4]; end + U_HOLD : begin LCD_E <= 0; LCD_D <= command[7:4]; end + UL_WAIT : begin LCD_E <= 0; LCD_D <= 4'b0000; end + L_SETUP : begin LCD_E <= 0; LCD_D <= command[3:0]; end + L_ENAB : begin LCD_E <= 1; LCD_D <= command[3:0]; end + L_HOLD : begin LCD_E <= 0; LCD_D <= command[3:0]; end + default : begin LCD_E <= 0; LCD_D <= 4'b0000; end + endcase + end + + /* Full 4-way Handshake */ + always @(posedge clock) begin + ack <= (reset | ~write) ? 0 : (((state == L_HOLD) && (bell == 1'b1)) ? 1 : ack); + end + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/LED/LED.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/LED/LED.v new file mode 100755 index 0000000..23213b4 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/LED/LED.v @@ -0,0 +1,49 @@ +`timescale 1ns / 1ps +/* + * File : LED.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 13-Jul-2012 GEA Initial design. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * A read/write interface between a 4-way handshaking data bus and + * 8 LEDs. + * + * An optional mode allows the LEDs to show current interrupts + * instead of bus data. + */ +module LED( + input clock, + input reset, + input [14:0] dataIn, + input [7:0] IP, + input Write, + input Read, + output [13:0] dataOut, + output reg Ack, + output [13:0] LED + ); + + reg [13:0] data; + reg useInterrupts; + + always @(posedge clock) begin + data <= (reset) ? 14'b0 : ((Write) ? dataIn[13:0] : data); + useInterrupts <= (reset) ? 0 : ((Write) ? dataIn[14] : useInterrupts); + end + + always @(posedge clock) begin + Ack <= (reset) ? 0 : (Write | Read); + end + + assign LED = (useInterrupts) ? {6'b0, IP[7:0]} : data; + assign dataOut = data; + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/ALU.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/ALU.v new file mode 100755 index 0000000..8dbc820 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/ALU.v @@ -0,0 +1,290 @@ +`timescale 1ns / 1ps +/* + * File : ALU.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 7-Jun-2011 GEA Initial design. + * 2.0 26-Jul-2012 GEA Many changes have been made. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * An Arithmetic Logic Unit for a MIPS32 processor. This module computes all + * arithmetic operations, including the following: + * + * Add, Subtract, Multiply, And, Or, Nor, Xor, Shift, Count leading 1s/0s. + */ +module ALU( + input clock, + input reset, + input EX_Stall, + input EX_Flush, + input [31:0] A, B, + input [4:0] Operation, + input signed [4:0] Shamt, + output reg signed [31:0] Result, + output BZero, // Used for Movc + output reg EXC_Ov, + output ALU_Stall // Stalls due to long ALU operations + ); + + `include "MIPS_Parameters.v" + + /*** + Performance Notes: + + The ALU is the longest delay path in the Execute stage, and one of the longest + in the entire processor. This path varies based on the logic blocks that are + chosen to implement various functions, but there is certainly room to improve + the speed of arithmetic operations. The ALU could also be placed in a separate + pipeline stage after the Execute forwarding has completed. + ***/ + + + /*** + Divider Logic: + + The hardware divider requires 32 cycles to complete. Because it writes its + results to HILO and not to the pipeline, the pipeline can proceed without + stalling. When a later instruction tries to access HILO, the pipeline will + stall if the divide operation has not yet completed. + ***/ + + + // Internal state registers + reg [63:0] HILO; + reg HILO_Access; // Behavioral; not DFFs + reg [5:0] CLO_Result, CLZ_Result; // Behavioral; not DFFs + reg div_fsm; + + // Internal signals + wire [31:0] HI, LO; + wire HILO_Commit; + wire signed [31:0] As, Bs; + wire AddSub_Add; + wire signed [31:0] AddSub_Result; + wire signed [63:0] Mult_Result; + wire [63:0] Multu_Result; + wire [31:0] Quotient; + wire [31:0] Remainder; + wire Div_Stall; + wire Div_Start, Divu_Start; + wire DivOp; + wire Div_Commit; + + // Assignments + assign HI = HILO[63:32]; + assign LO = HILO[31:0]; + assign HILO_Commit = ~(EX_Stall | EX_Flush); + assign As = A; + assign Bs = B; + assign AddSub_Add = ((Operation == AluOp_Add) | (Operation == AluOp_Addu)); + assign AddSub_Result = (AddSub_Add) ? (A + B) : (A - B); + assign Mult_Result = As * Bs; + assign Multu_Result = A * B; + assign BZero = (B == 32'h00000000); + assign DivOp = (Operation == AluOp_Div) || (Operation == AluOp_Divu); + assign Div_Commit = (div_fsm == 1'b1) && (Div_Stall == 1'b0); + assign Div_Start = (div_fsm == 1'b0) && (Operation == AluOp_Div) && (HILO_Commit == 1'b1); + assign Divu_Start = (div_fsm == 1'b0) && (Operation == AluOp_Divu) && (HILO_Commit == 1'b1); + assign ALU_Stall = (div_fsm == 1'b1) && (HILO_Access == 1'b1); + + always @(*) begin + case (Operation) + AluOp_Add : Result <= AddSub_Result; + AluOp_Addu : Result <= AddSub_Result; + AluOp_And : Result <= A & B; + AluOp_Clo : Result <= {26'b0, CLO_Result}; + AluOp_Clz : Result <= {26'b0, CLZ_Result}; + AluOp_Mfhi : Result <= HI; + AluOp_Mflo : Result <= LO; + AluOp_Mul : Result <= Mult_Result[31:0]; + AluOp_Nor : Result <= ~(A | B); + AluOp_Or : Result <= A | B; + AluOp_Sll : Result <= B << Shamt; + AluOp_Sllc : Result <= {B[15:0], 16'b0}; + AluOp_Sllv : Result <= B << A[4:0]; + AluOp_Slt : Result <= (As < Bs) ? 32'h00000001 : 32'h00000000; + AluOp_Sltu : Result <= (A < B) ? 32'h00000001 : 32'h00000000; + AluOp_Sra : Result <= Bs >>> Shamt; + AluOp_Srav : Result <= Bs >>> As[4:0]; + AluOp_Srl : Result <= B >> Shamt; + AluOp_Srlv : Result <= B >> A[4:0]; + AluOp_Sub : Result <= AddSub_Result; + AluOp_Subu : Result <= AddSub_Result; + AluOp_Xor : Result <= A ^ B; + default : Result <= 32'bx; + endcase + end + + + always @(posedge clock) begin + if (reset) begin + HILO <= 64'h00000000_00000000; + end + else if (Div_Commit) begin + HILO <= {Remainder, Quotient}; + end + else if (HILO_Commit) begin + case (Operation) + AluOp_Mult : HILO <= Mult_Result; + AluOp_Multu : HILO <= Multu_Result; + AluOp_Madd : HILO <= HILO + Mult_Result; + AluOp_Maddu : HILO <= HILO + Multu_Result; + AluOp_Msub : HILO <= HILO - Mult_Result; + AluOp_Msubu : HILO <= HILO - Multu_Result; + AluOp_Mthi : HILO <= {A, LO}; + AluOp_Mtlo : HILO <= {HI, B}; + default : HILO <= HILO; + endcase + end + else begin + HILO <= HILO; + end + end + + // Detect accesses to HILO. RAW and WAW hazards are possible while a + // divide operation is computing, so reads and writes to HILO must stall + // while the divider is busy. + // (This logic could be put into an earlier pipeline stage or into the + // datapath bits to improve timing.) + always @(Operation) begin + case (Operation) + AluOp_Div : HILO_Access <= 1; + AluOp_Divu : HILO_Access <= 1; + AluOp_Mfhi : HILO_Access <= 1; + AluOp_Mflo : HILO_Access <= 1; + AluOp_Mult : HILO_Access <= 1; + AluOp_Multu : HILO_Access <= 1; + AluOp_Madd : HILO_Access <= 1; + AluOp_Maddu : HILO_Access <= 1; + AluOp_Msub : HILO_Access <= 1; + AluOp_Msubu : HILO_Access <= 1; + AluOp_Mthi : HILO_Access <= 1; + AluOp_Mtlo : HILO_Access <= 1; + default : HILO_Access <= 0; + endcase + end + + // Divider FSM: The divide unit is either available or busy. + always @(posedge clock) begin + if (reset) begin + div_fsm <= 2'd0; + end + else begin + case (div_fsm) + 1'd0 : div_fsm <= (DivOp & HILO_Commit) ? 1'd1 : 1'd0; + 1'd1 : div_fsm <= (~Div_Stall) ? 1'd0 : 1'd1; + endcase + end + end + + // Detect overflow for signed operations. Note that MIPS32 has no overflow + // detection for multiplication/division operations. + always @(*) begin + case (Operation) + AluOp_Add : EXC_Ov <= ((A[31] ~^ B[31]) & (A[31] ^ AddSub_Result[31])); + AluOp_Sub : EXC_Ov <= ((A[31] ^ B[31]) & (A[31] ^ AddSub_Result[31])); + default : EXC_Ov <= 0; + endcase + end + + // Count Leading Ones + always @(A) begin + casex (A) + 32'b0xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd0; + 32'b10xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd1; + 32'b110x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd2; + 32'b1110_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd3; + 32'b1111_0xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd4; + 32'b1111_10xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd5; + 32'b1111_110x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd6; + 32'b1111_1110_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd7; + 32'b1111_1111_0xxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd8; + 32'b1111_1111_10xx_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd9; + 32'b1111_1111_110x_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd10; + 32'b1111_1111_1110_xxxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd11; + 32'b1111_1111_1111_0xxx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd12; + 32'b1111_1111_1111_10xx_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd13; + 32'b1111_1111_1111_110x_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd14; + 32'b1111_1111_1111_1110_xxxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd15; + 32'b1111_1111_1111_1111_0xxx_xxxx_xxxx_xxxx : CLO_Result <= 6'd16; + 32'b1111_1111_1111_1111_10xx_xxxx_xxxx_xxxx : CLO_Result <= 6'd17; + 32'b1111_1111_1111_1111_110x_xxxx_xxxx_xxxx : CLO_Result <= 6'd18; + 32'b1111_1111_1111_1111_1110_xxxx_xxxx_xxxx : CLO_Result <= 6'd19; + 32'b1111_1111_1111_1111_1111_0xxx_xxxx_xxxx : CLO_Result <= 6'd20; + 32'b1111_1111_1111_1111_1111_10xx_xxxx_xxxx : CLO_Result <= 6'd21; + 32'b1111_1111_1111_1111_1111_110x_xxxx_xxxx : CLO_Result <= 6'd22; + 32'b1111_1111_1111_1111_1111_1110_xxxx_xxxx : CLO_Result <= 6'd23; + 32'b1111_1111_1111_1111_1111_1111_0xxx_xxxx : CLO_Result <= 6'd24; + 32'b1111_1111_1111_1111_1111_1111_10xx_xxxx : CLO_Result <= 6'd25; + 32'b1111_1111_1111_1111_1111_1111_110x_xxxx : CLO_Result <= 6'd26; + 32'b1111_1111_1111_1111_1111_1111_1110_xxxx : CLO_Result <= 6'd27; + 32'b1111_1111_1111_1111_1111_1111_1111_0xxx : CLO_Result <= 6'd28; + 32'b1111_1111_1111_1111_1111_1111_1111_10xx : CLO_Result <= 6'd29; + 32'b1111_1111_1111_1111_1111_1111_1111_110x : CLO_Result <= 6'd30; + 32'b1111_1111_1111_1111_1111_1111_1111_1110 : CLO_Result <= 6'd31; + 32'b1111_1111_1111_1111_1111_1111_1111_1111 : CLO_Result <= 6'd32; + default : CLO_Result <= 6'd0; + endcase + end + + // Count Leading Zeros + always @(A) begin + casex (A) + 32'b1xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd0; + 32'b01xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd1; + 32'b001x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd2; + 32'b0001_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd3; + 32'b0000_1xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd4; + 32'b0000_01xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd5; + 32'b0000_001x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd6; + 32'b0000_0001_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd7; + 32'b0000_0000_1xxx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd8; + 32'b0000_0000_01xx_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd9; + 32'b0000_0000_001x_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd10; + 32'b0000_0000_0001_xxxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd11; + 32'b0000_0000_0000_1xxx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd12; + 32'b0000_0000_0000_01xx_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd13; + 32'b0000_0000_0000_001x_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd14; + 32'b0000_0000_0000_0001_xxxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd15; + 32'b0000_0000_0000_0000_1xxx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd16; + 32'b0000_0000_0000_0000_01xx_xxxx_xxxx_xxxx : CLZ_Result <= 6'd17; + 32'b0000_0000_0000_0000_001x_xxxx_xxxx_xxxx : CLZ_Result <= 6'd18; + 32'b0000_0000_0000_0000_0001_xxxx_xxxx_xxxx : CLZ_Result <= 6'd19; + 32'b0000_0000_0000_0000_0000_1xxx_xxxx_xxxx : CLZ_Result <= 6'd20; + 32'b0000_0000_0000_0000_0000_01xx_xxxx_xxxx : CLZ_Result <= 6'd21; + 32'b0000_0000_0000_0000_0000_001x_xxxx_xxxx : CLZ_Result <= 6'd22; + 32'b0000_0000_0000_0000_0000_0001_xxxx_xxxx : CLZ_Result <= 6'd23; + 32'b0000_0000_0000_0000_0000_0000_1xxx_xxxx : CLZ_Result <= 6'd24; + 32'b0000_0000_0000_0000_0000_0000_01xx_xxxx : CLZ_Result <= 6'd25; + 32'b0000_0000_0000_0000_0000_0000_001x_xxxx : CLZ_Result <= 6'd26; + 32'b0000_0000_0000_0000_0000_0000_0001_xxxx : CLZ_Result <= 6'd27; + 32'b0000_0000_0000_0000_0000_0000_0000_1xxx : CLZ_Result <= 6'd28; + 32'b0000_0000_0000_0000_0000_0000_0000_01xx : CLZ_Result <= 6'd29; + 32'b0000_0000_0000_0000_0000_0000_0000_001x : CLZ_Result <= 6'd30; + 32'b0000_0000_0000_0000_0000_0000_0000_0001 : CLZ_Result <= 6'd31; + 32'b0000_0000_0000_0000_0000_0000_0000_0000 : CLZ_Result <= 6'd32; + default : CLZ_Result <= 6'd0; + endcase + end + + // Multicycle divide unit + Divide Divider ( + .clock (clock), + .reset (reset), + .OP_div (Div_Start), + .OP_divu (Divu_Start), + .Dividend (A), + .Divisor (B), + .Quotient (Quotient), + .Remainder (Remainder), + .Stall (Div_Stall) + ); + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/Add.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/Add.v new file mode 100755 index 0000000..859cd40 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/Add.v @@ -0,0 +1,26 @@ +`timescale 1ns / 1ps +/* + * File : Add.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 7-Jun-2011 GEA Initial design. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * A simple 32-bit 2-input adder. + */ +module Add( + input [31:0] A, + input [31:0] B, + output [31:0] C + ); + + assign C = (A + B); + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/CPZero.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/CPZero.v new file mode 100755 index 0000000..84d18c9 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/CPZero.v @@ -0,0 +1,529 @@ +`timescale 1ns / 1ps +/* + * File : CPZero.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 16-Sep-2011 GEA Initial design. + * 2.0 14-May-2012 GEA Complete rework. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * The MIPS-32 Coprocessor 0 (CP0). This is the processor management unit that allows + * interrupts, traps, system calls, and other exceptions. It distinguishes + * user and kernel modes, provides status information, and can override program + * flow. This processor is designed for "bare metal" memory access and thus does + * not have virtual memory hardware as a part of it. However, the subset of CP0 + * is MIPS-32-compliant. + */ +module CPZero( + input clock, + //-- CP0 Functionality --// + input Mfc0, // CPU instruction is Mfc0 + input Mtc0, // CPU instruction is Mtc0 + input IF_Stall, + input ID_Stall, // Commits are not made during stalls + input COP1, // Instruction for Coprocessor 1 + input COP2, // Instruction for Coprocessor 2 + input COP3, // Instruction for Coprocessor 3 + input ERET, // Instruction is ERET (Exception Return) + input [4:0] Rd, // Specifies Cp0 register + input [2:0] Sel, // Specifies Cp0 'select' + input [31:0] Reg_In, // Data from GP register to replace CP0 register + output reg [31:0] Reg_Out, // Data from CP0 register for GP register + output KernelMode, // Kernel mode indicator for pipeline transit + output ReverseEndian, // Reverse Endian memory indicator for User Mode + //-- Hw Interrupts --// + input [4:0] Int, // Five hardware interrupts external to the processor + //-- Exceptions --// + input reset, // Cold Reset (EXC_Reset) +// input EXC_SReset, // Soft Reset (not implemented) + input EXC_NMI, // Non-Maskable Interrupt + input EXC_AdIF, // Address Error Exception from i-fetch (mapped to AdEL) + input EXC_AdEL, // Address Error Exception from data memory load + input EXC_AdES, // Address Error Exception from data memory store + input EXC_Ov, // Integer Overflow Exception + input EXC_Tr, // Trap Exception + input EXC_Sys, // System Call Exception + input EXC_Bp, // Breakpoint Exception + input EXC_RI, // Reserved Instruction Exception + //-- Exception Data --// + input [31:0] ID_RestartPC, // PC for exception, whether PC of instruction or of branch (PC-4) if BDS + input [31:0] EX_RestartPC, // Same as 'ID_RestartPC' but in EX stage + input [31:0] M_RestartPC, // Same as 'ID_RestartPC' but in MEM stage + input ID_IsFlushed, + input IF_IsBD, // Indicator of IF exception being a branch delay slot instruction + input ID_IsBD, // Indicator of ID exception being a branch delay slot instruction + input EX_IsBD, // Indicator of EX exception being a branch delay slot instruction + input M_IsBD, // Indicator of M exception being a branch delay slot instruction + input [31:0] BadAddr_M, // Bad 'Virtual' Address for exceptions AdEL, AdES in MEM stage + input [31:0] BadAddr_IF, // Bad 'Virtual' Address for AdIF (i.e. AdEL) in IF stage + input ID_CanErr, // Cumulative signal, i.e. (ID_ID_CanErr | ID_EX_CanErr | ID_M_CanErr) + input EX_CanErr, // Cumulative signal, i.e. (EX_EX_CanErr | EX_M_CanErr) + input M_CanErr, // Memory stage can error (i.e. cause exception) + //-- Exception Control Flow --/ + output IF_Exception_Stall, + output ID_Exception_Stall, + output EX_Exception_Stall, + output M_Exception_Stall, + output IF_Exception_Flush, + output ID_Exception_Flush, + output EX_Exception_Flush, + output M_Exception_Flush, + output Exc_PC_Sel, // Mux selector for exception PC override + output reg [31:0] Exc_PC_Out, // Address for PC at the beginning of an exception + output [7:0] IP // Pending Interrupts from Cause register (for diagnostic purposes) + ); + + `include "MIPS_Parameters.v" + + + /*** + Exception Control Flow Notes + + - Exceptions can occur in every pipeline stage. This implies that more than one exception + can be raised in a single cycle. When this occurs, only the forward-most exception + (i.e. MEM over EX) is handled. This and the following note guarantee program order. + + - An exception in any pipeline stage must stall that stage until all following stages are + exception-free. This is because it only makes sense for exceptions to occur in program order. + + - A pipeline stage which causes an exception must flush, i.e. prevent any commits it would + have normally made and convert itself to a NOP for the next pipeline stage. Furthermore, + it must flush all previous pipeline stages as well in order to retain program order. + + - Instructions reading CP0 (mtc0) read in ID without further action. Writes to CP0 (mtc0, + eret) also write in ID, but only after forward pipeline stages have been cleared + of possible exceptions. This prevents many insidious bugs, such as switching to User Mode + in ID when a legitimate memory access in kernel mode is processing in MEM, or conversely + a switch to Kernel Mode in ID when an instruction in User Mode is attempting a kernel region + memory access (when a kernel mode signal does not propagate through the pipeline). + + - Commits occur in ID (CP0), EX (HILO), MEM, and WB (registers). + + - Hardware interrupts are detected and inserted in the ID stage, but only when there are no + other possible exceptions in the pipeline. Because they appear 'asynchronous' to the + processor, the remaining instructions in forward stages (EX, MEM, WB) can either be + flushed or completed. It is simplest to have them complete to avoid restarts, but the + interrupt latency is higher if e.g. the MEM stage stalls on a memory access (this would + be unavoidable on single-cycle processors). This implementation allows all forward instructions + to complete, for a greater instruction throughput but higher interrupt latency. + + - Software interrupts should appear synchronous in the program order, meaning that all + instructions previous to them should complete and no instructions after them should start + until the interrupts has been processed. + + Exception Name Short Name Pipeline Stage + Address Error Ex (AdEL, AdES) MEM, IF + Integer Overflow Ex (Ov) EX + Trap Ex (Tr) MEM + Syscall (Sys) ID + Breakpoint (Bp) ID + Reserved Instruction (RI) ID + Coprocessor Unusable (CpU) ID + Interrupt (Int) ID + Reset, SReset, NMI ID + ***/ + + + // Exceptions Generated Internally + wire EXC_CpU; + + // Hardware Interrupt #5, caused by Timer/Perf counter + wire Int5; + + // Top-level Authoritative Interrupt Signal + wire EXC_Int; + + // General Exception detection (all but Interrupts, Reset, Soft Reset, and NMI) + wire EXC_General = EXC_AdIF | EXC_AdEL | EXC_AdES | EXC_Ov | EXC_Tr | EXC_Sys | EXC_Bp | EXC_RI | EXC_CpU; + + // Misc + wire CP0_WriteCond; + reg [3:0] Cause_ExcCode_bits; + + reg reset_r; + always @(posedge clock) begin + reset_r <= reset; + end + + /*** + MIPS-32 COPROCESSOR 0 (Cp0) REGISTERS + + These are defined in "MIPS32 Architecture for Programmers Volume III: + The MIPS32 Privileged Resource Architecture" from MIPS Technologies, Inc. + + Optional registers are omitted. Changes to the processor (such as adding + an MMU/TLB, etc. must be reflected in these registers. + */ + + // BadVAddr Register (Register 8, Select 0) + reg [31:0] BadVAddr; + + // Count Register (Register 9, Select 0) + reg [31:0] Count; + + // Compare Register (Register 11, Select 0) + reg [31:0] Compare; + + // Status Register (Register 12, Select 0) + wire [2:0] Status_CU_321 = 3'b000; + reg Status_CU_0; // Access Control to CPs, [2]->Cp3, ... [0]->Cp0 + wire Status_RP = 0; + wire Status_FR = 0; + reg Status_RE; // Reverse Endian Memory for User Mode + wire Status_MX = 0; + wire Status_PX = 0; + reg Status_BEV; // Exception vector locations (0->Norm, 1->Bootstrap) + wire Status_TS = 0; + wire Status_SR = 0; // Soft reset not implemented + reg Status_NMI; // Non-Maskable Interrupt + wire Status_RES = 0; + wire [1:0] Status_Custom = 2'b00; + reg [7:0] Status_IM; // Interrupt mask + wire Status_KX = 0; + wire Status_SX = 0; + wire Status_UX = 0; + reg Status_UM; // Base operating mode (0->Kernel, 1->User) + wire Status_R0 = 0; + reg Status_ERL; // Error Level (0->Normal, 1->Error (reset, NMI)) + reg Status_EXL; // Exception level (0->Normal, 1->Exception) + reg Status_IE; // Interrupt Enable + wire [31:0] Status = {Status_CU_321, Status_CU_0, Status_RP, Status_FR, Status_RE, Status_MX, + Status_PX, Status_BEV, Status_TS, Status_SR, Status_NMI, Status_RES, + Status_Custom, Status_IM, Status_KX, Status_SX, Status_UX, + Status_UM, Status_R0, Status_ERL, Status_EXL, Status_IE}; + + // Cause Register (Register 13, Select 0) + reg Cause_BD; // Exception occured in Branch Delay + reg [1:0] Cause_CE; // CP number for CP Unusable exception + reg Cause_IV; // Indicator of general IV (0->0x180) or special IV (1->0x200) + wire Cause_WP = 0; + reg [7:0] Cause_IP; // Pending HW Interrupt indicator. + wire Cause_ExcCode4 = 0; // Can be made into a register when this bit is needed. + reg [3:0] Cause_ExcCode30; // Description of Exception (only lower 4 bits currently used; see above) + wire [31:0] Cause = {Cause_BD, 1'b0, Cause_CE, 4'b0000, Cause_IV, Cause_WP, + 6'b000000, Cause_IP, 1'b0, Cause_ExcCode4, Cause_ExcCode30, 2'b00}; + + // Exception Program Counter (Register 14, Select 0) + reg [31:0] EPC; + + // Processor Identification (Register 15, Select 0) + wire [7:0] ID_Options = 8'b0000_0000; + wire [7:0] ID_CID = 8'b0000_0000; + wire [7:0] ID_PID = 8'b0000_0000; + wire [7:0] ID_Rev = 8'b0000_0001; + wire [31:0] PRId = {ID_Options, ID_CID, ID_PID, ID_Rev}; + + // Configuration Register (Register 16, Select 0) + wire Config_M = 1; + wire [14:0] Config_Impl = 15'b000_0000_0000_0000; + wire Config_BE = Big_Endian; // From parameters file + wire [1:0] Config_AT = 2'b00; + wire [2:0] Config_AR = 3'b000; + wire [2:0] Config_MT = 3'b000; + wire [2:0] Config_K0 = 3'b000; + wire [31:0] Config = {Config_M, Config_Impl, Config_BE, Config_AT, Config_AR, Config_MT, + 4'b0000, Config_K0}; + + // Configuration Register 1 (Register 16, Select 1) + wire Config1_M = 0; + wire [5:0] Config1_MMU = 6'b000000; + wire [2:0] Config1_IS = 3'b000; + wire [2:0] Config1_IL = 3'b000; + wire [2:0] Config1_IA = 3'b000; + wire [2:0] Config1_DS = 3'b000; + wire [2:0] Config1_DL = 3'b000; + wire [2:0] Config1_DA = 3'b000; + wire Config1_C2 = 0; + wire Config1_MD = 0; + wire Config1_PC = 0; // XXX Performance Counters + wire Config1_WR = 0; // XXX Watch Registers + wire Config1_CA = 0; + wire Config1_EP = 0; + wire Config1_FP = 0; + wire [31:0] Config1 = {Config1_M, Config1_MMU, Config1_IS, Config1_IL, Config1_IA, + Config1_DS, Config1_DL, Config1_DA, Config1_C2, + Config1_MD, Config1_PC, Config1_WR, Config1_CA, + Config1_EP, Config1_FP}; + + // Performance Counter Register (Register 25) XXX TODO + + // ErrorEPC Register (Register 30, Select 0) + reg [31:0] ErrorEPC; + + // Exception Detection and Processing + wire M_Exception_Detect, EX_Exception_Detect, ID_Exception_Detect, IF_Exception_Detect; + wire M_Exception_Mask, EX_Exception_Mask, ID_Exception_Mask, IF_Exception_Mask; + wire M_Exception_Ready, EX_Exception_Ready, ID_Exception_Ready, IF_Exception_Ready; + + assign IP = Cause_IP; + + /*** Coprocessor Unusable Exception ***/ + assign EXC_CpU = COP1 | COP2 | COP3 | ((Mtc0 | Mfc0 | ERET) & ~(Status_CU_0 | KernelMode)); + + /*** Kernel Mode Signal ***/ + assign KernelMode = ~Status_UM | Status_EXL | Status_ERL; + + /*** Reverse Endian for User Mode ***/ + assign ReverseEndian = Status_RE; + + /*** Interrupts ***/ + assign Int5 = (Count == Compare); + //assign EXC_Int = ((Cause_IP[7:0] & Status_IM[7:0]) != 8'h00) & Status_IE & ~Status_EXL & ~Status_ERL & ~ID_IsFlushed; + wire Enabled_Interrupt = EXC_NMI | (Status_IE & ((Cause_IP[7:0] & Status_IM[7:0]) != 8'h00)); + assign EXC_Int = Enabled_Interrupt & ~Status_EXL & ~Status_ERL & ~ID_IsFlushed; + + assign CP0_WriteCond = (Status_CU_0 | KernelMode) & Mtc0 & ~ID_Stall; + + + /*** + Exception Hazard Flow Control Explanation: + - An exception at any time in any stage causes its own and any previous stages to + flush (clear own commits, NOPS to fwd stages). + - An exception in a stage can also stall that stage (and inherently all previous stages) if and only if: + 1. A forward stage is capable of causing an exception AND + 2. A forward stage is not currently causing an exception. + - An exception is ready to process when it is detected and not stalled in a stage. + + Flush specifics per pipeline stage: + MEM: Mask 'MemWrite' and 'MemRead' (for performance) after EX/M and before data memory. NOPs to M/WB. + EX : Mask writes to HI/LO. NOPs to EX/M. + ID : Mask writes (reads?) to CP0. NOPs to ID/EX. + IF : NOP to IF/ID. + ***/ + + /*** Exceptions grouped by pipeline stage ***/ + assign M_Exception_Detect = EXC_AdEL | EXC_AdES | EXC_Tr; + assign EX_Exception_Detect = EXC_Ov; + assign ID_Exception_Detect = EXC_Sys | EXC_Bp | EXC_RI | EXC_CpU | EXC_Int; + assign IF_Exception_Detect = EXC_AdIF; + + /*** Exception mask conditions ***/ + + // A potential bug would occur if e.g. EX stalls, MEM has data, but MEM is not stalled and finishes + // going through the pipeline so forwarding would fail. This is not a problem however because + // EX would not need data since it would flush on an exception. + assign M_Exception_Mask = IF_Stall; + assign EX_Exception_Mask = IF_Stall | M_CanErr; + assign ID_Exception_Mask = IF_Stall | M_CanErr | EX_CanErr; + assign IF_Exception_Mask = M_CanErr | EX_CanErr | ID_CanErr | EXC_Int; + + /*** + Exceptions which must wait for forward stages. A stage will not stall if a forward stage has an exception. + These stalls must be inserted as stall conditions in the hazard unit so that it will take care of chaining. + All writes to CP0 must also wait for forward hazard conditions to clear. + */ + assign M_Exception_Stall = M_Exception_Detect & M_Exception_Mask; + assign EX_Exception_Stall = EX_Exception_Detect & EX_Exception_Mask & ~M_Exception_Detect; + assign ID_Exception_Stall = (ID_Exception_Detect | ERET | Mtc0) & ID_Exception_Mask & ~(EX_Exception_Detect | M_Exception_Detect); + assign IF_Exception_Stall = IF_Exception_Detect & IF_Exception_Mask & ~(ID_Exception_Detect | EX_Exception_Detect | M_Exception_Detect); + + + /*** Exceptions which are ready to process (mutually exclusive) ***/ + // XXX can remove ~ID_Stall since in mask now (?) + assign M_Exception_Ready = ~ID_Stall & M_Exception_Detect & ~M_Exception_Mask; + assign EX_Exception_Ready = ~ID_Stall & EX_Exception_Detect & ~EX_Exception_Mask; + assign ID_Exception_Ready = ~ID_Stall & ID_Exception_Detect & ~ID_Exception_Mask; + assign IF_Exception_Ready = ~ID_Stall & IF_Exception_Detect & ~IF_Exception_Mask; + + /*** + Flushes. A flush clears a pipeline stage's control signals and prevents the stage from committing any changes. + Data such as 'RestartPC' and the detected exception must remain. + */ + assign M_Exception_Flush = M_Exception_Detect; + assign EX_Exception_Flush = M_Exception_Detect | EX_Exception_Detect; + assign ID_Exception_Flush = M_Exception_Detect | EX_Exception_Detect | ID_Exception_Detect; + assign IF_Exception_Flush = M_Exception_Detect | EX_Exception_Detect | ID_Exception_Detect | IF_Exception_Detect | (ERET & ~ID_Stall) | reset_r; + + + /*** Software reads of CP0 Registers ***/ + always @(*) begin + if (Mfc0 & (Status_CU_0 | KernelMode)) begin + case (Rd) + 5'd8 : Reg_Out <= BadVAddr; + 5'd9 : Reg_Out <= Count; + 5'd11 : Reg_Out <= Compare; + 5'd12 : Reg_Out <= Status; + 5'd13 : Reg_Out <= Cause; + 5'd14 : Reg_Out <= EPC; + 5'd15 : Reg_Out <= PRId; + 5'd16 : Reg_Out <= (Sel == 3'b000) ? Config : Config1; + 5'd30 : Reg_Out <= ErrorEPC; + default : Reg_Out <= 32'h0000_0000; + endcase + end + else begin + Reg_Out <= 32'h0000_0000; + end + end + + /*** Cp0 Register Assignments: Non-general exceptions (Reset, Soft Reset, NMI...) ***/ + always @(posedge clock) begin + if (reset) begin + Status_BEV <= 1; + Status_NMI <= 0; + Status_ERL <= 1; + ErrorEPC <= 32'b0; + end + else if (ID_Exception_Ready & EXC_NMI) begin + Status_BEV <= 1; + Status_NMI <= 1; + Status_ERL <= 1; + ErrorEPC <= ID_RestartPC; + end + else begin + Status_BEV <= (CP0_WriteCond & (Rd == 5'd12) & (Sel == 3'b000)) ? Reg_In[22] : Status_BEV; + Status_NMI <= (CP0_WriteCond & (Rd == 5'd12) & (Sel == 3'b000)) ? Reg_In[19] : Status_NMI; + Status_ERL <= (CP0_WriteCond & (Rd == 5'd12) & (Sel == 3'b000)) ? Reg_In[2] : ((Status_ERL & ERET & ~ID_Stall) ? 0 : Status_ERL); + ErrorEPC <= (CP0_WriteCond & (Rd == 5'd30) & (Sel == 3'b000)) ? Reg_In : ErrorEPC; + end + end + + /*** Cp0 Register Assignments: All other registers ***/ + always @(posedge clock) begin + if (reset) begin + Count <= 32'b0; + Compare <= 32'b0; + Status_CU_0 <= 0; + Status_RE <= 0; + Status_IM <= 8'b0; + Status_UM <= 0; + Status_IE <= 0; + Cause_IV <= 0; + Cause_IP <= 8'b0; + end + else begin + Count <= (CP0_WriteCond & (Rd == 5'd9 ) & (Sel == 3'b000)) ? Reg_In : ((Count == Compare) ? 32'b0 : Count + 1); + Compare <= (CP0_WriteCond & (Rd == 5'd11) & (Sel == 3'b000)) ? Reg_In : Compare; + Status_CU_0 <= (CP0_WriteCond & (Rd == 5'd12) & (Sel == 3'b000)) ? Reg_In[28] : Status_CU_0; + Status_RE <= (CP0_WriteCond & (Rd == 5'd12) & (Sel == 3'b000)) ? Reg_In[25] : Status_RE; + Status_IM <= (CP0_WriteCond & (Rd == 5'd12) & (Sel == 3'b000)) ? Reg_In[15:8] : Status_IM; + Status_UM <= (CP0_WriteCond & (Rd == 5'd12) & (Sel == 3'b000)) ? Reg_In[4] : Status_UM; + Status_IE <= (CP0_WriteCond & (Rd == 5'd12) & (Sel == 3'b000)) ? Reg_In[0] : Status_IE; + Cause_IV <= (CP0_WriteCond & (Rd == 5'd13) & (Sel == 3'b000)) ? Reg_In[23] : Cause_IV; + /* Cause_IP indicates 8 interrupts: + [7] is set by the timer comparison, and cleared by reading 'Count'. + [6:2] are set and cleared by external hardware. + [1:0] are set and cleared by software. + */ + // If reading -> 0, Otherwise if 0 -> Int5. + Cause_IP[7] <= ((Status_CU_0 | KernelMode) & Mfc0 & (Rd == 5'd9) & (Sel == 3'b000)) ? 0 : ((Cause_IP[7] == 0) ? Int5 : Cause_IP[7]); + Cause_IP[6:2] <= Int[4:0]; + Cause_IP[1:0] <= (CP0_WriteCond & (Rd == 5'd13) & (Sel == 3'b000)) ? Reg_In[9:8] : Cause_IP[1:0]; + end + end + + /*** Cp0 Register Assignments: General Exception and Interrupt Processing ***/ + always @(posedge clock) begin + if (reset) begin + Cause_BD <= 0; + Cause_CE <= 2'b00; + Cause_ExcCode30 <= 4'b0000; + Status_EXL <= 0; + EPC <= 32'h0; + BadVAddr <= 32'h0; + end + else begin + // MEM stage + if (M_Exception_Ready) begin + Cause_BD <= (Status_EXL) ? Cause_BD : M_IsBD; + Cause_CE <= (COP3) ? 2'b11 : ((COP2) ? 2'b10 : ((COP1) ? 2'b01 : 2'b00)); + Cause_ExcCode30 <= Cause_ExcCode_bits; + Status_EXL <= 1; + EPC <= (Status_EXL) ? EPC : M_RestartPC; + BadVAddr <= BadAddr_M; + end + // EX stage + else if (EX_Exception_Ready) begin + Cause_BD <= (Status_EXL) ? Cause_BD : EX_IsBD; + Cause_CE <= (COP3) ? 2'b11 : ((COP2) ? 2'b10 : ((COP1) ? 2'b01 : 2'b00)); + Cause_ExcCode30 <= Cause_ExcCode_bits; + Status_EXL <= 1; + EPC <= (Status_EXL) ? EPC : EX_RestartPC; + BadVAddr <= BadVAddr; + end + // ID stage + else if (ID_Exception_Ready) begin + Cause_BD <= (Status_EXL) ? Cause_BD : ID_IsBD; + Cause_CE <= (COP3) ? 2'b11 : ((COP2) ? 2'b10 : ((COP1) ? 2'b01 : 2'b00)); + Cause_ExcCode30 <= Cause_ExcCode_bits; + Status_EXL <= 1; + EPC <= (Status_EXL) ? EPC : ID_RestartPC; + BadVAddr <= BadVAddr; + end + // IF stage + else if (IF_Exception_Ready) begin + Cause_BD <= (Status_EXL) ? Cause_BD : IF_IsBD; + Cause_CE <= (COP3) ? 2'b11 : ((COP2) ? 2'b10 : ((COP1) ? 2'b01 : 2'b00)); + Cause_ExcCode30 <= Cause_ExcCode_bits; + Status_EXL <= 1; + EPC <= (Status_EXL) ? EPC : BadAddr_IF; + BadVAddr <= BadAddr_IF; + end + // No exceptions this cycle + else begin + Cause_BD <= 1'b0; + Cause_CE <= Cause_CE; + Cause_ExcCode30 <= Cause_ExcCode30; + // Without new exceptions, 'Status_EXL' is set by software or cleared by ERET. + Status_EXL <= (CP0_WriteCond & (Rd == 5'd12) & (Sel == 3'b000)) ? Reg_In[1] : ((Status_EXL & ERET & ~ID_Stall) ? 0 : Status_EXL); + // The EPC is also writable by software + EPC <= (CP0_WriteCond & (Rd == 5'd14) & (Sel == 3'b000)) ? Reg_In : EPC; + BadVAddr <= BadVAddr; + end + end + end + + + /*** Program Counter for all Exceptions/Interrupts ***/ + always @(*) begin + // Following is redundant since PC has initial value now. + if (reset) begin + Exc_PC_Out <= EXC_Vector_Base_Reset; + end + else if (ERET & ~ID_Stall) begin + Exc_PC_Out <= (Status_ERL) ? ErrorEPC : EPC; + end + else if (EXC_General) begin + Exc_PC_Out <= (Status_BEV) ? (EXC_Vector_Base_Other_Boot + EXC_Vector_Offset_General) : + (EXC_Vector_Base_Other_NoBoot + EXC_Vector_Offset_General); + end + else if (EXC_NMI) begin + Exc_PC_Out <= EXC_Vector_Base_Reset; + end + else if (EXC_Int & Cause_IV) begin + Exc_PC_Out <= (Status_BEV) ? (EXC_Vector_Base_Other_Boot + EXC_Vector_Offset_Special) : + (EXC_Vector_Base_Other_NoBoot + EXC_Vector_Offset_Special); + end + else begin + Exc_PC_Out <= (Status_BEV) ? (EXC_Vector_Base_Other_Boot + EXC_Vector_Offset_General) : + (EXC_Vector_Base_Other_NoBoot + EXC_Vector_Offset_General); + end + end + + //assign Exc_PC_Sel = (reset | (ERET & ~ID_Stall) | EXC_General | EXC_Int); + assign Exc_PC_Sel = reset | (ERET & ~ID_Stall) | IF_Exception_Ready | ID_Exception_Ready | EX_Exception_Ready | M_Exception_Ready; + + /*** Cause Register ExcCode Field ***/ + always @(*) begin + // Ordered by Pipeline Stage with Interrupts last + if (EXC_AdEL) Cause_ExcCode_bits <= 4'h4; // 00100 + else if (EXC_AdES) Cause_ExcCode_bits <= 4'h5; // 00101 + else if (EXC_Tr) Cause_ExcCode_bits <= 4'hd; // 01101 + else if (EXC_Ov) Cause_ExcCode_bits <= 4'hc; // 01100 + else if (EXC_Sys) Cause_ExcCode_bits <= 4'h8; // 01000 + else if (EXC_Bp) Cause_ExcCode_bits <= 4'h9; // 01001 + else if (EXC_RI) Cause_ExcCode_bits <= 4'ha; // 01010 + else if (EXC_CpU) Cause_ExcCode_bits <= 4'hb; // 01011 + else if (EXC_AdIF) Cause_ExcCode_bits <= 4'h4; // 00100 + else if (EXC_Int) Cause_ExcCode_bits <= 4'h0; // 00000 // OK that NMI writes this. + else Cause_ExcCode_bits <= 4'bxxxx; + end + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/Compare.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/Compare.v new file mode 100755 index 0000000..6ec671a --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/Compare.v @@ -0,0 +1,41 @@ +`timescale 1ns / 1ps +/* + * File : Compare.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 15-Jun-2011 GEA Initial design. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * Compares two 32-bit values and outputs the following information about them: + * EQ : A and B are equal + * GZ : A is greater than zero + * LZ : A is less than zero + * GEZ : A is greater than or equal to zero + * LEZ : A is less than or equal to zero + */ +module Compare( + input [31:0] A, + input [31:0] B, + output EQ, + output GZ, + output LZ, + output GEZ, + output LEZ + ); + + wire ZeroA = (A == 32'b0); + + assign EQ = ( A == B); + assign GZ = (~A[31] & ~ZeroA); + assign LZ = A[31]; + assign GEZ = ~A[31]; + assign LEZ = ( A[31] | ZeroA); + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/Control.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/Control.v new file mode 100755 index 0000000..058d937 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/Control.v @@ -0,0 +1,509 @@ + `timescale 1ns / 1ps +/* + * File : Control.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 7-Jun-2011 GEA Initial design. + * 2.0 26-May-2012 GEA Release version with CP0. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * The Datapath Controller. This module sets the datapath control + * bits for an incoming instruction. These control bits follow the + * instruction through each pipeline stage as needed, and constitute + * the effective operation of the processor through each pipeline stage. + */ +module Control( + input ID_Stall, + input [5:0] OpCode, + input [5:0] Funct, + input [4:0] Rs, // used to differentiate mfc0 and mtc0 + input [4:0] Rt, // used to differentiate bgez,bgezal,bltz,bltzal,teqi,tgei,tgeiu,tlti,tltiu,tnei + input Cmp_EQ, + input Cmp_GZ, + input Cmp_GEZ, + input Cmp_LZ, + input Cmp_LEZ, + //------------ + output IF_Flush, + output reg [7:0] DP_Hazards, + output [1:0] PCSrc, + output SignExtend, + output Link, + output Movn, + output Movz, + output Mfc0, + output Mtc0, + output CP1, + output CP2, + output CP3, + output Eret, + output Trap, + output TrapCond, + output EXC_Sys, + output EXC_Bp, + output EXC_RI, + output ID_CanErr, + output EX_CanErr, + output M_CanErr, + output NextIsDelay, + output RegDst, + output ALUSrcImm, + output reg [4:0] ALUOp, + output LLSC, + output MemWrite, + output MemRead, + output MemByte, + output MemHalf, + output MemSignExtend, + output Left, + output Right, + output RegWrite, + output MemtoReg + ); + + `include "MIPS_Parameters.v" + + wire Movc; + wire Branch, Branch_EQ, Branch_GTZ, Branch_LEZ, Branch_NEQ, Branch_GEZ, Branch_LTZ; + wire Unaligned_Mem; + + reg [15:0] Datapath; + assign PCSrc[0] = Datapath[14]; + assign Link = Datapath[13]; + assign ALUSrcImm = Datapath[12]; + assign Movc = Datapath[11]; + assign Trap = Datapath[10]; + assign TrapCond = Datapath[9]; + assign RegDst = Datapath[8]; + assign LLSC = Datapath[7]; + assign MemRead = Datapath[6]; + assign MemWrite = Datapath[5]; + assign MemHalf = Datapath[4]; + assign MemByte = Datapath[3]; + assign MemSignExtend = Datapath[2]; + assign RegWrite = Datapath[1]; + assign MemtoReg = Datapath[0]; + + reg [2:0] DP_Exceptions; + assign ID_CanErr = DP_Exceptions[2]; + assign EX_CanErr = DP_Exceptions[1]; + assign M_CanErr = DP_Exceptions[0]; + + // Set the main datapath control signals based on the Op Code + always @(*) begin + if (ID_Stall) + Datapath <= DP_None; + else begin + case (OpCode) + // R-Type + Op_Type_R : + begin + case (Funct) + Funct_Add : Datapath <= DP_Add; + Funct_Addu : Datapath <= DP_Addu; + Funct_And : Datapath <= DP_And; + Funct_Break : Datapath <= DP_Break; + Funct_Div : Datapath <= DP_Div; + Funct_Divu : Datapath <= DP_Divu; + Funct_Jalr : Datapath <= DP_Jalr; + Funct_Jr : Datapath <= DP_Jr; + Funct_Mfhi : Datapath <= DP_Mfhi; + Funct_Mflo : Datapath <= DP_Mflo; + Funct_Movn : Datapath <= DP_Movn; + Funct_Movz : Datapath <= DP_Movz; + Funct_Mthi : Datapath <= DP_Mthi; + Funct_Mtlo : Datapath <= DP_Mtlo; + Funct_Mult : Datapath <= DP_Mult; + Funct_Multu : Datapath <= DP_Multu; + Funct_Nor : Datapath <= DP_Nor; + Funct_Or : Datapath <= DP_Or; + Funct_Sll : Datapath <= DP_Sll; + Funct_Sllv : Datapath <= DP_Sllv; + Funct_Slt : Datapath <= DP_Slt; + Funct_Sltu : Datapath <= DP_Sltu; + Funct_Sra : Datapath <= DP_Sra; + Funct_Srav : Datapath <= DP_Srav; + Funct_Srl : Datapath <= DP_Srl; + Funct_Srlv : Datapath <= DP_Srlv; + Funct_Sub : Datapath <= DP_Sub; + Funct_Subu : Datapath <= DP_Subu; + Funct_Syscall : Datapath <= DP_Syscall; + Funct_Teq : Datapath <= DP_Teq; + Funct_Tge : Datapath <= DP_Tge; + Funct_Tgeu : Datapath <= DP_Tgeu; + Funct_Tlt : Datapath <= DP_Tlt; + Funct_Tltu : Datapath <= DP_Tltu; + Funct_Tne : Datapath <= DP_Tne; + Funct_Xor : Datapath <= DP_Xor; + default : Datapath <= DP_None; + endcase + end + // R2-Type + Op_Type_R2 : + begin + case (Funct) + Funct_Clo : Datapath <= DP_Clo; + Funct_Clz : Datapath <= DP_Clz; + Funct_Madd : Datapath <= DP_Madd; + Funct_Maddu : Datapath <= DP_Maddu; + Funct_Msub : Datapath <= DP_Msub; + Funct_Msubu : Datapath <= DP_Msubu; + Funct_Mul : Datapath <= DP_Mul; + default : Datapath <= DP_None; + endcase + end + // I-Type + Op_Addi : Datapath <= DP_Addi; + Op_Addiu : Datapath <= DP_Addiu; + Op_Andi : Datapath <= DP_Andi; + Op_Ori : Datapath <= DP_Ori; + Op_Pref : Datapath <= DP_Pref; + Op_Slti : Datapath <= DP_Slti; + Op_Sltiu : Datapath <= DP_Sltiu; + Op_Xori : Datapath <= DP_Xori; + // Jumps (using immediates) + Op_J : Datapath <= DP_J; + Op_Jal : Datapath <= DP_Jal; + // Branches and Traps + Op_Type_BI : + begin + case (Rt) + OpRt_Bgez : Datapath <= DP_Bgez; + OpRt_Bgezal : Datapath <= DP_Bgezal; + OpRt_Bltz : Datapath <= DP_Bltz; + OpRt_Bltzal : Datapath <= DP_Bltzal; + OpRt_Teqi : Datapath <= DP_Teqi; + OpRt_Tgei : Datapath <= DP_Tgei; + OpRt_Tgeiu : Datapath <= DP_Tgeiu; + OpRt_Tlti : Datapath <= DP_Tlti; + OpRt_Tltiu : Datapath <= DP_Tltiu; + OpRt_Tnei : Datapath <= DP_Tnei; + default : Datapath <= DP_None; + endcase + end + Op_Beq : Datapath <= DP_Beq; + Op_Bgtz : Datapath <= DP_Bgtz; + Op_Blez : Datapath <= DP_Blez; + Op_Bne : Datapath <= DP_Bne; + // Coprocessor 0 + Op_Type_CP0 : + begin + case (Rs) + OpRs_MF : Datapath <= DP_Mfc0; + OpRs_MT : Datapath <= DP_Mtc0; + OpRs_ERET : Datapath <= (Funct == Funct_ERET) ? DP_Eret : DP_None; + default : Datapath <= DP_None; + endcase + end + // Memory + Op_Lb : Datapath <= DP_Lb; + Op_Lbu : Datapath <= DP_Lbu; + Op_Lh : Datapath <= DP_Lh; + Op_Lhu : Datapath <= DP_Lhu; + Op_Ll : Datapath <= DP_Ll; + Op_Lui : Datapath <= DP_Lui; + Op_Lw : Datapath <= DP_Lw; + Op_Lwl : Datapath <= DP_Lwl; + Op_Lwr : Datapath <= DP_Lwr; + Op_Sb : Datapath <= DP_Sb; + Op_Sc : Datapath <= DP_Sc; + Op_Sh : Datapath <= DP_Sh; + Op_Sw : Datapath <= DP_Sw; + Op_Swl : Datapath <= DP_Swl; + Op_Swr : Datapath <= DP_Swr; + default : Datapath <= DP_None; + endcase + end + end + + // Set the Hazard Control Signals and Exception Indicators based on the Op Code + always @(*) begin + case (OpCode) + // R-Type + Op_Type_R : + begin + case (Funct) + Funct_Add : begin DP_Hazards <= HAZ_Add; DP_Exceptions <= EXC_Add; end + Funct_Addu : begin DP_Hazards <= HAZ_Addu; DP_Exceptions <= EXC_Addu; end + Funct_And : begin DP_Hazards <= HAZ_And; DP_Exceptions <= EXC_And; end + Funct_Break : begin DP_Hazards <= HAZ_Break; DP_Exceptions <= EXC_Break; end + Funct_Div : begin DP_Hazards <= HAZ_Div; DP_Exceptions <= EXC_Div; end + Funct_Divu : begin DP_Hazards <= HAZ_Divu; DP_Exceptions <= EXC_Divu; end + Funct_Jalr : begin DP_Hazards <= HAZ_Jalr; DP_Exceptions <= EXC_Jalr; end + Funct_Jr : begin DP_Hazards <= HAZ_Jr; DP_Exceptions <= EXC_Jr; end + Funct_Mfhi : begin DP_Hazards <= HAZ_Mfhi; DP_Exceptions <= EXC_Mfhi; end + Funct_Mflo : begin DP_Hazards <= HAZ_Mflo; DP_Exceptions <= EXC_Mflo; end + Funct_Movn : begin DP_Hazards <= HAZ_Movn; DP_Exceptions <= EXC_Movn; end + Funct_Movz : begin DP_Hazards <= HAZ_Movz; DP_Exceptions <= EXC_Movz; end + Funct_Mthi : begin DP_Hazards <= HAZ_Mthi; DP_Exceptions <= EXC_Mthi; end + Funct_Mtlo : begin DP_Hazards <= HAZ_Mtlo; DP_Exceptions <= EXC_Mtlo; end + Funct_Mult : begin DP_Hazards <= HAZ_Mult; DP_Exceptions <= EXC_Mult; end + Funct_Multu : begin DP_Hazards <= HAZ_Multu; DP_Exceptions <= EXC_Multu; end + Funct_Nor : begin DP_Hazards <= HAZ_Nor; DP_Exceptions <= EXC_Nor; end + Funct_Or : begin DP_Hazards <= HAZ_Or; DP_Exceptions <= EXC_Or; end + Funct_Sll : begin DP_Hazards <= HAZ_Sll; DP_Exceptions <= EXC_Sll; end + Funct_Sllv : begin DP_Hazards <= HAZ_Sllv; DP_Exceptions <= EXC_Sllv; end + Funct_Slt : begin DP_Hazards <= HAZ_Slt; DP_Exceptions <= EXC_Slt; end + Funct_Sltu : begin DP_Hazards <= HAZ_Sltu; DP_Exceptions <= EXC_Sltu; end + Funct_Sra : begin DP_Hazards <= HAZ_Sra; DP_Exceptions <= EXC_Sra; end + Funct_Srav : begin DP_Hazards <= HAZ_Srav; DP_Exceptions <= EXC_Srav; end + Funct_Srl : begin DP_Hazards <= HAZ_Srl; DP_Exceptions <= EXC_Srl; end + Funct_Srlv : begin DP_Hazards <= HAZ_Srlv; DP_Exceptions <= EXC_Srlv; end + Funct_Sub : begin DP_Hazards <= HAZ_Sub; DP_Exceptions <= EXC_Sub; end + Funct_Subu : begin DP_Hazards <= HAZ_Subu; DP_Exceptions <= EXC_Subu; end + Funct_Syscall : begin DP_Hazards <= HAZ_Syscall; DP_Exceptions <= EXC_Syscall; end + Funct_Teq : begin DP_Hazards <= HAZ_Teq; DP_Exceptions <= EXC_Teq; end + Funct_Tge : begin DP_Hazards <= HAZ_Tge; DP_Exceptions <= EXC_Tge; end + Funct_Tgeu : begin DP_Hazards <= HAZ_Tgeu; DP_Exceptions <= EXC_Tgeu; end + Funct_Tlt : begin DP_Hazards <= HAZ_Tlt; DP_Exceptions <= EXC_Tlt; end + Funct_Tltu : begin DP_Hazards <= HAZ_Tltu; DP_Exceptions <= EXC_Tltu; end + Funct_Tne : begin DP_Hazards <= HAZ_Tne; DP_Exceptions <= EXC_Tne; end + Funct_Xor : begin DP_Hazards <= HAZ_Xor; DP_Exceptions <= EXC_Xor; end + default : begin DP_Hazards <= 8'hxx; DP_Exceptions <= 3'bxxx; end + endcase + end + // R2-Type + Op_Type_R2 : + begin + case (Funct) + Funct_Clo : begin DP_Hazards <= HAZ_Clo; DP_Exceptions <= EXC_Clo; end + Funct_Clz : begin DP_Hazards <= HAZ_Clz; DP_Exceptions <= EXC_Clz; end + Funct_Madd : begin DP_Hazards <= HAZ_Madd; DP_Exceptions <= EXC_Madd; end + Funct_Maddu : begin DP_Hazards <= HAZ_Maddu; DP_Exceptions <= EXC_Maddu; end + Funct_Msub : begin DP_Hazards <= HAZ_Msub; DP_Exceptions <= EXC_Msub; end + Funct_Msubu : begin DP_Hazards <= HAZ_Msubu; DP_Exceptions <= EXC_Msubu; end + Funct_Mul : begin DP_Hazards <= HAZ_Mul; DP_Exceptions <= EXC_Mul; end + default : begin DP_Hazards <= 8'hxx; DP_Exceptions <= 3'bxxx; end + endcase + end + // I-Type + Op_Addi : begin DP_Hazards <= HAZ_Addi; DP_Exceptions <= EXC_Addi; end + Op_Addiu : begin DP_Hazards <= HAZ_Addiu; DP_Exceptions <= EXC_Addiu; end + Op_Andi : begin DP_Hazards <= HAZ_Andi; DP_Exceptions <= EXC_Andi; end + Op_Ori : begin DP_Hazards <= HAZ_Ori; DP_Exceptions <= EXC_Ori; end + Op_Pref : begin DP_Hazards <= HAZ_Pref; DP_Exceptions <= EXC_Pref; end + Op_Slti : begin DP_Hazards <= HAZ_Slti; DP_Exceptions <= EXC_Slti; end + Op_Sltiu : begin DP_Hazards <= HAZ_Sltiu; DP_Exceptions <= EXC_Sltiu; end + Op_Xori : begin DP_Hazards <= HAZ_Xori; DP_Exceptions <= EXC_Xori; end + // Jumps + Op_J : begin DP_Hazards <= HAZ_J; DP_Exceptions <= EXC_J; end + Op_Jal : begin DP_Hazards <= HAZ_Jal; DP_Exceptions <= EXC_Jal; end + // Branches and Traps + Op_Type_BI : + begin + case (Rt) + OpRt_Bgez : begin DP_Hazards <= HAZ_Bgez; DP_Exceptions <= EXC_Bgez; end + OpRt_Bgezal : begin DP_Hazards <= HAZ_Bgezal; DP_Exceptions <= EXC_Bgezal; end + OpRt_Bltz : begin DP_Hazards <= HAZ_Bltz; DP_Exceptions <= EXC_Bltz; end + OpRt_Bltzal : begin DP_Hazards <= HAZ_Bltzal; DP_Exceptions <= EXC_Bltzal; end + OpRt_Teqi : begin DP_Hazards <= HAZ_Teqi; DP_Exceptions <= EXC_Teqi; end + OpRt_Tgei : begin DP_Hazards <= HAZ_Tgei; DP_Exceptions <= EXC_Tgei; end + OpRt_Tgeiu : begin DP_Hazards <= HAZ_Tgeiu; DP_Exceptions <= EXC_Tgeiu; end + OpRt_Tlti : begin DP_Hazards <= HAZ_Tlti; DP_Exceptions <= EXC_Tlti; end + OpRt_Tltiu : begin DP_Hazards <= HAZ_Tltiu; DP_Exceptions <= EXC_Tltiu; end + OpRt_Tnei : begin DP_Hazards <= HAZ_Tnei; DP_Exceptions <= EXC_Tnei; end + default : begin DP_Hazards <= 8'hxx; DP_Exceptions <= 3'bxxx; end + endcase + end + Op_Beq : begin DP_Hazards <= HAZ_Beq; DP_Exceptions <= EXC_Beq; end + Op_Bgtz : begin DP_Hazards <= HAZ_Bgtz; DP_Exceptions <= EXC_Bgtz; end + Op_Blez : begin DP_Hazards <= HAZ_Blez; DP_Exceptions <= EXC_Blez; end + Op_Bne : begin DP_Hazards <= HAZ_Bne; DP_Exceptions <= EXC_Bne; end + // Coprocessor 0 + Op_Type_CP0 : + begin + case (Rs) + OpRs_MF : begin DP_Hazards <= HAZ_Mfc0; DP_Exceptions <= EXC_Mfc0; end + OpRs_MT : begin DP_Hazards <= HAZ_Mtc0; DP_Exceptions <= EXC_Mtc0; end + OpRs_ERET : begin DP_Hazards <= (Funct == Funct_ERET) ? DP_Eret : 8'hxx; DP_Exceptions <= EXC_Eret; end + default : begin DP_Hazards <= 8'hxx; DP_Exceptions <= 3'bxxx; end + endcase + end + // Memory + Op_Lb : begin DP_Hazards <= HAZ_Lb; DP_Exceptions <= EXC_Lb; end + Op_Lbu : begin DP_Hazards <= HAZ_Lbu; DP_Exceptions <= EXC_Lbu; end + Op_Lh : begin DP_Hazards <= HAZ_Lh; DP_Exceptions <= EXC_Lh; end + Op_Lhu : begin DP_Hazards <= HAZ_Lhu; DP_Exceptions <= EXC_Lhu; end + Op_Ll : begin DP_Hazards <= HAZ_Ll; DP_Exceptions <= EXC_Ll; end + Op_Lui : begin DP_Hazards <= HAZ_Lui; DP_Exceptions <= EXC_Lui; end + Op_Lw : begin DP_Hazards <= HAZ_Lw; DP_Exceptions <= EXC_Lw; end + Op_Lwl : begin DP_Hazards <= HAZ_Lwl; DP_Exceptions <= EXC_Lwl; end + Op_Lwr : begin DP_Hazards <= HAZ_Lwr; DP_Exceptions <= EXC_Lwr; end + Op_Sb : begin DP_Hazards <= HAZ_Sb; DP_Exceptions <= EXC_Sb; end + Op_Sc : begin DP_Hazards <= HAZ_Sc; DP_Exceptions <= EXC_Sc; end + Op_Sh : begin DP_Hazards <= HAZ_Sh; DP_Exceptions <= EXC_Sh; end + Op_Sw : begin DP_Hazards <= HAZ_Sw; DP_Exceptions <= EXC_Sw; end + Op_Swl : begin DP_Hazards <= HAZ_Swl; DP_Exceptions <= EXC_Swl; end + Op_Swr : begin DP_Hazards <= HAZ_Swr; DP_Exceptions <= EXC_Swr; end + default : begin DP_Hazards <= 8'hxx; DP_Exceptions <= 3'bxxx; end + endcase + end + + // ALU Assignment + always @(*) begin + if (ID_Stall) + ALUOp <= AluOp_Addu; // Any Op that doesn't write HILO or cause exceptions + else begin + case (OpCode) + Op_Type_R : + begin + case (Funct) + Funct_Add : ALUOp <= AluOp_Add; + Funct_Addu : ALUOp <= AluOp_Addu; + Funct_And : ALUOp <= AluOp_And; + Funct_Div : ALUOp <= AluOp_Div; + Funct_Divu : ALUOp <= AluOp_Divu; + Funct_Jalr : ALUOp <= AluOp_Addu; + Funct_Mfhi : ALUOp <= AluOp_Mfhi; + Funct_Mflo : ALUOp <= AluOp_Mflo; + Funct_Movn : ALUOp <= AluOp_Addu; + Funct_Movz : ALUOp <= AluOp_Addu; + Funct_Mthi : ALUOp <= AluOp_Mthi; + Funct_Mtlo : ALUOp <= AluOp_Mtlo; + Funct_Mult : ALUOp <= AluOp_Mult; + Funct_Multu : ALUOp <= AluOp_Multu; + Funct_Nor : ALUOp <= AluOp_Nor; + Funct_Or : ALUOp <= AluOp_Or; + Funct_Sll : ALUOp <= AluOp_Sll; + Funct_Sllv : ALUOp <= AluOp_Sllv; + Funct_Slt : ALUOp <= AluOp_Slt; + Funct_Sltu : ALUOp <= AluOp_Sltu; + Funct_Sra : ALUOp <= AluOp_Sra; + Funct_Srav : ALUOp <= AluOp_Srav; + Funct_Srl : ALUOp <= AluOp_Srl; + Funct_Srlv : ALUOp <= AluOp_Srlv; + Funct_Sub : ALUOp <= AluOp_Sub; + Funct_Subu : ALUOp <= AluOp_Subu; + Funct_Syscall : ALUOp <= AluOp_Addu; + Funct_Teq : ALUOp <= AluOp_Subu; + Funct_Tge : ALUOp <= AluOp_Slt; + Funct_Tgeu : ALUOp <= AluOp_Sltu; + Funct_Tlt : ALUOp <= AluOp_Slt; + Funct_Tltu : ALUOp <= AluOp_Sltu; + Funct_Tne : ALUOp <= AluOp_Subu; + Funct_Xor : ALUOp <= AluOp_Xor; + default : ALUOp <= AluOp_Addu; + endcase + end + Op_Type_R2 : + begin + case (Funct) + Funct_Clo : ALUOp <= AluOp_Clo; + Funct_Clz : ALUOp <= AluOp_Clz; + Funct_Madd : ALUOp <= AluOp_Madd; + Funct_Maddu : ALUOp <= AluOp_Maddu; + Funct_Msub : ALUOp <= AluOp_Msub; + Funct_Msubu : ALUOp <= AluOp_Msubu; + Funct_Mul : ALUOp <= AluOp_Mul; + default : ALUOp <= AluOp_Addu; + endcase + end + Op_Type_BI : + begin + case (Rt) + OpRt_Teqi : ALUOp <= AluOp_Subu; + OpRt_Tgei : ALUOp <= AluOp_Slt; + OpRt_Tgeiu : ALUOp <= AluOp_Sltu; + OpRt_Tlti : ALUOp <= AluOp_Slt; + OpRt_Tltiu : ALUOp <= AluOp_Sltu; + OpRt_Tnei : ALUOp <= AluOp_Subu; + default : ALUOp <= AluOp_Addu; // Branches don't matter. + endcase + end + Op_Type_CP0 : ALUOp <= AluOp_Addu; + Op_Addi : ALUOp <= AluOp_Add; + Op_Addiu : ALUOp <= AluOp_Addu; + Op_Andi : ALUOp <= AluOp_And; + Op_Jal : ALUOp <= AluOp_Addu; + Op_Lb : ALUOp <= AluOp_Addu; + Op_Lbu : ALUOp <= AluOp_Addu; + Op_Lh : ALUOp <= AluOp_Addu; + Op_Lhu : ALUOp <= AluOp_Addu; + Op_Ll : ALUOp <= AluOp_Addu; + Op_Lui : ALUOp <= AluOp_Sllc; + Op_Lw : ALUOp <= AluOp_Addu; + Op_Lwl : ALUOp <= AluOp_Addu; + Op_Lwr : ALUOp <= AluOp_Addu; + Op_Ori : ALUOp <= AluOp_Or; + Op_Sb : ALUOp <= AluOp_Addu; + Op_Sc : ALUOp <= AluOp_Addu; // XXX Needs HW implement + Op_Sh : ALUOp <= AluOp_Addu; + Op_Slti : ALUOp <= AluOp_Slt; + Op_Sltiu : ALUOp <= AluOp_Sltu; + Op_Sw : ALUOp <= AluOp_Addu; + Op_Swl : ALUOp <= AluOp_Addu; + Op_Swr : ALUOp <= AluOp_Addu; + Op_Xori : ALUOp <= AluOp_Xor; + default : ALUOp <= AluOp_Addu; + endcase + end + end + + /*** + These remaining options cover portions of the datapath that are not + controlled directly by the datapath bits. Note that some refer to bits of + the opcode or other fields, which breaks the otherwise fully-abstracted view + of instruction encodings. Make sure when adding custom instructions that + no false positives/negatives are generated here. + ***/ + + // Branch Detection: Options are mutually exclusive. + assign Branch_EQ = OpCode[2] & ~OpCode[1] & ~OpCode[0] & Cmp_EQ; + assign Branch_GTZ = OpCode[2] & OpCode[1] & OpCode[0] & Cmp_GZ; + assign Branch_LEZ = OpCode[2] & OpCode[1] & ~OpCode[0] & Cmp_LEZ; + assign Branch_NEQ = OpCode[2] & ~OpCode[1] & OpCode[0] & ~Cmp_EQ; + assign Branch_GEZ = ~OpCode[2] & Rt[0] & Cmp_GEZ; + assign Branch_LTZ = ~OpCode[2] & ~Rt[0] & Cmp_LZ; + + assign Branch = Branch_EQ | Branch_GTZ | Branch_LEZ | Branch_NEQ | Branch_GEZ | Branch_LTZ; + assign PCSrc[1] = (Datapath[15] & ~Datapath[14]) ? Branch : Datapath[15]; + + /* In MIPS32, all Branch and Jump operations execute the Branch Delay Slot, + * or next instruction, regardless if the branch is taken or not. The exception + * is the "Branch Likely" instruction group. These are deprecated, however, and not + * implemented here. "IF_Flush" is defined to allow for the cancelation of a + * Branch Delay Slot should these be implemented later. + */ + assign IF_Flush = 0; + + // Indicator that next instruction is a Branch Delay Slot. + assign NextIsDelay = Datapath[15] | Datapath[14]; + + // Sign- or Zero-Extension Control. The only ops that require zero-extension are + // Andi, Ori, and Xori. The following also zero-extends 'lui', however it does not alter the effect of lui. + assign SignExtend = (OpCode[5:2] != 4'b0011); + + // Move Conditional + assign Movn = Movc & Funct[0]; + assign Movz = Movc & ~Funct[0]; + + // Coprocessor 0 (Mfc0, Mtc0) control signals. + assign Mfc0 = ((OpCode == Op_Type_CP0) && (Rs == OpRs_MF)); + assign Mtc0 = ((OpCode == Op_Type_CP0) && (Rs == OpRs_MT)); + assign Eret = ((OpCode == Op_Type_CP0) && (Rs == OpRs_ERET) && (Funct == Funct_ERET)); + + // Coprocessor 1,2,3 accesses (not implemented) + assign CP1 = (OpCode == Op_Type_CP1); + assign CP2 = (OpCode == Op_Type_CP2); + assign CP3 = (OpCode == Op_Type_CP3); + + // Exceptions found in ID + assign EXC_Sys = ((OpCode == Op_Type_R) && (Funct == Funct_Syscall)); + assign EXC_Bp = ((OpCode == Op_Type_R) && (Funct == Funct_Break)); + + // Unaligned Memory Accesses (lwl, lwr, swl, swr) + assign Unaligned_Mem = OpCode[5] & ~OpCode[4] & OpCode[1] & ~OpCode[0]; + assign Left = Unaligned_Mem & ~OpCode[2]; + assign Right = Unaligned_Mem & OpCode[2]; + + // TODO: Reserved Instruction Exception must still be implemented + assign EXC_RI = 0; + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/Divide.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/Divide.v new file mode 100755 index 0000000..8a2e617 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/Divide.v @@ -0,0 +1,100 @@ +`timescale 1ns / 1ns +/* + * File : Divide.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Neil Russell + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 6-Nov-2012 NJR Initial design. + * + * Description: + * A multi-cycle 32-bit divider. + * + * On any cycle that one of OP_div or OP_divu are true, the Dividend and + * Divisor will be captured and a multi-cycle divide operation initiated. + * Stall will go true on the next cycle and the first cycle of the divide + * operation completed. After some time (about 32 cycles), Stall will go + * false on the same cycle that the result becomes valid. OP_div or OP_divu + * will abort any currently running divide operation and initiate a new one. + */ +module Divide( + input clock, + input reset, + input OP_div, // True to initiate a signed divide + input OP_divu, // True to initiate an unsigned divide + input [31:0] Dividend, + input [31:0] Divisor, + output [31:0] Quotient, + output [31:0] Remainder, + output Stall // True while calculating + ); + + + reg active; // True if the divider is running + reg neg; // True if the result will be negative + reg [4:0] cycle; // Number of cycles to go + + reg [31:0] result; // Begin with dividend, end with quotient + reg [31:0] denom; // Divisor + reg [31:0] work; // Running remainder + + // Calculate the current digit + wire [32:0] sub = { work[30:0], result[31] } - denom; + + // Send the results to our master + assign Quotient = !neg ? result : -result; + assign Remainder = work; + assign Stall = active; + + // The state machine + always @(posedge clock) begin + if (reset) begin + active <= 0; + neg <= 0; + cycle <= 0; + result <= 0; + denom <= 0; + work <= 0; + end + else begin + if (OP_div) begin + // Set up for a signed divide. Remember the resulting sign, + // and make the operands positive. + cycle <= 5'd31; + result <= (Dividend[31] == 0) ? Dividend : -Dividend; + denom <= (Divisor[31] == 0) ? Divisor : -Divisor; + work <= 32'b0; + neg <= Dividend[31] ^ Divisor[31]; + active <= 1; + end + else if (OP_divu) begin + // Set up for an unsigned divide. + cycle <= 5'd31; + result <= Dividend; + denom <= Divisor; + work <= 32'b0; + neg <= 0; + active <= 1; + end + else if (active) begin + // Run an iteration of the divide. + if (sub[32] == 0) begin + work <= sub[31:0]; + result <= {result[30:0], 1'b1}; + end + else begin + work <= {work[30:0], result[31]}; + result <= {result[30:0], 1'b0}; + end + + if (cycle == 0) begin + active <= 0; + end + + cycle <= cycle - 5'd1; + end + end + end + +endmodule diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/EXMEM_Stage.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/EXMEM_Stage.v new file mode 100755 index 0000000..99d3c7b --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/EXMEM_Stage.v @@ -0,0 +1,116 @@ +`timescale 1ns / 1ps +/* + * File : EXMEM_Stage.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 9-Jun-2011 GEA Initial design. + * 2.0 26-Jul-2012 GEA Many updates have been made. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * The Pipeline Register to bridge the Execute and Memory stages. + */ +module EXMEM_Stage( + input clock, + input reset, + input EX_Flush, + input EX_Stall, + input M_Stall, + // Control Signals + input EX_Movn, + input EX_Movz, + input EX_BZero, + input EX_RegWrite, // Future Control to WB + input EX_MemtoReg, // Future Control to WB + input EX_ReverseEndian, + input EX_LLSC, + input EX_MemRead, + input EX_MemWrite, + input EX_MemByte, + input EX_MemHalf, + input EX_MemSignExtend, + input EX_Left, + input EX_Right, + // Exception Control/Info + input EX_KernelMode, + input [31:0] EX_RestartPC, + input EX_IsBDS, + input EX_Trap, + input EX_TrapCond, + input EX_M_CanErr, + // Data Signals + input [31:0] EX_ALU_Result, + input [31:0] EX_ReadData2, + input [4:0] EX_RtRd, + // ------------------ + output reg M_RegWrite, + output reg M_MemtoReg, + output reg M_ReverseEndian, + output reg M_LLSC, + output reg M_MemRead, + output reg M_MemWrite, + output reg M_MemByte, + output reg M_MemHalf, + output reg M_MemSignExtend, + output reg M_Left, + output reg M_Right, + output reg M_KernelMode, + output reg [31:0] M_RestartPC, + output reg M_IsBDS, + output reg M_Trap, + output reg M_TrapCond, + output reg M_M_CanErr, + output reg [31:0] M_ALU_Result, + output reg [31:0] M_ReadData2, + output reg [4:0] M_RtRd + ); + + /*** + The purpose of a pipeline register is to capture data from one pipeline stage + and provide it to the next pipeline stage. This creates at least one clock cycle + of delay, but reduces the combinatorial path length of signals which allows for + higher clock speeds. + + All pipeline registers update unless the forward stage is stalled. When this occurs + or when the current stage is being flushed, the forward stage will receive data that + is effectively a NOP and causes nothing to happen throughout the remaining pipeline + traversal. In other words: + + A stall masks all control signals to forward stages. A flush permanently clears + control signals to forward stages (but not certain data for exception purposes). + ***/ + + // Mask of RegWrite if a Move Conditional failed. + wire MovcRegWrite = (EX_Movn & ~EX_BZero) | (EX_Movz & EX_BZero); + + always @(posedge clock) begin + M_RegWrite <= (reset) ? 0 : ((M_Stall) ? M_RegWrite : ((EX_Stall | EX_Flush) ? 0 : EX_RegWrite)); + M_RegWrite <= (reset) ? 0 : ((M_Stall) ? M_RegWrite : ((EX_Stall | EX_Flush) ? 0 : ((EX_Movn | EX_Movz) ? MovcRegWrite : EX_RegWrite))); + M_MemtoReg <= (reset) ? 0 : ((M_Stall) ? M_MemtoReg : EX_MemtoReg); + M_ReverseEndian <= (reset) ? 0 : ((M_Stall) ? M_ReverseEndian : EX_ReverseEndian); + M_LLSC <= (reset) ? 0 : ((M_Stall) ? M_LLSC : EX_LLSC); + M_MemRead <= (reset) ? 0 : ((M_Stall) ? M_MemRead : ((EX_Stall | EX_Flush) ? 0 : EX_MemRead)); + M_MemWrite <= (reset) ? 0 : ((M_Stall) ? M_MemWrite : ((EX_Stall | EX_Flush) ? 0 : EX_MemWrite)); + M_MemByte <= (reset) ? 0 : ((M_Stall) ? M_MemByte : EX_MemByte); + M_MemHalf <= (reset) ? 0 : ((M_Stall) ? M_MemHalf : EX_MemHalf); + M_MemSignExtend <= (reset) ? 0 : ((M_Stall) ? M_MemSignExtend : EX_MemSignExtend); + M_Left <= (reset) ? 0 : ((M_Stall) ? M_Left : EX_Left); + M_Right <= (reset) ? 0 : ((M_Stall) ? M_Right : EX_Right); + M_KernelMode <= (reset) ? 0 : ((M_Stall) ? M_KernelMode : EX_KernelMode); + M_RestartPC <= (reset) ? 32'b0 : ((M_Stall) ? M_RestartPC : EX_RestartPC); + M_IsBDS <= (reset) ? 0 : ((M_Stall) ? M_IsBDS : EX_IsBDS); + M_Trap <= (reset) ? 0 : ((M_Stall) ? M_Trap : ((EX_Stall | EX_Flush) ? 0 : EX_Trap)); + M_TrapCond <= (reset) ? 0 : ((M_Stall) ? M_TrapCond : EX_TrapCond); + M_M_CanErr <= (reset) ? 0 : ((M_Stall) ? M_M_CanErr : ((EX_Stall | EX_Flush) ? 0 : EX_M_CanErr)); + M_ALU_Result <= (reset) ? 32'b0 : ((M_Stall) ? M_ALU_Result : EX_ALU_Result); + M_ReadData2 <= (reset) ? 32'b0 : ((M_Stall) ? M_ReadData2 : EX_ReadData2); + M_RtRd <= (reset) ? 5'b0 : ((M_Stall) ? M_RtRd : EX_RtRd); + end + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/Hazard_Detection.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/Hazard_Detection.v new file mode 100755 index 0000000..b719664 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/Hazard_Detection.v @@ -0,0 +1,175 @@ +`timescale 1ns / 1ps +/* + * File : Hazard_Detection.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 23-Jul-2011 GEA Initial design. + * 2.0 26-May-2012 GEA Release version with CP0. + * 2.01 1-Nov-2012 GEA Fixed issue with Jal. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * Hazard Detection and Forward Control. This is the glue that allows a + * pipelined processor to operate efficiently and correctly in the presence + * of data, structural, and control hazards. For each pipeline stage, it + * detects whether that stage requires data that is still in the pipeline, + * and whether that data may be forwarded or if the pipeline must be stalled. + * + * This module is heavily commented. Read below for more information. + */ +module Hazard_Detection( + input [7:0] DP_Hazards, + input [4:0] ID_Rs, + input [4:0] ID_Rt, + input [4:0] EX_Rs, + input [4:0] EX_Rt, + input [4:0] EX_RtRd, + input [4:0] MEM_RtRd, + input [4:0] WB_RtRd, + input EX_Link, + input EX_RegWrite, + input MEM_RegWrite, + input WB_RegWrite, + input MEM_MemRead, + input MEM_MemWrite, // Needed for Store Conditional which writes to a register + input InstMem_Read, + input InstMem_Ready, + input Mfc0, // Using fwd mux; not part of haz/fwd. + input IF_Exception_Stall, + input ID_Exception_Stall, + input EX_Exception_Stall, + input EX_ALU_Stall, + input M_Stall_Controller, // Determined by data memory controller + output IF_Stall, + output ID_Stall, + output EX_Stall, + output M_Stall, + output WB_Stall, + output [1:0] ID_RsFwdSel, + output [1:0] ID_RtFwdSel, + output [1:0] EX_RsFwdSel, + output [1:0] EX_RtFwdSel, + output M_WriteDataFwdSel + ); + + /* Hazard and Forward Detection + * + * Most instructions read from one or more registers. Normally this occurs in + * the ID stage. However, frequently the register file in the ID stage is stale + * when one or more forward stages in the pipeline (EX, MEM, or WB) contains + * an instruction which will eventually update it but has not yet done so. + * + * A hazard condition is created when a forward pipeline stage is set to write + * the same register that a current pipeline stage (e.g. in ID) needs to read. + * The solution is to stall the current stage (and effectively all stages behind + * it) or bypass (forward) the data from forward stages. Fortunately forwarding + * works for most combinations of instructions. + * + * Hazard and Forward conditions are handled based on two simple rules: + * "Wants" and "Needs." If an instruction "wants" data in a certain pipeline + * stage, and that data is available further along in the pipeline, it will + * be forwarded. If it "needs" data and the data is not yet available for forwarding, + * the pipeline stage stalls. If it does not want or need data in a certain + * stage, forwarding is disabled and a stall will not occur. This is important + * for instructions which insert custom data, such as jal or movz. + * + * Currently, "Want" and "Need" conditions are defined for both Rs data and Rt + * data (the two read registers in MIPS), and these conditions exist in the + * ID and EX pipeline stages. This is a total of eight condition bits. + * + * A unique exception exists with Store instructions, which don't need the + * "Rt" data until the MEM stage. Because data doesn't change in WB, and WB + * is the only stage following MEM, forwarding is *always* possible from + * WB to Mem. This unit handles this situation, and a condition bit is not + * needed. + * + * When data is needed from the MEM stage by a previous stage (ID or EX), the + * decision to forward or stall is based on whether MEM is accessing memory + * (stall) or not (forward). Normally store instructions don't write to registers + * and thus are never needed for a data dependence, so the signal 'MEM_MemRead' + * is sufficient to determine. Because of the Store Conditional instruction, + * however, 'MEM_MemWrite' must also be considered because it writes to a register. + * + */ + + wire WantRsByID, NeedRsByID, WantRtByID, NeedRtByID, WantRsByEX, NeedRsByEX, WantRtByEX, NeedRtByEX; + assign WantRsByID = DP_Hazards[7]; + assign NeedRsByID = DP_Hazards[6]; + assign WantRtByID = DP_Hazards[5]; + assign NeedRtByID = DP_Hazards[4]; + assign WantRsByEX = DP_Hazards[3]; + assign NeedRsByEX = DP_Hazards[2]; + assign WantRtByEX = DP_Hazards[1]; + assign NeedRtByEX = DP_Hazards[0]; + + // Trick allowed by RegDst = 0 which gives Rt. MEM_Rt is only used on + // Data Memory write operations (stores), and RegWrite is always 0 in this case. + wire [4:0] MEM_Rt = MEM_RtRd; + + // Forwarding should not happen when the src/dst register is $zero + wire EX_RtRd_NZ = (EX_RtRd != 5'b00000); + wire MEM_RtRd_NZ = (MEM_RtRd != 5'b00000); + wire WB_RtRd_NZ = (WB_RtRd != 5'b00000); + + // ID Dependencies + wire Rs_IDEX_Match = (ID_Rs == EX_RtRd) & EX_RtRd_NZ & (WantRsByID | NeedRsByID) & EX_RegWrite; + wire Rt_IDEX_Match = (ID_Rt == EX_RtRd) & EX_RtRd_NZ & (WantRtByID | NeedRtByID) & EX_RegWrite; + wire Rs_IDMEM_Match = (ID_Rs == MEM_RtRd) & MEM_RtRd_NZ & (WantRsByID | NeedRsByID) & MEM_RegWrite; + wire Rt_IDMEM_Match = (ID_Rt == MEM_RtRd) & MEM_RtRd_NZ & (WantRtByID | NeedRtByID) & MEM_RegWrite; + wire Rs_IDWB_Match = (ID_Rs == WB_RtRd) & WB_RtRd_NZ & (WantRsByID | NeedRsByID) & WB_RegWrite; + wire Rt_IDWB_Match = (ID_Rt == WB_RtRd) & WB_RtRd_NZ & (WantRtByID | NeedRtByID) & WB_RegWrite; + // EX Dependencies + wire Rs_EXMEM_Match = (EX_Rs == MEM_RtRd) & MEM_RtRd_NZ & (WantRsByEX | NeedRsByEX) & MEM_RegWrite; + wire Rt_EXMEM_Match = (EX_Rt == MEM_RtRd) & MEM_RtRd_NZ & (WantRtByEX | NeedRtByEX) & MEM_RegWrite; + wire Rs_EXWB_Match = (EX_Rs == WB_RtRd) & WB_RtRd_NZ & (WantRsByEX | NeedRsByEX) & WB_RegWrite; + wire Rt_EXWB_Match = (EX_Rt == WB_RtRd) & WB_RtRd_NZ & (WantRtByEX | NeedRtByEX) & WB_RegWrite; + // MEM Dependencies + wire Rt_MEMWB_Match = (MEM_Rt == WB_RtRd) & WB_RtRd_NZ & WB_RegWrite; + + + // ID needs data from EX : Stall + wire ID_Stall_1 = (Rs_IDEX_Match & NeedRsByID); + wire ID_Stall_2 = (Rt_IDEX_Match & NeedRtByID); + // ID needs data from MEM : Stall if mem access + wire ID_Stall_3 = (Rs_IDMEM_Match & (MEM_MemRead | MEM_MemWrite) & NeedRsByID); + wire ID_Stall_4 = (Rt_IDMEM_Match & (MEM_MemRead | MEM_MemWrite) & NeedRtByID); + // ID wants data from MEM : Forward if not mem access + wire ID_Fwd_1 = (Rs_IDMEM_Match & ~(MEM_MemRead | MEM_MemWrite)); + wire ID_Fwd_2 = (Rt_IDMEM_Match & ~(MEM_MemRead | MEM_MemWrite)); + // ID wants/needs data from WB : Forward + wire ID_Fwd_3 = (Rs_IDWB_Match); + wire ID_Fwd_4 = (Rt_IDWB_Match); + // EX needs data from MEM : Stall if mem access + wire EX_Stall_1 = (Rs_EXMEM_Match & (MEM_MemRead | MEM_MemWrite) & NeedRsByEX); + wire EX_Stall_2 = (Rt_EXMEM_Match & (MEM_MemRead | MEM_MemWrite) & NeedRtByEX); + // EX wants data from MEM : Forward if not mem access + wire EX_Fwd_1 = (Rs_EXMEM_Match & ~(MEM_MemRead | MEM_MemWrite)); + wire EX_Fwd_2 = (Rt_EXMEM_Match & ~(MEM_MemRead | MEM_MemWrite)); + // EX wants/needs data from WB : Forward + wire EX_Fwd_3 = (Rs_EXWB_Match); + wire EX_Fwd_4 = (Rt_EXWB_Match); + // MEM needs data from WB : Forward + wire MEM_Fwd_1 = (Rt_MEMWB_Match); + + + // Stalls and Control Flow Final Assignments + assign WB_Stall = M_Stall; + assign M_Stall = IF_Stall | M_Stall_Controller; + assign EX_Stall = (EX_Stall_1 | EX_Stall_2 | EX_Exception_Stall) | EX_ALU_Stall | M_Stall; + assign ID_Stall = (ID_Stall_1 | ID_Stall_2 | ID_Stall_3 | ID_Stall_4 | ID_Exception_Stall) | EX_Stall; + assign IF_Stall = InstMem_Read | InstMem_Ready | IF_Exception_Stall; + + // Forwarding Control Final Assignments + assign ID_RsFwdSel = (ID_Fwd_1) ? 2'b01 : ((ID_Fwd_3) ? 2'b10 : 2'b00); + assign ID_RtFwdSel = (Mfc0) ? 2'b11 : ((ID_Fwd_2) ? 2'b01 : ((ID_Fwd_4) ? 2'b10 : 2'b00)); + assign EX_RsFwdSel = (EX_Link) ? 2'b11 : ((EX_Fwd_1) ? 2'b01 : ((EX_Fwd_3) ? 2'b10 : 2'b00)); + assign EX_RtFwdSel = (EX_Link) ? 2'b11 : ((EX_Fwd_2) ? 2'b01 : ((EX_Fwd_4) ? 2'b10 : 2'b00)); + assign M_WriteDataFwdSel = MEM_Fwd_1; + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/IDEX_Stage.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/IDEX_Stage.v new file mode 100755 index 0000000..3cdaaee --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/IDEX_Stage.v @@ -0,0 +1,159 @@ +`timescale 1ns / 1ps +/* + * File : IDEX_Stage.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 9-Jun-2011 GEA Initial design. + * 2.0 26-Jul-2012 GEA Many updates have been made. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * The Pipeline Register to bridge the Instruction Decode + * and Execute stages. + */ +module IDEX_Stage( + input clock, + input reset, + input ID_Flush, + input ID_Stall, + input EX_Stall, + // Control Signals + input ID_Link, + input ID_RegDst, + input ID_ALUSrcImm, + input [4:0] ID_ALUOp, + input ID_Movn, + input ID_Movz, + input ID_LLSC, + input ID_MemRead, + input ID_MemWrite, + input ID_MemByte, + input ID_MemHalf, + input ID_MemSignExtend, + input ID_Left, + input ID_Right, + input ID_RegWrite, + input ID_MemtoReg, + input ID_ReverseEndian, + // Hazard & Forwarding + input [4:0] ID_Rs, + input [4:0] ID_Rt, + input ID_WantRsByEX, + input ID_NeedRsByEX, + input ID_WantRtByEX, + input ID_NeedRtByEX, + // Exception Control/Info + input ID_KernelMode, + input [31:0] ID_RestartPC, + input ID_IsBDS, + input ID_Trap, + input ID_TrapCond, + input ID_EX_CanErr, + input ID_M_CanErr, + // Data Signals + input [31:0] ID_ReadData1, + input [31:0] ID_ReadData2, + input [16:0] ID_SignExtImm, // ID_Rd, ID_Shamt included here + // ---------------- + output reg EX_Link, + output [1:0] EX_LinkRegDst, + output reg EX_ALUSrcImm, + output reg [4:0] EX_ALUOp, + output reg EX_Movn, + output reg EX_Movz, + output reg EX_LLSC, + output reg EX_MemRead, + output reg EX_MemWrite, + output reg EX_MemByte, + output reg EX_MemHalf, + output reg EX_MemSignExtend, + output reg EX_Left, + output reg EX_Right, + output reg EX_RegWrite, + output reg EX_MemtoReg, + output reg EX_ReverseEndian, + output reg [4:0] EX_Rs, + output reg [4:0] EX_Rt, + output reg EX_WantRsByEX, + output reg EX_NeedRsByEX, + output reg EX_WantRtByEX, + output reg EX_NeedRtByEX, + output reg EX_KernelMode, + output reg [31:0] EX_RestartPC, + output reg EX_IsBDS, + output reg EX_Trap, + output reg EX_TrapCond, + output reg EX_EX_CanErr, + output reg EX_M_CanErr, + output reg [31:0] EX_ReadData1, + output reg [31:0] EX_ReadData2, + output [31:0] EX_SignExtImm, + output [4:0] EX_Rd, + output [4:0] EX_Shamt + ); + + /*** + The purpose of a pipeline register is to capture data from one pipeline stage + and provide it to the next pipeline stage. This creates at least one clock cycle + of delay, but reduces the combinatorial path length of signals which allows for + higher clock speeds. + + All pipeline registers update unless the forward stage is stalled. When this occurs + or when the current stage is being flushed, the forward stage will receive data that + is effectively a NOP and causes nothing to happen throughout the remaining pipeline + traversal. In other words: + + A stall masks all control signals to forward stages. A flush permanently clears + control signals to forward stages (but not certain data for exception purposes). + ***/ + + reg [16:0] EX_SignExtImm_pre; + reg EX_RegDst; + assign EX_LinkRegDst = (EX_Link) ? 2'b10 : ((EX_RegDst) ? 2'b01 : 2'b00); + assign EX_Rd = EX_SignExtImm[15:11]; + assign EX_Shamt = EX_SignExtImm[10:6]; + assign EX_SignExtImm = (EX_SignExtImm_pre[16]) ? {15'h7fff, EX_SignExtImm_pre[16:0]} : {15'h0000, EX_SignExtImm_pre[16:0]}; + + always @(posedge clock) begin + EX_Link <= (reset) ? 0 : ((EX_Stall) ? EX_Link : ID_Link); + EX_RegDst <= (reset) ? 0 : ((EX_Stall) ? EX_RegDst : ID_RegDst); + EX_ALUSrcImm <= (reset) ? 0 : ((EX_Stall) ? EX_ALUSrcImm : ID_ALUSrcImm); + EX_ALUOp <= (reset) ? 5'b0 : ((EX_Stall) ? EX_ALUOp : ((ID_Stall | ID_Flush) ? 5'b0 : ID_ALUOp)); + EX_Movn <= (reset) ? 0 : ((EX_Stall) ? EX_Movn : ID_Movn); + EX_Movz <= (reset) ? 0 : ((EX_Stall) ? EX_Movz : ID_Movz); + EX_LLSC <= (reset) ? 0 : ((EX_Stall) ? EX_LLSC : ID_LLSC); + EX_MemRead <= (reset) ? 0 : ((EX_Stall) ? EX_MemRead : ((ID_Stall | ID_Flush) ? 0 : ID_MemRead)); + EX_MemWrite <= (reset) ? 0 : ((EX_Stall) ? EX_MemWrite : ((ID_Stall | ID_Flush) ? 0 : ID_MemWrite)); + EX_MemByte <= (reset) ? 0 : ((EX_Stall) ? EX_MemByte : ID_MemByte); + EX_MemHalf <= (reset) ? 0 : ((EX_Stall) ? EX_MemHalf : ID_MemHalf); + EX_MemSignExtend <= (reset) ? 0 : ((EX_Stall) ? EX_MemSignExtend : ID_MemSignExtend); + EX_Left <= (reset) ? 0 : ((EX_Stall) ? EX_Left : ID_Left); + EX_Right <= (reset) ? 0 : ((EX_Stall) ? EX_Right : ID_Right); + EX_RegWrite <= (reset) ? 0 : ((EX_Stall) ? EX_RegWrite : ((ID_Stall | ID_Flush) ? 0 : ID_RegWrite)); + EX_MemtoReg <= (reset) ? 0 : ((EX_Stall) ? EX_MemtoReg : ID_MemtoReg); + EX_ReverseEndian <= (reset) ? 0 : ((EX_Stall) ? EX_ReverseEndian : ID_ReverseEndian); + EX_RestartPC <= (reset) ? 32'b0 : ((EX_Stall) ? EX_RestartPC : ID_RestartPC); + EX_IsBDS <= (reset) ? 0 : ((EX_Stall) ? EX_IsBDS : ID_IsBDS); + EX_Trap <= (reset) ? 0 : ((EX_Stall) ? EX_Trap : ((ID_Stall | ID_Flush) ? 0 : ID_Trap)); + EX_TrapCond <= (reset) ? 0 : ((EX_Stall) ? EX_TrapCond : ID_TrapCond); + EX_EX_CanErr <= (reset) ? 0 : ((EX_Stall) ? EX_EX_CanErr : ((ID_Stall | ID_Flush) ? 0 : ID_EX_CanErr)); + EX_M_CanErr <= (reset) ? 0 : ((EX_Stall) ? EX_M_CanErr : ((ID_Stall | ID_Flush) ? 0 : ID_M_CanErr)); + EX_ReadData1 <= (reset) ? 32'b0 : ((EX_Stall) ? EX_ReadData1 : ID_ReadData1); + EX_ReadData2 <= (reset) ? 32'b0 : ((EX_Stall) ? EX_ReadData2 : ID_ReadData2); + EX_SignExtImm_pre <= (reset) ? 17'b0 : ((EX_Stall) ? EX_SignExtImm_pre : ID_SignExtImm); + EX_Rs <= (reset) ? 5'b0 : ((EX_Stall) ? EX_Rs : ID_Rs); + EX_Rt <= (reset) ? 5'b0 : ((EX_Stall) ? EX_Rt : ID_Rt); + EX_WantRsByEX <= (reset) ? 0 : ((EX_Stall) ? EX_WantRsByEX : ((ID_Stall | ID_Flush) ? 0 : ID_WantRsByEX)); + EX_NeedRsByEX <= (reset) ? 0 : ((EX_Stall) ? EX_NeedRsByEX : ((ID_Stall | ID_Flush) ? 0 : ID_NeedRsByEX)); + EX_WantRtByEX <= (reset) ? 0 : ((EX_Stall) ? EX_WantRtByEX : ((ID_Stall | ID_Flush) ? 0 : ID_WantRtByEX)); + EX_NeedRtByEX <= (reset) ? 0 : ((EX_Stall) ? EX_NeedRtByEX : ((ID_Stall | ID_Flush) ? 0 : ID_NeedRtByEX)); + EX_KernelMode <= (reset) ? 0 : ((EX_Stall) ? EX_KernelMode : ID_KernelMode); + end + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/IFID_Stage.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/IFID_Stage.v new file mode 100755 index 0000000..f6c7435 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/IFID_Stage.v @@ -0,0 +1,75 @@ +`timescale 1ns / 1ps +/* + * File : IFID_Stage.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 9-Jun-2011 GEA Initial design. + * 2.0 26-Jul-2012 GEA Many updates have been made. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * The Pipeline Register to bridge the Instruction Fetch + * and Instruction Decode stages. + */ +module IFID_Stage( + input clock, + input reset, + input IF_Flush, + input IF_Stall, + input ID_Stall, + // Control Signals + input [31:0] IF_Instruction, + // Data Signals + input [31:0] IF_PCAdd4, + input [31:0] IF_PC, + input IF_IsBDS, + // ------------------ + output reg [31:0] ID_Instruction, + output reg [31:0] ID_PCAdd4, + output reg [31:0] ID_RestartPC, + output reg ID_IsBDS, + output reg ID_IsFlushed + ); + + /*** + The purpose of a pipeline register is to capture data from one pipeline stage + and provide it to the next pipeline stage. This creates at least one clock cycle + of delay, but reduces the combinatorial path length of signals which allows for + higher clock speeds. + + All pipeline registers update unless the forward stage is stalled. When this occurs + or when the current stage is being flushed, the forward stage will receive data that + is effectively a NOP and causes nothing to happen throughout the remaining pipeline + traversal. In other words: + + A stall masks all control signals to forward stages. A flush permanently clears + control signals to forward stages (but not certain data for exception purposes). + ***/ + + + /*** + The signal 'ID_IsFlushed' is needed because of interrupts. Normally, a flushed instruction + is a NOP which will never cause an exception and thus its restart PC will never be needed + or used. However, interrupts are detected in ID and may occur when any instruction, flushed + or not, is in the ID stage. It is an error to save the restart PC of a flushed instruction + since it was never supposed to execute (such as the "delay slot" after ERET or the branch + delay slot after a canceled Branch Likely instruction). A simple way to prevent this is to + pass a signal to ID indicating that its instruction was flushed. Interrupt detection is then + masked when this signal is high, and the interrupt will trigger on the next instruction load to ID. + ***/ + + always @(posedge clock) begin + ID_Instruction <= (reset) ? 32'b0 : ((ID_Stall) ? ID_Instruction : ((IF_Stall | IF_Flush) ? 32'b0 : IF_Instruction)); + ID_PCAdd4 <= (reset) ? 32'b0 : ((ID_Stall) ? ID_PCAdd4 : IF_PCAdd4); + ID_IsBDS <= (reset) ? 0 : ((ID_Stall) ? ID_IsBDS : IF_IsBDS); + ID_RestartPC <= (reset) ? 32'b0 : ((ID_Stall | IF_IsBDS) ? ID_RestartPC : IF_PC); + ID_IsFlushed <= (reset) ? 0 : ((ID_Stall) ? ID_IsFlushed : IF_Flush); + end + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/MEMWB_Stage.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/MEMWB_Stage.v new file mode 100755 index 0000000..5c22049 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/MEMWB_Stage.v @@ -0,0 +1,74 @@ +`timescale 1ns / 1ps +/* + * File : MEMWB_Stage.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 9-Jun-2011 GEA Initial design. + * 2.0 26-Jul-2012 GEA Many updates have been made. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * The Pipeline Register to bridge the Memory and Writeback stages. + */ +module MEMWB_Stage( + input clock, + input reset, + input M_Flush, + input M_Stall, + input WB_Stall, + // Control Signals + input M_RegWrite, + input M_MemtoReg, + // Data Signals + input [31:0] M_ReadData, + input [31:0] M_ALU_Result, + input [4:0] M_RtRd, + // ---------------- + output reg WB_RegWrite, + output reg WB_MemtoReg, + output reg [31:0] WB_ReadData, + output reg [31:0] WB_ALU_Result, + output reg [4:0] WB_RtRd + ); + + + /*** + The purpose of a pipeline register is to capture data from one pipeline stage + and provide it to the next pipeline stage. This creates at least one clock cycle + of delay, but reduces the combinatorial path length of signals which allows for + higher clock speeds. + + All pipeline registers update unless the forward stage is stalled. When this occurs + or when the current stage is being flushed, the forward stage will receive data that + is effectively a NOP and causes nothing to happen throughout the remaining pipeline + traversal. In other words: + + A stall masks all control signals to forward stages. A flush permanently clears + control signals to forward stages (but not certain data for exception purposes). + + Since WB is the final stage in the pipeline, it would normally never stall. + However, because the MEM stage may be using data forwarded from WB, WB must stall + when MEM is stalled. If it didn't, the forward data would not be preserved. If + the processor didn't forward any data, a stall would not be needed. + + In practice, the only time WB stalls is when forwarding for a Lw->Sw sequence, since + MEM doesn't need the data until its stage, but it does not latch the forwarded data. + This means WB_Stall is probably identical to M_Stall. There is no speed difference by + allowing WB to stall. + ***/ + + always @(posedge clock) begin + WB_RegWrite <= (reset) ? 0 : ((WB_Stall) ? WB_RegWrite : ((M_Stall | M_Flush) ? 0 : M_RegWrite)); + WB_MemtoReg <= (reset) ? 0 : ((WB_Stall) ? WB_MemtoReg : M_MemtoReg); + WB_ReadData <= (reset) ? 32'b0 : ((WB_Stall) ? WB_ReadData : M_ReadData); + WB_ALU_Result <= (reset) ? 32'b0 : ((WB_Stall) ? WB_ALU_Result : M_ALU_Result); + WB_RtRd <= (reset) ? 5'b0 : ((WB_Stall) ? WB_RtRd : M_RtRd); + end + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/MIPS_Parameters.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/MIPS_Parameters.v new file mode 100755 index 0000000..7a994ef --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/MIPS_Parameters.v @@ -0,0 +1,631 @@ +/* + * File : MIPS_Parameters.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 26-May-2012 GEA Release version. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * Provides a language abstraction for the MIPS32-specific op-codes and + * the processor-specific datapath, hazard, and exception bits which + * control the processor. These parameter names are used extensively + * throughout the processor HDL modules. + */ + + +/*** Exception Vector Locations *** + + When the CPU powers up or is reset, it will begin execution at 'EXC_Vector_Base_Reset'. + All other exceptions are the sum of a base address and offset: + - The base address is either a bootstrap or normal value. It is controlled by + the 'BEV' bit in the CP0 'Status' register. Both base addresses can be mapped to + the same location. + - The offset address is either a standard offset (which is always used for + non-interrupt general exceptions in this processor because it lacks TLB Refill + and Cache errors), or a special interrupt-only offset for interrupts, which is + enabled with the 'IV' bit in the CP0 'Cause' register. + + Current Setup: + General exceptions go to 0x0. Interrupts go to 0x8. Booting starts at 0x10. +*/ +parameter [31:0] EXC_Vector_Base_Reset = 32'h0000_0010; // MIPS Standard is 0xBFC0_0000 +parameter [31:0] EXC_Vector_Base_Other_NoBoot = 32'h0000_0000; // MIPS Standard is 0x8000_0000 +parameter [31:0] EXC_Vector_Base_Other_Boot = 32'h0000_0000; // MIPS Standard is 0xBFC0_0200 +parameter [31:0] EXC_Vector_Offset_General = 32'h0000_0000; // MIPS Standard is 0x0000_0180 +parameter [31:0] EXC_Vector_Offset_Special = 32'h0000_0008; // MIPS Standard is 0x0000_0200 + + + +/*** Kernel/User Memory Areas *** + + Kernel memory starts at address 0x0. User memory starts at 'UMem_Lower' and extends to + the end of the address space. + + A distinction is made to protect against accesses to kernel memory while the processor + is in user mode. Lacking MMU hardware, these addresses are physical, not virtual. + This simple two-part division of the address space can be extended almost arbitrarily + in the Data Memory Controller. Note that there is currently no user/kernel space check + for the Instruction Memory, because it is assumed that instructions are in the kernel space. +*/ +parameter [31:0] UMem_Lower = 32'h08000000; + + + +/*** Processor Endianness *** + + The MIPS Configuration Register (CP0 Register 16 Select 0) specifies the processor's + endianness. A processor in user mode may switch to reverse endianness, which will be + the opposite of this parameter. +*/ +parameter Big_Endian = 1; + + + +/*** Encodings for MIPS32 Release 1 Architecture ***/ + + +/* Op Code Categories */ +parameter [5:0] Op_Type_R = 6'b00_0000; // Standard R-Type instructions +parameter [5:0] Op_Type_R2 = 6'b01_1100; // Extended R-Like instructions +parameter [5:0] Op_Type_BI = 6'b00_0001; // Branch/Trap extended instructions +parameter [5:0] Op_Type_CP0 = 6'b01_0000; // Coprocessor 0 instructions +parameter [5:0] Op_Type_CP1 = 6'b01_0001; // Coprocessor 1 instructions (not implemented) +parameter [5:0] Op_Type_CP2 = 6'b01_0010; // Coprocessor 2 instructions (not implemented) +parameter [5:0] Op_Type_CP3 = 6'b01_0011; // Coprocessor 3 instructions (not implemented) +// -------------------------------------- +parameter [5:0] Op_Add = Op_Type_R; +parameter [5:0] Op_Addi = 6'b00_1000; +parameter [5:0] Op_Addiu = 6'b00_1001; +parameter [5:0] Op_Addu = Op_Type_R; +parameter [5:0] Op_And = Op_Type_R; +parameter [5:0] Op_Andi = 6'b00_1100; +parameter [5:0] Op_Beq = 6'b00_0100; +parameter [5:0] Op_Bgez = Op_Type_BI; +parameter [5:0] Op_Bgezal = Op_Type_BI; +parameter [5:0] Op_Bgtz = 6'b00_0111; +parameter [5:0] Op_Blez = 6'b00_0110; +parameter [5:0] Op_Bltz = Op_Type_BI; +parameter [5:0] Op_Bltzal = Op_Type_BI; +parameter [5:0] Op_Bne = 6'b00_0101; +parameter [5:0] Op_Break = Op_Type_R; +parameter [5:0] Op_Clo = Op_Type_R2; +parameter [5:0] Op_Clz = Op_Type_R2; +parameter [5:0] Op_Div = Op_Type_R; +parameter [5:0] Op_Divu = Op_Type_R; +parameter [5:0] Op_Eret = Op_Type_CP0; +parameter [5:0] Op_J = 6'b00_0010; +parameter [5:0] Op_Jal = 6'b00_0011; +parameter [5:0] Op_Jalr = Op_Type_R; +parameter [5:0] Op_Jr = Op_Type_R; +parameter [5:0] Op_Lb = 6'b10_0000; +parameter [5:0] Op_Lbu = 6'b10_0100; +parameter [5:0] Op_Lh = 6'b10_0001; +parameter [5:0] Op_Lhu = 6'b10_0101; +parameter [5:0] Op_Ll = 6'b11_0000; +parameter [5:0] Op_Lui = 6'b00_1111; +parameter [5:0] Op_Lw = 6'b10_0011; +parameter [5:0] Op_Lwl = 6'b10_0010; +parameter [5:0] Op_Lwr = 6'b10_0110; +parameter [5:0] Op_Madd = Op_Type_R2; +parameter [5:0] Op_Maddu = Op_Type_R2; +parameter [5:0] Op_Mfc0 = Op_Type_CP0; +parameter [5:0] Op_Mfhi = Op_Type_R; +parameter [5:0] Op_Mflo = Op_Type_R; +parameter [5:0] Op_Movn = Op_Type_R; +parameter [5:0] Op_Movz = Op_Type_R; +parameter [5:0] Op_Msub = Op_Type_R2; +parameter [5:0] Op_Msubu = Op_Type_R2; +parameter [5:0] Op_Mtc0 = Op_Type_CP0; +parameter [5:0] Op_Mthi = Op_Type_R; +parameter [5:0] Op_Mtlo = Op_Type_R; +parameter [5:0] Op_Mul = Op_Type_R2; +parameter [5:0] Op_Mult = Op_Type_R; +parameter [5:0] Op_Multu = Op_Type_R; +parameter [5:0] Op_Nor = Op_Type_R; +parameter [5:0] Op_Or = Op_Type_R; +parameter [5:0] Op_Ori = 6'b00_1101; +parameter [5:0] Op_Pref = 6'b11_0011; // Prefetch does nothing in this implementation. +parameter [5:0] Op_Sb = 6'b10_1000; +parameter [5:0] Op_Sc = 6'b11_1000; +parameter [5:0] Op_Sh = 6'b10_1001; +parameter [5:0] Op_Sll = Op_Type_R; +parameter [5:0] Op_Sllv = Op_Type_R; +parameter [5:0] Op_Slt = Op_Type_R; +parameter [5:0] Op_Slti = 6'b00_1010; +parameter [5:0] Op_Sltiu = 6'b00_1011; +parameter [5:0] Op_Sltu = Op_Type_R; +parameter [5:0] Op_Sra = Op_Type_R; +parameter [5:0] Op_Srav = Op_Type_R; +parameter [5:0] Op_Srl = Op_Type_R; +parameter [5:0] Op_Srlv = Op_Type_R; +parameter [5:0] Op_Sub = Op_Type_R; +parameter [5:0] Op_Subu = Op_Type_R; +parameter [5:0] Op_Sw = 6'b10_1011; +parameter [5:0] Op_Swl = 6'b10_1010; +parameter [5:0] Op_Swr = 6'b10_1110; +parameter [5:0] Op_Syscall = Op_Type_R; +parameter [5:0] Op_Teq = Op_Type_R; +parameter [5:0] Op_Teqi = Op_Type_BI; +parameter [5:0] Op_Tge = Op_Type_R; +parameter [5:0] Op_Tgei = Op_Type_BI; +parameter [5:0] Op_Tgeiu = Op_Type_BI; +parameter [5:0] Op_Tgeu = Op_Type_R; +parameter [5:0] Op_Tlt = Op_Type_R; +parameter [5:0] Op_Tlti = Op_Type_BI; +parameter [5:0] Op_Tltiu = Op_Type_BI; +parameter [5:0] Op_Tltu = Op_Type_R; +parameter [5:0] Op_Tne = Op_Type_R; +parameter [5:0] Op_Tnei = Op_Type_BI; +parameter [5:0] Op_Xor = Op_Type_R; +parameter [5:0] Op_Xori = 6'b00_1110; + +/* Op Code Rt fields for Branches & Traps */ +parameter [4:0] OpRt_Bgez = 5'b00001; +parameter [4:0] OpRt_Bgezal = 5'b10001; +parameter [4:0] OpRt_Bltz = 5'b00000; +parameter [4:0] OpRt_Bltzal = 5'b10000; +parameter [4:0] OpRt_Teqi = 5'b01100; +parameter [4:0] OpRt_Tgei = 5'b01000; +parameter [4:0] OpRt_Tgeiu = 5'b01001; +parameter [4:0] OpRt_Tlti = 5'b01010; +parameter [4:0] OpRt_Tltiu = 5'b01011; +parameter [4:0] OpRt_Tnei = 5'b01110; + +/* Op Code Rs fields for Coprocessors */ +parameter [4:0] OpRs_MF = 5'b00000; +parameter [4:0] OpRs_MT = 5'b00100; + +/* Special handling for ERET */ +parameter [4:0] OpRs_ERET = 5'b10000; +parameter [5:0] Funct_ERET = 6'b011000; + +/* Function Codes for R-Type Op Codes */ +parameter [5:0] Funct_Add = 6'b10_0000; +parameter [5:0] Funct_Addu = 6'b10_0001; +parameter [5:0] Funct_And = 6'b10_0100; +parameter [5:0] Funct_Break = 6'b00_1101; +parameter [5:0] Funct_Clo = 6'b10_0001; // same as Addu +parameter [5:0] Funct_Clz = 6'b10_0000; // same as Add +parameter [5:0] Funct_Div = 6'b01_1010; +parameter [5:0] Funct_Divu = 6'b01_1011; +parameter [5:0] Funct_Jr = 6'b00_1000; +parameter [5:0] Funct_Jalr = 6'b00_1001; +parameter [5:0] Funct_Madd = 6'b00_0000; +parameter [5:0] Funct_Maddu = 6'b00_0001; +parameter [5:0] Funct_Mfhi = 6'b01_0000; +parameter [5:0] Funct_Mflo = 6'b01_0010; +parameter [5:0] Funct_Movn = 6'b00_1011; +parameter [5:0] Funct_Movz = 6'b00_1010; +parameter [5:0] Funct_Msub = 6'b00_0100; // same as Sllv +parameter [5:0] Funct_Msubu = 6'b00_0101; +parameter [5:0] Funct_Mthi = 6'b01_0001; +parameter [5:0] Funct_Mtlo = 6'b01_0011; +parameter [5:0] Funct_Mul = 6'b00_0010; // same as Srl +parameter [5:0] Funct_Mult = 6'b01_1000; +parameter [5:0] Funct_Multu = 6'b01_1001; +parameter [5:0] Funct_Nor = 6'b10_0111; +parameter [5:0] Funct_Or = 6'b10_0101; +parameter [5:0] Funct_Sll = 6'b00_0000; +parameter [5:0] Funct_Sllv = 6'b00_0100; +parameter [5:0] Funct_Slt = 6'b10_1010; +parameter [5:0] Funct_Sltu = 6'b10_1011; +parameter [5:0] Funct_Sra = 6'b00_0011; +parameter [5:0] Funct_Srav = 6'b00_0111; +parameter [5:0] Funct_Srl = 6'b00_0010; +parameter [5:0] Funct_Srlv = 6'b00_0110; +parameter [5:0] Funct_Sub = 6'b10_0010; +parameter [5:0] Funct_Subu = 6'b10_0011; +parameter [5:0] Funct_Syscall = 6'b00_1100; +parameter [5:0] Funct_Teq = 6'b11_0100; +parameter [5:0] Funct_Tge = 6'b11_0000; +parameter [5:0] Funct_Tgeu = 6'b11_0001; +parameter [5:0] Funct_Tlt = 6'b11_0010; +parameter [5:0] Funct_Tltu = 6'b11_0011; +parameter [5:0] Funct_Tne = 6'b11_0110; +parameter [5:0] Funct_Xor = 6'b10_0110; + +/* ALU Operations (Implementation) */ +parameter [4:0] AluOp_Add = 5'd1; +parameter [4:0] AluOp_Addu = 5'd0; +parameter [4:0] AluOp_And = 5'd2; +parameter [4:0] AluOp_Clo = 5'd3; +parameter [4:0] AluOp_Clz = 5'd4; +parameter [4:0] AluOp_Div = 5'd5; +parameter [4:0] AluOp_Divu = 5'd6; +parameter [4:0] AluOp_Madd = 5'd7; +parameter [4:0] AluOp_Maddu = 5'd8; +parameter [4:0] AluOp_Mfhi = 5'd9; +parameter [4:0] AluOp_Mflo = 5'd10; +parameter [4:0] AluOp_Msub = 5'd13; +parameter [4:0] AluOp_Msubu = 5'd14; +parameter [4:0] AluOp_Mthi = 5'd11; +parameter [4:0] AluOp_Mtlo = 5'd12; +parameter [4:0] AluOp_Mul = 5'd15; +parameter [4:0] AluOp_Mult = 5'd16; +parameter [4:0] AluOp_Multu = 5'd17; +parameter [4:0] AluOp_Nor = 5'd18; +parameter [4:0] AluOp_Or = 5'd19; +parameter [4:0] AluOp_Sll = 5'd20; +parameter [4:0] AluOp_Sllc = 5'd21; // Move this if another AluOp is needed +parameter [4:0] AluOp_Sllv = 5'd22; +parameter [4:0] AluOp_Slt = 5'd23; +parameter [4:0] AluOp_Sltu = 5'd24; +parameter [4:0] AluOp_Sra = 5'd25; +parameter [4:0] AluOp_Srav = 5'd26; +parameter [4:0] AluOp_Srl = 5'd27; +parameter [4:0] AluOp_Srlv = 5'd28; +parameter [4:0] AluOp_Sub = 5'd29; +parameter [4:0] AluOp_Subu = 5'd30; +parameter [4:0] AluOp_Xor = 5'd31; + + +// Movc:10->11, Trap:9->10, TrapCond:8->9, RegDst:7->8 + +/*** Datapath *** + + All Signals are Active High. Branching and Jump signals (determined by "PCSrc"), + as well as ALU operation signals ("ALUOp") are handled by the controller and are not found here. + + Bit Name Description + ------------------------------ + 15: PCSrc (Instruction Type) + 14: 11: Instruction is Jump to Register + 10: Instruction is Branch + 01: Instruction is Jump to Immediate + 00: Instruction does not branch nor jump + 13: Link (Link on Branch/Jump) + ------------------------------ + 12: ALUSrc (ALU Source) [0=ALU input B is 2nd register file output; 1=Immediate value] + 11: Movc (Conditional Move) + 10: Trap (Trap Instruction) + 9 : TrapCond (Trap Condition) [0=ALU result is 0; 1=ALU result is not 0] + 8 : RegDst (Register File Target) [0=Rt field; 1=Rd field] + ------------------------------ + 7 : LLSC (Load Linked or Store Conditional) + 6 : MemRead (Data Memory Read) + 5 : MemWrite (Data Memory Write) + 4 : MemHalf (Half Word Memory Access) + 3 : MemByte (Byte size Memory Access) + 2 : MemSignExtend (Sign Extend Read Memory) [0=Zero Extend; 1=Sign Extend] + ------------------------------ + 1 : RegWrite (Register File Write) + 0 : MemtoReg (Memory to Register) [0=Register File write data is ALU output; 1=Is Data Memory] + ------------------------------ +*/ +parameter [15:0] DP_None = 16'b000_00000_000000_00; // Instructions which require nothing of the main datapath. +parameter [15:0] DP_RType = 16'b000_00001_000000_10; // Standard R-Type +parameter [15:0] DP_IType = 16'b000_10000_000000_10; // Standard I-Type +parameter [15:0] DP_Branch = 16'b100_00000_000000_00; // Standard Branch +parameter [15:0] DP_BranchLink = 16'b101_00000_000000_10; // Branch and Link +parameter [15:0] DP_HiLoWr = 16'b000_00000_000000_00; // Write to Hi/Lo ALU register (Div,Divu,Mult,Multu,Mthi,Mtlo). Currently 'DP_None'. +parameter [15:0] DP_Jump = 16'b010_00000_000000_00; // Standard Jump +parameter [15:0] DP_JumpLink = 16'b011_00000_000000_10; // Jump and Link +parameter [15:0] DP_JumpLinkReg = 16'b111_00000_000000_10; // Jump and Link Register +parameter [15:0] DP_JumpReg = 16'b110_00000_000000_00; // Jump Register +parameter [15:0] DP_LoadByteS = 16'b000_10000_010011_11; // Load Byte Signed +parameter [15:0] DP_LoadByteU = 16'b000_10000_010010_11; // Load Byte Unsigned +parameter [15:0] DP_LoadHalfS = 16'b000_10000_010101_11; // Load Half Signed +parameter [15:0] DP_LoadHalfU = 16'b000_10000_010100_11; // Load Half Unsigned +parameter [15:0] DP_LoadWord = 16'b000_10000_010000_11; // Load Word +parameter [15:0] DP_ExtWrRt = 16'b000_00000_000000_10; // A DP-external write to Rt +parameter [15:0] DP_ExtWrRd = 16'b000_00001_000000_10; // A DP-external write to Rd +parameter [15:0] DP_Movc = 16'b000_01001_000000_10; // Conditional Move +parameter [15:0] DP_LoadLinked = 16'b000_10000_110000_11; // Load Linked +parameter [15:0] DP_StoreCond = 16'b000_10000_101000_11; // Store Conditional +parameter [15:0] DP_StoreByte = 16'b000_10000_001010_00; // Store Byte +parameter [15:0] DP_StoreHalf = 16'b000_10000_001100_00; // Store Half +parameter [15:0] DP_StoreWord = 16'b000_10000_001000_00; // Store Word +parameter [15:0] DP_TrapRegCNZ = 16'b000_00110_000000_00; // Trap using Rs and Rt, non-zero ALU (Tlt, Tltu, Tne) +parameter [15:0] DP_TrapRegCZ = 16'b000_00100_000000_00; // Trap using RS and Rt, zero ALU (Teq, Tge, Tgeu) +parameter [15:0] DP_TrapImmCNZ = 16'b000_10110_000000_00; // Trap using Rs and Imm, non-zero ALU (Tlti, Tltiu, Tnei) +parameter [15:0] DP_TrapImmCZ = 16'b000_10100_000000_00; // Trap using Rs and Imm, zero ALU (Teqi, Tgei, Tgeiu) +//-------------------------------------------------------- +parameter [15:0] DP_Add = DP_RType; +parameter [15:0] DP_Addi = DP_IType; +parameter [15:0] DP_Addiu = DP_IType; +parameter [15:0] DP_Addu = DP_RType; +parameter [15:0] DP_And = DP_RType; +parameter [15:0] DP_Andi = DP_IType; +parameter [15:0] DP_Beq = DP_Branch; +parameter [15:0] DP_Bgez = DP_Branch; +parameter [15:0] DP_Bgezal = DP_BranchLink; +parameter [15:0] DP_Bgtz = DP_Branch; +parameter [15:0] DP_Blez = DP_Branch; +parameter [15:0] DP_Bltz = DP_Branch; +parameter [15:0] DP_Bltzal = DP_BranchLink; +parameter [15:0] DP_Bne = DP_Branch; +parameter [15:0] DP_Break = DP_None; +parameter [15:0] DP_Clo = DP_RType; +parameter [15:0] DP_Clz = DP_RType; +parameter [15:0] DP_Div = DP_HiLoWr; +parameter [15:0] DP_Divu = DP_HiLoWr; +parameter [15:0] DP_Eret = DP_None; +parameter [15:0] DP_J = DP_Jump; +parameter [15:0] DP_Jal = DP_JumpLink; +parameter [15:0] DP_Jalr = DP_JumpLinkReg; +parameter [15:0] DP_Jr = DP_JumpReg; +parameter [15:0] DP_Lb = DP_LoadByteS; +parameter [15:0] DP_Lbu = DP_LoadByteU; +parameter [15:0] DP_Lh = DP_LoadHalfS; +parameter [15:0] DP_Lhu = DP_LoadHalfU; +parameter [15:0] DP_Ll = DP_LoadLinked; +parameter [15:0] DP_Lui = DP_IType; +parameter [15:0] DP_Lw = DP_LoadWord; +parameter [15:0] DP_Lwl = DP_LoadWord; +parameter [15:0] DP_Lwr = DP_LoadWord; +parameter [15:0] DP_Madd = DP_HiLoWr; +parameter [15:0] DP_Maddu = DP_HiLoWr; +parameter [15:0] DP_Mfc0 = DP_ExtWrRt; +parameter [15:0] DP_Mfhi = DP_ExtWrRd; +parameter [15:0] DP_Mflo = DP_ExtWrRd; +parameter [15:0] DP_Movn = DP_Movc; +parameter [15:0] DP_Movz = DP_Movc; +parameter [15:0] DP_Msub = DP_HiLoWr; +parameter [15:0] DP_Msubu = DP_HiLoWr; +parameter [15:0] DP_Mtc0 = DP_None; +parameter [15:0] DP_Mthi = DP_HiLoWr; +parameter [15:0] DP_Mtlo = DP_HiLoWr; +parameter [15:0] DP_Mul = DP_RType; +parameter [15:0] DP_Mult = DP_HiLoWr; +parameter [15:0] DP_Multu = DP_HiLoWr; +parameter [15:0] DP_Nor = DP_RType; +parameter [15:0] DP_Or = DP_RType; +parameter [15:0] DP_Ori = DP_IType; +parameter [15:0] DP_Pref = DP_None; // Not Implemented +parameter [15:0] DP_Sb = DP_StoreByte; +parameter [15:0] DP_Sc = DP_StoreCond; +parameter [15:0] DP_Sh = DP_StoreHalf; +parameter [15:0] DP_Sll = DP_RType; +parameter [15:0] DP_Sllv = DP_RType; +parameter [15:0] DP_Slt = DP_RType; +parameter [15:0] DP_Slti = DP_IType; +parameter [15:0] DP_Sltiu = DP_IType; +parameter [15:0] DP_Sltu = DP_RType; +parameter [15:0] DP_Sra = DP_RType; +parameter [15:0] DP_Srav = DP_RType; +parameter [15:0] DP_Srl = DP_RType; +parameter [15:0] DP_Srlv = DP_RType; +parameter [15:0] DP_Sub = DP_RType; +parameter [15:0] DP_Subu = DP_RType; +parameter [15:0] DP_Sw = DP_StoreWord; +parameter [15:0] DP_Swl = DP_StoreWord; +parameter [15:0] DP_Swr = DP_StoreWord; +parameter [15:0] DP_Syscall = DP_None; +parameter [15:0] DP_Teq = DP_TrapRegCZ; +parameter [15:0] DP_Teqi = DP_TrapImmCZ; +parameter [15:0] DP_Tge = DP_TrapRegCZ; +parameter [15:0] DP_Tgei = DP_TrapImmCZ; +parameter [15:0] DP_Tgeiu = DP_TrapImmCZ; +parameter [15:0] DP_Tgeu = DP_TrapRegCZ; +parameter [15:0] DP_Tlt = DP_TrapRegCNZ; +parameter [15:0] DP_Tlti = DP_TrapImmCNZ; +parameter [15:0] DP_Tltiu = DP_TrapImmCNZ; +parameter [15:0] DP_Tltu = DP_TrapRegCNZ; +parameter [15:0] DP_Tne = DP_TrapRegCNZ; +parameter [15:0] DP_Tnei = DP_TrapImmCNZ; +parameter [15:0] DP_Xor = DP_RType; +parameter [15:0] DP_Xori = DP_IType; + + + + +/*** Exception Information *** + + All signals are Active High. + + Bit Meaning + ------------ + 2: Instruction can cause exceptions in ID + 1: Instruction can cause exceptions in EX + 0: Instruction can cause exceptions in MEM +*/ +parameter [2:0] EXC_None = 3'b000; +parameter [2:0] EXC_ID = 3'b100; +parameter [2:0] EXC_EX = 3'b010; +parameter [2:0] EXC_MEM = 3'b001; +//-------------------------------- +parameter [2:0] EXC_Add = EXC_EX; +parameter [2:0] EXC_Addi = EXC_EX; +parameter [2:0] EXC_Addiu = EXC_None; +parameter [2:0] EXC_Addu = EXC_None; +parameter [2:0] EXC_And = EXC_None; +parameter [2:0] EXC_Andi = EXC_None; +parameter [2:0] EXC_Beq = EXC_None; +parameter [2:0] EXC_Bgez = EXC_None; +parameter [2:0] EXC_Bgezal = EXC_None; +parameter [2:0] EXC_Bgtz = EXC_None; +parameter [2:0] EXC_Blez = EXC_None; +parameter [2:0] EXC_Bltz = EXC_None; +parameter [2:0] EXC_Bltzal = EXC_None; +parameter [2:0] EXC_Bne = EXC_None; +parameter [2:0] EXC_Break = EXC_ID; +parameter [2:0] EXC_Clo = EXC_None; +parameter [2:0] EXC_Clz = EXC_None; +parameter [2:0] EXC_Div = EXC_None; +parameter [2:0] EXC_Divu = EXC_None; +parameter [2:0] EXC_Eret = EXC_ID; +parameter [2:0] EXC_J = EXC_None; +parameter [2:0] EXC_Jal = EXC_None; +parameter [2:0] EXC_Jalr = EXC_None; +parameter [2:0] EXC_Jr = EXC_None; +parameter [2:0] EXC_Lb = EXC_MEM; +parameter [2:0] EXC_Lbu = EXC_MEM; +parameter [2:0] EXC_Lh = EXC_MEM; +parameter [2:0] EXC_Lhu = EXC_MEM; +parameter [2:0] EXC_Ll = EXC_MEM; +parameter [2:0] EXC_Lui = EXC_None; +parameter [2:0] EXC_Lw = EXC_MEM; +parameter [2:0] EXC_Lwl = EXC_MEM; +parameter [2:0] EXC_Lwr = EXC_MEM; +parameter [2:0] EXC_Madd = EXC_None; +parameter [2:0] EXC_Maddu = EXC_None; +parameter [2:0] EXC_Mfc0 = EXC_ID; +parameter [2:0] EXC_Mfhi = EXC_None; +parameter [2:0] EXC_Mflo = EXC_None; +parameter [2:0] EXC_Movn = EXC_None; +parameter [2:0] EXC_Movz = EXC_None; +parameter [2:0] EXC_Msub = EXC_None; +parameter [2:0] EXC_Msubu = EXC_None; +parameter [2:0] EXC_Mtc0 = EXC_ID; +parameter [2:0] EXC_Mthi = EXC_None; +parameter [2:0] EXC_Mtlo = EXC_None; +parameter [2:0] EXC_Mul = EXC_None; +parameter [2:0] EXC_Mult = EXC_None; +parameter [2:0] EXC_Multu = EXC_None; +parameter [2:0] EXC_Nor = EXC_None; +parameter [2:0] EXC_Or = EXC_None; +parameter [2:0] EXC_Ori = EXC_None; +parameter [2:0] EXC_Pref = EXC_None; // XXX +parameter [2:0] EXC_Sb = EXC_MEM; +parameter [2:0] EXC_Sc = EXC_MEM; +parameter [2:0] EXC_Sh = EXC_MEM; +parameter [2:0] EXC_Sll = EXC_None; +parameter [2:0] EXC_Sllv = EXC_None; +parameter [2:0] EXC_Slt = EXC_None; +parameter [2:0] EXC_Slti = EXC_None; +parameter [2:0] EXC_Sltiu = EXC_None; +parameter [2:0] EXC_Sltu = EXC_None; +parameter [2:0] EXC_Sra = EXC_None; +parameter [2:0] EXC_Srav = EXC_None; +parameter [2:0] EXC_Srl = EXC_None; +parameter [2:0] EXC_Srlv = EXC_None; +parameter [2:0] EXC_Sub = EXC_EX; +parameter [2:0] EXC_Subu = EXC_None; +parameter [2:0] EXC_Sw = EXC_MEM; +parameter [2:0] EXC_Swl = EXC_MEM; +parameter [2:0] EXC_Swr = EXC_MEM; +parameter [2:0] EXC_Syscall = EXC_ID; +parameter [2:0] EXC_Teq = EXC_MEM; +parameter [2:0] EXC_Teqi = EXC_MEM; +parameter [2:0] EXC_Tge = EXC_MEM; +parameter [2:0] EXC_Tgei = EXC_MEM; +parameter [2:0] EXC_Tgeiu = EXC_MEM; +parameter [2:0] EXC_Tgeu = EXC_MEM; +parameter [2:0] EXC_Tlt = EXC_MEM; +parameter [2:0] EXC_Tlti = EXC_MEM; +parameter [2:0] EXC_Tltiu = EXC_MEM; +parameter [2:0] EXC_Tltu = EXC_MEM; +parameter [2:0] EXC_Tne = EXC_MEM; +parameter [2:0] EXC_Tnei = EXC_MEM; +parameter [2:0] EXC_Xor = EXC_None; +parameter [2:0] EXC_Xori = EXC_None; + + + + +/*** Hazard & Forwarding Datapath *** + + All signals are Active High. + + Bit Meaning + ------------ + 7: Wants Rs by ID + 6: Needs Rs by ID + 5: Wants Rt by ID + 4: Needs Rt by ID + 3: Wants Rs by EX + 2: Needs Rs by EX + 1: Wants Rt by EX + 0: Needs Rt by EX +*/ +parameter [7:0] HAZ_Nothing = 8'b00000000; // Jumps, Lui, Mfhi/lo, special, etc. +parameter [7:0] HAZ_IDRsIDRt = 8'b11110000; // Beq, Bne, Traps +parameter [7:0] HAZ_IDRs = 8'b11000000; // Most branches, Jumps to registers +parameter [7:0] HAZ_IDRt = 8'b00110000; // Mtc0 +parameter [7:0] HAZ_IDRtEXRs = 8'b10111100; // Movn, Movz +parameter [7:0] HAZ_EXRsEXRt = 8'b10101111; // Many R-Type ops +parameter [7:0] HAZ_EXRs = 8'b10001100; // Immediates: Loads, Clo/z, Mthi/lo, etc. +parameter [7:0] HAZ_EXRsWRt = 8'b10101110; // Stores +parameter [7:0] HAZ_EXRt = 8'b00100011; // Shifts using Shamt field +//----------------------------------------- +parameter [7:0] HAZ_Add = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Addi = HAZ_EXRs; +parameter [7:0] HAZ_Addiu = HAZ_EXRs; +parameter [7:0] HAZ_Addu = HAZ_EXRsEXRt; +parameter [7:0] HAZ_And = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Andi = HAZ_EXRs; +parameter [7:0] HAZ_Beq = HAZ_IDRsIDRt; +parameter [7:0] HAZ_Bgez = HAZ_IDRs; +parameter [7:0] HAZ_Bgezal = HAZ_IDRs; +parameter [7:0] HAZ_Bgtz = HAZ_IDRs; +parameter [7:0] HAZ_Blez = HAZ_IDRs; +parameter [7:0] HAZ_Bltz = HAZ_IDRs; +parameter [7:0] HAZ_Bltzal = HAZ_IDRs; +parameter [7:0] HAZ_Bne = HAZ_IDRsIDRt; +parameter [7:0] HAZ_Break = HAZ_Nothing; +parameter [7:0] HAZ_Clo = HAZ_EXRs; +parameter [7:0] HAZ_Clz = HAZ_EXRs; +parameter [7:0] HAZ_Div = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Divu = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Eret = HAZ_Nothing; +parameter [7:0] HAZ_J = HAZ_Nothing; +parameter [7:0] HAZ_Jal = HAZ_Nothing; +parameter [7:0] HAZ_Jalr = HAZ_IDRs; +parameter [7:0] HAZ_Jr = HAZ_IDRs; +parameter [7:0] HAZ_Lb = HAZ_EXRs; +parameter [7:0] HAZ_Lbu = HAZ_EXRs; +parameter [7:0] HAZ_Lh = HAZ_EXRs; +parameter [7:0] HAZ_Lhu = HAZ_EXRs; +parameter [7:0] HAZ_Ll = HAZ_EXRs; +parameter [7:0] HAZ_Lui = HAZ_Nothing; +parameter [7:0] HAZ_Lw = HAZ_EXRs; +parameter [7:0] HAZ_Lwl = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Lwr = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Madd = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Maddu = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Mfc0 = HAZ_Nothing; +parameter [7:0] HAZ_Mfhi = HAZ_Nothing; +parameter [7:0] HAZ_Mflo = HAZ_Nothing; +parameter [7:0] HAZ_Movn = HAZ_IDRtEXRs; +parameter [7:0] HAZ_Movz = HAZ_IDRtEXRs; +parameter [7:0] HAZ_Msub = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Msubu = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Mtc0 = HAZ_IDRt; +parameter [7:0] HAZ_Mthi = HAZ_EXRs; +parameter [7:0] HAZ_Mtlo = HAZ_EXRs; +parameter [7:0] HAZ_Mul = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Mult = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Multu = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Nor = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Or = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Ori = HAZ_EXRs; +parameter [7:0] HAZ_Pref = HAZ_Nothing; // XXX +parameter [7:0] HAZ_Sb = HAZ_EXRsWRt; +parameter [7:0] HAZ_Sc = HAZ_EXRsWRt; +parameter [7:0] HAZ_Sh = HAZ_EXRsWRt; +parameter [7:0] HAZ_Sll = HAZ_EXRt; +parameter [7:0] HAZ_Sllv = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Slt = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Slti = HAZ_EXRs; +parameter [7:0] HAZ_Sltiu = HAZ_EXRs; +parameter [7:0] HAZ_Sltu = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Sra = HAZ_EXRt; +parameter [7:0] HAZ_Srav = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Srl = HAZ_EXRt; +parameter [7:0] HAZ_Srlv = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Sub = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Subu = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Sw = HAZ_EXRsWRt; +parameter [7:0] HAZ_Swl = HAZ_EXRsWRt; +parameter [7:0] HAZ_Swr = HAZ_EXRsWRt; +parameter [7:0] HAZ_Syscall = HAZ_Nothing; +parameter [7:0] HAZ_Teq = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Teqi = HAZ_EXRs; +parameter [7:0] HAZ_Tge = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Tgei = HAZ_EXRs; +parameter [7:0] HAZ_Tgeiu = HAZ_EXRs; +parameter [7:0] HAZ_Tgeu = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Tlt = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Tlti = HAZ_EXRs; +parameter [7:0] HAZ_Tltiu = HAZ_EXRs; +parameter [7:0] HAZ_Tltu = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Tne = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Tnei = HAZ_EXRs; +parameter [7:0] HAZ_Xor = HAZ_EXRsEXRt; +parameter [7:0] HAZ_Xori = HAZ_EXRs; + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/MemControl.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/MemControl.v new file mode 100755 index 0000000..6f4f4c4 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/MemControl.v @@ -0,0 +1,233 @@ +`timescale 1ns / 1ps +/* + * File : MemControl.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 24-Jun-2011 GEA Initial design. + * 2.0 28-Jun-2012 GEA Expanded from a simple byte/half/word unit to + * An advanced data memory controller capable of + * handling big/little endian, atomic and unaligned + * memory accesses. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * A Data Memory Controller which handles all read and write requests from the + * processor to data memory. All data accesses--whether big endian, little endian, + * byte, half, word, or unaligned transfers--are transformed into a simple read + * and write command to data memory over a 32-bit data bus, where the read command + * is one bit and the write command is 4 bits, one for each byte in the 32-bit word. + */ +module MemControl( + input clock, + input reset, + input [31:0] DataIn, // Data from CPU + input [31:0] Address, // From CPU + input [31:0] MReadData, // Data from Memory + input MemRead, // Memory Read command from CPU + input MemWrite, // Memory Write command from CPU + input DataMem_Ready, // Ready signal from Memory + input Byte, // Load/Store is Byte (8-bit) + input Half, // Load/Store is Half (16-bit) + input SignExtend, // Sub-word load should be sign extended + input KernelMode, // (Exception logic) + input ReverseEndian, // Reverse Endian Memory for User Mode + input LLSC, // (LLSC logic) + input ERET, // (LLSC logic) + input Left, // Unaligned Load/Store Word Left + input Right, // Unaligned Load/Store Word Right + input M_Exception_Stall, + input IF_Stall, // XXX Clean this up between this module and HAZ/FWD + output reg [31:0] DataOut, // Data to CPU + output [31:0] MWriteData, // Data to Memory + output reg [3:0] WriteEnable, // Write Enable to Memory for each of 4 bytes of Memory + output ReadEnable, // Read Enable to Memory + output M_Stall, + output EXC_AdEL, // Load Exception + output EXC_AdES // Store Exception + ); + + `include "MIPS_Parameters.v" + + /*** Reverse Endian Mode + Normal memory accesses in the processor are Big Endian. The endianness can be reversed + to Little Endian in User Mode only. + */ + wire BE = KernelMode | ~ReverseEndian; + + /*** Indicator that the current memory reference must be word-aligned ***/ + wire Word = ~(Half | Byte | Left | Right); + + // Exception Detection + wire EXC_KernelMem = ~KernelMode & (Address < UMem_Lower); + wire EXC_Word = Word & (Address[1] | Address[0]); + wire EXC_Half = Half & Address[0]; + assign EXC_AdEL = MemRead & (EXC_KernelMem | EXC_Word | EXC_Half); + assign EXC_AdES = MemWrite & (EXC_KernelMem | EXC_Word | EXC_Half); + + /*** Load Linked and Store Conditional logic *** + + A 32-bit register keeps track of the address for atomic Load Linked / Store Conditional + operations. This register can be updated during stalls since it is not visible to + forward stages. It does not need to be flushed during exceptions, since ERET destroys + the atomicity condition and there are no detrimental effects in an exception handler. + + The atomic condition is set with a Load Linked instruction, and cleared on an ERET + instruction or when any store instruction writes to one or more bytes covered by + the word address register. It does not update on a stall condition. + + The MIPS32 spec states that an ERET instruction between LL and SC will cause the + atomicity condition to fail. This implementation uses the ERET signal from the ID + stage, which means instruction sequences such as "LL SC" could appear to have an + ERET instruction between them even though they don't. One way to fix this is to pass + the ERET signal through the pipeline to the MEM stage. However, because of the nature + of LL/SC operations (they occur in a loop which checks the result at each iteration), + an ERET will normally never be inserted into the pipeline programmatically until the + LL/SC sequence has completed (exceptions such as interrupts can still cause ERET, but + they can still cause them in the LL SC sequence as well). In other words, by not passing + ERET through the pipeline, the only possible effect is a performance penalty. Also this + may be irrelevant since currently ERET stalls for forward stages which can cause exceptions, + which includes LL and SC. + */ + reg [29:0] LLSC_Address; + reg LLSC_Atomic; + wire LLSC_MemWrite_Mask; + + always @(posedge clock) begin + LLSC_Address <= (reset) ? 30'b0 : (MemRead & LLSC) ? Address[31:2] : LLSC_Address; + end + + always @(posedge clock) begin + if (reset) begin + LLSC_Atomic <= 0; + end + else if (MemRead) begin + LLSC_Atomic <= (LLSC) ? 1 : LLSC_Atomic; + end + // XXX GEA Bug for Ganesh: remove "& ~IF_Stall" from below, then SC will always fail: + else if (ERET | (~M_Stall & ~IF_Stall & MemWrite & (Address[31:2] == LLSC_Address))) begin + LLSC_Atomic <= 0; + end + else begin + LLSC_Atomic <= LLSC_Atomic; + end + end + assign LLSC_MemWrite_Mask = (LLSC & MemWrite & (~LLSC_Atomic | (Address[31:2] != LLSC_Address))); + + wire WriteCondition = MemWrite & ~(EXC_KernelMem | EXC_Word | EXC_Half) & ~LLSC_MemWrite_Mask; + wire ReadCondition = MemRead & ~(EXC_KernelMem | EXC_Word | EXC_Half); + + reg RW_Mask; + always @(posedge clock) begin + RW_Mask <= (reset) ? 0 : (((MemWrite | MemRead) & DataMem_Ready) ? 1 : ((~M_Stall & ~IF_Stall) ? 0 : RW_Mask)); + end + assign M_Stall = ReadEnable | (WriteEnable != 4'b0000) | DataMem_Ready | M_Exception_Stall; + assign ReadEnable = ReadCondition & ~RW_Mask; + + wire Half_Access_L = (Address[1] ^ BE); + wire Half_Access_R = (Address[1] ~^ BE); + wire Byte_Access_LL = Half_Access_L & (Address[1] ~^ Address[0]); + wire Byte_Access_LM = Half_Access_L & (Address[0] ~^ BE); + wire Byte_Access_RM = Half_Access_R & (Address[0] ^ BE); + wire Byte_Access_RR = Half_Access_R & (Address[1] ~^ Address[0]); + + // Write-Enable Signals to Memory + always @(*) begin + if (WriteCondition & ~RW_Mask) begin + if (Byte) begin + WriteEnable[3] <= Byte_Access_LL; + WriteEnable[2] <= Byte_Access_LM; + WriteEnable[1] <= Byte_Access_RM; + WriteEnable[0] <= Byte_Access_RR; + end + else if (Half) begin + WriteEnable[3] <= Half_Access_L; + WriteEnable[2] <= Half_Access_L; + WriteEnable[1] <= Half_Access_R; + WriteEnable[0] <= Half_Access_R; + end + else if (Left) begin + case (Address[1:0]) + 2'b00 : WriteEnable <= (BE) ? 4'b1111 : 4'b0001; + 2'b01 : WriteEnable <= (BE) ? 4'b0111 : 4'b0011; + 2'b10 : WriteEnable <= (BE) ? 4'b0011 : 4'b0111; + 2'b11 : WriteEnable <= (BE) ? 4'b0001 : 4'b1111; + endcase + end + else if (Right) begin + case (Address[1:0]) + 2'b00 : WriteEnable <= (BE) ? 4'b1000 : 4'b1111; + 2'b01 : WriteEnable <= (BE) ? 4'b1100 : 4'b1110; + 2'b10 : WriteEnable <= (BE) ? 4'b1110 : 4'b1100; + 2'b11 : WriteEnable <= (BE) ? 4'b1111 : 4'b1000; + endcase + end + else begin + WriteEnable <= 4'b1111; + end + end + else begin + WriteEnable <= 4'b0000; + end + end + + // Data Going to Memory + assign MWriteData[31:24] = (Byte) ? DataIn[7:0] : ((Half) ? DataIn[15:8] : DataIn[31:24]); + assign MWriteData[23:16] = (Byte | Half) ? DataIn[7:0] : DataIn[23:16]; + assign MWriteData[15:8] = (Byte) ? DataIn[7:0] : DataIn[15:8]; + assign MWriteData[7:0] = DataIn[7:0]; + + // Data Read from Memory + always @(*) begin + if (Byte) begin + if (Byte_Access_LL) begin + DataOut <= (SignExtend & MReadData[31]) ? {24'hFFFFFF, MReadData[31:24]} : {24'h000000, MReadData[31:24]}; + end + else if (Byte_Access_LM) begin + DataOut <= (SignExtend & MReadData[23]) ? {24'hFFFFFF, MReadData[23:16]} : {24'h000000, MReadData[23:16]}; + end + else if (Byte_Access_RM) begin + DataOut <= (SignExtend & MReadData[15]) ? {24'hFFFFFF, MReadData[15:8]} : {24'h000000, MReadData[15:8]}; + end + else begin + DataOut <= (SignExtend & MReadData[7]) ? {24'hFFFFFF, MReadData[7:0]} : {24'h000000, MReadData[7:0]}; + end + end + else if (Half) begin + if (Half_Access_L) begin + DataOut <= (SignExtend & MReadData[31]) ? {16'hFFFF, MReadData[31:16]} : {16'h0000, MReadData[31:16]}; + end + else begin + DataOut <= (SignExtend & MReadData[15]) ? {16'hFFFF, MReadData[15:0]} : {16'h0000, MReadData[15:0]}; + end + end + else if (LLSC & MemWrite) begin + DataOut <= (LLSC_Atomic & (Address[31:2] == LLSC_Address)) ? 32'h0000_0001 : 32'h0000_0000; + end + else if (Left) begin + case (Address[1:0]) + 2'b00 : DataOut <= (BE) ? MReadData : {MReadData[7:0], DataIn[23:0]}; + 2'b01 : DataOut <= (BE) ? {MReadData[23:0], DataIn[7:0]} : {MReadData[15:0], DataIn[15:0]}; + 2'b10 : DataOut <= (BE) ? {MReadData[15:0], DataIn[15:0]} : {MReadData[23:0], DataIn[7:0]}; + 2'b11 : DataOut <= (BE) ? {MReadData[7:0], DataIn[23:0]} : MReadData; + endcase + end + else if (Right) begin + case (Address[1:0]) + 2'b00 : DataOut <= (BE) ? {DataIn[31:8], MReadData[31:24]} : MReadData; + 2'b01 : DataOut <= (BE) ? {DataIn[31:16], MReadData[31:16]} : {DataIn[31:24], MReadData[31:8]}; + 2'b10 : DataOut <= (BE) ? {DataIn[31:24], MReadData[31:8]} : {DataIn[31:16], MReadData[31:16]}; + 2'b11 : DataOut <= (BE) ? MReadData : {DataIn[31:8], MReadData[31:24]}; + endcase + end + else begin + DataOut <= MReadData; + end + end + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/Processor.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/Processor.v new file mode 100755 index 0000000..46c2b85 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/Processor.v @@ -0,0 +1,679 @@ +`timescale 1ns / 1ps +/* + * File : Processor.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 23-Jul-2011 GEA Initial design. + * 2.0 26-May-2012 GEA Release version with CP0. + * 2.01 1-Nov-2012 GEA Fixed issue with Jal. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * The top-level MIPS32 Processor. This file is mostly the instantiation + * and wiring of the building blocks of the processor according to the + * hardware design diagram. It contains very little logic itself. + */ +module Processor( + input clock, + input reset, + input [4:0] Interrupts, // 5 general-purpose hardware interrupts + input NMI, // Non-maskable interrupt + // Data Memory Interface + input [31:0] DataMem_In, + input DataMem_Ready, + output DataMem_Read, + output [3:0] DataMem_Write, // 4-bit Write, one for each byte in word. + output [29:0] DataMem_Address, // Addresses are words, not bytes. + output [31:0] DataMem_Out, + // Instruction Memory Interface + input [31:0] InstMem_In, + output [29:0] InstMem_Address, // Addresses are words, not bytes. + input InstMem_Ready, + output InstMem_Read, + output [7:0] IP // Pending interrupts (diagnostic) + ); + + `include "MIPS_Parameters.v" + + + /*** MIPS Instruction and Components (ID Stage) ***/ + wire [31:0] Instruction; + wire [5:0] OpCode = Instruction[31:26]; + wire [4:0] Rs = Instruction[25:21]; + wire [4:0] Rt = Instruction[20:16]; + wire [4:0] Rd = Instruction[15:11]; + wire [5:0] Funct = Instruction[5:0]; + wire [15:0] Immediate = Instruction[15:0]; + wire [25:0] JumpAddress = Instruction[25:0]; + wire [2:0] Cp0_Sel = Instruction[2:0]; + + /*** IF (Instruction Fetch) Signals ***/ + wire IF_Stall, IF_Flush; + wire IF_EXC_AdIF; + wire IF_Exception_Stall; + wire IF_Exception_Flush; + wire IF_IsBDS; + wire [31:0] IF_PCAdd4, IF_PC_PreExc, IF_PCIn, IF_PCOut, IF_Instruction; + + /*** ID (Instruction Decode) Signals ***/ + wire ID_Stall; + wire [1:0] ID_PCSrc; + wire [1:0] ID_RsFwdSel, ID_RtFwdSel; + wire ID_Link, ID_Movn, ID_Movz; + wire ID_SignExtend; + wire ID_LLSC; + wire ID_RegDst, ID_ALUSrcImm, ID_MemWrite, ID_MemRead, ID_MemByte, ID_MemHalf, ID_MemSignExtend, ID_RegWrite, ID_MemtoReg; + wire [4:0] ID_ALUOp; + wire ID_Mfc0, ID_Mtc0, ID_Eret; + wire ID_NextIsDelay; + wire ID_CanErr, ID_ID_CanErr, ID_EX_CanErr, ID_M_CanErr; + wire ID_KernelMode; + wire ID_ReverseEndian; + wire ID_Trap, ID_TrapCond; + wire ID_EXC_Sys, ID_EXC_Bp, ID_EXC_RI; + wire ID_Exception_Stall; + wire ID_Exception_Flush; + wire ID_PCSrc_Exc; + wire [31:0] ID_ExceptionPC; + wire ID_CP1, ID_CP2, ID_CP3; + wire [31:0] ID_PCAdd4; + wire [31:0] ID_ReadData1_RF, ID_ReadData1_End; + wire [31:0] ID_ReadData2_RF, ID_ReadData2_End; + wire [31:0] CP0_RegOut; + wire ID_CmpEQ, ID_CmpGZ, ID_CmpLZ, ID_CmpGEZ, ID_CmpLEZ; + wire [29:0] ID_SignExtImm = (ID_SignExtend & Immediate[15]) ? {14'h3FFF, Immediate} : {14'h0000, Immediate}; + wire [31:0] ID_ImmLeftShift2 = {ID_SignExtImm[29:0], 2'b00}; + wire [31:0] ID_JumpAddress = {ID_PCAdd4[31:28], JumpAddress[25:0], 2'b00}; + wire [31:0] ID_BranchAddress; + wire [31:0] ID_RestartPC; + wire ID_IsBDS; + wire ID_Left, ID_Right; + wire ID_IsFlushed; + + /*** EX (Execute) Signals ***/ + wire EX_ALU_Stall, EX_Stall; + wire [1:0] EX_RsFwdSel, EX_RtFwdSel; + wire EX_Link; + wire [1:0] EX_LinkRegDst; + wire EX_ALUSrcImm; + wire [4:0] EX_ALUOp; + wire EX_Movn, EX_Movz; + wire EX_LLSC; + wire EX_MemRead, EX_MemWrite, EX_MemByte, EX_MemHalf, EX_MemSignExtend, EX_RegWrite, EX_MemtoReg; + wire [4:0] EX_Rs, EX_Rt; + wire EX_WantRsByEX, EX_NeedRsByEX, EX_WantRtByEX, EX_NeedRtByEX; + wire EX_Trap, EX_TrapCond; + wire EX_CanErr, EX_EX_CanErr, EX_M_CanErr; + wire EX_KernelMode; + wire EX_ReverseEndian; + wire EX_Exception_Stall; + wire EX_Exception_Flush; + wire [31:0] EX_ReadData1_PR, EX_ReadData1_Fwd, EX_ReadData2_PR, EX_ReadData2_Fwd, EX_ReadData2_Imm; + wire [31:0] EX_SignExtImm; + wire [4:0] EX_Rd, EX_RtRd, EX_Shamt; + wire [31:0] EX_ALUResult; + wire EX_BZero; + wire EX_EXC_Ov; + wire [31:0] EX_RestartPC; + wire EX_IsBDS; + wire EX_Left, EX_Right; + + /*** MEM (Memory) Signals ***/ + wire M_Stall, M_Stall_Controller; + wire M_LLSC; + wire M_MemRead, M_MemWrite, M_MemByte, M_MemHalf, M_MemSignExtend; + wire M_RegWrite, M_MemtoReg; + wire M_WriteDataFwdSel; + wire M_EXC_AdEL, M_EXC_AdES; + wire M_M_CanErr; + wire M_KernelMode; + wire M_ReverseEndian; + wire M_Trap, M_TrapCond; + wire M_EXC_Tr; + wire M_Exception_Flush; + wire [31:0] M_ALUResult, M_ReadData2_PR; + wire [4:0] M_RtRd; + wire [31:0] M_MemReadData; + wire [31:0] M_RestartPC; + wire M_IsBDS; + wire [31:0] M_WriteData_Pre; + wire M_Left, M_Right; + wire M_Exception_Stall; + + /*** WB (Writeback) Signals ***/ + wire WB_Stall, WB_RegWrite; + wire [31:0] WB_ReadData, WB_ALUResult; + wire [4:0] WB_RtRd; + wire [31:0] WB_WriteData; + + /*** Other Signals ***/ + wire [7:0] ID_DP_Hazards, HAZ_DP_Hazards; + + /*** Assignments ***/ + assign IF_Instruction = (IF_Stall) ? 32'h00000000 : InstMem_In; + assign IF_IsBDS = ID_NextIsDelay; + assign HAZ_DP_Hazards = {ID_DP_Hazards[7:4], EX_WantRsByEX, EX_NeedRsByEX, EX_WantRtByEX, EX_NeedRtByEX}; + assign IF_EXC_AdIF = IF_PCOut[1] | IF_PCOut[0]; + assign ID_CanErr = ID_ID_CanErr | ID_EX_CanErr | ID_M_CanErr; + assign EX_CanErr = EX_EX_CanErr | EX_M_CanErr; + assign M_CanErr = M_M_CanErr; + + // External Memory Interface + reg IRead, IReadMask; + assign InstMem_Address = IF_PCOut[31:2]; + assign DataMem_Address = M_ALUResult[31:2]; + always @(posedge clock) begin + IRead <= (reset) ? 1 : ~InstMem_Ready; + IReadMask <= (reset) ? 0 : ((IRead & InstMem_Ready) ? 1 : ((~IF_Stall) ? 0 : IReadMask)); + end + assign InstMem_Read = IRead & ~IReadMask; + + + /*** Datapath Controller ***/ + Control Controller ( + .ID_Stall (ID_Stall), + .OpCode (OpCode), + .Funct (Funct), + .Rs (Rs), + .Rt (Rt), + .Cmp_EQ (ID_CmpEQ), + .Cmp_GZ (ID_CmpGZ), + .Cmp_GEZ (ID_CmpGEZ), + .Cmp_LZ (ID_CmpLZ), + .Cmp_LEZ (ID_CmpLEZ), + .IF_Flush (IF_Flush), + .DP_Hazards (ID_DP_Hazards), + .PCSrc (ID_PCSrc), + .SignExtend (ID_SignExtend), + .Link (ID_Link), + .Movn (ID_Movn), + .Movz (ID_Movz), + .Mfc0 (ID_Mfc0), + .Mtc0 (ID_Mtc0), + .CP1 (ID_CP1), + .CP2 (ID_CP2), + .CP3 (ID_CP3), + .Eret (ID_Eret), + .Trap (ID_Trap), + .TrapCond (ID_TrapCond), + .EXC_Sys (ID_EXC_Sys), + .EXC_Bp (ID_EXC_Bp), + .EXC_RI (ID_EXC_RI), + .ID_CanErr (ID_ID_CanErr), + .EX_CanErr (ID_EX_CanErr), + .M_CanErr (ID_M_CanErr), + .NextIsDelay (ID_NextIsDelay), + .RegDst (ID_RegDst), + .ALUSrcImm (ID_ALUSrcImm), + .ALUOp (ID_ALUOp), + .LLSC (ID_LLSC), + .MemWrite (ID_MemWrite), + .MemRead (ID_MemRead), + .MemByte (ID_MemByte), + .MemHalf (ID_MemHalf), + .MemSignExtend (ID_MemSignExtend), + .Left (ID_Left), + .Right (ID_Right), + .RegWrite (ID_RegWrite), + .MemtoReg (ID_MemtoReg) + ); + + /*** Hazard and Forward Control Unit ***/ + Hazard_Detection HazardControl ( + .DP_Hazards (HAZ_DP_Hazards), + .ID_Rs (Rs), + .ID_Rt (Rt), + .EX_Rs (EX_Rs), + .EX_Rt (EX_Rt), + .EX_RtRd (EX_RtRd), + .MEM_RtRd (M_RtRd), + .WB_RtRd (WB_RtRd), + .EX_Link (EX_Link), + .EX_RegWrite (EX_RegWrite), + .MEM_RegWrite (M_RegWrite), + .WB_RegWrite (WB_RegWrite), + .MEM_MemRead (M_MemRead), + .MEM_MemWrite (M_MemWrite), + .InstMem_Read (InstMem_Read), + .InstMem_Ready (InstMem_Ready), + .Mfc0 (ID_Mfc0), + .IF_Exception_Stall (IF_Exception_Stall), + .ID_Exception_Stall (ID_Exception_Stall), + .EX_Exception_Stall (EX_Exception_Stall), + .EX_ALU_Stall (EX_ALU_Stall), + .M_Stall_Controller (M_Stall_Controller), + .IF_Stall (IF_Stall), + .ID_Stall (ID_Stall), + .EX_Stall (EX_Stall), + .M_Stall (M_Stall), + .WB_Stall (WB_Stall), + .ID_RsFwdSel (ID_RsFwdSel), + .ID_RtFwdSel (ID_RtFwdSel), + .EX_RsFwdSel (EX_RsFwdSel), + .EX_RtFwdSel (EX_RtFwdSel), + .M_WriteDataFwdSel (M_WriteDataFwdSel) + ); + + /*** Coprocessor 0: Exceptions and Interrupts ***/ + CPZero CP0 ( + .clock (clock), + .Mfc0 (ID_Mfc0), + .Mtc0 (ID_Mtc0), + .IF_Stall (IF_Stall), + .ID_Stall (ID_Stall), + .COP1 (ID_CP1), + .COP2 (ID_CP2), + .COP3 (ID_CP3), + .ERET (ID_Eret), + .Rd (Rd), + .Sel (Cp0_Sel), + .Reg_In (ID_ReadData2_End), + .Reg_Out (CP0_RegOut), + .KernelMode (ID_KernelMode), + .ReverseEndian (ID_ReverseEndian), + .Int (Interrupts), + .reset (reset), + .EXC_NMI (NMI), + .EXC_AdIF (IF_EXC_AdIF), + .EXC_AdEL (M_EXC_AdEL), + .EXC_AdES (M_EXC_AdES), + .EXC_Ov (EX_EXC_Ov), + .EXC_Tr (M_EXC_Tr), + .EXC_Sys (ID_EXC_Sys), + .EXC_Bp (ID_EXC_Bp), + .EXC_RI (ID_EXC_RI), + .ID_RestartPC (ID_RestartPC), + .EX_RestartPC (EX_RestartPC), + .M_RestartPC (M_RestartPC), + .ID_IsFlushed (ID_IsFlushed), + .IF_IsBD (IF_IsBDS), + .ID_IsBD (ID_IsBDS), + .EX_IsBD (EX_IsBDS), + .M_IsBD (M_IsBDS), + .BadAddr_M (M_ALUResult), + .BadAddr_IF (IF_PCOut), + .ID_CanErr (ID_CanErr), + .EX_CanErr (EX_CanErr), + .M_CanErr (M_CanErr), + .IF_Exception_Stall (IF_Exception_Stall), + .ID_Exception_Stall (ID_Exception_Stall), + .EX_Exception_Stall (EX_Exception_Stall), + .M_Exception_Stall (M_Exception_Stall), + .IF_Exception_Flush (IF_Exception_Flush), + .ID_Exception_Flush (ID_Exception_Flush), + .EX_Exception_Flush (EX_Exception_Flush), + .M_Exception_Flush (M_Exception_Flush), + .Exc_PC_Sel (ID_PCSrc_Exc), + .Exc_PC_Out (ID_ExceptionPC), + .IP (IP) + ); + + /*** PC Source Non-Exception Mux ***/ + Mux4 #(.WIDTH(32)) PCSrcStd_Mux ( + .sel (ID_PCSrc), + .in0 (IF_PCAdd4), + .in1 (ID_JumpAddress), + .in2 (ID_BranchAddress), + .in3 (ID_ReadData1_End), + .out (IF_PC_PreExc) + ); + + /*** PC Source Exception Mux ***/ + Mux2 #(.WIDTH(32)) PCSrcExc_Mux ( + .sel (ID_PCSrc_Exc), + .in0 (IF_PC_PreExc), + .in1 (ID_ExceptionPC), + .out (IF_PCIn) + ); + + /*** Program Counter (MIPS spec is 0xBFC00000 starting address) ***/ + Register #(.WIDTH(32), .INIT(EXC_Vector_Base_Reset)) PC ( + .clock (clock), + .reset (reset), + //.enable (~IF_Stall), // XXX verify. HERE. Was 1 but on stall latches PC+4, ad nauseum. + .enable (~(IF_Stall | ID_Stall)), + .D (IF_PCIn), + .Q (IF_PCOut) + ); + + /*** PC +4 Adder ***/ + Add PC_Add4 ( + .A (IF_PCOut), + .B (32'h00000004), + .C (IF_PCAdd4) + ); + + /*** Instruction Fetch -> Instruction Decode Stage Register ***/ + IFID_Stage IFID ( + .clock (clock), + .reset (reset), + .IF_Flush (IF_Exception_Flush | IF_Flush), + .IF_Stall (IF_Stall), + .ID_Stall (ID_Stall), + .IF_Instruction (IF_Instruction), + .IF_PCAdd4 (IF_PCAdd4), + .IF_PC (IF_PCOut), + .IF_IsBDS (IF_IsBDS), + .ID_Instruction (Instruction), + .ID_PCAdd4 (ID_PCAdd4), + .ID_RestartPC (ID_RestartPC), + .ID_IsBDS (ID_IsBDS), + .ID_IsFlushed (ID_IsFlushed) + ); + + /*** Register File ***/ + RegisterFile RegisterFile ( + .clock (clock), + .reset (reset), + .ReadReg1 (Rs), + .ReadReg2 (Rt), + .WriteReg (WB_RtRd), + .WriteData (WB_WriteData), + .RegWrite (WB_RegWrite), + .ReadData1 (ID_ReadData1_RF), + .ReadData2 (ID_ReadData2_RF) + ); + + /*** ID Rs Forwarding/Link Mux ***/ + Mux4 #(.WIDTH(32)) IDRsFwd_Mux ( + .sel (ID_RsFwdSel), + .in0 (ID_ReadData1_RF), + .in1 (M_ALUResult), + .in2 (WB_WriteData), + .in3 (32'hxxxxxxxx), + .out (ID_ReadData1_End) + ); + + /*** ID Rt Forwarding/CP0 Mfc0 Mux ***/ + Mux4 #(.WIDTH(32)) IDRtFwd_Mux ( + .sel (ID_RtFwdSel), + .in0 (ID_ReadData2_RF), + .in1 (M_ALUResult), + .in2 (WB_WriteData), + .in3 (CP0_RegOut), + .out (ID_ReadData2_End) + ); + + /*** Condition Compare Unit ***/ + Compare Compare ( + .A (ID_ReadData1_End), + .B (ID_ReadData2_End), + .EQ (ID_CmpEQ), + .GZ (ID_CmpGZ), + .LZ (ID_CmpLZ), + .GEZ (ID_CmpGEZ), + .LEZ (ID_CmpLEZ) + ); + + /*** Branch Address Adder ***/ + Add BranchAddress_Add ( + .A (ID_PCAdd4), + .B (ID_ImmLeftShift2), + .C (ID_BranchAddress) + ); + + /*** Instruction Decode -> Execute Pipeline Stage ***/ + IDEX_Stage IDEX ( + .clock (clock), + .reset (reset), + .ID_Flush (ID_Exception_Flush), + .ID_Stall (ID_Stall), + .EX_Stall (EX_Stall), + .ID_Link (ID_Link), + .ID_RegDst (ID_RegDst), + .ID_ALUSrcImm (ID_ALUSrcImm), + .ID_ALUOp (ID_ALUOp), + .ID_Movn (ID_Movn), + .ID_Movz (ID_Movz), + .ID_LLSC (ID_LLSC), + .ID_MemRead (ID_MemRead), + .ID_MemWrite (ID_MemWrite), + .ID_MemByte (ID_MemByte), + .ID_MemHalf (ID_MemHalf), + .ID_MemSignExtend (ID_MemSignExtend), + .ID_Left (ID_Left), + .ID_Right (ID_Right), + .ID_RegWrite (ID_RegWrite), + .ID_MemtoReg (ID_MemtoReg), + .ID_ReverseEndian (ID_ReverseEndian), + .ID_Rs (Rs), + .ID_Rt (Rt), + .ID_WantRsByEX (ID_DP_Hazards[3]), + .ID_NeedRsByEX (ID_DP_Hazards[2]), + .ID_WantRtByEX (ID_DP_Hazards[1]), + .ID_NeedRtByEX (ID_DP_Hazards[0]), + .ID_KernelMode (ID_KernelMode), + .ID_RestartPC (ID_RestartPC), + .ID_IsBDS (ID_IsBDS), + .ID_Trap (ID_Trap), + .ID_TrapCond (ID_TrapCond), + .ID_EX_CanErr (ID_EX_CanErr), + .ID_M_CanErr (ID_M_CanErr), + .ID_ReadData1 (ID_ReadData1_End), + .ID_ReadData2 (ID_ReadData2_End), + .ID_SignExtImm (ID_SignExtImm[16:0]), + .EX_Link (EX_Link), + .EX_LinkRegDst (EX_LinkRegDst), + .EX_ALUSrcImm (EX_ALUSrcImm), + .EX_ALUOp (EX_ALUOp), + .EX_Movn (EX_Movn), + .EX_Movz (EX_Movz), + .EX_LLSC (EX_LLSC), + .EX_MemRead (EX_MemRead), + .EX_MemWrite (EX_MemWrite), + .EX_MemByte (EX_MemByte), + .EX_MemHalf (EX_MemHalf), + .EX_MemSignExtend (EX_MemSignExtend), + .EX_Left (EX_Left), + .EX_Right (EX_Right), + .EX_RegWrite (EX_RegWrite), + .EX_MemtoReg (EX_MemtoReg), + .EX_ReverseEndian (EX_ReverseEndian), + .EX_Rs (EX_Rs), + .EX_Rt (EX_Rt), + .EX_WantRsByEX (EX_WantRsByEX), + .EX_NeedRsByEX (EX_NeedRsByEX), + .EX_WantRtByEX (EX_WantRtByEX), + .EX_NeedRtByEX (EX_NeedRtByEX), + .EX_KernelMode (EX_KernelMode), + .EX_RestartPC (EX_RestartPC), + .EX_IsBDS (EX_IsBDS), + .EX_Trap (EX_Trap), + .EX_TrapCond (EX_TrapCond), + .EX_EX_CanErr (EX_EX_CanErr), + .EX_M_CanErr (EX_M_CanErr), + .EX_ReadData1 (EX_ReadData1_PR), + .EX_ReadData2 (EX_ReadData2_PR), + .EX_SignExtImm (EX_SignExtImm), + .EX_Rd (EX_Rd), + .EX_Shamt (EX_Shamt) + ); + + /*** EX Rs Forwarding Mux ***/ + Mux4 #(.WIDTH(32)) EXRsFwd_Mux ( + .sel (EX_RsFwdSel), + .in0 (EX_ReadData1_PR), + .in1 (M_ALUResult), + .in2 (WB_WriteData), + .in3 (EX_RestartPC), + .out (EX_ReadData1_Fwd) + ); + + /*** EX Rt Forwarding / Link Mux ***/ + Mux4 #(.WIDTH(32)) EXRtFwdLnk_Mux ( + .sel (EX_RtFwdSel), + .in0 (EX_ReadData2_PR), + .in1 (M_ALUResult), + .in2 (WB_WriteData), + .in3 (32'h00000008), + .out (EX_ReadData2_Fwd) + ); + + /*** EX ALU Immediate Mux ***/ + Mux2 #(.WIDTH(32)) EXALUImm_Mux ( + .sel (EX_ALUSrcImm), + .in0 (EX_ReadData2_Fwd), + .in1 (EX_SignExtImm), + .out (EX_ReadData2_Imm) + ); + + /*** EX RtRd / Link Mux ***/ + Mux4 #(.WIDTH(5)) EXRtRdLnk_Mux ( + .sel (EX_LinkRegDst), + .in0 (EX_Rt), + .in1 (EX_Rd), + .in2 (5'b11111), + .in3 (5'bxxxxx), + .out (EX_RtRd) + ); + + /*** Arithmetic Logic Unit ***/ + ALU ALU ( + .clock (clock), + .reset (reset), + .EX_Stall (EX_Stall), + .EX_Flush (EX_Exception_Flush), + .A (EX_ReadData1_Fwd), + .B (EX_ReadData2_Imm), + .Operation (EX_ALUOp), + .Shamt (EX_Shamt), + .Result (EX_ALUResult), + .BZero (EX_BZero), + .EXC_Ov (EX_EXC_Ov), + .ALU_Stall (EX_ALU_Stall) + ); + + /*** Execute -> Memory Pipeline Stage ***/ + EXMEM_Stage EXMEM ( + .clock (clock), + .reset (reset), + .EX_Flush (EX_Exception_Flush), + .EX_Stall (EX_Stall), + .M_Stall (M_Stall), + .EX_Movn (EX_Movn), + .EX_Movz (EX_Movz), + .EX_BZero (EX_BZero), + .EX_RegWrite (EX_RegWrite), + .EX_MemtoReg (EX_MemtoReg), + .EX_ReverseEndian (EX_ReverseEndian), + .EX_LLSC (EX_LLSC), + .EX_MemRead (EX_MemRead), + .EX_MemWrite (EX_MemWrite), + .EX_MemByte (EX_MemByte), + .EX_MemHalf (EX_MemHalf), + .EX_MemSignExtend (EX_MemSignExtend), + .EX_Left (EX_Left), + .EX_Right (EX_Right), + .EX_KernelMode (EX_KernelMode), + .EX_RestartPC (EX_RestartPC), + .EX_IsBDS (EX_IsBDS), + .EX_Trap (EX_Trap), + .EX_TrapCond (EX_TrapCond), + .EX_M_CanErr (EX_M_CanErr), + .EX_ALU_Result (EX_ALUResult), + .EX_ReadData2 (EX_ReadData2_Fwd), + .EX_RtRd (EX_RtRd), + .M_RegWrite (M_RegWrite), + .M_MemtoReg (M_MemtoReg), + .M_ReverseEndian (M_ReverseEndian), + .M_LLSC (M_LLSC), + .M_MemRead (M_MemRead), + .M_MemWrite (M_MemWrite), + .M_MemByte (M_MemByte), + .M_MemHalf (M_MemHalf), + .M_MemSignExtend (M_MemSignExtend), + .M_Left (M_Left), + .M_Right (M_Right), + .M_KernelMode (M_KernelMode), + .M_RestartPC (M_RestartPC), + .M_IsBDS (M_IsBDS), + .M_Trap (M_Trap), + .M_TrapCond (M_TrapCond), + .M_M_CanErr (M_M_CanErr), + .M_ALU_Result (M_ALUResult), + .M_ReadData2 (M_ReadData2_PR), + .M_RtRd (M_RtRd) + ); + + /*** Trap Detection Unit ***/ + TrapDetect TrapDetect ( + .Trap (M_Trap), + .TrapCond (M_TrapCond), + .ALUResult (M_ALUResult), + .EXC_Tr (M_EXC_Tr) + ); + + /*** MEM Write Data Mux ***/ + Mux2 #(.WIDTH(32)) MWriteData_Mux ( + .sel (M_WriteDataFwdSel), + .in0 (M_ReadData2_PR), + .in1 (WB_WriteData), + .out (M_WriteData_Pre) + ); + + /*** Data Memory Controller ***/ + MemControl DataMem_Controller ( + .clock (clock), + .reset (reset), + .DataIn (M_WriteData_Pre), + .Address (M_ALUResult), + .MReadData (DataMem_In), + .MemRead (M_MemRead), + .MemWrite (M_MemWrite), + .DataMem_Ready (DataMem_Ready), + .Byte (M_MemByte), + .Half (M_MemHalf), + .SignExtend (M_MemSignExtend), + .KernelMode (M_KernelMode), + .ReverseEndian (M_ReverseEndian), + .LLSC (M_LLSC), + .ERET (ID_Eret), + .Left (M_Left), + .Right (M_Right), + .M_Exception_Stall (M_Exception_Stall), + + .IF_Stall (IF_Stall), + + .DataOut (M_MemReadData), + .MWriteData (DataMem_Out), + .WriteEnable (DataMem_Write), + .ReadEnable (DataMem_Read), + .M_Stall (M_Stall_Controller), + .EXC_AdEL (M_EXC_AdEL), + .EXC_AdES (M_EXC_AdES) + ); + + /*** Memory -> Writeback Pipeline Stage ***/ + MEMWB_Stage MEMWB ( + .clock (clock), + .reset (reset), + .M_Flush (M_Exception_Flush), + .M_Stall (M_Stall), + .WB_Stall (WB_Stall), + .M_RegWrite (M_RegWrite), + .M_MemtoReg (M_MemtoReg), + .M_ReadData (M_MemReadData), + .M_ALU_Result (M_ALUResult), + .M_RtRd (M_RtRd), + .WB_RegWrite (WB_RegWrite), + .WB_MemtoReg (WB_MemtoReg), + .WB_ReadData (WB_ReadData), + .WB_ALU_Result (WB_ALUResult), + .WB_RtRd (WB_RtRd) + ); + + /*** WB MemtoReg Mux ***/ + Mux2 #(.WIDTH(32)) WBMemtoReg_Mux ( + .sel (WB_MemtoReg), + .in0 (WB_ALUResult), + .in1 (WB_ReadData), + .out (WB_WriteData) + ); + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/Register.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/Register.v new file mode 100755 index 0000000..ae073d6 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/Register.v @@ -0,0 +1,34 @@ +`timescale 1ns / 1ps +/* + * File : Register.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 7-Jun-2011 GEA Initial design. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * A variable-width register (d flip-flop) with configurable initial + * value. Default is 32-bit width and 0s for initial value. + */ +module Register #(parameter WIDTH = 32, INIT = 0)( + input clock, + input reset, + input enable, + input [(WIDTH-1):0] D, + output reg [(WIDTH-1):0] Q + ); + + initial + Q = INIT; + + always @(posedge clock) begin + Q <= (reset) ? INIT : ((enable) ? D : Q); + end + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/RegisterFile.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/RegisterFile.v new file mode 100755 index 0000000..ac0c0ab --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/RegisterFile.v @@ -0,0 +1,58 @@ +`timescale 1ns / 1ps +/* + * File : RegisterFile.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 7-Jun-2011 GEA Initial design. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * A Register File for a MIPS processor. Contains 32 general-purpose + * 32-bit wide registers and two read ports. Register 0 always reads + * as zero. + */ +module RegisterFile( + input clock, + input reset, + input [4:0] ReadReg1, ReadReg2, WriteReg, + input [31:0] WriteData, + input RegWrite, + output [31:0] ReadData1, ReadData2 + ); + + // Register file of 32 32-bit registers. Register 0 is hardwired to 0s + reg [31:0] registers [1:31]; + + // Initialize all to zero + integer i; + initial begin + for (i=1; i<32; i=i+1) begin + registers[i] <= 0; + end + end + + // Sequential (clocked) write. + // 'WriteReg' is the register index to write. 'RegWrite' is the command. + always @(posedge clock) begin + if (reset) begin + for (i=1; i<32; i=i+1) begin + registers[i] <= 0; + end + end + else begin + if (WriteReg != 0) + registers[WriteReg] <= (RegWrite) ? WriteData : registers[WriteReg]; + end + end + + // Combinatorial Read. Register 0 is all 0s. + assign ReadData1 = (ReadReg1 == 0) ? 32'h00000000 : registers[ReadReg1]; + assign ReadData2 = (ReadReg2 == 0) ? 32'h00000000 : registers[ReadReg2]; + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/TrapDetect.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/TrapDetect.v new file mode 100755 index 0000000..5b5884b --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/MIPS32/TrapDetect.v @@ -0,0 +1,28 @@ +`timescale 1ns / 1ps +/* + * File : TrapDetect.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 15-May-2012 GEA Initial design. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * Detects a Trap Exception in the pipeline. + */ +module TrapDetect( + input Trap, + input TrapCond, + input [31:0] ALUResult, + output EXC_Tr + ); + + wire ALUZero = (ALUResult == 32'h00000000); + assign EXC_Tr = Trap & (TrapCond ^ ALUZero); + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Piezo/Piezo.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Piezo/Piezo.v new file mode 100755 index 0000000..170ffc9 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Piezo/Piezo.v @@ -0,0 +1,43 @@ +`timescale 1ns / 1ps +/* + * File : Piezo.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 11-Jun-2012 GEA Initial design. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * A sound driver for a piezo-electric transducer (or other + * oscillating device). When enabled, the output oscillates + * between high and low, switching at a rate determined by the + * 'count' register and clock frequency. The output is enabled + * when the highest bit is set on a Write. + */ +module Piezo_Driver( + input clock, + input reset, + input [24:0] data, + input Write, + output reg Ack, + output reg Piezo + ); + + reg [23:0] count; + reg [23:0] compare; + reg enabled; + + always @(posedge clock) begin + count <= (reset | (count == compare)) ? 24'h000000 : count + 1; + compare <= (reset) ? 24'h000000 : ((Write) ? data[23:0] : compare); + enabled <= (reset) ? 0 : ((Write) ? data[24] : enabled); + Piezo <= (reset | ~enabled) ? 0 : ((count == compare) ? ~Piezo : Piezo); + Ack <= (reset) ? 0 : Write; + end + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Simulation/Top_Tester.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Simulation/Top_Tester.v new file mode 100755 index 0000000..aca2662 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Simulation/Top_Tester.v @@ -0,0 +1,79 @@ +`timescale 1ns / 1ps + +//////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 12:38:44 09/10/2012 +// Design Name: Top +// Module Name: C:/root/Work/Gauss/Final/Hardware/XUM_Singlecore/MIPS32-Pipelined-Hw/src/Simulation/Top_Tester.v +// Project Name: MIPS32-Pipelined-Hw +// Target Device: +// Tool versions: +// Description: +// +// Verilog Test Fixture created by ISE for module: Top +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +//////////////////////////////////////////////////////////////////////////////// + +module Top_Tester; + + // Inputs + reg clock_100MHz; + reg reset_n; + reg [7:0] Switch; + reg UART_Rx; + + // Outputs + wire [14:0] LED; + wire [6:0] LCD; + wire UART_Tx; + wire Piezo; + + // Bidirs + wire i2c_scl; + wire i2c_sda; + + // Instantiate the Unit Under Test (UUT) + Top uut ( + .clock_100MHz(clock_100MHz), + .reset_n(reset_n), + .Switch(Switch), + .LED(LED), + .LCD(LCD), + .UART_Rx(UART_Rx), + .UART_Tx(UART_Tx), + .i2c_scl(i2c_scl), + .i2c_sda(i2c_sda), + .Piezo(Piezo) + ); + integer i; + + initial begin + // Initialize Inputs + clock_100MHz = 0; + reset_n = 0; + Switch = 0; + UART_Rx = 0; + + // Wait 100 ns for global reset to finish + #100; + + // Add stimulus here + for (i=0; i<900000; i=i+1) begin + reset_n = (i < 28) ? 0 : 1; + clock_100MHz = ~clock_100MHz; + if (i > 4000) Switch <= 8'h00; + if (i > 100000) i = i - 1; + #5; + end + end + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Simulation/waveform.wcfg b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Simulation/waveform.wcfg new file mode 100755 index 0000000..7bb4140 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Simulation/waveform.wcfg @@ -0,0 +1,609 @@ + + + + + + + + + + + + + + + clock + clock + + + reset + reset + + + ID_Instruction[31:0] + ID_Instruction[31:0] + HEXRADIX + + + ID_RestartPC[31:0] + ID_RestartPC[31:0] + HEXRADIX + + + Stages + label + + EX_RestartPC[31:0] + EX_RestartPC[31:0] + HEXRADIX + + + M_RestartPC[31:0] + M_RestartPC[31:0] + HEXRADIX + + + + Forwards + label + + ID_RsFwdSel[1:0] + ID_RsFwdSel[1:0] + + + ID_RtFwdSel[1:0] + ID_RtFwdSel[1:0] + + + EX_RsFwdSel[1:0] + EX_RsFwdSel[1:0] + + + EX_RtFwdSel[1:0] + EX_RtFwdSel[1:0] + + + M_WriteDataFwdSel + M_WriteDataFwdSel + + + + Stalls + label + + WB_Stall + WB_Stall + + + M_Stall + M_Stall + + + label + M_Stall + M_Stall + M_Stall_Controller + + + EX_Stall + EX_Stall + + + ID_Stall + ID_Stall + + + IF_Stall + IF_Stall + + + + InstMem_Read + InstMem_Read + + + InstMem_Ready + InstMem_Ready + + + MIPS32_InstMem_In[31:0] + MIPS32_InstMem_In[31:0] + HEXRADIX + + + IF_PCIn[31:0] + IF_PCIn[31:0] + HEXRADIX + + + IF_PCOut[31:0] + IF_PCOut[31:0] + HEXRADIX + + + label + enable + enable + PC_Enable + + + ID_PCSrc[1:0] + ID_PCSrc[1:0] + + + ID_PCSrc_Exc + ID_PCSrc_Exc + + + M_RegWrite + M_RegWrite + + + LLSC_Atomic + LLSC_Atomic + + + WB STAGE + label + + M_Flush + M_Flush + + + M_Stall + M_Stall + + + WB_Stall + WB_Stall + + + M_RtRd[4:0] + M_RtRd[4:0] + UNSIGNEDDECRADIX + + + WB_RegWrite + WB_RegWrite + + + WB_MemtoReg + WB_MemtoReg + + + M_ReadData[31:0] + M_ReadData[31:0] + HEXRADIX + + + WB_ReadData[31:0] + WB_ReadData[31:0] + HEXRADIX + + + WB_ALU_Result[31:0] + WB_ALU_Result[31:0] + HEXRADIX + + + WB_WriteData[31:0] + WB_WriteData[31:0] + HEXRADIX + + + + Address[31:0] + Address[31:0] + HEXRADIX + + + DataMem_Address[29:0] + DataMem_Address[29:0] + HEXRADIX + + + DataMem_Out[31:0] + DataMem_Out[31:0] + HEXRADIX + + + DataMem_In[31:0] + DataMem_In[31:0] + HEXRADIX + + + DataMem_Write[3:0] + DataMem_Write[3:0] + + + DataMem_Read + DataMem_Read + + + DataMem_Ready + DataMem_Ready + + + M_MemRead + M_MemRead + + + M_MemWrite + M_MemWrite + + + WriteCondition + WriteCondition + + + web[3:0] + web[3:0] + + + Exceptions + label + + EXC_AdIF + EXC_AdIF + + + EXC_AdEL + EXC_AdEL + + + EXC_AdES + EXC_AdES + + + EXC_Ov + EXC_Ov + + + EXC_Tr + EXC_Tr + + + EXC_Sys + EXC_Sys + + + EXC_Bp + EXC_Bp + + + EXC_RI + EXC_RI + + + EXC_CpU + EXC_CpU + + + EXC_Int + EXC_Int + + + + CP0 + label + + ID_Exception_Stall + ID_Exception_Stall + + + Flushes + label + + IF_Exception_Flush + IF_Exception_Flush + + + ID_Exception_Flush + ID_Exception_Flush + + + EX_Exception_Flush + EX_Exception_Flush + + + M_Exception_Flush + M_Exception_Flush + + + + ID_Exception_Ready + ID_Exception_Ready + + + EX_Exception_Ready + EX_Exception_Ready + + + M_Exception_Ready + M_Exception_Ready + + + label + EXC_Tr + EXC_Tr + M_EXC_Tr + + + ErrorEPC[31:0] + ErrorEPC[31:0] + HEXRADIX + + + EPC[31:0] + EPC[31:0] + HEXRADIX + + + Exc_PC_Out[31:0] + Exc_PC_Out[31:0] + HEXRADIX + + + Status_ERL + Status_ERL + + + Status_EXL + Status_EXL + + + Status[31:0] + Status[31:0] + HEXRADIX + + + Cause[31:0] + Cause[31:0] + HEXRADIX + + + Mtc0 + Mtc0 + + + CP0_WriteCond + CP0_WriteCond + + + ERET + ERET + + + Interrupts[4:0] + Interrupts[4:0] + BINARYRADIX + + + + Registers + label + + label + [1,31:0] + registers[1,31:0] + HEXRADIX + at (1) + + + label + [2,31:0] + registers[2,31:0] + HEXRADIX + v0 (2) + + + label + [3,31:0] + registers[3,31:0] + HEXRADIX + v1 (3) + + + label + [4,31:0] + registers[4,31:0] + HEXRADIX + a0 (4) + + + label + [5,31:0] + registers[5,31:0] + ASCIIRADIX + a1 (5) + + + label + [6,31:0] + registers[6,31:0] + HEXRADIX + a2 (6) + + + label + [7,31:0] + registers[7,31:0] + HEXRADIX + a3 (7) + + + label + [8,31:0] + registers[8,31:0] + UNSIGNEDDECRADIX + t0 (8) + + + label + [9,31:0] + registers[9,31:0] + UNSIGNEDDECRADIX + t1 (9) + + + label + [10,31:0] + registers[10,31:0] + HEXRADIX + t2 (10) + + + label + [11,31:0] + registers[11,31:0] + HEXRADIX + t3 (11) + + + label + [12,31:0] + registers[12,31:0] + HEXRADIX + t4 (12) + + + label + [13,31:0] + registers[13,31:0] + HEXRADIX + t5 (13) + + + label + [14,31:0] + registers[14,31:0] + HEXRADIX + t6 (14) + + + label + [15,31:0] + registers[15,31:0] + HEXRADIX + t7 (15) + + + label + [16,31:0] + registers[16,31:0] + HEXRADIX + s0 (16) + + + [17,31:0] + registers[17,31:0] + HEXRADIX + + + [18,31:0] + registers[18,31:0] + HEXRADIX + + + [19,31:0] + registers[19,31:0] + HEXRADIX + + + [20,31:0] + registers[20,31:0] + HEXRADIX + + + [21,31:0] + registers[21,31:0] + HEXRADIX + + + [22,31:0] + registers[22,31:0] + HEXRADIX + + + label + [23,31:0] + registers[23,31:0] + HEXRADIX + s7 (23) + + + [24,31:0] + registers[24,31:0] + HEXRADIX + + + [25,31:0] + registers[25,31:0] + HEXRADIX + + + [26,31:0] + registers[26,31:0] + HEXRADIX + + + [27,31:0] + registers[27,31:0] + HEXRADIX + + + [28,31:0] + registers[28,31:0] + HEXRADIX + + + [29,31:0] + registers[29,31:0] + HEXRADIX + + + [30,31:0] + registers[30,31:0] + HEXRADIX + + + [31,31:0] + registers[31,31:0] + HEXRADIX + + + + I2C + label + + scl + scl + + + i2c_sda + i2c_sda + + + scl_tick_90 + scl_tick_90 + + + state[5:0] + state[5:0] + UNSIGNEDDECRADIX + + + Write + Write + + + I2C_Nack + I2C_Nack + + + count[8:0] + count[8:0] + UNSIGNEDDECRADIX + + + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Switches/Switch_Filter.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Switches/Switch_Filter.v new file mode 100755 index 0000000..0fa6bee --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Switches/Switch_Filter.v @@ -0,0 +1,76 @@ +`timescale 1ns / 1ps +/* + * File : Switch_Filter.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 18-Jun-2012 GEA Initial design. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * A debouncer for 8 switches. + */ +module Switch_Filter( + input clock, + input reset, + input [7:0] switch_in, + output reg [7:0] switch_out + ); + + + reg [5:0] c7, c6, c5, c4, c3, c2, c1, c0; + + always @(posedge clock) begin + c0 <= (reset) ? 6'h20 : ((switch_in[0] & (c0 != 6'h3F)) ? c0 + 1 : ((~switch_in[0] & (c0 != 6'h00)) ? c0 - 1 : c0)); + c1 <= (reset) ? 6'h20 : ((switch_in[1] & (c1 != 6'h3F)) ? c1 + 1 : ((~switch_in[1] & (c1 != 6'h00)) ? c1 - 1 : c1)); + c2 <= (reset) ? 6'h20 : ((switch_in[2] & (c2 != 6'h3F)) ? c2 + 1 : ((~switch_in[2] & (c2 != 6'h00)) ? c2 - 1 : c2)); + c3 <= (reset) ? 6'h20 : ((switch_in[3] & (c3 != 6'h3F)) ? c3 + 1 : ((~switch_in[3] & (c3 != 6'h00)) ? c3 - 1 : c3)); + c4 <= (reset) ? 6'h20 : ((switch_in[4] & (c4 != 6'h3F)) ? c4 + 1 : ((~switch_in[4] & (c4 != 6'h00)) ? c4 - 1 : c4)); + c5 <= (reset) ? 6'h20 : ((switch_in[5] & (c5 != 6'h3F)) ? c5 + 1 : ((~switch_in[5] & (c5 != 6'h00)) ? c5 - 1 : c5)); + c6 <= (reset) ? 6'h20 : ((switch_in[6] & (c6 != 6'h3F)) ? c6 + 1 : ((~switch_in[6] & (c6 != 6'h00)) ? c6 - 1 : c6)); + c7 <= (reset) ? 6'h20 : ((switch_in[7] & (c7 != 6'h3F)) ? c7 + 1 : ((~switch_in[7] & (c7 != 6'h00)) ? c7 - 1 : c7)); + end + + always @(posedge clock) begin + switch_out[0] <= (reset) ? 0 : ((c0 == 6'h00) ? 0 : ((c0 == 6'h3F) ? 1 : switch_out[0])); + switch_out[1] <= (reset) ? 0 : ((c1 == 6'h00) ? 0 : ((c1 == 6'h3F) ? 1 : switch_out[1])); + switch_out[2] <= (reset) ? 0 : ((c2 == 6'h00) ? 0 : ((c2 == 6'h3F) ? 1 : switch_out[2])); + switch_out[3] <= (reset) ? 0 : ((c3 == 6'h00) ? 0 : ((c3 == 6'h3F) ? 1 : switch_out[3])); + switch_out[4] <= (reset) ? 0 : ((c4 == 6'h00) ? 0 : ((c4 == 6'h3F) ? 1 : switch_out[4])); + switch_out[5] <= (reset) ? 0 : ((c5 == 6'h00) ? 0 : ((c5 == 6'h3F) ? 1 : switch_out[5])); + switch_out[6] <= (reset) ? 0 : ((c6 == 6'h00) ? 0 : ((c6 == 6'h3F) ? 1 : switch_out[6])); + switch_out[7] <= (reset) ? 0 : ((c7 == 6'h00) ? 0 : ((c7 == 6'h3F) ? 1 : switch_out[7])); + end + +/* + reg [19:0] c7, c6, c5, c4, c3, c2, c1, c0; + + always @(posedge clock) begin + c0 <= (reset) ? 20'h80000 : ((switch_in[0] & (c0 != 20'hFFFFF)) ? c0 + 1 : ((~switch_in[0] & (c0 != 20'h00000)) ? c0 - 1 : c0)); + c1 <= (reset) ? 20'h80000 : ((switch_in[1] & (c1 != 20'hFFFFF)) ? c1 + 1 : ((~switch_in[1] & (c1 != 20'h00000)) ? c1 - 1 : c1)); + c2 <= (reset) ? 20'h80000 : ((switch_in[2] & (c2 != 20'hFFFFF)) ? c2 + 1 : ((~switch_in[2] & (c2 != 20'h00000)) ? c2 - 1 : c2)); + c3 <= (reset) ? 20'h80000 : ((switch_in[3] & (c3 != 20'hFFFFF)) ? c3 + 1 : ((~switch_in[3] & (c3 != 20'h00000)) ? c3 - 1 : c3)); + c4 <= (reset) ? 20'h80000 : ((switch_in[4] & (c4 != 20'hFFFFF)) ? c4 + 1 : ((~switch_in[4] & (c4 != 20'h00000)) ? c4 - 1 : c4)); + c5 <= (reset) ? 20'h80000 : ((switch_in[5] & (c5 != 20'hFFFFF)) ? c5 + 1 : ((~switch_in[5] & (c5 != 20'h00000)) ? c5 - 1 : c5)); + c6 <= (reset) ? 20'h80000 : ((switch_in[6] & (c6 != 20'hFFFFF)) ? c6 + 1 : ((~switch_in[6] & (c6 != 20'h00000)) ? c6 - 1 : c6)); + c7 <= (reset) ? 20'h80000 : ((switch_in[7] & (c7 != 20'hFFFFF)) ? c7 + 1 : ((~switch_in[7] & (c7 != 20'h00000)) ? c7 - 1 : c7)); + end + + always @(posedge clock) begin + switch_out[0] <= (reset) ? 0 : ((c0 == 20'h00000) ? 0 : ((c0 == 20'hFFFFF) ? 1 : switch_out[0])); + switch_out[1] <= (reset) ? 0 : ((c1 == 20'h00000) ? 0 : ((c1 == 20'hFFFFF) ? 1 : switch_out[1])); + switch_out[2] <= (reset) ? 0 : ((c2 == 20'h00000) ? 0 : ((c2 == 20'hFFFFF) ? 1 : switch_out[2])); + switch_out[3] <= (reset) ? 0 : ((c3 == 20'h00000) ? 0 : ((c3 == 20'hFFFFF) ? 1 : switch_out[3])); + switch_out[4] <= (reset) ? 0 : ((c4 == 20'h00000) ? 0 : ((c4 == 20'hFFFFF) ? 1 : switch_out[4])); + switch_out[5] <= (reset) ? 0 : ((c5 == 20'h00000) ? 0 : ((c5 == 20'hFFFFF) ? 1 : switch_out[5])); + switch_out[6] <= (reset) ? 0 : ((c6 == 20'h00000) ? 0 : ((c6 == 20'hFFFFF) ? 1 : switch_out[6])); + switch_out[7] <= (reset) ? 0 : ((c7 == 20'h00000) ? 0 : ((c7 == 20'hFFFFF) ? 1 : switch_out[7])); + end +*/ + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Switches/Switches.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Switches/Switches.v new file mode 100755 index 0000000..54a0779 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Switches/Switches.v @@ -0,0 +1,41 @@ +`timescale 1ns / 1ps +/* + * File : Switches.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 17-Jul-2012 GEA Initial design. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * A read interface between a 4-way handshaking data bus and + * 8 physical switches, which are debounced. + */ +module Switches( + input clock, + input reset, + input Read, + input Write, + input [7:0] Switch_in, // Direct from physical switches + output reg Ack, + output [7:0] Switch_out + ); + + always @(posedge clock) begin + Ack <= (reset) ? 0 : (Read | Write); + end + + // Low-level switch debounce filter + Switch_Filter Switch_Filter ( + .clock (clock), + .reset (reset), + .switch_in (Switch_in), + .switch_out (Switch_out) + ); + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Top.ucf b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Top.ucf new file mode 100755 index 0000000..dabb345 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Top.ucf @@ -0,0 +1,53 @@ + +# Clock and Reset +NET "clock_100Mhz" LOC = AH15 | IOSTANDARD = LVCMOS33; # 100 MHz +NET "clock_100MHz" TNM_NET = "BOARD_CLK"; +TIMESPEC "TS_BOARD_CLK" = PERIOD "BOARD_CLK" 10 ns HIGH 50 %; +NET "reset_n" LOC = E9 | IOSTANDARD = LVCMOS33; + +# UART +NET "UART_Rx" LOC = AG15 | IOSTANDARD = LVCMOS33; +NET "UART_Tx" LOC = AG20 | IOSTANDARD = LVCMOS33; + +# LCD Screen +NET "lcd[6]" LOC = T11 | IOSTANDARD = LVCMOS33; #D_4 +NET "lcd[5]" LOC = G6 | IOSTANDARD = LVCMOS33; #D_3 +NET "lcd[4]" LOC = G7 | IOSTANDARD = LVCMOS33; #D_2 +NET "lcd[3]" LOC = T9 | IOSTANDARD = LVCMOS33; #D_1 +NET "lcd[2]" LOC = AC9 | IOSTANDARD = LVCMOS33; #E +NET "lcd[1]" LOC = J17 | IOSTANDARD = LVCMOS25; #RS +NET "lcd[0]" LOC = AC10 | IOSTANDARD = LVCMOS33; #RW + +# General-Purpose LEDs +NET "LED[0]" LOC = AE24 | IOSTANDARD = SSTL18_I; # LED 7 +NET "LED[1]" LOC = AD24 | IOSTANDARD = SSTL18_I; # LED 6 +NET "LED[2]" LOC = AD25 | IOSTANDARD = SSTL18_I; # LED 5 +NET "LED[3]" LOC = G16 | IOSTANDARD = LVCMOS25; # LED 4 +NET "LED[4]" LOC = AD26 | IOSTANDARD = SSTL18_I; # LED 3 +NET "LED[5]" LOC = G15 | IOSTANDARD = LVCMOS25; # LED 2 +NET "LED[6]" LOC = L18 | IOSTANDARD = LVCMOS25; # LED 1 +NET "LED[7]" LOC = H18 | IOSTANDARD = LVCMOS25; # LED 0 +NET "LED[8]" LOC = E8 | IOSTANDARD = LVCMOS33; # LED Center +NET "LED[9]" LOC = AF23 | IOSTANDARD = LVCMOS33; # LED West +NET "LED[10]" LOC = AG12 | IOSTANDARD = LVCMOS33; # LED South +NET "LED[11]" LOC = AG23 | IOSTANDARD = LVCMOS33; # LED East +NET "LED[12]" LOC = AF13 | IOSTANDARD = LVCMOS33; # LED North +NET "LED[13]" LOC = F6 | IOSTANDARD = LVCMOS33; # LED Error 1 +NET "LED[14]" LOC = T10 | IOSTANDARD = LVCMOS33; # LED Error 2 + +# Piezo Transducer +NET "Piezo" LOC = G30 | IOSTANDARD = SSTL18_I; + +# General Purpose Switches +NET "Switch[7]" LOC = U25 | IOSTANDARD = SSTL18_I; # DIP 1 +NET "Switch[6]" LOC = AG27 | IOSTANDARD = SSTL18_I; # DIP 2 +NET "Switch[5]" LOC = AF25 | IOSTANDARD = SSTL18_I; # DIP 3 +NET "Switch[4]" LOC = AF26 | IOSTANDARD = SSTL18_I; # DIP 4 +NET "Switch[3]" LOC = AE27 | IOSTANDARD = SSTL18_I; # DIP 5 +NET "Switch[2]" LOC = AE26 | IOSTANDARD = SSTL18_I; # DIP 6 +NET "Switch[1]" LOC = AC25 | IOSTANDARD = SSTL18_I; # DIP 7 +NET "Switch[0]" LOC = AC24 | IOSTANDARD = SSTL18_I; # DIP 8 + +# Main IIC Bus +NET "i2c_scl" LOC = F9 | IOSTANDARD = LVCMOS33; # IIC_Main SCL +NET "i2c_sda" LOC = F8 | IOSTANDARD = LVCMOS33; # IIC_Main SDA diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Top.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Top.v new file mode 100755 index 0000000..17e5a02 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/Top.v @@ -0,0 +1,307 @@ +`timescale 1ns / 1ps +/* + * File : Top.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 8-Jul-2011 GEA Initial design. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * The top-level file for the FPGA. Also known as the 'motherboard,' this + * file connects all processor, memory, clocks, and I/O devices together. + * All inputs and outputs correspond to actual FPGA pins. + */ +module Top( + input clock_100MHz, + input reset_n, + // I/O + input [7:0] Switch, + output [14:0] LED, + output [6:0] LCD, + input UART_Rx, + output UART_Tx, + inout i2c_scl, + inout i2c_sda, + output Piezo + ); + + + // Clock signals + wire clock, clock2x; + wire PLL_Locked; + + reg reset; + always @(posedge clock) begin + reset <= ~reset_n | ~PLL_Locked; + end + + // MIPS Processor Signals + reg [31:0] MIPS32_DataMem_In; + wire [31:0] MIPS32_DataMem_Out, MIPS32_InstMem_In; + wire [29:0] MIPS32_DataMem_Address, MIPS32_InstMem_Address; + wire [3:0] MIPS32_DataMem_WE; + wire MIPS32_DataMem_Read, MIPS32_InstMem_Read; + reg MIPS32_DataMem_Ready; + wire [4:0] MIPS32_Interrupts; + wire MIPS32_NMI; + wire [7:0] MIPS32_IP; + wire MIPS32_IO_WE; + + // BRAM Memory Signals + reg [3:0] BRAM_WEA; + reg BRAM_REA; + reg [17:0] BRAM_AddrA; + reg [31:0] BRAM_DINA; + wire BRAM_ReadyA; + wire BRAM_REB; + wire [3:0] BRAM_WEB; + wire [31:0] BRAM_DOUTB; + wire BRAM_ReadyB; + + // LCD Signals + wire [3:0] LCD_WE; + wire LCD_Ready; + + // UART Bootloader Signals + wire UART_RE; + wire UART_WE; + wire [16:0] UART_DOUT; + wire UART_Ack; + wire UART_Interrupt; + wire UART_BootResetCPU; + wire [17:0] UART_BootAddress; + wire [31:0] UART_BootData; + wire UART_BootWriteMem_pre; + wire [3:0] UART_BootWriteMem = (UART_BootWriteMem_pre) ? 4'hF : 4'h0; + + // I2C Signals + wire I2C_Ready; + wire [10:0] I2C_DOUT; + wire I2C_RE, I2C_WE; + + // Piezo Transducer Signals + wire Piezo_WE; + wire Piezo_Ready; + + // LED Signals + wire LED_WE; + wire LED_RE; + wire [13:0] LED_DOUT; + wire LED_Ready; + wire [13:0] LED_Sw_LEDs; + + // Filtered Switch Input Signals + wire Switches_RE; + wire Switches_WE; + wire Switches_Ready; + wire [7:0] Switches_DOUT; + + // Clock Generation + PLL_100MHz_to_33MHz_66MHz Clock_Generator ( + .CLKIN1_IN (clock_100MHz), + .RST_IN (1'b0), + .CLKOUT0_OUT (clock), + .CLKOUT1_OUT (clock2x), + .LOCKED_OUT (PLL_Locked) + ); + + // MIPS-32 Core + Processor MIPS32 ( + .clock (clock), + .reset ((reset | UART_BootResetCPU)), + .Interrupts (MIPS32_Interrupts), + .NMI (MIPS32_NMI), + .DataMem_In (MIPS32_DataMem_In), + .DataMem_Ready (MIPS32_DataMem_Ready), + .DataMem_Read (MIPS32_DataMem_Read), + .DataMem_Write (MIPS32_DataMem_WE), + .DataMem_Address (MIPS32_DataMem_Address), + .DataMem_Out (MIPS32_DataMem_Out), + .InstMem_In (MIPS32_InstMem_In), + .InstMem_Address (MIPS32_InstMem_Address), + .InstMem_Ready (BRAM_ReadyA), + .InstMem_Read (MIPS32_InstMem_Read), + .IP (MIPS32_IP) + ); + + // On-Chip Block RAM + BRAM_592KB_Wrapper Memory ( + .clock (clock2x), + .reset (reset), + .rea (BRAM_REA), + .wea (BRAM_WEA), + .addra (BRAM_AddrA), + .dina (BRAM_DINA), + .douta (MIPS32_InstMem_In), + .dreadya (BRAM_ReadyA), + .reb (BRAM_REB), + .web (BRAM_WEB), + .addrb (MIPS32_DataMem_Address[17:0]), + .dinb (MIPS32_DataMem_Out), + .doutb (BRAM_DOUTB), + .dreadyb (BRAM_ReadyB) + ); + + // 16x2 LCD Display Screen + LCD LCD_Screen ( + .clock_100MHz (clock2x), + .clock_Mem (clock2x), + .reset (reset), + .address (MIPS32_DataMem_Address[2:0]), + .data (MIPS32_DataMem_Out), + .writeEnable (LCD_WE), + .ack (LCD_Ready), + .LCD (LCD) + ); + + // UART + Boot Loader (v2) + uart_bootloader UART ( + .clock (clock2x), + .reset (reset), + .Read (UART_RE), + .Write (UART_WE), + .DataIn (MIPS32_DataMem_Out[8:0]), + .DataOut (UART_DOUT), + .Ack (UART_Ack), + .DataReady (UART_Interrupt), + .BootResetCPU (UART_BootResetCPU), + .BootWriteMem (UART_BootWriteMem_pre), + .BootAddr (UART_BootAddress), + .BootData (UART_BootData), + .RxD (UART_Rx), + .TxD (UART_Tx) + ); + + // I2C Module + I2C_Controller I2C ( + .clock (clock2x), + .reset (reset), + .Read (I2C_RE), + .Write (I2C_WE), + .DataIn (MIPS32_DataMem_Out[12:0]), + .DataOut (I2C_DOUT), + .Ack (I2C_Ready), + .i2c_scl (i2c_scl), + .i2c_sda (i2c_sda) + ); + + // Piezo-electric Transducer + Piezo_Driver Piezo_Driver ( + .clock (clock2x), + .reset (reset), + .data (MIPS32_DataMem_Out[24:0]), + .Write (Piezo_WE), + .Ack (Piezo_Ready), + .Piezo (Piezo) + ); + + // LEDs + LED LEDs ( + .clock (clock2x), + .reset (reset), + .dataIn (MIPS32_DataMem_Out[14:0]), + .IP (MIPS32_IP), + .Write (LED_WE), + .Read (LED_RE), + .dataOut (LED_DOUT), + .Ack (LED_Ready), + .LED (LED_Sw_LEDs) + ); + + // Filtered Input Switches + Switches Switches ( + .clock (clock2x), + .reset (reset), + .Read (Switches_RE), + .Write (Switches_WE), + .Switch_in (Switch), + .Ack (Switches_Ready), + .Switch_out (Switches_DOUT) + ); + + + assign MIPS32_IO_WE = (MIPS32_DataMem_WE == 4'hF) ? 1 : 0; + assign MIPS32_Interrupts[4:1] = Switches_DOUT[7:4]; + assign MIPS32_Interrupts[0] = UART_Interrupt; + assign MIPS32_NMI = Switches_DOUT[3]; + assign LED = {UART_BootResetCPU, LED_Sw_LEDs[13:0]}; + + // Allow writes to Instruction Memory Port when bootloading + always @(*) begin + BRAM_REA <= (UART_BootResetCPU) ? 0 : MIPS32_InstMem_Read; + BRAM_WEA <= (UART_BootResetCPU) ? UART_BootWriteMem : 4'h0; + BRAM_AddrA <= (UART_BootResetCPU) ? UART_BootAddress : MIPS32_InstMem_Address; + BRAM_DINA <= (UART_BootResetCPU) ? UART_BootData : 32'h0000_0000; + end + + + always @(*) begin + case (MIPS32_DataMem_Address[29]) + 0 : begin + MIPS32_DataMem_In <= BRAM_DOUTB; + MIPS32_DataMem_Ready <= BRAM_ReadyB; + end + 1 : begin + // Memory-mapped I/O + case (MIPS32_DataMem_Address[28:26]) + // LCD + 3'b000 : begin + MIPS32_DataMem_In <= 32'h0000_0000; + MIPS32_DataMem_Ready <= LCD_Ready; + end + // I2C + 3'b001 : begin + MIPS32_DataMem_In <= {21'h000000, I2C_DOUT[10:0]}; + MIPS32_DataMem_Ready <= I2C_Ready; + end + // Piezo + 3'b010 : begin + MIPS32_DataMem_In <= 32'h0000_0000; + MIPS32_DataMem_Ready <= Piezo_Ready; + end + // UART + 3'b011 : begin + MIPS32_DataMem_In <= {15'h0000, UART_DOUT[16:0]}; + MIPS32_DataMem_Ready <= UART_Ack; + end + // LED + 3'b100 : begin + MIPS32_DataMem_In <= {18'h00000, LED_DOUT[13:0]}; + MIPS32_DataMem_Ready <= LED_Ready; + end + // Switches + 3'b101 : begin + MIPS32_DataMem_In <= {24'h000000, Switches_DOUT[7:0]}; + MIPS32_DataMem_Ready <= Switches_Ready; + end + default: begin + MIPS32_DataMem_In <= 32'h0000_0000; + MIPS32_DataMem_Ready <= 0; + end + endcase + end + endcase + end + + // Memory + assign BRAM_REB = (MIPS32_DataMem_Address[29]) ? 0 : MIPS32_DataMem_Read; + assign BRAM_WEB = (MIPS32_DataMem_Address[29]) ? 4'h0 : MIPS32_DataMem_WE; + // I/O + assign LCD_WE = (MIPS32_DataMem_Address[29:26] == 4'b1000) ? MIPS32_DataMem_WE : 4'h0; + assign Piezo_WE = (MIPS32_DataMem_Address[29:26] == 4'b1010) ? MIPS32_IO_WE : 0; + assign I2C_WE = (MIPS32_DataMem_Address[29:26] == 4'b1001) ? MIPS32_IO_WE : 0; + assign I2C_RE = (MIPS32_DataMem_Address[29:26] == 4'b1001) ? MIPS32_DataMem_Read : 0; + assign UART_WE = (MIPS32_DataMem_Address[29:26] == 4'b1011) ? MIPS32_IO_WE : 0; + assign UART_RE = (MIPS32_DataMem_Address[29:26] == 4'b1011) ? MIPS32_DataMem_Read : 0; + assign LED_WE = (MIPS32_DataMem_Address[29:26] == 4'b1100) ? MIPS32_IO_WE : 0; + assign LED_RE = (MIPS32_DataMem_Address[29:26] == 4'b1100) ? MIPS32_DataMem_Read : 0; + assign Switches_WE = (MIPS32_DataMem_Address[29:26] == 4'b1101) ? MIPS32_IO_WE : 0; + assign Switches_RE = (MIPS32_DataMem_Address[29:26] == 4'b1101) ? MIPS32_DataMem_Read : 0; + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/UART/uart-min.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/UART/uart-min.v new file mode 100755 index 0000000..32433c6 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/UART/uart-min.v @@ -0,0 +1,129 @@ +`timescale 1ns / 1ps +/* + * File : uart-min.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 24-May-2010 GEA Initial design. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * 115200 baud 8-N-1 serial port, using only Tx and Rx. + * (8 data bits, no parity, 1 stop bit, no flow control.) + * Configurable baud rate determined by clocking module, 16x oversampling + * for Rx data, Rx filtering, and configurable FIFO buffers for receiving + * and transmitting. + * + * Described as '_min' due to lack of overflow and other status signals + * as well as the use of only Tx and Rx signals. + */ +module uart_min( + input clock, + input reset, + input write, + input [7:0] data_in, // tx going into uart, out of serial port + input read, + output [7:0] data_out, // rx coming in from serial port, out of uart + output data_ready, + output [8:0] rx_count, + /*------------------------*/ + input RxD, + output TxD + ); + + localparam DATA_WIDTH = 8; // Bit-width of FIFO data (should be 8) + localparam ADDR_WIDTH = 8; // 2^ADDR_WIDTH words of FIFO space + + /* Clocking Signals */ + wire uart_tick, uart_tick_16x; + + /* Receive Signals */ + wire [7:0] rx_data; // Raw bytes coming in from uart + wire rx_data_ready; // Synchronous pulse indicating this (^) + wire rx_fifo_empty; + + /* Send Signals */ + reg tx_fifo_deQ = 0; + reg tx_start = 0; + wire tx_free; + wire tx_fifo_empty; + wire [7:0] tx_fifo_data_out; + + assign data_ready = ~rx_fifo_empty; + + always @(posedge clock) begin + if (reset) begin + tx_fifo_deQ <= 0; + tx_start <= 0; + end + else begin + if (~tx_fifo_empty & tx_free & uart_tick) begin + tx_fifo_deQ <= 1; + tx_start <= 1; + end + else begin + tx_fifo_deQ <= 0; + tx_start <= 0; + end + end + end + + uart_clock clocks ( + .clock (clock), + .uart_tick (uart_tick), + .uart_tick_16x (uart_tick_16x) + ); + + uart_tx tx ( + .clock (clock), + .reset (reset), + .uart_tick (uart_tick), + .TxD_data (tx_fifo_data_out), + .TxD_start (tx_start), + .ready (tx_free), + .TxD (TxD) + ); + + uart_rx rx ( + .clock (clock), + .reset (reset), + .RxD (RxD), + .uart_tick_16x (uart_tick_16x), + .RxD_data (rx_data), + .data_ready (rx_data_ready) + ); + + FIFO_NoFull_Count #( + .DATA_WIDTH (DATA_WIDTH), + .ADDR_WIDTH (ADDR_WIDTH)) + tx_buffer ( + .clock (clock), + .reset (reset), + .enQ (write), + .deQ (tx_fifo_deQ), + .data_in (data_in), + .data_out (tx_fifo_data_out), + .empty (tx_fifo_empty), + .count () + ); + + FIFO_NoFull_Count #( + .DATA_WIDTH (DATA_WIDTH), + .ADDR_WIDTH (ADDR_WIDTH)) + rx_buffer ( + .clock (clock), + .reset (reset), + .enQ (rx_data_ready), + .deQ (read), + .data_in (rx_data), + .data_out (data_out), + .empty (rx_fifo_empty), + .count (rx_count) + ); + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/UART/uart_bootloader_v1.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/UART/uart_bootloader_v1.v new file mode 100755 index 0000000..fa84458 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/UART/uart_bootloader_v1.v @@ -0,0 +1,183 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: Grant Ayers (ayers@cs.utah.edu) +// +// Create Date: 09:59:05 05/24/2010 +// Design Name: +// Module Name: uart_bootloader +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// Implements the XUM bootloader protocol over a serial port (115200 8N1). +// The protocol is as follows: +// +// 1. Programmer sends 'XUM' ascii bytes +// 2. Programmer sends a number indicating how many 32-bit data words it +// has to send, minus 1. (For example, if it has one 32-bit data word, +// this number will be 0.) The size of this number is 18 bits. +// This means the minimum transmission size is 1 word (32 bits), and +// the maximum transmission size is 262144 words (exactly 1MB). +// This 18-bit number is sent in three bytes, and the six most +// significant bits of the first byte must be 0. +// 3. The FPGA sends back the third size byte from the programmer, allowing +// the programmer to determine if the FPGA is listening and conforming +// to the XUM boot protocol. +// 4. The programmer sends another 18-bit number indicating the starting +// offset in memory where the data should be placed. Normally this will +// be 0. This number is also sent in three bytes, and the six most +// significant bits of the first byte are ignored. +// 5. The programmer sends the data. A copy of each byte that it sends will +// be sent back to the programmer from the FPGA, allowing the programmer +// to determine if all of the data was transmitted successfully. +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module uart_bootloader( + input clock, // 100Mhz + input reset, // System-wide global reset + input RxD, // UART data from computer + output TxD, // UART data to computer + output resetCPU, // Reset CPUs' PCs to start execution at 0x0 + output reg writeMem = 0, // Write command to instruction memory + output reg [17:0] addrMem = 0, // address to instruction memory + output reg [31:0] dataMem = 0 // 32-bit data words of instruction memory + ); + + localparam [3:0] HEAD_1=0, HEAD_2=1, HEAD_3=2, SIZE_1=3, SIZE_2=4, SIZE_3=5, OFST_1=6, OFST_2=7, + OFST_3=8, ADDRSET=9, DATA_1=10, DATA_2=11, DATA_3=12, DATA_4=13, ADDRINC=14; + + /* UART Signals */ + reg uart_write = 0; + reg uart_read = 0; + + wire [7:0] uart_rx_data; + wire [7:0] uart_tx_data = uart_rx_data; + wire uart_rx_data_ready; + + reg [17:0] size = 0; // Number of 32-bit words to expect + reg [17:0] offset = 0; // Starting address to store words + reg [17:0] rx_count = 0; // Number of 32-bit words received so far + + reg [3:0] state = HEAD_1; + + // The CPU(s) is continuously reset while memory is being replaced. + assign resetCPU = ((state!=HEAD_1) && (state!=HEAD_2) && (state!=HEAD_3) && (state!=SIZE_1)); + + always @(posedge clock) begin + if (reset) begin + state <= HEAD_1; + uart_read <= 0; + uart_write <= 0; + writeMem <= 0; + rx_count <= 0; + end + else begin + uart_read <= uart_rx_data_ready & ((state!=ADDRSET) && (state!=ADDRINC)); + uart_write <= uart_rx_data_ready & ((state==SIZE_3) || (state==DATA_1) || (state==DATA_2) || (state==DATA_3) || (state==DATA_4)); + writeMem <= uart_rx_data_ready & (state == DATA_4); + rx_count <= (state == HEAD_1) ? 0 : ((state == ADDRINC) ? rx_count + 1 : rx_count); + case (state) + HEAD_1: begin + if (uart_rx_data_ready) begin + state <= (uart_rx_data == 8'h58) ? HEAD_2 : HEAD_1; // 'X' + end + else begin + state <= HEAD_1; + end + end + HEAD_2: begin + if (uart_rx_data_ready) begin + state <= (uart_rx_data == 8'h55) ? HEAD_3 : HEAD_1; // 'U' + end + else begin + state <= HEAD_2; + end + end + HEAD_3: begin + if (uart_rx_data_ready) begin + state <= (uart_rx_data == 8'h4D) ? SIZE_1 : HEAD_1; // 'M' + end + else begin + state <= HEAD_3; + end + end + SIZE_1: begin + if (uart_rx_data_ready) begin + state <= (uart_rx_data[7:2] == 6'b000000) ? SIZE_2 : HEAD_1; // 6 leading 0s + size[17:16] <= uart_rx_data[1:0]; + end + else begin + state <= SIZE_1; + end + end + SIZE_2: begin + state <= (uart_rx_data_ready) ? SIZE_3 : SIZE_2; + size[15:8] <= (uart_rx_data_ready) ? uart_rx_data : size[15:8]; + end + SIZE_3: begin + state <= (uart_rx_data_ready) ? OFST_1 : SIZE_3; + size[7:0] <= (uart_rx_data_ready) ? uart_rx_data : size[7:0]; + end + OFST_1: begin + state <= (uart_rx_data_ready) ? OFST_2 : OFST_1; + offset[17:16] <= (uart_rx_data_ready) ? uart_rx_data[1:0] : offset[17:16]; + end + OFST_2: begin + state <= (uart_rx_data_ready) ? OFST_3 : OFST_2; + offset[15:8] <= (uart_rx_data_ready) ? uart_rx_data : offset[15:8]; + end + OFST_3: begin + state <= (uart_rx_data_ready) ? ADDRSET : OFST_3; + offset[7:0] <= (uart_rx_data_ready) ? uart_rx_data : offset[7:0]; + end + ADDRSET: begin + state <= DATA_1; + addrMem <= offset; + end + DATA_1: begin + state <= (uart_rx_data_ready) ? DATA_2 : DATA_1; + dataMem[31:24] <= (uart_rx_data_ready) ? uart_rx_data : dataMem[31:24]; + end + DATA_2: begin + state <= (uart_rx_data_ready) ? DATA_3 : DATA_2; + dataMem[23:16] <= (uart_rx_data_ready) ? uart_rx_data : dataMem[23:16]; + end + DATA_3: begin + state <= (uart_rx_data_ready) ? DATA_4 : DATA_3; + dataMem[15:8] <= (uart_rx_data_ready) ? uart_rx_data : dataMem[15:8]; + end + DATA_4: begin + state <= (uart_rx_data_ready) ? ADDRINC : DATA_4; + dataMem[7:0] <= (uart_rx_data_ready) ? uart_rx_data : dataMem[7:0]; + end + ADDRINC: begin + addrMem <= addrMem + 1; + state <= (rx_count == size) ? HEAD_1 : DATA_1; + end + default: state <= HEAD_1; + endcase + end + end + + + uart_min uart ( + .clock (clock), + .reset (reset), + .write (uart_write), + .data_in (uart_tx_data), + .read (uart_read), + .data_out (uart_rx_data), + .data_ready (uart_rx_data_ready), + .RxD (RxD), + .TxD (TxD) + ); + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/UART/uart_bootloader_v2.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/UART/uart_bootloader_v2.v new file mode 100755 index 0000000..0285215 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/UART/uart_bootloader_v2.v @@ -0,0 +1,221 @@ +`timescale 1ns / 1ps +/* + * File : uart_bootloader_v2.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 24-May-2010 GEA Initial design of standalone bootloader + * 2.0 7-Jul-2012 GEA Added data memory bus to allow for general-purpose use. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * An RS-232 compatible UART coupled with the XUM bootloader. + * + * The UART is general-purpose and capable of sending and receiving at a + * pre-determined BAUD rate (determined by the clocking module) + * with 8 data bits, 1 stop bit, and no parity. In other words it + * is 8N1 with only RxD and TxD signals. It uses two 256-byte FIFO + * buffers, one for receiving and the other for transmitting. + * + * The XUM bootloader protocol is as follows: + * + * 1. Programmer sends 'XUM' ASCII bytes. + * 2. Programmer sends a number indicating how many 32-bit data words + * it has to send, minus 1. (For example, if it has one 32-bit data word, + * this number would be 0.) The size of this number is 18 bits. + * This means the minimum transmission size is 1 word (32 bits), and + * the maximum transmission size is 262144 words, or exactly 1 MB. + * This 18-bit number is sent MSB first, in three bytes, with the six + * most-significant bits set to 0. + * 3. The FPGA sends back the third size byte from the programmer, allowing + * the programmer to determine if the FPGA is listening and conforming + * to the XUM boot protocol. + * 4. The programmer sends another 18-bit number indicating the starting + * offset in memory where the data should be placed. Normally this will + * be 0. This number is also sent in three bytes, and the six most-significant + * bits of the first byte are ignored. + * 5. The programmer sends the data. A copy of each byte that it sends will be + * sent back to the programmer from the FPGA, allowing the programmer + * to determine if all of the data was transmitted successfully. + * + * On reset, the bootloader is enabled by default. When the bootloader is enabled, + * the data memory bus will not see any incoming data. To configure the UART for + * general-purpose use, software must issue a write command to the UART + * over the data memory bus with bit 8 set. This disables the boot protocol until + * the UART is reset again and allows normal use. Note however that there is + * a 5-second guard time after reset during which the boot loader is + * enabled regardless of any software commands to disable it. After the 5 second + * time has lapsed after reset, the software state determines the operating mode + * of the UART. + */ +module uart_bootloader( + input clock, + input reset, + input Read, // MMIO + input Write, // MMIO + input [8:0] DataIn, // MMIO + output reg [16:0] DataOut, // MMIO + output Ack, // MMIO + output DataReady, // Can be used as an interrupt + output BootResetCPU, // XUM Boot Protocol: Reset CPU + output BootWriteMem, // XUM Boot Protocol: Write to CPU memory + output reg [17:0] BootAddr, // XUM Boot Protocol + output reg [31:0] BootData, // XUM Boot Protocol + input RxD, // UART Rx Signal + output TxD // UART Tx Signal + ); + + localparam [4:0] IDLE=0, WRITE=1, READ=2, BUSW=3, XHEAD1=4, XHEAD2=5, XHEAD3=6, XSIZE1=7, XSIZE2=8, XSIZE3=9, + XOFST1=10, XOFST2=11, XOFST3=12, XDATA1=13, XDATA2=14, XDATA3=15, XDATA4=16, XADDRI=17; + + // UART module signals + wire uart_write; + reg uart_read; + wire uart_data_ready; + wire [7:0] uart_data_in; + wire [7:0] uart_data_out; + wire [8:0] uart_rx_count; + + reg [8:0] DataIn_r; // Latch for incoming data to improve timing + wire DisableBoot = DataIn_r[8]; // Software boot disable command is bit 8 + reg [28:0] BootTimedEnable; // Hardware override enabler for boot loader after reset + reg BootSwEnabled; // Software enabled/disabled state of bootloader + wire BootProtoEnabled; // Master bootloader enabled signal + reg [17:0] rx_count; // Number of 32-bit words received (boot loader) + reg [17:0] rx_size; // Number of 32-bit words to expect (boot loader) + reg [4:0] state; + + always @(posedge clock) begin + if (reset) begin + state <= IDLE; + end + else begin + case (state) + IDLE: begin + if (Write) state <= WRITE; + else if (Read) state <= READ; + else if (BootProtoEnabled & uart_data_ready) state <= XHEAD1; + else state <= IDLE; + end + WRITE: state <= BUSW; + READ: state <= BUSW; + BUSW: state <= ~(Read | Write) ? IDLE : BUSW; + XHEAD1: state <= (uart_data_out == 8'h58) ? XHEAD2 : IDLE; // 'X' + XHEAD2: state <= (uart_data_ready) ? ((uart_data_out == 8'h55) ? XHEAD3 : IDLE) : XHEAD2; // 'U' + XHEAD3: state <= (uart_data_ready) ? ((uart_data_out == 8'h4D) ? XSIZE1 : IDLE) : XHEAD3; // 'M' + XSIZE1: state <= (uart_data_ready) ? ((uart_data_out[7:2] == 6'b000000) ? XSIZE2 : IDLE) : XSIZE1; + XSIZE2: state <= (uart_data_ready) ? XSIZE3 : XSIZE2; + XSIZE3: state <= (uart_data_ready) ? XOFST1 : XSIZE3; + XOFST1: state <= (uart_data_ready) ? XOFST2 : XOFST1; + XOFST2: state <= (uart_data_ready) ? XOFST3 : XOFST2; + XOFST3: state <= (uart_data_ready) ? XDATA1 : XOFST3; + XDATA1: state <= (uart_data_ready) ? XDATA2 : XDATA1; + XDATA2: state <= (uart_data_ready) ? XDATA3 : XDATA2; + XDATA3: state <= (uart_data_ready) ? XDATA4 : XDATA3; + XDATA4: state <= (uart_data_ready) ? XADDRI : XDATA4; + XADDRI: state <= (rx_count == rx_size) ? IDLE : XDATA1; + default: state <= IDLE; + endcase + end + end + + always @(*) begin + case (state) + IDLE: uart_read <= 0; + WRITE: uart_read <= 0; + READ: uart_read <= 1; + BUSW: uart_read <= 0; + XHEAD1: uart_read <= uart_data_ready; + XHEAD2: uart_read <= uart_data_ready; + XHEAD3: uart_read <= uart_data_ready; + XSIZE1: uart_read <= uart_data_ready; + XSIZE2: uart_read <= uart_data_ready; + XSIZE3: uart_read <= uart_data_ready; + XOFST1: uart_read <= uart_data_ready; + XOFST2: uart_read <= uart_data_ready; + XOFST3: uart_read <= uart_data_ready; + XDATA1: uart_read <= uart_data_ready; + XDATA2: uart_read <= uart_data_ready; + XDATA3: uart_read <= uart_data_ready; + XDATA4: uart_read <= uart_data_ready; + XADDRI: uart_read <= 0; + default: uart_read <= 0; + endcase + end + + always @(posedge clock) begin + DataIn_r <= ((state == IDLE) & Write) ? DataIn : DataIn_r; + end + + always @(posedge clock) begin + DataOut <= (reset) ? 17'h00000 : ((state == READ) ? {uart_rx_count[8:0], uart_data_out[7:0]} : DataOut); + end + + always @(posedge clock) begin + BootTimedEnable <= (reset) ? 29'h00000000 : (BootTimedEnable != 29'h1dcd6500) ? BootTimedEnable + 1 : BootTimedEnable; // 5 sec @ 100 MHz + BootSwEnabled <= (reset) ? 1 : ((state == WRITE) ? ~DisableBoot : BootSwEnabled); + end + + assign BootResetCPU = (state != IDLE) && (state != WRITE) && (state != READ) && (state != BUSW) && + (state != XHEAD1) && (state != XHEAD2) && (state != XHEAD3) && (state != XSIZE1); + assign BootWriteMem = (state == XADDRI); + assign uart_write = ((state == WRITE) & ~DisableBoot) | + (uart_data_ready & ((state == XSIZE3) | (state == XDATA1) | (state == XDATA2) | (state == XDATA3) | (state == XDATA4))); + assign uart_data_in = (state == WRITE) ? DataIn_r[7:0] : uart_data_out; + assign Ack = (state == BUSW); + assign DataReady = uart_data_ready; + assign BootProtoEnabled = BootSwEnabled | (BootTimedEnable != 29'h1dcd6500); + + + // XUM Boot Protocol Logic + always @(posedge clock) begin + BootData[31:24] <= (reset) ? 8'h00 : (((state == XDATA1) & uart_data_ready) ? uart_data_out : BootData[31:24]); + BootData[23:16] <= (reset) ? 8'h00 : (((state == XDATA2) & uart_data_ready) ? uart_data_out : BootData[23:16]); + BootData[15:8] <= (reset) ? 8'h00 : (((state == XDATA3) & uart_data_ready) ? uart_data_out : BootData[15:8]); + BootData[7:0] <= (reset) ? 8'h00 : (((state == XDATA4) & uart_data_ready) ? uart_data_out : BootData[7:0]); + end + + always @(posedge clock) begin + if (reset) begin + BootAddr <= 18'h00000; + end + else if (state == XADDRI) begin + BootAddr <= BootAddr + 1; + end + else begin + BootAddr[17:16] <= ((state == XOFST1) & uart_data_ready) ? uart_data_out[1:0] : BootAddr[17:16]; + BootAddr[15:8] <= ((state == XOFST2) & uart_data_ready) ? uart_data_out[7:0] : BootAddr[15:8]; + BootAddr[7:0] <= ((state == XOFST3) & uart_data_ready) ? uart_data_out[7:0] : BootAddr[7:0]; + end + end + + always @(posedge clock) begin + rx_count <= (state == IDLE) ? 18'h00000 : ((state == XADDRI) ? rx_count + 1 : rx_count); + end + + always @(posedge clock) begin + rx_size[17:16] <= (reset) ? 2'b00 : (((state == XSIZE1) & uart_data_ready) ? uart_data_out[1:0] : rx_size[17:16]); + rx_size[15:8] <= (reset) ? 8'h00 : (((state == XSIZE2) & uart_data_ready) ? uart_data_out[7:0] : rx_size[15:8]); + rx_size[7:0] <= (reset) ? 8'h00 : (((state == XSIZE3) & uart_data_ready) ? uart_data_out[7:0] : rx_size[7:0]); + end + + // UART Driver + uart_min UART ( + .clock (clock), + .reset (reset), + .write (uart_write), + .data_in (uart_data_in), + .read (uart_read), + .data_out (uart_data_out), + .data_ready (uart_data_ready), + .rx_count (uart_rx_count), + .RxD (RxD), + .TxD (TxD) + ); + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/UART/uart_clock.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/UART/uart_clock.v new file mode 100755 index 0000000..377de93 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/UART/uart_clock.v @@ -0,0 +1,56 @@ +`timescale 1ns / 1ps +/* + * File : uart_clock.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 24-May-2010 GEA Initial design. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * Takes a 100 MHz clock and generates synchronous pulses for 115200 baud + * and 16x 115200 baud (synchronized). + * + * This timing can be adjusted to allow for other baud rates. + */ +module uart_clock( + input clock, + output uart_tick, + output uart_tick_16x + ); + + // 100MHz / (2^13 / 151) == 16 * 115203.857 Hz + // 100MHz / (2^17 / 151) == 115203.857 Hz + // 66MHz / (2^14 / 453) == 16 * 115203.857 Hz + // 66MHz / (2^18 / 453) == 115203.857 Hz + + + // 66 MHz version + reg [14:0] accumulator = 15'h0000; + always @(posedge clock) begin + accumulator <= accumulator[13:0] + 453; + end + assign uart_tick_16x = accumulator[14]; + +/* + // 100 MHz version + reg [13:0] accumulator = 14'h0000; + always @(posedge clock) begin + accumulator <= accumulator[12:0] + 151; + end + assign uart_tick_16x = accumulator[13]; +*/ + + //------------------------------ + reg [3:0] uart_16x_count = 4'h0; + always @(posedge clock) begin + uart_16x_count <= (uart_tick_16x) ? uart_16x_count + 1 : uart_16x_count; + end + assign uart_tick = (uart_tick_16x==1'b1 && (uart_16x_count == 4'b1111)); + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/UART/uart_rx.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/UART/uart_rx.v new file mode 100755 index 0000000..c57c2aa --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/UART/uart_rx.v @@ -0,0 +1,96 @@ +`timescale 1ns / 1ps +/* + * File : uart_rx.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 26-May-2010 GEA Initial design. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * Recovers received data from the serial port with 16x clock over-sampling. + * 'data_ready' is a synchronous pulse indicator. 8N1. + */ +module uart_rx( + input clock, + input reset, + input RxD, + input uart_tick_16x, + output reg [7:0] RxD_data = 0, + output data_ready + ); + + /* Synchronize incoming RxD */ + reg [1:0] RxD_sync = 2'b11; //0; + always @(posedge clock) RxD_sync <= (uart_tick_16x) ? {RxD_sync[0], RxD} : RxD_sync; + + /* Filter Input */ + reg [1:0] RxD_cnt = 0; + reg RxD_bit = 1; //0; + always @(posedge clock) begin + if (uart_tick_16x) begin + case (RxD_sync[1]) + 0: RxD_cnt <= (RxD_cnt == 2'b11) ? RxD_cnt : RxD_cnt + 1; + 1: RxD_cnt <= (RxD_cnt == 2'b00) ? RxD_cnt : RxD_cnt - 1; + endcase + RxD_bit <= (RxD_cnt == 2'b11) ? 0 : ((RxD_cnt == 2'b00) ? 1 : RxD_bit); + end + else begin + RxD_cnt <= RxD_cnt; + RxD_bit <= RxD_bit; + end + end + + /* State Definitions */ + localparam [3:0] IDLE=0, BIT_0=1, BIT_1=2, BIT_2=3, BIT_3=4, BIT_4=5, BIT_5=6, + BIT_6=7, BIT_7=8, STOP=9; + reg [3:0] state = IDLE; + + /* Next-bit spacing and clock locking */ + reg clock_lock = 0; + reg [3:0] bit_spacing = 4'b1110; // Enable quick jumping from IDLE to BIT_0 when line was idle. + always @(posedge clock) begin + if (uart_tick_16x) begin + if (~clock_lock) clock_lock <= ~RxD_bit; // We lock on when we detect a filtered 0 from idle + else clock_lock <= ((state == IDLE) && (RxD_bit == 1'b1)) ? 0 : clock_lock; + bit_spacing <= (clock_lock) ? bit_spacing + 1 : 4'b1110; + end + else begin + clock_lock <= clock_lock; + bit_spacing <= bit_spacing; + end + end + wire next_bit = (bit_spacing == 4'b1111); + + /* State Machine */ + always @(posedge clock) begin + if (reset) state <= IDLE; + else if (uart_tick_16x) begin + case (state) + IDLE: state <= (next_bit & (RxD_bit == 1'b0)) ? BIT_0 : IDLE; // Start bit is 0 + BIT_0: state <= (next_bit) ? BIT_1 : BIT_0; + BIT_1: state <= (next_bit) ? BIT_2 : BIT_1; + BIT_2: state <= (next_bit) ? BIT_3 : BIT_2; + BIT_3: state <= (next_bit) ? BIT_4 : BIT_3; + BIT_4: state <= (next_bit) ? BIT_5 : BIT_4; + BIT_5: state <= (next_bit) ? BIT_6 : BIT_5; + BIT_6: state <= (next_bit) ? BIT_7 : BIT_6; + BIT_7: state <= (next_bit) ? STOP : BIT_7; + STOP: state <= (next_bit) ? IDLE : STOP; + default: state <= 4'bxxxx; + endcase + end + else state <= state; + end + + /* Shift Register to Collect Rx bits as they come */ + wire capture = (uart_tick_16x & next_bit & (state!=IDLE) & (state!=STOP)); + always @(posedge clock) RxD_data <= (capture) ? {RxD_bit, RxD_data[7:1]} : RxD_data[7:0]; + assign data_ready = (uart_tick_16x & next_bit & (state==STOP)); + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/UART/uart_tx.v b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/UART/uart_tx.v new file mode 100755 index 0000000..dd3edf7 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Hardware/XUPV5-LX110T_SoC/MIPS32-Pipelined-Hw/src/UART/uart_tx.v @@ -0,0 +1,79 @@ +`timescale 1ns / 1ps +/* + * File : uart_tx.v + * Project : University of Utah, XUM Project MIPS32 core + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 25-Mar-2010 GEA Initial design. + * + * Standards/Formatting: + * Verilog 2001, 4 soft tab, wide column. + * + * Description: + * Transmits bytes of data from the serial port. Capable of back-to-back + * transmission of data for maximum bandwidth utilization. + * 'TxD_start' must only pulse with a 'uart_tick' pulse. 8N1. + */ +module uart_tx ( + input clock, + input reset, + input uart_tick, + input [7:0] TxD_data, + input TxD_start, // Must happen with a uart_tick + output ready, + output reg TxD + ); + + localparam [3:0] IDLE=0, START=1, BIT_0=2, BIT_1=3, BIT_2=4, BIT_3=5, + BIT_4=6, BIT_5=7, BIT_6=8, BIT_7=9, STOP=10; + + reg [3:0] tx_state = IDLE; + reg [7:0] TxD_data_r = 8'h00; // Registered input data so it doesn't need to be held + + assign ready = (tx_state == IDLE) || (tx_state == STOP); + + always @(posedge clock) begin + TxD_data_r <= (ready & TxD_start) ? TxD_data : TxD_data_r; + end + + always @(posedge clock) begin + if (reset) tx_state <= IDLE; + else begin + case (tx_state) + IDLE: if (TxD_start) tx_state <= START; + START: if (uart_tick) tx_state <= BIT_0; + BIT_0: if (uart_tick) tx_state <= BIT_1; + BIT_1: if (uart_tick) tx_state <= BIT_2; + BIT_2: if (uart_tick) tx_state <= BIT_3; + BIT_3: if (uart_tick) tx_state <= BIT_4; + BIT_4: if (uart_tick) tx_state <= BIT_5; + BIT_5: if (uart_tick) tx_state <= BIT_6; + BIT_6: if (uart_tick) tx_state <= BIT_7; + BIT_7: if (uart_tick) tx_state <= STOP; + STOP: if (uart_tick) tx_state <= (TxD_start) ? START : IDLE; + default: tx_state <= 4'bxxxx; + endcase + end + end + + always @(tx_state, TxD_data_r) begin + case (tx_state) + IDLE: TxD <= 1; + START: TxD <= 0; + BIT_0: TxD <= TxD_data_r[0]; + BIT_1: TxD <= TxD_data_r[1]; + BIT_2: TxD <= TxD_data_r[2]; + BIT_3: TxD <= TxD_data_r[3]; + BIT_4: TxD <= TxD_data_r[4]; + BIT_5: TxD <= TxD_data_r[5]; + BIT_6: TxD <= TxD_data_r[6]; + BIT_7: TxD <= TxD_data_r[7]; + STOP: TxD <= 1; + default: TxD <= 1'bx; + endcase + end + +endmodule + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/LEGAL b/demo_chip_rtl/rtl/mips32r1/trunk/LEGAL new file mode 100755 index 0000000..65c5ca8 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/LEGAL @@ -0,0 +1,165 @@ + GNU LESSER GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + + This version of the GNU Lesser General Public License incorporates +the terms and conditions of version 3 of the GNU General Public +License, supplemented by the additional permissions listed below. + + 0. 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Combined Libraries. + + You may place library facilities that are a work based on the +Library side by side in a single library together with other library +facilities that are not Applications and are not covered by this +License, and convey such a combined library under terms of your +choice, if you do both of the following: + + a) Accompany the combined library with a copy of the same work based + on the Library, uncombined with any other library facilities, + conveyed under the terms of this License. + + b) Give prominent notice with the combined library that part of it + is a work based on the Library, and explaining where to find the + accompanying uncombined form of the same work. + + 6. Revised Versions of the GNU Lesser General Public License. + + The Free Software Foundation may publish revised and/or new versions +of the GNU Lesser General Public License from time to time. Such new +versions will be similar in spirit to the present version, but may +differ in detail to address new problems or concerns. + + Each version is given a distinguishing version number. If the +Library as you received it specifies that a certain numbered version +of the GNU Lesser General Public License "or any later version" +applies to it, you have the option of following the terms and +conditions either of that published version or of any later version +published by the Free Software Foundation. If the Library as you +received it does not specify a version number of the GNU Lesser +General Public License, you may choose any version of the GNU Lesser +General Public License ever published by the Free Software Foundation. + + If the Library as you received it specifies that a proxy can decide +whether future versions of the GNU Lesser General Public License shall +apply, that proxy's public statement of acceptance of any version is +permanent authorization for you to choose that version for the +Library. diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/README b/demo_chip_rtl/rtl/mips32r1/trunk/README new file mode 100755 index 0000000..9b78b25 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/README @@ -0,0 +1,47 @@ +XUM MIPS32-R1 Release - 14 Oct 2012 +----------------------------------- + +!!! Update January 1, 2014 +!!! This project has moved to GitHub. No updates will be committed +!!! to the OpenCores repository, and the repository itself may become +!!! unavailable at a later time. +!!! +!!! Please visit https://github.com/grantea/mips32r1 for the latest project. + + +This is an OpenCores release of the XUM MIPS32 processor +from release 2.0 of the XUM project at the University of Utah. + +This project provides all of the hardware and software needed to build +a MIPS32-compliant processor and several I/O peripherals all from scratch +and implement them on an FPGA. It contains a GCC- and binutils-based +cross-compiler toolchain to allow custom code to be compiled and run +on the hardware. + + +Directory Layout +---------------- + + Hardware: + -> MIPS32_Standalone: Processor HDL only. Top file is "Processor.v". + + -> XUPV5-LX110T_SoC: Full System-on-Chip for XUPV5 board and Xilinx ISE 14.1 + Project Navigator. Useful as a starting point for other + boards as well. See "HOWTO" in this directory for more + information. + + Software: + -> demos: Software demos for XUM + -> toolchain: Instructions for creating a MIPS crosscompiler toolchain + -> xum_bootloader: A C# implementation of the XUM bootloader. + + +Legal +----- + +All software and hardware included in this distribution is licensed under +the GNU LGPL. See the file 'LEGAL' in this same directory for more information. + + +Enjoy! + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/README b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/README new file mode 100755 index 0000000..ec1d740 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/README @@ -0,0 +1,4 @@ +Directory Contents +------------------ + util -> A set of utilities required to make XUM programs. + XD* -> XUM MIPS32 single-core demos diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD1_Hello/README b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD1_Hello/README new file mode 100755 index 0000000..390fa55 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD1_Hello/README @@ -0,0 +1,29 @@ +README for XUM Demo 1 : Hello +----------------------------- + +Creator: Grant Ayers (ayers@cs.utah.edu) +Date: 25 July 2012 + + + +DEMONSTRATES +------------ + +LCD screen, basic hardware functionality test. + + + +DESCRIPTION +----------- + +Prints the message "It works!" to the LCD screen. + + + +BUILDING AND RUNNING +-------------------- + +To compile, enter the 'bin' directory and update the paths in the Makefile. +Then run 'make' from within the same directory. Use the XUM bootloader to +send the resulting .xum file to the FPGA. + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD1_Hello/bin/Makefile b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD1_Hello/bin/Makefile new file mode 100755 index 0000000..282beeb --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD1_Hello/bin/Makefile @@ -0,0 +1,75 @@ +# Makefile for XUM +# +# Compiles code to run on the XUM platform, which +# is based on MIPS32 and a GCC cross-compiler toolchain. +# +# Author: Grant Ayers (ayers@cs.utah.edu) +# Date: 3 July 2012 +# + +SHELL = /bin/sh + +SRC = ../src +MIPS_PREFIX = /home/User/XUM/gnu_mips/crosstools +MIPS_BIN = $(MIPS_PREFIX)/bin +MIPS_LIB = $(MIPS_PREFIX)/mips-elf/lib +MIPS_CC = $(MIPS_BIN)/mips-elf-gcc-4.7.1.exe +MIPS_AS = $(MIPS_BIN)/mips-elf-as.exe +MIPS_LD = $(MIPS_BIN)/mips-elf-ld.exe +MIPS_OBJDUMP = $(MIPS_BIN)/mips-elf-objdump.exe +MIPS_OBJCOPY = $(MIPS_BIN)/mips-elf-objcopy.exe +UTIL_PREFIX = /home/User/XUM/demos/util +UTIL_CONVBIN = $(UTIL_PREFIX)/bintohex.exe +UTIL_CONVXUM = $(UTIL_PREFIX)/bintoxum.exe + +AS_FLAGS = -march=mips32 -EB -G0 +LD_FLAGS = -EB -static -Map app.map -T ../src/os/xum.ls +LD_LIBS = -lm -lc -lgcc +LD_SEARCH = -L$(MIPS_PREFIX)/mips-elf/lib \ + -L$(MIPS_PREFIX)/lib/gcc/mips-elf/4.7.1 +LD_DRIVER = $(MIPS_LD) $(LD_FLAGS) $(LD_SEARCH) $(LD_LIBS) +CC_FLAGS_ARCH = -march=mips32 -EB -msoft-float -mno-mips16 +CC_FLAGS_LANG = -Wall -O2 -mgpopt -mxgot -G0 +CC_FLAGS_INC = -I../src/ +CC_FLAGS_AS = -Wa,-EB,-mips32,-msoft-float +CC_FLAGS_LD = -nostdlib -nostartfiles -static -T ../src/os/xum.ls +CC_FLAGS_LIB = -lm -lc -lgcc +CC_DRIVER = $(MIPS_CC) $(CC_FLAGS_ARCH) $(CC_FLAGS_LANG) \ + $(CC_FLAGS_AS) $(CC_FLAGS_INC) + + +all : app + +app : app.o lcd.o boot.o vectors.o exceptions.o + $(LD_DRIVER) $^ -o app.exe + @$(MIPS_OBJDUMP) -EB --disassemble app.exe > app.lst + @$(MIPS_OBJCOPY) -O binary -j .text app.exe app-code.bin + @$(MIPS_OBJCOPY) -O binary -j .data app.exe app-data1.bin + @$(MIPS_OBJCOPY) -O binary -j .sdata app.exe app-data2.bin + @$(MIPS_OBJCOPY) -O binary -j .sbss app.exe app-data3.bin + @$(MIPS_OBJCOPY) -O binary -j .bss app.exe app-data4.bin + @cat app-data1.bin app-data2.bin app-data3.bin app-data4.bin >> app-data.bin + @$(UTIL_CONVXUM) -d 4096 app-code.bin app-data.bin app.xum + #@$(UTIL_CONVBIN) -c -b app-code.bin app-code.coe + $(UTIL_CONVBIN) -c -b app.xum app.coe + + + +app.o : $(SRC)/app/app.c + $(CC_DRIVER) -c $(SRC)/app/app.c -o app.o + +lcd.o : $(SRC)/drivers/lcd.c $(SRC)/drivers/lcd.h + $(CC_DRIVER) -c $(SRC)/drivers/lcd.c -o lcd.o + +boot.o : $(SRC)/os/boot.asm + $(MIPS_AS) $(AS_FLAGS) -o boot.o $(SRC)/os/boot.asm + +vectors.o : $(SRC)/os/vectors.asm + $(MIPS_AS) $(AS_FLAGS) -o vectors.o $(SRC)/os/vectors.asm + +exceptions.o : $(SRC)/os/exceptions.asm + $(MIPS_AS) $(AS_FLAGS) -o exceptions.o $(SRC)/os/exceptions.asm + +clean : + rm -f *.o *.exe *.map *.coe *.bin *.map *.xum *.lst + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD1_Hello/bin/app.xum b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD1_Hello/bin/app.xum new file mode 100755 index 0000000..8401473 Binary files /dev/null and b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD1_Hello/bin/app.xum differ diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD1_Hello/src/app/app.c b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD1_Hello/src/app/app.c new file mode 100755 index 0000000..00b98af --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD1_Hello/src/app/app.c @@ -0,0 +1,13 @@ +#include "drivers/lcd.h" + +char *message = "It works!"; + +int main(void) +{ + LCD_clear(); + LCD_setPos(19); + LCD_printString(message); + + return 0; +} + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD1_Hello/src/drivers/lcd.c b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD1_Hello/src/drivers/lcd.c new file mode 100755 index 0000000..a95b38a --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD1_Hello/src/drivers/lcd.c @@ -0,0 +1,142 @@ +#include "lcd.h" + +static uint8_t LCD_position = 0; +static uint8_t LCD_autoIncr = 1; + +static void LCD_incrPos(uint32_t amount) +{ + if (LCD_autoIncr == 0) { + return; + } + while (amount > 32) { + amount -= 32; + } + LCD_position += (uint8_t)amount; + if (LCD_position >= 32) { + LCD_position -= 32; + } +} + + +void LCD_clear(void) +{ + volatile uint32_t *LCD; + int i; + + LCD = (volatile uint32_t *)LCD_ADDRESS; + + for (i=0; i<8; i++) { + LCD[i] = 0x20202020; + } + LCD_position = 0; +} + +void LCD_setPos(uint8_t position) +{ + LCD_position = position; +} + +uint8_t LCD_getPos(void) +{ + return LCD_position; +} + +void LCD_setAutoIncr(uint8_t incr) +{ + LCD_autoIncr = incr; +} + +void LCD_printByte(uint8_t byte) +{ + volatile uint8_t *LCD; + + LCD = (volatile uint8_t *)(LCD_ADDRESS + LCD_position); + *LCD = byte; + LCD_incrPos(1); +} + +void LCD_printByteHex(uint8_t byte) +{ + volatile uint8_t *LCD; + uint8_t nibble_h, nibble_l; + + LCD = (volatile uint8_t *)(LCD_ADDRESS + LCD_position); + nibble_h = byte >> 4; + nibble_l = byte & 0x0f; + + if (nibble_h < 10) { + nibble_h += 48; + } + else { + nibble_h += 55; + } + if (nibble_l < 10) { + nibble_l += 48; + } + else { + nibble_h += 55; + } + *LCD = nibble_h; + LCD++; + *LCD = nibble_l; + LCD_incrPos(2); +} + +void LCD_printByteDec(uint8_t byte) +{ + volatile uint8_t *LCD; + uint8_t hundreds, tens, ones; + uint32_t n_printed = 1; + + LCD = (volatile uint8_t *)(LCD_ADDRESS + LCD_position); + hundreds = tens = ones = 48; + + while (byte >= 100) { + hundreds++; + byte -= 100; + } + while (byte >= 10) { + tens++; + byte -= 10; + } + while (byte >= 1) { + ones++; + byte -= 1; + } + if (hundreds > 48) { + *LCD = hundreds; + LCD++; + n_printed++; + } + if ((n_printed > 1) || (tens > 48)) { + *LCD = tens; + LCD++; + n_printed++; + } + *LCD = ones; + LCD_incrPos(n_printed); +} + +void LCD_printWord(uint32_t word) +{ + volatile uint32_t *LCD; + + LCD = (volatile uint32_t *)(LCD_ADDRESS + LCD_position); + *LCD = word; + LCD_incrPos(4); +} + +void LCD_printString(char *string) +{ + volatile char *LCD; + int i = 0; + + LCD = (volatile char *)(LCD_ADDRESS + LCD_position); + + while (string[i] != '\0') { + LCD[i] = string[i]; + i++; + } + LCD_incrPos(i); +} + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD1_Hello/src/drivers/lcd.h b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD1_Hello/src/drivers/lcd.h new file mode 100755 index 0000000..2ebcd14 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD1_Hello/src/drivers/lcd.h @@ -0,0 +1,19 @@ +#ifndef __LCD_H__ +#define __LCD_H__ + +#include + +#define LCD_ADDRESS 0x80000000 + +void LCD_clear(void); +void LCD_setPos(uint8_t position); +uint8_t LCD_getPos(void); +void LCD_setAutoIncr(uint8_t incr); +void LCD_printByte(uint8_t byte); +void LCD_printByteHex(uint8_t byte); +void LCD_printByteDec(uint8_t byte); +void LCD_printWord(uint32_t word); +void LCD_printString(char *string); + +#endif + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD1_Hello/src/os/boot.asm b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD1_Hello/src/os/boot.asm new file mode 100755 index 0000000..113490f --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD1_Hello/src/os/boot.asm @@ -0,0 +1,54 @@ +############################################################################### +# TITLE: Boot Up Code +# AUTHOR: Grant Ayers (ayers@cs.utah.edu) +# DATE: 19 July 2011 +# FILENAME: boot.asm +# PROJECT: University of Utah XUM Single Core +# DESCRIPTION: +# Initializes the global pointer and stack pointer. +# Zeros BSS memory region and jumps to main(). +# +############################################################################### + + + .text + .balign 4 + .global boot + .ent boot + .set noreorder +boot: + la $t0, _bss_start # Defined in linker script + la $t1, _bss_end + la $sp, _sp + la $gp, _gp + +$bss_clear: + beq $t0, $t1, $cp0_setup # Loop until BSS is cleared + nop + sb $0, 0($t0) + j $bss_clear + addiu $t0, $t0, 1 + +$cp0_setup: + la $26, $run + mtc0 $26, $30, 0 # ErrorEPC gets address of $run + mfc0 $26, $13, 0 # Load Cause register + lui $27, 0x0080 # Use "special" interrupt vector + or $26, $26, $27 + mtc0 $26, $13, 0 # Commit new Cause register + mfc0 $26, $12, 0 # Load Status register + lui $27, 0x0fff # Disable access to Coprocessors + ori $27, $27, 0x00ee # Disable all interrupts, + and $26, $26, $27 # and set kernel mode + mtc0 $26, $12, 0 # Commit new Status register + eret # Return from Reset Exception + +$run: + jal main + nop + +$done: + j $done + nop + .end boot + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD1_Hello/src/os/exceptions.asm b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD1_Hello/src/os/exceptions.asm new file mode 100755 index 0000000..f7774ff --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD1_Hello/src/os/exceptions.asm @@ -0,0 +1,23 @@ +############################################################################### +# TITLE: Exception Vectors +# AUTHOR: Grant Ayers (ayers@cs.utah.edu) +# DATE: 23 May 2012 +# FILENAME: exceptions.asm +# PROJECT: University of Utah XUM Single Core +# DESCRIPTION: +# Provides the exception vectors which jump to +# exception-handling routines. +# +############################################################################### + + .text + .balign 4 + .set noreorder + .global mips32_exception + .ent mips32_exception +mips32_exception: + j mips32_exception # Loop forever + nop + .end mips32_exception + + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD1_Hello/src/os/vectors.asm b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD1_Hello/src/os/vectors.asm new file mode 100755 index 0000000..e80b81c --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD1_Hello/src/os/vectors.asm @@ -0,0 +1,39 @@ +############################################################################### +# TITLE: Exception Vectors +# AUTHOR: Grant Ayers (ayers@cs.utah.edu) +# DATE: 23 May 2012 +# FILENAME: exceptions.asm +# PROJECT: University of Utah XUM Single Core +# DESCRIPTION: +# Provides the exception vectors which jump to +# exception-handling routines. +# +############################################################################### + + +# Current setup: +# 1. The exception vector begins at address 0x0. +# 2. The interrupt vector begins at address 0x8. +# 3. Each vector has room for 2 instructions (8 bytes) with which +# it must jump to its demultiplexing routine. The demultiplexing +# routine calls individual exception-specific handlers. +# 4. The linker script must ensure that this code is placed at the +# correct address. + + + .text + .balign 4 + .ent exception_vector + .set noreorder +exception_vector: + j mips32_exception + nop + .end exception_vector + + + .ent interrupt_vector +interrupt_vector: + j mips32_exception + nop + .end interrupt_vector + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD1_Hello/src/os/xum.ls b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD1_Hello/src/os/xum.ls new file mode 100755 index 0000000..ca9ea04 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD1_Hello/src/os/xum.ls @@ -0,0 +1,83 @@ +/* Linker script for MIPS32 (Single Core) FPGA, intended for XUM */ + + +/* Entry Point + * + * Set it to be the label "boot" (likely in boot.asm) + * + */ +/*ENTRY(boot)*/ + + +/* Memory Section + * + * The FPGA currently uses one region of Block RAM, which is 592 KB. + * + * Instruction Memory starts at address 0. + * + * Data Memory ends 592KB later, at address 0x00094000 (the last + * usable word address is 0x00093ffc). + * + * Instructions : 0x00000000 -> 0x0000fffc ( 64KB) + * Data / BSS : 0x00001000 -> 0x00017ffc ( 32KB) + * Stack / Heap : 0x00018000 -> 0x00093ffc (496KB) + * + * + */ + +/* Sections + * + */ + +SECTIONS +{ + _sp = 0x00094000; + + . = 0 ; + + .text : + { + vectors.o(.text) + . = 0x10 ; + boot.o(.text) + exceptions.o(.text) + *(.*text*) + } + + . = 0x00001000 ; + + .data : + { + *(.rodata*) + *(.data*) + } + + _gp = ALIGN(16) + 0x7ff0; + + .got : + { + *(.got) + } + + .sdata : + { + *(.*sdata*) + } + + _bss_start = . ; + + .sbss : + { + *(.*sbss) + } + + .bss : + { + *(.*bss) + } + + _bss_end = . ; + +} + + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/README b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/README new file mode 100755 index 0000000..f43b7c5 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/README @@ -0,0 +1,30 @@ +README for XUM Demo 2 : Timer Interrupt +--------------------------------------- + +Creator: Grant Ayers (ayers@cs.utah.edu) +Date: 26 July 2012 + + + +DEMONSTRATES +------------ + +Interrupts, LCD. + + + +DESCRIPTION +----------- + +Shows a timer interrupting the control flow of the main function, which +merely updates a location on the LCD screen as fast as possible. + + + +BUILDING AND RUNNING +-------------------- + +To compile, enter the 'bin' directory and update the paths in the Makefile. +Then run 'make' from within the same directory. Use the XUM bootloader to +send the resulting .xum file to the FPGA. + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/bin/Makefile b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/bin/Makefile new file mode 100755 index 0000000..19bfaee --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/bin/Makefile @@ -0,0 +1,87 @@ +# Makefile for XUM +# +# Compiles code to run on the XUM platform, which +# is based on MIPS32 and a GCC cross-compiler toolchain. +# +# Author: Grant Ayers (ayers@cs.utah.edu) +# Date: 3 July 2012 +# + +SHELL = /bin/sh + +SRC = ../src +MIPS_PREFIX = /home/User/XUM/gnu_mips/crosstools +MIPS_BIN = $(MIPS_PREFIX)/bin +MIPS_LIB = $(MIPS_PREFIX)/mips-elf/lib +MIPS_CC = $(MIPS_BIN)/mips-elf-gcc-4.7.1.exe +MIPS_AS = $(MIPS_BIN)/mips-elf-as.exe +MIPS_LD = $(MIPS_BIN)/mips-elf-ld.exe +MIPS_OBJDUMP = $(MIPS_BIN)/mips-elf-objdump.exe +MIPS_OBJCOPY = $(MIPS_BIN)/mips-elf-objcopy.exe +UTIL_PREFIX = /home/User/XUM/demos/util +UTIL_CONVBIN = $(UTIL_PREFIX)/bintohex.exe +UTIL_CONVXUM = $(UTIL_PREFIX)/bintoxum.exe + +AS_FLAGS = -march=mips32 -EB -G0 +LD_FLAGS = -EB -static -Map app.map -T ../src/os/xum.ls +LD_LIBS = -lm -lc -lgcc +LD_SEARCH = -L$(MIPS_PREFIX)/mips-elf/lib \ + -L$(MIPS_PREFIX)/lib/gcc/mips-elf/4.7.1 +LD_DRIVER = $(MIPS_LD) $(LD_FLAGS) $(LD_SEARCH) $(LD_LIBS) +CC_FLAGS_ARCH = -march=mips32 -EB -msoft-float -mno-mips16 +CC_FLAGS_LANG = -Wall -O2 -mgpopt -mxgot -G0 +CC_FLAGS_INC = -I../src/ +CC_FLAGS_AS = -Wa,-EB,-mips32,-msoft-float +CC_FLAGS_LD = -nostdlib -nostartfiles -static -T ../src/os/xum.ls +CC_FLAGS_LIB = -lm -lc -lgcc +CC_DRIVER = $(MIPS_CC) $(CC_FLAGS_ARCH) $(CC_FLAGS_LANG) \ + $(CC_FLAGS_AS) $(CC_FLAGS_INC) + + +all : app + +app : lcd.o app.o boot.o vectors.o exceptions.o exception_handler.o piezo.o + $(LD_DRIVER) $^ -o app.exe + @$(MIPS_OBJDUMP) -EB --disassemble app.exe > app.lst + @$(MIPS_OBJCOPY) -O binary -j .text app.exe app-code.bin + @$(MIPS_OBJCOPY) -O binary -j .data app.exe app-data1.bin + @$(MIPS_OBJCOPY) -O binary -j .sdata app.exe app-data2.bin + @$(MIPS_OBJCOPY) -O binary -j .sbss app.exe app-data3.bin + @$(MIPS_OBJCOPY) -O binary -j .bss app.exe app-data4.bin + @cat app-data1.bin app-data2.bin app-data3.bin app-data4.bin >> app-data.bin + @$(UTIL_CONVXUM) -d 4096 app-code.bin app-data.bin app.xum + #@$(UTIL_CONVBIN) -c -b app-code.bin app-code.coe + $(UTIL_CONVBIN) -c -b app.xum app.coe + + + +app.o : $(SRC)/app/app.c + $(CC_DRIVER) -c $(SRC)/app/app.c -o app.o + +i2c.o : $(SRC)/drivers/i2c.c $(SRC)/drivers/i2c.h + $(CC_DRIVER) -c $(SRC)/drivers/i2c.c -o i2c.o + +lcd.o : $(SRC)/drivers/lcd.c $(SRC)/drivers/lcd.h + $(CC_DRIVER) -c $(SRC)/drivers/lcd.c -o lcd.o + +monitor.o : $(SRC)/drivers/monitor.c $(SRC)/drivers/monitor.h i2c.o + $(CC_DRIVER) -c $(SRC)/drivers/monitor.c -o monitor.o + +piezo.o : $(SRC)/drivers/piezo.c $(SRC)/drivers/piezo.h + $(CC_DRIVER) -c $(SRC)/drivers/piezo.c -o piezo.o + +exception_handler.o : $(SRC)/os/exception_handler.c $(SRC)/os/exception_handler.h lcd.o piezo.o monitor.o + $(CC_DRIVER) -c $(SRC)/os/exception_handler.c -o exception_handler.o + +boot.o : $(SRC)/os/boot.asm + $(MIPS_AS) $(AS_FLAGS) -o boot.o $(SRC)/os/boot.asm + +vectors.o : $(SRC)/os/vectors.asm + $(MIPS_AS) $(AS_FLAGS) -o vectors.o $(SRC)/os/vectors.asm + +exceptions.o : $(SRC)/os/exceptions.asm + $(MIPS_AS) $(AS_FLAGS) -o exceptions.o $(SRC)/os/exceptions.asm + +clean : + rm -f *.o *.exe *.map *.coe *.bin *.map *.xum *.lst + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/bin/app.xum b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/bin/app.xum new file mode 100755 index 0000000..b288750 Binary files /dev/null and b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/bin/app.xum differ diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/app/app.c b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/app/app.c new file mode 100755 index 0000000..f9f0bda --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/app/app.c @@ -0,0 +1,28 @@ +#include "drivers/piezo.h" +#include "drivers/lcd.h" + + +char *str_int = "Interrupt\x7e"; +char *str_main = "Main\x7e"; + +int main(void) +{ + static volatile char disp = 0; + + Piezo_play(C5); + LCD_clear(); + LCD_setAutoIncr(0); + LCD_setPos(4); + LCD_printString(str_int); + LCD_setPos(25); + LCD_printString(str_main); + + while (1) { + LCD_setPos(31); + LCD_printByte(disp); + disp++; + } + + return 0; +} + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/drivers/i2c.c b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/drivers/i2c.c new file mode 100755 index 0000000..0d66526 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/drivers/i2c.c @@ -0,0 +1,50 @@ +#include "i2c.h" + +void I2C_clear(void) +{ + volatile uint32_t *i2c = (volatile uint32_t *)I2C_ADDRESS; + uint32_t cmd = (1 << 8); + + *i2c = cmd; +} + +void I2C_EnQ(uint8_t byte) +{ + volatile uint32_t *i2c = (volatile uint32_t *)I2C_ADDRESS; + + uint32_t cmd = (1 << 9) | (uint32_t)byte; + *i2c = cmd; +} + +void I2C_transmit(void) +{ + volatile uint32_t *i2c = (volatile uint32_t *)I2C_ADDRESS; + + uint32_t cmd = (1 << 10); + *i2c = cmd; +} + +void I2C_setReceive(uint8_t bytes) +{ + volatile uint32_t *i2c = (volatile uint32_t *)I2C_ADDRESS; + + uint32_t cmd = (1 << 12) | (uint32_t)bytes; + *i2c = cmd; +} + +void I2C_receive(void) +{ + volatile uint32_t *i2c = (volatile uint32_t *)I2C_ADDRESS; + + uint32_t cmd = (1 << 11); + *i2c = cmd; +} + +uint32_t I2C_DeQ(void) +{ + volatile uint32_t *i2c = (volatile uint32_t *)I2C_ADDRESS; + + uint32_t data = *i2c; + return data; +} + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/drivers/i2c.h b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/drivers/i2c.h new file mode 100755 index 0000000..eb06443 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/drivers/i2c.h @@ -0,0 +1,16 @@ +#ifndef __I2C_H__ +#define __I2C_H__ + +#include + +#define I2C_ADDRESS 0x90000000 + +void I2C_clear(void); +void I2C_EnQ(uint8_t byte); +void I2C_transmit(void); +void I2C_setReceive(uint8_t bytes); +void I2C_receive(void); +uint32_t I2C_DeQ(void); + +#endif + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/drivers/lcd.c b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/drivers/lcd.c new file mode 100755 index 0000000..a95b38a --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/drivers/lcd.c @@ -0,0 +1,142 @@ +#include "lcd.h" + +static uint8_t LCD_position = 0; +static uint8_t LCD_autoIncr = 1; + +static void LCD_incrPos(uint32_t amount) +{ + if (LCD_autoIncr == 0) { + return; + } + while (amount > 32) { + amount -= 32; + } + LCD_position += (uint8_t)amount; + if (LCD_position >= 32) { + LCD_position -= 32; + } +} + + +void LCD_clear(void) +{ + volatile uint32_t *LCD; + int i; + + LCD = (volatile uint32_t *)LCD_ADDRESS; + + for (i=0; i<8; i++) { + LCD[i] = 0x20202020; + } + LCD_position = 0; +} + +void LCD_setPos(uint8_t position) +{ + LCD_position = position; +} + +uint8_t LCD_getPos(void) +{ + return LCD_position; +} + +void LCD_setAutoIncr(uint8_t incr) +{ + LCD_autoIncr = incr; +} + +void LCD_printByte(uint8_t byte) +{ + volatile uint8_t *LCD; + + LCD = (volatile uint8_t *)(LCD_ADDRESS + LCD_position); + *LCD = byte; + LCD_incrPos(1); +} + +void LCD_printByteHex(uint8_t byte) +{ + volatile uint8_t *LCD; + uint8_t nibble_h, nibble_l; + + LCD = (volatile uint8_t *)(LCD_ADDRESS + LCD_position); + nibble_h = byte >> 4; + nibble_l = byte & 0x0f; + + if (nibble_h < 10) { + nibble_h += 48; + } + else { + nibble_h += 55; + } + if (nibble_l < 10) { + nibble_l += 48; + } + else { + nibble_h += 55; + } + *LCD = nibble_h; + LCD++; + *LCD = nibble_l; + LCD_incrPos(2); +} + +void LCD_printByteDec(uint8_t byte) +{ + volatile uint8_t *LCD; + uint8_t hundreds, tens, ones; + uint32_t n_printed = 1; + + LCD = (volatile uint8_t *)(LCD_ADDRESS + LCD_position); + hundreds = tens = ones = 48; + + while (byte >= 100) { + hundreds++; + byte -= 100; + } + while (byte >= 10) { + tens++; + byte -= 10; + } + while (byte >= 1) { + ones++; + byte -= 1; + } + if (hundreds > 48) { + *LCD = hundreds; + LCD++; + n_printed++; + } + if ((n_printed > 1) || (tens > 48)) { + *LCD = tens; + LCD++; + n_printed++; + } + *LCD = ones; + LCD_incrPos(n_printed); +} + +void LCD_printWord(uint32_t word) +{ + volatile uint32_t *LCD; + + LCD = (volatile uint32_t *)(LCD_ADDRESS + LCD_position); + *LCD = word; + LCD_incrPos(4); +} + +void LCD_printString(char *string) +{ + volatile char *LCD; + int i = 0; + + LCD = (volatile char *)(LCD_ADDRESS + LCD_position); + + while (string[i] != '\0') { + LCD[i] = string[i]; + i++; + } + LCD_incrPos(i); +} + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/drivers/lcd.h b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/drivers/lcd.h new file mode 100755 index 0000000..2ebcd14 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/drivers/lcd.h @@ -0,0 +1,19 @@ +#ifndef __LCD_H__ +#define __LCD_H__ + +#include + +#define LCD_ADDRESS 0x80000000 + +void LCD_clear(void); +void LCD_setPos(uint8_t position); +uint8_t LCD_getPos(void); +void LCD_setAutoIncr(uint8_t incr); +void LCD_printByte(uint8_t byte); +void LCD_printByteHex(uint8_t byte); +void LCD_printByteDec(uint8_t byte); +void LCD_printWord(uint32_t word); +void LCD_printString(char *string); + +#endif + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/drivers/monitor.c b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/drivers/monitor.c new file mode 100755 index 0000000..6509ac4 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/drivers/monitor.c @@ -0,0 +1,33 @@ +#include "monitor.h" + +void Monitor_start(void) +{ + I2C_clear(); + I2C_EnQ(MONITOR_BUS_ADDR); + I2C_EnQ(0x40); // Configuration Register 1 + I2C_EnQ(0x1); // Enable monitoring + I2C_transmit(); +} + + +// Node is 0->Remote 1, 1->Local, 2->Remote 2 +uint32_t Monitor_readTemp(int node) +{ + uint8_t reg = 0x25 + node; + uint32_t data; + + // Set the read register + I2C_clear(); + I2C_EnQ(MONITOR_BUS_ADDR); + I2C_EnQ(reg); + I2C_transmit(); + + // Receive the register + I2C_EnQ(MONITOR_BUS_ADDR); + I2C_setReceive(1); + I2C_receive(); + data = I2C_DeQ(); + + return data; +} + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/drivers/monitor.h b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/drivers/monitor.h new file mode 100755 index 0000000..9177ce0 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/drivers/monitor.h @@ -0,0 +1,13 @@ +#ifndef __MONITOR_H__ +#define __MONITOR_H__ + +#include "i2c.h" + +#define MONITOR_BUS_ADDR 0x2C + +void Monitor_start(void); +uint32_t Monitor_readTemp(int node); + + +#endif + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/drivers/piezo.c b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/drivers/piezo.c new file mode 100755 index 0000000..97ffe11 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/drivers/piezo.c @@ -0,0 +1,19 @@ +#include "piezo.h" + +void Piezo_set(uint32_t count, int enable) +{ + volatile uint32_t *Piezo = (volatile uint32_t *)PIEZO_ADDRESS; + + if (enable) { + *Piezo = count | 0x1000000; + } + else { + *Piezo = count & ~0x1000000; + } +} + +void Piezo_play(uint32_t note) +{ + Piezo_set(note, 1); +} + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/drivers/piezo.h b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/drivers/piezo.h new file mode 100755 index 0000000..b59b1d5 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/drivers/piezo.h @@ -0,0 +1,43 @@ +#ifndef __PIEZO_H__ +#define __PIEZO_H__ + +#include + +#define PIEZO_ADDRESS 0xA0000000 + +/* Following are defined for a 100 MHz Piezo driver */ +#define C0 3058104 +#define C1 1529052 + +#define C4 191110 +#define C4s 180388 +#define D4f C4s +#define D4 170264 +#define D4s 160705 +#define E4f D4s +#define E4 151685 +#define F4 143172 +#define F4s 135138 +#define G4f F4s +#define G4 127551 +#define G4s 120395 +#define A4f G4s +#define A4 113636 +#define A4s 107259 +#define B4f A4s +#define B4 101239 +#define C5 95557 +#define C5s 90192 +#define D5f C5s +#define D5 85131 +#define D5s 80354 +#define E5f D5s +#define E5 75843 + +#define C8 11945 + + +void Piezo_set(uint32_t count, int enable); +void Piezo_play(uint32_t note); + +#endif diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/os/boot.asm b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/os/boot.asm new file mode 100755 index 0000000..12f5218 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/os/boot.asm @@ -0,0 +1,70 @@ +############################################################################### +# TITLE: Boot Up Code +# AUTHOR: Grant Ayers (ayers@cs.utah.edu) +# DATE: 19 July 2011 +# FILENAME: boot.asm +# PROJECT: University of Utah XUM Single Core +# DESCRIPTION: +# Initializes the global pointer and stack pointer. +# Zeros BSS memory region and jumps to main(). +# +############################################################################### + + + .text + .balign 4 + .global boot + .ent boot + .set noreorder +boot: + la $t0, _bss_start # Defined in linker script + la $t1, _bss_end + la $sp, _sp + la $gp, _gp + +$bss_clear: + beq $t0, $t1, $cp0_setup # Loop until BSS is cleared + nop + sb $0, 0($t0) + j $bss_clear + addiu $t0, $t0, 1 + +$cp0_setup: + la $26, $run # Load the address of $run into + mtc0 $26, $30, 0 # the ErrorEPC + mfc0 $26, $13, 0 # Load Cause register + lui $27, 0x0080 # Use "special" interrupt vector + or $26, $26, $27 + mtc0 $26, $13, 0 # Commit new Cause register + mfc0 $26, $12, 0 # Load Status register + lui $27, 0x0fff # Disable access to Coprocessors, + ori $27, $27, 0xffef # Base operating mode is Kernel + and $26, $26, $27 + ori $27, $0, 0xff01 # Enable all interrupts + or $26, $26, $27 + mtc0 $26, $12, 0 # Commit new Status register + + #lui $26, 0x0000 # 1ms timer (50 MHz) + #ori $26, $26, 0xc350 + #lui $26, 0x0007 # 10ms timer (50 MHz) + #ori $26, $26, 0xa120 + #lui $26, 0x004c # 100ms timer (50 MHz) + #ori $26, $26, 0x4b40 + lui $26, 0x017d # 500ms timer (50 MHz) + ori $26, 0x7840 + #lui $26, 0x02fa # 1 sec timer (50 MHz) + #ori $26, $26, 0xf080 + mtc0 $26, $11, 0 # Set Compare register to timer value + + eret # Return from Reset Exception + +$run: + jal main + nop + +$done: + j $done + nop + + .end boot + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/os/exception_handler.c b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/os/exception_handler.c new file mode 100755 index 0000000..1a4614d --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/os/exception_handler.c @@ -0,0 +1,147 @@ +#include "drivers/lcd.h" +#include "drivers/piezo.h" + +void dead_loop(void) +{ + for (;;) {} +} + +void mips32_handler_AdEL(void) +{ + LCD_clear(); + LCD_printString("AdEL"); + dead_loop(); +} + +void mips32_handler_AdES(void) +{ + LCD_clear(); + LCD_printString("AdES"); + dead_loop(); +} + +void mips32_handler_Bp(void) +{ + LCD_clear(); + LCD_printString("Bp"); + dead_loop(); +} + +void mips32_handler_CpU(void) +{ + LCD_clear(); + LCD_printString("CpU"); + dead_loop(); +} + +void mips32_handler_Ov(void) +{ + LCD_clear(); + LCD_printString("Ov"); + dead_loop(); +} + +void mips32_handler_RI(void) +{ + LCD_clear(); + LCD_printString("RI"); + dead_loop(); +} + +void mips32_handler_Sys(void) +{ + LCD_clear(); + LCD_printString("Sys"); + dead_loop(); +} + +void mips32_handler_Tr(void) +{ + LCD_clear(); + LCD_printString("Trap"); + dead_loop(); +} + +/* Timer */ +void mips32_handler_HwInt5(void) +{ + static volatile char blink = 0; + static volatile char wait = 0; + + if (blink == 0) { + blink++; + LCD_setPos(15); + LCD_printByte(' '); + } + else { + blink--; + LCD_setPos(15); + LCD_printByte('.'); + } + + if (wait == 1) { + wait++; + Piezo_set(0, 0); + } + else if (wait < 1) { + wait++; + } +} + +void mips32_handler_HwInt4(void) +{ + static volatile char count = 0; + + LCD_printByte(count); + count++; +} + +void mips32_handler_HwInt3(void) +{ + static volatile char count = 0; + + LCD_printByte(count); + count++; +} + +void mips32_handler_HwInt2(void) +{ + static volatile char count = 0; + + LCD_printByte(count); + count++; +} + +void mips32_handler_HwInt1(void) +{ + static volatile char count = 0; + + LCD_printByte(count); + count++; +} + + +void mips32_handler_HwInt0(void) +{ + static volatile char count = 0; + + LCD_printByte(count); + count++; +} + +void mips32_handler_SwInt1(void) +{ + static volatile char count = 0; + + LCD_printByte(count); + count++; +} + +void mips32_handler_SwInt0(void) +{ + static volatile char count = 0; + + LCD_printByte(count); + count++; +} + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/os/exception_handler.h b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/os/exception_handler.h new file mode 100755 index 0000000..01502fe --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/os/exception_handler.h @@ -0,0 +1,25 @@ +#ifndef __exception_handler_h__ +#define __exception_handler_h__ + +/* MIPS32 Exception Handlers */ +void mips32_handler_AdEL(void); +void mips32_handler_AdES(void); +void mips32_handler_Bp(void); +void mips32_handler_CpU(void); +void mips32_handler_Ov(void); +void mips32_handler_RI(void); +void mips32_handler_Sys(void); +void mips32_handler_Tr(void); + +/* MIPS32 Interrupt Handlers */ +void mips32_handler_HwInt5(void); +void mips32_handler_HwInt4(void); +void mips32_handler_HwInt3(void); +void mips32_handler_HwInt2(void); +void mips32_handler_HwInt1(void); +void mips32_handler_HwInt0(void); +void mips32_handler_SwInt1(void); +void mips32_handler_SwInt0(void); + +#endif + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/os/exceptions.asm b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/os/exceptions.asm new file mode 100755 index 0000000..2796004 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/os/exceptions.asm @@ -0,0 +1,168 @@ +############################################################################### +# TITLE: Exception Vectors +# AUTHOR: Grant Ayers (ayers@cs.utah.edu) +# DATE: 23 May 2012 +# FILENAME: exceptions.asm +# PROJECT: University of Utah XUM Single Core +# DESCRIPTION: +# Provides the exception vectors which jump to +# exception-handling routines. +# +############################################################################### + + .text + .balign 4 + .set noreorder + .set noat + +exc_save: + # Save all registers except k0 k1 sp ra + addiu $sp, $sp, -112 + sw $1, 0($sp) + sw $2, 4($sp) + sw $3, 8($sp) + sw $4, 12($sp) + sw $5, 16($sp) + sw $6, 20($sp) + sw $7, 24($sp) + sw $8, 28($sp) + sw $9, 32($sp) + sw $10, 36($sp) + sw $11, 40($sp) + sw $12, 44($sp) + sw $13, 48($sp) + sw $14, 52($sp) + sw $15, 56($sp) + sw $16, 60($sp) + sw $17, 64($sp) + sw $18, 68($sp) + sw $19, 72($sp) + sw $20, 76($sp) + sw $21, 80($sp) + sw $22, 84($sp) + sw $23, 88($sp) + sw $24, 92($sp) + sw $25, 96($sp) + sw $28, 100($sp) + jr $ra + sw $30, 104($sp) + +exc_restore: + # Restore all registers except k0 k1 sp ra + lw $1, 0($sp) + lw $2, 4($sp) + lw $3, 8($sp) + lw $4, 12($sp) + lw $5, 16($sp) + lw $6, 20($sp) + lw $7, 24($sp) + lw $8, 28($sp) + lw $9, 32($sp) + lw $10, 36($sp) + lw $11, 40($sp) + lw $12, 44($sp) + lw $13, 48($sp) + lw $14, 52($sp) + lw $15, 56($sp) + lw $16, 60($sp) + lw $17, 64($sp) + lw $18, 68($sp) + lw $19, 72($sp) + lw $20, 76($sp) + lw $21, 80($sp) + lw $22, 84($sp) + lw $23, 88($sp) + lw $24, 92($sp) + lw $25, 96($sp) + lw $28, 100($sp) + lw $30, 104($sp) + jr $ra + addiu $sp, $sp, 112 + + + .global mips32_general_exception + .ent mips32_general_exception +mips32_general_exception: + or $26, $0, $ra + jal exc_save + nop + mfc0 $27, $13, 0 # Read Cause which has ExcCode bits + srl $27, $27, 2 # Extract exception code to $k1 + andi $27, $27, 0x001f + + la $ra, $end_exception # Jump to the appropriate handler + addiu $t0, $0, 4 + addiu $t1, $0, 5 + addiu $t2, $0, 8 + addiu $t3, $0, 9 + beq $t0, $27, mips32_handler_AdEL + addiu $t0, $0, 10 + beq $t1, $27, mips32_handler_AdES + addiu $t1, $0, 11 + beq $t2, $27, mips32_handler_Sys + addiu $t2, $0, 12 + beq $t3, $27, mips32_handler_Bp + addiu $t3, $0, 13 + beq $t0, $27, mips32_handler_RI + nop + beq $t1, $27, mips32_handler_CpU + nop + beq $t2, $27, mips32_handler_Ov + nop + beq $t3, $27, mips32_handler_Tr + nop + +$end_exception: + jal exc_restore + xor $27, $0, $0 + or $ra, $0, $26 + xor $26, $0, $0 + eret + .end mips32_general_exception + + + +### "Special" Interrupt Vector: Cause_IV must be set. + + .ent mips32_interrupt_exception + .global mips32_interrupt_exception +mips32_interrupt_exception: + mfc0 $26, $12, 0 # Status register for IM bits + mfc0 $27, $13, 0 # Cause register for IP bits + and $26, $26, $27 # Extract pending, unmasked interrupts + srl $26, $26, 8 + andi $26, $26, 0x00ff + + addu $27, $0, $ra + jal exc_save + clz $26, $26 + la $ra, $end_interrupt # All C functions will return here + addiu $t0, $0, 24 + addiu $t1, $0, 25 + addiu $t2, $0, 26 + beq $26, $t0, mips32_handler_HwInt5 + addiu $t0, $0, 27 + beq $26, $t1, mips32_handler_HwInt4 + addiu $t1, $0, 28 + beq $26, $t2, mips32_handler_HwInt3 + addiu $t2, $0, 29 + beq $26, $t0, mips32_handler_HwInt2 + addiu $t0, $0, 30 + beq $26, $t1, mips32_handler_HwInt1 + addiu $t1, $0, 31 + beq $26, $t2, mips32_handler_HwInt0 + nop + beq $26, $t0, mips32_handler_SwInt1 + nop + beq $26, $t1, mips32_handler_SwInt0 + nop + + +$end_interrupt: + jal exc_restore + mfc0 $26, $9, 0 # Clear HwInt5 if applicable + or $ra, $0, $27 + eret + .end mips32_interrupt_exception + + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/os/vectors.asm b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/os/vectors.asm new file mode 100755 index 0000000..dd455bc --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/os/vectors.asm @@ -0,0 +1,39 @@ +############################################################################### +# TITLE: Exception Vectors +# AUTHOR: Grant Ayers (ayers@cs.utah.edu) +# DATE: 23 May 2012 +# FILENAME: exceptions.asm +# PROJECT: University of Utah XUM Single Core +# DESCRIPTION: +# Provides the exception vectors which jump to +# exception-handling routines. +# +############################################################################### + + +# Current setup: +# 1. The exception vector begins at address 0x0. +# 2. The interrupt vector begins at address 0x8. +# 3. Each vector has room for 2 instructions (8 bytes) with which +# it must jump to its demultiplexing routine. The demultiplexing +# routine calls individual exception-specific handlers. +# 4. The linker script must ensure that this code is placed at the +# correct address. + + + .text + .balign 4 + .ent exception_vector + .set noreorder +exception_vector: + j mips32_general_exception + nop + .end exception_vector + + + .ent interrupt_vector +interrupt_vector: + j mips32_interrupt_exception + nop + .end interrupt_vector + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/os/xum.ls b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/os/xum.ls new file mode 100755 index 0000000..ca9ea04 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD2_Timer/src/os/xum.ls @@ -0,0 +1,83 @@ +/* Linker script for MIPS32 (Single Core) FPGA, intended for XUM */ + + +/* Entry Point + * + * Set it to be the label "boot" (likely in boot.asm) + * + */ +/*ENTRY(boot)*/ + + +/* Memory Section + * + * The FPGA currently uses one region of Block RAM, which is 592 KB. + * + * Instruction Memory starts at address 0. + * + * Data Memory ends 592KB later, at address 0x00094000 (the last + * usable word address is 0x00093ffc). + * + * Instructions : 0x00000000 -> 0x0000fffc ( 64KB) + * Data / BSS : 0x00001000 -> 0x00017ffc ( 32KB) + * Stack / Heap : 0x00018000 -> 0x00093ffc (496KB) + * + * + */ + +/* Sections + * + */ + +SECTIONS +{ + _sp = 0x00094000; + + . = 0 ; + + .text : + { + vectors.o(.text) + . = 0x10 ; + boot.o(.text) + exceptions.o(.text) + *(.*text*) + } + + . = 0x00001000 ; + + .data : + { + *(.rodata*) + *(.data*) + } + + _gp = ALIGN(16) + 0x7ff0; + + .got : + { + *(.got) + } + + .sdata : + { + *(.*sdata*) + } + + _bss_start = . ; + + .sbss : + { + *(.*sbss) + } + + .bss : + { + *(.*bss) + } + + _bss_end = . ; + +} + + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/README b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/README new file mode 100755 index 0000000..cba91b8 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/README @@ -0,0 +1,30 @@ +README for XUM Demo 3 : I2C +--------------------------- + +Creator: Grant Ayers (ayers@cs.utah.edu) +Date: 26 July 2012 + + + +DEMONSTRATES +------------ + +I2C bus, LCD. + + + +DESCRIPTION +----------- + +Uses the I2C main bus on the XUPV5 FPGA to read and display the temperature +from the onboard hardware monitor chip and from the FPGA. + + + +BUILDING AND RUNNING +-------------------- + +To compile, enter the 'bin' directory and update the paths in the Makefile. +Then run 'make' from within the same directory. Use the XUM bootloader to +send the resulting .xum file to the FPGA. + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/bin/Makefile b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/bin/Makefile new file mode 100755 index 0000000..36cf497 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/bin/Makefile @@ -0,0 +1,91 @@ +# Makefile for XUM +# +# Compiles code to run on the XUM platform, which +# is based on MIPS32 and a GCC cross-compiler toolchain. +# +# Author: Grant Ayers (ayers@cs.utah.edu) +# Date: 3 July 2012 +# + +SHELL = /bin/sh + +SRC = ../src +MIPS_PREFIX = /home/User/XUM/gnu_mips/crosstools +MIPS_BIN = $(MIPS_PREFIX)/bin +MIPS_LIB = $(MIPS_PREFIX)/mips-elf/lib +MIPS_CC = $(MIPS_BIN)/mips-elf-gcc-4.7.1.exe +MIPS_AS = $(MIPS_BIN)/mips-elf-as.exe +MIPS_LD = $(MIPS_BIN)/mips-elf-ld.exe +MIPS_OBJDUMP = $(MIPS_BIN)/mips-elf-objdump.exe +MIPS_OBJCOPY = $(MIPS_BIN)/mips-elf-objcopy.exe +UTIL_PREFIX = /home/User/XUM/demos/util +UTIL_CONVBIN = $(UTIL_PREFIX)/bintohex.exe +UTIL_CONVXUM = $(UTIL_PREFIX)/bintoxum.exe + +AS_FLAGS = -march=mips32 -EB -G0 +LD_FLAGS = -EB -static -Map app.map -T ../src/os/xum.ls +LD_LIBS = -lm -lc -lgcc +LD_SEARCH = -L$(MIPS_PREFIX)/mips-elf/lib \ + -L$(MIPS_PREFIX)/lib/gcc/mips-elf/4.7.1 +LD_DRIVER = $(MIPS_LD) $(LD_FLAGS) $(LD_SEARCH) $(LD_LIBS) +CC_FLAGS_ARCH = -march=mips32 -EB -msoft-float -mno-mips16 -mno-branch-likely \ + -mgpopt +CC_FLAGS_LANG = -Wall -O2 +CC_FLAGS_INC = -I../src/ +CC_FLAGS_AS = -Wa,-EB,-mips32,-msoft-float +CC_FLAGS_LD = -nostdlib -nostartfiles -static -T ../src/os/xum.ls +CC_FLAGS_LIB = -lm -lc -lgcc +CC_DRIVER = $(MIPS_CC) $(CC_FLAGS_ARCH) $(CC_FLAGS_LANG) \ + $(CC_FLAGS_AS) $(CC_FLAGS_INC) + + +all : app + +app : app.o monitor.o i2c.o lcd.o boot.o vectors.o exceptions.o exception_handler.o piezo.o + $(LD_DRIVER) $^ -o app.exe + @$(MIPS_OBJDUMP) -EB --disassemble app.exe > app.lst + @$(MIPS_OBJCOPY) -O binary -j .text app.exe app-code.bin + @$(MIPS_OBJCOPY) -O binary -j .data app.exe app-data1.bin + @$(MIPS_OBJCOPY) -O binary -j .sdata app.exe app-data2.bin + @$(MIPS_OBJCOPY) -O binary -j .sbss app.exe app-data3.bin + @$(MIPS_OBJCOPY) -O binary -j .bss app.exe app-data4.bin + @cat app-data1.bin app-data2.bin app-data3.bin app-data4.bin >> app-data.bin + @$(UTIL_CONVXUM) -d 4096 app-code.bin app-data.bin app.xum + #@$(UTIL_CONVBIN) -c -b app-code.bin app-code.coe + $(UTIL_CONVBIN) -c -b app.xum app.coe + + + +app.o : $(SRC)/app/app.c + $(CC_DRIVER) -c $(SRC)/app/app.c -o app.o + +uart.o : $(SRC)/drivers/uart.c $(SRC)/drivers/uart.h + $(CC_DRIVER) -c $(SRC)/drivers/uart.c -o uart.o + +i2c.o : $(SRC)/drivers/i2c.c $(SRC)/drivers/i2c.h + $(CC_DRIVER) -c $(SRC)/drivers/i2c.c -o i2c.o + +lcd.o : $(SRC)/drivers/lcd.c $(SRC)/drivers/lcd.h + $(CC_DRIVER) -c $(SRC)/drivers/lcd.c -o lcd.o + +monitor.o : $(SRC)/drivers/monitor.c $(SRC)/drivers/monitor.h i2c.o + $(CC_DRIVER) -c $(SRC)/drivers/monitor.c -o monitor.o + +piezo.o : $(SRC)/drivers/piezo.c $(SRC)/drivers/piezo.h + $(CC_DRIVER) -c $(SRC)/drivers/piezo.c -o piezo.o + +exception_handler.o : $(SRC)/os/exception_handler.c $(SRC)/os/exception_handler.h lcd.o piezo.o monitor.o + $(CC_DRIVER) -c $(SRC)/os/exception_handler.c -o exception_handler.o + +boot.o : $(SRC)/os/boot.asm + $(MIPS_AS) $(AS_FLAGS) -o boot.o $(SRC)/os/boot.asm + +vectors.o : $(SRC)/os/vectors.asm + $(MIPS_AS) $(AS_FLAGS) -o vectors.o $(SRC)/os/vectors.asm + +exceptions.o : $(SRC)/os/exceptions.asm + $(MIPS_AS) $(AS_FLAGS) -o exceptions.o $(SRC)/os/exceptions.asm + +clean : + rm -f *.o *.exe *.map *.coe *.bin *.map *.xum *.lst + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/bin/app.xum b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/bin/app.xum new file mode 100755 index 0000000..6f54ca0 Binary files /dev/null and b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/bin/app.xum differ diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/app/app.c b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/app/app.c new file mode 100755 index 0000000..2196921 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/app/app.c @@ -0,0 +1,39 @@ +#include "drivers/piezo.h" +#include "drivers/lcd.h" +#include "drivers/monitor.h" + +int main(void) +{ + static volatile char count = 0; + uint32_t temperature; + + Piezo_play(C5); + Monitor_start(); + LCD_clear(); + LCD_setPos(16); + LCD_printString("Temp:"); + + while (1) { + // Get Monitor temperature + temperature = Monitor_readTemp(1); + LCD_setPos(22); + LCD_printByteDec((uint8_t)temperature); + LCD_printByte('/'); + + // Get CPU temperature + temperature = Monitor_readTemp(0); + LCD_printByteDec((uint8_t)temperature); + LCD_printByte(0xdf); // degree symbol + LCD_printByte('C'); + LCD_printByte(' '); + LCD_printByte(' '); + + // Display a rolling value so we know we're alive + LCD_setPos(31); + LCD_printByte(count); + count++; + } + + return 0; +} + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/drivers/del.c b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/drivers/del.c new file mode 100755 index 0000000..85e913d --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/drivers/del.c @@ -0,0 +1,17 @@ +#include + +int foo(int a, int b) +{ + return (a+b); +} + +int foo(int a) +{ + return a*2; +} + +int main() +{ + return foo(2); +} + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/drivers/i2c.c b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/drivers/i2c.c new file mode 100755 index 0000000..0d66526 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/drivers/i2c.c @@ -0,0 +1,50 @@ +#include "i2c.h" + +void I2C_clear(void) +{ + volatile uint32_t *i2c = (volatile uint32_t *)I2C_ADDRESS; + uint32_t cmd = (1 << 8); + + *i2c = cmd; +} + +void I2C_EnQ(uint8_t byte) +{ + volatile uint32_t *i2c = (volatile uint32_t *)I2C_ADDRESS; + + uint32_t cmd = (1 << 9) | (uint32_t)byte; + *i2c = cmd; +} + +void I2C_transmit(void) +{ + volatile uint32_t *i2c = (volatile uint32_t *)I2C_ADDRESS; + + uint32_t cmd = (1 << 10); + *i2c = cmd; +} + +void I2C_setReceive(uint8_t bytes) +{ + volatile uint32_t *i2c = (volatile uint32_t *)I2C_ADDRESS; + + uint32_t cmd = (1 << 12) | (uint32_t)bytes; + *i2c = cmd; +} + +void I2C_receive(void) +{ + volatile uint32_t *i2c = (volatile uint32_t *)I2C_ADDRESS; + + uint32_t cmd = (1 << 11); + *i2c = cmd; +} + +uint32_t I2C_DeQ(void) +{ + volatile uint32_t *i2c = (volatile uint32_t *)I2C_ADDRESS; + + uint32_t data = *i2c; + return data; +} + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/drivers/i2c.h b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/drivers/i2c.h new file mode 100755 index 0000000..eb06443 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/drivers/i2c.h @@ -0,0 +1,16 @@ +#ifndef __I2C_H__ +#define __I2C_H__ + +#include + +#define I2C_ADDRESS 0x90000000 + +void I2C_clear(void); +void I2C_EnQ(uint8_t byte); +void I2C_transmit(void); +void I2C_setReceive(uint8_t bytes); +void I2C_receive(void); +uint32_t I2C_DeQ(void); + +#endif + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/drivers/lcd.c b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/drivers/lcd.c new file mode 100755 index 0000000..a95b38a --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/drivers/lcd.c @@ -0,0 +1,142 @@ +#include "lcd.h" + +static uint8_t LCD_position = 0; +static uint8_t LCD_autoIncr = 1; + +static void LCD_incrPos(uint32_t amount) +{ + if (LCD_autoIncr == 0) { + return; + } + while (amount > 32) { + amount -= 32; + } + LCD_position += (uint8_t)amount; + if (LCD_position >= 32) { + LCD_position -= 32; + } +} + + +void LCD_clear(void) +{ + volatile uint32_t *LCD; + int i; + + LCD = (volatile uint32_t *)LCD_ADDRESS; + + for (i=0; i<8; i++) { + LCD[i] = 0x20202020; + } + LCD_position = 0; +} + +void LCD_setPos(uint8_t position) +{ + LCD_position = position; +} + +uint8_t LCD_getPos(void) +{ + return LCD_position; +} + +void LCD_setAutoIncr(uint8_t incr) +{ + LCD_autoIncr = incr; +} + +void LCD_printByte(uint8_t byte) +{ + volatile uint8_t *LCD; + + LCD = (volatile uint8_t *)(LCD_ADDRESS + LCD_position); + *LCD = byte; + LCD_incrPos(1); +} + +void LCD_printByteHex(uint8_t byte) +{ + volatile uint8_t *LCD; + uint8_t nibble_h, nibble_l; + + LCD = (volatile uint8_t *)(LCD_ADDRESS + LCD_position); + nibble_h = byte >> 4; + nibble_l = byte & 0x0f; + + if (nibble_h < 10) { + nibble_h += 48; + } + else { + nibble_h += 55; + } + if (nibble_l < 10) { + nibble_l += 48; + } + else { + nibble_h += 55; + } + *LCD = nibble_h; + LCD++; + *LCD = nibble_l; + LCD_incrPos(2); +} + +void LCD_printByteDec(uint8_t byte) +{ + volatile uint8_t *LCD; + uint8_t hundreds, tens, ones; + uint32_t n_printed = 1; + + LCD = (volatile uint8_t *)(LCD_ADDRESS + LCD_position); + hundreds = tens = ones = 48; + + while (byte >= 100) { + hundreds++; + byte -= 100; + } + while (byte >= 10) { + tens++; + byte -= 10; + } + while (byte >= 1) { + ones++; + byte -= 1; + } + if (hundreds > 48) { + *LCD = hundreds; + LCD++; + n_printed++; + } + if ((n_printed > 1) || (tens > 48)) { + *LCD = tens; + LCD++; + n_printed++; + } + *LCD = ones; + LCD_incrPos(n_printed); +} + +void LCD_printWord(uint32_t word) +{ + volatile uint32_t *LCD; + + LCD = (volatile uint32_t *)(LCD_ADDRESS + LCD_position); + *LCD = word; + LCD_incrPos(4); +} + +void LCD_printString(char *string) +{ + volatile char *LCD; + int i = 0; + + LCD = (volatile char *)(LCD_ADDRESS + LCD_position); + + while (string[i] != '\0') { + LCD[i] = string[i]; + i++; + } + LCD_incrPos(i); +} + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/drivers/lcd.h b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/drivers/lcd.h new file mode 100755 index 0000000..2ebcd14 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/drivers/lcd.h @@ -0,0 +1,19 @@ +#ifndef __LCD_H__ +#define __LCD_H__ + +#include + +#define LCD_ADDRESS 0x80000000 + +void LCD_clear(void); +void LCD_setPos(uint8_t position); +uint8_t LCD_getPos(void); +void LCD_setAutoIncr(uint8_t incr); +void LCD_printByte(uint8_t byte); +void LCD_printByteHex(uint8_t byte); +void LCD_printByteDec(uint8_t byte); +void LCD_printWord(uint32_t word); +void LCD_printString(char *string); + +#endif + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/drivers/monitor.c b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/drivers/monitor.c new file mode 100755 index 0000000..6509ac4 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/drivers/monitor.c @@ -0,0 +1,33 @@ +#include "monitor.h" + +void Monitor_start(void) +{ + I2C_clear(); + I2C_EnQ(MONITOR_BUS_ADDR); + I2C_EnQ(0x40); // Configuration Register 1 + I2C_EnQ(0x1); // Enable monitoring + I2C_transmit(); +} + + +// Node is 0->Remote 1, 1->Local, 2->Remote 2 +uint32_t Monitor_readTemp(int node) +{ + uint8_t reg = 0x25 + node; + uint32_t data; + + // Set the read register + I2C_clear(); + I2C_EnQ(MONITOR_BUS_ADDR); + I2C_EnQ(reg); + I2C_transmit(); + + // Receive the register + I2C_EnQ(MONITOR_BUS_ADDR); + I2C_setReceive(1); + I2C_receive(); + data = I2C_DeQ(); + + return data; +} + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/drivers/monitor.h b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/drivers/monitor.h new file mode 100755 index 0000000..9177ce0 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/drivers/monitor.h @@ -0,0 +1,13 @@ +#ifndef __MONITOR_H__ +#define __MONITOR_H__ + +#include "i2c.h" + +#define MONITOR_BUS_ADDR 0x2C + +void Monitor_start(void); +uint32_t Monitor_readTemp(int node); + + +#endif + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/drivers/piezo.c b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/drivers/piezo.c new file mode 100755 index 0000000..97ffe11 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/drivers/piezo.c @@ -0,0 +1,19 @@ +#include "piezo.h" + +void Piezo_set(uint32_t count, int enable) +{ + volatile uint32_t *Piezo = (volatile uint32_t *)PIEZO_ADDRESS; + + if (enable) { + *Piezo = count | 0x1000000; + } + else { + *Piezo = count & ~0x1000000; + } +} + +void Piezo_play(uint32_t note) +{ + Piezo_set(note, 1); +} + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/drivers/piezo.h b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/drivers/piezo.h new file mode 100755 index 0000000..b59b1d5 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/drivers/piezo.h @@ -0,0 +1,43 @@ +#ifndef __PIEZO_H__ +#define __PIEZO_H__ + +#include + +#define PIEZO_ADDRESS 0xA0000000 + +/* Following are defined for a 100 MHz Piezo driver */ +#define C0 3058104 +#define C1 1529052 + +#define C4 191110 +#define C4s 180388 +#define D4f C4s +#define D4 170264 +#define D4s 160705 +#define E4f D4s +#define E4 151685 +#define F4 143172 +#define F4s 135138 +#define G4f F4s +#define G4 127551 +#define G4s 120395 +#define A4f G4s +#define A4 113636 +#define A4s 107259 +#define B4f A4s +#define B4 101239 +#define C5 95557 +#define C5s 90192 +#define D5f C5s +#define D5 85131 +#define D5s 80354 +#define E5f D5s +#define E5 75843 + +#define C8 11945 + + +void Piezo_set(uint32_t count, int enable); +void Piezo_play(uint32_t note); + +#endif diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/drivers/uart.c b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/drivers/uart.c new file mode 100755 index 0000000..3437c61 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/drivers/uart.c @@ -0,0 +1,38 @@ +#include "uart.h" + +void UART_disableBoot(void) +{ + volatile uint32_t *uart = (volatile uint32_t *)UART_ADDRESS; + uint32_t data; + + data = 0x00000100; + + *uart = data; +} + +uint8_t UART_readByte(void) +{ + volatile uint32_t *uart = (volatile uint32_t *)UART_ADDRESS; + uint32_t data; + + data = *uart; + + return (uint8_t)data; +} + +uint32_t UART_readMessage(void) +{ + volatile uint32_t *uart = (volatile uint32_t *)UART_ADDRESS; + + return *uart; +} + +void UART_writeByte(uint8_t byte) +{ + volatile uint32_t *uart = (volatile uint32_t *)UART_ADDRESS; + uint32_t data; + + data = (uint32_t)byte; + *uart = data; +} + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/drivers/uart.h b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/drivers/uart.h new file mode 100755 index 0000000..cf48a09 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/drivers/uart.h @@ -0,0 +1,14 @@ +#ifndef __UART_H__ +#define __UART_H__ + +#include + +#define UART_ADDRESS 0xB0000000 + +void UART_disableBoot(void); +uint8_t UART_readByte(void); +uint32_t UART_readMessage(void); +void UART_writeByte(uint8_t byte); + +#endif + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/os/boot.asm b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/os/boot.asm new file mode 100755 index 0000000..2cd243a --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/os/boot.asm @@ -0,0 +1,72 @@ +############################################################################### +# TITLE: Boot Up Code +# AUTHOR: Grant Ayers (ayers@cs.utah.edu) +# DATE: 19 July 2011 +# FILENAME: boot.asm +# PROJECT: University of Utah XUM Single Core +# DESCRIPTION: +# Initializes the global pointer and stack pointer. +# Zeros BSS memory region and jumps to main(). +# +############################################################################### + + + .text + .balign 4 + .global boot + .ent boot + .set noreorder +boot: + la $t0, _bss_start # Defined in linker script + la $t1, _bss_end + la $sp, _sp + la $gp, _gp + +$bss_clear: + beq $t0, $t1, $cp0_setup # Loop until BSS is cleared + nop + sb $0, 0($t0) + j $bss_clear + addiu $t0, $t0, 1 + +$cp0_setup: + la $26, $run # Load the address of $run into + mtc0 $26, $30, 0 # the ErrorEPC + mfc0 $26, $13, 0 # Load Cause register + lui $27, 0x0080 # Use "special" interrupt vector + or $26, $26, $27 + mtc0 $26, $13, 0 # Commit new Cause register + mfc0 $26, $12, 0 # Load Status register + lui $27, 0x0fff # Disable access to Coprocessors, + ori $27, $27, 0xffef # Base operating mode is Kernel + and $26, $26, $27 + ori $27, $0, 0xff01 # Enable all interrupts + or $26, $26, $27 + mtc0 $26, $12, 0 # Commit new Status register + + #lui $26, 0x0000 # 1ms timer (50 MHz) + #ori $26, $26, 0xc350 + #lui $26, 0x0007 # 10ms timer (50 MHz) + #ori $26, $26, 0xa120 + #lui $26, 0x004c # 100ms timer (50 MHz) + #ori $26, $26, 0x4b40 + lui $26, 0x00be # 250ms timer (50 MHz) + ori $26, 0xbc20 + #lui $26, 0x017d # 500ms timer (50 MHz) + #ori $26, 0x7840 + #lui $26, 0x02fa # 1 sec timer (50 MHz) + #ori $26, $26, 0xf080 + mtc0 $26, $11, 0 # Set Compare register to timer value + + eret # Return from Reset Exception + +$run: + jal main + nop + +$done: + j $done + nop + + .end boot + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/os/exception_handler.c b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/os/exception_handler.c new file mode 100755 index 0000000..88a0723 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/os/exception_handler.c @@ -0,0 +1,136 @@ +#include "drivers/lcd.h" +#include "drivers/piezo.h" + +void dead_loop(void) +{ + for (;;) {} +} + +void mips32_handler_AdEL(void) +{ + LCD_clear(); + LCD_printString("AdEL"); + dead_loop(); +} + +void mips32_handler_AdES(void) +{ + LCD_clear(); + LCD_printString("AdES"); + dead_loop(); +} + +void mips32_handler_Bp(void) +{ + LCD_clear(); + LCD_printString("Bp"); + dead_loop(); +} + +void mips32_handler_CpU(void) +{ + LCD_clear(); + LCD_printString("CpU"); + dead_loop(); +} + +void mips32_handler_Ov(void) +{ + LCD_clear(); + LCD_printString("Ov"); + dead_loop(); +} + +void mips32_handler_RI(void) +{ + LCD_clear(); + LCD_printString("RI"); + dead_loop(); +} + +void mips32_handler_Sys(void) +{ + LCD_clear(); + LCD_printString("Sys"); + dead_loop(); +} + +void mips32_handler_Tr(void) +{ + LCD_clear(); + LCD_printString("Trap"); + dead_loop(); +} + +/* Timer */ +void mips32_handler_HwInt5(void) +{ + static volatile char wait = 0; + + if (wait == 1) { + wait++; + Piezo_set(0, 0); + } + else if (wait < 1) { + wait++; + } +} + +void mips32_handler_HwInt4(void) +{ + static volatile char count = 0; + + LCD_printByte(count); + count++; +} + +void mips32_handler_HwInt3(void) +{ + static volatile char count = 0; + + LCD_printByte(count); + count++; +} + +void mips32_handler_HwInt2(void) +{ + static volatile char count = 0; + + LCD_printByte(count); + count++; +} + +void mips32_handler_HwInt1(void) +{ + static volatile char count = 0; + + LCD_printByte(count); + count++; +} + + +/* UART */ +void mips32_handler_HwInt0(void) +{ + static volatile char count = 0; + + LCD_printByte(count); + count++; +} + +void mips32_handler_SwInt1(void) +{ + static volatile char count = 0; + + LCD_printByte(count); + count++; +} + +void mips32_handler_SwInt0(void) +{ + static volatile char count = 0; + + LCD_printByte(count); + count++; +} + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/os/exception_handler.h b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/os/exception_handler.h new file mode 100755 index 0000000..01502fe --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/os/exception_handler.h @@ -0,0 +1,25 @@ +#ifndef __exception_handler_h__ +#define __exception_handler_h__ + +/* MIPS32 Exception Handlers */ +void mips32_handler_AdEL(void); +void mips32_handler_AdES(void); +void mips32_handler_Bp(void); +void mips32_handler_CpU(void); +void mips32_handler_Ov(void); +void mips32_handler_RI(void); +void mips32_handler_Sys(void); +void mips32_handler_Tr(void); + +/* MIPS32 Interrupt Handlers */ +void mips32_handler_HwInt5(void); +void mips32_handler_HwInt4(void); +void mips32_handler_HwInt3(void); +void mips32_handler_HwInt2(void); +void mips32_handler_HwInt1(void); +void mips32_handler_HwInt0(void); +void mips32_handler_SwInt1(void); +void mips32_handler_SwInt0(void); + +#endif + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/os/exceptions.asm b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/os/exceptions.asm new file mode 100755 index 0000000..2796004 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/os/exceptions.asm @@ -0,0 +1,168 @@ +############################################################################### +# TITLE: Exception Vectors +# AUTHOR: Grant Ayers (ayers@cs.utah.edu) +# DATE: 23 May 2012 +# FILENAME: exceptions.asm +# PROJECT: University of Utah XUM Single Core +# DESCRIPTION: +# Provides the exception vectors which jump to +# exception-handling routines. +# +############################################################################### + + .text + .balign 4 + .set noreorder + .set noat + +exc_save: + # Save all registers except k0 k1 sp ra + addiu $sp, $sp, -112 + sw $1, 0($sp) + sw $2, 4($sp) + sw $3, 8($sp) + sw $4, 12($sp) + sw $5, 16($sp) + sw $6, 20($sp) + sw $7, 24($sp) + sw $8, 28($sp) + sw $9, 32($sp) + sw $10, 36($sp) + sw $11, 40($sp) + sw $12, 44($sp) + sw $13, 48($sp) + sw $14, 52($sp) + sw $15, 56($sp) + sw $16, 60($sp) + sw $17, 64($sp) + sw $18, 68($sp) + sw $19, 72($sp) + sw $20, 76($sp) + sw $21, 80($sp) + sw $22, 84($sp) + sw $23, 88($sp) + sw $24, 92($sp) + sw $25, 96($sp) + sw $28, 100($sp) + jr $ra + sw $30, 104($sp) + +exc_restore: + # Restore all registers except k0 k1 sp ra + lw $1, 0($sp) + lw $2, 4($sp) + lw $3, 8($sp) + lw $4, 12($sp) + lw $5, 16($sp) + lw $6, 20($sp) + lw $7, 24($sp) + lw $8, 28($sp) + lw $9, 32($sp) + lw $10, 36($sp) + lw $11, 40($sp) + lw $12, 44($sp) + lw $13, 48($sp) + lw $14, 52($sp) + lw $15, 56($sp) + lw $16, 60($sp) + lw $17, 64($sp) + lw $18, 68($sp) + lw $19, 72($sp) + lw $20, 76($sp) + lw $21, 80($sp) + lw $22, 84($sp) + lw $23, 88($sp) + lw $24, 92($sp) + lw $25, 96($sp) + lw $28, 100($sp) + lw $30, 104($sp) + jr $ra + addiu $sp, $sp, 112 + + + .global mips32_general_exception + .ent mips32_general_exception +mips32_general_exception: + or $26, $0, $ra + jal exc_save + nop + mfc0 $27, $13, 0 # Read Cause which has ExcCode bits + srl $27, $27, 2 # Extract exception code to $k1 + andi $27, $27, 0x001f + + la $ra, $end_exception # Jump to the appropriate handler + addiu $t0, $0, 4 + addiu $t1, $0, 5 + addiu $t2, $0, 8 + addiu $t3, $0, 9 + beq $t0, $27, mips32_handler_AdEL + addiu $t0, $0, 10 + beq $t1, $27, mips32_handler_AdES + addiu $t1, $0, 11 + beq $t2, $27, mips32_handler_Sys + addiu $t2, $0, 12 + beq $t3, $27, mips32_handler_Bp + addiu $t3, $0, 13 + beq $t0, $27, mips32_handler_RI + nop + beq $t1, $27, mips32_handler_CpU + nop + beq $t2, $27, mips32_handler_Ov + nop + beq $t3, $27, mips32_handler_Tr + nop + +$end_exception: + jal exc_restore + xor $27, $0, $0 + or $ra, $0, $26 + xor $26, $0, $0 + eret + .end mips32_general_exception + + + +### "Special" Interrupt Vector: Cause_IV must be set. + + .ent mips32_interrupt_exception + .global mips32_interrupt_exception +mips32_interrupt_exception: + mfc0 $26, $12, 0 # Status register for IM bits + mfc0 $27, $13, 0 # Cause register for IP bits + and $26, $26, $27 # Extract pending, unmasked interrupts + srl $26, $26, 8 + andi $26, $26, 0x00ff + + addu $27, $0, $ra + jal exc_save + clz $26, $26 + la $ra, $end_interrupt # All C functions will return here + addiu $t0, $0, 24 + addiu $t1, $0, 25 + addiu $t2, $0, 26 + beq $26, $t0, mips32_handler_HwInt5 + addiu $t0, $0, 27 + beq $26, $t1, mips32_handler_HwInt4 + addiu $t1, $0, 28 + beq $26, $t2, mips32_handler_HwInt3 + addiu $t2, $0, 29 + beq $26, $t0, mips32_handler_HwInt2 + addiu $t0, $0, 30 + beq $26, $t1, mips32_handler_HwInt1 + addiu $t1, $0, 31 + beq $26, $t2, mips32_handler_HwInt0 + nop + beq $26, $t0, mips32_handler_SwInt1 + nop + beq $26, $t1, mips32_handler_SwInt0 + nop + + +$end_interrupt: + jal exc_restore + mfc0 $26, $9, 0 # Clear HwInt5 if applicable + or $ra, $0, $27 + eret + .end mips32_interrupt_exception + + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/os/vectors.asm b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/os/vectors.asm new file mode 100755 index 0000000..dd455bc --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/os/vectors.asm @@ -0,0 +1,39 @@ +############################################################################### +# TITLE: Exception Vectors +# AUTHOR: Grant Ayers (ayers@cs.utah.edu) +# DATE: 23 May 2012 +# FILENAME: exceptions.asm +# PROJECT: University of Utah XUM Single Core +# DESCRIPTION: +# Provides the exception vectors which jump to +# exception-handling routines. +# +############################################################################### + + +# Current setup: +# 1. The exception vector begins at address 0x0. +# 2. The interrupt vector begins at address 0x8. +# 3. Each vector has room for 2 instructions (8 bytes) with which +# it must jump to its demultiplexing routine. The demultiplexing +# routine calls individual exception-specific handlers. +# 4. The linker script must ensure that this code is placed at the +# correct address. + + + .text + .balign 4 + .ent exception_vector + .set noreorder +exception_vector: + j mips32_general_exception + nop + .end exception_vector + + + .ent interrupt_vector +interrupt_vector: + j mips32_interrupt_exception + nop + .end interrupt_vector + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/os/xum.ls b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/os/xum.ls new file mode 100755 index 0000000..ca9ea04 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD3_I2C/src/os/xum.ls @@ -0,0 +1,83 @@ +/* Linker script for MIPS32 (Single Core) FPGA, intended for XUM */ + + +/* Entry Point + * + * Set it to be the label "boot" (likely in boot.asm) + * + */ +/*ENTRY(boot)*/ + + +/* Memory Section + * + * The FPGA currently uses one region of Block RAM, which is 592 KB. + * + * Instruction Memory starts at address 0. + * + * Data Memory ends 592KB later, at address 0x00094000 (the last + * usable word address is 0x00093ffc). + * + * Instructions : 0x00000000 -> 0x0000fffc ( 64KB) + * Data / BSS : 0x00001000 -> 0x00017ffc ( 32KB) + * Stack / Heap : 0x00018000 -> 0x00093ffc (496KB) + * + * + */ + +/* Sections + * + */ + +SECTIONS +{ + _sp = 0x00094000; + + . = 0 ; + + .text : + { + vectors.o(.text) + . = 0x10 ; + boot.o(.text) + exceptions.o(.text) + *(.*text*) + } + + . = 0x00001000 ; + + .data : + { + *(.rodata*) + *(.data*) + } + + _gp = ALIGN(16) + 0x7ff0; + + .got : + { + *(.got) + } + + .sdata : + { + *(.*sdata*) + } + + _bss_start = . ; + + .sbss : + { + *(.*sbss) + } + + .bss : + { + *(.*bss) + } + + _bss_end = . ; + +} + + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/README b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/README new file mode 100755 index 0000000..2bb78e9 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/README @@ -0,0 +1,35 @@ +README for XUM Demo 4 : UART (Serial Port) +------------------------------------------ + +Creator: Grant Ayers (ayers@cs.utah.edu) +Date: 26 July 2012 + + + +DEMONSTRATES +------------ + +UART, Interrupts, LCD. + + + +DESCRIPTION +----------- + +Prints text that is received by the serial port to the LCD screen. The +screen has a blinking cursor which is toggled by the timer interrupt. +The UART utilizes a hardware interrupt to notify the processor of incoming +data. The backspace key moves the cursor backward one character. + +Connect to the FPGA using 115200 Baud, 1 stop bit, no parity, and no flow +control. Use a program such as Minicom in Linux or Putty in Windows. + + + +BUILDING AND RUNNING +-------------------- + +To compile, enter the 'bin' directory and update the paths in the Makefile. +Then run 'make' from within the same directory. Use the XUM bootloader to +send the resulting .xum file to the FPGA. + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/bin/Makefile b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/bin/Makefile new file mode 100755 index 0000000..d063d6b --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/bin/Makefile @@ -0,0 +1,91 @@ +# Makefile for XUM +# +# Compiles code to run on the XUM platform, which +# is based on MIPS32 and a GCC cross-compiler toolchain. +# +# Author: Grant Ayers (ayers@cs.utah.edu) +# Date: 3 July 2012 +# + +SHELL = /bin/sh + +SRC = ../src +MIPS_PREFIX = /home/User/XUM/gnu_mips/crosstools +MIPS_BIN = $(MIPS_PREFIX)/bin +MIPS_LIB = $(MIPS_PREFIX)/mips-elf/lib +MIPS_CC = $(MIPS_BIN)/mips-elf-gcc-4.7.1.exe +MIPS_AS = $(MIPS_BIN)/mips-elf-as.exe +MIPS_LD = $(MIPS_BIN)/mips-elf-ld.exe +MIPS_OBJDUMP = $(MIPS_BIN)/mips-elf-objdump.exe +MIPS_OBJCOPY = $(MIPS_BIN)/mips-elf-objcopy.exe +UTIL_PREFIX = /home/User/XUM/demos/util +UTIL_CONVBIN = $(UTIL_PREFIX)/bintohex.exe +UTIL_CONVXUM = $(UTIL_PREFIX)/bintoxum.exe + +AS_FLAGS = -march=mips32 -EB -G0 +LD_FLAGS = -EB -static -Map app.map -T ../src/os/xum.ls +LD_LIBS = -lm -lc -lgcc +LD_SEARCH = -L$(MIPS_PREFIX)/mips-elf/lib \ + -L$(MIPS_PREFIX)/lib/gcc/mips-elf/4.7.1 +LD_DRIVER = $(MIPS_LD) $(LD_FLAGS) $(LD_SEARCH) $(LD_LIBS) +CC_FLAGS_ARCH = -march=mips32 -EB -msoft-float -mno-mips16 -mno-branch-likely \ + -mgpopt +CC_FLAGS_LANG = -Wall -O2 +CC_FLAGS_INC = -I../src/ +CC_FLAGS_AS = -Wa,-EB,-mips32,-msoft-float +CC_FLAGS_LD = -nostdlib -nostartfiles -static -T ../src/os/xum.ls +CC_FLAGS_LIB = -lm -lc -lgcc +CC_DRIVER = $(MIPS_CC) $(CC_FLAGS_ARCH) $(CC_FLAGS_LANG) \ + $(CC_FLAGS_AS) $(CC_FLAGS_INC) + + +all : app + +app : app.o uart.o lcd.o boot.o vectors.o exceptions.o exception_handler.o piezo.o + $(LD_DRIVER) $^ -o app.exe + @$(MIPS_OBJDUMP) -EB --disassemble app.exe > app.lst + @$(MIPS_OBJCOPY) -O binary -j .text app.exe app-code.bin + @$(MIPS_OBJCOPY) -O binary -j .data app.exe app-data1.bin + @$(MIPS_OBJCOPY) -O binary -j .sdata app.exe app-data2.bin + @$(MIPS_OBJCOPY) -O binary -j .sbss app.exe app-data3.bin + @$(MIPS_OBJCOPY) -O binary -j .bss app.exe app-data4.bin + @cat app-data1.bin app-data2.bin app-data3.bin app-data4.bin >> app-data.bin + @$(UTIL_CONVXUM) -d 4096 app-code.bin app-data.bin app.xum + #@$(UTIL_CONVBIN) -c -b app-code.bin app-code.coe + $(UTIL_CONVBIN) -c -b app.xum app.coe + + + +app.o : $(SRC)/app/app.c + $(CC_DRIVER) -c $(SRC)/app/app.c -o app.o + +uart.o : $(SRC)/drivers/uart.c $(SRC)/drivers/uart.h + $(CC_DRIVER) -c $(SRC)/drivers/uart.c -o uart.o + +i2c.o : $(SRC)/drivers/i2c.c $(SRC)/drivers/i2c.h + $(CC_DRIVER) -c $(SRC)/drivers/i2c.c -o i2c.o + +lcd.o : $(SRC)/drivers/lcd.c $(SRC)/drivers/lcd.h + $(CC_DRIVER) -c $(SRC)/drivers/lcd.c -o lcd.o + +monitor.o : $(SRC)/drivers/monitor.c $(SRC)/drivers/monitor.h i2c.o + $(CC_DRIVER) -c $(SRC)/drivers/monitor.c -o monitor.o + +piezo.o : $(SRC)/drivers/piezo.c $(SRC)/drivers/piezo.h + $(CC_DRIVER) -c $(SRC)/drivers/piezo.c -o piezo.o + +exception_handler.o : $(SRC)/os/exception_handler.c $(SRC)/os/exception_handler.h lcd.o piezo.o monitor.o + $(CC_DRIVER) -c $(SRC)/os/exception_handler.c -o exception_handler.o + +boot.o : $(SRC)/os/boot.asm + $(MIPS_AS) $(AS_FLAGS) -o boot.o $(SRC)/os/boot.asm + +vectors.o : $(SRC)/os/vectors.asm + $(MIPS_AS) $(AS_FLAGS) -o vectors.o $(SRC)/os/vectors.asm + +exceptions.o : $(SRC)/os/exceptions.asm + $(MIPS_AS) $(AS_FLAGS) -o exceptions.o $(SRC)/os/exceptions.asm + +clean : + rm -f *.o *.exe *.map *.coe *.bin *.map *.xum *.lst + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/bin/app.xum b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/bin/app.xum new file mode 100755 index 0000000..7c9d0db Binary files /dev/null and b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/bin/app.xum differ diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/app/app.c b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/app/app.c new file mode 100755 index 0000000..6493fff --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/app/app.c @@ -0,0 +1,16 @@ +#include "drivers/piezo.h" +#include "drivers/lcd.h" +#include "drivers/uart.h" + + +int main(void) +{ + Piezo_play(C5); + LCD_clear(); + UART_disableBoot(); + + while (1) {}; + + return 0; +} + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/drivers/i2c.c b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/drivers/i2c.c new file mode 100755 index 0000000..0d66526 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/drivers/i2c.c @@ -0,0 +1,50 @@ +#include "i2c.h" + +void I2C_clear(void) +{ + volatile uint32_t *i2c = (volatile uint32_t *)I2C_ADDRESS; + uint32_t cmd = (1 << 8); + + *i2c = cmd; +} + +void I2C_EnQ(uint8_t byte) +{ + volatile uint32_t *i2c = (volatile uint32_t *)I2C_ADDRESS; + + uint32_t cmd = (1 << 9) | (uint32_t)byte; + *i2c = cmd; +} + +void I2C_transmit(void) +{ + volatile uint32_t *i2c = (volatile uint32_t *)I2C_ADDRESS; + + uint32_t cmd = (1 << 10); + *i2c = cmd; +} + +void I2C_setReceive(uint8_t bytes) +{ + volatile uint32_t *i2c = (volatile uint32_t *)I2C_ADDRESS; + + uint32_t cmd = (1 << 12) | (uint32_t)bytes; + *i2c = cmd; +} + +void I2C_receive(void) +{ + volatile uint32_t *i2c = (volatile uint32_t *)I2C_ADDRESS; + + uint32_t cmd = (1 << 11); + *i2c = cmd; +} + +uint32_t I2C_DeQ(void) +{ + volatile uint32_t *i2c = (volatile uint32_t *)I2C_ADDRESS; + + uint32_t data = *i2c; + return data; +} + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/drivers/i2c.h b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/drivers/i2c.h new file mode 100755 index 0000000..eb06443 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/drivers/i2c.h @@ -0,0 +1,16 @@ +#ifndef __I2C_H__ +#define __I2C_H__ + +#include + +#define I2C_ADDRESS 0x90000000 + +void I2C_clear(void); +void I2C_EnQ(uint8_t byte); +void I2C_transmit(void); +void I2C_setReceive(uint8_t bytes); +void I2C_receive(void); +uint32_t I2C_DeQ(void); + +#endif + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/drivers/lcd.c b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/drivers/lcd.c new file mode 100755 index 0000000..a95b38a --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/drivers/lcd.c @@ -0,0 +1,142 @@ +#include "lcd.h" + +static uint8_t LCD_position = 0; +static uint8_t LCD_autoIncr = 1; + +static void LCD_incrPos(uint32_t amount) +{ + if (LCD_autoIncr == 0) { + return; + } + while (amount > 32) { + amount -= 32; + } + LCD_position += (uint8_t)amount; + if (LCD_position >= 32) { + LCD_position -= 32; + } +} + + +void LCD_clear(void) +{ + volatile uint32_t *LCD; + int i; + + LCD = (volatile uint32_t *)LCD_ADDRESS; + + for (i=0; i<8; i++) { + LCD[i] = 0x20202020; + } + LCD_position = 0; +} + +void LCD_setPos(uint8_t position) +{ + LCD_position = position; +} + +uint8_t LCD_getPos(void) +{ + return LCD_position; +} + +void LCD_setAutoIncr(uint8_t incr) +{ + LCD_autoIncr = incr; +} + +void LCD_printByte(uint8_t byte) +{ + volatile uint8_t *LCD; + + LCD = (volatile uint8_t *)(LCD_ADDRESS + LCD_position); + *LCD = byte; + LCD_incrPos(1); +} + +void LCD_printByteHex(uint8_t byte) +{ + volatile uint8_t *LCD; + uint8_t nibble_h, nibble_l; + + LCD = (volatile uint8_t *)(LCD_ADDRESS + LCD_position); + nibble_h = byte >> 4; + nibble_l = byte & 0x0f; + + if (nibble_h < 10) { + nibble_h += 48; + } + else { + nibble_h += 55; + } + if (nibble_l < 10) { + nibble_l += 48; + } + else { + nibble_h += 55; + } + *LCD = nibble_h; + LCD++; + *LCD = nibble_l; + LCD_incrPos(2); +} + +void LCD_printByteDec(uint8_t byte) +{ + volatile uint8_t *LCD; + uint8_t hundreds, tens, ones; + uint32_t n_printed = 1; + + LCD = (volatile uint8_t *)(LCD_ADDRESS + LCD_position); + hundreds = tens = ones = 48; + + while (byte >= 100) { + hundreds++; + byte -= 100; + } + while (byte >= 10) { + tens++; + byte -= 10; + } + while (byte >= 1) { + ones++; + byte -= 1; + } + if (hundreds > 48) { + *LCD = hundreds; + LCD++; + n_printed++; + } + if ((n_printed > 1) || (tens > 48)) { + *LCD = tens; + LCD++; + n_printed++; + } + *LCD = ones; + LCD_incrPos(n_printed); +} + +void LCD_printWord(uint32_t word) +{ + volatile uint32_t *LCD; + + LCD = (volatile uint32_t *)(LCD_ADDRESS + LCD_position); + *LCD = word; + LCD_incrPos(4); +} + +void LCD_printString(char *string) +{ + volatile char *LCD; + int i = 0; + + LCD = (volatile char *)(LCD_ADDRESS + LCD_position); + + while (string[i] != '\0') { + LCD[i] = string[i]; + i++; + } + LCD_incrPos(i); +} + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/drivers/lcd.h b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/drivers/lcd.h new file mode 100755 index 0000000..2ebcd14 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/drivers/lcd.h @@ -0,0 +1,19 @@ +#ifndef __LCD_H__ +#define __LCD_H__ + +#include + +#define LCD_ADDRESS 0x80000000 + +void LCD_clear(void); +void LCD_setPos(uint8_t position); +uint8_t LCD_getPos(void); +void LCD_setAutoIncr(uint8_t incr); +void LCD_printByte(uint8_t byte); +void LCD_printByteHex(uint8_t byte); +void LCD_printByteDec(uint8_t byte); +void LCD_printWord(uint32_t word); +void LCD_printString(char *string); + +#endif + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/drivers/monitor.c b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/drivers/monitor.c new file mode 100755 index 0000000..6509ac4 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/drivers/monitor.c @@ -0,0 +1,33 @@ +#include "monitor.h" + +void Monitor_start(void) +{ + I2C_clear(); + I2C_EnQ(MONITOR_BUS_ADDR); + I2C_EnQ(0x40); // Configuration Register 1 + I2C_EnQ(0x1); // Enable monitoring + I2C_transmit(); +} + + +// Node is 0->Remote 1, 1->Local, 2->Remote 2 +uint32_t Monitor_readTemp(int node) +{ + uint8_t reg = 0x25 + node; + uint32_t data; + + // Set the read register + I2C_clear(); + I2C_EnQ(MONITOR_BUS_ADDR); + I2C_EnQ(reg); + I2C_transmit(); + + // Receive the register + I2C_EnQ(MONITOR_BUS_ADDR); + I2C_setReceive(1); + I2C_receive(); + data = I2C_DeQ(); + + return data; +} + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/drivers/monitor.h b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/drivers/monitor.h new file mode 100755 index 0000000..9177ce0 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/drivers/monitor.h @@ -0,0 +1,13 @@ +#ifndef __MONITOR_H__ +#define __MONITOR_H__ + +#include "i2c.h" + +#define MONITOR_BUS_ADDR 0x2C + +void Monitor_start(void); +uint32_t Monitor_readTemp(int node); + + +#endif + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/drivers/piezo.c b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/drivers/piezo.c new file mode 100755 index 0000000..97ffe11 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/drivers/piezo.c @@ -0,0 +1,19 @@ +#include "piezo.h" + +void Piezo_set(uint32_t count, int enable) +{ + volatile uint32_t *Piezo = (volatile uint32_t *)PIEZO_ADDRESS; + + if (enable) { + *Piezo = count | 0x1000000; + } + else { + *Piezo = count & ~0x1000000; + } +} + +void Piezo_play(uint32_t note) +{ + Piezo_set(note, 1); +} + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/drivers/piezo.h b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/drivers/piezo.h new file mode 100755 index 0000000..b59b1d5 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/drivers/piezo.h @@ -0,0 +1,43 @@ +#ifndef __PIEZO_H__ +#define __PIEZO_H__ + +#include + +#define PIEZO_ADDRESS 0xA0000000 + +/* Following are defined for a 100 MHz Piezo driver */ +#define C0 3058104 +#define C1 1529052 + +#define C4 191110 +#define C4s 180388 +#define D4f C4s +#define D4 170264 +#define D4s 160705 +#define E4f D4s +#define E4 151685 +#define F4 143172 +#define F4s 135138 +#define G4f F4s +#define G4 127551 +#define G4s 120395 +#define A4f G4s +#define A4 113636 +#define A4s 107259 +#define B4f A4s +#define B4 101239 +#define C5 95557 +#define C5s 90192 +#define D5f C5s +#define D5 85131 +#define D5s 80354 +#define E5f D5s +#define E5 75843 + +#define C8 11945 + + +void Piezo_set(uint32_t count, int enable); +void Piezo_play(uint32_t note); + +#endif diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/drivers/uart.c b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/drivers/uart.c new file mode 100755 index 0000000..3437c61 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/drivers/uart.c @@ -0,0 +1,38 @@ +#include "uart.h" + +void UART_disableBoot(void) +{ + volatile uint32_t *uart = (volatile uint32_t *)UART_ADDRESS; + uint32_t data; + + data = 0x00000100; + + *uart = data; +} + +uint8_t UART_readByte(void) +{ + volatile uint32_t *uart = (volatile uint32_t *)UART_ADDRESS; + uint32_t data; + + data = *uart; + + return (uint8_t)data; +} + +uint32_t UART_readMessage(void) +{ + volatile uint32_t *uart = (volatile uint32_t *)UART_ADDRESS; + + return *uart; +} + +void UART_writeByte(uint8_t byte) +{ + volatile uint32_t *uart = (volatile uint32_t *)UART_ADDRESS; + uint32_t data; + + data = (uint32_t)byte; + *uart = data; +} + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/drivers/uart.h b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/drivers/uart.h new file mode 100755 index 0000000..cf48a09 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/drivers/uart.h @@ -0,0 +1,14 @@ +#ifndef __UART_H__ +#define __UART_H__ + +#include + +#define UART_ADDRESS 0xB0000000 + +void UART_disableBoot(void); +uint8_t UART_readByte(void); +uint32_t UART_readMessage(void); +void UART_writeByte(uint8_t byte); + +#endif + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/os/boot.asm b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/os/boot.asm new file mode 100755 index 0000000..2cd243a --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/os/boot.asm @@ -0,0 +1,72 @@ +############################################################################### +# TITLE: Boot Up Code +# AUTHOR: Grant Ayers (ayers@cs.utah.edu) +# DATE: 19 July 2011 +# FILENAME: boot.asm +# PROJECT: University of Utah XUM Single Core +# DESCRIPTION: +# Initializes the global pointer and stack pointer. +# Zeros BSS memory region and jumps to main(). +# +############################################################################### + + + .text + .balign 4 + .global boot + .ent boot + .set noreorder +boot: + la $t0, _bss_start # Defined in linker script + la $t1, _bss_end + la $sp, _sp + la $gp, _gp + +$bss_clear: + beq $t0, $t1, $cp0_setup # Loop until BSS is cleared + nop + sb $0, 0($t0) + j $bss_clear + addiu $t0, $t0, 1 + +$cp0_setup: + la $26, $run # Load the address of $run into + mtc0 $26, $30, 0 # the ErrorEPC + mfc0 $26, $13, 0 # Load Cause register + lui $27, 0x0080 # Use "special" interrupt vector + or $26, $26, $27 + mtc0 $26, $13, 0 # Commit new Cause register + mfc0 $26, $12, 0 # Load Status register + lui $27, 0x0fff # Disable access to Coprocessors, + ori $27, $27, 0xffef # Base operating mode is Kernel + and $26, $26, $27 + ori $27, $0, 0xff01 # Enable all interrupts + or $26, $26, $27 + mtc0 $26, $12, 0 # Commit new Status register + + #lui $26, 0x0000 # 1ms timer (50 MHz) + #ori $26, $26, 0xc350 + #lui $26, 0x0007 # 10ms timer (50 MHz) + #ori $26, $26, 0xa120 + #lui $26, 0x004c # 100ms timer (50 MHz) + #ori $26, $26, 0x4b40 + lui $26, 0x00be # 250ms timer (50 MHz) + ori $26, 0xbc20 + #lui $26, 0x017d # 500ms timer (50 MHz) + #ori $26, 0x7840 + #lui $26, 0x02fa # 1 sec timer (50 MHz) + #ori $26, $26, 0xf080 + mtc0 $26, $11, 0 # Set Compare register to timer value + + eret # Return from Reset Exception + +$run: + jal main + nop + +$done: + j $done + nop + + .end boot + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/os/exception_handler.c b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/os/exception_handler.c new file mode 100755 index 0000000..a234d33 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/os/exception_handler.c @@ -0,0 +1,168 @@ +#include "drivers/lcd.h" +#include "drivers/piezo.h" +#include "drivers/monitor.h" +#include "drivers/uart.h" + +void dead_loop(void) +{ + for (;;) {} +} + +void mips32_handler_AdEL(void) +{ + LCD_clear(); + LCD_printString("AdEL"); + dead_loop(); +} + +void mips32_handler_AdES(void) +{ + LCD_clear(); + LCD_printString("AdES"); + dead_loop(); +} + +void mips32_handler_Bp(void) +{ + LCD_clear(); + LCD_printString("Bp"); + dead_loop(); +} + +void mips32_handler_CpU(void) +{ + LCD_clear(); + LCD_printString("CpU"); + dead_loop(); +} + +void mips32_handler_Ov(void) +{ + LCD_clear(); + LCD_printString("Ov"); + dead_loop(); +} + +void mips32_handler_RI(void) +{ + LCD_clear(); + LCD_printString("RI"); + dead_loop(); +} + +void mips32_handler_Sys(void) +{ + LCD_clear(); + LCD_printString("Sys"); + dead_loop(); +} + +void mips32_handler_Tr(void) +{ + LCD_clear(); + LCD_printString("Trap"); + dead_loop(); +} + +/* Timer */ +void mips32_handler_HwInt5(void) +{ + static volatile char wait = 0; + static volatile uint8_t cursor = 0x20; + + if (wait == 1) { + wait++; + Piezo_set(0, 0); + } + else if (wait < 1) { + wait++; + } + + LCD_setAutoIncr(0); + LCD_printByte(cursor); + LCD_setAutoIncr(1); + + if (cursor == 0x20) { + cursor = 0xff; + } + else { + cursor = 0x20; + } + +} + +void mips32_handler_HwInt4(void) +{ + static volatile char count = 0; + + LCD_printByte(count); + count++; +} + +void mips32_handler_HwInt3(void) +{ + static volatile char count = 0; + + LCD_printByte(count); + count++; +} + +void mips32_handler_HwInt2(void) +{ + static volatile char count = 0; + + LCD_printByte(count); + count++; +} + +void mips32_handler_HwInt1(void) +{ + static volatile char count = 0; + + LCD_printByte(count); + count++; +} + + +/* UART */ +void mips32_handler_HwInt0(void) +{ + uint32_t recv_msg; + uint32_t bytes_avail; + uint8_t read_byte; + + recv_msg = UART_readMessage(); + read_byte = (uint8_t)recv_msg; + bytes_avail = (recv_msg >> 8); + + while (bytes_avail > 0) { + if (read_byte == 0x7f) { // delete + LCD_setAutoIncr(0); + LCD_printByte(0x20); + LCD_setPos(LCD_getPos()-1); + LCD_setAutoIncr(1); + } + else { + LCD_printByte(read_byte); + } + bytes_avail--; + read_byte = UART_readByte(); + } +} + +void mips32_handler_SwInt1(void) +{ + static volatile char count = 0; + + LCD_printByte(count); + count++; +} + +void mips32_handler_SwInt0(void) +{ + static volatile char count = 0; + + LCD_printByte(count); + count++; +} + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/os/exception_handler.h b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/os/exception_handler.h new file mode 100755 index 0000000..01502fe --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/os/exception_handler.h @@ -0,0 +1,25 @@ +#ifndef __exception_handler_h__ +#define __exception_handler_h__ + +/* MIPS32 Exception Handlers */ +void mips32_handler_AdEL(void); +void mips32_handler_AdES(void); +void mips32_handler_Bp(void); +void mips32_handler_CpU(void); +void mips32_handler_Ov(void); +void mips32_handler_RI(void); +void mips32_handler_Sys(void); +void mips32_handler_Tr(void); + +/* MIPS32 Interrupt Handlers */ +void mips32_handler_HwInt5(void); +void mips32_handler_HwInt4(void); +void mips32_handler_HwInt3(void); +void mips32_handler_HwInt2(void); +void mips32_handler_HwInt1(void); +void mips32_handler_HwInt0(void); +void mips32_handler_SwInt1(void); +void mips32_handler_SwInt0(void); + +#endif + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/os/exceptions.asm b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/os/exceptions.asm new file mode 100755 index 0000000..2796004 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/os/exceptions.asm @@ -0,0 +1,168 @@ +############################################################################### +# TITLE: Exception Vectors +# AUTHOR: Grant Ayers (ayers@cs.utah.edu) +# DATE: 23 May 2012 +# FILENAME: exceptions.asm +# PROJECT: University of Utah XUM Single Core +# DESCRIPTION: +# Provides the exception vectors which jump to +# exception-handling routines. +# +############################################################################### + + .text + .balign 4 + .set noreorder + .set noat + +exc_save: + # Save all registers except k0 k1 sp ra + addiu $sp, $sp, -112 + sw $1, 0($sp) + sw $2, 4($sp) + sw $3, 8($sp) + sw $4, 12($sp) + sw $5, 16($sp) + sw $6, 20($sp) + sw $7, 24($sp) + sw $8, 28($sp) + sw $9, 32($sp) + sw $10, 36($sp) + sw $11, 40($sp) + sw $12, 44($sp) + sw $13, 48($sp) + sw $14, 52($sp) + sw $15, 56($sp) + sw $16, 60($sp) + sw $17, 64($sp) + sw $18, 68($sp) + sw $19, 72($sp) + sw $20, 76($sp) + sw $21, 80($sp) + sw $22, 84($sp) + sw $23, 88($sp) + sw $24, 92($sp) + sw $25, 96($sp) + sw $28, 100($sp) + jr $ra + sw $30, 104($sp) + +exc_restore: + # Restore all registers except k0 k1 sp ra + lw $1, 0($sp) + lw $2, 4($sp) + lw $3, 8($sp) + lw $4, 12($sp) + lw $5, 16($sp) + lw $6, 20($sp) + lw $7, 24($sp) + lw $8, 28($sp) + lw $9, 32($sp) + lw $10, 36($sp) + lw $11, 40($sp) + lw $12, 44($sp) + lw $13, 48($sp) + lw $14, 52($sp) + lw $15, 56($sp) + lw $16, 60($sp) + lw $17, 64($sp) + lw $18, 68($sp) + lw $19, 72($sp) + lw $20, 76($sp) + lw $21, 80($sp) + lw $22, 84($sp) + lw $23, 88($sp) + lw $24, 92($sp) + lw $25, 96($sp) + lw $28, 100($sp) + lw $30, 104($sp) + jr $ra + addiu $sp, $sp, 112 + + + .global mips32_general_exception + .ent mips32_general_exception +mips32_general_exception: + or $26, $0, $ra + jal exc_save + nop + mfc0 $27, $13, 0 # Read Cause which has ExcCode bits + srl $27, $27, 2 # Extract exception code to $k1 + andi $27, $27, 0x001f + + la $ra, $end_exception # Jump to the appropriate handler + addiu $t0, $0, 4 + addiu $t1, $0, 5 + addiu $t2, $0, 8 + addiu $t3, $0, 9 + beq $t0, $27, mips32_handler_AdEL + addiu $t0, $0, 10 + beq $t1, $27, mips32_handler_AdES + addiu $t1, $0, 11 + beq $t2, $27, mips32_handler_Sys + addiu $t2, $0, 12 + beq $t3, $27, mips32_handler_Bp + addiu $t3, $0, 13 + beq $t0, $27, mips32_handler_RI + nop + beq $t1, $27, mips32_handler_CpU + nop + beq $t2, $27, mips32_handler_Ov + nop + beq $t3, $27, mips32_handler_Tr + nop + +$end_exception: + jal exc_restore + xor $27, $0, $0 + or $ra, $0, $26 + xor $26, $0, $0 + eret + .end mips32_general_exception + + + +### "Special" Interrupt Vector: Cause_IV must be set. + + .ent mips32_interrupt_exception + .global mips32_interrupt_exception +mips32_interrupt_exception: + mfc0 $26, $12, 0 # Status register for IM bits + mfc0 $27, $13, 0 # Cause register for IP bits + and $26, $26, $27 # Extract pending, unmasked interrupts + srl $26, $26, 8 + andi $26, $26, 0x00ff + + addu $27, $0, $ra + jal exc_save + clz $26, $26 + la $ra, $end_interrupt # All C functions will return here + addiu $t0, $0, 24 + addiu $t1, $0, 25 + addiu $t2, $0, 26 + beq $26, $t0, mips32_handler_HwInt5 + addiu $t0, $0, 27 + beq $26, $t1, mips32_handler_HwInt4 + addiu $t1, $0, 28 + beq $26, $t2, mips32_handler_HwInt3 + addiu $t2, $0, 29 + beq $26, $t0, mips32_handler_HwInt2 + addiu $t0, $0, 30 + beq $26, $t1, mips32_handler_HwInt1 + addiu $t1, $0, 31 + beq $26, $t2, mips32_handler_HwInt0 + nop + beq $26, $t0, mips32_handler_SwInt1 + nop + beq $26, $t1, mips32_handler_SwInt0 + nop + + +$end_interrupt: + jal exc_restore + mfc0 $26, $9, 0 # Clear HwInt5 if applicable + or $ra, $0, $27 + eret + .end mips32_interrupt_exception + + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/os/vectors.asm b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/os/vectors.asm new file mode 100755 index 0000000..dd455bc --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/os/vectors.asm @@ -0,0 +1,39 @@ +############################################################################### +# TITLE: Exception Vectors +# AUTHOR: Grant Ayers (ayers@cs.utah.edu) +# DATE: 23 May 2012 +# FILENAME: exceptions.asm +# PROJECT: University of Utah XUM Single Core +# DESCRIPTION: +# Provides the exception vectors which jump to +# exception-handling routines. +# +############################################################################### + + +# Current setup: +# 1. The exception vector begins at address 0x0. +# 2. The interrupt vector begins at address 0x8. +# 3. Each vector has room for 2 instructions (8 bytes) with which +# it must jump to its demultiplexing routine. The demultiplexing +# routine calls individual exception-specific handlers. +# 4. The linker script must ensure that this code is placed at the +# correct address. + + + .text + .balign 4 + .ent exception_vector + .set noreorder +exception_vector: + j mips32_general_exception + nop + .end exception_vector + + + .ent interrupt_vector +interrupt_vector: + j mips32_interrupt_exception + nop + .end interrupt_vector + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/os/xum.ls b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/os/xum.ls new file mode 100755 index 0000000..ca9ea04 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD4_UART/src/os/xum.ls @@ -0,0 +1,83 @@ +/* Linker script for MIPS32 (Single Core) FPGA, intended for XUM */ + + +/* Entry Point + * + * Set it to be the label "boot" (likely in boot.asm) + * + */ +/*ENTRY(boot)*/ + + +/* Memory Section + * + * The FPGA currently uses one region of Block RAM, which is 592 KB. + * + * Instruction Memory starts at address 0. + * + * Data Memory ends 592KB later, at address 0x00094000 (the last + * usable word address is 0x00093ffc). + * + * Instructions : 0x00000000 -> 0x0000fffc ( 64KB) + * Data / BSS : 0x00001000 -> 0x00017ffc ( 32KB) + * Stack / Heap : 0x00018000 -> 0x00093ffc (496KB) + * + * + */ + +/* Sections + * + */ + +SECTIONS +{ + _sp = 0x00094000; + + . = 0 ; + + .text : + { + vectors.o(.text) + . = 0x10 ; + boot.o(.text) + exceptions.o(.text) + *(.*text*) + } + + . = 0x00001000 ; + + .data : + { + *(.rodata*) + *(.data*) + } + + _gp = ALIGN(16) + 0x7ff0; + + .got : + { + *(.got) + } + + .sdata : + { + *(.*sdata*) + } + + _bss_start = . ; + + .sbss : + { + *(.*sbss) + } + + .bss : + { + *(.*bss) + } + + _bss_end = . ; + +} + + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/README b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/README new file mode 100755 index 0000000..946f124 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/README @@ -0,0 +1,50 @@ +README for XUM Demo 5 : Threads +------------------------------- + +Creator: Grant Ayers (ayers@cs.utah.edu) +Date: 26 July 2012 + + + +DEMONSTRATES +------------ + +Atomic locks, threads, LEDs, LCD. + + + +DESCRIPTION +----------- + +This demo implements a basic thread scheduler which runs eight separate +threads on a single processor. Each thread writes a continuously-changing +value to a location on the LCD screen corresponding to its unique thread ID +(1 through 8). However, it only changes and updates this value when it holds +a lock which is shared among the eight threads. XXX + +Each thread has its own 16 KB stack space, arranged as follows: + + Thread Start End Initial SP + -------------------------------------------- + Kernel 0x90000 0x93ffc 0x94000 + Thread 1 0x8c000 0x8fffc 0x90000 + Thread 2 0x88000 0x8bffc 0x8c000 + Thread 3 0x84000 0x87ffc 0x88000 + Thread 4 0x80000 0x83ffc 0x84000 + Thread 5 0x7c000 0x7fffc 0x80000 + Thread 6 0x78000 0x7bffc 0x7c000 + Thread 7 0x74000 0x77ffc 0x78000 + Thread 8 0x70000 0x73ffc 0x74000 + +Scheduling decisions are made each time the timer interrupts, and the +scheduling policy is a simple round-robin rotation. + + + +BUILDING AND RUNNING +-------------------- + +To compile, enter the 'bin' directory and update the paths in the Makefile. +Then run 'make' from within the same directory. Use the XUM bootloader to +send the resulting .xum file to the FPGA. + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/bin/Makefile b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/bin/Makefile new file mode 100755 index 0000000..bd3d5c9 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/bin/Makefile @@ -0,0 +1,99 @@ +# Makefile for XUM +# +# Compiles code to run on the XUM platform, which +# is based on MIPS32 and a GCC cross-compiler toolchain. +# +# Author: Grant Ayers (ayers@cs.utah.edu) +# Date: 3 July 2012 +# + +SHELL = /bin/sh + +SRC = ../src +MIPS_PREFIX = /home/User/XUM/gnu_mips/crosstools +MIPS_BIN = $(MIPS_PREFIX)/bin +MIPS_LIB = $(MIPS_PREFIX)/mips-elf/lib +MIPS_CC = $(MIPS_BIN)/mips-elf-gcc-4.7.1.exe +MIPS_AS = $(MIPS_BIN)/mips-elf-as.exe +MIPS_LD = $(MIPS_BIN)/mips-elf-ld.exe +MIPS_OBJDUMP = $(MIPS_BIN)/mips-elf-objdump.exe +MIPS_OBJCOPY = $(MIPS_BIN)/mips-elf-objcopy.exe +UTIL_PREFIX = /home/User/XUM/demos/util +UTIL_CONVBIN = $(UTIL_PREFIX)/bintohex.exe +UTIL_CONVXUM = $(UTIL_PREFIX)/bintoxum.exe + +AS_FLAGS = -march=mips32 -EB -G0 +LD_FLAGS = -EB -static -Map app.map -T ../src/os/xum.ls +LD_LIBS = -lm -lc -lgcc +LD_SEARCH = -L$(MIPS_PREFIX)/mips-elf/lib \ + -L$(MIPS_PREFIX)/lib/gcc/mips-elf/4.7.1 +LD_DRIVER = $(MIPS_LD) $(LD_FLAGS) $(LD_SEARCH) $(LD_LIBS) +CC_FLAGS_ARCH = -march=mips32 -EB -msoft-float -mno-mips16 +CC_FLAGS_LANG = -Wall -O2 -mgpopt -mxgot +CC_FLAGS_INC = -I../src/ +CC_FLAGS_AS = -Wa,-EB,-mips32,-msoft-float +CC_FLAGS_LD = -nostdlib -nostartfiles -static -T ../src/os/xum.ls +CC_FLAGS_LIB = -lm -lc -lgcc +CC_DRIVER = $(MIPS_CC) $(CC_FLAGS_ARCH) $(CC_FLAGS_LANG) \ + $(CC_FLAGS_AS) $(CC_FLAGS_INC) + + +all : app + +app : lcd.o app.o boot.o kernel.o lock.o vectors.o exceptions.o \ + exception_handler.o piezo.o uart.o led.o + $(LD_DRIVER) $^ -o app.exe + @$(MIPS_OBJDUMP) -EB --disassemble app.exe > app.lst + @$(MIPS_OBJCOPY) -O binary -j .text app.exe app-code.bin + @$(MIPS_OBJCOPY) -O binary -j .data app.exe app-data1.bin + @$(MIPS_OBJCOPY) -O binary -j .sdata app.exe app-data2.bin + @$(MIPS_OBJCOPY) -O binary -j .sbss app.exe app-data3.bin + @$(MIPS_OBJCOPY) -O binary -j .bss app.exe app-data4.bin + @cat app-data1.bin app-data2.bin app-data3.bin app-data4.bin >> app-data.bin + @$(UTIL_CONVXUM) -d 4096 app-code.bin app-data.bin app.xum + @$(UTIL_CONVBIN) -c -b app-code.bin app-code.coe + + + +app.o : $(SRC)/app/app.c + $(CC_DRIVER) -c $(SRC)/app/app.c -o app.o + +uart.o : $(SRC)/drivers/uart.c $(SRC)/drivers/uart.h + $(CC_DRIVER) -c $(SRC)/drivers/uart.c -o uart.o + +i2c.o : $(SRC)/drivers/i2c.c $(SRC)/drivers/i2c.h + $(CC_DRIVER) -c $(SRC)/drivers/i2c.c -o i2c.o + +lcd.o : $(SRC)/drivers/lcd.c $(SRC)/drivers/lcd.h lock.o + $(CC_DRIVER) -c $(SRC)/drivers/lcd.c -o lcd.o + +monitor.o : $(SRC)/drivers/monitor.c $(SRC)/drivers/monitor.h i2c.o + $(CC_DRIVER) -c $(SRC)/drivers/monitor.c -o monitor.o + +piezo.o : $(SRC)/drivers/piezo.c $(SRC)/drivers/piezo.h + $(CC_DRIVER) -c $(SRC)/drivers/piezo.c -o piezo.o + +led.o : $(SRC)/drivers/led.c $(SRC)/drivers/led.h + $(CC_DRIVER) -c $(SRC)/drivers/led.c -o led.o + +exception_handler.o : $(SRC)/os/exception_handler.c $(SRC)/os/exception_handler.h lcd.o piezo.o monitor.o + $(CC_DRIVER) -c $(SRC)/os/exception_handler.c -o exception_handler.o + +kernel.o : $(SRC)/os/kernel.asm + $(MIPS_AS) $(AS_FLAGS) -o kernel.o $(SRC)/os/kernel.asm + +lock.o : $(SRC)/os/lock.c $(SRC)/os/lock.h + $(CC_DRIVER) -c $(SRC)/os/lock.c -o lock.o + +boot.o : $(SRC)/os/boot.asm + $(MIPS_AS) $(AS_FLAGS) -o boot.o $(SRC)/os/boot.asm + +vectors.o : $(SRC)/os/vectors.asm + $(MIPS_AS) $(AS_FLAGS) -o vectors.o $(SRC)/os/vectors.asm + +exceptions.o : $(SRC)/os/exceptions.asm + $(MIPS_AS) $(AS_FLAGS) -o exceptions.o $(SRC)/os/exceptions.asm + +clean : + rm -f *.o *.exe *.map *.coe *.bin *.map *.xum *.lst + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/bin/app.xum b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/bin/app.xum new file mode 100644 index 0000000..fb8889e Binary files /dev/null and b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/bin/app.xum differ diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/app/app.c b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/app/app.c new file mode 100755 index 0000000..f2966b1 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/app/app.c @@ -0,0 +1,115 @@ +#include +#include "drivers/lcd.h" +#include "drivers/led.h" +#include "os/lock.h" + +static int lock; + +void LED_showTID(int tid); +void LED_hideTID(int tid); +void delay(void); + + +/* Each thread will enter at main */ +int main(void) +{ + int tid = 0; + char val = 0; + + + /* Load unique thread ID which is stored in register k1 */ + asm ( + "addu %[tid], $27, $0\n\t" + : [tid] "=r"(tid) + : + : + ); + + /* Allow a single thread to set up the LCD screen and LEDs*/ + if (tid == 1) { + LED_write(0); + LCD_clear(); + LCD_setPos(0); + LCD_printString("Thread: 12345678"); + LCD_setPos(16); + LCD_printString("Work:"); + } + + /* Loop a critical section in which work is performed */ + while (1) { + Lock(&lock, NULL, NULL); + LED_showTID(tid); + LCD_setPos(23 + (uint8_t)tid); + LCD_printByte(val); + val++; + LED_hideTID(tid); + Unlock(&lock); + delay(); + } + + return 0; +} + + +/* delay: + * Create a software delay. Use this to increase or decrease + * the probability that the thread holds the lock when the + * scheduler swaps it out. + */ +void delay(void) +{ + /* A higher value of 'c' makes it less likely that + * a lock will be held, but also lowers throughput. */ + volatile unsigned int c = 16; // 0, 2, 8, 14, 16, 18, 500, 507 + + while (c != 0) { + c--; + } +} + +/* check_violation: + * Checks to see if more than one LED is lit, meaning that more + * than one is in the critical section. If this is true, the + * Error LED is lit. + */ +void check_violation(uint8_t led) +{ + int i; + int found_high = 0; + + for (i=0; i<8; i++) { + found_high += (led & 0x1); + if (found_high > 1) { + LED_write(LED_read() | LED_ERROR); + break; + } + led >>= 1; + } +} + +/* LED_showTID: + * Shows the thread ID (1->8) as a single lit LED (0->7). + */ +void LED_showTID(int tid) +{ + uint32_t led; + + led = LED_read(); + led |= (0x80 >> (tid - 1)); + LED_write(led); + check_violation(led); +} + + +/* LED_hideTID: + * Turns off the LED (0->7) corresponding to the thread ID (1->8). + */ +void LED_hideTID(int tid) +{ + uint32_t led; + + led = LED_read(); + led &= ~(0x80 >> (tid - 1)); + LED_write(led); +} + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/drivers/i2c.c b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/drivers/i2c.c new file mode 100755 index 0000000..0d66526 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/drivers/i2c.c @@ -0,0 +1,50 @@ +#include "i2c.h" + +void I2C_clear(void) +{ + volatile uint32_t *i2c = (volatile uint32_t *)I2C_ADDRESS; + uint32_t cmd = (1 << 8); + + *i2c = cmd; +} + +void I2C_EnQ(uint8_t byte) +{ + volatile uint32_t *i2c = (volatile uint32_t *)I2C_ADDRESS; + + uint32_t cmd = (1 << 9) | (uint32_t)byte; + *i2c = cmd; +} + +void I2C_transmit(void) +{ + volatile uint32_t *i2c = (volatile uint32_t *)I2C_ADDRESS; + + uint32_t cmd = (1 << 10); + *i2c = cmd; +} + +void I2C_setReceive(uint8_t bytes) +{ + volatile uint32_t *i2c = (volatile uint32_t *)I2C_ADDRESS; + + uint32_t cmd = (1 << 12) | (uint32_t)bytes; + *i2c = cmd; +} + +void I2C_receive(void) +{ + volatile uint32_t *i2c = (volatile uint32_t *)I2C_ADDRESS; + + uint32_t cmd = (1 << 11); + *i2c = cmd; +} + +uint32_t I2C_DeQ(void) +{ + volatile uint32_t *i2c = (volatile uint32_t *)I2C_ADDRESS; + + uint32_t data = *i2c; + return data; +} + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/drivers/i2c.h b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/drivers/i2c.h new file mode 100755 index 0000000..eb06443 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/drivers/i2c.h @@ -0,0 +1,16 @@ +#ifndef __I2C_H__ +#define __I2C_H__ + +#include + +#define I2C_ADDRESS 0x90000000 + +void I2C_clear(void); +void I2C_EnQ(uint8_t byte); +void I2C_transmit(void); +void I2C_setReceive(uint8_t bytes); +void I2C_receive(void); +uint32_t I2C_DeQ(void); + +#endif + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/drivers/lcd.c b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/drivers/lcd.c new file mode 100755 index 0000000..082ca9f --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/drivers/lcd.c @@ -0,0 +1,155 @@ +#include /* For definition of 'NULL' */ +#include "lcd.h" +#include "os/lock.h" + +static volatile int LCD_lock_var = 0; +static uint8_t LCD_position = 0; +static uint8_t LCD_autoIncr = 1; + +static void LCD_incrPos(uint32_t amount) +{ + if (LCD_autoIncr == 0) { + return; + } + while (amount > 32) { + amount -= 32; + } + LCD_position += (uint8_t)amount; + if (LCD_position >= 32) { + LCD_position -= 32; + } +} + + +void LCD_clear(void) +{ + volatile uint32_t *LCD; + int i; + + LCD = (volatile uint32_t *)LCD_ADDRESS; + + for (i=0; i<8; i++) { + LCD[i] = 0x20202020; + } + LCD_position = 0; +} + +void LCD_setPos(uint8_t position) +{ + LCD_position = position; +} + +uint8_t LCD_getPos(void) +{ + return LCD_position; +} + +void LCD_setAutoIncr(uint8_t incr) +{ + LCD_autoIncr = incr; +} + +void LCD_lock(void) +{ + Lock(&LCD_lock_var, NULL, NULL); +} + +void LCD_unlock(void) +{ + Unlock(&LCD_lock_var); +} + +void LCD_printByte(uint8_t byte) +{ + volatile uint8_t *LCD; + + LCD = (volatile uint8_t *)(LCD_ADDRESS + LCD_position); + *LCD = byte; + LCD_incrPos(1); +} + +void LCD_printByteHex(uint8_t byte) +{ + volatile uint8_t *LCD; + uint8_t nibble_h, nibble_l; + + LCD = (volatile uint8_t *)(LCD_ADDRESS + LCD_position); + nibble_h = byte >> 4; + nibble_l = byte & 0x0f; + + if (nibble_h < 10) { + nibble_h += 48; + } + else { + nibble_h += 55; + } + if (nibble_l < 10) { + nibble_l += 48; + } + else { + nibble_h += 55; + } + *LCD = nibble_h; + LCD++; + *LCD = nibble_l; + LCD_incrPos(2); +} + +void LCD_printByteDec(uint8_t byte) +{ + volatile uint8_t *LCD; + uint8_t hundreds, tens, ones; + uint32_t n_printed = 1; + + LCD = (volatile uint8_t *)(LCD_ADDRESS + LCD_position); + hundreds = tens = ones = 48; + + while (byte >= 100) { + hundreds++; + byte -= 100; + } + while (byte >= 10) { + tens++; + byte -= 10; + } + while (byte >= 1) { + ones++; + byte -= 1; + } + if (hundreds > 48) { + *LCD = hundreds; + LCD++; + n_printed++; + } + if ((n_printed > 1) || (tens > 48)) { + *LCD = tens; + LCD++; + n_printed++; + } + *LCD = ones; + LCD_incrPos(n_printed); +} + +void LCD_printWord(uint32_t word) +{ + volatile uint32_t *LCD; + + LCD = (volatile uint32_t *)(LCD_ADDRESS + LCD_position); + *LCD = word; + LCD_incrPos(4); +} + +void LCD_printString(char *string) +{ + volatile char *LCD; + int i = 0; + + LCD = (volatile char *)(LCD_ADDRESS + LCD_position); + + while (string[i] != '\0') { + LCD[i] = string[i]; + i++; + } + LCD_incrPos(i); +} + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/drivers/lcd.h b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/drivers/lcd.h new file mode 100755 index 0000000..0a2acf1 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/drivers/lcd.h @@ -0,0 +1,21 @@ +#ifndef __LCD_H__ +#define __LCD_H__ + +#include + +#define LCD_ADDRESS 0x80000000 + +void LCD_clear(void); +void LCD_setPos(uint8_t position); +uint8_t LCD_getPos(void); +void LCD_setAutoIncr(uint8_t incr); +void LCD_lock(void); +void LCD_unlock(void); +void LCD_printByte(uint8_t byte); +void LCD_printByteHex(uint8_t byte); +void LCD_printByteDec(uint8_t byte); +void LCD_printWord(uint32_t word); +void LCD_printString(char *string); + +#endif + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/drivers/led.c b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/drivers/led.c new file mode 100755 index 0000000..5789236 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/drivers/led.c @@ -0,0 +1,25 @@ +#include "led.h" + +uint32_t LED_read(void) +{ + volatile uint32_t *LED = (volatile uint32_t *)LED_ADDRESS; + uint32_t data; + + data = *LED; + return data; +} + +void LED_write(uint32_t value) +{ + volatile uint32_t *LED = (volatile uint32_t *)LED_ADDRESS; + + *LED = value; +} + +void LED_setMode(uint32_t mode) +{ + volatile uint32_t *LED = (volatile uint32_t *)LED_ADDRESS; + + *LED = mode; +} + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/drivers/led.h b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/drivers/led.h new file mode 100755 index 0000000..b3c856a --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/drivers/led.h @@ -0,0 +1,21 @@ +#ifndef __LED_H__ +#define __LED_H__ + +#include + +#define LED_ADDRESS 0xC0000000 +#define LED_MODE_DATA 0x00000000 +#define LED_MODE_INTR 0x00004000 +#define LED_CENTER 0x00000100 +#define LED_WEST 0x00000200 +#define LED_SOUTH 0x00000400 +#define LED_EAST 0x00000800 +#define LED_NORTH 0x00001000 +#define LED_ERROR 0x00002000 + +uint32_t LED_read(void); +void LED_write(uint32_t data); +void LED_setMode(uint32_t mode); + +#endif + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/drivers/monitor.c b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/drivers/monitor.c new file mode 100755 index 0000000..6509ac4 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/drivers/monitor.c @@ -0,0 +1,33 @@ +#include "monitor.h" + +void Monitor_start(void) +{ + I2C_clear(); + I2C_EnQ(MONITOR_BUS_ADDR); + I2C_EnQ(0x40); // Configuration Register 1 + I2C_EnQ(0x1); // Enable monitoring + I2C_transmit(); +} + + +// Node is 0->Remote 1, 1->Local, 2->Remote 2 +uint32_t Monitor_readTemp(int node) +{ + uint8_t reg = 0x25 + node; + uint32_t data; + + // Set the read register + I2C_clear(); + I2C_EnQ(MONITOR_BUS_ADDR); + I2C_EnQ(reg); + I2C_transmit(); + + // Receive the register + I2C_EnQ(MONITOR_BUS_ADDR); + I2C_setReceive(1); + I2C_receive(); + data = I2C_DeQ(); + + return data; +} + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/drivers/monitor.h b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/drivers/monitor.h new file mode 100755 index 0000000..9177ce0 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/drivers/monitor.h @@ -0,0 +1,13 @@ +#ifndef __MONITOR_H__ +#define __MONITOR_H__ + +#include "i2c.h" + +#define MONITOR_BUS_ADDR 0x2C + +void Monitor_start(void); +uint32_t Monitor_readTemp(int node); + + +#endif + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/drivers/piezo.c b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/drivers/piezo.c new file mode 100755 index 0000000..97ffe11 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/drivers/piezo.c @@ -0,0 +1,19 @@ +#include "piezo.h" + +void Piezo_set(uint32_t count, int enable) +{ + volatile uint32_t *Piezo = (volatile uint32_t *)PIEZO_ADDRESS; + + if (enable) { + *Piezo = count | 0x1000000; + } + else { + *Piezo = count & ~0x1000000; + } +} + +void Piezo_play(uint32_t note) +{ + Piezo_set(note, 1); +} + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/drivers/piezo.h b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/drivers/piezo.h new file mode 100755 index 0000000..b59b1d5 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/drivers/piezo.h @@ -0,0 +1,43 @@ +#ifndef __PIEZO_H__ +#define __PIEZO_H__ + +#include + +#define PIEZO_ADDRESS 0xA0000000 + +/* Following are defined for a 100 MHz Piezo driver */ +#define C0 3058104 +#define C1 1529052 + +#define C4 191110 +#define C4s 180388 +#define D4f C4s +#define D4 170264 +#define D4s 160705 +#define E4f D4s +#define E4 151685 +#define F4 143172 +#define F4s 135138 +#define G4f F4s +#define G4 127551 +#define G4s 120395 +#define A4f G4s +#define A4 113636 +#define A4s 107259 +#define B4f A4s +#define B4 101239 +#define C5 95557 +#define C5s 90192 +#define D5f C5s +#define D5 85131 +#define D5s 80354 +#define E5f D5s +#define E5 75843 + +#define C8 11945 + + +void Piezo_set(uint32_t count, int enable); +void Piezo_play(uint32_t note); + +#endif diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/drivers/uart.c b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/drivers/uart.c new file mode 100755 index 0000000..3437c61 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/drivers/uart.c @@ -0,0 +1,38 @@ +#include "uart.h" + +void UART_disableBoot(void) +{ + volatile uint32_t *uart = (volatile uint32_t *)UART_ADDRESS; + uint32_t data; + + data = 0x00000100; + + *uart = data; +} + +uint8_t UART_readByte(void) +{ + volatile uint32_t *uart = (volatile uint32_t *)UART_ADDRESS; + uint32_t data; + + data = *uart; + + return (uint8_t)data; +} + +uint32_t UART_readMessage(void) +{ + volatile uint32_t *uart = (volatile uint32_t *)UART_ADDRESS; + + return *uart; +} + +void UART_writeByte(uint8_t byte) +{ + volatile uint32_t *uart = (volatile uint32_t *)UART_ADDRESS; + uint32_t data; + + data = (uint32_t)byte; + *uart = data; +} + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/drivers/uart.h b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/drivers/uart.h new file mode 100755 index 0000000..cf48a09 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/drivers/uart.h @@ -0,0 +1,14 @@ +#ifndef __UART_H__ +#define __UART_H__ + +#include + +#define UART_ADDRESS 0xB0000000 + +void UART_disableBoot(void); +uint8_t UART_readByte(void); +uint32_t UART_readMessage(void); +void UART_writeByte(uint8_t byte); + +#endif + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/os/boot.asm b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/os/boot.asm new file mode 100755 index 0000000..4b1fb06 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/os/boot.asm @@ -0,0 +1,75 @@ +############################################################################### +# TITLE: Boot Up Code +# AUTHOR: Grant Ayers (ayers@cs.utah.edu) +# DATE: 19 July 2011 +# FILENAME: boot.asm +# PROJECT: University of Utah XUM Single Core +# DESCRIPTION: +# Initializes the global pointer and stack pointer. +# Zeros BSS memory region and jumps to main(). +# +############################################################################### + + + .text + .balign 4 + .global boot + .ent boot + .set noreorder +boot: + la $t0, _bss_start # Defined in linker script + la $t1, _bss_end + la $sp, _sp + la $gp, _gp + +$bss_clear: + beq $t0, $t1, $cp0_setup # Loop until BSS is cleared + nop + sb $0, 0($t0) + j $bss_clear + addiu $t0, $t0, 1 + +$cp0_setup: + la $26, $run # Load the address of $run into + mtc0 $26, $30, 0 # the ErrorEPC + mfc0 $26, $13, 0 # Load Cause register + lui $27, 0x0080 # Use "special" interrupt vector + or $26, $26, $27 + mtc0 $26, $13, 0 # Commit new Cause register + mfc0 $26, $12, 0 # Load Status register + lui $27, 0x0fff # Disable access to Coprocessors + ori $27, $27, 0xffff + and $26, $26, $27 + lui $27, 0xffff # Enable, but mask all interrupts + ori $27, $27, 0x00ff + and $26, $26, $27 + ori $27, $0, 0x0001 # Base operating mode is Kernel + or $26, $26, $27 + mtc0 $26, $12, 0 # Commit new Status register + + #lui $26, 0x0000 # 1ms timer (50 MHz) + #ori $26, $26, 0xc350 + lui $26, 0x0007 # 10ms timer (50 MHz) + ori $26, $26, 0xa120 + #lui $26, 0x004c # 100ms timer (50 MHz) + #ori $26, $26, 0x4b40 + #lui $26, 0x00be # 250ms timer (50 MHz) + #ori $26, 0xbc20 + #lui $26, 0x017d # 500ms timer (50 MHz) + #ori $26, 0x7840 + #lui $26, 0x02fa # 1 sec timer (50 MHz) + #ori $26, $26, 0xf080 + mtc0 $26, $11, 0 # Set Compare register to timer value + + eret # Return from Reset Exception + +$run: + jal kernel + nop + +$done: + j $done + nop + + .end boot + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/os/exception_handler.c b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/os/exception_handler.c new file mode 100755 index 0000000..5dbf988 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/os/exception_handler.c @@ -0,0 +1,146 @@ +#include "drivers/lcd.h" +#include "drivers/piezo.h" +#include "drivers/monitor.h" +#include "drivers/uart.h" + +void dead_loop(void) +{ + for (;;) {} +} + +void mips32_handler_AdEL(void) +{ + LCD_clear(); + LCD_printString("AdEL"); + dead_loop(); +} + +void mips32_handler_AdES(void) +{ + LCD_clear(); + LCD_printString("AdES"); + dead_loop(); +} + +void mips32_handler_Bp(void) +{ + LCD_clear(); + LCD_printString("Bp"); + dead_loop(); +} + +void mips32_handler_CpU(void) +{ + LCD_clear(); + LCD_printString("CpU"); + dead_loop(); +} + +void mips32_handler_Ov(void) +{ + LCD_clear(); + LCD_printString("Ov"); + dead_loop(); +} + +void mips32_handler_RI(void) +{ + LCD_clear(); + LCD_printString("RI"); + dead_loop(); +} + +void mips32_handler_Sys(void) +{ + LCD_clear(); + LCD_printString("Sys"); + dead_loop(); +} + +void mips32_handler_Tr(void) +{ + LCD_clear(); + LCD_printString("Trap"); + dead_loop(); +} + +/* Timer is bypassed to scheduler in this demo */ +void mips32_handler_HwInt5(void) +{ +} + +void mips32_handler_HwInt4(void) +{ + static volatile char count = 0; + + LCD_printByte(count); + count++; +} + +void mips32_handler_HwInt3(void) +{ + static volatile char count = 0; + + LCD_printByte(count); + count++; +} + +void mips32_handler_HwInt2(void) +{ + static volatile char count = 0; + + LCD_printByte(count); + count++; +} + +void mips32_handler_HwInt1(void) +{ + static volatile char count = 0; + + LCD_printByte(count); + count++; +} + + +/* UART */ +void mips32_handler_HwInt0(void) +{ + uint32_t recv_msg; + uint32_t bytes_avail; + uint8_t read_byte; + + recv_msg = UART_readMessage(); + read_byte = (uint8_t)recv_msg; + bytes_avail = (recv_msg >> 8); + + while (bytes_avail > 0) { + if (read_byte == 0x7f) { // delete + LCD_setAutoIncr(0); + LCD_printByte(0x20); + LCD_setPos(LCD_getPos()-1); + LCD_setAutoIncr(1); + } + else { + LCD_printByte(read_byte); + } + bytes_avail--; + read_byte = UART_readByte(); + } +} + +void mips32_handler_SwInt1(void) +{ + static volatile char count = 0; + + LCD_printByte(count); + count++; +} + +void mips32_handler_SwInt0(void) +{ + static volatile char count = 0; + + LCD_printByte(count); + count++; +} + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/os/exception_handler.h b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/os/exception_handler.h new file mode 100755 index 0000000..01502fe --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/os/exception_handler.h @@ -0,0 +1,25 @@ +#ifndef __exception_handler_h__ +#define __exception_handler_h__ + +/* MIPS32 Exception Handlers */ +void mips32_handler_AdEL(void); +void mips32_handler_AdES(void); +void mips32_handler_Bp(void); +void mips32_handler_CpU(void); +void mips32_handler_Ov(void); +void mips32_handler_RI(void); +void mips32_handler_Sys(void); +void mips32_handler_Tr(void); + +/* MIPS32 Interrupt Handlers */ +void mips32_handler_HwInt5(void); +void mips32_handler_HwInt4(void); +void mips32_handler_HwInt3(void); +void mips32_handler_HwInt2(void); +void mips32_handler_HwInt1(void); +void mips32_handler_HwInt0(void); +void mips32_handler_SwInt1(void); +void mips32_handler_SwInt0(void); + +#endif + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/os/exceptions.asm b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/os/exceptions.asm new file mode 100755 index 0000000..de18b75 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/os/exceptions.asm @@ -0,0 +1,161 @@ +############################################################################### +# TITLE: Exception Vectors +# AUTHOR: Grant Ayers (ayers@cs.utah.edu) +# DATE: 23 May 2012 +# FILENAME: exceptions.asm +# PROJECT: University of Utah XUM Single Core +# DESCRIPTION: +# Provides the exception vectors which jump to +# exception-handling routines. +# +############################################################################### + + .text + .balign 4 + .set noreorder + +exc_save: + addiu $sp, $sp, -96 + sw $2, 0($sp) + sw $3, 4($sp) + sw $4, 8($sp) + sw $5, 12($sp) + sw $6, 16($sp) + sw $7, 20($sp) + sw $8, 24($sp) + sw $9, 28($sp) + sw $10, 32($sp) + sw $11, 36($sp) + sw $12, 40($sp) + sw $13, 44($sp) + sw $14, 48($sp) + sw $15, 52($sp) + sw $16, 56($sp) + sw $17, 60($sp) + sw $18, 64($sp) + sw $19, 68($sp) + sw $20, 72($sp) + sw $21, 76($sp) + sw $22, 80($sp) + sw $23, 84($sp) + sw $24, 88($sp) + jr $ra + sw $25, 92($sp) + +exc_restore: + lw $2, 0($sp) + lw $3, 4($sp) + lw $4, 8($sp) + lw $5, 12($sp) + lw $6, 16($sp) + lw $7, 20($sp) + lw $8, 24($sp) + lw $9, 28($sp) + lw $10, 32($sp) + lw $11, 36($sp) + lw $12, 40($sp) + lw $13, 44($sp) + lw $14, 48($sp) + lw $15, 52($sp) + lw $16, 56($sp) + lw $17, 60($sp) + lw $18, 64($sp) + lw $19, 68($sp) + lw $20, 72($sp) + lw $21, 76($sp) + lw $22, 80($sp) + lw $23, 84($sp) + lw $24, 88($sp) + lw $25, 92($sp) + jr $ra + addiu $sp, $sp, 96 + + + .global mips32_general_exception + .ent mips32_general_exception +mips32_general_exception: + or $26, $0, $ra + jal exc_save + nop + mfc0 $27, $13, 0 # Read Cause which has ExcCode bits + srl $27, $27, 2 # Extract exception code to $k1 + andi $27, $27, 0x001f + + la $ra, $end_exception # Jump to the appropriate handler + addiu $t0, $0, 4 + addiu $t1, $0, 5 + addiu $t2, $0, 8 + addiu $t3, $0, 9 + beq $t0, $27, mips32_handler_AdEL + addiu $t0, $0, 10 + beq $t1, $27, mips32_handler_AdES + addiu $t1, $0, 11 + beq $t2, $27, mips32_handler_Sys + addiu $t2, $0, 12 + beq $t3, $27, mips32_handler_Bp + addiu $t3, $0, 13 + beq $t0, $27, mips32_handler_RI + nop + beq $t1, $27, mips32_handler_CpU + nop + beq $t2, $27, mips32_handler_Ov + nop + beq $t3, $27, mips32_handler_Tr + nop + +$end_exception: + jal exc_restore + xor $27, $0, $0 + or $ra, $0, $26 + xor $26, $0, $0 + eret + .end mips32_general_exception + + + +### "Special" Interrupt Vector: Cause_IV must be set. + + .ent mips32_interrupt_exception + .global mips32_interrupt_exception +mips32_interrupt_exception: + mfc0 $26, $12, 0 # Status register for IM bits + mfc0 $27, $13, 0 # Cause register for IP bits + and $26, $26, $27 # Extract pending, unmasked interrupts + srl $26, $26, 8 + andi $26, $26, 0x00ff + + clz $26, $26 + addiu $27, $0, 24 + beq $26, $27, scheduler # Hw Int 5 goes directly to scheduler + nop + + addu $27, $0, $ra + jal exc_save + nop + la $ra, $end_interrupt + addiu $t0, $0, 25 + addiu $t1, $0, 26 + addiu $t2, $0, 27 + beq $26, $t0, mips32_handler_HwInt4 + addiu $t0, $0, 28 + beq $26, $t1, mips32_handler_HwInt3 + addiu $t1, $0, 29 + beq $26, $t2, mips32_handler_HwInt2 + addiu $t2, $0, 30 + beq $26, $t0, mips32_handler_HwInt1 + addiu $t0, $0, 31 + beq $26, $t1, mips32_handler_HwInt0 + nop + beq $26, $t2, mips32_handler_SwInt1 + nop + beq $26, $t0, mips32_handler_SwInt0 + nop + +$end_interrupt: + jal exc_restore + xor $27, $0, $0 + or $ra, $0, $26 + xor $26, $0, $0 + eret + .end mips32_interrupt_exception + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/os/kernel.asm b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/os/kernel.asm new file mode 100755 index 0000000..f68d5a2 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/os/kernel.asm @@ -0,0 +1,218 @@ +############################################################################### +# TITLE: Thread kernel demo +# AUTHOR: Grant Ayers (ayers@cs.utah.edu) +# DATE: 30 June 2012 +# FILENAME: kernel.asm +# PROJECT: University of Utah XUM Single Core +# DESCRIPTION: +# Switches between 8 simultaneously-running threads. +# Demonstrates interrupts and llsc atomic operations. +# +############################################################################### + + + .text + .balign 4 + .global kernel + .ent kernel + .set noreorder + .set noat +kernel: + addiu $sp, $sp, -1152 # Room for 9*32 registers + + # Set the stack pointer ($29) for each of 8 threads + lui $t0, 0x0007 + ori $t0, $t0, 0x4000 + sw $t0, 1140($sp) + addiu $t0, $t0, 0x4000 + sw $t0, 1012($sp) + addiu $t0, $t0, 0x4000 + sw $t0, 884($sp) + addiu $t0, $t0, 0x4000 + sw $t0, 756($sp) + addiu $t0, $t0, 0x4000 + sw $t0, 628($sp) + addiu $t0, $t0, 0x4000 + sw $t0, 500($sp) + addiu $t0, $t0, 0x4000 + sw $t0, 372($sp) + addiu $t0, $t0, 0x4000 + sw $t0, 244($sp) + + # Set the global pointer ($28) for each of 8 threads + sw $gp, 240($sp) + sw $gp, 368($sp) + sw $gp, 496($sp) + sw $gp, 624($sp) + sw $gp, 752($sp) + sw $gp, 880($sp) + sw $gp, 1008($sp) + sw $gp, 1136($sp) + + # Set the EPC for each of 8 threads to start at main + lui $t0, main + ori $t0, $t0, main + sw $t0, 128($sp) + sw $t0, 256($sp) + sw $t0, 384($sp) + sw $t0, 512($sp) + sw $t0, 640($sp) + sw $t0, 768($sp) + sw $t0, 896($sp) + sw $t0, 1024($sp) + + sw $zero, 0($sp) # Current thread stored in 0($sp) + mfc0 $k0, $12, 0 # Enable timer interrupt + ori $k0, $k0, 0x8000 + mtc0 $k0, $12, 0 + +$wait: + j $wait # Wait for interrupt to begin schedule + nop + .end kernel + + + + + .global scheduler + .ent scheduler +scheduler: + addu $k0, $0, $sp # Recover the kernel stack pointer + la $sp, _sp + addiu $sp, $sp, -1152 + sw $25, 4($sp) # Free four registers for use + sw $28, 8($sp) + sw $30, 12($sp) + sw $31, 16($sp) + lw $k1, 0($sp) # Current TID to k1 + beq $k1, $zero, $skip_save # Don't save kernel's registers + nop + jal save_registers + nop +$skip_save: + lw $t0, 0($sp) # Increment TID + addiu $t0, $t0, 1 + addiu $t1, $zero, 9 # Move TID back to 1 if it reaches 9 + beq $t0, $t1, $reset_tid + nop +$tid_done: + sw $t0, 0($sp) + jal restore_registers # Load registers for next thread + nop + la $k1, _sp # Recover kernel stack pointer again + addiu $k1, $k1, -1152 + lw $k1, 0($k1) # Load TID to k1 for main function + mfc0 $26, $9, 0 # Read Count to clear timer interrupt + eret # Run thread +$reset_tid: + addiu $t0, $zero, 1 + j $tid_done + nop + .end scheduler + + +save_registers: + # Requires: k0 hold thread stack pointer + # k1 holds TID + # sp points to kernel stack + # Destroys: + + # Find offset for register table in kernel space + addiu $25, $zero, 128 + mul $25, $25, $k1 + addu $25, $25, $sp + + # Store thread stack pointer + sw $k0, 116($25) + addu $k0, $0, $25 + + # Store EPC from CP0 + mfc0 $25, $14, 0 + sw $25, 0($k0) + + # Store remaining registers + sw $1, 4($k0) + sw $2, 8($k0) + sw $3, 12($k0) + sw $4, 16($k0) + sw $5, 20($k0) + sw $6, 24($k0) + sw $7, 28($k0) + sw $8, 32($k0) + sw $9, 36($k0) + sw $10, 40($k0) + sw $11, 44($k0) + sw $12, 48($k0) + sw $13, 52($k0) + sw $14, 56($k0) + sw $15, 60($k0) + sw $16, 64($k0) + sw $17, 68($k0) + sw $18, 72($k0) + sw $19, 76($k0) + sw $20, 80($k0) + sw $21, 84($k0) + sw $22, 88($k0) + sw $23, 92($k0) + sw $24, 96($k0) + lw $25, 4($sp) + sw $25, 100($k0) + lw $28, 8($sp) + sw $28, 112($k0) + lw $30, 12($sp) + sw $30, 120($k0) + addu $k1, $0, $31 + lw $31, 16($sp) + sw $31, 124($k0) + jr $k1 + nop + + +restore_registers: + # Requires: t0 specifies which thread (1-8) + # sp points to kernel stack + # Destroys: All registers + + # Find offset for register table in kernel space + addiu $k1, $zero, 128 + mul $k0, $t0, $k1 + addu $k0, $k0, $sp + + + # Load EPC to CP0 + lw $k1, 0($k0) + mtc0 $k1, $14, 0 + # Load remaining registers + lw $1, 4($k0) + lw $2, 8($k0) + lw $3, 12($k0) + lw $4, 16($k0) + lw $5, 20($k0) + lw $6, 24($k0) + lw $7, 28($k0) + lw $8, 32($k0) + lw $9, 36($k0) + lw $10, 40($k0) + lw $11, 44($k0) + lw $12, 48($k0) + lw $13, 52($k0) + lw $14, 56($k0) + lw $15, 60($k0) + lw $16, 64($k0) + lw $17, 68($k0) + lw $18, 72($k0) + lw $19, 76($k0) + lw $20, 80($k0) + lw $21, 84($k0) + lw $22, 88($k0) + lw $23, 92($k0) + lw $24, 96($k0) + lw $25, 100($k0) + lw $28, 112($k0) + lw $29, 116($k0) + lw $30, 120($k0) + addu $k1, $0, $31 + lw $31, 124($k0) + jr $k1 + nop + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/os/lock.c b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/os/lock.c new file mode 100755 index 0000000..4058d11 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/os/lock.c @@ -0,0 +1,86 @@ +#include /* only for NULL */ +#include "lock.h" + +void Lock(volatile int *lock, int *load_count, int *store_count) +{ + int l_tries = 0; + int s_tries = 0; + + asm volatile( + ".set noreorder\n\t" + "addiu $8, $0, 1\n\t" + "addu %[l_tries], $0, $0\n\t" + "addu %[s_tries], $0, $0\n\t" + "1:\n\t" + "ll $9, %[lock]\n\t" + "bne $9, $0, 1b\n\t" + "addiu %[l_tries], %[l_tries], 1\n\t" + "sc $8, %[lock]\n\t" + "beq $8, $0, 1b\n\t" + "addiu %[s_tries], %[s_tries], 1\n\t" + ".set reorder\n\t" + : [l_tries] "=&r"(l_tries), [s_tries] "=&r"(s_tries), + [lock] "+m"(*lock) + : + : "$8", "$9", "memory" + ); + + if (load_count != NULL) { + *load_count = l_tries; + } + if (store_count != NULL) { + *store_count = s_tries; + } +} + +void LockAlmost(volatile int *lock, int *load_count, int *store_count) +{ + int l_tries = 0; + int s_tries = 0; + + asm volatile( + ".set noreorder\n\t" + "addiu $8, $0, 1\n\t" + "addu %[l_tries], $0, $0\n\t" + "addu %[s_tries], $0, $0\n\t" + "1:\n\t" + "ll $9, %[lock]\n\t" + "bne $9, $0, 1b\n\t" + "addiu %[l_tries], %[l_tries], 1\n\t" + + "nop\n\t" + "nop\n\t" + + "sc $8, %[lock]\n\t" + "addiu %[s_tries], %[s_tries], 1\n\t" + ".set reorder\n\t" + : [l_tries] "=&r"(l_tries), [s_tries] "=&r"(s_tries), + [lock] "+m"(*lock) + : + : "$8", "$9", "memory" + ); + + if (load_count != NULL) { + *load_count = l_tries; + } + if (store_count != NULL) { + *store_count = s_tries; + } +} + + +void LockNull(volatile int *lock, int *load_count, int *store_count) +{ + if (load_count != NULL) { + *load_count = 1; + } + if (store_count != NULL) { + *store_count = 1; + } +} + +void Unlock(volatile int *lock) +{ + *lock = 0; +} + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/os/lock.h b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/os/lock.h new file mode 100755 index 0000000..6c51360 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/os/lock.h @@ -0,0 +1,10 @@ +#ifndef __LOCK_H__ +#define __LOCK_H__ + +void Lock(volatile int *lock, int *load_count, int *store_count); +void LockAlmost(volatile int *lock, int *load_count, int *store_count); +void LockNull(volatile int *lock, int *load_count, int *store_count); +void Unlock(volatile int *lock); + +#endif + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/os/vectors.asm b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/os/vectors.asm new file mode 100755 index 0000000..dd455bc --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/os/vectors.asm @@ -0,0 +1,39 @@ +############################################################################### +# TITLE: Exception Vectors +# AUTHOR: Grant Ayers (ayers@cs.utah.edu) +# DATE: 23 May 2012 +# FILENAME: exceptions.asm +# PROJECT: University of Utah XUM Single Core +# DESCRIPTION: +# Provides the exception vectors which jump to +# exception-handling routines. +# +############################################################################### + + +# Current setup: +# 1. The exception vector begins at address 0x0. +# 2. The interrupt vector begins at address 0x8. +# 3. Each vector has room for 2 instructions (8 bytes) with which +# it must jump to its demultiplexing routine. The demultiplexing +# routine calls individual exception-specific handlers. +# 4. The linker script must ensure that this code is placed at the +# correct address. + + + .text + .balign 4 + .ent exception_vector + .set noreorder +exception_vector: + j mips32_general_exception + nop + .end exception_vector + + + .ent interrupt_vector +interrupt_vector: + j mips32_interrupt_exception + nop + .end interrupt_vector + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/os/xum.ls b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/os/xum.ls new file mode 100755 index 0000000..ca9ea04 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/XD5_Threads/src/os/xum.ls @@ -0,0 +1,83 @@ +/* Linker script for MIPS32 (Single Core) FPGA, intended for XUM */ + + +/* Entry Point + * + * Set it to be the label "boot" (likely in boot.asm) + * + */ +/*ENTRY(boot)*/ + + +/* Memory Section + * + * The FPGA currently uses one region of Block RAM, which is 592 KB. + * + * Instruction Memory starts at address 0. + * + * Data Memory ends 592KB later, at address 0x00094000 (the last + * usable word address is 0x00093ffc). + * + * Instructions : 0x00000000 -> 0x0000fffc ( 64KB) + * Data / BSS : 0x00001000 -> 0x00017ffc ( 32KB) + * Stack / Heap : 0x00018000 -> 0x00093ffc (496KB) + * + * + */ + +/* Sections + * + */ + +SECTIONS +{ + _sp = 0x00094000; + + . = 0 ; + + .text : + { + vectors.o(.text) + . = 0x10 ; + boot.o(.text) + exceptions.o(.text) + *(.*text*) + } + + . = 0x00001000 ; + + .data : + { + *(.rodata*) + *(.data*) + } + + _gp = ALIGN(16) + 0x7ff0; + + .got : + { + *(.got) + } + + .sdata : + { + *(.*sdata*) + } + + _bss_start = . ; + + .sbss : + { + *(.*sbss) + } + + .bss : + { + *(.*bss) + } + + _bss_end = . ; + +} + + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/util/bintohex.c b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/util/bintohex.c new file mode 100755 index 0000000..4674c3e --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/util/bintohex.c @@ -0,0 +1,178 @@ +/* + * File : bintohex.c + * Project : University of Utah, XUM Project + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 4-1-2011 GEA Initial design. + * + * Standards/Formatting: + * C, 8 hard tab, 80 column + * + * Description: + * Converts binary data into human-readable hex data. + * This is useful for FPGA block RAM initialization data, + * which is typically read in from a file in hex format. + * For block RAM cores, a .COE file is required, which is + * basically a hex file with some additional syntax. This + * utility will output in either format and can pad with + * zeros to a certain length. + */ +#include +#include +#include + + +void usage(void); +unsigned int doEndian(unsigned int val, int bigEndian); + +int main(int argc, char **argv) +{ + FILE *file; + char *i_name, *o_name; + int i_size; + unsigned int *input; + unsigned int data = 0; + int pad_length = 0; + int endian = -1; + int coe = 0; + int ch, i; + + while ((ch = getopt(argc, argv, "chbp:")) != -1) + { + switch (ch) + { + case 'c': + coe = 1; + break; + case 'h': + usage(); + break; + case 'b': + endian = 1; + break; + case 'p': + pad_length = (int)strtol(optarg, + (char **)NULL, 10); + break; + default: + usage(); + } + } + + argc -= optind; + argv += optind; + + if (argc != 2) + { + usage(); + } + + i_name = argv[0]; + o_name = argv[1]; + + + /* Read the input file */ + file = fopen(i_name, "rb"); + if (file == NULL) { + fprintf(stderr, "Error: Could not open \"%s\".\n", i_name); + exit(1); + } + fseek(file, 0L, SEEK_END); + i_size = (int)ftell(file); + if ((i_size < 0) || (ftell(file) > (long)i_size)) { + fprintf(stderr, "Error: Input file is too large.\n"); + exit(1); + } + fseek(file, 0L, SEEK_SET); + input = (unsigned int*)malloc(i_size); + if (input == NULL) { + fprintf(stderr, "Error: Could not allocate %d bytes of " + "memory.\n", i_size); + exit(1); + } + if (fread(input, 1, i_size, file) != i_size) { + fprintf(stderr, "Error reading input file.\n"); + exit(1); + } + fclose(file); + + /* Write the output file */ + file = fopen(o_name, "wb+"); + if (file == NULL) { + fprintf(stderr, "Error: Could not open \"%s\" for " + "writing.\n", o_name); + exit(1); + } + if (coe) { + fprintf(file, "memory_initialization_radix=16;\n" + "memory_initialization_vector=\n"); + } + for (i=0; i<(i_size/4); i++) { + if (i != 0) { + if (coe) { + fprintf(file, ",\n"); + } + else { + fprintf(file, "\n"); + } + } + fprintf(file, "%08x", doEndian(input[i], endian)); + } + if (coe) { + fprintf(file, ";\n"); + } + else { + fprintf(file, "\n"); + } + for (i=((i_size/4)*4); i<(i_size); i++) { + if (endian < 0) { + data <<= 8; + data |= (0x000000FF & ((char*)input)[i]); + } + else { + data >>= 8; + data |= (0xFF000000 & (((char*)input)[i] << 24)); + } + } + if ((i_size%4) != 0) { + if (coe) { + fprintf(file, "%08x;\n", data); + } + else { + fprintf(file, "%08x\n", data); + } + } + + /* Pad the output for non-COE files */ + if ((pad_length > 0) && !coe) { + ch = (i_size/4) + (((i_size%4) != 0) ? 1 : 0); + for (i=ch; i] [-b (Big Endian)] " + "[-c (Make COE file)] \n"); + exit(1); +} + +unsigned int doEndian(unsigned int val, int bigEndian) +{ + if (bigEndian == 1) { + return (((val >> 24)&0xff) | ((val<<8)&0xff0000) | + ((val>>8)&0xff00) | ((val<<24)&0xff000000)); + } + else { + return val; + } +} + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/util/bintohex.exe b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/util/bintohex.exe new file mode 100755 index 0000000..0e35dc7 Binary files /dev/null and b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/util/bintohex.exe differ diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/util/bintoxum.c b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/util/bintoxum.c new file mode 100755 index 0000000..94d2945 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/util/bintoxum.c @@ -0,0 +1,150 @@ +/* + * File : bintoxum.c + * Project : University of Utah, XUM Project + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 7-3-2012 GEA Initial Design. + * + * Standards/Formatting: + * C, 8 hard tab, 80 column + * + * Description: + * Combines the text (instruction) and data sections of an + * executable into one file. You can think of this as a very + * simple version of ELF or a.out files. + * + * The XUM processor has a simple flat physical address space + * which contains instructions and data. The output file from + * this utility is directly loadable into this memory, byte-for-byte, + * without using any kind of "intelligent" loader. It takes two + * binary input files, the instructions and data, and an offset + * address (decimal) for the data segment to begin, and outputs + * a file which can be sent directly to hardware via the XUM + * bootloader or other means. + */ +#include +#include +#include +#include + +void usage(void); +void read_file(char *name, int *size, char **buf); + +int main(int argc, char **argv) +{ + FILE *file; + char *it_name, *id_name, *o_name; + int it_size, id_size; + char *it_buf, *id_buf; + int data_start_addr; + int pad; + int ch; + + while ((ch = getopt(argc, argv, "d:")) != -1) { + switch (ch) { + case 'd': + data_start_addr = (int)strtol(optarg, + (char **)NULL, 10); + break; + default: + usage(); + } + } + + argc -= optind; + argv += optind; + + if (argc != 3) { + usage(); + } + + it_name = argv[0]; + id_name = argv[1]; + o_name = argv[2]; + + read_file(it_name, &it_size, &it_buf); + read_file(id_name, &id_size, &id_buf); + + /* Open the output file */ + file = fopen(o_name, "wb+"); + if (file == NULL) { + fprintf(stderr, "Error: Could not open \"%s\" for " + "writing.\n", o_name); + exit(1); + } + + /* Copy text segment directly to output file */ + if (fwrite((void *)it_buf, 1, it_size, file) != it_size) { + fprintf(stderr, "Error writing to output file.\n"); + exit(1); + } + + /* Pad until the data segment */ + it_buf[0] = 0; + while (it_size < data_start_addr) { + if (fwrite((void *)it_buf, 1, 1, file) != 1) { + fprintf(stderr, "Error writing to output file.\n"); + exit(1); + } + it_size++; + } + + /* Copy data segment to output file */ + if (fwrite((void *)id_buf, 1, id_size, file) != id_size) { + fprintf(stderr, "Error writing to output file.\n"); + exit(1); + } + + /* Pad the data section to word length if needed */ + /* NOTE: Assumes only padding needed would be at the end. */ + pad = ((id_size % 4) != 0) ? 4 - (id_size % 4) : 0; + if (pad != 0) { + memset((void *)id_buf, 0, 4); + if (fwrite((void *)id_buf, 1, pad, file) != pad) { + fprintf(stderr, "Error writing to output file.\n"); + exit(1); + } + } + + fclose(file); + + return 0; +} + +void usage(void) +{ + fprintf(stderr, "Usage: bintoxum [-d data start address] " + " \n"); + exit(1); +} + +void read_file(char *name, int *size, char **buf) +{ + FILE *file; + + file = fopen(name, "rb"); + if (file == NULL) { + fprintf(stderr, "Error: Could not open \"%s\".\n", name); + exit(1); + } + fseek(file, 0L, SEEK_END); + *size = (int)ftell(file); + if ((*size < 0) || (ftell(file) > (long)*size)) { + fprintf(stderr, "Error: Input file is too large.\n"); + exit(1); + } + fseek(file, 0L, SEEK_SET); + *buf = (char *)malloc(*size); + if (*buf == NULL) { + fprintf(stderr, "Error: Could not allocate %d bytes " + "of memory.\n", *size); + exit(1); + } + if (fread(*buf, 1, *size, file) != *size) { + fprintf(stderr, "Error reading input file.\n"); + exit(1); + } + fclose(file); +} diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/util/bintoxum.exe b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/util/bintoxum.exe new file mode 100755 index 0000000..21dbd2a Binary files /dev/null and b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/util/bintoxum.exe differ diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/util/ram_image.c b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/util/ram_image.c new file mode 100755 index 0000000..9018c98 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/util/ram_image.c @@ -0,0 +1,196 @@ +/* + * File : ram_image.c + * Project : University of Utah, XUM Project + * Creator(s) : Grant Ayers (ayers@cs.utah.edu) + * + * Modification History: + * Rev Date Initials Description of Change + * 1.0 7-8-2011 GEA Initial design. + * + * Standards/Formatting: + * C, 8 hard tab, 80 column + * + * Description: + * Fills a specific type of Verilog file which contains a + * Block RAM primitive with the initialization vectors from + * 'code.txt' and outputs 'imem_filled.v'. + * + * This utility is useful for filling simple and small block + * RAMs, especially for basic simulations. However it is no + * longer used for the production XUM project. + */ +#include +#include +#include + +void quit(int val); +int inject(char* vectors, char* output); + +FILE* verilog; +FILE* vectors; +FILE* output; +char* out_buf = NULL; +char* vec_buf = NULL; + +int main(int argc, char* argv[]) +{ + int verilog_size, vectors_size; + int inst_written; + + + if (argc < 4) + { + fprintf(stderr, "Usage: %s: \n", argv[0]); + fprintf(stderr, "Usage: %s: ram_xilinx.v code.txt ram_image.v\n", argv[0]); + quit(1); + } + + /* Open the Verilog source file and copy it into a buffer */ + verilog = fopen(argv[1], "rb"); + if (!verilog) + { + fprintf(stderr, "Could not open \"%s\".\n", argv[1]); + quit(1); + } + fseek(verilog, 0L, SEEK_END); + verilog_size = ftell(verilog); + fseek(verilog, 0L, SEEK_SET); + if (verilog_size == 0) + { + fprintf(stderr, "Error: Empty verilog input file.\n"); + quit(1); + } + out_buf = malloc(verilog_size); + if (!out_buf) + { + fprintf(stderr, "Error allocating memory.\n"); + quit(1); + } + if (fread(out_buf, 1, verilog_size, verilog) != verilog_size) + { + fprintf(stderr, "Error reading input file.\n"); + quit(1); + } + + + /* Open code vectors and copy them into a buffer */ + vectors = fopen(argv[2], "rb"); + if (!vectors) + { + fprintf(stderr, "Could not open \"%s\".\n", argv[2]); + quit(1); + } + fseek(vectors, 0L, SEEK_END); + vectors_size = ftell(vectors); + fseek(vectors, 0L, SEEK_SET); + if (vectors_size == 0) + { + fprintf(stderr, "Error: Empty vectors file.\n"); + quit(1); + } + //printf("Vectors size is %d bytes.\n", vectors_size); + vec_buf = malloc(vectors_size+1); + if (!vec_buf) + { + fprintf(stderr, "Error allocating memory.\n"); + quit(1); + } + if (fread(vec_buf, 1, vectors_size, vectors) != vectors_size) + { + fprintf(stderr, "Error reading vectors file.\n"); + quit(1); + } + vec_buf[vectors_size] = '\0'; + + /* Inject code */ + inst_written = inject(vec_buf, out_buf); + printf("Wrote %d instructions.\n", inst_written); + + /* Write output file */ + output = fopen(argv[3], "wb"); + if (output == NULL) + { + fprintf(stderr, "Error writing %s!\n", argv[3]); + quit(1); + } + fwrite(out_buf, 1, verilog_size, output); + fclose(output); + + + // Exit + quit(0); + return 0; +} + + +int inject(char* vectors, char* output) +{ + const char* delimeters = " \t\r\n"; + char row_key[15]; // ".INIT_XX(256'h" + char* token; + char* position; + int row = 0; + int col = 7; + int total = 0; + + token = strtok(vectors, delimeters); + snprintf(row_key, 14, ".INIT_%02X(256'h", row); + while ((token != NULL) && (row < 128)) + { + //printf("Got a token: \"%s\"\n", token); + if (strlen(token) != 8) + { + fprintf(stderr, "Error: Vector \"%s\" is not " + "a 32-bit hexadecimal number.\n", token); + quit(1); + } + position = strstr(output, row_key); + if (position == NULL) + { + fprintf(stderr, "Error: Could not find initialization " + "row %02X (hex) in the Block RAM. Check that " + "it has sufficient memory.\n", row); + printf("\n\n\nDEBUG\n%s\n", output); + quit(1); + } + //position += (14 + col + (8 * col)); + position += (14 + (8 * col)); + memcpy(position, token, 8); + total++; + col--; + if (col < 0) + { + col = 7; + row++; + snprintf(row_key, 14, ".INIT_%02X(256'h", row); + } + //printf("Col is %d row is %d\n", col, row); + token = strtok(NULL, delimeters); + } + return total; +} + + +void quit(int val) +{ + if (verilog) { + fclose(verilog); + } + if (vectors) { + fclose(vectors); + } + if (output) { + fclose(output); + } + if (out_buf) { + free(out_buf); + } + if (vec_buf) { + free(vec_buf); + } + + if (val != 0) { + exit(val); + } +} + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/util/ram_image.exe b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/util/ram_image.exe new file mode 100755 index 0000000..0ea3dd1 Binary files /dev/null and b/demo_chip_rtl/rtl/mips32r1/trunk/Software/demos/util/ram_image.exe differ diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/toolchain/Toolchain_Instructions b/demo_chip_rtl/rtl/mips32r1/trunk/Software/toolchain/Toolchain_Instructions new file mode 100755 index 0000000..d7d2ba8 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/toolchain/Toolchain_Instructions @@ -0,0 +1,69 @@ +Instructions for Creating a MIPS Compiler Toolchain +--------------------------------------------------- + +These are instructions for creating a MIPS cross-compiler toolchain based on +GCC 4.7.1, Binutils 2.21, and Newlib 1.20.0. + + +Required Files +-------------- + + - binutils-2.21.tar.bz2 (http://ftp.gnu.org/gnu/binutils/) + - gcc-4.7.1.tar.bz2 (http://gcc.gnu.org/mirrors.html) + - mpfr-3.0.1.tar.bz2 (http://www.mpfr.org/mpfr-3.0.1/) + - mpc-0.9.tar.gz (http://www.multiprecision.org/) + - gmp-5.0.5.tar.bz2 (http://gmplib.org/) + - newlib-1.20.0.tar.gz (ftp://sources.redhat.com/pub/newlib/index.html) + + +Procedure +--------- + +The following assumes you are using Bash or Bash-like shell. This procedure +has been tested in Linux environments as well as Windows under Cygwin. If you +are using Cygwin, you must be running on a 32-bit Windows OS or VM. +Limitations with WoW in 64-bit Windows prevents enough stack/heap space from +being allocated. Once the toolchain is compiled it may be used under 64-bit +Windows. + + +1. Set environment variables: + export TARGET=mips-elf + export PREFIX=[some directory]/gnu_mips/crosstools + export PATH=$PATH:$PREFIX/bin + +1.5. If you're on 32-bit Windows using Cygwin: + export CFLAGS="-Wl,--heap,200000000,--stack,8000000" + +2. Unpack everything: + bzip2 -dc binutils-2.21.tar.bz2 | tar xf - + bzip2 -dc gcc-4.7.1.tar.bz2 | tar xf - + bzip2 -dc mpfr-3.0.1.tar.bz2 | tar xf - + bzip2 -dc gmp-5.0.5.tar.bz2 | tar xf - + gzip -dc mpc-0.9.tar.gz | tar xf - + gzip -dc newlib-1.20.0.tar.gz | tar xf - + +3. Move (or symlink) GCC dependency packages + mv gmp-5.0.5 gcc-4.7.1/gmp + mv mpc-0.9 gcc-4.7.1/mpc + mv mpfr-3.0.1 gcc-4.7.1/mpfr + mv newlib-1.20.0/newlib gcc-4.7.1/newlib + mv newlib-1.20.0/libgloss gcc-4.7.1/libgloss + +4. Build binutils: + mkdir binutils-build && cd binutils-build + ../binutils-2.21/configure --prefix=$PREFIX --target=$TARGET --disable-nls + make + make install + cd .. + +5. Build gcc: + mkdir gcc-build && cd gcc-build + ../gcc-4.7.1/configure --prefix=$PREFIX --target=$TARGET --with-newlib \ + --without-headers --with-gnu-ld --with-gnu-as --disable-libssp \ + --disable-nls --enable-c99 --enable-long-long --enable-languages=c + make + make install + cd .. + +At this point you have a complete toolchain located at $PREFIX. \ No newline at end of file diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/toolchain/binutils-2.21.tar.bz2 b/demo_chip_rtl/rtl/mips32r1/trunk/Software/toolchain/binutils-2.21.tar.bz2 new file mode 100755 index 0000000..06a8fa8 Binary files /dev/null and b/demo_chip_rtl/rtl/mips32r1/trunk/Software/toolchain/binutils-2.21.tar.bz2 differ diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/toolchain/gcc-4.7.1.tar.bz2 b/demo_chip_rtl/rtl/mips32r1/trunk/Software/toolchain/gcc-4.7.1.tar.bz2 new file mode 100755 index 0000000..ff66b6c Binary files /dev/null and b/demo_chip_rtl/rtl/mips32r1/trunk/Software/toolchain/gcc-4.7.1.tar.bz2 differ diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/toolchain/gmp-5.0.5.tar.bz2 b/demo_chip_rtl/rtl/mips32r1/trunk/Software/toolchain/gmp-5.0.5.tar.bz2 new file mode 100755 index 0000000..42af0ef Binary files /dev/null and b/demo_chip_rtl/rtl/mips32r1/trunk/Software/toolchain/gmp-5.0.5.tar.bz2 differ diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/toolchain/mpc-0.9.tar.gz b/demo_chip_rtl/rtl/mips32r1/trunk/Software/toolchain/mpc-0.9.tar.gz new file mode 100755 index 0000000..8cb6d04 Binary files /dev/null and b/demo_chip_rtl/rtl/mips32r1/trunk/Software/toolchain/mpc-0.9.tar.gz differ diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/toolchain/mpfr-3.0.1.tar.bz2 b/demo_chip_rtl/rtl/mips32r1/trunk/Software/toolchain/mpfr-3.0.1.tar.bz2 new file mode 100755 index 0000000..1b02dd5 Binary files /dev/null and b/demo_chip_rtl/rtl/mips32r1/trunk/Software/toolchain/mpfr-3.0.1.tar.bz2 differ diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/toolchain/newlib-1.20.0.tar.gz b/demo_chip_rtl/rtl/mips32r1/trunk/Software/toolchain/newlib-1.20.0.tar.gz new file mode 100755 index 0000000..cce6d27 Binary files /dev/null and b/demo_chip_rtl/rtl/mips32r1/trunk/Software/toolchain/newlib-1.20.0.tar.gz differ diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/README b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/README new file mode 100755 index 0000000..fe066f6 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/README @@ -0,0 +1,48 @@ +XUM Bootloader version 1.01 Readme +---------------------------------- + +Contents: +--------- + + README - This file + + programmer/ - A C# Windows application for interfacing with a XUM device + win32_installer/ - A binary installer + win32_source/ - Visual Studio 2010 source project + + +Programmer Description: +----------------------- + + Implements programming software to interface with a XUM device over the + XUM boot protocol. This specific implementation is based on C# for a + Windows 32-bit environment. Sorry. + + The Verilog hardware files are not included here because this version + is released with the full XUM hardware files. + + +XUM Boot Protocol Description: +------------------------------ + + 1. Programmer sends 'XUM' ASCII bytes. + 2. Programmer sends a number indicating how many 32-bit data words it + has to send, minus 1. (For example, if it has one 32-bit data word, + this number will be 0.) The size of this number is 18 bits. + This means the minimum transmission size is 1 word (32 bits), and + the maximum transmission size is 262144 words (exactly 1MB). + This 18-bit number is sent in three bytes from high-order bits to + low-order bits, and the six most significant bits of the first + byte must be 0. + 3. The FPGA sends back the third size byte from the programmer, allowing + the programmer to determine if the FPGA is listening and conforming + to the XUM boot protocol. + 4. The programmer sends another 18-bit number indicating the starting + offset in memory where the data should be placed. Normally this will + be 0. This number is also sent in three bytes, and the six most + significant bits of the first byte are ignored. + 5. The programmer sends the data. A copy of each byte that it sends will + be sent back to the programmer from the FPGA, allowing the programmer + to determine if all the data was transmitted successfully. + + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_installer/Application Files/XUM Bootloader_1_0_0_1/XUM Bootloader.application b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_installer/Application Files/XUM Bootloader_1_0_0_1/XUM Bootloader.application new file mode 100755 index 0000000..2e463be --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_installer/Application Files/XUM Bootloader_1_0_0_1/XUM Bootloader.application @@ -0,0 +1,22 @@ + + + + + + + + + + + + + + + + + + lb5hk05zpI3hcrnHjjkJeL/LTDk= + + + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_installer/Application Files/XUM Bootloader_1_0_0_1/XUM Bootloader.exe.deploy b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_installer/Application Files/XUM Bootloader_1_0_0_1/XUM Bootloader.exe.deploy new file mode 100755 index 0000000..d17dd9e Binary files /dev/null and b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_installer/Application Files/XUM Bootloader_1_0_0_1/XUM Bootloader.exe.deploy differ diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_installer/Application Files/XUM Bootloader_1_0_0_1/XUM Bootloader.exe.manifest b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_installer/Application Files/XUM Bootloader_1_0_0_1/XUM Bootloader.exe.manifest new file mode 100755 index 0000000..38ae15b --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_installer/Application Files/XUM Bootloader_1_0_0_1/XUM Bootloader.exe.manifest @@ -0,0 +1,66 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Rbrxm97Dtegkf/HrMHph/O0RYNo= + + + + + + + + + + R4E1qhvYjXn/6LmAglPO8QzH7Zg= + + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_installer/Application Files/XUM Bootloader_1_0_0_1/xum.ico.deploy b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_installer/Application Files/XUM Bootloader_1_0_0_1/xum.ico.deploy new file mode 100755 index 0000000..315c7a4 Binary files /dev/null and b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_installer/Application Files/XUM Bootloader_1_0_0_1/xum.ico.deploy differ diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_installer/XUM Bootloader.application b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_installer/XUM Bootloader.application new file mode 100755 index 0000000..2e463be --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_installer/XUM Bootloader.application @@ -0,0 +1,22 @@ + + + + + + + + + + + + + + + + + + lb5hk05zpI3hcrnHjjkJeL/LTDk= + + + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_installer/setup.exe b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_installer/setup.exe new file mode 100755 index 0000000..d6d6fe7 Binary files /dev/null and b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_installer/setup.exe differ diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI.sln b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI.sln new file mode 100755 index 0000000..94c22ba --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI.sln @@ -0,0 +1,20 @@ + +Microsoft Visual Studio Solution File, Format Version 11.00 +# Visual Studio 2010 +Project("{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC}") = "XumBootloader_GUI", "XumBootloader_GUI\XumBootloader_GUI.csproj", "{553C455A-430B-4DC2-893F-DF77F5DDE1A1}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|x86 = Debug|x86 + Release|x86 = Release|x86 + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {553C455A-430B-4DC2-893F-DF77F5DDE1A1}.Debug|x86.ActiveCfg = Debug|x86 + {553C455A-430B-4DC2-893F-DF77F5DDE1A1}.Debug|x86.Build.0 = Debug|x86 + {553C455A-430B-4DC2-893F-DF77F5DDE1A1}.Release|x86.ActiveCfg = Release|x86 + {553C455A-430B-4DC2-893F-DF77F5DDE1A1}.Release|x86.Build.0 = Release|x86 + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection +EndGlobal diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI.suo b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI.suo new file mode 100755 index 0000000..408e654 Binary files /dev/null and b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI.suo differ diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI/Form1.Designer.cs b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI/Form1.Designer.cs new file mode 100755 index 0000000..4b9a9fb --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI/Form1.Designer.cs @@ -0,0 +1,236 @@ +namespace XumBootloader_GUI +{ + partial class Form1 + { + /// + /// Required designer variable. + /// + private System.ComponentModel.IContainer components = null; + + /// + /// Clean up any resources being used. + /// + /// true if managed resources should be disposed; otherwise, false. + protected override void Dispose(bool disposing) + { + if (disposing && (components != null)) + { + components.Dispose(); + } + base.Dispose(disposing); + } + + #region Windows Form Designer generated code + + /// + /// Required method for Designer support - do not modify + /// the contents of this method with the code editor. + /// + private void InitializeComponent() + { + this.components = new System.ComponentModel.Container(); + this.label1 = new System.Windows.Forms.Label(); + this.serialPortSelect = new System.Windows.Forms.ComboBox(); + this.label2 = new System.Windows.Forms.Label(); + this.baudRateSelect = new System.Windows.Forms.ComboBox(); + this.openFileDialog1 = new System.Windows.Forms.OpenFileDialog(); + this.selectFile = new System.Windows.Forms.Button(); + this.label3 = new System.Windows.Forms.Label(); + this.labelFilename = new System.Windows.Forms.Label(); + this.labelSize = new System.Windows.Forms.Label(); + this.Send = new System.Windows.Forms.Label(); + this.sendButton = new System.Windows.Forms.Button(); + this.serialPort1 = new System.IO.Ports.SerialPort(this.components); + this.label4 = new System.Windows.Forms.Label(); + this.setOffset = new System.Windows.Forms.TextBox(); + this.labelSuccess = new System.Windows.Forms.Label(); + this.progressBar1 = new System.Windows.Forms.ProgressBar(); + this.SuspendLayout(); + // + // label1 + // + this.label1.AutoSize = true; + this.label1.Location = new System.Drawing.Point(13, 13); + this.label1.Name = "label1"; + this.label1.Size = new System.Drawing.Size(55, 13); + this.label1.TabIndex = 0; + this.label1.Text = "Serial Port"; + // + // serialPortSelect + // + this.serialPortSelect.DropDownStyle = System.Windows.Forms.ComboBoxStyle.DropDownList; + this.serialPortSelect.FormattingEnabled = true; + this.serialPortSelect.Location = new System.Drawing.Point(16, 30); + this.serialPortSelect.Name = "serialPortSelect"; + this.serialPortSelect.Size = new System.Drawing.Size(74, 21); + this.serialPortSelect.TabIndex = 1; + // + // label2 + // + this.label2.AutoSize = true; + this.label2.Location = new System.Drawing.Point(104, 13); + this.label2.Name = "label2"; + this.label2.Size = new System.Drawing.Size(58, 13); + this.label2.TabIndex = 2; + this.label2.Text = "Baud Rate"; + // + // baudRateSelect + // + this.baudRateSelect.DropDownStyle = System.Windows.Forms.ComboBoxStyle.DropDownList; + this.baudRateSelect.FormattingEnabled = true; + this.baudRateSelect.Items.AddRange(new object[] { + "110", + "300", + "1200", + "2400", + "4800", + "9600", + "19200", + "38400", + "57600", + "115200", + "230400", + "460800", + "921600"}); + this.baudRateSelect.Location = new System.Drawing.Point(107, 30); + this.baudRateSelect.Name = "baudRateSelect"; + this.baudRateSelect.Size = new System.Drawing.Size(89, 21); + this.baudRateSelect.TabIndex = 3; + // + // selectFile + // + this.selectFile.Location = new System.Drawing.Point(211, 30); + this.selectFile.Name = "selectFile"; + this.selectFile.Size = new System.Drawing.Size(53, 23); + this.selectFile.TabIndex = 4; + this.selectFile.Text = "Open..."; + this.selectFile.UseVisualStyleBackColor = true; + this.selectFile.Click += new System.EventHandler(this.selectFile_Click); + // + // label3 + // + this.label3.AutoSize = true; + this.label3.Location = new System.Drawing.Point(208, 13); + this.label3.Name = "label3"; + this.label3.Size = new System.Drawing.Size(56, 13); + this.label3.TabIndex = 5; + this.label3.Text = "Select File"; + // + // labelFilename + // + this.labelFilename.AutoSize = true; + this.labelFilename.Location = new System.Drawing.Point(16, 67); + this.labelFilename.Name = "labelFilename"; + this.labelFilename.Size = new System.Drawing.Size(85, 13); + this.labelFilename.TabIndex = 6; + this.labelFilename.Text = "No File Selected"; + // + // labelSize + // + this.labelSize.AutoSize = true; + this.labelSize.Location = new System.Drawing.Point(16, 86); + this.labelSize.Name = "labelSize"; + this.labelSize.Size = new System.Drawing.Size(27, 13); + this.labelSize.TabIndex = 7; + this.labelSize.Text = "Size"; + // + // Send + // + this.Send.AutoSize = true; + this.Send.Location = new System.Drawing.Point(349, 13); + this.Send.Name = "Send"; + this.Send.Size = new System.Drawing.Size(32, 13); + this.Send.TabIndex = 8; + this.Send.Text = "Do it!"; + // + // sendButton + // + this.sendButton.Location = new System.Drawing.Point(352, 30); + this.sendButton.Name = "sendButton"; + this.sendButton.Size = new System.Drawing.Size(75, 23); + this.sendButton.TabIndex = 9; + this.sendButton.Text = "Send"; + this.sendButton.UseVisualStyleBackColor = true; + this.sendButton.Click += new System.EventHandler(this.sendButton_Click); + // + // label4 + // + this.label4.AutoSize = true; + this.label4.Location = new System.Drawing.Point(276, 13); + this.label4.Name = "label4"; + this.label4.Size = new System.Drawing.Size(35, 13); + this.label4.TabIndex = 10; + this.label4.Text = "Offset"; + // + // setOffset + // + this.setOffset.Location = new System.Drawing.Point(279, 32); + this.setOffset.Name = "setOffset"; + this.setOffset.Size = new System.Drawing.Size(58, 20); + this.setOffset.TabIndex = 11; + this.setOffset.Text = "0"; + this.setOffset.TextAlign = System.Windows.Forms.HorizontalAlignment.Right; + // + // labelSuccess + // + this.labelSuccess.AutoSize = true; + this.labelSuccess.Location = new System.Drawing.Point(16, 105); + this.labelSuccess.Name = "labelSuccess"; + this.labelSuccess.Size = new System.Drawing.Size(48, 13); + this.labelSuccess.TabIndex = 12; + this.labelSuccess.Text = "Success"; + // + // progressBar1 + // + this.progressBar1.Location = new System.Drawing.Point(352, 105); + this.progressBar1.Name = "progressBar1"; + this.progressBar1.Size = new System.Drawing.Size(75, 13); + this.progressBar1.TabIndex = 13; + // + // Form1 + // + this.AutoScaleDimensions = new System.Drawing.SizeF(6F, 13F); + this.AutoScaleMode = System.Windows.Forms.AutoScaleMode.Font; + this.ClientSize = new System.Drawing.Size(444, 131); + this.Controls.Add(this.progressBar1); + this.Controls.Add(this.labelSuccess); + this.Controls.Add(this.setOffset); + this.Controls.Add(this.label4); + this.Controls.Add(this.sendButton); + this.Controls.Add(this.Send); + this.Controls.Add(this.labelSize); + this.Controls.Add(this.labelFilename); + this.Controls.Add(this.label3); + this.Controls.Add(this.selectFile); + this.Controls.Add(this.baudRateSelect); + this.Controls.Add(this.label2); + this.Controls.Add(this.serialPortSelect); + this.Controls.Add(this.label1); + this.Name = "Form1"; + this.Text = "XUM Bootloader"; + this.ResumeLayout(false); + this.PerformLayout(); + + } + + #endregion + + private System.Windows.Forms.Label label1; + private System.Windows.Forms.ComboBox serialPortSelect; + private System.Windows.Forms.Label label2; + private System.Windows.Forms.ComboBox baudRateSelect; + private System.Windows.Forms.OpenFileDialog openFileDialog1; + private System.Windows.Forms.Button selectFile; + private System.Windows.Forms.Label label3; + private System.Windows.Forms.Label labelFilename; + private System.Windows.Forms.Label labelSize; + private System.Windows.Forms.Label Send; + private System.Windows.Forms.Button sendButton; + private System.IO.Ports.SerialPort serialPort1; + private System.Windows.Forms.Label label4; + private System.Windows.Forms.TextBox setOffset; + private System.Windows.Forms.Label labelSuccess; + private System.Windows.Forms.ProgressBar progressBar1; + } +} + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI/Form1.cs b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI/Form1.cs new file mode 100755 index 0000000..9ce50c3 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI/Form1.cs @@ -0,0 +1,274 @@ +/* Implements the XUM bootloader protocol. + * + * Designed by Grant Ayers (ayers@cs.utah.edu) for + * XUM project of the Gauss group at the University of Utah. + * + * You may reuse this code with proper attribution. + * + * Summer 2010 +*/ +using System; +using System.Collections.Generic; +using System.ComponentModel; +using System.Data; +using System.Drawing; +using System.Linq; +using System.Text; +using System.Windows.Forms; +using System.IO; +using System.Security.Permissions; +using System.IO.Ports; +using System.Diagnostics; + + +namespace XumBootloader_GUI +{ + public partial class Form1 : Form + { + public Form1() + { + InitializeComponent(); + + /* Initialize some form components */ + foreach (string str in Program.getComPortNames()) + { + try + { + serialPortSelect.Items.Add(str); + } + catch (System.ArgumentNullException ex) + { + MessageBox.Show(this, ex.Message + "\nYour system doesn't have any serial ports!"); + Environment.Exit(0); + } + } + try + { + serialPortSelect.SelectedIndex = 0; + baudRateSelect.SelectedItem = "115200"; + serialPort1.Parity = System.IO.Ports.Parity.None; + serialPort1.DataBits = 8; + serialPort1.StopBits = System.IO.Ports.StopBits.One; + serialPort1.Handshake = System.IO.Ports.Handshake.None; + //serialPort1.WriteBufferSize = 1048576; // 1MB + //serialPort1.ReadBufferSize = 1048576; // 1MB + serialPort1.ReadTimeout = 1400; // 1400ms more than enough for 1KB even at 9600 baud. + serialPort1.WriteTimeout = 1400; + labelSuccess.Text = ""; + labelSize.Text = ""; + progressBar1.Visible = false; + } + catch (Exception ex) + { + MessageBox.Show(this, ex.Message); + Environment.Exit(1); + } + + } + + private void selectFile_Click(object sender, EventArgs e) + { + labelSuccess.Text = ""; + progressBar1.Visible = false; + if (openFileDialog1.ShowDialog() == DialogResult.OK) + { + string filename = openFileDialog1.FileName; + labelFilename.Text = "Selected: " + filename; + try + { + System.IO.FileInfo fi = new System.IO.FileInfo(filename); + long filesize = fi.Length; + if (filesize > 1048576) // currently just 1MB + { + MessageBox.Show(this, "Maxiumum supported file size is 1MB"); + labelFilename.Text = ""; + labelSize.Text = ""; + openFileDialog1.FileName = ""; + return; + } + labelSize.Text = "Size: " + filesize + " bytes."; + if ((filesize % 4) != 0) + labelSize.Text = labelSize.Text + " (Not aligned to 32 bits!)"; + } + catch (Exception ex) + { + MessageBox.Show(this, ex.Message); + return; + } + } + if (openFileDialog1.FileName == "") + { + labelFilename.Text = "No File Selected."; + labelSize.Text = ""; + } + } + + private void sendButton_Click(object sender, EventArgs e) + { + try + { + labelSuccess.Text = ""; + if (openFileDialog1.FileName == "") + { + MessageBox.Show(this, "You must first select a file."); + return; + } + object portName = serialPortSelect.SelectedItem; + if (portName == null) + { + MessageBox.Show(this, "You must first select a serial port."); + return; + } + serialPort1.PortName = portName.ToString(); + object baudRate = baudRateSelect.SelectedItem; + if (baudRate == null) + { + MessageBox.Show(this, "You must first select the baud rate."); + return; + } + serialPort1.BaudRate = Convert.ToInt32(baudRate.ToString()); + if (serialPort1.IsOpen) // this doesn't work... + { + MessageBox.Show(this, "Serial port " + portName + " could not be opened and may be in use"); + return; + } + string filename = openFileDialog1.FileName; + int fileSizeBytes = 0; + System.IO.FileInfo fi = new System.IO.FileInfo(filename); + fileSizeBytes = (int)fi.Length; // already verified <= 1MB + labelSize.Text = "Size: " + fileSizeBytes + " bytes."; + int offsetWords; + string offsetStr = setOffset.Text; + if (offsetStr == "") + { + MessageBox.Show(this, "You must enter an offset between 0 and 262143"); + return; + } + try + { + offsetWords = Convert.ToInt32(offsetStr, 10); + } + catch (Exception) + { + MessageBox.Show(this, "\"" + offsetStr + "\" is not a valid number between 0 and 262143"); + return; + } + if ((offsetWords < 0) || (offsetWords > (1048576 - fileSizeBytes))) + { + MessageBox.Show(this, "Offset must be between 0 and (262144 - number of words)."); + return; + } + sendButton.Enabled = false; + serialPort1.Open(); + /* Send the data */ + fileSizeBytes--; + UInt32 size_head = (UInt32)((fileSizeBytes / 4)); + UInt32 offs_head = (UInt32)offsetWords; + byte size1 = (byte)((size_head << 14) >> 30); + byte size2 = (byte)((size_head << 16) >> 24); + byte size3 = (byte)((size_head << 24) >> 24); + byte offs1 = (byte)((offs_head << 14) >> 30); + byte offs2 = (byte)((offs_head << 16) >> 24); + byte offs3 = (byte)((offs_head << 24) >> 24); + byte[] header = { 0x58, 0x55, 0x4d, size1, size2, size3, offs1, offs2, offs3 }; // 'X''U''M' followed by size, offset. + serialPort1.Write(header, 0, header.Length); + fileSizeBytes++; + + /* Check that the copy of size3 came back */ + serialPort1.ReadTimeout = 500; // 500 ms to respond is more than enough. + byte[] response = new byte[1]; + try + { + serialPort1.Read(response, 0, 1); + } + catch (System.TimeoutException) + { + MessageBox.Show(this, "The device did not respond.\n\nIt may be off, disconnected, set at a different baud rate," + + "\nor not listening for the XUM boot protocol."); + serialPort1.Close(); + sendButton.Enabled = true; + return; + } + if (response[0] != size3) + { + MessageBox.Show(this, "An unexpected response was received from the device.\n" + + "(Expected " + size3 + ", Received " + response[0] + ")\n\n" + + "Make sure it is configured for the XUM boot protocol."); + serialPort1.Close(); + sendButton.Enabled = true; + return; + } + + /* Send and verify the data */ + progressBar1.Visible = true; + progressBar1.Minimum = 0; + progressBar1.Maximum = fileSizeBytes; + progressBar1.Value = 0; + byte[] fileData = new byte[fileSizeBytes]; + byte[] echoData = new byte[1024]; + System.IO.BinaryReader file = new System.IO.BinaryReader(File.Open(filename, FileMode.Open)); + file.Read(fileData, 0, fileSizeBytes); + file.Close(); + int sentByteCount = 0; + int currentSendSize = 0; + Stopwatch stopwatch = new Stopwatch(); + stopwatch.Start(); + while (sentByteCount < fileSizeBytes) + { + if ((fileSizeBytes - sentByteCount) >= 1024) + currentSendSize = 1024; + else + currentSendSize = (fileSizeBytes - sentByteCount); + + serialPort1.Write(fileData, sentByteCount, currentSendSize); + long waitStart = stopwatch.ElapsedMilliseconds; + while (serialPort1.BytesToRead < currentSendSize) { + if ((stopwatch.ElapsedMilliseconds - waitStart) > 4000) + { + MessageBox.Show(this, "The device stopped responding. Giving up." + "\nDevice Ack'd : " + serialPort1.BytesToRead + " of " + currentSendSize); + serialPort1.Close(); + sendButton.Enabled = true; + progressBar1.Value = 0; + progressBar1.Visible = false; + return; + } + } + if (serialPort1.BytesToRead > currentSendSize) + { + MessageBox.Show(this, "The device sent back an extra " + (serialPort1.BytesToRead - currentSendSize) + " byte(s), which was unexpected."); + } + serialPort1.Read(echoData, 0, currentSendSize); + for (int i = 0; i < currentSendSize; i++) + { + if (fileData[sentByteCount + i] != echoData[i]) + { + MessageBox.Show(this, "The device sent back non-matching data. There was a transmission error." + + "\n\n" + (sentByteCount + i) + " bytes were transmitted successfully."); + serialPort1.Close(); + sendButton.Enabled = true; + return; + } + } + sentByteCount += currentSendSize; + progressBar1.Value = sentByteCount; + } + stopwatch.Stop(); + labelSuccess.Text = "Success (" + (stopwatch.ElapsedMilliseconds / 1000.0) + " seconds)."; + serialPort1.Close(); + sendButton.Enabled = true; + } + catch (Exception ex) + { + MessageBox.Show(this, ex.Message); + if (serialPort1.IsOpen) + serialPort1.Close(); + sendButton.Enabled = true; + progressBar1.Value = 0; + return; + } + + } + + + } +} diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI/Form1.resx b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI/Form1.resx new file mode 100755 index 0000000..8bc7e03 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI/Form1.resx @@ -0,0 +1,126 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + text/microsoft-resx + + + 2.0 + + + System.Resources.ResXResourceReader, System.Windows.Forms, Version=4.0.0.0, Culture=neutral, PublicKeyToken=b77a5c561934e089 + + + System.Resources.ResXResourceWriter, System.Windows.Forms, Version=4.0.0.0, Culture=neutral, PublicKeyToken=b77a5c561934e089 + + + 17, 17 + + + 157, 17 + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI/Program.cs b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI/Program.cs new file mode 100755 index 0000000..a329079 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI/Program.cs @@ -0,0 +1,39 @@ +using System; +using System.Collections.Generic; +using System.Linq; +using System.Windows.Forms; +using System.IO.Ports; + +namespace XumBootloader_GUI +{ + static class Program + { + /// + /// The main entry point for the application. + /// + + public static string[] comPorts; // List of available serial ports. + [STAThread] + static void Main() + { + Application.EnableVisualStyles(); + Application.SetCompatibleTextRenderingDefault(false); + try + { + comPorts = SerialPort.GetPortNames(); + } + catch (System.ComponentModel.Win32Exception ex) + { + MessageBox.Show(ex.Message); + Environment.Exit(1); + } + Application.Run(new Form1()); + } + + /* Helper function to retrieve serial port names */ + public static string[] getComPortNames() + { + return comPorts; + } + } +} diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI/Properties/AssemblyInfo.cs b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI/Properties/AssemblyInfo.cs new file mode 100755 index 0000000..8c26619 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI/Properties/AssemblyInfo.cs @@ -0,0 +1,36 @@ +using System.Reflection; +using System.Runtime.CompilerServices; +using System.Runtime.InteropServices; + +// General Information about an assembly is controlled through the following +// set of attributes. Change these attribute values to modify the information +// associated with an assembly. +[assembly: AssemblyTitle("XUM Bootloader GUI")] +[assembly: AssemblyDescription("Implements the XUM Boot Protocol for configuring a device.")] +[assembly: AssemblyConfiguration("")] +[assembly: AssemblyCompany("University of Utah")] +[assembly: AssemblyProduct("XUM Bootloader")] +[assembly: AssemblyCopyright("Copyright © 2010")] +[assembly: AssemblyTrademark("")] +[assembly: AssemblyCulture("")] + +// Setting ComVisible to false makes the types in this assembly not visible +// to COM components. If you need to access a type in this assembly from +// COM, set the ComVisible attribute to true on that type. +[assembly: ComVisible(false)] + +// The following GUID is for the ID of the typelib if this project is exposed to COM +[assembly: Guid("86c1d8b9-e19b-45aa-a1f6-374b7810e358")] + +// Version information for an assembly consists of the following four values: +// +// Major Version +// Minor Version +// Build Number +// Revision +// +// You can specify all the values or you can default the Build and Revision Numbers +// by using the '*' as shown below: +// [assembly: AssemblyVersion("1.0.*")] +[assembly: AssemblyVersion("1.0.0.0")] +[assembly: AssemblyFileVersion("1.0.0.0")] diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI/Properties/Resources.Designer.cs b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI/Properties/Resources.Designer.cs new file mode 100755 index 0000000..8233bca --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI/Properties/Resources.Designer.cs @@ -0,0 +1,63 @@ +//------------------------------------------------------------------------------ +// +// This code was generated by a tool. +// Runtime Version:4.0.30319.1 +// +// Changes to this file may cause incorrect behavior and will be lost if +// the code is regenerated. +// +//------------------------------------------------------------------------------ + +namespace XumBootloader_GUI.Properties { + using System; + + + /// + /// A strongly-typed resource class, for looking up localized strings, etc. + /// + // This class was auto-generated by the StronglyTypedResourceBuilder + // class via a tool like ResGen or Visual Studio. + // To add or remove a member, edit your .ResX file then rerun ResGen + // with the /str option, or rebuild your VS project. + [global::System.CodeDom.Compiler.GeneratedCodeAttribute("System.Resources.Tools.StronglyTypedResourceBuilder", "4.0.0.0")] + [global::System.Diagnostics.DebuggerNonUserCodeAttribute()] + [global::System.Runtime.CompilerServices.CompilerGeneratedAttribute()] + internal class Resources { + + private static global::System.Resources.ResourceManager resourceMan; + + private static global::System.Globalization.CultureInfo resourceCulture; + + [global::System.Diagnostics.CodeAnalysis.SuppressMessageAttribute("Microsoft.Performance", "CA1811:AvoidUncalledPrivateCode")] + internal Resources() { + } + + /// + /// Returns the cached ResourceManager instance used by this class. + /// + [global::System.ComponentModel.EditorBrowsableAttribute(global::System.ComponentModel.EditorBrowsableState.Advanced)] + internal static global::System.Resources.ResourceManager ResourceManager { + get { + if (object.ReferenceEquals(resourceMan, null)) { + global::System.Resources.ResourceManager temp = new global::System.Resources.ResourceManager("XumBootloader_GUI.Properties.Resources", typeof(Resources).Assembly); + resourceMan = temp; + } + return resourceMan; + } + } + + /// + /// Overrides the current thread's CurrentUICulture property for all + /// resource lookups using this strongly typed resource class. + /// + [global::System.ComponentModel.EditorBrowsableAttribute(global::System.ComponentModel.EditorBrowsableState.Advanced)] + internal static global::System.Globalization.CultureInfo Culture { + get { + return resourceCulture; + } + set { + resourceCulture = value; + } + } + } +} diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI/Properties/Resources.resx b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI/Properties/Resources.resx new file mode 100755 index 0000000..ffecec8 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI/Properties/Resources.resx @@ -0,0 +1,117 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + text/microsoft-resx + + + 2.0 + + + System.Resources.ResXResourceReader, System.Windows.Forms, Version=2.0.0.0, Culture=neutral, PublicKeyToken=b77a5c561934e089 + + + System.Resources.ResXResourceWriter, System.Windows.Forms, Version=2.0.0.0, Culture=neutral, PublicKeyToken=b77a5c561934e089 + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI/Properties/Settings.Designer.cs b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI/Properties/Settings.Designer.cs new file mode 100755 index 0000000..3d9dc54 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI/Properties/Settings.Designer.cs @@ -0,0 +1,26 @@ +//------------------------------------------------------------------------------ +// +// This code was generated by a tool. +// Runtime Version:4.0.30319.1 +// +// Changes to this file may cause incorrect behavior and will be lost if +// the code is regenerated. +// +//------------------------------------------------------------------------------ + +namespace XumBootloader_GUI.Properties { + + + [global::System.Runtime.CompilerServices.CompilerGeneratedAttribute()] + [global::System.CodeDom.Compiler.GeneratedCodeAttribute("Microsoft.VisualStudio.Editors.SettingsDesigner.SettingsSingleFileGenerator", "10.0.0.0")] + internal sealed partial class Settings : global::System.Configuration.ApplicationSettingsBase { + + private static Settings defaultInstance = ((Settings)(global::System.Configuration.ApplicationSettingsBase.Synchronized(new Settings()))); + + public static Settings Default { + get { + return defaultInstance; + } + } + } +} diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI/Properties/Settings.settings b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI/Properties/Settings.settings new file mode 100755 index 0000000..abf36c5 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI/Properties/Settings.settings @@ -0,0 +1,7 @@ + + + + + + + diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI/XumBootloader_GUI.csproj b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI/XumBootloader_GUI.csproj new file mode 100755 index 0000000..f509e8e --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI/XumBootloader_GUI.csproj @@ -0,0 +1,146 @@ + + + + Debug + x86 + 8.0.30703 + 2.0 + {553C455A-430B-4DC2-893F-DF77F5DDE1A1} + WinExe + Properties + XumBootloader_GUI + XUM Bootloader + v4.0 + Client + 512 + false + C:\root\xilinx-proj\xum_uart_bootloader_BZ2\ + true + Disk + false + Foreground + 7 + Days + false + false + true + en + 2 + 1.0.0.%2a + false + true + true + + + x86 + true + full + false + bin\Debug\ + DEBUG;TRACE + prompt + 4 + + + x86 + pdbonly + true + bin\Release\ + TRACE + prompt + 4 + + + 3CD7213BE25EFD6BDE8F9138939D82BD6F4CC0AA + + + XumBootloader_GUI_TemporaryKey.pfx + + + true + + + false + + + xum.ico + + + + + + + + + + + + + + + + Form + + + Form1.cs + + + + + Form1.cs + + + ResXFileCodeGenerator + Resources.Designer.cs + Designer + + + True + Resources.resx + True + + + SettingsSingleFileGenerator + Settings.Designer.cs + + + True + Settings.settings + True + + + + + + False + Microsoft .NET Framework 4 Client Profile %28x86 and x64%29 + true + + + False + .NET Framework 3.5 SP1 Client Profile + false + + + False + .NET Framework 3.5 SP1 + false + + + False + Windows Installer 3.1 + true + + + + + + + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI/XumBootloader_GUI.csproj.user b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI/XumBootloader_GUI.csproj.user new file mode 100755 index 0000000..1ea1055 --- /dev/null +++ b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI/XumBootloader_GUI.csproj.user @@ -0,0 +1,13 @@ + + + + C:\root\xilinx-proj\xum_uart_bootloader_BZ2\|C:\Users\User\Desktop\Xum Bootloader Release\|C:\Users\User\Desktop\deploy\|publish\ + + + + + + en-US + false + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI/XumBootloader_GUI_TemporaryKey.pfx b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI/XumBootloader_GUI_TemporaryKey.pfx new file mode 100755 index 0000000..0afb382 Binary files /dev/null and b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI/XumBootloader_GUI_TemporaryKey.pfx differ diff --git a/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI/xum.ico b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI/xum.ico new file mode 100755 index 0000000..315c7a4 Binary files /dev/null and b/demo_chip_rtl/rtl/mips32r1/trunk/Software/xum_bootloader/programmer/win32_source/XumBootloader_GUI/xum.ico differ diff --git a/demo_chip_rtl/rtl/nova/tags/Start/MISC/readme.txt b/demo_chip_rtl/rtl/nova/tags/Start/MISC/readme.txt new file mode 100644 index 0000000..f331dbf --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/MISC/readme.txt @@ -0,0 +1 @@ +To be added soon \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/doc/readme.txt b/demo_chip_rtl/rtl/nova/tags/Start/doc/readme.txt new file mode 100644 index 0000000..f331dbf --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/doc/readme.txt @@ -0,0 +1 @@ +To be added soon \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/Beha_BitStream_ram.v b/demo_chip_rtl/rtl/nova/tags/Start/src/Beha_BitStream_ram.v new file mode 100644 index 0000000..02f3816 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/Beha_BitStream_ram.v @@ -0,0 +1,37 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : Beha_BitStream_ram.v +// Generated : May 16,2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Behavior RAM for encoded bitstream storing, NOT synthesizable +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module Beha_BitStream_ram(clk,BitStream_ram_ren,BitStream_ram_addr,BitStream_ram_data); + input clk; + input BitStream_ram_ren; + input [16:0] BitStream_ram_addr; + + output [15:0] BitStream_ram_data; + + reg [15:0] BitStream_ram_data; + reg [15:0] BitStream_ram[0:`Beha_Bitstream_ram_size]; + + initial + begin + $readmemh("D:/nova_opencores/bin2hex/akiyo300_1ref.txt",BitStream_ram); + end + + always @ (posedge clk) + if (BitStream_ram_ren == 0) + BitStream_ram_data <= #2 BitStream_ram[BitStream_ram_addr]; + +endmodule diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/BitStream_buffer.v b/demo_chip_rtl/rtl/nova/tags/Start/src/BitStream_buffer.v new file mode 100644 index 0000000..47c539a --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/BitStream_buffer.v @@ -0,0 +1,288 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : BitStream_buffer.v +// Generated : May 16,2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Circular buffer,interfacing between Beha_Bitstream_ram and the decoder +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module BitStream_buffer (clk,reset_n,BitStream_buffer_input,pc, + BitStream_ram_ren,BitStream_buffer_valid_n,BitStream_buffer_output,BitStream_ram_addr); + input clk,reset_n; + input [15:0] BitStream_buffer_input; + input [6:0] pc; + + output BitStream_ram_ren; + output BitStream_buffer_valid_n; + output [15:0] BitStream_buffer_output; + output [16:0]BitStream_ram_addr; + + reg BitStream_ram_ren; + reg BitStream_buffer_valid_n; + reg [15:0] BitStream_buffer_output; + reg [16:0]BitStream_ram_addr; + + reg [0:127]BS_buffer; + reg [6:0] pc_previous; + reg [3:0] reset_counter; + reg [2:0] half_fill_counter; + reg [6:0] buffer_index; //for buffer write + + /* + // synopsys translate_off + integer pc_statistical; + initial + begin + pc_statistical = $fopen("pc_statistical.txt"); + end + always @ (posedge clk) + $fdisplay (pc_statistical,"%d",pc); + // synopsys translate_on + */ + always @ (posedge clk) + if (reset_n == 1'b0) + pc_previous <= 0; + else + pc_previous <= pc; + + always @ (posedge clk) + if (reset_n == 1'b0) + reset_counter <= 0; + else if (reset_counter < 10) + reset_counter <= reset_counter + 1; + + always @ (posedge clk) + if (reset_n == 1'b0) + half_fill_counter <= 0; + else if (reset_counter == 10) + begin + if (((pc > 63 && pc_previous <= 63) || (pc <63 && pc_previous >=63)) && half_fill_counter == 0) + half_fill_counter <= 1; + else if (pc > 63 && half_fill_counter == 0 && buffer_index == 0) + half_fill_counter <= 1; + else if (pc < 63 && half_fill_counter == 0 && buffer_index == 64) + half_fill_counter <= 1; + else if (half_fill_counter > 0 && half_fill_counter < 5) + half_fill_counter <= half_fill_counter + 1; + else if (half_fill_counter == 5) + half_fill_counter <= 0; + end + + always @ (posedge clk) + if (reset_n == 1'b0) + buffer_index <= 0; + else if (reset_counter > 1 && reset_counter < 10) + buffer_index <= buffer_index + 16; + else if (half_fill_counter > 1 && half_fill_counter <= 5) + buffer_index <= buffer_index + 16; + + always @ (posedge clk) + if (reset_n == 1'b0) + BitStream_buffer_valid_n <= 1'b1; + else if (reset_counter == 10) + BitStream_buffer_valid_n <= 1'b0; + + always @ (posedge clk) + if (reset_n == 1'b0) + BitStream_ram_ren <= 1'b0; + else if (reset_counter < 9) + BitStream_ram_ren <= 1'b0; + else if (reset_counter == 9) + BitStream_ram_ren <= 1'b1; + else + begin + if (((pc > 63 && pc_previous <= 63) || (pc <63 && pc_previous >=63)) && half_fill_counter == 0) + BitStream_ram_ren <= 0; + else if (half_fill_counter > 0 && half_fill_counter < 5) + BitStream_ram_ren <= 0; + else + BitStream_ram_ren <= 1; + end + + always @ (posedge clk) + if (reset_n == 1'b0) + BitStream_ram_addr <= 0; + else if (reset_counter > 0 && reset_counter < 9) + BitStream_ram_addr <= BitStream_ram_addr + 1; + else if (half_fill_counter > 0 && half_fill_counter < 5 && BitStream_ram_addr != 17'd131071) //no wrap around + BitStream_ram_addr <= BitStream_ram_addr + 1; + + integer i; + always @ (posedge clk) + if (reset_n == 1'b0) + BS_buffer <= 0; + else if ((reset_counter > 1 && reset_counter < 10) || (half_fill_counter > 1 && half_fill_counter <= 5)) + case (buffer_index[6:4]) + 3'b000: + for (i=0;i<16;i=i+1) + BS_buffer[i] <= BitStream_buffer_input[15-i]; + 3'b001: + for (i=0;i<16;i=i+1) + BS_buffer[16+i] <= BitStream_buffer_input[15-i]; + 3'b010: + for (i=0;i<16;i=i+1) + BS_buffer[32+i] <= BitStream_buffer_input[15-i]; + 3'b011: + for (i=0;i<16;i=i+1) + BS_buffer[48+i] <= BitStream_buffer_input[15-i]; + 3'b100: + for (i=0;i<16;i=i+1) + BS_buffer[64+i] <= BitStream_buffer_input[15-i]; + 3'b101: + for (i=0;i<16;i=i+1) + BS_buffer[80+i] <= BitStream_buffer_input[15-i]; + 3'b110: + for (i=0;i<16;i=i+1) + BS_buffer[96+i] <= BitStream_buffer_input[15-i]; + 3'b111: + for (i=0;i<16;i=i+1) + BS_buffer[112+i] <= BitStream_buffer_input[15-i]; + endcase + + always @ (posedge clk) + //always @ (reset_n or BitStream_buffer_valid_n or pc) + if (reset_n == 1'b0) + BitStream_buffer_output <= 0; + else if (BitStream_buffer_valid_n == 0) + case (pc) + 0 :BitStream_buffer_output <= BS_buffer[0:15]; + 1 :BitStream_buffer_output <= BS_buffer[1:16]; + 2 :BitStream_buffer_output <= BS_buffer[2:17]; + 3 :BitStream_buffer_output <= BS_buffer[3:18]; + 4 :BitStream_buffer_output <= BS_buffer[4:19]; + 5 :BitStream_buffer_output <= BS_buffer[5:20]; + 6 :BitStream_buffer_output <= BS_buffer[6:21]; + 7 :BitStream_buffer_output <= BS_buffer[7:22]; + 8 :BitStream_buffer_output <= BS_buffer[8:23]; + 9 :BitStream_buffer_output <= BS_buffer[9:24]; + 10 :BitStream_buffer_output <= BS_buffer[10:25]; + 11 :BitStream_buffer_output <= BS_buffer[11:26]; + 12 :BitStream_buffer_output <= BS_buffer[12:27]; + 13 :BitStream_buffer_output <= BS_buffer[13:28]; + 14 :BitStream_buffer_output <= BS_buffer[14:29]; + 15 :BitStream_buffer_output <= BS_buffer[15:30]; + 16 :BitStream_buffer_output <= BS_buffer[16:31]; + 17 :BitStream_buffer_output <= BS_buffer[17:32]; + 18 :BitStream_buffer_output <= BS_buffer[18:33]; + 19 :BitStream_buffer_output <= BS_buffer[19:34]; + 20 :BitStream_buffer_output <= BS_buffer[20:35]; + 21 :BitStream_buffer_output <= BS_buffer[21:36]; + 22 :BitStream_buffer_output <= BS_buffer[22:37]; + 23 :BitStream_buffer_output <= BS_buffer[23:38]; + 24 :BitStream_buffer_output <= BS_buffer[24:39]; + 25 :BitStream_buffer_output <= BS_buffer[25:40]; + 26 :BitStream_buffer_output <= BS_buffer[26:41]; + 27 :BitStream_buffer_output <= BS_buffer[27:42]; + 28 :BitStream_buffer_output <= BS_buffer[28:43]; + 29 :BitStream_buffer_output <= BS_buffer[29:44]; + 30 :BitStream_buffer_output <= BS_buffer[30:45]; + 31 :BitStream_buffer_output <= BS_buffer[31:46]; + 32 :BitStream_buffer_output <= BS_buffer[32:47]; + 33 :BitStream_buffer_output <= BS_buffer[33:48]; + 34 :BitStream_buffer_output <= BS_buffer[34:49]; + 35 :BitStream_buffer_output <= BS_buffer[35:50]; + 36 :BitStream_buffer_output <= BS_buffer[36:51]; + 37 :BitStream_buffer_output <= BS_buffer[37:52]; + 38 :BitStream_buffer_output <= BS_buffer[38:53]; + 39 :BitStream_buffer_output <= BS_buffer[39:54]; + 40 :BitStream_buffer_output <= BS_buffer[40:55]; + 41 :BitStream_buffer_output <= BS_buffer[41:56]; + 42 :BitStream_buffer_output <= BS_buffer[42:57]; + 43 :BitStream_buffer_output <= BS_buffer[43:58]; + 44 :BitStream_buffer_output <= BS_buffer[44:59]; + 45 :BitStream_buffer_output <= BS_buffer[45:60]; + 46 :BitStream_buffer_output <= BS_buffer[46:61]; + 47 :BitStream_buffer_output <= BS_buffer[47:62]; + 48 :BitStream_buffer_output <= BS_buffer[48:63]; + 49 :BitStream_buffer_output <= BS_buffer[49:64]; + 50 :BitStream_buffer_output <= BS_buffer[50:65]; + 51 :BitStream_buffer_output <= BS_buffer[51:66]; + 52 :BitStream_buffer_output <= BS_buffer[52:67]; + 53 :BitStream_buffer_output <= BS_buffer[53:68]; + 54 :BitStream_buffer_output <= BS_buffer[54:69]; + 55 :BitStream_buffer_output <= BS_buffer[55:70]; + 56 :BitStream_buffer_output <= BS_buffer[56:71]; + 57 :BitStream_buffer_output <= BS_buffer[57:72]; + 58 :BitStream_buffer_output <= BS_buffer[58:73]; + 59 :BitStream_buffer_output <= BS_buffer[59:74]; + 60 :BitStream_buffer_output <= BS_buffer[60:75]; + 61 :BitStream_buffer_output <= BS_buffer[61:76]; + 62 :BitStream_buffer_output <= BS_buffer[62:77]; + 63 :BitStream_buffer_output <= BS_buffer[63:78]; + 64 :BitStream_buffer_output <= BS_buffer[64:79]; + 65 :BitStream_buffer_output <= BS_buffer[65:80]; + 66 :BitStream_buffer_output <= BS_buffer[66:81]; + 67 :BitStream_buffer_output <= BS_buffer[67:82]; + 68 :BitStream_buffer_output <= BS_buffer[68:83]; + 69 :BitStream_buffer_output <= BS_buffer[69:84]; + 70 :BitStream_buffer_output <= BS_buffer[70:85]; + 71 :BitStream_buffer_output <= BS_buffer[71:86]; + 72 :BitStream_buffer_output <= BS_buffer[72:87]; + 73 :BitStream_buffer_output <= BS_buffer[73:88]; + 74 :BitStream_buffer_output <= BS_buffer[74:89]; + 75 :BitStream_buffer_output <= BS_buffer[75:90]; + 76 :BitStream_buffer_output <= BS_buffer[76:91]; + 77 :BitStream_buffer_output <= BS_buffer[77:92]; + 78 :BitStream_buffer_output <= BS_buffer[78:93]; + 79 :BitStream_buffer_output <= BS_buffer[79:94]; + 80 :BitStream_buffer_output <= BS_buffer[80:95]; + 81 :BitStream_buffer_output <= BS_buffer[81:96]; + 82 :BitStream_buffer_output <= BS_buffer[82:97]; + 83 :BitStream_buffer_output <= BS_buffer[83:98]; + 84 :BitStream_buffer_output <= BS_buffer[84:99]; + 85 :BitStream_buffer_output <= BS_buffer[85:100]; + 86 :BitStream_buffer_output <= BS_buffer[86:101]; + 87 :BitStream_buffer_output <= BS_buffer[87:102]; + 88 :BitStream_buffer_output <= BS_buffer[88:103]; + 89 :BitStream_buffer_output <= BS_buffer[89:104]; + 90 :BitStream_buffer_output <= BS_buffer[90:105]; + 91 :BitStream_buffer_output <= BS_buffer[91:106]; + 92 :BitStream_buffer_output <= BS_buffer[92:107]; + 93 :BitStream_buffer_output <= BS_buffer[93:108]; + 94 :BitStream_buffer_output <= BS_buffer[94:109]; + 95 :BitStream_buffer_output <= BS_buffer[95:110]; + 96 :BitStream_buffer_output <= BS_buffer[96:111]; + 97 :BitStream_buffer_output <= BS_buffer[97:112]; + 98 :BitStream_buffer_output <= BS_buffer[98:113]; + 99 :BitStream_buffer_output <= BS_buffer[99:114]; + 100:BitStream_buffer_output <= BS_buffer[100:115]; + 101:BitStream_buffer_output <= BS_buffer[101:116]; + 102:BitStream_buffer_output <= BS_buffer[102:117]; + 103:BitStream_buffer_output <= BS_buffer[103:118]; + 104:BitStream_buffer_output <= BS_buffer[104:119]; + 105:BitStream_buffer_output <= BS_buffer[105:120]; + 106:BitStream_buffer_output <= BS_buffer[106:121]; + 107:BitStream_buffer_output <= BS_buffer[107:122]; + 108:BitStream_buffer_output <= BS_buffer[108:123]; + 109:BitStream_buffer_output <= BS_buffer[109:124]; + 110:BitStream_buffer_output <= BS_buffer[110:125]; + 111:BitStream_buffer_output <= BS_buffer[111:126]; + 112:BitStream_buffer_output <= BS_buffer[112:127]; + 113:BitStream_buffer_output <= {BS_buffer[113:127],BS_buffer[0]}; + 114:BitStream_buffer_output <= {BS_buffer[114:127],BS_buffer[0:1]}; + 115:BitStream_buffer_output <= {BS_buffer[115:127],BS_buffer[0:2]}; + 116:BitStream_buffer_output <= {BS_buffer[116:127],BS_buffer[0:3]}; + 117:BitStream_buffer_output <= {BS_buffer[117:127],BS_buffer[0:4]}; + 118:BitStream_buffer_output <= {BS_buffer[118:127],BS_buffer[0:5]}; + 119:BitStream_buffer_output <= {BS_buffer[119:127],BS_buffer[0:6]}; + 120:BitStream_buffer_output <= {BS_buffer[120:127],BS_buffer[0:7]}; + 121:BitStream_buffer_output <= {BS_buffer[121:127],BS_buffer[0:8]}; + 122:BitStream_buffer_output <= {BS_buffer[122:127],BS_buffer[0:9]}; + 123:BitStream_buffer_output <= {BS_buffer[123:127],BS_buffer[0:10]}; + 124:BitStream_buffer_output <= {BS_buffer[124:127],BS_buffer[0:11]}; + 125:BitStream_buffer_output <= {BS_buffer[125:127],BS_buffer[0:12]}; + 126:BitStream_buffer_output <= {BS_buffer[126:127],BS_buffer[0:13]}; + 127:BitStream_buffer_output <= {BS_buffer[127],BS_buffer[0:14]}; + endcase +endmodule + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/BitStream_controller.v b/demo_chip_rtl/rtl/nova/tags/Start/src/BitStream_controller.v new file mode 100644 index 0000000..cf81775 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/BitStream_controller.v @@ -0,0 +1,745 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : BitStream_controller.v +// Generated : June 12,2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// top module for bitstream controller +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module BitStream_controller (clk,reset_n,freq_ctrl0,freq_ctrl1,BitStream_buffer_input,pin_disable_DF, + trigger_CAVLC,blk4x4_rec_counter,end_of_DCBlk_IQIT,end_of_one_blk4x4_sum,end_of_MB_DEC,gclk_end_of_MB_DEC, + curr_DC_IsZero, + + BitStream_ram_ren,BitStream_ram_addr,pic_num, + mb_type_general,mb_num_h,mb_num_v,NextMB_IsSkip,LowerMB_IsSkip, + slice_data_state,residual_state,cavlc_decoder_state, + end_of_one_residual_block,end_of_NonZeroCoeff_CAVLC,end_of_one_frame, + Intra16x16_predmode,Intra4x4_predmode_CurrMb,Intra_chroma_predmode, + QPy,QPc,i4x4_CbCr,slice_alpha_c0_offset_div2,slice_beta_offset_div2, + CodedBlockPatternLuma,CodedBlockPatternChroma,TotalCoeff, + Is_skip_run_entry,skip_mv_calc,disable_DF, + coeffLevel_0,coeffLevel_1,coeffLevel_2, coeffLevel_3, coeffLevel_4, coeffLevel_5, coeffLevel_6, coeffLevel_7, + coeffLevel_8,coeffLevel_9,coeffLevel_10,coeffLevel_11,coeffLevel_12,coeffLevel_13,coeffLevel_14,coeffLevel_15, + mv_is16x16,mv_below8x8, + mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3,mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3, + end_of_BS_DEC,bs_V0,bs_V1,bs_V2,bs_V3,bs_H0,bs_H1,bs_H2,bs_H3, + + slice_header_s6 + ); + input clk,reset_n; + input freq_ctrl0; + input freq_ctrl1; + input [15:0] BitStream_buffer_input; + input pin_disable_DF; + input trigger_CAVLC; + input [4:0] blk4x4_rec_counter; + input end_of_DCBlk_IQIT; + input end_of_one_blk4x4_sum; + input end_of_MB_DEC; + input gclk_end_of_MB_DEC; + input curr_DC_IsZero; + + output BitStream_ram_ren; + output [16:0] BitStream_ram_addr; + output [5:0] pic_num; + + output [3:0] mb_type_general; + output [3:0] mb_num_h; + output [3:0] mb_num_v; + output NextMB_IsSkip; + output LowerMB_IsSkip; + output [3:0] slice_data_state; + output [3:0] residual_state; + output [3:0] cavlc_decoder_state; + output end_of_one_residual_block; + output end_of_NonZeroCoeff_CAVLC; + output end_of_one_frame; + output [1:0] Intra16x16_predmode; + output [63:0] Intra4x4_predmode_CurrMb; + output [1:0] Intra_chroma_predmode; + output [5:0] QPy; + output [5:0] QPc; + output [1:0] i4x4_CbCr; + output [3:0] slice_alpha_c0_offset_div2; + output [3:0] slice_beta_offset_div2; + output [3:0] CodedBlockPatternLuma; + output [1:0] CodedBlockPatternChroma; + output [4:0] TotalCoeff; + output Is_skip_run_entry; + output skip_mv_calc; + output disable_DF; + output [8:0] coeffLevel_0, coeffLevel_1, coeffLevel_2,coeffLevel_3, coeffLevel_4, coeffLevel_5; + output [8:0] coeffLevel_6, coeffLevel_7, coeffLevel_8, coeffLevel_9,coeffLevel_10,coeffLevel_11; + output [8:0] coeffLevel_12,coeffLevel_13,coeffLevel_14,coeffLevel_15; + output mv_is16x16; + output [3:0] mv_below8x8; + output [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3; + output [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3; + output end_of_BS_DEC; + output [11:0] bs_V0,bs_V1,bs_V2,bs_V3; + output [11:0] bs_H0,bs_H1,bs_H2,bs_H3; + + output slice_header_s6; + + wire gclk_parser; + wire gclk_nal; + wire gclk_slice; + wire gclk_sps; + wire gclk_pps; + wire gclk_slice_header; + wire gclk_slice_data; + wire gclk_residual; + wire gclk_cavlc; + wire gclk_bs_dec; + wire gclk_Intra4x4PredMode_mbAddrB_RF; + wire gclk_mvx_mbAddrB_RF; + wire gclk_mvy_mbAddrB_RF; + wire gclk_mvx_mbAddrC_RF; + wire gclk_mvy_mbAddrC_RF; + wire gclk_LumaLevel_mbAddrB_RF; + wire gclk_ChromaLevel_Cb_mbAddrB_RF; + wire gclk_ChromaLevel_Cr_mbAddrB_RF; + wire [6:0] pc; + wire [5:0] QPy,QPc; + wire [3:0] CodedBlockPatternLuma; + wire [1:0] CodedBlockPatternChroma; + wire [8:0] coeffLevel_0, coeffLevel_1, coeffLevel_2,coeffLevel_3, coeffLevel_4, coeffLevel_5; + wire [8:0] coeffLevel_6, coeffLevel_7, coeffLevel_8, coeffLevel_9,coeffLevel_10,coeffLevel_11; + wire [8:0] coeffLevel_12,coeffLevel_13,coeffLevel_14,coeffLevel_15; + wire [63:0] Intra4x4PredMode_CurrMb; + wire mv_is16x16; + wire Is_skip_run_end; + wire Is_skipMB_mv_calc; + wire [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3; + wire [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3; + + wire BitStream_buffer_valid_n; + wire [15:0] BitStream_buffer_output; + wire [1:0] parser_state; + wire [2:0] nal_unit_state; + wire [1:0] slice_layer_wo_partitioning_state; + wire [3:0] slice_header_state; + wire [2:0] ref_pic_list_reordering_state; + wire [1:0] dec_ref_pic_marking_state; + wire [3:0] slice_data_state; + wire [1:0] sub_mb_pred_state; + wire [2:0] mb_pred_state; + wire [3:0] seq_parameter_set_state; + wire [3:0] pic_parameter_set_state; + wire [3:0] residual_state; + wire [3:0] cavlc_decoder_state; + wire [3:0] exp_golomb_len; + wire [3:0] dependent_variable_len; + wire [4:0] cavlc_consumed_bits_len; + wire heading_one_en; + wire [3:0] heading_one_pos; + wire [7:0] exp_golomb_decoding_output; + wire [9:0] dependent_variable_decoding_output; + wire Intra4x4PredMode_mbAddrB_cs_n; + wire Intra4x4PredMode_mbAddrB_wr_n; + wire [3:0] Intra4x4PredMode_mbAddrB_rd_addr; + wire [3:0] Intra4x4PredMode_mbAddrB_wr_addr; + wire [15:0] Intra4x4PredMode_mbAddrB_din; + wire [15:0] Intra4x4PredMode_mbAddrB_dout; + wire mvx_mbAddrB_cs_n; + wire mvy_mbAddrB_cs_n; + wire mvx_mbAddrC_cs_n; + wire mvy_mbAddrC_cs_n; + wire mvx_mbAddrB_wr_n; + wire mvy_mbAddrB_wr_n; + wire mvx_mbAddrC_wr_n; + wire mvy_mbAddrC_wr_n; + wire [3:0] mvx_mbAddrB_rd_addr; + wire [3:0] mvy_mbAddrB_rd_addr; + wire [3:0] mvx_mbAddrC_rd_addr; + wire [3:0] mvy_mbAddrC_rd_addr; + wire [3:0] mvx_mbAddrB_wr_addr; + wire [3:0] mvy_mbAddrB_wr_addr; + wire [3:0] mvx_mbAddrC_wr_addr; + wire [3:0] mvy_mbAddrC_wr_addr; + wire [31:0] mvx_mbAddrA; + wire [31:0] mvy_mbAddrA; + wire [31:0] mvx_mbAddrB_din; + wire [31:0] mvx_mbAddrB_dout; + wire [31:0] mvy_mbAddrB_din; + wire [31:0] mvy_mbAddrB_dout; + wire [7:0] mvx_mbAddrC_din; + wire [7:0] mvx_mbAddrC_dout; + wire [7:0] mvy_mbAddrC_din; + wire [7:0] mvy_mbAddrC_dout; + wire end_of_NonZeroCoeff_CAVLC; + wire start_code_prefix_found; + wire [4:0] nal_unit_type; + wire deblocking_filter_control_present_flag; + wire [1:0] disable_deblocking_filter_idc; + wire disable_DF; + wire [6:0] mb_skip_run; + wire [2:0] NumMbPart; + wire [2:0] NumSubMbPart; + wire [1:0] MBTypeGen_mbAddrA; + wire MBTypeGen_mbAddrD; + wire [21:0]MBTypeGen_mbAddrB_reg; + wire [3:0] log2_max_frame_num_minus4; + wire [3:0] log2_max_pic_order_cnt_lsb_minus4; + wire constrained_intra_pred_flag; + wire num_ref_idx_active_override_flag; + wire [2:0] num_ref_idx_l0_active_minus1; + wire [2:0] slice_type; + wire [4:0] mb_type; + wire [3:0] mb_type_general; + wire [1:0] sub_mb_type; + wire [5:0] pic_init_qp_minus26; + wire [4:0] chroma_qp_index_offset; + wire [2:0] rem_intra4x4_pred_mode; + wire [7:0] mvd; + wire prev_intra4x4_pred_mode_flag; + wire cavlc_decoder_en; + wire [5:0] pic_num; + wire [6:0] mb_num; + wire [3:0] mb_num_h; + wire [3:0] mb_num_v; + wire [3:0] luma4x4BlkIdx; + wire [1:0] mbPartIdx; + wire [1:0] subMbPartIdx; + wire compIdx; + wire suffix_length_initialized; + wire IsRunLoop; + wire [1:0] i8x8,i4x4; + wire [1:0] i4x4_CbCr; + wire [3:0] coeffNum; + wire [3:0] i_level; + wire [3:0] i_run; + wire [3:0] i_TotalCoeff; + wire [4:0] TotalCoeff; + wire [1:0] TrailingOnes; + wire [4:0] maxNumCoeff; + wire [3:0] zerosLeft; + wire [3:0] run; + + wire [1:0] Luma_8x8_AllZeroCoeff_mbAddrA; + wire [19:0] LumaLevel_mbAddrA; + wire [19:0] LumaLevel_CurrMb0,LumaLevel_CurrMb1,LumaLevel_CurrMb2,LumaLevel_CurrMb3; + wire LumaLevel_mbAddrB_cs_n; + wire [19:0] LumaLevel_mbAddrB_dout; + wire ChromaLevel_Cb_mbAddrB_cs_n; + wire ChromaLevel_Cr_mbAddrB_cs_n; + wire [1:0] bs_dec_counter; + wire [11:0] bs_V0,bs_V1,bs_V2,bs_V3; + wire [11:0] bs_H0,bs_H1,bs_H2,bs_H3; + wire mv_mbAddrB_rd_for_DF; + + BitStream_buffer BitStream_buffer ( + .clk(clk), + .reset_n(reset_n), + .BitStream_buffer_input(BitStream_buffer_input), + .pc(pc), + .BitStream_ram_ren(BitStream_ram_ren), + .BitStream_buffer_valid_n(BitStream_buffer_valid_n), + .BitStream_buffer_output(BitStream_buffer_output), + .BitStream_ram_addr(BitStream_ram_addr) + ); + bitstream_gclk_gen bitstream_gclk_gen ( + .clk(clk), + .reset_n(reset_n), + .freq_ctrl0(freq_ctrl0), + .freq_ctrl1(freq_ctrl1), + .parser_state(parser_state), + .nal_unit_state(nal_unit_state), + .slice_layer_wo_partitioning_state(slice_layer_wo_partitioning_state), + .slice_header_state(slice_header_state), + .slice_data_state(slice_data_state), + .seq_parameter_set_state(seq_parameter_set_state), + .pic_parameter_set_state(pic_parameter_set_state), + .residual_state(residual_state), + .cavlc_decoder_state(cavlc_decoder_state), + .mb_num(mb_num), + .TotalCoeff(TotalCoeff), + .start_code_prefix_found(start_code_prefix_found), + .pc_2to0(pc[2:0]), + .deblocking_filter_control_present_flag(deblocking_filter_control_present_flag), + .disable_deblocking_filter_idc(disable_deblocking_filter_idc), + .end_of_one_residual_block(end_of_one_residual_block), + .Intra4x4PredMode_mbAddrB_cs_n(Intra4x4PredMode_mbAddrB_cs_n), + .mvx_mbAddrB_cs_n(mvx_mbAddrB_cs_n), + .mvy_mbAddrB_cs_n(mvy_mbAddrB_cs_n), + .mvx_mbAddrC_cs_n(mvx_mbAddrC_cs_n), + .mvy_mbAddrC_cs_n(mvy_mbAddrC_cs_n), + .LumaLevel_mbAddrB_cs_n(LumaLevel_mbAddrB_cs_n), + .ChromaLevel_Cb_mbAddrB_cs_n(ChromaLevel_Cb_mbAddrB_cs_n), + .ChromaLevel_Cr_mbAddrB_cs_n(ChromaLevel_Cr_mbAddrB_cs_n), + .trigger_CAVLC(trigger_CAVLC), + .blk4x4_rec_counter(blk4x4_rec_counter), + .end_of_DCBlk_IQIT(end_of_DCBlk_IQIT), + .end_of_one_blk4x4_sum(end_of_one_blk4x4_sum), + .end_of_MB_DEC(end_of_MB_DEC), + .disable_DF(disable_DF), + .bs_dec_counter(bs_dec_counter), + + .gclk_parser(gclk_parser), + .gclk_nal(gclk_nal), + .gclk_slice(gclk_slice), + .gclk_sps(gclk_sps), + .gclk_pps(gclk_pps), + .gclk_slice_header(gclk_slice_header), + .gclk_slice_data(gclk_slice_data), + .gclk_residual(gclk_residual), + .gclk_cavlc(gclk_cavlc), + .gclk_Intra4x4PredMode_mbAddrB_RF(gclk_Intra4x4PredMode_mbAddrB_RF), + .gclk_mvx_mbAddrB_RF(gclk_mvx_mbAddrB_RF), + .gclk_mvy_mbAddrB_RF(gclk_mvy_mbAddrB_RF), + .gclk_mvx_mbAddrC_RF(gclk_mvx_mbAddrC_RF), + .gclk_mvy_mbAddrC_RF(gclk_mvy_mbAddrC_RF), + .gclk_LumaLevel_mbAddrB_RF(gclk_LumaLevel_mbAddrB_RF), + .gclk_ChromaLevel_Cb_mbAddrB_RF(gclk_ChromaLevel_Cb_mbAddrB_RF), + .gclk_ChromaLevel_Cr_mbAddrB_RF(gclk_ChromaLevel_Cr_mbAddrB_RF), + .gclk_bs_dec(gclk_bs_dec), + .end_of_one_frame(end_of_one_frame) + ); + BitStream_parser_FSM BitStream_parser_FSM( + .clk(clk), + .reset_n(reset_n), + .end_of_one_blk4x4_sum(end_of_one_blk4x4_sum), + .end_of_MB_DEC(end_of_MB_DEC), + .gclk_parser(gclk_parser), + .gclk_nal(gclk_nal), + .gclk_slice(gclk_slice), + .gclk_sps(gclk_sps), + .gclk_pps(gclk_pps), + .gclk_slice_header(gclk_slice_header), + .gclk_slice_data(gclk_slice_data), + .gclk_residual(gclk_residual), + .gclk_cavlc(gclk_cavlc), + .trigger_CAVLC(trigger_CAVLC), + .BitStream_buffer_valid_n(BitStream_buffer_valid_n), + .nal_unit_type(nal_unit_type), + .slice_type(slice_type), + .num_ref_idx_active_override_flag(num_ref_idx_active_override_flag), + .deblocking_filter_control_present_flag(deblocking_filter_control_present_flag), + .disable_deblocking_filter_idc(disable_deblocking_filter_idc), + .mb_skip_run(mb_skip_run), + .mb_type_general(mb_type_general), + .prev_intra4x4_pred_mode_flag(prev_intra4x4_pred_mode_flag), + .CodedBlockPatternLuma(CodedBlockPatternLuma), + .CodedBlockPatternChroma(CodedBlockPatternChroma), + .pc_2to0(pc[2:0]), + .NumSubMbPart(NumSubMbPart), + .NumMbPart(NumMbPart), + .TotalCoeff(TotalCoeff), + .TrailingOnes(TrailingOnes), + .maxNumCoeff(maxNumCoeff), + .zerosLeft(zerosLeft), + .run(run), + + .parser_state(parser_state), + .nal_unit_state(nal_unit_state), + .slice_layer_wo_partitioning_state(slice_layer_wo_partitioning_state), + .slice_header_state(slice_header_state), + .slice_header_s6(slice_header_s6), + .ref_pic_list_reordering_state(ref_pic_list_reordering_state), + .dec_ref_pic_marking_state(dec_ref_pic_marking_state), + .slice_data_state(slice_data_state), + .sub_mb_pred_state(sub_mb_pred_state), + .mb_pred_state(mb_pred_state), + .seq_parameter_set_state(seq_parameter_set_state), + .pic_parameter_set_state(pic_parameter_set_state), + .residual_state(residual_state), + .cavlc_decoder_state(cavlc_decoder_state), + .heading_one_en(heading_one_en), + .pic_num(pic_num), + .mb_num(mb_num), + .mb_num_h(mb_num_h), + .mb_num_v(mb_num_v), + .NextMB_IsSkip(NextMB_IsSkip), + .LowerMB_IsSkip(LowerMB_IsSkip), + .Is_skip_run_entry(Is_skip_run_entry), + .Is_skip_run_end(Is_skip_run_end), + .luma4x4BlkIdx(luma4x4BlkIdx), + .mbPartIdx(mbPartIdx), + .subMbPartIdx(subMbPartIdx), + .compIdx(compIdx), + .i8x8(i8x8), + .i4x4(i4x4), + .i4x4_CbCr(i4x4_CbCr), + .coeffNum(coeffNum), + .i_level(i_level), + .i_run(i_run), + .i_TotalCoeff(i_TotalCoeff), + .suffix_length_initialized(suffix_length_initialized), + .IsRunLoop(IsRunLoop) + ); + pc_decoding pc_decoding ( + .clk(clk), + .reset_n(reset_n), + .parser_state(parser_state), + .nal_unit_state(nal_unit_state), + .slice_header_state(slice_header_state), + .ref_pic_list_reordering_state(ref_pic_list_reordering_state), + .dec_ref_pic_marking_state(dec_ref_pic_marking_state), + .slice_data_state(slice_data_state), + .sub_mb_pred_state(sub_mb_pred_state), + .mb_pred_state(mb_pred_state), + .seq_parameter_set_state(seq_parameter_set_state), + .pic_parameter_set_state(pic_parameter_set_state), + .exp_golomb_len(exp_golomb_len), + .dependent_variable_len(dependent_variable_len), + .cavlc_consumed_bits_len(cavlc_consumed_bits_len), + .pc(pc) + ); + heading_one_detector heading_one_detector ( + .heading_one_en(heading_one_en), + .BitStream_buffer_output(BitStream_buffer_output), + .heading_one_pos(heading_one_pos) + ); + exp_golomb_decoding exp_golomb_decoding ( + .reset_n(reset_n), + .heading_one_pos(heading_one_pos), + .BitStream_buffer_output(BitStream_buffer_output), + .num_ref_idx_l0_active_minus1(num_ref_idx_l0_active_minus1), + .exp_golomb_decoding_output(exp_golomb_decoding_output), + .exp_golomb_len(exp_golomb_len), + .slice_header_state(slice_header_state), + .slice_data_state(slice_data_state), + .mb_pred_state(mb_pred_state), + .sub_mb_pred_state(sub_mb_pred_state), + .seq_parameter_set_state(seq_parameter_set_state), + .pic_parameter_set_state(pic_parameter_set_state) + ); + dependent_variable_decoding dependent_variable_decoding ( + .slice_header_state(slice_header_state), + .log2_max_frame_num_minus4(log2_max_frame_num_minus4), + .log2_max_pic_order_cnt_lsb_minus4(log2_max_pic_order_cnt_lsb_minus4), + .BitStream_buffer_output(BitStream_buffer_output), + .dependent_variable_len(dependent_variable_len), + .dependent_variable_decoding_output(dependent_variable_decoding_output) + ); + QP_decoding QP_decoding ( + .clk(clk), + .reset_n(reset_n), + .slice_header_state(slice_header_state), + .slice_data_state(slice_data_state), + .pic_init_qp_minus26(pic_init_qp_minus26), + .exp_golomb_decoding_output_5to0(exp_golomb_decoding_output[5:0]), + .chroma_qp_index_offset(chroma_qp_index_offset), + .QPy(QPy), + .QPc(QPc) + ); + CodedBlockPattern_decoding CodedBlockPattern_decoding ( + .clk(clk), + .reset_n(reset_n), + .slice_data_state(slice_data_state), + .slice_type(slice_type), + .mb_type(mb_type), + .mb_type_general(mb_type_general), + .exp_golomb_decoding_output_5to0(exp_golomb_decoding_output[5:0]), + .CodedBlockPatternLuma(CodedBlockPatternLuma), + .CodedBlockPatternChroma(CodedBlockPatternChroma) + ); + Intra4x4_PredMode_decoding Intra4x4_PredMode_decoding ( + .clk(clk), + .reset_n(reset_n), + .mb_pred_state(mb_pred_state), + .luma4x4BlkIdx(luma4x4BlkIdx), + .mb_num_h(mb_num_h), + .mb_num_v(mb_num_v), + .MBTypeGen_mbAddrA(MBTypeGen_mbAddrA), + .MBTypeGen_mbAddrB_reg(MBTypeGen_mbAddrB_reg), + .constrained_intra_pred_flag(constrained_intra_pred_flag), + .rem_intra4x4_pred_mode(rem_intra4x4_pred_mode), + .prev_intra4x4_pred_mode_flag(prev_intra4x4_pred_mode_flag), + .Intra4x4PredMode_mbAddrB_dout(Intra4x4PredMode_mbAddrB_dout), + //pic_num can be wired out for debug purpose + //.pic_num(pic_num), + + .Intra4x4PredMode_CurrMb(Intra4x4_predmode_CurrMb), + .Intra4x4PredMode_mbAddrB_cs_n(Intra4x4PredMode_mbAddrB_cs_n), + .Intra4x4PredMode_mbAddrB_wr_n(Intra4x4PredMode_mbAddrB_wr_n), + .Intra4x4PredMode_mbAddrB_rd_addr(Intra4x4PredMode_mbAddrB_rd_addr), + .Intra4x4PredMode_mbAddrB_wr_addr(Intra4x4PredMode_mbAddrB_wr_addr), + .Intra4x4PredMode_mbAddrB_din(Intra4x4PredMode_mbAddrB_din) + ); + ram_async_1r_sync_1w # (`Intra4x4_PredMode_RF_data_width,`Intra4x4_PredMode_RF_data_depth) + Intra4x4_PredMode_RF ( + .clk(gclk_Intra4x4PredMode_mbAddrB_RF), + .rst_n(reset_n), + .cs_n(Intra4x4PredMode_mbAddrB_cs_n), + .wr_n(Intra4x4PredMode_mbAddrB_wr_n), + .rd_addr(Intra4x4PredMode_mbAddrB_rd_addr), + .wr_addr(Intra4x4PredMode_mbAddrB_wr_addr), + .data_in(Intra4x4PredMode_mbAddrB_din), + .data_out(Intra4x4PredMode_mbAddrB_dout) + ); + Inter_mv_decoding Inter_mv_decoding ( + .clk(clk), + .reset_n(reset_n), + .Is_skip_run_entry(Is_skip_run_entry), + .Is_skip_run_end(Is_skip_run_end), + .slice_data_state(slice_data_state), + .mb_pred_state(mb_pred_state), + .sub_mb_pred_state(sub_mb_pred_state), + .mvd(mvd), + .mb_num(mb_num), + .mb_num_h(mb_num_h), + .mb_num_v(mb_num_v), + .mb_type_general(mb_type_general), + .sub_mb_type(sub_mb_type), + .end_of_MB_DEC(end_of_MB_DEC), + .mbPartIdx(mbPartIdx), + .subMbPartIdx(subMbPartIdx), + .compIdx(compIdx), + .MBTypeGen_mbAddrA(MBTypeGen_mbAddrA), + .MBTypeGen_mbAddrB_reg(MBTypeGen_mbAddrB_reg), + .MBTypeGen_mbAddrD(MBTypeGen_mbAddrD), + .mvx_mbAddrB_dout(mvx_mbAddrB_dout), + .mvy_mbAddrB_dout(mvy_mbAddrB_dout), + .mvx_mbAddrC_dout(mvx_mbAddrC_dout), + .mvy_mbAddrC_dout(mvy_mbAddrC_dout), + .mv_mbAddrB_rd_for_DF(mv_mbAddrB_rd_for_DF), + + .skip_mv_calc(skip_mv_calc), + .Is_skipMB_mv_calc(Is_skipMB_mv_calc), + .mvx_mbAddrA(mvx_mbAddrA), + .mvy_mbAddrA(mvy_mbAddrA), + .mvx_mbAddrB_cs_n(mvx_mbAddrB_cs_n), + .mvx_mbAddrB_wr_n(mvx_mbAddrB_wr_n), + .mvx_mbAddrB_rd_addr(mvx_mbAddrB_rd_addr), + .mvx_mbAddrB_wr_addr(mvx_mbAddrB_wr_addr), + .mvx_mbAddrB_din(mvx_mbAddrB_din), + .mvy_mbAddrB_cs_n(mvy_mbAddrB_cs_n), + .mvy_mbAddrB_wr_n(mvy_mbAddrB_wr_n), + .mvy_mbAddrB_rd_addr(mvy_mbAddrB_rd_addr), + .mvy_mbAddrB_wr_addr(mvy_mbAddrB_wr_addr), + .mvy_mbAddrB_din(mvy_mbAddrB_din), + .mvx_mbAddrC_cs_n(mvx_mbAddrC_cs_n), + .mvx_mbAddrC_wr_n(mvx_mbAddrC_wr_n), + .mvx_mbAddrC_rd_addr(mvx_mbAddrC_rd_addr), + .mvx_mbAddrC_wr_addr(mvx_mbAddrC_wr_addr), + .mvx_mbAddrC_din(mvx_mbAddrC_din), + .mvy_mbAddrC_cs_n(mvy_mbAddrC_cs_n), + .mvy_mbAddrC_wr_n(mvy_mbAddrC_wr_n), + .mvy_mbAddrC_rd_addr(mvy_mbAddrC_rd_addr), + .mvy_mbAddrC_wr_addr(mvy_mbAddrC_wr_addr), + .mvy_mbAddrC_din(mvy_mbAddrC_din), + .mv_is16x16(mv_is16x16), + .mvx_CurrMb0(mvx_CurrMb0), + .mvx_CurrMb1(mvx_CurrMb1), + .mvx_CurrMb2(mvx_CurrMb2), + .mvx_CurrMb3(mvx_CurrMb3), + .mvy_CurrMb0(mvy_CurrMb0), + .mvy_CurrMb1(mvy_CurrMb1), + .mvy_CurrMb2(mvy_CurrMb2), + .mvy_CurrMb3(mvy_CurrMb3) + ); + ram_async_1r_sync_1w # (`mvx_mbAddrB_RF_data_width,`mvx_mbAddrB_RF_data_depth) + mvx_mbAddrB_RF ( + .clk(gclk_mvx_mbAddrB_RF), + .rst_n(reset_n), + .cs_n(mvx_mbAddrB_cs_n), + .wr_n(mvx_mbAddrB_wr_n), + .rd_addr(mvx_mbAddrB_rd_addr), + .wr_addr(mvx_mbAddrB_wr_addr), + .data_in(mvx_mbAddrB_din), + .data_out(mvx_mbAddrB_dout) + ); + ram_async_1r_sync_1w # (`mvy_mbAddrB_RF_data_width,`mvy_mbAddrB_RF_data_depth) + mvy_mbAddrB_RF ( + .clk(gclk_mvy_mbAddrB_RF), + .rst_n(reset_n), + .cs_n(mvy_mbAddrB_cs_n), + .wr_n(mvy_mbAddrB_wr_n), + .rd_addr(mvy_mbAddrB_rd_addr), + .wr_addr(mvy_mbAddrB_wr_addr), + .data_in(mvy_mbAddrB_din), + .data_out(mvy_mbAddrB_dout) + ); + ram_async_1r_sync_1w # (`mvx_mbAddrC_RF_data_width,`mvx_mbAddrC_RF_data_depth) + mvx_mbAddrC_RF ( + .clk(gclk_mvx_mbAddrC_RF), + .rst_n(reset_n), + .cs_n(mvx_mbAddrC_cs_n), + .wr_n(mvx_mbAddrC_wr_n), + .rd_addr(mvx_mbAddrC_rd_addr), + .wr_addr(mvx_mbAddrC_wr_addr), + .data_in(mvx_mbAddrC_din), + .data_out(mvx_mbAddrC_dout) + ); + ram_async_1r_sync_1w # (`mvy_mbAddrC_RF_data_width,`mvy_mbAddrC_RF_data_depth) + mvy_mbAddrC_RF ( + .clk(gclk_mvy_mbAddrC_RF), + .rst_n(reset_n), + .cs_n(mvy_mbAddrC_cs_n), + .wr_n(mvy_mbAddrC_wr_n), + .rd_addr(mvy_mbAddrC_rd_addr), + .wr_addr(mvy_mbAddrC_wr_addr), + .data_in(mvy_mbAddrC_din), + .data_out(mvy_mbAddrC_dout) + ); + syntax_decoding syntax_decoding ( + .clk(clk), + .reset_n(reset_n), + .mb_num_h(mb_num_h), + .mb_num_v(mb_num_v), + .end_of_MB_DEC(end_of_MB_DEC), + .pin_disable_DF(pin_disable_DF), + .parser_state(parser_state), + .nal_unit_state(nal_unit_state), + .seq_parameter_set_state(seq_parameter_set_state), + .pic_parameter_set_state(pic_parameter_set_state), + .slice_header_state(slice_header_state), + .slice_data_state(slice_data_state), + .mb_pred_state(mb_pred_state), + .sub_mb_pred_state(sub_mb_pred_state), + .exp_golomb_decoding_output(exp_golomb_decoding_output), + .BitStream_buffer_output(BitStream_buffer_output), + .dependent_variable_decoding_output(dependent_variable_decoding_output), + .mbPartIdx(mbPartIdx), + + .nal_unit_type(nal_unit_type), + .start_code_prefix_found(start_code_prefix_found), + .deblocking_filter_control_present_flag(deblocking_filter_control_present_flag), + .disable_deblocking_filter_idc(disable_deblocking_filter_idc), + .disable_DF(disable_DF), + .slice_alpha_c0_offset_div2(slice_alpha_c0_offset_div2), + .slice_beta_offset_div2(slice_beta_offset_div2), + .mb_skip_run(mb_skip_run), + .NumMbPart(NumMbPart), + .NumSubMbPart(NumSubMbPart), + .MBTypeGen_mbAddrA(MBTypeGen_mbAddrA), + .MBTypeGen_mbAddrD(MBTypeGen_mbAddrD), + .MBTypeGen_mbAddrB_reg(MBTypeGen_mbAddrB_reg), + .log2_max_frame_num_minus4(log2_max_frame_num_minus4), + .log2_max_pic_order_cnt_lsb_minus4(log2_max_pic_order_cnt_lsb_minus4), + .constrained_intra_pred_flag(constrained_intra_pred_flag), + .num_ref_idx_active_override_flag(num_ref_idx_active_override_flag), + .num_ref_idx_l0_active_minus1(num_ref_idx_l0_active_minus1), + .slice_type(slice_type), + .mb_type(mb_type), + .mb_type_general(mb_type_general), + .Intra16x16_predmode(Intra16x16_predmode), + .intra_chroma_pred_mode(Intra_chroma_predmode), + .sub_mb_type(sub_mb_type), + .pic_init_qp_minus26(pic_init_qp_minus26), + .chroma_qp_index_offset(chroma_qp_index_offset), + .rem_intra4x4_pred_mode(rem_intra4x4_pred_mode), + .prev_intra4x4_pred_mode_flag(prev_intra4x4_pred_mode_flag), + .mvd(mvd), + .mv_below8x8(mv_below8x8) + ); + cavlc_decoder cavlc_decoder( + .clk(clk), + .reset_n(reset_n), + .gclk_end_of_MB_DEC(gclk_end_of_MB_DEC), + .gclk_LumaLevel_mbAddrB_RF(gclk_LumaLevel_mbAddrB_RF), + .gclk_ChromaLevel_Cb_mbAddrB_RF(gclk_ChromaLevel_Cb_mbAddrB_RF), + .gclk_ChromaLevel_Cr_mbAddrB_RF(gclk_ChromaLevel_Cr_mbAddrB_RF), + .slice_data_state(slice_data_state), + .residual_state(residual_state), + .cavlc_decoder_state(cavlc_decoder_state), + .mb_num_h(mb_num_h), + .mb_num_v(mb_num_v), + .i8x8(i8x8), + .i4x4(i4x4), + .i4x4_CbCr(i4x4_CbCr), + .i_level(i_level), + .i_run(i_run), + .i_TotalCoeff(i_TotalCoeff), + .coeffNum(coeffNum), + .heading_one_pos(heading_one_pos), + .BitStream_buffer_output(BitStream_buffer_output), + .CodedBlockPatternLuma(CodedBlockPatternLuma), + .CodedBlockPatternChroma(CodedBlockPatternChroma), + .suffix_length_initialized(suffix_length_initialized), + .IsRunLoop(IsRunLoop), + + .Luma_8x8_AllZeroCoeff_mbAddrA(Luma_8x8_AllZeroCoeff_mbAddrA), + .LumaLevel_mbAddrA(LumaLevel_mbAddrA), + .LumaLevel_CurrMb0(LumaLevel_CurrMb0), + .LumaLevel_CurrMb1(LumaLevel_CurrMb1), + .LumaLevel_CurrMb2(LumaLevel_CurrMb2), + .LumaLevel_CurrMb3(LumaLevel_CurrMb3), + .LumaLevel_mbAddrB_dout(LumaLevel_mbAddrB_dout), + .LumaLevel_mbAddrB_cs_n(LumaLevel_mbAddrB_cs_n), + .ChromaLevel_Cb_mbAddrB_cs_n(ChromaLevel_Cb_mbAddrB_cs_n), + .ChromaLevel_Cr_mbAddrB_cs_n(ChromaLevel_Cr_mbAddrB_cs_n), + .end_of_one_residual_block(end_of_one_residual_block), + .end_of_NonZeroCoeff_CAVLC(end_of_NonZeroCoeff_CAVLC), + .cavlc_consumed_bits_len(cavlc_consumed_bits_len), + .TotalCoeff(TotalCoeff), + .TrailingOnes(TrailingOnes), + .maxNumCoeff(maxNumCoeff), + .zerosLeft(zerosLeft), + .run(run), + .coeffLevel_0(coeffLevel_0), + .coeffLevel_1(coeffLevel_1), + .coeffLevel_2(coeffLevel_2), + .coeffLevel_3(coeffLevel_3), + .coeffLevel_4(coeffLevel_4), + .coeffLevel_5(coeffLevel_5), + .coeffLevel_6(coeffLevel_6), + .coeffLevel_7(coeffLevel_7), + .coeffLevel_8(coeffLevel_8), + .coeffLevel_9(coeffLevel_9), + .coeffLevel_10(coeffLevel_10), + .coeffLevel_11(coeffLevel_11), + .coeffLevel_12(coeffLevel_12), + .coeffLevel_13(coeffLevel_13), + .coeffLevel_14(coeffLevel_14), + .coeffLevel_15(coeffLevel_15) + ); + bs_decoding bs_decoding ( + .clk(clk), + .reset_n(reset_n), + .gclk_end_of_MB_DEC(gclk_end_of_MB_DEC), + .gclk_bs_dec(gclk_bs_dec), + .end_of_MB_DEC(end_of_MB_DEC), + .end_of_one_blk4x4_sum(end_of_one_blk4x4_sum), + .mb_num_h(mb_num_h), + .mb_num_v(mb_num_v), + .disable_DF(disable_DF), + .blk4x4_rec_counter(blk4x4_rec_counter), + .CodedBlockPatternLuma(CodedBlockPatternLuma), + .mb_type_general(mb_type_general), + .slice_data_state(slice_data_state), + .residual_state(residual_state), + .MBTypeGen_mbAddrA(MBTypeGen_mbAddrA), + .MBTypeGen_mbAddrB_reg(MBTypeGen_mbAddrB_reg), + .end_of_one_residual_block(end_of_one_residual_block), + .TotalCoeff(TotalCoeff), + .curr_DC_IsZero(curr_DC_IsZero), + .Is_skipMB_mv_calc(Is_skipMB_mv_calc), + .mvx_mbAddrA(mvx_mbAddrA), + .mvy_mbAddrA(mvy_mbAddrA), + .mvx_mbAddrB_dout(mvx_mbAddrB_dout), + .mvy_mbAddrB_dout(mvy_mbAddrB_dout), + .mvx_CurrMb0(mvx_CurrMb0), + .mvx_CurrMb1(mvx_CurrMb1), + .mvx_CurrMb2(mvx_CurrMb2), + .mvx_CurrMb3(mvx_CurrMb3), + .mvy_CurrMb0(mvy_CurrMb0), + .mvy_CurrMb1(mvy_CurrMb1), + .mvy_CurrMb2(mvy_CurrMb2), + .mvy_CurrMb3(mvy_CurrMb3), + + .bs_dec_counter(bs_dec_counter), + .end_of_BS_DEC(end_of_BS_DEC), + .mv_mbAddrB_rd_for_DF(mv_mbAddrB_rd_for_DF), + .bs_V0(bs_V0), + .bs_V1(bs_V1), + .bs_V2(bs_V2), + .bs_V3(bs_V3), + .bs_H0(bs_H0), + .bs_H1(bs_H1), + .bs_H2(bs_H2), + .bs_H3(bs_H3) + ); +endmodule + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/BitStream_parser_FSM_gating.v b/demo_chip_rtl/rtl/nova/tags/Start/src/BitStream_parser_FSM_gating.v new file mode 100644 index 0000000..5989a40 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/BitStream_parser_FSM_gating.v @@ -0,0 +1,639 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : BitStream_parser_FSM_gating.v +// Generated : June 26,2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// BitStream_parser_FSM,clock gating version +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module BitStream_parser_FSM (clk,reset_n,end_of_one_blk4x4_sum,end_of_MB_DEC, + gclk_parser,gclk_nal,gclk_slice,gclk_sps,gclk_pps,gclk_slice_header, + gclk_slice_data,gclk_residual,gclk_cavlc, + trigger_CAVLC,BitStream_buffer_valid_n,nal_unit_type, + slice_type,num_ref_idx_active_override_flag, + deblocking_filter_control_present_flag,disable_deblocking_filter_idc, + mb_skip_run,mb_type_general,prev_intra4x4_pred_mode_flag,CodedBlockPatternLuma, + CodedBlockPatternChroma,pc_2to0,NumSubMbPart,NumMbPart, + TotalCoeff,TrailingOnes,maxNumCoeff,zerosLeft,run, + + parser_state,nal_unit_state,slice_layer_wo_partitioning_state,slice_header_state,slice_header_s6, + ref_pic_list_reordering_state,dec_ref_pic_marking_state,slice_data_state,sub_mb_pred_state, + mb_pred_state,seq_parameter_set_state,pic_parameter_set_state,residual_state,cavlc_decoder_state, + heading_one_en,pic_num,mb_num,mb_num_h,mb_num_v, + NextMB_IsSkip,LowerMB_IsSkip,Is_skip_run_entry,Is_skip_run_end, + luma4x4BlkIdx,mbPartIdx,subMbPartIdx,compIdx,i8x8,i4x4,i4x4_CbCr, + coeffNum,i_level,i_run,i_TotalCoeff, + suffix_length_initialized,IsRunLoop); + input clk; + input reset_n; + input end_of_one_blk4x4_sum; + input end_of_MB_DEC; + input gclk_parser; + input gclk_nal; + input gclk_slice; + input gclk_sps; + input gclk_pps; + input gclk_slice_header; + input gclk_slice_data; + input gclk_residual; + input gclk_cavlc; + input trigger_CAVLC; + input BitStream_buffer_valid_n; + input [4:0] nal_unit_type; + input [2:0] slice_type; + input num_ref_idx_active_override_flag; + input deblocking_filter_control_present_flag; + input [1:0] disable_deblocking_filter_idc; + input [6:0] mb_skip_run; + input [3:0] mb_type_general; + input prev_intra4x4_pred_mode_flag; + input [3:0] CodedBlockPatternLuma; + input [1:0] CodedBlockPatternChroma; + input [2:0] pc_2to0; + input [2:0] NumMbPart; + input [2:0] NumSubMbPart; + input [4:0] TotalCoeff; + input [1:0] TrailingOnes; + input [4:0] maxNumCoeff; + input [3:0] zerosLeft; + input [3:0] run; + + output [1:0] parser_state; + output [2:0] nal_unit_state; + output [1:0] slice_layer_wo_partitioning_state; + output [3:0] slice_header_state; + output slice_header_s6; + output [2:0] ref_pic_list_reordering_state; + output [1:0] dec_ref_pic_marking_state; + output [3:0] slice_data_state; + output [1:0] sub_mb_pred_state; + output [2:0] mb_pred_state; + output [3:0] seq_parameter_set_state; + output [3:0] pic_parameter_set_state; + output [3:0] residual_state; + output [3:0] cavlc_decoder_state; + output heading_one_en; + output [5:0] pic_num; + output [6:0] mb_num; + output [3:0] mb_num_h; + output [3:0] mb_num_v; + output NextMB_IsSkip; + output LowerMB_IsSkip; + output Is_skip_run_entry; + output Is_skip_run_end; + output [3:0] luma4x4BlkIdx; + output [1:0] mbPartIdx; + output [1:0] subMbPartIdx; + output compIdx; + output [1:0] i8x8,i4x4; + output [1:0] i4x4_CbCr; + output [3:0] coeffNum; + output [3:0] i_level; + output [3:0] i_run; + output [3:0] i_TotalCoeff; + output suffix_length_initialized; + output IsRunLoop; + + reg [1:0] parser_state; + reg [2:0] nal_unit_state; + reg [1:0] slice_layer_wo_partitioning_state; + reg [3:0] seq_parameter_set_state; + reg [3:0] pic_parameter_set_state; + reg [3:0] slice_header_state; + reg [2:0] ref_pic_list_reordering_state; + reg [1:0] dec_ref_pic_marking_state; + reg [3:0] slice_data_state; + reg [2:0] mb_pred_state; + reg [1:0] sub_mb_pred_state; + reg [3:0] residual_state; + reg [3:0] cavlc_decoder_state; + + wire heading_one_en; + reg [6:0] mb_num; + reg [3:0] mb_num_h; + reg [3:0] mb_num_v; + reg [1:0] mbPartIdx; + reg [1:0] subMbPartIdx; + reg compIdx; + reg [1:0] i8x8,i4x4; + reg [1:0] i4x4_CbCr; + reg [3:0] coeffNum; + reg [3:0] coeffNum_reg; + reg [3:0] i_level,i_run,i_TotalCoeff; + reg [6:0] count_mb_skip_run;//number of MBs to be skipped + reg [7:0] count_pcm_byte; + reg [3:0] luma4x4BlkIdx; + reg [5:0] pic_num; + reg suffix_length_initialized; + reg IsRunLoop; + + /* + // synopsys translate_off + integer tracefile; + initial + begin + tracefile = $fopen("trace.txt"); + end + // synopsys translate_on + */ + + //-------------- + //parser_state + //-------------- + always @ (posedge gclk_parser or negedge reset_n) + if (reset_n == 0) + parser_state <= `rst_parser; + else + case (parser_state) + `rst_parser :parser_state <= (BitStream_buffer_valid_n == 1'b0)? `start_code_prefix:`rst_parser; + `start_code_prefix:parser_state <= `nal_unit; + `nal_unit :parser_state <= `rst_parser; + endcase + //--------------- + //nal_unit_state + //--------------- + always @ (posedge gclk_nal or negedge reset_n) + if (reset_n == 0) + nal_unit_state <= `rst_nal_unit; + else + case (nal_unit_state) + `rst_nal_unit:nal_unit_state <= `forbidden_zero_bit_2_nal_unit_type; + `forbidden_zero_bit_2_nal_unit_type: + case (nal_unit_type) + 5'b00001:nal_unit_state <= `slice_layer_non_IDR_rbsp; + 5'b00101:nal_unit_state <= `slice_layer_IDR_rbsp; + 5'b00111:nal_unit_state <= `seq_parameter_set_rbsp; + 5'b01000:nal_unit_state <= `pic_parameter_set_rbsp; + endcase + `slice_layer_non_IDR_rbsp,`slice_layer_IDR_rbsp:nal_unit_state <= `rbsp_trailing_one_bit; + `seq_parameter_set_rbsp :nal_unit_state <= `rbsp_trailing_one_bit; + `pic_parameter_set_rbsp :nal_unit_state <= `rbsp_trailing_one_bit; + `rbsp_trailing_one_bit :nal_unit_state <= (pc_2to0 == 3'b000)? `rst_nal_unit:`rbsp_trailing_zero_bits; + `rbsp_trailing_zero_bits:nal_unit_state <= `rst_nal_unit; + endcase + //---------------------------------- + //slice_layer_wo_partitioning_state + //---------------------------------- + always @ (posedge gclk_slice or negedge reset_n) + if (reset_n == 1'b0) + slice_layer_wo_partitioning_state <= `rst_slice_layer_wo_partitioning; + else + case (slice_layer_wo_partitioning_state) + `rst_slice_layer_wo_partitioning :slice_layer_wo_partitioning_state <= `slice_header; + `slice_header :slice_layer_wo_partitioning_state <= `slice_data; + `slice_data :slice_layer_wo_partitioning_state <= `rst_slice_layer_wo_partitioning; + endcase + //------------------------ + //seq_parameter_set_state + //------------------------ + always @ (posedge gclk_sps or negedge reset_n) + if (reset_n == 0) + seq_parameter_set_state <= `rst_seq_parameter_set; + else + case (seq_parameter_set_state) + `rst_seq_parameter_set :seq_parameter_set_state <= `fixed_header; + `fixed_header :seq_parameter_set_state <= `level_idc_s; + `level_idc_s :seq_parameter_set_state <= `seq_parameter_set_id_sps_s; + `seq_parameter_set_id_sps_s :seq_parameter_set_state <= `log2_max_frame_num_minus4_s; + `log2_max_frame_num_minus4_s :seq_parameter_set_state <= `pic_order_cnt_type_s; + `pic_order_cnt_type_s :seq_parameter_set_state <= `log2_max_pic_order_cnt_lsb_minus4_s; + `log2_max_pic_order_cnt_lsb_minus4_s :seq_parameter_set_state <= `num_ref_frames_s; + `num_ref_frames_s :seq_parameter_set_state <= `gaps_in_frame_num_value_allowed_flag_s; + `gaps_in_frame_num_value_allowed_flag_s :seq_parameter_set_state <= `pic_width_in_mbs_minus1_s; + `pic_width_in_mbs_minus1_s :seq_parameter_set_state <= `pic_height_in_map_units_minus1_s; + `pic_height_in_map_units_minus1_s :seq_parameter_set_state <= `frame_mbs_only_flag_2_frame_cropping_flag; + `frame_mbs_only_flag_2_frame_cropping_flag:seq_parameter_set_state <= `vui_parameter_present_flag_s; + `vui_parameter_present_flag_s :seq_parameter_set_state <= `rst_seq_parameter_set; + endcase + //------------------------ + //pic_parameter_set_state + //------------------------ + always @ (posedge gclk_pps or negedge reset_n) + if (reset_n == 0) + pic_parameter_set_state <= `rst_pic_parameter_set; + else + case (pic_parameter_set_state) + `rst_pic_parameter_set :pic_parameter_set_state <= `pic_parameter_set_id_pps_s; + `pic_parameter_set_id_pps_s :pic_parameter_set_state <= `seq_parameter_set_id_pps_s; + `seq_parameter_set_id_pps_s :pic_parameter_set_state <= `entropy_coding_mode_flag_2_pic_order_present_flag; + `entropy_coding_mode_flag_2_pic_order_present_flag :pic_parameter_set_state <= `num_slice_groups_minus1_s; + `num_slice_groups_minus1_s :pic_parameter_set_state <= `num_ref_idx_l0_active_minus1_pps_s; + `num_ref_idx_l0_active_minus1_pps_s :pic_parameter_set_state <= `num_ref_idx_l1_active_minus1_pps_s; + `num_ref_idx_l1_active_minus1_pps_s :pic_parameter_set_state <= `weighted_pred_flag_2_weighted_bipred_idc; + `weighted_pred_flag_2_weighted_bipred_idc :pic_parameter_set_state <= `pic_init_qp_minus26_s; + `pic_init_qp_minus26_s :pic_parameter_set_state <= `pic_init_qs_minus26_s; + `pic_init_qs_minus26_s :pic_parameter_set_state <= `chroma_qp_index_offset_s; + `chroma_qp_index_offset_s :pic_parameter_set_state <= `deblocking_filter_control_2_redundant_pic_cnt_present_flag; + `deblocking_filter_control_2_redundant_pic_cnt_present_flag:pic_parameter_set_state <= `rst_pic_parameter_set; + endcase + //------------------- + //slice_header_state + //------------------- + always @ (posedge gclk_slice_header or negedge reset_n) + if (reset_n == 0) + begin + slice_header_state <= `rst_slice_header; + ref_pic_list_reordering_state <= `rst_ref_pic_list_reordering; + dec_ref_pic_marking_state <= `rst_dec_ref_pic_marking; + end + else + case (slice_header_state) + `rst_slice_header :slice_header_state <= `first_mb_in_slice_s; + `first_mb_in_slice_s :slice_header_state <= `slice_type_s; + `slice_type_s :slice_header_state <= `pic_parameter_set_id_slice_header_s; + `pic_parameter_set_id_slice_header_s:slice_header_state <= `frame_num_s; + `frame_num_s: + if (nal_unit_type == 5'b00101) slice_header_state <= `idr_pic_id_s; + else slice_header_state <= `pic_order_cnt_lsb_s; + `idr_pic_id_s :slice_header_state <= `pic_order_cnt_lsb_s; + `pic_order_cnt_lsb_s: + if (slice_type == 3'b101) slice_header_state <= `num_ref_idx_active_override_flag_s; + else slice_header_state <= `dec_ref_pic_marking; + `num_ref_idx_active_override_flag_s: + if (num_ref_idx_active_override_flag == 1'b1) slice_header_state <= `num_ref_idx_l0_active_minus1_slice_header_s; + else slice_header_state <= `ref_pic_list_reordering; + `num_ref_idx_l0_active_minus1_slice_header_s :slice_header_state <= `ref_pic_list_reordering; + `ref_pic_list_reordering: + case (ref_pic_list_reordering_state) + `rst_ref_pic_list_reordering: + if (slice_type == 3'b101) + ref_pic_list_reordering_state <= `ref_pic_list_reordering_flag_l0_s; + else + begin + ref_pic_list_reordering_state <= `rst_ref_pic_list_reordering; + slice_header_state <= `dec_ref_pic_marking; + end + `ref_pic_list_reordering_flag_l0_s: + begin + ref_pic_list_reordering_state <= `rst_ref_pic_list_reordering; + slice_header_state <= `dec_ref_pic_marking; + end + endcase + `dec_ref_pic_marking: + case (dec_ref_pic_marking_state) + `rst_dec_ref_pic_marking: + dec_ref_pic_marking_state <= (nal_unit_type == 3'b101)? `no_output_of_prior_pics_flag_2_long_term_reference_flag:`adaptive_ref_pic_marking_mode_flag_s; + `no_output_of_prior_pics_flag_2_long_term_reference_flag: + begin + dec_ref_pic_marking_state <= `rst_dec_ref_pic_marking; + slice_header_state <= `slice_qp_delta_s; + end + `adaptive_ref_pic_marking_mode_flag_s: + begin + dec_ref_pic_marking_state <= `rst_dec_ref_pic_marking; + slice_header_state <= `slice_qp_delta_s; + end + endcase + `slice_qp_delta_s: + slice_header_state <= (deblocking_filter_control_present_flag == 1'b1)? `disable_deblocking_filter_idc_s:`rst_slice_header; + `disable_deblocking_filter_idc_s: + slice_header_state <= (disable_deblocking_filter_idc != 2'b01)? `slice_alpha_c0_offset_div2_s:`rst_slice_header; + `slice_alpha_c0_offset_div2_s:slice_header_state <= `slice_beta_offset_div2_s; + `slice_beta_offset_div2_s :slice_header_state <= `rst_slice_header; + endcase + + assign slice_header_s6 = (slice_header_state == `frame_num_s)? 1'b1:1'b0; + //------------------ + //slice_data_state + //------------------ + reg Is_skip_run_entry; //for trigger inter pred.Originally it's a wire type which will trigger inter_pred signal too early + //than expected:cause inter_pred rise up before mv_below8x8 is set to 4'b0 for P_skip.Thus the + //preload_counter after inter_pred will sample wrong mv_below8x8/mv_below8x8_curr. + //Then it is changed to reg type to appear one cycle later @ May 15,2006 + wire Is_skip_run_end; //for stop triggering inter pred + + always @ (posedge clk) + if (reset_n == 1'b0) + Is_skip_run_entry <= 1'b0; + else if (slice_data_state == `mb_skip_run_s && mb_skip_run != 0) + Is_skip_run_entry <= 1'b1; + else + Is_skip_run_entry <= 1'b0; + + assign Is_skip_run_end = (slice_data_state == `skip_run_duration && end_of_MB_DEC && (mb_num == 98 || count_mb_skip_run == (mb_skip_run - 1)))? 1'b1:1'b0; + + always @ (posedge gclk_slice_data or negedge reset_n) + if (reset_n == 0) + begin + slice_data_state <= `rst_slice_data; + mb_pred_state <= `rst_mb_pred; + sub_mb_pred_state <= `rst_sub_mb_pred; + end + else + case (slice_data_state) + `rst_slice_data :slice_data_state <= (slice_type != 3'b111)? `mb_skip_run_s:`mb_type_s; + `mb_skip_run_s :slice_data_state <= (mb_skip_run == 0)? `mb_type_s:`skip_run_duration; + `skip_run_duration:slice_data_state <= (mb_num == 98)? `rst_slice_data:(count_mb_skip_run < (mb_skip_run - 1))? `skip_run_duration:`mb_type_s; + `mb_type_s :slice_data_state <= (mb_type_general == `MB_P_8x8 || mb_type_general == `MB_P_8x8ref0)? `sub_mb_pred:`mb_pred; + `sub_mb_pred: + case (sub_mb_pred_state) + `rst_sub_mb_pred:sub_mb_pred_state <= `sub_mb_type_s; + `sub_mb_type_s :sub_mb_pred_state <= (mbPartIdx == 2'b11)? `sub_mvd_l0_s:`sub_mb_type_s; + `sub_mvd_l0_s: + if (mbPartIdx == 2'b11 && {1'b0,subMbPartIdx} == (NumSubMbPart - 1) && compIdx == 1'b1) + begin + sub_mb_pred_state <= `rst_sub_mb_pred; + slice_data_state <= `coded_block_pattern_s; + end + endcase + `mb_pred: + case (mb_pred_state) + `rst_mb_pred: + if (mb_type_general[3] == 1'b1) //Intra + mb_pred_state <= (mb_type_general == `MB_Intra4x4)? `prev_intra4x4_pred_mode_flag_s:`intra_chroma_pred_mode_s; + else + mb_pred_state <= `mvd_l0_s; + `prev_intra4x4_pred_mode_flag_s: + mb_pred_state <= (prev_intra4x4_pred_mode_flag == 1'b0)? `rem_intra4x4_pred_mode_s: + (luma4x4BlkIdx == 4'b1111)? `intra_chroma_pred_mode_s:`prev_intra4x4_pred_mode_flag_s; + `rem_intra4x4_pred_mode_s: + mb_pred_state <= (luma4x4BlkIdx == 4'b1111)? `intra_chroma_pred_mode_s:`prev_intra4x4_pred_mode_flag_s; + `intra_chroma_pred_mode_s: + begin + mb_pred_state <= `rst_mb_pred; + slice_data_state <= (mb_type_general[3:2] != 2'b10)? `coded_block_pattern_s:`mb_qp_delta_s; + end + `mvd_l0_s: + if ({1'b0,mbPartIdx} == (NumMbPart - 1) && compIdx == 1'b1) + begin + mb_pred_state <= `rst_mb_pred; + slice_data_state <= `coded_block_pattern_s; + end + endcase + `coded_block_pattern_s:slice_data_state <= (CodedBlockPatternLuma == 0 && CodedBlockPatternChroma == 0)? `residual:`mb_qp_delta_s; + `mb_qp_delta_s: + slice_data_state <= (CodedBlockPatternLuma == 0 && CodedBlockPatternChroma == 0 && mb_type_general[3:2] != 2'b10)? `mb_num_update:`residual; + `residual:slice_data_state <= `mb_num_update; + `mb_num_update:slice_data_state <= `rst_slice_data; + endcase + //--------------- + //residual_state + //--------------- + always @ (posedge gclk_residual or negedge reset_n) + if (reset_n == 1'b0) + residual_state <= `rst_residual; + else + case (residual_state) + `rst_residual: + if (mb_type_general[3] == 1'b1 && mb_type_general != `MB_Intra4x4)//Intra16x16 + residual_state <= `Intra16x16DCLevel_s; + else + residual_state <= (CodedBlockPatternLuma == 0)? `LumaLevel_0_s:`LumaLevel_s; + `Intra16x16DCLevel_s:residual_state <= (CodedBlockPatternLuma == 0)? `Intra16x16ACLevel_0_s:`Intra16x16ACLevel_s; + `Intra16x16ACLevel_s,`Intra16x16ACLevel_0_s,`LumaLevel_s,`LumaLevel_0_s: + residual_state <= (CodedBlockPatternChroma == 0)? `ChromaACLevel_0_s:`ChromaDCLevel_Cb_s; + `ChromaDCLevel_Cb_s:residual_state <= `ChromaDCLevel_Cr_s; + `ChromaDCLevel_Cr_s:residual_state <= (CodedBlockPatternChroma == 2'b01)? `ChromaACLevel_0_s:`ChromaACLevel_Cb_s; + `ChromaACLevel_Cb_s:residual_state <= `ChromaACLevel_Cr_s; + `ChromaACLevel_Cr_s:residual_state <= `rst_residual; + `ChromaACLevel_0_s :residual_state <= `rst_residual; + endcase + //-------------------- + //cavlc_decoder_state + //-------------------- + always @ (posedge gclk_cavlc or negedge reset_n) + if (reset_n == 1'b0) + cavlc_decoder_state <= `rst_cavlc_decoder; + else + case (cavlc_decoder_state) + `rst_cavlc_decoder :cavlc_decoder_state <= `nAnB_decoding_s; + `nAnB_decoding_s :cavlc_decoder_state <= `nC_decoding_s; + `nC_decoding_s :cavlc_decoder_state <= `NumCoeffTrailingOnes_LUT; + `NumCoeffTrailingOnes_LUT://add trigger_CAVLC to trap a special case:after all-zero CrDC2x2 CAVLC decoding. + //Without adding trigger_CAVLC here,the gclk_cavlc can not catch trigger_CAVLC + //because it rises up too early (rise up at NumCoeffTrailingOnes_LUT instead of rst_cavlc_decoder) + cavlc_decoder_state <= (TotalCoeff == 0)? ((trigger_CAVLC)? `nAnB_decoding_s:`rst_cavlc_decoder):(TrailingOnes == 0)? `LevelPrefix:`TrailingOnesSignFlag; + `TrailingOnesSignFlag:cavlc_decoder_state <= (TotalCoeff == {3'b0,TrailingOnes})?`total_zeros_LUT:`LevelPrefix; + `LevelPrefix :cavlc_decoder_state <= `LevelSuffix; + `LevelSuffix :cavlc_decoder_state <= ({1'b0,i_level} == TotalCoeff-1)? ((TotalCoeff == maxNumCoeff)?`LevelRunCombination:`total_zeros_LUT):`LevelPrefix; + `total_zeros_LUT :cavlc_decoder_state <= (TotalCoeff == 1)? `RunOfZeros:`run_before_LUT; + `run_before_LUT :cavlc_decoder_state <= `RunOfZeros; + `RunOfZeros :cavlc_decoder_state <= ({1'b0,i_run} == (TotalCoeff - 1) || {1'b0,i_run} == (TotalCoeff - 2) || zerosLeft == 0)? `LevelRunCombination:`run_before_LUT; + `LevelRunCombination :cavlc_decoder_state <= (i_TotalCoeff == 0)? `rst_cavlc_decoder:`LevelRunCombination; + endcase + assign heading_one_en = ( + seq_parameter_set_state == `seq_parameter_set_id_sps_s || + seq_parameter_set_state == `log2_max_frame_num_minus4_s || + seq_parameter_set_state == `pic_order_cnt_type_s || + seq_parameter_set_state == `log2_max_pic_order_cnt_lsb_minus4_s || + seq_parameter_set_state == `num_ref_frames_s || + seq_parameter_set_state == `pic_width_in_mbs_minus1_s || + seq_parameter_set_state == `pic_height_in_map_units_minus1_s || + pic_parameter_set_state == `pic_parameter_set_id_pps_s || + pic_parameter_set_state == `seq_parameter_set_id_pps_s || + pic_parameter_set_state == `num_slice_groups_minus1_s || + pic_parameter_set_state == `num_ref_idx_l0_active_minus1_pps_s || + pic_parameter_set_state == `num_ref_idx_l1_active_minus1_pps_s || + pic_parameter_set_state == `pic_init_qp_minus26_s || + pic_parameter_set_state == `pic_init_qs_minus26_s || + pic_parameter_set_state == `chroma_qp_index_offset_s || + slice_header_state == `first_mb_in_slice_s || + slice_header_state == `slice_type_s || + slice_header_state == `pic_parameter_set_id_slice_header_s || + slice_header_state == `idr_pic_id_s || + slice_header_state == `num_ref_idx_l0_active_minus1_slice_header_s || + slice_header_state == `slice_qp_delta_s || + slice_header_state == `disable_deblocking_filter_idc_s || + slice_header_state == `slice_alpha_c0_offset_div2_s || + slice_header_state == `slice_beta_offset_div2_s || + slice_data_state == `mb_skip_run_s || + slice_data_state == `mb_type_s || + slice_data_state == `coded_block_pattern_s || + slice_data_state == `mb_qp_delta_s || + mb_pred_state == `intra_chroma_pred_mode_s || + mb_pred_state == `mvd_l0_s || + sub_mb_pred_state == `sub_mb_type_s || + sub_mb_pred_state == `sub_mvd_l0_s || + cavlc_decoder_state == `NumCoeffTrailingOnes_LUT || + cavlc_decoder_state == `LevelPrefix || + cavlc_decoder_state == `total_zeros_LUT)? 1'b0:1'b1; + + //count_mb_skip_run + always @ (posedge gclk_slice_data or negedge reset_n) + if (reset_n == 1'b0) + count_mb_skip_run <= 1'b0; + else if (slice_data_state == `skip_run_duration) + count_mb_skip_run <= (mb_num == 98)? 0:(count_mb_skip_run < (mb_skip_run - 1))? (count_mb_skip_run + 1):0; + + assign NextMB_IsSkip = (slice_data_state == `skip_run_duration && (count_mb_skip_run < (mb_skip_run - 1)))? 1'b1:1'b0; + + reg LowerMB_IsSkip; + always @ (slice_data_state or mb_skip_run or count_mb_skip_run) + if (slice_data_state == `skip_run_duration) + begin + if (mb_skip_run < 13) + LowerMB_IsSkip <= 1'b0; + else + LowerMB_IsSkip <= (count_mb_skip_run < (mb_skip_run - 12))? 1'b1:1'b0; + end + else + LowerMB_IsSkip <= 1'b0; + + //mb_num_h + always @ (posedge gclk_slice_data or negedge reset_n) + if (reset_n == 1'b0) + mb_num_h <= 0; + else if (slice_data_state == `skip_run_duration || slice_data_state == `mb_num_update) + mb_num_h <= (mb_num_h == 10) ? 0:(mb_num_h + 1); + + //mb_num_v + always @ (posedge gclk_slice_data or negedge reset_n) + if (reset_n == 1'b0) + mb_num_v <= 0; + else if ((slice_data_state == `skip_run_duration || slice_data_state == `mb_num_update) && mb_num_h == 10) + mb_num_v <= (mb_num_v == 8) ? 0:(mb_num_v + 1); + + //mb_num + always @ (posedge gclk_slice_data or negedge reset_n) + if (reset_n == 1'b0) + mb_num <= 0; + else if (slice_data_state == `skip_run_duration || slice_data_state == `mb_num_update) + mb_num <= (mb_num == 98)? 0:(mb_num + 1); + + //pic_num + always @ (posedge gclk_slice_data or negedge reset_n) + if (reset_n == 1'b0) + pic_num <= 0; + else if ((slice_data_state == `skip_run_duration || slice_data_state == `mb_num_update) && mb_num == 98) + pic_num <= pic_num + 1; + + //luma4x4BlkIdx + always @ (posedge gclk_slice_data or negedge reset_n) + if (reset_n == 1'b0) + luma4x4BlkIdx <= 0; + else + case (mb_pred_state) + `prev_intra4x4_pred_mode_flag_s: + if (prev_intra4x4_pred_mode_flag == 1'b1) + luma4x4BlkIdx <= (luma4x4BlkIdx == 4'b1111)? 0:(luma4x4BlkIdx + 1); + `rem_intra4x4_pred_mode_s:luma4x4BlkIdx <= (luma4x4BlkIdx == 4'b1111)? 0:(luma4x4BlkIdx + 1); + endcase + + //mbPartIdx + always @ (posedge gclk_slice_data or negedge reset_n) + if (reset_n == 1'b0) + mbPartIdx <= 0; + else if (mb_pred_state == `mvd_l0_s && compIdx == 1'b1) + mbPartIdx <= ({1'b0,mbPartIdx} < (NumMbPart-1))? (mbPartIdx + 1):0; + else if (sub_mb_pred_state == `sub_mb_type_s) + mbPartIdx <= (mbPartIdx == 2'b11)? 0:(mbPartIdx + 1); + else if (sub_mb_pred_state == `sub_mvd_l0_s && {1'b0,subMbPartIdx} == NumSubMbPart - 1 && compIdx == 1'b1) + mbPartIdx <= (mbPartIdx == 2'b11)? 0:(mbPartIdx + 1); + + //subMbPartIdx + always @ (posedge gclk_slice_data or negedge reset_n) + if (reset_n == 1'b0) + subMbPartIdx <= 0; + else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1'b1) + subMbPartIdx <= ({1'b0,subMbPartIdx} < NumSubMbPart-1)? (subMbPartIdx + 1):0; + + //compIdx + always @ (posedge gclk_slice_data or negedge reset_n) + if (reset_n == 1'b0) + compIdx <= 0; + else if (mb_pred_state == `mvd_l0_s || sub_mb_pred_state == `sub_mvd_l0_s) + compIdx <= ~ compIdx; + + //i8x8 + always @ (posedge clk) + if (reset_n == 1'b0) + i8x8 <= 0; + else if (slice_data_state == `residual && residual_state == `rst_residual && mb_type_general != `MB_Intra16x16_CBPChroma0 && mb_type_general != `MB_Intra16x16_CBPChroma1 && mb_type_general != `MB_Intra16x16_CBPChroma2) + i8x8 <= 0; + else if ((residual_state == `Intra16x16ACLevel_s || residual_state == `LumaLevel_s) && end_of_one_blk4x4_sum == 1 && i4x4 == 2'b11) + i8x8 <= (i8x8 == 2'b11)? 0:(i8x8 + 1); + + //i4x4 + always @ (posedge clk) + if (reset_n == 1'b0) + i4x4 <= 0; + else if ((residual_state == `Intra16x16ACLevel_s || residual_state == `LumaLevel_s) && end_of_one_blk4x4_sum == 1) + i4x4 <= (i4x4 == 2'b11)? 0:(i4x4 + 1); + + //i4x4_CbCr + always @ (posedge clk) + if (reset_n == 1'b0) + i4x4_CbCr <= 0; + else if ((residual_state == `ChromaACLevel_Cb_s || residual_state == `ChromaACLevel_Cr_s) && end_of_one_blk4x4_sum == 1'b1) + i4x4_CbCr <= (i4x4_CbCr == 2'b11)? 0:(i4x4_CbCr + 1); + + //suffix_length_initialized + always @ (posedge gclk_cavlc or negedge reset_n) + if (reset_n == 1'b0) + suffix_length_initialized <= 1'b0; + else if (cavlc_decoder_state == `rst_cavlc_decoder) + suffix_length_initialized <= 1'b0; + else if (cavlc_decoder_state == `LevelPrefix) + suffix_length_initialized <= 1'b1; + + //i_level + always @ (posedge gclk_cavlc or negedge reset_n) + if (reset_n == 1'b0) + i_level <= 0; + else if (cavlc_decoder_state == `NumCoeffTrailingOnes_LUT) + i_level <= 0; + else if (cavlc_decoder_state == `TrailingOnesSignFlag) + i_level <= i_level + TrailingOnes; + else if (cavlc_decoder_state == `LevelSuffix && {1'b0,i_level} != (TotalCoeff-1)) + i_level <= i_level + 1; + + //i_run + always @ (posedge gclk_cavlc or negedge reset_n) + if (reset_n == 1'b0) + i_run <= 0; + else if (cavlc_decoder_state == `total_zeros_LUT) + i_run <= 0; + else if (cavlc_decoder_state == `RunOfZeros && {1'b0,i_run} != (TotalCoeff - 1) && {1'b0,i_run} != (TotalCoeff - 2) && zerosLeft != 0) + i_run <= i_run + 1; + + //i_TotalCoeff + always @ (posedge gclk_cavlc or negedge reset_n) + if (reset_n == 1'b0) + i_TotalCoeff <= 0; + //enter from LevelSuffix + else if (cavlc_decoder_state == `LevelSuffix && {1'b0,i_level} == (TotalCoeff-1) && TotalCoeff == maxNumCoeff) + i_TotalCoeff <= TotalCoeff - 1; + //enter from RunOfZeros + else if (cavlc_decoder_state == `RunOfZeros && ({1'b0,i_run} == (TotalCoeff - 1) || {1'b0,i_run} == (TotalCoeff - 2) || zerosLeft == 0)) + i_TotalCoeff <= TotalCoeff - 1; + //Inside LevelRunCombination loop + else if (cavlc_decoder_state == `LevelRunCombination && i_TotalCoeff != 0) + i_TotalCoeff <= i_TotalCoeff-1; + + //coeffNum + always @ (cavlc_decoder_state or run or coeffNum_reg) + if (cavlc_decoder_state == `nAnB_decoding_s) + coeffNum <= 4'b1111; + else if (cavlc_decoder_state == `LevelRunCombination) + coeffNum <= coeffNum_reg + run + 1; + else + coeffNum <= coeffNum_reg; + + always @ (posedge gclk_cavlc or negedge reset_n) + if (reset_n == 1'b0) + coeffNum_reg <= 0; + else + coeffNum_reg <= coeffNum; + + //IsRunLoop + always @ (posedge gclk_cavlc or negedge reset_n) + if (reset_n == 1'b0) + IsRunLoop <= 0; + else if (cavlc_decoder_state == `RunOfZeros) + IsRunLoop <= ({1'b0,i_run} == TotalCoeff - 1 || {1'b0,i_run} == TotalCoeff - 2 || zerosLeft == 0)? 1'b0:1'b1; + +endmodule + + + + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/CodedBlockPattern_decoding.v b/demo_chip_rtl/rtl/nova/tags/Start/src/CodedBlockPattern_decoding.v new file mode 100644 index 0000000..d9e8846 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/CodedBlockPattern_decoding.v @@ -0,0 +1,157 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : CodedBlockPattern_decoding.v +// Generated : June 5,2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Decoding CodedBlockPatternLuma & CodedBlockPatternChroma (Table9-4 Page156 of H.264/AVC standard 2003) +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module CodedBlockPattern_decoding (clk,reset_n,slice_data_state,slice_type,mb_type,mb_type_general, + exp_golomb_decoding_output_5to0,CodedBlockPatternLuma,CodedBlockPatternChroma); + input clk,reset_n; + input [3:0] slice_data_state; + input [2:0] slice_type; + input [4:0] mb_type; + input [3:0] mb_type_general; + input [5:0] exp_golomb_decoding_output_5to0; + output [3:0] CodedBlockPatternLuma; + output [1:0] CodedBlockPatternChroma; + reg [3:0] CodedBlockPatternLuma; + reg [1:0] CodedBlockPatternChroma; + + reg [3:0] CodedBlockPatternLuma_reg; + reg [1:0] CodedBlockPatternChroma_reg; + + always @ (posedge clk) + CodedBlockPatternLuma_reg <= (reset_n == 0)? 0:CodedBlockPatternLuma; + always @ (posedge clk) + CodedBlockPatternChroma_reg <= (reset_n == 0)? 0:CodedBlockPatternChroma; + + always @ (slice_data_state or mb_type_general or slice_type or mb_type or exp_golomb_decoding_output_5to0 + or CodedBlockPatternLuma_reg) + if (mb_type_general[3:2] == 2'b10)//Intra16x16 + begin + if (slice_type == 0 || slice_type == 5) //P_slice + CodedBlockPatternLuma <= (mb_type < 18)? 4'd0:4'd15; + else //I_slice + CodedBlockPatternLuma <= (mb_type < 13)? 4'd0:4'd15; + end + else if (slice_data_state == `coded_block_pattern_s) + case (mb_type_general[3]) + 1'b0: //Inter + if (exp_golomb_decoding_output_5to0 < 2) //CBP = 0,16 + CodedBlockPatternLuma <= 0; + else if (exp_golomb_decoding_output_5to0 < 6) //CBP =1,2,4,8 + case (exp_golomb_decoding_output_5to0[2:0]) + 3'b010:CodedBlockPatternLuma <= 4'd1; + 3'b011:CodedBlockPatternLuma <= 4'd2; + 3'b100:CodedBlockPatternLuma <= 4'd4; + 3'b101:CodedBlockPatternLuma <= 4'd8; + default:CodedBlockPatternLuma <= CodedBlockPatternLuma_reg; + endcase + else + case (exp_golomb_decoding_output_5to0) + 6 :CodedBlockPatternLuma <= 4'd0; + 24,32 :CodedBlockPatternLuma <= 4'd1; + 25,33 :CodedBlockPatternLuma <= 4'd2; + 7,20,36 :CodedBlockPatternLuma <= 4'd3; + 26,34 :CodedBlockPatternLuma <= 4'd4; + 8,21,37 :CodedBlockPatternLuma <= 4'd5; + 17,44,46:CodedBlockPatternLuma <= 4'd6; + 13,28,40:CodedBlockPatternLuma <= 4'd7; + 27,35 :CodedBlockPatternLuma <= 4'd8; + 18,45,47:CodedBlockPatternLuma <= 4'd9; + 9,22,38 :CodedBlockPatternLuma <= 4'd10; + 14,29,41:CodedBlockPatternLuma <= 4'd11; + 10,23,39:CodedBlockPatternLuma <= 4'd12; + 15,30,42:CodedBlockPatternLuma <= 4'd13; + 16,31,43:CodedBlockPatternLuma <= 4'd14; + 11,12,19:CodedBlockPatternLuma <= 4'd15; + default :CodedBlockPatternLuma <= CodedBlockPatternLuma_reg; + endcase + 1'b1: //Intra4x4 + if (exp_golomb_decoding_output_5to0 < 3) //CBP = 47,31,15 + CodedBlockPatternLuma <= 4'd15; + else + case (exp_golomb_decoding_output_5to0) + 3,16,41 :CodedBlockPatternLuma <= 4'd0; + 29,33,42:CodedBlockPatternLuma <= 4'd1; + 30,34,43:CodedBlockPatternLuma <= 4'd2; + 17,21,25:CodedBlockPatternLuma <= 4'd3; + 31,35,44:CodedBlockPatternLuma <= 4'd4; + 18,22,26:CodedBlockPatternLuma <= 4'd5; + 37,39,46:CodedBlockPatternLuma <= 4'd6; + 4,8,12 :CodedBlockPatternLuma <= 4'd7; + 32,36,45:CodedBlockPatternLuma <= 4'd8; + 38,40,47:CodedBlockPatternLuma <= 4'd9; + 19,23,27:CodedBlockPatternLuma <= 4'd10; + 5,9,13 :CodedBlockPatternLuma <= 4'd11; + 20,24,28:CodedBlockPatternLuma <= 4'd12; + 6,10,14 :CodedBlockPatternLuma <= 4'd13; + 7,11,15 :CodedBlockPatternLuma <= 4'd14; + default :CodedBlockPatternLuma <= CodedBlockPatternLuma_reg; + endcase + endcase + else + CodedBlockPatternLuma <= CodedBlockPatternLuma_reg; + + + always @ (slice_data_state or mb_type_general or exp_golomb_decoding_output_5to0 or CodedBlockPatternChroma_reg) + if (mb_type_general[3:2] == 2'b10)//Intra16x16 + CodedBlockPatternChroma <= mb_type_general[1:0]; + else if (slice_data_state == `coded_block_pattern_s) + case (mb_type_general[3]) + 1'b0: //Inter + if (exp_golomb_decoding_output_5to0 < 2) //CBP = 0,16 + CodedBlockPatternChroma <= {1'b0,exp_golomb_decoding_output_5to0[0]}; + else if (exp_golomb_decoding_output_5to0 < 6) //CBP =1,2,4,8 + CodedBlockPatternChroma <= 2'd0; + else + case (exp_golomb_decoding_output_5to0) + 7,8,9,10,11,13,14,15,16,17,18 :CodedBlockPatternChroma <= 2'd0; + 19,32,33,34,35,36,37,38,39,40,41,42,43,44,45:CodedBlockPatternChroma <= 2'd1; + default :CodedBlockPatternChroma <= 2'd2; + endcase + 1'b1: //Intra4x4 + if (exp_golomb_decoding_output_5to0 < 3) //CBP = 47,31,15 + case (exp_golomb_decoding_output_5to0[1:0]) + 2'b00 :CodedBlockPatternChroma <= 2'd2; + 2'b01 :CodedBlockPatternChroma <= 2'd1; + default:CodedBlockPatternChroma <= 2'd0; + endcase + else + case (exp_golomb_decoding_output_5to0) + 3,8,9,10,11,17,18,19,20,29,30,31,32,37,38:CodedBlockPatternChroma <= 2'd0; + 4,5,6,7,16,21,22,23,24,33,34,35,36,39,40 :CodedBlockPatternChroma <= 2'd1; + default :CodedBlockPatternChroma <= 2'd2; + endcase + endcase + else + CodedBlockPatternChroma <= CodedBlockPatternChroma_reg; + +endmodule + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/DF_mem_ctrl.v b/demo_chip_rtl/rtl/nova/tags/Start/src/DF_mem_ctrl.v new file mode 100644 index 0000000..67ad62f --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/DF_mem_ctrl.v @@ -0,0 +1,740 @@ +//----------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : DF_mem_ctrl.v +// Generated : Nov 27,2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// controller for DF_mbAddrA_RAM & DF_mbAddrB_RAM & dis_frame_RAM +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module DF_mem_ctrl (clk,reset_n,gclk_end_of_MB_DEC,disable_DF,mb_num_h,mb_num_v, + bs_curr_MR,bs_curr_MW,blk4x4_sum_counter,blk4x4_rec_counter_2_raster_order, + DF_edge_counter_MR,DF_edge_counter_MW,one_edge_counter_MR,one_edge_counter_MW, + blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out, + p3_MW,p2_MW,p1_MW,p0_MW,q3_MW,q2_MW,q1_MW,q0_MW, + buf0_0,buf0_1,buf0_2,buf0_3, + buf2_0,buf2_1,buf2_2,buf2_3,buf3_0,buf3_1,buf3_2,buf3_3, + t0_0,t0_1,t0_2,t0_3,t1_0,t1_1,t1_2,t1_3,t2_0,t2_1,t2_2,t2_3, + + mb_num_h_DF,mb_num_v_DF,end_of_MB_DF,end_of_lastMB_DF, + DF_mbAddrA_RF_rd,DF_mbAddrA_RF_wr,DF_mbAddrA_RF_rd_addr,DF_mbAddrA_RF_wr_addr,DF_mbAddrA_RF_din, + DF_mbAddrB_RAM_rd,DF_mbAddrB_RAM_wr,DF_mbAddrB_RAM_addr,DF_mbAddrB_RAM_din, + dis_frame_RAM_wr,dis_frame_RAM_wr_addr,dis_frame_RAM_din); + input clk,reset_n; + input disable_DF; + input gclk_end_of_MB_DEC; + input [3:0] mb_num_h; + input [3:0] mb_num_v; + input [2:0] bs_curr_MR,bs_curr_MW; + input [2:0] blk4x4_sum_counter; + input [4:0] blk4x4_rec_counter_2_raster_order; + input [5:0] DF_edge_counter_MR,DF_edge_counter_MW; + input [1:0] one_edge_counter_MR,one_edge_counter_MW; + input [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out; + input [7:0] p3_MW,p2_MW,p1_MW,p0_MW; + input [7:0] q3_MW,q2_MW,q1_MW,q0_MW; + input [31:0] buf0_0,buf0_1,buf0_2,buf0_3; + input [31:0] buf2_0,buf2_1,buf2_2,buf2_3; + input [31:0] buf3_0,buf3_1,buf3_2,buf3_3; + input [31:0] t0_0,t0_1,t0_2,t0_3; + input [31:0] t1_0,t1_1,t1_2,t1_3; + input [31:0] t2_0,t2_1,t2_2,t2_3; + + output [3:0] mb_num_h_DF; + output [3:0] mb_num_v_DF; + output end_of_MB_DF; + output end_of_lastMB_DF; + output DF_mbAddrA_RF_rd; + output DF_mbAddrA_RF_wr; + output [4:0] DF_mbAddrA_RF_rd_addr; + output [4:0] DF_mbAddrA_RF_wr_addr; + output [31:0] DF_mbAddrA_RF_din; + + output DF_mbAddrB_RAM_rd; + output DF_mbAddrB_RAM_wr; + output [8:0] DF_mbAddrB_RAM_addr; + output [31:0] DF_mbAddrB_RAM_din; + + output dis_frame_RAM_wr; + output [13:0] dis_frame_RAM_wr_addr; + output [31:0] dis_frame_RAM_din; + + wire Is_mbAddrA_wr; + wire Is_mbAddrA_real_wr; + wire Is_mbAddrA_virtual_wr; + wire Is_mbAddrB_wr; + wire Is_currMB_wr; + wire Is_12cycles_wr; + wire dis_frame_RAM_wr_tmp; + + reg [3:0] mb_num_h_DF; + reg [3:0] mb_num_v_DF; + always @ (posedge gclk_end_of_MB_DEC or negedge reset_n) + if (reset_n == 1'b0) + begin mb_num_h_DF <= 0; mb_num_v_DF <= 0; end + else if (!disable_DF) + begin mb_num_h_DF <= mb_num_h; mb_num_v_DF <= mb_num_v; end + + + reg [3:0] DF_12_cycles; + always @ (posedge clk) + if (reset_n == 1'b0) + DF_12_cycles <= 4'd12; + else if (!disable_DF && DF_edge_counter_MW == 6'd47 && one_edge_counter_MW == 2'd3) + DF_12_cycles <= 0; + else if (DF_12_cycles != 4'd12) + DF_12_cycles <= DF_12_cycles + 1; + + reg end_of_MB_DF; + reg end_of_lastMB_DF;//end of MB_DF of 98th MB of one frame.Does not need to rise MB_rec_DF_align since there is only + //DF and no reconstruction.So dispart end_of_lastMB_DF from end_of_MB_DF + + always @ (posedge clk) + if (reset_n == 1'b0) + begin + end_of_MB_DF <= 1'b0; + end_of_lastMB_DF <= 1'b0; + end + else if (DF_12_cycles == 4'd11) + begin + end_of_MB_DF <= (!(mb_num_h_DF == 10 && mb_num_v_DF == 8))? 1'b1:1'b0; + end_of_lastMB_DF <= (mb_num_h_DF == 10 && mb_num_v_DF == 8)? 1'b1:1'b0; + end + else + begin + end_of_MB_DF <= 1'b0; + end_of_lastMB_DF <= 1'b0; + end + + wire [1:0] write_0to3_cycle; + assign write_0to3_cycle = (DF_12_cycles == 4'd12)? one_edge_counter_MW:DF_12_cycles[1:0]; + //------------------------------------------------------------------- + //DF_mbAddrA_RF control + //------------------------------------------------------------------- + + //For edge 18,34,42,it will update mbAddrB of left MB.So no matter bs_curr_MR is equal to 0 or not, + //mbAddrA should be read out for writing to mbAddrB of left MB.Otherwise,the value written to left + //mbAddrB will be a wrong value. + assign DF_mbAddrA_RF_rd = (mb_num_h_DF != 0 && ((( + DF_edge_counter_MR == 6'd0 || DF_edge_counter_MR == 6'd2 || DF_edge_counter_MR == 6'd16 || + DF_edge_counter_MR == 6'd32 || DF_edge_counter_MR == 6'd40) && bs_curr_MR != 0) || ( + DF_edge_counter_MR == 6'd18 || DF_edge_counter_MR == 6'd34 || DF_edge_counter_MR == 6'd42))); + + assign DF_mbAddrA_RF_wr = (DF_edge_counter_MW == 6'd16 || DF_edge_counter_MW == 6'd30 || + DF_edge_counter_MW == 6'd32 || DF_edge_counter_MW == 6'd33 || DF_edge_counter_MW == 6'd40 || + DF_edge_counter_MW == 6'd41 || DF_12_cycles[3:2] == 2'b01 || DF_12_cycles[3:2] == 2'b10); + //DF_mbAddrA_RF_rd_addr + reg [2:0] DF_mbAddrA_RF_rd_addr_blk4x4; + always @ (DF_mbAddrA_RF_rd or DF_edge_counter_MR) + if (DF_mbAddrA_RF_rd) + case (DF_edge_counter_MR) + 6'd0 :DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd0; //mbAddrA0 + 6'd2 :DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd1; //mbAddrA1 + 6'd16:DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd2; //mbAddrA2 + 6'd18:DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd3; //mbAddrA3 + 6'd32:DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd4; //mbAddrA4 + 6'd34:DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd5; //mbAddrA5 + 6'd40:DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd6; //mbAddrA6 + 6'd42:DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd7; //mbAddrA7 + default:DF_mbAddrA_RF_rd_addr_blk4x4 <= 0; + endcase + else + DF_mbAddrA_RF_rd_addr_blk4x4 <= 0; + assign DF_mbAddrA_RF_rd_addr = {5{DF_mbAddrA_RF_rd}} & + ({DF_mbAddrA_RF_rd_addr_blk4x4,2'b0} + one_edge_counter_MR); + //DF_mbAddrA_RF_wr_addr + reg [2:0] DF_mbAddrA_RF_wr_addr_blk4x4; + always @ (DF_mbAddrA_RF_wr or DF_edge_counter_MW or DF_12_cycles[3:2]) + if (DF_mbAddrA_RF_wr) + begin + if (DF_edge_counter_MW != 6'd48) + case (DF_edge_counter_MW) + 6'd16:DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd0; //mbAddrA0 + 6'd30:DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd1; //mbAddrA1 + 6'd32:DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd2; //mbAddrA2 + 6'd33:DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd3; //mbAddrA3 + 6'd40:DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd4; //mbAddrA4 + 6'd41:DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd5; //mbAddrA5 + default:DF_mbAddrA_RF_wr_addr_blk4x4 <= 0; + endcase + else if (DF_12_cycles[3:2] == 2'b01) + DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd6; + else + DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd7; + end + else + DF_mbAddrA_RF_wr_addr_blk4x4 <= 0; + + assign DF_mbAddrA_RF_wr_addr = {5{DF_mbAddrA_RF_wr}} & + ({DF_mbAddrA_RF_wr_addr_blk4x4,2'b0} + write_0to3_cycle); + + //DF_mbAddrA_RF_din + wire Is_mbAddrA_t1; + assign Is_mbAddrA_t1 = (DF_edge_counter_MW == 6'd30 || DF_edge_counter_MW == 6'd33 || + DF_edge_counter_MW == 6'd41 || DF_12_cycles[3:2] == 2'b10); + + reg [31:0] DF_mbAddrA_RF_din; + always @ (DF_mbAddrA_RF_wr or Is_mbAddrA_t1 or write_0to3_cycle or + t0_0 or t0_1 or t0_2 or t0_3 or t1_0 or t1_1 or t1_2 or t1_3) + if (DF_mbAddrA_RF_wr) + begin + if (Is_mbAddrA_t1) + case (write_0to3_cycle) + 2'd0:DF_mbAddrA_RF_din <= t1_0; + 2'd1:DF_mbAddrA_RF_din <= t1_1; + 2'd2:DF_mbAddrA_RF_din <= t1_2; + 2'd3:DF_mbAddrA_RF_din <= t1_3; + endcase + else + case (write_0to3_cycle) + 2'd0:DF_mbAddrA_RF_din <= t0_0; + 2'd1:DF_mbAddrA_RF_din <= t0_1; + 2'd2:DF_mbAddrA_RF_din <= t0_2; + 2'd3:DF_mbAddrA_RF_din <= t0_3; + endcase + end + else + DF_mbAddrA_RF_din <= 0; + //------------------------------------------------------------------- + //DF_mbAddrB_RAM control + //------------------------------------------------------------------- + assign DF_mbAddrB_RAM_rd = ((( + DF_edge_counter_MR == 6'd4 || DF_edge_counter_MR == 6'd8 || DF_edge_counter_MR == 6'd12 || + DF_edge_counter_MR == 6'd13 || DF_edge_counter_MR == 6'd36 || DF_edge_counter_MR == 6'd37 || + DF_edge_counter_MR == 6'd44 || DF_edge_counter_MR == 6'd45) && mb_num_v_DF != 0) || + DF_edge_counter_MR == 6'd20 || DF_edge_counter_MR == 6'd24 || DF_edge_counter_MR == 6'd28 || + DF_edge_counter_MR == 6'd29); + + wire DF_mbAddrB_RAM_wr_curr; + assign DF_mbAddrB_RAM_wr_curr = ((( + DF_edge_counter_MW == 6'd21 || DF_edge_counter_MW == 6'd25 || DF_edge_counter_MW == 6'd30 || + DF_edge_counter_MW == 6'd31 || DF_edge_counter_MW == 6'd38 || DF_edge_counter_MW == 6'd39 || + DF_edge_counter_MW == 6'd46 || DF_edge_counter_MW == 6'd47) && mb_num_v_DF != 4'd8) || + DF_edge_counter_MW == 6'd5 || DF_edge_counter_MW == 6'd9 || DF_edge_counter_MW == 6'd14 || + DF_edge_counter_MW == 6'd15); + + wire DF_mbAddrB_RAM_wr_leftMB; + assign DF_mbAddrB_RAM_wr_leftMB = (mb_num_h_DF != 0 && mb_num_v_DF != 4'd8 && ( + DF_edge_counter_MW == 6'd20 || DF_edge_counter_MW == 6'd37 || DF_edge_counter_MW == 6'd45)); + + assign DF_mbAddrB_RAM_wr = DF_mbAddrB_RAM_wr_curr | DF_mbAddrB_RAM_wr_leftMB; + + reg [2:0] DF_mbAddrB_RAM_addr_blk4x4; + always @ (DF_mbAddrB_RAM_rd or DF_edge_counter_MR or DF_mbAddrB_RAM_wr_curr + or DF_mbAddrB_RAM_wr_leftMB or DF_edge_counter_MW) + if (DF_mbAddrB_RAM_rd) + case (DF_edge_counter_MR) + 6'd4, 6'd20:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd0; + 6'd8, 6'd24:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd1; + 6'd12,6'd28:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd2; + 6'd13,6'd29:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd3; + 6'd36 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd4; + 6'd37 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd5; + 6'd44 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd6; + 6'd45 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd7; + default :DF_mbAddrB_RAM_addr_blk4x4 <= 0; + endcase + else if (DF_mbAddrB_RAM_wr_curr) + case (DF_edge_counter_MW) + 6'd5, 6'd21:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd0; + 6'd9, 6'd25:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd1; + 6'd14,6'd30:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd2; + 6'd15,6'd31:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd3; + 6'd38 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd4; + 6'd39 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd5; + 6'd46 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd6; + 6'd47 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd7; + default :DF_mbAddrB_RAM_addr_blk4x4 <= 0; + endcase + else if (DF_mbAddrB_RAM_wr_leftMB) + case (DF_edge_counter_MW) + 6'd20:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd3; + 6'd37:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd5; + default:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd7; + endcase + else + DF_mbAddrB_RAM_addr_blk4x4 <= 0; + + reg [1:0] DF_mbAddrB_RAM_addr_offset; + always @ (DF_mbAddrB_RAM_rd or one_edge_counter_MR or DF_mbAddrB_RAM_wr or one_edge_counter_MW) + if (DF_mbAddrB_RAM_rd) DF_mbAddrB_RAM_addr_offset <= one_edge_counter_MR; + else if (DF_mbAddrB_RAM_wr) DF_mbAddrB_RAM_addr_offset <= one_edge_counter_MW; + else DF_mbAddrB_RAM_addr_offset <= 0; + + wire [3:0] mb_num_h_DF_m1; + assign mb_num_h_DF_m1 = {4{Is_mbAddrA_wr | DF_mbAddrB_RAM_wr_leftMB}} & (mb_num_h_DF - 1); + + wire [8:0] mb_num_h_DF_x32; + assign mb_num_h_DF_x32 = (DF_mbAddrB_RAM_wr_leftMB)? {mb_num_h_DF_m1,5'b0}:{mb_num_h_DF,5'b0}; + assign DF_mbAddrB_RAM_addr = mb_num_h_DF_x32 + {DF_mbAddrB_RAM_addr_blk4x4,2'b0} + DF_mbAddrB_RAM_addr_offset; + + reg [31:0] DF_mbAddrB_RAM_din; + always @ (DF_mbAddrB_RAM_wr_curr or DF_mbAddrB_RAM_wr_leftMB or one_edge_counter_MW + or q0_MW or q1_MW or q2_MW or q3_MW or t2_0 or t2_1 or t2_2 or t2_3) + if (DF_mbAddrB_RAM_wr_curr) + DF_mbAddrB_RAM_din <= {q3_MW,q2_MW,q1_MW,q0_MW}; + else if (DF_mbAddrB_RAM_wr_leftMB) + case (one_edge_counter_MW) + 2'd0:DF_mbAddrB_RAM_din <= t2_0; + 2'd1:DF_mbAddrB_RAM_din <= t2_1; + 2'd2:DF_mbAddrB_RAM_din <= t2_2; + 2'd3:DF_mbAddrB_RAM_din <= t2_3; + endcase + else + DF_mbAddrB_RAM_din <= 0; + //------------------------------------------------------------------- + //dis_frame_RAM write control + //------------------------------------------------------------------- + //dis_frame_RAM_wr + assign Is_mbAddrA_wr = (mb_num_h_DF != 0 && ( + DF_edge_counter_MW == 6'd0 || DF_edge_counter_MW == 6'd2 || DF_edge_counter_MW == 6'd16 || + DF_edge_counter_MW == 6'd18 || DF_edge_counter_MW == 6'd32 || DF_edge_counter_MW == 6'd34 || + DF_edge_counter_MW == 6'd40 || DF_edge_counter_MW == 6'd42)); + assign Is_mbAddrA_real_wr = (Is_mbAddrA_wr && bs_curr_MW != 0); + assign Is_mbAddrA_virtual_wr = (Is_mbAddrA_wr && bs_curr_MW == 0); + + assign Is_mbAddrB_wr = (mb_num_v_DF != 0 && ( + DF_edge_counter_MW == 6'd5 || DF_edge_counter_MW == 6'd9 || DF_edge_counter_MW == 6'd13 || + DF_edge_counter_MW == 6'd14 || DF_edge_counter_MW == 6'd37 || DF_edge_counter_MW == 6'd38 || + DF_edge_counter_MW == 6'd45 || DF_edge_counter_MW == 6'd46)); + assign Is_currMB_wr = (( + DF_edge_counter_MW == 6'd6 || DF_edge_counter_MW == 6'd10 || DF_edge_counter_MW == 6'd15 || + DF_edge_counter_MW == 6'd17 || DF_edge_counter_MW == 6'd21 || DF_edge_counter_MW == 6'd22 || + DF_edge_counter_MW == 6'd23 || DF_edge_counter_MW == 6'd25 || DF_edge_counter_MW == 6'd26 || + DF_edge_counter_MW == 6'd27 || DF_edge_counter_MW == 6'd29 || DF_edge_counter_MW == 6'd30 || + DF_edge_counter_MW == 6'd31 || DF_edge_counter_MW == 6'd33 || DF_edge_counter_MW == 6'd35 || + DF_edge_counter_MW == 6'd36 || DF_edge_counter_MW == 6'd39 || DF_edge_counter_MW == 6'd41 || + DF_edge_counter_MW == 6'd43 || DF_edge_counter_MW == 6'd44 || DF_edge_counter_MW == 6'd47) && + one_edge_counter_MW != 3'd4); + assign Is_12cycles_wr = (DF_12_cycles != 4'd12); + + assign dis_frame_RAM_wr_tmp = + ( disable_DF && blk4x4_sum_counter[2] != 1'b1) || + (!disable_DF && (Is_mbAddrA_wr || Is_mbAddrB_wr || Is_currMB_wr || Is_12cycles_wr)); + assign dis_frame_RAM_wr = (dis_frame_RAM_wr_tmp & (~Is_mbAddrA_virtual_wr)); + + wire Is_luma_wr; + wire Is_chroma_wr; + wire Is_1st_cycle_wr; //if it is the position of first line of a 4x4 block,for both DF disable & enable + wire Is_MB_LeftTop_wr; //if it is the position of most left-top for a whole MB,only for DF is disabled + assign Is_luma_wr = (dis_frame_RAM_wr_tmp && ( + (disable_DF && blk4x4_rec_counter_2_raster_order[4] == 1'b0) || + (!disable_DF && (((Is_mbAddrA_wr || Is_mbAddrB_wr) && !DF_edge_counter_MW[5]) || + (Is_currMB_wr && DF_edge_counter_MW < 6'd39)))))? 1'b1:1'b0; + + assign Is_chroma_wr = (dis_frame_RAM_wr_tmp && !Is_luma_wr)? 1'b1:1'b0; + + assign Is_1st_cycle_wr = ( + ( disable_DF && blk4x4_sum_counter == 0) || + (!disable_DF && (one_edge_counter_MW == 0 && (Is_mbAddrA_wr || Is_mbAddrB_wr || Is_currMB_wr)) || + (DF_12_cycles[1:0] == 2'b00 && DF_12_cycles[3:2] != 2'b11)))? 1'b1:1'b0; + + assign Is_MB_LeftTop_wr = (disable_DF && blk4x4_sum_counter == 0 && ( + (blk4x4_rec_counter_2_raster_order[4] == 1'b0 && blk4x4_rec_counter_2_raster_order[3:0] == 4'b0) || + (blk4x4_rec_counter_2_raster_order[4] == 1'b1 && blk4x4_rec_counter_2_raster_order[1:0] == 2'b0))) ? 1'b1:1'b0; + + //--------------------------------------------------------------------------------- + // dis_frame_RAM_wr_addr_base + // Only updated at first write cycle(during 2,3,4 write cycle,it remains unchanged) + // Luma:0 Cb:6336 Cr:7920 + //--------------------------------------------------------------------------------- + reg [12:0] dis_frame_RAM_wr_addr_base; + always @ (disable_DF or Is_MB_LeftTop_wr or Is_1st_cycle_wr or Is_luma_wr or Is_12cycles_wr + or blk4x4_rec_counter_2_raster_order[2] or DF_edge_counter_MW) + if (disable_DF) + begin + if (Is_MB_LeftTop_wr) + begin + if (Is_luma_wr) //luma + dis_frame_RAM_wr_addr_base <= 13'd0; + else if (blk4x4_rec_counter_2_raster_order[2] == 1'b0) //Cb + dis_frame_RAM_wr_addr_base <= 13'd6336; + else //Cr + dis_frame_RAM_wr_addr_base <= 13'd7920; + end + else + dis_frame_RAM_wr_addr_base <= 13'd0; + end + else + begin + if (Is_1st_cycle_wr) //update only @ 1st write cycle + begin + if (Is_luma_wr) //luma + dis_frame_RAM_wr_addr_base <= 13'd0; + else if (DF_edge_counter_MW < 6'd45 && DF_edge_counter_MW != 40 && DF_edge_counter_MW != 42) //Cb + dis_frame_RAM_wr_addr_base <= 13'd6336; + else //Cr + dis_frame_RAM_wr_addr_base <= 13'd7920; + end + else + dis_frame_RAM_wr_addr_base <= 0; + end + //--------------------------------------------------------------------------------- + // dis_frame_RAM_wr_addr_x + // Only updated at first write cycle(during 2,3,4 write cycle,it remains unchanged) + // x position inside a frame,since every 4 horizontal pixels have been combined as + // a single 32bit word,thus 0 ~ 43 for luma and 0 ~ 21 for chroma + //--------------------------------------------------------------------------------- + wire [3:0] mb_num_v_DF_m1; + assign mb_num_v_DF_m1 = {4{Is_mbAddrB_wr}} & (mb_num_v_DF - 1); + + reg [1:0] blk4x4_xoffset; //0 ~ 3,xoffset for blk4x4 inside a MB + always @ (Is_luma_wr or Is_mbAddrA_wr or Is_mbAddrB_wr or Is_currMB_wr or DF_12_cycles or DF_edge_counter_MW) + case ({Is_mbAddrA_wr,Is_mbAddrB_wr,Is_currMB_wr}) + 3'b100: //Is_mbAddrA_wr + if (Is_luma_wr) blk4x4_xoffset <= 2'd3; + else blk4x4_xoffset <= 2'd1; + 3'b010: //Is_mbAddrB_wr + case (DF_edge_counter_MW) + 6'd5,6'd37,6'd45:blk4x4_xoffset <= 2'd0; + 6'd9,6'd38,6'd46:blk4x4_xoffset <= 2'd1; + 6'd13 :blk4x4_xoffset <= 2'd2; + 6'd14 :blk4x4_xoffset <= 2'd3; + default :blk4x4_xoffset <= 0; + endcase + 3'b001: //Is_currMB_wr + case (DF_edge_counter_MW) + //6'd6,6'd21,6'd23,6'd22,6'd39,6'd41,6'd47:blk4x4_xoffset <= 0; + 6'd10,6'd25,6'd27,6'd26,6'd43,6'd44 :blk4x4_xoffset <= 2'd1; + 6'd15,6'd29,6'd31,6'd33 :blk4x4_xoffset <= 2'd2; + 6'd17,6'd30,6'd35,6'd36 :blk4x4_xoffset <= 2'd3; + default :blk4x4_xoffset <= 0; + endcase + default: + if (DF_12_cycles != 4'd12) + case (DF_12_cycles[3:2]) + 2'b00 :blk4x4_xoffset <= 0; //buf2 -> blk22 + 2'b01,2'b10 :blk4x4_xoffset <= 2'd1; //T0 -> blk21,T1 -> blk23 + default :blk4x4_xoffset <= 0; + endcase + else + blk4x4_xoffset <= 0; + endcase + + reg [5:0] dis_frame_RAM_wr_addr_x; + + always @ (disable_DF or Is_MB_LeftTop_wr or Is_1st_cycle_wr or Is_luma_wr or Is_mbAddrA_wr + or Is_mbAddrB_wr or Is_currMB_wr or blk4x4_rec_counter_2_raster_order[1:0] + or mb_num_h or mb_num_h_DF_m1 or mb_num_h_DF or blk4x4_xoffset) + if (disable_DF) + begin + if (Is_MB_LeftTop_wr) + dis_frame_RAM_wr_addr_x <= (Is_luma_wr)? ({mb_num_h,2'b0} + blk4x4_rec_counter_2_raster_order[1:0]):({1'b0,mb_num_h,1'b0} + blk4x4_rec_counter_2_raster_order[0]); + else + dis_frame_RAM_wr_addr_x <= 0; + end + else + begin + if (Is_1st_cycle_wr) + case ({Is_mbAddrA_wr,Is_mbAddrB_wr,Is_currMB_wr}) + 3'b100: //Is_mbAddrA_wr + dis_frame_RAM_wr_addr_x <= (Is_luma_wr)? ({mb_num_h_DF_m1,2'b0} + blk4x4_xoffset):({1'b0,mb_num_h_DF_m1,1'b0} + blk4x4_xoffset); + 3'b010,3'b001: //Is_mbAddrB_wr,Is_currMB_wr + dis_frame_RAM_wr_addr_x <= (Is_luma_wr)? ({mb_num_h_DF,2'b0} + blk4x4_xoffset):({1'b0,mb_num_h_DF,1'b0} + blk4x4_xoffset); + + default: //for DF_12_cycles != 4'd12 + dis_frame_RAM_wr_addr_x <= {1'b0,mb_num_h_DF,1'b0} + blk4x4_xoffset; + endcase + else + dis_frame_RAM_wr_addr_x <= 0; + end + //--------------------------------------------------------------------------------- + // dis_frame_RAM_wr_addr_y + // a)Only updated at first write cycle(during 2,3,4 write cycle,it remains unchanged) + // b)For 2,3,4 write cycles,dis_frame_RAM_wr_addr is directly +44/+22 instead of + // changing dis_frame_RAM_wr_addr_y + // c)y addr increase 1 means +44 for luma or +22 for choma + //--------------------------------------------------------------------------------- + reg [1:0] blk4x4_yoffset; //0 ~ 3,yoffset for blk4x4 inside a MB + always @ (Is_mbAddrA_wr or Is_currMB_wr or DF_12_cycles or DF_edge_counter_MW) + if (Is_mbAddrA_wr) + case (DF_edge_counter_MW) + 6'd0,6'd32,6'd40:blk4x4_yoffset <= 2'd0; + 6'd2,6'd34,6'd42:blk4x4_yoffset <= 2'd1; + 6'd16 :blk4x4_yoffset <= 2'd2; + 6'd18 :blk4x4_yoffset <= 2'd3; + default :blk4x4_yoffset <= 0; + endcase + else if (Is_currMB_wr) + case (DF_edge_counter_MW) + //6'd6,6'd10,6'd15,6'd17,6'd39,6'd43,6'd47:blk4x4_yoffset <= 0; + 6'd21,6'd25,6'd29,6'd30,6'd41,6'd44 :blk4x4_yoffset <= 2'd1; + 6'd23,6'd27,6'd31,6'd35 :blk4x4_yoffset <= 2'd2; + 6'd22,6'd26,6'd33,6'd36 :blk4x4_yoffset <= 2'd3; + default :blk4x4_yoffset <= 0; + endcase + else if (DF_12_cycles != 4'd12) + case (DF_12_cycles[2]) + 1'b0:blk4x4_yoffset <= 2'd1; // 0 ~ 3:buf2->22; 8 ~ 11:T1->23 + 1'b1:blk4x4_yoffset <= 0; // 4 ~ 7:T0->21 + endcase + else + blk4x4_yoffset <= 0; + + reg [7:0] dis_frame_RAM_wr_addr_y; //y position inside a frame,0 ~ 143 for luma & 0 ~ 71 for chroma + always @ (disable_DF or Is_MB_LeftTop_wr or Is_1st_cycle_wr or Is_luma_wr + or Is_mbAddrA_wr or Is_mbAddrB_wr or Is_mbAddrB_wr or Is_currMB_wr + or blk4x4_sum_counter[1:0] or blk4x4_rec_counter_2_raster_order[4:1] + or mb_num_v or mb_num_v_DF or mb_num_v_DF_m1 + or one_edge_counter_MW or blk4x4_yoffset or DF_12_cycles) + if (disable_DF) + begin + if (Is_MB_LeftTop_wr) + dis_frame_RAM_wr_addr_y <= (Is_luma_wr)? + ({mb_num_v,4'b0} + {blk4x4_rec_counter_2_raster_order[3:2],2'b00} + blk4x4_sum_counter[1:0]): + ({1'b0,mb_num_v,3'b0} + {blk4x4_rec_counter_2_raster_order[1], 2'b00} + blk4x4_sum_counter[1:0]); + else + dis_frame_RAM_wr_addr_y <= 0; + end + else + begin + if (Is_1st_cycle_wr) + case ({Is_mbAddrA_wr,Is_mbAddrB_wr,Is_currMB_wr}) + 3'b100: //Is_mbAddrA_wr + dis_frame_RAM_wr_addr_y <= (Is_luma_wr)? //luma or chroma + (({mb_num_v_DF,4'b0} + {2'b00,blk4x4_yoffset,2'b00}) + one_edge_counter_MW): + (({1'b0,mb_num_v_DF,3'b0} + {2'b00,blk4x4_yoffset,2'b00}) + one_edge_counter_MW); + 3'b010: //Is_mbAddrB_wr + dis_frame_RAM_wr_addr_y <= (Is_luma_wr)? //luma or chroma + (({mb_num_v_DF_m1,4'b0} + 4'd12) + one_edge_counter_MW): + (({1'b0,mb_num_v_DF_m1,3'b0} + 4'd4 ) + one_edge_counter_MW); + 3'b001: //Is_currMB_wr + dis_frame_RAM_wr_addr_y <= (Is_luma_wr)? //luma or chroma + (({mb_num_v_DF,4'b0} + {blk4x4_yoffset,2'b0}) + one_edge_counter_MW): + (({1'b0,mb_num_v_DF,3'b0} + {blk4x4_yoffset,2'b0}) + one_edge_counter_MW); + default: + if (DF_12_cycles != 4'd12) + dis_frame_RAM_wr_addr_y <= {mb_num_v_DF,3'b0} + {blk4x4_yoffset,2'b0} + DF_12_cycles[1:0]; + else + dis_frame_RAM_wr_addr_y <= 0; + endcase + else + dis_frame_RAM_wr_addr_y <= 0; + end + + + wire [12:0] dis_frame_RAM_wr_addr_y_ext; //every "y" increase will increase 44(luma) or 22(chroma) for + //dis_frame_RAM address + + assign dis_frame_RAM_wr_addr_y_ext = (Is_luma_wr)? + //luma, x44 = x32 + x8 + x4 + ( {dis_frame_RAM_wr_addr_y,5'b0} + {2'b0,dis_frame_RAM_wr_addr_y,3'b0} + {3'b0,dis_frame_RAM_wr_addr_y,2'b0}): + //chroma,x22 = x16 + x4 + x2 + ({1'b0,dis_frame_RAM_wr_addr_y,4'b0} + {3'b0,dis_frame_RAM_wr_addr_y,2'b0} + {4'b0,dis_frame_RAM_wr_addr_y,1'b0}); + + wire [13:0] dis_frame_RAM_wr_addr_tmp; + reg [13:0] dis_frame_RAM_wr_addr_LeftTop_reg; + reg [13:0] dis_frame_RAM_wr_addr_reg; + reg [13:0] dis_frame_RAM_wr_addr; + + assign dis_frame_RAM_wr_addr_tmp = dis_frame_RAM_wr_addr_base + dis_frame_RAM_wr_addr_y_ext + dis_frame_RAM_wr_addr_x; + always @ (posedge clk) + if (reset_n == 1'b0) + dis_frame_RAM_wr_addr_LeftTop_reg <= 0; + else if (Is_MB_LeftTop_wr) + dis_frame_RAM_wr_addr_LeftTop_reg <= dis_frame_RAM_wr_addr_tmp; + + always @ (disable_DF or Is_MB_LeftTop_wr or Is_1st_cycle_wr or Is_luma_wr or Is_chroma_wr or dis_frame_RAM_wr_addr_tmp + or dis_frame_RAM_wr_addr_reg or blk4x4_rec_counter_2_raster_order or dis_frame_RAM_wr_addr_LeftTop_reg) + if (disable_DF) + begin + if (Is_MB_LeftTop_wr) + dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_tmp; + else if (Is_1st_cycle_wr) + case (blk4x4_rec_counter_2_raster_order[4]) + 1'b0: + case (blk4x4_rec_counter_2_raster_order[3:2]) + 2'b00:dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_LeftTop_reg + blk4x4_rec_counter_2_raster_order[1:0]; + 2'b01:dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_LeftTop_reg + blk4x4_rec_counter_2_raster_order[1:0] + 176; + 2'b10:dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_LeftTop_reg + blk4x4_rec_counter_2_raster_order[1:0] + 352; + 2'b11:dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_LeftTop_reg + blk4x4_rec_counter_2_raster_order[1:0] + 528; + endcase + 1'b1: + dis_frame_RAM_wr_addr <= (blk4x4_rec_counter_2_raster_order[1])? + (dis_frame_RAM_wr_addr_LeftTop_reg + 88 + blk4x4_rec_counter_2_raster_order[0]): + (dis_frame_RAM_wr_addr_LeftTop_reg + blk4x4_rec_counter_2_raster_order[0]); + endcase + else if (Is_luma_wr) + dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_reg + 44; + else if (Is_chroma_wr) + dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_reg + 22; + else + dis_frame_RAM_wr_addr <= 0; + end + else + begin + if (Is_1st_cycle_wr) + dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_tmp; + else if (Is_luma_wr) + dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_reg + 44; + else if (Is_chroma_wr) + dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_reg + 22; + else + dis_frame_RAM_wr_addr <= 0; + end + + always @ (posedge clk) + if (reset_n == 1'b0) + dis_frame_RAM_wr_addr_reg <= 0; + else if (dis_frame_RAM_wr_tmp) + dis_frame_RAM_wr_addr_reg <= dis_frame_RAM_wr_addr; + + //dis_frame_RAM_din + wire Is_mbAddrB_t1; + wire Is_currMB_buf0; + wire Is_currMB_buf2; + wire Is_currMB_buf3; + wire Is_currMB_t1; + assign Is_mbAddrB_t1 = (DF_edge_counter_MW == 6'd14 || DF_edge_counter_MW == 6'd38 || + DF_edge_counter_MW == 6'd46); + assign Is_currMB_buf0 = (DF_edge_counter_MW == 6'd6 || DF_edge_counter_MW == 6'd15 || + DF_edge_counter_MW == 6'd31 || DF_edge_counter_MW == 6'd39 || + DF_edge_counter_MW == 6'd47); + assign Is_currMB_buf2 = (DF_edge_counter_MW == 6'd22 || DF_edge_counter_MW == 6'd33 || + DF_edge_counter_MW == 6'd41); + assign Is_currMB_buf3 = (DF_edge_counter_MW == 6'd26); + assign Is_currMB_t1 = (DF_edge_counter_MW == 6'd10 || DF_edge_counter_MW == 6'd23 || + DF_edge_counter_MW == 6'd27 || DF_edge_counter_MW == 6'd30 || + DF_edge_counter_MW == 6'd36 || DF_edge_counter_MW == 6'd44); + + reg [31:0] dis_frame_RAM_din; + always @ (disable_DF or dis_frame_RAM_wr or blk4x4_sum_counter or one_edge_counter_MW or + DF_12_cycles or Is_mbAddrA_real_wr or Is_mbAddrB_wr or Is_mbAddrB_t1 or Is_currMB_buf0 or + Is_currMB_buf2 or Is_currMB_buf3 or Is_currMB_t1 or Is_currMB_wr or + blk4x4_sum_PE0_out or blk4x4_sum_PE1_out or blk4x4_sum_PE2_out or blk4x4_sum_PE3_out or + p0_MW or p1_MW or p2_MW or p3_MW or + buf0_0 or buf0_1 or buf0_2 or buf0_3 or + buf2_0 or buf2_1 or buf2_2 or buf2_3 or buf3_0 or buf3_1 or buf3_2 or buf3_3 or + t0_0 or t0_1 or t0_2 or t0_3 or t1_0 or t1_1 or t1_2 or t1_3) + if (disable_DF && dis_frame_RAM_wr) + begin + if (blk4x4_sum_counter[2] == 1'b0) + dis_frame_RAM_din <= {blk4x4_sum_PE3_out,blk4x4_sum_PE2_out,blk4x4_sum_PE1_out,blk4x4_sum_PE0_out}; + else + dis_frame_RAM_din <= 0; + end + else if (!disable_DF && dis_frame_RAM_wr) + case ({Is_mbAddrA_real_wr,Is_mbAddrB_wr,Is_currMB_wr}) + 3'b100: //Is_mbAddrA_wr + dis_frame_RAM_din <= {p0_MW,p1_MW,p2_MW,p3_MW}; + 3'b010: //Is_mbAddrB_wr + begin + if (Is_mbAddrB_t1) //T1 -> mbAddrB + case (one_edge_counter_MW) + 2'd0:dis_frame_RAM_din <= t1_0; + 2'd1:dis_frame_RAM_din <= t1_1; + 2'd2:dis_frame_RAM_din <= t1_2; + 2'd3:dis_frame_RAM_din <= t1_3; + endcase + else //T0 -> mbAddrB + case (one_edge_counter_MW) + 2'd0:dis_frame_RAM_din <= t0_0; + 2'd1:dis_frame_RAM_din <= t0_1; + 2'd2:dis_frame_RAM_din <= t0_2; + 2'd3:dis_frame_RAM_din <= t0_3; + endcase + end + 3'b001: //Is_currMB_wr + case ({Is_currMB_buf0,Is_currMB_buf2,Is_currMB_buf3,Is_currMB_t1}) + 4'b1000: //Is_currMB_buf0 + case (one_edge_counter_MW) + 2'd0:dis_frame_RAM_din <= buf0_0; + 2'd1:dis_frame_RAM_din <= buf0_1; + 2'd2:dis_frame_RAM_din <= buf0_2; + 2'd3:dis_frame_RAM_din <= buf0_3; + endcase + 4'b0100: //Is_currMB_buf2 + case (one_edge_counter_MW) + 2'd0:dis_frame_RAM_din <= buf2_0; + 2'd1:dis_frame_RAM_din <= buf2_1; + 2'd2:dis_frame_RAM_din <= buf2_2; + 2'd3:dis_frame_RAM_din <= buf2_3; + endcase + 4'b0010: //Is_currMB_buf3 + case (one_edge_counter_MW) + 2'd0:dis_frame_RAM_din <= buf3_0; + 2'd1:dis_frame_RAM_din <= buf3_1; + 2'd2:dis_frame_RAM_din <= buf3_2; + 2'd3:dis_frame_RAM_din <= buf3_3; + endcase + 4'b0001: //Is_currMB_t1 + case (one_edge_counter_MW) + 2'd0:dis_frame_RAM_din <= t1_0; + 2'd1:dis_frame_RAM_din <= t1_1; + 2'd2:dis_frame_RAM_din <= t1_2; + 2'd3:dis_frame_RAM_din <= t1_3; + endcase + default: //Is_currMB_t0 + case (one_edge_counter_MW) + 2'd0:dis_frame_RAM_din <= t0_0; + 2'd1:dis_frame_RAM_din <= t0_1; + 2'd2:dis_frame_RAM_din <= t0_2; + 2'd3:dis_frame_RAM_din <= t0_3; + endcase + endcase + default://additional 12 cycles + case (DF_12_cycles[3:2]) + 2'b00: //0 ~ 3,buf2 -> blk22 + case (DF_12_cycles[1:0]) + 2'd0:dis_frame_RAM_din <= buf2_0; + 2'd1:dis_frame_RAM_din <= buf2_1; + 2'd2:dis_frame_RAM_din <= buf2_2; + 2'd3:dis_frame_RAM_din <= buf2_3; + endcase + 2'b01: //4 ~ 7,T0 -> blk21 + case (DF_12_cycles[1:0]) + 2'd0:dis_frame_RAM_din <= t0_0; + 2'd1:dis_frame_RAM_din <= t0_1; + 2'd2:dis_frame_RAM_din <= t0_2; + 2'd3:dis_frame_RAM_din <= t0_3; + endcase + default://8 ~ 11,T1 -> blk23 + case (DF_12_cycles[1:0]) + 2'd0:dis_frame_RAM_din <= t1_0; + 2'd1:dis_frame_RAM_din <= t1_1; + 2'd2:dis_frame_RAM_din <= t1_2; + 2'd3:dis_frame_RAM_din <= t1_3; + endcase + endcase + endcase + else + dis_frame_RAM_din <= 0; +endmodule + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/DF_pipeline.v b/demo_chip_rtl/rtl/nova/tags/Start/src/DF_pipeline.v new file mode 100644 index 0000000..a474c13 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/DF_pipeline.v @@ -0,0 +1,861 @@ +//----------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : DF_pipeline.v +// Generated : Dec 2, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// 5-stage pipeline control for deblocking filter +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module DF_pipeline (clk,gclk_DF,gclk_end_of_MB_DEC,reset_n,disable_DF,end_of_BS_DEC, + end_of_MB_DF,end_of_lastMB_DF, + bs_V0,bs_V1,bs_V2,bs_V3,bs_H0,bs_H1,bs_H2,bs_H3, + QPy,QPc,slice_alpha_c0_offset_div2,slice_beta_offset_div2, + DF_mbAddrA_RF_dout,DF_mbAddrB_RAM_dout,rec_DF_RAM_dout, + buf0_0,buf0_1,buf0_2,buf0_3,buf1_0,buf1_1,buf1_2,buf1_3, + buf2_0,buf2_1,buf2_2,buf2_3,buf3_0,buf3_1,buf3_2,buf3_3, + + DF_duration, + DF_edge_counter_MR,DF_edge_counter_MW, + one_edge_counter_MR,one_edge_counter_MW, + bs_curr_MR,bs_curr_MW, + p0_MW,p1_MW,p2_MW,p3_MW,q0_MW,q1_MW,q2_MW,q3_MW); + input clk; + input gclk_DF; + input gclk_end_of_MB_DEC; + input reset_n; + input disable_DF; + input end_of_BS_DEC; + input end_of_MB_DF; + input end_of_lastMB_DF; + input [11:0] bs_V0,bs_V1,bs_V2,bs_V3; + input [11:0] bs_H0,bs_H1,bs_H2,bs_H3; + input [5:0] QPy,QPc; + input [3:0] slice_alpha_c0_offset_div2,slice_beta_offset_div2; + input [31:0] DF_mbAddrA_RF_dout,DF_mbAddrB_RAM_dout,rec_DF_RAM_dout; + input [31:0] buf0_0,buf0_1,buf0_2,buf0_3,buf1_0,buf1_1,buf1_2,buf1_3; + input [31:0] buf2_0,buf2_1,buf2_2,buf2_3,buf3_0,buf3_1,buf3_2,buf3_3; + + output DF_duration; + output [5:0] DF_edge_counter_MR,DF_edge_counter_MW; + output [1:0] one_edge_counter_MR,one_edge_counter_MW; + output [2:0] bs_curr_MR; + output [2:0] bs_curr_MW; + output [7:0] p0_MW,p1_MW,p2_MW,p3_MW; + output [7:0] q0_MW,q1_MW,q2_MW,q3_MW; + + reg DF_duration; + always @ (posedge clk or negedge reset_n) + if (reset_n == 1'b0) + DF_duration <= 1'b0; + else if (end_of_BS_DEC) + DF_duration <= 1'b1; + else if (end_of_MB_DF || end_of_lastMB_DF) + DF_duration <= 1'b0; + + //--------------------------------------------------------------------- + //1.MR: Memory Read + //--------------------------------------------------------------------- + //DF_edge_counter_MR & one_edge_counter_MR + reg [5:0] DF_edge_counter_MR; + reg [1:0] one_edge_counter_MR; + always @ (posedge gclk_DF or negedge reset_n) + if (reset_n == 1'b0) + DF_edge_counter_MR <= 6'd48; + else if (end_of_BS_DEC == 1'b1) + DF_edge_counter_MR <= 0; + else if (one_edge_counter_MR == 2'd3 && DF_edge_counter_MR != 6'd48) + DF_edge_counter_MR <= DF_edge_counter_MR + 1; + + always @ (posedge gclk_DF or negedge reset_n) + if (reset_n == 0) + one_edge_counter_MR <= 2'd3; + else if (end_of_BS_DEC == 1'b1) + one_edge_counter_MR <= 2'd0; + else + begin + if (one_edge_counter_MR == 2'd3 && DF_edge_counter_MR != 6'd47 && DF_edge_counter_MR[5:4] != 2'b11) //!47,!48 + one_edge_counter_MR <= 2'd0; + else if (one_edge_counter_MR != 2'd3) + one_edge_counter_MR <= one_edge_counter_MR + 1; + end + + //lumaEdgeFlag_MR,chromaEdgeFlag_MR + wire lumaEdgeFlag_MR,chromaEdgeFlag_MR; + assign lumaEdgeFlag_MR = !DF_edge_counter_MR[5]; + assign chromaEdgeFlag_MR = DF_edge_counter_MR[5] && (DF_edge_counter_MR != 6'd48); + + //bs_curr_MR + reg [2:0] bs_curr_MR; + always @ (disable_DF or lumaEdgeFlag_MR or chromaEdgeFlag_MR or + DF_edge_counter_MR[4:0] or one_edge_counter_MR[1] or + bs_V0 or bs_V1 or bs_V2 or bs_V3 or bs_H0 or bs_H1 or bs_H2 or bs_H3) + if (!disable_DF && lumaEdgeFlag_MR) + case (DF_edge_counter_MR[4:0]) + 5'd0 :bs_curr_MR <= bs_V0[2:0]; + 5'd1 :bs_curr_MR <= bs_V1[2:0]; + 5'd2 :bs_curr_MR <= bs_V0[5:3]; + 5'd3 :bs_curr_MR <= bs_V1[5:3]; + 5'd4 :bs_curr_MR <= bs_H0[2:0]; + 5'd5 :bs_curr_MR <= bs_H1[2:0]; + 5'd6 :bs_curr_MR <= bs_V2[2:0]; + 5'd7 :bs_curr_MR <= bs_V2[5:3]; + 5'd8 :bs_curr_MR <= bs_H0[5:3]; + 5'd9 :bs_curr_MR <= bs_H1[5:3]; + 5'd10:bs_curr_MR <= bs_V3[2:0]; + 5'd11:bs_curr_MR <= bs_V3[5:3]; + 5'd12:bs_curr_MR <= bs_H0[8:6]; + 5'd13:bs_curr_MR <= bs_H0[11:9]; + 5'd14:bs_curr_MR <= bs_H1[8:6]; + 5'd15:bs_curr_MR <= bs_H1[11:9]; + 5'd16:bs_curr_MR <= bs_V0[8:6]; + 5'd17:bs_curr_MR <= bs_V1[8:6]; + 5'd18:bs_curr_MR <= bs_V0[11:9]; + 5'd19:bs_curr_MR <= bs_V1[11:9]; + 5'd20:bs_curr_MR <= bs_H2[2:0]; + 5'd21:bs_curr_MR <= bs_H3[2:0]; + 5'd22:bs_curr_MR <= bs_V2[8:6]; + 5'd23:bs_curr_MR <= bs_V2[11:9]; + 5'd24:bs_curr_MR <= bs_H2[5:3]; + 5'd25:bs_curr_MR <= bs_H3[5:3]; + 5'd26:bs_curr_MR <= bs_V3[8:6]; + 5'd27:bs_curr_MR <= bs_V3[11:9]; + 5'd28:bs_curr_MR <= bs_H2[8:6]; + 5'd29:bs_curr_MR <= bs_H2[11:9]; + 5'd30:bs_curr_MR <= bs_H3[8:6]; + 5'd31:bs_curr_MR <= bs_H3[11:9]; + endcase + else if (!disable_DF && chromaEdgeFlag_MR) + case (DF_edge_counter_MR[3:0]) + 4'd0,4'd8: //32,40 + case (one_edge_counter_MR[1]) + 1'b0:bs_curr_MR <= bs_V0[2:0]; + 1'b1:bs_curr_MR <= bs_V0[5:3]; + endcase + 4'd2,4'd10: //34,42 + case (one_edge_counter_MR[1]) + 1'b0:bs_curr_MR <= bs_V0[8:6]; + 1'b1:bs_curr_MR <= bs_V0[11:9]; + endcase + 4'd1,4'd9: //33,41 + case (one_edge_counter_MR[1]) + 1'b0:bs_curr_MR <= bs_V2[2:0]; + 1'b1:bs_curr_MR <= bs_V2[5:3]; + endcase + 4'd3,4'd11: //35,43 + case (one_edge_counter_MR[1]) + 1'b0:bs_curr_MR <= bs_V2[8:6]; + 1'b1:bs_curr_MR <= bs_V2[11:9]; + endcase + 4'd4,4'd12: //36,44 + case (one_edge_counter_MR[1]) + 1'b0:bs_curr_MR <= bs_H0[2:0]; + 1'b1:bs_curr_MR <= bs_H0[5:3]; + endcase + 4'd5,4'd13: //37,45 + case (one_edge_counter_MR[1]) + 1'b0:bs_curr_MR <= bs_H0[8:6]; + 1'b1:bs_curr_MR <= bs_H0[11:9]; + endcase + 4'd6,4'd14: //38,46 + case (one_edge_counter_MR[1]) + 1'b0:bs_curr_MR <= bs_H2[2:0]; + 1'b1:bs_curr_MR <= bs_H2[5:3]; + endcase + 4'd7,4'd15: //39,47 + case (one_edge_counter_MR[1]) + 1'b0:bs_curr_MR <= bs_H2[8:6]; + 1'b1:bs_curr_MR <= bs_H2[11:9]; + endcase + endcase + else + bs_curr_MR <= 0; + + // Pipelined parameters + reg [2:0] bs_curr_TD; + reg lumaEdgeFlag_TD,chromaEdgeFlag_TD; + reg [5:0] DF_edge_counter_TD; + reg [1:0] one_edge_counter_TD; + always @ (posedge gclk_DF or negedge reset_n) + if (reset_n == 1'b0) + begin + bs_curr_TD <= 0; + lumaEdgeFlag_TD <= 0; + chromaEdgeFlag_TD <= 0; + DF_edge_counter_TD <= 6'd48; + one_edge_counter_TD <= 2'd3; + end + else + begin + bs_curr_TD <= bs_curr_MR; + lumaEdgeFlag_TD <= lumaEdgeFlag_MR; + chromaEdgeFlag_TD <= chromaEdgeFlag_MR; + DF_edge_counter_TD <= DF_edge_counter_MR; + one_edge_counter_TD <= one_edge_counter_MR; + end + //--------------------------------------------------------------------- + //2.TD: Threshold Decider + //--------------------------------------------------------------------- + wire [6:0] indexA_y_unclipped,indexA_c_unclipped; + wire [6:0] indexB_y_unclipped,indexB_c_unclipped; + assign indexA_y_unclipped = QPy + {{2{slice_alpha_c0_offset_div2[3]}},slice_alpha_c0_offset_div2,1'b0}; + assign indexA_c_unclipped = QPc + {{2{slice_alpha_c0_offset_div2[3]}},slice_alpha_c0_offset_div2,1'b0}; + assign indexB_y_unclipped = QPy + {{2{slice_beta_offset_div2[3]}},slice_beta_offset_div2,1'b0}; + assign indexB_c_unclipped = QPc + {{2{slice_beta_offset_div2[3]}},slice_beta_offset_div2,1'b0}; + + wire [5:0] indexA_y,indexA_c; + wire [5:0] indexB_y,indexB_c; + assign indexA_y = (indexA_y_unclipped[6] == 1)? 0:((indexA_y_unclipped[5:0] > 6'd51)? 6'd51:indexA_y_unclipped[5:0]); + assign indexA_c = (indexA_c_unclipped[6] == 1)? 0:((indexA_c_unclipped[5:0] > 6'd51)? 6'd51:indexA_c_unclipped[5:0]); + assign indexB_y = (indexB_y_unclipped[6] == 1)? 0:((indexB_y_unclipped[5:0] > 6'd51)? 6'd51:indexB_y_unclipped[5:0]); + assign indexB_c = (indexB_c_unclipped[6] == 1)? 0:((indexB_c_unclipped[5:0] > 6'd51)? 6'd51:indexB_c_unclipped[5:0]); + + reg [5:0] indexA_y_reg,indexA_c_reg; + reg [5:0] indexB_y_reg,indexB_c_reg; + always @ (posedge gclk_end_of_MB_DEC or negedge reset_n) + if (reset_n == 1'b0) + begin indexA_y_reg <= 0; indexA_c_reg <= 0; indexB_y_reg <= 0; indexB_c_reg <= 0; end + else if (!disable_DF) + begin + indexA_y_reg <= indexA_y; indexA_c_reg <= indexA_c; + indexB_y_reg <= indexB_y; indexB_c_reg <= indexB_c; + end + + wire [5:0] indexA,indexB; + assign indexA = (lumaEdgeFlag_TD)? indexA_y_reg:((chromaEdgeFlag_TD)? indexA_c_reg:0); + assign indexB = (lumaEdgeFlag_TD)? indexB_y_reg:((chromaEdgeFlag_TD)? indexB_c_reg:0); + + reg [7:0] alpha,beta; + //alpha + always @ (indexA) + if (indexA < 16) + alpha <= 0; + else + case (indexA) + 6'd16,6'd17:alpha <= 8'd4; + 6'd18:alpha <= 8'd5; 6'd19:alpha <= 8'd6; 6'd20:alpha <= 8'd7; 6'd21:alpha <= 8'd8; + 6'd22:alpha <= 8'd9; 6'd23:alpha <= 8'd10; 6'd24:alpha <= 8'd12; 6'd25:alpha <= 8'd13; + 6'd26:alpha <= 8'd15; 6'd27:alpha <= 8'd17; 6'd28:alpha <= 8'd20; 6'd29:alpha <= 8'd22; + 6'd30:alpha <= 8'd25; 6'd31:alpha <= 8'd28; 6'd32:alpha <= 8'd32; 6'd33:alpha <= 8'd36; + 6'd34:alpha <= 8'd40; 6'd35:alpha <= 8'd45; 6'd36:alpha <= 8'd50; 6'd37:alpha <= 8'd56; + 6'd38:alpha <= 8'd63; 6'd39:alpha <= 8'd71; 6'd40:alpha <= 8'd80; 6'd41:alpha <= 8'd90; + 6'd42:alpha <= 8'd101; 6'd43:alpha <= 8'd113; 6'd44:alpha <= 8'd127; 6'd45:alpha <= 8'd144; + 6'd46:alpha <= 8'd162; 6'd47:alpha <= 8'd182; 6'd48:alpha <= 8'd203; 6'd49:alpha <= 8'd226; + default:alpha <= 8'd255; + endcase + //beta + always @ (indexB) + if (indexB < 16) + beta <= 0; + else if (indexB > 15 && indexB < 26) + case (indexB) + 6'd16,6'd17,6'd18 :beta <= 8'd2; + 6'd19,6'd20,6'd21,6'd22 :beta <= 8'd3; + 6'd23,6'd24,6'd25 :beta <= 8'd4; + default:beta <= 0; + endcase + else + beta <= indexB[5:1] - 3'd7; + + wire [7:0] absolute_TD0_a,absolute_TD0_b; + wire [7:0] absolute_TD1_a,absolute_TD1_b; + wire [7:0] absolute_TD2_a,absolute_TD2_b; + wire [7:0] absolute_TD0_out,absolute_TD1_out,absolute_TD2_out; + absolute absolute_TD0 (.a(absolute_TD0_a),.b(absolute_TD0_b),.out(absolute_TD0_out)); + absolute absolute_TD1 (.a(absolute_TD1_a),.b(absolute_TD1_b),.out(absolute_TD1_out)); + absolute absolute_TD2 (.a(absolute_TD2_a),.b(absolute_TD2_b),.out(absolute_TD2_out)); + + //p0 ~ p3 + wire Is_p_from_mbAddrA; + wire Is_p_from_mbAddrB; + wire Is_p_from_buf0; + wire Is_p_from_buf1; + wire Is_p_from_buf2; + wire Is_p_from_buf3; + assign Is_p_from_mbAddrA = (DF_edge_counter_TD == 6'd0 || DF_edge_counter_TD == 6'd2 || + DF_edge_counter_TD == 6'd16 || DF_edge_counter_TD == 6'd18 || DF_edge_counter_TD == 6'd32 || + DF_edge_counter_TD == 6'd34 || DF_edge_counter_TD == 6'd40 || DF_edge_counter_TD == 6'd42); + + assign Is_p_from_mbAddrB = (DF_edge_counter_TD == 6'd4 || DF_edge_counter_TD == 6'd8 || + DF_edge_counter_TD == 6'd12 || DF_edge_counter_TD == 6'd13 || DF_edge_counter_TD == 6'd20 || + DF_edge_counter_TD == 6'd24 || DF_edge_counter_TD == 6'd28 || DF_edge_counter_TD == 6'd29 || + DF_edge_counter_TD == 6'd36 || DF_edge_counter_TD == 6'd37 || DF_edge_counter_TD == 6'd44 || + DF_edge_counter_TD == 6'd45); + + assign Is_p_from_buf0 = (DF_edge_counter_TD == 6'd1 || DF_edge_counter_TD == 6'd5 || + DF_edge_counter_TD == 6'd10 || DF_edge_counter_TD == 6'd14 || DF_edge_counter_TD == 6'd17 || + DF_edge_counter_TD == 6'd21 || DF_edge_counter_TD == 6'd26 || DF_edge_counter_TD == 6'd30 || + DF_edge_counter_TD == 6'd33 || DF_edge_counter_TD == 6'd38 || DF_edge_counter_TD == 6'd41 || + DF_edge_counter_TD == 6'd46); + + assign Is_p_from_buf1 = (DF_edge_counter_TD == 6'd6 || DF_edge_counter_TD == 6'd9 || + DF_edge_counter_TD == 6'd15 || DF_edge_counter_TD == 6'd22 || DF_edge_counter_TD == 6'd25 || + DF_edge_counter_TD == 6'd31 || DF_edge_counter_TD == 6'd39 || DF_edge_counter_TD == 6'd47); + + assign Is_p_from_buf2 = (DF_edge_counter_TD == 6'd3 || DF_edge_counter_TD == 6'd11 || + DF_edge_counter_TD == 6'd19 || DF_edge_counter_TD == 6'd27 || DF_edge_counter_TD == 6'd35 || + DF_edge_counter_TD == 6'd43); + + assign Is_p_from_buf3 = (DF_edge_counter_TD == 6'd7 || DF_edge_counter_TD == 6'd23); + + reg [7:0] p0,p1,p2,p3; + always @ (Is_p_from_mbAddrA or Is_p_from_mbAddrB or Is_p_from_buf0 or Is_p_from_buf1 or + Is_p_from_buf2 or Is_p_from_buf3 or one_edge_counter_TD or + DF_mbAddrA_RF_dout or DF_mbAddrB_RAM_dout or + buf0_0 or buf0_1 or buf0_2 or buf0_3 or buf1_0 or buf1_1 or buf1_2 or buf1_3 or + buf2_0 or buf2_1 or buf2_2 or buf2_3 or buf3_0 or buf3_1 or buf3_2 or buf3_3) + case ({Is_p_from_mbAddrA,Is_p_from_mbAddrB,Is_p_from_buf0,Is_p_from_buf1,Is_p_from_buf2,Is_p_from_buf3}) + 6'b100000:{p0,p1,p2,p3} <= DF_mbAddrA_RF_dout; + 6'b010000:{p0,p1,p2,p3} <= DF_mbAddrB_RAM_dout; + 6'b001000: case (one_edge_counter_TD) + 2'b00:{p0,p1,p2,p3} <= buf0_0; + 2'b01:{p0,p1,p2,p3} <= buf0_1; + 2'b10:{p0,p1,p2,p3} <= buf0_2; + 2'b11:{p0,p1,p2,p3} <= buf0_3; + endcase + 6'b000100: case (one_edge_counter_TD) + 2'b00:{p0,p1,p2,p3} <= buf1_0; + 2'b01:{p0,p1,p2,p3} <= buf1_1; + 2'b10:{p0,p1,p2,p3} <= buf1_2; + 2'b11:{p0,p1,p2,p3} <= buf1_3; + endcase + 6'b000010: case (one_edge_counter_TD) + 2'b00:{p0,p1,p2,p3} <= buf2_0; + 2'b01:{p0,p1,p2,p3} <= buf2_1; + 2'b10:{p0,p1,p2,p3} <= buf2_2; + 2'b11:{p0,p1,p2,p3} <= buf2_3; + endcase + 6'b000001: case (one_edge_counter_TD) + 2'b00:{p0,p1,p2,p3} <= buf3_0; + 2'b01:{p0,p1,p2,p3} <= buf3_1; + 2'b10:{p0,p1,p2,p3} <= buf3_2; + 2'b11:{p0,p1,p2,p3} <= buf3_3; + endcase + default:{p0,p1,p2,p3} <= 0; + endcase + + //q0 ~ q3 + wire Is_q_from_buf0; + wire Is_q_from_buf1; + wire Is_q_from_buf2; + wire Is_q_from_buf3; + + assign Is_q_from_buf0 = (DF_edge_counter_TD == 6'd4 || DF_edge_counter_TD == 6'd12 || + DF_edge_counter_TD == 6'd20 || DF_edge_counter_TD == 6'd28 || DF_edge_counter_TD == 6'd36 || + DF_edge_counter_TD == 6'd44); + + assign Is_q_from_buf1 = (DF_edge_counter_TD == 6'd8 || DF_edge_counter_TD == 6'd13 || + DF_edge_counter_TD == 6'd24 || DF_edge_counter_TD == 6'd29 || DF_edge_counter_TD == 6'd37 || + DF_edge_counter_TD == 6'd45); + + assign Is_q_from_buf2 = (DF_edge_counter_TD == 6'd5 || DF_edge_counter_TD == 6'd14 || + DF_edge_counter_TD == 6'd21 || DF_edge_counter_TD == 6'd30 || DF_edge_counter_TD == 6'd38 || + DF_edge_counter_TD == 6'd46); + + assign Is_q_from_buf3 = (DF_edge_counter_TD == 6'd9 || DF_edge_counter_TD == 6'd15 || + DF_edge_counter_TD == 6'd25 || DF_edge_counter_TD == 6'd31 || DF_edge_counter_TD == 6'd39 || + DF_edge_counter_TD == 6'd47); + + reg [7:0] q0,q1,q2,q3; + always @ (Is_q_from_buf0 or Is_q_from_buf1 or Is_q_from_buf2 or Is_q_from_buf3 or + rec_DF_RAM_dout or one_edge_counter_TD or DF_edge_counter_TD or + buf0_0 or buf0_1 or buf0_2 or buf0_3 or buf1_0 or buf1_1 or buf1_2 or buf1_3 or + buf2_0 or buf2_1 or buf2_2 or buf2_3 or buf3_0 or buf3_1 or buf3_2 or buf3_3) + case ({Is_q_from_buf0,Is_q_from_buf1,Is_q_from_buf2,Is_q_from_buf3}) + 4'b1000:case (one_edge_counter_TD) + 2'b00:{q3,q2,q1,q0} <= buf0_0; + 2'b01:{q3,q2,q1,q0} <= buf0_1; + 2'b10:{q3,q2,q1,q0} <= buf0_2; + 2'b11:{q3,q2,q1,q0} <= buf0_3; + endcase + 4'b0100:case (one_edge_counter_TD) + 2'b00:{q3,q2,q1,q0} <= buf1_0; + 2'b01:{q3,q2,q1,q0} <= buf1_1; + 2'b10:{q3,q2,q1,q0} <= buf1_2; + 2'b11:{q3,q2,q1,q0} <= buf1_3; + endcase + 4'b0010:case (one_edge_counter_TD) + 2'b00:{q3,q2,q1,q0} <= buf2_0; + 2'b01:{q3,q2,q1,q0} <= buf2_1; + 2'b10:{q3,q2,q1,q0} <= buf2_2; + 2'b11:{q3,q2,q1,q0} <= buf2_3; + endcase + 4'b0001:case (one_edge_counter_TD) + 2'b00:{q3,q2,q1,q0} <= buf3_0; + 2'b01:{q3,q2,q1,q0} <= buf3_1; + 2'b10:{q3,q2,q1,q0} <= buf3_2; + 2'b11:{q3,q2,q1,q0} <= buf3_3; + endcase + default:if (DF_edge_counter_TD != 6'd48) {q3,q2,q1,q0} <= rec_DF_RAM_dout; + else {q3,q2,q1,q0} <= 0; + endcase + + // |p0 - q0| < alpha + assign absolute_TD0_a = (!disable_DF && bs_curr_TD != 0)? p0:0; + assign absolute_TD0_b = (!disable_DF && bs_curr_TD != 0)? q0:0; + + // |p1 - p0| < beta + assign absolute_TD1_a = (!disable_DF && bs_curr_TD != 0)? p0:0; + assign absolute_TD1_b = (!disable_DF && bs_curr_TD != 0)? p1:0; + + // |q1 - q0| < beta + assign absolute_TD2_a = (!disable_DF && bs_curr_TD != 0)? q0:0; + assign absolute_TD2_b = (!disable_DF && bs_curr_TD != 0)? q1:0; + + // Threshold + wire threshold; + assign threshold = ((absolute_TD0_out < alpha) && (absolute_TD1_out < beta) && + (absolute_TD2_out < beta))? 1'b1:1'b0; + + // Pipelined parameters + reg [2:0] bs_curr_PRE; + reg [5:0] DF_edge_counter_PRE; + reg [1:0] one_edge_counter_PRE; + reg lumaEdgeFlag_PRE,chromaEdgeFlag_PRE; + reg [7:0] p0_PRE,p1_PRE,p2_PRE,p3_PRE; + reg [7:0] q0_PRE,q1_PRE,q2_PRE,q3_PRE; + reg [5:0] indexA_PRE; + reg [7:0] alpha_PRE,beta_PRE; + always @ (posedge gclk_DF or negedge reset_n) + if (reset_n == 1'b0) + begin + bs_curr_PRE <= 0; + DF_edge_counter_PRE <= 6'd48; + one_edge_counter_PRE <= 2'd3; + lumaEdgeFlag_PRE <= 0; + chromaEdgeFlag_PRE <= 0; + indexA_PRE <= 0; + alpha_PRE <= 0; + beta_PRE <= 0; + p0_PRE <= 0; p1_PRE <= 0; p2_PRE <= 0; p3_PRE <= 0; + q0_PRE <= 0; q1_PRE <= 0; q2_PRE <= 0; q3_PRE <= 0; + end + else + begin + bs_curr_PRE <= (threshold)? bs_curr_TD:0; + DF_edge_counter_PRE <= DF_edge_counter_TD; + one_edge_counter_PRE<= one_edge_counter_TD; + lumaEdgeFlag_PRE <= (threshold)? lumaEdgeFlag_TD:0; + chromaEdgeFlag_PRE <= (threshold)? chromaEdgeFlag_TD:0; + indexA_PRE <= (threshold)? indexA:0; + alpha_PRE <= (threshold)? alpha:0; + beta_PRE <= (threshold)? beta:0; + p0_PRE <= p0; p1_PRE <= p1; p2_PRE <= p2; p3_PRE <= p3; + q0_PRE <= q0; q1_PRE <= q1; q2_PRE <= q2; q3_PRE <= q3; + end + //--------------------------------------------------------------------- + //3.PRE: Precomputation + //--------------------------------------------------------------------- + wire [7:0] absolute_PRE0_a,absolute_PRE0_b; + wire [7:0] absolute_PRE1_a,absolute_PRE1_b; + wire [7:0] absolute_PRE2_a,absolute_PRE2_b; + wire [7:0] absolute_PRE0_out,absolute_PRE1_out,absolute_PRE2_out; + + absolute absolute_PRE0 (.a(absolute_PRE0_a),.b(absolute_PRE0_b),.out(absolute_PRE0_out)); + absolute absolute_PRE1 (.a(absolute_PRE1_a),.b(absolute_PRE1_b),.out(absolute_PRE1_out)); + absolute absolute_PRE2 (.a(absolute_PRE2_a),.b(absolute_PRE2_b),.out(absolute_PRE2_out)); + + // |p2 - p0| < beta + assign absolute_PRE0_a = (bs_curr_PRE != 0 && lumaEdgeFlag_PRE)? p2_PRE:0; + assign absolute_PRE0_b = (bs_curr_PRE != 0 && lumaEdgeFlag_PRE)? p0_PRE:0; + + // |q2 - q0| < beta + assign absolute_PRE1_a = (bs_curr_PRE != 0 && lumaEdgeFlag_PRE)? q2_PRE:0; + assign absolute_PRE1_b = (bs_curr_PRE != 0 && lumaEdgeFlag_PRE)? q0_PRE:0; + + // |p0 - q0| < alpha >> 2 + 2 + assign absolute_PRE2_a = (lumaEdgeFlag_PRE && bs_curr_PRE == 3'd4)? p0_PRE:0; + assign absolute_PRE2_b = (lumaEdgeFlag_PRE && bs_curr_PRE == 3'd4)? q0_PRE:0; + + wire p2_m_p0_less_beta,q2_m_q0_less_beta,p0_m_q0_less_alpha_shift; + assign p2_m_p0_less_beta = (bs_curr_PRE == 0 || !lumaEdgeFlag_PRE)? 1'b0: + ((absolute_PRE0_out < beta_PRE)? 1'b1:1'b0); + assign q2_m_q0_less_beta = (bs_curr_PRE == 0 || !lumaEdgeFlag_PRE)? 1'b0: + ((absolute_PRE1_out < beta_PRE)? 1'b1:1'b0); + assign p0_m_q0_less_alpha_shift = (!lumaEdgeFlag_PRE || bs_curr_PRE != 4)? 1'b0: + ((absolute_PRE2_out < ((alpha_PRE >> 2) + 2))? 1'b1:1'b0); + // bs = 1 ~ 3 + reg [4:0] c1; + always @ (bs_curr_PRE or indexA_PRE) + if (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4) + case (bs_curr_PRE) + 3'd1: + if (indexA_PRE < 23) c1 <= 5'd0; + else if (indexA_PRE < 33) c1 <= 5'd1; + else if (indexA_PRE < 37) c1 <= 5'd2; + else if (indexA_PRE < 40) c1 <= 5'd3; + else if (indexA_PRE < 43) c1 <= 5'd4; + else + case (indexA_PRE) + 6'd43:c1 <= 5'd5; 6'd44,6'd45:c1 <= 5'd6; + 6'd46:c1 <= 5'd7; 6'd47:c1 <= 5'd8; 6'd48:c1 <= 5'd9; + 6'd49:c1 <= 5'd10; 6'd50:c1 <= 5'd11; 6'd51:c1 <= 5'd13; + default:c1 <= 0; + endcase + 3'd2: + if (indexA_PRE < 21) c1 <= 5'd0; + else if (indexA_PRE < 31) c1 <= 5'd1; + else if (indexA_PRE < 35) c1 <= 5'd2; + else if (indexA_PRE < 38) c1 <= 5'd3; + else + case (indexA_PRE) + 6'd38,6'd39:c1 <= 5'd4; + 6'd40,6'd41:c1 <= 5'd5; + 6'd42:c1 <= 5'd6; 6'd43:c1 <= 5'd7; 6'd44,6'd45:c1 <= 5'd8; + 6'd46:c1 <= 5'd10; 6'd47:c1 <= 5'd11; 6'd48:c1 <= 5'd12; + 6'd49:c1 <= 5'd13; 6'd50:c1 <= 5'd15; 6'd51:c1 <= 5'd17; + default:c1 <= 5'd0; + endcase + 3'd3: + if (indexA_PRE < 17) c1 <= 5'd0; + else if (indexA_PRE < 27) c1 <= 5'd1; + else if (indexA_PRE < 31) c1 <= 5'd2; + else if (indexA_PRE < 34) c1 <= 5'd3; + else if (indexA_PRE < 37) c1 <= 5'd4; + else + case (indexA_PRE) + 6'd37:c1 <= 5'd5; 6'd38,6'd39:c1 <= 5'd6; + 6'd40:c1 <= 5'd7; 6'd41:c1 <= 5'd8; 6'd42:c1 <= 5'd9; 6'd43:c1 <= 5'd10; + 6'd44:c1 <= 5'd11; 6'd45:c1 <= 5'd13; 6'd46:c1 <= 5'd14; 6'd47:c1 <= 5'd16; + 6'd48:c1 <= 5'd18; 6'd49:c1 <= 5'd20; 6'd50:c1 <= 5'd23; 6'd51:c1 <= 5'd25; + default:c1 <= 5'd0; + endcase + default:c1 <= 0; + endcase + else + c1 <= 0; + + reg [4:0] c0; + always @ (bs_curr_PRE or lumaEdgeFlag_PRE or c1 or p2_m_p0_less_beta or q2_m_q0_less_beta) + if (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4) + begin + if (lumaEdgeFlag_PRE) //filter luma edge + c0 <= ( p2_m_p0_less_beta && q2_m_q0_less_beta)? (c1 + 2): + ((!p2_m_p0_less_beta && !q2_m_q0_less_beta)? c1:(c1+1)); + else //filter chroma edge + c0 <= c1 + 1; + end + else + c0 <= 0; + + //delta_0i = [(q0 - p0) << 2 + (p1 - q1) + 4] >> 3 : P151 (8-334) of H.264/AVC standard 2003 + wire [8:0] delta_0i; + wire need_delta_0i; + wire [8:0] q0_m_p0; //p0 - q0 + wire [11:0] delta_0i_tmp; //[(p0 - q0) << 2 + (p1 - q1) + 4] + assign need_delta_0i = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4); + assign q0_m_p0 = (need_delta_0i)? ({1'b0,q0_PRE} + {1'b1,~p0_PRE} + 1):0; + assign delta_0i_tmp = (need_delta_0i)? ({q0_m_p0[8],q0_m_p0,2'b0} + p1_PRE + {4'b1111,~q1_PRE} + 5):0; + assign delta_0i = delta_0i_tmp[11:3]; + + + //delta p1i = [(p2 + ((p0 + q0 + 1) >> 1) - (p1 << 1)] >> 1 : P152 (8-341) of H.264/AVC standard 2003 + //delta q1i = [(q2 + ((p0 + q0 + 1) >> 1) - (q1 << 1)] >> 1 : P152 (8-343) of H.264/AVC standard 2003 + wire [8:0] delta_p1i,delta_q1i; + wire need_p1i; + wire need_q1i; + wire [8:0] p0_q0_sum; //p0+q0+1 + wire [9:0] neg_p1_shift; //-(p1 << 1) + wire [9:0] neg_q1_shift; //-(q1 << 1) + wire [9:0] delta_p1i_tmp;// (p2 + ((p0 + q0 + 1) >> 1) - (p1 << 1) + wire [9:0] delta_q1i_tmp;// (q2 + ((p0 + q0 + 1) >> 1) - (q1 << 1) + assign need_p1i = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4 && p2_m_p0_less_beta); + assign need_q1i = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4 && q2_m_q0_less_beta); + assign p0_q0_sum = (need_p1i || need_q1i)? ({1'b0,p0_PRE} + {1'b0,q0_PRE} + 1):0; + assign neg_p1_shift = (need_p1i)? ({1'b1,~p1_PRE,1'b1} + 1):0; + assign neg_q1_shift = (need_q1i)? ({1'b1,~q1_PRE,1'b1} + 1):0; + assign delta_p1i_tmp = (need_p1i)? (p2_PRE + p0_q0_sum[8:1] + neg_p1_shift):0; + assign delta_q1i_tmp = (need_q1i)? (q2_PRE + p0_q0_sum[8:1] + neg_q1_shift):0; + assign delta_p1i = delta_p1i_tmp[9:1]; + assign delta_q1i = delta_q1i_tmp[9:1]; + + wire [8:0] clip_to_c_0_delta,clip_to_c_p1_delta,clip_to_c_q1_delta; + wire [4:0] clip_to_c_0_c,clip_to_c_p1_c,clip_to_c_q1_c; + wire [5:0] clip_to_c_0_out,clip_to_c_p1_out,clip_to_c_q1_out; + clip_to_c clip_to_c_0 (.delta(clip_to_c_0_delta),.c(clip_to_c_0_c),.out(clip_to_c_0_out)); + clip_to_c clip_to_c_p1 (.delta(clip_to_c_p1_delta),.c(clip_to_c_p1_c),.out(clip_to_c_p1_out)); + clip_to_c clip_to_c_q1 (.delta(clip_to_c_q1_delta),.c(clip_to_c_q1_c),.out(clip_to_c_q1_out)); + + assign clip_to_c_0_delta = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4)? delta_0i:0; + assign clip_to_c_0_c = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4)? c0:0; + assign clip_to_c_p1_delta = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4 && p2_m_p0_less_beta)? delta_p1i:0; + assign clip_to_c_p1_c = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4 && p2_m_p0_less_beta)? c1:0; + assign clip_to_c_q1_delta = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4 && q2_m_q0_less_beta)? delta_q1i:0; + assign clip_to_c_q1_c = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4 && q2_m_q0_less_beta)? c1:0; + + // Pipelined parameters + reg [5:0] delta_0,delta_p1,delta_q1; + always @ (posedge gclk_DF or negedge reset_n) + if (reset_n == 1'b0) + begin delta_0 <= 0; delta_p1 <= 0; delta_q1 <= 0; end + else if (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4) + begin + delta_0 <= clip_to_c_0_out; + delta_p1 <= (p2_m_p0_less_beta)? clip_to_c_p1_out:0; + delta_q1 <= (q2_m_q0_less_beta)? clip_to_c_q1_out:0; + end + + reg p2_m_p0_less_beta_FIR,q2_m_q0_less_beta_FIR,p0_m_q0_less_alpha_shift_FIR; + reg lumaEdgeFlag_FIR,chromaEdgeFlag_FIR; + reg [2:0] bs_curr_FIR; + reg [5:0] DF_edge_counter_FIR; + reg [1:0] one_edge_counter_FIR; + reg [7:0] p0_FIR,p1_FIR,p2_FIR,p3_FIR; + reg [7:0] q0_FIR,q1_FIR,q2_FIR,q3_FIR; + always @ (posedge gclk_DF or negedge reset_n) + if (reset_n == 1'b0) + begin + p2_m_p0_less_beta_FIR <= 0; q2_m_q0_less_beta_FIR <= 0; + p0_m_q0_less_alpha_shift_FIR <= 0; + bs_curr_FIR <= 0; + lumaEdgeFlag_FIR <= 0; chromaEdgeFlag_FIR <= 0; + DF_edge_counter_FIR <= 6'd48; one_edge_counter_FIR <= 2'd3; + p0_FIR <= 0; p1_FIR <= 0; p2_FIR <= 0; p3_FIR <= 0; + q0_FIR <= 0; q1_FIR <= 0; q2_FIR <= 0; q3_FIR <= 0; + end + else + begin + p2_m_p0_less_beta_FIR <= p2_m_p0_less_beta; + q2_m_q0_less_beta_FIR <= q2_m_q0_less_beta; + p0_m_q0_less_alpha_shift_FIR <= p0_m_q0_less_alpha_shift; + bs_curr_FIR <= bs_curr_PRE; + lumaEdgeFlag_FIR <= lumaEdgeFlag_PRE; chromaEdgeFlag_FIR <= chromaEdgeFlag_PRE; + DF_edge_counter_FIR <= DF_edge_counter_PRE; one_edge_counter_FIR <= one_edge_counter_PRE; + p0_FIR <= p0_PRE; p1_FIR <= p1_PRE; p2_FIR <= p2_PRE; p3_FIR <= p3_PRE; + q0_FIR <= q0_PRE; q1_FIR <= q1_PRE; q2_FIR <= q2_PRE; q3_FIR <= q3_PRE; + end + //--------------------------------------------------------------------- + //4.FIR: filtering + //--------------------------------------------------------------------- + reg [7:0] bs4_strong_FIR_p0,bs4_strong_FIR_p1,bs4_strong_FIR_p2,bs4_strong_FIR_p3; + reg [7:0] bs4_strong_FIR_q0,bs4_strong_FIR_q1,bs4_strong_FIR_q2,bs4_strong_FIR_q3; + wire [7:0] bs4_strong_FIR_p0_out,bs4_strong_FIR_p1_out,bs4_strong_FIR_p2_out; + wire [7:0] bs4_strong_FIR_q0_out,bs4_strong_FIR_q1_out,bs4_strong_FIR_q2_out; + bs4_strong_FIR bs4_strong_FIR ( + .p0(bs4_strong_FIR_p0),.p1(bs4_strong_FIR_p1),.p2(bs4_strong_FIR_p2),.p3(bs4_strong_FIR_p3), + .q0(bs4_strong_FIR_q0),.q1(bs4_strong_FIR_q1),.q2(bs4_strong_FIR_q2),.q3(bs4_strong_FIR_q3), + .p0_out(bs4_strong_FIR_p0_out),.p1_out(bs4_strong_FIR_p1_out),.p2_out(bs4_strong_FIR_p2_out), + .q0_out(bs4_strong_FIR_q0_out),.q1_out(bs4_strong_FIR_q1_out),.q2_out(bs4_strong_FIR_q2_out) + ); + reg [7:0] bs4_weak_FIR0_a,bs4_weak_FIR0_b,bs4_weak_FIR0_c; + reg [7:0] bs4_weak_FIR1_a,bs4_weak_FIR1_b,bs4_weak_FIR1_c; + wire [7:0] bs4_weak_FIR0_out,bs4_weak_FIR1_out; + bs4_weak_FIR bs4_weak_FIR0 (.a(bs4_weak_FIR0_a),.b(bs4_weak_FIR0_b),.c(bs4_weak_FIR0_c),.out(bs4_weak_FIR0_out)); + bs4_weak_FIR bs4_weak_FIR1 (.a(bs4_weak_FIR1_a),.b(bs4_weak_FIR1_b),.c(bs4_weak_FIR1_c),.out(bs4_weak_FIR1_out)); + // bs = 4 + always @ (bs_curr_FIR or lumaEdgeFlag_FIR or p0_m_q0_less_alpha_shift_FIR + or p2_m_p0_less_beta_FIR or q2_m_q0_less_beta_FIR + or p0_FIR or p1_FIR or p2_FIR or p3_FIR or q0_FIR or q1_FIR or q2_FIR or q3_FIR) + if (bs_curr_FIR == 3'd4 && lumaEdgeFlag_FIR == 1'b1 && p0_m_q0_less_alpha_shift_FIR + && (p2_m_p0_less_beta_FIR || q2_m_q0_less_beta_FIR)) + begin + bs4_strong_FIR_p0 <= p0_FIR; bs4_strong_FIR_p1 <= p1_FIR; + bs4_strong_FIR_p2 <= p2_FIR; bs4_strong_FIR_p3 <= p3_FIR; + bs4_strong_FIR_q0 <= q0_FIR; bs4_strong_FIR_q1 <= q1_FIR; + bs4_strong_FIR_q2 <= q2_FIR; bs4_strong_FIR_q3 <= q3_FIR; + end + else + begin + bs4_strong_FIR_p0 <= 0; bs4_strong_FIR_p1 <= 0; bs4_strong_FIR_p2 <= 0; bs4_strong_FIR_p3 <= 0; + bs4_strong_FIR_q0 <= 0; bs4_strong_FIR_q1 <= 0; bs4_strong_FIR_q2 <= 0; bs4_strong_FIR_q3 <= 0; + end + always @ (bs_curr_FIR or lumaEdgeFlag_FIR or chromaEdgeFlag_FIR + or p2_m_p0_less_beta_FIR or p0_m_q0_less_alpha_shift_FIR + or p1_FIR or p0_FIR or q1_FIR) + if (bs_curr_FIR == 3'd4 && lumaEdgeFlag_FIR == 1'b1) + begin + if (!p2_m_p0_less_beta_FIR || !p0_m_q0_less_alpha_shift_FIR) + begin + bs4_weak_FIR0_a <= p1_FIR; bs4_weak_FIR0_b <= p0_FIR; bs4_weak_FIR0_c <= q1_FIR; + end + else + begin + bs4_weak_FIR0_a <= 0; bs4_weak_FIR0_b <= 0; bs4_weak_FIR0_c <= 0; + end + end + else if (bs_curr_FIR == 3'd4 && chromaEdgeFlag_FIR == 1'b1) + begin + bs4_weak_FIR0_a <= p1_FIR; bs4_weak_FIR0_b <= p0_FIR; bs4_weak_FIR0_c <= q1_FIR; + end + else + begin + bs4_weak_FIR0_a <= 0; bs4_weak_FIR0_b <= 0; bs4_weak_FIR0_c <= 0; + end + always @ (bs_curr_FIR or lumaEdgeFlag_FIR or chromaEdgeFlag_FIR + or q2_m_q0_less_beta_FIR or p0_m_q0_less_alpha_shift_FIR + or q1_FIR or q0_FIR or p1_FIR) + if (bs_curr_FIR == 3'd4 && lumaEdgeFlag_FIR == 1'b1) + begin + if (!q2_m_q0_less_beta_FIR || !p0_m_q0_less_alpha_shift_FIR) + begin + bs4_weak_FIR1_a <= q1_FIR; bs4_weak_FIR1_b <= q0_FIR; bs4_weak_FIR1_c <= p1_FIR; + end + else + begin + bs4_weak_FIR1_a <= 0; bs4_weak_FIR1_b <= 0; bs4_weak_FIR1_c <= 0; + end + end + else if (bs_curr_FIR == 3'd4 && chromaEdgeFlag_FIR == 1'b1) + begin + bs4_weak_FIR1_a <= q1_FIR; bs4_weak_FIR1_b <= q0_FIR; bs4_weak_FIR1_c <= p1_FIR; + end + else + begin + bs4_weak_FIR1_a <= 0; bs4_weak_FIR1_b <= 0; bs4_weak_FIR1_c <= 0; + end + //bs = 1 ~ 3,for p0 and q0 filtering + wire [9:0] p0_MW_tmp,q0_MW_tmp; + wire [7:0] p0_MW_clipped,q0_MW_clipped; + assign p0_MW_tmp = (bs_curr_FIR != 0 && bs_curr_FIR != 3'd4)? ({2'b0,p0_FIR} + {{4{delta_0[5]}},delta_0}):0; + assign q0_MW_tmp = (bs_curr_FIR != 0 && bs_curr_FIR != 3'd4)? ({2'b0,q0_FIR} + + {~delta_0[5],~delta_0[5],~delta_0[5],~delta_0[5],~delta_0} + 1):0; + assign p0_MW_clipped = (p0_MW_tmp[9] == 1'b1)? 0:((p0_MW_tmp[8] == 1'b1)? 8'd255:p0_MW_tmp[7:0]); + assign q0_MW_clipped = (q0_MW_tmp[9] == 1'b1)? 0:((q0_MW_tmp[8] == 1'b1)? 8'd255:q0_MW_tmp[7:0]); + + // Pipelined parameters + reg [7:0] p0_MW,p1_MW,p2_MW,p3_MW; + reg [7:0] q0_MW,q1_MW,q2_MW,q3_MW; + always @ (posedge gclk_DF or negedge reset_n) + if (reset_n == 1'b0) + begin + p0_MW <= 0; p1_MW <= 0; p2_MW <= 0; + q0_MW <= 0; q1_MW <= 0; q2_MW <= 0; + end + else if (bs_curr_FIR == 3'd4) + begin + if (lumaEdgeFlag_FIR) + begin + p0_MW <= (p0_m_q0_less_alpha_shift_FIR && p2_m_p0_less_beta_FIR)? + bs4_strong_FIR_p0_out:bs4_weak_FIR0_out; + q0_MW <= (p0_m_q0_less_alpha_shift_FIR && q2_m_q0_less_beta_FIR)? + bs4_strong_FIR_q0_out:bs4_weak_FIR1_out; + p1_MW <= (p0_m_q0_less_alpha_shift_FIR && p2_m_p0_less_beta_FIR)? + bs4_strong_FIR_p1_out:p1_FIR; + q1_MW <= (p0_m_q0_less_alpha_shift_FIR && q2_m_q0_less_beta_FIR)? + bs4_strong_FIR_q1_out:q1_FIR; + p2_MW <= (p0_m_q0_less_alpha_shift_FIR && p2_m_p0_less_beta_FIR)? + bs4_strong_FIR_p2_out:p2_FIR; + q2_MW <= (p0_m_q0_less_alpha_shift_FIR && q2_m_q0_less_beta_FIR)? + bs4_strong_FIR_q2_out:q2_FIR; + end + else + begin + p0_MW <= bs4_weak_FIR0_out; q0_MW <= bs4_weak_FIR1_out; + p1_MW <= p1_FIR; q1_MW <= q1_FIR; + p2_MW <= p2_FIR; q2_MW <= q2_FIR; + end + end + else if (bs_curr_FIR != 0 && bs_curr_FIR != 3'd4) + begin + p0_MW <= p0_MW_clipped; + q0_MW <= q0_MW_clipped; + p1_MW <= (lumaEdgeFlag_FIR)? ((p2_m_p0_less_beta_FIR)? (p1_FIR + {delta_p1[5],delta_p1[5],delta_p1}):p1_FIR):p1_FIR; + q1_MW <= (lumaEdgeFlag_FIR)? ((q2_m_q0_less_beta_FIR)? (q1_FIR + {delta_q1[5],delta_q1[5],delta_q1}):q1_FIR):q1_FIR; + p2_MW <= p2_FIR; + q2_MW <= q2_FIR; + end + else + begin + p0_MW <= p0_FIR; p1_MW <= p1_FIR; p2_MW <= p2_FIR; + q0_MW <= q0_FIR; q1_MW <= q1_FIR; q2_MW <= q2_FIR; + end + + reg [2:0] bs_curr_MW; + reg [5:0] DF_edge_counter_MW; + reg [1:0] one_edge_counter_MW; + always @ (posedge gclk_DF or negedge reset_n) + if (reset_n == 1'b0) + begin + DF_edge_counter_MW <= 6'd48; one_edge_counter_MW <= 2'd3; + p3_MW <= 0; q3_MW <= 0; + bs_curr_MW <= 0; + end + else + begin + DF_edge_counter_MW <= DF_edge_counter_FIR; p3_MW <= p3_FIR; + one_edge_counter_MW <= one_edge_counter_FIR; q3_MW <= q3_FIR; + bs_curr_MW <= bs_curr_FIR; + end +endmodule + +module absolute (a,b,out); + input [7:0] a,b; + output [7:0] out; + + assign out = (a > b)? (a - b):(b - a); +endmodule + +module clip_to_c (delta,c,out); + input [8:0] delta; + input [4:0] c; // 0 ~ 25, [4:0] + output [5:0] out; // -25 ~ 25, [5:0] + reg [5:0] out; + + wire [5:0] neg_c; //-25 ~ 25,[5:0] + assign neg_c = {1'b1,~c} + 1; + + always @ (delta or c or neg_c) + if (delta[8] == 1'b0) //delta is positive + out <= (delta[7:0] > {3'b0,c})? {1'b0,c}:delta[5:0]; + else //delta is negtive + out <= (delta[7:0] < {2'b11,neg_c})? {1'b1,neg_c}:delta[5:0]; +endmodule + +module bs4_strong_FIR (p0,p1,p2,p3,q0,q1,q2,q3,p0_out,p1_out,p2_out,q0_out,q1_out,q2_out); + input [7:0] p0,p1,p2,p3,q0,q1,q2,q3; + output [7:0] p0_out,p1_out,p2_out,q0_out,q1_out,q2_out; + + wire [8:0] sum_p2p3,sum_p1p2,sum_p0q0,sum_p1q1,sum_q1q2,sum_q2q3; + assign sum_p2p3 = p2 + p3; + assign sum_p1p2 = p1 + p2; + assign sum_p0q0 = p0 + q0; + assign sum_p1q1 = p1 + q1; + assign sum_q1q2 = q1 + q2; + assign sum_q2q3 = q2 + q3; + + wire [9:0] sum_p2p3_x2,sum_q2q3_x2; + assign sum_p2p3_x2 = {sum_p2p3,1'b0}; + assign sum_q2q3_x2 = {sum_q2q3,1'b0}; + + wire [9:0] sum_0,sum_1,sum_2; + assign sum_0 = sum_p0q0 + sum_p1p2; + assign sum_1 = sum_p0q0 + sum_p1q1; + assign sum_2 = sum_p0q0 + sum_q1q2; + + wire [10:0] p0_tmp,p2_tmp,q0_tmp,q2_tmp; + assign p0_tmp = sum_0 + sum_1; + assign p2_tmp = sum_p2p3_x2 + sum_0; + assign q0_tmp = sum_1 + sum_2; + assign q2_tmp = sum_q2q3_x2 + sum_2; + + assign p0_out = (p0_tmp + 4) >> 3; + assign p1_out = (sum_0 + 2) >> 2; + assign p2_out = (p2_tmp + 4) >> 3; + assign q0_out = (q0_tmp + 4) >> 3; + assign q1_out = (sum_2 + 2) >> 2; + assign q2_out = (q2_tmp + 4) >> 3; +endmodule + +module bs4_weak_FIR (a,b,c,out); + input [7:0] a,b,c; + output [7:0] out; + + wire [8:0] a_x2; + assign a_x2 = {a,1'b0}; + + wire [8:0] sum_bc; + assign sum_bc = b + c; + + wire [9:0] out_tmp; + assign out_tmp = (a_x2 + sum_bc) + 2; + assign out = out_tmp[9:2]; +endmodule + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/DF_reg_ctrl.v b/demo_chip_rtl/rtl/nova/tags/Start/src/DF_reg_ctrl.v new file mode 100644 index 0000000..803874a --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/DF_reg_ctrl.v @@ -0,0 +1,335 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : DF_reg_ctrl.v +// Generated : Nov 27,2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// buffer buf0 ~ buf3 & transpose reg t0 ~ t1 control +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module DF_reg_ctrl (gclk_DF,reset_n,DF_edge_counter_MW,one_edge_counter_MW, + mb_num_h_DF,mb_num_v_DF,q0_MW,q1_MW,q2_MW,q3_MW,p0_MW,p1_MW,p2_MW,p3_MW, + buf0_0,buf0_1,buf0_2,buf0_3,buf1_0,buf1_1,buf1_2,buf1_3, + buf2_0,buf2_1,buf2_2,buf2_3,buf3_0,buf3_1,buf3_2,buf3_3, + t0_0,t0_1,t0_2,t0_3,t1_0,t1_1,t1_2,t1_3,t2_0,t2_1,t2_2,t2_3); + input gclk_DF,reset_n; + input [5:0] DF_edge_counter_MW; + input [1:0] one_edge_counter_MW; + input [3:0] mb_num_h_DF; + input [3:0] mb_num_v_DF; + input [7:0] q0_MW,q1_MW,q2_MW,q3_MW; + input [7:0] p0_MW,p1_MW,p2_MW,p3_MW; + + output [31:0] buf0_0,buf0_1,buf0_2,buf0_3; + output [31:0] buf1_0,buf1_1,buf1_2,buf1_3; + output [31:0] buf2_0,buf2_1,buf2_2,buf2_3; + output [31:0] buf3_0,buf3_1,buf3_2,buf3_3; + output [31:0] t0_0,t0_1,t0_2,t0_3; + output [31:0] t1_0,t1_1,t1_2,t1_3; + output [31:0] t2_0,t2_1,t2_2,t2_3; + + reg [31:0] buf0_0,buf0_1,buf0_2,buf0_3; + reg [31:0] buf1_0,buf1_1,buf1_2,buf1_3; + reg [31:0] buf2_0,buf2_1,buf2_2,buf2_3; + reg [31:0] buf3_0,buf3_1,buf3_2,buf3_3; + reg [31:0] t0_0,t0_1,t0_2,t0_3; + reg [31:0] t1_0,t1_1,t1_2,t1_3; + reg [31:0] t2_0,t2_1,t2_2,t2_3; + //------------------------------------------------------ + //buf0 + //------------------------------------------------------ + wire buf0_no_transpose; //buf0 updated without transpose + wire buf0_transpose; //buf0 updated after transpose + assign buf0_no_transpose = ( + DF_edge_counter_MW == 6'd0 || DF_edge_counter_MW == 6'd4 || DF_edge_counter_MW == 6'd6 || + DF_edge_counter_MW == 6'd12 || DF_edge_counter_MW == 6'd16 || DF_edge_counter_MW == 6'd20 || + DF_edge_counter_MW == 6'd22 || DF_edge_counter_MW == 6'd28 || DF_edge_counter_MW == 6'd32 || + DF_edge_counter_MW == 6'd36 || DF_edge_counter_MW == 6'd40 || DF_edge_counter_MW == 6'd44); + assign buf0_transpose = ( + DF_edge_counter_MW == 6'd1 || DF_edge_counter_MW == 6'd5 || DF_edge_counter_MW == 6'd10 || + DF_edge_counter_MW == 6'd14 || DF_edge_counter_MW == 6'd17 || DF_edge_counter_MW == 6'd26 || + DF_edge_counter_MW == 6'd30 || DF_edge_counter_MW == 6'd33 || DF_edge_counter_MW == 6'd38 || + DF_edge_counter_MW == 6'd41 || DF_edge_counter_MW == 6'd46); + + always @ (posedge gclk_DF or negedge reset_n) + if (reset_n == 1'b0) + begin + buf0_0 <= 0; buf0_1 <= 0; buf0_2 <= 0; buf0_3 <= 0; + end + //no transpose update,always "q" position (right or down of the edge to be filtered) + else if (buf0_no_transpose) + case (one_edge_counter_MW) + 2'd0:buf0_0 <= {q3_MW,q2_MW,q1_MW,q0_MW}; + 2'd1:buf0_1 <= {q3_MW,q2_MW,q1_MW,q0_MW}; + 2'd2:buf0_2 <= {q3_MW,q2_MW,q1_MW,q0_MW}; + 2'd3:buf0_3 <= {q3_MW,q2_MW,q1_MW,q0_MW}; + endcase + //transpose update,always "p" position (left or up of the edge to be filtered) + else if (buf0_transpose) + case (one_edge_counter_MW) + 2'd0:begin buf0_0[7:0] <= p3_MW; buf0_1[7:0] <= p2_MW; + buf0_2[7:0] <= p1_MW; buf0_3[7:0] <= p0_MW; end + 2'd1:begin buf0_0[15:8] <= p3_MW; buf0_1[15:8] <= p2_MW; + buf0_2[15:8] <= p1_MW; buf0_3[15:8] <= p0_MW; end + 2'd2:begin buf0_0[23:16] <= p3_MW; buf0_1[23:16] <= p2_MW; + buf0_2[23:16] <= p1_MW; buf0_3[23:16] <= p0_MW; end + 2'd3:begin buf0_0[31:24] <= p3_MW; buf0_1[31:24] <= p2_MW; + buf0_2[31:24] <= p1_MW; buf0_3[31:24] <= p0_MW; end + endcase + //------------------------------------------------------ + //buf1 + //------------------------------------------------------ + wire buf1_no_transpose; //buf1 updated without transpose + wire buf1_transpose; //buf1 updated after transpose + wire buf1_transpose_p; //buf1 transpose and buf1 stores "p" position pixels + assign buf1_no_transpose = ( + DF_edge_counter_MW == 6'd1 || DF_edge_counter_MW == 6'd8 || DF_edge_counter_MW == 6'd13 || + DF_edge_counter_MW == 6'd17 || DF_edge_counter_MW == 6'd24 || DF_edge_counter_MW == 6'd29 || + DF_edge_counter_MW == 6'd37 || DF_edge_counter_MW == 6'd45); + assign buf1_transpose = ( + DF_edge_counter_MW == 6'd6 || DF_edge_counter_MW == 6'd10 || DF_edge_counter_MW == 6'd22 || + DF_edge_counter_MW == 6'd26 || DF_edge_counter_MW == 6'd33 || DF_edge_counter_MW == 6'd41); + assign buf1_transpose_p = (DF_edge_counter_MW == 6'd6 || DF_edge_counter_MW == 6'd9 + || DF_edge_counter_MW == 6'd22); + always @ (posedge gclk_DF or negedge reset_n) + if (reset_n == 1'b0) + begin + buf1_0 <= 0; buf1_1 <= 0; buf1_2 <= 0; buf1_3 <= 0; + end + //no transpose update,always "q" position (right or down of the edge to be filtered) + else if (buf1_no_transpose) + case (one_edge_counter_MW) + 2'd0:buf1_0 <= {q3_MW,q2_MW,q1_MW,q0_MW}; + 2'd1:buf1_1 <= {q3_MW,q2_MW,q1_MW,q0_MW}; + 2'd2:buf1_2 <= {q3_MW,q2_MW,q1_MW,q0_MW}; + 2'd3:buf1_3 <= {q3_MW,q2_MW,q1_MW,q0_MW}; + endcase + //transpose update,"p":6/9/22,"q":10,26,33,41 + else if (buf1_transpose) + begin + if (buf1_transpose_p) // edge 6,22 "p" + case (one_edge_counter_MW) + 2'd0:begin buf1_0[7:0] <= p3_MW; buf1_1[7:0] <= p2_MW; + buf1_2[7:0] <= p1_MW; buf1_3[7:0] <= p0_MW; end + 2'd1:begin buf1_0[15:8] <= p3_MW; buf1_1[15:8] <= p2_MW; + buf1_2[15:8] <= p1_MW; buf1_3[15:8] <= p0_MW; end + 2'd2:begin buf1_0[23:16] <= p3_MW; buf1_1[23:16] <= p2_MW; + buf1_2[23:16] <= p1_MW; buf1_3[23:16] <= p0_MW; end + 2'd3:begin buf1_0[31:24] <= p3_MW; buf1_1[31:24] <= p2_MW; + buf1_2[31:24] <= p1_MW; buf1_3[31:24] <= p0_MW; end + endcase + else //edge 10,26,33,41 "q" + case (one_edge_counter_MW) + 2'd0:begin buf1_0[7:0] <= q0_MW; buf1_1[7:0] <= q1_MW; + buf1_2[7:0] <= q2_MW; buf1_3[7:0] <= q3_MW; end + 2'd1:begin buf1_0[15:8] <= q0_MW; buf1_1[15:8] <= q1_MW; + buf1_2[15:8] <= q2_MW; buf1_3[15:8] <= q3_MW; end + 2'd2:begin buf1_0[23:16] <= q0_MW; buf1_1[23:16] <= q1_MW; + buf1_2[23:16] <= q2_MW; buf1_3[23:16] <= q3_MW; end + 2'd3:begin buf1_0[31:24] <= q0_MW; buf1_1[31:24] <= q1_MW; + buf1_2[31:24] <= q2_MW; buf1_3[31:24] <= q3_MW; end + endcase + end + //------------------------------------------------------ + //buf2 + //------------------------------------------------------ + wire buf2_no_transpose; //buf2 updated without transpose + wire buf2_transpose; //buf2 updated after transpose + wire buf2_transpose_p; //buf2 transpose and buf2 stores "p" position pixels + assign buf2_no_transpose = ( + DF_edge_counter_MW == 6'd2 || DF_edge_counter_MW == 6'd7 || DF_edge_counter_MW == 6'd18 || + DF_edge_counter_MW == 6'd23 || DF_edge_counter_MW == 6'd34 || DF_edge_counter_MW == 6'd42); + assign buf2_transpose = ( + DF_edge_counter_MW == 6'd3 || DF_edge_counter_MW == 6'd11 || DF_edge_counter_MW == 6'd19 || + DF_edge_counter_MW == 6'd21 || DF_edge_counter_MW == 6'd27 || DF_edge_counter_MW == 6'd30 || + DF_edge_counter_MW == 6'd35 || DF_edge_counter_MW == 6'd38 || DF_edge_counter_MW == 6'd43 || + DF_edge_counter_MW == 6'd46); + assign buf2_transpose_p = (DF_edge_counter_MW == 6'd3 || DF_edge_counter_MW == 6'd11 + || DF_edge_counter_MW == 6'd19 || DF_edge_counter_MW == 6'd27 + || DF_edge_counter_MW == 6'd35 || DF_edge_counter_MW == 6'd43); + always @ (posedge gclk_DF or negedge reset_n) + if (reset_n == 1'b0) + begin + buf2_0 <= 0; buf2_1 <= 0; buf2_2 <= 0; buf2_3 <= 0; + end + //no transpose update,always "q" position (right or down of the edge to be filtered) + else if (buf2_no_transpose) + case (one_edge_counter_MW) + 2'd0:buf2_0 <= {q3_MW,q2_MW,q1_MW,q0_MW}; + 2'd1:buf2_1 <= {q3_MW,q2_MW,q1_MW,q0_MW}; + 2'd2:buf2_2 <= {q3_MW,q2_MW,q1_MW,q0_MW}; + 2'd3:buf2_3 <= {q3_MW,q2_MW,q1_MW,q0_MW}; + endcase + //transpose update,"p":3,11,19,27,35,43 "q":21,30,38,46 + else if (buf2_transpose) + begin + if (buf2_transpose_p) //"p":3,11,19,27,35,43 + case (one_edge_counter_MW) + 2'd0:begin buf2_0[7:0] <= p3_MW; buf2_1[7:0] <= p2_MW; + buf2_2[7:0] <= p1_MW; buf2_3[7:0] <= p0_MW; end + 2'd1:begin buf2_0[15:8] <= p3_MW; buf2_1[15:8] <= p2_MW; + buf2_2[15:8] <= p1_MW; buf2_3[15:8] <= p0_MW; end + 2'd2:begin buf2_0[23:16] <= p3_MW; buf2_1[23:16] <= p2_MW; + buf2_2[23:16] <= p1_MW; buf2_3[23:16] <= p0_MW; end + 2'd3:begin buf2_0[31:24] <= p3_MW; buf2_1[31:24] <= p2_MW; + buf2_2[31:24] <= p1_MW; buf2_3[31:24] <= p0_MW; end + endcase + else //"q":21,30,38,46 + case (one_edge_counter_MW) + 2'd0:begin buf2_0[7:0] <= q0_MW; buf2_1[7:0] <= q1_MW; + buf2_2[7:0] <= q2_MW; buf2_3[7:0] <= q3_MW; end + 2'd1:begin buf2_0[15:8] <= q0_MW; buf2_1[15:8] <= q1_MW; + buf2_2[15:8] <= q2_MW; buf2_3[15:8] <= q3_MW; end + 2'd2:begin buf2_0[23:16] <= q0_MW; buf2_1[23:16] <= q1_MW; + buf2_2[23:16] <= q2_MW; buf2_3[23:16] <= q3_MW; end + 2'd3:begin buf2_0[31:24] <= q0_MW; buf2_1[31:24] <= q1_MW; + buf2_2[31:24] <= q2_MW; buf2_3[31:24] <= q3_MW; end + endcase + end + //------------------------------------------------------ + //buf3 + //------------------------------------------------------ + wire buf3_no_transpose; //buf3 updated without transpose + wire buf3_transpose; //buf3 updated after transpose + wire buf3_transpose_p; //buf3 transpose and buf1 stores "p" position pixels + assign buf3_no_transpose = (DF_edge_counter_MW == 6'd3 || DF_edge_counter_MW == 6'd19); + assign buf3_transpose = ( DF_edge_counter_MW == 6'd7 || + DF_edge_counter_MW == 6'd11 || DF_edge_counter_MW == 6'd23 || DF_edge_counter_MW == 6'd27 || + DF_edge_counter_MW == 6'd25 || DF_edge_counter_MW == 6'd35 || DF_edge_counter_MW == 6'd43); + assign buf3_transpose_p = (DF_edge_counter_MW == 6'd7 || DF_edge_counter_MW == 6'd23); + always @ (posedge gclk_DF or negedge reset_n) + if (reset_n == 1'b0) + begin + buf3_0 <= 0; buf3_1 <= 0; buf3_2 <= 0; buf3_3 <= 0; + end + //no transpose update,always "q" position (right or down of the edge to be filtered) + else if (buf3_no_transpose) + case (one_edge_counter_MW) + 2'd0:buf3_0 <= {q3_MW,q2_MW,q1_MW,q0_MW}; + 2'd1:buf3_1 <= {q3_MW,q2_MW,q1_MW,q0_MW}; + 2'd2:buf3_2 <= {q3_MW,q2_MW,q1_MW,q0_MW}; + 2'd3:buf3_3 <= {q3_MW,q2_MW,q1_MW,q0_MW}; + endcase + //transpose update,"p":7,23 "q":11,25,27,35,43 + else if (buf3_transpose) + begin + if (buf3_transpose_p) //"p":7,23 + case (one_edge_counter_MW) + 2'd0:begin buf3_0[7:0] <= p3_MW; buf3_1[7:0] <= p2_MW; + buf3_2[7:0] <= p1_MW; buf3_3[7:0] <= p0_MW; end + 2'd1:begin buf3_0[15:8] <= p3_MW; buf3_1[15:8] <= p2_MW; + buf3_2[15:8] <= p1_MW; buf3_3[15:8] <= p0_MW; end + 2'd2:begin buf3_0[23:16] <= p3_MW; buf3_1[23:16] <= p2_MW; + buf3_2[23:16] <= p1_MW; buf3_3[23:16] <= p0_MW; end + 2'd3:begin buf3_0[31:24] <= p3_MW; buf3_1[31:24] <= p2_MW; + buf3_2[31:24] <= p1_MW; buf3_3[31:24] <= p0_MW; end + endcase + else //"q":11,25,35,43 + case (one_edge_counter_MW) + 2'd0:begin buf3_0[7:0] <= q0_MW; buf3_1[7:0] <= q1_MW; + buf3_2[7:0] <= q2_MW; buf3_3[7:0] <= q3_MW; end + 2'd1:begin buf3_0[15:8] <= q0_MW; buf3_1[15:8] <= q1_MW; + buf3_2[15:8] <= q2_MW; buf3_3[15:8] <= q3_MW; end + 2'd2:begin buf3_0[23:16] <= q0_MW; buf3_1[23:16] <= q1_MW; + buf3_2[23:16] <= q2_MW; buf3_3[23:16] <= q3_MW; end + 2'd3:begin buf3_0[31:24] <= q0_MW; buf3_1[31:24] <= q1_MW; + buf3_2[31:24] <= q2_MW; buf3_3[31:24] <= q3_MW; end + endcase + end + //------------------------------------------------------ + //T0:always updated after transpose,always "p" position + //------------------------------------------------------ + wire t0_transpose; //t0 updated after transpose + assign t0_transpose = ( + DF_edge_counter_MW == 6'd4 || DF_edge_counter_MW == 6'd8 || DF_edge_counter_MW == 6'd12 || DF_edge_counter_MW == 6'd36 || + DF_edge_counter_MW == 6'd44 || DF_edge_counter_MW == 6'd15 || DF_edge_counter_MW == 6'd20 || DF_edge_counter_MW == 6'd24 || + DF_edge_counter_MW == 6'd28 || DF_edge_counter_MW == 6'd31 || DF_edge_counter_MW == 6'd39 || DF_edge_counter_MW == 6'd47); + + always @ (posedge gclk_DF or negedge reset_n) + if (reset_n == 1'b0) + begin + t0_0 <= 0; t0_1 <= 0; t0_2 <= 0; t0_3 <= 0; + end + //always transpose update for "p" position + else if (t0_transpose) + case (one_edge_counter_MW) + 2'd0:begin t0_0[7:0] <= p3_MW; t0_1[7:0] <= p2_MW; + t0_2[7:0] <= p1_MW; t0_3[7:0] <= p0_MW; end + 2'd1:begin t0_0[15:8] <= p3_MW; t0_1[15:8] <= p2_MW; + t0_2[15:8] <= p1_MW; t0_3[15:8] <= p0_MW; end + 2'd2:begin t0_0[23:16] <= p3_MW; t0_1[23:16] <= p2_MW; + t0_2[23:16] <= p1_MW; t0_3[23:16] <= p0_MW; end + 2'd3:begin t0_0[31:24] <= p3_MW; t0_1[31:24] <= p2_MW; + t0_2[31:24] <= p1_MW; t0_3[31:24] <= p0_MW; end + endcase + //------------------------------------------------------ + //T1:always updated after transpose + //------------------------------------------------------ + wire t1_transpose; //t1 updated after transpose + wire t1_transpose_q; //t1 transpose and t1 stores "q" position pixels + assign t1_transpose = ( + DF_edge_counter_MW == 6'd13 || DF_edge_counter_MW == 6'd37 || DF_edge_counter_MW == 6'd45 || DF_edge_counter_MW == 6'd9 || + DF_edge_counter_MW == 6'd21 || DF_edge_counter_MW == 6'd25 || DF_edge_counter_MW == 6'd29 || DF_edge_counter_MW == 6'd31 || + DF_edge_counter_MW == 6'd39 || DF_edge_counter_MW == 6'd47); + + assign t1_transpose_q = (DF_edge_counter_MW == 6'd31 || DF_edge_counter_MW == 6'd39 || + DF_edge_counter_MW == 6'd47); + always @ (posedge gclk_DF or negedge reset_n) + if (reset_n == 1'b0) + begin + t1_0 <= 0; t1_1 <= 0; t1_2 <= 0; t1_3 <= 0; + end + else if (t1_transpose && !t1_transpose_q) //t1 transpose "p" + case (one_edge_counter_MW) + 2'd0:begin t1_0[7:0] <= p3_MW; t1_1[7:0] <= p2_MW; + t1_2[7:0] <= p1_MW; t1_3[7:0] <= p0_MW; end + 2'd1:begin t1_0[15:8] <= p3_MW; t1_1[15:8] <= p2_MW; + t1_2[15:8] <= p1_MW; t1_3[15:8] <= p0_MW; end + 2'd2:begin t1_0[23:16] <= p3_MW; t1_1[23:16] <= p2_MW; + t1_2[23:16] <= p1_MW; t1_3[23:16] <= p0_MW; end + 2'd3:begin t1_0[31:24] <= p3_MW; t1_1[31:24] <= p2_MW; + t1_2[31:24] <= p1_MW; t1_3[31:24] <= p0_MW; end + endcase + else if (t1_transpose) //t1 transpose "q" + case (one_edge_counter_MW) + 2'd0:begin t1_0[7:0] <= q0_MW; t1_1[7:0] <= q1_MW; + t1_2[7:0] <= q2_MW; t1_3[7:0] <= q3_MW; end + 2'd1:begin t1_0[15:8] <= q0_MW; t1_1[15:8] <= q1_MW; + t1_2[15:8] <= q2_MW; t1_3[15:8] <= q3_MW; end + 2'd2:begin t1_0[23:16] <= q0_MW; t1_1[23:16] <= q1_MW; + t1_2[23:16] <= q2_MW; t1_3[23:16] <= q3_MW; end + 2'd3:begin t1_0[31:24] <= q0_MW; t1_1[31:24] <= q1_MW; + t1_2[31:24] <= q2_MW; t1_3[31:24] <= q3_MW; end + endcase + //-------------------------------------------------------------------- + //T2:only used after filter edge 18/34/42 to update mbAddrB of left MB + //-------------------------------------------------------------------- + wire t2_wr; + assign t2_wr = ((mb_num_h_DF != 0 && mb_num_v_DF != 4'd8) && + (DF_edge_counter_MW == 6'd18 || DF_edge_counter_MW == 6'd34 || DF_edge_counter_MW == 6'd42)); + always @ (posedge gclk_DF or negedge reset_n) + if (reset_n == 1'b0) + begin + t2_0 <= 0; t2_1 <= 0; t2_2 <= 0; t2_3 <= 0; + end + else if (t2_wr) + case (one_edge_counter_MW) + 2'd0:begin t2_0[7:0] <= p3_MW; t2_1[7:0] <= p2_MW; + t2_2[7:0] <= p1_MW; t2_3[7:0] <= p0_MW; end + 2'd1:begin t2_0[15:8] <= p3_MW; t2_1[15:8] <= p2_MW; + t2_2[15:8] <= p1_MW; t2_3[15:8] <= p0_MW; end + 2'd2:begin t2_0[23:16] <= p3_MW; t2_1[23:16] <= p2_MW; + t2_2[23:16] <= p1_MW; t2_3[23:16] <= p0_MW; end + 2'd3:begin t2_0[31:24] <= p3_MW; t2_1[31:24] <= p2_MW; + t2_2[31:24] <= p1_MW; t2_3[31:24] <= p0_MW; end + endcase +endmodule + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/DF_top.v b/demo_chip_rtl/rtl/nova/tags/Start/src/DF_top.v new file mode 100644 index 0000000..bae31b1 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/DF_top.v @@ -0,0 +1,205 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : DF_top.v +// Generated : Dec 30, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Top module of deblocking filter +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module DF_top (clk,reset_n,gclk_DF,gclk_end_of_MB_DEC,gclk_DF_mbAddrA_RF,gclk_DF_mbAddrB_RAM, + end_of_BS_DEC,disable_DF,mb_num_h,mb_num_v, + bs_V0,bs_V1,bs_V2,bs_V3,bs_H0,bs_H1,bs_H2,bs_H3, + QPy,QPc,slice_alpha_c0_offset_div2,slice_beta_offset_div2, + blk4x4_sum_counter,blk4x4_rec_counter_2_raster_order,rec_DF_RAM_dout, + blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out, + + DF_duration,end_of_MB_DF,DF_edge_counter_MR,one_edge_counter_MR, + DF_mbAddrA_RF_rd,DF_mbAddrA_RF_wr,DF_mbAddrB_RAM_rd,DF_mbAddrB_RAM_wr, + dis_frame_RAM_wr,dis_frame_RAM_wr_addr,dis_frame_RAM_din); + input clk; + input gclk_DF; + input gclk_end_of_MB_DEC; + input gclk_DF_mbAddrA_RF; + input gclk_DF_mbAddrB_RAM; + input reset_n; + input end_of_BS_DEC; + input disable_DF; + input [3:0] mb_num_h; + input [3:0] mb_num_v; + input [11:0] bs_V0,bs_V1,bs_V2,bs_V3; + input [11:0] bs_H0,bs_H1,bs_H2,bs_H3; + input [5:0] QPy,QPc; + input [3:0] slice_alpha_c0_offset_div2; + input [3:0] slice_beta_offset_div2; + input [31:0] rec_DF_RAM_dout; + input [2:0] blk4x4_sum_counter; + input [4:0] blk4x4_rec_counter_2_raster_order; + input [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out; + + output DF_duration; + output end_of_MB_DF; + output [5:0] DF_edge_counter_MR; + output [1:0] one_edge_counter_MR; + output DF_mbAddrA_RF_rd,DF_mbAddrA_RF_wr; + output DF_mbAddrB_RAM_rd,DF_mbAddrB_RAM_wr; + output dis_frame_RAM_wr; + output [13:0] dis_frame_RAM_wr_addr; + output [31:0] dis_frame_RAM_din; + + wire end_of_MB_DF; + wire end_of_lastMB_DF; + wire [3:0] mb_num_h_DF; + wire [3:0] mb_num_v_DF; + wire [5:0] DF_edge_counter_MR,DF_edge_counter_MW; + wire [1:0] one_edge_counter_MR,one_edge_counter_MW; + wire [2:0] bs_curr_MR,bs_curr_MW; + wire [7:0] q0_MW,q1_MW,q2_MW,q3_MW; + wire [7:0] p0_MW,p1_MW,p2_MW,p3_MW; + wire [31:0] buf0_0,buf0_1,buf0_2,buf0_3; + wire [31:0] buf1_0,buf1_1,buf1_2,buf1_3; + wire [31:0] buf2_0,buf2_1,buf2_2,buf2_3; + wire [31:0] buf3_0,buf3_1,buf3_2,buf3_3; + wire [31:0] t0_0,t0_1,t0_2,t0_3; + wire [31:0] t1_0,t1_1,t1_2,t1_3; + wire [31:0] t2_0,t2_1,t2_2,t2_3; + wire DF_mbAddrA_RF_rd; + wire DF_mbAddrA_RF_wr; + wire [4:0] DF_mbAddrA_RF_rd_addr; + wire [4:0] DF_mbAddrA_RF_wr_addr; + wire [31:0] DF_mbAddrA_RF_din; + wire [31:0] DF_mbAddrA_RF_dout; + wire DF_mbAddrB_RAM_rd; + wire DF_mbAddrB_RAM_wr; + wire [8:0] DF_mbAddrB_RAM_addr; + wire [31:0] DF_mbAddrB_RAM_din; + wire [31:0] DF_mbAddrB_RAM_dout; + + DF_pipeline DF_pipeline ( + .clk(clk), + .gclk_DF(gclk_DF), + .gclk_end_of_MB_DEC(gclk_end_of_MB_DEC), + .reset_n(reset_n), + .disable_DF(disable_DF), + .end_of_BS_DEC(end_of_BS_DEC), + .end_of_MB_DF(end_of_MB_DF), + .end_of_lastMB_DF(end_of_lastMB_DF), + .bs_V0(bs_V0),.bs_V1(bs_V1),.bs_V2(bs_V2),.bs_V3(bs_V3), + .bs_H0(bs_H0),.bs_H1(bs_H1),.bs_H2(bs_H2),.bs_H3(bs_H3), + .QPy(QPy), + .QPc(QPc), + .slice_alpha_c0_offset_div2(slice_alpha_c0_offset_div2), + .slice_beta_offset_div2(slice_beta_offset_div2), + .DF_mbAddrA_RF_dout(DF_mbAddrA_RF_dout), + .DF_mbAddrB_RAM_dout(DF_mbAddrB_RAM_dout), + .rec_DF_RAM_dout(rec_DF_RAM_dout), + .buf0_0(buf0_0),.buf0_1(buf0_1),.buf0_2(buf0_2),.buf0_3(buf0_3), + .buf1_0(buf1_0),.buf1_1(buf1_1),.buf1_2(buf1_2),.buf1_3(buf1_3), + .buf2_0(buf2_0),.buf2_1(buf2_1),.buf2_2(buf2_2),.buf2_3(buf2_3), + .buf3_0(buf3_0),.buf3_1(buf3_1),.buf3_2(buf3_2),.buf3_3(buf3_3), + + .DF_duration(DF_duration), + .DF_edge_counter_MR(DF_edge_counter_MR), + .DF_edge_counter_MW(DF_edge_counter_MW), + .one_edge_counter_MR(one_edge_counter_MR), + .one_edge_counter_MW(one_edge_counter_MW), + .bs_curr_MR(bs_curr_MR), + .bs_curr_MW(bs_curr_MW), + .q0_MW(q0_MW),.q1_MW(q1_MW),.q2_MW(q2_MW),.q3_MW(q3_MW), + .p0_MW(p0_MW),.p1_MW(p1_MW),.p2_MW(p2_MW),.p3_MW(p3_MW) + ); + DF_reg_ctrl DF_reg_ctrl ( + .gclk_DF(gclk_DF), + .reset_n(reset_n), + .DF_edge_counter_MW(DF_edge_counter_MW), + .one_edge_counter_MW(one_edge_counter_MW), + .mb_num_h_DF(mb_num_h_DF), + .mb_num_v_DF(mb_num_v_DF), + + .q0_MW(q0_MW),.q1_MW(q1_MW),.q2_MW(q2_MW),.q3_MW(q3_MW), + .p0_MW(p0_MW),.p1_MW(p1_MW),.p2_MW(p2_MW),.p3_MW(p3_MW), + .buf0_0(buf0_0),.buf0_1(buf0_1),.buf0_2(buf0_2),.buf0_3(buf0_3), + .buf1_0(buf1_0),.buf1_1(buf1_1),.buf1_2(buf1_2),.buf1_3(buf1_3), + .buf2_0(buf2_0),.buf2_1(buf2_1),.buf2_2(buf2_2),.buf2_3(buf2_3), + .buf3_0(buf3_0),.buf3_1(buf3_1),.buf3_2(buf3_2),.buf3_3(buf3_3), + .t0_0(t0_0),.t0_1(t0_1),.t0_2(t0_2),.t0_3(t0_3), + .t1_0(t1_0),.t1_1(t1_1),.t1_2(t1_2),.t1_3(t1_3), + .t2_0(t2_0),.t2_1(t2_1),.t2_2(t2_2),.t2_3(t2_3) + ); + + DF_mem_ctrl DF_mem_ctrl ( + .clk(clk), + .reset_n(reset_n), + .gclk_end_of_MB_DEC(gclk_end_of_MB_DEC), + .disable_DF(disable_DF), + .mb_num_h(mb_num_h), + .mb_num_v(mb_num_v), + .bs_curr_MR(bs_curr_MR), + .bs_curr_MW(bs_curr_MW), + .blk4x4_sum_counter(blk4x4_sum_counter), + .blk4x4_rec_counter_2_raster_order(blk4x4_rec_counter_2_raster_order), + .DF_edge_counter_MR(DF_edge_counter_MR), + .DF_edge_counter_MW(DF_edge_counter_MW), + .one_edge_counter_MR(one_edge_counter_MR), + .one_edge_counter_MW(one_edge_counter_MW), + .blk4x4_sum_PE0_out(blk4x4_sum_PE0_out), + .blk4x4_sum_PE1_out(blk4x4_sum_PE1_out), + .blk4x4_sum_PE2_out(blk4x4_sum_PE2_out), + .blk4x4_sum_PE3_out(blk4x4_sum_PE3_out), + .q0_MW(q0_MW),.q1_MW(q1_MW),.q2_MW(q2_MW),.q3_MW(q3_MW), + .p0_MW(p0_MW),.p1_MW(p1_MW),.p2_MW(p2_MW),.p3_MW(p3_MW), + .buf0_0(buf0_0),.buf0_1(buf0_1),.buf0_2(buf0_2),.buf0_3(buf0_3), + .buf2_0(buf2_0),.buf2_1(buf2_1),.buf2_2(buf2_2),.buf2_3(buf2_3), + .buf3_0(buf3_0),.buf3_1(buf3_1),.buf3_2(buf3_2),.buf3_3(buf3_3), + .t0_0(t0_0),.t0_1(t0_1),.t0_2(t0_2),.t0_3(t0_3), + .t1_0(t1_0),.t1_1(t1_1),.t1_2(t1_2),.t1_3(t1_3), + .t2_0(t2_0),.t2_1(t2_1),.t2_2(t2_2),.t2_3(t2_3), + + .mb_num_h_DF(mb_num_h_DF), + .mb_num_v_DF(mb_num_v_DF), + .end_of_MB_DF(end_of_MB_DF), + .end_of_lastMB_DF(end_of_lastMB_DF), + .DF_mbAddrA_RF_rd(DF_mbAddrA_RF_rd), + .DF_mbAddrA_RF_wr(DF_mbAddrA_RF_wr), + .DF_mbAddrA_RF_rd_addr(DF_mbAddrA_RF_rd_addr), + .DF_mbAddrA_RF_wr_addr(DF_mbAddrA_RF_wr_addr), + .DF_mbAddrA_RF_din(DF_mbAddrA_RF_din), + .DF_mbAddrB_RAM_rd(DF_mbAddrB_RAM_rd), + .DF_mbAddrB_RAM_wr(DF_mbAddrB_RAM_wr), + .DF_mbAddrB_RAM_addr(DF_mbAddrB_RAM_addr), + .DF_mbAddrB_RAM_din(DF_mbAddrB_RAM_din), + .dis_frame_RAM_wr(dis_frame_RAM_wr), + .dis_frame_RAM_wr_addr(dis_frame_RAM_wr_addr), + .dis_frame_RAM_din(dis_frame_RAM_din) + ); + ram_sync_1r_sync_1w # (`DF_mbAddrA_RAM_data_width,`DF_mbAddrA_RAM_data_depth) + DF_mbAddrA_RAM ( + .clk(gclk_DF_mbAddrA_RF), + .rst_n(reset_n), + .wr_n(~DF_mbAddrA_RF_wr), + .rd_n(~DF_mbAddrA_RF_rd), + .wr_addr(DF_mbAddrA_RF_wr_addr), + .rd_addr(DF_mbAddrA_RF_rd_addr), + .data_in(DF_mbAddrA_RF_din), + .data_out(DF_mbAddrA_RF_dout) + ); + ram_sync_1r_sync_1w # (`DF_mbAddrB_RAM_data_width,`DF_mbAddrB_RAM_data_depth) + DF_mbAddrB_RAM ( + .clk(gclk_DF_mbAddrB_RAM), + .rst_n(reset_n), + .wr_n(~DF_mbAddrB_RAM_wr), + .rd_n(~DF_mbAddrB_RAM_rd), + .wr_addr(DF_mbAddrB_RAM_addr), + .rd_addr(DF_mbAddrB_RAM_addr), + .data_in(DF_mbAddrB_RAM_din), + .data_out(DF_mbAddrB_RAM_dout) + ); +endmodule \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/IQIT.v b/demo_chip_rtl/rtl/nova/tags/Start/src/IQIT.v new file mode 100644 index 0000000..e6c3334 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/IQIT.v @@ -0,0 +1,850 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : IQIT.v +// Generated : June 18, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Decoding the residual information +// 1.The res_mb_bypass | DConly | allzero signals should be decoded first +// 2.For DC coefficients,IDCT --> rescale +// 3.For AC coefficients,rescale --> IDCT --> rounding +// 4.coeffLevel:zig-zag order +// OneD_output,TwoD_output,DC_output,rescale_output,rounding_output:raster-scan order +// 5.Input coeffLevel_ext_0 ~ 15 are 2's complement,but with zig-zag order +//------------------------------------------------------------------------------------------------- +// Revise log +// 1.March 27,2006 +// DC_output: 0 ~ 15:for luma DC, 0 ~ 3:for Chroma Cb DC, 4 ~ 7:for Chroma Cr DC +// 2.March 28,2006 +// 1)For Intra16x16ACLevel and chroma AC,the first coeff of IDCT is DC value, the following coeffLevel_ext_0 ~ 14 should be moved backward 1 space and coeffLevel_ext_15 is abandoned +// 2)There are some blocks which have zero DC coeff but non-zero AC coeff. Additional signals as res_LumaDCBlk_IsZero,res_ChromaDCBlk_Cb_IsZero,res_ChromaDCBlk_Cr_IsZero are added to deal with such special case +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module IQIT (clk,reset_n,TotalCoeff,blk4x4_rec_counter, + gclk_1D,gclk_2D,gclk_rescale,gclk_rounding, + residual_state,cavlc_decoder_state, + end_of_one_residual_block,end_of_NonZeroCoeff_CAVLC, + QPy,QPc,i4x4_CbCr, + coeffLevel_ext_0, coeffLevel_ext_1, coeffLevel_ext_2, coeffLevel_ext_3, + coeffLevel_ext_4, coeffLevel_ext_5, coeffLevel_ext_6, coeffLevel_ext_7, + coeffLevel_ext_8, coeffLevel_ext_9, coeffLevel_ext_10,coeffLevel_ext_11, + coeffLevel_ext_12,coeffLevel_ext_13,coeffLevel_ext_14,coeffLevel_ext_15, + + OneD_counter,TwoD_counter,rescale_counter,rounding_counter, + curr_DC_IsZero,curr_DC_scaled, + rounding_output_0,rounding_output_1,rounding_output_2,rounding_output_3, + rounding_output_4,rounding_output_5,rounding_output_6,rounding_output_7, + rounding_output_8,rounding_output_9,rounding_output_10,rounding_output_11, + rounding_output_12,rounding_output_13,rounding_output_14,rounding_output_15, + end_of_ACBlk4x4_IQIT,end_of_DCBlk_IQIT + ); + input clk,reset_n; + input [4:0] TotalCoeff; + input [4:0] blk4x4_rec_counter; + input gclk_1D; + input gclk_2D; + input gclk_rescale; + input gclk_rounding; + input [3:0] residual_state; + input [3:0] cavlc_decoder_state; + input end_of_one_residual_block; + input end_of_NonZeroCoeff_CAVLC; + input [5:0] QPy; + input [5:0] QPc; + input [1:0] i4x4_CbCr; + input [15:0] coeffLevel_ext_0, coeffLevel_ext_1, coeffLevel_ext_2, coeffLevel_ext_3; + input [15:0] coeffLevel_ext_4, coeffLevel_ext_5, coeffLevel_ext_6, coeffLevel_ext_7; + input [15:0] coeffLevel_ext_8, coeffLevel_ext_9, coeffLevel_ext_10,coeffLevel_ext_11; + input [15:0] coeffLevel_ext_12,coeffLevel_ext_13,coeffLevel_ext_14,coeffLevel_ext_15; + + + output [2:0] OneD_counter; + output [2:0] TwoD_counter; + output [2:0] rescale_counter; + output [2:0] rounding_counter; + output curr_DC_IsZero; + output [8:0] curr_DC_scaled; + output [8:0] rounding_output_0, rounding_output_1, rounding_output_2, rounding_output_3; + output [8:0] rounding_output_4, rounding_output_5, rounding_output_6, rounding_output_7; + output [8:0] rounding_output_8, rounding_output_9, rounding_output_10,rounding_output_11; + output [8:0] rounding_output_12,rounding_output_13,rounding_output_14,rounding_output_15; + output end_of_ACBlk4x4_IQIT; //end of IQIT of one blk4x4 AC + output end_of_DCBlk_IQIT; //end of IQIT of one blk4x4/blk2x2 DC + + reg [8:0] rounding_output_0, rounding_output_1, rounding_output_2, rounding_output_3; + reg [8:0] rounding_output_4, rounding_output_5, rounding_output_6, rounding_output_7; + reg [8:0] rounding_output_8, rounding_output_9, rounding_output_10,rounding_output_11; + reg [8:0] rounding_output_12,rounding_output_13,rounding_output_14,rounding_output_15; + + reg [2:0] OneD_counter; + reg [2:0] TwoD_counter; + reg [2:0] rescale_counter; + reg [2:0] rounding_counter; + reg [4:0] LevelScale_DC; + reg [4:0] LevelScale_AC [3:0]; + reg [15:0] butterfly_D0,butterfly_D1,butterfly_D2,butterfly_D3; + reg [15:0] mult0_a,mult1_a,mult2_a,mult3_a; + reg IsLeftShift; + reg [3:0] shift_len; + reg [15:0] OneD_output [15:0]; + reg [15:0] TwoD_output [3:0]; + reg [15:0] rescale_output [3:0]; + reg [15:0] DC_output [15:0]; + + wire IsHadamard; + wire [5:0] QP; + wire [2:0] QPmod6; + wire [3:0] QPdiv6; + wire [15:0] butterfly_F0,butterfly_F1,butterfly_F2,butterfly_F3; + wire [4:0] LevelScale [3:0]; + wire [15:0] product0,product1,product2,product3; + wire [15:0] shift_output0,shift_output1,shift_output2,shift_output3; + wire [15:0] before_rounding0,before_rounding1,before_rounding2,before_rounding3; + wire [9:0] rounding_sum0,rounding_sum1,rounding_sum2,rounding_sum3; + + //----------------------------------------------------------------------------------- + // Zero-block-aware decoding + //----------------------------------------------------------------------------------- + //Whether DC block is zero + reg res_LumaDCBlk_IsZero; + reg res_ChromaDCBlk_Cb_IsZero; + reg res_ChromaDCBlk_Cr_IsZero; + + always @ (posedge clk) + if (reset_n == 1'b0) + begin + res_LumaDCBlk_IsZero <= 1'b0; + res_ChromaDCBlk_Cb_IsZero <= 1'b0; + res_ChromaDCBlk_Cr_IsZero <= 1'b0; + end + else if (cavlc_decoder_state == `NumCoeffTrailingOnes_LUT) + begin + if (residual_state == `Intra16x16DCLevel_s) + res_LumaDCBlk_IsZero <= (TotalCoeff == 0)? 1'b1:1'b0; + if (residual_state == `ChromaDCLevel_Cb_s) + res_ChromaDCBlk_Cb_IsZero <= (TotalCoeff == 0)? 1'b1:1'b0; + if (residual_state == `ChromaDCLevel_Cr_s) + res_ChromaDCBlk_Cr_IsZero <= (TotalCoeff == 0)? 1'b1:1'b0; + end + + //Whether current DC from DC_output[15:0] is zero + //If whole DC block are all zeros or current single DC is zero,curr_DC is assigned 0 + //If current blk4x4 doesn't need DC (e.g. LumaLevel_s), curr_DC is also assigned 0 + reg [15:0] curr_DC; + reg [15:0] curr_DC_reg; + always @ (posedge clk) + if (reset_n == 1'b0) + curr_DC_reg <= 0; + else + curr_DC_reg <= curr_DC; + + always @ (residual_state or TotalCoeff or blk4x4_rec_counter or end_of_one_residual_block + or res_LumaDCBlk_IsZero or res_ChromaDCBlk_Cb_IsZero or res_ChromaDCBlk_Cr_IsZero or curr_DC_reg + or DC_output[0] or DC_output[1] or DC_output[2] or DC_output[3] + or DC_output[4] or DC_output[5] or DC_output[6] or DC_output[7] + or DC_output[8] or DC_output[9] or DC_output[10] or DC_output[11] + or DC_output[12] or DC_output[13] or DC_output[14] or DC_output[15]) + if (residual_state == `Intra16x16ACLevel_0_s || (residual_state == `Intra16x16ACLevel_s && (end_of_one_residual_block && TotalCoeff == 0))) + begin + if (res_LumaDCBlk_IsZero == 1) + curr_DC <= 0; + else + case (blk4x4_rec_counter) + 0 :curr_DC <= DC_output[0]; 1 :curr_DC <= DC_output[1]; + 2 :curr_DC <= DC_output[2]; 3 :curr_DC <= DC_output[3]; + 4 :curr_DC <= DC_output[4]; 5 :curr_DC <= DC_output[5]; + 6 :curr_DC <= DC_output[6]; 7 :curr_DC <= DC_output[7]; + 8 :curr_DC <= DC_output[8]; 9 :curr_DC <= DC_output[9]; + 10:curr_DC <= DC_output[10];11:curr_DC <= DC_output[11]; + 12:curr_DC <= DC_output[12];13:curr_DC <= DC_output[13]; + 14:curr_DC <= DC_output[14];15:curr_DC <= DC_output[15]; + default:curr_DC <= curr_DC_reg; + endcase + end + else if (residual_state == `ChromaACLevel_0_s || ((residual_state == `ChromaACLevel_Cb_s + || residual_state == `ChromaACLevel_Cr_s) && (end_of_one_residual_block && TotalCoeff == 0))) + begin + if (blk4x4_rec_counter < 20) //Cb + begin + if (res_ChromaDCBlk_Cb_IsZero == 1'b1) + curr_DC <= 0; + else + case (blk4x4_rec_counter) + 16:curr_DC <= DC_output[0];17:curr_DC <= DC_output[1]; + 18:curr_DC <= DC_output[2];19:curr_DC <= DC_output[3]; + default:curr_DC <= curr_DC_reg; + endcase + end + else //Cr + begin + if (res_ChromaDCBlk_Cr_IsZero == 1'b1) + curr_DC <= 0; + else + case (blk4x4_rec_counter) + 20:curr_DC <= DC_output[4];21:curr_DC <= DC_output[5]; + 22:curr_DC <= DC_output[6];23:curr_DC <= DC_output[7]; + default:curr_DC <= curr_DC_reg; + endcase + end + end + else + curr_DC <= curr_DC_reg; + + wire curr_DC_IsZero; + assign curr_DC_IsZero = (curr_DC == 0); + + wire [15:0] curr_DC_tmp; + wire [8:0] curr_DC_scaled; + assign curr_DC_tmp = curr_DC + 32; + assign curr_DC_scaled = curr_DC_tmp[14:6]; + + //----------------------------------------------------------------------------------- + //residual type indicator + //----------------------------------------------------------------------------------- + wire res_DC; + wire res_AC; + wire res_luma; + + assign res_DC = (residual_state == `Intra16x16DCLevel_s || residual_state == `ChromaDCLevel_Cb_s || residual_state == `ChromaDCLevel_Cr_s); + assign res_AC = (residual_state != `rst_residual && !res_DC); + assign res_luma = (residual_state == `Intra16x16DCLevel_s || residual_state == `Intra16x16ACLevel_s || + residual_state == `Intra16x16ACLevel_0_s || residual_state == `LumaLevel_s || residual_state == `LumaLevel_0_s); + + //1.OneD_counter:control the step of 1D in IDCT,4 cycles + // For ChromaDC IDCT,we combine the original 2x2 2D IDCT into a 4x4-like 1D IDCT + // ChromaDC: 1 cycle + // Others : 4 cycles + always @ (posedge gclk_1D or negedge reset_n) + if (reset_n == 0) + OneD_counter <= 0; + else if (OneD_counter == 0) + OneD_counter <= (residual_state == `ChromaDCLevel_Cb_s || residual_state == `ChromaDCLevel_Cr_s)? 3'b001:3'b100; + else + OneD_counter <= OneD_counter - 1; + + //2.TwoD_counter:control the step of 2D in IDCT,4 cycles + // ChromaDC: 0 cycle (All ChromDC transform done at 1D-DCT) + // Others : 4 cycles + always @ (posedge gclk_2D or negedge reset_n) + if (reset_n == 0) + TwoD_counter <= 0; + else + TwoD_counter <= (TwoD_counter == 0)? 3'b100:TwoD_counter - 1; + + //3.rescale_counter:control the step of rescale + // ChromaDC: 1 cycle (only 4 ChromDC coefficients) + // Others : 4 cycles(16 coefficients) + always @ (posedge gclk_rescale or negedge reset_n) + if (reset_n == 0) + rescale_counter <= 0; + else if (rescale_counter != 0) + rescale_counter <= rescale_counter - 1; + else if (end_of_NonZeroCoeff_CAVLC == 1'b1) // AC + rescale_counter <= 3'b100; + else if (OneD_counter == 3'b001 && (residual_state == `ChromaDCLevel_Cb_s || residual_state == `ChromaDCLevel_Cr_s)) //ChromaDC + rescale_counter <= 3'b001; + else if (TwoD_counter == 3'b100 && residual_state == `Intra16x16DCLevel_s) //LumaDC + rescale_counter <= 3'b100; + + //4.rounding_counter + always @ (posedge gclk_rounding or negedge reset_n) + if (reset_n == 0) + rounding_counter <= 0; + else + rounding_counter <= (rounding_counter == 0)? 3'b100:(rounding_counter - 1); + + //----------------------------------------------------------------------------------- + //rescale + //----------------------------------------------------------------------------------- + + //butterfly IDCT + //1D DC:from coeffLevel + // Intra16x16 :(0,0) :from DC_output + // others:from rescale_output + // ChromaAC_Cb:(0,0) :from DC_output + // others:from rescale_output + // ChromaAC_Cr:(0,0) :from DC_output + // others:from rescale_output + // others :from rescale_output + // + //2D All from OneD_output + assign IsHadamard = (res_DC == 1'b1 && (OneD_counter != 0 || TwoD_counter != 0))? 1'b1:1'b0; + + butterfly butterfly ( + .D0(butterfly_D0), + .D1(butterfly_D1), + .D2(butterfly_D2), + .D3(butterfly_D3), + .F0(butterfly_F0), + .F1(butterfly_F1), + .F2(butterfly_F2), + .F3(butterfly_F3), + .IsHadamard(IsHadamard) + ); + + always @ (i4x4_CbCr or OneD_counter or TwoD_counter or blk4x4_rec_counter[3:0] or residual_state or res_AC + or res_LumaDCBlk_IsZero or res_ChromaDCBlk_Cb_IsZero or res_ChromaDCBlk_Cr_IsZero + or DC_output[0] or DC_output[1] or DC_output[2] or DC_output[3] + or DC_output[4] or DC_output[5] or DC_output[6] or DC_output[7] + or DC_output[8] or DC_output[9] or DC_output[10] or DC_output[11] + or DC_output[12] or DC_output[13] or DC_output[14] or DC_output[15] + or coeffLevel_ext_0 or coeffLevel_ext_1 or coeffLevel_ext_2 or coeffLevel_ext_3 + or coeffLevel_ext_4 or coeffLevel_ext_5 or coeffLevel_ext_6 or coeffLevel_ext_7 + or coeffLevel_ext_8 or coeffLevel_ext_9 or coeffLevel_ext_10 or coeffLevel_ext_11 + or coeffLevel_ext_12 or coeffLevel_ext_13 or coeffLevel_ext_14 or coeffLevel_ext_15 + or OneD_output[0] or OneD_output[1] or OneD_output[2] or OneD_output[3] + or OneD_output[4] or OneD_output[5] or OneD_output[6] or OneD_output[7] + or OneD_output[8] or OneD_output[9] or OneD_output[10] or OneD_output[11] + or OneD_output[12] or OneD_output[13] or OneD_output[14] or OneD_output[15] + or rescale_output[0] or rescale_output[1] or rescale_output[2] or rescale_output[3]) + if (OneD_counter != 0) + case (OneD_counter) + 3'b100: + begin + case (residual_state) + `Intra16x16ACLevel_s: + if (res_LumaDCBlk_IsZero == 1'b1) + butterfly_D0 <= 0; + else + case (blk4x4_rec_counter[3:0]) + 4'b0000: butterfly_D0 <= DC_output[0]; + 4'b0001: butterfly_D0 <= DC_output[1]; + 4'b0010: butterfly_D0 <= DC_output[2]; + 4'b0011: butterfly_D0 <= DC_output[3]; + 4'b0100: butterfly_D0 <= DC_output[4]; + 4'b0101: butterfly_D0 <= DC_output[5]; + 4'b0110: butterfly_D0 <= DC_output[6]; + 4'b0111: butterfly_D0 <= DC_output[7]; + 4'b1000: butterfly_D0 <= DC_output[8]; + 4'b1001: butterfly_D0 <= DC_output[9]; + 4'b1010: butterfly_D0 <= DC_output[10]; + 4'b1011: butterfly_D0 <= DC_output[11]; + 4'b1100: butterfly_D0 <= DC_output[12]; + 4'b1101: butterfly_D0 <= DC_output[13]; + 4'b1110: butterfly_D0 <= DC_output[14]; + 4'b1111: butterfly_D0 <= DC_output[15]; + endcase + `ChromaACLevel_Cb_s: + if(res_ChromaDCBlk_Cb_IsZero) + butterfly_D0 <= 0; + else + case (i4x4_CbCr) + 2'b00:butterfly_D0 <= DC_output[0]; + 2'b01:butterfly_D0 <= DC_output[1]; + 2'b10:butterfly_D0 <= DC_output[2]; + 2'b11:butterfly_D0 <= DC_output[3]; + endcase + `ChromaACLevel_Cr_s: + if(res_ChromaDCBlk_Cr_IsZero) + butterfly_D0 <= 0; + else + case (i4x4_CbCr) + 2'b00:butterfly_D0 <= DC_output[4]; + 2'b01:butterfly_D0 <= DC_output[5]; + 2'b10:butterfly_D0 <= DC_output[6]; + 2'b11:butterfly_D0 <= DC_output[7]; + endcase + default: //luma DC,chroma DC,luma4x4 AC + butterfly_D0 <= (res_AC == 1'b1)? rescale_output[0]:coeffLevel_ext_0; + endcase + butterfly_D1 <= (res_AC == 1'b1)? rescale_output[1]:coeffLevel_ext_1; + butterfly_D2 <= (res_AC == 1'b1)? rescale_output[2]:coeffLevel_ext_5; + butterfly_D3 <= (res_AC == 1'b1)? rescale_output[3]:coeffLevel_ext_6; + end + 3'b011: + begin + butterfly_D0 <= (res_AC == 1'b1)? rescale_output[0]:coeffLevel_ext_2; + butterfly_D1 <= (res_AC == 1'b1)? rescale_output[1]:coeffLevel_ext_4; + butterfly_D2 <= (res_AC == 1'b1)? rescale_output[2]:coeffLevel_ext_7; + butterfly_D3 <= (res_AC == 1'b1)? rescale_output[3]:coeffLevel_ext_12; + end + 3'b010: + begin + butterfly_D0 <= (res_AC == 1'b1)? rescale_output[0]:coeffLevel_ext_3; + butterfly_D1 <= (res_AC == 1'b1)? rescale_output[1]:coeffLevel_ext_8; + butterfly_D2 <= (res_AC == 1'b1)? rescale_output[2]:coeffLevel_ext_11; + butterfly_D3 <= (res_AC == 1'b1)? rescale_output[3]:coeffLevel_ext_13; + end + 3'b001: + begin + //luma DC + if (residual_state == `Intra16x16DCLevel_s) + begin + butterfly_D0 <= coeffLevel_ext_9; butterfly_D1 <= coeffLevel_ext_10; + butterfly_D2 <= coeffLevel_ext_14; butterfly_D3 <= coeffLevel_ext_15; + end + //chroma DC + else if (residual_state == `ChromaDCLevel_Cb_s || residual_state == `ChromaDCLevel_Cr_s) + begin + butterfly_D0 <= coeffLevel_ext_0; butterfly_D1 <= coeffLevel_ext_1; + butterfly_D2 <= coeffLevel_ext_2; butterfly_D3 <= coeffLevel_ext_3; + end + //AC + else + begin + butterfly_D0 <= rescale_output[0]; butterfly_D1 <= rescale_output[1]; + butterfly_D2 <= rescale_output[2]; butterfly_D3 <= rescale_output[3]; + end + end + default: + begin + butterfly_D0 <= 0; butterfly_D1 <= 0; + butterfly_D2 <= 0; butterfly_D3 <= 0; + end + endcase + else if (TwoD_counter != 0) + case (TwoD_counter) + 3'b100: + begin + butterfly_D0 <= OneD_output[0];butterfly_D1 <= OneD_output[4]; + butterfly_D2 <= OneD_output[8];butterfly_D3 <= OneD_output[12]; + end + 3'b011: + begin + butterfly_D0 <= OneD_output[1];butterfly_D1 <= OneD_output[5]; + butterfly_D2 <= OneD_output[9];butterfly_D3 <= OneD_output[13]; + end + 3'b010: + begin + butterfly_D0 <= OneD_output[2]; butterfly_D1 <= OneD_output[6]; + butterfly_D2 <= OneD_output[10];butterfly_D3 <= OneD_output[14]; + end + 3'b001: + begin + butterfly_D0 <= OneD_output[3]; butterfly_D1 <= OneD_output[7]; + butterfly_D2 <= OneD_output[11];butterfly_D3 <= OneD_output[15]; + end + default: + begin + butterfly_D0 <= 0; butterfly_D1 <= 0; + butterfly_D2 <= 0; butterfly_D3 <= 0; + end + endcase + else + begin + butterfly_D0 <= 0; butterfly_D1 <= 0; + butterfly_D2 <= 0; butterfly_D3 <= 0; + end + + assign QP = (res_luma == 1'b1)? QPy:QPc; + mod6 mod6 ( + .qp(QP), + .mod(QPmod6) + ); + + // Specify LevelScale parameter: LevelScale_DC & LevelScale_AC + always @ (rescale_counter or res_DC or QPmod6) + if (rescale_counter != 0 && res_DC == 1'b1) + case (QPmod6) + 0:LevelScale_DC <= 10; + 1:LevelScale_DC <= 11; + 2:LevelScale_DC <= 13; + 3:LevelScale_DC <= 14; + 4:LevelScale_DC <= 16; + 5:LevelScale_DC <= 18; + default:LevelScale_DC <= 0; + endcase + else + LevelScale_DC <= 0; + + always @ (rescale_counter or res_AC or QPmod6) + if (rescale_counter != 0 && res_AC == 1'b1) + case (rescale_counter) + 3'b100,3'b010: //1 & 3 row + case (QPmod6) + 3'b000:begin LevelScale_AC[0] <= 10; LevelScale_AC[1] <= 13; LevelScale_AC[2] <= 10; LevelScale_AC[3] <= 13; end + 3'b001:begin LevelScale_AC[0] <= 11; LevelScale_AC[1] <= 14; LevelScale_AC[2] <= 11; LevelScale_AC[3] <= 14; end + 3'b010:begin LevelScale_AC[0] <= 13; LevelScale_AC[1] <= 16; LevelScale_AC[2] <= 13; LevelScale_AC[3] <= 16; end + 3'b011:begin LevelScale_AC[0] <= 14; LevelScale_AC[1] <= 18; LevelScale_AC[2] <= 14; LevelScale_AC[3] <= 18; end + 3'b100:begin LevelScale_AC[0] <= 16; LevelScale_AC[1] <= 20; LevelScale_AC[2] <= 16; LevelScale_AC[3] <= 20; end + 3'b101:begin LevelScale_AC[0] <= 18; LevelScale_AC[1] <= 23; LevelScale_AC[2] <= 18; LevelScale_AC[3] <= 23; end + default:begin LevelScale_AC[0] <= 0; LevelScale_AC[1] <= 0; LevelScale_AC[2] <= 0; LevelScale_AC[3] <= 0; end + endcase + 3'b011,3'b001: //2 & 4 row + case (QPmod6) + 3'b000:begin LevelScale_AC[0] <= 13; LevelScale_AC[1] <= 16; LevelScale_AC[2] <= 13; LevelScale_AC[3] <= 16; end + 3'b001:begin LevelScale_AC[0] <= 14; LevelScale_AC[1] <= 18; LevelScale_AC[2] <= 14; LevelScale_AC[3] <= 18; end + 3'b010:begin LevelScale_AC[0] <= 16; LevelScale_AC[1] <= 20; LevelScale_AC[2] <= 16; LevelScale_AC[3] <= 20; end + 3'b011:begin LevelScale_AC[0] <= 18; LevelScale_AC[1] <= 23; LevelScale_AC[2] <= 18; LevelScale_AC[3] <= 23; end + 3'b100:begin LevelScale_AC[0] <= 20; LevelScale_AC[1] <= 25; LevelScale_AC[2] <= 20; LevelScale_AC[3] <= 25; end + 3'b101:begin LevelScale_AC[0] <= 23; LevelScale_AC[1] <= 29; LevelScale_AC[2] <= 23; LevelScale_AC[3] <= 29; end + default:begin LevelScale_AC[0] <= 0; LevelScale_AC[1] <= 0; LevelScale_AC[2] <= 0; LevelScale_AC[3] <= 0; end + endcase + default:begin LevelScale_AC[0] <= 0; LevelScale_AC[1] <= 0; LevelScale_AC[2] <= 0; LevelScale_AC[3] <= 0; end + endcase + else + begin + LevelScale_AC[0] <= 0; LevelScale_AC[1] <= 0; + LevelScale_AC[2] <= 0; LevelScale_AC[3] <= 0; + end + + assign LevelScale[0] = (rescale_counter == 0)? 0:((res_AC == 1)? LevelScale_AC[0]:LevelScale_DC); + assign LevelScale[1] = (rescale_counter == 0)? 0:((res_AC == 1)? LevelScale_AC[1]:LevelScale_DC); + assign LevelScale[2] = (rescale_counter == 0)? 0:((res_AC == 1)? LevelScale_AC[2]:LevelScale_DC); + assign LevelScale[3] = (rescale_counter == 0)? 0:((res_AC == 1)? LevelScale_AC[3]:LevelScale_DC); + + // Specify rescale multiplier input + always @ (residual_state or res_DC or rescale_counter + or OneD_output[0] or OneD_output[1] or OneD_output[2] or OneD_output[3] + or OneD_output[4] or OneD_output[5] or OneD_output[6] or OneD_output[7] + or OneD_output[8] or OneD_output[9] or OneD_output[10] or OneD_output[11] + or OneD_output[12] or OneD_output[13] or OneD_output[14] or OneD_output[15] + or TwoD_output[0] or TwoD_output[1] or TwoD_output[2] or TwoD_output[3] + or coeffLevel_ext_0 or coeffLevel_ext_1 or coeffLevel_ext_2 or coeffLevel_ext_3 + or coeffLevel_ext_4 or coeffLevel_ext_5 or coeffLevel_ext_6 or coeffLevel_ext_7 + or coeffLevel_ext_8 or coeffLevel_ext_9 or coeffLevel_ext_10 or coeffLevel_ext_11 + or coeffLevel_ext_12 or coeffLevel_ext_13 or coeffLevel_ext_14 or coeffLevel_ext_15) + if (residual_state == `Intra16x16DCLevel_s && rescale_counter != 0) //Intra16x16DC + begin + mult0_a <= TwoD_output[0]; mult1_a <= TwoD_output[1]; + mult2_a <= TwoD_output[2]; mult3_a <= TwoD_output[3]; + end + else if (res_DC == 1'b1 && rescale_counter != 0) //ChromaDC + begin + mult0_a <= OneD_output[12]; mult1_a <= OneD_output[15]; + mult2_a <= OneD_output[13]; mult3_a <= OneD_output[14]; + end + else if (rescale_counter != 0) //AC + case (rescale_counter) + 3'b100: + begin + mult0_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_0:0; + mult1_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_1:coeffLevel_ext_0; + mult2_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_5:coeffLevel_ext_4; + mult3_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_6:coeffLevel_ext_5; + end + 3'b011: + begin + mult0_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_2:coeffLevel_ext_1; + mult1_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_4:coeffLevel_ext_3; + mult2_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_7:coeffLevel_ext_6; + mult3_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_12:coeffLevel_ext_11; + end + 3'b010: + begin + mult0_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_3:coeffLevel_ext_2; + mult1_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_8:coeffLevel_ext_7; + mult2_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_11:coeffLevel_ext_10; + mult3_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_13:coeffLevel_ext_12; + end + 3'b001: + begin + mult0_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_9:coeffLevel_ext_8; + mult1_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_10:coeffLevel_ext_9; + mult2_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_14:coeffLevel_ext_13; + mult3_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_15:coeffLevel_ext_14; + end + default: + begin + mult0_a <= 0; mult1_a <= 0; + mult2_a <= 0; mult3_a <= 0; + end + endcase + else + begin + mult0_a <= 0; mult1_a <= 0; + mult2_a <= 0; mult3_a <= 0; + end + + //rescale multiplier + assign product0 = (rescale_counter == 0)? 0:mult0_a * {1'b0,LevelScale[0]}; + assign product1 = (rescale_counter == 0)? 0:mult1_a * {1'b0,LevelScale[1]}; + assign product2 = (rescale_counter == 0)? 0:mult2_a * {1'b0,LevelScale[2]}; + assign product3 = (rescale_counter == 0)? 0:mult3_a * {1'b0,LevelScale[3]}; + + always @ (res_AC or res_luma or QPy or QPc) + if (res_AC == 1'b1) + IsLeftShift <= 1'b1; + else if (res_luma == 1'b1) + IsLeftShift <= (QPy < 12)? 1'b0:1'b1; + else + IsLeftShift <= (QPc < 6)? 1'b0:1'b1; + + div6 div6 ( + .qp(QP), + .div(QPdiv6) + ); + + always @ (residual_state or res_DC or QPdiv6) + if (residual_state == `Intra16x16DCLevel_s) //Intra16x16DC + case (QPdiv6) + 4'b0000:shift_len <= 2; + 4'b0001:shift_len <= 1; + default:shift_len <= QPdiv6 - 2; + endcase + else if (res_DC) //ChromaDC + case (QPdiv6) + 4'b0000:shift_len <= 1; + default:shift_len <= QPdiv6 - 1; + endcase + else //AC + shift_len <= QPdiv6; + + rescale_shift rescale_shift0 ( + .IsLeftShift(IsLeftShift), + .shift_input(product0), + .shift_len(shift_len), + .shift_output(shift_output0) + ); + rescale_shift rescale_shift1 ( + .IsLeftShift(IsLeftShift), + .shift_input(product1), + .shift_len(shift_len), + .shift_output(shift_output1) + ); + rescale_shift rescale_shift2 ( + .IsLeftShift(IsLeftShift), + .shift_input(product2), + .shift_len(shift_len), + .shift_output(shift_output2) + ); + rescale_shift rescale_shift3 ( + .IsLeftShift(IsLeftShift), + .shift_input(product3), + .shift_len(shift_len), + .shift_output(shift_output3) + ); + //----------------------------------------------------------------------- + //rounding + //----------------------------------------------------------------------- + assign before_rounding0 = (rounding_counter != 0)? TwoD_output[0]:0; + assign before_rounding1 = (rounding_counter != 0)? TwoD_output[1]:0; + assign before_rounding2 = (rounding_counter != 0)? TwoD_output[2]:0; + assign before_rounding3 = (rounding_counter != 0)? TwoD_output[3]:0; + + assign rounding_sum0 = before_rounding0[14:5] + 1; + assign rounding_sum1 = before_rounding1[14:5] + 1; + assign rounding_sum2 = before_rounding2[14:5] + 1; + assign rounding_sum3 = before_rounding3[14:5] + 1; + + //----------------------------------------------------------------------- + // Strore results + //----------------------------------------------------------------------- + //1. Store OneD_output + integer i; + always @ (posedge gclk_1D or negedge reset_n) + if (reset_n == 0) + for (i=0;i<16;i=i+1) + OneD_output[i] <= 0; + else if (OneD_counter != 0) + case (OneD_counter) + 3'b100: + begin + OneD_output[0] <= butterfly_F0;OneD_output[1] <= butterfly_F1; + OneD_output[2] <= butterfly_F2;OneD_output[3] <= butterfly_F3; + end + 3'b011: + begin + OneD_output[4] <= butterfly_F0;OneD_output[5] <= butterfly_F1; + OneD_output[6] <= butterfly_F2;OneD_output[7] <= butterfly_F3; + end + 3'b010: + begin + OneD_output[8] <= butterfly_F0;OneD_output[9] <= butterfly_F1; + OneD_output[10] <= butterfly_F2;OneD_output[11] <= butterfly_F3; + end + 3'b001: + begin + OneD_output[12] <= butterfly_F0;OneD_output[13] <= butterfly_F1; + OneD_output[14] <= butterfly_F2;OneD_output[15] <= butterfly_F3; + end + endcase + + //2. Store TwoD_output + integer j; + always @ (posedge gclk_2D or negedge reset_n) + if (reset_n == 0) + for (j=0;j<4;j=j+1) + TwoD_output[j] <= 0; + else if (TwoD_counter != 0) + begin + TwoD_output[0] <= butterfly_F0; TwoD_output[1] <= butterfly_F1; + TwoD_output[2] <= butterfly_F2; TwoD_output[3] <= butterfly_F3; + end + + //3.1 Store rescale_output as DC_output + integer m; + always @ (posedge gclk_rescale or negedge reset_n) + if (reset_n == 1'b0) + for (m=0;m<16;m=m+1) + DC_output[m] <= 0; + else if (res_DC == 1'b1) + case (rescale_counter) + 3'b100: + begin + DC_output[0] <= shift_output0; DC_output[2] <= shift_output1; + DC_output[8] <= shift_output2; DC_output[10] <= shift_output3; + end + 3'b011: + begin + DC_output[1] <= shift_output0; DC_output[3] <= shift_output1; + DC_output[9] <= shift_output2; DC_output[11] <= shift_output3; + end + 3'b010: + begin + DC_output[4] <= shift_output0; DC_output[6] <= shift_output1; + DC_output[12] <= shift_output2; DC_output[14] <= shift_output3; + end + 3'b001: + if (residual_state == `ChromaDCLevel_Cb_s) + begin + DC_output[0] <= shift_output0; DC_output[1] <= shift_output1; + DC_output[2] <= shift_output2; DC_output[3] <= shift_output3; + end + else if (residual_state == `ChromaDCLevel_Cr_s) + begin + DC_output[4] <= shift_output0; DC_output[5] <= shift_output1; + DC_output[6] <= shift_output2; DC_output[7] <= shift_output3; + end + else + begin + DC_output[5] <= shift_output0; DC_output[7] <= shift_output1; + DC_output[13] <= shift_output2; DC_output[15] <= shift_output3; + end + endcase + + //3.2 Store rescale_output as AC_output + integer n; + always @ (posedge gclk_rescale or negedge reset_n) + if (reset_n == 1'b0) + for (n=0;n<4;n=n+1) + rescale_output[n] <= 0; + else if (res_AC == 1'b1 && rescale_counter != 0) + begin + rescale_output[0] <= shift_output0; rescale_output[1] <= shift_output1; + rescale_output[2] <= shift_output2; rescale_output[3] <= shift_output3; + end + + //4. Store rounding_output + always @ (posedge gclk_rounding or negedge reset_n) + if (reset_n == 1'b0) + begin + rounding_output_0 <= 0;rounding_output_1 <= 0;rounding_output_2 <= 0;rounding_output_3 <= 0; + rounding_output_4 <= 0;rounding_output_5 <= 0;rounding_output_6 <= 0;rounding_output_7 <= 0; + rounding_output_8 <= 0;rounding_output_9 <= 0;rounding_output_10 <= 0;rounding_output_11 <= 0; + rounding_output_12 <= 0;rounding_output_13 <= 0;rounding_output_14 <= 0;rounding_output_15 <= 0; + end + else + case (rounding_counter) + 3'b100: + begin + rounding_output_0 <= rounding_sum0[9:1]; + rounding_output_4 <= rounding_sum1[9:1]; + rounding_output_8 <= rounding_sum2[9:1]; + rounding_output_12 <= rounding_sum3[9:1]; + end + 3'b011: + begin + rounding_output_1 <= rounding_sum0[9:1]; + rounding_output_5 <= rounding_sum1[9:1]; + rounding_output_9 <= rounding_sum2[9:1]; + rounding_output_13 <= rounding_sum3[9:1]; + end + 3'b010: + begin + rounding_output_2 <= rounding_sum0[9:1]; + rounding_output_6 <= rounding_sum1[9:1]; + rounding_output_10 <= rounding_sum2[9:1]; + rounding_output_14 <= rounding_sum3[9:1]; + end + 3'b001: + begin + rounding_output_3 <= rounding_sum0[9:1]; + rounding_output_7 <= rounding_sum1[9:1]; + rounding_output_11 <= rounding_sum2[9:1]; + rounding_output_15 <= rounding_sum3[9:1]; + end + endcase + assign end_of_ACBlk4x4_IQIT = (rounding_counter == 3'b001)? 1'b1:1'b0; + assign end_of_DCBlk_IQIT = ((residual_state == `Intra16x16DCLevel_s || residual_state == `ChromaDCLevel_Cb_s || + residual_state == `ChromaDCLevel_Cr_s) && rescale_counter == 3'b001)? 1'b1:1'b0; +endmodule + +module butterfly (D0,D1,D2,D3,F0,F1,F2,F3,IsHadamard); + input [15:0] D0,D1,D2,D3; + input IsHadamard; + output [15:0] F0,F1,F2,F3; + + wire [15:0] T0,T1,T2,T3; + wire [15:0] D1_scale,D3_scale; + + assign D1_scale = (IsHadamard == 1'b1)? D1:{D1[15],D1[15:1]}; + assign D3_scale = (IsHadamard == 1'b1)? D3:{D3[15],D3[15:1]}; + + assign T0 = D0 + D2; + assign T1 = D0 - D2; + assign T2 = D1_scale - D3; + assign T3 = D1 + D3_scale; + + assign F0 = T0 + T3; + assign F1 = T1 + T2; + assign F2 = T1 - T2; + assign F3 = T0 - T3; +endmodule + +module mod6 (qp,mod); + input [5:0] qp; + output [2:0] mod; + reg [2:0] mod; + always @ (qp) + case (qp) + 0, 6,12,18,24,30,36,42,48:mod <= 3'b000; + 1, 7,13,19,25,31,37,43,49:mod <= 3'b001; + 2, 8,14,20,26,32,38,44,50:mod <= 3'b010; + 3, 9,15,21,27,33,39,45,51:mod <= 3'b011; + 4,10,16,22,28,34,40,46 :mod <= 3'b100; + 5,11,17,23,29,35,41,47 :mod <= 3'b101; + default :mod <= 3'b000; + endcase +endmodule + +module div6 (qp,div); + input [5:0] qp; + output [3:0] div; + reg [3:0] div; + always @ (qp) + case (qp) + 0, 1, 2, 3, 4, 5 :div <= 4'b0000; + 6, 7, 8, 9, 10,11:div <= 4'b0001; + 12,13,14,15,16,17:div <= 4'b0010; + 18,19,20,21,22,23:div <= 4'b0011; + 24,25,26,27,28,29:div <= 4'b0100; + 30,31,32,33,34,35:div <= 4'b0101; + 36,37,38,39,40,41:div <= 4'b0110; + 42,43,44,45,46,47:div <= 4'b0111; + 48,49,50,51 :div <= 4'b1000; + default :div <= 0; + endcase +endmodule + +module rescale_shift (IsLeftShift,shift_input,shift_len,shift_output); + input IsLeftShift; + input signed [15:0] shift_input; + input [3:0] shift_len; + output signed [15:0] shift_output; + + assign shift_output = (IsLeftShift == 1'b1)? (shift_input <<< shift_len):(shift_input >>> shift_len); +endmodule + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/Inter_mv_decoding.v b/demo_chip_rtl/rtl/nova/tags/Start/src/Inter_mv_decoding.v new file mode 100644 index 0000000..94524e7 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/Inter_mv_decoding.v @@ -0,0 +1,2612 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : Inter_mv_decoding.v +// Generated : May 25, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Decoding the motion vector x and motion vector y for Inter prediction and P_skip +// SearchRange = 16pix -> 64 -> -64 ~ + 64 -> mvd[7:0], mv[7:0], mvp[7:0] +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module Inter_mv_decoding (clk,reset_n,Is_skip_run_entry,Is_skip_run_end, + slice_data_state,mb_pred_state,sub_mb_pred_state,mvd, + mb_num,mb_num_h,mb_num_v,mb_type_general,sub_mb_type,end_of_MB_DEC,mbPartIdx,subMbPartIdx,compIdx, + MBTypeGen_mbAddrA,MBTypeGen_mbAddrB_reg,MBTypeGen_mbAddrD, + mvx_mbAddrB_dout,mvy_mbAddrB_dout,mvx_mbAddrC_dout,mvy_mbAddrC_dout,mv_mbAddrB_rd_for_DF, + + skip_mv_calc,Is_skipMB_mv_calc,mvx_mbAddrA,mvy_mbAddrA, + mvx_mbAddrB_cs_n,mvx_mbAddrB_wr_n,mvx_mbAddrB_rd_addr,mvx_mbAddrB_wr_addr,mvx_mbAddrB_din, + mvy_mbAddrB_cs_n,mvy_mbAddrB_wr_n,mvy_mbAddrB_rd_addr,mvy_mbAddrB_wr_addr,mvy_mbAddrB_din, + mvx_mbAddrC_cs_n,mvx_mbAddrC_wr_n,mvx_mbAddrC_rd_addr,mvx_mbAddrC_wr_addr,mvx_mbAddrC_din, + mvy_mbAddrC_cs_n,mvy_mbAddrC_wr_n,mvy_mbAddrC_rd_addr,mvy_mbAddrC_wr_addr,mvy_mbAddrC_din, + mv_is16x16, + mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3, + mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3); + input clk,reset_n; + input Is_skip_run_entry; + input Is_skip_run_end; + input [3:0] slice_data_state; + input [2:0] mb_pred_state; + input [1:0] sub_mb_pred_state; + input [7:0] mvd; + input [6:0] mb_num; + input [3:0] mb_num_h; + input [3:0] mb_num_v; + input [3:0] mb_type_general; + input [1:0] sub_mb_type; + input end_of_MB_DEC; + input [1:0] mbPartIdx,subMbPartIdx; + input compIdx; + input [1:0] MBTypeGen_mbAddrA; + input MBTypeGen_mbAddrD; + input [21:0] MBTypeGen_mbAddrB_reg; + input [31:0] mvx_mbAddrB_dout,mvy_mbAddrB_dout; + input [7:0] mvx_mbAddrC_dout,mvy_mbAddrC_dout; + input mv_mbAddrB_rd_for_DF; + + output skip_mv_calc; + output Is_skipMB_mv_calc; + output [31:0] mvx_mbAddrA,mvy_mbAddrA; + output mvx_mbAddrB_cs_n,mvy_mbAddrB_cs_n,mvx_mbAddrC_cs_n,mvy_mbAddrC_cs_n; + output mvx_mbAddrB_wr_n,mvy_mbAddrB_wr_n,mvx_mbAddrC_wr_n,mvy_mbAddrC_wr_n; + output [3:0] mvx_mbAddrB_rd_addr,mvy_mbAddrB_rd_addr,mvx_mbAddrC_rd_addr,mvy_mbAddrC_rd_addr; + output [3:0] mvx_mbAddrB_wr_addr,mvy_mbAddrB_wr_addr,mvx_mbAddrC_wr_addr,mvy_mbAddrC_wr_addr; + output [31:0] mvx_mbAddrB_din,mvy_mbAddrB_din; + output [7:0] mvx_mbAddrC_din,mvy_mbAddrC_din; + output mv_is16x16; + output [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3; + output [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3; + reg mvx_mbAddrB_cs_n,mvy_mbAddrB_cs_n,mvx_mbAddrC_cs_n,mvy_mbAddrC_cs_n; + reg mvx_mbAddrB_wr_n,mvy_mbAddrB_wr_n,mvx_mbAddrC_wr_n,mvy_mbAddrC_wr_n; + reg [3:0] mvx_mbAddrB_rd_addr,mvy_mbAddrB_rd_addr,mvx_mbAddrC_rd_addr,mvy_mbAddrC_rd_addr; + reg [3:0] mvx_mbAddrB_wr_addr,mvy_mbAddrB_wr_addr,mvx_mbAddrC_wr_addr,mvy_mbAddrC_wr_addr; + reg [31:0] mvx_mbAddrB_din,mvy_mbAddrB_din; + reg [7:0] mvx_mbAddrC_din,mvy_mbAddrC_din; + reg mv_is16x16; + reg [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3; + reg [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3; + + reg [7:0] mvpAx,mvpAy,mvpBx,mvpBy,mvpCx,mvpCy; + reg [31:0] mvx_mbAddrA,mvy_mbAddrA; + wire [7:0] mvx_mbAddrD,mvy_mbAddrD; + reg [7:0] mvpx,mvpy,mvx,mvy; + + reg skip_mv_calc; //This signal is of reg type and is active for one cycle after end_of_MB_DEC and before + //trigger_blk4x4_inter_pred.It is used to direct motion vector prediction for skipped MB + always @ (posedge clk) + if (reset_n == 1'b0) + skip_mv_calc <= 1'b0; + else if (slice_data_state == `skip_run_duration && end_of_MB_DEC && !Is_skip_run_end) + skip_mv_calc <= 1'b1; + else + skip_mv_calc <= 1'b0; + + wire Is_skipMB_mv_calc; + assign Is_skipMB_mv_calc = Is_skip_run_entry | skip_mv_calc; + + reg [1:0] MBTypeGen_mbAddrB; + reg [1:0] MBTypeGen_mbAddrC; + always @ (mb_num_h or MBTypeGen_mbAddrB_reg) + case (mb_num_h) + 0 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[1:0]; + 1 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[3:2]; + 2 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[5:4]; + 3 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[7:6]; + 4 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[9:8]; + 5 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[11:10]; + 6 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[13:12]; + 7 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[15:14]; + 8 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[17:16]; + 9 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[19:18]; + 10:MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[21:20]; + default:MBTypeGen_mbAddrB <= 0; + endcase + always @ (mb_num_h or MBTypeGen_mbAddrB_reg) + case (mb_num_h) + 0:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[3:2]; + 1:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[5:4]; + 2:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[7:6]; + 3:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[9:8]; + 4:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[11:10]; + 5:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[13:12]; + 6:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[15:14]; + 7:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[17:16]; + 8:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[19:18]; + 9:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[21:20]; + default:MBTypeGen_mbAddrC <= 0; + endcase + + wire refIdxL0_A; //Here refIdxL0_A == 1'b1 is equal to refIdxL0_A == -1 in Page122 of H.264 2003.5 standard + wire refIdxL0_B; //Here refIdxL0_B == 1'b1 is equal to refIdxL0_B == -1 in Page122 of H.264 2003.5 standard + reg refIdxL0_C; //Here refIdxL0_C == 1'b1 is equal to refIdxL0_C == -1 in Page122 of H.264 2003.5 standard + + assign refIdxL0_A = ( + //P_skip + (Is_skipMB_mv_calc || + //Inter16x16,Inter16x8,Inter8x16 left blk + (mb_pred_state == `mvd_l0_s && (mb_type_general == `MB_Inter16x16 || mb_type_general == `MB_Inter16x8 || (mb_type_general == `MB_Inter8x16 && mbPartIdx == 0))) || + //Inter8x8,left most blk + (sub_mb_pred_state == `sub_mvd_l0_s && (mbPartIdx == 0 || mbPartIdx == 2) && ( + sub_mb_type == 0 || + sub_mb_type == 1 || + (sub_mb_type == 2 && subMbPartIdx == 0) || + (sub_mb_type == 3 && (subMbPartIdx == 0 || subMbPartIdx == 2))))) && + (mb_num_h == 0 || MBTypeGen_mbAddrA[1] == 1))? 1'b1:1'b0; + + assign refIdxL0_B = ( + //P_skip + (Is_skipMB_mv_calc || + //Inter16x16,Inter16x8 upper blk,Inter8x16 + (mb_pred_state == `mvd_l0_s && (mb_type_general == `MB_Inter16x16 || (mb_type_general == `MB_Inter16x8 && mbPartIdx == 0) || mb_type_general == `MB_Inter8x16)) || + //Inter8x8,left most blk + (sub_mb_pred_state == `sub_mvd_l0_s && (mbPartIdx == 0 || mbPartIdx == 1) && ( + sub_mb_type == 0 || + sub_mb_type == 2 || + (sub_mb_type == 1 && subMbPartIdx == 0) || + (sub_mb_type == 3 && (subMbPartIdx == 0 || subMbPartIdx == 1))))) && + (mb_num_v == 0 || MBTypeGen_mbAddrB[1] == 1))? 1'b1:1'b0; + + always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state or mb_type_general or mb_num_v or mb_num_h + or sub_mb_type or mbPartIdx or subMbPartIdx or MBTypeGen_mbAddrC[1] or MBTypeGen_mbAddrD + or refIdxL0_A or refIdxL0_B) + //P_skip,Inter16x16 + if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16)) + begin + if (mb_num_v == 0) refIdxL0_C <= 1'b1; + else if (mb_num_h == 10) refIdxL0_C <= (MBTypeGen_mbAddrD == `MB_addrD_Intra)? 1'b1:1'b0; + else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0; + end + //Inter16x8 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8) + begin + if (mbPartIdx == 0) //upper blk + begin + if (mb_num_v == 0) refIdxL0_C <= 1'b1; + else if (mb_num_h == 10) refIdxL0_C <= (MBTypeGen_mbAddrD == `MB_addrD_Intra)? 1'b1:1'b0; + else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0; + end + else //bottom blk + refIdxL0_C <= refIdxL0_A; + end + //Inter8x16 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16) + begin + if (mbPartIdx == 0) //left blk + refIdxL0_C <= refIdxL0_B; + else //right blk + begin + if (mb_num_v == 0 || mb_num_h == 10) refIdxL0_C <= refIdxL0_B; + else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0; + end + end + //Inter8x8 and below + else if (sub_mb_pred_state == `sub_mvd_l0_s) + case (mbPartIdx) + 2'b00: //left-top 8x8 blk + case (sub_mb_type) + 0:refIdxL0_C <= refIdxL0_B; + 1:refIdxL0_C <= (subMbPartIdx == 0)? refIdxL0_B:refIdxL0_A; + 2:refIdxL0_C <= refIdxL0_B; + 3: + case (subMbPartIdx) + 0,1:refIdxL0_C <= refIdxL0_B; + 2,3:refIdxL0_C <= 1'b0; + endcase + endcase + 2'b01: //right-top 8x8 blk + case (sub_mb_type) + 0: //8x8 + if (mb_num_v == 0) refIdxL0_C <= 1'b1; + else if (mb_num_h == 10) refIdxL0_C <= refIdxL0_B; + else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0; + 1: //8x4 + if (subMbPartIdx == 0) + begin + if (mb_num_v == 0) refIdxL0_C <= 1'b1; + else if (mb_num_h == 10) refIdxL0_C <= refIdxL0_B; + else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0; + end + else + refIdxL0_C <= 1'b0; + 2: //4x8 + if (subMbPartIdx == 0) refIdxL0_C <= refIdxL0_B; + else + begin + if (mb_num_v == 0) refIdxL0_C <= 1'b1; + else if (mb_num_h == 10) refIdxL0_C <= refIdxL0_B; + else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0; + end + 3: //4x4 + case (subMbPartIdx) + 0:refIdxL0_C <= refIdxL0_B; + 1: + begin + if (mb_num_v == 0) refIdxL0_C <= 1'b1; + else if (mb_num_h == 10) refIdxL0_C <= refIdxL0_B; + else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0; + end + 2,3:refIdxL0_C <= 1'b0; + endcase + endcase + 2'b10: //left-bottom 8x8 blk + case (sub_mb_type) + 0:refIdxL0_C <= 1'b0; + 1:refIdxL0_C <= (subMbPartIdx == 0)? 1'b0:refIdxL0_A; + 2:refIdxL0_C <= 1'b0; + 3:refIdxL0_C <= 1'b0; + endcase + 2'b11: //right-bottom 8x8 blk + refIdxL0_C <= 1'b0; + endcase + else + refIdxL0_C <= 1'b0; + + //------------- + //mvpAx + //------------- + always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state + or mb_type_general or sub_mb_type or mbPartIdx or subMbPartIdx or compIdx + or mvx_mbAddrA or mvx_CurrMb0 or mvx_CurrMb1 or mvx_CurrMb2 or mvx_CurrMb3 + or refIdxL0_A or refIdxL0_B or refIdxL0_C) + //P_skip or Inter16x16 + if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0)) + mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0]; + //Inter16x8 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0) + begin + if (mbPartIdx == 0) + mvpAx <= {8{refIdxL0_B}} & mvx_mbAddrA[7:0]; + else + mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[23:16]; + end + //Inter8x16 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 0) + begin + if (mbPartIdx == 0) + mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0]; + else + mvpAx <= {8{refIdxL0_C}} & mvx_CurrMb0[15:8]; + end + //Inter8x8 + else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0) //sub_mb_pred + case (mbPartIdx) + 0: + case (sub_mb_type) + 0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0]; + 1: //8x4 + case (subMbPartIdx) + 0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0]; + 1:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[15:8]; + default:mvpAx <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0]; + 1:mvpAx <= mvx_CurrMb0[7:0]; + default:mvpAx <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0]; + 1:mvpAx <= mvx_CurrMb0[7:0]; + 2:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[15:8]; + 3:mvpAx <= mvx_CurrMb0[23:16]; + endcase + endcase + 1: + case (sub_mb_type) + 0:mvpAx <= mvx_CurrMb0[15:8]; + 1: //8x4 + case (subMbPartIdx) + 0:mvpAx <= mvx_CurrMb0[15:8]; 1:mvpAx <= mvx_CurrMb0[31:24]; + default:mvpAx <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:mvpAx <= mvx_CurrMb0[15:8]; 1:mvpAx <= mvx_CurrMb1[7:0]; + default:mvpAx <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvpAx <= mvx_CurrMb0[15:8] ; 1:mvpAx <= mvx_CurrMb1[7:0]; + 2:mvpAx <= mvx_CurrMb0[31:24]; 3:mvpAx <= mvx_CurrMb1[23:16]; + endcase + endcase + 2: + case (sub_mb_type) + 0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[23:16]; + 1: //8x4 + case (subMbPartIdx) + 0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[23:16]; + 1:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[31:24]; + default:mvpAx <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[23:16]; + 1:mvpAx <= mvx_CurrMb2[7:0]; + default:mvpAx <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[23:16]; + 1:mvpAx <= mvx_CurrMb2[7:0]; + 2:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[31:24]; + 3:mvpAx <= mvx_CurrMb2[23:16]; + endcase + endcase + 3: + case (sub_mb_type) + 0:mvpAx <= mvx_CurrMb2[15:8]; + 1: //8x4 + case (subMbPartIdx) + 0:mvpAx <= mvx_CurrMb2[15:8]; 1:mvpAx <= mvx_CurrMb2[31:24]; + default:mvpAx <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:mvpAx <= mvx_CurrMb2[15:8]; 1:mvpAx <= mvx_CurrMb3[7:0]; + default:mvpAx <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvpAx <= mvx_CurrMb2[15:8]; 1:mvpAx <= mvx_CurrMb3[7:0]; + 2:mvpAx <= mvx_CurrMb2[31:24]; 3:mvpAx <= mvx_CurrMb3[23:16]; + endcase + endcase + endcase + else + mvpAx <= 0; + + //------------- + //mvpAy + //------------- + always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state + or mb_type_general or sub_mb_type or mbPartIdx or subMbPartIdx or compIdx + or mvy_mbAddrA or mvy_CurrMb0 or mvy_CurrMb1 or mvy_CurrMb2 or mvy_CurrMb3 + or refIdxL0_A or refIdxL0_B or refIdxL0_C) + //P_skip or Inter16x16 + if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1)) + mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[7:0]; + //Inter16x8 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1) + begin + if (mbPartIdx == 0) + mvpAy <= {8{refIdxL0_B}} & mvy_mbAddrA[7:0]; + else + mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[23:16]; + end + //Inter8x16 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 1) + begin + if (mbPartIdx == 0) + mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[7:0]; + else + mvpAy <= {8{refIdxL0_C}} & mvy_CurrMb0[15:8]; + end + //Inter8x8 + else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1) //sub_mb_pred + case (mbPartIdx) + 0: + case (sub_mb_type) + 0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[7:0]; + 1: //8x4 + case (subMbPartIdx) + 0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[7:0]; + 1:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[15:8]; + default:mvpAy <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[7:0]; + 1:mvpAy <= mvy_CurrMb0[7:0]; + default:mvpAy <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[7:0]; + 1:mvpAy <= mvy_CurrMb0[7:0]; + 2:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[15:8]; + 3:mvpAy <= mvy_CurrMb0[23:16]; + endcase + endcase + 1: + case (sub_mb_type) + 0:mvpAy <= mvy_CurrMb0[15:8]; + 1: //8x4 + case (subMbPartIdx) + 0:mvpAy <= mvy_CurrMb0[15:8]; 1:mvpAy <= mvy_CurrMb0[31:24]; + default:mvpAy <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:mvpAy <= mvy_CurrMb0[15:8]; 1:mvpAy <= mvy_CurrMb1[7:0]; + default:mvpAy <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvpAy <= mvy_CurrMb0[15:8] ; 1:mvpAy <= mvy_CurrMb1[7:0]; + 2:mvpAy <= mvy_CurrMb0[31:24]; 3:mvpAy <= mvy_CurrMb1[23:16]; + endcase + endcase + 2: + case (sub_mb_type) + 0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[23:16]; + 1: //8x4 + case (subMbPartIdx) + 0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[23:16]; + 1:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[31:24]; + default:mvpAy <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[23:16]; + 1:mvpAy <= mvy_CurrMb2[7:0]; + default:mvpAy <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[23:16]; + 1:mvpAy <= mvy_CurrMb2[7:0]; + 2:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[31:24]; + 3:mvpAy <= mvy_CurrMb2[23:16]; + endcase + endcase + 3: + case (sub_mb_type) + 0:mvpAy <= mvy_CurrMb2[15:8]; + 1: //8x4 + case (subMbPartIdx) + 0:mvpAy <= mvy_CurrMb2[15:8]; 1:mvpAy <= mvy_CurrMb2[31:24]; + default:mvpAy <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:mvpAy <= mvy_CurrMb2[15:8]; 1:mvpAy <= mvy_CurrMb3[7:0]; + default:mvpAy <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvpAy <= mvy_CurrMb2[15:8]; 1:mvpAy <= mvy_CurrMb3[7:0]; + 2:mvpAy <= mvy_CurrMb2[31:24]; 3:mvpAy <= mvy_CurrMb3[23:16]; + endcase + endcase + endcase + else + mvpAy <= 0; + //------------- + //mvpBx + //------------- + //if B is not available,it can be predicted from A when both B and C are not available + always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state or mb_type_general or sub_mb_type + or mb_num or mb_num_v or mbPartIdx or subMbPartIdx or compIdx or MBTypeGen_mbAddrA[1] or MBTypeGen_mbAddrB[1] + or mvx_mbAddrA or mvx_mbAddrB_dout or mvx_CurrMb0 or mvx_CurrMb1 or mvx_CurrMb2 or mvx_CurrMb3 + or refIdxL0_A or refIdxL0_B or refIdxL0_C) + //P_skip or Inter16x16 + if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0)) + begin + if (mb_num == 0) mvpBx <= 0; + else if (mb_num_v == 0) mvpBx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0]; + else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[31:24]; + end + //Inter16x8 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0) + begin + if (mbPartIdx == 0) + begin + if (mb_num == 0) mvpBx <= 0; + else if (mb_num_v == 0) mvpBx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0]; + else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[31:24]; + end + else //for bottom 8x8 block when mbAddrA is not available + mvpBx <= (!refIdxL0_A)? 0:mvx_CurrMb0[23:16]; + end + //Inter8x16:for left 8x8 block when mbAddrA is not available + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 0) + begin + if (mbPartIdx == 0) //left blk + mvpBx <= (refIdxL0_A && !refIdxL0_B)? mvx_mbAddrB_dout[31:24]:0; + else //right blk + case (!refIdxL0_C) + 1'b1:mvpBx <= 0; + 1'b0: + if (mb_num_v == 0) + mvpBx <= mvx_CurrMb0[7:0]; + else + mvpBx <= (!refIdxL0_B)? mvx_mbAddrB_dout[15:8]:0; + endcase + end + //Inter8x8 + else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0) + case (mbPartIdx) + 0: + case (sub_mb_type) + 0:if (mb_num == 0) mvpBx <= 0; + else if (mb_num_v == 0) mvpBx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0]; + else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[31:24]; + 1: //8x4 + case (subMbPartIdx) + 0:if (mb_num == 0) mvpBx <= 0; + else if (mb_num_v == 0) mvpBx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0]; + else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[31:24]; + 1:mvpBx <= mvx_CurrMb0[7:0]; + default:mvpBx <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:if (mb_num == 0) mvpBx <= 0; + else if (mb_num_v == 0) mvpBx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0]; + else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[31:24]; + 1:if (mb_num_v == 0) mvpBx <= mvx_CurrMb0[7:0]; + else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16]; + default:mvpBx <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:if (mb_num == 0) mvpBx <= 0; + else if (mb_num_v == 0) mvpBx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0]; + else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[31:24]; + 1:if (mb_num_v == 0) mvpBx <= mvx_CurrMb0[7:0]; + else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16]; + 2:mvpBx <= mvx_CurrMb0[7:0]; + 3:mvpBx <= mvx_CurrMb0[15:8]; + endcase + endcase + 1: + case (sub_mb_type) + 0:mvpBx <= (mb_num_v == 0)? mvx_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]); + 1: //8x4 + case (subMbPartIdx) + 0:mvpBx <= (mb_num_v == 0)? mvx_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]); + 1:mvpBx <= mvx_CurrMb1[7:0]; + default:mvpBx <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:mvpBx <= (mb_num_v == 0)? mvx_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]); + 1:mvpBx <= (mb_num_v == 0)? mvx_CurrMb1[7:0] :((MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[7:0]); + default:mvpBx <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvpBx <= (mb_num_v == 0)? mvx_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]); + 1:mvpBx <= (mb_num_v == 0)? mvx_CurrMb1[7:0] :((MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[7:0]); + 2:mvpBx <= mvx_CurrMb1[7:0]; + 3:mvpBx <= mvx_CurrMb1[15:8]; + endcase + endcase + 2: + case (sub_mb_type) + 0:mvpBx <= mvx_CurrMb0[23:16]; + 1: //8x4 + case (subMbPartIdx) + 0:mvpBx <= mvx_CurrMb0[23:16]; 1:mvpBx <= mvx_CurrMb2[7:0]; default:mvpBx <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:mvpBx <= mvx_CurrMb0[23:16]; 1:mvpBx <= mvx_CurrMb0[31:24]; default:mvpBx <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvpBx <= mvx_CurrMb0[23:16]; 1:mvpBx <= mvx_CurrMb0[31:24]; + 2:mvpBx <= mvx_CurrMb2[7:0]; 3:mvpBx <= mvx_CurrMb2[15:8]; + endcase + endcase + 3: + case (sub_mb_type) + 0:mvpBx <= mvx_CurrMb1[23:16]; + 1: //8x4 + case (subMbPartIdx) + 0:mvpBx <= mvx_CurrMb1[23:16]; 1:mvpBx <= mvx_CurrMb3[7:0]; default:mvpBx <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:mvpBx <= mvx_CurrMb1[23:16]; 1:mvpBx <= mvx_CurrMb1[31:24]; default:mvpBx <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvpBx <= mvx_CurrMb1[23:16]; 1:mvpBx <= mvx_CurrMb1[31:24]; + 2:mvpBx <= mvx_CurrMb3[7:0]; 3:mvpBx <= mvx_CurrMb3[15:8]; + endcase + endcase + endcase + else + mvpBx <= 0; + //------------- + //mvpBy + //------------- + //if B is not available,it can be predicted from A when both B and C are not available + always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state or mb_type_general or sub_mb_type + or mb_num or mb_num_v or mbPartIdx or subMbPartIdx or compIdx or MBTypeGen_mbAddrA[1] or MBTypeGen_mbAddrB[1] + or mvy_mbAddrA or mvy_mbAddrB_dout or mvy_CurrMb0 or mvy_CurrMb1 or mvy_CurrMb2 or mvy_CurrMb3 + or refIdxL0_A or refIdxL0_B or refIdxL0_C) + //P_skip or Inter16x16 + if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1)) + begin + if (mb_num == 0) mvpBy <= 0; + else if (mb_num_v == 0) mvpBy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0]; + else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[31:24]; + end + //Inter16x8 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1) + begin + if (mbPartIdx == 0) //upper 8x8 block + begin + if (mb_num == 0) mvpBy <= 0; + else if (mb_num_v == 0) mvpBy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0]; + else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[31:24]; + end + else //for bottom 8x8 block when mbAddrA is not available + mvpBy <= (!refIdxL0_A)? 0:mvy_CurrMb0[23:16]; + end + //Inter8x16:for left 8x8 block when mbAddrA is not available + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 1) + begin + if (mbPartIdx == 0) //left blk + mvpBy <= (refIdxL0_A && !refIdxL0_B)? mvy_mbAddrB_dout[31:24]:0; + else //right blk + case (!refIdxL0_C) + 1'b1:mvpBy <= 0; + 1'b0: + if (mb_num_v == 0) + mvpBy <= mvy_CurrMb0[7:0]; + else + mvpBy <= (!refIdxL0_B)? mvy_mbAddrB_dout[15:8]:0; + endcase + end + //Inter8x8 + else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1) + case (mbPartIdx) + 0: + case (sub_mb_type) + 0:if (mb_num == 0) mvpBy <= 0; + else if (mb_num_v == 0) mvpBy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0]; + else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[31:24]; + 1: //8x4 + case (subMbPartIdx) + 0:if (mb_num == 0) mvpBy <= 0; + else if (mb_num_v == 0) mvpBy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0]; + else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[31:24]; + 1:mvpBy <= mvy_CurrMb0[7:0]; + default:mvpBy <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:if (mb_num == 0) mvpBy <= 0; + else if (mb_num_v == 0) mvpBy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0]; + else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[31:24]; + 1:if (mb_num_v == 0) mvpBy <= mvy_CurrMb0[7:0]; + else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16]; + default:mvpBy <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:if (mb_num == 0) mvpBy <= 0; + else if (mb_num_v == 0) mvpBy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0]; + else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[31:24]; + 1:if (mb_num_v == 0) mvpBy <= mvy_CurrMb0[7:0]; + else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16]; + 2:mvpBy <= mvy_CurrMb0[7:0]; + 3:mvpBy <= mvy_CurrMb0[15:8]; + endcase + endcase + 1: + case (sub_mb_type) + 0:mvpBy <= (mb_num_v == 0)? mvy_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]); + 1: //8x4 + case (subMbPartIdx) + 0:mvpBy <= (mb_num_v == 0)? mvy_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]); + 1:mvpBy <= mvy_CurrMb1[7:0]; + default:mvpBy <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:mvpBy <= (mb_num_v == 0)? mvy_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]); + 1:mvpBy <= (mb_num_v == 0)? mvy_CurrMb1[7:0] :((MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[7:0]); + default:mvpBy <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvpBy <= (mb_num_v == 0)? mvy_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]); + 1:mvpBy <= (mb_num_v == 0)? mvy_CurrMb1[7:0] :((MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[7:0]); + 2:mvpBy <= mvy_CurrMb1[7:0]; + 3:mvpBy <= mvy_CurrMb1[15:8]; + endcase + endcase + 2: + case (sub_mb_type) + 0:mvpBy <= mvy_CurrMb0[23:16]; + 1: //8x4 + case (subMbPartIdx) + 0:mvpBy <= mvy_CurrMb0[23:16]; 1:mvpBy <= mvy_CurrMb2[7:0]; default:mvpBy <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:mvpBy <= mvy_CurrMb0[23:16]; 1:mvpBy <= mvy_CurrMb0[31:24]; default:mvpBy <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvpBy <= mvy_CurrMb0[23:16]; 1:mvpBy <= mvy_CurrMb0[31:24]; + 2:mvpBy <= mvy_CurrMb2[7:0]; 3:mvpBy <= mvy_CurrMb2[15:8]; + endcase + endcase + 3: + case (sub_mb_type) + 0:mvpBy <= mvy_CurrMb1[23:16]; + 1: //8x4 + case (subMbPartIdx) + 0:mvpBy <= mvy_CurrMb1[23:16]; 1:mvpBy <= mvy_CurrMb3[7:0]; default:mvpBy <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:mvpBy <= mvy_CurrMb1[23:16]; 1:mvpBy <= mvy_CurrMb1[31:24]; default:mvpBy <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvpBy <= mvy_CurrMb1[23:16]; 1:mvpBy <= mvy_CurrMb1[31:24]; + 2:mvpBy <= mvy_CurrMb3[7:0]; 3:mvpBy <= mvy_CurrMb3[15:8]; + endcase + endcase + endcase + else + mvpBy <= 0; + //------------- + //mvpCx + //------------- + //if C is not available,it can be predicted from D,then from A + always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state or mb_num or mb_num_h or mb_num_v + or mb_type_general or sub_mb_type or mbPartIdx or subMbPartIdx or compIdx + or MBTypeGen_mbAddrA[1] or MBTypeGen_mbAddrB[1] or MBTypeGen_mbAddrC[1] or MBTypeGen_mbAddrD + or mvx_mbAddrA or mvx_mbAddrB_dout or mvx_mbAddrC_dout or mvx_mbAddrD + or mvx_CurrMb0 or mvx_CurrMb1 or mvx_CurrMb2 or mvx_CurrMb3 + or refIdxL0_A or refIdxL0_B or refIdxL0_C) + //P_skip,Inter16x16 + if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0)) + begin + if (mb_num == 0) mvpCx <= 0; + else if (mb_num_v == 0) mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0]; + else if (mb_num_h == 10) mvpCx <= (MBTypeGen_mbAddrD == 1)? 0:mvx_mbAddrD; + else mvpCx <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvx_mbAddrC_dout; + end + //Inter16x8 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0) + begin + if (mbPartIdx == 0) + mvpCx <= (refIdxL0_B && !refIdxL0_C)? ((mb_num_h == 10)? mvx_mbAddrD:mvx_mbAddrC_dout):0; + else + mvpCx <= 0; + end + //Inter8x16 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 0) + begin + //when mbAddrA is not available,Inter8x16 left blk needs to have its mbAddrC (= mbAddrB of upper line) derived + if (mbPartIdx == 0) //left blk + mvpCx <= (refIdxL0_A && !refIdxL0_B)? mvx_mbAddrB_dout[15:8]:0; + else //right blk + begin + if (mb_num == 0) mvpCx <= 0; + else if (mb_num_v == 0) mvpCx <= mvx_CurrMb0[15:8]; + else if (mb_num_h == 10) mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16]; + else mvpCx <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvx_mbAddrC_dout; + end + end + //Inter8x8 + else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0) + case (mbPartIdx) + 0: + case (sub_mb_type) + 0:if (mb_num == 0) mvpCx <= 0; + else if (mb_num_v == 0) mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0]; + else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]; + 1: //8x4 + case (subMbPartIdx) + 0:if (mb_num == 0) mvpCx <= 0; + else if (mb_num_v == 0) mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0]; + else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]; + 1:if (mb_num_h == 0) mvpCx <= 0; + else mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrD; + default:mvpCx <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:if (mb_num == 0) mvpCx <= 0; + else if (mb_num_v == 0) mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0]; + else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16]; + 1:if (mb_num_v == 0) mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_CurrMb0[7:0]; + else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]; + default:mvpCx <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:if (mb_num == 0) mvpCx <= 0; + else if (mb_num_v == 0) mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0]; + else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16]; + 1:if (mb_num_v == 0) mvpCx <= mvx_CurrMb0[7:0]; + else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]; + 2:mvpCx <= mvx_CurrMb0[15:8]; //always available + 3:mvpCx <= mvx_CurrMb0[7:0]; //always from D + endcase + endcase + 1: + case (sub_mb_type) + 0:if (mb_num_v == 0) mvpCx <= mvx_CurrMb0[15:8]; + else if (mb_num_h == 10) //predicted from D,but lies initial mbAddrB + mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16]; + else mvpCx <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvx_mbAddrC_dout; + 1: //8x4 + case (subMbPartIdx) + 0:if (mb_num_v == 0) mvpCx <= mvx_CurrMb0[15:8]; + else if (mb_num_h == 10) //predicted from D,but lies initial mbAddrB + mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16]; + else mvpCx <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvx_mbAddrC_dout; + 1:mvpCx <= mvx_CurrMb0[15:8]; //C is always unavailable,D is always available + default:mvpCx <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:if (mb_num_v == 0) mvpCx <= mvx_CurrMb0[15:8]; + else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[7:0]; + 1:if (mb_num_v == 0) mvpCx <= mvx_CurrMb1[7:0]; + else if (mb_num_h == 10) //predicted from D,but lies in mbAddrB + mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]; + else mvpCx <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvx_mbAddrC_dout; + default:mvpCx <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:if (mb_num_v == 0) mvpCx <= mvx_CurrMb0[15:8]; + else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[7:0]; + 1:if (mb_num_v == 0) mvpCx <= mvx_CurrMb1[7:0]; + else if (mb_num_h == 10) //predicted from D,but lies initial mbAddrB + mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]; + else mvpCx <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvx_mbAddrC_dout; + 2:mvpCx <= mvx_CurrMb1[15:8]; + 3:mvpCx <= mvx_CurrMb1[7:0]; + endcase + endcase + 2: + case (sub_mb_type) + 0:mvpCx <= mvx_CurrMb1[23:16]; + 1: //8x4 + case (subMbPartIdx) + 0:mvpCx <= mvx_CurrMb1[23:16]; + 1:if (mb_num_h == 0) mvpCx <= 0; + else mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrD; + default:mvpCx <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:mvpCx <= mvx_CurrMb0[31:24]; 1:mvpCx <= mvx_CurrMb1[23:16]; default:mvpCx <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvpCx <= mvx_CurrMb0[31:24]; 1:mvpCx <= mvx_CurrMb1[23:16]; + 2:mvpCx <= mvx_CurrMb2[15:8]; 3:mvpCx <= mvx_CurrMb2[7:0]; + endcase + endcase + 3: + case (sub_mb_type) + 0:mvpCx <= mvx_CurrMb0[31:24]; + 1: //8x4 + case (subMbPartIdx) + 0:mvpCx <= mvx_CurrMb0[31:24]; 1:mvpCx <= mvx_CurrMb2[15:8]; default:mvpCx <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:mvpCx <= mvx_CurrMb1[31:24]; 1:mvpCx <= mvx_CurrMb1[23:16]; default:mvpCx <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvpCx <= mvx_CurrMb1[31:24]; 1:mvpCx <= mvx_CurrMb1[23:16]; + 2:mvpCx <= mvx_CurrMb3[15:8]; 3:mvpCx <= mvx_CurrMb3[7:0]; + endcase + endcase + endcase + else + mvpCx <= 0; + //------------- + //mvpCy + //------------- + //if C is not available,it can be predicted from D,then from A + always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state or mb_num or mb_num_h or mb_num_v + or mb_type_general or sub_mb_type or mbPartIdx or subMbPartIdx or compIdx + or MBTypeGen_mbAddrA[1] or MBTypeGen_mbAddrB[1] or MBTypeGen_mbAddrC[1] or MBTypeGen_mbAddrD + or mvy_mbAddrA or mvy_mbAddrB_dout or mvy_mbAddrC_dout or mvy_mbAddrD + or mvy_CurrMb0 or mvy_CurrMb1 or mvy_CurrMb2 or mvy_CurrMb3 + or refIdxL0_A or refIdxL0_B or refIdxL0_C) + //P_skip,Inter16x16 + if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1)) + begin + if (mb_num == 0) mvpCy <= 0; + else if (mb_num_v == 0) mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0]; + else if (mb_num_h == 10) mvpCy <= (MBTypeGen_mbAddrD == 1)? 0:mvy_mbAddrD; + else mvpCy <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvy_mbAddrC_dout; + end + //Inter16x8 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1) + begin + if (mbPartIdx == 0) + mvpCy <= (refIdxL0_B && !refIdxL0_C)? ((mb_num_h == 10)? mvy_mbAddrD:mvy_mbAddrC_dout):0; + else + mvpCy <= 0; + end + //Inter8x16 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 1) + begin + //when mbAddrA is not available,Inter8x16 left blk needs to have its mbAddrC (= mbAddrB of upper line) derived + if (mbPartIdx == 0) //left blk + mvpCy <= (refIdxL0_A && !refIdxL0_B)? mvy_mbAddrB_dout[15:8]:0; + else //right blk + begin + if (mb_num == 0) mvpCy <= 0; + else if (mb_num_v == 0) mvpCy <= mvy_CurrMb0[15:8]; + else if (mb_num_h == 10) mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16]; + else mvpCy <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvy_mbAddrC_dout; + end + end + //Inter8x8 + else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1) + case (mbPartIdx) + 0: + case (sub_mb_type) + 0:if (mb_num == 0) mvpCy <= 0; + else if (mb_num_v == 0) mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0]; + else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]; + 1: //8x4 + case (subMbPartIdx) + 0:if (mb_num == 0) mvpCy <= 0; + else if (mb_num_v == 0) mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0]; + else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]; + 1:if (mb_num_h == 0) mvpCy <= 0; + else mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrD; + default:mvpCy <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:if (mb_num == 0) mvpCy <= 0; + else if (mb_num_v == 0) mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0]; + else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16]; + 1:if (mb_num_v == 0) mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_CurrMb0[7:0]; + else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]; + default:mvpCy <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:if (mb_num == 0) mvpCy <= 0; + else if (mb_num_v == 0) mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0]; + else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16]; + 1:if (mb_num_v == 0) mvpCy <= mvy_CurrMb0[7:0]; + else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]; + 2:mvpCy <= mvy_CurrMb0[15:8]; //always available + 3:mvpCy <= mvy_CurrMb0[7:0]; //always from D + endcase + endcase + 1: + case (sub_mb_type) + 0:if (mb_num_v == 0) mvpCy <= mvy_CurrMb0[15:8]; + else if (mb_num_h == 10) //predicted from D,but lies initial mbAddrB + mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16]; + else mvpCy <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvy_mbAddrC_dout; + 1: //8x4 + case (subMbPartIdx) + 0:if (mb_num_v == 0) mvpCy <= mvy_CurrMb0[15:8]; + else if (mb_num_h == 10) //predicted from D,but lies initial mbAddrB + mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16]; + else mvpCy <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvy_mbAddrC_dout; + 1:mvpCy <= mvy_CurrMb0[15:8]; //C is always unavailable,D is always available + default:mvpCy <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:if (mb_num_v == 0) mvpCy <= mvy_CurrMb0[15:8]; + else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[7:0]; + 1:if (mb_num_v == 0) mvpCy <= mvy_CurrMb1[7:0]; + else if (mb_num_h == 10) //predicted from D,but lies in mbAddrB + mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]; + else mvpCy <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvy_mbAddrC_dout; + default:mvpCy <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:if (mb_num_v == 0) mvpCy <= mvy_CurrMb0[15:8]; + else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[7:0]; + 1:if (mb_num_v == 0) mvpCy <= mvy_CurrMb1[7:0]; + else if (mb_num_h == 10) //predicted from D,but lies initial mbAddrB + mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]; + else mvpCy <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvy_mbAddrC_dout; + 2:mvpCy <= mvy_CurrMb1[15:8]; + 3:mvpCy <= mvy_CurrMb1[7:0]; + endcase + endcase + 2: + case (sub_mb_type) + 0:mvpCy <= mvy_CurrMb1[23:16]; + 1: //8x4 + case (subMbPartIdx) + 0:mvpCy <= mvy_CurrMb1[23:16]; + 1:if (mb_num_h == 0) mvpCy <= 0; + else mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrD; + default:mvpCy <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:mvpCy <= mvy_CurrMb0[31:24]; 1:mvpCy <= mvy_CurrMb1[23:16]; default:mvpCy <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvpCy <= mvy_CurrMb0[31:24]; 1:mvpCy <= mvy_CurrMb1[23:16]; + 2:mvpCy <= mvy_CurrMb2[15:8]; 3:mvpCy <= mvy_CurrMb2[7:0]; + endcase + endcase + 3: + case (sub_mb_type) + 0:mvpCy <= mvy_CurrMb0[31:24]; + 1: //8x4 + case (subMbPartIdx) + 0:mvpCy <= mvy_CurrMb0[31:24]; 1:mvpCy <= mvy_CurrMb2[15:8]; default:mvpCy <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:mvpCy <= mvy_CurrMb1[31:24]; 1:mvpCy <= mvy_CurrMb1[23:16]; default:mvpCy <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvpCy <= mvy_CurrMb1[31:24]; 1:mvpCy <= mvy_CurrMb1[23:16]; + 2:mvpCy <= mvy_CurrMb3[15:8]; 3:mvpCy <= mvy_CurrMb3[7:0]; + endcase + endcase + endcase + else + mvpCy <= 0; + //------------------------------------------------ + //obtain motion vector prediction for current Blk + //------------------------------------------------ + wire [8:0] sub_ABx,sub_ACx,sub_BCx; + wire flag_ABx,flag_ACx,flag_BCx; + assign sub_ABx = {mvpAx[7],mvpAx[7:0]} - {mvpBx[7],mvpBx[7:0]}; + assign sub_ACx = {mvpAx[7],mvpAx[7:0]} - {mvpCx[7],mvpCx[7:0]}; + assign sub_BCx = {mvpBx[7],mvpBx[7:0]} - {mvpCx[7],mvpCx[7:0]}; + assign flag_ABx = sub_ABx[8]; + assign flag_ACx = sub_ACx[8]; + assign flag_BCx = sub_BCx[8]; + + reg [7:0] mvpx_median; + always @ (flag_ABx or flag_ACx or flag_BCx or mvpAx or mvpBx or mvpCx) + if (((flag_ABx == 1'b1) && (flag_ACx == 1'b0)) || ((flag_ABx == 1'b0) && (flag_ACx == 1'b1))) + mvpx_median <= mvpAx; + else if (((flag_ABx == 1'b0) && (flag_BCx == 1'b0)) || ((flag_ABx == 1'b1) && (flag_BCx == 1'b1))) + mvpx_median <= mvpBx; + else + mvpx_median <= mvpCx; + + always @ (refIdxL0_A or refIdxL0_B or refIdxL0_C or mvpAx or mvpBx or mvpCx or mvpx_median) + case ({refIdxL0_A,refIdxL0_B,refIdxL0_C}) + 3'b011:mvpx <= mvpAx; + 3'b101:mvpx <= mvpBx; + 3'b110:mvpx <= mvpCx; + default:mvpx <= mvpx_median; + endcase + + wire [8:0] sub_ABy,sub_ACy,sub_BCy; + wire flag_ABy,flag_ACy,flag_BCy; + assign sub_ABy = {mvpAy[7],mvpAy[7:0]} - {mvpBy[7],mvpBy[7:0]}; + assign sub_ACy = {mvpAy[7],mvpAy[7:0]} - {mvpCy[7],mvpCy[7:0]}; + assign sub_BCy = {mvpBy[7],mvpBy[7:0]} - {mvpCy[7],mvpCy[7:0]}; + assign flag_ABy = sub_ABy[8]; + assign flag_ACy = sub_ACy[8]; + assign flag_BCy = sub_BCy[8]; + + reg [7:0] mvpy_median; + always @ (flag_ABy or flag_ACy or flag_BCy or mvpAy or mvpBy or mvpCy) + if (((flag_ABy == 1'b1) && (flag_ACy == 1'b0)) || ((flag_ABy == 1'b0) && (flag_ACy == 1'b1))) + mvpy_median <= mvpAy; + else if (((flag_ABy == 1'b0) && (flag_BCy == 1'b0)) || ((flag_ABy == 1'b1) && (flag_BCy == 1'b1))) + mvpy_median <= mvpBy; + else + mvpy_median <= mvpCy; + + always @ (refIdxL0_A or refIdxL0_B or refIdxL0_C or mvpAy or mvpBy or mvpCy or mvpy_median) + case ({refIdxL0_A,refIdxL0_B,refIdxL0_C}) + 3'b011:mvpy <= mvpAy; + 3'b101:mvpy <= mvpBy; + 3'b110:mvpy <= mvpCy; + default:mvpy <= mvpy_median; + endcase + + always @ (Is_skipMB_mv_calc or mb_num_h or mb_num_v or mb_pred_state or sub_mb_pred_state or compIdx or mvpx or mvpy + or mvd or mvpAx or mvpBx or mvpCx or mvpAy or mvpBy or mvpCy or mb_type_general or mbPartIdx + or refIdxL0_A or refIdxL0_B or refIdxL0_C) + if (Is_skipMB_mv_calc) + begin + //Refer to Page113,section 8.4.1.1 of H.264/AVC 2003.05 standard + if (mb_num_h == 0 || mb_num_v == 0 || (refIdxL0_A == 0 && mvpAx == 0 && mvpAy == 0) || + (refIdxL0_B == 0 && mvpBx == 0 && mvpBy == 0)) + begin mvx <= 0; mvy <= 0; end + else + begin mvx <= mvpx; mvy <= mvpy; end + end + else if (mb_pred_state == `mvd_l0_s || sub_mb_pred_state == `sub_mvd_l0_s) + begin + if (mb_type_general == `MB_Inter16x8) //16x8 + case (mbPartIdx) + 2'b00: //upper blk + if (!refIdxL0_B) + begin + mvx <= (compIdx == 0)? (mvpBx + mvd):0; + mvy <= (compIdx == 1)? (mvpBy + mvd):0; + end + else + begin + mvx <= (compIdx == 0)? (mvpx + mvd):0; + mvy <= (compIdx == 1)? (mvpy + mvd):0; + end + default: //bottom blk + if (!refIdxL0_A) + begin + mvx <= (compIdx == 0)? (mvpAx + mvd):0; + mvy <= (compIdx == 1)? (mvpAy + mvd):0; + end + else + begin + mvx <= (compIdx == 0)? (mvpx + mvd):0; + mvy <= (compIdx == 1)? (mvpy + mvd):0; + end + endcase + else if (mb_type_general == `MB_Inter8x16) //8x16 + case (mbPartIdx) + 2'b00: //left blk + if (!refIdxL0_A) + begin + mvx <= (compIdx == 0)? (mvpAx + mvd):0; + mvy <= (compIdx == 1)? (mvpAy + mvd):0; + end + else + begin + mvx <= (compIdx == 0)? (mvpx + mvd):0; + mvy <= (compIdx == 1)? (mvpy + mvd):0; + end + default: //right blk + //if mbAddrC is not available but mbAddrB (= mbAddrD) is INTER available (not only available,but also inter + //available),it still predicted from mbAddrC <- mbAddrD + if (!refIdxL0_C || (mb_num_h == 10 && !refIdxL0_B)) + begin + mvx <= (compIdx == 0)? (mvpCx + mvd):0; + mvy <= (compIdx == 1)? (mvpCy + mvd):0; + end + else + begin + mvx <= (compIdx == 0)? (mvpx + mvd):0; + mvy <= (compIdx == 1)? (mvpy + mvd):0; + end + endcase + else + begin + mvx <= (compIdx == 0)? (mvpx + mvd):0; + mvy <= (compIdx == 1)? (mvpy + mvd):0; + end + end + else + begin + mvx <= 0; mvy <= 0; + end + //----------------------------------------------------- + //Current MB write --> CurrMb0,CurrMb1,CurrMb2,CurrMb3 + //----------------------------------------------------- + always @ (posedge clk) + if (reset_n == 0) + mv_is16x16 <= 0; + else if (mb_type_general == `MB_Inter16x16 || mb_type_general == `MB_P_skip) + mv_is16x16 <= 1; + else + mv_is16x16 <= 0; + + always @ (posedge clk) + if (reset_n == 0) + begin + mvx_CurrMb0 <= 0; mvx_CurrMb1 <= 0; mvx_CurrMb2 <= 0; mvx_CurrMb3 <= 0; + end + //Inter16x16 or P_skip + else if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0)) + mvx_CurrMb0[7:0] <= mvx; + //Inter16x8 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0) + case (mbPartIdx) + 0:begin mvx_CurrMb0 <= {mvx,mvx,mvx,mvx}; mvx_CurrMb1 <= {mvx,mvx,mvx,mvx}; end + 1:begin mvx_CurrMb2 <= {mvx,mvx,mvx,mvx}; mvx_CurrMb3 <= {mvx,mvx,mvx,mvx}; end + endcase + //Inter8x16 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 0) + case (mbPartIdx) + 0:begin mvx_CurrMb0 <= {mvx,mvx,mvx,mvx}; mvx_CurrMb2 <= {mvx,mvx,mvx,mvx}; end + 1:begin mvx_CurrMb1 <= {mvx,mvx,mvx,mvx}; mvx_CurrMb3 <= {mvx,mvx,mvx,mvx}; end + endcase + //Inter8x8 + else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0) + case (mbPartIdx) + 0: + case (sub_mb_type) + 0:mvx_CurrMb0 <= {mvx,mvx,mvx,mvx}; + 1: //8x4 + case (subMbPartIdx) + 0:begin mvx_CurrMb0[7:0] <= mvx; mvx_CurrMb0[15:8] <= mvx; end + 1:begin mvx_CurrMb0[23:16] <= mvx; mvx_CurrMb0[31:24] <= mvx; end + endcase + 2: //4x8 + case (subMbPartIdx) + 0:begin mvx_CurrMb0[7:0] <= mvx; mvx_CurrMb0[23:16] <= mvx; end + 1:begin mvx_CurrMb0[15:8] <= mvx; mvx_CurrMb0[31:24] <= mvx; end + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvx_CurrMb0[7:0] <= mvx; + 1:mvx_CurrMb0[15:8] <= mvx; + 2:mvx_CurrMb0[23:16] <= mvx; + 3:mvx_CurrMb0[31:24] <= mvx; + endcase + endcase + 1: + case (sub_mb_type) + 0:mvx_CurrMb1 <= {mvx,mvx,mvx,mvx}; + 1: //8x4 + case (subMbPartIdx) + 0:begin mvx_CurrMb1[7:0] <= mvx; mvx_CurrMb1[15:8] <= mvx; end + 1:begin mvx_CurrMb1[23:16] <= mvx; mvx_CurrMb1[31:24] <= mvx; end + endcase + 2: //4x8 + case (subMbPartIdx) + 0:begin mvx_CurrMb1[7:0] <= mvx; mvx_CurrMb1[23:16] <= mvx; end + 1:begin mvx_CurrMb1[15:8] <= mvx; mvx_CurrMb1[31:24] <= mvx; end + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvx_CurrMb1[7:0] <= mvx; + 1:mvx_CurrMb1[15:8] <= mvx; + 2:mvx_CurrMb1[23:16] <= mvx; + 3:mvx_CurrMb1[31:24] <= mvx; + endcase + endcase + 2: + case (sub_mb_type) + 0:mvx_CurrMb2 <= {mvx,mvx,mvx,mvx}; + 1: //8x4 + case (subMbPartIdx) + 0:begin mvx_CurrMb2[7:0] <= mvx; mvx_CurrMb2[15:8] <= mvx; end + 1:begin mvx_CurrMb2[23:16] <= mvx; mvx_CurrMb2[31:24] <= mvx; end + endcase + 2: //4x8 + case (subMbPartIdx) + 0:begin mvx_CurrMb2[7:0] <= mvx; mvx_CurrMb2[23:16] <= mvx; end + 1:begin mvx_CurrMb2[15:8] <= mvx; mvx_CurrMb2[31:24] <= mvx; end + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvx_CurrMb2[7:0] <= mvx; + 1:mvx_CurrMb2[15:8] <= mvx; + 2:mvx_CurrMb2[23:16] <= mvx; + 3:mvx_CurrMb2[31:24] <= mvx; + endcase + endcase + 3: + case (sub_mb_type) + 0:mvx_CurrMb3 <= {mvx,mvx,mvx,mvx}; + 1: //8x4 + case (subMbPartIdx) + 0:begin mvx_CurrMb3[7:0] <= mvx; mvx_CurrMb3[15:8] <= mvx; end + 1:begin mvx_CurrMb3[23:16] <= mvx; mvx_CurrMb3[31:24] <= mvx; end + endcase + 2: //4x8 + case (subMbPartIdx) + 0:begin mvx_CurrMb3[7:0] <= mvx; mvx_CurrMb3[23:16] <= mvx; end + 1:begin mvx_CurrMb3[15:8] <= mvx; mvx_CurrMb3[31:24] <= mvx; end + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvx_CurrMb3[7:0] <= mvx; + 1:mvx_CurrMb3[15:8] <= mvx; + 2:mvx_CurrMb3[23:16] <= mvx; + 3:mvx_CurrMb3[31:24] <= mvx; + endcase + endcase + endcase + always @ (posedge clk) + if (reset_n == 0) + begin + mvy_CurrMb0 <= 0; mvy_CurrMb1 <= 0; mvy_CurrMb2 <= 0; mvy_CurrMb3 <= 0; + end + //Inter16x16 or P_skip + else if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1)) + begin + mvy_CurrMb0[7:0] <= mvy; + end + //Inter16x8 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1) + case (mbPartIdx) + 0:begin mvy_CurrMb0 <= {mvy,mvy,mvy,mvy}; mvy_CurrMb1 <= {mvy,mvy,mvy,mvy}; end + 1:begin mvy_CurrMb2 <= {mvy,mvy,mvy,mvy}; mvy_CurrMb3 <= {mvy,mvy,mvy,mvy}; end + endcase + //Inter8x16 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 1) + case (mbPartIdx) + 0:begin mvy_CurrMb0 <= {mvy,mvy,mvy,mvy}; mvy_CurrMb2 <= {mvy,mvy,mvy,mvy}; end + 1:begin mvy_CurrMb1 <= {mvy,mvy,mvy,mvy}; mvy_CurrMb3 <= {mvy,mvy,mvy,mvy}; end + endcase + //Inter8x8 + else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1) + case (mbPartIdx) + 0: + case (sub_mb_type) + 0:mvy_CurrMb0 <= {mvy,mvy,mvy,mvy}; + 1: //8x4 + case (subMbPartIdx) + 0:begin mvy_CurrMb0[7:0] <= mvy; mvy_CurrMb0[15:8] <= mvy; end + 1:begin mvy_CurrMb0[23:16] <= mvy; mvy_CurrMb0[31:24] <= mvy; end + endcase + 2: //4x8 + case (subMbPartIdx) + 0:begin mvy_CurrMb0[7:0] <= mvy; mvy_CurrMb0[23:16] <= mvy; end + 1:begin mvy_CurrMb0[15:8] <= mvy; mvy_CurrMb0[31:24] <= mvy; end + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvy_CurrMb0[7:0] <= mvy; + 1:mvy_CurrMb0[15:8] <= mvy; + 2:mvy_CurrMb0[23:16] <= mvy; + 3:mvy_CurrMb0[31:24] <= mvy; + endcase + endcase + 1: + case (sub_mb_type) + 0:mvy_CurrMb1 <= {mvy,mvy,mvy,mvy}; + 1: //8x4 + case (subMbPartIdx) + 0:begin mvy_CurrMb1[7:0] <= mvy; mvy_CurrMb1[15:8] <= mvy; end + 1:begin mvy_CurrMb1[23:16] <= mvy; mvy_CurrMb1[31:24] <= mvy; end + endcase + 2: //4x8 + case (subMbPartIdx) + 0:begin mvy_CurrMb1[7:0] <= mvy; mvy_CurrMb1[23:16] <= mvy; end + 1:begin mvy_CurrMb1[15:8] <= mvy; mvy_CurrMb1[31:24] <= mvy; end + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvy_CurrMb1[7:0] <= mvy; + 1:mvy_CurrMb1[15:8] <= mvy; + 2:mvy_CurrMb1[23:16] <= mvy; + 3:mvy_CurrMb1[31:24] <= mvy; + endcase + endcase + 2: + case (sub_mb_type) + 0:mvy_CurrMb2 <= {mvy,mvy,mvy,mvy}; + 1: //8x4 + case (subMbPartIdx) + 0:begin mvy_CurrMb2[7:0] <= mvy; mvy_CurrMb2[15:8] <= mvy; end + 1:begin mvy_CurrMb2[23:16] <= mvy; mvy_CurrMb2[31:24] <= mvy; end + endcase + 2: //4x8 + case (subMbPartIdx) + 0:begin mvy_CurrMb2[7:0] <= mvy; mvy_CurrMb2[23:16] <= mvy; end + 1:begin mvy_CurrMb2[15:8] <= mvy; mvy_CurrMb2[31:24] <= mvy; end + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvy_CurrMb2[7:0] <= mvy; + 1:mvy_CurrMb2[15:8] <= mvy; + 2:mvy_CurrMb2[23:16] <= mvy; + 3:mvy_CurrMb2[31:24] <= mvy; + endcase + endcase + 3: + case (sub_mb_type) + 0:mvy_CurrMb3 <= {mvy,mvy,mvy,mvy}; + 1: //8x4 + case (subMbPartIdx) + 0:begin mvy_CurrMb3[7:0] <= mvy; mvy_CurrMb3[15:8] <= mvy; end + 1:begin mvy_CurrMb3[23:16] <= mvy; mvy_CurrMb3[31:24] <= mvy; end + endcase + 2: //4x8 + case (subMbPartIdx) + 0:begin mvy_CurrMb3[7:0] <= mvy; mvy_CurrMb3[23:16] <= mvy; end + 1:begin mvy_CurrMb3[15:8] <= mvy; mvy_CurrMb3[31:24] <= mvy; end + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvy_CurrMb3[7:0] <= mvy; + 1:mvy_CurrMb3[15:8] <= mvy; + 2:mvy_CurrMb3[23:16] <= mvy; + 3:mvy_CurrMb3[31:24] <= mvy; + endcase + endcase + endcase + //---------------------------- + //mbAddrA write --> mvx_mbAddrA + //---------------------------- + always @ (posedge clk) + if (reset_n == 0) + mvx_mbAddrA <= 0; + else if (mb_num_h != 10)//if mb_num_h == 10,mvx_mbAddrA will be no use + begin + //P_skip + if (slice_data_state == `skip_run_duration && end_of_MB_DEC) + mvx_mbAddrA <= {mvx_CurrMb0[7:0],mvx_CurrMb0[7:0],mvx_CurrMb0[7:0],mvx_CurrMb0[7:0]}; + //Inter16x16 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0) + mvx_mbAddrA <= {mvx,mvx,mvx,mvx}; + //Inter16x8 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0) + case (mbPartIdx) + 0:begin mvx_mbAddrA[15:8] <= mvx; mvx_mbAddrA[7:0] <= mvx; end + 1:begin mvx_mbAddrA[23:16] <= mvx; mvx_mbAddrA[31:24] <= mvx; end + endcase + //Inter8x16 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && mbPartIdx == 1 && compIdx == 0) + mvx_mbAddrA <= {mvx,mvx,mvx,mvx}; + //Inter8x8 + else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0) + case (mbPartIdx) + 1: + case (sub_mb_type) + 0:begin mvx_mbAddrA[15:8] <= mvx; mvx_mbAddrA[7:0] <= mvx; end + 1:if (subMbPartIdx == 0) mvx_mbAddrA[7:0] <= mvx; + else mvx_mbAddrA[15:8] <= mvx; + 2:if (subMbPartIdx == 1) begin mvx_mbAddrA[15:8] <= mvx; mvx_mbAddrA[7:0] <= mvx;end + 3:if (subMbPartIdx == 1) mvx_mbAddrA[7:0] <= mvx; + else if (subMbPartIdx == 3) mvx_mbAddrA[15:8] <= mvx; + endcase + 3: + case (sub_mb_type) + 0:begin mvx_mbAddrA[23:16] <= mvx; mvx_mbAddrA[31:24] <= mvx; end + 1:if (subMbPartIdx == 0) mvx_mbAddrA[23:16] <= mvx; + else mvx_mbAddrA[31:24] <= mvx; + 2:if (subMbPartIdx == 1) begin mvx_mbAddrA[23:16] <= mvx; mvx_mbAddrA[31:24] <= mvx;end + 3:if (subMbPartIdx == 1) mvx_mbAddrA[23:16] <= mvx; + else if (subMbPartIdx == 3) mvx_mbAddrA[31:24] <= mvx; + endcase + endcase + end + always @ (posedge clk) + if (reset_n == 0) + mvy_mbAddrA <= 0; + else if (mb_num_h != 10)//if mb_num_h == 10,mvy_mbAddrA will be no use + begin + //P_skip + if (slice_data_state == `skip_run_duration && end_of_MB_DEC) + mvy_mbAddrA <= {mvy_CurrMb0[7:0],mvy_CurrMb0[7:0],mvy_CurrMb0[7:0],mvy_CurrMb0[7:0]}; + //Inter16x16 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1) + mvy_mbAddrA <= {mvy,mvy,mvy,mvy}; + //Inter16x8 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1) + case (mbPartIdx) + 0:begin mvy_mbAddrA[15:8] <= mvy; mvy_mbAddrA[7:0] <= mvy; end + 1:begin mvy_mbAddrA[23:16] <= mvy; mvy_mbAddrA[31:24] <= mvy; end + endcase + //Inter8x16 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && mbPartIdx == 1 && compIdx == 1) + mvy_mbAddrA <= {mvy,mvy,mvy,mvy}; + //Inter8x8 + else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1) + case (mbPartIdx) + 1: + case (sub_mb_type) + 0:begin mvy_mbAddrA[15:8] <= mvy; mvy_mbAddrA[7:0] <= mvy; end + 1:if (subMbPartIdx == 0) mvy_mbAddrA[7:0] <= mvy; + else mvy_mbAddrA[15:8] <= mvy; + 2:if (subMbPartIdx == 1) begin mvy_mbAddrA[15:8] <= mvy; mvy_mbAddrA[7:0] <= mvy;end + 3:if (subMbPartIdx == 1) mvy_mbAddrA[7:0] <= mvy; + else if (subMbPartIdx == 3) mvy_mbAddrA[15:8] <= mvy; + endcase + 3: + case (sub_mb_type) + 0:begin mvy_mbAddrA[23:16] <= mvy; mvy_mbAddrA[31:24] <= mvy; end + 1:if (subMbPartIdx == 0) mvy_mbAddrA[23:16] <= mvy; + else mvy_mbAddrA[31:24] <= mvy; + 2:if (subMbPartIdx == 1) begin mvy_mbAddrA[23:16] <= mvy; mvy_mbAddrA[31:24] <= mvy;end + 3:if (subMbPartIdx == 1) mvy_mbAddrA[23:16] <= mvy; + else if (subMbPartIdx == 3) mvy_mbAddrA[31:24] <= mvy; + endcase + endcase + end + //----------------------------------------- + //mbAddrB RF read and write --> mvx_mbAddrB + //----------------------------------------- + always @ (reset_n or slice_data_state or mb_pred_state or sub_mb_pred_state or mv_mbAddrB_rd_for_DF + or Is_skipMB_mv_calc or end_of_MB_DEC or mb_type_general or sub_mb_type or mb_num_h or mb_num_v + or mbPartIdx or subMbPartIdx or compIdx or mvx or mvx_CurrMb0[7:0] or mvx_CurrMb2 or mvx_CurrMb3 + or refIdxL0_A or refIdxL0_C) + if (reset_n == 0) + begin + mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; + mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + //read for DF boundary strength decoding + else if (mv_mbAddrB_rd_for_DF) + begin + mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_rd_addr <= mb_num_h; + mvx_mbAddrB_wr_n <= 1; mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + //P_skip + else if (slice_data_state == `skip_run_duration) + begin + if (Is_skipMB_mv_calc) //read + begin + if (mb_num_v == 0) + begin mvx_mbAddrB_cs_n <= 1;mvx_mbAddrB_rd_addr <= 0; end + else + begin mvx_mbAddrB_cs_n <= 0;mvx_mbAddrB_rd_addr <= mb_num_h;end + mvx_mbAddrB_wr_n <= 1; + mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + else if (end_of_MB_DEC) //write + begin + if (mb_num_v == 8) + begin + mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; + mvx_mbAddrB_wr_addr <= 0; mvx_mbAddrB_din <= 0; + end + else + begin + mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0; + mvx_mbAddrB_wr_addr <= mb_num_h; + mvx_mbAddrB_din <= {mvx_CurrMb0[7:0],mvx_CurrMb0[7:0],mvx_CurrMb0[7:0],mvx_CurrMb0[7:0]}; + end + mvx_mbAddrB_rd_addr <= 0; + end + else + begin + mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; + mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + end + //Inter16x16 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0) + begin + if (mb_num_v == 0) //!read,write + begin + mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0; + mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= mb_num_h; + mvx_mbAddrB_din <= {mvx,mvx,mvx,mvx}; + end + else if (mb_num_v == 8) //read,!write + begin + mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_rd_addr <= mb_num_h; + mvx_mbAddrB_wr_n <= 1; mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + else //read,write + begin + mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_rd_addr <= mb_num_h; + mvx_mbAddrB_wr_n <= 0; mvx_mbAddrB_wr_addr <= mb_num_h; + mvx_mbAddrB_din <= {mvx,mvx,mvx,mvx}; + end + end + //Inter16x8 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0) + case (mbPartIdx) + 0: //read,!write + begin + if (mb_num_v == 0) //!read,!write + begin + mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; + mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + else //read,!write + begin + mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 1; + mvx_mbAddrB_rd_addr <= mb_num_h; mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + end + 1: //!read,write + begin + if (mb_num_v == 8) //!read,!write + begin + mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_rd_addr <= mb_num_h; + mvx_mbAddrB_wr_n <= 1; mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + else //!read,write + begin + mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0; + mvx_mbAddrB_rd_addr <= mb_num_h; mvx_mbAddrB_wr_addr <= mb_num_h; + mvx_mbAddrB_din <= {mvx,mvx,mvx,mvx}; + end + end + default: + begin + mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; + mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + endcase + //Inter8x16 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 0) + case (mbPartIdx) + 0: //read when mbAddrA is not available for inter pred,!write + if (refIdxL0_A == 1'b1) + begin + mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 1; + mvx_mbAddrB_rd_addr <= mb_num_h;mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + else + begin + mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; + mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + 1: //need read :mb_num_h == 10 && mb_num_v != 0 + //need write:mb_num_v != 8 + begin + mvx_mbAddrB_cs_n <= ((mb_num_v != 8 || mb_num_h == 10) || (refIdxL0_C && mb_num_v != 0))? 1'b0:1'b1; + mvx_mbAddrB_wr_n <= (mb_num_v == 8)? 1'b1:1'b0; + mvx_mbAddrB_rd_addr <= mb_num_h; + mvx_mbAddrB_wr_addr <= mb_num_h; + mvx_mbAddrB_din <= {mvx_CurrMb2[23:16],mvx_CurrMb2[31:24],mvx,mvx}; + end + default: + begin + mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; + mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + endcase + //8x8 + else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0) + case (mbPartIdx) + 0,1: //read,!write + if (mb_num_v == 0) //!read,!write + begin + mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; + mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + else //read,!write + begin + mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 1; + mvx_mbAddrB_rd_addr <= mb_num_h; mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + 2: //!read,!write + begin + mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; + mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + 3: //!read,write + if (mb_num_v == 8) //!read,!write + begin + mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; + mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + else + case (sub_mb_type) + 0: //8x8 + begin + mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0; + mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= mb_num_h; + mvx_mbAddrB_din <= {mvx_CurrMb2[23:16],mvx_CurrMb2[31:24],mvx,mvx}; + end + 1: //8x4 + case (subMbPartIdx) + 1: + begin + mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0; + mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= mb_num_h; + mvx_mbAddrB_din <= {mvx_CurrMb2[23:16],mvx_CurrMb2[31:24],mvx,mvx}; + end + default: + begin + mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; + mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + endcase + 2: //4x8 + case (subMbPartIdx) + 1: + begin + mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0; + mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= mb_num_h; + mvx_mbAddrB_din <= {mvx_CurrMb2[23:16],mvx_CurrMb2[31:24],mvx_CurrMb3[23:16],mvx}; + end + default: + begin + mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; + mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + endcase + 3: //4x4 + case (subMbPartIdx) + 3: + begin + mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0; + mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= mb_num_h; + mvx_mbAddrB_din <= {mvx_CurrMb2[23:16],mvx_CurrMb2[31:24], + mvx_CurrMb3[23:16],mvx}; + end + default: + begin + mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; + mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + endcase + endcase + endcase + else + begin + mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; + mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + + always @ (reset_n or slice_data_state or mb_pred_state or sub_mb_pred_state or mv_mbAddrB_rd_for_DF + or Is_skipMB_mv_calc or end_of_MB_DEC or mb_type_general or sub_mb_type or mb_num_h or mb_num_v + or mbPartIdx or subMbPartIdx or compIdx or mvy or mvy_CurrMb0[7:0] or mvy_CurrMb2 or mvy_CurrMb3 + or refIdxL0_A or refIdxL0_C) + if (reset_n == 0) + begin + mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; + mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + //read for DF boundary strength decoding + else if (mv_mbAddrB_rd_for_DF) + begin + mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_rd_addr <= mb_num_h; + mvy_mbAddrB_wr_n <= 1; mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + //P_skip + else if (slice_data_state == `skip_run_duration) + begin + if (Is_skipMB_mv_calc) //read + begin + if (mb_num_v == 0) + begin mvy_mbAddrB_cs_n <= 1;mvy_mbAddrB_rd_addr <= 0; end + else + begin mvy_mbAddrB_cs_n <= 0;mvy_mbAddrB_rd_addr <= mb_num_h;end + mvy_mbAddrB_wr_n <= 1; + mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + else if (end_of_MB_DEC) //write + begin + if (mb_num_v == 8) + begin + mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; + mvy_mbAddrB_wr_addr <= 0; mvy_mbAddrB_din <= 0; + end + else + begin + mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0; + mvy_mbAddrB_wr_addr <= mb_num_h; + mvy_mbAddrB_din <= {mvy_CurrMb0[7:0],mvy_CurrMb0[7:0],mvy_CurrMb0[7:0],mvy_CurrMb0[7:0]}; + end + mvy_mbAddrB_rd_addr <= 0; + end + else + begin + mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; + mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + end + //Inter16x16 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1) + begin + if (mb_num_v == 0) //!read,write + begin + mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0; + mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= mb_num_h; + mvy_mbAddrB_din <= {mvy,mvy,mvy,mvy}; + end + else if (mb_num_v == 8) //read,!write + begin + mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_rd_addr <= mb_num_h; + mvy_mbAddrB_wr_n <= 1; mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + else //read,write + begin + mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_rd_addr <= mb_num_h; + mvy_mbAddrB_wr_n <= 0; mvy_mbAddrB_wr_addr <= mb_num_h; + mvy_mbAddrB_din <= {mvy,mvy,mvy,mvy}; + end + end + //Inter16x8 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1) + case (mbPartIdx) + 0: //read,!write + begin + if (mb_num_v == 0) //!read,!write + begin + mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; + mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + else //read,!write + begin + mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 1; + mvy_mbAddrB_rd_addr <= mb_num_h; mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + end + 1: //!read,write + begin + if (mb_num_v == 8) //!read,!write + begin + mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_rd_addr <= mb_num_h; + mvy_mbAddrB_wr_n <= 1; mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + else //!read,write + begin + mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0; + mvy_mbAddrB_rd_addr <= mb_num_h; mvy_mbAddrB_wr_addr <= mb_num_h; + mvy_mbAddrB_din <= {mvy,mvy,mvy,mvy}; + end + end + default: + begin + mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; + mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + endcase + //Inter8x16 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 1) + case (mbPartIdx) + 0: //read when mbAddrA is not available for inter pred,!write + if (refIdxL0_A == 1'b1) + begin + mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 1; + mvy_mbAddrB_rd_addr <= mb_num_h;mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + else + begin + mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; + mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + 1: //need read :mb_num_h == 10 && mb_num_v != 0 + //need write:mb_num_v != 8 + begin + mvy_mbAddrB_cs_n <= ((mb_num_v != 8 || mb_num_h == 10) || (refIdxL0_C && mb_num_v != 0))? 1'b0:1'b1; + mvy_mbAddrB_wr_n <= (mb_num_v == 8)? 1'b1:1'b0; + mvy_mbAddrB_rd_addr <= mb_num_h; + mvy_mbAddrB_wr_addr <= mb_num_h; + mvy_mbAddrB_din <= {mvy_CurrMb2[23:16],mvy_CurrMb2[31:24],mvy,mvy}; + end + default: + begin + mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; + mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + endcase + //8x8 + else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1) + case (mbPartIdx) + 0,1: //read,!write + if (mb_num_v == 0) //!read,!write + begin + mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; + mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + else //read,!write + begin + mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 1; + mvy_mbAddrB_rd_addr <= mb_num_h; mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + 2: //!read,!write + begin + mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; + mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + 3: //!read,write + if (mb_num_v == 8) //!read,!write + begin + mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; + mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + else + case (sub_mb_type) + 0: //8x8 + begin + mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0; + mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= mb_num_h; + mvy_mbAddrB_din <= {mvy_CurrMb2[23:16],mvy_CurrMb2[31:24],mvy,mvy}; + end + 1: //8x4 + case (subMbPartIdx) + 1: + begin + mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0; + mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= mb_num_h; + mvy_mbAddrB_din <= {mvy_CurrMb2[23:16],mvy_CurrMb2[31:24],mvy,mvy}; + end + default: + begin + mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; + mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + endcase + 2: //4x8 + case (subMbPartIdx) + 1: + begin + mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0; + mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= mb_num_h; + mvy_mbAddrB_din <= {mvy_CurrMb2[23:16],mvy_CurrMb2[31:24],mvy_CurrMb3[23:16],mvy}; + end + default: + begin + mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; + mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + endcase + 3: //4x4 + case (subMbPartIdx) + 3: + begin + mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0; + mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= mb_num_h; + mvy_mbAddrB_din <= {mvy_CurrMb2[23:16],mvy_CurrMb2[31:24], + mvy_CurrMb3[23:16],mvy}; + end + default: + begin + mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; + mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + endcase + endcase + endcase + else + begin + mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; + mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + //----------------------------------------- + //mbAddrC RF read and write --> mvx_mbAddrC + //----------------------------------------- + always @ (reset_n or slice_data_state or Is_skipMB_mv_calc or end_of_MB_DEC or mb_pred_state or sub_mb_type or sub_mb_pred_state + or mb_type_general or mb_num or mb_num_h or mb_num_v or mbPartIdx or subMbPartIdx or compIdx or mvx or mvx_CurrMb0[7:0] + or refIdxL0_B or refIdxL0_C) + if (reset_n == 0) + begin + mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + //P_skip + else if (slice_data_state == `skip_run_duration) + begin + if (Is_skipMB_mv_calc) //read + begin + if (mb_num_v == 0 || mb_num_h == 10)//!read,!write + begin mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_rd_addr <= 0; end + else + begin mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_rd_addr <= mb_num_h; end + mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + else if (end_of_MB_DEC) //write + begin + if (mb_num_v == 8 || mb_num_h == 0) //!write + begin + mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + else //write + begin + mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1; + mvx_mbAddrC_din <= mvx_CurrMb0[7:0]; + end + end + else + begin + mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + end + //Inter16x16 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0) + begin + if (mb_num == 0)//!read,!write + begin + mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + else if (mb_num_v == 0)//!read,write + begin + mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1; + mvx_mbAddrC_din <= mvx; + end + else if (mb_num_h == 0 || mb_num_v == 8) //read,!write + begin + mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + else //read,write + begin + mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0; + mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= mb_num_h - 1; + mvx_mbAddrC_din <= mvx; + end + end + //Inter16x8 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0) + begin + if (mbPartIdx == 0) //upper blk,may read,no write + begin + if (refIdxL0_B && !refIdxL0_C) //read,!write + begin + mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + else //!read,!write + begin + mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + end + else //bottom blk,may write,no read + begin + if (mb_num_h != 0) //!read,write + begin + mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1; + mvx_mbAddrC_din <= mvx; + end + else //!read,!write + begin + mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + end + end + //Inter8x16 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 0) + case (mbPartIdx) + 0: //!read,write + if (mb_num_v == 8) + begin + mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + else + begin + mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1; + mvx_mbAddrC_din <= mvx; + end + default: //read,!write + begin + if (mb_num_v == 0 || mb_num_h == 10) //!read,!write + begin + mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + else //read,!write + begin + mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + end + endcase + //Inter8x8 + else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0) + case (mbPartIdx) + 1: //read,!write + if (mb_num_v == 0 || mb_num_h == 10) //!read,!write + begin + mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + else //read,!write + case (sub_mb_type) + 0: //8x8 + begin + mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= mvx; + end + 1: //8x4 + case (subMbPartIdx) + 0: //read,!write + begin + mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= mvx; + end + default: //!read,!write + begin + mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + endcase + 2: //4x8 + case (subMbPartIdx) + 1: //read,!write + begin + mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= mvx; + end + default: //!read,!write + begin + mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + endcase + 3: //4x4 + case (subMbPartIdx) + 1: //read,!write + begin + mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= mvx; + end + default: //!read,!write + begin + mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + endcase + endcase + 2: //!read,write + if (mb_num_h == 0 || mb_num_v == 8) //!read,!write + begin + mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + else //!read,write + case (sub_mb_type) + 0: //8x8 + begin + mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1; + mvx_mbAddrC_din <= mvx; + end + 1: //8x4 + case (subMbPartIdx) + 1: //!read,write + begin + mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1; + mvx_mbAddrC_din <= mvx; + end + default: //!read,!write + begin + mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + endcase + 2: //4x8 + case (subMbPartIdx) + 0: //!read,write + begin + mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1; + mvx_mbAddrC_din <= mvx; + end + default: //!read,!write + begin + mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + endcase + 3: //4x4 + case (subMbPartIdx) + 2: //!read,write + begin + mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1; + mvx_mbAddrC_din <= mvx; + end + default: //!read,!write + begin + mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + endcase + endcase + default: + begin + mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + endcase + else + begin + mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + + always @ (reset_n or slice_data_state or Is_skipMB_mv_calc or end_of_MB_DEC or mb_pred_state or sub_mb_type or sub_mb_pred_state + or mb_type_general or mb_num or mb_num_h or mb_num_v or mbPartIdx or subMbPartIdx or compIdx or mvy or mvy_CurrMb0[7:0] + or refIdxL0_B or refIdxL0_C) + if (reset_n == 0) + begin + mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + //P_skip + else if (slice_data_state == `skip_run_duration) + begin + if (Is_skipMB_mv_calc) //read + begin + if (mb_num_v == 0 || mb_num_h == 10)//!read,!write + begin mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_rd_addr <= 0; end + else + begin mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_rd_addr <= mb_num_h; end + mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + else if (end_of_MB_DEC) //write + begin + if (mb_num_v == 8 || mb_num_h == 0) //!write + begin + mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + else //write + begin + mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1; + mvy_mbAddrC_din <= mvy_CurrMb0[7:0]; + end + end + else + begin + mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + end + //Inter16x16 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1) + begin + if (mb_num == 0)//!read,!write + begin + mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + else if (mb_num_v == 0)//!read,write + begin + mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1; + mvy_mbAddrC_din <= mvy; + end + else if (mb_num_h == 0 || mb_num_v == 8) //read,!write + begin + mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + else //read,write + begin + mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0; + mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= mb_num_h - 1; + mvy_mbAddrC_din <= mvy; + end + end + //Inter16x8 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1) + begin + if (mbPartIdx == 0) //upper blk,may read,no write + begin + if (refIdxL0_B && !refIdxL0_C) //read,!write + begin + mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + else //!read,!write + begin + mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + end + else //bottom blk,may write,no read + begin + if (mb_num_h != 0) //!read,write + begin + mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1; + mvy_mbAddrC_din <= mvy; + end + else //!read,!write + begin + mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + end + end + //Inter8x16 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 1) + case (mbPartIdx) + 0: //!read,write + if (mb_num_v == 8) + begin + mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + else + begin + mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1; + mvy_mbAddrC_din <= mvy; + end + default: //read,!write + begin + if (mb_num_v == 0 || mb_num_h == 10) //!read,!write + begin + mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + else //read,!write + begin + mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + end + endcase + //Inter8x8 + else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1) + case (mbPartIdx) + 1: //read,!write + if (mb_num_v == 0 || mb_num_h == 10) //!read,!write + begin + mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + else //read,!write + case (sub_mb_type) + 0: //8x8 + begin + mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= mvy; + end + 1: //8x4 + case (subMbPartIdx) + 0: //read,!write + begin + mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= mvy; + end + default: //!read,!write + begin + mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + endcase + 2: //4x8 + case (subMbPartIdx) + 1: //read,!write + begin + mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= mvy; + end + default: //!read,!write + begin + mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + endcase + 3: //4x4 + case (subMbPartIdx) + 1: //read,!write + begin + mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= mvy; + end + default: //!read,!write + begin + mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + endcase + endcase + 2: //!read,write + if (mb_num_h == 0 || mb_num_v == 8) //!read,!write + begin + mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + else //!read,write + case (sub_mb_type) + 0: //8x8 + begin + mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1; + mvy_mbAddrC_din <= mvy; + end + 1: //8x4 + case (subMbPartIdx) + 1: //!read,write + begin + mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1; + mvy_mbAddrC_din <= mvy; + end + default: //!read,!write + begin + mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + endcase + 2: //4x8 + case (subMbPartIdx) + 0: //!read,write + begin + mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1; + mvy_mbAddrC_din <= mvy; + end + default: //!read,!write + begin + mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + endcase + 3: //4x4 + case (subMbPartIdx) + 2: //!read,write + begin + mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1; + mvy_mbAddrC_din <= mvy; + end + default: //!read,!write + begin + mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + endcase + endcase + default: + begin + mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + endcase + else + begin + mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + + //------------------------------- + //mbAddrD write --> mvx_mbAddrD + //------------------------------- + //mvx_mbAddrD + reg [7:0] mvx_mbAddrD_subMB; + reg [7:0] mvx_mbAddrD_MB,mvx_mbAddrD_MB_tmp; + always @ (posedge clk) + if (reset_n == 0) + mvx_mbAddrD_subMB <= 0; + else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0) + case (mbPartIdx) + 0:if (sub_mb_type == 1 && subMbPartIdx == 0) //8x4 UpperBlk + mvx_mbAddrD_subMB <= mvx_mbAddrA[7:0]; + 2:if (sub_mb_type == 1 && subMbPartIdx == 0) //8x4 UpperBlk + mvx_mbAddrD_subMB <= mvx_mbAddrA[23:16]; + endcase + + always @ (posedge clk) + if (reset_n == 1'b0) + mvx_mbAddrD_MB_tmp <= 0; + else if (end_of_MB_DEC && mb_num_v != 8 && mb_num_h == 9 && mb_type_general[3] == 0) + mvx_mbAddrD_MB_tmp <= (mv_is16x16)? mvx_CurrMb0[7:0]:mvx_CurrMb3[31:24]; + + always @ (posedge clk) + if (reset_n == 1'b0) + mvx_mbAddrD_MB <= 0; + else if (end_of_MB_DEC && mb_num_h == 10) + mvx_mbAddrD_MB <= mvx_mbAddrD_MB_tmp; + + assign mvx_mbAddrD = ((mbPartIdx == 0 || mbPartIdx == 2) && sub_mb_type == 1 && subMbPartIdx == 1)? mvx_mbAddrD_subMB:mvx_mbAddrD_MB; + + //mvy_mbAddrD + reg [7:0] mvy_mbAddrD_subMB; + reg [7:0] mvy_mbAddrD_MB,mvy_mbAddrD_MB_tmp; + always @ (posedge clk) + if (reset_n == 0) + mvy_mbAddrD_subMB <= 0; + else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0) + case (mbPartIdx) + 0:if (sub_mb_type == 1 && subMbPartIdx == 0) //8x4 UpperBlk + mvy_mbAddrD_subMB <= mvy_mbAddrA[7:0]; + 2:if (sub_mb_type == 1 && subMbPartIdx == 0) //8x4 UpperBlk + mvy_mbAddrD_subMB <= mvy_mbAddrA[23:16]; + endcase + + always @ (posedge clk) + if (reset_n == 1'b0) + mvy_mbAddrD_MB_tmp <= 0; + else if (end_of_MB_DEC && mb_num_v != 8 && mb_num_h == 9 && mb_type_general[3] == 0) + mvy_mbAddrD_MB_tmp <= (mv_is16x16)? mvy_CurrMb0[7:0]:mvy_CurrMb3[31:24]; + + always @ (posedge clk) + if (reset_n == 1'b0) + mvy_mbAddrD_MB <= 0; + else if (end_of_MB_DEC && mb_num_h == 10) + mvy_mbAddrD_MB <= mvy_mbAddrD_MB_tmp; + + assign mvy_mbAddrD = ((mbPartIdx == 0 || mbPartIdx == 2) && sub_mb_type == 1 && subMbPartIdx == 1)? mvy_mbAddrD_subMB:mvy_mbAddrD_MB; + +endmodule \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/Inter_pred_CPE.v b/demo_chip_rtl/rtl/nova/tags/Start/src/Inter_pred_CPE.v new file mode 100644 index 0000000..82a7c0f --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/Inter_pred_CPE.v @@ -0,0 +1,150 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : Inter_pred_CPE.v +// Generated : Oct 14, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Processing Element for Inter prediction of Chroma pixels +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module Inter_pred_CPE (xFracC,yFracC, + Inter_C_window_0_0,Inter_C_window_1_0,Inter_C_window_2_0, + Inter_C_window_0_1,Inter_C_window_1_1,Inter_C_window_2_1, + Inter_C_window_0_2,Inter_C_window_1_2,Inter_C_window_2_2, + CPE0_out,CPE1_out,CPE2_out,CPE3_out); + input [2:0] xFracC,yFracC; + input [7:0] Inter_C_window_0_0,Inter_C_window_1_0,Inter_C_window_2_0; + input [7:0] Inter_C_window_0_1,Inter_C_window_1_1,Inter_C_window_2_1; + input [7:0] Inter_C_window_0_2,Inter_C_window_1_2,Inter_C_window_2_2; + output [7:0] CPE0_out,CPE1_out,CPE2_out,CPE3_out; + + wire [3:0] xFracC_n,yFracC_n; + assign xFracC_n = 4'b1000 - xFracC; + assign yFracC_n = 4'b1000 - yFracC; + + CPE CPE0 ( + .xFracC(xFracC), + .yFracC(yFracC), + .xFracC_n(xFracC_n), + .yFracC_n(yFracC_n), + .a(Inter_C_window_0_0), + .b(Inter_C_window_1_0), + .c(Inter_C_window_0_1), + .d(Inter_C_window_1_1), + .out(CPE0_out) + ); + CPE CPE1 ( + .xFracC(xFracC), + .yFracC(yFracC), + .xFracC_n(xFracC_n), + .yFracC_n(yFracC_n), + .a(Inter_C_window_1_0), + .b(Inter_C_window_2_0), + .c(Inter_C_window_1_1), + .d(Inter_C_window_2_1), + .out(CPE1_out) + ); + CPE CPE2 ( + .xFracC(xFracC), + .yFracC(yFracC), + .xFracC_n(xFracC_n), + .yFracC_n(yFracC_n), + .a(Inter_C_window_0_1), + .b(Inter_C_window_1_1), + .c(Inter_C_window_0_2), + .d(Inter_C_window_1_2), + .out(CPE2_out) + ); + CPE CPE3 ( + .xFracC(xFracC), + .yFracC(yFracC), + .xFracC_n(xFracC_n), + .yFracC_n(yFracC_n), + .a(Inter_C_window_1_1), + .b(Inter_C_window_2_1), + .c(Inter_C_window_1_2), + .d(Inter_C_window_2_2), + .out(CPE3_out) + ); +endmodule + +module CPE (xFracC,yFracC,xFracC_n,yFracC_n,a,b,c,d,out); + input [2:0] xFracC,yFracC; + input [3:0] xFracC_n,yFracC_n; + input [7:0] a,b,c,d; + output [7:0] out; + + wire [13:0] CPE_base0_out,CPE_base1_out,CPE_base2_out,CPE_base3_out; + wire [13:0] out_tmp; + + CPE_base CPE_base0 ( + .x(xFracC_n), + .y(yFracC_n), + .Int_pel(a), + .out(CPE_base0_out) + ); + CPE_base CPE_base1 ( + .x({1'b0,xFracC}), + .y(yFracC_n), + .Int_pel(b), + .out(CPE_base1_out) + ); + CPE_base CPE_base2 ( + .x(xFracC_n), + .y({1'b0,yFracC}), + .Int_pel(c), + .out(CPE_base2_out) + ); + CPE_base CPE_base3 ( + .x({1'b0,xFracC}), + .y({1'b0,yFracC}), + .Int_pel(d), + .out(CPE_base3_out) + ); + assign out_tmp = (CPE_base0_out + CPE_base1_out) + (CPE_base2_out + CPE_base3_out) + 32; + assign out = out_tmp[13:6]; +endmodule + +module CPE_base (x,y,Int_pel,out); + input [3:0] x; + input [3:0] y; + input [7:0] Int_pel; + output [13:0] out; + + wire [10:0] sum_x3; + wire [9:0] sum_x2; + wire [8:0] sum_x1; + wire [7:0] sum_x0; + wire [10:0] sum_x; + + wire [13:0] sum_y3; + wire [12:0] sum_y2; + wire [11:0] sum_y1; + wire [10:0] sum_y0; + + assign sum_x3 = (x[3] == 1'b1)? {Int_pel,3'b0}:0; + assign sum_x2 = (x[2] == 1'b1)? {Int_pel,2'b0}:0; + assign sum_x1 = (x[1] == 1'b1)? {Int_pel,1'b0}:0; + assign sum_x0 = (x[0] == 1'b1)? Int_pel:0; + assign sum_x = (sum_x3 + sum_x2) + (sum_x1 + sum_x0); + + assign sum_y3 = (y[3] == 1'b1)? {sum_x,3'b0}:0; + assign sum_y2 = (y[2] == 1'b1)? {sum_x,2'b0}:0; + assign sum_y1 = (y[1] == 1'b1)? {sum_x,1'b0}:0; + assign sum_y0 = (y[0] == 1'b1)? sum_x:0; + assign out = (sum_y3 + sum_y2) + (sum_y1 + sum_y0); +endmodule + + + + + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/Inter_pred_LPE.v b/demo_chip_rtl/rtl/nova/tags/Start/src/Inter_pred_LPE.v new file mode 100644 index 0000000..a5eb4e7 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/Inter_pred_LPE.v @@ -0,0 +1,591 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : Inter_pred_LPE.v +// Generated : Oct 11, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Processing Element for Inter prediction of Luma pixels +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module Inter_pred_LPE (clk,reset_n,pos_FracL,IsInterLuma, + blk4x4_inter_calculate_counter, + Inter_H_window_0_0,Inter_H_window_1_0,Inter_H_window_2_0,Inter_H_window_3_0,Inter_H_window_4_0,Inter_H_window_5_0, + Inter_H_window_0_1,Inter_H_window_1_1,Inter_H_window_2_1,Inter_H_window_3_1,Inter_H_window_4_1,Inter_H_window_5_1, + Inter_H_window_0_2,Inter_H_window_1_2,Inter_H_window_2_2,Inter_H_window_3_2,Inter_H_window_4_2,Inter_H_window_5_2, + Inter_H_window_0_3,Inter_H_window_1_3,Inter_H_window_2_3,Inter_H_window_3_3,Inter_H_window_4_3,Inter_H_window_5_3, + Inter_H_window_0_4,Inter_H_window_1_4,Inter_H_window_2_4,Inter_H_window_3_4,Inter_H_window_4_4,Inter_H_window_5_4, + Inter_H_window_0_5,Inter_H_window_1_5,Inter_H_window_2_5,Inter_H_window_3_5,Inter_H_window_4_5,Inter_H_window_5_5, + Inter_H_window_0_6,Inter_H_window_1_6,Inter_H_window_2_6,Inter_H_window_3_6,Inter_H_window_4_6,Inter_H_window_5_6, + Inter_H_window_0_7,Inter_H_window_1_7,Inter_H_window_2_7,Inter_H_window_3_7,Inter_H_window_4_7,Inter_H_window_5_7, + Inter_H_window_0_8,Inter_H_window_1_8,Inter_H_window_2_8,Inter_H_window_3_8,Inter_H_window_4_8,Inter_H_window_5_8, + Inter_V_window_0,Inter_V_window_1,Inter_V_window_2,Inter_V_window_3,Inter_V_window_4, + Inter_V_window_5,Inter_V_window_6,Inter_V_window_7,Inter_V_window_8, + Inter_bi_window_0,Inter_bi_window_1,Inter_bi_window_2,Inter_bi_window_3, + + LPE0_out,LPE1_out,LPE2_out,LPE3_out + ); + input clk,reset_n; + input [3:0] pos_FracL; + input IsInterLuma; + input [3:0] blk4x4_inter_calculate_counter; + + input [7:0] Inter_H_window_0_0,Inter_H_window_1_0,Inter_H_window_2_0,Inter_H_window_3_0,Inter_H_window_4_0,Inter_H_window_5_0; + input [7:0] Inter_H_window_0_1,Inter_H_window_1_1,Inter_H_window_2_1,Inter_H_window_3_1,Inter_H_window_4_1,Inter_H_window_5_1; + input [7:0] Inter_H_window_0_2,Inter_H_window_1_2,Inter_H_window_2_2,Inter_H_window_3_2,Inter_H_window_4_2,Inter_H_window_5_2; + input [7:0] Inter_H_window_0_3,Inter_H_window_1_3,Inter_H_window_2_3,Inter_H_window_3_3,Inter_H_window_4_3,Inter_H_window_5_3; + input [7:0] Inter_H_window_0_4,Inter_H_window_1_4,Inter_H_window_2_4,Inter_H_window_3_4,Inter_H_window_4_4,Inter_H_window_5_4; + input [7:0] Inter_H_window_0_5,Inter_H_window_1_5,Inter_H_window_2_5,Inter_H_window_3_5,Inter_H_window_4_5,Inter_H_window_5_5; + input [7:0] Inter_H_window_0_6,Inter_H_window_1_6,Inter_H_window_2_6,Inter_H_window_3_6,Inter_H_window_4_6,Inter_H_window_5_6; + input [7:0] Inter_H_window_0_7,Inter_H_window_1_7,Inter_H_window_2_7,Inter_H_window_3_7,Inter_H_window_4_7,Inter_H_window_5_7; + input [7:0] Inter_H_window_0_8,Inter_H_window_1_8,Inter_H_window_2_8,Inter_H_window_3_8,Inter_H_window_4_8,Inter_H_window_5_8; + input [7:0] Inter_V_window_0,Inter_V_window_1,Inter_V_window_2,Inter_V_window_3,Inter_V_window_4; + input [7:0] Inter_V_window_5,Inter_V_window_6,Inter_V_window_7,Inter_V_window_8; + input [7:0] Inter_bi_window_0,Inter_bi_window_1,Inter_bi_window_2,Inter_bi_window_3; + + output [7:0] LPE0_out,LPE1_out,LPE2_out,LPE3_out; + + reg [7:0] LPE0_out,LPE1_out,LPE2_out,LPE3_out; + + reg [14:0] b0_raw_reg,b1_raw_reg,b2_raw_reg,b3_raw_reg,b4_raw_reg,b5_raw_reg,b6_raw_reg,b7_raw_reg,b8_raw_reg; + reg [7:0] b0_reg,b1_reg,b2_reg,b3_reg; + reg [7:0] h0_reg,h1_reg,h2_reg,h3_reg; + //------------------------ + //Vertical 6tap filter + //------------------------ + wire Is_V_jfqik; //Is_V_jfqik: whether read from original [7:0] integer pixels and round as +16 >> 5 or read from b_raw[14:0] and round as +512 >> 10 + wire [14:0] V_6tapfilter0_A,V_6tapfilter0_B,V_6tapfilter0_C,V_6tapfilter0_D,V_6tapfilter0_E,V_6tapfilter0_F; + wire [14:0] V_6tapfilter1_A,V_6tapfilter1_B,V_6tapfilter1_C,V_6tapfilter1_D,V_6tapfilter1_E,V_6tapfilter1_F; + wire [14:0] V_6tapfilter2_A,V_6tapfilter2_B,V_6tapfilter2_C,V_6tapfilter2_D,V_6tapfilter2_E,V_6tapfilter2_F; + wire [14:0] V_6tapfilter3_A,V_6tapfilter3_B,V_6tapfilter3_C,V_6tapfilter3_D,V_6tapfilter3_E,V_6tapfilter3_F; + wire [7:0] V_6tapfilter0_round_out,V_6tapfilter1_round_out,V_6tapfilter2_round_out,V_6tapfilter3_round_out; + filterV_6tap V_6tapfilter0 ( + .A(V_6tapfilter0_A), + .B(V_6tapfilter0_B), + .C(V_6tapfilter0_C), + .D(V_6tapfilter0_D), + .E(V_6tapfilter0_E), + .F(V_6tapfilter0_F), + .Is_jfqik(Is_V_jfqik), + .round_out(V_6tapfilter0_round_out) + ); + filterV_6tap V_6tapfilter1 ( + .A(V_6tapfilter1_A), + .B(V_6tapfilter1_B), + .C(V_6tapfilter1_C), + .D(V_6tapfilter1_D), + .E(V_6tapfilter1_E), + .F(V_6tapfilter1_F), + .Is_jfqik(Is_V_jfqik), + .round_out(V_6tapfilter1_round_out) + ); + filterV_6tap V_6tapfilter2 ( + .A(V_6tapfilter2_A), + .B(V_6tapfilter2_B), + .C(V_6tapfilter2_C), + .D(V_6tapfilter2_D), + .E(V_6tapfilter2_E), + .F(V_6tapfilter2_F), + .Is_jfqik(Is_V_jfqik), + .round_out(V_6tapfilter2_round_out) + ); + filterV_6tap V_6tapfilter3 ( + .A(V_6tapfilter3_A), + .B(V_6tapfilter3_B), + .C(V_6tapfilter3_C), + .D(V_6tapfilter3_D), + .E(V_6tapfilter3_E), + .F(V_6tapfilter3_F), + .Is_jfqik(Is_V_jfqik), + .round_out(V_6tapfilter3_round_out) + ); + assign Is_V_jfqik = ( + (pos_FracL == `pos_j && ( + blk4x4_inter_calculate_counter == 4'd4 || blk4x4_inter_calculate_counter == 4'd3 || + blk4x4_inter_calculate_counter == 4'd2 || blk4x4_inter_calculate_counter == 4'd1)) || + ((pos_FracL == `pos_f || pos_FracL == `pos_q) && ( + blk4x4_inter_calculate_counter == 4'd4 || blk4x4_inter_calculate_counter == 4'd3 || + blk4x4_inter_calculate_counter == 4'd2 || blk4x4_inter_calculate_counter == 4'd1)) || + ((pos_FracL == `pos_i || pos_FracL == `pos_k) && ( + blk4x4_inter_calculate_counter == 4'd7 || blk4x4_inter_calculate_counter == 4'd5 || + blk4x4_inter_calculate_counter == 4'd3 || blk4x4_inter_calculate_counter == 4'd1)))? 1'b1:1'b0; + + assign V_6tapfilter0_A = (Is_V_jfqik)? b0_raw_reg:{7'b0,Inter_V_window_0}; + assign V_6tapfilter0_B = (Is_V_jfqik)? b1_raw_reg:{7'b0,Inter_V_window_1}; + assign V_6tapfilter0_C = (Is_V_jfqik)? b2_raw_reg:{7'b0,Inter_V_window_2}; + assign V_6tapfilter0_D = (Is_V_jfqik)? b3_raw_reg:{7'b0,Inter_V_window_3}; + assign V_6tapfilter0_E = (Is_V_jfqik)? b4_raw_reg:{7'b0,Inter_V_window_4}; + assign V_6tapfilter0_F = (Is_V_jfqik)? b5_raw_reg:{7'b0,Inter_V_window_5}; + + assign V_6tapfilter1_A = (Is_V_jfqik)? b1_raw_reg:{7'b0,Inter_V_window_1}; + assign V_6tapfilter1_B = (Is_V_jfqik)? b2_raw_reg:{7'b0,Inter_V_window_2}; + assign V_6tapfilter1_C = (Is_V_jfqik)? b3_raw_reg:{7'b0,Inter_V_window_3}; + assign V_6tapfilter1_D = (Is_V_jfqik)? b4_raw_reg:{7'b0,Inter_V_window_4}; + assign V_6tapfilter1_E = (Is_V_jfqik)? b5_raw_reg:{7'b0,Inter_V_window_5}; + assign V_6tapfilter1_F = (Is_V_jfqik)? b6_raw_reg:{7'b0,Inter_V_window_6}; + + assign V_6tapfilter2_A = (Is_V_jfqik)? b2_raw_reg:{7'b0,Inter_V_window_2}; + assign V_6tapfilter2_B = (Is_V_jfqik)? b3_raw_reg:{7'b0,Inter_V_window_3}; + assign V_6tapfilter2_C = (Is_V_jfqik)? b4_raw_reg:{7'b0,Inter_V_window_4}; + assign V_6tapfilter2_D = (Is_V_jfqik)? b5_raw_reg:{7'b0,Inter_V_window_5}; + assign V_6tapfilter2_E = (Is_V_jfqik)? b6_raw_reg:{7'b0,Inter_V_window_6}; + assign V_6tapfilter2_F = (Is_V_jfqik)? b7_raw_reg:{7'b0,Inter_V_window_7}; + + assign V_6tapfilter3_A = (Is_V_jfqik)? b3_raw_reg:{7'b0,Inter_V_window_3}; + assign V_6tapfilter3_B = (Is_V_jfqik)? b4_raw_reg:{7'b0,Inter_V_window_4}; + assign V_6tapfilter3_C = (Is_V_jfqik)? b5_raw_reg:{7'b0,Inter_V_window_5}; + assign V_6tapfilter3_D = (Is_V_jfqik)? b6_raw_reg:{7'b0,Inter_V_window_6}; + assign V_6tapfilter3_E = (Is_V_jfqik)? b7_raw_reg:{7'b0,Inter_V_window_7}; + assign V_6tapfilter3_F = (Is_V_jfqik)? b8_raw_reg:{7'b0,Inter_V_window_8}; + + //------------------------ + //Horizontal 6tap filter + //------------------------ + wire H_need_round; + wire [14:0] H_6tapfilter0_raw_out; + wire [14:0] H_6tapfilter1_raw_out; + wire [14:0] H_6tapfilter2_raw_out; + wire [14:0] H_6tapfilter3_raw_out; + wire [14:0] H_6tapfilter4_raw_out; + wire [14:0] H_6tapfilter5_raw_out; + wire [14:0] H_6tapfilter6_raw_out; + wire [14:0] H_6tapfilter7_raw_out; + wire [14:0] H_6tapfilter8_raw_out; + wire [7:0] H_6tapfilter0_round_out; + wire [7:0] H_6tapfilter1_round_out; + wire [7:0] H_6tapfilter2_round_out; + wire [7:0] H_6tapfilter3_round_out; + wire [7:0] H_6tapfilter4_round_out; + wire [7:0] H_6tapfilter5_round_out; + wire [7:0] H_6tapfilter6_round_out; + wire [7:0] H_6tapfilter7_round_out; + wire [7:0] H_6tapfilter8_round_out; + + assign H_need_round = (blk4x4_inter_calculate_counter != 0 && pos_FracL != `pos_Int && pos_FracL != `pos_i + && pos_FracL != `pos_j && pos_FracL != `pos_k && pos_FracL != `pos_d && pos_FracL != `pos_n); + + filterH_6tap H_6tapfilter0 ( + .A(Inter_H_window_0_0), + .B(Inter_H_window_1_0), + .C(Inter_H_window_2_0), + .D(Inter_H_window_3_0), + .E(Inter_H_window_4_0), + .F(Inter_H_window_5_0), + .H_need_round(1'b0), + .raw_out(H_6tapfilter0_raw_out), + .round_out(H_6tapfilter0_round_out) + ); + filterH_6tap H_6tapfilter1 ( + .A(Inter_H_window_0_1), + .B(Inter_H_window_1_1), + .C(Inter_H_window_2_1), + .D(Inter_H_window_3_1), + .E(Inter_H_window_4_1), + .F(Inter_H_window_5_1), + .H_need_round(1'b0), + .raw_out(H_6tapfilter1_raw_out), + .round_out(H_6tapfilter1_round_out) + ); + filterH_6tap H_6tapfilter2 ( + .A(Inter_H_window_0_2), + .B(Inter_H_window_1_2), + .C(Inter_H_window_2_2), + .D(Inter_H_window_3_2), + .E(Inter_H_window_4_2), + .F(Inter_H_window_5_2), + .H_need_round(H_need_round), + .raw_out(H_6tapfilter2_raw_out), + .round_out(H_6tapfilter2_round_out) + ); + filterH_6tap H_6tapfilter3 ( + .A(Inter_H_window_0_3), + .B(Inter_H_window_1_3), + .C(Inter_H_window_2_3), + .D(Inter_H_window_3_3), + .E(Inter_H_window_4_3), + .F(Inter_H_window_5_3), + .H_need_round(H_need_round), + .raw_out(H_6tapfilter3_raw_out), + .round_out(H_6tapfilter3_round_out) + ); + filterH_6tap H_6tapfilter4 ( + .A(Inter_H_window_0_4), + .B(Inter_H_window_1_4), + .C(Inter_H_window_2_4), + .D(Inter_H_window_3_4), + .E(Inter_H_window_4_4), + .F(Inter_H_window_5_4), + .H_need_round(H_need_round), + .raw_out(H_6tapfilter4_raw_out), + .round_out(H_6tapfilter4_round_out) + ); + filterH_6tap H_6tapfilter5 ( + .A(Inter_H_window_0_5), + .B(Inter_H_window_1_5), + .C(Inter_H_window_2_5), + .D(Inter_H_window_3_5), + .E(Inter_H_window_4_5), + .F(Inter_H_window_5_5), + .H_need_round(H_need_round), + .raw_out(H_6tapfilter5_raw_out), + .round_out(H_6tapfilter5_round_out) + ); + filterH_6tap H_6tapfilter6 ( + .A(Inter_H_window_0_6), + .B(Inter_H_window_1_6), + .C(Inter_H_window_2_6), + .D(Inter_H_window_3_6), + .E(Inter_H_window_4_6), + .F(Inter_H_window_5_6), + .H_need_round(H_need_round), + .raw_out(H_6tapfilter6_raw_out), + .round_out(H_6tapfilter6_round_out) + ); + filterH_6tap H_6tapfilter7 ( + .A(Inter_H_window_0_7), + .B(Inter_H_window_1_7), + .C(Inter_H_window_2_7), + .D(Inter_H_window_3_7), + .E(Inter_H_window_4_7), + .F(Inter_H_window_5_7), + .H_need_round(1'b0), + .raw_out(H_6tapfilter7_raw_out), + .round_out(H_6tapfilter7_round_out) + ); + filterH_6tap H_6tapfilter8 ( + .A(Inter_H_window_0_8), + .B(Inter_H_window_1_8), + .C(Inter_H_window_2_8), + .D(Inter_H_window_3_8), + .E(Inter_H_window_4_8), + .F(Inter_H_window_5_8), + .H_need_round(1'b0), + .raw_out(H_6tapfilter8_raw_out), + .round_out(H_6tapfilter8_round_out) + ); + + //-------------------- + //bilinear filter + //-------------------- + reg [7:0] bilinear0_A,bilinear0_B; + reg [7:0] bilinear1_A,bilinear1_B; + reg [7:0] bilinear2_A,bilinear2_B; + reg [7:0] bilinear3_A,bilinear3_B; + wire [7:0] bilinear0_out; + wire [7:0] bilinear1_out; + wire [7:0] bilinear2_out; + wire [7:0] bilinear3_out; + bilinear bilinear0 ( + .A(bilinear0_A), + .B(bilinear0_B), + .bilinear_out(bilinear0_out) + ); + bilinear bilinear1 ( + .A(bilinear1_A), + .B(bilinear1_B), + .bilinear_out(bilinear1_out) + ); + bilinear bilinear2 ( + .A(bilinear2_A), + .B(bilinear2_B), + .bilinear_out(bilinear2_out) + ); + bilinear bilinear3 ( + .A(bilinear3_A), + .B(bilinear3_B), + .bilinear_out(bilinear3_out) + ); + always @ (IsInterLuma or pos_FracL or blk4x4_inter_calculate_counter + or Inter_bi_window_0 or Inter_bi_window_1 or Inter_bi_window_2 or Inter_bi_window_3 + or H_6tapfilter2_round_out or H_6tapfilter3_round_out or H_6tapfilter4_round_out or H_6tapfilter5_round_out + or V_6tapfilter0_round_out or V_6tapfilter1_round_out or V_6tapfilter2_round_out or V_6tapfilter3_round_out + or b0_reg or b1_reg or b2_reg or b3_reg or h0_reg or h1_reg or h2_reg or h3_reg) + if (IsInterLuma) + case ({pos_FracL}) + `pos_a,`pos_c: + if (blk4x4_inter_calculate_counter != 4'd0) + begin + bilinear0_A <= Inter_bi_window_0; bilinear0_B <= H_6tapfilter2_round_out; + bilinear1_A <= Inter_bi_window_1; bilinear1_B <= H_6tapfilter3_round_out; + bilinear2_A <= Inter_bi_window_2; bilinear2_B <= H_6tapfilter4_round_out; + bilinear3_A <= Inter_bi_window_3; bilinear3_B <= H_6tapfilter5_round_out; + end + else + begin + bilinear0_A <= 0; bilinear0_B <= 0; bilinear1_A <= 0; bilinear1_B <= 0; + bilinear2_A <= 0; bilinear2_B <= 0; bilinear3_A <= 0; bilinear3_B <= 0; + end + `pos_d,`pos_n: + if (blk4x4_inter_calculate_counter != 4'd0) + begin + bilinear0_A <= Inter_bi_window_0; bilinear0_B <= V_6tapfilter0_round_out; + bilinear1_A <= Inter_bi_window_1; bilinear1_B <= V_6tapfilter1_round_out; + bilinear2_A <= Inter_bi_window_2; bilinear2_B <= V_6tapfilter2_round_out; + bilinear3_A <= Inter_bi_window_3; bilinear3_B <= V_6tapfilter3_round_out; + end + else + begin + bilinear0_A <= 0; bilinear0_B <= 0; bilinear1_A <= 0; bilinear1_B <= 0; + bilinear2_A <= 0; bilinear2_B <= 0; bilinear3_A <= 0; bilinear3_B <= 0; + end + `pos_e,`pos_g,`pos_p,`pos_r: + if (blk4x4_inter_calculate_counter != 4'd0) + begin + bilinear0_A <= H_6tapfilter2_round_out; bilinear0_B <= V_6tapfilter0_round_out; + bilinear1_A <= H_6tapfilter3_round_out; bilinear1_B <= V_6tapfilter1_round_out; + bilinear2_A <= H_6tapfilter4_round_out; bilinear2_B <= V_6tapfilter2_round_out; + bilinear3_A <= H_6tapfilter5_round_out; bilinear3_B <= V_6tapfilter3_round_out; + end + else + begin + bilinear0_A <= 0; bilinear0_B <= 0; bilinear1_A <= 0; bilinear1_B <= 0; + bilinear2_A <= 0; bilinear2_B <= 0; bilinear3_A <= 0; bilinear3_B <= 0; + end + `pos_i,`pos_k: + if (blk4x4_inter_calculate_counter == 4'd7 || blk4x4_inter_calculate_counter == 4'd5 || + blk4x4_inter_calculate_counter == 4'd3 || blk4x4_inter_calculate_counter == 4'd1) + begin + bilinear0_A <= h0_reg; bilinear0_B <= V_6tapfilter0_round_out; + bilinear1_A <= h1_reg; bilinear1_B <= V_6tapfilter1_round_out; + bilinear2_A <= h2_reg; bilinear2_B <= V_6tapfilter2_round_out; + bilinear3_A <= h3_reg; bilinear3_B <= V_6tapfilter3_round_out; + end + else + begin + bilinear0_A <= 0; bilinear0_B <= 0; bilinear1_A <= 0; bilinear1_B <= 0; + bilinear2_A <= 0; bilinear2_B <= 0; bilinear3_A <= 0; bilinear3_B <= 0; + end + `pos_f,`pos_q: + if (blk4x4_inter_calculate_counter != 4'd5 && blk4x4_inter_calculate_counter != 4'd0) + begin + bilinear0_A <= b0_reg; bilinear0_B <= V_6tapfilter0_round_out; + bilinear1_A <= b1_reg; bilinear1_B <= V_6tapfilter1_round_out; + bilinear2_A <= b2_reg; bilinear2_B <= V_6tapfilter2_round_out; + bilinear3_A <= b3_reg; bilinear3_B <= V_6tapfilter3_round_out; + end + else + begin + bilinear0_A <= 0; bilinear0_B <= 0; bilinear1_A <= 0; bilinear1_B <= 0; + bilinear2_A <= 0; bilinear2_B <= 0; bilinear3_A <= 0; bilinear3_B <= 0; + end + default: + begin + bilinear0_A <= 0; bilinear0_B <= 0; bilinear1_A <= 0; bilinear1_B <= 0; + bilinear2_A <= 0; bilinear2_B <= 0; bilinear3_A <= 0; bilinear3_B <= 0; + end + endcase + else + begin + bilinear0_A <= 0; bilinear0_B <= 0; bilinear1_A <= 0; bilinear1_B <= 0; + bilinear2_A <= 0; bilinear2_B <= 0; bilinear3_A <= 0; bilinear3_B <= 0; + end + + //------------------------------------------------------------------------------------------ + //only "b","h" and "j" of half-pel positions need to be stored to predict quater-pel samples + //------------------------------------------------------------------------------------------ + + //b0_raw_reg0 ~ b8_raw_reg:update after j/f/q/i/k horizontal filtering + wire b_raw_reg_ena; + assign b_raw_reg_ena = (IsInterLuma && + ((pos_FracL == `pos_j && blk4x4_inter_calculate_counter != 4'd1 && blk4x4_inter_calculate_counter != 4'd0) || + ((pos_FracL == `pos_f || pos_FracL == `pos_q) && (blk4x4_inter_calculate_counter == 4'd5 || + blk4x4_inter_calculate_counter == 4'd4 || + blk4x4_inter_calculate_counter == 4'd3 || + blk4x4_inter_calculate_counter == 4'd2)) || + ((pos_FracL == `pos_i || pos_FracL == `pos_k) && (blk4x4_inter_calculate_counter == 4'd8 || + blk4x4_inter_calculate_counter == 4'd6 || + blk4x4_inter_calculate_counter == 4'd4 || + blk4x4_inter_calculate_counter == 4'd2)))); + + always @ (posedge clk) + if (reset_n == 1'b0) + begin + b0_raw_reg <= 0; b1_raw_reg <= 0; b2_raw_reg <= 0; b3_raw_reg <= 0; b4_raw_reg <= 0; + b5_raw_reg <= 0; b6_raw_reg <= 0; b7_raw_reg <= 0; b8_raw_reg <= 0; + end + else if (b_raw_reg_ena) + begin + b0_raw_reg <= H_6tapfilter0_raw_out;b1_raw_reg <= H_6tapfilter1_raw_out;b2_raw_reg <= H_6tapfilter2_raw_out; + b3_raw_reg <= H_6tapfilter3_raw_out;b4_raw_reg <= H_6tapfilter4_raw_out;b5_raw_reg <= H_6tapfilter5_raw_out; + b6_raw_reg <= H_6tapfilter6_raw_out;b7_raw_reg <= H_6tapfilter7_raw_out;b8_raw_reg <= H_6tapfilter8_raw_out; + end + + //b0_reg ~ b3_reg:update for decoding f,q + //Note:position q needs "b" of next line + wire b_reg_ena; + assign b_reg_ena = (IsInterLuma && ((pos_FracL == `pos_f || pos_FracL == `pos_q) && (blk4x4_inter_calculate_counter == 4'd5 || + blk4x4_inter_calculate_counter == 4'd4 || blk4x4_inter_calculate_counter == 4'd3 || blk4x4_inter_calculate_counter == 4'd2))); + + always @ (posedge clk) + if (reset_n == 1'b0) + begin + b0_reg <= 0; b1_reg <= 0; b2_reg <= 0; b3_reg <= 0; + end + else if (b_reg_ena) + begin + if (pos_FracL == `pos_q) + begin + b0_reg <= H_6tapfilter3_round_out; b1_reg <= H_6tapfilter4_round_out; + b2_reg <= H_6tapfilter5_round_out; b3_reg <= H_6tapfilter6_round_out; + end + else + begin + b0_reg <= H_6tapfilter2_round_out; b1_reg <= H_6tapfilter3_round_out; + b2_reg <= H_6tapfilter4_round_out; b3_reg <= H_6tapfilter5_round_out; + end + end + + //h0_reg ~ h3_reg:update for decoding i,k + wire h_reg_ena; + assign h_reg_ena = (IsInterLuma && ((pos_FracL == `pos_i || pos_FracL == `pos_k) && (blk4x4_inter_calculate_counter == 4'd8 || + blk4x4_inter_calculate_counter == 4'd6 || blk4x4_inter_calculate_counter == 4'd4 || blk4x4_inter_calculate_counter == 4'd2))); + + always @ (posedge clk) + if (reset_n == 1'b0) + begin + h0_reg <= 0; h1_reg <= 0; h2_reg <= 0; h3_reg <= 0; + end + else if (h_reg_ena) + begin + h0_reg <= V_6tapfilter0_round_out; h1_reg <= V_6tapfilter1_round_out; + h2_reg <= V_6tapfilter2_round_out; h3_reg <= V_6tapfilter3_round_out; + end + //------------------------------------------------------------------------------------------ + //LPE output + //------------------------------------------------------------------------------------------ + always @ (IsInterLuma or pos_FracL or blk4x4_inter_calculate_counter + or V_6tapfilter0_round_out or V_6tapfilter1_round_out or V_6tapfilter2_round_out or V_6tapfilter3_round_out + or H_6tapfilter2_round_out or H_6tapfilter3_round_out or H_6tapfilter4_round_out or H_6tapfilter5_round_out + or bilinear0_out or bilinear1_out or bilinear2_out or bilinear3_out) + if (IsInterLuma) + case (pos_FracL) + //pos_Int: directly bypassed by Inter_pix_copy0 ~ Inter_pix_copy3 + `pos_b: + if (blk4x4_inter_calculate_counter != 0) + begin + LPE0_out <= H_6tapfilter2_round_out; LPE1_out <= H_6tapfilter3_round_out; + LPE2_out <= H_6tapfilter4_round_out; LPE3_out <= H_6tapfilter5_round_out; + end + else + begin LPE0_out <= 0; LPE1_out <= 0;LPE2_out <= 0; LPE3_out <= 0;end + `pos_h: + if (blk4x4_inter_calculate_counter != 0) + begin + LPE0_out <= V_6tapfilter0_round_out; LPE1_out <= V_6tapfilter1_round_out; + LPE2_out <= V_6tapfilter2_round_out; LPE3_out <= V_6tapfilter3_round_out; + end + else + begin LPE0_out <= 0; LPE1_out <= 0;LPE2_out <= 0; LPE3_out <= 0;end + `pos_j: + if (blk4x4_inter_calculate_counter != 4'd5 && blk4x4_inter_calculate_counter != 0) + begin + LPE0_out <= V_6tapfilter0_round_out; LPE1_out <= V_6tapfilter1_round_out; + LPE2_out <= V_6tapfilter2_round_out; LPE3_out <= V_6tapfilter3_round_out; + end + else + begin LPE0_out <= 0; LPE1_out <= 0;LPE2_out <= 0; LPE3_out <= 0;end + `pos_a,`pos_c,`pos_d,`pos_e,`pos_g,`pos_n,`pos_p,`pos_r,`pos_f,`pos_q: + if (blk4x4_inter_calculate_counter == 4'd4 || blk4x4_inter_calculate_counter == 4'd3 || + blk4x4_inter_calculate_counter == 4'd2 || blk4x4_inter_calculate_counter == 4'd1) + begin + LPE0_out <= bilinear0_out; LPE1_out <= bilinear1_out; + LPE2_out <= bilinear2_out; LPE3_out <= bilinear3_out; + end + else + begin LPE0_out <= 0; LPE1_out <= 0;LPE2_out <= 0; LPE3_out <= 0;end + `pos_i,`pos_k: + if (blk4x4_inter_calculate_counter == 4'd7 || blk4x4_inter_calculate_counter == 4'd5 || + blk4x4_inter_calculate_counter == 4'd3 || blk4x4_inter_calculate_counter == 4'd1) + begin + LPE0_out <= bilinear0_out; LPE1_out <= bilinear1_out; + LPE2_out <= bilinear2_out; LPE3_out <= bilinear3_out; + end + else + begin LPE0_out <= 0; LPE1_out <= 0;LPE2_out <= 0; LPE3_out <= 0;end + default: + begin LPE0_out <= 0; LPE1_out <= 0;LPE2_out <= 0; LPE3_out <= 0;end + endcase + else + begin LPE0_out <= 0; LPE1_out <= 0;LPE2_out <= 0; LPE3_out <= 0;end + +endmodule + +module filterH_6tap(A,B,C,D,E,F,H_need_round,raw_out,round_out); + input [7:0] A,B,C,D,E,F; + input H_need_round; + output [14:0] raw_out; //always output + output [7:0] round_out; + + wire [8:0] sum_AF; + wire [8:0] sum_BE; + wire [8:0] sum_CD; + wire [10:0] sum_4CD; + wire [11:0] sum_1; + wire [12:0] sum_2; + wire [13:0] sum_3; + wire [14:0] sum_round; + wire [9:0] round_tmp; + + assign sum_AF = A + F; + assign sum_BE = B + E; + assign sum_CD = C + D; + assign sum_4CD = {sum_CD,2'b0}; + assign sum_1 = {1'b0,sum_4CD} + {3'b111,~sum_BE} + 1; + assign sum_2 = {4'b0,sum_AF} + {sum_1[11],sum_1}; + assign sum_3 = {sum_1,2'b0}; + assign raw_out = {{2{sum_2[12]}},sum_2} + {sum_3[13],sum_3}; + //round + assign sum_round = (H_need_round)? (raw_out + 16):0; + assign round_tmp = (H_need_round)? sum_round[14:5]:0; + assign round_out = (round_tmp[9])? 8'd0:((round_tmp[8])? 8'd255:round_tmp[7:0]); +endmodule + +module filterV_6tap(A,B,C,D,E,F,Is_jfqik,round_out); + input [14:0] A,B,C,D,E,F; + input Is_jfqik; + output [7:0] round_out; + + wire [15:0] sum_AF; + wire [15:0] sum_BE; + wire [15:0] sum_CD; + wire [17:0] sum_4CD; + wire [17:0] sum_1; + wire [17:0] sum_2; + wire [19:0] sum_3; + wire [19:0] raw_out; + + wire [19:0] sum_round; + wire [9:0] round_tmp; + + assign sum_AF = {A[14],A} + {F[14],F}; + assign sum_BE = {B[14],B} + {E[14],E}; + assign sum_CD = {C[14],C} + {D[14],D}; + assign sum_4CD = {sum_CD,2'b0}; + assign sum_1 = sum_4CD + {~sum_BE[15],~sum_BE[15],~sum_BE} + 1; + assign sum_2 = {{2{sum_AF[15]}},sum_AF} + sum_1; + assign sum_3 = {sum_1,2'b0}; + assign raw_out = {{2{sum_2[17]}},sum_2} + sum_3; + //round + assign sum_round = (Is_jfqik)? (raw_out + 512):(raw_out + 16); + assign round_tmp = (Is_jfqik)? sum_round[19:10]:sum_round[14:5]; + assign round_out = (round_tmp[9])? 8'd0:((round_tmp[8])? 8'd255:round_tmp[7:0]); +endmodule + +module bilinear (A,B,bilinear_out); + input [7:0] A,B; + output [7:0] bilinear_out; + wire [8:0] sum_AB; + + assign sum_AB = A + B + 1; //here A and B should NOT extend as {A[7],A} + assign bilinear_out = sum_AB[8:1]; +endmodule + + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/Inter_pred_pipeline.v b/demo_chip_rtl/rtl/nova/tags/Start/src/Inter_pred_pipeline.v new file mode 100644 index 0000000..ad3c411 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/Inter_pred_pipeline.v @@ -0,0 +1,782 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : Inter_pred_pipeline.v +// Generated : Oct 4, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Inter prediction pipeline +//------------------------------------------------------------------------------------------------- +// Revise log +// 1.July 23,2006 +// Change the ext_frame_RAM from async read to sync read.Therefore,blk4x4_inter_preload_counter has to +1 for all the cases +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module Inter_pred_pipeline (clk,reset_n, + mb_num_h,mb_num_v,trigger_blk4x4_inter_pred,blk4x4_rec_counter,mb_type_general_bit3, + mv_is16x16,mv_below8x8, + mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3, + mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3, + Inter_pix_copy0,Inter_pix_copy1,Inter_pix_copy2,Inter_pix_copy3, + LPE0_out,LPE1_out,LPE2_out,LPE3_out, + CPE0_out,CPE1_out,CPE2_out,CPE3_out, + + mv_below8x8_curr,blk4x4_inter_preload_counter,blk4x4_inter_calculate_counter,Inter_chroma2x2_counter, + end_of_one_blk4x4_inter,IsInterLuma,IsInterChroma,Is_InterChromaCopy, + xInt_addr_unclip,xInt_org_unclip_1to0,pos_FracL,xFracC,yFracC, + Inter_pred_out0,Inter_pred_out1,Inter_pred_out2,Inter_pred_out3,Inter_blk4x4_pred_output_valid, + ref_frame_RAM_rd,ref_frame_RAM_rd_addr); + input clk; + input reset_n; + input [3:0] mb_num_h,mb_num_v; + input trigger_blk4x4_inter_pred; + input [4:0] blk4x4_rec_counter; + input mb_type_general_bit3; + input mv_is16x16; + input [3:0] mv_below8x8; + input [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3; + input [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3; + input [7:0] Inter_pix_copy0,Inter_pix_copy1,Inter_pix_copy2,Inter_pix_copy3; + input [7:0] LPE0_out,LPE1_out,LPE2_out,LPE3_out; + input [7:0] CPE0_out,CPE1_out,CPE2_out,CPE3_out; + + output mv_below8x8_curr; + output [5:0] blk4x4_inter_preload_counter; + output [3:0] blk4x4_inter_calculate_counter; + output [1:0] Inter_chroma2x2_counter; + output end_of_one_blk4x4_inter; + output IsInterLuma,IsInterChroma; + output Is_InterChromaCopy; + output [8:0] xInt_addr_unclip; + output [1:0] xInt_org_unclip_1to0; + output [3:0] pos_FracL; + output [2:0] xFracC,yFracC; + output [7:0] Inter_pred_out0,Inter_pred_out1,Inter_pred_out2,Inter_pred_out3; + output [1:0] Inter_blk4x4_pred_output_valid; //2'b01:luma output valid 2'b10:chroma output valid + output ref_frame_RAM_rd; + output [13:0] ref_frame_RAM_rd_addr; + + reg [5:0] blk4x4_inter_preload_counter; + reg [3:0] blk4x4_inter_calculate_counter; + reg mv_below8x8_curr; + reg [7:0] Inter_pred_out0,Inter_pred_out1,Inter_pred_out2,Inter_pred_out3; + reg [1:0] Inter_blk4x4_pred_output_valid; + wire ref_frame_RAM_rd; + wire IsInterLuma; + wire IsInterChroma; + wire [1:0] xFracL; + wire [1:0] yFracL; + wire [2:0] xFracC; + wire [2:0] yFracC; + wire [13:0] ref_frame_RAM_rd_addr; + + assign IsInterLuma = (!mb_type_general_bit3 && blk4x4_rec_counter < 16)? 1'b1:1'b0; + assign IsInterChroma = (!mb_type_general_bit3 && blk4x4_rec_counter > 15)? 1'b1:1'b0; + //------------------------------------------------------------------------- + //mv_below8x8_curr for each 2x2 Inter Chroma prediction + //------------------------------------------------------------------------- + always @ (IsInterLuma or IsInterChroma or blk4x4_rec_counter[3:0] or mv_below8x8) + if (IsInterLuma) + case (blk4x4_rec_counter[3:2]) + 2'b00:mv_below8x8_curr <= mv_below8x8[0]; + 2'b01:mv_below8x8_curr <= mv_below8x8[1]; + 2'b10:mv_below8x8_curr <= mv_below8x8[2]; + 2'b11:mv_below8x8_curr <= mv_below8x8[3]; + endcase + else if (IsInterChroma) + case (blk4x4_rec_counter[1:0]) + 2'b00:mv_below8x8_curr <= mv_below8x8[0]; + 2'b01:mv_below8x8_curr <= mv_below8x8[1]; + 2'b10:mv_below8x8_curr <= mv_below8x8[2]; + 2'b11:mv_below8x8_curr <= mv_below8x8[3]; + endcase + else + mv_below8x8_curr <= 0; + //---------------------------------------------------------------------------------------- + //Inter_chroma2x2_counter to guide the prediction of 2x2 chroma blocks + //2'b11 -> 2'b10 -> 2'b01 -> 2'b00 + //---------------------------------------------------------------------------------------- + reg [1:0] Inter_chroma2x2_counter; + always @ (posedge clk) + if (reset_n == 1'b0) + Inter_chroma2x2_counter <= 0; + //mv_below8x8_curr == 1'b1 includes the condition that "blk4x4_rec_counter > 15" + else if (IsInterChroma && trigger_blk4x4_inter_pred && mv_below8x8_curr) + Inter_chroma2x2_counter <= 2'b11; + else if (blk4x4_inter_calculate_counter == 4'd1 && Inter_chroma2x2_counter != 0) + Inter_chroma2x2_counter <= Inter_chroma2x2_counter - 1; + + //---------------------------------------------------------------------------------------- + //trigger_blk2x2_inter_pred:only for chroma 2x2 decoding + //We introduce this additional signal since we need Inter_chroma2x2_counter to update + //one cycle before blk4x4_inter_calculate_counter + //---------------------------------------------------------------------------------------- + reg trigger_blk2x2_inter_pred; + always @ (posedge clk) + if (reset_n == 1'b0) + trigger_blk2x2_inter_pred <= 0; + else if ((IsInterChroma && trigger_blk4x4_inter_pred && mv_below8x8_curr) || + (blk4x4_inter_calculate_counter == 4'd1 && Inter_chroma2x2_counter != 0)) + trigger_blk2x2_inter_pred <= 1'b1; + else + trigger_blk2x2_inter_pred <= 1'b0; + //---------------------------------------------------------------------------------------- + //Inter motion vector for current 4x4 luma/chroma block or 2x2 chroma block + // Inter_blk_mvx,Inter_blk_mvy + //---------------------------------------------------------------------------------------- + reg [7:0] Inter_blk_mvx,Inter_blk_mvy; + always @ (blk4x4_rec_counter or mv_below8x8_curr or Inter_chroma2x2_counter + or IsInterLuma or IsInterChroma or mv_is16x16 + or mvx_CurrMb0 or mvx_CurrMb1 or mvx_CurrMb2 or mvx_CurrMb3 + or mvy_CurrMb0 or mvy_CurrMb1 or mvy_CurrMb2 or mvy_CurrMb3) + //Inter luma + if (IsInterLuma) + begin + if (mv_is16x16) + begin Inter_blk_mvx <= mvx_CurrMb0[7:0]; Inter_blk_mvy <= mvy_CurrMb0[7:0]; end + else + case (mv_below8x8_curr) + 1'b0: + case (blk4x4_rec_counter[3:2]) + 2'b00:begin Inter_blk_mvx <= mvx_CurrMb0[7:0]; Inter_blk_mvy <= mvy_CurrMb0[7:0]; end + 2'b01:begin Inter_blk_mvx <= mvx_CurrMb1[7:0]; Inter_blk_mvy <= mvy_CurrMb1[7:0]; end + 2'b10:begin Inter_blk_mvx <= mvx_CurrMb2[7:0]; Inter_blk_mvy <= mvy_CurrMb2[7:0]; end + 2'b11:begin Inter_blk_mvx <= mvx_CurrMb3[7:0]; Inter_blk_mvy <= mvy_CurrMb3[7:0]; end + endcase + 1'b1: + case (blk4x4_rec_counter) + 0 :begin Inter_blk_mvx <= mvx_CurrMb0[7:0]; Inter_blk_mvy <= mvy_CurrMb0[7:0]; end + 1 :begin Inter_blk_mvx <= mvx_CurrMb0[15:8]; Inter_blk_mvy <= mvy_CurrMb0[15:8]; end + 2 :begin Inter_blk_mvx <= mvx_CurrMb0[23:16];Inter_blk_mvy <= mvy_CurrMb0[23:16]; end + 3 :begin Inter_blk_mvx <= mvx_CurrMb0[31:24];Inter_blk_mvy <= mvy_CurrMb0[31:24]; end + 4 :begin Inter_blk_mvx <= mvx_CurrMb1[7:0]; Inter_blk_mvy <= mvy_CurrMb1[7:0]; end + 5 :begin Inter_blk_mvx <= mvx_CurrMb1[15:8]; Inter_blk_mvy <= mvy_CurrMb1[15:8]; end + 6 :begin Inter_blk_mvx <= mvx_CurrMb1[23:16];Inter_blk_mvy <= mvy_CurrMb1[23:16]; end + 7 :begin Inter_blk_mvx <= mvx_CurrMb1[31:24];Inter_blk_mvy <= mvy_CurrMb1[31:24]; end + 8 :begin Inter_blk_mvx <= mvx_CurrMb2[7:0]; Inter_blk_mvy <= mvy_CurrMb2[7:0]; end + 9 :begin Inter_blk_mvx <= mvx_CurrMb2[15:8]; Inter_blk_mvy <= mvy_CurrMb2[15:8]; end + 10:begin Inter_blk_mvx <= mvx_CurrMb2[23:16];Inter_blk_mvy <= mvy_CurrMb2[23:16]; end + 11:begin Inter_blk_mvx <= mvx_CurrMb2[31:24];Inter_blk_mvy <= mvy_CurrMb2[31:24]; end + 12:begin Inter_blk_mvx <= mvx_CurrMb3[7:0]; Inter_blk_mvy <= mvy_CurrMb3[7:0]; end + 13:begin Inter_blk_mvx <= mvx_CurrMb3[15:8]; Inter_blk_mvy <= mvy_CurrMb3[15:8]; end + 14:begin Inter_blk_mvx <= mvx_CurrMb3[23:16];Inter_blk_mvy <= mvy_CurrMb3[23:16]; end + 15:begin Inter_blk_mvx <= mvx_CurrMb3[31:24];Inter_blk_mvy <= mvy_CurrMb3[31:24]; end + default:begin Inter_blk_mvx <= 0;Inter_blk_mvy <= 0; end + endcase + endcase + end + //Inter chroma + else if (IsInterChroma) + begin + if (mv_is16x16) + begin Inter_blk_mvx <= mvx_CurrMb0[7:0]; Inter_blk_mvy <= mvy_CurrMb0[7:0]; end + else + case (blk4x4_rec_counter[1:0]) + 2'b00: + if (mv_below8x8_curr) //chroma2x2 prediction + case (Inter_chroma2x2_counter) + 3:begin Inter_blk_mvx <= mvx_CurrMb0[7:0]; Inter_blk_mvy <= mvy_CurrMb0[7:0]; end + 2:begin Inter_blk_mvx <= mvx_CurrMb0[15:8]; Inter_blk_mvy <= mvy_CurrMb0[15:8]; end + 1:begin Inter_blk_mvx <= mvx_CurrMb0[23:16];Inter_blk_mvy <= mvy_CurrMb0[23:16]; end + 0:begin Inter_blk_mvx <= mvx_CurrMb0[31:24];Inter_blk_mvy <= mvy_CurrMb0[31:24]; end + endcase + else //chroma 4x4 prediction + begin Inter_blk_mvx <= mvx_CurrMb0[7:0]; Inter_blk_mvy <= mvy_CurrMb0[7:0]; end + 2'b01: + if (mv_below8x8_curr) //need chroma2x2 prediction + case (Inter_chroma2x2_counter) + 3:begin Inter_blk_mvx <= mvx_CurrMb1[7:0]; Inter_blk_mvy <= mvy_CurrMb1[7:0]; end + 2:begin Inter_blk_mvx <= mvx_CurrMb1[15:8]; Inter_blk_mvy <= mvy_CurrMb1[15:8]; end + 1:begin Inter_blk_mvx <= mvx_CurrMb1[23:16];Inter_blk_mvy <= mvy_CurrMb1[23:16]; end + 0:begin Inter_blk_mvx <= mvx_CurrMb1[31:24];Inter_blk_mvy <= mvy_CurrMb1[31:24]; end + endcase + else //chroma 4x4 prediction + begin Inter_blk_mvx <= mvx_CurrMb1[7:0]; Inter_blk_mvy <= mvy_CurrMb1[7:0]; end + 2'b10: + if (mv_below8x8_curr) //chroma2x2 prediction + case (Inter_chroma2x2_counter) + 3:begin Inter_blk_mvx <= mvx_CurrMb2[7:0]; Inter_blk_mvy <= mvy_CurrMb2[7:0]; end + 2:begin Inter_blk_mvx <= mvx_CurrMb2[15:8]; Inter_blk_mvy <= mvy_CurrMb2[15:8]; end + 1:begin Inter_blk_mvx <= mvx_CurrMb2[23:16];Inter_blk_mvy <= mvy_CurrMb2[23:16]; end + 0:begin Inter_blk_mvx <= mvx_CurrMb2[31:24];Inter_blk_mvy <= mvy_CurrMb2[31:24]; end + endcase + else //chroma 4x4 prediction + begin Inter_blk_mvx <= mvx_CurrMb2[7:0]; Inter_blk_mvy <= mvy_CurrMb2[7:0]; end + 2'b11: + if (mv_below8x8_curr) //chroma2x2 prediction + case (Inter_chroma2x2_counter) + 3:begin Inter_blk_mvx <= mvx_CurrMb3[7:0]; Inter_blk_mvy <= mvy_CurrMb3[7:0]; end + 2:begin Inter_blk_mvx <= mvx_CurrMb3[15:8]; Inter_blk_mvy <= mvy_CurrMb3[15:8]; end + 1:begin Inter_blk_mvx <= mvx_CurrMb3[23:16];Inter_blk_mvy <= mvy_CurrMb3[23:16]; end + 0:begin Inter_blk_mvx <= mvx_CurrMb3[31:24];Inter_blk_mvy <= mvy_CurrMb3[31:24]; end + endcase + else //chroma 4x4 prediction + begin Inter_blk_mvx <= mvx_CurrMb3[7:0]; Inter_blk_mvy <= mvy_CurrMb3[7:0]; end + endcase + end + else + begin Inter_blk_mvx <= 0; Inter_blk_mvy <= 0; end + //---------------------------------------------------------------------------------------- + //Describes the offset of each blk4x4 inside a MB + //---------------------------------------------------------------------------------------- + // xOffset = 0 for 0,2,8, 10 yOffset = 0 for 0, 1, 4, 5 + // xOffset = 4 for 1,3,9, 11 yOffset = 4 for 2, 3, 6, 7 + // xOffset = 8 for 4,6,12,14 yOffset = 8 for 8, 9, 12,13 + // xOffset = 12 for 5,7,13,15 yOffset = 12 for 10,11,14,15 + reg [3:0] xOffsetL,yOffsetL; + always @ (IsInterLuma or mv_below8x8_curr or blk4x4_rec_counter[2] or blk4x4_rec_counter[0]) + if (IsInterLuma) + begin + if (!mv_below8x8_curr) + xOffsetL <= (blk4x4_rec_counter[2])? 4'd8:4'd0; + else + case ({blk4x4_rec_counter[2],blk4x4_rec_counter[0]}) + 2'b00:xOffsetL <= 4'd0; + 2'b01:xOffsetL <= 4'd4; + 2'b10:xOffsetL <= 4'd8; + 2'b11:xOffsetL <= 4'd12; + endcase + end + else + xOffsetL <= 0; + + always @ (IsInterLuma or mv_below8x8_curr or blk4x4_rec_counter[3] or blk4x4_rec_counter[1]) + if (IsInterLuma) + begin + if (!mv_below8x8_curr) + yOffsetL <= (blk4x4_rec_counter[3])? 4'd8:4'd0; + else + case ({blk4x4_rec_counter[3],blk4x4_rec_counter[1]}) + 2'b00:yOffsetL <= 4'd0; + 2'b01:yOffsetL <= 4'd4; + 2'b10:yOffsetL <= 4'd8; + 2'b11:yOffsetL <= 4'd12; + endcase + end + else + yOffsetL <= 0; + + reg [2:0] xOffsetC,yOffsetC; + always @ (IsInterChroma or mv_below8x8_curr or blk4x4_rec_counter[0] or Inter_chroma2x2_counter[0]) + if (IsInterChroma) + begin + if (mv_below8x8_curr == 1'b0) + xOffsetC <= (blk4x4_rec_counter[0] == 1'b0)? 3'd0:3'd4; + else + case (blk4x4_rec_counter[0]) + 1'b0:xOffsetC <= (Inter_chroma2x2_counter[0] == 1'b1)? 3'd0:3'd2; + 1'b1:xOffsetC <= (Inter_chroma2x2_counter[0] == 1'b1)? 3'd4:3'd6; + endcase + end + else + xOffsetC <= 0; + + always @ (IsInterChroma or mv_below8x8_curr or blk4x4_rec_counter[1] or Inter_chroma2x2_counter[1]) + if (IsInterChroma) + begin + if (mv_below8x8_curr == 1'b0) + yOffsetC <= (blk4x4_rec_counter[1] == 1'b0)? 3'd0:3'd4; + else + case (blk4x4_rec_counter[1]) + 1'b0:yOffsetC <= (Inter_chroma2x2_counter[1] == 1'b1)? 3'd0:3'd2; + 1'b1:yOffsetC <= (Inter_chroma2x2_counter[1] == 1'b1)? 3'd4:3'd6; + endcase + end + else + yOffsetC <= 3'd0; + //---------------------------------------------------------------------------------------- + //Integer position of each left-up-most pixel of a 8x8/4x4/2x2 blk + //---------------------------------------------------------------------------------------- + wire [8:0] xIntL_unclip,yIntL_unclip; // 2's complement,bit[8] is the sign bit + wire [7:0] xIntC_unclip,yIntC_unclip; // 2's complement,bit[7] is the sign bit + assign xIntL_unclip = (IsInterLuma)? ({1'b0,mb_num_h,4'b0} + xOffsetL + {{3{Inter_blk_mvx[7]}},Inter_blk_mvx[7:2]}):0; + assign yIntL_unclip = (IsInterLuma)? ({1'b0,mb_num_v,4'b0} + yOffsetL + {{3{Inter_blk_mvy[7]}},Inter_blk_mvy[7:2]}):0; + assign xIntC_unclip = (IsInterChroma)? ({1'b0,mb_num_h,3'b0} + xOffsetC + {{3{Inter_blk_mvx[7]}},Inter_blk_mvx[7:3]}):0; + assign yIntC_unclip = (IsInterChroma)? ({1'b0,mb_num_v,3'b0} + yOffsetC + {{3{Inter_blk_mvy[7]}},Inter_blk_mvy[7:3]}):0; + + wire [8:0] xInt_org_unclip; + wire [8:0] yInt_org_unclip; + assign xInt_org_unclip = (IsInterLuma)? xIntL_unclip:{xIntC_unclip[7],xIntC_unclip}; + assign yInt_org_unclip = (IsInterLuma)? yIntL_unclip:{yIntC_unclip[7],yIntC_unclip}; + assign xInt_org_unclip_1to0 = xInt_org_unclip[1:0]; + //---------------------------------------------------------------------------------------- + //Fractional motion vector for both luma and chroma + //---------------------------------------------------------------------------------------- + wire [3:0] pos_FracL; + wire Is_InterChromaCopy;//If chroma is predicted by direct copy,calculate cycle would reduce + //from 16 cycles to 4 cycles + + assign xFracL = (IsInterLuma)? Inter_blk_mvx[1:0]:0; + assign yFracL = (IsInterLuma)? Inter_blk_mvy[1:0]:0; + assign xFracC = (IsInterChroma)? Inter_blk_mvx[2:0]:0; + assign yFracC = (IsInterChroma)? Inter_blk_mvy[2:0]:0; + assign pos_FracL = {xFracL,yFracL}; + assign Is_InterChromaCopy = (IsInterChroma && xFracC == 0 && yFracC == 0)? 1'b1:1'b0; + + //---------------------------------------------------------------------------------------- + //Inter prediction step control counter + //---------------------------------------------------------------------------------------- + //1.Preload integer pels counter + // If block partition equals 8x8 or above,preload only at first 4x4 block of each 8x8block + // If block partition is 8x4,4x8 or 4x4, preload at each 4x4 block + always @ (posedge clk) + if (reset_n == 1'b0) + blk4x4_inter_preload_counter <= 0; + //luma + else if (trigger_blk4x4_inter_pred && IsInterLuma) + begin + if (!mv_below8x8_curr && blk4x4_rec_counter[1:0] == 2'b00) + case (pos_FracL) + `pos_Int :blk4x4_inter_preload_counter <= (xInt_org_unclip[1:0] == 2'b00)? 6'd17:6'd25; + `pos_f,`pos_q,`pos_i,`pos_k,`pos_j:blk4x4_inter_preload_counter <= 6'd53; + `pos_d,`pos_h,`pos_n :blk4x4_inter_preload_counter <= (xInt_org_unclip[1:0] == 2'b00)? 6'd27:6'd40; + `pos_a,`pos_b,`pos_c :blk4x4_inter_preload_counter <= 6'd33; + `pos_e,`pos_g,`pos_p,`pos_r :blk4x4_inter_preload_counter <= 6'd49; + endcase + else if (mv_below8x8_curr) //partition below 8x8block + case (pos_FracL) + `pos_Int :blk4x4_inter_preload_counter <= (xInt_org_unclip[1:0] == 2'b00)? 6'd5:6'd9; + `pos_f,`pos_q,`pos_i,`pos_k,`pos_j:blk4x4_inter_preload_counter <= 6'd28; + `pos_d,`pos_h,`pos_n :blk4x4_inter_preload_counter <= (xInt_org_unclip[1:0] == 2'b00)? 6'd10:6'd19; + `pos_a,`pos_b,`pos_c :blk4x4_inter_preload_counter <= 6'd13; + `pos_e,`pos_g,`pos_p,`pos_r :blk4x4_inter_preload_counter <= 6'd24; + endcase + end + //chroma + else if (trigger_blk4x4_inter_pred && IsInterChroma && mv_below8x8_curr == 1'b0) + begin + if (xFracC == 0 && yFracC == 0) + blk4x4_inter_preload_counter <= (xInt_org_unclip[1:0] == 2'b00)? 6'd5:6'd9; + else + blk4x4_inter_preload_counter <= 6'd11; + end + else if (trigger_blk2x2_inter_pred && IsInterChroma && mv_below8x8_curr == 1'b1) + begin + if (xFracC == 0 && yFracC == 0) + blk4x4_inter_preload_counter <= (xInt_org_unclip[1:0] == 2'b11)? 6'd5:6'd3; + else + blk4x4_inter_preload_counter <= (xInt_org_unclip[1] == 1'b0 )? 6'd4:6'd7; + end + else if (blk4x4_inter_preload_counter != 0) + blk4x4_inter_preload_counter <= blk4x4_inter_preload_counter - 1; + + //2.Calculate counter + always @ (posedge clk) + if (reset_n == 1'b0) + blk4x4_inter_calculate_counter <= 0; + //luma + else if (IsInterLuma && ((!mv_below8x8_curr && ( + (blk4x4_rec_counter[1:0] == 2'b00 && blk4x4_inter_preload_counter == 1) || + (blk4x4_rec_counter[1:0] != 2'b00 && trigger_blk4x4_inter_pred))) || + (mv_below8x8_curr && blk4x4_inter_preload_counter == 1))) + case (pos_FracL) + `pos_j,`pos_f,`pos_q:blk4x4_inter_calculate_counter <= 4'd5; + `pos_i,`pos_k :blk4x4_inter_calculate_counter <= 4'd8; + default :blk4x4_inter_calculate_counter <= 4'd4; + endcase + //chroma + else if (blk4x4_inter_preload_counter == 1 && IsInterChroma == 1'b1) + case (mv_below8x8_curr) + 1'b0:blk4x4_inter_calculate_counter <= 4'd4; + 1'b1:blk4x4_inter_calculate_counter <= 4'd1; + endcase + else if (blk4x4_inter_calculate_counter != 0) + blk4x4_inter_calculate_counter <= blk4x4_inter_calculate_counter - 1; + + assign end_of_one_blk4x4_inter = (blk4x4_inter_calculate_counter == 4'd1 && + ((IsInterChroma && mv_below8x8_curr && Inter_chroma2x2_counter == 2'b00) || + !(IsInterChroma && mv_below8x8_curr))); + //---------------------------------------------------------------------------------------- + //Inter prediction reference frame RAM read control + //---------------------------------------------------------------------------------------- + assign ref_frame_RAM_rd = ((IsInterLuma || IsInterChroma) && blk4x4_inter_preload_counter != 6'd0 && blk4x4_inter_preload_counter != 6'd1); + + //compared with blk4x4_inter_preload_counter,blk4x4_inter_preload_counter_m2 has some advantages + //during some pos_FracL for vertical memory address decoding + wire [5:0] blk4x4_inter_preload_counter_m2; + assign blk4x4_inter_preload_counter_m2 = (blk4x4_inter_preload_counter == 6'd0 || blk4x4_inter_preload_counter == 6'd1)? + 6'd0:(blk4x4_inter_preload_counter - 2); + + //xInt_curr_offset: offset from the left-upper most pixel of current block,ranging -2 ~ +10. + //After each preload cycle,xInt_curr_offset will increase 4 + reg [4:0] xInt_curr_offset; + always @ (IsInterLuma or mv_below8x8_curr or pos_FracL or xFracC or yFracC + or xInt_org_unclip[1:0] or blk4x4_inter_preload_counter_m2 or blk4x4_inter_preload_counter) + if (blk4x4_inter_preload_counter != 6'd0 && blk4x4_inter_preload_counter != 6'd1) + begin + if (IsInterLuma) + begin + if (!mv_below8x8_curr) + case (pos_FracL) + `pos_f,`pos_q,`pos_i,`pos_k,`pos_j: + case (blk4x4_inter_preload_counter_m2[1:0]) + 2'b00:xInt_curr_offset <= 5'b01010; //+10 + 2'b01:xInt_curr_offset <= 5'b00110; //+6 + 2'b10:xInt_curr_offset <= 5'b00010; //+2 + 2'b11:xInt_curr_offset <= 5'b11110; //-2 + endcase + `pos_d,`pos_h,`pos_n: + if (xInt_org_unclip[1:0] == 2'b00) + xInt_curr_offset <= (blk4x4_inter_preload_counter_m2[0])? 4'b0:4'b0100; //+0 or +4 + else + case (blk4x4_inter_preload_counter_m2) + 6'd38,6'd35,6'd32,6'd29,6'd26,6'd23,6'd20,6'd17,6'd14,6'd11,6'd8,6'd5,6'd2: + xInt_curr_offset <= 5'b0; //+0 + 6'd37,6'd34,6'd31,6'd28,6'd25,6'd22,6'd19,6'd16,6'd13,6'd10,6'd7,6'd4,6'd1: + xInt_curr_offset <= 5'b00100; //+4 + default:xInt_curr_offset <= 5'b01000;//+8 + endcase + `pos_a,`pos_b,`pos_c: + case (blk4x4_inter_preload_counter_m2[1:0]) + 2'b00:xInt_curr_offset <= 5'b01010; //+10 + 2'b01:xInt_curr_offset <= 5'b00110; //+6 + 2'b10:xInt_curr_offset <= 5'b00010; //+2 + 2'b11:xInt_curr_offset <= 5'b11110; //-2 + endcase + `pos_Int: + if (xInt_org_unclip[1:0] == 2'b00) + xInt_curr_offset <= (blk4x4_inter_preload_counter_m2[0])? 5'b0:5'b0100; //+0 or +4 + else + case (blk4x4_inter_preload_counter_m2) + 6'd23,6'd20,6'd17,6'd14,6'd11,6'd8,6'd5,6'd2: + xInt_curr_offset <= 5'b00000; //+0 + 6'd22,6'd19,6'd16,6'd13,6'd10,6'd7,6'd4,6'd1: + xInt_curr_offset <= 5'b00100; //+4 + default:xInt_curr_offset <= 5'b01000;//+8 + endcase + `pos_e,`pos_g,`pos_p,`pos_r: + case (blk4x4_inter_preload_counter_m2) + 6'd47,6'd44,6'd5,6'd2: + xInt_curr_offset <= 5'b00000; //+0 + 6'd46,6'd43,6'd4,6'd1: + xInt_curr_offset <= 5'b00100; //+4 + 6'd45,6'd42,6'd3,6'd0: + xInt_curr_offset <= 5'b01000; //+8 + default: + case (blk4x4_inter_preload_counter_m2[1:0]) + 2'b00:xInt_curr_offset <= 5'b00010; //+2 + 2'b01:xInt_curr_offset <= 5'b11110; //-2 + 2'b10:xInt_curr_offset <= 5'b01010; //+10 + 2'b11:xInt_curr_offset <= 5'b00110; //+6 + endcase + endcase + endcase + else //block partition below 8x8 + case (pos_FracL) + `pos_f,`pos_q,`pos_i,`pos_k,`pos_j: + case (blk4x4_inter_preload_counter_m2) + 6'd26,6'd23,6'd20,6'd17,6'd14,6'd11,6'd8,6'd5,6'd2:xInt_curr_offset <= 5'b11110;//-2 + 6'd25,6'd22,6'd19,6'd16,6'd13,6'd10,6'd7,6'd4,6'd1:xInt_curr_offset <= 5'b00010;//+2 + default:xInt_curr_offset <= 5'b00110; //+6 + endcase + `pos_d,`pos_h,`pos_n: + if (xInt_org_unclip[1:0] == 2'b00) + xInt_curr_offset <= 5'b0; //+0 + else + xInt_curr_offset <= (blk4x4_inter_preload_counter_m2[0])? 5'b0:5'b00100;//+0 or +4 + `pos_a,`pos_b,`pos_c: + case (blk4x4_inter_preload_counter_m2) + 6'd11,6'd8,6'd5,6'd2:xInt_curr_offset <= 5'b11110; //-2 + 6'd10,6'd7,6'd4,6'd1:xInt_curr_offset <= 5'b00010; //+2 + default:xInt_curr_offset <= 5'b00110; //+6 + endcase + `pos_Int: + if (xInt_org_unclip[1:0] == 2'b00) + xInt_curr_offset <= 5'b0; //+0 + else + xInt_curr_offset <= (blk4x4_inter_preload_counter_m2[0])? 5'b0:5'b00100; //+0 or +4 + `pos_e,`pos_g,`pos_p,`pos_r: + case (blk4x4_inter_preload_counter_m2) + 6'd22,6'd20,6'd3,6'd1:xInt_curr_offset <= 5'b0; //+0 + 6'd21,6'd19,6'd2,6'd0:xInt_curr_offset <= 5'b00100; //+4 + 6'd18,6'd15,6'd12,6'd9,6'd6:xInt_curr_offset <= 5'b11110;//-2 + 6'd17,6'd14,6'd11,6'd8,6'd5:xInt_curr_offset <= 5'b00010;//+2 + 6'd16,6'd13,6'd10,6'd7,6'd4:xInt_curr_offset <= 5'b00110;//+6 + default:xInt_curr_offset <= 5'b0; + endcase + endcase + end + else //IsInterChroma + begin + if (!mv_below8x8_curr) + begin + if (xFracC == 0 && yFracC == 0) + begin + if (xInt_org_unclip[1:0] == 2'b00) + xInt_curr_offset <= 5'b0; + else + xInt_curr_offset <= (blk4x4_inter_preload_counter_m2[0] == 1'b1)? 5'b0:5'b0100; + end + else + xInt_curr_offset <= (blk4x4_inter_preload_counter_m2[0] == 1'b1)? 5'b0:5'b0100; + end + else //mv_below8x8_curr == 1'b1 + begin + if (xFracC == 0 && yFracC == 0) + begin + if (xInt_org_unclip[1:0] == 2'b11) // 4 preload cycles + xInt_curr_offset <= (blk4x4_inter_preload_counter_m2[0] == 1'b1)? 5'b0:5'b0100; + else + xInt_curr_offset <= 0; + end + else + begin + if (xInt_org_unclip[1] == 1'b0) + xInt_curr_offset <= 0; + else + xInt_curr_offset <= (blk4x4_inter_preload_counter_m2[0] == 1'b1)? 5'b0:5'b0100; + end + end + end + end + else //blk4x4_inter_preload_counter == 0 || blk4x4_inter_preload_counter == 1 + xInt_curr_offset <= 5'b0; + + //Derive unclipped x pos for each preload cycle + wire [8:0] xInt_addr_unclip; + assign xInt_addr_unclip = xInt_org_unclip + {{4{xInt_curr_offset[4]}},xInt_curr_offset}; + + //x addr clipped:x address in pixels + reg [7:0] xInt_addr; + always @ (xInt_addr_unclip or IsInterLuma or IsInterChroma) + if (xInt_addr_unclip[8] == 1'b1) //negative + xInt_addr <= 0; + else if (IsInterLuma) + xInt_addr <= (xInt_addr_unclip[7:0] > (`pic_width - 4))? 8'd172:xInt_addr_unclip[7:0]; + else if (IsInterChroma) + xInt_addr <= (xInt_addr_unclip[7:0] > (`half_pic_width - 4))? 8'd84:xInt_addr_unclip[7:0]; + else + xInt_addr <= 0; + + //yInt_p1:when loading from Xth line to (X-1)th line,yInt_p1 is set to 1'b1 at the last + //loading cycle of current Xth line + reg yInt_p1; + always @ (IsInterLuma or mv_below8x8_curr or pos_FracL or xFracC or yFracC + or blk4x4_inter_preload_counter or blk4x4_inter_preload_counter_m2 or xInt_org_unclip[1:0] or xInt_org_unclip[1]) + if (blk4x4_inter_preload_counter != 6'd0 && blk4x4_inter_preload_counter != 6'd1) + begin + if (IsInterLuma) + case (mv_below8x8_curr) + 1'b0: + case (pos_FracL) + `pos_f,`pos_q,`pos_i,`pos_k,`pos_j: + yInt_p1 <= (blk4x4_inter_preload_counter_m2[1:0] == 2'b00)? 1'b1:1'b0; + `pos_d,`pos_h,`pos_n: + if (xInt_org_unclip[1:0] == 2'b00) + yInt_p1 <= (blk4x4_inter_preload_counter_m2[0] == 1'b0)? 1'b1:1'b0; + else + case (blk4x4_inter_preload_counter_m2) + 6'd36,6'd33,6'd30,6'd27,6'd24,6'd21,6'd18,6'd15,6'd12,6'd9,6'd6,6'd3,6'd0: + yInt_p1 <= 1'b1; + default:yInt_p1 <= 1'b0; + endcase + `pos_a,`pos_b,`pos_c: + yInt_p1 <= (blk4x4_inter_preload_counter_m2[1:0] == 2'b00)? 1'b1:1'b0; + `pos_Int: + if (xInt_org_unclip[1:0] == 2'b00) + yInt_p1 <= (blk4x4_inter_preload_counter_m2[0] == 1'b0)? 1'b1:1'b0; + else + case (blk4x4_inter_preload_counter_m2) + 6'd21,6'd18,6'd15,6'd12,6'd9,6'd6,6'd3,6'd0:yInt_p1 <= 1'b1; + default: yInt_p1 <= 1'b0; + endcase + `pos_e,`pos_g,`pos_p,`pos_r: + case (blk4x4_inter_preload_counter_m2) + 6'd45,6'd42,6'd3,6'd0:yInt_p1 <= 1'b1; + 6'd6,6'd10,6'd14,6'd18,6'd22,6'd26,6'd30,6'd34,6'd38:yInt_p1 <= 1'b1; + default:yInt_p1 <= 1'b0; + endcase + endcase + 1'b1: //block partition below 8x8 + case (pos_FracL) + `pos_f,`pos_q,`pos_i,`pos_k,`pos_j: + case (blk4x4_inter_preload_counter_m2) + 6'd24,6'd21,6'd18,6'd15,6'd12,6'd9,6'd6,6'd3,6'd0:yInt_p1 <= 1'b1; + default:yInt_p1 <= 1'b0; + endcase + `pos_d,`pos_h,`pos_n: + if (xInt_org_unclip[1:0] == 2'b00) + yInt_p1 <= 1'b1; + else + yInt_p1 <= (blk4x4_inter_preload_counter_m2[0] == 1'b0)? 1'b1:1'b0; + `pos_a,`pos_b,`pos_c: + case (blk4x4_inter_preload_counter_m2) + 5'd9,5'd6,5'd3,5'd0 :yInt_p1 <= 1'b1; + default :yInt_p1 <= 1'b0; + endcase + `pos_Int: + if (xInt_org_unclip[1:0] == 2'b00) + yInt_p1 <= 1'b1; + else + yInt_p1 <= (blk4x4_inter_preload_counter_m2[0] == 1'b0)? 1'b1:1'b0; + `pos_e,`pos_g,`pos_p,`pos_r: + case (blk4x4_inter_preload_counter_m2) + 6'd21,6'd19,6'd2,6'd0 :yInt_p1 <= 1'b1; + 6'd4,6'd7,6'd10,6'd13,6'd16 :yInt_p1 <= 1'b1; + default :yInt_p1 <= 1'b0; + endcase + endcase + endcase + else //IsInterChroma + case (mv_below8x8_curr) + 1'b0: + if (xFracC == 0 && yFracC == 0) + begin + if (xInt_org_unclip[1:0] == 2'b00) + yInt_p1 <= 1'b1; + else + yInt_p1 <= (blk4x4_inter_preload_counter_m2[0] == 1'b0)? 1'b1:1'b0; + end + else + yInt_p1 <= (blk4x4_inter_preload_counter_m2[0] == 1'b0)? 1'b1:1'b0; + 1'b1: + if (xFracC == 0 && yFracC == 0) + begin + if (xInt_org_unclip[1:0] != 2'b11) + yInt_p1 <= 1'b1; + else + yInt_p1 <= (blk4x4_inter_preload_counter_m2[0] == 1'b0)? 1'b1:1'b0; + end + else + begin + if (xInt_org_unclip[1] == 1'b0) + yInt_p1 <= 1'b1; + else + yInt_p1 <= (blk4x4_inter_preload_counter_m2[0] == 1'b0)? 1'b1:1'b0; + end + endcase + end + else // blk4x4_inter_preload_counter == 0 || blk4x4_inter_preload_counter == 1 + yInt_p1 <= 1'b0; + + //Derive unclipped y pos for each preload cycle + reg [8:0] yInt_addr_unclip; + always @ (posedge clk) + if (reset_n == 1'b0) + yInt_addr_unclip <= 0; + else if ((IsInterLuma && (trigger_blk4x4_inter_pred && (mv_below8x8_curr || + (!mv_below8x8_curr && blk4x4_rec_counter[1:0] == 2'b00)))) || + (IsInterChroma && (!mv_below8x8_curr && trigger_blk4x4_inter_pred) || + (mv_below8x8_curr && trigger_blk2x2_inter_pred))) + begin + if (IsInterLuma) //Luma + case (pos_FracL) + `pos_a,`pos_b,`pos_c,`pos_Int: + yInt_addr_unclip <= yInt_org_unclip; + default: //need -2 here + yInt_addr_unclip <= yInt_org_unclip + 9'b111111110; + endcase + else //Chroma + yInt_addr_unclip <= yInt_org_unclip; + end + else if (blk4x4_inter_preload_counter_m2 != 0 && yInt_p1 == 1'b1) + yInt_addr_unclip <= yInt_addr_unclip + 1; + + //y addr clipped + reg [7:0] yInt_addr; + always @ (yInt_addr_unclip or IsInterLuma or IsInterChroma) + if (yInt_addr_unclip[8] == 1'b1) //negative + yInt_addr <= 0; + else if (IsInterLuma) + yInt_addr <= (yInt_addr_unclip[7:0] > (`pic_height - 1))? 8'd143:yInt_addr_unclip[7:0]; + else if (IsInterChroma) + yInt_addr <= (yInt_addr_unclip[7:0] > (`half_pic_height - 1))? 8'd71:yInt_addr_unclip[7:0]; + else + yInt_addr <= 0; + + wire [12:0] offset_constant; + wire [10:0] yInt_addr_x11; + wire [12:0] offset_yInt_addr; + assign offset_constant = (IsInterLuma)? 0:((IsInterChroma)? ((blk4x4_rec_counter < 5'd20)? 13'd6336:13'd7920):0); + assign yInt_addr_x11 = {yInt_addr,3'b0} + {2'b0,yInt_addr,1'b0} + {3'b0,yInt_addr}; + assign offset_yInt_addr = (IsInterLuma)? {yInt_addr_x11,2'b0}:{1'b0,yInt_addr_x11,1'b0}; + assign ref_frame_RAM_rd_addr = (offset_constant + {8'b0,xInt_addr[7:2]}) + {1'b0,offset_yInt_addr}; + + //---------------------------------------------------------------------------------------- + //Inter prediction output control: from LPE or from CPE + //---------------------------------------------------------------------------------------- + always @ (IsInterLuma or IsInterChroma or Is_InterChromaCopy + or blk4x4_inter_calculate_counter or pos_FracL + or Inter_pix_copy0 or Inter_pix_copy1 or Inter_pix_copy2 or Inter_pix_copy3 + or LPE0_out or LPE1_out or LPE2_out or LPE3_out + or CPE0_out or CPE1_out or CPE2_out or CPE3_out) + if (IsInterLuma && blk4x4_inter_calculate_counter != 0) + begin + Inter_blk4x4_pred_output_valid <= 2'b01; + case (pos_FracL) + `pos_Int: + begin + Inter_pred_out0 <= Inter_pix_copy0;Inter_pred_out1 <= Inter_pix_copy1; + Inter_pred_out2 <= Inter_pix_copy2;Inter_pred_out3 <= Inter_pix_copy3; + end + `pos_i,`pos_k: + if (blk4x4_inter_calculate_counter == 4'd7 || blk4x4_inter_calculate_counter == 4'd5 || + blk4x4_inter_calculate_counter == 4'd3 || blk4x4_inter_calculate_counter == 4'd1) + begin + Inter_pred_out0 <= LPE0_out;Inter_pred_out1 <= LPE1_out; + Inter_pred_out2 <= LPE2_out;Inter_pred_out3 <= LPE3_out; + end + else + begin + Inter_pred_out0 <= 0;Inter_pred_out1 <= 0;Inter_pred_out2 <= 0;Inter_pred_out3 <= 0; + end + default: + if (blk4x4_inter_calculate_counter == 4'd4 || blk4x4_inter_calculate_counter == 4'd3 || + blk4x4_inter_calculate_counter == 4'd2 || blk4x4_inter_calculate_counter == 4'd1) + begin + Inter_pred_out0 <= LPE0_out;Inter_pred_out1 <= LPE1_out; + Inter_pred_out2 <= LPE2_out;Inter_pred_out3 <= LPE3_out; + end + else + begin + Inter_pred_out0 <= 0;Inter_pred_out1 <= 0;Inter_pred_out2 <= 0;Inter_pred_out3 <= 0; + end + endcase + end + else if (IsInterChroma && blk4x4_inter_calculate_counter != 0) + begin + Inter_pred_out0 <= (Is_InterChromaCopy)? Inter_pix_copy0:CPE0_out; + Inter_pred_out1 <= (Is_InterChromaCopy)? Inter_pix_copy1:CPE1_out; + Inter_pred_out2 <= (Is_InterChromaCopy)? Inter_pix_copy2:CPE2_out; + Inter_pred_out3 <= (Is_InterChromaCopy)? Inter_pix_copy3:CPE3_out; + Inter_blk4x4_pred_output_valid <= 2'b10; + end + else + begin + Inter_pred_out0 <= 0;Inter_pred_out1 <= 0;Inter_pred_out2 <= 0;Inter_pred_out3 <= 0; + Inter_blk4x4_pred_output_valid <= 2'b00; + end +endmodule + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/Inter_pred_reg_ctrl.v b/demo_chip_rtl/rtl/nova/tags/Start/src/Inter_pred_reg_ctrl.v new file mode 100644 index 0000000..6a059aa --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/Inter_pred_reg_ctrl.v @@ -0,0 +1,1699 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : Inter_pred_reg_ctrl.v +// Generated : Oct 17, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Prepare the appropriate registers for Inter prediction (luma & chroma) +// Including padding +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module Inter_pred_reg_ctrl (gclk_Inter_ref_rf,reset_n,blk4x4_inter_preload_counter,ref_frame_RAM_dout, + IsInterLuma,IsInterChroma,xInt_addr_unclip,xInt_org_unclip_1to0,pos_FracL,xFracC,yFracC,mv_below8x8_curr, + + Inter_ref_00_00,Inter_ref_01_00,Inter_ref_02_00,Inter_ref_03_00,Inter_ref_04_00,Inter_ref_05_00, + Inter_ref_06_00,Inter_ref_07_00,Inter_ref_08_00,Inter_ref_09_00,Inter_ref_10_00,Inter_ref_11_00,Inter_ref_12_00, + Inter_ref_00_01,Inter_ref_01_01,Inter_ref_02_01,Inter_ref_03_01,Inter_ref_04_01,Inter_ref_05_01, + Inter_ref_06_01,Inter_ref_07_01,Inter_ref_08_01,Inter_ref_09_01,Inter_ref_10_01,Inter_ref_11_01,Inter_ref_12_01, + Inter_ref_00_02,Inter_ref_01_02,Inter_ref_02_02,Inter_ref_03_02,Inter_ref_04_02,Inter_ref_05_02, + Inter_ref_06_02,Inter_ref_07_02,Inter_ref_08_02,Inter_ref_09_02,Inter_ref_10_02,Inter_ref_11_02,Inter_ref_12_02, + Inter_ref_00_03,Inter_ref_01_03,Inter_ref_02_03,Inter_ref_03_03,Inter_ref_04_03,Inter_ref_05_03, + Inter_ref_06_03,Inter_ref_07_03,Inter_ref_08_03,Inter_ref_09_03,Inter_ref_10_03,Inter_ref_11_03,Inter_ref_12_03, + Inter_ref_00_04,Inter_ref_01_04,Inter_ref_02_04,Inter_ref_03_04,Inter_ref_04_04,Inter_ref_05_04, + Inter_ref_06_04,Inter_ref_07_04,Inter_ref_08_04,Inter_ref_09_04,Inter_ref_10_04,Inter_ref_11_04,Inter_ref_12_04, + Inter_ref_00_05,Inter_ref_01_05,Inter_ref_02_05,Inter_ref_03_05,Inter_ref_04_05,Inter_ref_05_05, + Inter_ref_06_05,Inter_ref_07_05,Inter_ref_08_05,Inter_ref_09_05,Inter_ref_10_05,Inter_ref_11_05,Inter_ref_12_05, + Inter_ref_00_06,Inter_ref_01_06,Inter_ref_02_06,Inter_ref_03_06,Inter_ref_04_06,Inter_ref_05_06, + Inter_ref_06_06,Inter_ref_07_06,Inter_ref_08_06,Inter_ref_09_06,Inter_ref_10_06,Inter_ref_11_06,Inter_ref_12_06, + Inter_ref_00_07,Inter_ref_01_07,Inter_ref_02_07,Inter_ref_03_07,Inter_ref_04_07,Inter_ref_05_07, + Inter_ref_06_07,Inter_ref_07_07,Inter_ref_08_07,Inter_ref_09_07,Inter_ref_10_07,Inter_ref_11_07,Inter_ref_12_07, + Inter_ref_00_08,Inter_ref_01_08,Inter_ref_02_08,Inter_ref_03_08,Inter_ref_04_08,Inter_ref_05_08, + Inter_ref_06_08,Inter_ref_07_08,Inter_ref_08_08,Inter_ref_09_08,Inter_ref_10_08,Inter_ref_11_08,Inter_ref_12_08, + Inter_ref_00_09,Inter_ref_01_09,Inter_ref_02_09,Inter_ref_03_09,Inter_ref_04_09,Inter_ref_05_09, + Inter_ref_06_09,Inter_ref_07_09,Inter_ref_08_09,Inter_ref_09_09,Inter_ref_10_09,Inter_ref_11_09,Inter_ref_12_09, + Inter_ref_00_10,Inter_ref_01_10,Inter_ref_02_10,Inter_ref_03_10,Inter_ref_04_10,Inter_ref_05_10, + Inter_ref_06_10,Inter_ref_07_10,Inter_ref_08_10,Inter_ref_09_10,Inter_ref_10_10,Inter_ref_11_10,Inter_ref_12_10, + Inter_ref_00_11,Inter_ref_01_11,Inter_ref_02_11,Inter_ref_03_11,Inter_ref_04_11,Inter_ref_05_11, + Inter_ref_06_11,Inter_ref_07_11,Inter_ref_08_11,Inter_ref_09_11,Inter_ref_10_11,Inter_ref_11_11,Inter_ref_12_11, + Inter_ref_00_12,Inter_ref_01_12,Inter_ref_02_12,Inter_ref_03_12,Inter_ref_04_12,Inter_ref_05_12, + Inter_ref_06_12,Inter_ref_07_12,Inter_ref_08_12,Inter_ref_09_12,Inter_ref_10_12,Inter_ref_11_12,Inter_ref_12_12); + + input gclk_Inter_ref_rf; + input reset_n; + input [5:0] blk4x4_inter_preload_counter; + input [31:0] ref_frame_RAM_dout; + input IsInterLuma,IsInterChroma; + input [8:0] xInt_addr_unclip; + input [1:0] xInt_org_unclip_1to0; + input [3:0] pos_FracL; + input [2:0] xFracC,yFracC; + input mv_below8x8_curr; + + output [7:0] Inter_ref_00_00,Inter_ref_01_00,Inter_ref_02_00,Inter_ref_03_00,Inter_ref_04_00,Inter_ref_05_00; + output [7:0] Inter_ref_06_00,Inter_ref_07_00,Inter_ref_08_00,Inter_ref_09_00,Inter_ref_10_00,Inter_ref_11_00,Inter_ref_12_00; + output [7:0] Inter_ref_00_01,Inter_ref_01_01,Inter_ref_02_01,Inter_ref_03_01,Inter_ref_04_01,Inter_ref_05_01; + output [7:0] Inter_ref_06_01,Inter_ref_07_01,Inter_ref_08_01,Inter_ref_09_01,Inter_ref_10_01,Inter_ref_11_01,Inter_ref_12_01; + output [7:0] Inter_ref_00_02,Inter_ref_01_02,Inter_ref_02_02,Inter_ref_03_02,Inter_ref_04_02,Inter_ref_05_02; + output [7:0] Inter_ref_06_02,Inter_ref_07_02,Inter_ref_08_02,Inter_ref_09_02,Inter_ref_10_02,Inter_ref_11_02,Inter_ref_12_02; + output [7:0] Inter_ref_00_03,Inter_ref_01_03,Inter_ref_02_03,Inter_ref_03_03,Inter_ref_04_03,Inter_ref_05_03; + output [7:0] Inter_ref_06_03,Inter_ref_07_03,Inter_ref_08_03,Inter_ref_09_03,Inter_ref_10_03,Inter_ref_11_03,Inter_ref_12_03; + output [7:0] Inter_ref_00_04,Inter_ref_01_04,Inter_ref_02_04,Inter_ref_03_04,Inter_ref_04_04,Inter_ref_05_04; + output [7:0] Inter_ref_06_04,Inter_ref_07_04,Inter_ref_08_04,Inter_ref_09_04,Inter_ref_10_04,Inter_ref_11_04,Inter_ref_12_04; + output [7:0] Inter_ref_00_05,Inter_ref_01_05,Inter_ref_02_05,Inter_ref_03_05,Inter_ref_04_05,Inter_ref_05_05; + output [7:0] Inter_ref_06_05,Inter_ref_07_05,Inter_ref_08_05,Inter_ref_09_05,Inter_ref_10_05,Inter_ref_11_05,Inter_ref_12_05; + output [7:0] Inter_ref_00_06,Inter_ref_01_06,Inter_ref_02_06,Inter_ref_03_06,Inter_ref_04_06,Inter_ref_05_06; + output [7:0] Inter_ref_06_06,Inter_ref_07_06,Inter_ref_08_06,Inter_ref_09_06,Inter_ref_10_06,Inter_ref_11_06,Inter_ref_12_06; + output [7:0] Inter_ref_00_07,Inter_ref_01_07,Inter_ref_02_07,Inter_ref_03_07,Inter_ref_04_07,Inter_ref_05_07; + output [7:0] Inter_ref_06_07,Inter_ref_07_07,Inter_ref_08_07,Inter_ref_09_07,Inter_ref_10_07,Inter_ref_11_07,Inter_ref_12_07; + output [7:0] Inter_ref_00_08,Inter_ref_01_08,Inter_ref_02_08,Inter_ref_03_08,Inter_ref_04_08,Inter_ref_05_08; + output [7:0] Inter_ref_06_08,Inter_ref_07_08,Inter_ref_08_08,Inter_ref_09_08,Inter_ref_10_08,Inter_ref_11_08,Inter_ref_12_08; + output [7:0] Inter_ref_00_09,Inter_ref_01_09,Inter_ref_02_09,Inter_ref_03_09,Inter_ref_04_09,Inter_ref_05_09; + output [7:0] Inter_ref_06_09,Inter_ref_07_09,Inter_ref_08_09,Inter_ref_09_09,Inter_ref_10_09,Inter_ref_11_09,Inter_ref_12_09; + output [7:0] Inter_ref_00_10,Inter_ref_01_10,Inter_ref_02_10,Inter_ref_03_10,Inter_ref_04_10,Inter_ref_05_10; + output [7:0] Inter_ref_06_10,Inter_ref_07_10,Inter_ref_08_10,Inter_ref_09_10,Inter_ref_10_10,Inter_ref_11_10,Inter_ref_12_10; + output [7:0] Inter_ref_00_11,Inter_ref_01_11,Inter_ref_02_11,Inter_ref_03_11,Inter_ref_04_11,Inter_ref_05_11; + output [7:0] Inter_ref_06_11,Inter_ref_07_11,Inter_ref_08_11,Inter_ref_09_11,Inter_ref_10_11,Inter_ref_11_11,Inter_ref_12_11; + output [7:0] Inter_ref_00_12,Inter_ref_01_12,Inter_ref_02_12,Inter_ref_03_12,Inter_ref_04_12,Inter_ref_05_12; + output [7:0] Inter_ref_06_12,Inter_ref_07_12,Inter_ref_08_12,Inter_ref_09_12,Inter_ref_10_12,Inter_ref_11_12,Inter_ref_12_12; + + reg [7:0] Inter_ref_00_00,Inter_ref_01_00,Inter_ref_02_00,Inter_ref_03_00,Inter_ref_04_00,Inter_ref_05_00; + reg [7:0] Inter_ref_06_00,Inter_ref_07_00,Inter_ref_08_00,Inter_ref_09_00,Inter_ref_10_00,Inter_ref_11_00,Inter_ref_12_00; + reg [7:0] Inter_ref_00_01,Inter_ref_01_01,Inter_ref_02_01,Inter_ref_03_01,Inter_ref_04_01,Inter_ref_05_01; + reg [7:0] Inter_ref_06_01,Inter_ref_07_01,Inter_ref_08_01,Inter_ref_09_01,Inter_ref_10_01,Inter_ref_11_01,Inter_ref_12_01; + reg [7:0] Inter_ref_00_02,Inter_ref_01_02,Inter_ref_02_02,Inter_ref_03_02,Inter_ref_04_02,Inter_ref_05_02; + reg [7:0] Inter_ref_06_02,Inter_ref_07_02,Inter_ref_08_02,Inter_ref_09_02,Inter_ref_10_02,Inter_ref_11_02,Inter_ref_12_02; + reg [7:0] Inter_ref_00_03,Inter_ref_01_03,Inter_ref_02_03,Inter_ref_03_03,Inter_ref_04_03,Inter_ref_05_03; + reg [7:0] Inter_ref_06_03,Inter_ref_07_03,Inter_ref_08_03,Inter_ref_09_03,Inter_ref_10_03,Inter_ref_11_03,Inter_ref_12_03; + reg [7:0] Inter_ref_00_04,Inter_ref_01_04,Inter_ref_02_04,Inter_ref_03_04,Inter_ref_04_04,Inter_ref_05_04; + reg [7:0] Inter_ref_06_04,Inter_ref_07_04,Inter_ref_08_04,Inter_ref_09_04,Inter_ref_10_04,Inter_ref_11_04,Inter_ref_12_04; + reg [7:0] Inter_ref_00_05,Inter_ref_01_05,Inter_ref_02_05,Inter_ref_03_05,Inter_ref_04_05,Inter_ref_05_05; + reg [7:0] Inter_ref_06_05,Inter_ref_07_05,Inter_ref_08_05,Inter_ref_09_05,Inter_ref_10_05,Inter_ref_11_05,Inter_ref_12_05; + reg [7:0] Inter_ref_00_06,Inter_ref_01_06,Inter_ref_02_06,Inter_ref_03_06,Inter_ref_04_06,Inter_ref_05_06; + reg [7:0] Inter_ref_06_06,Inter_ref_07_06,Inter_ref_08_06,Inter_ref_09_06,Inter_ref_10_06,Inter_ref_11_06,Inter_ref_12_06; + reg [7:0] Inter_ref_00_07,Inter_ref_01_07,Inter_ref_02_07,Inter_ref_03_07,Inter_ref_04_07,Inter_ref_05_07; + reg [7:0] Inter_ref_06_07,Inter_ref_07_07,Inter_ref_08_07,Inter_ref_09_07,Inter_ref_10_07,Inter_ref_11_07,Inter_ref_12_07; + reg [7:0] Inter_ref_00_08,Inter_ref_01_08,Inter_ref_02_08,Inter_ref_03_08,Inter_ref_04_08,Inter_ref_05_08; + reg [7:0] Inter_ref_06_08,Inter_ref_07_08,Inter_ref_08_08,Inter_ref_09_08,Inter_ref_10_08,Inter_ref_11_08,Inter_ref_12_08; + reg [7:0] Inter_ref_00_09,Inter_ref_01_09,Inter_ref_02_09,Inter_ref_03_09,Inter_ref_04_09,Inter_ref_05_09; + reg [7:0] Inter_ref_06_09,Inter_ref_07_09,Inter_ref_08_09,Inter_ref_09_09,Inter_ref_10_09,Inter_ref_11_09,Inter_ref_12_09; + reg [7:0] Inter_ref_00_10,Inter_ref_01_10,Inter_ref_02_10,Inter_ref_03_10,Inter_ref_04_10,Inter_ref_05_10; + reg [7:0] Inter_ref_06_10,Inter_ref_07_10,Inter_ref_08_10,Inter_ref_09_10,Inter_ref_10_10,Inter_ref_11_10,Inter_ref_12_10; + reg [7:0] Inter_ref_00_11,Inter_ref_01_11,Inter_ref_02_11,Inter_ref_03_11,Inter_ref_04_11,Inter_ref_05_11; + reg [7:0] Inter_ref_06_11,Inter_ref_07_11,Inter_ref_08_11,Inter_ref_09_11,Inter_ref_10_11,Inter_ref_11_11,Inter_ref_12_11; + reg [7:0] Inter_ref_00_12,Inter_ref_01_12,Inter_ref_02_12,Inter_ref_03_12,Inter_ref_04_12,Inter_ref_05_12; + reg [7:0] Inter_ref_06_12,Inter_ref_07_12,Inter_ref_08_12,Inter_ref_09_12,Inter_ref_10_12,Inter_ref_11_12,Inter_ref_12_12; + + //------------------------------------------------------------------------- + //out of bound padding + //------------------------------------------------------------------------- + //In original version where ext_frame_RAM is read async,no need to latch xInt_addr_unclip + //since it is used here in the same cycle as it is generated in Inter_pred_pipeline module. + //However,when ext_frame_RAM is changed to sync read,xInt_addr_unclip will be used one cyle later. + reg [8:0] xInt_addr_unclip_reg; + always @ (posedge gclk_Inter_ref_rf or negedge reset_n) + if (reset_n == 1'b0) + xInt_addr_unclip_reg <= 0; + else + xInt_addr_unclip_reg <= xInt_addr_unclip; + + reg [31:0] RefFrameOutPadding; + always @ (xInt_addr_unclip_reg or ref_frame_RAM_dout or IsInterLuma or IsInterChroma) + if (xInt_addr_unclip_reg[8] == 1'b1) //out of left bound + RefFrameOutPadding <= {ref_frame_RAM_dout[7:0],ref_frame_RAM_dout[7:0], + ref_frame_RAM_dout[7:0],ref_frame_RAM_dout[7:0]}; + else + begin + if ((IsInterLuma && xInt_addr_unclip_reg[7:2] > 6'b101011) || //out of right bound + (IsInterChroma && xInt_addr_unclip_reg[7:2] > 6'b010101)) + RefFrameOutPadding <= {ref_frame_RAM_dout[31:24],ref_frame_RAM_dout[31:24], + ref_frame_RAM_dout[31:24],ref_frame_RAM_dout[31:24]}; + else + RefFrameOutPadding <= ref_frame_RAM_dout; + end + //------------------------------------------------------------------------- + //Inter_ref_00_00 ~ Inter_ref_12_12 + //------------------------------------------------------------------------- + always @ (posedge gclk_Inter_ref_rf or negedge reset_n) + if (reset_n == 0) + begin + Inter_ref_00_00 <= 0;Inter_ref_01_00 <= 0;Inter_ref_02_00 <= 0;Inter_ref_03_00 <= 0; + Inter_ref_04_00 <= 0;Inter_ref_05_00 <= 0;Inter_ref_06_00 <= 0;Inter_ref_07_00 <= 0; + Inter_ref_08_00 <= 0;Inter_ref_09_00 <= 0;Inter_ref_10_00 <= 0;Inter_ref_11_00 <= 0;Inter_ref_12_00 <= 0; + Inter_ref_00_01 <= 0;Inter_ref_01_01 <= 0;Inter_ref_02_01 <= 0;Inter_ref_03_01 <= 0; + Inter_ref_04_01 <= 0;Inter_ref_05_01 <= 0;Inter_ref_06_01 <= 0;Inter_ref_07_01 <= 0; + Inter_ref_08_01 <= 0;Inter_ref_09_01 <= 0;Inter_ref_10_01 <= 0;Inter_ref_11_01 <= 0;Inter_ref_12_01 <= 0; + Inter_ref_00_02 <= 0;Inter_ref_01_02 <= 0;Inter_ref_02_02 <= 0;Inter_ref_03_02 <= 0; + Inter_ref_04_02 <= 0;Inter_ref_05_02 <= 0;Inter_ref_06_02 <= 0;Inter_ref_07_02 <= 0; + Inter_ref_08_02 <= 0;Inter_ref_09_02 <= 0;Inter_ref_10_02 <= 0;Inter_ref_11_02 <= 0;Inter_ref_12_02 <= 0; + Inter_ref_00_03 <= 0;Inter_ref_01_03 <= 0;Inter_ref_02_03 <= 0;Inter_ref_03_03 <= 0; + Inter_ref_04_03 <= 0;Inter_ref_05_03 <= 0;Inter_ref_06_03 <= 0;Inter_ref_07_03 <= 0; + Inter_ref_08_03 <= 0;Inter_ref_09_03 <= 0;Inter_ref_10_03 <= 0;Inter_ref_11_03 <= 0;Inter_ref_12_03 <= 0; + Inter_ref_00_04 <= 0;Inter_ref_01_04 <= 0;Inter_ref_02_04 <= 0;Inter_ref_03_04 <= 0; + Inter_ref_04_04 <= 0;Inter_ref_05_04 <= 0;Inter_ref_06_04 <= 0;Inter_ref_07_04 <= 0; + Inter_ref_08_04 <= 0;Inter_ref_09_04 <= 0;Inter_ref_10_04 <= 0;Inter_ref_11_04 <= 0;Inter_ref_12_04 <= 0; + Inter_ref_00_05 <= 0;Inter_ref_01_05 <= 0;Inter_ref_02_05 <= 0;Inter_ref_03_05 <= 0; + Inter_ref_04_05 <= 0;Inter_ref_05_05 <= 0;Inter_ref_06_05 <= 0;Inter_ref_07_05 <= 0; + Inter_ref_08_05 <= 0;Inter_ref_09_05 <= 0;Inter_ref_10_05 <= 0;Inter_ref_11_05 <= 0;Inter_ref_12_05 <= 0; + Inter_ref_00_06 <= 0;Inter_ref_01_06 <= 0;Inter_ref_02_06 <= 0;Inter_ref_03_06 <= 0; + Inter_ref_04_06 <= 0;Inter_ref_05_06 <= 0;Inter_ref_06_06 <= 0;Inter_ref_07_06 <= 0; + Inter_ref_08_06 <= 0;Inter_ref_09_06 <= 0;Inter_ref_10_06 <= 0;Inter_ref_11_06 <= 0;Inter_ref_12_06 <= 0; + Inter_ref_00_07 <= 0;Inter_ref_01_07 <= 0;Inter_ref_02_07 <= 0;Inter_ref_03_07 <= 0; + Inter_ref_04_07 <= 0;Inter_ref_05_07 <= 0;Inter_ref_06_07 <= 0;Inter_ref_07_07 <= 0; + Inter_ref_08_07 <= 0;Inter_ref_09_07 <= 0;Inter_ref_10_07 <= 0;Inter_ref_11_07 <= 0;Inter_ref_12_07 <= 0; + Inter_ref_00_08 <= 0;Inter_ref_01_08 <= 0;Inter_ref_02_08 <= 0;Inter_ref_03_08 <= 0; + Inter_ref_04_08 <= 0;Inter_ref_05_08 <= 0;Inter_ref_06_08 <= 0;Inter_ref_07_08 <= 0; + Inter_ref_08_08 <= 0;Inter_ref_09_08 <= 0;Inter_ref_10_08 <= 0;Inter_ref_11_08 <= 0;Inter_ref_12_08 <= 0; + Inter_ref_00_09 <= 0;Inter_ref_01_09 <= 0;Inter_ref_02_09 <= 0;Inter_ref_03_09 <= 0; + Inter_ref_04_09 <= 0;Inter_ref_05_09 <= 0;Inter_ref_06_09 <= 0;Inter_ref_07_09 <= 0; + Inter_ref_08_09 <= 0;Inter_ref_09_09 <= 0;Inter_ref_10_09 <= 0;Inter_ref_11_09 <= 0;Inter_ref_12_09 <= 0; + Inter_ref_00_10 <= 0;Inter_ref_01_10 <= 0;Inter_ref_02_10 <= 0;Inter_ref_03_10 <= 0; + Inter_ref_04_10 <= 0;Inter_ref_05_10 <= 0;Inter_ref_06_10 <= 0;Inter_ref_07_10 <= 0; + Inter_ref_08_10 <= 0;Inter_ref_09_10 <= 0;Inter_ref_10_10 <= 0;Inter_ref_11_10 <= 0;Inter_ref_12_10 <= 0; + Inter_ref_00_11 <= 0;Inter_ref_01_11 <= 0;Inter_ref_02_11 <= 0;Inter_ref_03_11 <= 0; + Inter_ref_04_11 <= 0;Inter_ref_05_11 <= 0;Inter_ref_06_11 <= 0;Inter_ref_07_11 <= 0; + Inter_ref_08_11 <= 0;Inter_ref_09_11 <= 0;Inter_ref_10_11 <= 0;Inter_ref_11_11 <= 0;Inter_ref_12_11 <= 0; + Inter_ref_00_12 <= 0;Inter_ref_01_12 <= 0;Inter_ref_02_12 <= 0;Inter_ref_03_12 <= 0; + Inter_ref_04_12 <= 0;Inter_ref_05_12 <= 0;Inter_ref_06_12 <= 0;Inter_ref_07_12 <= 0; + Inter_ref_08_12 <= 0;Inter_ref_09_12 <= 0;Inter_ref_10_12 <= 0;Inter_ref_11_12 <= 0;Inter_ref_12_12 <= 0; + end + else if (IsInterLuma && blk4x4_inter_preload_counter != 0) + case (mv_below8x8_curr) + 1'b0: + case (pos_FracL) + `pos_f,`pos_q,`pos_i,`pos_k,`pos_j: + case (xInt_org_unclip_1to0) + 2'b00: + case (blk4x4_inter_preload_counter) + 6'd52:{Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[31:16]; + 6'd51:{Inter_ref_05_00,Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding; + 6'd50:{Inter_ref_09_00,Inter_ref_08_00,Inter_ref_07_00,Inter_ref_06_00} <= RefFrameOutPadding; + 6'd49:{Inter_ref_12_00,Inter_ref_11_00,Inter_ref_10_00} <= RefFrameOutPadding[23:0]; + 6'd48:{Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[31:16]; + 6'd47:{Inter_ref_05_01,Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding; + 6'd46:{Inter_ref_09_01,Inter_ref_08_01,Inter_ref_07_01,Inter_ref_06_01} <= RefFrameOutPadding; + 6'd45:{Inter_ref_12_01,Inter_ref_11_01,Inter_ref_10_01} <= RefFrameOutPadding[23:0]; + 6'd44:{Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:16]; + 6'd43:{Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding; + 6'd42:{Inter_ref_09_02,Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02} <= RefFrameOutPadding; + 6'd41:{Inter_ref_12_02,Inter_ref_11_02,Inter_ref_10_02} <= RefFrameOutPadding[23:0]; + 6'd40:{Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:16]; + 6'd39:{Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding; + 6'd38:{Inter_ref_09_03,Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03} <= RefFrameOutPadding; + 6'd37:{Inter_ref_12_03,Inter_ref_11_03,Inter_ref_10_03} <= RefFrameOutPadding[23:0]; + 6'd36:{Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:16]; + 6'd35:{Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding; + 6'd34:{Inter_ref_09_04,Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04} <= RefFrameOutPadding; + 6'd33:{Inter_ref_12_04,Inter_ref_11_04,Inter_ref_10_04} <= RefFrameOutPadding[23:0]; + 6'd32:{Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding[31:16]; + 6'd31:{Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding; + 6'd30:{Inter_ref_09_05,Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05} <= RefFrameOutPadding; + 6'd29:{Inter_ref_12_05,Inter_ref_11_05,Inter_ref_10_05} <= RefFrameOutPadding[23:0]; + 6'd28:{Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding[31:16]; + 6'd27:{Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding; + 6'd26:{Inter_ref_09_06,Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06} <= RefFrameOutPadding; + 6'd25:{Inter_ref_12_06,Inter_ref_11_06,Inter_ref_10_06} <= RefFrameOutPadding[23:0]; + 6'd24:{Inter_ref_01_07,Inter_ref_00_07} <= RefFrameOutPadding[31:16]; + 6'd23:{Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding; + 6'd22:{Inter_ref_09_07,Inter_ref_08_07,Inter_ref_07_07,Inter_ref_06_07} <= RefFrameOutPadding; + 6'd21:{Inter_ref_12_07,Inter_ref_11_07,Inter_ref_10_07} <= RefFrameOutPadding[23:0]; + 6'd20:{Inter_ref_01_08,Inter_ref_00_08} <= RefFrameOutPadding[31:16]; + 6'd19:{Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding; + 6'd18:{Inter_ref_09_08,Inter_ref_08_08,Inter_ref_07_08,Inter_ref_06_08} <= RefFrameOutPadding; + 6'd17:{Inter_ref_12_08,Inter_ref_11_08,Inter_ref_10_08} <= RefFrameOutPadding[23:0]; + 6'd16:{Inter_ref_01_09,Inter_ref_00_09} <= RefFrameOutPadding[31:16]; + 6'd15:{Inter_ref_05_09,Inter_ref_04_09,Inter_ref_03_09,Inter_ref_02_09} <= RefFrameOutPadding; + 6'd14:{Inter_ref_09_09,Inter_ref_08_09,Inter_ref_07_09,Inter_ref_06_09} <= RefFrameOutPadding; + 6'd13:{Inter_ref_12_09,Inter_ref_11_09,Inter_ref_10_09} <= RefFrameOutPadding[23:0]; + 6'd12:{Inter_ref_01_10,Inter_ref_00_10} <= RefFrameOutPadding[31:16]; + 6'd11:{Inter_ref_05_10,Inter_ref_04_10,Inter_ref_03_10,Inter_ref_02_10} <= RefFrameOutPadding; + 6'd10:{Inter_ref_09_10,Inter_ref_08_10,Inter_ref_07_10,Inter_ref_06_10} <= RefFrameOutPadding; + 6'd9 :{Inter_ref_12_10,Inter_ref_11_10,Inter_ref_10_10} <= RefFrameOutPadding[23:0]; + 6'd8 :{Inter_ref_01_11,Inter_ref_00_11} <= RefFrameOutPadding[31:16]; + 6'd7 :{Inter_ref_05_11,Inter_ref_04_11,Inter_ref_03_11,Inter_ref_02_11} <= RefFrameOutPadding; + 6'd6 :{Inter_ref_09_11,Inter_ref_08_11,Inter_ref_07_11,Inter_ref_06_11} <= RefFrameOutPadding; + 6'd5 :{Inter_ref_12_11,Inter_ref_11_11,Inter_ref_10_11} <= RefFrameOutPadding[23:0]; + 6'd4 :{Inter_ref_01_12,Inter_ref_00_12} <= RefFrameOutPadding[31:16]; + 6'd3 :{Inter_ref_05_12,Inter_ref_04_12,Inter_ref_03_12,Inter_ref_02_12} <= RefFrameOutPadding; + 6'd2 :{Inter_ref_09_12,Inter_ref_08_12,Inter_ref_07_12,Inter_ref_06_12} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_12_12,Inter_ref_11_12,Inter_ref_10_12} <= RefFrameOutPadding[23:0]; + endcase + 2'b01: + case (blk4x4_inter_preload_counter) + 6'd52:Inter_ref_00_00 <= RefFrameOutPadding[31:24]; + 6'd51:{Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00,Inter_ref_01_00} <= RefFrameOutPadding; + 6'd50:{Inter_ref_08_00,Inter_ref_07_00,Inter_ref_06_00,Inter_ref_05_00} <= RefFrameOutPadding; + 6'd49:{Inter_ref_12_00,Inter_ref_11_00,Inter_ref_10_00,Inter_ref_09_00} <= RefFrameOutPadding; + 6'd48:Inter_ref_00_01 <= RefFrameOutPadding[31:24]; + 6'd47:{Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01,Inter_ref_01_01} <= RefFrameOutPadding; + 6'd46:{Inter_ref_08_01,Inter_ref_07_01,Inter_ref_06_01,Inter_ref_05_01} <= RefFrameOutPadding; + 6'd45:{Inter_ref_12_01,Inter_ref_11_01,Inter_ref_10_01,Inter_ref_09_01} <= RefFrameOutPadding; + 6'd44:Inter_ref_00_02 <= RefFrameOutPadding[31:24]; + 6'd43:{Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02} <= RefFrameOutPadding; + 6'd42:{Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02} <= RefFrameOutPadding; + 6'd41:{Inter_ref_12_02,Inter_ref_11_02,Inter_ref_10_02,Inter_ref_09_02} <= RefFrameOutPadding; + 6'd40:Inter_ref_00_03 <= RefFrameOutPadding[31:24]; + 6'd39:{Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03} <= RefFrameOutPadding; + 6'd38:{Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03} <= RefFrameOutPadding; + 6'd37:{Inter_ref_12_03,Inter_ref_11_03,Inter_ref_10_03,Inter_ref_09_03} <= RefFrameOutPadding; + 6'd36:Inter_ref_00_04 <= RefFrameOutPadding[31:24]; + 6'd35:{Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04} <= RefFrameOutPadding; + 6'd34:{Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04} <= RefFrameOutPadding; + 6'd33:{Inter_ref_12_04,Inter_ref_11_04,Inter_ref_10_04,Inter_ref_09_04} <= RefFrameOutPadding; + 6'd32:Inter_ref_00_05 <= RefFrameOutPadding[31:24]; + 6'd31:{Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05,Inter_ref_01_05} <= RefFrameOutPadding; + 6'd30:{Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05} <= RefFrameOutPadding; + 6'd29:{Inter_ref_12_05,Inter_ref_11_05,Inter_ref_10_05,Inter_ref_09_05} <= RefFrameOutPadding; + 6'd28:Inter_ref_00_06 <= RefFrameOutPadding[31:24]; + 6'd27:{Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06,Inter_ref_01_06} <= RefFrameOutPadding; + 6'd26:{Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06} <= RefFrameOutPadding; + 6'd25:{Inter_ref_12_06,Inter_ref_11_06,Inter_ref_10_06,Inter_ref_09_06} <= RefFrameOutPadding; + 6'd24:Inter_ref_00_07 <= RefFrameOutPadding[31:24]; + 6'd23:{Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07,Inter_ref_01_07} <= RefFrameOutPadding; + 6'd22:{Inter_ref_08_07,Inter_ref_07_07,Inter_ref_06_07,Inter_ref_05_07} <= RefFrameOutPadding; + 6'd21:{Inter_ref_12_07,Inter_ref_11_07,Inter_ref_10_07,Inter_ref_09_07} <= RefFrameOutPadding; + 6'd20:Inter_ref_00_08 <= RefFrameOutPadding[31:24]; + 6'd19:{Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08,Inter_ref_01_08} <= RefFrameOutPadding; + 6'd18:{Inter_ref_08_08,Inter_ref_07_08,Inter_ref_06_08,Inter_ref_05_08} <= RefFrameOutPadding; + 6'd17:{Inter_ref_12_08,Inter_ref_11_08,Inter_ref_10_08,Inter_ref_09_08} <= RefFrameOutPadding; + 6'd16:Inter_ref_00_09 <= RefFrameOutPadding[31:24]; + 6'd15:{Inter_ref_04_09,Inter_ref_03_09,Inter_ref_02_09,Inter_ref_01_09} <= RefFrameOutPadding; + 6'd14:{Inter_ref_08_09,Inter_ref_07_09,Inter_ref_06_09,Inter_ref_05_09} <= RefFrameOutPadding; + 6'd13:{Inter_ref_12_09,Inter_ref_11_09,Inter_ref_10_09,Inter_ref_09_09} <= RefFrameOutPadding; + 6'd12:Inter_ref_00_10 <= RefFrameOutPadding[31:24]; + 6'd11:{Inter_ref_04_10,Inter_ref_03_10,Inter_ref_02_10,Inter_ref_01_10} <= RefFrameOutPadding; + 6'd10:{Inter_ref_08_10,Inter_ref_07_10,Inter_ref_06_10,Inter_ref_05_10} <= RefFrameOutPadding; + 6'd9 :{Inter_ref_12_10,Inter_ref_11_10,Inter_ref_10_10,Inter_ref_09_10} <= RefFrameOutPadding; + 6'd8 :Inter_ref_00_11 <= RefFrameOutPadding[31:24]; + 6'd7 :{Inter_ref_04_11,Inter_ref_03_11,Inter_ref_02_11,Inter_ref_01_11} <= RefFrameOutPadding; + 6'd6 :{Inter_ref_08_11,Inter_ref_07_11,Inter_ref_06_11,Inter_ref_05_11} <= RefFrameOutPadding; + 6'd5 :{Inter_ref_12_11,Inter_ref_11_11,Inter_ref_10_11,Inter_ref_09_11} <= RefFrameOutPadding; + 6'd4 :Inter_ref_00_12 <= RefFrameOutPadding[31:24]; + 6'd3 :{Inter_ref_04_12,Inter_ref_03_12,Inter_ref_02_12,Inter_ref_01_12} <= RefFrameOutPadding; + 6'd2 :{Inter_ref_08_12,Inter_ref_07_12,Inter_ref_06_12,Inter_ref_05_12} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_12_12,Inter_ref_11_12,Inter_ref_10_12,Inter_ref_09_12} <= RefFrameOutPadding; + endcase + 2'b10: + case (blk4x4_inter_preload_counter) + 6'd52:{Inter_ref_03_00,Inter_ref_02_00,Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding; + 6'd51:{Inter_ref_07_00,Inter_ref_06_00,Inter_ref_05_00,Inter_ref_04_00} <= RefFrameOutPadding; + 6'd50:{Inter_ref_11_00,Inter_ref_10_00,Inter_ref_09_00,Inter_ref_08_00} <= RefFrameOutPadding; + 6'd49:Inter_ref_12_00 <= RefFrameOutPadding[7:0]; + 6'd48:{Inter_ref_03_01,Inter_ref_02_01,Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding; + 6'd47:{Inter_ref_07_01,Inter_ref_06_01,Inter_ref_05_01,Inter_ref_04_01} <= RefFrameOutPadding; + 6'd46:{Inter_ref_11_01,Inter_ref_10_01,Inter_ref_09_01,Inter_ref_08_01} <= RefFrameOutPadding; + 6'd45:Inter_ref_12_01 <= RefFrameOutPadding[7:0]; + 6'd44:{Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding; + 6'd43:{Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02} <= RefFrameOutPadding; + 6'd42:{Inter_ref_11_02,Inter_ref_10_02,Inter_ref_09_02,Inter_ref_08_02} <= RefFrameOutPadding; + 6'd41:Inter_ref_12_02 <= RefFrameOutPadding[7:0]; + 6'd40:{Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding; + 6'd39:{Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03} <= RefFrameOutPadding; + 6'd38:{Inter_ref_11_03,Inter_ref_10_03,Inter_ref_09_03,Inter_ref_08_03} <= RefFrameOutPadding; + 6'd37:Inter_ref_12_03 <= RefFrameOutPadding[7:0]; + 6'd36:{Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding; + 6'd35:{Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04} <= RefFrameOutPadding; + 6'd34:{Inter_ref_11_04,Inter_ref_10_04,Inter_ref_09_04,Inter_ref_08_04} <= RefFrameOutPadding; + 6'd33:Inter_ref_12_04 <= RefFrameOutPadding[7:0]; + 6'd32:{Inter_ref_03_05,Inter_ref_02_05,Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding; + 6'd31:{Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05} <= RefFrameOutPadding; + 6'd30:{Inter_ref_11_05,Inter_ref_10_05,Inter_ref_09_05,Inter_ref_08_05} <= RefFrameOutPadding; + 6'd29:Inter_ref_12_05 <= RefFrameOutPadding[7:0]; + 6'd28:{Inter_ref_03_06,Inter_ref_02_06,Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding; + 6'd27:{Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06} <= RefFrameOutPadding; + 6'd26:{Inter_ref_11_06,Inter_ref_10_06,Inter_ref_09_06,Inter_ref_08_06} <= RefFrameOutPadding; + 6'd25:Inter_ref_12_06 <= RefFrameOutPadding[7:0]; + 6'd24:{Inter_ref_03_07,Inter_ref_02_07,Inter_ref_01_07,Inter_ref_00_07} <= RefFrameOutPadding; + 6'd23:{Inter_ref_07_07,Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07} <= RefFrameOutPadding; + 6'd22:{Inter_ref_11_07,Inter_ref_10_07,Inter_ref_09_07,Inter_ref_08_07} <= RefFrameOutPadding; + 6'd21:Inter_ref_12_07 <= RefFrameOutPadding[7:0]; + 6'd20:{Inter_ref_03_08,Inter_ref_02_08,Inter_ref_01_08,Inter_ref_00_08} <= RefFrameOutPadding; + 6'd19:{Inter_ref_07_08,Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08} <= RefFrameOutPadding; + 6'd18:{Inter_ref_11_08,Inter_ref_10_08,Inter_ref_09_08,Inter_ref_08_08} <= RefFrameOutPadding; + 6'd17:Inter_ref_12_08 <= RefFrameOutPadding[7:0]; + 6'd16:{Inter_ref_03_09,Inter_ref_02_09,Inter_ref_01_09,Inter_ref_00_09} <= RefFrameOutPadding; + 6'd15:{Inter_ref_07_09,Inter_ref_06_09,Inter_ref_05_09,Inter_ref_04_09} <= RefFrameOutPadding; + 6'd14:{Inter_ref_11_09,Inter_ref_10_09,Inter_ref_09_09,Inter_ref_08_09} <= RefFrameOutPadding; + 6'd13:Inter_ref_12_09 <= RefFrameOutPadding[7:0]; + 6'd12:{Inter_ref_03_10,Inter_ref_02_10,Inter_ref_01_10,Inter_ref_00_10} <= RefFrameOutPadding; + 6'd11:{Inter_ref_07_10,Inter_ref_06_10,Inter_ref_05_10,Inter_ref_04_10} <= RefFrameOutPadding; + 6'd10:{Inter_ref_11_10,Inter_ref_10_10,Inter_ref_09_10,Inter_ref_08_10} <= RefFrameOutPadding; + 6'd9 :Inter_ref_12_10 <= RefFrameOutPadding[7:0]; + 6'd8 :{Inter_ref_03_11,Inter_ref_02_11,Inter_ref_01_11,Inter_ref_00_11} <= RefFrameOutPadding; + 6'd7 :{Inter_ref_07_11,Inter_ref_06_11,Inter_ref_05_11,Inter_ref_04_11} <= RefFrameOutPadding; + 6'd6 :{Inter_ref_11_11,Inter_ref_10_11,Inter_ref_09_11,Inter_ref_08_11} <= RefFrameOutPadding; + 6'd5 :Inter_ref_12_11 <= RefFrameOutPadding[7:0]; + 6'd4 :{Inter_ref_03_12,Inter_ref_02_12,Inter_ref_01_12,Inter_ref_00_12} <= RefFrameOutPadding; + 6'd3 :{Inter_ref_07_12,Inter_ref_06_12,Inter_ref_05_12,Inter_ref_04_12} <= RefFrameOutPadding; + 6'd2 :{Inter_ref_11_12,Inter_ref_10_12,Inter_ref_09_12,Inter_ref_08_12} <= RefFrameOutPadding; + 6'd1 :Inter_ref_12_12 <= RefFrameOutPadding[7:0]; + endcase + 2'b11: + case (blk4x4_inter_preload_counter) + 6'd52:{Inter_ref_02_00,Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[31:8]; + 6'd51:{Inter_ref_06_00,Inter_ref_05_00,Inter_ref_04_00,Inter_ref_03_00} <= RefFrameOutPadding; + 6'd50:{Inter_ref_10_00,Inter_ref_09_00,Inter_ref_08_00,Inter_ref_07_00} <= RefFrameOutPadding; + 6'd49:{Inter_ref_12_00,Inter_ref_11_00} <= RefFrameOutPadding[15:0]; + 6'd48:{Inter_ref_02_01,Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[31:8]; + 6'd47:{Inter_ref_06_01,Inter_ref_05_01,Inter_ref_04_01,Inter_ref_03_01} <= RefFrameOutPadding; + 6'd46:{Inter_ref_10_01,Inter_ref_09_01,Inter_ref_08_01,Inter_ref_07_01} <= RefFrameOutPadding; + 6'd45:{Inter_ref_12_01,Inter_ref_11_01} <= RefFrameOutPadding[15:0]; + 6'd44:{Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:8]; + 6'd43:{Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02} <= RefFrameOutPadding; + 6'd42:{Inter_ref_10_02,Inter_ref_09_02,Inter_ref_08_02,Inter_ref_07_02} <= RefFrameOutPadding; + 6'd41:{Inter_ref_12_02,Inter_ref_11_02} <= RefFrameOutPadding[15:0]; + 6'd40:{Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:8]; + 6'd39:{Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03} <= RefFrameOutPadding; + 6'd38:{Inter_ref_10_03,Inter_ref_09_03,Inter_ref_08_03,Inter_ref_07_03} <= RefFrameOutPadding; + 6'd37:{Inter_ref_12_03,Inter_ref_11_03} <= RefFrameOutPadding[15:0]; + 6'd36:{Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:8]; + 6'd35:{Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04} <= RefFrameOutPadding; + 6'd34:{Inter_ref_10_04,Inter_ref_09_04,Inter_ref_08_04,Inter_ref_07_04} <= RefFrameOutPadding; + 6'd33:{Inter_ref_12_04,Inter_ref_11_04} <= RefFrameOutPadding[15:0]; + 6'd32:{Inter_ref_02_05,Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding[31:8]; + 6'd31:{Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05} <= RefFrameOutPadding; + 6'd30:{Inter_ref_10_05,Inter_ref_09_05,Inter_ref_08_05,Inter_ref_07_05} <= RefFrameOutPadding; + 6'd29:{Inter_ref_12_05,Inter_ref_11_05} <= RefFrameOutPadding[15:0]; + 6'd28:{Inter_ref_02_06,Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding[31:8]; + 6'd27:{Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06} <= RefFrameOutPadding; + 6'd26:{Inter_ref_10_06,Inter_ref_09_06,Inter_ref_08_06,Inter_ref_07_06} <= RefFrameOutPadding; + 6'd25:{Inter_ref_12_06,Inter_ref_11_06} <= RefFrameOutPadding[15:0]; + 6'd24:{Inter_ref_02_07,Inter_ref_01_07,Inter_ref_00_07} <= RefFrameOutPadding[31:8]; + 6'd23:{Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07} <= RefFrameOutPadding; + 6'd22:{Inter_ref_10_07,Inter_ref_09_07,Inter_ref_08_07,Inter_ref_07_07} <= RefFrameOutPadding; + 6'd21:{Inter_ref_12_07,Inter_ref_11_07} <= RefFrameOutPadding[15:0]; + 6'd20:{Inter_ref_02_08,Inter_ref_01_08,Inter_ref_00_08} <= RefFrameOutPadding[31:8]; + 6'd19:{Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08} <= RefFrameOutPadding; + 6'd18:{Inter_ref_10_08,Inter_ref_09_08,Inter_ref_08_08,Inter_ref_07_08} <= RefFrameOutPadding; + 6'd17:{Inter_ref_12_08,Inter_ref_11_08} <= RefFrameOutPadding[15:0]; + 6'd16:{Inter_ref_02_09,Inter_ref_01_09,Inter_ref_00_09} <= RefFrameOutPadding[31:8]; + 6'd15:{Inter_ref_06_09,Inter_ref_05_09,Inter_ref_04_09,Inter_ref_03_09} <= RefFrameOutPadding; + 6'd14:{Inter_ref_10_09,Inter_ref_09_09,Inter_ref_08_09,Inter_ref_07_09} <= RefFrameOutPadding; + 6'd13:{Inter_ref_12_09,Inter_ref_11_09} <= RefFrameOutPadding[15:0]; + 6'd12:{Inter_ref_02_10,Inter_ref_01_10,Inter_ref_00_10} <= RefFrameOutPadding[31:8]; + 6'd11:{Inter_ref_06_10,Inter_ref_05_10,Inter_ref_04_10,Inter_ref_03_10} <= RefFrameOutPadding; + 6'd10:{Inter_ref_10_10,Inter_ref_09_10,Inter_ref_08_10,Inter_ref_07_10} <= RefFrameOutPadding; + 6'd9 :{Inter_ref_12_10,Inter_ref_11_10} <= RefFrameOutPadding[15:0]; + 6'd8 :{Inter_ref_02_11,Inter_ref_01_11,Inter_ref_00_11} <= RefFrameOutPadding[31:8]; + 6'd7 :{Inter_ref_06_11,Inter_ref_05_11,Inter_ref_04_11,Inter_ref_03_11} <= RefFrameOutPadding; + 6'd6 :{Inter_ref_10_11,Inter_ref_09_11,Inter_ref_08_11,Inter_ref_07_11} <= RefFrameOutPadding; + 6'd5 :{Inter_ref_12_11,Inter_ref_11_11} <= RefFrameOutPadding[15:0]; + 6'd4 :{Inter_ref_02_12,Inter_ref_01_12,Inter_ref_00_12} <= RefFrameOutPadding[31:8]; + 6'd3 :{Inter_ref_06_12,Inter_ref_05_12,Inter_ref_04_12,Inter_ref_03_12} <= RefFrameOutPadding; + 6'd2 :{Inter_ref_10_12,Inter_ref_09_12,Inter_ref_08_12,Inter_ref_07_12} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_12_12,Inter_ref_11_12} <= RefFrameOutPadding[15:0]; + endcase + endcase + `pos_d,`pos_h,`pos_n: + case (xInt_org_unclip_1to0) + 2'b00: + case (blk4x4_inter_preload_counter) + 6'd26:{Inter_ref_05_00,Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding; + 6'd25:{Inter_ref_09_00,Inter_ref_08_00,Inter_ref_07_00,Inter_ref_06_00} <= RefFrameOutPadding; + 6'd24:{Inter_ref_05_01,Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding; + 6'd23:{Inter_ref_09_01,Inter_ref_08_01,Inter_ref_07_01,Inter_ref_06_01} <= RefFrameOutPadding; + 6'd22:{Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding; + 6'd21:{Inter_ref_09_02,Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02} <= RefFrameOutPadding; + 6'd20:{Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding; + 6'd19:{Inter_ref_09_03,Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03} <= RefFrameOutPadding; + 6'd18:{Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding; + 6'd17:{Inter_ref_09_04,Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04} <= RefFrameOutPadding; + 6'd16:{Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding; + 6'd15:{Inter_ref_09_05,Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05} <= RefFrameOutPadding; + 6'd14:{Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding; + 6'd13:{Inter_ref_09_06,Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06} <= RefFrameOutPadding; + 6'd12:{Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding; + 6'd11:{Inter_ref_09_07,Inter_ref_08_07,Inter_ref_07_07,Inter_ref_06_07} <= RefFrameOutPadding; + 6'd10:{Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding; + 6'd9 :{Inter_ref_09_08,Inter_ref_08_08,Inter_ref_07_08,Inter_ref_06_08} <= RefFrameOutPadding; + 6'd8 :{Inter_ref_05_09,Inter_ref_04_09,Inter_ref_03_09,Inter_ref_02_09} <= RefFrameOutPadding; + 6'd7 :{Inter_ref_09_09,Inter_ref_08_09,Inter_ref_07_09,Inter_ref_06_09} <= RefFrameOutPadding; + 6'd6 :{Inter_ref_05_10,Inter_ref_04_10,Inter_ref_03_10,Inter_ref_02_10} <= RefFrameOutPadding; + 6'd5 :{Inter_ref_09_10,Inter_ref_08_10,Inter_ref_07_10,Inter_ref_06_10} <= RefFrameOutPadding; + 6'd4 :{Inter_ref_05_11,Inter_ref_04_11,Inter_ref_03_11,Inter_ref_02_11} <= RefFrameOutPadding; + 6'd3 :{Inter_ref_09_11,Inter_ref_08_11,Inter_ref_07_11,Inter_ref_06_11} <= RefFrameOutPadding; + 6'd2 :{Inter_ref_05_12,Inter_ref_04_12,Inter_ref_03_12,Inter_ref_02_12} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_09_12,Inter_ref_08_12,Inter_ref_07_12,Inter_ref_06_12} <= RefFrameOutPadding; + endcase + 2'b01: + case (blk4x4_inter_preload_counter) + 6'd39:{Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding[31:8]; + 6'd38:{Inter_ref_08_00,Inter_ref_07_00,Inter_ref_06_00,Inter_ref_05_00} <= RefFrameOutPadding; + 6'd37:Inter_ref_09_00 <= RefFrameOutPadding[7:0]; + 6'd36:{Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding[31:8]; + 6'd35:{Inter_ref_08_01,Inter_ref_07_01,Inter_ref_06_01,Inter_ref_05_01} <= RefFrameOutPadding; + 6'd34:Inter_ref_09_01 <= RefFrameOutPadding[7:0]; + 6'd33:{Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding[31:8]; + 6'd32:{Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02} <= RefFrameOutPadding; + 6'd31:Inter_ref_09_02 <= RefFrameOutPadding[7:0]; + 6'd30:{Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding[31:8]; + 6'd29:{Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03} <= RefFrameOutPadding; + 6'd28:Inter_ref_09_03 <= RefFrameOutPadding[7:0]; + 6'd27:{Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding[31:8]; + 6'd26:{Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04} <= RefFrameOutPadding; + 6'd25:Inter_ref_09_04 <= RefFrameOutPadding[7:0]; + 6'd24:{Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding[31:8]; + 6'd23:{Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05} <= RefFrameOutPadding; + 6'd22:Inter_ref_09_05 <= RefFrameOutPadding[7:0]; + 6'd21:{Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding[31:8]; + 6'd20:{Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06} <= RefFrameOutPadding; + 6'd19:Inter_ref_09_06 <= RefFrameOutPadding[7:0]; + 6'd18:{Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding[31:8]; + 6'd17:{Inter_ref_08_07,Inter_ref_07_07,Inter_ref_06_07,Inter_ref_05_07} <= RefFrameOutPadding; + 6'd16:Inter_ref_09_07 <= RefFrameOutPadding[7:0]; + 6'd15:{Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding[31:8]; + 6'd14:{Inter_ref_08_08,Inter_ref_07_08,Inter_ref_06_08,Inter_ref_05_08} <= RefFrameOutPadding; + 6'd13:Inter_ref_09_08 <= RefFrameOutPadding[7:0]; + 6'd12:{Inter_ref_04_09,Inter_ref_03_09,Inter_ref_02_09} <= RefFrameOutPadding[31:8]; + 6'd11:{Inter_ref_08_09,Inter_ref_07_09,Inter_ref_06_09,Inter_ref_05_09} <= RefFrameOutPadding; + 6'd10:Inter_ref_09_09 <= RefFrameOutPadding[7:0]; + 6'd9 :{Inter_ref_04_10,Inter_ref_03_10,Inter_ref_02_10} <= RefFrameOutPadding[31:8]; + 6'd8 :{Inter_ref_08_10,Inter_ref_07_10,Inter_ref_06_10,Inter_ref_05_10} <= RefFrameOutPadding; + 6'd7 :Inter_ref_09_10 <= RefFrameOutPadding[7:0]; + 6'd6 :{Inter_ref_04_11,Inter_ref_03_11,Inter_ref_02_11} <= RefFrameOutPadding[31:8]; + 6'd5 :{Inter_ref_08_11,Inter_ref_07_11,Inter_ref_06_11,Inter_ref_05_11} <= RefFrameOutPadding; + 6'd4 :Inter_ref_09_11 <= RefFrameOutPadding[7:0]; + 6'd3 :{Inter_ref_04_12,Inter_ref_03_12,Inter_ref_02_12} <= RefFrameOutPadding[31:8]; + 6'd2 :{Inter_ref_08_12,Inter_ref_07_12,Inter_ref_06_12,Inter_ref_05_12} <= RefFrameOutPadding; + 6'd1 :Inter_ref_09_12 <= RefFrameOutPadding[7:0]; + endcase + 2'b10: + case (blk4x4_inter_preload_counter) + 6'd39:{Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding[31:16]; + 6'd38:{Inter_ref_07_00,Inter_ref_06_00,Inter_ref_05_00,Inter_ref_04_00} <= RefFrameOutPadding; + 6'd37:{Inter_ref_09_00,Inter_ref_08_00} <= RefFrameOutPadding[15:0]; + 6'd36:{Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding[31:16]; + 6'd35:{Inter_ref_07_01,Inter_ref_06_01,Inter_ref_05_01,Inter_ref_04_01} <= RefFrameOutPadding; + 6'd34:{Inter_ref_09_01,Inter_ref_08_01} <= RefFrameOutPadding[15:0]; + 6'd33:{Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding[31:16]; + 6'd32:{Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02} <= RefFrameOutPadding; + 6'd31:{Inter_ref_09_02,Inter_ref_08_02} <= RefFrameOutPadding[15:0]; + 6'd30:{Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding[31:16]; + 6'd29:{Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03} <= RefFrameOutPadding; + 6'd28:{Inter_ref_09_03,Inter_ref_08_03} <= RefFrameOutPadding[15:0]; + 6'd27:{Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding[31:16]; + 6'd26:{Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04} <= RefFrameOutPadding; + 6'd25:{Inter_ref_09_04,Inter_ref_08_04} <= RefFrameOutPadding[15:0]; + 6'd24:{Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding[31:16]; + 6'd23:{Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05} <= RefFrameOutPadding; + 6'd22:{Inter_ref_09_05,Inter_ref_08_05} <= RefFrameOutPadding[15:0]; + 6'd21:{Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding[31:16]; + 6'd20:{Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06} <= RefFrameOutPadding; + 6'd19:{Inter_ref_09_06,Inter_ref_08_06} <= RefFrameOutPadding[15:0]; + 6'd18:{Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding[31:16]; + 6'd17:{Inter_ref_07_07,Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07} <= RefFrameOutPadding; + 6'd16:{Inter_ref_09_07,Inter_ref_08_07} <= RefFrameOutPadding[15:0]; + 6'd15:{Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding[31:16]; + 6'd14:{Inter_ref_07_08,Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08} <= RefFrameOutPadding; + 6'd13:{Inter_ref_09_08,Inter_ref_08_08} <= RefFrameOutPadding[15:0]; + 6'd12:{Inter_ref_03_09,Inter_ref_02_09} <= RefFrameOutPadding[31:16]; + 6'd11:{Inter_ref_07_09,Inter_ref_06_09,Inter_ref_05_09,Inter_ref_04_09} <= RefFrameOutPadding; + 6'd10:{Inter_ref_09_09,Inter_ref_08_09} <= RefFrameOutPadding[15:0]; + 6'd9 :{Inter_ref_03_10,Inter_ref_02_10} <= RefFrameOutPadding[31:16]; + 6'd8 :{Inter_ref_07_10,Inter_ref_06_10,Inter_ref_05_10,Inter_ref_04_10} <= RefFrameOutPadding; + 6'd7 :{Inter_ref_09_10,Inter_ref_08_10} <= RefFrameOutPadding[15:0]; + 6'd6 :{Inter_ref_03_11,Inter_ref_02_11} <= RefFrameOutPadding[31:16]; + 6'd5 :{Inter_ref_07_11,Inter_ref_06_11,Inter_ref_05_11,Inter_ref_04_11} <= RefFrameOutPadding; + 6'd4 :{Inter_ref_09_11,Inter_ref_08_11} <= RefFrameOutPadding[15:0]; + 6'd3 :{Inter_ref_03_12,Inter_ref_02_12} <= RefFrameOutPadding[31:16]; + 6'd2 :{Inter_ref_07_12,Inter_ref_06_12,Inter_ref_05_12,Inter_ref_04_12} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_09_12,Inter_ref_08_12} <= RefFrameOutPadding[15:0]; + endcase + 2'b11: + case (blk4x4_inter_preload_counter) + 6'd39:{Inter_ref_02_00} <= RefFrameOutPadding[31:24]; + 6'd38:{Inter_ref_06_00,Inter_ref_05_00,Inter_ref_04_00,Inter_ref_03_00} <= RefFrameOutPadding; + 6'd37:{Inter_ref_09_00,Inter_ref_08_00,Inter_ref_07_00} <= RefFrameOutPadding[23:0]; + 6'd36:{Inter_ref_02_01} <= RefFrameOutPadding[31:24]; + 6'd35:{Inter_ref_06_01,Inter_ref_05_01,Inter_ref_04_01,Inter_ref_03_01} <= RefFrameOutPadding; + 6'd34:{Inter_ref_09_01,Inter_ref_08_01,Inter_ref_07_01} <= RefFrameOutPadding[23:0]; + 6'd33:{Inter_ref_02_02} <= RefFrameOutPadding[31:24]; + 6'd32:{Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02} <= RefFrameOutPadding; + 6'd31:{Inter_ref_09_02,Inter_ref_08_02,Inter_ref_07_02} <= RefFrameOutPadding[23:0]; + 6'd30:{Inter_ref_02_03} <= RefFrameOutPadding[31:24]; + 6'd29:{Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03} <= RefFrameOutPadding; + 6'd28:{Inter_ref_09_03,Inter_ref_08_03,Inter_ref_07_03} <= RefFrameOutPadding[23:0]; + 6'd27:{Inter_ref_02_04} <= RefFrameOutPadding[31:24]; + 6'd26:{Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04} <= RefFrameOutPadding; + 6'd25:{Inter_ref_09_04,Inter_ref_08_04,Inter_ref_07_04} <= RefFrameOutPadding[23:0]; + 6'd24:{Inter_ref_02_05} <= RefFrameOutPadding[31:24]; + 6'd23:{Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05} <= RefFrameOutPadding; + 6'd22:{Inter_ref_09_05,Inter_ref_08_05,Inter_ref_07_05} <= RefFrameOutPadding[23:0]; + 6'd21:{Inter_ref_02_06} <= RefFrameOutPadding[31:24]; + 6'd20:{Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06} <= RefFrameOutPadding; + 6'd19:{Inter_ref_09_06,Inter_ref_08_06,Inter_ref_07_06} <= RefFrameOutPadding[23:0]; + 6'd18:{Inter_ref_02_07} <= RefFrameOutPadding[31:24]; + 6'd17:{Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07} <= RefFrameOutPadding; + 6'd16:{Inter_ref_09_07,Inter_ref_08_07,Inter_ref_07_07} <= RefFrameOutPadding[23:0]; + 6'd15:{Inter_ref_02_08} <= RefFrameOutPadding[31:24]; + 6'd14:{Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08} <= RefFrameOutPadding; + 6'd13:{Inter_ref_09_08,Inter_ref_08_08,Inter_ref_07_08} <= RefFrameOutPadding[23:0]; + 6'd12:{Inter_ref_02_09} <= RefFrameOutPadding[31:24]; + 6'd11:{Inter_ref_06_09,Inter_ref_05_09,Inter_ref_04_09,Inter_ref_03_09} <= RefFrameOutPadding; + 6'd10:{Inter_ref_09_09,Inter_ref_08_09,Inter_ref_07_09} <= RefFrameOutPadding[23:0]; + 6'd9 :{Inter_ref_02_10} <= RefFrameOutPadding[31:24]; + 6'd8 :{Inter_ref_06_10,Inter_ref_05_10,Inter_ref_04_10,Inter_ref_03_10} <= RefFrameOutPadding; + 6'd7 :{Inter_ref_09_10,Inter_ref_08_10,Inter_ref_07_10} <= RefFrameOutPadding[23:0]; + 6'd6 :{Inter_ref_02_11} <= RefFrameOutPadding[31:24]; + 6'd5 :{Inter_ref_06_11,Inter_ref_05_11,Inter_ref_04_11,Inter_ref_03_11} <= RefFrameOutPadding; + 6'd4 :{Inter_ref_09_11,Inter_ref_08_11,Inter_ref_07_11} <= RefFrameOutPadding[23:0]; + 6'd3 :{Inter_ref_02_12} <= RefFrameOutPadding[31:24]; + 6'd2 :{Inter_ref_06_12,Inter_ref_05_12,Inter_ref_04_12,Inter_ref_03_12} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_09_12,Inter_ref_08_12,Inter_ref_07_12} <= RefFrameOutPadding[23:0]; + endcase + endcase + `pos_a,`pos_b,`pos_c: + case (xInt_org_unclip_1to0) + 2'b00: + case (blk4x4_inter_preload_counter) + 6'd32:{Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:16]; + 6'd31:{Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding; + 6'd30:{Inter_ref_09_02,Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02} <= RefFrameOutPadding; + 6'd29:{Inter_ref_12_02,Inter_ref_11_02,Inter_ref_10_02} <= RefFrameOutPadding[23:0]; + 6'd28:{Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:16]; + 6'd27:{Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding; + 6'd26:{Inter_ref_09_03,Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03} <= RefFrameOutPadding; + 6'd25:{Inter_ref_12_03,Inter_ref_11_03,Inter_ref_10_03} <= RefFrameOutPadding[23:0]; + 6'd24:{Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:16]; + 6'd23:{Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding; + 6'd22:{Inter_ref_09_04,Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04} <= RefFrameOutPadding; + 6'd21:{Inter_ref_12_04,Inter_ref_11_04,Inter_ref_10_04} <= RefFrameOutPadding[23:0]; + 6'd20:{Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding[31:16]; + 6'd19:{Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding; + 6'd18:{Inter_ref_09_05,Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05} <= RefFrameOutPadding; + 6'd17:{Inter_ref_12_05,Inter_ref_11_05,Inter_ref_10_05} <= RefFrameOutPadding[23:0]; + 6'd16:{Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding[31:16]; + 6'd15:{Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding; + 6'd14:{Inter_ref_09_06,Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06} <= RefFrameOutPadding; + 6'd13:{Inter_ref_12_06,Inter_ref_11_06,Inter_ref_10_06} <= RefFrameOutPadding[23:0]; + 6'd12:{Inter_ref_01_07,Inter_ref_00_07} <= RefFrameOutPadding[31:16]; + 6'd11:{Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding; + 6'd10:{Inter_ref_09_07,Inter_ref_08_07,Inter_ref_07_07,Inter_ref_06_07} <= RefFrameOutPadding; + 6'd9 :{Inter_ref_12_07,Inter_ref_11_07,Inter_ref_10_07} <= RefFrameOutPadding[23:0]; + 6'd8 :{Inter_ref_01_08,Inter_ref_00_08} <= RefFrameOutPadding[31:16]; + 6'd7 :{Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding; + 6'd6 :{Inter_ref_09_08,Inter_ref_08_08,Inter_ref_07_08,Inter_ref_06_08} <= RefFrameOutPadding; + 6'd5 :{Inter_ref_12_08,Inter_ref_11_08,Inter_ref_10_08} <= RefFrameOutPadding[23:0]; + 6'd4 :{Inter_ref_01_09,Inter_ref_00_09} <= RefFrameOutPadding[31:16]; + 6'd3 :{Inter_ref_05_09,Inter_ref_04_09,Inter_ref_03_09,Inter_ref_02_09} <= RefFrameOutPadding; + 6'd2 :{Inter_ref_09_09,Inter_ref_08_09,Inter_ref_07_09,Inter_ref_06_09} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_12_09,Inter_ref_11_09,Inter_ref_10_09} <= RefFrameOutPadding[23:0]; + endcase + 2'b01: + case (blk4x4_inter_preload_counter) + 6'd32:Inter_ref_00_02 <= RefFrameOutPadding[31:24]; + 6'd31:{Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02} <= RefFrameOutPadding; + 6'd30:{Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02} <= RefFrameOutPadding; + 6'd29:{Inter_ref_12_02,Inter_ref_11_02,Inter_ref_10_02,Inter_ref_09_02} <= RefFrameOutPadding; + 6'd28:Inter_ref_00_03 <= RefFrameOutPadding[31:24]; + 6'd27:{Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03} <= RefFrameOutPadding; + 6'd26:{Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03} <= RefFrameOutPadding; + 6'd25:{Inter_ref_12_03,Inter_ref_11_03,Inter_ref_10_03,Inter_ref_09_03} <= RefFrameOutPadding; + 6'd24:Inter_ref_00_04 <= RefFrameOutPadding[31:24]; + 6'd23:{Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04} <= RefFrameOutPadding; + 6'd22:{Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04} <= RefFrameOutPadding; + 6'd21:{Inter_ref_12_04,Inter_ref_11_04,Inter_ref_10_04,Inter_ref_09_04} <= RefFrameOutPadding; + 6'd20:Inter_ref_00_05 <= RefFrameOutPadding[31:24]; + 6'd19:{Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05,Inter_ref_01_05} <= RefFrameOutPadding; + 6'd18:{Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05} <= RefFrameOutPadding; + 6'd17:{Inter_ref_12_05,Inter_ref_11_05,Inter_ref_10_05,Inter_ref_09_05} <= RefFrameOutPadding; + 6'd16:Inter_ref_00_06 <= RefFrameOutPadding[31:24]; + 6'd15:{Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06,Inter_ref_01_06} <= RefFrameOutPadding; + 6'd14:{Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06} <= RefFrameOutPadding; + 6'd13:{Inter_ref_12_06,Inter_ref_11_06,Inter_ref_10_06,Inter_ref_09_06} <= RefFrameOutPadding; + 6'd12:Inter_ref_00_07 <= RefFrameOutPadding[31:24]; + 6'd11:{Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07,Inter_ref_01_07} <= RefFrameOutPadding; + 6'd10:{Inter_ref_08_07,Inter_ref_07_07,Inter_ref_06_07,Inter_ref_05_07} <= RefFrameOutPadding; + 6'd9 :{Inter_ref_12_07,Inter_ref_11_07,Inter_ref_10_07,Inter_ref_09_07} <= RefFrameOutPadding; + 6'd8 :Inter_ref_00_08 <= RefFrameOutPadding[31:24]; + 6'd7 :{Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08,Inter_ref_01_08} <= RefFrameOutPadding; + 6'd6 :{Inter_ref_08_08,Inter_ref_07_08,Inter_ref_06_08,Inter_ref_05_08} <= RefFrameOutPadding; + 6'd5 :{Inter_ref_12_08,Inter_ref_11_08,Inter_ref_10_08,Inter_ref_09_08} <= RefFrameOutPadding; + 6'd4 :Inter_ref_00_09 <= RefFrameOutPadding[31:24]; + 6'd3 :{Inter_ref_04_09,Inter_ref_03_09,Inter_ref_02_09,Inter_ref_01_09} <= RefFrameOutPadding; + 6'd2 :{Inter_ref_08_09,Inter_ref_07_09,Inter_ref_06_09,Inter_ref_05_09} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_12_09,Inter_ref_11_09,Inter_ref_10_09,Inter_ref_09_09} <= RefFrameOutPadding; + endcase + 2'b10: + case (blk4x4_inter_preload_counter) + 6'd32:{Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding; + 6'd31:{Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02} <= RefFrameOutPadding; + 6'd30:{Inter_ref_11_02,Inter_ref_10_02,Inter_ref_09_02,Inter_ref_08_02} <= RefFrameOutPadding; + 6'd29:Inter_ref_12_02 <= RefFrameOutPadding[7:0]; + 6'd28:{Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding; + 6'd27:{Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03} <= RefFrameOutPadding; + 6'd26:{Inter_ref_11_03,Inter_ref_10_03,Inter_ref_09_03,Inter_ref_08_03} <= RefFrameOutPadding; + 6'd25:Inter_ref_12_03 <= RefFrameOutPadding[7:0]; + 6'd24:{Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding; + 6'd23:{Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04} <= RefFrameOutPadding; + 6'd22:{Inter_ref_11_04,Inter_ref_10_04,Inter_ref_09_04,Inter_ref_08_04} <= RefFrameOutPadding; + 6'd21:Inter_ref_12_04 <= RefFrameOutPadding[7:0]; + 6'd20:{Inter_ref_03_05,Inter_ref_02_05,Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding; + 6'd19:{Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05} <= RefFrameOutPadding; + 6'd18:{Inter_ref_11_05,Inter_ref_10_05,Inter_ref_09_05,Inter_ref_08_05} <= RefFrameOutPadding; + 6'd17:Inter_ref_12_05 <= RefFrameOutPadding[7:0]; + 6'd16:{Inter_ref_03_06,Inter_ref_02_06,Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding; + 6'd15:{Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06} <= RefFrameOutPadding; + 6'd14:{Inter_ref_11_06,Inter_ref_10_06,Inter_ref_09_06,Inter_ref_08_06} <= RefFrameOutPadding; + 6'd13:Inter_ref_12_06 <= RefFrameOutPadding[7:0]; + 6'd12:{Inter_ref_03_07,Inter_ref_02_07,Inter_ref_01_07,Inter_ref_00_07} <= RefFrameOutPadding; + 6'd11:{Inter_ref_07_07,Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07} <= RefFrameOutPadding; + 6'd10:{Inter_ref_11_07,Inter_ref_10_07,Inter_ref_09_07,Inter_ref_08_07} <= RefFrameOutPadding; + 6'd9 :Inter_ref_12_07 <= RefFrameOutPadding[7:0]; + 6'd8 :{Inter_ref_03_08,Inter_ref_02_08,Inter_ref_01_08,Inter_ref_00_08} <= RefFrameOutPadding; + 6'd7 :{Inter_ref_07_08,Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08} <= RefFrameOutPadding; + 6'd6 :{Inter_ref_11_08,Inter_ref_10_08,Inter_ref_09_08,Inter_ref_08_08} <= RefFrameOutPadding; + 6'd5 :Inter_ref_12_08 <= RefFrameOutPadding[7:0]; + 6'd4 :{Inter_ref_03_09,Inter_ref_02_09,Inter_ref_01_09,Inter_ref_00_09} <= RefFrameOutPadding; + 6'd3 :{Inter_ref_07_09,Inter_ref_06_09,Inter_ref_05_09,Inter_ref_04_09} <= RefFrameOutPadding; + 6'd2 :{Inter_ref_11_09,Inter_ref_10_09,Inter_ref_09_09,Inter_ref_08_09} <= RefFrameOutPadding; + 6'd1 :Inter_ref_12_09 <= RefFrameOutPadding[7:0]; + endcase + 2'b11: + case (blk4x4_inter_preload_counter) + 6'd32:{Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:8]; + 6'd31:{Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02} <= RefFrameOutPadding; + 6'd30:{Inter_ref_10_02,Inter_ref_09_02,Inter_ref_08_02,Inter_ref_07_02} <= RefFrameOutPadding; + 6'd29:{Inter_ref_12_02,Inter_ref_11_02} <= RefFrameOutPadding[15:0]; + 6'd28:{Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:8]; + 6'd27:{Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03} <= RefFrameOutPadding; + 6'd26:{Inter_ref_10_03,Inter_ref_09_03,Inter_ref_08_03,Inter_ref_07_03} <= RefFrameOutPadding; + 6'd25:{Inter_ref_12_03,Inter_ref_11_03} <= RefFrameOutPadding[15:0]; + 6'd24:{Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:8]; + 6'd23:{Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04} <= RefFrameOutPadding; + 6'd22:{Inter_ref_10_04,Inter_ref_09_04,Inter_ref_08_04,Inter_ref_07_04} <= RefFrameOutPadding; + 6'd21:{Inter_ref_12_04,Inter_ref_11_04} <= RefFrameOutPadding[15:0]; + 6'd20:{Inter_ref_02_05,Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding[31:8]; + 6'd19:{Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05} <= RefFrameOutPadding; + 6'd18:{Inter_ref_10_05,Inter_ref_09_05,Inter_ref_08_05,Inter_ref_07_05} <= RefFrameOutPadding; + 6'd17:{Inter_ref_12_05,Inter_ref_11_05} <= RefFrameOutPadding[15:0]; + 6'd16:{Inter_ref_02_06,Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding[31:8]; + 6'd15:{Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06} <= RefFrameOutPadding; + 6'd14:{Inter_ref_10_06,Inter_ref_09_06,Inter_ref_08_06,Inter_ref_07_06} <= RefFrameOutPadding; + 6'd13:{Inter_ref_12_06,Inter_ref_11_06} <= RefFrameOutPadding[15:0]; + 6'd12:{Inter_ref_02_07,Inter_ref_01_07,Inter_ref_00_07} <= RefFrameOutPadding[31:8]; + 6'd11:{Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07} <= RefFrameOutPadding; + 6'd10:{Inter_ref_10_07,Inter_ref_09_07,Inter_ref_08_07,Inter_ref_07_07} <= RefFrameOutPadding; + 6'd9 :{Inter_ref_12_07,Inter_ref_11_07} <= RefFrameOutPadding[15:0]; + 6'd8 :{Inter_ref_02_08,Inter_ref_01_08,Inter_ref_00_08} <= RefFrameOutPadding[31:8]; + 6'd7 :{Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08} <= RefFrameOutPadding; + 6'd6 :{Inter_ref_10_08,Inter_ref_09_08,Inter_ref_08_08,Inter_ref_07_08} <= RefFrameOutPadding; + 6'd5 :{Inter_ref_12_08,Inter_ref_11_08} <= RefFrameOutPadding[15:0]; + 6'd4 :{Inter_ref_02_09,Inter_ref_01_09,Inter_ref_00_09} <= RefFrameOutPadding[31:8]; + 6'd3 :{Inter_ref_06_09,Inter_ref_05_09,Inter_ref_04_09,Inter_ref_03_09} <= RefFrameOutPadding; + 6'd2 :{Inter_ref_10_09,Inter_ref_09_09,Inter_ref_08_09,Inter_ref_07_09} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_12_09,Inter_ref_11_09} <= RefFrameOutPadding[15:0]; + endcase + endcase + `pos_Int: + case (xInt_org_unclip_1to0) + 2'b00: + case (blk4x4_inter_preload_counter) + 6'd16:{Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding; + 6'd15:{Inter_ref_09_02,Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02} <= RefFrameOutPadding; + 6'd14:{Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding; + 6'd13:{Inter_ref_09_03,Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03} <= RefFrameOutPadding; + 6'd12:{Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding; + 6'd11:{Inter_ref_09_04,Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04} <= RefFrameOutPadding; + 6'd10:{Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding; + 6'd9 :{Inter_ref_09_05,Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05} <= RefFrameOutPadding; + 6'd8 :{Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding; + 6'd7 :{Inter_ref_09_06,Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06} <= RefFrameOutPadding; + 6'd6 :{Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding; + 6'd5 :{Inter_ref_09_07,Inter_ref_08_07,Inter_ref_07_07,Inter_ref_06_07} <= RefFrameOutPadding; + 6'd4 :{Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding; + 6'd3 :{Inter_ref_09_08,Inter_ref_08_08,Inter_ref_07_08,Inter_ref_06_08} <= RefFrameOutPadding; + 6'd2 :{Inter_ref_05_09,Inter_ref_04_09,Inter_ref_03_09,Inter_ref_02_09} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_09_09,Inter_ref_08_09,Inter_ref_07_09,Inter_ref_06_09} <= RefFrameOutPadding; + endcase + 2'b01: + case (blk4x4_inter_preload_counter) + 6'd24:{Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding[31:8]; + 6'd23:{Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02} <= RefFrameOutPadding; + 6'd22:Inter_ref_09_02 <= RefFrameOutPadding[7:0]; + 6'd21:{Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding[31:8]; + 6'd20:{Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03} <= RefFrameOutPadding; + 6'd19:Inter_ref_09_03 <= RefFrameOutPadding[7:0]; + 6'd18:{Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding[31:8]; + 6'd17:{Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04} <= RefFrameOutPadding; + 6'd16:Inter_ref_09_04 <= RefFrameOutPadding[7:0]; + 6'd15:{Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding[31:8]; + 6'd14:{Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05} <= RefFrameOutPadding; + 6'd13:Inter_ref_09_05 <= RefFrameOutPadding[7:0]; + 6'd12:{Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding[31:8]; + 6'd11:{Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06} <= RefFrameOutPadding; + 6'd10:Inter_ref_09_06 <= RefFrameOutPadding[7:0]; + 6'd9 :{Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding[31:8]; + 6'd8 :{Inter_ref_08_07,Inter_ref_07_07,Inter_ref_06_07,Inter_ref_05_07} <= RefFrameOutPadding; + 6'd7 :Inter_ref_09_07 <= RefFrameOutPadding[7:0]; + 6'd6 :{Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding[31:8]; + 6'd5 :{Inter_ref_08_08,Inter_ref_07_08,Inter_ref_06_08,Inter_ref_05_08} <= RefFrameOutPadding; + 6'd4 :Inter_ref_09_08 <= RefFrameOutPadding[7:0]; + 6'd3 :{Inter_ref_04_09,Inter_ref_03_09,Inter_ref_02_09} <= RefFrameOutPadding[31:8]; + 6'd2 :{Inter_ref_08_09,Inter_ref_07_09,Inter_ref_06_09,Inter_ref_05_09} <= RefFrameOutPadding; + 6'd1 :Inter_ref_09_09 <= RefFrameOutPadding[7:0]; + endcase + 2'b10: + case (blk4x4_inter_preload_counter) + 6'd24:{Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding[31:16]; + 6'd23:{Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02} <= RefFrameOutPadding; + 6'd22:{Inter_ref_09_02,Inter_ref_08_02} <= RefFrameOutPadding[15:0]; + 6'd21:{Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding[31:16]; + 6'd20:{Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03} <= RefFrameOutPadding; + 6'd19:{Inter_ref_09_03,Inter_ref_08_03} <= RefFrameOutPadding[15:0]; + 6'd18:{Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding[31:16]; + 6'd17:{Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04} <= RefFrameOutPadding; + 6'd16:{Inter_ref_09_04,Inter_ref_08_04} <= RefFrameOutPadding[15:0]; + 6'd15:{Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding[31:16]; + 6'd14:{Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05} <= RefFrameOutPadding; + 6'd13:{Inter_ref_09_05,Inter_ref_08_05} <= RefFrameOutPadding[15:0]; + 6'd12:{Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding[31:16]; + 6'd11:{Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06} <= RefFrameOutPadding; + 6'd10:{Inter_ref_09_06,Inter_ref_08_06} <= RefFrameOutPadding[15:0]; + 6'd9 :{Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding[31:16]; + 6'd8 :{Inter_ref_07_07,Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07} <= RefFrameOutPadding; + 6'd7 :{Inter_ref_09_07,Inter_ref_08_07} <= RefFrameOutPadding[15:0]; + 6'd6 :{Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding[31:16]; + 6'd5 :{Inter_ref_07_08,Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08} <= RefFrameOutPadding; + 6'd4 :{Inter_ref_09_08,Inter_ref_08_08} <= RefFrameOutPadding[15:0]; + 6'd3 :{Inter_ref_03_09,Inter_ref_02_09} <= RefFrameOutPadding[31:16]; + 6'd2 :{Inter_ref_07_09,Inter_ref_06_09,Inter_ref_05_09,Inter_ref_04_09} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_09_09,Inter_ref_08_09} <= RefFrameOutPadding[15:0]; + endcase + 2'b11: + case (blk4x4_inter_preload_counter) + 6'd24:{Inter_ref_02_02} <= RefFrameOutPadding[31:24]; + 6'd23:{Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02} <= RefFrameOutPadding; + 6'd22:{Inter_ref_09_02,Inter_ref_08_02,Inter_ref_07_02} <= RefFrameOutPadding[23:0]; + 6'd21:{Inter_ref_02_03} <= RefFrameOutPadding[31:24]; + 6'd20:{Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03} <= RefFrameOutPadding; + 6'd19:{Inter_ref_09_03,Inter_ref_08_03,Inter_ref_07_03} <= RefFrameOutPadding[23:0]; + 6'd18:{Inter_ref_02_04} <= RefFrameOutPadding[31:24]; + 6'd17:{Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04} <= RefFrameOutPadding; + 6'd16:{Inter_ref_09_04,Inter_ref_08_04,Inter_ref_07_04} <= RefFrameOutPadding[23:0]; + 6'd15:{Inter_ref_02_05} <= RefFrameOutPadding[31:24]; + 6'd14:{Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05} <= RefFrameOutPadding; + 6'd13:{Inter_ref_09_05,Inter_ref_08_05,Inter_ref_07_05} <= RefFrameOutPadding[23:0]; + 6'd12:{Inter_ref_02_06} <= RefFrameOutPadding[31:24]; + 6'd11:{Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06} <= RefFrameOutPadding; + 6'd10:{Inter_ref_09_06,Inter_ref_08_06,Inter_ref_07_06} <= RefFrameOutPadding[23:0]; + 6'd9 :{Inter_ref_02_07} <= RefFrameOutPadding[31:24]; + 6'd8 :{Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07} <= RefFrameOutPadding; + 6'd7 :{Inter_ref_09_07,Inter_ref_08_07,Inter_ref_07_07} <= RefFrameOutPadding[23:0]; + 6'd6 :{Inter_ref_02_08} <= RefFrameOutPadding[31:24]; + 6'd5 :{Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08} <= RefFrameOutPadding; + 6'd4 :{Inter_ref_09_08,Inter_ref_08_08,Inter_ref_07_08} <= RefFrameOutPadding[23:0]; + 6'd3 :{Inter_ref_02_09} <= RefFrameOutPadding[31:24]; + 6'd2 :{Inter_ref_06_09,Inter_ref_05_09,Inter_ref_04_09,Inter_ref_03_09} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_09_09,Inter_ref_08_09,Inter_ref_07_09} <= RefFrameOutPadding[23:0]; + endcase + endcase + `pos_e,`pos_g,`pos_p,`pos_r: + case (xInt_org_unclip_1to0) + 2'b00: + case (blk4x4_inter_preload_counter) + 6'd48:{Inter_ref_05_00,Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding; + 6'd47:{Inter_ref_09_00,Inter_ref_08_00,Inter_ref_07_00,Inter_ref_06_00} <= RefFrameOutPadding; + 6'd46:Inter_ref_10_00 <= RefFrameOutPadding[7:0]; + 6'd45:{Inter_ref_05_01,Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding; + 6'd44:{Inter_ref_09_01,Inter_ref_08_01,Inter_ref_07_01,Inter_ref_06_01} <= RefFrameOutPadding; + 6'd43:Inter_ref_10_01 <= RefFrameOutPadding[7:0]; + + 6'd42:{Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:16]; + 6'd41:{Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding; + 6'd40:{Inter_ref_09_02,Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02} <= RefFrameOutPadding; + 6'd39:{Inter_ref_12_02,Inter_ref_11_02,Inter_ref_10_02} <= RefFrameOutPadding[23:0]; + 6'd38:{Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:16]; + 6'd37:{Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding; + 6'd36:{Inter_ref_09_03,Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03} <= RefFrameOutPadding; + 6'd35:{Inter_ref_12_03,Inter_ref_11_03,Inter_ref_10_03} <= RefFrameOutPadding[23:0]; + 6'd34:{Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:16]; + 6'd33:{Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding; + 6'd32:{Inter_ref_09_04,Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04} <= RefFrameOutPadding; + 6'd31:{Inter_ref_12_04,Inter_ref_11_04,Inter_ref_10_04} <= RefFrameOutPadding[23:0]; + 6'd30:{Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding[31:16]; + 6'd29:{Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding; + 6'd28:{Inter_ref_09_05,Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05} <= RefFrameOutPadding; + 6'd27:{Inter_ref_12_05,Inter_ref_11_05,Inter_ref_10_05} <= RefFrameOutPadding[23:0]; + 6'd26:{Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding[31:16]; + 6'd25:{Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding; + 6'd24:{Inter_ref_09_06,Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06} <= RefFrameOutPadding; + 6'd23:{Inter_ref_12_06,Inter_ref_11_06,Inter_ref_10_06} <= RefFrameOutPadding[23:0]; + 6'd22:{Inter_ref_01_07,Inter_ref_00_07} <= RefFrameOutPadding[31:16]; + 6'd21:{Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding; + 6'd20:{Inter_ref_09_07,Inter_ref_08_07,Inter_ref_07_07,Inter_ref_06_07} <= RefFrameOutPadding; + 6'd19:{Inter_ref_12_07,Inter_ref_11_07,Inter_ref_10_07} <= RefFrameOutPadding[23:0]; + 6'd18:{Inter_ref_01_08,Inter_ref_00_08} <= RefFrameOutPadding[31:16]; + 6'd17:{Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding; + 6'd16:{Inter_ref_09_08,Inter_ref_08_08,Inter_ref_07_08,Inter_ref_06_08} <= RefFrameOutPadding; + 6'd15:{Inter_ref_12_08,Inter_ref_11_08,Inter_ref_10_08} <= RefFrameOutPadding[23:0]; + 6'd14:{Inter_ref_01_09,Inter_ref_00_09} <= RefFrameOutPadding[31:16]; + 6'd13:{Inter_ref_05_09,Inter_ref_04_09,Inter_ref_03_09,Inter_ref_02_09} <= RefFrameOutPadding; + 6'd12:{Inter_ref_09_09,Inter_ref_08_09,Inter_ref_07_09,Inter_ref_06_09} <= RefFrameOutPadding; + 6'd11:{Inter_ref_12_09,Inter_ref_11_09,Inter_ref_10_09} <= RefFrameOutPadding[23:0]; + 6'd10:{Inter_ref_01_10,Inter_ref_00_10} <= RefFrameOutPadding[31:16]; + 6'd9 :{Inter_ref_05_10,Inter_ref_04_10,Inter_ref_03_10,Inter_ref_02_10} <= RefFrameOutPadding; + 6'd8 :{Inter_ref_09_10,Inter_ref_08_10,Inter_ref_07_10,Inter_ref_06_10} <= RefFrameOutPadding; + 6'd7 :{Inter_ref_12_10,Inter_ref_11_10,Inter_ref_10_10} <= RefFrameOutPadding[23:0]; + + 6'd6 :{Inter_ref_05_11,Inter_ref_04_11,Inter_ref_03_11,Inter_ref_02_11} <= RefFrameOutPadding; + 6'd5 :{Inter_ref_09_11,Inter_ref_08_11,Inter_ref_07_11,Inter_ref_06_11} <= RefFrameOutPadding; + 6'd4 :Inter_ref_10_11 <= RefFrameOutPadding[7:0]; + 6'd3 :{Inter_ref_05_12,Inter_ref_04_12,Inter_ref_03_12,Inter_ref_02_12} <= RefFrameOutPadding; + 6'd2 :{Inter_ref_09_12,Inter_ref_08_12,Inter_ref_07_12,Inter_ref_06_12} <= RefFrameOutPadding; + 6'd1 :Inter_ref_10_12 <= RefFrameOutPadding[7:0]; + endcase + 2'b01: + case (blk4x4_inter_preload_counter) + 6'd48:{Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding[31:8]; + 6'd47:{Inter_ref_08_00,Inter_ref_07_00,Inter_ref_06_00,Inter_ref_05_00} <= RefFrameOutPadding; + 6'd46:{Inter_ref_10_00,Inter_ref_09_00} <= RefFrameOutPadding[15:0]; + 6'd45:{Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding[31:8]; + 6'd44:{Inter_ref_08_01,Inter_ref_07_01,Inter_ref_06_01,Inter_ref_05_01} <= RefFrameOutPadding; + 6'd43:{Inter_ref_10_01,Inter_ref_09_01} <= RefFrameOutPadding[15:0]; + + 6'd42:Inter_ref_00_02 <= RefFrameOutPadding[31:24]; + 6'd41:{Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02} <= RefFrameOutPadding; + 6'd40:{Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02} <= RefFrameOutPadding; + 6'd39:{Inter_ref_12_02,Inter_ref_11_02,Inter_ref_10_02,Inter_ref_09_02} <= RefFrameOutPadding; + 6'd38:Inter_ref_00_03 <= RefFrameOutPadding[31:24]; + 6'd37:{Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03} <= RefFrameOutPadding; + 6'd36:{Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03} <= RefFrameOutPadding; + 6'd35:{Inter_ref_12_03,Inter_ref_11_03,Inter_ref_10_03,Inter_ref_09_03} <= RefFrameOutPadding; + 6'd34:Inter_ref_00_04 <= RefFrameOutPadding[31:24]; + 6'd33:{Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04} <= RefFrameOutPadding; + 6'd32:{Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04} <= RefFrameOutPadding; + 6'd31:{Inter_ref_12_04,Inter_ref_11_04,Inter_ref_10_04,Inter_ref_09_04} <= RefFrameOutPadding; + 6'd30:Inter_ref_00_05 <= RefFrameOutPadding[31:24]; + 6'd29:{Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05,Inter_ref_01_05} <= RefFrameOutPadding; + 6'd28:{Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05} <= RefFrameOutPadding; + 6'd27:{Inter_ref_12_05,Inter_ref_11_05,Inter_ref_10_05,Inter_ref_09_05} <= RefFrameOutPadding; + 6'd26:Inter_ref_00_06 <= RefFrameOutPadding[31:24]; + 6'd25:{Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06,Inter_ref_01_06} <= RefFrameOutPadding; + 6'd24:{Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06} <= RefFrameOutPadding; + 6'd23:{Inter_ref_12_06,Inter_ref_11_06,Inter_ref_10_06,Inter_ref_09_06} <= RefFrameOutPadding; + 6'd22:Inter_ref_00_07 <= RefFrameOutPadding[31:24]; + 6'd21:{Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07,Inter_ref_01_07} <= RefFrameOutPadding; + 6'd20:{Inter_ref_08_07,Inter_ref_07_07,Inter_ref_06_07,Inter_ref_05_07} <= RefFrameOutPadding; + 6'd19:{Inter_ref_12_07,Inter_ref_11_07,Inter_ref_10_07,Inter_ref_09_07} <= RefFrameOutPadding; + 6'd18:Inter_ref_00_08 <= RefFrameOutPadding[31:24]; + 6'd17:{Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08,Inter_ref_01_08} <= RefFrameOutPadding; + 6'd16:{Inter_ref_08_08,Inter_ref_07_08,Inter_ref_06_08,Inter_ref_05_08} <= RefFrameOutPadding; + 6'd15:{Inter_ref_12_08,Inter_ref_11_08,Inter_ref_10_08,Inter_ref_09_08} <= RefFrameOutPadding; + 6'd14:Inter_ref_00_09 <= RefFrameOutPadding[31:24]; + 6'd13:{Inter_ref_04_09,Inter_ref_03_09,Inter_ref_02_09,Inter_ref_01_09} <= RefFrameOutPadding; + 6'd12:{Inter_ref_08_09,Inter_ref_07_09,Inter_ref_06_09,Inter_ref_05_09} <= RefFrameOutPadding; + 6'd11:{Inter_ref_12_09,Inter_ref_11_09,Inter_ref_10_09,Inter_ref_09_09} <= RefFrameOutPadding; + 6'd10:Inter_ref_00_10 <= RefFrameOutPadding[31:24]; + 6'd9 :{Inter_ref_04_10,Inter_ref_03_10,Inter_ref_02_10,Inter_ref_01_10} <= RefFrameOutPadding; + 6'd8 :{Inter_ref_08_10,Inter_ref_07_10,Inter_ref_06_10,Inter_ref_05_10} <= RefFrameOutPadding; + 6'd7 :{Inter_ref_12_10,Inter_ref_11_10,Inter_ref_10_10,Inter_ref_09_10} <= RefFrameOutPadding; + + 6'd6 :{Inter_ref_04_11,Inter_ref_03_11,Inter_ref_02_11} <= RefFrameOutPadding[31:8]; + 6'd5 :{Inter_ref_08_11,Inter_ref_07_11,Inter_ref_06_11,Inter_ref_05_11} <= RefFrameOutPadding; + 6'd4 :{Inter_ref_10_11,Inter_ref_09_11} <= RefFrameOutPadding[15:0]; + 6'd3 :{Inter_ref_04_12,Inter_ref_03_12,Inter_ref_02_12} <= RefFrameOutPadding[31:8]; + 6'd2 :{Inter_ref_08_12,Inter_ref_07_12,Inter_ref_06_12,Inter_ref_05_12} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_10_12,Inter_ref_09_12} <= RefFrameOutPadding[15:0]; + endcase + 2'b10: + case (blk4x4_inter_preload_counter) + 6'd48:{Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding[31:16]; + 6'd47:{Inter_ref_07_00,Inter_ref_06_00,Inter_ref_05_00,Inter_ref_04_00} <= RefFrameOutPadding; + 6'd46:{Inter_ref_10_00,Inter_ref_09_00,Inter_ref_08_00} <= RefFrameOutPadding[23:0]; + 6'd45:{Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding[31:16]; + 6'd44:{Inter_ref_07_01,Inter_ref_06_01,Inter_ref_05_01,Inter_ref_04_01} <= RefFrameOutPadding; + 6'd43:{Inter_ref_10_01,Inter_ref_09_01,Inter_ref_08_01} <= RefFrameOutPadding[23:0]; + + 6'd42:{Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding; + 6'd41:{Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02} <= RefFrameOutPadding; + 6'd40:{Inter_ref_11_02,Inter_ref_10_02,Inter_ref_09_02,Inter_ref_08_02} <= RefFrameOutPadding; + 6'd39:Inter_ref_12_02 <= RefFrameOutPadding[7:0]; + 6'd38:{Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding; + 6'd37:{Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03} <= RefFrameOutPadding; + 6'd36:{Inter_ref_11_03,Inter_ref_10_03,Inter_ref_09_03,Inter_ref_08_03} <= RefFrameOutPadding; + 6'd35:Inter_ref_12_03 <= RefFrameOutPadding[7:0]; + 6'd34:{Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding; + 6'd33:{Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04} <= RefFrameOutPadding; + 6'd32:{Inter_ref_11_04,Inter_ref_10_04,Inter_ref_09_04,Inter_ref_08_04} <= RefFrameOutPadding; + 6'd31:Inter_ref_12_04 <= RefFrameOutPadding[7:0]; + 6'd30:{Inter_ref_03_05,Inter_ref_02_05,Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding; + 6'd29:{Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05} <= RefFrameOutPadding; + 6'd28:{Inter_ref_11_05,Inter_ref_10_05,Inter_ref_09_05,Inter_ref_08_05} <= RefFrameOutPadding; + 6'd27:Inter_ref_12_05 <= RefFrameOutPadding[7:0]; + 6'd26:{Inter_ref_03_06,Inter_ref_02_06,Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding; + 6'd25:{Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06} <= RefFrameOutPadding; + 6'd24:{Inter_ref_11_06,Inter_ref_10_06,Inter_ref_09_06,Inter_ref_08_06} <= RefFrameOutPadding; + 6'd23:Inter_ref_12_06 <= RefFrameOutPadding[7:0]; + 6'd22:{Inter_ref_03_07,Inter_ref_02_07,Inter_ref_01_07,Inter_ref_00_07} <= RefFrameOutPadding; + 6'd21:{Inter_ref_07_07,Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07} <= RefFrameOutPadding; + 6'd20:{Inter_ref_11_07,Inter_ref_10_07,Inter_ref_09_07,Inter_ref_08_07} <= RefFrameOutPadding; + 6'd19:Inter_ref_12_07 <= RefFrameOutPadding[7:0]; + 6'd18:{Inter_ref_03_08,Inter_ref_02_08,Inter_ref_01_08,Inter_ref_00_08} <= RefFrameOutPadding; + 6'd17:{Inter_ref_07_08,Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08} <= RefFrameOutPadding; + 6'd16:{Inter_ref_11_08,Inter_ref_10_08,Inter_ref_09_08,Inter_ref_08_08} <= RefFrameOutPadding; + 6'd15:Inter_ref_12_08 <= RefFrameOutPadding[7:0]; + 6'd14:{Inter_ref_03_09,Inter_ref_02_09,Inter_ref_01_09,Inter_ref_00_09} <= RefFrameOutPadding; + 6'd13:{Inter_ref_07_09,Inter_ref_06_09,Inter_ref_05_09,Inter_ref_04_09} <= RefFrameOutPadding; + 6'd12:{Inter_ref_11_09,Inter_ref_10_09,Inter_ref_09_09,Inter_ref_08_09} <= RefFrameOutPadding; + 6'd11:Inter_ref_12_09 <= RefFrameOutPadding[7:0]; + 6'd10:{Inter_ref_03_10,Inter_ref_02_10,Inter_ref_01_10,Inter_ref_00_10} <= RefFrameOutPadding; + 6'd9 :{Inter_ref_07_10,Inter_ref_06_10,Inter_ref_05_10,Inter_ref_04_10} <= RefFrameOutPadding; + 6'd8 :{Inter_ref_11_10,Inter_ref_10_10,Inter_ref_09_10,Inter_ref_08_10} <= RefFrameOutPadding; + 6'd7 :Inter_ref_12_10 <= RefFrameOutPadding[7:0]; + + 6'd6 :{Inter_ref_03_11,Inter_ref_02_11} <= RefFrameOutPadding[31:16]; + 6'd5 :{Inter_ref_07_11,Inter_ref_06_11,Inter_ref_05_11,Inter_ref_04_11} <= RefFrameOutPadding; + 6'd4 :{Inter_ref_10_11,Inter_ref_09_11,Inter_ref_08_11} <= RefFrameOutPadding[23:0]; + 6'd3 :{Inter_ref_03_12,Inter_ref_02_12} <= RefFrameOutPadding[31:16]; + 6'd2 :{Inter_ref_07_12,Inter_ref_06_12,Inter_ref_05_12,Inter_ref_04_12} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_10_12,Inter_ref_09_12,Inter_ref_08_12} <= RefFrameOutPadding[23:0]; + endcase + 2'b11: + case (blk4x4_inter_preload_counter) + 6'd48:{Inter_ref_02_00} <= RefFrameOutPadding[31:24]; + 6'd47:{Inter_ref_06_00,Inter_ref_05_00,Inter_ref_04_00,Inter_ref_03_00} <= RefFrameOutPadding; + 6'd46:{Inter_ref_10_00,Inter_ref_09_00,Inter_ref_08_00,Inter_ref_07_00} <= RefFrameOutPadding; + 6'd45:{Inter_ref_02_01} <= RefFrameOutPadding[31:24]; + 6'd44:{Inter_ref_06_01,Inter_ref_05_01,Inter_ref_04_01,Inter_ref_03_01} <= RefFrameOutPadding; + 6'd43:{Inter_ref_10_01,Inter_ref_09_01,Inter_ref_08_01,Inter_ref_07_01} <= RefFrameOutPadding; + + 6'd42:{Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:8]; + 6'd41:{Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02} <= RefFrameOutPadding; + 6'd40:{Inter_ref_10_02,Inter_ref_09_02,Inter_ref_08_02,Inter_ref_07_02} <= RefFrameOutPadding; + 6'd39:{Inter_ref_12_02,Inter_ref_11_02} <= RefFrameOutPadding[15:0]; + 6'd38:{Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:8]; + 6'd37:{Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03} <= RefFrameOutPadding; + 6'd36:{Inter_ref_10_03,Inter_ref_09_03,Inter_ref_08_03,Inter_ref_07_03} <= RefFrameOutPadding; + 6'd35:{Inter_ref_12_03,Inter_ref_11_03} <= RefFrameOutPadding[15:0]; + 6'd34:{Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:8]; + 6'd33:{Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04} <= RefFrameOutPadding; + 6'd32:{Inter_ref_10_04,Inter_ref_09_04,Inter_ref_08_04,Inter_ref_07_04} <= RefFrameOutPadding; + 6'd31:{Inter_ref_12_04,Inter_ref_11_04} <= RefFrameOutPadding[15:0]; + 6'd30:{Inter_ref_02_05,Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding[31:8]; + 6'd29:{Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05} <= RefFrameOutPadding; + 6'd28:{Inter_ref_10_05,Inter_ref_09_05,Inter_ref_08_05,Inter_ref_07_05} <= RefFrameOutPadding; + 6'd27:{Inter_ref_12_05,Inter_ref_11_05} <= RefFrameOutPadding[15:0]; + 6'd26:{Inter_ref_02_06,Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding[31:8]; + 6'd25:{Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06} <= RefFrameOutPadding; + 6'd24:{Inter_ref_10_06,Inter_ref_09_06,Inter_ref_08_06,Inter_ref_07_06} <= RefFrameOutPadding; + 6'd23:{Inter_ref_12_06,Inter_ref_11_06} <= RefFrameOutPadding[15:0]; + 6'd22:{Inter_ref_02_07,Inter_ref_01_07,Inter_ref_00_07} <= RefFrameOutPadding[31:8]; + 6'd21:{Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07} <= RefFrameOutPadding; + 6'd20:{Inter_ref_10_07,Inter_ref_09_07,Inter_ref_08_07,Inter_ref_07_07} <= RefFrameOutPadding; + 6'd19:{Inter_ref_12_07,Inter_ref_11_07} <= RefFrameOutPadding[15:0]; + 6'd18:{Inter_ref_02_08,Inter_ref_01_08,Inter_ref_00_08} <= RefFrameOutPadding[31:8]; + 6'd17:{Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08} <= RefFrameOutPadding; + 6'd16:{Inter_ref_10_08,Inter_ref_09_08,Inter_ref_08_08,Inter_ref_07_08} <= RefFrameOutPadding; + 6'd15:{Inter_ref_12_08,Inter_ref_11_08} <= RefFrameOutPadding[15:0]; + 6'd14:{Inter_ref_02_09,Inter_ref_01_09,Inter_ref_00_09} <= RefFrameOutPadding[31:8]; + 6'd13:{Inter_ref_06_09,Inter_ref_05_09,Inter_ref_04_09,Inter_ref_03_09} <= RefFrameOutPadding; + 6'd12:{Inter_ref_10_09,Inter_ref_09_09,Inter_ref_08_09,Inter_ref_07_09} <= RefFrameOutPadding; + 6'd11:{Inter_ref_12_09,Inter_ref_11_09} <= RefFrameOutPadding[15:0]; + 6'd10:{Inter_ref_02_10,Inter_ref_01_10,Inter_ref_00_10} <= RefFrameOutPadding[31:8]; + 6'd9 :{Inter_ref_06_10,Inter_ref_05_10,Inter_ref_04_10,Inter_ref_03_10} <= RefFrameOutPadding; + 6'd8 :{Inter_ref_10_10,Inter_ref_09_10,Inter_ref_08_10,Inter_ref_07_10} <= RefFrameOutPadding; + 6'd7 :{Inter_ref_12_10,Inter_ref_11_10} <= RefFrameOutPadding[15:0]; + + 6'd6 :{Inter_ref_02_11} <= RefFrameOutPadding[31:24]; + 6'd5 :{Inter_ref_06_11,Inter_ref_05_11,Inter_ref_04_11,Inter_ref_03_11} <= RefFrameOutPadding; + 6'd4 :{Inter_ref_10_11,Inter_ref_09_11,Inter_ref_08_11,Inter_ref_07_11} <= RefFrameOutPadding; + 6'd3 :{Inter_ref_02_12} <= RefFrameOutPadding[31:24]; + 6'd2 :{Inter_ref_06_12,Inter_ref_05_12,Inter_ref_04_12,Inter_ref_03_12} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_10_12,Inter_ref_09_12,Inter_ref_08_12,Inter_ref_07_12} <= RefFrameOutPadding; + endcase + endcase + endcase + 1'b1: //mv_below8x8_curr == 1'b1 + case (pos_FracL) + `pos_f,`pos_q,`pos_i,`pos_k,`pos_j: + case (xInt_org_unclip_1to0) + 2'b00: + case (blk4x4_inter_preload_counter) + 6'd27:{Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[31:16]; + 6'd26:{Inter_ref_05_00,Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding; + 6'd25:{Inter_ref_08_00,Inter_ref_07_00,Inter_ref_06_00} <= RefFrameOutPadding[23:0]; + 6'd24:{Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[31:16]; + 6'd23:{Inter_ref_05_01,Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding; + 6'd22:{Inter_ref_08_01,Inter_ref_07_01,Inter_ref_06_01} <= RefFrameOutPadding[23:0]; + 6'd21:{Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:16]; + 6'd20:{Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding; + 6'd19:{Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02} <= RefFrameOutPadding[23:0]; + 6'd18:{Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:16]; + 6'd17:{Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding; + 6'd16:{Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03} <= RefFrameOutPadding[23:0]; + 6'd15:{Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:16]; + 6'd14:{Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding; + 6'd13:{Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04} <= RefFrameOutPadding[23:0]; + 6'd12:{Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding[31:16]; + 6'd11:{Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding; + 6'd10:{Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05} <= RefFrameOutPadding[23:0]; + 6'd9 :{Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding[31:16]; + 6'd8 :{Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding; + 6'd7 :{Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06} <= RefFrameOutPadding[23:0]; + 6'd6 :{Inter_ref_01_07,Inter_ref_00_07} <= RefFrameOutPadding[31:16]; + 6'd5 :{Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding; + 6'd4 :{Inter_ref_08_07,Inter_ref_07_07,Inter_ref_06_07} <= RefFrameOutPadding[23:0]; + 6'd3 :{Inter_ref_01_08,Inter_ref_00_08} <= RefFrameOutPadding[31:16]; + 6'd2 :{Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_08_08,Inter_ref_07_08,Inter_ref_06_08} <= RefFrameOutPadding[23:0]; + endcase + 2'b01: + case (blk4x4_inter_preload_counter) + 6'd27:Inter_ref_00_00 <= RefFrameOutPadding[31:24]; + 6'd26:{Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00,Inter_ref_01_00} <= RefFrameOutPadding; + 6'd25:{Inter_ref_08_00,Inter_ref_07_00,Inter_ref_06_00,Inter_ref_05_00} <= RefFrameOutPadding; + 6'd24:Inter_ref_00_01 <= RefFrameOutPadding[31:24]; + 6'd23:{Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01,Inter_ref_01_01} <= RefFrameOutPadding; + 6'd22:{Inter_ref_08_01,Inter_ref_07_01,Inter_ref_06_01,Inter_ref_05_01} <= RefFrameOutPadding; + 6'd21:Inter_ref_00_02 <= RefFrameOutPadding[31:24]; + 6'd20:{Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02} <= RefFrameOutPadding; + 6'd19:{Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02} <= RefFrameOutPadding; + 6'd18:Inter_ref_00_03 <= RefFrameOutPadding[31:24]; + 6'd17:{Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03} <= RefFrameOutPadding; + 6'd16:{Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03} <= RefFrameOutPadding; + 6'd15:Inter_ref_00_04 <= RefFrameOutPadding[31:24]; + 6'd14:{Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04} <= RefFrameOutPadding; + 6'd13:{Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04} <= RefFrameOutPadding; + 6'd12:Inter_ref_00_05 <= RefFrameOutPadding[31:24]; + 6'd11:{Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05,Inter_ref_01_05} <= RefFrameOutPadding; + 6'd10:{Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05} <= RefFrameOutPadding; + 6'd9 :Inter_ref_00_06 <= RefFrameOutPadding[31:24]; + 6'd8 :{Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06,Inter_ref_01_06} <= RefFrameOutPadding; + 6'd7 :{Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06} <= RefFrameOutPadding; + 6'd6 :Inter_ref_00_07 <= RefFrameOutPadding[31:24]; + 6'd5 :{Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07,Inter_ref_01_07} <= RefFrameOutPadding; + 6'd4 :{Inter_ref_08_07,Inter_ref_07_07,Inter_ref_06_07,Inter_ref_05_07} <= RefFrameOutPadding; + 6'd3 :Inter_ref_00_08 <= RefFrameOutPadding[31:24]; + 6'd2 :{Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08,Inter_ref_01_08} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_08_08,Inter_ref_07_08,Inter_ref_06_08,Inter_ref_05_08} <= RefFrameOutPadding; + endcase + 2'b10: + case (blk4x4_inter_preload_counter) + 6'd27:{Inter_ref_03_00,Inter_ref_02_00,Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding; + 6'd26:{Inter_ref_07_00,Inter_ref_06_00,Inter_ref_05_00,Inter_ref_04_00} <= RefFrameOutPadding; + 6'd25:Inter_ref_08_00 <= RefFrameOutPadding[7:0]; + 6'd24:{Inter_ref_03_01,Inter_ref_02_01,Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding; + 6'd23:{Inter_ref_07_01,Inter_ref_06_01,Inter_ref_05_01,Inter_ref_04_01} <= RefFrameOutPadding; + 6'd22:Inter_ref_08_01 <= RefFrameOutPadding[7:0]; + 6'd21:{Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding; + 6'd20:{Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02} <= RefFrameOutPadding; + 6'd19:Inter_ref_08_02 <= RefFrameOutPadding[7:0]; + 6'd18:{Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding; + 6'd17:{Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03} <= RefFrameOutPadding; + 6'd16:Inter_ref_08_03 <= RefFrameOutPadding[7:0]; + 6'd15:{Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding; + 6'd14:{Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04} <= RefFrameOutPadding; + 6'd13:Inter_ref_08_04 <= RefFrameOutPadding[7:0]; + 6'd12:{Inter_ref_03_05,Inter_ref_02_05,Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding; + 6'd11:{Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05} <= RefFrameOutPadding; + 6'd10:Inter_ref_08_05 <= RefFrameOutPadding[7:0]; + 6'd9 :{Inter_ref_03_06,Inter_ref_02_06,Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding; + 6'd8 :{Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06} <= RefFrameOutPadding; + 6'd7 :Inter_ref_08_06 <= RefFrameOutPadding[7:0]; + 6'd6 :{Inter_ref_03_07,Inter_ref_02_07,Inter_ref_01_07,Inter_ref_00_07} <= RefFrameOutPadding; + 6'd5 :{Inter_ref_07_07,Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07} <= RefFrameOutPadding; + 6'd4 :Inter_ref_08_07 <= RefFrameOutPadding[7:0]; + 6'd3 :{Inter_ref_03_08,Inter_ref_02_08,Inter_ref_01_08,Inter_ref_00_08} <= RefFrameOutPadding; + 6'd2 :{Inter_ref_07_08,Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08} <= RefFrameOutPadding; + 6'd1 :Inter_ref_08_08 <= RefFrameOutPadding[7:0]; + endcase + 2'b11: + case (blk4x4_inter_preload_counter) + 6'd27:{Inter_ref_02_00,Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[31:8]; + 6'd26:{Inter_ref_06_00,Inter_ref_05_00,Inter_ref_04_00,Inter_ref_03_00} <= RefFrameOutPadding; + 6'd25:{Inter_ref_08_00,Inter_ref_07_00} <= RefFrameOutPadding[15:0]; + + 6'd24:{Inter_ref_02_01,Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[31:8]; + 6'd23:{Inter_ref_06_01,Inter_ref_05_01,Inter_ref_04_01,Inter_ref_03_01} <= RefFrameOutPadding; + 6'd22:{Inter_ref_08_01,Inter_ref_07_01} <= RefFrameOutPadding[15:0]; + + 6'd21:{Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:8]; + 6'd20:{Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02} <= RefFrameOutPadding; + 6'd19:{Inter_ref_08_02,Inter_ref_07_02} <= RefFrameOutPadding[15:0]; + + 6'd18:{Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:8]; + 6'd17:{Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03} <= RefFrameOutPadding; + 6'd16:{Inter_ref_08_03,Inter_ref_07_03} <= RefFrameOutPadding[15:0]; + + 6'd15:{Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:8]; + 6'd14:{Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04} <= RefFrameOutPadding; + 6'd13:{Inter_ref_08_04,Inter_ref_07_04} <= RefFrameOutPadding[15:0]; + + 6'd12:{Inter_ref_02_05,Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding[31:8]; + 6'd11:{Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05} <= RefFrameOutPadding; + 6'd10:{Inter_ref_08_05,Inter_ref_07_05} <= RefFrameOutPadding[15:0]; + + 6'd9 :{Inter_ref_02_06,Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding[31:8]; + 6'd8 :{Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06} <= RefFrameOutPadding; + 6'd7 :{Inter_ref_08_06,Inter_ref_07_06} <= RefFrameOutPadding[15:0]; + + 6'd6 :{Inter_ref_02_07,Inter_ref_01_07,Inter_ref_00_07} <= RefFrameOutPadding[31:8]; + 6'd5 :{Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07} <= RefFrameOutPadding; + 6'd4 :{Inter_ref_08_07,Inter_ref_07_07} <= RefFrameOutPadding[15:0]; + + 6'd3 :{Inter_ref_02_08,Inter_ref_01_08,Inter_ref_00_08} <= RefFrameOutPadding[31:8]; + 6'd2 :{Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_08_08,Inter_ref_07_08} <= RefFrameOutPadding[15:0]; + endcase + endcase + `pos_d,`pos_h,`pos_n: + case (xInt_org_unclip_1to0) + 2'b00: + case (blk4x4_inter_preload_counter) + 6'd9:{Inter_ref_05_00,Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding; + 6'd8:{Inter_ref_05_01,Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding; + 6'd7:{Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding; + 6'd6:{Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding; + 6'd5:{Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding; + 6'd4:{Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding; + 6'd3:{Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding; + 6'd2:{Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding; + 6'd1:{Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding; + endcase + 2'b01: + case (blk4x4_inter_preload_counter) + 6'd18:{Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding[31:8]; + 6'd17:Inter_ref_05_00 <= RefFrameOutPadding[7:0]; + + 6'd16:{Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding[31:8]; + 6'd15:Inter_ref_05_01 <= RefFrameOutPadding[7:0]; + + 6'd14:{Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding[31:8]; + 6'd13:Inter_ref_05_02 <= RefFrameOutPadding[7:0]; + + 6'd12:{Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding[31:8]; + 6'd11:Inter_ref_05_03 <= RefFrameOutPadding[7:0]; + + 6'd10:{Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding[31:8]; + 6'd9 :Inter_ref_05_04 <= RefFrameOutPadding[7:0]; + + 6'd8 :{Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding[31:8]; + 6'd7 :Inter_ref_05_05 <= RefFrameOutPadding[7:0]; + + 6'd6 :{Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding[31:8]; + 6'd5 :Inter_ref_05_06 <= RefFrameOutPadding[7:0]; + + 6'd4 :{Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding[31:8]; + 6'd3 :Inter_ref_05_07 <= RefFrameOutPadding[7:0]; + + 6'd2 :{Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding[31:8]; + 6'd1 :Inter_ref_05_08 <= RefFrameOutPadding[7:0]; + endcase + 2'b10: + case (blk4x4_inter_preload_counter) + 6'd18:{Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding[31:16]; + 6'd17:{Inter_ref_05_00,Inter_ref_04_00} <= RefFrameOutPadding[15:0]; + + 6'd16:{Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding[31:16]; + 6'd15:{Inter_ref_05_01,Inter_ref_04_01} <= RefFrameOutPadding[15:0]; + + 6'd14:{Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding[31:16]; + 6'd13:{Inter_ref_05_02,Inter_ref_04_02} <= RefFrameOutPadding[15:0]; + + 6'd12:{Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding[31:16]; + 6'd11:{Inter_ref_05_03,Inter_ref_04_03} <= RefFrameOutPadding[15:0]; + + 6'd10:{Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding[31:16]; + 6'd9 :{Inter_ref_05_04,Inter_ref_04_04} <= RefFrameOutPadding[15:0]; + + 6'd8 :{Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding[31:16]; + 6'd7 :{Inter_ref_05_05,Inter_ref_04_05} <= RefFrameOutPadding[15:0]; + + 6'd6 :{Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding[31:16]; + 6'd5 :{Inter_ref_05_06,Inter_ref_04_06} <= RefFrameOutPadding[15:0]; + + 6'd4 :{Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding[31:16]; + 6'd3 :{Inter_ref_05_07,Inter_ref_04_07} <= RefFrameOutPadding[15:0]; + + 6'd2 :{Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding[31:16]; + 6'd1 :{Inter_ref_05_08,Inter_ref_04_08} <= RefFrameOutPadding[15:0]; + endcase + 2'b11: + case (blk4x4_inter_preload_counter) + 6'd18:Inter_ref_02_00 <= RefFrameOutPadding[31:24]; + 6'd17:{Inter_ref_05_00,Inter_ref_04_00,Inter_ref_03_00} <= RefFrameOutPadding[23:0]; + + 6'd16:Inter_ref_02_01 <= RefFrameOutPadding[31:24]; + 6'd15:{Inter_ref_05_01,Inter_ref_04_01,Inter_ref_03_01} <= RefFrameOutPadding[23:0]; + + 6'd14:Inter_ref_02_02 <= RefFrameOutPadding[31:24]; + 6'd13:{Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02} <= RefFrameOutPadding[23:0]; + + 6'd12:Inter_ref_02_03 <= RefFrameOutPadding[31:24]; + 6'd11:{Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03} <= RefFrameOutPadding[23:0]; + + 6'd10:Inter_ref_02_04 <= RefFrameOutPadding[31:24]; + 6'd9 :{Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04} <= RefFrameOutPadding[23:0]; + + 6'd8 :Inter_ref_02_05 <= RefFrameOutPadding[31:24]; + 6'd7 :{Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05} <= RefFrameOutPadding[23:0]; + + 6'd6 :Inter_ref_02_06 <= RefFrameOutPadding[31:24]; + 6'd5 :{Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06} <= RefFrameOutPadding[23:0]; + + 6'd4 :Inter_ref_02_07 <= RefFrameOutPadding[31:24]; + 6'd3 :{Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07} <= RefFrameOutPadding[23:0]; + + 6'd2 :Inter_ref_02_08 <= RefFrameOutPadding[31:24]; + 6'd1 :{Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08} <= RefFrameOutPadding[23:0]; + endcase + endcase + `pos_a,`pos_b,`pos_c: + case (xInt_org_unclip_1to0) + 2'b00: + case (blk4x4_inter_preload_counter) + 6'd12:{Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:16]; + 6'd11:{Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding; + 6'd10:{Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02} <= RefFrameOutPadding[23:0]; + + 6'd9 :{Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:16]; + 6'd8 :{Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding; + 6'd7 :{Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03} <= RefFrameOutPadding[23:0]; + + 6'd6 :{Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:16]; + 6'd5 :{Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding; + 6'd4 :{Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04} <= RefFrameOutPadding[23:0]; + + 6'd3 :{Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding[31:16]; + 6'd2 :{Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05} <= RefFrameOutPadding[23:0]; + endcase + 2'b01: + case (blk4x4_inter_preload_counter) + 6'd12:Inter_ref_00_02 <= RefFrameOutPadding[31:24]; + 6'd11:{Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02} <= RefFrameOutPadding; + 6'd10:{Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02} <= RefFrameOutPadding; + + 6'd9 :Inter_ref_00_03 <= RefFrameOutPadding[31:24]; + 6'd8 :{Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03} <= RefFrameOutPadding; + 6'd7 :{Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03} <= RefFrameOutPadding; + + 6'd6 :Inter_ref_00_04 <= RefFrameOutPadding[31:24]; + 6'd5 :{Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04} <= RefFrameOutPadding; + 6'd4 :{Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04} <= RefFrameOutPadding; + + 6'd3 :Inter_ref_00_05 <= RefFrameOutPadding[31:24]; + 6'd2 :{Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05,Inter_ref_01_05} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05} <= RefFrameOutPadding; + endcase + 2'b10: + case (blk4x4_inter_preload_counter) + 6'd12:{Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding; + 6'd11:{Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02} <= RefFrameOutPadding; + 6'd10:Inter_ref_08_02 <= RefFrameOutPadding[7:0]; + + 6'd9 :{Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding; + 6'd8 :{Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03} <= RefFrameOutPadding; + 6'd7 :Inter_ref_08_03 <= RefFrameOutPadding[7:0]; + + 6'd6 :{Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding; + 6'd5 :{Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04} <= RefFrameOutPadding; + 6'd4 :Inter_ref_08_04 <= RefFrameOutPadding[7:0]; + + 6'd3 :{Inter_ref_03_05,Inter_ref_02_05,Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding; + 6'd2 :{Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05} <= RefFrameOutPadding; + 6'd1 :Inter_ref_08_05 <= RefFrameOutPadding[7:0]; + endcase + 2'b11: + case (blk4x4_inter_preload_counter) + 6'd12:{Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:8]; + 6'd11:{Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02} <= RefFrameOutPadding; + 6'd10:{Inter_ref_08_02,Inter_ref_07_02} <= RefFrameOutPadding[15:0]; + + 6'd9 :{Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:8]; + 6'd8 :{Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03} <= RefFrameOutPadding; + 6'd7 :{Inter_ref_08_03,Inter_ref_07_03} <= RefFrameOutPadding[15:0]; + + 6'd6 :{Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:8]; + 6'd5 :{Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04} <= RefFrameOutPadding; + 6'd4 :{Inter_ref_08_04,Inter_ref_07_04} <= RefFrameOutPadding[15:0]; + + 6'd3 :{Inter_ref_02_05,Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding[31:8]; + 6'd2 :{Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_08_05,Inter_ref_07_05} <= RefFrameOutPadding[15:0]; + endcase + endcase + `pos_Int: + case (xInt_org_unclip_1to0) + 2'b00: + case (blk4x4_inter_preload_counter) + 6'd4:{Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding; + 6'd3:{Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding; + 6'd2:{Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding; + 6'd1:{Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding; + endcase + 2'b01: + case (blk4x4_inter_preload_counter) + 6'd8:{Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding[31:8]; + 6'd7:Inter_ref_05_02 <= RefFrameOutPadding[7:0]; + + 6'd6:{Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding[31:8]; + 6'd5:Inter_ref_05_03 <= RefFrameOutPadding[7:0]; + + 6'd4:{Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding[31:8]; + 6'd3:Inter_ref_05_04 <= RefFrameOutPadding[7:0]; + + 6'd2:{Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding[31:8]; + 6'd1:Inter_ref_05_05 <= RefFrameOutPadding[7:0]; + endcase + 2'b10: + case (blk4x4_inter_preload_counter) + 6'd8:{Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding[31:16]; + 6'd7:{Inter_ref_05_02,Inter_ref_04_02} <= RefFrameOutPadding[15:0]; + + 6'd6:{Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding[31:16]; + 6'd5:{Inter_ref_05_03,Inter_ref_04_03} <= RefFrameOutPadding[15:0]; + + 6'd4:{Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding[31:16]; + 6'd3:{Inter_ref_05_04,Inter_ref_04_04} <= RefFrameOutPadding[15:0]; + + 6'd2:{Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding[31:16]; + 6'd1:{Inter_ref_05_05,Inter_ref_04_05} <= RefFrameOutPadding[15:0]; + endcase + 2'b11: + case (blk4x4_inter_preload_counter) + 6'd8:Inter_ref_02_02 <= RefFrameOutPadding[31:24]; + 6'd7:{Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02} <= RefFrameOutPadding[23:0]; + + 6'd6:Inter_ref_02_03 <= RefFrameOutPadding[31:24]; + 6'd5:{Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03} <= RefFrameOutPadding[23:0]; + + 6'd4:Inter_ref_02_04 <= RefFrameOutPadding[31:24]; + 6'd3:{Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04} <= RefFrameOutPadding[23:0]; + + 6'd2:Inter_ref_02_05 <= RefFrameOutPadding[31:24]; + 6'd1:{Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05} <= RefFrameOutPadding[23:0]; + endcase + endcase + `pos_e,`pos_g,`pos_p,`pos_r: + case (xInt_org_unclip_1to0) + 2'b00: + case (blk4x4_inter_preload_counter) + 6'd23:{Inter_ref_05_00,Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding; + 6'd22:Inter_ref_06_00 <= RefFrameOutPadding[7:0]; + 6'd21:{Inter_ref_05_01,Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding; + 6'd20:Inter_ref_06_01 <= RefFrameOutPadding[7:0]; + + 6'd19:{Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:16]; + 6'd18:{Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding; + 6'd17:{Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02} <= RefFrameOutPadding[23:0]; + 6'd16:{Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:16]; + 6'd15:{Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding; + 6'd14:{Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03} <= RefFrameOutPadding[23:0]; + 6'd13:{Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:16]; + 6'd12:{Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding; + 6'd11:{Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04} <= RefFrameOutPadding[23:0]; + 6'd10:{Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding[31:16]; + 6'd9 :{Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding; + 6'd8 :{Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05} <= RefFrameOutPadding[23:0]; + 6'd7 :{Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding[31:16]; + 6'd6 :{Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding; + 6'd5 :{Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06} <= RefFrameOutPadding[23:0]; + + 6'd4 :{Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding; + 6'd3 :Inter_ref_06_07 <= RefFrameOutPadding[7:0]; + 6'd2 :{Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding; + 6'd1 :Inter_ref_06_08 <= RefFrameOutPadding[7:0]; + endcase + 2'b01: + case (blk4x4_inter_preload_counter) + 6'd23:{Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding[31:8]; + 6'd22:{Inter_ref_06_00,Inter_ref_05_00} <= RefFrameOutPadding[15:0]; + 6'd21:{Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding[31:8]; + 6'd20:{Inter_ref_06_01,Inter_ref_05_01} <= RefFrameOutPadding[15:0]; + + 6'd19:Inter_ref_00_02 <= RefFrameOutPadding[31:24]; + 6'd18:{Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02} <= RefFrameOutPadding; + 6'd17:{Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02} <= RefFrameOutPadding; + 6'd16:Inter_ref_00_03 <= RefFrameOutPadding[31:24]; + 6'd15:{Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03} <= RefFrameOutPadding; + 6'd14:{Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03} <= RefFrameOutPadding; + 6'd13:Inter_ref_00_04 <= RefFrameOutPadding[31:24]; + 6'd12:{Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04} <= RefFrameOutPadding; + 6'd11:{Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04} <= RefFrameOutPadding; + 6'd10:Inter_ref_00_05 <= RefFrameOutPadding[31:24]; + 6'd9 :{Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05,Inter_ref_01_05} <= RefFrameOutPadding; + 6'd8 :{Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05} <= RefFrameOutPadding; + 6'd7 :Inter_ref_00_06 <= RefFrameOutPadding[31:24]; + 6'd6 :{Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06,Inter_ref_01_06} <= RefFrameOutPadding; + 6'd5 :{Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06} <= RefFrameOutPadding; + + 6'd4 :{Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding[31:8]; + 6'd3 :{Inter_ref_06_07,Inter_ref_05_07} <= RefFrameOutPadding[15:0]; + 6'd2 :{Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding[31:8]; + 6'd1 :{Inter_ref_06_08,Inter_ref_05_08} <= RefFrameOutPadding[15:0]; + endcase + 2'b10: + case (blk4x4_inter_preload_counter) + 6'd23:{Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding[31:16]; + 6'd22:{Inter_ref_06_00,Inter_ref_05_00,Inter_ref_04_00} <= RefFrameOutPadding[23:0]; + 6'd21:{Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding[31:16]; + 6'd20:{Inter_ref_06_01,Inter_ref_05_01,Inter_ref_04_01} <= RefFrameOutPadding[23:0]; + + 6'd19:{Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding; + 6'd18:{Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02} <= RefFrameOutPadding; + 6'd17:Inter_ref_08_02 <= RefFrameOutPadding[7:0]; + 6'd16:{Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding; + 6'd15:{Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03} <= RefFrameOutPadding; + 6'd14:Inter_ref_08_03 <= RefFrameOutPadding[7:0]; + 6'd13:{Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding; + 6'd12:{Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04} <= RefFrameOutPadding; + 6'd11:Inter_ref_08_04 <= RefFrameOutPadding[7:0]; + 6'd10:{Inter_ref_03_05,Inter_ref_02_05,Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding; + 6'd9 :{Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05} <= RefFrameOutPadding; + 6'd8 :Inter_ref_08_05 <= RefFrameOutPadding[7:0]; + 6'd7 :{Inter_ref_03_06,Inter_ref_02_06,Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding; + 6'd6 :{Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06} <= RefFrameOutPadding; + 6'd5 :Inter_ref_08_06 <= RefFrameOutPadding[7:0]; + + 6'd4 :{Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding[31:16]; + 6'd3 :{Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07} <= RefFrameOutPadding[23:0]; + 6'd2 :{Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding[31:16]; + 6'd1 :{Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08} <= RefFrameOutPadding[23:0]; + endcase + 2'b11: + case (blk4x4_inter_preload_counter) + 6'd23:Inter_ref_02_00 <= RefFrameOutPadding[31:24]; + 6'd22:{Inter_ref_06_00,Inter_ref_05_00,Inter_ref_04_00,Inter_ref_03_00} <= RefFrameOutPadding; + 6'd21:Inter_ref_02_01 <= RefFrameOutPadding[31:24]; + 6'd20:{Inter_ref_06_01,Inter_ref_05_01,Inter_ref_04_01,Inter_ref_03_01} <= RefFrameOutPadding; + + 6'd19:{Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:8]; + 6'd18:{Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02} <= RefFrameOutPadding; + 6'd17:{Inter_ref_08_02,Inter_ref_07_02} <= RefFrameOutPadding[15:0]; + 6'd16:{Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:8]; + 6'd15:{Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03} <= RefFrameOutPadding; + 6'd14:{Inter_ref_08_03,Inter_ref_07_03} <= RefFrameOutPadding[15:0]; + 6'd13:{Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:8]; + 6'd12:{Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04} <= RefFrameOutPadding; + 6'd11:{Inter_ref_08_04,Inter_ref_07_04} <= RefFrameOutPadding[15:0]; + 6'd10:{Inter_ref_02_05,Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding[31:8]; + 6'd9 :{Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05} <= RefFrameOutPadding; + 6'd8 :{Inter_ref_08_05,Inter_ref_07_05} <= RefFrameOutPadding[15:0]; + 6'd7 :{Inter_ref_02_06,Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding[31:8]; + 6'd6 :{Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06} <= RefFrameOutPadding; + 6'd5 :{Inter_ref_08_06,Inter_ref_07_06} <= RefFrameOutPadding[15:0]; + + 6'd4 :Inter_ref_02_07 <= RefFrameOutPadding[31:24]; + 6'd3 :{Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07} <= RefFrameOutPadding; + 6'd2 :Inter_ref_02_08 <= RefFrameOutPadding[31:24]; + 6'd1 :{Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08} <= RefFrameOutPadding; + endcase + endcase + endcase + endcase + else if (IsInterChroma && blk4x4_inter_preload_counter != 0) + begin + if (mv_below8x8_curr == 1'b0) + begin + if (xFracC == 0 && yFracC == 0) // 8 or 4 cycles + case (xInt_org_unclip_1to0) + 2'b00: + case (blk4x4_inter_preload_counter) + 6'd4:{Inter_ref_03_00,Inter_ref_02_00,Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding; + 6'd3:{Inter_ref_03_01,Inter_ref_02_01,Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding; + 6'd2:{Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding; + 6'd1:{Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding; + endcase + 2'b01: + case (blk4x4_inter_preload_counter) + 6'd8:{Inter_ref_02_00,Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[31:8]; + 6'd7:Inter_ref_03_00 <= RefFrameOutPadding[7:0]; + 6'd6:{Inter_ref_02_01,Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[31:8]; + 6'd5:Inter_ref_03_01 <= RefFrameOutPadding[7:0]; + 6'd4:{Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:8]; + 6'd3:Inter_ref_03_02 <= RefFrameOutPadding[7:0]; + 6'd2:{Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:8]; + 6'd1:Inter_ref_03_03 <= RefFrameOutPadding[7:0]; + endcase + 2'b10: + case (blk4x4_inter_preload_counter) + 6'd8:{Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[31:16]; + 6'd7:{Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding[15:0]; + 6'd6:{Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[31:16]; + 6'd5:{Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding[15:0]; + 6'd4:{Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:16]; + 6'd3:{Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding[15:0]; + 6'd2:{Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:16]; + 6'd1:{Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding[15:0]; + endcase + 2'b11: + case (blk4x4_inter_preload_counter) + 6'd8:Inter_ref_00_00 <= RefFrameOutPadding[31:24]; + 6'd7:{Inter_ref_03_00,Inter_ref_02_00,Inter_ref_01_00} <= RefFrameOutPadding[23:0]; + 6'd6:Inter_ref_00_01 <= RefFrameOutPadding[31:24]; + 6'd5:{Inter_ref_03_01,Inter_ref_02_01,Inter_ref_01_01} <= RefFrameOutPadding[23:0]; + 6'd4:Inter_ref_00_02 <= RefFrameOutPadding[31:24]; + 6'd3:{Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02} <= RefFrameOutPadding[23:0]; + 6'd2:Inter_ref_00_03 <= RefFrameOutPadding[31:24]; + 6'd1:{Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03} <= RefFrameOutPadding[23:0]; + endcase + endcase + else + case (xInt_org_unclip_1to0) + 2'b00: + case(blk4x4_inter_preload_counter) + 6'd10:{Inter_ref_03_00,Inter_ref_02_00,Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding; + 6'd9 :Inter_ref_04_00 <= RefFrameOutPadding[7:0]; + 6'd8 :{Inter_ref_03_01,Inter_ref_02_01,Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding; + 6'd7 :Inter_ref_04_01 <= RefFrameOutPadding[7:0]; + 6'd6 :{Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding; + 6'd5 :Inter_ref_04_02 <= RefFrameOutPadding[7:0]; + 6'd4 :{Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding; + 6'd3 :Inter_ref_04_03 <= RefFrameOutPadding[7:0]; + 6'd2 :{Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding; + 6'd1 :Inter_ref_04_04 <= RefFrameOutPadding[7:0]; + endcase + 2'b01: + case (blk4x4_inter_preload_counter) + 6'd10:{Inter_ref_02_00,Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[31:8]; + 6'd9 :{Inter_ref_04_00,Inter_ref_03_00} <= RefFrameOutPadding[15:0]; + 6'd8 :{Inter_ref_02_01,Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[31:8]; + 6'd7 :{Inter_ref_04_01,Inter_ref_03_01} <= RefFrameOutPadding[15:0]; + 6'd6 :{Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:8]; + 6'd5 :{Inter_ref_04_02,Inter_ref_03_02} <= RefFrameOutPadding[15:0]; + 6'd4 :{Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:8]; + 6'd3 :{Inter_ref_04_03,Inter_ref_03_03} <= RefFrameOutPadding[15:0]; + 6'd2 :{Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:8]; + 6'd1 :{Inter_ref_04_04,Inter_ref_03_04} <= RefFrameOutPadding[15:0]; + endcase + 2'b10: + case (blk4x4_inter_preload_counter) + 6'd10:{Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[31:16]; + 6'd9 :{Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding[23:0]; + 6'd8 :{Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[31:16]; + 6'd7 :{Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding[23:0]; + 6'd6 :{Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:16]; + 6'd5 :{Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding[23:0]; + 6'd4 :{Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:16]; + 6'd3 :{Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding[23:0]; + 6'd2 :{Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:16]; + 6'd1 :{Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding[23:0]; + endcase + 2'b11: + case (blk4x4_inter_preload_counter) + 6'd10:Inter_ref_00_00 <= RefFrameOutPadding[31:24]; + 6'd9 :{Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00,Inter_ref_01_00} <= RefFrameOutPadding; + 6'd8 :Inter_ref_00_01 <= RefFrameOutPadding[31:24]; + 6'd7 :{Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01,Inter_ref_01_01} <= RefFrameOutPadding; + 6'd6 :Inter_ref_00_02 <= RefFrameOutPadding[31:24]; + 6'd5 :{Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02} <= RefFrameOutPadding; + 6'd4 :Inter_ref_00_03 <= RefFrameOutPadding[31:24]; + 6'd3 :{Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03} <= RefFrameOutPadding; + 6'd2 :Inter_ref_00_04 <= RefFrameOutPadding[31:24]; + 6'd1 :{Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04} <= RefFrameOutPadding; + endcase + endcase + end + else // mv_below8x8_curr == 1'b1 + begin + if (xFracC == 0 && yFracC == 0) // 4 or 2 cycles + case (xInt_org_unclip_1to0) + 2'b00: + case (blk4x4_inter_preload_counter) + 6'd2:{Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[15:0]; + 6'd1:{Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[15:0]; + endcase + 2'b01: + case (blk4x4_inter_preload_counter) + 6'd2:{Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[23:8]; + 6'd1:{Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[23:8]; + endcase + 2'b10: + case (blk4x4_inter_preload_counter) + 6'd2:{Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[31:16]; + 6'd1:{Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[31:16]; + endcase + 2'b11: + case (blk4x4_inter_preload_counter) + 6'd4:Inter_ref_00_00 <= RefFrameOutPadding[31:24]; + 6'd3:Inter_ref_01_00 <= RefFrameOutPadding[7:0]; + 6'd2:Inter_ref_00_01 <= RefFrameOutPadding[31:24]; + 6'd1:Inter_ref_01_01 <= RefFrameOutPadding[7:0]; + endcase + endcase + else // 6 or 3 cycles + case (xInt_org_unclip_1to0) + 2'b00: + case (blk4x4_inter_preload_counter) + 6'd3:{Inter_ref_02_00,Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[23:0]; + 6'd2:{Inter_ref_02_01,Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[23:0]; + 6'd1:{Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[23:0]; + endcase + 2'b01: + case (blk4x4_inter_preload_counter) + 6'd3:{Inter_ref_02_00,Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[31:8]; + 6'd2:{Inter_ref_02_01,Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[31:8]; + 6'd1:{Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:8]; + endcase + 2'b10: + case (blk4x4_inter_preload_counter) + 6'd6:{Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[31:16]; + 6'd5:Inter_ref_02_00 <= RefFrameOutPadding[7:0]; + 6'd4:{Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[31:16]; + 6'd3:Inter_ref_02_01 <= RefFrameOutPadding[7:0]; + 6'd2:{Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:16]; + 6'd1:Inter_ref_02_02 <= RefFrameOutPadding[7:0]; + endcase + 2'b11: + case (blk4x4_inter_preload_counter) + 6'd6:Inter_ref_00_00 <= RefFrameOutPadding[31:24]; + 6'd5:{Inter_ref_02_00,Inter_ref_01_00} <= RefFrameOutPadding[15:0]; + 6'd4:Inter_ref_00_01 <= RefFrameOutPadding[31:24]; + 6'd3:{Inter_ref_02_01,Inter_ref_01_01} <= RefFrameOutPadding[15:0]; + 6'd2:Inter_ref_00_02 <= RefFrameOutPadding[31:24]; + 6'd1:{Inter_ref_02_02,Inter_ref_01_02} <= RefFrameOutPadding[15:0]; + endcase + endcase + end + end + +endmodule + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/Inter_pred_sliding_window.v b/demo_chip_rtl/rtl/nova/tags/Start/src/Inter_pred_sliding_window.v new file mode 100644 index 0000000..9266d72 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/Inter_pred_sliding_window.v @@ -0,0 +1,2227 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : Inter_pred_sliding_window.v +// Generated : Oct 25, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Prepare the appropriate registers for Inter prediction (luma & chroma) +// 1)Luma:horizontal window 6x9,vertical window 1x9 +// 2)Chroma:window 2x2 +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module Inter_pred_sliding_window (IsInterLuma,IsInterChroma,Is_InterChromaCopy,mv_below8x8_curr, + pos_FracL,blk4x4_rec_counter_1to0,blk4x4_inter_calculate_counter, + Inter_ref_00_00,Inter_ref_01_00,Inter_ref_02_00,Inter_ref_03_00,Inter_ref_04_00,Inter_ref_05_00, + Inter_ref_06_00,Inter_ref_07_00,Inter_ref_08_00,Inter_ref_09_00,Inter_ref_10_00,Inter_ref_11_00,Inter_ref_12_00, + Inter_ref_00_01,Inter_ref_01_01,Inter_ref_02_01,Inter_ref_03_01,Inter_ref_04_01,Inter_ref_05_01, + Inter_ref_06_01,Inter_ref_07_01,Inter_ref_08_01,Inter_ref_09_01,Inter_ref_10_01,Inter_ref_11_01,Inter_ref_12_01, + Inter_ref_00_02,Inter_ref_01_02,Inter_ref_02_02,Inter_ref_03_02,Inter_ref_04_02,Inter_ref_05_02, + Inter_ref_06_02,Inter_ref_07_02,Inter_ref_08_02,Inter_ref_09_02,Inter_ref_10_02,Inter_ref_11_02,Inter_ref_12_02, + Inter_ref_00_03,Inter_ref_01_03,Inter_ref_02_03,Inter_ref_03_03,Inter_ref_04_03,Inter_ref_05_03, + Inter_ref_06_03,Inter_ref_07_03,Inter_ref_08_03,Inter_ref_09_03,Inter_ref_10_03,Inter_ref_11_03,Inter_ref_12_03, + Inter_ref_00_04,Inter_ref_01_04,Inter_ref_02_04,Inter_ref_03_04,Inter_ref_04_04,Inter_ref_05_04, + Inter_ref_06_04,Inter_ref_07_04,Inter_ref_08_04,Inter_ref_09_04,Inter_ref_10_04,Inter_ref_11_04,Inter_ref_12_04, + Inter_ref_00_05,Inter_ref_01_05,Inter_ref_02_05,Inter_ref_03_05,Inter_ref_04_05,Inter_ref_05_05, + Inter_ref_06_05,Inter_ref_07_05,Inter_ref_08_05,Inter_ref_09_05,Inter_ref_10_05,Inter_ref_11_05,Inter_ref_12_05, + Inter_ref_00_06,Inter_ref_01_06,Inter_ref_02_06,Inter_ref_03_06,Inter_ref_04_06,Inter_ref_05_06, + Inter_ref_06_06,Inter_ref_07_06,Inter_ref_08_06,Inter_ref_09_06,Inter_ref_10_06,Inter_ref_11_06,Inter_ref_12_06, + Inter_ref_00_07,Inter_ref_01_07,Inter_ref_02_07,Inter_ref_03_07,Inter_ref_04_07,Inter_ref_05_07, + Inter_ref_06_07,Inter_ref_07_07,Inter_ref_08_07,Inter_ref_09_07,Inter_ref_10_07,Inter_ref_11_07,Inter_ref_12_07, + Inter_ref_00_08,Inter_ref_01_08,Inter_ref_02_08,Inter_ref_03_08,Inter_ref_04_08,Inter_ref_05_08, + Inter_ref_06_08,Inter_ref_07_08,Inter_ref_08_08,Inter_ref_09_08,Inter_ref_10_08,Inter_ref_11_08,Inter_ref_12_08, + Inter_ref_00_09,Inter_ref_01_09,Inter_ref_02_09,Inter_ref_03_09,Inter_ref_04_09,Inter_ref_05_09, + Inter_ref_06_09,Inter_ref_07_09,Inter_ref_08_09,Inter_ref_09_09,Inter_ref_10_09,Inter_ref_11_09,Inter_ref_12_09, + Inter_ref_00_10,Inter_ref_01_10,Inter_ref_02_10,Inter_ref_03_10,Inter_ref_04_10,Inter_ref_05_10, + Inter_ref_06_10,Inter_ref_07_10,Inter_ref_08_10,Inter_ref_09_10,Inter_ref_10_10,Inter_ref_11_10,Inter_ref_12_10, + Inter_ref_00_11,Inter_ref_01_11,Inter_ref_02_11,Inter_ref_03_11,Inter_ref_04_11,Inter_ref_05_11, + Inter_ref_06_11,Inter_ref_07_11,Inter_ref_08_11,Inter_ref_09_11,Inter_ref_10_11,Inter_ref_11_11,Inter_ref_12_11, + Inter_ref_00_12,Inter_ref_01_12,Inter_ref_02_12,Inter_ref_03_12,Inter_ref_04_12,Inter_ref_05_12, + Inter_ref_06_12,Inter_ref_07_12,Inter_ref_08_12,Inter_ref_09_12,Inter_ref_10_12,Inter_ref_11_12,Inter_ref_12_12, + + Inter_pix_copy0,Inter_pix_copy1,Inter_pix_copy2,Inter_pix_copy3, + Inter_H_window_0_0,Inter_H_window_1_0,Inter_H_window_2_0,Inter_H_window_3_0,Inter_H_window_4_0,Inter_H_window_5_0, + Inter_H_window_0_1,Inter_H_window_1_1,Inter_H_window_2_1,Inter_H_window_3_1,Inter_H_window_4_1,Inter_H_window_5_1, + Inter_H_window_0_2,Inter_H_window_1_2,Inter_H_window_2_2,Inter_H_window_3_2,Inter_H_window_4_2,Inter_H_window_5_2, + Inter_H_window_0_3,Inter_H_window_1_3,Inter_H_window_2_3,Inter_H_window_3_3,Inter_H_window_4_3,Inter_H_window_5_3, + Inter_H_window_0_4,Inter_H_window_1_4,Inter_H_window_2_4,Inter_H_window_3_4,Inter_H_window_4_4,Inter_H_window_5_4, + Inter_H_window_0_5,Inter_H_window_1_5,Inter_H_window_2_5,Inter_H_window_3_5,Inter_H_window_4_5,Inter_H_window_5_5, + Inter_H_window_0_6,Inter_H_window_1_6,Inter_H_window_2_6,Inter_H_window_3_6,Inter_H_window_4_6,Inter_H_window_5_6, + Inter_H_window_0_7,Inter_H_window_1_7,Inter_H_window_2_7,Inter_H_window_3_7,Inter_H_window_4_7,Inter_H_window_5_7, + Inter_H_window_0_8,Inter_H_window_1_8,Inter_H_window_2_8,Inter_H_window_3_8,Inter_H_window_4_8,Inter_H_window_5_8, + Inter_V_window_0,Inter_V_window_1,Inter_V_window_2,Inter_V_window_3,Inter_V_window_4, + Inter_V_window_5,Inter_V_window_6,Inter_V_window_7,Inter_V_window_8, + Inter_C_window_0_0,Inter_C_window_1_0,Inter_C_window_2_0, + Inter_C_window_0_1,Inter_C_window_1_1,Inter_C_window_2_1, + Inter_C_window_0_2,Inter_C_window_1_2,Inter_C_window_2_2, + Inter_bi_window_0,Inter_bi_window_1,Inter_bi_window_2,Inter_bi_window_3); + input IsInterLuma; + input IsInterChroma; + input Is_InterChromaCopy; + input mv_below8x8_curr; + input [3:0] pos_FracL; + input [1:0] blk4x4_rec_counter_1to0; + input [3:0] blk4x4_inter_calculate_counter; + + input [7:0] Inter_ref_00_00,Inter_ref_01_00,Inter_ref_02_00,Inter_ref_03_00,Inter_ref_04_00,Inter_ref_05_00; + input [7:0] Inter_ref_06_00,Inter_ref_07_00,Inter_ref_08_00,Inter_ref_09_00,Inter_ref_10_00,Inter_ref_11_00,Inter_ref_12_00; + input [7:0] Inter_ref_00_01,Inter_ref_01_01,Inter_ref_02_01,Inter_ref_03_01,Inter_ref_04_01,Inter_ref_05_01; + input [7:0] Inter_ref_06_01,Inter_ref_07_01,Inter_ref_08_01,Inter_ref_09_01,Inter_ref_10_01,Inter_ref_11_01,Inter_ref_12_01; + input [7:0] Inter_ref_00_02,Inter_ref_01_02,Inter_ref_02_02,Inter_ref_03_02,Inter_ref_04_02,Inter_ref_05_02; + input [7:0] Inter_ref_06_02,Inter_ref_07_02,Inter_ref_08_02,Inter_ref_09_02,Inter_ref_10_02,Inter_ref_11_02,Inter_ref_12_02; + input [7:0] Inter_ref_00_03,Inter_ref_01_03,Inter_ref_02_03,Inter_ref_03_03,Inter_ref_04_03,Inter_ref_05_03; + input [7:0] Inter_ref_06_03,Inter_ref_07_03,Inter_ref_08_03,Inter_ref_09_03,Inter_ref_10_03,Inter_ref_11_03,Inter_ref_12_03; + input [7:0] Inter_ref_00_04,Inter_ref_01_04,Inter_ref_02_04,Inter_ref_03_04,Inter_ref_04_04,Inter_ref_05_04; + input [7:0] Inter_ref_06_04,Inter_ref_07_04,Inter_ref_08_04,Inter_ref_09_04,Inter_ref_10_04,Inter_ref_11_04,Inter_ref_12_04; + input [7:0] Inter_ref_00_05,Inter_ref_01_05,Inter_ref_02_05,Inter_ref_03_05,Inter_ref_04_05,Inter_ref_05_05; + input [7:0] Inter_ref_06_05,Inter_ref_07_05,Inter_ref_08_05,Inter_ref_09_05,Inter_ref_10_05,Inter_ref_11_05,Inter_ref_12_05; + input [7:0] Inter_ref_00_06,Inter_ref_01_06,Inter_ref_02_06,Inter_ref_03_06,Inter_ref_04_06,Inter_ref_05_06; + input [7:0] Inter_ref_06_06,Inter_ref_07_06,Inter_ref_08_06,Inter_ref_09_06,Inter_ref_10_06,Inter_ref_11_06,Inter_ref_12_06; + input [7:0] Inter_ref_00_07,Inter_ref_01_07,Inter_ref_02_07,Inter_ref_03_07,Inter_ref_04_07,Inter_ref_05_07; + input [7:0] Inter_ref_06_07,Inter_ref_07_07,Inter_ref_08_07,Inter_ref_09_07,Inter_ref_10_07,Inter_ref_11_07,Inter_ref_12_07; + input [7:0] Inter_ref_00_08,Inter_ref_01_08,Inter_ref_02_08,Inter_ref_03_08,Inter_ref_04_08,Inter_ref_05_08; + input [7:0] Inter_ref_06_08,Inter_ref_07_08,Inter_ref_08_08,Inter_ref_09_08,Inter_ref_10_08,Inter_ref_11_08,Inter_ref_12_08; + input [7:0] Inter_ref_00_09,Inter_ref_01_09,Inter_ref_02_09,Inter_ref_03_09,Inter_ref_04_09,Inter_ref_05_09; + input [7:0] Inter_ref_06_09,Inter_ref_07_09,Inter_ref_08_09,Inter_ref_09_09,Inter_ref_10_09,Inter_ref_11_09,Inter_ref_12_09; + input [7:0] Inter_ref_00_10,Inter_ref_01_10,Inter_ref_02_10,Inter_ref_03_10,Inter_ref_04_10,Inter_ref_05_10; + input [7:0] Inter_ref_06_10,Inter_ref_07_10,Inter_ref_08_10,Inter_ref_09_10,Inter_ref_10_10,Inter_ref_11_10,Inter_ref_12_10; + input [7:0] Inter_ref_00_11,Inter_ref_01_11,Inter_ref_02_11,Inter_ref_03_11,Inter_ref_04_11,Inter_ref_05_11; + input [7:0] Inter_ref_06_11,Inter_ref_07_11,Inter_ref_08_11,Inter_ref_09_11,Inter_ref_10_11,Inter_ref_11_11,Inter_ref_12_11; + input [7:0] Inter_ref_00_12,Inter_ref_01_12,Inter_ref_02_12,Inter_ref_03_12,Inter_ref_04_12,Inter_ref_05_12; + input [7:0] Inter_ref_06_12,Inter_ref_07_12,Inter_ref_08_12,Inter_ref_09_12,Inter_ref_10_12,Inter_ref_11_12,Inter_ref_12_12; + + output [7:0] Inter_pix_copy0,Inter_pix_copy1,Inter_pix_copy2,Inter_pix_copy3; + output [7:0] Inter_H_window_0_0,Inter_H_window_1_0,Inter_H_window_2_0,Inter_H_window_3_0,Inter_H_window_4_0,Inter_H_window_5_0; + output [7:0] Inter_H_window_0_1,Inter_H_window_1_1,Inter_H_window_2_1,Inter_H_window_3_1,Inter_H_window_4_1,Inter_H_window_5_1; + output [7:0] Inter_H_window_0_2,Inter_H_window_1_2,Inter_H_window_2_2,Inter_H_window_3_2,Inter_H_window_4_2,Inter_H_window_5_2; + output [7:0] Inter_H_window_0_3,Inter_H_window_1_3,Inter_H_window_2_3,Inter_H_window_3_3,Inter_H_window_4_3,Inter_H_window_5_3; + output [7:0] Inter_H_window_0_4,Inter_H_window_1_4,Inter_H_window_2_4,Inter_H_window_3_4,Inter_H_window_4_4,Inter_H_window_5_4; + output [7:0] Inter_H_window_0_5,Inter_H_window_1_5,Inter_H_window_2_5,Inter_H_window_3_5,Inter_H_window_4_5,Inter_H_window_5_5; + output [7:0] Inter_H_window_0_6,Inter_H_window_1_6,Inter_H_window_2_6,Inter_H_window_3_6,Inter_H_window_4_6,Inter_H_window_5_6; + output [7:0] Inter_H_window_0_7,Inter_H_window_1_7,Inter_H_window_2_7,Inter_H_window_3_7,Inter_H_window_4_7,Inter_H_window_5_7; + output [7:0] Inter_H_window_0_8,Inter_H_window_1_8,Inter_H_window_2_8,Inter_H_window_3_8,Inter_H_window_4_8,Inter_H_window_5_8; + output [7:0] Inter_V_window_0,Inter_V_window_1,Inter_V_window_2,Inter_V_window_3,Inter_V_window_4; + output [7:0] Inter_V_window_5,Inter_V_window_6,Inter_V_window_7,Inter_V_window_8; + output [7:0] Inter_C_window_0_0,Inter_C_window_1_0,Inter_C_window_2_0; + output [7:0] Inter_C_window_0_1,Inter_C_window_1_1,Inter_C_window_2_1; + output [7:0] Inter_C_window_0_2,Inter_C_window_1_2,Inter_C_window_2_2; + output [7:0] Inter_bi_window_0,Inter_bi_window_1,Inter_bi_window_2,Inter_bi_window_3; + + reg [7:0] Inter_pix_copy0,Inter_pix_copy1,Inter_pix_copy2,Inter_pix_copy3; + reg [7:0] Inter_H_window_0_0,Inter_H_window_1_0,Inter_H_window_2_0,Inter_H_window_3_0,Inter_H_window_4_0,Inter_H_window_5_0; + reg [7:0] Inter_H_window_0_1,Inter_H_window_1_1,Inter_H_window_2_1,Inter_H_window_3_1,Inter_H_window_4_1,Inter_H_window_5_1; + reg [7:0] Inter_H_window_0_2,Inter_H_window_1_2,Inter_H_window_2_2,Inter_H_window_3_2,Inter_H_window_4_2,Inter_H_window_5_2; + reg [7:0] Inter_H_window_0_3,Inter_H_window_1_3,Inter_H_window_2_3,Inter_H_window_3_3,Inter_H_window_4_3,Inter_H_window_5_3; + reg [7:0] Inter_H_window_0_4,Inter_H_window_1_4,Inter_H_window_2_4,Inter_H_window_3_4,Inter_H_window_4_4,Inter_H_window_5_4; + reg [7:0] Inter_H_window_0_5,Inter_H_window_1_5,Inter_H_window_2_5,Inter_H_window_3_5,Inter_H_window_4_5,Inter_H_window_5_5; + reg [7:0] Inter_H_window_0_6,Inter_H_window_1_6,Inter_H_window_2_6,Inter_H_window_3_6,Inter_H_window_4_6,Inter_H_window_5_6; + reg [7:0] Inter_H_window_0_7,Inter_H_window_1_7,Inter_H_window_2_7,Inter_H_window_3_7,Inter_H_window_4_7,Inter_H_window_5_7; + reg [7:0] Inter_H_window_0_8,Inter_H_window_1_8,Inter_H_window_2_8,Inter_H_window_3_8,Inter_H_window_4_8,Inter_H_window_5_8; + reg [7:0] Inter_V_window_0,Inter_V_window_1,Inter_V_window_2,Inter_V_window_3,Inter_V_window_4; + reg [7:0] Inter_V_window_5,Inter_V_window_6,Inter_V_window_7,Inter_V_window_8; + reg [7:0] Inter_C_window_0_0,Inter_C_window_1_0,Inter_C_window_2_0; + reg [7:0] Inter_C_window_0_1,Inter_C_window_1_1,Inter_C_window_2_1; + reg [7:0] Inter_C_window_0_2,Inter_C_window_1_2,Inter_C_window_2_2; + reg [7:0] Inter_bi_window_0,Inter_bi_window_1,Inter_bi_window_2,Inter_bi_window_3; + + parameter pos_Int = 4'b0000; + parameter pos_a = 4'b0100; + parameter pos_b = 4'b1000; + parameter pos_c = 4'b1100; + parameter pos_d = 4'b0001; + parameter pos_e = 4'b0101; + parameter pos_f = 4'b1001; + parameter pos_g = 4'b1101; + parameter pos_h = 4'b0010; + parameter pos_i = 4'b0110; + parameter pos_j = 4'b1010; + parameter pos_k = 4'b1110; + parameter pos_n = 4'b0011; + parameter pos_p = 4'b0111; + parameter pos_q = 4'b1011; + parameter pos_r = 4'b1111; + + //------------------------------- + //sliding window control + //------------------------------- + wire Is_blk4x4_0;//When inter 8x8(or above) predicted: top-left blk4x4 + //When inter 4x4 predicted: each blk4x4 + wire Is_blk4x4_1; + wire Is_blk4x4_2; + wire Is_blk4x4_3; + assign Is_blk4x4_0 = (IsInterLuma && (mv_below8x8_curr || (!mv_below8x8_curr && + blk4x4_rec_counter_1to0 == 2'b00))); //top-left + assign Is_blk4x4_1 = (IsInterLuma && (!mv_below8x8_curr && blk4x4_rec_counter_1to0 == 2'b01)); //top-right + assign Is_blk4x4_2 = (IsInterLuma && (!mv_below8x8_curr && blk4x4_rec_counter_1to0 == 2'b10)); //bottom-left + assign Is_blk4x4_3 = (IsInterLuma && (!mv_below8x8_curr && blk4x4_rec_counter_1to0 == 2'b11)); //bottom-right + + //For both luma & chroma,if current pixel is to be directly copied instead of inter calculated, + //the sliding windows output Inter_pix_copy0 ~ 3 is the inter prediction output + always @ (IsInterLuma or pos_FracL or blk4x4_inter_calculate_counter + or Is_blk4x4_0 or Is_blk4x4_1 or Is_blk4x4_2 or Is_blk4x4_3 + or Is_InterChromaCopy or mv_below8x8_curr + or Inter_ref_00_00 or Inter_ref_01_00 or Inter_ref_02_00 or Inter_ref_03_00 + or Inter_ref_00_01 or Inter_ref_01_01 or Inter_ref_02_01 or Inter_ref_03_01 + or Inter_ref_00_02 or Inter_ref_01_02 or Inter_ref_02_02 or Inter_ref_03_02 + or Inter_ref_04_02 or Inter_ref_05_02 or Inter_ref_06_02 or Inter_ref_07_02 + or Inter_ref_08_02 or Inter_ref_09_02 or Inter_ref_00_03 or Inter_ref_01_03 + or Inter_ref_02_03 or Inter_ref_03_03 or Inter_ref_04_03 or Inter_ref_05_03 + or Inter_ref_06_03 or Inter_ref_07_03 or Inter_ref_08_03 or Inter_ref_09_03 + or Inter_ref_02_04 or Inter_ref_03_04 or Inter_ref_04_04 or Inter_ref_05_04 + or Inter_ref_06_04 or Inter_ref_07_04 or Inter_ref_08_04 or Inter_ref_09_04 + or Inter_ref_02_05 or Inter_ref_03_05 or Inter_ref_04_05 or Inter_ref_05_05 + or Inter_ref_06_05 or Inter_ref_07_05 or Inter_ref_08_05 or Inter_ref_09_05 + or Inter_ref_02_06 or Inter_ref_03_06 or Inter_ref_04_06 or Inter_ref_05_06 + or Inter_ref_06_06 or Inter_ref_07_06 or Inter_ref_08_06 or Inter_ref_09_06 + or Inter_ref_02_07 or Inter_ref_03_07 or Inter_ref_04_07 or Inter_ref_05_07 + or Inter_ref_06_07 or Inter_ref_07_07 or Inter_ref_08_07 or Inter_ref_09_07 + or Inter_ref_02_08 or Inter_ref_03_08 or Inter_ref_04_08 or Inter_ref_05_08 + or Inter_ref_06_08 or Inter_ref_07_08 or Inter_ref_08_08 or Inter_ref_09_08 + or Inter_ref_02_09 or Inter_ref_03_09 or Inter_ref_04_09 or Inter_ref_05_09 + or Inter_ref_06_09 or Inter_ref_07_09 or Inter_ref_08_09 or Inter_ref_09_09) + if (IsInterLuma && pos_FracL == `pos_Int) + case ({Is_blk4x4_0,Is_blk4x4_1,Is_blk4x4_2,Is_blk4x4_3}) + 4'b1000: + case (blk4x4_inter_calculate_counter) + 4'd4:begin Inter_pix_copy0 <= Inter_ref_02_02; Inter_pix_copy1 <= Inter_ref_02_03; + Inter_pix_copy2 <= Inter_ref_02_04; Inter_pix_copy3 <= Inter_ref_02_05;end + 4'd3:begin Inter_pix_copy0 <= Inter_ref_03_02; Inter_pix_copy1 <= Inter_ref_03_03; + Inter_pix_copy2 <= Inter_ref_03_04; Inter_pix_copy3 <= Inter_ref_03_05;end + 4'd2:begin Inter_pix_copy0 <= Inter_ref_04_02; Inter_pix_copy1 <= Inter_ref_04_03; + Inter_pix_copy2 <= Inter_ref_04_04; Inter_pix_copy3 <= Inter_ref_04_05;end + 4'd1:begin Inter_pix_copy0 <= Inter_ref_05_02; Inter_pix_copy1 <= Inter_ref_05_03; + Inter_pix_copy2 <= Inter_ref_05_04; Inter_pix_copy3 <= Inter_ref_05_05;end + default:begin Inter_pix_copy0 <= 0; Inter_pix_copy1 <= 0; + Inter_pix_copy2 <= 0; Inter_pix_copy3 <= 0;end + endcase + 4'b0100: + case (blk4x4_inter_calculate_counter) + 4'd4:begin Inter_pix_copy0 <= Inter_ref_06_02; Inter_pix_copy1 <= Inter_ref_06_03; + Inter_pix_copy2 <= Inter_ref_06_04; Inter_pix_copy3 <= Inter_ref_06_05;end + 4'd3:begin Inter_pix_copy0 <= Inter_ref_07_02; Inter_pix_copy1 <= Inter_ref_07_03; + Inter_pix_copy2 <= Inter_ref_07_04; Inter_pix_copy3 <= Inter_ref_07_05;end + 4'd2:begin Inter_pix_copy0 <= Inter_ref_08_02; Inter_pix_copy1 <= Inter_ref_08_03; + Inter_pix_copy2 <= Inter_ref_08_04; Inter_pix_copy3 <= Inter_ref_08_05;end + 4'd1:begin Inter_pix_copy0 <= Inter_ref_09_02; Inter_pix_copy1 <= Inter_ref_09_03; + Inter_pix_copy2 <= Inter_ref_09_04; Inter_pix_copy3 <= Inter_ref_09_05;end + default:begin Inter_pix_copy0 <= 0; Inter_pix_copy1 <= 0; + Inter_pix_copy2 <= 0; Inter_pix_copy3 <= 0;end + endcase + 4'b0010: + case (blk4x4_inter_calculate_counter) + 4'd4:begin Inter_pix_copy0 <= Inter_ref_02_06; Inter_pix_copy1 <= Inter_ref_02_07; + Inter_pix_copy2 <= Inter_ref_02_08; Inter_pix_copy3 <= Inter_ref_02_09;end + 4'd3:begin Inter_pix_copy0 <= Inter_ref_03_06; Inter_pix_copy1 <= Inter_ref_03_07; + Inter_pix_copy2 <= Inter_ref_03_08; Inter_pix_copy3 <= Inter_ref_03_09;end + 4'd2:begin Inter_pix_copy0 <= Inter_ref_04_06; Inter_pix_copy1 <= Inter_ref_04_07; + Inter_pix_copy2 <= Inter_ref_04_08; Inter_pix_copy3 <= Inter_ref_04_09;end + 4'd1:begin Inter_pix_copy0 <= Inter_ref_05_06; Inter_pix_copy1 <= Inter_ref_05_07; + Inter_pix_copy2 <= Inter_ref_05_08; Inter_pix_copy3 <= Inter_ref_05_09;end + default:begin Inter_pix_copy0 <= 0; Inter_pix_copy1 <= 0; + Inter_pix_copy2 <= 0; Inter_pix_copy3 <= 0;end + endcase + 4'b0001: + case (blk4x4_inter_calculate_counter) + 4'd4:begin Inter_pix_copy0 <= Inter_ref_06_06; Inter_pix_copy1 <= Inter_ref_06_07; + Inter_pix_copy2 <= Inter_ref_06_08; Inter_pix_copy3 <= Inter_ref_06_09;end + 4'd3:begin Inter_pix_copy0 <= Inter_ref_07_06; Inter_pix_copy1 <= Inter_ref_07_07; + Inter_pix_copy2 <= Inter_ref_07_08; Inter_pix_copy3 <= Inter_ref_07_09;end + 4'd2:begin Inter_pix_copy0 <= Inter_ref_08_06; Inter_pix_copy1 <= Inter_ref_08_07; + Inter_pix_copy2 <= Inter_ref_08_08; Inter_pix_copy3 <= Inter_ref_08_09;end + 4'd1:begin Inter_pix_copy0 <= Inter_ref_09_06; Inter_pix_copy1 <= Inter_ref_09_07; + Inter_pix_copy2 <= Inter_ref_09_08; Inter_pix_copy3 <= Inter_ref_09_09;end + default:begin Inter_pix_copy0 <= 0; Inter_pix_copy1 <= 0; + Inter_pix_copy2 <= 0; Inter_pix_copy3 <= 0;end + endcase + default:begin Inter_pix_copy0 <= 0; Inter_pix_copy1 <= 0; + Inter_pix_copy2 <= 0; Inter_pix_copy3 <= 0;end + endcase + else if (Is_InterChromaCopy) + case (mv_below8x8_curr) + 1'b1://only one cycle + begin + Inter_pix_copy0 <= (blk4x4_inter_calculate_counter != 0)? Inter_ref_00_00:0; + Inter_pix_copy1 <= (blk4x4_inter_calculate_counter != 0)? Inter_ref_01_00:0; + Inter_pix_copy2 <= (blk4x4_inter_calculate_counter != 0)? Inter_ref_00_01:0; + Inter_pix_copy3 <= (blk4x4_inter_calculate_counter != 0)? Inter_ref_01_01:0; + end + 1'b0://4 cycles,each cycle for one blk2x2 in blk2x2-zig-zag order + case (blk4x4_inter_calculate_counter) + 4'd4: + begin + Inter_pix_copy0 <= Inter_ref_00_00; Inter_pix_copy1 <= Inter_ref_01_00; + Inter_pix_copy2 <= Inter_ref_00_01; Inter_pix_copy3 <= Inter_ref_01_01; + end + 4'd3: + begin + Inter_pix_copy0 <= Inter_ref_02_00; Inter_pix_copy1 <= Inter_ref_03_00; + Inter_pix_copy2 <= Inter_ref_02_01; Inter_pix_copy3 <= Inter_ref_03_01; + end + 4'd2: + begin + Inter_pix_copy0 <= Inter_ref_00_02; Inter_pix_copy1 <= Inter_ref_01_02; + Inter_pix_copy2 <= Inter_ref_00_03; Inter_pix_copy3 <= Inter_ref_01_03; + end + 4'd1: + begin + Inter_pix_copy0 <= Inter_ref_02_02; Inter_pix_copy1 <= Inter_ref_03_02; + Inter_pix_copy2 <= Inter_ref_02_03; Inter_pix_copy3 <= Inter_ref_03_03; + end + default: + begin + Inter_pix_copy0 <= 0; Inter_pix_copy1 <= 0; Inter_pix_copy2 <= 0; Inter_pix_copy3 <= 0; + end + endcase + endcase + else + begin + Inter_pix_copy0 <= 0; Inter_pix_copy1 <= 0; Inter_pix_copy2 <= 0; Inter_pix_copy3 <= 0; + end + + //Horizontal sliding windows:Inter_H_window_0_0 ~ Inter_H_window_5_8 (6x9 windows) + // Inter_H_window_x_0,Inter_H_window_x_1,Inter_H_window_x_6,Inter_H_window_x_7,Inter_H_window_x_8 + // are only used for pos_j/pos_i/pos_k/pos_f/pos_q + //Vertical sliding window:Inter_V_window_0 ~ Inter_V_window_8 + //Chroma sliding window:Inter_C_window_0 ~ Inter_C_window_3 + + //By careful study,we find that pos_b calculate cycle4 needs the same window as pos_a calculate cycl5. + //Similar cases happens with pos_b and pos_a/pos_c,pos_h and pos_d/pos_n, pos_j and pos_f/pos_q/pos_i/pos_k...... + + //Inter_H_window_counter0:for Inter_H_window_x_0/1/6/7/8 sliding window control + reg [2:0] Inter_H_window_counter0; + always @ (pos_FracL or blk4x4_inter_calculate_counter) + if ((pos_FracL == `pos_j && blk4x4_inter_calculate_counter == 4'd5) || + ((pos_FracL == `pos_f || pos_FracL == `pos_q) && blk4x4_inter_calculate_counter == 4'd5) || + ((pos_FracL == `pos_i || pos_FracL == `pos_k) && blk4x4_inter_calculate_counter == 4'd8)) + Inter_H_window_counter0 <= 3'd4; + else if ((pos_FracL == `pos_j && blk4x4_inter_calculate_counter == 4'd4) || + ((pos_FracL == `pos_f || pos_FracL == `pos_q) && blk4x4_inter_calculate_counter == 4'd4) || + ((pos_FracL == `pos_i || pos_FracL == `pos_k) && blk4x4_inter_calculate_counter == 4'd6)) + Inter_H_window_counter0 <= 3'd3; + else if ((pos_FracL == `pos_j && blk4x4_inter_calculate_counter == 4'd3) || + ((pos_FracL == `pos_f || pos_FracL == `pos_q) && blk4x4_inter_calculate_counter == 4'd3) || + ((pos_FracL == `pos_i || pos_FracL == `pos_k) && blk4x4_inter_calculate_counter == 4'd4)) + Inter_H_window_counter0 <= 3'd2; + else if ((pos_FracL == `pos_j && blk4x4_inter_calculate_counter == 4'd2) || + ((pos_FracL == `pos_f || pos_FracL == `pos_q) && blk4x4_inter_calculate_counter == 4'd2) || + ((pos_FracL == `pos_i || pos_FracL == `pos_k) && blk4x4_inter_calculate_counter == 4'd2)) + Inter_H_window_counter0 <= 3'd1; + else + Inter_H_window_counter0 <= 0; + + + //Inter_H_window_x_0,Inter_H_window_x_1 + //Inter_H_window_x_6,Inter_H_window_x_7,Inter_H_window_x_8 + //Active only for pos j,i/k/f/q + always @ (Is_blk4x4_0 or Is_blk4x4_1 or Is_blk4x4_2 or Is_blk4x4_3 or Inter_H_window_counter0 + + or Inter_ref_00_00 or Inter_ref_01_00 or Inter_ref_02_00 or Inter_ref_03_00 + or Inter_ref_04_00 or Inter_ref_05_00 or Inter_ref_06_00 or Inter_ref_07_00 + or Inter_ref_08_00 or Inter_ref_09_00 or Inter_ref_10_00 or Inter_ref_11_00 or Inter_ref_12_00 + + or Inter_ref_00_01 or Inter_ref_01_01 or Inter_ref_02_01 or Inter_ref_03_01 + or Inter_ref_04_01 or Inter_ref_05_01 or Inter_ref_06_01 or Inter_ref_07_01 + or Inter_ref_08_01 or Inter_ref_09_01 or Inter_ref_10_01 or Inter_ref_11_01 or Inter_ref_12_01 + + or Inter_ref_00_06 or Inter_ref_01_06 or Inter_ref_02_06 or Inter_ref_03_06 + or Inter_ref_04_06 or Inter_ref_05_06 or Inter_ref_06_06 or Inter_ref_07_06 + or Inter_ref_08_06 or Inter_ref_09_06 or Inter_ref_10_06 or Inter_ref_11_06 or Inter_ref_12_06 + + or Inter_ref_00_07 or Inter_ref_01_07 or Inter_ref_02_07 or Inter_ref_03_07 + or Inter_ref_04_07 or Inter_ref_05_07 or Inter_ref_06_07 or Inter_ref_07_07 + or Inter_ref_08_07 or Inter_ref_09_07 or Inter_ref_10_07 or Inter_ref_11_07 or Inter_ref_12_07 + + or Inter_ref_00_08 or Inter_ref_01_08 or Inter_ref_02_08 or Inter_ref_03_08 + or Inter_ref_04_08 or Inter_ref_05_08 or Inter_ref_06_08 or Inter_ref_07_08 + or Inter_ref_08_08 or Inter_ref_09_08 or Inter_ref_10_08 or Inter_ref_11_08 or Inter_ref_12_08 + + or Inter_ref_00_04 or Inter_ref_01_04 or Inter_ref_02_04 or Inter_ref_03_04 + or Inter_ref_04_04 or Inter_ref_05_04 or Inter_ref_06_04 or Inter_ref_07_04 + or Inter_ref_08_04 or Inter_ref_09_04 or Inter_ref_10_04 or Inter_ref_11_04 or Inter_ref_12_04 + + or Inter_ref_00_05 or Inter_ref_01_05 or Inter_ref_02_05 or Inter_ref_03_05 + or Inter_ref_04_05 or Inter_ref_05_05 or Inter_ref_06_05 or Inter_ref_07_05 + or Inter_ref_08_05 or Inter_ref_09_05 or Inter_ref_10_05 or Inter_ref_11_05 or Inter_ref_12_05 + + or Inter_ref_00_10 or Inter_ref_01_10 or Inter_ref_02_10 or Inter_ref_03_10 + or Inter_ref_04_10 or Inter_ref_05_10 or Inter_ref_06_10 or Inter_ref_07_10 + or Inter_ref_08_10 or Inter_ref_09_10 or Inter_ref_10_10 or Inter_ref_11_10 or Inter_ref_12_10 + + or Inter_ref_00_11 or Inter_ref_01_11 or Inter_ref_02_11 or Inter_ref_03_11 + or Inter_ref_04_11 or Inter_ref_05_11 or Inter_ref_06_11 or Inter_ref_07_11 + or Inter_ref_08_11 or Inter_ref_09_11 or Inter_ref_10_11 or Inter_ref_11_11 or Inter_ref_12_11 + + or Inter_ref_00_12 or Inter_ref_01_12 or Inter_ref_02_12 or Inter_ref_03_12 + or Inter_ref_04_12 or Inter_ref_05_12 or Inter_ref_06_12 or Inter_ref_07_12 + or Inter_ref_08_12 or Inter_ref_09_12 or Inter_ref_10_12 or Inter_ref_11_12 or Inter_ref_12_12 + ) + case ({Is_blk4x4_0,Is_blk4x4_1,Is_blk4x4_2,Is_blk4x4_3}) + 4'b1000: //Left top blk4x4 + case (Inter_H_window_counter0) + 3'd4: + begin + Inter_H_window_0_0 <= Inter_ref_00_00;Inter_H_window_1_0 <= Inter_ref_01_00; + Inter_H_window_2_0 <= Inter_ref_02_00;Inter_H_window_3_0 <= Inter_ref_03_00; + Inter_H_window_4_0 <= Inter_ref_04_00;Inter_H_window_5_0 <= Inter_ref_05_00; + + Inter_H_window_0_1 <= Inter_ref_00_01;Inter_H_window_1_1 <= Inter_ref_01_01; + Inter_H_window_2_1 <= Inter_ref_02_01;Inter_H_window_3_1 <= Inter_ref_03_01; + Inter_H_window_4_1 <= Inter_ref_04_01;Inter_H_window_5_1 <= Inter_ref_05_01; + + Inter_H_window_0_6 <= Inter_ref_00_06;Inter_H_window_1_6 <= Inter_ref_01_06; + Inter_H_window_2_6 <= Inter_ref_02_06;Inter_H_window_3_6 <= Inter_ref_03_06; + Inter_H_window_4_6 <= Inter_ref_04_06;Inter_H_window_5_6 <= Inter_ref_05_06; + + Inter_H_window_0_7 <= Inter_ref_00_07;Inter_H_window_1_7 <= Inter_ref_01_07; + Inter_H_window_2_7 <= Inter_ref_02_07;Inter_H_window_3_7 <= Inter_ref_03_07; + Inter_H_window_4_7 <= Inter_ref_04_07;Inter_H_window_5_7 <= Inter_ref_05_07; + + Inter_H_window_0_8 <= Inter_ref_00_08;Inter_H_window_1_8 <= Inter_ref_01_08; + Inter_H_window_2_8 <= Inter_ref_02_08;Inter_H_window_3_8 <= Inter_ref_03_08; + Inter_H_window_4_8 <= Inter_ref_04_08;Inter_H_window_5_8 <= Inter_ref_05_08; + end + 3'd3: + begin + Inter_H_window_0_0 <= Inter_ref_01_00;Inter_H_window_1_0 <= Inter_ref_02_00; + Inter_H_window_2_0 <= Inter_ref_03_00;Inter_H_window_3_0 <= Inter_ref_04_00; + Inter_H_window_4_0 <= Inter_ref_05_00;Inter_H_window_5_0 <= Inter_ref_06_00; + + Inter_H_window_0_1 <= Inter_ref_01_01;Inter_H_window_1_1 <= Inter_ref_02_01; + Inter_H_window_2_1 <= Inter_ref_03_01;Inter_H_window_3_1 <= Inter_ref_04_01; + Inter_H_window_4_1 <= Inter_ref_05_01;Inter_H_window_5_1 <= Inter_ref_06_01; + + Inter_H_window_0_6 <= Inter_ref_01_06;Inter_H_window_1_6 <= Inter_ref_02_06; + Inter_H_window_2_6 <= Inter_ref_03_06;Inter_H_window_3_6 <= Inter_ref_04_06; + Inter_H_window_4_6 <= Inter_ref_05_06;Inter_H_window_5_6 <= Inter_ref_06_06; + + Inter_H_window_0_7 <= Inter_ref_01_07;Inter_H_window_1_7 <= Inter_ref_02_07; + Inter_H_window_2_7 <= Inter_ref_03_07;Inter_H_window_3_7 <= Inter_ref_04_07; + Inter_H_window_4_7 <= Inter_ref_05_07;Inter_H_window_5_7 <= Inter_ref_06_07; + + Inter_H_window_0_8 <= Inter_ref_01_08;Inter_H_window_1_8 <= Inter_ref_02_08; + Inter_H_window_2_8 <= Inter_ref_03_08;Inter_H_window_3_8 <= Inter_ref_04_08; + Inter_H_window_4_8 <= Inter_ref_05_08;Inter_H_window_5_8 <= Inter_ref_06_08; + end + 3'd2: + begin + Inter_H_window_0_0 <= Inter_ref_02_00;Inter_H_window_1_0 <= Inter_ref_03_00; + Inter_H_window_2_0 <= Inter_ref_04_00;Inter_H_window_3_0 <= Inter_ref_05_00; + Inter_H_window_4_0 <= Inter_ref_06_00;Inter_H_window_5_0 <= Inter_ref_07_00; + + Inter_H_window_0_1 <= Inter_ref_02_01;Inter_H_window_1_1 <= Inter_ref_03_01; + Inter_H_window_2_1 <= Inter_ref_04_01;Inter_H_window_3_1 <= Inter_ref_05_01; + Inter_H_window_4_1 <= Inter_ref_06_01;Inter_H_window_5_1 <= Inter_ref_07_01; + + Inter_H_window_0_6 <= Inter_ref_02_06;Inter_H_window_1_6 <= Inter_ref_03_06; + Inter_H_window_2_6 <= Inter_ref_04_06;Inter_H_window_3_6 <= Inter_ref_05_06; + Inter_H_window_4_6 <= Inter_ref_06_06;Inter_H_window_5_6 <= Inter_ref_07_06; + + Inter_H_window_0_7 <= Inter_ref_02_07;Inter_H_window_1_7 <= Inter_ref_03_07; + Inter_H_window_2_7 <= Inter_ref_04_07;Inter_H_window_3_7 <= Inter_ref_05_07; + Inter_H_window_4_7 <= Inter_ref_06_07;Inter_H_window_5_7 <= Inter_ref_07_07; + + Inter_H_window_0_8 <= Inter_ref_02_08;Inter_H_window_1_8 <= Inter_ref_03_08; + Inter_H_window_2_8 <= Inter_ref_04_08;Inter_H_window_3_8 <= Inter_ref_05_08; + Inter_H_window_4_8 <= Inter_ref_06_08;Inter_H_window_5_8 <= Inter_ref_07_08; + end + 3'd1: + begin + Inter_H_window_0_0 <= Inter_ref_03_00;Inter_H_window_1_0 <= Inter_ref_04_00; + Inter_H_window_2_0 <= Inter_ref_05_00;Inter_H_window_3_0 <= Inter_ref_06_00; + Inter_H_window_4_0 <= Inter_ref_07_00;Inter_H_window_5_0 <= Inter_ref_08_00; + + Inter_H_window_0_1 <= Inter_ref_03_01;Inter_H_window_1_1 <= Inter_ref_04_01; + Inter_H_window_2_1 <= Inter_ref_05_01;Inter_H_window_3_1 <= Inter_ref_06_01; + Inter_H_window_4_1 <= Inter_ref_07_01;Inter_H_window_5_1 <= Inter_ref_08_01; + + Inter_H_window_0_6 <= Inter_ref_03_06;Inter_H_window_1_6 <= Inter_ref_04_06; + Inter_H_window_2_6 <= Inter_ref_05_06;Inter_H_window_3_6 <= Inter_ref_06_06; + Inter_H_window_4_6 <= Inter_ref_07_06;Inter_H_window_5_6 <= Inter_ref_08_06; + + Inter_H_window_0_7 <= Inter_ref_03_07;Inter_H_window_1_7 <= Inter_ref_04_07; + Inter_H_window_2_7 <= Inter_ref_05_07;Inter_H_window_3_7 <= Inter_ref_06_07; + Inter_H_window_4_7 <= Inter_ref_07_07;Inter_H_window_5_7 <= Inter_ref_08_07; + + Inter_H_window_0_8 <= Inter_ref_03_08;Inter_H_window_1_8 <= Inter_ref_04_08; + Inter_H_window_2_8 <= Inter_ref_05_08;Inter_H_window_3_8 <= Inter_ref_06_08; + Inter_H_window_4_8 <= Inter_ref_07_08;Inter_H_window_5_8 <= Inter_ref_08_08; + end + default: + begin + Inter_H_window_0_0 <= 0;Inter_H_window_1_0 <= 0;Inter_H_window_2_0 <= 0; + Inter_H_window_3_0 <= 0;Inter_H_window_4_0 <= 0;Inter_H_window_5_0 <= 0; + + Inter_H_window_0_1 <= 0;Inter_H_window_1_1 <= 0;Inter_H_window_2_1 <= 0; + Inter_H_window_3_1 <= 0;Inter_H_window_4_1 <= 0;Inter_H_window_5_1 <= 0; + + Inter_H_window_0_6 <= 0;Inter_H_window_1_6 <= 0;Inter_H_window_2_6 <= 0; + Inter_H_window_3_6 <= 0;Inter_H_window_4_6 <= 0;Inter_H_window_5_6 <= 0; + + Inter_H_window_0_7 <= 0;Inter_H_window_1_7 <= 0;Inter_H_window_2_7 <= 0; + Inter_H_window_3_7 <= 0;Inter_H_window_4_7 <= 0;Inter_H_window_5_7 <= 0; + + Inter_H_window_0_8 <= 0;Inter_H_window_1_8 <= 0;Inter_H_window_2_8 <= 0; + Inter_H_window_3_8 <= 0;Inter_H_window_4_8 <= 0;Inter_H_window_5_8 <= 0; + end + endcase + 4'b0100: //Right top blk8x8 + case (Inter_H_window_counter0) + 3'd4: + begin + Inter_H_window_0_0 <= Inter_ref_04_00;Inter_H_window_1_0 <= Inter_ref_05_00; + Inter_H_window_2_0 <= Inter_ref_06_00;Inter_H_window_3_0 <= Inter_ref_07_00; + Inter_H_window_4_0 <= Inter_ref_08_00;Inter_H_window_5_0 <= Inter_ref_09_00; + + Inter_H_window_0_1 <= Inter_ref_04_01;Inter_H_window_1_1 <= Inter_ref_05_01; + Inter_H_window_2_1 <= Inter_ref_06_01;Inter_H_window_3_1 <= Inter_ref_07_01; + Inter_H_window_4_1 <= Inter_ref_08_01;Inter_H_window_5_1 <= Inter_ref_09_01; + + Inter_H_window_0_6 <= Inter_ref_04_06;Inter_H_window_1_6 <= Inter_ref_05_06; + Inter_H_window_2_6 <= Inter_ref_06_06;Inter_H_window_3_6 <= Inter_ref_07_06; + Inter_H_window_4_6 <= Inter_ref_08_06;Inter_H_window_5_6 <= Inter_ref_09_06; + + Inter_H_window_0_7 <= Inter_ref_04_07;Inter_H_window_1_7 <= Inter_ref_05_07; + Inter_H_window_2_7 <= Inter_ref_06_07;Inter_H_window_3_7 <= Inter_ref_07_07; + Inter_H_window_4_7 <= Inter_ref_08_07;Inter_H_window_5_7 <= Inter_ref_09_07; + + Inter_H_window_0_8 <= Inter_ref_04_08;Inter_H_window_1_8 <= Inter_ref_05_08; + Inter_H_window_2_8 <= Inter_ref_06_08;Inter_H_window_3_8 <= Inter_ref_07_08; + Inter_H_window_4_8 <= Inter_ref_08_08;Inter_H_window_5_8 <= Inter_ref_09_08; + end + 3'd3: + begin + Inter_H_window_0_0 <= Inter_ref_05_00;Inter_H_window_1_0 <= Inter_ref_06_00; + Inter_H_window_2_0 <= Inter_ref_07_00;Inter_H_window_3_0 <= Inter_ref_08_00; + Inter_H_window_4_0 <= Inter_ref_09_00;Inter_H_window_5_0 <= Inter_ref_10_00; + + Inter_H_window_0_1 <= Inter_ref_05_01;Inter_H_window_1_1 <= Inter_ref_06_01; + Inter_H_window_2_1 <= Inter_ref_07_01;Inter_H_window_3_1 <= Inter_ref_08_01; + Inter_H_window_4_1 <= Inter_ref_09_01;Inter_H_window_5_1 <= Inter_ref_10_01; + + Inter_H_window_0_6 <= Inter_ref_05_06;Inter_H_window_1_6 <= Inter_ref_06_06; + Inter_H_window_2_6 <= Inter_ref_07_06;Inter_H_window_3_6 <= Inter_ref_08_06; + Inter_H_window_4_6 <= Inter_ref_09_06;Inter_H_window_5_6 <= Inter_ref_10_06; + + Inter_H_window_0_7 <= Inter_ref_05_07;Inter_H_window_1_7 <= Inter_ref_06_07; + Inter_H_window_2_7 <= Inter_ref_07_07;Inter_H_window_3_7 <= Inter_ref_08_07; + Inter_H_window_4_7 <= Inter_ref_09_07;Inter_H_window_5_7 <= Inter_ref_10_07; + + Inter_H_window_0_8 <= Inter_ref_05_08;Inter_H_window_1_8 <= Inter_ref_06_08; + Inter_H_window_2_8 <= Inter_ref_07_08;Inter_H_window_3_8 <= Inter_ref_08_08; + Inter_H_window_4_8 <= Inter_ref_09_08;Inter_H_window_5_8 <= Inter_ref_10_08; + end + 3'd2: + begin + Inter_H_window_0_0 <= Inter_ref_06_00;Inter_H_window_1_0 <= Inter_ref_07_00; + Inter_H_window_2_0 <= Inter_ref_08_00;Inter_H_window_3_0 <= Inter_ref_09_00; + Inter_H_window_4_0 <= Inter_ref_10_00;Inter_H_window_5_0 <= Inter_ref_11_00; + + Inter_H_window_0_1 <= Inter_ref_06_01;Inter_H_window_1_1 <= Inter_ref_07_01; + Inter_H_window_2_1 <= Inter_ref_08_01;Inter_H_window_3_1 <= Inter_ref_09_01; + Inter_H_window_4_1 <= Inter_ref_10_01;Inter_H_window_5_1 <= Inter_ref_11_01; + + Inter_H_window_0_6 <= Inter_ref_06_06;Inter_H_window_1_6 <= Inter_ref_07_06; + Inter_H_window_2_6 <= Inter_ref_08_06;Inter_H_window_3_6 <= Inter_ref_09_06; + Inter_H_window_4_6 <= Inter_ref_10_06;Inter_H_window_5_6 <= Inter_ref_11_06; + + Inter_H_window_0_7 <= Inter_ref_06_07;Inter_H_window_1_7 <= Inter_ref_07_07; + Inter_H_window_2_7 <= Inter_ref_08_07;Inter_H_window_3_7 <= Inter_ref_09_07; + Inter_H_window_4_7 <= Inter_ref_10_07;Inter_H_window_5_7 <= Inter_ref_11_07; + + Inter_H_window_0_8 <= Inter_ref_06_08;Inter_H_window_1_8 <= Inter_ref_07_08; + Inter_H_window_2_8 <= Inter_ref_08_08;Inter_H_window_3_8 <= Inter_ref_09_08; + Inter_H_window_4_8 <= Inter_ref_10_08;Inter_H_window_5_8 <= Inter_ref_11_08; + end + 3'd1: + begin + Inter_H_window_0_0 <= Inter_ref_07_00;Inter_H_window_1_0 <= Inter_ref_08_00; + Inter_H_window_2_0 <= Inter_ref_09_00;Inter_H_window_3_0 <= Inter_ref_10_00; + Inter_H_window_4_0 <= Inter_ref_11_00;Inter_H_window_5_0 <= Inter_ref_12_00; + + Inter_H_window_0_1 <= Inter_ref_07_01;Inter_H_window_1_1 <= Inter_ref_08_01; + Inter_H_window_2_1 <= Inter_ref_09_01;Inter_H_window_3_1 <= Inter_ref_10_01; + Inter_H_window_4_1 <= Inter_ref_11_01;Inter_H_window_5_1 <= Inter_ref_12_01; + + Inter_H_window_0_6 <= Inter_ref_07_06;Inter_H_window_1_6 <= Inter_ref_08_06; + Inter_H_window_2_6 <= Inter_ref_09_06;Inter_H_window_3_6 <= Inter_ref_10_06; + Inter_H_window_4_6 <= Inter_ref_11_06;Inter_H_window_5_6 <= Inter_ref_12_06; + + Inter_H_window_0_7 <= Inter_ref_07_07;Inter_H_window_1_7 <= Inter_ref_08_07; + Inter_H_window_2_7 <= Inter_ref_09_07;Inter_H_window_3_7 <= Inter_ref_10_07; + Inter_H_window_4_7 <= Inter_ref_11_07;Inter_H_window_5_7 <= Inter_ref_12_07; + + Inter_H_window_0_8 <= Inter_ref_07_08;Inter_H_window_1_8 <= Inter_ref_08_08; + Inter_H_window_2_8 <= Inter_ref_09_08;Inter_H_window_3_8 <= Inter_ref_10_08; + Inter_H_window_4_8 <= Inter_ref_11_08;Inter_H_window_5_8 <= Inter_ref_12_08; + end + default: + begin + Inter_H_window_0_0 <= 0;Inter_H_window_1_0 <= 0;Inter_H_window_2_0 <= 0; + Inter_H_window_3_0 <= 0;Inter_H_window_4_0 <= 0;Inter_H_window_5_0 <= 0; + + Inter_H_window_0_1 <= 0;Inter_H_window_1_1 <= 0;Inter_H_window_2_1 <= 0; + Inter_H_window_3_1 <= 0;Inter_H_window_4_1 <= 0;Inter_H_window_5_1 <= 0; + + Inter_H_window_0_6 <= 0;Inter_H_window_1_6 <= 0;Inter_H_window_2_6 <= 0; + Inter_H_window_3_6 <= 0;Inter_H_window_4_6 <= 0;Inter_H_window_5_6 <= 0; + + Inter_H_window_0_7 <= 0;Inter_H_window_1_7 <= 0;Inter_H_window_2_7 <= 0; + Inter_H_window_3_7 <= 0;Inter_H_window_4_7 <= 0;Inter_H_window_5_7 <= 0; + + Inter_H_window_0_8 <= 0;Inter_H_window_1_8 <= 0;Inter_H_window_2_8 <= 0; + Inter_H_window_3_8 <= 0;Inter_H_window_4_8 <= 0;Inter_H_window_5_8 <= 0; + end + endcase + 4'b0010: //Left bottom blk4x4 + case (Inter_H_window_counter0) + 3'd4: + begin + Inter_H_window_0_0 <= Inter_ref_00_04;Inter_H_window_1_0 <= Inter_ref_01_04; + Inter_H_window_2_0 <= Inter_ref_02_04;Inter_H_window_3_0 <= Inter_ref_03_04; + Inter_H_window_4_0 <= Inter_ref_04_04;Inter_H_window_5_0 <= Inter_ref_05_04; + + Inter_H_window_0_1 <= Inter_ref_00_05;Inter_H_window_1_1 <= Inter_ref_01_05; + Inter_H_window_2_1 <= Inter_ref_02_05;Inter_H_window_3_1 <= Inter_ref_03_05; + Inter_H_window_4_1 <= Inter_ref_04_05;Inter_H_window_5_1 <= Inter_ref_05_05; + + Inter_H_window_0_6 <= Inter_ref_00_10;Inter_H_window_1_6 <= Inter_ref_01_10; + Inter_H_window_2_6 <= Inter_ref_02_10;Inter_H_window_3_6 <= Inter_ref_03_10; + Inter_H_window_4_6 <= Inter_ref_04_10;Inter_H_window_5_6 <= Inter_ref_05_10; + + Inter_H_window_0_7 <= Inter_ref_00_11;Inter_H_window_1_7 <= Inter_ref_01_11; + Inter_H_window_2_7 <= Inter_ref_02_11;Inter_H_window_3_7 <= Inter_ref_03_11; + Inter_H_window_4_7 <= Inter_ref_04_11;Inter_H_window_5_7 <= Inter_ref_05_11; + + Inter_H_window_0_8 <= Inter_ref_00_12;Inter_H_window_1_8 <= Inter_ref_01_12; + Inter_H_window_2_8 <= Inter_ref_02_12;Inter_H_window_3_8 <= Inter_ref_03_12; + Inter_H_window_4_8 <= Inter_ref_04_12;Inter_H_window_5_8 <= Inter_ref_05_12; + end + 3'd3: + begin + Inter_H_window_0_0 <= Inter_ref_01_04;Inter_H_window_1_0 <= Inter_ref_02_04; + Inter_H_window_2_0 <= Inter_ref_03_04;Inter_H_window_3_0 <= Inter_ref_04_04; + Inter_H_window_4_0 <= Inter_ref_05_04;Inter_H_window_5_0 <= Inter_ref_06_04; + + Inter_H_window_0_1 <= Inter_ref_01_05;Inter_H_window_1_1 <= Inter_ref_02_05; + Inter_H_window_2_1 <= Inter_ref_03_05;Inter_H_window_3_1 <= Inter_ref_04_05; + Inter_H_window_4_1 <= Inter_ref_05_05;Inter_H_window_5_1 <= Inter_ref_06_05; + + Inter_H_window_0_6 <= Inter_ref_01_10;Inter_H_window_1_6 <= Inter_ref_02_10; + Inter_H_window_2_6 <= Inter_ref_03_10;Inter_H_window_3_6 <= Inter_ref_04_10; + Inter_H_window_4_6 <= Inter_ref_05_10;Inter_H_window_5_6 <= Inter_ref_06_10; + + Inter_H_window_0_7 <= Inter_ref_01_11;Inter_H_window_1_7 <= Inter_ref_02_11; + Inter_H_window_2_7 <= Inter_ref_03_11;Inter_H_window_3_7 <= Inter_ref_04_11; + Inter_H_window_4_7 <= Inter_ref_05_11;Inter_H_window_5_7 <= Inter_ref_06_11; + + Inter_H_window_0_8 <= Inter_ref_01_12;Inter_H_window_1_8 <= Inter_ref_02_12; + Inter_H_window_2_8 <= Inter_ref_03_12;Inter_H_window_3_8 <= Inter_ref_04_12; + Inter_H_window_4_8 <= Inter_ref_05_12;Inter_H_window_5_8 <= Inter_ref_06_12; + end + 3'd2: + begin + Inter_H_window_0_0 <= Inter_ref_02_04;Inter_H_window_1_0 <= Inter_ref_03_04; + Inter_H_window_2_0 <= Inter_ref_04_04;Inter_H_window_3_0 <= Inter_ref_05_04; + Inter_H_window_4_0 <= Inter_ref_06_04;Inter_H_window_5_0 <= Inter_ref_07_04; + + Inter_H_window_0_1 <= Inter_ref_02_05;Inter_H_window_1_1 <= Inter_ref_03_05; + Inter_H_window_2_1 <= Inter_ref_04_05;Inter_H_window_3_1 <= Inter_ref_05_05; + Inter_H_window_4_1 <= Inter_ref_06_05;Inter_H_window_5_1 <= Inter_ref_07_05; + + Inter_H_window_0_6 <= Inter_ref_02_10;Inter_H_window_1_6 <= Inter_ref_03_10; + Inter_H_window_2_6 <= Inter_ref_04_10;Inter_H_window_3_6 <= Inter_ref_05_10; + Inter_H_window_4_6 <= Inter_ref_06_10;Inter_H_window_5_6 <= Inter_ref_07_10; + + Inter_H_window_0_7 <= Inter_ref_02_11;Inter_H_window_1_7 <= Inter_ref_03_11; + Inter_H_window_2_7 <= Inter_ref_04_11;Inter_H_window_3_7 <= Inter_ref_05_11; + Inter_H_window_4_7 <= Inter_ref_06_11;Inter_H_window_5_7 <= Inter_ref_07_11; + + Inter_H_window_0_8 <= Inter_ref_02_12;Inter_H_window_1_8 <= Inter_ref_03_12; + Inter_H_window_2_8 <= Inter_ref_04_12;Inter_H_window_3_8 <= Inter_ref_05_12; + Inter_H_window_4_8 <= Inter_ref_06_12;Inter_H_window_5_8 <= Inter_ref_07_12; + end + 3'd1: + begin + Inter_H_window_0_0 <= Inter_ref_03_04;Inter_H_window_1_0 <= Inter_ref_04_04; + Inter_H_window_2_0 <= Inter_ref_05_04;Inter_H_window_3_0 <= Inter_ref_06_04; + Inter_H_window_4_0 <= Inter_ref_07_04;Inter_H_window_5_0 <= Inter_ref_08_04; + + Inter_H_window_0_1 <= Inter_ref_03_05;Inter_H_window_1_1 <= Inter_ref_04_05; + Inter_H_window_2_1 <= Inter_ref_05_05;Inter_H_window_3_1 <= Inter_ref_06_05; + Inter_H_window_4_1 <= Inter_ref_07_05;Inter_H_window_5_1 <= Inter_ref_08_05; + + Inter_H_window_0_6 <= Inter_ref_03_10;Inter_H_window_1_6 <= Inter_ref_04_10; + Inter_H_window_2_6 <= Inter_ref_05_10;Inter_H_window_3_6 <= Inter_ref_06_10; + Inter_H_window_4_6 <= Inter_ref_07_10;Inter_H_window_5_6 <= Inter_ref_08_10; + + Inter_H_window_0_7 <= Inter_ref_03_11;Inter_H_window_1_7 <= Inter_ref_04_11; + Inter_H_window_2_7 <= Inter_ref_05_11;Inter_H_window_3_7 <= Inter_ref_06_11; + Inter_H_window_4_7 <= Inter_ref_07_11;Inter_H_window_5_7 <= Inter_ref_08_11; + + Inter_H_window_0_8 <= Inter_ref_03_12;Inter_H_window_1_8 <= Inter_ref_04_12; + Inter_H_window_2_8 <= Inter_ref_05_12;Inter_H_window_3_8 <= Inter_ref_06_12; + Inter_H_window_4_8 <= Inter_ref_07_12;Inter_H_window_5_8 <= Inter_ref_08_12; + end + default: + begin + Inter_H_window_0_0 <= 0;Inter_H_window_1_0 <= 0;Inter_H_window_2_0 <= 0; + Inter_H_window_3_0 <= 0;Inter_H_window_4_0 <= 0;Inter_H_window_5_0 <= 0; + + Inter_H_window_0_1 <= 0;Inter_H_window_1_1 <= 0;Inter_H_window_2_1 <= 0; + Inter_H_window_3_1 <= 0;Inter_H_window_4_1 <= 0;Inter_H_window_5_1 <= 0; + + Inter_H_window_0_6 <= 0;Inter_H_window_1_6 <= 0;Inter_H_window_2_6 <= 0; + Inter_H_window_3_6 <= 0;Inter_H_window_4_6 <= 0;Inter_H_window_5_6 <= 0; + + Inter_H_window_0_7 <= 0;Inter_H_window_1_7 <= 0;Inter_H_window_2_7 <= 0; + Inter_H_window_3_7 <= 0;Inter_H_window_4_7 <= 0;Inter_H_window_5_7 <= 0; + + Inter_H_window_0_8 <= 0;Inter_H_window_1_8 <= 0;Inter_H_window_2_8 <= 0; + Inter_H_window_3_8 <= 0;Inter_H_window_4_8 <= 0;Inter_H_window_5_8 <= 0; + end + endcase + 4'b0001: //Right bottom blk4x4 + case (Inter_H_window_counter0) + 3'd4: + begin + Inter_H_window_0_0 <= Inter_ref_04_04;Inter_H_window_1_0 <= Inter_ref_05_04; + Inter_H_window_2_0 <= Inter_ref_06_04;Inter_H_window_3_0 <= Inter_ref_07_04; + Inter_H_window_4_0 <= Inter_ref_08_04;Inter_H_window_5_0 <= Inter_ref_09_04; + + Inter_H_window_0_1 <= Inter_ref_04_05;Inter_H_window_1_1 <= Inter_ref_05_05; + Inter_H_window_2_1 <= Inter_ref_06_05;Inter_H_window_3_1 <= Inter_ref_07_05; + Inter_H_window_4_1 <= Inter_ref_08_05;Inter_H_window_5_1 <= Inter_ref_09_05; + + Inter_H_window_0_6 <= Inter_ref_04_10;Inter_H_window_1_6 <= Inter_ref_05_10; + Inter_H_window_2_6 <= Inter_ref_06_10;Inter_H_window_3_6 <= Inter_ref_07_10; + Inter_H_window_4_6 <= Inter_ref_08_10;Inter_H_window_5_6 <= Inter_ref_09_10; + + Inter_H_window_0_7 <= Inter_ref_04_11;Inter_H_window_1_7 <= Inter_ref_05_11; + Inter_H_window_2_7 <= Inter_ref_06_11;Inter_H_window_3_7 <= Inter_ref_07_11; + Inter_H_window_4_7 <= Inter_ref_08_11;Inter_H_window_5_7 <= Inter_ref_09_11; + + Inter_H_window_0_8 <= Inter_ref_04_12;Inter_H_window_1_8 <= Inter_ref_05_12; + Inter_H_window_2_8 <= Inter_ref_06_12;Inter_H_window_3_8 <= Inter_ref_07_12; + Inter_H_window_4_8 <= Inter_ref_08_12;Inter_H_window_5_8 <= Inter_ref_09_12; + end + 3'd3: + begin + Inter_H_window_0_0 <= Inter_ref_05_04;Inter_H_window_1_0 <= Inter_ref_06_04; + Inter_H_window_2_0 <= Inter_ref_07_04;Inter_H_window_3_0 <= Inter_ref_08_04; + Inter_H_window_4_0 <= Inter_ref_09_04;Inter_H_window_5_0 <= Inter_ref_10_04; + + Inter_H_window_0_1 <= Inter_ref_05_05;Inter_H_window_1_1 <= Inter_ref_06_05; + Inter_H_window_2_1 <= Inter_ref_07_05;Inter_H_window_3_1 <= Inter_ref_08_05; + Inter_H_window_4_1 <= Inter_ref_09_05;Inter_H_window_5_1 <= Inter_ref_10_05; + + Inter_H_window_0_6 <= Inter_ref_05_10;Inter_H_window_1_6 <= Inter_ref_06_10; + Inter_H_window_2_6 <= Inter_ref_07_10;Inter_H_window_3_6 <= Inter_ref_08_10; + Inter_H_window_4_6 <= Inter_ref_09_10;Inter_H_window_5_6 <= Inter_ref_10_10; + + Inter_H_window_0_7 <= Inter_ref_05_11;Inter_H_window_1_7 <= Inter_ref_06_11; + Inter_H_window_2_7 <= Inter_ref_07_11;Inter_H_window_3_7 <= Inter_ref_08_11; + Inter_H_window_4_7 <= Inter_ref_09_11;Inter_H_window_5_7 <= Inter_ref_10_11; + + Inter_H_window_0_8 <= Inter_ref_05_12;Inter_H_window_1_8 <= Inter_ref_06_12; + Inter_H_window_2_8 <= Inter_ref_07_12;Inter_H_window_3_8 <= Inter_ref_08_12; + Inter_H_window_4_8 <= Inter_ref_09_12;Inter_H_window_5_8 <= Inter_ref_10_12; + end + 3'd2: + begin + Inter_H_window_0_0 <= Inter_ref_06_04;Inter_H_window_1_0 <= Inter_ref_07_04; + Inter_H_window_2_0 <= Inter_ref_08_04;Inter_H_window_3_0 <= Inter_ref_09_04; + Inter_H_window_4_0 <= Inter_ref_10_04;Inter_H_window_5_0 <= Inter_ref_11_04; + + Inter_H_window_0_1 <= Inter_ref_06_05;Inter_H_window_1_1 <= Inter_ref_07_05; + Inter_H_window_2_1 <= Inter_ref_08_05;Inter_H_window_3_1 <= Inter_ref_09_05; + Inter_H_window_4_1 <= Inter_ref_10_05;Inter_H_window_5_1 <= Inter_ref_11_05; + + Inter_H_window_0_6 <= Inter_ref_06_10;Inter_H_window_1_6 <= Inter_ref_07_10; + Inter_H_window_2_6 <= Inter_ref_08_10;Inter_H_window_3_6 <= Inter_ref_09_10; + Inter_H_window_4_6 <= Inter_ref_10_10;Inter_H_window_5_6 <= Inter_ref_11_10; + + Inter_H_window_0_7 <= Inter_ref_06_11;Inter_H_window_1_7 <= Inter_ref_07_11; + Inter_H_window_2_7 <= Inter_ref_08_11;Inter_H_window_3_7 <= Inter_ref_09_11; + Inter_H_window_4_7 <= Inter_ref_10_11;Inter_H_window_5_7 <= Inter_ref_11_11; + + Inter_H_window_0_8 <= Inter_ref_06_12;Inter_H_window_1_8 <= Inter_ref_07_12; + Inter_H_window_2_8 <= Inter_ref_08_12;Inter_H_window_3_8 <= Inter_ref_09_12; + Inter_H_window_4_8 <= Inter_ref_10_12;Inter_H_window_5_8 <= Inter_ref_11_12; + end + 3'd1: + begin + Inter_H_window_0_0 <= Inter_ref_07_04;Inter_H_window_1_0 <= Inter_ref_08_04; + Inter_H_window_2_0 <= Inter_ref_09_04;Inter_H_window_3_0 <= Inter_ref_10_04; + Inter_H_window_4_0 <= Inter_ref_11_04;Inter_H_window_5_0 <= Inter_ref_12_04; + + Inter_H_window_0_1 <= Inter_ref_07_05;Inter_H_window_1_1 <= Inter_ref_08_05; + Inter_H_window_2_1 <= Inter_ref_09_05;Inter_H_window_3_1 <= Inter_ref_10_05; + Inter_H_window_4_1 <= Inter_ref_11_05;Inter_H_window_5_1 <= Inter_ref_12_05; + + Inter_H_window_0_6 <= Inter_ref_07_10;Inter_H_window_1_6 <= Inter_ref_08_10; + Inter_H_window_2_6 <= Inter_ref_09_10;Inter_H_window_3_6 <= Inter_ref_10_10; + Inter_H_window_4_6 <= Inter_ref_11_10;Inter_H_window_5_6 <= Inter_ref_12_10; + + Inter_H_window_0_7 <= Inter_ref_07_11;Inter_H_window_1_7 <= Inter_ref_08_11; + Inter_H_window_2_7 <= Inter_ref_09_11;Inter_H_window_3_7 <= Inter_ref_10_11; + Inter_H_window_4_7 <= Inter_ref_11_11;Inter_H_window_5_7 <= Inter_ref_12_11; + + Inter_H_window_0_8 <= Inter_ref_07_12;Inter_H_window_1_8 <= Inter_ref_08_12; + Inter_H_window_2_8 <= Inter_ref_09_12;Inter_H_window_3_8 <= Inter_ref_10_12; + Inter_H_window_4_8 <= Inter_ref_11_12;Inter_H_window_5_8 <= Inter_ref_12_12; + end + default: + begin + Inter_H_window_0_0 <= 0;Inter_H_window_1_0 <= 0;Inter_H_window_2_0 <= 0; + Inter_H_window_3_0 <= 0;Inter_H_window_4_0 <= 0;Inter_H_window_5_0 <= 0; + + Inter_H_window_0_1 <= 0;Inter_H_window_1_1 <= 0;Inter_H_window_2_1 <= 0; + Inter_H_window_3_1 <= 0;Inter_H_window_4_1 <= 0;Inter_H_window_5_1 <= 0; + + Inter_H_window_0_6 <= 0;Inter_H_window_1_6 <= 0;Inter_H_window_2_6 <= 0; + Inter_H_window_3_6 <= 0;Inter_H_window_4_6 <= 0;Inter_H_window_5_6 <= 0; + + Inter_H_window_0_7 <= 0;Inter_H_window_1_7 <= 0;Inter_H_window_2_7 <= 0; + Inter_H_window_3_7 <= 0;Inter_H_window_4_7 <= 0;Inter_H_window_5_7 <= 0; + + Inter_H_window_0_8 <= 0;Inter_H_window_1_8 <= 0;Inter_H_window_2_8 <= 0; + Inter_H_window_3_8 <= 0;Inter_H_window_4_8 <= 0;Inter_H_window_5_8 <= 0; + end + endcase + default: + begin + Inter_H_window_0_0 <= 0;Inter_H_window_1_0 <= 0;Inter_H_window_2_0 <= 0; + Inter_H_window_3_0 <= 0;Inter_H_window_4_0 <= 0;Inter_H_window_5_0 <= 0; + + Inter_H_window_0_1 <= 0;Inter_H_window_1_1 <= 0;Inter_H_window_2_1 <= 0; + Inter_H_window_3_1 <= 0;Inter_H_window_4_1 <= 0;Inter_H_window_5_1 <= 0; + + Inter_H_window_0_6 <= 0;Inter_H_window_1_6 <= 0;Inter_H_window_2_6 <= 0; + Inter_H_window_3_6 <= 0;Inter_H_window_4_6 <= 0;Inter_H_window_5_6 <= 0; + + Inter_H_window_0_7 <= 0;Inter_H_window_1_7 <= 0;Inter_H_window_2_7 <= 0; + Inter_H_window_3_7 <= 0;Inter_H_window_4_7 <= 0;Inter_H_window_5_7 <= 0; + + Inter_H_window_0_8 <= 0;Inter_H_window_1_8 <= 0;Inter_H_window_2_8 <= 0; + Inter_H_window_3_8 <= 0;Inter_H_window_4_8 <= 0;Inter_H_window_5_8 <= 0; + end + endcase + + //Inter_H_window_counter1:for Inter_H_window_x_2/3/4/5 sliding window control + reg [2:0] Inter_H_window_counter1; + always @ (pos_FracL or blk4x4_inter_calculate_counter) + if (((pos_FracL == `pos_b || pos_FracL == `pos_a || pos_FracL == `pos_c || pos_FracL == `pos_e || pos_FracL == `pos_g + || pos_FracL == `pos_p || pos_FracL == `pos_r) && blk4x4_inter_calculate_counter == 4'd4) || + ((pos_FracL == `pos_j || pos_FracL == `pos_f || pos_FracL == `pos_q) && blk4x4_inter_calculate_counter == 4'd5) || + ((pos_FracL == `pos_i || pos_FracL == `pos_k) && blk4x4_inter_calculate_counter == 4'd8)) + Inter_H_window_counter1 <= 3'd4; + else if (((pos_FracL == `pos_b || pos_FracL == `pos_a || pos_FracL == `pos_c || pos_FracL == `pos_e || pos_FracL == `pos_g + || pos_FracL == `pos_p || pos_FracL == `pos_r) && blk4x4_inter_calculate_counter == 4'd3) || + ((pos_FracL == `pos_j || pos_FracL == `pos_f || pos_FracL == `pos_q) && blk4x4_inter_calculate_counter == 4'd4) || + ((pos_FracL == `pos_i || pos_FracL == `pos_k) && blk4x4_inter_calculate_counter == 4'd6)) + Inter_H_window_counter1 <= 3'd3; + else if (((pos_FracL == `pos_b || pos_FracL == `pos_a || pos_FracL == `pos_c || pos_FracL == `pos_e || pos_FracL == `pos_g + || pos_FracL == `pos_p || pos_FracL == `pos_r) && blk4x4_inter_calculate_counter == 4'd2) || + ((pos_FracL == `pos_j || pos_FracL == `pos_f || pos_FracL == `pos_q) && blk4x4_inter_calculate_counter == 4'd3) || + ((pos_FracL == `pos_i || pos_FracL == `pos_k) && blk4x4_inter_calculate_counter == 4'd4)) + Inter_H_window_counter1 <= 3'd2; + else if (((pos_FracL == `pos_b || pos_FracL == `pos_a || pos_FracL == `pos_c || pos_FracL == `pos_e || pos_FracL == `pos_g + || pos_FracL == `pos_p || pos_FracL == `pos_r) && blk4x4_inter_calculate_counter == 4'd1) || + ((pos_FracL == `pos_j || pos_FracL == `pos_f || pos_FracL == `pos_q) && blk4x4_inter_calculate_counter == 4'd2) || + ((pos_FracL == `pos_i || pos_FracL == `pos_k) && blk4x4_inter_calculate_counter == 4'd2)) + Inter_H_window_counter1 <= 3'd1; + else + Inter_H_window_counter1 <= 0; + + //Inter_H_window_x_2,Inter_H_window_x_3,Inter_H_window_x_4,Inter_H_window_x_5 + always @ (Is_blk4x4_0 or Is_blk4x4_1 or Is_blk4x4_2 or Is_blk4x4_3 or pos_FracL or Inter_H_window_counter1 + or Inter_ref_00_02 or Inter_ref_01_02 or Inter_ref_02_02 or Inter_ref_03_02 + or Inter_ref_04_02 or Inter_ref_05_02 or Inter_ref_06_02 or Inter_ref_07_02 + or Inter_ref_08_02 or Inter_ref_09_02 or Inter_ref_10_02 or Inter_ref_11_02 or Inter_ref_12_02 + + or Inter_ref_00_03 or Inter_ref_01_03 or Inter_ref_02_03 or Inter_ref_03_03 + or Inter_ref_04_03 or Inter_ref_05_03 or Inter_ref_06_03 or Inter_ref_07_03 + or Inter_ref_08_03 or Inter_ref_09_03 or Inter_ref_10_03 or Inter_ref_11_03 or Inter_ref_12_03 + + or Inter_ref_00_04 or Inter_ref_01_04 or Inter_ref_02_04 or Inter_ref_03_04 + or Inter_ref_04_04 or Inter_ref_05_04 or Inter_ref_06_04 or Inter_ref_07_04 + or Inter_ref_08_04 or Inter_ref_09_04 or Inter_ref_10_04 or Inter_ref_11_04 or Inter_ref_12_04 + + or Inter_ref_00_05 or Inter_ref_01_05 or Inter_ref_02_05 or Inter_ref_03_05 + or Inter_ref_04_05 or Inter_ref_05_05 or Inter_ref_06_05 or Inter_ref_07_05 + or Inter_ref_08_05 or Inter_ref_09_05 or Inter_ref_10_05 or Inter_ref_11_05 or Inter_ref_12_05 + + or Inter_ref_00_06 or Inter_ref_01_06 or Inter_ref_02_06 or Inter_ref_03_06 + or Inter_ref_04_06 or Inter_ref_05_06 or Inter_ref_06_06 or Inter_ref_07_06 + or Inter_ref_08_06 or Inter_ref_09_06 or Inter_ref_10_06 or Inter_ref_11_06 or Inter_ref_12_06 + + or Inter_ref_00_07 or Inter_ref_01_07 or Inter_ref_02_07 or Inter_ref_03_07 + or Inter_ref_04_07 or Inter_ref_05_07 or Inter_ref_06_07 or Inter_ref_07_07 + or Inter_ref_08_07 or Inter_ref_09_07 or Inter_ref_10_07 or Inter_ref_11_07 or Inter_ref_12_07 + + or Inter_ref_00_08 or Inter_ref_01_08 or Inter_ref_02_08 or Inter_ref_03_08 + or Inter_ref_04_08 or Inter_ref_05_08 or Inter_ref_06_08 or Inter_ref_07_08 + or Inter_ref_08_08 or Inter_ref_09_08 or Inter_ref_10_08 or Inter_ref_11_08 or Inter_ref_12_08 + + or Inter_ref_00_09 or Inter_ref_01_09 or Inter_ref_02_09 or Inter_ref_03_09 + or Inter_ref_04_09 or Inter_ref_05_09 or Inter_ref_06_09 or Inter_ref_07_09 + or Inter_ref_08_09 or Inter_ref_09_09 or Inter_ref_10_09 or Inter_ref_11_09 or Inter_ref_12_09 + + or Inter_ref_00_10 or Inter_ref_01_10 or Inter_ref_02_10 or Inter_ref_03_10 + or Inter_ref_04_10 or Inter_ref_05_10 or Inter_ref_06_10 or Inter_ref_07_10 + or Inter_ref_08_10 or Inter_ref_09_10 or Inter_ref_10_10 or Inter_ref_11_10 or Inter_ref_12_10 + ) + case ({Is_blk4x4_0,Is_blk4x4_1,Is_blk4x4_2,Is_blk4x4_3}) + 4'b1000: //Left top blk4x4 + case (Inter_H_window_counter1) + 3'd4: + if (pos_FracL == `pos_p || pos_FracL == `pos_r) + begin + Inter_H_window_0_2 <= Inter_ref_00_03;Inter_H_window_1_2 <= Inter_ref_01_03; + Inter_H_window_2_2 <= Inter_ref_02_03;Inter_H_window_3_2 <= Inter_ref_03_03; + Inter_H_window_4_2 <= Inter_ref_04_03;Inter_H_window_5_2 <= Inter_ref_05_03; + + Inter_H_window_0_3 <= Inter_ref_00_04;Inter_H_window_1_3 <= Inter_ref_01_04; + Inter_H_window_2_3 <= Inter_ref_02_04;Inter_H_window_3_3 <= Inter_ref_03_04; + Inter_H_window_4_3 <= Inter_ref_04_04;Inter_H_window_5_3 <= Inter_ref_05_04; + + Inter_H_window_0_4 <= Inter_ref_00_05;Inter_H_window_1_4 <= Inter_ref_01_05; + Inter_H_window_2_4 <= Inter_ref_02_05;Inter_H_window_3_4 <= Inter_ref_03_05; + Inter_H_window_4_4 <= Inter_ref_04_05;Inter_H_window_5_4 <= Inter_ref_05_05; + + Inter_H_window_0_5 <= Inter_ref_00_06;Inter_H_window_1_5 <= Inter_ref_01_06; + Inter_H_window_2_5 <= Inter_ref_02_06;Inter_H_window_3_5 <= Inter_ref_03_06; + Inter_H_window_4_5 <= Inter_ref_04_06;Inter_H_window_5_5 <= Inter_ref_05_06; + end + else + begin + Inter_H_window_0_2 <= Inter_ref_00_02;Inter_H_window_1_2 <= Inter_ref_01_02; + Inter_H_window_2_2 <= Inter_ref_02_02;Inter_H_window_3_2 <= Inter_ref_03_02; + Inter_H_window_4_2 <= Inter_ref_04_02;Inter_H_window_5_2 <= Inter_ref_05_02; + + Inter_H_window_0_3 <= Inter_ref_00_03;Inter_H_window_1_3 <= Inter_ref_01_03; + Inter_H_window_2_3 <= Inter_ref_02_03;Inter_H_window_3_3 <= Inter_ref_03_03; + Inter_H_window_4_3 <= Inter_ref_04_03;Inter_H_window_5_3 <= Inter_ref_05_03; + + Inter_H_window_0_4 <= Inter_ref_00_04;Inter_H_window_1_4 <= Inter_ref_01_04; + Inter_H_window_2_4 <= Inter_ref_02_04;Inter_H_window_3_4 <= Inter_ref_03_04; + Inter_H_window_4_4 <= Inter_ref_04_04;Inter_H_window_5_4 <= Inter_ref_05_04; + + Inter_H_window_0_5 <= Inter_ref_00_05;Inter_H_window_1_5 <= Inter_ref_01_05; + Inter_H_window_2_5 <= Inter_ref_02_05;Inter_H_window_3_5 <= Inter_ref_03_05; + Inter_H_window_4_5 <= Inter_ref_04_05;Inter_H_window_5_5 <= Inter_ref_05_05; + end + 3'd3: + if (pos_FracL == `pos_p || pos_FracL == `pos_r) + begin + Inter_H_window_0_2 <= Inter_ref_01_03;Inter_H_window_1_2 <= Inter_ref_02_03; + Inter_H_window_2_2 <= Inter_ref_03_03;Inter_H_window_3_2 <= Inter_ref_04_03; + Inter_H_window_4_2 <= Inter_ref_05_03;Inter_H_window_5_2 <= Inter_ref_06_03; + + Inter_H_window_0_3 <= Inter_ref_01_04;Inter_H_window_1_3 <= Inter_ref_02_04; + Inter_H_window_2_3 <= Inter_ref_03_04;Inter_H_window_3_3 <= Inter_ref_04_04; + Inter_H_window_4_3 <= Inter_ref_05_04;Inter_H_window_5_3 <= Inter_ref_06_04; + + Inter_H_window_0_4 <= Inter_ref_01_05;Inter_H_window_1_4 <= Inter_ref_02_05; + Inter_H_window_2_4 <= Inter_ref_03_05;Inter_H_window_3_4 <= Inter_ref_04_05; + Inter_H_window_4_4 <= Inter_ref_05_05;Inter_H_window_5_4 <= Inter_ref_06_05; + + Inter_H_window_0_5 <= Inter_ref_01_06;Inter_H_window_1_5 <= Inter_ref_02_06; + Inter_H_window_2_5 <= Inter_ref_03_06;Inter_H_window_3_5 <= Inter_ref_04_06; + Inter_H_window_4_5 <= Inter_ref_05_06;Inter_H_window_5_5 <= Inter_ref_06_06; + end + else + begin + Inter_H_window_0_2 <= Inter_ref_01_02;Inter_H_window_1_2 <= Inter_ref_02_02; + Inter_H_window_2_2 <= Inter_ref_03_02;Inter_H_window_3_2 <= Inter_ref_04_02; + Inter_H_window_4_2 <= Inter_ref_05_02;Inter_H_window_5_2 <= Inter_ref_06_02; + + Inter_H_window_0_3 <= Inter_ref_01_03;Inter_H_window_1_3 <= Inter_ref_02_03; + Inter_H_window_2_3 <= Inter_ref_03_03;Inter_H_window_3_3 <= Inter_ref_04_03; + Inter_H_window_4_3 <= Inter_ref_05_03;Inter_H_window_5_3 <= Inter_ref_06_03; + + Inter_H_window_0_4 <= Inter_ref_01_04;Inter_H_window_1_4 <= Inter_ref_02_04; + Inter_H_window_2_4 <= Inter_ref_03_04;Inter_H_window_3_4 <= Inter_ref_04_04; + Inter_H_window_4_4 <= Inter_ref_05_04;Inter_H_window_5_4 <= Inter_ref_06_04; + + Inter_H_window_0_5 <= Inter_ref_01_05;Inter_H_window_1_5 <= Inter_ref_02_05; + Inter_H_window_2_5 <= Inter_ref_03_05;Inter_H_window_3_5 <= Inter_ref_04_05; + Inter_H_window_4_5 <= Inter_ref_05_05;Inter_H_window_5_5 <= Inter_ref_06_05; + end + 3'd2: + if (pos_FracL == `pos_p || pos_FracL == `pos_r) + begin + Inter_H_window_0_2 <= Inter_ref_02_03;Inter_H_window_1_2 <= Inter_ref_03_03; + Inter_H_window_2_2 <= Inter_ref_04_03;Inter_H_window_3_2 <= Inter_ref_05_03; + Inter_H_window_4_2 <= Inter_ref_06_03;Inter_H_window_5_2 <= Inter_ref_07_03; + + Inter_H_window_0_3 <= Inter_ref_02_04;Inter_H_window_1_3 <= Inter_ref_03_04; + Inter_H_window_2_3 <= Inter_ref_04_04;Inter_H_window_3_3 <= Inter_ref_05_04; + Inter_H_window_4_3 <= Inter_ref_06_04;Inter_H_window_5_3 <= Inter_ref_07_04; + + Inter_H_window_0_4 <= Inter_ref_02_05;Inter_H_window_1_4 <= Inter_ref_03_05; + Inter_H_window_2_4 <= Inter_ref_04_05;Inter_H_window_3_4 <= Inter_ref_05_05; + Inter_H_window_4_4 <= Inter_ref_06_05;Inter_H_window_5_4 <= Inter_ref_07_05; + + Inter_H_window_0_5 <= Inter_ref_02_06;Inter_H_window_1_5 <= Inter_ref_03_06; + Inter_H_window_2_5 <= Inter_ref_04_06;Inter_H_window_3_5 <= Inter_ref_05_06; + Inter_H_window_4_5 <= Inter_ref_06_06;Inter_H_window_5_5 <= Inter_ref_07_06; + end + else + begin + Inter_H_window_0_2 <= Inter_ref_02_02;Inter_H_window_1_2 <= Inter_ref_03_02; + Inter_H_window_2_2 <= Inter_ref_04_02;Inter_H_window_3_2 <= Inter_ref_05_02; + Inter_H_window_4_2 <= Inter_ref_06_02;Inter_H_window_5_2 <= Inter_ref_07_02; + + Inter_H_window_0_3 <= Inter_ref_02_03;Inter_H_window_1_3 <= Inter_ref_03_03; + Inter_H_window_2_3 <= Inter_ref_04_03;Inter_H_window_3_3 <= Inter_ref_05_03; + Inter_H_window_4_3 <= Inter_ref_06_03;Inter_H_window_5_3 <= Inter_ref_07_03; + + Inter_H_window_0_4 <= Inter_ref_02_04;Inter_H_window_1_4 <= Inter_ref_03_04; + Inter_H_window_2_4 <= Inter_ref_04_04;Inter_H_window_3_4 <= Inter_ref_05_04; + Inter_H_window_4_4 <= Inter_ref_06_04;Inter_H_window_5_4 <= Inter_ref_07_04; + + Inter_H_window_0_5 <= Inter_ref_02_05;Inter_H_window_1_5 <= Inter_ref_03_05; + Inter_H_window_2_5 <= Inter_ref_04_05;Inter_H_window_3_5 <= Inter_ref_05_05; + Inter_H_window_4_5 <= Inter_ref_06_05;Inter_H_window_5_5 <= Inter_ref_07_05; + end + 3'd1: + if (pos_FracL == `pos_p || pos_FracL == `pos_r) + begin + Inter_H_window_0_2 <= Inter_ref_03_03;Inter_H_window_1_2 <= Inter_ref_04_03; + Inter_H_window_2_2 <= Inter_ref_05_03;Inter_H_window_3_2 <= Inter_ref_06_03; + Inter_H_window_4_2 <= Inter_ref_07_03;Inter_H_window_5_2 <= Inter_ref_08_03; + + Inter_H_window_0_3 <= Inter_ref_03_04;Inter_H_window_1_3 <= Inter_ref_04_04; + Inter_H_window_2_3 <= Inter_ref_05_04;Inter_H_window_3_3 <= Inter_ref_06_04; + Inter_H_window_4_3 <= Inter_ref_07_04;Inter_H_window_5_3 <= Inter_ref_08_04; + + Inter_H_window_0_4 <= Inter_ref_03_05;Inter_H_window_1_4 <= Inter_ref_04_05; + Inter_H_window_2_4 <= Inter_ref_05_05;Inter_H_window_3_4 <= Inter_ref_06_05; + Inter_H_window_4_4 <= Inter_ref_07_05;Inter_H_window_5_4 <= Inter_ref_08_05; + + Inter_H_window_0_5 <= Inter_ref_03_06;Inter_H_window_1_5 <= Inter_ref_04_06; + Inter_H_window_2_5 <= Inter_ref_05_06;Inter_H_window_3_5 <= Inter_ref_06_06; + Inter_H_window_4_5 <= Inter_ref_07_06;Inter_H_window_5_5 <= Inter_ref_08_06; + end + else + begin + Inter_H_window_0_2 <= Inter_ref_03_02;Inter_H_window_1_2 <= Inter_ref_04_02; + Inter_H_window_2_2 <= Inter_ref_05_02;Inter_H_window_3_2 <= Inter_ref_06_02; + Inter_H_window_4_2 <= Inter_ref_07_02;Inter_H_window_5_2 <= Inter_ref_08_02; + + Inter_H_window_0_3 <= Inter_ref_03_03;Inter_H_window_1_3 <= Inter_ref_04_03; + Inter_H_window_2_3 <= Inter_ref_05_03;Inter_H_window_3_3 <= Inter_ref_06_03; + Inter_H_window_4_3 <= Inter_ref_07_03;Inter_H_window_5_3 <= Inter_ref_08_03; + + Inter_H_window_0_4 <= Inter_ref_03_04;Inter_H_window_1_4 <= Inter_ref_04_04; + Inter_H_window_2_4 <= Inter_ref_05_04;Inter_H_window_3_4 <= Inter_ref_06_04; + Inter_H_window_4_4 <= Inter_ref_07_04;Inter_H_window_5_4 <= Inter_ref_08_04; + + Inter_H_window_0_5 <= Inter_ref_03_05;Inter_H_window_1_5 <= Inter_ref_04_05; + Inter_H_window_2_5 <= Inter_ref_05_05;Inter_H_window_3_5 <= Inter_ref_06_05; + Inter_H_window_4_5 <= Inter_ref_07_05;Inter_H_window_5_5 <= Inter_ref_08_05; + end + default: + begin + Inter_H_window_0_2 <= 0;Inter_H_window_1_2 <= 0;Inter_H_window_2_2 <= 0; + Inter_H_window_3_2 <= 0;Inter_H_window_4_2 <= 0;Inter_H_window_5_2 <= 0; + + Inter_H_window_0_3 <= 0;Inter_H_window_1_3 <= 0;Inter_H_window_2_3 <= 0; + Inter_H_window_3_3 <= 0;Inter_H_window_4_3 <= 0;Inter_H_window_5_3 <= 0; + + Inter_H_window_0_4 <= 0;Inter_H_window_1_4 <= 0;Inter_H_window_2_4 <= 0; + Inter_H_window_3_4 <= 0;Inter_H_window_4_4 <= 0;Inter_H_window_5_4 <= 0; + + Inter_H_window_0_5 <= 0;Inter_H_window_1_5 <= 0;Inter_H_window_2_5 <= 0; + Inter_H_window_3_5 <= 0;Inter_H_window_4_5 <= 0;Inter_H_window_5_5 <= 0; + end + endcase + 4'b0100: //Right top blk4x4 + case (Inter_H_window_counter1) + 3'd4: + if (pos_FracL == `pos_p || pos_FracL == `pos_r) + begin + Inter_H_window_0_2 <= Inter_ref_04_03;Inter_H_window_1_2 <= Inter_ref_05_03; + Inter_H_window_2_2 <= Inter_ref_06_03;Inter_H_window_3_2 <= Inter_ref_07_03; + Inter_H_window_4_2 <= Inter_ref_08_03;Inter_H_window_5_2 <= Inter_ref_09_03; + + Inter_H_window_0_3 <= Inter_ref_04_04;Inter_H_window_1_3 <= Inter_ref_05_04; + Inter_H_window_2_3 <= Inter_ref_06_04;Inter_H_window_3_3 <= Inter_ref_07_04; + Inter_H_window_4_3 <= Inter_ref_08_04;Inter_H_window_5_3 <= Inter_ref_09_04; + + Inter_H_window_0_4 <= Inter_ref_04_05;Inter_H_window_1_4 <= Inter_ref_05_05; + Inter_H_window_2_4 <= Inter_ref_06_05;Inter_H_window_3_4 <= Inter_ref_07_05; + Inter_H_window_4_4 <= Inter_ref_08_05;Inter_H_window_5_4 <= Inter_ref_09_05; + + Inter_H_window_0_5 <= Inter_ref_04_06;Inter_H_window_1_5 <= Inter_ref_05_06; + Inter_H_window_2_5 <= Inter_ref_06_06;Inter_H_window_3_5 <= Inter_ref_07_06; + Inter_H_window_4_5 <= Inter_ref_08_06;Inter_H_window_5_5 <= Inter_ref_09_06; + end + else + begin + Inter_H_window_0_2 <= Inter_ref_04_02;Inter_H_window_1_2 <= Inter_ref_05_02; + Inter_H_window_2_2 <= Inter_ref_06_02;Inter_H_window_3_2 <= Inter_ref_07_02; + Inter_H_window_4_2 <= Inter_ref_08_02;Inter_H_window_5_2 <= Inter_ref_09_02; + + Inter_H_window_0_3 <= Inter_ref_04_03;Inter_H_window_1_3 <= Inter_ref_05_03; + Inter_H_window_2_3 <= Inter_ref_06_03;Inter_H_window_3_3 <= Inter_ref_07_03; + Inter_H_window_4_3 <= Inter_ref_08_03;Inter_H_window_5_3 <= Inter_ref_09_03; + + Inter_H_window_0_4 <= Inter_ref_04_04;Inter_H_window_1_4 <= Inter_ref_05_04; + Inter_H_window_2_4 <= Inter_ref_06_04;Inter_H_window_3_4 <= Inter_ref_07_04; + Inter_H_window_4_4 <= Inter_ref_08_04;Inter_H_window_5_4 <= Inter_ref_09_04; + + Inter_H_window_0_5 <= Inter_ref_04_05;Inter_H_window_1_5 <= Inter_ref_05_05; + Inter_H_window_2_5 <= Inter_ref_06_05;Inter_H_window_3_5 <= Inter_ref_07_05; + Inter_H_window_4_5 <= Inter_ref_08_05;Inter_H_window_5_5 <= Inter_ref_09_05; + end + 3'd3: + if (pos_FracL == `pos_p || pos_FracL == `pos_r) + begin + Inter_H_window_0_2 <= Inter_ref_05_03;Inter_H_window_1_2 <= Inter_ref_06_03; + Inter_H_window_2_2 <= Inter_ref_07_03;Inter_H_window_3_2 <= Inter_ref_08_03; + Inter_H_window_4_2 <= Inter_ref_09_03;Inter_H_window_5_2 <= Inter_ref_10_03; + + Inter_H_window_0_3 <= Inter_ref_05_04;Inter_H_window_1_3 <= Inter_ref_06_04; + Inter_H_window_2_3 <= Inter_ref_07_04;Inter_H_window_3_3 <= Inter_ref_08_04; + Inter_H_window_4_3 <= Inter_ref_09_04;Inter_H_window_5_3 <= Inter_ref_10_04; + + Inter_H_window_0_4 <= Inter_ref_05_05;Inter_H_window_1_4 <= Inter_ref_06_05; + Inter_H_window_2_4 <= Inter_ref_07_05;Inter_H_window_3_4 <= Inter_ref_08_05; + Inter_H_window_4_4 <= Inter_ref_09_05;Inter_H_window_5_4 <= Inter_ref_10_05; + + Inter_H_window_0_5 <= Inter_ref_05_06;Inter_H_window_1_5 <= Inter_ref_06_06; + Inter_H_window_2_5 <= Inter_ref_07_06;Inter_H_window_3_5 <= Inter_ref_08_06; + Inter_H_window_4_5 <= Inter_ref_09_06;Inter_H_window_5_5 <= Inter_ref_10_06; + end + else + begin + Inter_H_window_0_2 <= Inter_ref_05_02;Inter_H_window_1_2 <= Inter_ref_06_02; + Inter_H_window_2_2 <= Inter_ref_07_02;Inter_H_window_3_2 <= Inter_ref_08_02; + Inter_H_window_4_2 <= Inter_ref_09_02;Inter_H_window_5_2 <= Inter_ref_10_02; + + Inter_H_window_0_3 <= Inter_ref_05_03;Inter_H_window_1_3 <= Inter_ref_06_03; + Inter_H_window_2_3 <= Inter_ref_07_03;Inter_H_window_3_3 <= Inter_ref_08_03; + Inter_H_window_4_3 <= Inter_ref_09_03;Inter_H_window_5_3 <= Inter_ref_10_03; + + Inter_H_window_0_4 <= Inter_ref_05_04;Inter_H_window_1_4 <= Inter_ref_06_04; + Inter_H_window_2_4 <= Inter_ref_07_04;Inter_H_window_3_4 <= Inter_ref_08_04; + Inter_H_window_4_4 <= Inter_ref_09_04;Inter_H_window_5_4 <= Inter_ref_10_04; + + Inter_H_window_0_5 <= Inter_ref_05_05;Inter_H_window_1_5 <= Inter_ref_06_05; + Inter_H_window_2_5 <= Inter_ref_07_05;Inter_H_window_3_5 <= Inter_ref_08_05; + Inter_H_window_4_5 <= Inter_ref_09_05;Inter_H_window_5_5 <= Inter_ref_10_05; + end + 3'd2: + if (pos_FracL == `pos_p || pos_FracL == `pos_r) + begin + Inter_H_window_0_2 <= Inter_ref_06_03;Inter_H_window_1_2 <= Inter_ref_07_03; + Inter_H_window_2_2 <= Inter_ref_08_03;Inter_H_window_3_2 <= Inter_ref_09_03; + Inter_H_window_4_2 <= Inter_ref_10_03;Inter_H_window_5_2 <= Inter_ref_11_03; + + Inter_H_window_0_3 <= Inter_ref_06_04;Inter_H_window_1_3 <= Inter_ref_07_04; + Inter_H_window_2_3 <= Inter_ref_08_04;Inter_H_window_3_3 <= Inter_ref_09_04; + Inter_H_window_4_3 <= Inter_ref_10_04;Inter_H_window_5_3 <= Inter_ref_11_04; + + Inter_H_window_0_4 <= Inter_ref_06_05;Inter_H_window_1_4 <= Inter_ref_07_05; + Inter_H_window_2_4 <= Inter_ref_08_05;Inter_H_window_3_4 <= Inter_ref_09_05; + Inter_H_window_4_4 <= Inter_ref_10_05;Inter_H_window_5_4 <= Inter_ref_11_05; + + Inter_H_window_0_5 <= Inter_ref_06_06;Inter_H_window_1_5 <= Inter_ref_07_06; + Inter_H_window_2_5 <= Inter_ref_08_06;Inter_H_window_3_5 <= Inter_ref_09_06; + Inter_H_window_4_5 <= Inter_ref_10_06;Inter_H_window_5_5 <= Inter_ref_11_06; + end + else + begin + Inter_H_window_0_2 <= Inter_ref_06_02;Inter_H_window_1_2 <= Inter_ref_07_02; + Inter_H_window_2_2 <= Inter_ref_08_02;Inter_H_window_3_2 <= Inter_ref_09_02; + Inter_H_window_4_2 <= Inter_ref_10_02;Inter_H_window_5_2 <= Inter_ref_11_02; + + Inter_H_window_0_3 <= Inter_ref_06_03;Inter_H_window_1_3 <= Inter_ref_07_03; + Inter_H_window_2_3 <= Inter_ref_08_03;Inter_H_window_3_3 <= Inter_ref_09_03; + Inter_H_window_4_3 <= Inter_ref_10_03;Inter_H_window_5_3 <= Inter_ref_11_03; + + Inter_H_window_0_4 <= Inter_ref_06_04;Inter_H_window_1_4 <= Inter_ref_07_04; + Inter_H_window_2_4 <= Inter_ref_08_04;Inter_H_window_3_4 <= Inter_ref_09_04; + Inter_H_window_4_4 <= Inter_ref_10_04;Inter_H_window_5_4 <= Inter_ref_11_04; + + Inter_H_window_0_5 <= Inter_ref_06_05;Inter_H_window_1_5 <= Inter_ref_07_05; + Inter_H_window_2_5 <= Inter_ref_08_05;Inter_H_window_3_5 <= Inter_ref_09_05; + Inter_H_window_4_5 <= Inter_ref_10_05;Inter_H_window_5_5 <= Inter_ref_11_05; + end + 3'd1: + if (pos_FracL == `pos_p || pos_FracL == `pos_r) + begin + Inter_H_window_0_2 <= Inter_ref_07_03;Inter_H_window_1_2 <= Inter_ref_08_03; + Inter_H_window_2_2 <= Inter_ref_09_03;Inter_H_window_3_2 <= Inter_ref_10_03; + Inter_H_window_4_2 <= Inter_ref_11_03;Inter_H_window_5_2 <= Inter_ref_12_03; + + Inter_H_window_0_3 <= Inter_ref_07_04;Inter_H_window_1_3 <= Inter_ref_08_04; + Inter_H_window_2_3 <= Inter_ref_09_04;Inter_H_window_3_3 <= Inter_ref_10_04; + Inter_H_window_4_3 <= Inter_ref_11_04;Inter_H_window_5_3 <= Inter_ref_12_04; + + Inter_H_window_0_4 <= Inter_ref_07_05;Inter_H_window_1_4 <= Inter_ref_08_05; + Inter_H_window_2_4 <= Inter_ref_09_05;Inter_H_window_3_4 <= Inter_ref_10_05; + Inter_H_window_4_4 <= Inter_ref_11_05;Inter_H_window_5_4 <= Inter_ref_12_05; + + Inter_H_window_0_5 <= Inter_ref_07_06;Inter_H_window_1_5 <= Inter_ref_08_06; + Inter_H_window_2_5 <= Inter_ref_09_06;Inter_H_window_3_5 <= Inter_ref_10_06; + Inter_H_window_4_5 <= Inter_ref_11_06;Inter_H_window_5_5 <= Inter_ref_12_06; + end + else + begin + Inter_H_window_0_2 <= Inter_ref_07_02;Inter_H_window_1_2 <= Inter_ref_08_02; + Inter_H_window_2_2 <= Inter_ref_09_02;Inter_H_window_3_2 <= Inter_ref_10_02; + Inter_H_window_4_2 <= Inter_ref_11_02;Inter_H_window_5_2 <= Inter_ref_12_02; + + Inter_H_window_0_3 <= Inter_ref_07_03;Inter_H_window_1_3 <= Inter_ref_08_03; + Inter_H_window_2_3 <= Inter_ref_09_03;Inter_H_window_3_3 <= Inter_ref_10_03; + Inter_H_window_4_3 <= Inter_ref_11_03;Inter_H_window_5_3 <= Inter_ref_12_03; + + Inter_H_window_0_4 <= Inter_ref_07_04;Inter_H_window_1_4 <= Inter_ref_08_04; + Inter_H_window_2_4 <= Inter_ref_09_04;Inter_H_window_3_4 <= Inter_ref_10_04; + Inter_H_window_4_4 <= Inter_ref_11_04;Inter_H_window_5_4 <= Inter_ref_12_04; + + Inter_H_window_0_5 <= Inter_ref_07_05;Inter_H_window_1_5 <= Inter_ref_08_05; + Inter_H_window_2_5 <= Inter_ref_09_05;Inter_H_window_3_5 <= Inter_ref_10_05; + Inter_H_window_4_5 <= Inter_ref_11_05;Inter_H_window_5_5 <= Inter_ref_12_05; + end + default: + begin + Inter_H_window_0_2 <= 0;Inter_H_window_1_2 <= 0;Inter_H_window_2_2 <= 0; + Inter_H_window_3_2 <= 0;Inter_H_window_4_2 <= 0;Inter_H_window_5_2 <= 0; + + Inter_H_window_0_3 <= 0;Inter_H_window_1_3 <= 0;Inter_H_window_2_3 <= 0; + Inter_H_window_3_3 <= 0;Inter_H_window_4_3 <= 0;Inter_H_window_5_3 <= 0; + + Inter_H_window_0_4 <= 0;Inter_H_window_1_4 <= 0;Inter_H_window_2_4 <= 0; + Inter_H_window_3_4 <= 0;Inter_H_window_4_4 <= 0;Inter_H_window_5_4 <= 0; + + Inter_H_window_0_5 <= 0;Inter_H_window_1_5 <= 0;Inter_H_window_2_5 <= 0; + Inter_H_window_3_5 <= 0;Inter_H_window_4_5 <= 0;Inter_H_window_5_5 <= 0; + end + endcase + 4'b0010: //Left bottom blk4x4 + case (Inter_H_window_counter1) + 3'd4: + if (pos_FracL == `pos_p || pos_FracL == `pos_r) + begin + Inter_H_window_0_2 <= Inter_ref_00_07;Inter_H_window_1_2 <= Inter_ref_01_07; + Inter_H_window_2_2 <= Inter_ref_02_07;Inter_H_window_3_2 <= Inter_ref_03_07; + Inter_H_window_4_2 <= Inter_ref_04_07;Inter_H_window_5_2 <= Inter_ref_05_07; + + Inter_H_window_0_3 <= Inter_ref_00_08;Inter_H_window_1_3 <= Inter_ref_01_08; + Inter_H_window_2_3 <= Inter_ref_02_08;Inter_H_window_3_3 <= Inter_ref_03_08; + Inter_H_window_4_3 <= Inter_ref_04_08;Inter_H_window_5_3 <= Inter_ref_05_08; + + Inter_H_window_0_4 <= Inter_ref_00_09;Inter_H_window_1_4 <= Inter_ref_01_09; + Inter_H_window_2_4 <= Inter_ref_02_09;Inter_H_window_3_4 <= Inter_ref_03_09; + Inter_H_window_4_4 <= Inter_ref_04_09;Inter_H_window_5_4 <= Inter_ref_05_09; + + Inter_H_window_0_5 <= Inter_ref_00_10;Inter_H_window_1_5 <= Inter_ref_01_10; + Inter_H_window_2_5 <= Inter_ref_02_10;Inter_H_window_3_5 <= Inter_ref_03_10; + Inter_H_window_4_5 <= Inter_ref_04_10;Inter_H_window_5_5 <= Inter_ref_05_10; + end + else + begin + Inter_H_window_0_2 <= Inter_ref_00_06;Inter_H_window_1_2 <= Inter_ref_01_06; + Inter_H_window_2_2 <= Inter_ref_02_06;Inter_H_window_3_2 <= Inter_ref_03_06; + Inter_H_window_4_2 <= Inter_ref_04_06;Inter_H_window_5_2 <= Inter_ref_05_06; + + Inter_H_window_0_3 <= Inter_ref_00_07;Inter_H_window_1_3 <= Inter_ref_01_07; + Inter_H_window_2_3 <= Inter_ref_02_07;Inter_H_window_3_3 <= Inter_ref_03_07; + Inter_H_window_4_3 <= Inter_ref_04_07;Inter_H_window_5_3 <= Inter_ref_05_07; + + Inter_H_window_0_4 <= Inter_ref_00_08;Inter_H_window_1_4 <= Inter_ref_01_08; + Inter_H_window_2_4 <= Inter_ref_02_08;Inter_H_window_3_4 <= Inter_ref_03_08; + Inter_H_window_4_4 <= Inter_ref_04_08;Inter_H_window_5_4 <= Inter_ref_05_08; + + Inter_H_window_0_5 <= Inter_ref_00_09;Inter_H_window_1_5 <= Inter_ref_01_09; + Inter_H_window_2_5 <= Inter_ref_02_09;Inter_H_window_3_5 <= Inter_ref_03_09; + Inter_H_window_4_5 <= Inter_ref_04_09;Inter_H_window_5_5 <= Inter_ref_05_09; + end + 3'd3: + if (pos_FracL == `pos_p || pos_FracL == `pos_r) + begin + Inter_H_window_0_2 <= Inter_ref_01_07;Inter_H_window_1_2 <= Inter_ref_02_07; + Inter_H_window_2_2 <= Inter_ref_03_07;Inter_H_window_3_2 <= Inter_ref_04_07; + Inter_H_window_4_2 <= Inter_ref_05_07;Inter_H_window_5_2 <= Inter_ref_06_07; + + Inter_H_window_0_3 <= Inter_ref_01_08;Inter_H_window_1_3 <= Inter_ref_02_08; + Inter_H_window_2_3 <= Inter_ref_03_08;Inter_H_window_3_3 <= Inter_ref_04_08; + Inter_H_window_4_3 <= Inter_ref_05_08;Inter_H_window_5_3 <= Inter_ref_06_08; + + Inter_H_window_0_4 <= Inter_ref_01_09;Inter_H_window_1_4 <= Inter_ref_02_09; + Inter_H_window_2_4 <= Inter_ref_03_09;Inter_H_window_3_4 <= Inter_ref_04_09; + Inter_H_window_4_4 <= Inter_ref_05_09;Inter_H_window_5_4 <= Inter_ref_06_09; + + Inter_H_window_0_5 <= Inter_ref_01_10;Inter_H_window_1_5 <= Inter_ref_02_10; + Inter_H_window_2_5 <= Inter_ref_03_10;Inter_H_window_3_5 <= Inter_ref_04_10; + Inter_H_window_4_5 <= Inter_ref_05_10;Inter_H_window_5_5 <= Inter_ref_06_10; + end + else + begin + Inter_H_window_0_2 <= Inter_ref_01_06;Inter_H_window_1_2 <= Inter_ref_02_06; + Inter_H_window_2_2 <= Inter_ref_03_06;Inter_H_window_3_2 <= Inter_ref_04_06; + Inter_H_window_4_2 <= Inter_ref_05_06;Inter_H_window_5_2 <= Inter_ref_06_06; + + Inter_H_window_0_3 <= Inter_ref_01_07;Inter_H_window_1_3 <= Inter_ref_02_07; + Inter_H_window_2_3 <= Inter_ref_03_07;Inter_H_window_3_3 <= Inter_ref_04_07; + Inter_H_window_4_3 <= Inter_ref_05_07;Inter_H_window_5_3 <= Inter_ref_06_07; + + Inter_H_window_0_4 <= Inter_ref_01_08;Inter_H_window_1_4 <= Inter_ref_02_08; + Inter_H_window_2_4 <= Inter_ref_03_08;Inter_H_window_3_4 <= Inter_ref_04_08; + Inter_H_window_4_4 <= Inter_ref_05_08;Inter_H_window_5_4 <= Inter_ref_06_08; + + Inter_H_window_0_5 <= Inter_ref_01_09;Inter_H_window_1_5 <= Inter_ref_02_09; + Inter_H_window_2_5 <= Inter_ref_03_09;Inter_H_window_3_5 <= Inter_ref_04_09; + Inter_H_window_4_5 <= Inter_ref_05_09;Inter_H_window_5_5 <= Inter_ref_06_09; + end + 3'd2: + if (pos_FracL == `pos_p || pos_FracL == `pos_r) + begin + Inter_H_window_0_2 <= Inter_ref_02_07;Inter_H_window_1_2 <= Inter_ref_03_07; + Inter_H_window_2_2 <= Inter_ref_04_07;Inter_H_window_3_2 <= Inter_ref_05_07; + Inter_H_window_4_2 <= Inter_ref_06_07;Inter_H_window_5_2 <= Inter_ref_07_07; + + Inter_H_window_0_3 <= Inter_ref_02_08;Inter_H_window_1_3 <= Inter_ref_03_08; + Inter_H_window_2_3 <= Inter_ref_04_08;Inter_H_window_3_3 <= Inter_ref_05_08; + Inter_H_window_4_3 <= Inter_ref_06_08;Inter_H_window_5_3 <= Inter_ref_07_08; + + Inter_H_window_0_4 <= Inter_ref_02_09;Inter_H_window_1_4 <= Inter_ref_03_09; + Inter_H_window_2_4 <= Inter_ref_04_09;Inter_H_window_3_4 <= Inter_ref_05_09; + Inter_H_window_4_4 <= Inter_ref_06_09;Inter_H_window_5_4 <= Inter_ref_07_09; + + Inter_H_window_0_5 <= Inter_ref_02_10;Inter_H_window_1_5 <= Inter_ref_03_10; + Inter_H_window_2_5 <= Inter_ref_04_10;Inter_H_window_3_5 <= Inter_ref_05_10; + Inter_H_window_4_5 <= Inter_ref_06_10;Inter_H_window_5_5 <= Inter_ref_07_10; + end + else + begin + Inter_H_window_0_2 <= Inter_ref_02_06;Inter_H_window_1_2 <= Inter_ref_03_06; + Inter_H_window_2_2 <= Inter_ref_04_06;Inter_H_window_3_2 <= Inter_ref_05_06; + Inter_H_window_4_2 <= Inter_ref_06_06;Inter_H_window_5_2 <= Inter_ref_07_06; + + Inter_H_window_0_3 <= Inter_ref_02_07;Inter_H_window_1_3 <= Inter_ref_03_07; + Inter_H_window_2_3 <= Inter_ref_04_07;Inter_H_window_3_3 <= Inter_ref_05_07; + Inter_H_window_4_3 <= Inter_ref_06_07;Inter_H_window_5_3 <= Inter_ref_07_07; + + Inter_H_window_0_4 <= Inter_ref_02_08;Inter_H_window_1_4 <= Inter_ref_03_08; + Inter_H_window_2_4 <= Inter_ref_04_08;Inter_H_window_3_4 <= Inter_ref_05_08; + Inter_H_window_4_4 <= Inter_ref_06_08;Inter_H_window_5_4 <= Inter_ref_07_08; + + Inter_H_window_0_5 <= Inter_ref_02_09;Inter_H_window_1_5 <= Inter_ref_03_09; + Inter_H_window_2_5 <= Inter_ref_04_09;Inter_H_window_3_5 <= Inter_ref_05_09; + Inter_H_window_4_5 <= Inter_ref_06_09;Inter_H_window_5_5 <= Inter_ref_07_09; + end + 3'd1: + if (pos_FracL == `pos_p || pos_FracL == `pos_r) + begin + Inter_H_window_0_2 <= Inter_ref_03_07;Inter_H_window_1_2 <= Inter_ref_04_07; + Inter_H_window_2_2 <= Inter_ref_05_07;Inter_H_window_3_2 <= Inter_ref_06_07; + Inter_H_window_4_2 <= Inter_ref_07_07;Inter_H_window_5_2 <= Inter_ref_08_07; + + Inter_H_window_0_3 <= Inter_ref_03_08;Inter_H_window_1_3 <= Inter_ref_04_08; + Inter_H_window_2_3 <= Inter_ref_05_08;Inter_H_window_3_3 <= Inter_ref_06_08; + Inter_H_window_4_3 <= Inter_ref_07_08;Inter_H_window_5_3 <= Inter_ref_08_08; + + Inter_H_window_0_4 <= Inter_ref_03_09;Inter_H_window_1_4 <= Inter_ref_04_09; + Inter_H_window_2_4 <= Inter_ref_05_09;Inter_H_window_3_4 <= Inter_ref_06_09; + Inter_H_window_4_4 <= Inter_ref_07_09;Inter_H_window_5_4 <= Inter_ref_08_09; + + Inter_H_window_0_5 <= Inter_ref_03_10;Inter_H_window_1_5 <= Inter_ref_04_10; + Inter_H_window_2_5 <= Inter_ref_05_10;Inter_H_window_3_5 <= Inter_ref_06_10; + Inter_H_window_4_5 <= Inter_ref_07_10;Inter_H_window_5_5 <= Inter_ref_08_10; + end + else + begin + Inter_H_window_0_2 <= Inter_ref_03_06;Inter_H_window_1_2 <= Inter_ref_04_06; + Inter_H_window_2_2 <= Inter_ref_05_06;Inter_H_window_3_2 <= Inter_ref_06_06; + Inter_H_window_4_2 <= Inter_ref_07_06;Inter_H_window_5_2 <= Inter_ref_08_06; + + Inter_H_window_0_3 <= Inter_ref_03_07;Inter_H_window_1_3 <= Inter_ref_04_07; + Inter_H_window_2_3 <= Inter_ref_05_07;Inter_H_window_3_3 <= Inter_ref_06_07; + Inter_H_window_4_3 <= Inter_ref_07_07;Inter_H_window_5_3 <= Inter_ref_08_07; + + Inter_H_window_0_4 <= Inter_ref_03_08;Inter_H_window_1_4 <= Inter_ref_04_08; + Inter_H_window_2_4 <= Inter_ref_05_08;Inter_H_window_3_4 <= Inter_ref_06_08; + Inter_H_window_4_4 <= Inter_ref_07_08;Inter_H_window_5_4 <= Inter_ref_08_08; + + Inter_H_window_0_5 <= Inter_ref_03_09;Inter_H_window_1_5 <= Inter_ref_04_09; + Inter_H_window_2_5 <= Inter_ref_05_09;Inter_H_window_3_5 <= Inter_ref_06_09; + Inter_H_window_4_5 <= Inter_ref_07_09;Inter_H_window_5_5 <= Inter_ref_08_09; + end + default: + begin + Inter_H_window_0_2 <= 0;Inter_H_window_1_2 <= 0;Inter_H_window_2_2 <= 0; + Inter_H_window_3_2 <= 0;Inter_H_window_4_2 <= 0;Inter_H_window_5_2 <= 0; + + Inter_H_window_0_3 <= 0;Inter_H_window_1_3 <= 0;Inter_H_window_2_3 <= 0; + Inter_H_window_3_3 <= 0;Inter_H_window_4_3 <= 0;Inter_H_window_5_3 <= 0; + + Inter_H_window_0_4 <= 0;Inter_H_window_1_4 <= 0;Inter_H_window_2_4 <= 0; + Inter_H_window_3_4 <= 0;Inter_H_window_4_4 <= 0;Inter_H_window_5_4 <= 0; + + Inter_H_window_0_5 <= 0;Inter_H_window_1_5 <= 0;Inter_H_window_2_5 <= 0; + Inter_H_window_3_5 <= 0;Inter_H_window_4_5 <= 0;Inter_H_window_5_5 <= 0; + end + endcase + 4'b0001: //Right bottom blk4x4 + case (Inter_H_window_counter1) + 3'd4: + if (pos_FracL == `pos_p || pos_FracL == `pos_r) + begin + Inter_H_window_0_2 <= Inter_ref_04_07;Inter_H_window_1_2 <= Inter_ref_05_07; + Inter_H_window_2_2 <= Inter_ref_06_07;Inter_H_window_3_2 <= Inter_ref_07_07; + Inter_H_window_4_2 <= Inter_ref_08_07;Inter_H_window_5_2 <= Inter_ref_09_07; + + Inter_H_window_0_3 <= Inter_ref_04_08;Inter_H_window_1_3 <= Inter_ref_05_08; + Inter_H_window_2_3 <= Inter_ref_06_08;Inter_H_window_3_3 <= Inter_ref_07_08; + Inter_H_window_4_3 <= Inter_ref_08_08;Inter_H_window_5_3 <= Inter_ref_09_08; + + Inter_H_window_0_4 <= Inter_ref_04_09;Inter_H_window_1_4 <= Inter_ref_05_09; + Inter_H_window_2_4 <= Inter_ref_06_09;Inter_H_window_3_4 <= Inter_ref_07_09; + Inter_H_window_4_4 <= Inter_ref_08_09;Inter_H_window_5_4 <= Inter_ref_09_09; + + Inter_H_window_0_5 <= Inter_ref_04_10;Inter_H_window_1_5 <= Inter_ref_05_10; + Inter_H_window_2_5 <= Inter_ref_06_10;Inter_H_window_3_5 <= Inter_ref_07_10; + Inter_H_window_4_5 <= Inter_ref_08_10;Inter_H_window_5_5 <= Inter_ref_09_10; + end + else + begin + Inter_H_window_0_2 <= Inter_ref_04_06;Inter_H_window_1_2 <= Inter_ref_05_06; + Inter_H_window_2_2 <= Inter_ref_06_06;Inter_H_window_3_2 <= Inter_ref_07_06; + Inter_H_window_4_2 <= Inter_ref_08_06;Inter_H_window_5_2 <= Inter_ref_09_06; + + Inter_H_window_0_3 <= Inter_ref_04_07;Inter_H_window_1_3 <= Inter_ref_05_07; + Inter_H_window_2_3 <= Inter_ref_06_07;Inter_H_window_3_3 <= Inter_ref_07_07; + Inter_H_window_4_3 <= Inter_ref_08_07;Inter_H_window_5_3 <= Inter_ref_09_07; + + Inter_H_window_0_4 <= Inter_ref_04_08;Inter_H_window_1_4 <= Inter_ref_05_08; + Inter_H_window_2_4 <= Inter_ref_06_08;Inter_H_window_3_4 <= Inter_ref_07_08; + Inter_H_window_4_4 <= Inter_ref_08_08;Inter_H_window_5_4 <= Inter_ref_09_08; + + Inter_H_window_0_5 <= Inter_ref_04_09;Inter_H_window_1_5 <= Inter_ref_05_09; + Inter_H_window_2_5 <= Inter_ref_06_09;Inter_H_window_3_5 <= Inter_ref_07_09; + Inter_H_window_4_5 <= Inter_ref_08_09;Inter_H_window_5_5 <= Inter_ref_09_09; + end + 3'd3: + if (pos_FracL == `pos_p || pos_FracL == `pos_r) + begin + Inter_H_window_0_2 <= Inter_ref_05_07;Inter_H_window_1_2 <= Inter_ref_06_07; + Inter_H_window_2_2 <= Inter_ref_07_07;Inter_H_window_3_2 <= Inter_ref_08_07; + Inter_H_window_4_2 <= Inter_ref_09_07;Inter_H_window_5_2 <= Inter_ref_10_07; + + Inter_H_window_0_3 <= Inter_ref_05_08;Inter_H_window_1_3 <= Inter_ref_06_08; + Inter_H_window_2_3 <= Inter_ref_07_08;Inter_H_window_3_3 <= Inter_ref_08_08; + Inter_H_window_4_3 <= Inter_ref_09_08;Inter_H_window_5_3 <= Inter_ref_10_08; + + Inter_H_window_0_4 <= Inter_ref_05_09;Inter_H_window_1_4 <= Inter_ref_06_09; + Inter_H_window_2_4 <= Inter_ref_07_09;Inter_H_window_3_4 <= Inter_ref_08_09; + Inter_H_window_4_4 <= Inter_ref_09_09;Inter_H_window_5_4 <= Inter_ref_10_09; + + Inter_H_window_0_5 <= Inter_ref_05_10;Inter_H_window_1_5 <= Inter_ref_06_10; + Inter_H_window_2_5 <= Inter_ref_07_10;Inter_H_window_3_5 <= Inter_ref_08_10; + Inter_H_window_4_5 <= Inter_ref_09_10;Inter_H_window_5_5 <= Inter_ref_10_10; + end + else + begin + Inter_H_window_0_2 <= Inter_ref_05_06;Inter_H_window_1_2 <= Inter_ref_06_06; + Inter_H_window_2_2 <= Inter_ref_07_06;Inter_H_window_3_2 <= Inter_ref_08_06; + Inter_H_window_4_2 <= Inter_ref_09_06;Inter_H_window_5_2 <= Inter_ref_10_06; + + Inter_H_window_0_3 <= Inter_ref_05_07;Inter_H_window_1_3 <= Inter_ref_06_07; + Inter_H_window_2_3 <= Inter_ref_07_07;Inter_H_window_3_3 <= Inter_ref_08_07; + Inter_H_window_4_3 <= Inter_ref_09_07;Inter_H_window_5_3 <= Inter_ref_10_07; + + Inter_H_window_0_4 <= Inter_ref_05_08;Inter_H_window_1_4 <= Inter_ref_06_08; + Inter_H_window_2_4 <= Inter_ref_07_08;Inter_H_window_3_4 <= Inter_ref_08_08; + Inter_H_window_4_4 <= Inter_ref_09_08;Inter_H_window_5_4 <= Inter_ref_10_08; + + Inter_H_window_0_5 <= Inter_ref_05_09;Inter_H_window_1_5 <= Inter_ref_06_09; + Inter_H_window_2_5 <= Inter_ref_07_09;Inter_H_window_3_5 <= Inter_ref_08_09; + Inter_H_window_4_5 <= Inter_ref_09_09;Inter_H_window_5_5 <= Inter_ref_10_09; + end + 3'd2: + if (pos_FracL == `pos_p || pos_FracL == `pos_r) + begin + Inter_H_window_0_2 <= Inter_ref_06_07;Inter_H_window_1_2 <= Inter_ref_07_07; + Inter_H_window_2_2 <= Inter_ref_08_07;Inter_H_window_3_2 <= Inter_ref_09_07; + Inter_H_window_4_2 <= Inter_ref_10_07;Inter_H_window_5_2 <= Inter_ref_11_07; + + Inter_H_window_0_3 <= Inter_ref_06_08;Inter_H_window_1_3 <= Inter_ref_07_08; + Inter_H_window_2_3 <= Inter_ref_08_08;Inter_H_window_3_3 <= Inter_ref_09_08; + Inter_H_window_4_3 <= Inter_ref_10_08;Inter_H_window_5_3 <= Inter_ref_11_08; + + Inter_H_window_0_4 <= Inter_ref_06_09;Inter_H_window_1_4 <= Inter_ref_07_09; + Inter_H_window_2_4 <= Inter_ref_08_09;Inter_H_window_3_4 <= Inter_ref_09_09; + Inter_H_window_4_4 <= Inter_ref_10_09;Inter_H_window_5_4 <= Inter_ref_11_09; + + Inter_H_window_0_5 <= Inter_ref_06_10;Inter_H_window_1_5 <= Inter_ref_07_10; + Inter_H_window_2_5 <= Inter_ref_08_10;Inter_H_window_3_5 <= Inter_ref_09_10; + Inter_H_window_4_5 <= Inter_ref_10_10;Inter_H_window_5_5 <= Inter_ref_11_10; + end + else + begin + Inter_H_window_0_2 <= Inter_ref_06_06;Inter_H_window_1_2 <= Inter_ref_07_06; + Inter_H_window_2_2 <= Inter_ref_08_06;Inter_H_window_3_2 <= Inter_ref_09_06; + Inter_H_window_4_2 <= Inter_ref_10_06;Inter_H_window_5_2 <= Inter_ref_11_06; + + Inter_H_window_0_3 <= Inter_ref_06_07;Inter_H_window_1_3 <= Inter_ref_07_07; + Inter_H_window_2_3 <= Inter_ref_08_07;Inter_H_window_3_3 <= Inter_ref_09_07; + Inter_H_window_4_3 <= Inter_ref_10_07;Inter_H_window_5_3 <= Inter_ref_11_07; + + Inter_H_window_0_4 <= Inter_ref_06_08;Inter_H_window_1_4 <= Inter_ref_07_08; + Inter_H_window_2_4 <= Inter_ref_08_08;Inter_H_window_3_4 <= Inter_ref_09_08; + Inter_H_window_4_4 <= Inter_ref_10_08;Inter_H_window_5_4 <= Inter_ref_11_08; + + Inter_H_window_0_5 <= Inter_ref_06_09;Inter_H_window_1_5 <= Inter_ref_07_09; + Inter_H_window_2_5 <= Inter_ref_08_09;Inter_H_window_3_5 <= Inter_ref_09_09; + Inter_H_window_4_5 <= Inter_ref_10_09;Inter_H_window_5_5 <= Inter_ref_11_09; + end + 3'd1: + if (pos_FracL == `pos_p || pos_FracL == `pos_r) + begin + Inter_H_window_0_2 <= Inter_ref_07_07;Inter_H_window_1_2 <= Inter_ref_08_07; + Inter_H_window_2_2 <= Inter_ref_09_07;Inter_H_window_3_2 <= Inter_ref_10_07; + Inter_H_window_4_2 <= Inter_ref_11_07;Inter_H_window_5_2 <= Inter_ref_12_07; + + Inter_H_window_0_3 <= Inter_ref_07_08;Inter_H_window_1_3 <= Inter_ref_08_08; + Inter_H_window_2_3 <= Inter_ref_09_08;Inter_H_window_3_3 <= Inter_ref_10_08; + Inter_H_window_4_3 <= Inter_ref_11_08;Inter_H_window_5_3 <= Inter_ref_12_08; + + Inter_H_window_0_4 <= Inter_ref_07_09;Inter_H_window_1_4 <= Inter_ref_08_09; + Inter_H_window_2_4 <= Inter_ref_09_09;Inter_H_window_3_4 <= Inter_ref_10_09; + Inter_H_window_4_4 <= Inter_ref_11_09;Inter_H_window_5_4 <= Inter_ref_12_09; + + Inter_H_window_0_5 <= Inter_ref_07_10;Inter_H_window_1_5 <= Inter_ref_08_10; + Inter_H_window_2_5 <= Inter_ref_09_10;Inter_H_window_3_5 <= Inter_ref_10_10; + Inter_H_window_4_5 <= Inter_ref_11_10;Inter_H_window_5_5 <= Inter_ref_12_10; + end + else + begin + Inter_H_window_0_2 <= Inter_ref_07_06;Inter_H_window_1_2 <= Inter_ref_08_06; + Inter_H_window_2_2 <= Inter_ref_09_06;Inter_H_window_3_2 <= Inter_ref_10_06; + Inter_H_window_4_2 <= Inter_ref_11_06;Inter_H_window_5_2 <= Inter_ref_12_06; + + Inter_H_window_0_3 <= Inter_ref_07_07;Inter_H_window_1_3 <= Inter_ref_08_07; + Inter_H_window_2_3 <= Inter_ref_09_07;Inter_H_window_3_3 <= Inter_ref_10_07; + Inter_H_window_4_3 <= Inter_ref_11_07;Inter_H_window_5_3 <= Inter_ref_12_07; + + Inter_H_window_0_4 <= Inter_ref_07_08;Inter_H_window_1_4 <= Inter_ref_08_08; + Inter_H_window_2_4 <= Inter_ref_09_08;Inter_H_window_3_4 <= Inter_ref_10_08; + Inter_H_window_4_4 <= Inter_ref_11_08;Inter_H_window_5_4 <= Inter_ref_12_08; + + Inter_H_window_0_5 <= Inter_ref_07_09;Inter_H_window_1_5 <= Inter_ref_08_09; + Inter_H_window_2_5 <= Inter_ref_09_09;Inter_H_window_3_5 <= Inter_ref_10_09; + Inter_H_window_4_5 <= Inter_ref_11_09;Inter_H_window_5_5 <= Inter_ref_12_09; + end + default: + begin + Inter_H_window_0_2 <= 0;Inter_H_window_1_2 <= 0;Inter_H_window_2_2 <= 0; + Inter_H_window_3_2 <= 0;Inter_H_window_4_2 <= 0;Inter_H_window_5_2 <= 0; + + Inter_H_window_0_3 <= 0;Inter_H_window_1_3 <= 0;Inter_H_window_2_3 <= 0; + Inter_H_window_3_3 <= 0;Inter_H_window_4_3 <= 0;Inter_H_window_5_3 <= 0; + + Inter_H_window_0_4 <= 0;Inter_H_window_1_4 <= 0;Inter_H_window_2_4 <= 0; + Inter_H_window_3_4 <= 0;Inter_H_window_4_4 <= 0;Inter_H_window_5_4 <= 0; + + Inter_H_window_0_5 <= 0;Inter_H_window_1_5 <= 0;Inter_H_window_2_5 <= 0; + Inter_H_window_3_5 <= 0;Inter_H_window_4_5 <= 0;Inter_H_window_5_5 <= 0; + end + endcase + default: + begin + Inter_H_window_0_2 <= 0;Inter_H_window_1_2 <= 0;Inter_H_window_2_2 <= 0; + Inter_H_window_3_2 <= 0;Inter_H_window_4_2 <= 0;Inter_H_window_5_2 <= 0; + + Inter_H_window_0_3 <= 0;Inter_H_window_1_3 <= 0;Inter_H_window_2_3 <= 0; + Inter_H_window_3_3 <= 0;Inter_H_window_4_3 <= 0;Inter_H_window_5_3 <= 0; + + Inter_H_window_0_4 <= 0;Inter_H_window_1_4 <= 0;Inter_H_window_2_4 <= 0; + Inter_H_window_3_4 <= 0;Inter_H_window_4_4 <= 0;Inter_H_window_5_4 <= 0; + + Inter_H_window_0_5 <= 0;Inter_H_window_1_5 <= 0;Inter_H_window_2_5 <= 0; + Inter_H_window_3_5 <= 0;Inter_H_window_4_5 <= 0;Inter_H_window_5_5 <= 0; + end + endcase + + //Inter_V_window_counter:for Inter_V_window_0 ~ Inter_V_window_8 + reg [2:0] Inter_V_window_counter; + always @ (pos_FracL or blk4x4_inter_calculate_counter) + if (((pos_FracL == `pos_h || pos_FracL == `pos_d || pos_FracL == `pos_n || pos_FracL == `pos_e || pos_FracL == `pos_g + || pos_FracL == `pos_p || pos_FracL == `pos_r) && blk4x4_inter_calculate_counter == 4'd4) || + ((pos_FracL == `pos_i || pos_FracL == `pos_k) && blk4x4_inter_calculate_counter == 4'd8)) + Inter_V_window_counter <= 3'd4; + else if (((pos_FracL == `pos_h || pos_FracL == `pos_d || pos_FracL == `pos_n || pos_FracL == `pos_e || pos_FracL == `pos_g + || pos_FracL == `pos_p || pos_FracL == `pos_r) && blk4x4_inter_calculate_counter == 4'd3) || + ((pos_FracL == `pos_i || pos_FracL == `pos_k) && blk4x4_inter_calculate_counter == 4'd6)) + Inter_V_window_counter <= 3'd3; + else if (((pos_FracL == `pos_h || pos_FracL == `pos_d || pos_FracL == `pos_n || pos_FracL == `pos_e || pos_FracL == `pos_g + || pos_FracL == `pos_p || pos_FracL == `pos_r) && blk4x4_inter_calculate_counter == 4'd2) || + ((pos_FracL == `pos_i || pos_FracL == `pos_k) && blk4x4_inter_calculate_counter == 4'd4)) + Inter_V_window_counter <= 3'd2; + else if (((pos_FracL == `pos_h || pos_FracL == `pos_d || pos_FracL == `pos_n || pos_FracL == `pos_e || pos_FracL == `pos_g + || pos_FracL == `pos_p || pos_FracL == `pos_r) && blk4x4_inter_calculate_counter == 4'd1) || + ((pos_FracL == `pos_i || pos_FracL == `pos_k) && blk4x4_inter_calculate_counter == 4'd2)) + Inter_V_window_counter <= 3'd1; + else + Inter_V_window_counter <= 0; + + //Inter_V_window_0 ~ Inter_V_window_8 + always @ (Is_blk4x4_0 or Is_blk4x4_1 or Is_blk4x4_2 or Is_blk4x4_3 or pos_FracL or Inter_V_window_counter + or Inter_ref_02_00 or Inter_ref_02_01 or Inter_ref_02_02 or Inter_ref_02_03 or Inter_ref_02_04 + or Inter_ref_02_05 or Inter_ref_02_06 or Inter_ref_02_07 or Inter_ref_02_08 or Inter_ref_02_09 + or Inter_ref_02_10 or Inter_ref_02_11 or Inter_ref_02_12 + + or Inter_ref_03_00 or Inter_ref_03_01 or Inter_ref_03_02 or Inter_ref_03_03 or Inter_ref_03_04 + or Inter_ref_03_05 or Inter_ref_03_06 or Inter_ref_03_07 or Inter_ref_03_08 or Inter_ref_03_09 + or Inter_ref_03_10 or Inter_ref_03_11 or Inter_ref_03_12 + + or Inter_ref_04_00 or Inter_ref_04_01 or Inter_ref_04_02 or Inter_ref_04_03 or Inter_ref_04_04 + or Inter_ref_04_05 or Inter_ref_04_06 or Inter_ref_04_07 or Inter_ref_04_08 or Inter_ref_04_09 + or Inter_ref_04_10 or Inter_ref_04_11 or Inter_ref_04_12 + + or Inter_ref_05_00 or Inter_ref_05_01 or Inter_ref_05_02 or Inter_ref_05_03 or Inter_ref_05_04 + or Inter_ref_05_05 or Inter_ref_05_06 or Inter_ref_05_07 or Inter_ref_05_08 or Inter_ref_05_09 + or Inter_ref_05_10 or Inter_ref_05_11 or Inter_ref_05_12 + + or Inter_ref_06_00 or Inter_ref_06_01 or Inter_ref_06_02 or Inter_ref_06_03 or Inter_ref_06_04 + or Inter_ref_06_05 or Inter_ref_06_06 or Inter_ref_06_07 or Inter_ref_06_08 or Inter_ref_06_09 + or Inter_ref_06_10 or Inter_ref_06_11 or Inter_ref_06_12 + + or Inter_ref_07_00 or Inter_ref_07_01 or Inter_ref_07_02 or Inter_ref_07_03 or Inter_ref_07_04 + or Inter_ref_07_05 or Inter_ref_07_06 or Inter_ref_07_07 or Inter_ref_07_08 or Inter_ref_07_09 + or Inter_ref_07_10 or Inter_ref_07_11 or Inter_ref_07_12 + + or Inter_ref_08_00 or Inter_ref_08_01 or Inter_ref_08_02 or Inter_ref_08_03 or Inter_ref_08_04 + or Inter_ref_08_05 or Inter_ref_08_06 or Inter_ref_08_07 or Inter_ref_08_08 or Inter_ref_08_09 + or Inter_ref_08_10 or Inter_ref_08_11 or Inter_ref_08_12 + + or Inter_ref_09_00 or Inter_ref_09_01 or Inter_ref_09_02 or Inter_ref_09_03 or Inter_ref_09_04 + or Inter_ref_09_05 or Inter_ref_09_06 or Inter_ref_09_07 or Inter_ref_09_08 or Inter_ref_09_09 + or Inter_ref_09_10 or Inter_ref_09_11 or Inter_ref_09_12 + + or Inter_ref_10_00 or Inter_ref_10_01 or Inter_ref_10_02 or Inter_ref_10_03 or Inter_ref_10_04 + or Inter_ref_10_05 or Inter_ref_10_06 or Inter_ref_10_07 or Inter_ref_10_08 or Inter_ref_10_09 + or Inter_ref_10_10 or Inter_ref_10_11 or Inter_ref_10_12 + ) + case ({Is_blk4x4_0,Is_blk4x4_1,Is_blk4x4_2,Is_blk4x4_3}) + 4'b1000: //Left top blk4x4 + case (Inter_V_window_counter) + 3'd4: + if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) + begin + Inter_V_window_0 <= Inter_ref_03_00;Inter_V_window_1 <= Inter_ref_03_01; + Inter_V_window_2 <= Inter_ref_03_02;Inter_V_window_3 <= Inter_ref_03_03; + Inter_V_window_4 <= Inter_ref_03_04;Inter_V_window_5 <= Inter_ref_03_05; + Inter_V_window_6 <= Inter_ref_03_06;Inter_V_window_7 <= Inter_ref_03_07; + Inter_V_window_8 <= Inter_ref_03_08; + end + else + begin + Inter_V_window_0 <= Inter_ref_02_00;Inter_V_window_1 <= Inter_ref_02_01; + Inter_V_window_2 <= Inter_ref_02_02;Inter_V_window_3 <= Inter_ref_02_03; + Inter_V_window_4 <= Inter_ref_02_04;Inter_V_window_5 <= Inter_ref_02_05; + Inter_V_window_6 <= Inter_ref_02_06;Inter_V_window_7 <= Inter_ref_02_07; + Inter_V_window_8 <= Inter_ref_02_08; + end + 3'd3: + if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) + begin + Inter_V_window_0 <= Inter_ref_04_00;Inter_V_window_1 <= Inter_ref_04_01; + Inter_V_window_2 <= Inter_ref_04_02;Inter_V_window_3 <= Inter_ref_04_03; + Inter_V_window_4 <= Inter_ref_04_04;Inter_V_window_5 <= Inter_ref_04_05; + Inter_V_window_6 <= Inter_ref_04_06;Inter_V_window_7 <= Inter_ref_04_07; + Inter_V_window_8 <= Inter_ref_04_08; + end + else + begin + Inter_V_window_0 <= Inter_ref_03_00;Inter_V_window_1 <= Inter_ref_03_01; + Inter_V_window_2 <= Inter_ref_03_02;Inter_V_window_3 <= Inter_ref_03_03; + Inter_V_window_4 <= Inter_ref_03_04;Inter_V_window_5 <= Inter_ref_03_05; + Inter_V_window_6 <= Inter_ref_03_06;Inter_V_window_7 <= Inter_ref_03_07; + Inter_V_window_8 <= Inter_ref_03_08; + end + 3'd2: + if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) + begin + Inter_V_window_0 <= Inter_ref_05_00;Inter_V_window_1 <= Inter_ref_05_01; + Inter_V_window_2 <= Inter_ref_05_02;Inter_V_window_3 <= Inter_ref_05_03; + Inter_V_window_4 <= Inter_ref_05_04;Inter_V_window_5 <= Inter_ref_05_05; + Inter_V_window_6 <= Inter_ref_05_06;Inter_V_window_7 <= Inter_ref_05_07; + Inter_V_window_8 <= Inter_ref_05_08; + end + else + begin + Inter_V_window_0 <= Inter_ref_04_00;Inter_V_window_1 <= Inter_ref_04_01; + Inter_V_window_2 <= Inter_ref_04_02;Inter_V_window_3 <= Inter_ref_04_03; + Inter_V_window_4 <= Inter_ref_04_04;Inter_V_window_5 <= Inter_ref_04_05; + Inter_V_window_6 <= Inter_ref_04_06;Inter_V_window_7 <= Inter_ref_04_07; + Inter_V_window_8 <= Inter_ref_04_08; + end + 3'd1: + if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) + begin + Inter_V_window_0 <= Inter_ref_06_00;Inter_V_window_1 <= Inter_ref_06_01; + Inter_V_window_2 <= Inter_ref_06_02;Inter_V_window_3 <= Inter_ref_06_03; + Inter_V_window_4 <= Inter_ref_06_04;Inter_V_window_5 <= Inter_ref_06_05; + Inter_V_window_6 <= Inter_ref_06_06;Inter_V_window_7 <= Inter_ref_06_07; + Inter_V_window_8 <= Inter_ref_06_08; + end + else + begin + Inter_V_window_0 <= Inter_ref_05_00;Inter_V_window_1 <= Inter_ref_05_01; + Inter_V_window_2 <= Inter_ref_05_02;Inter_V_window_3 <= Inter_ref_05_03; + Inter_V_window_4 <= Inter_ref_05_04;Inter_V_window_5 <= Inter_ref_05_05; + Inter_V_window_6 <= Inter_ref_05_06;Inter_V_window_7 <= Inter_ref_05_07; + Inter_V_window_8 <= Inter_ref_05_08; + end + default: + begin + Inter_V_window_0 <= 0;Inter_V_window_1 <= 0;Inter_V_window_2 <= 0; + Inter_V_window_3 <= 0;Inter_V_window_4 <= 0;Inter_V_window_5 <= 0; + Inter_V_window_6 <= 0;Inter_V_window_7 <= 0;Inter_V_window_8 <= 0; + end + endcase + 4'b0100: //Right top blk4x4 + case (Inter_V_window_counter) + 3'd4: + if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) + begin + Inter_V_window_0 <= Inter_ref_07_00;Inter_V_window_1 <= Inter_ref_07_01; + Inter_V_window_2 <= Inter_ref_07_02;Inter_V_window_3 <= Inter_ref_07_03; + Inter_V_window_4 <= Inter_ref_07_04;Inter_V_window_5 <= Inter_ref_07_05; + Inter_V_window_6 <= Inter_ref_07_06;Inter_V_window_7 <= Inter_ref_07_07; + Inter_V_window_8 <= Inter_ref_07_08; + end + else + begin + Inter_V_window_0 <= Inter_ref_06_00;Inter_V_window_1 <= Inter_ref_06_01; + Inter_V_window_2 <= Inter_ref_06_02;Inter_V_window_3 <= Inter_ref_06_03; + Inter_V_window_4 <= Inter_ref_06_04;Inter_V_window_5 <= Inter_ref_06_05; + Inter_V_window_6 <= Inter_ref_06_06;Inter_V_window_7 <= Inter_ref_06_07; + Inter_V_window_8 <= Inter_ref_06_08; + end + 3'd3: + if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) + begin + Inter_V_window_0 <= Inter_ref_08_00;Inter_V_window_1 <= Inter_ref_08_01; + Inter_V_window_2 <= Inter_ref_08_02;Inter_V_window_3 <= Inter_ref_08_03; + Inter_V_window_4 <= Inter_ref_08_04;Inter_V_window_5 <= Inter_ref_08_05; + Inter_V_window_6 <= Inter_ref_08_06;Inter_V_window_7 <= Inter_ref_08_07; + Inter_V_window_8 <= Inter_ref_08_08; + end + else + begin + Inter_V_window_0 <= Inter_ref_07_00;Inter_V_window_1 <= Inter_ref_07_01; + Inter_V_window_2 <= Inter_ref_07_02;Inter_V_window_3 <= Inter_ref_07_03; + Inter_V_window_4 <= Inter_ref_07_04;Inter_V_window_5 <= Inter_ref_07_05; + Inter_V_window_6 <= Inter_ref_07_06;Inter_V_window_7 <= Inter_ref_07_07; + Inter_V_window_8 <= Inter_ref_07_08; + end + 3'd2: + if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) + begin + Inter_V_window_0 <= Inter_ref_09_00;Inter_V_window_1 <= Inter_ref_09_01; + Inter_V_window_2 <= Inter_ref_09_02;Inter_V_window_3 <= Inter_ref_09_03; + Inter_V_window_4 <= Inter_ref_09_04;Inter_V_window_5 <= Inter_ref_09_05; + Inter_V_window_6 <= Inter_ref_09_06;Inter_V_window_7 <= Inter_ref_09_07; + Inter_V_window_8 <= Inter_ref_09_08; + end + else + begin + Inter_V_window_0 <= Inter_ref_08_00;Inter_V_window_1 <= Inter_ref_08_01; + Inter_V_window_2 <= Inter_ref_08_02;Inter_V_window_3 <= Inter_ref_08_03; + Inter_V_window_4 <= Inter_ref_08_04;Inter_V_window_5 <= Inter_ref_08_05; + Inter_V_window_6 <= Inter_ref_08_06;Inter_V_window_7 <= Inter_ref_08_07; + Inter_V_window_8 <= Inter_ref_08_08; + end + 3'd1: + if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) + begin + Inter_V_window_0 <= Inter_ref_10_00;Inter_V_window_1 <= Inter_ref_10_01; + Inter_V_window_2 <= Inter_ref_10_02;Inter_V_window_3 <= Inter_ref_10_03; + Inter_V_window_4 <= Inter_ref_10_04;Inter_V_window_5 <= Inter_ref_10_05; + Inter_V_window_6 <= Inter_ref_10_06;Inter_V_window_7 <= Inter_ref_10_07; + Inter_V_window_8 <= Inter_ref_10_08; + end + else + begin + Inter_V_window_0 <= Inter_ref_09_00;Inter_V_window_1 <= Inter_ref_09_01; + Inter_V_window_2 <= Inter_ref_09_02;Inter_V_window_3 <= Inter_ref_09_03; + Inter_V_window_4 <= Inter_ref_09_04;Inter_V_window_5 <= Inter_ref_09_05; + Inter_V_window_6 <= Inter_ref_09_06;Inter_V_window_7 <= Inter_ref_09_07; + Inter_V_window_8 <= Inter_ref_09_08; + end + default: + begin + Inter_V_window_0 <= 0;Inter_V_window_1 <= 0;Inter_V_window_2 <= 0; + Inter_V_window_3 <= 0;Inter_V_window_4 <= 0;Inter_V_window_5 <= 0; + Inter_V_window_6 <= 0;Inter_V_window_7 <= 0;Inter_V_window_8 <= 0; + end + endcase + 4'b0010: //Left bottom blk4x4 + case (Inter_V_window_counter) + 3'd4: + if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) + begin + Inter_V_window_0 <= Inter_ref_03_04;Inter_V_window_1 <= Inter_ref_03_05; + Inter_V_window_2 <= Inter_ref_03_06;Inter_V_window_3 <= Inter_ref_03_07; + Inter_V_window_4 <= Inter_ref_03_08;Inter_V_window_5 <= Inter_ref_03_09; + Inter_V_window_6 <= Inter_ref_03_10;Inter_V_window_7 <= Inter_ref_03_11; + Inter_V_window_8 <= Inter_ref_03_12; + end + else + begin + Inter_V_window_0 <= Inter_ref_02_04;Inter_V_window_1 <= Inter_ref_02_05; + Inter_V_window_2 <= Inter_ref_02_06;Inter_V_window_3 <= Inter_ref_02_07; + Inter_V_window_4 <= Inter_ref_02_08;Inter_V_window_5 <= Inter_ref_02_09; + Inter_V_window_6 <= Inter_ref_02_10;Inter_V_window_7 <= Inter_ref_02_11; + Inter_V_window_8 <= Inter_ref_02_12; + end + 3'd3: + if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) + begin + Inter_V_window_0 <= Inter_ref_04_04;Inter_V_window_1 <= Inter_ref_04_05; + Inter_V_window_2 <= Inter_ref_04_06;Inter_V_window_3 <= Inter_ref_04_07; + Inter_V_window_4 <= Inter_ref_04_08;Inter_V_window_5 <= Inter_ref_04_09; + Inter_V_window_6 <= Inter_ref_04_10;Inter_V_window_7 <= Inter_ref_04_11; + Inter_V_window_8 <= Inter_ref_04_12; + end + else + begin + Inter_V_window_0 <= Inter_ref_03_04;Inter_V_window_1 <= Inter_ref_03_05; + Inter_V_window_2 <= Inter_ref_03_06;Inter_V_window_3 <= Inter_ref_03_07; + Inter_V_window_4 <= Inter_ref_03_08;Inter_V_window_5 <= Inter_ref_03_09; + Inter_V_window_6 <= Inter_ref_03_10;Inter_V_window_7 <= Inter_ref_03_11; + Inter_V_window_8 <= Inter_ref_03_12; + end + 3'd2: + if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) + begin + Inter_V_window_0 <= Inter_ref_05_04;Inter_V_window_1 <= Inter_ref_05_05; + Inter_V_window_2 <= Inter_ref_05_06;Inter_V_window_3 <= Inter_ref_05_07; + Inter_V_window_4 <= Inter_ref_05_08;Inter_V_window_5 <= Inter_ref_05_09; + Inter_V_window_6 <= Inter_ref_05_10;Inter_V_window_7 <= Inter_ref_05_11; + Inter_V_window_8 <= Inter_ref_05_12; + end + else + begin + Inter_V_window_0 <= Inter_ref_04_04;Inter_V_window_1 <= Inter_ref_04_05; + Inter_V_window_2 <= Inter_ref_04_06;Inter_V_window_3 <= Inter_ref_04_07; + Inter_V_window_4 <= Inter_ref_04_08;Inter_V_window_5 <= Inter_ref_04_09; + Inter_V_window_6 <= Inter_ref_04_10;Inter_V_window_7 <= Inter_ref_04_11; + Inter_V_window_8 <= Inter_ref_04_12; + end + 3'd1: + if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) + begin + Inter_V_window_0 <= Inter_ref_06_04;Inter_V_window_1 <= Inter_ref_06_05; + Inter_V_window_2 <= Inter_ref_06_06;Inter_V_window_3 <= Inter_ref_06_07; + Inter_V_window_4 <= Inter_ref_06_08;Inter_V_window_5 <= Inter_ref_06_09; + Inter_V_window_6 <= Inter_ref_06_10;Inter_V_window_7 <= Inter_ref_06_11; + Inter_V_window_8 <= Inter_ref_06_12; + end + else + begin + Inter_V_window_0 <= Inter_ref_05_04;Inter_V_window_1 <= Inter_ref_05_05; + Inter_V_window_2 <= Inter_ref_05_06;Inter_V_window_3 <= Inter_ref_05_07; + Inter_V_window_4 <= Inter_ref_05_08;Inter_V_window_5 <= Inter_ref_05_09; + Inter_V_window_6 <= Inter_ref_05_10;Inter_V_window_7 <= Inter_ref_05_11; + Inter_V_window_8 <= Inter_ref_05_12; + end + default: + begin + Inter_V_window_0 <= 0;Inter_V_window_1 <= 0;Inter_V_window_2 <= 0; + Inter_V_window_3 <= 0;Inter_V_window_4 <= 0;Inter_V_window_5 <= 0; + Inter_V_window_6 <= 0;Inter_V_window_7 <= 0;Inter_V_window_8 <= 0; + end + endcase + 4'b0001: //Right bottom blk4x4 + case (Inter_V_window_counter) + 3'd4: + if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) + begin + Inter_V_window_0 <= Inter_ref_07_04;Inter_V_window_1 <= Inter_ref_07_05; + Inter_V_window_2 <= Inter_ref_07_06;Inter_V_window_3 <= Inter_ref_07_07; + Inter_V_window_4 <= Inter_ref_07_08;Inter_V_window_5 <= Inter_ref_07_09; + Inter_V_window_6 <= Inter_ref_07_10;Inter_V_window_7 <= Inter_ref_07_11; + Inter_V_window_8 <= Inter_ref_07_12; + end + else + begin + Inter_V_window_0 <= Inter_ref_06_04;Inter_V_window_1 <= Inter_ref_06_05; + Inter_V_window_2 <= Inter_ref_06_06;Inter_V_window_3 <= Inter_ref_06_07; + Inter_V_window_4 <= Inter_ref_06_08;Inter_V_window_5 <= Inter_ref_06_09; + Inter_V_window_6 <= Inter_ref_06_10;Inter_V_window_7 <= Inter_ref_06_11; + Inter_V_window_8 <= Inter_ref_06_12; + end + 3'd3: + if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) + begin + Inter_V_window_0 <= Inter_ref_08_04;Inter_V_window_1 <= Inter_ref_08_05; + Inter_V_window_2 <= Inter_ref_08_06;Inter_V_window_3 <= Inter_ref_08_07; + Inter_V_window_4 <= Inter_ref_08_08;Inter_V_window_5 <= Inter_ref_08_09; + Inter_V_window_6 <= Inter_ref_08_10;Inter_V_window_7 <= Inter_ref_08_11; + Inter_V_window_8 <= Inter_ref_08_12; + end + else + begin + Inter_V_window_0 <= Inter_ref_07_04;Inter_V_window_1 <= Inter_ref_07_05; + Inter_V_window_2 <= Inter_ref_07_06;Inter_V_window_3 <= Inter_ref_07_07; + Inter_V_window_4 <= Inter_ref_07_08;Inter_V_window_5 <= Inter_ref_07_09; + Inter_V_window_6 <= Inter_ref_07_10;Inter_V_window_7 <= Inter_ref_07_11; + Inter_V_window_8 <= Inter_ref_07_12; + end + 3'd2: + if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) + begin + Inter_V_window_0 <= Inter_ref_09_04;Inter_V_window_1 <= Inter_ref_09_05; + Inter_V_window_2 <= Inter_ref_09_06;Inter_V_window_3 <= Inter_ref_09_07; + Inter_V_window_4 <= Inter_ref_09_08;Inter_V_window_5 <= Inter_ref_09_09; + Inter_V_window_6 <= Inter_ref_09_10;Inter_V_window_7 <= Inter_ref_09_11; + Inter_V_window_8 <= Inter_ref_09_12; + end + else + begin + Inter_V_window_0 <= Inter_ref_08_04;Inter_V_window_1 <= Inter_ref_08_05; + Inter_V_window_2 <= Inter_ref_08_06;Inter_V_window_3 <= Inter_ref_08_07; + Inter_V_window_4 <= Inter_ref_08_08;Inter_V_window_5 <= Inter_ref_08_09; + Inter_V_window_6 <= Inter_ref_08_10;Inter_V_window_7 <= Inter_ref_08_11; + Inter_V_window_8 <= Inter_ref_08_12; + end + 3'd1: + if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) + begin + Inter_V_window_0 <= Inter_ref_10_04;Inter_V_window_1 <= Inter_ref_10_05; + Inter_V_window_2 <= Inter_ref_10_06;Inter_V_window_3 <= Inter_ref_10_07; + Inter_V_window_4 <= Inter_ref_10_08;Inter_V_window_5 <= Inter_ref_10_09; + Inter_V_window_6 <= Inter_ref_10_10;Inter_V_window_7 <= Inter_ref_10_11; + Inter_V_window_8 <= Inter_ref_10_12; + end + else + begin + Inter_V_window_0 <= Inter_ref_09_04;Inter_V_window_1 <= Inter_ref_09_05; + Inter_V_window_2 <= Inter_ref_09_06;Inter_V_window_3 <= Inter_ref_09_07; + Inter_V_window_4 <= Inter_ref_09_08;Inter_V_window_5 <= Inter_ref_09_09; + Inter_V_window_6 <= Inter_ref_09_10;Inter_V_window_7 <= Inter_ref_09_11; + Inter_V_window_8 <= Inter_ref_09_12; + end + default: + begin + Inter_V_window_0 <= 0;Inter_V_window_1 <= 0;Inter_V_window_2 <= 0; + Inter_V_window_3 <= 0;Inter_V_window_4 <= 0;Inter_V_window_5 <= 0; + Inter_V_window_6 <= 0;Inter_V_window_7 <= 0;Inter_V_window_8 <= 0; + end + endcase + default: + begin + Inter_V_window_0 <= 0;Inter_V_window_1 <= 0;Inter_V_window_2 <= 0; + Inter_V_window_3 <= 0;Inter_V_window_4 <= 0;Inter_V_window_5 <= 0; + Inter_V_window_6 <= 0;Inter_V_window_7 <= 0;Inter_V_window_8 <= 0; + end + endcase + + //Luma bilinear window + always @ (Is_blk4x4_0 or Is_blk4x4_1 or Is_blk4x4_2 or Is_blk4x4_3 or pos_FracL or blk4x4_inter_calculate_counter + or Inter_ref_02_02 or Inter_ref_03_02 or Inter_ref_04_02 or Inter_ref_05_02 or Inter_ref_06_02 + or Inter_ref_07_02 or Inter_ref_08_02 or Inter_ref_09_02 or Inter_ref_10_02 + or Inter_ref_02_03 or Inter_ref_03_03 or Inter_ref_04_03 or Inter_ref_05_03 or Inter_ref_06_03 + or Inter_ref_07_03 or Inter_ref_08_03 or Inter_ref_09_03 or Inter_ref_10_03 + or Inter_ref_02_04 or Inter_ref_03_04 or Inter_ref_04_04 or Inter_ref_05_04 or Inter_ref_06_04 + or Inter_ref_07_04 or Inter_ref_08_04 or Inter_ref_09_04 or Inter_ref_10_04 + or Inter_ref_02_05 or Inter_ref_03_05 or Inter_ref_04_05 or Inter_ref_05_05 or Inter_ref_06_05 + or Inter_ref_07_05 or Inter_ref_08_05 or Inter_ref_09_05 or Inter_ref_10_05 + or Inter_ref_02_06 or Inter_ref_03_06 or Inter_ref_04_06 or Inter_ref_05_06 or Inter_ref_06_06 + or Inter_ref_07_06 or Inter_ref_08_06 or Inter_ref_09_06 or Inter_ref_10_06 + or Inter_ref_02_07 or Inter_ref_03_07 or Inter_ref_04_07 or Inter_ref_05_07 or Inter_ref_06_07 + or Inter_ref_07_07 or Inter_ref_08_07 or Inter_ref_09_07 or Inter_ref_10_07 + or Inter_ref_02_08 or Inter_ref_03_08 or Inter_ref_04_08 or Inter_ref_05_08 or Inter_ref_06_08 + or Inter_ref_07_08 or Inter_ref_08_08 or Inter_ref_09_08 or Inter_ref_10_08 + or Inter_ref_02_09 or Inter_ref_03_09 or Inter_ref_04_09 or Inter_ref_05_09 or Inter_ref_06_09 + or Inter_ref_07_09 or Inter_ref_08_09 or Inter_ref_09_09 or Inter_ref_10_09 + or Inter_ref_02_10 or Inter_ref_03_10 or Inter_ref_04_10 or Inter_ref_05_10 or Inter_ref_06_10 + or Inter_ref_07_10 or Inter_ref_08_10 or Inter_ref_09_10) + case ({Is_blk4x4_0,Is_blk4x4_1,Is_blk4x4_2,Is_blk4x4_3}) + 4'b1000: //Left top blk4x4 + case (pos_FracL) + pos_a,pos_d: + case (blk4x4_inter_calculate_counter) + 4'd4:begin Inter_bi_window_0 <= Inter_ref_02_02;Inter_bi_window_1 <= Inter_ref_02_03; + Inter_bi_window_2 <= Inter_ref_02_04;Inter_bi_window_3 <= Inter_ref_02_05; end + 4'd3:begin Inter_bi_window_0 <= Inter_ref_03_02;Inter_bi_window_1 <= Inter_ref_03_03; + Inter_bi_window_2 <= Inter_ref_03_04;Inter_bi_window_3 <= Inter_ref_03_05; end + 4'd2:begin Inter_bi_window_0 <= Inter_ref_04_02;Inter_bi_window_1 <= Inter_ref_04_03; + Inter_bi_window_2 <= Inter_ref_04_04;Inter_bi_window_3 <= Inter_ref_04_05; end + 4'd1:begin Inter_bi_window_0 <= Inter_ref_05_02;Inter_bi_window_1 <= Inter_ref_05_03; + Inter_bi_window_2 <= Inter_ref_05_04;Inter_bi_window_3 <= Inter_ref_05_05; end + default:begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; + Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end + endcase + pos_c: + case (blk4x4_inter_calculate_counter) + 4'd4:begin Inter_bi_window_0 <= Inter_ref_03_02;Inter_bi_window_1 <= Inter_ref_03_03; + Inter_bi_window_2 <= Inter_ref_03_04;Inter_bi_window_3 <= Inter_ref_03_05; end + 4'd3:begin Inter_bi_window_0 <= Inter_ref_04_02;Inter_bi_window_1 <= Inter_ref_04_03; + Inter_bi_window_2 <= Inter_ref_04_04;Inter_bi_window_3 <= Inter_ref_04_05; end + 4'd2:begin Inter_bi_window_0 <= Inter_ref_05_02;Inter_bi_window_1 <= Inter_ref_05_03; + Inter_bi_window_2 <= Inter_ref_05_04;Inter_bi_window_3 <= Inter_ref_05_05; end + 4'd1:begin Inter_bi_window_0 <= Inter_ref_06_02;Inter_bi_window_1 <= Inter_ref_06_03; + Inter_bi_window_2 <= Inter_ref_06_04;Inter_bi_window_3 <= Inter_ref_06_05; end + default:begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; + Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end + endcase + pos_n: + case (blk4x4_inter_calculate_counter) + 4'd4:begin Inter_bi_window_0 <= Inter_ref_02_03;Inter_bi_window_1 <= Inter_ref_02_04; + Inter_bi_window_2 <= Inter_ref_02_05;Inter_bi_window_3 <= Inter_ref_02_06; end + 4'd3:begin Inter_bi_window_0 <= Inter_ref_03_03;Inter_bi_window_1 <= Inter_ref_03_04; + Inter_bi_window_2 <= Inter_ref_03_05;Inter_bi_window_3 <= Inter_ref_03_06; end + 4'd2:begin Inter_bi_window_0 <= Inter_ref_04_03;Inter_bi_window_1 <= Inter_ref_04_04; + Inter_bi_window_2 <= Inter_ref_04_05;Inter_bi_window_3 <= Inter_ref_04_06; end + 4'd1:begin Inter_bi_window_0 <= Inter_ref_05_03;Inter_bi_window_1 <= Inter_ref_05_04; + Inter_bi_window_2 <= Inter_ref_05_05;Inter_bi_window_3 <= Inter_ref_05_06; end + default:begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; + Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end + endcase + default: + begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; + Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end + endcase + 4'b0100: //Right top blk4x4 + case (pos_FracL) + pos_a,pos_d: + case (blk4x4_inter_calculate_counter) + 4'd4:begin Inter_bi_window_0 <= Inter_ref_06_02;Inter_bi_window_1 <= Inter_ref_06_03; + Inter_bi_window_2 <= Inter_ref_06_04;Inter_bi_window_3 <= Inter_ref_06_05; end + 4'd3:begin Inter_bi_window_0 <= Inter_ref_07_02;Inter_bi_window_1 <= Inter_ref_07_03; + Inter_bi_window_2 <= Inter_ref_07_04;Inter_bi_window_3 <= Inter_ref_07_05; end + 4'd2:begin Inter_bi_window_0 <= Inter_ref_08_02;Inter_bi_window_1 <= Inter_ref_08_03; + Inter_bi_window_2 <= Inter_ref_08_04;Inter_bi_window_3 <= Inter_ref_08_05; end + 4'd1:begin Inter_bi_window_0 <= Inter_ref_09_02;Inter_bi_window_1 <= Inter_ref_09_03; + Inter_bi_window_2 <= Inter_ref_09_04;Inter_bi_window_3 <= Inter_ref_09_05; end + default:begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; + Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end + endcase + pos_c: + case (blk4x4_inter_calculate_counter) + 4'd4:begin Inter_bi_window_0 <= Inter_ref_07_02;Inter_bi_window_1 <= Inter_ref_07_03; + Inter_bi_window_2 <= Inter_ref_07_04;Inter_bi_window_3 <= Inter_ref_07_05; end + 4'd3:begin Inter_bi_window_0 <= Inter_ref_08_02;Inter_bi_window_1 <= Inter_ref_08_03; + Inter_bi_window_2 <= Inter_ref_08_04;Inter_bi_window_3 <= Inter_ref_08_05; end + 4'd2:begin Inter_bi_window_0 <= Inter_ref_09_02;Inter_bi_window_1 <= Inter_ref_09_03; + Inter_bi_window_2 <= Inter_ref_09_04;Inter_bi_window_3 <= Inter_ref_09_05; end + 4'd1:begin Inter_bi_window_0 <= Inter_ref_10_02;Inter_bi_window_1 <= Inter_ref_10_03; + Inter_bi_window_2 <= Inter_ref_10_04;Inter_bi_window_3 <= Inter_ref_10_05; end + default:begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; + Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end + endcase + pos_n: + case (blk4x4_inter_calculate_counter) + 4'd4:begin Inter_bi_window_0 <= Inter_ref_06_03;Inter_bi_window_1 <= Inter_ref_06_04; + Inter_bi_window_2 <= Inter_ref_06_05;Inter_bi_window_3 <= Inter_ref_06_06; end + 4'd3:begin Inter_bi_window_0 <= Inter_ref_07_03;Inter_bi_window_1 <= Inter_ref_07_04; + Inter_bi_window_2 <= Inter_ref_07_05;Inter_bi_window_3 <= Inter_ref_07_06; end + 4'd2:begin Inter_bi_window_0 <= Inter_ref_08_03;Inter_bi_window_1 <= Inter_ref_08_04; + Inter_bi_window_2 <= Inter_ref_08_05;Inter_bi_window_3 <= Inter_ref_08_06; end + 4'd1:begin Inter_bi_window_0 <= Inter_ref_09_03;Inter_bi_window_1 <= Inter_ref_09_04; + Inter_bi_window_2 <= Inter_ref_09_05;Inter_bi_window_3 <= Inter_ref_09_06; end + default:begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; + Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end + endcase + default: + begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; + Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end + endcase + 4'b0010: //Left bottom blk4x4 + case (pos_FracL) + pos_a,pos_d: + case (blk4x4_inter_calculate_counter) + 4'd4:begin Inter_bi_window_0 <= Inter_ref_02_06;Inter_bi_window_1 <= Inter_ref_02_07; + Inter_bi_window_2 <= Inter_ref_02_08;Inter_bi_window_3 <= Inter_ref_02_09; end + 4'd3:begin Inter_bi_window_0 <= Inter_ref_03_06;Inter_bi_window_1 <= Inter_ref_03_07; + Inter_bi_window_2 <= Inter_ref_03_08;Inter_bi_window_3 <= Inter_ref_03_09; end + 4'd2:begin Inter_bi_window_0 <= Inter_ref_04_06;Inter_bi_window_1 <= Inter_ref_04_07; + Inter_bi_window_2 <= Inter_ref_04_08;Inter_bi_window_3 <= Inter_ref_04_09; end + 4'd1:begin Inter_bi_window_0 <= Inter_ref_05_06;Inter_bi_window_1 <= Inter_ref_05_07; + Inter_bi_window_2 <= Inter_ref_05_08;Inter_bi_window_3 <= Inter_ref_05_09; end + default:begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; + Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end + endcase + pos_c: + case (blk4x4_inter_calculate_counter) + 4'd4:begin Inter_bi_window_0 <= Inter_ref_03_06;Inter_bi_window_1 <= Inter_ref_03_07; + Inter_bi_window_2 <= Inter_ref_03_08;Inter_bi_window_3 <= Inter_ref_03_09; end + 4'd3:begin Inter_bi_window_0 <= Inter_ref_04_06;Inter_bi_window_1 <= Inter_ref_04_07; + Inter_bi_window_2 <= Inter_ref_04_08;Inter_bi_window_3 <= Inter_ref_04_09; end + 4'd2:begin Inter_bi_window_0 <= Inter_ref_05_06;Inter_bi_window_1 <= Inter_ref_05_07; + Inter_bi_window_2 <= Inter_ref_05_08;Inter_bi_window_3 <= Inter_ref_05_09; end + 4'd1:begin Inter_bi_window_0 <= Inter_ref_06_06;Inter_bi_window_1 <= Inter_ref_06_07; + Inter_bi_window_2 <= Inter_ref_06_08;Inter_bi_window_3 <= Inter_ref_06_09; end + default:begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; + Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end + endcase + pos_n: + case (blk4x4_inter_calculate_counter) + 4'd4:begin Inter_bi_window_0 <= Inter_ref_02_07;Inter_bi_window_1 <= Inter_ref_02_08; + Inter_bi_window_2 <= Inter_ref_02_09;Inter_bi_window_3 <= Inter_ref_02_10; end + 4'd3:begin Inter_bi_window_0 <= Inter_ref_03_07;Inter_bi_window_1 <= Inter_ref_03_08; + Inter_bi_window_2 <= Inter_ref_03_09;Inter_bi_window_3 <= Inter_ref_03_10; end + 4'd2:begin Inter_bi_window_0 <= Inter_ref_04_07;Inter_bi_window_1 <= Inter_ref_04_08; + Inter_bi_window_2 <= Inter_ref_04_09;Inter_bi_window_3 <= Inter_ref_04_10; end + 4'd1:begin Inter_bi_window_0 <= Inter_ref_05_07;Inter_bi_window_1 <= Inter_ref_05_08; + Inter_bi_window_2 <= Inter_ref_05_09;Inter_bi_window_3 <= Inter_ref_05_10; end + default:begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; + Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end + endcase + default: + begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; + Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end + endcase + 4'b0001: //Right bottom blk4x4 + case (pos_FracL) + pos_a,pos_d: + case (blk4x4_inter_calculate_counter) + 4'd4:begin Inter_bi_window_0 <= Inter_ref_06_06;Inter_bi_window_1 <= Inter_ref_06_07; + Inter_bi_window_2 <= Inter_ref_06_08;Inter_bi_window_3 <= Inter_ref_06_09; end + 4'd3:begin Inter_bi_window_0 <= Inter_ref_07_06;Inter_bi_window_1 <= Inter_ref_07_07; + Inter_bi_window_2 <= Inter_ref_07_08;Inter_bi_window_3 <= Inter_ref_07_09; end + 4'd2:begin Inter_bi_window_0 <= Inter_ref_08_06;Inter_bi_window_1 <= Inter_ref_08_07; + Inter_bi_window_2 <= Inter_ref_08_08;Inter_bi_window_3 <= Inter_ref_08_09; end + 4'd1:begin Inter_bi_window_0 <= Inter_ref_09_06;Inter_bi_window_1 <= Inter_ref_09_07; + Inter_bi_window_2 <= Inter_ref_09_08;Inter_bi_window_3 <= Inter_ref_09_09; end + default:begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; + Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end + endcase + pos_c: + case (blk4x4_inter_calculate_counter) + 4'd4:begin Inter_bi_window_0 <= Inter_ref_07_06;Inter_bi_window_1 <= Inter_ref_07_07; + Inter_bi_window_2 <= Inter_ref_07_08;Inter_bi_window_3 <= Inter_ref_07_09; end + 4'd3:begin Inter_bi_window_0 <= Inter_ref_08_06;Inter_bi_window_1 <= Inter_ref_08_07; + Inter_bi_window_2 <= Inter_ref_08_08;Inter_bi_window_3 <= Inter_ref_08_09; end + 4'd2:begin Inter_bi_window_0 <= Inter_ref_09_06;Inter_bi_window_1 <= Inter_ref_09_07; + Inter_bi_window_2 <= Inter_ref_09_08;Inter_bi_window_3 <= Inter_ref_09_09; end + 4'd1:begin Inter_bi_window_0 <= Inter_ref_10_06;Inter_bi_window_1 <= Inter_ref_10_07; + Inter_bi_window_2 <= Inter_ref_10_08;Inter_bi_window_3 <= Inter_ref_10_09; end + default:begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; + Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end + endcase + pos_n: + case (blk4x4_inter_calculate_counter) + 4'd4:begin Inter_bi_window_0 <= Inter_ref_06_07;Inter_bi_window_1 <= Inter_ref_06_08; + Inter_bi_window_2 <= Inter_ref_06_09;Inter_bi_window_3 <= Inter_ref_06_10; end + 4'd3:begin Inter_bi_window_0 <= Inter_ref_07_07;Inter_bi_window_1 <= Inter_ref_07_08; + Inter_bi_window_2 <= Inter_ref_07_09;Inter_bi_window_3 <= Inter_ref_07_10; end + 4'd2:begin Inter_bi_window_0 <= Inter_ref_08_07;Inter_bi_window_1 <= Inter_ref_08_08; + Inter_bi_window_2 <= Inter_ref_08_09;Inter_bi_window_3 <= Inter_ref_08_10; end + 4'd1:begin Inter_bi_window_0 <= Inter_ref_09_07;Inter_bi_window_1 <= Inter_ref_09_08; + Inter_bi_window_2 <= Inter_ref_09_09;Inter_bi_window_3 <= Inter_ref_09_10; end + default:begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; + Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end + endcase + default: + begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; + Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end + endcase + default: + begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; + Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end + endcase + + //chroma sliding window:Inter_C_window_0 ~ Inter_C_window_3 + always @ (IsInterChroma or blk4x4_inter_calculate_counter or mv_below8x8_curr + or Inter_ref_00_00 or Inter_ref_01_00 or Inter_ref_02_00 or Inter_ref_03_00 or Inter_ref_04_00 + or Inter_ref_00_01 or Inter_ref_01_01 or Inter_ref_02_01 or Inter_ref_03_01 or Inter_ref_04_01 + or Inter_ref_00_02 or Inter_ref_01_02 or Inter_ref_02_02 or Inter_ref_03_02 or Inter_ref_04_02 + or Inter_ref_00_03 or Inter_ref_01_03 or Inter_ref_02_03 or Inter_ref_03_03 or Inter_ref_04_03 + or Inter_ref_00_04 or Inter_ref_01_04 or Inter_ref_02_04 or Inter_ref_03_04 or Inter_ref_04_04 + ) + if (IsInterChroma && mv_below8x8_curr == 1'b0) + case (blk4x4_inter_calculate_counter) + 4'd4: + begin + Inter_C_window_0_0 <= Inter_ref_00_00; Inter_C_window_1_0 <= Inter_ref_01_00; + Inter_C_window_2_0 <= Inter_ref_02_00; + Inter_C_window_0_1 <= Inter_ref_00_01; Inter_C_window_1_1 <= Inter_ref_01_01; + Inter_C_window_2_1 <= Inter_ref_02_01; + Inter_C_window_0_2 <= Inter_ref_00_02; Inter_C_window_1_2 <= Inter_ref_01_02; + Inter_C_window_2_2 <= Inter_ref_02_02; + end + 4'd3: + begin + Inter_C_window_0_0 <= Inter_ref_02_00; Inter_C_window_1_0 <= Inter_ref_03_00; + Inter_C_window_2_0 <= Inter_ref_04_00; + Inter_C_window_0_1 <= Inter_ref_02_01; Inter_C_window_1_1 <= Inter_ref_03_01; + Inter_C_window_2_1 <= Inter_ref_04_01; + Inter_C_window_0_2 <= Inter_ref_02_02; Inter_C_window_1_2 <= Inter_ref_03_02; + Inter_C_window_2_2 <= Inter_ref_04_02; + end + 4'd2: + begin + Inter_C_window_0_0 <= Inter_ref_00_02; Inter_C_window_1_0 <= Inter_ref_01_02; + Inter_C_window_2_0 <= Inter_ref_02_02; + Inter_C_window_0_1 <= Inter_ref_00_03; Inter_C_window_1_1 <= Inter_ref_01_03; + Inter_C_window_2_1 <= Inter_ref_02_03; + Inter_C_window_0_2 <= Inter_ref_00_04; Inter_C_window_1_2 <= Inter_ref_01_04; + Inter_C_window_2_2 <= Inter_ref_02_04; + end + 4'd1: + begin + Inter_C_window_0_0 <= Inter_ref_02_02; Inter_C_window_1_0 <= Inter_ref_03_02; + Inter_C_window_2_0 <= Inter_ref_04_02; + Inter_C_window_0_1 <= Inter_ref_02_03; Inter_C_window_1_1 <= Inter_ref_03_03; + Inter_C_window_2_1 <= Inter_ref_04_03; + Inter_C_window_0_2 <= Inter_ref_02_04; Inter_C_window_1_2 <= Inter_ref_03_04; + Inter_C_window_2_2 <= Inter_ref_04_04; + end + default: + begin + Inter_C_window_0_0 <= 0; Inter_C_window_1_0 <= 0;Inter_C_window_2_0 <= 0; + Inter_C_window_0_1 <= 0; Inter_C_window_1_1 <= 0;Inter_C_window_2_1 <= 0; + Inter_C_window_0_2 <= 0; Inter_C_window_1_2 <= 0;Inter_C_window_2_2 <= 0; + end + endcase + else if (IsInterChroma && mv_below8x8_curr == 1'b1) + case (blk4x4_inter_calculate_counter) + 4'd1: + begin + Inter_C_window_0_0 <= Inter_ref_00_00; Inter_C_window_1_0 <= Inter_ref_01_00; + Inter_C_window_2_0 <= Inter_ref_02_00; + Inter_C_window_0_1 <= Inter_ref_00_01; Inter_C_window_1_1 <= Inter_ref_01_01; + Inter_C_window_2_1 <= Inter_ref_02_01; + Inter_C_window_0_2 <= Inter_ref_00_02; Inter_C_window_1_2 <= Inter_ref_01_02; + Inter_C_window_2_2 <= Inter_ref_02_02; + end + default: + begin + Inter_C_window_0_0 <= 0; Inter_C_window_1_0 <= 0;Inter_C_window_2_0 <= 0; + Inter_C_window_0_1 <= 0; Inter_C_window_1_1 <= 0;Inter_C_window_2_1 <= 0; + Inter_C_window_0_2 <= 0; Inter_C_window_1_2 <= 0;Inter_C_window_2_2 <= 0; + end + endcase + else + begin + Inter_C_window_0_0 <= 0; Inter_C_window_1_0 <= 0;Inter_C_window_2_0 <= 0; + Inter_C_window_0_1 <= 0; Inter_C_window_1_1 <= 0;Inter_C_window_2_1 <= 0; + Inter_C_window_0_2 <= 0; Inter_C_window_1_2 <= 0;Inter_C_window_2_2 <= 0; + end + +endmodule + + + + + + + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/Inter_pred_top.v b/demo_chip_rtl/rtl/nova/tags/Start/src/Inter_pred_top.v new file mode 100644 index 0000000..0b03bef --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/Inter_pred_top.v @@ -0,0 +1,703 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : Inter_pred_top.v +// Generated : Oct 28, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Top module of Inter prediction, including +// Inter_pred_pipeline.v +// Inter_pred_reg_control.v +// Inter_pred_sliding_window.v +// Inter_pred_LPE.v +// Inter_pred_CPE.v +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module Inter_pred_top (clk,gclk_Inter_ref_rf,reset_n,mb_num_h,mb_num_v,trigger_blk4x4_inter_pred,blk4x4_rec_counter, + mb_type_general_bit3,mv_is16x16,mv_below8x8,mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3, + mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3,ref_frame_RAM_dout, + + Inter_pred_out0,Inter_pred_out1,Inter_pred_out2,Inter_pred_out3, + blk4x4_inter_preload_counter,blk4x4_inter_calculate_counter,Inter_chroma2x2_counter, + mv_below8x8_curr,pos_FracL,end_of_one_blk4x4_inter,Inter_blk4x4_pred_output_valid, + ref_frame_RAM_rd,ref_frame_RAM_rd_addr); + input clk; + input gclk_Inter_ref_rf; + input reset_n; + input [3:0] mb_num_h,mb_num_v; + input trigger_blk4x4_inter_pred; + input [4:0] blk4x4_rec_counter; + input mb_type_general_bit3; + input mv_is16x16; + input [3:0] mv_below8x8; + input [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3; + input [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3; + input [31:0] ref_frame_RAM_dout; + + output [7:0] Inter_pred_out0,Inter_pred_out1,Inter_pred_out2,Inter_pred_out3; + output [5:0] blk4x4_inter_preload_counter; + output [3:0] blk4x4_inter_calculate_counter; + output [1:0] Inter_chroma2x2_counter; + output mv_below8x8_curr; + output [3:0] pos_FracL; + output end_of_one_blk4x4_inter; + output [1:0] Inter_blk4x4_pred_output_valid; + output ref_frame_RAM_rd; + output [13:0] ref_frame_RAM_rd_addr; + + wire [7:0] LPE0_out,LPE1_out,LPE2_out,LPE3_out; + wire [7:0] CPE0_out,CPE1_out,CPE2_out,CPE3_out; + wire [5:0] blk4x4_inter_preload_counter; + wire mv_below8x8_curr; + wire IsInterLuma,IsInterChroma; + wire Is_InterChromaCopy; + wire [8:0] xInt_addr_unclip; + wire [1:0] xInt_org_unclip_1to0; + wire [2:0] xFracC,yFracC; + + wire [7:0] Inter_ref_00_00,Inter_ref_01_00,Inter_ref_02_00,Inter_ref_03_00,Inter_ref_04_00,Inter_ref_05_00; + wire [7:0] Inter_ref_06_00,Inter_ref_07_00,Inter_ref_08_00,Inter_ref_09_00,Inter_ref_10_00,Inter_ref_11_00,Inter_ref_12_00; + wire [7:0] Inter_ref_00_01,Inter_ref_01_01,Inter_ref_02_01,Inter_ref_03_01,Inter_ref_04_01,Inter_ref_05_01; + wire [7:0] Inter_ref_06_01,Inter_ref_07_01,Inter_ref_08_01,Inter_ref_09_01,Inter_ref_10_01,Inter_ref_11_01,Inter_ref_12_01; + wire [7:0] Inter_ref_00_02,Inter_ref_01_02,Inter_ref_02_02,Inter_ref_03_02,Inter_ref_04_02,Inter_ref_05_02; + wire [7:0] Inter_ref_06_02,Inter_ref_07_02,Inter_ref_08_02,Inter_ref_09_02,Inter_ref_10_02,Inter_ref_11_02,Inter_ref_12_02; + wire [7:0] Inter_ref_00_03,Inter_ref_01_03,Inter_ref_02_03,Inter_ref_03_03,Inter_ref_04_03,Inter_ref_05_03; + wire [7:0] Inter_ref_06_03,Inter_ref_07_03,Inter_ref_08_03,Inter_ref_09_03,Inter_ref_10_03,Inter_ref_11_03,Inter_ref_12_03; + wire [7:0] Inter_ref_00_04,Inter_ref_01_04,Inter_ref_02_04,Inter_ref_03_04,Inter_ref_04_04,Inter_ref_05_04; + wire [7:0] Inter_ref_06_04,Inter_ref_07_04,Inter_ref_08_04,Inter_ref_09_04,Inter_ref_10_04,Inter_ref_11_04,Inter_ref_12_04; + wire [7:0] Inter_ref_00_05,Inter_ref_01_05,Inter_ref_02_05,Inter_ref_03_05,Inter_ref_04_05,Inter_ref_05_05; + wire [7:0] Inter_ref_06_05,Inter_ref_07_05,Inter_ref_08_05,Inter_ref_09_05,Inter_ref_10_05,Inter_ref_11_05,Inter_ref_12_05; + wire [7:0] Inter_ref_00_06,Inter_ref_01_06,Inter_ref_02_06,Inter_ref_03_06,Inter_ref_04_06,Inter_ref_05_06; + wire [7:0] Inter_ref_06_06,Inter_ref_07_06,Inter_ref_08_06,Inter_ref_09_06,Inter_ref_10_06,Inter_ref_11_06,Inter_ref_12_06; + wire [7:0] Inter_ref_00_07,Inter_ref_01_07,Inter_ref_02_07,Inter_ref_03_07,Inter_ref_04_07,Inter_ref_05_07; + wire [7:0] Inter_ref_06_07,Inter_ref_07_07,Inter_ref_08_07,Inter_ref_09_07,Inter_ref_10_07,Inter_ref_11_07,Inter_ref_12_07; + wire [7:0] Inter_ref_00_08,Inter_ref_01_08,Inter_ref_02_08,Inter_ref_03_08,Inter_ref_04_08,Inter_ref_05_08; + wire [7:0] Inter_ref_06_08,Inter_ref_07_08,Inter_ref_08_08,Inter_ref_09_08,Inter_ref_10_08,Inter_ref_11_08,Inter_ref_12_08; + wire [7:0] Inter_ref_00_09,Inter_ref_01_09,Inter_ref_02_09,Inter_ref_03_09,Inter_ref_04_09,Inter_ref_05_09; + wire [7:0] Inter_ref_06_09,Inter_ref_07_09,Inter_ref_08_09,Inter_ref_09_09,Inter_ref_10_09,Inter_ref_11_09,Inter_ref_12_09; + wire [7:0] Inter_ref_00_10,Inter_ref_01_10,Inter_ref_02_10,Inter_ref_03_10,Inter_ref_04_10,Inter_ref_05_10; + wire [7:0] Inter_ref_06_10,Inter_ref_07_10,Inter_ref_08_10,Inter_ref_09_10,Inter_ref_10_10,Inter_ref_11_10,Inter_ref_12_10; + wire [7:0] Inter_ref_00_11,Inter_ref_01_11,Inter_ref_02_11,Inter_ref_03_11,Inter_ref_04_11,Inter_ref_05_11; + wire [7:0] Inter_ref_06_11,Inter_ref_07_11,Inter_ref_08_11,Inter_ref_09_11,Inter_ref_10_11,Inter_ref_11_11,Inter_ref_12_11; + wire [7:0] Inter_ref_00_12,Inter_ref_01_12,Inter_ref_02_12,Inter_ref_03_12,Inter_ref_04_12,Inter_ref_05_12; + wire [7:0] Inter_ref_06_12,Inter_ref_07_12,Inter_ref_08_12,Inter_ref_09_12,Inter_ref_10_12,Inter_ref_11_12,Inter_ref_12_12; + + wire [7:0] Inter_pix_copy0,Inter_pix_copy1,Inter_pix_copy2,Inter_pix_copy3; + wire [7:0] Inter_H_window_0_0,Inter_H_window_1_0,Inter_H_window_2_0,Inter_H_window_3_0,Inter_H_window_4_0,Inter_H_window_5_0; + wire [7:0] Inter_H_window_0_1,Inter_H_window_1_1,Inter_H_window_2_1,Inter_H_window_3_1,Inter_H_window_4_1,Inter_H_window_5_1; + wire [7:0] Inter_H_window_0_2,Inter_H_window_1_2,Inter_H_window_2_2,Inter_H_window_3_2,Inter_H_window_4_2,Inter_H_window_5_2; + wire [7:0] Inter_H_window_0_3,Inter_H_window_1_3,Inter_H_window_2_3,Inter_H_window_3_3,Inter_H_window_4_3,Inter_H_window_5_3; + wire [7:0] Inter_H_window_0_4,Inter_H_window_1_4,Inter_H_window_2_4,Inter_H_window_3_4,Inter_H_window_4_4,Inter_H_window_5_4; + wire [7:0] Inter_H_window_0_5,Inter_H_window_1_5,Inter_H_window_2_5,Inter_H_window_3_5,Inter_H_window_4_5,Inter_H_window_5_5; + wire [7:0] Inter_H_window_0_6,Inter_H_window_1_6,Inter_H_window_2_6,Inter_H_window_3_6,Inter_H_window_4_6,Inter_H_window_5_6; + wire [7:0] Inter_H_window_0_7,Inter_H_window_1_7,Inter_H_window_2_7,Inter_H_window_3_7,Inter_H_window_4_7,Inter_H_window_5_7; + wire [7:0] Inter_H_window_0_8,Inter_H_window_1_8,Inter_H_window_2_8,Inter_H_window_3_8,Inter_H_window_4_8,Inter_H_window_5_8; + wire [7:0] Inter_V_window_0,Inter_V_window_1,Inter_V_window_2,Inter_V_window_3,Inter_V_window_4; + wire [7:0] Inter_V_window_5,Inter_V_window_6,Inter_V_window_7,Inter_V_window_8; + wire [7:0] Inter_C_window_0_0,Inter_C_window_1_0,Inter_C_window_2_0; + wire [7:0] Inter_C_window_0_1,Inter_C_window_1_1,Inter_C_window_2_1; + wire [7:0] Inter_C_window_0_2,Inter_C_window_1_2,Inter_C_window_2_2; + wire [7:0] Inter_bi_window_0,Inter_bi_window_1,Inter_bi_window_2,Inter_bi_window_3; + + Inter_pred_pipeline Inter_pred_pipeline( + .clk(clk), + .reset_n(reset_n), + .mb_num_h(mb_num_h), + .mb_num_v(mb_num_v), + .trigger_blk4x4_inter_pred(trigger_blk4x4_inter_pred), + .blk4x4_rec_counter(blk4x4_rec_counter), + .mb_type_general_bit3(mb_type_general_bit3), + .mv_is16x16(mv_is16x16), + .mv_below8x8(mv_below8x8), + .mvx_CurrMb0(mvx_CurrMb0), + .mvx_CurrMb1(mvx_CurrMb1), + .mvx_CurrMb2(mvx_CurrMb2), + .mvx_CurrMb3(mvx_CurrMb3), + .mvy_CurrMb0(mvy_CurrMb0), + .mvy_CurrMb1(mvy_CurrMb1), + .mvy_CurrMb2(mvy_CurrMb2), + .mvy_CurrMb3(mvy_CurrMb3), + .Inter_pix_copy0(Inter_pix_copy0), + .Inter_pix_copy1(Inter_pix_copy1), + .Inter_pix_copy2(Inter_pix_copy2), + .Inter_pix_copy3(Inter_pix_copy3), + .LPE0_out(LPE0_out), + .LPE1_out(LPE1_out), + .LPE2_out(LPE2_out), + .LPE3_out(LPE3_out), + .CPE0_out(CPE0_out), + .CPE1_out(CPE1_out), + .CPE2_out(CPE2_out), + .CPE3_out(CPE3_out), + + .mv_below8x8_curr(mv_below8x8_curr), + .blk4x4_inter_preload_counter(blk4x4_inter_preload_counter), + .blk4x4_inter_calculate_counter(blk4x4_inter_calculate_counter), + .Inter_chroma2x2_counter(Inter_chroma2x2_counter), + .end_of_one_blk4x4_inter(end_of_one_blk4x4_inter), + .IsInterLuma(IsInterLuma), + .IsInterChroma(IsInterChroma), + .Is_InterChromaCopy(Is_InterChromaCopy), + .xInt_addr_unclip(xInt_addr_unclip), + .xInt_org_unclip_1to0(xInt_org_unclip_1to0), + .pos_FracL(pos_FracL), + .xFracC(xFracC), + .yFracC(yFracC), + .Inter_pred_out0(Inter_pred_out0), + .Inter_pred_out1(Inter_pred_out1), + .Inter_pred_out2(Inter_pred_out2), + .Inter_pred_out3(Inter_pred_out3), + .Inter_blk4x4_pred_output_valid(Inter_blk4x4_pred_output_valid), + .ref_frame_RAM_rd(ref_frame_RAM_rd), + .ref_frame_RAM_rd_addr(ref_frame_RAM_rd_addr) + ); + + Inter_pred_reg_ctrl Inter_pred_reg_ctrl ( + .gclk_Inter_ref_rf(gclk_Inter_ref_rf), + .reset_n(reset_n), + .blk4x4_inter_preload_counter(blk4x4_inter_preload_counter), + .ref_frame_RAM_dout(ref_frame_RAM_dout), + .IsInterLuma(IsInterLuma), + .IsInterChroma(IsInterChroma), + .xInt_addr_unclip(xInt_addr_unclip), + .xInt_org_unclip_1to0(xInt_org_unclip_1to0), + .pos_FracL(pos_FracL), + .xFracC(xFracC), + .yFracC(yFracC), + .mv_below8x8_curr(mv_below8x8_curr), + + .Inter_ref_00_00(Inter_ref_00_00), + .Inter_ref_01_00(Inter_ref_01_00), + .Inter_ref_02_00(Inter_ref_02_00), + .Inter_ref_03_00(Inter_ref_03_00), + .Inter_ref_04_00(Inter_ref_04_00), + .Inter_ref_05_00(Inter_ref_05_00), + .Inter_ref_06_00(Inter_ref_06_00), + .Inter_ref_07_00(Inter_ref_07_00), + .Inter_ref_08_00(Inter_ref_08_00), + .Inter_ref_09_00(Inter_ref_09_00), + .Inter_ref_10_00(Inter_ref_10_00), + .Inter_ref_11_00(Inter_ref_11_00), + .Inter_ref_12_00(Inter_ref_12_00), + .Inter_ref_00_01(Inter_ref_00_01), + .Inter_ref_01_01(Inter_ref_01_01), + .Inter_ref_02_01(Inter_ref_02_01), + .Inter_ref_03_01(Inter_ref_03_01), + .Inter_ref_04_01(Inter_ref_04_01), + .Inter_ref_05_01(Inter_ref_05_01), + .Inter_ref_06_01(Inter_ref_06_01), + .Inter_ref_07_01(Inter_ref_07_01), + .Inter_ref_08_01(Inter_ref_08_01), + .Inter_ref_09_01(Inter_ref_09_01), + .Inter_ref_10_01(Inter_ref_10_01), + .Inter_ref_11_01(Inter_ref_11_01), + .Inter_ref_12_01(Inter_ref_12_01), + .Inter_ref_00_02(Inter_ref_00_02), + .Inter_ref_01_02(Inter_ref_01_02), + .Inter_ref_02_02(Inter_ref_02_02), + .Inter_ref_03_02(Inter_ref_03_02), + .Inter_ref_04_02(Inter_ref_04_02), + .Inter_ref_05_02(Inter_ref_05_02), + .Inter_ref_06_02(Inter_ref_06_02), + .Inter_ref_07_02(Inter_ref_07_02), + .Inter_ref_08_02(Inter_ref_08_02), + .Inter_ref_09_02(Inter_ref_09_02), + .Inter_ref_10_02(Inter_ref_10_02), + .Inter_ref_11_02(Inter_ref_11_02), + .Inter_ref_12_02(Inter_ref_12_02), + .Inter_ref_00_03(Inter_ref_00_03), + .Inter_ref_01_03(Inter_ref_01_03), + .Inter_ref_02_03(Inter_ref_02_03), + .Inter_ref_03_03(Inter_ref_03_03), + .Inter_ref_04_03(Inter_ref_04_03), + .Inter_ref_05_03(Inter_ref_05_03), + .Inter_ref_06_03(Inter_ref_06_03), + .Inter_ref_07_03(Inter_ref_07_03), + .Inter_ref_08_03(Inter_ref_08_03), + .Inter_ref_09_03(Inter_ref_09_03), + .Inter_ref_10_03(Inter_ref_10_03), + .Inter_ref_11_03(Inter_ref_11_03), + .Inter_ref_12_03(Inter_ref_12_03), + .Inter_ref_00_04(Inter_ref_00_04), + .Inter_ref_01_04(Inter_ref_01_04), + .Inter_ref_02_04(Inter_ref_02_04), + .Inter_ref_03_04(Inter_ref_03_04), + .Inter_ref_04_04(Inter_ref_04_04), + .Inter_ref_05_04(Inter_ref_05_04), + .Inter_ref_06_04(Inter_ref_06_04), + .Inter_ref_07_04(Inter_ref_07_04), + .Inter_ref_08_04(Inter_ref_08_04), + .Inter_ref_09_04(Inter_ref_09_04), + .Inter_ref_10_04(Inter_ref_10_04), + .Inter_ref_11_04(Inter_ref_11_04), + .Inter_ref_12_04(Inter_ref_12_04), + .Inter_ref_00_05(Inter_ref_00_05), + .Inter_ref_01_05(Inter_ref_01_05), + .Inter_ref_02_05(Inter_ref_02_05), + .Inter_ref_03_05(Inter_ref_03_05), + .Inter_ref_04_05(Inter_ref_04_05), + .Inter_ref_05_05(Inter_ref_05_05), + .Inter_ref_06_05(Inter_ref_06_05), + .Inter_ref_07_05(Inter_ref_07_05), + .Inter_ref_08_05(Inter_ref_08_05), + .Inter_ref_09_05(Inter_ref_09_05), + .Inter_ref_10_05(Inter_ref_10_05), + .Inter_ref_11_05(Inter_ref_11_05), + .Inter_ref_12_05(Inter_ref_12_05), + .Inter_ref_00_06(Inter_ref_00_06), + .Inter_ref_01_06(Inter_ref_01_06), + .Inter_ref_02_06(Inter_ref_02_06), + .Inter_ref_03_06(Inter_ref_03_06), + .Inter_ref_04_06(Inter_ref_04_06), + .Inter_ref_05_06(Inter_ref_05_06), + .Inter_ref_06_06(Inter_ref_06_06), + .Inter_ref_07_06(Inter_ref_07_06), + .Inter_ref_08_06(Inter_ref_08_06), + .Inter_ref_09_06(Inter_ref_09_06), + .Inter_ref_10_06(Inter_ref_10_06), + .Inter_ref_11_06(Inter_ref_11_06), + .Inter_ref_12_06(Inter_ref_12_06), + .Inter_ref_00_07(Inter_ref_00_07), + .Inter_ref_01_07(Inter_ref_01_07), + .Inter_ref_02_07(Inter_ref_02_07), + .Inter_ref_03_07(Inter_ref_03_07), + .Inter_ref_04_07(Inter_ref_04_07), + .Inter_ref_05_07(Inter_ref_05_07), + .Inter_ref_06_07(Inter_ref_06_07), + .Inter_ref_07_07(Inter_ref_07_07), + .Inter_ref_08_07(Inter_ref_08_07), + .Inter_ref_09_07(Inter_ref_09_07), + .Inter_ref_10_07(Inter_ref_10_07), + .Inter_ref_11_07(Inter_ref_11_07), + .Inter_ref_12_07(Inter_ref_12_07), + .Inter_ref_00_08(Inter_ref_00_08), + .Inter_ref_01_08(Inter_ref_01_08), + .Inter_ref_02_08(Inter_ref_02_08), + .Inter_ref_03_08(Inter_ref_03_08), + .Inter_ref_04_08(Inter_ref_04_08), + .Inter_ref_05_08(Inter_ref_05_08), + .Inter_ref_06_08(Inter_ref_06_08), + .Inter_ref_07_08(Inter_ref_07_08), + .Inter_ref_08_08(Inter_ref_08_08), + .Inter_ref_09_08(Inter_ref_09_08), + .Inter_ref_10_08(Inter_ref_10_08), + .Inter_ref_11_08(Inter_ref_11_08), + .Inter_ref_12_08(Inter_ref_12_08), + .Inter_ref_00_09(Inter_ref_00_09), + .Inter_ref_01_09(Inter_ref_01_09), + .Inter_ref_02_09(Inter_ref_02_09), + .Inter_ref_03_09(Inter_ref_03_09), + .Inter_ref_04_09(Inter_ref_04_09), + .Inter_ref_05_09(Inter_ref_05_09), + .Inter_ref_06_09(Inter_ref_06_09), + .Inter_ref_07_09(Inter_ref_07_09), + .Inter_ref_08_09(Inter_ref_08_09), + .Inter_ref_09_09(Inter_ref_09_09), + .Inter_ref_10_09(Inter_ref_10_09), + .Inter_ref_11_09(Inter_ref_11_09), + .Inter_ref_12_09(Inter_ref_12_09), + .Inter_ref_00_10(Inter_ref_00_10), + .Inter_ref_01_10(Inter_ref_01_10), + .Inter_ref_02_10(Inter_ref_02_10), + .Inter_ref_03_10(Inter_ref_03_10), + .Inter_ref_04_10(Inter_ref_04_10), + .Inter_ref_05_10(Inter_ref_05_10), + .Inter_ref_06_10(Inter_ref_06_10), + .Inter_ref_07_10(Inter_ref_07_10), + .Inter_ref_08_10(Inter_ref_08_10), + .Inter_ref_09_10(Inter_ref_09_10), + .Inter_ref_10_10(Inter_ref_10_10), + .Inter_ref_11_10(Inter_ref_11_10), + .Inter_ref_12_10(Inter_ref_12_10), + .Inter_ref_00_11(Inter_ref_00_11), + .Inter_ref_01_11(Inter_ref_01_11), + .Inter_ref_02_11(Inter_ref_02_11), + .Inter_ref_03_11(Inter_ref_03_11), + .Inter_ref_04_11(Inter_ref_04_11), + .Inter_ref_05_11(Inter_ref_05_11), + .Inter_ref_06_11(Inter_ref_06_11), + .Inter_ref_07_11(Inter_ref_07_11), + .Inter_ref_08_11(Inter_ref_08_11), + .Inter_ref_09_11(Inter_ref_09_11), + .Inter_ref_10_11(Inter_ref_10_11), + .Inter_ref_11_11(Inter_ref_11_11), + .Inter_ref_12_11(Inter_ref_12_11), + .Inter_ref_00_12(Inter_ref_00_12), + .Inter_ref_01_12(Inter_ref_01_12), + .Inter_ref_02_12(Inter_ref_02_12), + .Inter_ref_03_12(Inter_ref_03_12), + .Inter_ref_04_12(Inter_ref_04_12), + .Inter_ref_05_12(Inter_ref_05_12), + .Inter_ref_06_12(Inter_ref_06_12), + .Inter_ref_07_12(Inter_ref_07_12), + .Inter_ref_08_12(Inter_ref_08_12), + .Inter_ref_09_12(Inter_ref_09_12), + .Inter_ref_10_12(Inter_ref_10_12), + .Inter_ref_11_12(Inter_ref_11_12), + .Inter_ref_12_12(Inter_ref_12_12) + ); + Inter_pred_sliding_window Inter_pred_sliding_window ( + .IsInterLuma(IsInterLuma), + .IsInterChroma(IsInterChroma), + .Is_InterChromaCopy(Is_InterChromaCopy), + .mv_below8x8_curr(mv_below8x8_curr), + .pos_FracL(pos_FracL), + .blk4x4_rec_counter_1to0(blk4x4_rec_counter[1:0]), + .blk4x4_inter_calculate_counter(blk4x4_inter_calculate_counter), + .Inter_ref_00_00(Inter_ref_00_00), + .Inter_ref_01_00(Inter_ref_01_00), + .Inter_ref_02_00(Inter_ref_02_00), + .Inter_ref_03_00(Inter_ref_03_00), + .Inter_ref_04_00(Inter_ref_04_00), + .Inter_ref_05_00(Inter_ref_05_00), + .Inter_ref_06_00(Inter_ref_06_00), + .Inter_ref_07_00(Inter_ref_07_00), + .Inter_ref_08_00(Inter_ref_08_00), + .Inter_ref_09_00(Inter_ref_09_00), + .Inter_ref_10_00(Inter_ref_10_00), + .Inter_ref_11_00(Inter_ref_11_00), + .Inter_ref_12_00(Inter_ref_12_00), + .Inter_ref_00_01(Inter_ref_00_01), + .Inter_ref_01_01(Inter_ref_01_01), + .Inter_ref_02_01(Inter_ref_02_01), + .Inter_ref_03_01(Inter_ref_03_01), + .Inter_ref_04_01(Inter_ref_04_01), + .Inter_ref_05_01(Inter_ref_05_01), + .Inter_ref_06_01(Inter_ref_06_01), + .Inter_ref_07_01(Inter_ref_07_01), + .Inter_ref_08_01(Inter_ref_08_01), + .Inter_ref_09_01(Inter_ref_09_01), + .Inter_ref_10_01(Inter_ref_10_01), + .Inter_ref_11_01(Inter_ref_11_01), + .Inter_ref_12_01(Inter_ref_12_01), + .Inter_ref_00_02(Inter_ref_00_02), + .Inter_ref_01_02(Inter_ref_01_02), + .Inter_ref_02_02(Inter_ref_02_02), + .Inter_ref_03_02(Inter_ref_03_02), + .Inter_ref_04_02(Inter_ref_04_02), + .Inter_ref_05_02(Inter_ref_05_02), + .Inter_ref_06_02(Inter_ref_06_02), + .Inter_ref_07_02(Inter_ref_07_02), + .Inter_ref_08_02(Inter_ref_08_02), + .Inter_ref_09_02(Inter_ref_09_02), + .Inter_ref_10_02(Inter_ref_10_02), + .Inter_ref_11_02(Inter_ref_11_02), + .Inter_ref_12_02(Inter_ref_12_02), + .Inter_ref_00_03(Inter_ref_00_03), + .Inter_ref_01_03(Inter_ref_01_03), + .Inter_ref_02_03(Inter_ref_02_03), + .Inter_ref_03_03(Inter_ref_03_03), + .Inter_ref_04_03(Inter_ref_04_03), + .Inter_ref_05_03(Inter_ref_05_03), + .Inter_ref_06_03(Inter_ref_06_03), + .Inter_ref_07_03(Inter_ref_07_03), + .Inter_ref_08_03(Inter_ref_08_03), + .Inter_ref_09_03(Inter_ref_09_03), + .Inter_ref_10_03(Inter_ref_10_03), + .Inter_ref_11_03(Inter_ref_11_03), + .Inter_ref_12_03(Inter_ref_12_03), + .Inter_ref_00_04(Inter_ref_00_04), + .Inter_ref_01_04(Inter_ref_01_04), + .Inter_ref_02_04(Inter_ref_02_04), + .Inter_ref_03_04(Inter_ref_03_04), + .Inter_ref_04_04(Inter_ref_04_04), + .Inter_ref_05_04(Inter_ref_05_04), + .Inter_ref_06_04(Inter_ref_06_04), + .Inter_ref_07_04(Inter_ref_07_04), + .Inter_ref_08_04(Inter_ref_08_04), + .Inter_ref_09_04(Inter_ref_09_04), + .Inter_ref_10_04(Inter_ref_10_04), + .Inter_ref_11_04(Inter_ref_11_04), + .Inter_ref_12_04(Inter_ref_12_04), + .Inter_ref_00_05(Inter_ref_00_05), + .Inter_ref_01_05(Inter_ref_01_05), + .Inter_ref_02_05(Inter_ref_02_05), + .Inter_ref_03_05(Inter_ref_03_05), + .Inter_ref_04_05(Inter_ref_04_05), + .Inter_ref_05_05(Inter_ref_05_05), + .Inter_ref_06_05(Inter_ref_06_05), + .Inter_ref_07_05(Inter_ref_07_05), + .Inter_ref_08_05(Inter_ref_08_05), + .Inter_ref_09_05(Inter_ref_09_05), + .Inter_ref_10_05(Inter_ref_10_05), + .Inter_ref_11_05(Inter_ref_11_05), + .Inter_ref_12_05(Inter_ref_12_05), + .Inter_ref_00_06(Inter_ref_00_06), + .Inter_ref_01_06(Inter_ref_01_06), + .Inter_ref_02_06(Inter_ref_02_06), + .Inter_ref_03_06(Inter_ref_03_06), + .Inter_ref_04_06(Inter_ref_04_06), + .Inter_ref_05_06(Inter_ref_05_06), + .Inter_ref_06_06(Inter_ref_06_06), + .Inter_ref_07_06(Inter_ref_07_06), + .Inter_ref_08_06(Inter_ref_08_06), + .Inter_ref_09_06(Inter_ref_09_06), + .Inter_ref_10_06(Inter_ref_10_06), + .Inter_ref_11_06(Inter_ref_11_06), + .Inter_ref_12_06(Inter_ref_12_06), + .Inter_ref_00_07(Inter_ref_00_07), + .Inter_ref_01_07(Inter_ref_01_07), + .Inter_ref_02_07(Inter_ref_02_07), + .Inter_ref_03_07(Inter_ref_03_07), + .Inter_ref_04_07(Inter_ref_04_07), + .Inter_ref_05_07(Inter_ref_05_07), + .Inter_ref_06_07(Inter_ref_06_07), + .Inter_ref_07_07(Inter_ref_07_07), + .Inter_ref_08_07(Inter_ref_08_07), + .Inter_ref_09_07(Inter_ref_09_07), + .Inter_ref_10_07(Inter_ref_10_07), + .Inter_ref_11_07(Inter_ref_11_07), + .Inter_ref_12_07(Inter_ref_12_07), + .Inter_ref_00_08(Inter_ref_00_08), + .Inter_ref_01_08(Inter_ref_01_08), + .Inter_ref_02_08(Inter_ref_02_08), + .Inter_ref_03_08(Inter_ref_03_08), + .Inter_ref_04_08(Inter_ref_04_08), + .Inter_ref_05_08(Inter_ref_05_08), + .Inter_ref_06_08(Inter_ref_06_08), + .Inter_ref_07_08(Inter_ref_07_08), + .Inter_ref_08_08(Inter_ref_08_08), + .Inter_ref_09_08(Inter_ref_09_08), + .Inter_ref_10_08(Inter_ref_10_08), + .Inter_ref_11_08(Inter_ref_11_08), + .Inter_ref_12_08(Inter_ref_12_08), + .Inter_ref_00_09(Inter_ref_00_09), + .Inter_ref_01_09(Inter_ref_01_09), + .Inter_ref_02_09(Inter_ref_02_09), + .Inter_ref_03_09(Inter_ref_03_09), + .Inter_ref_04_09(Inter_ref_04_09), + .Inter_ref_05_09(Inter_ref_05_09), + .Inter_ref_06_09(Inter_ref_06_09), + .Inter_ref_07_09(Inter_ref_07_09), + .Inter_ref_08_09(Inter_ref_08_09), + .Inter_ref_09_09(Inter_ref_09_09), + .Inter_ref_10_09(Inter_ref_10_09), + .Inter_ref_11_09(Inter_ref_11_09), + .Inter_ref_12_09(Inter_ref_12_09), + .Inter_ref_00_10(Inter_ref_00_10), + .Inter_ref_01_10(Inter_ref_01_10), + .Inter_ref_02_10(Inter_ref_02_10), + .Inter_ref_03_10(Inter_ref_03_10), + .Inter_ref_04_10(Inter_ref_04_10), + .Inter_ref_05_10(Inter_ref_05_10), + .Inter_ref_06_10(Inter_ref_06_10), + .Inter_ref_07_10(Inter_ref_07_10), + .Inter_ref_08_10(Inter_ref_08_10), + .Inter_ref_09_10(Inter_ref_09_10), + .Inter_ref_10_10(Inter_ref_10_10), + .Inter_ref_11_10(Inter_ref_11_10), + .Inter_ref_12_10(Inter_ref_12_10), + .Inter_ref_00_11(Inter_ref_00_11), + .Inter_ref_01_11(Inter_ref_01_11), + .Inter_ref_02_11(Inter_ref_02_11), + .Inter_ref_03_11(Inter_ref_03_11), + .Inter_ref_04_11(Inter_ref_04_11), + .Inter_ref_05_11(Inter_ref_05_11), + .Inter_ref_06_11(Inter_ref_06_11), + .Inter_ref_07_11(Inter_ref_07_11), + .Inter_ref_08_11(Inter_ref_08_11), + .Inter_ref_09_11(Inter_ref_09_11), + .Inter_ref_10_11(Inter_ref_10_11), + .Inter_ref_11_11(Inter_ref_11_11), + .Inter_ref_12_11(Inter_ref_12_11), + .Inter_ref_00_12(Inter_ref_00_12), + .Inter_ref_01_12(Inter_ref_01_12), + .Inter_ref_02_12(Inter_ref_02_12), + .Inter_ref_03_12(Inter_ref_03_12), + .Inter_ref_04_12(Inter_ref_04_12), + .Inter_ref_05_12(Inter_ref_05_12), + .Inter_ref_06_12(Inter_ref_06_12), + .Inter_ref_07_12(Inter_ref_07_12), + .Inter_ref_08_12(Inter_ref_08_12), + .Inter_ref_09_12(Inter_ref_09_12), + .Inter_ref_10_12(Inter_ref_10_12), + .Inter_ref_11_12(Inter_ref_11_12), + .Inter_ref_12_12(Inter_ref_12_12), + + .Inter_pix_copy0(Inter_pix_copy0), + .Inter_pix_copy1(Inter_pix_copy1), + .Inter_pix_copy2(Inter_pix_copy2), + .Inter_pix_copy3(Inter_pix_copy3), + .Inter_H_window_0_0(Inter_H_window_0_0), + .Inter_H_window_1_0(Inter_H_window_1_0), + .Inter_H_window_2_0(Inter_H_window_2_0), + .Inter_H_window_3_0(Inter_H_window_3_0), + .Inter_H_window_4_0(Inter_H_window_4_0), + .Inter_H_window_5_0(Inter_H_window_5_0), + .Inter_H_window_0_1(Inter_H_window_0_1), + .Inter_H_window_1_1(Inter_H_window_1_1), + .Inter_H_window_2_1(Inter_H_window_2_1), + .Inter_H_window_3_1(Inter_H_window_3_1), + .Inter_H_window_4_1(Inter_H_window_4_1), + .Inter_H_window_5_1(Inter_H_window_5_1), + .Inter_H_window_0_2(Inter_H_window_0_2), + .Inter_H_window_1_2(Inter_H_window_1_2), + .Inter_H_window_2_2(Inter_H_window_2_2), + .Inter_H_window_3_2(Inter_H_window_3_2), + .Inter_H_window_4_2(Inter_H_window_4_2), + .Inter_H_window_5_2(Inter_H_window_5_2), + .Inter_H_window_0_3(Inter_H_window_0_3), + .Inter_H_window_1_3(Inter_H_window_1_3), + .Inter_H_window_2_3(Inter_H_window_2_3), + .Inter_H_window_3_3(Inter_H_window_3_3), + .Inter_H_window_4_3(Inter_H_window_4_3), + .Inter_H_window_5_3(Inter_H_window_5_3), + .Inter_H_window_0_4(Inter_H_window_0_4), + .Inter_H_window_1_4(Inter_H_window_1_4), + .Inter_H_window_2_4(Inter_H_window_2_4), + .Inter_H_window_3_4(Inter_H_window_3_4), + .Inter_H_window_4_4(Inter_H_window_4_4), + .Inter_H_window_5_4(Inter_H_window_5_4), + .Inter_H_window_0_5(Inter_H_window_0_5), + .Inter_H_window_1_5(Inter_H_window_1_5), + .Inter_H_window_2_5(Inter_H_window_2_5), + .Inter_H_window_3_5(Inter_H_window_3_5), + .Inter_H_window_4_5(Inter_H_window_4_5), + .Inter_H_window_5_5(Inter_H_window_5_5), + .Inter_H_window_0_6(Inter_H_window_0_6), + .Inter_H_window_1_6(Inter_H_window_1_6), + .Inter_H_window_2_6(Inter_H_window_2_6), + .Inter_H_window_3_6(Inter_H_window_3_6), + .Inter_H_window_4_6(Inter_H_window_4_6), + .Inter_H_window_5_6(Inter_H_window_5_6), + .Inter_H_window_0_7(Inter_H_window_0_7), + .Inter_H_window_1_7(Inter_H_window_1_7), + .Inter_H_window_2_7(Inter_H_window_2_7), + .Inter_H_window_3_7(Inter_H_window_3_7), + .Inter_H_window_4_7(Inter_H_window_4_7), + .Inter_H_window_5_7(Inter_H_window_5_7), + .Inter_H_window_0_8(Inter_H_window_0_8), + .Inter_H_window_1_8(Inter_H_window_1_8), + .Inter_H_window_2_8(Inter_H_window_2_8), + .Inter_H_window_3_8(Inter_H_window_3_8), + .Inter_H_window_4_8(Inter_H_window_4_8), + .Inter_H_window_5_8(Inter_H_window_5_8), + .Inter_V_window_0(Inter_V_window_0), + .Inter_V_window_1(Inter_V_window_1), + .Inter_V_window_2(Inter_V_window_2), + .Inter_V_window_3(Inter_V_window_3), + .Inter_V_window_4(Inter_V_window_4), + .Inter_V_window_5(Inter_V_window_5), + .Inter_V_window_6(Inter_V_window_6), + .Inter_V_window_7(Inter_V_window_7), + .Inter_V_window_8(Inter_V_window_8), + .Inter_C_window_0_0(Inter_C_window_0_0), + .Inter_C_window_1_0(Inter_C_window_1_0), + .Inter_C_window_2_0(Inter_C_window_2_0), + .Inter_C_window_0_1(Inter_C_window_0_1), + .Inter_C_window_1_1(Inter_C_window_1_1), + .Inter_C_window_2_1(Inter_C_window_2_1), + .Inter_C_window_0_2(Inter_C_window_0_2), + .Inter_C_window_1_2(Inter_C_window_1_2), + .Inter_C_window_2_2(Inter_C_window_2_2), + .Inter_bi_window_0(Inter_bi_window_0), + .Inter_bi_window_1(Inter_bi_window_1), + .Inter_bi_window_2(Inter_bi_window_2), + .Inter_bi_window_3(Inter_bi_window_3) + ); + + Inter_pred_LPE Inter_pred_LPE ( + .clk(clk), + .reset_n(reset_n), + .pos_FracL(pos_FracL), + .IsInterLuma(IsInterLuma), + .blk4x4_inter_calculate_counter(blk4x4_inter_calculate_counter), + .Inter_H_window_0_0(Inter_H_window_0_0), + .Inter_H_window_1_0(Inter_H_window_1_0), + .Inter_H_window_2_0(Inter_H_window_2_0), + .Inter_H_window_3_0(Inter_H_window_3_0), + .Inter_H_window_4_0(Inter_H_window_4_0), + .Inter_H_window_5_0(Inter_H_window_5_0), + .Inter_H_window_0_1(Inter_H_window_0_1), + .Inter_H_window_1_1(Inter_H_window_1_1), + .Inter_H_window_2_1(Inter_H_window_2_1), + .Inter_H_window_3_1(Inter_H_window_3_1), + .Inter_H_window_4_1(Inter_H_window_4_1), + .Inter_H_window_5_1(Inter_H_window_5_1), + .Inter_H_window_0_2(Inter_H_window_0_2), + .Inter_H_window_1_2(Inter_H_window_1_2), + .Inter_H_window_2_2(Inter_H_window_2_2), + .Inter_H_window_3_2(Inter_H_window_3_2), + .Inter_H_window_4_2(Inter_H_window_4_2), + .Inter_H_window_5_2(Inter_H_window_5_2), + .Inter_H_window_0_3(Inter_H_window_0_3), + .Inter_H_window_1_3(Inter_H_window_1_3), + .Inter_H_window_2_3(Inter_H_window_2_3), + .Inter_H_window_3_3(Inter_H_window_3_3), + .Inter_H_window_4_3(Inter_H_window_4_3), + .Inter_H_window_5_3(Inter_H_window_5_3), + .Inter_H_window_0_4(Inter_H_window_0_4), + .Inter_H_window_1_4(Inter_H_window_1_4), + .Inter_H_window_2_4(Inter_H_window_2_4), + .Inter_H_window_3_4(Inter_H_window_3_4), + .Inter_H_window_4_4(Inter_H_window_4_4), + .Inter_H_window_5_4(Inter_H_window_5_4), + .Inter_H_window_0_5(Inter_H_window_0_5), + .Inter_H_window_1_5(Inter_H_window_1_5), + .Inter_H_window_2_5(Inter_H_window_2_5), + .Inter_H_window_3_5(Inter_H_window_3_5), + .Inter_H_window_4_5(Inter_H_window_4_5), + .Inter_H_window_5_5(Inter_H_window_5_5), + .Inter_H_window_0_6(Inter_H_window_0_6), + .Inter_H_window_1_6(Inter_H_window_1_6), + .Inter_H_window_2_6(Inter_H_window_2_6), + .Inter_H_window_3_6(Inter_H_window_3_6), + .Inter_H_window_4_6(Inter_H_window_4_6), + .Inter_H_window_5_6(Inter_H_window_5_6), + .Inter_H_window_0_7(Inter_H_window_0_7), + .Inter_H_window_1_7(Inter_H_window_1_7), + .Inter_H_window_2_7(Inter_H_window_2_7), + .Inter_H_window_3_7(Inter_H_window_3_7), + .Inter_H_window_4_7(Inter_H_window_4_7), + .Inter_H_window_5_7(Inter_H_window_5_7), + .Inter_H_window_0_8(Inter_H_window_0_8), + .Inter_H_window_1_8(Inter_H_window_1_8), + .Inter_H_window_2_8(Inter_H_window_2_8), + .Inter_H_window_3_8(Inter_H_window_3_8), + .Inter_H_window_4_8(Inter_H_window_4_8), + .Inter_H_window_5_8(Inter_H_window_5_8), + .Inter_V_window_0(Inter_V_window_0), + .Inter_V_window_1(Inter_V_window_1), + .Inter_V_window_2(Inter_V_window_2), + .Inter_V_window_3(Inter_V_window_3), + .Inter_V_window_4(Inter_V_window_4), + .Inter_V_window_5(Inter_V_window_5), + .Inter_V_window_6(Inter_V_window_6), + .Inter_V_window_7(Inter_V_window_7), + .Inter_V_window_8(Inter_V_window_8), + .Inter_bi_window_0(Inter_bi_window_0), + .Inter_bi_window_1(Inter_bi_window_1), + .Inter_bi_window_2(Inter_bi_window_2), + .Inter_bi_window_3(Inter_bi_window_3), + + .LPE0_out(LPE0_out), + .LPE1_out(LPE1_out), + .LPE2_out(LPE2_out), + .LPE3_out(LPE3_out) + ); + Inter_pred_CPE Inter_pred_CPE ( + .xFracC(xFracC), + .yFracC(yFracC), + .Inter_C_window_0_0(Inter_C_window_0_0), + .Inter_C_window_1_0(Inter_C_window_1_0), + .Inter_C_window_2_0(Inter_C_window_2_0), + .Inter_C_window_0_1(Inter_C_window_0_1), + .Inter_C_window_1_1(Inter_C_window_1_1), + .Inter_C_window_2_1(Inter_C_window_2_1), + .Inter_C_window_0_2(Inter_C_window_0_2), + .Inter_C_window_1_2(Inter_C_window_1_2), + .Inter_C_window_2_2(Inter_C_window_2_2), + .CPE0_out(CPE0_out), + .CPE1_out(CPE1_out), + .CPE2_out(CPE2_out), + .CPE3_out(CPE3_out) + ); +endmodule + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/Intra4x4_PredMode_decoding.v b/demo_chip_rtl/rtl/nova/tags/Start/src/Intra4x4_PredMode_decoding.v new file mode 100644 index 0000000..bcc79a1 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/Intra4x4_PredMode_decoding.v @@ -0,0 +1,333 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : Intra4x4_PredMode_decoding.v +// Generated : May 31, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Decoding the prediction mode for Intra4x4 +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module Intra4x4_PredMode_decoding (clk,reset_n,mb_pred_state,luma4x4BlkIdx,mb_num_h,mb_num_v, + MBTypeGen_mbAddrA,MBTypeGen_mbAddrB_reg,constrained_intra_pred_flag, + rem_intra4x4_pred_mode,prev_intra4x4_pred_mode_flag,Intra4x4PredMode_mbAddrB_dout, + + Intra4x4PredMode_CurrMb, + Intra4x4PredMode_mbAddrB_cs_n,Intra4x4PredMode_mbAddrB_wr_n,Intra4x4PredMode_mbAddrB_rd_addr, + Intra4x4PredMode_mbAddrB_wr_addr,Intra4x4PredMode_mbAddrB_din + ); + input clk,reset_n; + input [2:0] mb_pred_state; + input [3:0] luma4x4BlkIdx; + input [3:0] mb_num_h,mb_num_v; + input [1:0] MBTypeGen_mbAddrA; + input [21:0] MBTypeGen_mbAddrB_reg; + input constrained_intra_pred_flag; + input [2:0] rem_intra4x4_pred_mode; + input prev_intra4x4_pred_mode_flag; + input [15:0] Intra4x4PredMode_mbAddrB_dout; + //input [8:0] pic_num; + + output [63:0] Intra4x4PredMode_CurrMb; + output Intra4x4PredMode_mbAddrB_cs_n,Intra4x4PredMode_mbAddrB_wr_n; + output [3:0] Intra4x4PredMode_mbAddrB_rd_addr,Intra4x4PredMode_mbAddrB_wr_addr; + output [15:0] Intra4x4PredMode_mbAddrB_din; + + reg Intra4x4PredMode_mbAddrB_cs_n,Intra4x4PredMode_mbAddrB_wr_n; + reg [3:0] Intra4x4PredMode_mbAddrB_rd_addr,Intra4x4PredMode_mbAddrB_wr_addr; + reg [15:0] Intra4x4PredMode_mbAddrB_din; + + wire mbAddrA_availability; + wire mbAddrB_availability; + wire mbAddrA; + wire mbAddrB; + wire [3:0] predIntra4x4PredMode; //prediction mode obtained at `prev_intra4x4_pred_mode_flag_s + reg dcOnlyPredictionFlag; + reg [15:0] Intra4x4PredMode_mbAddrA; + reg [63:0] Intra4x4PredMode_CurrMb; + reg [3:0] Intra4x4PredModeA,Intra4x4PredModeB; + + reg [3:0] rem_Intra4x4PredMode; //prediction mode obtained at `rem_intra4x4_pred_mode_s + reg [3:0] predIntra4x4PredMode_reg; //the reg value of predIntra4x4PredMode + + + reg [1:0] MBTypeGen_mbAddrB; + always @ (mb_num_h or MBTypeGen_mbAddrB_reg) + case (mb_num_h) + 0 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[1:0]; + 1 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[3:2]; + 2 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[5:4]; + 3 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[7:6]; + 4 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[9:8]; + 5 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[11:10]; + 6 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[13:12]; + 7 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[15:14]; + 8 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[17:16]; + 9 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[19:18]; + 10:MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[21:20]; + default:MBTypeGen_mbAddrB <= 0; + endcase + + //neighboring block decoding for Intra4x4 prediction mode,NO mapping from Blk4x4 order --> raster order + assign mbAddrA_availability = (luma4x4BlkIdx == 0 || luma4x4BlkIdx == 2 + || luma4x4BlkIdx == 8 || luma4x4BlkIdx == 10)? ((mb_num_h == 0)? 1'b0:1'b1):1'b1; + + assign mbAddrB_availability = (luma4x4BlkIdx == 0 || luma4x4BlkIdx == 1 + || luma4x4BlkIdx == 4 || luma4x4BlkIdx == 5)? ((mb_num_v == 0)? 1'b0:1'b1):1'b1; + + assign mbAddrA = (luma4x4BlkIdx == 0 || luma4x4BlkIdx == 2 || luma4x4BlkIdx == 8 + || luma4x4BlkIdx == 10)? 1'b0:1'b1; //0:left MB;1:curr MB + + assign mbAddrB = (luma4x4BlkIdx == 0 || luma4x4BlkIdx == 1 || luma4x4BlkIdx == 4 + || luma4x4BlkIdx == 5)? 1'b0:1'b1; //0:upper MB;1:curr MB + + //dcOnlyPredictionFlag + always @ (mb_pred_state or mbAddrA_availability or mbAddrB_availability or mbAddrA or mbAddrB or + MBTypeGen_mbAddrA or MBTypeGen_mbAddrB or constrained_intra_pred_flag) + if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s) + begin + if (mbAddrA_availability == 0) + dcOnlyPredictionFlag <= 1; + else if (mbAddrB_availability == 0) + dcOnlyPredictionFlag <= 1; + else if (mbAddrA == 0 && MBTypeGen_mbAddrA < 2 && constrained_intra_pred_flag == 1) + dcOnlyPredictionFlag <= 1; + else if (mbAddrB == 0 && MBTypeGen_mbAddrB < 2 && constrained_intra_pred_flag == 1) + dcOnlyPredictionFlag <= 1; + else + dcOnlyPredictionFlag <= 0; + end + else + dcOnlyPredictionFlag <= 0; + //Intra4x4PredModeA + always @ (mb_pred_state or dcOnlyPredictionFlag or mbAddrA or mbAddrA_availability or MBTypeGen_mbAddrA + or Intra4x4PredMode_mbAddrA or Intra4x4PredMode_CurrMb or luma4x4BlkIdx) + if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s) + begin + if (dcOnlyPredictionFlag == 1) + Intra4x4PredModeA <= 2; + else if (mbAddrA_availability == 1 && mbAddrA == 0 && MBTypeGen_mbAddrA != `MB_addrA_addrB_Intra4x4)//not coded in Intra4x4 + Intra4x4PredModeA <= 2; + else + case (luma4x4BlkIdx) + 0 :Intra4x4PredModeA <= Intra4x4PredMode_mbAddrA[3:0]; + 1 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[3:0]; + 2 :Intra4x4PredModeA <= Intra4x4PredMode_mbAddrA[7:4]; + 3 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[11:8]; + 4 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[7:4]; + 5 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[19:16]; + 6 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[15:12]; + 7 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[27:24]; + 8 :Intra4x4PredModeA <= Intra4x4PredMode_mbAddrA[11:8]; + 9 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[35:32]; + 10:Intra4x4PredModeA <= Intra4x4PredMode_mbAddrA[15:12]; + 11:Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[43:40]; + 12:Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[39:36]; + 13:Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[51:48]; + 14:Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[47:44]; + 15:Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[59:56]; + endcase + end + else + Intra4x4PredModeA <= 0; + //Intra4x4PredModeB + always @ (mb_pred_state or dcOnlyPredictionFlag or mbAddrB or mbAddrB_availability or MBTypeGen_mbAddrB + or Intra4x4PredMode_mbAddrB_dout or Intra4x4PredMode_CurrMb or luma4x4BlkIdx) + if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s) + begin + if (dcOnlyPredictionFlag == 1) + Intra4x4PredModeB <= 2; + else if (mbAddrB_availability == 1 && mbAddrB == 0 && MBTypeGen_mbAddrB != `MB_addrA_addrB_Intra4x4) //not coded in Intra4x4 + Intra4x4PredModeB <= 2; + else + case (luma4x4BlkIdx) + 0 :Intra4x4PredModeB <= Intra4x4PredMode_mbAddrB_dout[15:12]; + 1 :Intra4x4PredModeB <= Intra4x4PredMode_mbAddrB_dout[11:8]; + 2 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[3:0]; + 3 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[7:4]; + 4 :Intra4x4PredModeB <= Intra4x4PredMode_mbAddrB_dout[7:4]; + 5 :Intra4x4PredModeB <= Intra4x4PredMode_mbAddrB_dout[3:0]; + 6 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[19:16]; + 7 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[23:20]; + 8 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[11:8]; + 9 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[15:12]; + 10:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[35:32]; + 11:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[39:36]; + 12:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[27:24]; + 13:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[31:28]; + 14:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[51:48]; + 15:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[55:52]; + endcase + end + else + Intra4x4PredModeB <= 0; + //obtain prediction mode at prev_intra4x4_pred_mode_flag_s + assign predIntra4x4PredMode = (Intra4x4PredModeA < Intra4x4PredModeB)? Intra4x4PredModeA:Intra4x4PredModeB; + always @ (posedge clk) + if (reset_n == 0) + predIntra4x4PredMode_reg <= 0; + else if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s && prev_intra4x4_pred_mode_flag == 0) + predIntra4x4PredMode_reg <= predIntra4x4PredMode; + //obtain prediction mode at rem_intra4x4_pred_mode_s + always @ (mb_pred_state or rem_intra4x4_pred_mode or predIntra4x4PredMode_reg) + if (mb_pred_state == `rem_intra4x4_pred_mode_s) + rem_Intra4x4PredMode <= ({1'b0,rem_intra4x4_pred_mode} < predIntra4x4PredMode_reg)? + {1'b0,rem_intra4x4_pred_mode}:(rem_intra4x4_pred_mode + 1); + else + rem_Intra4x4PredMode <= 0; + //----------------------------- + //Intra4x4PredMode_CurrMb write + //----------------------------- + always @ (posedge clk) + if (reset_n == 0) + Intra4x4PredMode_CurrMb <= 0; + else if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s && prev_intra4x4_pred_mode_flag == 1) + case (luma4x4BlkIdx) + 0 :Intra4x4PredMode_CurrMb[3:0] <= predIntra4x4PredMode; + 1 :Intra4x4PredMode_CurrMb[7:4] <= predIntra4x4PredMode; + 2 :Intra4x4PredMode_CurrMb[11:8] <= predIntra4x4PredMode; + 3 :Intra4x4PredMode_CurrMb[15:12] <= predIntra4x4PredMode; + 4 :Intra4x4PredMode_CurrMb[19:16] <= predIntra4x4PredMode; + 5 :Intra4x4PredMode_CurrMb[23:20] <= predIntra4x4PredMode; + 6 :Intra4x4PredMode_CurrMb[27:24] <= predIntra4x4PredMode; + 7 :Intra4x4PredMode_CurrMb[31:28] <= predIntra4x4PredMode; + 8 :Intra4x4PredMode_CurrMb[35:32] <= predIntra4x4PredMode; + 9 :Intra4x4PredMode_CurrMb[39:36] <= predIntra4x4PredMode; + 10 :Intra4x4PredMode_CurrMb[43:40] <= predIntra4x4PredMode; + 11 :Intra4x4PredMode_CurrMb[47:44] <= predIntra4x4PredMode; + 12 :Intra4x4PredMode_CurrMb[51:48] <= predIntra4x4PredMode; + 13 :Intra4x4PredMode_CurrMb[55:52] <= predIntra4x4PredMode; + 14 :Intra4x4PredMode_CurrMb[59:56] <= predIntra4x4PredMode; + 15 :Intra4x4PredMode_CurrMb[63:60] <= predIntra4x4PredMode; + endcase + else if (mb_pred_state == `rem_intra4x4_pred_mode_s) + case (luma4x4BlkIdx) + 0 :Intra4x4PredMode_CurrMb[3:0] <= rem_Intra4x4PredMode; + 1 :Intra4x4PredMode_CurrMb[7:4] <= rem_Intra4x4PredMode; + 2 :Intra4x4PredMode_CurrMb[11:8] <= rem_Intra4x4PredMode; + 3 :Intra4x4PredMode_CurrMb[15:12] <= rem_Intra4x4PredMode; + 4 :Intra4x4PredMode_CurrMb[19:16] <= rem_Intra4x4PredMode; + 5 :Intra4x4PredMode_CurrMb[23:20] <= rem_Intra4x4PredMode; + 6 :Intra4x4PredMode_CurrMb[27:24] <= rem_Intra4x4PredMode; + 7 :Intra4x4PredMode_CurrMb[31:28] <= rem_Intra4x4PredMode; + 8 :Intra4x4PredMode_CurrMb[35:32] <= rem_Intra4x4PredMode; + 9 :Intra4x4PredMode_CurrMb[39:36] <= rem_Intra4x4PredMode; + 10 :Intra4x4PredMode_CurrMb[43:40] <= rem_Intra4x4PredMode; + 11 :Intra4x4PredMode_CurrMb[47:44] <= rem_Intra4x4PredMode; + 12 :Intra4x4PredMode_CurrMb[51:48] <= rem_Intra4x4PredMode; + 13 :Intra4x4PredMode_CurrMb[55:52] <= rem_Intra4x4PredMode; + 14 :Intra4x4PredMode_CurrMb[59:56] <= rem_Intra4x4PredMode; + 15 :Intra4x4PredMode_CurrMb[63:60] <= rem_Intra4x4PredMode; + endcase + //------------------------------ + //Intra4x4PredMode_mbAddrA write + //------------------------------ + always @ (posedge clk) + if (reset_n == 0) + Intra4x4PredMode_mbAddrA <= 0; + else if (mb_num_h != 10) //mb_num_h == 10,no need to store mbAddrA + begin + if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s && prev_intra4x4_pred_mode_flag == 1) + case (luma4x4BlkIdx) + 5: Intra4x4PredMode_mbAddrA[3:0] <= predIntra4x4PredMode; + 7: Intra4x4PredMode_mbAddrA[7:4] <= predIntra4x4PredMode; + 13:Intra4x4PredMode_mbAddrA[11:8] <= predIntra4x4PredMode; + 15:Intra4x4PredMode_mbAddrA[15:12] <= predIntra4x4PredMode; + endcase + else if (mb_pred_state == `rem_intra4x4_pred_mode_s) + case (luma4x4BlkIdx) + 5: Intra4x4PredMode_mbAddrA[3:0] <= rem_Intra4x4PredMode; + 7: Intra4x4PredMode_mbAddrA[7:4] <= rem_Intra4x4PredMode; + 13:Intra4x4PredMode_mbAddrA[11:8] <= rem_Intra4x4PredMode; + 15:Intra4x4PredMode_mbAddrA[15:12] <= rem_Intra4x4PredMode; + endcase + end + //---------------------------------------- + //Intra4x4PredMode_mbAddrB RF read & write + //---------------------------------------- + always @ (reset_n or mb_num_v or mb_num_h or luma4x4BlkIdx or mb_pred_state or prev_intra4x4_pred_mode_flag + or Intra4x4PredMode_CurrMb or predIntra4x4PredMode or rem_Intra4x4PredMode) + if (reset_n == 0) + begin + Intra4x4PredMode_mbAddrB_cs_n <= 1; Intra4x4PredMode_mbAddrB_wr_n <= 1; + Intra4x4PredMode_mbAddrB_rd_addr <= 0; Intra4x4PredMode_mbAddrB_wr_addr <= 0; + Intra4x4PredMode_mbAddrB_din <= 0; + end + else if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s) + begin + Intra4x4PredMode_mbAddrB_cs_n <= 0; //read is always even if in cases as luma4x4BlkIdx = 2,3,6,7... + Intra4x4PredMode_mbAddrB_rd_addr <= mb_num_h; + if (prev_intra4x4_pred_mode_flag == 1 && luma4x4BlkIdx == 15 && mb_num_v != 8)//write is conditional when mb_num_v != 8 + begin + Intra4x4PredMode_mbAddrB_wr_n <= 0; + Intra4x4PredMode_mbAddrB_wr_addr <= mb_num_h; + Intra4x4PredMode_mbAddrB_din <= {Intra4x4PredMode_CurrMb[43:40], + Intra4x4PredMode_CurrMb[47:44],Intra4x4PredMode_CurrMb[59:56],predIntra4x4PredMode}; + end + else + begin + Intra4x4PredMode_mbAddrB_wr_n <= 1; + Intra4x4PredMode_mbAddrB_wr_addr <= 0; + Intra4x4PredMode_mbAddrB_din <= 0; + end + end + else if (mb_pred_state == `rem_intra4x4_pred_mode_s) + begin + Intra4x4PredMode_mbAddrB_cs_n <= 0; //read is always even if in cases as luma4x4BlkIdx = 2,3,6,7... + Intra4x4PredMode_mbAddrB_rd_addr <= mb_num_h; + if (luma4x4BlkIdx == 15 && mb_num_v != 8) //write is conditional when mb_num_v != 8 + begin + Intra4x4PredMode_mbAddrB_wr_n <= 0; + Intra4x4PredMode_mbAddrB_wr_addr <= mb_num_h; + Intra4x4PredMode_mbAddrB_din <= {Intra4x4PredMode_CurrMb[43:40], + Intra4x4PredMode_CurrMb[47:44],Intra4x4PredMode_CurrMb[59:56],rem_Intra4x4PredMode}; + end + else + begin + Intra4x4PredMode_mbAddrB_wr_n <= 1; + Intra4x4PredMode_mbAddrB_wr_addr <= 0; + Intra4x4PredMode_mbAddrB_din <= 0; + end + end + else + begin + Intra4x4PredMode_mbAddrB_cs_n <= 1; Intra4x4PredMode_mbAddrB_wr_n <= 1; + Intra4x4PredMode_mbAddrB_rd_addr <= 0; Intra4x4PredMode_mbAddrB_wr_addr <= 0; + Intra4x4PredMode_mbAddrB_din <= 0; + end + + /* + // synopsys translate_off + integer tracefile; + wire [6:0] mb_num; + assign mb_num = mb_num_v * 11 + mb_num_h; + + initial + begin + tracefile = $fopen("intra_4x4_trace.txt"); + end + always @ (posedge clk) + if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s && prev_intra4x4_pred_mode_flag == 1) + begin + $fdisplay (tracefile," Pic_num = %3d,MB_num = %3d,blkIdx = %3d,Intra4x4PredMode = %3d", + pic_num,mb_num,luma4x4BlkIdx,predIntra4x4PredMode); + if (luma4x4BlkIdx == 15) + $fdisplay (tracefile,"--------------------------------------------------------------------"); + end + else if (mb_pred_state == `rem_intra4x4_pred_mode_s) + begin + $fdisplay (tracefile," Pic_num = %3d,MB_num = %3d,blkIdx = %3d,Intra4x4PredMode = %3d", + pic_num,mb_num,luma4x4BlkIdx,rem_Intra4x4PredMode); + if (luma4x4BlkIdx == 15) + $fdisplay (tracefile,"--------------------------------------------------------------------"); + end + // synopsys translate_on + */ +endmodule \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/Intra_pred_PE.v b/demo_chip_rtl/rtl/nova/tags/Start/src/Intra_pred_PE.v new file mode 100644 index 0000000..9eeceec --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/Intra_pred_PE.v @@ -0,0 +1,1626 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : Intra_pred_PE.v +// Generated : Sep 19, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Processing Element for Intra prediction,PE0 ~ PE3 +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module Intra_pred_PE (clk,reset_n,mb_type_general,blk4x4_rec_counter,blk4x4_intra_calculate_counter, + Intra4x4_predmode,Intra16x16_predmode,Intra_chroma_predmode, + blkAddrA_availability,blkAddrB_availability,mbAddrA_availability,mbAddrB_availability, + + Intra_mbAddrA_window0,Intra_mbAddrA_window1,Intra_mbAddrA_window2,Intra_mbAddrA_window3, + Intra_mbAddrB_window0,Intra_mbAddrB_window1,Intra_mbAddrB_window2,Intra_mbAddrB_window3, + Intra_mbAddrC_window0,Intra_mbAddrC_window1,Intra_mbAddrC_window2,Intra_mbAddrC_window3, + Intra_mbAddrD_window, + + Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3, + Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7, + Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11, + Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15, + Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3, + Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7, + Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11, + Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15, + + blk4x4_pred_output0, blk4x4_pred_output1, blk4x4_pred_output2, + blk4x4_pred_output4, blk4x4_pred_output5, blk4x4_pred_output6, + blk4x4_pred_output8, blk4x4_pred_output9, blk4x4_pred_output10, + blk4x4_pred_output12,blk4x4_pred_output13,blk4x4_pred_output14, + + seed,b,c, + + PE0_out,PE1_out,PE2_out,PE3_out,PE0_sum_out,PE3_sum_out); + input clk,reset_n; + input [3:0] mb_type_general; + input [4:0] blk4x4_rec_counter; + input [2:0] blk4x4_intra_calculate_counter; + input [3:0] Intra4x4_predmode; + input [1:0] Intra16x16_predmode; + input [1:0] Intra_chroma_predmode; + input blkAddrA_availability; + input blkAddrB_availability; + input mbAddrA_availability; + input mbAddrB_availability; + input [15:0] Intra_mbAddrA_window0,Intra_mbAddrA_window1,Intra_mbAddrA_window2,Intra_mbAddrA_window3; + input [15:0] Intra_mbAddrB_window0,Intra_mbAddrB_window1,Intra_mbAddrB_window2,Intra_mbAddrB_window3; + input [15:0] Intra_mbAddrC_window0,Intra_mbAddrC_window1,Intra_mbAddrC_window2,Intra_mbAddrC_window3; + input [15:0] Intra_mbAddrD_window; + input [15:0] Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3; + input [15:0] Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7; + input [15:0] Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11; + input [15:0] Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15; + input [15:0] Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3; + input [15:0] Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7; + input [15:0] Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11; + input [15:0] Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15; + input [15:0] blk4x4_pred_output0, blk4x4_pred_output1, blk4x4_pred_output2; + input [15:0] blk4x4_pred_output4, blk4x4_pred_output5, blk4x4_pred_output6; + input [15:0] blk4x4_pred_output8, blk4x4_pred_output9, blk4x4_pred_output10; + input [15:0] blk4x4_pred_output12,blk4x4_pred_output13,blk4x4_pred_output14; + input [15:0] seed; + input [11:0] b,c; + + output [7:0] PE0_out; + output [7:0] PE1_out; + output [7:0] PE2_out; + output [7:0] PE3_out; + output [15:0] PE0_sum_out; //for store as 2nd-level seed + output [15:0] PE3_sum_out; //for store as 2nd-level seed + + reg [15:0] PE0_in0,PE0_in1,PE0_in2,PE0_in3; + reg PE0_IsShift; + reg PE0_IsStore; + reg PE0_IsClip; + reg PE0_full_bypass; + reg [4:0] PE0_round_value; + reg [2:0] PE0_shift_len; + + reg [15:0] PE1_in0,PE1_in1,PE1_in2,PE1_in3; + reg PE1_IsShift; + reg PE1_IsStore; + reg PE1_IsClip; + reg PE1_full_bypass; + reg [4:0] PE1_round_value; + reg [2:0] PE1_shift_len; + + reg [15:0] PE2_in0,PE2_in1,PE2_in2,PE2_in3; + reg PE2_IsShift; + reg PE2_IsStore; + reg PE2_IsClip; + reg PE2_full_bypass; + reg [4:0] PE2_round_value; + reg [2:0] PE2_shift_len; + + reg [15:0] PE3_in0,PE3_in1,PE3_in2,PE3_in3; + reg PE3_IsShift; + reg PE3_IsStore; + reg PE3_IsClip; + reg PE3_full_bypass; + reg [4:0] PE3_round_value; + reg [2:0] PE3_shift_len; + + wire [15:0] PE0_out_reg; + wire [15:0] PE1_out_reg; + wire [15:0] PE2_out_reg; + wire [15:0] PE3_out_reg; + + wire [15:0] PE0_sum_out; + wire [15:0] PE1_sum_out; + wire [15:0] PE2_sum_out; + wire [15:0] PE3_sum_out; + + wire [15:0] b_ext,c_ext; + assign b_ext = (b[11] == 1'b1)? {4'b1111,b}:{4'b0000,b}; + assign c_ext = (c[11] == 1'b1)? {4'b1111,c}:{4'b0000,c}; + + PE PE0 ( + .clk(clk), + .reset_n(reset_n), + .in0(PE0_in0), + .in1(PE0_in1), + .in2(PE0_in2), + .in3(PE0_in3), + .IsShift(PE0_IsShift), + .IsStore(PE0_IsStore), + .IsClip(PE0_IsClip), + .full_bypass(PE0_full_bypass), + .round_value(PE0_round_value), + .shift_len(PE0_shift_len), + .PE_out_reg(PE0_out_reg), + .PE_out(PE0_out), + .sum_out(PE0_sum_out) + ); + PE PE1 ( + .clk(clk), + .reset_n(reset_n), + .in0(PE1_in0), + .in1(PE1_in1), + .in2(PE1_in2), + .in3(PE1_in3), + .IsShift(PE1_IsShift), + .IsStore(PE1_IsStore), + .IsClip(PE1_IsClip), + .full_bypass(PE1_full_bypass), + .round_value(PE1_round_value), + .shift_len(PE1_shift_len), + .PE_out_reg(PE1_out_reg), + .PE_out(PE1_out), + .sum_out(PE1_sum_out) + ); + PE PE2 ( + .clk(clk), + .reset_n(reset_n), + .in0(PE2_in0), + .in1(PE2_in1), + .in2(PE2_in2), + .in3(PE2_in3), + .IsShift(PE2_IsShift), + .IsStore(PE2_IsStore), + .IsClip(PE2_IsClip), + .full_bypass(PE2_full_bypass), + .round_value(PE2_round_value), + .shift_len(PE2_shift_len), + .PE_out_reg(PE2_out_reg), + .PE_out(PE2_out), + .sum_out(PE2_sum_out) + ); + PE PE3 ( + .clk(clk), + .reset_n(reset_n), + .in0(PE3_in0), + .in1(PE3_in1), + .in2(PE3_in2), + .in3(PE3_in3), + .IsShift(PE3_IsShift), + .IsStore(PE3_IsStore), + .IsClip(PE3_IsClip), + .full_bypass(PE3_full_bypass), + .round_value(PE3_round_value), + .shift_len(PE3_shift_len), + .PE_out_reg(PE3_out_reg), + .PE_out(PE3_out), + .sum_out(PE3_sum_out) + ); + //---- + //PE0 | + //---- + always @ (mb_type_general or blk4x4_rec_counter or blk4x4_intra_calculate_counter + or Intra4x4_predmode or Intra16x16_predmode or Intra_chroma_predmode + or blkAddrA_availability or blkAddrB_availability or mbAddrA_availability or mbAddrB_availability + or Intra_mbAddrA_window0 or Intra_mbAddrA_window1 or Intra_mbAddrA_window2 + or Intra_mbAddrB_window0 or Intra_mbAddrB_window1 or Intra_mbAddrB_window2 or Intra_mbAddrB_window3 + or Intra_mbAddrD_window + or Intra_mbAddrA_reg0 or Intra_mbAddrA_reg1 or Intra_mbAddrA_reg2 or Intra_mbAddrA_reg3 + or Intra_mbAddrB_reg1 or Intra_mbAddrB_reg2 or Intra_mbAddrB_reg3 + or PE0_out_reg or PE1_out_reg or PE2_out_reg or PE3_out_reg + or blk4x4_pred_output4 or blk4x4_pred_output5 or blk4x4_pred_output8 + or blk4x4_pred_output9 or blk4x4_pred_output10 or blk4x4_pred_output12 + or seed or b_ext or c_ext) + //Intra 4x4 + if (mb_type_general[3:2] == 2'b11 && blk4x4_rec_counter < 16) + case (Intra4x4_predmode) + `Intra4x4_Vertical: + begin + case (blk4x4_intra_calculate_counter) + 4:PE0_in0 <= Intra_mbAddrB_window0; + 3:PE0_in0 <= Intra_mbAddrB_window1; + 2:PE0_in0 <= Intra_mbAddrB_window2; + 1:PE0_in0 <= Intra_mbAddrB_window3; + default:PE0_in0 <= 0; + endcase + PE0_in1 <= 0; PE0_in2 <= 0; PE0_in3 <= 0; + PE0_IsShift <= 0; PE0_IsStore <= 0; PE0_IsClip <= 0; + PE0_full_bypass <= 1; PE0_round_value <= 0; PE0_shift_len <= 0; + end + `Intra4x4_Horizontal: + begin + PE0_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window0:0; + PE0_in1 <= 0; PE0_in2 <= 0; PE0_in3 <= 0; + PE0_IsShift <= 0; PE0_IsStore <= 0; PE0_IsClip <= 0; + PE0_full_bypass <= 1; PE0_round_value <= 0; PE0_shift_len <= 0; + end + `Intra4x4_DC: + case (blk4x4_intra_calculate_counter) + 4: //A ~ D + begin + if (blkAddrB_availability == 1) + begin + PE0_in0 <= Intra_mbAddrB_window0; PE0_in1 <= Intra_mbAddrB_window1; + PE0_in2 <= Intra_mbAddrB_window2; PE0_in3 <= Intra_mbAddrB_window3; + PE0_IsStore <= 1'b1; PE0_full_bypass <= 1'b0; + end + else + begin + PE0_in0 <= 0; PE0_in1 <= 0; PE0_in2 <= 0; PE0_in3 <= 0; + PE0_IsStore <= 1'b0; PE0_full_bypass <= 1'b1; + end + PE0_IsShift <= 0; PE0_IsClip <= 0; + PE0_round_value <= 0; PE0_shift_len <= 0; + end + 3: + begin + case ({blkAddrB_availability,blkAddrA_availability}) + 2'b00: + begin + PE0_in0 <= 128; PE0_in1 <= 0; + PE0_full_bypass <= 1'b1; PE0_round_value <= 0; PE0_shift_len <= 0; + end + 2'b01,2'b10: + begin + PE0_in0 <= (blkAddrB_availability)? PE0_out_reg:0; + PE0_in1 <= (blkAddrA_availability)? PE1_out_reg:0; + PE0_full_bypass <= 1'b0; PE0_round_value <= 2; PE0_shift_len <= 2; + end + 2'b11: + begin + PE0_in0 <= PE0_out_reg; PE0_in1 <= PE1_out_reg; + PE0_full_bypass <= 1'b0; PE0_round_value <= 4; PE0_shift_len <= 3; + end + endcase + PE0_in2 <= 0; PE0_in3 <= 0; + PE0_IsStore <= 0; PE0_IsShift <= 0; PE0_IsClip <= 0; + end + default: + begin + PE0_in0 <= 0; PE0_in1 <= 0; PE0_in2 <= 0; PE0_in3 <= 0; + PE0_IsShift <= 0; PE0_IsStore <= 0; PE0_IsClip <= 0; + PE0_full_bypass <= 1; PE0_round_value <= 0; PE0_shift_len <= 0; + end + endcase + `Intra4x4_Diagonal_Down_Left: + begin + case (blk4x4_intra_calculate_counter) + 4:PE0_in0 <= Intra_mbAddrB_window0; + 3:PE0_in0 <= blk4x4_pred_output4; + 2:PE0_in0 <= blk4x4_pred_output8; + 1:PE0_in0 <= blk4x4_pred_output12; + default:PE0_in0 <= 0; + endcase + PE0_in1 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrB_window2:0; + PE0_in2 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrB_window1:0; + PE0_in3 <= 0; + PE0_IsShift <= (blk4x4_intra_calculate_counter == 4)? 1'b1:1'b0; + PE0_IsStore <= 1'b0; PE0_IsClip <= 1'b0; + PE0_full_bypass <= (blk4x4_intra_calculate_counter == 4)? 1'b0:1'b1; + PE0_round_value <= (blk4x4_intra_calculate_counter == 4)? 5'b00010:5'b0; // +2 + PE0_shift_len <= (blk4x4_intra_calculate_counter == 4)? 3'b010:3'b0; // >>2 + end + `Intra4x4_Diagonal_Down_Right: + begin + case (blk4x4_intra_calculate_counter) + 4:begin PE0_in0 <= Intra_mbAddrB_window0; PE0_in1 <= Intra_mbAddrA_window0; + PE0_in2 <= Intra_mbAddrD_window; end + 3:begin PE0_in0 <= Intra_mbAddrD_window; PE0_in1 <= Intra_mbAddrB_window1; + PE0_in2 <= Intra_mbAddrB_window0; end + 2:begin PE0_in0 <= Intra_mbAddrB_window0; PE0_in1 <= Intra_mbAddrB_window2; + PE0_in2 <= Intra_mbAddrB_window1; end + 1:begin PE0_in0 <= Intra_mbAddrB_window1; PE0_in1 <= Intra_mbAddrB_window3; + PE0_in2 <= Intra_mbAddrB_window2; end + default:begin PE0_in0 <= 0;PE0_in1 <= 0;PE0_in2 <= 0; end + endcase + PE0_in3 <= 0; + PE0_IsShift <= (blk4x4_intra_calculate_counter == 0)? 1'b0:1'b1; + PE0_IsStore <= 1'b0; PE0_IsClip <= 1'b0; PE0_full_bypass <= 1'b0; + PE0_round_value <= (blk4x4_intra_calculate_counter == 0)? 5'b0:5'b00010; // +2 + PE0_shift_len <= (blk4x4_intra_calculate_counter == 0)? 3'b0:3'b010; // >>2 + end + `Intra4x4_Vertical_Right: + begin + case (blk4x4_intra_calculate_counter) + 4:begin PE0_in0 <= Intra_mbAddrB_window0;PE0_in1 <= Intra_mbAddrD_window; end + 3:begin PE0_in0 <= Intra_mbAddrB_window0;PE0_in1 <= Intra_mbAddrB_window1;end + 2:begin PE0_in0 <= Intra_mbAddrB_window2;PE0_in1 <= Intra_mbAddrB_window1;end + 1:begin PE0_in0 <= Intra_mbAddrB_window2;PE0_in1 <= Intra_mbAddrB_window3;end + default:begin PE0_in0 <= 0;PE0_in1 <= 0; end + endcase + PE0_in2 <= 0; PE0_in3 <= 0; + PE0_IsShift <= 1'b0;PE0_IsStore <= 1'b0; PE0_IsClip <= 1'b0; PE0_full_bypass <= 1'b0; + PE0_round_value <= (blk4x4_intra_calculate_counter == 0)? 5'b0:5'b00001; // +1 + PE0_shift_len <= (blk4x4_intra_calculate_counter == 0)? 3'b0:3'b001; // >>1 + end + `Intra4x4_Horizontal_Down: + begin + case (blk4x4_intra_calculate_counter) + 4:begin PE0_in0 <= Intra_mbAddrA_window0;PE0_in1 <= Intra_mbAddrD_window; + PE0_in2 <= 0; + PE0_round_value <= 5'b00001; PE0_shift_len <= 3'b001;end + 3:begin PE0_in0 <= Intra_mbAddrA_window0;PE0_in1 <= Intra_mbAddrB_window0; + PE0_in2 <= Intra_mbAddrD_window; + PE0_round_value <= 5'b00010; PE0_shift_len <= 3'b010;end + 2:begin PE0_in0 <= Intra_mbAddrD_window; PE0_in1 <= Intra_mbAddrB_window1; + PE0_in2 <= Intra_mbAddrB_window0; + PE0_round_value <= 5'b00010; PE0_shift_len <= 3'b010;end + 1:begin PE0_in0 <= Intra_mbAddrB_window0;PE0_in1 <= Intra_mbAddrB_window2; + PE0_in2 <= Intra_mbAddrB_window1; + PE0_round_value <= 5'b00010; PE0_shift_len <= 3'b010;end + default:begin PE0_in0 <= 0;PE0_in1 <= 0;PE0_in2 <= 0; + PE0_round_value <= 0;PE0_shift_len <= 0; end + endcase + PE0_in3 <= 0; + PE0_IsShift <= (blk4x4_intra_calculate_counter == 3 || blk4x4_intra_calculate_counter == 2 + || blk4x4_intra_calculate_counter == 1)? 1'b1:1'b0; + PE0_IsStore <= 1'b0; PE0_IsClip <= 1'b0; PE0_full_bypass <= 1'b0; + end + `Intra4x4_Vertical_Left: + begin + case (blk4x4_intra_calculate_counter) + 4:PE0_in0 <= Intra_mbAddrB_window0; + 3:PE0_in0 <= blk4x4_pred_output8; + 2:PE0_in0 <= blk4x4_pred_output9; + 1:PE0_in0 <= blk4x4_pred_output10; + default:PE0_in0 <= 0; + endcase + PE0_in1 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrB_window1:0; + PE0_in2 <= 0; PE0_in3 <= 0; + PE0_IsShift <= 1'b0; PE0_IsStore <= 1'b0; PE0_IsClip <= 1'b0; + PE0_full_bypass <= (blk4x4_intra_calculate_counter == 4)? 1'b0:1'b1; + PE0_round_value <= (blk4x4_intra_calculate_counter == 4)? 5'b00001:5'b0; // +1 + PE0_shift_len <= (blk4x4_intra_calculate_counter == 4)? 3'b001:3'b0; // >>1 + end + `Intra4x4_Horizontal_Up: + begin + case (blk4x4_intra_calculate_counter) + 4:begin PE0_in0 <= Intra_mbAddrA_window0; PE0_in1 <= Intra_mbAddrA_window1; end + 3:begin PE0_in0 <= Intra_mbAddrA_window0; PE0_in1 <= Intra_mbAddrA_window2; end + 2:begin PE0_in0 <= blk4x4_pred_output4; PE0_in1 <= 0; end + 1:begin PE0_in0 <= blk4x4_pred_output5; PE0_in1 <= 0; end + default:begin PE0_in0 <= 0; PE0_in1 <= 0; end + endcase + PE0_in2 <= (blk4x4_intra_calculate_counter == 3)? Intra_mbAddrA_window1:0; + PE0_in3 <= 0; + PE0_IsShift <= (blk4x4_intra_calculate_counter == 3)? 1'b1:1'b0; + PE0_IsStore <= 1'b0; PE0_IsClip <= 1'b0; + PE0_full_bypass <= (blk4x4_intra_calculate_counter == 4 || + blk4x4_intra_calculate_counter == 3)? 1'b0:1'b1; + PE0_round_value <= (blk4x4_intra_calculate_counter == 4)? 5'd1: + (blk4x4_intra_calculate_counter == 3)? 5'd2:5'd0; + PE0_shift_len <= (blk4x4_intra_calculate_counter == 4)? 3'd1: + (blk4x4_intra_calculate_counter == 3)? 3'd2:3'd0; + end + default: + begin + PE0_in0 <= 0; PE0_in1 <= 0; PE0_in2 <= 0; PE0_in3 <= 0; + PE0_IsShift <= 0; PE0_IsStore <= 0; PE0_IsClip <= 0; + PE0_full_bypass <= 0; PE0_round_value <= 0; PE0_shift_len <= 0; + end + endcase + //Intra16x16 + else if (mb_type_general[3:2] == 2'b10 && blk4x4_rec_counter < 16) + case (Intra16x16_predmode) + `Intra16x16_Vertical: + begin + case (blk4x4_intra_calculate_counter) + 4:PE0_in0 <= Intra_mbAddrB_window0; + 3:PE0_in0 <= Intra_mbAddrB_window1; + 2:PE0_in0 <= Intra_mbAddrB_window2; + 1:PE0_in0 <= Intra_mbAddrB_window3; + default:PE0_in0 <= 0; + endcase + PE0_in1 <= 0; PE0_in2 <= 0; PE0_in3 <= 0; + PE0_IsShift <= 0; PE0_IsStore <= 0; PE0_IsClip <= 0; + PE0_full_bypass <= 1; PE0_round_value <= 0; PE0_shift_len <= 0; + end + `Intra16x16_Horizontal: + begin + PE0_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window0:0; + PE0_in1 <= 0; PE0_in2 <= 0; PE0_in3 <= 0; + PE0_IsShift <= 0; PE0_IsStore <= 0; PE0_IsClip <= 0; + PE0_full_bypass <= 1; PE0_round_value <= 0; PE0_shift_len <= 0; + end + `Intra16x16_DC: + if (blk4x4_rec_counter == 0) + case (blk4x4_intra_calculate_counter) + 4:begin // A2 + B2 + C2 + D2 + PE0_in0 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg0; + PE0_in1 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg1; + PE0_in2 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg2; + PE0_in3 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg3; + PE0_IsShift <= 0; PE0_IsStore <= 1; PE0_IsClip <= 0; + PE0_full_bypass <= 0; PE0_round_value <= 0; PE0_shift_len <= 0; end + 3:begin // PE0 output + B1 + C1 + D1 + PE0_in0 <= PE0_out_reg; + PE0_in1 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg1; + PE0_in2 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg2; + PE0_in3 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg3; + PE0_IsShift <= 0; PE0_IsStore <= 1; PE0_IsClip <= 0; + PE0_full_bypass <= 0; PE0_round_value <= 0; PE0_shift_len <= 0; end + 2:begin // PE0 output + PE1 output + PE2 output + PE3 output + PE0_in0 <= PE0_out_reg; PE0_in1 <= PE1_out_reg; + PE0_in2 <= PE2_out_reg; PE0_in3 <= PE3_out_reg; + PE0_IsShift <= 0; PE0_IsStore <= 1; PE0_IsClip <= 0; + PE0_full_bypass <= 0; PE0_round_value <= 0; PE0_shift_len <= 0; end + 1:begin // final DC output + PE0_in0 <= (!mbAddrA_availability && !mbAddrB_availability)? 16'd128:PE0_out_reg; + PE0_in1 <= PE1_out_reg; PE0_in2 <= 0; PE0_in3 <= 0; + PE0_IsShift <= 0; PE0_IsStore <= 1; PE0_IsClip <= 0; + PE0_full_bypass <= (!mbAddrA_availability && !mbAddrB_availability)? 1'b1 :1'b0; + PE0_round_value <= ( mbAddrA_availability && mbAddrB_availability)? 5'b10000:5'b01000; + PE0_shift_len <= ( mbAddrA_availability && mbAddrB_availability)? 3'b101 :3'b100; + end + default:begin + PE0_in0 <= 0; PE0_in1 <= 0; PE0_in2 <= 0; PE0_in3 <= 0; + PE0_IsShift <= 0; PE0_IsStore <= 0; PE0_IsClip <= 0; + PE0_full_bypass <= 0; PE0_round_value <= 0; PE0_shift_len <= 0; end + endcase + else + begin + PE0_in0 <= 0; PE0_in1 <= 0; PE0_in2 <= 0; PE0_in3 <= 0; + PE0_IsShift <= 0; PE0_IsStore <= 0; PE0_IsClip <= 0; + PE0_full_bypass <= 0; PE0_round_value <= 0; PE0_shift_len <= 0; + end + `Intra16x16_Plane: + begin + if (blk4x4_intra_calculate_counter != 0) + //blk0,2,4,6,8,10,12,14,calc counter == 3'b100:PE0_in0 <= seed; + //other cases :PE0_in0 <= left pixel output + PE0_in0 <= (blk4x4_intra_calculate_counter == 4 && blk4x4_rec_counter[0] == 1'b0)? + seed:PE0_out_reg; + else + PE0_in0 <= 0; + //blk0,2,8,10,calc counter == 3'b100:PE0_in1 <= c_ext + //other cases :PE0_in1 <= b_ext + if (blk4x4_intra_calculate_counter != 0) + PE0_in1 <= (blk4x4_intra_calculate_counter == 4 && !blk4x4_rec_counter[2] && !blk4x4_rec_counter[0])? + c_ext:b_ext; + else + PE0_in1 <= 0; + PE0_in2 <= 0; PE0_in3 <= 0; + PE0_IsShift <= 1'b0; + PE0_IsStore <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0; + PE0_IsClip <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0; + PE0_full_bypass <= 1'b0; + PE0_round_value <= (blk4x4_intra_calculate_counter != 0)? 5'd16:5'd0; + PE0_shift_len <= (blk4x4_intra_calculate_counter != 0)? 3'd5 :3'd0; + end + endcase + //Chroma + else if (mb_type_general[3] == 1'b1 && blk4x4_rec_counter > 15) + case (Intra_chroma_predmode) + `Intra_chroma_DC: + begin + case ({mbAddrA_availability,mbAddrB_availability}) + 2'b00:PE0_in0 <= (blk4x4_intra_calculate_counter == 3)? 15'd128:15'd0; + 2'b01:PE0_in0 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrB_window0: + (blk4x4_intra_calculate_counter == 3)? PE0_out_reg:0; + 2'b10:PE0_in0 <= (blk4x4_intra_calculate_counter == 3)? PE1_out_reg:0; + 2'b11: + if (blk4x4_intra_calculate_counter == 4) + PE0_in0 <= (blk4x4_rec_counter == 18 || blk4x4_rec_counter == 22)? + 0:Intra_mbAddrB_window0; + else if (blk4x4_intra_calculate_counter == 3) + PE0_in0 <= PE0_out_reg; + else + PE0_in0 <= 0; + endcase + case ({mbAddrA_availability,mbAddrB_availability}) + 2'b00:PE0_in1 <= 0; + 2'b01:PE0_in1 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrB_window1:0; + 2'b10:PE0_in1 <= 0; + 2'b11: + if (blk4x4_intra_calculate_counter == 4) + PE0_in1 <= (blk4x4_rec_counter == 18 || blk4x4_rec_counter == 22)? + 0:Intra_mbAddrB_window1; + else if (blk4x4_intra_calculate_counter == 3) + PE0_in1 <= PE1_out_reg; + else + PE0_in1 <= 0; + endcase + case (mbAddrB_availability) + 1'b0:begin PE0_in2 <= 0; PE0_in3 <= 0; end + 1'b1: + begin + if (blk4x4_intra_calculate_counter == 4) + begin + PE0_in2 <= ((blk4x4_rec_counter == 18 || blk4x4_rec_counter == 22) && mbAddrA_availability)? + 0:Intra_mbAddrB_window2; + PE0_in3 <= ((blk4x4_rec_counter == 18 || blk4x4_rec_counter == 22) && mbAddrA_availability)? + 0:Intra_mbAddrB_window3; + end + else + begin PE0_in2 <= 0; PE0_in3 <= 0; end + end + endcase + PE0_IsShift <= 1'b0; + PE0_IsStore <= (mbAddrB_availability && blk4x4_intra_calculate_counter == 4)? 1'b1:1'b0; + PE0_IsClip <= 1'b0; + PE0_full_bypass <= (!mbAddrA_availability && !mbAddrB_availability && + blk4x4_intra_calculate_counter == 3)? 1'b1:1'b0; + case ({mbAddrA_availability,mbAddrB_availability}) + 2'b00 :begin PE0_round_value <= 0; PE0_shift_len <= 0; end + 2'b01,2'b10 :begin PE0_round_value <= (blk4x4_intra_calculate_counter == 3)? 5'd2:5'd0; + PE0_shift_len <= (blk4x4_intra_calculate_counter == 3)? 3'd2:3'd0; end + 2'b11: + begin + if (blk4x4_intra_calculate_counter == 3) + begin + PE0_round_value <= (blk4x4_rec_counter == 16 || blk4x4_rec_counter == 19 || + blk4x4_rec_counter == 20 || blk4x4_rec_counter == 23)? 5'd4:5'd2; + PE0_shift_len <= (blk4x4_rec_counter == 16 || blk4x4_rec_counter == 19 || + blk4x4_rec_counter == 20 || blk4x4_rec_counter == 23)? 3'd3:3'd2; + end + else + begin PE0_round_value <= 0; PE0_shift_len <= 0; end + end + endcase + end + `Intra_chroma_Horizontal: //---horizontal--- + begin + PE0_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window0:0; + PE0_in1 <= 0; PE0_in2 <= 0; PE0_in3 <= 0; + PE0_IsShift <= 0; PE0_IsStore <= 0; PE0_IsClip <= 0; + PE0_full_bypass <= 1; PE0_round_value <= 0; PE0_shift_len <= 0; + end + `Intra_chroma_Vertical: //---vertical--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE0_in0 <= Intra_mbAddrB_window0; + 3:PE0_in0 <= Intra_mbAddrB_window1; + 2:PE0_in0 <= Intra_mbAddrB_window2; + 1:PE0_in0 <= Intra_mbAddrB_window3; + default:PE0_in0 <= 0; + endcase + PE0_in1 <= 0; PE0_in2 <= 0; PE0_in3 <= 0; + PE0_IsShift <= 0; PE0_IsStore <= 0; PE0_IsClip <= 0; + PE0_full_bypass <= 1; PE0_round_value <= 0; PE0_shift_len <= 0; + end + `Intra_chroma_Plane: //---plane--- + begin + if (blk4x4_intra_calculate_counter != 0) + //need seed, blk4x4 = 16 | 18 | 20 | 22 + //do not need seed,blk4x4 = 17 | 19 | 21 | 23 + PE0_in0 <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)? + seed:PE0_out_reg; + else + PE0_in0 <= 0; + if (blk4x4_intra_calculate_counter != 0) + PE0_in1 <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)? c_ext:b_ext; + else + PE0_in1 <= 0; + PE0_in2 <= 0; PE0_in3 <= 0; + PE0_IsShift <= 1'b0; + PE0_IsStore <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0; + PE0_IsClip <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0; + PE0_full_bypass <= 1'b0; + PE0_round_value <= (blk4x4_intra_calculate_counter != 0)? 5'd16:5'd0; + PE0_shift_len <= (blk4x4_intra_calculate_counter != 0)? 3'd5 :3'd0; + end + endcase + else + begin + PE0_in0 <= 0; PE0_in1 <= 0; PE0_in2 <= 0; PE0_in3 <= 0; + PE0_IsShift <= 0; PE0_IsStore <= 0; PE0_IsClip <= 0; + PE0_full_bypass <= 0; PE0_round_value <= 0; PE0_shift_len <= 0; + end + //---- + //PE1 | + //---- + always @ (mb_type_general or blk4x4_rec_counter or blk4x4_intra_calculate_counter + or Intra4x4_predmode or Intra16x16_predmode or Intra_chroma_predmode + or blkAddrA_availability or mbAddrA_availability or mbAddrB_availability + + or Intra_mbAddrA_window0 or Intra_mbAddrA_window1 or Intra_mbAddrA_window2 or Intra_mbAddrA_window3 + or Intra_mbAddrB_window0 or Intra_mbAddrB_window1 or Intra_mbAddrB_window2 or Intra_mbAddrB_window3 + or Intra_mbAddrD_window + + or Intra_mbAddrA_reg4 or Intra_mbAddrA_reg5 or Intra_mbAddrA_reg6 or Intra_mbAddrA_reg7 + or Intra_mbAddrB_reg0 or Intra_mbAddrB_reg4 or Intra_mbAddrB_reg5 or Intra_mbAddrB_reg6 + or Intra_mbAddrB_reg7 or Intra_mbAddrB_reg8 or Intra_mbAddrB_reg12 + + or PE1_out_reg + or blk4x4_pred_output0 or blk4x4_pred_output1 or blk4x4_pred_output2 + or blk4x4_pred_output8 or blk4x4_pred_output9 or blk4x4_pred_output12 + or blk4x4_pred_output13 or blk4x4_pred_output14 + or seed or b_ext or c_ext) + //Intra 4x4 + if (mb_type_general[3:2] == 2'b11 && blk4x4_rec_counter < 16) + case (Intra4x4_predmode) + `Intra4x4_Vertical: //---Vertical--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE1_in0 <= Intra_mbAddrB_window0; + 3:PE1_in0 <= Intra_mbAddrB_window1; + 2:PE1_in0 <= Intra_mbAddrB_window2; + 1:PE1_in0 <= Intra_mbAddrB_window3; + default:PE1_in0 <= 0; + endcase + PE1_in1 <= 0; PE1_in2 <= 0; PE1_in3 <= 0; + PE1_IsShift <= 0; PE1_IsStore <= 0; PE1_IsClip <= 0; + PE1_full_bypass <= 1; PE1_round_value <= 0; PE1_shift_len <= 0; + end + `Intra4x4_Horizontal: //---Horizontal--- + begin + PE1_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window1:0; + PE1_in1 <= 0; PE1_in2 <= 0; PE1_in3 <= 0; + PE1_IsShift <= 0; PE1_IsStore <= 0; PE1_IsClip <= 0; + PE1_full_bypass <= 1; PE1_round_value <= 0; PE1_shift_len <= 0; + end + `Intra4x4_DC: //---DC--- + begin + PE1_in0 <= (blk4x4_intra_calculate_counter == 4 && blkAddrA_availability == 1)? + Intra_mbAddrA_window0:0; + PE1_in1 <= (blk4x4_intra_calculate_counter == 4 && blkAddrA_availability == 1)? + Intra_mbAddrA_window1:0; + PE1_in2 <= (blk4x4_intra_calculate_counter == 4 && blkAddrA_availability == 1)? + Intra_mbAddrA_window2:0; + PE1_in3 <= (blk4x4_intra_calculate_counter == 4 && blkAddrA_availability == 1)? + Intra_mbAddrA_window3:0; + PE1_IsStore <= (blk4x4_intra_calculate_counter == 4 && blkAddrA_availability == 1)? 1'b1:1'b0; + PE1_full_bypass <= 1'b0; PE1_IsShift <= 0; PE1_IsClip <= 0; + PE1_round_value <= 0; PE1_shift_len <= 0; + end + `Intra4x4_Diagonal_Down_Left: //---diagonal down-left--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE1_in0 <= Intra_mbAddrB_window1; + 3:PE1_in0 <= blk4x4_pred_output8; + 2:PE1_in0 <= blk4x4_pred_output12; + 1:PE1_in0 <= blk4x4_pred_output13; + default:PE1_in0 <= 0; + endcase + PE1_in1 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrB_window3:0; + PE1_in2 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrB_window2:0; + PE1_in3 <= 0; + PE1_IsShift <= (blk4x4_intra_calculate_counter == 4)? 1'b1:1'b0; + PE1_IsStore <= 1'b0; PE1_IsClip <= 1'b0; + PE1_full_bypass <= (blk4x4_intra_calculate_counter == 4)? 1'b0:1'b1; + PE1_round_value <= (blk4x4_intra_calculate_counter == 4)? 5'b00010:5'b0; // +2 + PE1_shift_len <= (blk4x4_intra_calculate_counter == 4)? 3'b010 :3'b0; // >>2 + end + `Intra4x4_Diagonal_Down_Right: //---diagonal down-right--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE1_in0 <= Intra_mbAddrD_window; + 3:PE1_in0 <= blk4x4_pred_output0; + 2:PE1_in0 <= blk4x4_pred_output1; + 1:PE1_in0 <= blk4x4_pred_output2; + default:PE1_in0 <= 0; + endcase + PE1_in1 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrA_window1:0; + PE1_in2 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrA_window0:0; + PE1_in3 <= 0; + PE1_IsShift <= (blk4x4_intra_calculate_counter == 0)? 1'b0:1'b1; + PE1_IsStore <= 1'b0; PE1_IsClip <= 1'b0; + PE1_full_bypass <= (blk4x4_intra_calculate_counter == 4)? 1'b0:1'b1; + PE1_round_value <= (blk4x4_intra_calculate_counter == 0)? 5'b0:5'b00010; // +2 + PE1_shift_len <= (blk4x4_intra_calculate_counter == 0)? 3'b0:3'b010; // >>2 + end + `Intra4x4_Vertical_Right: //---vertical right--- + begin + case (blk4x4_intra_calculate_counter) + 4:begin PE1_in0 <= Intra_mbAddrB_window0; PE1_in1 <= Intra_mbAddrA_window0; + PE1_in2 <= Intra_mbAddrD_window; end + 3:begin PE1_in0 <= Intra_mbAddrD_window; PE1_in1 <= Intra_mbAddrB_window1; + PE1_in2 <= Intra_mbAddrB_window0; end + 2:begin PE1_in0 <= Intra_mbAddrB_window0; PE1_in1 <= Intra_mbAddrB_window2; + PE1_in2 <= Intra_mbAddrB_window1; end + 1:begin PE1_in0 <= Intra_mbAddrB_window1; PE1_in1 <= Intra_mbAddrB_window3; + PE1_in2 <= Intra_mbAddrB_window2; end + default:begin PE1_in0 <= 0;PE1_in1 <= 0;PE1_in2 <= 0; end + endcase + PE1_in3 <= 0; + PE1_IsShift <= (blk4x4_intra_calculate_counter == 0)? 1'b0:1'b1; + PE1_IsStore <= 1'b0; PE1_IsClip <= 1'b0; PE1_full_bypass <= 1'b0; + PE1_round_value <= (blk4x4_intra_calculate_counter == 0)? 5'b0:5'b00010; // +2 + PE1_shift_len <= (blk4x4_intra_calculate_counter == 0)? 3'b0:3'b010; // >>2 + end + `Intra4x4_Horizontal_Down: //---horizontal down--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE1_in0 <= Intra_mbAddrA_window0; + 3:PE1_in0 <= Intra_mbAddrD_window; + 2:PE1_in0 <= blk4x4_pred_output0; + 1:PE1_in0 <= blk4x4_pred_output1; + default:PE1_in0 <= 0; + endcase + PE1_in1 <= (blk4x4_intra_calculate_counter == 4 || blk4x4_intra_calculate_counter == 3)? + Intra_mbAddrA_window1:0; + PE1_in2 <= (blk4x4_intra_calculate_counter == 3)? Intra_mbAddrA_window0:0; + PE1_in3 <= 0; + PE1_IsShift <= (blk4x4_intra_calculate_counter == 3)? 1'b1:1'b0; + PE1_IsStore <= 1'b0; PE1_IsClip <= 1'b0; + PE1_full_bypass <= (blk4x4_intra_calculate_counter == 2 || + blk4x4_intra_calculate_counter == 1)? 1'b1:1'b0; + PE1_round_value <= (blk4x4_intra_calculate_counter == 4)? 5'd1: + (blk4x4_intra_calculate_counter == 3)? 5'd2:5'd0; + PE1_shift_len <= (blk4x4_intra_calculate_counter == 4)? 3'd1: + (blk4x4_intra_calculate_counter == 3)? 3'd2:3'd0; + end + `Intra4x4_Vertical_Left: //---vertical left--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE1_in0 <= Intra_mbAddrB_window0; + 3:PE1_in0 <= blk4x4_pred_output12; + 2:PE1_in0 <= blk4x4_pred_output13; + 1:PE1_in0 <= blk4x4_pred_output14; + default:PE1_in0 <= 0; + endcase + PE1_in1 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrB_window2:0; + PE1_in2 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrB_window1:0; + PE1_in3 <= 0; + PE1_IsShift <= (blk4x4_intra_calculate_counter == 4)? 1'b1:1'b0; + PE1_IsStore <= 1'b0; PE1_IsClip <= 1'b0; + PE1_full_bypass <= (blk4x4_intra_calculate_counter == 4)? 1'b0:1'b1; + PE1_round_value <= (blk4x4_intra_calculate_counter == 4)? 5'd2:5'd0; // +2 + PE1_shift_len <= (blk4x4_intra_calculate_counter == 4)? 3'd2:3'd0; // >>2 + end + `Intra4x4_Horizontal_Up: //---horizontal up--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE1_in0 <= Intra_mbAddrA_window1; + 3:PE1_in0 <= Intra_mbAddrA_window1; + 2:PE1_in0 <= blk4x4_pred_output8; + 1:PE1_in0 <= blk4x4_pred_output9; + default:PE1_in0 <= 0; + endcase + PE1_in1 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrA_window2: + (blk4x4_intra_calculate_counter == 3)? Intra_mbAddrA_window3:0; + PE1_in2 <= (blk4x4_intra_calculate_counter == 3)? Intra_mbAddrA_window2:0; + PE1_in3 <= 0; + PE1_IsShift <= (blk4x4_intra_calculate_counter == 3)? 1'b1:1'b0; + PE1_IsStore <= 1'b0; PE1_IsClip <= 1'b0; + PE1_full_bypass <= (blk4x4_intra_calculate_counter == 2 || + blk4x4_intra_calculate_counter == 1)? 1'b1:1'b0; + PE1_round_value <= (blk4x4_intra_calculate_counter == 4)? 5'd1: + (blk4x4_intra_calculate_counter == 3)? 5'd2:5'd0; + PE1_shift_len <= (blk4x4_intra_calculate_counter == 4)? 3'd1: + (blk4x4_intra_calculate_counter == 3)? 3'd2:3'd0; + end + default: + begin + PE1_in0 <= 0; PE1_in1 <= 0; PE1_in2 <= 0; PE1_in3 <= 0; + PE1_IsShift <= 0; PE1_IsStore <= 0; PE1_IsClip <= 0; + PE1_full_bypass <= 0; PE1_round_value <= 0; PE1_shift_len <= 0; + end + endcase + //Intra16x16 + else if (mb_type_general[3:2] == 2'b10 && blk4x4_rec_counter < 16) + case (Intra16x16_predmode) + `Intra16x16_Vertical: //---Vertical--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE1_in0 <= Intra_mbAddrB_window0; + 3:PE1_in0 <= Intra_mbAddrB_window1; + 2:PE1_in0 <= Intra_mbAddrB_window2; + 1:PE1_in0 <= Intra_mbAddrB_window3; + default:PE1_in0 <= 0; + endcase + PE1_in1 <= 0; PE1_in2 <= 0; PE1_in3 <= 0; + PE1_IsShift <= 0; PE1_IsStore <= 0; PE1_IsClip <= 0; + PE1_full_bypass <= 1; PE1_round_value <= 0; PE1_shift_len <= 0; + end + `Intra16x16_Horizontal: //---Horizontal--- + begin + PE1_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window1:0; + PE1_in1 <= 0; PE1_in2 <= 0; PE1_in3 <= 0; + PE1_IsShift <= 0; PE1_IsStore <= 0; PE1_IsClip <= 0; + PE1_full_bypass <= 1; PE1_round_value <= 0; PE1_shift_len <= 0; + end + `Intra16x16_DC: //---DC--- + if (blk4x4_rec_counter == 0) + case (blk4x4_intra_calculate_counter) + 4:begin // E2 + F2 + G2 + H2 + PE1_in0 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg4; + PE1_in1 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg5; + PE1_in2 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg6; + PE1_in3 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg7; + PE1_IsShift <= 0; PE1_IsStore <= 1; PE1_IsClip <= 0; + PE1_full_bypass <= 0; PE1_round_value <= 0; PE1_shift_len <= 0; end + 3:begin // PE1 output + F1 + G1 + H1 + PE1_in0 <= PE1_out_reg; + PE1_in1 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg5; + PE1_in2 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg6; + PE1_in3 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg7; + PE1_IsShift <= 0; PE1_IsStore <= 1; PE1_IsClip <= 0; + PE1_full_bypass <= 0; PE1_round_value <= 0; PE1_shift_len <= 0; end + 2:begin // A1 + E1 + I1 + M1 + PE1_in0 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg0; + PE1_in1 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg4; + PE1_in2 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg8; + PE1_in3 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg12; + PE1_IsShift <= 0; PE1_IsStore <= 1; PE1_IsClip <= 0; + PE1_full_bypass <= 0; PE1_round_value <= 0; PE1_shift_len <= 0; end + default:begin + PE1_in0 <= 0; PE1_in1 <= 0; PE1_in2 <= 0; PE1_in3 <= 0; + PE1_IsShift <= 0; PE1_IsStore <= 0; PE1_IsClip <= 0; + PE1_full_bypass <= 0; PE1_round_value <= 0; PE1_shift_len <= 0; end + endcase + else + begin + PE1_in0 <= 0; PE1_in1 <= 0; PE1_in2 <= 0; PE1_in3 <= 0; + PE1_IsShift <= 0; PE1_IsStore <= 0; PE1_IsClip <= 0; + PE1_full_bypass <= 0; PE1_round_value <= 0; PE1_shift_len <= 0; + end + `Intra16x16_Plane: //---plane--- + begin + if (blk4x4_intra_calculate_counter != 0) + //blk0,2,4,6,8,10,12,14,calc counter == 3'b100:PE1_in0 <= seed; + //other cases :PE1_in0 <= left pixel output + PE1_in0 <= (blk4x4_intra_calculate_counter == 4 && blk4x4_rec_counter[0] == 1'b0)? + seed:PE1_out_reg; + else + PE1_in0 <= 0; + if (blk4x4_intra_calculate_counter != 0) + //blk0,2,8,10,calc counter == 3'b100:PE1_in1 <= c_ext x 2 + //other cases :PE1_in1 <= b_ext + PE1_in1 <= (blk4x4_intra_calculate_counter == 4 && !blk4x4_rec_counter[2] && !blk4x4_rec_counter[0])? + {c_ext[14:0],1'b0}:b_ext; + else + PE1_in1 <= 0; + //blk4,6,12,14,calc counter == 3'b100:PE1_in2 <= c_ext; + //other cases :PE1_in2 <= 0 + PE1_in2 <= (blk4x4_intra_calculate_counter == 4 && blk4x4_rec_counter[2] && !blk4x4_rec_counter[0])? + c_ext:0; + PE1_in3 <= 0; + PE1_IsShift <= 1'b0; + PE1_IsStore <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0; + PE1_IsClip <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0; + PE1_full_bypass <= 1'b0; + PE1_round_value <= (blk4x4_intra_calculate_counter != 0)? 5'd16:5'd0; + PE1_shift_len <= (blk4x4_intra_calculate_counter != 0)? 3'd5 :3'd0; + end + endcase + //Chroma + else if (mb_type_general[3] == 1'b1 && blk4x4_rec_counter > 15) + case (Intra_chroma_predmode) + `Intra_chroma_DC: //---DC--- + if (blk4x4_intra_calculate_counter == 4) + begin + case ({mbAddrA_availability,mbAddrB_availability}) + 2'b00,2'b01: + begin + PE1_in0 <= 0; PE1_in1 <= 0; PE1_in2 <= 0; PE1_in3 <= 0; + end + 2'b10: + begin + PE1_in0 <= Intra_mbAddrA_window0; PE1_in1 <= Intra_mbAddrA_window1; + PE1_in2 <= Intra_mbAddrA_window2; PE1_in3 <= Intra_mbAddrA_window3; + end + 2'b11: + begin + PE1_in0 <= (blk4x4_rec_counter == 17 || blk4x4_rec_counter == 21)? + 0:Intra_mbAddrA_window0; + PE1_in1 <= (blk4x4_rec_counter == 17 || blk4x4_rec_counter == 21)? + 0:Intra_mbAddrA_window1; + PE1_in2 <= (blk4x4_rec_counter == 17 || blk4x4_rec_counter == 21)? + 0:Intra_mbAddrA_window2; + PE1_in3 <= (blk4x4_rec_counter == 17 || blk4x4_rec_counter == 21)? + 0:Intra_mbAddrA_window3; + end + endcase + PE1_IsShift <= 1'b0; PE1_IsClip <= 1'b0; + PE1_IsStore <= (mbAddrA_availability)? 1'b1:1'b0; + PE1_full_bypass <= 1'b0; + PE1_round_value <= 0; PE1_shift_len <= 0; + end + else + begin + PE1_in0 <= 0; PE1_in1 <= 0; PE1_in2 <= 0; PE1_in3 <= 0; + PE1_IsShift <= 0; PE1_IsStore <= 0; PE1_IsClip <= 0; + PE1_full_bypass <= 0; PE1_round_value <= 0; PE1_shift_len <= 0; + end + `Intra_chroma_Horizontal: //---horizontal--- + begin + PE1_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window1:0; + PE1_in1 <= 0; PE1_in2 <= 0; PE1_in3 <= 0; + PE1_IsShift <= 0; PE1_IsStore <= 0; PE1_IsClip <= 0; + PE1_full_bypass <= 1; PE1_round_value <= 0; PE1_shift_len <= 0; + end + `Intra_chroma_Vertical: //---vertical--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE1_in0 <= Intra_mbAddrB_window0; + 3:PE1_in0 <= Intra_mbAddrB_window1; + 2:PE1_in0 <= Intra_mbAddrB_window2; + 1:PE1_in0 <= Intra_mbAddrB_window3; + default:PE1_in0 <= 0; + endcase + PE1_in1 <= 0; PE1_in2 <= 0; PE1_in3 <= 0; + PE1_IsShift <= 0; PE1_IsStore <= 0; PE1_IsClip <= 0; + PE1_full_bypass <= 1; PE1_round_value <= 0; PE1_shift_len <= 0; + end + `Intra_chroma_Plane: //---plane--- + begin + if (blk4x4_intra_calculate_counter != 0) + //need seed, blk4x4 = 16 | 18 | 20 | 22 + //do not need seed,blk4x4 = 17 | 19 | 21 | 23 + PE1_in0 <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)? + seed:PE1_out_reg; + else + PE1_in0 <= 0; + if (blk4x4_intra_calculate_counter != 0) + PE1_in1 <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)? + 0:b_ext; + else + PE1_in1 <= 0; + //0,2,8,10,the 4th cycle,+2c + PE1_in2 <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)? c_ext:0; + PE1_in3 <= 0; + PE1_IsShift <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)? + 1'b1:1'b0; + PE1_IsStore <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0; + PE1_IsClip <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0; + PE1_full_bypass <= 1'b0; + PE1_round_value <= (blk4x4_intra_calculate_counter != 0)? 5'd16:5'd0; + PE1_shift_len <= (blk4x4_intra_calculate_counter != 0)? 3'd5 :3'd0; + end + endcase + else + begin + PE1_in0 <= 0; PE1_in1 <= 0; PE1_in2 <= 0; PE1_in3 <= 0; + PE1_IsShift <= 0; PE1_IsStore <= 0; PE1_IsClip <= 0; + PE1_full_bypass <= 0; PE1_round_value <= 0; PE1_shift_len <= 0; + end + + //---- + //PE2 | + //---- + always @ (mb_type_general or blk4x4_rec_counter or blk4x4_intra_calculate_counter + or Intra4x4_predmode or Intra16x16_predmode or Intra_chroma_predmode + or mbAddrA_availability or mbAddrB_availability + + or Intra_mbAddrA_window0 or Intra_mbAddrA_window1 or Intra_mbAddrA_window2 or Intra_mbAddrA_window3 + or Intra_mbAddrB_window0 or Intra_mbAddrB_window1 or Intra_mbAddrB_window2 or Intra_mbAddrB_window3 + or Intra_mbAddrD_window + or Intra_mbAddrC_window0 or Intra_mbAddrC_window1 + + or Intra_mbAddrA_reg8 or Intra_mbAddrA_reg9 or Intra_mbAddrA_reg10 or Intra_mbAddrA_reg11 + or Intra_mbAddrB_reg9 or Intra_mbAddrB_reg10 or Intra_mbAddrB_reg11 + or blk4x4_pred_output0 or blk4x4_pred_output1 or blk4x4_pred_output2 + or blk4x4_pred_output4 or blk4x4_pred_output5 or blk4x4_pred_output12 + or blk4x4_pred_output13 or blk4x4_pred_output14 + or PE2_out_reg + + or seed or b_ext or c_ext) + //Intra 4x4 + if (mb_type_general[3:2] == 2'b11 && blk4x4_rec_counter < 16) + case (Intra4x4_predmode) + `Intra4x4_Vertical: //---Vertical--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE2_in0 <= Intra_mbAddrB_window0; + 3:PE2_in0 <= Intra_mbAddrB_window1; + 2:PE2_in0 <= Intra_mbAddrB_window2; + 1:PE2_in0 <= Intra_mbAddrB_window3; + default:PE2_in0 <= 0; + endcase + PE2_in1 <= 0; PE2_in2 <= 0; PE2_in3 <= 0; + PE2_IsShift <= 0; PE2_IsStore <= 0; PE2_IsClip <= 0; + PE2_full_bypass <= 1; PE2_round_value <= 0; PE2_shift_len <= 0; + end + `Intra4x4_Horizontal: //---Horizontal--- + begin + PE2_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window2:0; + PE2_in1 <= 0; PE2_in2 <= 0; PE2_in3 <= 0; + PE2_IsShift <= 0; PE2_IsStore <= 0; PE2_IsClip <= 0; + PE2_full_bypass <= 1; PE2_round_value <= 0; PE2_shift_len <= 0; + end + //------------- + //no PE2 for DC + //4'b0010: + //------------- + `Intra4x4_Diagonal_Down_Left: //---diagonal down-left--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE2_in0 <= Intra_mbAddrB_window2; + 3:PE2_in0 <= blk4x4_pred_output12; + 2:PE2_in0 <= blk4x4_pred_output13; + 1:PE2_in0 <= blk4x4_pred_output14; + default:PE2_in0 <= 0; + endcase + PE2_in1 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrC_window0:0; + PE2_in2 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrB_window3:0; + PE2_in3 <= 0; + PE2_IsShift <= (blk4x4_intra_calculate_counter == 4)? 1'b1:1'b0; + PE2_IsStore <= 1'b0; PE2_IsClip <= 1'b0; + PE2_full_bypass <= (blk4x4_intra_calculate_counter == 4)? 1'b0:1'b1; + PE2_round_value <= (blk4x4_intra_calculate_counter == 4)? 5'd2:5'd0; // +2 + PE2_shift_len <= (blk4x4_intra_calculate_counter == 4)? 3'd2:3'd0; // >>2 + end + `Intra4x4_Diagonal_Down_Right: //---diagonal down-right--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE2_in0 <= Intra_mbAddrA_window0; + 3:PE2_in0 <= blk4x4_pred_output4; + 2:PE2_in0 <= blk4x4_pred_output0; + 1:PE2_in0 <= blk4x4_pred_output1; + default:PE2_in0 <= 0; + endcase + PE2_in1 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrA_window2:0; + PE2_in2 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrA_window1:0; + PE2_in3 <= 0; + PE2_IsShift <= (blk4x4_intra_calculate_counter == 0)? 1'b0:1'b1; + PE2_IsStore <= 1'b0; PE2_IsClip <= 1'b0; + PE2_full_bypass <= (blk4x4_intra_calculate_counter == 4)? 1'b0:1'b1; + PE2_round_value <= (blk4x4_intra_calculate_counter == 0)? 5'd0:5'd2; // +2 + PE2_shift_len <= (blk4x4_intra_calculate_counter == 0)? 3'd0:3'd2; // >>2 + end + `Intra4x4_Vertical_Right: //---vertical right--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE2_in0 <= Intra_mbAddrD_window; + 3:PE2_in0 <= blk4x4_pred_output0; + 2:PE2_in0 <= blk4x4_pred_output1; + 1:PE2_in0 <= blk4x4_pred_output2; + default:PE2_in0 <= 0; + endcase + PE2_in1 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrA_window1:0; + PE2_in2 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrA_window0:0; + PE2_in3 <= 0; + PE2_IsShift <= (blk4x4_intra_calculate_counter == 0)? 1'b0:1'b1; + PE2_IsStore <= 1'b0; PE2_IsClip <= 1'b0; + PE2_full_bypass <= (blk4x4_intra_calculate_counter == 4)? 1'b0:1'b1; + PE2_round_value <= (blk4x4_intra_calculate_counter == 0)? 5'd0:5'd2; // +2 + PE2_shift_len <= (blk4x4_intra_calculate_counter == 0)? 3'd0:3'd2; // >>2 + end + `Intra4x4_Horizontal_Down: //---horizontal down--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE2_in0 <= Intra_mbAddrA_window1; + 3:PE2_in0 <= Intra_mbAddrA_window0; + 2:PE2_in0 <= blk4x4_pred_output4; + 1:PE2_in0 <= blk4x4_pred_output5; + default:PE2_in0 <= 0; + endcase + PE2_in1 <= (blk4x4_intra_calculate_counter == 4 || blk4x4_intra_calculate_counter == 3)? + Intra_mbAddrA_window2:0; + PE2_in2 <= (blk4x4_intra_calculate_counter == 3)? Intra_mbAddrA_window1:0; + PE2_in3 <= 0; + PE2_IsShift <= (blk4x4_intra_calculate_counter == 3)? 1'b1:1'b0; + PE2_IsStore <= 1'b0; PE2_IsClip <= 1'b0; + PE2_full_bypass <= (blk4x4_intra_calculate_counter == 2 || + blk4x4_intra_calculate_counter == 1)? 1'b1:1'b0; + PE2_round_value <= (blk4x4_intra_calculate_counter == 4)? 5'd1: + (blk4x4_intra_calculate_counter == 3)? 5'd2:5'd0; + PE2_shift_len <= (blk4x4_intra_calculate_counter == 4)? 3'd1: + (blk4x4_intra_calculate_counter == 3)? 3'd2:3'd0; + end + `Intra4x4_Vertical_Left: //---vertical left--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE2_in0 <= Intra_mbAddrB_window1; + 3:PE2_in0 <= Intra_mbAddrB_window3; + 2:PE2_in0 <= Intra_mbAddrB_window3; + 1:PE2_in0 <= Intra_mbAddrC_window1; + default:PE2_in0 <= 0; + endcase + case (blk4x4_intra_calculate_counter) + 4,3:PE2_in1 <= Intra_mbAddrB_window2; + 2,1:PE2_in1 <= Intra_mbAddrC_window0; + default:PE2_in1 <= 0; + endcase + PE2_in2 <= 0; PE2_in3 <= 0; + PE2_IsShift <= 0; PE2_IsStore <= 0; PE2_IsClip <= 1'b0; PE2_full_bypass <= 1'b0; + PE2_round_value <= (blk4x4_intra_calculate_counter != 0)? 5'd1:5'd0; // +1 + PE2_shift_len <= (blk4x4_intra_calculate_counter != 0)? 3'd1:3'd0; // >>1 + end + `Intra4x4_Horizontal_Up: //---horizontal up--- + begin + case (blk4x4_intra_calculate_counter) + 4,3:PE2_in0 <= Intra_mbAddrA_window2; + 2,1:PE2_in0 <= blk4x4_pred_output12; + default:PE2_in0 <= 0; + endcase + PE2_in1 <= (blk4x4_intra_calculate_counter == 4 || blk4x4_intra_calculate_counter == 3)? + Intra_mbAddrA_window3:0; + PE2_in2 <= (blk4x4_intra_calculate_counter == 3)? Intra_mbAddrA_window3:0; + PE2_in3 <= 0; + PE2_IsShift <= (blk4x4_intra_calculate_counter == 3)? 1'b1:1'b0; + PE2_IsStore <= 1'b0; PE2_IsClip <= 1'b0; + PE2_full_bypass <= (blk4x4_intra_calculate_counter == 2 || + blk4x4_intra_calculate_counter == 1)? 1'b1:1'b0; + PE2_round_value <= (blk4x4_intra_calculate_counter == 4)? 5'd1: + (blk4x4_intra_calculate_counter == 3)? 5'd2:5'd0; + PE2_shift_len <= (blk4x4_intra_calculate_counter == 4)? 3'd1: + (blk4x4_intra_calculate_counter == 3)? 3'd2:3'd0; + end + default: + begin + PE2_in0 <= 0; PE2_in1 <= 0; PE2_in2 <= 0; PE2_in3 <= 0; + PE2_IsShift <= 0; PE2_IsStore <= 0; PE2_IsClip <= 0; + PE2_full_bypass <= 0; PE2_round_value <= 0; PE2_shift_len <= 0; + end + endcase + //Intra16x16 + else if (mb_type_general[3:2] == 2'b10 && blk4x4_rec_counter < 16) + case (Intra16x16_predmode) + `Intra16x16_Vertical: //---Vertical--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE2_in0 <= Intra_mbAddrB_window0; + 3:PE2_in0 <= Intra_mbAddrB_window1; + 2:PE2_in0 <= Intra_mbAddrB_window2; + 1:PE2_in0 <= Intra_mbAddrB_window3; + default:PE2_in0 <= 0; + endcase + PE2_in1 <= 0; PE2_in2 <= 0; PE2_in3 <= 0; + PE2_IsShift <= 0; PE2_IsStore <= 0; PE2_IsClip <= 0; + PE2_full_bypass <= 1; PE2_round_value <= 0; PE2_shift_len <= 0; + end + `Intra16x16_Horizontal: //---Horizontal--- + begin + PE2_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window2:0; + PE2_in1 <= 0; PE2_in2 <= 0; PE2_in3 <= 0; + PE2_IsShift <= 0; PE2_IsStore <= 0; PE2_IsClip <= 0; + PE2_full_bypass <= 1; PE2_round_value <= 0; PE2_shift_len <= 0; + end + `Intra16x16_DC: //---DC--- + if (blk4x4_rec_counter == 0) + case (blk4x4_intra_calculate_counter) + 4:begin // I2 + J2 + K2 + L2 + PE2_in0 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg8; + PE2_in1 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg9; + PE2_in2 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg10; + PE2_in3 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg11; + PE2_IsShift <= 0; PE2_IsStore <= 1; PE2_IsClip <= 0; + PE2_full_bypass <= 0; PE2_round_value <= 0; PE2_shift_len <= 0; end + 3:begin // PE2 output + J1 + K1 + L1 + PE2_in0 <= PE2_out_reg; + PE2_in1 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg9; + PE2_in2 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg10; + PE2_in3 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg11; + PE2_IsShift <= 0; PE2_IsStore <= 1; PE2_IsClip <= 0; + PE2_full_bypass <= 0; PE2_round_value <= 0; PE2_shift_len <= 0; end + default:begin + PE2_in0 <= 0; PE2_in1 <= 0; PE2_in2 <= 0; PE2_in3 <= 0; + PE2_IsShift <= 0; PE2_IsStore <= 0; PE2_IsClip <= 0; + PE2_full_bypass <= 0; PE2_round_value <= 0; PE2_shift_len <= 0; end + endcase + else + begin + PE2_in0 <= 0; PE2_in1 <= 0; PE2_in2 <= 0; PE2_in3 <= 0; + PE2_IsShift <= 0; PE2_IsStore <= 0; PE2_IsClip <= 0; + PE2_full_bypass <= 0; PE2_round_value <= 0; PE2_shift_len <= 0; + end + `Intra16x16_Plane: //---plane--- + begin + if (blk4x4_intra_calculate_counter != 0) + //blk0,2,4,6,8,10,12,14,calc counter == 3'b100:PE2_in0 <= seed; + //other cases :PE2_in0 <= left pixel output + PE2_in0 <= (blk4x4_intra_calculate_counter == 4 && blk4x4_rec_counter[0] == 1'b0)? + seed:PE2_out_reg; + else + PE2_in0 <= 0; + if (blk4x4_intra_calculate_counter != 0) + //blk0,2,8,10,calc counter == 3'b100:PE2_in1 <= c_ext x 2 + //other cases :PE2_in1 <= b_ext + PE2_in1 <= (blk4x4_intra_calculate_counter == 4 && !blk4x4_rec_counter[2] && !blk4x4_rec_counter[0])? + {c_ext[14:0],1'b0}:b_ext; + else + PE2_in1 <= 0; + //blk0,2, 8,10,calc counter == 3'b100:PE2_in2 <= c_ext; + //blk4,6,12,14,calc counter == 3'b100:PE2_in2 <= c_ext x 2; + //other cases :PE2_in2 <= 0 + if (blk4x4_intra_calculate_counter == 3'b100 && !blk4x4_rec_counter[0]) + PE2_in2 <= (blk4x4_rec_counter[2])? {c_ext[14:0],1'b0}:c_ext; + else + PE2_in2 <= 0; + PE2_in3 <= 0; + PE2_IsShift <= 1'b0; + PE2_IsStore <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0; + PE2_IsClip <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0; + PE2_full_bypass <= 1'b0; + PE2_round_value <= (blk4x4_intra_calculate_counter != 0)? 5'd16:5'd0; + PE2_shift_len <= (blk4x4_intra_calculate_counter != 0)? 3'd5 :3'd0; + end + endcase + //Chroma + else if (mb_type_general[3] == 1'b1 && blk4x4_rec_counter > 15) + case (Intra_chroma_predmode) + //-------------------- + //no PE2 for Chroma DC + //2'b00: + //-------------------- + `Intra_chroma_Horizontal: //---horizontal--- + begin + PE2_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window2:0; + PE2_in1 <= 0; PE2_in2 <= 0; PE2_in3 <= 0; + PE2_IsShift <= 0; PE2_IsStore <= 0; PE2_IsClip <= 0; + PE2_full_bypass <= 1; PE2_round_value <= 0; PE2_shift_len <= 0; + end + `Intra_chroma_Vertical: //---vertical--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE2_in0 <= Intra_mbAddrB_window0; + 3:PE2_in0 <= Intra_mbAddrB_window1; + 2:PE2_in0 <= Intra_mbAddrB_window2; + 1:PE2_in0 <= Intra_mbAddrB_window3; + default:PE2_in0 <= 0; + endcase + PE2_in1 <= 0; PE2_in2 <= 0; PE2_in3 <= 0; + PE2_IsShift <= 0; PE2_IsStore <= 0; PE2_IsClip <= 0; + PE2_full_bypass <= 1; PE2_round_value <= 0; PE2_shift_len <= 0; + end + `Intra_chroma_Plane: //---plane--- + begin + if (blk4x4_intra_calculate_counter != 0) + //need seed, blk4x4 = 16 | 18 | 20 | 22 + //do not need seed,blk4x4 = 17 | 19 | 21 | 23 + PE2_in0 <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)? + seed:PE2_out_reg; + else + PE2_in0 <= 0; + if (blk4x4_intra_calculate_counter != 0) + PE2_in1 <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)? + c_ext:b_ext; + else + PE2_in1 <= 0; + PE2_in2 <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)? + c_ext:0; + PE2_in3 <= 0; + PE2_IsShift <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)? + 1'b1:1'b0; + PE2_IsStore <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0; + PE2_IsClip <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0; + PE2_full_bypass <= 1'b0; + PE2_round_value <= (blk4x4_intra_calculate_counter != 0)? 5'd16:5'd0; + PE2_shift_len <= (blk4x4_intra_calculate_counter != 0)? 3'd5 :3'd0; + end + default: + begin + PE2_in0 <= 0; PE2_in1 <= 0; PE2_in2 <= 0; PE2_in3 <= 0; + PE2_IsShift <= 0; PE2_IsStore <= 0; PE2_IsClip <= 0; + PE2_full_bypass <= 0; PE2_round_value <= 0; PE2_shift_len <= 0; + end + endcase + else + begin + PE2_in0 <= 0; PE2_in1 <= 0; PE2_in2 <= 0; PE2_in3 <= 0; + PE2_IsShift <= 0; PE2_IsStore <= 0; PE2_IsClip <= 0; + PE2_full_bypass <= 0; PE2_round_value <= 0; PE2_shift_len <= 0; + end + + //---- + //PE3 | + //---- + always @ (mb_type_general or blk4x4_rec_counter or blk4x4_intra_calculate_counter + or Intra4x4_predmode or Intra16x16_predmode or Intra_chroma_predmode + or mbAddrA_availability or mbAddrB_availability + or Intra_mbAddrA_window0 or Intra_mbAddrA_window1 or Intra_mbAddrA_window2 or Intra_mbAddrA_window3 + or Intra_mbAddrB_window0 or Intra_mbAddrB_window1 or Intra_mbAddrB_window2 or Intra_mbAddrB_window3 + or Intra_mbAddrC_window0 or Intra_mbAddrC_window1 or Intra_mbAddrC_window2 or Intra_mbAddrC_window3 + + or Intra_mbAddrA_reg12 or Intra_mbAddrA_reg13 or Intra_mbAddrA_reg14 or Intra_mbAddrA_reg15 + or Intra_mbAddrB_reg13 or Intra_mbAddrB_reg14 or Intra_mbAddrB_reg15 + or blk4x4_pred_output0 or blk4x4_pred_output4 or blk4x4_pred_output5 + or blk4x4_pred_output6 or blk4x4_pred_output8 or blk4x4_pred_output9 + or PE3_out_reg + + or seed or b_ext or c_ext) + //Intra 4x4 + if (mb_type_general[3:2] == 2'b11 && blk4x4_rec_counter < 16) + case (Intra4x4_predmode) + `Intra4x4_Vertical: //---Vertical--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE3_in0 <= Intra_mbAddrB_window0; + 3:PE3_in0 <= Intra_mbAddrB_window1; + 2:PE3_in0 <= Intra_mbAddrB_window2; + 1:PE3_in0 <= Intra_mbAddrB_window3; + default:PE3_in0 <= 0; + endcase + PE3_in1 <= 0; PE3_in2 <= 0; PE3_in3 <= 0; + PE3_IsShift <= 0; PE3_IsStore <= 0; PE3_IsClip <= 0; + PE3_full_bypass <= 1; PE3_round_value <= 0; PE3_shift_len <= 0; + end + `Intra4x4_Horizontal: //---Horizontal--- + begin + PE3_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window3:0; + PE3_in1 <= 0; PE3_in2 <= 0; PE3_in3 <= 0; + PE3_IsShift <= 0; PE3_IsStore <= 0; PE3_IsClip <= 0; + PE3_full_bypass <= 1; PE3_round_value <= 0; PE3_shift_len <= 0; + end + //------------- + //no PE2 for DC + //4'b0010: + //------------- + `Intra4x4_Diagonal_Down_Left: //---diagonal down-left--- + begin + case (blk4x4_intra_calculate_counter) + 4:begin PE3_in0 <= Intra_mbAddrB_window3; PE3_in1 <= Intra_mbAddrC_window1; + PE3_in2 <= Intra_mbAddrC_window0; end + 3:begin PE3_in0 <= Intra_mbAddrC_window0; PE3_in1 <= Intra_mbAddrC_window2; + PE3_in2 <= Intra_mbAddrC_window1; end + 2:begin PE3_in0 <= Intra_mbAddrC_window1; PE3_in1 <= Intra_mbAddrC_window3; + PE3_in2 <= Intra_mbAddrC_window2; end + 1:begin PE3_in0 <= Intra_mbAddrC_window2; PE3_in1 <= Intra_mbAddrC_window3; + PE3_in2 <= Intra_mbAddrC_window3; end + default:begin PE3_in0 <= 0;PE3_in1 <= 0;PE3_in2 <= 0; end + endcase + PE3_in3 <= 0; + PE3_IsShift <= (blk4x4_intra_calculate_counter == 0)? 1'b0:1'b1; + PE3_IsStore <= 1'b0; PE3_IsClip <= 1'b0; PE3_full_bypass <= 1'b0; + PE3_round_value <= (blk4x4_intra_calculate_counter == 0)? 5'd0:5'd2; // +2 + PE3_shift_len <= (blk4x4_intra_calculate_counter == 0)? 3'd0:3'd2; // >>2 + end + `Intra4x4_Diagonal_Down_Right: //---diagonal down-right--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE3_in0 <= Intra_mbAddrA_window1; + 3:PE3_in0 <= blk4x4_pred_output8; + 2:PE3_in0 <= blk4x4_pred_output4; + 1:PE3_in0 <= blk4x4_pred_output0; + default:PE3_in0 <= 0; + endcase + PE3_in1 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrA_window3:0; + PE3_in2 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrA_window2:0; + PE3_in3 <= 0; + PE3_IsShift <= (blk4x4_intra_calculate_counter == 0)? 1'b0:1'b1; + PE3_IsStore <= 1'b0; PE3_IsClip <= 1'b0; + PE3_full_bypass <= (blk4x4_intra_calculate_counter == 4)? 1'b0:1'b1; + PE3_round_value <= (blk4x4_intra_calculate_counter == 0)? 5'd0:5'd2; // +2 + PE3_shift_len <= (blk4x4_intra_calculate_counter == 0)? 3'd0:3'd2; // >>2 + end + `Intra4x4_Vertical_Right: //---vertical right--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE3_in0 <= Intra_mbAddrA_window0; + 3:PE3_in0 <= blk4x4_pred_output4; + 2:PE3_in0 <= blk4x4_pred_output5; + 1:PE3_in0 <= blk4x4_pred_output6; + default:PE3_in0 <= 0; + endcase + PE3_in1 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrA_window2:0; + PE3_in2 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrA_window1:0; + PE3_in3 <= 0; + PE3_IsShift <= (blk4x4_intra_calculate_counter == 0)? 1'b0:1'b1; + PE3_IsStore <= 1'b0; PE3_IsClip <= 1'b0; + PE3_full_bypass <= (blk4x4_intra_calculate_counter == 4)? 1'b0:1'b1; + PE3_round_value <= (blk4x4_intra_calculate_counter == 0)? 5'd0:5'd2; // +2 + PE3_shift_len <= (blk4x4_intra_calculate_counter == 0)? 3'd0:3'd2; // >>2 + end + `Intra4x4_Horizontal_Down: //---horizontal down--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE3_in0 <= Intra_mbAddrA_window2; + 3:PE3_in0 <= Intra_mbAddrA_window1; + 2:PE3_in0 <= blk4x4_pred_output8; + 1:PE3_in0 <= blk4x4_pred_output9; + default:PE3_in0 <= 0; + endcase + PE3_in1 <= (blk4x4_intra_calculate_counter == 4 || blk4x4_intra_calculate_counter == 3)? + Intra_mbAddrA_window3:0; + PE3_in2 <= (blk4x4_intra_calculate_counter == 3)? Intra_mbAddrA_window2:0; + PE3_in3 <= 0; + PE3_IsShift <= (blk4x4_intra_calculate_counter == 3)? 1'b1:1'b0; + PE3_IsStore <= 1'b0; PE3_IsClip <= 1'b0; + PE3_full_bypass <= (blk4x4_intra_calculate_counter == 2 || + blk4x4_intra_calculate_counter == 1)? 1'b1:1'b0; + PE3_round_value <= (blk4x4_intra_calculate_counter == 4)? 5'd1: + (blk4x4_intra_calculate_counter == 3)? 5'd2:5'd0; + PE3_shift_len <= (blk4x4_intra_calculate_counter == 4)? 3'd1: + (blk4x4_intra_calculate_counter == 3)? 3'd2:3'd0; + end + `Intra4x4_Vertical_Left: //---vertical left--- + begin + case (blk4x4_intra_calculate_counter) + 4:begin PE3_in0 <= Intra_mbAddrB_window1; PE3_in1 <= Intra_mbAddrB_window3; + PE3_in2 <= Intra_mbAddrB_window2; end + 3:begin PE3_in0 <= Intra_mbAddrB_window2; PE3_in1 <= Intra_mbAddrC_window0; + PE3_in2 <= Intra_mbAddrB_window3; end + 2:begin PE3_in0 <= Intra_mbAddrB_window3; PE3_in1 <= Intra_mbAddrC_window1; + PE3_in2 <= Intra_mbAddrC_window0; end + 1:begin PE3_in0 <= Intra_mbAddrC_window0; PE3_in1 <= Intra_mbAddrC_window2; + PE3_in2 <= Intra_mbAddrC_window1; end + default:begin PE3_in0 <= 0;PE3_in1 <= 0;PE3_in2 <= 0; end + endcase + PE3_in3 <= 0; + PE3_IsShift <= (blk4x4_intra_calculate_counter == 0)? 1'b0:1'b1; + PE3_IsStore <= 1'b0; PE3_IsClip <= 1'b0; PE3_full_bypass <= 1'b0; + PE3_round_value <= (blk4x4_intra_calculate_counter == 0)? 5'd0:5'd2; // +2 + PE3_shift_len <= (blk4x4_intra_calculate_counter == 0)? 3'd0:3'd2; // >>2 + end + `Intra4x4_Horizontal_Up: //---horizontal up--- + begin + PE3_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window3:0; + PE3_in1 <= 0; PE3_in2 <= 0; PE3_in3 <= 0; + PE3_IsShift <= 0; PE3_IsStore <= 0; PE3_IsClip <= 0; + PE3_full_bypass <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0; + PE3_round_value <= 0; PE3_shift_len <= 0; + end + default: + begin + PE3_in0 <= 0; PE3_in1 <= 0; PE3_in2 <= 0; PE3_in3 <= 0; + PE3_IsShift <= 0; PE3_IsStore <= 0; PE3_IsClip <= 0; + PE3_full_bypass <= 0; PE3_round_value <= 0; PE3_shift_len <= 0; + end + endcase + //Intra16x16 + else if (mb_type_general[3:2] == 2'b10 && blk4x4_rec_counter < 16) + case (Intra16x16_predmode) + `Intra16x16_Vertical: //---Vertical--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE3_in0 <= Intra_mbAddrB_window0; + 3:PE3_in0 <= Intra_mbAddrB_window1; + 2:PE3_in0 <= Intra_mbAddrB_window2; + 1:PE3_in0 <= Intra_mbAddrB_window3; + default:PE3_in0 <= 0; + endcase + PE3_in1 <= 0; PE3_in2 <= 0; PE3_in3 <= 0; + PE3_IsShift <= 0; PE3_IsStore <= 0; PE3_IsClip <= 0; + PE3_full_bypass <= 1; PE3_round_value <= 0; PE3_shift_len <= 0; + end + `Intra16x16_Horizontal: //---Horizontal--- + begin + PE3_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window3:0; + PE3_in1 <= 0; PE3_in2 <= 0; PE3_in3 <= 0; + PE3_IsShift <= 0; PE3_IsStore <= 0; PE3_IsClip <= 0; + PE3_full_bypass <= 1; PE3_round_value <= 0; PE3_shift_len <= 0; + end + `Intra16x16_DC: //---DC--- + if (blk4x4_rec_counter == 0) + case (blk4x4_intra_calculate_counter) + 4:begin // M2 + N2 + O2 + P2 + PE3_in0 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg12; + PE3_in1 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg13; + PE3_in2 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg14; + PE3_in3 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg15; + PE3_IsShift <= 0; PE3_IsStore <= 1; PE3_IsClip <= 0; + PE3_full_bypass <= 0; PE3_round_value <= 0; PE3_shift_len <= 0; end + 3:begin // PE3 output + N1 + O1 + P1 + PE3_in0 <= PE3_out_reg; + PE3_in1 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg13; + PE3_in2 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg14; + PE3_in3 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg15; + PE3_IsShift <= 0; PE3_IsStore <= 1; PE3_IsClip <= 0; + PE3_full_bypass <= 0; PE3_round_value <= 0; PE3_shift_len <= 0; end + default:begin + PE3_in0 <= 0; PE3_in1 <= 0; PE3_in2 <= 0; PE3_in3 <= 0; + PE3_IsShift <= 0; PE3_IsStore <= 0; PE3_IsClip <= 0; + PE3_full_bypass <= 0; PE3_round_value <= 0; PE3_shift_len <= 0; end + endcase + else + begin + PE3_in0 <= 0; PE3_in1 <= 0; PE3_in2 <= 0; PE3_in3 <= 0; + PE3_IsShift <= 0; PE3_IsStore <= 0; PE3_IsClip <= 0; + PE3_full_bypass <= 0; PE3_round_value <= 0; PE3_shift_len <= 0; + end + `Intra16x16_Plane: //---plane--- + begin + if (blk4x4_intra_calculate_counter != 0) + //blk0,2,4,6,8,10,12,14,calc counter == 3'b100:PE3_in0 <= seed; + //other cases :PE3_in0 <= left pixel output + PE3_in0 <= (blk4x4_intra_calculate_counter == 4 && blk4x4_rec_counter[0] == 1'b0)? + seed:PE3_out_reg; + else + PE3_in0 <= 0; + if (blk4x4_intra_calculate_counter != 0) + //blk0,2,8,10,calc counter == 3'b100:PE3_in1 <= c_ext x 4 + //other cases :PE3_in1 <= b_ext + PE3_in1 <= (blk4x4_intra_calculate_counter == 4 && !blk4x4_rec_counter[2] && !blk4x4_rec_counter[0])? + {c_ext[13:0],2'b0}:b_ext; + else + PE3_in1 <= 0; + //blk4,6,12,14,calc counter == 3'b100:PE3_in2 <= c_ext x 2; + //other cases :PE3_in2 <= 0 + PE3_in2 <= (blk4x4_intra_calculate_counter == 3'b100 && blk4x4_rec_counter[2] && !blk4x4_rec_counter[0])? + {c_ext[14:0],1'b0}:0; + //blk4,6,12,14,calc counter == 3'b100:PE3_in3 <= c_ext; + //other cases :PE3_in3 <= 0 + PE3_in3 <= (blk4x4_intra_calculate_counter == 3'b100 && blk4x4_rec_counter[2] && !blk4x4_rec_counter[0])? + c_ext:0; + PE3_IsShift <= 1'b0; + PE3_IsStore <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0; + PE3_IsClip <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0; + PE3_full_bypass <= 1'b0; + PE3_round_value <= (blk4x4_intra_calculate_counter != 0)? 5'd16:5'd0; + PE3_shift_len <= (blk4x4_intra_calculate_counter != 0)? 3'd5 :3'd0; + end + endcase + //Chroma + else if (mb_type_general[3] == 1'b1 && blk4x4_rec_counter > 15) + case (Intra_chroma_predmode) + //-------------------- + //no PE2 for Chroma DC + //2'b00: + //-------------------- + `Intra_chroma_Horizontal: //---horizontal--- + begin + PE3_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window3:0; + PE3_in1 <= 0; PE3_in2 <= 0; PE3_in3 <= 0; + PE3_IsShift <= 0; PE3_IsStore <= 0; PE3_IsClip <= 0; + PE3_full_bypass <= 1; PE3_round_value <= 0; PE3_shift_len <= 0; + end + `Intra_chroma_Vertical: //---vertical--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE3_in0 <= Intra_mbAddrB_window0; + 3:PE3_in0 <= Intra_mbAddrB_window1; + 2:PE3_in0 <= Intra_mbAddrB_window2; + 1:PE3_in0 <= Intra_mbAddrB_window3; + default:PE3_in0 <= 0; + endcase + PE3_in1 <= 0; PE3_in2 <= 0; PE3_in3 <= 0; + PE3_IsShift <= 0; PE3_IsStore <= 0; PE3_IsClip <= 0; + PE3_full_bypass <= 1; PE3_round_value <= 0; PE3_shift_len <= 0; + end + `Intra_chroma_Plane: //---plane--- + begin + if (blk4x4_intra_calculate_counter != 0) + //need seed, blk4x4 = 16 | 18 | 20 | 22 + //do not need seed,blk4x4 = 17 | 19 | 21 | 23 + PE3_in0 <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)? + seed:PE3_out_reg; + else + PE3_in0 <= 0; + if (blk4x4_intra_calculate_counter != 0) + PE3_in1 <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)? + {c_ext[14:0],1'b0}:b_ext; + else + PE3_in1 <= 0; + PE3_in2 <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)? + c_ext:0; + PE3_in3 <= 0; + PE3_IsShift <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)? + 1'b1:1'b0; + PE3_IsStore <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0; + PE3_IsClip <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0; + PE3_full_bypass <= 1'b0; + PE3_round_value <= (blk4x4_intra_calculate_counter != 0)? 5'd16:5'd0; + PE3_shift_len <= (blk4x4_intra_calculate_counter != 0)? 3'd5 :3'd0; + end + default: + begin + PE3_in0 <= 0; PE3_in1 <= 0; PE3_in2 <= 0; PE3_in3 <= 0; + PE3_IsShift <= 0; PE3_IsStore <= 0; PE3_IsClip <= 0; + PE3_full_bypass <= 0; PE3_round_value <= 0; PE3_shift_len <= 0; + end + endcase + else + begin + PE3_in0 <= 0; PE3_in1 <= 0; PE3_in2 <= 0; PE3_in3 <= 0; + PE3_IsShift <= 0; PE3_IsStore <= 0; PE3_IsClip <= 0; + PE3_full_bypass <= 0; PE3_round_value <= 0; PE3_shift_len <= 0; + end +endmodule + +module PE (clk,reset_n,in0,in1,in2,in3,IsShift,IsStore,IsClip,full_bypass,round_value,shift_len, + PE_out_reg,PE_out,sum_out); + input clk,reset_n; + input [15:0] in0,in1,in2,in3; + input IsShift; + input IsStore; + input IsClip; + input full_bypass; + input [4:0] round_value; + input [2:0] shift_len; + + + output [15:0] PE_out_reg; + output [7:0] PE_out; + output [15:0] sum_out; + reg [15:0] PE_out_reg; + + wire [15:0] sum1; + wire [15:0] sum2; + wire [16:0] round_tmp; + wire [15:0] round_out; + wire [7:0] clip_out; + + assign sum1 = (full_bypass)? 0:(in0 + in1); + assign sum2 = (full_bypass)? 0:((IsShift)? {in2[14:0],1'b0}:(in2 + in3)); + assign sum_out = (full_bypass)? 0:(sum1 + sum2); + + always @ (posedge clk) + if (reset_n == 1'b0) + PE_out_reg <= 0; + else if (IsStore) + PE_out_reg <= sum_out; + + assign round_tmp = sum_out + round_value; + assign round_out = round_tmp >> shift_len; + assign clip_out = (IsClip)? ((round_out[15] == 1'b1)? 8'd0:((round_out[15:8] == 0)? round_out[7:0]:8'd255)) + :round_out[7:0]; + assign PE_out = (full_bypass)? in0[7:0]:clip_out; +endmodule \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/Intra_pred_pipeline.v b/demo_chip_rtl/rtl/nova/tags/Start/src/Intra_pred_pipeline.v new file mode 100644 index 0000000..de56b24 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/Intra_pred_pipeline.v @@ -0,0 +1,743 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : Intra_pred_pipeline.v +// Generated : Aug 4, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Intra16x16,Intra4x4 prediction pipeline +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module Intra_pred_pipeline (clk,reset_n,mb_type_general,blk4x4_rec_counter, + trigger_blk4x4_intra_pred,mb_num_v,mb_num_h,blk4x4_sum_counter,NextMB_IsSkip, + Intra16x16_predmode,Intra4x4_predmode_CurrMb,Intra_chroma_predmode, + + Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3, + Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7, + Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11, + Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15, + + Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3, + Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7, + Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11, + Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15, + Intra_mbAddrD_window, + + Intra4x4_predmode,blk4x4_intra_preload_counter,blk4x4_intra_precompute_counter, + blk4x4_intra_calculate_counter,end_of_one_blk4x4_intra, + blkAddrA_availability,blkAddrB_availability,mbAddrA_availability,mbAddrB_availability,mbAddrC_availability, + main_seed,plane_b_reg,plane_c_reg, + Intra_mbAddrB_RAM_rd,Intra_mbAddrB_RAM_rd_addr + ); + input clk,reset_n; + input [3:0] mb_type_general; + input [4:0] blk4x4_rec_counter; + input trigger_blk4x4_intra_pred; + input [3:0] mb_num_v,mb_num_h; + input [2:0] blk4x4_sum_counter; + input NextMB_IsSkip; + input [1:0] Intra16x16_predmode; + input [63:0] Intra4x4_predmode_CurrMb; + input [1:0] Intra_chroma_predmode; + + input [7:0] Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3; + input [7:0] Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7; + input [7:0] Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11; + input [7:0] Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15; + + input [7:0] Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3; + input [7:0] Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7; + input [7:0] Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11; + input [7:0] Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15; + input [7:0] Intra_mbAddrD_window; + + output [3:0] Intra4x4_predmode; + output [2:0] blk4x4_intra_preload_counter; + output [3:0] blk4x4_intra_precompute_counter; + output [2:0] blk4x4_intra_calculate_counter; + output end_of_one_blk4x4_intra; + output blkAddrA_availability,blkAddrB_availability; + output mbAddrA_availability,mbAddrB_availability,mbAddrC_availability; + output [15:0] main_seed; + output [11:0] plane_b_reg,plane_c_reg; + output Intra_mbAddrB_RAM_rd; + output [6:0] Intra_mbAddrB_RAM_rd_addr; + + reg [3:0] Intra4x4_predmode; + reg [2:0] blk4x4_intra_preload_counter; + reg [3:0] blk4x4_intra_precompute_counter; + reg [2:0] blk4x4_intra_calculate_counter; + + reg [11:0] plane_b_reg,plane_c_reg; + wire Intra_mbAddrB_RAM_rd; + wire [6:0] Intra_mbAddrB_RAM_rd_addr; + wire end_of_one_blk4x4_intra; + wire blkAddrA_availability,blkAddrB_availability; + wire mbAddrA_availability,mbAddrB_availability; + + //---------------------------------------------------------------------------------------- + //Intra4x4 prediction mode for current 4x4 block + //---------------------------------------------------------------------------------------- + always @ (Intra4x4_predmode_CurrMb or blk4x4_rec_counter or mb_type_general) + if (mb_type_general == `MB_Intra4x4) + case (blk4x4_rec_counter) + 0 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[3:0]; + 1 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[7:4]; + 2 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[11:8]; + 3 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[15:12]; + 4 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[19:16]; + 5 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[23:20]; + 6 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[27:24]; + 7 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[31:28]; + 8 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[35:32]; + 9 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[39:36]; + 10:Intra4x4_predmode <= Intra4x4_predmode_CurrMb[43:40]; + 11:Intra4x4_predmode <= Intra4x4_predmode_CurrMb[47:44]; + 12:Intra4x4_predmode <= Intra4x4_predmode_CurrMb[51:48]; + 13:Intra4x4_predmode <= Intra4x4_predmode_CurrMb[55:52]; + 14:Intra4x4_predmode <= Intra4x4_predmode_CurrMb[59:56]; + 15:Intra4x4_predmode <= Intra4x4_predmode_CurrMb[63:60]; + default:Intra4x4_predmode <= 4'b1111; + endcase + else + Intra4x4_predmode <= 4'b1111; + + //availability for intra4x4 predmode = Intra4x4_DC only + assign blkAddrA_availability = (mb_type_general == `MB_Intra4x4 && Intra4x4_predmode == `Intra4x4_DC && + blk4x4_rec_counter < 16 && ((blk4x4_rec_counter == 0 || blk4x4_rec_counter == 2 || blk4x4_rec_counter == 8 || + blk4x4_rec_counter == 10) && mb_num_h == 0))? 1'b0:1'b1; + + assign blkAddrB_availability = (mb_type_general == `MB_Intra4x4 && Intra4x4_predmode == `Intra4x4_DC && + blk4x4_rec_counter < 16 && ((blk4x4_rec_counter == 0 || blk4x4_rec_counter == 1 || blk4x4_rec_counter == 4 || + blk4x4_rec_counter == 5) && mb_num_v == 0))? 1'b0:1'b1; + + //availability for whole intra predicted MB (both intra16x16 & intra4x4) + //assign mbAddrA_availability = (mb_type_general[3] && mb_num_h != 0)? 1'b1:1'b0; + //assign mbAddrB_availability = (mb_type_general[3] && mb_num_v != 0)? 1'b1:1'b0; + assign mbAddrA_availability = (mb_type_general[3] && mb_num_h != 0)? 1'b1:1'b0; + assign mbAddrB_availability = (mb_type_general[3] && mb_num_v != 0)? 1'b1:1'b0; + assign mbAddrC_availability = (mb_type_general[3] && mb_num_v != 0 && mb_num_h != 10)? 1'b1:1'b0; + + //---------------------------------------------------------------------------------------- + //Intra prediction step control counter + //---------------------------------------------------------------------------------------- + //1.Preload upper pels counter + always @ (posedge clk) + if (reset_n == 1'b0) + blk4x4_intra_preload_counter <= 0; + else if (trigger_blk4x4_intra_pred) + begin + //Chroma + if (mb_type_general[3] == 1'b1 && (blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20)) + case (Intra_chroma_predmode) + `Intra_chroma_DC :blk4x4_intra_preload_counter <= (mbAddrB_availability)? 3'b011:3'b000; + `Intra_chroma_Horizontal:blk4x4_intra_preload_counter <= 3'b000; + `Intra_chroma_Vertical :blk4x4_intra_preload_counter <= 3'b011; + `Intra_chroma_Plane :blk4x4_intra_preload_counter <= 3'b011; + endcase + //Luma + // Intra16x16 + else if (mb_type_general[3:2] == 2'b10 && blk4x4_rec_counter == 0) + case (Intra16x16_predmode) + `Intra16x16_Vertical :blk4x4_intra_preload_counter <= 3'b101; + `Intra16x16_Horizontal:blk4x4_intra_preload_counter <= 3'b000; + `Intra16x16_DC :blk4x4_intra_preload_counter <= (mbAddrB_availability)? 3'b101:3'b000; + `Intra16x16_Plane :blk4x4_intra_preload_counter <= 3'b101; + endcase + // Intra4x4 + else if (mb_type_general[3:2] == 2'b11 && (blk4x4_rec_counter == 0 || blk4x4_rec_counter == 1 + || blk4x4_rec_counter == 4 || blk4x4_rec_counter == 5)) + case (Intra4x4_predmode) + `Intra4x4_Vertical :blk4x4_intra_preload_counter <= 3'b010; + `Intra4x4_Horizontal :blk4x4_intra_preload_counter <= 3'b000; + `Intra4x4_DC :blk4x4_intra_preload_counter <= (mbAddrB_availability)? 3'b010:3'b000; + `Intra4x4_Diagonal_Down_Left :blk4x4_intra_preload_counter <= 3'b011; //need mbAddrC + `Intra4x4_Diagonal_Down_Right:blk4x4_intra_preload_counter <= (blk4x4_rec_counter == 0)? 3'b010:3'b011;//need mbAddrD + `Intra4x4_Vertical_Right :blk4x4_intra_preload_counter <= (blk4x4_rec_counter == 0)? 3'b010:3'b011;//need mbAddrD + `Intra4x4_Horizontal_Down :blk4x4_intra_preload_counter <= (blk4x4_rec_counter == 0)? 3'b010:3'b011;//need mbAddrD + `Intra4x4_Vertical_Left :blk4x4_intra_preload_counter <= 3'b011; //need mbAddrC + `Intra4x4_Horizontal_Up :blk4x4_intra_preload_counter <= 3'b000; + endcase + end + else if (blk4x4_intra_preload_counter != 0) + blk4x4_intra_preload_counter <= blk4x4_intra_preload_counter - 1; + + //2.Precomputation for plane mode counter + always @ (posedge clk) + if (reset_n == 1'b0) + blk4x4_intra_precompute_counter <= 0; + //Intra16x16 plane mode: 10 cycle + 1 cycle (seed) + else if (mb_type_general[2] == 1'b0 && blk4x4_rec_counter == 0 && Intra16x16_predmode == `Intra16x16_Plane && blk4x4_intra_preload_counter == 3'b001) + blk4x4_intra_precompute_counter <= 4'b1011; + //Chroma8x8 plane mode: 6 cycle + 1 cycle (seed) + else if ((blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20) && Intra_chroma_predmode == `Intra_chroma_Plane && blk4x4_intra_preload_counter == 3'b001) + blk4x4_intra_precompute_counter <= 4'b0111; + else if (blk4x4_intra_precompute_counter != 0) + blk4x4_intra_precompute_counter <= blk4x4_intra_precompute_counter - 1; + + //3.Intra prediction calculation counter + always @ (posedge clk) + if (reset_n == 1'b0) + blk4x4_intra_calculate_counter <= 0; + //Intra16x16 Luma + else if (mb_type_general[3:2] == 2'b10 && blk4x4_rec_counter < 16) + begin + if (blk4x4_rec_counter == 0) + case (Intra16x16_predmode) + `Intra16x16_Vertical: + if (blk4x4_intra_preload_counter == 3'b001) + blk4x4_intra_calculate_counter <= 3'b100; + else if (blk4x4_intra_calculate_counter != 0) + blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1; + `Intra16x16_Horizontal: + if (trigger_blk4x4_intra_pred) + blk4x4_intra_calculate_counter <= 3'b100; + else if (blk4x4_intra_calculate_counter != 0) + blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1; + `Intra16x16_DC: + if (mbAddrB_availability && blk4x4_intra_preload_counter == 3'b001) + blk4x4_intra_calculate_counter <= 3'b100; + else if (!mbAddrB_availability && trigger_blk4x4_intra_pred) + blk4x4_intra_calculate_counter <= 3'b100; + else if (blk4x4_intra_calculate_counter != 0) + blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1; + `Intra16x16_Plane: + if (blk4x4_intra_precompute_counter == 4'b0001) + blk4x4_intra_calculate_counter <= 3'b100; + else if (blk4x4_intra_calculate_counter != 0) + blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1; + endcase + else + begin + if (trigger_blk4x4_intra_pred) + blk4x4_intra_calculate_counter <= 3'b100; + else if (blk4x4_intra_calculate_counter != 0) + blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1; + end + end + //Intra4x4 Luma + else if (mb_type_general[3:2] == 2'b11 && blk4x4_rec_counter < 16) + begin + if (blk4x4_rec_counter == 0 || blk4x4_rec_counter == 1 || + blk4x4_rec_counter == 4 || blk4x4_rec_counter == 5) + case (Intra4x4_predmode) + `Intra4x4_Horizontal,`Intra4x4_Horizontal_Up://Intra4x4 prediction modes do NOT need preload + if (trigger_blk4x4_intra_pred) + blk4x4_intra_calculate_counter <= 3'b100; + else if (blk4x4_intra_calculate_counter != 0) + blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1; + `Intra4x4_DC: //Intra4x4 prediction modes may or may NOT need preload + if (mbAddrB_availability == 1'b1) //need reload + begin + if (blk4x4_intra_preload_counter == 3'b001) + blk4x4_intra_calculate_counter <= 3'b100; + else if (blk4x4_intra_calculate_counter != 0) + blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1; + end + else //do not need reload + begin + if (trigger_blk4x4_intra_pred) + blk4x4_intra_calculate_counter <= 3'b100; + else if (blk4x4_intra_calculate_counter != 0) + blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1; + end + default: //other Intra4x4 prediction modes that needs preload + if (blk4x4_intra_preload_counter == 3'b001) + blk4x4_intra_calculate_counter <= 3'b100; + else if (blk4x4_intra_calculate_counter != 0) + blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1; + endcase + else if (trigger_blk4x4_intra_pred) + blk4x4_intra_calculate_counter <= 3'b100; + else if (blk4x4_intra_calculate_counter != 0) + blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1; + end + //Chroma + else if (blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20) + case (Intra_chroma_predmode) + `Intra_chroma_DC: + if ((mbAddrB_availability && blk4x4_intra_preload_counter == 3'b001) || (!mbAddrB_availability && trigger_blk4x4_intra_pred)) + blk4x4_intra_calculate_counter <= 3'b100; + else if (blk4x4_intra_calculate_counter != 0) + blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1; + `Intra_chroma_Horizontal: + if (trigger_blk4x4_intra_pred) + blk4x4_intra_calculate_counter <= 3'b100; + else if (blk4x4_intra_calculate_counter != 0) + blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1; + `Intra_chroma_Vertical: + if (blk4x4_intra_preload_counter == 3'b001) + blk4x4_intra_calculate_counter <= 3'b100; + else if (blk4x4_intra_calculate_counter != 0) + blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1; + `Intra_chroma_Plane: //plane + if (blk4x4_intra_precompute_counter == 4'b0001) + blk4x4_intra_calculate_counter <= 3'b100; + else if (blk4x4_intra_calculate_counter != 0) + blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1; + endcase + else + begin + if (trigger_blk4x4_intra_pred) + blk4x4_intra_calculate_counter <= 3'b100; + else if (blk4x4_intra_calculate_counter != 0) + blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1; + end + + assign end_of_one_blk4x4_intra = (blk4x4_intra_calculate_counter == 3'd1)? 1'b1:1'b0; + //---------------------------------------------------------------------------------------- + //1.Preload + // For intra4x4,preload_counter == 3'b010 means preload mbAddrC or mbAddrD + // preload_counter == 3'b001 means preload mbAddrB + //---------------------------------------------------------------------------------------- + wire [6:0] Intra_mbAddrB_RAM_addr_bp; + reg [5:0] Intra_mbAddrB_RAM_addr_sp; + reg [1:0] Intra_mbAddrB_RAM_addr_ip; + + wire Intra_mbAddrB_RAM_rd_for_mbAddrD; + assign Intra_mbAddrB_RAM_rd_for_mbAddrD = (blk4x4_sum_counter == 3'b0 && + (blk4x4_rec_counter == 15 || blk4x4_rec_counter == 19 || blk4x4_rec_counter == 23) && + mb_num_h != 10 && mb_num_v != 0 && !NextMB_IsSkip)? 1'b1:1'b0; + + assign Intra_mbAddrB_RAM_rd = ((blk4x4_intra_preload_counter != 0 && blk4x4_intra_preload_counter != 1) || Intra_mbAddrB_RAM_rd_for_mbAddrD)? 1'b1:1'b0; + + // base pointer, [43:0] luma, [65:44] Chroma Cb, [87:66] Chroma Cr + assign Intra_mbAddrB_RAM_addr_bp = (Intra_mbAddrB_RAM_rd)? ((blk4x4_rec_counter > 15)? ((blk4x4_rec_counter > 19)? 7'd66:7'd44):0):0; + + // shift pointer,x2 for chroma,x4 for luma + always @ (Intra_mbAddrB_RAM_rd_for_mbAddrD or Intra_mbAddrB_RAM_rd or mb_num_h or + blk4x4_rec_counter or Intra4x4_predmode or blk4x4_intra_preload_counter) + if (Intra_mbAddrB_RAM_rd_for_mbAddrD) + Intra_mbAddrB_RAM_addr_sp <= (blk4x4_rec_counter < 16)? {mb_num_h,2'b0}:{1'b0,mb_num_h,1'b0}; + else if (Intra_mbAddrB_RAM_rd) + begin + if (blk4x4_rec_counter < 16) + Intra_mbAddrB_RAM_addr_sp <= ((Intra4x4_predmode == `Intra4x4_Diagonal_Down_Left + || Intra4x4_predmode == `Intra4x4_Vertical_Left) && blk4x4_rec_counter == 5 + && blk4x4_intra_preload_counter == 3'b011)? //read for mbAddrC + {(mb_num_h + 1),2'b0}:{mb_num_h,2'b0}; + else + Intra_mbAddrB_RAM_addr_sp <= {1'b0,mb_num_h,1'b0}; + end + else + Intra_mbAddrB_RAM_addr_sp <= 0; + + // pointer for relative address of each 4x4 block inside a MB + always @ (Intra_mbAddrB_RAM_rd or blk4x4_rec_counter or blk4x4_intra_preload_counter or + mb_type_general[3:2] or Intra4x4_predmode or Intra_mbAddrB_RAM_rd_for_mbAddrD) + if (blk4x4_rec_counter < 16 && Intra_mbAddrB_RAM_rd) //luma + begin + if (blk4x4_intra_preload_counter != 0 && blk4x4_intra_preload_counter != 1) + begin + if (mb_type_general[3:2] == 2'b10) //Intra16x16 + case (blk4x4_intra_preload_counter) + 3'b101:Intra_mbAddrB_RAM_addr_ip <= 0; + 3'b100:Intra_mbAddrB_RAM_addr_ip <= 2'b01; + 3'b011:Intra_mbAddrB_RAM_addr_ip <= 2'b10; + 3'b010:Intra_mbAddrB_RAM_addr_ip <= 2'b11; + default:Intra_mbAddrB_RAM_addr_ip <= 0; + endcase + else //Intra4x4 + begin + if (blk4x4_intra_preload_counter == 3'b010) //For mbAddrB + case (blk4x4_rec_counter) + 0:Intra_mbAddrB_RAM_addr_ip <= 0; + 1:Intra_mbAddrB_RAM_addr_ip <= 2'b01; + 4:Intra_mbAddrB_RAM_addr_ip <= 2'b10; + 5:Intra_mbAddrB_RAM_addr_ip <= 2'b11; + default:Intra_mbAddrB_RAM_addr_ip <= 0; + endcase + else if (Intra4x4_predmode == `Intra4x4_Diagonal_Down_Left + || Intra4x4_predmode == `Intra4x4_Vertical_Left) //For mbAddrC + case (blk4x4_rec_counter) + 0:Intra_mbAddrB_RAM_addr_ip <= 2'b01; + 1:Intra_mbAddrB_RAM_addr_ip <= 2'b10; + 4:Intra_mbAddrB_RAM_addr_ip <= 2'b11; + 5:Intra_mbAddrB_RAM_addr_ip <= 2'b00; + default:Intra_mbAddrB_RAM_addr_ip <= 0; + endcase + else //For mbAddrD + case (blk4x4_rec_counter) + 1:Intra_mbAddrB_RAM_addr_ip <= 2'b00; + 4:Intra_mbAddrB_RAM_addr_ip <= 2'b01; + 5:Intra_mbAddrB_RAM_addr_ip <= 2'b10; + default:Intra_mbAddrB_RAM_addr_ip <= 0; + endcase + end + end + else if (Intra_mbAddrB_RAM_rd_for_mbAddrD) + Intra_mbAddrB_RAM_addr_ip <= 2'b11; + else + Intra_mbAddrB_RAM_addr_ip <= 0; + end + else if (Intra_mbAddrB_RAM_rd) //chroma + Intra_mbAddrB_RAM_addr_ip <= (blk4x4_intra_preload_counter != 0 && blk4x4_intra_preload_counter != 1)? {1'b0,~blk4x4_intra_preload_counter[0]}:2'b01; + else + Intra_mbAddrB_RAM_addr_ip <= 0; + + // pointer for each 4x4 block + assign Intra_mbAddrB_RAM_rd_addr = Intra_mbAddrB_RAM_addr_bp + Intra_mbAddrB_RAM_addr_sp + Intra_mbAddrB_RAM_addr_ip; + + //---------------------------------------------------------------------------------------- + //2.Precomputation + // For Intra16x16 Luma Plane + // cycle11: x1 + x3 | + // cycle10: x2 + x5 | + // cycle9 : x4 + x6 | + // cycle8 : x8 + x7 | Vertical,V For Intra Chroma Plane + // cycle7 : calculate c cycle7: x1 + x3 | + // cycle6 : x1 + x3 | cycle6: x2 + x4 | Vertical,V + // cycle5 : x2 + x5 | cycle5: calculate c + // cycle4 : x4 + x6 | cycle4: x1 + x3 | + // cycle3 : x8 + x7 | Horizontal,H cycle3: x2 + x4 | Horizontal,H + // cycle2 : calculate a & b cycle2 : calculate a & b + // cycle1 : seed cycle1 : seed + //---------------------------------------------------------------------------------------- + // 2.1 precomputation for HV: + reg [14:0] plane_HV_prev_in; + reg [7:0] plane_HV_A1,plane_HV_A2,plane_HV_B1,plane_HV_B2; + reg [1:0] plane_HV_shifter1_len,plane_HV_shifter2_len; + reg plane_HV_mux1_sel,plane_HV_mux2_sel; + reg plane_HV_Is7; + wire [14:0] plane_HV_out; + reg [14:0] plane_HV_out_reg; + + plane_HV_precomputation plane_HV_precomputation ( + .prev_in(plane_HV_prev_in), + .A1(plane_HV_A1), + .A2(plane_HV_A2), + .B1(plane_HV_B1), + .B2(plane_HV_B2), + .shifter1_len(plane_HV_shifter1_len), + .shifter2_len(plane_HV_shifter2_len), + .mux1_sel(plane_HV_mux1_sel), + .mux2_sel(plane_HV_mux2_sel), + .Is7(plane_HV_Is7), + .HV_out(plane_HV_out) + ); + always @ (blk4x4_intra_precompute_counter or mb_type_general[2] or blk4x4_rec_counter or plane_HV_out_reg + or Intra_mbAddrA_reg0 or Intra_mbAddrA_reg1 or Intra_mbAddrA_reg2 or Intra_mbAddrA_reg3 + or Intra_mbAddrA_reg4 or Intra_mbAddrA_reg5 or Intra_mbAddrA_reg6 or Intra_mbAddrA_reg7 + or Intra_mbAddrA_reg8 or Intra_mbAddrA_reg9 or Intra_mbAddrA_reg10 or Intra_mbAddrA_reg11 + or Intra_mbAddrA_reg12 or Intra_mbAddrA_reg13 or Intra_mbAddrA_reg14 or Intra_mbAddrA_reg15 + or Intra_mbAddrB_reg0 or Intra_mbAddrB_reg1 or Intra_mbAddrB_reg2 or Intra_mbAddrB_reg3 + or Intra_mbAddrB_reg4 or Intra_mbAddrB_reg5 or Intra_mbAddrB_reg6 or Intra_mbAddrB_reg7 + or Intra_mbAddrB_reg8 or Intra_mbAddrB_reg9 or Intra_mbAddrB_reg10 or Intra_mbAddrB_reg11 + or Intra_mbAddrB_reg12 or Intra_mbAddrB_reg13 or Intra_mbAddrB_reg14 or Intra_mbAddrB_reg15 + or Intra_mbAddrD_window) + //Intra16x16 plane + if (mb_type_general[2] == 1'b0 && blk4x4_rec_counter == 0) + case (blk4x4_intra_precompute_counter) + 11,6: // x1,x3 + begin + plane_HV_prev_in <= 0; plane_HV_Is7 <= 1'b0; + plane_HV_A1 <= (blk4x4_intra_precompute_counter == 11)? Intra_mbAddrA_reg8 :Intra_mbAddrB_reg8; + plane_HV_A2 <= (blk4x4_intra_precompute_counter == 11)? Intra_mbAddrA_reg6 :Intra_mbAddrB_reg6; + plane_HV_B1 <= (blk4x4_intra_precompute_counter == 11)? Intra_mbAddrA_reg10:Intra_mbAddrB_reg10; + plane_HV_B2 <= (blk4x4_intra_precompute_counter == 11)? Intra_mbAddrA_reg4 :Intra_mbAddrB_reg4; + plane_HV_shifter1_len <= 0; plane_HV_shifter2_len <= 2'b01; + plane_HV_mux1_sel <= 1'b0; plane_HV_mux2_sel <= 1'b0; + end + 10,5 : // x2,x5 + begin + plane_HV_prev_in <= plane_HV_out_reg; plane_HV_Is7 <= 1'b0; + plane_HV_A1 <= (blk4x4_intra_precompute_counter == 10)? Intra_mbAddrA_reg9 :Intra_mbAddrB_reg9; + plane_HV_A2 <= (blk4x4_intra_precompute_counter == 10)? Intra_mbAddrA_reg5 :Intra_mbAddrB_reg5; + plane_HV_B1 <= (blk4x4_intra_precompute_counter == 10)? Intra_mbAddrA_reg12:Intra_mbAddrB_reg12; + plane_HV_B2 <= (blk4x4_intra_precompute_counter == 10)? Intra_mbAddrA_reg2 :Intra_mbAddrB_reg2; + plane_HV_shifter1_len <= 2'b01; plane_HV_shifter2_len <= 2'b10; + plane_HV_mux1_sel <= 1'b1; plane_HV_mux2_sel <= 1'b0; + end + 9,4 : // x4,x6 + begin + plane_HV_prev_in <= plane_HV_out_reg; plane_HV_Is7 <= 1'b0; + plane_HV_A1 <= (blk4x4_intra_precompute_counter == 9)? Intra_mbAddrA_reg11:Intra_mbAddrB_reg11; + plane_HV_A2 <= (blk4x4_intra_precompute_counter == 9)? Intra_mbAddrA_reg3 :Intra_mbAddrB_reg3; + plane_HV_B1 <= (blk4x4_intra_precompute_counter == 9)? Intra_mbAddrA_reg13:Intra_mbAddrB_reg13; + plane_HV_B2 <= (blk4x4_intra_precompute_counter == 9)? Intra_mbAddrA_reg1 :Intra_mbAddrB_reg1; + plane_HV_shifter1_len <= 2'b10; plane_HV_shifter2_len <= 2'b10; + plane_HV_mux1_sel <= 1'b1; plane_HV_mux2_sel <= 1'b1; + end + 8,3 : // x8,x7 + begin + plane_HV_prev_in <= plane_HV_out_reg; plane_HV_Is7 <= 1'b1; + plane_HV_A1 <= (blk4x4_intra_precompute_counter == 8)? Intra_mbAddrA_reg15:Intra_mbAddrB_reg15; + plane_HV_A2 <= Intra_mbAddrD_window; + plane_HV_B1 <= (blk4x4_intra_precompute_counter == 8)? Intra_mbAddrA_reg14:Intra_mbAddrB_reg14; + plane_HV_B2 <= (blk4x4_intra_precompute_counter == 8)? Intra_mbAddrA_reg0 :Intra_mbAddrB_reg0; + plane_HV_shifter1_len <= 2'b11; plane_HV_shifter2_len <= 2'b11; + plane_HV_mux1_sel <= 1'b1; plane_HV_mux2_sel <= 1'b0; + end + default: + begin + plane_HV_prev_in <= 0; plane_HV_Is7 <= 0; + plane_HV_A1 <= 0; plane_HV_A2 <= 0; plane_HV_B1 <= 0; plane_HV_B2 <= 0; + plane_HV_shifter1_len <= 0; plane_HV_shifter2_len <= 0; + plane_HV_mux1_sel <= 0; plane_HV_mux2_sel <= 0; + end + endcase + //Chroma Cb/Cr plane + else if (blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20) + case (blk4x4_intra_precompute_counter) + 7,4: //x1,x3 + begin + plane_HV_prev_in <= 0; plane_HV_Is7 <= 1'b0; + plane_HV_A1 <= (blk4x4_intra_precompute_counter == 7)? Intra_mbAddrA_reg4:Intra_mbAddrB_reg4; + plane_HV_A2 <= (blk4x4_intra_precompute_counter == 7)? Intra_mbAddrA_reg2:Intra_mbAddrB_reg2; + plane_HV_B1 <= (blk4x4_intra_precompute_counter == 7)? Intra_mbAddrA_reg6:Intra_mbAddrB_reg6; + plane_HV_B2 <= (blk4x4_intra_precompute_counter == 7)? Intra_mbAddrA_reg0:Intra_mbAddrB_reg0; + plane_HV_shifter1_len <= 0; plane_HV_shifter2_len <= 2'b01; + plane_HV_mux1_sel <= 1'b0; plane_HV_mux2_sel <= 1'b0; + end + 6,3: //x2,x4 + begin + plane_HV_prev_in <= plane_HV_out_reg; plane_HV_Is7 <= 1'b0; + plane_HV_A1 <= (blk4x4_intra_precompute_counter == 6)? Intra_mbAddrA_reg5:Intra_mbAddrB_reg5; + plane_HV_A2 <= (blk4x4_intra_precompute_counter == 6)? Intra_mbAddrA_reg1:Intra_mbAddrB_reg1; + plane_HV_B1 <= (blk4x4_intra_precompute_counter == 6)? Intra_mbAddrA_reg7:Intra_mbAddrB_reg7; + plane_HV_B2 <= (blk4x4_intra_precompute_counter == 6)? Intra_mbAddrD_window :Intra_mbAddrD_window; + plane_HV_shifter1_len <= 2'b01; plane_HV_shifter2_len <= 2'b01; + plane_HV_mux1_sel <= 1'b1; plane_HV_mux2_sel <= 1'b1; + end + default: + begin + plane_HV_prev_in <= 0; plane_HV_Is7 <= 0; + plane_HV_A1 <= 0; plane_HV_A2 <= 0; plane_HV_B1 <= 0; plane_HV_B2 <= 0; + plane_HV_shifter1_len <= 0; plane_HV_shifter2_len <= 0; + plane_HV_mux1_sel <= 0; plane_HV_mux2_sel <= 0; + end + endcase + else + begin + plane_HV_prev_in <= 0; plane_HV_Is7 <= 0; + plane_HV_A1 <= 0; plane_HV_A2 <= 0; plane_HV_B1 <= 0; plane_HV_B2 <= 0; + plane_HV_shifter1_len <= 0; plane_HV_shifter2_len <= 0; + plane_HV_mux1_sel <= 0; plane_HV_mux2_sel <= 0; + end + + wire Is_HV_latch; + assign Is_HV_latch = ((blk4x4_rec_counter == 0 && blk4x4_intra_precompute_counter != 7 && blk4x4_intra_precompute_counter != 2 && + blk4x4_intra_precompute_counter != 1 && blk4x4_intra_precompute_counter != 0) || ( + (blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20) && (blk4x4_intra_precompute_counter != 5 && + blk4x4_intra_precompute_counter != 2 && blk4x4_intra_precompute_counter != 1 && blk4x4_intra_precompute_counter != 0))); + always @ (posedge clk) + if (reset_n == 1'b0) + plane_HV_out_reg <= 0; + else if (Is_HV_latch) + plane_HV_out_reg <= plane_HV_out; + + // 2.2 precomputation for b,c + reg [14:0] plane_bc_in; + reg plane_bc_IsLuma; + wire [11:0] plane_bc; + plane_bc_precomputation plane_bc_precomputation ( + .HV_in(plane_bc_in), + .IsLuma(plane_bc_IsLuma), + .bc_out(plane_bc) + ); + always @ (mb_type_general[3:2] or Intra16x16_predmode or blk4x4_rec_counter or blk4x4_intra_precompute_counter or plane_HV_out_reg) + //Intra16x16 plane + if (mb_type_general[3:2] == 2'b10 && Intra16x16_predmode == `Intra16x16_Plane && blk4x4_rec_counter == 0) + case (blk4x4_intra_precompute_counter) + 7,2 :begin plane_bc_in <= plane_HV_out_reg; plane_bc_IsLuma <= 1'b1; end + default:begin plane_bc_in <= 0; plane_bc_IsLuma <= 1'b0; end + endcase + //Chroma Cb,Cr plane + else if (mb_type_general[3] == 1'b1 && (blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20)) + case (blk4x4_intra_precompute_counter) + 5,2 :begin plane_bc_in <= plane_HV_out_reg; plane_bc_IsLuma <= 1'b0; end + default:begin plane_bc_in <= 0; plane_bc_IsLuma <= 1'b0; end + endcase + else + begin plane_bc_in <= 0; plane_bc_IsLuma <= 1'b0; end + + wire c_latch_ena; + assign c_latch_ena = ((blk4x4_rec_counter == 0 && blk4x4_intra_precompute_counter == 7) || + ((blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20) && blk4x4_intra_precompute_counter == 5)); + always @ (posedge clk) + if (reset_n == 0) + plane_c_reg <= 0; + else if (c_latch_ena) + plane_c_reg <= plane_bc; + // 2.3 precomputation for a,and latch a & b at the same time at cycle 2 + reg [7:0] plane_a_pix_in1,plane_a_pix_in2; + wire [13:0] plane_a; + reg [13:0] plane_a_reg; + + plane_a_precomputation plane_a_precomputation( + .pix_in1(plane_a_pix_in1), + .pix_in2(plane_a_pix_in2), + .a_out(plane_a) + ); + always @ (blk4x4_rec_counter or blk4x4_intra_precompute_counter or Intra_mbAddrA_reg15 + or Intra_mbAddrB_reg15 or Intra_mbAddrA_reg7 or Intra_mbAddrB_reg7) + //Intra16x16 + if (blk4x4_rec_counter == 0 && blk4x4_intra_precompute_counter == 2) + begin + plane_a_pix_in1 <= Intra_mbAddrA_reg15; + plane_a_pix_in2 <= Intra_mbAddrB_reg15; + end + //Chroma + else if((blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20) && blk4x4_intra_precompute_counter == 2) + begin + plane_a_pix_in1 <= Intra_mbAddrA_reg7; + plane_a_pix_in2 <= Intra_mbAddrB_reg7; + end + else + begin + plane_a_pix_in1 <= 0; + plane_a_pix_in2 <= 0; + end + + wire ab_latch_ena; + assign ab_latch_ena = (blk4x4_intra_precompute_counter == 2); + always @ (posedge clk) + if (reset_n == 1'b0) + begin + plane_a_reg <= 0; + plane_b_reg <= 0; + end + else if (ab_latch_ena) + begin + plane_a_reg <= plane_a; + plane_b_reg <= plane_bc; + end + // 2.4 precomputation for main seed @ blk4x4_intra_precompute_counter == 1 + wire [13:0] main_seed_a; + wire [11:0] main_seed_b,main_seed_c; + wire main_seed_IsIntra16x16; + + main_seed_precomputation main_seed_precomputation ( + .a(main_seed_a), + .b(main_seed_b), + .c(main_seed_c), + .IsIntra16x16(main_seed_IsIntra16x16), + .main_seed(main_seed) + ); + assign main_seed_a = (blk4x4_intra_precompute_counter == 1)? plane_a_reg:0; + assign main_seed_b = (blk4x4_intra_precompute_counter == 1)? plane_b_reg:0; + assign main_seed_c = (blk4x4_intra_precompute_counter == 1)? plane_c_reg:0; + assign main_seed_IsIntra16x16 = (blk4x4_intra_precompute_counter == 1)? ((blk4x4_rec_counter == 0)? 1'b1:1'b0):1'b0; + + //---------------------------------------------------------------------------------------- + //3.calculation: by Intra_pred_PE.v + //---------------------------------------------------------------------------------------- + +endmodule + +module plane_a_precomputation (pix_in1,pix_in2,a_out); + input [7:0] pix_in1,pix_in2; + output [13:0] a_out; + + wire [8:0] sum; + assign sum = pix_in1 + pix_in2; + assign a_out = {1'b0,sum,4'b0}; +endmodule + +module plane_bc_precomputation (HV_in,IsLuma,bc_out); + input [14:0] HV_in; + input IsLuma; + output [11:0] bc_out; + + wire [16:0] multiply_4or16; + wire [16:0] product; + wire [5:0] addend; + wire [16:0] sum; + + assign multiply_4or16 = (IsLuma)? {HV_in,2'b0}:{HV_in[12:0],4'b0}; + assign product = multiply_4or16 + {{2{HV_in[14]}},HV_in}; + assign addend = (IsLuma)? 6'b100000:6'b010000; //32 for luma,16 for chroma + assign sum = product + addend; + assign bc_out = (IsLuma)? {sum[16],sum[16:6]}:sum[16:5]; + +endmodule + +module plane_HV_precomputation (prev_in,A1,A2,B1,B2,shifter1_len,shifter2_len,mux1_sel,mux2_sel,Is7,HV_out); + input [14:0] prev_in; + input [7:0] A1,A2,B1,B2; + input [1:0] shifter1_len,shifter2_len; + input mux1_sel,mux2_sel; + input Is7; + output [14:0] HV_out; + + wire [7:0] neg_A2; + wire signed [8:0] A1_minus_A2; + wire signed [11:0] shifter1_out; + wire [11:0] mux1_out; + wire [14:0] adder1_out; + wire [7:0] neg_B2; + wire signed [8:0] B1_minus_B2; + wire signed [11:0] shifter2_out; + wire [9:0] mux2_out; + wire [9:0] neg_mux2_out; + wire [11:0] adder2_out; + //Left part,multiply by 1,2,4,8 + assign neg_A2 = ~A2; + assign A1_minus_A2 = {1'b0,A1} + {1'b1,neg_A2} + 1; + assign shifter1_out = A1_minus_A2 <<< shifter1_len; + assign mux1_out = (mux1_sel == 1'b0)? {{3{A1_minus_A2[8]}},A1_minus_A2}:shifter1_out; + assign adder1_out = prev_in + {{3{mux1_out[11]}},mux1_out}; + //Right part,multiply by 3,5,6,7 + assign neg_B2 = ~B2; + assign B1_minus_B2 = {1'b0,B1} + {1'b1,neg_B2} + 1; + assign shifter2_out = B1_minus_B2 <<< shifter2_len; + assign mux2_out = (mux2_sel == 1'b0)? {B1_minus_B2[8],B1_minus_B2}:{B1_minus_B2,1'b0}; + assign neg_mux2_out = (Is7 == 1'b1)? (~mux2_out + 1):mux2_out; + assign adder2_out = shifter2_out + {{2{neg_mux2_out[9]}},neg_mux2_out}; + assign HV_out = adder1_out + {{3{adder2_out[11]}},adder2_out}; +endmodule + +module main_seed_precomputation (a,b,c,IsIntra16x16,main_seed); + input [13:0] a; + input [11:0] b,c; + input IsIntra16x16; + output [15:0] main_seed; + + wire [14:0] b_x8_or_x4; + wire [14:0] c_x8_or_x4; + wire [11:0] neg_b; + wire [14:0] b_x7_or_x3; + wire [15:0] neg_b_x7_or_x3; + wire [15:0] neg_c_x8_or_x4; + + assign b_x8_or_x4 = (IsIntra16x16)? {b[11:0],3'b0}:{b[11],b[11:0],2'b0}; + assign c_x8_or_x4 = (IsIntra16x16)? {c[11:0],3'b0}:{c[11],c[11:0],2'b0}; + assign neg_b = ~ b; + assign b_x7_or_x3 = b_x8_or_x4 + {{3{neg_b[11]}},neg_b} + 1; + assign neg_b_x7_or_x3 = {~b_x7_or_x3[14],~b_x7_or_x3} + 1; + assign neg_c_x8_or_x4 = {~c_x8_or_x4[14],~c_x8_or_x4} + 1; + assign main_seed = {a[13],a[13],a} + (neg_c_x8_or_x4 + neg_b_x7_or_x3); +endmodule + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/Intra_pred_reg_ctrl.v b/demo_chip_rtl/rtl/nova/tags/Start/src/Intra_pred_reg_ctrl.v new file mode 100644 index 0000000..8974ba5 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/Intra_pred_reg_ctrl.v @@ -0,0 +1,839 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : Intra_pred_reg_ctrl.v +// Generated : Sep 25, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Prepare the appropriate registers for PE0 ~ PE3 +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module Intra_pred_reg_ctrl (reset_n,gclk_intra_mbAddrA_luma,gclk_intra_mbAddrA_Cb, + gclk_intra_mbAddrA_Cr,gclk_intra_mbAddrB,gclk_intra_mbAddrC_luma,gclk_intra_mbAddrD,gclk_seed, + mbAddrA_availability,mbAddrC_availability,blk4x4_rec_counter,blk4x4_sum_counter, + blk4x4_intra_preload_counter,blk4x4_intra_precompute_counter,blk4x4_intra_calculate_counter, + mb_type_general,Intra4x4_predmode,Intra16x16_predmode,Intra_chroma_predmode, + + Intra_mbAddrB_RAM_dout,sum_right_column_reg, + blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out, + main_seed,PE0_sum_out,PE3_sum_out, + + Intra_mbAddrA_window0,Intra_mbAddrA_window1,Intra_mbAddrA_window2,Intra_mbAddrA_window3, + Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3, + Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7, + Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11, + Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15, + + Intra_mbAddrB_window0,Intra_mbAddrB_window1,Intra_mbAddrB_window2,Intra_mbAddrB_window3, + Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3, + Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7, + Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11, + Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15, + + Intra_mbAddrC_window0,Intra_mbAddrC_window1,Intra_mbAddrC_window2,Intra_mbAddrC_window3,Intra_mbAddrD_window, + seed); + input reset_n; + input gclk_intra_mbAddrA_luma; + input gclk_intra_mbAddrA_Cb; + input gclk_intra_mbAddrA_Cr; + input gclk_intra_mbAddrB; + input gclk_intra_mbAddrC_luma; + input gclk_intra_mbAddrD; + input gclk_seed; + input mbAddrA_availability; + input mbAddrC_availability; + input [4:0] blk4x4_rec_counter; + input [2:0] blk4x4_sum_counter; + input [2:0] blk4x4_intra_preload_counter; + input [3:0] blk4x4_intra_precompute_counter; + input [2:0] blk4x4_intra_calculate_counter; + input [3:0] mb_type_general; + input [3:0] Intra4x4_predmode; + input [1:0] Intra16x16_predmode; + input [1:0] Intra_chroma_predmode; + input [31:0] Intra_mbAddrB_RAM_dout; + input [23:0] sum_right_column_reg; + input [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out; + input [15:0] main_seed; + input [15:0] PE0_sum_out,PE3_sum_out; + + output [7:0] Intra_mbAddrA_window0,Intra_mbAddrA_window1,Intra_mbAddrA_window2,Intra_mbAddrA_window3; + output [7:0] Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3; + output [7:0] Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7; + output [7:0] Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11; + output [7:0] Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15; + + output [7:0] Intra_mbAddrB_window0,Intra_mbAddrB_window1,Intra_mbAddrB_window2,Intra_mbAddrB_window3; + output [7:0] Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3; + output [7:0] Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7; + output [7:0] Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11; + output [7:0] Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15; + + output [7:0] Intra_mbAddrC_window0,Intra_mbAddrC_window1,Intra_mbAddrC_window2,Intra_mbAddrC_window3; + output [7:0] Intra_mbAddrD_window; + output [15:0] seed; + + reg [7:0] Intra_mbAddrA_luma_reg0, Intra_mbAddrA_luma_reg1, Intra_mbAddrA_luma_reg2, Intra_mbAddrA_luma_reg3; + reg [7:0] Intra_mbAddrA_luma_reg4, Intra_mbAddrA_luma_reg5, Intra_mbAddrA_luma_reg6, Intra_mbAddrA_luma_reg7; + reg [7:0] Intra_mbAddrA_luma_reg8, Intra_mbAddrA_luma_reg9, Intra_mbAddrA_luma_reg10,Intra_mbAddrA_luma_reg11; + reg [7:0] Intra_mbAddrA_luma_reg12,Intra_mbAddrA_luma_reg13,Intra_mbAddrA_luma_reg14,Intra_mbAddrA_luma_reg15; + reg [7:0] Intra_mbAddrA_Cb_reg0,Intra_mbAddrA_Cb_reg1,Intra_mbAddrA_Cb_reg2,Intra_mbAddrA_Cb_reg3; + reg [7:0] Intra_mbAddrA_Cb_reg4,Intra_mbAddrA_Cb_reg5,Intra_mbAddrA_Cb_reg6,Intra_mbAddrA_Cb_reg7; + reg [7:0] Intra_mbAddrA_Cr_reg0,Intra_mbAddrA_Cr_reg1,Intra_mbAddrA_Cr_reg2,Intra_mbAddrA_Cr_reg3; + reg [7:0] Intra_mbAddrA_Cr_reg4,Intra_mbAddrA_Cr_reg5,Intra_mbAddrA_Cr_reg6,Intra_mbAddrA_Cr_reg7; + reg [7:0] Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3; + reg [7:0] Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7; + reg [7:0] Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11; + reg [7:0] Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15; + reg [7:0] Intra_mbAddrA_window0,Intra_mbAddrA_window1,Intra_mbAddrA_window2,Intra_mbAddrA_window3; + + reg [7:0] Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3; + reg [7:0] Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7; + reg [7:0] Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11; + reg [7:0] Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15; + reg [7:0] Intra_mbAddrB_window0,Intra_mbAddrB_window1,Intra_mbAddrB_window2,Intra_mbAddrB_window3; + + reg [7:0] Intra_mbAddrC_reg0,Intra_mbAddrC_reg1,Intra_mbAddrC_reg2,Intra_mbAddrC_reg3; + reg [7:0] Intra_mbAddrC_window0,Intra_mbAddrC_window1,Intra_mbAddrC_window2,Intra_mbAddrC_window3; + + reg [7:0] Intra_mbAddrD_reg0,Intra_mbAddrD_reg1,Intra_mbAddrD_reg2; + reg [7:0] Intra_mbAddrD_reg3,Intra_mbAddrD_reg4; + reg [7:0] Intra_mbAddrD_LeftMB_luma_reg,Intra_mbAddrD_LeftMB_Cb_reg,Intra_mbAddrD_LeftMB_Cr_reg; + reg [7:0] Intra_mbAddrD_window; + + reg [15:0] seed_0,seed_1,seed_2,seed_3; + reg [15:0] seed; + //--------------------------------------------------------------------- + //Intra_mbAddrA_luma_reg0 ~ 15 + //Intra_mbAddrA_Cb_reg0 ~ 7 + //Intra_mbAddrA_Cr_reg0 ~ 7 + //--------------------------------------------------------------------- + always @ (posedge gclk_intra_mbAddrA_luma or negedge reset_n) + if (reset_n == 1'b0) + begin + Intra_mbAddrA_luma_reg0 <= 0; Intra_mbAddrA_luma_reg1 <= 0; Intra_mbAddrA_luma_reg2 <= 0; + Intra_mbAddrA_luma_reg3 <= 0; Intra_mbAddrA_luma_reg4 <= 0; Intra_mbAddrA_luma_reg5 <= 0; + Intra_mbAddrA_luma_reg6 <= 0; Intra_mbAddrA_luma_reg7 <= 0; Intra_mbAddrA_luma_reg8 <= 0; + Intra_mbAddrA_luma_reg9 <= 0; Intra_mbAddrA_luma_reg10 <= 0; Intra_mbAddrA_luma_reg11 <= 0; + Intra_mbAddrA_luma_reg12 <= 0; Intra_mbAddrA_luma_reg13 <= 0; Intra_mbAddrA_luma_reg14 <= 0; + Intra_mbAddrA_luma_reg15 <= 0; + end + else + case (blk4x4_rec_counter) + 0,1,4,5: + begin + Intra_mbAddrA_luma_reg0 <= sum_right_column_reg[7:0]; + Intra_mbAddrA_luma_reg1 <= sum_right_column_reg[15:8]; + Intra_mbAddrA_luma_reg2 <= sum_right_column_reg[23:16]; + Intra_mbAddrA_luma_reg3 <= blk4x4_sum_PE3_out; + end + 2,3,6,7: + begin + Intra_mbAddrA_luma_reg4 <= sum_right_column_reg[7:0]; + Intra_mbAddrA_luma_reg5 <= sum_right_column_reg[15:8]; + Intra_mbAddrA_luma_reg6 <= sum_right_column_reg[23:16]; + Intra_mbAddrA_luma_reg7 <= blk4x4_sum_PE3_out; + end + 8,9,12,13: + begin + Intra_mbAddrA_luma_reg8 <= sum_right_column_reg[7:0]; + Intra_mbAddrA_luma_reg9 <= sum_right_column_reg[15:8]; + Intra_mbAddrA_luma_reg10 <= sum_right_column_reg[23:16]; + Intra_mbAddrA_luma_reg11 <= blk4x4_sum_PE3_out; + end + 10,11,14,15: + begin + Intra_mbAddrA_luma_reg12 <= sum_right_column_reg[7:0]; + Intra_mbAddrA_luma_reg13 <= sum_right_column_reg[15:8]; + Intra_mbAddrA_luma_reg14 <= sum_right_column_reg[23:16]; + Intra_mbAddrA_luma_reg15 <= blk4x4_sum_PE3_out; + end + endcase + + always @ (posedge gclk_intra_mbAddrA_Cb or negedge reset_n) + if (reset_n == 1'b0) + begin + Intra_mbAddrA_Cb_reg0 <= 0; Intra_mbAddrA_Cb_reg1 <= 0; Intra_mbAddrA_Cb_reg2 <= 0; + Intra_mbAddrA_Cb_reg3 <= 0; Intra_mbAddrA_Cb_reg4 <= 0; Intra_mbAddrA_Cb_reg5 <= 0; + Intra_mbAddrA_Cb_reg6 <= 0; Intra_mbAddrA_Cb_reg7 <= 0; + end + else if (blk4x4_rec_counter == 17) + begin + Intra_mbAddrA_Cb_reg0 <= sum_right_column_reg[7:0]; + Intra_mbAddrA_Cb_reg1 <= sum_right_column_reg[15:8]; + Intra_mbAddrA_Cb_reg2 <= sum_right_column_reg[23:16]; + Intra_mbAddrA_Cb_reg3 <= blk4x4_sum_PE3_out; + end + else + begin + Intra_mbAddrA_Cb_reg4 <= sum_right_column_reg[7:0]; + Intra_mbAddrA_Cb_reg5 <= sum_right_column_reg[15:8]; + Intra_mbAddrA_Cb_reg6 <= sum_right_column_reg[23:16]; + Intra_mbAddrA_Cb_reg7 <= blk4x4_sum_PE3_out; + end + + always @ (posedge gclk_intra_mbAddrA_Cr or negedge reset_n) + if (reset_n == 1'b0) + begin + Intra_mbAddrA_Cr_reg0 <= 0; Intra_mbAddrA_Cr_reg1 <= 0; Intra_mbAddrA_Cr_reg2 <= 0; + Intra_mbAddrA_Cr_reg3 <= 0; Intra_mbAddrA_Cr_reg4 <= 0; Intra_mbAddrA_Cr_reg5 <= 0; + Intra_mbAddrA_Cr_reg6 <= 0; Intra_mbAddrA_Cr_reg7 <= 0; + end + else if (blk4x4_rec_counter == 21) + begin + Intra_mbAddrA_Cr_reg0 <= sum_right_column_reg[7:0]; + Intra_mbAddrA_Cr_reg1 <= sum_right_column_reg[15:8]; + Intra_mbAddrA_Cr_reg2 <= sum_right_column_reg[23:16]; + Intra_mbAddrA_Cr_reg3 <= blk4x4_sum_PE3_out; + end + else + begin + Intra_mbAddrA_Cr_reg4 <= sum_right_column_reg[7:0]; + Intra_mbAddrA_Cr_reg5 <= sum_right_column_reg[15:8]; + Intra_mbAddrA_Cr_reg6 <= sum_right_column_reg[23:16]; + Intra_mbAddrA_Cr_reg7 <= blk4x4_sum_PE3_out; + end + //--------------------------------------------------------------------- + //Intra_mbAddrB_reg0 ~ 15 + //--------------------------------------------------------------------- + always @ (posedge gclk_intra_mbAddrB or negedge reset_n) + if (reset_n == 1'b0) + begin + Intra_mbAddrB_reg0 <= 0; Intra_mbAddrB_reg1 <= 0; Intra_mbAddrB_reg2 <= 0; + Intra_mbAddrB_reg3 <= 0; Intra_mbAddrB_reg4 <= 0; Intra_mbAddrB_reg5 <= 0; + Intra_mbAddrB_reg6 <= 0; Intra_mbAddrB_reg7 <= 0; Intra_mbAddrB_reg8 <= 0; + Intra_mbAddrB_reg9 <= 0; Intra_mbAddrB_reg10 <= 0; Intra_mbAddrB_reg11 <= 0; + Intra_mbAddrB_reg12 <= 0; Intra_mbAddrB_reg13 <= 0; Intra_mbAddrB_reg14 <= 0; + Intra_mbAddrB_reg15 <= 0; + end + //Intra4x4 + else if (mb_type_general[3:2] == 2'b11 && blk4x4_rec_counter < 16) + begin + // blk 0,1,4,5,load from RAM + if (blk4x4_intra_preload_counter == 3'b001) + case (blk4x4_rec_counter) + 0: + begin + Intra_mbAddrB_reg0 <= Intra_mbAddrB_RAM_dout[7:0]; + Intra_mbAddrB_reg1 <= Intra_mbAddrB_RAM_dout[15:8]; + Intra_mbAddrB_reg2 <= Intra_mbAddrB_RAM_dout[23:16]; + Intra_mbAddrB_reg3 <= Intra_mbAddrB_RAM_dout[31:24]; + end + 1: + begin + Intra_mbAddrB_reg4 <= Intra_mbAddrB_RAM_dout[7:0]; + Intra_mbAddrB_reg5 <= Intra_mbAddrB_RAM_dout[15:8]; + Intra_mbAddrB_reg6 <= Intra_mbAddrB_RAM_dout[23:16]; + Intra_mbAddrB_reg7 <= Intra_mbAddrB_RAM_dout[31:24]; + end + 4: + begin + Intra_mbAddrB_reg8 <= Intra_mbAddrB_RAM_dout[7:0]; + Intra_mbAddrB_reg9 <= Intra_mbAddrB_RAM_dout[15:8]; + Intra_mbAddrB_reg10 <= Intra_mbAddrB_RAM_dout[23:16]; + Intra_mbAddrB_reg11 <= Intra_mbAddrB_RAM_dout[31:24]; + end + 5: + begin + Intra_mbAddrB_reg12 <= Intra_mbAddrB_RAM_dout[7:0]; + Intra_mbAddrB_reg13 <= Intra_mbAddrB_RAM_dout[15:8]; + Intra_mbAddrB_reg14 <= Intra_mbAddrB_RAM_dout[23:16]; + Intra_mbAddrB_reg15 <= Intra_mbAddrB_RAM_dout[31:24]; + end + endcase + //other blocks,from blk4x4_sum output + else if ((blk4x4_rec_counter != 10 || blk4x4_rec_counter != 11 || blk4x4_rec_counter != 14 || + blk4x4_rec_counter != 15) && blk4x4_sum_counter == 3'd3) + case (blk4x4_rec_counter) + 0,2,8: + begin + Intra_mbAddrB_reg0 <= blk4x4_sum_PE0_out; + Intra_mbAddrB_reg1 <= blk4x4_sum_PE1_out; + Intra_mbAddrB_reg2 <= blk4x4_sum_PE2_out; + Intra_mbAddrB_reg3 <= blk4x4_sum_PE3_out; + end + 1,3,9: + begin + Intra_mbAddrB_reg4 <= blk4x4_sum_PE0_out; + Intra_mbAddrB_reg5 <= blk4x4_sum_PE1_out; + Intra_mbAddrB_reg6 <= blk4x4_sum_PE2_out; + Intra_mbAddrB_reg7 <= blk4x4_sum_PE3_out; + end + 4,6,12: + begin + Intra_mbAddrB_reg8 <= blk4x4_sum_PE0_out; + Intra_mbAddrB_reg9 <= blk4x4_sum_PE1_out; + Intra_mbAddrB_reg10 <= blk4x4_sum_PE2_out; + Intra_mbAddrB_reg11 <= blk4x4_sum_PE3_out; + end + 5,7,13: + begin + Intra_mbAddrB_reg12 <= blk4x4_sum_PE0_out; + Intra_mbAddrB_reg13 <= blk4x4_sum_PE1_out; + Intra_mbAddrB_reg14 <= blk4x4_sum_PE2_out; + Intra_mbAddrB_reg15 <= blk4x4_sum_PE3_out; + end + endcase + end + //Intra16x16 + else if (mb_type_general[3:2] == 2'b10 && blk4x4_rec_counter < 16) + case (blk4x4_intra_preload_counter) + 3'b100: + begin + Intra_mbAddrB_reg0 <= Intra_mbAddrB_RAM_dout[7:0]; + Intra_mbAddrB_reg1 <= Intra_mbAddrB_RAM_dout[15:8]; + Intra_mbAddrB_reg2 <= Intra_mbAddrB_RAM_dout[23:16]; + Intra_mbAddrB_reg3 <= Intra_mbAddrB_RAM_dout[31:24]; + end + 3'b011: + begin + Intra_mbAddrB_reg4 <= Intra_mbAddrB_RAM_dout[7:0]; + Intra_mbAddrB_reg5 <= Intra_mbAddrB_RAM_dout[15:8]; + Intra_mbAddrB_reg6 <= Intra_mbAddrB_RAM_dout[23:16]; + Intra_mbAddrB_reg7 <= Intra_mbAddrB_RAM_dout[31:24]; + end + 3'b010: + begin + Intra_mbAddrB_reg8 <= Intra_mbAddrB_RAM_dout[7:0]; + Intra_mbAddrB_reg9 <= Intra_mbAddrB_RAM_dout[15:8]; + Intra_mbAddrB_reg10 <= Intra_mbAddrB_RAM_dout[23:16]; + Intra_mbAddrB_reg11 <= Intra_mbAddrB_RAM_dout[31:24]; + end + 3'b001: + begin + Intra_mbAddrB_reg12 <= Intra_mbAddrB_RAM_dout[7:0]; + Intra_mbAddrB_reg13 <= Intra_mbAddrB_RAM_dout[15:8]; + Intra_mbAddrB_reg14 <= Intra_mbAddrB_RAM_dout[23:16]; + Intra_mbAddrB_reg15 <= Intra_mbAddrB_RAM_dout[31:24]; + end + endcase + //Chroma + else if (mb_type_general[3] == 1'b1 && blk4x4_rec_counter > 15) + begin + if (blk4x4_intra_preload_counter == 3'b010) + begin + Intra_mbAddrB_reg0 <= Intra_mbAddrB_RAM_dout[7:0]; + Intra_mbAddrB_reg1 <= Intra_mbAddrB_RAM_dout[15:8]; + Intra_mbAddrB_reg2 <= Intra_mbAddrB_RAM_dout[23:16]; + Intra_mbAddrB_reg3 <= Intra_mbAddrB_RAM_dout[31:24]; + end + else if (blk4x4_intra_preload_counter == 3'b001) + begin + Intra_mbAddrB_reg4 <= Intra_mbAddrB_RAM_dout[7:0]; + Intra_mbAddrB_reg5 <= Intra_mbAddrB_RAM_dout[15:8]; + Intra_mbAddrB_reg6 <= Intra_mbAddrB_RAM_dout[23:16]; + Intra_mbAddrB_reg7 <= Intra_mbAddrB_RAM_dout[31:24]; + end + end + //-------------------------------------------------------- + //Intra_mbAddrC_reg0 ~ 3,only useful for Intra4x4 with + // blkIdx = 0/1/4/5 + //-------------------------------------------------------- + + always @ (posedge gclk_intra_mbAddrC_luma or negedge reset_n) + if (reset_n == 1'b0) + begin + Intra_mbAddrC_reg0 <= 0; Intra_mbAddrC_reg1 <= 0; + Intra_mbAddrC_reg2 <= 0; Intra_mbAddrC_reg3 <= 0; + end + else + begin + Intra_mbAddrC_reg0 <= Intra_mbAddrB_RAM_dout[7:0]; + Intra_mbAddrC_reg1 <= Intra_mbAddrB_RAM_dout[15:8]; + Intra_mbAddrC_reg2 <= Intra_mbAddrB_RAM_dout[23:16]; + Intra_mbAddrC_reg3 <= Intra_mbAddrB_RAM_dout[31:24]; + end + //-------------------------------------------------------- + //Intra_mbAddrD_reg0 ~ 5 + //Intra_mbAddrD_LeftMB_reg + //-------------------------------------------------------- + always @ (posedge gclk_intra_mbAddrD or negedge reset_n) + if (reset_n == 1'b0) + Intra_mbAddrD_LeftMB_luma_reg <= 0; + else if (blk4x4_rec_counter == 15) + Intra_mbAddrD_LeftMB_luma_reg <= Intra_mbAddrB_RAM_dout[31:24]; + else if (mb_type_general[3:2] == 2'b11 && blk4x4_sum_counter == 3'd3) //Intra4x4 + case (blk4x4_rec_counter) + 0:Intra_mbAddrD_LeftMB_luma_reg <= Intra_mbAddrA_reg3; + 2:Intra_mbAddrD_LeftMB_luma_reg <= Intra_mbAddrA_reg7; + 8:Intra_mbAddrD_LeftMB_luma_reg <= Intra_mbAddrA_reg11; + endcase + + always @ (posedge gclk_intra_mbAddrD or negedge reset_n) + if (reset_n == 1'b0) + Intra_mbAddrD_LeftMB_Cb_reg <= 0; + else if (blk4x4_rec_counter == 19) + Intra_mbAddrD_LeftMB_Cb_reg <= Intra_mbAddrB_RAM_dout[31:24]; + + always @ (posedge gclk_intra_mbAddrD or negedge reset_n) + if (reset_n == 1'b0) + Intra_mbAddrD_LeftMB_Cr_reg <= 0; + else if (blk4x4_rec_counter == 23) + Intra_mbAddrD_LeftMB_Cr_reg <= Intra_mbAddrB_RAM_dout[31:24]; + + always @ (posedge gclk_intra_mbAddrD or negedge reset_n) + if (reset_n == 1'b0) + begin + Intra_mbAddrD_reg0 <= 0; Intra_mbAddrD_reg1 <= 0; Intra_mbAddrD_reg2 <= 0; + Intra_mbAddrD_reg3 <= 0; Intra_mbAddrD_reg4 <= 0; + end + else if (mb_type_general[3:2] == 2'b11) + begin + //load from Intra_mbAddrB_RAM for blk 1/4/5 + if (blk4x4_intra_preload_counter == 3'b010) + case (blk4x4_rec_counter) + 1:Intra_mbAddrD_reg1 <= Intra_mbAddrB_RAM_dout[31:24]; + 4:Intra_mbAddrD_reg4 <= Intra_mbAddrB_RAM_dout[31:24]; + 5:Intra_mbAddrD_reg0 <= Intra_mbAddrB_RAM_dout[31:24]; + endcase + //update Intra_mbAddrD_reg by pixels already decoded from left up blk4x4 + //After sum of blk0/1/4, update Intra_mbAddrD_reg0/1/2 for blkIdx 3 /6 /7 + //After sum of blk2/3/6, update Intra_mbAddrD_reg3/4/5 for blkIdx 9 /12/13 + //After sum of blk8/9/12,update Intra_mbAddrD_reg0/1/2 for blkIdx 11/14/15 + else + case (blk4x4_rec_counter) + 0,6 :Intra_mbAddrD_reg0 <= blk4x4_sum_PE3_out; + 1,8 :Intra_mbAddrD_reg1 <= blk4x4_sum_PE3_out; + 2,12:Intra_mbAddrD_reg2 <= blk4x4_sum_PE3_out; + 3 :Intra_mbAddrD_reg3 <= blk4x4_sum_PE3_out; + 4,9 :Intra_mbAddrD_reg4 <= blk4x4_sum_PE3_out; + endcase + end + //--------------------------- + //sliding window output + //--------------------------- + //Intra_mbAddrA_reg0 ~ 15 + always @ (mb_type_general[3:2] or blk4x4_rec_counter or blk4x4_intra_calculate_counter or + blk4x4_intra_precompute_counter or Intra16x16_predmode or Intra_chroma_predmode + or mbAddrA_availability + + or Intra_mbAddrA_luma_reg0 or Intra_mbAddrA_luma_reg1 or Intra_mbAddrA_luma_reg2 + or Intra_mbAddrA_luma_reg3 or Intra_mbAddrA_luma_reg4 or Intra_mbAddrA_luma_reg5 + or Intra_mbAddrA_luma_reg6 or Intra_mbAddrA_luma_reg7 or Intra_mbAddrA_luma_reg8 + or Intra_mbAddrA_luma_reg9 or Intra_mbAddrA_luma_reg10 or Intra_mbAddrA_luma_reg11 + or Intra_mbAddrA_luma_reg12 or Intra_mbAddrA_luma_reg13 or Intra_mbAddrA_luma_reg14 + or Intra_mbAddrA_luma_reg15 + + or Intra_mbAddrA_Cb_reg0 or Intra_mbAddrA_Cb_reg1 or Intra_mbAddrA_Cb_reg2 + or Intra_mbAddrA_Cb_reg3 or Intra_mbAddrA_Cb_reg4 or Intra_mbAddrA_Cb_reg5 + or Intra_mbAddrA_Cb_reg6 or Intra_mbAddrA_Cb_reg7 + + or Intra_mbAddrA_Cr_reg0 or Intra_mbAddrA_Cr_reg1 or Intra_mbAddrA_Cr_reg2 + or Intra_mbAddrA_Cr_reg3 or Intra_mbAddrA_Cr_reg4 or Intra_mbAddrA_Cr_reg5 + or Intra_mbAddrA_Cr_reg6 or Intra_mbAddrA_Cr_reg7) + if (mb_type_general[3] == 1'b1) + begin + //Intra4x4 + //Intra16x16_Horizontal,Intra16x16_DC,Intra16x16_Plane + if (blk4x4_rec_counter < 16 && + (mb_type_general[2] == 1'b1 || (mb_type_general[2] == 1'b0 && ( + (Intra16x16_predmode == `Intra16x16_Horizontal && blk4x4_intra_calculate_counter != 0) || + (Intra16x16_predmode == `Intra16x16_DC && blk4x4_intra_calculate_counter != 0 && mbAddrA_availability == 1'b1) || + (Intra16x16_predmode == `Intra16x16_Plane && blk4x4_intra_precompute_counter != 0))))) + begin + Intra_mbAddrA_reg0 <= Intra_mbAddrA_luma_reg0; + Intra_mbAddrA_reg1 <= Intra_mbAddrA_luma_reg1; + Intra_mbAddrA_reg2 <= Intra_mbAddrA_luma_reg2; + Intra_mbAddrA_reg3 <= Intra_mbAddrA_luma_reg3; + Intra_mbAddrA_reg4 <= Intra_mbAddrA_luma_reg4; + Intra_mbAddrA_reg5 <= Intra_mbAddrA_luma_reg5; + Intra_mbAddrA_reg6 <= Intra_mbAddrA_luma_reg6; + Intra_mbAddrA_reg7 <= Intra_mbAddrA_luma_reg7; + Intra_mbAddrA_reg8 <= Intra_mbAddrA_luma_reg8; + Intra_mbAddrA_reg9 <= Intra_mbAddrA_luma_reg9; + Intra_mbAddrA_reg10 <= Intra_mbAddrA_luma_reg10; + Intra_mbAddrA_reg11 <= Intra_mbAddrA_luma_reg11; + Intra_mbAddrA_reg12 <= Intra_mbAddrA_luma_reg12; + Intra_mbAddrA_reg13 <= Intra_mbAddrA_luma_reg13; + Intra_mbAddrA_reg14 <= Intra_mbAddrA_luma_reg14; + Intra_mbAddrA_reg15 <= Intra_mbAddrA_luma_reg15; + end + //Chroma Cb + else if (blk4x4_rec_counter > 15 && blk4x4_rec_counter < 20 && ( + (Intra_chroma_predmode == `Intra_chroma_Horizontal && blk4x4_intra_calculate_counter != 0) || + (Intra_chroma_predmode == `Intra_chroma_DC && blk4x4_intra_calculate_counter != 0 && mbAddrA_availability == 1'b1) || + (Intra_chroma_predmode == `Intra_chroma_Plane && blk4x4_intra_precompute_counter != 0))) + begin + Intra_mbAddrA_reg0 <= Intra_mbAddrA_Cb_reg0; + Intra_mbAddrA_reg1 <= Intra_mbAddrA_Cb_reg1; + Intra_mbAddrA_reg2 <= Intra_mbAddrA_Cb_reg2; + Intra_mbAddrA_reg3 <= Intra_mbAddrA_Cb_reg3; + Intra_mbAddrA_reg4 <= Intra_mbAddrA_Cb_reg4; + Intra_mbAddrA_reg5 <= Intra_mbAddrA_Cb_reg5; + Intra_mbAddrA_reg6 <= Intra_mbAddrA_Cb_reg6; + Intra_mbAddrA_reg7 <= Intra_mbAddrA_Cb_reg7; + Intra_mbAddrA_reg8 <= 0; Intra_mbAddrA_reg9 <= 0; + Intra_mbAddrA_reg10 <= 0; Intra_mbAddrA_reg11 <= 0; + Intra_mbAddrA_reg12 <= 0; Intra_mbAddrA_reg13 <= 0; + Intra_mbAddrA_reg14 <= 0; Intra_mbAddrA_reg15 <= 0; + end + //Chroma Cr + else if (blk4x4_rec_counter > 19 && blk4x4_rec_counter < 24 && ( + (Intra_chroma_predmode == `Intra_chroma_Horizontal && blk4x4_intra_calculate_counter != 0) || + (Intra_chroma_predmode == `Intra_chroma_DC && blk4x4_intra_calculate_counter != 0 && mbAddrA_availability == 1'b1) || + (Intra_chroma_predmode == `Intra_chroma_Plane && blk4x4_intra_precompute_counter != 0))) + begin + Intra_mbAddrA_reg0 <= Intra_mbAddrA_Cr_reg0; + Intra_mbAddrA_reg1 <= Intra_mbAddrA_Cr_reg1; + Intra_mbAddrA_reg2 <= Intra_mbAddrA_Cr_reg2; + Intra_mbAddrA_reg3 <= Intra_mbAddrA_Cr_reg3; + Intra_mbAddrA_reg4 <= Intra_mbAddrA_Cr_reg4; + Intra_mbAddrA_reg5 <= Intra_mbAddrA_Cr_reg5; + Intra_mbAddrA_reg6 <= Intra_mbAddrA_Cr_reg6; + Intra_mbAddrA_reg7 <= Intra_mbAddrA_Cr_reg7; + Intra_mbAddrA_reg8 <= 0; Intra_mbAddrA_reg9 <= 0; + Intra_mbAddrA_reg10 <= 0; Intra_mbAddrA_reg11 <= 0; + Intra_mbAddrA_reg12 <= 0; Intra_mbAddrA_reg13 <= 0; + Intra_mbAddrA_reg14 <= 0; Intra_mbAddrA_reg15 <= 0; + end + else + begin + Intra_mbAddrA_reg0 <= 0; Intra_mbAddrA_reg1 <= 0; + Intra_mbAddrA_reg2 <= 0; Intra_mbAddrA_reg3 <= 0; + Intra_mbAddrA_reg4 <= 0; Intra_mbAddrA_reg5 <= 0; + Intra_mbAddrA_reg6 <= 0; Intra_mbAddrA_reg7 <= 0; + Intra_mbAddrA_reg8 <= 0; Intra_mbAddrA_reg9 <= 0; + Intra_mbAddrA_reg10 <= 0; Intra_mbAddrA_reg11 <= 0; + Intra_mbAddrA_reg12 <= 0; Intra_mbAddrA_reg13 <= 0; + Intra_mbAddrA_reg14 <= 0; Intra_mbAddrA_reg15 <= 0; + end + end + else + begin + Intra_mbAddrA_reg0 <= 0; Intra_mbAddrA_reg1 <= 0; + Intra_mbAddrA_reg2 <= 0; Intra_mbAddrA_reg3 <= 0; + Intra_mbAddrA_reg4 <= 0; Intra_mbAddrA_reg5 <= 0; + Intra_mbAddrA_reg6 <= 0; Intra_mbAddrA_reg7 <= 0; + Intra_mbAddrA_reg8 <= 0; Intra_mbAddrA_reg9 <= 0; + Intra_mbAddrA_reg10 <= 0; Intra_mbAddrA_reg11 <= 0; + Intra_mbAddrA_reg12 <= 0; Intra_mbAddrA_reg13 <= 0; + Intra_mbAddrA_reg14 <= 0; Intra_mbAddrA_reg15 <= 0; + end + //Intra_mbAddrA_window0 ~ 3 + always @ (mb_type_general or Intra16x16_predmode or Intra_chroma_predmode + or blk4x4_intra_calculate_counter or blk4x4_rec_counter or mbAddrA_availability + + or Intra_mbAddrA_reg0 or Intra_mbAddrA_reg1 or Intra_mbAddrA_reg2 or Intra_mbAddrA_reg3 + or Intra_mbAddrA_reg4 or Intra_mbAddrA_reg5 or Intra_mbAddrA_reg6 or Intra_mbAddrA_reg7 + or Intra_mbAddrA_reg8 or Intra_mbAddrA_reg9 or Intra_mbAddrA_reg10 or Intra_mbAddrA_reg11 + or Intra_mbAddrA_reg12 or Intra_mbAddrA_reg13 or Intra_mbAddrA_reg14 or Intra_mbAddrA_reg15 + + or Intra_mbAddrA_Cb_reg0 or Intra_mbAddrA_Cb_reg1 or Intra_mbAddrA_Cb_reg2 or Intra_mbAddrA_Cb_reg3 + or Intra_mbAddrA_Cb_reg4 or Intra_mbAddrA_Cb_reg5 or Intra_mbAddrA_Cb_reg6 or Intra_mbAddrA_Cb_reg7 + or Intra_mbAddrA_Cr_reg0 or Intra_mbAddrA_Cr_reg1 or Intra_mbAddrA_Cr_reg2 or Intra_mbAddrA_Cr_reg3 + or Intra_mbAddrA_Cr_reg4 or Intra_mbAddrA_Cr_reg5 or Intra_mbAddrA_Cr_reg6 or Intra_mbAddrA_Cr_reg7) + if (mb_type_general[3] == 1'b1) + begin + //Intra4x4 && Intra16x16_horizontal + if (blk4x4_rec_counter < 16 && blk4x4_intra_calculate_counter != 0 && + (mb_type_general[2] == 1'b1 || ( + (mb_type_general[2] == 1'b0 && Intra16x16_predmode == `Intra16x16_Horizontal)))) + case (blk4x4_rec_counter) + 0,1,4,5: + begin + Intra_mbAddrA_window0 <= Intra_mbAddrA_reg0; Intra_mbAddrA_window1 <= Intra_mbAddrA_reg1; + Intra_mbAddrA_window2 <= Intra_mbAddrA_reg2; Intra_mbAddrA_window3 <= Intra_mbAddrA_reg3; + end + 2,3,6,7: + begin + Intra_mbAddrA_window0 <= Intra_mbAddrA_reg4; Intra_mbAddrA_window1 <= Intra_mbAddrA_reg5; + Intra_mbAddrA_window2 <= Intra_mbAddrA_reg6; Intra_mbAddrA_window3 <= Intra_mbAddrA_reg7; + end + 8,9,12,13: + begin + Intra_mbAddrA_window0 <= Intra_mbAddrA_reg8; Intra_mbAddrA_window1 <= Intra_mbAddrA_reg9; + Intra_mbAddrA_window2 <= Intra_mbAddrA_reg10;Intra_mbAddrA_window3 <= Intra_mbAddrA_reg11; + end + 10,11,14,15: + begin + Intra_mbAddrA_window0 <= Intra_mbAddrA_reg12;Intra_mbAddrA_window1 <= Intra_mbAddrA_reg13; + Intra_mbAddrA_window2 <= Intra_mbAddrA_reg14;Intra_mbAddrA_window3 <= Intra_mbAddrA_reg15; + end + default: + begin + Intra_mbAddrA_window0 <= 0;Intra_mbAddrA_window1 <= 0; + Intra_mbAddrA_window2 <= 0;Intra_mbAddrA_window3 <= 0; + end + endcase + //Chroma Cb/Cr Horizontal & DC + else if (blk4x4_rec_counter > 15 && blk4x4_intra_calculate_counter != 0 && + (Intra_chroma_predmode == `Intra_chroma_Horizontal || (Intra_chroma_predmode == `Intra_chroma_DC && mbAddrA_availability))) + case (blk4x4_rec_counter) + 16,17: + begin + Intra_mbAddrA_window0 <= Intra_mbAddrA_Cb_reg0; + Intra_mbAddrA_window1 <= Intra_mbAddrA_Cb_reg1; + Intra_mbAddrA_window2 <= Intra_mbAddrA_Cb_reg2; + Intra_mbAddrA_window3 <= Intra_mbAddrA_Cb_reg3; + end + 18,19: + begin + Intra_mbAddrA_window0 <= Intra_mbAddrA_Cb_reg4; + Intra_mbAddrA_window1 <= Intra_mbAddrA_Cb_reg5; + Intra_mbAddrA_window2 <= Intra_mbAddrA_Cb_reg6; + Intra_mbAddrA_window3 <= Intra_mbAddrA_Cb_reg7; + end + 20,21: + begin + Intra_mbAddrA_window0 <= Intra_mbAddrA_Cr_reg0; + Intra_mbAddrA_window1 <= Intra_mbAddrA_Cr_reg1; + Intra_mbAddrA_window2 <= Intra_mbAddrA_Cr_reg2; + Intra_mbAddrA_window3 <= Intra_mbAddrA_Cr_reg3; + end + 22,23: + begin + Intra_mbAddrA_window0 <= Intra_mbAddrA_Cr_reg4; + Intra_mbAddrA_window1 <= Intra_mbAddrA_Cr_reg5; + Intra_mbAddrA_window2 <= Intra_mbAddrA_Cr_reg6; + Intra_mbAddrA_window3 <= Intra_mbAddrA_Cr_reg7; + end + default: + begin + Intra_mbAddrA_window0 <= 0;Intra_mbAddrA_window1 <= 0; + Intra_mbAddrA_window2 <= 0;Intra_mbAddrA_window3 <= 0; + end + endcase + else + begin + Intra_mbAddrA_window0 <= 0;Intra_mbAddrA_window1 <= 0; + Intra_mbAddrA_window2 <= 0;Intra_mbAddrA_window3 <= 0; + end + end + else + begin + Intra_mbAddrA_window0 <= 0;Intra_mbAddrA_window1 <= 0; + Intra_mbAddrA_window2 <= 0;Intra_mbAddrA_window3 <= 0; + end + + + //Intra_mbAddrB_window0 ~ 3 + always @ (mb_type_general or Intra16x16_predmode or Intra_chroma_predmode + or blk4x4_intra_calculate_counter or blk4x4_rec_counter + or Intra_mbAddrB_reg0 or Intra_mbAddrB_reg1 or Intra_mbAddrB_reg2 + or Intra_mbAddrB_reg3 or Intra_mbAddrB_reg4 or Intra_mbAddrB_reg5 + or Intra_mbAddrB_reg6 or Intra_mbAddrB_reg7 or Intra_mbAddrB_reg8 + or Intra_mbAddrB_reg9 or Intra_mbAddrB_reg10 or Intra_mbAddrB_reg11 + or Intra_mbAddrB_reg12 or Intra_mbAddrB_reg13 or Intra_mbAddrB_reg14 + or Intra_mbAddrB_reg15) + if (mb_type_general[3] == 1'b1) + begin + //Intra4x4 && Intra16x16_Vertical + if (blk4x4_rec_counter < 16 && blk4x4_intra_calculate_counter != 0 && + (mb_type_general[2] == 1'b1 || ( + (mb_type_general[2] == 1'b0 && Intra16x16_predmode == `Intra16x16_Vertical)))) + case (blk4x4_rec_counter) + 0,2,8,10: + begin + Intra_mbAddrB_window0 <= Intra_mbAddrB_reg0; + Intra_mbAddrB_window1 <= Intra_mbAddrB_reg1; + Intra_mbAddrB_window2 <= Intra_mbAddrB_reg2; + Intra_mbAddrB_window3 <= Intra_mbAddrB_reg3; + end + 1,3,9,11: + begin + Intra_mbAddrB_window0 <= Intra_mbAddrB_reg4; + Intra_mbAddrB_window1 <= Intra_mbAddrB_reg5; + Intra_mbAddrB_window2 <= Intra_mbAddrB_reg6; + Intra_mbAddrB_window3 <= Intra_mbAddrB_reg7; + end + 4,6,12,14: + begin + Intra_mbAddrB_window0 <= Intra_mbAddrB_reg8; + Intra_mbAddrB_window1 <= Intra_mbAddrB_reg9; + Intra_mbAddrB_window2 <= Intra_mbAddrB_reg10; + Intra_mbAddrB_window3 <= Intra_mbAddrB_reg11; + end + 5,7,13,15: + begin + Intra_mbAddrB_window0 <= Intra_mbAddrB_reg12; + Intra_mbAddrB_window1 <= Intra_mbAddrB_reg13; + Intra_mbAddrB_window2 <= Intra_mbAddrB_reg14; + Intra_mbAddrB_window3 <= Intra_mbAddrB_reg15; + end + default: + begin + Intra_mbAddrB_window0 <= 0;Intra_mbAddrB_window1 <= 0; + Intra_mbAddrB_window2 <= 0;Intra_mbAddrB_window3 <= 0; + end + endcase + //Chroma Cb/Cr Vertical and DC + else if (blk4x4_rec_counter > 15 && blk4x4_rec_counter < 24 && + (Intra_chroma_predmode == `Intra_chroma_Vertical || Intra_chroma_predmode == `Intra_chroma_DC) && blk4x4_intra_calculate_counter != 0) + case (blk4x4_rec_counter) + 16,18,20,22: + begin + Intra_mbAddrB_window0 <= Intra_mbAddrB_reg0; + Intra_mbAddrB_window1 <= Intra_mbAddrB_reg1; + Intra_mbAddrB_window2 <= Intra_mbAddrB_reg2; + Intra_mbAddrB_window3 <= Intra_mbAddrB_reg3; + end + 17,19,21,23: + begin + Intra_mbAddrB_window0 <= Intra_mbAddrB_reg4; + Intra_mbAddrB_window1 <= Intra_mbAddrB_reg5; + Intra_mbAddrB_window2 <= Intra_mbAddrB_reg6; + Intra_mbAddrB_window3 <= Intra_mbAddrB_reg7; + end + default: + begin + Intra_mbAddrB_window0 <= 0;Intra_mbAddrB_window1 <= 0; + Intra_mbAddrB_window2 <= 0;Intra_mbAddrB_window3 <= 0; + end + endcase + else + begin + Intra_mbAddrB_window0 <= 0;Intra_mbAddrB_window1 <= 0; + Intra_mbAddrB_window2 <= 0;Intra_mbAddrB_window3 <= 0; + end + end + else + begin + Intra_mbAddrB_window0 <= 0;Intra_mbAddrB_window1 <= 0; + Intra_mbAddrB_window2 <= 0;Intra_mbAddrB_window3 <= 0; + end + //Intra_mbAddrC_window0 ~ 3 + always @ (mb_type_general[3:2] or blk4x4_intra_calculate_counter or blk4x4_rec_counter or Intra4x4_predmode + or Intra_mbAddrC_reg0 or Intra_mbAddrC_reg1 or Intra_mbAddrC_reg2 or Intra_mbAddrC_reg3 + or Intra_mbAddrB_reg4 or Intra_mbAddrB_reg5 or Intra_mbAddrB_reg6 or Intra_mbAddrB_reg7 + or Intra_mbAddrB_reg8 or Intra_mbAddrB_reg9 or Intra_mbAddrB_reg10 or Intra_mbAddrB_reg11 + or Intra_mbAddrB_reg12 or Intra_mbAddrB_reg13 or Intra_mbAddrB_reg14 or Intra_mbAddrB_reg15 + or mbAddrC_availability or Intra_mbAddrB_window3) + if (mb_type_general[3:2] == 2'b11 && blk4x4_intra_calculate_counter != 0 && ( + Intra4x4_predmode == `Intra4x4_Diagonal_Down_Left || Intra4x4_predmode == `Intra4x4_Vertical_Left) && blk4x4_rec_counter < 16) + case (blk4x4_rec_counter) + 0,1,4: + begin + Intra_mbAddrC_window0 <= Intra_mbAddrC_reg0; + Intra_mbAddrC_window1 <= Intra_mbAddrC_reg1; + Intra_mbAddrC_window2 <= Intra_mbAddrC_reg2; + Intra_mbAddrC_window3 <= Intra_mbAddrC_reg3; + end + 5: + begin + Intra_mbAddrC_window0 <= (mbAddrC_availability)? Intra_mbAddrC_reg0:Intra_mbAddrB_reg15; + Intra_mbAddrC_window1 <= (mbAddrC_availability)? Intra_mbAddrC_reg1:Intra_mbAddrB_reg15; + Intra_mbAddrC_window2 <= (mbAddrC_availability)? Intra_mbAddrC_reg2:Intra_mbAddrB_reg15; + Intra_mbAddrC_window3 <= (mbAddrC_availability)? Intra_mbAddrC_reg3:Intra_mbAddrB_reg15; + end + 2,8,10: + begin + Intra_mbAddrC_window0 <= Intra_mbAddrB_reg4; + Intra_mbAddrC_window1 <= Intra_mbAddrB_reg5; + Intra_mbAddrC_window2 <= Intra_mbAddrB_reg6; + Intra_mbAddrC_window3 <= Intra_mbAddrB_reg7; + end + 9: + begin + Intra_mbAddrC_window0 <= Intra_mbAddrB_reg8; + Intra_mbAddrC_window1 <= Intra_mbAddrB_reg9; + Intra_mbAddrC_window2 <= Intra_mbAddrB_reg10; + Intra_mbAddrC_window3 <= Intra_mbAddrB_reg11; + end + 6,12,14: + begin + Intra_mbAddrC_window0 <= Intra_mbAddrB_reg12; + Intra_mbAddrC_window1 <= Intra_mbAddrB_reg13; + Intra_mbAddrC_window2 <= Intra_mbAddrB_reg14; + Intra_mbAddrC_window3 <= Intra_mbAddrB_reg15; + end + 3,11,7,13,15: + begin + Intra_mbAddrC_window0 <= Intra_mbAddrB_window3; + Intra_mbAddrC_window1 <= Intra_mbAddrB_window3; + Intra_mbAddrC_window2 <= Intra_mbAddrB_window3; + Intra_mbAddrC_window3 <= Intra_mbAddrB_window3; + end + default: + begin + Intra_mbAddrC_window0 <= 0; Intra_mbAddrC_window1 <= 0; + Intra_mbAddrC_window2 <= 0; Intra_mbAddrC_window3 <= 0; + end + endcase + else + begin + Intra_mbAddrC_window0 <= 0; Intra_mbAddrC_window1 <= 0; + Intra_mbAddrC_window2 <= 0; Intra_mbAddrC_window3 <= 0; + end + + //Intra_mbAddrD_window + always @ (mb_type_general[3:2] or blk4x4_rec_counter + or blk4x4_intra_calculate_counter or blk4x4_intra_precompute_counter + or Intra4x4_predmode or Intra16x16_predmode or Intra_chroma_predmode + or Intra_mbAddrD_reg0 or Intra_mbAddrD_reg1 or Intra_mbAddrD_reg2 + or Intra_mbAddrD_reg3 or Intra_mbAddrD_reg4 + or Intra_mbAddrD_LeftMB_luma_reg or Intra_mbAddrD_LeftMB_Cb_reg or Intra_mbAddrD_LeftMB_Cr_reg) + //Intra + if (mb_type_general[3] == 1'b1 && (blk4x4_intra_calculate_counter != 0 || blk4x4_intra_precompute_counter != 0)) + begin + //Intra luma + if (blk4x4_rec_counter[4] == 1'b0) + begin + //Intra4x4 luma + if (mb_type_general[2] == 1'b1 && (Intra4x4_predmode == `Intra4x4_Diagonal_Down_Right || + Intra4x4_predmode == `Intra4x4_Vertical_Right || + Intra4x4_predmode == `Intra4x4_Horizontal_Down)) + case (blk4x4_rec_counter[3:0]) + 0,2,8,10:Intra_mbAddrD_window <= Intra_mbAddrD_LeftMB_luma_reg; + 3,5,13 :Intra_mbAddrD_window <= Intra_mbAddrD_reg0; + 1,6,11 :Intra_mbAddrD_window <= Intra_mbAddrD_reg1; + 9,15 :Intra_mbAddrD_window <= Intra_mbAddrD_reg2; + 12 :Intra_mbAddrD_window <= Intra_mbAddrD_reg3; + 4,7,14 :Intra_mbAddrD_window <= Intra_mbAddrD_reg4; + endcase + //Intra16x16 + else + Intra_mbAddrD_window <= (Intra16x16_predmode == `Intra16x16_Plane)? Intra_mbAddrD_LeftMB_luma_reg:0; + end + //Intra chroma + else if (blk4x4_rec_counter > 15 && Intra_chroma_predmode == `Intra_chroma_Plane) + Intra_mbAddrD_window <= (blk4x4_rec_counter < 20)? Intra_mbAddrD_LeftMB_Cb_reg:Intra_mbAddrD_LeftMB_Cr_reg; + else + Intra_mbAddrD_window <= 0; + end + //Inter + else + Intra_mbAddrD_window <= 0; + + //seed + always @ (posedge gclk_seed or negedge reset_n) + if (reset_n == 1'b0) + begin + seed_0 <= 0; seed_1 <= 0; seed_2 <= 0; + end + else if (blk4x4_intra_precompute_counter == 1) + seed_0 <= main_seed; + else + case (blk4x4_rec_counter) + 0,2,8,16,20 :seed_0 <= PE3_sum_out; + 1,9 :seed_1 <= PE0_sum_out; + 3,11 :seed_2 <= PE0_sum_out; + endcase + + always @ (mb_type_general[3:2] or Intra16x16_predmode or Intra_chroma_predmode + or blk4x4_intra_calculate_counter or blk4x4_rec_counter or seed_0 or seed_1 or seed_2) + if (mb_type_general[3:2] == 2'b10 && Intra16x16_predmode == `Intra16x16_Plane && blk4x4_intra_calculate_counter == 4 && blk4x4_rec_counter < 16) + case (blk4x4_rec_counter) + 0,2,8,10:seed <= seed_0; + 4,12 :seed <= seed_1; + 6,14 :seed <= seed_2; + default :seed <= 0; + endcase + else if (mb_type_general[3] == 1'b1 && Intra_chroma_predmode == `Intra_chroma_Plane && blk4x4_intra_calculate_counter == 4 && blk4x4_rec_counter > 15) + if (blk4x4_rec_counter[0] == 1'b0) //16,18,20,22 + seed <= seed_0; + else + seed <= 0; + else + seed <= 0; + +endmodule + + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/Intra_pred_top.v b/demo_chip_rtl/rtl/nova/tags/Start/src/Intra_pred_top.v new file mode 100644 index 0000000..4fc626b --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/Intra_pred_top.v @@ -0,0 +1,334 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : Intra_pred_top.v +// Generated : Sep 30,2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Top module of Intra prediction +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module Intra_pred_top (clk,reset_n, + gclk_intra_mbAddrA_luma,gclk_intra_mbAddrA_Cb,gclk_intra_mbAddrA_Cr,gclk_intra_mbAddrB, + gclk_intra_mbAddrC_luma,gclk_intra_mbAddrD,gclk_seed,gclk_Intra_mbAddrB_RAM, + mb_num_h,mb_num_v,mb_type_general,NextMB_IsSkip, + Intra16x16_predmode,Intra4x4_predmode_CurrMb,Intra_chroma_predmode, + blk4x4_rec_counter,trigger_blk4x4_intra_pred,blk4x4_sum_counter, + sum_right_column_reg,blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out, + blk4x4_pred_output0, blk4x4_pred_output1, blk4x4_pred_output2, + blk4x4_pred_output4, blk4x4_pred_output5, blk4x4_pred_output6, + blk4x4_pred_output8, blk4x4_pred_output9, blk4x4_pred_output10, + blk4x4_pred_output12,blk4x4_pred_output13,blk4x4_pred_output14, + Intra_mbAddrB_RAM_wr,Intra_mbAddrB_RAM_wr_addr,Intra_mbAddrB_RAM_din, + + PE0_out,PE1_out,PE2_out,PE3_out,Intra4x4_predmode, + blk4x4_intra_preload_counter,blk4x4_intra_precompute_counter,blk4x4_intra_calculate_counter, + end_of_one_blk4x4_intra,Intra_mbAddrB_RAM_rd + ); + input clk,reset_n; + input gclk_intra_mbAddrA_luma; + input gclk_intra_mbAddrA_Cb; + input gclk_intra_mbAddrA_Cr; + input gclk_intra_mbAddrB; + input gclk_intra_mbAddrC_luma; + input gclk_intra_mbAddrD; + input gclk_seed; + input gclk_Intra_mbAddrB_RAM; + input [3:0] mb_num_h; + input [3:0] mb_num_v; + input [3:0] mb_type_general; + input NextMB_IsSkip; + input [1:0] Intra16x16_predmode; + input [63:0] Intra4x4_predmode_CurrMb; + input [1:0] Intra_chroma_predmode; + input [4:0] blk4x4_rec_counter; + input trigger_blk4x4_intra_pred; + input [2:0] blk4x4_sum_counter; + input [23:0] sum_right_column_reg; + input [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out; + input [7:0] blk4x4_pred_output0, blk4x4_pred_output1, blk4x4_pred_output2; + input [7:0] blk4x4_pred_output4, blk4x4_pred_output5, blk4x4_pred_output6; + input [7:0] blk4x4_pred_output8, blk4x4_pred_output9, blk4x4_pred_output10; + input [7:0] blk4x4_pred_output12,blk4x4_pred_output13,blk4x4_pred_output14; + input Intra_mbAddrB_RAM_wr; + input [6:0] Intra_mbAddrB_RAM_wr_addr; + input [31:0] Intra_mbAddrB_RAM_din; + + output [7:0] PE0_out; + output [7:0] PE1_out; + output [7:0] PE2_out; + output [7:0] PE3_out; + output [3:0] Intra4x4_predmode; + output [2:0] blk4x4_intra_preload_counter; + output [3:0] blk4x4_intra_precompute_counter; + output [2:0] blk4x4_intra_calculate_counter; + output end_of_one_blk4x4_intra; + output Intra_mbAddrB_RAM_rd; + + wire blkAddrA_availability,blkAddrB_availability; + wire mbAddrA_availability,mbAddrB_availability,mbAddrC_availability; + wire [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out; + wire [15:0] PE0_sum_out,PE3_sum_out; + wire Intra_mbAddrB_RAM_rd; + wire [6:0] Intra_mbAddrB_RAM_rd_addr; + wire [31:0] Intra_mbAddrB_RAM_dout; + + wire [7:0] Intra_mbAddrA_window0,Intra_mbAddrA_window1,Intra_mbAddrA_window2,Intra_mbAddrA_window3; + wire [7:0] Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3; + wire [7:0] Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7; + wire [7:0] Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11; + wire [7:0] Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15; + + wire [7:0] Intra_mbAddrB_window0,Intra_mbAddrB_window1,Intra_mbAddrB_window2,Intra_mbAddrB_window3; + wire [7:0] Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3; + wire [7:0] Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7; + wire [7:0] Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11; + wire [7:0] Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15; + + wire [7:0] Intra_mbAddrC_window0,Intra_mbAddrC_window1,Intra_mbAddrC_window2,Intra_mbAddrC_window3; + wire [7:0] Intra_mbAddrD_window; + wire [15:0] main_seed,seed; + wire [11:0] plane_b_reg,plane_c_reg; + + Intra_pred_pipeline Intra_pred_pipeline ( + .clk(clk), + .reset_n(reset_n), + .mb_type_general(mb_type_general), + .blk4x4_rec_counter(blk4x4_rec_counter), + .trigger_blk4x4_intra_pred(trigger_blk4x4_intra_pred), + .mb_num_v(mb_num_v), + .mb_num_h(mb_num_h), + .blk4x4_sum_counter(blk4x4_sum_counter), + .NextMB_IsSkip(NextMB_IsSkip), + .Intra16x16_predmode(Intra16x16_predmode), + .Intra4x4_predmode_CurrMb(Intra4x4_predmode_CurrMb), + .Intra_chroma_predmode(Intra_chroma_predmode), + .Intra_mbAddrA_reg0(Intra_mbAddrA_reg0), + .Intra_mbAddrA_reg1(Intra_mbAddrA_reg1), + .Intra_mbAddrA_reg2(Intra_mbAddrA_reg2), + .Intra_mbAddrA_reg3(Intra_mbAddrA_reg3), + .Intra_mbAddrA_reg4(Intra_mbAddrA_reg4), + .Intra_mbAddrA_reg5(Intra_mbAddrA_reg5), + .Intra_mbAddrA_reg6(Intra_mbAddrA_reg6), + .Intra_mbAddrA_reg7(Intra_mbAddrA_reg7), + .Intra_mbAddrA_reg8(Intra_mbAddrA_reg8), + .Intra_mbAddrA_reg9(Intra_mbAddrA_reg9), + .Intra_mbAddrA_reg10(Intra_mbAddrA_reg10), + .Intra_mbAddrA_reg11(Intra_mbAddrA_reg11), + .Intra_mbAddrA_reg12(Intra_mbAddrA_reg12), + .Intra_mbAddrA_reg13(Intra_mbAddrA_reg13), + .Intra_mbAddrA_reg14(Intra_mbAddrA_reg14), + .Intra_mbAddrA_reg15(Intra_mbAddrA_reg15), + .Intra_mbAddrB_reg0(Intra_mbAddrB_reg0), + .Intra_mbAddrB_reg1(Intra_mbAddrB_reg1), + .Intra_mbAddrB_reg2(Intra_mbAddrB_reg2), + .Intra_mbAddrB_reg3(Intra_mbAddrB_reg3), + .Intra_mbAddrB_reg4(Intra_mbAddrB_reg4), + .Intra_mbAddrB_reg5(Intra_mbAddrB_reg5), + .Intra_mbAddrB_reg6(Intra_mbAddrB_reg6), + .Intra_mbAddrB_reg7(Intra_mbAddrB_reg7), + .Intra_mbAddrB_reg8(Intra_mbAddrB_reg8), + .Intra_mbAddrB_reg9(Intra_mbAddrB_reg9), + .Intra_mbAddrB_reg10(Intra_mbAddrB_reg10), + .Intra_mbAddrB_reg11(Intra_mbAddrB_reg11), + .Intra_mbAddrB_reg12(Intra_mbAddrB_reg12), + .Intra_mbAddrB_reg13(Intra_mbAddrB_reg13), + .Intra_mbAddrB_reg14(Intra_mbAddrB_reg14), + .Intra_mbAddrB_reg15(Intra_mbAddrB_reg15), + .Intra_mbAddrD_window(Intra_mbAddrD_window), + + .Intra4x4_predmode(Intra4x4_predmode), + .blk4x4_intra_preload_counter(blk4x4_intra_preload_counter), + .blk4x4_intra_precompute_counter(blk4x4_intra_precompute_counter), + .blk4x4_intra_calculate_counter(blk4x4_intra_calculate_counter), + .end_of_one_blk4x4_intra(end_of_one_blk4x4_intra), + .blkAddrA_availability(blkAddrA_availability), + .blkAddrB_availability(blkAddrB_availability), + .mbAddrA_availability(mbAddrA_availability), + .mbAddrB_availability(mbAddrB_availability), + .mbAddrC_availability(mbAddrC_availability), + .main_seed(main_seed), + .plane_b_reg(plane_b_reg), + .plane_c_reg(plane_c_reg), + .Intra_mbAddrB_RAM_rd(Intra_mbAddrB_RAM_rd), + .Intra_mbAddrB_RAM_rd_addr(Intra_mbAddrB_RAM_rd_addr) + ); + + Intra_pred_reg_ctrl Intra_pred_reg_ctrl ( + .reset_n(reset_n), + .gclk_intra_mbAddrA_luma(gclk_intra_mbAddrA_luma), + .gclk_intra_mbAddrA_Cb(gclk_intra_mbAddrA_Cb), + .gclk_intra_mbAddrA_Cr(gclk_intra_mbAddrA_Cr), + .gclk_intra_mbAddrB(gclk_intra_mbAddrB), + .gclk_intra_mbAddrC_luma(gclk_intra_mbAddrC_luma), + .gclk_intra_mbAddrD(gclk_intra_mbAddrD), + .gclk_seed(gclk_seed), + .mbAddrA_availability(mbAddrA_availability), + .mbAddrC_availability(mbAddrC_availability), + .blk4x4_rec_counter(blk4x4_rec_counter), + .blk4x4_sum_counter(blk4x4_sum_counter), + .blk4x4_intra_preload_counter(blk4x4_intra_preload_counter), + .blk4x4_intra_precompute_counter(blk4x4_intra_precompute_counter), + .blk4x4_intra_calculate_counter(blk4x4_intra_calculate_counter), + .mb_type_general(mb_type_general), + .Intra4x4_predmode(Intra4x4_predmode), + .Intra16x16_predmode(Intra16x16_predmode), + .Intra_chroma_predmode(Intra_chroma_predmode), + .Intra_mbAddrB_RAM_dout(Intra_mbAddrB_RAM_dout), + .sum_right_column_reg(sum_right_column_reg), + .blk4x4_sum_PE0_out(blk4x4_sum_PE0_out), + .blk4x4_sum_PE1_out(blk4x4_sum_PE1_out), + .blk4x4_sum_PE2_out(blk4x4_sum_PE2_out), + .blk4x4_sum_PE3_out(blk4x4_sum_PE3_out), + .main_seed(main_seed), + .PE0_sum_out(PE0_sum_out), + .PE3_sum_out(PE3_sum_out), + + .Intra_mbAddrA_window0(Intra_mbAddrA_window0), + .Intra_mbAddrA_window1(Intra_mbAddrA_window1), + .Intra_mbAddrA_window2(Intra_mbAddrA_window2), + .Intra_mbAddrA_window3(Intra_mbAddrA_window3), + .Intra_mbAddrA_reg0(Intra_mbAddrA_reg0), + .Intra_mbAddrA_reg1(Intra_mbAddrA_reg1), + .Intra_mbAddrA_reg2(Intra_mbAddrA_reg2), + .Intra_mbAddrA_reg3(Intra_mbAddrA_reg3), + .Intra_mbAddrA_reg4(Intra_mbAddrA_reg4), + .Intra_mbAddrA_reg5(Intra_mbAddrA_reg5), + .Intra_mbAddrA_reg6(Intra_mbAddrA_reg6), + .Intra_mbAddrA_reg7(Intra_mbAddrA_reg7), + .Intra_mbAddrA_reg8(Intra_mbAddrA_reg8), + .Intra_mbAddrA_reg9(Intra_mbAddrA_reg9), + .Intra_mbAddrA_reg10(Intra_mbAddrA_reg10), + .Intra_mbAddrA_reg11(Intra_mbAddrA_reg11), + .Intra_mbAddrA_reg12(Intra_mbAddrA_reg12), + .Intra_mbAddrA_reg13(Intra_mbAddrA_reg13), + .Intra_mbAddrA_reg14(Intra_mbAddrA_reg14), + .Intra_mbAddrA_reg15(Intra_mbAddrA_reg15), + .Intra_mbAddrB_window0(Intra_mbAddrB_window0), + .Intra_mbAddrB_window1(Intra_mbAddrB_window1), + .Intra_mbAddrB_window2(Intra_mbAddrB_window2), + .Intra_mbAddrB_window3(Intra_mbAddrB_window3), + .Intra_mbAddrB_reg0(Intra_mbAddrB_reg0), + .Intra_mbAddrB_reg1(Intra_mbAddrB_reg1), + .Intra_mbAddrB_reg2(Intra_mbAddrB_reg2), + .Intra_mbAddrB_reg3(Intra_mbAddrB_reg3), + .Intra_mbAddrB_reg4(Intra_mbAddrB_reg4), + .Intra_mbAddrB_reg5(Intra_mbAddrB_reg5), + .Intra_mbAddrB_reg6(Intra_mbAddrB_reg6), + .Intra_mbAddrB_reg7(Intra_mbAddrB_reg7), + .Intra_mbAddrB_reg8(Intra_mbAddrB_reg8), + .Intra_mbAddrB_reg9(Intra_mbAddrB_reg9), + .Intra_mbAddrB_reg10(Intra_mbAddrB_reg10), + .Intra_mbAddrB_reg11(Intra_mbAddrB_reg11), + .Intra_mbAddrB_reg12(Intra_mbAddrB_reg12), + .Intra_mbAddrB_reg13(Intra_mbAddrB_reg13), + .Intra_mbAddrB_reg14(Intra_mbAddrB_reg14), + .Intra_mbAddrB_reg15(Intra_mbAddrB_reg15), + .Intra_mbAddrC_window0(Intra_mbAddrC_window0), + .Intra_mbAddrC_window1(Intra_mbAddrC_window1), + .Intra_mbAddrC_window2(Intra_mbAddrC_window2), + .Intra_mbAddrC_window3(Intra_mbAddrC_window3), + .Intra_mbAddrD_window(Intra_mbAddrD_window), + .seed(seed) + ); + + Intra_pred_PE Intra_pred_PE ( + .clk(clk), + .reset_n(reset_n), + .mb_type_general(mb_type_general), + .blk4x4_rec_counter(blk4x4_rec_counter), + .blk4x4_intra_calculate_counter(blk4x4_intra_calculate_counter), + .Intra4x4_predmode(Intra4x4_predmode), + .Intra16x16_predmode(Intra16x16_predmode), + .Intra_chroma_predmode(Intra_chroma_predmode), + .blkAddrA_availability(blkAddrA_availability), + .blkAddrB_availability(blkAddrB_availability), + .mbAddrA_availability(mbAddrA_availability), + .mbAddrB_availability(mbAddrB_availability), + .Intra_mbAddrA_window0({8'b0,Intra_mbAddrA_window0}), + .Intra_mbAddrA_window1({8'b0,Intra_mbAddrA_window1}), + .Intra_mbAddrA_window2({8'b0,Intra_mbAddrA_window2}), + .Intra_mbAddrA_window3({8'b0,Intra_mbAddrA_window3}), + .Intra_mbAddrB_window0({8'b0,Intra_mbAddrB_window0}), + .Intra_mbAddrB_window1({8'b0,Intra_mbAddrB_window1}), + .Intra_mbAddrB_window2({8'b0,Intra_mbAddrB_window2}), + .Intra_mbAddrB_window3({8'b0,Intra_mbAddrB_window3}), + .Intra_mbAddrC_window0({8'b0,Intra_mbAddrC_window0}), + .Intra_mbAddrC_window1({8'b0,Intra_mbAddrC_window1}), + .Intra_mbAddrC_window2({8'b0,Intra_mbAddrC_window2}), + .Intra_mbAddrC_window3({8'b0,Intra_mbAddrC_window3}), + .Intra_mbAddrD_window({8'b0,Intra_mbAddrD_window}), + .Intra_mbAddrA_reg0({8'b0,Intra_mbAddrA_reg0}), + .Intra_mbAddrA_reg1({8'b0,Intra_mbAddrA_reg1}), + .Intra_mbAddrA_reg2({8'b0,Intra_mbAddrA_reg2}), + .Intra_mbAddrA_reg3({8'b0,Intra_mbAddrA_reg3}), + .Intra_mbAddrA_reg4({8'b0,Intra_mbAddrA_reg4}), + .Intra_mbAddrA_reg5({8'b0,Intra_mbAddrA_reg5}), + .Intra_mbAddrA_reg6({8'b0,Intra_mbAddrA_reg6}), + .Intra_mbAddrA_reg7({8'b0,Intra_mbAddrA_reg7}), + .Intra_mbAddrA_reg8({8'b0,Intra_mbAddrA_reg8}), + .Intra_mbAddrA_reg9({8'b0,Intra_mbAddrA_reg9}), + .Intra_mbAddrA_reg10({8'b0,Intra_mbAddrA_reg10}), + .Intra_mbAddrA_reg11({8'b0,Intra_mbAddrA_reg11}), + .Intra_mbAddrA_reg12({8'b0,Intra_mbAddrA_reg12}), + .Intra_mbAddrA_reg13({8'b0,Intra_mbAddrA_reg13}), + .Intra_mbAddrA_reg14({8'b0,Intra_mbAddrA_reg14}), + .Intra_mbAddrA_reg15({8'b0,Intra_mbAddrA_reg15}), + .Intra_mbAddrB_reg0({8'b0,Intra_mbAddrB_reg0}), + .Intra_mbAddrB_reg1({8'b0,Intra_mbAddrB_reg1}), + .Intra_mbAddrB_reg2({8'b0,Intra_mbAddrB_reg2}), + .Intra_mbAddrB_reg3({8'b0,Intra_mbAddrB_reg3}), + .Intra_mbAddrB_reg4({8'b0,Intra_mbAddrB_reg4}), + .Intra_mbAddrB_reg5({8'b0,Intra_mbAddrB_reg5}), + .Intra_mbAddrB_reg6({8'b0,Intra_mbAddrB_reg6}), + .Intra_mbAddrB_reg7({8'b0,Intra_mbAddrB_reg7}), + .Intra_mbAddrB_reg8({8'b0,Intra_mbAddrB_reg8}), + .Intra_mbAddrB_reg9({8'b0,Intra_mbAddrB_reg9}), + .Intra_mbAddrB_reg10({8'b0,Intra_mbAddrB_reg10}), + .Intra_mbAddrB_reg11({8'b0,Intra_mbAddrB_reg11}), + .Intra_mbAddrB_reg12({8'b0,Intra_mbAddrB_reg12}), + .Intra_mbAddrB_reg13({8'b0,Intra_mbAddrB_reg13}), + .Intra_mbAddrB_reg14({8'b0,Intra_mbAddrB_reg14}), + .Intra_mbAddrB_reg15({8'b0,Intra_mbAddrB_reg15}), + .blk4x4_pred_output0({8'b0,blk4x4_pred_output0}), + .blk4x4_pred_output1({8'b0,blk4x4_pred_output1}), + .blk4x4_pred_output2({8'b0,blk4x4_pred_output2}), + .blk4x4_pred_output4({8'b0,blk4x4_pred_output4}), + .blk4x4_pred_output5({8'b0,blk4x4_pred_output5}), + .blk4x4_pred_output6({8'b0,blk4x4_pred_output6}), + .blk4x4_pred_output8({8'b0,blk4x4_pred_output8}), + .blk4x4_pred_output9({8'b0,blk4x4_pred_output9}), + .blk4x4_pred_output10({8'b0,blk4x4_pred_output10}), + .blk4x4_pred_output12({8'b0,blk4x4_pred_output12}), + .blk4x4_pred_output13({8'b0,blk4x4_pred_output13}), + .blk4x4_pred_output14({8'b0,blk4x4_pred_output14}), + .seed(seed), + .b(plane_b_reg), + .c(plane_c_reg), + + .PE0_out(PE0_out), + .PE1_out(PE1_out), + .PE2_out(PE2_out), + .PE3_out(PE3_out), + .PE0_sum_out(PE0_sum_out), + .PE3_sum_out(PE3_sum_out) + ); + ram_sync_1r_sync_1w #(`Intra_mbAddrB_RAM_data_width,`Intra_mbAddrB_RAM_data_depth) + Intra_mbAddrB_RAM ( + .clk(gclk_Intra_mbAddrB_RAM), + .rst_n(reset_n), + .wr_n(~Intra_mbAddrB_RAM_wr), + .rd_n(~Intra_mbAddrB_RAM_rd), + .wr_addr(Intra_mbAddrB_RAM_wr_addr), + .rd_addr(Intra_mbAddrB_RAM_rd_addr), + .data_in(Intra_mbAddrB_RAM_din), + .data_out(Intra_mbAddrB_RAM_dout) + ); +endmodule \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/NumCoeffTrailingOnes_decoding.v b/demo_chip_rtl/rtl/nova/tags/Start/src/NumCoeffTrailingOnes_decoding.v new file mode 100644 index 0000000..57a2866 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/NumCoeffTrailingOnes_decoding.v @@ -0,0 +1,678 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : NumCoeffTrailingOnes_decoding.v +// Generated : June 8, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Decoding for Table 9-5 on Page159 of H.264/AVC standard 2003 +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module NumCoeffTrailingOnes_decoding (clk,reset_n,cavlc_decoder_state,heading_one_pos,BitStream_buffer_output, + nC,TrailingOnes,TotalCoeff,NumCoeffTrailingOnes_len); + input clk,reset_n; + input [3:0] cavlc_decoder_state; + input [3:0] heading_one_pos; + input [15:0] BitStream_buffer_output; + input [4:0] nC; + output [1:0] TrailingOnes; + output [4:0] TotalCoeff; + output [4:0] NumCoeffTrailingOnes_len; + reg [1:0] TrailingOnes; + reg [4:0] TotalCoeff; + reg [4:0] NumCoeffTrailingOnes_len; + + reg [1:0] TrailingOnes_reg; + reg [4:0] TotalCoeff_reg; + + wire nC_0to2,nC_2to4,nC_4to8,nC_n1,nC_GE8; + wire nC_0to2_t0,nC_0to2_t1,nC_0to2_t2,nC_0to2_t3; + wire nC_2to4_t0,nC_2to4_t1,nC_2to4_t2,nC_2to4_t3; + wire nC_4to8_t0,nC_4to8_t1; + wire nC_n1_t0; + //Select nC values to choose table + assign nC_0to2 = (cavlc_decoder_state == `NumCoeffTrailingOnes_LUT && (nC == 5'd0 || nC == 5'd1)); + assign nC_2to4 = (cavlc_decoder_state == `NumCoeffTrailingOnes_LUT && (nC == 5'd2 || nC == 5'd3)); + assign nC_4to8 = (cavlc_decoder_state == `NumCoeffTrailingOnes_LUT && (nC == 5'd4 || nC == 5'd5 || nC == 5'd6 || nC == 5'd7)); + assign nC_n1 = (cavlc_decoder_state == `NumCoeffTrailingOnes_LUT && (nC == 5'd31)); + assign nC_GE8 = (cavlc_decoder_state == `NumCoeffTrailingOnes_LUT && !nC_0to2 && !nC_2to4 && !nC_4to8 && !nC_n1); + + //1.nC_0to2 t0 ~ t4 sub-table selection + assign nC_0to2_t0 = (nC_0to2 && (heading_one_pos == 4'd0 || heading_one_pos == 4'd1 || heading_one_pos == 4'd2)); + assign nC_0to2_t1 = (nC_0to2 && (heading_one_pos == 4'd3 || heading_one_pos == 4'd4)); + assign nC_0to2_t2 = (nC_0to2 && (heading_one_pos == 4'd5 || heading_one_pos == 4'd6 || heading_one_pos == 4'd7 || heading_one_pos == 4'd8)); + assign nC_0to2_t3 = (nC_0to2 && (heading_one_pos == 4'd9 || heading_one_pos == 4'd10)); + //2.nC_2to4 t0 ~ t4 sub-table selection + assign nC_2to4_t0 = (nC_2to4 && (heading_one_pos == 4'd0 || heading_one_pos == 4'd1)); + assign nC_2to4_t1 = (nC_2to4 && (heading_one_pos == 4'd2 || heading_one_pos == 4'd3)); + assign nC_2to4_t2 = (nC_2to4 && (heading_one_pos == 4'd4 || heading_one_pos == 4'd5 || heading_one_pos == 4'd6)); + assign nC_2to4_t3 = (nC_2to4 && (heading_one_pos == 4'd7 || heading_one_pos == 4'd8)); + //3.nC_4to8 t0 ~ t2 sub-table selection + assign nC_4to8_t0 = (nC_4to8 && heading_one_pos == 4'd0); + assign nC_4to8_t1 = (nC_4to8 && (heading_one_pos == 4'd1 || heading_one_pos == 4'd2 || heading_one_pos == 4'd3 || heading_one_pos == 4'd4)); + //4.nC_GE8:single table, NO sub-table selection + //5.nC_n1 t0 ~ t1 sub-table selection + assign nC_n1_t0 = (nC_n1 && (heading_one_pos == 4'd0 || heading_one_pos == 4'd1 || heading_one_pos == 4'd2)); + + //NumCoeffTrailingOnes_len + always @ (nC_0to2 or nC_2to4 or nC_4to8 or nC_GE8 or nC_n1 or heading_one_pos or BitStream_buffer_output) + if (nC_0to2) + case (heading_one_pos) + 0 :NumCoeffTrailingOnes_len <= 5'd1; + 1 :NumCoeffTrailingOnes_len <= 5'd2; + 2 :NumCoeffTrailingOnes_len <= 5'd3; + 3 :NumCoeffTrailingOnes_len <= (BitStream_buffer_output[11] == 1)? 5'd5:5'd6; + 4 :NumCoeffTrailingOnes_len <= (BitStream_buffer_output[10] == 1)? 5'd6:5'd7; + 5 :NumCoeffTrailingOnes_len <= 5'd8; + 6 :NumCoeffTrailingOnes_len <= 5'd9; + 7 :NumCoeffTrailingOnes_len <= 5'd10; + 8 :NumCoeffTrailingOnes_len <= 5'd11; + 9 :NumCoeffTrailingOnes_len <= 5'd13; + 10:NumCoeffTrailingOnes_len <= 5'd14; + 11:NumCoeffTrailingOnes_len <= 5'd15; + 12:NumCoeffTrailingOnes_len <= 5'd16; + 13:NumCoeffTrailingOnes_len <= 5'd16; + 14:NumCoeffTrailingOnes_len <= 5'd15; + default:NumCoeffTrailingOnes_len <= 5'd0; + endcase + else if (nC_2to4) + case (heading_one_pos) + 0 :NumCoeffTrailingOnes_len <= 5'd2; + 1 :NumCoeffTrailingOnes_len <= (BitStream_buffer_output[13] == 1)? 5'd3:5'd4; + 2 :NumCoeffTrailingOnes_len <= (BitStream_buffer_output[12] == 1)? 5'd5:5'd6; + 3 :NumCoeffTrailingOnes_len <= 5'd6; + 4 :NumCoeffTrailingOnes_len <= 5'd7; + 5 :NumCoeffTrailingOnes_len <= 5'd8; + 6 :NumCoeffTrailingOnes_len <= 5'd9; + 7 :NumCoeffTrailingOnes_len <= 5'd11; + 8 :NumCoeffTrailingOnes_len <= 5'd12; + 9 :NumCoeffTrailingOnes_len <= 5'd13; + 10:NumCoeffTrailingOnes_len <= (BitStream_buffer_output[4] == 1)? 5'd13:5'd14; + 11:NumCoeffTrailingOnes_len <= 5'd14; + 12:NumCoeffTrailingOnes_len <= 5'd13; + default:NumCoeffTrailingOnes_len <= 5'd0; + endcase + else if (nC_n1) + case (heading_one_pos) + 0:NumCoeffTrailingOnes_len <= 5'd1; + 1:NumCoeffTrailingOnes_len <= 5'd2; + 2:NumCoeffTrailingOnes_len <= 5'd3; + 3:NumCoeffTrailingOnes_len <= 5'd6; + 4:NumCoeffTrailingOnes_len <= 5'd6; + 5:NumCoeffTrailingOnes_len <= 5'd7; + 6:NumCoeffTrailingOnes_len <= 5'd8; + default:NumCoeffTrailingOnes_len <= 5'd7; + endcase + else if (nC_4to8) + case (heading_one_pos) + 0 :NumCoeffTrailingOnes_len <= 5'd4; + 1 :NumCoeffTrailingOnes_len <= 5'd5; + 2 :NumCoeffTrailingOnes_len <= 5'd6; + 3 :NumCoeffTrailingOnes_len <= 5'd7; + 4 :NumCoeffTrailingOnes_len <= 5'd8; + 5 :NumCoeffTrailingOnes_len <= 5'd9; + 6 :NumCoeffTrailingOnes_len <= (BitStream_buffer_output[8:7] == 2'b11)? 5'd9:5'd10; + 7 :NumCoeffTrailingOnes_len <= 5'd10; + 8 :NumCoeffTrailingOnes_len <= 5'd10; + 9 :NumCoeffTrailingOnes_len <= 5'd10; + 10:NumCoeffTrailingOnes_len <= 5'd10; + default:NumCoeffTrailingOnes_len <= 5'd0; + endcase + else if (nC_GE8) + NumCoeffTrailingOnes_len <= 5'd6; + else + NumCoeffTrailingOnes_len <= 0; + + + //TrailingOnes + always @ (posedge clk) + if (reset_n == 0) + TrailingOnes_reg <= 0; + else if (cavlc_decoder_state == `NumCoeffTrailingOnes_LUT) + TrailingOnes_reg <= TrailingOnes; + + always @ (nC_0to2 or nC_2to4 or nC_4to8 or nC_n1 or nC_GE8 + or nC_0to2_t0 or nC_0to2_t1 or nC_0to2_t2 or nC_0to2_t3 + or nC_2to4_t0 or nC_2to4_t1 or nC_2to4_t2 or nC_2to4_t3 + or nC_4to8_t0 or nC_4to8_t1 or nC_n1_t0 + or TrailingOnes_reg or heading_one_pos or BitStream_buffer_output) + if (nC_0to2) + begin + if (nC_0to2_t0) + TrailingOnes <= heading_one_pos[1:0]; + else if (nC_0to2_t1) + begin + if (heading_one_pos == 4'd3 && !BitStream_buffer_output[11]) + TrailingOnes <= (BitStream_buffer_output[10])? 2'd0:2'd1; + else if (heading_one_pos == 4'd4 && BitStream_buffer_output[10:9] == 2'b01) + TrailingOnes <= 2'd2; + else + TrailingOnes <= 2'd3; + end + else if (nC_0to2_t2) + begin + if (heading_one_pos == 4'd5) + case (BitStream_buffer_output[9:8]) + 2'b00:TrailingOnes <= 2'd3; + 2'b01:TrailingOnes <= 2'd2; + 2'b10:TrailingOnes <= 2'd1; + 2'b11:TrailingOnes <= 2'd0; + endcase + else if (heading_one_pos == 4'd6) + case (BitStream_buffer_output[8:7]) + 2'b00:TrailingOnes <= 2'd3; + 2'b01:TrailingOnes <= 2'd2; + 2'b10:TrailingOnes <= 2'd1; + 2'b11:TrailingOnes <= 2'd0; + endcase + else if (heading_one_pos == 4'd7) + case (BitStream_buffer_output[7:6]) + 2'b00:TrailingOnes <= 2'd3; + 2'b01:TrailingOnes <= 2'd2; + 2'b10:TrailingOnes <= 2'd1; + 2'b11:TrailingOnes <= 2'd0; + endcase + else + case (BitStream_buffer_output[6:5]) + 2'b00:TrailingOnes <= 2'd3; + 2'b01:TrailingOnes <= 2'd2; + 2'b10:TrailingOnes <= 2'd1; + 2'b11:TrailingOnes <= 2'd0; + endcase + end + else if (nC_0to2_t3) + begin + if (heading_one_pos == 4'd9) + case (BitStream_buffer_output[4:3]) + 2'b00:TrailingOnes <= (BitStream_buffer_output[5])? 2'd3:2'd0; + 2'b10:TrailingOnes <= 2'd1; + 2'b01:TrailingOnes <= 2'd2; + 2'b11:TrailingOnes <= 2'd0; + endcase + else + case (BitStream_buffer_output[3:2]) + 2'b00:TrailingOnes <= 2'd3; + 2'b01:TrailingOnes <= 2'd2; + 2'b10:TrailingOnes <= 2'd1; + 2'b11:TrailingOnes <= 2'd0; + endcase + end + else + begin + if ((heading_one_pos == 4'd11 && BitStream_buffer_output[2:1] == 2'b11) || + (heading_one_pos == 4'd12 && BitStream_buffer_output[1:0] == 2'b11) || + (heading_one_pos == 4'd13 && (BitStream_buffer_output[1:0] == 2'b00 || BitStream_buffer_output[1:0] == 2'b11))) + TrailingOnes <= 2'd0; + else if ((heading_one_pos == 4'd11 && BitStream_buffer_output[2:1] == 2'b10) || + (heading_one_pos == 4'd12 && BitStream_buffer_output[1:0] == 2'b10) || + (heading_one_pos == 4'd13 && BitStream_buffer_output[1:0] == 2'b10) || + heading_one_pos == 4'd14) + TrailingOnes <= 2'd1; + else if ((heading_one_pos == 4'd11 && BitStream_buffer_output[2:1] == 2'b01) || + (heading_one_pos == 4'd12 && BitStream_buffer_output[1:0] == 2'b01) || + (heading_one_pos == 4'd13 && BitStream_buffer_output[1:0] == 2'b01)) + TrailingOnes <= 2'd2; + else + TrailingOnes <= 2'd3; + end + end + else if (nC_2to4) + begin + if (nC_2to4_t0) + begin + if (heading_one_pos == 4'd0) + TrailingOnes <= {1'b0,~BitStream_buffer_output[14]}; + else + TrailingOnes <= (BitStream_buffer_output[13])? 2'd2:2'd3; + end + else if (nC_2to4_t1) + begin + if ((heading_one_pos == 4'd2 && BitStream_buffer_output[12:10] == 3'b011) || + (heading_one_pos == 4'd3 && BitStream_buffer_output[11:10] == 2'b11)) + TrailingOnes <= 2'd0; + else if ((heading_one_pos == 4'd2 && (BitStream_buffer_output[12:11] == 2'b11 || BitStream_buffer_output[12:10] == 3'b010)) || + (heading_one_pos == 4'd3 && BitStream_buffer_output[11:10] == 2'b10)) + TrailingOnes <= 2'd1; + else if ((heading_one_pos == 4'd2 && BitStream_buffer_output[12:10] == 3'b001) || + (heading_one_pos == 4'd3 && BitStream_buffer_output[11:10] == 2'b01)) + TrailingOnes <= 2'd2; + else + TrailingOnes <= 2'd3; + end + else if (nC_2to4_t2) + begin + if (heading_one_pos == 4'd4) + case (BitStream_buffer_output[10:9]) + 2'b00:TrailingOnes <= 2'd3; + 2'b01:TrailingOnes <= 2'd2; + 2'b10:TrailingOnes <= 2'd1; + 2'b11:TrailingOnes <= 2'd0; + endcase + else if (heading_one_pos == 4'd5) + case (BitStream_buffer_output[9:8]) + 2'b00:TrailingOnes <= 2'd0; + 2'b01:TrailingOnes <= 2'd2; + 2'b10:TrailingOnes <= 2'd1; + 2'b11:TrailingOnes <= 2'd0; + endcase + else + case (BitStream_buffer_output[8:7]) + 2'b00:TrailingOnes <= 2'd3; + 2'b01:TrailingOnes <= 2'd2; + 2'b10:TrailingOnes <= 2'd1; + 2'b11:TrailingOnes <= 2'd0; + endcase + end + else if (nC_2to4_t3) + begin + if ((heading_one_pos == 4'd7 && BitStream_buffer_output[6:5] == 2'b11) || + (heading_one_pos == 4'd8 && (BitStream_buffer_output[5:4] == 2'b11 || BitStream_buffer_output[6:4] == 3'b000))) + TrailingOnes <= 2'd0; + else if ((heading_one_pos == 4'd7 && BitStream_buffer_output[6:5] == 2'b10) || + (heading_one_pos == 4'd8 && BitStream_buffer_output[5:4] == 2'b10)) + TrailingOnes <= 2'd1; + else if ((heading_one_pos == 4'd7 && BitStream_buffer_output[6:5] == 2'b01) || + (heading_one_pos == 4'd8 && BitStream_buffer_output[5:4] == 2'b01)) + TrailingOnes <= 2'd2; + else + TrailingOnes <= 2'd3; + end + else + begin + if ((heading_one_pos == 4'd9 && BitStream_buffer_output[4:3] == 2'b11) || + (heading_one_pos == 4'd10 && (BitStream_buffer_output[4:3] == 2'b11 || BitStream_buffer_output[4:2] == 3'b001)) || + (heading_one_pos == 4'd11 && BitStream_buffer_output[3:2] == 2'b11)) + TrailingOnes <= 2'd0; + else if ((heading_one_pos == 4'd9 && BitStream_buffer_output[4:3] == 2'b10) || + (heading_one_pos == 4'd10 && (BitStream_buffer_output[4:2] == 3'b000 || BitStream_buffer_output[4:2] == 3'b011)) || + (heading_one_pos == 4'd11 && BitStream_buffer_output[3:2] == 2'b10)) + TrailingOnes <= 2'd1; + else if ((heading_one_pos == 4'd9 && BitStream_buffer_output[4:3] == 2'b01) || + (heading_one_pos == 4'd10 && (BitStream_buffer_output[4:3] == 2'b10 || BitStream_buffer_output[4:2] == 3'b010)) || + (heading_one_pos == 4'd11 && BitStream_buffer_output[3:2] == 2'b01)) + TrailingOnes <= 2'd2; + else + TrailingOnes <= 2'd3; + end + end + else if (nC_n1) + begin + if (nC_n1_t0) + begin + if (BitStream_buffer_output[15]) TrailingOnes <= 2'd1; + else if (BitStream_buffer_output[14]) TrailingOnes <= 2'd0; + else TrailingOnes <= 2'd2; + end + else + begin + if ((heading_one_pos == 4'd3 && (BitStream_buffer_output[11:10] == 2'b00 || BitStream_buffer_output[11:10] == 2'b11)) || + heading_one_pos == 4'd4) + TrailingOnes <= 2'd0; + else if ((heading_one_pos == 4'd3 && BitStream_buffer_output[11:10] == 2'b10) || + (heading_one_pos == 4'd5 && BitStream_buffer_output[9]) || + (heading_one_pos == 4'd6 && BitStream_buffer_output[8])) + TrailingOnes <= 2'd1; + else if ((heading_one_pos == 4'd5 && !BitStream_buffer_output[9]) || + (heading_one_pos == 4'd6 && !BitStream_buffer_output[8])) + TrailingOnes <= 2'd2; + else + TrailingOnes <= 2'd3; + end + end + else if (nC_4to8) + begin + if (nC_4to8_t0) + begin + if (BitStream_buffer_output[14:12] == 3'b111) TrailingOnes <= 2'd0; + else if (BitStream_buffer_output[14:12] == 3'b110) TrailingOnes <= 2'd1; + else if (BitStream_buffer_output[14:12] == 3'b101) TrailingOnes <= 2'd2; + else TrailingOnes <= 2'd3; + end + else if (nC_4to8_t1) + begin + if ((heading_one_pos == 4'd1 && + (BitStream_buffer_output[13:11] == 3'b000 || BitStream_buffer_output[13:11] == 3'b010 || + BitStream_buffer_output[13:11] == 3'b100 || BitStream_buffer_output[13:11] == 3'b111)) || + (heading_one_pos == 4'd2 && BitStream_buffer_output[11:10] == 2'b10 ) || + (heading_one_pos == 4'd3 && BitStream_buffer_output[11:9] == 3'b110) || + (heading_one_pos == 4'd4 && BitStream_buffer_output[9:8] == 2'b10 )) + TrailingOnes <= 2'd1; + else if ( + (heading_one_pos == 4'd1 && (BitStream_buffer_output[13:11] == 3'b001 || BitStream_buffer_output[13:11] == 3'b011 || BitStream_buffer_output[13:11] == 3'b110))|| + (heading_one_pos == 4'd2 && BitStream_buffer_output[11:10] == 2'b01) || + (heading_one_pos == 4'd3 && (BitStream_buffer_output[11:9] == 3'b010 || BitStream_buffer_output[11:9] == 3'b101))|| + (heading_one_pos == 4'd4 && BitStream_buffer_output[9:8] == 2'b01)) + TrailingOnes <= 2'd2; + else if ( + (heading_one_pos == 4'd1 && BitStream_buffer_output[13:11] == 3'b101) || + (heading_one_pos == 4'd2 && BitStream_buffer_output[12:10] == 3'b100) || + (heading_one_pos == 4'd3 && BitStream_buffer_output[11:9] == 3'b100) || + (heading_one_pos == 4'd4 && BitStream_buffer_output[9:8] == 2'b00)) + TrailingOnes <= 2'd3; + else + TrailingOnes <= 2'd0; + end + else + begin + if ((heading_one_pos == 4'd5 && BitStream_buffer_output[8:7] == 2'b10) || + (heading_one_pos == 4'd6 && (BitStream_buffer_output[8:7] == 2'b11 || BitStream_buffer_output[7:6] == 2'b00)) || + (heading_one_pos == 4'd7 && BitStream_buffer_output[7:6] == 2'b00)) + TrailingOnes <= 2'd1; + else if ( + (heading_one_pos == 4'd5 && BitStream_buffer_output[8:7] == 2'b01) || + (heading_one_pos == 4'd6 && BitStream_buffer_output[8:6] == 3'b011) || + (heading_one_pos == 4'd7 && BitStream_buffer_output[7:6] == 2'b11) || + (heading_one_pos == 4'd8 && BitStream_buffer_output[6])) + TrailingOnes <= 2'd2; + else if ( + (heading_one_pos == 4'd5 && BitStream_buffer_output[9:7] == 3'b100) || + (heading_one_pos == 4'd6 && BitStream_buffer_output[8:6] == 3'b010) || + (heading_one_pos == 4'd7 && BitStream_buffer_output[7:6] == 2'b10) || + (heading_one_pos == 4'd8 && !BitStream_buffer_output[6])) + TrailingOnes <= 2'd3; + else + TrailingOnes <= 2'd0; + end + end + else if (nC_GE8) + begin + if (BitStream_buffer_output[15:10] == 6'b0 || heading_one_pos == 4'd4) + TrailingOnes <= 2'd0; + else if (heading_one_pos == 4'd5) + TrailingOnes <= 2'd1; + else + TrailingOnes <= BitStream_buffer_output[11:10]; + end + else + TrailingOnes <= TrailingOnes_reg; + + //TotalCoeff + always @ (posedge clk) + if (reset_n == 0) + TotalCoeff_reg <= 0; + else if (cavlc_decoder_state == `NumCoeffTrailingOnes_LUT) + TotalCoeff_reg <= TotalCoeff; + + always @ (nC_0to2 or nC_2to4 or nC_4to8 or nC_n1 or nC_GE8 + or nC_0to2_t0 or nC_0to2_t1 or nC_0to2_t2 or nC_0to2_t3 + or nC_2to4_t0 or nC_2to4_t1 or nC_2to4_t2 or nC_2to4_t3 + or nC_4to8_t0 or nC_4to8_t1 or nC_n1_t0 + or TotalCoeff_reg or heading_one_pos or BitStream_buffer_output) + if (nC_0to2) + begin + if (nC_0to2_t0) + TotalCoeff <= {3'b0,heading_one_pos[1:0]}; + else if (nC_0to2_t1) + begin + if (heading_one_pos == 4'd3) + case (BitStream_buffer_output[11:10]) + 2'b00 :TotalCoeff <= 5'd2; + 2'b01 :TotalCoeff <= 5'd1; + default:TotalCoeff <= 5'd3; + endcase + else + case (BitStream_buffer_output[10:9]) + 2'b00 :TotalCoeff <= 5'd5; + 2'b01 :TotalCoeff <= 5'd3; + default:TotalCoeff <= 5'd4; + endcase + end + else if (nC_0to2_t2) + begin + if (heading_one_pos == 4'd5) + case (BitStream_buffer_output[9:8]) + 2'b00:TotalCoeff <= 5'd6; + 2'b01:TotalCoeff <= 5'd4; + 2'b10:TotalCoeff <= 5'd3; + 2'b11:TotalCoeff <= 5'd2; + endcase + else if (heading_one_pos == 4'd6) + case (BitStream_buffer_output[8:7]) + 2'b00:TotalCoeff <= 5'd7; + 2'b01:TotalCoeff <= 5'd5; + 2'b10:TotalCoeff <= 5'd4; + 2'b11:TotalCoeff <= 5'd3; + endcase + else if (heading_one_pos == 4'd7) + case (BitStream_buffer_output[7:6]) + 2'b00:TotalCoeff <= 5'd8; + 2'b01:TotalCoeff <= 5'd6; + 2'b10:TotalCoeff <= 5'd5; + 2'b11:TotalCoeff <= 5'd4; + endcase + else + case (BitStream_buffer_output[6:5]) + 2'b00:TotalCoeff <= 5'd9; + 2'b01:TotalCoeff <= 5'd7; + 2'b10:TotalCoeff <= 5'd6; + 2'b11:TotalCoeff <= 5'd5; + endcase + end + else if (nC_0to2_t3) + begin + if (heading_one_pos == 4'd9) + case (BitStream_buffer_output[5:3]) + 3'b001 :TotalCoeff <= 5'd9; + 3'b011,3'b110:TotalCoeff <= 5'd7; + 3'b100 :TotalCoeff <= 5'd10; + 3'b111 :TotalCoeff <= 5'd6; + default :TotalCoeff <= 5'd8; + endcase + else + case (BitStream_buffer_output[4:2]) + 3'b000 :TotalCoeff <= 5'd12; + 3'b001,3'b100:TotalCoeff <= 5'd11; + 3'b110,3'b111:TotalCoeff <= 5'd9; + default :TotalCoeff <= 5'd10; + endcase + end + else + begin + if (heading_one_pos == 4'd11) + case (BitStream_buffer_output[3:1]) + 3'b000 :TotalCoeff <= 5'd14; + 3'b001,3'b100:TotalCoeff <= 5'd13; + 3'b110,3'b111:TotalCoeff <= 5'd11; + default :TotalCoeff <= 5'd12; + endcase + else if (heading_one_pos == 4'd12) + case (BitStream_buffer_output[2:0]) + 3'b000 :TotalCoeff <= 5'd16; + 3'b011,3'b101,3'b110:TotalCoeff <= 5'd14; + 3'b111 :TotalCoeff <= 5'd13; + default :TotalCoeff <= 5'd15; + endcase + else if (heading_one_pos == 4'd13) + TotalCoeff <= (BitStream_buffer_output[1:0] == 2'b11)? 5'd15:5'd16; + else + TotalCoeff <= 5'd13; + end + end + else if (nC_2to4) + begin + if (nC_2to4_t0) + begin + if (heading_one_pos == 4'd0) + TotalCoeff <= {4'b0,~BitStream_buffer_output[14]}; + else + case (BitStream_buffer_output[13:12]) + 2'b00 :TotalCoeff <= 5'd4; + 2'b01 :TotalCoeff <= 5'd3; + default:TotalCoeff <= 5'd2; + endcase + end + else if (nC_2to4_t1) + begin + if (heading_one_pos == 4'd2) + case (BitStream_buffer_output[12:11]) + 2'b00:TotalCoeff <= (BitStream_buffer_output[10])? 5'd3:5'd6; + 2'b01:TotalCoeff <= (BitStream_buffer_output[10])? 5'd1:5'd3; + 2'b10:TotalCoeff <= 5'd5; + 2'b11:TotalCoeff <= 5'd2; + endcase + else + case (BitStream_buffer_output[11:10]) + 2'b00 :TotalCoeff <= 5'd7; + 2'b11 :TotalCoeff <= 5'd2; + default:TotalCoeff <= 5'd4; + endcase + end + else if (nC_2to4_t2) + begin + if (heading_one_pos == 4'd4) + case (BitStream_buffer_output[10:9]) + 2'b00 :TotalCoeff <= 5'd8; + 2'b11 :TotalCoeff <= 5'd3; + default:TotalCoeff <= 5'd5; + endcase + else if (heading_one_pos == 4'd5) + case (BitStream_buffer_output[9:8]) + 2'b00 :TotalCoeff <= 5'd5; + 2'b11 :TotalCoeff <= 5'd4; + default:TotalCoeff <= 5'd6; + endcase + else + case (BitStream_buffer_output[8:7]) + 2'b00 :TotalCoeff <= 5'd9; + 2'b11 :TotalCoeff <= 5'd6; + default:TotalCoeff <= 5'd7; + endcase + end + else if (nC_2to4_t3) + begin + if (heading_one_pos == 4'd7) + case (BitStream_buffer_output[7:5]) + 3'b000 :TotalCoeff <= 5'd11; + 3'b001,3'b010:TotalCoeff <= 5'd9; + 3'b100 :TotalCoeff <= 5'd10; + 3'b111 :TotalCoeff <= 5'd7; + default :TotalCoeff <= 5'd8; + endcase + else + case (BitStream_buffer_output[6:4]) + 3'b000,3'b001,3'b010:TotalCoeff <= 5'd11; + 3'b100 :TotalCoeff <= 5'd12; + 3'b111 :TotalCoeff <= 5'd9; + default :TotalCoeff <= 5'd10; + endcase + end + else + begin + if (heading_one_pos == 4'd9) + case (BitStream_buffer_output[5:3]) + 3'b000 :TotalCoeff <= 5'd14; + 3'b101,3'b110,3'b111:TotalCoeff <= 5'd12; + default :TotalCoeff <= 5'd13; + endcase + else if (heading_one_pos == 4'd10) + TotalCoeff <= (BitStream_buffer_output[4:2] == 3'b0 || BitStream_buffer_output[4:2] == 3'b001 || BitStream_buffer_output[4:2] == 3'b010)? 5'd15:5'd14; + else if (heading_one_pos == 4'd11) + TotalCoeff <= 5'd16; + else + TotalCoeff <= 5'd15; + end + end + else if (nC_n1) + begin + if (nC_n1_t0) + begin + if (BitStream_buffer_output[15]) TotalCoeff <= 5'd1; + else if (BitStream_buffer_output[14]) TotalCoeff <= 5'd0; + else TotalCoeff <= 5'd2; + end + else + begin + if (heading_one_pos == 4'd3) + case (BitStream_buffer_output[11:10]) + 2'b01 :TotalCoeff <= 5'd3; + 2'b11 :TotalCoeff <= 5'd1; + default:TotalCoeff <= 5'd2; + endcase + else if (heading_one_pos == 4'd4) + TotalCoeff <= (BitStream_buffer_output[10])? 5'd3:5'd4; + else if (heading_one_pos == 4'd5) + TotalCoeff <= 5'd3; + else + TotalCoeff <= 5'd4; + end + end + else if (nC_4to8) + begin + if (nC_4to8_t0) + TotalCoeff <= {2'b0,~BitStream_buffer_output[14:12]}; + else if (nC_4to8_t1) + begin + if (heading_one_pos == 4'd1) + case (BitStream_buffer_output[13:11]) + 3'b000,3'b001:TotalCoeff <= 5'd5; + 3'b010,3'b011:TotalCoeff <= 5'd4; + 3'b101 :TotalCoeff <= 5'd8; + 3'b111 :TotalCoeff <= 5'd2; + default :TotalCoeff <= 5'd3; + endcase + else if (heading_one_pos == 4'd2) + case (BitStream_buffer_output[12:10]) + 3'b000 :TotalCoeff <= 5'd3; + 3'b001,3'b010:TotalCoeff <= 5'd7; + 3'b011 :TotalCoeff <= 5'd2; + 3'b100 :TotalCoeff <= 5'd9; + 3'b111 :TotalCoeff <= 5'd1; + default :TotalCoeff <= 5'd6; + endcase + else if (heading_one_pos == 4'd3) + case (BitStream_buffer_output[11:9]) + 3'b000 :TotalCoeff <= 5'd7; + 3'b001 :TotalCoeff <= 5'd6; + 3'b010 :TotalCoeff <= 5'd9; + 3'b011 :TotalCoeff <= 5'd5; + 3'b100 :TotalCoeff <= 5'd10; + 3'b111 :TotalCoeff <= 5'd4; + default:TotalCoeff <= 5'd8; + endcase + else + case (BitStream_buffer_output[10:8]) + 3'b000 :TotalCoeff <= 5'd12; + 3'b001,3'b100:TotalCoeff <= 5'd11; + 3'b010,3'b101:TotalCoeff <= 5'd10; + 3'b111 :TotalCoeff <= 5'd8; + default :TotalCoeff <= 5'd9; + endcase + end + else + begin + if (heading_one_pos == 4'd5) + case (BitStream_buffer_output[9:7]) + 3'b001,3'b100 :TotalCoeff <= 5'd13; + 3'b011,3'b110 :TotalCoeff <= 5'd11; + 3'b111 :TotalCoeff <= 5'd10; + default :TotalCoeff <= 5'd12; + endcase + else if (heading_one_pos == 4'd6) + case (BitStream_buffer_output[8:6]) + 3'b000 :TotalCoeff <= 5'd15; + 3'b101,3'b110,3'b111:TotalCoeff <= 5'd13; + default :TotalCoeff <= 5'd14; + endcase + else if (heading_one_pos == 4'd7) + TotalCoeff <= (BitStream_buffer_output[7:6] == 2'b00)? 5'd16:5'd15; + else + TotalCoeff <= 5'd16; + end + end + else if (nC_GE8) + begin + if (heading_one_pos == 4'd4) + TotalCoeff <= 5'd0; + else + TotalCoeff <= BitStream_buffer_output[15:12] + 1; + end + else + TotalCoeff <= TotalCoeff_reg; +endmodule \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/QP_decoding.v b/demo_chip_rtl/rtl/nova/tags/Start/src/QP_decoding.v new file mode 100644 index 0000000..64354ff --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/QP_decoding.v @@ -0,0 +1,70 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : QP_decoding.v +// Generated : June 7, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// QPy:the luma quantisation parameter +// QPi:the intermediate quantisation parameter derived from QPy +// QPc:the chroma quantisation parameter derived from QPi on Table 8-13,Page136 +//------------------------------------------------------------------------------------------------- +// Revise log +// 1. March 21,2006 +// Input signals slice_qp_delta and mb_qp_delta are removed, using +// exp_golomb_decoding_output_5to0 instead since these two signals are latched at clock +// rising edge which is too late for computation. So use exp_golomb_decoding_output_5to0 directly +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module QP_decoding (clk,reset_n,slice_header_state,slice_data_state,pic_init_qp_minus26, + exp_golomb_decoding_output_5to0,chroma_qp_index_offset,QPy,QPc); + input clk,reset_n; + input [3:0] slice_header_state; + input [3:0] slice_data_state; + input [5:0] pic_init_qp_minus26; + input [5:0] exp_golomb_decoding_output_5to0; + input [4:0] chroma_qp_index_offset; + output [5:0] QPy,QPc; + reg [5:0] QPy,QPc; + + always @ (posedge clk) + if (reset_n == 0) + QPy <= 0; + else if (slice_header_state == `slice_qp_delta_s) + QPy <= 26 + pic_init_qp_minus26 + exp_golomb_decoding_output_5to0; + else if (slice_data_state == `mb_qp_delta_s) + QPy <= QPy + exp_golomb_decoding_output_5to0; + + wire [5:0] QPi; + assign QPi = QPy + {1'b0,chroma_qp_index_offset}; + always @ (posedge clk) + if (reset_n == 0) + QPc <= 0; + else + begin + if (QPi < 30) + QPc <= QPi; + else + case (QPi) + 30 :QPc <= 29; + 31 :QPc <= 30; + 32 :QPc <= 31; + 33,34 :QPc <= 32; + 35 :QPc <= 33; + 36,37 :QPc <= 34; + 38,39 :QPc <= 35; + 40,41 :QPc <= 36; + 42,43,44:QPc <= 37; + 45,46,47:QPc <= 38; + default :QPc <= 39; + endcase + end +endmodule + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/bitstream_gclk_gen.v b/demo_chip_rtl/rtl/nova/tags/Start/src/bitstream_gclk_gen.v new file mode 100644 index 0000000..cbf8e35 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/bitstream_gclk_gen.v @@ -0,0 +1,333 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : bitstream_gclk_gen.v +// Generated : Jan 9,2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Gated clock generation module for bitstream controller +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module bitstream_gclk_gen (clk,reset_n,freq_ctrl0,freq_ctrl1,parser_state,nal_unit_state,slice_layer_wo_partitioning_state, + slice_header_state,slice_data_state,seq_parameter_set_state,pic_parameter_set_state,residual_state,cavlc_decoder_state, + mb_num,TotalCoeff,start_code_prefix_found,pc_2to0,deblocking_filter_control_present_flag, + disable_deblocking_filter_idc,end_of_one_residual_block, + Intra4x4PredMode_mbAddrB_cs_n,mvx_mbAddrB_cs_n,mvy_mbAddrB_cs_n,mvx_mbAddrC_cs_n,mvy_mbAddrC_cs_n, + LumaLevel_mbAddrB_cs_n,ChromaLevel_Cb_mbAddrB_cs_n,ChromaLevel_Cr_mbAddrB_cs_n, + trigger_CAVLC,blk4x4_rec_counter,end_of_DCBlk_IQIT,end_of_one_blk4x4_sum,end_of_MB_DEC,disable_DF,bs_dec_counter, + + gclk_parser,gclk_nal,gclk_slice,gclk_sps,gclk_pps, + gclk_slice_header,gclk_slice_data,gclk_residual,gclk_cavlc, + gclk_Intra4x4PredMode_mbAddrB_RF, + gclk_mvx_mbAddrB_RF,gclk_mvy_mbAddrB_RF,gclk_mvx_mbAddrC_RF,gclk_mvy_mbAddrC_RF, + gclk_LumaLevel_mbAddrB_RF,gclk_ChromaLevel_Cb_mbAddrB_RF,gclk_ChromaLevel_Cr_mbAddrB_RF,gclk_bs_dec, + end_of_one_frame); + input clk; + input reset_n; + input freq_ctrl0; + input freq_ctrl1; + input [1:0] parser_state; + input [2:0] nal_unit_state; + input [1:0] slice_layer_wo_partitioning_state; + input [3:0] slice_header_state; + input [3:0] slice_data_state; + input [3:0] seq_parameter_set_state; + input [3:0] pic_parameter_set_state; + input [3:0] residual_state; + input [3:0] cavlc_decoder_state; + input [6:0] mb_num; + input [4:0] TotalCoeff; + input start_code_prefix_found; + input [2:0] pc_2to0; + input deblocking_filter_control_present_flag; + input [1:0] disable_deblocking_filter_idc; + input end_of_one_residual_block; + input Intra4x4PredMode_mbAddrB_cs_n; + input mvx_mbAddrB_cs_n; + input mvy_mbAddrB_cs_n; + input mvx_mbAddrC_cs_n; + input mvy_mbAddrC_cs_n; + input LumaLevel_mbAddrB_cs_n; + input ChromaLevel_Cb_mbAddrB_cs_n; + input ChromaLevel_Cr_mbAddrB_cs_n; + input trigger_CAVLC; + input [4:0] blk4x4_rec_counter; + input end_of_DCBlk_IQIT; + input end_of_one_blk4x4_sum; + input end_of_MB_DEC; + input disable_DF; + input [1:0] bs_dec_counter; + + output gclk_parser; + output gclk_nal; + output gclk_slice; + output gclk_sps; + output gclk_pps; + output gclk_slice_header; + output gclk_slice_data; + output gclk_residual; + output gclk_cavlc; + output gclk_Intra4x4PredMode_mbAddrB_RF; + output gclk_mvx_mbAddrB_RF; + output gclk_mvy_mbAddrB_RF; + output gclk_mvx_mbAddrC_RF; + output gclk_mvy_mbAddrC_RF; + output gclk_LumaLevel_mbAddrB_RF; + output gclk_ChromaLevel_Cb_mbAddrB_RF; + output gclk_ChromaLevel_Cr_mbAddrB_RF; + output gclk_bs_dec; + output end_of_one_frame; + + //Input pin freq_ctrl0 & freq_ctrl1 can be used to adjust frequency after the chip is fabricated + reg [16:0] cycles_per_frame; + always @ (freq_ctrl0 or freq_ctrl1) + case ({freq_ctrl1,freq_ctrl0}) + 2'b00:cycles_per_frame <= `cycles_per_frame0; + 2'b01:cycles_per_frame <= `cycles_per_frame1; + 2'b11:cycles_per_frame <= `cycles_per_frame3; + default:cycles_per_frame <= `cycles_per_frame2; + endcase + + //--------------------------------------------------------------------------------- + // decoding rate control + //--------------------------------------------------------------------------------- + reg [16:0] frame_cycle_counter; + reg end_of_one_frame; + always @ (posedge clk) + if (reset_n == 1'b0) + begin + frame_cycle_counter <= 0; + end_of_one_frame <= 1'b0; + end + else if (parser_state == `start_code_prefix) + begin + frame_cycle_counter <= 0; + end_of_one_frame <= 1'b0; + end + else if (frame_cycle_counter < cycles_per_frame) + begin + frame_cycle_counter <= frame_cycle_counter + 1; + end_of_one_frame <= 1'b0; + end + else + begin + frame_cycle_counter <= 0; + end_of_one_frame <= 1'b1; + end + //PPS and SPS doesn't need rate control,so after PPS/SPS decoding,bitstream parser should continue + //without waiting for "end_of_one_frame" signal when parser_state == rst_parser. + //PPS_SPS_complete is used to identify whether next nal_unit to be decoded is PPS/SPS or normal frame + reg PPS_SPS_complete; + always @ (posedge gclk_slice or negedge reset_n) + if (reset_n == 1'b0) + PPS_SPS_complete <= 1'b0; + else if (slice_layer_wo_partitioning_state == `slice_header) + PPS_SPS_complete <= 1'b1; + + //1.gclk_parser + wire parser_ena; + reg l_parser_ena; + wire gclk_parser; + assign parser_ena = ( + (parser_state == `rst_parser && (!PPS_SPS_complete || (PPS_SPS_complete && end_of_one_frame))) || + (parser_state == `start_code_prefix && start_code_prefix_found == 1'b1) || + (nal_unit_state == `rbsp_trailing_one_bit && pc_2to0 == 3'b000) || + nal_unit_state == `rbsp_trailing_zero_bits)? 1'b1:1'b0; + always @ (clk or parser_ena) + if (!clk) l_parser_ena <= parser_ena; + assign gclk_parser = l_parser_ena & clk; + + //2.gclk_nal + //including rate control for end of one frame + wire nal_ena; + reg l_nal_ena; + wire gclk_nal; + assign nal_ena = (parser_state == `nal_unit && ( + nal_unit_state == `rst_nal_unit || + nal_unit_state == `forbidden_zero_bit_2_nal_unit_type || + (((slice_data_state == `skip_run_duration && end_of_MB_DEC)|| slice_data_state == `mb_num_update) + && mb_num == 98) || + seq_parameter_set_state == `vui_parameter_present_flag_s || + pic_parameter_set_state == `deblocking_filter_control_2_redundant_pic_cnt_present_flag || + nal_unit_state == `rbsp_trailing_one_bit || + nal_unit_state == `rbsp_trailing_zero_bits))? 1'b1:1'b0; + always @ (clk or nal_ena) + if (!clk) l_nal_ena <= nal_ena; + assign gclk_nal = l_nal_ena & clk; + + //3.gclk_slice:for slice_layer_wo_partitioning_state FSM + wire slice_ena; + reg l_slice_ena; + wire gclk_slice; + assign slice_ena = ( + (nal_unit_state == `slice_layer_non_IDR_rbsp || nal_unit_state == `slice_layer_IDR_rbsp) && + (slice_layer_wo_partitioning_state == `rst_slice_layer_wo_partitioning || + (slice_header_state == `slice_qp_delta_s && deblocking_filter_control_present_flag == 1'b0) || + (slice_header_state == `disable_deblocking_filter_idc_s && disable_deblocking_filter_idc == 2'b01) || + slice_header_state == `slice_beta_offset_div2_s || + (((slice_data_state == `skip_run_duration && end_of_MB_DEC) || slice_data_state == `mb_num_update) + && mb_num == 98)))? 1'b1:1'b0; + always @ (clk or slice_ena) + if (!clk) l_slice_ena <= slice_ena; + assign gclk_slice = l_slice_ena & clk; + + //4.gclk_sps + wire sps_ena; + reg l_sps_ena; + wire gclk_sps; + assign sps_ena = (nal_unit_state == `seq_parameter_set_rbsp)? 1'b1:1'b0; + always @ (clk or sps_ena) + if (!clk) l_sps_ena <= sps_ena; + assign gclk_sps = l_sps_ena & clk; + + //5.gclk_pps + wire pps_ena; + reg l_pps_ena; + wire gclk_pps; + + assign pps_ena = (nal_unit_state == `pic_parameter_set_rbsp)? 1'b1:1'b0; + always @ (clk or pps_ena) + if (!clk) l_pps_ena <= pps_ena; + assign gclk_pps = l_pps_ena & clk; + + //6.gclk_slice_header + wire slice_header_ena; + reg l_slice_header_ena; + wire gclk_slice_header; + assign slice_header_ena = (slice_layer_wo_partitioning_state == `slice_header)? 1'b1:1'b0; + always @ (clk or slice_header_ena) + if (!clk) l_slice_header_ena <= slice_header_ena; + assign gclk_slice_header = l_slice_header_ena & clk; + + //7.gclk_slice_data + //including rate control for skipped macroblock:skip_run_duration + //including rate control for normal macroblock:mb_num_update + wire slice_data_ena; + reg l_slice_data_ena; + wire gclk_slice_data; + assign slice_data_ena = (slice_layer_wo_partitioning_state == `slice_data && ( + (slice_data_state != `skip_run_duration && slice_data_state != `residual) || + (slice_data_state == `skip_run_duration && end_of_MB_DEC == 1'b1) || + (slice_data_state == `residual && end_of_MB_DEC == 1'b1)))? 1'b1:1'b0; + always @ (clk or slice_data_ena) + if (!clk) l_slice_data_ena <= slice_data_ena; + assign gclk_slice_data = l_slice_data_ena & clk; + + //8.gclk_residual + wire residual_ena; + reg l_residual_ena; + wire gclk_residual; + + assign residual_ena = (slice_data_state == `residual && + (residual_state == `rst_residual || + + ((residual_state == `Intra16x16DCLevel_s || residual_state == `ChromaDCLevel_Cb_s + || residual_state == `ChromaDCLevel_Cr_s) && + ((end_of_one_residual_block == 1 && TotalCoeff == 0) || end_of_DCBlk_IQIT)) || + + ((residual_state == `Intra16x16ACLevel_s || residual_state == `Intra16x16ACLevel_0_s + || residual_state == `LumaLevel_s || residual_state == `LumaLevel_0_s) + && blk4x4_rec_counter == 15 && end_of_one_blk4x4_sum == 1) || + (residual_state == `ChromaACLevel_Cb_s && blk4x4_rec_counter == 19 && end_of_one_blk4x4_sum == 1) || + (residual_state == `ChromaACLevel_Cr_s && blk4x4_rec_counter == 23 && end_of_one_blk4x4_sum == 1) || + (residual_state == `ChromaACLevel_0_s && blk4x4_rec_counter == 23 && end_of_one_blk4x4_sum == 1)))? 1'b1:1'b0; + + always @ (clk or residual_ena) + if (!clk) l_residual_ena <= residual_ena; + assign gclk_residual = l_residual_ena & clk; + + //9.gclk_cavlc + wire cavlc_ena; + reg l_cavlc_ena; + wire gclk_cavlc; + assign cavlc_ena = (slice_data_state == `residual && (cavlc_decoder_state != `rst_cavlc_decoder || + (cavlc_decoder_state == `rst_cavlc_decoder && trigger_CAVLC)))? 1'b1:1'b0; + + always @ (clk or cavlc_ena) + if (!clk) l_cavlc_ena <= cavlc_ena; + assign gclk_cavlc = l_cavlc_ena & clk; + + //---------------------------------------------------------------------- + //gclk for bitstream controller register file + //---------------------------------------------------------------------- + //1.gclk_Intra4x4PredMode_mbAddrB_RF + reg l_Intra4x4PredMode_mbAddrB_RF_ena; + wire gclk_Intra4x4PredMode_mbAddrB_RF; + always @ (clk or Intra4x4PredMode_mbAddrB_cs_n) + if (!clk) l_Intra4x4PredMode_mbAddrB_RF_ena <= ~Intra4x4PredMode_mbAddrB_cs_n; + assign gclk_Intra4x4PredMode_mbAddrB_RF = clk & l_Intra4x4PredMode_mbAddrB_RF_ena; + + //2.gclk_mvx_mbAddrB_RF + reg l_mvx_mbAddrB_RF_ena; + wire gclk_mvx_mbAddrB_RF; + always @ (clk or mvx_mbAddrB_cs_n) + if (!clk) l_mvx_mbAddrB_RF_ena <= ~mvx_mbAddrB_cs_n; + assign gclk_mvx_mbAddrB_RF = clk & l_mvx_mbAddrB_RF_ena; + + //3.gclk_mvy_mbAddrB_RF + reg l_mvy_mbAddrB_RF_ena; + wire gclk_mvy_mbAddrB_RF; + always @ (clk or mvy_mbAddrB_cs_n) + if (!clk) l_mvy_mbAddrB_RF_ena <= ~mvy_mbAddrB_cs_n; + assign gclk_mvy_mbAddrB_RF = clk & l_mvy_mbAddrB_RF_ena; + + //4.gclk_mvx_mbAddrC_RF + reg l_mvx_mbAddrC_RF_ena; + wire gclk_mvx_mbAddrC_RF; + always @ (clk or mvx_mbAddrC_cs_n) + if (!clk) l_mvx_mbAddrC_RF_ena <= ~mvx_mbAddrC_cs_n; + assign gclk_mvx_mbAddrC_RF = clk & l_mvx_mbAddrC_RF_ena; + + //5.gclk_mvy_mbAddrC_RF + reg l_mvy_mbAddrC_RF_ena; + wire gclk_mvy_mbAddrC_RF; + always @ (clk or mvy_mbAddrC_cs_n) + if (!clk) l_mvy_mbAddrC_RF_ena <= ~mvy_mbAddrC_cs_n; + assign gclk_mvy_mbAddrC_RF = clk & l_mvy_mbAddrC_RF_ena; + //---------------------------------------------------------------------- + //gclk for CAVLC_decoder related regfiles + //---------------------------------------------------------------------- + //1.gclk_LumaLevel_mbAddrB_RF + reg l_LumaLevel_mbAddrB_RF_ena; + wire gclk_LumaLevel_mbAddrB_RF; + always @ (clk or LumaLevel_mbAddrB_cs_n) + if (!clk) l_LumaLevel_mbAddrB_RF_ena <= ~LumaLevel_mbAddrB_cs_n; + assign gclk_LumaLevel_mbAddrB_RF = clk & l_LumaLevel_mbAddrB_RF_ena; + + //2.gclk_ChromaLevel_Cb_mbAddrB_RF + reg l_ChromaLevel_Cb_mbAddrB_RF_ena; + wire gclk_ChromaLevel_Cb_mbAddrB_RF; + always @ (clk or ChromaLevel_Cb_mbAddrB_cs_n) + if (!clk) l_ChromaLevel_Cb_mbAddrB_RF_ena <= ~ChromaLevel_Cb_mbAddrB_cs_n; + assign gclk_ChromaLevel_Cb_mbAddrB_RF = clk & l_ChromaLevel_Cb_mbAddrB_RF_ena; + + //3.gclk_ChromaLevel_Cr_mbAddrB_RF + reg l_ChromaLevel_Cr_mbAddrB_RF_ena; + wire gclk_ChromaLevel_Cr_mbAddrB_RF; + always @ (clk or ChromaLevel_Cr_mbAddrB_cs_n) + if (!clk) l_ChromaLevel_Cr_mbAddrB_RF_ena <= ~ChromaLevel_Cr_mbAddrB_cs_n; + assign gclk_ChromaLevel_Cr_mbAddrB_RF = clk & l_ChromaLevel_Cr_mbAddrB_RF_ena; + + //---------------------------------------------------------------------- + //gclk for boundary strength decoding + //---------------------------------------------------------------------- + wire bs_dec_ena; + reg l_bs_dec_ena; + wire gclk_bs_dec; + + assign bs_dec_ena = ((end_of_MB_DEC == 1'b1 && disable_DF == 1'b0) || bs_dec_counter != 0)? 1'b1:1'b0; + always @ (clk or bs_dec_ena) + if (!clk) l_bs_dec_ena <= bs_dec_ena; + assign gclk_bs_dec = l_bs_dec_ena & clk; + +endmodule + + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/bs_decoding.v b/demo_chip_rtl/rtl/nova/tags/Start/src/bs_decoding.v new file mode 100644 index 0000000..68313c4 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/bs_decoding.v @@ -0,0 +1,906 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : bs_decoding.v +// Generated : Nov 17,2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Deblocking Filter Boundary Strength decoding +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module bs_decoding (clk,reset_n,gclk_bs_dec,gclk_end_of_MB_DEC,end_of_MB_DEC,end_of_one_blk4x4_sum,mb_num_h,mb_num_v, + disable_DF,blk4x4_rec_counter,CodedBlockPatternLuma,mb_type_general,slice_data_state,residual_state, + MBTypeGen_mbAddrA,MBTypeGen_mbAddrB_reg,end_of_one_residual_block,TotalCoeff, + curr_DC_IsZero,Is_skipMB_mv_calc, + mvx_mbAddrA,mvy_mbAddrA,mvx_mbAddrB_dout,mvy_mbAddrB_dout, + mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3,mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3, + + bs_dec_counter,end_of_BS_DEC,mv_mbAddrB_rd_for_DF, + bs_V0,bs_V1,bs_V2,bs_V3,bs_H0,bs_H1,bs_H2,bs_H3 + ); + input clk; + input reset_n; + input gclk_bs_dec; + input gclk_end_of_MB_DEC; + input end_of_MB_DEC; + input end_of_one_blk4x4_sum; + input [3:0] mb_num_h; + input [3:0] mb_num_v; + input [4:0] blk4x4_rec_counter; + input disable_DF; + input [3:0] CodedBlockPatternLuma; + input [3:0] mb_type_general; + input [3:0] slice_data_state; + input [3:0] residual_state; + input [1:0] MBTypeGen_mbAddrA; + input [21:0] MBTypeGen_mbAddrB_reg; + input end_of_one_residual_block; + input [4:0] TotalCoeff; + input curr_DC_IsZero; + input Is_skipMB_mv_calc; + input [31:0] mvx_mbAddrA,mvy_mbAddrA,mvx_mbAddrB_dout,mvy_mbAddrB_dout; + input [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3; + input [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3; + + output [1:0] bs_dec_counter; + output end_of_BS_DEC; + output mv_mbAddrB_rd_for_DF; + output [11:0] bs_V0,bs_V1,bs_V2,bs_V3,bs_H0,bs_H1,bs_H2,bs_H3; + + reg [11:0] bs_V0,bs_V1,bs_V2,bs_V3,bs_H0,bs_H1,bs_H2,bs_H3; + + //------------------------------------------- + //mb_type_general needs to be latched for DF + //------------------------------------------- + reg [3:0] mb_type_general_DF; + always @ (posedge clk) + if (reset_n == 1'b0) + mb_type_general_DF <= 4'b0; + else if (!disable_DF && end_of_one_blk4x4_sum && blk4x4_rec_counter == 5'd22) + mb_type_general_DF <= mb_type_general; + + reg [1:0] MB_inter_size; + always @ (mb_type_general_DF) + if (mb_type_general_DF[3] == 1'b0) + case (mb_type_general_DF[2:0]) + 3'b000,3'b101:MB_inter_size <= `I16x16; + 3'b001 :MB_inter_size <= `I16x8; + 3'b010 :MB_inter_size <= `I8x16; + default :MB_inter_size <= `I8x8; + endcase + else //Although it should be Intra,but we have no other choice + MB_inter_size <= `I8x8; + + reg [1:0] MBTypeGen_mbAddrB; + always @ (mb_num_h or MBTypeGen_mbAddrB_reg) + case (mb_num_h) + 0: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[1:0]; + 1: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[3:2]; + 2: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[5:4]; + 3: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[7:6]; + 4: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[9:8]; + 5: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[11:10]; + 6: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[13:12]; + 7: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[15:14]; + 8: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[17:16]; + 9: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[19:18]; + 10:MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[21:20]; + default:MBTypeGen_mbAddrB <= 0; + endcase + + reg [1:0] bs_dec_counter; + always @ (posedge gclk_bs_dec or negedge reset_n) + if (reset_n == 1'b0) + bs_dec_counter <= 0; + else + bs_dec_counter <= bs_dec_counter - 1; + + assign end_of_BS_DEC = (bs_dec_counter == 2'd1)? 1'b1:1'b0; + + wire mvx_V0_diff_GE4,mvx_V1_diff_GE4,mvx_V2_diff_GE4,mvx_V3_diff_GE4; + wire mvy_V0_diff_GE4,mvy_V1_diff_GE4,mvy_V2_diff_GE4,mvy_V3_diff_GE4; + wire mvx_H0_diff_GE4,mvx_H1_diff_GE4,mvx_H2_diff_GE4,mvx_H3_diff_GE4; + wire mvy_H0_diff_GE4,mvy_H1_diff_GE4,mvy_H2_diff_GE4,mvy_H3_diff_GE4; + + + //-------------------------------------------------------------------- + //If current MB is Inter,derive current MB non-zero coeff information + //No need to do this for P_skip or Intra.No need for chroma,either. + //-------------------------------------------------------------------- + reg [15:0] currMB_coeff;//whether each 4x4blk of current MB has at least one non-zero transform coeff + //currMB_coeff is organized in zig-zag order,according to blk4x4_rec_counter + //= 1'b1:this 4x4blk has at least one non-zero transform coeff + //= 1'b0:this 4x4blk has all 16 zero transform coeff + //only useful for Inter (excluding P_skip) MB + always @ (posedge clk) + if (reset_n == 1'b0) + currMB_coeff <= 16'd0; + else if (!disable_DF) + begin + //need to be reset evey MB + //Since only Inter MB needs currMB_coeff,we can use "coded_block_pattern_s" state as timing slot + if (slice_data_state == `coded_block_pattern_s) + currMB_coeff <= 16'd0; + else if (mb_type_general[3] == 1'b0 && mb_type_general[2:0] != 3'b101) //Inter but not P_skip + case (residual_state) + `Intra16x16ACLevel_s: + if (end_of_one_residual_block) + case (blk4x4_rec_counter[3:0]) + 4'd0 :currMB_coeff[0] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1; + 4'd1 :currMB_coeff[1] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1; + 4'd2 :currMB_coeff[2] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1; + 4'd3 :currMB_coeff[3] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1; + 4'd4 :currMB_coeff[4] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1; + 4'd5 :currMB_coeff[5] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1; + 4'd6 :currMB_coeff[6] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1; + 4'd7 :currMB_coeff[7] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1; + 4'd8 :currMB_coeff[8] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1; + 4'd9 :currMB_coeff[9] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1; + 4'd10:currMB_coeff[10] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1; + 4'd11:currMB_coeff[11] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1; + 4'd12:currMB_coeff[12] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1; + 4'd13:currMB_coeff[13] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1; + 4'd14:currMB_coeff[14] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1; + 4'd15:currMB_coeff[15] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1; + endcase + `Intra16x16ACLevel_0_s: + case (blk4x4_rec_counter[3:0]) + 4'd0:currMB_coeff[0] <= ~curr_DC_IsZero; + 4'd1:currMB_coeff[1] <= ~curr_DC_IsZero; + 4'd2:currMB_coeff[2] <= ~curr_DC_IsZero; + 4'd3:currMB_coeff[3] <= ~curr_DC_IsZero; + 4'd4:currMB_coeff[4] <= ~curr_DC_IsZero; + 4'd5:currMB_coeff[5] <= ~curr_DC_IsZero; + 4'd6:currMB_coeff[6] <= ~curr_DC_IsZero; + 4'd7:currMB_coeff[7] <= ~curr_DC_IsZero; + 4'd8:currMB_coeff[8] <= ~curr_DC_IsZero; + 4'd9:currMB_coeff[9] <= ~curr_DC_IsZero; + 4'd10:currMB_coeff[10] <= ~curr_DC_IsZero; + 4'd11:currMB_coeff[11] <= ~curr_DC_IsZero; + 4'd12:currMB_coeff[12] <= ~curr_DC_IsZero; + 4'd13:currMB_coeff[13] <= ~curr_DC_IsZero; + 4'd14:currMB_coeff[14] <= ~curr_DC_IsZero; + 4'd15:currMB_coeff[15] <= ~curr_DC_IsZero; + endcase + `LumaLevel_s: + case (blk4x4_rec_counter[3:0]) + 4'd0 :if (CodedBlockPatternLuma[0] == 1'b0) currMB_coeff[0] <= 1'b0; + else if (end_of_one_residual_block) currMB_coeff[0] <= (TotalCoeff == 0)? 1'b0:1'b1; + 4'd1 :if (CodedBlockPatternLuma[0] == 1'b0) currMB_coeff[1] <= 1'b0; + else if (end_of_one_residual_block) currMB_coeff[1] <= (TotalCoeff == 0)? 1'b0:1'b1; + 4'd2 :if (CodedBlockPatternLuma[0] == 1'b0) currMB_coeff[2] <= 1'b0; + else if (end_of_one_residual_block) currMB_coeff[2] <= (TotalCoeff == 0)? 1'b0:1'b1; + 4'd3 :if (CodedBlockPatternLuma[0] == 1'b0) currMB_coeff[3] <= 1'b0; + else if (end_of_one_residual_block) currMB_coeff[3] <= (TotalCoeff == 0)? 1'b0:1'b1; + 4'd4 :if (CodedBlockPatternLuma[1] == 1'b0) currMB_coeff[4] <= 1'b0; + else if (end_of_one_residual_block) currMB_coeff[4] <= (TotalCoeff == 0)? 1'b0:1'b1; + 4'd5 :if (CodedBlockPatternLuma[1] == 1'b0) currMB_coeff[5] <= 1'b0; + else if (end_of_one_residual_block) currMB_coeff[5] <= (TotalCoeff == 0)? 1'b0:1'b1; + 4'd6 :if (CodedBlockPatternLuma[1] == 1'b0) currMB_coeff[6] <= 1'b0; + else if (end_of_one_residual_block) currMB_coeff[6] <= (TotalCoeff == 0)? 1'b0:1'b1; + 4'd7 :if (CodedBlockPatternLuma[1] == 1'b0) currMB_coeff[7] <= 1'b0; + else if (end_of_one_residual_block) currMB_coeff[7] <= (TotalCoeff == 0)? 1'b0:1'b1; + 4'd8 :if (CodedBlockPatternLuma[2] == 1'b0) currMB_coeff[8] <= 1'b0; + else if (end_of_one_residual_block) currMB_coeff[8] <= (TotalCoeff == 0)? 1'b0:1'b1; + 4'd9 :if (CodedBlockPatternLuma[2] == 1'b0) currMB_coeff[9] <= 1'b0; + else if (end_of_one_residual_block) currMB_coeff[9] <= (TotalCoeff == 0)? 1'b0:1'b1; + 4'd10:if (CodedBlockPatternLuma[2] == 1'b0) currMB_coeff[10] <= 1'b0; + else if (end_of_one_residual_block) currMB_coeff[10] <= (TotalCoeff == 0)? 1'b0:1'b1; + 4'd11:if (CodedBlockPatternLuma[2] == 1'b0) currMB_coeff[11] <= 1'b0; + else if (end_of_one_residual_block) currMB_coeff[11] <= (TotalCoeff == 0)? 1'b0:1'b1; + 4'd12:if (CodedBlockPatternLuma[3] == 1'b0) currMB_coeff[12] <= 1'b0; + else if (end_of_one_residual_block) currMB_coeff[12] <= (TotalCoeff == 0)? 1'b0:1'b1; + 4'd13:if (CodedBlockPatternLuma[3] == 1'b0) currMB_coeff[13] <= 1'b0; + else if (end_of_one_residual_block) currMB_coeff[13] <= (TotalCoeff == 0)? 1'b0:1'b1; + 4'd14:if (CodedBlockPatternLuma[3] == 1'b0) currMB_coeff[14] <= 1'b0; + else if (end_of_one_residual_block) currMB_coeff[14] <= (TotalCoeff == 0)? 1'b0:1'b1; + 4'd15:if (CodedBlockPatternLuma[3] == 1'b0) currMB_coeff[15] <= 1'b0; + else if (end_of_one_residual_block) currMB_coeff[15] <= (TotalCoeff == 0)? 1'b0:1'b1; + endcase + `LumaLevel_0_s:currMB_coeff <= 16'd0; + endcase + end + + //whether each 4x4blk of MB at mbAddrB has at least one non-zero transform coeff + reg [43:0] mbAddrB_coeff_reg; + always @ (posedge gclk_end_of_MB_DEC or negedge reset_n) + if (reset_n == 1'b0) + mbAddrB_coeff_reg <= 44'd0; + else if (!disable_DF && mb_type_general[3] == 1'b0 && mb_type_general[2:0] != 3'b101 && mb_num_v != 8) //Inter but not P_skip + case (mb_num_h) + 4'd0 :mbAddrB_coeff_reg[3:0] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]}; + 4'd1 :mbAddrB_coeff_reg[7:4] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]}; + 4'd2 :mbAddrB_coeff_reg[11:8] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]}; + 4'd3 :mbAddrB_coeff_reg[15:12] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]}; + 4'd4 :mbAddrB_coeff_reg[19:16] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]}; + 4'd5 :mbAddrB_coeff_reg[23:20] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]}; + 4'd6 :mbAddrB_coeff_reg[27:24] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]}; + 4'd7 :mbAddrB_coeff_reg[31:28] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]}; + 4'd8 :mbAddrB_coeff_reg[35:32] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]}; + 4'd9 :mbAddrB_coeff_reg[39:36] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]}; + 4'd10:mbAddrB_coeff_reg[43:40] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]}; + endcase + //------------------------------------------------- + //backup mbAddrA coding information to derive bs_V0 + //------------------------------------------------- + reg [3:0] mbAddrA_coeff; + reg [31:0] mbAddrA_mvx; + reg [31:0] mbAddrA_mvy; + always @ (posedge clk) + if (reset_n == 1'b0) + begin + mbAddrA_coeff <= 4'b0; + mbAddrA_mvx <= 32'b0; + mbAddrA_mvy <= 32'b0; + end + else if (!disable_DF && mb_num_h != 0 && + ((mb_type_general == `MB_P_skip && Is_skipMB_mv_calc && MBTypeGen_mbAddrA[1] == 1'b0) //Current MB is P_skip + || (slice_data_state == `mb_type_s && mb_type_general[3] == 1'b0))) //Current MB is Inter + begin + mbAddrA_mvx <= mvx_mbAddrA; mbAddrA_mvy <= mvy_mbAddrA; + //if mbAddrA is Inter (not P_skip),back up non-zero residual coeff information + if (MBTypeGen_mbAddrA[0] == 1'b0) mbAddrA_coeff <= {currMB_coeff[15],currMB_coeff[13],currMB_coeff[7],currMB_coeff[5]}; + end + //------------------------------------------------- + //backup mbAddrB coding information to derive bs_H0 + //------------------------------------------------- + + //1)For P_skip,at "Is_skipMB_mv_calc", no matter DF is enabled or not,mvx_mbAddrB/mvy_mbAddrB should be read to + // derive current motion vector + //2)For Inter other than P_skip, mvx_mbAddrB/mvy_mbAddrB are read at mb_pred or sub_mb_pred state.So we add a new + // signal "mv_mbAddrB_rd_for_DF" at "slice_data_state == `mb_type_s" + assign mv_mbAddrB_rd_for_DF = (!disable_DF && slice_data_state == `mb_type_s && mb_type_general[3] == 1'b0 && mb_num_v != 0); + reg [3:0] mbAddrB_coeff; + reg [31:0] mbAddrB_mvx; + reg [31:0] mbAddrB_mvy; + always @ (posedge clk) + if (reset_n == 1'b0) + begin + mbAddrB_coeff <= 4'b0; + mbAddrB_mvx <= 32'b0; + mbAddrB_mvy <= 32'b0; + end + else if (!disable_DF && mb_num_v != 0 && + ((mb_type_general == `MB_P_skip && Is_skipMB_mv_calc && MBTypeGen_mbAddrB[1] == 1'b0) //Current MB is P_skip + || (slice_data_state == `mb_type_s && mb_type_general[3] == 1'b0))) //Current MB is Inter + begin + mbAddrB_mvx <= mvx_mbAddrB_dout; mbAddrB_mvy <= mvy_mbAddrB_dout; + //if mbAddrB is Inter (not P_skip),back up non-zero residual coeff information + if (MBTypeGen_mbAddrB[0] == 1'b0) + case (mb_num_h) + 4'd0 :mbAddrB_coeff <= mbAddrB_coeff_reg[3:0]; + 4'd1 :mbAddrB_coeff <= mbAddrB_coeff_reg[7:4]; + 4'd2 :mbAddrB_coeff <= mbAddrB_coeff_reg[11:8]; + 4'd3 :mbAddrB_coeff <= mbAddrB_coeff_reg[15:12]; + 4'd4 :mbAddrB_coeff <= mbAddrB_coeff_reg[19:16]; + 4'd5 :mbAddrB_coeff <= mbAddrB_coeff_reg[23:20]; + 4'd6 :mbAddrB_coeff <= mbAddrB_coeff_reg[27:24]; + 4'd7 :mbAddrB_coeff <= mbAddrB_coeff_reg[31:28]; + 4'd8 :mbAddrB_coeff <= mbAddrB_coeff_reg[35:32]; + 4'd9 :mbAddrB_coeff <= mbAddrB_coeff_reg[39:36]; + 4'd10:mbAddrB_coeff <= mbAddrB_coeff_reg[43:40]; + endcase + end + + always @ (posedge gclk_bs_dec or negedge reset_n) + if (reset_n == 1'b0) + begin + bs_V0 <= 0; bs_V1 <= 0; bs_V2 <= 0; bs_V3 <= 0; + bs_H0 <= 0; bs_H1 <= 0; bs_H2 <= 0; bs_H3 <= 0; + end + //----------------------- + //Current MB is P_skip + //----------------------- + else if (mb_type_general_DF == `MB_P_skip) + case (bs_dec_counter) + 2'b00: + begin + //V0 + if (mb_num_h == 0) //edge of frame,bs = 0 + bs_V0 <= 12'b0; + else if (MBTypeGen_mbAddrA[1] == 1'b1) //mbAddrA is Intra,bs = 4 + bs_V0 <= 12'b100100100100; + else if (MBTypeGen_mbAddrA == `MB_addrA_addrB_P_skip) //mbAddrA is P_skip + bs_V0 <= (mvx_V0_diff_GE4 || mvy_V0_diff_GE4)? 12'b001001001001:12'b0; + else //mbAddrA is Inter + begin + bs_V0[2:0] <= (mbAddrA_coeff[0])? 3'd2:(mvx_V0_diff_GE4 || mvy_V0_diff_GE4)? 3'd1:3'd0; + bs_V0[5:3] <= (mbAddrA_coeff[1])? 3'd2:(mvx_V1_diff_GE4 || mvy_V1_diff_GE4)? 3'd1:3'd0; + bs_V0[8:6] <= (mbAddrA_coeff[2])? 3'd2:(mvx_V2_diff_GE4 || mvy_V2_diff_GE4)? 3'd1:3'd0; + bs_V0[11:9] <= (mbAddrA_coeff[3])? 3'd2:(mvx_V3_diff_GE4 || mvy_V3_diff_GE4)? 3'd1:3'd0; + end + //H0 + if (mb_num_v == 0) //edge of frame,bs = 0 + bs_H0 <= 12'b0; + else if (MBTypeGen_mbAddrB[1] == 1'b1) //mbAddrB is Intra,bs=4 + bs_H0 <= 12'b100100100100; + else if (MBTypeGen_mbAddrB == `MB_addrA_addrB_P_skip) //mbAddrB is P_skip + bs_H0 <= (mvx_H0_diff_GE4 || mvy_H0_diff_GE4)? 12'b001001001001:12'b0; + else + begin + bs_H0[2:0] <= (mbAddrB_coeff[0])? 3'd2:(mvx_H0_diff_GE4 || mvy_H0_diff_GE4)? 3'd1:3'd0; + bs_H0[5:3] <= (mbAddrB_coeff[1])? 3'd2:(mvx_H1_diff_GE4 || mvy_H1_diff_GE4)? 3'd1:3'd0; + bs_H0[8:6] <= (mbAddrB_coeff[2])? 3'd2:(mvx_H2_diff_GE4 || mvy_H2_diff_GE4)? 3'd1:3'd0; + bs_H0[11:9] <= (mbAddrB_coeff[3])? 3'd2:(mvx_H3_diff_GE4 || mvy_H3_diff_GE4)? 3'd1:3'd0; + end + end + 2'b11:begin bs_V1 <= 0; bs_H1 <= 0; end + 2'b10:begin bs_V2 <= 0; bs_H2 <= 0; end + 2'b01:begin bs_V3 <= 0; bs_H3 <= 0; end + endcase + //-------------------- + //Current MB is Intra + //----------------------- + else if (mb_type_general_DF[3] == 1'b1) + case (bs_dec_counter) + 2'b00: + begin + bs_V0 <= (mb_num_h == 0)? 12'b0:12'b100100100100; + bs_H0 <= (mb_num_v == 0)? 12'b0:12'b100100100100; + end + 2'b11:begin bs_V1 <= 12'b011011011011; bs_H1 <= 12'b011011011011; end + 2'b10:begin bs_V2 <= 12'b011011011011; bs_H2 <= 12'b011011011011; end + 2'b01:begin bs_V3 <= 12'b011011011011; bs_H3 <= 12'b011011011011; end + endcase + //----------------------- + //Current MB is Inter + //----------------------- + else + case (bs_dec_counter) + 2'b00: //V0,H0 + begin + //V0 + if (mb_num_h == 0) //edge of frame,bs = 0 + bs_V0 <= 12'b0; + else if (MBTypeGen_mbAddrA[1] == 1'b1) //mbAddrA is Intra,bs = 4 + bs_V0 <= 12'b100100100100; + else if (MBTypeGen_mbAddrA == `MB_addrA_addrB_P_skip) //mbAddrA is P_skip + begin + bs_V0[2:0] <= (currMB_coeff[0])? 3'd2:(mvx_V0_diff_GE4 || mvy_V0_diff_GE4)? 3'd1:3'd0; + bs_V0[5:3] <= (currMB_coeff[2])? 3'd2:(mvx_V1_diff_GE4 || mvy_V1_diff_GE4)? 3'd1:3'd0; + bs_V0[8:6] <= (currMB_coeff[8])? 3'd2:(mvx_V2_diff_GE4 || mvy_V2_diff_GE4)? 3'd1:3'd0; + bs_V0[11:9] <= (currMB_coeff[10])? 3'd2:(mvx_V3_diff_GE4 || mvy_V3_diff_GE4)? 3'd1:3'd0; + end + else //mbAddrA is Inter + begin + bs_V0[2:0] <= (mbAddrA_coeff[0] || currMB_coeff[0])? 3'd2:(mvx_V0_diff_GE4 || mvy_V0_diff_GE4)? 3'd1:3'd0; + bs_V0[5:3] <= (mbAddrA_coeff[1] || currMB_coeff[2])? 3'd2:(mvx_V1_diff_GE4 || mvy_V1_diff_GE4)? 3'd1:3'd0; + bs_V0[8:6] <= (mbAddrA_coeff[2] || currMB_coeff[8])? 3'd2:(mvx_V2_diff_GE4 || mvy_V2_diff_GE4)? 3'd1:3'd0; + bs_V0[11:9] <= (mbAddrA_coeff[3] || currMB_coeff[10])? 3'd2:(mvx_V3_diff_GE4 || mvy_V3_diff_GE4)? 3'd1:3'd0; + end + //H0 + if (mb_num_v == 0) //edge of frame,bs = 0 + bs_H0 <= 12'b0; + else if (MBTypeGen_mbAddrB[1] == 1'b1) //mbAddrB is Intra,bs = 4 + bs_H0 <= 12'b100100100100; + else if (MBTypeGen_mbAddrB == `MB_addrA_addrB_P_skip) //mbAddrB is P_skip + begin + bs_H0[2:0] <= (currMB_coeff[0])? 3'd2:(mvx_H0_diff_GE4 || mvy_H0_diff_GE4)? 3'd1:3'd0; + bs_H0[5:3] <= (currMB_coeff[1])? 3'd2:(mvx_H1_diff_GE4 || mvy_H1_diff_GE4)? 3'd1:3'd0; + bs_H0[8:6] <= (currMB_coeff[4])? 3'd2:(mvx_H2_diff_GE4 || mvy_H2_diff_GE4)? 3'd1:3'd0; + bs_H0[11:9] <= (currMB_coeff[5])? 3'd2:(mvx_H3_diff_GE4 || mvy_H3_diff_GE4)? 3'd1:3'd0; + end + else //mbAddrB is Inter + begin + bs_H0[2:0] <= (mbAddrB_coeff[0] || currMB_coeff[0])? 3'd2:(mvx_H0_diff_GE4 || mvy_H0_diff_GE4)? 3'd1:3'd0; + bs_H0[5:3] <= (mbAddrB_coeff[1] || currMB_coeff[1])? 3'd2:(mvx_H1_diff_GE4 || mvy_H1_diff_GE4)? 3'd1:3'd0; + bs_H0[8:6] <= (mbAddrB_coeff[2] || currMB_coeff[4])? 3'd2:(mvx_H2_diff_GE4 || mvy_H2_diff_GE4)? 3'd1:3'd0; + bs_H0[11:9] <= (mbAddrB_coeff[3] || currMB_coeff[5])? 3'd2:(mvx_H3_diff_GE4 || mvy_H3_diff_GE4)? 3'd1:3'd0; + end + end + 2'b11://V1,H1 + begin + bs_V1[2:0] <= (currMB_coeff[0] || currMB_coeff[1])? 3'd2:(MB_inter_size != `I8x8)? + 0:(mvx_V0_diff_GE4 || mvy_V0_diff_GE4)? 3'd1:3'd0; + + bs_V1[5:3] <= (currMB_coeff[2] || currMB_coeff[3])? 3'd2:(MB_inter_size != `I8x8)? + 0:(mvx_V1_diff_GE4 || mvy_V1_diff_GE4)? 3'd1:3'd0; + + bs_V1[8:6] <= (currMB_coeff[8] || currMB_coeff[9])? 3'd2:(MB_inter_size != `I8x8)? + 0:(mvx_V2_diff_GE4 || mvy_V2_diff_GE4)? 3'd1:3'd0; + + bs_V1[11:9] <= (currMB_coeff[10] || currMB_coeff[11])? 3'd2:(MB_inter_size != `I8x8)? + 0:(mvx_V3_diff_GE4 || mvy_V3_diff_GE4)? 3'd1:3'd0; + + bs_H1[2:0] <= (currMB_coeff[0] || currMB_coeff[2])? 3'd2:(MB_inter_size != `I8x8)? + 0:(mvx_H0_diff_GE4 || mvy_H0_diff_GE4)? 3'd1:3'd0; + + bs_H1[5:3] <= (currMB_coeff[1] || currMB_coeff[3])? 3'd2:(MB_inter_size != `I8x8)? + 0:(mvx_H1_diff_GE4 || mvy_H1_diff_GE4)? 3'd1:3'd0; + + bs_H1[8:6] <= (currMB_coeff[4] || currMB_coeff[6])? 3'd2:(MB_inter_size != `I8x8)? + 0:(mvx_H2_diff_GE4 || mvy_H2_diff_GE4)? 3'd1:3'd0; + bs_H1[11:9] <= (currMB_coeff[5] || currMB_coeff[7])? 3'd2:(MB_inter_size != `I8x8)? + 0:(mvx_H3_diff_GE4 || mvy_H3_diff_GE4)? 3'd1:3'd0; + end + 2'b10://V2,H2 + begin + bs_V2[2:0] <= (currMB_coeff[1] || currMB_coeff[4])? 3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? + 0:(mvx_V0_diff_GE4 || mvy_V0_diff_GE4)? 3'd1:3'd0; + + bs_V2[5:3] <= (currMB_coeff[3] || currMB_coeff[6])? 3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? + 0:(mvx_V1_diff_GE4 || mvy_V1_diff_GE4)? 3'd1:3'd0; + + bs_V2[8:6] <= (currMB_coeff[9] || currMB_coeff[12])? 3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? + 0:(mvx_V2_diff_GE4 || mvy_V2_diff_GE4)? 3'd1:3'd0; + + bs_V2[11:9] <= (currMB_coeff[11] || currMB_coeff[14])? 3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? + 0:(mvx_V3_diff_GE4 || mvy_V3_diff_GE4)? 3'd1:3'd0; + + bs_H2[2:0] <= (currMB_coeff[2] || currMB_coeff[8])? 3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? + 0:(mvx_H0_diff_GE4 || mvy_H0_diff_GE4)? 3'd1:3'd0; + + bs_H2[5:3] <= (currMB_coeff[3] || currMB_coeff[9])? 3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? + 0:(mvx_H1_diff_GE4 || mvy_H1_diff_GE4)? 3'd1:3'd0; + + bs_H2[8:6] <= (currMB_coeff[6] || currMB_coeff[12])? 3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? + 0:(mvx_H2_diff_GE4 || mvy_H2_diff_GE4)? 3'd1:3'd0; + + bs_H2[11:9] <= (currMB_coeff[7] || currMB_coeff[13])? 3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? + 0:(mvx_H3_diff_GE4 || mvy_H3_diff_GE4)? 3'd1:3'd0; + end + 2'b01://V3,H3 + begin + bs_V3[2:0] <= (currMB_coeff[4] || currMB_coeff[5])? 3'd2:(MB_inter_size != `I8x8)? + 0:(mvx_V0_diff_GE4 || mvy_V0_diff_GE4)? 3'd1:3'd0; + + bs_V3[5:3] <= (currMB_coeff[6] || currMB_coeff[7])? 3'd2:(MB_inter_size != `I8x8)? + 0:(mvx_V1_diff_GE4 || mvy_V1_diff_GE4)? 3'd1:3'd0; + + bs_V3[8:6] <= (currMB_coeff[12] || currMB_coeff[13])? 3'd2:(MB_inter_size != `I8x8)? + 0:(mvx_V2_diff_GE4 || mvy_V2_diff_GE4)? 3'd1:3'd0; + + bs_V3[11:9] <= (currMB_coeff[14] || currMB_coeff[15])? 3'd2:(MB_inter_size != `I8x8)? + 0:(mvx_V3_diff_GE4 || mvy_V3_diff_GE4)? 3'd1:3'd0; + + bs_H3[2:0] <= (currMB_coeff[8] || currMB_coeff[10])? 3'd2:(MB_inter_size != `I8x8)? + 0:(mvx_H0_diff_GE4 || mvy_H0_diff_GE4)? 3'd1:3'd0; + + bs_H3[5:3] <= (currMB_coeff[9] || currMB_coeff[11])? 3'd2:(MB_inter_size != `I8x8)? + 0:(mvx_H1_diff_GE4 || mvy_H1_diff_GE4)? 3'd1:3'd0; + + bs_H3[8:6] <= (currMB_coeff[12] || currMB_coeff[14])? 3'd2:(MB_inter_size != `I8x8)? + 0:(mvx_H2_diff_GE4 || mvy_H2_diff_GE4)? 3'd1:3'd0; + + bs_H3[11:9] <= (currMB_coeff[13] || currMB_coeff[15])? 3'd2:(MB_inter_size != `I8x8)? + 0:(mvx_H3_diff_GE4 || mvy_H3_diff_GE4)? 3'd1:3'd0; + end + endcase + + reg [7:0] mvx_V0_diff_a,mvx_V0_diff_b; + reg [7:0] mvx_V1_diff_a,mvx_V1_diff_b; + reg [7:0] mvx_V2_diff_a,mvx_V2_diff_b; + reg [7:0] mvx_V3_diff_a,mvx_V3_diff_b; + reg [7:0] mvy_V0_diff_a,mvy_V0_diff_b; + reg [7:0] mvy_V1_diff_a,mvy_V1_diff_b; + reg [7:0] mvy_V2_diff_a,mvy_V2_diff_b; + reg [7:0] mvy_V3_diff_a,mvy_V3_diff_b; + + reg [7:0] mvx_H0_diff_a,mvx_H0_diff_b; + reg [7:0] mvx_H1_diff_a,mvx_H1_diff_b; + reg [7:0] mvx_H2_diff_a,mvx_H2_diff_b; + reg [7:0] mvx_H3_diff_a,mvx_H3_diff_b; + reg [7:0] mvy_H0_diff_a,mvy_H0_diff_b; + reg [7:0] mvy_H1_diff_a,mvy_H1_diff_b; + reg [7:0] mvy_H2_diff_a,mvy_H2_diff_b; + reg [7:0] mvy_H3_diff_a,mvy_H3_diff_b; + + mv_diff_GE4 mvx_V0_diff (.mv_a(mvx_V0_diff_a),.mv_b(mvx_V0_diff_b),.diff_GE4(mvx_V0_diff_GE4)); + mv_diff_GE4 mvx_V1_diff (.mv_a(mvx_V1_diff_a),.mv_b(mvx_V1_diff_b),.diff_GE4(mvx_V1_diff_GE4)); + mv_diff_GE4 mvx_V2_diff (.mv_a(mvx_V2_diff_a),.mv_b(mvx_V2_diff_b),.diff_GE4(mvx_V2_diff_GE4)); + mv_diff_GE4 mvx_V3_diff (.mv_a(mvx_V3_diff_a),.mv_b(mvx_V3_diff_b),.diff_GE4(mvx_V3_diff_GE4)); + mv_diff_GE4 mvy_V0_diff (.mv_a(mvy_V0_diff_a),.mv_b(mvy_V0_diff_b),.diff_GE4(mvy_V0_diff_GE4)); + mv_diff_GE4 mvy_V1_diff (.mv_a(mvy_V1_diff_a),.mv_b(mvy_V1_diff_b),.diff_GE4(mvy_V1_diff_GE4)); + mv_diff_GE4 mvy_V2_diff (.mv_a(mvy_V2_diff_a),.mv_b(mvy_V2_diff_b),.diff_GE4(mvy_V2_diff_GE4)); + mv_diff_GE4 mvy_V3_diff (.mv_a(mvy_V3_diff_a),.mv_b(mvy_V3_diff_b),.diff_GE4(mvy_V3_diff_GE4)); + + mv_diff_GE4 mvx_H0_diff (.mv_a(mvx_H0_diff_a),.mv_b(mvx_H0_diff_b),.diff_GE4(mvx_H0_diff_GE4)); + mv_diff_GE4 mvx_H1_diff (.mv_a(mvx_H1_diff_a),.mv_b(mvx_H1_diff_b),.diff_GE4(mvx_H1_diff_GE4)); + mv_diff_GE4 mvx_H2_diff (.mv_a(mvx_H2_diff_a),.mv_b(mvx_H2_diff_b),.diff_GE4(mvx_H2_diff_GE4)); + mv_diff_GE4 mvx_H3_diff (.mv_a(mvx_H3_diff_a),.mv_b(mvx_H3_diff_b),.diff_GE4(mvx_H3_diff_GE4)); + mv_diff_GE4 mvy_H0_diff (.mv_a(mvy_H0_diff_a),.mv_b(mvy_H0_diff_b),.diff_GE4(mvy_H0_diff_GE4)); + mv_diff_GE4 mvy_H1_diff (.mv_a(mvy_H1_diff_a),.mv_b(mvy_H1_diff_b),.diff_GE4(mvy_H1_diff_GE4)); + mv_diff_GE4 mvy_H2_diff (.mv_a(mvy_H2_diff_a),.mv_b(mvy_H2_diff_b),.diff_GE4(mvy_H2_diff_GE4)); + mv_diff_GE4 mvy_H3_diff (.mv_a(mvy_H3_diff_a),.mv_b(mvy_H3_diff_b),.diff_GE4(mvy_H3_diff_GE4)); + + always @ (end_of_MB_DEC or disable_DF or bs_dec_counter or mb_type_general_DF + or mb_num_h or MB_inter_size or MBTypeGen_mbAddrA + or mbAddrA_mvx or mvx_CurrMb0 or mvx_CurrMb1 or mvx_CurrMb2 or mvx_CurrMb3 + or mbAddrA_mvy or mvy_CurrMb0 or mvy_CurrMb1 or mvy_CurrMb2 or mvy_CurrMb3) + if ((end_of_MB_DEC && disable_DF == 1'b0) || bs_dec_counter != 0) + begin + //----------------------- + //Current MB is P_skip + //----------------------- + if (mb_type_general_DF == `MB_P_skip && bs_dec_counter == 2'b00)//V0 + begin + if (mb_num_h != 0 && MBTypeGen_mbAddrA == `MB_addrA_addrB_P_skip) //mbAddrA is P_skip + begin + mvx_V0_diff_a <= mbAddrA_mvx[7:0]; mvx_V0_diff_b <= mvx_CurrMb0[7:0]; + mvx_V1_diff_a <= 0; mvx_V1_diff_b <= 0; + mvx_V2_diff_a <= 0; mvx_V2_diff_b <= 0; + mvx_V3_diff_a <= 0; mvx_V3_diff_b <= 0; + mvy_V0_diff_a <= mbAddrA_mvy[7:0]; mvy_V0_diff_b <= mvy_CurrMb0[7:0]; + mvy_V1_diff_a <= 0; mvy_V1_diff_b <= 0; + mvy_V2_diff_a <= 0; mvy_V2_diff_b <= 0; + mvy_V3_diff_a <= 0; mvy_V3_diff_b <= 0; + end + else if (mb_num_h != 0 && MBTypeGen_mbAddrA == `MB_addrA_addrB_Inter) //mbAddrA is Inter + begin + mvx_V0_diff_a <= mbAddrA_mvx[7:0]; mvx_V0_diff_b <= mvx_CurrMb0[7:0]; + mvx_V1_diff_a <= mbAddrA_mvx[15:8]; mvx_V1_diff_b <= mvx_CurrMb0[7:0]; + mvx_V2_diff_a <= mbAddrA_mvx[23:16];mvx_V2_diff_b <= mvx_CurrMb0[7:0]; + mvx_V3_diff_a <= mbAddrA_mvx[31:24];mvx_V3_diff_b <= mvx_CurrMb0[7:0]; + mvy_V0_diff_a <= mbAddrA_mvy[7:0]; mvy_V0_diff_b <= mvy_CurrMb0[7:0]; + mvy_V1_diff_a <= mbAddrA_mvy[15:8]; mvy_V1_diff_b <= mvy_CurrMb0[7:0]; + mvy_V2_diff_a <= mbAddrA_mvy[23:16];mvy_V2_diff_b <= mvy_CurrMb0[7:0]; + mvy_V3_diff_a <= mbAddrA_mvy[31:24];mvy_V3_diff_b <= mvy_CurrMb0[7:0]; + end + else + begin + mvx_V0_diff_a <= 0; mvx_V0_diff_b <= 0; + mvx_V1_diff_a <= 0; mvx_V1_diff_b <= 0; + mvx_V2_diff_a <= 0; mvx_V2_diff_b <= 0; + mvx_V3_diff_a <= 0; mvx_V3_diff_b <= 0; + mvy_V0_diff_a <= 0; mvy_V0_diff_b <= 0; + mvy_V1_diff_a <= 0; mvy_V1_diff_b <= 0; + mvy_V2_diff_a <= 0; mvy_V2_diff_b <= 0; + mvy_V3_diff_a <= 0; mvy_V3_diff_b <= 0; + end + end + //----------------------- + //Current MB is Inter + //----------------------- + else if (mb_type_general_DF[3] == 1'b0) + case (bs_dec_counter) + 2'b00: //V0 + if (mb_num_h != 0 && (MBTypeGen_mbAddrA[1] == 1'b0)) //mbAddrA is P_skip or Inter + begin + mvx_V0_diff_a <= mbAddrA_mvx[7:0]; mvx_V0_diff_b <= mvx_CurrMb0[7:0]; + + mvx_V1_diff_a <= mbAddrA_mvx[15:8]; + mvx_V1_diff_b <= (MB_inter_size == `I16x16)? mvx_CurrMb0[7:0]:mvx_CurrMb0[23:16]; + + mvx_V2_diff_a <= mbAddrA_mvx[23:16]; + mvx_V2_diff_b <= (MB_inter_size == `I16x16)? mvx_CurrMb0[7:0]:mvx_CurrMb2[7:0]; + + mvx_V3_diff_a <= mbAddrA_mvx[31:24]; + mvx_V3_diff_b <= (MB_inter_size == `I16x16)? mvx_CurrMb0[7:0]:mvx_CurrMb2[23:16]; + + mvy_V0_diff_a <= mbAddrA_mvy[7:0]; mvy_V0_diff_b <= mvy_CurrMb0[7:0]; + + mvy_V1_diff_a <= mbAddrA_mvy[15:8]; + mvy_V1_diff_b <= (MB_inter_size == `I16x16)? mvy_CurrMb0[7:0]:mvy_CurrMb0[23:16]; + + mvy_V2_diff_a <= mbAddrA_mvy[23:16]; + mvy_V2_diff_b <= (MB_inter_size == `I16x16)? mvy_CurrMb0[7:0]:mvy_CurrMb2[7:0]; + + mvy_V3_diff_a <= mbAddrA_mvy[31:24]; + mvy_V3_diff_b <= (MB_inter_size == `I16x16)? mvy_CurrMb0[7:0]:mvy_CurrMb2[23:16]; + end + else + begin + mvx_V0_diff_a <= 0; mvx_V0_diff_b <= 0; + mvx_V1_diff_a <= 0; mvx_V1_diff_b <= 0; + mvx_V2_diff_a <= 0; mvx_V2_diff_b <= 0; + mvx_V3_diff_a <= 0; mvx_V3_diff_b <= 0; + mvy_V0_diff_a <= 0; mvy_V0_diff_b <= 0; + mvy_V1_diff_a <= 0; mvy_V1_diff_b <= 0; + mvy_V2_diff_a <= 0; mvy_V2_diff_b <= 0; + mvy_V3_diff_a <= 0; mvy_V3_diff_b <= 0; + end + 2'b11: //V1 + begin + mvx_V0_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb0[7:0]; + mvx_V0_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb0[15:8]; + mvx_V1_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb0[23:16]; + mvx_V1_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb0[31:24]; + mvx_V2_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb2[7:0]; + mvx_V2_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb2[15:8]; + mvx_V3_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb2[23:16]; + mvx_V3_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb2[31:24]; + + mvy_V0_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb0[7:0]; + mvy_V0_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb0[15:8]; + mvy_V1_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb0[23:16]; + mvy_V1_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb0[31:24]; + mvy_V2_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb2[7:0]; + mvy_V2_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb2[15:8]; + mvy_V3_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb2[23:16]; + mvy_V3_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb2[31:24]; + end + 2'b10: //V2 + begin + mvx_V0_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvx_CurrMb0[15:8]; + mvx_V0_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvx_CurrMb1[7:0]; + mvx_V1_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvx_CurrMb0[31:24]; + mvx_V1_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvx_CurrMb1[23:16]; + mvx_V2_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvx_CurrMb2[15:8]; + mvx_V2_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvx_CurrMb3[7:0]; + mvx_V3_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvx_CurrMb2[31:24]; + mvx_V3_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvx_CurrMb3[23:16]; + mvy_V0_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvy_CurrMb0[15:8]; + mvy_V0_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvy_CurrMb1[7:0]; + mvy_V1_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvy_CurrMb0[31:24]; + mvy_V1_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvy_CurrMb1[23:16]; + mvy_V2_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvy_CurrMb2[15:8]; + mvy_V2_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvy_CurrMb3[7:0]; + mvy_V3_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvy_CurrMb2[31:24]; + mvy_V3_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvy_CurrMb3[23:16]; + end + 2'b01: //V3 + begin + mvx_V0_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb1[7:0]; + mvx_V0_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb1[15:8]; + mvx_V1_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb1[23:16]; + mvx_V1_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb1[31:24]; + mvx_V2_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb3[7:0]; + mvx_V2_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb3[15:8]; + mvx_V3_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb3[23:16]; + mvx_V3_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb3[31:24]; + + mvy_V0_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb1[7:0]; + mvy_V0_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb1[15:8]; + mvy_V1_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb1[23:16]; + mvy_V1_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb1[31:24]; + mvy_V2_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb3[7:0]; + mvy_V2_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb3[15:8]; + mvy_V3_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb3[23:16]; + mvy_V3_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb3[31:24]; + end + endcase + else + begin + mvx_V0_diff_a <= 0; mvx_V0_diff_b <= 0; + mvx_V1_diff_a <= 0; mvx_V1_diff_b <= 0; + mvx_V2_diff_a <= 0; mvx_V2_diff_b <= 0; + mvx_V3_diff_a <= 0; mvx_V3_diff_b <= 0; + mvy_V0_diff_a <= 0; mvy_V0_diff_b <= 0; + mvy_V1_diff_a <= 0; mvy_V1_diff_b <= 0; + mvy_V2_diff_a <= 0; mvy_V2_diff_b <= 0; + mvy_V3_diff_a <= 0; mvy_V3_diff_b <= 0; + end + end + else + begin + mvx_V0_diff_a <= 0; mvx_V0_diff_b <= 0; + mvx_V1_diff_a <= 0; mvx_V1_diff_b <= 0; + mvx_V2_diff_a <= 0; mvx_V2_diff_b <= 0; + mvx_V3_diff_a <= 0; mvx_V3_diff_b <= 0; + mvy_V0_diff_a <= 0; mvy_V0_diff_b <= 0; + mvy_V1_diff_a <= 0; mvy_V1_diff_b <= 0; + mvy_V2_diff_a <= 0; mvy_V2_diff_b <= 0; + mvy_V3_diff_a <= 0; mvy_V3_diff_b <= 0; + end + + + always @ (end_of_MB_DEC or disable_DF or bs_dec_counter or mb_type_general_DF + or mb_num_v or MBTypeGen_mbAddrB or MB_inter_size + or mbAddrB_mvx or mvx_CurrMb0 or mvx_CurrMb1 or mvx_CurrMb2 or mvx_CurrMb3 + or mbAddrB_mvy or mvy_CurrMb0 or mvy_CurrMb1 or mvy_CurrMb2 or mvy_CurrMb3) + if ((end_of_MB_DEC && disable_DF == 1'b0) || bs_dec_counter != 0) + begin + //----------------------- + //Current MB is P_skip + //----------------------- + if (mb_type_general_DF == `MB_P_skip && bs_dec_counter == 2'b00) //H0 + begin + if (mb_num_v != 0 && MBTypeGen_mbAddrB == `MB_addrA_addrB_P_skip) //mbAddrB is P_skip + begin + mvx_H0_diff_a <= mbAddrB_mvx[31:24]; mvx_H0_diff_b <= mvx_CurrMb0[7:0]; + mvx_H1_diff_a <= 0; mvx_H1_diff_b <= 0; + mvx_H2_diff_a <= 0; mvx_H2_diff_b <= 0; + mvx_H3_diff_a <= 0; mvx_H3_diff_b <= 0; + mvy_H0_diff_a <= mbAddrB_mvy[31:24]; mvy_H0_diff_b <= mvy_CurrMb0[7:0]; + mvy_H1_diff_a <= 0; mvy_H1_diff_b <= 0; + mvy_H2_diff_a <= 0; mvy_H2_diff_b <= 0; + mvy_H3_diff_a <= 0; mvy_H3_diff_b <= 0; + end + else if (mb_num_v != 0 && MBTypeGen_mbAddrB == 2'b00) //mbAddrB is Inter + begin + mvx_H0_diff_a <= mbAddrB_mvx[31:24]; mvx_H0_diff_b <= mvx_CurrMb0[7:0]; + mvx_H1_diff_a <= mbAddrB_mvx[23:16]; mvx_H1_diff_b <= mvx_CurrMb0[7:0]; + mvx_H2_diff_a <= mbAddrB_mvx[15:8]; mvx_H2_diff_b <= mvx_CurrMb0[7:0]; + mvx_H3_diff_a <= mbAddrB_mvx[7:0]; mvx_H3_diff_b <= mvx_CurrMb0[7:0]; + mvy_H0_diff_a <= mbAddrB_mvy[31:24]; mvy_H0_diff_b <= mvy_CurrMb0[7:0]; + mvy_H1_diff_a <= mbAddrB_mvy[23:16]; mvy_H1_diff_b <= mvy_CurrMb0[7:0]; + mvy_H2_diff_a <= mbAddrB_mvy[15:8]; mvy_H2_diff_b <= mvy_CurrMb0[7:0]; + mvy_H3_diff_a <= mbAddrB_mvy[7:0]; mvy_H3_diff_b <= mvy_CurrMb0[7:0]; + end + else + begin + mvx_H0_diff_a <= 0; mvx_H0_diff_b <= 0; + mvx_H1_diff_a <= 0; mvx_H1_diff_b <= 0; + mvx_H2_diff_a <= 0; mvx_H2_diff_b <= 0; + mvx_H3_diff_a <= 0; mvx_H3_diff_b <= 0; + mvy_H0_diff_a <= 0; mvy_H0_diff_b <= 0; + mvy_H1_diff_a <= 0; mvy_H1_diff_b <= 0; + mvy_H2_diff_a <= 0; mvy_H2_diff_b <= 0; + mvy_H3_diff_a <= 0; mvy_H3_diff_b <= 0; + end + end + //----------------------- + //Current MB is Inter + //----------------------- + else if (mb_type_general_DF[3] == 1'b0) + case (bs_dec_counter) + 2'b00: //H0 + if (mb_num_v != 0 && (MBTypeGen_mbAddrB[1] == 1'b0))//mbAddrB is P_skip or Inter + begin + mvx_H0_diff_a <= mbAddrB_mvx[31:24]; mvx_H0_diff_b <= mvx_CurrMb0[7:0]; + + mvx_H1_diff_a <= mbAddrB_mvx[23:16]; + mvx_H1_diff_b <= (MB_inter_size == `I16x16)? mvx_CurrMb0[7:0]:mvx_CurrMb0[15:8]; + + mvx_H2_diff_a <= mbAddrB_mvx[15:8]; + mvx_H2_diff_b <= (MB_inter_size == `I16x16)? mvx_CurrMb0[7:0]:mvx_CurrMb1[7:0]; + + mvx_H3_diff_a <= mbAddrB_mvx[7:0]; + mvx_H3_diff_b <= (MB_inter_size == `I16x16)? mvx_CurrMb0[7:0]:mvx_CurrMb1[15:8]; + + mvy_H0_diff_a <= mbAddrB_mvy[31:24]; mvy_H0_diff_b <= mvy_CurrMb0[7:0]; + + mvy_H1_diff_a <= mbAddrB_mvy[23:16]; + mvy_H1_diff_b <= (MB_inter_size == `I16x16)? mvy_CurrMb0[7:0]:mvy_CurrMb0[15:8]; + + mvy_H2_diff_a <= mbAddrB_mvy[15:8]; + mvy_H2_diff_b <= (MB_inter_size == `I16x16)? mvy_CurrMb0[7:0]:mvy_CurrMb1[7:0]; + + mvy_H3_diff_a <= mbAddrB_mvy[7:0]; + mvy_H3_diff_b <= (MB_inter_size == `I16x16)? mvy_CurrMb0[7:0]:mvy_CurrMb1[15:8]; + end + else + begin + mvx_H0_diff_a <= 0; mvx_H0_diff_b <= 0; + mvx_H1_diff_a <= 0; mvx_H1_diff_b <= 0; + mvx_H2_diff_a <= 0; mvx_H2_diff_b <= 0; + mvx_H3_diff_a <= 0; mvx_H3_diff_b <= 0; + mvy_H0_diff_a <= 0; mvy_H0_diff_b <= 0; + mvy_H1_diff_a <= 0; mvy_H1_diff_b <= 0; + mvy_H2_diff_a <= 0; mvy_H2_diff_b <= 0; + mvy_H3_diff_a <= 0; mvy_H3_diff_b <= 0; + end + 2'b11: //H1 + begin + mvx_H0_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb0[7:0]; + mvx_H0_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb0[23:16]; + mvx_H1_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb0[15:8]; + mvx_H1_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb0[31:24]; + mvx_H2_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb1[7:0]; + mvx_H2_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb1[23:16]; + mvx_H3_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb1[15:8]; + mvx_H3_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb1[31:24]; + + mvy_H0_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb0[7:0]; + mvy_H0_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb0[23:16]; + mvy_H1_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb0[15:8]; + mvy_H1_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb0[31:24]; + mvy_H2_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb1[7:0]; + mvy_H2_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb1[23:16]; + mvy_H3_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb1[15:8]; + mvy_H3_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb1[31:24]; + end + 2'b10: //H2 + begin + mvx_H0_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvx_CurrMb0[23:16]; + mvx_H0_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvx_CurrMb2[7:0]; + mvx_H1_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvx_CurrMb0[31:24]; + mvx_H1_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvx_CurrMb2[15:8]; + mvx_H2_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvx_CurrMb1[23:16]; + mvx_H2_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvx_CurrMb3[7:0]; + mvx_H3_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvx_CurrMb1[31:24]; + mvx_H3_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvx_CurrMb3[15:8]; + + mvy_H0_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvy_CurrMb0[23:16]; + mvy_H0_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvy_CurrMb2[7:0]; + mvy_H1_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvy_CurrMb0[31:24]; + mvy_H1_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvy_CurrMb2[15:8]; + mvy_H2_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvy_CurrMb1[23:16]; + mvy_H2_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvy_CurrMb3[7:0]; + mvy_H3_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvy_CurrMb1[31:24]; + mvy_H3_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvy_CurrMb3[15:8]; + + end + 2'b01: //H3 + begin + mvx_H0_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb2[7:0]; + mvx_H0_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb2[23:16]; + mvx_H1_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb2[15:8]; + mvx_H1_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb2[31:24]; + mvx_H2_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb3[7:0]; + mvx_H2_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb3[23:16]; + mvx_H3_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb3[15:8]; + mvx_H3_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb3[31:24]; + + mvy_H0_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb2[7:0]; + mvy_H0_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb2[23:16]; + mvy_H1_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb2[15:8]; + mvy_H1_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb2[31:24]; + mvy_H2_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb3[7:0]; + mvy_H2_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb3[23:16]; + mvy_H3_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb3[15:8]; + mvy_H3_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb3[31:24]; + end + endcase + else + begin + mvx_H0_diff_a <= 0; mvx_H0_diff_b <= 0; + mvx_H1_diff_a <= 0; mvx_H1_diff_b <= 0; + mvx_H2_diff_a <= 0; mvx_H2_diff_b <= 0; + mvx_H3_diff_a <= 0; mvx_H3_diff_b <= 0; + mvy_H0_diff_a <= 0; mvy_H0_diff_b <= 0; + mvy_H1_diff_a <= 0; mvy_H1_diff_b <= 0; + mvy_H2_diff_a <= 0; mvy_H2_diff_b <= 0; + mvy_H3_diff_a <= 0; mvy_H3_diff_b <= 0; + end + end + else + begin + mvx_H0_diff_a <= 0; mvx_H0_diff_b <= 0; + mvx_H1_diff_a <= 0; mvx_H1_diff_b <= 0; + mvx_H2_diff_a <= 0; mvx_H2_diff_b <= 0; + mvx_H3_diff_a <= 0; mvx_H3_diff_b <= 0; + mvy_H0_diff_a <= 0; mvy_H0_diff_b <= 0; + mvy_H1_diff_a <= 0; mvy_H1_diff_b <= 0; + mvy_H2_diff_a <= 0; mvy_H2_diff_b <= 0; + mvy_H3_diff_a <= 0; mvy_H3_diff_b <= 0; + end + /* + // synopsys translate_off + integer tracefile; + integer pic_num; + wire [6:0] mb_num; + assign mb_num = mb_num_v * 11 + mb_num_h; + + initial + begin + tracefile = $fopen("bs_trace.txt"); + end + reg bs_dec_will_end; + always @ (posedge clk) + if (bs_dec_counter == 2'b01) + bs_dec_will_end <= 1'b1; + else + bs_dec_will_end <= 1'b0; + always @ (posedge clk or negedge reset_n) + if (reset_n == 1'b0) + pic_num <= 0; + else if (bs_dec_will_end) + begin + $fdisplay (tracefile, "-------------------------------"); + if (mb_num == 0) + $fdisplay (tracefile, " Pic_num = %3d,MB_num = 98",(pic_num - 1)); + else + $fdisplay (tracefile, " Pic_num = %3d,MB_num = %3d",pic_num,(mb_num - 1)); + $fdisplay (tracefile, " Vertical Edge 0:Bs = %d,%d,%d,%d",bs_V0[2:0],bs_V0[5:3],bs_V0[8:6],bs_V0[11:9]); + $fdisplay (tracefile, " Vertical Edge 1:Bs = %d,%d,%d,%d",bs_V1[2:0],bs_V1[5:3],bs_V1[8:6],bs_V1[11:9]); + $fdisplay (tracefile, " Vertical Edge 2:Bs = %d,%d,%d,%d",bs_V2[2:0],bs_V2[5:3],bs_V2[8:6],bs_V2[11:9]); + $fdisplay (tracefile, " Vertical Edge 3:Bs = %d,%d,%d,%d",bs_V3[2:0],bs_V3[5:3],bs_V3[8:6],bs_V3[11:9]); + $fdisplay (tracefile, " Horizontal Edge 0:Bs = %d,%d,%d,%d",bs_H0[2:0],bs_H0[5:3],bs_H0[8:6],bs_H0[11:9]); + $fdisplay (tracefile, " Horizontal Edge 1:Bs = %d,%d,%d,%d",bs_H1[2:0],bs_H1[5:3],bs_H1[8:6],bs_H1[11:9]); + $fdisplay (tracefile, " Horizontal Edge 2:Bs = %d,%d,%d,%d",bs_H2[2:0],bs_H2[5:3],bs_H2[8:6],bs_H2[11:9]); + $fdisplay (tracefile, " Horizontal Edge 3:Bs = %d,%d,%d,%d",bs_H3[2:0],bs_H3[5:3],bs_H3[8:6],bs_H3[11:9]); + if (mb_num == 98) + pic_num <= pic_num + 1; + end + // synopsys translate_on + */ +endmodule + +module mv_diff_GE4 (mv_a,mv_b,diff_GE4); + input [7:0] mv_a,mv_b; + output diff_GE4; + wire [7:0] diff_tmp; + wire [6:0] diff; + assign diff_tmp = mv_a + ~ mv_b + 1; + assign diff = (diff_tmp[7] == 1'b1)? (~diff_tmp[6:0] + 1):diff_tmp[6:0]; + assign diff_GE4 = (diff[6:2] != 0)? 1'b1:1'b0; +endmodule + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/cavlc_consumed_bits_decoding.v b/demo_chip_rtl/rtl/nova/tags/Start/src/cavlc_consumed_bits_decoding.v new file mode 100644 index 0000000..046fd92 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/cavlc_consumed_bits_decoding.v @@ -0,0 +1,42 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : cavlc_consumed_bits_decoding.v +// Generated : June 12,2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Calculate the consumed bit length of CAVLC decoder of each clock cycle +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module cavlc_consumed_bits_decoding (cavlc_decoder_state,NumCoeffTrailingOnes_len,TrailingOnes, + heading_one_pos,levelSuffixSize,total_zeros_len,run_of_zeros_len,cavlc_consumed_bits_len); + input [3:0] cavlc_decoder_state; + input [4:0] NumCoeffTrailingOnes_len; + input [1:0] TrailingOnes; + input [3:0] heading_one_pos; + input [3:0] levelSuffixSize; + input [3:0] total_zeros_len; + input [3:0] run_of_zeros_len; + output [4:0] cavlc_consumed_bits_len; + reg [4:0] cavlc_consumed_bits_len; + + always @ (cavlc_decoder_state or NumCoeffTrailingOnes_len or TrailingOnes or heading_one_pos or + levelSuffixSize or total_zeros_len or run_of_zeros_len) + case (cavlc_decoder_state) + `NumCoeffTrailingOnes_LUT:cavlc_consumed_bits_len <= NumCoeffTrailingOnes_len; + `TrailingOnesSignFlag :cavlc_consumed_bits_len <= TrailingOnes; + `LevelPrefix :cavlc_consumed_bits_len <= heading_one_pos + 1; + `LevelSuffix :cavlc_consumed_bits_len <= levelSuffixSize; + `total_zeros_LUT :cavlc_consumed_bits_len <= total_zeros_len; + `run_before_LUT :cavlc_consumed_bits_len <= run_of_zeros_len; + default :cavlc_consumed_bits_len <= 0; + endcase +endmodule + diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/cavlc_decoder.v b/demo_chip_rtl/rtl/nova/tags/Start/src/cavlc_decoder.v new file mode 100644 index 0000000..de22b8c --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/cavlc_decoder.v @@ -0,0 +1,288 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : cavlc_decoder.v +// Generated : June 12,2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// cavlc_decoder top module +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module cavlc_decoder (clk,reset_n,gclk_end_of_MB_DEC, + gclk_LumaLevel_mbAddrB_RF,gclk_ChromaLevel_Cb_mbAddrB_RF,gclk_ChromaLevel_Cr_mbAddrB_RF, + slice_data_state,residual_state,cavlc_decoder_state,mb_num_h,mb_num_v,i8x8,i4x4,i4x4_CbCr, + i_level,i_run,i_TotalCoeff,coeffNum, + heading_one_pos,BitStream_buffer_output, + CodedBlockPatternLuma,CodedBlockPatternChroma,suffix_length_initialized,IsRunLoop, + + Luma_8x8_AllZeroCoeff_mbAddrA,LumaLevel_mbAddrA,LumaLevel_CurrMb0,LumaLevel_CurrMb1,LumaLevel_CurrMb2,LumaLevel_CurrMb3, + LumaLevel_mbAddrB_dout,LumaLevel_mbAddrB_cs_n,ChromaLevel_Cb_mbAddrB_cs_n,ChromaLevel_Cr_mbAddrB_cs_n, + end_of_one_residual_block,end_of_NonZeroCoeff_CAVLC, + cavlc_consumed_bits_len,TotalCoeff,TrailingOnes,maxNumCoeff,zerosLeft,run, + coeffLevel_0,coeffLevel_1,coeffLevel_2, coeffLevel_3, coeffLevel_4, coeffLevel_5, coeffLevel_6, coeffLevel_7, + coeffLevel_8,coeffLevel_9,coeffLevel_10,coeffLevel_11,coeffLevel_12,coeffLevel_13,coeffLevel_14,coeffLevel_15); + input clk,reset_n; + input gclk_end_of_MB_DEC; + input gclk_LumaLevel_mbAddrB_RF; + input gclk_ChromaLevel_Cb_mbAddrB_RF; + input gclk_ChromaLevel_Cr_mbAddrB_RF; + input [3:0] slice_data_state; + input [3:0] residual_state; + input [3:0] cavlc_decoder_state; + input [3:0] mb_num_h; + input [3:0] mb_num_v; + input [1:0] i8x8; + input [1:0] i4x4; + input [1:0] i4x4_CbCr; + input [3:0] i_level; + input [3:0] i_run; + input [3:0] i_TotalCoeff; + input [3:0] coeffNum; + input [3:0] heading_one_pos; + input [15:0] BitStream_buffer_output; + input [3:0] CodedBlockPatternLuma; + input [1:0] CodedBlockPatternChroma; + input suffix_length_initialized; + input IsRunLoop; + + output [1:0] Luma_8x8_AllZeroCoeff_mbAddrA; + output [19:0] LumaLevel_mbAddrA; + output [19:0] LumaLevel_CurrMb0,LumaLevel_CurrMb1,LumaLevel_CurrMb2,LumaLevel_CurrMb3; + output [19:0] LumaLevel_mbAddrB_dout; + output LumaLevel_mbAddrB_cs_n; + output ChromaLevel_Cb_mbAddrB_cs_n; + output ChromaLevel_Cr_mbAddrB_cs_n; + output end_of_one_residual_block; + output end_of_NonZeroCoeff_CAVLC; + output [4:0] cavlc_consumed_bits_len; + output [4:0] TotalCoeff; + output [1:0] TrailingOnes; + output [4:0] maxNumCoeff; + output [3:0] zerosLeft; + output [3:0] run; + output [8:0] coeffLevel_0, coeffLevel_1, coeffLevel_2,coeffLevel_3, coeffLevel_4, coeffLevel_5, coeffLevel_6; + output [8:0] coeffLevel_7, coeffLevel_8, coeffLevel_9,coeffLevel_10,coeffLevel_11,coeffLevel_12,coeffLevel_13; + output [8:0] coeffLevel_14,coeffLevel_15; + + wire LumaLevel_mbAddrB_cs_n,LumaLevel_mbAddrB_wr_n; + wire [3:0] LumaLevel_mbAddrB_rd_addr,LumaLevel_mbAddrB_wr_addr; + wire [19:0] LumaLevel_mbAddrB_din; + wire [19:0] LumaLevel_mbAddrB_dout; + wire ChromaLevel_Cb_mbAddrB_cs_n,ChromaLevel_Cb_mbAddrB_wr_n; + wire [3:0] ChromaLevel_Cb_mbAddrB_rd_addr,ChromaLevel_Cb_mbAddrB_wr_addr; + wire [9:0] ChromaLevel_Cb_mbAddrB_din; + wire [9:0] ChromaLevel_Cb_mbAddrB_dout; + wire ChromaLevel_Cr_mbAddrB_cs_n,ChromaLevel_Cr_mbAddrB_wr_n; + wire [3:0] ChromaLevel_Cr_mbAddrB_rd_addr,ChromaLevel_Cr_mbAddrB_wr_addr; + wire [9:0] ChromaLevel_Cr_mbAddrB_din; + wire [9:0] ChromaLevel_Cr_mbAddrB_dout; + wire [4:0] nC; + wire [4:0] NumCoeffTrailingOnes_len; + wire [3:0] levelSuffixSize; + wire [8:0] level_0,level_1,level_2, level_3, level_4, level_5, level_6, level_7; + wire [8:0] level_8,level_9,level_10,level_11,level_12,level_13,level_14,level_15; + wire [3:0] total_zeros; + wire [3:0] total_zeros_len; + wire [3:0] run_of_zeros_len; + + nC_decoding nC_decoding ( + .clk(clk), + .reset_n(reset_n), + .gclk_end_of_MB_DEC(gclk_end_of_MB_DEC), + .cavlc_decoder_state(cavlc_decoder_state), + .residual_state(residual_state), + .slice_data_state(slice_data_state), + .mb_num_h(mb_num_h), + .mb_num_v(mb_num_v), + .i8x8(i8x8), + .i4x4(i4x4), + .i4x4_CbCr(i4x4_CbCr), + .CodedBlockPatternLuma(CodedBlockPatternLuma), + .CodedBlockPatternChroma(CodedBlockPatternChroma), + .LumaLevel_mbAddrB_dout(LumaLevel_mbAddrB_dout), + .ChromaLevel_Cb_mbAddrB_dout(ChromaLevel_Cb_mbAddrB_dout), + .ChromaLevel_Cr_mbAddrB_dout(ChromaLevel_Cr_mbAddrB_dout), + .end_of_one_residual_block(end_of_one_residual_block), + .TotalCoeff(TotalCoeff), + + .nC(nC), + .Luma_8x8_AllZeroCoeff_mbAddrA(Luma_8x8_AllZeroCoeff_mbAddrA), + .LumaLevel_mbAddrA(LumaLevel_mbAddrA), + .LumaLevel_CurrMb0(LumaLevel_CurrMb0), + .LumaLevel_CurrMb1(LumaLevel_CurrMb1), + .LumaLevel_CurrMb2(LumaLevel_CurrMb2), + .LumaLevel_CurrMb3(LumaLevel_CurrMb3), + .LumaLevel_mbAddrB_cs_n(LumaLevel_mbAddrB_cs_n), + .LumaLevel_mbAddrB_wr_n(LumaLevel_mbAddrB_wr_n), + .LumaLevel_mbAddrB_rd_addr(LumaLevel_mbAddrB_rd_addr), + .LumaLevel_mbAddrB_wr_addr(LumaLevel_mbAddrB_wr_addr), + .LumaLevel_mbAddrB_din(LumaLevel_mbAddrB_din), + .ChromaLevel_Cb_mbAddrB_cs_n(ChromaLevel_Cb_mbAddrB_cs_n), + .ChromaLevel_Cb_mbAddrB_wr_n(ChromaLevel_Cb_mbAddrB_wr_n), + .ChromaLevel_Cb_mbAddrB_rd_addr(ChromaLevel_Cb_mbAddrB_rd_addr), + .ChromaLevel_Cb_mbAddrB_wr_addr(ChromaLevel_Cb_mbAddrB_wr_addr), + .ChromaLevel_Cb_mbAddrB_din(ChromaLevel_Cb_mbAddrB_din), + .ChromaLevel_Cr_mbAddrB_cs_n(ChromaLevel_Cr_mbAddrB_cs_n), + .ChromaLevel_Cr_mbAddrB_wr_n(ChromaLevel_Cr_mbAddrB_wr_n), + .ChromaLevel_Cr_mbAddrB_rd_addr(ChromaLevel_Cr_mbAddrB_rd_addr), + .ChromaLevel_Cr_mbAddrB_wr_addr(ChromaLevel_Cr_mbAddrB_wr_addr), + .ChromaLevel_Cr_mbAddrB_din(ChromaLevel_Cr_mbAddrB_din) + ); + ram_async_1r_sync_1w # (`LumaLevel_mbAddrB_RF_data_width,`LumaLevel_mbAddrB_RF_data_depth) + LumaLevel_mbAddrB_RF( + .clk(gclk_LumaLevel_mbAddrB_RF), + .rst_n(reset_n), + .cs_n(LumaLevel_mbAddrB_cs_n), + .wr_n(LumaLevel_mbAddrB_wr_n), + .rd_addr(LumaLevel_mbAddrB_rd_addr), + .wr_addr(LumaLevel_mbAddrB_wr_addr), + .data_in(LumaLevel_mbAddrB_din), + .data_out(LumaLevel_mbAddrB_dout) + ); + ram_async_1r_sync_1w # (`ChromaLevel_Cb_mbAddrB_RF_data_width,`ChromaLevel_Cb_mbAddrB_RF_data_depth) + ChromaLevel_Cb_mbAddrB_RF( + .clk(gclk_ChromaLevel_Cb_mbAddrB_RF), + .rst_n(reset_n), + .cs_n(ChromaLevel_Cb_mbAddrB_cs_n), + .wr_n(ChromaLevel_Cb_mbAddrB_wr_n), + .rd_addr(ChromaLevel_Cb_mbAddrB_rd_addr), + .wr_addr(ChromaLevel_Cb_mbAddrB_wr_addr), + .data_in(ChromaLevel_Cb_mbAddrB_din), + .data_out(ChromaLevel_Cb_mbAddrB_dout) + ); + ram_async_1r_sync_1w # (`ChromaLevel_Cr_mbAddrB_RF_data_width,`ChromaLevel_Cr_mbAddrB_RF_data_depth) + ChromaLevel_Cr_mbAddrB_RF( + .clk(gclk_ChromaLevel_Cr_mbAddrB_RF), + .rst_n(reset_n), + .cs_n(ChromaLevel_Cr_mbAddrB_cs_n), + .wr_n(ChromaLevel_Cr_mbAddrB_wr_n), + .rd_addr(ChromaLevel_Cr_mbAddrB_rd_addr), + .wr_addr(ChromaLevel_Cr_mbAddrB_wr_addr), + .data_in(ChromaLevel_Cr_mbAddrB_din), + .data_out(ChromaLevel_Cr_mbAddrB_dout) + ); + NumCoeffTrailingOnes_decoding NumCoeffTrailingOnes_decoding( + .clk(clk), + .reset_n(reset_n), + .cavlc_decoder_state(cavlc_decoder_state), + .heading_one_pos(heading_one_pos), + .BitStream_buffer_output(BitStream_buffer_output), + .nC(nC), + .TrailingOnes(TrailingOnes), + .TotalCoeff(TotalCoeff), + .NumCoeffTrailingOnes_len(NumCoeffTrailingOnes_len) + ); + level_decoding level_decoding( + .clk(clk), + .reset_n(reset_n), + .cavlc_decoder_state(cavlc_decoder_state), + .heading_one_pos(heading_one_pos), + .suffix_length_initialized(suffix_length_initialized), + .i_level(i_level), + .TotalCoeff(TotalCoeff), + .TrailingOnes(TrailingOnes), + .BitStream_buffer_output(BitStream_buffer_output), + .levelSuffixSize(levelSuffixSize), + .level_0(level_0), + .level_1(level_1), + .level_2(level_2), + .level_3(level_3), + .level_4(level_4), + .level_5(level_5), + .level_6(level_6), + .level_7(level_7), + .level_8(level_8), + .level_9(level_9), + .level_10(level_10), + .level_11(level_11), + .level_12(level_12), + .level_13(level_13), + .level_14(level_14), + .level_15(level_15) + ); + total_zeros_decoding total_zeros_decoding( + .clk(clk), + .reset_n(reset_n), + .residual_state(residual_state), + .cavlc_decoder_state(cavlc_decoder_state), + .TotalCoeff_3to0(TotalCoeff[3:0]), + .heading_one_pos(heading_one_pos), + .BitStream_buffer_output(BitStream_buffer_output), + .maxNumCoeff(maxNumCoeff), + .total_zeros(total_zeros), + .total_zeros_len(total_zeros_len) + ); + run_decoding run_decoding( + .clk(clk), + .reset_n(reset_n), + .cavlc_decoder_state(cavlc_decoder_state), + .BitStream_buffer_output(BitStream_buffer_output), + .total_zeros(total_zeros), + .level_0(level_0), + .level_1(level_1), + .level_2(level_2), + .level_3(level_3), + .level_4(level_4), + .level_5(level_5), + .level_6(level_6), + .level_7(level_7), + .level_8(level_8), + .level_9(level_9), + .level_10(level_10), + .level_11(level_11), + .level_12(level_12), + .level_13(level_13), + .level_14(level_14), + .level_15(level_15), + .TotalCoeff(TotalCoeff), + .i_run(i_run), + .i_TotalCoeff(i_TotalCoeff), + .coeffNum(coeffNum), + .IsRunLoop(IsRunLoop), + + .run_of_zeros_len(run_of_zeros_len), + .zerosLeft(zerosLeft), + .run(run), + .coeffLevel_0(coeffLevel_0), + .coeffLevel_1(coeffLevel_1), + .coeffLevel_2(coeffLevel_2), + .coeffLevel_3(coeffLevel_3), + .coeffLevel_4(coeffLevel_4), + .coeffLevel_5(coeffLevel_5), + .coeffLevel_6(coeffLevel_6), + .coeffLevel_7(coeffLevel_7), + .coeffLevel_8(coeffLevel_8), + .coeffLevel_9(coeffLevel_9), + .coeffLevel_10(coeffLevel_10), + .coeffLevel_11(coeffLevel_11), + .coeffLevel_12(coeffLevel_12), + .coeffLevel_13(coeffLevel_13), + .coeffLevel_14(coeffLevel_14), + .coeffLevel_15(coeffLevel_15) + ); + end_of_blk_decoding end_of_blk_decoding( + .reset_n(reset_n), + .cavlc_decoder_state(cavlc_decoder_state), + .TotalCoeff(TotalCoeff), + .i_TotalCoeff(i_TotalCoeff), + .end_of_one_residual_block(end_of_one_residual_block), + .end_of_NonZeroCoeff_CAVLC(end_of_NonZeroCoeff_CAVLC) + ); + cavlc_consumed_bits_decoding cavlc_consumed_bits_decoding( + .cavlc_decoder_state(cavlc_decoder_state), + .NumCoeffTrailingOnes_len(NumCoeffTrailingOnes_len), + .TrailingOnes(TrailingOnes), + .heading_one_pos(heading_one_pos), + .levelSuffixSize(levelSuffixSize), + .total_zeros_len(total_zeros_len), + .run_of_zeros_len(run_of_zeros_len), + .cavlc_consumed_bits_len(cavlc_consumed_bits_len) + ); +endmodule \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/dependent_variable_decoding.v b/demo_chip_rtl/rtl/nova/tags/Start/src/dependent_variable_decoding.v new file mode 100644 index 0000000..b37f861 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/dependent_variable_decoding.v @@ -0,0 +1,55 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : dependent_variable_decoding.v +// Generated : June 6,2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// for u(v) decoding as frame_num,pic_order_cnt_lsb +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module dependent_variable_decoding (slice_header_state,log2_max_frame_num_minus4, + log2_max_pic_order_cnt_lsb_minus4,BitStream_buffer_output, + dependent_variable_len,dependent_variable_decoding_output); + input [3:0] slice_header_state; + input [3:0] log2_max_frame_num_minus4; + input [3:0] log2_max_pic_order_cnt_lsb_minus4; + input [15:0] BitStream_buffer_output; + output [3:0] dependent_variable_len; + output [9:0] dependent_variable_decoding_output; + reg [3:0] dependent_variable_len; + reg [9:0] dependent_variable_decoding_output; + + always @ (slice_header_state or log2_max_frame_num_minus4 or log2_max_pic_order_cnt_lsb_minus4) + if (slice_header_state == `frame_num_s) + dependent_variable_len <= log2_max_frame_num_minus4 + 4; + else if (slice_header_state == `pic_order_cnt_lsb_s) + dependent_variable_len <= log2_max_pic_order_cnt_lsb_minus4 + 4; + else + dependent_variable_len <= 0; + + always @ (slice_header_state or dependent_variable_len or BitStream_buffer_output) + if (slice_header_state == `frame_num_s || slice_header_state == `pic_order_cnt_lsb_s) + case (dependent_variable_len) + 4 :dependent_variable_decoding_output <= {6'b0,BitStream_buffer_output[15:12]}; + 5 :dependent_variable_decoding_output <= {5'b0,BitStream_buffer_output[15:11]}; + 6 :dependent_variable_decoding_output <= {4'b0,BitStream_buffer_output[15:10]}; + 7 :dependent_variable_decoding_output <= {3'b0,BitStream_buffer_output[15:9]}; + 8 :dependent_variable_decoding_output <= {2'b0,BitStream_buffer_output[15:8]}; + 9 :dependent_variable_decoding_output <= {1'b0,BitStream_buffer_output[15:7]}; + 10:dependent_variable_decoding_output <= BitStream_buffer_output[15:6]; + default:dependent_variable_decoding_output <= 0; + endcase + else + dependent_variable_decoding_output <= 0; +endmodule + + + diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/end_of_blk_decoding.v b/demo_chip_rtl/rtl/nova/tags/Start/src/end_of_blk_decoding.v new file mode 100644 index 0000000..e92989c --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/end_of_blk_decoding.v @@ -0,0 +1,64 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : end_of_blk_decoding.v +// Generated : June 12, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Decoding end_of_one_residual_block signal for 1 cycle duration +// 1)for BitStream_parser_FSM to update signals such as i4x4 and direct state switch +// 2)for nC_decoding to update LumaLevel/ChromaLevel CurrMb,mbAddrA,mbAddrB +// Decoding end_of_residual signal for 1 cycle duration +// 1)for nC_decoding to update general control regs such as Luma_8x8_AllZeroCoeff_mbAddrA,Luma_8x8_AllZeroCoeff_mbAddrB_reg,Chroma_8x8_AllZeroCoeff_mbAddrA,Chroma_8x8_AllZeroCoeff_mbAddrB_reg +// 2)Note:for P_skip MBs,their general control regs as *8x8_ALLZeroCoeff* are directly controlled by the state instead of end_of_residual signal +//------------------------------------------------------------------------------------------------- +// Revise log +// 1. March 24,2006 +// Add signal end_of_NonZeroCoeff_CAVLC for IQIT to update res_AC/res_DC/... signals. +// end_of_NonZeroCoeff_CAVLC:combinational logic,active one cycle at the end of CAVLC decoding of one non zero coefficient residual. +// 2. March 29,2006 +// Add signal lumaDC_IsAllZero,ChromaDC_Cb_IsAllZero,ChromaDC_Cr_IsAllZero to deal with special case:zero DC coeff,but non-zero AC coeff +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module end_of_blk_decoding (reset_n,cavlc_decoder_state, + TotalCoeff,i_TotalCoeff,end_of_one_residual_block,end_of_NonZeroCoeff_CAVLC + ); + input reset_n; + input [3:0] cavlc_decoder_state; + input [4:0] TotalCoeff; + input [3:0] i_TotalCoeff; + output end_of_one_residual_block; + output end_of_NonZeroCoeff_CAVLC; + + reg end_of_one_residual_block; + reg end_of_NonZeroCoeff_CAVLC; + reg lumaDC_IsAllZero; + reg ChromaDC_Cb_IsAllZero; + reg ChromaDC_Cr_IsAllZero; + + always @ (reset_n or cavlc_decoder_state or TotalCoeff or i_TotalCoeff) + if (reset_n == 0) + end_of_one_residual_block <= 0; + else if (cavlc_decoder_state == `NumCoeffTrailingOnes_LUT && TotalCoeff == 0) + end_of_one_residual_block <= 1; + else if (cavlc_decoder_state == `LevelRunCombination && i_TotalCoeff == 0) + end_of_one_residual_block <= 1; + else + end_of_one_residual_block <= 0; + + always @ (reset_n or cavlc_decoder_state or i_TotalCoeff) + if (reset_n == 0) + end_of_NonZeroCoeff_CAVLC <= 0; + else if (cavlc_decoder_state == `LevelRunCombination && i_TotalCoeff == 0) + end_of_NonZeroCoeff_CAVLC <= 1; + else + end_of_NonZeroCoeff_CAVLC <= 0; + +endmodule \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/exp_golomb_decoding.v b/demo_chip_rtl/rtl/nova/tags/Start/src/exp_golomb_decoding.v new file mode 100644 index 0000000..660a92d --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/exp_golomb_decoding.v @@ -0,0 +1,152 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : exp_golomb_decoding.v +// Generated : June 6, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Exp-Golomb code decoding +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module exp_golomb_decoding (reset_n,heading_one_pos,BitStream_buffer_output,num_ref_idx_l0_active_minus1, + slice_header_state,slice_data_state,mb_pred_state,sub_mb_pred_state, + seq_parameter_set_state,pic_parameter_set_state,exp_golomb_decoding_output,exp_golomb_len); + input reset_n; + input [3:0] heading_one_pos; + input [15:0] BitStream_buffer_output; + input [2:0] num_ref_idx_l0_active_minus1; + input [3:0] slice_header_state; + input [3:0] slice_data_state; + input [2:0] mb_pred_state; + input [1:0] sub_mb_pred_state; + input [3:0] seq_parameter_set_state; + input [3:0] pic_parameter_set_state; + output [7:0] exp_golomb_decoding_output; + output [3:0] exp_golomb_len; + + reg [7:0] exp_golomb_decoding_output; + reg [3:0] exp_golomb_len; + + parameter rst_exp_golomb_sel = 2'b00; + parameter ue = 2'b01; + parameter se = 2'b10; + parameter te = 2'b11; + + reg [7:0] codeNum; + reg [1:0] exp_golomb_sel; + + always @ (exp_golomb_sel or heading_one_pos or BitStream_buffer_output) + if (exp_golomb_sel != rst_exp_golomb_sel) + case (heading_one_pos) + 0:codeNum <= 0; + 1:codeNum <= {6'b0,BitStream_buffer_output[14:13]} - 1; + 2:codeNum <= {5'b0,BitStream_buffer_output[13:11]} - 1; + 3:codeNum <= {4'b0,BitStream_buffer_output[12:9]} - 1; + 4:codeNum <= {3'b0,BitStream_buffer_output[11:7]} - 1; + 5:codeNum <= {2'b0,BitStream_buffer_output[10:5]} - 1; + 6:codeNum <= {1'b0,BitStream_buffer_output[9:3]} - 1; + 7:codeNum <= BitStream_buffer_output[8:1] - 1; + default:codeNum <= 0; + endcase + else + codeNum <= 0; + + wire [2:0] te_range; + assign te_range = num_ref_idx_l0_active_minus1 + 1; + always @ (exp_golomb_sel or heading_one_pos or te_range) + case (exp_golomb_sel) + ue,se:exp_golomb_len <= (heading_one_pos << 1) + 1; + te :exp_golomb_len <= (te_range == 2)? 1:((heading_one_pos << 1) + 1); + default:exp_golomb_len <= 0; + endcase + + wire [7:0] codeNum_se_tmp; + assign codeNum_se_tmp = codeNum >> 1; + always @ (exp_golomb_sel or codeNum or codeNum_se_tmp or te_range) + case (exp_golomb_sel) + ue:exp_golomb_decoding_output <= codeNum; + se: + case (codeNum[0]) + 1:exp_golomb_decoding_output <= (codeNum + 1) >> 1; + 0:exp_golomb_decoding_output <= ~codeNum_se_tmp + 1; + endcase + te: + if (te_range == 2) exp_golomb_decoding_output <= (codeNum == 0)? 8'd0:8'd1; + else exp_golomb_decoding_output <= codeNum; + default:exp_golomb_decoding_output <= 0; + endcase + + always @ (reset_n or slice_header_state or slice_data_state or mb_pred_state or sub_mb_pred_state or + seq_parameter_set_state or pic_parameter_set_state) + if (reset_n == 0) + exp_golomb_sel <= rst_exp_golomb_sel; + else if (slice_header_state != `rst_slice_header) + case (slice_header_state) + `first_mb_in_slice_s :exp_golomb_sel <= ue; + `slice_type_s :exp_golomb_sel <= ue; + `pic_parameter_set_id_slice_header_s:exp_golomb_sel <= ue; + `idr_pic_id_s :exp_golomb_sel <= ue; + `slice_qp_delta_s :exp_golomb_sel <= se; + `disable_deblocking_filter_idc_s :exp_golomb_sel <= ue; + `slice_alpha_c0_offset_div2_s :exp_golomb_sel <= se; + `slice_beta_offset_div2_s :exp_golomb_sel <= ue; + default :exp_golomb_sel <= rst_exp_golomb_sel; + endcase + else if (slice_data_state != `rst_slice_data) + case (slice_data_state) + `mb_skip_run_s :exp_golomb_sel <= ue; + `mb_type_s :exp_golomb_sel <= ue; + `sub_mb_pred: + case (sub_mb_pred_state) + `sub_mb_type_s :exp_golomb_sel <= ue; + `sub_ref_idx_l0_s:exp_golomb_sel <= te; + `sub_mvd_l0_s :exp_golomb_sel <= se; + default :exp_golomb_sel <= rst_exp_golomb_sel; + endcase + `mb_pred: + case (mb_pred_state) + `intra_chroma_pred_mode_s:exp_golomb_sel <= ue; + `ref_idx_l0_s :exp_golomb_sel <= te; + `mvd_l0_s :exp_golomb_sel <= se; + default :exp_golomb_sel <= rst_exp_golomb_sel; + endcase + `coded_block_pattern_s :exp_golomb_sel <= ue; + `mb_qp_delta_s :exp_golomb_sel <= se; + default :exp_golomb_sel <= rst_exp_golomb_sel; + endcase + else if (seq_parameter_set_state != `rst_seq_parameter_set) + case (seq_parameter_set_state) + `seq_parameter_set_id_sps_s :exp_golomb_sel <= ue; + `log2_max_frame_num_minus4_s :exp_golomb_sel <= ue; + `pic_order_cnt_type_s :exp_golomb_sel <= ue; + `log2_max_pic_order_cnt_lsb_minus4_s:exp_golomb_sel <= ue; + `num_ref_frames_s :exp_golomb_sel <= ue; + `pic_width_in_mbs_minus1_s :exp_golomb_sel <= ue; + `pic_height_in_map_units_minus1_s :exp_golomb_sel <= ue; + default :exp_golomb_sel <= rst_exp_golomb_sel; + endcase + else if (pic_parameter_set_state != `rst_pic_parameter_set) + case (pic_parameter_set_state) + `pic_parameter_set_id_pps_s :exp_golomb_sel <= ue; + `seq_parameter_set_id_pps_s :exp_golomb_sel <= ue; + `num_slice_groups_minus1_s :exp_golomb_sel <= ue; + `num_ref_idx_l0_active_minus1_pps_s:exp_golomb_sel <= ue; + `num_ref_idx_l1_active_minus1_pps_s:exp_golomb_sel <= ue; + `pic_init_qp_minus26_s :exp_golomb_sel <= se; + `pic_init_qs_minus26_s :exp_golomb_sel <= se; + `chroma_qp_index_offset_s :exp_golomb_sel <= se; + default :exp_golomb_sel <= rst_exp_golomb_sel; + endcase + else + exp_golomb_sel <= rst_exp_golomb_sel; + +endmodule + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/ext_RAM_ctrl.v b/demo_chip_rtl/rtl/nova/tags/Start/src/ext_RAM_ctrl.v new file mode 100644 index 0000000..2f9f2fa --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/ext_RAM_ctrl.v @@ -0,0 +1,97 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : ext_frame_RAM1_wrapper.v +// Generated : Nov 28,2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Controller for ext_frame_RAM +// Rread as ref_frame_RAM before Inter Prediction +// Write as dis_frame_RAM after Deblocking Filter +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module ext_RAM_ctrl (clk,reset_n,end_of_one_frame,ref_frame_RAM_rd,ref_frame_RAM_rd_addr,dis_frame_RAM_wr, + dis_frame_RAM_wr_addr,ref_frame_RAM_dout, + ext_frame_RAM0_cs_n,ext_frame_RAM0_wr,ext_frame_RAM0_addr,ext_frame_RAM0_data, + ext_frame_RAM1_cs_n,ext_frame_RAM1_wr,ext_frame_RAM1_addr,ext_frame_RAM1_data); + input clk,reset_n; + input end_of_one_frame; + input ref_frame_RAM_rd; + input [13:0] ref_frame_RAM_rd_addr; + input dis_frame_RAM_wr; + input [13:0] dis_frame_RAM_wr_addr; + //input [31:0] dis_frame_RAM_din; + input [31:0] ext_frame_RAM0_data; + input [31:0] ext_frame_RAM1_data; + + output [31:0] ref_frame_RAM_dout; + + output ext_frame_RAM0_cs_n; + output ext_frame_RAM0_wr; + output [13:0] ext_frame_RAM0_addr; + + output ext_frame_RAM1_cs_n; + output ext_frame_RAM1_wr; + output [13:0] ext_frame_RAM1_addr; + + reg ext_frame_RAM_sel; //0:ext_frame_RAM0 as dis_frame_RAM to be written + //0:ext_frame_RAM1 as ref_frame_RAM to be read + //1:ext_frame_RAM0 as ref_frame_RAM to be read + //1:ext_frame_RAM1 as dis_frame_RAM to be written + always @ (posedge clk) + if (reset_n == 1'b0) + ext_frame_RAM_sel <= 1'b0; + else if (end_of_one_frame) + ext_frame_RAM_sel <= ~ ext_frame_RAM_sel; + + reg [31:0] ref_frame_RAM_dout; + + reg ext_frame_RAM0_cs_n; + reg ext_frame_RAM0_wr; + reg [13:0] ext_frame_RAM0_addr; + + reg ext_frame_RAM1_cs_n; + reg ext_frame_RAM1_wr; + reg [13:0] ext_frame_RAM1_addr; + + always @ (ext_frame_RAM_sel or + ref_frame_RAM_rd or ref_frame_RAM_rd_addr or ext_frame_RAM0_data or ext_frame_RAM1_data or + dis_frame_RAM_wr or dis_frame_RAM_wr_addr) + case (ext_frame_RAM_sel) + 1'b0: + begin + //ext_frame_RAM0 as dis_frame_RAM to be written + ext_frame_RAM0_cs_n <= !dis_frame_RAM_wr; ext_frame_RAM0_wr <= dis_frame_RAM_wr; + ext_frame_RAM0_addr <= dis_frame_RAM_wr_addr; + + //ext_frame_RAM1 as ref_frame_RAM to be read + ext_frame_RAM1_cs_n <= !ref_frame_RAM_rd; ext_frame_RAM1_wr <= 1'b0; + ext_frame_RAM1_addr <= ref_frame_RAM_rd_addr; + + ref_frame_RAM_dout <= ext_frame_RAM1_data; + end + 1'b1: + begin + //ext_frame_RAM0 as ref_frame_RAM to be read + ext_frame_RAM0_cs_n <= !ref_frame_RAM_rd; ext_frame_RAM0_wr <= 1'b0; + ext_frame_RAM0_addr <= ref_frame_RAM_rd_addr; + + //ext_frame_RAM1 as dis_frame_RAM to be written + ext_frame_RAM1_cs_n <= !dis_frame_RAM_wr; ext_frame_RAM1_wr <= dis_frame_RAM_wr; + ext_frame_RAM1_addr <= dis_frame_RAM_wr_addr; + + ref_frame_RAM_dout <= ext_frame_RAM0_data; + end + endcase + //assign ext_frame_RAM0_data = (!ext_frame_RAM_sel && dis_frame_RAM_wr)? dis_frame_RAM_din:32'bz; + //assign ext_frame_RAM1_data = ( ext_frame_RAM_sel && dis_frame_RAM_wr)? dis_frame_RAM_din:32'bz; +endmodule + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/ext_frame_RAM0_wrapper.v b/demo_chip_rtl/rtl/nova/tags/Start/src/ext_frame_RAM0_wrapper.v new file mode 100644 index 0000000..ee62bce --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/ext_frame_RAM0_wrapper.v @@ -0,0 +1,135 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : ext_frame_RAM0_wrapper.v +// Generated : April 23,2006 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// SRAM beha model for external RAM tween reconstruction and deblocking filter (9504x32bit) +// Sync Read,Sync Write +//------------------------------------------------------------------------------------------------- +// Revise log +// 1.July 23,2006 +// Change the ext_frame_RAM0 from async read to sync read. +// +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module ext_frame_RAM0_wrapper (clk,reset_n,ext_frame_RAM0_cs_n,ext_frame_RAM0_wr,ext_frame_RAM0_addr,dis_frame_RAM_din,ext_frame_RAM0_data, + pic_num,slice_header_s6); + input clk; + input reset_n; + input ext_frame_RAM0_cs_n; + input ext_frame_RAM0_wr; + input [13:0] ext_frame_RAM0_addr; + input [31:0] dis_frame_RAM_din; + input [5:0] pic_num; + input slice_header_s6; + output [31:0] ext_frame_RAM0_data; + + reg [31:0] ext_frame_RAM0 [0:9503]; + reg [31:0] ext_frame_RAM0_data; + + always @ (posedge clk) + if (!ext_frame_RAM0_cs_n && ext_frame_RAM0_wr) + ext_frame_RAM0[ext_frame_RAM0_addr] <= dis_frame_RAM_din; + + //assign ext_frame_RAM0_data = (!ext_frame_RAM0_cs_n && !ext_frame_RAM0_wr)? ext_frame_RAM0[ext_frame_RAM0_addr]:32'bz; + always @ (posedge clk) + if (!ext_frame_RAM0_cs_n && !ext_frame_RAM0_wr) + ext_frame_RAM0_data <= ext_frame_RAM0[ext_frame_RAM0_addr]; + + + // synopsys translate_off + integer tracefile_display; + integer tracefile_verify; + integer mb_num; + integer j; + reg [31:0] luma_out0,luma_out1,luma_out2,luma_out3; + reg [31:0] Cb_out0,Cb_out1; + reg [31:0] Cr_out0,Cr_out1; + reg [8:0] pic_num_ext; + + parameter display = 1; + parameter verify = 1; + + always @ (negedge reset_n or pic_num) + if (reset_n == 1'b0) + pic_num_ext <= 0; + else + pic_num_ext <= pic_num_ext + 1; + + + always @ (posedge clk) + if (slice_header_s6 == 1'b1 && pic_num[0] == 1'b1) + begin + if (display == 1'b1) //display + begin + tracefile_display = $fopen("nova_display.log","a"); + for (j= 0; j < 9504; j= j + 1) + begin + $fdisplay (tracefile_display,"%h",ext_frame_RAM0[j]); + end + $fclose(tracefile_display); + end + if (verify == 1'b1) //verify + begin + tracefile_verify = $fopen("nova_MB_output.log","a"); + for (mb_num = 0;mb_num < 99; mb_num = mb_num + 1) + begin + $fdisplay (tracefile_verify,"-------------------------------------------"); + $fdisplay (tracefile_verify," Pic_num = %3d,MB_num = %3d",pic_num_ext - 1,mb_num); + $fdisplay (tracefile_verify,"-------------------------------------------"); + $fdisplay (tracefile_verify," luma 16x16 block:"); + for (j = 0; j < 16; j = j + 1) + begin + luma_out0 = ext_frame_RAM0[(mb_num/11)*704+(mb_num%11)*4+j*44]; + luma_out1 = ext_frame_RAM0[(mb_num/11)*704+(mb_num%11)*4+j*44+1]; + luma_out2 = ext_frame_RAM0[(mb_num/11)*704+(mb_num%11)*4+j*44+2]; + luma_out3 = ext_frame_RAM0[(mb_num/11)*704+(mb_num%11)*4+j*44+3]; + + $fdisplay (tracefile_verify," %3H %3H %3H %3H | %3H %3H %3H %3H | %3H %3H %3H %3H | %3H %3H %3H %3H", + luma_out0[7:0],luma_out0[15:8],luma_out0[23:16],luma_out0[31:24], + luma_out1[7:0],luma_out1[15:8],luma_out1[23:16],luma_out1[31:24], + luma_out2[7:0],luma_out2[15:8],luma_out2[23:16],luma_out2[31:24], + luma_out3[7:0],luma_out3[15:8],luma_out3[23:16],luma_out3[31:24]); + + if (j == 3 || j == 7 || j == 11) + $fdisplay (tracefile_verify, ""); + end + $fdisplay (tracefile_verify," Chroma Cb 8x8 block:"); + for (j = 0; j < 8; j = j + 1) + begin + Cb_out0 = ext_frame_RAM0[6336+(mb_num/11)*176+(mb_num%11)*2+j*22]; + Cb_out1 = ext_frame_RAM0[6336+(mb_num/11)*176+(mb_num%11)*2+j*22+1]; + + $fdisplay (tracefile_verify, " %3H %3H %3H %3H | %3H %3H %3H %3H", + Cb_out0[7:0],Cb_out0[15:8],Cb_out0[23:16],Cb_out0[31:24], + Cb_out1[7:0],Cb_out1[15:8],Cb_out1[23:16],Cb_out1[31:24]); + if (j == 3) + $fdisplay (tracefile_verify, ""); + end + $fdisplay (tracefile_verify," Chroma Cr 8x8 block:"); + for (j = 0; j < 8; j = j + 1) + begin + Cr_out0 = ext_frame_RAM0[7920+(mb_num/11)*176+(mb_num%11)*2+j*22]; + Cr_out1 = ext_frame_RAM0[7920+(mb_num/11)*176+(mb_num%11)*2+j*22+1]; + + $fdisplay (tracefile_verify, " %3H %3H %3H %3H | %3H %3H %3H %3H", + Cr_out0[7:0],Cr_out0[15:8],Cr_out0[23:16],Cr_out0[31:24], + Cr_out1[7:0],Cr_out1[15:8],Cr_out1[23:16],Cr_out1[31:24]); + if (j == 3) + $fdisplay (tracefile_verify, ""); + end + end + $fclose(tracefile_verify); + end + end + // synopsys translate_on +endmodule \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/ext_frame_RAM1_wrapper.v b/demo_chip_rtl/rtl/nova/tags/Start/src/ext_frame_RAM1_wrapper.v new file mode 100644 index 0000000..16e0ad4 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/ext_frame_RAM1_wrapper.v @@ -0,0 +1,134 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : ext_frame_RAM1_wrapper.v +// Generated : April 23,2006 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// SRAM beha model for external RAM tween reconstruction and deblocking filter (9504x32bit) +// Sync Read,Sync Write +//------------------------------------------------------------------------------------------------- +// Revise log +// 1.July 23,2006 +// Change the ext_frame_RAM1 from async read to sync read. +// +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module ext_frame_RAM1_wrapper (clk,reset_n,ext_frame_RAM1_cs_n,ext_frame_RAM1_wr,ext_frame_RAM1_addr,dis_frame_RAM_din,ext_frame_RAM1_data, + pic_num,slice_header_s6); + input clk; + input reset_n; + input ext_frame_RAM1_cs_n; + input ext_frame_RAM1_wr; + input [13:0] ext_frame_RAM1_addr; + input [31:0] dis_frame_RAM_din; + input [5:0] pic_num; + input slice_header_s6; + output [31:0] ext_frame_RAM1_data; + + reg [31:0] ext_frame_RAM1 [0:9503]; + reg [31:0] ext_frame_RAM1_data; + + always @ (posedge clk) + if (!ext_frame_RAM1_cs_n && ext_frame_RAM1_wr) + ext_frame_RAM1[ext_frame_RAM1_addr] <= dis_frame_RAM_din; + + //assign ext_frame_RAM1_data = (!ext_frame_RAM1_cs_n && !ext_frame_RAM1_wr)? ext_frame_RAM1[ext_frame_RAM1_addr]:32'bz; + + always @ (posedge clk) + if (!ext_frame_RAM1_cs_n && !ext_frame_RAM1_wr) + ext_frame_RAM1_data <= ext_frame_RAM1[ext_frame_RAM1_addr]; + + // synopsys translate_off + integer tracefile_display; + integer tracefile_verify; + integer mb_num; + integer j; + reg [31:0] luma_out0,luma_out1,luma_out2,luma_out3; + reg [31:0] Cb_out0,Cb_out1; + reg [31:0] Cr_out0,Cr_out1; + reg [8:0] pic_num_ext; + + parameter display = 1; + parameter verify = 1; + +always @ (negedge reset_n or pic_num) + if (reset_n == 1'b0) + pic_num_ext <= 0; + else + pic_num_ext <= pic_num_ext + 1; + + always @ (posedge clk) + if (slice_header_s6 == 1'b1 && pic_num[0] == 1'b0 && pic_num_ext != 0) + begin + if (display == 1'b1) //display + begin + tracefile_display = $fopen("nova_display.log","a"); + for (j= 0; j < 9504; j= j + 1) + begin + $fdisplay (tracefile_display,"%h",ext_frame_RAM1[j]); + end + $fclose(tracefile_display); + end + if (verify == 1'b1) //verify + begin + tracefile_verify = $fopen("nova_MB_output.log","a"); + for (mb_num = 0;mb_num < 99; mb_num = mb_num + 1) + begin + $fdisplay (tracefile_verify,"-------------------------------------------"); + $fdisplay (tracefile_verify," Pic_num = %3d,MB_num = %3d",pic_num_ext - 1,mb_num); + $fdisplay (tracefile_verify,"-------------------------------------------"); + $fdisplay (tracefile_verify," luma 16x16 block:"); + for (j = 0; j < 16; j = j + 1) + begin + luma_out0 = ext_frame_RAM1[(mb_num/11)*704+(mb_num%11)*4+j*44]; + luma_out1 = ext_frame_RAM1[(mb_num/11)*704+(mb_num%11)*4+j*44+1]; + luma_out2 = ext_frame_RAM1[(mb_num/11)*704+(mb_num%11)*4+j*44+2]; + luma_out3 = ext_frame_RAM1[(mb_num/11)*704+(mb_num%11)*4+j*44+3]; + + $fdisplay (tracefile_verify," %3H %3H %3H %3H | %3H %3H %3H %3H | %3H %3H %3H %3H | %3H %3H %3H %3H", + luma_out0[7:0],luma_out0[15:8],luma_out0[23:16],luma_out0[31:24], + luma_out1[7:0],luma_out1[15:8],luma_out1[23:16],luma_out1[31:24], + luma_out2[7:0],luma_out2[15:8],luma_out2[23:16],luma_out2[31:24], + luma_out3[7:0],luma_out3[15:8],luma_out3[23:16],luma_out3[31:24]); + + if (j == 3 || j == 7 || j == 11) + $fdisplay (tracefile_verify, ""); + end + $fdisplay (tracefile_verify," Chroma Cb 8x8 block:"); + for (j = 0; j < 8; j = j + 1) + begin + Cb_out0 = ext_frame_RAM1[6336+(mb_num/11)*176+(mb_num%11)*2+j*22]; + Cb_out1 = ext_frame_RAM1[6336+(mb_num/11)*176+(mb_num%11)*2+j*22+1]; + + $fdisplay (tracefile_verify, " %3H %3H %3H %3H | %3H %3H %3H %3H", + Cb_out0[7:0],Cb_out0[15:8],Cb_out0[23:16],Cb_out0[31:24], + Cb_out1[7:0],Cb_out1[15:8],Cb_out1[23:16],Cb_out1[31:24]); + if (j == 3) + $fdisplay (tracefile_verify, ""); + end + $fdisplay (tracefile_verify," Chroma Cr 8x8 block:"); + for (j = 0; j < 8; j = j + 1) + begin + Cr_out0 = ext_frame_RAM1[7920+(mb_num/11)*176+(mb_num%11)*2+j*22]; + Cr_out1 = ext_frame_RAM1[7920+(mb_num/11)*176+(mb_num%11)*2+j*22+1]; + + $fdisplay (tracefile_verify, " %3H %3H %3H %3H | %3H %3H %3H %3H", + Cr_out0[7:0],Cr_out0[15:8],Cr_out0[23:16],Cr_out0[31:24], + Cr_out1[7:0],Cr_out1[15:8],Cr_out1[23:16],Cr_out1[31:24]); + if (j == 3) + $fdisplay (tracefile_verify, ""); + end + end + $fclose(tracefile_verify); + end + end + // synopsys translate_on +endmodule \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/heading_one_detector.v b/demo_chip_rtl/rtl/nova/tags/Start/src/heading_one_detector.v new file mode 100644 index 0000000..f47134a --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/heading_one_detector.v @@ -0,0 +1,60 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : heading_one_detector.v +// Generated : June 6, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Priority based heading one detection +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module heading_one_detector (heading_one_en,BitStream_buffer_output,heading_one_pos); + input heading_one_en; + input [15:0] BitStream_buffer_output; + output [3:0] heading_one_pos; + reg [3:0] heading_one_pos; + + always @ (heading_one_en or BitStream_buffer_output) + if (heading_one_en == 1'b0) + begin + if (BitStream_buffer_output[15] == 1'b1 || BitStream_buffer_output[14] == 1'b1) + begin + if (BitStream_buffer_output[15] == 1'b1) heading_one_pos <= 0; + else heading_one_pos <= 4'd1; + end + else if (BitStream_buffer_output[13] == 1'b1 || BitStream_buffer_output[12] == 1'b1 || + BitStream_buffer_output[11] == 1'b1 || BitStream_buffer_output[10] == 1'b1) + begin + if (BitStream_buffer_output[13] == 1'b1) heading_one_pos <= 4'd2; + else if (BitStream_buffer_output[12] == 1'b1) heading_one_pos <= 4'd3; + else if (BitStream_buffer_output[11] == 1'b1) heading_one_pos <= 4'd4; + else heading_one_pos <= 4'd5; + end + else + begin + if (BitStream_buffer_output[9] == 1'b1) heading_one_pos <= 4'd6; + else if (BitStream_buffer_output[8] == 1'b1) heading_one_pos <= 4'd7; + else if (BitStream_buffer_output[7] == 1'b1) heading_one_pos <= 4'd8; + else if (BitStream_buffer_output[6] == 1'b1) heading_one_pos <= 4'd9; + else if (BitStream_buffer_output[5] == 1'b1) heading_one_pos <= 4'd10; + else if (BitStream_buffer_output[4] == 1'b1) heading_one_pos <= 4'd11; + else if (BitStream_buffer_output[3] == 1'b1) heading_one_pos <= 4'd12; + else if (BitStream_buffer_output[2] == 1'b1) heading_one_pos <= 4'd13; + else if (BitStream_buffer_output[1] == 1'b1) heading_one_pos <= 4'd14; + else heading_one_pos <= 4'd15; + end + end + else + heading_one_pos <= 0; +endmodule + + + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/hybrid_pipeline_ctrl.v b/demo_chip_rtl/rtl/nova/tags/Start/src/hybrid_pipeline_ctrl.v new file mode 100644 index 0000000..901c367 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/hybrid_pipeline_ctrl.v @@ -0,0 +1,265 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : hybrid_pipeline_ctrl.v +// Generated : Sept 5, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Control 4x4 block level pipeline for reconstruction +// Receive the 1cycle end_of_xxx signal(combinational) +// Generated the 1cycle trigger_xxx signal +//------------------------------------------------------------------------------------------------- +// Revise log +// 1.April 11,2006 +// Modify the 1cycle trigger_xxx signal from registers to combinational logic to save decoding clock cycles +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module hybrid_pipeline_ctrl (clk,reset_n,mb_num_h,mb_num_v,blk4x4_rec_counter,CodedBlockPatternLuma,CodedBlockPatternChroma, + mb_type_general,slice_data_state,residual_state,TotalCoeff,Is_skip_run_entry,skip_mv_calc, + end_of_one_residual_block,end_of_DCBlk_IQIT,end_of_ACBlk4x4_IQIT,end_of_one_blk4x4_intra,end_of_one_blk4x4_inter, + end_of_one_blk4x4_sum,end_of_MB_DF,disable_DF, + + curr_CBPLuma_IsZero,end_of_MB_DEC,trigger_CAVLC,trigger_blk4x4_intra_pred, + trigger_blk4x4_inter_pred,trigger_blk4x4_rec_sum); + input clk,reset_n; + input [3:0] mb_num_h; + input [3:0] mb_num_v; + input [4:0] blk4x4_rec_counter; + input [3:0] CodedBlockPatternLuma; + input [1:0] CodedBlockPatternChroma; + input [3:0] mb_type_general; + input [3:0] slice_data_state; + input [3:0] residual_state; + input [4:0] TotalCoeff; + input Is_skip_run_entry; + input skip_mv_calc; + input end_of_one_residual_block; + input end_of_DCBlk_IQIT; + input end_of_ACBlk4x4_IQIT; + input end_of_one_blk4x4_intra,end_of_one_blk4x4_inter,end_of_one_blk4x4_sum; + input end_of_MB_DF; + input disable_DF; + + output curr_CBPLuma_IsZero; + output end_of_MB_DEC; + output trigger_CAVLC; + output trigger_blk4x4_intra_pred,trigger_blk4x4_inter_pred; + output trigger_blk4x4_rec_sum; + + //change trigger_blk4x4_intra_pred from combination to reg + reg trigger_CAVLC; //combination + reg trigger_blk4x4_intra_pred; //reg + reg trigger_blk4x4_inter_pred; //reg + reg trigger_blk4x4_rec_sum; //combination + + //CBPLuma only make sense for residual_state == LumaLevel_s + //CBPLuma is derived to help judge whether res_blk4x4_IsAllZero caused by CodedBlockPattern != 4'b1111 + reg curr_CBPLuma_IsZero; + always @ (blk4x4_rec_counter or CodedBlockPatternLuma) + if (blk4x4_rec_counter < 16) + case (blk4x4_rec_counter[3:2]) + 2'b00:curr_CBPLuma_IsZero <= !CodedBlockPatternLuma[0]; + 2'b01:curr_CBPLuma_IsZero <= !CodedBlockPatternLuma[1]; + 2'b10:curr_CBPLuma_IsZero <= !CodedBlockPatternLuma[2]; + 2'b11:curr_CBPLuma_IsZero <= !CodedBlockPatternLuma[3]; + endcase + else + curr_CBPLuma_IsZero <= 0; + //--------------------------------------------------------------------------------- + //signals to trigger: + // 1.4x4 blk CAVLC + // 2.4x4 Intra Prediction + // 3.4x4 Inter Prediction + // 4.4x4 reconstruction sum + // 5.16x16 deblocking filter + // All the trigger_xxx signals are generated by sequential logic + //--------------------------------------------------------------------------------- + + //1. trigger_CAVLC: when reconstruction is dealing with skip_run or zero residual (construction + // only from inter/intra prediction) blocks,CAVLC decoder,as well as whole bitstream parsing FSM, + // needs to be stalled and wait until the reconstruction process of previous + + always @ (slice_data_state or residual_state or mb_type_general[3:2] or CodedBlockPatternLuma + or CodedBlockPatternChroma or end_of_one_residual_block or end_of_DCBlk_IQIT or end_of_one_blk4x4_sum + or blk4x4_rec_counter or TotalCoeff or curr_CBPLuma_IsZero) + // Entry + if (slice_data_state == `residual && residual_state == `rst_residual) + begin + if (mb_type_general[3:2] == 2'b10) //Intra16x16:first block must be DC + trigger_CAVLC <= 1'b1; + else if (CodedBlockPatternLuma[0] == 1'b0) //First 8x8 block has no residuals + trigger_CAVLC <= 1'b0; + else //normal case + trigger_CAVLC <= 1'b1; + end + // End of one DC + else if ((residual_state == `Intra16x16DCLevel_s || residual_state == `ChromaDCLevel_Cb_s || + residual_state == `ChromaDCLevel_Cr_s) && ((end_of_one_residual_block && TotalCoeff == 0)|| end_of_DCBlk_IQIT)) + case (residual_state) + `Intra16x16DCLevel_s: //end of luma DC + trigger_CAVLC <= (CodedBlockPatternLuma[0] == 1'b0)? 1'b0:1'b1; + `ChromaDCLevel_Cb_s: //end of chroma DC Cb,trigger chroma DC Cr now! + trigger_CAVLC <= 1'b1; + `ChromaDCLevel_Cr_s: //end of chroma DC Cr + trigger_CAVLC <= (CodedBlockPatternChroma == 2'b01)? 1'b0:1'b1; + default:trigger_CAVLC <= 1'b0; + endcase + // End of skip or normal + else if (end_of_one_blk4x4_sum) + begin + if (slice_data_state == `skip_run_duration) + trigger_CAVLC <= 1'b0; + else + case (blk4x4_rec_counter) + 0,1,2,4,5,6,8,9,10,12,13,14:trigger_CAVLC <= (curr_CBPLuma_IsZero)? 1'b0:1'b1; + 3 :trigger_CAVLC <= (CodedBlockPatternLuma[1])? 1'b1:1'b0; + 7 :trigger_CAVLC <= (CodedBlockPatternLuma[2])? 1'b1:1'b0; + 11:trigger_CAVLC <= (CodedBlockPatternLuma[3])? 1'b1:1'b0; + 15:trigger_CAVLC <= (CodedBlockPatternChroma == 0)? 1'b0:1'b1; + 23:trigger_CAVLC <= 1'b0; + default:trigger_CAVLC <= (CodedBlockPatternChroma == 2)? 1'b1:1'b0; + endcase + end + else + trigger_CAVLC <= 1'b0; + + //end_of_MB_rec:end of one MB reconstruction + wire end_of_MB_rec; + assign end_of_MB_rec = (blk4x4_rec_counter == 5'd23 && end_of_one_blk4x4_sum == 1'b1)? 1'b1:1'b0; + + //MB_needs_DF: identify whether this MB needs to be deblocking filtered + reg MB_needs_DF; + always @ (posedge clk) + if (reset_n == 1'b0) + MB_needs_DF <= 1'b0; + else if (end_of_MB_DEC == 1'b1 && !disable_DF) + MB_needs_DF <= 1'b1; + else if (end_of_MB_DEC == 1'b1 && disable_DF) + MB_needs_DF <= 1'b0; + //MB_rec_DF_align:latch the first arrival of end_of_MB_rec and end_of_MB_DF + reg MB_rec_DF_align; + always @ (posedge clk) + if (reset_n == 1'b0) + MB_rec_DF_align <= 1'b0; + else if (end_of_MB_DEC) + MB_rec_DF_align <= 1'b0; + else if (MB_needs_DF && (end_of_MB_rec || end_of_MB_DF == 1'b1)) + MB_rec_DF_align <= 1'b1; + + + //end_of_MB_DEC:end of one macroblock decoding (end of both reconstruction and previous MB's deblocking + // (if previous MB needs deblocking)),generated by combinational logic + reg end_of_MB_DEC; + always @ (MB_needs_DF or end_of_MB_rec or end_of_MB_DF or MB_rec_DF_align or mb_num_h or mb_num_v) + if (MB_needs_DF == 1'b1) + begin + if (end_of_MB_rec && end_of_MB_DF) //arrive simultaneously + end_of_MB_DEC <= 1'b1; + else if (MB_rec_DF_align == 1'b1 && (end_of_MB_rec || end_of_MB_DF)) + end_of_MB_DEC <= 1'b1; + else if (mb_num_h == 0 && mb_num_v == 0 && end_of_MB_rec)//first MB has no correspinding DF process + end_of_MB_DEC <= 1'b1; + else + end_of_MB_DEC <= 1'b0; + end + else + end_of_MB_DEC <= (end_of_MB_rec)? 1'b1:1'b0; + + //2. trigger_blk4x4_intra_pred + wire trigger_blk4x4_intra_pred_tmp; + assign trigger_blk4x4_intra_pred_tmp = (mb_type_general[3] && ((slice_data_state == `residual && + residual_state == `rst_residual) || (end_of_one_blk4x4_sum && blk4x4_rec_counter != 23)))? 1'b1:1'b0; + + always @ (posedge clk) + if (reset_n == 1'b0) + trigger_blk4x4_intra_pred <= 1'b0; + else + trigger_blk4x4_intra_pred <= trigger_blk4x4_intra_pred_tmp; + + //3. trigger_blk4x4_inter_pred + always @ (posedge clk) + if (reset_n == 1'b0) + trigger_blk4x4_inter_pred <= 1'b0; + //For skip_run_duration + // 1.trigger inter pred when entering skip_run_duration after mb_skip_run_s state + else if (Is_skip_run_entry) + trigger_blk4x4_inter_pred <= 1'b1; + // 2.trigger inter pred during skip_run_duration + else if (slice_data_state == `skip_run_duration) + begin + if (skip_mv_calc) + trigger_blk4x4_inter_pred <= 1'b1; + else + trigger_blk4x4_inter_pred <= (end_of_one_blk4x4_sum && blk4x4_rec_counter != 23)? 1'b1:1'b0; + end + //For normal case:inside residual_state + // 1.entry + else if (slice_data_state == `residual && residual_state == `rst_residual && !mb_type_general[3]) + trigger_blk4x4_inter_pred <= 1'b1; + // 2.end of normal + else if (end_of_one_blk4x4_sum && blk4x4_rec_counter != 23 && !mb_type_general[3]) + trigger_blk4x4_inter_pred <= 1'b1; + else + trigger_blk4x4_inter_pred <= 1'b0; + + //4. trigger reconstruction sum + // Need to align the output of residual(IQIT) and predition(inter/intra) + wire end_of_one_blk4x4_pred; + wire end_of_one_blk4x4_res; //end of one zero or non-zero AC blk4x4 IQIT (NOT DC!) + reg blk4x4_res_pred_align; + + assign end_of_one_blk4x4_pred = (end_of_one_blk4x4_inter || end_of_one_blk4x4_intra); + assign end_of_one_blk4x4_res = (((residual_state == `Intra16x16ACLevel_s || residual_state == `LumaLevel_s || + residual_state == `ChromaACLevel_Cb_s || residual_state == `ChromaACLevel_Cr_s) && + (end_of_one_residual_block && TotalCoeff == 0)) || end_of_ACBlk4x4_IQIT)? 1'b1:1'b0; + + //align the completion of prediction and residual decoding + always @ (posedge clk) + if (reset_n == 1'b0) + blk4x4_res_pred_align <= 0; + else if (trigger_blk4x4_rec_sum == 1'b1) + blk4x4_res_pred_align <= 1'b0; + else if (end_of_one_blk4x4_res && end_of_one_blk4x4_pred) //arrive simultaneously,no align + blk4x4_res_pred_align <= 1'b0; + else if (end_of_one_blk4x4_res || end_of_one_blk4x4_pred) + blk4x4_res_pred_align <= 1'b1; + + + always @ (slice_data_state or residual_state or curr_CBPLuma_IsZero or blk4x4_res_pred_align or + end_of_one_blk4x4_pred or end_of_one_blk4x4_res) + if (slice_data_state == `skip_run_duration) + trigger_blk4x4_rec_sum <= (end_of_one_blk4x4_pred)? 1'b1:1'b0; + // Normal + else if (residual_state == `Intra16x16ACLevel_s || residual_state == `LumaLevel_s || + residual_state == `ChromaACLevel_Cb_s || residual_state == `ChromaACLevel_Cr_s) + begin + if (curr_CBPLuma_IsZero) + trigger_blk4x4_rec_sum <= (blk4x4_res_pred_align)? 1'b1:end_of_one_blk4x4_pred; + else if (end_of_one_blk4x4_res && end_of_one_blk4x4_pred) //arrive simultaneously + trigger_blk4x4_rec_sum <= 1'b1; + else if ((end_of_one_blk4x4_res || end_of_one_blk4x4_pred) && blk4x4_res_pred_align) + trigger_blk4x4_rec_sum <= 1'b1; + else + trigger_blk4x4_rec_sum <= 1'b0; + end + // zero blocks + else if (residual_state == `Intra16x16ACLevel_0_s || residual_state == `LumaLevel_0_s + || residual_state == `ChromaACLevel_0_s) + trigger_blk4x4_rec_sum <= (end_of_one_blk4x4_pred || blk4x4_res_pred_align)? 1'b1:1'b0; + else + trigger_blk4x4_rec_sum <= 1'b0; + + //5.trigger Deblocking Filter + //assign trigger_MB_DF = (end_of_MB_DEC == 1'b1 && !disable_DF)? 1'b1:1'b0; + +endmodule + + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/level_decoding.v b/demo_chip_rtl/rtl/nova/tags/Start/src/level_decoding.v new file mode 100644 index 0000000..e87a141 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/level_decoding.v @@ -0,0 +1,206 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : level_decoding.v +// Generated : June 9, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Devive the level_prefix,level_suffix,suffixLength,levelSuffixSize,levelCode +// In systemC,levelSuffixSize is decoded @LevelPrefix,in RTL,now changed to @LevelSuffix +// level_suffix[7:0],levelCode[7:0],level[8:0] +// 1. level_abs_tmp[8:0]:|levelCode+2| or |-levelCode-1| | reg +// 2. level_abs [7:0]:level_abs_tmp >> 1 and latched, used for suffixLength calculation | wire +// 3. level_tmp [8:0]:2's complement, equals (levelCode+2)>>1 or (-levelCode-1)>>1 | wire +// 4. level_0 ~ level_15:According to i_level,level_tmp is assigned to level_[i_level] | reg +// level_0 ~ level_15 are 2's complement +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module level_decoding (clk,reset_n,cavlc_decoder_state,heading_one_pos,suffix_length_initialized,i_level, + TotalCoeff,TrailingOnes,BitStream_buffer_output, + levelSuffixSize, + level_0,level_1,level_2, level_3, level_4, level_5, level_6, level_7, + level_8,level_9,level_10,level_11,level_12,level_13,level_14,level_15); + input clk,reset_n; + input [3:0] cavlc_decoder_state; + input [3:0] heading_one_pos; + input suffix_length_initialized; + input [3:0] i_level; + input [4:0] TotalCoeff; + input [1:0] TrailingOnes; + input [15:0] BitStream_buffer_output; + output [3:0] levelSuffixSize; + output [8:0] level_0,level_1,level_2,level_3,level_4,level_5,level_6,level_7; + output [8:0] level_8,level_9,level_10,level_11,level_12,level_13,level_14,level_15; + + reg [3:0] levelSuffixSize; + reg [8:0] level_0,level_1,level_2,level_3,level_4,level_5,level_6,level_7; + reg [8:0] level_8,level_9,level_10,level_11,level_12,level_13,level_14,level_15; + + reg [3:0] level_prefix; + reg [3:0] suffixLength; + reg [11:0] level_suffix; + reg [8:0] levelCode; + reg [8:0] level_tmp; + reg [7:0] level_abs; + + wire [8:0] levelCode_tmp; + + //@LevelPrefix,latch the result + always @ (posedge clk) + if (reset_n == 0) + level_prefix <= 0; + else if (cavlc_decoder_state == `LevelPrefix) + level_prefix <= heading_one_pos; + //@LevelPrefix,latch the result + always @ (posedge clk) + if (reset_n == 0) + suffixLength <= 0; + else if (cavlc_decoder_state == `LevelPrefix) + begin + if (suffix_length_initialized == 1'b0) + suffixLength <= (TotalCoeff > 10 && TrailingOnes < 3)? 4'd1:4'd0; + //Revise log:March 26,2006 + //else if (suffixLength == 0 && ((level_abs > (8'd3 << (suffixLength - 1))) && suffixLength < 6)) + else if (suffixLength == 0 && level_abs > 8'd3) + suffixLength <= 4'd2; + else if (suffixLength == 0) + suffixLength <= 4'd1; + else if ((level_abs > (8'd3 << (suffixLength - 1))) && suffixLength < 6) + suffixLength <= suffixLength + 1; + end + //@LevelSuffix,temporary result + always @ (cavlc_decoder_state or level_prefix or suffixLength) + if (cavlc_decoder_state == `LevelSuffix) + begin + if (level_prefix == 14 && suffixLength == 0) + levelSuffixSize <= 4; + else if (level_prefix == 4'd15) + levelSuffixSize <= 4'd12; + else + levelSuffixSize <= suffixLength; + end + else + levelSuffixSize <= 0; + //@LevelSuffix,temporay result + always @ (cavlc_decoder_state or levelSuffixSize or BitStream_buffer_output) + if (cavlc_decoder_state == `LevelSuffix) + begin + if (levelSuffixSize == 0) + level_suffix <= 0; + else + case (levelSuffixSize) + 1 :level_suffix <= {11'b0,BitStream_buffer_output[15]}; + 2 :level_suffix <= {10'b0,BitStream_buffer_output[15:14]}; + 3 :level_suffix <= {9'b0,BitStream_buffer_output[15:13]}; + 4 :level_suffix <= {8'b0,BitStream_buffer_output[15:12]}; + 5 :level_suffix <= {7'b0,BitStream_buffer_output[15:11]}; + 6 :level_suffix <= {6'b0,BitStream_buffer_output[15:10]}; + 7 :level_suffix <= {5'b0,BitStream_buffer_output[15:9]}; + 8 :level_suffix <= {4'b0,BitStream_buffer_output[15:8]}; + 9 :level_suffix <= {3'b0,BitStream_buffer_output[15:7]}; + 10:level_suffix <= {2'b0,BitStream_buffer_output[15:6]}; + 11:level_suffix <= {1'b0,BitStream_buffer_output[15:5]}; + 12:level_suffix <= BitStream_buffer_output[15:4]; + default:level_suffix <= 0; + endcase + end + else + level_suffix <= 0; + + assign levelCode_tmp = (cavlc_decoder_state == `LevelSuffix)? ((level_prefix << suffixLength) + level_suffix):0; + + always @ (cavlc_decoder_state or level_prefix or suffixLength or i_level or TrailingOnes or levelCode_tmp) + if (cavlc_decoder_state == `LevelSuffix) + begin + if (level_prefix == 15 && suffixLength == 0 && i_level == {2'b0,TrailingOnes} && TrailingOnes < 3) + levelCode <= levelCode_tmp + 17; + else if (level_prefix == 15 && suffixLength == 0) + levelCode <= levelCode_tmp + 15; + else if (i_level == {2'b0,TrailingOnes} && TrailingOnes < 3) + levelCode <= levelCode_tmp + 2; + else + levelCode <= levelCode_tmp; + end + else + levelCode <= 0; + //We need an additional "level_abs" signal here in order to upgrade suffixLength for next codeword,but for + //trailingones,no need to do so since abs(+1/-1) will never greater than (3<<(suffixLength-1)). + + //level_abs_tmp:absolute value of level + reg [8:0] level_abs_tmp; + always @ (cavlc_decoder_state or levelCode) + if (cavlc_decoder_state == `LevelSuffix) + begin + if (levelCode[0] == 1'b0) //even + level_abs_tmp <= levelCode + 2; + else + level_abs_tmp <= levelCode + 1; + end + else + level_abs_tmp <= 0; + + //level_abs:latched absolute value of level,for upgrading of suffixLength + always @ (posedge clk) + if (reset_n == 0) + level_abs <= 0; + else if (cavlc_decoder_state == `LevelSuffix) + level_abs <= level_abs_tmp[8:1]; + + always @ (cavlc_decoder_state or levelCode or level_abs_tmp) + if (cavlc_decoder_state == `LevelSuffix) + begin + if (levelCode[0] == 1'b0) //even + level_tmp <= {1'b0,level_abs_tmp[8:1]}; + else + level_tmp <= {1'b1,~levelCode[8:1]}; + end + else + level_tmp <= 0; + + always @ (posedge clk) + if (reset_n == 0) + begin + level_0 <= 0; level_1 <= 0; level_2 <= 0; level_3 <= 0; + level_4 <= 0; level_5 <= 0; level_6 <= 0; level_7 <= 0; + level_8 <= 0; level_9 <= 0; level_10<= 0; level_11<= 0; + level_12<= 0; level_13<= 0; level_14<= 0; level_15<= 0; + end + else if (cavlc_decoder_state == `TrailingOnesSignFlag) + begin + level_0 <= (BitStream_buffer_output[15] == 0)? 9'b000000001:9'b111111111; + if (TrailingOnes > 1) + level_1 <= (BitStream_buffer_output[14] == 0)? 9'b000000001:9'b111111111; + if (TrailingOnes == 3) + level_2 <= (BitStream_buffer_output[13] == 0)? 9'b000000001:9'b111111111; + end + else if (cavlc_decoder_state == `LevelSuffix) + case (i_level) + 0 :level_0 <= level_tmp; + 1 :level_1 <= level_tmp; + 2 :level_2 <= level_tmp; + 3 :level_3 <= level_tmp; + 4 :level_4 <= level_tmp; + 5 :level_5 <= level_tmp; + 6 :level_6 <= level_tmp; + 7 :level_7 <= level_tmp; + 8 :level_8 <= level_tmp; + 9 :level_9 <= level_tmp; + 10:level_10<= level_tmp; + 11:level_11<= level_tmp; + 12:level_12<= level_tmp; + 13:level_13<= level_tmp; + 14:level_14<= level_tmp; + 15:level_15<= level_tmp; + endcase +endmodule + + + + diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/nC_decoding.v b/demo_chip_rtl/rtl/nova/tags/Start/src/nC_decoding.v new file mode 100644 index 0000000..98fd884 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/nC_decoding.v @@ -0,0 +1,761 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : nC_decoding.v +// Generated : May 18, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Devive the number of none-zero coeff during nC decoding for TotalCoeff & TrailingOnes LUT +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module nC_decoding (clk,reset_n,gclk_end_of_MB_DEC, + cavlc_decoder_state,residual_state,slice_data_state, + mb_num_h,mb_num_v,i8x8,i4x4,i4x4_CbCr,CodedBlockPatternLuma,CodedBlockPatternChroma, + LumaLevel_mbAddrB_dout,ChromaLevel_Cb_mbAddrB_dout,ChromaLevel_Cr_mbAddrB_dout, + end_of_one_residual_block,TotalCoeff, + + nC, + Luma_8x8_AllZeroCoeff_mbAddrA,LumaLevel_mbAddrA, + LumaLevel_CurrMb0,LumaLevel_CurrMb1,LumaLevel_CurrMb2,LumaLevel_CurrMb3, + LumaLevel_mbAddrB_cs_n,LumaLevel_mbAddrB_wr_n,LumaLevel_mbAddrB_rd_addr, + LumaLevel_mbAddrB_wr_addr,LumaLevel_mbAddrB_din, + ChromaLevel_Cb_mbAddrB_cs_n,ChromaLevel_Cb_mbAddrB_wr_n,ChromaLevel_Cb_mbAddrB_rd_addr, + ChromaLevel_Cb_mbAddrB_wr_addr,ChromaLevel_Cb_mbAddrB_din, + ChromaLevel_Cr_mbAddrB_cs_n,ChromaLevel_Cr_mbAddrB_wr_n,ChromaLevel_Cr_mbAddrB_rd_addr, + ChromaLevel_Cr_mbAddrB_wr_addr,ChromaLevel_Cr_mbAddrB_din); + + input clk,reset_n; + input gclk_end_of_MB_DEC; + input [3:0] cavlc_decoder_state; + input [3:0] residual_state; + input [3:0] slice_data_state; + input [3:0] mb_num_h; + input [3:0] mb_num_v; + input [1:0] i8x8,i4x4; + input [1:0] i4x4_CbCr; + input [3:0] CodedBlockPatternLuma; + input [1:0] CodedBlockPatternChroma; + input [19:0] LumaLevel_mbAddrB_dout; + input [9:0] ChromaLevel_Cb_mbAddrB_dout,ChromaLevel_Cr_mbAddrB_dout; + input end_of_one_residual_block; + input [4:0] TotalCoeff; + + output [4:0] nC; + output [1:0] Luma_8x8_AllZeroCoeff_mbAddrA; + output [19:0] LumaLevel_mbAddrA; + output [19:0] LumaLevel_CurrMb0,LumaLevel_CurrMb1,LumaLevel_CurrMb2,LumaLevel_CurrMb3; + output LumaLevel_mbAddrB_cs_n,LumaLevel_mbAddrB_wr_n; + output [3:0] LumaLevel_mbAddrB_rd_addr,LumaLevel_mbAddrB_wr_addr; + output [19:0]LumaLevel_mbAddrB_din; + output ChromaLevel_Cb_mbAddrB_cs_n,ChromaLevel_Cb_mbAddrB_wr_n; + output [3:0] ChromaLevel_Cb_mbAddrB_rd_addr,ChromaLevel_Cb_mbAddrB_wr_addr; + output [9:0] ChromaLevel_Cb_mbAddrB_din; + output ChromaLevel_Cr_mbAddrB_cs_n,ChromaLevel_Cr_mbAddrB_wr_n; + output [3:0] ChromaLevel_Cr_mbAddrB_rd_addr,ChromaLevel_Cr_mbAddrB_wr_addr; + output [9:0] ChromaLevel_Cr_mbAddrB_din; + + reg [4:0] nC; + reg LumaLevel_mbAddrB_cs_n,LumaLevel_mbAddrB_wr_n; + reg [3:0] LumaLevel_mbAddrB_rd_addr,LumaLevel_mbAddrB_wr_addr; + reg [19:0]LumaLevel_mbAddrB_din; + reg ChromaLevel_Cb_mbAddrB_cs_n,ChromaLevel_Cb_mbAddrB_wr_n; + reg [3:0] ChromaLevel_Cb_mbAddrB_rd_addr,ChromaLevel_Cb_mbAddrB_wr_addr; + reg [9:0] ChromaLevel_Cb_mbAddrB_din; + reg ChromaLevel_Cr_mbAddrB_cs_n,ChromaLevel_Cr_mbAddrB_wr_n; + reg [3:0] ChromaLevel_Cr_mbAddrB_rd_addr,ChromaLevel_Cr_mbAddrB_wr_addr; + reg [9:0] ChromaLevel_Cr_mbAddrB_din; + + reg nA_availability,nB_availability; + reg nA_availability_reg,nB_availability_reg; + reg [4:0] nA,nB; + reg [19:0] LumaLevel_mbAddrA; + reg [19:0] LumaLevel_CurrMb0,LumaLevel_CurrMb1,LumaLevel_CurrMb2,LumaLevel_CurrMb3; + reg [19:0] ChromaLevel_Cb_CurrMb; + reg [9:0] ChromaLevel_Cb_mbAddrA; + reg [19:0] ChromaLevel_Cr_CurrMb; + reg [9:0] ChromaLevel_Cr_mbAddrA; + reg [1:0] Luma_8x8_AllZeroCoeff_mbAddrA; + reg [0:21] Luma_8x8_AllZeroCoeff_mbAddrB_reg; + reg [0:1] Luma_8x8_AllZeroCoeff_mbAddrB; + reg Chroma_8x8_AllZeroCoeff_mbAddrA; + reg [10:0] Chroma_8x8_AllZeroCoeff_mbAddrB_reg; + reg Chroma_8x8_AllZeroCoeff_mbAddrB; + + always @ (mb_num_h or Luma_8x8_AllZeroCoeff_mbAddrB_reg) + case (mb_num_h) + 0 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[0:1]; + 1 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[2:3]; + 2 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[4:5]; + 3 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[6:7]; + 4 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[8:9]; + 5 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[10:11]; + 6 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[12:13]; + 7 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[14:15]; + 8 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[16:17]; + 9 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[18:19]; + 10:Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[20:21]; + default:Luma_8x8_AllZeroCoeff_mbAddrB <= 0; + endcase + always @ (mb_num_h or Chroma_8x8_AllZeroCoeff_mbAddrB_reg) + case (mb_num_h) + 0 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[0]; + 1 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[1]; + 2 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[2]; + 3 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[3]; + 4 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[4]; + 5 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[5]; + 6 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[6]; + 7 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[7]; + 8 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[8]; + 9 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[9]; + 10:Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[10]; + default:Chroma_8x8_AllZeroCoeff_mbAddrB <= 0; + endcase + //---------------------------- + //Update 8x8_AllZero registers + //---------------------------- + always @ (posedge gclk_end_of_MB_DEC or negedge reset_n) + if (reset_n == 0) + Luma_8x8_AllZeroCoeff_mbAddrA <= 0; + else if (slice_data_state == `skip_run_duration) + Luma_8x8_AllZeroCoeff_mbAddrA <= 0; + else //update 8x8_AllZero reg when finished one MB residual parsing + begin + Luma_8x8_AllZeroCoeff_mbAddrA[0] <= (CodedBlockPatternLuma[1] == 0)? 1'b0:1'b1; + Luma_8x8_AllZeroCoeff_mbAddrA[1] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1; + end + always @ (posedge gclk_end_of_MB_DEC or negedge reset_n) + if (reset_n == 0) + Luma_8x8_AllZeroCoeff_mbAddrB_reg <= 0; + else if (slice_data_state == `skip_run_duration) + case (mb_num_h) + 0 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[0:1] <= 0; + 1 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[2:3] <= 0; + 2 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[4:5] <= 0; + 3 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[6:7] <= 0; + 4 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[8:9] <= 0; + 5 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[10:11] <= 0; + 6 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[12:13] <= 0; + 7 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[14:15] <= 0; + 8 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[16:17] <= 0; + 9 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[18:19] <= 0; + 10:Luma_8x8_AllZeroCoeff_mbAddrB_reg[20:21] <= 0; + endcase + else //update 8x8_AllZero reg when finished one MB residual parsing + case (mb_num_h) + 0: + begin + Luma_8x8_AllZeroCoeff_mbAddrB_reg [0] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1; + Luma_8x8_AllZeroCoeff_mbAddrB_reg [1] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1; + end + 1: + begin + Luma_8x8_AllZeroCoeff_mbAddrB_reg [2] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1; + Luma_8x8_AllZeroCoeff_mbAddrB_reg [3] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1; + end + 2: + begin + Luma_8x8_AllZeroCoeff_mbAddrB_reg [4] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1; + Luma_8x8_AllZeroCoeff_mbAddrB_reg [5] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1; + end + 3: + begin + Luma_8x8_AllZeroCoeff_mbAddrB_reg [6] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1; + Luma_8x8_AllZeroCoeff_mbAddrB_reg [7] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1; + end + 4: + begin + Luma_8x8_AllZeroCoeff_mbAddrB_reg [8] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1; + Luma_8x8_AllZeroCoeff_mbAddrB_reg [9] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1; + end + 5: + begin + Luma_8x8_AllZeroCoeff_mbAddrB_reg [10] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1; + Luma_8x8_AllZeroCoeff_mbAddrB_reg [11] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1; + end + 6: + begin + Luma_8x8_AllZeroCoeff_mbAddrB_reg [12] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1; + Luma_8x8_AllZeroCoeff_mbAddrB_reg [13] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1; + end + 7: + begin + Luma_8x8_AllZeroCoeff_mbAddrB_reg [14] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1; + Luma_8x8_AllZeroCoeff_mbAddrB_reg [15] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1; + end + 8: + begin + Luma_8x8_AllZeroCoeff_mbAddrB_reg [16] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1; + Luma_8x8_AllZeroCoeff_mbAddrB_reg [17] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1; + end + 9: + begin + Luma_8x8_AllZeroCoeff_mbAddrB_reg [18] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1; + Luma_8x8_AllZeroCoeff_mbAddrB_reg [19] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1; + end + 10: + begin + Luma_8x8_AllZeroCoeff_mbAddrB_reg [20] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1; + Luma_8x8_AllZeroCoeff_mbAddrB_reg [21] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1; + end + endcase + always @ (posedge gclk_end_of_MB_DEC or negedge reset_n) + if (reset_n == 0) + Chroma_8x8_AllZeroCoeff_mbAddrA <= 0; + else if (slice_data_state == `skip_run_duration) + Chroma_8x8_AllZeroCoeff_mbAddrA <= 0; + else //update 8x8_AllZero reg when finished one MB residual parsing + Chroma_8x8_AllZeroCoeff_mbAddrA <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1; + always @ (posedge gclk_end_of_MB_DEC or negedge reset_n) + if (reset_n == 0) + Chroma_8x8_AllZeroCoeff_mbAddrB_reg <= 0; + else if (slice_data_state == `skip_run_duration) + case (mb_num_h) + 0 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[0] <= 0; + 1 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[1] <= 0; + 2 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[2] <= 0; + 3 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[3] <= 0; + 4 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[4] <= 0; + 5 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[5] <= 0; + 6 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[6] <= 0; + 7 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[7] <= 0; + 8 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[8] <= 0; + 9 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[9] <= 0; + 10:Chroma_8x8_AllZeroCoeff_mbAddrB_reg[10] <= 0; + endcase + else if (mb_num_v != 8) + case (mb_num_h) + 0 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[0] <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1; + 1 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[1] <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1; + 2 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[2] <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1; + 3 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[3] <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1; + 4 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[4] <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1; + 5 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[5] <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1; + 6 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[6] <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1; + 7 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[7] <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1; + 8 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[8] <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1; + 9 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[9] <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1; + 10:Chroma_8x8_AllZeroCoeff_mbAddrB_reg[10] <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1; + endcase + //------------------- + //nA_availability + //------------------- + always @ (posedge clk) + if (reset_n == 0) + nA_availability_reg <= 0; + else if (cavlc_decoder_state == `nAnB_decoding_s) + nA_availability_reg <= nA_availability; + always @ (reset_n or cavlc_decoder_state or residual_state or mb_num_h or i8x8 or i4x4 or i4x4_CbCr or nA_availability_reg) + if (reset_n == 1'b0) + nA_availability <= 1'b0; + else if (cavlc_decoder_state == `nAnB_decoding_s) + case (residual_state) + //luma + `Intra16x16DCLevel_s:nA_availability <= (mb_num_h == 0)? 1'b0:1'b1; + `Intra16x16ACLevel_s,`LumaLevel_s: + if ((i8x8 == 0 || i8x8 == 2) && (i4x4 == 0 || i4x4 == 2)) + nA_availability <= (mb_num_h == 0)? 1'b0:1'b1; + else + nA_availability <= 1'b1; + //chroma + `ChromaACLevel_Cb_s,`ChromaACLevel_Cr_s: + nA_availability <= (mb_num_h == 0 && i4x4_CbCr[0] == 0)? 1'b0:1'b1; + default:nA_availability <= 1'b0; + endcase + else + nA_availability <= nA_availability_reg; + //------------------- + //nB_availability + //------------------- + always @ (posedge clk) + if (reset_n == 0) + nB_availability_reg <= 0; + else if (cavlc_decoder_state == `nAnB_decoding_s) + nB_availability_reg <= nB_availability; + always @ (reset_n or cavlc_decoder_state or residual_state or mb_num_v or i8x8 or i4x4 or i4x4_CbCr + or nB_availability_reg) + if (reset_n == 1'b0) + nB_availability <= 1'b0; + else if (cavlc_decoder_state == `nAnB_decoding_s) + case (residual_state) + //luma + `Intra16x16DCLevel_s:nB_availability <= (mb_num_v == 0)? 1'b0:1'b1; + `Intra16x16ACLevel_s,`LumaLevel_s: + if ((i8x8 == 0 || i8x8 == 1) && (i4x4 == 0 || i4x4 == 1)) + nB_availability <= (mb_num_v == 0)? 1'b0:1'b1; + else + nB_availability <= 1'b1; + //chroma + `ChromaACLevel_Cb_s,`ChromaACLevel_Cr_s: + nB_availability <= (mb_num_v == 0 && i4x4_CbCr[1] == 0)? 1'b0:1'b1; + default:nB_availability <= 1'b0; + endcase + else + nB_availability <= nB_availability_reg; + //------------ + //Derive nA + //------------ + always @ (posedge clk) + if (reset_n == 0) + nA <= 0; + else if (cavlc_decoder_state == `nAnB_decoding_s && nA_availability == 1) + case (residual_state) + //luma + `Intra16x16DCLevel_s:nA <= (Luma_8x8_AllZeroCoeff_mbAddrA[0] == 0)? 0:LumaLevel_mbAddrA[4:0]; + `Intra16x16ACLevel_s,`LumaLevel_s: + case (i8x8) + 0: + case (i4x4) + 0:nA <= (Luma_8x8_AllZeroCoeff_mbAddrA[0] == 0)? 0:LumaLevel_mbAddrA[4:0]; + 1:nA <= LumaLevel_CurrMb0[4:0]; + 2:nA <= (Luma_8x8_AllZeroCoeff_mbAddrA[0] == 0)? 0:LumaLevel_mbAddrA[9:5]; + 3:nA <= LumaLevel_CurrMb0[14:10]; + endcase + 1: + case (i4x4) + 0:nA <= (CodedBlockPatternLuma[0] == 0)? 0:LumaLevel_CurrMb0[9:5]; + 1:nA <= LumaLevel_CurrMb1[4:0]; + 2:nA <= (CodedBlockPatternLuma[0] == 0)? 0:LumaLevel_CurrMb0[19:15]; + 3:nA <= LumaLevel_CurrMb1[14:10]; + endcase + 2: + case (i4x4) + 0:nA <= (Luma_8x8_AllZeroCoeff_mbAddrA[1] == 0)? 0:LumaLevel_mbAddrA[14:10]; + 1:nA <= LumaLevel_CurrMb2[4:0]; + 2:nA <= (Luma_8x8_AllZeroCoeff_mbAddrA[1] == 0)? 0:LumaLevel_mbAddrA[19:15]; + 3:nA <= LumaLevel_CurrMb2[14:10]; + endcase + 3: + case (i4x4) + 0:nA <= (CodedBlockPatternLuma[2] == 0)? 0:LumaLevel_CurrMb2[9:5]; + 1:nA <= LumaLevel_CurrMb3[4:0]; + 2:nA <= (CodedBlockPatternLuma[2] == 0)? 0:LumaLevel_CurrMb2[19:15]; + 3:nA <= LumaLevel_CurrMb3[14:10]; + endcase + endcase + //chroma + `ChromaACLevel_Cb_s: + case (i4x4_CbCr) + 2'b00:nA <= (Chroma_8x8_AllZeroCoeff_mbAddrA == 0)? 0:ChromaLevel_Cb_mbAddrA[4:0]; + 2'b10:nA <= (Chroma_8x8_AllZeroCoeff_mbAddrA == 0)? 0:ChromaLevel_Cb_mbAddrA[9:5]; + 2'b01:nA <= (CodedBlockPatternChroma != 2)? 0:ChromaLevel_Cb_CurrMb[4:0]; + 2'b11:nA <= (CodedBlockPatternChroma != 2)? 0:ChromaLevel_Cb_CurrMb[14:10]; + endcase + `ChromaACLevel_Cr_s: + case (i4x4_CbCr) + 2'b00:nA <= (Chroma_8x8_AllZeroCoeff_mbAddrA == 0)? 0:ChromaLevel_Cr_mbAddrA[4:0]; + 2'b10:nA <= (Chroma_8x8_AllZeroCoeff_mbAddrA == 0)? 0:ChromaLevel_Cr_mbAddrA[9:5]; + 2'b01:nA <= (CodedBlockPatternChroma != 2)? 0:ChromaLevel_Cr_CurrMb[4:0]; + 2'b11:nA <= (CodedBlockPatternChroma != 2)? 0:ChromaLevel_Cr_CurrMb[14:10]; + endcase + endcase + else if (cavlc_decoder_state == `nAnB_decoding_s && nA_availability == 0) + nA <= 0; + //------------ + //Derive nB + //------------ + always @ (posedge clk) + if (reset_n == 0) + nB <= 0; + else if (cavlc_decoder_state == `nAnB_decoding_s && nB_availability == 1) + case (residual_state) + `Intra16x16DCLevel_s: + nB <= (Luma_8x8_AllZeroCoeff_mbAddrB[0] == 0)? 0:LumaLevel_mbAddrB_dout[19:15]; + `Intra16x16ACLevel_s,`LumaLevel_s: + case (i8x8) + 0: + case (i4x4) + 0:nB <= (Luma_8x8_AllZeroCoeff_mbAddrB[0] == 0)? 0:LumaLevel_mbAddrB_dout[19:15]; + 1:nB <= (Luma_8x8_AllZeroCoeff_mbAddrB[0] == 0)? 0:LumaLevel_mbAddrB_dout[14:10]; + 2:nB <= LumaLevel_CurrMb0[4:0]; + 3:nB <= LumaLevel_CurrMb0[9:5]; + endcase + 1: + case (i4x4) + 0:nB <= (Luma_8x8_AllZeroCoeff_mbAddrB[1] == 0)? 0:LumaLevel_mbAddrB_dout[9:5]; + 1:nB <= (Luma_8x8_AllZeroCoeff_mbAddrB[1] == 0)? 0:LumaLevel_mbAddrB_dout[4:0]; + 2:nB <= LumaLevel_CurrMb1[4:0]; + 3:nB <= LumaLevel_CurrMb1[9:5]; + endcase + 2: + case (i4x4) + 0:nB <= (CodedBlockPatternLuma[0] == 0)? 0:LumaLevel_CurrMb0[14:10]; + 1:nB <= (CodedBlockPatternLuma[0] == 0)? 0:LumaLevel_CurrMb0[19:15]; + 2:nB <= LumaLevel_CurrMb2[4:0]; + 3:nB <= LumaLevel_CurrMb2[9:5]; + endcase + 3: + case (i4x4) + 0:nB <= (CodedBlockPatternLuma[1] == 0)? 0:LumaLevel_CurrMb1[14:10]; + 1:nB <= (CodedBlockPatternLuma[1] == 0)? 0:LumaLevel_CurrMb1[19:15]; + 2:nB <= LumaLevel_CurrMb3[4:0]; + 3:nB <= LumaLevel_CurrMb3[9:5]; + endcase + endcase + `ChromaACLevel_Cb_s: + case (i4x4_CbCr) + 0:nB <= (Chroma_8x8_AllZeroCoeff_mbAddrB == 0)? 0:ChromaLevel_Cb_mbAddrB_dout[9:5]; + 1:nB <= (Chroma_8x8_AllZeroCoeff_mbAddrB == 0)? 0:ChromaLevel_Cb_mbAddrB_dout[4:0]; + 2:nB <= ChromaLevel_Cb_CurrMb[4:0]; + 3:nB <= ChromaLevel_Cb_CurrMb[9:5]; + endcase + `ChromaACLevel_Cr_s: + case (i4x4_CbCr) + 0:nB <= (Chroma_8x8_AllZeroCoeff_mbAddrB == 0)? 0:ChromaLevel_Cr_mbAddrB_dout[9:5]; + 1:nB <= (Chroma_8x8_AllZeroCoeff_mbAddrB == 0)? 0:ChromaLevel_Cr_mbAddrB_dout[4:0]; + 2:nB <= ChromaLevel_Cr_CurrMb[4:0]; + 3:nB <= ChromaLevel_Cr_CurrMb[9:5]; + endcase + default: nB <= 0; + endcase + else if (cavlc_decoder_state == `nAnB_decoding_s && nB_availability == 0) + nB <= 0; + //------------ + //Derive nC + //------------ + always @ (posedge clk) + if (reset_n == 0) + nC <= 0; + else if (cavlc_decoder_state == `nC_decoding_s) + begin + if (residual_state == `ChromaDCLevel_Cb_s || residual_state == `ChromaDCLevel_Cr_s) + nC <= 5'b11111; + else if (nA_availability == 1 && nB_availability == 1) + nC <= (nA + nB + 1) >> 1; + else + nC <= nA + nB; + end + //----------------------- + //LumaLevel_CurrMb write + //----------------------- + always @ (posedge clk) + if (reset_n == 0) + begin + LumaLevel_CurrMb0 <= 0; LumaLevel_CurrMb1 <= 0; + LumaLevel_CurrMb2 <= 0; LumaLevel_CurrMb3 <= 0; + end + else if (end_of_one_residual_block == 1 && (residual_state == `Intra16x16ACLevel_s || + residual_state == `LumaLevel_s)) + case (i8x8) + 0: + case (i4x4) + 0:LumaLevel_CurrMb0[4:0] <= TotalCoeff; + 1:LumaLevel_CurrMb0[9:5] <= TotalCoeff; + 2:LumaLevel_CurrMb0[14:10] <= TotalCoeff; + 3:LumaLevel_CurrMb0[19:15] <= TotalCoeff; + endcase + 1: + case (i4x4) + 0:LumaLevel_CurrMb1[4:0] <= TotalCoeff; + 1:LumaLevel_CurrMb1[9:5] <= TotalCoeff; + 2:LumaLevel_CurrMb1[14:10] <= TotalCoeff; + 3:LumaLevel_CurrMb1[19:15] <= TotalCoeff; + endcase + 2: + case (i4x4) + 0:LumaLevel_CurrMb2[4:0] <= TotalCoeff; + 1:LumaLevel_CurrMb2[9:5] <= TotalCoeff; + 2:LumaLevel_CurrMb2[14:10] <= TotalCoeff; + 3:LumaLevel_CurrMb2[19:15] <= TotalCoeff; + endcase + 3: + case (i4x4) + 0:LumaLevel_CurrMb3[4:0] <= TotalCoeff; + 1:LumaLevel_CurrMb3[9:5] <= TotalCoeff; + 2:LumaLevel_CurrMb3[14:10] <= TotalCoeff; + 3:LumaLevel_CurrMb3[19:15] <= TotalCoeff; + endcase + endcase + //--------------------------- + //ChromaLevel_Cb_CurrMb write + //--------------------------- + always @ (posedge clk) + if (reset_n == 0) + ChromaLevel_Cb_CurrMb <= 0; + else if (end_of_one_residual_block == 1 && residual_state == `ChromaACLevel_Cb_s) + case (i4x4_CbCr) + 0:ChromaLevel_Cb_CurrMb[4:0] <= TotalCoeff; + 1:ChromaLevel_Cb_CurrMb[9:5] <= TotalCoeff; + 2:ChromaLevel_Cb_CurrMb[14:10] <= TotalCoeff; + 3:ChromaLevel_Cb_CurrMb[19:15] <= TotalCoeff; + endcase + //--------------------------- + //ChromaLevel_Cr_CurrMb write + //--------------------------- + always @ (posedge clk) + if (reset_n == 0) + ChromaLevel_Cr_CurrMb <= 0; + else if (end_of_one_residual_block == 1 && residual_state == `ChromaACLevel_Cr_s) + case (i4x4_CbCr) + 0:ChromaLevel_Cr_CurrMb[4:0] <= TotalCoeff; + 1:ChromaLevel_Cr_CurrMb[9:5] <= TotalCoeff; + 2:ChromaLevel_Cr_CurrMb[14:10] <= TotalCoeff; + 3:ChromaLevel_Cr_CurrMb[19:15] <= TotalCoeff; + endcase + //----------------------- + //LumaLevel_mbAddrA write + //----------------------- + always @ (posedge clk) + if (reset_n == 0) + LumaLevel_mbAddrA <= 0; + else if (end_of_one_residual_block == 1 && (residual_state == `Intra16x16ACLevel_s || residual_state == `LumaLevel_s) && mb_num_h != 10) + case (i8x8) + 1: + case (i4x4) + 1:LumaLevel_mbAddrA[4:0] <= TotalCoeff; + 3:LumaLevel_mbAddrA[9:5] <= TotalCoeff; + endcase + 3: + case (i4x4) + 1:LumaLevel_mbAddrA[14:10] <= TotalCoeff; + 3:LumaLevel_mbAddrA[19:15] <= TotalCoeff; + endcase + endcase + //---------------------------- + //ChromaLevel_Cb_mbAddrA write + //---------------------------- + always @ (posedge clk) + if (reset_n == 0) + ChromaLevel_Cb_mbAddrA <= 0; + else if (end_of_one_residual_block == 1 && residual_state == `ChromaACLevel_Cb_s && mb_num_h != 10) + begin + if (i4x4_CbCr == 1) + ChromaLevel_Cb_mbAddrA[4:0] <= TotalCoeff; + if (i4x4_CbCr == 3) + ChromaLevel_Cb_mbAddrA[9:5] <= TotalCoeff; + end + //---------------------------- + //ChromaLevel_Cr_mbAddrA write + //---------------------------- + always @ (posedge clk) + if (reset_n == 0) + ChromaLevel_Cr_mbAddrA <= 0; + else if (end_of_one_residual_block == 1 && residual_state == `ChromaACLevel_Cr_s && mb_num_h != 10) + begin + if (i4x4_CbCr == 1) + ChromaLevel_Cr_mbAddrA[4:0] <= TotalCoeff; + if (i4x4_CbCr == 3) + ChromaLevel_Cr_mbAddrA[9:5] <= TotalCoeff; + end + //------------------------------ + //LumaLevel_mbAddrB read & write + //------------------------------ + always @ (reset_n or cavlc_decoder_state or residual_state or nB_availability or + Luma_8x8_AllZeroCoeff_mbAddrB or i8x8 or i4x4 or end_of_one_residual_block or + mb_num_v or mb_num_h or CodedBlockPatternLuma or LumaLevel_CurrMb2 or LumaLevel_CurrMb3 or TotalCoeff) + if (reset_n == 0) + begin + LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1; + LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0; + LumaLevel_mbAddrB_din <= 0; + end + //--read-- + else if (cavlc_decoder_state == `nAnB_decoding_s && nB_availability == 1) //read + case (residual_state) + `Intra16x16DCLevel_s: + if (Luma_8x8_AllZeroCoeff_mbAddrB == 0) + begin + LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1; + LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0; + LumaLevel_mbAddrB_din <= 0; + end + else + begin + LumaLevel_mbAddrB_cs_n <= 0; LumaLevel_mbAddrB_wr_n <= 1; + LumaLevel_mbAddrB_rd_addr <= mb_num_h; LumaLevel_mbAddrB_wr_addr <= 0; + LumaLevel_mbAddrB_din <= 0; + end + `Intra16x16ACLevel_s,`LumaLevel_s: + case (i8x8) + 0: + if (Luma_8x8_AllZeroCoeff_mbAddrB[0] == 0) + begin + LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1; + LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0; + LumaLevel_mbAddrB_din <= 0; + end + else + begin + LumaLevel_mbAddrB_cs_n <= 0; LumaLevel_mbAddrB_wr_n <= 1; + LumaLevel_mbAddrB_rd_addr <= mb_num_h; LumaLevel_mbAddrB_wr_addr <= 0; + LumaLevel_mbAddrB_din <= 0; + end + 1: + if (Luma_8x8_AllZeroCoeff_mbAddrB[1] == 0) + begin + LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1; + LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0; + LumaLevel_mbAddrB_din <= 0; + end + else + begin + LumaLevel_mbAddrB_cs_n <= 0; LumaLevel_mbAddrB_wr_n <= 1; + LumaLevel_mbAddrB_rd_addr <= mb_num_h; LumaLevel_mbAddrB_wr_addr <= 0; + LumaLevel_mbAddrB_din <= 0; + end + default: + begin + LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1; + LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0; + LumaLevel_mbAddrB_din <= 0; + end + endcase + default: + begin + LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1; + LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0; + LumaLevel_mbAddrB_din <= 0; + end + endcase + //--write-- + else if ((residual_state == `Intra16x16ACLevel_s || residual_state == `LumaLevel_s) && end_of_one_residual_block == 1 && mb_num_v != 8) + case (CodedBlockPatternLuma[3:2]) + 2'b00: + begin + LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1; + LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0; + LumaLevel_mbAddrB_din <= 0; + end + 2'b10,2'b11: + if (i8x8 == 3 && i4x4 == 3) + begin + LumaLevel_mbAddrB_cs_n <= 0; LumaLevel_mbAddrB_wr_n <= 0; + LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= mb_num_h; + LumaLevel_mbAddrB_din <= (CodedBlockPatternLuma[3:2] == 2'b10)? + {10'b0, LumaLevel_CurrMb3[14:10],TotalCoeff}: + {LumaLevel_CurrMb2[14:10],LumaLevel_CurrMb2[19:15],LumaLevel_CurrMb3[14:10],TotalCoeff}; + end + else + begin + LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1; + LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0; + LumaLevel_mbAddrB_din <= 0; + end + 2'b01: + if (i8x8 == 2 && i4x4 == 3) + begin + LumaLevel_mbAddrB_cs_n <= 0; LumaLevel_mbAddrB_wr_n <= 0; + LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= mb_num_h; + LumaLevel_mbAddrB_din <= {LumaLevel_CurrMb2[14:10],TotalCoeff,10'b0}; + end + else + begin + LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1; + LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0; + LumaLevel_mbAddrB_din <= 0; + end + endcase + else + begin + LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1; + LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0; + LumaLevel_mbAddrB_din <= 0; + end + //----------------------------------- + //ChromaLevel_Cb_mbAddrB read & write + //----------------------------------- + always @ (reset_n or cavlc_decoder_state or residual_state or nB_availability or i4x4_CbCr or ChromaLevel_Cb_CurrMb + or Chroma_8x8_AllZeroCoeff_mbAddrB or mb_num_h or mb_num_v or TotalCoeff or end_of_one_residual_block) + if (reset_n == 0) + begin + ChromaLevel_Cb_mbAddrB_cs_n <= 1; ChromaLevel_Cb_mbAddrB_wr_n <= 1; + ChromaLevel_Cb_mbAddrB_rd_addr <= 0; ChromaLevel_Cb_mbAddrB_wr_addr <= 0; + ChromaLevel_Cb_mbAddrB_din <= 0; + end + //--read-- + else if (cavlc_decoder_state == `nAnB_decoding_s && nB_availability == 1 && + residual_state == `ChromaACLevel_Cb_s) + begin + if (i4x4_CbCr[1] == 0 && Chroma_8x8_AllZeroCoeff_mbAddrB == 1) + begin + ChromaLevel_Cb_mbAddrB_cs_n <= 0; ChromaLevel_Cb_mbAddrB_wr_n <= 1; + ChromaLevel_Cb_mbAddrB_rd_addr <= mb_num_h; ChromaLevel_Cb_mbAddrB_wr_addr <= 0; + ChromaLevel_Cb_mbAddrB_din <= 0; + end + else + begin + ChromaLevel_Cb_mbAddrB_cs_n <= 1; ChromaLevel_Cb_mbAddrB_wr_n <= 1; + ChromaLevel_Cb_mbAddrB_rd_addr <= 0; ChromaLevel_Cb_mbAddrB_wr_addr <= 0; + ChromaLevel_Cb_mbAddrB_din <= 0; + end + end + //--write-- + else if (residual_state == `ChromaACLevel_Cb_s && end_of_one_residual_block == 1 && mb_num_v != 8) + begin + if (i4x4_CbCr == 3) + begin + ChromaLevel_Cb_mbAddrB_cs_n <= 0; ChromaLevel_Cb_mbAddrB_wr_n <= 0; + ChromaLevel_Cb_mbAddrB_rd_addr <= 0; ChromaLevel_Cb_mbAddrB_wr_addr <= mb_num_h; + ChromaLevel_Cb_mbAddrB_din <= {ChromaLevel_Cb_CurrMb[14:10],TotalCoeff}; + end + else + begin + ChromaLevel_Cb_mbAddrB_cs_n <= 1; ChromaLevel_Cb_mbAddrB_wr_n <= 1; + ChromaLevel_Cb_mbAddrB_rd_addr <= 0; ChromaLevel_Cb_mbAddrB_wr_addr <= 0; + ChromaLevel_Cb_mbAddrB_din <= 0; + end + end + else + begin + ChromaLevel_Cb_mbAddrB_cs_n <= 1; ChromaLevel_Cb_mbAddrB_wr_n <= 1; + ChromaLevel_Cb_mbAddrB_rd_addr <= 0; ChromaLevel_Cb_mbAddrB_wr_addr <= 0; + ChromaLevel_Cb_mbAddrB_din <= 0; + end + //----------------------------------- + //ChromaLevel_Cr_mbAddrB read & write + //----------------------------------- + always @ (reset_n or cavlc_decoder_state or residual_state or nB_availability or i4x4_CbCr + or ChromaLevel_Cr_CurrMb or Chroma_8x8_AllZeroCoeff_mbAddrB or mb_num_h or mb_num_v or TotalCoeff + or end_of_one_residual_block) + if (reset_n == 0) + begin + ChromaLevel_Cr_mbAddrB_cs_n <= 1; ChromaLevel_Cr_mbAddrB_wr_n <= 1; + ChromaLevel_Cr_mbAddrB_rd_addr <= 0; ChromaLevel_Cr_mbAddrB_wr_addr <= 0; + ChromaLevel_Cr_mbAddrB_din <= 0; + end + //--read-- + else if (cavlc_decoder_state == `nAnB_decoding_s && nB_availability == 1 && residual_state == `ChromaACLevel_Cr_s) //read + begin + if (i4x4_CbCr[1] == 0 && Chroma_8x8_AllZeroCoeff_mbAddrB == 1) + begin + ChromaLevel_Cr_mbAddrB_cs_n <= 0; ChromaLevel_Cr_mbAddrB_wr_n <= 1; + ChromaLevel_Cr_mbAddrB_rd_addr <= mb_num_h; ChromaLevel_Cr_mbAddrB_wr_addr <= 0; + ChromaLevel_Cr_mbAddrB_din <= 0; + end + else + begin + ChromaLevel_Cr_mbAddrB_cs_n <= 1; ChromaLevel_Cr_mbAddrB_wr_n <= 1; + ChromaLevel_Cr_mbAddrB_rd_addr <= 0; ChromaLevel_Cr_mbAddrB_wr_addr <= 0; + ChromaLevel_Cr_mbAddrB_din <= 0; + end + end + //--write-- + else if (residual_state == `ChromaACLevel_Cr_s && end_of_one_residual_block == 1 && mb_num_v != 8) + begin + if (i4x4_CbCr == 3) + begin + ChromaLevel_Cr_mbAddrB_cs_n <= 0; ChromaLevel_Cr_mbAddrB_wr_n <= 0; + ChromaLevel_Cr_mbAddrB_rd_addr <= 0; ChromaLevel_Cr_mbAddrB_wr_addr <= mb_num_h; + ChromaLevel_Cr_mbAddrB_din <= {ChromaLevel_Cr_CurrMb[14:10],TotalCoeff}; + end + else + begin + ChromaLevel_Cr_mbAddrB_cs_n <= 1; ChromaLevel_Cr_mbAddrB_wr_n <= 1; + ChromaLevel_Cr_mbAddrB_rd_addr <= 0; ChromaLevel_Cr_mbAddrB_wr_addr <= 0; + ChromaLevel_Cr_mbAddrB_din <= 0; + end + end + else + begin + ChromaLevel_Cr_mbAddrB_cs_n <= 1; ChromaLevel_Cr_mbAddrB_wr_n <= 1; + ChromaLevel_Cr_mbAddrB_rd_addr <= 0; ChromaLevel_Cr_mbAddrB_wr_addr <= 0; + ChromaLevel_Cr_mbAddrB_din <= 0; + end +endmodule diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/nova.v b/demo_chip_rtl/rtl/nova/tags/Start/src/nova.v new file mode 100644 index 0000000..377b6e6 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/nova.v @@ -0,0 +1,259 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : nova.v +// Generated : Feb 25,2006 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Top module of nova design, including two main blocks: BitStream controller and reconstruction datapath +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module nova (clk,reset_n,BitStream_buffer_input,BitStream_ram_ren,BitStream_ram_addr, + pic_num,pin_disable_DF,freq_ctrl0,freq_ctrl1, + ext_frame_RAM0_cs_n,ext_frame_RAM0_wr,ext_frame_RAM0_addr,ext_frame_RAM0_data, + ext_frame_RAM1_cs_n,ext_frame_RAM1_wr,ext_frame_RAM1_addr,ext_frame_RAM1_data, + dis_frame_RAM_din, + + slice_header_s6 + ); + input clk,reset_n; + input [15:0] BitStream_buffer_input; + input pin_disable_DF; + input freq_ctrl0; + input freq_ctrl1; + + output BitStream_ram_ren; + output [16:0] BitStream_ram_addr; + output [5:0] pic_num; + //---ext_frame_RAM0--- + output ext_frame_RAM0_cs_n; + output ext_frame_RAM0_wr; + output [13:0] ext_frame_RAM0_addr; + //inout [31:0] ext_frame_RAM0_data; + input [31:0] ext_frame_RAM0_data; + + //---ext_frame_RAM1--- + output ext_frame_RAM1_cs_n; + output ext_frame_RAM1_wr; + output [13:0] ext_frame_RAM1_addr; + //inout [31:0] ext_frame_RAM1_data; + input [31:0] ext_frame_RAM1_data; + + output [31:0] dis_frame_RAM_din; + output slice_header_s6; + + wire trigger_CAVLC; + wire end_of_NonZeroCoeff_CAVLC; + wire end_of_DCBlk_IQIT; + wire end_of_one_blk4x4_sum; + wire end_of_MB_DEC; + wire gclk_end_of_MB_DEC; + wire end_of_one_residual_block; + wire end_of_one_frame; + wire Is_skip_run_entry; + wire Is_skip_run_end; + wire skip_mv_calc; + wire [3:0] mb_type_general; + wire [3:0] mb_num_h; + wire [3:0] mb_num_v; + wire NextMB_IsSkip; + wire LowerMB_IsSkip; + wire [4:0] blk4x4_rec_counter; + wire [3:0] slice_data_state; + wire [3:0] residual_state; + wire [3:0] cavlc_decoder_state; + wire [1:0] Intra16x16_predmode; + wire [63:0] Intra4x4_predmode_CurrMb; + wire [1:0] Intra_chroma_predmode; + wire [5:0] QPy; + wire [5:0] QPc; + wire [1:0] i4x4_CbCr; + wire [3:0] slice_alpha_c0_offset_div2; + wire [3:0] slice_beta_offset_div2; + wire [3:0] CodedBlockPatternLuma; + wire [1:0] CodedBlockPatternChroma; + wire [4:0] TotalCoeff; + wire disable_DF; + wire [8:0] coeffLevel_0, coeffLevel_1, coeffLevel_2,coeffLevel_3, coeffLevel_4, coeffLevel_5; + wire [8:0] coeffLevel_6, coeffLevel_7, coeffLevel_8, coeffLevel_9,coeffLevel_10,coeffLevel_11; + wire [8:0] coeffLevel_12,coeffLevel_13,coeffLevel_14,coeffLevel_15; + wire mv_is16x16; + wire [3:0] mv_below8x8; + wire [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3; + wire [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3; + wire [11:0] bs_V0,bs_V1,bs_V2,bs_V3; + wire [11:0] bs_H0,bs_H1,bs_H2,bs_H3; + wire curr_DC_IsZero; + wire end_of_BS_DEC; + + BitStream_controller BitStream_controller ( + .clk(clk), + .reset_n(reset_n), + .freq_ctrl0(freq_ctrl0), + .freq_ctrl1(freq_ctrl1), + .BitStream_buffer_input(BitStream_buffer_input), + .pin_disable_DF(pin_disable_DF), + .trigger_CAVLC(trigger_CAVLC), + .blk4x4_rec_counter(blk4x4_rec_counter), + .end_of_DCBlk_IQIT(end_of_DCBlk_IQIT), + .end_of_one_blk4x4_sum(end_of_one_blk4x4_sum), + .end_of_MB_DEC(end_of_MB_DEC), + .gclk_end_of_MB_DEC(gclk_end_of_MB_DEC), + .curr_DC_IsZero(curr_DC_IsZero), + + .BitStream_ram_ren(BitStream_ram_ren), + .BitStream_ram_addr(BitStream_ram_addr), + .pic_num(pic_num), + .mb_type_general(mb_type_general), + .mb_num_h(mb_num_h), + .mb_num_v(mb_num_v), + .NextMB_IsSkip(NextMB_IsSkip), + .LowerMB_IsSkip(LowerMB_IsSkip), + .slice_data_state(slice_data_state), + .residual_state(residual_state), + .cavlc_decoder_state(cavlc_decoder_state), + .end_of_one_residual_block(end_of_one_residual_block), + .end_of_NonZeroCoeff_CAVLC(end_of_NonZeroCoeff_CAVLC), + .end_of_one_frame(end_of_one_frame), + .Intra16x16_predmode(Intra16x16_predmode), + .Intra4x4_predmode_CurrMb(Intra4x4_predmode_CurrMb), + .Intra_chroma_predmode(Intra_chroma_predmode), + .QPy(QPy), + .QPc(QPc), + .i4x4_CbCr(i4x4_CbCr), + .slice_alpha_c0_offset_div2(slice_alpha_c0_offset_div2), + .slice_beta_offset_div2(slice_beta_offset_div2), + .CodedBlockPatternLuma(CodedBlockPatternLuma), + .CodedBlockPatternChroma(CodedBlockPatternChroma), + .TotalCoeff(TotalCoeff), + .Is_skip_run_entry(Is_skip_run_entry), + .skip_mv_calc(skip_mv_calc), + .disable_DF(disable_DF), + .coeffLevel_0(coeffLevel_0), + .coeffLevel_1(coeffLevel_1), + .coeffLevel_2(coeffLevel_2), + .coeffLevel_3(coeffLevel_3), + .coeffLevel_4(coeffLevel_4), + .coeffLevel_5(coeffLevel_5), + .coeffLevel_6(coeffLevel_6), + .coeffLevel_7(coeffLevel_7), + .coeffLevel_8(coeffLevel_8), + .coeffLevel_9(coeffLevel_9), + .coeffLevel_10(coeffLevel_10), + .coeffLevel_11(coeffLevel_11), + .coeffLevel_12(coeffLevel_12), + .coeffLevel_13(coeffLevel_13), + .coeffLevel_14(coeffLevel_14), + .coeffLevel_15(coeffLevel_15), + .mv_is16x16(mv_is16x16), + .mv_below8x8(mv_below8x8), + .mvx_CurrMb0(mvx_CurrMb0), + .mvx_CurrMb1(mvx_CurrMb1), + .mvx_CurrMb2(mvx_CurrMb2), + .mvx_CurrMb3(mvx_CurrMb3), + .mvy_CurrMb0(mvy_CurrMb0), + .mvy_CurrMb1(mvy_CurrMb1), + .mvy_CurrMb2(mvy_CurrMb2), + .mvy_CurrMb3(mvy_CurrMb3), + .end_of_BS_DEC(end_of_BS_DEC), + .bs_V0(bs_V0), + .bs_V1(bs_V1), + .bs_V2(bs_V2), + .bs_V3(bs_V3), + .bs_H0(bs_H0), + .bs_H1(bs_H1), + .bs_H2(bs_H2), + .bs_H3(bs_H3), + + .slice_header_s6(slice_header_s6) + ); + reconstruction reconstruction ( + .clk(clk), + .reset_n(reset_n), + .mb_type_general(mb_type_general), + .mb_num_h(mb_num_h), + .mb_num_v(mb_num_v), + .NextMB_IsSkip(NextMB_IsSkip), + .LowerMB_IsSkip(LowerMB_IsSkip), + .slice_data_state(slice_data_state), + .residual_state(residual_state), + .cavlc_decoder_state(cavlc_decoder_state), + .end_of_one_residual_block(end_of_one_residual_block), + .end_of_NonZeroCoeff_CAVLC(end_of_NonZeroCoeff_CAVLC), + .end_of_one_frame(end_of_one_frame), + .Intra16x16_predmode(Intra16x16_predmode), + .Intra4x4_predmode_CurrMb(Intra4x4_predmode_CurrMb), + .Intra_chroma_predmode(Intra_chroma_predmode), + .QPy(QPy), + .QPc(QPc), + .i4x4_CbCr(i4x4_CbCr), + .slice_alpha_c0_offset_div2(slice_alpha_c0_offset_div2), + .slice_beta_offset_div2(slice_beta_offset_div2), + .CodedBlockPatternLuma(CodedBlockPatternLuma), + .CodedBlockPatternChroma(CodedBlockPatternChroma), + .TotalCoeff(TotalCoeff), + .Is_skip_run_entry(Is_skip_run_entry), + .skip_mv_calc(skip_mv_calc), + .disable_DF(disable_DF), + .coeffLevel_0(coeffLevel_0), + .coeffLevel_1(coeffLevel_1), + .coeffLevel_2(coeffLevel_2), + .coeffLevel_3(coeffLevel_3), + .coeffLevel_4(coeffLevel_4), + .coeffLevel_5(coeffLevel_5), + .coeffLevel_6(coeffLevel_6), + .coeffLevel_7(coeffLevel_7), + .coeffLevel_8(coeffLevel_8), + .coeffLevel_9(coeffLevel_9), + .coeffLevel_10(coeffLevel_10), + .coeffLevel_11(coeffLevel_11), + .coeffLevel_12(coeffLevel_12), + .coeffLevel_13(coeffLevel_13), + .coeffLevel_14(coeffLevel_14), + .coeffLevel_15(coeffLevel_15), + .mv_is16x16(mv_is16x16), + .mv_below8x8(mv_below8x8), + .mvx_CurrMb0(mvx_CurrMb0), + .mvx_CurrMb1(mvx_CurrMb1), + .mvx_CurrMb2(mvx_CurrMb2), + .mvx_CurrMb3(mvx_CurrMb3), + .mvy_CurrMb0(mvy_CurrMb0), + .mvy_CurrMb1(mvy_CurrMb1), + .mvy_CurrMb2(mvy_CurrMb2), + .mvy_CurrMb3(mvy_CurrMb3), + .end_of_BS_DEC(end_of_BS_DEC), + .bs_V0(bs_V0), + .bs_V1(bs_V1), + .bs_V2(bs_V2), + .bs_V3(bs_V3), + .bs_H0(bs_H0), + .bs_H1(bs_H1), + .bs_H2(bs_H2), + .bs_H3(bs_H3), + + .trigger_CAVLC(trigger_CAVLC), + .blk4x4_rec_counter(blk4x4_rec_counter), + .end_of_DCBlk_IQIT(end_of_DCBlk_IQIT), + .end_of_one_blk4x4_sum(end_of_one_blk4x4_sum), + .end_of_MB_DEC(end_of_MB_DEC), + .gclk_end_of_MB_DEC(gclk_end_of_MB_DEC), + .curr_DC_IsZero(curr_DC_IsZero), + .ext_frame_RAM0_cs_n(ext_frame_RAM0_cs_n), + .ext_frame_RAM0_wr(ext_frame_RAM0_wr), + .ext_frame_RAM0_addr(ext_frame_RAM0_addr), + .ext_frame_RAM0_data(ext_frame_RAM0_data), + .ext_frame_RAM1_cs_n(ext_frame_RAM1_cs_n), + .ext_frame_RAM1_wr(ext_frame_RAM1_wr), + .ext_frame_RAM1_addr(ext_frame_RAM1_addr), + .ext_frame_RAM1_data(ext_frame_RAM1_data), + .dis_frame_RAM_din(dis_frame_RAM_din) + ); + +endmodule diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/nova_defines.v b/demo_chip_rtl/rtl/nova/tags/Start/src/nova_defines.v new file mode 100644 index 0000000..e16f5d0 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/nova_defines.v @@ -0,0 +1,309 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : nova_defines.v +// Generated : April 20,2008 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Global parameters of nova +//------------------------------------------------------------------------------------------------- + +//------------------------------------------------------------------------------------------------- +//BitStream_controller parameters +//------------------------------------------------------------------------------------------------- + +//---Beha_BitStream_ram.v--- +`define Beha_Bitstream_ram_size 131071 //Beha_Bitstream_ram size + +//bitstream_gclk_gen +//Assume running at 1.5MHz,so 50,000 cycles is needed for each frame +//1)50,000 cycles are not enough for foreman300,8th frame.So increase to 51,000 cycles +//2)51,000 cycles are not enough for foreman300,11th frame.So increase to 51,500 cycles +//3)51,500 cycles are not enough for foreman300,38th frame.So increase to 52,000 cycles +//4)52,000 cycles are not enough for foreman300,66th frame.So increase to 52,500 cycles +//5)52,500 cycles are not enough for foreman300,138th frame.So increase to 55,000 cycles +//6)55,000 cycles are not enough for foreman300,223th frame.So increase to 56,000 cycles +//After ext_frame_RAM is changed from async read (the FPGA does not support async read mode)to sync read, +//the cycles required to decode each frame increased +//7)56,000 cycles are not enough for foreman300,138th frame.So increase to 56,500 cycles +//8)56,500 cycles are not enough for foreman300,223th frame.So increase to 57,300 cycles +`define cycles_per_frame0 17'd45000 +`define cycles_per_frame1 17'd50000 //fast enough for akiyo300 +`define cycles_per_frame2 17'd57300 //preferred frequency for most critical sequence:foreman300 +`define cycles_per_frame3 17'd70000 + +//---pc_decoding--- +`define rst_consumed_bits_sel 3'b000 +`define exp_golomb 3'b001 +`define fixed_length 3'b011 +`define dependent_variable 3'b010 +`define cavlc_consumed 3'b110 +`define trailing_bits 3'b111 +`define pcm_alignment 3'b101 + +//---syntax_decoding--- +//mb_type_general +`define MB_Inter16x16 4'b0000 +`define MB_Inter16x8 4'b0001 +`define MB_Inter8x16 4'b0010 +`define MB_P_8x8 4'b0011 +`define MB_P_8x8ref0 4'b0100 +`define MB_P_skip 4'b0101 +`define MB_I_PCM 4'b0110 +`define MB_type_reserved0 4'b0111 +`define MB_Intra16x16_CBPChroma0 4'b1000 +`define MB_Intra16x16_CBPChroma1 4'b1001 +`define MB_Intra16x16_CBPChroma2 4'b1010 +`define MB_type_reserved1 4'b1011 +`define MB_Intra4x4 4'b1100 +`define MB_type_reserved2 4'b1101 +`define MB_type_reserved3 4'b1110 +`define MB_type_rst 4'b1111 + +//MBTypeGen_mbAddrA,MBTypeGen_mbAddrB_reg +`define MB_addrA_addrB_Inter 2'b00 +`define MB_addrA_addrB_P_skip 2'b01 +`define MB_addrA_addrB_Intra16x16 2'b10 +`define MB_addrA_addrB_Intra4x4 2'b11 + +//MBTypeGen_mbAddrD +`define MB_addrD_Inter_P_skip 1'b0 +`define MB_addrD_Intra 1'b1 + +//Gray-encoded FSM states to reduce power consumption during state switching +`define rst_parser 2'b00 +`define start_code_prefix 2'b01 +`define nal_unit 2'b11 + +`define rst_nal_unit 3'b000 +`define forbidden_zero_bit_2_nal_unit_type 3'b001 +`define slice_layer_non_IDR_rbsp 3'b011 +`define slice_layer_IDR_rbsp 3'b010 +`define seq_parameter_set_rbsp 3'b110 +`define pic_parameter_set_rbsp 3'b111 +`define rbsp_trailing_one_bit 3'b101 +`define rbsp_trailing_zero_bits 3'b100 + +`define rst_slice_layer_wo_partitioning 2'b00 +`define slice_header 2'b01 +`define slice_data 2'b11 + +`define rst_seq_parameter_set 4'b0000 +`define fixed_header 4'b0001 +`define level_idc_s 4'b0011 +`define seq_parameter_set_id_sps_s 4'b0010 +`define log2_max_frame_num_minus4_s 4'b0110 +`define pic_order_cnt_type_s 4'b0111 +`define log2_max_pic_order_cnt_lsb_minus4_s 4'b0101 +`define num_ref_frames_s 4'b0100 +`define gaps_in_frame_num_value_allowed_flag_s 4'b1100 +`define pic_width_in_mbs_minus1_s 4'b1101 +`define pic_height_in_map_units_minus1_s 4'b1111 +`define frame_mbs_only_flag_2_frame_cropping_flag 4'b1110 +`define vui_parameter_present_flag_s 4'b1010 + +`define rst_pic_parameter_set 4'b0000 +`define pic_parameter_set_id_pps_s 4'b0001 +`define seq_parameter_set_id_pps_s 4'b0011 +`define entropy_coding_mode_flag_2_pic_order_present_flag 4'b0010 +`define num_slice_groups_minus1_s 4'b0110 +`define num_ref_idx_l0_active_minus1_pps_s 4'b0111 +`define num_ref_idx_l1_active_minus1_pps_s 4'b0101 +`define weighted_pred_flag_2_weighted_bipred_idc 4'b0100 +`define pic_init_qp_minus26_s 4'b1100 +`define pic_init_qs_minus26_s 4'b1101 +`define chroma_qp_index_offset_s 4'b1111 +`define deblocking_filter_control_2_redundant_pic_cnt_present_flag 4'b1110 + +`define rst_slice_header 4'b0000 +`define first_mb_in_slice_s 4'b0001 +`define slice_type_s 4'b0011 +`define pic_parameter_set_id_slice_header_s 4'b0010 +`define frame_num_s 4'b0110 +`define idr_pic_id_s 4'b0111 +`define pic_order_cnt_lsb_s 4'b0101 +`define num_ref_idx_active_override_flag_s 4'b0100 +`define num_ref_idx_l0_active_minus1_slice_header_s 4'b1100 +`define ref_pic_list_reordering 4'b1101 +`define dec_ref_pic_marking 4'b1111 +`define slice_qp_delta_s 4'b1110 +`define disable_deblocking_filter_idc_s 4'b1010 +`define slice_alpha_c0_offset_div2_s 4'b1011 +`define slice_beta_offset_div2_s 4'b1001 + +//ref_pic_list_reordering_state +`define rst_ref_pic_list_reordering 3'b000 +`define ref_pic_list_reordering_flag_l0_s 3'b001 + +//dec_ref_pic_marking_state +`define rst_dec_ref_pic_marking 2'b00 +`define no_output_of_prior_pics_flag_2_long_term_reference_flag 2'b01 +`define adaptive_ref_pic_marking_mode_flag_s 2'b11 + +`define rst_slice_data 4'b0000 +`define mb_skip_run_s 4'b0001 +`define skip_run_duration 4'b0011 +`define mb_type_s 4'b0010 +`define pcm_alignment_zero_bit_s 4'b0110 +`define pcm_byte_s 4'b0111 +`define sub_mb_pred 4'b0101 +`define mb_pred 4'b0100 +`define coded_block_pattern_s 4'b1100 +`define mb_qp_delta_s 4'b1101 +`define residual 4'b1111 +`define mb_num_update 4'b1110 + +//mb_pred_state +`define rst_mb_pred 3'b000 +`define prev_intra4x4_pred_mode_flag_s 3'b001 +`define rem_intra4x4_pred_mode_s 3'b011 +`define intra_chroma_pred_mode_s 3'b010 +`define ref_idx_l0_s 3'b110 +`define mvd_l0_s 3'b111 + +//sub_mb_pred_state +`define rst_sub_mb_pred 2'b00 +`define sub_mb_type_s 2'b01 +`define sub_ref_idx_l0_s 2'b11 +`define sub_mvd_l0_s 2'b10 + +`define rst_residual 4'b0000 +`define Intra16x16DCLevel_s 4'b0001 +`define Intra16x16ACLevel_s 4'b0011 +`define Intra16x16ACLevel_0_s 4'b0010 +`define LumaLevel_s 4'b0110 +`define LumaLevel_0_s 4'b0111 +`define ChromaDCLevel_Cb_s 4'b0101 +`define ChromaDCLevel_Cr_s 4'b0100 +`define ChromaACLevel_Cb_s 4'b1100 +`define ChromaACLevel_Cr_s 4'b1101 +`define ChromaACLevel_0_s 4'b1110 + +`define rst_cavlc_decoder 4'b0000 +`define nAnB_decoding_s 4'b0001 +`define nC_decoding_s 4'b0011 +`define NumCoeffTrailingOnes_LUT 4'b0010 +`define TrailingOnesSignFlag 4'b0110 +`define LevelPrefix 4'b0111 +`define LevelSuffix 4'b0101 +`define total_zeros_LUT 4'b0100 +`define run_before_LUT 4'b1100 +`define RunOfZeros 4'b1101 +`define LevelRunCombination 4'b1111 + +//---LumaLevel_mbAddrB_RF--- +`define LumaLevel_mbAddrB_RF_data_width 20 +`define LumaLevel_mbAddrB_RF_data_depth 11 +//---ChromaLevel_Cb_mbAddrB_RF--- +`define ChromaLevel_Cb_mbAddrB_RF_data_width 10 +`define ChromaLevel_Cb_mbAddrB_RF_data_depth 11 +//---ChromaLevel_Cr_mbAddrB_RF--- +`define ChromaLevel_Cr_mbAddrB_RF_data_width 10 +`define ChromaLevel_Cr_mbAddrB_RF_data_depth 11 + +//---Intra4x4_PredMode_RF--- +`define Intra4x4_PredMode_RF_data_width 16 +`define Intra4x4_PredMode_RF_data_depth 11 + +//---mvx_mbAddrB_RF--- +`define mvx_mbAddrB_RF_data_width 32 +`define mvx_mbAddrB_RF_data_depth 11 +//---mvy_mbAddrB_RF--- +`define mvy_mbAddrB_RF_data_width 32 +`define mvy_mbAddrB_RF_data_depth 11 +//---mvx_mbAddrB_RF--- +`define mvx_mbAddrC_RF_data_width 8 +`define mvx_mbAddrC_RF_data_depth 10 +//---mvy_mbAddrB_RF--- +`define mvy_mbAddrC_RF_data_width 8 +`define mvy_mbAddrC_RF_data_depth 10 + +//------------------------------------------------------------------------------------------------- +//Intra prediction parameters +//------------------------------------------------------------------------------------------------- + +//---Intra_mbAddrB_RAM--- +`define Intra_mbAddrB_RAM_data_width 32 +`define Intra_mbAddrB_RAM_data_depth 88 + +//---Intra_pred_PE,Intra_pred_pipeline,Intra_pred_reg_ctrl--- +`define Intra4x4_Vertical 4'b0000 +`define Intra4x4_Horizontal 4'b0001 +`define Intra4x4_DC 4'b0010 +`define Intra4x4_Diagonal_Down_Left 4'b0011 +`define Intra4x4_Diagonal_Down_Right 4'b0100 +`define Intra4x4_Vertical_Right 4'b0101 +`define Intra4x4_Horizontal_Down 4'b0110 +`define Intra4x4_Vertical_Left 4'b0111 +`define Intra4x4_Horizontal_Up 4'b1000 + +`define Intra16x16_Vertical 2'b00 +`define Intra16x16_Horizontal 2'b01 +`define Intra16x16_DC 2'b10 +`define Intra16x16_Plane 2'b11 + +`define Intra_chroma_DC 2'b00 +`define Intra_chroma_Horizontal 2'b01 +`define Intra_chroma_Vertical 2'b10 +`define Intra_chroma_Plane 2'b11 + +//------------------------------------------------------------------------------------------------- +//Inter prediction parameters +//------------------------------------------------------------------------------------------------- + +//---Inter_pred_LPE,Inter_pred_pipeline,Inter_pred_reg_ctrl,Inter_pred_sliding_window--- +`define pos_Int 4'b0000 +`define pos_a 4'b0100 +`define pos_b 4'b1000 +`define pos_c 4'b1100 +`define pos_d 4'b0001 +`define pos_e 4'b0101 +`define pos_f 4'b1001 +`define pos_g 4'b1101 +`define pos_h 4'b0010 +`define pos_i 4'b0110 +`define pos_j 4'b1010 +`define pos_k 4'b1110 +`define pos_n 4'b0011 +`define pos_p 4'b0111 +`define pos_q 4'b1011 +`define pos_r 4'b1111 + +//---Inter_pred_pipeline +`define pic_width 8'd176 +`define pic_height 8'd144 +`define half_pic_width 7'd88 +`define half_pic_height 7'd72 + +//------------------------------------------------------------------------------------------------- +//Deblocking filter parameters +//------------------------------------------------------------------------------------------------- + +//---bs_decoding--- +`define I8x8 2'b00 //size of inter prediction partitions +`define I16x8 2'b01 +`define I8x16 2'b10 +`define I16x16 2'b11 + +//---DF_mbAddrA_RAM--- +`define DF_mbAddrA_RAM_data_width 32 +`define DF_mbAddrA_RAM_data_depth 32 + +//---DF_mbAddrB_RAM--- +`define DF_mbAddrB_RAM_data_width 32 +`define DF_mbAddrB_RAM_data_depth 352 + +//---rec_DF_RAM0--- +`define rec_DF_RAM0_data_width 32 +`define rec_DF_RAM0_data_depth 96 + +//---rec_DF_RAM1--- +`define rec_DF_RAM1_data_width 32 +`define rec_DF_RAM1_data_depth 96 + +//------------------------------------------------------------------------------------------------- +//Hybrid pipeline control parameters +//------------------------------------------------------------------------------------------------- + diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/nova_tb.v b/demo_chip_rtl/rtl/nova/tags/Start/src/nova_tb.v new file mode 100644 index 0000000..b7fbcd8 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/nova_tb.v @@ -0,0 +1,108 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : nova_tb.v +// Generated : March 13,2006 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Testbench for nova +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module nova_tb; + + reg clk; + reg reset_n; + reg pin_disable_DF; + reg freq_ctrl0; + reg freq_ctrl1; + + wire BitStream_ram_ren; + wire [16:0] BitStream_ram_addr; + wire [15:0] BitStream_buffer_input; + wire [5:0] pic_num; + wire [6:0] mb_num; + + wire [13:0] ext_frame_RAM0_addr; + wire [31:0] ext_frame_RAM0_data; + wire [13:0] ext_frame_RAM1_addr; + wire [31:0] ext_frame_RAM1_data; + wire [31:0] dis_frame_RAM_din; + + wire [15:0] temp; + assign temp = dis_frame_RAM_din[15:0]; + + //for debug only + wire slice_header_s6; + + Beha_BitStream_ram Beha_BitStream_ram ( + .clk(clk), + .BitStream_ram_ren(BitStream_ram_ren), + .BitStream_ram_addr(BitStream_ram_addr), + .BitStream_ram_data(BitStream_buffer_input) + ); + ext_frame_RAM0_wrapper ext_frame_RAM0_wrapper ( + .clk(clk), + .reset_n(reset_n), + .ext_frame_RAM0_cs_n(ext_frame_RAM0_cs_n), + .ext_frame_RAM0_wr(ext_frame_RAM0_wr), + .ext_frame_RAM0_addr(ext_frame_RAM0_addr), + .dis_frame_RAM_din(dis_frame_RAM_din), + .ext_frame_RAM0_data(ext_frame_RAM0_data), + .pic_num(pic_num), + .slice_header_s6(slice_header_s6) + ); + ext_frame_RAM1_wrapper ext_frame_RAM1_wrapper ( + .clk(clk), + .reset_n(reset_n), + .ext_frame_RAM1_cs_n(ext_frame_RAM1_cs_n), + .ext_frame_RAM1_wr(ext_frame_RAM1_wr), + .ext_frame_RAM1_addr(ext_frame_RAM1_addr), + .dis_frame_RAM_din(dis_frame_RAM_din), + .ext_frame_RAM1_data(ext_frame_RAM1_data), + .pic_num(pic_num), + .slice_header_s6(slice_header_s6) + ); + nova nova ( + .clk(clk), + .reset_n(reset_n), + .freq_ctrl0(freq_ctrl0), + .freq_ctrl1(freq_ctrl1), + .BitStream_buffer_input(BitStream_buffer_input), + .BitStream_ram_ren(BitStream_ram_ren), + .BitStream_ram_addr(BitStream_ram_addr), + .pic_num(pic_num), + .pin_disable_DF(pin_disable_DF), + .ext_frame_RAM0_cs_n(ext_frame_RAM0_cs_n), + .ext_frame_RAM0_wr(ext_frame_RAM0_wr), + .ext_frame_RAM0_addr(ext_frame_RAM0_addr), + .ext_frame_RAM0_data(ext_frame_RAM0_data), + .ext_frame_RAM1_cs_n(ext_frame_RAM1_cs_n), + .ext_frame_RAM1_wr(ext_frame_RAM1_wr), + .ext_frame_RAM1_addr(ext_frame_RAM1_addr), + .ext_frame_RAM1_data(ext_frame_RAM1_data), + .dis_frame_RAM_din(dis_frame_RAM_din), + .slice_header_s6(slice_header_s6) + ); + + initial + begin + clk = 1'b1; + reset_n = 1'b1; + pin_disable_DF = 1'b0; + freq_ctrl0 = 1'b0; + freq_ctrl1 = 1'b1; + #1100 reset_n = 1'b0; + #1000 reset_n = 1'b1; + end + + always + #340 clk = ~clk; + +endmodule diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/pc_decoding.v b/demo_chip_rtl/rtl/nova/tags/Start/src/pc_decoding.v new file mode 100644 index 0000000..48a658d --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/pc_decoding.v @@ -0,0 +1,204 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : pc_decoding.v +// Generated : June 6, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Decoding program counter for bitstream_buffer +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module pc_decoding (clk,reset_n,parser_state,nal_unit_state,slice_header_state,ref_pic_list_reordering_state, + dec_ref_pic_marking_state,slice_data_state,sub_mb_pred_state,mb_pred_state,seq_parameter_set_state, + pic_parameter_set_state,exp_golomb_len,dependent_variable_len,cavlc_consumed_bits_len, + pc); + input clk,reset_n; + input [1:0] parser_state; + input [2:0] nal_unit_state; + input [3:0] slice_header_state; + input [2:0] ref_pic_list_reordering_state; + input [1:0] dec_ref_pic_marking_state; + input [3:0] slice_data_state; + input [1:0] sub_mb_pred_state; + input [2:0] mb_pred_state; + input [3:0] seq_parameter_set_state; + input [3:0] pic_parameter_set_state; + input [3:0] exp_golomb_len; + input [3:0] dependent_variable_len; + input [4:0] cavlc_consumed_bits_len; + output [6:0] pc; + reg [6:0] pc; + + reg [2:0] consumed_bits_sel; + reg [4:0] FixedLen; + + always @ (reset_n or parser_state or nal_unit_state or slice_header_state or ref_pic_list_reordering_state or + dec_ref_pic_marking_state or slice_data_state or sub_mb_pred_state or mb_pred_state or + seq_parameter_set_state or pic_parameter_set_state) + if (reset_n == 0) + consumed_bits_sel <= `rst_consumed_bits_sel; + else if (parser_state == `start_code_prefix) + consumed_bits_sel <= `fixed_length; + else if (nal_unit_state == `forbidden_zero_bit_2_nal_unit_type) + consumed_bits_sel <= `fixed_length; + else if (slice_header_state != `rst_slice_header) + case (slice_header_state) + `first_mb_in_slice_s :consumed_bits_sel <= `exp_golomb; + `slice_type_s :consumed_bits_sel <= `exp_golomb; + `pic_parameter_set_id_slice_header_s :consumed_bits_sel <= `exp_golomb; + `frame_num_s :consumed_bits_sel <= `dependent_variable; + `idr_pic_id_s :consumed_bits_sel <= `exp_golomb; + `pic_order_cnt_lsb_s :consumed_bits_sel <= `dependent_variable; + `num_ref_idx_active_override_flag_s :consumed_bits_sel <= `fixed_length; + `num_ref_idx_l0_active_minus1_slice_header_s:consumed_bits_sel <= `exp_golomb; + `ref_pic_list_reordering: + case (ref_pic_list_reordering_state) + `ref_pic_list_reordering_flag_l0_s:consumed_bits_sel <= `fixed_length; + default :consumed_bits_sel <= `rst_consumed_bits_sel; + endcase + `dec_ref_pic_marking: + case (dec_ref_pic_marking_state) + `no_output_of_prior_pics_flag_2_long_term_reference_flag:consumed_bits_sel <= `fixed_length; + `adaptive_ref_pic_marking_mode_flag_s :consumed_bits_sel <= `fixed_length; + default :consumed_bits_sel <= `rst_consumed_bits_sel; + endcase + `slice_qp_delta_s :consumed_bits_sel <= `exp_golomb; + `disable_deblocking_filter_idc_s:consumed_bits_sel <= `exp_golomb; + `slice_alpha_c0_offset_div2_s :consumed_bits_sel <= `exp_golomb; + `slice_beta_offset_div2_s :consumed_bits_sel <= `exp_golomb; + default :consumed_bits_sel <= `rst_consumed_bits_sel; + endcase + else if (slice_data_state != `rst_slice_data) + case (slice_data_state) + `mb_skip_run_s :consumed_bits_sel <= `exp_golomb; + `mb_type_s :consumed_bits_sel <= `exp_golomb; + `pcm_alignment_zero_bit_s:consumed_bits_sel <= `exp_golomb; + `pcm_byte_s :consumed_bits_sel <= `pcm_alignment; + `sub_mb_pred: + case (sub_mb_pred_state) + `rst_sub_mb_pred:consumed_bits_sel <= `rst_consumed_bits_sel; + default :consumed_bits_sel <= `exp_golomb; + endcase + `mb_pred: + case (mb_pred_state) + `prev_intra4x4_pred_mode_flag_s:consumed_bits_sel <= `fixed_length; + `rem_intra4x4_pred_mode_s :consumed_bits_sel <= `fixed_length; + `intra_chroma_pred_mode_s :consumed_bits_sel <= `exp_golomb; + `ref_idx_l0_s :consumed_bits_sel <= `exp_golomb; + `mvd_l0_s :consumed_bits_sel <= `exp_golomb; + default :consumed_bits_sel <= `rst_consumed_bits_sel; + endcase + `coded_block_pattern_s:consumed_bits_sel <= `exp_golomb; + `mb_qp_delta_s :consumed_bits_sel <= `exp_golomb; + `residual :consumed_bits_sel <= `cavlc_consumed; + default :consumed_bits_sel <= `rst_consumed_bits_sel; + endcase + else if (seq_parameter_set_state != `rst_seq_parameter_set) + case (seq_parameter_set_state) + `fixed_header :consumed_bits_sel <= `fixed_length; + `level_idc_s :consumed_bits_sel <= `fixed_length; + `seq_parameter_set_id_sps_s :consumed_bits_sel <= `exp_golomb; + `log2_max_frame_num_minus4_s :consumed_bits_sel <= `exp_golomb; + `pic_order_cnt_type_s :consumed_bits_sel <= `exp_golomb; + `log2_max_pic_order_cnt_lsb_minus4_s :consumed_bits_sel <= `exp_golomb; + `num_ref_frames_s :consumed_bits_sel <= `exp_golomb; + `gaps_in_frame_num_value_allowed_flag_s :consumed_bits_sel <= `fixed_length; + `pic_width_in_mbs_minus1_s :consumed_bits_sel <= `exp_golomb; + `pic_height_in_map_units_minus1_s :consumed_bits_sel <= `exp_golomb; + `frame_mbs_only_flag_2_frame_cropping_flag:consumed_bits_sel <= `fixed_length; + `vui_parameter_present_flag_s :consumed_bits_sel <= `fixed_length; + default :consumed_bits_sel <= `rst_consumed_bits_sel; + endcase + else if (pic_parameter_set_state != `rst_pic_parameter_set) + case (pic_parameter_set_state) + `pic_parameter_set_id_pps_s :consumed_bits_sel <= `exp_golomb; + `seq_parameter_set_id_pps_s :consumed_bits_sel <= `exp_golomb; + `entropy_coding_mode_flag_2_pic_order_present_flag :consumed_bits_sel <= `fixed_length; + `num_slice_groups_minus1_s :consumed_bits_sel <= `exp_golomb; + `num_ref_idx_l0_active_minus1_pps_s :consumed_bits_sel <= `exp_golomb; + `num_ref_idx_l1_active_minus1_pps_s :consumed_bits_sel <= `exp_golomb; + `weighted_pred_flag_2_weighted_bipred_idc :consumed_bits_sel <= `fixed_length; + `pic_init_qp_minus26_s :consumed_bits_sel <= `exp_golomb; + `pic_init_qs_minus26_s :consumed_bits_sel <= `exp_golomb; + `chroma_qp_index_offset_s :consumed_bits_sel <= `exp_golomb; + `deblocking_filter_control_2_redundant_pic_cnt_present_flag:consumed_bits_sel <= `fixed_length; + default :consumed_bits_sel <= `rst_consumed_bits_sel; + endcase + else if (nal_unit_state == `rbsp_trailing_one_bit) + consumed_bits_sel <= `fixed_length; + else if (nal_unit_state == `rbsp_trailing_zero_bits) + consumed_bits_sel <= `trailing_bits; + else + consumed_bits_sel <= `rst_consumed_bits_sel; + + always @ (reset_n or parser_state or nal_unit_state or slice_header_state or ref_pic_list_reordering_state or + dec_ref_pic_marking_state or slice_data_state or mb_pred_state or seq_parameter_set_state or pic_parameter_set_state) + if (reset_n == 0) + FixedLen <= 0; + else + begin + if (parser_state == `start_code_prefix) + FixedLen <= 5'd16; + else if (nal_unit_state == `forbidden_zero_bit_2_nal_unit_type) + FixedLen <= 8; + else if (slice_header_state == `num_ref_idx_active_override_flag_s) + FixedLen <= 1; + else if (ref_pic_list_reordering_state == `ref_pic_list_reordering_flag_l0_s) + FixedLen <= 1; + else if (dec_ref_pic_marking_state == `no_output_of_prior_pics_flag_2_long_term_reference_flag) + FixedLen <= 2; + else if (dec_ref_pic_marking_state == `adaptive_ref_pic_marking_mode_flag_s) + FixedLen <= 1; + else if (slice_data_state == `pcm_byte_s) + FixedLen <= 5'd16; + else if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s) + FixedLen <= 1; + else if (mb_pred_state == `rem_intra4x4_pred_mode_s) + FixedLen <= 3; + else if (seq_parameter_set_state == `fixed_header) + FixedLen <= 5'd16; + else if (seq_parameter_set_state == `level_idc_s) + FixedLen <= 8; + else if (seq_parameter_set_state == `gaps_in_frame_num_value_allowed_flag_s) + FixedLen <= 1; + else if (seq_parameter_set_state == `frame_mbs_only_flag_2_frame_cropping_flag) + FixedLen <= 3; + else if (seq_parameter_set_state == `vui_parameter_present_flag_s) + FixedLen <= 1; + else if (pic_parameter_set_state == `entropy_coding_mode_flag_2_pic_order_present_flag) + FixedLen <= 2; + else if (pic_parameter_set_state == `weighted_pred_flag_2_weighted_bipred_idc) + FixedLen <= 3; + else if (pic_parameter_set_state == `deblocking_filter_control_2_redundant_pic_cnt_present_flag) + FixedLen <= 3; + else if (nal_unit_state == `rbsp_trailing_one_bit) + FixedLen <= 1; + else + FixedLen <= 1; + end + + reg [6:0] pc_reg; + always @ (consumed_bits_sel or pc_reg or exp_golomb_len or dependent_variable_len or + cavlc_consumed_bits_len or FixedLen) + case (consumed_bits_sel) + `exp_golomb :pc <= pc_reg + exp_golomb_len; + `dependent_variable:pc <= pc_reg + dependent_variable_len; + `cavlc_consumed :pc <= pc_reg + cavlc_consumed_bits_len; + `fixed_length :pc <= pc_reg + FixedLen; + `trailing_bits :pc <= (pc_reg[2:0] == 3'b000)? pc_reg:{{pc_reg[6:3] + 1},3'b0}; + `pcm_alignment :pc <= (pc_reg[2:0] == 3'b000)? pc_reg:{{pc_reg[6:3] + 1},3'b0}; + default :pc <= pc_reg; + endcase + always @ (posedge clk) + pc_reg <= (reset_n == 0)? 0:pc; + +endmodule + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/ram_async_1r_sync_1w.v b/demo_chip_rtl/rtl/nova/tags/Start/src/ram_async_1r_sync_1w.v new file mode 100644 index 0000000..5952a86 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/ram_async_1r_sync_1w.v @@ -0,0 +1,81 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : ram_async_1r_sync_1w.v +// Generated : April 25,2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Synch Write, Asynch Read RAM, NOT synthesizable +// In real silicon, use register file (DFF) instead of RAM +// legal range:data_width [ 1 to 128 ] +// legal range:data_depth [ 2 to 256 ] +// Input data :data_in[data_width-1:0] +// Output data:data_out[data_width-1:0] +// Read Address :rd_addr[addr_width-1:0] +// Write Address:wr_addr[addr_width-1:0] +// Write enable (active low): wr_n +// Chip select (active low): cs_n +// Reset (active low): rst_n +// Clock:clk +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" +module ram_async_1r_sync_1w (clk, rst_n, cs_n, wr_n, rd_addr, wr_addr, data_in, data_out); + + parameter data_width = 4; //will be overrided during module instantiation + parameter data_depth = 8; //will be overrided during module instantiation + + `define addr_width ((data_depth>16)?((data_depth>64)?((data_depth>128)?8:7):((data_depth>32)?6:5)):((data_depth>4)?((data_depth>8)?4:3):((data_depth>2)?2:1))) + + input clk; + input rst_n; + input cs_n; + input wr_n; + input [data_width-1:0] data_in; + input [`addr_width-1:0] rd_addr; + input [`addr_width-1:0] wr_addr; + output [data_width-1:0] data_out; + + reg [data_width-1:0] ram [data_depth-1:0]; + + //data_width & data_depth check + initial + begin:parameter_check + integer param_error_flag; + param_error_flag = 0; + + if ( (data_width < 1) || (data_width > 128) ) + begin + param_error_flag = 1; + $display("Error: %m :\n Invalid value (%d) for parameter data_width (legal range: 1 to 128)",data_width ); + end + + if ( (data_depth < 2) || (data_depth > 256 ) ) + begin + param_error_flag = 1; + $display("Error: %m :\n Invalid value (%d) for parameter data_depth (legal range: 2 to 256 )",data_depth ); + end + + if ( param_error_flag == 1) + begin + $display("%m :\n Simulation aborted due to invalid parameter value(s)"); + $finish; + end + + end // end data_width & data_depth check + + //read + assign data_out = ((rd_addr ^ rd_addr) !== {`addr_width{1'b0}})? {data_width{1'bx}} : ((rd_addr >= data_depth)? {data_width{1'b0}} : ram[rd_addr] ); + + //write + always @ (posedge clk) + if (!cs_n && !wr_n) + ram[wr_addr] <= data_in; + +endmodule + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/ram_sync_1r_sync_1w.v b/demo_chip_rtl/rtl/nova/tags/Start/src/ram_sync_1r_sync_1w.v new file mode 100644 index 0000000..753b0b1 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/ram_sync_1r_sync_1w.v @@ -0,0 +1,94 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : ram_sync_1r_sync_1w.v +// Generated : April 25,2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Synch Write, Synch Read RAM, NOT synthesizable +// In real silicon, use customized RAM instead of DFF +// legal range:data_width [ 1 to 256 ] +// legal range:data_depth [ 2 to 1024 ] +// Input data :data_in[data_width-1:0] +// Output data:data_out[data_width-1:0] +// Read Address :rd_addr[addr_width-1:0] +// Write Address:wr_addr[addr_width-1:0] +// Write enable (active low): wr_n +// Chip select (active low): cs_n +// Reset (active low): rst_n +// Clock:clk +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module ram_sync_1r_sync_1w (clk, rst_n, wr_n, rd_n, wr_addr, rd_addr, data_in, data_out); + + parameter data_width = 4; //will be overrided during module instantiation + parameter data_depth = 8; //will be overrided during module instantiation + + `define addr_width ((data_depth>32)?((data_depth>256)?((data_depth>512)?10:9):((data_depth>128)?8:((data_depth>64)?7:6))):((data_depth>8) ?((data_depth>16) ?5:4) :((data_depth>4) ?3:((data_depth>2) ?1:0)))) + + input clk; + input rst_n; + input wr_n; + input rd_n; + input [`addr_width-1:0] wr_addr; + input [`addr_width-1:0] rd_addr; + input [data_width-1:0] data_in; + output [data_width-1:0] data_out; + + reg [data_width-1:0] data_out; + reg [data_width-1:0] ram [data_depth-1:0]; + + //data_width, data_depth, simultaneously read/write check + initial + begin:parameter_check + integer param_error_flag; + param_error_flag = 0; + + if ( (data_width < 1) || (data_width > 256) ) + begin + param_error_flag = 1; + $display("Error: %m :\n Invalid value (%d) for parameter data_width (legal range: 1 to 256)",data_width ); + end + + if ( (data_depth < 2) || (data_depth > 1024 ) ) + begin + param_error_flag = 1; + $display("Error: %m :\n Invalid value (%d) for parameter data_depth (legal range: 2 to 1024 )",data_depth ); + end + + /* + if ( (cs_n == 1'b0 && wr_n == 1'b0 && rd_n == 1'b0 ) ) + begin + param_error_flag = 1; + $display("Error: %m :\n Not allowed! RAM simultaneously read and write occur"); + end + */ + if ( param_error_flag == 1) + begin + $display("%m :\n Simulation aborted due to invalid parameter value(s)"); + $finish; + end + + end // end data_width & data_depth check + + //read + always @ (posedge clk or negedge rst_n) + if (rst_n == 1'b0) + data_out <= 0; + else if (!rd_n) + data_out <= ram[rd_addr]; + + //write + always @ (posedge clk) + if (!wr_n) + ram[wr_addr] <= data_in; + +endmodule + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/rec_DF_RAM0_96x32.v b/demo_chip_rtl/rtl/nova/tags/Start/src/rec_DF_RAM0_96x32.v new file mode 100644 index 0000000..ed82acc --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/rec_DF_RAM0_96x32.v @@ -0,0 +1,530 @@ +// +// Copyright (C) 2004 Virtual Silicon Technology Inc.. All Rights Reserved. +// Silicon Ready, The Heart of Great Silicon, and the Virtual Silicon logo are +// registered trademarks of Virtual Silicon Technology Inc. +// All other trademarks are the property of their respective owner. +// +// Virtual Silicon Technology Inc. +// 1322 Orleans Drive +// Sunnyvale, CA 94089-1135 +// Phone : 408-548-2700 +// Fax : 408-548-2750 +// Web Site : www.virtual-silicon.com +// +// VST Library Release: UMCL18G415T3_1.0 +// Product: High Density Single Port SRAM Compiler +// Process: L180 Generic II +// +// High Density one-Port RAM 96 words by 32 bits +// column mux = 4 +// bytewrite = n +// test = n +// powerbus = b +// frequency = 10 +// +`timescale 1 ns / 1 ps + +`celldefine +module rec_DF_RAM0_96x32 ( + CK, + CEN, + WEN, + OEN, + ADR, + DI, + DOUT + ); + +// parameter and port declaration block + parameter words = 96; + parameter bits = 32; + parameter addMsb = 6; + parameter bytes= 4; + parameter bitMsb = 31; + + input CK; + input CEN; + input WEN; + input OEN; + input [addMsb:0] ADR; + input [bitMsb:0] DI; + output [bitMsb:0] DOUT; + +// input buffer block + buf (buf_CK, CK); + buf (buf_CEN, CEN); + buf (buf_WEN, WEN); + buf (buf_OEN, OEN); + + wire [addMsb:0] buf_ADR; + wire [bitMsb:0] buf_DI; + assign buf_ADR = ADR; + assign buf_DI = DI; + + +// internal variable declarations + reg int_CEN; + reg int_WEN; + reg [addMsb:0] int_ADR; + reg [bitMsb:0] int_DI; + reg [bitMsb:0] int_DOUT; + reg [bitMsb:0] memory_array [95:0]; + + reg old_CK; + reg write_error; + reg read_error; + reg risingTmp; + always @(posedge buf_CK) + risingTmp = 1'b1; + always @(negedge buf_CK) + risingTmp = 1'b0; + + wire risingCK = risingTmp; + + wire rflag = risingCK & (buf_WEN!==1'b0); + wire wflag = risingCK & (buf_WEN!==1'b1); + + +// DOUT processing + wire [bitMsb:0] out_DOUT; + assign out_DOUT = int_DOUT; + + wire int_OEN = buf_OEN; + bufif0(DOUT[0], out_DOUT[0], int_OEN); + bufif0(DOUT[1], out_DOUT[1], int_OEN); + bufif0(DOUT[2], out_DOUT[2], int_OEN); + bufif0(DOUT[3], out_DOUT[3], int_OEN); + bufif0(DOUT[4], out_DOUT[4], int_OEN); + bufif0(DOUT[5], out_DOUT[5], int_OEN); + bufif0(DOUT[6], out_DOUT[6], int_OEN); + bufif0(DOUT[7], out_DOUT[7], int_OEN); + bufif0(DOUT[8], out_DOUT[8], int_OEN); + bufif0(DOUT[9], out_DOUT[9], int_OEN); + bufif0(DOUT[10], out_DOUT[10], int_OEN); + bufif0(DOUT[11], out_DOUT[11], int_OEN); + bufif0(DOUT[12], out_DOUT[12], int_OEN); + bufif0(DOUT[13], out_DOUT[13], int_OEN); + bufif0(DOUT[14], out_DOUT[14], int_OEN); + bufif0(DOUT[15], out_DOUT[15], int_OEN); + bufif0(DOUT[16], out_DOUT[16], int_OEN); + bufif0(DOUT[17], out_DOUT[17], int_OEN); + bufif0(DOUT[18], out_DOUT[18], int_OEN); + bufif0(DOUT[19], out_DOUT[19], int_OEN); + bufif0(DOUT[20], out_DOUT[20], int_OEN); + bufif0(DOUT[21], out_DOUT[21], int_OEN); + bufif0(DOUT[22], out_DOUT[22], int_OEN); + bufif0(DOUT[23], out_DOUT[23], int_OEN); + bufif0(DOUT[24], out_DOUT[24], int_OEN); + bufif0(DOUT[25], out_DOUT[25], int_OEN); + bufif0(DOUT[26], out_DOUT[26], int_OEN); + bufif0(DOUT[27], out_DOUT[27], int_OEN); + bufif0(DOUT[28], out_DOUT[28], int_OEN); + bufif0(DOUT[29], out_DOUT[29], int_OEN); + bufif0(DOUT[30], out_DOUT[30], int_OEN); + bufif0(DOUT[31], out_DOUT[31], int_OEN); + + + and (chk_DI, ~buf_CEN, ~buf_WEN); + + reg mpwCK_notifier; + reg pwhCK_notifier; + reg shCEN_notifier; + reg shADR_notifier; + reg shWEN_notifier; + reg shDI_notifier; + + integer i, j, h, k, m; + + parameter x_data = 32'bx; + parameter data_0 = {32{1'b0}}; + parameter x_adr = 7'bx; + parameter adr_0 = {7{1'b0}}; + +initial begin + for (i = 0; i < words; i=i+1) + memory_array[i] = x_data; +end + +initial begin + read_error = 1'b0; + write_error = 1'b0; + old_CK = 1'b0; + // Wait for valid initial transition + wait (buf_CK === 1'b0); + + forever @(buf_CK) begin + case ({old_CK,buf_CK}) + // 0->1 transition + 2'b01: + begin + int_CEN = buf_CEN; + int_WEN = buf_WEN; + int_ADR = buf_ADR; + int_DI = buf_DI; + + if (int_CEN === 1'b0) begin + // Read cycle + if( ^int_ADR === 1'bx) begin + ADR_error; + end else if (int_WEN === 1'b1) begin + int_DOUT = memory_array[int_ADR]; + // Write cycle + end else if (int_WEN === 1'b0) begin + if (write_error === 1'b0) begin + memory_array[int_ADR] = int_DI; // Write cycle + int_DOUT = int_DI; + end + // Unknown cycle + end else begin // int_WEN = x + SHWrite_error; + end + end else if (int_CEN === 1'bx) begin + wipe_memory_output; + end + // 0->unknown transition, wait until returns to 0 + end + 2'b0x, 2'b1x, 2'bx1, 2'bx0: begin + int_CEN = 1'bx; + wipe_memory_output; + end + endcase + old_CK <= #0.002 buf_CK; + end + end // end memory loop + + +//==================== +// Task and procedure +//==================== + +// This task process entire MEM and OUTPUTs +task wipe_memory_output; +integer i; + begin + write_error = 1'b1; + int_DOUT = x_data; + int_ADR = x_adr; + int_WEN = 1'bx; + int_DI = x_data; + + + for (i = 0; i < words; i=i+1) begin + memory_array[i] = x_data; + end + write_error = 1'b0; + end +endtask + +// This task process write through violation +task SHWrite_error; +integer ic, ib; + begin + write_error = 1'b1; + read_error = 1'b1; + if (int_WEN===1'bx) begin + memory_array[int_ADR] = x_data; + int_DOUT = x_data; + end else if (int_WEN===1'b0) begin + memory_array[int_ADR] = int_DI; + int_DOUT = int_DI; + end + + write_error = 1'b0; + read_error = 1'b0; + end +endtask + +// This task process read violation +task SHRead_error; + begin + read_error = 1'b1; + int_DOUT = x_data; + //wait (buf_CK === 1'b0); + read_error = 1'b0; + end +endtask + +// This task process ADR violation +task ADR_error; +integer i; + begin + write_error = 1'b1; + read_error = 1'b1; + int_DOUT = x_data; + for (i = 0; i < words; i=i+1) + memory_array[i] = x_data; + write_error = 1'b0; + read_error = 1'b0; + end +endtask + +//======================= +// Violation processing +//======================= +// CK violation +always @(pwhCK_notifier) begin + $display ("%m CLK cycle pulse width high timing violation detected %t", $realtime); + int_CEN = 1'bx; + wipe_memory_output; +end + +always @(mpwCK_notifier) begin + $display ("%m CLK cycle timing violation detected %t", $realtime); + #0.001; + wipe_memory_output; + risingTmp = 1'b0; +end + + +// CEN violation +always @(shCEN_notifier) begin + int_CEN = 1'bx; + $display ("%m Cell enable timing violation detected %t", $realtime); + wipe_memory_output; +end + +// ADR violation +always @(shADR_notifier) begin + int_ADR = x_adr; + $display ("%m Address timing violation detected %t", $realtime); + ADR_error; +end + +// WEN violation +always @(shWEN_notifier) begin + int_WEN = 1'bx; + $display ("%m Write enable timing violation detected %t", $realtime); + if( ^int_ADR !== 1'bx) + SHWrite_error; +end + + +// DI violation +always @(shDI_notifier) begin + int_DI = x_data; + $display ("%m Input data timing violation detected %t", $realtime); + if( ^int_ADR !== 1'bx) + SHWrite_error; +end + + + +specify + + // Path delays + if (rflag) (CK *> DOUT[0]) = 0.1; + if (wflag) (CK *> DOUT[0]) = 0.1; + if (rflag) (CK *> DOUT[1]) = 0.1; + if (wflag) (CK *> DOUT[1]) = 0.1; + if (rflag) (CK *> DOUT[2]) = 0.1; + if (wflag) (CK *> DOUT[2]) = 0.1; + if (rflag) (CK *> DOUT[3]) = 0.1; + if (wflag) (CK *> DOUT[3]) = 0.1; + if (rflag) (CK *> DOUT[4]) = 0.1; + if (wflag) (CK *> DOUT[4]) = 0.1; + if (rflag) (CK *> DOUT[5]) = 0.1; + if (wflag) (CK *> DOUT[5]) = 0.1; + if (rflag) (CK *> DOUT[6]) = 0.1; + if (wflag) (CK *> DOUT[6]) = 0.1; + if (rflag) (CK *> DOUT[7]) = 0.1; + if (wflag) (CK *> DOUT[7]) = 0.1; + if (rflag) (CK *> DOUT[8]) = 0.1; + if (wflag) (CK *> DOUT[8]) = 0.1; + if (rflag) (CK *> DOUT[9]) = 0.1; + if (wflag) (CK *> DOUT[9]) = 0.1; + if (rflag) (CK *> DOUT[10]) = 0.1; + if (wflag) (CK *> DOUT[10]) = 0.1; + if (rflag) (CK *> DOUT[11]) = 0.1; + if (wflag) (CK *> DOUT[11]) = 0.1; + if (rflag) (CK *> DOUT[12]) = 0.1; + if (wflag) (CK *> DOUT[12]) = 0.1; + if (rflag) (CK *> DOUT[13]) = 0.1; + if (wflag) (CK *> DOUT[13]) = 0.1; + if (rflag) (CK *> DOUT[14]) = 0.1; + if (wflag) (CK *> DOUT[14]) = 0.1; + if (rflag) (CK *> DOUT[15]) = 0.1; + if (wflag) (CK *> DOUT[15]) = 0.1; + if (rflag) (CK *> DOUT[16]) = 0.1; + if (wflag) (CK *> DOUT[16]) = 0.1; + if (rflag) (CK *> DOUT[17]) = 0.1; + if (wflag) (CK *> DOUT[17]) = 0.1; + if (rflag) (CK *> DOUT[18]) = 0.1; + if (wflag) (CK *> DOUT[18]) = 0.1; + if (rflag) (CK *> DOUT[19]) = 0.1; + if (wflag) (CK *> DOUT[19]) = 0.1; + if (rflag) (CK *> DOUT[20]) = 0.1; + if (wflag) (CK *> DOUT[20]) = 0.1; + if (rflag) (CK *> DOUT[21]) = 0.1; + if (wflag) (CK *> DOUT[21]) = 0.1; + if (rflag) (CK *> DOUT[22]) = 0.1; + if (wflag) (CK *> DOUT[22]) = 0.1; + if (rflag) (CK *> DOUT[23]) = 0.1; + if (wflag) (CK *> DOUT[23]) = 0.1; + if (rflag) (CK *> DOUT[24]) = 0.1; + if (wflag) (CK *> DOUT[24]) = 0.1; + if (rflag) (CK *> DOUT[25]) = 0.1; + if (wflag) (CK *> DOUT[25]) = 0.1; + if (rflag) (CK *> DOUT[26]) = 0.1; + if (wflag) (CK *> DOUT[26]) = 0.1; + if (rflag) (CK *> DOUT[27]) = 0.1; + if (wflag) (CK *> DOUT[27]) = 0.1; + if (rflag) (CK *> DOUT[28]) = 0.1; + if (wflag) (CK *> DOUT[28]) = 0.1; + if (rflag) (CK *> DOUT[29]) = 0.1; + if (wflag) (CK *> DOUT[29]) = 0.1; + if (rflag) (CK *> DOUT[30]) = 0.1; + if (wflag) (CK *> DOUT[30]) = 0.1; + if (rflag) (CK *> DOUT[31]) = 0.1; + if (wflag) (CK *> DOUT[31]) = 0.1; + + (OEN *> DOUT[0]) = 0.1; + (OEN *> DOUT[1]) = 0.1; + (OEN *> DOUT[2]) = 0.1; + (OEN *> DOUT[3]) = 0.1; + (OEN *> DOUT[4]) = 0.1; + (OEN *> DOUT[5]) = 0.1; + (OEN *> DOUT[6]) = 0.1; + (OEN *> DOUT[7]) = 0.1; + (OEN *> DOUT[8]) = 0.1; + (OEN *> DOUT[9]) = 0.1; + (OEN *> DOUT[10]) = 0.1; + (OEN *> DOUT[11]) = 0.1; + (OEN *> DOUT[12]) = 0.1; + (OEN *> DOUT[13]) = 0.1; + (OEN *> DOUT[14]) = 0.1; + (OEN *> DOUT[15]) = 0.1; + (OEN *> DOUT[16]) = 0.1; + (OEN *> DOUT[17]) = 0.1; + (OEN *> DOUT[18]) = 0.1; + (OEN *> DOUT[19]) = 0.1; + (OEN *> DOUT[20]) = 0.1; + (OEN *> DOUT[21]) = 0.1; + (OEN *> DOUT[22]) = 0.1; + (OEN *> DOUT[23]) = 0.1; + (OEN *> DOUT[24]) = 0.1; + (OEN *> DOUT[25]) = 0.1; + (OEN *> DOUT[26]) = 0.1; + (OEN *> DOUT[27]) = 0.1; + (OEN *> DOUT[28]) = 0.1; + (OEN *> DOUT[29]) = 0.1; + (OEN *> DOUT[30]) = 0.1; + (OEN *> DOUT[31]) = 0.1; + + + + // Timing check parameters + specparam tsadrl = 0; + specparam thadrl = 0; + specparam tsadrh = 0; + specparam thadrh = 0; + specparam tsdil = 0; + specparam tsdih = 0; + specparam thdil = 0; + specparam thdih = 0; + specparam tscenl = 0; + specparam thcenl = 0; + specparam tscenh = 0; + specparam thcenh = 0; + specparam tswenl = 0; + specparam thwenl = 0; + specparam tswenh = 0; + specparam thwenh = 0; + specparam tcyc = 0; + specparam tlck = 0; + specparam thck = 0; + + // Timing checks + $setuphold(posedge CK, negedge CEN, tscenl, thcenl, shCEN_notifier); + $setuphold(posedge CK, posedge CEN, tscenh, thcenh, shCEN_notifier); + + $setuphold(posedge CK &&& (CEN===1'b0), negedge ADR[0], tsadrl, thadrl, shADR_notifier); + $setuphold(posedge CK &&& (CEN===1'b0), posedge ADR[0], tsadrh, thadrh, shADR_notifier); + $setuphold(posedge CK &&& (CEN===1'b0), negedge ADR[1], tsadrl, thadrl, shADR_notifier); + $setuphold(posedge CK &&& (CEN===1'b0), posedge ADR[1], tsadrh, thadrh, shADR_notifier); + $setuphold(posedge CK &&& (CEN===1'b0), negedge ADR[2], tsadrl, thadrl, shADR_notifier); + $setuphold(posedge CK &&& (CEN===1'b0), posedge ADR[2], tsadrh, thadrh, shADR_notifier); + $setuphold(posedge CK &&& (CEN===1'b0), negedge ADR[3], tsadrl, thadrl, shADR_notifier); + $setuphold(posedge CK &&& (CEN===1'b0), posedge ADR[3], tsadrh, thadrh, shADR_notifier); + $setuphold(posedge CK &&& (CEN===1'b0), negedge ADR[4], tsadrl, thadrl, shADR_notifier); + $setuphold(posedge CK &&& (CEN===1'b0), posedge ADR[4], tsadrh, thadrh, shADR_notifier); + $setuphold(posedge CK &&& (CEN===1'b0), negedge ADR[5], tsadrl, thadrl, shADR_notifier); + $setuphold(posedge CK &&& (CEN===1'b0), posedge ADR[5], tsadrh, thadrh, shADR_notifier); + $setuphold(posedge CK &&& (CEN===1'b0), negedge ADR[6], tsadrl, thadrl, shADR_notifier); + $setuphold(posedge CK &&& (CEN===1'b0), posedge ADR[6], tsadrh, thadrh, shADR_notifier); + + $setuphold(posedge CK &&& (CEN===1'b0), negedge WEN, tswenl, thwenl, shWEN_notifier); + $setuphold(posedge CK &&& (CEN===1'b0), posedge WEN, tswenh, thwenh, shWEN_notifier); + + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[0], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[0], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[1], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[1], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[2], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[2], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[3], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[3], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[4], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[4], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[5], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[5], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[6], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[6], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[7], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[7], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[8], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[8], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[9], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[9], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[10], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[10], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[11], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[11], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[12], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[12], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[13], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[13], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[14], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[14], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[15], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[15], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[16], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[16], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[17], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[17], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[18], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[18], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[19], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[19], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[20], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[20], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[21], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[21], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[22], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[22], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[23], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[23], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[24], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[24], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[25], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[25], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[26], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[26], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[27], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[27], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[28], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[28], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[29], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[29], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[30], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[30], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[31], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[31], tsdih, thdih, shDI_notifier); + + $period(posedge CK, tcyc, mpwCK_notifier); + $width(negedge CK, tlck, 0, mpwCK_notifier); + $width(posedge CK, thck, 0, pwhCK_notifier); + +endspecify + +endmodule +`endcelldefine diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/rec_DF_RAM0_wrapper.v b/demo_chip_rtl/rtl/nova/tags/Start/src/rec_DF_RAM0_wrapper.v new file mode 100644 index 0000000..6734330 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/rec_DF_RAM0_wrapper.v @@ -0,0 +1,66 @@ +//-------------------------------------------------------------------------------------------------- +// Design : H264Decoder +// Author : KE XU +// Email : kexu@ee.cuhk.edu.hk +// File : rec_DF_RAM0.v +// Generated : Dec 7 2005 +//------------------------------------------------------------------------------------------------- +// +// Description : SRAM between reconstruction and deblocking filter (96x32bit) +//------------------------------------------------------------------------------------------------- +`timescale 1ns/1ns +module rec_DF_RAM0_wrapper (clk,gclk_rec_DF_RAM0,reset_n, + rec_DF_RAM0_cs_n,rec_DF_RAM0_wr,rec_DF_RAM0_addr,rec_DF_RAM0_din,rec_DF_RAM0_dout); + input clk; + input gclk_rec_DF_RAM0; + input reset_n; + input rec_DF_RAM0_cs_n; + input rec_DF_RAM0_wr; + input [6:0] rec_DF_RAM0_addr; + input [31:0] rec_DF_RAM0_din; + output [31:0] rec_DF_RAM0_dout; + + reg rec_DF_RAM0_OEN; + always @ (posedge clk) + if (reset_n == 1'b0) + rec_DF_RAM0_OEN <= 1'b1; + else if (!rec_DF_RAM0_cs_n && !rec_DF_RAM0_wr) + rec_DF_RAM0_OEN <= 1'b0; + else + rec_DF_RAM0_OEN <= 1'b1; + + wire rec_DF_RAM0_CEN; + assign rec_DF_RAM0_CEN = rec_DF_RAM0_cs_n & rec_DF_RAM0_OEN; + + rec_DF_RAM0_96x32 rec_DF_RAM0_96x32 ( + .CK(gclk_rec_DF_RAM0), + .ADR(rec_DF_RAM0_addr), + .DI(rec_DF_RAM0_din), + .WEN(~rec_DF_RAM0_wr), + .CEN(rec_DF_RAM0_CEN), + .OEN(rec_DF_RAM0_OEN), + .DOUT(rec_DF_RAM0_dout) + ); +endmodule +/* +module rec_DF_RAM0_96x32 (CK,ADR,DI,WEN,CEN,OEN,DOUT); + input CK; + input [6:0] ADR; + input [31:0] DI; + input WEN; + input CEN; + input OEN; + output [31:0] DOUT; + reg [31:0] DOUT; + reg [31:0] RAM [0:95]; + + always @ (posedge CK) + if (!CEN && !WEN) + RAM[ADR] <= DI; + + always @ (posedge CK) + if (!CEN && !OEN) + DOUT <= RAM[ADR]; +endmodule*/ + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/rec_DF_RAM1_96x32.v b/demo_chip_rtl/rtl/nova/tags/Start/src/rec_DF_RAM1_96x32.v new file mode 100644 index 0000000..69cced7 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/rec_DF_RAM1_96x32.v @@ -0,0 +1,530 @@ +// +// Copyright (C) 2004 Virtual Silicon Technology Inc.. All Rights Reserved. +// Silicon Ready, The Heart of Great Silicon, and the Virtual Silicon logo are +// registered trademarks of Virtual Silicon Technology Inc. +// All other trademarks are the property of their respective owner. +// +// Virtual Silicon Technology Inc. +// 1322 Orleans Drive +// Sunnyvale, CA 94089-1135 +// Phone : 408-548-2700 +// Fax : 408-548-2750 +// Web Site : www.virtual-silicon.com +// +// VST Library Release: UMCL18G415T3_1.0 +// Product: High Density Single Port SRAM Compiler +// Process: L180 Generic II +// +// High Density one-Port RAM 96 words by 32 bits +// column mux = 4 +// bytewrite = n +// test = n +// powerbus = b +// frequency = 10 +// +`timescale 1 ns / 1 ps + +`celldefine +module rec_DF_RAM1_96x32 ( + CK, + CEN, + WEN, + OEN, + ADR, + DI, + DOUT + ); + +// parameter and port declaration block + parameter words = 96; + parameter bits = 32; + parameter addMsb = 6; + parameter bytes= 4; + parameter bitMsb = 31; + + input CK; + input CEN; + input WEN; + input OEN; + input [addMsb:0] ADR; + input [bitMsb:0] DI; + output [bitMsb:0] DOUT; + +// input buffer block + buf (buf_CK, CK); + buf (buf_CEN, CEN); + buf (buf_WEN, WEN); + buf (buf_OEN, OEN); + + wire [addMsb:0] buf_ADR; + wire [bitMsb:0] buf_DI; + assign buf_ADR = ADR; + assign buf_DI = DI; + + +// internal variable declarations + reg int_CEN; + reg int_WEN; + reg [addMsb:0] int_ADR; + reg [bitMsb:0] int_DI; + reg [bitMsb:0] int_DOUT; + reg [bitMsb:0] memory_array [95:0]; + + reg old_CK; + reg write_error; + reg read_error; + reg risingTmp; + always @(posedge buf_CK) + risingTmp = 1'b1; + always @(negedge buf_CK) + risingTmp = 1'b0; + + wire risingCK = risingTmp; + + wire rflag = risingCK & (buf_WEN!==1'b0); + wire wflag = risingCK & (buf_WEN!==1'b1); + + +// DOUT processing + wire [bitMsb:0] out_DOUT; + assign out_DOUT = int_DOUT; + + wire int_OEN = buf_OEN; + bufif0(DOUT[0], out_DOUT[0], int_OEN); + bufif0(DOUT[1], out_DOUT[1], int_OEN); + bufif0(DOUT[2], out_DOUT[2], int_OEN); + bufif0(DOUT[3], out_DOUT[3], int_OEN); + bufif0(DOUT[4], out_DOUT[4], int_OEN); + bufif0(DOUT[5], out_DOUT[5], int_OEN); + bufif0(DOUT[6], out_DOUT[6], int_OEN); + bufif0(DOUT[7], out_DOUT[7], int_OEN); + bufif0(DOUT[8], out_DOUT[8], int_OEN); + bufif0(DOUT[9], out_DOUT[9], int_OEN); + bufif0(DOUT[10], out_DOUT[10], int_OEN); + bufif0(DOUT[11], out_DOUT[11], int_OEN); + bufif0(DOUT[12], out_DOUT[12], int_OEN); + bufif0(DOUT[13], out_DOUT[13], int_OEN); + bufif0(DOUT[14], out_DOUT[14], int_OEN); + bufif0(DOUT[15], out_DOUT[15], int_OEN); + bufif0(DOUT[16], out_DOUT[16], int_OEN); + bufif0(DOUT[17], out_DOUT[17], int_OEN); + bufif0(DOUT[18], out_DOUT[18], int_OEN); + bufif0(DOUT[19], out_DOUT[19], int_OEN); + bufif0(DOUT[20], out_DOUT[20], int_OEN); + bufif0(DOUT[21], out_DOUT[21], int_OEN); + bufif0(DOUT[22], out_DOUT[22], int_OEN); + bufif0(DOUT[23], out_DOUT[23], int_OEN); + bufif0(DOUT[24], out_DOUT[24], int_OEN); + bufif0(DOUT[25], out_DOUT[25], int_OEN); + bufif0(DOUT[26], out_DOUT[26], int_OEN); + bufif0(DOUT[27], out_DOUT[27], int_OEN); + bufif0(DOUT[28], out_DOUT[28], int_OEN); + bufif0(DOUT[29], out_DOUT[29], int_OEN); + bufif0(DOUT[30], out_DOUT[30], int_OEN); + bufif0(DOUT[31], out_DOUT[31], int_OEN); + + + and (chk_DI, ~buf_CEN, ~buf_WEN); + + reg mpwCK_notifier; + reg pwhCK_notifier; + reg shCEN_notifier; + reg shADR_notifier; + reg shWEN_notifier; + reg shDI_notifier; + + integer i, j, h, k, m; + + parameter x_data = 32'bx; + parameter data_0 = {32{1'b0}}; + parameter x_adr = 7'bx; + parameter adr_0 = {7{1'b0}}; + +initial begin + for (i = 0; i < words; i=i+1) + memory_array[i] = x_data; +end + +initial begin + read_error = 1'b0; + write_error = 1'b0; + old_CK = 1'b0; + // Wait for valid initial transition + wait (buf_CK === 1'b0); + + forever @(buf_CK) begin + case ({old_CK,buf_CK}) + // 0->1 transition + 2'b01: + begin + int_CEN = buf_CEN; + int_WEN = buf_WEN; + int_ADR = buf_ADR; + int_DI = buf_DI; + + if (int_CEN === 1'b0) begin + // Read cycle + if( ^int_ADR === 1'bx) begin + ADR_error; + end else if (int_WEN === 1'b1) begin + int_DOUT = memory_array[int_ADR]; + // Write cycle + end else if (int_WEN === 1'b0) begin + if (write_error === 1'b0) begin + memory_array[int_ADR] = int_DI; // Write cycle + int_DOUT = int_DI; + end + // Unknown cycle + end else begin // int_WEN = x + SHWrite_error; + end + end else if (int_CEN === 1'bx) begin + wipe_memory_output; + end + // 0->unknown transition, wait until returns to 0 + end + 2'b0x, 2'b1x, 2'bx1, 2'bx0: begin + int_CEN = 1'bx; + wipe_memory_output; + end + endcase + old_CK <= #0.002 buf_CK; + end + end // end memory loop + + +//==================== +// Task and procedure +//==================== + +// This task process entire MEM and OUTPUTs +task wipe_memory_output; +integer i; + begin + write_error = 1'b1; + int_DOUT = x_data; + int_ADR = x_adr; + int_WEN = 1'bx; + int_DI = x_data; + + + for (i = 0; i < words; i=i+1) begin + memory_array[i] = x_data; + end + write_error = 1'b0; + end +endtask + +// This task process write through violation +task SHWrite_error; +integer ic, ib; + begin + write_error = 1'b1; + read_error = 1'b1; + if (int_WEN===1'bx) begin + memory_array[int_ADR] = x_data; + int_DOUT = x_data; + end else if (int_WEN===1'b0) begin + memory_array[int_ADR] = int_DI; + int_DOUT = int_DI; + end + + write_error = 1'b0; + read_error = 1'b0; + end +endtask + +// This task process read violation +task SHRead_error; + begin + read_error = 1'b1; + int_DOUT = x_data; + //wait (buf_CK === 1'b0); + read_error = 1'b0; + end +endtask + +// This task process ADR violation +task ADR_error; +integer i; + begin + write_error = 1'b1; + read_error = 1'b1; + int_DOUT = x_data; + for (i = 0; i < words; i=i+1) + memory_array[i] = x_data; + write_error = 1'b0; + read_error = 1'b0; + end +endtask + +//======================= +// Violation processing +//======================= +// CK violation +always @(pwhCK_notifier) begin + $display ("%m CLK cycle pulse width high timing violation detected %t", $realtime); + int_CEN = 1'bx; + wipe_memory_output; +end + +always @(mpwCK_notifier) begin + $display ("%m CLK cycle timing violation detected %t", $realtime); + #0.001; + wipe_memory_output; + risingTmp = 1'b0; +end + + +// CEN violation +always @(shCEN_notifier) begin + int_CEN = 1'bx; + $display ("%m Cell enable timing violation detected %t", $realtime); + wipe_memory_output; +end + +// ADR violation +always @(shADR_notifier) begin + int_ADR = x_adr; + $display ("%m Address timing violation detected %t", $realtime); + ADR_error; +end + +// WEN violation +always @(shWEN_notifier) begin + int_WEN = 1'bx; + $display ("%m Write enable timing violation detected %t", $realtime); + if( ^int_ADR !== 1'bx) + SHWrite_error; +end + + +// DI violation +always @(shDI_notifier) begin + int_DI = x_data; + $display ("%m Input data timing violation detected %t", $realtime); + if( ^int_ADR !== 1'bx) + SHWrite_error; +end + + + +specify + + // Path delays + if (rflag) (CK *> DOUT[0]) = 0.1; + if (wflag) (CK *> DOUT[0]) = 0.1; + if (rflag) (CK *> DOUT[1]) = 0.1; + if (wflag) (CK *> DOUT[1]) = 0.1; + if (rflag) (CK *> DOUT[2]) = 0.1; + if (wflag) (CK *> DOUT[2]) = 0.1; + if (rflag) (CK *> DOUT[3]) = 0.1; + if (wflag) (CK *> DOUT[3]) = 0.1; + if (rflag) (CK *> DOUT[4]) = 0.1; + if (wflag) (CK *> DOUT[4]) = 0.1; + if (rflag) (CK *> DOUT[5]) = 0.1; + if (wflag) (CK *> DOUT[5]) = 0.1; + if (rflag) (CK *> DOUT[6]) = 0.1; + if (wflag) (CK *> DOUT[6]) = 0.1; + if (rflag) (CK *> DOUT[7]) = 0.1; + if (wflag) (CK *> DOUT[7]) = 0.1; + if (rflag) (CK *> DOUT[8]) = 0.1; + if (wflag) (CK *> DOUT[8]) = 0.1; + if (rflag) (CK *> DOUT[9]) = 0.1; + if (wflag) (CK *> DOUT[9]) = 0.1; + if (rflag) (CK *> DOUT[10]) = 0.1; + if (wflag) (CK *> DOUT[10]) = 0.1; + if (rflag) (CK *> DOUT[11]) = 0.1; + if (wflag) (CK *> DOUT[11]) = 0.1; + if (rflag) (CK *> DOUT[12]) = 0.1; + if (wflag) (CK *> DOUT[12]) = 0.1; + if (rflag) (CK *> DOUT[13]) = 0.1; + if (wflag) (CK *> DOUT[13]) = 0.1; + if (rflag) (CK *> DOUT[14]) = 0.1; + if (wflag) (CK *> DOUT[14]) = 0.1; + if (rflag) (CK *> DOUT[15]) = 0.1; + if (wflag) (CK *> DOUT[15]) = 0.1; + if (rflag) (CK *> DOUT[16]) = 0.1; + if (wflag) (CK *> DOUT[16]) = 0.1; + if (rflag) (CK *> DOUT[17]) = 0.1; + if (wflag) (CK *> DOUT[17]) = 0.1; + if (rflag) (CK *> DOUT[18]) = 0.1; + if (wflag) (CK *> DOUT[18]) = 0.1; + if (rflag) (CK *> DOUT[19]) = 0.1; + if (wflag) (CK *> DOUT[19]) = 0.1; + if (rflag) (CK *> DOUT[20]) = 0.1; + if (wflag) (CK *> DOUT[20]) = 0.1; + if (rflag) (CK *> DOUT[21]) = 0.1; + if (wflag) (CK *> DOUT[21]) = 0.1; + if (rflag) (CK *> DOUT[22]) = 0.1; + if (wflag) (CK *> DOUT[22]) = 0.1; + if (rflag) (CK *> DOUT[23]) = 0.1; + if (wflag) (CK *> DOUT[23]) = 0.1; + if (rflag) (CK *> DOUT[24]) = 0.1; + if (wflag) (CK *> DOUT[24]) = 0.1; + if (rflag) (CK *> DOUT[25]) = 0.1; + if (wflag) (CK *> DOUT[25]) = 0.1; + if (rflag) (CK *> DOUT[26]) = 0.1; + if (wflag) (CK *> DOUT[26]) = 0.1; + if (rflag) (CK *> DOUT[27]) = 0.1; + if (wflag) (CK *> DOUT[27]) = 0.1; + if (rflag) (CK *> DOUT[28]) = 0.1; + if (wflag) (CK *> DOUT[28]) = 0.1; + if (rflag) (CK *> DOUT[29]) = 0.1; + if (wflag) (CK *> DOUT[29]) = 0.1; + if (rflag) (CK *> DOUT[30]) = 0.1; + if (wflag) (CK *> DOUT[30]) = 0.1; + if (rflag) (CK *> DOUT[31]) = 0.1; + if (wflag) (CK *> DOUT[31]) = 0.1; + + (OEN *> DOUT[0]) = 0.1; + (OEN *> DOUT[1]) = 0.1; + (OEN *> DOUT[2]) = 0.1; + (OEN *> DOUT[3]) = 0.1; + (OEN *> DOUT[4]) = 0.1; + (OEN *> DOUT[5]) = 0.1; + (OEN *> DOUT[6]) = 0.1; + (OEN *> DOUT[7]) = 0.1; + (OEN *> DOUT[8]) = 0.1; + (OEN *> DOUT[9]) = 0.1; + (OEN *> DOUT[10]) = 0.1; + (OEN *> DOUT[11]) = 0.1; + (OEN *> DOUT[12]) = 0.1; + (OEN *> DOUT[13]) = 0.1; + (OEN *> DOUT[14]) = 0.1; + (OEN *> DOUT[15]) = 0.1; + (OEN *> DOUT[16]) = 0.1; + (OEN *> DOUT[17]) = 0.1; + (OEN *> DOUT[18]) = 0.1; + (OEN *> DOUT[19]) = 0.1; + (OEN *> DOUT[20]) = 0.1; + (OEN *> DOUT[21]) = 0.1; + (OEN *> DOUT[22]) = 0.1; + (OEN *> DOUT[23]) = 0.1; + (OEN *> DOUT[24]) = 0.1; + (OEN *> DOUT[25]) = 0.1; + (OEN *> DOUT[26]) = 0.1; + (OEN *> DOUT[27]) = 0.1; + (OEN *> DOUT[28]) = 0.1; + (OEN *> DOUT[29]) = 0.1; + (OEN *> DOUT[30]) = 0.1; + (OEN *> DOUT[31]) = 0.1; + + + + // Timing check parameters + specparam tsadrl = 0; + specparam thadrl = 0; + specparam tsadrh = 0; + specparam thadrh = 0; + specparam tsdil = 0; + specparam tsdih = 0; + specparam thdil = 0; + specparam thdih = 0; + specparam tscenl = 0; + specparam thcenl = 0; + specparam tscenh = 0; + specparam thcenh = 0; + specparam tswenl = 0; + specparam thwenl = 0; + specparam tswenh = 0; + specparam thwenh = 0; + specparam tcyc = 0; + specparam tlck = 0; + specparam thck = 0; + + // Timing checks + $setuphold(posedge CK, negedge CEN, tscenl, thcenl, shCEN_notifier); + $setuphold(posedge CK, posedge CEN, tscenh, thcenh, shCEN_notifier); + + $setuphold(posedge CK &&& (CEN===1'b0), negedge ADR[0], tsadrl, thadrl, shADR_notifier); + $setuphold(posedge CK &&& (CEN===1'b0), posedge ADR[0], tsadrh, thadrh, shADR_notifier); + $setuphold(posedge CK &&& (CEN===1'b0), negedge ADR[1], tsadrl, thadrl, shADR_notifier); + $setuphold(posedge CK &&& (CEN===1'b0), posedge ADR[1], tsadrh, thadrh, shADR_notifier); + $setuphold(posedge CK &&& (CEN===1'b0), negedge ADR[2], tsadrl, thadrl, shADR_notifier); + $setuphold(posedge CK &&& (CEN===1'b0), posedge ADR[2], tsadrh, thadrh, shADR_notifier); + $setuphold(posedge CK &&& (CEN===1'b0), negedge ADR[3], tsadrl, thadrl, shADR_notifier); + $setuphold(posedge CK &&& (CEN===1'b0), posedge ADR[3], tsadrh, thadrh, shADR_notifier); + $setuphold(posedge CK &&& (CEN===1'b0), negedge ADR[4], tsadrl, thadrl, shADR_notifier); + $setuphold(posedge CK &&& (CEN===1'b0), posedge ADR[4], tsadrh, thadrh, shADR_notifier); + $setuphold(posedge CK &&& (CEN===1'b0), negedge ADR[5], tsadrl, thadrl, shADR_notifier); + $setuphold(posedge CK &&& (CEN===1'b0), posedge ADR[5], tsadrh, thadrh, shADR_notifier); + $setuphold(posedge CK &&& (CEN===1'b0), negedge ADR[6], tsadrl, thadrl, shADR_notifier); + $setuphold(posedge CK &&& (CEN===1'b0), posedge ADR[6], tsadrh, thadrh, shADR_notifier); + + $setuphold(posedge CK &&& (CEN===1'b0), negedge WEN, tswenl, thwenl, shWEN_notifier); + $setuphold(posedge CK &&& (CEN===1'b0), posedge WEN, tswenh, thwenh, shWEN_notifier); + + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[0], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[0], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[1], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[1], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[2], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[2], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[3], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[3], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[4], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[4], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[5], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[5], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[6], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[6], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[7], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[7], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[8], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[8], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[9], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[9], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[10], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[10], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[11], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[11], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[12], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[12], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[13], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[13], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[14], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[14], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[15], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[15], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[16], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[16], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[17], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[17], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[18], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[18], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[19], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[19], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[20], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[20], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[21], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[21], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[22], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[22], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[23], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[23], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[24], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[24], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[25], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[25], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[26], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[26], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[27], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[27], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[28], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[28], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[29], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[29], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[30], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[30], tsdih, thdih, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), negedge DI[31], tsdil, thdil, shDI_notifier); + $setuphold(posedge CK &&& (chk_DI===1'b1), posedge DI[31], tsdih, thdih, shDI_notifier); + + $period(posedge CK, tcyc, mpwCK_notifier); + $width(negedge CK, tlck, 0, mpwCK_notifier); + $width(posedge CK, thck, 0, pwhCK_notifier); + +endspecify + +endmodule +`endcelldefine diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/rec_DF_RAM1_wrapper.v b/demo_chip_rtl/rtl/nova/tags/Start/src/rec_DF_RAM1_wrapper.v new file mode 100644 index 0000000..f084bf4 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/rec_DF_RAM1_wrapper.v @@ -0,0 +1,66 @@ +//-------------------------------------------------------------------------------------------------- +// Design : H264Decoder +// Author : KE XU +// Email : kexu@ee.cuhk.edu.hk +// File : rec_DF_RAM1.v +// Generated : Dec 7 2005 +//------------------------------------------------------------------------------------------------- +// +// Description : SRAM between reconstruction and deblocking filter (96x32bit) +//------------------------------------------------------------------------------------------------- +`timescale 1ns/1ns +module rec_DF_RAM1_wrapper (clk,gclk_rec_DF_RAM1,reset_n, + rec_DF_RAM1_cs_n,rec_DF_RAM1_wr,rec_DF_RAM1_addr,rec_DF_RAM1_din,rec_DF_RAM1_dout); + input clk; + input gclk_rec_DF_RAM1; + input reset_n; + input rec_DF_RAM1_cs_n; + input rec_DF_RAM1_wr; + input [6:0] rec_DF_RAM1_addr; + input [31:0] rec_DF_RAM1_din; + output [31:0] rec_DF_RAM1_dout; + + reg rec_DF_RAM1_OEN; + always @ (posedge clk) + if (reset_n == 1'b0) + rec_DF_RAM1_OEN <= 1'b1; + else if (!rec_DF_RAM1_cs_n && !rec_DF_RAM1_wr) + rec_DF_RAM1_OEN <= 1'b0; + else + rec_DF_RAM1_OEN <= 1'b1; + + wire rec_DF_RAM1_CEN; + assign rec_DF_RAM1_CEN = rec_DF_RAM1_cs_n & rec_DF_RAM1_OEN; + + rec_DF_RAM1_96x32 rec_DF_RAM1_96x32 ( + .CK(gclk_rec_DF_RAM1), + .ADR(rec_DF_RAM1_addr), + .DI(rec_DF_RAM1_din), + .WEN(~rec_DF_RAM1_wr), + .CEN(rec_DF_RAM1_CEN), + .OEN(rec_DF_RAM1_OEN), + .DOUT(rec_DF_RAM1_dout) + ); +endmodule +/* +module rec_DF_RAM1_96x32 (CK,ADR,DI,WEN,CEN,OEN,DOUT); + input CK; + input [6:0] ADR; + input [31:0] DI; + input WEN; + input CEN; + input OEN; + output [31:0] DOUT; + reg [31:0] DOUT; + reg [31:0] RAM [0:95]; + + always @ (posedge CK) + if (!CEN && !WEN) + RAM[ADR] <= DI; + + always @ (posedge CK) + if (!CEN && !OEN) + DOUT <= RAM[ADR]; +endmodule*/ + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/rec_DF_RAM_ctrl.v b/demo_chip_rtl/rtl/nova/tags/Start/src/rec_DF_RAM_ctrl.v new file mode 100644 index 0000000..70bb696 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/rec_DF_RAM_ctrl.v @@ -0,0 +1,173 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : rec_DF_RAM_ctrl.v +// Generated : Nov 3, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Controller for rec_DF_RAM0 & rec_DF_RAM1,single port SRAM +// write during reconstruction,read during DF +// assume "_wr" & "_rd" are both high active +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module rec_DF_RAM_ctrl (clk,reset_n,disable_DF,end_of_MB_DEC, + DF_edge_counter_MR,one_edge_counter_MR, + blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out, + blk4x4_sum_counter,blk4x4_rec_counter_2_raster_order,rec_DF_RAM0_dout,rec_DF_RAM1_dout, + + rec_DF_RAM_dout, + rec_DF_RAM0_wr,rec_DF_RAM0_rd,rec_DF_RAM0_addr,rec_DF_RAM0_din, + rec_DF_RAM1_wr,rec_DF_RAM1_rd,rec_DF_RAM1_addr,rec_DF_RAM1_din); + input clk,reset_n; + input disable_DF; + input end_of_MB_DEC; + input [5:0] DF_edge_counter_MR; + input [1:0] one_edge_counter_MR; + input [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out; + input [2:0] blk4x4_sum_counter; + input [4:0] blk4x4_rec_counter_2_raster_order; + input [31:0] rec_DF_RAM0_dout,rec_DF_RAM1_dout; + + output [31:0] rec_DF_RAM_dout; + output rec_DF_RAM0_wr; + output rec_DF_RAM0_rd; + output [6:0]rec_DF_RAM0_addr; + output [31:0] rec_DF_RAM0_din; + output rec_DF_RAM1_wr; + output rec_DF_RAM1_rd; + output [6:0]rec_DF_RAM1_addr; + output [31:0] rec_DF_RAM1_din; + + reg rec_DF_RAM0_wr; + reg rec_DF_RAM0_rd; + reg [6:0]rec_DF_RAM0_addr; + reg [31:0] rec_DF_RAM0_din; + reg rec_DF_RAM1_wr; + reg rec_DF_RAM1_rd; + reg [6:0]rec_DF_RAM1_addr; + reg [31:0] rec_DF_RAM1_din; + //----------------------------------------------------------------- + //Write:after reconstruction + //----------------------------------------------------------------- + wire rec_DF_RAM_wr; + wire [4:0] rec_DF_RAM_wr_addr_blk4x4; + wire [1:0] rec_DF_RAM_wr_addr_offset; + wire [6:0] rec_DF_RAM_wr_addr; + wire [31:0] rec_DF_RAM_din; + + assign rec_DF_RAM_wr = !disable_DF && (blk4x4_sum_counter[2] != 1'b1); + assign rec_DF_RAM_wr_addr_blk4x4 = {5{rec_DF_RAM_wr}} & blk4x4_rec_counter_2_raster_order; + assign rec_DF_RAM_wr_addr_offset = {2{rec_DF_RAM_wr}} & blk4x4_sum_counter[1:0]; + assign rec_DF_RAM_wr_addr = {rec_DF_RAM_wr_addr_blk4x4,2'b0} + rec_DF_RAM_wr_addr_offset; + assign rec_DF_RAM_din = (rec_DF_RAM_wr)? {blk4x4_sum_PE3_out,blk4x4_sum_PE2_out,blk4x4_sum_PE1_out,blk4x4_sum_PE0_out}:0; + //----------------------------------------------------------------- + //Read:during deblocking filter + //----------------------------------------------------------------- + wire rec_DF_RAM_rd; + reg [4:0] rec_DF_RAM_rd_addr_blk4x4; + wire [1:0] rec_DF_RAM_rd_addr_offset; + wire [6:0] rec_DF_RAM_rd_addr; + + assign rec_DF_RAM_rd = ((DF_edge_counter_MR[5] == 1'b0 && (DF_edge_counter_MR[3:0] == 4'd0 || + DF_edge_counter_MR[3:0] == 4'd1 || DF_edge_counter_MR[3:0] == 4'd2 || DF_edge_counter_MR[3:0] == 4'd3 || + DF_edge_counter_MR[3:0] == 4'd6 || DF_edge_counter_MR[3:0] == 4'd7 || DF_edge_counter_MR[3:0] == 4'd10|| + DF_edge_counter_MR[3:0] == 4'd11)) || (DF_edge_counter_MR[5] == 1'b1 && DF_edge_counter_MR[2] == 1'b0)); + + always @ (rec_DF_RAM_rd or DF_edge_counter_MR) + if (rec_DF_RAM_rd) + case (DF_edge_counter_MR) + 6'd0 :rec_DF_RAM_rd_addr_blk4x4 <= 5'd0; + 6'd1 :rec_DF_RAM_rd_addr_blk4x4 <= 5'd1; + 6'd2 :rec_DF_RAM_rd_addr_blk4x4 <= 5'd4; + 6'd3 :rec_DF_RAM_rd_addr_blk4x4 <= 5'd5; + 6'd6 :rec_DF_RAM_rd_addr_blk4x4 <= 5'd2; + 6'd7 :rec_DF_RAM_rd_addr_blk4x4 <= 5'd6; + 6'd10:rec_DF_RAM_rd_addr_blk4x4 <= 5'd3; + 6'd11:rec_DF_RAM_rd_addr_blk4x4 <= 5'd7; + 6'd16:rec_DF_RAM_rd_addr_blk4x4 <= 5'd8; + 6'd17:rec_DF_RAM_rd_addr_blk4x4 <= 5'd9; + 6'd18:rec_DF_RAM_rd_addr_blk4x4 <= 5'd12; + 6'd19:rec_DF_RAM_rd_addr_blk4x4 <= 5'd13; + 6'd22:rec_DF_RAM_rd_addr_blk4x4 <= 5'd10; + 6'd23:rec_DF_RAM_rd_addr_blk4x4 <= 5'd14; + 6'd26:rec_DF_RAM_rd_addr_blk4x4 <= 5'd11; + 6'd27:rec_DF_RAM_rd_addr_blk4x4 <= 5'd15; + 6'd32:rec_DF_RAM_rd_addr_blk4x4 <= 5'd16; + 6'd33:rec_DF_RAM_rd_addr_blk4x4 <= 5'd17; + 6'd34:rec_DF_RAM_rd_addr_blk4x4 <= 5'd18; + 6'd35:rec_DF_RAM_rd_addr_blk4x4 <= 5'd19; + 6'd40:rec_DF_RAM_rd_addr_blk4x4 <= 5'd20; + 6'd41:rec_DF_RAM_rd_addr_blk4x4 <= 5'd21; + 6'd42:rec_DF_RAM_rd_addr_blk4x4 <= 5'd22; + 6'd43:rec_DF_RAM_rd_addr_blk4x4 <= 5'd23; + default:rec_DF_RAM_rd_addr_blk4x4 <= 0; + endcase + else + rec_DF_RAM_rd_addr_blk4x4 <= 0; + + assign rec_DF_RAM_rd_addr_offset = one_edge_counter_MR; + assign rec_DF_RAM_rd_addr = {rec_DF_RAM_rd_addr_blk4x4,2'b0} + rec_DF_RAM_rd_addr_offset; + + //---------------------------------------------------------------------------------- + //Generate control signals for rec_DF_RAM0 & rec_DF_RAM1 + //---------------------------------------------------------------------------------- + reg rec_DF_RAM_sel; //0:rec_DF_RAM0 at reconstruction stage + //0:rec_DF_RAM1 at DF stage + //1:rec_DF_RAM0 at DF stage + //1:rec_DF_RAM1 at reconstruction stage + always @ (posedge clk) + if (reset_n == 1'b0) + rec_DF_RAM_sel <= 1'b0; + else if (end_of_MB_DEC) + rec_DF_RAM_sel <= ~ rec_DF_RAM_sel; + + assign rec_DF_RAM_dout = (rec_DF_RAM_sel == 1'b0)? rec_DF_RAM1_dout:rec_DF_RAM0_dout; + + always @ (rec_DF_RAM_sel + or rec_DF_RAM_wr or rec_DF_RAM_wr_addr or rec_DF_RAM_din + or rec_DF_RAM_rd or rec_DF_RAM_rd_addr) + case (rec_DF_RAM_sel) + 1'b0: //rec_DF_RAM0 at reconstruction stage,rec_DF_RAM1 at DF stage + begin + rec_DF_RAM0_wr <= rec_DF_RAM_wr; + rec_DF_RAM0_rd <= 1'b0; + rec_DF_RAM0_addr <= rec_DF_RAM_wr_addr; + rec_DF_RAM0_din <= rec_DF_RAM_din; + + rec_DF_RAM1_wr <= 1'b0; + rec_DF_RAM1_rd <= rec_DF_RAM_rd; + rec_DF_RAM1_addr <= rec_DF_RAM_rd_addr; + rec_DF_RAM1_din <= 0; + end + 1'b1: //rec_DF_RAM0 at DF stage,rec_DF_RAM1 at reconstruction stage + begin + rec_DF_RAM0_wr <= 1'b0; + rec_DF_RAM0_rd <= rec_DF_RAM_rd; + rec_DF_RAM0_addr <= rec_DF_RAM_rd_addr; + rec_DF_RAM0_din <= 0; + + rec_DF_RAM1_wr <= rec_DF_RAM_wr; + rec_DF_RAM1_rd <= 1'b0; + rec_DF_RAM1_addr <= rec_DF_RAM_wr_addr; + rec_DF_RAM1_din <= rec_DF_RAM_din; + end + endcase +endmodule + + + + + + + + + + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/rec_gclk_gen.v b/demo_chip_rtl/rtl/nova/tags/Start/src/rec_gclk_gen.v new file mode 100644 index 0000000..1d4214c --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/rec_gclk_gen.v @@ -0,0 +1,427 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : rec_gclk_gen.v +// Generated : Jan 3, 2006 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Gated clock generation module for reconstruction +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module rec_gclk_gen(clk, + //IQIT + end_of_NonZeroCoeff_CAVLC,OneD_counter,TwoD_counter,rescale_counter, + rounding_counter,residual_state,cavlc_decoder_state, + gclk_1D,gclk_2D,gclk_rescale,gclk_rounding, + //Intra pred + mb_num_h,mb_num_v,NextMB_IsSkip, + mb_type_general,blk4x4_rec_counter,blk4x4_sum_counter,blk4x4_intra_preload_counter, + blk4x4_intra_precompute_counter,blk4x4_intra_calculate_counter, + Intra4x4_predmode,Intra16x16_predmode,Intra_chroma_predmode, + gclk_intra_mbAddrA_luma,gclk_intra_mbAddrA_Cb,gclk_intra_mbAddrA_Cr, + gclk_intra_mbAddrB,gclk_intra_mbAddrC_luma,gclk_intra_mbAddrD,gclk_seed, + //Inter pred + blk4x4_inter_preload_counter,gclk_Inter_ref_rf, + //sum + Inter_blk4x4_pred_output_valid,gclk_pred_output,gclk_blk4x4_sum, + //Deblocking filter + end_of_MB_DEC,end_of_BS_DEC,DF_duration, + gclk_end_of_MB_DEC,gclk_DF, + //memory + Intra_mbAddrB_RAM_rd,Intra_mbAddrB_RAM_wr,gclk_Intra_mbAddrB_RAM, + rec_DF_RAM0_cs_n,gclk_rec_DF_RAM0, + rec_DF_RAM1_cs_n,gclk_rec_DF_RAM1, + DF_mbAddrA_RF_rd,DF_mbAddrA_RF_wr,gclk_DF_mbAddrA_RF, + DF_mbAddrB_RAM_rd,DF_mbAddrB_RAM_wr,gclk_DF_mbAddrB_RAM + ); + input clk; + //IQIT + input end_of_NonZeroCoeff_CAVLC; + input [2:0] OneD_counter; + input [2:0] TwoD_counter; + input [2:0] rescale_counter; + input [2:0] rounding_counter; + input [3:0] residual_state; + input [3:0] cavlc_decoder_state; + output gclk_1D; + output gclk_2D; + output gclk_rescale; + output gclk_rounding; + //Intra pred + input [3:0] mb_num_h; + input [3:0] mb_num_v; + input NextMB_IsSkip; + input [3:0] mb_type_general; + input [4:0] blk4x4_rec_counter; + input [2:0] blk4x4_sum_counter; + input [2:0] blk4x4_intra_preload_counter; + input [3:0] blk4x4_intra_precompute_counter; + input [2:0] blk4x4_intra_calculate_counter; + input [3:0] Intra4x4_predmode; + input [1:0] Intra16x16_predmode; + input [1:0] Intra_chroma_predmode; + output gclk_intra_mbAddrA_luma; + output gclk_intra_mbAddrA_Cb; + output gclk_intra_mbAddrA_Cr; + output gclk_intra_mbAddrB; + output gclk_intra_mbAddrC_luma; + output gclk_intra_mbAddrD; + output gclk_seed; + //Inter pred + input [5:0] blk4x4_inter_preload_counter; + output gclk_Inter_ref_rf; + //sum + input [1:0] Inter_blk4x4_pred_output_valid; + output gclk_pred_output; + output gclk_blk4x4_sum; + //DF + input end_of_MB_DEC; + input end_of_BS_DEC; + input DF_duration; + output gclk_end_of_MB_DEC; + output gclk_DF; + //memory + input Intra_mbAddrB_RAM_rd; + input Intra_mbAddrB_RAM_wr; + output gclk_Intra_mbAddrB_RAM; + input rec_DF_RAM0_cs_n; + output gclk_rec_DF_RAM0; + input rec_DF_RAM1_cs_n; + output gclk_rec_DF_RAM1; + input DF_mbAddrA_RF_rd,DF_mbAddrA_RF_wr; + output gclk_DF_mbAddrA_RF; + input DF_mbAddrB_RAM_rd,DF_mbAddrB_RAM_wr; + output gclk_DF_mbAddrB_RAM; + + parameter rst_residual = 4'b0000; + parameter Intra16x16DCLevel_s = 4'b0001; + parameter Intra16x16ACLevel_s = 4'b0011; + parameter Intra16x16ACLevel_0_s = 4'b0010; + parameter LumaLevel_s = 4'b0110; + parameter LumaLevel_0_s = 4'b0111; + parameter ChromaDCLevel_Cb_s = 4'b0101; + parameter ChromaDCLevel_Cr_s = 4'b0100; + parameter ChromaACLevel_Cb_s = 4'b1100; + parameter ChromaACLevel_Cr_s = 4'b1101; + + parameter Intra4x4_Vertical = 4'b0000; + parameter Intra4x4_Horizontal = 4'b0001; + parameter Intra4x4_DC = 4'b0010; + parameter Intra4x4_Diagonal_Down_Left = 4'b0011; + parameter Intra4x4_Diagonal_Down_Right = 4'b0100; + parameter Intra4x4_Vertical_Right = 4'b0101; + parameter Intra4x4_Horizontal_Down = 4'b0110; + parameter Intra4x4_Vertical_Left = 4'b0111; + parameter Intra4x4_Horizontal_Up = 4'b1000; + + parameter Intra16x16_Plane = 2'b11; + parameter Intra_chroma_Plane = 2'b11; + + parameter NumCoeffTrailingOnes_LUT = 4'b0010; + //------------------------------------------------- + //IQIT + //------------------------------------------------- + //gclk_end_of_one_residual_block + //reg l_end_of_one_residual_block; + //wire gclk_end_of_one_residual_block; + //always @ (clk or end_of_one_residual_block) + // if (!clk) l_end_of_one_residual_block <= end_of_one_residual_block; + //assign gclk_end_of_one_residual_block = clk & l_end_of_one_residual_block; + + //gclk_endof1NonZeroCoeffResBlk + //reg l_end_of_NonZeroCoeff_CAVLC; + //wire gclk_endof1NonZeroCoeffResBlk; + //always @ (clk or end_of_NonZeroCoeff_CAVLC) + // if (!clk) l_end_of_NonZeroCoeff_CAVLC <= end_of_NonZeroCoeff_CAVLC; + //assign gclk_endof1NonZeroCoeffResBlk = clk & l_end_of_NonZeroCoeff_CAVLC; + + //gclk_1D + wire OneD_en; + reg l_OneD_en; + wire gclk_1D; + assign OneD_en = ( + // trap DC case after CAVLC:residual_state is still available now + (end_of_NonZeroCoeff_CAVLC == 1'b1 && cavlc_decoder_state != `NumCoeffTrailingOnes_LUT && + (residual_state == `Intra16x16DCLevel_s || residual_state == `ChromaDCLevel_Cb_s || + residual_state == `ChromaDCLevel_Cr_s)) || + // trap AC case after rescale:residual_state is still available now + ((residual_state == `Intra16x16ACLevel_s || residual_state == `LumaLevel_s || residual_state == `ChromaACLevel_Cb_s || + residual_state == `ChromaACLevel_Cr_s) && rescale_counter == 3'b100) || + // trap internal loop + OneD_counter != 0); + always @ (clk or OneD_en) + if (!clk) l_OneD_en <= OneD_en; + assign gclk_1D = clk & l_OneD_en; + + //gclk_2D + wire TwoD_en; + reg l_TwoD_en; + wire gclk_2D; + assign TwoD_en = ((OneD_counter == 3'b001 && residual_state != `ChromaDCLevel_Cb_s && residual_state != `ChromaDCLevel_Cr_s) + || TwoD_counter != 0); + always @ (clk or TwoD_en) + if (!clk) l_TwoD_en <= TwoD_en; + assign gclk_2D = clk & l_TwoD_en; + + //gclk_rescale + wire rescale_en; + reg l_rescale_en; + wire gclk_rescale; + assign rescale_en = ( + //trap AC after CAVLC except all zero coeffs case + (end_of_NonZeroCoeff_CAVLC == 1'b1 && cavlc_decoder_state != `NumCoeffTrailingOnes_LUT && ( + residual_state == `Intra16x16ACLevel_s || residual_state == `LumaLevel_s || + residual_state == `ChromaACLevel_Cb_s || residual_state == `ChromaACLevel_Cr_s)) || + //trap DC case after IDCT,chromaDC:after 1D-IDCT,lumaDC:after 2D-IDCT + ((residual_state == `Intra16x16DCLevel_s && TwoD_counter == 3'b100) || + ((residual_state == `ChromaDCLevel_Cb_s || residual_state == `ChromaDCLevel_Cr_s) && OneD_counter == 3'b001)) || + //trap internal loop + rescale_counter != 0); + always @ (clk or rescale_en) + if (!clk) l_rescale_en <= rescale_en; + and gc_rescale (gclk_rescale,clk,l_rescale_en); + + //gclk_rounding + wire rounding_en; + reg l_rounding_en; + wire gclk_rounding; + assign rounding_en = (((residual_state == `Intra16x16ACLevel_s || residual_state == `LumaLevel_s || + residual_state == `ChromaACLevel_Cb_s || residual_state == `ChromaACLevel_Cr_s) && TwoD_counter == 3'b100) + || rounding_counter !=0)?1'b1:1'b0; + always @ (clk or rounding_en) + if (!clk) l_rounding_en <= rounding_en; + assign gclk_rounding = clk & l_rounding_en; + //------------------------------------------------- + //Intra pred + //------------------------------------------------- + //1.gclk_intra_mbAddrA_luma @ Intra_pred_reg_ctrl.v + // For intra pred,update after every blk4x4 is summed + // For inter pred,update after blk4x4 5,7,13,15 is summed + wire intra_mbAddrA_luma_ena; + reg l_intra_mbAddrA_luma_ena; + wire gclk_intra_mbAddrA_luma; + wire Is_LumaRightMostBlk4x4; + + assign Is_LumaRightMostBlk4x4 = (blk4x4_rec_counter == 5 || blk4x4_rec_counter == 7 || + blk4x4_rec_counter == 13 || blk4x4_rec_counter == 15); + + assign intra_mbAddrA_luma_ena = (blk4x4_rec_counter < 16 && blk4x4_sum_counter == 3'd3 && ( + //Intra4x4:update when every blk4x4 summed + (mb_type_general[3:2] == 2'b11 && !(mb_num_h == 10 && Is_LumaRightMostBlk4x4)) || + //Intra16x16 && Inter (including skip MB):update when blk4x4 5/7/13/15 is summed + //and NextMB_IsSkip is false + (mb_type_general[3:2] != 2'b11 && mb_num_h != 10 && Is_LumaRightMostBlk4x4 && !NextMB_IsSkip))); + always @ (clk or intra_mbAddrA_luma_ena) + if (!clk) l_intra_mbAddrA_luma_ena <= intra_mbAddrA_luma_ena; + assign gclk_intra_mbAddrA_luma = l_intra_mbAddrA_luma_ena & clk; + + //2.gclk_intra_mbAddrA_Cb @ Intra_pred_reg_ctrl.v + wire intra_mbAddrA_Cb_ena; + reg l_intra_mbAddrA_Cb_ena; + wire gclk_intra_mbAddrA_Cb; + wire Is_CbRightMostBlk4x4; + assign Is_CbRightMostBlk4x4 = (blk4x4_rec_counter == 17 || blk4x4_rec_counter == 19); + + assign intra_mbAddrA_Cb_ena = (blk4x4_sum_counter == 3'd3 && ( + //Intra4x4 + (mb_type_general[3:2] == 2'b11 && mb_num_h != 10 && Is_CbRightMostBlk4x4) || + //Intra16x16 && Inter (including skip MB) + (mb_type_general[3:2] != 2'b11 && mb_num_h != 10 && Is_CbRightMostBlk4x4 && !NextMB_IsSkip))); + always @ (clk or intra_mbAddrA_Cb_ena) + if (!clk) l_intra_mbAddrA_Cb_ena <= intra_mbAddrA_Cb_ena; + assign gclk_intra_mbAddrA_Cb = l_intra_mbAddrA_Cb_ena & clk; + + //3.gclk_intra_mbAddrA_Cr @ Intra_pred_reg_ctrl.v + wire intra_mbAddrA_Cr_ena; + reg l_intra_mbAddrA_Cr_ena; + wire gclk_intra_mbAddrA_Cr; + wire Is_CrRightMostBlk4x4; + assign Is_CrRightMostBlk4x4 = (blk4x4_rec_counter == 21 || blk4x4_rec_counter == 23); + assign intra_mbAddrA_Cr_ena = (blk4x4_sum_counter == 3'd3 && ( + //Intra4x4 + (mb_type_general[3:2] == 2'b11 && mb_num_h != 10 && Is_CrRightMostBlk4x4) || + //Intra16x16 && Inter (including skip MB) + (mb_type_general[3:2] != 2'b11 && mb_num_h != 10 && Is_CrRightMostBlk4x4 && !NextMB_IsSkip))); + always @ (clk or intra_mbAddrA_Cr_ena) + if (!clk) l_intra_mbAddrA_Cr_ena <= intra_mbAddrA_Cr_ena; + assign gclk_intra_mbAddrA_Cr = l_intra_mbAddrA_Cr_ena & clk; + + //4.gclk_intra_mbAddrB @ Intra_pred_reg_ctrl.v + // Control the write of Intra_mbAddrB_reg0 ~ reg 15 + wire intra_mbAddrB_ena; + reg l_intra_mbAddrB_ena; + wire gclk_intra_mbAddrB; + assign intra_mbAddrB_ena = ( + // Intra4x4 + (mb_type_general[3:2] == 2'b11 && blk4x4_rec_counter < 16 && + (blk4x4_intra_preload_counter == 1 || blk4x4_sum_counter[2] != 1'b1)) || + // Intra16x16 + (mb_type_general[3:2] == 2'b10 && blk4x4_rec_counter < 16 && blk4x4_intra_preload_counter !=0) || + // Intra chroma + (mb_type_general[3] == 1'b1 && blk4x4_rec_counter > 15 && blk4x4_intra_preload_counter !=0)); + always @ (clk or intra_mbAddrB_ena) + if (!clk) l_intra_mbAddrB_ena <= intra_mbAddrB_ena; + assign gclk_intra_mbAddrB = l_intra_mbAddrB_ena & clk; + + //5.gclk_intra_mbAddrC_luma @ Intra_pred_reg_ctrl.v + //1)For blkIdx=0/1/4/5,Intra_mbAddrC_reg are loaded from Intra_mbAddrB_RAM + //2)For blkIdx other than 0/1/4/5,Intra_mbAddrC_reg directly obtained from Intra_mbAddrB_reg + wire intra_mbAddrC_luma_ena; + reg l_intra_mbAddrC_luma_ena; + wire gclk_intra_mbAddrC_luma; + assign intra_mbAddrC_luma_ena = (mb_type_general[3:2] == 2'b11 && (Intra4x4_predmode == Intra4x4_Diagonal_Down_Left + || Intra4x4_predmode == Intra4x4_Vertical_Left) && blk4x4_intra_preload_counter == 3'b010); + always @ (clk or intra_mbAddrC_luma_ena) + if (!clk) l_intra_mbAddrC_luma_ena <= intra_mbAddrC_luma_ena; + assign gclk_intra_mbAddrC_luma = l_intra_mbAddrC_luma_ena & clk; + + //6.gclk_intra_mbAddrD @ Intra_pred_reg_ctrl.v + //1)For Intra4x4 blkIdx=1/4/5 or Intra16x16 & Chrom plane mode,Intra mbAddrD regs are loaded from + // Intra_mbAddrB_RAM. + //2)For blkIdx other than 1/4/5,Intra mbAddrD reg are updated during sum + wire intra_mbAddrD_ena; + reg l_intra_mbAddrD_ena; + wire gclk_intra_mbAddrD; + assign intra_mbAddrD_ena = ( + //1.Update when blkIdx = 15,19,23,from Intra_mbAddrB_RAM + // In reality,sum_counter = 0/1/2/3 are all OK for update,we choose sum_counter = 0 here + (blk4x4_sum_counter == 3'd1 && mb_num_h != 10 && mb_num_v != 0 && !NextMB_IsSkip && + (blk4x4_rec_counter == 15 || blk4x4_rec_counter == 19 || blk4x4_rec_counter == 23)) || + (mb_type_general[3:2] == 2'b11 && ( + //2.For blk4x4 1/4/5 mbAddrD reg update from Intra_mbAddrB_RAM + (blk4x4_intra_preload_counter == 3'b010 && + (Intra4x4_predmode == Intra4x4_Diagonal_Down_Right || Intra4x4_predmode == Intra4x4_Vertical_Right + || Intra4x4_predmode == Intra4x4_Horizontal_Down)) || + //3.For other blk4x4 mbAddrD reg update from sum output + (blk4x4_sum_counter == 3'd3 && ( + blk4x4_rec_counter == 0 || blk4x4_rec_counter == 1 || blk4x4_rec_counter == 4 || + blk4x4_rec_counter == 2 || blk4x4_rec_counter == 3 || blk4x4_rec_counter == 6 || + blk4x4_rec_counter == 8 || blk4x4_rec_counter == 9 || blk4x4_rec_counter == 12))))); + always @ (clk or intra_mbAddrD_ena) + if (!clk) l_intra_mbAddrD_ena <= intra_mbAddrD_ena; + assign gclk_intra_mbAddrD = l_intra_mbAddrD_ena & clk; + + //7.gclk_seed @ Intra_pred_reg_ctrl.v + wire seed_ena; + reg l_seed_ena; + wire gclk_seed; + //assign seed_ena = (blk4x4_intra_precompute_counter == 1 || ((Intra16x16_predmode == Intra16x16_Plane || + //Intra_chroma_predmode == Intra_chroma_Plane) && blk4x4_intra_calculate_counter == 3)); + + assign seed_ena = (blk4x4_intra_precompute_counter == 1 || ( + (Intra16x16_predmode == Intra16x16_Plane && ( + ((blk4x4_rec_counter == 0 || blk4x4_rec_counter == 2 || blk4x4_rec_counter == 8) && + blk4x4_intra_calculate_counter == 3'b100) || + ((blk4x4_rec_counter == 1 || blk4x4_rec_counter == 3 || blk4x4_rec_counter == 9 || + blk4x4_rec_counter == 11) && blk4x4_intra_calculate_counter == 3'b001))) || + (Intra_chroma_predmode == Intra_chroma_Plane && ( + (blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20) && blk4x4_intra_calculate_counter == 3'b100)))); + + always @ (clk or seed_ena) + if (!clk) l_seed_ena <= seed_ena; + assign gclk_seed = l_seed_ena & clk; + + //------------------------------------------------- + //Inter pred + //------------------------------------------------- + wire Inter_ref_rf_ena; + reg l_Inter_ref_rf_ena; + wire gclk_Inter_ref_rf; + assign Inter_ref_rf_ena = (blk4x4_inter_preload_counter == 0)? 1'b0:1'b1; + always @ (clk or Inter_ref_rf_ena) + if (!clk) l_Inter_ref_rf_ena <= Inter_ref_rf_ena; + assign gclk_Inter_ref_rf = l_Inter_ref_rf_ena & clk; + + //------------------------------------------------- + //sum + //------------------------------------------------- + //1.gclk_pred_output + wire pred_output_ena; + reg l_pred_output_ena; + wire gclk_pred_output; + assign pred_output_ena = (blk4x4_intra_calculate_counter != 0 || Inter_blk4x4_pred_output_valid != 0)? 1'b1:1'b0; + always @ (clk or pred_output_ena) + if (!clk) l_pred_output_ena <= pred_output_ena; + assign gclk_pred_output = l_pred_output_ena & clk; + + //2.gclk_blk4x4_sum + wire blk4x4_sum_ena; + reg l_blk4x4_sum_ena; + wire gclk_blk4x4_sum; + assign blk4x4_sum_ena = (blk4x4_sum_counter[2] != 1'b1); + always @ (clk or blk4x4_sum_ena) + if (!clk) l_blk4x4_sum_ena <= blk4x4_sum_ena; + assign gclk_blk4x4_sum = l_blk4x4_sum_ena & clk; + + //------------------------------------------------- + //deblocking filter + //------------------------------------------------- + //1.gclk_end_of_MB_DEC + reg l_end_of_MB_DEC; + wire gclk_end_of_MB_DEC; + always @ (clk or end_of_MB_DEC) + if (!clk) l_end_of_MB_DEC <= end_of_MB_DEC; + assign gclk_end_of_MB_DEC = l_end_of_MB_DEC & clk; + //2.gclk_DF + wire DF_ena; + reg l_DF_ena; + assign DF_ena = DF_duration | end_of_BS_DEC; + always @ (clk or DF_ena) + if (!clk) l_DF_ena <= DF_ena; + assign gclk_DF = l_DF_ena & clk; + + //------------------------------------------------- + //memory + //------------------------------------------------- + //gclk_Intra_mbAddrB_RAM + wire Intra_mbAddrB_RAM_ena; + reg l_Intra_mbAddrB_RAM_ena; + wire gclk_Intra_mbAddrB_RAM; + assign Intra_mbAddrB_RAM_ena = Intra_mbAddrB_RAM_rd | Intra_mbAddrB_RAM_wr; + always @ (clk or Intra_mbAddrB_RAM_ena) + if (!clk) l_Intra_mbAddrB_RAM_ena <= Intra_mbAddrB_RAM_ena; + assign gclk_Intra_mbAddrB_RAM = clk & l_Intra_mbAddrB_RAM_ena; + + //gclk_rec_DF_RAM0 + reg l_rec_DF_RAM0_ena; + wire gclk_rec_DF_RAM0; + always @ (clk or rec_DF_RAM0_cs_n) + if (!clk) l_rec_DF_RAM0_ena <= !rec_DF_RAM0_cs_n; + assign gclk_rec_DF_RAM0 = clk & l_rec_DF_RAM0_ena; + + //gclk_rec_DF_RAM1 + reg l_rec_DF_RAM1_ena; + wire gclk_rec_DF_RAM1; + always @ (clk or rec_DF_RAM1_cs_n) + if (!clk) l_rec_DF_RAM1_ena <= !rec_DF_RAM1_cs_n; + assign gclk_rec_DF_RAM1 = clk & l_rec_DF_RAM1_ena; + + //gclk_DF_mbAddrA_RF + wire DF_mbAddrA_RF_ena; + reg l_DF_mbAddrA_RF_ena; + wire gclk_DF_mbAddrA_RF; + assign DF_mbAddrA_RF_ena = DF_mbAddrA_RF_rd | DF_mbAddrA_RF_wr; + always @ (clk or DF_mbAddrA_RF_ena) + if (!clk) l_DF_mbAddrA_RF_ena <= DF_mbAddrA_RF_ena; + assign gclk_DF_mbAddrA_RF = clk & l_DF_mbAddrA_RF_ena; + + //gclk_DF_mbAddrB_RAM + wire DF_mbAddrB_RAM_ena; + reg l_DF_mbAddrB_RAM_ena; + wire gclk_DF_mbAddrB_RAM; + assign DF_mbAddrB_RAM_ena = DF_mbAddrB_RAM_rd | DF_mbAddrB_RAM_wr; + always @ (clk or DF_mbAddrB_RAM_ena) + if (!clk) l_DF_mbAddrB_RAM_ena <= DF_mbAddrB_RAM_ena; + assign gclk_DF_mbAddrB_RAM = clk & l_DF_mbAddrB_RAM_ena; + + +endmodule + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/reconstruction.v b/demo_chip_rtl/rtl/nova/tags/Start/src/reconstruction.v new file mode 100644 index 0000000..178ea1f --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/reconstruction.v @@ -0,0 +1,626 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : reconstruction.v +// Generated : Jan 3,2006 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// reconstruction top module,including: +// rec_gclk_gen +// hybrid_pipeline_ctrl +// IQIT +// Intra_pred_top +// sum +// DF_top +// rec_DF_RAM_ctrl +// rec_DF_RAM0 +// rec_DF_RAM1 +// ext_RAM_ctrl +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module reconstruction (clk,reset_n,mb_type_general,mb_num_h,mb_num_v,NextMB_IsSkip,LowerMB_IsSkip, + slice_data_state,residual_state,cavlc_decoder_state, + end_of_one_residual_block,end_of_NonZeroCoeff_CAVLC,end_of_one_frame, + Intra16x16_predmode,Intra4x4_predmode_CurrMb,Intra_chroma_predmode, + QPy,QPc,i4x4_CbCr,slice_alpha_c0_offset_div2,slice_beta_offset_div2, + CodedBlockPatternLuma,CodedBlockPatternChroma,TotalCoeff,Is_skip_run_entry, + skip_mv_calc,disable_DF, + + coeffLevel_0,coeffLevel_1,coeffLevel_2, coeffLevel_3, coeffLevel_4, coeffLevel_5, coeffLevel_6, coeffLevel_7, + coeffLevel_8,coeffLevel_9,coeffLevel_10,coeffLevel_11,coeffLevel_12,coeffLevel_13,coeffLevel_14,coeffLevel_15, + mv_is16x16,mv_below8x8, + mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3,mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3, + end_of_BS_DEC,bs_V0,bs_V1,bs_V2,bs_V3,bs_H0,bs_H1,bs_H2,bs_H3, + + trigger_CAVLC,blk4x4_rec_counter,end_of_DCBlk_IQIT,end_of_one_blk4x4_sum, + end_of_MB_DEC,gclk_end_of_MB_DEC,curr_DC_IsZero, + ext_frame_RAM0_cs_n,ext_frame_RAM0_wr,ext_frame_RAM0_addr,ext_frame_RAM0_data, + ext_frame_RAM1_cs_n,ext_frame_RAM1_wr,ext_frame_RAM1_addr,ext_frame_RAM1_data, + dis_frame_RAM_din + ); + input clk; + input reset_n; + input [3:0] mb_type_general; + input [3:0] mb_num_h; + input [3:0] mb_num_v; + input NextMB_IsSkip; + input LowerMB_IsSkip; + input [3:0] slice_data_state; + input [3:0] residual_state; + input [3:0] cavlc_decoder_state; + input end_of_one_residual_block; + input end_of_NonZeroCoeff_CAVLC; + input end_of_one_frame; + input [1:0] Intra16x16_predmode; + input [63:0] Intra4x4_predmode_CurrMb; + input [1:0] Intra_chroma_predmode; + input [5:0] QPy; + input [5:0] QPc; + input [1:0] i4x4_CbCr; + input [3:0] slice_alpha_c0_offset_div2; + input [3:0] slice_beta_offset_div2; + input [3:0] CodedBlockPatternLuma; + input [1:0] CodedBlockPatternChroma; + input [4:0] TotalCoeff; + input Is_skip_run_entry; + input skip_mv_calc; + input disable_DF; + input [8:0] coeffLevel_0, coeffLevel_1, coeffLevel_2,coeffLevel_3, coeffLevel_4, coeffLevel_5; + input [8:0] coeffLevel_6, coeffLevel_7, coeffLevel_8, coeffLevel_9,coeffLevel_10,coeffLevel_11; + input [8:0] coeffLevel_12,coeffLevel_13,coeffLevel_14,coeffLevel_15; + input mv_is16x16; + input [3:0] mv_below8x8; + input [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3; + input [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3; + input end_of_BS_DEC; + input [11:0] bs_V0,bs_V1,bs_V2,bs_V3; + input [11:0] bs_H0,bs_H1,bs_H2,bs_H3; + input [31:0] ext_frame_RAM0_data; + input [31:0] ext_frame_RAM1_data; + + output trigger_CAVLC; + output [4:0] blk4x4_rec_counter; + output end_of_DCBlk_IQIT; + output end_of_one_blk4x4_sum; + output end_of_MB_DEC; + output gclk_end_of_MB_DEC; + output curr_DC_IsZero; + + output ext_frame_RAM0_cs_n; + output ext_frame_RAM0_wr; + output [13:0] ext_frame_RAM0_addr; + + output ext_frame_RAM1_cs_n; + output ext_frame_RAM1_wr; + output [13:0] ext_frame_RAM1_addr; + + output [31:0] dis_frame_RAM_din; + + wire gclk_endof1resblk; + wire gclk_1D; + wire gclk_2D; + wire gclk_rescale; + wire gclk_rounding; + wire gclk_intra_mbAddrA_luma; + wire gclk_intra_mbAddrA_Cb; + wire gclk_intra_mbAddrA_Cr; + wire gclk_intra_mbAddrB; + wire gclk_intra_mbAddrC_luma; + wire gclk_intra_mbAddrD; + wire gclk_seed; + wire gclk_Inter_ref_rf; + wire gclk_pred_output; + wire gclk_blk4x4_sum; + wire gclk_DF; + wire gclk_end_of_MB_DEC; + + wire curr_CBPLuma_IsZero; + wire curr_DC_IsZero; + wire end_of_ACBlk4x4_IQIT; + wire end_of_one_blk4x4_intra; + wire end_of_one_blk4x4_inter; + wire end_of_one_blk4x4_sum; + wire end_of_MB_DF; + wire end_of_MB_DEC; + wire trigger_blk4x4_intra_pred; + wire trigger_blk4x4_inter_pred; + wire trigger_blk4x4_rec_sum; + wire [15:0] res_luma_DConly; + wire res_chroma_DConly; + wire res_AC; + wire res_DC; + wire res_luma; + wire [2:0] OneD_counter; + wire [2:0] TwoD_counter; + wire [2:0] rescale_counter; + wire [2:0] rounding_counter; + wire [2:0] blk4x4_intra_preload_counter; + wire [3:0] blk4x4_intra_precompute_counter; + wire [2:0] blk4x4_intra_calculate_counter; + wire [5:0] blk4x4_inter_preload_counter; + wire [3:0] blk4x4_inter_calculate_counter; + wire [1:0] Inter_chroma2x2_counter; + wire [4:0] blk4x4_rec_counter; + wire [2:0] blk4x4_sum_counter; + wire [4:0] blk4x4_rec_counter_2_raster_order; + wire [5:0] DF_edge_counter_MR; + wire [1:0] one_edge_counter_MR; + wire [1:0] Inter_blk4x4_pred_output_valid; + wire mv_below8x8_curr; + wire [3:0] pos_FracL; + + wire [3:0] Intra4x4_predmode; + wire [8:0] IQIT_output_0, IQIT_output_1, IQIT_output_2, IQIT_output_3; + wire [8:0] IQIT_output_4, IQIT_output_5, IQIT_output_6, IQIT_output_7; + wire [8:0] IQIT_output_8, IQIT_output_9, IQIT_output_10,IQIT_output_11; + wire [8:0] IQIT_output_12,IQIT_output_13,IQIT_output_14,IQIT_output_15; + wire [7:0] Intra_pred_PE0_out,Intra_pred_PE1_out,Intra_pred_PE2_out,Intra_pred_PE3_out; + wire [7:0] Inter_pred_out0,Inter_pred_out1,Inter_pred_out2,Inter_pred_out3; + wire [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out; + wire [7:0] blk4x4_pred_output0, blk4x4_pred_output1, blk4x4_pred_output2; + wire [7:0] blk4x4_pred_output4, blk4x4_pred_output5, blk4x4_pred_output6; + wire [7:0] blk4x4_pred_output8, blk4x4_pred_output9, blk4x4_pred_output10; + wire [7:0] blk4x4_pred_output12,blk4x4_pred_output13,blk4x4_pred_output14; + wire [8:0] curr_DC_scaled; + wire [23:0] sum_right_column_reg; + + wire DF_duration; + wire gclk_Intra_mbAddrB_RAM; + wire Intra_mbAddrB_RAM_rd; + wire Intra_mbAddrB_RAM_wr; + wire [6:0] Intra_mbAddrB_RAM_rd_addr,Intra_mbAddrB_RAM_wr_addr; + wire [31:0] Intra_mbAddrB_RAM_din; + wire [31:0] Intra_mbAddrB_RAM_dout; + wire gclk_DF_mbAddrA_RF; + wire DF_mbAddrA_RF_rd; + wire DF_mbAddrA_RF_wr; + wire [4:0] DF_mbAddrA_RF_rd_addr; + wire [4:0] DF_mbAddrA_RF_wr_addr; + wire [31:0] DF_mbAddrA_RF_din; + wire [31:0] DF_mbAddrA_RF_dout; + wire gclk_DF_mbAddrB_RAM; + wire DF_mbAddrB_RAM_rd,DF_mbAddrB_RAM_wr; + wire [8:0] DF_mbAddrB_RAM_addr; + wire [31:0] DF_mbAddrB_RAM_din; + wire [31:0] DF_mbAddrB_RAM_dout; + wire gclk_rec_DF_RAM0,gclk_rec_DF_RAM1; + wire [31:0] rec_DF_RAM_dout; + wire rec_DF_RAM0_wr,rec_DF_RAM1_wr; + wire rec_DF_RAM0_rd,rec_DF_RAM1_rd; + wire [6:0] rec_DF_RAM0_addr,rec_DF_RAM1_addr; + wire [31:0] rec_DF_RAM0_din,rec_DF_RAM1_din; + wire [31:0] rec_DF_RAM0_dout,rec_DF_RAM1_dout; + wire dis_frame_RAM_wr; + wire [13:0] dis_frame_RAM_wr_addr; + wire [31:0] dis_frame_RAM_din; + wire ref_frame_RAM_rd; + wire [13:0] ref_frame_RAM_rd_addr; + wire [31:0] ref_frame_RAM_dout; + + + rec_gclk_gen rec_gclk_gen ( + .clk(clk), + .end_of_NonZeroCoeff_CAVLC(end_of_NonZeroCoeff_CAVLC), + .OneD_counter(OneD_counter), + .TwoD_counter(TwoD_counter), + .rescale_counter(rescale_counter), + .rounding_counter(rounding_counter), + .residual_state(residual_state), + .cavlc_decoder_state(cavlc_decoder_state), + .gclk_1D(gclk_1D), + .gclk_2D(gclk_2D), + .gclk_rescale(gclk_rescale), + .gclk_rounding(gclk_rounding), + .mb_num_h(mb_num_h), + .mb_num_v(mb_num_v), + .NextMB_IsSkip(NextMB_IsSkip), + .mb_type_general(mb_type_general), + .blk4x4_rec_counter(blk4x4_rec_counter), + .blk4x4_sum_counter(blk4x4_sum_counter), + .blk4x4_intra_preload_counter(blk4x4_intra_preload_counter), + .blk4x4_intra_precompute_counter(blk4x4_intra_precompute_counter), + .blk4x4_intra_calculate_counter(blk4x4_intra_calculate_counter), + .Intra4x4_predmode(Intra4x4_predmode), + .Intra16x16_predmode(Intra16x16_predmode), + .Intra_chroma_predmode(Intra_chroma_predmode), + .gclk_intra_mbAddrA_luma(gclk_intra_mbAddrA_luma), + .gclk_intra_mbAddrA_Cb(gclk_intra_mbAddrA_Cb), + .gclk_intra_mbAddrA_Cr(gclk_intra_mbAddrA_Cr), + .gclk_intra_mbAddrB(gclk_intra_mbAddrB), + .gclk_intra_mbAddrC_luma(gclk_intra_mbAddrC_luma), + .gclk_intra_mbAddrD(gclk_intra_mbAddrD), + .gclk_seed(gclk_seed), + .blk4x4_inter_preload_counter(blk4x4_inter_preload_counter), + .gclk_Inter_ref_rf(gclk_Inter_ref_rf), + .Inter_blk4x4_pred_output_valid(Inter_blk4x4_pred_output_valid), + .gclk_pred_output(gclk_pred_output), + .gclk_blk4x4_sum(gclk_blk4x4_sum), + .end_of_MB_DEC(end_of_MB_DEC), + .end_of_BS_DEC(end_of_BS_DEC), + .DF_duration(DF_duration), + .gclk_end_of_MB_DEC(gclk_end_of_MB_DEC), + .gclk_DF(gclk_DF), + .Intra_mbAddrB_RAM_rd(Intra_mbAddrB_RAM_rd), + .Intra_mbAddrB_RAM_wr(Intra_mbAddrB_RAM_wr), + .gclk_Intra_mbAddrB_RAM(gclk_Intra_mbAddrB_RAM), + .rec_DF_RAM0_cs_n(rec_DF_RAM0_cs_n), + .gclk_rec_DF_RAM0(gclk_rec_DF_RAM0), + .rec_DF_RAM1_cs_n(rec_DF_RAM1_cs_n), + .gclk_rec_DF_RAM1(gclk_rec_DF_RAM1), + .DF_mbAddrA_RF_rd(DF_mbAddrA_RF_rd), + .DF_mbAddrA_RF_wr(DF_mbAddrA_RF_wr), + .gclk_DF_mbAddrA_RF(gclk_DF_mbAddrA_RF), + .DF_mbAddrB_RAM_rd(DF_mbAddrB_RAM_rd), + .DF_mbAddrB_RAM_wr(DF_mbAddrB_RAM_wr), + .gclk_DF_mbAddrB_RAM(gclk_DF_mbAddrB_RAM) + ); + hybrid_pipeline_ctrl hybrid_pipeline_ctrl ( + .clk(clk), + .reset_n(reset_n), + .mb_num_h(mb_num_h), + .mb_num_v(mb_num_v), + .blk4x4_rec_counter(blk4x4_rec_counter), + .CodedBlockPatternLuma(CodedBlockPatternLuma), + .CodedBlockPatternChroma(CodedBlockPatternChroma), + .mb_type_general(mb_type_general), + .slice_data_state(slice_data_state), + .residual_state(residual_state), + .TotalCoeff(TotalCoeff), + .Is_skip_run_entry(Is_skip_run_entry), + .skip_mv_calc(skip_mv_calc), + .end_of_one_residual_block(end_of_one_residual_block), + .end_of_DCBlk_IQIT(end_of_DCBlk_IQIT), + .end_of_ACBlk4x4_IQIT(end_of_ACBlk4x4_IQIT), + .end_of_one_blk4x4_intra(end_of_one_blk4x4_intra), + .end_of_one_blk4x4_inter(end_of_one_blk4x4_inter), + .end_of_one_blk4x4_sum(end_of_one_blk4x4_sum), + .end_of_MB_DF(end_of_MB_DF), + .disable_DF(disable_DF), + + .curr_CBPLuma_IsZero(curr_CBPLuma_IsZero), + .end_of_MB_DEC(end_of_MB_DEC), + .trigger_CAVLC(trigger_CAVLC), + .trigger_blk4x4_intra_pred(trigger_blk4x4_intra_pred), + .trigger_blk4x4_inter_pred(trigger_blk4x4_inter_pred), + .trigger_blk4x4_rec_sum(trigger_blk4x4_rec_sum) + ); + IQIT IQIT ( + .clk(clk), + .reset_n(reset_n), + .TotalCoeff(TotalCoeff), + .blk4x4_rec_counter(blk4x4_rec_counter), + .gclk_1D(gclk_1D), + .gclk_2D(gclk_2D), + .gclk_rescale(gclk_rescale), + .gclk_rounding(gclk_rounding), + .residual_state(residual_state), + .cavlc_decoder_state(cavlc_decoder_state), + .end_of_one_residual_block(end_of_one_residual_block), + .end_of_NonZeroCoeff_CAVLC(end_of_NonZeroCoeff_CAVLC), + .QPy(QPy), + .QPc(QPc), + .i4x4_CbCr(i4x4_CbCr), + .coeffLevel_ext_0({{7{coeffLevel_0[8]}},coeffLevel_0}), + .coeffLevel_ext_1({{7{coeffLevel_1[8]}},coeffLevel_1}), + .coeffLevel_ext_2({{7{coeffLevel_2[8]}},coeffLevel_2}), + .coeffLevel_ext_3({{7{coeffLevel_3[8]}},coeffLevel_3}), + .coeffLevel_ext_4({{7{coeffLevel_4[8]}},coeffLevel_4}), + .coeffLevel_ext_5({{7{coeffLevel_5[8]}},coeffLevel_5}), + .coeffLevel_ext_6({{7{coeffLevel_6[8]}},coeffLevel_6}), + .coeffLevel_ext_7({{7{coeffLevel_7[8]}},coeffLevel_7}), + .coeffLevel_ext_8({{7{coeffLevel_8[8]}},coeffLevel_8}), + .coeffLevel_ext_9({{7{coeffLevel_9[8]}},coeffLevel_9}), + .coeffLevel_ext_10({{7{coeffLevel_10[8]}},coeffLevel_10}), + .coeffLevel_ext_11({{7{coeffLevel_11[8]}},coeffLevel_11}), + .coeffLevel_ext_12({{7{coeffLevel_12[8]}},coeffLevel_12}), + .coeffLevel_ext_13({{7{coeffLevel_13[8]}},coeffLevel_13}), + .coeffLevel_ext_14({{7{coeffLevel_14[8]}},coeffLevel_14}), + .coeffLevel_ext_15({{7{coeffLevel_15[8]}},coeffLevel_15}), + + .OneD_counter(OneD_counter), + .TwoD_counter(TwoD_counter), + .rescale_counter(rescale_counter), + .rounding_counter(rounding_counter), + .curr_DC_IsZero(curr_DC_IsZero), + .curr_DC_scaled(curr_DC_scaled), + .rounding_output_0(IQIT_output_0), + .rounding_output_1(IQIT_output_1), + .rounding_output_2(IQIT_output_2), + .rounding_output_3(IQIT_output_3), + .rounding_output_4(IQIT_output_4), + .rounding_output_5(IQIT_output_5), + .rounding_output_6(IQIT_output_6), + .rounding_output_7(IQIT_output_7), + .rounding_output_8(IQIT_output_8), + .rounding_output_9(IQIT_output_9), + .rounding_output_10(IQIT_output_10), + .rounding_output_11(IQIT_output_11), + .rounding_output_12(IQIT_output_12), + .rounding_output_13(IQIT_output_13), + .rounding_output_14(IQIT_output_14), + .rounding_output_15(IQIT_output_15), + .end_of_ACBlk4x4_IQIT(end_of_ACBlk4x4_IQIT), + .end_of_DCBlk_IQIT(end_of_DCBlk_IQIT) + ); + Intra_pred_top Intra_pred_top ( + .clk(clk), + .reset_n(reset_n), + .gclk_intra_mbAddrA_luma(gclk_intra_mbAddrA_luma), + .gclk_intra_mbAddrA_Cb(gclk_intra_mbAddrA_Cb), + .gclk_intra_mbAddrA_Cr(gclk_intra_mbAddrA_Cr), + .gclk_intra_mbAddrB(gclk_intra_mbAddrB), + .gclk_intra_mbAddrC_luma(gclk_intra_mbAddrC_luma), + .gclk_intra_mbAddrD(gclk_intra_mbAddrD), + .gclk_seed(gclk_seed), + .gclk_Intra_mbAddrB_RAM(gclk_Intra_mbAddrB_RAM), + .mb_num_h(mb_num_h), + .mb_num_v(mb_num_v), + .mb_type_general(mb_type_general), + .NextMB_IsSkip(NextMB_IsSkip), + .Intra16x16_predmode(Intra16x16_predmode), + .Intra4x4_predmode_CurrMb(Intra4x4_predmode_CurrMb), + .Intra_chroma_predmode(Intra_chroma_predmode), + .blk4x4_rec_counter(blk4x4_rec_counter), + .trigger_blk4x4_intra_pred(trigger_blk4x4_intra_pred), + .blk4x4_sum_counter(blk4x4_sum_counter), + .sum_right_column_reg(sum_right_column_reg), + .blk4x4_sum_PE0_out(blk4x4_sum_PE0_out), + .blk4x4_sum_PE1_out(blk4x4_sum_PE1_out), + .blk4x4_sum_PE2_out(blk4x4_sum_PE2_out), + .blk4x4_sum_PE3_out(blk4x4_sum_PE3_out), + .blk4x4_pred_output0(blk4x4_pred_output0), + .blk4x4_pred_output1(blk4x4_pred_output1), + .blk4x4_pred_output2(blk4x4_pred_output2), + .blk4x4_pred_output4(blk4x4_pred_output4), + .blk4x4_pred_output5(blk4x4_pred_output5), + .blk4x4_pred_output6(blk4x4_pred_output6), + .blk4x4_pred_output8(blk4x4_pred_output8), + .blk4x4_pred_output9(blk4x4_pred_output9), + .blk4x4_pred_output10(blk4x4_pred_output10), + .blk4x4_pred_output12(blk4x4_pred_output12), + .blk4x4_pred_output13(blk4x4_pred_output13), + .blk4x4_pred_output14(blk4x4_pred_output14), + .Intra_mbAddrB_RAM_wr(Intra_mbAddrB_RAM_wr), + .Intra_mbAddrB_RAM_wr_addr(Intra_mbAddrB_RAM_wr_addr), + .Intra_mbAddrB_RAM_din(Intra_mbAddrB_RAM_din), + + .PE0_out(Intra_pred_PE0_out), + .PE1_out(Intra_pred_PE1_out), + .PE2_out(Intra_pred_PE2_out), + .PE3_out(Intra_pred_PE3_out), + .Intra4x4_predmode(Intra4x4_predmode), + .blk4x4_intra_preload_counter(blk4x4_intra_preload_counter), + .blk4x4_intra_precompute_counter(blk4x4_intra_precompute_counter), + .blk4x4_intra_calculate_counter(blk4x4_intra_calculate_counter), + .end_of_one_blk4x4_intra(end_of_one_blk4x4_intra), + .Intra_mbAddrB_RAM_rd(Intra_mbAddrB_RAM_rd) + ); + Inter_pred_top Inter_pred_top ( + .clk(clk), + .gclk_Inter_ref_rf(gclk_Inter_ref_rf), + .reset_n(reset_n), + .mb_num_h(mb_num_h), + .mb_num_v(mb_num_v), + .trigger_blk4x4_inter_pred(trigger_blk4x4_inter_pred), + .blk4x4_rec_counter(blk4x4_rec_counter), + .mb_type_general_bit3(mb_type_general[3]), + .mv_is16x16(mv_is16x16), + .mv_below8x8(mv_below8x8), + .mvx_CurrMb0(mvx_CurrMb0), + .mvx_CurrMb1(mvx_CurrMb1), + .mvx_CurrMb2(mvx_CurrMb2), + .mvx_CurrMb3(mvx_CurrMb3), + .mvy_CurrMb0(mvy_CurrMb0), + .mvy_CurrMb1(mvy_CurrMb1), + .mvy_CurrMb2(mvy_CurrMb2), + .mvy_CurrMb3(mvy_CurrMb3), + .ref_frame_RAM_dout(ref_frame_RAM_dout), + + .Inter_pred_out0(Inter_pred_out0), + .Inter_pred_out1(Inter_pred_out1), + .Inter_pred_out2(Inter_pred_out2), + .Inter_pred_out3(Inter_pred_out3), + .blk4x4_inter_preload_counter(blk4x4_inter_preload_counter), + .blk4x4_inter_calculate_counter(blk4x4_inter_calculate_counter), + .Inter_chroma2x2_counter(Inter_chroma2x2_counter), + .mv_below8x8_curr(mv_below8x8_curr), + .pos_FracL(pos_FracL), + .end_of_one_blk4x4_inter(end_of_one_blk4x4_inter), + .Inter_blk4x4_pred_output_valid(Inter_blk4x4_pred_output_valid), + .ref_frame_RAM_rd(ref_frame_RAM_rd), + .ref_frame_RAM_rd_addr(ref_frame_RAM_rd_addr) + ); + sum sum ( + .clk(clk), + .reset_n(reset_n), + .slice_data_state(slice_data_state), + .residual_state(residual_state), + .TotalCoeff(TotalCoeff), + .curr_CBPLuma_IsZero(curr_CBPLuma_IsZero), + .CodedBlockPatternChroma(CodedBlockPatternChroma), + .curr_DC_IsZero(curr_DC_IsZero), + .curr_DC_scaled(curr_DC_scaled), + .gclk_pred_output(gclk_pred_output), + .gclk_blk4x4_sum(gclk_blk4x4_sum), + .trigger_blk4x4_rec_sum(trigger_blk4x4_rec_sum), + .IQIT_output_0(IQIT_output_0), + .IQIT_output_1(IQIT_output_1), + .IQIT_output_2(IQIT_output_2), + .IQIT_output_3(IQIT_output_3), + .IQIT_output_4(IQIT_output_4), + .IQIT_output_5(IQIT_output_5), + .IQIT_output_6(IQIT_output_6), + .IQIT_output_7(IQIT_output_7), + .IQIT_output_8(IQIT_output_8), + .IQIT_output_9(IQIT_output_9), + .IQIT_output_10(IQIT_output_10), + .IQIT_output_11(IQIT_output_11), + .IQIT_output_12(IQIT_output_12), + .IQIT_output_13(IQIT_output_13), + .IQIT_output_14(IQIT_output_14), + .IQIT_output_15(IQIT_output_15), + .mb_type_general(mb_type_general), + .Intra4x4_predmode(Intra4x4_predmode), + .Intra16x16_predmode(Intra16x16_predmode), + .Intra_chroma_predmode(Intra_chroma_predmode), + .Intra_pred_PE0_out(Intra_pred_PE0_out), + .Intra_pred_PE1_out(Intra_pred_PE1_out), + .Intra_pred_PE2_out(Intra_pred_PE2_out), + .Intra_pred_PE3_out(Intra_pred_PE3_out), + .blk4x4_intra_calculate_counter(blk4x4_intra_calculate_counter), + .Inter_pred_out0(Inter_pred_out0), + .Inter_pred_out1(Inter_pred_out1), + .Inter_pred_out2(Inter_pred_out2), + .Inter_pred_out3(Inter_pred_out3), + .blk4x4_inter_calculate_counter(blk4x4_inter_calculate_counter), + .Inter_chroma2x2_counter(Inter_chroma2x2_counter), + .Inter_blk4x4_pred_output_valid(Inter_blk4x4_pred_output_valid), + .mv_below8x8_curr(mv_below8x8_curr), + .pos_FracL(pos_FracL), + .mb_num_h(mb_num_h), + .mb_num_v(mb_num_v), + .LowerMB_IsSkip(LowerMB_IsSkip), + + .end_of_one_blk4x4_sum(end_of_one_blk4x4_sum), + .blk4x4_sum_counter(blk4x4_sum_counter), + .blk4x4_rec_counter(blk4x4_rec_counter), + .blk4x4_sum_PE0_out(blk4x4_sum_PE0_out), + .blk4x4_sum_PE1_out(blk4x4_sum_PE1_out), + .blk4x4_sum_PE2_out(blk4x4_sum_PE2_out), + .blk4x4_sum_PE3_out(blk4x4_sum_PE3_out), + .blk4x4_rec_counter_2_raster_order(blk4x4_rec_counter_2_raster_order), + .sum_right_column_reg(sum_right_column_reg), + .blk4x4_pred_output0(blk4x4_pred_output0), + .blk4x4_pred_output1(blk4x4_pred_output1), + .blk4x4_pred_output2(blk4x4_pred_output2), + .blk4x4_pred_output4(blk4x4_pred_output4), + .blk4x4_pred_output5(blk4x4_pred_output5), + .blk4x4_pred_output6(blk4x4_pred_output6), + .blk4x4_pred_output8(blk4x4_pred_output8), + .blk4x4_pred_output9(blk4x4_pred_output9), + .blk4x4_pred_output10(blk4x4_pred_output10), + .blk4x4_pred_output12(blk4x4_pred_output12), + .blk4x4_pred_output13(blk4x4_pred_output13), + .blk4x4_pred_output14(blk4x4_pred_output14), + .Intra_mbAddrB_RAM_wr(Intra_mbAddrB_RAM_wr), + .Intra_mbAddrB_RAM_wr_addr(Intra_mbAddrB_RAM_wr_addr), + .Intra_mbAddrB_RAM_din(Intra_mbAddrB_RAM_din) + ); + DF_top DF_top ( + .clk(clk), + .reset_n(reset_n), + .gclk_DF(gclk_DF), + .gclk_end_of_MB_DEC(gclk_end_of_MB_DEC), + .gclk_DF_mbAddrA_RF(gclk_DF_mbAddrA_RF), + .gclk_DF_mbAddrB_RAM(gclk_DF_mbAddrB_RAM), + .end_of_BS_DEC(end_of_BS_DEC), + .disable_DF(disable_DF), + .mb_num_h(mb_num_h), + .mb_num_v(mb_num_v), + .bs_V0(bs_V0), + .bs_V1(bs_V1), + .bs_V2(bs_V2), + .bs_V3(bs_V3), + .bs_H0(bs_H0), + .bs_H1(bs_H1), + .bs_H2(bs_H2), + .bs_H3(bs_H3), + .QPy(QPy), + .QPc(QPc), + .slice_alpha_c0_offset_div2(slice_alpha_c0_offset_div2), + .slice_beta_offset_div2(slice_beta_offset_div2), + .blk4x4_sum_counter(blk4x4_sum_counter), + .blk4x4_rec_counter_2_raster_order(blk4x4_rec_counter_2_raster_order), + .rec_DF_RAM_dout(rec_DF_RAM_dout), + .blk4x4_sum_PE0_out(blk4x4_sum_PE0_out), + .blk4x4_sum_PE1_out(blk4x4_sum_PE1_out), + .blk4x4_sum_PE2_out(blk4x4_sum_PE2_out), + .blk4x4_sum_PE3_out(blk4x4_sum_PE3_out), + + .DF_duration(DF_duration), + .end_of_MB_DF(end_of_MB_DF), + .DF_edge_counter_MR(DF_edge_counter_MR), + .one_edge_counter_MR(one_edge_counter_MR), + .DF_mbAddrA_RF_rd(DF_mbAddrA_RF_rd), + .DF_mbAddrA_RF_wr(DF_mbAddrA_RF_wr), + .DF_mbAddrB_RAM_rd(DF_mbAddrB_RAM_rd), + .DF_mbAddrB_RAM_wr(DF_mbAddrB_RAM_wr), + .dis_frame_RAM_wr(dis_frame_RAM_wr), + .dis_frame_RAM_wr_addr(dis_frame_RAM_wr_addr), + .dis_frame_RAM_din(dis_frame_RAM_din) + ); + rec_DF_RAM_ctrl rec_DF_RAM_ctrl ( + .clk(clk), + .reset_n(reset_n), + .disable_DF(disable_DF), + .end_of_MB_DEC(end_of_MB_DEC), + .DF_edge_counter_MR(DF_edge_counter_MR), + .one_edge_counter_MR(one_edge_counter_MR), + .blk4x4_sum_PE0_out(blk4x4_sum_PE0_out), + .blk4x4_sum_PE1_out(blk4x4_sum_PE1_out), + .blk4x4_sum_PE2_out(blk4x4_sum_PE2_out), + .blk4x4_sum_PE3_out(blk4x4_sum_PE3_out), + .blk4x4_sum_counter(blk4x4_sum_counter), + .blk4x4_rec_counter_2_raster_order(blk4x4_rec_counter_2_raster_order), + .rec_DF_RAM0_dout(rec_DF_RAM0_dout), + .rec_DF_RAM1_dout(rec_DF_RAM1_dout), + + .rec_DF_RAM_dout(rec_DF_RAM_dout), + .rec_DF_RAM0_wr(rec_DF_RAM0_wr), + .rec_DF_RAM0_rd(rec_DF_RAM0_rd), + .rec_DF_RAM0_addr(rec_DF_RAM0_addr), + .rec_DF_RAM0_din(rec_DF_RAM0_din), + .rec_DF_RAM1_wr(rec_DF_RAM1_wr), + .rec_DF_RAM1_rd(rec_DF_RAM1_rd), + .rec_DF_RAM1_addr(rec_DF_RAM1_addr), + .rec_DF_RAM1_din(rec_DF_RAM1_din) + ); + ram_sync_1r_sync_1w #(`rec_DF_RAM0_data_width,`rec_DF_RAM0_data_depth) + rec_DF_RAM0 ( + .clk(gclk_rec_DF_RAM0), + .rst_n(reset_n), + .wr_n(~rec_DF_RAM0_wr), + .rd_n(~rec_DF_RAM0_rd), + .wr_addr(rec_DF_RAM0_addr), + .rd_addr(rec_DF_RAM0_addr), + .data_in(rec_DF_RAM0_din), + .data_out(rec_DF_RAM0_dout) + ); + ram_sync_1r_sync_1w #(`rec_DF_RAM1_data_width,`rec_DF_RAM1_data_depth) + rec_DF_RAM1 ( + .clk(gclk_rec_DF_RAM1), + .rst_n(reset_n), + .wr_n(~rec_DF_RAM1_wr), + .rd_n(~rec_DF_RAM1_rd), + .wr_addr(rec_DF_RAM1_addr), + .rd_addr(rec_DF_RAM1_addr), + .data_in(rec_DF_RAM1_din), + .data_out(rec_DF_RAM1_dout) + ); + ext_RAM_ctrl ext_RAM_ctrl( + .clk(clk), + .reset_n(reset_n), + .end_of_one_frame(end_of_one_frame), + .ref_frame_RAM_rd(ref_frame_RAM_rd), + .ref_frame_RAM_rd_addr(ref_frame_RAM_rd_addr), + .dis_frame_RAM_wr(dis_frame_RAM_wr), + .dis_frame_RAM_wr_addr(dis_frame_RAM_wr_addr), + //.dis_frame_RAM_din(dis_frame_RAM_din), + .ref_frame_RAM_dout(ref_frame_RAM_dout), + .ext_frame_RAM0_cs_n(ext_frame_RAM0_cs_n), + .ext_frame_RAM0_wr(ext_frame_RAM0_wr), + .ext_frame_RAM0_addr(ext_frame_RAM0_addr), + .ext_frame_RAM0_data(ext_frame_RAM0_data), + .ext_frame_RAM1_cs_n(ext_frame_RAM1_cs_n), + .ext_frame_RAM1_wr(ext_frame_RAM1_wr), + .ext_frame_RAM1_addr(ext_frame_RAM1_addr), + .ext_frame_RAM1_data(ext_frame_RAM1_data) + ); +endmodule \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/run_decoding.v b/demo_chip_rtl/rtl/nova/tags/Start/src/run_decoding.v new file mode 100644 index 0000000..ab5a77d --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/run_decoding.v @@ -0,0 +1,299 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : run_decoding.v +// Generated : June 11, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Decoding the all the remaining syntax for CAVLC +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module run_decoding (clk,reset_n,cavlc_decoder_state,BitStream_buffer_output,total_zeros, + level_0,level_1,level_2,level_3,level_4,level_5,level_6,level_7, + level_8,level_9,level_10,level_11,level_12,level_13,level_14,level_15, + TotalCoeff,i_run,i_TotalCoeff,coeffNum,IsRunLoop, + + run_of_zeros_len,zerosLeft,run, + coeffLevel_0,coeffLevel_1,coeffLevel_2, coeffLevel_3, coeffLevel_4, coeffLevel_5, coeffLevel_6, coeffLevel_7, + coeffLevel_8,coeffLevel_9,coeffLevel_10,coeffLevel_11,coeffLevel_12,coeffLevel_13,coeffLevel_14,coeffLevel_15); + input clk,reset_n; + input [3:0] cavlc_decoder_state; + input [15:0] BitStream_buffer_output; + input [3:0] total_zeros; + input [8:0] level_0,level_1,level_2,level_3,level_4,level_5,level_6,level_7; + input [8:0] level_8,level_9,level_10,level_11,level_12,level_13,level_14,level_15; + input [4:0] TotalCoeff; + input [3:0] i_run; + input [3:0] i_TotalCoeff; + input [3:0] coeffNum; + input IsRunLoop; + output [3:0] run_of_zeros_len; + output [3:0] zerosLeft; + output [3:0] run; + output [8:0] coeffLevel_0, coeffLevel_1, coeffLevel_2,coeffLevel_3, coeffLevel_4, coeffLevel_5, coeffLevel_6; + output [8:0] coeffLevel_7, coeffLevel_8, coeffLevel_9,coeffLevel_10,coeffLevel_11,coeffLevel_12,coeffLevel_13; + output [8:0] coeffLevel_14,coeffLevel_15; + + reg [3:0] run_of_zeros_len; + reg [3:0] zerosLeft; + reg [3:0] run; + reg [8:0] coeffLevel_0, coeffLevel_1, coeffLevel_2,coeffLevel_3, coeffLevel_4, coeffLevel_5, coeffLevel_6; + reg [8:0] coeffLevel_7, coeffLevel_8, coeffLevel_9,coeffLevel_10,coeffLevel_11,coeffLevel_12,coeffLevel_13; + reg [8:0] coeffLevel_14,coeffLevel_15; + + reg [3:0] run_before; + reg [3:0] zerosLeft_reg; + reg [3:0] run_0,run_1,run_2,run_3,run_4,run_5,run_6,run_7; + reg [3:0] run_8,run_9,run_10,run_11,run_12,run_13,run_14,run_15; + reg [8:0] level_output; + + //decoding Table 9-10 + always @ (cavlc_decoder_state or zerosLeft or BitStream_buffer_output) + if (cavlc_decoder_state == `run_before_LUT) + case (zerosLeft) + 0:run_of_zeros_len <= 0;//special case added for "total_zeros==0" + 1:run_of_zeros_len <= 1; + 2:run_of_zeros_len <= (BitStream_buffer_output[15] == 1)? 4'd1:4'd2; + 3:run_of_zeros_len <= 2; + 4:run_of_zeros_len <= (BitStream_buffer_output[15:14] == 2'b00)? 4'd3:4'd2; + 5:run_of_zeros_len <= (BitStream_buffer_output[15] == 1)? 4'd2:4'd3; + 6:run_of_zeros_len <= (BitStream_buffer_output[15:14] == 2'b11)? 4'd2:4'd3; + default: + if (BitStream_buffer_output[15] == 1 || BitStream_buffer_output[14] == 1 || BitStream_buffer_output[13] == 1) + run_of_zeros_len <= 3; + else if (BitStream_buffer_output[15:12] == 1) run_of_zeros_len <= 4; + else if (BitStream_buffer_output[15:11] == 1) run_of_zeros_len <= 5; + else if (BitStream_buffer_output[15:10] == 1) run_of_zeros_len <= 6; + else if (BitStream_buffer_output[15:9] == 1) run_of_zeros_len <= 7; + else if (BitStream_buffer_output[15:8] == 1) run_of_zeros_len <= 4'd8; + else if (BitStream_buffer_output[15:7] == 1) run_of_zeros_len <= 4'd9; + else if (BitStream_buffer_output[15:6] == 1) run_of_zeros_len <= 4'd10; + else if (BitStream_buffer_output[15:5] == 1) run_of_zeros_len <= 4'd11; + else run_of_zeros_len <= 0; + endcase + else + run_of_zeros_len <= 0; + + always @ (posedge clk) + if (reset_n == 0) + run_before <= 0; + else if (cavlc_decoder_state == `run_before_LUT) + case (zerosLeft) + 0:run_before <= 0;//special case added for "total_zeros==0" + 1:run_before <= (BitStream_buffer_output[15] == 0)? 4'd1:4'd0; + 2:if (BitStream_buffer_output[15] == 1) run_before <= 0; + else if (BitStream_buffer_output[15:14] == 2'b01) run_before <= 1; + else run_before <= 2; + 3:case (BitStream_buffer_output[15:14]) + 2'b00:run_before <= 3; + 2'b01:run_before <= 2; + 2'b10:run_before <= 1; + 2'b11:run_before <= 0; + endcase + 4:case (BitStream_buffer_output[15:14]) + 2'b00:run_before <= (BitStream_buffer_output[13] == 1)? 4'd3:4'd4; + 2'b01:run_before <= 2; + 2'b10:run_before <= 1; + 2'b11:run_before <= 0; + endcase + 5:case (BitStream_buffer_output[15:14]) + 2'b00:run_before <= (BitStream_buffer_output[13] == 1)? 4'd4:4'd5; + 2'b01:run_before <= (BitStream_buffer_output[13] == 1)? 4'd2:4'd3; + 2'b10:run_before <= 1; + 2'b11:run_before <= 0; + endcase + 6:casex (BitStream_buffer_output[15:13]) + 3'b11x:run_before <= 0; + 3'b000:run_before <= 1; + 3'b001:run_before <= 2; + 3'b011:run_before <= 3; + 3'b010:run_before <= 4; + 3'b101:run_before <= 5; + 3'b100:run_before <= 6; + endcase + default: + case (BitStream_buffer_output[15:13]) + 3'b000:run_before <= run_of_zeros_len + 3; + 3'b111:run_before <= 0; + 3'b110:run_before <= 1; + 3'b101:run_before <= 2; + 3'b100:run_before <= 3; + 3'b011:run_before <= 4; + 3'b010:run_before <= 5; + 3'b001:run_before <= 6; + endcase + endcase + + always @ (cavlc_decoder_state or total_zeros or run_before or zerosLeft_reg or IsRunLoop) + if (cavlc_decoder_state == `run_before_LUT) + zerosLeft <= (IsRunLoop == 0)? total_zeros:zerosLeft_reg; + else if (cavlc_decoder_state == `RunOfZeros) + zerosLeft <= zerosLeft_reg - run_before; + else + zerosLeft <= 0; + + always @ (posedge clk) + if (reset_n == 0) + zerosLeft_reg <= 0; + else if (cavlc_decoder_state == `run_before_LUT || cavlc_decoder_state == `RunOfZeros) + zerosLeft_reg <= zerosLeft; + + always @ (posedge clk) + if (reset_n == 0) + begin + run_0 <= 0; run_1 <= 0; run_2 <= 0; run_3 <= 0; + run_4 <= 0; run_5 <= 0; run_6 <= 0; run_7 <= 0; + run_8 <= 0; run_9 <= 0; run_10 <= 0; run_11 <= 0; + run_12 <= 0; run_13 <= 0; run_14 <= 0; run_15 <= 0; + end + //reset run0 ~ run15 for each 4x4 CAVLC as early as nAnB_decoding_s stage + else if (cavlc_decoder_state == `nAnB_decoding_s) + begin + run_0 <= 0; run_1 <= 0; run_2 <= 0; run_3 <= 0; + run_4 <= 0; run_5 <= 0; run_6 <= 0; run_7 <= 0; + run_8 <= 0; run_9 <= 0; run_10 <= 0; run_11 <= 0; + run_12 <= 0; run_13 <= 0; run_14 <= 0; run_15 <= 0; + end + else if (cavlc_decoder_state == `RunOfZeros) + begin + if (TotalCoeff == 1) + run_0 <= total_zeros; + else if (total_zeros == 0) + begin + run_0 <= 0; run_1 <= 0; run_2 <= 0; run_3 <= 0; + run_4 <= 0; run_5 <= 0; run_6 <= 0; run_7 <= 0; + run_8 <= 0; run_9 <= 0; run_10 <= 0; run_11 <= 0; + run_12 <= 0; run_13 <= 0; run_14 <= 0; run_15 <= 0; + end + else if ({1'b0,i_run} == TotalCoeff - 2) + case (i_run) + 0 :begin run_0 <= run_before; run_1 <= zerosLeft; end + 1 :begin run_1 <= run_before; run_2 <= zerosLeft; end + 2 :begin run_2 <= run_before; run_3 <= zerosLeft; end + 3 :begin run_3 <= run_before; run_4 <= zerosLeft; end + 4 :begin run_4 <= run_before; run_5 <= zerosLeft; end + 5 :begin run_5 <= run_before; run_6 <= zerosLeft; end + 6 :begin run_6 <= run_before; run_7 <= zerosLeft; end + 7 :begin run_7 <= run_before; run_8 <= zerosLeft; end + 8 :begin run_8 <= run_before; run_9 <= zerosLeft; end + 9 :begin run_9 <= run_before; run_10<= zerosLeft; end + 10:begin run_10<= run_before; run_11<= zerosLeft; end + 11:begin run_11<= run_before; run_12<= zerosLeft; end + 12:begin run_12<= run_before; run_13<= zerosLeft; end + 13:begin run_13<= run_before; run_14<= zerosLeft; end + endcase + else + case (i_run) + 0 :run_0 <= run_before; + 1 :run_1 <= run_before; + 2 :run_2 <= run_before; + 3 :run_3 <= run_before; + 4 :run_4 <= run_before; + 5 :run_5 <= run_before; + 6 :run_6 <= run_before; + 7 :run_7 <= run_before; + 8 :run_8 <= run_before; + 9 :run_9 <= run_before; + 10:run_10<= run_before; + 11:run_11<= run_before; + 12:run_12<= run_before; + 13:run_13<= run_before; + endcase + end + always @ (cavlc_decoder_state or i_TotalCoeff or run_0 or run_1 or run_2 or run_3 or run_4 or + run_5 or run_6 or run_7 or run_8 or run_9 or run_10 or run_11 or run_12 or run_13 or run_14) + if (cavlc_decoder_state == `LevelRunCombination) + case (i_TotalCoeff) //coeffNum = coeffNum + run[i_TotalCoeff-1] + 1; + 0 :run <= run_0; + 1 :run <= run_1; + 2 :run <= run_2; + 3 :run <= run_3; + 4 :run <= run_4; + 5 :run <= run_5; + 6 :run <= run_6; + 7 :run <= run_7; + 8 :run <= run_8; + 9 :run <= run_9; + 10:run <= run_10; + 11:run <= run_11; + 12:run <= run_12; + 13:run <= run_13; + 14:run <= run_14; + default:run <= 0; + endcase + else + run <= 0; + + always @ (i_TotalCoeff or level_0 or level_1 or level_2 or level_3 or level_4 or level_5 or level_6 or + level_7 or level_8 or level_9 or level_10 or level_11 or level_12 or level_13 or level_14 or level_15) + case (i_TotalCoeff) + 0 :level_output <= level_0; + 1 :level_output <= level_1; + 2 :level_output <= level_2; + 3 :level_output <= level_3; + 4 :level_output <= level_4; + 5 :level_output <= level_5; + 6 :level_output <= level_6; + 7 :level_output <= level_7; + 8 :level_output <= level_8; + 9 :level_output <= level_9; + 10:level_output <= level_10; + 11:level_output <= level_11; + 12:level_output <= level_12; + 13:level_output <= level_13; + 14:level_output <= level_14; + 15:level_output <= level_15; + endcase + + + always @ (posedge clk) + if (reset_n == 0) + begin + coeffLevel_0 <= 0; coeffLevel_1 <= 0; coeffLevel_2 <= 0; coeffLevel_3 <= 0; + coeffLevel_4 <= 0; coeffLevel_5 <= 0; coeffLevel_6 <= 0; coeffLevel_7 <= 0; + coeffLevel_8 <= 0; coeffLevel_9 <= 0; coeffLevel_10 <= 0; coeffLevel_11 <= 0; + coeffLevel_12 <= 0; coeffLevel_13 <= 0; coeffLevel_14 <= 0; coeffLevel_15 <= 0; + end + //Revise log: March 24,2006 + //change reset coeffLevel_0 ~ 14 at total_zeros_LUT stage + //else if (cavlc_decoder_state == RunOfZeros && //reset coeffLevel_0 ~ 14 only at last RunOfZeros + // (i_run == TotalCoeff - 1 || i_run == TotalCoeff - 2 || zerosLeft == 0)) + else if (cavlc_decoder_state == `total_zeros_LUT) + begin + coeffLevel_0 <= 0; coeffLevel_1 <= 0; coeffLevel_2 <= 0; coeffLevel_3 <= 0; + coeffLevel_4 <= 0; coeffLevel_5 <= 0; coeffLevel_6 <= 0; coeffLevel_7 <= 0; + coeffLevel_8 <= 0; coeffLevel_9 <= 0; coeffLevel_10 <= 0; coeffLevel_11 <= 0; + coeffLevel_12 <= 0; coeffLevel_13 <= 0; coeffLevel_14 <= 0; coeffLevel_15 <= 0; + end + else if (cavlc_decoder_state == `LevelRunCombination) + begin + case (coeffNum) + 0 :coeffLevel_0 <= level_output; + 1 :coeffLevel_1 <= level_output; + 2 :coeffLevel_2 <= level_output; + 3 :coeffLevel_3 <= level_output; + 4 :coeffLevel_4 <= level_output; + 5 :coeffLevel_5 <= level_output; + 6 :coeffLevel_6 <= level_output; + 7 :coeffLevel_7 <= level_output; + 8 :coeffLevel_8 <= level_output; + 9 :coeffLevel_9 <= level_output; + 10:coeffLevel_10<= level_output; + 11:coeffLevel_11<= level_output; + 12:coeffLevel_12<= level_output; + 13:coeffLevel_13<= level_output; + 14:coeffLevel_14<= level_output; + 15:coeffLevel_15<= level_output; + endcase + end + endmodule + + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/sum.v b/demo_chip_rtl/rtl/nova/tags/Start/src/sum.v new file mode 100644 index 0000000..13b0a3d --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/sum.v @@ -0,0 +1,510 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : sum.v +// Generated : Oct 29, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Sum module for residual + prediction +// Including output transpose and Intra_mbAddrB_RAM write control +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module sum (clk,reset_n,slice_data_state,residual_state,TotalCoeff,curr_CBPLuma_IsZero,CodedBlockPatternChroma, + curr_DC_IsZero,curr_DC_scaled,gclk_pred_output,gclk_blk4x4_sum,trigger_blk4x4_rec_sum, + IQIT_output_0, IQIT_output_1, IQIT_output_2, IQIT_output_3, + IQIT_output_4, IQIT_output_5, IQIT_output_6, IQIT_output_7, + IQIT_output_8, IQIT_output_9, IQIT_output_10,IQIT_output_11, + IQIT_output_12,IQIT_output_13,IQIT_output_14,IQIT_output_15, + mb_type_general,Intra4x4_predmode,Intra16x16_predmode,Intra_chroma_predmode, + Intra_pred_PE0_out,Intra_pred_PE1_out,Intra_pred_PE2_out,Intra_pred_PE3_out,blk4x4_intra_calculate_counter, + Inter_pred_out0,Inter_pred_out1,Inter_pred_out2,Inter_pred_out3,blk4x4_inter_calculate_counter,Inter_chroma2x2_counter, + Inter_blk4x4_pred_output_valid,mv_below8x8_curr,pos_FracL,mb_num_v,mb_num_h,LowerMB_IsSkip, + + end_of_one_blk4x4_sum,blk4x4_sum_counter,blk4x4_rec_counter, + blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out, + sum_right_column_reg,blk4x4_rec_counter_2_raster_order, + blk4x4_pred_output0, blk4x4_pred_output1, blk4x4_pred_output2, + blk4x4_pred_output4, blk4x4_pred_output5, blk4x4_pred_output6, + blk4x4_pred_output8, blk4x4_pred_output9, blk4x4_pred_output10, + blk4x4_pred_output12,blk4x4_pred_output13,blk4x4_pred_output14, + Intra_mbAddrB_RAM_wr,Intra_mbAddrB_RAM_wr_addr,Intra_mbAddrB_RAM_din + ); + input clk,reset_n; + input [3:0] slice_data_state; + input [3:0] residual_state; + input [4:0] TotalCoeff; + input curr_CBPLuma_IsZero; + input [1:0] CodedBlockPatternChroma; + input curr_DC_IsZero; + input [8:0] curr_DC_scaled; + input gclk_pred_output; + input gclk_blk4x4_sum; + input trigger_blk4x4_rec_sum; + //residual from IQIT + input [8:0] IQIT_output_0, IQIT_output_1, IQIT_output_2, IQIT_output_3; + input [8:0] IQIT_output_4, IQIT_output_5, IQIT_output_6, IQIT_output_7; + input [8:0] IQIT_output_8, IQIT_output_9, IQIT_output_10,IQIT_output_11; + input [8:0] IQIT_output_12,IQIT_output_13,IQIT_output_14,IQIT_output_15; + //Intra prediction output + input [3:0] mb_type_general; + input [3:0] Intra4x4_predmode; + input [1:0] Intra16x16_predmode; + input [1:0] Intra_chroma_predmode; + input [7:0] Intra_pred_PE0_out,Intra_pred_PE1_out,Intra_pred_PE2_out,Intra_pred_PE3_out; + input [2:0] blk4x4_intra_calculate_counter; + //Inter prediction output + input [7:0] Inter_pred_out0,Inter_pred_out1,Inter_pred_out2,Inter_pred_out3; + input [1:0] Inter_blk4x4_pred_output_valid; + input mv_below8x8_curr; + input [3:0] pos_FracL; + input [3:0] blk4x4_inter_calculate_counter; + input [1:0] Inter_chroma2x2_counter; + input [3:0] mb_num_h,mb_num_v; + input LowerMB_IsSkip; + + output end_of_one_blk4x4_sum; + output [2:0] blk4x4_sum_counter; + output [4:0] blk4x4_rec_counter; + output [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out; + output [23:0] sum_right_column_reg; + output [4:0] blk4x4_rec_counter_2_raster_order; + output [7:0] blk4x4_pred_output0, blk4x4_pred_output1, blk4x4_pred_output2; + output [7:0] blk4x4_pred_output4, blk4x4_pred_output5, blk4x4_pred_output6; + output [7:0] blk4x4_pred_output8, blk4x4_pred_output9, blk4x4_pred_output10; + output [7:0] blk4x4_pred_output12,blk4x4_pred_output13,blk4x4_pred_output14; + output Intra_mbAddrB_RAM_wr; + output [6:0] Intra_mbAddrB_RAM_wr_addr; + output [31:0] Intra_mbAddrB_RAM_din; + + reg [2:0] blk4x4_sum_counter; + reg [4:0] blk4x4_rec_counter; + reg [4:0] blk4x4_rec_counter_2_raster_order; + reg [23:0] sum_right_column_reg; + + reg [7:0] blk4x4_pred_output0, blk4x4_pred_output1, blk4x4_pred_output2, blk4x4_pred_output3; + reg [7:0] blk4x4_pred_output4, blk4x4_pred_output5, blk4x4_pred_output6, blk4x4_pred_output7; + reg [7:0] blk4x4_pred_output8, blk4x4_pred_output9, blk4x4_pred_output10,blk4x4_pred_output11; + reg [7:0] blk4x4_pred_output12,blk4x4_pred_output13,blk4x4_pred_output14,blk4x4_pred_output15; + + + always @ (posedge gclk_pred_output or negedge reset_n) + if (reset_n == 1'b0) + begin blk4x4_pred_output0 <= 0; blk4x4_pred_output1 <= 0; blk4x4_pred_output2 <= 0; blk4x4_pred_output3 <= 0; + blk4x4_pred_output4 <= 0; blk4x4_pred_output5 <= 0; blk4x4_pred_output6 <= 0; blk4x4_pred_output7 <= 0; + blk4x4_pred_output8 <= 0; blk4x4_pred_output9 <= 0; blk4x4_pred_output10 <= 0; blk4x4_pred_output11 <= 0; + blk4x4_pred_output12 <= 0; blk4x4_pred_output13<= 0; blk4x4_pred_output14 <= 0; blk4x4_pred_output15 <= 0; end + else if (blk4x4_intra_calculate_counter != 0) + begin + //Intra4x4DC or chromaDC intra prediction:output valid only at cycle3 by PE0 + if ((mb_type_general[3:2] == 2'b11 && blk4x4_rec_counter < 16 && Intra4x4_predmode == `Intra4x4_DC) || + (mb_type_general[3] == 1'b1 && blk4x4_rec_counter > 15 && Intra_chroma_predmode == `Intra_chroma_DC)) + begin + if (blk4x4_intra_calculate_counter == 3'd3) //Intra4x4DC or chromaDC completes calculation at cycle3 by PE0 + begin + blk4x4_pred_output0 <= Intra_pred_PE0_out; blk4x4_pred_output1 <= Intra_pred_PE0_out; + blk4x4_pred_output2 <= Intra_pred_PE0_out; blk4x4_pred_output3 <= Intra_pred_PE0_out; + blk4x4_pred_output4 <= Intra_pred_PE0_out; blk4x4_pred_output5 <= Intra_pred_PE0_out; + blk4x4_pred_output6 <= Intra_pred_PE0_out; blk4x4_pred_output7 <= Intra_pred_PE0_out; + blk4x4_pred_output8 <= Intra_pred_PE0_out; blk4x4_pred_output9 <= Intra_pred_PE0_out; + blk4x4_pred_output10 <= Intra_pred_PE0_out; blk4x4_pred_output11 <= Intra_pred_PE0_out; + blk4x4_pred_output12 <= Intra_pred_PE0_out; blk4x4_pred_output13 <= Intra_pred_PE0_out; + blk4x4_pred_output14 <= Intra_pred_PE0_out; blk4x4_pred_output15 <= Intra_pred_PE0_out; + end + end + //Intra16x16DC intra prediction:output valid only at cycle1 by PE0 + else if (mb_type_general[3:2] == 2'b10 && blk4x4_rec_counter < 16 && Intra16x16_predmode == `Intra16x16_DC) + begin + if (blk4x4_rec_counter == 0 && blk4x4_intra_calculate_counter == 3'd1) + begin + blk4x4_pred_output0 <= Intra_pred_PE0_out; blk4x4_pred_output1 <= Intra_pred_PE0_out; + blk4x4_pred_output2 <= Intra_pred_PE0_out; blk4x4_pred_output3 <= Intra_pred_PE0_out; + blk4x4_pred_output4 <= Intra_pred_PE0_out; blk4x4_pred_output5 <= Intra_pred_PE0_out; + blk4x4_pred_output6 <= Intra_pred_PE0_out; blk4x4_pred_output7 <= Intra_pred_PE0_out; + blk4x4_pred_output8 <= Intra_pred_PE0_out; blk4x4_pred_output9 <= Intra_pred_PE0_out; + blk4x4_pred_output10 <= Intra_pred_PE0_out; blk4x4_pred_output11 <= Intra_pred_PE0_out; + blk4x4_pred_output12 <= Intra_pred_PE0_out; blk4x4_pred_output13 <= Intra_pred_PE0_out; + blk4x4_pred_output14 <= Intra_pred_PE0_out; blk4x4_pred_output15 <= Intra_pred_PE0_out; + end + end + //Besides above DC intra prediction case,other intra prediction modes output valid from cycle4 ~ cycle1 + else + case (blk4x4_intra_calculate_counter) + 3'd4:begin blk4x4_pred_output0 <= Intra_pred_PE0_out; blk4x4_pred_output4 <= Intra_pred_PE1_out; + blk4x4_pred_output8 <= Intra_pred_PE2_out; blk4x4_pred_output12 <= Intra_pred_PE3_out; end + 3'd3:begin blk4x4_pred_output1 <= Intra_pred_PE0_out; blk4x4_pred_output5 <= Intra_pred_PE1_out; + blk4x4_pred_output9 <= Intra_pred_PE2_out; blk4x4_pred_output13 <= Intra_pred_PE3_out; end + 3'd2:begin blk4x4_pred_output2 <= Intra_pred_PE0_out; blk4x4_pred_output6 <= Intra_pred_PE1_out; + blk4x4_pred_output10 <= Intra_pred_PE2_out; blk4x4_pred_output14 <= Intra_pred_PE3_out; end + 3'd1:begin blk4x4_pred_output3 <= Intra_pred_PE0_out; blk4x4_pred_output7 <= Intra_pred_PE1_out; + blk4x4_pred_output11 <= Intra_pred_PE2_out; blk4x4_pred_output15 <= Intra_pred_PE3_out; end + endcase + end + //Inter luma prediction output store + else if (Inter_blk4x4_pred_output_valid == 2'b01) + begin + if (pos_FracL == `pos_i || pos_FracL == `pos_k) + case (blk4x4_inter_calculate_counter) + 4'd7:begin blk4x4_pred_output0 <= Inter_pred_out0; blk4x4_pred_output4 <= Inter_pred_out1; + blk4x4_pred_output8 <= Inter_pred_out2; blk4x4_pred_output12 <= Inter_pred_out3; end + 4'd5:begin blk4x4_pred_output1 <= Inter_pred_out0; blk4x4_pred_output5 <= Inter_pred_out1; + blk4x4_pred_output9 <= Inter_pred_out2; blk4x4_pred_output13 <= Inter_pred_out3; end + 4'd3:begin blk4x4_pred_output2 <= Inter_pred_out0; blk4x4_pred_output6 <= Inter_pred_out1; + blk4x4_pred_output10 <= Inter_pred_out2; blk4x4_pred_output14 <= Inter_pred_out3; end + 4'd1:begin blk4x4_pred_output3 <= Inter_pred_out0; blk4x4_pred_output7 <= Inter_pred_out1; + blk4x4_pred_output11 <= Inter_pred_out2; blk4x4_pred_output15 <= Inter_pred_out3; end + endcase + else + case (blk4x4_inter_calculate_counter) + 4'd4:begin blk4x4_pred_output0 <= Inter_pred_out0; blk4x4_pred_output4 <= Inter_pred_out1; + blk4x4_pred_output8 <= Inter_pred_out2; blk4x4_pred_output12 <= Inter_pred_out3; end + 4'd3:begin blk4x4_pred_output1 <= Inter_pred_out0; blk4x4_pred_output5 <= Inter_pred_out1; + blk4x4_pred_output9 <= Inter_pred_out2; blk4x4_pred_output13 <= Inter_pred_out3; end + 4'd2:begin blk4x4_pred_output2 <= Inter_pred_out0; blk4x4_pred_output6 <= Inter_pred_out1; + blk4x4_pred_output10 <= Inter_pred_out2; blk4x4_pred_output14 <= Inter_pred_out3; end + 4'd1:begin blk4x4_pred_output3 <= Inter_pred_out0; blk4x4_pred_output7 <= Inter_pred_out1; + blk4x4_pred_output11 <= Inter_pred_out2; blk4x4_pred_output15 <= Inter_pred_out3; end + endcase + end + //Inter chroma prediction output store + else if (Inter_blk4x4_pred_output_valid == 2'b10) + case (mv_below8x8_curr) + 1'b1: + case (Inter_chroma2x2_counter) + 2'b11: + begin + blk4x4_pred_output0 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out0:0; + blk4x4_pred_output1 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out1:0; + blk4x4_pred_output4 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out2:0; + blk4x4_pred_output5 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out3:0; + end + 2'b10: + begin + blk4x4_pred_output2 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out0:0; + blk4x4_pred_output3 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out1:0; + blk4x4_pred_output6 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out2:0; + blk4x4_pred_output7 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out3:0; + end + 2'b01: + begin + blk4x4_pred_output8 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out0:0; + blk4x4_pred_output9 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out1:0; + blk4x4_pred_output12 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out2:0; + blk4x4_pred_output13 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out3:0; + end + 2'b00: + begin + blk4x4_pred_output10 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out0:0; + blk4x4_pred_output11 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out1:0; + blk4x4_pred_output14 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out2:0; + blk4x4_pred_output15 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out3:0; + end + endcase + 1'b0: + case (blk4x4_inter_calculate_counter) + 4'd4:begin blk4x4_pred_output0 <= Inter_pred_out0; blk4x4_pred_output1 <= Inter_pred_out1; + blk4x4_pred_output4 <= Inter_pred_out2; blk4x4_pred_output5 <= Inter_pred_out3; end + 4'd3:begin blk4x4_pred_output2 <= Inter_pred_out0; blk4x4_pred_output3 <= Inter_pred_out1; + blk4x4_pred_output6 <= Inter_pred_out2; blk4x4_pred_output7 <= Inter_pred_out3; end + 4'd2:begin blk4x4_pred_output8 <= Inter_pred_out0; blk4x4_pred_output9 <= Inter_pred_out1; + blk4x4_pred_output12 <= Inter_pred_out2; blk4x4_pred_output13 <= Inter_pred_out3; end + 4'd1:begin blk4x4_pred_output10 <= Inter_pred_out0; blk4x4_pred_output11 <= Inter_pred_out1; + blk4x4_pred_output14 <= Inter_pred_out2; blk4x4_pred_output15 <= Inter_pred_out3; end + endcase + endcase + + //------------------------------------------------------ + //blk4x4_sum_counter + //------------------------------------------------------ + always @ (posedge clk) + if (reset_n == 1'b0) + blk4x4_sum_counter <= 3'd4; + else if (trigger_blk4x4_rec_sum == 1'b1) + blk4x4_sum_counter <= 3'd0; + else if (blk4x4_sum_counter != 3'd4) + blk4x4_sum_counter <= blk4x4_sum_counter + 1; + + assign end_of_one_blk4x4_sum = (blk4x4_sum_counter == 3'd3)? 1'b1:1'b0; + //------------------------------------------------------ + //blk4x4_rec_counter + //------------------------------------------------------ + always @ (posedge clk) + if (reset_n == 1'b0) + blk4x4_rec_counter <= 0; + else if (blk4x4_sum_counter == 3'd3) + blk4x4_rec_counter <= (blk4x4_rec_counter == 5'd23)? 5'd0:(blk4x4_rec_counter + 1); + //------------------------------------------------------ + //reconstruction sum + //------------------------------------------------------ + + //Note:since res_blk4x4_IsAllZero has a higer priority over res_blk4x4_OnlyDC,the conditions + //to assign res_blk4x4_OnlyDC is NOT complete (but when take current assigned res_blk4x4_IsAllZero + //value into account, res_blk4x4_OnlyDC is correct!) + + //res_blk4x4_IsAllZero:curr_DC_IsZero? curr_CBPLuma_IsZero? TotalCoeff is zero? CBPChroma is zero or one? + + reg res_blk4x4_IsAllZero; + reg res_blk4x4_onlyDC; + always @ (slice_data_state or residual_state or curr_DC_IsZero or TotalCoeff + or curr_DC_IsZero or curr_CBPLuma_IsZero or CodedBlockPatternChroma) + if (slice_data_state == `skip_run_duration) + begin + res_blk4x4_IsAllZero <= 1'b1; + res_blk4x4_onlyDC <= 1'b0; + end + else + case (residual_state) + `Intra16x16ACLevel_0_s: + begin + res_blk4x4_IsAllZero <= (curr_DC_IsZero)? 1'b1:1'b0; + res_blk4x4_onlyDC <= (curr_DC_IsZero)? 1'b0:1'b1; + end + `Intra16x16ACLevel_s,`ChromaACLevel_Cb_s,`ChromaACLevel_Cr_s: + begin + res_blk4x4_IsAllZero <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b1:1'b0; + res_blk4x4_onlyDC <= (TotalCoeff == 0)? 1'b1:1'b0; + end + `LumaLevel_0_s: + begin + res_blk4x4_IsAllZero <= 1'b1; + res_blk4x4_onlyDC <= 1'b0; + end + `LumaLevel_s: + begin + res_blk4x4_IsAllZero <= (TotalCoeff == 0 || curr_CBPLuma_IsZero)? 1'b1:1'b0; + res_blk4x4_onlyDC <= 1'b0; + end + `ChromaACLevel_0_s: //CodedBlockPatternChroma == 0 or 1 + if (CodedBlockPatternChroma == 0) //CodedBlockPatternChroma == 0 + begin + res_blk4x4_IsAllZero <= 1'b1; + res_blk4x4_onlyDC <= 1'b0; + end + else //CodedBlockPatternChroma == 1 + begin + res_blk4x4_IsAllZero <= (curr_DC_IsZero)? 1'b1:1'b0; + res_blk4x4_onlyDC <= (curr_DC_IsZero)? 1'b0:1'b1; + end + default: + begin + res_blk4x4_IsAllZero <= 1'b0; + res_blk4x4_onlyDC <= 1'b0; + end + endcase + + reg [8:0] sum_PE0_a,sum_PE1_a,sum_PE2_a,sum_PE3_a; + reg [7:0] sum_PE0_b,sum_PE1_b,sum_PE2_b,sum_PE3_b; + wire sum_PE_bypass; //only one bypass signal for all sum_PE0 ~ sum_PE3 + assign sum_PE_bypass = (blk4x4_sum_counter != 3'd4 && !res_blk4x4_IsAllZero)? 1'b0:1'b1; + + sum_PE sum_PE0 ( + .a(sum_PE0_a), + .b(sum_PE0_b), + .bypass(sum_PE_bypass), + .c(blk4x4_sum_PE0_out) + ); + sum_PE sum_PE1 ( + .a(sum_PE1_a), + .b(sum_PE1_b), + .bypass(sum_PE_bypass), + .c(blk4x4_sum_PE1_out) + ); + sum_PE sum_PE2 ( + .a(sum_PE2_a), + .b(sum_PE2_b), + .bypass(sum_PE_bypass), + .c(blk4x4_sum_PE2_out) + ); + sum_PE sum_PE3 ( + .a(sum_PE3_a), + .b(sum_PE3_b), + .bypass(sum_PE_bypass), + .c(blk4x4_sum_PE3_out) + ); + + // only for statistical purpose + // synopsys translate_off + integer number_of_IsAllZero; + integer number_of_onlyDC; + initial + begin + number_of_IsAllZero = 0; + number_of_onlyDC = 0; + end + always @ (blk4x4_sum_counter) + if (blk4x4_sum_counter == 3'd2) + begin + if (res_blk4x4_IsAllZero == 1'b1) number_of_IsAllZero <= number_of_IsAllZero + 1; + else if (res_blk4x4_onlyDC == 1'b1) number_of_onlyDC <= number_of_onlyDC + 1; + end + // synopsys translate_on + + always @ (blk4x4_sum_counter or res_blk4x4_IsAllZero or res_blk4x4_onlyDC or curr_DC_scaled or + IQIT_output_0 or IQIT_output_1 or IQIT_output_2 or IQIT_output_3 or + IQIT_output_4 or IQIT_output_5 or IQIT_output_6 or IQIT_output_7 or + IQIT_output_8 or IQIT_output_9 or IQIT_output_10 or IQIT_output_11 or + IQIT_output_12 or IQIT_output_13 or IQIT_output_14 or IQIT_output_15) + if (res_blk4x4_IsAllZero) + begin sum_PE0_a <= 0; sum_PE1_a <= 0; sum_PE2_a <= 0; sum_PE3_a <= 0; end + else if (res_blk4x4_onlyDC) + begin sum_PE0_a <= curr_DC_scaled; sum_PE1_a <= curr_DC_scaled; + sum_PE2_a <= curr_DC_scaled; sum_PE3_a <= curr_DC_scaled; end + else + case (blk4x4_sum_counter) + 0:begin sum_PE0_a <= IQIT_output_0; sum_PE1_a <= IQIT_output_1; + sum_PE2_a <= IQIT_output_2; sum_PE3_a <= IQIT_output_3; end + 1:begin sum_PE0_a <= IQIT_output_4; sum_PE1_a <= IQIT_output_5; + sum_PE2_a <= IQIT_output_6; sum_PE3_a <= IQIT_output_7; end + 2:begin sum_PE0_a <= IQIT_output_8; sum_PE1_a <= IQIT_output_9; + sum_PE2_a <= IQIT_output_10;sum_PE3_a <= IQIT_output_11; end + 3:begin sum_PE0_a <= IQIT_output_12;sum_PE1_a <= IQIT_output_13; + sum_PE2_a <= IQIT_output_14;sum_PE3_a <= IQIT_output_15; end + default:begin sum_PE0_a <= 0; sum_PE1_a <= 0; sum_PE2_a <= 0; sum_PE3_a <= 0; end + endcase + always @ (blk4x4_sum_counter or + blk4x4_pred_output0 or blk4x4_pred_output1 or blk4x4_pred_output2 or blk4x4_pred_output3 or + blk4x4_pred_output4 or blk4x4_pred_output5 or blk4x4_pred_output6 or blk4x4_pred_output7 or + blk4x4_pred_output8 or blk4x4_pred_output9 or blk4x4_pred_output10 or blk4x4_pred_output11 or + blk4x4_pred_output12 or blk4x4_pred_output13 or blk4x4_pred_output14 or blk4x4_pred_output15) + case (blk4x4_sum_counter) + 0:begin sum_PE0_b <= blk4x4_pred_output0; sum_PE1_b <= blk4x4_pred_output1; + sum_PE2_b <= blk4x4_pred_output2; sum_PE3_b <= blk4x4_pred_output3; end + 1:begin sum_PE0_b <= blk4x4_pred_output4; sum_PE1_b <= blk4x4_pred_output5; + sum_PE2_b <= blk4x4_pred_output6; sum_PE3_b <= blk4x4_pred_output7; end + 2:begin sum_PE0_b <= blk4x4_pred_output8; sum_PE1_b <= blk4x4_pred_output9; + sum_PE2_b <= blk4x4_pred_output10;sum_PE3_b <= blk4x4_pred_output11; end + 3:begin sum_PE0_b <= blk4x4_pred_output12;sum_PE1_b <= blk4x4_pred_output13; + sum_PE2_b <= blk4x4_pred_output14;sum_PE3_b <= blk4x4_pred_output15; end + default:begin sum_PE0_b <= 0; sum_PE1_b <= 0; sum_PE2_b <= 0; sum_PE3_b <= 0; end + endcase + //---------------------------------------------------------------------- + //sum right most column latch for Intra mbAddrA + //---------------------------------------------------------------------- + //sum_right_column_reg: + always @ (posedge gclk_blk4x4_sum or negedge reset_n) + if (reset_n == 0) + sum_right_column_reg <= 0; + else + case (blk4x4_sum_counter) + 3'd0:sum_right_column_reg[7:0] <= blk4x4_sum_PE3_out; + 3'd1:sum_right_column_reg[15:8] <= blk4x4_sum_PE3_out; + 3'd2:sum_right_column_reg[23:16] <= blk4x4_sum_PE3_out; + endcase + + //blk4x4_rec_counter_2_raster_order: + //change from double-z order to raster order + always @ (blk4x4_rec_counter) + case (blk4x4_rec_counter) + 5'd2 :blk4x4_rec_counter_2_raster_order <= 5'd4; + 5'd3 :blk4x4_rec_counter_2_raster_order <= 5'd5; + 5'd4 :blk4x4_rec_counter_2_raster_order <= 5'd2; + 5'd5 :blk4x4_rec_counter_2_raster_order <= 5'd3; + 5'd10:blk4x4_rec_counter_2_raster_order <= 5'd12; + 5'd11:blk4x4_rec_counter_2_raster_order <= 5'd13; + 5'd12:blk4x4_rec_counter_2_raster_order <= 5'd10; + 5'd13:blk4x4_rec_counter_2_raster_order <= 5'd11; + default:blk4x4_rec_counter_2_raster_order <= blk4x4_rec_counter; + endcase + //---------------------------------------------------------------------- + //Intra_mbAddrB_RAM write control + //---------------------------------------------------------------------- + wire Is_blk4x4_rec_bottom; + assign Is_blk4x4_rec_bottom = (blk4x4_rec_counter == 5'd10 || blk4x4_rec_counter == 5'd11 || + blk4x4_rec_counter == 5'd14 || blk4x4_rec_counter == 5'd15 || blk4x4_rec_counter == 5'd18 || + blk4x4_rec_counter == 5'd19 || blk4x4_rec_counter == 5'd22 || blk4x4_rec_counter == 5'd23); + + assign Intra_mbAddrB_RAM_wr = (mb_num_v != 4'd8 && blk4x4_sum_counter == 3'd3 && Is_blk4x4_rec_bottom && !LowerMB_IsSkip); + assign Intra_mbAddrB_RAM_din = (Intra_mbAddrB_RAM_wr)? {blk4x4_sum_PE3_out,blk4x4_sum_PE2_out,blk4x4_sum_PE1_out,blk4x4_sum_PE0_out}:0; + + // base pointer, [43:0] luma, [65:44] Chroma Cb, [87:66] Chroma Cr + reg [6:0] Intra_mbAddrB_RAM_addr_bp; + always @ (Intra_mbAddrB_RAM_wr or blk4x4_rec_counter[4] or blk4x4_rec_counter[2]) + if (Intra_mbAddrB_RAM_wr) + begin + if (blk4x4_rec_counter[4] == 1'b0) Intra_mbAddrB_RAM_addr_bp <= 0; + else if (blk4x4_rec_counter[2] == 1'b0) Intra_mbAddrB_RAM_addr_bp <= 7'd44; + else Intra_mbAddrB_RAM_addr_bp <= 7'd66; + end + else Intra_mbAddrB_RAM_addr_bp <= 0; + + // shift pointer,x2 for chroma,x4 for luma + wire [5:0] Intra_mbAddrB_RAM_addr_sp; + assign Intra_mbAddrB_RAM_addr_sp = (Intra_mbAddrB_RAM_wr && blk4x4_rec_counter[4] == 1'b1)? + {1'b0,mb_num_h,1'b0}:{mb_num_h,2'b0}; + // pointer for relative address of each 4x4 block inside a MB + reg [1:0] Intra_mbAddrB_RAM_addr_ip; + always @ (Intra_mbAddrB_RAM_wr or blk4x4_rec_counter[4] or blk4x4_rec_counter[2:0]) + if (Intra_mbAddrB_RAM_wr) + begin + if (blk4x4_rec_counter[4] == 1'b0) + case (blk4x4_rec_counter[2:0]) + 3'b010:Intra_mbAddrB_RAM_addr_ip <= 2'd0; + 3'b011:Intra_mbAddrB_RAM_addr_ip <= 2'd1; + 3'b110:Intra_mbAddrB_RAM_addr_ip <= 2'd2; + 3'b111:Intra_mbAddrB_RAM_addr_ip <= 2'd3; + default:Intra_mbAddrB_RAM_addr_ip <= 0; + endcase + else + Intra_mbAddrB_RAM_addr_ip <= {1'b0,blk4x4_rec_counter[0]}; + end + else + Intra_mbAddrB_RAM_addr_ip <= 0; + + assign Intra_mbAddrB_RAM_wr_addr = Intra_mbAddrB_RAM_addr_bp + Intra_mbAddrB_RAM_addr_sp + Intra_mbAddrB_RAM_addr_ip; + + /* + // synopsys translate_off + integer tracefile; + initial + begin + tracefile = $fopen("nova_sum_output.log"); + end + + wire [6:0] mb_num; + assign mb_num = mb_num_v * 11 + mb_num_h; + + wire [1:0] blk4x4_rec_counter_M4; + assign blk4x4_rec_counter_M4 = blk4x4_rec_counter[1:0]; + + reg [8:0] pic_num; + always @ (reset_n or mb_num) + if (reset_n == 1'b0) + pic_num <= 9'b111111111; + else if (mb_num == 0) + pic_num <= pic_num + 1; + + always @ (posedge clk) + if (blk4x4_sum_counter == 0) + begin + $fdisplay (tracefile,"------------------------ Pic = %3d, MB = %3d -------------------------",pic_num,mb_num); + if (blk4x4_rec_counter < 16) + $fdisplay (tracefile," [Luma] blk4x4Idx = %2d",blk4x4_rec_counter); + else + $fdisplay (tracefile," [Chroma] blk4x4Idx = %2d",blk4x4_rec_counter_M4); + $fdisplay (tracefile," Sum output: %8d %8d %8d %8d",blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out); + end + else if (blk4x4_sum_counter != 3'd4) + $fdisplay (tracefile," %8d %8d %8d %8d",blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out); + // synopsys translate_on + */ + +endmodule + +module sum_PE (a,b,bypass,c); + input [8:0] a; //for residual from IQIT + input [7:0] b; //for prediction from intra or inter + input bypass; + output [7:0] c; + + wire [9:0] sum; + + assign sum = (bypass)? 0:({2'b0,b} + {a[8],a}); + assign c = (bypass)? b:((sum[9] == 1'b1)? 0:((sum[8] == 1'b1)? 8'd255:sum[7:0])); +endmodule + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/syntax_decoding.v b/demo_chip_rtl/rtl/nova/tags/Start/src/syntax_decoding.v new file mode 100644 index 0000000..daa91a9 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/syntax_decoding.v @@ -0,0 +1,622 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : syntax_decoding.v +// Generated : May 23, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Decoding each sytax inside the bitstream +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module syntax_decoding (clk,reset_n,mb_num_h,mb_num_v,end_of_MB_DEC,pin_disable_DF, + parser_state,nal_unit_state,seq_parameter_set_state,pic_parameter_set_state, + slice_header_state,slice_data_state,mb_pred_state,sub_mb_pred_state, + exp_golomb_decoding_output,BitStream_buffer_output,dependent_variable_decoding_output,mbPartIdx, + + nal_unit_type,start_code_prefix_found, + deblocking_filter_control_present_flag,disable_deblocking_filter_idc,disable_DF, + slice_alpha_c0_offset_div2,slice_beta_offset_div2, + mb_skip_run,NumMbPart,NumSubMbPart, + MBTypeGen_mbAddrA,MBTypeGen_mbAddrD,MBTypeGen_mbAddrB_reg, + log2_max_frame_num_minus4,log2_max_pic_order_cnt_lsb_minus4,constrained_intra_pred_flag, + num_ref_idx_active_override_flag,num_ref_idx_l0_active_minus1, + slice_type,mb_type,mb_type_general,sub_mb_type,Intra16x16_predmode,intra_chroma_pred_mode, + pic_init_qp_minus26,chroma_qp_index_offset, + rem_intra4x4_pred_mode,prev_intra4x4_pred_mode_flag,mvd,mv_below8x8); + input clk,reset_n; + input [3:0] mb_num_h,mb_num_v; + input end_of_MB_DEC; + input pin_disable_DF; + input [1:0] parser_state; + input [2:0] nal_unit_state; + input [3:0] seq_parameter_set_state; + input [3:0] pic_parameter_set_state; + input [3:0] slice_header_state; + input [3:0] slice_data_state; + input [2:0] mb_pred_state; + input [1:0] sub_mb_pred_state; + input [15:0] BitStream_buffer_output; + input [7:0] exp_golomb_decoding_output; + input [9:0] dependent_variable_decoding_output; + input [1:0] mbPartIdx; + + output [4:0] nal_unit_type; + output start_code_prefix_found; + output deblocking_filter_control_present_flag; + output [1:0] disable_deblocking_filter_idc; + output disable_DF; + output [3:0] slice_alpha_c0_offset_div2; + output [3:0] slice_beta_offset_div2; + output [6:0] mb_skip_run; + output [2:0] NumMbPart; + output [2:0] NumSubMbPart; + output [1:0] MBTypeGen_mbAddrA; + output MBTypeGen_mbAddrD; + output [21:0] MBTypeGen_mbAddrB_reg; + output [3:0] log2_max_frame_num_minus4; + output [3:0] log2_max_pic_order_cnt_lsb_minus4; + output constrained_intra_pred_flag; + output num_ref_idx_active_override_flag; + output [2:0] num_ref_idx_l0_active_minus1; + output [2:0] slice_type; + output [4:0] mb_type; + output [3:0] mb_type_general; + output [1:0] Intra16x16_predmode; + output [1:0] intra_chroma_pred_mode; + output [1:0] sub_mb_type; + output [5:0] pic_init_qp_minus26; + output [4:0] chroma_qp_index_offset; + output [2:0] rem_intra4x4_pred_mode; + output prev_intra4x4_pred_mode_flag; + output [7:0] mvd; + output [3:0] mv_below8x8; + //-------------------------- + //start_code_prefix + //-------------------------- + reg start_code_prefix_found; + always @ (parser_state or BitStream_buffer_output) + if (parser_state == `start_code_prefix) + begin + if (BitStream_buffer_output == 16'b0000000000000001) + start_code_prefix_found <= 1; + else + start_code_prefix_found <= 0; + end + else + start_code_prefix_found <= 0; + //-------------------------- + //nal_unit + //-------------------------- + reg forbidden_zero_bit; + reg [1:0] nal_ref_idc; + reg [4:0] nal_unit_type_reg; + wire [4:0] nal_unit_type; + assign nal_unit_type = (nal_unit_state == `forbidden_zero_bit_2_nal_unit_type)? BitStream_buffer_output[12:8]:nal_unit_type_reg; + always @ (posedge clk) + if (reset_n == 0) + begin + forbidden_zero_bit <= 0; + nal_ref_idc <= 0; + nal_unit_type_reg <= 0; + end + else if (nal_unit_state == `forbidden_zero_bit_2_nal_unit_type) + begin + forbidden_zero_bit <= BitStream_buffer_output[15]; + nal_ref_idc <= BitStream_buffer_output[14:13]; + nal_unit_type_reg <= nal_unit_type; + end + //-------------------------- + //seq_parameter_set + //-------------------------- + reg [7:0] profile_idc; + reg constraint_set0_flag,constraint_set1_flag,constraint_set2_flag,constraint_set3_flag; + reg [3:0] reserved_zero_4bits; + reg [7:0] level_idc; + reg [4:0] seq_parameter_set_id_sps; + reg [3:0] log2_max_frame_num_minus4; + reg [1:0] pic_order_cnt_type; + reg [3:0] log2_max_pic_order_cnt_lsb_minus4; + reg [2:0] num_ref_frames; //however,we only support 1 reference frame currently + reg gaps_in_frame_num_value_allowed_flag; + reg [3:0] pic_width_in_mbs_minus1; + reg [3:0] pic_height_in_map_units_minus1; + reg frame_mbs_only_flag; + reg direct_8x8_inference_flag; + reg frame_cropping_flag; + reg vui_parameter_present_flag; + always @ (posedge clk) + if (reset_n == 0) + begin + profile_idc <= 0; + constraint_set0_flag <= 0; + constraint_set1_flag <= 0; + constraint_set2_flag <= 0; + constraint_set3_flag <= 0; + reserved_zero_4bits <= 0; + level_idc <= 0; + seq_parameter_set_id_sps <= 0; + log2_max_frame_num_minus4 <= 0; + pic_order_cnt_type <= 0; + log2_max_pic_order_cnt_lsb_minus4 <= 0; + num_ref_frames <= 0; + gaps_in_frame_num_value_allowed_flag <= 0; + pic_width_in_mbs_minus1 <= 0; + pic_height_in_map_units_minus1 <= 0; + frame_mbs_only_flag <= 0; + direct_8x8_inference_flag <= 0; + frame_cropping_flag <= 0; + vui_parameter_present_flag <= 0; + end + else + case (seq_parameter_set_state) + `fixed_header: + begin + profile_idc <= BitStream_buffer_output[15:8]; + constraint_set0_flag <= BitStream_buffer_output[7]; + constraint_set1_flag <= BitStream_buffer_output[6]; + constraint_set2_flag <= BitStream_buffer_output[5]; + constraint_set3_flag <= BitStream_buffer_output[4]; + reserved_zero_4bits <= BitStream_buffer_output[3:0]; + end + `level_idc_s :level_idc <= BitStream_buffer_output[15:8]; + `seq_parameter_set_id_sps_s :seq_parameter_set_id_sps <= exp_golomb_decoding_output[4:0]; + `log2_max_frame_num_minus4_s :log2_max_frame_num_minus4 <= exp_golomb_decoding_output[3:0]; + `pic_order_cnt_type_s :pic_order_cnt_type <= exp_golomb_decoding_output[1:0]; + `log2_max_pic_order_cnt_lsb_minus4_s :log2_max_pic_order_cnt_lsb_minus4 <= exp_golomb_decoding_output[3:0]; + `num_ref_frames_s :num_ref_frames <= exp_golomb_decoding_output[0]; + `gaps_in_frame_num_value_allowed_flag_s:gaps_in_frame_num_value_allowed_flag <= BitStream_buffer_output[15]; + `pic_width_in_mbs_minus1_s :pic_width_in_mbs_minus1 <= exp_golomb_decoding_output[3:0]; + `pic_height_in_map_units_minus1_s :pic_height_in_map_units_minus1 <= exp_golomb_decoding_output[3:0]; + `frame_mbs_only_flag_2_frame_cropping_flag: + begin + frame_mbs_only_flag <= BitStream_buffer_output[15]; + direct_8x8_inference_flag <= BitStream_buffer_output[14]; + frame_cropping_flag <= BitStream_buffer_output[13]; + end + `vui_parameter_present_flag_s:vui_parameter_present_flag <= BitStream_buffer_output[15]; + endcase + //-------------------------- + //pic_parameter_set + //-------------------------- + reg [7:0] pic_parameter_set_id_pps; + reg [4:0] seq_parameter_set_id_pps; + reg entropy_coding_mode_flag; + reg pic_order_present_flag; + reg [2:0] num_slice_groups_minus1; + reg [2:0] num_ref_idx_l0_active_minus1; + reg [2:0] num_ref_idx_l1_active_minus1; + reg weighted_pred_flag; + reg [1:0] weighted_bipred_idc; + reg [5:0] pic_init_qp_minus26,pic_init_qs_minus26; + reg [4:0] chroma_qp_index_offset; + reg deblocking_filter_control_present_flag; + reg constrained_intra_pred_flag; + reg redundant_pic_cnt_present_flag; + always @ (posedge clk) + if (reset_n == 0) + begin + pic_parameter_set_id_pps <= 0; + seq_parameter_set_id_pps <= 0; + entropy_coding_mode_flag <= 0; + pic_order_present_flag <= 0; + num_slice_groups_minus1 <= 0; + num_ref_idx_l0_active_minus1 <= 0; + num_ref_idx_l1_active_minus1 <= 0; + weighted_pred_flag <= 0; + weighted_bipred_idc <= 0; + pic_init_qp_minus26 <= 0; + pic_init_qs_minus26 <= 0; + chroma_qp_index_offset <= 0; + deblocking_filter_control_present_flag <= 0; + constrained_intra_pred_flag <= 0; + redundant_pic_cnt_present_flag <= 0; + end + else + case (pic_parameter_set_state) + `pic_parameter_set_id_pps_s:pic_parameter_set_id_pps <= exp_golomb_decoding_output[7:0]; + `seq_parameter_set_id_pps_s:seq_parameter_set_id_pps <= exp_golomb_decoding_output[4:0]; + `entropy_coding_mode_flag_2_pic_order_present_flag: + begin + entropy_coding_mode_flag <= BitStream_buffer_output[15]; + pic_order_present_flag <= BitStream_buffer_output[14]; + end + `num_slice_groups_minus1_s :num_slice_groups_minus1 <= exp_golomb_decoding_output[2:0]; + `num_ref_idx_l0_active_minus1_pps_s:num_ref_idx_l0_active_minus1 <= exp_golomb_decoding_output[2:0]; + `num_ref_idx_l1_active_minus1_pps_s:num_ref_idx_l1_active_minus1 <= exp_golomb_decoding_output[2:0]; + `weighted_pred_flag_2_weighted_bipred_idc: + begin + weighted_pred_flag <= BitStream_buffer_output[15]; + weighted_bipred_idc <= BitStream_buffer_output[14:13]; + end + `pic_init_qp_minus26_s :pic_init_qp_minus26 <= exp_golomb_decoding_output[5:0]; + `pic_init_qs_minus26_s :pic_init_qs_minus26 <= exp_golomb_decoding_output[5:0]; + `chroma_qp_index_offset_s:chroma_qp_index_offset <= exp_golomb_decoding_output[4:0]; + `deblocking_filter_control_2_redundant_pic_cnt_present_flag: + begin + deblocking_filter_control_present_flag <= BitStream_buffer_output[15]; + constrained_intra_pred_flag <= BitStream_buffer_output[14]; + redundant_pic_cnt_present_flag <= BitStream_buffer_output[13]; + end + endcase + //-------------------------- + //slice_header + //-------------------------- + reg first_mb_in_slice; + reg [2:0] slice_type; + reg [7:0] pic_parameter_set_id_slice_header; + reg [3:0] frame_num; + reg idr_pic_id; + reg [9:0] pic_order_cnt_lsb; + reg num_ref_idx_active_override_flag; + reg [1:0] disable_deblocking_filter_idc; + reg [3:0] slice_alpha_c0_offset_div2_dec; + reg [3:0] slice_beta_offset_div2_dec; + always @ (posedge clk) + if (reset_n == 0) + begin + first_mb_in_slice <= 0; + slice_type <= 0; + pic_parameter_set_id_slice_header <= 0; + frame_num <= 0; + idr_pic_id <= 0; + pic_order_cnt_lsb <= 0; + num_ref_idx_active_override_flag <= 0; + disable_deblocking_filter_idc <= 0; + slice_alpha_c0_offset_div2_dec <= 0; + slice_beta_offset_div2_dec <= 0; + end + else + case (slice_header_state) + `first_mb_in_slice_s :first_mb_in_slice <= exp_golomb_decoding_output[0]; + `slice_type_s :slice_type <= exp_golomb_decoding_output[2:0]; + `pic_parameter_set_id_slice_header_s:pic_parameter_set_id_slice_header <= exp_golomb_decoding_output; + `frame_num_s :frame_num <= dependent_variable_decoding_output[3:0]; + `idr_pic_id_s :idr_pic_id <= exp_golomb_decoding_output[0]; + `pic_order_cnt_lsb_s :pic_order_cnt_lsb <= dependent_variable_decoding_output[9:0]; + `num_ref_idx_active_override_flag_s :num_ref_idx_active_override_flag <= BitStream_buffer_output[15]; + //num_ref_idx_l0_active_minus1_slice_header_s: + //slice_qp_delta_s:slice_qp_delta <= exp_golomb_decoding_output[5:0]; + `disable_deblocking_filter_idc_s :disable_deblocking_filter_idc <= exp_golomb_decoding_output[1:0]; + `slice_alpha_c0_offset_div2_s :slice_alpha_c0_offset_div2_dec <= exp_golomb_decoding_output[3:0]; + `slice_beta_offset_div2_s :slice_beta_offset_div2_dec <= exp_golomb_decoding_output[3:0]; + //slice_group_change_cycle_s: + endcase + + wire [3:0] slice_alpha_c0_offset_div2; + wire [3:0] slice_beta_offset_div2; + assign slice_alpha_c0_offset_div2 = {4{deblocking_filter_control_present_flag}} & slice_alpha_c0_offset_div2_dec; + assign slice_beta_offset_div2 = {4{deblocking_filter_control_present_flag}} & slice_beta_offset_div2_dec; + + reg sw_disable_DF; + always @ (posedge clk) + if (reset_n == 0) + sw_disable_DF <= 0; + else if (slice_header_state == `disable_deblocking_filter_idc_s && disable_deblocking_filter_idc == 1) + sw_disable_DF <= 1; + else + sw_disable_DF <= 0; + + assign disable_DF = sw_disable_DF | pin_disable_DF; + //-------------------------- + //slice_data + //-------------------------- + wire [6:0] mb_skip_run; + reg [6:0] mb_skip_run_reg; + reg [4:0] mb_type; + reg [3:0] mb_type_general; + reg [3:0] mb_type_general_reg; + reg [1:0] Intra16x16_predmode; + + //mb_type_general + assign mb_skip_run = (slice_data_state == `mb_skip_run_s)? exp_golomb_decoding_output[6:0]:mb_skip_run_reg; + always @ (slice_data_state or slice_type or exp_golomb_decoding_output or mb_type_general_reg) + if (slice_data_state == `skip_run_duration) + mb_type_general <= `MB_P_skip; + else if (slice_data_state == `mb_type_s) + begin + if (slice_type == 2 || slice_type == 7) //I slice + case (exp_golomb_decoding_output) + 0: mb_type_general <= `MB_Intra4x4; + 1,2,3,4,13,14,15,16: mb_type_general <= `MB_Intra16x16_CBPChroma0; + 5,6,7,8,17,18,19,20: mb_type_general <= `MB_Intra16x16_CBPChroma1; + 9,10,11,12,21,22,23,24: mb_type_general <= `MB_Intra16x16_CBPChroma2; + default: mb_type_general <= `MB_Inter16x16; + endcase + else //P slice + case (exp_golomb_decoding_output) + 0: mb_type_general <= `MB_Inter16x16; + 1: mb_type_general <= `MB_Inter16x8; + 2: mb_type_general <= `MB_Inter8x16; + 3: mb_type_general <= `MB_P_8x8; + 4: mb_type_general <= `MB_P_8x8ref0; + 5: mb_type_general <= `MB_Intra4x4; + 6,7,8,9,18,19,20,21: mb_type_general <= `MB_Intra16x16_CBPChroma0; + 10,11,12,13,22,23,24,25:mb_type_general <= `MB_Intra16x16_CBPChroma1; + 14,15,16,17,26,27,28,29:mb_type_general <= `MB_Intra16x16_CBPChroma0; + default: mb_type_general <= `MB_Inter16x8; + endcase + end + else + mb_type_general <= mb_type_general_reg; + + //Intra16x16_predmode + always @ (posedge clk) + if (reset_n == 0) + Intra16x16_predmode <= 2'b0; + else if (slice_data_state == `mb_type_s) + begin + if (slice_type == 2 || slice_type == 7) //I slice + begin + if (exp_golomb_decoding_output != 0) + case (exp_golomb_decoding_output[1:0]) + 2'b00:Intra16x16_predmode <= 2'b11; + 2'b01:Intra16x16_predmode <= 2'b00; + 2'b10:Intra16x16_predmode <= 2'b01; + 2'b11:Intra16x16_predmode <= 2'b10; + endcase + end + else if (exp_golomb_decoding_output[4:0] > 5) //P slice + case (exp_golomb_decoding_output[1:0]) + 2'b00:Intra16x16_predmode <= 2'b10; + 2'b01:Intra16x16_predmode <= 2'b11; + 2'b10:Intra16x16_predmode <= 2'b00; + 2'b11:Intra16x16_predmode <= 2'b01; + endcase + end + + always @ (posedge clk) + if (reset_n == 0) + begin + mb_skip_run_reg <= 0; + mb_type <= 0; + mb_type_general_reg <= `MB_type_rst; + end + else + case (slice_data_state) + `mb_skip_run_s:mb_skip_run_reg <= mb_skip_run; + `skip_run_duration: + begin + mb_type <= 5'd31; + mb_type_general_reg <= mb_type_general; + end + `mb_type_s: + begin + mb_type <= exp_golomb_decoding_output[4:0]; + mb_type_general_reg <= mb_type_general; + end + //pcm_byte_s: --> Currently no deal with it + //coded_block_pattern_s: --> See CodedBlockPattern_decoding.v + //mb_qp_delta_s:mb_qp_delta <= exp_golomb_decoding_output; + endcase + //Update MBTypeGen information + reg [1:0] MBTypeGen_mbAddrA; + reg MBTypeGen_mbAddrD_tmp; + reg MBTypeGen_mbAddrD; + reg [21:0] MBTypeGen_mbAddrB_reg; + always @ (posedge clk) + if (reset_n == 0) + begin + MBTypeGen_mbAddrA <= 0; + MBTypeGen_mbAddrD_tmp <= 0; + MBTypeGen_mbAddrB_reg <= 0; + end + else if (slice_data_state == `skip_run_duration && end_of_MB_DEC)//for P_skip + begin + if (mb_num_h != 10) + MBTypeGen_mbAddrA <= `MB_addrA_addrB_P_skip; + if (mb_num_h == 9) + MBTypeGen_mbAddrD_tmp <= 1'b0; + if (mb_num_v != 8) + case (mb_num_h) + 0:MBTypeGen_mbAddrB_reg[1:0] <= `MB_addrA_addrB_P_skip;1:MBTypeGen_mbAddrB_reg[3:2] <= `MB_addrA_addrB_P_skip; + 2:MBTypeGen_mbAddrB_reg[5:4] <= `MB_addrA_addrB_P_skip;3:MBTypeGen_mbAddrB_reg[7:6] <= `MB_addrA_addrB_P_skip; + 4:MBTypeGen_mbAddrB_reg[9:8] <= `MB_addrA_addrB_P_skip;5:MBTypeGen_mbAddrB_reg[11:10] <= `MB_addrA_addrB_P_skip; + 6:MBTypeGen_mbAddrB_reg[13:12] <= `MB_addrA_addrB_P_skip;7:MBTypeGen_mbAddrB_reg[15:14] <= `MB_addrA_addrB_P_skip; + 8:MBTypeGen_mbAddrB_reg[17:16] <= `MB_addrA_addrB_P_skip;9:MBTypeGen_mbAddrB_reg[19:18] <= `MB_addrA_addrB_P_skip; + 10:MBTypeGen_mbAddrB_reg[21:20] <= `MB_addrA_addrB_P_skip; + endcase + end + else if (slice_data_state == `mb_num_update) + begin + if (mb_num_h != 10) + begin + if (mb_type_general[3] == 1'b0) + MBTypeGen_mbAddrA <= `MB_addrA_addrB_Inter; + else if (mb_type_general[3:2] == 2'b10) + MBTypeGen_mbAddrA <= `MB_addrA_addrB_Intra16x16; + else if (mb_type_general == `MB_Intra4x4) + MBTypeGen_mbAddrA <= `MB_addrA_addrB_Intra4x4; + end + if (mb_num_h == 9) + MBTypeGen_mbAddrD_tmp <= mb_type_general[3]; + if (mb_num_v != 8) + begin + if (mb_type_general[3] == 1'b0) + case (mb_num_h) + 0:MBTypeGen_mbAddrB_reg[1:0] <= `MB_addrA_addrB_Inter; 1:MBTypeGen_mbAddrB_reg[3:2] <= `MB_addrA_addrB_Inter; + 2:MBTypeGen_mbAddrB_reg[5:4] <= `MB_addrA_addrB_Inter; 3:MBTypeGen_mbAddrB_reg[7:6] <= `MB_addrA_addrB_Inter; + 4:MBTypeGen_mbAddrB_reg[9:8] <= `MB_addrA_addrB_Inter; 5:MBTypeGen_mbAddrB_reg[11:10] <= `MB_addrA_addrB_Inter; + 6:MBTypeGen_mbAddrB_reg[13:12] <= `MB_addrA_addrB_Inter; 7:MBTypeGen_mbAddrB_reg[15:14] <= `MB_addrA_addrB_Inter; + 8:MBTypeGen_mbAddrB_reg[17:16] <= `MB_addrA_addrB_Inter; 9:MBTypeGen_mbAddrB_reg[19:18] <= `MB_addrA_addrB_Inter; + 10:MBTypeGen_mbAddrB_reg[21:20]<= `MB_addrA_addrB_Inter; + endcase + else if (mb_type_general[3:2] == 2'b10) + case (mb_num_h) + 0:MBTypeGen_mbAddrB_reg[1:0] <= `MB_addrA_addrB_Intra16x16; 1:MBTypeGen_mbAddrB_reg[3:2] <= `MB_addrA_addrB_Intra16x16; + 2:MBTypeGen_mbAddrB_reg[5:4] <= `MB_addrA_addrB_Intra16x16; 3:MBTypeGen_mbAddrB_reg[7:6] <= `MB_addrA_addrB_Intra16x16; + 4:MBTypeGen_mbAddrB_reg[9:8] <= `MB_addrA_addrB_Intra16x16; 5:MBTypeGen_mbAddrB_reg[11:10] <= `MB_addrA_addrB_Intra16x16; + 6:MBTypeGen_mbAddrB_reg[13:12] <= `MB_addrA_addrB_Intra16x16; 7:MBTypeGen_mbAddrB_reg[15:14] <= `MB_addrA_addrB_Intra16x16; + 8:MBTypeGen_mbAddrB_reg[17:16] <= `MB_addrA_addrB_Intra16x16; 9:MBTypeGen_mbAddrB_reg[19:18] <= `MB_addrA_addrB_Intra16x16; + 10:MBTypeGen_mbAddrB_reg[21:20]<= `MB_addrA_addrB_Intra16x16; + endcase + else if (mb_type_general == `MB_Intra4x4) + case (mb_num_h) + 0:MBTypeGen_mbAddrB_reg[1:0] <= `MB_addrA_addrB_Intra4x4; 1:MBTypeGen_mbAddrB_reg[3:2] <= `MB_addrA_addrB_Intra4x4; + 2:MBTypeGen_mbAddrB_reg[5:4] <= `MB_addrA_addrB_Intra4x4; 3:MBTypeGen_mbAddrB_reg[7:6] <= `MB_addrA_addrB_Intra4x4; + 4:MBTypeGen_mbAddrB_reg[9:8] <= `MB_addrA_addrB_Intra4x4; 5:MBTypeGen_mbAddrB_reg[11:10] <= `MB_addrA_addrB_Intra4x4; + 6:MBTypeGen_mbAddrB_reg[13:12] <= `MB_addrA_addrB_Intra4x4; 7:MBTypeGen_mbAddrB_reg[15:14] <= `MB_addrA_addrB_Intra4x4; + 8:MBTypeGen_mbAddrB_reg[17:16] <= `MB_addrA_addrB_Intra4x4; 9:MBTypeGen_mbAddrB_reg[19:18] <= `MB_addrA_addrB_Intra4x4; + 10:MBTypeGen_mbAddrB_reg[21:20]<= `MB_addrA_addrB_Intra4x4; + endcase + end + end + + always @ (posedge clk) + if (reset_n == 1'b0) + MBTypeGen_mbAddrD <= 0; + else if (mb_num_h == 0) + MBTypeGen_mbAddrD <= MBTypeGen_mbAddrD_tmp; + + //---------------------------------------------------------------------- + //mb_pred & sub_mb_pred + // --> Also refer to Intra4x4_PredMode_decoding.v & Inter_mv_decoding.v + //---------------------------------------------------------------------- + wire prev_intra4x4_pred_mode_flag; + reg prev_intra4x4_pred_mode_flag_reg; + wire [2:0] rem_intra4x4_pred_mode; + reg [2:0] rem_intra4x4_pred_mode_reg; + reg [1:0] intra_chroma_pred_mode; + wire [7:0] mvd; + reg [7:0] mvd_reg; + reg [7:0] sub_mb_type_reg; + assign prev_intra4x4_pred_mode_flag = (mb_pred_state == `prev_intra4x4_pred_mode_flag_s)? BitStream_buffer_output[15]:prev_intra4x4_pred_mode_flag_reg; + assign rem_intra4x4_pred_mode = (mb_pred_state == `rem_intra4x4_pred_mode_s)? BitStream_buffer_output[15:13]:rem_intra4x4_pred_mode_reg; + assign mvd = ((mb_pred_state == `mvd_l0_s) || (sub_mb_pred_state == `sub_mvd_l0_s))? exp_golomb_decoding_output[7:0]:mvd_reg; + always @ (posedge clk) + if (reset_n == 0) + begin + prev_intra4x4_pred_mode_flag_reg <= 0; + rem_intra4x4_pred_mode_reg <= 0; + intra_chroma_pred_mode <= 0; + mvd_reg <= 0; + sub_mb_type_reg <= 0; + end + else + begin + case (mb_pred_state) + `prev_intra4x4_pred_mode_flag_s:prev_intra4x4_pred_mode_flag_reg <= prev_intra4x4_pred_mode_flag; + `rem_intra4x4_pred_mode_s :rem_intra4x4_pred_mode_reg <= rem_intra4x4_pred_mode; + `intra_chroma_pred_mode_s :intra_chroma_pred_mode <= exp_golomb_decoding_output[1:0]; + //ref_idx_l0_s: --> only 1 reference frame,so never jump into this state + `mvd_l0_s: mvd_reg <= mvd; + endcase + case (sub_mb_pred_state) + `sub_mb_type_s: + case (mbPartIdx) + 0:sub_mb_type_reg[1:0] <= exp_golomb_decoding_output[1:0]; + 1:sub_mb_type_reg[3:2] <= exp_golomb_decoding_output[1:0]; + 2:sub_mb_type_reg[5:4] <= exp_golomb_decoding_output[1:0]; + 3:sub_mb_type_reg[7:6] <= exp_golomb_decoding_output[1:0]; + endcase + //sub_ref_idx_l0_s: --> only 1 reference frame,so never jump into this state + `sub_mvd_l0_s: mvd_reg <= mvd; + endcase + end + reg [2:0] NumMbPart; + reg [2:0] NumSubMbPart; + reg [1:0] sub_mb_type; + always @ (sub_mb_pred_state or sub_mb_type_reg or mbPartIdx) + if (sub_mb_pred_state == `sub_mvd_l0_s) + case (mbPartIdx) + 0:sub_mb_type <= sub_mb_type_reg[1:0]; + 1:sub_mb_type <= sub_mb_type_reg[3:2]; + 2:sub_mb_type <= sub_mb_type_reg[5:4]; + 3:sub_mb_type <= sub_mb_type_reg[7:6]; + endcase + else + sub_mb_type <= 0; + always @ (mb_pred_state or mb_type_general or sub_mb_pred_state) + if (mb_pred_state == `mvd_l0_s) + case (mb_type_general) + 0:NumMbPart <= 3'd1; + default:NumMbPart <= 3'd2; + endcase + else if (sub_mb_pred_state == `sub_mvd_l0_s) + NumMbPart <= 3'd4; + else + NumMbPart <= 3'd0; + always @ (sub_mb_pred_state or mbPartIdx or sub_mb_type_reg) + if (sub_mb_pred_state == `sub_mvd_l0_s) + case (mbPartIdx) + 0: + case (sub_mb_type_reg[1:0]) + 2'b00 :NumSubMbPart <= 3'd1; + 2'b01,2'b10:NumSubMbPart <= 3'd2; + 2'b11 :NumSubMbPart <= 3'd4; + endcase + 1: + case (sub_mb_type_reg[3:2]) + 2'b00 :NumSubMbPart <= 3'd1; + 2'b01,2'b10:NumSubMbPart <= 3'd2; + 2'b11 :NumSubMbPart <= 3'd4; + endcase + 2: + case (sub_mb_type_reg[5:4]) + 2'b00 :NumSubMbPart <= 3'd1; + 2'b01,2'b10:NumSubMbPart <= 3'd2; + 2'b11 :NumSubMbPart <= 3'd4; + endcase + 3: + case (sub_mb_type_reg[7:6]) + 2'b00 :NumSubMbPart <= 3'd1; + 2'b01,2'b10:NumSubMbPart <= 3'd2; + 2'b11 :NumSubMbPart <= 3'd4; + endcase + endcase + else + NumSubMbPart <= 0; + + //mv_below8x8 + reg [3:0] mv_below8x8; + always @ (posedge clk) + if (reset_n == 1'b0) + mv_below8x8 <= 4'b0; + else if (sub_mb_pred_state == `sub_mb_type_s) + case (mbPartIdx) + 0:mv_below8x8[0] <= (exp_golomb_decoding_output[1:0] == 2'b00)? 1'b0:1'b1; + 1:mv_below8x8[1] <= (exp_golomb_decoding_output[1:0] == 2'b00)? 1'b0:1'b1; + 2:mv_below8x8[2] <= (exp_golomb_decoding_output[1:0] == 2'b00)? 1'b0:1'b1; + 3:mv_below8x8[3] <= (exp_golomb_decoding_output[1:0] == 2'b00)? 1'b0:1'b1; + endcase + else if (slice_data_state == `mb_pred || slice_data_state == `skip_run_duration) + mv_below8x8 <= 4'b0; + +endmodule + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/timescale.v b/demo_chip_rtl/rtl/nova/tags/Start/src/timescale.v new file mode 100644 index 0000000..b0f520d --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/timescale.v @@ -0,0 +1,13 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : timescale.v +// Generated : April 20, 2008 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Time scale for the entire design +//------------------------------------------------------------------------------------------------- + +`timescale 1ns/1ns diff --git a/demo_chip_rtl/rtl/nova/tags/Start/src/total_zeros_decoding.v b/demo_chip_rtl/rtl/nova/tags/Start/src/total_zeros_decoding.v new file mode 100644 index 0000000..13fccf9 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/src/total_zeros_decoding.v @@ -0,0 +1,400 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : total_zeros_decoding.v +// Generated : June 9, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Decoding total_zeros from Table9-7,Table9-8,Table9-9 of H.264/AVC standard 2003 +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module total_zeros_decoding (clk,reset_n,residual_state,cavlc_decoder_state,TotalCoeff_3to0,heading_one_pos, + BitStream_buffer_output,maxNumCoeff,total_zeros,total_zeros_len); + input clk,reset_n; + input [3:0] residual_state; + input [3:0] cavlc_decoder_state; + input [3:0] TotalCoeff_3to0; + input [3:0] heading_one_pos; + input [15:0] BitStream_buffer_output; + output [4:0] maxNumCoeff; + output [3:0] total_zeros; + output [3:0] total_zeros_len; + reg [4:0] maxNumCoeff; + reg [3:0] total_zeros; + reg [3:0] total_zeros_len; + + reg [3:0] total_zeros_reg; + always @ (posedge clk) + if (reset_n == 0) + maxNumCoeff <= 0; + else + case (residual_state) + `Intra16x16DCLevel_s:maxNumCoeff <= 5'd16; + `Intra16x16ACLevel_s:maxNumCoeff <= 15; + `LumaLevel_s :maxNumCoeff <= 5'd16; + `ChromaDCLevel_Cb_s :maxNumCoeff <= 4; + `ChromaDCLevel_Cr_s :maxNumCoeff <= 4; + `ChromaACLevel_Cb_s :maxNumCoeff <= 15; + `ChromaACLevel_Cr_s :maxNumCoeff <= 15; + endcase + + //total_zeros_len + always @ (cavlc_decoder_state or maxNumCoeff or TotalCoeff_3to0 or heading_one_pos or BitStream_buffer_output) + if (cavlc_decoder_state == `total_zeros_LUT) + begin + if (maxNumCoeff == 4) + case (TotalCoeff_3to0) + 1:if (heading_one_pos == 0) total_zeros_len <= 1; + else if (heading_one_pos == 1) total_zeros_len <= 2; + else total_zeros_len <= 3; + 2:if (heading_one_pos == 0) total_zeros_len <= 1; + else total_zeros_len <= 2; + 3: total_zeros_len <= 1; + default: total_zeros_len <= 0; + endcase + else + case (TotalCoeff_3to0) + 1:if (heading_one_pos == 0) total_zeros_len <= 1; + else if (heading_one_pos == 8) total_zeros_len <= 4'd9; + else total_zeros_len <= heading_one_pos + 2; + 2:if (heading_one_pos == 0) total_zeros_len <= 4'd3; + else if (heading_one_pos == 1) + total_zeros_len <= (BitStream_buffer_output[13] == 1'b1)? 4'd3:4'd4; + else if (heading_one_pos == 2) total_zeros_len <= 4; + else if (heading_one_pos == 3) total_zeros_len <= 5; + else if (heading_one_pos == 4) total_zeros_len <= 6; + else total_zeros_len <= 6; + 3:if (heading_one_pos == 0) total_zeros_len <= 4'd3; + else if (heading_one_pos == 1) + total_zeros_len <= (BitStream_buffer_output[13] == 1'b1)? 4'd3:4'd4; + else if (heading_one_pos == 2) total_zeros_len <= 4; + else if (heading_one_pos == 3) total_zeros_len <= 5; + else if (heading_one_pos == 4) total_zeros_len <= 5; + else total_zeros_len <= 4'd6; + 4:if (heading_one_pos == 0) total_zeros_len <= 3; + else if (heading_one_pos == 1) + total_zeros_len <= (BitStream_buffer_output[13] == 1'b1)? 4'd3:4'd4; + else if (heading_one_pos == 2) total_zeros_len <= 4; + else if (heading_one_pos == 3) total_zeros_len <= 5; + else total_zeros_len <= 5; + 5:if (heading_one_pos == 0) total_zeros_len <= 4'd3; + else if (heading_one_pos == 1) + total_zeros_len <= (BitStream_buffer_output[13] == 1'b1)? 4'd3:4'd4; + else if (heading_one_pos == 2) total_zeros_len <= 4; + else if (heading_one_pos == 3) total_zeros_len <= 4; + else total_zeros_len <= 5; + 6:if (heading_one_pos == 0 || heading_one_pos == 1 || heading_one_pos ==2) + total_zeros_len <= 3; + else if (heading_one_pos == 3) total_zeros_len <= 4; + else if (heading_one_pos == 4) total_zeros_len <= 5; + else total_zeros_len <= 6; + 7:if (heading_one_pos == 0 && BitStream_buffer_output[14] == 1) + total_zeros_len <= 2; + else if (heading_one_pos == 0 || heading_one_pos == 1 || heading_one_pos == 2) + total_zeros_len <= 3; + else if (heading_one_pos == 3) total_zeros_len <= 4; + else if (heading_one_pos == 4) total_zeros_len <= 5; + else total_zeros_len <= 6; + 8:if (heading_one_pos == 0) total_zeros_len <= 2; + else if (heading_one_pos == 1 || heading_one_pos == 2) + total_zeros_len <= 3; + else if (heading_one_pos == 3) total_zeros_len <= 4; + else if (heading_one_pos == 4) total_zeros_len <= 5; + else total_zeros_len <= 6; + 9:if (heading_one_pos == 0 || heading_one_pos == 1) + total_zeros_len <= 2; + else if (heading_one_pos == 2) total_zeros_len <= 3; + else if (heading_one_pos == 3) total_zeros_len <= 4; + else if (heading_one_pos == 4) total_zeros_len <= 5; + else total_zeros_len <= 6; + 10:if (heading_one_pos == 0 || heading_one_pos == 1) + total_zeros_len <= 2; + else if (heading_one_pos == 2) total_zeros_len <= 3; + else if (heading_one_pos == 3) total_zeros_len <= 4; + else total_zeros_len <= 5; + 11:if (heading_one_pos == 0) total_zeros_len <= 1; + else if (heading_one_pos == 1 || heading_one_pos == 2) + total_zeros_len <= 3; + else total_zeros_len <= 4; + 12:if (heading_one_pos == 0 || heading_one_pos == 1 || heading_one_pos == 2 || heading_one_pos == 3) + total_zeros_len <= heading_one_pos + 1; + else total_zeros_len <= 4; + 13:if (heading_one_pos == 0 || heading_one_pos == 1 || heading_one_pos == 2) + total_zeros_len <= heading_one_pos + 1; + else total_zeros_len <= 3; + 14:if (heading_one_pos == 0) total_zeros_len <= 1; + else total_zeros_len <= 2; + 15:total_zeros_len <= 1; + default:total_zeros_len <= 0; + endcase + end + else + total_zeros_len <= 0; + + //total_zeros + wire total_zeros_t0,total_zeros_t1; + assign total_zeros_t0 = (cavlc_decoder_state == `total_zeros_LUT && maxNumCoeff != 4); //Table 9-7,9-8 + assign total_zeros_t1 = (cavlc_decoder_state == `total_zeros_LUT && maxNumCoeff == 4); //Table 9-9 + always @ (total_zeros_t0 or total_zeros_t1 or TotalCoeff_3to0 or heading_one_pos + or BitStream_buffer_output or total_zeros_reg) + if (total_zeros_t0) + case (TotalCoeff_3to0) + 1: + if (heading_one_pos == 4'd0) + total_zeros <= 4'd0; + else if (heading_one_pos == 4'd1) + total_zeros <= (BitStream_buffer_output[13])? 4'd1:4'd2; + else if (heading_one_pos == 4'd2) + total_zeros <= (BitStream_buffer_output[12])? 4'd3:4'd4; + else if (heading_one_pos == 4'd3) + total_zeros <= (BitStream_buffer_output[11])? 4'd5:4'd6; + else if (heading_one_pos == 4'd4) + total_zeros <= (BitStream_buffer_output[10])? 4'd7:4'd8; + else if (heading_one_pos == 4'd5) + total_zeros <= (BitStream_buffer_output[9])? 4'd9:4'd10; + else if (heading_one_pos == 4'd6) + total_zeros <= (BitStream_buffer_output[8])? 4'd11:4'd12; + else if (heading_one_pos == 4'd7) + total_zeros <= (BitStream_buffer_output[7])? 4'd13:4'd14; + else + total_zeros <= 4'd15; + 2: + if (heading_one_pos == 4'd0) + total_zeros <= {2'b0,~BitStream_buffer_output[14:13]}; + else if (heading_one_pos == 4'd1) + case (BitStream_buffer_output[13:12]) + 2'b01:total_zeros <= 4'd5; + 2'b00:total_zeros <= 4'd6; + default:total_zeros <= 4'd4; + endcase + else if (heading_one_pos == 4'd2) + total_zeros <= (BitStream_buffer_output[12])? 4'd7:4'd8; + else if (heading_one_pos == 4'd3) + total_zeros <= (BitStream_buffer_output[11])? 4'd9:4'd10; + else if (heading_one_pos == 4'd4) + total_zeros <= (BitStream_buffer_output[10])? 4'd11:4'd12; + else if (heading_one_pos == 4'd5) + total_zeros <= 4'd13; + else + total_zeros <= 4'd14; + 3: + if (heading_one_pos == 4'd0) + case (BitStream_buffer_output[14:13]) + 2'b00:total_zeros <= 4'd6; + 2'b01:total_zeros <= 4'd3; + 2'b10:total_zeros <= 4'd2; + 2'b11:total_zeros <= 4'd1; + endcase + else if (heading_one_pos == 4'd1) + case (BitStream_buffer_output[13:12]) + 2'b00:total_zeros <= 4'd4; + 2'b01:total_zeros <= 4'd0; + default:total_zeros <= 4'd7; + endcase + else if (heading_one_pos == 4'd2) + total_zeros <= (BitStream_buffer_output[12])? 4'd5:4'd8; + else if (heading_one_pos == 4'd3) + total_zeros <= (BitStream_buffer_output[11])? 4'd9:4'd10; + else if (heading_one_pos == 4'd4) + total_zeros <= 4'd12; + else if (heading_one_pos == 4'd5) + total_zeros <= 4'd11; + else + total_zeros <= 4'd13; + 4: + if (heading_one_pos == 4'd0) + case (BitStream_buffer_output[14:13]) + 2'b00:total_zeros <= 4'd6; + 2'b01:total_zeros <= 4'd5; + 2'b10:total_zeros <= 4'd4; + 2'b11:total_zeros <= 4'd1; + endcase + else if (heading_one_pos == 4'd1) + case (BitStream_buffer_output[13:12]) + 2'b00:total_zeros <= 4'd3; + 2'b01:total_zeros <= 4'd2; + default:total_zeros <= 4'd8; + endcase + else if (heading_one_pos == 4'd2) + total_zeros <= (BitStream_buffer_output[12])? 4'd7:4'd9; + else if (heading_one_pos == 4'd3) + total_zeros <= (BitStream_buffer_output[11])? 4'd0:4'd10; + else if (heading_one_pos == 4'd4) + total_zeros <= 4'd11; + else + total_zeros <= 4'd12; + 5: + if (heading_one_pos == 4'd0) + case (BitStream_buffer_output[14:13]) + 2'b00:total_zeros <= 4'd6; + 2'b01:total_zeros <= 4'd5; + 2'b10:total_zeros <= 4'd4; + 2'b11:total_zeros <= 4'd3; + endcase + else if (heading_one_pos == 4'd1) + case (BitStream_buffer_output[13:12]) + 2'b00:total_zeros <= 4'd1; + 2'b01:total_zeros <= 4'd0; + default:total_zeros <= 4'd7; + endcase + else if (heading_one_pos == 4'd2) + total_zeros <= (BitStream_buffer_output[12])? 4'd2:4'd8; + else if (heading_one_pos == 4'd3) + total_zeros <= 4'd10; + else if (heading_one_pos == 4'd4) + total_zeros <= 4'd9; + else + total_zeros <= 4'd11; + 6: + if (heading_one_pos == 4'd0) + case (BitStream_buffer_output[14:13]) + 2'b00:total_zeros <= 4'd5; + 2'b01:total_zeros <= 4'd4; + 2'b10:total_zeros <= 4'd3; + 2'b11:total_zeros <= 4'd2; + endcase + else if (heading_one_pos == 4'd1) + total_zeros <= (BitStream_buffer_output[13])? 4'd6:4'd7; + else if (heading_one_pos == 4'd2) + total_zeros <= 4'd9; + else if (heading_one_pos == 4'd3) + total_zeros <= 4'd8; + else if (heading_one_pos == 4'd4) + total_zeros <= 4'd1; + else if (heading_one_pos == 4'd5) + total_zeros <= 4'd0; + else + total_zeros <= 4'd10; + 7: + if (heading_one_pos == 4'd0) + case (BitStream_buffer_output[14:13]) + 2'b00:total_zeros <= 4'd3; + 2'b01:total_zeros <= 4'd2; + default:total_zeros <= 4'd5; + endcase + else if (heading_one_pos == 4'd1) + total_zeros <= (BitStream_buffer_output[13])? 4'd4:4'd6; + else if (heading_one_pos == 4'd2) + total_zeros <= 4'd8; + else if (heading_one_pos == 4'd3) + total_zeros <= 4'd7; + else if (heading_one_pos == 4'd4) + total_zeros <= 4'd1; + else if (heading_one_pos == 4'd5) + total_zeros <= 4'd0; + else + total_zeros <= 4'd9; + 8: + if (heading_one_pos == 4'd0) + total_zeros <= (BitStream_buffer_output[14])? 4'd4:4'd5; + else if (heading_one_pos == 4'd1) + total_zeros <= (BitStream_buffer_output[13])? 4'd3:4'd6; + else if (heading_one_pos == 4'd2) + total_zeros <= 4'd7; + else if (heading_one_pos == 4'd3) + total_zeros <= 4'd1; + else if (heading_one_pos == 4'd4) + total_zeros <= 4'd2; + else if (heading_one_pos == 4'd5) + total_zeros <= 4'd0; + else + total_zeros <= 4'd8; + 9: + if (heading_one_pos == 4'd0) + total_zeros <= (BitStream_buffer_output[14])? 4'd3:4'd4; + else if (heading_one_pos == 4'd1) + total_zeros <= 4'd6; + else if (heading_one_pos == 4'd2) + total_zeros <= 4'd5; + else if (heading_one_pos == 4'd3) + total_zeros <= 4'd2; + else if (heading_one_pos == 4'd4) + total_zeros <= 4'd7; + else if (heading_one_pos == 4'd5) + total_zeros <= 4'd0; + else + total_zeros <= 4'd1; + 10: + if (heading_one_pos == 4'd0) + total_zeros <= (BitStream_buffer_output[14])? 4'd3:4'd4; + else if (heading_one_pos == 4'd1) + total_zeros <= 4'd5; + else if (heading_one_pos == 4'd2) + total_zeros <= 4'd2; + else if (heading_one_pos == 4'd3) + total_zeros <= 4'd6; + else if (heading_one_pos == 4'd4) + total_zeros <= 4'd0; + else + total_zeros <= 4'd1; + 11: + if (heading_one_pos == 4'd0) + total_zeros <= 4'd4; + else if (heading_one_pos == 4'd1) + total_zeros <= (BitStream_buffer_output[13])? 4'd5:4'd3; + else if (heading_one_pos == 4'd2) + total_zeros <= 4'd2; + else if (heading_one_pos == 4'd3) + total_zeros <= 4'd1; + else + total_zeros <= 4'd0; + 12: + if (heading_one_pos == 4'd0) + total_zeros <= 4'd3; + else if (heading_one_pos == 4'd1) + total_zeros <= 4'd2; + else if (heading_one_pos == 4'd2) + total_zeros <= 4'd4; + else if (heading_one_pos == 4'd3) + total_zeros <= 4'd1; + else + total_zeros <= 4'd0; + 13: + if (heading_one_pos == 4'd0) + total_zeros <= 4'd2; + else if (heading_one_pos == 4'd1) + total_zeros <= 4'd3; + else if (heading_one_pos == 4'd2) + total_zeros <= 4'd1; + else + total_zeros <= 4'd0; + 14: + if (heading_one_pos == 4'd0) + total_zeros <= 4'd2; + else if (heading_one_pos == 4'd1) + total_zeros <= 4'd1; + else + total_zeros <= 4'd0; + default:total_zeros <= (heading_one_pos == 4'd0)? 4'd1:4'd0; + endcase + else if (total_zeros_t1) + case (TotalCoeff_3to0) + 1:if (heading_one_pos == 4'd0) total_zeros <= 4'd0; + else if (heading_one_pos == 4'd1) total_zeros <= 4'd1; + else if (heading_one_pos == 4'd2) total_zeros <= 4'd2; + else total_zeros <= 4'd3; + 2:if (heading_one_pos == 4'd0) total_zeros <= 4'd0; + else if (heading_one_pos == 4'd1) total_zeros <= 4'd1; + else total_zeros <= 4'd2; + 3:total_zeros <= {3'b0,~BitStream_buffer_output[15]}; + default:total_zeros <= 0; + endcase + else + total_zeros <= total_zeros_reg; + + always @ (posedge clk) + if (reset_n == 0) + total_zeros_reg <= 0; + else if (cavlc_decoder_state == `total_zeros_LUT) + total_zeros_reg <= total_zeros; + +endmodule + + diff --git a/demo_chip_rtl/rtl/nova/tags/Start/test/readme.txt b/demo_chip_rtl/rtl/nova/tags/Start/test/readme.txt new file mode 100644 index 0000000..f331dbf --- /dev/null +++ b/demo_chip_rtl/rtl/nova/tags/Start/test/readme.txt @@ -0,0 +1 @@ +To be added soon \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/MISC/readme.txt b/demo_chip_rtl/rtl/nova/trunk/MISC/readme.txt new file mode 100644 index 0000000..f331dbf --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/MISC/readme.txt @@ -0,0 +1 @@ +To be added soon \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/doc/nova_spec.doc b/demo_chip_rtl/rtl/nova/trunk/doc/nova_spec.doc new file mode 100644 index 0000000..833d84f Binary files /dev/null and b/demo_chip_rtl/rtl/nova/trunk/doc/nova_spec.doc differ diff --git a/demo_chip_rtl/rtl/nova/trunk/doc/readme.txt b/demo_chip_rtl/rtl/nova/trunk/doc/readme.txt new file mode 100644 index 0000000..6682a6b --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/doc/readme.txt @@ -0,0 +1 @@ +nova_spec.doc:specifications of nova design \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/Beha_BitStream_ram.v b/demo_chip_rtl/rtl/nova/trunk/src/Beha_BitStream_ram.v new file mode 100644 index 0000000..02f3816 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/Beha_BitStream_ram.v @@ -0,0 +1,37 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : Beha_BitStream_ram.v +// Generated : May 16,2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Behavior RAM for encoded bitstream storing, NOT synthesizable +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module Beha_BitStream_ram(clk,BitStream_ram_ren,BitStream_ram_addr,BitStream_ram_data); + input clk; + input BitStream_ram_ren; + input [16:0] BitStream_ram_addr; + + output [15:0] BitStream_ram_data; + + reg [15:0] BitStream_ram_data; + reg [15:0] BitStream_ram[0:`Beha_Bitstream_ram_size]; + + initial + begin + $readmemh("D:/nova_opencores/bin2hex/akiyo300_1ref.txt",BitStream_ram); + end + + always @ (posedge clk) + if (BitStream_ram_ren == 0) + BitStream_ram_data <= #2 BitStream_ram[BitStream_ram_addr]; + +endmodule diff --git a/demo_chip_rtl/rtl/nova/trunk/src/BitStream_buffer.v b/demo_chip_rtl/rtl/nova/trunk/src/BitStream_buffer.v new file mode 100644 index 0000000..47c539a --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/BitStream_buffer.v @@ -0,0 +1,288 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : BitStream_buffer.v +// Generated : May 16,2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Circular buffer,interfacing between Beha_Bitstream_ram and the decoder +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module BitStream_buffer (clk,reset_n,BitStream_buffer_input,pc, + BitStream_ram_ren,BitStream_buffer_valid_n,BitStream_buffer_output,BitStream_ram_addr); + input clk,reset_n; + input [15:0] BitStream_buffer_input; + input [6:0] pc; + + output BitStream_ram_ren; + output BitStream_buffer_valid_n; + output [15:0] BitStream_buffer_output; + output [16:0]BitStream_ram_addr; + + reg BitStream_ram_ren; + reg BitStream_buffer_valid_n; + reg [15:0] BitStream_buffer_output; + reg [16:0]BitStream_ram_addr; + + reg [0:127]BS_buffer; + reg [6:0] pc_previous; + reg [3:0] reset_counter; + reg [2:0] half_fill_counter; + reg [6:0] buffer_index; //for buffer write + + /* + // synopsys translate_off + integer pc_statistical; + initial + begin + pc_statistical = $fopen("pc_statistical.txt"); + end + always @ (posedge clk) + $fdisplay (pc_statistical,"%d",pc); + // synopsys translate_on + */ + always @ (posedge clk) + if (reset_n == 1'b0) + pc_previous <= 0; + else + pc_previous <= pc; + + always @ (posedge clk) + if (reset_n == 1'b0) + reset_counter <= 0; + else if (reset_counter < 10) + reset_counter <= reset_counter + 1; + + always @ (posedge clk) + if (reset_n == 1'b0) + half_fill_counter <= 0; + else if (reset_counter == 10) + begin + if (((pc > 63 && pc_previous <= 63) || (pc <63 && pc_previous >=63)) && half_fill_counter == 0) + half_fill_counter <= 1; + else if (pc > 63 && half_fill_counter == 0 && buffer_index == 0) + half_fill_counter <= 1; + else if (pc < 63 && half_fill_counter == 0 && buffer_index == 64) + half_fill_counter <= 1; + else if (half_fill_counter > 0 && half_fill_counter < 5) + half_fill_counter <= half_fill_counter + 1; + else if (half_fill_counter == 5) + half_fill_counter <= 0; + end + + always @ (posedge clk) + if (reset_n == 1'b0) + buffer_index <= 0; + else if (reset_counter > 1 && reset_counter < 10) + buffer_index <= buffer_index + 16; + else if (half_fill_counter > 1 && half_fill_counter <= 5) + buffer_index <= buffer_index + 16; + + always @ (posedge clk) + if (reset_n == 1'b0) + BitStream_buffer_valid_n <= 1'b1; + else if (reset_counter == 10) + BitStream_buffer_valid_n <= 1'b0; + + always @ (posedge clk) + if (reset_n == 1'b0) + BitStream_ram_ren <= 1'b0; + else if (reset_counter < 9) + BitStream_ram_ren <= 1'b0; + else if (reset_counter == 9) + BitStream_ram_ren <= 1'b1; + else + begin + if (((pc > 63 && pc_previous <= 63) || (pc <63 && pc_previous >=63)) && half_fill_counter == 0) + BitStream_ram_ren <= 0; + else if (half_fill_counter > 0 && half_fill_counter < 5) + BitStream_ram_ren <= 0; + else + BitStream_ram_ren <= 1; + end + + always @ (posedge clk) + if (reset_n == 1'b0) + BitStream_ram_addr <= 0; + else if (reset_counter > 0 && reset_counter < 9) + BitStream_ram_addr <= BitStream_ram_addr + 1; + else if (half_fill_counter > 0 && half_fill_counter < 5 && BitStream_ram_addr != 17'd131071) //no wrap around + BitStream_ram_addr <= BitStream_ram_addr + 1; + + integer i; + always @ (posedge clk) + if (reset_n == 1'b0) + BS_buffer <= 0; + else if ((reset_counter > 1 && reset_counter < 10) || (half_fill_counter > 1 && half_fill_counter <= 5)) + case (buffer_index[6:4]) + 3'b000: + for (i=0;i<16;i=i+1) + BS_buffer[i] <= BitStream_buffer_input[15-i]; + 3'b001: + for (i=0;i<16;i=i+1) + BS_buffer[16+i] <= BitStream_buffer_input[15-i]; + 3'b010: + for (i=0;i<16;i=i+1) + BS_buffer[32+i] <= BitStream_buffer_input[15-i]; + 3'b011: + for (i=0;i<16;i=i+1) + BS_buffer[48+i] <= BitStream_buffer_input[15-i]; + 3'b100: + for (i=0;i<16;i=i+1) + BS_buffer[64+i] <= BitStream_buffer_input[15-i]; + 3'b101: + for (i=0;i<16;i=i+1) + BS_buffer[80+i] <= BitStream_buffer_input[15-i]; + 3'b110: + for (i=0;i<16;i=i+1) + BS_buffer[96+i] <= BitStream_buffer_input[15-i]; + 3'b111: + for (i=0;i<16;i=i+1) + BS_buffer[112+i] <= BitStream_buffer_input[15-i]; + endcase + + always @ (posedge clk) + //always @ (reset_n or BitStream_buffer_valid_n or pc) + if (reset_n == 1'b0) + BitStream_buffer_output <= 0; + else if (BitStream_buffer_valid_n == 0) + case (pc) + 0 :BitStream_buffer_output <= BS_buffer[0:15]; + 1 :BitStream_buffer_output <= BS_buffer[1:16]; + 2 :BitStream_buffer_output <= BS_buffer[2:17]; + 3 :BitStream_buffer_output <= BS_buffer[3:18]; + 4 :BitStream_buffer_output <= BS_buffer[4:19]; + 5 :BitStream_buffer_output <= BS_buffer[5:20]; + 6 :BitStream_buffer_output <= BS_buffer[6:21]; + 7 :BitStream_buffer_output <= BS_buffer[7:22]; + 8 :BitStream_buffer_output <= BS_buffer[8:23]; + 9 :BitStream_buffer_output <= BS_buffer[9:24]; + 10 :BitStream_buffer_output <= BS_buffer[10:25]; + 11 :BitStream_buffer_output <= BS_buffer[11:26]; + 12 :BitStream_buffer_output <= BS_buffer[12:27]; + 13 :BitStream_buffer_output <= BS_buffer[13:28]; + 14 :BitStream_buffer_output <= BS_buffer[14:29]; + 15 :BitStream_buffer_output <= BS_buffer[15:30]; + 16 :BitStream_buffer_output <= BS_buffer[16:31]; + 17 :BitStream_buffer_output <= BS_buffer[17:32]; + 18 :BitStream_buffer_output <= BS_buffer[18:33]; + 19 :BitStream_buffer_output <= BS_buffer[19:34]; + 20 :BitStream_buffer_output <= BS_buffer[20:35]; + 21 :BitStream_buffer_output <= BS_buffer[21:36]; + 22 :BitStream_buffer_output <= BS_buffer[22:37]; + 23 :BitStream_buffer_output <= BS_buffer[23:38]; + 24 :BitStream_buffer_output <= BS_buffer[24:39]; + 25 :BitStream_buffer_output <= BS_buffer[25:40]; + 26 :BitStream_buffer_output <= BS_buffer[26:41]; + 27 :BitStream_buffer_output <= BS_buffer[27:42]; + 28 :BitStream_buffer_output <= BS_buffer[28:43]; + 29 :BitStream_buffer_output <= BS_buffer[29:44]; + 30 :BitStream_buffer_output <= BS_buffer[30:45]; + 31 :BitStream_buffer_output <= BS_buffer[31:46]; + 32 :BitStream_buffer_output <= BS_buffer[32:47]; + 33 :BitStream_buffer_output <= BS_buffer[33:48]; + 34 :BitStream_buffer_output <= BS_buffer[34:49]; + 35 :BitStream_buffer_output <= BS_buffer[35:50]; + 36 :BitStream_buffer_output <= BS_buffer[36:51]; + 37 :BitStream_buffer_output <= BS_buffer[37:52]; + 38 :BitStream_buffer_output <= BS_buffer[38:53]; + 39 :BitStream_buffer_output <= BS_buffer[39:54]; + 40 :BitStream_buffer_output <= BS_buffer[40:55]; + 41 :BitStream_buffer_output <= BS_buffer[41:56]; + 42 :BitStream_buffer_output <= BS_buffer[42:57]; + 43 :BitStream_buffer_output <= BS_buffer[43:58]; + 44 :BitStream_buffer_output <= BS_buffer[44:59]; + 45 :BitStream_buffer_output <= BS_buffer[45:60]; + 46 :BitStream_buffer_output <= BS_buffer[46:61]; + 47 :BitStream_buffer_output <= BS_buffer[47:62]; + 48 :BitStream_buffer_output <= BS_buffer[48:63]; + 49 :BitStream_buffer_output <= BS_buffer[49:64]; + 50 :BitStream_buffer_output <= BS_buffer[50:65]; + 51 :BitStream_buffer_output <= BS_buffer[51:66]; + 52 :BitStream_buffer_output <= BS_buffer[52:67]; + 53 :BitStream_buffer_output <= BS_buffer[53:68]; + 54 :BitStream_buffer_output <= BS_buffer[54:69]; + 55 :BitStream_buffer_output <= BS_buffer[55:70]; + 56 :BitStream_buffer_output <= BS_buffer[56:71]; + 57 :BitStream_buffer_output <= BS_buffer[57:72]; + 58 :BitStream_buffer_output <= BS_buffer[58:73]; + 59 :BitStream_buffer_output <= BS_buffer[59:74]; + 60 :BitStream_buffer_output <= BS_buffer[60:75]; + 61 :BitStream_buffer_output <= BS_buffer[61:76]; + 62 :BitStream_buffer_output <= BS_buffer[62:77]; + 63 :BitStream_buffer_output <= BS_buffer[63:78]; + 64 :BitStream_buffer_output <= BS_buffer[64:79]; + 65 :BitStream_buffer_output <= BS_buffer[65:80]; + 66 :BitStream_buffer_output <= BS_buffer[66:81]; + 67 :BitStream_buffer_output <= BS_buffer[67:82]; + 68 :BitStream_buffer_output <= BS_buffer[68:83]; + 69 :BitStream_buffer_output <= BS_buffer[69:84]; + 70 :BitStream_buffer_output <= BS_buffer[70:85]; + 71 :BitStream_buffer_output <= BS_buffer[71:86]; + 72 :BitStream_buffer_output <= BS_buffer[72:87]; + 73 :BitStream_buffer_output <= BS_buffer[73:88]; + 74 :BitStream_buffer_output <= BS_buffer[74:89]; + 75 :BitStream_buffer_output <= BS_buffer[75:90]; + 76 :BitStream_buffer_output <= BS_buffer[76:91]; + 77 :BitStream_buffer_output <= BS_buffer[77:92]; + 78 :BitStream_buffer_output <= BS_buffer[78:93]; + 79 :BitStream_buffer_output <= BS_buffer[79:94]; + 80 :BitStream_buffer_output <= BS_buffer[80:95]; + 81 :BitStream_buffer_output <= BS_buffer[81:96]; + 82 :BitStream_buffer_output <= BS_buffer[82:97]; + 83 :BitStream_buffer_output <= BS_buffer[83:98]; + 84 :BitStream_buffer_output <= BS_buffer[84:99]; + 85 :BitStream_buffer_output <= BS_buffer[85:100]; + 86 :BitStream_buffer_output <= BS_buffer[86:101]; + 87 :BitStream_buffer_output <= BS_buffer[87:102]; + 88 :BitStream_buffer_output <= BS_buffer[88:103]; + 89 :BitStream_buffer_output <= BS_buffer[89:104]; + 90 :BitStream_buffer_output <= BS_buffer[90:105]; + 91 :BitStream_buffer_output <= BS_buffer[91:106]; + 92 :BitStream_buffer_output <= BS_buffer[92:107]; + 93 :BitStream_buffer_output <= BS_buffer[93:108]; + 94 :BitStream_buffer_output <= BS_buffer[94:109]; + 95 :BitStream_buffer_output <= BS_buffer[95:110]; + 96 :BitStream_buffer_output <= BS_buffer[96:111]; + 97 :BitStream_buffer_output <= BS_buffer[97:112]; + 98 :BitStream_buffer_output <= BS_buffer[98:113]; + 99 :BitStream_buffer_output <= BS_buffer[99:114]; + 100:BitStream_buffer_output <= BS_buffer[100:115]; + 101:BitStream_buffer_output <= BS_buffer[101:116]; + 102:BitStream_buffer_output <= BS_buffer[102:117]; + 103:BitStream_buffer_output <= BS_buffer[103:118]; + 104:BitStream_buffer_output <= BS_buffer[104:119]; + 105:BitStream_buffer_output <= BS_buffer[105:120]; + 106:BitStream_buffer_output <= BS_buffer[106:121]; + 107:BitStream_buffer_output <= BS_buffer[107:122]; + 108:BitStream_buffer_output <= BS_buffer[108:123]; + 109:BitStream_buffer_output <= BS_buffer[109:124]; + 110:BitStream_buffer_output <= BS_buffer[110:125]; + 111:BitStream_buffer_output <= BS_buffer[111:126]; + 112:BitStream_buffer_output <= BS_buffer[112:127]; + 113:BitStream_buffer_output <= {BS_buffer[113:127],BS_buffer[0]}; + 114:BitStream_buffer_output <= {BS_buffer[114:127],BS_buffer[0:1]}; + 115:BitStream_buffer_output <= {BS_buffer[115:127],BS_buffer[0:2]}; + 116:BitStream_buffer_output <= {BS_buffer[116:127],BS_buffer[0:3]}; + 117:BitStream_buffer_output <= {BS_buffer[117:127],BS_buffer[0:4]}; + 118:BitStream_buffer_output <= {BS_buffer[118:127],BS_buffer[0:5]}; + 119:BitStream_buffer_output <= {BS_buffer[119:127],BS_buffer[0:6]}; + 120:BitStream_buffer_output <= {BS_buffer[120:127],BS_buffer[0:7]}; + 121:BitStream_buffer_output <= {BS_buffer[121:127],BS_buffer[0:8]}; + 122:BitStream_buffer_output <= {BS_buffer[122:127],BS_buffer[0:9]}; + 123:BitStream_buffer_output <= {BS_buffer[123:127],BS_buffer[0:10]}; + 124:BitStream_buffer_output <= {BS_buffer[124:127],BS_buffer[0:11]}; + 125:BitStream_buffer_output <= {BS_buffer[125:127],BS_buffer[0:12]}; + 126:BitStream_buffer_output <= {BS_buffer[126:127],BS_buffer[0:13]}; + 127:BitStream_buffer_output <= {BS_buffer[127],BS_buffer[0:14]}; + endcase +endmodule + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/BitStream_controller.v b/demo_chip_rtl/rtl/nova/trunk/src/BitStream_controller.v new file mode 100644 index 0000000..cf81775 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/BitStream_controller.v @@ -0,0 +1,745 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : BitStream_controller.v +// Generated : June 12,2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// top module for bitstream controller +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module BitStream_controller (clk,reset_n,freq_ctrl0,freq_ctrl1,BitStream_buffer_input,pin_disable_DF, + trigger_CAVLC,blk4x4_rec_counter,end_of_DCBlk_IQIT,end_of_one_blk4x4_sum,end_of_MB_DEC,gclk_end_of_MB_DEC, + curr_DC_IsZero, + + BitStream_ram_ren,BitStream_ram_addr,pic_num, + mb_type_general,mb_num_h,mb_num_v,NextMB_IsSkip,LowerMB_IsSkip, + slice_data_state,residual_state,cavlc_decoder_state, + end_of_one_residual_block,end_of_NonZeroCoeff_CAVLC,end_of_one_frame, + Intra16x16_predmode,Intra4x4_predmode_CurrMb,Intra_chroma_predmode, + QPy,QPc,i4x4_CbCr,slice_alpha_c0_offset_div2,slice_beta_offset_div2, + CodedBlockPatternLuma,CodedBlockPatternChroma,TotalCoeff, + Is_skip_run_entry,skip_mv_calc,disable_DF, + coeffLevel_0,coeffLevel_1,coeffLevel_2, coeffLevel_3, coeffLevel_4, coeffLevel_5, coeffLevel_6, coeffLevel_7, + coeffLevel_8,coeffLevel_9,coeffLevel_10,coeffLevel_11,coeffLevel_12,coeffLevel_13,coeffLevel_14,coeffLevel_15, + mv_is16x16,mv_below8x8, + mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3,mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3, + end_of_BS_DEC,bs_V0,bs_V1,bs_V2,bs_V3,bs_H0,bs_H1,bs_H2,bs_H3, + + slice_header_s6 + ); + input clk,reset_n; + input freq_ctrl0; + input freq_ctrl1; + input [15:0] BitStream_buffer_input; + input pin_disable_DF; + input trigger_CAVLC; + input [4:0] blk4x4_rec_counter; + input end_of_DCBlk_IQIT; + input end_of_one_blk4x4_sum; + input end_of_MB_DEC; + input gclk_end_of_MB_DEC; + input curr_DC_IsZero; + + output BitStream_ram_ren; + output [16:0] BitStream_ram_addr; + output [5:0] pic_num; + + output [3:0] mb_type_general; + output [3:0] mb_num_h; + output [3:0] mb_num_v; + output NextMB_IsSkip; + output LowerMB_IsSkip; + output [3:0] slice_data_state; + output [3:0] residual_state; + output [3:0] cavlc_decoder_state; + output end_of_one_residual_block; + output end_of_NonZeroCoeff_CAVLC; + output end_of_one_frame; + output [1:0] Intra16x16_predmode; + output [63:0] Intra4x4_predmode_CurrMb; + output [1:0] Intra_chroma_predmode; + output [5:0] QPy; + output [5:0] QPc; + output [1:0] i4x4_CbCr; + output [3:0] slice_alpha_c0_offset_div2; + output [3:0] slice_beta_offset_div2; + output [3:0] CodedBlockPatternLuma; + output [1:0] CodedBlockPatternChroma; + output [4:0] TotalCoeff; + output Is_skip_run_entry; + output skip_mv_calc; + output disable_DF; + output [8:0] coeffLevel_0, coeffLevel_1, coeffLevel_2,coeffLevel_3, coeffLevel_4, coeffLevel_5; + output [8:0] coeffLevel_6, coeffLevel_7, coeffLevel_8, coeffLevel_9,coeffLevel_10,coeffLevel_11; + output [8:0] coeffLevel_12,coeffLevel_13,coeffLevel_14,coeffLevel_15; + output mv_is16x16; + output [3:0] mv_below8x8; + output [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3; + output [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3; + output end_of_BS_DEC; + output [11:0] bs_V0,bs_V1,bs_V2,bs_V3; + output [11:0] bs_H0,bs_H1,bs_H2,bs_H3; + + output slice_header_s6; + + wire gclk_parser; + wire gclk_nal; + wire gclk_slice; + wire gclk_sps; + wire gclk_pps; + wire gclk_slice_header; + wire gclk_slice_data; + wire gclk_residual; + wire gclk_cavlc; + wire gclk_bs_dec; + wire gclk_Intra4x4PredMode_mbAddrB_RF; + wire gclk_mvx_mbAddrB_RF; + wire gclk_mvy_mbAddrB_RF; + wire gclk_mvx_mbAddrC_RF; + wire gclk_mvy_mbAddrC_RF; + wire gclk_LumaLevel_mbAddrB_RF; + wire gclk_ChromaLevel_Cb_mbAddrB_RF; + wire gclk_ChromaLevel_Cr_mbAddrB_RF; + wire [6:0] pc; + wire [5:0] QPy,QPc; + wire [3:0] CodedBlockPatternLuma; + wire [1:0] CodedBlockPatternChroma; + wire [8:0] coeffLevel_0, coeffLevel_1, coeffLevel_2,coeffLevel_3, coeffLevel_4, coeffLevel_5; + wire [8:0] coeffLevel_6, coeffLevel_7, coeffLevel_8, coeffLevel_9,coeffLevel_10,coeffLevel_11; + wire [8:0] coeffLevel_12,coeffLevel_13,coeffLevel_14,coeffLevel_15; + wire [63:0] Intra4x4PredMode_CurrMb; + wire mv_is16x16; + wire Is_skip_run_end; + wire Is_skipMB_mv_calc; + wire [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3; + wire [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3; + + wire BitStream_buffer_valid_n; + wire [15:0] BitStream_buffer_output; + wire [1:0] parser_state; + wire [2:0] nal_unit_state; + wire [1:0] slice_layer_wo_partitioning_state; + wire [3:0] slice_header_state; + wire [2:0] ref_pic_list_reordering_state; + wire [1:0] dec_ref_pic_marking_state; + wire [3:0] slice_data_state; + wire [1:0] sub_mb_pred_state; + wire [2:0] mb_pred_state; + wire [3:0] seq_parameter_set_state; + wire [3:0] pic_parameter_set_state; + wire [3:0] residual_state; + wire [3:0] cavlc_decoder_state; + wire [3:0] exp_golomb_len; + wire [3:0] dependent_variable_len; + wire [4:0] cavlc_consumed_bits_len; + wire heading_one_en; + wire [3:0] heading_one_pos; + wire [7:0] exp_golomb_decoding_output; + wire [9:0] dependent_variable_decoding_output; + wire Intra4x4PredMode_mbAddrB_cs_n; + wire Intra4x4PredMode_mbAddrB_wr_n; + wire [3:0] Intra4x4PredMode_mbAddrB_rd_addr; + wire [3:0] Intra4x4PredMode_mbAddrB_wr_addr; + wire [15:0] Intra4x4PredMode_mbAddrB_din; + wire [15:0] Intra4x4PredMode_mbAddrB_dout; + wire mvx_mbAddrB_cs_n; + wire mvy_mbAddrB_cs_n; + wire mvx_mbAddrC_cs_n; + wire mvy_mbAddrC_cs_n; + wire mvx_mbAddrB_wr_n; + wire mvy_mbAddrB_wr_n; + wire mvx_mbAddrC_wr_n; + wire mvy_mbAddrC_wr_n; + wire [3:0] mvx_mbAddrB_rd_addr; + wire [3:0] mvy_mbAddrB_rd_addr; + wire [3:0] mvx_mbAddrC_rd_addr; + wire [3:0] mvy_mbAddrC_rd_addr; + wire [3:0] mvx_mbAddrB_wr_addr; + wire [3:0] mvy_mbAddrB_wr_addr; + wire [3:0] mvx_mbAddrC_wr_addr; + wire [3:0] mvy_mbAddrC_wr_addr; + wire [31:0] mvx_mbAddrA; + wire [31:0] mvy_mbAddrA; + wire [31:0] mvx_mbAddrB_din; + wire [31:0] mvx_mbAddrB_dout; + wire [31:0] mvy_mbAddrB_din; + wire [31:0] mvy_mbAddrB_dout; + wire [7:0] mvx_mbAddrC_din; + wire [7:0] mvx_mbAddrC_dout; + wire [7:0] mvy_mbAddrC_din; + wire [7:0] mvy_mbAddrC_dout; + wire end_of_NonZeroCoeff_CAVLC; + wire start_code_prefix_found; + wire [4:0] nal_unit_type; + wire deblocking_filter_control_present_flag; + wire [1:0] disable_deblocking_filter_idc; + wire disable_DF; + wire [6:0] mb_skip_run; + wire [2:0] NumMbPart; + wire [2:0] NumSubMbPart; + wire [1:0] MBTypeGen_mbAddrA; + wire MBTypeGen_mbAddrD; + wire [21:0]MBTypeGen_mbAddrB_reg; + wire [3:0] log2_max_frame_num_minus4; + wire [3:0] log2_max_pic_order_cnt_lsb_minus4; + wire constrained_intra_pred_flag; + wire num_ref_idx_active_override_flag; + wire [2:0] num_ref_idx_l0_active_minus1; + wire [2:0] slice_type; + wire [4:0] mb_type; + wire [3:0] mb_type_general; + wire [1:0] sub_mb_type; + wire [5:0] pic_init_qp_minus26; + wire [4:0] chroma_qp_index_offset; + wire [2:0] rem_intra4x4_pred_mode; + wire [7:0] mvd; + wire prev_intra4x4_pred_mode_flag; + wire cavlc_decoder_en; + wire [5:0] pic_num; + wire [6:0] mb_num; + wire [3:0] mb_num_h; + wire [3:0] mb_num_v; + wire [3:0] luma4x4BlkIdx; + wire [1:0] mbPartIdx; + wire [1:0] subMbPartIdx; + wire compIdx; + wire suffix_length_initialized; + wire IsRunLoop; + wire [1:0] i8x8,i4x4; + wire [1:0] i4x4_CbCr; + wire [3:0] coeffNum; + wire [3:0] i_level; + wire [3:0] i_run; + wire [3:0] i_TotalCoeff; + wire [4:0] TotalCoeff; + wire [1:0] TrailingOnes; + wire [4:0] maxNumCoeff; + wire [3:0] zerosLeft; + wire [3:0] run; + + wire [1:0] Luma_8x8_AllZeroCoeff_mbAddrA; + wire [19:0] LumaLevel_mbAddrA; + wire [19:0] LumaLevel_CurrMb0,LumaLevel_CurrMb1,LumaLevel_CurrMb2,LumaLevel_CurrMb3; + wire LumaLevel_mbAddrB_cs_n; + wire [19:0] LumaLevel_mbAddrB_dout; + wire ChromaLevel_Cb_mbAddrB_cs_n; + wire ChromaLevel_Cr_mbAddrB_cs_n; + wire [1:0] bs_dec_counter; + wire [11:0] bs_V0,bs_V1,bs_V2,bs_V3; + wire [11:0] bs_H0,bs_H1,bs_H2,bs_H3; + wire mv_mbAddrB_rd_for_DF; + + BitStream_buffer BitStream_buffer ( + .clk(clk), + .reset_n(reset_n), + .BitStream_buffer_input(BitStream_buffer_input), + .pc(pc), + .BitStream_ram_ren(BitStream_ram_ren), + .BitStream_buffer_valid_n(BitStream_buffer_valid_n), + .BitStream_buffer_output(BitStream_buffer_output), + .BitStream_ram_addr(BitStream_ram_addr) + ); + bitstream_gclk_gen bitstream_gclk_gen ( + .clk(clk), + .reset_n(reset_n), + .freq_ctrl0(freq_ctrl0), + .freq_ctrl1(freq_ctrl1), + .parser_state(parser_state), + .nal_unit_state(nal_unit_state), + .slice_layer_wo_partitioning_state(slice_layer_wo_partitioning_state), + .slice_header_state(slice_header_state), + .slice_data_state(slice_data_state), + .seq_parameter_set_state(seq_parameter_set_state), + .pic_parameter_set_state(pic_parameter_set_state), + .residual_state(residual_state), + .cavlc_decoder_state(cavlc_decoder_state), + .mb_num(mb_num), + .TotalCoeff(TotalCoeff), + .start_code_prefix_found(start_code_prefix_found), + .pc_2to0(pc[2:0]), + .deblocking_filter_control_present_flag(deblocking_filter_control_present_flag), + .disable_deblocking_filter_idc(disable_deblocking_filter_idc), + .end_of_one_residual_block(end_of_one_residual_block), + .Intra4x4PredMode_mbAddrB_cs_n(Intra4x4PredMode_mbAddrB_cs_n), + .mvx_mbAddrB_cs_n(mvx_mbAddrB_cs_n), + .mvy_mbAddrB_cs_n(mvy_mbAddrB_cs_n), + .mvx_mbAddrC_cs_n(mvx_mbAddrC_cs_n), + .mvy_mbAddrC_cs_n(mvy_mbAddrC_cs_n), + .LumaLevel_mbAddrB_cs_n(LumaLevel_mbAddrB_cs_n), + .ChromaLevel_Cb_mbAddrB_cs_n(ChromaLevel_Cb_mbAddrB_cs_n), + .ChromaLevel_Cr_mbAddrB_cs_n(ChromaLevel_Cr_mbAddrB_cs_n), + .trigger_CAVLC(trigger_CAVLC), + .blk4x4_rec_counter(blk4x4_rec_counter), + .end_of_DCBlk_IQIT(end_of_DCBlk_IQIT), + .end_of_one_blk4x4_sum(end_of_one_blk4x4_sum), + .end_of_MB_DEC(end_of_MB_DEC), + .disable_DF(disable_DF), + .bs_dec_counter(bs_dec_counter), + + .gclk_parser(gclk_parser), + .gclk_nal(gclk_nal), + .gclk_slice(gclk_slice), + .gclk_sps(gclk_sps), + .gclk_pps(gclk_pps), + .gclk_slice_header(gclk_slice_header), + .gclk_slice_data(gclk_slice_data), + .gclk_residual(gclk_residual), + .gclk_cavlc(gclk_cavlc), + .gclk_Intra4x4PredMode_mbAddrB_RF(gclk_Intra4x4PredMode_mbAddrB_RF), + .gclk_mvx_mbAddrB_RF(gclk_mvx_mbAddrB_RF), + .gclk_mvy_mbAddrB_RF(gclk_mvy_mbAddrB_RF), + .gclk_mvx_mbAddrC_RF(gclk_mvx_mbAddrC_RF), + .gclk_mvy_mbAddrC_RF(gclk_mvy_mbAddrC_RF), + .gclk_LumaLevel_mbAddrB_RF(gclk_LumaLevel_mbAddrB_RF), + .gclk_ChromaLevel_Cb_mbAddrB_RF(gclk_ChromaLevel_Cb_mbAddrB_RF), + .gclk_ChromaLevel_Cr_mbAddrB_RF(gclk_ChromaLevel_Cr_mbAddrB_RF), + .gclk_bs_dec(gclk_bs_dec), + .end_of_one_frame(end_of_one_frame) + ); + BitStream_parser_FSM BitStream_parser_FSM( + .clk(clk), + .reset_n(reset_n), + .end_of_one_blk4x4_sum(end_of_one_blk4x4_sum), + .end_of_MB_DEC(end_of_MB_DEC), + .gclk_parser(gclk_parser), + .gclk_nal(gclk_nal), + .gclk_slice(gclk_slice), + .gclk_sps(gclk_sps), + .gclk_pps(gclk_pps), + .gclk_slice_header(gclk_slice_header), + .gclk_slice_data(gclk_slice_data), + .gclk_residual(gclk_residual), + .gclk_cavlc(gclk_cavlc), + .trigger_CAVLC(trigger_CAVLC), + .BitStream_buffer_valid_n(BitStream_buffer_valid_n), + .nal_unit_type(nal_unit_type), + .slice_type(slice_type), + .num_ref_idx_active_override_flag(num_ref_idx_active_override_flag), + .deblocking_filter_control_present_flag(deblocking_filter_control_present_flag), + .disable_deblocking_filter_idc(disable_deblocking_filter_idc), + .mb_skip_run(mb_skip_run), + .mb_type_general(mb_type_general), + .prev_intra4x4_pred_mode_flag(prev_intra4x4_pred_mode_flag), + .CodedBlockPatternLuma(CodedBlockPatternLuma), + .CodedBlockPatternChroma(CodedBlockPatternChroma), + .pc_2to0(pc[2:0]), + .NumSubMbPart(NumSubMbPart), + .NumMbPart(NumMbPart), + .TotalCoeff(TotalCoeff), + .TrailingOnes(TrailingOnes), + .maxNumCoeff(maxNumCoeff), + .zerosLeft(zerosLeft), + .run(run), + + .parser_state(parser_state), + .nal_unit_state(nal_unit_state), + .slice_layer_wo_partitioning_state(slice_layer_wo_partitioning_state), + .slice_header_state(slice_header_state), + .slice_header_s6(slice_header_s6), + .ref_pic_list_reordering_state(ref_pic_list_reordering_state), + .dec_ref_pic_marking_state(dec_ref_pic_marking_state), + .slice_data_state(slice_data_state), + .sub_mb_pred_state(sub_mb_pred_state), + .mb_pred_state(mb_pred_state), + .seq_parameter_set_state(seq_parameter_set_state), + .pic_parameter_set_state(pic_parameter_set_state), + .residual_state(residual_state), + .cavlc_decoder_state(cavlc_decoder_state), + .heading_one_en(heading_one_en), + .pic_num(pic_num), + .mb_num(mb_num), + .mb_num_h(mb_num_h), + .mb_num_v(mb_num_v), + .NextMB_IsSkip(NextMB_IsSkip), + .LowerMB_IsSkip(LowerMB_IsSkip), + .Is_skip_run_entry(Is_skip_run_entry), + .Is_skip_run_end(Is_skip_run_end), + .luma4x4BlkIdx(luma4x4BlkIdx), + .mbPartIdx(mbPartIdx), + .subMbPartIdx(subMbPartIdx), + .compIdx(compIdx), + .i8x8(i8x8), + .i4x4(i4x4), + .i4x4_CbCr(i4x4_CbCr), + .coeffNum(coeffNum), + .i_level(i_level), + .i_run(i_run), + .i_TotalCoeff(i_TotalCoeff), + .suffix_length_initialized(suffix_length_initialized), + .IsRunLoop(IsRunLoop) + ); + pc_decoding pc_decoding ( + .clk(clk), + .reset_n(reset_n), + .parser_state(parser_state), + .nal_unit_state(nal_unit_state), + .slice_header_state(slice_header_state), + .ref_pic_list_reordering_state(ref_pic_list_reordering_state), + .dec_ref_pic_marking_state(dec_ref_pic_marking_state), + .slice_data_state(slice_data_state), + .sub_mb_pred_state(sub_mb_pred_state), + .mb_pred_state(mb_pred_state), + .seq_parameter_set_state(seq_parameter_set_state), + .pic_parameter_set_state(pic_parameter_set_state), + .exp_golomb_len(exp_golomb_len), + .dependent_variable_len(dependent_variable_len), + .cavlc_consumed_bits_len(cavlc_consumed_bits_len), + .pc(pc) + ); + heading_one_detector heading_one_detector ( + .heading_one_en(heading_one_en), + .BitStream_buffer_output(BitStream_buffer_output), + .heading_one_pos(heading_one_pos) + ); + exp_golomb_decoding exp_golomb_decoding ( + .reset_n(reset_n), + .heading_one_pos(heading_one_pos), + .BitStream_buffer_output(BitStream_buffer_output), + .num_ref_idx_l0_active_minus1(num_ref_idx_l0_active_minus1), + .exp_golomb_decoding_output(exp_golomb_decoding_output), + .exp_golomb_len(exp_golomb_len), + .slice_header_state(slice_header_state), + .slice_data_state(slice_data_state), + .mb_pred_state(mb_pred_state), + .sub_mb_pred_state(sub_mb_pred_state), + .seq_parameter_set_state(seq_parameter_set_state), + .pic_parameter_set_state(pic_parameter_set_state) + ); + dependent_variable_decoding dependent_variable_decoding ( + .slice_header_state(slice_header_state), + .log2_max_frame_num_minus4(log2_max_frame_num_minus4), + .log2_max_pic_order_cnt_lsb_minus4(log2_max_pic_order_cnt_lsb_minus4), + .BitStream_buffer_output(BitStream_buffer_output), + .dependent_variable_len(dependent_variable_len), + .dependent_variable_decoding_output(dependent_variable_decoding_output) + ); + QP_decoding QP_decoding ( + .clk(clk), + .reset_n(reset_n), + .slice_header_state(slice_header_state), + .slice_data_state(slice_data_state), + .pic_init_qp_minus26(pic_init_qp_minus26), + .exp_golomb_decoding_output_5to0(exp_golomb_decoding_output[5:0]), + .chroma_qp_index_offset(chroma_qp_index_offset), + .QPy(QPy), + .QPc(QPc) + ); + CodedBlockPattern_decoding CodedBlockPattern_decoding ( + .clk(clk), + .reset_n(reset_n), + .slice_data_state(slice_data_state), + .slice_type(slice_type), + .mb_type(mb_type), + .mb_type_general(mb_type_general), + .exp_golomb_decoding_output_5to0(exp_golomb_decoding_output[5:0]), + .CodedBlockPatternLuma(CodedBlockPatternLuma), + .CodedBlockPatternChroma(CodedBlockPatternChroma) + ); + Intra4x4_PredMode_decoding Intra4x4_PredMode_decoding ( + .clk(clk), + .reset_n(reset_n), + .mb_pred_state(mb_pred_state), + .luma4x4BlkIdx(luma4x4BlkIdx), + .mb_num_h(mb_num_h), + .mb_num_v(mb_num_v), + .MBTypeGen_mbAddrA(MBTypeGen_mbAddrA), + .MBTypeGen_mbAddrB_reg(MBTypeGen_mbAddrB_reg), + .constrained_intra_pred_flag(constrained_intra_pred_flag), + .rem_intra4x4_pred_mode(rem_intra4x4_pred_mode), + .prev_intra4x4_pred_mode_flag(prev_intra4x4_pred_mode_flag), + .Intra4x4PredMode_mbAddrB_dout(Intra4x4PredMode_mbAddrB_dout), + //pic_num can be wired out for debug purpose + //.pic_num(pic_num), + + .Intra4x4PredMode_CurrMb(Intra4x4_predmode_CurrMb), + .Intra4x4PredMode_mbAddrB_cs_n(Intra4x4PredMode_mbAddrB_cs_n), + .Intra4x4PredMode_mbAddrB_wr_n(Intra4x4PredMode_mbAddrB_wr_n), + .Intra4x4PredMode_mbAddrB_rd_addr(Intra4x4PredMode_mbAddrB_rd_addr), + .Intra4x4PredMode_mbAddrB_wr_addr(Intra4x4PredMode_mbAddrB_wr_addr), + .Intra4x4PredMode_mbAddrB_din(Intra4x4PredMode_mbAddrB_din) + ); + ram_async_1r_sync_1w # (`Intra4x4_PredMode_RF_data_width,`Intra4x4_PredMode_RF_data_depth) + Intra4x4_PredMode_RF ( + .clk(gclk_Intra4x4PredMode_mbAddrB_RF), + .rst_n(reset_n), + .cs_n(Intra4x4PredMode_mbAddrB_cs_n), + .wr_n(Intra4x4PredMode_mbAddrB_wr_n), + .rd_addr(Intra4x4PredMode_mbAddrB_rd_addr), + .wr_addr(Intra4x4PredMode_mbAddrB_wr_addr), + .data_in(Intra4x4PredMode_mbAddrB_din), + .data_out(Intra4x4PredMode_mbAddrB_dout) + ); + Inter_mv_decoding Inter_mv_decoding ( + .clk(clk), + .reset_n(reset_n), + .Is_skip_run_entry(Is_skip_run_entry), + .Is_skip_run_end(Is_skip_run_end), + .slice_data_state(slice_data_state), + .mb_pred_state(mb_pred_state), + .sub_mb_pred_state(sub_mb_pred_state), + .mvd(mvd), + .mb_num(mb_num), + .mb_num_h(mb_num_h), + .mb_num_v(mb_num_v), + .mb_type_general(mb_type_general), + .sub_mb_type(sub_mb_type), + .end_of_MB_DEC(end_of_MB_DEC), + .mbPartIdx(mbPartIdx), + .subMbPartIdx(subMbPartIdx), + .compIdx(compIdx), + .MBTypeGen_mbAddrA(MBTypeGen_mbAddrA), + .MBTypeGen_mbAddrB_reg(MBTypeGen_mbAddrB_reg), + .MBTypeGen_mbAddrD(MBTypeGen_mbAddrD), + .mvx_mbAddrB_dout(mvx_mbAddrB_dout), + .mvy_mbAddrB_dout(mvy_mbAddrB_dout), + .mvx_mbAddrC_dout(mvx_mbAddrC_dout), + .mvy_mbAddrC_dout(mvy_mbAddrC_dout), + .mv_mbAddrB_rd_for_DF(mv_mbAddrB_rd_for_DF), + + .skip_mv_calc(skip_mv_calc), + .Is_skipMB_mv_calc(Is_skipMB_mv_calc), + .mvx_mbAddrA(mvx_mbAddrA), + .mvy_mbAddrA(mvy_mbAddrA), + .mvx_mbAddrB_cs_n(mvx_mbAddrB_cs_n), + .mvx_mbAddrB_wr_n(mvx_mbAddrB_wr_n), + .mvx_mbAddrB_rd_addr(mvx_mbAddrB_rd_addr), + .mvx_mbAddrB_wr_addr(mvx_mbAddrB_wr_addr), + .mvx_mbAddrB_din(mvx_mbAddrB_din), + .mvy_mbAddrB_cs_n(mvy_mbAddrB_cs_n), + .mvy_mbAddrB_wr_n(mvy_mbAddrB_wr_n), + .mvy_mbAddrB_rd_addr(mvy_mbAddrB_rd_addr), + .mvy_mbAddrB_wr_addr(mvy_mbAddrB_wr_addr), + .mvy_mbAddrB_din(mvy_mbAddrB_din), + .mvx_mbAddrC_cs_n(mvx_mbAddrC_cs_n), + .mvx_mbAddrC_wr_n(mvx_mbAddrC_wr_n), + .mvx_mbAddrC_rd_addr(mvx_mbAddrC_rd_addr), + .mvx_mbAddrC_wr_addr(mvx_mbAddrC_wr_addr), + .mvx_mbAddrC_din(mvx_mbAddrC_din), + .mvy_mbAddrC_cs_n(mvy_mbAddrC_cs_n), + .mvy_mbAddrC_wr_n(mvy_mbAddrC_wr_n), + .mvy_mbAddrC_rd_addr(mvy_mbAddrC_rd_addr), + .mvy_mbAddrC_wr_addr(mvy_mbAddrC_wr_addr), + .mvy_mbAddrC_din(mvy_mbAddrC_din), + .mv_is16x16(mv_is16x16), + .mvx_CurrMb0(mvx_CurrMb0), + .mvx_CurrMb1(mvx_CurrMb1), + .mvx_CurrMb2(mvx_CurrMb2), + .mvx_CurrMb3(mvx_CurrMb3), + .mvy_CurrMb0(mvy_CurrMb0), + .mvy_CurrMb1(mvy_CurrMb1), + .mvy_CurrMb2(mvy_CurrMb2), + .mvy_CurrMb3(mvy_CurrMb3) + ); + ram_async_1r_sync_1w # (`mvx_mbAddrB_RF_data_width,`mvx_mbAddrB_RF_data_depth) + mvx_mbAddrB_RF ( + .clk(gclk_mvx_mbAddrB_RF), + .rst_n(reset_n), + .cs_n(mvx_mbAddrB_cs_n), + .wr_n(mvx_mbAddrB_wr_n), + .rd_addr(mvx_mbAddrB_rd_addr), + .wr_addr(mvx_mbAddrB_wr_addr), + .data_in(mvx_mbAddrB_din), + .data_out(mvx_mbAddrB_dout) + ); + ram_async_1r_sync_1w # (`mvy_mbAddrB_RF_data_width,`mvy_mbAddrB_RF_data_depth) + mvy_mbAddrB_RF ( + .clk(gclk_mvy_mbAddrB_RF), + .rst_n(reset_n), + .cs_n(mvy_mbAddrB_cs_n), + .wr_n(mvy_mbAddrB_wr_n), + .rd_addr(mvy_mbAddrB_rd_addr), + .wr_addr(mvy_mbAddrB_wr_addr), + .data_in(mvy_mbAddrB_din), + .data_out(mvy_mbAddrB_dout) + ); + ram_async_1r_sync_1w # (`mvx_mbAddrC_RF_data_width,`mvx_mbAddrC_RF_data_depth) + mvx_mbAddrC_RF ( + .clk(gclk_mvx_mbAddrC_RF), + .rst_n(reset_n), + .cs_n(mvx_mbAddrC_cs_n), + .wr_n(mvx_mbAddrC_wr_n), + .rd_addr(mvx_mbAddrC_rd_addr), + .wr_addr(mvx_mbAddrC_wr_addr), + .data_in(mvx_mbAddrC_din), + .data_out(mvx_mbAddrC_dout) + ); + ram_async_1r_sync_1w # (`mvy_mbAddrC_RF_data_width,`mvy_mbAddrC_RF_data_depth) + mvy_mbAddrC_RF ( + .clk(gclk_mvy_mbAddrC_RF), + .rst_n(reset_n), + .cs_n(mvy_mbAddrC_cs_n), + .wr_n(mvy_mbAddrC_wr_n), + .rd_addr(mvy_mbAddrC_rd_addr), + .wr_addr(mvy_mbAddrC_wr_addr), + .data_in(mvy_mbAddrC_din), + .data_out(mvy_mbAddrC_dout) + ); + syntax_decoding syntax_decoding ( + .clk(clk), + .reset_n(reset_n), + .mb_num_h(mb_num_h), + .mb_num_v(mb_num_v), + .end_of_MB_DEC(end_of_MB_DEC), + .pin_disable_DF(pin_disable_DF), + .parser_state(parser_state), + .nal_unit_state(nal_unit_state), + .seq_parameter_set_state(seq_parameter_set_state), + .pic_parameter_set_state(pic_parameter_set_state), + .slice_header_state(slice_header_state), + .slice_data_state(slice_data_state), + .mb_pred_state(mb_pred_state), + .sub_mb_pred_state(sub_mb_pred_state), + .exp_golomb_decoding_output(exp_golomb_decoding_output), + .BitStream_buffer_output(BitStream_buffer_output), + .dependent_variable_decoding_output(dependent_variable_decoding_output), + .mbPartIdx(mbPartIdx), + + .nal_unit_type(nal_unit_type), + .start_code_prefix_found(start_code_prefix_found), + .deblocking_filter_control_present_flag(deblocking_filter_control_present_flag), + .disable_deblocking_filter_idc(disable_deblocking_filter_idc), + .disable_DF(disable_DF), + .slice_alpha_c0_offset_div2(slice_alpha_c0_offset_div2), + .slice_beta_offset_div2(slice_beta_offset_div2), + .mb_skip_run(mb_skip_run), + .NumMbPart(NumMbPart), + .NumSubMbPart(NumSubMbPart), + .MBTypeGen_mbAddrA(MBTypeGen_mbAddrA), + .MBTypeGen_mbAddrD(MBTypeGen_mbAddrD), + .MBTypeGen_mbAddrB_reg(MBTypeGen_mbAddrB_reg), + .log2_max_frame_num_minus4(log2_max_frame_num_minus4), + .log2_max_pic_order_cnt_lsb_minus4(log2_max_pic_order_cnt_lsb_minus4), + .constrained_intra_pred_flag(constrained_intra_pred_flag), + .num_ref_idx_active_override_flag(num_ref_idx_active_override_flag), + .num_ref_idx_l0_active_minus1(num_ref_idx_l0_active_minus1), + .slice_type(slice_type), + .mb_type(mb_type), + .mb_type_general(mb_type_general), + .Intra16x16_predmode(Intra16x16_predmode), + .intra_chroma_pred_mode(Intra_chroma_predmode), + .sub_mb_type(sub_mb_type), + .pic_init_qp_minus26(pic_init_qp_minus26), + .chroma_qp_index_offset(chroma_qp_index_offset), + .rem_intra4x4_pred_mode(rem_intra4x4_pred_mode), + .prev_intra4x4_pred_mode_flag(prev_intra4x4_pred_mode_flag), + .mvd(mvd), + .mv_below8x8(mv_below8x8) + ); + cavlc_decoder cavlc_decoder( + .clk(clk), + .reset_n(reset_n), + .gclk_end_of_MB_DEC(gclk_end_of_MB_DEC), + .gclk_LumaLevel_mbAddrB_RF(gclk_LumaLevel_mbAddrB_RF), + .gclk_ChromaLevel_Cb_mbAddrB_RF(gclk_ChromaLevel_Cb_mbAddrB_RF), + .gclk_ChromaLevel_Cr_mbAddrB_RF(gclk_ChromaLevel_Cr_mbAddrB_RF), + .slice_data_state(slice_data_state), + .residual_state(residual_state), + .cavlc_decoder_state(cavlc_decoder_state), + .mb_num_h(mb_num_h), + .mb_num_v(mb_num_v), + .i8x8(i8x8), + .i4x4(i4x4), + .i4x4_CbCr(i4x4_CbCr), + .i_level(i_level), + .i_run(i_run), + .i_TotalCoeff(i_TotalCoeff), + .coeffNum(coeffNum), + .heading_one_pos(heading_one_pos), + .BitStream_buffer_output(BitStream_buffer_output), + .CodedBlockPatternLuma(CodedBlockPatternLuma), + .CodedBlockPatternChroma(CodedBlockPatternChroma), + .suffix_length_initialized(suffix_length_initialized), + .IsRunLoop(IsRunLoop), + + .Luma_8x8_AllZeroCoeff_mbAddrA(Luma_8x8_AllZeroCoeff_mbAddrA), + .LumaLevel_mbAddrA(LumaLevel_mbAddrA), + .LumaLevel_CurrMb0(LumaLevel_CurrMb0), + .LumaLevel_CurrMb1(LumaLevel_CurrMb1), + .LumaLevel_CurrMb2(LumaLevel_CurrMb2), + .LumaLevel_CurrMb3(LumaLevel_CurrMb3), + .LumaLevel_mbAddrB_dout(LumaLevel_mbAddrB_dout), + .LumaLevel_mbAddrB_cs_n(LumaLevel_mbAddrB_cs_n), + .ChromaLevel_Cb_mbAddrB_cs_n(ChromaLevel_Cb_mbAddrB_cs_n), + .ChromaLevel_Cr_mbAddrB_cs_n(ChromaLevel_Cr_mbAddrB_cs_n), + .end_of_one_residual_block(end_of_one_residual_block), + .end_of_NonZeroCoeff_CAVLC(end_of_NonZeroCoeff_CAVLC), + .cavlc_consumed_bits_len(cavlc_consumed_bits_len), + .TotalCoeff(TotalCoeff), + .TrailingOnes(TrailingOnes), + .maxNumCoeff(maxNumCoeff), + .zerosLeft(zerosLeft), + .run(run), + .coeffLevel_0(coeffLevel_0), + .coeffLevel_1(coeffLevel_1), + .coeffLevel_2(coeffLevel_2), + .coeffLevel_3(coeffLevel_3), + .coeffLevel_4(coeffLevel_4), + .coeffLevel_5(coeffLevel_5), + .coeffLevel_6(coeffLevel_6), + .coeffLevel_7(coeffLevel_7), + .coeffLevel_8(coeffLevel_8), + .coeffLevel_9(coeffLevel_9), + .coeffLevel_10(coeffLevel_10), + .coeffLevel_11(coeffLevel_11), + .coeffLevel_12(coeffLevel_12), + .coeffLevel_13(coeffLevel_13), + .coeffLevel_14(coeffLevel_14), + .coeffLevel_15(coeffLevel_15) + ); + bs_decoding bs_decoding ( + .clk(clk), + .reset_n(reset_n), + .gclk_end_of_MB_DEC(gclk_end_of_MB_DEC), + .gclk_bs_dec(gclk_bs_dec), + .end_of_MB_DEC(end_of_MB_DEC), + .end_of_one_blk4x4_sum(end_of_one_blk4x4_sum), + .mb_num_h(mb_num_h), + .mb_num_v(mb_num_v), + .disable_DF(disable_DF), + .blk4x4_rec_counter(blk4x4_rec_counter), + .CodedBlockPatternLuma(CodedBlockPatternLuma), + .mb_type_general(mb_type_general), + .slice_data_state(slice_data_state), + .residual_state(residual_state), + .MBTypeGen_mbAddrA(MBTypeGen_mbAddrA), + .MBTypeGen_mbAddrB_reg(MBTypeGen_mbAddrB_reg), + .end_of_one_residual_block(end_of_one_residual_block), + .TotalCoeff(TotalCoeff), + .curr_DC_IsZero(curr_DC_IsZero), + .Is_skipMB_mv_calc(Is_skipMB_mv_calc), + .mvx_mbAddrA(mvx_mbAddrA), + .mvy_mbAddrA(mvy_mbAddrA), + .mvx_mbAddrB_dout(mvx_mbAddrB_dout), + .mvy_mbAddrB_dout(mvy_mbAddrB_dout), + .mvx_CurrMb0(mvx_CurrMb0), + .mvx_CurrMb1(mvx_CurrMb1), + .mvx_CurrMb2(mvx_CurrMb2), + .mvx_CurrMb3(mvx_CurrMb3), + .mvy_CurrMb0(mvy_CurrMb0), + .mvy_CurrMb1(mvy_CurrMb1), + .mvy_CurrMb2(mvy_CurrMb2), + .mvy_CurrMb3(mvy_CurrMb3), + + .bs_dec_counter(bs_dec_counter), + .end_of_BS_DEC(end_of_BS_DEC), + .mv_mbAddrB_rd_for_DF(mv_mbAddrB_rd_for_DF), + .bs_V0(bs_V0), + .bs_V1(bs_V1), + .bs_V2(bs_V2), + .bs_V3(bs_V3), + .bs_H0(bs_H0), + .bs_H1(bs_H1), + .bs_H2(bs_H2), + .bs_H3(bs_H3) + ); +endmodule + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/BitStream_parser_FSM_gating.v b/demo_chip_rtl/rtl/nova/trunk/src/BitStream_parser_FSM_gating.v new file mode 100644 index 0000000..5989a40 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/BitStream_parser_FSM_gating.v @@ -0,0 +1,639 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : BitStream_parser_FSM_gating.v +// Generated : June 26,2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// BitStream_parser_FSM,clock gating version +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module BitStream_parser_FSM (clk,reset_n,end_of_one_blk4x4_sum,end_of_MB_DEC, + gclk_parser,gclk_nal,gclk_slice,gclk_sps,gclk_pps,gclk_slice_header, + gclk_slice_data,gclk_residual,gclk_cavlc, + trigger_CAVLC,BitStream_buffer_valid_n,nal_unit_type, + slice_type,num_ref_idx_active_override_flag, + deblocking_filter_control_present_flag,disable_deblocking_filter_idc, + mb_skip_run,mb_type_general,prev_intra4x4_pred_mode_flag,CodedBlockPatternLuma, + CodedBlockPatternChroma,pc_2to0,NumSubMbPart,NumMbPart, + TotalCoeff,TrailingOnes,maxNumCoeff,zerosLeft,run, + + parser_state,nal_unit_state,slice_layer_wo_partitioning_state,slice_header_state,slice_header_s6, + ref_pic_list_reordering_state,dec_ref_pic_marking_state,slice_data_state,sub_mb_pred_state, + mb_pred_state,seq_parameter_set_state,pic_parameter_set_state,residual_state,cavlc_decoder_state, + heading_one_en,pic_num,mb_num,mb_num_h,mb_num_v, + NextMB_IsSkip,LowerMB_IsSkip,Is_skip_run_entry,Is_skip_run_end, + luma4x4BlkIdx,mbPartIdx,subMbPartIdx,compIdx,i8x8,i4x4,i4x4_CbCr, + coeffNum,i_level,i_run,i_TotalCoeff, + suffix_length_initialized,IsRunLoop); + input clk; + input reset_n; + input end_of_one_blk4x4_sum; + input end_of_MB_DEC; + input gclk_parser; + input gclk_nal; + input gclk_slice; + input gclk_sps; + input gclk_pps; + input gclk_slice_header; + input gclk_slice_data; + input gclk_residual; + input gclk_cavlc; + input trigger_CAVLC; + input BitStream_buffer_valid_n; + input [4:0] nal_unit_type; + input [2:0] slice_type; + input num_ref_idx_active_override_flag; + input deblocking_filter_control_present_flag; + input [1:0] disable_deblocking_filter_idc; + input [6:0] mb_skip_run; + input [3:0] mb_type_general; + input prev_intra4x4_pred_mode_flag; + input [3:0] CodedBlockPatternLuma; + input [1:0] CodedBlockPatternChroma; + input [2:0] pc_2to0; + input [2:0] NumMbPart; + input [2:0] NumSubMbPart; + input [4:0] TotalCoeff; + input [1:0] TrailingOnes; + input [4:0] maxNumCoeff; + input [3:0] zerosLeft; + input [3:0] run; + + output [1:0] parser_state; + output [2:0] nal_unit_state; + output [1:0] slice_layer_wo_partitioning_state; + output [3:0] slice_header_state; + output slice_header_s6; + output [2:0] ref_pic_list_reordering_state; + output [1:0] dec_ref_pic_marking_state; + output [3:0] slice_data_state; + output [1:0] sub_mb_pred_state; + output [2:0] mb_pred_state; + output [3:0] seq_parameter_set_state; + output [3:0] pic_parameter_set_state; + output [3:0] residual_state; + output [3:0] cavlc_decoder_state; + output heading_one_en; + output [5:0] pic_num; + output [6:0] mb_num; + output [3:0] mb_num_h; + output [3:0] mb_num_v; + output NextMB_IsSkip; + output LowerMB_IsSkip; + output Is_skip_run_entry; + output Is_skip_run_end; + output [3:0] luma4x4BlkIdx; + output [1:0] mbPartIdx; + output [1:0] subMbPartIdx; + output compIdx; + output [1:0] i8x8,i4x4; + output [1:0] i4x4_CbCr; + output [3:0] coeffNum; + output [3:0] i_level; + output [3:0] i_run; + output [3:0] i_TotalCoeff; + output suffix_length_initialized; + output IsRunLoop; + + reg [1:0] parser_state; + reg [2:0] nal_unit_state; + reg [1:0] slice_layer_wo_partitioning_state; + reg [3:0] seq_parameter_set_state; + reg [3:0] pic_parameter_set_state; + reg [3:0] slice_header_state; + reg [2:0] ref_pic_list_reordering_state; + reg [1:0] dec_ref_pic_marking_state; + reg [3:0] slice_data_state; + reg [2:0] mb_pred_state; + reg [1:0] sub_mb_pred_state; + reg [3:0] residual_state; + reg [3:0] cavlc_decoder_state; + + wire heading_one_en; + reg [6:0] mb_num; + reg [3:0] mb_num_h; + reg [3:0] mb_num_v; + reg [1:0] mbPartIdx; + reg [1:0] subMbPartIdx; + reg compIdx; + reg [1:0] i8x8,i4x4; + reg [1:0] i4x4_CbCr; + reg [3:0] coeffNum; + reg [3:0] coeffNum_reg; + reg [3:0] i_level,i_run,i_TotalCoeff; + reg [6:0] count_mb_skip_run;//number of MBs to be skipped + reg [7:0] count_pcm_byte; + reg [3:0] luma4x4BlkIdx; + reg [5:0] pic_num; + reg suffix_length_initialized; + reg IsRunLoop; + + /* + // synopsys translate_off + integer tracefile; + initial + begin + tracefile = $fopen("trace.txt"); + end + // synopsys translate_on + */ + + //-------------- + //parser_state + //-------------- + always @ (posedge gclk_parser or negedge reset_n) + if (reset_n == 0) + parser_state <= `rst_parser; + else + case (parser_state) + `rst_parser :parser_state <= (BitStream_buffer_valid_n == 1'b0)? `start_code_prefix:`rst_parser; + `start_code_prefix:parser_state <= `nal_unit; + `nal_unit :parser_state <= `rst_parser; + endcase + //--------------- + //nal_unit_state + //--------------- + always @ (posedge gclk_nal or negedge reset_n) + if (reset_n == 0) + nal_unit_state <= `rst_nal_unit; + else + case (nal_unit_state) + `rst_nal_unit:nal_unit_state <= `forbidden_zero_bit_2_nal_unit_type; + `forbidden_zero_bit_2_nal_unit_type: + case (nal_unit_type) + 5'b00001:nal_unit_state <= `slice_layer_non_IDR_rbsp; + 5'b00101:nal_unit_state <= `slice_layer_IDR_rbsp; + 5'b00111:nal_unit_state <= `seq_parameter_set_rbsp; + 5'b01000:nal_unit_state <= `pic_parameter_set_rbsp; + endcase + `slice_layer_non_IDR_rbsp,`slice_layer_IDR_rbsp:nal_unit_state <= `rbsp_trailing_one_bit; + `seq_parameter_set_rbsp :nal_unit_state <= `rbsp_trailing_one_bit; + `pic_parameter_set_rbsp :nal_unit_state <= `rbsp_trailing_one_bit; + `rbsp_trailing_one_bit :nal_unit_state <= (pc_2to0 == 3'b000)? `rst_nal_unit:`rbsp_trailing_zero_bits; + `rbsp_trailing_zero_bits:nal_unit_state <= `rst_nal_unit; + endcase + //---------------------------------- + //slice_layer_wo_partitioning_state + //---------------------------------- + always @ (posedge gclk_slice or negedge reset_n) + if (reset_n == 1'b0) + slice_layer_wo_partitioning_state <= `rst_slice_layer_wo_partitioning; + else + case (slice_layer_wo_partitioning_state) + `rst_slice_layer_wo_partitioning :slice_layer_wo_partitioning_state <= `slice_header; + `slice_header :slice_layer_wo_partitioning_state <= `slice_data; + `slice_data :slice_layer_wo_partitioning_state <= `rst_slice_layer_wo_partitioning; + endcase + //------------------------ + //seq_parameter_set_state + //------------------------ + always @ (posedge gclk_sps or negedge reset_n) + if (reset_n == 0) + seq_parameter_set_state <= `rst_seq_parameter_set; + else + case (seq_parameter_set_state) + `rst_seq_parameter_set :seq_parameter_set_state <= `fixed_header; + `fixed_header :seq_parameter_set_state <= `level_idc_s; + `level_idc_s :seq_parameter_set_state <= `seq_parameter_set_id_sps_s; + `seq_parameter_set_id_sps_s :seq_parameter_set_state <= `log2_max_frame_num_minus4_s; + `log2_max_frame_num_minus4_s :seq_parameter_set_state <= `pic_order_cnt_type_s; + `pic_order_cnt_type_s :seq_parameter_set_state <= `log2_max_pic_order_cnt_lsb_minus4_s; + `log2_max_pic_order_cnt_lsb_minus4_s :seq_parameter_set_state <= `num_ref_frames_s; + `num_ref_frames_s :seq_parameter_set_state <= `gaps_in_frame_num_value_allowed_flag_s; + `gaps_in_frame_num_value_allowed_flag_s :seq_parameter_set_state <= `pic_width_in_mbs_minus1_s; + `pic_width_in_mbs_minus1_s :seq_parameter_set_state <= `pic_height_in_map_units_minus1_s; + `pic_height_in_map_units_minus1_s :seq_parameter_set_state <= `frame_mbs_only_flag_2_frame_cropping_flag; + `frame_mbs_only_flag_2_frame_cropping_flag:seq_parameter_set_state <= `vui_parameter_present_flag_s; + `vui_parameter_present_flag_s :seq_parameter_set_state <= `rst_seq_parameter_set; + endcase + //------------------------ + //pic_parameter_set_state + //------------------------ + always @ (posedge gclk_pps or negedge reset_n) + if (reset_n == 0) + pic_parameter_set_state <= `rst_pic_parameter_set; + else + case (pic_parameter_set_state) + `rst_pic_parameter_set :pic_parameter_set_state <= `pic_parameter_set_id_pps_s; + `pic_parameter_set_id_pps_s :pic_parameter_set_state <= `seq_parameter_set_id_pps_s; + `seq_parameter_set_id_pps_s :pic_parameter_set_state <= `entropy_coding_mode_flag_2_pic_order_present_flag; + `entropy_coding_mode_flag_2_pic_order_present_flag :pic_parameter_set_state <= `num_slice_groups_minus1_s; + `num_slice_groups_minus1_s :pic_parameter_set_state <= `num_ref_idx_l0_active_minus1_pps_s; + `num_ref_idx_l0_active_minus1_pps_s :pic_parameter_set_state <= `num_ref_idx_l1_active_minus1_pps_s; + `num_ref_idx_l1_active_minus1_pps_s :pic_parameter_set_state <= `weighted_pred_flag_2_weighted_bipred_idc; + `weighted_pred_flag_2_weighted_bipred_idc :pic_parameter_set_state <= `pic_init_qp_minus26_s; + `pic_init_qp_minus26_s :pic_parameter_set_state <= `pic_init_qs_minus26_s; + `pic_init_qs_minus26_s :pic_parameter_set_state <= `chroma_qp_index_offset_s; + `chroma_qp_index_offset_s :pic_parameter_set_state <= `deblocking_filter_control_2_redundant_pic_cnt_present_flag; + `deblocking_filter_control_2_redundant_pic_cnt_present_flag:pic_parameter_set_state <= `rst_pic_parameter_set; + endcase + //------------------- + //slice_header_state + //------------------- + always @ (posedge gclk_slice_header or negedge reset_n) + if (reset_n == 0) + begin + slice_header_state <= `rst_slice_header; + ref_pic_list_reordering_state <= `rst_ref_pic_list_reordering; + dec_ref_pic_marking_state <= `rst_dec_ref_pic_marking; + end + else + case (slice_header_state) + `rst_slice_header :slice_header_state <= `first_mb_in_slice_s; + `first_mb_in_slice_s :slice_header_state <= `slice_type_s; + `slice_type_s :slice_header_state <= `pic_parameter_set_id_slice_header_s; + `pic_parameter_set_id_slice_header_s:slice_header_state <= `frame_num_s; + `frame_num_s: + if (nal_unit_type == 5'b00101) slice_header_state <= `idr_pic_id_s; + else slice_header_state <= `pic_order_cnt_lsb_s; + `idr_pic_id_s :slice_header_state <= `pic_order_cnt_lsb_s; + `pic_order_cnt_lsb_s: + if (slice_type == 3'b101) slice_header_state <= `num_ref_idx_active_override_flag_s; + else slice_header_state <= `dec_ref_pic_marking; + `num_ref_idx_active_override_flag_s: + if (num_ref_idx_active_override_flag == 1'b1) slice_header_state <= `num_ref_idx_l0_active_minus1_slice_header_s; + else slice_header_state <= `ref_pic_list_reordering; + `num_ref_idx_l0_active_minus1_slice_header_s :slice_header_state <= `ref_pic_list_reordering; + `ref_pic_list_reordering: + case (ref_pic_list_reordering_state) + `rst_ref_pic_list_reordering: + if (slice_type == 3'b101) + ref_pic_list_reordering_state <= `ref_pic_list_reordering_flag_l0_s; + else + begin + ref_pic_list_reordering_state <= `rst_ref_pic_list_reordering; + slice_header_state <= `dec_ref_pic_marking; + end + `ref_pic_list_reordering_flag_l0_s: + begin + ref_pic_list_reordering_state <= `rst_ref_pic_list_reordering; + slice_header_state <= `dec_ref_pic_marking; + end + endcase + `dec_ref_pic_marking: + case (dec_ref_pic_marking_state) + `rst_dec_ref_pic_marking: + dec_ref_pic_marking_state <= (nal_unit_type == 3'b101)? `no_output_of_prior_pics_flag_2_long_term_reference_flag:`adaptive_ref_pic_marking_mode_flag_s; + `no_output_of_prior_pics_flag_2_long_term_reference_flag: + begin + dec_ref_pic_marking_state <= `rst_dec_ref_pic_marking; + slice_header_state <= `slice_qp_delta_s; + end + `adaptive_ref_pic_marking_mode_flag_s: + begin + dec_ref_pic_marking_state <= `rst_dec_ref_pic_marking; + slice_header_state <= `slice_qp_delta_s; + end + endcase + `slice_qp_delta_s: + slice_header_state <= (deblocking_filter_control_present_flag == 1'b1)? `disable_deblocking_filter_idc_s:`rst_slice_header; + `disable_deblocking_filter_idc_s: + slice_header_state <= (disable_deblocking_filter_idc != 2'b01)? `slice_alpha_c0_offset_div2_s:`rst_slice_header; + `slice_alpha_c0_offset_div2_s:slice_header_state <= `slice_beta_offset_div2_s; + `slice_beta_offset_div2_s :slice_header_state <= `rst_slice_header; + endcase + + assign slice_header_s6 = (slice_header_state == `frame_num_s)? 1'b1:1'b0; + //------------------ + //slice_data_state + //------------------ + reg Is_skip_run_entry; //for trigger inter pred.Originally it's a wire type which will trigger inter_pred signal too early + //than expected:cause inter_pred rise up before mv_below8x8 is set to 4'b0 for P_skip.Thus the + //preload_counter after inter_pred will sample wrong mv_below8x8/mv_below8x8_curr. + //Then it is changed to reg type to appear one cycle later @ May 15,2006 + wire Is_skip_run_end; //for stop triggering inter pred + + always @ (posedge clk) + if (reset_n == 1'b0) + Is_skip_run_entry <= 1'b0; + else if (slice_data_state == `mb_skip_run_s && mb_skip_run != 0) + Is_skip_run_entry <= 1'b1; + else + Is_skip_run_entry <= 1'b0; + + assign Is_skip_run_end = (slice_data_state == `skip_run_duration && end_of_MB_DEC && (mb_num == 98 || count_mb_skip_run == (mb_skip_run - 1)))? 1'b1:1'b0; + + always @ (posedge gclk_slice_data or negedge reset_n) + if (reset_n == 0) + begin + slice_data_state <= `rst_slice_data; + mb_pred_state <= `rst_mb_pred; + sub_mb_pred_state <= `rst_sub_mb_pred; + end + else + case (slice_data_state) + `rst_slice_data :slice_data_state <= (slice_type != 3'b111)? `mb_skip_run_s:`mb_type_s; + `mb_skip_run_s :slice_data_state <= (mb_skip_run == 0)? `mb_type_s:`skip_run_duration; + `skip_run_duration:slice_data_state <= (mb_num == 98)? `rst_slice_data:(count_mb_skip_run < (mb_skip_run - 1))? `skip_run_duration:`mb_type_s; + `mb_type_s :slice_data_state <= (mb_type_general == `MB_P_8x8 || mb_type_general == `MB_P_8x8ref0)? `sub_mb_pred:`mb_pred; + `sub_mb_pred: + case (sub_mb_pred_state) + `rst_sub_mb_pred:sub_mb_pred_state <= `sub_mb_type_s; + `sub_mb_type_s :sub_mb_pred_state <= (mbPartIdx == 2'b11)? `sub_mvd_l0_s:`sub_mb_type_s; + `sub_mvd_l0_s: + if (mbPartIdx == 2'b11 && {1'b0,subMbPartIdx} == (NumSubMbPart - 1) && compIdx == 1'b1) + begin + sub_mb_pred_state <= `rst_sub_mb_pred; + slice_data_state <= `coded_block_pattern_s; + end + endcase + `mb_pred: + case (mb_pred_state) + `rst_mb_pred: + if (mb_type_general[3] == 1'b1) //Intra + mb_pred_state <= (mb_type_general == `MB_Intra4x4)? `prev_intra4x4_pred_mode_flag_s:`intra_chroma_pred_mode_s; + else + mb_pred_state <= `mvd_l0_s; + `prev_intra4x4_pred_mode_flag_s: + mb_pred_state <= (prev_intra4x4_pred_mode_flag == 1'b0)? `rem_intra4x4_pred_mode_s: + (luma4x4BlkIdx == 4'b1111)? `intra_chroma_pred_mode_s:`prev_intra4x4_pred_mode_flag_s; + `rem_intra4x4_pred_mode_s: + mb_pred_state <= (luma4x4BlkIdx == 4'b1111)? `intra_chroma_pred_mode_s:`prev_intra4x4_pred_mode_flag_s; + `intra_chroma_pred_mode_s: + begin + mb_pred_state <= `rst_mb_pred; + slice_data_state <= (mb_type_general[3:2] != 2'b10)? `coded_block_pattern_s:`mb_qp_delta_s; + end + `mvd_l0_s: + if ({1'b0,mbPartIdx} == (NumMbPart - 1) && compIdx == 1'b1) + begin + mb_pred_state <= `rst_mb_pred; + slice_data_state <= `coded_block_pattern_s; + end + endcase + `coded_block_pattern_s:slice_data_state <= (CodedBlockPatternLuma == 0 && CodedBlockPatternChroma == 0)? `residual:`mb_qp_delta_s; + `mb_qp_delta_s: + slice_data_state <= (CodedBlockPatternLuma == 0 && CodedBlockPatternChroma == 0 && mb_type_general[3:2] != 2'b10)? `mb_num_update:`residual; + `residual:slice_data_state <= `mb_num_update; + `mb_num_update:slice_data_state <= `rst_slice_data; + endcase + //--------------- + //residual_state + //--------------- + always @ (posedge gclk_residual or negedge reset_n) + if (reset_n == 1'b0) + residual_state <= `rst_residual; + else + case (residual_state) + `rst_residual: + if (mb_type_general[3] == 1'b1 && mb_type_general != `MB_Intra4x4)//Intra16x16 + residual_state <= `Intra16x16DCLevel_s; + else + residual_state <= (CodedBlockPatternLuma == 0)? `LumaLevel_0_s:`LumaLevel_s; + `Intra16x16DCLevel_s:residual_state <= (CodedBlockPatternLuma == 0)? `Intra16x16ACLevel_0_s:`Intra16x16ACLevel_s; + `Intra16x16ACLevel_s,`Intra16x16ACLevel_0_s,`LumaLevel_s,`LumaLevel_0_s: + residual_state <= (CodedBlockPatternChroma == 0)? `ChromaACLevel_0_s:`ChromaDCLevel_Cb_s; + `ChromaDCLevel_Cb_s:residual_state <= `ChromaDCLevel_Cr_s; + `ChromaDCLevel_Cr_s:residual_state <= (CodedBlockPatternChroma == 2'b01)? `ChromaACLevel_0_s:`ChromaACLevel_Cb_s; + `ChromaACLevel_Cb_s:residual_state <= `ChromaACLevel_Cr_s; + `ChromaACLevel_Cr_s:residual_state <= `rst_residual; + `ChromaACLevel_0_s :residual_state <= `rst_residual; + endcase + //-------------------- + //cavlc_decoder_state + //-------------------- + always @ (posedge gclk_cavlc or negedge reset_n) + if (reset_n == 1'b0) + cavlc_decoder_state <= `rst_cavlc_decoder; + else + case (cavlc_decoder_state) + `rst_cavlc_decoder :cavlc_decoder_state <= `nAnB_decoding_s; + `nAnB_decoding_s :cavlc_decoder_state <= `nC_decoding_s; + `nC_decoding_s :cavlc_decoder_state <= `NumCoeffTrailingOnes_LUT; + `NumCoeffTrailingOnes_LUT://add trigger_CAVLC to trap a special case:after all-zero CrDC2x2 CAVLC decoding. + //Without adding trigger_CAVLC here,the gclk_cavlc can not catch trigger_CAVLC + //because it rises up too early (rise up at NumCoeffTrailingOnes_LUT instead of rst_cavlc_decoder) + cavlc_decoder_state <= (TotalCoeff == 0)? ((trigger_CAVLC)? `nAnB_decoding_s:`rst_cavlc_decoder):(TrailingOnes == 0)? `LevelPrefix:`TrailingOnesSignFlag; + `TrailingOnesSignFlag:cavlc_decoder_state <= (TotalCoeff == {3'b0,TrailingOnes})?`total_zeros_LUT:`LevelPrefix; + `LevelPrefix :cavlc_decoder_state <= `LevelSuffix; + `LevelSuffix :cavlc_decoder_state <= ({1'b0,i_level} == TotalCoeff-1)? ((TotalCoeff == maxNumCoeff)?`LevelRunCombination:`total_zeros_LUT):`LevelPrefix; + `total_zeros_LUT :cavlc_decoder_state <= (TotalCoeff == 1)? `RunOfZeros:`run_before_LUT; + `run_before_LUT :cavlc_decoder_state <= `RunOfZeros; + `RunOfZeros :cavlc_decoder_state <= ({1'b0,i_run} == (TotalCoeff - 1) || {1'b0,i_run} == (TotalCoeff - 2) || zerosLeft == 0)? `LevelRunCombination:`run_before_LUT; + `LevelRunCombination :cavlc_decoder_state <= (i_TotalCoeff == 0)? `rst_cavlc_decoder:`LevelRunCombination; + endcase + assign heading_one_en = ( + seq_parameter_set_state == `seq_parameter_set_id_sps_s || + seq_parameter_set_state == `log2_max_frame_num_minus4_s || + seq_parameter_set_state == `pic_order_cnt_type_s || + seq_parameter_set_state == `log2_max_pic_order_cnt_lsb_minus4_s || + seq_parameter_set_state == `num_ref_frames_s || + seq_parameter_set_state == `pic_width_in_mbs_minus1_s || + seq_parameter_set_state == `pic_height_in_map_units_minus1_s || + pic_parameter_set_state == `pic_parameter_set_id_pps_s || + pic_parameter_set_state == `seq_parameter_set_id_pps_s || + pic_parameter_set_state == `num_slice_groups_minus1_s || + pic_parameter_set_state == `num_ref_idx_l0_active_minus1_pps_s || + pic_parameter_set_state == `num_ref_idx_l1_active_minus1_pps_s || + pic_parameter_set_state == `pic_init_qp_minus26_s || + pic_parameter_set_state == `pic_init_qs_minus26_s || + pic_parameter_set_state == `chroma_qp_index_offset_s || + slice_header_state == `first_mb_in_slice_s || + slice_header_state == `slice_type_s || + slice_header_state == `pic_parameter_set_id_slice_header_s || + slice_header_state == `idr_pic_id_s || + slice_header_state == `num_ref_idx_l0_active_minus1_slice_header_s || + slice_header_state == `slice_qp_delta_s || + slice_header_state == `disable_deblocking_filter_idc_s || + slice_header_state == `slice_alpha_c0_offset_div2_s || + slice_header_state == `slice_beta_offset_div2_s || + slice_data_state == `mb_skip_run_s || + slice_data_state == `mb_type_s || + slice_data_state == `coded_block_pattern_s || + slice_data_state == `mb_qp_delta_s || + mb_pred_state == `intra_chroma_pred_mode_s || + mb_pred_state == `mvd_l0_s || + sub_mb_pred_state == `sub_mb_type_s || + sub_mb_pred_state == `sub_mvd_l0_s || + cavlc_decoder_state == `NumCoeffTrailingOnes_LUT || + cavlc_decoder_state == `LevelPrefix || + cavlc_decoder_state == `total_zeros_LUT)? 1'b0:1'b1; + + //count_mb_skip_run + always @ (posedge gclk_slice_data or negedge reset_n) + if (reset_n == 1'b0) + count_mb_skip_run <= 1'b0; + else if (slice_data_state == `skip_run_duration) + count_mb_skip_run <= (mb_num == 98)? 0:(count_mb_skip_run < (mb_skip_run - 1))? (count_mb_skip_run + 1):0; + + assign NextMB_IsSkip = (slice_data_state == `skip_run_duration && (count_mb_skip_run < (mb_skip_run - 1)))? 1'b1:1'b0; + + reg LowerMB_IsSkip; + always @ (slice_data_state or mb_skip_run or count_mb_skip_run) + if (slice_data_state == `skip_run_duration) + begin + if (mb_skip_run < 13) + LowerMB_IsSkip <= 1'b0; + else + LowerMB_IsSkip <= (count_mb_skip_run < (mb_skip_run - 12))? 1'b1:1'b0; + end + else + LowerMB_IsSkip <= 1'b0; + + //mb_num_h + always @ (posedge gclk_slice_data or negedge reset_n) + if (reset_n == 1'b0) + mb_num_h <= 0; + else if (slice_data_state == `skip_run_duration || slice_data_state == `mb_num_update) + mb_num_h <= (mb_num_h == 10) ? 0:(mb_num_h + 1); + + //mb_num_v + always @ (posedge gclk_slice_data or negedge reset_n) + if (reset_n == 1'b0) + mb_num_v <= 0; + else if ((slice_data_state == `skip_run_duration || slice_data_state == `mb_num_update) && mb_num_h == 10) + mb_num_v <= (mb_num_v == 8) ? 0:(mb_num_v + 1); + + //mb_num + always @ (posedge gclk_slice_data or negedge reset_n) + if (reset_n == 1'b0) + mb_num <= 0; + else if (slice_data_state == `skip_run_duration || slice_data_state == `mb_num_update) + mb_num <= (mb_num == 98)? 0:(mb_num + 1); + + //pic_num + always @ (posedge gclk_slice_data or negedge reset_n) + if (reset_n == 1'b0) + pic_num <= 0; + else if ((slice_data_state == `skip_run_duration || slice_data_state == `mb_num_update) && mb_num == 98) + pic_num <= pic_num + 1; + + //luma4x4BlkIdx + always @ (posedge gclk_slice_data or negedge reset_n) + if (reset_n == 1'b0) + luma4x4BlkIdx <= 0; + else + case (mb_pred_state) + `prev_intra4x4_pred_mode_flag_s: + if (prev_intra4x4_pred_mode_flag == 1'b1) + luma4x4BlkIdx <= (luma4x4BlkIdx == 4'b1111)? 0:(luma4x4BlkIdx + 1); + `rem_intra4x4_pred_mode_s:luma4x4BlkIdx <= (luma4x4BlkIdx == 4'b1111)? 0:(luma4x4BlkIdx + 1); + endcase + + //mbPartIdx + always @ (posedge gclk_slice_data or negedge reset_n) + if (reset_n == 1'b0) + mbPartIdx <= 0; + else if (mb_pred_state == `mvd_l0_s && compIdx == 1'b1) + mbPartIdx <= ({1'b0,mbPartIdx} < (NumMbPart-1))? (mbPartIdx + 1):0; + else if (sub_mb_pred_state == `sub_mb_type_s) + mbPartIdx <= (mbPartIdx == 2'b11)? 0:(mbPartIdx + 1); + else if (sub_mb_pred_state == `sub_mvd_l0_s && {1'b0,subMbPartIdx} == NumSubMbPart - 1 && compIdx == 1'b1) + mbPartIdx <= (mbPartIdx == 2'b11)? 0:(mbPartIdx + 1); + + //subMbPartIdx + always @ (posedge gclk_slice_data or negedge reset_n) + if (reset_n == 1'b0) + subMbPartIdx <= 0; + else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1'b1) + subMbPartIdx <= ({1'b0,subMbPartIdx} < NumSubMbPart-1)? (subMbPartIdx + 1):0; + + //compIdx + always @ (posedge gclk_slice_data or negedge reset_n) + if (reset_n == 1'b0) + compIdx <= 0; + else if (mb_pred_state == `mvd_l0_s || sub_mb_pred_state == `sub_mvd_l0_s) + compIdx <= ~ compIdx; + + //i8x8 + always @ (posedge clk) + if (reset_n == 1'b0) + i8x8 <= 0; + else if (slice_data_state == `residual && residual_state == `rst_residual && mb_type_general != `MB_Intra16x16_CBPChroma0 && mb_type_general != `MB_Intra16x16_CBPChroma1 && mb_type_general != `MB_Intra16x16_CBPChroma2) + i8x8 <= 0; + else if ((residual_state == `Intra16x16ACLevel_s || residual_state == `LumaLevel_s) && end_of_one_blk4x4_sum == 1 && i4x4 == 2'b11) + i8x8 <= (i8x8 == 2'b11)? 0:(i8x8 + 1); + + //i4x4 + always @ (posedge clk) + if (reset_n == 1'b0) + i4x4 <= 0; + else if ((residual_state == `Intra16x16ACLevel_s || residual_state == `LumaLevel_s) && end_of_one_blk4x4_sum == 1) + i4x4 <= (i4x4 == 2'b11)? 0:(i4x4 + 1); + + //i4x4_CbCr + always @ (posedge clk) + if (reset_n == 1'b0) + i4x4_CbCr <= 0; + else if ((residual_state == `ChromaACLevel_Cb_s || residual_state == `ChromaACLevel_Cr_s) && end_of_one_blk4x4_sum == 1'b1) + i4x4_CbCr <= (i4x4_CbCr == 2'b11)? 0:(i4x4_CbCr + 1); + + //suffix_length_initialized + always @ (posedge gclk_cavlc or negedge reset_n) + if (reset_n == 1'b0) + suffix_length_initialized <= 1'b0; + else if (cavlc_decoder_state == `rst_cavlc_decoder) + suffix_length_initialized <= 1'b0; + else if (cavlc_decoder_state == `LevelPrefix) + suffix_length_initialized <= 1'b1; + + //i_level + always @ (posedge gclk_cavlc or negedge reset_n) + if (reset_n == 1'b0) + i_level <= 0; + else if (cavlc_decoder_state == `NumCoeffTrailingOnes_LUT) + i_level <= 0; + else if (cavlc_decoder_state == `TrailingOnesSignFlag) + i_level <= i_level + TrailingOnes; + else if (cavlc_decoder_state == `LevelSuffix && {1'b0,i_level} != (TotalCoeff-1)) + i_level <= i_level + 1; + + //i_run + always @ (posedge gclk_cavlc or negedge reset_n) + if (reset_n == 1'b0) + i_run <= 0; + else if (cavlc_decoder_state == `total_zeros_LUT) + i_run <= 0; + else if (cavlc_decoder_state == `RunOfZeros && {1'b0,i_run} != (TotalCoeff - 1) && {1'b0,i_run} != (TotalCoeff - 2) && zerosLeft != 0) + i_run <= i_run + 1; + + //i_TotalCoeff + always @ (posedge gclk_cavlc or negedge reset_n) + if (reset_n == 1'b0) + i_TotalCoeff <= 0; + //enter from LevelSuffix + else if (cavlc_decoder_state == `LevelSuffix && {1'b0,i_level} == (TotalCoeff-1) && TotalCoeff == maxNumCoeff) + i_TotalCoeff <= TotalCoeff - 1; + //enter from RunOfZeros + else if (cavlc_decoder_state == `RunOfZeros && ({1'b0,i_run} == (TotalCoeff - 1) || {1'b0,i_run} == (TotalCoeff - 2) || zerosLeft == 0)) + i_TotalCoeff <= TotalCoeff - 1; + //Inside LevelRunCombination loop + else if (cavlc_decoder_state == `LevelRunCombination && i_TotalCoeff != 0) + i_TotalCoeff <= i_TotalCoeff-1; + + //coeffNum + always @ (cavlc_decoder_state or run or coeffNum_reg) + if (cavlc_decoder_state == `nAnB_decoding_s) + coeffNum <= 4'b1111; + else if (cavlc_decoder_state == `LevelRunCombination) + coeffNum <= coeffNum_reg + run + 1; + else + coeffNum <= coeffNum_reg; + + always @ (posedge gclk_cavlc or negedge reset_n) + if (reset_n == 1'b0) + coeffNum_reg <= 0; + else + coeffNum_reg <= coeffNum; + + //IsRunLoop + always @ (posedge gclk_cavlc or negedge reset_n) + if (reset_n == 1'b0) + IsRunLoop <= 0; + else if (cavlc_decoder_state == `RunOfZeros) + IsRunLoop <= ({1'b0,i_run} == TotalCoeff - 1 || {1'b0,i_run} == TotalCoeff - 2 || zerosLeft == 0)? 1'b0:1'b1; + +endmodule + + + + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/CodedBlockPattern_decoding.v b/demo_chip_rtl/rtl/nova/trunk/src/CodedBlockPattern_decoding.v new file mode 100644 index 0000000..d9e8846 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/CodedBlockPattern_decoding.v @@ -0,0 +1,157 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : CodedBlockPattern_decoding.v +// Generated : June 5,2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Decoding CodedBlockPatternLuma & CodedBlockPatternChroma (Table9-4 Page156 of H.264/AVC standard 2003) +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module CodedBlockPattern_decoding (clk,reset_n,slice_data_state,slice_type,mb_type,mb_type_general, + exp_golomb_decoding_output_5to0,CodedBlockPatternLuma,CodedBlockPatternChroma); + input clk,reset_n; + input [3:0] slice_data_state; + input [2:0] slice_type; + input [4:0] mb_type; + input [3:0] mb_type_general; + input [5:0] exp_golomb_decoding_output_5to0; + output [3:0] CodedBlockPatternLuma; + output [1:0] CodedBlockPatternChroma; + reg [3:0] CodedBlockPatternLuma; + reg [1:0] CodedBlockPatternChroma; + + reg [3:0] CodedBlockPatternLuma_reg; + reg [1:0] CodedBlockPatternChroma_reg; + + always @ (posedge clk) + CodedBlockPatternLuma_reg <= (reset_n == 0)? 0:CodedBlockPatternLuma; + always @ (posedge clk) + CodedBlockPatternChroma_reg <= (reset_n == 0)? 0:CodedBlockPatternChroma; + + always @ (slice_data_state or mb_type_general or slice_type or mb_type or exp_golomb_decoding_output_5to0 + or CodedBlockPatternLuma_reg) + if (mb_type_general[3:2] == 2'b10)//Intra16x16 + begin + if (slice_type == 0 || slice_type == 5) //P_slice + CodedBlockPatternLuma <= (mb_type < 18)? 4'd0:4'd15; + else //I_slice + CodedBlockPatternLuma <= (mb_type < 13)? 4'd0:4'd15; + end + else if (slice_data_state == `coded_block_pattern_s) + case (mb_type_general[3]) + 1'b0: //Inter + if (exp_golomb_decoding_output_5to0 < 2) //CBP = 0,16 + CodedBlockPatternLuma <= 0; + else if (exp_golomb_decoding_output_5to0 < 6) //CBP =1,2,4,8 + case (exp_golomb_decoding_output_5to0[2:0]) + 3'b010:CodedBlockPatternLuma <= 4'd1; + 3'b011:CodedBlockPatternLuma <= 4'd2; + 3'b100:CodedBlockPatternLuma <= 4'd4; + 3'b101:CodedBlockPatternLuma <= 4'd8; + default:CodedBlockPatternLuma <= CodedBlockPatternLuma_reg; + endcase + else + case (exp_golomb_decoding_output_5to0) + 6 :CodedBlockPatternLuma <= 4'd0; + 24,32 :CodedBlockPatternLuma <= 4'd1; + 25,33 :CodedBlockPatternLuma <= 4'd2; + 7,20,36 :CodedBlockPatternLuma <= 4'd3; + 26,34 :CodedBlockPatternLuma <= 4'd4; + 8,21,37 :CodedBlockPatternLuma <= 4'd5; + 17,44,46:CodedBlockPatternLuma <= 4'd6; + 13,28,40:CodedBlockPatternLuma <= 4'd7; + 27,35 :CodedBlockPatternLuma <= 4'd8; + 18,45,47:CodedBlockPatternLuma <= 4'd9; + 9,22,38 :CodedBlockPatternLuma <= 4'd10; + 14,29,41:CodedBlockPatternLuma <= 4'd11; + 10,23,39:CodedBlockPatternLuma <= 4'd12; + 15,30,42:CodedBlockPatternLuma <= 4'd13; + 16,31,43:CodedBlockPatternLuma <= 4'd14; + 11,12,19:CodedBlockPatternLuma <= 4'd15; + default :CodedBlockPatternLuma <= CodedBlockPatternLuma_reg; + endcase + 1'b1: //Intra4x4 + if (exp_golomb_decoding_output_5to0 < 3) //CBP = 47,31,15 + CodedBlockPatternLuma <= 4'd15; + else + case (exp_golomb_decoding_output_5to0) + 3,16,41 :CodedBlockPatternLuma <= 4'd0; + 29,33,42:CodedBlockPatternLuma <= 4'd1; + 30,34,43:CodedBlockPatternLuma <= 4'd2; + 17,21,25:CodedBlockPatternLuma <= 4'd3; + 31,35,44:CodedBlockPatternLuma <= 4'd4; + 18,22,26:CodedBlockPatternLuma <= 4'd5; + 37,39,46:CodedBlockPatternLuma <= 4'd6; + 4,8,12 :CodedBlockPatternLuma <= 4'd7; + 32,36,45:CodedBlockPatternLuma <= 4'd8; + 38,40,47:CodedBlockPatternLuma <= 4'd9; + 19,23,27:CodedBlockPatternLuma <= 4'd10; + 5,9,13 :CodedBlockPatternLuma <= 4'd11; + 20,24,28:CodedBlockPatternLuma <= 4'd12; + 6,10,14 :CodedBlockPatternLuma <= 4'd13; + 7,11,15 :CodedBlockPatternLuma <= 4'd14; + default :CodedBlockPatternLuma <= CodedBlockPatternLuma_reg; + endcase + endcase + else + CodedBlockPatternLuma <= CodedBlockPatternLuma_reg; + + + always @ (slice_data_state or mb_type_general or exp_golomb_decoding_output_5to0 or CodedBlockPatternChroma_reg) + if (mb_type_general[3:2] == 2'b10)//Intra16x16 + CodedBlockPatternChroma <= mb_type_general[1:0]; + else if (slice_data_state == `coded_block_pattern_s) + case (mb_type_general[3]) + 1'b0: //Inter + if (exp_golomb_decoding_output_5to0 < 2) //CBP = 0,16 + CodedBlockPatternChroma <= {1'b0,exp_golomb_decoding_output_5to0[0]}; + else if (exp_golomb_decoding_output_5to0 < 6) //CBP =1,2,4,8 + CodedBlockPatternChroma <= 2'd0; + else + case (exp_golomb_decoding_output_5to0) + 7,8,9,10,11,13,14,15,16,17,18 :CodedBlockPatternChroma <= 2'd0; + 19,32,33,34,35,36,37,38,39,40,41,42,43,44,45:CodedBlockPatternChroma <= 2'd1; + default :CodedBlockPatternChroma <= 2'd2; + endcase + 1'b1: //Intra4x4 + if (exp_golomb_decoding_output_5to0 < 3) //CBP = 47,31,15 + case (exp_golomb_decoding_output_5to0[1:0]) + 2'b00 :CodedBlockPatternChroma <= 2'd2; + 2'b01 :CodedBlockPatternChroma <= 2'd1; + default:CodedBlockPatternChroma <= 2'd0; + endcase + else + case (exp_golomb_decoding_output_5to0) + 3,8,9,10,11,17,18,19,20,29,30,31,32,37,38:CodedBlockPatternChroma <= 2'd0; + 4,5,6,7,16,21,22,23,24,33,34,35,36,39,40 :CodedBlockPatternChroma <= 2'd1; + default :CodedBlockPatternChroma <= 2'd2; + endcase + endcase + else + CodedBlockPatternChroma <= CodedBlockPatternChroma_reg; + +endmodule + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/DF_mem_ctrl.v b/demo_chip_rtl/rtl/nova/trunk/src/DF_mem_ctrl.v new file mode 100644 index 0000000..67ad62f --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/DF_mem_ctrl.v @@ -0,0 +1,740 @@ +//----------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : DF_mem_ctrl.v +// Generated : Nov 27,2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// controller for DF_mbAddrA_RAM & DF_mbAddrB_RAM & dis_frame_RAM +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module DF_mem_ctrl (clk,reset_n,gclk_end_of_MB_DEC,disable_DF,mb_num_h,mb_num_v, + bs_curr_MR,bs_curr_MW,blk4x4_sum_counter,blk4x4_rec_counter_2_raster_order, + DF_edge_counter_MR,DF_edge_counter_MW,one_edge_counter_MR,one_edge_counter_MW, + blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out, + p3_MW,p2_MW,p1_MW,p0_MW,q3_MW,q2_MW,q1_MW,q0_MW, + buf0_0,buf0_1,buf0_2,buf0_3, + buf2_0,buf2_1,buf2_2,buf2_3,buf3_0,buf3_1,buf3_2,buf3_3, + t0_0,t0_1,t0_2,t0_3,t1_0,t1_1,t1_2,t1_3,t2_0,t2_1,t2_2,t2_3, + + mb_num_h_DF,mb_num_v_DF,end_of_MB_DF,end_of_lastMB_DF, + DF_mbAddrA_RF_rd,DF_mbAddrA_RF_wr,DF_mbAddrA_RF_rd_addr,DF_mbAddrA_RF_wr_addr,DF_mbAddrA_RF_din, + DF_mbAddrB_RAM_rd,DF_mbAddrB_RAM_wr,DF_mbAddrB_RAM_addr,DF_mbAddrB_RAM_din, + dis_frame_RAM_wr,dis_frame_RAM_wr_addr,dis_frame_RAM_din); + input clk,reset_n; + input disable_DF; + input gclk_end_of_MB_DEC; + input [3:0] mb_num_h; + input [3:0] mb_num_v; + input [2:0] bs_curr_MR,bs_curr_MW; + input [2:0] blk4x4_sum_counter; + input [4:0] blk4x4_rec_counter_2_raster_order; + input [5:0] DF_edge_counter_MR,DF_edge_counter_MW; + input [1:0] one_edge_counter_MR,one_edge_counter_MW; + input [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out; + input [7:0] p3_MW,p2_MW,p1_MW,p0_MW; + input [7:0] q3_MW,q2_MW,q1_MW,q0_MW; + input [31:0] buf0_0,buf0_1,buf0_2,buf0_3; + input [31:0] buf2_0,buf2_1,buf2_2,buf2_3; + input [31:0] buf3_0,buf3_1,buf3_2,buf3_3; + input [31:0] t0_0,t0_1,t0_2,t0_3; + input [31:0] t1_0,t1_1,t1_2,t1_3; + input [31:0] t2_0,t2_1,t2_2,t2_3; + + output [3:0] mb_num_h_DF; + output [3:0] mb_num_v_DF; + output end_of_MB_DF; + output end_of_lastMB_DF; + output DF_mbAddrA_RF_rd; + output DF_mbAddrA_RF_wr; + output [4:0] DF_mbAddrA_RF_rd_addr; + output [4:0] DF_mbAddrA_RF_wr_addr; + output [31:0] DF_mbAddrA_RF_din; + + output DF_mbAddrB_RAM_rd; + output DF_mbAddrB_RAM_wr; + output [8:0] DF_mbAddrB_RAM_addr; + output [31:0] DF_mbAddrB_RAM_din; + + output dis_frame_RAM_wr; + output [13:0] dis_frame_RAM_wr_addr; + output [31:0] dis_frame_RAM_din; + + wire Is_mbAddrA_wr; + wire Is_mbAddrA_real_wr; + wire Is_mbAddrA_virtual_wr; + wire Is_mbAddrB_wr; + wire Is_currMB_wr; + wire Is_12cycles_wr; + wire dis_frame_RAM_wr_tmp; + + reg [3:0] mb_num_h_DF; + reg [3:0] mb_num_v_DF; + always @ (posedge gclk_end_of_MB_DEC or negedge reset_n) + if (reset_n == 1'b0) + begin mb_num_h_DF <= 0; mb_num_v_DF <= 0; end + else if (!disable_DF) + begin mb_num_h_DF <= mb_num_h; mb_num_v_DF <= mb_num_v; end + + + reg [3:0] DF_12_cycles; + always @ (posedge clk) + if (reset_n == 1'b0) + DF_12_cycles <= 4'd12; + else if (!disable_DF && DF_edge_counter_MW == 6'd47 && one_edge_counter_MW == 2'd3) + DF_12_cycles <= 0; + else if (DF_12_cycles != 4'd12) + DF_12_cycles <= DF_12_cycles + 1; + + reg end_of_MB_DF; + reg end_of_lastMB_DF;//end of MB_DF of 98th MB of one frame.Does not need to rise MB_rec_DF_align since there is only + //DF and no reconstruction.So dispart end_of_lastMB_DF from end_of_MB_DF + + always @ (posedge clk) + if (reset_n == 1'b0) + begin + end_of_MB_DF <= 1'b0; + end_of_lastMB_DF <= 1'b0; + end + else if (DF_12_cycles == 4'd11) + begin + end_of_MB_DF <= (!(mb_num_h_DF == 10 && mb_num_v_DF == 8))? 1'b1:1'b0; + end_of_lastMB_DF <= (mb_num_h_DF == 10 && mb_num_v_DF == 8)? 1'b1:1'b0; + end + else + begin + end_of_MB_DF <= 1'b0; + end_of_lastMB_DF <= 1'b0; + end + + wire [1:0] write_0to3_cycle; + assign write_0to3_cycle = (DF_12_cycles == 4'd12)? one_edge_counter_MW:DF_12_cycles[1:0]; + //------------------------------------------------------------------- + //DF_mbAddrA_RF control + //------------------------------------------------------------------- + + //For edge 18,34,42,it will update mbAddrB of left MB.So no matter bs_curr_MR is equal to 0 or not, + //mbAddrA should be read out for writing to mbAddrB of left MB.Otherwise,the value written to left + //mbAddrB will be a wrong value. + assign DF_mbAddrA_RF_rd = (mb_num_h_DF != 0 && ((( + DF_edge_counter_MR == 6'd0 || DF_edge_counter_MR == 6'd2 || DF_edge_counter_MR == 6'd16 || + DF_edge_counter_MR == 6'd32 || DF_edge_counter_MR == 6'd40) && bs_curr_MR != 0) || ( + DF_edge_counter_MR == 6'd18 || DF_edge_counter_MR == 6'd34 || DF_edge_counter_MR == 6'd42))); + + assign DF_mbAddrA_RF_wr = (DF_edge_counter_MW == 6'd16 || DF_edge_counter_MW == 6'd30 || + DF_edge_counter_MW == 6'd32 || DF_edge_counter_MW == 6'd33 || DF_edge_counter_MW == 6'd40 || + DF_edge_counter_MW == 6'd41 || DF_12_cycles[3:2] == 2'b01 || DF_12_cycles[3:2] == 2'b10); + //DF_mbAddrA_RF_rd_addr + reg [2:0] DF_mbAddrA_RF_rd_addr_blk4x4; + always @ (DF_mbAddrA_RF_rd or DF_edge_counter_MR) + if (DF_mbAddrA_RF_rd) + case (DF_edge_counter_MR) + 6'd0 :DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd0; //mbAddrA0 + 6'd2 :DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd1; //mbAddrA1 + 6'd16:DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd2; //mbAddrA2 + 6'd18:DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd3; //mbAddrA3 + 6'd32:DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd4; //mbAddrA4 + 6'd34:DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd5; //mbAddrA5 + 6'd40:DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd6; //mbAddrA6 + 6'd42:DF_mbAddrA_RF_rd_addr_blk4x4 <= 3'd7; //mbAddrA7 + default:DF_mbAddrA_RF_rd_addr_blk4x4 <= 0; + endcase + else + DF_mbAddrA_RF_rd_addr_blk4x4 <= 0; + assign DF_mbAddrA_RF_rd_addr = {5{DF_mbAddrA_RF_rd}} & + ({DF_mbAddrA_RF_rd_addr_blk4x4,2'b0} + one_edge_counter_MR); + //DF_mbAddrA_RF_wr_addr + reg [2:0] DF_mbAddrA_RF_wr_addr_blk4x4; + always @ (DF_mbAddrA_RF_wr or DF_edge_counter_MW or DF_12_cycles[3:2]) + if (DF_mbAddrA_RF_wr) + begin + if (DF_edge_counter_MW != 6'd48) + case (DF_edge_counter_MW) + 6'd16:DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd0; //mbAddrA0 + 6'd30:DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd1; //mbAddrA1 + 6'd32:DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd2; //mbAddrA2 + 6'd33:DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd3; //mbAddrA3 + 6'd40:DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd4; //mbAddrA4 + 6'd41:DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd5; //mbAddrA5 + default:DF_mbAddrA_RF_wr_addr_blk4x4 <= 0; + endcase + else if (DF_12_cycles[3:2] == 2'b01) + DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd6; + else + DF_mbAddrA_RF_wr_addr_blk4x4 <= 3'd7; + end + else + DF_mbAddrA_RF_wr_addr_blk4x4 <= 0; + + assign DF_mbAddrA_RF_wr_addr = {5{DF_mbAddrA_RF_wr}} & + ({DF_mbAddrA_RF_wr_addr_blk4x4,2'b0} + write_0to3_cycle); + + //DF_mbAddrA_RF_din + wire Is_mbAddrA_t1; + assign Is_mbAddrA_t1 = (DF_edge_counter_MW == 6'd30 || DF_edge_counter_MW == 6'd33 || + DF_edge_counter_MW == 6'd41 || DF_12_cycles[3:2] == 2'b10); + + reg [31:0] DF_mbAddrA_RF_din; + always @ (DF_mbAddrA_RF_wr or Is_mbAddrA_t1 or write_0to3_cycle or + t0_0 or t0_1 or t0_2 or t0_3 or t1_0 or t1_1 or t1_2 or t1_3) + if (DF_mbAddrA_RF_wr) + begin + if (Is_mbAddrA_t1) + case (write_0to3_cycle) + 2'd0:DF_mbAddrA_RF_din <= t1_0; + 2'd1:DF_mbAddrA_RF_din <= t1_1; + 2'd2:DF_mbAddrA_RF_din <= t1_2; + 2'd3:DF_mbAddrA_RF_din <= t1_3; + endcase + else + case (write_0to3_cycle) + 2'd0:DF_mbAddrA_RF_din <= t0_0; + 2'd1:DF_mbAddrA_RF_din <= t0_1; + 2'd2:DF_mbAddrA_RF_din <= t0_2; + 2'd3:DF_mbAddrA_RF_din <= t0_3; + endcase + end + else + DF_mbAddrA_RF_din <= 0; + //------------------------------------------------------------------- + //DF_mbAddrB_RAM control + //------------------------------------------------------------------- + assign DF_mbAddrB_RAM_rd = ((( + DF_edge_counter_MR == 6'd4 || DF_edge_counter_MR == 6'd8 || DF_edge_counter_MR == 6'd12 || + DF_edge_counter_MR == 6'd13 || DF_edge_counter_MR == 6'd36 || DF_edge_counter_MR == 6'd37 || + DF_edge_counter_MR == 6'd44 || DF_edge_counter_MR == 6'd45) && mb_num_v_DF != 0) || + DF_edge_counter_MR == 6'd20 || DF_edge_counter_MR == 6'd24 || DF_edge_counter_MR == 6'd28 || + DF_edge_counter_MR == 6'd29); + + wire DF_mbAddrB_RAM_wr_curr; + assign DF_mbAddrB_RAM_wr_curr = ((( + DF_edge_counter_MW == 6'd21 || DF_edge_counter_MW == 6'd25 || DF_edge_counter_MW == 6'd30 || + DF_edge_counter_MW == 6'd31 || DF_edge_counter_MW == 6'd38 || DF_edge_counter_MW == 6'd39 || + DF_edge_counter_MW == 6'd46 || DF_edge_counter_MW == 6'd47) && mb_num_v_DF != 4'd8) || + DF_edge_counter_MW == 6'd5 || DF_edge_counter_MW == 6'd9 || DF_edge_counter_MW == 6'd14 || + DF_edge_counter_MW == 6'd15); + + wire DF_mbAddrB_RAM_wr_leftMB; + assign DF_mbAddrB_RAM_wr_leftMB = (mb_num_h_DF != 0 && mb_num_v_DF != 4'd8 && ( + DF_edge_counter_MW == 6'd20 || DF_edge_counter_MW == 6'd37 || DF_edge_counter_MW == 6'd45)); + + assign DF_mbAddrB_RAM_wr = DF_mbAddrB_RAM_wr_curr | DF_mbAddrB_RAM_wr_leftMB; + + reg [2:0] DF_mbAddrB_RAM_addr_blk4x4; + always @ (DF_mbAddrB_RAM_rd or DF_edge_counter_MR or DF_mbAddrB_RAM_wr_curr + or DF_mbAddrB_RAM_wr_leftMB or DF_edge_counter_MW) + if (DF_mbAddrB_RAM_rd) + case (DF_edge_counter_MR) + 6'd4, 6'd20:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd0; + 6'd8, 6'd24:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd1; + 6'd12,6'd28:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd2; + 6'd13,6'd29:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd3; + 6'd36 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd4; + 6'd37 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd5; + 6'd44 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd6; + 6'd45 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd7; + default :DF_mbAddrB_RAM_addr_blk4x4 <= 0; + endcase + else if (DF_mbAddrB_RAM_wr_curr) + case (DF_edge_counter_MW) + 6'd5, 6'd21:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd0; + 6'd9, 6'd25:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd1; + 6'd14,6'd30:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd2; + 6'd15,6'd31:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd3; + 6'd38 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd4; + 6'd39 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd5; + 6'd46 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd6; + 6'd47 :DF_mbAddrB_RAM_addr_blk4x4 <= 3'd7; + default :DF_mbAddrB_RAM_addr_blk4x4 <= 0; + endcase + else if (DF_mbAddrB_RAM_wr_leftMB) + case (DF_edge_counter_MW) + 6'd20:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd3; + 6'd37:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd5; + default:DF_mbAddrB_RAM_addr_blk4x4 <= 3'd7; + endcase + else + DF_mbAddrB_RAM_addr_blk4x4 <= 0; + + reg [1:0] DF_mbAddrB_RAM_addr_offset; + always @ (DF_mbAddrB_RAM_rd or one_edge_counter_MR or DF_mbAddrB_RAM_wr or one_edge_counter_MW) + if (DF_mbAddrB_RAM_rd) DF_mbAddrB_RAM_addr_offset <= one_edge_counter_MR; + else if (DF_mbAddrB_RAM_wr) DF_mbAddrB_RAM_addr_offset <= one_edge_counter_MW; + else DF_mbAddrB_RAM_addr_offset <= 0; + + wire [3:0] mb_num_h_DF_m1; + assign mb_num_h_DF_m1 = {4{Is_mbAddrA_wr | DF_mbAddrB_RAM_wr_leftMB}} & (mb_num_h_DF - 1); + + wire [8:0] mb_num_h_DF_x32; + assign mb_num_h_DF_x32 = (DF_mbAddrB_RAM_wr_leftMB)? {mb_num_h_DF_m1,5'b0}:{mb_num_h_DF,5'b0}; + assign DF_mbAddrB_RAM_addr = mb_num_h_DF_x32 + {DF_mbAddrB_RAM_addr_blk4x4,2'b0} + DF_mbAddrB_RAM_addr_offset; + + reg [31:0] DF_mbAddrB_RAM_din; + always @ (DF_mbAddrB_RAM_wr_curr or DF_mbAddrB_RAM_wr_leftMB or one_edge_counter_MW + or q0_MW or q1_MW or q2_MW or q3_MW or t2_0 or t2_1 or t2_2 or t2_3) + if (DF_mbAddrB_RAM_wr_curr) + DF_mbAddrB_RAM_din <= {q3_MW,q2_MW,q1_MW,q0_MW}; + else if (DF_mbAddrB_RAM_wr_leftMB) + case (one_edge_counter_MW) + 2'd0:DF_mbAddrB_RAM_din <= t2_0; + 2'd1:DF_mbAddrB_RAM_din <= t2_1; + 2'd2:DF_mbAddrB_RAM_din <= t2_2; + 2'd3:DF_mbAddrB_RAM_din <= t2_3; + endcase + else + DF_mbAddrB_RAM_din <= 0; + //------------------------------------------------------------------- + //dis_frame_RAM write control + //------------------------------------------------------------------- + //dis_frame_RAM_wr + assign Is_mbAddrA_wr = (mb_num_h_DF != 0 && ( + DF_edge_counter_MW == 6'd0 || DF_edge_counter_MW == 6'd2 || DF_edge_counter_MW == 6'd16 || + DF_edge_counter_MW == 6'd18 || DF_edge_counter_MW == 6'd32 || DF_edge_counter_MW == 6'd34 || + DF_edge_counter_MW == 6'd40 || DF_edge_counter_MW == 6'd42)); + assign Is_mbAddrA_real_wr = (Is_mbAddrA_wr && bs_curr_MW != 0); + assign Is_mbAddrA_virtual_wr = (Is_mbAddrA_wr && bs_curr_MW == 0); + + assign Is_mbAddrB_wr = (mb_num_v_DF != 0 && ( + DF_edge_counter_MW == 6'd5 || DF_edge_counter_MW == 6'd9 || DF_edge_counter_MW == 6'd13 || + DF_edge_counter_MW == 6'd14 || DF_edge_counter_MW == 6'd37 || DF_edge_counter_MW == 6'd38 || + DF_edge_counter_MW == 6'd45 || DF_edge_counter_MW == 6'd46)); + assign Is_currMB_wr = (( + DF_edge_counter_MW == 6'd6 || DF_edge_counter_MW == 6'd10 || DF_edge_counter_MW == 6'd15 || + DF_edge_counter_MW == 6'd17 || DF_edge_counter_MW == 6'd21 || DF_edge_counter_MW == 6'd22 || + DF_edge_counter_MW == 6'd23 || DF_edge_counter_MW == 6'd25 || DF_edge_counter_MW == 6'd26 || + DF_edge_counter_MW == 6'd27 || DF_edge_counter_MW == 6'd29 || DF_edge_counter_MW == 6'd30 || + DF_edge_counter_MW == 6'd31 || DF_edge_counter_MW == 6'd33 || DF_edge_counter_MW == 6'd35 || + DF_edge_counter_MW == 6'd36 || DF_edge_counter_MW == 6'd39 || DF_edge_counter_MW == 6'd41 || + DF_edge_counter_MW == 6'd43 || DF_edge_counter_MW == 6'd44 || DF_edge_counter_MW == 6'd47) && + one_edge_counter_MW != 3'd4); + assign Is_12cycles_wr = (DF_12_cycles != 4'd12); + + assign dis_frame_RAM_wr_tmp = + ( disable_DF && blk4x4_sum_counter[2] != 1'b1) || + (!disable_DF && (Is_mbAddrA_wr || Is_mbAddrB_wr || Is_currMB_wr || Is_12cycles_wr)); + assign dis_frame_RAM_wr = (dis_frame_RAM_wr_tmp & (~Is_mbAddrA_virtual_wr)); + + wire Is_luma_wr; + wire Is_chroma_wr; + wire Is_1st_cycle_wr; //if it is the position of first line of a 4x4 block,for both DF disable & enable + wire Is_MB_LeftTop_wr; //if it is the position of most left-top for a whole MB,only for DF is disabled + assign Is_luma_wr = (dis_frame_RAM_wr_tmp && ( + (disable_DF && blk4x4_rec_counter_2_raster_order[4] == 1'b0) || + (!disable_DF && (((Is_mbAddrA_wr || Is_mbAddrB_wr) && !DF_edge_counter_MW[5]) || + (Is_currMB_wr && DF_edge_counter_MW < 6'd39)))))? 1'b1:1'b0; + + assign Is_chroma_wr = (dis_frame_RAM_wr_tmp && !Is_luma_wr)? 1'b1:1'b0; + + assign Is_1st_cycle_wr = ( + ( disable_DF && blk4x4_sum_counter == 0) || + (!disable_DF && (one_edge_counter_MW == 0 && (Is_mbAddrA_wr || Is_mbAddrB_wr || Is_currMB_wr)) || + (DF_12_cycles[1:0] == 2'b00 && DF_12_cycles[3:2] != 2'b11)))? 1'b1:1'b0; + + assign Is_MB_LeftTop_wr = (disable_DF && blk4x4_sum_counter == 0 && ( + (blk4x4_rec_counter_2_raster_order[4] == 1'b0 && blk4x4_rec_counter_2_raster_order[3:0] == 4'b0) || + (blk4x4_rec_counter_2_raster_order[4] == 1'b1 && blk4x4_rec_counter_2_raster_order[1:0] == 2'b0))) ? 1'b1:1'b0; + + //--------------------------------------------------------------------------------- + // dis_frame_RAM_wr_addr_base + // Only updated at first write cycle(during 2,3,4 write cycle,it remains unchanged) + // Luma:0 Cb:6336 Cr:7920 + //--------------------------------------------------------------------------------- + reg [12:0] dis_frame_RAM_wr_addr_base; + always @ (disable_DF or Is_MB_LeftTop_wr or Is_1st_cycle_wr or Is_luma_wr or Is_12cycles_wr + or blk4x4_rec_counter_2_raster_order[2] or DF_edge_counter_MW) + if (disable_DF) + begin + if (Is_MB_LeftTop_wr) + begin + if (Is_luma_wr) //luma + dis_frame_RAM_wr_addr_base <= 13'd0; + else if (blk4x4_rec_counter_2_raster_order[2] == 1'b0) //Cb + dis_frame_RAM_wr_addr_base <= 13'd6336; + else //Cr + dis_frame_RAM_wr_addr_base <= 13'd7920; + end + else + dis_frame_RAM_wr_addr_base <= 13'd0; + end + else + begin + if (Is_1st_cycle_wr) //update only @ 1st write cycle + begin + if (Is_luma_wr) //luma + dis_frame_RAM_wr_addr_base <= 13'd0; + else if (DF_edge_counter_MW < 6'd45 && DF_edge_counter_MW != 40 && DF_edge_counter_MW != 42) //Cb + dis_frame_RAM_wr_addr_base <= 13'd6336; + else //Cr + dis_frame_RAM_wr_addr_base <= 13'd7920; + end + else + dis_frame_RAM_wr_addr_base <= 0; + end + //--------------------------------------------------------------------------------- + // dis_frame_RAM_wr_addr_x + // Only updated at first write cycle(during 2,3,4 write cycle,it remains unchanged) + // x position inside a frame,since every 4 horizontal pixels have been combined as + // a single 32bit word,thus 0 ~ 43 for luma and 0 ~ 21 for chroma + //--------------------------------------------------------------------------------- + wire [3:0] mb_num_v_DF_m1; + assign mb_num_v_DF_m1 = {4{Is_mbAddrB_wr}} & (mb_num_v_DF - 1); + + reg [1:0] blk4x4_xoffset; //0 ~ 3,xoffset for blk4x4 inside a MB + always @ (Is_luma_wr or Is_mbAddrA_wr or Is_mbAddrB_wr or Is_currMB_wr or DF_12_cycles or DF_edge_counter_MW) + case ({Is_mbAddrA_wr,Is_mbAddrB_wr,Is_currMB_wr}) + 3'b100: //Is_mbAddrA_wr + if (Is_luma_wr) blk4x4_xoffset <= 2'd3; + else blk4x4_xoffset <= 2'd1; + 3'b010: //Is_mbAddrB_wr + case (DF_edge_counter_MW) + 6'd5,6'd37,6'd45:blk4x4_xoffset <= 2'd0; + 6'd9,6'd38,6'd46:blk4x4_xoffset <= 2'd1; + 6'd13 :blk4x4_xoffset <= 2'd2; + 6'd14 :blk4x4_xoffset <= 2'd3; + default :blk4x4_xoffset <= 0; + endcase + 3'b001: //Is_currMB_wr + case (DF_edge_counter_MW) + //6'd6,6'd21,6'd23,6'd22,6'd39,6'd41,6'd47:blk4x4_xoffset <= 0; + 6'd10,6'd25,6'd27,6'd26,6'd43,6'd44 :blk4x4_xoffset <= 2'd1; + 6'd15,6'd29,6'd31,6'd33 :blk4x4_xoffset <= 2'd2; + 6'd17,6'd30,6'd35,6'd36 :blk4x4_xoffset <= 2'd3; + default :blk4x4_xoffset <= 0; + endcase + default: + if (DF_12_cycles != 4'd12) + case (DF_12_cycles[3:2]) + 2'b00 :blk4x4_xoffset <= 0; //buf2 -> blk22 + 2'b01,2'b10 :blk4x4_xoffset <= 2'd1; //T0 -> blk21,T1 -> blk23 + default :blk4x4_xoffset <= 0; + endcase + else + blk4x4_xoffset <= 0; + endcase + + reg [5:0] dis_frame_RAM_wr_addr_x; + + always @ (disable_DF or Is_MB_LeftTop_wr or Is_1st_cycle_wr or Is_luma_wr or Is_mbAddrA_wr + or Is_mbAddrB_wr or Is_currMB_wr or blk4x4_rec_counter_2_raster_order[1:0] + or mb_num_h or mb_num_h_DF_m1 or mb_num_h_DF or blk4x4_xoffset) + if (disable_DF) + begin + if (Is_MB_LeftTop_wr) + dis_frame_RAM_wr_addr_x <= (Is_luma_wr)? ({mb_num_h,2'b0} + blk4x4_rec_counter_2_raster_order[1:0]):({1'b0,mb_num_h,1'b0} + blk4x4_rec_counter_2_raster_order[0]); + else + dis_frame_RAM_wr_addr_x <= 0; + end + else + begin + if (Is_1st_cycle_wr) + case ({Is_mbAddrA_wr,Is_mbAddrB_wr,Is_currMB_wr}) + 3'b100: //Is_mbAddrA_wr + dis_frame_RAM_wr_addr_x <= (Is_luma_wr)? ({mb_num_h_DF_m1,2'b0} + blk4x4_xoffset):({1'b0,mb_num_h_DF_m1,1'b0} + blk4x4_xoffset); + 3'b010,3'b001: //Is_mbAddrB_wr,Is_currMB_wr + dis_frame_RAM_wr_addr_x <= (Is_luma_wr)? ({mb_num_h_DF,2'b0} + blk4x4_xoffset):({1'b0,mb_num_h_DF,1'b0} + blk4x4_xoffset); + + default: //for DF_12_cycles != 4'd12 + dis_frame_RAM_wr_addr_x <= {1'b0,mb_num_h_DF,1'b0} + blk4x4_xoffset; + endcase + else + dis_frame_RAM_wr_addr_x <= 0; + end + //--------------------------------------------------------------------------------- + // dis_frame_RAM_wr_addr_y + // a)Only updated at first write cycle(during 2,3,4 write cycle,it remains unchanged) + // b)For 2,3,4 write cycles,dis_frame_RAM_wr_addr is directly +44/+22 instead of + // changing dis_frame_RAM_wr_addr_y + // c)y addr increase 1 means +44 for luma or +22 for choma + //--------------------------------------------------------------------------------- + reg [1:0] blk4x4_yoffset; //0 ~ 3,yoffset for blk4x4 inside a MB + always @ (Is_mbAddrA_wr or Is_currMB_wr or DF_12_cycles or DF_edge_counter_MW) + if (Is_mbAddrA_wr) + case (DF_edge_counter_MW) + 6'd0,6'd32,6'd40:blk4x4_yoffset <= 2'd0; + 6'd2,6'd34,6'd42:blk4x4_yoffset <= 2'd1; + 6'd16 :blk4x4_yoffset <= 2'd2; + 6'd18 :blk4x4_yoffset <= 2'd3; + default :blk4x4_yoffset <= 0; + endcase + else if (Is_currMB_wr) + case (DF_edge_counter_MW) + //6'd6,6'd10,6'd15,6'd17,6'd39,6'd43,6'd47:blk4x4_yoffset <= 0; + 6'd21,6'd25,6'd29,6'd30,6'd41,6'd44 :blk4x4_yoffset <= 2'd1; + 6'd23,6'd27,6'd31,6'd35 :blk4x4_yoffset <= 2'd2; + 6'd22,6'd26,6'd33,6'd36 :blk4x4_yoffset <= 2'd3; + default :blk4x4_yoffset <= 0; + endcase + else if (DF_12_cycles != 4'd12) + case (DF_12_cycles[2]) + 1'b0:blk4x4_yoffset <= 2'd1; // 0 ~ 3:buf2->22; 8 ~ 11:T1->23 + 1'b1:blk4x4_yoffset <= 0; // 4 ~ 7:T0->21 + endcase + else + blk4x4_yoffset <= 0; + + reg [7:0] dis_frame_RAM_wr_addr_y; //y position inside a frame,0 ~ 143 for luma & 0 ~ 71 for chroma + always @ (disable_DF or Is_MB_LeftTop_wr or Is_1st_cycle_wr or Is_luma_wr + or Is_mbAddrA_wr or Is_mbAddrB_wr or Is_mbAddrB_wr or Is_currMB_wr + or blk4x4_sum_counter[1:0] or blk4x4_rec_counter_2_raster_order[4:1] + or mb_num_v or mb_num_v_DF or mb_num_v_DF_m1 + or one_edge_counter_MW or blk4x4_yoffset or DF_12_cycles) + if (disable_DF) + begin + if (Is_MB_LeftTop_wr) + dis_frame_RAM_wr_addr_y <= (Is_luma_wr)? + ({mb_num_v,4'b0} + {blk4x4_rec_counter_2_raster_order[3:2],2'b00} + blk4x4_sum_counter[1:0]): + ({1'b0,mb_num_v,3'b0} + {blk4x4_rec_counter_2_raster_order[1], 2'b00} + blk4x4_sum_counter[1:0]); + else + dis_frame_RAM_wr_addr_y <= 0; + end + else + begin + if (Is_1st_cycle_wr) + case ({Is_mbAddrA_wr,Is_mbAddrB_wr,Is_currMB_wr}) + 3'b100: //Is_mbAddrA_wr + dis_frame_RAM_wr_addr_y <= (Is_luma_wr)? //luma or chroma + (({mb_num_v_DF,4'b0} + {2'b00,blk4x4_yoffset,2'b00}) + one_edge_counter_MW): + (({1'b0,mb_num_v_DF,3'b0} + {2'b00,blk4x4_yoffset,2'b00}) + one_edge_counter_MW); + 3'b010: //Is_mbAddrB_wr + dis_frame_RAM_wr_addr_y <= (Is_luma_wr)? //luma or chroma + (({mb_num_v_DF_m1,4'b0} + 4'd12) + one_edge_counter_MW): + (({1'b0,mb_num_v_DF_m1,3'b0} + 4'd4 ) + one_edge_counter_MW); + 3'b001: //Is_currMB_wr + dis_frame_RAM_wr_addr_y <= (Is_luma_wr)? //luma or chroma + (({mb_num_v_DF,4'b0} + {blk4x4_yoffset,2'b0}) + one_edge_counter_MW): + (({1'b0,mb_num_v_DF,3'b0} + {blk4x4_yoffset,2'b0}) + one_edge_counter_MW); + default: + if (DF_12_cycles != 4'd12) + dis_frame_RAM_wr_addr_y <= {mb_num_v_DF,3'b0} + {blk4x4_yoffset,2'b0} + DF_12_cycles[1:0]; + else + dis_frame_RAM_wr_addr_y <= 0; + endcase + else + dis_frame_RAM_wr_addr_y <= 0; + end + + + wire [12:0] dis_frame_RAM_wr_addr_y_ext; //every "y" increase will increase 44(luma) or 22(chroma) for + //dis_frame_RAM address + + assign dis_frame_RAM_wr_addr_y_ext = (Is_luma_wr)? + //luma, x44 = x32 + x8 + x4 + ( {dis_frame_RAM_wr_addr_y,5'b0} + {2'b0,dis_frame_RAM_wr_addr_y,3'b0} + {3'b0,dis_frame_RAM_wr_addr_y,2'b0}): + //chroma,x22 = x16 + x4 + x2 + ({1'b0,dis_frame_RAM_wr_addr_y,4'b0} + {3'b0,dis_frame_RAM_wr_addr_y,2'b0} + {4'b0,dis_frame_RAM_wr_addr_y,1'b0}); + + wire [13:0] dis_frame_RAM_wr_addr_tmp; + reg [13:0] dis_frame_RAM_wr_addr_LeftTop_reg; + reg [13:0] dis_frame_RAM_wr_addr_reg; + reg [13:0] dis_frame_RAM_wr_addr; + + assign dis_frame_RAM_wr_addr_tmp = dis_frame_RAM_wr_addr_base + dis_frame_RAM_wr_addr_y_ext + dis_frame_RAM_wr_addr_x; + always @ (posedge clk) + if (reset_n == 1'b0) + dis_frame_RAM_wr_addr_LeftTop_reg <= 0; + else if (Is_MB_LeftTop_wr) + dis_frame_RAM_wr_addr_LeftTop_reg <= dis_frame_RAM_wr_addr_tmp; + + always @ (disable_DF or Is_MB_LeftTop_wr or Is_1st_cycle_wr or Is_luma_wr or Is_chroma_wr or dis_frame_RAM_wr_addr_tmp + or dis_frame_RAM_wr_addr_reg or blk4x4_rec_counter_2_raster_order or dis_frame_RAM_wr_addr_LeftTop_reg) + if (disable_DF) + begin + if (Is_MB_LeftTop_wr) + dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_tmp; + else if (Is_1st_cycle_wr) + case (blk4x4_rec_counter_2_raster_order[4]) + 1'b0: + case (blk4x4_rec_counter_2_raster_order[3:2]) + 2'b00:dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_LeftTop_reg + blk4x4_rec_counter_2_raster_order[1:0]; + 2'b01:dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_LeftTop_reg + blk4x4_rec_counter_2_raster_order[1:0] + 176; + 2'b10:dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_LeftTop_reg + blk4x4_rec_counter_2_raster_order[1:0] + 352; + 2'b11:dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_LeftTop_reg + blk4x4_rec_counter_2_raster_order[1:0] + 528; + endcase + 1'b1: + dis_frame_RAM_wr_addr <= (blk4x4_rec_counter_2_raster_order[1])? + (dis_frame_RAM_wr_addr_LeftTop_reg + 88 + blk4x4_rec_counter_2_raster_order[0]): + (dis_frame_RAM_wr_addr_LeftTop_reg + blk4x4_rec_counter_2_raster_order[0]); + endcase + else if (Is_luma_wr) + dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_reg + 44; + else if (Is_chroma_wr) + dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_reg + 22; + else + dis_frame_RAM_wr_addr <= 0; + end + else + begin + if (Is_1st_cycle_wr) + dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_tmp; + else if (Is_luma_wr) + dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_reg + 44; + else if (Is_chroma_wr) + dis_frame_RAM_wr_addr <= dis_frame_RAM_wr_addr_reg + 22; + else + dis_frame_RAM_wr_addr <= 0; + end + + always @ (posedge clk) + if (reset_n == 1'b0) + dis_frame_RAM_wr_addr_reg <= 0; + else if (dis_frame_RAM_wr_tmp) + dis_frame_RAM_wr_addr_reg <= dis_frame_RAM_wr_addr; + + //dis_frame_RAM_din + wire Is_mbAddrB_t1; + wire Is_currMB_buf0; + wire Is_currMB_buf2; + wire Is_currMB_buf3; + wire Is_currMB_t1; + assign Is_mbAddrB_t1 = (DF_edge_counter_MW == 6'd14 || DF_edge_counter_MW == 6'd38 || + DF_edge_counter_MW == 6'd46); + assign Is_currMB_buf0 = (DF_edge_counter_MW == 6'd6 || DF_edge_counter_MW == 6'd15 || + DF_edge_counter_MW == 6'd31 || DF_edge_counter_MW == 6'd39 || + DF_edge_counter_MW == 6'd47); + assign Is_currMB_buf2 = (DF_edge_counter_MW == 6'd22 || DF_edge_counter_MW == 6'd33 || + DF_edge_counter_MW == 6'd41); + assign Is_currMB_buf3 = (DF_edge_counter_MW == 6'd26); + assign Is_currMB_t1 = (DF_edge_counter_MW == 6'd10 || DF_edge_counter_MW == 6'd23 || + DF_edge_counter_MW == 6'd27 || DF_edge_counter_MW == 6'd30 || + DF_edge_counter_MW == 6'd36 || DF_edge_counter_MW == 6'd44); + + reg [31:0] dis_frame_RAM_din; + always @ (disable_DF or dis_frame_RAM_wr or blk4x4_sum_counter or one_edge_counter_MW or + DF_12_cycles or Is_mbAddrA_real_wr or Is_mbAddrB_wr or Is_mbAddrB_t1 or Is_currMB_buf0 or + Is_currMB_buf2 or Is_currMB_buf3 or Is_currMB_t1 or Is_currMB_wr or + blk4x4_sum_PE0_out or blk4x4_sum_PE1_out or blk4x4_sum_PE2_out or blk4x4_sum_PE3_out or + p0_MW or p1_MW or p2_MW or p3_MW or + buf0_0 or buf0_1 or buf0_2 or buf0_3 or + buf2_0 or buf2_1 or buf2_2 or buf2_3 or buf3_0 or buf3_1 or buf3_2 or buf3_3 or + t0_0 or t0_1 or t0_2 or t0_3 or t1_0 or t1_1 or t1_2 or t1_3) + if (disable_DF && dis_frame_RAM_wr) + begin + if (blk4x4_sum_counter[2] == 1'b0) + dis_frame_RAM_din <= {blk4x4_sum_PE3_out,blk4x4_sum_PE2_out,blk4x4_sum_PE1_out,blk4x4_sum_PE0_out}; + else + dis_frame_RAM_din <= 0; + end + else if (!disable_DF && dis_frame_RAM_wr) + case ({Is_mbAddrA_real_wr,Is_mbAddrB_wr,Is_currMB_wr}) + 3'b100: //Is_mbAddrA_wr + dis_frame_RAM_din <= {p0_MW,p1_MW,p2_MW,p3_MW}; + 3'b010: //Is_mbAddrB_wr + begin + if (Is_mbAddrB_t1) //T1 -> mbAddrB + case (one_edge_counter_MW) + 2'd0:dis_frame_RAM_din <= t1_0; + 2'd1:dis_frame_RAM_din <= t1_1; + 2'd2:dis_frame_RAM_din <= t1_2; + 2'd3:dis_frame_RAM_din <= t1_3; + endcase + else //T0 -> mbAddrB + case (one_edge_counter_MW) + 2'd0:dis_frame_RAM_din <= t0_0; + 2'd1:dis_frame_RAM_din <= t0_1; + 2'd2:dis_frame_RAM_din <= t0_2; + 2'd3:dis_frame_RAM_din <= t0_3; + endcase + end + 3'b001: //Is_currMB_wr + case ({Is_currMB_buf0,Is_currMB_buf2,Is_currMB_buf3,Is_currMB_t1}) + 4'b1000: //Is_currMB_buf0 + case (one_edge_counter_MW) + 2'd0:dis_frame_RAM_din <= buf0_0; + 2'd1:dis_frame_RAM_din <= buf0_1; + 2'd2:dis_frame_RAM_din <= buf0_2; + 2'd3:dis_frame_RAM_din <= buf0_3; + endcase + 4'b0100: //Is_currMB_buf2 + case (one_edge_counter_MW) + 2'd0:dis_frame_RAM_din <= buf2_0; + 2'd1:dis_frame_RAM_din <= buf2_1; + 2'd2:dis_frame_RAM_din <= buf2_2; + 2'd3:dis_frame_RAM_din <= buf2_3; + endcase + 4'b0010: //Is_currMB_buf3 + case (one_edge_counter_MW) + 2'd0:dis_frame_RAM_din <= buf3_0; + 2'd1:dis_frame_RAM_din <= buf3_1; + 2'd2:dis_frame_RAM_din <= buf3_2; + 2'd3:dis_frame_RAM_din <= buf3_3; + endcase + 4'b0001: //Is_currMB_t1 + case (one_edge_counter_MW) + 2'd0:dis_frame_RAM_din <= t1_0; + 2'd1:dis_frame_RAM_din <= t1_1; + 2'd2:dis_frame_RAM_din <= t1_2; + 2'd3:dis_frame_RAM_din <= t1_3; + endcase + default: //Is_currMB_t0 + case (one_edge_counter_MW) + 2'd0:dis_frame_RAM_din <= t0_0; + 2'd1:dis_frame_RAM_din <= t0_1; + 2'd2:dis_frame_RAM_din <= t0_2; + 2'd3:dis_frame_RAM_din <= t0_3; + endcase + endcase + default://additional 12 cycles + case (DF_12_cycles[3:2]) + 2'b00: //0 ~ 3,buf2 -> blk22 + case (DF_12_cycles[1:0]) + 2'd0:dis_frame_RAM_din <= buf2_0; + 2'd1:dis_frame_RAM_din <= buf2_1; + 2'd2:dis_frame_RAM_din <= buf2_2; + 2'd3:dis_frame_RAM_din <= buf2_3; + endcase + 2'b01: //4 ~ 7,T0 -> blk21 + case (DF_12_cycles[1:0]) + 2'd0:dis_frame_RAM_din <= t0_0; + 2'd1:dis_frame_RAM_din <= t0_1; + 2'd2:dis_frame_RAM_din <= t0_2; + 2'd3:dis_frame_RAM_din <= t0_3; + endcase + default://8 ~ 11,T1 -> blk23 + case (DF_12_cycles[1:0]) + 2'd0:dis_frame_RAM_din <= t1_0; + 2'd1:dis_frame_RAM_din <= t1_1; + 2'd2:dis_frame_RAM_din <= t1_2; + 2'd3:dis_frame_RAM_din <= t1_3; + endcase + endcase + endcase + else + dis_frame_RAM_din <= 0; +endmodule + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/DF_pipeline.v b/demo_chip_rtl/rtl/nova/trunk/src/DF_pipeline.v new file mode 100644 index 0000000..a474c13 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/DF_pipeline.v @@ -0,0 +1,861 @@ +//----------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : DF_pipeline.v +// Generated : Dec 2, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// 5-stage pipeline control for deblocking filter +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module DF_pipeline (clk,gclk_DF,gclk_end_of_MB_DEC,reset_n,disable_DF,end_of_BS_DEC, + end_of_MB_DF,end_of_lastMB_DF, + bs_V0,bs_V1,bs_V2,bs_V3,bs_H0,bs_H1,bs_H2,bs_H3, + QPy,QPc,slice_alpha_c0_offset_div2,slice_beta_offset_div2, + DF_mbAddrA_RF_dout,DF_mbAddrB_RAM_dout,rec_DF_RAM_dout, + buf0_0,buf0_1,buf0_2,buf0_3,buf1_0,buf1_1,buf1_2,buf1_3, + buf2_0,buf2_1,buf2_2,buf2_3,buf3_0,buf3_1,buf3_2,buf3_3, + + DF_duration, + DF_edge_counter_MR,DF_edge_counter_MW, + one_edge_counter_MR,one_edge_counter_MW, + bs_curr_MR,bs_curr_MW, + p0_MW,p1_MW,p2_MW,p3_MW,q0_MW,q1_MW,q2_MW,q3_MW); + input clk; + input gclk_DF; + input gclk_end_of_MB_DEC; + input reset_n; + input disable_DF; + input end_of_BS_DEC; + input end_of_MB_DF; + input end_of_lastMB_DF; + input [11:0] bs_V0,bs_V1,bs_V2,bs_V3; + input [11:0] bs_H0,bs_H1,bs_H2,bs_H3; + input [5:0] QPy,QPc; + input [3:0] slice_alpha_c0_offset_div2,slice_beta_offset_div2; + input [31:0] DF_mbAddrA_RF_dout,DF_mbAddrB_RAM_dout,rec_DF_RAM_dout; + input [31:0] buf0_0,buf0_1,buf0_2,buf0_3,buf1_0,buf1_1,buf1_2,buf1_3; + input [31:0] buf2_0,buf2_1,buf2_2,buf2_3,buf3_0,buf3_1,buf3_2,buf3_3; + + output DF_duration; + output [5:0] DF_edge_counter_MR,DF_edge_counter_MW; + output [1:0] one_edge_counter_MR,one_edge_counter_MW; + output [2:0] bs_curr_MR; + output [2:0] bs_curr_MW; + output [7:0] p0_MW,p1_MW,p2_MW,p3_MW; + output [7:0] q0_MW,q1_MW,q2_MW,q3_MW; + + reg DF_duration; + always @ (posedge clk or negedge reset_n) + if (reset_n == 1'b0) + DF_duration <= 1'b0; + else if (end_of_BS_DEC) + DF_duration <= 1'b1; + else if (end_of_MB_DF || end_of_lastMB_DF) + DF_duration <= 1'b0; + + //--------------------------------------------------------------------- + //1.MR: Memory Read + //--------------------------------------------------------------------- + //DF_edge_counter_MR & one_edge_counter_MR + reg [5:0] DF_edge_counter_MR; + reg [1:0] one_edge_counter_MR; + always @ (posedge gclk_DF or negedge reset_n) + if (reset_n == 1'b0) + DF_edge_counter_MR <= 6'd48; + else if (end_of_BS_DEC == 1'b1) + DF_edge_counter_MR <= 0; + else if (one_edge_counter_MR == 2'd3 && DF_edge_counter_MR != 6'd48) + DF_edge_counter_MR <= DF_edge_counter_MR + 1; + + always @ (posedge gclk_DF or negedge reset_n) + if (reset_n == 0) + one_edge_counter_MR <= 2'd3; + else if (end_of_BS_DEC == 1'b1) + one_edge_counter_MR <= 2'd0; + else + begin + if (one_edge_counter_MR == 2'd3 && DF_edge_counter_MR != 6'd47 && DF_edge_counter_MR[5:4] != 2'b11) //!47,!48 + one_edge_counter_MR <= 2'd0; + else if (one_edge_counter_MR != 2'd3) + one_edge_counter_MR <= one_edge_counter_MR + 1; + end + + //lumaEdgeFlag_MR,chromaEdgeFlag_MR + wire lumaEdgeFlag_MR,chromaEdgeFlag_MR; + assign lumaEdgeFlag_MR = !DF_edge_counter_MR[5]; + assign chromaEdgeFlag_MR = DF_edge_counter_MR[5] && (DF_edge_counter_MR != 6'd48); + + //bs_curr_MR + reg [2:0] bs_curr_MR; + always @ (disable_DF or lumaEdgeFlag_MR or chromaEdgeFlag_MR or + DF_edge_counter_MR[4:0] or one_edge_counter_MR[1] or + bs_V0 or bs_V1 or bs_V2 or bs_V3 or bs_H0 or bs_H1 or bs_H2 or bs_H3) + if (!disable_DF && lumaEdgeFlag_MR) + case (DF_edge_counter_MR[4:0]) + 5'd0 :bs_curr_MR <= bs_V0[2:0]; + 5'd1 :bs_curr_MR <= bs_V1[2:0]; + 5'd2 :bs_curr_MR <= bs_V0[5:3]; + 5'd3 :bs_curr_MR <= bs_V1[5:3]; + 5'd4 :bs_curr_MR <= bs_H0[2:0]; + 5'd5 :bs_curr_MR <= bs_H1[2:0]; + 5'd6 :bs_curr_MR <= bs_V2[2:0]; + 5'd7 :bs_curr_MR <= bs_V2[5:3]; + 5'd8 :bs_curr_MR <= bs_H0[5:3]; + 5'd9 :bs_curr_MR <= bs_H1[5:3]; + 5'd10:bs_curr_MR <= bs_V3[2:0]; + 5'd11:bs_curr_MR <= bs_V3[5:3]; + 5'd12:bs_curr_MR <= bs_H0[8:6]; + 5'd13:bs_curr_MR <= bs_H0[11:9]; + 5'd14:bs_curr_MR <= bs_H1[8:6]; + 5'd15:bs_curr_MR <= bs_H1[11:9]; + 5'd16:bs_curr_MR <= bs_V0[8:6]; + 5'd17:bs_curr_MR <= bs_V1[8:6]; + 5'd18:bs_curr_MR <= bs_V0[11:9]; + 5'd19:bs_curr_MR <= bs_V1[11:9]; + 5'd20:bs_curr_MR <= bs_H2[2:0]; + 5'd21:bs_curr_MR <= bs_H3[2:0]; + 5'd22:bs_curr_MR <= bs_V2[8:6]; + 5'd23:bs_curr_MR <= bs_V2[11:9]; + 5'd24:bs_curr_MR <= bs_H2[5:3]; + 5'd25:bs_curr_MR <= bs_H3[5:3]; + 5'd26:bs_curr_MR <= bs_V3[8:6]; + 5'd27:bs_curr_MR <= bs_V3[11:9]; + 5'd28:bs_curr_MR <= bs_H2[8:6]; + 5'd29:bs_curr_MR <= bs_H2[11:9]; + 5'd30:bs_curr_MR <= bs_H3[8:6]; + 5'd31:bs_curr_MR <= bs_H3[11:9]; + endcase + else if (!disable_DF && chromaEdgeFlag_MR) + case (DF_edge_counter_MR[3:0]) + 4'd0,4'd8: //32,40 + case (one_edge_counter_MR[1]) + 1'b0:bs_curr_MR <= bs_V0[2:0]; + 1'b1:bs_curr_MR <= bs_V0[5:3]; + endcase + 4'd2,4'd10: //34,42 + case (one_edge_counter_MR[1]) + 1'b0:bs_curr_MR <= bs_V0[8:6]; + 1'b1:bs_curr_MR <= bs_V0[11:9]; + endcase + 4'd1,4'd9: //33,41 + case (one_edge_counter_MR[1]) + 1'b0:bs_curr_MR <= bs_V2[2:0]; + 1'b1:bs_curr_MR <= bs_V2[5:3]; + endcase + 4'd3,4'd11: //35,43 + case (one_edge_counter_MR[1]) + 1'b0:bs_curr_MR <= bs_V2[8:6]; + 1'b1:bs_curr_MR <= bs_V2[11:9]; + endcase + 4'd4,4'd12: //36,44 + case (one_edge_counter_MR[1]) + 1'b0:bs_curr_MR <= bs_H0[2:0]; + 1'b1:bs_curr_MR <= bs_H0[5:3]; + endcase + 4'd5,4'd13: //37,45 + case (one_edge_counter_MR[1]) + 1'b0:bs_curr_MR <= bs_H0[8:6]; + 1'b1:bs_curr_MR <= bs_H0[11:9]; + endcase + 4'd6,4'd14: //38,46 + case (one_edge_counter_MR[1]) + 1'b0:bs_curr_MR <= bs_H2[2:0]; + 1'b1:bs_curr_MR <= bs_H2[5:3]; + endcase + 4'd7,4'd15: //39,47 + case (one_edge_counter_MR[1]) + 1'b0:bs_curr_MR <= bs_H2[8:6]; + 1'b1:bs_curr_MR <= bs_H2[11:9]; + endcase + endcase + else + bs_curr_MR <= 0; + + // Pipelined parameters + reg [2:0] bs_curr_TD; + reg lumaEdgeFlag_TD,chromaEdgeFlag_TD; + reg [5:0] DF_edge_counter_TD; + reg [1:0] one_edge_counter_TD; + always @ (posedge gclk_DF or negedge reset_n) + if (reset_n == 1'b0) + begin + bs_curr_TD <= 0; + lumaEdgeFlag_TD <= 0; + chromaEdgeFlag_TD <= 0; + DF_edge_counter_TD <= 6'd48; + one_edge_counter_TD <= 2'd3; + end + else + begin + bs_curr_TD <= bs_curr_MR; + lumaEdgeFlag_TD <= lumaEdgeFlag_MR; + chromaEdgeFlag_TD <= chromaEdgeFlag_MR; + DF_edge_counter_TD <= DF_edge_counter_MR; + one_edge_counter_TD <= one_edge_counter_MR; + end + //--------------------------------------------------------------------- + //2.TD: Threshold Decider + //--------------------------------------------------------------------- + wire [6:0] indexA_y_unclipped,indexA_c_unclipped; + wire [6:0] indexB_y_unclipped,indexB_c_unclipped; + assign indexA_y_unclipped = QPy + {{2{slice_alpha_c0_offset_div2[3]}},slice_alpha_c0_offset_div2,1'b0}; + assign indexA_c_unclipped = QPc + {{2{slice_alpha_c0_offset_div2[3]}},slice_alpha_c0_offset_div2,1'b0}; + assign indexB_y_unclipped = QPy + {{2{slice_beta_offset_div2[3]}},slice_beta_offset_div2,1'b0}; + assign indexB_c_unclipped = QPc + {{2{slice_beta_offset_div2[3]}},slice_beta_offset_div2,1'b0}; + + wire [5:0] indexA_y,indexA_c; + wire [5:0] indexB_y,indexB_c; + assign indexA_y = (indexA_y_unclipped[6] == 1)? 0:((indexA_y_unclipped[5:0] > 6'd51)? 6'd51:indexA_y_unclipped[5:0]); + assign indexA_c = (indexA_c_unclipped[6] == 1)? 0:((indexA_c_unclipped[5:0] > 6'd51)? 6'd51:indexA_c_unclipped[5:0]); + assign indexB_y = (indexB_y_unclipped[6] == 1)? 0:((indexB_y_unclipped[5:0] > 6'd51)? 6'd51:indexB_y_unclipped[5:0]); + assign indexB_c = (indexB_c_unclipped[6] == 1)? 0:((indexB_c_unclipped[5:0] > 6'd51)? 6'd51:indexB_c_unclipped[5:0]); + + reg [5:0] indexA_y_reg,indexA_c_reg; + reg [5:0] indexB_y_reg,indexB_c_reg; + always @ (posedge gclk_end_of_MB_DEC or negedge reset_n) + if (reset_n == 1'b0) + begin indexA_y_reg <= 0; indexA_c_reg <= 0; indexB_y_reg <= 0; indexB_c_reg <= 0; end + else if (!disable_DF) + begin + indexA_y_reg <= indexA_y; indexA_c_reg <= indexA_c; + indexB_y_reg <= indexB_y; indexB_c_reg <= indexB_c; + end + + wire [5:0] indexA,indexB; + assign indexA = (lumaEdgeFlag_TD)? indexA_y_reg:((chromaEdgeFlag_TD)? indexA_c_reg:0); + assign indexB = (lumaEdgeFlag_TD)? indexB_y_reg:((chromaEdgeFlag_TD)? indexB_c_reg:0); + + reg [7:0] alpha,beta; + //alpha + always @ (indexA) + if (indexA < 16) + alpha <= 0; + else + case (indexA) + 6'd16,6'd17:alpha <= 8'd4; + 6'd18:alpha <= 8'd5; 6'd19:alpha <= 8'd6; 6'd20:alpha <= 8'd7; 6'd21:alpha <= 8'd8; + 6'd22:alpha <= 8'd9; 6'd23:alpha <= 8'd10; 6'd24:alpha <= 8'd12; 6'd25:alpha <= 8'd13; + 6'd26:alpha <= 8'd15; 6'd27:alpha <= 8'd17; 6'd28:alpha <= 8'd20; 6'd29:alpha <= 8'd22; + 6'd30:alpha <= 8'd25; 6'd31:alpha <= 8'd28; 6'd32:alpha <= 8'd32; 6'd33:alpha <= 8'd36; + 6'd34:alpha <= 8'd40; 6'd35:alpha <= 8'd45; 6'd36:alpha <= 8'd50; 6'd37:alpha <= 8'd56; + 6'd38:alpha <= 8'd63; 6'd39:alpha <= 8'd71; 6'd40:alpha <= 8'd80; 6'd41:alpha <= 8'd90; + 6'd42:alpha <= 8'd101; 6'd43:alpha <= 8'd113; 6'd44:alpha <= 8'd127; 6'd45:alpha <= 8'd144; + 6'd46:alpha <= 8'd162; 6'd47:alpha <= 8'd182; 6'd48:alpha <= 8'd203; 6'd49:alpha <= 8'd226; + default:alpha <= 8'd255; + endcase + //beta + always @ (indexB) + if (indexB < 16) + beta <= 0; + else if (indexB > 15 && indexB < 26) + case (indexB) + 6'd16,6'd17,6'd18 :beta <= 8'd2; + 6'd19,6'd20,6'd21,6'd22 :beta <= 8'd3; + 6'd23,6'd24,6'd25 :beta <= 8'd4; + default:beta <= 0; + endcase + else + beta <= indexB[5:1] - 3'd7; + + wire [7:0] absolute_TD0_a,absolute_TD0_b; + wire [7:0] absolute_TD1_a,absolute_TD1_b; + wire [7:0] absolute_TD2_a,absolute_TD2_b; + wire [7:0] absolute_TD0_out,absolute_TD1_out,absolute_TD2_out; + absolute absolute_TD0 (.a(absolute_TD0_a),.b(absolute_TD0_b),.out(absolute_TD0_out)); + absolute absolute_TD1 (.a(absolute_TD1_a),.b(absolute_TD1_b),.out(absolute_TD1_out)); + absolute absolute_TD2 (.a(absolute_TD2_a),.b(absolute_TD2_b),.out(absolute_TD2_out)); + + //p0 ~ p3 + wire Is_p_from_mbAddrA; + wire Is_p_from_mbAddrB; + wire Is_p_from_buf0; + wire Is_p_from_buf1; + wire Is_p_from_buf2; + wire Is_p_from_buf3; + assign Is_p_from_mbAddrA = (DF_edge_counter_TD == 6'd0 || DF_edge_counter_TD == 6'd2 || + DF_edge_counter_TD == 6'd16 || DF_edge_counter_TD == 6'd18 || DF_edge_counter_TD == 6'd32 || + DF_edge_counter_TD == 6'd34 || DF_edge_counter_TD == 6'd40 || DF_edge_counter_TD == 6'd42); + + assign Is_p_from_mbAddrB = (DF_edge_counter_TD == 6'd4 || DF_edge_counter_TD == 6'd8 || + DF_edge_counter_TD == 6'd12 || DF_edge_counter_TD == 6'd13 || DF_edge_counter_TD == 6'd20 || + DF_edge_counter_TD == 6'd24 || DF_edge_counter_TD == 6'd28 || DF_edge_counter_TD == 6'd29 || + DF_edge_counter_TD == 6'd36 || DF_edge_counter_TD == 6'd37 || DF_edge_counter_TD == 6'd44 || + DF_edge_counter_TD == 6'd45); + + assign Is_p_from_buf0 = (DF_edge_counter_TD == 6'd1 || DF_edge_counter_TD == 6'd5 || + DF_edge_counter_TD == 6'd10 || DF_edge_counter_TD == 6'd14 || DF_edge_counter_TD == 6'd17 || + DF_edge_counter_TD == 6'd21 || DF_edge_counter_TD == 6'd26 || DF_edge_counter_TD == 6'd30 || + DF_edge_counter_TD == 6'd33 || DF_edge_counter_TD == 6'd38 || DF_edge_counter_TD == 6'd41 || + DF_edge_counter_TD == 6'd46); + + assign Is_p_from_buf1 = (DF_edge_counter_TD == 6'd6 || DF_edge_counter_TD == 6'd9 || + DF_edge_counter_TD == 6'd15 || DF_edge_counter_TD == 6'd22 || DF_edge_counter_TD == 6'd25 || + DF_edge_counter_TD == 6'd31 || DF_edge_counter_TD == 6'd39 || DF_edge_counter_TD == 6'd47); + + assign Is_p_from_buf2 = (DF_edge_counter_TD == 6'd3 || DF_edge_counter_TD == 6'd11 || + DF_edge_counter_TD == 6'd19 || DF_edge_counter_TD == 6'd27 || DF_edge_counter_TD == 6'd35 || + DF_edge_counter_TD == 6'd43); + + assign Is_p_from_buf3 = (DF_edge_counter_TD == 6'd7 || DF_edge_counter_TD == 6'd23); + + reg [7:0] p0,p1,p2,p3; + always @ (Is_p_from_mbAddrA or Is_p_from_mbAddrB or Is_p_from_buf0 or Is_p_from_buf1 or + Is_p_from_buf2 or Is_p_from_buf3 or one_edge_counter_TD or + DF_mbAddrA_RF_dout or DF_mbAddrB_RAM_dout or + buf0_0 or buf0_1 or buf0_2 or buf0_3 or buf1_0 or buf1_1 or buf1_2 or buf1_3 or + buf2_0 or buf2_1 or buf2_2 or buf2_3 or buf3_0 or buf3_1 or buf3_2 or buf3_3) + case ({Is_p_from_mbAddrA,Is_p_from_mbAddrB,Is_p_from_buf0,Is_p_from_buf1,Is_p_from_buf2,Is_p_from_buf3}) + 6'b100000:{p0,p1,p2,p3} <= DF_mbAddrA_RF_dout; + 6'b010000:{p0,p1,p2,p3} <= DF_mbAddrB_RAM_dout; + 6'b001000: case (one_edge_counter_TD) + 2'b00:{p0,p1,p2,p3} <= buf0_0; + 2'b01:{p0,p1,p2,p3} <= buf0_1; + 2'b10:{p0,p1,p2,p3} <= buf0_2; + 2'b11:{p0,p1,p2,p3} <= buf0_3; + endcase + 6'b000100: case (one_edge_counter_TD) + 2'b00:{p0,p1,p2,p3} <= buf1_0; + 2'b01:{p0,p1,p2,p3} <= buf1_1; + 2'b10:{p0,p1,p2,p3} <= buf1_2; + 2'b11:{p0,p1,p2,p3} <= buf1_3; + endcase + 6'b000010: case (one_edge_counter_TD) + 2'b00:{p0,p1,p2,p3} <= buf2_0; + 2'b01:{p0,p1,p2,p3} <= buf2_1; + 2'b10:{p0,p1,p2,p3} <= buf2_2; + 2'b11:{p0,p1,p2,p3} <= buf2_3; + endcase + 6'b000001: case (one_edge_counter_TD) + 2'b00:{p0,p1,p2,p3} <= buf3_0; + 2'b01:{p0,p1,p2,p3} <= buf3_1; + 2'b10:{p0,p1,p2,p3} <= buf3_2; + 2'b11:{p0,p1,p2,p3} <= buf3_3; + endcase + default:{p0,p1,p2,p3} <= 0; + endcase + + //q0 ~ q3 + wire Is_q_from_buf0; + wire Is_q_from_buf1; + wire Is_q_from_buf2; + wire Is_q_from_buf3; + + assign Is_q_from_buf0 = (DF_edge_counter_TD == 6'd4 || DF_edge_counter_TD == 6'd12 || + DF_edge_counter_TD == 6'd20 || DF_edge_counter_TD == 6'd28 || DF_edge_counter_TD == 6'd36 || + DF_edge_counter_TD == 6'd44); + + assign Is_q_from_buf1 = (DF_edge_counter_TD == 6'd8 || DF_edge_counter_TD == 6'd13 || + DF_edge_counter_TD == 6'd24 || DF_edge_counter_TD == 6'd29 || DF_edge_counter_TD == 6'd37 || + DF_edge_counter_TD == 6'd45); + + assign Is_q_from_buf2 = (DF_edge_counter_TD == 6'd5 || DF_edge_counter_TD == 6'd14 || + DF_edge_counter_TD == 6'd21 || DF_edge_counter_TD == 6'd30 || DF_edge_counter_TD == 6'd38 || + DF_edge_counter_TD == 6'd46); + + assign Is_q_from_buf3 = (DF_edge_counter_TD == 6'd9 || DF_edge_counter_TD == 6'd15 || + DF_edge_counter_TD == 6'd25 || DF_edge_counter_TD == 6'd31 || DF_edge_counter_TD == 6'd39 || + DF_edge_counter_TD == 6'd47); + + reg [7:0] q0,q1,q2,q3; + always @ (Is_q_from_buf0 or Is_q_from_buf1 or Is_q_from_buf2 or Is_q_from_buf3 or + rec_DF_RAM_dout or one_edge_counter_TD or DF_edge_counter_TD or + buf0_0 or buf0_1 or buf0_2 or buf0_3 or buf1_0 or buf1_1 or buf1_2 or buf1_3 or + buf2_0 or buf2_1 or buf2_2 or buf2_3 or buf3_0 or buf3_1 or buf3_2 or buf3_3) + case ({Is_q_from_buf0,Is_q_from_buf1,Is_q_from_buf2,Is_q_from_buf3}) + 4'b1000:case (one_edge_counter_TD) + 2'b00:{q3,q2,q1,q0} <= buf0_0; + 2'b01:{q3,q2,q1,q0} <= buf0_1; + 2'b10:{q3,q2,q1,q0} <= buf0_2; + 2'b11:{q3,q2,q1,q0} <= buf0_3; + endcase + 4'b0100:case (one_edge_counter_TD) + 2'b00:{q3,q2,q1,q0} <= buf1_0; + 2'b01:{q3,q2,q1,q0} <= buf1_1; + 2'b10:{q3,q2,q1,q0} <= buf1_2; + 2'b11:{q3,q2,q1,q0} <= buf1_3; + endcase + 4'b0010:case (one_edge_counter_TD) + 2'b00:{q3,q2,q1,q0} <= buf2_0; + 2'b01:{q3,q2,q1,q0} <= buf2_1; + 2'b10:{q3,q2,q1,q0} <= buf2_2; + 2'b11:{q3,q2,q1,q0} <= buf2_3; + endcase + 4'b0001:case (one_edge_counter_TD) + 2'b00:{q3,q2,q1,q0} <= buf3_0; + 2'b01:{q3,q2,q1,q0} <= buf3_1; + 2'b10:{q3,q2,q1,q0} <= buf3_2; + 2'b11:{q3,q2,q1,q0} <= buf3_3; + endcase + default:if (DF_edge_counter_TD != 6'd48) {q3,q2,q1,q0} <= rec_DF_RAM_dout; + else {q3,q2,q1,q0} <= 0; + endcase + + // |p0 - q0| < alpha + assign absolute_TD0_a = (!disable_DF && bs_curr_TD != 0)? p0:0; + assign absolute_TD0_b = (!disable_DF && bs_curr_TD != 0)? q0:0; + + // |p1 - p0| < beta + assign absolute_TD1_a = (!disable_DF && bs_curr_TD != 0)? p0:0; + assign absolute_TD1_b = (!disable_DF && bs_curr_TD != 0)? p1:0; + + // |q1 - q0| < beta + assign absolute_TD2_a = (!disable_DF && bs_curr_TD != 0)? q0:0; + assign absolute_TD2_b = (!disable_DF && bs_curr_TD != 0)? q1:0; + + // Threshold + wire threshold; + assign threshold = ((absolute_TD0_out < alpha) && (absolute_TD1_out < beta) && + (absolute_TD2_out < beta))? 1'b1:1'b0; + + // Pipelined parameters + reg [2:0] bs_curr_PRE; + reg [5:0] DF_edge_counter_PRE; + reg [1:0] one_edge_counter_PRE; + reg lumaEdgeFlag_PRE,chromaEdgeFlag_PRE; + reg [7:0] p0_PRE,p1_PRE,p2_PRE,p3_PRE; + reg [7:0] q0_PRE,q1_PRE,q2_PRE,q3_PRE; + reg [5:0] indexA_PRE; + reg [7:0] alpha_PRE,beta_PRE; + always @ (posedge gclk_DF or negedge reset_n) + if (reset_n == 1'b0) + begin + bs_curr_PRE <= 0; + DF_edge_counter_PRE <= 6'd48; + one_edge_counter_PRE <= 2'd3; + lumaEdgeFlag_PRE <= 0; + chromaEdgeFlag_PRE <= 0; + indexA_PRE <= 0; + alpha_PRE <= 0; + beta_PRE <= 0; + p0_PRE <= 0; p1_PRE <= 0; p2_PRE <= 0; p3_PRE <= 0; + q0_PRE <= 0; q1_PRE <= 0; q2_PRE <= 0; q3_PRE <= 0; + end + else + begin + bs_curr_PRE <= (threshold)? bs_curr_TD:0; + DF_edge_counter_PRE <= DF_edge_counter_TD; + one_edge_counter_PRE<= one_edge_counter_TD; + lumaEdgeFlag_PRE <= (threshold)? lumaEdgeFlag_TD:0; + chromaEdgeFlag_PRE <= (threshold)? chromaEdgeFlag_TD:0; + indexA_PRE <= (threshold)? indexA:0; + alpha_PRE <= (threshold)? alpha:0; + beta_PRE <= (threshold)? beta:0; + p0_PRE <= p0; p1_PRE <= p1; p2_PRE <= p2; p3_PRE <= p3; + q0_PRE <= q0; q1_PRE <= q1; q2_PRE <= q2; q3_PRE <= q3; + end + //--------------------------------------------------------------------- + //3.PRE: Precomputation + //--------------------------------------------------------------------- + wire [7:0] absolute_PRE0_a,absolute_PRE0_b; + wire [7:0] absolute_PRE1_a,absolute_PRE1_b; + wire [7:0] absolute_PRE2_a,absolute_PRE2_b; + wire [7:0] absolute_PRE0_out,absolute_PRE1_out,absolute_PRE2_out; + + absolute absolute_PRE0 (.a(absolute_PRE0_a),.b(absolute_PRE0_b),.out(absolute_PRE0_out)); + absolute absolute_PRE1 (.a(absolute_PRE1_a),.b(absolute_PRE1_b),.out(absolute_PRE1_out)); + absolute absolute_PRE2 (.a(absolute_PRE2_a),.b(absolute_PRE2_b),.out(absolute_PRE2_out)); + + // |p2 - p0| < beta + assign absolute_PRE0_a = (bs_curr_PRE != 0 && lumaEdgeFlag_PRE)? p2_PRE:0; + assign absolute_PRE0_b = (bs_curr_PRE != 0 && lumaEdgeFlag_PRE)? p0_PRE:0; + + // |q2 - q0| < beta + assign absolute_PRE1_a = (bs_curr_PRE != 0 && lumaEdgeFlag_PRE)? q2_PRE:0; + assign absolute_PRE1_b = (bs_curr_PRE != 0 && lumaEdgeFlag_PRE)? q0_PRE:0; + + // |p0 - q0| < alpha >> 2 + 2 + assign absolute_PRE2_a = (lumaEdgeFlag_PRE && bs_curr_PRE == 3'd4)? p0_PRE:0; + assign absolute_PRE2_b = (lumaEdgeFlag_PRE && bs_curr_PRE == 3'd4)? q0_PRE:0; + + wire p2_m_p0_less_beta,q2_m_q0_less_beta,p0_m_q0_less_alpha_shift; + assign p2_m_p0_less_beta = (bs_curr_PRE == 0 || !lumaEdgeFlag_PRE)? 1'b0: + ((absolute_PRE0_out < beta_PRE)? 1'b1:1'b0); + assign q2_m_q0_less_beta = (bs_curr_PRE == 0 || !lumaEdgeFlag_PRE)? 1'b0: + ((absolute_PRE1_out < beta_PRE)? 1'b1:1'b0); + assign p0_m_q0_less_alpha_shift = (!lumaEdgeFlag_PRE || bs_curr_PRE != 4)? 1'b0: + ((absolute_PRE2_out < ((alpha_PRE >> 2) + 2))? 1'b1:1'b0); + // bs = 1 ~ 3 + reg [4:0] c1; + always @ (bs_curr_PRE or indexA_PRE) + if (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4) + case (bs_curr_PRE) + 3'd1: + if (indexA_PRE < 23) c1 <= 5'd0; + else if (indexA_PRE < 33) c1 <= 5'd1; + else if (indexA_PRE < 37) c1 <= 5'd2; + else if (indexA_PRE < 40) c1 <= 5'd3; + else if (indexA_PRE < 43) c1 <= 5'd4; + else + case (indexA_PRE) + 6'd43:c1 <= 5'd5; 6'd44,6'd45:c1 <= 5'd6; + 6'd46:c1 <= 5'd7; 6'd47:c1 <= 5'd8; 6'd48:c1 <= 5'd9; + 6'd49:c1 <= 5'd10; 6'd50:c1 <= 5'd11; 6'd51:c1 <= 5'd13; + default:c1 <= 0; + endcase + 3'd2: + if (indexA_PRE < 21) c1 <= 5'd0; + else if (indexA_PRE < 31) c1 <= 5'd1; + else if (indexA_PRE < 35) c1 <= 5'd2; + else if (indexA_PRE < 38) c1 <= 5'd3; + else + case (indexA_PRE) + 6'd38,6'd39:c1 <= 5'd4; + 6'd40,6'd41:c1 <= 5'd5; + 6'd42:c1 <= 5'd6; 6'd43:c1 <= 5'd7; 6'd44,6'd45:c1 <= 5'd8; + 6'd46:c1 <= 5'd10; 6'd47:c1 <= 5'd11; 6'd48:c1 <= 5'd12; + 6'd49:c1 <= 5'd13; 6'd50:c1 <= 5'd15; 6'd51:c1 <= 5'd17; + default:c1 <= 5'd0; + endcase + 3'd3: + if (indexA_PRE < 17) c1 <= 5'd0; + else if (indexA_PRE < 27) c1 <= 5'd1; + else if (indexA_PRE < 31) c1 <= 5'd2; + else if (indexA_PRE < 34) c1 <= 5'd3; + else if (indexA_PRE < 37) c1 <= 5'd4; + else + case (indexA_PRE) + 6'd37:c1 <= 5'd5; 6'd38,6'd39:c1 <= 5'd6; + 6'd40:c1 <= 5'd7; 6'd41:c1 <= 5'd8; 6'd42:c1 <= 5'd9; 6'd43:c1 <= 5'd10; + 6'd44:c1 <= 5'd11; 6'd45:c1 <= 5'd13; 6'd46:c1 <= 5'd14; 6'd47:c1 <= 5'd16; + 6'd48:c1 <= 5'd18; 6'd49:c1 <= 5'd20; 6'd50:c1 <= 5'd23; 6'd51:c1 <= 5'd25; + default:c1 <= 5'd0; + endcase + default:c1 <= 0; + endcase + else + c1 <= 0; + + reg [4:0] c0; + always @ (bs_curr_PRE or lumaEdgeFlag_PRE or c1 or p2_m_p0_less_beta or q2_m_q0_less_beta) + if (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4) + begin + if (lumaEdgeFlag_PRE) //filter luma edge + c0 <= ( p2_m_p0_less_beta && q2_m_q0_less_beta)? (c1 + 2): + ((!p2_m_p0_less_beta && !q2_m_q0_less_beta)? c1:(c1+1)); + else //filter chroma edge + c0 <= c1 + 1; + end + else + c0 <= 0; + + //delta_0i = [(q0 - p0) << 2 + (p1 - q1) + 4] >> 3 : P151 (8-334) of H.264/AVC standard 2003 + wire [8:0] delta_0i; + wire need_delta_0i; + wire [8:0] q0_m_p0; //p0 - q0 + wire [11:0] delta_0i_tmp; //[(p0 - q0) << 2 + (p1 - q1) + 4] + assign need_delta_0i = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4); + assign q0_m_p0 = (need_delta_0i)? ({1'b0,q0_PRE} + {1'b1,~p0_PRE} + 1):0; + assign delta_0i_tmp = (need_delta_0i)? ({q0_m_p0[8],q0_m_p0,2'b0} + p1_PRE + {4'b1111,~q1_PRE} + 5):0; + assign delta_0i = delta_0i_tmp[11:3]; + + + //delta p1i = [(p2 + ((p0 + q0 + 1) >> 1) - (p1 << 1)] >> 1 : P152 (8-341) of H.264/AVC standard 2003 + //delta q1i = [(q2 + ((p0 + q0 + 1) >> 1) - (q1 << 1)] >> 1 : P152 (8-343) of H.264/AVC standard 2003 + wire [8:0] delta_p1i,delta_q1i; + wire need_p1i; + wire need_q1i; + wire [8:0] p0_q0_sum; //p0+q0+1 + wire [9:0] neg_p1_shift; //-(p1 << 1) + wire [9:0] neg_q1_shift; //-(q1 << 1) + wire [9:0] delta_p1i_tmp;// (p2 + ((p0 + q0 + 1) >> 1) - (p1 << 1) + wire [9:0] delta_q1i_tmp;// (q2 + ((p0 + q0 + 1) >> 1) - (q1 << 1) + assign need_p1i = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4 && p2_m_p0_less_beta); + assign need_q1i = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4 && q2_m_q0_less_beta); + assign p0_q0_sum = (need_p1i || need_q1i)? ({1'b0,p0_PRE} + {1'b0,q0_PRE} + 1):0; + assign neg_p1_shift = (need_p1i)? ({1'b1,~p1_PRE,1'b1} + 1):0; + assign neg_q1_shift = (need_q1i)? ({1'b1,~q1_PRE,1'b1} + 1):0; + assign delta_p1i_tmp = (need_p1i)? (p2_PRE + p0_q0_sum[8:1] + neg_p1_shift):0; + assign delta_q1i_tmp = (need_q1i)? (q2_PRE + p0_q0_sum[8:1] + neg_q1_shift):0; + assign delta_p1i = delta_p1i_tmp[9:1]; + assign delta_q1i = delta_q1i_tmp[9:1]; + + wire [8:0] clip_to_c_0_delta,clip_to_c_p1_delta,clip_to_c_q1_delta; + wire [4:0] clip_to_c_0_c,clip_to_c_p1_c,clip_to_c_q1_c; + wire [5:0] clip_to_c_0_out,clip_to_c_p1_out,clip_to_c_q1_out; + clip_to_c clip_to_c_0 (.delta(clip_to_c_0_delta),.c(clip_to_c_0_c),.out(clip_to_c_0_out)); + clip_to_c clip_to_c_p1 (.delta(clip_to_c_p1_delta),.c(clip_to_c_p1_c),.out(clip_to_c_p1_out)); + clip_to_c clip_to_c_q1 (.delta(clip_to_c_q1_delta),.c(clip_to_c_q1_c),.out(clip_to_c_q1_out)); + + assign clip_to_c_0_delta = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4)? delta_0i:0; + assign clip_to_c_0_c = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4)? c0:0; + assign clip_to_c_p1_delta = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4 && p2_m_p0_less_beta)? delta_p1i:0; + assign clip_to_c_p1_c = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4 && p2_m_p0_less_beta)? c1:0; + assign clip_to_c_q1_delta = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4 && q2_m_q0_less_beta)? delta_q1i:0; + assign clip_to_c_q1_c = (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4 && q2_m_q0_less_beta)? c1:0; + + // Pipelined parameters + reg [5:0] delta_0,delta_p1,delta_q1; + always @ (posedge gclk_DF or negedge reset_n) + if (reset_n == 1'b0) + begin delta_0 <= 0; delta_p1 <= 0; delta_q1 <= 0; end + else if (bs_curr_PRE != 0 && bs_curr_PRE != 3'd4) + begin + delta_0 <= clip_to_c_0_out; + delta_p1 <= (p2_m_p0_less_beta)? clip_to_c_p1_out:0; + delta_q1 <= (q2_m_q0_less_beta)? clip_to_c_q1_out:0; + end + + reg p2_m_p0_less_beta_FIR,q2_m_q0_less_beta_FIR,p0_m_q0_less_alpha_shift_FIR; + reg lumaEdgeFlag_FIR,chromaEdgeFlag_FIR; + reg [2:0] bs_curr_FIR; + reg [5:0] DF_edge_counter_FIR; + reg [1:0] one_edge_counter_FIR; + reg [7:0] p0_FIR,p1_FIR,p2_FIR,p3_FIR; + reg [7:0] q0_FIR,q1_FIR,q2_FIR,q3_FIR; + always @ (posedge gclk_DF or negedge reset_n) + if (reset_n == 1'b0) + begin + p2_m_p0_less_beta_FIR <= 0; q2_m_q0_less_beta_FIR <= 0; + p0_m_q0_less_alpha_shift_FIR <= 0; + bs_curr_FIR <= 0; + lumaEdgeFlag_FIR <= 0; chromaEdgeFlag_FIR <= 0; + DF_edge_counter_FIR <= 6'd48; one_edge_counter_FIR <= 2'd3; + p0_FIR <= 0; p1_FIR <= 0; p2_FIR <= 0; p3_FIR <= 0; + q0_FIR <= 0; q1_FIR <= 0; q2_FIR <= 0; q3_FIR <= 0; + end + else + begin + p2_m_p0_less_beta_FIR <= p2_m_p0_less_beta; + q2_m_q0_less_beta_FIR <= q2_m_q0_less_beta; + p0_m_q0_less_alpha_shift_FIR <= p0_m_q0_less_alpha_shift; + bs_curr_FIR <= bs_curr_PRE; + lumaEdgeFlag_FIR <= lumaEdgeFlag_PRE; chromaEdgeFlag_FIR <= chromaEdgeFlag_PRE; + DF_edge_counter_FIR <= DF_edge_counter_PRE; one_edge_counter_FIR <= one_edge_counter_PRE; + p0_FIR <= p0_PRE; p1_FIR <= p1_PRE; p2_FIR <= p2_PRE; p3_FIR <= p3_PRE; + q0_FIR <= q0_PRE; q1_FIR <= q1_PRE; q2_FIR <= q2_PRE; q3_FIR <= q3_PRE; + end + //--------------------------------------------------------------------- + //4.FIR: filtering + //--------------------------------------------------------------------- + reg [7:0] bs4_strong_FIR_p0,bs4_strong_FIR_p1,bs4_strong_FIR_p2,bs4_strong_FIR_p3; + reg [7:0] bs4_strong_FIR_q0,bs4_strong_FIR_q1,bs4_strong_FIR_q2,bs4_strong_FIR_q3; + wire [7:0] bs4_strong_FIR_p0_out,bs4_strong_FIR_p1_out,bs4_strong_FIR_p2_out; + wire [7:0] bs4_strong_FIR_q0_out,bs4_strong_FIR_q1_out,bs4_strong_FIR_q2_out; + bs4_strong_FIR bs4_strong_FIR ( + .p0(bs4_strong_FIR_p0),.p1(bs4_strong_FIR_p1),.p2(bs4_strong_FIR_p2),.p3(bs4_strong_FIR_p3), + .q0(bs4_strong_FIR_q0),.q1(bs4_strong_FIR_q1),.q2(bs4_strong_FIR_q2),.q3(bs4_strong_FIR_q3), + .p0_out(bs4_strong_FIR_p0_out),.p1_out(bs4_strong_FIR_p1_out),.p2_out(bs4_strong_FIR_p2_out), + .q0_out(bs4_strong_FIR_q0_out),.q1_out(bs4_strong_FIR_q1_out),.q2_out(bs4_strong_FIR_q2_out) + ); + reg [7:0] bs4_weak_FIR0_a,bs4_weak_FIR0_b,bs4_weak_FIR0_c; + reg [7:0] bs4_weak_FIR1_a,bs4_weak_FIR1_b,bs4_weak_FIR1_c; + wire [7:0] bs4_weak_FIR0_out,bs4_weak_FIR1_out; + bs4_weak_FIR bs4_weak_FIR0 (.a(bs4_weak_FIR0_a),.b(bs4_weak_FIR0_b),.c(bs4_weak_FIR0_c),.out(bs4_weak_FIR0_out)); + bs4_weak_FIR bs4_weak_FIR1 (.a(bs4_weak_FIR1_a),.b(bs4_weak_FIR1_b),.c(bs4_weak_FIR1_c),.out(bs4_weak_FIR1_out)); + // bs = 4 + always @ (bs_curr_FIR or lumaEdgeFlag_FIR or p0_m_q0_less_alpha_shift_FIR + or p2_m_p0_less_beta_FIR or q2_m_q0_less_beta_FIR + or p0_FIR or p1_FIR or p2_FIR or p3_FIR or q0_FIR or q1_FIR or q2_FIR or q3_FIR) + if (bs_curr_FIR == 3'd4 && lumaEdgeFlag_FIR == 1'b1 && p0_m_q0_less_alpha_shift_FIR + && (p2_m_p0_less_beta_FIR || q2_m_q0_less_beta_FIR)) + begin + bs4_strong_FIR_p0 <= p0_FIR; bs4_strong_FIR_p1 <= p1_FIR; + bs4_strong_FIR_p2 <= p2_FIR; bs4_strong_FIR_p3 <= p3_FIR; + bs4_strong_FIR_q0 <= q0_FIR; bs4_strong_FIR_q1 <= q1_FIR; + bs4_strong_FIR_q2 <= q2_FIR; bs4_strong_FIR_q3 <= q3_FIR; + end + else + begin + bs4_strong_FIR_p0 <= 0; bs4_strong_FIR_p1 <= 0; bs4_strong_FIR_p2 <= 0; bs4_strong_FIR_p3 <= 0; + bs4_strong_FIR_q0 <= 0; bs4_strong_FIR_q1 <= 0; bs4_strong_FIR_q2 <= 0; bs4_strong_FIR_q3 <= 0; + end + always @ (bs_curr_FIR or lumaEdgeFlag_FIR or chromaEdgeFlag_FIR + or p2_m_p0_less_beta_FIR or p0_m_q0_less_alpha_shift_FIR + or p1_FIR or p0_FIR or q1_FIR) + if (bs_curr_FIR == 3'd4 && lumaEdgeFlag_FIR == 1'b1) + begin + if (!p2_m_p0_less_beta_FIR || !p0_m_q0_less_alpha_shift_FIR) + begin + bs4_weak_FIR0_a <= p1_FIR; bs4_weak_FIR0_b <= p0_FIR; bs4_weak_FIR0_c <= q1_FIR; + end + else + begin + bs4_weak_FIR0_a <= 0; bs4_weak_FIR0_b <= 0; bs4_weak_FIR0_c <= 0; + end + end + else if (bs_curr_FIR == 3'd4 && chromaEdgeFlag_FIR == 1'b1) + begin + bs4_weak_FIR0_a <= p1_FIR; bs4_weak_FIR0_b <= p0_FIR; bs4_weak_FIR0_c <= q1_FIR; + end + else + begin + bs4_weak_FIR0_a <= 0; bs4_weak_FIR0_b <= 0; bs4_weak_FIR0_c <= 0; + end + always @ (bs_curr_FIR or lumaEdgeFlag_FIR or chromaEdgeFlag_FIR + or q2_m_q0_less_beta_FIR or p0_m_q0_less_alpha_shift_FIR + or q1_FIR or q0_FIR or p1_FIR) + if (bs_curr_FIR == 3'd4 && lumaEdgeFlag_FIR == 1'b1) + begin + if (!q2_m_q0_less_beta_FIR || !p0_m_q0_less_alpha_shift_FIR) + begin + bs4_weak_FIR1_a <= q1_FIR; bs4_weak_FIR1_b <= q0_FIR; bs4_weak_FIR1_c <= p1_FIR; + end + else + begin + bs4_weak_FIR1_a <= 0; bs4_weak_FIR1_b <= 0; bs4_weak_FIR1_c <= 0; + end + end + else if (bs_curr_FIR == 3'd4 && chromaEdgeFlag_FIR == 1'b1) + begin + bs4_weak_FIR1_a <= q1_FIR; bs4_weak_FIR1_b <= q0_FIR; bs4_weak_FIR1_c <= p1_FIR; + end + else + begin + bs4_weak_FIR1_a <= 0; bs4_weak_FIR1_b <= 0; bs4_weak_FIR1_c <= 0; + end + //bs = 1 ~ 3,for p0 and q0 filtering + wire [9:0] p0_MW_tmp,q0_MW_tmp; + wire [7:0] p0_MW_clipped,q0_MW_clipped; + assign p0_MW_tmp = (bs_curr_FIR != 0 && bs_curr_FIR != 3'd4)? ({2'b0,p0_FIR} + {{4{delta_0[5]}},delta_0}):0; + assign q0_MW_tmp = (bs_curr_FIR != 0 && bs_curr_FIR != 3'd4)? ({2'b0,q0_FIR} + + {~delta_0[5],~delta_0[5],~delta_0[5],~delta_0[5],~delta_0} + 1):0; + assign p0_MW_clipped = (p0_MW_tmp[9] == 1'b1)? 0:((p0_MW_tmp[8] == 1'b1)? 8'd255:p0_MW_tmp[7:0]); + assign q0_MW_clipped = (q0_MW_tmp[9] == 1'b1)? 0:((q0_MW_tmp[8] == 1'b1)? 8'd255:q0_MW_tmp[7:0]); + + // Pipelined parameters + reg [7:0] p0_MW,p1_MW,p2_MW,p3_MW; + reg [7:0] q0_MW,q1_MW,q2_MW,q3_MW; + always @ (posedge gclk_DF or negedge reset_n) + if (reset_n == 1'b0) + begin + p0_MW <= 0; p1_MW <= 0; p2_MW <= 0; + q0_MW <= 0; q1_MW <= 0; q2_MW <= 0; + end + else if (bs_curr_FIR == 3'd4) + begin + if (lumaEdgeFlag_FIR) + begin + p0_MW <= (p0_m_q0_less_alpha_shift_FIR && p2_m_p0_less_beta_FIR)? + bs4_strong_FIR_p0_out:bs4_weak_FIR0_out; + q0_MW <= (p0_m_q0_less_alpha_shift_FIR && q2_m_q0_less_beta_FIR)? + bs4_strong_FIR_q0_out:bs4_weak_FIR1_out; + p1_MW <= (p0_m_q0_less_alpha_shift_FIR && p2_m_p0_less_beta_FIR)? + bs4_strong_FIR_p1_out:p1_FIR; + q1_MW <= (p0_m_q0_less_alpha_shift_FIR && q2_m_q0_less_beta_FIR)? + bs4_strong_FIR_q1_out:q1_FIR; + p2_MW <= (p0_m_q0_less_alpha_shift_FIR && p2_m_p0_less_beta_FIR)? + bs4_strong_FIR_p2_out:p2_FIR; + q2_MW <= (p0_m_q0_less_alpha_shift_FIR && q2_m_q0_less_beta_FIR)? + bs4_strong_FIR_q2_out:q2_FIR; + end + else + begin + p0_MW <= bs4_weak_FIR0_out; q0_MW <= bs4_weak_FIR1_out; + p1_MW <= p1_FIR; q1_MW <= q1_FIR; + p2_MW <= p2_FIR; q2_MW <= q2_FIR; + end + end + else if (bs_curr_FIR != 0 && bs_curr_FIR != 3'd4) + begin + p0_MW <= p0_MW_clipped; + q0_MW <= q0_MW_clipped; + p1_MW <= (lumaEdgeFlag_FIR)? ((p2_m_p0_less_beta_FIR)? (p1_FIR + {delta_p1[5],delta_p1[5],delta_p1}):p1_FIR):p1_FIR; + q1_MW <= (lumaEdgeFlag_FIR)? ((q2_m_q0_less_beta_FIR)? (q1_FIR + {delta_q1[5],delta_q1[5],delta_q1}):q1_FIR):q1_FIR; + p2_MW <= p2_FIR; + q2_MW <= q2_FIR; + end + else + begin + p0_MW <= p0_FIR; p1_MW <= p1_FIR; p2_MW <= p2_FIR; + q0_MW <= q0_FIR; q1_MW <= q1_FIR; q2_MW <= q2_FIR; + end + + reg [2:0] bs_curr_MW; + reg [5:0] DF_edge_counter_MW; + reg [1:0] one_edge_counter_MW; + always @ (posedge gclk_DF or negedge reset_n) + if (reset_n == 1'b0) + begin + DF_edge_counter_MW <= 6'd48; one_edge_counter_MW <= 2'd3; + p3_MW <= 0; q3_MW <= 0; + bs_curr_MW <= 0; + end + else + begin + DF_edge_counter_MW <= DF_edge_counter_FIR; p3_MW <= p3_FIR; + one_edge_counter_MW <= one_edge_counter_FIR; q3_MW <= q3_FIR; + bs_curr_MW <= bs_curr_FIR; + end +endmodule + +module absolute (a,b,out); + input [7:0] a,b; + output [7:0] out; + + assign out = (a > b)? (a - b):(b - a); +endmodule + +module clip_to_c (delta,c,out); + input [8:0] delta; + input [4:0] c; // 0 ~ 25, [4:0] + output [5:0] out; // -25 ~ 25, [5:0] + reg [5:0] out; + + wire [5:0] neg_c; //-25 ~ 25,[5:0] + assign neg_c = {1'b1,~c} + 1; + + always @ (delta or c or neg_c) + if (delta[8] == 1'b0) //delta is positive + out <= (delta[7:0] > {3'b0,c})? {1'b0,c}:delta[5:0]; + else //delta is negtive + out <= (delta[7:0] < {2'b11,neg_c})? {1'b1,neg_c}:delta[5:0]; +endmodule + +module bs4_strong_FIR (p0,p1,p2,p3,q0,q1,q2,q3,p0_out,p1_out,p2_out,q0_out,q1_out,q2_out); + input [7:0] p0,p1,p2,p3,q0,q1,q2,q3; + output [7:0] p0_out,p1_out,p2_out,q0_out,q1_out,q2_out; + + wire [8:0] sum_p2p3,sum_p1p2,sum_p0q0,sum_p1q1,sum_q1q2,sum_q2q3; + assign sum_p2p3 = p2 + p3; + assign sum_p1p2 = p1 + p2; + assign sum_p0q0 = p0 + q0; + assign sum_p1q1 = p1 + q1; + assign sum_q1q2 = q1 + q2; + assign sum_q2q3 = q2 + q3; + + wire [9:0] sum_p2p3_x2,sum_q2q3_x2; + assign sum_p2p3_x2 = {sum_p2p3,1'b0}; + assign sum_q2q3_x2 = {sum_q2q3,1'b0}; + + wire [9:0] sum_0,sum_1,sum_2; + assign sum_0 = sum_p0q0 + sum_p1p2; + assign sum_1 = sum_p0q0 + sum_p1q1; + assign sum_2 = sum_p0q0 + sum_q1q2; + + wire [10:0] p0_tmp,p2_tmp,q0_tmp,q2_tmp; + assign p0_tmp = sum_0 + sum_1; + assign p2_tmp = sum_p2p3_x2 + sum_0; + assign q0_tmp = sum_1 + sum_2; + assign q2_tmp = sum_q2q3_x2 + sum_2; + + assign p0_out = (p0_tmp + 4) >> 3; + assign p1_out = (sum_0 + 2) >> 2; + assign p2_out = (p2_tmp + 4) >> 3; + assign q0_out = (q0_tmp + 4) >> 3; + assign q1_out = (sum_2 + 2) >> 2; + assign q2_out = (q2_tmp + 4) >> 3; +endmodule + +module bs4_weak_FIR (a,b,c,out); + input [7:0] a,b,c; + output [7:0] out; + + wire [8:0] a_x2; + assign a_x2 = {a,1'b0}; + + wire [8:0] sum_bc; + assign sum_bc = b + c; + + wire [9:0] out_tmp; + assign out_tmp = (a_x2 + sum_bc) + 2; + assign out = out_tmp[9:2]; +endmodule + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/DF_reg_ctrl.v b/demo_chip_rtl/rtl/nova/trunk/src/DF_reg_ctrl.v new file mode 100644 index 0000000..803874a --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/DF_reg_ctrl.v @@ -0,0 +1,335 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : DF_reg_ctrl.v +// Generated : Nov 27,2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// buffer buf0 ~ buf3 & transpose reg t0 ~ t1 control +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module DF_reg_ctrl (gclk_DF,reset_n,DF_edge_counter_MW,one_edge_counter_MW, + mb_num_h_DF,mb_num_v_DF,q0_MW,q1_MW,q2_MW,q3_MW,p0_MW,p1_MW,p2_MW,p3_MW, + buf0_0,buf0_1,buf0_2,buf0_3,buf1_0,buf1_1,buf1_2,buf1_3, + buf2_0,buf2_1,buf2_2,buf2_3,buf3_0,buf3_1,buf3_2,buf3_3, + t0_0,t0_1,t0_2,t0_3,t1_0,t1_1,t1_2,t1_3,t2_0,t2_1,t2_2,t2_3); + input gclk_DF,reset_n; + input [5:0] DF_edge_counter_MW; + input [1:0] one_edge_counter_MW; + input [3:0] mb_num_h_DF; + input [3:0] mb_num_v_DF; + input [7:0] q0_MW,q1_MW,q2_MW,q3_MW; + input [7:0] p0_MW,p1_MW,p2_MW,p3_MW; + + output [31:0] buf0_0,buf0_1,buf0_2,buf0_3; + output [31:0] buf1_0,buf1_1,buf1_2,buf1_3; + output [31:0] buf2_0,buf2_1,buf2_2,buf2_3; + output [31:0] buf3_0,buf3_1,buf3_2,buf3_3; + output [31:0] t0_0,t0_1,t0_2,t0_3; + output [31:0] t1_0,t1_1,t1_2,t1_3; + output [31:0] t2_0,t2_1,t2_2,t2_3; + + reg [31:0] buf0_0,buf0_1,buf0_2,buf0_3; + reg [31:0] buf1_0,buf1_1,buf1_2,buf1_3; + reg [31:0] buf2_0,buf2_1,buf2_2,buf2_3; + reg [31:0] buf3_0,buf3_1,buf3_2,buf3_3; + reg [31:0] t0_0,t0_1,t0_2,t0_3; + reg [31:0] t1_0,t1_1,t1_2,t1_3; + reg [31:0] t2_0,t2_1,t2_2,t2_3; + //------------------------------------------------------ + //buf0 + //------------------------------------------------------ + wire buf0_no_transpose; //buf0 updated without transpose + wire buf0_transpose; //buf0 updated after transpose + assign buf0_no_transpose = ( + DF_edge_counter_MW == 6'd0 || DF_edge_counter_MW == 6'd4 || DF_edge_counter_MW == 6'd6 || + DF_edge_counter_MW == 6'd12 || DF_edge_counter_MW == 6'd16 || DF_edge_counter_MW == 6'd20 || + DF_edge_counter_MW == 6'd22 || DF_edge_counter_MW == 6'd28 || DF_edge_counter_MW == 6'd32 || + DF_edge_counter_MW == 6'd36 || DF_edge_counter_MW == 6'd40 || DF_edge_counter_MW == 6'd44); + assign buf0_transpose = ( + DF_edge_counter_MW == 6'd1 || DF_edge_counter_MW == 6'd5 || DF_edge_counter_MW == 6'd10 || + DF_edge_counter_MW == 6'd14 || DF_edge_counter_MW == 6'd17 || DF_edge_counter_MW == 6'd26 || + DF_edge_counter_MW == 6'd30 || DF_edge_counter_MW == 6'd33 || DF_edge_counter_MW == 6'd38 || + DF_edge_counter_MW == 6'd41 || DF_edge_counter_MW == 6'd46); + + always @ (posedge gclk_DF or negedge reset_n) + if (reset_n == 1'b0) + begin + buf0_0 <= 0; buf0_1 <= 0; buf0_2 <= 0; buf0_3 <= 0; + end + //no transpose update,always "q" position (right or down of the edge to be filtered) + else if (buf0_no_transpose) + case (one_edge_counter_MW) + 2'd0:buf0_0 <= {q3_MW,q2_MW,q1_MW,q0_MW}; + 2'd1:buf0_1 <= {q3_MW,q2_MW,q1_MW,q0_MW}; + 2'd2:buf0_2 <= {q3_MW,q2_MW,q1_MW,q0_MW}; + 2'd3:buf0_3 <= {q3_MW,q2_MW,q1_MW,q0_MW}; + endcase + //transpose update,always "p" position (left or up of the edge to be filtered) + else if (buf0_transpose) + case (one_edge_counter_MW) + 2'd0:begin buf0_0[7:0] <= p3_MW; buf0_1[7:0] <= p2_MW; + buf0_2[7:0] <= p1_MW; buf0_3[7:0] <= p0_MW; end + 2'd1:begin buf0_0[15:8] <= p3_MW; buf0_1[15:8] <= p2_MW; + buf0_2[15:8] <= p1_MW; buf0_3[15:8] <= p0_MW; end + 2'd2:begin buf0_0[23:16] <= p3_MW; buf0_1[23:16] <= p2_MW; + buf0_2[23:16] <= p1_MW; buf0_3[23:16] <= p0_MW; end + 2'd3:begin buf0_0[31:24] <= p3_MW; buf0_1[31:24] <= p2_MW; + buf0_2[31:24] <= p1_MW; buf0_3[31:24] <= p0_MW; end + endcase + //------------------------------------------------------ + //buf1 + //------------------------------------------------------ + wire buf1_no_transpose; //buf1 updated without transpose + wire buf1_transpose; //buf1 updated after transpose + wire buf1_transpose_p; //buf1 transpose and buf1 stores "p" position pixels + assign buf1_no_transpose = ( + DF_edge_counter_MW == 6'd1 || DF_edge_counter_MW == 6'd8 || DF_edge_counter_MW == 6'd13 || + DF_edge_counter_MW == 6'd17 || DF_edge_counter_MW == 6'd24 || DF_edge_counter_MW == 6'd29 || + DF_edge_counter_MW == 6'd37 || DF_edge_counter_MW == 6'd45); + assign buf1_transpose = ( + DF_edge_counter_MW == 6'd6 || DF_edge_counter_MW == 6'd10 || DF_edge_counter_MW == 6'd22 || + DF_edge_counter_MW == 6'd26 || DF_edge_counter_MW == 6'd33 || DF_edge_counter_MW == 6'd41); + assign buf1_transpose_p = (DF_edge_counter_MW == 6'd6 || DF_edge_counter_MW == 6'd9 + || DF_edge_counter_MW == 6'd22); + always @ (posedge gclk_DF or negedge reset_n) + if (reset_n == 1'b0) + begin + buf1_0 <= 0; buf1_1 <= 0; buf1_2 <= 0; buf1_3 <= 0; + end + //no transpose update,always "q" position (right or down of the edge to be filtered) + else if (buf1_no_transpose) + case (one_edge_counter_MW) + 2'd0:buf1_0 <= {q3_MW,q2_MW,q1_MW,q0_MW}; + 2'd1:buf1_1 <= {q3_MW,q2_MW,q1_MW,q0_MW}; + 2'd2:buf1_2 <= {q3_MW,q2_MW,q1_MW,q0_MW}; + 2'd3:buf1_3 <= {q3_MW,q2_MW,q1_MW,q0_MW}; + endcase + //transpose update,"p":6/9/22,"q":10,26,33,41 + else if (buf1_transpose) + begin + if (buf1_transpose_p) // edge 6,22 "p" + case (one_edge_counter_MW) + 2'd0:begin buf1_0[7:0] <= p3_MW; buf1_1[7:0] <= p2_MW; + buf1_2[7:0] <= p1_MW; buf1_3[7:0] <= p0_MW; end + 2'd1:begin buf1_0[15:8] <= p3_MW; buf1_1[15:8] <= p2_MW; + buf1_2[15:8] <= p1_MW; buf1_3[15:8] <= p0_MW; end + 2'd2:begin buf1_0[23:16] <= p3_MW; buf1_1[23:16] <= p2_MW; + buf1_2[23:16] <= p1_MW; buf1_3[23:16] <= p0_MW; end + 2'd3:begin buf1_0[31:24] <= p3_MW; buf1_1[31:24] <= p2_MW; + buf1_2[31:24] <= p1_MW; buf1_3[31:24] <= p0_MW; end + endcase + else //edge 10,26,33,41 "q" + case (one_edge_counter_MW) + 2'd0:begin buf1_0[7:0] <= q0_MW; buf1_1[7:0] <= q1_MW; + buf1_2[7:0] <= q2_MW; buf1_3[7:0] <= q3_MW; end + 2'd1:begin buf1_0[15:8] <= q0_MW; buf1_1[15:8] <= q1_MW; + buf1_2[15:8] <= q2_MW; buf1_3[15:8] <= q3_MW; end + 2'd2:begin buf1_0[23:16] <= q0_MW; buf1_1[23:16] <= q1_MW; + buf1_2[23:16] <= q2_MW; buf1_3[23:16] <= q3_MW; end + 2'd3:begin buf1_0[31:24] <= q0_MW; buf1_1[31:24] <= q1_MW; + buf1_2[31:24] <= q2_MW; buf1_3[31:24] <= q3_MW; end + endcase + end + //------------------------------------------------------ + //buf2 + //------------------------------------------------------ + wire buf2_no_transpose; //buf2 updated without transpose + wire buf2_transpose; //buf2 updated after transpose + wire buf2_transpose_p; //buf2 transpose and buf2 stores "p" position pixels + assign buf2_no_transpose = ( + DF_edge_counter_MW == 6'd2 || DF_edge_counter_MW == 6'd7 || DF_edge_counter_MW == 6'd18 || + DF_edge_counter_MW == 6'd23 || DF_edge_counter_MW == 6'd34 || DF_edge_counter_MW == 6'd42); + assign buf2_transpose = ( + DF_edge_counter_MW == 6'd3 || DF_edge_counter_MW == 6'd11 || DF_edge_counter_MW == 6'd19 || + DF_edge_counter_MW == 6'd21 || DF_edge_counter_MW == 6'd27 || DF_edge_counter_MW == 6'd30 || + DF_edge_counter_MW == 6'd35 || DF_edge_counter_MW == 6'd38 || DF_edge_counter_MW == 6'd43 || + DF_edge_counter_MW == 6'd46); + assign buf2_transpose_p = (DF_edge_counter_MW == 6'd3 || DF_edge_counter_MW == 6'd11 + || DF_edge_counter_MW == 6'd19 || DF_edge_counter_MW == 6'd27 + || DF_edge_counter_MW == 6'd35 || DF_edge_counter_MW == 6'd43); + always @ (posedge gclk_DF or negedge reset_n) + if (reset_n == 1'b0) + begin + buf2_0 <= 0; buf2_1 <= 0; buf2_2 <= 0; buf2_3 <= 0; + end + //no transpose update,always "q" position (right or down of the edge to be filtered) + else if (buf2_no_transpose) + case (one_edge_counter_MW) + 2'd0:buf2_0 <= {q3_MW,q2_MW,q1_MW,q0_MW}; + 2'd1:buf2_1 <= {q3_MW,q2_MW,q1_MW,q0_MW}; + 2'd2:buf2_2 <= {q3_MW,q2_MW,q1_MW,q0_MW}; + 2'd3:buf2_3 <= {q3_MW,q2_MW,q1_MW,q0_MW}; + endcase + //transpose update,"p":3,11,19,27,35,43 "q":21,30,38,46 + else if (buf2_transpose) + begin + if (buf2_transpose_p) //"p":3,11,19,27,35,43 + case (one_edge_counter_MW) + 2'd0:begin buf2_0[7:0] <= p3_MW; buf2_1[7:0] <= p2_MW; + buf2_2[7:0] <= p1_MW; buf2_3[7:0] <= p0_MW; end + 2'd1:begin buf2_0[15:8] <= p3_MW; buf2_1[15:8] <= p2_MW; + buf2_2[15:8] <= p1_MW; buf2_3[15:8] <= p0_MW; end + 2'd2:begin buf2_0[23:16] <= p3_MW; buf2_1[23:16] <= p2_MW; + buf2_2[23:16] <= p1_MW; buf2_3[23:16] <= p0_MW; end + 2'd3:begin buf2_0[31:24] <= p3_MW; buf2_1[31:24] <= p2_MW; + buf2_2[31:24] <= p1_MW; buf2_3[31:24] <= p0_MW; end + endcase + else //"q":21,30,38,46 + case (one_edge_counter_MW) + 2'd0:begin buf2_0[7:0] <= q0_MW; buf2_1[7:0] <= q1_MW; + buf2_2[7:0] <= q2_MW; buf2_3[7:0] <= q3_MW; end + 2'd1:begin buf2_0[15:8] <= q0_MW; buf2_1[15:8] <= q1_MW; + buf2_2[15:8] <= q2_MW; buf2_3[15:8] <= q3_MW; end + 2'd2:begin buf2_0[23:16] <= q0_MW; buf2_1[23:16] <= q1_MW; + buf2_2[23:16] <= q2_MW; buf2_3[23:16] <= q3_MW; end + 2'd3:begin buf2_0[31:24] <= q0_MW; buf2_1[31:24] <= q1_MW; + buf2_2[31:24] <= q2_MW; buf2_3[31:24] <= q3_MW; end + endcase + end + //------------------------------------------------------ + //buf3 + //------------------------------------------------------ + wire buf3_no_transpose; //buf3 updated without transpose + wire buf3_transpose; //buf3 updated after transpose + wire buf3_transpose_p; //buf3 transpose and buf1 stores "p" position pixels + assign buf3_no_transpose = (DF_edge_counter_MW == 6'd3 || DF_edge_counter_MW == 6'd19); + assign buf3_transpose = ( DF_edge_counter_MW == 6'd7 || + DF_edge_counter_MW == 6'd11 || DF_edge_counter_MW == 6'd23 || DF_edge_counter_MW == 6'd27 || + DF_edge_counter_MW == 6'd25 || DF_edge_counter_MW == 6'd35 || DF_edge_counter_MW == 6'd43); + assign buf3_transpose_p = (DF_edge_counter_MW == 6'd7 || DF_edge_counter_MW == 6'd23); + always @ (posedge gclk_DF or negedge reset_n) + if (reset_n == 1'b0) + begin + buf3_0 <= 0; buf3_1 <= 0; buf3_2 <= 0; buf3_3 <= 0; + end + //no transpose update,always "q" position (right or down of the edge to be filtered) + else if (buf3_no_transpose) + case (one_edge_counter_MW) + 2'd0:buf3_0 <= {q3_MW,q2_MW,q1_MW,q0_MW}; + 2'd1:buf3_1 <= {q3_MW,q2_MW,q1_MW,q0_MW}; + 2'd2:buf3_2 <= {q3_MW,q2_MW,q1_MW,q0_MW}; + 2'd3:buf3_3 <= {q3_MW,q2_MW,q1_MW,q0_MW}; + endcase + //transpose update,"p":7,23 "q":11,25,27,35,43 + else if (buf3_transpose) + begin + if (buf3_transpose_p) //"p":7,23 + case (one_edge_counter_MW) + 2'd0:begin buf3_0[7:0] <= p3_MW; buf3_1[7:0] <= p2_MW; + buf3_2[7:0] <= p1_MW; buf3_3[7:0] <= p0_MW; end + 2'd1:begin buf3_0[15:8] <= p3_MW; buf3_1[15:8] <= p2_MW; + buf3_2[15:8] <= p1_MW; buf3_3[15:8] <= p0_MW; end + 2'd2:begin buf3_0[23:16] <= p3_MW; buf3_1[23:16] <= p2_MW; + buf3_2[23:16] <= p1_MW; buf3_3[23:16] <= p0_MW; end + 2'd3:begin buf3_0[31:24] <= p3_MW; buf3_1[31:24] <= p2_MW; + buf3_2[31:24] <= p1_MW; buf3_3[31:24] <= p0_MW; end + endcase + else //"q":11,25,35,43 + case (one_edge_counter_MW) + 2'd0:begin buf3_0[7:0] <= q0_MW; buf3_1[7:0] <= q1_MW; + buf3_2[7:0] <= q2_MW; buf3_3[7:0] <= q3_MW; end + 2'd1:begin buf3_0[15:8] <= q0_MW; buf3_1[15:8] <= q1_MW; + buf3_2[15:8] <= q2_MW; buf3_3[15:8] <= q3_MW; end + 2'd2:begin buf3_0[23:16] <= q0_MW; buf3_1[23:16] <= q1_MW; + buf3_2[23:16] <= q2_MW; buf3_3[23:16] <= q3_MW; end + 2'd3:begin buf3_0[31:24] <= q0_MW; buf3_1[31:24] <= q1_MW; + buf3_2[31:24] <= q2_MW; buf3_3[31:24] <= q3_MW; end + endcase + end + //------------------------------------------------------ + //T0:always updated after transpose,always "p" position + //------------------------------------------------------ + wire t0_transpose; //t0 updated after transpose + assign t0_transpose = ( + DF_edge_counter_MW == 6'd4 || DF_edge_counter_MW == 6'd8 || DF_edge_counter_MW == 6'd12 || DF_edge_counter_MW == 6'd36 || + DF_edge_counter_MW == 6'd44 || DF_edge_counter_MW == 6'd15 || DF_edge_counter_MW == 6'd20 || DF_edge_counter_MW == 6'd24 || + DF_edge_counter_MW == 6'd28 || DF_edge_counter_MW == 6'd31 || DF_edge_counter_MW == 6'd39 || DF_edge_counter_MW == 6'd47); + + always @ (posedge gclk_DF or negedge reset_n) + if (reset_n == 1'b0) + begin + t0_0 <= 0; t0_1 <= 0; t0_2 <= 0; t0_3 <= 0; + end + //always transpose update for "p" position + else if (t0_transpose) + case (one_edge_counter_MW) + 2'd0:begin t0_0[7:0] <= p3_MW; t0_1[7:0] <= p2_MW; + t0_2[7:0] <= p1_MW; t0_3[7:0] <= p0_MW; end + 2'd1:begin t0_0[15:8] <= p3_MW; t0_1[15:8] <= p2_MW; + t0_2[15:8] <= p1_MW; t0_3[15:8] <= p0_MW; end + 2'd2:begin t0_0[23:16] <= p3_MW; t0_1[23:16] <= p2_MW; + t0_2[23:16] <= p1_MW; t0_3[23:16] <= p0_MW; end + 2'd3:begin t0_0[31:24] <= p3_MW; t0_1[31:24] <= p2_MW; + t0_2[31:24] <= p1_MW; t0_3[31:24] <= p0_MW; end + endcase + //------------------------------------------------------ + //T1:always updated after transpose + //------------------------------------------------------ + wire t1_transpose; //t1 updated after transpose + wire t1_transpose_q; //t1 transpose and t1 stores "q" position pixels + assign t1_transpose = ( + DF_edge_counter_MW == 6'd13 || DF_edge_counter_MW == 6'd37 || DF_edge_counter_MW == 6'd45 || DF_edge_counter_MW == 6'd9 || + DF_edge_counter_MW == 6'd21 || DF_edge_counter_MW == 6'd25 || DF_edge_counter_MW == 6'd29 || DF_edge_counter_MW == 6'd31 || + DF_edge_counter_MW == 6'd39 || DF_edge_counter_MW == 6'd47); + + assign t1_transpose_q = (DF_edge_counter_MW == 6'd31 || DF_edge_counter_MW == 6'd39 || + DF_edge_counter_MW == 6'd47); + always @ (posedge gclk_DF or negedge reset_n) + if (reset_n == 1'b0) + begin + t1_0 <= 0; t1_1 <= 0; t1_2 <= 0; t1_3 <= 0; + end + else if (t1_transpose && !t1_transpose_q) //t1 transpose "p" + case (one_edge_counter_MW) + 2'd0:begin t1_0[7:0] <= p3_MW; t1_1[7:0] <= p2_MW; + t1_2[7:0] <= p1_MW; t1_3[7:0] <= p0_MW; end + 2'd1:begin t1_0[15:8] <= p3_MW; t1_1[15:8] <= p2_MW; + t1_2[15:8] <= p1_MW; t1_3[15:8] <= p0_MW; end + 2'd2:begin t1_0[23:16] <= p3_MW; t1_1[23:16] <= p2_MW; + t1_2[23:16] <= p1_MW; t1_3[23:16] <= p0_MW; end + 2'd3:begin t1_0[31:24] <= p3_MW; t1_1[31:24] <= p2_MW; + t1_2[31:24] <= p1_MW; t1_3[31:24] <= p0_MW; end + endcase + else if (t1_transpose) //t1 transpose "q" + case (one_edge_counter_MW) + 2'd0:begin t1_0[7:0] <= q0_MW; t1_1[7:0] <= q1_MW; + t1_2[7:0] <= q2_MW; t1_3[7:0] <= q3_MW; end + 2'd1:begin t1_0[15:8] <= q0_MW; t1_1[15:8] <= q1_MW; + t1_2[15:8] <= q2_MW; t1_3[15:8] <= q3_MW; end + 2'd2:begin t1_0[23:16] <= q0_MW; t1_1[23:16] <= q1_MW; + t1_2[23:16] <= q2_MW; t1_3[23:16] <= q3_MW; end + 2'd3:begin t1_0[31:24] <= q0_MW; t1_1[31:24] <= q1_MW; + t1_2[31:24] <= q2_MW; t1_3[31:24] <= q3_MW; end + endcase + //-------------------------------------------------------------------- + //T2:only used after filter edge 18/34/42 to update mbAddrB of left MB + //-------------------------------------------------------------------- + wire t2_wr; + assign t2_wr = ((mb_num_h_DF != 0 && mb_num_v_DF != 4'd8) && + (DF_edge_counter_MW == 6'd18 || DF_edge_counter_MW == 6'd34 || DF_edge_counter_MW == 6'd42)); + always @ (posedge gclk_DF or negedge reset_n) + if (reset_n == 1'b0) + begin + t2_0 <= 0; t2_1 <= 0; t2_2 <= 0; t2_3 <= 0; + end + else if (t2_wr) + case (one_edge_counter_MW) + 2'd0:begin t2_0[7:0] <= p3_MW; t2_1[7:0] <= p2_MW; + t2_2[7:0] <= p1_MW; t2_3[7:0] <= p0_MW; end + 2'd1:begin t2_0[15:8] <= p3_MW; t2_1[15:8] <= p2_MW; + t2_2[15:8] <= p1_MW; t2_3[15:8] <= p0_MW; end + 2'd2:begin t2_0[23:16] <= p3_MW; t2_1[23:16] <= p2_MW; + t2_2[23:16] <= p1_MW; t2_3[23:16] <= p0_MW; end + 2'd3:begin t2_0[31:24] <= p3_MW; t2_1[31:24] <= p2_MW; + t2_2[31:24] <= p1_MW; t2_3[31:24] <= p0_MW; end + endcase +endmodule + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/DF_top.v b/demo_chip_rtl/rtl/nova/trunk/src/DF_top.v new file mode 100644 index 0000000..bae31b1 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/DF_top.v @@ -0,0 +1,205 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : DF_top.v +// Generated : Dec 30, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Top module of deblocking filter +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module DF_top (clk,reset_n,gclk_DF,gclk_end_of_MB_DEC,gclk_DF_mbAddrA_RF,gclk_DF_mbAddrB_RAM, + end_of_BS_DEC,disable_DF,mb_num_h,mb_num_v, + bs_V0,bs_V1,bs_V2,bs_V3,bs_H0,bs_H1,bs_H2,bs_H3, + QPy,QPc,slice_alpha_c0_offset_div2,slice_beta_offset_div2, + blk4x4_sum_counter,blk4x4_rec_counter_2_raster_order,rec_DF_RAM_dout, + blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out, + + DF_duration,end_of_MB_DF,DF_edge_counter_MR,one_edge_counter_MR, + DF_mbAddrA_RF_rd,DF_mbAddrA_RF_wr,DF_mbAddrB_RAM_rd,DF_mbAddrB_RAM_wr, + dis_frame_RAM_wr,dis_frame_RAM_wr_addr,dis_frame_RAM_din); + input clk; + input gclk_DF; + input gclk_end_of_MB_DEC; + input gclk_DF_mbAddrA_RF; + input gclk_DF_mbAddrB_RAM; + input reset_n; + input end_of_BS_DEC; + input disable_DF; + input [3:0] mb_num_h; + input [3:0] mb_num_v; + input [11:0] bs_V0,bs_V1,bs_V2,bs_V3; + input [11:0] bs_H0,bs_H1,bs_H2,bs_H3; + input [5:0] QPy,QPc; + input [3:0] slice_alpha_c0_offset_div2; + input [3:0] slice_beta_offset_div2; + input [31:0] rec_DF_RAM_dout; + input [2:0] blk4x4_sum_counter; + input [4:0] blk4x4_rec_counter_2_raster_order; + input [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out; + + output DF_duration; + output end_of_MB_DF; + output [5:0] DF_edge_counter_MR; + output [1:0] one_edge_counter_MR; + output DF_mbAddrA_RF_rd,DF_mbAddrA_RF_wr; + output DF_mbAddrB_RAM_rd,DF_mbAddrB_RAM_wr; + output dis_frame_RAM_wr; + output [13:0] dis_frame_RAM_wr_addr; + output [31:0] dis_frame_RAM_din; + + wire end_of_MB_DF; + wire end_of_lastMB_DF; + wire [3:0] mb_num_h_DF; + wire [3:0] mb_num_v_DF; + wire [5:0] DF_edge_counter_MR,DF_edge_counter_MW; + wire [1:0] one_edge_counter_MR,one_edge_counter_MW; + wire [2:0] bs_curr_MR,bs_curr_MW; + wire [7:0] q0_MW,q1_MW,q2_MW,q3_MW; + wire [7:0] p0_MW,p1_MW,p2_MW,p3_MW; + wire [31:0] buf0_0,buf0_1,buf0_2,buf0_3; + wire [31:0] buf1_0,buf1_1,buf1_2,buf1_3; + wire [31:0] buf2_0,buf2_1,buf2_2,buf2_3; + wire [31:0] buf3_0,buf3_1,buf3_2,buf3_3; + wire [31:0] t0_0,t0_1,t0_2,t0_3; + wire [31:0] t1_0,t1_1,t1_2,t1_3; + wire [31:0] t2_0,t2_1,t2_2,t2_3; + wire DF_mbAddrA_RF_rd; + wire DF_mbAddrA_RF_wr; + wire [4:0] DF_mbAddrA_RF_rd_addr; + wire [4:0] DF_mbAddrA_RF_wr_addr; + wire [31:0] DF_mbAddrA_RF_din; + wire [31:0] DF_mbAddrA_RF_dout; + wire DF_mbAddrB_RAM_rd; + wire DF_mbAddrB_RAM_wr; + wire [8:0] DF_mbAddrB_RAM_addr; + wire [31:0] DF_mbAddrB_RAM_din; + wire [31:0] DF_mbAddrB_RAM_dout; + + DF_pipeline DF_pipeline ( + .clk(clk), + .gclk_DF(gclk_DF), + .gclk_end_of_MB_DEC(gclk_end_of_MB_DEC), + .reset_n(reset_n), + .disable_DF(disable_DF), + .end_of_BS_DEC(end_of_BS_DEC), + .end_of_MB_DF(end_of_MB_DF), + .end_of_lastMB_DF(end_of_lastMB_DF), + .bs_V0(bs_V0),.bs_V1(bs_V1),.bs_V2(bs_V2),.bs_V3(bs_V3), + .bs_H0(bs_H0),.bs_H1(bs_H1),.bs_H2(bs_H2),.bs_H3(bs_H3), + .QPy(QPy), + .QPc(QPc), + .slice_alpha_c0_offset_div2(slice_alpha_c0_offset_div2), + .slice_beta_offset_div2(slice_beta_offset_div2), + .DF_mbAddrA_RF_dout(DF_mbAddrA_RF_dout), + .DF_mbAddrB_RAM_dout(DF_mbAddrB_RAM_dout), + .rec_DF_RAM_dout(rec_DF_RAM_dout), + .buf0_0(buf0_0),.buf0_1(buf0_1),.buf0_2(buf0_2),.buf0_3(buf0_3), + .buf1_0(buf1_0),.buf1_1(buf1_1),.buf1_2(buf1_2),.buf1_3(buf1_3), + .buf2_0(buf2_0),.buf2_1(buf2_1),.buf2_2(buf2_2),.buf2_3(buf2_3), + .buf3_0(buf3_0),.buf3_1(buf3_1),.buf3_2(buf3_2),.buf3_3(buf3_3), + + .DF_duration(DF_duration), + .DF_edge_counter_MR(DF_edge_counter_MR), + .DF_edge_counter_MW(DF_edge_counter_MW), + .one_edge_counter_MR(one_edge_counter_MR), + .one_edge_counter_MW(one_edge_counter_MW), + .bs_curr_MR(bs_curr_MR), + .bs_curr_MW(bs_curr_MW), + .q0_MW(q0_MW),.q1_MW(q1_MW),.q2_MW(q2_MW),.q3_MW(q3_MW), + .p0_MW(p0_MW),.p1_MW(p1_MW),.p2_MW(p2_MW),.p3_MW(p3_MW) + ); + DF_reg_ctrl DF_reg_ctrl ( + .gclk_DF(gclk_DF), + .reset_n(reset_n), + .DF_edge_counter_MW(DF_edge_counter_MW), + .one_edge_counter_MW(one_edge_counter_MW), + .mb_num_h_DF(mb_num_h_DF), + .mb_num_v_DF(mb_num_v_DF), + + .q0_MW(q0_MW),.q1_MW(q1_MW),.q2_MW(q2_MW),.q3_MW(q3_MW), + .p0_MW(p0_MW),.p1_MW(p1_MW),.p2_MW(p2_MW),.p3_MW(p3_MW), + .buf0_0(buf0_0),.buf0_1(buf0_1),.buf0_2(buf0_2),.buf0_3(buf0_3), + .buf1_0(buf1_0),.buf1_1(buf1_1),.buf1_2(buf1_2),.buf1_3(buf1_3), + .buf2_0(buf2_0),.buf2_1(buf2_1),.buf2_2(buf2_2),.buf2_3(buf2_3), + .buf3_0(buf3_0),.buf3_1(buf3_1),.buf3_2(buf3_2),.buf3_3(buf3_3), + .t0_0(t0_0),.t0_1(t0_1),.t0_2(t0_2),.t0_3(t0_3), + .t1_0(t1_0),.t1_1(t1_1),.t1_2(t1_2),.t1_3(t1_3), + .t2_0(t2_0),.t2_1(t2_1),.t2_2(t2_2),.t2_3(t2_3) + ); + + DF_mem_ctrl DF_mem_ctrl ( + .clk(clk), + .reset_n(reset_n), + .gclk_end_of_MB_DEC(gclk_end_of_MB_DEC), + .disable_DF(disable_DF), + .mb_num_h(mb_num_h), + .mb_num_v(mb_num_v), + .bs_curr_MR(bs_curr_MR), + .bs_curr_MW(bs_curr_MW), + .blk4x4_sum_counter(blk4x4_sum_counter), + .blk4x4_rec_counter_2_raster_order(blk4x4_rec_counter_2_raster_order), + .DF_edge_counter_MR(DF_edge_counter_MR), + .DF_edge_counter_MW(DF_edge_counter_MW), + .one_edge_counter_MR(one_edge_counter_MR), + .one_edge_counter_MW(one_edge_counter_MW), + .blk4x4_sum_PE0_out(blk4x4_sum_PE0_out), + .blk4x4_sum_PE1_out(blk4x4_sum_PE1_out), + .blk4x4_sum_PE2_out(blk4x4_sum_PE2_out), + .blk4x4_sum_PE3_out(blk4x4_sum_PE3_out), + .q0_MW(q0_MW),.q1_MW(q1_MW),.q2_MW(q2_MW),.q3_MW(q3_MW), + .p0_MW(p0_MW),.p1_MW(p1_MW),.p2_MW(p2_MW),.p3_MW(p3_MW), + .buf0_0(buf0_0),.buf0_1(buf0_1),.buf0_2(buf0_2),.buf0_3(buf0_3), + .buf2_0(buf2_0),.buf2_1(buf2_1),.buf2_2(buf2_2),.buf2_3(buf2_3), + .buf3_0(buf3_0),.buf3_1(buf3_1),.buf3_2(buf3_2),.buf3_3(buf3_3), + .t0_0(t0_0),.t0_1(t0_1),.t0_2(t0_2),.t0_3(t0_3), + .t1_0(t1_0),.t1_1(t1_1),.t1_2(t1_2),.t1_3(t1_3), + .t2_0(t2_0),.t2_1(t2_1),.t2_2(t2_2),.t2_3(t2_3), + + .mb_num_h_DF(mb_num_h_DF), + .mb_num_v_DF(mb_num_v_DF), + .end_of_MB_DF(end_of_MB_DF), + .end_of_lastMB_DF(end_of_lastMB_DF), + .DF_mbAddrA_RF_rd(DF_mbAddrA_RF_rd), + .DF_mbAddrA_RF_wr(DF_mbAddrA_RF_wr), + .DF_mbAddrA_RF_rd_addr(DF_mbAddrA_RF_rd_addr), + .DF_mbAddrA_RF_wr_addr(DF_mbAddrA_RF_wr_addr), + .DF_mbAddrA_RF_din(DF_mbAddrA_RF_din), + .DF_mbAddrB_RAM_rd(DF_mbAddrB_RAM_rd), + .DF_mbAddrB_RAM_wr(DF_mbAddrB_RAM_wr), + .DF_mbAddrB_RAM_addr(DF_mbAddrB_RAM_addr), + .DF_mbAddrB_RAM_din(DF_mbAddrB_RAM_din), + .dis_frame_RAM_wr(dis_frame_RAM_wr), + .dis_frame_RAM_wr_addr(dis_frame_RAM_wr_addr), + .dis_frame_RAM_din(dis_frame_RAM_din) + ); + ram_sync_1r_sync_1w # (`DF_mbAddrA_RAM_data_width,`DF_mbAddrA_RAM_data_depth) + DF_mbAddrA_RAM ( + .clk(gclk_DF_mbAddrA_RF), + .rst_n(reset_n), + .wr_n(~DF_mbAddrA_RF_wr), + .rd_n(~DF_mbAddrA_RF_rd), + .wr_addr(DF_mbAddrA_RF_wr_addr), + .rd_addr(DF_mbAddrA_RF_rd_addr), + .data_in(DF_mbAddrA_RF_din), + .data_out(DF_mbAddrA_RF_dout) + ); + ram_sync_1r_sync_1w # (`DF_mbAddrB_RAM_data_width,`DF_mbAddrB_RAM_data_depth) + DF_mbAddrB_RAM ( + .clk(gclk_DF_mbAddrB_RAM), + .rst_n(reset_n), + .wr_n(~DF_mbAddrB_RAM_wr), + .rd_n(~DF_mbAddrB_RAM_rd), + .wr_addr(DF_mbAddrB_RAM_addr), + .rd_addr(DF_mbAddrB_RAM_addr), + .data_in(DF_mbAddrB_RAM_din), + .data_out(DF_mbAddrB_RAM_dout) + ); +endmodule \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/IQIT.v b/demo_chip_rtl/rtl/nova/trunk/src/IQIT.v new file mode 100644 index 0000000..e6c3334 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/IQIT.v @@ -0,0 +1,850 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : IQIT.v +// Generated : June 18, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Decoding the residual information +// 1.The res_mb_bypass | DConly | allzero signals should be decoded first +// 2.For DC coefficients,IDCT --> rescale +// 3.For AC coefficients,rescale --> IDCT --> rounding +// 4.coeffLevel:zig-zag order +// OneD_output,TwoD_output,DC_output,rescale_output,rounding_output:raster-scan order +// 5.Input coeffLevel_ext_0 ~ 15 are 2's complement,but with zig-zag order +//------------------------------------------------------------------------------------------------- +// Revise log +// 1.March 27,2006 +// DC_output: 0 ~ 15:for luma DC, 0 ~ 3:for Chroma Cb DC, 4 ~ 7:for Chroma Cr DC +// 2.March 28,2006 +// 1)For Intra16x16ACLevel and chroma AC,the first coeff of IDCT is DC value, the following coeffLevel_ext_0 ~ 14 should be moved backward 1 space and coeffLevel_ext_15 is abandoned +// 2)There are some blocks which have zero DC coeff but non-zero AC coeff. Additional signals as res_LumaDCBlk_IsZero,res_ChromaDCBlk_Cb_IsZero,res_ChromaDCBlk_Cr_IsZero are added to deal with such special case +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module IQIT (clk,reset_n,TotalCoeff,blk4x4_rec_counter, + gclk_1D,gclk_2D,gclk_rescale,gclk_rounding, + residual_state,cavlc_decoder_state, + end_of_one_residual_block,end_of_NonZeroCoeff_CAVLC, + QPy,QPc,i4x4_CbCr, + coeffLevel_ext_0, coeffLevel_ext_1, coeffLevel_ext_2, coeffLevel_ext_3, + coeffLevel_ext_4, coeffLevel_ext_5, coeffLevel_ext_6, coeffLevel_ext_7, + coeffLevel_ext_8, coeffLevel_ext_9, coeffLevel_ext_10,coeffLevel_ext_11, + coeffLevel_ext_12,coeffLevel_ext_13,coeffLevel_ext_14,coeffLevel_ext_15, + + OneD_counter,TwoD_counter,rescale_counter,rounding_counter, + curr_DC_IsZero,curr_DC_scaled, + rounding_output_0,rounding_output_1,rounding_output_2,rounding_output_3, + rounding_output_4,rounding_output_5,rounding_output_6,rounding_output_7, + rounding_output_8,rounding_output_9,rounding_output_10,rounding_output_11, + rounding_output_12,rounding_output_13,rounding_output_14,rounding_output_15, + end_of_ACBlk4x4_IQIT,end_of_DCBlk_IQIT + ); + input clk,reset_n; + input [4:0] TotalCoeff; + input [4:0] blk4x4_rec_counter; + input gclk_1D; + input gclk_2D; + input gclk_rescale; + input gclk_rounding; + input [3:0] residual_state; + input [3:0] cavlc_decoder_state; + input end_of_one_residual_block; + input end_of_NonZeroCoeff_CAVLC; + input [5:0] QPy; + input [5:0] QPc; + input [1:0] i4x4_CbCr; + input [15:0] coeffLevel_ext_0, coeffLevel_ext_1, coeffLevel_ext_2, coeffLevel_ext_3; + input [15:0] coeffLevel_ext_4, coeffLevel_ext_5, coeffLevel_ext_6, coeffLevel_ext_7; + input [15:0] coeffLevel_ext_8, coeffLevel_ext_9, coeffLevel_ext_10,coeffLevel_ext_11; + input [15:0] coeffLevel_ext_12,coeffLevel_ext_13,coeffLevel_ext_14,coeffLevel_ext_15; + + + output [2:0] OneD_counter; + output [2:0] TwoD_counter; + output [2:0] rescale_counter; + output [2:0] rounding_counter; + output curr_DC_IsZero; + output [8:0] curr_DC_scaled; + output [8:0] rounding_output_0, rounding_output_1, rounding_output_2, rounding_output_3; + output [8:0] rounding_output_4, rounding_output_5, rounding_output_6, rounding_output_7; + output [8:0] rounding_output_8, rounding_output_9, rounding_output_10,rounding_output_11; + output [8:0] rounding_output_12,rounding_output_13,rounding_output_14,rounding_output_15; + output end_of_ACBlk4x4_IQIT; //end of IQIT of one blk4x4 AC + output end_of_DCBlk_IQIT; //end of IQIT of one blk4x4/blk2x2 DC + + reg [8:0] rounding_output_0, rounding_output_1, rounding_output_2, rounding_output_3; + reg [8:0] rounding_output_4, rounding_output_5, rounding_output_6, rounding_output_7; + reg [8:0] rounding_output_8, rounding_output_9, rounding_output_10,rounding_output_11; + reg [8:0] rounding_output_12,rounding_output_13,rounding_output_14,rounding_output_15; + + reg [2:0] OneD_counter; + reg [2:0] TwoD_counter; + reg [2:0] rescale_counter; + reg [2:0] rounding_counter; + reg [4:0] LevelScale_DC; + reg [4:0] LevelScale_AC [3:0]; + reg [15:0] butterfly_D0,butterfly_D1,butterfly_D2,butterfly_D3; + reg [15:0] mult0_a,mult1_a,mult2_a,mult3_a; + reg IsLeftShift; + reg [3:0] shift_len; + reg [15:0] OneD_output [15:0]; + reg [15:0] TwoD_output [3:0]; + reg [15:0] rescale_output [3:0]; + reg [15:0] DC_output [15:0]; + + wire IsHadamard; + wire [5:0] QP; + wire [2:0] QPmod6; + wire [3:0] QPdiv6; + wire [15:0] butterfly_F0,butterfly_F1,butterfly_F2,butterfly_F3; + wire [4:0] LevelScale [3:0]; + wire [15:0] product0,product1,product2,product3; + wire [15:0] shift_output0,shift_output1,shift_output2,shift_output3; + wire [15:0] before_rounding0,before_rounding1,before_rounding2,before_rounding3; + wire [9:0] rounding_sum0,rounding_sum1,rounding_sum2,rounding_sum3; + + //----------------------------------------------------------------------------------- + // Zero-block-aware decoding + //----------------------------------------------------------------------------------- + //Whether DC block is zero + reg res_LumaDCBlk_IsZero; + reg res_ChromaDCBlk_Cb_IsZero; + reg res_ChromaDCBlk_Cr_IsZero; + + always @ (posedge clk) + if (reset_n == 1'b0) + begin + res_LumaDCBlk_IsZero <= 1'b0; + res_ChromaDCBlk_Cb_IsZero <= 1'b0; + res_ChromaDCBlk_Cr_IsZero <= 1'b0; + end + else if (cavlc_decoder_state == `NumCoeffTrailingOnes_LUT) + begin + if (residual_state == `Intra16x16DCLevel_s) + res_LumaDCBlk_IsZero <= (TotalCoeff == 0)? 1'b1:1'b0; + if (residual_state == `ChromaDCLevel_Cb_s) + res_ChromaDCBlk_Cb_IsZero <= (TotalCoeff == 0)? 1'b1:1'b0; + if (residual_state == `ChromaDCLevel_Cr_s) + res_ChromaDCBlk_Cr_IsZero <= (TotalCoeff == 0)? 1'b1:1'b0; + end + + //Whether current DC from DC_output[15:0] is zero + //If whole DC block are all zeros or current single DC is zero,curr_DC is assigned 0 + //If current blk4x4 doesn't need DC (e.g. LumaLevel_s), curr_DC is also assigned 0 + reg [15:0] curr_DC; + reg [15:0] curr_DC_reg; + always @ (posedge clk) + if (reset_n == 1'b0) + curr_DC_reg <= 0; + else + curr_DC_reg <= curr_DC; + + always @ (residual_state or TotalCoeff or blk4x4_rec_counter or end_of_one_residual_block + or res_LumaDCBlk_IsZero or res_ChromaDCBlk_Cb_IsZero or res_ChromaDCBlk_Cr_IsZero or curr_DC_reg + or DC_output[0] or DC_output[1] or DC_output[2] or DC_output[3] + or DC_output[4] or DC_output[5] or DC_output[6] or DC_output[7] + or DC_output[8] or DC_output[9] or DC_output[10] or DC_output[11] + or DC_output[12] or DC_output[13] or DC_output[14] or DC_output[15]) + if (residual_state == `Intra16x16ACLevel_0_s || (residual_state == `Intra16x16ACLevel_s && (end_of_one_residual_block && TotalCoeff == 0))) + begin + if (res_LumaDCBlk_IsZero == 1) + curr_DC <= 0; + else + case (blk4x4_rec_counter) + 0 :curr_DC <= DC_output[0]; 1 :curr_DC <= DC_output[1]; + 2 :curr_DC <= DC_output[2]; 3 :curr_DC <= DC_output[3]; + 4 :curr_DC <= DC_output[4]; 5 :curr_DC <= DC_output[5]; + 6 :curr_DC <= DC_output[6]; 7 :curr_DC <= DC_output[7]; + 8 :curr_DC <= DC_output[8]; 9 :curr_DC <= DC_output[9]; + 10:curr_DC <= DC_output[10];11:curr_DC <= DC_output[11]; + 12:curr_DC <= DC_output[12];13:curr_DC <= DC_output[13]; + 14:curr_DC <= DC_output[14];15:curr_DC <= DC_output[15]; + default:curr_DC <= curr_DC_reg; + endcase + end + else if (residual_state == `ChromaACLevel_0_s || ((residual_state == `ChromaACLevel_Cb_s + || residual_state == `ChromaACLevel_Cr_s) && (end_of_one_residual_block && TotalCoeff == 0))) + begin + if (blk4x4_rec_counter < 20) //Cb + begin + if (res_ChromaDCBlk_Cb_IsZero == 1'b1) + curr_DC <= 0; + else + case (blk4x4_rec_counter) + 16:curr_DC <= DC_output[0];17:curr_DC <= DC_output[1]; + 18:curr_DC <= DC_output[2];19:curr_DC <= DC_output[3]; + default:curr_DC <= curr_DC_reg; + endcase + end + else //Cr + begin + if (res_ChromaDCBlk_Cr_IsZero == 1'b1) + curr_DC <= 0; + else + case (blk4x4_rec_counter) + 20:curr_DC <= DC_output[4];21:curr_DC <= DC_output[5]; + 22:curr_DC <= DC_output[6];23:curr_DC <= DC_output[7]; + default:curr_DC <= curr_DC_reg; + endcase + end + end + else + curr_DC <= curr_DC_reg; + + wire curr_DC_IsZero; + assign curr_DC_IsZero = (curr_DC == 0); + + wire [15:0] curr_DC_tmp; + wire [8:0] curr_DC_scaled; + assign curr_DC_tmp = curr_DC + 32; + assign curr_DC_scaled = curr_DC_tmp[14:6]; + + //----------------------------------------------------------------------------------- + //residual type indicator + //----------------------------------------------------------------------------------- + wire res_DC; + wire res_AC; + wire res_luma; + + assign res_DC = (residual_state == `Intra16x16DCLevel_s || residual_state == `ChromaDCLevel_Cb_s || residual_state == `ChromaDCLevel_Cr_s); + assign res_AC = (residual_state != `rst_residual && !res_DC); + assign res_luma = (residual_state == `Intra16x16DCLevel_s || residual_state == `Intra16x16ACLevel_s || + residual_state == `Intra16x16ACLevel_0_s || residual_state == `LumaLevel_s || residual_state == `LumaLevel_0_s); + + //1.OneD_counter:control the step of 1D in IDCT,4 cycles + // For ChromaDC IDCT,we combine the original 2x2 2D IDCT into a 4x4-like 1D IDCT + // ChromaDC: 1 cycle + // Others : 4 cycles + always @ (posedge gclk_1D or negedge reset_n) + if (reset_n == 0) + OneD_counter <= 0; + else if (OneD_counter == 0) + OneD_counter <= (residual_state == `ChromaDCLevel_Cb_s || residual_state == `ChromaDCLevel_Cr_s)? 3'b001:3'b100; + else + OneD_counter <= OneD_counter - 1; + + //2.TwoD_counter:control the step of 2D in IDCT,4 cycles + // ChromaDC: 0 cycle (All ChromDC transform done at 1D-DCT) + // Others : 4 cycles + always @ (posedge gclk_2D or negedge reset_n) + if (reset_n == 0) + TwoD_counter <= 0; + else + TwoD_counter <= (TwoD_counter == 0)? 3'b100:TwoD_counter - 1; + + //3.rescale_counter:control the step of rescale + // ChromaDC: 1 cycle (only 4 ChromDC coefficients) + // Others : 4 cycles(16 coefficients) + always @ (posedge gclk_rescale or negedge reset_n) + if (reset_n == 0) + rescale_counter <= 0; + else if (rescale_counter != 0) + rescale_counter <= rescale_counter - 1; + else if (end_of_NonZeroCoeff_CAVLC == 1'b1) // AC + rescale_counter <= 3'b100; + else if (OneD_counter == 3'b001 && (residual_state == `ChromaDCLevel_Cb_s || residual_state == `ChromaDCLevel_Cr_s)) //ChromaDC + rescale_counter <= 3'b001; + else if (TwoD_counter == 3'b100 && residual_state == `Intra16x16DCLevel_s) //LumaDC + rescale_counter <= 3'b100; + + //4.rounding_counter + always @ (posedge gclk_rounding or negedge reset_n) + if (reset_n == 0) + rounding_counter <= 0; + else + rounding_counter <= (rounding_counter == 0)? 3'b100:(rounding_counter - 1); + + //----------------------------------------------------------------------------------- + //rescale + //----------------------------------------------------------------------------------- + + //butterfly IDCT + //1D DC:from coeffLevel + // Intra16x16 :(0,0) :from DC_output + // others:from rescale_output + // ChromaAC_Cb:(0,0) :from DC_output + // others:from rescale_output + // ChromaAC_Cr:(0,0) :from DC_output + // others:from rescale_output + // others :from rescale_output + // + //2D All from OneD_output + assign IsHadamard = (res_DC == 1'b1 && (OneD_counter != 0 || TwoD_counter != 0))? 1'b1:1'b0; + + butterfly butterfly ( + .D0(butterfly_D0), + .D1(butterfly_D1), + .D2(butterfly_D2), + .D3(butterfly_D3), + .F0(butterfly_F0), + .F1(butterfly_F1), + .F2(butterfly_F2), + .F3(butterfly_F3), + .IsHadamard(IsHadamard) + ); + + always @ (i4x4_CbCr or OneD_counter or TwoD_counter or blk4x4_rec_counter[3:0] or residual_state or res_AC + or res_LumaDCBlk_IsZero or res_ChromaDCBlk_Cb_IsZero or res_ChromaDCBlk_Cr_IsZero + or DC_output[0] or DC_output[1] or DC_output[2] or DC_output[3] + or DC_output[4] or DC_output[5] or DC_output[6] or DC_output[7] + or DC_output[8] or DC_output[9] or DC_output[10] or DC_output[11] + or DC_output[12] or DC_output[13] or DC_output[14] or DC_output[15] + or coeffLevel_ext_0 or coeffLevel_ext_1 or coeffLevel_ext_2 or coeffLevel_ext_3 + or coeffLevel_ext_4 or coeffLevel_ext_5 or coeffLevel_ext_6 or coeffLevel_ext_7 + or coeffLevel_ext_8 or coeffLevel_ext_9 or coeffLevel_ext_10 or coeffLevel_ext_11 + or coeffLevel_ext_12 or coeffLevel_ext_13 or coeffLevel_ext_14 or coeffLevel_ext_15 + or OneD_output[0] or OneD_output[1] or OneD_output[2] or OneD_output[3] + or OneD_output[4] or OneD_output[5] or OneD_output[6] or OneD_output[7] + or OneD_output[8] or OneD_output[9] or OneD_output[10] or OneD_output[11] + or OneD_output[12] or OneD_output[13] or OneD_output[14] or OneD_output[15] + or rescale_output[0] or rescale_output[1] or rescale_output[2] or rescale_output[3]) + if (OneD_counter != 0) + case (OneD_counter) + 3'b100: + begin + case (residual_state) + `Intra16x16ACLevel_s: + if (res_LumaDCBlk_IsZero == 1'b1) + butterfly_D0 <= 0; + else + case (blk4x4_rec_counter[3:0]) + 4'b0000: butterfly_D0 <= DC_output[0]; + 4'b0001: butterfly_D0 <= DC_output[1]; + 4'b0010: butterfly_D0 <= DC_output[2]; + 4'b0011: butterfly_D0 <= DC_output[3]; + 4'b0100: butterfly_D0 <= DC_output[4]; + 4'b0101: butterfly_D0 <= DC_output[5]; + 4'b0110: butterfly_D0 <= DC_output[6]; + 4'b0111: butterfly_D0 <= DC_output[7]; + 4'b1000: butterfly_D0 <= DC_output[8]; + 4'b1001: butterfly_D0 <= DC_output[9]; + 4'b1010: butterfly_D0 <= DC_output[10]; + 4'b1011: butterfly_D0 <= DC_output[11]; + 4'b1100: butterfly_D0 <= DC_output[12]; + 4'b1101: butterfly_D0 <= DC_output[13]; + 4'b1110: butterfly_D0 <= DC_output[14]; + 4'b1111: butterfly_D0 <= DC_output[15]; + endcase + `ChromaACLevel_Cb_s: + if(res_ChromaDCBlk_Cb_IsZero) + butterfly_D0 <= 0; + else + case (i4x4_CbCr) + 2'b00:butterfly_D0 <= DC_output[0]; + 2'b01:butterfly_D0 <= DC_output[1]; + 2'b10:butterfly_D0 <= DC_output[2]; + 2'b11:butterfly_D0 <= DC_output[3]; + endcase + `ChromaACLevel_Cr_s: + if(res_ChromaDCBlk_Cr_IsZero) + butterfly_D0 <= 0; + else + case (i4x4_CbCr) + 2'b00:butterfly_D0 <= DC_output[4]; + 2'b01:butterfly_D0 <= DC_output[5]; + 2'b10:butterfly_D0 <= DC_output[6]; + 2'b11:butterfly_D0 <= DC_output[7]; + endcase + default: //luma DC,chroma DC,luma4x4 AC + butterfly_D0 <= (res_AC == 1'b1)? rescale_output[0]:coeffLevel_ext_0; + endcase + butterfly_D1 <= (res_AC == 1'b1)? rescale_output[1]:coeffLevel_ext_1; + butterfly_D2 <= (res_AC == 1'b1)? rescale_output[2]:coeffLevel_ext_5; + butterfly_D3 <= (res_AC == 1'b1)? rescale_output[3]:coeffLevel_ext_6; + end + 3'b011: + begin + butterfly_D0 <= (res_AC == 1'b1)? rescale_output[0]:coeffLevel_ext_2; + butterfly_D1 <= (res_AC == 1'b1)? rescale_output[1]:coeffLevel_ext_4; + butterfly_D2 <= (res_AC == 1'b1)? rescale_output[2]:coeffLevel_ext_7; + butterfly_D3 <= (res_AC == 1'b1)? rescale_output[3]:coeffLevel_ext_12; + end + 3'b010: + begin + butterfly_D0 <= (res_AC == 1'b1)? rescale_output[0]:coeffLevel_ext_3; + butterfly_D1 <= (res_AC == 1'b1)? rescale_output[1]:coeffLevel_ext_8; + butterfly_D2 <= (res_AC == 1'b1)? rescale_output[2]:coeffLevel_ext_11; + butterfly_D3 <= (res_AC == 1'b1)? rescale_output[3]:coeffLevel_ext_13; + end + 3'b001: + begin + //luma DC + if (residual_state == `Intra16x16DCLevel_s) + begin + butterfly_D0 <= coeffLevel_ext_9; butterfly_D1 <= coeffLevel_ext_10; + butterfly_D2 <= coeffLevel_ext_14; butterfly_D3 <= coeffLevel_ext_15; + end + //chroma DC + else if (residual_state == `ChromaDCLevel_Cb_s || residual_state == `ChromaDCLevel_Cr_s) + begin + butterfly_D0 <= coeffLevel_ext_0; butterfly_D1 <= coeffLevel_ext_1; + butterfly_D2 <= coeffLevel_ext_2; butterfly_D3 <= coeffLevel_ext_3; + end + //AC + else + begin + butterfly_D0 <= rescale_output[0]; butterfly_D1 <= rescale_output[1]; + butterfly_D2 <= rescale_output[2]; butterfly_D3 <= rescale_output[3]; + end + end + default: + begin + butterfly_D0 <= 0; butterfly_D1 <= 0; + butterfly_D2 <= 0; butterfly_D3 <= 0; + end + endcase + else if (TwoD_counter != 0) + case (TwoD_counter) + 3'b100: + begin + butterfly_D0 <= OneD_output[0];butterfly_D1 <= OneD_output[4]; + butterfly_D2 <= OneD_output[8];butterfly_D3 <= OneD_output[12]; + end + 3'b011: + begin + butterfly_D0 <= OneD_output[1];butterfly_D1 <= OneD_output[5]; + butterfly_D2 <= OneD_output[9];butterfly_D3 <= OneD_output[13]; + end + 3'b010: + begin + butterfly_D0 <= OneD_output[2]; butterfly_D1 <= OneD_output[6]; + butterfly_D2 <= OneD_output[10];butterfly_D3 <= OneD_output[14]; + end + 3'b001: + begin + butterfly_D0 <= OneD_output[3]; butterfly_D1 <= OneD_output[7]; + butterfly_D2 <= OneD_output[11];butterfly_D3 <= OneD_output[15]; + end + default: + begin + butterfly_D0 <= 0; butterfly_D1 <= 0; + butterfly_D2 <= 0; butterfly_D3 <= 0; + end + endcase + else + begin + butterfly_D0 <= 0; butterfly_D1 <= 0; + butterfly_D2 <= 0; butterfly_D3 <= 0; + end + + assign QP = (res_luma == 1'b1)? QPy:QPc; + mod6 mod6 ( + .qp(QP), + .mod(QPmod6) + ); + + // Specify LevelScale parameter: LevelScale_DC & LevelScale_AC + always @ (rescale_counter or res_DC or QPmod6) + if (rescale_counter != 0 && res_DC == 1'b1) + case (QPmod6) + 0:LevelScale_DC <= 10; + 1:LevelScale_DC <= 11; + 2:LevelScale_DC <= 13; + 3:LevelScale_DC <= 14; + 4:LevelScale_DC <= 16; + 5:LevelScale_DC <= 18; + default:LevelScale_DC <= 0; + endcase + else + LevelScale_DC <= 0; + + always @ (rescale_counter or res_AC or QPmod6) + if (rescale_counter != 0 && res_AC == 1'b1) + case (rescale_counter) + 3'b100,3'b010: //1 & 3 row + case (QPmod6) + 3'b000:begin LevelScale_AC[0] <= 10; LevelScale_AC[1] <= 13; LevelScale_AC[2] <= 10; LevelScale_AC[3] <= 13; end + 3'b001:begin LevelScale_AC[0] <= 11; LevelScale_AC[1] <= 14; LevelScale_AC[2] <= 11; LevelScale_AC[3] <= 14; end + 3'b010:begin LevelScale_AC[0] <= 13; LevelScale_AC[1] <= 16; LevelScale_AC[2] <= 13; LevelScale_AC[3] <= 16; end + 3'b011:begin LevelScale_AC[0] <= 14; LevelScale_AC[1] <= 18; LevelScale_AC[2] <= 14; LevelScale_AC[3] <= 18; end + 3'b100:begin LevelScale_AC[0] <= 16; LevelScale_AC[1] <= 20; LevelScale_AC[2] <= 16; LevelScale_AC[3] <= 20; end + 3'b101:begin LevelScale_AC[0] <= 18; LevelScale_AC[1] <= 23; LevelScale_AC[2] <= 18; LevelScale_AC[3] <= 23; end + default:begin LevelScale_AC[0] <= 0; LevelScale_AC[1] <= 0; LevelScale_AC[2] <= 0; LevelScale_AC[3] <= 0; end + endcase + 3'b011,3'b001: //2 & 4 row + case (QPmod6) + 3'b000:begin LevelScale_AC[0] <= 13; LevelScale_AC[1] <= 16; LevelScale_AC[2] <= 13; LevelScale_AC[3] <= 16; end + 3'b001:begin LevelScale_AC[0] <= 14; LevelScale_AC[1] <= 18; LevelScale_AC[2] <= 14; LevelScale_AC[3] <= 18; end + 3'b010:begin LevelScale_AC[0] <= 16; LevelScale_AC[1] <= 20; LevelScale_AC[2] <= 16; LevelScale_AC[3] <= 20; end + 3'b011:begin LevelScale_AC[0] <= 18; LevelScale_AC[1] <= 23; LevelScale_AC[2] <= 18; LevelScale_AC[3] <= 23; end + 3'b100:begin LevelScale_AC[0] <= 20; LevelScale_AC[1] <= 25; LevelScale_AC[2] <= 20; LevelScale_AC[3] <= 25; end + 3'b101:begin LevelScale_AC[0] <= 23; LevelScale_AC[1] <= 29; LevelScale_AC[2] <= 23; LevelScale_AC[3] <= 29; end + default:begin LevelScale_AC[0] <= 0; LevelScale_AC[1] <= 0; LevelScale_AC[2] <= 0; LevelScale_AC[3] <= 0; end + endcase + default:begin LevelScale_AC[0] <= 0; LevelScale_AC[1] <= 0; LevelScale_AC[2] <= 0; LevelScale_AC[3] <= 0; end + endcase + else + begin + LevelScale_AC[0] <= 0; LevelScale_AC[1] <= 0; + LevelScale_AC[2] <= 0; LevelScale_AC[3] <= 0; + end + + assign LevelScale[0] = (rescale_counter == 0)? 0:((res_AC == 1)? LevelScale_AC[0]:LevelScale_DC); + assign LevelScale[1] = (rescale_counter == 0)? 0:((res_AC == 1)? LevelScale_AC[1]:LevelScale_DC); + assign LevelScale[2] = (rescale_counter == 0)? 0:((res_AC == 1)? LevelScale_AC[2]:LevelScale_DC); + assign LevelScale[3] = (rescale_counter == 0)? 0:((res_AC == 1)? LevelScale_AC[3]:LevelScale_DC); + + // Specify rescale multiplier input + always @ (residual_state or res_DC or rescale_counter + or OneD_output[0] or OneD_output[1] or OneD_output[2] or OneD_output[3] + or OneD_output[4] or OneD_output[5] or OneD_output[6] or OneD_output[7] + or OneD_output[8] or OneD_output[9] or OneD_output[10] or OneD_output[11] + or OneD_output[12] or OneD_output[13] or OneD_output[14] or OneD_output[15] + or TwoD_output[0] or TwoD_output[1] or TwoD_output[2] or TwoD_output[3] + or coeffLevel_ext_0 or coeffLevel_ext_1 or coeffLevel_ext_2 or coeffLevel_ext_3 + or coeffLevel_ext_4 or coeffLevel_ext_5 or coeffLevel_ext_6 or coeffLevel_ext_7 + or coeffLevel_ext_8 or coeffLevel_ext_9 or coeffLevel_ext_10 or coeffLevel_ext_11 + or coeffLevel_ext_12 or coeffLevel_ext_13 or coeffLevel_ext_14 or coeffLevel_ext_15) + if (residual_state == `Intra16x16DCLevel_s && rescale_counter != 0) //Intra16x16DC + begin + mult0_a <= TwoD_output[0]; mult1_a <= TwoD_output[1]; + mult2_a <= TwoD_output[2]; mult3_a <= TwoD_output[3]; + end + else if (res_DC == 1'b1 && rescale_counter != 0) //ChromaDC + begin + mult0_a <= OneD_output[12]; mult1_a <= OneD_output[15]; + mult2_a <= OneD_output[13]; mult3_a <= OneD_output[14]; + end + else if (rescale_counter != 0) //AC + case (rescale_counter) + 3'b100: + begin + mult0_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_0:0; + mult1_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_1:coeffLevel_ext_0; + mult2_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_5:coeffLevel_ext_4; + mult3_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_6:coeffLevel_ext_5; + end + 3'b011: + begin + mult0_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_2:coeffLevel_ext_1; + mult1_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_4:coeffLevel_ext_3; + mult2_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_7:coeffLevel_ext_6; + mult3_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_12:coeffLevel_ext_11; + end + 3'b010: + begin + mult0_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_3:coeffLevel_ext_2; + mult1_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_8:coeffLevel_ext_7; + mult2_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_11:coeffLevel_ext_10; + mult3_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_13:coeffLevel_ext_12; + end + 3'b001: + begin + mult0_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_9:coeffLevel_ext_8; + mult1_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_10:coeffLevel_ext_9; + mult2_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_14:coeffLevel_ext_13; + mult3_a <= (residual_state == `LumaLevel_s)? coeffLevel_ext_15:coeffLevel_ext_14; + end + default: + begin + mult0_a <= 0; mult1_a <= 0; + mult2_a <= 0; mult3_a <= 0; + end + endcase + else + begin + mult0_a <= 0; mult1_a <= 0; + mult2_a <= 0; mult3_a <= 0; + end + + //rescale multiplier + assign product0 = (rescale_counter == 0)? 0:mult0_a * {1'b0,LevelScale[0]}; + assign product1 = (rescale_counter == 0)? 0:mult1_a * {1'b0,LevelScale[1]}; + assign product2 = (rescale_counter == 0)? 0:mult2_a * {1'b0,LevelScale[2]}; + assign product3 = (rescale_counter == 0)? 0:mult3_a * {1'b0,LevelScale[3]}; + + always @ (res_AC or res_luma or QPy or QPc) + if (res_AC == 1'b1) + IsLeftShift <= 1'b1; + else if (res_luma == 1'b1) + IsLeftShift <= (QPy < 12)? 1'b0:1'b1; + else + IsLeftShift <= (QPc < 6)? 1'b0:1'b1; + + div6 div6 ( + .qp(QP), + .div(QPdiv6) + ); + + always @ (residual_state or res_DC or QPdiv6) + if (residual_state == `Intra16x16DCLevel_s) //Intra16x16DC + case (QPdiv6) + 4'b0000:shift_len <= 2; + 4'b0001:shift_len <= 1; + default:shift_len <= QPdiv6 - 2; + endcase + else if (res_DC) //ChromaDC + case (QPdiv6) + 4'b0000:shift_len <= 1; + default:shift_len <= QPdiv6 - 1; + endcase + else //AC + shift_len <= QPdiv6; + + rescale_shift rescale_shift0 ( + .IsLeftShift(IsLeftShift), + .shift_input(product0), + .shift_len(shift_len), + .shift_output(shift_output0) + ); + rescale_shift rescale_shift1 ( + .IsLeftShift(IsLeftShift), + .shift_input(product1), + .shift_len(shift_len), + .shift_output(shift_output1) + ); + rescale_shift rescale_shift2 ( + .IsLeftShift(IsLeftShift), + .shift_input(product2), + .shift_len(shift_len), + .shift_output(shift_output2) + ); + rescale_shift rescale_shift3 ( + .IsLeftShift(IsLeftShift), + .shift_input(product3), + .shift_len(shift_len), + .shift_output(shift_output3) + ); + //----------------------------------------------------------------------- + //rounding + //----------------------------------------------------------------------- + assign before_rounding0 = (rounding_counter != 0)? TwoD_output[0]:0; + assign before_rounding1 = (rounding_counter != 0)? TwoD_output[1]:0; + assign before_rounding2 = (rounding_counter != 0)? TwoD_output[2]:0; + assign before_rounding3 = (rounding_counter != 0)? TwoD_output[3]:0; + + assign rounding_sum0 = before_rounding0[14:5] + 1; + assign rounding_sum1 = before_rounding1[14:5] + 1; + assign rounding_sum2 = before_rounding2[14:5] + 1; + assign rounding_sum3 = before_rounding3[14:5] + 1; + + //----------------------------------------------------------------------- + // Strore results + //----------------------------------------------------------------------- + //1. Store OneD_output + integer i; + always @ (posedge gclk_1D or negedge reset_n) + if (reset_n == 0) + for (i=0;i<16;i=i+1) + OneD_output[i] <= 0; + else if (OneD_counter != 0) + case (OneD_counter) + 3'b100: + begin + OneD_output[0] <= butterfly_F0;OneD_output[1] <= butterfly_F1; + OneD_output[2] <= butterfly_F2;OneD_output[3] <= butterfly_F3; + end + 3'b011: + begin + OneD_output[4] <= butterfly_F0;OneD_output[5] <= butterfly_F1; + OneD_output[6] <= butterfly_F2;OneD_output[7] <= butterfly_F3; + end + 3'b010: + begin + OneD_output[8] <= butterfly_F0;OneD_output[9] <= butterfly_F1; + OneD_output[10] <= butterfly_F2;OneD_output[11] <= butterfly_F3; + end + 3'b001: + begin + OneD_output[12] <= butterfly_F0;OneD_output[13] <= butterfly_F1; + OneD_output[14] <= butterfly_F2;OneD_output[15] <= butterfly_F3; + end + endcase + + //2. Store TwoD_output + integer j; + always @ (posedge gclk_2D or negedge reset_n) + if (reset_n == 0) + for (j=0;j<4;j=j+1) + TwoD_output[j] <= 0; + else if (TwoD_counter != 0) + begin + TwoD_output[0] <= butterfly_F0; TwoD_output[1] <= butterfly_F1; + TwoD_output[2] <= butterfly_F2; TwoD_output[3] <= butterfly_F3; + end + + //3.1 Store rescale_output as DC_output + integer m; + always @ (posedge gclk_rescale or negedge reset_n) + if (reset_n == 1'b0) + for (m=0;m<16;m=m+1) + DC_output[m] <= 0; + else if (res_DC == 1'b1) + case (rescale_counter) + 3'b100: + begin + DC_output[0] <= shift_output0; DC_output[2] <= shift_output1; + DC_output[8] <= shift_output2; DC_output[10] <= shift_output3; + end + 3'b011: + begin + DC_output[1] <= shift_output0; DC_output[3] <= shift_output1; + DC_output[9] <= shift_output2; DC_output[11] <= shift_output3; + end + 3'b010: + begin + DC_output[4] <= shift_output0; DC_output[6] <= shift_output1; + DC_output[12] <= shift_output2; DC_output[14] <= shift_output3; + end + 3'b001: + if (residual_state == `ChromaDCLevel_Cb_s) + begin + DC_output[0] <= shift_output0; DC_output[1] <= shift_output1; + DC_output[2] <= shift_output2; DC_output[3] <= shift_output3; + end + else if (residual_state == `ChromaDCLevel_Cr_s) + begin + DC_output[4] <= shift_output0; DC_output[5] <= shift_output1; + DC_output[6] <= shift_output2; DC_output[7] <= shift_output3; + end + else + begin + DC_output[5] <= shift_output0; DC_output[7] <= shift_output1; + DC_output[13] <= shift_output2; DC_output[15] <= shift_output3; + end + endcase + + //3.2 Store rescale_output as AC_output + integer n; + always @ (posedge gclk_rescale or negedge reset_n) + if (reset_n == 1'b0) + for (n=0;n<4;n=n+1) + rescale_output[n] <= 0; + else if (res_AC == 1'b1 && rescale_counter != 0) + begin + rescale_output[0] <= shift_output0; rescale_output[1] <= shift_output1; + rescale_output[2] <= shift_output2; rescale_output[3] <= shift_output3; + end + + //4. Store rounding_output + always @ (posedge gclk_rounding or negedge reset_n) + if (reset_n == 1'b0) + begin + rounding_output_0 <= 0;rounding_output_1 <= 0;rounding_output_2 <= 0;rounding_output_3 <= 0; + rounding_output_4 <= 0;rounding_output_5 <= 0;rounding_output_6 <= 0;rounding_output_7 <= 0; + rounding_output_8 <= 0;rounding_output_9 <= 0;rounding_output_10 <= 0;rounding_output_11 <= 0; + rounding_output_12 <= 0;rounding_output_13 <= 0;rounding_output_14 <= 0;rounding_output_15 <= 0; + end + else + case (rounding_counter) + 3'b100: + begin + rounding_output_0 <= rounding_sum0[9:1]; + rounding_output_4 <= rounding_sum1[9:1]; + rounding_output_8 <= rounding_sum2[9:1]; + rounding_output_12 <= rounding_sum3[9:1]; + end + 3'b011: + begin + rounding_output_1 <= rounding_sum0[9:1]; + rounding_output_5 <= rounding_sum1[9:1]; + rounding_output_9 <= rounding_sum2[9:1]; + rounding_output_13 <= rounding_sum3[9:1]; + end + 3'b010: + begin + rounding_output_2 <= rounding_sum0[9:1]; + rounding_output_6 <= rounding_sum1[9:1]; + rounding_output_10 <= rounding_sum2[9:1]; + rounding_output_14 <= rounding_sum3[9:1]; + end + 3'b001: + begin + rounding_output_3 <= rounding_sum0[9:1]; + rounding_output_7 <= rounding_sum1[9:1]; + rounding_output_11 <= rounding_sum2[9:1]; + rounding_output_15 <= rounding_sum3[9:1]; + end + endcase + assign end_of_ACBlk4x4_IQIT = (rounding_counter == 3'b001)? 1'b1:1'b0; + assign end_of_DCBlk_IQIT = ((residual_state == `Intra16x16DCLevel_s || residual_state == `ChromaDCLevel_Cb_s || + residual_state == `ChromaDCLevel_Cr_s) && rescale_counter == 3'b001)? 1'b1:1'b0; +endmodule + +module butterfly (D0,D1,D2,D3,F0,F1,F2,F3,IsHadamard); + input [15:0] D0,D1,D2,D3; + input IsHadamard; + output [15:0] F0,F1,F2,F3; + + wire [15:0] T0,T1,T2,T3; + wire [15:0] D1_scale,D3_scale; + + assign D1_scale = (IsHadamard == 1'b1)? D1:{D1[15],D1[15:1]}; + assign D3_scale = (IsHadamard == 1'b1)? D3:{D3[15],D3[15:1]}; + + assign T0 = D0 + D2; + assign T1 = D0 - D2; + assign T2 = D1_scale - D3; + assign T3 = D1 + D3_scale; + + assign F0 = T0 + T3; + assign F1 = T1 + T2; + assign F2 = T1 - T2; + assign F3 = T0 - T3; +endmodule + +module mod6 (qp,mod); + input [5:0] qp; + output [2:0] mod; + reg [2:0] mod; + always @ (qp) + case (qp) + 0, 6,12,18,24,30,36,42,48:mod <= 3'b000; + 1, 7,13,19,25,31,37,43,49:mod <= 3'b001; + 2, 8,14,20,26,32,38,44,50:mod <= 3'b010; + 3, 9,15,21,27,33,39,45,51:mod <= 3'b011; + 4,10,16,22,28,34,40,46 :mod <= 3'b100; + 5,11,17,23,29,35,41,47 :mod <= 3'b101; + default :mod <= 3'b000; + endcase +endmodule + +module div6 (qp,div); + input [5:0] qp; + output [3:0] div; + reg [3:0] div; + always @ (qp) + case (qp) + 0, 1, 2, 3, 4, 5 :div <= 4'b0000; + 6, 7, 8, 9, 10,11:div <= 4'b0001; + 12,13,14,15,16,17:div <= 4'b0010; + 18,19,20,21,22,23:div <= 4'b0011; + 24,25,26,27,28,29:div <= 4'b0100; + 30,31,32,33,34,35:div <= 4'b0101; + 36,37,38,39,40,41:div <= 4'b0110; + 42,43,44,45,46,47:div <= 4'b0111; + 48,49,50,51 :div <= 4'b1000; + default :div <= 0; + endcase +endmodule + +module rescale_shift (IsLeftShift,shift_input,shift_len,shift_output); + input IsLeftShift; + input signed [15:0] shift_input; + input [3:0] shift_len; + output signed [15:0] shift_output; + + assign shift_output = (IsLeftShift == 1'b1)? (shift_input <<< shift_len):(shift_input >>> shift_len); +endmodule + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/Inter_mv_decoding.v b/demo_chip_rtl/rtl/nova/trunk/src/Inter_mv_decoding.v new file mode 100644 index 0000000..94524e7 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/Inter_mv_decoding.v @@ -0,0 +1,2612 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : Inter_mv_decoding.v +// Generated : May 25, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Decoding the motion vector x and motion vector y for Inter prediction and P_skip +// SearchRange = 16pix -> 64 -> -64 ~ + 64 -> mvd[7:0], mv[7:0], mvp[7:0] +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module Inter_mv_decoding (clk,reset_n,Is_skip_run_entry,Is_skip_run_end, + slice_data_state,mb_pred_state,sub_mb_pred_state,mvd, + mb_num,mb_num_h,mb_num_v,mb_type_general,sub_mb_type,end_of_MB_DEC,mbPartIdx,subMbPartIdx,compIdx, + MBTypeGen_mbAddrA,MBTypeGen_mbAddrB_reg,MBTypeGen_mbAddrD, + mvx_mbAddrB_dout,mvy_mbAddrB_dout,mvx_mbAddrC_dout,mvy_mbAddrC_dout,mv_mbAddrB_rd_for_DF, + + skip_mv_calc,Is_skipMB_mv_calc,mvx_mbAddrA,mvy_mbAddrA, + mvx_mbAddrB_cs_n,mvx_mbAddrB_wr_n,mvx_mbAddrB_rd_addr,mvx_mbAddrB_wr_addr,mvx_mbAddrB_din, + mvy_mbAddrB_cs_n,mvy_mbAddrB_wr_n,mvy_mbAddrB_rd_addr,mvy_mbAddrB_wr_addr,mvy_mbAddrB_din, + mvx_mbAddrC_cs_n,mvx_mbAddrC_wr_n,mvx_mbAddrC_rd_addr,mvx_mbAddrC_wr_addr,mvx_mbAddrC_din, + mvy_mbAddrC_cs_n,mvy_mbAddrC_wr_n,mvy_mbAddrC_rd_addr,mvy_mbAddrC_wr_addr,mvy_mbAddrC_din, + mv_is16x16, + mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3, + mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3); + input clk,reset_n; + input Is_skip_run_entry; + input Is_skip_run_end; + input [3:0] slice_data_state; + input [2:0] mb_pred_state; + input [1:0] sub_mb_pred_state; + input [7:0] mvd; + input [6:0] mb_num; + input [3:0] mb_num_h; + input [3:0] mb_num_v; + input [3:0] mb_type_general; + input [1:0] sub_mb_type; + input end_of_MB_DEC; + input [1:0] mbPartIdx,subMbPartIdx; + input compIdx; + input [1:0] MBTypeGen_mbAddrA; + input MBTypeGen_mbAddrD; + input [21:0] MBTypeGen_mbAddrB_reg; + input [31:0] mvx_mbAddrB_dout,mvy_mbAddrB_dout; + input [7:0] mvx_mbAddrC_dout,mvy_mbAddrC_dout; + input mv_mbAddrB_rd_for_DF; + + output skip_mv_calc; + output Is_skipMB_mv_calc; + output [31:0] mvx_mbAddrA,mvy_mbAddrA; + output mvx_mbAddrB_cs_n,mvy_mbAddrB_cs_n,mvx_mbAddrC_cs_n,mvy_mbAddrC_cs_n; + output mvx_mbAddrB_wr_n,mvy_mbAddrB_wr_n,mvx_mbAddrC_wr_n,mvy_mbAddrC_wr_n; + output [3:0] mvx_mbAddrB_rd_addr,mvy_mbAddrB_rd_addr,mvx_mbAddrC_rd_addr,mvy_mbAddrC_rd_addr; + output [3:0] mvx_mbAddrB_wr_addr,mvy_mbAddrB_wr_addr,mvx_mbAddrC_wr_addr,mvy_mbAddrC_wr_addr; + output [31:0] mvx_mbAddrB_din,mvy_mbAddrB_din; + output [7:0] mvx_mbAddrC_din,mvy_mbAddrC_din; + output mv_is16x16; + output [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3; + output [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3; + reg mvx_mbAddrB_cs_n,mvy_mbAddrB_cs_n,mvx_mbAddrC_cs_n,mvy_mbAddrC_cs_n; + reg mvx_mbAddrB_wr_n,mvy_mbAddrB_wr_n,mvx_mbAddrC_wr_n,mvy_mbAddrC_wr_n; + reg [3:0] mvx_mbAddrB_rd_addr,mvy_mbAddrB_rd_addr,mvx_mbAddrC_rd_addr,mvy_mbAddrC_rd_addr; + reg [3:0] mvx_mbAddrB_wr_addr,mvy_mbAddrB_wr_addr,mvx_mbAddrC_wr_addr,mvy_mbAddrC_wr_addr; + reg [31:0] mvx_mbAddrB_din,mvy_mbAddrB_din; + reg [7:0] mvx_mbAddrC_din,mvy_mbAddrC_din; + reg mv_is16x16; + reg [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3; + reg [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3; + + reg [7:0] mvpAx,mvpAy,mvpBx,mvpBy,mvpCx,mvpCy; + reg [31:0] mvx_mbAddrA,mvy_mbAddrA; + wire [7:0] mvx_mbAddrD,mvy_mbAddrD; + reg [7:0] mvpx,mvpy,mvx,mvy; + + reg skip_mv_calc; //This signal is of reg type and is active for one cycle after end_of_MB_DEC and before + //trigger_blk4x4_inter_pred.It is used to direct motion vector prediction for skipped MB + always @ (posedge clk) + if (reset_n == 1'b0) + skip_mv_calc <= 1'b0; + else if (slice_data_state == `skip_run_duration && end_of_MB_DEC && !Is_skip_run_end) + skip_mv_calc <= 1'b1; + else + skip_mv_calc <= 1'b0; + + wire Is_skipMB_mv_calc; + assign Is_skipMB_mv_calc = Is_skip_run_entry | skip_mv_calc; + + reg [1:0] MBTypeGen_mbAddrB; + reg [1:0] MBTypeGen_mbAddrC; + always @ (mb_num_h or MBTypeGen_mbAddrB_reg) + case (mb_num_h) + 0 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[1:0]; + 1 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[3:2]; + 2 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[5:4]; + 3 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[7:6]; + 4 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[9:8]; + 5 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[11:10]; + 6 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[13:12]; + 7 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[15:14]; + 8 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[17:16]; + 9 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[19:18]; + 10:MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[21:20]; + default:MBTypeGen_mbAddrB <= 0; + endcase + always @ (mb_num_h or MBTypeGen_mbAddrB_reg) + case (mb_num_h) + 0:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[3:2]; + 1:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[5:4]; + 2:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[7:6]; + 3:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[9:8]; + 4:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[11:10]; + 5:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[13:12]; + 6:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[15:14]; + 7:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[17:16]; + 8:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[19:18]; + 9:MBTypeGen_mbAddrC <= MBTypeGen_mbAddrB_reg[21:20]; + default:MBTypeGen_mbAddrC <= 0; + endcase + + wire refIdxL0_A; //Here refIdxL0_A == 1'b1 is equal to refIdxL0_A == -1 in Page122 of H.264 2003.5 standard + wire refIdxL0_B; //Here refIdxL0_B == 1'b1 is equal to refIdxL0_B == -1 in Page122 of H.264 2003.5 standard + reg refIdxL0_C; //Here refIdxL0_C == 1'b1 is equal to refIdxL0_C == -1 in Page122 of H.264 2003.5 standard + + assign refIdxL0_A = ( + //P_skip + (Is_skipMB_mv_calc || + //Inter16x16,Inter16x8,Inter8x16 left blk + (mb_pred_state == `mvd_l0_s && (mb_type_general == `MB_Inter16x16 || mb_type_general == `MB_Inter16x8 || (mb_type_general == `MB_Inter8x16 && mbPartIdx == 0))) || + //Inter8x8,left most blk + (sub_mb_pred_state == `sub_mvd_l0_s && (mbPartIdx == 0 || mbPartIdx == 2) && ( + sub_mb_type == 0 || + sub_mb_type == 1 || + (sub_mb_type == 2 && subMbPartIdx == 0) || + (sub_mb_type == 3 && (subMbPartIdx == 0 || subMbPartIdx == 2))))) && + (mb_num_h == 0 || MBTypeGen_mbAddrA[1] == 1))? 1'b1:1'b0; + + assign refIdxL0_B = ( + //P_skip + (Is_skipMB_mv_calc || + //Inter16x16,Inter16x8 upper blk,Inter8x16 + (mb_pred_state == `mvd_l0_s && (mb_type_general == `MB_Inter16x16 || (mb_type_general == `MB_Inter16x8 && mbPartIdx == 0) || mb_type_general == `MB_Inter8x16)) || + //Inter8x8,left most blk + (sub_mb_pred_state == `sub_mvd_l0_s && (mbPartIdx == 0 || mbPartIdx == 1) && ( + sub_mb_type == 0 || + sub_mb_type == 2 || + (sub_mb_type == 1 && subMbPartIdx == 0) || + (sub_mb_type == 3 && (subMbPartIdx == 0 || subMbPartIdx == 1))))) && + (mb_num_v == 0 || MBTypeGen_mbAddrB[1] == 1))? 1'b1:1'b0; + + always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state or mb_type_general or mb_num_v or mb_num_h + or sub_mb_type or mbPartIdx or subMbPartIdx or MBTypeGen_mbAddrC[1] or MBTypeGen_mbAddrD + or refIdxL0_A or refIdxL0_B) + //P_skip,Inter16x16 + if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16)) + begin + if (mb_num_v == 0) refIdxL0_C <= 1'b1; + else if (mb_num_h == 10) refIdxL0_C <= (MBTypeGen_mbAddrD == `MB_addrD_Intra)? 1'b1:1'b0; + else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0; + end + //Inter16x8 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8) + begin + if (mbPartIdx == 0) //upper blk + begin + if (mb_num_v == 0) refIdxL0_C <= 1'b1; + else if (mb_num_h == 10) refIdxL0_C <= (MBTypeGen_mbAddrD == `MB_addrD_Intra)? 1'b1:1'b0; + else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0; + end + else //bottom blk + refIdxL0_C <= refIdxL0_A; + end + //Inter8x16 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16) + begin + if (mbPartIdx == 0) //left blk + refIdxL0_C <= refIdxL0_B; + else //right blk + begin + if (mb_num_v == 0 || mb_num_h == 10) refIdxL0_C <= refIdxL0_B; + else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0; + end + end + //Inter8x8 and below + else if (sub_mb_pred_state == `sub_mvd_l0_s) + case (mbPartIdx) + 2'b00: //left-top 8x8 blk + case (sub_mb_type) + 0:refIdxL0_C <= refIdxL0_B; + 1:refIdxL0_C <= (subMbPartIdx == 0)? refIdxL0_B:refIdxL0_A; + 2:refIdxL0_C <= refIdxL0_B; + 3: + case (subMbPartIdx) + 0,1:refIdxL0_C <= refIdxL0_B; + 2,3:refIdxL0_C <= 1'b0; + endcase + endcase + 2'b01: //right-top 8x8 blk + case (sub_mb_type) + 0: //8x8 + if (mb_num_v == 0) refIdxL0_C <= 1'b1; + else if (mb_num_h == 10) refIdxL0_C <= refIdxL0_B; + else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0; + 1: //8x4 + if (subMbPartIdx == 0) + begin + if (mb_num_v == 0) refIdxL0_C <= 1'b1; + else if (mb_num_h == 10) refIdxL0_C <= refIdxL0_B; + else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0; + end + else + refIdxL0_C <= 1'b0; + 2: //4x8 + if (subMbPartIdx == 0) refIdxL0_C <= refIdxL0_B; + else + begin + if (mb_num_v == 0) refIdxL0_C <= 1'b1; + else if (mb_num_h == 10) refIdxL0_C <= refIdxL0_B; + else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0; + end + 3: //4x4 + case (subMbPartIdx) + 0:refIdxL0_C <= refIdxL0_B; + 1: + begin + if (mb_num_v == 0) refIdxL0_C <= 1'b1; + else if (mb_num_h == 10) refIdxL0_C <= refIdxL0_B; + else refIdxL0_C <= (MBTypeGen_mbAddrC[1] == 1'b1)? 1'b1:1'b0; + end + 2,3:refIdxL0_C <= 1'b0; + endcase + endcase + 2'b10: //left-bottom 8x8 blk + case (sub_mb_type) + 0:refIdxL0_C <= 1'b0; + 1:refIdxL0_C <= (subMbPartIdx == 0)? 1'b0:refIdxL0_A; + 2:refIdxL0_C <= 1'b0; + 3:refIdxL0_C <= 1'b0; + endcase + 2'b11: //right-bottom 8x8 blk + refIdxL0_C <= 1'b0; + endcase + else + refIdxL0_C <= 1'b0; + + //------------- + //mvpAx + //------------- + always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state + or mb_type_general or sub_mb_type or mbPartIdx or subMbPartIdx or compIdx + or mvx_mbAddrA or mvx_CurrMb0 or mvx_CurrMb1 or mvx_CurrMb2 or mvx_CurrMb3 + or refIdxL0_A or refIdxL0_B or refIdxL0_C) + //P_skip or Inter16x16 + if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0)) + mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0]; + //Inter16x8 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0) + begin + if (mbPartIdx == 0) + mvpAx <= {8{refIdxL0_B}} & mvx_mbAddrA[7:0]; + else + mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[23:16]; + end + //Inter8x16 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 0) + begin + if (mbPartIdx == 0) + mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0]; + else + mvpAx <= {8{refIdxL0_C}} & mvx_CurrMb0[15:8]; + end + //Inter8x8 + else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0) //sub_mb_pred + case (mbPartIdx) + 0: + case (sub_mb_type) + 0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0]; + 1: //8x4 + case (subMbPartIdx) + 0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0]; + 1:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[15:8]; + default:mvpAx <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0]; + 1:mvpAx <= mvx_CurrMb0[7:0]; + default:mvpAx <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[7:0]; + 1:mvpAx <= mvx_CurrMb0[7:0]; + 2:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[15:8]; + 3:mvpAx <= mvx_CurrMb0[23:16]; + endcase + endcase + 1: + case (sub_mb_type) + 0:mvpAx <= mvx_CurrMb0[15:8]; + 1: //8x4 + case (subMbPartIdx) + 0:mvpAx <= mvx_CurrMb0[15:8]; 1:mvpAx <= mvx_CurrMb0[31:24]; + default:mvpAx <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:mvpAx <= mvx_CurrMb0[15:8]; 1:mvpAx <= mvx_CurrMb1[7:0]; + default:mvpAx <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvpAx <= mvx_CurrMb0[15:8] ; 1:mvpAx <= mvx_CurrMb1[7:0]; + 2:mvpAx <= mvx_CurrMb0[31:24]; 3:mvpAx <= mvx_CurrMb1[23:16]; + endcase + endcase + 2: + case (sub_mb_type) + 0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[23:16]; + 1: //8x4 + case (subMbPartIdx) + 0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[23:16]; + 1:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[31:24]; + default:mvpAx <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[23:16]; + 1:mvpAx <= mvx_CurrMb2[7:0]; + default:mvpAx <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[23:16]; + 1:mvpAx <= mvx_CurrMb2[7:0]; + 2:mvpAx <= {8{~refIdxL0_A}} & mvx_mbAddrA[31:24]; + 3:mvpAx <= mvx_CurrMb2[23:16]; + endcase + endcase + 3: + case (sub_mb_type) + 0:mvpAx <= mvx_CurrMb2[15:8]; + 1: //8x4 + case (subMbPartIdx) + 0:mvpAx <= mvx_CurrMb2[15:8]; 1:mvpAx <= mvx_CurrMb2[31:24]; + default:mvpAx <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:mvpAx <= mvx_CurrMb2[15:8]; 1:mvpAx <= mvx_CurrMb3[7:0]; + default:mvpAx <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvpAx <= mvx_CurrMb2[15:8]; 1:mvpAx <= mvx_CurrMb3[7:0]; + 2:mvpAx <= mvx_CurrMb2[31:24]; 3:mvpAx <= mvx_CurrMb3[23:16]; + endcase + endcase + endcase + else + mvpAx <= 0; + + //------------- + //mvpAy + //------------- + always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state + or mb_type_general or sub_mb_type or mbPartIdx or subMbPartIdx or compIdx + or mvy_mbAddrA or mvy_CurrMb0 or mvy_CurrMb1 or mvy_CurrMb2 or mvy_CurrMb3 + or refIdxL0_A or refIdxL0_B or refIdxL0_C) + //P_skip or Inter16x16 + if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1)) + mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[7:0]; + //Inter16x8 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1) + begin + if (mbPartIdx == 0) + mvpAy <= {8{refIdxL0_B}} & mvy_mbAddrA[7:0]; + else + mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[23:16]; + end + //Inter8x16 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 1) + begin + if (mbPartIdx == 0) + mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[7:0]; + else + mvpAy <= {8{refIdxL0_C}} & mvy_CurrMb0[15:8]; + end + //Inter8x8 + else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1) //sub_mb_pred + case (mbPartIdx) + 0: + case (sub_mb_type) + 0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[7:0]; + 1: //8x4 + case (subMbPartIdx) + 0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[7:0]; + 1:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[15:8]; + default:mvpAy <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[7:0]; + 1:mvpAy <= mvy_CurrMb0[7:0]; + default:mvpAy <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[7:0]; + 1:mvpAy <= mvy_CurrMb0[7:0]; + 2:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[15:8]; + 3:mvpAy <= mvy_CurrMb0[23:16]; + endcase + endcase + 1: + case (sub_mb_type) + 0:mvpAy <= mvy_CurrMb0[15:8]; + 1: //8x4 + case (subMbPartIdx) + 0:mvpAy <= mvy_CurrMb0[15:8]; 1:mvpAy <= mvy_CurrMb0[31:24]; + default:mvpAy <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:mvpAy <= mvy_CurrMb0[15:8]; 1:mvpAy <= mvy_CurrMb1[7:0]; + default:mvpAy <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvpAy <= mvy_CurrMb0[15:8] ; 1:mvpAy <= mvy_CurrMb1[7:0]; + 2:mvpAy <= mvy_CurrMb0[31:24]; 3:mvpAy <= mvy_CurrMb1[23:16]; + endcase + endcase + 2: + case (sub_mb_type) + 0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[23:16]; + 1: //8x4 + case (subMbPartIdx) + 0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[23:16]; + 1:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[31:24]; + default:mvpAy <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[23:16]; + 1:mvpAy <= mvy_CurrMb2[7:0]; + default:mvpAy <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[23:16]; + 1:mvpAy <= mvy_CurrMb2[7:0]; + 2:mvpAy <= {8{~refIdxL0_A}} & mvy_mbAddrA[31:24]; + 3:mvpAy <= mvy_CurrMb2[23:16]; + endcase + endcase + 3: + case (sub_mb_type) + 0:mvpAy <= mvy_CurrMb2[15:8]; + 1: //8x4 + case (subMbPartIdx) + 0:mvpAy <= mvy_CurrMb2[15:8]; 1:mvpAy <= mvy_CurrMb2[31:24]; + default:mvpAy <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:mvpAy <= mvy_CurrMb2[15:8]; 1:mvpAy <= mvy_CurrMb3[7:0]; + default:mvpAy <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvpAy <= mvy_CurrMb2[15:8]; 1:mvpAy <= mvy_CurrMb3[7:0]; + 2:mvpAy <= mvy_CurrMb2[31:24]; 3:mvpAy <= mvy_CurrMb3[23:16]; + endcase + endcase + endcase + else + mvpAy <= 0; + //------------- + //mvpBx + //------------- + //if B is not available,it can be predicted from A when both B and C are not available + always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state or mb_type_general or sub_mb_type + or mb_num or mb_num_v or mbPartIdx or subMbPartIdx or compIdx or MBTypeGen_mbAddrA[1] or MBTypeGen_mbAddrB[1] + or mvx_mbAddrA or mvx_mbAddrB_dout or mvx_CurrMb0 or mvx_CurrMb1 or mvx_CurrMb2 or mvx_CurrMb3 + or refIdxL0_A or refIdxL0_B or refIdxL0_C) + //P_skip or Inter16x16 + if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0)) + begin + if (mb_num == 0) mvpBx <= 0; + else if (mb_num_v == 0) mvpBx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0]; + else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[31:24]; + end + //Inter16x8 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0) + begin + if (mbPartIdx == 0) + begin + if (mb_num == 0) mvpBx <= 0; + else if (mb_num_v == 0) mvpBx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0]; + else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[31:24]; + end + else //for bottom 8x8 block when mbAddrA is not available + mvpBx <= (!refIdxL0_A)? 0:mvx_CurrMb0[23:16]; + end + //Inter8x16:for left 8x8 block when mbAddrA is not available + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 0) + begin + if (mbPartIdx == 0) //left blk + mvpBx <= (refIdxL0_A && !refIdxL0_B)? mvx_mbAddrB_dout[31:24]:0; + else //right blk + case (!refIdxL0_C) + 1'b1:mvpBx <= 0; + 1'b0: + if (mb_num_v == 0) + mvpBx <= mvx_CurrMb0[7:0]; + else + mvpBx <= (!refIdxL0_B)? mvx_mbAddrB_dout[15:8]:0; + endcase + end + //Inter8x8 + else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0) + case (mbPartIdx) + 0: + case (sub_mb_type) + 0:if (mb_num == 0) mvpBx <= 0; + else if (mb_num_v == 0) mvpBx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0]; + else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[31:24]; + 1: //8x4 + case (subMbPartIdx) + 0:if (mb_num == 0) mvpBx <= 0; + else if (mb_num_v == 0) mvpBx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0]; + else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[31:24]; + 1:mvpBx <= mvx_CurrMb0[7:0]; + default:mvpBx <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:if (mb_num == 0) mvpBx <= 0; + else if (mb_num_v == 0) mvpBx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0]; + else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[31:24]; + 1:if (mb_num_v == 0) mvpBx <= mvx_CurrMb0[7:0]; + else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16]; + default:mvpBx <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:if (mb_num == 0) mvpBx <= 0; + else if (mb_num_v == 0) mvpBx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0]; + else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[31:24]; + 1:if (mb_num_v == 0) mvpBx <= mvx_CurrMb0[7:0]; + else mvpBx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16]; + 2:mvpBx <= mvx_CurrMb0[7:0]; + 3:mvpBx <= mvx_CurrMb0[15:8]; + endcase + endcase + 1: + case (sub_mb_type) + 0:mvpBx <= (mb_num_v == 0)? mvx_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]); + 1: //8x4 + case (subMbPartIdx) + 0:mvpBx <= (mb_num_v == 0)? mvx_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]); + 1:mvpBx <= mvx_CurrMb1[7:0]; + default:mvpBx <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:mvpBx <= (mb_num_v == 0)? mvx_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]); + 1:mvpBx <= (mb_num_v == 0)? mvx_CurrMb1[7:0] :((MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[7:0]); + default:mvpBx <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvpBx <= (mb_num_v == 0)? mvx_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]); + 1:mvpBx <= (mb_num_v == 0)? mvx_CurrMb1[7:0] :((MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[7:0]); + 2:mvpBx <= mvx_CurrMb1[7:0]; + 3:mvpBx <= mvx_CurrMb1[15:8]; + endcase + endcase + 2: + case (sub_mb_type) + 0:mvpBx <= mvx_CurrMb0[23:16]; + 1: //8x4 + case (subMbPartIdx) + 0:mvpBx <= mvx_CurrMb0[23:16]; 1:mvpBx <= mvx_CurrMb2[7:0]; default:mvpBx <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:mvpBx <= mvx_CurrMb0[23:16]; 1:mvpBx <= mvx_CurrMb0[31:24]; default:mvpBx <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvpBx <= mvx_CurrMb0[23:16]; 1:mvpBx <= mvx_CurrMb0[31:24]; + 2:mvpBx <= mvx_CurrMb2[7:0]; 3:mvpBx <= mvx_CurrMb2[15:8]; + endcase + endcase + 3: + case (sub_mb_type) + 0:mvpBx <= mvx_CurrMb1[23:16]; + 1: //8x4 + case (subMbPartIdx) + 0:mvpBx <= mvx_CurrMb1[23:16]; 1:mvpBx <= mvx_CurrMb3[7:0]; default:mvpBx <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:mvpBx <= mvx_CurrMb1[23:16]; 1:mvpBx <= mvx_CurrMb1[31:24]; default:mvpBx <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvpBx <= mvx_CurrMb1[23:16]; 1:mvpBx <= mvx_CurrMb1[31:24]; + 2:mvpBx <= mvx_CurrMb3[7:0]; 3:mvpBx <= mvx_CurrMb3[15:8]; + endcase + endcase + endcase + else + mvpBx <= 0; + //------------- + //mvpBy + //------------- + //if B is not available,it can be predicted from A when both B and C are not available + always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state or mb_type_general or sub_mb_type + or mb_num or mb_num_v or mbPartIdx or subMbPartIdx or compIdx or MBTypeGen_mbAddrA[1] or MBTypeGen_mbAddrB[1] + or mvy_mbAddrA or mvy_mbAddrB_dout or mvy_CurrMb0 or mvy_CurrMb1 or mvy_CurrMb2 or mvy_CurrMb3 + or refIdxL0_A or refIdxL0_B or refIdxL0_C) + //P_skip or Inter16x16 + if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1)) + begin + if (mb_num == 0) mvpBy <= 0; + else if (mb_num_v == 0) mvpBy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0]; + else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[31:24]; + end + //Inter16x8 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1) + begin + if (mbPartIdx == 0) //upper 8x8 block + begin + if (mb_num == 0) mvpBy <= 0; + else if (mb_num_v == 0) mvpBy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0]; + else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[31:24]; + end + else //for bottom 8x8 block when mbAddrA is not available + mvpBy <= (!refIdxL0_A)? 0:mvy_CurrMb0[23:16]; + end + //Inter8x16:for left 8x8 block when mbAddrA is not available + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 1) + begin + if (mbPartIdx == 0) //left blk + mvpBy <= (refIdxL0_A && !refIdxL0_B)? mvy_mbAddrB_dout[31:24]:0; + else //right blk + case (!refIdxL0_C) + 1'b1:mvpBy <= 0; + 1'b0: + if (mb_num_v == 0) + mvpBy <= mvy_CurrMb0[7:0]; + else + mvpBy <= (!refIdxL0_B)? mvy_mbAddrB_dout[15:8]:0; + endcase + end + //Inter8x8 + else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1) + case (mbPartIdx) + 0: + case (sub_mb_type) + 0:if (mb_num == 0) mvpBy <= 0; + else if (mb_num_v == 0) mvpBy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0]; + else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[31:24]; + 1: //8x4 + case (subMbPartIdx) + 0:if (mb_num == 0) mvpBy <= 0; + else if (mb_num_v == 0) mvpBy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0]; + else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[31:24]; + 1:mvpBy <= mvy_CurrMb0[7:0]; + default:mvpBy <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:if (mb_num == 0) mvpBy <= 0; + else if (mb_num_v == 0) mvpBy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0]; + else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[31:24]; + 1:if (mb_num_v == 0) mvpBy <= mvy_CurrMb0[7:0]; + else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16]; + default:mvpBy <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:if (mb_num == 0) mvpBy <= 0; + else if (mb_num_v == 0) mvpBy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0]; + else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[31:24]; + 1:if (mb_num_v == 0) mvpBy <= mvy_CurrMb0[7:0]; + else mvpBy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16]; + 2:mvpBy <= mvy_CurrMb0[7:0]; + 3:mvpBy <= mvy_CurrMb0[15:8]; + endcase + endcase + 1: + case (sub_mb_type) + 0:mvpBy <= (mb_num_v == 0)? mvy_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]); + 1: //8x4 + case (subMbPartIdx) + 0:mvpBy <= (mb_num_v == 0)? mvy_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]); + 1:mvpBy <= mvy_CurrMb1[7:0]; + default:mvpBy <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:mvpBy <= (mb_num_v == 0)? mvy_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]); + 1:mvpBy <= (mb_num_v == 0)? mvy_CurrMb1[7:0] :((MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[7:0]); + default:mvpBy <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvpBy <= (mb_num_v == 0)? mvy_CurrMb0[15:8]:((MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]); + 1:mvpBy <= (mb_num_v == 0)? mvy_CurrMb1[7:0] :((MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[7:0]); + 2:mvpBy <= mvy_CurrMb1[7:0]; + 3:mvpBy <= mvy_CurrMb1[15:8]; + endcase + endcase + 2: + case (sub_mb_type) + 0:mvpBy <= mvy_CurrMb0[23:16]; + 1: //8x4 + case (subMbPartIdx) + 0:mvpBy <= mvy_CurrMb0[23:16]; 1:mvpBy <= mvy_CurrMb2[7:0]; default:mvpBy <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:mvpBy <= mvy_CurrMb0[23:16]; 1:mvpBy <= mvy_CurrMb0[31:24]; default:mvpBy <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvpBy <= mvy_CurrMb0[23:16]; 1:mvpBy <= mvy_CurrMb0[31:24]; + 2:mvpBy <= mvy_CurrMb2[7:0]; 3:mvpBy <= mvy_CurrMb2[15:8]; + endcase + endcase + 3: + case (sub_mb_type) + 0:mvpBy <= mvy_CurrMb1[23:16]; + 1: //8x4 + case (subMbPartIdx) + 0:mvpBy <= mvy_CurrMb1[23:16]; 1:mvpBy <= mvy_CurrMb3[7:0]; default:mvpBy <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:mvpBy <= mvy_CurrMb1[23:16]; 1:mvpBy <= mvy_CurrMb1[31:24]; default:mvpBy <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvpBy <= mvy_CurrMb1[23:16]; 1:mvpBy <= mvy_CurrMb1[31:24]; + 2:mvpBy <= mvy_CurrMb3[7:0]; 3:mvpBy <= mvy_CurrMb3[15:8]; + endcase + endcase + endcase + else + mvpBy <= 0; + //------------- + //mvpCx + //------------- + //if C is not available,it can be predicted from D,then from A + always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state or mb_num or mb_num_h or mb_num_v + or mb_type_general or sub_mb_type or mbPartIdx or subMbPartIdx or compIdx + or MBTypeGen_mbAddrA[1] or MBTypeGen_mbAddrB[1] or MBTypeGen_mbAddrC[1] or MBTypeGen_mbAddrD + or mvx_mbAddrA or mvx_mbAddrB_dout or mvx_mbAddrC_dout or mvx_mbAddrD + or mvx_CurrMb0 or mvx_CurrMb1 or mvx_CurrMb2 or mvx_CurrMb3 + or refIdxL0_A or refIdxL0_B or refIdxL0_C) + //P_skip,Inter16x16 + if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0)) + begin + if (mb_num == 0) mvpCx <= 0; + else if (mb_num_v == 0) mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0]; + else if (mb_num_h == 10) mvpCx <= (MBTypeGen_mbAddrD == 1)? 0:mvx_mbAddrD; + else mvpCx <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvx_mbAddrC_dout; + end + //Inter16x8 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0) + begin + if (mbPartIdx == 0) + mvpCx <= (refIdxL0_B && !refIdxL0_C)? ((mb_num_h == 10)? mvx_mbAddrD:mvx_mbAddrC_dout):0; + else + mvpCx <= 0; + end + //Inter8x16 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 0) + begin + //when mbAddrA is not available,Inter8x16 left blk needs to have its mbAddrC (= mbAddrB of upper line) derived + if (mbPartIdx == 0) //left blk + mvpCx <= (refIdxL0_A && !refIdxL0_B)? mvx_mbAddrB_dout[15:8]:0; + else //right blk + begin + if (mb_num == 0) mvpCx <= 0; + else if (mb_num_v == 0) mvpCx <= mvx_CurrMb0[15:8]; + else if (mb_num_h == 10) mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16]; + else mvpCx <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvx_mbAddrC_dout; + end + end + //Inter8x8 + else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0) + case (mbPartIdx) + 0: + case (sub_mb_type) + 0:if (mb_num == 0) mvpCx <= 0; + else if (mb_num_v == 0) mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0]; + else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]; + 1: //8x4 + case (subMbPartIdx) + 0:if (mb_num == 0) mvpCx <= 0; + else if (mb_num_v == 0) mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0]; + else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]; + 1:if (mb_num_h == 0) mvpCx <= 0; + else mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrD; + default:mvpCx <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:if (mb_num == 0) mvpCx <= 0; + else if (mb_num_v == 0) mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0]; + else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16]; + 1:if (mb_num_v == 0) mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_CurrMb0[7:0]; + else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]; + default:mvpCx <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:if (mb_num == 0) mvpCx <= 0; + else if (mb_num_v == 0) mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrA[7:0]; + else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16]; + 1:if (mb_num_v == 0) mvpCx <= mvx_CurrMb0[7:0]; + else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]; + 2:mvpCx <= mvx_CurrMb0[15:8]; //always available + 3:mvpCx <= mvx_CurrMb0[7:0]; //always from D + endcase + endcase + 1: + case (sub_mb_type) + 0:if (mb_num_v == 0) mvpCx <= mvx_CurrMb0[15:8]; + else if (mb_num_h == 10) //predicted from D,but lies initial mbAddrB + mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16]; + else mvpCx <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvx_mbAddrC_dout; + 1: //8x4 + case (subMbPartIdx) + 0:if (mb_num_v == 0) mvpCx <= mvx_CurrMb0[15:8]; + else if (mb_num_h == 10) //predicted from D,but lies initial mbAddrB + mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[23:16]; + else mvpCx <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvx_mbAddrC_dout; + 1:mvpCx <= mvx_CurrMb0[15:8]; //C is always unavailable,D is always available + default:mvpCx <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:if (mb_num_v == 0) mvpCx <= mvx_CurrMb0[15:8]; + else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[7:0]; + 1:if (mb_num_v == 0) mvpCx <= mvx_CurrMb1[7:0]; + else if (mb_num_h == 10) //predicted from D,but lies in mbAddrB + mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]; + else mvpCx <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvx_mbAddrC_dout; + default:mvpCx <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:if (mb_num_v == 0) mvpCx <= mvx_CurrMb0[15:8]; + else mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[7:0]; + 1:if (mb_num_v == 0) mvpCx <= mvx_CurrMb1[7:0]; + else if (mb_num_h == 10) //predicted from D,but lies initial mbAddrB + mvpCx <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvx_mbAddrB_dout[15:8]; + else mvpCx <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvx_mbAddrC_dout; + 2:mvpCx <= mvx_CurrMb1[15:8]; + 3:mvpCx <= mvx_CurrMb1[7:0]; + endcase + endcase + 2: + case (sub_mb_type) + 0:mvpCx <= mvx_CurrMb1[23:16]; + 1: //8x4 + case (subMbPartIdx) + 0:mvpCx <= mvx_CurrMb1[23:16]; + 1:if (mb_num_h == 0) mvpCx <= 0; + else mvpCx <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvx_mbAddrD; + default:mvpCx <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:mvpCx <= mvx_CurrMb0[31:24]; 1:mvpCx <= mvx_CurrMb1[23:16]; default:mvpCx <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvpCx <= mvx_CurrMb0[31:24]; 1:mvpCx <= mvx_CurrMb1[23:16]; + 2:mvpCx <= mvx_CurrMb2[15:8]; 3:mvpCx <= mvx_CurrMb2[7:0]; + endcase + endcase + 3: + case (sub_mb_type) + 0:mvpCx <= mvx_CurrMb0[31:24]; + 1: //8x4 + case (subMbPartIdx) + 0:mvpCx <= mvx_CurrMb0[31:24]; 1:mvpCx <= mvx_CurrMb2[15:8]; default:mvpCx <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:mvpCx <= mvx_CurrMb1[31:24]; 1:mvpCx <= mvx_CurrMb1[23:16]; default:mvpCx <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvpCx <= mvx_CurrMb1[31:24]; 1:mvpCx <= mvx_CurrMb1[23:16]; + 2:mvpCx <= mvx_CurrMb3[15:8]; 3:mvpCx <= mvx_CurrMb3[7:0]; + endcase + endcase + endcase + else + mvpCx <= 0; + //------------- + //mvpCy + //------------- + //if C is not available,it can be predicted from D,then from A + always @ (Is_skipMB_mv_calc or mb_pred_state or sub_mb_pred_state or mb_num or mb_num_h or mb_num_v + or mb_type_general or sub_mb_type or mbPartIdx or subMbPartIdx or compIdx + or MBTypeGen_mbAddrA[1] or MBTypeGen_mbAddrB[1] or MBTypeGen_mbAddrC[1] or MBTypeGen_mbAddrD + or mvy_mbAddrA or mvy_mbAddrB_dout or mvy_mbAddrC_dout or mvy_mbAddrD + or mvy_CurrMb0 or mvy_CurrMb1 or mvy_CurrMb2 or mvy_CurrMb3 + or refIdxL0_A or refIdxL0_B or refIdxL0_C) + //P_skip,Inter16x16 + if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1)) + begin + if (mb_num == 0) mvpCy <= 0; + else if (mb_num_v == 0) mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0]; + else if (mb_num_h == 10) mvpCy <= (MBTypeGen_mbAddrD == 1)? 0:mvy_mbAddrD; + else mvpCy <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvy_mbAddrC_dout; + end + //Inter16x8 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1) + begin + if (mbPartIdx == 0) + mvpCy <= (refIdxL0_B && !refIdxL0_C)? ((mb_num_h == 10)? mvy_mbAddrD:mvy_mbAddrC_dout):0; + else + mvpCy <= 0; + end + //Inter8x16 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 1) + begin + //when mbAddrA is not available,Inter8x16 left blk needs to have its mbAddrC (= mbAddrB of upper line) derived + if (mbPartIdx == 0) //left blk + mvpCy <= (refIdxL0_A && !refIdxL0_B)? mvy_mbAddrB_dout[15:8]:0; + else //right blk + begin + if (mb_num == 0) mvpCy <= 0; + else if (mb_num_v == 0) mvpCy <= mvy_CurrMb0[15:8]; + else if (mb_num_h == 10) mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16]; + else mvpCy <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvy_mbAddrC_dout; + end + end + //Inter8x8 + else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1) + case (mbPartIdx) + 0: + case (sub_mb_type) + 0:if (mb_num == 0) mvpCy <= 0; + else if (mb_num_v == 0) mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0]; + else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]; + 1: //8x4 + case (subMbPartIdx) + 0:if (mb_num == 0) mvpCy <= 0; + else if (mb_num_v == 0) mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0]; + else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]; + 1:if (mb_num_h == 0) mvpCy <= 0; + else mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrD; + default:mvpCy <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:if (mb_num == 0) mvpCy <= 0; + else if (mb_num_v == 0) mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0]; + else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16]; + 1:if (mb_num_v == 0) mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_CurrMb0[7:0]; + else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]; + default:mvpCy <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:if (mb_num == 0) mvpCy <= 0; + else if (mb_num_v == 0) mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrA[7:0]; + else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16]; + 1:if (mb_num_v == 0) mvpCy <= mvy_CurrMb0[7:0]; + else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]; + 2:mvpCy <= mvy_CurrMb0[15:8]; //always available + 3:mvpCy <= mvy_CurrMb0[7:0]; //always from D + endcase + endcase + 1: + case (sub_mb_type) + 0:if (mb_num_v == 0) mvpCy <= mvy_CurrMb0[15:8]; + else if (mb_num_h == 10) //predicted from D,but lies initial mbAddrB + mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16]; + else mvpCy <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvy_mbAddrC_dout; + 1: //8x4 + case (subMbPartIdx) + 0:if (mb_num_v == 0) mvpCy <= mvy_CurrMb0[15:8]; + else if (mb_num_h == 10) //predicted from D,but lies initial mbAddrB + mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[23:16]; + else mvpCy <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvy_mbAddrC_dout; + 1:mvpCy <= mvy_CurrMb0[15:8]; //C is always unavailable,D is always available + default:mvpCy <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:if (mb_num_v == 0) mvpCy <= mvy_CurrMb0[15:8]; + else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[7:0]; + 1:if (mb_num_v == 0) mvpCy <= mvy_CurrMb1[7:0]; + else if (mb_num_h == 10) //predicted from D,but lies in mbAddrB + mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]; + else mvpCy <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvy_mbAddrC_dout; + default:mvpCy <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:if (mb_num_v == 0) mvpCy <= mvy_CurrMb0[15:8]; + else mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[7:0]; + 1:if (mb_num_v == 0) mvpCy <= mvy_CurrMb1[7:0]; + else if (mb_num_h == 10) //predicted from D,but lies initial mbAddrB + mvpCy <= (MBTypeGen_mbAddrB[1] == 1)? 0:mvy_mbAddrB_dout[15:8]; + else mvpCy <= (MBTypeGen_mbAddrC[1] == 1)? 0:mvy_mbAddrC_dout; + 2:mvpCy <= mvy_CurrMb1[15:8]; + 3:mvpCy <= mvy_CurrMb1[7:0]; + endcase + endcase + 2: + case (sub_mb_type) + 0:mvpCy <= mvy_CurrMb1[23:16]; + 1: //8x4 + case (subMbPartIdx) + 0:mvpCy <= mvy_CurrMb1[23:16]; + 1:if (mb_num_h == 0) mvpCy <= 0; + else mvpCy <= (MBTypeGen_mbAddrA[1] == 1)? 0:mvy_mbAddrD; + default:mvpCy <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:mvpCy <= mvy_CurrMb0[31:24]; 1:mvpCy <= mvy_CurrMb1[23:16]; default:mvpCy <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvpCy <= mvy_CurrMb0[31:24]; 1:mvpCy <= mvy_CurrMb1[23:16]; + 2:mvpCy <= mvy_CurrMb2[15:8]; 3:mvpCy <= mvy_CurrMb2[7:0]; + endcase + endcase + 3: + case (sub_mb_type) + 0:mvpCy <= mvy_CurrMb0[31:24]; + 1: //8x4 + case (subMbPartIdx) + 0:mvpCy <= mvy_CurrMb0[31:24]; 1:mvpCy <= mvy_CurrMb2[15:8]; default:mvpCy <= 0; + endcase + 2: //4x8 + case (subMbPartIdx) + 0:mvpCy <= mvy_CurrMb1[31:24]; 1:mvpCy <= mvy_CurrMb1[23:16]; default:mvpCy <= 0; + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvpCy <= mvy_CurrMb1[31:24]; 1:mvpCy <= mvy_CurrMb1[23:16]; + 2:mvpCy <= mvy_CurrMb3[15:8]; 3:mvpCy <= mvy_CurrMb3[7:0]; + endcase + endcase + endcase + else + mvpCy <= 0; + //------------------------------------------------ + //obtain motion vector prediction for current Blk + //------------------------------------------------ + wire [8:0] sub_ABx,sub_ACx,sub_BCx; + wire flag_ABx,flag_ACx,flag_BCx; + assign sub_ABx = {mvpAx[7],mvpAx[7:0]} - {mvpBx[7],mvpBx[7:0]}; + assign sub_ACx = {mvpAx[7],mvpAx[7:0]} - {mvpCx[7],mvpCx[7:0]}; + assign sub_BCx = {mvpBx[7],mvpBx[7:0]} - {mvpCx[7],mvpCx[7:0]}; + assign flag_ABx = sub_ABx[8]; + assign flag_ACx = sub_ACx[8]; + assign flag_BCx = sub_BCx[8]; + + reg [7:0] mvpx_median; + always @ (flag_ABx or flag_ACx or flag_BCx or mvpAx or mvpBx or mvpCx) + if (((flag_ABx == 1'b1) && (flag_ACx == 1'b0)) || ((flag_ABx == 1'b0) && (flag_ACx == 1'b1))) + mvpx_median <= mvpAx; + else if (((flag_ABx == 1'b0) && (flag_BCx == 1'b0)) || ((flag_ABx == 1'b1) && (flag_BCx == 1'b1))) + mvpx_median <= mvpBx; + else + mvpx_median <= mvpCx; + + always @ (refIdxL0_A or refIdxL0_B or refIdxL0_C or mvpAx or mvpBx or mvpCx or mvpx_median) + case ({refIdxL0_A,refIdxL0_B,refIdxL0_C}) + 3'b011:mvpx <= mvpAx; + 3'b101:mvpx <= mvpBx; + 3'b110:mvpx <= mvpCx; + default:mvpx <= mvpx_median; + endcase + + wire [8:0] sub_ABy,sub_ACy,sub_BCy; + wire flag_ABy,flag_ACy,flag_BCy; + assign sub_ABy = {mvpAy[7],mvpAy[7:0]} - {mvpBy[7],mvpBy[7:0]}; + assign sub_ACy = {mvpAy[7],mvpAy[7:0]} - {mvpCy[7],mvpCy[7:0]}; + assign sub_BCy = {mvpBy[7],mvpBy[7:0]} - {mvpCy[7],mvpCy[7:0]}; + assign flag_ABy = sub_ABy[8]; + assign flag_ACy = sub_ACy[8]; + assign flag_BCy = sub_BCy[8]; + + reg [7:0] mvpy_median; + always @ (flag_ABy or flag_ACy or flag_BCy or mvpAy or mvpBy or mvpCy) + if (((flag_ABy == 1'b1) && (flag_ACy == 1'b0)) || ((flag_ABy == 1'b0) && (flag_ACy == 1'b1))) + mvpy_median <= mvpAy; + else if (((flag_ABy == 1'b0) && (flag_BCy == 1'b0)) || ((flag_ABy == 1'b1) && (flag_BCy == 1'b1))) + mvpy_median <= mvpBy; + else + mvpy_median <= mvpCy; + + always @ (refIdxL0_A or refIdxL0_B or refIdxL0_C or mvpAy or mvpBy or mvpCy or mvpy_median) + case ({refIdxL0_A,refIdxL0_B,refIdxL0_C}) + 3'b011:mvpy <= mvpAy; + 3'b101:mvpy <= mvpBy; + 3'b110:mvpy <= mvpCy; + default:mvpy <= mvpy_median; + endcase + + always @ (Is_skipMB_mv_calc or mb_num_h or mb_num_v or mb_pred_state or sub_mb_pred_state or compIdx or mvpx or mvpy + or mvd or mvpAx or mvpBx or mvpCx or mvpAy or mvpBy or mvpCy or mb_type_general or mbPartIdx + or refIdxL0_A or refIdxL0_B or refIdxL0_C) + if (Is_skipMB_mv_calc) + begin + //Refer to Page113,section 8.4.1.1 of H.264/AVC 2003.05 standard + if (mb_num_h == 0 || mb_num_v == 0 || (refIdxL0_A == 0 && mvpAx == 0 && mvpAy == 0) || + (refIdxL0_B == 0 && mvpBx == 0 && mvpBy == 0)) + begin mvx <= 0; mvy <= 0; end + else + begin mvx <= mvpx; mvy <= mvpy; end + end + else if (mb_pred_state == `mvd_l0_s || sub_mb_pred_state == `sub_mvd_l0_s) + begin + if (mb_type_general == `MB_Inter16x8) //16x8 + case (mbPartIdx) + 2'b00: //upper blk + if (!refIdxL0_B) + begin + mvx <= (compIdx == 0)? (mvpBx + mvd):0; + mvy <= (compIdx == 1)? (mvpBy + mvd):0; + end + else + begin + mvx <= (compIdx == 0)? (mvpx + mvd):0; + mvy <= (compIdx == 1)? (mvpy + mvd):0; + end + default: //bottom blk + if (!refIdxL0_A) + begin + mvx <= (compIdx == 0)? (mvpAx + mvd):0; + mvy <= (compIdx == 1)? (mvpAy + mvd):0; + end + else + begin + mvx <= (compIdx == 0)? (mvpx + mvd):0; + mvy <= (compIdx == 1)? (mvpy + mvd):0; + end + endcase + else if (mb_type_general == `MB_Inter8x16) //8x16 + case (mbPartIdx) + 2'b00: //left blk + if (!refIdxL0_A) + begin + mvx <= (compIdx == 0)? (mvpAx + mvd):0; + mvy <= (compIdx == 1)? (mvpAy + mvd):0; + end + else + begin + mvx <= (compIdx == 0)? (mvpx + mvd):0; + mvy <= (compIdx == 1)? (mvpy + mvd):0; + end + default: //right blk + //if mbAddrC is not available but mbAddrB (= mbAddrD) is INTER available (not only available,but also inter + //available),it still predicted from mbAddrC <- mbAddrD + if (!refIdxL0_C || (mb_num_h == 10 && !refIdxL0_B)) + begin + mvx <= (compIdx == 0)? (mvpCx + mvd):0; + mvy <= (compIdx == 1)? (mvpCy + mvd):0; + end + else + begin + mvx <= (compIdx == 0)? (mvpx + mvd):0; + mvy <= (compIdx == 1)? (mvpy + mvd):0; + end + endcase + else + begin + mvx <= (compIdx == 0)? (mvpx + mvd):0; + mvy <= (compIdx == 1)? (mvpy + mvd):0; + end + end + else + begin + mvx <= 0; mvy <= 0; + end + //----------------------------------------------------- + //Current MB write --> CurrMb0,CurrMb1,CurrMb2,CurrMb3 + //----------------------------------------------------- + always @ (posedge clk) + if (reset_n == 0) + mv_is16x16 <= 0; + else if (mb_type_general == `MB_Inter16x16 || mb_type_general == `MB_P_skip) + mv_is16x16 <= 1; + else + mv_is16x16 <= 0; + + always @ (posedge clk) + if (reset_n == 0) + begin + mvx_CurrMb0 <= 0; mvx_CurrMb1 <= 0; mvx_CurrMb2 <= 0; mvx_CurrMb3 <= 0; + end + //Inter16x16 or P_skip + else if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0)) + mvx_CurrMb0[7:0] <= mvx; + //Inter16x8 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0) + case (mbPartIdx) + 0:begin mvx_CurrMb0 <= {mvx,mvx,mvx,mvx}; mvx_CurrMb1 <= {mvx,mvx,mvx,mvx}; end + 1:begin mvx_CurrMb2 <= {mvx,mvx,mvx,mvx}; mvx_CurrMb3 <= {mvx,mvx,mvx,mvx}; end + endcase + //Inter8x16 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 0) + case (mbPartIdx) + 0:begin mvx_CurrMb0 <= {mvx,mvx,mvx,mvx}; mvx_CurrMb2 <= {mvx,mvx,mvx,mvx}; end + 1:begin mvx_CurrMb1 <= {mvx,mvx,mvx,mvx}; mvx_CurrMb3 <= {mvx,mvx,mvx,mvx}; end + endcase + //Inter8x8 + else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0) + case (mbPartIdx) + 0: + case (sub_mb_type) + 0:mvx_CurrMb0 <= {mvx,mvx,mvx,mvx}; + 1: //8x4 + case (subMbPartIdx) + 0:begin mvx_CurrMb0[7:0] <= mvx; mvx_CurrMb0[15:8] <= mvx; end + 1:begin mvx_CurrMb0[23:16] <= mvx; mvx_CurrMb0[31:24] <= mvx; end + endcase + 2: //4x8 + case (subMbPartIdx) + 0:begin mvx_CurrMb0[7:0] <= mvx; mvx_CurrMb0[23:16] <= mvx; end + 1:begin mvx_CurrMb0[15:8] <= mvx; mvx_CurrMb0[31:24] <= mvx; end + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvx_CurrMb0[7:0] <= mvx; + 1:mvx_CurrMb0[15:8] <= mvx; + 2:mvx_CurrMb0[23:16] <= mvx; + 3:mvx_CurrMb0[31:24] <= mvx; + endcase + endcase + 1: + case (sub_mb_type) + 0:mvx_CurrMb1 <= {mvx,mvx,mvx,mvx}; + 1: //8x4 + case (subMbPartIdx) + 0:begin mvx_CurrMb1[7:0] <= mvx; mvx_CurrMb1[15:8] <= mvx; end + 1:begin mvx_CurrMb1[23:16] <= mvx; mvx_CurrMb1[31:24] <= mvx; end + endcase + 2: //4x8 + case (subMbPartIdx) + 0:begin mvx_CurrMb1[7:0] <= mvx; mvx_CurrMb1[23:16] <= mvx; end + 1:begin mvx_CurrMb1[15:8] <= mvx; mvx_CurrMb1[31:24] <= mvx; end + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvx_CurrMb1[7:0] <= mvx; + 1:mvx_CurrMb1[15:8] <= mvx; + 2:mvx_CurrMb1[23:16] <= mvx; + 3:mvx_CurrMb1[31:24] <= mvx; + endcase + endcase + 2: + case (sub_mb_type) + 0:mvx_CurrMb2 <= {mvx,mvx,mvx,mvx}; + 1: //8x4 + case (subMbPartIdx) + 0:begin mvx_CurrMb2[7:0] <= mvx; mvx_CurrMb2[15:8] <= mvx; end + 1:begin mvx_CurrMb2[23:16] <= mvx; mvx_CurrMb2[31:24] <= mvx; end + endcase + 2: //4x8 + case (subMbPartIdx) + 0:begin mvx_CurrMb2[7:0] <= mvx; mvx_CurrMb2[23:16] <= mvx; end + 1:begin mvx_CurrMb2[15:8] <= mvx; mvx_CurrMb2[31:24] <= mvx; end + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvx_CurrMb2[7:0] <= mvx; + 1:mvx_CurrMb2[15:8] <= mvx; + 2:mvx_CurrMb2[23:16] <= mvx; + 3:mvx_CurrMb2[31:24] <= mvx; + endcase + endcase + 3: + case (sub_mb_type) + 0:mvx_CurrMb3 <= {mvx,mvx,mvx,mvx}; + 1: //8x4 + case (subMbPartIdx) + 0:begin mvx_CurrMb3[7:0] <= mvx; mvx_CurrMb3[15:8] <= mvx; end + 1:begin mvx_CurrMb3[23:16] <= mvx; mvx_CurrMb3[31:24] <= mvx; end + endcase + 2: //4x8 + case (subMbPartIdx) + 0:begin mvx_CurrMb3[7:0] <= mvx; mvx_CurrMb3[23:16] <= mvx; end + 1:begin mvx_CurrMb3[15:8] <= mvx; mvx_CurrMb3[31:24] <= mvx; end + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvx_CurrMb3[7:0] <= mvx; + 1:mvx_CurrMb3[15:8] <= mvx; + 2:mvx_CurrMb3[23:16] <= mvx; + 3:mvx_CurrMb3[31:24] <= mvx; + endcase + endcase + endcase + always @ (posedge clk) + if (reset_n == 0) + begin + mvy_CurrMb0 <= 0; mvy_CurrMb1 <= 0; mvy_CurrMb2 <= 0; mvy_CurrMb3 <= 0; + end + //Inter16x16 or P_skip + else if (Is_skipMB_mv_calc || (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1)) + begin + mvy_CurrMb0[7:0] <= mvy; + end + //Inter16x8 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1) + case (mbPartIdx) + 0:begin mvy_CurrMb0 <= {mvy,mvy,mvy,mvy}; mvy_CurrMb1 <= {mvy,mvy,mvy,mvy}; end + 1:begin mvy_CurrMb2 <= {mvy,mvy,mvy,mvy}; mvy_CurrMb3 <= {mvy,mvy,mvy,mvy}; end + endcase + //Inter8x16 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 1) + case (mbPartIdx) + 0:begin mvy_CurrMb0 <= {mvy,mvy,mvy,mvy}; mvy_CurrMb2 <= {mvy,mvy,mvy,mvy}; end + 1:begin mvy_CurrMb1 <= {mvy,mvy,mvy,mvy}; mvy_CurrMb3 <= {mvy,mvy,mvy,mvy}; end + endcase + //Inter8x8 + else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1) + case (mbPartIdx) + 0: + case (sub_mb_type) + 0:mvy_CurrMb0 <= {mvy,mvy,mvy,mvy}; + 1: //8x4 + case (subMbPartIdx) + 0:begin mvy_CurrMb0[7:0] <= mvy; mvy_CurrMb0[15:8] <= mvy; end + 1:begin mvy_CurrMb0[23:16] <= mvy; mvy_CurrMb0[31:24] <= mvy; end + endcase + 2: //4x8 + case (subMbPartIdx) + 0:begin mvy_CurrMb0[7:0] <= mvy; mvy_CurrMb0[23:16] <= mvy; end + 1:begin mvy_CurrMb0[15:8] <= mvy; mvy_CurrMb0[31:24] <= mvy; end + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvy_CurrMb0[7:0] <= mvy; + 1:mvy_CurrMb0[15:8] <= mvy; + 2:mvy_CurrMb0[23:16] <= mvy; + 3:mvy_CurrMb0[31:24] <= mvy; + endcase + endcase + 1: + case (sub_mb_type) + 0:mvy_CurrMb1 <= {mvy,mvy,mvy,mvy}; + 1: //8x4 + case (subMbPartIdx) + 0:begin mvy_CurrMb1[7:0] <= mvy; mvy_CurrMb1[15:8] <= mvy; end + 1:begin mvy_CurrMb1[23:16] <= mvy; mvy_CurrMb1[31:24] <= mvy; end + endcase + 2: //4x8 + case (subMbPartIdx) + 0:begin mvy_CurrMb1[7:0] <= mvy; mvy_CurrMb1[23:16] <= mvy; end + 1:begin mvy_CurrMb1[15:8] <= mvy; mvy_CurrMb1[31:24] <= mvy; end + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvy_CurrMb1[7:0] <= mvy; + 1:mvy_CurrMb1[15:8] <= mvy; + 2:mvy_CurrMb1[23:16] <= mvy; + 3:mvy_CurrMb1[31:24] <= mvy; + endcase + endcase + 2: + case (sub_mb_type) + 0:mvy_CurrMb2 <= {mvy,mvy,mvy,mvy}; + 1: //8x4 + case (subMbPartIdx) + 0:begin mvy_CurrMb2[7:0] <= mvy; mvy_CurrMb2[15:8] <= mvy; end + 1:begin mvy_CurrMb2[23:16] <= mvy; mvy_CurrMb2[31:24] <= mvy; end + endcase + 2: //4x8 + case (subMbPartIdx) + 0:begin mvy_CurrMb2[7:0] <= mvy; mvy_CurrMb2[23:16] <= mvy; end + 1:begin mvy_CurrMb2[15:8] <= mvy; mvy_CurrMb2[31:24] <= mvy; end + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvy_CurrMb2[7:0] <= mvy; + 1:mvy_CurrMb2[15:8] <= mvy; + 2:mvy_CurrMb2[23:16] <= mvy; + 3:mvy_CurrMb2[31:24] <= mvy; + endcase + endcase + 3: + case (sub_mb_type) + 0:mvy_CurrMb3 <= {mvy,mvy,mvy,mvy}; + 1: //8x4 + case (subMbPartIdx) + 0:begin mvy_CurrMb3[7:0] <= mvy; mvy_CurrMb3[15:8] <= mvy; end + 1:begin mvy_CurrMb3[23:16] <= mvy; mvy_CurrMb3[31:24] <= mvy; end + endcase + 2: //4x8 + case (subMbPartIdx) + 0:begin mvy_CurrMb3[7:0] <= mvy; mvy_CurrMb3[23:16] <= mvy; end + 1:begin mvy_CurrMb3[15:8] <= mvy; mvy_CurrMb3[31:24] <= mvy; end + endcase + 3: //4x4 + case (subMbPartIdx) + 0:mvy_CurrMb3[7:0] <= mvy; + 1:mvy_CurrMb3[15:8] <= mvy; + 2:mvy_CurrMb3[23:16] <= mvy; + 3:mvy_CurrMb3[31:24] <= mvy; + endcase + endcase + endcase + //---------------------------- + //mbAddrA write --> mvx_mbAddrA + //---------------------------- + always @ (posedge clk) + if (reset_n == 0) + mvx_mbAddrA <= 0; + else if (mb_num_h != 10)//if mb_num_h == 10,mvx_mbAddrA will be no use + begin + //P_skip + if (slice_data_state == `skip_run_duration && end_of_MB_DEC) + mvx_mbAddrA <= {mvx_CurrMb0[7:0],mvx_CurrMb0[7:0],mvx_CurrMb0[7:0],mvx_CurrMb0[7:0]}; + //Inter16x16 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0) + mvx_mbAddrA <= {mvx,mvx,mvx,mvx}; + //Inter16x8 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0) + case (mbPartIdx) + 0:begin mvx_mbAddrA[15:8] <= mvx; mvx_mbAddrA[7:0] <= mvx; end + 1:begin mvx_mbAddrA[23:16] <= mvx; mvx_mbAddrA[31:24] <= mvx; end + endcase + //Inter8x16 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && mbPartIdx == 1 && compIdx == 0) + mvx_mbAddrA <= {mvx,mvx,mvx,mvx}; + //Inter8x8 + else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0) + case (mbPartIdx) + 1: + case (sub_mb_type) + 0:begin mvx_mbAddrA[15:8] <= mvx; mvx_mbAddrA[7:0] <= mvx; end + 1:if (subMbPartIdx == 0) mvx_mbAddrA[7:0] <= mvx; + else mvx_mbAddrA[15:8] <= mvx; + 2:if (subMbPartIdx == 1) begin mvx_mbAddrA[15:8] <= mvx; mvx_mbAddrA[7:0] <= mvx;end + 3:if (subMbPartIdx == 1) mvx_mbAddrA[7:0] <= mvx; + else if (subMbPartIdx == 3) mvx_mbAddrA[15:8] <= mvx; + endcase + 3: + case (sub_mb_type) + 0:begin mvx_mbAddrA[23:16] <= mvx; mvx_mbAddrA[31:24] <= mvx; end + 1:if (subMbPartIdx == 0) mvx_mbAddrA[23:16] <= mvx; + else mvx_mbAddrA[31:24] <= mvx; + 2:if (subMbPartIdx == 1) begin mvx_mbAddrA[23:16] <= mvx; mvx_mbAddrA[31:24] <= mvx;end + 3:if (subMbPartIdx == 1) mvx_mbAddrA[23:16] <= mvx; + else if (subMbPartIdx == 3) mvx_mbAddrA[31:24] <= mvx; + endcase + endcase + end + always @ (posedge clk) + if (reset_n == 0) + mvy_mbAddrA <= 0; + else if (mb_num_h != 10)//if mb_num_h == 10,mvy_mbAddrA will be no use + begin + //P_skip + if (slice_data_state == `skip_run_duration && end_of_MB_DEC) + mvy_mbAddrA <= {mvy_CurrMb0[7:0],mvy_CurrMb0[7:0],mvy_CurrMb0[7:0],mvy_CurrMb0[7:0]}; + //Inter16x16 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1) + mvy_mbAddrA <= {mvy,mvy,mvy,mvy}; + //Inter16x8 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1) + case (mbPartIdx) + 0:begin mvy_mbAddrA[15:8] <= mvy; mvy_mbAddrA[7:0] <= mvy; end + 1:begin mvy_mbAddrA[23:16] <= mvy; mvy_mbAddrA[31:24] <= mvy; end + endcase + //Inter8x16 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && mbPartIdx == 1 && compIdx == 1) + mvy_mbAddrA <= {mvy,mvy,mvy,mvy}; + //Inter8x8 + else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1) + case (mbPartIdx) + 1: + case (sub_mb_type) + 0:begin mvy_mbAddrA[15:8] <= mvy; mvy_mbAddrA[7:0] <= mvy; end + 1:if (subMbPartIdx == 0) mvy_mbAddrA[7:0] <= mvy; + else mvy_mbAddrA[15:8] <= mvy; + 2:if (subMbPartIdx == 1) begin mvy_mbAddrA[15:8] <= mvy; mvy_mbAddrA[7:0] <= mvy;end + 3:if (subMbPartIdx == 1) mvy_mbAddrA[7:0] <= mvy; + else if (subMbPartIdx == 3) mvy_mbAddrA[15:8] <= mvy; + endcase + 3: + case (sub_mb_type) + 0:begin mvy_mbAddrA[23:16] <= mvy; mvy_mbAddrA[31:24] <= mvy; end + 1:if (subMbPartIdx == 0) mvy_mbAddrA[23:16] <= mvy; + else mvy_mbAddrA[31:24] <= mvy; + 2:if (subMbPartIdx == 1) begin mvy_mbAddrA[23:16] <= mvy; mvy_mbAddrA[31:24] <= mvy;end + 3:if (subMbPartIdx == 1) mvy_mbAddrA[23:16] <= mvy; + else if (subMbPartIdx == 3) mvy_mbAddrA[31:24] <= mvy; + endcase + endcase + end + //----------------------------------------- + //mbAddrB RF read and write --> mvx_mbAddrB + //----------------------------------------- + always @ (reset_n or slice_data_state or mb_pred_state or sub_mb_pred_state or mv_mbAddrB_rd_for_DF + or Is_skipMB_mv_calc or end_of_MB_DEC or mb_type_general or sub_mb_type or mb_num_h or mb_num_v + or mbPartIdx or subMbPartIdx or compIdx or mvx or mvx_CurrMb0[7:0] or mvx_CurrMb2 or mvx_CurrMb3 + or refIdxL0_A or refIdxL0_C) + if (reset_n == 0) + begin + mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; + mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + //read for DF boundary strength decoding + else if (mv_mbAddrB_rd_for_DF) + begin + mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_rd_addr <= mb_num_h; + mvx_mbAddrB_wr_n <= 1; mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + //P_skip + else if (slice_data_state == `skip_run_duration) + begin + if (Is_skipMB_mv_calc) //read + begin + if (mb_num_v == 0) + begin mvx_mbAddrB_cs_n <= 1;mvx_mbAddrB_rd_addr <= 0; end + else + begin mvx_mbAddrB_cs_n <= 0;mvx_mbAddrB_rd_addr <= mb_num_h;end + mvx_mbAddrB_wr_n <= 1; + mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + else if (end_of_MB_DEC) //write + begin + if (mb_num_v == 8) + begin + mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; + mvx_mbAddrB_wr_addr <= 0; mvx_mbAddrB_din <= 0; + end + else + begin + mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0; + mvx_mbAddrB_wr_addr <= mb_num_h; + mvx_mbAddrB_din <= {mvx_CurrMb0[7:0],mvx_CurrMb0[7:0],mvx_CurrMb0[7:0],mvx_CurrMb0[7:0]}; + end + mvx_mbAddrB_rd_addr <= 0; + end + else + begin + mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; + mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + end + //Inter16x16 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0) + begin + if (mb_num_v == 0) //!read,write + begin + mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0; + mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= mb_num_h; + mvx_mbAddrB_din <= {mvx,mvx,mvx,mvx}; + end + else if (mb_num_v == 8) //read,!write + begin + mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_rd_addr <= mb_num_h; + mvx_mbAddrB_wr_n <= 1; mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + else //read,write + begin + mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_rd_addr <= mb_num_h; + mvx_mbAddrB_wr_n <= 0; mvx_mbAddrB_wr_addr <= mb_num_h; + mvx_mbAddrB_din <= {mvx,mvx,mvx,mvx}; + end + end + //Inter16x8 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0) + case (mbPartIdx) + 0: //read,!write + begin + if (mb_num_v == 0) //!read,!write + begin + mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; + mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + else //read,!write + begin + mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 1; + mvx_mbAddrB_rd_addr <= mb_num_h; mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + end + 1: //!read,write + begin + if (mb_num_v == 8) //!read,!write + begin + mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_rd_addr <= mb_num_h; + mvx_mbAddrB_wr_n <= 1; mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + else //!read,write + begin + mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0; + mvx_mbAddrB_rd_addr <= mb_num_h; mvx_mbAddrB_wr_addr <= mb_num_h; + mvx_mbAddrB_din <= {mvx,mvx,mvx,mvx}; + end + end + default: + begin + mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; + mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + endcase + //Inter8x16 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 0) + case (mbPartIdx) + 0: //read when mbAddrA is not available for inter pred,!write + if (refIdxL0_A == 1'b1) + begin + mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 1; + mvx_mbAddrB_rd_addr <= mb_num_h;mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + else + begin + mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; + mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + 1: //need read :mb_num_h == 10 && mb_num_v != 0 + //need write:mb_num_v != 8 + begin + mvx_mbAddrB_cs_n <= ((mb_num_v != 8 || mb_num_h == 10) || (refIdxL0_C && mb_num_v != 0))? 1'b0:1'b1; + mvx_mbAddrB_wr_n <= (mb_num_v == 8)? 1'b1:1'b0; + mvx_mbAddrB_rd_addr <= mb_num_h; + mvx_mbAddrB_wr_addr <= mb_num_h; + mvx_mbAddrB_din <= {mvx_CurrMb2[23:16],mvx_CurrMb2[31:24],mvx,mvx}; + end + default: + begin + mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; + mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + endcase + //8x8 + else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0) + case (mbPartIdx) + 0,1: //read,!write + if (mb_num_v == 0) //!read,!write + begin + mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; + mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + else //read,!write + begin + mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 1; + mvx_mbAddrB_rd_addr <= mb_num_h; mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + 2: //!read,!write + begin + mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; + mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + 3: //!read,write + if (mb_num_v == 8) //!read,!write + begin + mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; + mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + else + case (sub_mb_type) + 0: //8x8 + begin + mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0; + mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= mb_num_h; + mvx_mbAddrB_din <= {mvx_CurrMb2[23:16],mvx_CurrMb2[31:24],mvx,mvx}; + end + 1: //8x4 + case (subMbPartIdx) + 1: + begin + mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0; + mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= mb_num_h; + mvx_mbAddrB_din <= {mvx_CurrMb2[23:16],mvx_CurrMb2[31:24],mvx,mvx}; + end + default: + begin + mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; + mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + endcase + 2: //4x8 + case (subMbPartIdx) + 1: + begin + mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0; + mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= mb_num_h; + mvx_mbAddrB_din <= {mvx_CurrMb2[23:16],mvx_CurrMb2[31:24],mvx_CurrMb3[23:16],mvx}; + end + default: + begin + mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; + mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + endcase + 3: //4x4 + case (subMbPartIdx) + 3: + begin + mvx_mbAddrB_cs_n <= 0; mvx_mbAddrB_wr_n <= 0; + mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= mb_num_h; + mvx_mbAddrB_din <= {mvx_CurrMb2[23:16],mvx_CurrMb2[31:24], + mvx_CurrMb3[23:16],mvx}; + end + default: + begin + mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; + mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + endcase + endcase + endcase + else + begin + mvx_mbAddrB_cs_n <= 1; mvx_mbAddrB_wr_n <= 1; + mvx_mbAddrB_rd_addr <= 0; mvx_mbAddrB_wr_addr <= 0; + mvx_mbAddrB_din <= 0; + end + + always @ (reset_n or slice_data_state or mb_pred_state or sub_mb_pred_state or mv_mbAddrB_rd_for_DF + or Is_skipMB_mv_calc or end_of_MB_DEC or mb_type_general or sub_mb_type or mb_num_h or mb_num_v + or mbPartIdx or subMbPartIdx or compIdx or mvy or mvy_CurrMb0[7:0] or mvy_CurrMb2 or mvy_CurrMb3 + or refIdxL0_A or refIdxL0_C) + if (reset_n == 0) + begin + mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; + mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + //read for DF boundary strength decoding + else if (mv_mbAddrB_rd_for_DF) + begin + mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_rd_addr <= mb_num_h; + mvy_mbAddrB_wr_n <= 1; mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + //P_skip + else if (slice_data_state == `skip_run_duration) + begin + if (Is_skipMB_mv_calc) //read + begin + if (mb_num_v == 0) + begin mvy_mbAddrB_cs_n <= 1;mvy_mbAddrB_rd_addr <= 0; end + else + begin mvy_mbAddrB_cs_n <= 0;mvy_mbAddrB_rd_addr <= mb_num_h;end + mvy_mbAddrB_wr_n <= 1; + mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + else if (end_of_MB_DEC) //write + begin + if (mb_num_v == 8) + begin + mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; + mvy_mbAddrB_wr_addr <= 0; mvy_mbAddrB_din <= 0; + end + else + begin + mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0; + mvy_mbAddrB_wr_addr <= mb_num_h; + mvy_mbAddrB_din <= {mvy_CurrMb0[7:0],mvy_CurrMb0[7:0],mvy_CurrMb0[7:0],mvy_CurrMb0[7:0]}; + end + mvy_mbAddrB_rd_addr <= 0; + end + else + begin + mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; + mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + end + //Inter16x16 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1) + begin + if (mb_num_v == 0) //!read,write + begin + mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0; + mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= mb_num_h; + mvy_mbAddrB_din <= {mvy,mvy,mvy,mvy}; + end + else if (mb_num_v == 8) //read,!write + begin + mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_rd_addr <= mb_num_h; + mvy_mbAddrB_wr_n <= 1; mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + else //read,write + begin + mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_rd_addr <= mb_num_h; + mvy_mbAddrB_wr_n <= 0; mvy_mbAddrB_wr_addr <= mb_num_h; + mvy_mbAddrB_din <= {mvy,mvy,mvy,mvy}; + end + end + //Inter16x8 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1) + case (mbPartIdx) + 0: //read,!write + begin + if (mb_num_v == 0) //!read,!write + begin + mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; + mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + else //read,!write + begin + mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 1; + mvy_mbAddrB_rd_addr <= mb_num_h; mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + end + 1: //!read,write + begin + if (mb_num_v == 8) //!read,!write + begin + mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_rd_addr <= mb_num_h; + mvy_mbAddrB_wr_n <= 1; mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + else //!read,write + begin + mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0; + mvy_mbAddrB_rd_addr <= mb_num_h; mvy_mbAddrB_wr_addr <= mb_num_h; + mvy_mbAddrB_din <= {mvy,mvy,mvy,mvy}; + end + end + default: + begin + mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; + mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + endcase + //Inter8x16 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 1) + case (mbPartIdx) + 0: //read when mbAddrA is not available for inter pred,!write + if (refIdxL0_A == 1'b1) + begin + mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 1; + mvy_mbAddrB_rd_addr <= mb_num_h;mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + else + begin + mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; + mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + 1: //need read :mb_num_h == 10 && mb_num_v != 0 + //need write:mb_num_v != 8 + begin + mvy_mbAddrB_cs_n <= ((mb_num_v != 8 || mb_num_h == 10) || (refIdxL0_C && mb_num_v != 0))? 1'b0:1'b1; + mvy_mbAddrB_wr_n <= (mb_num_v == 8)? 1'b1:1'b0; + mvy_mbAddrB_rd_addr <= mb_num_h; + mvy_mbAddrB_wr_addr <= mb_num_h; + mvy_mbAddrB_din <= {mvy_CurrMb2[23:16],mvy_CurrMb2[31:24],mvy,mvy}; + end + default: + begin + mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; + mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + endcase + //8x8 + else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1) + case (mbPartIdx) + 0,1: //read,!write + if (mb_num_v == 0) //!read,!write + begin + mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; + mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + else //read,!write + begin + mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 1; + mvy_mbAddrB_rd_addr <= mb_num_h; mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + 2: //!read,!write + begin + mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; + mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + 3: //!read,write + if (mb_num_v == 8) //!read,!write + begin + mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; + mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + else + case (sub_mb_type) + 0: //8x8 + begin + mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0; + mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= mb_num_h; + mvy_mbAddrB_din <= {mvy_CurrMb2[23:16],mvy_CurrMb2[31:24],mvy,mvy}; + end + 1: //8x4 + case (subMbPartIdx) + 1: + begin + mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0; + mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= mb_num_h; + mvy_mbAddrB_din <= {mvy_CurrMb2[23:16],mvy_CurrMb2[31:24],mvy,mvy}; + end + default: + begin + mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; + mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + endcase + 2: //4x8 + case (subMbPartIdx) + 1: + begin + mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0; + mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= mb_num_h; + mvy_mbAddrB_din <= {mvy_CurrMb2[23:16],mvy_CurrMb2[31:24],mvy_CurrMb3[23:16],mvy}; + end + default: + begin + mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; + mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + endcase + 3: //4x4 + case (subMbPartIdx) + 3: + begin + mvy_mbAddrB_cs_n <= 0; mvy_mbAddrB_wr_n <= 0; + mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= mb_num_h; + mvy_mbAddrB_din <= {mvy_CurrMb2[23:16],mvy_CurrMb2[31:24], + mvy_CurrMb3[23:16],mvy}; + end + default: + begin + mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; + mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + endcase + endcase + endcase + else + begin + mvy_mbAddrB_cs_n <= 1; mvy_mbAddrB_wr_n <= 1; + mvy_mbAddrB_rd_addr <= 0; mvy_mbAddrB_wr_addr <= 0; + mvy_mbAddrB_din <= 0; + end + //----------------------------------------- + //mbAddrC RF read and write --> mvx_mbAddrC + //----------------------------------------- + always @ (reset_n or slice_data_state or Is_skipMB_mv_calc or end_of_MB_DEC or mb_pred_state or sub_mb_type or sub_mb_pred_state + or mb_type_general or mb_num or mb_num_h or mb_num_v or mbPartIdx or subMbPartIdx or compIdx or mvx or mvx_CurrMb0[7:0] + or refIdxL0_B or refIdxL0_C) + if (reset_n == 0) + begin + mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + //P_skip + else if (slice_data_state == `skip_run_duration) + begin + if (Is_skipMB_mv_calc) //read + begin + if (mb_num_v == 0 || mb_num_h == 10)//!read,!write + begin mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_rd_addr <= 0; end + else + begin mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_rd_addr <= mb_num_h; end + mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + else if (end_of_MB_DEC) //write + begin + if (mb_num_v == 8 || mb_num_h == 0) //!write + begin + mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + else //write + begin + mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1; + mvx_mbAddrC_din <= mvx_CurrMb0[7:0]; + end + end + else + begin + mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + end + //Inter16x16 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 0) + begin + if (mb_num == 0)//!read,!write + begin + mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + else if (mb_num_v == 0)//!read,write + begin + mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1; + mvx_mbAddrC_din <= mvx; + end + else if (mb_num_h == 0 || mb_num_v == 8) //read,!write + begin + mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + else //read,write + begin + mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0; + mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= mb_num_h - 1; + mvx_mbAddrC_din <= mvx; + end + end + //Inter16x8 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 0) + begin + if (mbPartIdx == 0) //upper blk,may read,no write + begin + if (refIdxL0_B && !refIdxL0_C) //read,!write + begin + mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + else //!read,!write + begin + mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + end + else //bottom blk,may write,no read + begin + if (mb_num_h != 0) //!read,write + begin + mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1; + mvx_mbAddrC_din <= mvx; + end + else //!read,!write + begin + mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + end + end + //Inter8x16 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 0) + case (mbPartIdx) + 0: //!read,write + if (mb_num_v == 8) + begin + mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + else + begin + mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1; + mvx_mbAddrC_din <= mvx; + end + default: //read,!write + begin + if (mb_num_v == 0 || mb_num_h == 10) //!read,!write + begin + mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + else //read,!write + begin + mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + end + endcase + //Inter8x8 + else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0) + case (mbPartIdx) + 1: //read,!write + if (mb_num_v == 0 || mb_num_h == 10) //!read,!write + begin + mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + else //read,!write + case (sub_mb_type) + 0: //8x8 + begin + mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= mvx; + end + 1: //8x4 + case (subMbPartIdx) + 0: //read,!write + begin + mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= mvx; + end + default: //!read,!write + begin + mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + endcase + 2: //4x8 + case (subMbPartIdx) + 1: //read,!write + begin + mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= mvx; + end + default: //!read,!write + begin + mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + endcase + 3: //4x4 + case (subMbPartIdx) + 1: //read,!write + begin + mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= mb_num_h; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= mvx; + end + default: //!read,!write + begin + mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + endcase + endcase + 2: //!read,write + if (mb_num_h == 0 || mb_num_v == 8) //!read,!write + begin + mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + else //!read,write + case (sub_mb_type) + 0: //8x8 + begin + mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1; + mvx_mbAddrC_din <= mvx; + end + 1: //8x4 + case (subMbPartIdx) + 1: //!read,write + begin + mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1; + mvx_mbAddrC_din <= mvx; + end + default: //!read,!write + begin + mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + endcase + 2: //4x8 + case (subMbPartIdx) + 0: //!read,write + begin + mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1; + mvx_mbAddrC_din <= mvx; + end + default: //!read,!write + begin + mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + endcase + 3: //4x4 + case (subMbPartIdx) + 2: //!read,write + begin + mvx_mbAddrC_cs_n <= 0; mvx_mbAddrC_wr_n <= 0; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= mb_num_h - 1; + mvx_mbAddrC_din <= mvx; + end + default: //!read,!write + begin + mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + endcase + endcase + default: + begin + mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + endcase + else + begin + mvx_mbAddrC_cs_n <= 1; mvx_mbAddrC_wr_n <= 1; + mvx_mbAddrC_rd_addr <= 0; mvx_mbAddrC_wr_addr <= 0; + mvx_mbAddrC_din <= 0; + end + + always @ (reset_n or slice_data_state or Is_skipMB_mv_calc or end_of_MB_DEC or mb_pred_state or sub_mb_type or sub_mb_pred_state + or mb_type_general or mb_num or mb_num_h or mb_num_v or mbPartIdx or subMbPartIdx or compIdx or mvy or mvy_CurrMb0[7:0] + or refIdxL0_B or refIdxL0_C) + if (reset_n == 0) + begin + mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + //P_skip + else if (slice_data_state == `skip_run_duration) + begin + if (Is_skipMB_mv_calc) //read + begin + if (mb_num_v == 0 || mb_num_h == 10)//!read,!write + begin mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_rd_addr <= 0; end + else + begin mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_rd_addr <= mb_num_h; end + mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + else if (end_of_MB_DEC) //write + begin + if (mb_num_v == 8 || mb_num_h == 0) //!write + begin + mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + else //write + begin + mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1; + mvy_mbAddrC_din <= mvy_CurrMb0[7:0]; + end + end + else + begin + mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + end + //Inter16x16 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x16 && compIdx == 1) + begin + if (mb_num == 0)//!read,!write + begin + mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + else if (mb_num_v == 0)//!read,write + begin + mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1; + mvy_mbAddrC_din <= mvy; + end + else if (mb_num_h == 0 || mb_num_v == 8) //read,!write + begin + mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + else //read,write + begin + mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0; + mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= mb_num_h - 1; + mvy_mbAddrC_din <= mvy; + end + end + //Inter16x8 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter16x8 && compIdx == 1) + begin + if (mbPartIdx == 0) //upper blk,may read,no write + begin + if (refIdxL0_B && !refIdxL0_C) //read,!write + begin + mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + else //!read,!write + begin + mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + end + else //bottom blk,may write,no read + begin + if (mb_num_h != 0) //!read,write + begin + mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1; + mvy_mbAddrC_din <= mvy; + end + else //!read,!write + begin + mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + end + end + //Inter8x16 + else if (mb_pred_state == `mvd_l0_s && mb_type_general == `MB_Inter8x16 && compIdx == 1) + case (mbPartIdx) + 0: //!read,write + if (mb_num_v == 8) + begin + mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + else + begin + mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1; + mvy_mbAddrC_din <= mvy; + end + default: //read,!write + begin + if (mb_num_v == 0 || mb_num_h == 10) //!read,!write + begin + mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + else //read,!write + begin + mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + end + endcase + //Inter8x8 + else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 1) + case (mbPartIdx) + 1: //read,!write + if (mb_num_v == 0 || mb_num_h == 10) //!read,!write + begin + mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + else //read,!write + case (sub_mb_type) + 0: //8x8 + begin + mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= mvy; + end + 1: //8x4 + case (subMbPartIdx) + 0: //read,!write + begin + mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= mvy; + end + default: //!read,!write + begin + mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + endcase + 2: //4x8 + case (subMbPartIdx) + 1: //read,!write + begin + mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= mvy; + end + default: //!read,!write + begin + mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + endcase + 3: //4x4 + case (subMbPartIdx) + 1: //read,!write + begin + mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= mb_num_h; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= mvy; + end + default: //!read,!write + begin + mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + endcase + endcase + 2: //!read,write + if (mb_num_h == 0 || mb_num_v == 8) //!read,!write + begin + mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + else //!read,write + case (sub_mb_type) + 0: //8x8 + begin + mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1; + mvy_mbAddrC_din <= mvy; + end + 1: //8x4 + case (subMbPartIdx) + 1: //!read,write + begin + mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1; + mvy_mbAddrC_din <= mvy; + end + default: //!read,!write + begin + mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + endcase + 2: //4x8 + case (subMbPartIdx) + 0: //!read,write + begin + mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1; + mvy_mbAddrC_din <= mvy; + end + default: //!read,!write + begin + mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + endcase + 3: //4x4 + case (subMbPartIdx) + 2: //!read,write + begin + mvy_mbAddrC_cs_n <= 0; mvy_mbAddrC_wr_n <= 0; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= mb_num_h - 1; + mvy_mbAddrC_din <= mvy; + end + default: //!read,!write + begin + mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + endcase + endcase + default: + begin + mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + endcase + else + begin + mvy_mbAddrC_cs_n <= 1; mvy_mbAddrC_wr_n <= 1; + mvy_mbAddrC_rd_addr <= 0; mvy_mbAddrC_wr_addr <= 0; + mvy_mbAddrC_din <= 0; + end + + //------------------------------- + //mbAddrD write --> mvx_mbAddrD + //------------------------------- + //mvx_mbAddrD + reg [7:0] mvx_mbAddrD_subMB; + reg [7:0] mvx_mbAddrD_MB,mvx_mbAddrD_MB_tmp; + always @ (posedge clk) + if (reset_n == 0) + mvx_mbAddrD_subMB <= 0; + else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0) + case (mbPartIdx) + 0:if (sub_mb_type == 1 && subMbPartIdx == 0) //8x4 UpperBlk + mvx_mbAddrD_subMB <= mvx_mbAddrA[7:0]; + 2:if (sub_mb_type == 1 && subMbPartIdx == 0) //8x4 UpperBlk + mvx_mbAddrD_subMB <= mvx_mbAddrA[23:16]; + endcase + + always @ (posedge clk) + if (reset_n == 1'b0) + mvx_mbAddrD_MB_tmp <= 0; + else if (end_of_MB_DEC && mb_num_v != 8 && mb_num_h == 9 && mb_type_general[3] == 0) + mvx_mbAddrD_MB_tmp <= (mv_is16x16)? mvx_CurrMb0[7:0]:mvx_CurrMb3[31:24]; + + always @ (posedge clk) + if (reset_n == 1'b0) + mvx_mbAddrD_MB <= 0; + else if (end_of_MB_DEC && mb_num_h == 10) + mvx_mbAddrD_MB <= mvx_mbAddrD_MB_tmp; + + assign mvx_mbAddrD = ((mbPartIdx == 0 || mbPartIdx == 2) && sub_mb_type == 1 && subMbPartIdx == 1)? mvx_mbAddrD_subMB:mvx_mbAddrD_MB; + + //mvy_mbAddrD + reg [7:0] mvy_mbAddrD_subMB; + reg [7:0] mvy_mbAddrD_MB,mvy_mbAddrD_MB_tmp; + always @ (posedge clk) + if (reset_n == 0) + mvy_mbAddrD_subMB <= 0; + else if (sub_mb_pred_state == `sub_mvd_l0_s && compIdx == 0) + case (mbPartIdx) + 0:if (sub_mb_type == 1 && subMbPartIdx == 0) //8x4 UpperBlk + mvy_mbAddrD_subMB <= mvy_mbAddrA[7:0]; + 2:if (sub_mb_type == 1 && subMbPartIdx == 0) //8x4 UpperBlk + mvy_mbAddrD_subMB <= mvy_mbAddrA[23:16]; + endcase + + always @ (posedge clk) + if (reset_n == 1'b0) + mvy_mbAddrD_MB_tmp <= 0; + else if (end_of_MB_DEC && mb_num_v != 8 && mb_num_h == 9 && mb_type_general[3] == 0) + mvy_mbAddrD_MB_tmp <= (mv_is16x16)? mvy_CurrMb0[7:0]:mvy_CurrMb3[31:24]; + + always @ (posedge clk) + if (reset_n == 1'b0) + mvy_mbAddrD_MB <= 0; + else if (end_of_MB_DEC && mb_num_h == 10) + mvy_mbAddrD_MB <= mvy_mbAddrD_MB_tmp; + + assign mvy_mbAddrD = ((mbPartIdx == 0 || mbPartIdx == 2) && sub_mb_type == 1 && subMbPartIdx == 1)? mvy_mbAddrD_subMB:mvy_mbAddrD_MB; + +endmodule \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/Inter_pred_CPE.v b/demo_chip_rtl/rtl/nova/trunk/src/Inter_pred_CPE.v new file mode 100644 index 0000000..82a7c0f --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/Inter_pred_CPE.v @@ -0,0 +1,150 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : Inter_pred_CPE.v +// Generated : Oct 14, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Processing Element for Inter prediction of Chroma pixels +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module Inter_pred_CPE (xFracC,yFracC, + Inter_C_window_0_0,Inter_C_window_1_0,Inter_C_window_2_0, + Inter_C_window_0_1,Inter_C_window_1_1,Inter_C_window_2_1, + Inter_C_window_0_2,Inter_C_window_1_2,Inter_C_window_2_2, + CPE0_out,CPE1_out,CPE2_out,CPE3_out); + input [2:0] xFracC,yFracC; + input [7:0] Inter_C_window_0_0,Inter_C_window_1_0,Inter_C_window_2_0; + input [7:0] Inter_C_window_0_1,Inter_C_window_1_1,Inter_C_window_2_1; + input [7:0] Inter_C_window_0_2,Inter_C_window_1_2,Inter_C_window_2_2; + output [7:0] CPE0_out,CPE1_out,CPE2_out,CPE3_out; + + wire [3:0] xFracC_n,yFracC_n; + assign xFracC_n = 4'b1000 - xFracC; + assign yFracC_n = 4'b1000 - yFracC; + + CPE CPE0 ( + .xFracC(xFracC), + .yFracC(yFracC), + .xFracC_n(xFracC_n), + .yFracC_n(yFracC_n), + .a(Inter_C_window_0_0), + .b(Inter_C_window_1_0), + .c(Inter_C_window_0_1), + .d(Inter_C_window_1_1), + .out(CPE0_out) + ); + CPE CPE1 ( + .xFracC(xFracC), + .yFracC(yFracC), + .xFracC_n(xFracC_n), + .yFracC_n(yFracC_n), + .a(Inter_C_window_1_0), + .b(Inter_C_window_2_0), + .c(Inter_C_window_1_1), + .d(Inter_C_window_2_1), + .out(CPE1_out) + ); + CPE CPE2 ( + .xFracC(xFracC), + .yFracC(yFracC), + .xFracC_n(xFracC_n), + .yFracC_n(yFracC_n), + .a(Inter_C_window_0_1), + .b(Inter_C_window_1_1), + .c(Inter_C_window_0_2), + .d(Inter_C_window_1_2), + .out(CPE2_out) + ); + CPE CPE3 ( + .xFracC(xFracC), + .yFracC(yFracC), + .xFracC_n(xFracC_n), + .yFracC_n(yFracC_n), + .a(Inter_C_window_1_1), + .b(Inter_C_window_2_1), + .c(Inter_C_window_1_2), + .d(Inter_C_window_2_2), + .out(CPE3_out) + ); +endmodule + +module CPE (xFracC,yFracC,xFracC_n,yFracC_n,a,b,c,d,out); + input [2:0] xFracC,yFracC; + input [3:0] xFracC_n,yFracC_n; + input [7:0] a,b,c,d; + output [7:0] out; + + wire [13:0] CPE_base0_out,CPE_base1_out,CPE_base2_out,CPE_base3_out; + wire [13:0] out_tmp; + + CPE_base CPE_base0 ( + .x(xFracC_n), + .y(yFracC_n), + .Int_pel(a), + .out(CPE_base0_out) + ); + CPE_base CPE_base1 ( + .x({1'b0,xFracC}), + .y(yFracC_n), + .Int_pel(b), + .out(CPE_base1_out) + ); + CPE_base CPE_base2 ( + .x(xFracC_n), + .y({1'b0,yFracC}), + .Int_pel(c), + .out(CPE_base2_out) + ); + CPE_base CPE_base3 ( + .x({1'b0,xFracC}), + .y({1'b0,yFracC}), + .Int_pel(d), + .out(CPE_base3_out) + ); + assign out_tmp = (CPE_base0_out + CPE_base1_out) + (CPE_base2_out + CPE_base3_out) + 32; + assign out = out_tmp[13:6]; +endmodule + +module CPE_base (x,y,Int_pel,out); + input [3:0] x; + input [3:0] y; + input [7:0] Int_pel; + output [13:0] out; + + wire [10:0] sum_x3; + wire [9:0] sum_x2; + wire [8:0] sum_x1; + wire [7:0] sum_x0; + wire [10:0] sum_x; + + wire [13:0] sum_y3; + wire [12:0] sum_y2; + wire [11:0] sum_y1; + wire [10:0] sum_y0; + + assign sum_x3 = (x[3] == 1'b1)? {Int_pel,3'b0}:0; + assign sum_x2 = (x[2] == 1'b1)? {Int_pel,2'b0}:0; + assign sum_x1 = (x[1] == 1'b1)? {Int_pel,1'b0}:0; + assign sum_x0 = (x[0] == 1'b1)? Int_pel:0; + assign sum_x = (sum_x3 + sum_x2) + (sum_x1 + sum_x0); + + assign sum_y3 = (y[3] == 1'b1)? {sum_x,3'b0}:0; + assign sum_y2 = (y[2] == 1'b1)? {sum_x,2'b0}:0; + assign sum_y1 = (y[1] == 1'b1)? {sum_x,1'b0}:0; + assign sum_y0 = (y[0] == 1'b1)? sum_x:0; + assign out = (sum_y3 + sum_y2) + (sum_y1 + sum_y0); +endmodule + + + + + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/Inter_pred_LPE.v b/demo_chip_rtl/rtl/nova/trunk/src/Inter_pred_LPE.v new file mode 100644 index 0000000..a5eb4e7 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/Inter_pred_LPE.v @@ -0,0 +1,591 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : Inter_pred_LPE.v +// Generated : Oct 11, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Processing Element for Inter prediction of Luma pixels +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module Inter_pred_LPE (clk,reset_n,pos_FracL,IsInterLuma, + blk4x4_inter_calculate_counter, + Inter_H_window_0_0,Inter_H_window_1_0,Inter_H_window_2_0,Inter_H_window_3_0,Inter_H_window_4_0,Inter_H_window_5_0, + Inter_H_window_0_1,Inter_H_window_1_1,Inter_H_window_2_1,Inter_H_window_3_1,Inter_H_window_4_1,Inter_H_window_5_1, + Inter_H_window_0_2,Inter_H_window_1_2,Inter_H_window_2_2,Inter_H_window_3_2,Inter_H_window_4_2,Inter_H_window_5_2, + Inter_H_window_0_3,Inter_H_window_1_3,Inter_H_window_2_3,Inter_H_window_3_3,Inter_H_window_4_3,Inter_H_window_5_3, + Inter_H_window_0_4,Inter_H_window_1_4,Inter_H_window_2_4,Inter_H_window_3_4,Inter_H_window_4_4,Inter_H_window_5_4, + Inter_H_window_0_5,Inter_H_window_1_5,Inter_H_window_2_5,Inter_H_window_3_5,Inter_H_window_4_5,Inter_H_window_5_5, + Inter_H_window_0_6,Inter_H_window_1_6,Inter_H_window_2_6,Inter_H_window_3_6,Inter_H_window_4_6,Inter_H_window_5_6, + Inter_H_window_0_7,Inter_H_window_1_7,Inter_H_window_2_7,Inter_H_window_3_7,Inter_H_window_4_7,Inter_H_window_5_7, + Inter_H_window_0_8,Inter_H_window_1_8,Inter_H_window_2_8,Inter_H_window_3_8,Inter_H_window_4_8,Inter_H_window_5_8, + Inter_V_window_0,Inter_V_window_1,Inter_V_window_2,Inter_V_window_3,Inter_V_window_4, + Inter_V_window_5,Inter_V_window_6,Inter_V_window_7,Inter_V_window_8, + Inter_bi_window_0,Inter_bi_window_1,Inter_bi_window_2,Inter_bi_window_3, + + LPE0_out,LPE1_out,LPE2_out,LPE3_out + ); + input clk,reset_n; + input [3:0] pos_FracL; + input IsInterLuma; + input [3:0] blk4x4_inter_calculate_counter; + + input [7:0] Inter_H_window_0_0,Inter_H_window_1_0,Inter_H_window_2_0,Inter_H_window_3_0,Inter_H_window_4_0,Inter_H_window_5_0; + input [7:0] Inter_H_window_0_1,Inter_H_window_1_1,Inter_H_window_2_1,Inter_H_window_3_1,Inter_H_window_4_1,Inter_H_window_5_1; + input [7:0] Inter_H_window_0_2,Inter_H_window_1_2,Inter_H_window_2_2,Inter_H_window_3_2,Inter_H_window_4_2,Inter_H_window_5_2; + input [7:0] Inter_H_window_0_3,Inter_H_window_1_3,Inter_H_window_2_3,Inter_H_window_3_3,Inter_H_window_4_3,Inter_H_window_5_3; + input [7:0] Inter_H_window_0_4,Inter_H_window_1_4,Inter_H_window_2_4,Inter_H_window_3_4,Inter_H_window_4_4,Inter_H_window_5_4; + input [7:0] Inter_H_window_0_5,Inter_H_window_1_5,Inter_H_window_2_5,Inter_H_window_3_5,Inter_H_window_4_5,Inter_H_window_5_5; + input [7:0] Inter_H_window_0_6,Inter_H_window_1_6,Inter_H_window_2_6,Inter_H_window_3_6,Inter_H_window_4_6,Inter_H_window_5_6; + input [7:0] Inter_H_window_0_7,Inter_H_window_1_7,Inter_H_window_2_7,Inter_H_window_3_7,Inter_H_window_4_7,Inter_H_window_5_7; + input [7:0] Inter_H_window_0_8,Inter_H_window_1_8,Inter_H_window_2_8,Inter_H_window_3_8,Inter_H_window_4_8,Inter_H_window_5_8; + input [7:0] Inter_V_window_0,Inter_V_window_1,Inter_V_window_2,Inter_V_window_3,Inter_V_window_4; + input [7:0] Inter_V_window_5,Inter_V_window_6,Inter_V_window_7,Inter_V_window_8; + input [7:0] Inter_bi_window_0,Inter_bi_window_1,Inter_bi_window_2,Inter_bi_window_3; + + output [7:0] LPE0_out,LPE1_out,LPE2_out,LPE3_out; + + reg [7:0] LPE0_out,LPE1_out,LPE2_out,LPE3_out; + + reg [14:0] b0_raw_reg,b1_raw_reg,b2_raw_reg,b3_raw_reg,b4_raw_reg,b5_raw_reg,b6_raw_reg,b7_raw_reg,b8_raw_reg; + reg [7:0] b0_reg,b1_reg,b2_reg,b3_reg; + reg [7:0] h0_reg,h1_reg,h2_reg,h3_reg; + //------------------------ + //Vertical 6tap filter + //------------------------ + wire Is_V_jfqik; //Is_V_jfqik: whether read from original [7:0] integer pixels and round as +16 >> 5 or read from b_raw[14:0] and round as +512 >> 10 + wire [14:0] V_6tapfilter0_A,V_6tapfilter0_B,V_6tapfilter0_C,V_6tapfilter0_D,V_6tapfilter0_E,V_6tapfilter0_F; + wire [14:0] V_6tapfilter1_A,V_6tapfilter1_B,V_6tapfilter1_C,V_6tapfilter1_D,V_6tapfilter1_E,V_6tapfilter1_F; + wire [14:0] V_6tapfilter2_A,V_6tapfilter2_B,V_6tapfilter2_C,V_6tapfilter2_D,V_6tapfilter2_E,V_6tapfilter2_F; + wire [14:0] V_6tapfilter3_A,V_6tapfilter3_B,V_6tapfilter3_C,V_6tapfilter3_D,V_6tapfilter3_E,V_6tapfilter3_F; + wire [7:0] V_6tapfilter0_round_out,V_6tapfilter1_round_out,V_6tapfilter2_round_out,V_6tapfilter3_round_out; + filterV_6tap V_6tapfilter0 ( + .A(V_6tapfilter0_A), + .B(V_6tapfilter0_B), + .C(V_6tapfilter0_C), + .D(V_6tapfilter0_D), + .E(V_6tapfilter0_E), + .F(V_6tapfilter0_F), + .Is_jfqik(Is_V_jfqik), + .round_out(V_6tapfilter0_round_out) + ); + filterV_6tap V_6tapfilter1 ( + .A(V_6tapfilter1_A), + .B(V_6tapfilter1_B), + .C(V_6tapfilter1_C), + .D(V_6tapfilter1_D), + .E(V_6tapfilter1_E), + .F(V_6tapfilter1_F), + .Is_jfqik(Is_V_jfqik), + .round_out(V_6tapfilter1_round_out) + ); + filterV_6tap V_6tapfilter2 ( + .A(V_6tapfilter2_A), + .B(V_6tapfilter2_B), + .C(V_6tapfilter2_C), + .D(V_6tapfilter2_D), + .E(V_6tapfilter2_E), + .F(V_6tapfilter2_F), + .Is_jfqik(Is_V_jfqik), + .round_out(V_6tapfilter2_round_out) + ); + filterV_6tap V_6tapfilter3 ( + .A(V_6tapfilter3_A), + .B(V_6tapfilter3_B), + .C(V_6tapfilter3_C), + .D(V_6tapfilter3_D), + .E(V_6tapfilter3_E), + .F(V_6tapfilter3_F), + .Is_jfqik(Is_V_jfqik), + .round_out(V_6tapfilter3_round_out) + ); + assign Is_V_jfqik = ( + (pos_FracL == `pos_j && ( + blk4x4_inter_calculate_counter == 4'd4 || blk4x4_inter_calculate_counter == 4'd3 || + blk4x4_inter_calculate_counter == 4'd2 || blk4x4_inter_calculate_counter == 4'd1)) || + ((pos_FracL == `pos_f || pos_FracL == `pos_q) && ( + blk4x4_inter_calculate_counter == 4'd4 || blk4x4_inter_calculate_counter == 4'd3 || + blk4x4_inter_calculate_counter == 4'd2 || blk4x4_inter_calculate_counter == 4'd1)) || + ((pos_FracL == `pos_i || pos_FracL == `pos_k) && ( + blk4x4_inter_calculate_counter == 4'd7 || blk4x4_inter_calculate_counter == 4'd5 || + blk4x4_inter_calculate_counter == 4'd3 || blk4x4_inter_calculate_counter == 4'd1)))? 1'b1:1'b0; + + assign V_6tapfilter0_A = (Is_V_jfqik)? b0_raw_reg:{7'b0,Inter_V_window_0}; + assign V_6tapfilter0_B = (Is_V_jfqik)? b1_raw_reg:{7'b0,Inter_V_window_1}; + assign V_6tapfilter0_C = (Is_V_jfqik)? b2_raw_reg:{7'b0,Inter_V_window_2}; + assign V_6tapfilter0_D = (Is_V_jfqik)? b3_raw_reg:{7'b0,Inter_V_window_3}; + assign V_6tapfilter0_E = (Is_V_jfqik)? b4_raw_reg:{7'b0,Inter_V_window_4}; + assign V_6tapfilter0_F = (Is_V_jfqik)? b5_raw_reg:{7'b0,Inter_V_window_5}; + + assign V_6tapfilter1_A = (Is_V_jfqik)? b1_raw_reg:{7'b0,Inter_V_window_1}; + assign V_6tapfilter1_B = (Is_V_jfqik)? b2_raw_reg:{7'b0,Inter_V_window_2}; + assign V_6tapfilter1_C = (Is_V_jfqik)? b3_raw_reg:{7'b0,Inter_V_window_3}; + assign V_6tapfilter1_D = (Is_V_jfqik)? b4_raw_reg:{7'b0,Inter_V_window_4}; + assign V_6tapfilter1_E = (Is_V_jfqik)? b5_raw_reg:{7'b0,Inter_V_window_5}; + assign V_6tapfilter1_F = (Is_V_jfqik)? b6_raw_reg:{7'b0,Inter_V_window_6}; + + assign V_6tapfilter2_A = (Is_V_jfqik)? b2_raw_reg:{7'b0,Inter_V_window_2}; + assign V_6tapfilter2_B = (Is_V_jfqik)? b3_raw_reg:{7'b0,Inter_V_window_3}; + assign V_6tapfilter2_C = (Is_V_jfqik)? b4_raw_reg:{7'b0,Inter_V_window_4}; + assign V_6tapfilter2_D = (Is_V_jfqik)? b5_raw_reg:{7'b0,Inter_V_window_5}; + assign V_6tapfilter2_E = (Is_V_jfqik)? b6_raw_reg:{7'b0,Inter_V_window_6}; + assign V_6tapfilter2_F = (Is_V_jfqik)? b7_raw_reg:{7'b0,Inter_V_window_7}; + + assign V_6tapfilter3_A = (Is_V_jfqik)? b3_raw_reg:{7'b0,Inter_V_window_3}; + assign V_6tapfilter3_B = (Is_V_jfqik)? b4_raw_reg:{7'b0,Inter_V_window_4}; + assign V_6tapfilter3_C = (Is_V_jfqik)? b5_raw_reg:{7'b0,Inter_V_window_5}; + assign V_6tapfilter3_D = (Is_V_jfqik)? b6_raw_reg:{7'b0,Inter_V_window_6}; + assign V_6tapfilter3_E = (Is_V_jfqik)? b7_raw_reg:{7'b0,Inter_V_window_7}; + assign V_6tapfilter3_F = (Is_V_jfqik)? b8_raw_reg:{7'b0,Inter_V_window_8}; + + //------------------------ + //Horizontal 6tap filter + //------------------------ + wire H_need_round; + wire [14:0] H_6tapfilter0_raw_out; + wire [14:0] H_6tapfilter1_raw_out; + wire [14:0] H_6tapfilter2_raw_out; + wire [14:0] H_6tapfilter3_raw_out; + wire [14:0] H_6tapfilter4_raw_out; + wire [14:0] H_6tapfilter5_raw_out; + wire [14:0] H_6tapfilter6_raw_out; + wire [14:0] H_6tapfilter7_raw_out; + wire [14:0] H_6tapfilter8_raw_out; + wire [7:0] H_6tapfilter0_round_out; + wire [7:0] H_6tapfilter1_round_out; + wire [7:0] H_6tapfilter2_round_out; + wire [7:0] H_6tapfilter3_round_out; + wire [7:0] H_6tapfilter4_round_out; + wire [7:0] H_6tapfilter5_round_out; + wire [7:0] H_6tapfilter6_round_out; + wire [7:0] H_6tapfilter7_round_out; + wire [7:0] H_6tapfilter8_round_out; + + assign H_need_round = (blk4x4_inter_calculate_counter != 0 && pos_FracL != `pos_Int && pos_FracL != `pos_i + && pos_FracL != `pos_j && pos_FracL != `pos_k && pos_FracL != `pos_d && pos_FracL != `pos_n); + + filterH_6tap H_6tapfilter0 ( + .A(Inter_H_window_0_0), + .B(Inter_H_window_1_0), + .C(Inter_H_window_2_0), + .D(Inter_H_window_3_0), + .E(Inter_H_window_4_0), + .F(Inter_H_window_5_0), + .H_need_round(1'b0), + .raw_out(H_6tapfilter0_raw_out), + .round_out(H_6tapfilter0_round_out) + ); + filterH_6tap H_6tapfilter1 ( + .A(Inter_H_window_0_1), + .B(Inter_H_window_1_1), + .C(Inter_H_window_2_1), + .D(Inter_H_window_3_1), + .E(Inter_H_window_4_1), + .F(Inter_H_window_5_1), + .H_need_round(1'b0), + .raw_out(H_6tapfilter1_raw_out), + .round_out(H_6tapfilter1_round_out) + ); + filterH_6tap H_6tapfilter2 ( + .A(Inter_H_window_0_2), + .B(Inter_H_window_1_2), + .C(Inter_H_window_2_2), + .D(Inter_H_window_3_2), + .E(Inter_H_window_4_2), + .F(Inter_H_window_5_2), + .H_need_round(H_need_round), + .raw_out(H_6tapfilter2_raw_out), + .round_out(H_6tapfilter2_round_out) + ); + filterH_6tap H_6tapfilter3 ( + .A(Inter_H_window_0_3), + .B(Inter_H_window_1_3), + .C(Inter_H_window_2_3), + .D(Inter_H_window_3_3), + .E(Inter_H_window_4_3), + .F(Inter_H_window_5_3), + .H_need_round(H_need_round), + .raw_out(H_6tapfilter3_raw_out), + .round_out(H_6tapfilter3_round_out) + ); + filterH_6tap H_6tapfilter4 ( + .A(Inter_H_window_0_4), + .B(Inter_H_window_1_4), + .C(Inter_H_window_2_4), + .D(Inter_H_window_3_4), + .E(Inter_H_window_4_4), + .F(Inter_H_window_5_4), + .H_need_round(H_need_round), + .raw_out(H_6tapfilter4_raw_out), + .round_out(H_6tapfilter4_round_out) + ); + filterH_6tap H_6tapfilter5 ( + .A(Inter_H_window_0_5), + .B(Inter_H_window_1_5), + .C(Inter_H_window_2_5), + .D(Inter_H_window_3_5), + .E(Inter_H_window_4_5), + .F(Inter_H_window_5_5), + .H_need_round(H_need_round), + .raw_out(H_6tapfilter5_raw_out), + .round_out(H_6tapfilter5_round_out) + ); + filterH_6tap H_6tapfilter6 ( + .A(Inter_H_window_0_6), + .B(Inter_H_window_1_6), + .C(Inter_H_window_2_6), + .D(Inter_H_window_3_6), + .E(Inter_H_window_4_6), + .F(Inter_H_window_5_6), + .H_need_round(H_need_round), + .raw_out(H_6tapfilter6_raw_out), + .round_out(H_6tapfilter6_round_out) + ); + filterH_6tap H_6tapfilter7 ( + .A(Inter_H_window_0_7), + .B(Inter_H_window_1_7), + .C(Inter_H_window_2_7), + .D(Inter_H_window_3_7), + .E(Inter_H_window_4_7), + .F(Inter_H_window_5_7), + .H_need_round(1'b0), + .raw_out(H_6tapfilter7_raw_out), + .round_out(H_6tapfilter7_round_out) + ); + filterH_6tap H_6tapfilter8 ( + .A(Inter_H_window_0_8), + .B(Inter_H_window_1_8), + .C(Inter_H_window_2_8), + .D(Inter_H_window_3_8), + .E(Inter_H_window_4_8), + .F(Inter_H_window_5_8), + .H_need_round(1'b0), + .raw_out(H_6tapfilter8_raw_out), + .round_out(H_6tapfilter8_round_out) + ); + + //-------------------- + //bilinear filter + //-------------------- + reg [7:0] bilinear0_A,bilinear0_B; + reg [7:0] bilinear1_A,bilinear1_B; + reg [7:0] bilinear2_A,bilinear2_B; + reg [7:0] bilinear3_A,bilinear3_B; + wire [7:0] bilinear0_out; + wire [7:0] bilinear1_out; + wire [7:0] bilinear2_out; + wire [7:0] bilinear3_out; + bilinear bilinear0 ( + .A(bilinear0_A), + .B(bilinear0_B), + .bilinear_out(bilinear0_out) + ); + bilinear bilinear1 ( + .A(bilinear1_A), + .B(bilinear1_B), + .bilinear_out(bilinear1_out) + ); + bilinear bilinear2 ( + .A(bilinear2_A), + .B(bilinear2_B), + .bilinear_out(bilinear2_out) + ); + bilinear bilinear3 ( + .A(bilinear3_A), + .B(bilinear3_B), + .bilinear_out(bilinear3_out) + ); + always @ (IsInterLuma or pos_FracL or blk4x4_inter_calculate_counter + or Inter_bi_window_0 or Inter_bi_window_1 or Inter_bi_window_2 or Inter_bi_window_3 + or H_6tapfilter2_round_out or H_6tapfilter3_round_out or H_6tapfilter4_round_out or H_6tapfilter5_round_out + or V_6tapfilter0_round_out or V_6tapfilter1_round_out or V_6tapfilter2_round_out or V_6tapfilter3_round_out + or b0_reg or b1_reg or b2_reg or b3_reg or h0_reg or h1_reg or h2_reg or h3_reg) + if (IsInterLuma) + case ({pos_FracL}) + `pos_a,`pos_c: + if (blk4x4_inter_calculate_counter != 4'd0) + begin + bilinear0_A <= Inter_bi_window_0; bilinear0_B <= H_6tapfilter2_round_out; + bilinear1_A <= Inter_bi_window_1; bilinear1_B <= H_6tapfilter3_round_out; + bilinear2_A <= Inter_bi_window_2; bilinear2_B <= H_6tapfilter4_round_out; + bilinear3_A <= Inter_bi_window_3; bilinear3_B <= H_6tapfilter5_round_out; + end + else + begin + bilinear0_A <= 0; bilinear0_B <= 0; bilinear1_A <= 0; bilinear1_B <= 0; + bilinear2_A <= 0; bilinear2_B <= 0; bilinear3_A <= 0; bilinear3_B <= 0; + end + `pos_d,`pos_n: + if (blk4x4_inter_calculate_counter != 4'd0) + begin + bilinear0_A <= Inter_bi_window_0; bilinear0_B <= V_6tapfilter0_round_out; + bilinear1_A <= Inter_bi_window_1; bilinear1_B <= V_6tapfilter1_round_out; + bilinear2_A <= Inter_bi_window_2; bilinear2_B <= V_6tapfilter2_round_out; + bilinear3_A <= Inter_bi_window_3; bilinear3_B <= V_6tapfilter3_round_out; + end + else + begin + bilinear0_A <= 0; bilinear0_B <= 0; bilinear1_A <= 0; bilinear1_B <= 0; + bilinear2_A <= 0; bilinear2_B <= 0; bilinear3_A <= 0; bilinear3_B <= 0; + end + `pos_e,`pos_g,`pos_p,`pos_r: + if (blk4x4_inter_calculate_counter != 4'd0) + begin + bilinear0_A <= H_6tapfilter2_round_out; bilinear0_B <= V_6tapfilter0_round_out; + bilinear1_A <= H_6tapfilter3_round_out; bilinear1_B <= V_6tapfilter1_round_out; + bilinear2_A <= H_6tapfilter4_round_out; bilinear2_B <= V_6tapfilter2_round_out; + bilinear3_A <= H_6tapfilter5_round_out; bilinear3_B <= V_6tapfilter3_round_out; + end + else + begin + bilinear0_A <= 0; bilinear0_B <= 0; bilinear1_A <= 0; bilinear1_B <= 0; + bilinear2_A <= 0; bilinear2_B <= 0; bilinear3_A <= 0; bilinear3_B <= 0; + end + `pos_i,`pos_k: + if (blk4x4_inter_calculate_counter == 4'd7 || blk4x4_inter_calculate_counter == 4'd5 || + blk4x4_inter_calculate_counter == 4'd3 || blk4x4_inter_calculate_counter == 4'd1) + begin + bilinear0_A <= h0_reg; bilinear0_B <= V_6tapfilter0_round_out; + bilinear1_A <= h1_reg; bilinear1_B <= V_6tapfilter1_round_out; + bilinear2_A <= h2_reg; bilinear2_B <= V_6tapfilter2_round_out; + bilinear3_A <= h3_reg; bilinear3_B <= V_6tapfilter3_round_out; + end + else + begin + bilinear0_A <= 0; bilinear0_B <= 0; bilinear1_A <= 0; bilinear1_B <= 0; + bilinear2_A <= 0; bilinear2_B <= 0; bilinear3_A <= 0; bilinear3_B <= 0; + end + `pos_f,`pos_q: + if (blk4x4_inter_calculate_counter != 4'd5 && blk4x4_inter_calculate_counter != 4'd0) + begin + bilinear0_A <= b0_reg; bilinear0_B <= V_6tapfilter0_round_out; + bilinear1_A <= b1_reg; bilinear1_B <= V_6tapfilter1_round_out; + bilinear2_A <= b2_reg; bilinear2_B <= V_6tapfilter2_round_out; + bilinear3_A <= b3_reg; bilinear3_B <= V_6tapfilter3_round_out; + end + else + begin + bilinear0_A <= 0; bilinear0_B <= 0; bilinear1_A <= 0; bilinear1_B <= 0; + bilinear2_A <= 0; bilinear2_B <= 0; bilinear3_A <= 0; bilinear3_B <= 0; + end + default: + begin + bilinear0_A <= 0; bilinear0_B <= 0; bilinear1_A <= 0; bilinear1_B <= 0; + bilinear2_A <= 0; bilinear2_B <= 0; bilinear3_A <= 0; bilinear3_B <= 0; + end + endcase + else + begin + bilinear0_A <= 0; bilinear0_B <= 0; bilinear1_A <= 0; bilinear1_B <= 0; + bilinear2_A <= 0; bilinear2_B <= 0; bilinear3_A <= 0; bilinear3_B <= 0; + end + + //------------------------------------------------------------------------------------------ + //only "b","h" and "j" of half-pel positions need to be stored to predict quater-pel samples + //------------------------------------------------------------------------------------------ + + //b0_raw_reg0 ~ b8_raw_reg:update after j/f/q/i/k horizontal filtering + wire b_raw_reg_ena; + assign b_raw_reg_ena = (IsInterLuma && + ((pos_FracL == `pos_j && blk4x4_inter_calculate_counter != 4'd1 && blk4x4_inter_calculate_counter != 4'd0) || + ((pos_FracL == `pos_f || pos_FracL == `pos_q) && (blk4x4_inter_calculate_counter == 4'd5 || + blk4x4_inter_calculate_counter == 4'd4 || + blk4x4_inter_calculate_counter == 4'd3 || + blk4x4_inter_calculate_counter == 4'd2)) || + ((pos_FracL == `pos_i || pos_FracL == `pos_k) && (blk4x4_inter_calculate_counter == 4'd8 || + blk4x4_inter_calculate_counter == 4'd6 || + blk4x4_inter_calculate_counter == 4'd4 || + blk4x4_inter_calculate_counter == 4'd2)))); + + always @ (posedge clk) + if (reset_n == 1'b0) + begin + b0_raw_reg <= 0; b1_raw_reg <= 0; b2_raw_reg <= 0; b3_raw_reg <= 0; b4_raw_reg <= 0; + b5_raw_reg <= 0; b6_raw_reg <= 0; b7_raw_reg <= 0; b8_raw_reg <= 0; + end + else if (b_raw_reg_ena) + begin + b0_raw_reg <= H_6tapfilter0_raw_out;b1_raw_reg <= H_6tapfilter1_raw_out;b2_raw_reg <= H_6tapfilter2_raw_out; + b3_raw_reg <= H_6tapfilter3_raw_out;b4_raw_reg <= H_6tapfilter4_raw_out;b5_raw_reg <= H_6tapfilter5_raw_out; + b6_raw_reg <= H_6tapfilter6_raw_out;b7_raw_reg <= H_6tapfilter7_raw_out;b8_raw_reg <= H_6tapfilter8_raw_out; + end + + //b0_reg ~ b3_reg:update for decoding f,q + //Note:position q needs "b" of next line + wire b_reg_ena; + assign b_reg_ena = (IsInterLuma && ((pos_FracL == `pos_f || pos_FracL == `pos_q) && (blk4x4_inter_calculate_counter == 4'd5 || + blk4x4_inter_calculate_counter == 4'd4 || blk4x4_inter_calculate_counter == 4'd3 || blk4x4_inter_calculate_counter == 4'd2))); + + always @ (posedge clk) + if (reset_n == 1'b0) + begin + b0_reg <= 0; b1_reg <= 0; b2_reg <= 0; b3_reg <= 0; + end + else if (b_reg_ena) + begin + if (pos_FracL == `pos_q) + begin + b0_reg <= H_6tapfilter3_round_out; b1_reg <= H_6tapfilter4_round_out; + b2_reg <= H_6tapfilter5_round_out; b3_reg <= H_6tapfilter6_round_out; + end + else + begin + b0_reg <= H_6tapfilter2_round_out; b1_reg <= H_6tapfilter3_round_out; + b2_reg <= H_6tapfilter4_round_out; b3_reg <= H_6tapfilter5_round_out; + end + end + + //h0_reg ~ h3_reg:update for decoding i,k + wire h_reg_ena; + assign h_reg_ena = (IsInterLuma && ((pos_FracL == `pos_i || pos_FracL == `pos_k) && (blk4x4_inter_calculate_counter == 4'd8 || + blk4x4_inter_calculate_counter == 4'd6 || blk4x4_inter_calculate_counter == 4'd4 || blk4x4_inter_calculate_counter == 4'd2))); + + always @ (posedge clk) + if (reset_n == 1'b0) + begin + h0_reg <= 0; h1_reg <= 0; h2_reg <= 0; h3_reg <= 0; + end + else if (h_reg_ena) + begin + h0_reg <= V_6tapfilter0_round_out; h1_reg <= V_6tapfilter1_round_out; + h2_reg <= V_6tapfilter2_round_out; h3_reg <= V_6tapfilter3_round_out; + end + //------------------------------------------------------------------------------------------ + //LPE output + //------------------------------------------------------------------------------------------ + always @ (IsInterLuma or pos_FracL or blk4x4_inter_calculate_counter + or V_6tapfilter0_round_out or V_6tapfilter1_round_out or V_6tapfilter2_round_out or V_6tapfilter3_round_out + or H_6tapfilter2_round_out or H_6tapfilter3_round_out or H_6tapfilter4_round_out or H_6tapfilter5_round_out + or bilinear0_out or bilinear1_out or bilinear2_out or bilinear3_out) + if (IsInterLuma) + case (pos_FracL) + //pos_Int: directly bypassed by Inter_pix_copy0 ~ Inter_pix_copy3 + `pos_b: + if (blk4x4_inter_calculate_counter != 0) + begin + LPE0_out <= H_6tapfilter2_round_out; LPE1_out <= H_6tapfilter3_round_out; + LPE2_out <= H_6tapfilter4_round_out; LPE3_out <= H_6tapfilter5_round_out; + end + else + begin LPE0_out <= 0; LPE1_out <= 0;LPE2_out <= 0; LPE3_out <= 0;end + `pos_h: + if (blk4x4_inter_calculate_counter != 0) + begin + LPE0_out <= V_6tapfilter0_round_out; LPE1_out <= V_6tapfilter1_round_out; + LPE2_out <= V_6tapfilter2_round_out; LPE3_out <= V_6tapfilter3_round_out; + end + else + begin LPE0_out <= 0; LPE1_out <= 0;LPE2_out <= 0; LPE3_out <= 0;end + `pos_j: + if (blk4x4_inter_calculate_counter != 4'd5 && blk4x4_inter_calculate_counter != 0) + begin + LPE0_out <= V_6tapfilter0_round_out; LPE1_out <= V_6tapfilter1_round_out; + LPE2_out <= V_6tapfilter2_round_out; LPE3_out <= V_6tapfilter3_round_out; + end + else + begin LPE0_out <= 0; LPE1_out <= 0;LPE2_out <= 0; LPE3_out <= 0;end + `pos_a,`pos_c,`pos_d,`pos_e,`pos_g,`pos_n,`pos_p,`pos_r,`pos_f,`pos_q: + if (blk4x4_inter_calculate_counter == 4'd4 || blk4x4_inter_calculate_counter == 4'd3 || + blk4x4_inter_calculate_counter == 4'd2 || blk4x4_inter_calculate_counter == 4'd1) + begin + LPE0_out <= bilinear0_out; LPE1_out <= bilinear1_out; + LPE2_out <= bilinear2_out; LPE3_out <= bilinear3_out; + end + else + begin LPE0_out <= 0; LPE1_out <= 0;LPE2_out <= 0; LPE3_out <= 0;end + `pos_i,`pos_k: + if (blk4x4_inter_calculate_counter == 4'd7 || blk4x4_inter_calculate_counter == 4'd5 || + blk4x4_inter_calculate_counter == 4'd3 || blk4x4_inter_calculate_counter == 4'd1) + begin + LPE0_out <= bilinear0_out; LPE1_out <= bilinear1_out; + LPE2_out <= bilinear2_out; LPE3_out <= bilinear3_out; + end + else + begin LPE0_out <= 0; LPE1_out <= 0;LPE2_out <= 0; LPE3_out <= 0;end + default: + begin LPE0_out <= 0; LPE1_out <= 0;LPE2_out <= 0; LPE3_out <= 0;end + endcase + else + begin LPE0_out <= 0; LPE1_out <= 0;LPE2_out <= 0; LPE3_out <= 0;end + +endmodule + +module filterH_6tap(A,B,C,D,E,F,H_need_round,raw_out,round_out); + input [7:0] A,B,C,D,E,F; + input H_need_round; + output [14:0] raw_out; //always output + output [7:0] round_out; + + wire [8:0] sum_AF; + wire [8:0] sum_BE; + wire [8:0] sum_CD; + wire [10:0] sum_4CD; + wire [11:0] sum_1; + wire [12:0] sum_2; + wire [13:0] sum_3; + wire [14:0] sum_round; + wire [9:0] round_tmp; + + assign sum_AF = A + F; + assign sum_BE = B + E; + assign sum_CD = C + D; + assign sum_4CD = {sum_CD,2'b0}; + assign sum_1 = {1'b0,sum_4CD} + {3'b111,~sum_BE} + 1; + assign sum_2 = {4'b0,sum_AF} + {sum_1[11],sum_1}; + assign sum_3 = {sum_1,2'b0}; + assign raw_out = {{2{sum_2[12]}},sum_2} + {sum_3[13],sum_3}; + //round + assign sum_round = (H_need_round)? (raw_out + 16):0; + assign round_tmp = (H_need_round)? sum_round[14:5]:0; + assign round_out = (round_tmp[9])? 8'd0:((round_tmp[8])? 8'd255:round_tmp[7:0]); +endmodule + +module filterV_6tap(A,B,C,D,E,F,Is_jfqik,round_out); + input [14:0] A,B,C,D,E,F; + input Is_jfqik; + output [7:0] round_out; + + wire [15:0] sum_AF; + wire [15:0] sum_BE; + wire [15:0] sum_CD; + wire [17:0] sum_4CD; + wire [17:0] sum_1; + wire [17:0] sum_2; + wire [19:0] sum_3; + wire [19:0] raw_out; + + wire [19:0] sum_round; + wire [9:0] round_tmp; + + assign sum_AF = {A[14],A} + {F[14],F}; + assign sum_BE = {B[14],B} + {E[14],E}; + assign sum_CD = {C[14],C} + {D[14],D}; + assign sum_4CD = {sum_CD,2'b0}; + assign sum_1 = sum_4CD + {~sum_BE[15],~sum_BE[15],~sum_BE} + 1; + assign sum_2 = {{2{sum_AF[15]}},sum_AF} + sum_1; + assign sum_3 = {sum_1,2'b0}; + assign raw_out = {{2{sum_2[17]}},sum_2} + sum_3; + //round + assign sum_round = (Is_jfqik)? (raw_out + 512):(raw_out + 16); + assign round_tmp = (Is_jfqik)? sum_round[19:10]:sum_round[14:5]; + assign round_out = (round_tmp[9])? 8'd0:((round_tmp[8])? 8'd255:round_tmp[7:0]); +endmodule + +module bilinear (A,B,bilinear_out); + input [7:0] A,B; + output [7:0] bilinear_out; + wire [8:0] sum_AB; + + assign sum_AB = A + B + 1; //here A and B should NOT extend as {A[7],A} + assign bilinear_out = sum_AB[8:1]; +endmodule + + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/Inter_pred_pipeline.v b/demo_chip_rtl/rtl/nova/trunk/src/Inter_pred_pipeline.v new file mode 100644 index 0000000..ad3c411 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/Inter_pred_pipeline.v @@ -0,0 +1,782 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : Inter_pred_pipeline.v +// Generated : Oct 4, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Inter prediction pipeline +//------------------------------------------------------------------------------------------------- +// Revise log +// 1.July 23,2006 +// Change the ext_frame_RAM from async read to sync read.Therefore,blk4x4_inter_preload_counter has to +1 for all the cases +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module Inter_pred_pipeline (clk,reset_n, + mb_num_h,mb_num_v,trigger_blk4x4_inter_pred,blk4x4_rec_counter,mb_type_general_bit3, + mv_is16x16,mv_below8x8, + mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3, + mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3, + Inter_pix_copy0,Inter_pix_copy1,Inter_pix_copy2,Inter_pix_copy3, + LPE0_out,LPE1_out,LPE2_out,LPE3_out, + CPE0_out,CPE1_out,CPE2_out,CPE3_out, + + mv_below8x8_curr,blk4x4_inter_preload_counter,blk4x4_inter_calculate_counter,Inter_chroma2x2_counter, + end_of_one_blk4x4_inter,IsInterLuma,IsInterChroma,Is_InterChromaCopy, + xInt_addr_unclip,xInt_org_unclip_1to0,pos_FracL,xFracC,yFracC, + Inter_pred_out0,Inter_pred_out1,Inter_pred_out2,Inter_pred_out3,Inter_blk4x4_pred_output_valid, + ref_frame_RAM_rd,ref_frame_RAM_rd_addr); + input clk; + input reset_n; + input [3:0] mb_num_h,mb_num_v; + input trigger_blk4x4_inter_pred; + input [4:0] blk4x4_rec_counter; + input mb_type_general_bit3; + input mv_is16x16; + input [3:0] mv_below8x8; + input [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3; + input [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3; + input [7:0] Inter_pix_copy0,Inter_pix_copy1,Inter_pix_copy2,Inter_pix_copy3; + input [7:0] LPE0_out,LPE1_out,LPE2_out,LPE3_out; + input [7:0] CPE0_out,CPE1_out,CPE2_out,CPE3_out; + + output mv_below8x8_curr; + output [5:0] blk4x4_inter_preload_counter; + output [3:0] blk4x4_inter_calculate_counter; + output [1:0] Inter_chroma2x2_counter; + output end_of_one_blk4x4_inter; + output IsInterLuma,IsInterChroma; + output Is_InterChromaCopy; + output [8:0] xInt_addr_unclip; + output [1:0] xInt_org_unclip_1to0; + output [3:0] pos_FracL; + output [2:0] xFracC,yFracC; + output [7:0] Inter_pred_out0,Inter_pred_out1,Inter_pred_out2,Inter_pred_out3; + output [1:0] Inter_blk4x4_pred_output_valid; //2'b01:luma output valid 2'b10:chroma output valid + output ref_frame_RAM_rd; + output [13:0] ref_frame_RAM_rd_addr; + + reg [5:0] blk4x4_inter_preload_counter; + reg [3:0] blk4x4_inter_calculate_counter; + reg mv_below8x8_curr; + reg [7:0] Inter_pred_out0,Inter_pred_out1,Inter_pred_out2,Inter_pred_out3; + reg [1:0] Inter_blk4x4_pred_output_valid; + wire ref_frame_RAM_rd; + wire IsInterLuma; + wire IsInterChroma; + wire [1:0] xFracL; + wire [1:0] yFracL; + wire [2:0] xFracC; + wire [2:0] yFracC; + wire [13:0] ref_frame_RAM_rd_addr; + + assign IsInterLuma = (!mb_type_general_bit3 && blk4x4_rec_counter < 16)? 1'b1:1'b0; + assign IsInterChroma = (!mb_type_general_bit3 && blk4x4_rec_counter > 15)? 1'b1:1'b0; + //------------------------------------------------------------------------- + //mv_below8x8_curr for each 2x2 Inter Chroma prediction + //------------------------------------------------------------------------- + always @ (IsInterLuma or IsInterChroma or blk4x4_rec_counter[3:0] or mv_below8x8) + if (IsInterLuma) + case (blk4x4_rec_counter[3:2]) + 2'b00:mv_below8x8_curr <= mv_below8x8[0]; + 2'b01:mv_below8x8_curr <= mv_below8x8[1]; + 2'b10:mv_below8x8_curr <= mv_below8x8[2]; + 2'b11:mv_below8x8_curr <= mv_below8x8[3]; + endcase + else if (IsInterChroma) + case (blk4x4_rec_counter[1:0]) + 2'b00:mv_below8x8_curr <= mv_below8x8[0]; + 2'b01:mv_below8x8_curr <= mv_below8x8[1]; + 2'b10:mv_below8x8_curr <= mv_below8x8[2]; + 2'b11:mv_below8x8_curr <= mv_below8x8[3]; + endcase + else + mv_below8x8_curr <= 0; + //---------------------------------------------------------------------------------------- + //Inter_chroma2x2_counter to guide the prediction of 2x2 chroma blocks + //2'b11 -> 2'b10 -> 2'b01 -> 2'b00 + //---------------------------------------------------------------------------------------- + reg [1:0] Inter_chroma2x2_counter; + always @ (posedge clk) + if (reset_n == 1'b0) + Inter_chroma2x2_counter <= 0; + //mv_below8x8_curr == 1'b1 includes the condition that "blk4x4_rec_counter > 15" + else if (IsInterChroma && trigger_blk4x4_inter_pred && mv_below8x8_curr) + Inter_chroma2x2_counter <= 2'b11; + else if (blk4x4_inter_calculate_counter == 4'd1 && Inter_chroma2x2_counter != 0) + Inter_chroma2x2_counter <= Inter_chroma2x2_counter - 1; + + //---------------------------------------------------------------------------------------- + //trigger_blk2x2_inter_pred:only for chroma 2x2 decoding + //We introduce this additional signal since we need Inter_chroma2x2_counter to update + //one cycle before blk4x4_inter_calculate_counter + //---------------------------------------------------------------------------------------- + reg trigger_blk2x2_inter_pred; + always @ (posedge clk) + if (reset_n == 1'b0) + trigger_blk2x2_inter_pred <= 0; + else if ((IsInterChroma && trigger_blk4x4_inter_pred && mv_below8x8_curr) || + (blk4x4_inter_calculate_counter == 4'd1 && Inter_chroma2x2_counter != 0)) + trigger_blk2x2_inter_pred <= 1'b1; + else + trigger_blk2x2_inter_pred <= 1'b0; + //---------------------------------------------------------------------------------------- + //Inter motion vector for current 4x4 luma/chroma block or 2x2 chroma block + // Inter_blk_mvx,Inter_blk_mvy + //---------------------------------------------------------------------------------------- + reg [7:0] Inter_blk_mvx,Inter_blk_mvy; + always @ (blk4x4_rec_counter or mv_below8x8_curr or Inter_chroma2x2_counter + or IsInterLuma or IsInterChroma or mv_is16x16 + or mvx_CurrMb0 or mvx_CurrMb1 or mvx_CurrMb2 or mvx_CurrMb3 + or mvy_CurrMb0 or mvy_CurrMb1 or mvy_CurrMb2 or mvy_CurrMb3) + //Inter luma + if (IsInterLuma) + begin + if (mv_is16x16) + begin Inter_blk_mvx <= mvx_CurrMb0[7:0]; Inter_blk_mvy <= mvy_CurrMb0[7:0]; end + else + case (mv_below8x8_curr) + 1'b0: + case (blk4x4_rec_counter[3:2]) + 2'b00:begin Inter_blk_mvx <= mvx_CurrMb0[7:0]; Inter_blk_mvy <= mvy_CurrMb0[7:0]; end + 2'b01:begin Inter_blk_mvx <= mvx_CurrMb1[7:0]; Inter_blk_mvy <= mvy_CurrMb1[7:0]; end + 2'b10:begin Inter_blk_mvx <= mvx_CurrMb2[7:0]; Inter_blk_mvy <= mvy_CurrMb2[7:0]; end + 2'b11:begin Inter_blk_mvx <= mvx_CurrMb3[7:0]; Inter_blk_mvy <= mvy_CurrMb3[7:0]; end + endcase + 1'b1: + case (blk4x4_rec_counter) + 0 :begin Inter_blk_mvx <= mvx_CurrMb0[7:0]; Inter_blk_mvy <= mvy_CurrMb0[7:0]; end + 1 :begin Inter_blk_mvx <= mvx_CurrMb0[15:8]; Inter_blk_mvy <= mvy_CurrMb0[15:8]; end + 2 :begin Inter_blk_mvx <= mvx_CurrMb0[23:16];Inter_blk_mvy <= mvy_CurrMb0[23:16]; end + 3 :begin Inter_blk_mvx <= mvx_CurrMb0[31:24];Inter_blk_mvy <= mvy_CurrMb0[31:24]; end + 4 :begin Inter_blk_mvx <= mvx_CurrMb1[7:0]; Inter_blk_mvy <= mvy_CurrMb1[7:0]; end + 5 :begin Inter_blk_mvx <= mvx_CurrMb1[15:8]; Inter_blk_mvy <= mvy_CurrMb1[15:8]; end + 6 :begin Inter_blk_mvx <= mvx_CurrMb1[23:16];Inter_blk_mvy <= mvy_CurrMb1[23:16]; end + 7 :begin Inter_blk_mvx <= mvx_CurrMb1[31:24];Inter_blk_mvy <= mvy_CurrMb1[31:24]; end + 8 :begin Inter_blk_mvx <= mvx_CurrMb2[7:0]; Inter_blk_mvy <= mvy_CurrMb2[7:0]; end + 9 :begin Inter_blk_mvx <= mvx_CurrMb2[15:8]; Inter_blk_mvy <= mvy_CurrMb2[15:8]; end + 10:begin Inter_blk_mvx <= mvx_CurrMb2[23:16];Inter_blk_mvy <= mvy_CurrMb2[23:16]; end + 11:begin Inter_blk_mvx <= mvx_CurrMb2[31:24];Inter_blk_mvy <= mvy_CurrMb2[31:24]; end + 12:begin Inter_blk_mvx <= mvx_CurrMb3[7:0]; Inter_blk_mvy <= mvy_CurrMb3[7:0]; end + 13:begin Inter_blk_mvx <= mvx_CurrMb3[15:8]; Inter_blk_mvy <= mvy_CurrMb3[15:8]; end + 14:begin Inter_blk_mvx <= mvx_CurrMb3[23:16];Inter_blk_mvy <= mvy_CurrMb3[23:16]; end + 15:begin Inter_blk_mvx <= mvx_CurrMb3[31:24];Inter_blk_mvy <= mvy_CurrMb3[31:24]; end + default:begin Inter_blk_mvx <= 0;Inter_blk_mvy <= 0; end + endcase + endcase + end + //Inter chroma + else if (IsInterChroma) + begin + if (mv_is16x16) + begin Inter_blk_mvx <= mvx_CurrMb0[7:0]; Inter_blk_mvy <= mvy_CurrMb0[7:0]; end + else + case (blk4x4_rec_counter[1:0]) + 2'b00: + if (mv_below8x8_curr) //chroma2x2 prediction + case (Inter_chroma2x2_counter) + 3:begin Inter_blk_mvx <= mvx_CurrMb0[7:0]; Inter_blk_mvy <= mvy_CurrMb0[7:0]; end + 2:begin Inter_blk_mvx <= mvx_CurrMb0[15:8]; Inter_blk_mvy <= mvy_CurrMb0[15:8]; end + 1:begin Inter_blk_mvx <= mvx_CurrMb0[23:16];Inter_blk_mvy <= mvy_CurrMb0[23:16]; end + 0:begin Inter_blk_mvx <= mvx_CurrMb0[31:24];Inter_blk_mvy <= mvy_CurrMb0[31:24]; end + endcase + else //chroma 4x4 prediction + begin Inter_blk_mvx <= mvx_CurrMb0[7:0]; Inter_blk_mvy <= mvy_CurrMb0[7:0]; end + 2'b01: + if (mv_below8x8_curr) //need chroma2x2 prediction + case (Inter_chroma2x2_counter) + 3:begin Inter_blk_mvx <= mvx_CurrMb1[7:0]; Inter_blk_mvy <= mvy_CurrMb1[7:0]; end + 2:begin Inter_blk_mvx <= mvx_CurrMb1[15:8]; Inter_blk_mvy <= mvy_CurrMb1[15:8]; end + 1:begin Inter_blk_mvx <= mvx_CurrMb1[23:16];Inter_blk_mvy <= mvy_CurrMb1[23:16]; end + 0:begin Inter_blk_mvx <= mvx_CurrMb1[31:24];Inter_blk_mvy <= mvy_CurrMb1[31:24]; end + endcase + else //chroma 4x4 prediction + begin Inter_blk_mvx <= mvx_CurrMb1[7:0]; Inter_blk_mvy <= mvy_CurrMb1[7:0]; end + 2'b10: + if (mv_below8x8_curr) //chroma2x2 prediction + case (Inter_chroma2x2_counter) + 3:begin Inter_blk_mvx <= mvx_CurrMb2[7:0]; Inter_blk_mvy <= mvy_CurrMb2[7:0]; end + 2:begin Inter_blk_mvx <= mvx_CurrMb2[15:8]; Inter_blk_mvy <= mvy_CurrMb2[15:8]; end + 1:begin Inter_blk_mvx <= mvx_CurrMb2[23:16];Inter_blk_mvy <= mvy_CurrMb2[23:16]; end + 0:begin Inter_blk_mvx <= mvx_CurrMb2[31:24];Inter_blk_mvy <= mvy_CurrMb2[31:24]; end + endcase + else //chroma 4x4 prediction + begin Inter_blk_mvx <= mvx_CurrMb2[7:0]; Inter_blk_mvy <= mvy_CurrMb2[7:0]; end + 2'b11: + if (mv_below8x8_curr) //chroma2x2 prediction + case (Inter_chroma2x2_counter) + 3:begin Inter_blk_mvx <= mvx_CurrMb3[7:0]; Inter_blk_mvy <= mvy_CurrMb3[7:0]; end + 2:begin Inter_blk_mvx <= mvx_CurrMb3[15:8]; Inter_blk_mvy <= mvy_CurrMb3[15:8]; end + 1:begin Inter_blk_mvx <= mvx_CurrMb3[23:16];Inter_blk_mvy <= mvy_CurrMb3[23:16]; end + 0:begin Inter_blk_mvx <= mvx_CurrMb3[31:24];Inter_blk_mvy <= mvy_CurrMb3[31:24]; end + endcase + else //chroma 4x4 prediction + begin Inter_blk_mvx <= mvx_CurrMb3[7:0]; Inter_blk_mvy <= mvy_CurrMb3[7:0]; end + endcase + end + else + begin Inter_blk_mvx <= 0; Inter_blk_mvy <= 0; end + //---------------------------------------------------------------------------------------- + //Describes the offset of each blk4x4 inside a MB + //---------------------------------------------------------------------------------------- + // xOffset = 0 for 0,2,8, 10 yOffset = 0 for 0, 1, 4, 5 + // xOffset = 4 for 1,3,9, 11 yOffset = 4 for 2, 3, 6, 7 + // xOffset = 8 for 4,6,12,14 yOffset = 8 for 8, 9, 12,13 + // xOffset = 12 for 5,7,13,15 yOffset = 12 for 10,11,14,15 + reg [3:0] xOffsetL,yOffsetL; + always @ (IsInterLuma or mv_below8x8_curr or blk4x4_rec_counter[2] or blk4x4_rec_counter[0]) + if (IsInterLuma) + begin + if (!mv_below8x8_curr) + xOffsetL <= (blk4x4_rec_counter[2])? 4'd8:4'd0; + else + case ({blk4x4_rec_counter[2],blk4x4_rec_counter[0]}) + 2'b00:xOffsetL <= 4'd0; + 2'b01:xOffsetL <= 4'd4; + 2'b10:xOffsetL <= 4'd8; + 2'b11:xOffsetL <= 4'd12; + endcase + end + else + xOffsetL <= 0; + + always @ (IsInterLuma or mv_below8x8_curr or blk4x4_rec_counter[3] or blk4x4_rec_counter[1]) + if (IsInterLuma) + begin + if (!mv_below8x8_curr) + yOffsetL <= (blk4x4_rec_counter[3])? 4'd8:4'd0; + else + case ({blk4x4_rec_counter[3],blk4x4_rec_counter[1]}) + 2'b00:yOffsetL <= 4'd0; + 2'b01:yOffsetL <= 4'd4; + 2'b10:yOffsetL <= 4'd8; + 2'b11:yOffsetL <= 4'd12; + endcase + end + else + yOffsetL <= 0; + + reg [2:0] xOffsetC,yOffsetC; + always @ (IsInterChroma or mv_below8x8_curr or blk4x4_rec_counter[0] or Inter_chroma2x2_counter[0]) + if (IsInterChroma) + begin + if (mv_below8x8_curr == 1'b0) + xOffsetC <= (blk4x4_rec_counter[0] == 1'b0)? 3'd0:3'd4; + else + case (blk4x4_rec_counter[0]) + 1'b0:xOffsetC <= (Inter_chroma2x2_counter[0] == 1'b1)? 3'd0:3'd2; + 1'b1:xOffsetC <= (Inter_chroma2x2_counter[0] == 1'b1)? 3'd4:3'd6; + endcase + end + else + xOffsetC <= 0; + + always @ (IsInterChroma or mv_below8x8_curr or blk4x4_rec_counter[1] or Inter_chroma2x2_counter[1]) + if (IsInterChroma) + begin + if (mv_below8x8_curr == 1'b0) + yOffsetC <= (blk4x4_rec_counter[1] == 1'b0)? 3'd0:3'd4; + else + case (blk4x4_rec_counter[1]) + 1'b0:yOffsetC <= (Inter_chroma2x2_counter[1] == 1'b1)? 3'd0:3'd2; + 1'b1:yOffsetC <= (Inter_chroma2x2_counter[1] == 1'b1)? 3'd4:3'd6; + endcase + end + else + yOffsetC <= 3'd0; + //---------------------------------------------------------------------------------------- + //Integer position of each left-up-most pixel of a 8x8/4x4/2x2 blk + //---------------------------------------------------------------------------------------- + wire [8:0] xIntL_unclip,yIntL_unclip; // 2's complement,bit[8] is the sign bit + wire [7:0] xIntC_unclip,yIntC_unclip; // 2's complement,bit[7] is the sign bit + assign xIntL_unclip = (IsInterLuma)? ({1'b0,mb_num_h,4'b0} + xOffsetL + {{3{Inter_blk_mvx[7]}},Inter_blk_mvx[7:2]}):0; + assign yIntL_unclip = (IsInterLuma)? ({1'b0,mb_num_v,4'b0} + yOffsetL + {{3{Inter_blk_mvy[7]}},Inter_blk_mvy[7:2]}):0; + assign xIntC_unclip = (IsInterChroma)? ({1'b0,mb_num_h,3'b0} + xOffsetC + {{3{Inter_blk_mvx[7]}},Inter_blk_mvx[7:3]}):0; + assign yIntC_unclip = (IsInterChroma)? ({1'b0,mb_num_v,3'b0} + yOffsetC + {{3{Inter_blk_mvy[7]}},Inter_blk_mvy[7:3]}):0; + + wire [8:0] xInt_org_unclip; + wire [8:0] yInt_org_unclip; + assign xInt_org_unclip = (IsInterLuma)? xIntL_unclip:{xIntC_unclip[7],xIntC_unclip}; + assign yInt_org_unclip = (IsInterLuma)? yIntL_unclip:{yIntC_unclip[7],yIntC_unclip}; + assign xInt_org_unclip_1to0 = xInt_org_unclip[1:0]; + //---------------------------------------------------------------------------------------- + //Fractional motion vector for both luma and chroma + //---------------------------------------------------------------------------------------- + wire [3:0] pos_FracL; + wire Is_InterChromaCopy;//If chroma is predicted by direct copy,calculate cycle would reduce + //from 16 cycles to 4 cycles + + assign xFracL = (IsInterLuma)? Inter_blk_mvx[1:0]:0; + assign yFracL = (IsInterLuma)? Inter_blk_mvy[1:0]:0; + assign xFracC = (IsInterChroma)? Inter_blk_mvx[2:0]:0; + assign yFracC = (IsInterChroma)? Inter_blk_mvy[2:0]:0; + assign pos_FracL = {xFracL,yFracL}; + assign Is_InterChromaCopy = (IsInterChroma && xFracC == 0 && yFracC == 0)? 1'b1:1'b0; + + //---------------------------------------------------------------------------------------- + //Inter prediction step control counter + //---------------------------------------------------------------------------------------- + //1.Preload integer pels counter + // If block partition equals 8x8 or above,preload only at first 4x4 block of each 8x8block + // If block partition is 8x4,4x8 or 4x4, preload at each 4x4 block + always @ (posedge clk) + if (reset_n == 1'b0) + blk4x4_inter_preload_counter <= 0; + //luma + else if (trigger_blk4x4_inter_pred && IsInterLuma) + begin + if (!mv_below8x8_curr && blk4x4_rec_counter[1:0] == 2'b00) + case (pos_FracL) + `pos_Int :blk4x4_inter_preload_counter <= (xInt_org_unclip[1:0] == 2'b00)? 6'd17:6'd25; + `pos_f,`pos_q,`pos_i,`pos_k,`pos_j:blk4x4_inter_preload_counter <= 6'd53; + `pos_d,`pos_h,`pos_n :blk4x4_inter_preload_counter <= (xInt_org_unclip[1:0] == 2'b00)? 6'd27:6'd40; + `pos_a,`pos_b,`pos_c :blk4x4_inter_preload_counter <= 6'd33; + `pos_e,`pos_g,`pos_p,`pos_r :blk4x4_inter_preload_counter <= 6'd49; + endcase + else if (mv_below8x8_curr) //partition below 8x8block + case (pos_FracL) + `pos_Int :blk4x4_inter_preload_counter <= (xInt_org_unclip[1:0] == 2'b00)? 6'd5:6'd9; + `pos_f,`pos_q,`pos_i,`pos_k,`pos_j:blk4x4_inter_preload_counter <= 6'd28; + `pos_d,`pos_h,`pos_n :blk4x4_inter_preload_counter <= (xInt_org_unclip[1:0] == 2'b00)? 6'd10:6'd19; + `pos_a,`pos_b,`pos_c :blk4x4_inter_preload_counter <= 6'd13; + `pos_e,`pos_g,`pos_p,`pos_r :blk4x4_inter_preload_counter <= 6'd24; + endcase + end + //chroma + else if (trigger_blk4x4_inter_pred && IsInterChroma && mv_below8x8_curr == 1'b0) + begin + if (xFracC == 0 && yFracC == 0) + blk4x4_inter_preload_counter <= (xInt_org_unclip[1:0] == 2'b00)? 6'd5:6'd9; + else + blk4x4_inter_preload_counter <= 6'd11; + end + else if (trigger_blk2x2_inter_pred && IsInterChroma && mv_below8x8_curr == 1'b1) + begin + if (xFracC == 0 && yFracC == 0) + blk4x4_inter_preload_counter <= (xInt_org_unclip[1:0] == 2'b11)? 6'd5:6'd3; + else + blk4x4_inter_preload_counter <= (xInt_org_unclip[1] == 1'b0 )? 6'd4:6'd7; + end + else if (blk4x4_inter_preload_counter != 0) + blk4x4_inter_preload_counter <= blk4x4_inter_preload_counter - 1; + + //2.Calculate counter + always @ (posedge clk) + if (reset_n == 1'b0) + blk4x4_inter_calculate_counter <= 0; + //luma + else if (IsInterLuma && ((!mv_below8x8_curr && ( + (blk4x4_rec_counter[1:0] == 2'b00 && blk4x4_inter_preload_counter == 1) || + (blk4x4_rec_counter[1:0] != 2'b00 && trigger_blk4x4_inter_pred))) || + (mv_below8x8_curr && blk4x4_inter_preload_counter == 1))) + case (pos_FracL) + `pos_j,`pos_f,`pos_q:blk4x4_inter_calculate_counter <= 4'd5; + `pos_i,`pos_k :blk4x4_inter_calculate_counter <= 4'd8; + default :blk4x4_inter_calculate_counter <= 4'd4; + endcase + //chroma + else if (blk4x4_inter_preload_counter == 1 && IsInterChroma == 1'b1) + case (mv_below8x8_curr) + 1'b0:blk4x4_inter_calculate_counter <= 4'd4; + 1'b1:blk4x4_inter_calculate_counter <= 4'd1; + endcase + else if (blk4x4_inter_calculate_counter != 0) + blk4x4_inter_calculate_counter <= blk4x4_inter_calculate_counter - 1; + + assign end_of_one_blk4x4_inter = (blk4x4_inter_calculate_counter == 4'd1 && + ((IsInterChroma && mv_below8x8_curr && Inter_chroma2x2_counter == 2'b00) || + !(IsInterChroma && mv_below8x8_curr))); + //---------------------------------------------------------------------------------------- + //Inter prediction reference frame RAM read control + //---------------------------------------------------------------------------------------- + assign ref_frame_RAM_rd = ((IsInterLuma || IsInterChroma) && blk4x4_inter_preload_counter != 6'd0 && blk4x4_inter_preload_counter != 6'd1); + + //compared with blk4x4_inter_preload_counter,blk4x4_inter_preload_counter_m2 has some advantages + //during some pos_FracL for vertical memory address decoding + wire [5:0] blk4x4_inter_preload_counter_m2; + assign blk4x4_inter_preload_counter_m2 = (blk4x4_inter_preload_counter == 6'd0 || blk4x4_inter_preload_counter == 6'd1)? + 6'd0:(blk4x4_inter_preload_counter - 2); + + //xInt_curr_offset: offset from the left-upper most pixel of current block,ranging -2 ~ +10. + //After each preload cycle,xInt_curr_offset will increase 4 + reg [4:0] xInt_curr_offset; + always @ (IsInterLuma or mv_below8x8_curr or pos_FracL or xFracC or yFracC + or xInt_org_unclip[1:0] or blk4x4_inter_preload_counter_m2 or blk4x4_inter_preload_counter) + if (blk4x4_inter_preload_counter != 6'd0 && blk4x4_inter_preload_counter != 6'd1) + begin + if (IsInterLuma) + begin + if (!mv_below8x8_curr) + case (pos_FracL) + `pos_f,`pos_q,`pos_i,`pos_k,`pos_j: + case (blk4x4_inter_preload_counter_m2[1:0]) + 2'b00:xInt_curr_offset <= 5'b01010; //+10 + 2'b01:xInt_curr_offset <= 5'b00110; //+6 + 2'b10:xInt_curr_offset <= 5'b00010; //+2 + 2'b11:xInt_curr_offset <= 5'b11110; //-2 + endcase + `pos_d,`pos_h,`pos_n: + if (xInt_org_unclip[1:0] == 2'b00) + xInt_curr_offset <= (blk4x4_inter_preload_counter_m2[0])? 4'b0:4'b0100; //+0 or +4 + else + case (blk4x4_inter_preload_counter_m2) + 6'd38,6'd35,6'd32,6'd29,6'd26,6'd23,6'd20,6'd17,6'd14,6'd11,6'd8,6'd5,6'd2: + xInt_curr_offset <= 5'b0; //+0 + 6'd37,6'd34,6'd31,6'd28,6'd25,6'd22,6'd19,6'd16,6'd13,6'd10,6'd7,6'd4,6'd1: + xInt_curr_offset <= 5'b00100; //+4 + default:xInt_curr_offset <= 5'b01000;//+8 + endcase + `pos_a,`pos_b,`pos_c: + case (blk4x4_inter_preload_counter_m2[1:0]) + 2'b00:xInt_curr_offset <= 5'b01010; //+10 + 2'b01:xInt_curr_offset <= 5'b00110; //+6 + 2'b10:xInt_curr_offset <= 5'b00010; //+2 + 2'b11:xInt_curr_offset <= 5'b11110; //-2 + endcase + `pos_Int: + if (xInt_org_unclip[1:0] == 2'b00) + xInt_curr_offset <= (blk4x4_inter_preload_counter_m2[0])? 5'b0:5'b0100; //+0 or +4 + else + case (blk4x4_inter_preload_counter_m2) + 6'd23,6'd20,6'd17,6'd14,6'd11,6'd8,6'd5,6'd2: + xInt_curr_offset <= 5'b00000; //+0 + 6'd22,6'd19,6'd16,6'd13,6'd10,6'd7,6'd4,6'd1: + xInt_curr_offset <= 5'b00100; //+4 + default:xInt_curr_offset <= 5'b01000;//+8 + endcase + `pos_e,`pos_g,`pos_p,`pos_r: + case (blk4x4_inter_preload_counter_m2) + 6'd47,6'd44,6'd5,6'd2: + xInt_curr_offset <= 5'b00000; //+0 + 6'd46,6'd43,6'd4,6'd1: + xInt_curr_offset <= 5'b00100; //+4 + 6'd45,6'd42,6'd3,6'd0: + xInt_curr_offset <= 5'b01000; //+8 + default: + case (blk4x4_inter_preload_counter_m2[1:0]) + 2'b00:xInt_curr_offset <= 5'b00010; //+2 + 2'b01:xInt_curr_offset <= 5'b11110; //-2 + 2'b10:xInt_curr_offset <= 5'b01010; //+10 + 2'b11:xInt_curr_offset <= 5'b00110; //+6 + endcase + endcase + endcase + else //block partition below 8x8 + case (pos_FracL) + `pos_f,`pos_q,`pos_i,`pos_k,`pos_j: + case (blk4x4_inter_preload_counter_m2) + 6'd26,6'd23,6'd20,6'd17,6'd14,6'd11,6'd8,6'd5,6'd2:xInt_curr_offset <= 5'b11110;//-2 + 6'd25,6'd22,6'd19,6'd16,6'd13,6'd10,6'd7,6'd4,6'd1:xInt_curr_offset <= 5'b00010;//+2 + default:xInt_curr_offset <= 5'b00110; //+6 + endcase + `pos_d,`pos_h,`pos_n: + if (xInt_org_unclip[1:0] == 2'b00) + xInt_curr_offset <= 5'b0; //+0 + else + xInt_curr_offset <= (blk4x4_inter_preload_counter_m2[0])? 5'b0:5'b00100;//+0 or +4 + `pos_a,`pos_b,`pos_c: + case (blk4x4_inter_preload_counter_m2) + 6'd11,6'd8,6'd5,6'd2:xInt_curr_offset <= 5'b11110; //-2 + 6'd10,6'd7,6'd4,6'd1:xInt_curr_offset <= 5'b00010; //+2 + default:xInt_curr_offset <= 5'b00110; //+6 + endcase + `pos_Int: + if (xInt_org_unclip[1:0] == 2'b00) + xInt_curr_offset <= 5'b0; //+0 + else + xInt_curr_offset <= (blk4x4_inter_preload_counter_m2[0])? 5'b0:5'b00100; //+0 or +4 + `pos_e,`pos_g,`pos_p,`pos_r: + case (blk4x4_inter_preload_counter_m2) + 6'd22,6'd20,6'd3,6'd1:xInt_curr_offset <= 5'b0; //+0 + 6'd21,6'd19,6'd2,6'd0:xInt_curr_offset <= 5'b00100; //+4 + 6'd18,6'd15,6'd12,6'd9,6'd6:xInt_curr_offset <= 5'b11110;//-2 + 6'd17,6'd14,6'd11,6'd8,6'd5:xInt_curr_offset <= 5'b00010;//+2 + 6'd16,6'd13,6'd10,6'd7,6'd4:xInt_curr_offset <= 5'b00110;//+6 + default:xInt_curr_offset <= 5'b0; + endcase + endcase + end + else //IsInterChroma + begin + if (!mv_below8x8_curr) + begin + if (xFracC == 0 && yFracC == 0) + begin + if (xInt_org_unclip[1:0] == 2'b00) + xInt_curr_offset <= 5'b0; + else + xInt_curr_offset <= (blk4x4_inter_preload_counter_m2[0] == 1'b1)? 5'b0:5'b0100; + end + else + xInt_curr_offset <= (blk4x4_inter_preload_counter_m2[0] == 1'b1)? 5'b0:5'b0100; + end + else //mv_below8x8_curr == 1'b1 + begin + if (xFracC == 0 && yFracC == 0) + begin + if (xInt_org_unclip[1:0] == 2'b11) // 4 preload cycles + xInt_curr_offset <= (blk4x4_inter_preload_counter_m2[0] == 1'b1)? 5'b0:5'b0100; + else + xInt_curr_offset <= 0; + end + else + begin + if (xInt_org_unclip[1] == 1'b0) + xInt_curr_offset <= 0; + else + xInt_curr_offset <= (blk4x4_inter_preload_counter_m2[0] == 1'b1)? 5'b0:5'b0100; + end + end + end + end + else //blk4x4_inter_preload_counter == 0 || blk4x4_inter_preload_counter == 1 + xInt_curr_offset <= 5'b0; + + //Derive unclipped x pos for each preload cycle + wire [8:0] xInt_addr_unclip; + assign xInt_addr_unclip = xInt_org_unclip + {{4{xInt_curr_offset[4]}},xInt_curr_offset}; + + //x addr clipped:x address in pixels + reg [7:0] xInt_addr; + always @ (xInt_addr_unclip or IsInterLuma or IsInterChroma) + if (xInt_addr_unclip[8] == 1'b1) //negative + xInt_addr <= 0; + else if (IsInterLuma) + xInt_addr <= (xInt_addr_unclip[7:0] > (`pic_width - 4))? 8'd172:xInt_addr_unclip[7:0]; + else if (IsInterChroma) + xInt_addr <= (xInt_addr_unclip[7:0] > (`half_pic_width - 4))? 8'd84:xInt_addr_unclip[7:0]; + else + xInt_addr <= 0; + + //yInt_p1:when loading from Xth line to (X-1)th line,yInt_p1 is set to 1'b1 at the last + //loading cycle of current Xth line + reg yInt_p1; + always @ (IsInterLuma or mv_below8x8_curr or pos_FracL or xFracC or yFracC + or blk4x4_inter_preload_counter or blk4x4_inter_preload_counter_m2 or xInt_org_unclip[1:0] or xInt_org_unclip[1]) + if (blk4x4_inter_preload_counter != 6'd0 && blk4x4_inter_preload_counter != 6'd1) + begin + if (IsInterLuma) + case (mv_below8x8_curr) + 1'b0: + case (pos_FracL) + `pos_f,`pos_q,`pos_i,`pos_k,`pos_j: + yInt_p1 <= (blk4x4_inter_preload_counter_m2[1:0] == 2'b00)? 1'b1:1'b0; + `pos_d,`pos_h,`pos_n: + if (xInt_org_unclip[1:0] == 2'b00) + yInt_p1 <= (blk4x4_inter_preload_counter_m2[0] == 1'b0)? 1'b1:1'b0; + else + case (blk4x4_inter_preload_counter_m2) + 6'd36,6'd33,6'd30,6'd27,6'd24,6'd21,6'd18,6'd15,6'd12,6'd9,6'd6,6'd3,6'd0: + yInt_p1 <= 1'b1; + default:yInt_p1 <= 1'b0; + endcase + `pos_a,`pos_b,`pos_c: + yInt_p1 <= (blk4x4_inter_preload_counter_m2[1:0] == 2'b00)? 1'b1:1'b0; + `pos_Int: + if (xInt_org_unclip[1:0] == 2'b00) + yInt_p1 <= (blk4x4_inter_preload_counter_m2[0] == 1'b0)? 1'b1:1'b0; + else + case (blk4x4_inter_preload_counter_m2) + 6'd21,6'd18,6'd15,6'd12,6'd9,6'd6,6'd3,6'd0:yInt_p1 <= 1'b1; + default: yInt_p1 <= 1'b0; + endcase + `pos_e,`pos_g,`pos_p,`pos_r: + case (blk4x4_inter_preload_counter_m2) + 6'd45,6'd42,6'd3,6'd0:yInt_p1 <= 1'b1; + 6'd6,6'd10,6'd14,6'd18,6'd22,6'd26,6'd30,6'd34,6'd38:yInt_p1 <= 1'b1; + default:yInt_p1 <= 1'b0; + endcase + endcase + 1'b1: //block partition below 8x8 + case (pos_FracL) + `pos_f,`pos_q,`pos_i,`pos_k,`pos_j: + case (blk4x4_inter_preload_counter_m2) + 6'd24,6'd21,6'd18,6'd15,6'd12,6'd9,6'd6,6'd3,6'd0:yInt_p1 <= 1'b1; + default:yInt_p1 <= 1'b0; + endcase + `pos_d,`pos_h,`pos_n: + if (xInt_org_unclip[1:0] == 2'b00) + yInt_p1 <= 1'b1; + else + yInt_p1 <= (blk4x4_inter_preload_counter_m2[0] == 1'b0)? 1'b1:1'b0; + `pos_a,`pos_b,`pos_c: + case (blk4x4_inter_preload_counter_m2) + 5'd9,5'd6,5'd3,5'd0 :yInt_p1 <= 1'b1; + default :yInt_p1 <= 1'b0; + endcase + `pos_Int: + if (xInt_org_unclip[1:0] == 2'b00) + yInt_p1 <= 1'b1; + else + yInt_p1 <= (blk4x4_inter_preload_counter_m2[0] == 1'b0)? 1'b1:1'b0; + `pos_e,`pos_g,`pos_p,`pos_r: + case (blk4x4_inter_preload_counter_m2) + 6'd21,6'd19,6'd2,6'd0 :yInt_p1 <= 1'b1; + 6'd4,6'd7,6'd10,6'd13,6'd16 :yInt_p1 <= 1'b1; + default :yInt_p1 <= 1'b0; + endcase + endcase + endcase + else //IsInterChroma + case (mv_below8x8_curr) + 1'b0: + if (xFracC == 0 && yFracC == 0) + begin + if (xInt_org_unclip[1:0] == 2'b00) + yInt_p1 <= 1'b1; + else + yInt_p1 <= (blk4x4_inter_preload_counter_m2[0] == 1'b0)? 1'b1:1'b0; + end + else + yInt_p1 <= (blk4x4_inter_preload_counter_m2[0] == 1'b0)? 1'b1:1'b0; + 1'b1: + if (xFracC == 0 && yFracC == 0) + begin + if (xInt_org_unclip[1:0] != 2'b11) + yInt_p1 <= 1'b1; + else + yInt_p1 <= (blk4x4_inter_preload_counter_m2[0] == 1'b0)? 1'b1:1'b0; + end + else + begin + if (xInt_org_unclip[1] == 1'b0) + yInt_p1 <= 1'b1; + else + yInt_p1 <= (blk4x4_inter_preload_counter_m2[0] == 1'b0)? 1'b1:1'b0; + end + endcase + end + else // blk4x4_inter_preload_counter == 0 || blk4x4_inter_preload_counter == 1 + yInt_p1 <= 1'b0; + + //Derive unclipped y pos for each preload cycle + reg [8:0] yInt_addr_unclip; + always @ (posedge clk) + if (reset_n == 1'b0) + yInt_addr_unclip <= 0; + else if ((IsInterLuma && (trigger_blk4x4_inter_pred && (mv_below8x8_curr || + (!mv_below8x8_curr && blk4x4_rec_counter[1:0] == 2'b00)))) || + (IsInterChroma && (!mv_below8x8_curr && trigger_blk4x4_inter_pred) || + (mv_below8x8_curr && trigger_blk2x2_inter_pred))) + begin + if (IsInterLuma) //Luma + case (pos_FracL) + `pos_a,`pos_b,`pos_c,`pos_Int: + yInt_addr_unclip <= yInt_org_unclip; + default: //need -2 here + yInt_addr_unclip <= yInt_org_unclip + 9'b111111110; + endcase + else //Chroma + yInt_addr_unclip <= yInt_org_unclip; + end + else if (blk4x4_inter_preload_counter_m2 != 0 && yInt_p1 == 1'b1) + yInt_addr_unclip <= yInt_addr_unclip + 1; + + //y addr clipped + reg [7:0] yInt_addr; + always @ (yInt_addr_unclip or IsInterLuma or IsInterChroma) + if (yInt_addr_unclip[8] == 1'b1) //negative + yInt_addr <= 0; + else if (IsInterLuma) + yInt_addr <= (yInt_addr_unclip[7:0] > (`pic_height - 1))? 8'd143:yInt_addr_unclip[7:0]; + else if (IsInterChroma) + yInt_addr <= (yInt_addr_unclip[7:0] > (`half_pic_height - 1))? 8'd71:yInt_addr_unclip[7:0]; + else + yInt_addr <= 0; + + wire [12:0] offset_constant; + wire [10:0] yInt_addr_x11; + wire [12:0] offset_yInt_addr; + assign offset_constant = (IsInterLuma)? 0:((IsInterChroma)? ((blk4x4_rec_counter < 5'd20)? 13'd6336:13'd7920):0); + assign yInt_addr_x11 = {yInt_addr,3'b0} + {2'b0,yInt_addr,1'b0} + {3'b0,yInt_addr}; + assign offset_yInt_addr = (IsInterLuma)? {yInt_addr_x11,2'b0}:{1'b0,yInt_addr_x11,1'b0}; + assign ref_frame_RAM_rd_addr = (offset_constant + {8'b0,xInt_addr[7:2]}) + {1'b0,offset_yInt_addr}; + + //---------------------------------------------------------------------------------------- + //Inter prediction output control: from LPE or from CPE + //---------------------------------------------------------------------------------------- + always @ (IsInterLuma or IsInterChroma or Is_InterChromaCopy + or blk4x4_inter_calculate_counter or pos_FracL + or Inter_pix_copy0 or Inter_pix_copy1 or Inter_pix_copy2 or Inter_pix_copy3 + or LPE0_out or LPE1_out or LPE2_out or LPE3_out + or CPE0_out or CPE1_out or CPE2_out or CPE3_out) + if (IsInterLuma && blk4x4_inter_calculate_counter != 0) + begin + Inter_blk4x4_pred_output_valid <= 2'b01; + case (pos_FracL) + `pos_Int: + begin + Inter_pred_out0 <= Inter_pix_copy0;Inter_pred_out1 <= Inter_pix_copy1; + Inter_pred_out2 <= Inter_pix_copy2;Inter_pred_out3 <= Inter_pix_copy3; + end + `pos_i,`pos_k: + if (blk4x4_inter_calculate_counter == 4'd7 || blk4x4_inter_calculate_counter == 4'd5 || + blk4x4_inter_calculate_counter == 4'd3 || blk4x4_inter_calculate_counter == 4'd1) + begin + Inter_pred_out0 <= LPE0_out;Inter_pred_out1 <= LPE1_out; + Inter_pred_out2 <= LPE2_out;Inter_pred_out3 <= LPE3_out; + end + else + begin + Inter_pred_out0 <= 0;Inter_pred_out1 <= 0;Inter_pred_out2 <= 0;Inter_pred_out3 <= 0; + end + default: + if (blk4x4_inter_calculate_counter == 4'd4 || blk4x4_inter_calculate_counter == 4'd3 || + blk4x4_inter_calculate_counter == 4'd2 || blk4x4_inter_calculate_counter == 4'd1) + begin + Inter_pred_out0 <= LPE0_out;Inter_pred_out1 <= LPE1_out; + Inter_pred_out2 <= LPE2_out;Inter_pred_out3 <= LPE3_out; + end + else + begin + Inter_pred_out0 <= 0;Inter_pred_out1 <= 0;Inter_pred_out2 <= 0;Inter_pred_out3 <= 0; + end + endcase + end + else if (IsInterChroma && blk4x4_inter_calculate_counter != 0) + begin + Inter_pred_out0 <= (Is_InterChromaCopy)? Inter_pix_copy0:CPE0_out; + Inter_pred_out1 <= (Is_InterChromaCopy)? Inter_pix_copy1:CPE1_out; + Inter_pred_out2 <= (Is_InterChromaCopy)? Inter_pix_copy2:CPE2_out; + Inter_pred_out3 <= (Is_InterChromaCopy)? Inter_pix_copy3:CPE3_out; + Inter_blk4x4_pred_output_valid <= 2'b10; + end + else + begin + Inter_pred_out0 <= 0;Inter_pred_out1 <= 0;Inter_pred_out2 <= 0;Inter_pred_out3 <= 0; + Inter_blk4x4_pred_output_valid <= 2'b00; + end +endmodule + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/Inter_pred_reg_ctrl.v b/demo_chip_rtl/rtl/nova/trunk/src/Inter_pred_reg_ctrl.v new file mode 100644 index 0000000..6a059aa --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/Inter_pred_reg_ctrl.v @@ -0,0 +1,1699 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : Inter_pred_reg_ctrl.v +// Generated : Oct 17, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Prepare the appropriate registers for Inter prediction (luma & chroma) +// Including padding +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module Inter_pred_reg_ctrl (gclk_Inter_ref_rf,reset_n,blk4x4_inter_preload_counter,ref_frame_RAM_dout, + IsInterLuma,IsInterChroma,xInt_addr_unclip,xInt_org_unclip_1to0,pos_FracL,xFracC,yFracC,mv_below8x8_curr, + + Inter_ref_00_00,Inter_ref_01_00,Inter_ref_02_00,Inter_ref_03_00,Inter_ref_04_00,Inter_ref_05_00, + Inter_ref_06_00,Inter_ref_07_00,Inter_ref_08_00,Inter_ref_09_00,Inter_ref_10_00,Inter_ref_11_00,Inter_ref_12_00, + Inter_ref_00_01,Inter_ref_01_01,Inter_ref_02_01,Inter_ref_03_01,Inter_ref_04_01,Inter_ref_05_01, + Inter_ref_06_01,Inter_ref_07_01,Inter_ref_08_01,Inter_ref_09_01,Inter_ref_10_01,Inter_ref_11_01,Inter_ref_12_01, + Inter_ref_00_02,Inter_ref_01_02,Inter_ref_02_02,Inter_ref_03_02,Inter_ref_04_02,Inter_ref_05_02, + Inter_ref_06_02,Inter_ref_07_02,Inter_ref_08_02,Inter_ref_09_02,Inter_ref_10_02,Inter_ref_11_02,Inter_ref_12_02, + Inter_ref_00_03,Inter_ref_01_03,Inter_ref_02_03,Inter_ref_03_03,Inter_ref_04_03,Inter_ref_05_03, + Inter_ref_06_03,Inter_ref_07_03,Inter_ref_08_03,Inter_ref_09_03,Inter_ref_10_03,Inter_ref_11_03,Inter_ref_12_03, + Inter_ref_00_04,Inter_ref_01_04,Inter_ref_02_04,Inter_ref_03_04,Inter_ref_04_04,Inter_ref_05_04, + Inter_ref_06_04,Inter_ref_07_04,Inter_ref_08_04,Inter_ref_09_04,Inter_ref_10_04,Inter_ref_11_04,Inter_ref_12_04, + Inter_ref_00_05,Inter_ref_01_05,Inter_ref_02_05,Inter_ref_03_05,Inter_ref_04_05,Inter_ref_05_05, + Inter_ref_06_05,Inter_ref_07_05,Inter_ref_08_05,Inter_ref_09_05,Inter_ref_10_05,Inter_ref_11_05,Inter_ref_12_05, + Inter_ref_00_06,Inter_ref_01_06,Inter_ref_02_06,Inter_ref_03_06,Inter_ref_04_06,Inter_ref_05_06, + Inter_ref_06_06,Inter_ref_07_06,Inter_ref_08_06,Inter_ref_09_06,Inter_ref_10_06,Inter_ref_11_06,Inter_ref_12_06, + Inter_ref_00_07,Inter_ref_01_07,Inter_ref_02_07,Inter_ref_03_07,Inter_ref_04_07,Inter_ref_05_07, + Inter_ref_06_07,Inter_ref_07_07,Inter_ref_08_07,Inter_ref_09_07,Inter_ref_10_07,Inter_ref_11_07,Inter_ref_12_07, + Inter_ref_00_08,Inter_ref_01_08,Inter_ref_02_08,Inter_ref_03_08,Inter_ref_04_08,Inter_ref_05_08, + Inter_ref_06_08,Inter_ref_07_08,Inter_ref_08_08,Inter_ref_09_08,Inter_ref_10_08,Inter_ref_11_08,Inter_ref_12_08, + Inter_ref_00_09,Inter_ref_01_09,Inter_ref_02_09,Inter_ref_03_09,Inter_ref_04_09,Inter_ref_05_09, + Inter_ref_06_09,Inter_ref_07_09,Inter_ref_08_09,Inter_ref_09_09,Inter_ref_10_09,Inter_ref_11_09,Inter_ref_12_09, + Inter_ref_00_10,Inter_ref_01_10,Inter_ref_02_10,Inter_ref_03_10,Inter_ref_04_10,Inter_ref_05_10, + Inter_ref_06_10,Inter_ref_07_10,Inter_ref_08_10,Inter_ref_09_10,Inter_ref_10_10,Inter_ref_11_10,Inter_ref_12_10, + Inter_ref_00_11,Inter_ref_01_11,Inter_ref_02_11,Inter_ref_03_11,Inter_ref_04_11,Inter_ref_05_11, + Inter_ref_06_11,Inter_ref_07_11,Inter_ref_08_11,Inter_ref_09_11,Inter_ref_10_11,Inter_ref_11_11,Inter_ref_12_11, + Inter_ref_00_12,Inter_ref_01_12,Inter_ref_02_12,Inter_ref_03_12,Inter_ref_04_12,Inter_ref_05_12, + Inter_ref_06_12,Inter_ref_07_12,Inter_ref_08_12,Inter_ref_09_12,Inter_ref_10_12,Inter_ref_11_12,Inter_ref_12_12); + + input gclk_Inter_ref_rf; + input reset_n; + input [5:0] blk4x4_inter_preload_counter; + input [31:0] ref_frame_RAM_dout; + input IsInterLuma,IsInterChroma; + input [8:0] xInt_addr_unclip; + input [1:0] xInt_org_unclip_1to0; + input [3:0] pos_FracL; + input [2:0] xFracC,yFracC; + input mv_below8x8_curr; + + output [7:0] Inter_ref_00_00,Inter_ref_01_00,Inter_ref_02_00,Inter_ref_03_00,Inter_ref_04_00,Inter_ref_05_00; + output [7:0] Inter_ref_06_00,Inter_ref_07_00,Inter_ref_08_00,Inter_ref_09_00,Inter_ref_10_00,Inter_ref_11_00,Inter_ref_12_00; + output [7:0] Inter_ref_00_01,Inter_ref_01_01,Inter_ref_02_01,Inter_ref_03_01,Inter_ref_04_01,Inter_ref_05_01; + output [7:0] Inter_ref_06_01,Inter_ref_07_01,Inter_ref_08_01,Inter_ref_09_01,Inter_ref_10_01,Inter_ref_11_01,Inter_ref_12_01; + output [7:0] Inter_ref_00_02,Inter_ref_01_02,Inter_ref_02_02,Inter_ref_03_02,Inter_ref_04_02,Inter_ref_05_02; + output [7:0] Inter_ref_06_02,Inter_ref_07_02,Inter_ref_08_02,Inter_ref_09_02,Inter_ref_10_02,Inter_ref_11_02,Inter_ref_12_02; + output [7:0] Inter_ref_00_03,Inter_ref_01_03,Inter_ref_02_03,Inter_ref_03_03,Inter_ref_04_03,Inter_ref_05_03; + output [7:0] Inter_ref_06_03,Inter_ref_07_03,Inter_ref_08_03,Inter_ref_09_03,Inter_ref_10_03,Inter_ref_11_03,Inter_ref_12_03; + output [7:0] Inter_ref_00_04,Inter_ref_01_04,Inter_ref_02_04,Inter_ref_03_04,Inter_ref_04_04,Inter_ref_05_04; + output [7:0] Inter_ref_06_04,Inter_ref_07_04,Inter_ref_08_04,Inter_ref_09_04,Inter_ref_10_04,Inter_ref_11_04,Inter_ref_12_04; + output [7:0] Inter_ref_00_05,Inter_ref_01_05,Inter_ref_02_05,Inter_ref_03_05,Inter_ref_04_05,Inter_ref_05_05; + output [7:0] Inter_ref_06_05,Inter_ref_07_05,Inter_ref_08_05,Inter_ref_09_05,Inter_ref_10_05,Inter_ref_11_05,Inter_ref_12_05; + output [7:0] Inter_ref_00_06,Inter_ref_01_06,Inter_ref_02_06,Inter_ref_03_06,Inter_ref_04_06,Inter_ref_05_06; + output [7:0] Inter_ref_06_06,Inter_ref_07_06,Inter_ref_08_06,Inter_ref_09_06,Inter_ref_10_06,Inter_ref_11_06,Inter_ref_12_06; + output [7:0] Inter_ref_00_07,Inter_ref_01_07,Inter_ref_02_07,Inter_ref_03_07,Inter_ref_04_07,Inter_ref_05_07; + output [7:0] Inter_ref_06_07,Inter_ref_07_07,Inter_ref_08_07,Inter_ref_09_07,Inter_ref_10_07,Inter_ref_11_07,Inter_ref_12_07; + output [7:0] Inter_ref_00_08,Inter_ref_01_08,Inter_ref_02_08,Inter_ref_03_08,Inter_ref_04_08,Inter_ref_05_08; + output [7:0] Inter_ref_06_08,Inter_ref_07_08,Inter_ref_08_08,Inter_ref_09_08,Inter_ref_10_08,Inter_ref_11_08,Inter_ref_12_08; + output [7:0] Inter_ref_00_09,Inter_ref_01_09,Inter_ref_02_09,Inter_ref_03_09,Inter_ref_04_09,Inter_ref_05_09; + output [7:0] Inter_ref_06_09,Inter_ref_07_09,Inter_ref_08_09,Inter_ref_09_09,Inter_ref_10_09,Inter_ref_11_09,Inter_ref_12_09; + output [7:0] Inter_ref_00_10,Inter_ref_01_10,Inter_ref_02_10,Inter_ref_03_10,Inter_ref_04_10,Inter_ref_05_10; + output [7:0] Inter_ref_06_10,Inter_ref_07_10,Inter_ref_08_10,Inter_ref_09_10,Inter_ref_10_10,Inter_ref_11_10,Inter_ref_12_10; + output [7:0] Inter_ref_00_11,Inter_ref_01_11,Inter_ref_02_11,Inter_ref_03_11,Inter_ref_04_11,Inter_ref_05_11; + output [7:0] Inter_ref_06_11,Inter_ref_07_11,Inter_ref_08_11,Inter_ref_09_11,Inter_ref_10_11,Inter_ref_11_11,Inter_ref_12_11; + output [7:0] Inter_ref_00_12,Inter_ref_01_12,Inter_ref_02_12,Inter_ref_03_12,Inter_ref_04_12,Inter_ref_05_12; + output [7:0] Inter_ref_06_12,Inter_ref_07_12,Inter_ref_08_12,Inter_ref_09_12,Inter_ref_10_12,Inter_ref_11_12,Inter_ref_12_12; + + reg [7:0] Inter_ref_00_00,Inter_ref_01_00,Inter_ref_02_00,Inter_ref_03_00,Inter_ref_04_00,Inter_ref_05_00; + reg [7:0] Inter_ref_06_00,Inter_ref_07_00,Inter_ref_08_00,Inter_ref_09_00,Inter_ref_10_00,Inter_ref_11_00,Inter_ref_12_00; + reg [7:0] Inter_ref_00_01,Inter_ref_01_01,Inter_ref_02_01,Inter_ref_03_01,Inter_ref_04_01,Inter_ref_05_01; + reg [7:0] Inter_ref_06_01,Inter_ref_07_01,Inter_ref_08_01,Inter_ref_09_01,Inter_ref_10_01,Inter_ref_11_01,Inter_ref_12_01; + reg [7:0] Inter_ref_00_02,Inter_ref_01_02,Inter_ref_02_02,Inter_ref_03_02,Inter_ref_04_02,Inter_ref_05_02; + reg [7:0] Inter_ref_06_02,Inter_ref_07_02,Inter_ref_08_02,Inter_ref_09_02,Inter_ref_10_02,Inter_ref_11_02,Inter_ref_12_02; + reg [7:0] Inter_ref_00_03,Inter_ref_01_03,Inter_ref_02_03,Inter_ref_03_03,Inter_ref_04_03,Inter_ref_05_03; + reg [7:0] Inter_ref_06_03,Inter_ref_07_03,Inter_ref_08_03,Inter_ref_09_03,Inter_ref_10_03,Inter_ref_11_03,Inter_ref_12_03; + reg [7:0] Inter_ref_00_04,Inter_ref_01_04,Inter_ref_02_04,Inter_ref_03_04,Inter_ref_04_04,Inter_ref_05_04; + reg [7:0] Inter_ref_06_04,Inter_ref_07_04,Inter_ref_08_04,Inter_ref_09_04,Inter_ref_10_04,Inter_ref_11_04,Inter_ref_12_04; + reg [7:0] Inter_ref_00_05,Inter_ref_01_05,Inter_ref_02_05,Inter_ref_03_05,Inter_ref_04_05,Inter_ref_05_05; + reg [7:0] Inter_ref_06_05,Inter_ref_07_05,Inter_ref_08_05,Inter_ref_09_05,Inter_ref_10_05,Inter_ref_11_05,Inter_ref_12_05; + reg [7:0] Inter_ref_00_06,Inter_ref_01_06,Inter_ref_02_06,Inter_ref_03_06,Inter_ref_04_06,Inter_ref_05_06; + reg [7:0] Inter_ref_06_06,Inter_ref_07_06,Inter_ref_08_06,Inter_ref_09_06,Inter_ref_10_06,Inter_ref_11_06,Inter_ref_12_06; + reg [7:0] Inter_ref_00_07,Inter_ref_01_07,Inter_ref_02_07,Inter_ref_03_07,Inter_ref_04_07,Inter_ref_05_07; + reg [7:0] Inter_ref_06_07,Inter_ref_07_07,Inter_ref_08_07,Inter_ref_09_07,Inter_ref_10_07,Inter_ref_11_07,Inter_ref_12_07; + reg [7:0] Inter_ref_00_08,Inter_ref_01_08,Inter_ref_02_08,Inter_ref_03_08,Inter_ref_04_08,Inter_ref_05_08; + reg [7:0] Inter_ref_06_08,Inter_ref_07_08,Inter_ref_08_08,Inter_ref_09_08,Inter_ref_10_08,Inter_ref_11_08,Inter_ref_12_08; + reg [7:0] Inter_ref_00_09,Inter_ref_01_09,Inter_ref_02_09,Inter_ref_03_09,Inter_ref_04_09,Inter_ref_05_09; + reg [7:0] Inter_ref_06_09,Inter_ref_07_09,Inter_ref_08_09,Inter_ref_09_09,Inter_ref_10_09,Inter_ref_11_09,Inter_ref_12_09; + reg [7:0] Inter_ref_00_10,Inter_ref_01_10,Inter_ref_02_10,Inter_ref_03_10,Inter_ref_04_10,Inter_ref_05_10; + reg [7:0] Inter_ref_06_10,Inter_ref_07_10,Inter_ref_08_10,Inter_ref_09_10,Inter_ref_10_10,Inter_ref_11_10,Inter_ref_12_10; + reg [7:0] Inter_ref_00_11,Inter_ref_01_11,Inter_ref_02_11,Inter_ref_03_11,Inter_ref_04_11,Inter_ref_05_11; + reg [7:0] Inter_ref_06_11,Inter_ref_07_11,Inter_ref_08_11,Inter_ref_09_11,Inter_ref_10_11,Inter_ref_11_11,Inter_ref_12_11; + reg [7:0] Inter_ref_00_12,Inter_ref_01_12,Inter_ref_02_12,Inter_ref_03_12,Inter_ref_04_12,Inter_ref_05_12; + reg [7:0] Inter_ref_06_12,Inter_ref_07_12,Inter_ref_08_12,Inter_ref_09_12,Inter_ref_10_12,Inter_ref_11_12,Inter_ref_12_12; + + //------------------------------------------------------------------------- + //out of bound padding + //------------------------------------------------------------------------- + //In original version where ext_frame_RAM is read async,no need to latch xInt_addr_unclip + //since it is used here in the same cycle as it is generated in Inter_pred_pipeline module. + //However,when ext_frame_RAM is changed to sync read,xInt_addr_unclip will be used one cyle later. + reg [8:0] xInt_addr_unclip_reg; + always @ (posedge gclk_Inter_ref_rf or negedge reset_n) + if (reset_n == 1'b0) + xInt_addr_unclip_reg <= 0; + else + xInt_addr_unclip_reg <= xInt_addr_unclip; + + reg [31:0] RefFrameOutPadding; + always @ (xInt_addr_unclip_reg or ref_frame_RAM_dout or IsInterLuma or IsInterChroma) + if (xInt_addr_unclip_reg[8] == 1'b1) //out of left bound + RefFrameOutPadding <= {ref_frame_RAM_dout[7:0],ref_frame_RAM_dout[7:0], + ref_frame_RAM_dout[7:0],ref_frame_RAM_dout[7:0]}; + else + begin + if ((IsInterLuma && xInt_addr_unclip_reg[7:2] > 6'b101011) || //out of right bound + (IsInterChroma && xInt_addr_unclip_reg[7:2] > 6'b010101)) + RefFrameOutPadding <= {ref_frame_RAM_dout[31:24],ref_frame_RAM_dout[31:24], + ref_frame_RAM_dout[31:24],ref_frame_RAM_dout[31:24]}; + else + RefFrameOutPadding <= ref_frame_RAM_dout; + end + //------------------------------------------------------------------------- + //Inter_ref_00_00 ~ Inter_ref_12_12 + //------------------------------------------------------------------------- + always @ (posedge gclk_Inter_ref_rf or negedge reset_n) + if (reset_n == 0) + begin + Inter_ref_00_00 <= 0;Inter_ref_01_00 <= 0;Inter_ref_02_00 <= 0;Inter_ref_03_00 <= 0; + Inter_ref_04_00 <= 0;Inter_ref_05_00 <= 0;Inter_ref_06_00 <= 0;Inter_ref_07_00 <= 0; + Inter_ref_08_00 <= 0;Inter_ref_09_00 <= 0;Inter_ref_10_00 <= 0;Inter_ref_11_00 <= 0;Inter_ref_12_00 <= 0; + Inter_ref_00_01 <= 0;Inter_ref_01_01 <= 0;Inter_ref_02_01 <= 0;Inter_ref_03_01 <= 0; + Inter_ref_04_01 <= 0;Inter_ref_05_01 <= 0;Inter_ref_06_01 <= 0;Inter_ref_07_01 <= 0; + Inter_ref_08_01 <= 0;Inter_ref_09_01 <= 0;Inter_ref_10_01 <= 0;Inter_ref_11_01 <= 0;Inter_ref_12_01 <= 0; + Inter_ref_00_02 <= 0;Inter_ref_01_02 <= 0;Inter_ref_02_02 <= 0;Inter_ref_03_02 <= 0; + Inter_ref_04_02 <= 0;Inter_ref_05_02 <= 0;Inter_ref_06_02 <= 0;Inter_ref_07_02 <= 0; + Inter_ref_08_02 <= 0;Inter_ref_09_02 <= 0;Inter_ref_10_02 <= 0;Inter_ref_11_02 <= 0;Inter_ref_12_02 <= 0; + Inter_ref_00_03 <= 0;Inter_ref_01_03 <= 0;Inter_ref_02_03 <= 0;Inter_ref_03_03 <= 0; + Inter_ref_04_03 <= 0;Inter_ref_05_03 <= 0;Inter_ref_06_03 <= 0;Inter_ref_07_03 <= 0; + Inter_ref_08_03 <= 0;Inter_ref_09_03 <= 0;Inter_ref_10_03 <= 0;Inter_ref_11_03 <= 0;Inter_ref_12_03 <= 0; + Inter_ref_00_04 <= 0;Inter_ref_01_04 <= 0;Inter_ref_02_04 <= 0;Inter_ref_03_04 <= 0; + Inter_ref_04_04 <= 0;Inter_ref_05_04 <= 0;Inter_ref_06_04 <= 0;Inter_ref_07_04 <= 0; + Inter_ref_08_04 <= 0;Inter_ref_09_04 <= 0;Inter_ref_10_04 <= 0;Inter_ref_11_04 <= 0;Inter_ref_12_04 <= 0; + Inter_ref_00_05 <= 0;Inter_ref_01_05 <= 0;Inter_ref_02_05 <= 0;Inter_ref_03_05 <= 0; + Inter_ref_04_05 <= 0;Inter_ref_05_05 <= 0;Inter_ref_06_05 <= 0;Inter_ref_07_05 <= 0; + Inter_ref_08_05 <= 0;Inter_ref_09_05 <= 0;Inter_ref_10_05 <= 0;Inter_ref_11_05 <= 0;Inter_ref_12_05 <= 0; + Inter_ref_00_06 <= 0;Inter_ref_01_06 <= 0;Inter_ref_02_06 <= 0;Inter_ref_03_06 <= 0; + Inter_ref_04_06 <= 0;Inter_ref_05_06 <= 0;Inter_ref_06_06 <= 0;Inter_ref_07_06 <= 0; + Inter_ref_08_06 <= 0;Inter_ref_09_06 <= 0;Inter_ref_10_06 <= 0;Inter_ref_11_06 <= 0;Inter_ref_12_06 <= 0; + Inter_ref_00_07 <= 0;Inter_ref_01_07 <= 0;Inter_ref_02_07 <= 0;Inter_ref_03_07 <= 0; + Inter_ref_04_07 <= 0;Inter_ref_05_07 <= 0;Inter_ref_06_07 <= 0;Inter_ref_07_07 <= 0; + Inter_ref_08_07 <= 0;Inter_ref_09_07 <= 0;Inter_ref_10_07 <= 0;Inter_ref_11_07 <= 0;Inter_ref_12_07 <= 0; + Inter_ref_00_08 <= 0;Inter_ref_01_08 <= 0;Inter_ref_02_08 <= 0;Inter_ref_03_08 <= 0; + Inter_ref_04_08 <= 0;Inter_ref_05_08 <= 0;Inter_ref_06_08 <= 0;Inter_ref_07_08 <= 0; + Inter_ref_08_08 <= 0;Inter_ref_09_08 <= 0;Inter_ref_10_08 <= 0;Inter_ref_11_08 <= 0;Inter_ref_12_08 <= 0; + Inter_ref_00_09 <= 0;Inter_ref_01_09 <= 0;Inter_ref_02_09 <= 0;Inter_ref_03_09 <= 0; + Inter_ref_04_09 <= 0;Inter_ref_05_09 <= 0;Inter_ref_06_09 <= 0;Inter_ref_07_09 <= 0; + Inter_ref_08_09 <= 0;Inter_ref_09_09 <= 0;Inter_ref_10_09 <= 0;Inter_ref_11_09 <= 0;Inter_ref_12_09 <= 0; + Inter_ref_00_10 <= 0;Inter_ref_01_10 <= 0;Inter_ref_02_10 <= 0;Inter_ref_03_10 <= 0; + Inter_ref_04_10 <= 0;Inter_ref_05_10 <= 0;Inter_ref_06_10 <= 0;Inter_ref_07_10 <= 0; + Inter_ref_08_10 <= 0;Inter_ref_09_10 <= 0;Inter_ref_10_10 <= 0;Inter_ref_11_10 <= 0;Inter_ref_12_10 <= 0; + Inter_ref_00_11 <= 0;Inter_ref_01_11 <= 0;Inter_ref_02_11 <= 0;Inter_ref_03_11 <= 0; + Inter_ref_04_11 <= 0;Inter_ref_05_11 <= 0;Inter_ref_06_11 <= 0;Inter_ref_07_11 <= 0; + Inter_ref_08_11 <= 0;Inter_ref_09_11 <= 0;Inter_ref_10_11 <= 0;Inter_ref_11_11 <= 0;Inter_ref_12_11 <= 0; + Inter_ref_00_12 <= 0;Inter_ref_01_12 <= 0;Inter_ref_02_12 <= 0;Inter_ref_03_12 <= 0; + Inter_ref_04_12 <= 0;Inter_ref_05_12 <= 0;Inter_ref_06_12 <= 0;Inter_ref_07_12 <= 0; + Inter_ref_08_12 <= 0;Inter_ref_09_12 <= 0;Inter_ref_10_12 <= 0;Inter_ref_11_12 <= 0;Inter_ref_12_12 <= 0; + end + else if (IsInterLuma && blk4x4_inter_preload_counter != 0) + case (mv_below8x8_curr) + 1'b0: + case (pos_FracL) + `pos_f,`pos_q,`pos_i,`pos_k,`pos_j: + case (xInt_org_unclip_1to0) + 2'b00: + case (blk4x4_inter_preload_counter) + 6'd52:{Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[31:16]; + 6'd51:{Inter_ref_05_00,Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding; + 6'd50:{Inter_ref_09_00,Inter_ref_08_00,Inter_ref_07_00,Inter_ref_06_00} <= RefFrameOutPadding; + 6'd49:{Inter_ref_12_00,Inter_ref_11_00,Inter_ref_10_00} <= RefFrameOutPadding[23:0]; + 6'd48:{Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[31:16]; + 6'd47:{Inter_ref_05_01,Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding; + 6'd46:{Inter_ref_09_01,Inter_ref_08_01,Inter_ref_07_01,Inter_ref_06_01} <= RefFrameOutPadding; + 6'd45:{Inter_ref_12_01,Inter_ref_11_01,Inter_ref_10_01} <= RefFrameOutPadding[23:0]; + 6'd44:{Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:16]; + 6'd43:{Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding; + 6'd42:{Inter_ref_09_02,Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02} <= RefFrameOutPadding; + 6'd41:{Inter_ref_12_02,Inter_ref_11_02,Inter_ref_10_02} <= RefFrameOutPadding[23:0]; + 6'd40:{Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:16]; + 6'd39:{Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding; + 6'd38:{Inter_ref_09_03,Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03} <= RefFrameOutPadding; + 6'd37:{Inter_ref_12_03,Inter_ref_11_03,Inter_ref_10_03} <= RefFrameOutPadding[23:0]; + 6'd36:{Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:16]; + 6'd35:{Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding; + 6'd34:{Inter_ref_09_04,Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04} <= RefFrameOutPadding; + 6'd33:{Inter_ref_12_04,Inter_ref_11_04,Inter_ref_10_04} <= RefFrameOutPadding[23:0]; + 6'd32:{Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding[31:16]; + 6'd31:{Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding; + 6'd30:{Inter_ref_09_05,Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05} <= RefFrameOutPadding; + 6'd29:{Inter_ref_12_05,Inter_ref_11_05,Inter_ref_10_05} <= RefFrameOutPadding[23:0]; + 6'd28:{Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding[31:16]; + 6'd27:{Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding; + 6'd26:{Inter_ref_09_06,Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06} <= RefFrameOutPadding; + 6'd25:{Inter_ref_12_06,Inter_ref_11_06,Inter_ref_10_06} <= RefFrameOutPadding[23:0]; + 6'd24:{Inter_ref_01_07,Inter_ref_00_07} <= RefFrameOutPadding[31:16]; + 6'd23:{Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding; + 6'd22:{Inter_ref_09_07,Inter_ref_08_07,Inter_ref_07_07,Inter_ref_06_07} <= RefFrameOutPadding; + 6'd21:{Inter_ref_12_07,Inter_ref_11_07,Inter_ref_10_07} <= RefFrameOutPadding[23:0]; + 6'd20:{Inter_ref_01_08,Inter_ref_00_08} <= RefFrameOutPadding[31:16]; + 6'd19:{Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding; + 6'd18:{Inter_ref_09_08,Inter_ref_08_08,Inter_ref_07_08,Inter_ref_06_08} <= RefFrameOutPadding; + 6'd17:{Inter_ref_12_08,Inter_ref_11_08,Inter_ref_10_08} <= RefFrameOutPadding[23:0]; + 6'd16:{Inter_ref_01_09,Inter_ref_00_09} <= RefFrameOutPadding[31:16]; + 6'd15:{Inter_ref_05_09,Inter_ref_04_09,Inter_ref_03_09,Inter_ref_02_09} <= RefFrameOutPadding; + 6'd14:{Inter_ref_09_09,Inter_ref_08_09,Inter_ref_07_09,Inter_ref_06_09} <= RefFrameOutPadding; + 6'd13:{Inter_ref_12_09,Inter_ref_11_09,Inter_ref_10_09} <= RefFrameOutPadding[23:0]; + 6'd12:{Inter_ref_01_10,Inter_ref_00_10} <= RefFrameOutPadding[31:16]; + 6'd11:{Inter_ref_05_10,Inter_ref_04_10,Inter_ref_03_10,Inter_ref_02_10} <= RefFrameOutPadding; + 6'd10:{Inter_ref_09_10,Inter_ref_08_10,Inter_ref_07_10,Inter_ref_06_10} <= RefFrameOutPadding; + 6'd9 :{Inter_ref_12_10,Inter_ref_11_10,Inter_ref_10_10} <= RefFrameOutPadding[23:0]; + 6'd8 :{Inter_ref_01_11,Inter_ref_00_11} <= RefFrameOutPadding[31:16]; + 6'd7 :{Inter_ref_05_11,Inter_ref_04_11,Inter_ref_03_11,Inter_ref_02_11} <= RefFrameOutPadding; + 6'd6 :{Inter_ref_09_11,Inter_ref_08_11,Inter_ref_07_11,Inter_ref_06_11} <= RefFrameOutPadding; + 6'd5 :{Inter_ref_12_11,Inter_ref_11_11,Inter_ref_10_11} <= RefFrameOutPadding[23:0]; + 6'd4 :{Inter_ref_01_12,Inter_ref_00_12} <= RefFrameOutPadding[31:16]; + 6'd3 :{Inter_ref_05_12,Inter_ref_04_12,Inter_ref_03_12,Inter_ref_02_12} <= RefFrameOutPadding; + 6'd2 :{Inter_ref_09_12,Inter_ref_08_12,Inter_ref_07_12,Inter_ref_06_12} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_12_12,Inter_ref_11_12,Inter_ref_10_12} <= RefFrameOutPadding[23:0]; + endcase + 2'b01: + case (blk4x4_inter_preload_counter) + 6'd52:Inter_ref_00_00 <= RefFrameOutPadding[31:24]; + 6'd51:{Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00,Inter_ref_01_00} <= RefFrameOutPadding; + 6'd50:{Inter_ref_08_00,Inter_ref_07_00,Inter_ref_06_00,Inter_ref_05_00} <= RefFrameOutPadding; + 6'd49:{Inter_ref_12_00,Inter_ref_11_00,Inter_ref_10_00,Inter_ref_09_00} <= RefFrameOutPadding; + 6'd48:Inter_ref_00_01 <= RefFrameOutPadding[31:24]; + 6'd47:{Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01,Inter_ref_01_01} <= RefFrameOutPadding; + 6'd46:{Inter_ref_08_01,Inter_ref_07_01,Inter_ref_06_01,Inter_ref_05_01} <= RefFrameOutPadding; + 6'd45:{Inter_ref_12_01,Inter_ref_11_01,Inter_ref_10_01,Inter_ref_09_01} <= RefFrameOutPadding; + 6'd44:Inter_ref_00_02 <= RefFrameOutPadding[31:24]; + 6'd43:{Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02} <= RefFrameOutPadding; + 6'd42:{Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02} <= RefFrameOutPadding; + 6'd41:{Inter_ref_12_02,Inter_ref_11_02,Inter_ref_10_02,Inter_ref_09_02} <= RefFrameOutPadding; + 6'd40:Inter_ref_00_03 <= RefFrameOutPadding[31:24]; + 6'd39:{Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03} <= RefFrameOutPadding; + 6'd38:{Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03} <= RefFrameOutPadding; + 6'd37:{Inter_ref_12_03,Inter_ref_11_03,Inter_ref_10_03,Inter_ref_09_03} <= RefFrameOutPadding; + 6'd36:Inter_ref_00_04 <= RefFrameOutPadding[31:24]; + 6'd35:{Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04} <= RefFrameOutPadding; + 6'd34:{Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04} <= RefFrameOutPadding; + 6'd33:{Inter_ref_12_04,Inter_ref_11_04,Inter_ref_10_04,Inter_ref_09_04} <= RefFrameOutPadding; + 6'd32:Inter_ref_00_05 <= RefFrameOutPadding[31:24]; + 6'd31:{Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05,Inter_ref_01_05} <= RefFrameOutPadding; + 6'd30:{Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05} <= RefFrameOutPadding; + 6'd29:{Inter_ref_12_05,Inter_ref_11_05,Inter_ref_10_05,Inter_ref_09_05} <= RefFrameOutPadding; + 6'd28:Inter_ref_00_06 <= RefFrameOutPadding[31:24]; + 6'd27:{Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06,Inter_ref_01_06} <= RefFrameOutPadding; + 6'd26:{Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06} <= RefFrameOutPadding; + 6'd25:{Inter_ref_12_06,Inter_ref_11_06,Inter_ref_10_06,Inter_ref_09_06} <= RefFrameOutPadding; + 6'd24:Inter_ref_00_07 <= RefFrameOutPadding[31:24]; + 6'd23:{Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07,Inter_ref_01_07} <= RefFrameOutPadding; + 6'd22:{Inter_ref_08_07,Inter_ref_07_07,Inter_ref_06_07,Inter_ref_05_07} <= RefFrameOutPadding; + 6'd21:{Inter_ref_12_07,Inter_ref_11_07,Inter_ref_10_07,Inter_ref_09_07} <= RefFrameOutPadding; + 6'd20:Inter_ref_00_08 <= RefFrameOutPadding[31:24]; + 6'd19:{Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08,Inter_ref_01_08} <= RefFrameOutPadding; + 6'd18:{Inter_ref_08_08,Inter_ref_07_08,Inter_ref_06_08,Inter_ref_05_08} <= RefFrameOutPadding; + 6'd17:{Inter_ref_12_08,Inter_ref_11_08,Inter_ref_10_08,Inter_ref_09_08} <= RefFrameOutPadding; + 6'd16:Inter_ref_00_09 <= RefFrameOutPadding[31:24]; + 6'd15:{Inter_ref_04_09,Inter_ref_03_09,Inter_ref_02_09,Inter_ref_01_09} <= RefFrameOutPadding; + 6'd14:{Inter_ref_08_09,Inter_ref_07_09,Inter_ref_06_09,Inter_ref_05_09} <= RefFrameOutPadding; + 6'd13:{Inter_ref_12_09,Inter_ref_11_09,Inter_ref_10_09,Inter_ref_09_09} <= RefFrameOutPadding; + 6'd12:Inter_ref_00_10 <= RefFrameOutPadding[31:24]; + 6'd11:{Inter_ref_04_10,Inter_ref_03_10,Inter_ref_02_10,Inter_ref_01_10} <= RefFrameOutPadding; + 6'd10:{Inter_ref_08_10,Inter_ref_07_10,Inter_ref_06_10,Inter_ref_05_10} <= RefFrameOutPadding; + 6'd9 :{Inter_ref_12_10,Inter_ref_11_10,Inter_ref_10_10,Inter_ref_09_10} <= RefFrameOutPadding; + 6'd8 :Inter_ref_00_11 <= RefFrameOutPadding[31:24]; + 6'd7 :{Inter_ref_04_11,Inter_ref_03_11,Inter_ref_02_11,Inter_ref_01_11} <= RefFrameOutPadding; + 6'd6 :{Inter_ref_08_11,Inter_ref_07_11,Inter_ref_06_11,Inter_ref_05_11} <= RefFrameOutPadding; + 6'd5 :{Inter_ref_12_11,Inter_ref_11_11,Inter_ref_10_11,Inter_ref_09_11} <= RefFrameOutPadding; + 6'd4 :Inter_ref_00_12 <= RefFrameOutPadding[31:24]; + 6'd3 :{Inter_ref_04_12,Inter_ref_03_12,Inter_ref_02_12,Inter_ref_01_12} <= RefFrameOutPadding; + 6'd2 :{Inter_ref_08_12,Inter_ref_07_12,Inter_ref_06_12,Inter_ref_05_12} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_12_12,Inter_ref_11_12,Inter_ref_10_12,Inter_ref_09_12} <= RefFrameOutPadding; + endcase + 2'b10: + case (blk4x4_inter_preload_counter) + 6'd52:{Inter_ref_03_00,Inter_ref_02_00,Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding; + 6'd51:{Inter_ref_07_00,Inter_ref_06_00,Inter_ref_05_00,Inter_ref_04_00} <= RefFrameOutPadding; + 6'd50:{Inter_ref_11_00,Inter_ref_10_00,Inter_ref_09_00,Inter_ref_08_00} <= RefFrameOutPadding; + 6'd49:Inter_ref_12_00 <= RefFrameOutPadding[7:0]; + 6'd48:{Inter_ref_03_01,Inter_ref_02_01,Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding; + 6'd47:{Inter_ref_07_01,Inter_ref_06_01,Inter_ref_05_01,Inter_ref_04_01} <= RefFrameOutPadding; + 6'd46:{Inter_ref_11_01,Inter_ref_10_01,Inter_ref_09_01,Inter_ref_08_01} <= RefFrameOutPadding; + 6'd45:Inter_ref_12_01 <= RefFrameOutPadding[7:0]; + 6'd44:{Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding; + 6'd43:{Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02} <= RefFrameOutPadding; + 6'd42:{Inter_ref_11_02,Inter_ref_10_02,Inter_ref_09_02,Inter_ref_08_02} <= RefFrameOutPadding; + 6'd41:Inter_ref_12_02 <= RefFrameOutPadding[7:0]; + 6'd40:{Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding; + 6'd39:{Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03} <= RefFrameOutPadding; + 6'd38:{Inter_ref_11_03,Inter_ref_10_03,Inter_ref_09_03,Inter_ref_08_03} <= RefFrameOutPadding; + 6'd37:Inter_ref_12_03 <= RefFrameOutPadding[7:0]; + 6'd36:{Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding; + 6'd35:{Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04} <= RefFrameOutPadding; + 6'd34:{Inter_ref_11_04,Inter_ref_10_04,Inter_ref_09_04,Inter_ref_08_04} <= RefFrameOutPadding; + 6'd33:Inter_ref_12_04 <= RefFrameOutPadding[7:0]; + 6'd32:{Inter_ref_03_05,Inter_ref_02_05,Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding; + 6'd31:{Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05} <= RefFrameOutPadding; + 6'd30:{Inter_ref_11_05,Inter_ref_10_05,Inter_ref_09_05,Inter_ref_08_05} <= RefFrameOutPadding; + 6'd29:Inter_ref_12_05 <= RefFrameOutPadding[7:0]; + 6'd28:{Inter_ref_03_06,Inter_ref_02_06,Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding; + 6'd27:{Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06} <= RefFrameOutPadding; + 6'd26:{Inter_ref_11_06,Inter_ref_10_06,Inter_ref_09_06,Inter_ref_08_06} <= RefFrameOutPadding; + 6'd25:Inter_ref_12_06 <= RefFrameOutPadding[7:0]; + 6'd24:{Inter_ref_03_07,Inter_ref_02_07,Inter_ref_01_07,Inter_ref_00_07} <= RefFrameOutPadding; + 6'd23:{Inter_ref_07_07,Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07} <= RefFrameOutPadding; + 6'd22:{Inter_ref_11_07,Inter_ref_10_07,Inter_ref_09_07,Inter_ref_08_07} <= RefFrameOutPadding; + 6'd21:Inter_ref_12_07 <= RefFrameOutPadding[7:0]; + 6'd20:{Inter_ref_03_08,Inter_ref_02_08,Inter_ref_01_08,Inter_ref_00_08} <= RefFrameOutPadding; + 6'd19:{Inter_ref_07_08,Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08} <= RefFrameOutPadding; + 6'd18:{Inter_ref_11_08,Inter_ref_10_08,Inter_ref_09_08,Inter_ref_08_08} <= RefFrameOutPadding; + 6'd17:Inter_ref_12_08 <= RefFrameOutPadding[7:0]; + 6'd16:{Inter_ref_03_09,Inter_ref_02_09,Inter_ref_01_09,Inter_ref_00_09} <= RefFrameOutPadding; + 6'd15:{Inter_ref_07_09,Inter_ref_06_09,Inter_ref_05_09,Inter_ref_04_09} <= RefFrameOutPadding; + 6'd14:{Inter_ref_11_09,Inter_ref_10_09,Inter_ref_09_09,Inter_ref_08_09} <= RefFrameOutPadding; + 6'd13:Inter_ref_12_09 <= RefFrameOutPadding[7:0]; + 6'd12:{Inter_ref_03_10,Inter_ref_02_10,Inter_ref_01_10,Inter_ref_00_10} <= RefFrameOutPadding; + 6'd11:{Inter_ref_07_10,Inter_ref_06_10,Inter_ref_05_10,Inter_ref_04_10} <= RefFrameOutPadding; + 6'd10:{Inter_ref_11_10,Inter_ref_10_10,Inter_ref_09_10,Inter_ref_08_10} <= RefFrameOutPadding; + 6'd9 :Inter_ref_12_10 <= RefFrameOutPadding[7:0]; + 6'd8 :{Inter_ref_03_11,Inter_ref_02_11,Inter_ref_01_11,Inter_ref_00_11} <= RefFrameOutPadding; + 6'd7 :{Inter_ref_07_11,Inter_ref_06_11,Inter_ref_05_11,Inter_ref_04_11} <= RefFrameOutPadding; + 6'd6 :{Inter_ref_11_11,Inter_ref_10_11,Inter_ref_09_11,Inter_ref_08_11} <= RefFrameOutPadding; + 6'd5 :Inter_ref_12_11 <= RefFrameOutPadding[7:0]; + 6'd4 :{Inter_ref_03_12,Inter_ref_02_12,Inter_ref_01_12,Inter_ref_00_12} <= RefFrameOutPadding; + 6'd3 :{Inter_ref_07_12,Inter_ref_06_12,Inter_ref_05_12,Inter_ref_04_12} <= RefFrameOutPadding; + 6'd2 :{Inter_ref_11_12,Inter_ref_10_12,Inter_ref_09_12,Inter_ref_08_12} <= RefFrameOutPadding; + 6'd1 :Inter_ref_12_12 <= RefFrameOutPadding[7:0]; + endcase + 2'b11: + case (blk4x4_inter_preload_counter) + 6'd52:{Inter_ref_02_00,Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[31:8]; + 6'd51:{Inter_ref_06_00,Inter_ref_05_00,Inter_ref_04_00,Inter_ref_03_00} <= RefFrameOutPadding; + 6'd50:{Inter_ref_10_00,Inter_ref_09_00,Inter_ref_08_00,Inter_ref_07_00} <= RefFrameOutPadding; + 6'd49:{Inter_ref_12_00,Inter_ref_11_00} <= RefFrameOutPadding[15:0]; + 6'd48:{Inter_ref_02_01,Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[31:8]; + 6'd47:{Inter_ref_06_01,Inter_ref_05_01,Inter_ref_04_01,Inter_ref_03_01} <= RefFrameOutPadding; + 6'd46:{Inter_ref_10_01,Inter_ref_09_01,Inter_ref_08_01,Inter_ref_07_01} <= RefFrameOutPadding; + 6'd45:{Inter_ref_12_01,Inter_ref_11_01} <= RefFrameOutPadding[15:0]; + 6'd44:{Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:8]; + 6'd43:{Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02} <= RefFrameOutPadding; + 6'd42:{Inter_ref_10_02,Inter_ref_09_02,Inter_ref_08_02,Inter_ref_07_02} <= RefFrameOutPadding; + 6'd41:{Inter_ref_12_02,Inter_ref_11_02} <= RefFrameOutPadding[15:0]; + 6'd40:{Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:8]; + 6'd39:{Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03} <= RefFrameOutPadding; + 6'd38:{Inter_ref_10_03,Inter_ref_09_03,Inter_ref_08_03,Inter_ref_07_03} <= RefFrameOutPadding; + 6'd37:{Inter_ref_12_03,Inter_ref_11_03} <= RefFrameOutPadding[15:0]; + 6'd36:{Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:8]; + 6'd35:{Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04} <= RefFrameOutPadding; + 6'd34:{Inter_ref_10_04,Inter_ref_09_04,Inter_ref_08_04,Inter_ref_07_04} <= RefFrameOutPadding; + 6'd33:{Inter_ref_12_04,Inter_ref_11_04} <= RefFrameOutPadding[15:0]; + 6'd32:{Inter_ref_02_05,Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding[31:8]; + 6'd31:{Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05} <= RefFrameOutPadding; + 6'd30:{Inter_ref_10_05,Inter_ref_09_05,Inter_ref_08_05,Inter_ref_07_05} <= RefFrameOutPadding; + 6'd29:{Inter_ref_12_05,Inter_ref_11_05} <= RefFrameOutPadding[15:0]; + 6'd28:{Inter_ref_02_06,Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding[31:8]; + 6'd27:{Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06} <= RefFrameOutPadding; + 6'd26:{Inter_ref_10_06,Inter_ref_09_06,Inter_ref_08_06,Inter_ref_07_06} <= RefFrameOutPadding; + 6'd25:{Inter_ref_12_06,Inter_ref_11_06} <= RefFrameOutPadding[15:0]; + 6'd24:{Inter_ref_02_07,Inter_ref_01_07,Inter_ref_00_07} <= RefFrameOutPadding[31:8]; + 6'd23:{Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07} <= RefFrameOutPadding; + 6'd22:{Inter_ref_10_07,Inter_ref_09_07,Inter_ref_08_07,Inter_ref_07_07} <= RefFrameOutPadding; + 6'd21:{Inter_ref_12_07,Inter_ref_11_07} <= RefFrameOutPadding[15:0]; + 6'd20:{Inter_ref_02_08,Inter_ref_01_08,Inter_ref_00_08} <= RefFrameOutPadding[31:8]; + 6'd19:{Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08} <= RefFrameOutPadding; + 6'd18:{Inter_ref_10_08,Inter_ref_09_08,Inter_ref_08_08,Inter_ref_07_08} <= RefFrameOutPadding; + 6'd17:{Inter_ref_12_08,Inter_ref_11_08} <= RefFrameOutPadding[15:0]; + 6'd16:{Inter_ref_02_09,Inter_ref_01_09,Inter_ref_00_09} <= RefFrameOutPadding[31:8]; + 6'd15:{Inter_ref_06_09,Inter_ref_05_09,Inter_ref_04_09,Inter_ref_03_09} <= RefFrameOutPadding; + 6'd14:{Inter_ref_10_09,Inter_ref_09_09,Inter_ref_08_09,Inter_ref_07_09} <= RefFrameOutPadding; + 6'd13:{Inter_ref_12_09,Inter_ref_11_09} <= RefFrameOutPadding[15:0]; + 6'd12:{Inter_ref_02_10,Inter_ref_01_10,Inter_ref_00_10} <= RefFrameOutPadding[31:8]; + 6'd11:{Inter_ref_06_10,Inter_ref_05_10,Inter_ref_04_10,Inter_ref_03_10} <= RefFrameOutPadding; + 6'd10:{Inter_ref_10_10,Inter_ref_09_10,Inter_ref_08_10,Inter_ref_07_10} <= RefFrameOutPadding; + 6'd9 :{Inter_ref_12_10,Inter_ref_11_10} <= RefFrameOutPadding[15:0]; + 6'd8 :{Inter_ref_02_11,Inter_ref_01_11,Inter_ref_00_11} <= RefFrameOutPadding[31:8]; + 6'd7 :{Inter_ref_06_11,Inter_ref_05_11,Inter_ref_04_11,Inter_ref_03_11} <= RefFrameOutPadding; + 6'd6 :{Inter_ref_10_11,Inter_ref_09_11,Inter_ref_08_11,Inter_ref_07_11} <= RefFrameOutPadding; + 6'd5 :{Inter_ref_12_11,Inter_ref_11_11} <= RefFrameOutPadding[15:0]; + 6'd4 :{Inter_ref_02_12,Inter_ref_01_12,Inter_ref_00_12} <= RefFrameOutPadding[31:8]; + 6'd3 :{Inter_ref_06_12,Inter_ref_05_12,Inter_ref_04_12,Inter_ref_03_12} <= RefFrameOutPadding; + 6'd2 :{Inter_ref_10_12,Inter_ref_09_12,Inter_ref_08_12,Inter_ref_07_12} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_12_12,Inter_ref_11_12} <= RefFrameOutPadding[15:0]; + endcase + endcase + `pos_d,`pos_h,`pos_n: + case (xInt_org_unclip_1to0) + 2'b00: + case (blk4x4_inter_preload_counter) + 6'd26:{Inter_ref_05_00,Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding; + 6'd25:{Inter_ref_09_00,Inter_ref_08_00,Inter_ref_07_00,Inter_ref_06_00} <= RefFrameOutPadding; + 6'd24:{Inter_ref_05_01,Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding; + 6'd23:{Inter_ref_09_01,Inter_ref_08_01,Inter_ref_07_01,Inter_ref_06_01} <= RefFrameOutPadding; + 6'd22:{Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding; + 6'd21:{Inter_ref_09_02,Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02} <= RefFrameOutPadding; + 6'd20:{Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding; + 6'd19:{Inter_ref_09_03,Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03} <= RefFrameOutPadding; + 6'd18:{Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding; + 6'd17:{Inter_ref_09_04,Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04} <= RefFrameOutPadding; + 6'd16:{Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding; + 6'd15:{Inter_ref_09_05,Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05} <= RefFrameOutPadding; + 6'd14:{Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding; + 6'd13:{Inter_ref_09_06,Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06} <= RefFrameOutPadding; + 6'd12:{Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding; + 6'd11:{Inter_ref_09_07,Inter_ref_08_07,Inter_ref_07_07,Inter_ref_06_07} <= RefFrameOutPadding; + 6'd10:{Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding; + 6'd9 :{Inter_ref_09_08,Inter_ref_08_08,Inter_ref_07_08,Inter_ref_06_08} <= RefFrameOutPadding; + 6'd8 :{Inter_ref_05_09,Inter_ref_04_09,Inter_ref_03_09,Inter_ref_02_09} <= RefFrameOutPadding; + 6'd7 :{Inter_ref_09_09,Inter_ref_08_09,Inter_ref_07_09,Inter_ref_06_09} <= RefFrameOutPadding; + 6'd6 :{Inter_ref_05_10,Inter_ref_04_10,Inter_ref_03_10,Inter_ref_02_10} <= RefFrameOutPadding; + 6'd5 :{Inter_ref_09_10,Inter_ref_08_10,Inter_ref_07_10,Inter_ref_06_10} <= RefFrameOutPadding; + 6'd4 :{Inter_ref_05_11,Inter_ref_04_11,Inter_ref_03_11,Inter_ref_02_11} <= RefFrameOutPadding; + 6'd3 :{Inter_ref_09_11,Inter_ref_08_11,Inter_ref_07_11,Inter_ref_06_11} <= RefFrameOutPadding; + 6'd2 :{Inter_ref_05_12,Inter_ref_04_12,Inter_ref_03_12,Inter_ref_02_12} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_09_12,Inter_ref_08_12,Inter_ref_07_12,Inter_ref_06_12} <= RefFrameOutPadding; + endcase + 2'b01: + case (blk4x4_inter_preload_counter) + 6'd39:{Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding[31:8]; + 6'd38:{Inter_ref_08_00,Inter_ref_07_00,Inter_ref_06_00,Inter_ref_05_00} <= RefFrameOutPadding; + 6'd37:Inter_ref_09_00 <= RefFrameOutPadding[7:0]; + 6'd36:{Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding[31:8]; + 6'd35:{Inter_ref_08_01,Inter_ref_07_01,Inter_ref_06_01,Inter_ref_05_01} <= RefFrameOutPadding; + 6'd34:Inter_ref_09_01 <= RefFrameOutPadding[7:0]; + 6'd33:{Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding[31:8]; + 6'd32:{Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02} <= RefFrameOutPadding; + 6'd31:Inter_ref_09_02 <= RefFrameOutPadding[7:0]; + 6'd30:{Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding[31:8]; + 6'd29:{Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03} <= RefFrameOutPadding; + 6'd28:Inter_ref_09_03 <= RefFrameOutPadding[7:0]; + 6'd27:{Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding[31:8]; + 6'd26:{Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04} <= RefFrameOutPadding; + 6'd25:Inter_ref_09_04 <= RefFrameOutPadding[7:0]; + 6'd24:{Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding[31:8]; + 6'd23:{Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05} <= RefFrameOutPadding; + 6'd22:Inter_ref_09_05 <= RefFrameOutPadding[7:0]; + 6'd21:{Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding[31:8]; + 6'd20:{Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06} <= RefFrameOutPadding; + 6'd19:Inter_ref_09_06 <= RefFrameOutPadding[7:0]; + 6'd18:{Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding[31:8]; + 6'd17:{Inter_ref_08_07,Inter_ref_07_07,Inter_ref_06_07,Inter_ref_05_07} <= RefFrameOutPadding; + 6'd16:Inter_ref_09_07 <= RefFrameOutPadding[7:0]; + 6'd15:{Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding[31:8]; + 6'd14:{Inter_ref_08_08,Inter_ref_07_08,Inter_ref_06_08,Inter_ref_05_08} <= RefFrameOutPadding; + 6'd13:Inter_ref_09_08 <= RefFrameOutPadding[7:0]; + 6'd12:{Inter_ref_04_09,Inter_ref_03_09,Inter_ref_02_09} <= RefFrameOutPadding[31:8]; + 6'd11:{Inter_ref_08_09,Inter_ref_07_09,Inter_ref_06_09,Inter_ref_05_09} <= RefFrameOutPadding; + 6'd10:Inter_ref_09_09 <= RefFrameOutPadding[7:0]; + 6'd9 :{Inter_ref_04_10,Inter_ref_03_10,Inter_ref_02_10} <= RefFrameOutPadding[31:8]; + 6'd8 :{Inter_ref_08_10,Inter_ref_07_10,Inter_ref_06_10,Inter_ref_05_10} <= RefFrameOutPadding; + 6'd7 :Inter_ref_09_10 <= RefFrameOutPadding[7:0]; + 6'd6 :{Inter_ref_04_11,Inter_ref_03_11,Inter_ref_02_11} <= RefFrameOutPadding[31:8]; + 6'd5 :{Inter_ref_08_11,Inter_ref_07_11,Inter_ref_06_11,Inter_ref_05_11} <= RefFrameOutPadding; + 6'd4 :Inter_ref_09_11 <= RefFrameOutPadding[7:0]; + 6'd3 :{Inter_ref_04_12,Inter_ref_03_12,Inter_ref_02_12} <= RefFrameOutPadding[31:8]; + 6'd2 :{Inter_ref_08_12,Inter_ref_07_12,Inter_ref_06_12,Inter_ref_05_12} <= RefFrameOutPadding; + 6'd1 :Inter_ref_09_12 <= RefFrameOutPadding[7:0]; + endcase + 2'b10: + case (blk4x4_inter_preload_counter) + 6'd39:{Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding[31:16]; + 6'd38:{Inter_ref_07_00,Inter_ref_06_00,Inter_ref_05_00,Inter_ref_04_00} <= RefFrameOutPadding; + 6'd37:{Inter_ref_09_00,Inter_ref_08_00} <= RefFrameOutPadding[15:0]; + 6'd36:{Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding[31:16]; + 6'd35:{Inter_ref_07_01,Inter_ref_06_01,Inter_ref_05_01,Inter_ref_04_01} <= RefFrameOutPadding; + 6'd34:{Inter_ref_09_01,Inter_ref_08_01} <= RefFrameOutPadding[15:0]; + 6'd33:{Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding[31:16]; + 6'd32:{Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02} <= RefFrameOutPadding; + 6'd31:{Inter_ref_09_02,Inter_ref_08_02} <= RefFrameOutPadding[15:0]; + 6'd30:{Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding[31:16]; + 6'd29:{Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03} <= RefFrameOutPadding; + 6'd28:{Inter_ref_09_03,Inter_ref_08_03} <= RefFrameOutPadding[15:0]; + 6'd27:{Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding[31:16]; + 6'd26:{Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04} <= RefFrameOutPadding; + 6'd25:{Inter_ref_09_04,Inter_ref_08_04} <= RefFrameOutPadding[15:0]; + 6'd24:{Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding[31:16]; + 6'd23:{Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05} <= RefFrameOutPadding; + 6'd22:{Inter_ref_09_05,Inter_ref_08_05} <= RefFrameOutPadding[15:0]; + 6'd21:{Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding[31:16]; + 6'd20:{Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06} <= RefFrameOutPadding; + 6'd19:{Inter_ref_09_06,Inter_ref_08_06} <= RefFrameOutPadding[15:0]; + 6'd18:{Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding[31:16]; + 6'd17:{Inter_ref_07_07,Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07} <= RefFrameOutPadding; + 6'd16:{Inter_ref_09_07,Inter_ref_08_07} <= RefFrameOutPadding[15:0]; + 6'd15:{Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding[31:16]; + 6'd14:{Inter_ref_07_08,Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08} <= RefFrameOutPadding; + 6'd13:{Inter_ref_09_08,Inter_ref_08_08} <= RefFrameOutPadding[15:0]; + 6'd12:{Inter_ref_03_09,Inter_ref_02_09} <= RefFrameOutPadding[31:16]; + 6'd11:{Inter_ref_07_09,Inter_ref_06_09,Inter_ref_05_09,Inter_ref_04_09} <= RefFrameOutPadding; + 6'd10:{Inter_ref_09_09,Inter_ref_08_09} <= RefFrameOutPadding[15:0]; + 6'd9 :{Inter_ref_03_10,Inter_ref_02_10} <= RefFrameOutPadding[31:16]; + 6'd8 :{Inter_ref_07_10,Inter_ref_06_10,Inter_ref_05_10,Inter_ref_04_10} <= RefFrameOutPadding; + 6'd7 :{Inter_ref_09_10,Inter_ref_08_10} <= RefFrameOutPadding[15:0]; + 6'd6 :{Inter_ref_03_11,Inter_ref_02_11} <= RefFrameOutPadding[31:16]; + 6'd5 :{Inter_ref_07_11,Inter_ref_06_11,Inter_ref_05_11,Inter_ref_04_11} <= RefFrameOutPadding; + 6'd4 :{Inter_ref_09_11,Inter_ref_08_11} <= RefFrameOutPadding[15:0]; + 6'd3 :{Inter_ref_03_12,Inter_ref_02_12} <= RefFrameOutPadding[31:16]; + 6'd2 :{Inter_ref_07_12,Inter_ref_06_12,Inter_ref_05_12,Inter_ref_04_12} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_09_12,Inter_ref_08_12} <= RefFrameOutPadding[15:0]; + endcase + 2'b11: + case (blk4x4_inter_preload_counter) + 6'd39:{Inter_ref_02_00} <= RefFrameOutPadding[31:24]; + 6'd38:{Inter_ref_06_00,Inter_ref_05_00,Inter_ref_04_00,Inter_ref_03_00} <= RefFrameOutPadding; + 6'd37:{Inter_ref_09_00,Inter_ref_08_00,Inter_ref_07_00} <= RefFrameOutPadding[23:0]; + 6'd36:{Inter_ref_02_01} <= RefFrameOutPadding[31:24]; + 6'd35:{Inter_ref_06_01,Inter_ref_05_01,Inter_ref_04_01,Inter_ref_03_01} <= RefFrameOutPadding; + 6'd34:{Inter_ref_09_01,Inter_ref_08_01,Inter_ref_07_01} <= RefFrameOutPadding[23:0]; + 6'd33:{Inter_ref_02_02} <= RefFrameOutPadding[31:24]; + 6'd32:{Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02} <= RefFrameOutPadding; + 6'd31:{Inter_ref_09_02,Inter_ref_08_02,Inter_ref_07_02} <= RefFrameOutPadding[23:0]; + 6'd30:{Inter_ref_02_03} <= RefFrameOutPadding[31:24]; + 6'd29:{Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03} <= RefFrameOutPadding; + 6'd28:{Inter_ref_09_03,Inter_ref_08_03,Inter_ref_07_03} <= RefFrameOutPadding[23:0]; + 6'd27:{Inter_ref_02_04} <= RefFrameOutPadding[31:24]; + 6'd26:{Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04} <= RefFrameOutPadding; + 6'd25:{Inter_ref_09_04,Inter_ref_08_04,Inter_ref_07_04} <= RefFrameOutPadding[23:0]; + 6'd24:{Inter_ref_02_05} <= RefFrameOutPadding[31:24]; + 6'd23:{Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05} <= RefFrameOutPadding; + 6'd22:{Inter_ref_09_05,Inter_ref_08_05,Inter_ref_07_05} <= RefFrameOutPadding[23:0]; + 6'd21:{Inter_ref_02_06} <= RefFrameOutPadding[31:24]; + 6'd20:{Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06} <= RefFrameOutPadding; + 6'd19:{Inter_ref_09_06,Inter_ref_08_06,Inter_ref_07_06} <= RefFrameOutPadding[23:0]; + 6'd18:{Inter_ref_02_07} <= RefFrameOutPadding[31:24]; + 6'd17:{Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07} <= RefFrameOutPadding; + 6'd16:{Inter_ref_09_07,Inter_ref_08_07,Inter_ref_07_07} <= RefFrameOutPadding[23:0]; + 6'd15:{Inter_ref_02_08} <= RefFrameOutPadding[31:24]; + 6'd14:{Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08} <= RefFrameOutPadding; + 6'd13:{Inter_ref_09_08,Inter_ref_08_08,Inter_ref_07_08} <= RefFrameOutPadding[23:0]; + 6'd12:{Inter_ref_02_09} <= RefFrameOutPadding[31:24]; + 6'd11:{Inter_ref_06_09,Inter_ref_05_09,Inter_ref_04_09,Inter_ref_03_09} <= RefFrameOutPadding; + 6'd10:{Inter_ref_09_09,Inter_ref_08_09,Inter_ref_07_09} <= RefFrameOutPadding[23:0]; + 6'd9 :{Inter_ref_02_10} <= RefFrameOutPadding[31:24]; + 6'd8 :{Inter_ref_06_10,Inter_ref_05_10,Inter_ref_04_10,Inter_ref_03_10} <= RefFrameOutPadding; + 6'd7 :{Inter_ref_09_10,Inter_ref_08_10,Inter_ref_07_10} <= RefFrameOutPadding[23:0]; + 6'd6 :{Inter_ref_02_11} <= RefFrameOutPadding[31:24]; + 6'd5 :{Inter_ref_06_11,Inter_ref_05_11,Inter_ref_04_11,Inter_ref_03_11} <= RefFrameOutPadding; + 6'd4 :{Inter_ref_09_11,Inter_ref_08_11,Inter_ref_07_11} <= RefFrameOutPadding[23:0]; + 6'd3 :{Inter_ref_02_12} <= RefFrameOutPadding[31:24]; + 6'd2 :{Inter_ref_06_12,Inter_ref_05_12,Inter_ref_04_12,Inter_ref_03_12} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_09_12,Inter_ref_08_12,Inter_ref_07_12} <= RefFrameOutPadding[23:0]; + endcase + endcase + `pos_a,`pos_b,`pos_c: + case (xInt_org_unclip_1to0) + 2'b00: + case (blk4x4_inter_preload_counter) + 6'd32:{Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:16]; + 6'd31:{Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding; + 6'd30:{Inter_ref_09_02,Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02} <= RefFrameOutPadding; + 6'd29:{Inter_ref_12_02,Inter_ref_11_02,Inter_ref_10_02} <= RefFrameOutPadding[23:0]; + 6'd28:{Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:16]; + 6'd27:{Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding; + 6'd26:{Inter_ref_09_03,Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03} <= RefFrameOutPadding; + 6'd25:{Inter_ref_12_03,Inter_ref_11_03,Inter_ref_10_03} <= RefFrameOutPadding[23:0]; + 6'd24:{Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:16]; + 6'd23:{Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding; + 6'd22:{Inter_ref_09_04,Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04} <= RefFrameOutPadding; + 6'd21:{Inter_ref_12_04,Inter_ref_11_04,Inter_ref_10_04} <= RefFrameOutPadding[23:0]; + 6'd20:{Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding[31:16]; + 6'd19:{Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding; + 6'd18:{Inter_ref_09_05,Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05} <= RefFrameOutPadding; + 6'd17:{Inter_ref_12_05,Inter_ref_11_05,Inter_ref_10_05} <= RefFrameOutPadding[23:0]; + 6'd16:{Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding[31:16]; + 6'd15:{Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding; + 6'd14:{Inter_ref_09_06,Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06} <= RefFrameOutPadding; + 6'd13:{Inter_ref_12_06,Inter_ref_11_06,Inter_ref_10_06} <= RefFrameOutPadding[23:0]; + 6'd12:{Inter_ref_01_07,Inter_ref_00_07} <= RefFrameOutPadding[31:16]; + 6'd11:{Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding; + 6'd10:{Inter_ref_09_07,Inter_ref_08_07,Inter_ref_07_07,Inter_ref_06_07} <= RefFrameOutPadding; + 6'd9 :{Inter_ref_12_07,Inter_ref_11_07,Inter_ref_10_07} <= RefFrameOutPadding[23:0]; + 6'd8 :{Inter_ref_01_08,Inter_ref_00_08} <= RefFrameOutPadding[31:16]; + 6'd7 :{Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding; + 6'd6 :{Inter_ref_09_08,Inter_ref_08_08,Inter_ref_07_08,Inter_ref_06_08} <= RefFrameOutPadding; + 6'd5 :{Inter_ref_12_08,Inter_ref_11_08,Inter_ref_10_08} <= RefFrameOutPadding[23:0]; + 6'd4 :{Inter_ref_01_09,Inter_ref_00_09} <= RefFrameOutPadding[31:16]; + 6'd3 :{Inter_ref_05_09,Inter_ref_04_09,Inter_ref_03_09,Inter_ref_02_09} <= RefFrameOutPadding; + 6'd2 :{Inter_ref_09_09,Inter_ref_08_09,Inter_ref_07_09,Inter_ref_06_09} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_12_09,Inter_ref_11_09,Inter_ref_10_09} <= RefFrameOutPadding[23:0]; + endcase + 2'b01: + case (blk4x4_inter_preload_counter) + 6'd32:Inter_ref_00_02 <= RefFrameOutPadding[31:24]; + 6'd31:{Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02} <= RefFrameOutPadding; + 6'd30:{Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02} <= RefFrameOutPadding; + 6'd29:{Inter_ref_12_02,Inter_ref_11_02,Inter_ref_10_02,Inter_ref_09_02} <= RefFrameOutPadding; + 6'd28:Inter_ref_00_03 <= RefFrameOutPadding[31:24]; + 6'd27:{Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03} <= RefFrameOutPadding; + 6'd26:{Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03} <= RefFrameOutPadding; + 6'd25:{Inter_ref_12_03,Inter_ref_11_03,Inter_ref_10_03,Inter_ref_09_03} <= RefFrameOutPadding; + 6'd24:Inter_ref_00_04 <= RefFrameOutPadding[31:24]; + 6'd23:{Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04} <= RefFrameOutPadding; + 6'd22:{Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04} <= RefFrameOutPadding; + 6'd21:{Inter_ref_12_04,Inter_ref_11_04,Inter_ref_10_04,Inter_ref_09_04} <= RefFrameOutPadding; + 6'd20:Inter_ref_00_05 <= RefFrameOutPadding[31:24]; + 6'd19:{Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05,Inter_ref_01_05} <= RefFrameOutPadding; + 6'd18:{Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05} <= RefFrameOutPadding; + 6'd17:{Inter_ref_12_05,Inter_ref_11_05,Inter_ref_10_05,Inter_ref_09_05} <= RefFrameOutPadding; + 6'd16:Inter_ref_00_06 <= RefFrameOutPadding[31:24]; + 6'd15:{Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06,Inter_ref_01_06} <= RefFrameOutPadding; + 6'd14:{Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06} <= RefFrameOutPadding; + 6'd13:{Inter_ref_12_06,Inter_ref_11_06,Inter_ref_10_06,Inter_ref_09_06} <= RefFrameOutPadding; + 6'd12:Inter_ref_00_07 <= RefFrameOutPadding[31:24]; + 6'd11:{Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07,Inter_ref_01_07} <= RefFrameOutPadding; + 6'd10:{Inter_ref_08_07,Inter_ref_07_07,Inter_ref_06_07,Inter_ref_05_07} <= RefFrameOutPadding; + 6'd9 :{Inter_ref_12_07,Inter_ref_11_07,Inter_ref_10_07,Inter_ref_09_07} <= RefFrameOutPadding; + 6'd8 :Inter_ref_00_08 <= RefFrameOutPadding[31:24]; + 6'd7 :{Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08,Inter_ref_01_08} <= RefFrameOutPadding; + 6'd6 :{Inter_ref_08_08,Inter_ref_07_08,Inter_ref_06_08,Inter_ref_05_08} <= RefFrameOutPadding; + 6'd5 :{Inter_ref_12_08,Inter_ref_11_08,Inter_ref_10_08,Inter_ref_09_08} <= RefFrameOutPadding; + 6'd4 :Inter_ref_00_09 <= RefFrameOutPadding[31:24]; + 6'd3 :{Inter_ref_04_09,Inter_ref_03_09,Inter_ref_02_09,Inter_ref_01_09} <= RefFrameOutPadding; + 6'd2 :{Inter_ref_08_09,Inter_ref_07_09,Inter_ref_06_09,Inter_ref_05_09} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_12_09,Inter_ref_11_09,Inter_ref_10_09,Inter_ref_09_09} <= RefFrameOutPadding; + endcase + 2'b10: + case (blk4x4_inter_preload_counter) + 6'd32:{Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding; + 6'd31:{Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02} <= RefFrameOutPadding; + 6'd30:{Inter_ref_11_02,Inter_ref_10_02,Inter_ref_09_02,Inter_ref_08_02} <= RefFrameOutPadding; + 6'd29:Inter_ref_12_02 <= RefFrameOutPadding[7:0]; + 6'd28:{Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding; + 6'd27:{Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03} <= RefFrameOutPadding; + 6'd26:{Inter_ref_11_03,Inter_ref_10_03,Inter_ref_09_03,Inter_ref_08_03} <= RefFrameOutPadding; + 6'd25:Inter_ref_12_03 <= RefFrameOutPadding[7:0]; + 6'd24:{Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding; + 6'd23:{Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04} <= RefFrameOutPadding; + 6'd22:{Inter_ref_11_04,Inter_ref_10_04,Inter_ref_09_04,Inter_ref_08_04} <= RefFrameOutPadding; + 6'd21:Inter_ref_12_04 <= RefFrameOutPadding[7:0]; + 6'd20:{Inter_ref_03_05,Inter_ref_02_05,Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding; + 6'd19:{Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05} <= RefFrameOutPadding; + 6'd18:{Inter_ref_11_05,Inter_ref_10_05,Inter_ref_09_05,Inter_ref_08_05} <= RefFrameOutPadding; + 6'd17:Inter_ref_12_05 <= RefFrameOutPadding[7:0]; + 6'd16:{Inter_ref_03_06,Inter_ref_02_06,Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding; + 6'd15:{Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06} <= RefFrameOutPadding; + 6'd14:{Inter_ref_11_06,Inter_ref_10_06,Inter_ref_09_06,Inter_ref_08_06} <= RefFrameOutPadding; + 6'd13:Inter_ref_12_06 <= RefFrameOutPadding[7:0]; + 6'd12:{Inter_ref_03_07,Inter_ref_02_07,Inter_ref_01_07,Inter_ref_00_07} <= RefFrameOutPadding; + 6'd11:{Inter_ref_07_07,Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07} <= RefFrameOutPadding; + 6'd10:{Inter_ref_11_07,Inter_ref_10_07,Inter_ref_09_07,Inter_ref_08_07} <= RefFrameOutPadding; + 6'd9 :Inter_ref_12_07 <= RefFrameOutPadding[7:0]; + 6'd8 :{Inter_ref_03_08,Inter_ref_02_08,Inter_ref_01_08,Inter_ref_00_08} <= RefFrameOutPadding; + 6'd7 :{Inter_ref_07_08,Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08} <= RefFrameOutPadding; + 6'd6 :{Inter_ref_11_08,Inter_ref_10_08,Inter_ref_09_08,Inter_ref_08_08} <= RefFrameOutPadding; + 6'd5 :Inter_ref_12_08 <= RefFrameOutPadding[7:0]; + 6'd4 :{Inter_ref_03_09,Inter_ref_02_09,Inter_ref_01_09,Inter_ref_00_09} <= RefFrameOutPadding; + 6'd3 :{Inter_ref_07_09,Inter_ref_06_09,Inter_ref_05_09,Inter_ref_04_09} <= RefFrameOutPadding; + 6'd2 :{Inter_ref_11_09,Inter_ref_10_09,Inter_ref_09_09,Inter_ref_08_09} <= RefFrameOutPadding; + 6'd1 :Inter_ref_12_09 <= RefFrameOutPadding[7:0]; + endcase + 2'b11: + case (blk4x4_inter_preload_counter) + 6'd32:{Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:8]; + 6'd31:{Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02} <= RefFrameOutPadding; + 6'd30:{Inter_ref_10_02,Inter_ref_09_02,Inter_ref_08_02,Inter_ref_07_02} <= RefFrameOutPadding; + 6'd29:{Inter_ref_12_02,Inter_ref_11_02} <= RefFrameOutPadding[15:0]; + 6'd28:{Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:8]; + 6'd27:{Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03} <= RefFrameOutPadding; + 6'd26:{Inter_ref_10_03,Inter_ref_09_03,Inter_ref_08_03,Inter_ref_07_03} <= RefFrameOutPadding; + 6'd25:{Inter_ref_12_03,Inter_ref_11_03} <= RefFrameOutPadding[15:0]; + 6'd24:{Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:8]; + 6'd23:{Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04} <= RefFrameOutPadding; + 6'd22:{Inter_ref_10_04,Inter_ref_09_04,Inter_ref_08_04,Inter_ref_07_04} <= RefFrameOutPadding; + 6'd21:{Inter_ref_12_04,Inter_ref_11_04} <= RefFrameOutPadding[15:0]; + 6'd20:{Inter_ref_02_05,Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding[31:8]; + 6'd19:{Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05} <= RefFrameOutPadding; + 6'd18:{Inter_ref_10_05,Inter_ref_09_05,Inter_ref_08_05,Inter_ref_07_05} <= RefFrameOutPadding; + 6'd17:{Inter_ref_12_05,Inter_ref_11_05} <= RefFrameOutPadding[15:0]; + 6'd16:{Inter_ref_02_06,Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding[31:8]; + 6'd15:{Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06} <= RefFrameOutPadding; + 6'd14:{Inter_ref_10_06,Inter_ref_09_06,Inter_ref_08_06,Inter_ref_07_06} <= RefFrameOutPadding; + 6'd13:{Inter_ref_12_06,Inter_ref_11_06} <= RefFrameOutPadding[15:0]; + 6'd12:{Inter_ref_02_07,Inter_ref_01_07,Inter_ref_00_07} <= RefFrameOutPadding[31:8]; + 6'd11:{Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07} <= RefFrameOutPadding; + 6'd10:{Inter_ref_10_07,Inter_ref_09_07,Inter_ref_08_07,Inter_ref_07_07} <= RefFrameOutPadding; + 6'd9 :{Inter_ref_12_07,Inter_ref_11_07} <= RefFrameOutPadding[15:0]; + 6'd8 :{Inter_ref_02_08,Inter_ref_01_08,Inter_ref_00_08} <= RefFrameOutPadding[31:8]; + 6'd7 :{Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08} <= RefFrameOutPadding; + 6'd6 :{Inter_ref_10_08,Inter_ref_09_08,Inter_ref_08_08,Inter_ref_07_08} <= RefFrameOutPadding; + 6'd5 :{Inter_ref_12_08,Inter_ref_11_08} <= RefFrameOutPadding[15:0]; + 6'd4 :{Inter_ref_02_09,Inter_ref_01_09,Inter_ref_00_09} <= RefFrameOutPadding[31:8]; + 6'd3 :{Inter_ref_06_09,Inter_ref_05_09,Inter_ref_04_09,Inter_ref_03_09} <= RefFrameOutPadding; + 6'd2 :{Inter_ref_10_09,Inter_ref_09_09,Inter_ref_08_09,Inter_ref_07_09} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_12_09,Inter_ref_11_09} <= RefFrameOutPadding[15:0]; + endcase + endcase + `pos_Int: + case (xInt_org_unclip_1to0) + 2'b00: + case (blk4x4_inter_preload_counter) + 6'd16:{Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding; + 6'd15:{Inter_ref_09_02,Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02} <= RefFrameOutPadding; + 6'd14:{Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding; + 6'd13:{Inter_ref_09_03,Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03} <= RefFrameOutPadding; + 6'd12:{Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding; + 6'd11:{Inter_ref_09_04,Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04} <= RefFrameOutPadding; + 6'd10:{Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding; + 6'd9 :{Inter_ref_09_05,Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05} <= RefFrameOutPadding; + 6'd8 :{Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding; + 6'd7 :{Inter_ref_09_06,Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06} <= RefFrameOutPadding; + 6'd6 :{Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding; + 6'd5 :{Inter_ref_09_07,Inter_ref_08_07,Inter_ref_07_07,Inter_ref_06_07} <= RefFrameOutPadding; + 6'd4 :{Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding; + 6'd3 :{Inter_ref_09_08,Inter_ref_08_08,Inter_ref_07_08,Inter_ref_06_08} <= RefFrameOutPadding; + 6'd2 :{Inter_ref_05_09,Inter_ref_04_09,Inter_ref_03_09,Inter_ref_02_09} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_09_09,Inter_ref_08_09,Inter_ref_07_09,Inter_ref_06_09} <= RefFrameOutPadding; + endcase + 2'b01: + case (blk4x4_inter_preload_counter) + 6'd24:{Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding[31:8]; + 6'd23:{Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02} <= RefFrameOutPadding; + 6'd22:Inter_ref_09_02 <= RefFrameOutPadding[7:0]; + 6'd21:{Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding[31:8]; + 6'd20:{Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03} <= RefFrameOutPadding; + 6'd19:Inter_ref_09_03 <= RefFrameOutPadding[7:0]; + 6'd18:{Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding[31:8]; + 6'd17:{Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04} <= RefFrameOutPadding; + 6'd16:Inter_ref_09_04 <= RefFrameOutPadding[7:0]; + 6'd15:{Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding[31:8]; + 6'd14:{Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05} <= RefFrameOutPadding; + 6'd13:Inter_ref_09_05 <= RefFrameOutPadding[7:0]; + 6'd12:{Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding[31:8]; + 6'd11:{Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06} <= RefFrameOutPadding; + 6'd10:Inter_ref_09_06 <= RefFrameOutPadding[7:0]; + 6'd9 :{Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding[31:8]; + 6'd8 :{Inter_ref_08_07,Inter_ref_07_07,Inter_ref_06_07,Inter_ref_05_07} <= RefFrameOutPadding; + 6'd7 :Inter_ref_09_07 <= RefFrameOutPadding[7:0]; + 6'd6 :{Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding[31:8]; + 6'd5 :{Inter_ref_08_08,Inter_ref_07_08,Inter_ref_06_08,Inter_ref_05_08} <= RefFrameOutPadding; + 6'd4 :Inter_ref_09_08 <= RefFrameOutPadding[7:0]; + 6'd3 :{Inter_ref_04_09,Inter_ref_03_09,Inter_ref_02_09} <= RefFrameOutPadding[31:8]; + 6'd2 :{Inter_ref_08_09,Inter_ref_07_09,Inter_ref_06_09,Inter_ref_05_09} <= RefFrameOutPadding; + 6'd1 :Inter_ref_09_09 <= RefFrameOutPadding[7:0]; + endcase + 2'b10: + case (blk4x4_inter_preload_counter) + 6'd24:{Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding[31:16]; + 6'd23:{Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02} <= RefFrameOutPadding; + 6'd22:{Inter_ref_09_02,Inter_ref_08_02} <= RefFrameOutPadding[15:0]; + 6'd21:{Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding[31:16]; + 6'd20:{Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03} <= RefFrameOutPadding; + 6'd19:{Inter_ref_09_03,Inter_ref_08_03} <= RefFrameOutPadding[15:0]; + 6'd18:{Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding[31:16]; + 6'd17:{Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04} <= RefFrameOutPadding; + 6'd16:{Inter_ref_09_04,Inter_ref_08_04} <= RefFrameOutPadding[15:0]; + 6'd15:{Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding[31:16]; + 6'd14:{Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05} <= RefFrameOutPadding; + 6'd13:{Inter_ref_09_05,Inter_ref_08_05} <= RefFrameOutPadding[15:0]; + 6'd12:{Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding[31:16]; + 6'd11:{Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06} <= RefFrameOutPadding; + 6'd10:{Inter_ref_09_06,Inter_ref_08_06} <= RefFrameOutPadding[15:0]; + 6'd9 :{Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding[31:16]; + 6'd8 :{Inter_ref_07_07,Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07} <= RefFrameOutPadding; + 6'd7 :{Inter_ref_09_07,Inter_ref_08_07} <= RefFrameOutPadding[15:0]; + 6'd6 :{Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding[31:16]; + 6'd5 :{Inter_ref_07_08,Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08} <= RefFrameOutPadding; + 6'd4 :{Inter_ref_09_08,Inter_ref_08_08} <= RefFrameOutPadding[15:0]; + 6'd3 :{Inter_ref_03_09,Inter_ref_02_09} <= RefFrameOutPadding[31:16]; + 6'd2 :{Inter_ref_07_09,Inter_ref_06_09,Inter_ref_05_09,Inter_ref_04_09} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_09_09,Inter_ref_08_09} <= RefFrameOutPadding[15:0]; + endcase + 2'b11: + case (blk4x4_inter_preload_counter) + 6'd24:{Inter_ref_02_02} <= RefFrameOutPadding[31:24]; + 6'd23:{Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02} <= RefFrameOutPadding; + 6'd22:{Inter_ref_09_02,Inter_ref_08_02,Inter_ref_07_02} <= RefFrameOutPadding[23:0]; + 6'd21:{Inter_ref_02_03} <= RefFrameOutPadding[31:24]; + 6'd20:{Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03} <= RefFrameOutPadding; + 6'd19:{Inter_ref_09_03,Inter_ref_08_03,Inter_ref_07_03} <= RefFrameOutPadding[23:0]; + 6'd18:{Inter_ref_02_04} <= RefFrameOutPadding[31:24]; + 6'd17:{Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04} <= RefFrameOutPadding; + 6'd16:{Inter_ref_09_04,Inter_ref_08_04,Inter_ref_07_04} <= RefFrameOutPadding[23:0]; + 6'd15:{Inter_ref_02_05} <= RefFrameOutPadding[31:24]; + 6'd14:{Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05} <= RefFrameOutPadding; + 6'd13:{Inter_ref_09_05,Inter_ref_08_05,Inter_ref_07_05} <= RefFrameOutPadding[23:0]; + 6'd12:{Inter_ref_02_06} <= RefFrameOutPadding[31:24]; + 6'd11:{Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06} <= RefFrameOutPadding; + 6'd10:{Inter_ref_09_06,Inter_ref_08_06,Inter_ref_07_06} <= RefFrameOutPadding[23:0]; + 6'd9 :{Inter_ref_02_07} <= RefFrameOutPadding[31:24]; + 6'd8 :{Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07} <= RefFrameOutPadding; + 6'd7 :{Inter_ref_09_07,Inter_ref_08_07,Inter_ref_07_07} <= RefFrameOutPadding[23:0]; + 6'd6 :{Inter_ref_02_08} <= RefFrameOutPadding[31:24]; + 6'd5 :{Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08} <= RefFrameOutPadding; + 6'd4 :{Inter_ref_09_08,Inter_ref_08_08,Inter_ref_07_08} <= RefFrameOutPadding[23:0]; + 6'd3 :{Inter_ref_02_09} <= RefFrameOutPadding[31:24]; + 6'd2 :{Inter_ref_06_09,Inter_ref_05_09,Inter_ref_04_09,Inter_ref_03_09} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_09_09,Inter_ref_08_09,Inter_ref_07_09} <= RefFrameOutPadding[23:0]; + endcase + endcase + `pos_e,`pos_g,`pos_p,`pos_r: + case (xInt_org_unclip_1to0) + 2'b00: + case (blk4x4_inter_preload_counter) + 6'd48:{Inter_ref_05_00,Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding; + 6'd47:{Inter_ref_09_00,Inter_ref_08_00,Inter_ref_07_00,Inter_ref_06_00} <= RefFrameOutPadding; + 6'd46:Inter_ref_10_00 <= RefFrameOutPadding[7:0]; + 6'd45:{Inter_ref_05_01,Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding; + 6'd44:{Inter_ref_09_01,Inter_ref_08_01,Inter_ref_07_01,Inter_ref_06_01} <= RefFrameOutPadding; + 6'd43:Inter_ref_10_01 <= RefFrameOutPadding[7:0]; + + 6'd42:{Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:16]; + 6'd41:{Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding; + 6'd40:{Inter_ref_09_02,Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02} <= RefFrameOutPadding; + 6'd39:{Inter_ref_12_02,Inter_ref_11_02,Inter_ref_10_02} <= RefFrameOutPadding[23:0]; + 6'd38:{Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:16]; + 6'd37:{Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding; + 6'd36:{Inter_ref_09_03,Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03} <= RefFrameOutPadding; + 6'd35:{Inter_ref_12_03,Inter_ref_11_03,Inter_ref_10_03} <= RefFrameOutPadding[23:0]; + 6'd34:{Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:16]; + 6'd33:{Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding; + 6'd32:{Inter_ref_09_04,Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04} <= RefFrameOutPadding; + 6'd31:{Inter_ref_12_04,Inter_ref_11_04,Inter_ref_10_04} <= RefFrameOutPadding[23:0]; + 6'd30:{Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding[31:16]; + 6'd29:{Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding; + 6'd28:{Inter_ref_09_05,Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05} <= RefFrameOutPadding; + 6'd27:{Inter_ref_12_05,Inter_ref_11_05,Inter_ref_10_05} <= RefFrameOutPadding[23:0]; + 6'd26:{Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding[31:16]; + 6'd25:{Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding; + 6'd24:{Inter_ref_09_06,Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06} <= RefFrameOutPadding; + 6'd23:{Inter_ref_12_06,Inter_ref_11_06,Inter_ref_10_06} <= RefFrameOutPadding[23:0]; + 6'd22:{Inter_ref_01_07,Inter_ref_00_07} <= RefFrameOutPadding[31:16]; + 6'd21:{Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding; + 6'd20:{Inter_ref_09_07,Inter_ref_08_07,Inter_ref_07_07,Inter_ref_06_07} <= RefFrameOutPadding; + 6'd19:{Inter_ref_12_07,Inter_ref_11_07,Inter_ref_10_07} <= RefFrameOutPadding[23:0]; + 6'd18:{Inter_ref_01_08,Inter_ref_00_08} <= RefFrameOutPadding[31:16]; + 6'd17:{Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding; + 6'd16:{Inter_ref_09_08,Inter_ref_08_08,Inter_ref_07_08,Inter_ref_06_08} <= RefFrameOutPadding; + 6'd15:{Inter_ref_12_08,Inter_ref_11_08,Inter_ref_10_08} <= RefFrameOutPadding[23:0]; + 6'd14:{Inter_ref_01_09,Inter_ref_00_09} <= RefFrameOutPadding[31:16]; + 6'd13:{Inter_ref_05_09,Inter_ref_04_09,Inter_ref_03_09,Inter_ref_02_09} <= RefFrameOutPadding; + 6'd12:{Inter_ref_09_09,Inter_ref_08_09,Inter_ref_07_09,Inter_ref_06_09} <= RefFrameOutPadding; + 6'd11:{Inter_ref_12_09,Inter_ref_11_09,Inter_ref_10_09} <= RefFrameOutPadding[23:0]; + 6'd10:{Inter_ref_01_10,Inter_ref_00_10} <= RefFrameOutPadding[31:16]; + 6'd9 :{Inter_ref_05_10,Inter_ref_04_10,Inter_ref_03_10,Inter_ref_02_10} <= RefFrameOutPadding; + 6'd8 :{Inter_ref_09_10,Inter_ref_08_10,Inter_ref_07_10,Inter_ref_06_10} <= RefFrameOutPadding; + 6'd7 :{Inter_ref_12_10,Inter_ref_11_10,Inter_ref_10_10} <= RefFrameOutPadding[23:0]; + + 6'd6 :{Inter_ref_05_11,Inter_ref_04_11,Inter_ref_03_11,Inter_ref_02_11} <= RefFrameOutPadding; + 6'd5 :{Inter_ref_09_11,Inter_ref_08_11,Inter_ref_07_11,Inter_ref_06_11} <= RefFrameOutPadding; + 6'd4 :Inter_ref_10_11 <= RefFrameOutPadding[7:0]; + 6'd3 :{Inter_ref_05_12,Inter_ref_04_12,Inter_ref_03_12,Inter_ref_02_12} <= RefFrameOutPadding; + 6'd2 :{Inter_ref_09_12,Inter_ref_08_12,Inter_ref_07_12,Inter_ref_06_12} <= RefFrameOutPadding; + 6'd1 :Inter_ref_10_12 <= RefFrameOutPadding[7:0]; + endcase + 2'b01: + case (blk4x4_inter_preload_counter) + 6'd48:{Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding[31:8]; + 6'd47:{Inter_ref_08_00,Inter_ref_07_00,Inter_ref_06_00,Inter_ref_05_00} <= RefFrameOutPadding; + 6'd46:{Inter_ref_10_00,Inter_ref_09_00} <= RefFrameOutPadding[15:0]; + 6'd45:{Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding[31:8]; + 6'd44:{Inter_ref_08_01,Inter_ref_07_01,Inter_ref_06_01,Inter_ref_05_01} <= RefFrameOutPadding; + 6'd43:{Inter_ref_10_01,Inter_ref_09_01} <= RefFrameOutPadding[15:0]; + + 6'd42:Inter_ref_00_02 <= RefFrameOutPadding[31:24]; + 6'd41:{Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02} <= RefFrameOutPadding; + 6'd40:{Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02} <= RefFrameOutPadding; + 6'd39:{Inter_ref_12_02,Inter_ref_11_02,Inter_ref_10_02,Inter_ref_09_02} <= RefFrameOutPadding; + 6'd38:Inter_ref_00_03 <= RefFrameOutPadding[31:24]; + 6'd37:{Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03} <= RefFrameOutPadding; + 6'd36:{Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03} <= RefFrameOutPadding; + 6'd35:{Inter_ref_12_03,Inter_ref_11_03,Inter_ref_10_03,Inter_ref_09_03} <= RefFrameOutPadding; + 6'd34:Inter_ref_00_04 <= RefFrameOutPadding[31:24]; + 6'd33:{Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04} <= RefFrameOutPadding; + 6'd32:{Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04} <= RefFrameOutPadding; + 6'd31:{Inter_ref_12_04,Inter_ref_11_04,Inter_ref_10_04,Inter_ref_09_04} <= RefFrameOutPadding; + 6'd30:Inter_ref_00_05 <= RefFrameOutPadding[31:24]; + 6'd29:{Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05,Inter_ref_01_05} <= RefFrameOutPadding; + 6'd28:{Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05} <= RefFrameOutPadding; + 6'd27:{Inter_ref_12_05,Inter_ref_11_05,Inter_ref_10_05,Inter_ref_09_05} <= RefFrameOutPadding; + 6'd26:Inter_ref_00_06 <= RefFrameOutPadding[31:24]; + 6'd25:{Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06,Inter_ref_01_06} <= RefFrameOutPadding; + 6'd24:{Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06} <= RefFrameOutPadding; + 6'd23:{Inter_ref_12_06,Inter_ref_11_06,Inter_ref_10_06,Inter_ref_09_06} <= RefFrameOutPadding; + 6'd22:Inter_ref_00_07 <= RefFrameOutPadding[31:24]; + 6'd21:{Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07,Inter_ref_01_07} <= RefFrameOutPadding; + 6'd20:{Inter_ref_08_07,Inter_ref_07_07,Inter_ref_06_07,Inter_ref_05_07} <= RefFrameOutPadding; + 6'd19:{Inter_ref_12_07,Inter_ref_11_07,Inter_ref_10_07,Inter_ref_09_07} <= RefFrameOutPadding; + 6'd18:Inter_ref_00_08 <= RefFrameOutPadding[31:24]; + 6'd17:{Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08,Inter_ref_01_08} <= RefFrameOutPadding; + 6'd16:{Inter_ref_08_08,Inter_ref_07_08,Inter_ref_06_08,Inter_ref_05_08} <= RefFrameOutPadding; + 6'd15:{Inter_ref_12_08,Inter_ref_11_08,Inter_ref_10_08,Inter_ref_09_08} <= RefFrameOutPadding; + 6'd14:Inter_ref_00_09 <= RefFrameOutPadding[31:24]; + 6'd13:{Inter_ref_04_09,Inter_ref_03_09,Inter_ref_02_09,Inter_ref_01_09} <= RefFrameOutPadding; + 6'd12:{Inter_ref_08_09,Inter_ref_07_09,Inter_ref_06_09,Inter_ref_05_09} <= RefFrameOutPadding; + 6'd11:{Inter_ref_12_09,Inter_ref_11_09,Inter_ref_10_09,Inter_ref_09_09} <= RefFrameOutPadding; + 6'd10:Inter_ref_00_10 <= RefFrameOutPadding[31:24]; + 6'd9 :{Inter_ref_04_10,Inter_ref_03_10,Inter_ref_02_10,Inter_ref_01_10} <= RefFrameOutPadding; + 6'd8 :{Inter_ref_08_10,Inter_ref_07_10,Inter_ref_06_10,Inter_ref_05_10} <= RefFrameOutPadding; + 6'd7 :{Inter_ref_12_10,Inter_ref_11_10,Inter_ref_10_10,Inter_ref_09_10} <= RefFrameOutPadding; + + 6'd6 :{Inter_ref_04_11,Inter_ref_03_11,Inter_ref_02_11} <= RefFrameOutPadding[31:8]; + 6'd5 :{Inter_ref_08_11,Inter_ref_07_11,Inter_ref_06_11,Inter_ref_05_11} <= RefFrameOutPadding; + 6'd4 :{Inter_ref_10_11,Inter_ref_09_11} <= RefFrameOutPadding[15:0]; + 6'd3 :{Inter_ref_04_12,Inter_ref_03_12,Inter_ref_02_12} <= RefFrameOutPadding[31:8]; + 6'd2 :{Inter_ref_08_12,Inter_ref_07_12,Inter_ref_06_12,Inter_ref_05_12} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_10_12,Inter_ref_09_12} <= RefFrameOutPadding[15:0]; + endcase + 2'b10: + case (blk4x4_inter_preload_counter) + 6'd48:{Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding[31:16]; + 6'd47:{Inter_ref_07_00,Inter_ref_06_00,Inter_ref_05_00,Inter_ref_04_00} <= RefFrameOutPadding; + 6'd46:{Inter_ref_10_00,Inter_ref_09_00,Inter_ref_08_00} <= RefFrameOutPadding[23:0]; + 6'd45:{Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding[31:16]; + 6'd44:{Inter_ref_07_01,Inter_ref_06_01,Inter_ref_05_01,Inter_ref_04_01} <= RefFrameOutPadding; + 6'd43:{Inter_ref_10_01,Inter_ref_09_01,Inter_ref_08_01} <= RefFrameOutPadding[23:0]; + + 6'd42:{Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding; + 6'd41:{Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02} <= RefFrameOutPadding; + 6'd40:{Inter_ref_11_02,Inter_ref_10_02,Inter_ref_09_02,Inter_ref_08_02} <= RefFrameOutPadding; + 6'd39:Inter_ref_12_02 <= RefFrameOutPadding[7:0]; + 6'd38:{Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding; + 6'd37:{Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03} <= RefFrameOutPadding; + 6'd36:{Inter_ref_11_03,Inter_ref_10_03,Inter_ref_09_03,Inter_ref_08_03} <= RefFrameOutPadding; + 6'd35:Inter_ref_12_03 <= RefFrameOutPadding[7:0]; + 6'd34:{Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding; + 6'd33:{Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04} <= RefFrameOutPadding; + 6'd32:{Inter_ref_11_04,Inter_ref_10_04,Inter_ref_09_04,Inter_ref_08_04} <= RefFrameOutPadding; + 6'd31:Inter_ref_12_04 <= RefFrameOutPadding[7:0]; + 6'd30:{Inter_ref_03_05,Inter_ref_02_05,Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding; + 6'd29:{Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05} <= RefFrameOutPadding; + 6'd28:{Inter_ref_11_05,Inter_ref_10_05,Inter_ref_09_05,Inter_ref_08_05} <= RefFrameOutPadding; + 6'd27:Inter_ref_12_05 <= RefFrameOutPadding[7:0]; + 6'd26:{Inter_ref_03_06,Inter_ref_02_06,Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding; + 6'd25:{Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06} <= RefFrameOutPadding; + 6'd24:{Inter_ref_11_06,Inter_ref_10_06,Inter_ref_09_06,Inter_ref_08_06} <= RefFrameOutPadding; + 6'd23:Inter_ref_12_06 <= RefFrameOutPadding[7:0]; + 6'd22:{Inter_ref_03_07,Inter_ref_02_07,Inter_ref_01_07,Inter_ref_00_07} <= RefFrameOutPadding; + 6'd21:{Inter_ref_07_07,Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07} <= RefFrameOutPadding; + 6'd20:{Inter_ref_11_07,Inter_ref_10_07,Inter_ref_09_07,Inter_ref_08_07} <= RefFrameOutPadding; + 6'd19:Inter_ref_12_07 <= RefFrameOutPadding[7:0]; + 6'd18:{Inter_ref_03_08,Inter_ref_02_08,Inter_ref_01_08,Inter_ref_00_08} <= RefFrameOutPadding; + 6'd17:{Inter_ref_07_08,Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08} <= RefFrameOutPadding; + 6'd16:{Inter_ref_11_08,Inter_ref_10_08,Inter_ref_09_08,Inter_ref_08_08} <= RefFrameOutPadding; + 6'd15:Inter_ref_12_08 <= RefFrameOutPadding[7:0]; + 6'd14:{Inter_ref_03_09,Inter_ref_02_09,Inter_ref_01_09,Inter_ref_00_09} <= RefFrameOutPadding; + 6'd13:{Inter_ref_07_09,Inter_ref_06_09,Inter_ref_05_09,Inter_ref_04_09} <= RefFrameOutPadding; + 6'd12:{Inter_ref_11_09,Inter_ref_10_09,Inter_ref_09_09,Inter_ref_08_09} <= RefFrameOutPadding; + 6'd11:Inter_ref_12_09 <= RefFrameOutPadding[7:0]; + 6'd10:{Inter_ref_03_10,Inter_ref_02_10,Inter_ref_01_10,Inter_ref_00_10} <= RefFrameOutPadding; + 6'd9 :{Inter_ref_07_10,Inter_ref_06_10,Inter_ref_05_10,Inter_ref_04_10} <= RefFrameOutPadding; + 6'd8 :{Inter_ref_11_10,Inter_ref_10_10,Inter_ref_09_10,Inter_ref_08_10} <= RefFrameOutPadding; + 6'd7 :Inter_ref_12_10 <= RefFrameOutPadding[7:0]; + + 6'd6 :{Inter_ref_03_11,Inter_ref_02_11} <= RefFrameOutPadding[31:16]; + 6'd5 :{Inter_ref_07_11,Inter_ref_06_11,Inter_ref_05_11,Inter_ref_04_11} <= RefFrameOutPadding; + 6'd4 :{Inter_ref_10_11,Inter_ref_09_11,Inter_ref_08_11} <= RefFrameOutPadding[23:0]; + 6'd3 :{Inter_ref_03_12,Inter_ref_02_12} <= RefFrameOutPadding[31:16]; + 6'd2 :{Inter_ref_07_12,Inter_ref_06_12,Inter_ref_05_12,Inter_ref_04_12} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_10_12,Inter_ref_09_12,Inter_ref_08_12} <= RefFrameOutPadding[23:0]; + endcase + 2'b11: + case (blk4x4_inter_preload_counter) + 6'd48:{Inter_ref_02_00} <= RefFrameOutPadding[31:24]; + 6'd47:{Inter_ref_06_00,Inter_ref_05_00,Inter_ref_04_00,Inter_ref_03_00} <= RefFrameOutPadding; + 6'd46:{Inter_ref_10_00,Inter_ref_09_00,Inter_ref_08_00,Inter_ref_07_00} <= RefFrameOutPadding; + 6'd45:{Inter_ref_02_01} <= RefFrameOutPadding[31:24]; + 6'd44:{Inter_ref_06_01,Inter_ref_05_01,Inter_ref_04_01,Inter_ref_03_01} <= RefFrameOutPadding; + 6'd43:{Inter_ref_10_01,Inter_ref_09_01,Inter_ref_08_01,Inter_ref_07_01} <= RefFrameOutPadding; + + 6'd42:{Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:8]; + 6'd41:{Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02} <= RefFrameOutPadding; + 6'd40:{Inter_ref_10_02,Inter_ref_09_02,Inter_ref_08_02,Inter_ref_07_02} <= RefFrameOutPadding; + 6'd39:{Inter_ref_12_02,Inter_ref_11_02} <= RefFrameOutPadding[15:0]; + 6'd38:{Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:8]; + 6'd37:{Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03} <= RefFrameOutPadding; + 6'd36:{Inter_ref_10_03,Inter_ref_09_03,Inter_ref_08_03,Inter_ref_07_03} <= RefFrameOutPadding; + 6'd35:{Inter_ref_12_03,Inter_ref_11_03} <= RefFrameOutPadding[15:0]; + 6'd34:{Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:8]; + 6'd33:{Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04} <= RefFrameOutPadding; + 6'd32:{Inter_ref_10_04,Inter_ref_09_04,Inter_ref_08_04,Inter_ref_07_04} <= RefFrameOutPadding; + 6'd31:{Inter_ref_12_04,Inter_ref_11_04} <= RefFrameOutPadding[15:0]; + 6'd30:{Inter_ref_02_05,Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding[31:8]; + 6'd29:{Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05} <= RefFrameOutPadding; + 6'd28:{Inter_ref_10_05,Inter_ref_09_05,Inter_ref_08_05,Inter_ref_07_05} <= RefFrameOutPadding; + 6'd27:{Inter_ref_12_05,Inter_ref_11_05} <= RefFrameOutPadding[15:0]; + 6'd26:{Inter_ref_02_06,Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding[31:8]; + 6'd25:{Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06} <= RefFrameOutPadding; + 6'd24:{Inter_ref_10_06,Inter_ref_09_06,Inter_ref_08_06,Inter_ref_07_06} <= RefFrameOutPadding; + 6'd23:{Inter_ref_12_06,Inter_ref_11_06} <= RefFrameOutPadding[15:0]; + 6'd22:{Inter_ref_02_07,Inter_ref_01_07,Inter_ref_00_07} <= RefFrameOutPadding[31:8]; + 6'd21:{Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07} <= RefFrameOutPadding; + 6'd20:{Inter_ref_10_07,Inter_ref_09_07,Inter_ref_08_07,Inter_ref_07_07} <= RefFrameOutPadding; + 6'd19:{Inter_ref_12_07,Inter_ref_11_07} <= RefFrameOutPadding[15:0]; + 6'd18:{Inter_ref_02_08,Inter_ref_01_08,Inter_ref_00_08} <= RefFrameOutPadding[31:8]; + 6'd17:{Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08} <= RefFrameOutPadding; + 6'd16:{Inter_ref_10_08,Inter_ref_09_08,Inter_ref_08_08,Inter_ref_07_08} <= RefFrameOutPadding; + 6'd15:{Inter_ref_12_08,Inter_ref_11_08} <= RefFrameOutPadding[15:0]; + 6'd14:{Inter_ref_02_09,Inter_ref_01_09,Inter_ref_00_09} <= RefFrameOutPadding[31:8]; + 6'd13:{Inter_ref_06_09,Inter_ref_05_09,Inter_ref_04_09,Inter_ref_03_09} <= RefFrameOutPadding; + 6'd12:{Inter_ref_10_09,Inter_ref_09_09,Inter_ref_08_09,Inter_ref_07_09} <= RefFrameOutPadding; + 6'd11:{Inter_ref_12_09,Inter_ref_11_09} <= RefFrameOutPadding[15:0]; + 6'd10:{Inter_ref_02_10,Inter_ref_01_10,Inter_ref_00_10} <= RefFrameOutPadding[31:8]; + 6'd9 :{Inter_ref_06_10,Inter_ref_05_10,Inter_ref_04_10,Inter_ref_03_10} <= RefFrameOutPadding; + 6'd8 :{Inter_ref_10_10,Inter_ref_09_10,Inter_ref_08_10,Inter_ref_07_10} <= RefFrameOutPadding; + 6'd7 :{Inter_ref_12_10,Inter_ref_11_10} <= RefFrameOutPadding[15:0]; + + 6'd6 :{Inter_ref_02_11} <= RefFrameOutPadding[31:24]; + 6'd5 :{Inter_ref_06_11,Inter_ref_05_11,Inter_ref_04_11,Inter_ref_03_11} <= RefFrameOutPadding; + 6'd4 :{Inter_ref_10_11,Inter_ref_09_11,Inter_ref_08_11,Inter_ref_07_11} <= RefFrameOutPadding; + 6'd3 :{Inter_ref_02_12} <= RefFrameOutPadding[31:24]; + 6'd2 :{Inter_ref_06_12,Inter_ref_05_12,Inter_ref_04_12,Inter_ref_03_12} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_10_12,Inter_ref_09_12,Inter_ref_08_12,Inter_ref_07_12} <= RefFrameOutPadding; + endcase + endcase + endcase + 1'b1: //mv_below8x8_curr == 1'b1 + case (pos_FracL) + `pos_f,`pos_q,`pos_i,`pos_k,`pos_j: + case (xInt_org_unclip_1to0) + 2'b00: + case (blk4x4_inter_preload_counter) + 6'd27:{Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[31:16]; + 6'd26:{Inter_ref_05_00,Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding; + 6'd25:{Inter_ref_08_00,Inter_ref_07_00,Inter_ref_06_00} <= RefFrameOutPadding[23:0]; + 6'd24:{Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[31:16]; + 6'd23:{Inter_ref_05_01,Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding; + 6'd22:{Inter_ref_08_01,Inter_ref_07_01,Inter_ref_06_01} <= RefFrameOutPadding[23:0]; + 6'd21:{Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:16]; + 6'd20:{Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding; + 6'd19:{Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02} <= RefFrameOutPadding[23:0]; + 6'd18:{Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:16]; + 6'd17:{Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding; + 6'd16:{Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03} <= RefFrameOutPadding[23:0]; + 6'd15:{Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:16]; + 6'd14:{Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding; + 6'd13:{Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04} <= RefFrameOutPadding[23:0]; + 6'd12:{Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding[31:16]; + 6'd11:{Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding; + 6'd10:{Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05} <= RefFrameOutPadding[23:0]; + 6'd9 :{Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding[31:16]; + 6'd8 :{Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding; + 6'd7 :{Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06} <= RefFrameOutPadding[23:0]; + 6'd6 :{Inter_ref_01_07,Inter_ref_00_07} <= RefFrameOutPadding[31:16]; + 6'd5 :{Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding; + 6'd4 :{Inter_ref_08_07,Inter_ref_07_07,Inter_ref_06_07} <= RefFrameOutPadding[23:0]; + 6'd3 :{Inter_ref_01_08,Inter_ref_00_08} <= RefFrameOutPadding[31:16]; + 6'd2 :{Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_08_08,Inter_ref_07_08,Inter_ref_06_08} <= RefFrameOutPadding[23:0]; + endcase + 2'b01: + case (blk4x4_inter_preload_counter) + 6'd27:Inter_ref_00_00 <= RefFrameOutPadding[31:24]; + 6'd26:{Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00,Inter_ref_01_00} <= RefFrameOutPadding; + 6'd25:{Inter_ref_08_00,Inter_ref_07_00,Inter_ref_06_00,Inter_ref_05_00} <= RefFrameOutPadding; + 6'd24:Inter_ref_00_01 <= RefFrameOutPadding[31:24]; + 6'd23:{Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01,Inter_ref_01_01} <= RefFrameOutPadding; + 6'd22:{Inter_ref_08_01,Inter_ref_07_01,Inter_ref_06_01,Inter_ref_05_01} <= RefFrameOutPadding; + 6'd21:Inter_ref_00_02 <= RefFrameOutPadding[31:24]; + 6'd20:{Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02} <= RefFrameOutPadding; + 6'd19:{Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02} <= RefFrameOutPadding; + 6'd18:Inter_ref_00_03 <= RefFrameOutPadding[31:24]; + 6'd17:{Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03} <= RefFrameOutPadding; + 6'd16:{Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03} <= RefFrameOutPadding; + 6'd15:Inter_ref_00_04 <= RefFrameOutPadding[31:24]; + 6'd14:{Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04} <= RefFrameOutPadding; + 6'd13:{Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04} <= RefFrameOutPadding; + 6'd12:Inter_ref_00_05 <= RefFrameOutPadding[31:24]; + 6'd11:{Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05,Inter_ref_01_05} <= RefFrameOutPadding; + 6'd10:{Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05} <= RefFrameOutPadding; + 6'd9 :Inter_ref_00_06 <= RefFrameOutPadding[31:24]; + 6'd8 :{Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06,Inter_ref_01_06} <= RefFrameOutPadding; + 6'd7 :{Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06} <= RefFrameOutPadding; + 6'd6 :Inter_ref_00_07 <= RefFrameOutPadding[31:24]; + 6'd5 :{Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07,Inter_ref_01_07} <= RefFrameOutPadding; + 6'd4 :{Inter_ref_08_07,Inter_ref_07_07,Inter_ref_06_07,Inter_ref_05_07} <= RefFrameOutPadding; + 6'd3 :Inter_ref_00_08 <= RefFrameOutPadding[31:24]; + 6'd2 :{Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08,Inter_ref_01_08} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_08_08,Inter_ref_07_08,Inter_ref_06_08,Inter_ref_05_08} <= RefFrameOutPadding; + endcase + 2'b10: + case (blk4x4_inter_preload_counter) + 6'd27:{Inter_ref_03_00,Inter_ref_02_00,Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding; + 6'd26:{Inter_ref_07_00,Inter_ref_06_00,Inter_ref_05_00,Inter_ref_04_00} <= RefFrameOutPadding; + 6'd25:Inter_ref_08_00 <= RefFrameOutPadding[7:0]; + 6'd24:{Inter_ref_03_01,Inter_ref_02_01,Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding; + 6'd23:{Inter_ref_07_01,Inter_ref_06_01,Inter_ref_05_01,Inter_ref_04_01} <= RefFrameOutPadding; + 6'd22:Inter_ref_08_01 <= RefFrameOutPadding[7:0]; + 6'd21:{Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding; + 6'd20:{Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02} <= RefFrameOutPadding; + 6'd19:Inter_ref_08_02 <= RefFrameOutPadding[7:0]; + 6'd18:{Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding; + 6'd17:{Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03} <= RefFrameOutPadding; + 6'd16:Inter_ref_08_03 <= RefFrameOutPadding[7:0]; + 6'd15:{Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding; + 6'd14:{Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04} <= RefFrameOutPadding; + 6'd13:Inter_ref_08_04 <= RefFrameOutPadding[7:0]; + 6'd12:{Inter_ref_03_05,Inter_ref_02_05,Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding; + 6'd11:{Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05} <= RefFrameOutPadding; + 6'd10:Inter_ref_08_05 <= RefFrameOutPadding[7:0]; + 6'd9 :{Inter_ref_03_06,Inter_ref_02_06,Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding; + 6'd8 :{Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06} <= RefFrameOutPadding; + 6'd7 :Inter_ref_08_06 <= RefFrameOutPadding[7:0]; + 6'd6 :{Inter_ref_03_07,Inter_ref_02_07,Inter_ref_01_07,Inter_ref_00_07} <= RefFrameOutPadding; + 6'd5 :{Inter_ref_07_07,Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07} <= RefFrameOutPadding; + 6'd4 :Inter_ref_08_07 <= RefFrameOutPadding[7:0]; + 6'd3 :{Inter_ref_03_08,Inter_ref_02_08,Inter_ref_01_08,Inter_ref_00_08} <= RefFrameOutPadding; + 6'd2 :{Inter_ref_07_08,Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08} <= RefFrameOutPadding; + 6'd1 :Inter_ref_08_08 <= RefFrameOutPadding[7:0]; + endcase + 2'b11: + case (blk4x4_inter_preload_counter) + 6'd27:{Inter_ref_02_00,Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[31:8]; + 6'd26:{Inter_ref_06_00,Inter_ref_05_00,Inter_ref_04_00,Inter_ref_03_00} <= RefFrameOutPadding; + 6'd25:{Inter_ref_08_00,Inter_ref_07_00} <= RefFrameOutPadding[15:0]; + + 6'd24:{Inter_ref_02_01,Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[31:8]; + 6'd23:{Inter_ref_06_01,Inter_ref_05_01,Inter_ref_04_01,Inter_ref_03_01} <= RefFrameOutPadding; + 6'd22:{Inter_ref_08_01,Inter_ref_07_01} <= RefFrameOutPadding[15:0]; + + 6'd21:{Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:8]; + 6'd20:{Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02} <= RefFrameOutPadding; + 6'd19:{Inter_ref_08_02,Inter_ref_07_02} <= RefFrameOutPadding[15:0]; + + 6'd18:{Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:8]; + 6'd17:{Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03} <= RefFrameOutPadding; + 6'd16:{Inter_ref_08_03,Inter_ref_07_03} <= RefFrameOutPadding[15:0]; + + 6'd15:{Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:8]; + 6'd14:{Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04} <= RefFrameOutPadding; + 6'd13:{Inter_ref_08_04,Inter_ref_07_04} <= RefFrameOutPadding[15:0]; + + 6'd12:{Inter_ref_02_05,Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding[31:8]; + 6'd11:{Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05} <= RefFrameOutPadding; + 6'd10:{Inter_ref_08_05,Inter_ref_07_05} <= RefFrameOutPadding[15:0]; + + 6'd9 :{Inter_ref_02_06,Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding[31:8]; + 6'd8 :{Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06} <= RefFrameOutPadding; + 6'd7 :{Inter_ref_08_06,Inter_ref_07_06} <= RefFrameOutPadding[15:0]; + + 6'd6 :{Inter_ref_02_07,Inter_ref_01_07,Inter_ref_00_07} <= RefFrameOutPadding[31:8]; + 6'd5 :{Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07} <= RefFrameOutPadding; + 6'd4 :{Inter_ref_08_07,Inter_ref_07_07} <= RefFrameOutPadding[15:0]; + + 6'd3 :{Inter_ref_02_08,Inter_ref_01_08,Inter_ref_00_08} <= RefFrameOutPadding[31:8]; + 6'd2 :{Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_08_08,Inter_ref_07_08} <= RefFrameOutPadding[15:0]; + endcase + endcase + `pos_d,`pos_h,`pos_n: + case (xInt_org_unclip_1to0) + 2'b00: + case (blk4x4_inter_preload_counter) + 6'd9:{Inter_ref_05_00,Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding; + 6'd8:{Inter_ref_05_01,Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding; + 6'd7:{Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding; + 6'd6:{Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding; + 6'd5:{Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding; + 6'd4:{Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding; + 6'd3:{Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding; + 6'd2:{Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding; + 6'd1:{Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding; + endcase + 2'b01: + case (blk4x4_inter_preload_counter) + 6'd18:{Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding[31:8]; + 6'd17:Inter_ref_05_00 <= RefFrameOutPadding[7:0]; + + 6'd16:{Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding[31:8]; + 6'd15:Inter_ref_05_01 <= RefFrameOutPadding[7:0]; + + 6'd14:{Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding[31:8]; + 6'd13:Inter_ref_05_02 <= RefFrameOutPadding[7:0]; + + 6'd12:{Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding[31:8]; + 6'd11:Inter_ref_05_03 <= RefFrameOutPadding[7:0]; + + 6'd10:{Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding[31:8]; + 6'd9 :Inter_ref_05_04 <= RefFrameOutPadding[7:0]; + + 6'd8 :{Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding[31:8]; + 6'd7 :Inter_ref_05_05 <= RefFrameOutPadding[7:0]; + + 6'd6 :{Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding[31:8]; + 6'd5 :Inter_ref_05_06 <= RefFrameOutPadding[7:0]; + + 6'd4 :{Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding[31:8]; + 6'd3 :Inter_ref_05_07 <= RefFrameOutPadding[7:0]; + + 6'd2 :{Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding[31:8]; + 6'd1 :Inter_ref_05_08 <= RefFrameOutPadding[7:0]; + endcase + 2'b10: + case (blk4x4_inter_preload_counter) + 6'd18:{Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding[31:16]; + 6'd17:{Inter_ref_05_00,Inter_ref_04_00} <= RefFrameOutPadding[15:0]; + + 6'd16:{Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding[31:16]; + 6'd15:{Inter_ref_05_01,Inter_ref_04_01} <= RefFrameOutPadding[15:0]; + + 6'd14:{Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding[31:16]; + 6'd13:{Inter_ref_05_02,Inter_ref_04_02} <= RefFrameOutPadding[15:0]; + + 6'd12:{Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding[31:16]; + 6'd11:{Inter_ref_05_03,Inter_ref_04_03} <= RefFrameOutPadding[15:0]; + + 6'd10:{Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding[31:16]; + 6'd9 :{Inter_ref_05_04,Inter_ref_04_04} <= RefFrameOutPadding[15:0]; + + 6'd8 :{Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding[31:16]; + 6'd7 :{Inter_ref_05_05,Inter_ref_04_05} <= RefFrameOutPadding[15:0]; + + 6'd6 :{Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding[31:16]; + 6'd5 :{Inter_ref_05_06,Inter_ref_04_06} <= RefFrameOutPadding[15:0]; + + 6'd4 :{Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding[31:16]; + 6'd3 :{Inter_ref_05_07,Inter_ref_04_07} <= RefFrameOutPadding[15:0]; + + 6'd2 :{Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding[31:16]; + 6'd1 :{Inter_ref_05_08,Inter_ref_04_08} <= RefFrameOutPadding[15:0]; + endcase + 2'b11: + case (blk4x4_inter_preload_counter) + 6'd18:Inter_ref_02_00 <= RefFrameOutPadding[31:24]; + 6'd17:{Inter_ref_05_00,Inter_ref_04_00,Inter_ref_03_00} <= RefFrameOutPadding[23:0]; + + 6'd16:Inter_ref_02_01 <= RefFrameOutPadding[31:24]; + 6'd15:{Inter_ref_05_01,Inter_ref_04_01,Inter_ref_03_01} <= RefFrameOutPadding[23:0]; + + 6'd14:Inter_ref_02_02 <= RefFrameOutPadding[31:24]; + 6'd13:{Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02} <= RefFrameOutPadding[23:0]; + + 6'd12:Inter_ref_02_03 <= RefFrameOutPadding[31:24]; + 6'd11:{Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03} <= RefFrameOutPadding[23:0]; + + 6'd10:Inter_ref_02_04 <= RefFrameOutPadding[31:24]; + 6'd9 :{Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04} <= RefFrameOutPadding[23:0]; + + 6'd8 :Inter_ref_02_05 <= RefFrameOutPadding[31:24]; + 6'd7 :{Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05} <= RefFrameOutPadding[23:0]; + + 6'd6 :Inter_ref_02_06 <= RefFrameOutPadding[31:24]; + 6'd5 :{Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06} <= RefFrameOutPadding[23:0]; + + 6'd4 :Inter_ref_02_07 <= RefFrameOutPadding[31:24]; + 6'd3 :{Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07} <= RefFrameOutPadding[23:0]; + + 6'd2 :Inter_ref_02_08 <= RefFrameOutPadding[31:24]; + 6'd1 :{Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08} <= RefFrameOutPadding[23:0]; + endcase + endcase + `pos_a,`pos_b,`pos_c: + case (xInt_org_unclip_1to0) + 2'b00: + case (blk4x4_inter_preload_counter) + 6'd12:{Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:16]; + 6'd11:{Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding; + 6'd10:{Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02} <= RefFrameOutPadding[23:0]; + + 6'd9 :{Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:16]; + 6'd8 :{Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding; + 6'd7 :{Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03} <= RefFrameOutPadding[23:0]; + + 6'd6 :{Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:16]; + 6'd5 :{Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding; + 6'd4 :{Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04} <= RefFrameOutPadding[23:0]; + + 6'd3 :{Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding[31:16]; + 6'd2 :{Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05} <= RefFrameOutPadding[23:0]; + endcase + 2'b01: + case (blk4x4_inter_preload_counter) + 6'd12:Inter_ref_00_02 <= RefFrameOutPadding[31:24]; + 6'd11:{Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02} <= RefFrameOutPadding; + 6'd10:{Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02} <= RefFrameOutPadding; + + 6'd9 :Inter_ref_00_03 <= RefFrameOutPadding[31:24]; + 6'd8 :{Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03} <= RefFrameOutPadding; + 6'd7 :{Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03} <= RefFrameOutPadding; + + 6'd6 :Inter_ref_00_04 <= RefFrameOutPadding[31:24]; + 6'd5 :{Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04} <= RefFrameOutPadding; + 6'd4 :{Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04} <= RefFrameOutPadding; + + 6'd3 :Inter_ref_00_05 <= RefFrameOutPadding[31:24]; + 6'd2 :{Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05,Inter_ref_01_05} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05} <= RefFrameOutPadding; + endcase + 2'b10: + case (blk4x4_inter_preload_counter) + 6'd12:{Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding; + 6'd11:{Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02} <= RefFrameOutPadding; + 6'd10:Inter_ref_08_02 <= RefFrameOutPadding[7:0]; + + 6'd9 :{Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding; + 6'd8 :{Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03} <= RefFrameOutPadding; + 6'd7 :Inter_ref_08_03 <= RefFrameOutPadding[7:0]; + + 6'd6 :{Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding; + 6'd5 :{Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04} <= RefFrameOutPadding; + 6'd4 :Inter_ref_08_04 <= RefFrameOutPadding[7:0]; + + 6'd3 :{Inter_ref_03_05,Inter_ref_02_05,Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding; + 6'd2 :{Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05} <= RefFrameOutPadding; + 6'd1 :Inter_ref_08_05 <= RefFrameOutPadding[7:0]; + endcase + 2'b11: + case (blk4x4_inter_preload_counter) + 6'd12:{Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:8]; + 6'd11:{Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02} <= RefFrameOutPadding; + 6'd10:{Inter_ref_08_02,Inter_ref_07_02} <= RefFrameOutPadding[15:0]; + + 6'd9 :{Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:8]; + 6'd8 :{Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03} <= RefFrameOutPadding; + 6'd7 :{Inter_ref_08_03,Inter_ref_07_03} <= RefFrameOutPadding[15:0]; + + 6'd6 :{Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:8]; + 6'd5 :{Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04} <= RefFrameOutPadding; + 6'd4 :{Inter_ref_08_04,Inter_ref_07_04} <= RefFrameOutPadding[15:0]; + + 6'd3 :{Inter_ref_02_05,Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding[31:8]; + 6'd2 :{Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05} <= RefFrameOutPadding; + 6'd1 :{Inter_ref_08_05,Inter_ref_07_05} <= RefFrameOutPadding[15:0]; + endcase + endcase + `pos_Int: + case (xInt_org_unclip_1to0) + 2'b00: + case (blk4x4_inter_preload_counter) + 6'd4:{Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding; + 6'd3:{Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding; + 6'd2:{Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding; + 6'd1:{Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding; + endcase + 2'b01: + case (blk4x4_inter_preload_counter) + 6'd8:{Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding[31:8]; + 6'd7:Inter_ref_05_02 <= RefFrameOutPadding[7:0]; + + 6'd6:{Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding[31:8]; + 6'd5:Inter_ref_05_03 <= RefFrameOutPadding[7:0]; + + 6'd4:{Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding[31:8]; + 6'd3:Inter_ref_05_04 <= RefFrameOutPadding[7:0]; + + 6'd2:{Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding[31:8]; + 6'd1:Inter_ref_05_05 <= RefFrameOutPadding[7:0]; + endcase + 2'b10: + case (blk4x4_inter_preload_counter) + 6'd8:{Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding[31:16]; + 6'd7:{Inter_ref_05_02,Inter_ref_04_02} <= RefFrameOutPadding[15:0]; + + 6'd6:{Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding[31:16]; + 6'd5:{Inter_ref_05_03,Inter_ref_04_03} <= RefFrameOutPadding[15:0]; + + 6'd4:{Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding[31:16]; + 6'd3:{Inter_ref_05_04,Inter_ref_04_04} <= RefFrameOutPadding[15:0]; + + 6'd2:{Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding[31:16]; + 6'd1:{Inter_ref_05_05,Inter_ref_04_05} <= RefFrameOutPadding[15:0]; + endcase + 2'b11: + case (blk4x4_inter_preload_counter) + 6'd8:Inter_ref_02_02 <= RefFrameOutPadding[31:24]; + 6'd7:{Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02} <= RefFrameOutPadding[23:0]; + + 6'd6:Inter_ref_02_03 <= RefFrameOutPadding[31:24]; + 6'd5:{Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03} <= RefFrameOutPadding[23:0]; + + 6'd4:Inter_ref_02_04 <= RefFrameOutPadding[31:24]; + 6'd3:{Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04} <= RefFrameOutPadding[23:0]; + + 6'd2:Inter_ref_02_05 <= RefFrameOutPadding[31:24]; + 6'd1:{Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05} <= RefFrameOutPadding[23:0]; + endcase + endcase + `pos_e,`pos_g,`pos_p,`pos_r: + case (xInt_org_unclip_1to0) + 2'b00: + case (blk4x4_inter_preload_counter) + 6'd23:{Inter_ref_05_00,Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding; + 6'd22:Inter_ref_06_00 <= RefFrameOutPadding[7:0]; + 6'd21:{Inter_ref_05_01,Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding; + 6'd20:Inter_ref_06_01 <= RefFrameOutPadding[7:0]; + + 6'd19:{Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:16]; + 6'd18:{Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding; + 6'd17:{Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02} <= RefFrameOutPadding[23:0]; + 6'd16:{Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:16]; + 6'd15:{Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding; + 6'd14:{Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03} <= RefFrameOutPadding[23:0]; + 6'd13:{Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:16]; + 6'd12:{Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding; + 6'd11:{Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04} <= RefFrameOutPadding[23:0]; + 6'd10:{Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding[31:16]; + 6'd9 :{Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05} <= RefFrameOutPadding; + 6'd8 :{Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05} <= RefFrameOutPadding[23:0]; + 6'd7 :{Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding[31:16]; + 6'd6 :{Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06} <= RefFrameOutPadding; + 6'd5 :{Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06} <= RefFrameOutPadding[23:0]; + + 6'd4 :{Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding; + 6'd3 :Inter_ref_06_07 <= RefFrameOutPadding[7:0]; + 6'd2 :{Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding; + 6'd1 :Inter_ref_06_08 <= RefFrameOutPadding[7:0]; + endcase + 2'b01: + case (blk4x4_inter_preload_counter) + 6'd23:{Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding[31:8]; + 6'd22:{Inter_ref_06_00,Inter_ref_05_00} <= RefFrameOutPadding[15:0]; + 6'd21:{Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding[31:8]; + 6'd20:{Inter_ref_06_01,Inter_ref_05_01} <= RefFrameOutPadding[15:0]; + + 6'd19:Inter_ref_00_02 <= RefFrameOutPadding[31:24]; + 6'd18:{Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02} <= RefFrameOutPadding; + 6'd17:{Inter_ref_08_02,Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02} <= RefFrameOutPadding; + 6'd16:Inter_ref_00_03 <= RefFrameOutPadding[31:24]; + 6'd15:{Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03} <= RefFrameOutPadding; + 6'd14:{Inter_ref_08_03,Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03} <= RefFrameOutPadding; + 6'd13:Inter_ref_00_04 <= RefFrameOutPadding[31:24]; + 6'd12:{Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04} <= RefFrameOutPadding; + 6'd11:{Inter_ref_08_04,Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04} <= RefFrameOutPadding; + 6'd10:Inter_ref_00_05 <= RefFrameOutPadding[31:24]; + 6'd9 :{Inter_ref_04_05,Inter_ref_03_05,Inter_ref_02_05,Inter_ref_01_05} <= RefFrameOutPadding; + 6'd8 :{Inter_ref_08_05,Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05} <= RefFrameOutPadding; + 6'd7 :Inter_ref_00_06 <= RefFrameOutPadding[31:24]; + 6'd6 :{Inter_ref_04_06,Inter_ref_03_06,Inter_ref_02_06,Inter_ref_01_06} <= RefFrameOutPadding; + 6'd5 :{Inter_ref_08_06,Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06} <= RefFrameOutPadding; + + 6'd4 :{Inter_ref_04_07,Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding[31:8]; + 6'd3 :{Inter_ref_06_07,Inter_ref_05_07} <= RefFrameOutPadding[15:0]; + 6'd2 :{Inter_ref_04_08,Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding[31:8]; + 6'd1 :{Inter_ref_06_08,Inter_ref_05_08} <= RefFrameOutPadding[15:0]; + endcase + 2'b10: + case (blk4x4_inter_preload_counter) + 6'd23:{Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding[31:16]; + 6'd22:{Inter_ref_06_00,Inter_ref_05_00,Inter_ref_04_00} <= RefFrameOutPadding[23:0]; + 6'd21:{Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding[31:16]; + 6'd20:{Inter_ref_06_01,Inter_ref_05_01,Inter_ref_04_01} <= RefFrameOutPadding[23:0]; + + 6'd19:{Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding; + 6'd18:{Inter_ref_07_02,Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02} <= RefFrameOutPadding; + 6'd17:Inter_ref_08_02 <= RefFrameOutPadding[7:0]; + 6'd16:{Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding; + 6'd15:{Inter_ref_07_03,Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03} <= RefFrameOutPadding; + 6'd14:Inter_ref_08_03 <= RefFrameOutPadding[7:0]; + 6'd13:{Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding; + 6'd12:{Inter_ref_07_04,Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04} <= RefFrameOutPadding; + 6'd11:Inter_ref_08_04 <= RefFrameOutPadding[7:0]; + 6'd10:{Inter_ref_03_05,Inter_ref_02_05,Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding; + 6'd9 :{Inter_ref_07_05,Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05} <= RefFrameOutPadding; + 6'd8 :Inter_ref_08_05 <= RefFrameOutPadding[7:0]; + 6'd7 :{Inter_ref_03_06,Inter_ref_02_06,Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding; + 6'd6 :{Inter_ref_07_06,Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06} <= RefFrameOutPadding; + 6'd5 :Inter_ref_08_06 <= RefFrameOutPadding[7:0]; + + 6'd4 :{Inter_ref_03_07,Inter_ref_02_07} <= RefFrameOutPadding[31:16]; + 6'd3 :{Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07} <= RefFrameOutPadding[23:0]; + 6'd2 :{Inter_ref_03_08,Inter_ref_02_08} <= RefFrameOutPadding[31:16]; + 6'd1 :{Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08} <= RefFrameOutPadding[23:0]; + endcase + 2'b11: + case (blk4x4_inter_preload_counter) + 6'd23:Inter_ref_02_00 <= RefFrameOutPadding[31:24]; + 6'd22:{Inter_ref_06_00,Inter_ref_05_00,Inter_ref_04_00,Inter_ref_03_00} <= RefFrameOutPadding; + 6'd21:Inter_ref_02_01 <= RefFrameOutPadding[31:24]; + 6'd20:{Inter_ref_06_01,Inter_ref_05_01,Inter_ref_04_01,Inter_ref_03_01} <= RefFrameOutPadding; + + 6'd19:{Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:8]; + 6'd18:{Inter_ref_06_02,Inter_ref_05_02,Inter_ref_04_02,Inter_ref_03_02} <= RefFrameOutPadding; + 6'd17:{Inter_ref_08_02,Inter_ref_07_02} <= RefFrameOutPadding[15:0]; + 6'd16:{Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:8]; + 6'd15:{Inter_ref_06_03,Inter_ref_05_03,Inter_ref_04_03,Inter_ref_03_03} <= RefFrameOutPadding; + 6'd14:{Inter_ref_08_03,Inter_ref_07_03} <= RefFrameOutPadding[15:0]; + 6'd13:{Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:8]; + 6'd12:{Inter_ref_06_04,Inter_ref_05_04,Inter_ref_04_04,Inter_ref_03_04} <= RefFrameOutPadding; + 6'd11:{Inter_ref_08_04,Inter_ref_07_04} <= RefFrameOutPadding[15:0]; + 6'd10:{Inter_ref_02_05,Inter_ref_01_05,Inter_ref_00_05} <= RefFrameOutPadding[31:8]; + 6'd9 :{Inter_ref_06_05,Inter_ref_05_05,Inter_ref_04_05,Inter_ref_03_05} <= RefFrameOutPadding; + 6'd8 :{Inter_ref_08_05,Inter_ref_07_05} <= RefFrameOutPadding[15:0]; + 6'd7 :{Inter_ref_02_06,Inter_ref_01_06,Inter_ref_00_06} <= RefFrameOutPadding[31:8]; + 6'd6 :{Inter_ref_06_06,Inter_ref_05_06,Inter_ref_04_06,Inter_ref_03_06} <= RefFrameOutPadding; + 6'd5 :{Inter_ref_08_06,Inter_ref_07_06} <= RefFrameOutPadding[15:0]; + + 6'd4 :Inter_ref_02_07 <= RefFrameOutPadding[31:24]; + 6'd3 :{Inter_ref_06_07,Inter_ref_05_07,Inter_ref_04_07,Inter_ref_03_07} <= RefFrameOutPadding; + 6'd2 :Inter_ref_02_08 <= RefFrameOutPadding[31:24]; + 6'd1 :{Inter_ref_06_08,Inter_ref_05_08,Inter_ref_04_08,Inter_ref_03_08} <= RefFrameOutPadding; + endcase + endcase + endcase + endcase + else if (IsInterChroma && blk4x4_inter_preload_counter != 0) + begin + if (mv_below8x8_curr == 1'b0) + begin + if (xFracC == 0 && yFracC == 0) // 8 or 4 cycles + case (xInt_org_unclip_1to0) + 2'b00: + case (blk4x4_inter_preload_counter) + 6'd4:{Inter_ref_03_00,Inter_ref_02_00,Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding; + 6'd3:{Inter_ref_03_01,Inter_ref_02_01,Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding; + 6'd2:{Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding; + 6'd1:{Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding; + endcase + 2'b01: + case (blk4x4_inter_preload_counter) + 6'd8:{Inter_ref_02_00,Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[31:8]; + 6'd7:Inter_ref_03_00 <= RefFrameOutPadding[7:0]; + 6'd6:{Inter_ref_02_01,Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[31:8]; + 6'd5:Inter_ref_03_01 <= RefFrameOutPadding[7:0]; + 6'd4:{Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:8]; + 6'd3:Inter_ref_03_02 <= RefFrameOutPadding[7:0]; + 6'd2:{Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:8]; + 6'd1:Inter_ref_03_03 <= RefFrameOutPadding[7:0]; + endcase + 2'b10: + case (blk4x4_inter_preload_counter) + 6'd8:{Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[31:16]; + 6'd7:{Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding[15:0]; + 6'd6:{Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[31:16]; + 6'd5:{Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding[15:0]; + 6'd4:{Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:16]; + 6'd3:{Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding[15:0]; + 6'd2:{Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:16]; + 6'd1:{Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding[15:0]; + endcase + 2'b11: + case (blk4x4_inter_preload_counter) + 6'd8:Inter_ref_00_00 <= RefFrameOutPadding[31:24]; + 6'd7:{Inter_ref_03_00,Inter_ref_02_00,Inter_ref_01_00} <= RefFrameOutPadding[23:0]; + 6'd6:Inter_ref_00_01 <= RefFrameOutPadding[31:24]; + 6'd5:{Inter_ref_03_01,Inter_ref_02_01,Inter_ref_01_01} <= RefFrameOutPadding[23:0]; + 6'd4:Inter_ref_00_02 <= RefFrameOutPadding[31:24]; + 6'd3:{Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02} <= RefFrameOutPadding[23:0]; + 6'd2:Inter_ref_00_03 <= RefFrameOutPadding[31:24]; + 6'd1:{Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03} <= RefFrameOutPadding[23:0]; + endcase + endcase + else + case (xInt_org_unclip_1to0) + 2'b00: + case(blk4x4_inter_preload_counter) + 6'd10:{Inter_ref_03_00,Inter_ref_02_00,Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding; + 6'd9 :Inter_ref_04_00 <= RefFrameOutPadding[7:0]; + 6'd8 :{Inter_ref_03_01,Inter_ref_02_01,Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding; + 6'd7 :Inter_ref_04_01 <= RefFrameOutPadding[7:0]; + 6'd6 :{Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding; + 6'd5 :Inter_ref_04_02 <= RefFrameOutPadding[7:0]; + 6'd4 :{Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding; + 6'd3 :Inter_ref_04_03 <= RefFrameOutPadding[7:0]; + 6'd2 :{Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding; + 6'd1 :Inter_ref_04_04 <= RefFrameOutPadding[7:0]; + endcase + 2'b01: + case (blk4x4_inter_preload_counter) + 6'd10:{Inter_ref_02_00,Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[31:8]; + 6'd9 :{Inter_ref_04_00,Inter_ref_03_00} <= RefFrameOutPadding[15:0]; + 6'd8 :{Inter_ref_02_01,Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[31:8]; + 6'd7 :{Inter_ref_04_01,Inter_ref_03_01} <= RefFrameOutPadding[15:0]; + 6'd6 :{Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:8]; + 6'd5 :{Inter_ref_04_02,Inter_ref_03_02} <= RefFrameOutPadding[15:0]; + 6'd4 :{Inter_ref_02_03,Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:8]; + 6'd3 :{Inter_ref_04_03,Inter_ref_03_03} <= RefFrameOutPadding[15:0]; + 6'd2 :{Inter_ref_02_04,Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:8]; + 6'd1 :{Inter_ref_04_04,Inter_ref_03_04} <= RefFrameOutPadding[15:0]; + endcase + 2'b10: + case (blk4x4_inter_preload_counter) + 6'd10:{Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[31:16]; + 6'd9 :{Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00} <= RefFrameOutPadding[23:0]; + 6'd8 :{Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[31:16]; + 6'd7 :{Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01} <= RefFrameOutPadding[23:0]; + 6'd6 :{Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:16]; + 6'd5 :{Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02} <= RefFrameOutPadding[23:0]; + 6'd4 :{Inter_ref_01_03,Inter_ref_00_03} <= RefFrameOutPadding[31:16]; + 6'd3 :{Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03} <= RefFrameOutPadding[23:0]; + 6'd2 :{Inter_ref_01_04,Inter_ref_00_04} <= RefFrameOutPadding[31:16]; + 6'd1 :{Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04} <= RefFrameOutPadding[23:0]; + endcase + 2'b11: + case (blk4x4_inter_preload_counter) + 6'd10:Inter_ref_00_00 <= RefFrameOutPadding[31:24]; + 6'd9 :{Inter_ref_04_00,Inter_ref_03_00,Inter_ref_02_00,Inter_ref_01_00} <= RefFrameOutPadding; + 6'd8 :Inter_ref_00_01 <= RefFrameOutPadding[31:24]; + 6'd7 :{Inter_ref_04_01,Inter_ref_03_01,Inter_ref_02_01,Inter_ref_01_01} <= RefFrameOutPadding; + 6'd6 :Inter_ref_00_02 <= RefFrameOutPadding[31:24]; + 6'd5 :{Inter_ref_04_02,Inter_ref_03_02,Inter_ref_02_02,Inter_ref_01_02} <= RefFrameOutPadding; + 6'd4 :Inter_ref_00_03 <= RefFrameOutPadding[31:24]; + 6'd3 :{Inter_ref_04_03,Inter_ref_03_03,Inter_ref_02_03,Inter_ref_01_03} <= RefFrameOutPadding; + 6'd2 :Inter_ref_00_04 <= RefFrameOutPadding[31:24]; + 6'd1 :{Inter_ref_04_04,Inter_ref_03_04,Inter_ref_02_04,Inter_ref_01_04} <= RefFrameOutPadding; + endcase + endcase + end + else // mv_below8x8_curr == 1'b1 + begin + if (xFracC == 0 && yFracC == 0) // 4 or 2 cycles + case (xInt_org_unclip_1to0) + 2'b00: + case (blk4x4_inter_preload_counter) + 6'd2:{Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[15:0]; + 6'd1:{Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[15:0]; + endcase + 2'b01: + case (blk4x4_inter_preload_counter) + 6'd2:{Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[23:8]; + 6'd1:{Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[23:8]; + endcase + 2'b10: + case (blk4x4_inter_preload_counter) + 6'd2:{Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[31:16]; + 6'd1:{Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[31:16]; + endcase + 2'b11: + case (blk4x4_inter_preload_counter) + 6'd4:Inter_ref_00_00 <= RefFrameOutPadding[31:24]; + 6'd3:Inter_ref_01_00 <= RefFrameOutPadding[7:0]; + 6'd2:Inter_ref_00_01 <= RefFrameOutPadding[31:24]; + 6'd1:Inter_ref_01_01 <= RefFrameOutPadding[7:0]; + endcase + endcase + else // 6 or 3 cycles + case (xInt_org_unclip_1to0) + 2'b00: + case (blk4x4_inter_preload_counter) + 6'd3:{Inter_ref_02_00,Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[23:0]; + 6'd2:{Inter_ref_02_01,Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[23:0]; + 6'd1:{Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[23:0]; + endcase + 2'b01: + case (blk4x4_inter_preload_counter) + 6'd3:{Inter_ref_02_00,Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[31:8]; + 6'd2:{Inter_ref_02_01,Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[31:8]; + 6'd1:{Inter_ref_02_02,Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:8]; + endcase + 2'b10: + case (blk4x4_inter_preload_counter) + 6'd6:{Inter_ref_01_00,Inter_ref_00_00} <= RefFrameOutPadding[31:16]; + 6'd5:Inter_ref_02_00 <= RefFrameOutPadding[7:0]; + 6'd4:{Inter_ref_01_01,Inter_ref_00_01} <= RefFrameOutPadding[31:16]; + 6'd3:Inter_ref_02_01 <= RefFrameOutPadding[7:0]; + 6'd2:{Inter_ref_01_02,Inter_ref_00_02} <= RefFrameOutPadding[31:16]; + 6'd1:Inter_ref_02_02 <= RefFrameOutPadding[7:0]; + endcase + 2'b11: + case (blk4x4_inter_preload_counter) + 6'd6:Inter_ref_00_00 <= RefFrameOutPadding[31:24]; + 6'd5:{Inter_ref_02_00,Inter_ref_01_00} <= RefFrameOutPadding[15:0]; + 6'd4:Inter_ref_00_01 <= RefFrameOutPadding[31:24]; + 6'd3:{Inter_ref_02_01,Inter_ref_01_01} <= RefFrameOutPadding[15:0]; + 6'd2:Inter_ref_00_02 <= RefFrameOutPadding[31:24]; + 6'd1:{Inter_ref_02_02,Inter_ref_01_02} <= RefFrameOutPadding[15:0]; + endcase + endcase + end + end + +endmodule + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/Inter_pred_sliding_window.v b/demo_chip_rtl/rtl/nova/trunk/src/Inter_pred_sliding_window.v new file mode 100644 index 0000000..9266d72 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/Inter_pred_sliding_window.v @@ -0,0 +1,2227 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : Inter_pred_sliding_window.v +// Generated : Oct 25, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Prepare the appropriate registers for Inter prediction (luma & chroma) +// 1)Luma:horizontal window 6x9,vertical window 1x9 +// 2)Chroma:window 2x2 +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module Inter_pred_sliding_window (IsInterLuma,IsInterChroma,Is_InterChromaCopy,mv_below8x8_curr, + pos_FracL,blk4x4_rec_counter_1to0,blk4x4_inter_calculate_counter, + Inter_ref_00_00,Inter_ref_01_00,Inter_ref_02_00,Inter_ref_03_00,Inter_ref_04_00,Inter_ref_05_00, + Inter_ref_06_00,Inter_ref_07_00,Inter_ref_08_00,Inter_ref_09_00,Inter_ref_10_00,Inter_ref_11_00,Inter_ref_12_00, + Inter_ref_00_01,Inter_ref_01_01,Inter_ref_02_01,Inter_ref_03_01,Inter_ref_04_01,Inter_ref_05_01, + Inter_ref_06_01,Inter_ref_07_01,Inter_ref_08_01,Inter_ref_09_01,Inter_ref_10_01,Inter_ref_11_01,Inter_ref_12_01, + Inter_ref_00_02,Inter_ref_01_02,Inter_ref_02_02,Inter_ref_03_02,Inter_ref_04_02,Inter_ref_05_02, + Inter_ref_06_02,Inter_ref_07_02,Inter_ref_08_02,Inter_ref_09_02,Inter_ref_10_02,Inter_ref_11_02,Inter_ref_12_02, + Inter_ref_00_03,Inter_ref_01_03,Inter_ref_02_03,Inter_ref_03_03,Inter_ref_04_03,Inter_ref_05_03, + Inter_ref_06_03,Inter_ref_07_03,Inter_ref_08_03,Inter_ref_09_03,Inter_ref_10_03,Inter_ref_11_03,Inter_ref_12_03, + Inter_ref_00_04,Inter_ref_01_04,Inter_ref_02_04,Inter_ref_03_04,Inter_ref_04_04,Inter_ref_05_04, + Inter_ref_06_04,Inter_ref_07_04,Inter_ref_08_04,Inter_ref_09_04,Inter_ref_10_04,Inter_ref_11_04,Inter_ref_12_04, + Inter_ref_00_05,Inter_ref_01_05,Inter_ref_02_05,Inter_ref_03_05,Inter_ref_04_05,Inter_ref_05_05, + Inter_ref_06_05,Inter_ref_07_05,Inter_ref_08_05,Inter_ref_09_05,Inter_ref_10_05,Inter_ref_11_05,Inter_ref_12_05, + Inter_ref_00_06,Inter_ref_01_06,Inter_ref_02_06,Inter_ref_03_06,Inter_ref_04_06,Inter_ref_05_06, + Inter_ref_06_06,Inter_ref_07_06,Inter_ref_08_06,Inter_ref_09_06,Inter_ref_10_06,Inter_ref_11_06,Inter_ref_12_06, + Inter_ref_00_07,Inter_ref_01_07,Inter_ref_02_07,Inter_ref_03_07,Inter_ref_04_07,Inter_ref_05_07, + Inter_ref_06_07,Inter_ref_07_07,Inter_ref_08_07,Inter_ref_09_07,Inter_ref_10_07,Inter_ref_11_07,Inter_ref_12_07, + Inter_ref_00_08,Inter_ref_01_08,Inter_ref_02_08,Inter_ref_03_08,Inter_ref_04_08,Inter_ref_05_08, + Inter_ref_06_08,Inter_ref_07_08,Inter_ref_08_08,Inter_ref_09_08,Inter_ref_10_08,Inter_ref_11_08,Inter_ref_12_08, + Inter_ref_00_09,Inter_ref_01_09,Inter_ref_02_09,Inter_ref_03_09,Inter_ref_04_09,Inter_ref_05_09, + Inter_ref_06_09,Inter_ref_07_09,Inter_ref_08_09,Inter_ref_09_09,Inter_ref_10_09,Inter_ref_11_09,Inter_ref_12_09, + Inter_ref_00_10,Inter_ref_01_10,Inter_ref_02_10,Inter_ref_03_10,Inter_ref_04_10,Inter_ref_05_10, + Inter_ref_06_10,Inter_ref_07_10,Inter_ref_08_10,Inter_ref_09_10,Inter_ref_10_10,Inter_ref_11_10,Inter_ref_12_10, + Inter_ref_00_11,Inter_ref_01_11,Inter_ref_02_11,Inter_ref_03_11,Inter_ref_04_11,Inter_ref_05_11, + Inter_ref_06_11,Inter_ref_07_11,Inter_ref_08_11,Inter_ref_09_11,Inter_ref_10_11,Inter_ref_11_11,Inter_ref_12_11, + Inter_ref_00_12,Inter_ref_01_12,Inter_ref_02_12,Inter_ref_03_12,Inter_ref_04_12,Inter_ref_05_12, + Inter_ref_06_12,Inter_ref_07_12,Inter_ref_08_12,Inter_ref_09_12,Inter_ref_10_12,Inter_ref_11_12,Inter_ref_12_12, + + Inter_pix_copy0,Inter_pix_copy1,Inter_pix_copy2,Inter_pix_copy3, + Inter_H_window_0_0,Inter_H_window_1_0,Inter_H_window_2_0,Inter_H_window_3_0,Inter_H_window_4_0,Inter_H_window_5_0, + Inter_H_window_0_1,Inter_H_window_1_1,Inter_H_window_2_1,Inter_H_window_3_1,Inter_H_window_4_1,Inter_H_window_5_1, + Inter_H_window_0_2,Inter_H_window_1_2,Inter_H_window_2_2,Inter_H_window_3_2,Inter_H_window_4_2,Inter_H_window_5_2, + Inter_H_window_0_3,Inter_H_window_1_3,Inter_H_window_2_3,Inter_H_window_3_3,Inter_H_window_4_3,Inter_H_window_5_3, + Inter_H_window_0_4,Inter_H_window_1_4,Inter_H_window_2_4,Inter_H_window_3_4,Inter_H_window_4_4,Inter_H_window_5_4, + Inter_H_window_0_5,Inter_H_window_1_5,Inter_H_window_2_5,Inter_H_window_3_5,Inter_H_window_4_5,Inter_H_window_5_5, + Inter_H_window_0_6,Inter_H_window_1_6,Inter_H_window_2_6,Inter_H_window_3_6,Inter_H_window_4_6,Inter_H_window_5_6, + Inter_H_window_0_7,Inter_H_window_1_7,Inter_H_window_2_7,Inter_H_window_3_7,Inter_H_window_4_7,Inter_H_window_5_7, + Inter_H_window_0_8,Inter_H_window_1_8,Inter_H_window_2_8,Inter_H_window_3_8,Inter_H_window_4_8,Inter_H_window_5_8, + Inter_V_window_0,Inter_V_window_1,Inter_V_window_2,Inter_V_window_3,Inter_V_window_4, + Inter_V_window_5,Inter_V_window_6,Inter_V_window_7,Inter_V_window_8, + Inter_C_window_0_0,Inter_C_window_1_0,Inter_C_window_2_0, + Inter_C_window_0_1,Inter_C_window_1_1,Inter_C_window_2_1, + Inter_C_window_0_2,Inter_C_window_1_2,Inter_C_window_2_2, + Inter_bi_window_0,Inter_bi_window_1,Inter_bi_window_2,Inter_bi_window_3); + input IsInterLuma; + input IsInterChroma; + input Is_InterChromaCopy; + input mv_below8x8_curr; + input [3:0] pos_FracL; + input [1:0] blk4x4_rec_counter_1to0; + input [3:0] blk4x4_inter_calculate_counter; + + input [7:0] Inter_ref_00_00,Inter_ref_01_00,Inter_ref_02_00,Inter_ref_03_00,Inter_ref_04_00,Inter_ref_05_00; + input [7:0] Inter_ref_06_00,Inter_ref_07_00,Inter_ref_08_00,Inter_ref_09_00,Inter_ref_10_00,Inter_ref_11_00,Inter_ref_12_00; + input [7:0] Inter_ref_00_01,Inter_ref_01_01,Inter_ref_02_01,Inter_ref_03_01,Inter_ref_04_01,Inter_ref_05_01; + input [7:0] Inter_ref_06_01,Inter_ref_07_01,Inter_ref_08_01,Inter_ref_09_01,Inter_ref_10_01,Inter_ref_11_01,Inter_ref_12_01; + input [7:0] Inter_ref_00_02,Inter_ref_01_02,Inter_ref_02_02,Inter_ref_03_02,Inter_ref_04_02,Inter_ref_05_02; + input [7:0] Inter_ref_06_02,Inter_ref_07_02,Inter_ref_08_02,Inter_ref_09_02,Inter_ref_10_02,Inter_ref_11_02,Inter_ref_12_02; + input [7:0] Inter_ref_00_03,Inter_ref_01_03,Inter_ref_02_03,Inter_ref_03_03,Inter_ref_04_03,Inter_ref_05_03; + input [7:0] Inter_ref_06_03,Inter_ref_07_03,Inter_ref_08_03,Inter_ref_09_03,Inter_ref_10_03,Inter_ref_11_03,Inter_ref_12_03; + input [7:0] Inter_ref_00_04,Inter_ref_01_04,Inter_ref_02_04,Inter_ref_03_04,Inter_ref_04_04,Inter_ref_05_04; + input [7:0] Inter_ref_06_04,Inter_ref_07_04,Inter_ref_08_04,Inter_ref_09_04,Inter_ref_10_04,Inter_ref_11_04,Inter_ref_12_04; + input [7:0] Inter_ref_00_05,Inter_ref_01_05,Inter_ref_02_05,Inter_ref_03_05,Inter_ref_04_05,Inter_ref_05_05; + input [7:0] Inter_ref_06_05,Inter_ref_07_05,Inter_ref_08_05,Inter_ref_09_05,Inter_ref_10_05,Inter_ref_11_05,Inter_ref_12_05; + input [7:0] Inter_ref_00_06,Inter_ref_01_06,Inter_ref_02_06,Inter_ref_03_06,Inter_ref_04_06,Inter_ref_05_06; + input [7:0] Inter_ref_06_06,Inter_ref_07_06,Inter_ref_08_06,Inter_ref_09_06,Inter_ref_10_06,Inter_ref_11_06,Inter_ref_12_06; + input [7:0] Inter_ref_00_07,Inter_ref_01_07,Inter_ref_02_07,Inter_ref_03_07,Inter_ref_04_07,Inter_ref_05_07; + input [7:0] Inter_ref_06_07,Inter_ref_07_07,Inter_ref_08_07,Inter_ref_09_07,Inter_ref_10_07,Inter_ref_11_07,Inter_ref_12_07; + input [7:0] Inter_ref_00_08,Inter_ref_01_08,Inter_ref_02_08,Inter_ref_03_08,Inter_ref_04_08,Inter_ref_05_08; + input [7:0] Inter_ref_06_08,Inter_ref_07_08,Inter_ref_08_08,Inter_ref_09_08,Inter_ref_10_08,Inter_ref_11_08,Inter_ref_12_08; + input [7:0] Inter_ref_00_09,Inter_ref_01_09,Inter_ref_02_09,Inter_ref_03_09,Inter_ref_04_09,Inter_ref_05_09; + input [7:0] Inter_ref_06_09,Inter_ref_07_09,Inter_ref_08_09,Inter_ref_09_09,Inter_ref_10_09,Inter_ref_11_09,Inter_ref_12_09; + input [7:0] Inter_ref_00_10,Inter_ref_01_10,Inter_ref_02_10,Inter_ref_03_10,Inter_ref_04_10,Inter_ref_05_10; + input [7:0] Inter_ref_06_10,Inter_ref_07_10,Inter_ref_08_10,Inter_ref_09_10,Inter_ref_10_10,Inter_ref_11_10,Inter_ref_12_10; + input [7:0] Inter_ref_00_11,Inter_ref_01_11,Inter_ref_02_11,Inter_ref_03_11,Inter_ref_04_11,Inter_ref_05_11; + input [7:0] Inter_ref_06_11,Inter_ref_07_11,Inter_ref_08_11,Inter_ref_09_11,Inter_ref_10_11,Inter_ref_11_11,Inter_ref_12_11; + input [7:0] Inter_ref_00_12,Inter_ref_01_12,Inter_ref_02_12,Inter_ref_03_12,Inter_ref_04_12,Inter_ref_05_12; + input [7:0] Inter_ref_06_12,Inter_ref_07_12,Inter_ref_08_12,Inter_ref_09_12,Inter_ref_10_12,Inter_ref_11_12,Inter_ref_12_12; + + output [7:0] Inter_pix_copy0,Inter_pix_copy1,Inter_pix_copy2,Inter_pix_copy3; + output [7:0] Inter_H_window_0_0,Inter_H_window_1_0,Inter_H_window_2_0,Inter_H_window_3_0,Inter_H_window_4_0,Inter_H_window_5_0; + output [7:0] Inter_H_window_0_1,Inter_H_window_1_1,Inter_H_window_2_1,Inter_H_window_3_1,Inter_H_window_4_1,Inter_H_window_5_1; + output [7:0] Inter_H_window_0_2,Inter_H_window_1_2,Inter_H_window_2_2,Inter_H_window_3_2,Inter_H_window_4_2,Inter_H_window_5_2; + output [7:0] Inter_H_window_0_3,Inter_H_window_1_3,Inter_H_window_2_3,Inter_H_window_3_3,Inter_H_window_4_3,Inter_H_window_5_3; + output [7:0] Inter_H_window_0_4,Inter_H_window_1_4,Inter_H_window_2_4,Inter_H_window_3_4,Inter_H_window_4_4,Inter_H_window_5_4; + output [7:0] Inter_H_window_0_5,Inter_H_window_1_5,Inter_H_window_2_5,Inter_H_window_3_5,Inter_H_window_4_5,Inter_H_window_5_5; + output [7:0] Inter_H_window_0_6,Inter_H_window_1_6,Inter_H_window_2_6,Inter_H_window_3_6,Inter_H_window_4_6,Inter_H_window_5_6; + output [7:0] Inter_H_window_0_7,Inter_H_window_1_7,Inter_H_window_2_7,Inter_H_window_3_7,Inter_H_window_4_7,Inter_H_window_5_7; + output [7:0] Inter_H_window_0_8,Inter_H_window_1_8,Inter_H_window_2_8,Inter_H_window_3_8,Inter_H_window_4_8,Inter_H_window_5_8; + output [7:0] Inter_V_window_0,Inter_V_window_1,Inter_V_window_2,Inter_V_window_3,Inter_V_window_4; + output [7:0] Inter_V_window_5,Inter_V_window_6,Inter_V_window_7,Inter_V_window_8; + output [7:0] Inter_C_window_0_0,Inter_C_window_1_0,Inter_C_window_2_0; + output [7:0] Inter_C_window_0_1,Inter_C_window_1_1,Inter_C_window_2_1; + output [7:0] Inter_C_window_0_2,Inter_C_window_1_2,Inter_C_window_2_2; + output [7:0] Inter_bi_window_0,Inter_bi_window_1,Inter_bi_window_2,Inter_bi_window_3; + + reg [7:0] Inter_pix_copy0,Inter_pix_copy1,Inter_pix_copy2,Inter_pix_copy3; + reg [7:0] Inter_H_window_0_0,Inter_H_window_1_0,Inter_H_window_2_0,Inter_H_window_3_0,Inter_H_window_4_0,Inter_H_window_5_0; + reg [7:0] Inter_H_window_0_1,Inter_H_window_1_1,Inter_H_window_2_1,Inter_H_window_3_1,Inter_H_window_4_1,Inter_H_window_5_1; + reg [7:0] Inter_H_window_0_2,Inter_H_window_1_2,Inter_H_window_2_2,Inter_H_window_3_2,Inter_H_window_4_2,Inter_H_window_5_2; + reg [7:0] Inter_H_window_0_3,Inter_H_window_1_3,Inter_H_window_2_3,Inter_H_window_3_3,Inter_H_window_4_3,Inter_H_window_5_3; + reg [7:0] Inter_H_window_0_4,Inter_H_window_1_4,Inter_H_window_2_4,Inter_H_window_3_4,Inter_H_window_4_4,Inter_H_window_5_4; + reg [7:0] Inter_H_window_0_5,Inter_H_window_1_5,Inter_H_window_2_5,Inter_H_window_3_5,Inter_H_window_4_5,Inter_H_window_5_5; + reg [7:0] Inter_H_window_0_6,Inter_H_window_1_6,Inter_H_window_2_6,Inter_H_window_3_6,Inter_H_window_4_6,Inter_H_window_5_6; + reg [7:0] Inter_H_window_0_7,Inter_H_window_1_7,Inter_H_window_2_7,Inter_H_window_3_7,Inter_H_window_4_7,Inter_H_window_5_7; + reg [7:0] Inter_H_window_0_8,Inter_H_window_1_8,Inter_H_window_2_8,Inter_H_window_3_8,Inter_H_window_4_8,Inter_H_window_5_8; + reg [7:0] Inter_V_window_0,Inter_V_window_1,Inter_V_window_2,Inter_V_window_3,Inter_V_window_4; + reg [7:0] Inter_V_window_5,Inter_V_window_6,Inter_V_window_7,Inter_V_window_8; + reg [7:0] Inter_C_window_0_0,Inter_C_window_1_0,Inter_C_window_2_0; + reg [7:0] Inter_C_window_0_1,Inter_C_window_1_1,Inter_C_window_2_1; + reg [7:0] Inter_C_window_0_2,Inter_C_window_1_2,Inter_C_window_2_2; + reg [7:0] Inter_bi_window_0,Inter_bi_window_1,Inter_bi_window_2,Inter_bi_window_3; + + parameter pos_Int = 4'b0000; + parameter pos_a = 4'b0100; + parameter pos_b = 4'b1000; + parameter pos_c = 4'b1100; + parameter pos_d = 4'b0001; + parameter pos_e = 4'b0101; + parameter pos_f = 4'b1001; + parameter pos_g = 4'b1101; + parameter pos_h = 4'b0010; + parameter pos_i = 4'b0110; + parameter pos_j = 4'b1010; + parameter pos_k = 4'b1110; + parameter pos_n = 4'b0011; + parameter pos_p = 4'b0111; + parameter pos_q = 4'b1011; + parameter pos_r = 4'b1111; + + //------------------------------- + //sliding window control + //------------------------------- + wire Is_blk4x4_0;//When inter 8x8(or above) predicted: top-left blk4x4 + //When inter 4x4 predicted: each blk4x4 + wire Is_blk4x4_1; + wire Is_blk4x4_2; + wire Is_blk4x4_3; + assign Is_blk4x4_0 = (IsInterLuma && (mv_below8x8_curr || (!mv_below8x8_curr && + blk4x4_rec_counter_1to0 == 2'b00))); //top-left + assign Is_blk4x4_1 = (IsInterLuma && (!mv_below8x8_curr && blk4x4_rec_counter_1to0 == 2'b01)); //top-right + assign Is_blk4x4_2 = (IsInterLuma && (!mv_below8x8_curr && blk4x4_rec_counter_1to0 == 2'b10)); //bottom-left + assign Is_blk4x4_3 = (IsInterLuma && (!mv_below8x8_curr && blk4x4_rec_counter_1to0 == 2'b11)); //bottom-right + + //For both luma & chroma,if current pixel is to be directly copied instead of inter calculated, + //the sliding windows output Inter_pix_copy0 ~ 3 is the inter prediction output + always @ (IsInterLuma or pos_FracL or blk4x4_inter_calculate_counter + or Is_blk4x4_0 or Is_blk4x4_1 or Is_blk4x4_2 or Is_blk4x4_3 + or Is_InterChromaCopy or mv_below8x8_curr + or Inter_ref_00_00 or Inter_ref_01_00 or Inter_ref_02_00 or Inter_ref_03_00 + or Inter_ref_00_01 or Inter_ref_01_01 or Inter_ref_02_01 or Inter_ref_03_01 + or Inter_ref_00_02 or Inter_ref_01_02 or Inter_ref_02_02 or Inter_ref_03_02 + or Inter_ref_04_02 or Inter_ref_05_02 or Inter_ref_06_02 or Inter_ref_07_02 + or Inter_ref_08_02 or Inter_ref_09_02 or Inter_ref_00_03 or Inter_ref_01_03 + or Inter_ref_02_03 or Inter_ref_03_03 or Inter_ref_04_03 or Inter_ref_05_03 + or Inter_ref_06_03 or Inter_ref_07_03 or Inter_ref_08_03 or Inter_ref_09_03 + or Inter_ref_02_04 or Inter_ref_03_04 or Inter_ref_04_04 or Inter_ref_05_04 + or Inter_ref_06_04 or Inter_ref_07_04 or Inter_ref_08_04 or Inter_ref_09_04 + or Inter_ref_02_05 or Inter_ref_03_05 or Inter_ref_04_05 or Inter_ref_05_05 + or Inter_ref_06_05 or Inter_ref_07_05 or Inter_ref_08_05 or Inter_ref_09_05 + or Inter_ref_02_06 or Inter_ref_03_06 or Inter_ref_04_06 or Inter_ref_05_06 + or Inter_ref_06_06 or Inter_ref_07_06 or Inter_ref_08_06 or Inter_ref_09_06 + or Inter_ref_02_07 or Inter_ref_03_07 or Inter_ref_04_07 or Inter_ref_05_07 + or Inter_ref_06_07 or Inter_ref_07_07 or Inter_ref_08_07 or Inter_ref_09_07 + or Inter_ref_02_08 or Inter_ref_03_08 or Inter_ref_04_08 or Inter_ref_05_08 + or Inter_ref_06_08 or Inter_ref_07_08 or Inter_ref_08_08 or Inter_ref_09_08 + or Inter_ref_02_09 or Inter_ref_03_09 or Inter_ref_04_09 or Inter_ref_05_09 + or Inter_ref_06_09 or Inter_ref_07_09 or Inter_ref_08_09 or Inter_ref_09_09) + if (IsInterLuma && pos_FracL == `pos_Int) + case ({Is_blk4x4_0,Is_blk4x4_1,Is_blk4x4_2,Is_blk4x4_3}) + 4'b1000: + case (blk4x4_inter_calculate_counter) + 4'd4:begin Inter_pix_copy0 <= Inter_ref_02_02; Inter_pix_copy1 <= Inter_ref_02_03; + Inter_pix_copy2 <= Inter_ref_02_04; Inter_pix_copy3 <= Inter_ref_02_05;end + 4'd3:begin Inter_pix_copy0 <= Inter_ref_03_02; Inter_pix_copy1 <= Inter_ref_03_03; + Inter_pix_copy2 <= Inter_ref_03_04; Inter_pix_copy3 <= Inter_ref_03_05;end + 4'd2:begin Inter_pix_copy0 <= Inter_ref_04_02; Inter_pix_copy1 <= Inter_ref_04_03; + Inter_pix_copy2 <= Inter_ref_04_04; Inter_pix_copy3 <= Inter_ref_04_05;end + 4'd1:begin Inter_pix_copy0 <= Inter_ref_05_02; Inter_pix_copy1 <= Inter_ref_05_03; + Inter_pix_copy2 <= Inter_ref_05_04; Inter_pix_copy3 <= Inter_ref_05_05;end + default:begin Inter_pix_copy0 <= 0; Inter_pix_copy1 <= 0; + Inter_pix_copy2 <= 0; Inter_pix_copy3 <= 0;end + endcase + 4'b0100: + case (blk4x4_inter_calculate_counter) + 4'd4:begin Inter_pix_copy0 <= Inter_ref_06_02; Inter_pix_copy1 <= Inter_ref_06_03; + Inter_pix_copy2 <= Inter_ref_06_04; Inter_pix_copy3 <= Inter_ref_06_05;end + 4'd3:begin Inter_pix_copy0 <= Inter_ref_07_02; Inter_pix_copy1 <= Inter_ref_07_03; + Inter_pix_copy2 <= Inter_ref_07_04; Inter_pix_copy3 <= Inter_ref_07_05;end + 4'd2:begin Inter_pix_copy0 <= Inter_ref_08_02; Inter_pix_copy1 <= Inter_ref_08_03; + Inter_pix_copy2 <= Inter_ref_08_04; Inter_pix_copy3 <= Inter_ref_08_05;end + 4'd1:begin Inter_pix_copy0 <= Inter_ref_09_02; Inter_pix_copy1 <= Inter_ref_09_03; + Inter_pix_copy2 <= Inter_ref_09_04; Inter_pix_copy3 <= Inter_ref_09_05;end + default:begin Inter_pix_copy0 <= 0; Inter_pix_copy1 <= 0; + Inter_pix_copy2 <= 0; Inter_pix_copy3 <= 0;end + endcase + 4'b0010: + case (blk4x4_inter_calculate_counter) + 4'd4:begin Inter_pix_copy0 <= Inter_ref_02_06; Inter_pix_copy1 <= Inter_ref_02_07; + Inter_pix_copy2 <= Inter_ref_02_08; Inter_pix_copy3 <= Inter_ref_02_09;end + 4'd3:begin Inter_pix_copy0 <= Inter_ref_03_06; Inter_pix_copy1 <= Inter_ref_03_07; + Inter_pix_copy2 <= Inter_ref_03_08; Inter_pix_copy3 <= Inter_ref_03_09;end + 4'd2:begin Inter_pix_copy0 <= Inter_ref_04_06; Inter_pix_copy1 <= Inter_ref_04_07; + Inter_pix_copy2 <= Inter_ref_04_08; Inter_pix_copy3 <= Inter_ref_04_09;end + 4'd1:begin Inter_pix_copy0 <= Inter_ref_05_06; Inter_pix_copy1 <= Inter_ref_05_07; + Inter_pix_copy2 <= Inter_ref_05_08; Inter_pix_copy3 <= Inter_ref_05_09;end + default:begin Inter_pix_copy0 <= 0; Inter_pix_copy1 <= 0; + Inter_pix_copy2 <= 0; Inter_pix_copy3 <= 0;end + endcase + 4'b0001: + case (blk4x4_inter_calculate_counter) + 4'd4:begin Inter_pix_copy0 <= Inter_ref_06_06; Inter_pix_copy1 <= Inter_ref_06_07; + Inter_pix_copy2 <= Inter_ref_06_08; Inter_pix_copy3 <= Inter_ref_06_09;end + 4'd3:begin Inter_pix_copy0 <= Inter_ref_07_06; Inter_pix_copy1 <= Inter_ref_07_07; + Inter_pix_copy2 <= Inter_ref_07_08; Inter_pix_copy3 <= Inter_ref_07_09;end + 4'd2:begin Inter_pix_copy0 <= Inter_ref_08_06; Inter_pix_copy1 <= Inter_ref_08_07; + Inter_pix_copy2 <= Inter_ref_08_08; Inter_pix_copy3 <= Inter_ref_08_09;end + 4'd1:begin Inter_pix_copy0 <= Inter_ref_09_06; Inter_pix_copy1 <= Inter_ref_09_07; + Inter_pix_copy2 <= Inter_ref_09_08; Inter_pix_copy3 <= Inter_ref_09_09;end + default:begin Inter_pix_copy0 <= 0; Inter_pix_copy1 <= 0; + Inter_pix_copy2 <= 0; Inter_pix_copy3 <= 0;end + endcase + default:begin Inter_pix_copy0 <= 0; Inter_pix_copy1 <= 0; + Inter_pix_copy2 <= 0; Inter_pix_copy3 <= 0;end + endcase + else if (Is_InterChromaCopy) + case (mv_below8x8_curr) + 1'b1://only one cycle + begin + Inter_pix_copy0 <= (blk4x4_inter_calculate_counter != 0)? Inter_ref_00_00:0; + Inter_pix_copy1 <= (blk4x4_inter_calculate_counter != 0)? Inter_ref_01_00:0; + Inter_pix_copy2 <= (blk4x4_inter_calculate_counter != 0)? Inter_ref_00_01:0; + Inter_pix_copy3 <= (blk4x4_inter_calculate_counter != 0)? Inter_ref_01_01:0; + end + 1'b0://4 cycles,each cycle for one blk2x2 in blk2x2-zig-zag order + case (blk4x4_inter_calculate_counter) + 4'd4: + begin + Inter_pix_copy0 <= Inter_ref_00_00; Inter_pix_copy1 <= Inter_ref_01_00; + Inter_pix_copy2 <= Inter_ref_00_01; Inter_pix_copy3 <= Inter_ref_01_01; + end + 4'd3: + begin + Inter_pix_copy0 <= Inter_ref_02_00; Inter_pix_copy1 <= Inter_ref_03_00; + Inter_pix_copy2 <= Inter_ref_02_01; Inter_pix_copy3 <= Inter_ref_03_01; + end + 4'd2: + begin + Inter_pix_copy0 <= Inter_ref_00_02; Inter_pix_copy1 <= Inter_ref_01_02; + Inter_pix_copy2 <= Inter_ref_00_03; Inter_pix_copy3 <= Inter_ref_01_03; + end + 4'd1: + begin + Inter_pix_copy0 <= Inter_ref_02_02; Inter_pix_copy1 <= Inter_ref_03_02; + Inter_pix_copy2 <= Inter_ref_02_03; Inter_pix_copy3 <= Inter_ref_03_03; + end + default: + begin + Inter_pix_copy0 <= 0; Inter_pix_copy1 <= 0; Inter_pix_copy2 <= 0; Inter_pix_copy3 <= 0; + end + endcase + endcase + else + begin + Inter_pix_copy0 <= 0; Inter_pix_copy1 <= 0; Inter_pix_copy2 <= 0; Inter_pix_copy3 <= 0; + end + + //Horizontal sliding windows:Inter_H_window_0_0 ~ Inter_H_window_5_8 (6x9 windows) + // Inter_H_window_x_0,Inter_H_window_x_1,Inter_H_window_x_6,Inter_H_window_x_7,Inter_H_window_x_8 + // are only used for pos_j/pos_i/pos_k/pos_f/pos_q + //Vertical sliding window:Inter_V_window_0 ~ Inter_V_window_8 + //Chroma sliding window:Inter_C_window_0 ~ Inter_C_window_3 + + //By careful study,we find that pos_b calculate cycle4 needs the same window as pos_a calculate cycl5. + //Similar cases happens with pos_b and pos_a/pos_c,pos_h and pos_d/pos_n, pos_j and pos_f/pos_q/pos_i/pos_k...... + + //Inter_H_window_counter0:for Inter_H_window_x_0/1/6/7/8 sliding window control + reg [2:0] Inter_H_window_counter0; + always @ (pos_FracL or blk4x4_inter_calculate_counter) + if ((pos_FracL == `pos_j && blk4x4_inter_calculate_counter == 4'd5) || + ((pos_FracL == `pos_f || pos_FracL == `pos_q) && blk4x4_inter_calculate_counter == 4'd5) || + ((pos_FracL == `pos_i || pos_FracL == `pos_k) && blk4x4_inter_calculate_counter == 4'd8)) + Inter_H_window_counter0 <= 3'd4; + else if ((pos_FracL == `pos_j && blk4x4_inter_calculate_counter == 4'd4) || + ((pos_FracL == `pos_f || pos_FracL == `pos_q) && blk4x4_inter_calculate_counter == 4'd4) || + ((pos_FracL == `pos_i || pos_FracL == `pos_k) && blk4x4_inter_calculate_counter == 4'd6)) + Inter_H_window_counter0 <= 3'd3; + else if ((pos_FracL == `pos_j && blk4x4_inter_calculate_counter == 4'd3) || + ((pos_FracL == `pos_f || pos_FracL == `pos_q) && blk4x4_inter_calculate_counter == 4'd3) || + ((pos_FracL == `pos_i || pos_FracL == `pos_k) && blk4x4_inter_calculate_counter == 4'd4)) + Inter_H_window_counter0 <= 3'd2; + else if ((pos_FracL == `pos_j && blk4x4_inter_calculate_counter == 4'd2) || + ((pos_FracL == `pos_f || pos_FracL == `pos_q) && blk4x4_inter_calculate_counter == 4'd2) || + ((pos_FracL == `pos_i || pos_FracL == `pos_k) && blk4x4_inter_calculate_counter == 4'd2)) + Inter_H_window_counter0 <= 3'd1; + else + Inter_H_window_counter0 <= 0; + + + //Inter_H_window_x_0,Inter_H_window_x_1 + //Inter_H_window_x_6,Inter_H_window_x_7,Inter_H_window_x_8 + //Active only for pos j,i/k/f/q + always @ (Is_blk4x4_0 or Is_blk4x4_1 or Is_blk4x4_2 or Is_blk4x4_3 or Inter_H_window_counter0 + + or Inter_ref_00_00 or Inter_ref_01_00 or Inter_ref_02_00 or Inter_ref_03_00 + or Inter_ref_04_00 or Inter_ref_05_00 or Inter_ref_06_00 or Inter_ref_07_00 + or Inter_ref_08_00 or Inter_ref_09_00 or Inter_ref_10_00 or Inter_ref_11_00 or Inter_ref_12_00 + + or Inter_ref_00_01 or Inter_ref_01_01 or Inter_ref_02_01 or Inter_ref_03_01 + or Inter_ref_04_01 or Inter_ref_05_01 or Inter_ref_06_01 or Inter_ref_07_01 + or Inter_ref_08_01 or Inter_ref_09_01 or Inter_ref_10_01 or Inter_ref_11_01 or Inter_ref_12_01 + + or Inter_ref_00_06 or Inter_ref_01_06 or Inter_ref_02_06 or Inter_ref_03_06 + or Inter_ref_04_06 or Inter_ref_05_06 or Inter_ref_06_06 or Inter_ref_07_06 + or Inter_ref_08_06 or Inter_ref_09_06 or Inter_ref_10_06 or Inter_ref_11_06 or Inter_ref_12_06 + + or Inter_ref_00_07 or Inter_ref_01_07 or Inter_ref_02_07 or Inter_ref_03_07 + or Inter_ref_04_07 or Inter_ref_05_07 or Inter_ref_06_07 or Inter_ref_07_07 + or Inter_ref_08_07 or Inter_ref_09_07 or Inter_ref_10_07 or Inter_ref_11_07 or Inter_ref_12_07 + + or Inter_ref_00_08 or Inter_ref_01_08 or Inter_ref_02_08 or Inter_ref_03_08 + or Inter_ref_04_08 or Inter_ref_05_08 or Inter_ref_06_08 or Inter_ref_07_08 + or Inter_ref_08_08 or Inter_ref_09_08 or Inter_ref_10_08 or Inter_ref_11_08 or Inter_ref_12_08 + + or Inter_ref_00_04 or Inter_ref_01_04 or Inter_ref_02_04 or Inter_ref_03_04 + or Inter_ref_04_04 or Inter_ref_05_04 or Inter_ref_06_04 or Inter_ref_07_04 + or Inter_ref_08_04 or Inter_ref_09_04 or Inter_ref_10_04 or Inter_ref_11_04 or Inter_ref_12_04 + + or Inter_ref_00_05 or Inter_ref_01_05 or Inter_ref_02_05 or Inter_ref_03_05 + or Inter_ref_04_05 or Inter_ref_05_05 or Inter_ref_06_05 or Inter_ref_07_05 + or Inter_ref_08_05 or Inter_ref_09_05 or Inter_ref_10_05 or Inter_ref_11_05 or Inter_ref_12_05 + + or Inter_ref_00_10 or Inter_ref_01_10 or Inter_ref_02_10 or Inter_ref_03_10 + or Inter_ref_04_10 or Inter_ref_05_10 or Inter_ref_06_10 or Inter_ref_07_10 + or Inter_ref_08_10 or Inter_ref_09_10 or Inter_ref_10_10 or Inter_ref_11_10 or Inter_ref_12_10 + + or Inter_ref_00_11 or Inter_ref_01_11 or Inter_ref_02_11 or Inter_ref_03_11 + or Inter_ref_04_11 or Inter_ref_05_11 or Inter_ref_06_11 or Inter_ref_07_11 + or Inter_ref_08_11 or Inter_ref_09_11 or Inter_ref_10_11 or Inter_ref_11_11 or Inter_ref_12_11 + + or Inter_ref_00_12 or Inter_ref_01_12 or Inter_ref_02_12 or Inter_ref_03_12 + or Inter_ref_04_12 or Inter_ref_05_12 or Inter_ref_06_12 or Inter_ref_07_12 + or Inter_ref_08_12 or Inter_ref_09_12 or Inter_ref_10_12 or Inter_ref_11_12 or Inter_ref_12_12 + ) + case ({Is_blk4x4_0,Is_blk4x4_1,Is_blk4x4_2,Is_blk4x4_3}) + 4'b1000: //Left top blk4x4 + case (Inter_H_window_counter0) + 3'd4: + begin + Inter_H_window_0_0 <= Inter_ref_00_00;Inter_H_window_1_0 <= Inter_ref_01_00; + Inter_H_window_2_0 <= Inter_ref_02_00;Inter_H_window_3_0 <= Inter_ref_03_00; + Inter_H_window_4_0 <= Inter_ref_04_00;Inter_H_window_5_0 <= Inter_ref_05_00; + + Inter_H_window_0_1 <= Inter_ref_00_01;Inter_H_window_1_1 <= Inter_ref_01_01; + Inter_H_window_2_1 <= Inter_ref_02_01;Inter_H_window_3_1 <= Inter_ref_03_01; + Inter_H_window_4_1 <= Inter_ref_04_01;Inter_H_window_5_1 <= Inter_ref_05_01; + + Inter_H_window_0_6 <= Inter_ref_00_06;Inter_H_window_1_6 <= Inter_ref_01_06; + Inter_H_window_2_6 <= Inter_ref_02_06;Inter_H_window_3_6 <= Inter_ref_03_06; + Inter_H_window_4_6 <= Inter_ref_04_06;Inter_H_window_5_6 <= Inter_ref_05_06; + + Inter_H_window_0_7 <= Inter_ref_00_07;Inter_H_window_1_7 <= Inter_ref_01_07; + Inter_H_window_2_7 <= Inter_ref_02_07;Inter_H_window_3_7 <= Inter_ref_03_07; + Inter_H_window_4_7 <= Inter_ref_04_07;Inter_H_window_5_7 <= Inter_ref_05_07; + + Inter_H_window_0_8 <= Inter_ref_00_08;Inter_H_window_1_8 <= Inter_ref_01_08; + Inter_H_window_2_8 <= Inter_ref_02_08;Inter_H_window_3_8 <= Inter_ref_03_08; + Inter_H_window_4_8 <= Inter_ref_04_08;Inter_H_window_5_8 <= Inter_ref_05_08; + end + 3'd3: + begin + Inter_H_window_0_0 <= Inter_ref_01_00;Inter_H_window_1_0 <= Inter_ref_02_00; + Inter_H_window_2_0 <= Inter_ref_03_00;Inter_H_window_3_0 <= Inter_ref_04_00; + Inter_H_window_4_0 <= Inter_ref_05_00;Inter_H_window_5_0 <= Inter_ref_06_00; + + Inter_H_window_0_1 <= Inter_ref_01_01;Inter_H_window_1_1 <= Inter_ref_02_01; + Inter_H_window_2_1 <= Inter_ref_03_01;Inter_H_window_3_1 <= Inter_ref_04_01; + Inter_H_window_4_1 <= Inter_ref_05_01;Inter_H_window_5_1 <= Inter_ref_06_01; + + Inter_H_window_0_6 <= Inter_ref_01_06;Inter_H_window_1_6 <= Inter_ref_02_06; + Inter_H_window_2_6 <= Inter_ref_03_06;Inter_H_window_3_6 <= Inter_ref_04_06; + Inter_H_window_4_6 <= Inter_ref_05_06;Inter_H_window_5_6 <= Inter_ref_06_06; + + Inter_H_window_0_7 <= Inter_ref_01_07;Inter_H_window_1_7 <= Inter_ref_02_07; + Inter_H_window_2_7 <= Inter_ref_03_07;Inter_H_window_3_7 <= Inter_ref_04_07; + Inter_H_window_4_7 <= Inter_ref_05_07;Inter_H_window_5_7 <= Inter_ref_06_07; + + Inter_H_window_0_8 <= Inter_ref_01_08;Inter_H_window_1_8 <= Inter_ref_02_08; + Inter_H_window_2_8 <= Inter_ref_03_08;Inter_H_window_3_8 <= Inter_ref_04_08; + Inter_H_window_4_8 <= Inter_ref_05_08;Inter_H_window_5_8 <= Inter_ref_06_08; + end + 3'd2: + begin + Inter_H_window_0_0 <= Inter_ref_02_00;Inter_H_window_1_0 <= Inter_ref_03_00; + Inter_H_window_2_0 <= Inter_ref_04_00;Inter_H_window_3_0 <= Inter_ref_05_00; + Inter_H_window_4_0 <= Inter_ref_06_00;Inter_H_window_5_0 <= Inter_ref_07_00; + + Inter_H_window_0_1 <= Inter_ref_02_01;Inter_H_window_1_1 <= Inter_ref_03_01; + Inter_H_window_2_1 <= Inter_ref_04_01;Inter_H_window_3_1 <= Inter_ref_05_01; + Inter_H_window_4_1 <= Inter_ref_06_01;Inter_H_window_5_1 <= Inter_ref_07_01; + + Inter_H_window_0_6 <= Inter_ref_02_06;Inter_H_window_1_6 <= Inter_ref_03_06; + Inter_H_window_2_6 <= Inter_ref_04_06;Inter_H_window_3_6 <= Inter_ref_05_06; + Inter_H_window_4_6 <= Inter_ref_06_06;Inter_H_window_5_6 <= Inter_ref_07_06; + + Inter_H_window_0_7 <= Inter_ref_02_07;Inter_H_window_1_7 <= Inter_ref_03_07; + Inter_H_window_2_7 <= Inter_ref_04_07;Inter_H_window_3_7 <= Inter_ref_05_07; + Inter_H_window_4_7 <= Inter_ref_06_07;Inter_H_window_5_7 <= Inter_ref_07_07; + + Inter_H_window_0_8 <= Inter_ref_02_08;Inter_H_window_1_8 <= Inter_ref_03_08; + Inter_H_window_2_8 <= Inter_ref_04_08;Inter_H_window_3_8 <= Inter_ref_05_08; + Inter_H_window_4_8 <= Inter_ref_06_08;Inter_H_window_5_8 <= Inter_ref_07_08; + end + 3'd1: + begin + Inter_H_window_0_0 <= Inter_ref_03_00;Inter_H_window_1_0 <= Inter_ref_04_00; + Inter_H_window_2_0 <= Inter_ref_05_00;Inter_H_window_3_0 <= Inter_ref_06_00; + Inter_H_window_4_0 <= Inter_ref_07_00;Inter_H_window_5_0 <= Inter_ref_08_00; + + Inter_H_window_0_1 <= Inter_ref_03_01;Inter_H_window_1_1 <= Inter_ref_04_01; + Inter_H_window_2_1 <= Inter_ref_05_01;Inter_H_window_3_1 <= Inter_ref_06_01; + Inter_H_window_4_1 <= Inter_ref_07_01;Inter_H_window_5_1 <= Inter_ref_08_01; + + Inter_H_window_0_6 <= Inter_ref_03_06;Inter_H_window_1_6 <= Inter_ref_04_06; + Inter_H_window_2_6 <= Inter_ref_05_06;Inter_H_window_3_6 <= Inter_ref_06_06; + Inter_H_window_4_6 <= Inter_ref_07_06;Inter_H_window_5_6 <= Inter_ref_08_06; + + Inter_H_window_0_7 <= Inter_ref_03_07;Inter_H_window_1_7 <= Inter_ref_04_07; + Inter_H_window_2_7 <= Inter_ref_05_07;Inter_H_window_3_7 <= Inter_ref_06_07; + Inter_H_window_4_7 <= Inter_ref_07_07;Inter_H_window_5_7 <= Inter_ref_08_07; + + Inter_H_window_0_8 <= Inter_ref_03_08;Inter_H_window_1_8 <= Inter_ref_04_08; + Inter_H_window_2_8 <= Inter_ref_05_08;Inter_H_window_3_8 <= Inter_ref_06_08; + Inter_H_window_4_8 <= Inter_ref_07_08;Inter_H_window_5_8 <= Inter_ref_08_08; + end + default: + begin + Inter_H_window_0_0 <= 0;Inter_H_window_1_0 <= 0;Inter_H_window_2_0 <= 0; + Inter_H_window_3_0 <= 0;Inter_H_window_4_0 <= 0;Inter_H_window_5_0 <= 0; + + Inter_H_window_0_1 <= 0;Inter_H_window_1_1 <= 0;Inter_H_window_2_1 <= 0; + Inter_H_window_3_1 <= 0;Inter_H_window_4_1 <= 0;Inter_H_window_5_1 <= 0; + + Inter_H_window_0_6 <= 0;Inter_H_window_1_6 <= 0;Inter_H_window_2_6 <= 0; + Inter_H_window_3_6 <= 0;Inter_H_window_4_6 <= 0;Inter_H_window_5_6 <= 0; + + Inter_H_window_0_7 <= 0;Inter_H_window_1_7 <= 0;Inter_H_window_2_7 <= 0; + Inter_H_window_3_7 <= 0;Inter_H_window_4_7 <= 0;Inter_H_window_5_7 <= 0; + + Inter_H_window_0_8 <= 0;Inter_H_window_1_8 <= 0;Inter_H_window_2_8 <= 0; + Inter_H_window_3_8 <= 0;Inter_H_window_4_8 <= 0;Inter_H_window_5_8 <= 0; + end + endcase + 4'b0100: //Right top blk8x8 + case (Inter_H_window_counter0) + 3'd4: + begin + Inter_H_window_0_0 <= Inter_ref_04_00;Inter_H_window_1_0 <= Inter_ref_05_00; + Inter_H_window_2_0 <= Inter_ref_06_00;Inter_H_window_3_0 <= Inter_ref_07_00; + Inter_H_window_4_0 <= Inter_ref_08_00;Inter_H_window_5_0 <= Inter_ref_09_00; + + Inter_H_window_0_1 <= Inter_ref_04_01;Inter_H_window_1_1 <= Inter_ref_05_01; + Inter_H_window_2_1 <= Inter_ref_06_01;Inter_H_window_3_1 <= Inter_ref_07_01; + Inter_H_window_4_1 <= Inter_ref_08_01;Inter_H_window_5_1 <= Inter_ref_09_01; + + Inter_H_window_0_6 <= Inter_ref_04_06;Inter_H_window_1_6 <= Inter_ref_05_06; + Inter_H_window_2_6 <= Inter_ref_06_06;Inter_H_window_3_6 <= Inter_ref_07_06; + Inter_H_window_4_6 <= Inter_ref_08_06;Inter_H_window_5_6 <= Inter_ref_09_06; + + Inter_H_window_0_7 <= Inter_ref_04_07;Inter_H_window_1_7 <= Inter_ref_05_07; + Inter_H_window_2_7 <= Inter_ref_06_07;Inter_H_window_3_7 <= Inter_ref_07_07; + Inter_H_window_4_7 <= Inter_ref_08_07;Inter_H_window_5_7 <= Inter_ref_09_07; + + Inter_H_window_0_8 <= Inter_ref_04_08;Inter_H_window_1_8 <= Inter_ref_05_08; + Inter_H_window_2_8 <= Inter_ref_06_08;Inter_H_window_3_8 <= Inter_ref_07_08; + Inter_H_window_4_8 <= Inter_ref_08_08;Inter_H_window_5_8 <= Inter_ref_09_08; + end + 3'd3: + begin + Inter_H_window_0_0 <= Inter_ref_05_00;Inter_H_window_1_0 <= Inter_ref_06_00; + Inter_H_window_2_0 <= Inter_ref_07_00;Inter_H_window_3_0 <= Inter_ref_08_00; + Inter_H_window_4_0 <= Inter_ref_09_00;Inter_H_window_5_0 <= Inter_ref_10_00; + + Inter_H_window_0_1 <= Inter_ref_05_01;Inter_H_window_1_1 <= Inter_ref_06_01; + Inter_H_window_2_1 <= Inter_ref_07_01;Inter_H_window_3_1 <= Inter_ref_08_01; + Inter_H_window_4_1 <= Inter_ref_09_01;Inter_H_window_5_1 <= Inter_ref_10_01; + + Inter_H_window_0_6 <= Inter_ref_05_06;Inter_H_window_1_6 <= Inter_ref_06_06; + Inter_H_window_2_6 <= Inter_ref_07_06;Inter_H_window_3_6 <= Inter_ref_08_06; + Inter_H_window_4_6 <= Inter_ref_09_06;Inter_H_window_5_6 <= Inter_ref_10_06; + + Inter_H_window_0_7 <= Inter_ref_05_07;Inter_H_window_1_7 <= Inter_ref_06_07; + Inter_H_window_2_7 <= Inter_ref_07_07;Inter_H_window_3_7 <= Inter_ref_08_07; + Inter_H_window_4_7 <= Inter_ref_09_07;Inter_H_window_5_7 <= Inter_ref_10_07; + + Inter_H_window_0_8 <= Inter_ref_05_08;Inter_H_window_1_8 <= Inter_ref_06_08; + Inter_H_window_2_8 <= Inter_ref_07_08;Inter_H_window_3_8 <= Inter_ref_08_08; + Inter_H_window_4_8 <= Inter_ref_09_08;Inter_H_window_5_8 <= Inter_ref_10_08; + end + 3'd2: + begin + Inter_H_window_0_0 <= Inter_ref_06_00;Inter_H_window_1_0 <= Inter_ref_07_00; + Inter_H_window_2_0 <= Inter_ref_08_00;Inter_H_window_3_0 <= Inter_ref_09_00; + Inter_H_window_4_0 <= Inter_ref_10_00;Inter_H_window_5_0 <= Inter_ref_11_00; + + Inter_H_window_0_1 <= Inter_ref_06_01;Inter_H_window_1_1 <= Inter_ref_07_01; + Inter_H_window_2_1 <= Inter_ref_08_01;Inter_H_window_3_1 <= Inter_ref_09_01; + Inter_H_window_4_1 <= Inter_ref_10_01;Inter_H_window_5_1 <= Inter_ref_11_01; + + Inter_H_window_0_6 <= Inter_ref_06_06;Inter_H_window_1_6 <= Inter_ref_07_06; + Inter_H_window_2_6 <= Inter_ref_08_06;Inter_H_window_3_6 <= Inter_ref_09_06; + Inter_H_window_4_6 <= Inter_ref_10_06;Inter_H_window_5_6 <= Inter_ref_11_06; + + Inter_H_window_0_7 <= Inter_ref_06_07;Inter_H_window_1_7 <= Inter_ref_07_07; + Inter_H_window_2_7 <= Inter_ref_08_07;Inter_H_window_3_7 <= Inter_ref_09_07; + Inter_H_window_4_7 <= Inter_ref_10_07;Inter_H_window_5_7 <= Inter_ref_11_07; + + Inter_H_window_0_8 <= Inter_ref_06_08;Inter_H_window_1_8 <= Inter_ref_07_08; + Inter_H_window_2_8 <= Inter_ref_08_08;Inter_H_window_3_8 <= Inter_ref_09_08; + Inter_H_window_4_8 <= Inter_ref_10_08;Inter_H_window_5_8 <= Inter_ref_11_08; + end + 3'd1: + begin + Inter_H_window_0_0 <= Inter_ref_07_00;Inter_H_window_1_0 <= Inter_ref_08_00; + Inter_H_window_2_0 <= Inter_ref_09_00;Inter_H_window_3_0 <= Inter_ref_10_00; + Inter_H_window_4_0 <= Inter_ref_11_00;Inter_H_window_5_0 <= Inter_ref_12_00; + + Inter_H_window_0_1 <= Inter_ref_07_01;Inter_H_window_1_1 <= Inter_ref_08_01; + Inter_H_window_2_1 <= Inter_ref_09_01;Inter_H_window_3_1 <= Inter_ref_10_01; + Inter_H_window_4_1 <= Inter_ref_11_01;Inter_H_window_5_1 <= Inter_ref_12_01; + + Inter_H_window_0_6 <= Inter_ref_07_06;Inter_H_window_1_6 <= Inter_ref_08_06; + Inter_H_window_2_6 <= Inter_ref_09_06;Inter_H_window_3_6 <= Inter_ref_10_06; + Inter_H_window_4_6 <= Inter_ref_11_06;Inter_H_window_5_6 <= Inter_ref_12_06; + + Inter_H_window_0_7 <= Inter_ref_07_07;Inter_H_window_1_7 <= Inter_ref_08_07; + Inter_H_window_2_7 <= Inter_ref_09_07;Inter_H_window_3_7 <= Inter_ref_10_07; + Inter_H_window_4_7 <= Inter_ref_11_07;Inter_H_window_5_7 <= Inter_ref_12_07; + + Inter_H_window_0_8 <= Inter_ref_07_08;Inter_H_window_1_8 <= Inter_ref_08_08; + Inter_H_window_2_8 <= Inter_ref_09_08;Inter_H_window_3_8 <= Inter_ref_10_08; + Inter_H_window_4_8 <= Inter_ref_11_08;Inter_H_window_5_8 <= Inter_ref_12_08; + end + default: + begin + Inter_H_window_0_0 <= 0;Inter_H_window_1_0 <= 0;Inter_H_window_2_0 <= 0; + Inter_H_window_3_0 <= 0;Inter_H_window_4_0 <= 0;Inter_H_window_5_0 <= 0; + + Inter_H_window_0_1 <= 0;Inter_H_window_1_1 <= 0;Inter_H_window_2_1 <= 0; + Inter_H_window_3_1 <= 0;Inter_H_window_4_1 <= 0;Inter_H_window_5_1 <= 0; + + Inter_H_window_0_6 <= 0;Inter_H_window_1_6 <= 0;Inter_H_window_2_6 <= 0; + Inter_H_window_3_6 <= 0;Inter_H_window_4_6 <= 0;Inter_H_window_5_6 <= 0; + + Inter_H_window_0_7 <= 0;Inter_H_window_1_7 <= 0;Inter_H_window_2_7 <= 0; + Inter_H_window_3_7 <= 0;Inter_H_window_4_7 <= 0;Inter_H_window_5_7 <= 0; + + Inter_H_window_0_8 <= 0;Inter_H_window_1_8 <= 0;Inter_H_window_2_8 <= 0; + Inter_H_window_3_8 <= 0;Inter_H_window_4_8 <= 0;Inter_H_window_5_8 <= 0; + end + endcase + 4'b0010: //Left bottom blk4x4 + case (Inter_H_window_counter0) + 3'd4: + begin + Inter_H_window_0_0 <= Inter_ref_00_04;Inter_H_window_1_0 <= Inter_ref_01_04; + Inter_H_window_2_0 <= Inter_ref_02_04;Inter_H_window_3_0 <= Inter_ref_03_04; + Inter_H_window_4_0 <= Inter_ref_04_04;Inter_H_window_5_0 <= Inter_ref_05_04; + + Inter_H_window_0_1 <= Inter_ref_00_05;Inter_H_window_1_1 <= Inter_ref_01_05; + Inter_H_window_2_1 <= Inter_ref_02_05;Inter_H_window_3_1 <= Inter_ref_03_05; + Inter_H_window_4_1 <= Inter_ref_04_05;Inter_H_window_5_1 <= Inter_ref_05_05; + + Inter_H_window_0_6 <= Inter_ref_00_10;Inter_H_window_1_6 <= Inter_ref_01_10; + Inter_H_window_2_6 <= Inter_ref_02_10;Inter_H_window_3_6 <= Inter_ref_03_10; + Inter_H_window_4_6 <= Inter_ref_04_10;Inter_H_window_5_6 <= Inter_ref_05_10; + + Inter_H_window_0_7 <= Inter_ref_00_11;Inter_H_window_1_7 <= Inter_ref_01_11; + Inter_H_window_2_7 <= Inter_ref_02_11;Inter_H_window_3_7 <= Inter_ref_03_11; + Inter_H_window_4_7 <= Inter_ref_04_11;Inter_H_window_5_7 <= Inter_ref_05_11; + + Inter_H_window_0_8 <= Inter_ref_00_12;Inter_H_window_1_8 <= Inter_ref_01_12; + Inter_H_window_2_8 <= Inter_ref_02_12;Inter_H_window_3_8 <= Inter_ref_03_12; + Inter_H_window_4_8 <= Inter_ref_04_12;Inter_H_window_5_8 <= Inter_ref_05_12; + end + 3'd3: + begin + Inter_H_window_0_0 <= Inter_ref_01_04;Inter_H_window_1_0 <= Inter_ref_02_04; + Inter_H_window_2_0 <= Inter_ref_03_04;Inter_H_window_3_0 <= Inter_ref_04_04; + Inter_H_window_4_0 <= Inter_ref_05_04;Inter_H_window_5_0 <= Inter_ref_06_04; + + Inter_H_window_0_1 <= Inter_ref_01_05;Inter_H_window_1_1 <= Inter_ref_02_05; + Inter_H_window_2_1 <= Inter_ref_03_05;Inter_H_window_3_1 <= Inter_ref_04_05; + Inter_H_window_4_1 <= Inter_ref_05_05;Inter_H_window_5_1 <= Inter_ref_06_05; + + Inter_H_window_0_6 <= Inter_ref_01_10;Inter_H_window_1_6 <= Inter_ref_02_10; + Inter_H_window_2_6 <= Inter_ref_03_10;Inter_H_window_3_6 <= Inter_ref_04_10; + Inter_H_window_4_6 <= Inter_ref_05_10;Inter_H_window_5_6 <= Inter_ref_06_10; + + Inter_H_window_0_7 <= Inter_ref_01_11;Inter_H_window_1_7 <= Inter_ref_02_11; + Inter_H_window_2_7 <= Inter_ref_03_11;Inter_H_window_3_7 <= Inter_ref_04_11; + Inter_H_window_4_7 <= Inter_ref_05_11;Inter_H_window_5_7 <= Inter_ref_06_11; + + Inter_H_window_0_8 <= Inter_ref_01_12;Inter_H_window_1_8 <= Inter_ref_02_12; + Inter_H_window_2_8 <= Inter_ref_03_12;Inter_H_window_3_8 <= Inter_ref_04_12; + Inter_H_window_4_8 <= Inter_ref_05_12;Inter_H_window_5_8 <= Inter_ref_06_12; + end + 3'd2: + begin + Inter_H_window_0_0 <= Inter_ref_02_04;Inter_H_window_1_0 <= Inter_ref_03_04; + Inter_H_window_2_0 <= Inter_ref_04_04;Inter_H_window_3_0 <= Inter_ref_05_04; + Inter_H_window_4_0 <= Inter_ref_06_04;Inter_H_window_5_0 <= Inter_ref_07_04; + + Inter_H_window_0_1 <= Inter_ref_02_05;Inter_H_window_1_1 <= Inter_ref_03_05; + Inter_H_window_2_1 <= Inter_ref_04_05;Inter_H_window_3_1 <= Inter_ref_05_05; + Inter_H_window_4_1 <= Inter_ref_06_05;Inter_H_window_5_1 <= Inter_ref_07_05; + + Inter_H_window_0_6 <= Inter_ref_02_10;Inter_H_window_1_6 <= Inter_ref_03_10; + Inter_H_window_2_6 <= Inter_ref_04_10;Inter_H_window_3_6 <= Inter_ref_05_10; + Inter_H_window_4_6 <= Inter_ref_06_10;Inter_H_window_5_6 <= Inter_ref_07_10; + + Inter_H_window_0_7 <= Inter_ref_02_11;Inter_H_window_1_7 <= Inter_ref_03_11; + Inter_H_window_2_7 <= Inter_ref_04_11;Inter_H_window_3_7 <= Inter_ref_05_11; + Inter_H_window_4_7 <= Inter_ref_06_11;Inter_H_window_5_7 <= Inter_ref_07_11; + + Inter_H_window_0_8 <= Inter_ref_02_12;Inter_H_window_1_8 <= Inter_ref_03_12; + Inter_H_window_2_8 <= Inter_ref_04_12;Inter_H_window_3_8 <= Inter_ref_05_12; + Inter_H_window_4_8 <= Inter_ref_06_12;Inter_H_window_5_8 <= Inter_ref_07_12; + end + 3'd1: + begin + Inter_H_window_0_0 <= Inter_ref_03_04;Inter_H_window_1_0 <= Inter_ref_04_04; + Inter_H_window_2_0 <= Inter_ref_05_04;Inter_H_window_3_0 <= Inter_ref_06_04; + Inter_H_window_4_0 <= Inter_ref_07_04;Inter_H_window_5_0 <= Inter_ref_08_04; + + Inter_H_window_0_1 <= Inter_ref_03_05;Inter_H_window_1_1 <= Inter_ref_04_05; + Inter_H_window_2_1 <= Inter_ref_05_05;Inter_H_window_3_1 <= Inter_ref_06_05; + Inter_H_window_4_1 <= Inter_ref_07_05;Inter_H_window_5_1 <= Inter_ref_08_05; + + Inter_H_window_0_6 <= Inter_ref_03_10;Inter_H_window_1_6 <= Inter_ref_04_10; + Inter_H_window_2_6 <= Inter_ref_05_10;Inter_H_window_3_6 <= Inter_ref_06_10; + Inter_H_window_4_6 <= Inter_ref_07_10;Inter_H_window_5_6 <= Inter_ref_08_10; + + Inter_H_window_0_7 <= Inter_ref_03_11;Inter_H_window_1_7 <= Inter_ref_04_11; + Inter_H_window_2_7 <= Inter_ref_05_11;Inter_H_window_3_7 <= Inter_ref_06_11; + Inter_H_window_4_7 <= Inter_ref_07_11;Inter_H_window_5_7 <= Inter_ref_08_11; + + Inter_H_window_0_8 <= Inter_ref_03_12;Inter_H_window_1_8 <= Inter_ref_04_12; + Inter_H_window_2_8 <= Inter_ref_05_12;Inter_H_window_3_8 <= Inter_ref_06_12; + Inter_H_window_4_8 <= Inter_ref_07_12;Inter_H_window_5_8 <= Inter_ref_08_12; + end + default: + begin + Inter_H_window_0_0 <= 0;Inter_H_window_1_0 <= 0;Inter_H_window_2_0 <= 0; + Inter_H_window_3_0 <= 0;Inter_H_window_4_0 <= 0;Inter_H_window_5_0 <= 0; + + Inter_H_window_0_1 <= 0;Inter_H_window_1_1 <= 0;Inter_H_window_2_1 <= 0; + Inter_H_window_3_1 <= 0;Inter_H_window_4_1 <= 0;Inter_H_window_5_1 <= 0; + + Inter_H_window_0_6 <= 0;Inter_H_window_1_6 <= 0;Inter_H_window_2_6 <= 0; + Inter_H_window_3_6 <= 0;Inter_H_window_4_6 <= 0;Inter_H_window_5_6 <= 0; + + Inter_H_window_0_7 <= 0;Inter_H_window_1_7 <= 0;Inter_H_window_2_7 <= 0; + Inter_H_window_3_7 <= 0;Inter_H_window_4_7 <= 0;Inter_H_window_5_7 <= 0; + + Inter_H_window_0_8 <= 0;Inter_H_window_1_8 <= 0;Inter_H_window_2_8 <= 0; + Inter_H_window_3_8 <= 0;Inter_H_window_4_8 <= 0;Inter_H_window_5_8 <= 0; + end + endcase + 4'b0001: //Right bottom blk4x4 + case (Inter_H_window_counter0) + 3'd4: + begin + Inter_H_window_0_0 <= Inter_ref_04_04;Inter_H_window_1_0 <= Inter_ref_05_04; + Inter_H_window_2_0 <= Inter_ref_06_04;Inter_H_window_3_0 <= Inter_ref_07_04; + Inter_H_window_4_0 <= Inter_ref_08_04;Inter_H_window_5_0 <= Inter_ref_09_04; + + Inter_H_window_0_1 <= Inter_ref_04_05;Inter_H_window_1_1 <= Inter_ref_05_05; + Inter_H_window_2_1 <= Inter_ref_06_05;Inter_H_window_3_1 <= Inter_ref_07_05; + Inter_H_window_4_1 <= Inter_ref_08_05;Inter_H_window_5_1 <= Inter_ref_09_05; + + Inter_H_window_0_6 <= Inter_ref_04_10;Inter_H_window_1_6 <= Inter_ref_05_10; + Inter_H_window_2_6 <= Inter_ref_06_10;Inter_H_window_3_6 <= Inter_ref_07_10; + Inter_H_window_4_6 <= Inter_ref_08_10;Inter_H_window_5_6 <= Inter_ref_09_10; + + Inter_H_window_0_7 <= Inter_ref_04_11;Inter_H_window_1_7 <= Inter_ref_05_11; + Inter_H_window_2_7 <= Inter_ref_06_11;Inter_H_window_3_7 <= Inter_ref_07_11; + Inter_H_window_4_7 <= Inter_ref_08_11;Inter_H_window_5_7 <= Inter_ref_09_11; + + Inter_H_window_0_8 <= Inter_ref_04_12;Inter_H_window_1_8 <= Inter_ref_05_12; + Inter_H_window_2_8 <= Inter_ref_06_12;Inter_H_window_3_8 <= Inter_ref_07_12; + Inter_H_window_4_8 <= Inter_ref_08_12;Inter_H_window_5_8 <= Inter_ref_09_12; + end + 3'd3: + begin + Inter_H_window_0_0 <= Inter_ref_05_04;Inter_H_window_1_0 <= Inter_ref_06_04; + Inter_H_window_2_0 <= Inter_ref_07_04;Inter_H_window_3_0 <= Inter_ref_08_04; + Inter_H_window_4_0 <= Inter_ref_09_04;Inter_H_window_5_0 <= Inter_ref_10_04; + + Inter_H_window_0_1 <= Inter_ref_05_05;Inter_H_window_1_1 <= Inter_ref_06_05; + Inter_H_window_2_1 <= Inter_ref_07_05;Inter_H_window_3_1 <= Inter_ref_08_05; + Inter_H_window_4_1 <= Inter_ref_09_05;Inter_H_window_5_1 <= Inter_ref_10_05; + + Inter_H_window_0_6 <= Inter_ref_05_10;Inter_H_window_1_6 <= Inter_ref_06_10; + Inter_H_window_2_6 <= Inter_ref_07_10;Inter_H_window_3_6 <= Inter_ref_08_10; + Inter_H_window_4_6 <= Inter_ref_09_10;Inter_H_window_5_6 <= Inter_ref_10_10; + + Inter_H_window_0_7 <= Inter_ref_05_11;Inter_H_window_1_7 <= Inter_ref_06_11; + Inter_H_window_2_7 <= Inter_ref_07_11;Inter_H_window_3_7 <= Inter_ref_08_11; + Inter_H_window_4_7 <= Inter_ref_09_11;Inter_H_window_5_7 <= Inter_ref_10_11; + + Inter_H_window_0_8 <= Inter_ref_05_12;Inter_H_window_1_8 <= Inter_ref_06_12; + Inter_H_window_2_8 <= Inter_ref_07_12;Inter_H_window_3_8 <= Inter_ref_08_12; + Inter_H_window_4_8 <= Inter_ref_09_12;Inter_H_window_5_8 <= Inter_ref_10_12; + end + 3'd2: + begin + Inter_H_window_0_0 <= Inter_ref_06_04;Inter_H_window_1_0 <= Inter_ref_07_04; + Inter_H_window_2_0 <= Inter_ref_08_04;Inter_H_window_3_0 <= Inter_ref_09_04; + Inter_H_window_4_0 <= Inter_ref_10_04;Inter_H_window_5_0 <= Inter_ref_11_04; + + Inter_H_window_0_1 <= Inter_ref_06_05;Inter_H_window_1_1 <= Inter_ref_07_05; + Inter_H_window_2_1 <= Inter_ref_08_05;Inter_H_window_3_1 <= Inter_ref_09_05; + Inter_H_window_4_1 <= Inter_ref_10_05;Inter_H_window_5_1 <= Inter_ref_11_05; + + Inter_H_window_0_6 <= Inter_ref_06_10;Inter_H_window_1_6 <= Inter_ref_07_10; + Inter_H_window_2_6 <= Inter_ref_08_10;Inter_H_window_3_6 <= Inter_ref_09_10; + Inter_H_window_4_6 <= Inter_ref_10_10;Inter_H_window_5_6 <= Inter_ref_11_10; + + Inter_H_window_0_7 <= Inter_ref_06_11;Inter_H_window_1_7 <= Inter_ref_07_11; + Inter_H_window_2_7 <= Inter_ref_08_11;Inter_H_window_3_7 <= Inter_ref_09_11; + Inter_H_window_4_7 <= Inter_ref_10_11;Inter_H_window_5_7 <= Inter_ref_11_11; + + Inter_H_window_0_8 <= Inter_ref_06_12;Inter_H_window_1_8 <= Inter_ref_07_12; + Inter_H_window_2_8 <= Inter_ref_08_12;Inter_H_window_3_8 <= Inter_ref_09_12; + Inter_H_window_4_8 <= Inter_ref_10_12;Inter_H_window_5_8 <= Inter_ref_11_12; + end + 3'd1: + begin + Inter_H_window_0_0 <= Inter_ref_07_04;Inter_H_window_1_0 <= Inter_ref_08_04; + Inter_H_window_2_0 <= Inter_ref_09_04;Inter_H_window_3_0 <= Inter_ref_10_04; + Inter_H_window_4_0 <= Inter_ref_11_04;Inter_H_window_5_0 <= Inter_ref_12_04; + + Inter_H_window_0_1 <= Inter_ref_07_05;Inter_H_window_1_1 <= Inter_ref_08_05; + Inter_H_window_2_1 <= Inter_ref_09_05;Inter_H_window_3_1 <= Inter_ref_10_05; + Inter_H_window_4_1 <= Inter_ref_11_05;Inter_H_window_5_1 <= Inter_ref_12_05; + + Inter_H_window_0_6 <= Inter_ref_07_10;Inter_H_window_1_6 <= Inter_ref_08_10; + Inter_H_window_2_6 <= Inter_ref_09_10;Inter_H_window_3_6 <= Inter_ref_10_10; + Inter_H_window_4_6 <= Inter_ref_11_10;Inter_H_window_5_6 <= Inter_ref_12_10; + + Inter_H_window_0_7 <= Inter_ref_07_11;Inter_H_window_1_7 <= Inter_ref_08_11; + Inter_H_window_2_7 <= Inter_ref_09_11;Inter_H_window_3_7 <= Inter_ref_10_11; + Inter_H_window_4_7 <= Inter_ref_11_11;Inter_H_window_5_7 <= Inter_ref_12_11; + + Inter_H_window_0_8 <= Inter_ref_07_12;Inter_H_window_1_8 <= Inter_ref_08_12; + Inter_H_window_2_8 <= Inter_ref_09_12;Inter_H_window_3_8 <= Inter_ref_10_12; + Inter_H_window_4_8 <= Inter_ref_11_12;Inter_H_window_5_8 <= Inter_ref_12_12; + end + default: + begin + Inter_H_window_0_0 <= 0;Inter_H_window_1_0 <= 0;Inter_H_window_2_0 <= 0; + Inter_H_window_3_0 <= 0;Inter_H_window_4_0 <= 0;Inter_H_window_5_0 <= 0; + + Inter_H_window_0_1 <= 0;Inter_H_window_1_1 <= 0;Inter_H_window_2_1 <= 0; + Inter_H_window_3_1 <= 0;Inter_H_window_4_1 <= 0;Inter_H_window_5_1 <= 0; + + Inter_H_window_0_6 <= 0;Inter_H_window_1_6 <= 0;Inter_H_window_2_6 <= 0; + Inter_H_window_3_6 <= 0;Inter_H_window_4_6 <= 0;Inter_H_window_5_6 <= 0; + + Inter_H_window_0_7 <= 0;Inter_H_window_1_7 <= 0;Inter_H_window_2_7 <= 0; + Inter_H_window_3_7 <= 0;Inter_H_window_4_7 <= 0;Inter_H_window_5_7 <= 0; + + Inter_H_window_0_8 <= 0;Inter_H_window_1_8 <= 0;Inter_H_window_2_8 <= 0; + Inter_H_window_3_8 <= 0;Inter_H_window_4_8 <= 0;Inter_H_window_5_8 <= 0; + end + endcase + default: + begin + Inter_H_window_0_0 <= 0;Inter_H_window_1_0 <= 0;Inter_H_window_2_0 <= 0; + Inter_H_window_3_0 <= 0;Inter_H_window_4_0 <= 0;Inter_H_window_5_0 <= 0; + + Inter_H_window_0_1 <= 0;Inter_H_window_1_1 <= 0;Inter_H_window_2_1 <= 0; + Inter_H_window_3_1 <= 0;Inter_H_window_4_1 <= 0;Inter_H_window_5_1 <= 0; + + Inter_H_window_0_6 <= 0;Inter_H_window_1_6 <= 0;Inter_H_window_2_6 <= 0; + Inter_H_window_3_6 <= 0;Inter_H_window_4_6 <= 0;Inter_H_window_5_6 <= 0; + + Inter_H_window_0_7 <= 0;Inter_H_window_1_7 <= 0;Inter_H_window_2_7 <= 0; + Inter_H_window_3_7 <= 0;Inter_H_window_4_7 <= 0;Inter_H_window_5_7 <= 0; + + Inter_H_window_0_8 <= 0;Inter_H_window_1_8 <= 0;Inter_H_window_2_8 <= 0; + Inter_H_window_3_8 <= 0;Inter_H_window_4_8 <= 0;Inter_H_window_5_8 <= 0; + end + endcase + + //Inter_H_window_counter1:for Inter_H_window_x_2/3/4/5 sliding window control + reg [2:0] Inter_H_window_counter1; + always @ (pos_FracL or blk4x4_inter_calculate_counter) + if (((pos_FracL == `pos_b || pos_FracL == `pos_a || pos_FracL == `pos_c || pos_FracL == `pos_e || pos_FracL == `pos_g + || pos_FracL == `pos_p || pos_FracL == `pos_r) && blk4x4_inter_calculate_counter == 4'd4) || + ((pos_FracL == `pos_j || pos_FracL == `pos_f || pos_FracL == `pos_q) && blk4x4_inter_calculate_counter == 4'd5) || + ((pos_FracL == `pos_i || pos_FracL == `pos_k) && blk4x4_inter_calculate_counter == 4'd8)) + Inter_H_window_counter1 <= 3'd4; + else if (((pos_FracL == `pos_b || pos_FracL == `pos_a || pos_FracL == `pos_c || pos_FracL == `pos_e || pos_FracL == `pos_g + || pos_FracL == `pos_p || pos_FracL == `pos_r) && blk4x4_inter_calculate_counter == 4'd3) || + ((pos_FracL == `pos_j || pos_FracL == `pos_f || pos_FracL == `pos_q) && blk4x4_inter_calculate_counter == 4'd4) || + ((pos_FracL == `pos_i || pos_FracL == `pos_k) && blk4x4_inter_calculate_counter == 4'd6)) + Inter_H_window_counter1 <= 3'd3; + else if (((pos_FracL == `pos_b || pos_FracL == `pos_a || pos_FracL == `pos_c || pos_FracL == `pos_e || pos_FracL == `pos_g + || pos_FracL == `pos_p || pos_FracL == `pos_r) && blk4x4_inter_calculate_counter == 4'd2) || + ((pos_FracL == `pos_j || pos_FracL == `pos_f || pos_FracL == `pos_q) && blk4x4_inter_calculate_counter == 4'd3) || + ((pos_FracL == `pos_i || pos_FracL == `pos_k) && blk4x4_inter_calculate_counter == 4'd4)) + Inter_H_window_counter1 <= 3'd2; + else if (((pos_FracL == `pos_b || pos_FracL == `pos_a || pos_FracL == `pos_c || pos_FracL == `pos_e || pos_FracL == `pos_g + || pos_FracL == `pos_p || pos_FracL == `pos_r) && blk4x4_inter_calculate_counter == 4'd1) || + ((pos_FracL == `pos_j || pos_FracL == `pos_f || pos_FracL == `pos_q) && blk4x4_inter_calculate_counter == 4'd2) || + ((pos_FracL == `pos_i || pos_FracL == `pos_k) && blk4x4_inter_calculate_counter == 4'd2)) + Inter_H_window_counter1 <= 3'd1; + else + Inter_H_window_counter1 <= 0; + + //Inter_H_window_x_2,Inter_H_window_x_3,Inter_H_window_x_4,Inter_H_window_x_5 + always @ (Is_blk4x4_0 or Is_blk4x4_1 or Is_blk4x4_2 or Is_blk4x4_3 or pos_FracL or Inter_H_window_counter1 + or Inter_ref_00_02 or Inter_ref_01_02 or Inter_ref_02_02 or Inter_ref_03_02 + or Inter_ref_04_02 or Inter_ref_05_02 or Inter_ref_06_02 or Inter_ref_07_02 + or Inter_ref_08_02 or Inter_ref_09_02 or Inter_ref_10_02 or Inter_ref_11_02 or Inter_ref_12_02 + + or Inter_ref_00_03 or Inter_ref_01_03 or Inter_ref_02_03 or Inter_ref_03_03 + or Inter_ref_04_03 or Inter_ref_05_03 or Inter_ref_06_03 or Inter_ref_07_03 + or Inter_ref_08_03 or Inter_ref_09_03 or Inter_ref_10_03 or Inter_ref_11_03 or Inter_ref_12_03 + + or Inter_ref_00_04 or Inter_ref_01_04 or Inter_ref_02_04 or Inter_ref_03_04 + or Inter_ref_04_04 or Inter_ref_05_04 or Inter_ref_06_04 or Inter_ref_07_04 + or Inter_ref_08_04 or Inter_ref_09_04 or Inter_ref_10_04 or Inter_ref_11_04 or Inter_ref_12_04 + + or Inter_ref_00_05 or Inter_ref_01_05 or Inter_ref_02_05 or Inter_ref_03_05 + or Inter_ref_04_05 or Inter_ref_05_05 or Inter_ref_06_05 or Inter_ref_07_05 + or Inter_ref_08_05 or Inter_ref_09_05 or Inter_ref_10_05 or Inter_ref_11_05 or Inter_ref_12_05 + + or Inter_ref_00_06 or Inter_ref_01_06 or Inter_ref_02_06 or Inter_ref_03_06 + or Inter_ref_04_06 or Inter_ref_05_06 or Inter_ref_06_06 or Inter_ref_07_06 + or Inter_ref_08_06 or Inter_ref_09_06 or Inter_ref_10_06 or Inter_ref_11_06 or Inter_ref_12_06 + + or Inter_ref_00_07 or Inter_ref_01_07 or Inter_ref_02_07 or Inter_ref_03_07 + or Inter_ref_04_07 or Inter_ref_05_07 or Inter_ref_06_07 or Inter_ref_07_07 + or Inter_ref_08_07 or Inter_ref_09_07 or Inter_ref_10_07 or Inter_ref_11_07 or Inter_ref_12_07 + + or Inter_ref_00_08 or Inter_ref_01_08 or Inter_ref_02_08 or Inter_ref_03_08 + or Inter_ref_04_08 or Inter_ref_05_08 or Inter_ref_06_08 or Inter_ref_07_08 + or Inter_ref_08_08 or Inter_ref_09_08 or Inter_ref_10_08 or Inter_ref_11_08 or Inter_ref_12_08 + + or Inter_ref_00_09 or Inter_ref_01_09 or Inter_ref_02_09 or Inter_ref_03_09 + or Inter_ref_04_09 or Inter_ref_05_09 or Inter_ref_06_09 or Inter_ref_07_09 + or Inter_ref_08_09 or Inter_ref_09_09 or Inter_ref_10_09 or Inter_ref_11_09 or Inter_ref_12_09 + + or Inter_ref_00_10 or Inter_ref_01_10 or Inter_ref_02_10 or Inter_ref_03_10 + or Inter_ref_04_10 or Inter_ref_05_10 or Inter_ref_06_10 or Inter_ref_07_10 + or Inter_ref_08_10 or Inter_ref_09_10 or Inter_ref_10_10 or Inter_ref_11_10 or Inter_ref_12_10 + ) + case ({Is_blk4x4_0,Is_blk4x4_1,Is_blk4x4_2,Is_blk4x4_3}) + 4'b1000: //Left top blk4x4 + case (Inter_H_window_counter1) + 3'd4: + if (pos_FracL == `pos_p || pos_FracL == `pos_r) + begin + Inter_H_window_0_2 <= Inter_ref_00_03;Inter_H_window_1_2 <= Inter_ref_01_03; + Inter_H_window_2_2 <= Inter_ref_02_03;Inter_H_window_3_2 <= Inter_ref_03_03; + Inter_H_window_4_2 <= Inter_ref_04_03;Inter_H_window_5_2 <= Inter_ref_05_03; + + Inter_H_window_0_3 <= Inter_ref_00_04;Inter_H_window_1_3 <= Inter_ref_01_04; + Inter_H_window_2_3 <= Inter_ref_02_04;Inter_H_window_3_3 <= Inter_ref_03_04; + Inter_H_window_4_3 <= Inter_ref_04_04;Inter_H_window_5_3 <= Inter_ref_05_04; + + Inter_H_window_0_4 <= Inter_ref_00_05;Inter_H_window_1_4 <= Inter_ref_01_05; + Inter_H_window_2_4 <= Inter_ref_02_05;Inter_H_window_3_4 <= Inter_ref_03_05; + Inter_H_window_4_4 <= Inter_ref_04_05;Inter_H_window_5_4 <= Inter_ref_05_05; + + Inter_H_window_0_5 <= Inter_ref_00_06;Inter_H_window_1_5 <= Inter_ref_01_06; + Inter_H_window_2_5 <= Inter_ref_02_06;Inter_H_window_3_5 <= Inter_ref_03_06; + Inter_H_window_4_5 <= Inter_ref_04_06;Inter_H_window_5_5 <= Inter_ref_05_06; + end + else + begin + Inter_H_window_0_2 <= Inter_ref_00_02;Inter_H_window_1_2 <= Inter_ref_01_02; + Inter_H_window_2_2 <= Inter_ref_02_02;Inter_H_window_3_2 <= Inter_ref_03_02; + Inter_H_window_4_2 <= Inter_ref_04_02;Inter_H_window_5_2 <= Inter_ref_05_02; + + Inter_H_window_0_3 <= Inter_ref_00_03;Inter_H_window_1_3 <= Inter_ref_01_03; + Inter_H_window_2_3 <= Inter_ref_02_03;Inter_H_window_3_3 <= Inter_ref_03_03; + Inter_H_window_4_3 <= Inter_ref_04_03;Inter_H_window_5_3 <= Inter_ref_05_03; + + Inter_H_window_0_4 <= Inter_ref_00_04;Inter_H_window_1_4 <= Inter_ref_01_04; + Inter_H_window_2_4 <= Inter_ref_02_04;Inter_H_window_3_4 <= Inter_ref_03_04; + Inter_H_window_4_4 <= Inter_ref_04_04;Inter_H_window_5_4 <= Inter_ref_05_04; + + Inter_H_window_0_5 <= Inter_ref_00_05;Inter_H_window_1_5 <= Inter_ref_01_05; + Inter_H_window_2_5 <= Inter_ref_02_05;Inter_H_window_3_5 <= Inter_ref_03_05; + Inter_H_window_4_5 <= Inter_ref_04_05;Inter_H_window_5_5 <= Inter_ref_05_05; + end + 3'd3: + if (pos_FracL == `pos_p || pos_FracL == `pos_r) + begin + Inter_H_window_0_2 <= Inter_ref_01_03;Inter_H_window_1_2 <= Inter_ref_02_03; + Inter_H_window_2_2 <= Inter_ref_03_03;Inter_H_window_3_2 <= Inter_ref_04_03; + Inter_H_window_4_2 <= Inter_ref_05_03;Inter_H_window_5_2 <= Inter_ref_06_03; + + Inter_H_window_0_3 <= Inter_ref_01_04;Inter_H_window_1_3 <= Inter_ref_02_04; + Inter_H_window_2_3 <= Inter_ref_03_04;Inter_H_window_3_3 <= Inter_ref_04_04; + Inter_H_window_4_3 <= Inter_ref_05_04;Inter_H_window_5_3 <= Inter_ref_06_04; + + Inter_H_window_0_4 <= Inter_ref_01_05;Inter_H_window_1_4 <= Inter_ref_02_05; + Inter_H_window_2_4 <= Inter_ref_03_05;Inter_H_window_3_4 <= Inter_ref_04_05; + Inter_H_window_4_4 <= Inter_ref_05_05;Inter_H_window_5_4 <= Inter_ref_06_05; + + Inter_H_window_0_5 <= Inter_ref_01_06;Inter_H_window_1_5 <= Inter_ref_02_06; + Inter_H_window_2_5 <= Inter_ref_03_06;Inter_H_window_3_5 <= Inter_ref_04_06; + Inter_H_window_4_5 <= Inter_ref_05_06;Inter_H_window_5_5 <= Inter_ref_06_06; + end + else + begin + Inter_H_window_0_2 <= Inter_ref_01_02;Inter_H_window_1_2 <= Inter_ref_02_02; + Inter_H_window_2_2 <= Inter_ref_03_02;Inter_H_window_3_2 <= Inter_ref_04_02; + Inter_H_window_4_2 <= Inter_ref_05_02;Inter_H_window_5_2 <= Inter_ref_06_02; + + Inter_H_window_0_3 <= Inter_ref_01_03;Inter_H_window_1_3 <= Inter_ref_02_03; + Inter_H_window_2_3 <= Inter_ref_03_03;Inter_H_window_3_3 <= Inter_ref_04_03; + Inter_H_window_4_3 <= Inter_ref_05_03;Inter_H_window_5_3 <= Inter_ref_06_03; + + Inter_H_window_0_4 <= Inter_ref_01_04;Inter_H_window_1_4 <= Inter_ref_02_04; + Inter_H_window_2_4 <= Inter_ref_03_04;Inter_H_window_3_4 <= Inter_ref_04_04; + Inter_H_window_4_4 <= Inter_ref_05_04;Inter_H_window_5_4 <= Inter_ref_06_04; + + Inter_H_window_0_5 <= Inter_ref_01_05;Inter_H_window_1_5 <= Inter_ref_02_05; + Inter_H_window_2_5 <= Inter_ref_03_05;Inter_H_window_3_5 <= Inter_ref_04_05; + Inter_H_window_4_5 <= Inter_ref_05_05;Inter_H_window_5_5 <= Inter_ref_06_05; + end + 3'd2: + if (pos_FracL == `pos_p || pos_FracL == `pos_r) + begin + Inter_H_window_0_2 <= Inter_ref_02_03;Inter_H_window_1_2 <= Inter_ref_03_03; + Inter_H_window_2_2 <= Inter_ref_04_03;Inter_H_window_3_2 <= Inter_ref_05_03; + Inter_H_window_4_2 <= Inter_ref_06_03;Inter_H_window_5_2 <= Inter_ref_07_03; + + Inter_H_window_0_3 <= Inter_ref_02_04;Inter_H_window_1_3 <= Inter_ref_03_04; + Inter_H_window_2_3 <= Inter_ref_04_04;Inter_H_window_3_3 <= Inter_ref_05_04; + Inter_H_window_4_3 <= Inter_ref_06_04;Inter_H_window_5_3 <= Inter_ref_07_04; + + Inter_H_window_0_4 <= Inter_ref_02_05;Inter_H_window_1_4 <= Inter_ref_03_05; + Inter_H_window_2_4 <= Inter_ref_04_05;Inter_H_window_3_4 <= Inter_ref_05_05; + Inter_H_window_4_4 <= Inter_ref_06_05;Inter_H_window_5_4 <= Inter_ref_07_05; + + Inter_H_window_0_5 <= Inter_ref_02_06;Inter_H_window_1_5 <= Inter_ref_03_06; + Inter_H_window_2_5 <= Inter_ref_04_06;Inter_H_window_3_5 <= Inter_ref_05_06; + Inter_H_window_4_5 <= Inter_ref_06_06;Inter_H_window_5_5 <= Inter_ref_07_06; + end + else + begin + Inter_H_window_0_2 <= Inter_ref_02_02;Inter_H_window_1_2 <= Inter_ref_03_02; + Inter_H_window_2_2 <= Inter_ref_04_02;Inter_H_window_3_2 <= Inter_ref_05_02; + Inter_H_window_4_2 <= Inter_ref_06_02;Inter_H_window_5_2 <= Inter_ref_07_02; + + Inter_H_window_0_3 <= Inter_ref_02_03;Inter_H_window_1_3 <= Inter_ref_03_03; + Inter_H_window_2_3 <= Inter_ref_04_03;Inter_H_window_3_3 <= Inter_ref_05_03; + Inter_H_window_4_3 <= Inter_ref_06_03;Inter_H_window_5_3 <= Inter_ref_07_03; + + Inter_H_window_0_4 <= Inter_ref_02_04;Inter_H_window_1_4 <= Inter_ref_03_04; + Inter_H_window_2_4 <= Inter_ref_04_04;Inter_H_window_3_4 <= Inter_ref_05_04; + Inter_H_window_4_4 <= Inter_ref_06_04;Inter_H_window_5_4 <= Inter_ref_07_04; + + Inter_H_window_0_5 <= Inter_ref_02_05;Inter_H_window_1_5 <= Inter_ref_03_05; + Inter_H_window_2_5 <= Inter_ref_04_05;Inter_H_window_3_5 <= Inter_ref_05_05; + Inter_H_window_4_5 <= Inter_ref_06_05;Inter_H_window_5_5 <= Inter_ref_07_05; + end + 3'd1: + if (pos_FracL == `pos_p || pos_FracL == `pos_r) + begin + Inter_H_window_0_2 <= Inter_ref_03_03;Inter_H_window_1_2 <= Inter_ref_04_03; + Inter_H_window_2_2 <= Inter_ref_05_03;Inter_H_window_3_2 <= Inter_ref_06_03; + Inter_H_window_4_2 <= Inter_ref_07_03;Inter_H_window_5_2 <= Inter_ref_08_03; + + Inter_H_window_0_3 <= Inter_ref_03_04;Inter_H_window_1_3 <= Inter_ref_04_04; + Inter_H_window_2_3 <= Inter_ref_05_04;Inter_H_window_3_3 <= Inter_ref_06_04; + Inter_H_window_4_3 <= Inter_ref_07_04;Inter_H_window_5_3 <= Inter_ref_08_04; + + Inter_H_window_0_4 <= Inter_ref_03_05;Inter_H_window_1_4 <= Inter_ref_04_05; + Inter_H_window_2_4 <= Inter_ref_05_05;Inter_H_window_3_4 <= Inter_ref_06_05; + Inter_H_window_4_4 <= Inter_ref_07_05;Inter_H_window_5_4 <= Inter_ref_08_05; + + Inter_H_window_0_5 <= Inter_ref_03_06;Inter_H_window_1_5 <= Inter_ref_04_06; + Inter_H_window_2_5 <= Inter_ref_05_06;Inter_H_window_3_5 <= Inter_ref_06_06; + Inter_H_window_4_5 <= Inter_ref_07_06;Inter_H_window_5_5 <= Inter_ref_08_06; + end + else + begin + Inter_H_window_0_2 <= Inter_ref_03_02;Inter_H_window_1_2 <= Inter_ref_04_02; + Inter_H_window_2_2 <= Inter_ref_05_02;Inter_H_window_3_2 <= Inter_ref_06_02; + Inter_H_window_4_2 <= Inter_ref_07_02;Inter_H_window_5_2 <= Inter_ref_08_02; + + Inter_H_window_0_3 <= Inter_ref_03_03;Inter_H_window_1_3 <= Inter_ref_04_03; + Inter_H_window_2_3 <= Inter_ref_05_03;Inter_H_window_3_3 <= Inter_ref_06_03; + Inter_H_window_4_3 <= Inter_ref_07_03;Inter_H_window_5_3 <= Inter_ref_08_03; + + Inter_H_window_0_4 <= Inter_ref_03_04;Inter_H_window_1_4 <= Inter_ref_04_04; + Inter_H_window_2_4 <= Inter_ref_05_04;Inter_H_window_3_4 <= Inter_ref_06_04; + Inter_H_window_4_4 <= Inter_ref_07_04;Inter_H_window_5_4 <= Inter_ref_08_04; + + Inter_H_window_0_5 <= Inter_ref_03_05;Inter_H_window_1_5 <= Inter_ref_04_05; + Inter_H_window_2_5 <= Inter_ref_05_05;Inter_H_window_3_5 <= Inter_ref_06_05; + Inter_H_window_4_5 <= Inter_ref_07_05;Inter_H_window_5_5 <= Inter_ref_08_05; + end + default: + begin + Inter_H_window_0_2 <= 0;Inter_H_window_1_2 <= 0;Inter_H_window_2_2 <= 0; + Inter_H_window_3_2 <= 0;Inter_H_window_4_2 <= 0;Inter_H_window_5_2 <= 0; + + Inter_H_window_0_3 <= 0;Inter_H_window_1_3 <= 0;Inter_H_window_2_3 <= 0; + Inter_H_window_3_3 <= 0;Inter_H_window_4_3 <= 0;Inter_H_window_5_3 <= 0; + + Inter_H_window_0_4 <= 0;Inter_H_window_1_4 <= 0;Inter_H_window_2_4 <= 0; + Inter_H_window_3_4 <= 0;Inter_H_window_4_4 <= 0;Inter_H_window_5_4 <= 0; + + Inter_H_window_0_5 <= 0;Inter_H_window_1_5 <= 0;Inter_H_window_2_5 <= 0; + Inter_H_window_3_5 <= 0;Inter_H_window_4_5 <= 0;Inter_H_window_5_5 <= 0; + end + endcase + 4'b0100: //Right top blk4x4 + case (Inter_H_window_counter1) + 3'd4: + if (pos_FracL == `pos_p || pos_FracL == `pos_r) + begin + Inter_H_window_0_2 <= Inter_ref_04_03;Inter_H_window_1_2 <= Inter_ref_05_03; + Inter_H_window_2_2 <= Inter_ref_06_03;Inter_H_window_3_2 <= Inter_ref_07_03; + Inter_H_window_4_2 <= Inter_ref_08_03;Inter_H_window_5_2 <= Inter_ref_09_03; + + Inter_H_window_0_3 <= Inter_ref_04_04;Inter_H_window_1_3 <= Inter_ref_05_04; + Inter_H_window_2_3 <= Inter_ref_06_04;Inter_H_window_3_3 <= Inter_ref_07_04; + Inter_H_window_4_3 <= Inter_ref_08_04;Inter_H_window_5_3 <= Inter_ref_09_04; + + Inter_H_window_0_4 <= Inter_ref_04_05;Inter_H_window_1_4 <= Inter_ref_05_05; + Inter_H_window_2_4 <= Inter_ref_06_05;Inter_H_window_3_4 <= Inter_ref_07_05; + Inter_H_window_4_4 <= Inter_ref_08_05;Inter_H_window_5_4 <= Inter_ref_09_05; + + Inter_H_window_0_5 <= Inter_ref_04_06;Inter_H_window_1_5 <= Inter_ref_05_06; + Inter_H_window_2_5 <= Inter_ref_06_06;Inter_H_window_3_5 <= Inter_ref_07_06; + Inter_H_window_4_5 <= Inter_ref_08_06;Inter_H_window_5_5 <= Inter_ref_09_06; + end + else + begin + Inter_H_window_0_2 <= Inter_ref_04_02;Inter_H_window_1_2 <= Inter_ref_05_02; + Inter_H_window_2_2 <= Inter_ref_06_02;Inter_H_window_3_2 <= Inter_ref_07_02; + Inter_H_window_4_2 <= Inter_ref_08_02;Inter_H_window_5_2 <= Inter_ref_09_02; + + Inter_H_window_0_3 <= Inter_ref_04_03;Inter_H_window_1_3 <= Inter_ref_05_03; + Inter_H_window_2_3 <= Inter_ref_06_03;Inter_H_window_3_3 <= Inter_ref_07_03; + Inter_H_window_4_3 <= Inter_ref_08_03;Inter_H_window_5_3 <= Inter_ref_09_03; + + Inter_H_window_0_4 <= Inter_ref_04_04;Inter_H_window_1_4 <= Inter_ref_05_04; + Inter_H_window_2_4 <= Inter_ref_06_04;Inter_H_window_3_4 <= Inter_ref_07_04; + Inter_H_window_4_4 <= Inter_ref_08_04;Inter_H_window_5_4 <= Inter_ref_09_04; + + Inter_H_window_0_5 <= Inter_ref_04_05;Inter_H_window_1_5 <= Inter_ref_05_05; + Inter_H_window_2_5 <= Inter_ref_06_05;Inter_H_window_3_5 <= Inter_ref_07_05; + Inter_H_window_4_5 <= Inter_ref_08_05;Inter_H_window_5_5 <= Inter_ref_09_05; + end + 3'd3: + if (pos_FracL == `pos_p || pos_FracL == `pos_r) + begin + Inter_H_window_0_2 <= Inter_ref_05_03;Inter_H_window_1_2 <= Inter_ref_06_03; + Inter_H_window_2_2 <= Inter_ref_07_03;Inter_H_window_3_2 <= Inter_ref_08_03; + Inter_H_window_4_2 <= Inter_ref_09_03;Inter_H_window_5_2 <= Inter_ref_10_03; + + Inter_H_window_0_3 <= Inter_ref_05_04;Inter_H_window_1_3 <= Inter_ref_06_04; + Inter_H_window_2_3 <= Inter_ref_07_04;Inter_H_window_3_3 <= Inter_ref_08_04; + Inter_H_window_4_3 <= Inter_ref_09_04;Inter_H_window_5_3 <= Inter_ref_10_04; + + Inter_H_window_0_4 <= Inter_ref_05_05;Inter_H_window_1_4 <= Inter_ref_06_05; + Inter_H_window_2_4 <= Inter_ref_07_05;Inter_H_window_3_4 <= Inter_ref_08_05; + Inter_H_window_4_4 <= Inter_ref_09_05;Inter_H_window_5_4 <= Inter_ref_10_05; + + Inter_H_window_0_5 <= Inter_ref_05_06;Inter_H_window_1_5 <= Inter_ref_06_06; + Inter_H_window_2_5 <= Inter_ref_07_06;Inter_H_window_3_5 <= Inter_ref_08_06; + Inter_H_window_4_5 <= Inter_ref_09_06;Inter_H_window_5_5 <= Inter_ref_10_06; + end + else + begin + Inter_H_window_0_2 <= Inter_ref_05_02;Inter_H_window_1_2 <= Inter_ref_06_02; + Inter_H_window_2_2 <= Inter_ref_07_02;Inter_H_window_3_2 <= Inter_ref_08_02; + Inter_H_window_4_2 <= Inter_ref_09_02;Inter_H_window_5_2 <= Inter_ref_10_02; + + Inter_H_window_0_3 <= Inter_ref_05_03;Inter_H_window_1_3 <= Inter_ref_06_03; + Inter_H_window_2_3 <= Inter_ref_07_03;Inter_H_window_3_3 <= Inter_ref_08_03; + Inter_H_window_4_3 <= Inter_ref_09_03;Inter_H_window_5_3 <= Inter_ref_10_03; + + Inter_H_window_0_4 <= Inter_ref_05_04;Inter_H_window_1_4 <= Inter_ref_06_04; + Inter_H_window_2_4 <= Inter_ref_07_04;Inter_H_window_3_4 <= Inter_ref_08_04; + Inter_H_window_4_4 <= Inter_ref_09_04;Inter_H_window_5_4 <= Inter_ref_10_04; + + Inter_H_window_0_5 <= Inter_ref_05_05;Inter_H_window_1_5 <= Inter_ref_06_05; + Inter_H_window_2_5 <= Inter_ref_07_05;Inter_H_window_3_5 <= Inter_ref_08_05; + Inter_H_window_4_5 <= Inter_ref_09_05;Inter_H_window_5_5 <= Inter_ref_10_05; + end + 3'd2: + if (pos_FracL == `pos_p || pos_FracL == `pos_r) + begin + Inter_H_window_0_2 <= Inter_ref_06_03;Inter_H_window_1_2 <= Inter_ref_07_03; + Inter_H_window_2_2 <= Inter_ref_08_03;Inter_H_window_3_2 <= Inter_ref_09_03; + Inter_H_window_4_2 <= Inter_ref_10_03;Inter_H_window_5_2 <= Inter_ref_11_03; + + Inter_H_window_0_3 <= Inter_ref_06_04;Inter_H_window_1_3 <= Inter_ref_07_04; + Inter_H_window_2_3 <= Inter_ref_08_04;Inter_H_window_3_3 <= Inter_ref_09_04; + Inter_H_window_4_3 <= Inter_ref_10_04;Inter_H_window_5_3 <= Inter_ref_11_04; + + Inter_H_window_0_4 <= Inter_ref_06_05;Inter_H_window_1_4 <= Inter_ref_07_05; + Inter_H_window_2_4 <= Inter_ref_08_05;Inter_H_window_3_4 <= Inter_ref_09_05; + Inter_H_window_4_4 <= Inter_ref_10_05;Inter_H_window_5_4 <= Inter_ref_11_05; + + Inter_H_window_0_5 <= Inter_ref_06_06;Inter_H_window_1_5 <= Inter_ref_07_06; + Inter_H_window_2_5 <= Inter_ref_08_06;Inter_H_window_3_5 <= Inter_ref_09_06; + Inter_H_window_4_5 <= Inter_ref_10_06;Inter_H_window_5_5 <= Inter_ref_11_06; + end + else + begin + Inter_H_window_0_2 <= Inter_ref_06_02;Inter_H_window_1_2 <= Inter_ref_07_02; + Inter_H_window_2_2 <= Inter_ref_08_02;Inter_H_window_3_2 <= Inter_ref_09_02; + Inter_H_window_4_2 <= Inter_ref_10_02;Inter_H_window_5_2 <= Inter_ref_11_02; + + Inter_H_window_0_3 <= Inter_ref_06_03;Inter_H_window_1_3 <= Inter_ref_07_03; + Inter_H_window_2_3 <= Inter_ref_08_03;Inter_H_window_3_3 <= Inter_ref_09_03; + Inter_H_window_4_3 <= Inter_ref_10_03;Inter_H_window_5_3 <= Inter_ref_11_03; + + Inter_H_window_0_4 <= Inter_ref_06_04;Inter_H_window_1_4 <= Inter_ref_07_04; + Inter_H_window_2_4 <= Inter_ref_08_04;Inter_H_window_3_4 <= Inter_ref_09_04; + Inter_H_window_4_4 <= Inter_ref_10_04;Inter_H_window_5_4 <= Inter_ref_11_04; + + Inter_H_window_0_5 <= Inter_ref_06_05;Inter_H_window_1_5 <= Inter_ref_07_05; + Inter_H_window_2_5 <= Inter_ref_08_05;Inter_H_window_3_5 <= Inter_ref_09_05; + Inter_H_window_4_5 <= Inter_ref_10_05;Inter_H_window_5_5 <= Inter_ref_11_05; + end + 3'd1: + if (pos_FracL == `pos_p || pos_FracL == `pos_r) + begin + Inter_H_window_0_2 <= Inter_ref_07_03;Inter_H_window_1_2 <= Inter_ref_08_03; + Inter_H_window_2_2 <= Inter_ref_09_03;Inter_H_window_3_2 <= Inter_ref_10_03; + Inter_H_window_4_2 <= Inter_ref_11_03;Inter_H_window_5_2 <= Inter_ref_12_03; + + Inter_H_window_0_3 <= Inter_ref_07_04;Inter_H_window_1_3 <= Inter_ref_08_04; + Inter_H_window_2_3 <= Inter_ref_09_04;Inter_H_window_3_3 <= Inter_ref_10_04; + Inter_H_window_4_3 <= Inter_ref_11_04;Inter_H_window_5_3 <= Inter_ref_12_04; + + Inter_H_window_0_4 <= Inter_ref_07_05;Inter_H_window_1_4 <= Inter_ref_08_05; + Inter_H_window_2_4 <= Inter_ref_09_05;Inter_H_window_3_4 <= Inter_ref_10_05; + Inter_H_window_4_4 <= Inter_ref_11_05;Inter_H_window_5_4 <= Inter_ref_12_05; + + Inter_H_window_0_5 <= Inter_ref_07_06;Inter_H_window_1_5 <= Inter_ref_08_06; + Inter_H_window_2_5 <= Inter_ref_09_06;Inter_H_window_3_5 <= Inter_ref_10_06; + Inter_H_window_4_5 <= Inter_ref_11_06;Inter_H_window_5_5 <= Inter_ref_12_06; + end + else + begin + Inter_H_window_0_2 <= Inter_ref_07_02;Inter_H_window_1_2 <= Inter_ref_08_02; + Inter_H_window_2_2 <= Inter_ref_09_02;Inter_H_window_3_2 <= Inter_ref_10_02; + Inter_H_window_4_2 <= Inter_ref_11_02;Inter_H_window_5_2 <= Inter_ref_12_02; + + Inter_H_window_0_3 <= Inter_ref_07_03;Inter_H_window_1_3 <= Inter_ref_08_03; + Inter_H_window_2_3 <= Inter_ref_09_03;Inter_H_window_3_3 <= Inter_ref_10_03; + Inter_H_window_4_3 <= Inter_ref_11_03;Inter_H_window_5_3 <= Inter_ref_12_03; + + Inter_H_window_0_4 <= Inter_ref_07_04;Inter_H_window_1_4 <= Inter_ref_08_04; + Inter_H_window_2_4 <= Inter_ref_09_04;Inter_H_window_3_4 <= Inter_ref_10_04; + Inter_H_window_4_4 <= Inter_ref_11_04;Inter_H_window_5_4 <= Inter_ref_12_04; + + Inter_H_window_0_5 <= Inter_ref_07_05;Inter_H_window_1_5 <= Inter_ref_08_05; + Inter_H_window_2_5 <= Inter_ref_09_05;Inter_H_window_3_5 <= Inter_ref_10_05; + Inter_H_window_4_5 <= Inter_ref_11_05;Inter_H_window_5_5 <= Inter_ref_12_05; + end + default: + begin + Inter_H_window_0_2 <= 0;Inter_H_window_1_2 <= 0;Inter_H_window_2_2 <= 0; + Inter_H_window_3_2 <= 0;Inter_H_window_4_2 <= 0;Inter_H_window_5_2 <= 0; + + Inter_H_window_0_3 <= 0;Inter_H_window_1_3 <= 0;Inter_H_window_2_3 <= 0; + Inter_H_window_3_3 <= 0;Inter_H_window_4_3 <= 0;Inter_H_window_5_3 <= 0; + + Inter_H_window_0_4 <= 0;Inter_H_window_1_4 <= 0;Inter_H_window_2_4 <= 0; + Inter_H_window_3_4 <= 0;Inter_H_window_4_4 <= 0;Inter_H_window_5_4 <= 0; + + Inter_H_window_0_5 <= 0;Inter_H_window_1_5 <= 0;Inter_H_window_2_5 <= 0; + Inter_H_window_3_5 <= 0;Inter_H_window_4_5 <= 0;Inter_H_window_5_5 <= 0; + end + endcase + 4'b0010: //Left bottom blk4x4 + case (Inter_H_window_counter1) + 3'd4: + if (pos_FracL == `pos_p || pos_FracL == `pos_r) + begin + Inter_H_window_0_2 <= Inter_ref_00_07;Inter_H_window_1_2 <= Inter_ref_01_07; + Inter_H_window_2_2 <= Inter_ref_02_07;Inter_H_window_3_2 <= Inter_ref_03_07; + Inter_H_window_4_2 <= Inter_ref_04_07;Inter_H_window_5_2 <= Inter_ref_05_07; + + Inter_H_window_0_3 <= Inter_ref_00_08;Inter_H_window_1_3 <= Inter_ref_01_08; + Inter_H_window_2_3 <= Inter_ref_02_08;Inter_H_window_3_3 <= Inter_ref_03_08; + Inter_H_window_4_3 <= Inter_ref_04_08;Inter_H_window_5_3 <= Inter_ref_05_08; + + Inter_H_window_0_4 <= Inter_ref_00_09;Inter_H_window_1_4 <= Inter_ref_01_09; + Inter_H_window_2_4 <= Inter_ref_02_09;Inter_H_window_3_4 <= Inter_ref_03_09; + Inter_H_window_4_4 <= Inter_ref_04_09;Inter_H_window_5_4 <= Inter_ref_05_09; + + Inter_H_window_0_5 <= Inter_ref_00_10;Inter_H_window_1_5 <= Inter_ref_01_10; + Inter_H_window_2_5 <= Inter_ref_02_10;Inter_H_window_3_5 <= Inter_ref_03_10; + Inter_H_window_4_5 <= Inter_ref_04_10;Inter_H_window_5_5 <= Inter_ref_05_10; + end + else + begin + Inter_H_window_0_2 <= Inter_ref_00_06;Inter_H_window_1_2 <= Inter_ref_01_06; + Inter_H_window_2_2 <= Inter_ref_02_06;Inter_H_window_3_2 <= Inter_ref_03_06; + Inter_H_window_4_2 <= Inter_ref_04_06;Inter_H_window_5_2 <= Inter_ref_05_06; + + Inter_H_window_0_3 <= Inter_ref_00_07;Inter_H_window_1_3 <= Inter_ref_01_07; + Inter_H_window_2_3 <= Inter_ref_02_07;Inter_H_window_3_3 <= Inter_ref_03_07; + Inter_H_window_4_3 <= Inter_ref_04_07;Inter_H_window_5_3 <= Inter_ref_05_07; + + Inter_H_window_0_4 <= Inter_ref_00_08;Inter_H_window_1_4 <= Inter_ref_01_08; + Inter_H_window_2_4 <= Inter_ref_02_08;Inter_H_window_3_4 <= Inter_ref_03_08; + Inter_H_window_4_4 <= Inter_ref_04_08;Inter_H_window_5_4 <= Inter_ref_05_08; + + Inter_H_window_0_5 <= Inter_ref_00_09;Inter_H_window_1_5 <= Inter_ref_01_09; + Inter_H_window_2_5 <= Inter_ref_02_09;Inter_H_window_3_5 <= Inter_ref_03_09; + Inter_H_window_4_5 <= Inter_ref_04_09;Inter_H_window_5_5 <= Inter_ref_05_09; + end + 3'd3: + if (pos_FracL == `pos_p || pos_FracL == `pos_r) + begin + Inter_H_window_0_2 <= Inter_ref_01_07;Inter_H_window_1_2 <= Inter_ref_02_07; + Inter_H_window_2_2 <= Inter_ref_03_07;Inter_H_window_3_2 <= Inter_ref_04_07; + Inter_H_window_4_2 <= Inter_ref_05_07;Inter_H_window_5_2 <= Inter_ref_06_07; + + Inter_H_window_0_3 <= Inter_ref_01_08;Inter_H_window_1_3 <= Inter_ref_02_08; + Inter_H_window_2_3 <= Inter_ref_03_08;Inter_H_window_3_3 <= Inter_ref_04_08; + Inter_H_window_4_3 <= Inter_ref_05_08;Inter_H_window_5_3 <= Inter_ref_06_08; + + Inter_H_window_0_4 <= Inter_ref_01_09;Inter_H_window_1_4 <= Inter_ref_02_09; + Inter_H_window_2_4 <= Inter_ref_03_09;Inter_H_window_3_4 <= Inter_ref_04_09; + Inter_H_window_4_4 <= Inter_ref_05_09;Inter_H_window_5_4 <= Inter_ref_06_09; + + Inter_H_window_0_5 <= Inter_ref_01_10;Inter_H_window_1_5 <= Inter_ref_02_10; + Inter_H_window_2_5 <= Inter_ref_03_10;Inter_H_window_3_5 <= Inter_ref_04_10; + Inter_H_window_4_5 <= Inter_ref_05_10;Inter_H_window_5_5 <= Inter_ref_06_10; + end + else + begin + Inter_H_window_0_2 <= Inter_ref_01_06;Inter_H_window_1_2 <= Inter_ref_02_06; + Inter_H_window_2_2 <= Inter_ref_03_06;Inter_H_window_3_2 <= Inter_ref_04_06; + Inter_H_window_4_2 <= Inter_ref_05_06;Inter_H_window_5_2 <= Inter_ref_06_06; + + Inter_H_window_0_3 <= Inter_ref_01_07;Inter_H_window_1_3 <= Inter_ref_02_07; + Inter_H_window_2_3 <= Inter_ref_03_07;Inter_H_window_3_3 <= Inter_ref_04_07; + Inter_H_window_4_3 <= Inter_ref_05_07;Inter_H_window_5_3 <= Inter_ref_06_07; + + Inter_H_window_0_4 <= Inter_ref_01_08;Inter_H_window_1_4 <= Inter_ref_02_08; + Inter_H_window_2_4 <= Inter_ref_03_08;Inter_H_window_3_4 <= Inter_ref_04_08; + Inter_H_window_4_4 <= Inter_ref_05_08;Inter_H_window_5_4 <= Inter_ref_06_08; + + Inter_H_window_0_5 <= Inter_ref_01_09;Inter_H_window_1_5 <= Inter_ref_02_09; + Inter_H_window_2_5 <= Inter_ref_03_09;Inter_H_window_3_5 <= Inter_ref_04_09; + Inter_H_window_4_5 <= Inter_ref_05_09;Inter_H_window_5_5 <= Inter_ref_06_09; + end + 3'd2: + if (pos_FracL == `pos_p || pos_FracL == `pos_r) + begin + Inter_H_window_0_2 <= Inter_ref_02_07;Inter_H_window_1_2 <= Inter_ref_03_07; + Inter_H_window_2_2 <= Inter_ref_04_07;Inter_H_window_3_2 <= Inter_ref_05_07; + Inter_H_window_4_2 <= Inter_ref_06_07;Inter_H_window_5_2 <= Inter_ref_07_07; + + Inter_H_window_0_3 <= Inter_ref_02_08;Inter_H_window_1_3 <= Inter_ref_03_08; + Inter_H_window_2_3 <= Inter_ref_04_08;Inter_H_window_3_3 <= Inter_ref_05_08; + Inter_H_window_4_3 <= Inter_ref_06_08;Inter_H_window_5_3 <= Inter_ref_07_08; + + Inter_H_window_0_4 <= Inter_ref_02_09;Inter_H_window_1_4 <= Inter_ref_03_09; + Inter_H_window_2_4 <= Inter_ref_04_09;Inter_H_window_3_4 <= Inter_ref_05_09; + Inter_H_window_4_4 <= Inter_ref_06_09;Inter_H_window_5_4 <= Inter_ref_07_09; + + Inter_H_window_0_5 <= Inter_ref_02_10;Inter_H_window_1_5 <= Inter_ref_03_10; + Inter_H_window_2_5 <= Inter_ref_04_10;Inter_H_window_3_5 <= Inter_ref_05_10; + Inter_H_window_4_5 <= Inter_ref_06_10;Inter_H_window_5_5 <= Inter_ref_07_10; + end + else + begin + Inter_H_window_0_2 <= Inter_ref_02_06;Inter_H_window_1_2 <= Inter_ref_03_06; + Inter_H_window_2_2 <= Inter_ref_04_06;Inter_H_window_3_2 <= Inter_ref_05_06; + Inter_H_window_4_2 <= Inter_ref_06_06;Inter_H_window_5_2 <= Inter_ref_07_06; + + Inter_H_window_0_3 <= Inter_ref_02_07;Inter_H_window_1_3 <= Inter_ref_03_07; + Inter_H_window_2_3 <= Inter_ref_04_07;Inter_H_window_3_3 <= Inter_ref_05_07; + Inter_H_window_4_3 <= Inter_ref_06_07;Inter_H_window_5_3 <= Inter_ref_07_07; + + Inter_H_window_0_4 <= Inter_ref_02_08;Inter_H_window_1_4 <= Inter_ref_03_08; + Inter_H_window_2_4 <= Inter_ref_04_08;Inter_H_window_3_4 <= Inter_ref_05_08; + Inter_H_window_4_4 <= Inter_ref_06_08;Inter_H_window_5_4 <= Inter_ref_07_08; + + Inter_H_window_0_5 <= Inter_ref_02_09;Inter_H_window_1_5 <= Inter_ref_03_09; + Inter_H_window_2_5 <= Inter_ref_04_09;Inter_H_window_3_5 <= Inter_ref_05_09; + Inter_H_window_4_5 <= Inter_ref_06_09;Inter_H_window_5_5 <= Inter_ref_07_09; + end + 3'd1: + if (pos_FracL == `pos_p || pos_FracL == `pos_r) + begin + Inter_H_window_0_2 <= Inter_ref_03_07;Inter_H_window_1_2 <= Inter_ref_04_07; + Inter_H_window_2_2 <= Inter_ref_05_07;Inter_H_window_3_2 <= Inter_ref_06_07; + Inter_H_window_4_2 <= Inter_ref_07_07;Inter_H_window_5_2 <= Inter_ref_08_07; + + Inter_H_window_0_3 <= Inter_ref_03_08;Inter_H_window_1_3 <= Inter_ref_04_08; + Inter_H_window_2_3 <= Inter_ref_05_08;Inter_H_window_3_3 <= Inter_ref_06_08; + Inter_H_window_4_3 <= Inter_ref_07_08;Inter_H_window_5_3 <= Inter_ref_08_08; + + Inter_H_window_0_4 <= Inter_ref_03_09;Inter_H_window_1_4 <= Inter_ref_04_09; + Inter_H_window_2_4 <= Inter_ref_05_09;Inter_H_window_3_4 <= Inter_ref_06_09; + Inter_H_window_4_4 <= Inter_ref_07_09;Inter_H_window_5_4 <= Inter_ref_08_09; + + Inter_H_window_0_5 <= Inter_ref_03_10;Inter_H_window_1_5 <= Inter_ref_04_10; + Inter_H_window_2_5 <= Inter_ref_05_10;Inter_H_window_3_5 <= Inter_ref_06_10; + Inter_H_window_4_5 <= Inter_ref_07_10;Inter_H_window_5_5 <= Inter_ref_08_10; + end + else + begin + Inter_H_window_0_2 <= Inter_ref_03_06;Inter_H_window_1_2 <= Inter_ref_04_06; + Inter_H_window_2_2 <= Inter_ref_05_06;Inter_H_window_3_2 <= Inter_ref_06_06; + Inter_H_window_4_2 <= Inter_ref_07_06;Inter_H_window_5_2 <= Inter_ref_08_06; + + Inter_H_window_0_3 <= Inter_ref_03_07;Inter_H_window_1_3 <= Inter_ref_04_07; + Inter_H_window_2_3 <= Inter_ref_05_07;Inter_H_window_3_3 <= Inter_ref_06_07; + Inter_H_window_4_3 <= Inter_ref_07_07;Inter_H_window_5_3 <= Inter_ref_08_07; + + Inter_H_window_0_4 <= Inter_ref_03_08;Inter_H_window_1_4 <= Inter_ref_04_08; + Inter_H_window_2_4 <= Inter_ref_05_08;Inter_H_window_3_4 <= Inter_ref_06_08; + Inter_H_window_4_4 <= Inter_ref_07_08;Inter_H_window_5_4 <= Inter_ref_08_08; + + Inter_H_window_0_5 <= Inter_ref_03_09;Inter_H_window_1_5 <= Inter_ref_04_09; + Inter_H_window_2_5 <= Inter_ref_05_09;Inter_H_window_3_5 <= Inter_ref_06_09; + Inter_H_window_4_5 <= Inter_ref_07_09;Inter_H_window_5_5 <= Inter_ref_08_09; + end + default: + begin + Inter_H_window_0_2 <= 0;Inter_H_window_1_2 <= 0;Inter_H_window_2_2 <= 0; + Inter_H_window_3_2 <= 0;Inter_H_window_4_2 <= 0;Inter_H_window_5_2 <= 0; + + Inter_H_window_0_3 <= 0;Inter_H_window_1_3 <= 0;Inter_H_window_2_3 <= 0; + Inter_H_window_3_3 <= 0;Inter_H_window_4_3 <= 0;Inter_H_window_5_3 <= 0; + + Inter_H_window_0_4 <= 0;Inter_H_window_1_4 <= 0;Inter_H_window_2_4 <= 0; + Inter_H_window_3_4 <= 0;Inter_H_window_4_4 <= 0;Inter_H_window_5_4 <= 0; + + Inter_H_window_0_5 <= 0;Inter_H_window_1_5 <= 0;Inter_H_window_2_5 <= 0; + Inter_H_window_3_5 <= 0;Inter_H_window_4_5 <= 0;Inter_H_window_5_5 <= 0; + end + endcase + 4'b0001: //Right bottom blk4x4 + case (Inter_H_window_counter1) + 3'd4: + if (pos_FracL == `pos_p || pos_FracL == `pos_r) + begin + Inter_H_window_0_2 <= Inter_ref_04_07;Inter_H_window_1_2 <= Inter_ref_05_07; + Inter_H_window_2_2 <= Inter_ref_06_07;Inter_H_window_3_2 <= Inter_ref_07_07; + Inter_H_window_4_2 <= Inter_ref_08_07;Inter_H_window_5_2 <= Inter_ref_09_07; + + Inter_H_window_0_3 <= Inter_ref_04_08;Inter_H_window_1_3 <= Inter_ref_05_08; + Inter_H_window_2_3 <= Inter_ref_06_08;Inter_H_window_3_3 <= Inter_ref_07_08; + Inter_H_window_4_3 <= Inter_ref_08_08;Inter_H_window_5_3 <= Inter_ref_09_08; + + Inter_H_window_0_4 <= Inter_ref_04_09;Inter_H_window_1_4 <= Inter_ref_05_09; + Inter_H_window_2_4 <= Inter_ref_06_09;Inter_H_window_3_4 <= Inter_ref_07_09; + Inter_H_window_4_4 <= Inter_ref_08_09;Inter_H_window_5_4 <= Inter_ref_09_09; + + Inter_H_window_0_5 <= Inter_ref_04_10;Inter_H_window_1_5 <= Inter_ref_05_10; + Inter_H_window_2_5 <= Inter_ref_06_10;Inter_H_window_3_5 <= Inter_ref_07_10; + Inter_H_window_4_5 <= Inter_ref_08_10;Inter_H_window_5_5 <= Inter_ref_09_10; + end + else + begin + Inter_H_window_0_2 <= Inter_ref_04_06;Inter_H_window_1_2 <= Inter_ref_05_06; + Inter_H_window_2_2 <= Inter_ref_06_06;Inter_H_window_3_2 <= Inter_ref_07_06; + Inter_H_window_4_2 <= Inter_ref_08_06;Inter_H_window_5_2 <= Inter_ref_09_06; + + Inter_H_window_0_3 <= Inter_ref_04_07;Inter_H_window_1_3 <= Inter_ref_05_07; + Inter_H_window_2_3 <= Inter_ref_06_07;Inter_H_window_3_3 <= Inter_ref_07_07; + Inter_H_window_4_3 <= Inter_ref_08_07;Inter_H_window_5_3 <= Inter_ref_09_07; + + Inter_H_window_0_4 <= Inter_ref_04_08;Inter_H_window_1_4 <= Inter_ref_05_08; + Inter_H_window_2_4 <= Inter_ref_06_08;Inter_H_window_3_4 <= Inter_ref_07_08; + Inter_H_window_4_4 <= Inter_ref_08_08;Inter_H_window_5_4 <= Inter_ref_09_08; + + Inter_H_window_0_5 <= Inter_ref_04_09;Inter_H_window_1_5 <= Inter_ref_05_09; + Inter_H_window_2_5 <= Inter_ref_06_09;Inter_H_window_3_5 <= Inter_ref_07_09; + Inter_H_window_4_5 <= Inter_ref_08_09;Inter_H_window_5_5 <= Inter_ref_09_09; + end + 3'd3: + if (pos_FracL == `pos_p || pos_FracL == `pos_r) + begin + Inter_H_window_0_2 <= Inter_ref_05_07;Inter_H_window_1_2 <= Inter_ref_06_07; + Inter_H_window_2_2 <= Inter_ref_07_07;Inter_H_window_3_2 <= Inter_ref_08_07; + Inter_H_window_4_2 <= Inter_ref_09_07;Inter_H_window_5_2 <= Inter_ref_10_07; + + Inter_H_window_0_3 <= Inter_ref_05_08;Inter_H_window_1_3 <= Inter_ref_06_08; + Inter_H_window_2_3 <= Inter_ref_07_08;Inter_H_window_3_3 <= Inter_ref_08_08; + Inter_H_window_4_3 <= Inter_ref_09_08;Inter_H_window_5_3 <= Inter_ref_10_08; + + Inter_H_window_0_4 <= Inter_ref_05_09;Inter_H_window_1_4 <= Inter_ref_06_09; + Inter_H_window_2_4 <= Inter_ref_07_09;Inter_H_window_3_4 <= Inter_ref_08_09; + Inter_H_window_4_4 <= Inter_ref_09_09;Inter_H_window_5_4 <= Inter_ref_10_09; + + Inter_H_window_0_5 <= Inter_ref_05_10;Inter_H_window_1_5 <= Inter_ref_06_10; + Inter_H_window_2_5 <= Inter_ref_07_10;Inter_H_window_3_5 <= Inter_ref_08_10; + Inter_H_window_4_5 <= Inter_ref_09_10;Inter_H_window_5_5 <= Inter_ref_10_10; + end + else + begin + Inter_H_window_0_2 <= Inter_ref_05_06;Inter_H_window_1_2 <= Inter_ref_06_06; + Inter_H_window_2_2 <= Inter_ref_07_06;Inter_H_window_3_2 <= Inter_ref_08_06; + Inter_H_window_4_2 <= Inter_ref_09_06;Inter_H_window_5_2 <= Inter_ref_10_06; + + Inter_H_window_0_3 <= Inter_ref_05_07;Inter_H_window_1_3 <= Inter_ref_06_07; + Inter_H_window_2_3 <= Inter_ref_07_07;Inter_H_window_3_3 <= Inter_ref_08_07; + Inter_H_window_4_3 <= Inter_ref_09_07;Inter_H_window_5_3 <= Inter_ref_10_07; + + Inter_H_window_0_4 <= Inter_ref_05_08;Inter_H_window_1_4 <= Inter_ref_06_08; + Inter_H_window_2_4 <= Inter_ref_07_08;Inter_H_window_3_4 <= Inter_ref_08_08; + Inter_H_window_4_4 <= Inter_ref_09_08;Inter_H_window_5_4 <= Inter_ref_10_08; + + Inter_H_window_0_5 <= Inter_ref_05_09;Inter_H_window_1_5 <= Inter_ref_06_09; + Inter_H_window_2_5 <= Inter_ref_07_09;Inter_H_window_3_5 <= Inter_ref_08_09; + Inter_H_window_4_5 <= Inter_ref_09_09;Inter_H_window_5_5 <= Inter_ref_10_09; + end + 3'd2: + if (pos_FracL == `pos_p || pos_FracL == `pos_r) + begin + Inter_H_window_0_2 <= Inter_ref_06_07;Inter_H_window_1_2 <= Inter_ref_07_07; + Inter_H_window_2_2 <= Inter_ref_08_07;Inter_H_window_3_2 <= Inter_ref_09_07; + Inter_H_window_4_2 <= Inter_ref_10_07;Inter_H_window_5_2 <= Inter_ref_11_07; + + Inter_H_window_0_3 <= Inter_ref_06_08;Inter_H_window_1_3 <= Inter_ref_07_08; + Inter_H_window_2_3 <= Inter_ref_08_08;Inter_H_window_3_3 <= Inter_ref_09_08; + Inter_H_window_4_3 <= Inter_ref_10_08;Inter_H_window_5_3 <= Inter_ref_11_08; + + Inter_H_window_0_4 <= Inter_ref_06_09;Inter_H_window_1_4 <= Inter_ref_07_09; + Inter_H_window_2_4 <= Inter_ref_08_09;Inter_H_window_3_4 <= Inter_ref_09_09; + Inter_H_window_4_4 <= Inter_ref_10_09;Inter_H_window_5_4 <= Inter_ref_11_09; + + Inter_H_window_0_5 <= Inter_ref_06_10;Inter_H_window_1_5 <= Inter_ref_07_10; + Inter_H_window_2_5 <= Inter_ref_08_10;Inter_H_window_3_5 <= Inter_ref_09_10; + Inter_H_window_4_5 <= Inter_ref_10_10;Inter_H_window_5_5 <= Inter_ref_11_10; + end + else + begin + Inter_H_window_0_2 <= Inter_ref_06_06;Inter_H_window_1_2 <= Inter_ref_07_06; + Inter_H_window_2_2 <= Inter_ref_08_06;Inter_H_window_3_2 <= Inter_ref_09_06; + Inter_H_window_4_2 <= Inter_ref_10_06;Inter_H_window_5_2 <= Inter_ref_11_06; + + Inter_H_window_0_3 <= Inter_ref_06_07;Inter_H_window_1_3 <= Inter_ref_07_07; + Inter_H_window_2_3 <= Inter_ref_08_07;Inter_H_window_3_3 <= Inter_ref_09_07; + Inter_H_window_4_3 <= Inter_ref_10_07;Inter_H_window_5_3 <= Inter_ref_11_07; + + Inter_H_window_0_4 <= Inter_ref_06_08;Inter_H_window_1_4 <= Inter_ref_07_08; + Inter_H_window_2_4 <= Inter_ref_08_08;Inter_H_window_3_4 <= Inter_ref_09_08; + Inter_H_window_4_4 <= Inter_ref_10_08;Inter_H_window_5_4 <= Inter_ref_11_08; + + Inter_H_window_0_5 <= Inter_ref_06_09;Inter_H_window_1_5 <= Inter_ref_07_09; + Inter_H_window_2_5 <= Inter_ref_08_09;Inter_H_window_3_5 <= Inter_ref_09_09; + Inter_H_window_4_5 <= Inter_ref_10_09;Inter_H_window_5_5 <= Inter_ref_11_09; + end + 3'd1: + if (pos_FracL == `pos_p || pos_FracL == `pos_r) + begin + Inter_H_window_0_2 <= Inter_ref_07_07;Inter_H_window_1_2 <= Inter_ref_08_07; + Inter_H_window_2_2 <= Inter_ref_09_07;Inter_H_window_3_2 <= Inter_ref_10_07; + Inter_H_window_4_2 <= Inter_ref_11_07;Inter_H_window_5_2 <= Inter_ref_12_07; + + Inter_H_window_0_3 <= Inter_ref_07_08;Inter_H_window_1_3 <= Inter_ref_08_08; + Inter_H_window_2_3 <= Inter_ref_09_08;Inter_H_window_3_3 <= Inter_ref_10_08; + Inter_H_window_4_3 <= Inter_ref_11_08;Inter_H_window_5_3 <= Inter_ref_12_08; + + Inter_H_window_0_4 <= Inter_ref_07_09;Inter_H_window_1_4 <= Inter_ref_08_09; + Inter_H_window_2_4 <= Inter_ref_09_09;Inter_H_window_3_4 <= Inter_ref_10_09; + Inter_H_window_4_4 <= Inter_ref_11_09;Inter_H_window_5_4 <= Inter_ref_12_09; + + Inter_H_window_0_5 <= Inter_ref_07_10;Inter_H_window_1_5 <= Inter_ref_08_10; + Inter_H_window_2_5 <= Inter_ref_09_10;Inter_H_window_3_5 <= Inter_ref_10_10; + Inter_H_window_4_5 <= Inter_ref_11_10;Inter_H_window_5_5 <= Inter_ref_12_10; + end + else + begin + Inter_H_window_0_2 <= Inter_ref_07_06;Inter_H_window_1_2 <= Inter_ref_08_06; + Inter_H_window_2_2 <= Inter_ref_09_06;Inter_H_window_3_2 <= Inter_ref_10_06; + Inter_H_window_4_2 <= Inter_ref_11_06;Inter_H_window_5_2 <= Inter_ref_12_06; + + Inter_H_window_0_3 <= Inter_ref_07_07;Inter_H_window_1_3 <= Inter_ref_08_07; + Inter_H_window_2_3 <= Inter_ref_09_07;Inter_H_window_3_3 <= Inter_ref_10_07; + Inter_H_window_4_3 <= Inter_ref_11_07;Inter_H_window_5_3 <= Inter_ref_12_07; + + Inter_H_window_0_4 <= Inter_ref_07_08;Inter_H_window_1_4 <= Inter_ref_08_08; + Inter_H_window_2_4 <= Inter_ref_09_08;Inter_H_window_3_4 <= Inter_ref_10_08; + Inter_H_window_4_4 <= Inter_ref_11_08;Inter_H_window_5_4 <= Inter_ref_12_08; + + Inter_H_window_0_5 <= Inter_ref_07_09;Inter_H_window_1_5 <= Inter_ref_08_09; + Inter_H_window_2_5 <= Inter_ref_09_09;Inter_H_window_3_5 <= Inter_ref_10_09; + Inter_H_window_4_5 <= Inter_ref_11_09;Inter_H_window_5_5 <= Inter_ref_12_09; + end + default: + begin + Inter_H_window_0_2 <= 0;Inter_H_window_1_2 <= 0;Inter_H_window_2_2 <= 0; + Inter_H_window_3_2 <= 0;Inter_H_window_4_2 <= 0;Inter_H_window_5_2 <= 0; + + Inter_H_window_0_3 <= 0;Inter_H_window_1_3 <= 0;Inter_H_window_2_3 <= 0; + Inter_H_window_3_3 <= 0;Inter_H_window_4_3 <= 0;Inter_H_window_5_3 <= 0; + + Inter_H_window_0_4 <= 0;Inter_H_window_1_4 <= 0;Inter_H_window_2_4 <= 0; + Inter_H_window_3_4 <= 0;Inter_H_window_4_4 <= 0;Inter_H_window_5_4 <= 0; + + Inter_H_window_0_5 <= 0;Inter_H_window_1_5 <= 0;Inter_H_window_2_5 <= 0; + Inter_H_window_3_5 <= 0;Inter_H_window_4_5 <= 0;Inter_H_window_5_5 <= 0; + end + endcase + default: + begin + Inter_H_window_0_2 <= 0;Inter_H_window_1_2 <= 0;Inter_H_window_2_2 <= 0; + Inter_H_window_3_2 <= 0;Inter_H_window_4_2 <= 0;Inter_H_window_5_2 <= 0; + + Inter_H_window_0_3 <= 0;Inter_H_window_1_3 <= 0;Inter_H_window_2_3 <= 0; + Inter_H_window_3_3 <= 0;Inter_H_window_4_3 <= 0;Inter_H_window_5_3 <= 0; + + Inter_H_window_0_4 <= 0;Inter_H_window_1_4 <= 0;Inter_H_window_2_4 <= 0; + Inter_H_window_3_4 <= 0;Inter_H_window_4_4 <= 0;Inter_H_window_5_4 <= 0; + + Inter_H_window_0_5 <= 0;Inter_H_window_1_5 <= 0;Inter_H_window_2_5 <= 0; + Inter_H_window_3_5 <= 0;Inter_H_window_4_5 <= 0;Inter_H_window_5_5 <= 0; + end + endcase + + //Inter_V_window_counter:for Inter_V_window_0 ~ Inter_V_window_8 + reg [2:0] Inter_V_window_counter; + always @ (pos_FracL or blk4x4_inter_calculate_counter) + if (((pos_FracL == `pos_h || pos_FracL == `pos_d || pos_FracL == `pos_n || pos_FracL == `pos_e || pos_FracL == `pos_g + || pos_FracL == `pos_p || pos_FracL == `pos_r) && blk4x4_inter_calculate_counter == 4'd4) || + ((pos_FracL == `pos_i || pos_FracL == `pos_k) && blk4x4_inter_calculate_counter == 4'd8)) + Inter_V_window_counter <= 3'd4; + else if (((pos_FracL == `pos_h || pos_FracL == `pos_d || pos_FracL == `pos_n || pos_FracL == `pos_e || pos_FracL == `pos_g + || pos_FracL == `pos_p || pos_FracL == `pos_r) && blk4x4_inter_calculate_counter == 4'd3) || + ((pos_FracL == `pos_i || pos_FracL == `pos_k) && blk4x4_inter_calculate_counter == 4'd6)) + Inter_V_window_counter <= 3'd3; + else if (((pos_FracL == `pos_h || pos_FracL == `pos_d || pos_FracL == `pos_n || pos_FracL == `pos_e || pos_FracL == `pos_g + || pos_FracL == `pos_p || pos_FracL == `pos_r) && blk4x4_inter_calculate_counter == 4'd2) || + ((pos_FracL == `pos_i || pos_FracL == `pos_k) && blk4x4_inter_calculate_counter == 4'd4)) + Inter_V_window_counter <= 3'd2; + else if (((pos_FracL == `pos_h || pos_FracL == `pos_d || pos_FracL == `pos_n || pos_FracL == `pos_e || pos_FracL == `pos_g + || pos_FracL == `pos_p || pos_FracL == `pos_r) && blk4x4_inter_calculate_counter == 4'd1) || + ((pos_FracL == `pos_i || pos_FracL == `pos_k) && blk4x4_inter_calculate_counter == 4'd2)) + Inter_V_window_counter <= 3'd1; + else + Inter_V_window_counter <= 0; + + //Inter_V_window_0 ~ Inter_V_window_8 + always @ (Is_blk4x4_0 or Is_blk4x4_1 or Is_blk4x4_2 or Is_blk4x4_3 or pos_FracL or Inter_V_window_counter + or Inter_ref_02_00 or Inter_ref_02_01 or Inter_ref_02_02 or Inter_ref_02_03 or Inter_ref_02_04 + or Inter_ref_02_05 or Inter_ref_02_06 or Inter_ref_02_07 or Inter_ref_02_08 or Inter_ref_02_09 + or Inter_ref_02_10 or Inter_ref_02_11 or Inter_ref_02_12 + + or Inter_ref_03_00 or Inter_ref_03_01 or Inter_ref_03_02 or Inter_ref_03_03 or Inter_ref_03_04 + or Inter_ref_03_05 or Inter_ref_03_06 or Inter_ref_03_07 or Inter_ref_03_08 or Inter_ref_03_09 + or Inter_ref_03_10 or Inter_ref_03_11 or Inter_ref_03_12 + + or Inter_ref_04_00 or Inter_ref_04_01 or Inter_ref_04_02 or Inter_ref_04_03 or Inter_ref_04_04 + or Inter_ref_04_05 or Inter_ref_04_06 or Inter_ref_04_07 or Inter_ref_04_08 or Inter_ref_04_09 + or Inter_ref_04_10 or Inter_ref_04_11 or Inter_ref_04_12 + + or Inter_ref_05_00 or Inter_ref_05_01 or Inter_ref_05_02 or Inter_ref_05_03 or Inter_ref_05_04 + or Inter_ref_05_05 or Inter_ref_05_06 or Inter_ref_05_07 or Inter_ref_05_08 or Inter_ref_05_09 + or Inter_ref_05_10 or Inter_ref_05_11 or Inter_ref_05_12 + + or Inter_ref_06_00 or Inter_ref_06_01 or Inter_ref_06_02 or Inter_ref_06_03 or Inter_ref_06_04 + or Inter_ref_06_05 or Inter_ref_06_06 or Inter_ref_06_07 or Inter_ref_06_08 or Inter_ref_06_09 + or Inter_ref_06_10 or Inter_ref_06_11 or Inter_ref_06_12 + + or Inter_ref_07_00 or Inter_ref_07_01 or Inter_ref_07_02 or Inter_ref_07_03 or Inter_ref_07_04 + or Inter_ref_07_05 or Inter_ref_07_06 or Inter_ref_07_07 or Inter_ref_07_08 or Inter_ref_07_09 + or Inter_ref_07_10 or Inter_ref_07_11 or Inter_ref_07_12 + + or Inter_ref_08_00 or Inter_ref_08_01 or Inter_ref_08_02 or Inter_ref_08_03 or Inter_ref_08_04 + or Inter_ref_08_05 or Inter_ref_08_06 or Inter_ref_08_07 or Inter_ref_08_08 or Inter_ref_08_09 + or Inter_ref_08_10 or Inter_ref_08_11 or Inter_ref_08_12 + + or Inter_ref_09_00 or Inter_ref_09_01 or Inter_ref_09_02 or Inter_ref_09_03 or Inter_ref_09_04 + or Inter_ref_09_05 or Inter_ref_09_06 or Inter_ref_09_07 or Inter_ref_09_08 or Inter_ref_09_09 + or Inter_ref_09_10 or Inter_ref_09_11 or Inter_ref_09_12 + + or Inter_ref_10_00 or Inter_ref_10_01 or Inter_ref_10_02 or Inter_ref_10_03 or Inter_ref_10_04 + or Inter_ref_10_05 or Inter_ref_10_06 or Inter_ref_10_07 or Inter_ref_10_08 or Inter_ref_10_09 + or Inter_ref_10_10 or Inter_ref_10_11 or Inter_ref_10_12 + ) + case ({Is_blk4x4_0,Is_blk4x4_1,Is_blk4x4_2,Is_blk4x4_3}) + 4'b1000: //Left top blk4x4 + case (Inter_V_window_counter) + 3'd4: + if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) + begin + Inter_V_window_0 <= Inter_ref_03_00;Inter_V_window_1 <= Inter_ref_03_01; + Inter_V_window_2 <= Inter_ref_03_02;Inter_V_window_3 <= Inter_ref_03_03; + Inter_V_window_4 <= Inter_ref_03_04;Inter_V_window_5 <= Inter_ref_03_05; + Inter_V_window_6 <= Inter_ref_03_06;Inter_V_window_7 <= Inter_ref_03_07; + Inter_V_window_8 <= Inter_ref_03_08; + end + else + begin + Inter_V_window_0 <= Inter_ref_02_00;Inter_V_window_1 <= Inter_ref_02_01; + Inter_V_window_2 <= Inter_ref_02_02;Inter_V_window_3 <= Inter_ref_02_03; + Inter_V_window_4 <= Inter_ref_02_04;Inter_V_window_5 <= Inter_ref_02_05; + Inter_V_window_6 <= Inter_ref_02_06;Inter_V_window_7 <= Inter_ref_02_07; + Inter_V_window_8 <= Inter_ref_02_08; + end + 3'd3: + if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) + begin + Inter_V_window_0 <= Inter_ref_04_00;Inter_V_window_1 <= Inter_ref_04_01; + Inter_V_window_2 <= Inter_ref_04_02;Inter_V_window_3 <= Inter_ref_04_03; + Inter_V_window_4 <= Inter_ref_04_04;Inter_V_window_5 <= Inter_ref_04_05; + Inter_V_window_6 <= Inter_ref_04_06;Inter_V_window_7 <= Inter_ref_04_07; + Inter_V_window_8 <= Inter_ref_04_08; + end + else + begin + Inter_V_window_0 <= Inter_ref_03_00;Inter_V_window_1 <= Inter_ref_03_01; + Inter_V_window_2 <= Inter_ref_03_02;Inter_V_window_3 <= Inter_ref_03_03; + Inter_V_window_4 <= Inter_ref_03_04;Inter_V_window_5 <= Inter_ref_03_05; + Inter_V_window_6 <= Inter_ref_03_06;Inter_V_window_7 <= Inter_ref_03_07; + Inter_V_window_8 <= Inter_ref_03_08; + end + 3'd2: + if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) + begin + Inter_V_window_0 <= Inter_ref_05_00;Inter_V_window_1 <= Inter_ref_05_01; + Inter_V_window_2 <= Inter_ref_05_02;Inter_V_window_3 <= Inter_ref_05_03; + Inter_V_window_4 <= Inter_ref_05_04;Inter_V_window_5 <= Inter_ref_05_05; + Inter_V_window_6 <= Inter_ref_05_06;Inter_V_window_7 <= Inter_ref_05_07; + Inter_V_window_8 <= Inter_ref_05_08; + end + else + begin + Inter_V_window_0 <= Inter_ref_04_00;Inter_V_window_1 <= Inter_ref_04_01; + Inter_V_window_2 <= Inter_ref_04_02;Inter_V_window_3 <= Inter_ref_04_03; + Inter_V_window_4 <= Inter_ref_04_04;Inter_V_window_5 <= Inter_ref_04_05; + Inter_V_window_6 <= Inter_ref_04_06;Inter_V_window_7 <= Inter_ref_04_07; + Inter_V_window_8 <= Inter_ref_04_08; + end + 3'd1: + if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) + begin + Inter_V_window_0 <= Inter_ref_06_00;Inter_V_window_1 <= Inter_ref_06_01; + Inter_V_window_2 <= Inter_ref_06_02;Inter_V_window_3 <= Inter_ref_06_03; + Inter_V_window_4 <= Inter_ref_06_04;Inter_V_window_5 <= Inter_ref_06_05; + Inter_V_window_6 <= Inter_ref_06_06;Inter_V_window_7 <= Inter_ref_06_07; + Inter_V_window_8 <= Inter_ref_06_08; + end + else + begin + Inter_V_window_0 <= Inter_ref_05_00;Inter_V_window_1 <= Inter_ref_05_01; + Inter_V_window_2 <= Inter_ref_05_02;Inter_V_window_3 <= Inter_ref_05_03; + Inter_V_window_4 <= Inter_ref_05_04;Inter_V_window_5 <= Inter_ref_05_05; + Inter_V_window_6 <= Inter_ref_05_06;Inter_V_window_7 <= Inter_ref_05_07; + Inter_V_window_8 <= Inter_ref_05_08; + end + default: + begin + Inter_V_window_0 <= 0;Inter_V_window_1 <= 0;Inter_V_window_2 <= 0; + Inter_V_window_3 <= 0;Inter_V_window_4 <= 0;Inter_V_window_5 <= 0; + Inter_V_window_6 <= 0;Inter_V_window_7 <= 0;Inter_V_window_8 <= 0; + end + endcase + 4'b0100: //Right top blk4x4 + case (Inter_V_window_counter) + 3'd4: + if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) + begin + Inter_V_window_0 <= Inter_ref_07_00;Inter_V_window_1 <= Inter_ref_07_01; + Inter_V_window_2 <= Inter_ref_07_02;Inter_V_window_3 <= Inter_ref_07_03; + Inter_V_window_4 <= Inter_ref_07_04;Inter_V_window_5 <= Inter_ref_07_05; + Inter_V_window_6 <= Inter_ref_07_06;Inter_V_window_7 <= Inter_ref_07_07; + Inter_V_window_8 <= Inter_ref_07_08; + end + else + begin + Inter_V_window_0 <= Inter_ref_06_00;Inter_V_window_1 <= Inter_ref_06_01; + Inter_V_window_2 <= Inter_ref_06_02;Inter_V_window_3 <= Inter_ref_06_03; + Inter_V_window_4 <= Inter_ref_06_04;Inter_V_window_5 <= Inter_ref_06_05; + Inter_V_window_6 <= Inter_ref_06_06;Inter_V_window_7 <= Inter_ref_06_07; + Inter_V_window_8 <= Inter_ref_06_08; + end + 3'd3: + if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) + begin + Inter_V_window_0 <= Inter_ref_08_00;Inter_V_window_1 <= Inter_ref_08_01; + Inter_V_window_2 <= Inter_ref_08_02;Inter_V_window_3 <= Inter_ref_08_03; + Inter_V_window_4 <= Inter_ref_08_04;Inter_V_window_5 <= Inter_ref_08_05; + Inter_V_window_6 <= Inter_ref_08_06;Inter_V_window_7 <= Inter_ref_08_07; + Inter_V_window_8 <= Inter_ref_08_08; + end + else + begin + Inter_V_window_0 <= Inter_ref_07_00;Inter_V_window_1 <= Inter_ref_07_01; + Inter_V_window_2 <= Inter_ref_07_02;Inter_V_window_3 <= Inter_ref_07_03; + Inter_V_window_4 <= Inter_ref_07_04;Inter_V_window_5 <= Inter_ref_07_05; + Inter_V_window_6 <= Inter_ref_07_06;Inter_V_window_7 <= Inter_ref_07_07; + Inter_V_window_8 <= Inter_ref_07_08; + end + 3'd2: + if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) + begin + Inter_V_window_0 <= Inter_ref_09_00;Inter_V_window_1 <= Inter_ref_09_01; + Inter_V_window_2 <= Inter_ref_09_02;Inter_V_window_3 <= Inter_ref_09_03; + Inter_V_window_4 <= Inter_ref_09_04;Inter_V_window_5 <= Inter_ref_09_05; + Inter_V_window_6 <= Inter_ref_09_06;Inter_V_window_7 <= Inter_ref_09_07; + Inter_V_window_8 <= Inter_ref_09_08; + end + else + begin + Inter_V_window_0 <= Inter_ref_08_00;Inter_V_window_1 <= Inter_ref_08_01; + Inter_V_window_2 <= Inter_ref_08_02;Inter_V_window_3 <= Inter_ref_08_03; + Inter_V_window_4 <= Inter_ref_08_04;Inter_V_window_5 <= Inter_ref_08_05; + Inter_V_window_6 <= Inter_ref_08_06;Inter_V_window_7 <= Inter_ref_08_07; + Inter_V_window_8 <= Inter_ref_08_08; + end + 3'd1: + if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) + begin + Inter_V_window_0 <= Inter_ref_10_00;Inter_V_window_1 <= Inter_ref_10_01; + Inter_V_window_2 <= Inter_ref_10_02;Inter_V_window_3 <= Inter_ref_10_03; + Inter_V_window_4 <= Inter_ref_10_04;Inter_V_window_5 <= Inter_ref_10_05; + Inter_V_window_6 <= Inter_ref_10_06;Inter_V_window_7 <= Inter_ref_10_07; + Inter_V_window_8 <= Inter_ref_10_08; + end + else + begin + Inter_V_window_0 <= Inter_ref_09_00;Inter_V_window_1 <= Inter_ref_09_01; + Inter_V_window_2 <= Inter_ref_09_02;Inter_V_window_3 <= Inter_ref_09_03; + Inter_V_window_4 <= Inter_ref_09_04;Inter_V_window_5 <= Inter_ref_09_05; + Inter_V_window_6 <= Inter_ref_09_06;Inter_V_window_7 <= Inter_ref_09_07; + Inter_V_window_8 <= Inter_ref_09_08; + end + default: + begin + Inter_V_window_0 <= 0;Inter_V_window_1 <= 0;Inter_V_window_2 <= 0; + Inter_V_window_3 <= 0;Inter_V_window_4 <= 0;Inter_V_window_5 <= 0; + Inter_V_window_6 <= 0;Inter_V_window_7 <= 0;Inter_V_window_8 <= 0; + end + endcase + 4'b0010: //Left bottom blk4x4 + case (Inter_V_window_counter) + 3'd4: + if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) + begin + Inter_V_window_0 <= Inter_ref_03_04;Inter_V_window_1 <= Inter_ref_03_05; + Inter_V_window_2 <= Inter_ref_03_06;Inter_V_window_3 <= Inter_ref_03_07; + Inter_V_window_4 <= Inter_ref_03_08;Inter_V_window_5 <= Inter_ref_03_09; + Inter_V_window_6 <= Inter_ref_03_10;Inter_V_window_7 <= Inter_ref_03_11; + Inter_V_window_8 <= Inter_ref_03_12; + end + else + begin + Inter_V_window_0 <= Inter_ref_02_04;Inter_V_window_1 <= Inter_ref_02_05; + Inter_V_window_2 <= Inter_ref_02_06;Inter_V_window_3 <= Inter_ref_02_07; + Inter_V_window_4 <= Inter_ref_02_08;Inter_V_window_5 <= Inter_ref_02_09; + Inter_V_window_6 <= Inter_ref_02_10;Inter_V_window_7 <= Inter_ref_02_11; + Inter_V_window_8 <= Inter_ref_02_12; + end + 3'd3: + if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) + begin + Inter_V_window_0 <= Inter_ref_04_04;Inter_V_window_1 <= Inter_ref_04_05; + Inter_V_window_2 <= Inter_ref_04_06;Inter_V_window_3 <= Inter_ref_04_07; + Inter_V_window_4 <= Inter_ref_04_08;Inter_V_window_5 <= Inter_ref_04_09; + Inter_V_window_6 <= Inter_ref_04_10;Inter_V_window_7 <= Inter_ref_04_11; + Inter_V_window_8 <= Inter_ref_04_12; + end + else + begin + Inter_V_window_0 <= Inter_ref_03_04;Inter_V_window_1 <= Inter_ref_03_05; + Inter_V_window_2 <= Inter_ref_03_06;Inter_V_window_3 <= Inter_ref_03_07; + Inter_V_window_4 <= Inter_ref_03_08;Inter_V_window_5 <= Inter_ref_03_09; + Inter_V_window_6 <= Inter_ref_03_10;Inter_V_window_7 <= Inter_ref_03_11; + Inter_V_window_8 <= Inter_ref_03_12; + end + 3'd2: + if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) + begin + Inter_V_window_0 <= Inter_ref_05_04;Inter_V_window_1 <= Inter_ref_05_05; + Inter_V_window_2 <= Inter_ref_05_06;Inter_V_window_3 <= Inter_ref_05_07; + Inter_V_window_4 <= Inter_ref_05_08;Inter_V_window_5 <= Inter_ref_05_09; + Inter_V_window_6 <= Inter_ref_05_10;Inter_V_window_7 <= Inter_ref_05_11; + Inter_V_window_8 <= Inter_ref_05_12; + end + else + begin + Inter_V_window_0 <= Inter_ref_04_04;Inter_V_window_1 <= Inter_ref_04_05; + Inter_V_window_2 <= Inter_ref_04_06;Inter_V_window_3 <= Inter_ref_04_07; + Inter_V_window_4 <= Inter_ref_04_08;Inter_V_window_5 <= Inter_ref_04_09; + Inter_V_window_6 <= Inter_ref_04_10;Inter_V_window_7 <= Inter_ref_04_11; + Inter_V_window_8 <= Inter_ref_04_12; + end + 3'd1: + if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) + begin + Inter_V_window_0 <= Inter_ref_06_04;Inter_V_window_1 <= Inter_ref_06_05; + Inter_V_window_2 <= Inter_ref_06_06;Inter_V_window_3 <= Inter_ref_06_07; + Inter_V_window_4 <= Inter_ref_06_08;Inter_V_window_5 <= Inter_ref_06_09; + Inter_V_window_6 <= Inter_ref_06_10;Inter_V_window_7 <= Inter_ref_06_11; + Inter_V_window_8 <= Inter_ref_06_12; + end + else + begin + Inter_V_window_0 <= Inter_ref_05_04;Inter_V_window_1 <= Inter_ref_05_05; + Inter_V_window_2 <= Inter_ref_05_06;Inter_V_window_3 <= Inter_ref_05_07; + Inter_V_window_4 <= Inter_ref_05_08;Inter_V_window_5 <= Inter_ref_05_09; + Inter_V_window_6 <= Inter_ref_05_10;Inter_V_window_7 <= Inter_ref_05_11; + Inter_V_window_8 <= Inter_ref_05_12; + end + default: + begin + Inter_V_window_0 <= 0;Inter_V_window_1 <= 0;Inter_V_window_2 <= 0; + Inter_V_window_3 <= 0;Inter_V_window_4 <= 0;Inter_V_window_5 <= 0; + Inter_V_window_6 <= 0;Inter_V_window_7 <= 0;Inter_V_window_8 <= 0; + end + endcase + 4'b0001: //Right bottom blk4x4 + case (Inter_V_window_counter) + 3'd4: + if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) + begin + Inter_V_window_0 <= Inter_ref_07_04;Inter_V_window_1 <= Inter_ref_07_05; + Inter_V_window_2 <= Inter_ref_07_06;Inter_V_window_3 <= Inter_ref_07_07; + Inter_V_window_4 <= Inter_ref_07_08;Inter_V_window_5 <= Inter_ref_07_09; + Inter_V_window_6 <= Inter_ref_07_10;Inter_V_window_7 <= Inter_ref_07_11; + Inter_V_window_8 <= Inter_ref_07_12; + end + else + begin + Inter_V_window_0 <= Inter_ref_06_04;Inter_V_window_1 <= Inter_ref_06_05; + Inter_V_window_2 <= Inter_ref_06_06;Inter_V_window_3 <= Inter_ref_06_07; + Inter_V_window_4 <= Inter_ref_06_08;Inter_V_window_5 <= Inter_ref_06_09; + Inter_V_window_6 <= Inter_ref_06_10;Inter_V_window_7 <= Inter_ref_06_11; + Inter_V_window_8 <= Inter_ref_06_12; + end + 3'd3: + if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) + begin + Inter_V_window_0 <= Inter_ref_08_04;Inter_V_window_1 <= Inter_ref_08_05; + Inter_V_window_2 <= Inter_ref_08_06;Inter_V_window_3 <= Inter_ref_08_07; + Inter_V_window_4 <= Inter_ref_08_08;Inter_V_window_5 <= Inter_ref_08_09; + Inter_V_window_6 <= Inter_ref_08_10;Inter_V_window_7 <= Inter_ref_08_11; + Inter_V_window_8 <= Inter_ref_08_12; + end + else + begin + Inter_V_window_0 <= Inter_ref_07_04;Inter_V_window_1 <= Inter_ref_07_05; + Inter_V_window_2 <= Inter_ref_07_06;Inter_V_window_3 <= Inter_ref_07_07; + Inter_V_window_4 <= Inter_ref_07_08;Inter_V_window_5 <= Inter_ref_07_09; + Inter_V_window_6 <= Inter_ref_07_10;Inter_V_window_7 <= Inter_ref_07_11; + Inter_V_window_8 <= Inter_ref_07_12; + end + 3'd2: + if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) + begin + Inter_V_window_0 <= Inter_ref_09_04;Inter_V_window_1 <= Inter_ref_09_05; + Inter_V_window_2 <= Inter_ref_09_06;Inter_V_window_3 <= Inter_ref_09_07; + Inter_V_window_4 <= Inter_ref_09_08;Inter_V_window_5 <= Inter_ref_09_09; + Inter_V_window_6 <= Inter_ref_09_10;Inter_V_window_7 <= Inter_ref_09_11; + Inter_V_window_8 <= Inter_ref_09_12; + end + else + begin + Inter_V_window_0 <= Inter_ref_08_04;Inter_V_window_1 <= Inter_ref_08_05; + Inter_V_window_2 <= Inter_ref_08_06;Inter_V_window_3 <= Inter_ref_08_07; + Inter_V_window_4 <= Inter_ref_08_08;Inter_V_window_5 <= Inter_ref_08_09; + Inter_V_window_6 <= Inter_ref_08_10;Inter_V_window_7 <= Inter_ref_08_11; + Inter_V_window_8 <= Inter_ref_08_12; + end + 3'd1: + if (pos_FracL == `pos_g || pos_FracL == `pos_r || pos_FracL == `pos_k) + begin + Inter_V_window_0 <= Inter_ref_10_04;Inter_V_window_1 <= Inter_ref_10_05; + Inter_V_window_2 <= Inter_ref_10_06;Inter_V_window_3 <= Inter_ref_10_07; + Inter_V_window_4 <= Inter_ref_10_08;Inter_V_window_5 <= Inter_ref_10_09; + Inter_V_window_6 <= Inter_ref_10_10;Inter_V_window_7 <= Inter_ref_10_11; + Inter_V_window_8 <= Inter_ref_10_12; + end + else + begin + Inter_V_window_0 <= Inter_ref_09_04;Inter_V_window_1 <= Inter_ref_09_05; + Inter_V_window_2 <= Inter_ref_09_06;Inter_V_window_3 <= Inter_ref_09_07; + Inter_V_window_4 <= Inter_ref_09_08;Inter_V_window_5 <= Inter_ref_09_09; + Inter_V_window_6 <= Inter_ref_09_10;Inter_V_window_7 <= Inter_ref_09_11; + Inter_V_window_8 <= Inter_ref_09_12; + end + default: + begin + Inter_V_window_0 <= 0;Inter_V_window_1 <= 0;Inter_V_window_2 <= 0; + Inter_V_window_3 <= 0;Inter_V_window_4 <= 0;Inter_V_window_5 <= 0; + Inter_V_window_6 <= 0;Inter_V_window_7 <= 0;Inter_V_window_8 <= 0; + end + endcase + default: + begin + Inter_V_window_0 <= 0;Inter_V_window_1 <= 0;Inter_V_window_2 <= 0; + Inter_V_window_3 <= 0;Inter_V_window_4 <= 0;Inter_V_window_5 <= 0; + Inter_V_window_6 <= 0;Inter_V_window_7 <= 0;Inter_V_window_8 <= 0; + end + endcase + + //Luma bilinear window + always @ (Is_blk4x4_0 or Is_blk4x4_1 or Is_blk4x4_2 or Is_blk4x4_3 or pos_FracL or blk4x4_inter_calculate_counter + or Inter_ref_02_02 or Inter_ref_03_02 or Inter_ref_04_02 or Inter_ref_05_02 or Inter_ref_06_02 + or Inter_ref_07_02 or Inter_ref_08_02 or Inter_ref_09_02 or Inter_ref_10_02 + or Inter_ref_02_03 or Inter_ref_03_03 or Inter_ref_04_03 or Inter_ref_05_03 or Inter_ref_06_03 + or Inter_ref_07_03 or Inter_ref_08_03 or Inter_ref_09_03 or Inter_ref_10_03 + or Inter_ref_02_04 or Inter_ref_03_04 or Inter_ref_04_04 or Inter_ref_05_04 or Inter_ref_06_04 + or Inter_ref_07_04 or Inter_ref_08_04 or Inter_ref_09_04 or Inter_ref_10_04 + or Inter_ref_02_05 or Inter_ref_03_05 or Inter_ref_04_05 or Inter_ref_05_05 or Inter_ref_06_05 + or Inter_ref_07_05 or Inter_ref_08_05 or Inter_ref_09_05 or Inter_ref_10_05 + or Inter_ref_02_06 or Inter_ref_03_06 or Inter_ref_04_06 or Inter_ref_05_06 or Inter_ref_06_06 + or Inter_ref_07_06 or Inter_ref_08_06 or Inter_ref_09_06 or Inter_ref_10_06 + or Inter_ref_02_07 or Inter_ref_03_07 or Inter_ref_04_07 or Inter_ref_05_07 or Inter_ref_06_07 + or Inter_ref_07_07 or Inter_ref_08_07 or Inter_ref_09_07 or Inter_ref_10_07 + or Inter_ref_02_08 or Inter_ref_03_08 or Inter_ref_04_08 or Inter_ref_05_08 or Inter_ref_06_08 + or Inter_ref_07_08 or Inter_ref_08_08 or Inter_ref_09_08 or Inter_ref_10_08 + or Inter_ref_02_09 or Inter_ref_03_09 or Inter_ref_04_09 or Inter_ref_05_09 or Inter_ref_06_09 + or Inter_ref_07_09 or Inter_ref_08_09 or Inter_ref_09_09 or Inter_ref_10_09 + or Inter_ref_02_10 or Inter_ref_03_10 or Inter_ref_04_10 or Inter_ref_05_10 or Inter_ref_06_10 + or Inter_ref_07_10 or Inter_ref_08_10 or Inter_ref_09_10) + case ({Is_blk4x4_0,Is_blk4x4_1,Is_blk4x4_2,Is_blk4x4_3}) + 4'b1000: //Left top blk4x4 + case (pos_FracL) + pos_a,pos_d: + case (blk4x4_inter_calculate_counter) + 4'd4:begin Inter_bi_window_0 <= Inter_ref_02_02;Inter_bi_window_1 <= Inter_ref_02_03; + Inter_bi_window_2 <= Inter_ref_02_04;Inter_bi_window_3 <= Inter_ref_02_05; end + 4'd3:begin Inter_bi_window_0 <= Inter_ref_03_02;Inter_bi_window_1 <= Inter_ref_03_03; + Inter_bi_window_2 <= Inter_ref_03_04;Inter_bi_window_3 <= Inter_ref_03_05; end + 4'd2:begin Inter_bi_window_0 <= Inter_ref_04_02;Inter_bi_window_1 <= Inter_ref_04_03; + Inter_bi_window_2 <= Inter_ref_04_04;Inter_bi_window_3 <= Inter_ref_04_05; end + 4'd1:begin Inter_bi_window_0 <= Inter_ref_05_02;Inter_bi_window_1 <= Inter_ref_05_03; + Inter_bi_window_2 <= Inter_ref_05_04;Inter_bi_window_3 <= Inter_ref_05_05; end + default:begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; + Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end + endcase + pos_c: + case (blk4x4_inter_calculate_counter) + 4'd4:begin Inter_bi_window_0 <= Inter_ref_03_02;Inter_bi_window_1 <= Inter_ref_03_03; + Inter_bi_window_2 <= Inter_ref_03_04;Inter_bi_window_3 <= Inter_ref_03_05; end + 4'd3:begin Inter_bi_window_0 <= Inter_ref_04_02;Inter_bi_window_1 <= Inter_ref_04_03; + Inter_bi_window_2 <= Inter_ref_04_04;Inter_bi_window_3 <= Inter_ref_04_05; end + 4'd2:begin Inter_bi_window_0 <= Inter_ref_05_02;Inter_bi_window_1 <= Inter_ref_05_03; + Inter_bi_window_2 <= Inter_ref_05_04;Inter_bi_window_3 <= Inter_ref_05_05; end + 4'd1:begin Inter_bi_window_0 <= Inter_ref_06_02;Inter_bi_window_1 <= Inter_ref_06_03; + Inter_bi_window_2 <= Inter_ref_06_04;Inter_bi_window_3 <= Inter_ref_06_05; end + default:begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; + Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end + endcase + pos_n: + case (blk4x4_inter_calculate_counter) + 4'd4:begin Inter_bi_window_0 <= Inter_ref_02_03;Inter_bi_window_1 <= Inter_ref_02_04; + Inter_bi_window_2 <= Inter_ref_02_05;Inter_bi_window_3 <= Inter_ref_02_06; end + 4'd3:begin Inter_bi_window_0 <= Inter_ref_03_03;Inter_bi_window_1 <= Inter_ref_03_04; + Inter_bi_window_2 <= Inter_ref_03_05;Inter_bi_window_3 <= Inter_ref_03_06; end + 4'd2:begin Inter_bi_window_0 <= Inter_ref_04_03;Inter_bi_window_1 <= Inter_ref_04_04; + Inter_bi_window_2 <= Inter_ref_04_05;Inter_bi_window_3 <= Inter_ref_04_06; end + 4'd1:begin Inter_bi_window_0 <= Inter_ref_05_03;Inter_bi_window_1 <= Inter_ref_05_04; + Inter_bi_window_2 <= Inter_ref_05_05;Inter_bi_window_3 <= Inter_ref_05_06; end + default:begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; + Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end + endcase + default: + begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; + Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end + endcase + 4'b0100: //Right top blk4x4 + case (pos_FracL) + pos_a,pos_d: + case (blk4x4_inter_calculate_counter) + 4'd4:begin Inter_bi_window_0 <= Inter_ref_06_02;Inter_bi_window_1 <= Inter_ref_06_03; + Inter_bi_window_2 <= Inter_ref_06_04;Inter_bi_window_3 <= Inter_ref_06_05; end + 4'd3:begin Inter_bi_window_0 <= Inter_ref_07_02;Inter_bi_window_1 <= Inter_ref_07_03; + Inter_bi_window_2 <= Inter_ref_07_04;Inter_bi_window_3 <= Inter_ref_07_05; end + 4'd2:begin Inter_bi_window_0 <= Inter_ref_08_02;Inter_bi_window_1 <= Inter_ref_08_03; + Inter_bi_window_2 <= Inter_ref_08_04;Inter_bi_window_3 <= Inter_ref_08_05; end + 4'd1:begin Inter_bi_window_0 <= Inter_ref_09_02;Inter_bi_window_1 <= Inter_ref_09_03; + Inter_bi_window_2 <= Inter_ref_09_04;Inter_bi_window_3 <= Inter_ref_09_05; end + default:begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; + Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end + endcase + pos_c: + case (blk4x4_inter_calculate_counter) + 4'd4:begin Inter_bi_window_0 <= Inter_ref_07_02;Inter_bi_window_1 <= Inter_ref_07_03; + Inter_bi_window_2 <= Inter_ref_07_04;Inter_bi_window_3 <= Inter_ref_07_05; end + 4'd3:begin Inter_bi_window_0 <= Inter_ref_08_02;Inter_bi_window_1 <= Inter_ref_08_03; + Inter_bi_window_2 <= Inter_ref_08_04;Inter_bi_window_3 <= Inter_ref_08_05; end + 4'd2:begin Inter_bi_window_0 <= Inter_ref_09_02;Inter_bi_window_1 <= Inter_ref_09_03; + Inter_bi_window_2 <= Inter_ref_09_04;Inter_bi_window_3 <= Inter_ref_09_05; end + 4'd1:begin Inter_bi_window_0 <= Inter_ref_10_02;Inter_bi_window_1 <= Inter_ref_10_03; + Inter_bi_window_2 <= Inter_ref_10_04;Inter_bi_window_3 <= Inter_ref_10_05; end + default:begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; + Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end + endcase + pos_n: + case (blk4x4_inter_calculate_counter) + 4'd4:begin Inter_bi_window_0 <= Inter_ref_06_03;Inter_bi_window_1 <= Inter_ref_06_04; + Inter_bi_window_2 <= Inter_ref_06_05;Inter_bi_window_3 <= Inter_ref_06_06; end + 4'd3:begin Inter_bi_window_0 <= Inter_ref_07_03;Inter_bi_window_1 <= Inter_ref_07_04; + Inter_bi_window_2 <= Inter_ref_07_05;Inter_bi_window_3 <= Inter_ref_07_06; end + 4'd2:begin Inter_bi_window_0 <= Inter_ref_08_03;Inter_bi_window_1 <= Inter_ref_08_04; + Inter_bi_window_2 <= Inter_ref_08_05;Inter_bi_window_3 <= Inter_ref_08_06; end + 4'd1:begin Inter_bi_window_0 <= Inter_ref_09_03;Inter_bi_window_1 <= Inter_ref_09_04; + Inter_bi_window_2 <= Inter_ref_09_05;Inter_bi_window_3 <= Inter_ref_09_06; end + default:begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; + Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end + endcase + default: + begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; + Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end + endcase + 4'b0010: //Left bottom blk4x4 + case (pos_FracL) + pos_a,pos_d: + case (blk4x4_inter_calculate_counter) + 4'd4:begin Inter_bi_window_0 <= Inter_ref_02_06;Inter_bi_window_1 <= Inter_ref_02_07; + Inter_bi_window_2 <= Inter_ref_02_08;Inter_bi_window_3 <= Inter_ref_02_09; end + 4'd3:begin Inter_bi_window_0 <= Inter_ref_03_06;Inter_bi_window_1 <= Inter_ref_03_07; + Inter_bi_window_2 <= Inter_ref_03_08;Inter_bi_window_3 <= Inter_ref_03_09; end + 4'd2:begin Inter_bi_window_0 <= Inter_ref_04_06;Inter_bi_window_1 <= Inter_ref_04_07; + Inter_bi_window_2 <= Inter_ref_04_08;Inter_bi_window_3 <= Inter_ref_04_09; end + 4'd1:begin Inter_bi_window_0 <= Inter_ref_05_06;Inter_bi_window_1 <= Inter_ref_05_07; + Inter_bi_window_2 <= Inter_ref_05_08;Inter_bi_window_3 <= Inter_ref_05_09; end + default:begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; + Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end + endcase + pos_c: + case (blk4x4_inter_calculate_counter) + 4'd4:begin Inter_bi_window_0 <= Inter_ref_03_06;Inter_bi_window_1 <= Inter_ref_03_07; + Inter_bi_window_2 <= Inter_ref_03_08;Inter_bi_window_3 <= Inter_ref_03_09; end + 4'd3:begin Inter_bi_window_0 <= Inter_ref_04_06;Inter_bi_window_1 <= Inter_ref_04_07; + Inter_bi_window_2 <= Inter_ref_04_08;Inter_bi_window_3 <= Inter_ref_04_09; end + 4'd2:begin Inter_bi_window_0 <= Inter_ref_05_06;Inter_bi_window_1 <= Inter_ref_05_07; + Inter_bi_window_2 <= Inter_ref_05_08;Inter_bi_window_3 <= Inter_ref_05_09; end + 4'd1:begin Inter_bi_window_0 <= Inter_ref_06_06;Inter_bi_window_1 <= Inter_ref_06_07; + Inter_bi_window_2 <= Inter_ref_06_08;Inter_bi_window_3 <= Inter_ref_06_09; end + default:begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; + Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end + endcase + pos_n: + case (blk4x4_inter_calculate_counter) + 4'd4:begin Inter_bi_window_0 <= Inter_ref_02_07;Inter_bi_window_1 <= Inter_ref_02_08; + Inter_bi_window_2 <= Inter_ref_02_09;Inter_bi_window_3 <= Inter_ref_02_10; end + 4'd3:begin Inter_bi_window_0 <= Inter_ref_03_07;Inter_bi_window_1 <= Inter_ref_03_08; + Inter_bi_window_2 <= Inter_ref_03_09;Inter_bi_window_3 <= Inter_ref_03_10; end + 4'd2:begin Inter_bi_window_0 <= Inter_ref_04_07;Inter_bi_window_1 <= Inter_ref_04_08; + Inter_bi_window_2 <= Inter_ref_04_09;Inter_bi_window_3 <= Inter_ref_04_10; end + 4'd1:begin Inter_bi_window_0 <= Inter_ref_05_07;Inter_bi_window_1 <= Inter_ref_05_08; + Inter_bi_window_2 <= Inter_ref_05_09;Inter_bi_window_3 <= Inter_ref_05_10; end + default:begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; + Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end + endcase + default: + begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; + Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end + endcase + 4'b0001: //Right bottom blk4x4 + case (pos_FracL) + pos_a,pos_d: + case (blk4x4_inter_calculate_counter) + 4'd4:begin Inter_bi_window_0 <= Inter_ref_06_06;Inter_bi_window_1 <= Inter_ref_06_07; + Inter_bi_window_2 <= Inter_ref_06_08;Inter_bi_window_3 <= Inter_ref_06_09; end + 4'd3:begin Inter_bi_window_0 <= Inter_ref_07_06;Inter_bi_window_1 <= Inter_ref_07_07; + Inter_bi_window_2 <= Inter_ref_07_08;Inter_bi_window_3 <= Inter_ref_07_09; end + 4'd2:begin Inter_bi_window_0 <= Inter_ref_08_06;Inter_bi_window_1 <= Inter_ref_08_07; + Inter_bi_window_2 <= Inter_ref_08_08;Inter_bi_window_3 <= Inter_ref_08_09; end + 4'd1:begin Inter_bi_window_0 <= Inter_ref_09_06;Inter_bi_window_1 <= Inter_ref_09_07; + Inter_bi_window_2 <= Inter_ref_09_08;Inter_bi_window_3 <= Inter_ref_09_09; end + default:begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; + Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end + endcase + pos_c: + case (blk4x4_inter_calculate_counter) + 4'd4:begin Inter_bi_window_0 <= Inter_ref_07_06;Inter_bi_window_1 <= Inter_ref_07_07; + Inter_bi_window_2 <= Inter_ref_07_08;Inter_bi_window_3 <= Inter_ref_07_09; end + 4'd3:begin Inter_bi_window_0 <= Inter_ref_08_06;Inter_bi_window_1 <= Inter_ref_08_07; + Inter_bi_window_2 <= Inter_ref_08_08;Inter_bi_window_3 <= Inter_ref_08_09; end + 4'd2:begin Inter_bi_window_0 <= Inter_ref_09_06;Inter_bi_window_1 <= Inter_ref_09_07; + Inter_bi_window_2 <= Inter_ref_09_08;Inter_bi_window_3 <= Inter_ref_09_09; end + 4'd1:begin Inter_bi_window_0 <= Inter_ref_10_06;Inter_bi_window_1 <= Inter_ref_10_07; + Inter_bi_window_2 <= Inter_ref_10_08;Inter_bi_window_3 <= Inter_ref_10_09; end + default:begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; + Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end + endcase + pos_n: + case (blk4x4_inter_calculate_counter) + 4'd4:begin Inter_bi_window_0 <= Inter_ref_06_07;Inter_bi_window_1 <= Inter_ref_06_08; + Inter_bi_window_2 <= Inter_ref_06_09;Inter_bi_window_3 <= Inter_ref_06_10; end + 4'd3:begin Inter_bi_window_0 <= Inter_ref_07_07;Inter_bi_window_1 <= Inter_ref_07_08; + Inter_bi_window_2 <= Inter_ref_07_09;Inter_bi_window_3 <= Inter_ref_07_10; end + 4'd2:begin Inter_bi_window_0 <= Inter_ref_08_07;Inter_bi_window_1 <= Inter_ref_08_08; + Inter_bi_window_2 <= Inter_ref_08_09;Inter_bi_window_3 <= Inter_ref_08_10; end + 4'd1:begin Inter_bi_window_0 <= Inter_ref_09_07;Inter_bi_window_1 <= Inter_ref_09_08; + Inter_bi_window_2 <= Inter_ref_09_09;Inter_bi_window_3 <= Inter_ref_09_10; end + default:begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; + Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end + endcase + default: + begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; + Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end + endcase + default: + begin Inter_bi_window_0 <= 0;Inter_bi_window_1 <= 0; + Inter_bi_window_2 <= 0;Inter_bi_window_3 <= 0; end + endcase + + //chroma sliding window:Inter_C_window_0 ~ Inter_C_window_3 + always @ (IsInterChroma or blk4x4_inter_calculate_counter or mv_below8x8_curr + or Inter_ref_00_00 or Inter_ref_01_00 or Inter_ref_02_00 or Inter_ref_03_00 or Inter_ref_04_00 + or Inter_ref_00_01 or Inter_ref_01_01 or Inter_ref_02_01 or Inter_ref_03_01 or Inter_ref_04_01 + or Inter_ref_00_02 or Inter_ref_01_02 or Inter_ref_02_02 or Inter_ref_03_02 or Inter_ref_04_02 + or Inter_ref_00_03 or Inter_ref_01_03 or Inter_ref_02_03 or Inter_ref_03_03 or Inter_ref_04_03 + or Inter_ref_00_04 or Inter_ref_01_04 or Inter_ref_02_04 or Inter_ref_03_04 or Inter_ref_04_04 + ) + if (IsInterChroma && mv_below8x8_curr == 1'b0) + case (blk4x4_inter_calculate_counter) + 4'd4: + begin + Inter_C_window_0_0 <= Inter_ref_00_00; Inter_C_window_1_0 <= Inter_ref_01_00; + Inter_C_window_2_0 <= Inter_ref_02_00; + Inter_C_window_0_1 <= Inter_ref_00_01; Inter_C_window_1_1 <= Inter_ref_01_01; + Inter_C_window_2_1 <= Inter_ref_02_01; + Inter_C_window_0_2 <= Inter_ref_00_02; Inter_C_window_1_2 <= Inter_ref_01_02; + Inter_C_window_2_2 <= Inter_ref_02_02; + end + 4'd3: + begin + Inter_C_window_0_0 <= Inter_ref_02_00; Inter_C_window_1_0 <= Inter_ref_03_00; + Inter_C_window_2_0 <= Inter_ref_04_00; + Inter_C_window_0_1 <= Inter_ref_02_01; Inter_C_window_1_1 <= Inter_ref_03_01; + Inter_C_window_2_1 <= Inter_ref_04_01; + Inter_C_window_0_2 <= Inter_ref_02_02; Inter_C_window_1_2 <= Inter_ref_03_02; + Inter_C_window_2_2 <= Inter_ref_04_02; + end + 4'd2: + begin + Inter_C_window_0_0 <= Inter_ref_00_02; Inter_C_window_1_0 <= Inter_ref_01_02; + Inter_C_window_2_0 <= Inter_ref_02_02; + Inter_C_window_0_1 <= Inter_ref_00_03; Inter_C_window_1_1 <= Inter_ref_01_03; + Inter_C_window_2_1 <= Inter_ref_02_03; + Inter_C_window_0_2 <= Inter_ref_00_04; Inter_C_window_1_2 <= Inter_ref_01_04; + Inter_C_window_2_2 <= Inter_ref_02_04; + end + 4'd1: + begin + Inter_C_window_0_0 <= Inter_ref_02_02; Inter_C_window_1_0 <= Inter_ref_03_02; + Inter_C_window_2_0 <= Inter_ref_04_02; + Inter_C_window_0_1 <= Inter_ref_02_03; Inter_C_window_1_1 <= Inter_ref_03_03; + Inter_C_window_2_1 <= Inter_ref_04_03; + Inter_C_window_0_2 <= Inter_ref_02_04; Inter_C_window_1_2 <= Inter_ref_03_04; + Inter_C_window_2_2 <= Inter_ref_04_04; + end + default: + begin + Inter_C_window_0_0 <= 0; Inter_C_window_1_0 <= 0;Inter_C_window_2_0 <= 0; + Inter_C_window_0_1 <= 0; Inter_C_window_1_1 <= 0;Inter_C_window_2_1 <= 0; + Inter_C_window_0_2 <= 0; Inter_C_window_1_2 <= 0;Inter_C_window_2_2 <= 0; + end + endcase + else if (IsInterChroma && mv_below8x8_curr == 1'b1) + case (blk4x4_inter_calculate_counter) + 4'd1: + begin + Inter_C_window_0_0 <= Inter_ref_00_00; Inter_C_window_1_0 <= Inter_ref_01_00; + Inter_C_window_2_0 <= Inter_ref_02_00; + Inter_C_window_0_1 <= Inter_ref_00_01; Inter_C_window_1_1 <= Inter_ref_01_01; + Inter_C_window_2_1 <= Inter_ref_02_01; + Inter_C_window_0_2 <= Inter_ref_00_02; Inter_C_window_1_2 <= Inter_ref_01_02; + Inter_C_window_2_2 <= Inter_ref_02_02; + end + default: + begin + Inter_C_window_0_0 <= 0; Inter_C_window_1_0 <= 0;Inter_C_window_2_0 <= 0; + Inter_C_window_0_1 <= 0; Inter_C_window_1_1 <= 0;Inter_C_window_2_1 <= 0; + Inter_C_window_0_2 <= 0; Inter_C_window_1_2 <= 0;Inter_C_window_2_2 <= 0; + end + endcase + else + begin + Inter_C_window_0_0 <= 0; Inter_C_window_1_0 <= 0;Inter_C_window_2_0 <= 0; + Inter_C_window_0_1 <= 0; Inter_C_window_1_1 <= 0;Inter_C_window_2_1 <= 0; + Inter_C_window_0_2 <= 0; Inter_C_window_1_2 <= 0;Inter_C_window_2_2 <= 0; + end + +endmodule + + + + + + + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/Inter_pred_top.v b/demo_chip_rtl/rtl/nova/trunk/src/Inter_pred_top.v new file mode 100644 index 0000000..0b03bef --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/Inter_pred_top.v @@ -0,0 +1,703 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : Inter_pred_top.v +// Generated : Oct 28, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Top module of Inter prediction, including +// Inter_pred_pipeline.v +// Inter_pred_reg_control.v +// Inter_pred_sliding_window.v +// Inter_pred_LPE.v +// Inter_pred_CPE.v +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module Inter_pred_top (clk,gclk_Inter_ref_rf,reset_n,mb_num_h,mb_num_v,trigger_blk4x4_inter_pred,blk4x4_rec_counter, + mb_type_general_bit3,mv_is16x16,mv_below8x8,mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3, + mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3,ref_frame_RAM_dout, + + Inter_pred_out0,Inter_pred_out1,Inter_pred_out2,Inter_pred_out3, + blk4x4_inter_preload_counter,blk4x4_inter_calculate_counter,Inter_chroma2x2_counter, + mv_below8x8_curr,pos_FracL,end_of_one_blk4x4_inter,Inter_blk4x4_pred_output_valid, + ref_frame_RAM_rd,ref_frame_RAM_rd_addr); + input clk; + input gclk_Inter_ref_rf; + input reset_n; + input [3:0] mb_num_h,mb_num_v; + input trigger_blk4x4_inter_pred; + input [4:0] blk4x4_rec_counter; + input mb_type_general_bit3; + input mv_is16x16; + input [3:0] mv_below8x8; + input [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3; + input [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3; + input [31:0] ref_frame_RAM_dout; + + output [7:0] Inter_pred_out0,Inter_pred_out1,Inter_pred_out2,Inter_pred_out3; + output [5:0] blk4x4_inter_preload_counter; + output [3:0] blk4x4_inter_calculate_counter; + output [1:0] Inter_chroma2x2_counter; + output mv_below8x8_curr; + output [3:0] pos_FracL; + output end_of_one_blk4x4_inter; + output [1:0] Inter_blk4x4_pred_output_valid; + output ref_frame_RAM_rd; + output [13:0] ref_frame_RAM_rd_addr; + + wire [7:0] LPE0_out,LPE1_out,LPE2_out,LPE3_out; + wire [7:0] CPE0_out,CPE1_out,CPE2_out,CPE3_out; + wire [5:0] blk4x4_inter_preload_counter; + wire mv_below8x8_curr; + wire IsInterLuma,IsInterChroma; + wire Is_InterChromaCopy; + wire [8:0] xInt_addr_unclip; + wire [1:0] xInt_org_unclip_1to0; + wire [2:0] xFracC,yFracC; + + wire [7:0] Inter_ref_00_00,Inter_ref_01_00,Inter_ref_02_00,Inter_ref_03_00,Inter_ref_04_00,Inter_ref_05_00; + wire [7:0] Inter_ref_06_00,Inter_ref_07_00,Inter_ref_08_00,Inter_ref_09_00,Inter_ref_10_00,Inter_ref_11_00,Inter_ref_12_00; + wire [7:0] Inter_ref_00_01,Inter_ref_01_01,Inter_ref_02_01,Inter_ref_03_01,Inter_ref_04_01,Inter_ref_05_01; + wire [7:0] Inter_ref_06_01,Inter_ref_07_01,Inter_ref_08_01,Inter_ref_09_01,Inter_ref_10_01,Inter_ref_11_01,Inter_ref_12_01; + wire [7:0] Inter_ref_00_02,Inter_ref_01_02,Inter_ref_02_02,Inter_ref_03_02,Inter_ref_04_02,Inter_ref_05_02; + wire [7:0] Inter_ref_06_02,Inter_ref_07_02,Inter_ref_08_02,Inter_ref_09_02,Inter_ref_10_02,Inter_ref_11_02,Inter_ref_12_02; + wire [7:0] Inter_ref_00_03,Inter_ref_01_03,Inter_ref_02_03,Inter_ref_03_03,Inter_ref_04_03,Inter_ref_05_03; + wire [7:0] Inter_ref_06_03,Inter_ref_07_03,Inter_ref_08_03,Inter_ref_09_03,Inter_ref_10_03,Inter_ref_11_03,Inter_ref_12_03; + wire [7:0] Inter_ref_00_04,Inter_ref_01_04,Inter_ref_02_04,Inter_ref_03_04,Inter_ref_04_04,Inter_ref_05_04; + wire [7:0] Inter_ref_06_04,Inter_ref_07_04,Inter_ref_08_04,Inter_ref_09_04,Inter_ref_10_04,Inter_ref_11_04,Inter_ref_12_04; + wire [7:0] Inter_ref_00_05,Inter_ref_01_05,Inter_ref_02_05,Inter_ref_03_05,Inter_ref_04_05,Inter_ref_05_05; + wire [7:0] Inter_ref_06_05,Inter_ref_07_05,Inter_ref_08_05,Inter_ref_09_05,Inter_ref_10_05,Inter_ref_11_05,Inter_ref_12_05; + wire [7:0] Inter_ref_00_06,Inter_ref_01_06,Inter_ref_02_06,Inter_ref_03_06,Inter_ref_04_06,Inter_ref_05_06; + wire [7:0] Inter_ref_06_06,Inter_ref_07_06,Inter_ref_08_06,Inter_ref_09_06,Inter_ref_10_06,Inter_ref_11_06,Inter_ref_12_06; + wire [7:0] Inter_ref_00_07,Inter_ref_01_07,Inter_ref_02_07,Inter_ref_03_07,Inter_ref_04_07,Inter_ref_05_07; + wire [7:0] Inter_ref_06_07,Inter_ref_07_07,Inter_ref_08_07,Inter_ref_09_07,Inter_ref_10_07,Inter_ref_11_07,Inter_ref_12_07; + wire [7:0] Inter_ref_00_08,Inter_ref_01_08,Inter_ref_02_08,Inter_ref_03_08,Inter_ref_04_08,Inter_ref_05_08; + wire [7:0] Inter_ref_06_08,Inter_ref_07_08,Inter_ref_08_08,Inter_ref_09_08,Inter_ref_10_08,Inter_ref_11_08,Inter_ref_12_08; + wire [7:0] Inter_ref_00_09,Inter_ref_01_09,Inter_ref_02_09,Inter_ref_03_09,Inter_ref_04_09,Inter_ref_05_09; + wire [7:0] Inter_ref_06_09,Inter_ref_07_09,Inter_ref_08_09,Inter_ref_09_09,Inter_ref_10_09,Inter_ref_11_09,Inter_ref_12_09; + wire [7:0] Inter_ref_00_10,Inter_ref_01_10,Inter_ref_02_10,Inter_ref_03_10,Inter_ref_04_10,Inter_ref_05_10; + wire [7:0] Inter_ref_06_10,Inter_ref_07_10,Inter_ref_08_10,Inter_ref_09_10,Inter_ref_10_10,Inter_ref_11_10,Inter_ref_12_10; + wire [7:0] Inter_ref_00_11,Inter_ref_01_11,Inter_ref_02_11,Inter_ref_03_11,Inter_ref_04_11,Inter_ref_05_11; + wire [7:0] Inter_ref_06_11,Inter_ref_07_11,Inter_ref_08_11,Inter_ref_09_11,Inter_ref_10_11,Inter_ref_11_11,Inter_ref_12_11; + wire [7:0] Inter_ref_00_12,Inter_ref_01_12,Inter_ref_02_12,Inter_ref_03_12,Inter_ref_04_12,Inter_ref_05_12; + wire [7:0] Inter_ref_06_12,Inter_ref_07_12,Inter_ref_08_12,Inter_ref_09_12,Inter_ref_10_12,Inter_ref_11_12,Inter_ref_12_12; + + wire [7:0] Inter_pix_copy0,Inter_pix_copy1,Inter_pix_copy2,Inter_pix_copy3; + wire [7:0] Inter_H_window_0_0,Inter_H_window_1_0,Inter_H_window_2_0,Inter_H_window_3_0,Inter_H_window_4_0,Inter_H_window_5_0; + wire [7:0] Inter_H_window_0_1,Inter_H_window_1_1,Inter_H_window_2_1,Inter_H_window_3_1,Inter_H_window_4_1,Inter_H_window_5_1; + wire [7:0] Inter_H_window_0_2,Inter_H_window_1_2,Inter_H_window_2_2,Inter_H_window_3_2,Inter_H_window_4_2,Inter_H_window_5_2; + wire [7:0] Inter_H_window_0_3,Inter_H_window_1_3,Inter_H_window_2_3,Inter_H_window_3_3,Inter_H_window_4_3,Inter_H_window_5_3; + wire [7:0] Inter_H_window_0_4,Inter_H_window_1_4,Inter_H_window_2_4,Inter_H_window_3_4,Inter_H_window_4_4,Inter_H_window_5_4; + wire [7:0] Inter_H_window_0_5,Inter_H_window_1_5,Inter_H_window_2_5,Inter_H_window_3_5,Inter_H_window_4_5,Inter_H_window_5_5; + wire [7:0] Inter_H_window_0_6,Inter_H_window_1_6,Inter_H_window_2_6,Inter_H_window_3_6,Inter_H_window_4_6,Inter_H_window_5_6; + wire [7:0] Inter_H_window_0_7,Inter_H_window_1_7,Inter_H_window_2_7,Inter_H_window_3_7,Inter_H_window_4_7,Inter_H_window_5_7; + wire [7:0] Inter_H_window_0_8,Inter_H_window_1_8,Inter_H_window_2_8,Inter_H_window_3_8,Inter_H_window_4_8,Inter_H_window_5_8; + wire [7:0] Inter_V_window_0,Inter_V_window_1,Inter_V_window_2,Inter_V_window_3,Inter_V_window_4; + wire [7:0] Inter_V_window_5,Inter_V_window_6,Inter_V_window_7,Inter_V_window_8; + wire [7:0] Inter_C_window_0_0,Inter_C_window_1_0,Inter_C_window_2_0; + wire [7:0] Inter_C_window_0_1,Inter_C_window_1_1,Inter_C_window_2_1; + wire [7:0] Inter_C_window_0_2,Inter_C_window_1_2,Inter_C_window_2_2; + wire [7:0] Inter_bi_window_0,Inter_bi_window_1,Inter_bi_window_2,Inter_bi_window_3; + + Inter_pred_pipeline Inter_pred_pipeline( + .clk(clk), + .reset_n(reset_n), + .mb_num_h(mb_num_h), + .mb_num_v(mb_num_v), + .trigger_blk4x4_inter_pred(trigger_blk4x4_inter_pred), + .blk4x4_rec_counter(blk4x4_rec_counter), + .mb_type_general_bit3(mb_type_general_bit3), + .mv_is16x16(mv_is16x16), + .mv_below8x8(mv_below8x8), + .mvx_CurrMb0(mvx_CurrMb0), + .mvx_CurrMb1(mvx_CurrMb1), + .mvx_CurrMb2(mvx_CurrMb2), + .mvx_CurrMb3(mvx_CurrMb3), + .mvy_CurrMb0(mvy_CurrMb0), + .mvy_CurrMb1(mvy_CurrMb1), + .mvy_CurrMb2(mvy_CurrMb2), + .mvy_CurrMb3(mvy_CurrMb3), + .Inter_pix_copy0(Inter_pix_copy0), + .Inter_pix_copy1(Inter_pix_copy1), + .Inter_pix_copy2(Inter_pix_copy2), + .Inter_pix_copy3(Inter_pix_copy3), + .LPE0_out(LPE0_out), + .LPE1_out(LPE1_out), + .LPE2_out(LPE2_out), + .LPE3_out(LPE3_out), + .CPE0_out(CPE0_out), + .CPE1_out(CPE1_out), + .CPE2_out(CPE2_out), + .CPE3_out(CPE3_out), + + .mv_below8x8_curr(mv_below8x8_curr), + .blk4x4_inter_preload_counter(blk4x4_inter_preload_counter), + .blk4x4_inter_calculate_counter(blk4x4_inter_calculate_counter), + .Inter_chroma2x2_counter(Inter_chroma2x2_counter), + .end_of_one_blk4x4_inter(end_of_one_blk4x4_inter), + .IsInterLuma(IsInterLuma), + .IsInterChroma(IsInterChroma), + .Is_InterChromaCopy(Is_InterChromaCopy), + .xInt_addr_unclip(xInt_addr_unclip), + .xInt_org_unclip_1to0(xInt_org_unclip_1to0), + .pos_FracL(pos_FracL), + .xFracC(xFracC), + .yFracC(yFracC), + .Inter_pred_out0(Inter_pred_out0), + .Inter_pred_out1(Inter_pred_out1), + .Inter_pred_out2(Inter_pred_out2), + .Inter_pred_out3(Inter_pred_out3), + .Inter_blk4x4_pred_output_valid(Inter_blk4x4_pred_output_valid), + .ref_frame_RAM_rd(ref_frame_RAM_rd), + .ref_frame_RAM_rd_addr(ref_frame_RAM_rd_addr) + ); + + Inter_pred_reg_ctrl Inter_pred_reg_ctrl ( + .gclk_Inter_ref_rf(gclk_Inter_ref_rf), + .reset_n(reset_n), + .blk4x4_inter_preload_counter(blk4x4_inter_preload_counter), + .ref_frame_RAM_dout(ref_frame_RAM_dout), + .IsInterLuma(IsInterLuma), + .IsInterChroma(IsInterChroma), + .xInt_addr_unclip(xInt_addr_unclip), + .xInt_org_unclip_1to0(xInt_org_unclip_1to0), + .pos_FracL(pos_FracL), + .xFracC(xFracC), + .yFracC(yFracC), + .mv_below8x8_curr(mv_below8x8_curr), + + .Inter_ref_00_00(Inter_ref_00_00), + .Inter_ref_01_00(Inter_ref_01_00), + .Inter_ref_02_00(Inter_ref_02_00), + .Inter_ref_03_00(Inter_ref_03_00), + .Inter_ref_04_00(Inter_ref_04_00), + .Inter_ref_05_00(Inter_ref_05_00), + .Inter_ref_06_00(Inter_ref_06_00), + .Inter_ref_07_00(Inter_ref_07_00), + .Inter_ref_08_00(Inter_ref_08_00), + .Inter_ref_09_00(Inter_ref_09_00), + .Inter_ref_10_00(Inter_ref_10_00), + .Inter_ref_11_00(Inter_ref_11_00), + .Inter_ref_12_00(Inter_ref_12_00), + .Inter_ref_00_01(Inter_ref_00_01), + .Inter_ref_01_01(Inter_ref_01_01), + .Inter_ref_02_01(Inter_ref_02_01), + .Inter_ref_03_01(Inter_ref_03_01), + .Inter_ref_04_01(Inter_ref_04_01), + .Inter_ref_05_01(Inter_ref_05_01), + .Inter_ref_06_01(Inter_ref_06_01), + .Inter_ref_07_01(Inter_ref_07_01), + .Inter_ref_08_01(Inter_ref_08_01), + .Inter_ref_09_01(Inter_ref_09_01), + .Inter_ref_10_01(Inter_ref_10_01), + .Inter_ref_11_01(Inter_ref_11_01), + .Inter_ref_12_01(Inter_ref_12_01), + .Inter_ref_00_02(Inter_ref_00_02), + .Inter_ref_01_02(Inter_ref_01_02), + .Inter_ref_02_02(Inter_ref_02_02), + .Inter_ref_03_02(Inter_ref_03_02), + .Inter_ref_04_02(Inter_ref_04_02), + .Inter_ref_05_02(Inter_ref_05_02), + .Inter_ref_06_02(Inter_ref_06_02), + .Inter_ref_07_02(Inter_ref_07_02), + .Inter_ref_08_02(Inter_ref_08_02), + .Inter_ref_09_02(Inter_ref_09_02), + .Inter_ref_10_02(Inter_ref_10_02), + .Inter_ref_11_02(Inter_ref_11_02), + .Inter_ref_12_02(Inter_ref_12_02), + .Inter_ref_00_03(Inter_ref_00_03), + .Inter_ref_01_03(Inter_ref_01_03), + .Inter_ref_02_03(Inter_ref_02_03), + .Inter_ref_03_03(Inter_ref_03_03), + .Inter_ref_04_03(Inter_ref_04_03), + .Inter_ref_05_03(Inter_ref_05_03), + .Inter_ref_06_03(Inter_ref_06_03), + .Inter_ref_07_03(Inter_ref_07_03), + .Inter_ref_08_03(Inter_ref_08_03), + .Inter_ref_09_03(Inter_ref_09_03), + .Inter_ref_10_03(Inter_ref_10_03), + .Inter_ref_11_03(Inter_ref_11_03), + .Inter_ref_12_03(Inter_ref_12_03), + .Inter_ref_00_04(Inter_ref_00_04), + .Inter_ref_01_04(Inter_ref_01_04), + .Inter_ref_02_04(Inter_ref_02_04), + .Inter_ref_03_04(Inter_ref_03_04), + .Inter_ref_04_04(Inter_ref_04_04), + .Inter_ref_05_04(Inter_ref_05_04), + .Inter_ref_06_04(Inter_ref_06_04), + .Inter_ref_07_04(Inter_ref_07_04), + .Inter_ref_08_04(Inter_ref_08_04), + .Inter_ref_09_04(Inter_ref_09_04), + .Inter_ref_10_04(Inter_ref_10_04), + .Inter_ref_11_04(Inter_ref_11_04), + .Inter_ref_12_04(Inter_ref_12_04), + .Inter_ref_00_05(Inter_ref_00_05), + .Inter_ref_01_05(Inter_ref_01_05), + .Inter_ref_02_05(Inter_ref_02_05), + .Inter_ref_03_05(Inter_ref_03_05), + .Inter_ref_04_05(Inter_ref_04_05), + .Inter_ref_05_05(Inter_ref_05_05), + .Inter_ref_06_05(Inter_ref_06_05), + .Inter_ref_07_05(Inter_ref_07_05), + .Inter_ref_08_05(Inter_ref_08_05), + .Inter_ref_09_05(Inter_ref_09_05), + .Inter_ref_10_05(Inter_ref_10_05), + .Inter_ref_11_05(Inter_ref_11_05), + .Inter_ref_12_05(Inter_ref_12_05), + .Inter_ref_00_06(Inter_ref_00_06), + .Inter_ref_01_06(Inter_ref_01_06), + .Inter_ref_02_06(Inter_ref_02_06), + .Inter_ref_03_06(Inter_ref_03_06), + .Inter_ref_04_06(Inter_ref_04_06), + .Inter_ref_05_06(Inter_ref_05_06), + .Inter_ref_06_06(Inter_ref_06_06), + .Inter_ref_07_06(Inter_ref_07_06), + .Inter_ref_08_06(Inter_ref_08_06), + .Inter_ref_09_06(Inter_ref_09_06), + .Inter_ref_10_06(Inter_ref_10_06), + .Inter_ref_11_06(Inter_ref_11_06), + .Inter_ref_12_06(Inter_ref_12_06), + .Inter_ref_00_07(Inter_ref_00_07), + .Inter_ref_01_07(Inter_ref_01_07), + .Inter_ref_02_07(Inter_ref_02_07), + .Inter_ref_03_07(Inter_ref_03_07), + .Inter_ref_04_07(Inter_ref_04_07), + .Inter_ref_05_07(Inter_ref_05_07), + .Inter_ref_06_07(Inter_ref_06_07), + .Inter_ref_07_07(Inter_ref_07_07), + .Inter_ref_08_07(Inter_ref_08_07), + .Inter_ref_09_07(Inter_ref_09_07), + .Inter_ref_10_07(Inter_ref_10_07), + .Inter_ref_11_07(Inter_ref_11_07), + .Inter_ref_12_07(Inter_ref_12_07), + .Inter_ref_00_08(Inter_ref_00_08), + .Inter_ref_01_08(Inter_ref_01_08), + .Inter_ref_02_08(Inter_ref_02_08), + .Inter_ref_03_08(Inter_ref_03_08), + .Inter_ref_04_08(Inter_ref_04_08), + .Inter_ref_05_08(Inter_ref_05_08), + .Inter_ref_06_08(Inter_ref_06_08), + .Inter_ref_07_08(Inter_ref_07_08), + .Inter_ref_08_08(Inter_ref_08_08), + .Inter_ref_09_08(Inter_ref_09_08), + .Inter_ref_10_08(Inter_ref_10_08), + .Inter_ref_11_08(Inter_ref_11_08), + .Inter_ref_12_08(Inter_ref_12_08), + .Inter_ref_00_09(Inter_ref_00_09), + .Inter_ref_01_09(Inter_ref_01_09), + .Inter_ref_02_09(Inter_ref_02_09), + .Inter_ref_03_09(Inter_ref_03_09), + .Inter_ref_04_09(Inter_ref_04_09), + .Inter_ref_05_09(Inter_ref_05_09), + .Inter_ref_06_09(Inter_ref_06_09), + .Inter_ref_07_09(Inter_ref_07_09), + .Inter_ref_08_09(Inter_ref_08_09), + .Inter_ref_09_09(Inter_ref_09_09), + .Inter_ref_10_09(Inter_ref_10_09), + .Inter_ref_11_09(Inter_ref_11_09), + .Inter_ref_12_09(Inter_ref_12_09), + .Inter_ref_00_10(Inter_ref_00_10), + .Inter_ref_01_10(Inter_ref_01_10), + .Inter_ref_02_10(Inter_ref_02_10), + .Inter_ref_03_10(Inter_ref_03_10), + .Inter_ref_04_10(Inter_ref_04_10), + .Inter_ref_05_10(Inter_ref_05_10), + .Inter_ref_06_10(Inter_ref_06_10), + .Inter_ref_07_10(Inter_ref_07_10), + .Inter_ref_08_10(Inter_ref_08_10), + .Inter_ref_09_10(Inter_ref_09_10), + .Inter_ref_10_10(Inter_ref_10_10), + .Inter_ref_11_10(Inter_ref_11_10), + .Inter_ref_12_10(Inter_ref_12_10), + .Inter_ref_00_11(Inter_ref_00_11), + .Inter_ref_01_11(Inter_ref_01_11), + .Inter_ref_02_11(Inter_ref_02_11), + .Inter_ref_03_11(Inter_ref_03_11), + .Inter_ref_04_11(Inter_ref_04_11), + .Inter_ref_05_11(Inter_ref_05_11), + .Inter_ref_06_11(Inter_ref_06_11), + .Inter_ref_07_11(Inter_ref_07_11), + .Inter_ref_08_11(Inter_ref_08_11), + .Inter_ref_09_11(Inter_ref_09_11), + .Inter_ref_10_11(Inter_ref_10_11), + .Inter_ref_11_11(Inter_ref_11_11), + .Inter_ref_12_11(Inter_ref_12_11), + .Inter_ref_00_12(Inter_ref_00_12), + .Inter_ref_01_12(Inter_ref_01_12), + .Inter_ref_02_12(Inter_ref_02_12), + .Inter_ref_03_12(Inter_ref_03_12), + .Inter_ref_04_12(Inter_ref_04_12), + .Inter_ref_05_12(Inter_ref_05_12), + .Inter_ref_06_12(Inter_ref_06_12), + .Inter_ref_07_12(Inter_ref_07_12), + .Inter_ref_08_12(Inter_ref_08_12), + .Inter_ref_09_12(Inter_ref_09_12), + .Inter_ref_10_12(Inter_ref_10_12), + .Inter_ref_11_12(Inter_ref_11_12), + .Inter_ref_12_12(Inter_ref_12_12) + ); + Inter_pred_sliding_window Inter_pred_sliding_window ( + .IsInterLuma(IsInterLuma), + .IsInterChroma(IsInterChroma), + .Is_InterChromaCopy(Is_InterChromaCopy), + .mv_below8x8_curr(mv_below8x8_curr), + .pos_FracL(pos_FracL), + .blk4x4_rec_counter_1to0(blk4x4_rec_counter[1:0]), + .blk4x4_inter_calculate_counter(blk4x4_inter_calculate_counter), + .Inter_ref_00_00(Inter_ref_00_00), + .Inter_ref_01_00(Inter_ref_01_00), + .Inter_ref_02_00(Inter_ref_02_00), + .Inter_ref_03_00(Inter_ref_03_00), + .Inter_ref_04_00(Inter_ref_04_00), + .Inter_ref_05_00(Inter_ref_05_00), + .Inter_ref_06_00(Inter_ref_06_00), + .Inter_ref_07_00(Inter_ref_07_00), + .Inter_ref_08_00(Inter_ref_08_00), + .Inter_ref_09_00(Inter_ref_09_00), + .Inter_ref_10_00(Inter_ref_10_00), + .Inter_ref_11_00(Inter_ref_11_00), + .Inter_ref_12_00(Inter_ref_12_00), + .Inter_ref_00_01(Inter_ref_00_01), + .Inter_ref_01_01(Inter_ref_01_01), + .Inter_ref_02_01(Inter_ref_02_01), + .Inter_ref_03_01(Inter_ref_03_01), + .Inter_ref_04_01(Inter_ref_04_01), + .Inter_ref_05_01(Inter_ref_05_01), + .Inter_ref_06_01(Inter_ref_06_01), + .Inter_ref_07_01(Inter_ref_07_01), + .Inter_ref_08_01(Inter_ref_08_01), + .Inter_ref_09_01(Inter_ref_09_01), + .Inter_ref_10_01(Inter_ref_10_01), + .Inter_ref_11_01(Inter_ref_11_01), + .Inter_ref_12_01(Inter_ref_12_01), + .Inter_ref_00_02(Inter_ref_00_02), + .Inter_ref_01_02(Inter_ref_01_02), + .Inter_ref_02_02(Inter_ref_02_02), + .Inter_ref_03_02(Inter_ref_03_02), + .Inter_ref_04_02(Inter_ref_04_02), + .Inter_ref_05_02(Inter_ref_05_02), + .Inter_ref_06_02(Inter_ref_06_02), + .Inter_ref_07_02(Inter_ref_07_02), + .Inter_ref_08_02(Inter_ref_08_02), + .Inter_ref_09_02(Inter_ref_09_02), + .Inter_ref_10_02(Inter_ref_10_02), + .Inter_ref_11_02(Inter_ref_11_02), + .Inter_ref_12_02(Inter_ref_12_02), + .Inter_ref_00_03(Inter_ref_00_03), + .Inter_ref_01_03(Inter_ref_01_03), + .Inter_ref_02_03(Inter_ref_02_03), + .Inter_ref_03_03(Inter_ref_03_03), + .Inter_ref_04_03(Inter_ref_04_03), + .Inter_ref_05_03(Inter_ref_05_03), + .Inter_ref_06_03(Inter_ref_06_03), + .Inter_ref_07_03(Inter_ref_07_03), + .Inter_ref_08_03(Inter_ref_08_03), + .Inter_ref_09_03(Inter_ref_09_03), + .Inter_ref_10_03(Inter_ref_10_03), + .Inter_ref_11_03(Inter_ref_11_03), + .Inter_ref_12_03(Inter_ref_12_03), + .Inter_ref_00_04(Inter_ref_00_04), + .Inter_ref_01_04(Inter_ref_01_04), + .Inter_ref_02_04(Inter_ref_02_04), + .Inter_ref_03_04(Inter_ref_03_04), + .Inter_ref_04_04(Inter_ref_04_04), + .Inter_ref_05_04(Inter_ref_05_04), + .Inter_ref_06_04(Inter_ref_06_04), + .Inter_ref_07_04(Inter_ref_07_04), + .Inter_ref_08_04(Inter_ref_08_04), + .Inter_ref_09_04(Inter_ref_09_04), + .Inter_ref_10_04(Inter_ref_10_04), + .Inter_ref_11_04(Inter_ref_11_04), + .Inter_ref_12_04(Inter_ref_12_04), + .Inter_ref_00_05(Inter_ref_00_05), + .Inter_ref_01_05(Inter_ref_01_05), + .Inter_ref_02_05(Inter_ref_02_05), + .Inter_ref_03_05(Inter_ref_03_05), + .Inter_ref_04_05(Inter_ref_04_05), + .Inter_ref_05_05(Inter_ref_05_05), + .Inter_ref_06_05(Inter_ref_06_05), + .Inter_ref_07_05(Inter_ref_07_05), + .Inter_ref_08_05(Inter_ref_08_05), + .Inter_ref_09_05(Inter_ref_09_05), + .Inter_ref_10_05(Inter_ref_10_05), + .Inter_ref_11_05(Inter_ref_11_05), + .Inter_ref_12_05(Inter_ref_12_05), + .Inter_ref_00_06(Inter_ref_00_06), + .Inter_ref_01_06(Inter_ref_01_06), + .Inter_ref_02_06(Inter_ref_02_06), + .Inter_ref_03_06(Inter_ref_03_06), + .Inter_ref_04_06(Inter_ref_04_06), + .Inter_ref_05_06(Inter_ref_05_06), + .Inter_ref_06_06(Inter_ref_06_06), + .Inter_ref_07_06(Inter_ref_07_06), + .Inter_ref_08_06(Inter_ref_08_06), + .Inter_ref_09_06(Inter_ref_09_06), + .Inter_ref_10_06(Inter_ref_10_06), + .Inter_ref_11_06(Inter_ref_11_06), + .Inter_ref_12_06(Inter_ref_12_06), + .Inter_ref_00_07(Inter_ref_00_07), + .Inter_ref_01_07(Inter_ref_01_07), + .Inter_ref_02_07(Inter_ref_02_07), + .Inter_ref_03_07(Inter_ref_03_07), + .Inter_ref_04_07(Inter_ref_04_07), + .Inter_ref_05_07(Inter_ref_05_07), + .Inter_ref_06_07(Inter_ref_06_07), + .Inter_ref_07_07(Inter_ref_07_07), + .Inter_ref_08_07(Inter_ref_08_07), + .Inter_ref_09_07(Inter_ref_09_07), + .Inter_ref_10_07(Inter_ref_10_07), + .Inter_ref_11_07(Inter_ref_11_07), + .Inter_ref_12_07(Inter_ref_12_07), + .Inter_ref_00_08(Inter_ref_00_08), + .Inter_ref_01_08(Inter_ref_01_08), + .Inter_ref_02_08(Inter_ref_02_08), + .Inter_ref_03_08(Inter_ref_03_08), + .Inter_ref_04_08(Inter_ref_04_08), + .Inter_ref_05_08(Inter_ref_05_08), + .Inter_ref_06_08(Inter_ref_06_08), + .Inter_ref_07_08(Inter_ref_07_08), + .Inter_ref_08_08(Inter_ref_08_08), + .Inter_ref_09_08(Inter_ref_09_08), + .Inter_ref_10_08(Inter_ref_10_08), + .Inter_ref_11_08(Inter_ref_11_08), + .Inter_ref_12_08(Inter_ref_12_08), + .Inter_ref_00_09(Inter_ref_00_09), + .Inter_ref_01_09(Inter_ref_01_09), + .Inter_ref_02_09(Inter_ref_02_09), + .Inter_ref_03_09(Inter_ref_03_09), + .Inter_ref_04_09(Inter_ref_04_09), + .Inter_ref_05_09(Inter_ref_05_09), + .Inter_ref_06_09(Inter_ref_06_09), + .Inter_ref_07_09(Inter_ref_07_09), + .Inter_ref_08_09(Inter_ref_08_09), + .Inter_ref_09_09(Inter_ref_09_09), + .Inter_ref_10_09(Inter_ref_10_09), + .Inter_ref_11_09(Inter_ref_11_09), + .Inter_ref_12_09(Inter_ref_12_09), + .Inter_ref_00_10(Inter_ref_00_10), + .Inter_ref_01_10(Inter_ref_01_10), + .Inter_ref_02_10(Inter_ref_02_10), + .Inter_ref_03_10(Inter_ref_03_10), + .Inter_ref_04_10(Inter_ref_04_10), + .Inter_ref_05_10(Inter_ref_05_10), + .Inter_ref_06_10(Inter_ref_06_10), + .Inter_ref_07_10(Inter_ref_07_10), + .Inter_ref_08_10(Inter_ref_08_10), + .Inter_ref_09_10(Inter_ref_09_10), + .Inter_ref_10_10(Inter_ref_10_10), + .Inter_ref_11_10(Inter_ref_11_10), + .Inter_ref_12_10(Inter_ref_12_10), + .Inter_ref_00_11(Inter_ref_00_11), + .Inter_ref_01_11(Inter_ref_01_11), + .Inter_ref_02_11(Inter_ref_02_11), + .Inter_ref_03_11(Inter_ref_03_11), + .Inter_ref_04_11(Inter_ref_04_11), + .Inter_ref_05_11(Inter_ref_05_11), + .Inter_ref_06_11(Inter_ref_06_11), + .Inter_ref_07_11(Inter_ref_07_11), + .Inter_ref_08_11(Inter_ref_08_11), + .Inter_ref_09_11(Inter_ref_09_11), + .Inter_ref_10_11(Inter_ref_10_11), + .Inter_ref_11_11(Inter_ref_11_11), + .Inter_ref_12_11(Inter_ref_12_11), + .Inter_ref_00_12(Inter_ref_00_12), + .Inter_ref_01_12(Inter_ref_01_12), + .Inter_ref_02_12(Inter_ref_02_12), + .Inter_ref_03_12(Inter_ref_03_12), + .Inter_ref_04_12(Inter_ref_04_12), + .Inter_ref_05_12(Inter_ref_05_12), + .Inter_ref_06_12(Inter_ref_06_12), + .Inter_ref_07_12(Inter_ref_07_12), + .Inter_ref_08_12(Inter_ref_08_12), + .Inter_ref_09_12(Inter_ref_09_12), + .Inter_ref_10_12(Inter_ref_10_12), + .Inter_ref_11_12(Inter_ref_11_12), + .Inter_ref_12_12(Inter_ref_12_12), + + .Inter_pix_copy0(Inter_pix_copy0), + .Inter_pix_copy1(Inter_pix_copy1), + .Inter_pix_copy2(Inter_pix_copy2), + .Inter_pix_copy3(Inter_pix_copy3), + .Inter_H_window_0_0(Inter_H_window_0_0), + .Inter_H_window_1_0(Inter_H_window_1_0), + .Inter_H_window_2_0(Inter_H_window_2_0), + .Inter_H_window_3_0(Inter_H_window_3_0), + .Inter_H_window_4_0(Inter_H_window_4_0), + .Inter_H_window_5_0(Inter_H_window_5_0), + .Inter_H_window_0_1(Inter_H_window_0_1), + .Inter_H_window_1_1(Inter_H_window_1_1), + .Inter_H_window_2_1(Inter_H_window_2_1), + .Inter_H_window_3_1(Inter_H_window_3_1), + .Inter_H_window_4_1(Inter_H_window_4_1), + .Inter_H_window_5_1(Inter_H_window_5_1), + .Inter_H_window_0_2(Inter_H_window_0_2), + .Inter_H_window_1_2(Inter_H_window_1_2), + .Inter_H_window_2_2(Inter_H_window_2_2), + .Inter_H_window_3_2(Inter_H_window_3_2), + .Inter_H_window_4_2(Inter_H_window_4_2), + .Inter_H_window_5_2(Inter_H_window_5_2), + .Inter_H_window_0_3(Inter_H_window_0_3), + .Inter_H_window_1_3(Inter_H_window_1_3), + .Inter_H_window_2_3(Inter_H_window_2_3), + .Inter_H_window_3_3(Inter_H_window_3_3), + .Inter_H_window_4_3(Inter_H_window_4_3), + .Inter_H_window_5_3(Inter_H_window_5_3), + .Inter_H_window_0_4(Inter_H_window_0_4), + .Inter_H_window_1_4(Inter_H_window_1_4), + .Inter_H_window_2_4(Inter_H_window_2_4), + .Inter_H_window_3_4(Inter_H_window_3_4), + .Inter_H_window_4_4(Inter_H_window_4_4), + .Inter_H_window_5_4(Inter_H_window_5_4), + .Inter_H_window_0_5(Inter_H_window_0_5), + .Inter_H_window_1_5(Inter_H_window_1_5), + .Inter_H_window_2_5(Inter_H_window_2_5), + .Inter_H_window_3_5(Inter_H_window_3_5), + .Inter_H_window_4_5(Inter_H_window_4_5), + .Inter_H_window_5_5(Inter_H_window_5_5), + .Inter_H_window_0_6(Inter_H_window_0_6), + .Inter_H_window_1_6(Inter_H_window_1_6), + .Inter_H_window_2_6(Inter_H_window_2_6), + .Inter_H_window_3_6(Inter_H_window_3_6), + .Inter_H_window_4_6(Inter_H_window_4_6), + .Inter_H_window_5_6(Inter_H_window_5_6), + .Inter_H_window_0_7(Inter_H_window_0_7), + .Inter_H_window_1_7(Inter_H_window_1_7), + .Inter_H_window_2_7(Inter_H_window_2_7), + .Inter_H_window_3_7(Inter_H_window_3_7), + .Inter_H_window_4_7(Inter_H_window_4_7), + .Inter_H_window_5_7(Inter_H_window_5_7), + .Inter_H_window_0_8(Inter_H_window_0_8), + .Inter_H_window_1_8(Inter_H_window_1_8), + .Inter_H_window_2_8(Inter_H_window_2_8), + .Inter_H_window_3_8(Inter_H_window_3_8), + .Inter_H_window_4_8(Inter_H_window_4_8), + .Inter_H_window_5_8(Inter_H_window_5_8), + .Inter_V_window_0(Inter_V_window_0), + .Inter_V_window_1(Inter_V_window_1), + .Inter_V_window_2(Inter_V_window_2), + .Inter_V_window_3(Inter_V_window_3), + .Inter_V_window_4(Inter_V_window_4), + .Inter_V_window_5(Inter_V_window_5), + .Inter_V_window_6(Inter_V_window_6), + .Inter_V_window_7(Inter_V_window_7), + .Inter_V_window_8(Inter_V_window_8), + .Inter_C_window_0_0(Inter_C_window_0_0), + .Inter_C_window_1_0(Inter_C_window_1_0), + .Inter_C_window_2_0(Inter_C_window_2_0), + .Inter_C_window_0_1(Inter_C_window_0_1), + .Inter_C_window_1_1(Inter_C_window_1_1), + .Inter_C_window_2_1(Inter_C_window_2_1), + .Inter_C_window_0_2(Inter_C_window_0_2), + .Inter_C_window_1_2(Inter_C_window_1_2), + .Inter_C_window_2_2(Inter_C_window_2_2), + .Inter_bi_window_0(Inter_bi_window_0), + .Inter_bi_window_1(Inter_bi_window_1), + .Inter_bi_window_2(Inter_bi_window_2), + .Inter_bi_window_3(Inter_bi_window_3) + ); + + Inter_pred_LPE Inter_pred_LPE ( + .clk(clk), + .reset_n(reset_n), + .pos_FracL(pos_FracL), + .IsInterLuma(IsInterLuma), + .blk4x4_inter_calculate_counter(blk4x4_inter_calculate_counter), + .Inter_H_window_0_0(Inter_H_window_0_0), + .Inter_H_window_1_0(Inter_H_window_1_0), + .Inter_H_window_2_0(Inter_H_window_2_0), + .Inter_H_window_3_0(Inter_H_window_3_0), + .Inter_H_window_4_0(Inter_H_window_4_0), + .Inter_H_window_5_0(Inter_H_window_5_0), + .Inter_H_window_0_1(Inter_H_window_0_1), + .Inter_H_window_1_1(Inter_H_window_1_1), + .Inter_H_window_2_1(Inter_H_window_2_1), + .Inter_H_window_3_1(Inter_H_window_3_1), + .Inter_H_window_4_1(Inter_H_window_4_1), + .Inter_H_window_5_1(Inter_H_window_5_1), + .Inter_H_window_0_2(Inter_H_window_0_2), + .Inter_H_window_1_2(Inter_H_window_1_2), + .Inter_H_window_2_2(Inter_H_window_2_2), + .Inter_H_window_3_2(Inter_H_window_3_2), + .Inter_H_window_4_2(Inter_H_window_4_2), + .Inter_H_window_5_2(Inter_H_window_5_2), + .Inter_H_window_0_3(Inter_H_window_0_3), + .Inter_H_window_1_3(Inter_H_window_1_3), + .Inter_H_window_2_3(Inter_H_window_2_3), + .Inter_H_window_3_3(Inter_H_window_3_3), + .Inter_H_window_4_3(Inter_H_window_4_3), + .Inter_H_window_5_3(Inter_H_window_5_3), + .Inter_H_window_0_4(Inter_H_window_0_4), + .Inter_H_window_1_4(Inter_H_window_1_4), + .Inter_H_window_2_4(Inter_H_window_2_4), + .Inter_H_window_3_4(Inter_H_window_3_4), + .Inter_H_window_4_4(Inter_H_window_4_4), + .Inter_H_window_5_4(Inter_H_window_5_4), + .Inter_H_window_0_5(Inter_H_window_0_5), + .Inter_H_window_1_5(Inter_H_window_1_5), + .Inter_H_window_2_5(Inter_H_window_2_5), + .Inter_H_window_3_5(Inter_H_window_3_5), + .Inter_H_window_4_5(Inter_H_window_4_5), + .Inter_H_window_5_5(Inter_H_window_5_5), + .Inter_H_window_0_6(Inter_H_window_0_6), + .Inter_H_window_1_6(Inter_H_window_1_6), + .Inter_H_window_2_6(Inter_H_window_2_6), + .Inter_H_window_3_6(Inter_H_window_3_6), + .Inter_H_window_4_6(Inter_H_window_4_6), + .Inter_H_window_5_6(Inter_H_window_5_6), + .Inter_H_window_0_7(Inter_H_window_0_7), + .Inter_H_window_1_7(Inter_H_window_1_7), + .Inter_H_window_2_7(Inter_H_window_2_7), + .Inter_H_window_3_7(Inter_H_window_3_7), + .Inter_H_window_4_7(Inter_H_window_4_7), + .Inter_H_window_5_7(Inter_H_window_5_7), + .Inter_H_window_0_8(Inter_H_window_0_8), + .Inter_H_window_1_8(Inter_H_window_1_8), + .Inter_H_window_2_8(Inter_H_window_2_8), + .Inter_H_window_3_8(Inter_H_window_3_8), + .Inter_H_window_4_8(Inter_H_window_4_8), + .Inter_H_window_5_8(Inter_H_window_5_8), + .Inter_V_window_0(Inter_V_window_0), + .Inter_V_window_1(Inter_V_window_1), + .Inter_V_window_2(Inter_V_window_2), + .Inter_V_window_3(Inter_V_window_3), + .Inter_V_window_4(Inter_V_window_4), + .Inter_V_window_5(Inter_V_window_5), + .Inter_V_window_6(Inter_V_window_6), + .Inter_V_window_7(Inter_V_window_7), + .Inter_V_window_8(Inter_V_window_8), + .Inter_bi_window_0(Inter_bi_window_0), + .Inter_bi_window_1(Inter_bi_window_1), + .Inter_bi_window_2(Inter_bi_window_2), + .Inter_bi_window_3(Inter_bi_window_3), + + .LPE0_out(LPE0_out), + .LPE1_out(LPE1_out), + .LPE2_out(LPE2_out), + .LPE3_out(LPE3_out) + ); + Inter_pred_CPE Inter_pred_CPE ( + .xFracC(xFracC), + .yFracC(yFracC), + .Inter_C_window_0_0(Inter_C_window_0_0), + .Inter_C_window_1_0(Inter_C_window_1_0), + .Inter_C_window_2_0(Inter_C_window_2_0), + .Inter_C_window_0_1(Inter_C_window_0_1), + .Inter_C_window_1_1(Inter_C_window_1_1), + .Inter_C_window_2_1(Inter_C_window_2_1), + .Inter_C_window_0_2(Inter_C_window_0_2), + .Inter_C_window_1_2(Inter_C_window_1_2), + .Inter_C_window_2_2(Inter_C_window_2_2), + .CPE0_out(CPE0_out), + .CPE1_out(CPE1_out), + .CPE2_out(CPE2_out), + .CPE3_out(CPE3_out) + ); +endmodule + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/Intra4x4_PredMode_decoding.v b/demo_chip_rtl/rtl/nova/trunk/src/Intra4x4_PredMode_decoding.v new file mode 100644 index 0000000..bcc79a1 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/Intra4x4_PredMode_decoding.v @@ -0,0 +1,333 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : Intra4x4_PredMode_decoding.v +// Generated : May 31, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Decoding the prediction mode for Intra4x4 +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module Intra4x4_PredMode_decoding (clk,reset_n,mb_pred_state,luma4x4BlkIdx,mb_num_h,mb_num_v, + MBTypeGen_mbAddrA,MBTypeGen_mbAddrB_reg,constrained_intra_pred_flag, + rem_intra4x4_pred_mode,prev_intra4x4_pred_mode_flag,Intra4x4PredMode_mbAddrB_dout, + + Intra4x4PredMode_CurrMb, + Intra4x4PredMode_mbAddrB_cs_n,Intra4x4PredMode_mbAddrB_wr_n,Intra4x4PredMode_mbAddrB_rd_addr, + Intra4x4PredMode_mbAddrB_wr_addr,Intra4x4PredMode_mbAddrB_din + ); + input clk,reset_n; + input [2:0] mb_pred_state; + input [3:0] luma4x4BlkIdx; + input [3:0] mb_num_h,mb_num_v; + input [1:0] MBTypeGen_mbAddrA; + input [21:0] MBTypeGen_mbAddrB_reg; + input constrained_intra_pred_flag; + input [2:0] rem_intra4x4_pred_mode; + input prev_intra4x4_pred_mode_flag; + input [15:0] Intra4x4PredMode_mbAddrB_dout; + //input [8:0] pic_num; + + output [63:0] Intra4x4PredMode_CurrMb; + output Intra4x4PredMode_mbAddrB_cs_n,Intra4x4PredMode_mbAddrB_wr_n; + output [3:0] Intra4x4PredMode_mbAddrB_rd_addr,Intra4x4PredMode_mbAddrB_wr_addr; + output [15:0] Intra4x4PredMode_mbAddrB_din; + + reg Intra4x4PredMode_mbAddrB_cs_n,Intra4x4PredMode_mbAddrB_wr_n; + reg [3:0] Intra4x4PredMode_mbAddrB_rd_addr,Intra4x4PredMode_mbAddrB_wr_addr; + reg [15:0] Intra4x4PredMode_mbAddrB_din; + + wire mbAddrA_availability; + wire mbAddrB_availability; + wire mbAddrA; + wire mbAddrB; + wire [3:0] predIntra4x4PredMode; //prediction mode obtained at `prev_intra4x4_pred_mode_flag_s + reg dcOnlyPredictionFlag; + reg [15:0] Intra4x4PredMode_mbAddrA; + reg [63:0] Intra4x4PredMode_CurrMb; + reg [3:0] Intra4x4PredModeA,Intra4x4PredModeB; + + reg [3:0] rem_Intra4x4PredMode; //prediction mode obtained at `rem_intra4x4_pred_mode_s + reg [3:0] predIntra4x4PredMode_reg; //the reg value of predIntra4x4PredMode + + + reg [1:0] MBTypeGen_mbAddrB; + always @ (mb_num_h or MBTypeGen_mbAddrB_reg) + case (mb_num_h) + 0 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[1:0]; + 1 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[3:2]; + 2 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[5:4]; + 3 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[7:6]; + 4 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[9:8]; + 5 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[11:10]; + 6 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[13:12]; + 7 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[15:14]; + 8 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[17:16]; + 9 :MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[19:18]; + 10:MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[21:20]; + default:MBTypeGen_mbAddrB <= 0; + endcase + + //neighboring block decoding for Intra4x4 prediction mode,NO mapping from Blk4x4 order --> raster order + assign mbAddrA_availability = (luma4x4BlkIdx == 0 || luma4x4BlkIdx == 2 + || luma4x4BlkIdx == 8 || luma4x4BlkIdx == 10)? ((mb_num_h == 0)? 1'b0:1'b1):1'b1; + + assign mbAddrB_availability = (luma4x4BlkIdx == 0 || luma4x4BlkIdx == 1 + || luma4x4BlkIdx == 4 || luma4x4BlkIdx == 5)? ((mb_num_v == 0)? 1'b0:1'b1):1'b1; + + assign mbAddrA = (luma4x4BlkIdx == 0 || luma4x4BlkIdx == 2 || luma4x4BlkIdx == 8 + || luma4x4BlkIdx == 10)? 1'b0:1'b1; //0:left MB;1:curr MB + + assign mbAddrB = (luma4x4BlkIdx == 0 || luma4x4BlkIdx == 1 || luma4x4BlkIdx == 4 + || luma4x4BlkIdx == 5)? 1'b0:1'b1; //0:upper MB;1:curr MB + + //dcOnlyPredictionFlag + always @ (mb_pred_state or mbAddrA_availability or mbAddrB_availability or mbAddrA or mbAddrB or + MBTypeGen_mbAddrA or MBTypeGen_mbAddrB or constrained_intra_pred_flag) + if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s) + begin + if (mbAddrA_availability == 0) + dcOnlyPredictionFlag <= 1; + else if (mbAddrB_availability == 0) + dcOnlyPredictionFlag <= 1; + else if (mbAddrA == 0 && MBTypeGen_mbAddrA < 2 && constrained_intra_pred_flag == 1) + dcOnlyPredictionFlag <= 1; + else if (mbAddrB == 0 && MBTypeGen_mbAddrB < 2 && constrained_intra_pred_flag == 1) + dcOnlyPredictionFlag <= 1; + else + dcOnlyPredictionFlag <= 0; + end + else + dcOnlyPredictionFlag <= 0; + //Intra4x4PredModeA + always @ (mb_pred_state or dcOnlyPredictionFlag or mbAddrA or mbAddrA_availability or MBTypeGen_mbAddrA + or Intra4x4PredMode_mbAddrA or Intra4x4PredMode_CurrMb or luma4x4BlkIdx) + if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s) + begin + if (dcOnlyPredictionFlag == 1) + Intra4x4PredModeA <= 2; + else if (mbAddrA_availability == 1 && mbAddrA == 0 && MBTypeGen_mbAddrA != `MB_addrA_addrB_Intra4x4)//not coded in Intra4x4 + Intra4x4PredModeA <= 2; + else + case (luma4x4BlkIdx) + 0 :Intra4x4PredModeA <= Intra4x4PredMode_mbAddrA[3:0]; + 1 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[3:0]; + 2 :Intra4x4PredModeA <= Intra4x4PredMode_mbAddrA[7:4]; + 3 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[11:8]; + 4 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[7:4]; + 5 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[19:16]; + 6 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[15:12]; + 7 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[27:24]; + 8 :Intra4x4PredModeA <= Intra4x4PredMode_mbAddrA[11:8]; + 9 :Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[35:32]; + 10:Intra4x4PredModeA <= Intra4x4PredMode_mbAddrA[15:12]; + 11:Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[43:40]; + 12:Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[39:36]; + 13:Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[51:48]; + 14:Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[47:44]; + 15:Intra4x4PredModeA <= Intra4x4PredMode_CurrMb[59:56]; + endcase + end + else + Intra4x4PredModeA <= 0; + //Intra4x4PredModeB + always @ (mb_pred_state or dcOnlyPredictionFlag or mbAddrB or mbAddrB_availability or MBTypeGen_mbAddrB + or Intra4x4PredMode_mbAddrB_dout or Intra4x4PredMode_CurrMb or luma4x4BlkIdx) + if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s) + begin + if (dcOnlyPredictionFlag == 1) + Intra4x4PredModeB <= 2; + else if (mbAddrB_availability == 1 && mbAddrB == 0 && MBTypeGen_mbAddrB != `MB_addrA_addrB_Intra4x4) //not coded in Intra4x4 + Intra4x4PredModeB <= 2; + else + case (luma4x4BlkIdx) + 0 :Intra4x4PredModeB <= Intra4x4PredMode_mbAddrB_dout[15:12]; + 1 :Intra4x4PredModeB <= Intra4x4PredMode_mbAddrB_dout[11:8]; + 2 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[3:0]; + 3 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[7:4]; + 4 :Intra4x4PredModeB <= Intra4x4PredMode_mbAddrB_dout[7:4]; + 5 :Intra4x4PredModeB <= Intra4x4PredMode_mbAddrB_dout[3:0]; + 6 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[19:16]; + 7 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[23:20]; + 8 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[11:8]; + 9 :Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[15:12]; + 10:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[35:32]; + 11:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[39:36]; + 12:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[27:24]; + 13:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[31:28]; + 14:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[51:48]; + 15:Intra4x4PredModeB <= Intra4x4PredMode_CurrMb[55:52]; + endcase + end + else + Intra4x4PredModeB <= 0; + //obtain prediction mode at prev_intra4x4_pred_mode_flag_s + assign predIntra4x4PredMode = (Intra4x4PredModeA < Intra4x4PredModeB)? Intra4x4PredModeA:Intra4x4PredModeB; + always @ (posedge clk) + if (reset_n == 0) + predIntra4x4PredMode_reg <= 0; + else if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s && prev_intra4x4_pred_mode_flag == 0) + predIntra4x4PredMode_reg <= predIntra4x4PredMode; + //obtain prediction mode at rem_intra4x4_pred_mode_s + always @ (mb_pred_state or rem_intra4x4_pred_mode or predIntra4x4PredMode_reg) + if (mb_pred_state == `rem_intra4x4_pred_mode_s) + rem_Intra4x4PredMode <= ({1'b0,rem_intra4x4_pred_mode} < predIntra4x4PredMode_reg)? + {1'b0,rem_intra4x4_pred_mode}:(rem_intra4x4_pred_mode + 1); + else + rem_Intra4x4PredMode <= 0; + //----------------------------- + //Intra4x4PredMode_CurrMb write + //----------------------------- + always @ (posedge clk) + if (reset_n == 0) + Intra4x4PredMode_CurrMb <= 0; + else if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s && prev_intra4x4_pred_mode_flag == 1) + case (luma4x4BlkIdx) + 0 :Intra4x4PredMode_CurrMb[3:0] <= predIntra4x4PredMode; + 1 :Intra4x4PredMode_CurrMb[7:4] <= predIntra4x4PredMode; + 2 :Intra4x4PredMode_CurrMb[11:8] <= predIntra4x4PredMode; + 3 :Intra4x4PredMode_CurrMb[15:12] <= predIntra4x4PredMode; + 4 :Intra4x4PredMode_CurrMb[19:16] <= predIntra4x4PredMode; + 5 :Intra4x4PredMode_CurrMb[23:20] <= predIntra4x4PredMode; + 6 :Intra4x4PredMode_CurrMb[27:24] <= predIntra4x4PredMode; + 7 :Intra4x4PredMode_CurrMb[31:28] <= predIntra4x4PredMode; + 8 :Intra4x4PredMode_CurrMb[35:32] <= predIntra4x4PredMode; + 9 :Intra4x4PredMode_CurrMb[39:36] <= predIntra4x4PredMode; + 10 :Intra4x4PredMode_CurrMb[43:40] <= predIntra4x4PredMode; + 11 :Intra4x4PredMode_CurrMb[47:44] <= predIntra4x4PredMode; + 12 :Intra4x4PredMode_CurrMb[51:48] <= predIntra4x4PredMode; + 13 :Intra4x4PredMode_CurrMb[55:52] <= predIntra4x4PredMode; + 14 :Intra4x4PredMode_CurrMb[59:56] <= predIntra4x4PredMode; + 15 :Intra4x4PredMode_CurrMb[63:60] <= predIntra4x4PredMode; + endcase + else if (mb_pred_state == `rem_intra4x4_pred_mode_s) + case (luma4x4BlkIdx) + 0 :Intra4x4PredMode_CurrMb[3:0] <= rem_Intra4x4PredMode; + 1 :Intra4x4PredMode_CurrMb[7:4] <= rem_Intra4x4PredMode; + 2 :Intra4x4PredMode_CurrMb[11:8] <= rem_Intra4x4PredMode; + 3 :Intra4x4PredMode_CurrMb[15:12] <= rem_Intra4x4PredMode; + 4 :Intra4x4PredMode_CurrMb[19:16] <= rem_Intra4x4PredMode; + 5 :Intra4x4PredMode_CurrMb[23:20] <= rem_Intra4x4PredMode; + 6 :Intra4x4PredMode_CurrMb[27:24] <= rem_Intra4x4PredMode; + 7 :Intra4x4PredMode_CurrMb[31:28] <= rem_Intra4x4PredMode; + 8 :Intra4x4PredMode_CurrMb[35:32] <= rem_Intra4x4PredMode; + 9 :Intra4x4PredMode_CurrMb[39:36] <= rem_Intra4x4PredMode; + 10 :Intra4x4PredMode_CurrMb[43:40] <= rem_Intra4x4PredMode; + 11 :Intra4x4PredMode_CurrMb[47:44] <= rem_Intra4x4PredMode; + 12 :Intra4x4PredMode_CurrMb[51:48] <= rem_Intra4x4PredMode; + 13 :Intra4x4PredMode_CurrMb[55:52] <= rem_Intra4x4PredMode; + 14 :Intra4x4PredMode_CurrMb[59:56] <= rem_Intra4x4PredMode; + 15 :Intra4x4PredMode_CurrMb[63:60] <= rem_Intra4x4PredMode; + endcase + //------------------------------ + //Intra4x4PredMode_mbAddrA write + //------------------------------ + always @ (posedge clk) + if (reset_n == 0) + Intra4x4PredMode_mbAddrA <= 0; + else if (mb_num_h != 10) //mb_num_h == 10,no need to store mbAddrA + begin + if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s && prev_intra4x4_pred_mode_flag == 1) + case (luma4x4BlkIdx) + 5: Intra4x4PredMode_mbAddrA[3:0] <= predIntra4x4PredMode; + 7: Intra4x4PredMode_mbAddrA[7:4] <= predIntra4x4PredMode; + 13:Intra4x4PredMode_mbAddrA[11:8] <= predIntra4x4PredMode; + 15:Intra4x4PredMode_mbAddrA[15:12] <= predIntra4x4PredMode; + endcase + else if (mb_pred_state == `rem_intra4x4_pred_mode_s) + case (luma4x4BlkIdx) + 5: Intra4x4PredMode_mbAddrA[3:0] <= rem_Intra4x4PredMode; + 7: Intra4x4PredMode_mbAddrA[7:4] <= rem_Intra4x4PredMode; + 13:Intra4x4PredMode_mbAddrA[11:8] <= rem_Intra4x4PredMode; + 15:Intra4x4PredMode_mbAddrA[15:12] <= rem_Intra4x4PredMode; + endcase + end + //---------------------------------------- + //Intra4x4PredMode_mbAddrB RF read & write + //---------------------------------------- + always @ (reset_n or mb_num_v or mb_num_h or luma4x4BlkIdx or mb_pred_state or prev_intra4x4_pred_mode_flag + or Intra4x4PredMode_CurrMb or predIntra4x4PredMode or rem_Intra4x4PredMode) + if (reset_n == 0) + begin + Intra4x4PredMode_mbAddrB_cs_n <= 1; Intra4x4PredMode_mbAddrB_wr_n <= 1; + Intra4x4PredMode_mbAddrB_rd_addr <= 0; Intra4x4PredMode_mbAddrB_wr_addr <= 0; + Intra4x4PredMode_mbAddrB_din <= 0; + end + else if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s) + begin + Intra4x4PredMode_mbAddrB_cs_n <= 0; //read is always even if in cases as luma4x4BlkIdx = 2,3,6,7... + Intra4x4PredMode_mbAddrB_rd_addr <= mb_num_h; + if (prev_intra4x4_pred_mode_flag == 1 && luma4x4BlkIdx == 15 && mb_num_v != 8)//write is conditional when mb_num_v != 8 + begin + Intra4x4PredMode_mbAddrB_wr_n <= 0; + Intra4x4PredMode_mbAddrB_wr_addr <= mb_num_h; + Intra4x4PredMode_mbAddrB_din <= {Intra4x4PredMode_CurrMb[43:40], + Intra4x4PredMode_CurrMb[47:44],Intra4x4PredMode_CurrMb[59:56],predIntra4x4PredMode}; + end + else + begin + Intra4x4PredMode_mbAddrB_wr_n <= 1; + Intra4x4PredMode_mbAddrB_wr_addr <= 0; + Intra4x4PredMode_mbAddrB_din <= 0; + end + end + else if (mb_pred_state == `rem_intra4x4_pred_mode_s) + begin + Intra4x4PredMode_mbAddrB_cs_n <= 0; //read is always even if in cases as luma4x4BlkIdx = 2,3,6,7... + Intra4x4PredMode_mbAddrB_rd_addr <= mb_num_h; + if (luma4x4BlkIdx == 15 && mb_num_v != 8) //write is conditional when mb_num_v != 8 + begin + Intra4x4PredMode_mbAddrB_wr_n <= 0; + Intra4x4PredMode_mbAddrB_wr_addr <= mb_num_h; + Intra4x4PredMode_mbAddrB_din <= {Intra4x4PredMode_CurrMb[43:40], + Intra4x4PredMode_CurrMb[47:44],Intra4x4PredMode_CurrMb[59:56],rem_Intra4x4PredMode}; + end + else + begin + Intra4x4PredMode_mbAddrB_wr_n <= 1; + Intra4x4PredMode_mbAddrB_wr_addr <= 0; + Intra4x4PredMode_mbAddrB_din <= 0; + end + end + else + begin + Intra4x4PredMode_mbAddrB_cs_n <= 1; Intra4x4PredMode_mbAddrB_wr_n <= 1; + Intra4x4PredMode_mbAddrB_rd_addr <= 0; Intra4x4PredMode_mbAddrB_wr_addr <= 0; + Intra4x4PredMode_mbAddrB_din <= 0; + end + + /* + // synopsys translate_off + integer tracefile; + wire [6:0] mb_num; + assign mb_num = mb_num_v * 11 + mb_num_h; + + initial + begin + tracefile = $fopen("intra_4x4_trace.txt"); + end + always @ (posedge clk) + if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s && prev_intra4x4_pred_mode_flag == 1) + begin + $fdisplay (tracefile," Pic_num = %3d,MB_num = %3d,blkIdx = %3d,Intra4x4PredMode = %3d", + pic_num,mb_num,luma4x4BlkIdx,predIntra4x4PredMode); + if (luma4x4BlkIdx == 15) + $fdisplay (tracefile,"--------------------------------------------------------------------"); + end + else if (mb_pred_state == `rem_intra4x4_pred_mode_s) + begin + $fdisplay (tracefile," Pic_num = %3d,MB_num = %3d,blkIdx = %3d,Intra4x4PredMode = %3d", + pic_num,mb_num,luma4x4BlkIdx,rem_Intra4x4PredMode); + if (luma4x4BlkIdx == 15) + $fdisplay (tracefile,"--------------------------------------------------------------------"); + end + // synopsys translate_on + */ +endmodule \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/Intra_pred_PE.v b/demo_chip_rtl/rtl/nova/trunk/src/Intra_pred_PE.v new file mode 100644 index 0000000..9eeceec --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/Intra_pred_PE.v @@ -0,0 +1,1626 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : Intra_pred_PE.v +// Generated : Sep 19, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Processing Element for Intra prediction,PE0 ~ PE3 +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module Intra_pred_PE (clk,reset_n,mb_type_general,blk4x4_rec_counter,blk4x4_intra_calculate_counter, + Intra4x4_predmode,Intra16x16_predmode,Intra_chroma_predmode, + blkAddrA_availability,blkAddrB_availability,mbAddrA_availability,mbAddrB_availability, + + Intra_mbAddrA_window0,Intra_mbAddrA_window1,Intra_mbAddrA_window2,Intra_mbAddrA_window3, + Intra_mbAddrB_window0,Intra_mbAddrB_window1,Intra_mbAddrB_window2,Intra_mbAddrB_window3, + Intra_mbAddrC_window0,Intra_mbAddrC_window1,Intra_mbAddrC_window2,Intra_mbAddrC_window3, + Intra_mbAddrD_window, + + Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3, + Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7, + Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11, + Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15, + Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3, + Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7, + Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11, + Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15, + + blk4x4_pred_output0, blk4x4_pred_output1, blk4x4_pred_output2, + blk4x4_pred_output4, blk4x4_pred_output5, blk4x4_pred_output6, + blk4x4_pred_output8, blk4x4_pred_output9, blk4x4_pred_output10, + blk4x4_pred_output12,blk4x4_pred_output13,blk4x4_pred_output14, + + seed,b,c, + + PE0_out,PE1_out,PE2_out,PE3_out,PE0_sum_out,PE3_sum_out); + input clk,reset_n; + input [3:0] mb_type_general; + input [4:0] blk4x4_rec_counter; + input [2:0] blk4x4_intra_calculate_counter; + input [3:0] Intra4x4_predmode; + input [1:0] Intra16x16_predmode; + input [1:0] Intra_chroma_predmode; + input blkAddrA_availability; + input blkAddrB_availability; + input mbAddrA_availability; + input mbAddrB_availability; + input [15:0] Intra_mbAddrA_window0,Intra_mbAddrA_window1,Intra_mbAddrA_window2,Intra_mbAddrA_window3; + input [15:0] Intra_mbAddrB_window0,Intra_mbAddrB_window1,Intra_mbAddrB_window2,Intra_mbAddrB_window3; + input [15:0] Intra_mbAddrC_window0,Intra_mbAddrC_window1,Intra_mbAddrC_window2,Intra_mbAddrC_window3; + input [15:0] Intra_mbAddrD_window; + input [15:0] Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3; + input [15:0] Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7; + input [15:0] Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11; + input [15:0] Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15; + input [15:0] Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3; + input [15:0] Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7; + input [15:0] Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11; + input [15:0] Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15; + input [15:0] blk4x4_pred_output0, blk4x4_pred_output1, blk4x4_pred_output2; + input [15:0] blk4x4_pred_output4, blk4x4_pred_output5, blk4x4_pred_output6; + input [15:0] blk4x4_pred_output8, blk4x4_pred_output9, blk4x4_pred_output10; + input [15:0] blk4x4_pred_output12,blk4x4_pred_output13,blk4x4_pred_output14; + input [15:0] seed; + input [11:0] b,c; + + output [7:0] PE0_out; + output [7:0] PE1_out; + output [7:0] PE2_out; + output [7:0] PE3_out; + output [15:0] PE0_sum_out; //for store as 2nd-level seed + output [15:0] PE3_sum_out; //for store as 2nd-level seed + + reg [15:0] PE0_in0,PE0_in1,PE0_in2,PE0_in3; + reg PE0_IsShift; + reg PE0_IsStore; + reg PE0_IsClip; + reg PE0_full_bypass; + reg [4:0] PE0_round_value; + reg [2:0] PE0_shift_len; + + reg [15:0] PE1_in0,PE1_in1,PE1_in2,PE1_in3; + reg PE1_IsShift; + reg PE1_IsStore; + reg PE1_IsClip; + reg PE1_full_bypass; + reg [4:0] PE1_round_value; + reg [2:0] PE1_shift_len; + + reg [15:0] PE2_in0,PE2_in1,PE2_in2,PE2_in3; + reg PE2_IsShift; + reg PE2_IsStore; + reg PE2_IsClip; + reg PE2_full_bypass; + reg [4:0] PE2_round_value; + reg [2:0] PE2_shift_len; + + reg [15:0] PE3_in0,PE3_in1,PE3_in2,PE3_in3; + reg PE3_IsShift; + reg PE3_IsStore; + reg PE3_IsClip; + reg PE3_full_bypass; + reg [4:0] PE3_round_value; + reg [2:0] PE3_shift_len; + + wire [15:0] PE0_out_reg; + wire [15:0] PE1_out_reg; + wire [15:0] PE2_out_reg; + wire [15:0] PE3_out_reg; + + wire [15:0] PE0_sum_out; + wire [15:0] PE1_sum_out; + wire [15:0] PE2_sum_out; + wire [15:0] PE3_sum_out; + + wire [15:0] b_ext,c_ext; + assign b_ext = (b[11] == 1'b1)? {4'b1111,b}:{4'b0000,b}; + assign c_ext = (c[11] == 1'b1)? {4'b1111,c}:{4'b0000,c}; + + PE PE0 ( + .clk(clk), + .reset_n(reset_n), + .in0(PE0_in0), + .in1(PE0_in1), + .in2(PE0_in2), + .in3(PE0_in3), + .IsShift(PE0_IsShift), + .IsStore(PE0_IsStore), + .IsClip(PE0_IsClip), + .full_bypass(PE0_full_bypass), + .round_value(PE0_round_value), + .shift_len(PE0_shift_len), + .PE_out_reg(PE0_out_reg), + .PE_out(PE0_out), + .sum_out(PE0_sum_out) + ); + PE PE1 ( + .clk(clk), + .reset_n(reset_n), + .in0(PE1_in0), + .in1(PE1_in1), + .in2(PE1_in2), + .in3(PE1_in3), + .IsShift(PE1_IsShift), + .IsStore(PE1_IsStore), + .IsClip(PE1_IsClip), + .full_bypass(PE1_full_bypass), + .round_value(PE1_round_value), + .shift_len(PE1_shift_len), + .PE_out_reg(PE1_out_reg), + .PE_out(PE1_out), + .sum_out(PE1_sum_out) + ); + PE PE2 ( + .clk(clk), + .reset_n(reset_n), + .in0(PE2_in0), + .in1(PE2_in1), + .in2(PE2_in2), + .in3(PE2_in3), + .IsShift(PE2_IsShift), + .IsStore(PE2_IsStore), + .IsClip(PE2_IsClip), + .full_bypass(PE2_full_bypass), + .round_value(PE2_round_value), + .shift_len(PE2_shift_len), + .PE_out_reg(PE2_out_reg), + .PE_out(PE2_out), + .sum_out(PE2_sum_out) + ); + PE PE3 ( + .clk(clk), + .reset_n(reset_n), + .in0(PE3_in0), + .in1(PE3_in1), + .in2(PE3_in2), + .in3(PE3_in3), + .IsShift(PE3_IsShift), + .IsStore(PE3_IsStore), + .IsClip(PE3_IsClip), + .full_bypass(PE3_full_bypass), + .round_value(PE3_round_value), + .shift_len(PE3_shift_len), + .PE_out_reg(PE3_out_reg), + .PE_out(PE3_out), + .sum_out(PE3_sum_out) + ); + //---- + //PE0 | + //---- + always @ (mb_type_general or blk4x4_rec_counter or blk4x4_intra_calculate_counter + or Intra4x4_predmode or Intra16x16_predmode or Intra_chroma_predmode + or blkAddrA_availability or blkAddrB_availability or mbAddrA_availability or mbAddrB_availability + or Intra_mbAddrA_window0 or Intra_mbAddrA_window1 or Intra_mbAddrA_window2 + or Intra_mbAddrB_window0 or Intra_mbAddrB_window1 or Intra_mbAddrB_window2 or Intra_mbAddrB_window3 + or Intra_mbAddrD_window + or Intra_mbAddrA_reg0 or Intra_mbAddrA_reg1 or Intra_mbAddrA_reg2 or Intra_mbAddrA_reg3 + or Intra_mbAddrB_reg1 or Intra_mbAddrB_reg2 or Intra_mbAddrB_reg3 + or PE0_out_reg or PE1_out_reg or PE2_out_reg or PE3_out_reg + or blk4x4_pred_output4 or blk4x4_pred_output5 or blk4x4_pred_output8 + or blk4x4_pred_output9 or blk4x4_pred_output10 or blk4x4_pred_output12 + or seed or b_ext or c_ext) + //Intra 4x4 + if (mb_type_general[3:2] == 2'b11 && blk4x4_rec_counter < 16) + case (Intra4x4_predmode) + `Intra4x4_Vertical: + begin + case (blk4x4_intra_calculate_counter) + 4:PE0_in0 <= Intra_mbAddrB_window0; + 3:PE0_in0 <= Intra_mbAddrB_window1; + 2:PE0_in0 <= Intra_mbAddrB_window2; + 1:PE0_in0 <= Intra_mbAddrB_window3; + default:PE0_in0 <= 0; + endcase + PE0_in1 <= 0; PE0_in2 <= 0; PE0_in3 <= 0; + PE0_IsShift <= 0; PE0_IsStore <= 0; PE0_IsClip <= 0; + PE0_full_bypass <= 1; PE0_round_value <= 0; PE0_shift_len <= 0; + end + `Intra4x4_Horizontal: + begin + PE0_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window0:0; + PE0_in1 <= 0; PE0_in2 <= 0; PE0_in3 <= 0; + PE0_IsShift <= 0; PE0_IsStore <= 0; PE0_IsClip <= 0; + PE0_full_bypass <= 1; PE0_round_value <= 0; PE0_shift_len <= 0; + end + `Intra4x4_DC: + case (blk4x4_intra_calculate_counter) + 4: //A ~ D + begin + if (blkAddrB_availability == 1) + begin + PE0_in0 <= Intra_mbAddrB_window0; PE0_in1 <= Intra_mbAddrB_window1; + PE0_in2 <= Intra_mbAddrB_window2; PE0_in3 <= Intra_mbAddrB_window3; + PE0_IsStore <= 1'b1; PE0_full_bypass <= 1'b0; + end + else + begin + PE0_in0 <= 0; PE0_in1 <= 0; PE0_in2 <= 0; PE0_in3 <= 0; + PE0_IsStore <= 1'b0; PE0_full_bypass <= 1'b1; + end + PE0_IsShift <= 0; PE0_IsClip <= 0; + PE0_round_value <= 0; PE0_shift_len <= 0; + end + 3: + begin + case ({blkAddrB_availability,blkAddrA_availability}) + 2'b00: + begin + PE0_in0 <= 128; PE0_in1 <= 0; + PE0_full_bypass <= 1'b1; PE0_round_value <= 0; PE0_shift_len <= 0; + end + 2'b01,2'b10: + begin + PE0_in0 <= (blkAddrB_availability)? PE0_out_reg:0; + PE0_in1 <= (blkAddrA_availability)? PE1_out_reg:0; + PE0_full_bypass <= 1'b0; PE0_round_value <= 2; PE0_shift_len <= 2; + end + 2'b11: + begin + PE0_in0 <= PE0_out_reg; PE0_in1 <= PE1_out_reg; + PE0_full_bypass <= 1'b0; PE0_round_value <= 4; PE0_shift_len <= 3; + end + endcase + PE0_in2 <= 0; PE0_in3 <= 0; + PE0_IsStore <= 0; PE0_IsShift <= 0; PE0_IsClip <= 0; + end + default: + begin + PE0_in0 <= 0; PE0_in1 <= 0; PE0_in2 <= 0; PE0_in3 <= 0; + PE0_IsShift <= 0; PE0_IsStore <= 0; PE0_IsClip <= 0; + PE0_full_bypass <= 1; PE0_round_value <= 0; PE0_shift_len <= 0; + end + endcase + `Intra4x4_Diagonal_Down_Left: + begin + case (blk4x4_intra_calculate_counter) + 4:PE0_in0 <= Intra_mbAddrB_window0; + 3:PE0_in0 <= blk4x4_pred_output4; + 2:PE0_in0 <= blk4x4_pred_output8; + 1:PE0_in0 <= blk4x4_pred_output12; + default:PE0_in0 <= 0; + endcase + PE0_in1 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrB_window2:0; + PE0_in2 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrB_window1:0; + PE0_in3 <= 0; + PE0_IsShift <= (blk4x4_intra_calculate_counter == 4)? 1'b1:1'b0; + PE0_IsStore <= 1'b0; PE0_IsClip <= 1'b0; + PE0_full_bypass <= (blk4x4_intra_calculate_counter == 4)? 1'b0:1'b1; + PE0_round_value <= (blk4x4_intra_calculate_counter == 4)? 5'b00010:5'b0; // +2 + PE0_shift_len <= (blk4x4_intra_calculate_counter == 4)? 3'b010:3'b0; // >>2 + end + `Intra4x4_Diagonal_Down_Right: + begin + case (blk4x4_intra_calculate_counter) + 4:begin PE0_in0 <= Intra_mbAddrB_window0; PE0_in1 <= Intra_mbAddrA_window0; + PE0_in2 <= Intra_mbAddrD_window; end + 3:begin PE0_in0 <= Intra_mbAddrD_window; PE0_in1 <= Intra_mbAddrB_window1; + PE0_in2 <= Intra_mbAddrB_window0; end + 2:begin PE0_in0 <= Intra_mbAddrB_window0; PE0_in1 <= Intra_mbAddrB_window2; + PE0_in2 <= Intra_mbAddrB_window1; end + 1:begin PE0_in0 <= Intra_mbAddrB_window1; PE0_in1 <= Intra_mbAddrB_window3; + PE0_in2 <= Intra_mbAddrB_window2; end + default:begin PE0_in0 <= 0;PE0_in1 <= 0;PE0_in2 <= 0; end + endcase + PE0_in3 <= 0; + PE0_IsShift <= (blk4x4_intra_calculate_counter == 0)? 1'b0:1'b1; + PE0_IsStore <= 1'b0; PE0_IsClip <= 1'b0; PE0_full_bypass <= 1'b0; + PE0_round_value <= (blk4x4_intra_calculate_counter == 0)? 5'b0:5'b00010; // +2 + PE0_shift_len <= (blk4x4_intra_calculate_counter == 0)? 3'b0:3'b010; // >>2 + end + `Intra4x4_Vertical_Right: + begin + case (blk4x4_intra_calculate_counter) + 4:begin PE0_in0 <= Intra_mbAddrB_window0;PE0_in1 <= Intra_mbAddrD_window; end + 3:begin PE0_in0 <= Intra_mbAddrB_window0;PE0_in1 <= Intra_mbAddrB_window1;end + 2:begin PE0_in0 <= Intra_mbAddrB_window2;PE0_in1 <= Intra_mbAddrB_window1;end + 1:begin PE0_in0 <= Intra_mbAddrB_window2;PE0_in1 <= Intra_mbAddrB_window3;end + default:begin PE0_in0 <= 0;PE0_in1 <= 0; end + endcase + PE0_in2 <= 0; PE0_in3 <= 0; + PE0_IsShift <= 1'b0;PE0_IsStore <= 1'b0; PE0_IsClip <= 1'b0; PE0_full_bypass <= 1'b0; + PE0_round_value <= (blk4x4_intra_calculate_counter == 0)? 5'b0:5'b00001; // +1 + PE0_shift_len <= (blk4x4_intra_calculate_counter == 0)? 3'b0:3'b001; // >>1 + end + `Intra4x4_Horizontal_Down: + begin + case (blk4x4_intra_calculate_counter) + 4:begin PE0_in0 <= Intra_mbAddrA_window0;PE0_in1 <= Intra_mbAddrD_window; + PE0_in2 <= 0; + PE0_round_value <= 5'b00001; PE0_shift_len <= 3'b001;end + 3:begin PE0_in0 <= Intra_mbAddrA_window0;PE0_in1 <= Intra_mbAddrB_window0; + PE0_in2 <= Intra_mbAddrD_window; + PE0_round_value <= 5'b00010; PE0_shift_len <= 3'b010;end + 2:begin PE0_in0 <= Intra_mbAddrD_window; PE0_in1 <= Intra_mbAddrB_window1; + PE0_in2 <= Intra_mbAddrB_window0; + PE0_round_value <= 5'b00010; PE0_shift_len <= 3'b010;end + 1:begin PE0_in0 <= Intra_mbAddrB_window0;PE0_in1 <= Intra_mbAddrB_window2; + PE0_in2 <= Intra_mbAddrB_window1; + PE0_round_value <= 5'b00010; PE0_shift_len <= 3'b010;end + default:begin PE0_in0 <= 0;PE0_in1 <= 0;PE0_in2 <= 0; + PE0_round_value <= 0;PE0_shift_len <= 0; end + endcase + PE0_in3 <= 0; + PE0_IsShift <= (blk4x4_intra_calculate_counter == 3 || blk4x4_intra_calculate_counter == 2 + || blk4x4_intra_calculate_counter == 1)? 1'b1:1'b0; + PE0_IsStore <= 1'b0; PE0_IsClip <= 1'b0; PE0_full_bypass <= 1'b0; + end + `Intra4x4_Vertical_Left: + begin + case (blk4x4_intra_calculate_counter) + 4:PE0_in0 <= Intra_mbAddrB_window0; + 3:PE0_in0 <= blk4x4_pred_output8; + 2:PE0_in0 <= blk4x4_pred_output9; + 1:PE0_in0 <= blk4x4_pred_output10; + default:PE0_in0 <= 0; + endcase + PE0_in1 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrB_window1:0; + PE0_in2 <= 0; PE0_in3 <= 0; + PE0_IsShift <= 1'b0; PE0_IsStore <= 1'b0; PE0_IsClip <= 1'b0; + PE0_full_bypass <= (blk4x4_intra_calculate_counter == 4)? 1'b0:1'b1; + PE0_round_value <= (blk4x4_intra_calculate_counter == 4)? 5'b00001:5'b0; // +1 + PE0_shift_len <= (blk4x4_intra_calculate_counter == 4)? 3'b001:3'b0; // >>1 + end + `Intra4x4_Horizontal_Up: + begin + case (blk4x4_intra_calculate_counter) + 4:begin PE0_in0 <= Intra_mbAddrA_window0; PE0_in1 <= Intra_mbAddrA_window1; end + 3:begin PE0_in0 <= Intra_mbAddrA_window0; PE0_in1 <= Intra_mbAddrA_window2; end + 2:begin PE0_in0 <= blk4x4_pred_output4; PE0_in1 <= 0; end + 1:begin PE0_in0 <= blk4x4_pred_output5; PE0_in1 <= 0; end + default:begin PE0_in0 <= 0; PE0_in1 <= 0; end + endcase + PE0_in2 <= (blk4x4_intra_calculate_counter == 3)? Intra_mbAddrA_window1:0; + PE0_in3 <= 0; + PE0_IsShift <= (blk4x4_intra_calculate_counter == 3)? 1'b1:1'b0; + PE0_IsStore <= 1'b0; PE0_IsClip <= 1'b0; + PE0_full_bypass <= (blk4x4_intra_calculate_counter == 4 || + blk4x4_intra_calculate_counter == 3)? 1'b0:1'b1; + PE0_round_value <= (blk4x4_intra_calculate_counter == 4)? 5'd1: + (blk4x4_intra_calculate_counter == 3)? 5'd2:5'd0; + PE0_shift_len <= (blk4x4_intra_calculate_counter == 4)? 3'd1: + (blk4x4_intra_calculate_counter == 3)? 3'd2:3'd0; + end + default: + begin + PE0_in0 <= 0; PE0_in1 <= 0; PE0_in2 <= 0; PE0_in3 <= 0; + PE0_IsShift <= 0; PE0_IsStore <= 0; PE0_IsClip <= 0; + PE0_full_bypass <= 0; PE0_round_value <= 0; PE0_shift_len <= 0; + end + endcase + //Intra16x16 + else if (mb_type_general[3:2] == 2'b10 && blk4x4_rec_counter < 16) + case (Intra16x16_predmode) + `Intra16x16_Vertical: + begin + case (blk4x4_intra_calculate_counter) + 4:PE0_in0 <= Intra_mbAddrB_window0; + 3:PE0_in0 <= Intra_mbAddrB_window1; + 2:PE0_in0 <= Intra_mbAddrB_window2; + 1:PE0_in0 <= Intra_mbAddrB_window3; + default:PE0_in0 <= 0; + endcase + PE0_in1 <= 0; PE0_in2 <= 0; PE0_in3 <= 0; + PE0_IsShift <= 0; PE0_IsStore <= 0; PE0_IsClip <= 0; + PE0_full_bypass <= 1; PE0_round_value <= 0; PE0_shift_len <= 0; + end + `Intra16x16_Horizontal: + begin + PE0_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window0:0; + PE0_in1 <= 0; PE0_in2 <= 0; PE0_in3 <= 0; + PE0_IsShift <= 0; PE0_IsStore <= 0; PE0_IsClip <= 0; + PE0_full_bypass <= 1; PE0_round_value <= 0; PE0_shift_len <= 0; + end + `Intra16x16_DC: + if (blk4x4_rec_counter == 0) + case (blk4x4_intra_calculate_counter) + 4:begin // A2 + B2 + C2 + D2 + PE0_in0 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg0; + PE0_in1 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg1; + PE0_in2 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg2; + PE0_in3 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg3; + PE0_IsShift <= 0; PE0_IsStore <= 1; PE0_IsClip <= 0; + PE0_full_bypass <= 0; PE0_round_value <= 0; PE0_shift_len <= 0; end + 3:begin // PE0 output + B1 + C1 + D1 + PE0_in0 <= PE0_out_reg; + PE0_in1 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg1; + PE0_in2 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg2; + PE0_in3 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg3; + PE0_IsShift <= 0; PE0_IsStore <= 1; PE0_IsClip <= 0; + PE0_full_bypass <= 0; PE0_round_value <= 0; PE0_shift_len <= 0; end + 2:begin // PE0 output + PE1 output + PE2 output + PE3 output + PE0_in0 <= PE0_out_reg; PE0_in1 <= PE1_out_reg; + PE0_in2 <= PE2_out_reg; PE0_in3 <= PE3_out_reg; + PE0_IsShift <= 0; PE0_IsStore <= 1; PE0_IsClip <= 0; + PE0_full_bypass <= 0; PE0_round_value <= 0; PE0_shift_len <= 0; end + 1:begin // final DC output + PE0_in0 <= (!mbAddrA_availability && !mbAddrB_availability)? 16'd128:PE0_out_reg; + PE0_in1 <= PE1_out_reg; PE0_in2 <= 0; PE0_in3 <= 0; + PE0_IsShift <= 0; PE0_IsStore <= 1; PE0_IsClip <= 0; + PE0_full_bypass <= (!mbAddrA_availability && !mbAddrB_availability)? 1'b1 :1'b0; + PE0_round_value <= ( mbAddrA_availability && mbAddrB_availability)? 5'b10000:5'b01000; + PE0_shift_len <= ( mbAddrA_availability && mbAddrB_availability)? 3'b101 :3'b100; + end + default:begin + PE0_in0 <= 0; PE0_in1 <= 0; PE0_in2 <= 0; PE0_in3 <= 0; + PE0_IsShift <= 0; PE0_IsStore <= 0; PE0_IsClip <= 0; + PE0_full_bypass <= 0; PE0_round_value <= 0; PE0_shift_len <= 0; end + endcase + else + begin + PE0_in0 <= 0; PE0_in1 <= 0; PE0_in2 <= 0; PE0_in3 <= 0; + PE0_IsShift <= 0; PE0_IsStore <= 0; PE0_IsClip <= 0; + PE0_full_bypass <= 0; PE0_round_value <= 0; PE0_shift_len <= 0; + end + `Intra16x16_Plane: + begin + if (blk4x4_intra_calculate_counter != 0) + //blk0,2,4,6,8,10,12,14,calc counter == 3'b100:PE0_in0 <= seed; + //other cases :PE0_in0 <= left pixel output + PE0_in0 <= (blk4x4_intra_calculate_counter == 4 && blk4x4_rec_counter[0] == 1'b0)? + seed:PE0_out_reg; + else + PE0_in0 <= 0; + //blk0,2,8,10,calc counter == 3'b100:PE0_in1 <= c_ext + //other cases :PE0_in1 <= b_ext + if (blk4x4_intra_calculate_counter != 0) + PE0_in1 <= (blk4x4_intra_calculate_counter == 4 && !blk4x4_rec_counter[2] && !blk4x4_rec_counter[0])? + c_ext:b_ext; + else + PE0_in1 <= 0; + PE0_in2 <= 0; PE0_in3 <= 0; + PE0_IsShift <= 1'b0; + PE0_IsStore <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0; + PE0_IsClip <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0; + PE0_full_bypass <= 1'b0; + PE0_round_value <= (blk4x4_intra_calculate_counter != 0)? 5'd16:5'd0; + PE0_shift_len <= (blk4x4_intra_calculate_counter != 0)? 3'd5 :3'd0; + end + endcase + //Chroma + else if (mb_type_general[3] == 1'b1 && blk4x4_rec_counter > 15) + case (Intra_chroma_predmode) + `Intra_chroma_DC: + begin + case ({mbAddrA_availability,mbAddrB_availability}) + 2'b00:PE0_in0 <= (blk4x4_intra_calculate_counter == 3)? 15'd128:15'd0; + 2'b01:PE0_in0 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrB_window0: + (blk4x4_intra_calculate_counter == 3)? PE0_out_reg:0; + 2'b10:PE0_in0 <= (blk4x4_intra_calculate_counter == 3)? PE1_out_reg:0; + 2'b11: + if (blk4x4_intra_calculate_counter == 4) + PE0_in0 <= (blk4x4_rec_counter == 18 || blk4x4_rec_counter == 22)? + 0:Intra_mbAddrB_window0; + else if (blk4x4_intra_calculate_counter == 3) + PE0_in0 <= PE0_out_reg; + else + PE0_in0 <= 0; + endcase + case ({mbAddrA_availability,mbAddrB_availability}) + 2'b00:PE0_in1 <= 0; + 2'b01:PE0_in1 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrB_window1:0; + 2'b10:PE0_in1 <= 0; + 2'b11: + if (blk4x4_intra_calculate_counter == 4) + PE0_in1 <= (blk4x4_rec_counter == 18 || blk4x4_rec_counter == 22)? + 0:Intra_mbAddrB_window1; + else if (blk4x4_intra_calculate_counter == 3) + PE0_in1 <= PE1_out_reg; + else + PE0_in1 <= 0; + endcase + case (mbAddrB_availability) + 1'b0:begin PE0_in2 <= 0; PE0_in3 <= 0; end + 1'b1: + begin + if (blk4x4_intra_calculate_counter == 4) + begin + PE0_in2 <= ((blk4x4_rec_counter == 18 || blk4x4_rec_counter == 22) && mbAddrA_availability)? + 0:Intra_mbAddrB_window2; + PE0_in3 <= ((blk4x4_rec_counter == 18 || blk4x4_rec_counter == 22) && mbAddrA_availability)? + 0:Intra_mbAddrB_window3; + end + else + begin PE0_in2 <= 0; PE0_in3 <= 0; end + end + endcase + PE0_IsShift <= 1'b0; + PE0_IsStore <= (mbAddrB_availability && blk4x4_intra_calculate_counter == 4)? 1'b1:1'b0; + PE0_IsClip <= 1'b0; + PE0_full_bypass <= (!mbAddrA_availability && !mbAddrB_availability && + blk4x4_intra_calculate_counter == 3)? 1'b1:1'b0; + case ({mbAddrA_availability,mbAddrB_availability}) + 2'b00 :begin PE0_round_value <= 0; PE0_shift_len <= 0; end + 2'b01,2'b10 :begin PE0_round_value <= (blk4x4_intra_calculate_counter == 3)? 5'd2:5'd0; + PE0_shift_len <= (blk4x4_intra_calculate_counter == 3)? 3'd2:3'd0; end + 2'b11: + begin + if (blk4x4_intra_calculate_counter == 3) + begin + PE0_round_value <= (blk4x4_rec_counter == 16 || blk4x4_rec_counter == 19 || + blk4x4_rec_counter == 20 || blk4x4_rec_counter == 23)? 5'd4:5'd2; + PE0_shift_len <= (blk4x4_rec_counter == 16 || blk4x4_rec_counter == 19 || + blk4x4_rec_counter == 20 || blk4x4_rec_counter == 23)? 3'd3:3'd2; + end + else + begin PE0_round_value <= 0; PE0_shift_len <= 0; end + end + endcase + end + `Intra_chroma_Horizontal: //---horizontal--- + begin + PE0_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window0:0; + PE0_in1 <= 0; PE0_in2 <= 0; PE0_in3 <= 0; + PE0_IsShift <= 0; PE0_IsStore <= 0; PE0_IsClip <= 0; + PE0_full_bypass <= 1; PE0_round_value <= 0; PE0_shift_len <= 0; + end + `Intra_chroma_Vertical: //---vertical--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE0_in0 <= Intra_mbAddrB_window0; + 3:PE0_in0 <= Intra_mbAddrB_window1; + 2:PE0_in0 <= Intra_mbAddrB_window2; + 1:PE0_in0 <= Intra_mbAddrB_window3; + default:PE0_in0 <= 0; + endcase + PE0_in1 <= 0; PE0_in2 <= 0; PE0_in3 <= 0; + PE0_IsShift <= 0; PE0_IsStore <= 0; PE0_IsClip <= 0; + PE0_full_bypass <= 1; PE0_round_value <= 0; PE0_shift_len <= 0; + end + `Intra_chroma_Plane: //---plane--- + begin + if (blk4x4_intra_calculate_counter != 0) + //need seed, blk4x4 = 16 | 18 | 20 | 22 + //do not need seed,blk4x4 = 17 | 19 | 21 | 23 + PE0_in0 <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)? + seed:PE0_out_reg; + else + PE0_in0 <= 0; + if (blk4x4_intra_calculate_counter != 0) + PE0_in1 <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)? c_ext:b_ext; + else + PE0_in1 <= 0; + PE0_in2 <= 0; PE0_in3 <= 0; + PE0_IsShift <= 1'b0; + PE0_IsStore <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0; + PE0_IsClip <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0; + PE0_full_bypass <= 1'b0; + PE0_round_value <= (blk4x4_intra_calculate_counter != 0)? 5'd16:5'd0; + PE0_shift_len <= (blk4x4_intra_calculate_counter != 0)? 3'd5 :3'd0; + end + endcase + else + begin + PE0_in0 <= 0; PE0_in1 <= 0; PE0_in2 <= 0; PE0_in3 <= 0; + PE0_IsShift <= 0; PE0_IsStore <= 0; PE0_IsClip <= 0; + PE0_full_bypass <= 0; PE0_round_value <= 0; PE0_shift_len <= 0; + end + //---- + //PE1 | + //---- + always @ (mb_type_general or blk4x4_rec_counter or blk4x4_intra_calculate_counter + or Intra4x4_predmode or Intra16x16_predmode or Intra_chroma_predmode + or blkAddrA_availability or mbAddrA_availability or mbAddrB_availability + + or Intra_mbAddrA_window0 or Intra_mbAddrA_window1 or Intra_mbAddrA_window2 or Intra_mbAddrA_window3 + or Intra_mbAddrB_window0 or Intra_mbAddrB_window1 or Intra_mbAddrB_window2 or Intra_mbAddrB_window3 + or Intra_mbAddrD_window + + or Intra_mbAddrA_reg4 or Intra_mbAddrA_reg5 or Intra_mbAddrA_reg6 or Intra_mbAddrA_reg7 + or Intra_mbAddrB_reg0 or Intra_mbAddrB_reg4 or Intra_mbAddrB_reg5 or Intra_mbAddrB_reg6 + or Intra_mbAddrB_reg7 or Intra_mbAddrB_reg8 or Intra_mbAddrB_reg12 + + or PE1_out_reg + or blk4x4_pred_output0 or blk4x4_pred_output1 or blk4x4_pred_output2 + or blk4x4_pred_output8 or blk4x4_pred_output9 or blk4x4_pred_output12 + or blk4x4_pred_output13 or blk4x4_pred_output14 + or seed or b_ext or c_ext) + //Intra 4x4 + if (mb_type_general[3:2] == 2'b11 && blk4x4_rec_counter < 16) + case (Intra4x4_predmode) + `Intra4x4_Vertical: //---Vertical--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE1_in0 <= Intra_mbAddrB_window0; + 3:PE1_in0 <= Intra_mbAddrB_window1; + 2:PE1_in0 <= Intra_mbAddrB_window2; + 1:PE1_in0 <= Intra_mbAddrB_window3; + default:PE1_in0 <= 0; + endcase + PE1_in1 <= 0; PE1_in2 <= 0; PE1_in3 <= 0; + PE1_IsShift <= 0; PE1_IsStore <= 0; PE1_IsClip <= 0; + PE1_full_bypass <= 1; PE1_round_value <= 0; PE1_shift_len <= 0; + end + `Intra4x4_Horizontal: //---Horizontal--- + begin + PE1_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window1:0; + PE1_in1 <= 0; PE1_in2 <= 0; PE1_in3 <= 0; + PE1_IsShift <= 0; PE1_IsStore <= 0; PE1_IsClip <= 0; + PE1_full_bypass <= 1; PE1_round_value <= 0; PE1_shift_len <= 0; + end + `Intra4x4_DC: //---DC--- + begin + PE1_in0 <= (blk4x4_intra_calculate_counter == 4 && blkAddrA_availability == 1)? + Intra_mbAddrA_window0:0; + PE1_in1 <= (blk4x4_intra_calculate_counter == 4 && blkAddrA_availability == 1)? + Intra_mbAddrA_window1:0; + PE1_in2 <= (blk4x4_intra_calculate_counter == 4 && blkAddrA_availability == 1)? + Intra_mbAddrA_window2:0; + PE1_in3 <= (blk4x4_intra_calculate_counter == 4 && blkAddrA_availability == 1)? + Intra_mbAddrA_window3:0; + PE1_IsStore <= (blk4x4_intra_calculate_counter == 4 && blkAddrA_availability == 1)? 1'b1:1'b0; + PE1_full_bypass <= 1'b0; PE1_IsShift <= 0; PE1_IsClip <= 0; + PE1_round_value <= 0; PE1_shift_len <= 0; + end + `Intra4x4_Diagonal_Down_Left: //---diagonal down-left--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE1_in0 <= Intra_mbAddrB_window1; + 3:PE1_in0 <= blk4x4_pred_output8; + 2:PE1_in0 <= blk4x4_pred_output12; + 1:PE1_in0 <= blk4x4_pred_output13; + default:PE1_in0 <= 0; + endcase + PE1_in1 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrB_window3:0; + PE1_in2 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrB_window2:0; + PE1_in3 <= 0; + PE1_IsShift <= (blk4x4_intra_calculate_counter == 4)? 1'b1:1'b0; + PE1_IsStore <= 1'b0; PE1_IsClip <= 1'b0; + PE1_full_bypass <= (blk4x4_intra_calculate_counter == 4)? 1'b0:1'b1; + PE1_round_value <= (blk4x4_intra_calculate_counter == 4)? 5'b00010:5'b0; // +2 + PE1_shift_len <= (blk4x4_intra_calculate_counter == 4)? 3'b010 :3'b0; // >>2 + end + `Intra4x4_Diagonal_Down_Right: //---diagonal down-right--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE1_in0 <= Intra_mbAddrD_window; + 3:PE1_in0 <= blk4x4_pred_output0; + 2:PE1_in0 <= blk4x4_pred_output1; + 1:PE1_in0 <= blk4x4_pred_output2; + default:PE1_in0 <= 0; + endcase + PE1_in1 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrA_window1:0; + PE1_in2 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrA_window0:0; + PE1_in3 <= 0; + PE1_IsShift <= (blk4x4_intra_calculate_counter == 0)? 1'b0:1'b1; + PE1_IsStore <= 1'b0; PE1_IsClip <= 1'b0; + PE1_full_bypass <= (blk4x4_intra_calculate_counter == 4)? 1'b0:1'b1; + PE1_round_value <= (blk4x4_intra_calculate_counter == 0)? 5'b0:5'b00010; // +2 + PE1_shift_len <= (blk4x4_intra_calculate_counter == 0)? 3'b0:3'b010; // >>2 + end + `Intra4x4_Vertical_Right: //---vertical right--- + begin + case (blk4x4_intra_calculate_counter) + 4:begin PE1_in0 <= Intra_mbAddrB_window0; PE1_in1 <= Intra_mbAddrA_window0; + PE1_in2 <= Intra_mbAddrD_window; end + 3:begin PE1_in0 <= Intra_mbAddrD_window; PE1_in1 <= Intra_mbAddrB_window1; + PE1_in2 <= Intra_mbAddrB_window0; end + 2:begin PE1_in0 <= Intra_mbAddrB_window0; PE1_in1 <= Intra_mbAddrB_window2; + PE1_in2 <= Intra_mbAddrB_window1; end + 1:begin PE1_in0 <= Intra_mbAddrB_window1; PE1_in1 <= Intra_mbAddrB_window3; + PE1_in2 <= Intra_mbAddrB_window2; end + default:begin PE1_in0 <= 0;PE1_in1 <= 0;PE1_in2 <= 0; end + endcase + PE1_in3 <= 0; + PE1_IsShift <= (blk4x4_intra_calculate_counter == 0)? 1'b0:1'b1; + PE1_IsStore <= 1'b0; PE1_IsClip <= 1'b0; PE1_full_bypass <= 1'b0; + PE1_round_value <= (blk4x4_intra_calculate_counter == 0)? 5'b0:5'b00010; // +2 + PE1_shift_len <= (blk4x4_intra_calculate_counter == 0)? 3'b0:3'b010; // >>2 + end + `Intra4x4_Horizontal_Down: //---horizontal down--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE1_in0 <= Intra_mbAddrA_window0; + 3:PE1_in0 <= Intra_mbAddrD_window; + 2:PE1_in0 <= blk4x4_pred_output0; + 1:PE1_in0 <= blk4x4_pred_output1; + default:PE1_in0 <= 0; + endcase + PE1_in1 <= (blk4x4_intra_calculate_counter == 4 || blk4x4_intra_calculate_counter == 3)? + Intra_mbAddrA_window1:0; + PE1_in2 <= (blk4x4_intra_calculate_counter == 3)? Intra_mbAddrA_window0:0; + PE1_in3 <= 0; + PE1_IsShift <= (blk4x4_intra_calculate_counter == 3)? 1'b1:1'b0; + PE1_IsStore <= 1'b0; PE1_IsClip <= 1'b0; + PE1_full_bypass <= (blk4x4_intra_calculate_counter == 2 || + blk4x4_intra_calculate_counter == 1)? 1'b1:1'b0; + PE1_round_value <= (blk4x4_intra_calculate_counter == 4)? 5'd1: + (blk4x4_intra_calculate_counter == 3)? 5'd2:5'd0; + PE1_shift_len <= (blk4x4_intra_calculate_counter == 4)? 3'd1: + (blk4x4_intra_calculate_counter == 3)? 3'd2:3'd0; + end + `Intra4x4_Vertical_Left: //---vertical left--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE1_in0 <= Intra_mbAddrB_window0; + 3:PE1_in0 <= blk4x4_pred_output12; + 2:PE1_in0 <= blk4x4_pred_output13; + 1:PE1_in0 <= blk4x4_pred_output14; + default:PE1_in0 <= 0; + endcase + PE1_in1 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrB_window2:0; + PE1_in2 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrB_window1:0; + PE1_in3 <= 0; + PE1_IsShift <= (blk4x4_intra_calculate_counter == 4)? 1'b1:1'b0; + PE1_IsStore <= 1'b0; PE1_IsClip <= 1'b0; + PE1_full_bypass <= (blk4x4_intra_calculate_counter == 4)? 1'b0:1'b1; + PE1_round_value <= (blk4x4_intra_calculate_counter == 4)? 5'd2:5'd0; // +2 + PE1_shift_len <= (blk4x4_intra_calculate_counter == 4)? 3'd2:3'd0; // >>2 + end + `Intra4x4_Horizontal_Up: //---horizontal up--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE1_in0 <= Intra_mbAddrA_window1; + 3:PE1_in0 <= Intra_mbAddrA_window1; + 2:PE1_in0 <= blk4x4_pred_output8; + 1:PE1_in0 <= blk4x4_pred_output9; + default:PE1_in0 <= 0; + endcase + PE1_in1 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrA_window2: + (blk4x4_intra_calculate_counter == 3)? Intra_mbAddrA_window3:0; + PE1_in2 <= (blk4x4_intra_calculate_counter == 3)? Intra_mbAddrA_window2:0; + PE1_in3 <= 0; + PE1_IsShift <= (blk4x4_intra_calculate_counter == 3)? 1'b1:1'b0; + PE1_IsStore <= 1'b0; PE1_IsClip <= 1'b0; + PE1_full_bypass <= (blk4x4_intra_calculate_counter == 2 || + blk4x4_intra_calculate_counter == 1)? 1'b1:1'b0; + PE1_round_value <= (blk4x4_intra_calculate_counter == 4)? 5'd1: + (blk4x4_intra_calculate_counter == 3)? 5'd2:5'd0; + PE1_shift_len <= (blk4x4_intra_calculate_counter == 4)? 3'd1: + (blk4x4_intra_calculate_counter == 3)? 3'd2:3'd0; + end + default: + begin + PE1_in0 <= 0; PE1_in1 <= 0; PE1_in2 <= 0; PE1_in3 <= 0; + PE1_IsShift <= 0; PE1_IsStore <= 0; PE1_IsClip <= 0; + PE1_full_bypass <= 0; PE1_round_value <= 0; PE1_shift_len <= 0; + end + endcase + //Intra16x16 + else if (mb_type_general[3:2] == 2'b10 && blk4x4_rec_counter < 16) + case (Intra16x16_predmode) + `Intra16x16_Vertical: //---Vertical--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE1_in0 <= Intra_mbAddrB_window0; + 3:PE1_in0 <= Intra_mbAddrB_window1; + 2:PE1_in0 <= Intra_mbAddrB_window2; + 1:PE1_in0 <= Intra_mbAddrB_window3; + default:PE1_in0 <= 0; + endcase + PE1_in1 <= 0; PE1_in2 <= 0; PE1_in3 <= 0; + PE1_IsShift <= 0; PE1_IsStore <= 0; PE1_IsClip <= 0; + PE1_full_bypass <= 1; PE1_round_value <= 0; PE1_shift_len <= 0; + end + `Intra16x16_Horizontal: //---Horizontal--- + begin + PE1_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window1:0; + PE1_in1 <= 0; PE1_in2 <= 0; PE1_in3 <= 0; + PE1_IsShift <= 0; PE1_IsStore <= 0; PE1_IsClip <= 0; + PE1_full_bypass <= 1; PE1_round_value <= 0; PE1_shift_len <= 0; + end + `Intra16x16_DC: //---DC--- + if (blk4x4_rec_counter == 0) + case (blk4x4_intra_calculate_counter) + 4:begin // E2 + F2 + G2 + H2 + PE1_in0 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg4; + PE1_in1 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg5; + PE1_in2 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg6; + PE1_in3 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg7; + PE1_IsShift <= 0; PE1_IsStore <= 1; PE1_IsClip <= 0; + PE1_full_bypass <= 0; PE1_round_value <= 0; PE1_shift_len <= 0; end + 3:begin // PE1 output + F1 + G1 + H1 + PE1_in0 <= PE1_out_reg; + PE1_in1 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg5; + PE1_in2 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg6; + PE1_in3 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg7; + PE1_IsShift <= 0; PE1_IsStore <= 1; PE1_IsClip <= 0; + PE1_full_bypass <= 0; PE1_round_value <= 0; PE1_shift_len <= 0; end + 2:begin // A1 + E1 + I1 + M1 + PE1_in0 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg0; + PE1_in1 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg4; + PE1_in2 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg8; + PE1_in3 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg12; + PE1_IsShift <= 0; PE1_IsStore <= 1; PE1_IsClip <= 0; + PE1_full_bypass <= 0; PE1_round_value <= 0; PE1_shift_len <= 0; end + default:begin + PE1_in0 <= 0; PE1_in1 <= 0; PE1_in2 <= 0; PE1_in3 <= 0; + PE1_IsShift <= 0; PE1_IsStore <= 0; PE1_IsClip <= 0; + PE1_full_bypass <= 0; PE1_round_value <= 0; PE1_shift_len <= 0; end + endcase + else + begin + PE1_in0 <= 0; PE1_in1 <= 0; PE1_in2 <= 0; PE1_in3 <= 0; + PE1_IsShift <= 0; PE1_IsStore <= 0; PE1_IsClip <= 0; + PE1_full_bypass <= 0; PE1_round_value <= 0; PE1_shift_len <= 0; + end + `Intra16x16_Plane: //---plane--- + begin + if (blk4x4_intra_calculate_counter != 0) + //blk0,2,4,6,8,10,12,14,calc counter == 3'b100:PE1_in0 <= seed; + //other cases :PE1_in0 <= left pixel output + PE1_in0 <= (blk4x4_intra_calculate_counter == 4 && blk4x4_rec_counter[0] == 1'b0)? + seed:PE1_out_reg; + else + PE1_in0 <= 0; + if (blk4x4_intra_calculate_counter != 0) + //blk0,2,8,10,calc counter == 3'b100:PE1_in1 <= c_ext x 2 + //other cases :PE1_in1 <= b_ext + PE1_in1 <= (blk4x4_intra_calculate_counter == 4 && !blk4x4_rec_counter[2] && !blk4x4_rec_counter[0])? + {c_ext[14:0],1'b0}:b_ext; + else + PE1_in1 <= 0; + //blk4,6,12,14,calc counter == 3'b100:PE1_in2 <= c_ext; + //other cases :PE1_in2 <= 0 + PE1_in2 <= (blk4x4_intra_calculate_counter == 4 && blk4x4_rec_counter[2] && !blk4x4_rec_counter[0])? + c_ext:0; + PE1_in3 <= 0; + PE1_IsShift <= 1'b0; + PE1_IsStore <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0; + PE1_IsClip <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0; + PE1_full_bypass <= 1'b0; + PE1_round_value <= (blk4x4_intra_calculate_counter != 0)? 5'd16:5'd0; + PE1_shift_len <= (blk4x4_intra_calculate_counter != 0)? 3'd5 :3'd0; + end + endcase + //Chroma + else if (mb_type_general[3] == 1'b1 && blk4x4_rec_counter > 15) + case (Intra_chroma_predmode) + `Intra_chroma_DC: //---DC--- + if (blk4x4_intra_calculate_counter == 4) + begin + case ({mbAddrA_availability,mbAddrB_availability}) + 2'b00,2'b01: + begin + PE1_in0 <= 0; PE1_in1 <= 0; PE1_in2 <= 0; PE1_in3 <= 0; + end + 2'b10: + begin + PE1_in0 <= Intra_mbAddrA_window0; PE1_in1 <= Intra_mbAddrA_window1; + PE1_in2 <= Intra_mbAddrA_window2; PE1_in3 <= Intra_mbAddrA_window3; + end + 2'b11: + begin + PE1_in0 <= (blk4x4_rec_counter == 17 || blk4x4_rec_counter == 21)? + 0:Intra_mbAddrA_window0; + PE1_in1 <= (blk4x4_rec_counter == 17 || blk4x4_rec_counter == 21)? + 0:Intra_mbAddrA_window1; + PE1_in2 <= (blk4x4_rec_counter == 17 || blk4x4_rec_counter == 21)? + 0:Intra_mbAddrA_window2; + PE1_in3 <= (blk4x4_rec_counter == 17 || blk4x4_rec_counter == 21)? + 0:Intra_mbAddrA_window3; + end + endcase + PE1_IsShift <= 1'b0; PE1_IsClip <= 1'b0; + PE1_IsStore <= (mbAddrA_availability)? 1'b1:1'b0; + PE1_full_bypass <= 1'b0; + PE1_round_value <= 0; PE1_shift_len <= 0; + end + else + begin + PE1_in0 <= 0; PE1_in1 <= 0; PE1_in2 <= 0; PE1_in3 <= 0; + PE1_IsShift <= 0; PE1_IsStore <= 0; PE1_IsClip <= 0; + PE1_full_bypass <= 0; PE1_round_value <= 0; PE1_shift_len <= 0; + end + `Intra_chroma_Horizontal: //---horizontal--- + begin + PE1_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window1:0; + PE1_in1 <= 0; PE1_in2 <= 0; PE1_in3 <= 0; + PE1_IsShift <= 0; PE1_IsStore <= 0; PE1_IsClip <= 0; + PE1_full_bypass <= 1; PE1_round_value <= 0; PE1_shift_len <= 0; + end + `Intra_chroma_Vertical: //---vertical--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE1_in0 <= Intra_mbAddrB_window0; + 3:PE1_in0 <= Intra_mbAddrB_window1; + 2:PE1_in0 <= Intra_mbAddrB_window2; + 1:PE1_in0 <= Intra_mbAddrB_window3; + default:PE1_in0 <= 0; + endcase + PE1_in1 <= 0; PE1_in2 <= 0; PE1_in3 <= 0; + PE1_IsShift <= 0; PE1_IsStore <= 0; PE1_IsClip <= 0; + PE1_full_bypass <= 1; PE1_round_value <= 0; PE1_shift_len <= 0; + end + `Intra_chroma_Plane: //---plane--- + begin + if (blk4x4_intra_calculate_counter != 0) + //need seed, blk4x4 = 16 | 18 | 20 | 22 + //do not need seed,blk4x4 = 17 | 19 | 21 | 23 + PE1_in0 <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)? + seed:PE1_out_reg; + else + PE1_in0 <= 0; + if (blk4x4_intra_calculate_counter != 0) + PE1_in1 <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)? + 0:b_ext; + else + PE1_in1 <= 0; + //0,2,8,10,the 4th cycle,+2c + PE1_in2 <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)? c_ext:0; + PE1_in3 <= 0; + PE1_IsShift <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)? + 1'b1:1'b0; + PE1_IsStore <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0; + PE1_IsClip <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0; + PE1_full_bypass <= 1'b0; + PE1_round_value <= (blk4x4_intra_calculate_counter != 0)? 5'd16:5'd0; + PE1_shift_len <= (blk4x4_intra_calculate_counter != 0)? 3'd5 :3'd0; + end + endcase + else + begin + PE1_in0 <= 0; PE1_in1 <= 0; PE1_in2 <= 0; PE1_in3 <= 0; + PE1_IsShift <= 0; PE1_IsStore <= 0; PE1_IsClip <= 0; + PE1_full_bypass <= 0; PE1_round_value <= 0; PE1_shift_len <= 0; + end + + //---- + //PE2 | + //---- + always @ (mb_type_general or blk4x4_rec_counter or blk4x4_intra_calculate_counter + or Intra4x4_predmode or Intra16x16_predmode or Intra_chroma_predmode + or mbAddrA_availability or mbAddrB_availability + + or Intra_mbAddrA_window0 or Intra_mbAddrA_window1 or Intra_mbAddrA_window2 or Intra_mbAddrA_window3 + or Intra_mbAddrB_window0 or Intra_mbAddrB_window1 or Intra_mbAddrB_window2 or Intra_mbAddrB_window3 + or Intra_mbAddrD_window + or Intra_mbAddrC_window0 or Intra_mbAddrC_window1 + + or Intra_mbAddrA_reg8 or Intra_mbAddrA_reg9 or Intra_mbAddrA_reg10 or Intra_mbAddrA_reg11 + or Intra_mbAddrB_reg9 or Intra_mbAddrB_reg10 or Intra_mbAddrB_reg11 + or blk4x4_pred_output0 or blk4x4_pred_output1 or blk4x4_pred_output2 + or blk4x4_pred_output4 or blk4x4_pred_output5 or blk4x4_pred_output12 + or blk4x4_pred_output13 or blk4x4_pred_output14 + or PE2_out_reg + + or seed or b_ext or c_ext) + //Intra 4x4 + if (mb_type_general[3:2] == 2'b11 && blk4x4_rec_counter < 16) + case (Intra4x4_predmode) + `Intra4x4_Vertical: //---Vertical--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE2_in0 <= Intra_mbAddrB_window0; + 3:PE2_in0 <= Intra_mbAddrB_window1; + 2:PE2_in0 <= Intra_mbAddrB_window2; + 1:PE2_in0 <= Intra_mbAddrB_window3; + default:PE2_in0 <= 0; + endcase + PE2_in1 <= 0; PE2_in2 <= 0; PE2_in3 <= 0; + PE2_IsShift <= 0; PE2_IsStore <= 0; PE2_IsClip <= 0; + PE2_full_bypass <= 1; PE2_round_value <= 0; PE2_shift_len <= 0; + end + `Intra4x4_Horizontal: //---Horizontal--- + begin + PE2_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window2:0; + PE2_in1 <= 0; PE2_in2 <= 0; PE2_in3 <= 0; + PE2_IsShift <= 0; PE2_IsStore <= 0; PE2_IsClip <= 0; + PE2_full_bypass <= 1; PE2_round_value <= 0; PE2_shift_len <= 0; + end + //------------- + //no PE2 for DC + //4'b0010: + //------------- + `Intra4x4_Diagonal_Down_Left: //---diagonal down-left--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE2_in0 <= Intra_mbAddrB_window2; + 3:PE2_in0 <= blk4x4_pred_output12; + 2:PE2_in0 <= blk4x4_pred_output13; + 1:PE2_in0 <= blk4x4_pred_output14; + default:PE2_in0 <= 0; + endcase + PE2_in1 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrC_window0:0; + PE2_in2 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrB_window3:0; + PE2_in3 <= 0; + PE2_IsShift <= (blk4x4_intra_calculate_counter == 4)? 1'b1:1'b0; + PE2_IsStore <= 1'b0; PE2_IsClip <= 1'b0; + PE2_full_bypass <= (blk4x4_intra_calculate_counter == 4)? 1'b0:1'b1; + PE2_round_value <= (blk4x4_intra_calculate_counter == 4)? 5'd2:5'd0; // +2 + PE2_shift_len <= (blk4x4_intra_calculate_counter == 4)? 3'd2:3'd0; // >>2 + end + `Intra4x4_Diagonal_Down_Right: //---diagonal down-right--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE2_in0 <= Intra_mbAddrA_window0; + 3:PE2_in0 <= blk4x4_pred_output4; + 2:PE2_in0 <= blk4x4_pred_output0; + 1:PE2_in0 <= blk4x4_pred_output1; + default:PE2_in0 <= 0; + endcase + PE2_in1 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrA_window2:0; + PE2_in2 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrA_window1:0; + PE2_in3 <= 0; + PE2_IsShift <= (blk4x4_intra_calculate_counter == 0)? 1'b0:1'b1; + PE2_IsStore <= 1'b0; PE2_IsClip <= 1'b0; + PE2_full_bypass <= (blk4x4_intra_calculate_counter == 4)? 1'b0:1'b1; + PE2_round_value <= (blk4x4_intra_calculate_counter == 0)? 5'd0:5'd2; // +2 + PE2_shift_len <= (blk4x4_intra_calculate_counter == 0)? 3'd0:3'd2; // >>2 + end + `Intra4x4_Vertical_Right: //---vertical right--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE2_in0 <= Intra_mbAddrD_window; + 3:PE2_in0 <= blk4x4_pred_output0; + 2:PE2_in0 <= blk4x4_pred_output1; + 1:PE2_in0 <= blk4x4_pred_output2; + default:PE2_in0 <= 0; + endcase + PE2_in1 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrA_window1:0; + PE2_in2 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrA_window0:0; + PE2_in3 <= 0; + PE2_IsShift <= (blk4x4_intra_calculate_counter == 0)? 1'b0:1'b1; + PE2_IsStore <= 1'b0; PE2_IsClip <= 1'b0; + PE2_full_bypass <= (blk4x4_intra_calculate_counter == 4)? 1'b0:1'b1; + PE2_round_value <= (blk4x4_intra_calculate_counter == 0)? 5'd0:5'd2; // +2 + PE2_shift_len <= (blk4x4_intra_calculate_counter == 0)? 3'd0:3'd2; // >>2 + end + `Intra4x4_Horizontal_Down: //---horizontal down--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE2_in0 <= Intra_mbAddrA_window1; + 3:PE2_in0 <= Intra_mbAddrA_window0; + 2:PE2_in0 <= blk4x4_pred_output4; + 1:PE2_in0 <= blk4x4_pred_output5; + default:PE2_in0 <= 0; + endcase + PE2_in1 <= (blk4x4_intra_calculate_counter == 4 || blk4x4_intra_calculate_counter == 3)? + Intra_mbAddrA_window2:0; + PE2_in2 <= (blk4x4_intra_calculate_counter == 3)? Intra_mbAddrA_window1:0; + PE2_in3 <= 0; + PE2_IsShift <= (blk4x4_intra_calculate_counter == 3)? 1'b1:1'b0; + PE2_IsStore <= 1'b0; PE2_IsClip <= 1'b0; + PE2_full_bypass <= (blk4x4_intra_calculate_counter == 2 || + blk4x4_intra_calculate_counter == 1)? 1'b1:1'b0; + PE2_round_value <= (blk4x4_intra_calculate_counter == 4)? 5'd1: + (blk4x4_intra_calculate_counter == 3)? 5'd2:5'd0; + PE2_shift_len <= (blk4x4_intra_calculate_counter == 4)? 3'd1: + (blk4x4_intra_calculate_counter == 3)? 3'd2:3'd0; + end + `Intra4x4_Vertical_Left: //---vertical left--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE2_in0 <= Intra_mbAddrB_window1; + 3:PE2_in0 <= Intra_mbAddrB_window3; + 2:PE2_in0 <= Intra_mbAddrB_window3; + 1:PE2_in0 <= Intra_mbAddrC_window1; + default:PE2_in0 <= 0; + endcase + case (blk4x4_intra_calculate_counter) + 4,3:PE2_in1 <= Intra_mbAddrB_window2; + 2,1:PE2_in1 <= Intra_mbAddrC_window0; + default:PE2_in1 <= 0; + endcase + PE2_in2 <= 0; PE2_in3 <= 0; + PE2_IsShift <= 0; PE2_IsStore <= 0; PE2_IsClip <= 1'b0; PE2_full_bypass <= 1'b0; + PE2_round_value <= (blk4x4_intra_calculate_counter != 0)? 5'd1:5'd0; // +1 + PE2_shift_len <= (blk4x4_intra_calculate_counter != 0)? 3'd1:3'd0; // >>1 + end + `Intra4x4_Horizontal_Up: //---horizontal up--- + begin + case (blk4x4_intra_calculate_counter) + 4,3:PE2_in0 <= Intra_mbAddrA_window2; + 2,1:PE2_in0 <= blk4x4_pred_output12; + default:PE2_in0 <= 0; + endcase + PE2_in1 <= (blk4x4_intra_calculate_counter == 4 || blk4x4_intra_calculate_counter == 3)? + Intra_mbAddrA_window3:0; + PE2_in2 <= (blk4x4_intra_calculate_counter == 3)? Intra_mbAddrA_window3:0; + PE2_in3 <= 0; + PE2_IsShift <= (blk4x4_intra_calculate_counter == 3)? 1'b1:1'b0; + PE2_IsStore <= 1'b0; PE2_IsClip <= 1'b0; + PE2_full_bypass <= (blk4x4_intra_calculate_counter == 2 || + blk4x4_intra_calculate_counter == 1)? 1'b1:1'b0; + PE2_round_value <= (blk4x4_intra_calculate_counter == 4)? 5'd1: + (blk4x4_intra_calculate_counter == 3)? 5'd2:5'd0; + PE2_shift_len <= (blk4x4_intra_calculate_counter == 4)? 3'd1: + (blk4x4_intra_calculate_counter == 3)? 3'd2:3'd0; + end + default: + begin + PE2_in0 <= 0; PE2_in1 <= 0; PE2_in2 <= 0; PE2_in3 <= 0; + PE2_IsShift <= 0; PE2_IsStore <= 0; PE2_IsClip <= 0; + PE2_full_bypass <= 0; PE2_round_value <= 0; PE2_shift_len <= 0; + end + endcase + //Intra16x16 + else if (mb_type_general[3:2] == 2'b10 && blk4x4_rec_counter < 16) + case (Intra16x16_predmode) + `Intra16x16_Vertical: //---Vertical--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE2_in0 <= Intra_mbAddrB_window0; + 3:PE2_in0 <= Intra_mbAddrB_window1; + 2:PE2_in0 <= Intra_mbAddrB_window2; + 1:PE2_in0 <= Intra_mbAddrB_window3; + default:PE2_in0 <= 0; + endcase + PE2_in1 <= 0; PE2_in2 <= 0; PE2_in3 <= 0; + PE2_IsShift <= 0; PE2_IsStore <= 0; PE2_IsClip <= 0; + PE2_full_bypass <= 1; PE2_round_value <= 0; PE2_shift_len <= 0; + end + `Intra16x16_Horizontal: //---Horizontal--- + begin + PE2_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window2:0; + PE2_in1 <= 0; PE2_in2 <= 0; PE2_in3 <= 0; + PE2_IsShift <= 0; PE2_IsStore <= 0; PE2_IsClip <= 0; + PE2_full_bypass <= 1; PE2_round_value <= 0; PE2_shift_len <= 0; + end + `Intra16x16_DC: //---DC--- + if (blk4x4_rec_counter == 0) + case (blk4x4_intra_calculate_counter) + 4:begin // I2 + J2 + K2 + L2 + PE2_in0 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg8; + PE2_in1 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg9; + PE2_in2 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg10; + PE2_in3 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg11; + PE2_IsShift <= 0; PE2_IsStore <= 1; PE2_IsClip <= 0; + PE2_full_bypass <= 0; PE2_round_value <= 0; PE2_shift_len <= 0; end + 3:begin // PE2 output + J1 + K1 + L1 + PE2_in0 <= PE2_out_reg; + PE2_in1 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg9; + PE2_in2 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg10; + PE2_in3 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg11; + PE2_IsShift <= 0; PE2_IsStore <= 1; PE2_IsClip <= 0; + PE2_full_bypass <= 0; PE2_round_value <= 0; PE2_shift_len <= 0; end + default:begin + PE2_in0 <= 0; PE2_in1 <= 0; PE2_in2 <= 0; PE2_in3 <= 0; + PE2_IsShift <= 0; PE2_IsStore <= 0; PE2_IsClip <= 0; + PE2_full_bypass <= 0; PE2_round_value <= 0; PE2_shift_len <= 0; end + endcase + else + begin + PE2_in0 <= 0; PE2_in1 <= 0; PE2_in2 <= 0; PE2_in3 <= 0; + PE2_IsShift <= 0; PE2_IsStore <= 0; PE2_IsClip <= 0; + PE2_full_bypass <= 0; PE2_round_value <= 0; PE2_shift_len <= 0; + end + `Intra16x16_Plane: //---plane--- + begin + if (blk4x4_intra_calculate_counter != 0) + //blk0,2,4,6,8,10,12,14,calc counter == 3'b100:PE2_in0 <= seed; + //other cases :PE2_in0 <= left pixel output + PE2_in0 <= (blk4x4_intra_calculate_counter == 4 && blk4x4_rec_counter[0] == 1'b0)? + seed:PE2_out_reg; + else + PE2_in0 <= 0; + if (blk4x4_intra_calculate_counter != 0) + //blk0,2,8,10,calc counter == 3'b100:PE2_in1 <= c_ext x 2 + //other cases :PE2_in1 <= b_ext + PE2_in1 <= (blk4x4_intra_calculate_counter == 4 && !blk4x4_rec_counter[2] && !blk4x4_rec_counter[0])? + {c_ext[14:0],1'b0}:b_ext; + else + PE2_in1 <= 0; + //blk0,2, 8,10,calc counter == 3'b100:PE2_in2 <= c_ext; + //blk4,6,12,14,calc counter == 3'b100:PE2_in2 <= c_ext x 2; + //other cases :PE2_in2 <= 0 + if (blk4x4_intra_calculate_counter == 3'b100 && !blk4x4_rec_counter[0]) + PE2_in2 <= (blk4x4_rec_counter[2])? {c_ext[14:0],1'b0}:c_ext; + else + PE2_in2 <= 0; + PE2_in3 <= 0; + PE2_IsShift <= 1'b0; + PE2_IsStore <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0; + PE2_IsClip <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0; + PE2_full_bypass <= 1'b0; + PE2_round_value <= (blk4x4_intra_calculate_counter != 0)? 5'd16:5'd0; + PE2_shift_len <= (blk4x4_intra_calculate_counter != 0)? 3'd5 :3'd0; + end + endcase + //Chroma + else if (mb_type_general[3] == 1'b1 && blk4x4_rec_counter > 15) + case (Intra_chroma_predmode) + //-------------------- + //no PE2 for Chroma DC + //2'b00: + //-------------------- + `Intra_chroma_Horizontal: //---horizontal--- + begin + PE2_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window2:0; + PE2_in1 <= 0; PE2_in2 <= 0; PE2_in3 <= 0; + PE2_IsShift <= 0; PE2_IsStore <= 0; PE2_IsClip <= 0; + PE2_full_bypass <= 1; PE2_round_value <= 0; PE2_shift_len <= 0; + end + `Intra_chroma_Vertical: //---vertical--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE2_in0 <= Intra_mbAddrB_window0; + 3:PE2_in0 <= Intra_mbAddrB_window1; + 2:PE2_in0 <= Intra_mbAddrB_window2; + 1:PE2_in0 <= Intra_mbAddrB_window3; + default:PE2_in0 <= 0; + endcase + PE2_in1 <= 0; PE2_in2 <= 0; PE2_in3 <= 0; + PE2_IsShift <= 0; PE2_IsStore <= 0; PE2_IsClip <= 0; + PE2_full_bypass <= 1; PE2_round_value <= 0; PE2_shift_len <= 0; + end + `Intra_chroma_Plane: //---plane--- + begin + if (blk4x4_intra_calculate_counter != 0) + //need seed, blk4x4 = 16 | 18 | 20 | 22 + //do not need seed,blk4x4 = 17 | 19 | 21 | 23 + PE2_in0 <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)? + seed:PE2_out_reg; + else + PE2_in0 <= 0; + if (blk4x4_intra_calculate_counter != 0) + PE2_in1 <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)? + c_ext:b_ext; + else + PE2_in1 <= 0; + PE2_in2 <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)? + c_ext:0; + PE2_in3 <= 0; + PE2_IsShift <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)? + 1'b1:1'b0; + PE2_IsStore <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0; + PE2_IsClip <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0; + PE2_full_bypass <= 1'b0; + PE2_round_value <= (blk4x4_intra_calculate_counter != 0)? 5'd16:5'd0; + PE2_shift_len <= (blk4x4_intra_calculate_counter != 0)? 3'd5 :3'd0; + end + default: + begin + PE2_in0 <= 0; PE2_in1 <= 0; PE2_in2 <= 0; PE2_in3 <= 0; + PE2_IsShift <= 0; PE2_IsStore <= 0; PE2_IsClip <= 0; + PE2_full_bypass <= 0; PE2_round_value <= 0; PE2_shift_len <= 0; + end + endcase + else + begin + PE2_in0 <= 0; PE2_in1 <= 0; PE2_in2 <= 0; PE2_in3 <= 0; + PE2_IsShift <= 0; PE2_IsStore <= 0; PE2_IsClip <= 0; + PE2_full_bypass <= 0; PE2_round_value <= 0; PE2_shift_len <= 0; + end + + //---- + //PE3 | + //---- + always @ (mb_type_general or blk4x4_rec_counter or blk4x4_intra_calculate_counter + or Intra4x4_predmode or Intra16x16_predmode or Intra_chroma_predmode + or mbAddrA_availability or mbAddrB_availability + or Intra_mbAddrA_window0 or Intra_mbAddrA_window1 or Intra_mbAddrA_window2 or Intra_mbAddrA_window3 + or Intra_mbAddrB_window0 or Intra_mbAddrB_window1 or Intra_mbAddrB_window2 or Intra_mbAddrB_window3 + or Intra_mbAddrC_window0 or Intra_mbAddrC_window1 or Intra_mbAddrC_window2 or Intra_mbAddrC_window3 + + or Intra_mbAddrA_reg12 or Intra_mbAddrA_reg13 or Intra_mbAddrA_reg14 or Intra_mbAddrA_reg15 + or Intra_mbAddrB_reg13 or Intra_mbAddrB_reg14 or Intra_mbAddrB_reg15 + or blk4x4_pred_output0 or blk4x4_pred_output4 or blk4x4_pred_output5 + or blk4x4_pred_output6 or blk4x4_pred_output8 or blk4x4_pred_output9 + or PE3_out_reg + + or seed or b_ext or c_ext) + //Intra 4x4 + if (mb_type_general[3:2] == 2'b11 && blk4x4_rec_counter < 16) + case (Intra4x4_predmode) + `Intra4x4_Vertical: //---Vertical--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE3_in0 <= Intra_mbAddrB_window0; + 3:PE3_in0 <= Intra_mbAddrB_window1; + 2:PE3_in0 <= Intra_mbAddrB_window2; + 1:PE3_in0 <= Intra_mbAddrB_window3; + default:PE3_in0 <= 0; + endcase + PE3_in1 <= 0; PE3_in2 <= 0; PE3_in3 <= 0; + PE3_IsShift <= 0; PE3_IsStore <= 0; PE3_IsClip <= 0; + PE3_full_bypass <= 1; PE3_round_value <= 0; PE3_shift_len <= 0; + end + `Intra4x4_Horizontal: //---Horizontal--- + begin + PE3_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window3:0; + PE3_in1 <= 0; PE3_in2 <= 0; PE3_in3 <= 0; + PE3_IsShift <= 0; PE3_IsStore <= 0; PE3_IsClip <= 0; + PE3_full_bypass <= 1; PE3_round_value <= 0; PE3_shift_len <= 0; + end + //------------- + //no PE2 for DC + //4'b0010: + //------------- + `Intra4x4_Diagonal_Down_Left: //---diagonal down-left--- + begin + case (blk4x4_intra_calculate_counter) + 4:begin PE3_in0 <= Intra_mbAddrB_window3; PE3_in1 <= Intra_mbAddrC_window1; + PE3_in2 <= Intra_mbAddrC_window0; end + 3:begin PE3_in0 <= Intra_mbAddrC_window0; PE3_in1 <= Intra_mbAddrC_window2; + PE3_in2 <= Intra_mbAddrC_window1; end + 2:begin PE3_in0 <= Intra_mbAddrC_window1; PE3_in1 <= Intra_mbAddrC_window3; + PE3_in2 <= Intra_mbAddrC_window2; end + 1:begin PE3_in0 <= Intra_mbAddrC_window2; PE3_in1 <= Intra_mbAddrC_window3; + PE3_in2 <= Intra_mbAddrC_window3; end + default:begin PE3_in0 <= 0;PE3_in1 <= 0;PE3_in2 <= 0; end + endcase + PE3_in3 <= 0; + PE3_IsShift <= (blk4x4_intra_calculate_counter == 0)? 1'b0:1'b1; + PE3_IsStore <= 1'b0; PE3_IsClip <= 1'b0; PE3_full_bypass <= 1'b0; + PE3_round_value <= (blk4x4_intra_calculate_counter == 0)? 5'd0:5'd2; // +2 + PE3_shift_len <= (blk4x4_intra_calculate_counter == 0)? 3'd0:3'd2; // >>2 + end + `Intra4x4_Diagonal_Down_Right: //---diagonal down-right--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE3_in0 <= Intra_mbAddrA_window1; + 3:PE3_in0 <= blk4x4_pred_output8; + 2:PE3_in0 <= blk4x4_pred_output4; + 1:PE3_in0 <= blk4x4_pred_output0; + default:PE3_in0 <= 0; + endcase + PE3_in1 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrA_window3:0; + PE3_in2 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrA_window2:0; + PE3_in3 <= 0; + PE3_IsShift <= (blk4x4_intra_calculate_counter == 0)? 1'b0:1'b1; + PE3_IsStore <= 1'b0; PE3_IsClip <= 1'b0; + PE3_full_bypass <= (blk4x4_intra_calculate_counter == 4)? 1'b0:1'b1; + PE3_round_value <= (blk4x4_intra_calculate_counter == 0)? 5'd0:5'd2; // +2 + PE3_shift_len <= (blk4x4_intra_calculate_counter == 0)? 3'd0:3'd2; // >>2 + end + `Intra4x4_Vertical_Right: //---vertical right--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE3_in0 <= Intra_mbAddrA_window0; + 3:PE3_in0 <= blk4x4_pred_output4; + 2:PE3_in0 <= blk4x4_pred_output5; + 1:PE3_in0 <= blk4x4_pred_output6; + default:PE3_in0 <= 0; + endcase + PE3_in1 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrA_window2:0; + PE3_in2 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrA_window1:0; + PE3_in3 <= 0; + PE3_IsShift <= (blk4x4_intra_calculate_counter == 0)? 1'b0:1'b1; + PE3_IsStore <= 1'b0; PE3_IsClip <= 1'b0; + PE3_full_bypass <= (blk4x4_intra_calculate_counter == 4)? 1'b0:1'b1; + PE3_round_value <= (blk4x4_intra_calculate_counter == 0)? 5'd0:5'd2; // +2 + PE3_shift_len <= (blk4x4_intra_calculate_counter == 0)? 3'd0:3'd2; // >>2 + end + `Intra4x4_Horizontal_Down: //---horizontal down--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE3_in0 <= Intra_mbAddrA_window2; + 3:PE3_in0 <= Intra_mbAddrA_window1; + 2:PE3_in0 <= blk4x4_pred_output8; + 1:PE3_in0 <= blk4x4_pred_output9; + default:PE3_in0 <= 0; + endcase + PE3_in1 <= (blk4x4_intra_calculate_counter == 4 || blk4x4_intra_calculate_counter == 3)? + Intra_mbAddrA_window3:0; + PE3_in2 <= (blk4x4_intra_calculate_counter == 3)? Intra_mbAddrA_window2:0; + PE3_in3 <= 0; + PE3_IsShift <= (blk4x4_intra_calculate_counter == 3)? 1'b1:1'b0; + PE3_IsStore <= 1'b0; PE3_IsClip <= 1'b0; + PE3_full_bypass <= (blk4x4_intra_calculate_counter == 2 || + blk4x4_intra_calculate_counter == 1)? 1'b1:1'b0; + PE3_round_value <= (blk4x4_intra_calculate_counter == 4)? 5'd1: + (blk4x4_intra_calculate_counter == 3)? 5'd2:5'd0; + PE3_shift_len <= (blk4x4_intra_calculate_counter == 4)? 3'd1: + (blk4x4_intra_calculate_counter == 3)? 3'd2:3'd0; + end + `Intra4x4_Vertical_Left: //---vertical left--- + begin + case (blk4x4_intra_calculate_counter) + 4:begin PE3_in0 <= Intra_mbAddrB_window1; PE3_in1 <= Intra_mbAddrB_window3; + PE3_in2 <= Intra_mbAddrB_window2; end + 3:begin PE3_in0 <= Intra_mbAddrB_window2; PE3_in1 <= Intra_mbAddrC_window0; + PE3_in2 <= Intra_mbAddrB_window3; end + 2:begin PE3_in0 <= Intra_mbAddrB_window3; PE3_in1 <= Intra_mbAddrC_window1; + PE3_in2 <= Intra_mbAddrC_window0; end + 1:begin PE3_in0 <= Intra_mbAddrC_window0; PE3_in1 <= Intra_mbAddrC_window2; + PE3_in2 <= Intra_mbAddrC_window1; end + default:begin PE3_in0 <= 0;PE3_in1 <= 0;PE3_in2 <= 0; end + endcase + PE3_in3 <= 0; + PE3_IsShift <= (blk4x4_intra_calculate_counter == 0)? 1'b0:1'b1; + PE3_IsStore <= 1'b0; PE3_IsClip <= 1'b0; PE3_full_bypass <= 1'b0; + PE3_round_value <= (blk4x4_intra_calculate_counter == 0)? 5'd0:5'd2; // +2 + PE3_shift_len <= (blk4x4_intra_calculate_counter == 0)? 3'd0:3'd2; // >>2 + end + `Intra4x4_Horizontal_Up: //---horizontal up--- + begin + PE3_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window3:0; + PE3_in1 <= 0; PE3_in2 <= 0; PE3_in3 <= 0; + PE3_IsShift <= 0; PE3_IsStore <= 0; PE3_IsClip <= 0; + PE3_full_bypass <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0; + PE3_round_value <= 0; PE3_shift_len <= 0; + end + default: + begin + PE3_in0 <= 0; PE3_in1 <= 0; PE3_in2 <= 0; PE3_in3 <= 0; + PE3_IsShift <= 0; PE3_IsStore <= 0; PE3_IsClip <= 0; + PE3_full_bypass <= 0; PE3_round_value <= 0; PE3_shift_len <= 0; + end + endcase + //Intra16x16 + else if (mb_type_general[3:2] == 2'b10 && blk4x4_rec_counter < 16) + case (Intra16x16_predmode) + `Intra16x16_Vertical: //---Vertical--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE3_in0 <= Intra_mbAddrB_window0; + 3:PE3_in0 <= Intra_mbAddrB_window1; + 2:PE3_in0 <= Intra_mbAddrB_window2; + 1:PE3_in0 <= Intra_mbAddrB_window3; + default:PE3_in0 <= 0; + endcase + PE3_in1 <= 0; PE3_in2 <= 0; PE3_in3 <= 0; + PE3_IsShift <= 0; PE3_IsStore <= 0; PE3_IsClip <= 0; + PE3_full_bypass <= 1; PE3_round_value <= 0; PE3_shift_len <= 0; + end + `Intra16x16_Horizontal: //---Horizontal--- + begin + PE3_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window3:0; + PE3_in1 <= 0; PE3_in2 <= 0; PE3_in3 <= 0; + PE3_IsShift <= 0; PE3_IsStore <= 0; PE3_IsClip <= 0; + PE3_full_bypass <= 1; PE3_round_value <= 0; PE3_shift_len <= 0; + end + `Intra16x16_DC: //---DC--- + if (blk4x4_rec_counter == 0) + case (blk4x4_intra_calculate_counter) + 4:begin // M2 + N2 + O2 + P2 + PE3_in0 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg12; + PE3_in1 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg13; + PE3_in2 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg14; + PE3_in3 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg15; + PE3_IsShift <= 0; PE3_IsStore <= 1; PE3_IsClip <= 0; + PE3_full_bypass <= 0; PE3_round_value <= 0; PE3_shift_len <= 0; end + 3:begin // PE3 output + N1 + O1 + P1 + PE3_in0 <= PE3_out_reg; + PE3_in1 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg13; + PE3_in2 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg14; + PE3_in3 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg15; + PE3_IsShift <= 0; PE3_IsStore <= 1; PE3_IsClip <= 0; + PE3_full_bypass <= 0; PE3_round_value <= 0; PE3_shift_len <= 0; end + default:begin + PE3_in0 <= 0; PE3_in1 <= 0; PE3_in2 <= 0; PE3_in3 <= 0; + PE3_IsShift <= 0; PE3_IsStore <= 0; PE3_IsClip <= 0; + PE3_full_bypass <= 0; PE3_round_value <= 0; PE3_shift_len <= 0; end + endcase + else + begin + PE3_in0 <= 0; PE3_in1 <= 0; PE3_in2 <= 0; PE3_in3 <= 0; + PE3_IsShift <= 0; PE3_IsStore <= 0; PE3_IsClip <= 0; + PE3_full_bypass <= 0; PE3_round_value <= 0; PE3_shift_len <= 0; + end + `Intra16x16_Plane: //---plane--- + begin + if (blk4x4_intra_calculate_counter != 0) + //blk0,2,4,6,8,10,12,14,calc counter == 3'b100:PE3_in0 <= seed; + //other cases :PE3_in0 <= left pixel output + PE3_in0 <= (blk4x4_intra_calculate_counter == 4 && blk4x4_rec_counter[0] == 1'b0)? + seed:PE3_out_reg; + else + PE3_in0 <= 0; + if (blk4x4_intra_calculate_counter != 0) + //blk0,2,8,10,calc counter == 3'b100:PE3_in1 <= c_ext x 4 + //other cases :PE3_in1 <= b_ext + PE3_in1 <= (blk4x4_intra_calculate_counter == 4 && !blk4x4_rec_counter[2] && !blk4x4_rec_counter[0])? + {c_ext[13:0],2'b0}:b_ext; + else + PE3_in1 <= 0; + //blk4,6,12,14,calc counter == 3'b100:PE3_in2 <= c_ext x 2; + //other cases :PE3_in2 <= 0 + PE3_in2 <= (blk4x4_intra_calculate_counter == 3'b100 && blk4x4_rec_counter[2] && !blk4x4_rec_counter[0])? + {c_ext[14:0],1'b0}:0; + //blk4,6,12,14,calc counter == 3'b100:PE3_in3 <= c_ext; + //other cases :PE3_in3 <= 0 + PE3_in3 <= (blk4x4_intra_calculate_counter == 3'b100 && blk4x4_rec_counter[2] && !blk4x4_rec_counter[0])? + c_ext:0; + PE3_IsShift <= 1'b0; + PE3_IsStore <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0; + PE3_IsClip <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0; + PE3_full_bypass <= 1'b0; + PE3_round_value <= (blk4x4_intra_calculate_counter != 0)? 5'd16:5'd0; + PE3_shift_len <= (blk4x4_intra_calculate_counter != 0)? 3'd5 :3'd0; + end + endcase + //Chroma + else if (mb_type_general[3] == 1'b1 && blk4x4_rec_counter > 15) + case (Intra_chroma_predmode) + //-------------------- + //no PE2 for Chroma DC + //2'b00: + //-------------------- + `Intra_chroma_Horizontal: //---horizontal--- + begin + PE3_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window3:0; + PE3_in1 <= 0; PE3_in2 <= 0; PE3_in3 <= 0; + PE3_IsShift <= 0; PE3_IsStore <= 0; PE3_IsClip <= 0; + PE3_full_bypass <= 1; PE3_round_value <= 0; PE3_shift_len <= 0; + end + `Intra_chroma_Vertical: //---vertical--- + begin + case (blk4x4_intra_calculate_counter) + 4:PE3_in0 <= Intra_mbAddrB_window0; + 3:PE3_in0 <= Intra_mbAddrB_window1; + 2:PE3_in0 <= Intra_mbAddrB_window2; + 1:PE3_in0 <= Intra_mbAddrB_window3; + default:PE3_in0 <= 0; + endcase + PE3_in1 <= 0; PE3_in2 <= 0; PE3_in3 <= 0; + PE3_IsShift <= 0; PE3_IsStore <= 0; PE3_IsClip <= 0; + PE3_full_bypass <= 1; PE3_round_value <= 0; PE3_shift_len <= 0; + end + `Intra_chroma_Plane: //---plane--- + begin + if (blk4x4_intra_calculate_counter != 0) + //need seed, blk4x4 = 16 | 18 | 20 | 22 + //do not need seed,blk4x4 = 17 | 19 | 21 | 23 + PE3_in0 <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)? + seed:PE3_out_reg; + else + PE3_in0 <= 0; + if (blk4x4_intra_calculate_counter != 0) + PE3_in1 <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)? + {c_ext[14:0],1'b0}:b_ext; + else + PE3_in1 <= 0; + PE3_in2 <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)? + c_ext:0; + PE3_in3 <= 0; + PE3_IsShift <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)? + 1'b1:1'b0; + PE3_IsStore <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0; + PE3_IsClip <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0; + PE3_full_bypass <= 1'b0; + PE3_round_value <= (blk4x4_intra_calculate_counter != 0)? 5'd16:5'd0; + PE3_shift_len <= (blk4x4_intra_calculate_counter != 0)? 3'd5 :3'd0; + end + default: + begin + PE3_in0 <= 0; PE3_in1 <= 0; PE3_in2 <= 0; PE3_in3 <= 0; + PE3_IsShift <= 0; PE3_IsStore <= 0; PE3_IsClip <= 0; + PE3_full_bypass <= 0; PE3_round_value <= 0; PE3_shift_len <= 0; + end + endcase + else + begin + PE3_in0 <= 0; PE3_in1 <= 0; PE3_in2 <= 0; PE3_in3 <= 0; + PE3_IsShift <= 0; PE3_IsStore <= 0; PE3_IsClip <= 0; + PE3_full_bypass <= 0; PE3_round_value <= 0; PE3_shift_len <= 0; + end +endmodule + +module PE (clk,reset_n,in0,in1,in2,in3,IsShift,IsStore,IsClip,full_bypass,round_value,shift_len, + PE_out_reg,PE_out,sum_out); + input clk,reset_n; + input [15:0] in0,in1,in2,in3; + input IsShift; + input IsStore; + input IsClip; + input full_bypass; + input [4:0] round_value; + input [2:0] shift_len; + + + output [15:0] PE_out_reg; + output [7:0] PE_out; + output [15:0] sum_out; + reg [15:0] PE_out_reg; + + wire [15:0] sum1; + wire [15:0] sum2; + wire [16:0] round_tmp; + wire [15:0] round_out; + wire [7:0] clip_out; + + assign sum1 = (full_bypass)? 0:(in0 + in1); + assign sum2 = (full_bypass)? 0:((IsShift)? {in2[14:0],1'b0}:(in2 + in3)); + assign sum_out = (full_bypass)? 0:(sum1 + sum2); + + always @ (posedge clk) + if (reset_n == 1'b0) + PE_out_reg <= 0; + else if (IsStore) + PE_out_reg <= sum_out; + + assign round_tmp = sum_out + round_value; + assign round_out = round_tmp >> shift_len; + assign clip_out = (IsClip)? ((round_out[15] == 1'b1)? 8'd0:((round_out[15:8] == 0)? round_out[7:0]:8'd255)) + :round_out[7:0]; + assign PE_out = (full_bypass)? in0[7:0]:clip_out; +endmodule \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/Intra_pred_pipeline.v b/demo_chip_rtl/rtl/nova/trunk/src/Intra_pred_pipeline.v new file mode 100644 index 0000000..de56b24 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/Intra_pred_pipeline.v @@ -0,0 +1,743 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : Intra_pred_pipeline.v +// Generated : Aug 4, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Intra16x16,Intra4x4 prediction pipeline +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module Intra_pred_pipeline (clk,reset_n,mb_type_general,blk4x4_rec_counter, + trigger_blk4x4_intra_pred,mb_num_v,mb_num_h,blk4x4_sum_counter,NextMB_IsSkip, + Intra16x16_predmode,Intra4x4_predmode_CurrMb,Intra_chroma_predmode, + + Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3, + Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7, + Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11, + Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15, + + Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3, + Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7, + Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11, + Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15, + Intra_mbAddrD_window, + + Intra4x4_predmode,blk4x4_intra_preload_counter,blk4x4_intra_precompute_counter, + blk4x4_intra_calculate_counter,end_of_one_blk4x4_intra, + blkAddrA_availability,blkAddrB_availability,mbAddrA_availability,mbAddrB_availability,mbAddrC_availability, + main_seed,plane_b_reg,plane_c_reg, + Intra_mbAddrB_RAM_rd,Intra_mbAddrB_RAM_rd_addr + ); + input clk,reset_n; + input [3:0] mb_type_general; + input [4:0] blk4x4_rec_counter; + input trigger_blk4x4_intra_pred; + input [3:0] mb_num_v,mb_num_h; + input [2:0] blk4x4_sum_counter; + input NextMB_IsSkip; + input [1:0] Intra16x16_predmode; + input [63:0] Intra4x4_predmode_CurrMb; + input [1:0] Intra_chroma_predmode; + + input [7:0] Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3; + input [7:0] Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7; + input [7:0] Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11; + input [7:0] Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15; + + input [7:0] Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3; + input [7:0] Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7; + input [7:0] Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11; + input [7:0] Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15; + input [7:0] Intra_mbAddrD_window; + + output [3:0] Intra4x4_predmode; + output [2:0] blk4x4_intra_preload_counter; + output [3:0] blk4x4_intra_precompute_counter; + output [2:0] blk4x4_intra_calculate_counter; + output end_of_one_blk4x4_intra; + output blkAddrA_availability,blkAddrB_availability; + output mbAddrA_availability,mbAddrB_availability,mbAddrC_availability; + output [15:0] main_seed; + output [11:0] plane_b_reg,plane_c_reg; + output Intra_mbAddrB_RAM_rd; + output [6:0] Intra_mbAddrB_RAM_rd_addr; + + reg [3:0] Intra4x4_predmode; + reg [2:0] blk4x4_intra_preload_counter; + reg [3:0] blk4x4_intra_precompute_counter; + reg [2:0] blk4x4_intra_calculate_counter; + + reg [11:0] plane_b_reg,plane_c_reg; + wire Intra_mbAddrB_RAM_rd; + wire [6:0] Intra_mbAddrB_RAM_rd_addr; + wire end_of_one_blk4x4_intra; + wire blkAddrA_availability,blkAddrB_availability; + wire mbAddrA_availability,mbAddrB_availability; + + //---------------------------------------------------------------------------------------- + //Intra4x4 prediction mode for current 4x4 block + //---------------------------------------------------------------------------------------- + always @ (Intra4x4_predmode_CurrMb or blk4x4_rec_counter or mb_type_general) + if (mb_type_general == `MB_Intra4x4) + case (blk4x4_rec_counter) + 0 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[3:0]; + 1 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[7:4]; + 2 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[11:8]; + 3 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[15:12]; + 4 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[19:16]; + 5 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[23:20]; + 6 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[27:24]; + 7 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[31:28]; + 8 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[35:32]; + 9 :Intra4x4_predmode <= Intra4x4_predmode_CurrMb[39:36]; + 10:Intra4x4_predmode <= Intra4x4_predmode_CurrMb[43:40]; + 11:Intra4x4_predmode <= Intra4x4_predmode_CurrMb[47:44]; + 12:Intra4x4_predmode <= Intra4x4_predmode_CurrMb[51:48]; + 13:Intra4x4_predmode <= Intra4x4_predmode_CurrMb[55:52]; + 14:Intra4x4_predmode <= Intra4x4_predmode_CurrMb[59:56]; + 15:Intra4x4_predmode <= Intra4x4_predmode_CurrMb[63:60]; + default:Intra4x4_predmode <= 4'b1111; + endcase + else + Intra4x4_predmode <= 4'b1111; + + //availability for intra4x4 predmode = Intra4x4_DC only + assign blkAddrA_availability = (mb_type_general == `MB_Intra4x4 && Intra4x4_predmode == `Intra4x4_DC && + blk4x4_rec_counter < 16 && ((blk4x4_rec_counter == 0 || blk4x4_rec_counter == 2 || blk4x4_rec_counter == 8 || + blk4x4_rec_counter == 10) && mb_num_h == 0))? 1'b0:1'b1; + + assign blkAddrB_availability = (mb_type_general == `MB_Intra4x4 && Intra4x4_predmode == `Intra4x4_DC && + blk4x4_rec_counter < 16 && ((blk4x4_rec_counter == 0 || blk4x4_rec_counter == 1 || blk4x4_rec_counter == 4 || + blk4x4_rec_counter == 5) && mb_num_v == 0))? 1'b0:1'b1; + + //availability for whole intra predicted MB (both intra16x16 & intra4x4) + //assign mbAddrA_availability = (mb_type_general[3] && mb_num_h != 0)? 1'b1:1'b0; + //assign mbAddrB_availability = (mb_type_general[3] && mb_num_v != 0)? 1'b1:1'b0; + assign mbAddrA_availability = (mb_type_general[3] && mb_num_h != 0)? 1'b1:1'b0; + assign mbAddrB_availability = (mb_type_general[3] && mb_num_v != 0)? 1'b1:1'b0; + assign mbAddrC_availability = (mb_type_general[3] && mb_num_v != 0 && mb_num_h != 10)? 1'b1:1'b0; + + //---------------------------------------------------------------------------------------- + //Intra prediction step control counter + //---------------------------------------------------------------------------------------- + //1.Preload upper pels counter + always @ (posedge clk) + if (reset_n == 1'b0) + blk4x4_intra_preload_counter <= 0; + else if (trigger_blk4x4_intra_pred) + begin + //Chroma + if (mb_type_general[3] == 1'b1 && (blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20)) + case (Intra_chroma_predmode) + `Intra_chroma_DC :blk4x4_intra_preload_counter <= (mbAddrB_availability)? 3'b011:3'b000; + `Intra_chroma_Horizontal:blk4x4_intra_preload_counter <= 3'b000; + `Intra_chroma_Vertical :blk4x4_intra_preload_counter <= 3'b011; + `Intra_chroma_Plane :blk4x4_intra_preload_counter <= 3'b011; + endcase + //Luma + // Intra16x16 + else if (mb_type_general[3:2] == 2'b10 && blk4x4_rec_counter == 0) + case (Intra16x16_predmode) + `Intra16x16_Vertical :blk4x4_intra_preload_counter <= 3'b101; + `Intra16x16_Horizontal:blk4x4_intra_preload_counter <= 3'b000; + `Intra16x16_DC :blk4x4_intra_preload_counter <= (mbAddrB_availability)? 3'b101:3'b000; + `Intra16x16_Plane :blk4x4_intra_preload_counter <= 3'b101; + endcase + // Intra4x4 + else if (mb_type_general[3:2] == 2'b11 && (blk4x4_rec_counter == 0 || blk4x4_rec_counter == 1 + || blk4x4_rec_counter == 4 || blk4x4_rec_counter == 5)) + case (Intra4x4_predmode) + `Intra4x4_Vertical :blk4x4_intra_preload_counter <= 3'b010; + `Intra4x4_Horizontal :blk4x4_intra_preload_counter <= 3'b000; + `Intra4x4_DC :blk4x4_intra_preload_counter <= (mbAddrB_availability)? 3'b010:3'b000; + `Intra4x4_Diagonal_Down_Left :blk4x4_intra_preload_counter <= 3'b011; //need mbAddrC + `Intra4x4_Diagonal_Down_Right:blk4x4_intra_preload_counter <= (blk4x4_rec_counter == 0)? 3'b010:3'b011;//need mbAddrD + `Intra4x4_Vertical_Right :blk4x4_intra_preload_counter <= (blk4x4_rec_counter == 0)? 3'b010:3'b011;//need mbAddrD + `Intra4x4_Horizontal_Down :blk4x4_intra_preload_counter <= (blk4x4_rec_counter == 0)? 3'b010:3'b011;//need mbAddrD + `Intra4x4_Vertical_Left :blk4x4_intra_preload_counter <= 3'b011; //need mbAddrC + `Intra4x4_Horizontal_Up :blk4x4_intra_preload_counter <= 3'b000; + endcase + end + else if (blk4x4_intra_preload_counter != 0) + blk4x4_intra_preload_counter <= blk4x4_intra_preload_counter - 1; + + //2.Precomputation for plane mode counter + always @ (posedge clk) + if (reset_n == 1'b0) + blk4x4_intra_precompute_counter <= 0; + //Intra16x16 plane mode: 10 cycle + 1 cycle (seed) + else if (mb_type_general[2] == 1'b0 && blk4x4_rec_counter == 0 && Intra16x16_predmode == `Intra16x16_Plane && blk4x4_intra_preload_counter == 3'b001) + blk4x4_intra_precompute_counter <= 4'b1011; + //Chroma8x8 plane mode: 6 cycle + 1 cycle (seed) + else if ((blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20) && Intra_chroma_predmode == `Intra_chroma_Plane && blk4x4_intra_preload_counter == 3'b001) + blk4x4_intra_precompute_counter <= 4'b0111; + else if (blk4x4_intra_precompute_counter != 0) + blk4x4_intra_precompute_counter <= blk4x4_intra_precompute_counter - 1; + + //3.Intra prediction calculation counter + always @ (posedge clk) + if (reset_n == 1'b0) + blk4x4_intra_calculate_counter <= 0; + //Intra16x16 Luma + else if (mb_type_general[3:2] == 2'b10 && blk4x4_rec_counter < 16) + begin + if (blk4x4_rec_counter == 0) + case (Intra16x16_predmode) + `Intra16x16_Vertical: + if (blk4x4_intra_preload_counter == 3'b001) + blk4x4_intra_calculate_counter <= 3'b100; + else if (blk4x4_intra_calculate_counter != 0) + blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1; + `Intra16x16_Horizontal: + if (trigger_blk4x4_intra_pred) + blk4x4_intra_calculate_counter <= 3'b100; + else if (blk4x4_intra_calculate_counter != 0) + blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1; + `Intra16x16_DC: + if (mbAddrB_availability && blk4x4_intra_preload_counter == 3'b001) + blk4x4_intra_calculate_counter <= 3'b100; + else if (!mbAddrB_availability && trigger_blk4x4_intra_pred) + blk4x4_intra_calculate_counter <= 3'b100; + else if (blk4x4_intra_calculate_counter != 0) + blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1; + `Intra16x16_Plane: + if (blk4x4_intra_precompute_counter == 4'b0001) + blk4x4_intra_calculate_counter <= 3'b100; + else if (blk4x4_intra_calculate_counter != 0) + blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1; + endcase + else + begin + if (trigger_blk4x4_intra_pred) + blk4x4_intra_calculate_counter <= 3'b100; + else if (blk4x4_intra_calculate_counter != 0) + blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1; + end + end + //Intra4x4 Luma + else if (mb_type_general[3:2] == 2'b11 && blk4x4_rec_counter < 16) + begin + if (blk4x4_rec_counter == 0 || blk4x4_rec_counter == 1 || + blk4x4_rec_counter == 4 || blk4x4_rec_counter == 5) + case (Intra4x4_predmode) + `Intra4x4_Horizontal,`Intra4x4_Horizontal_Up://Intra4x4 prediction modes do NOT need preload + if (trigger_blk4x4_intra_pred) + blk4x4_intra_calculate_counter <= 3'b100; + else if (blk4x4_intra_calculate_counter != 0) + blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1; + `Intra4x4_DC: //Intra4x4 prediction modes may or may NOT need preload + if (mbAddrB_availability == 1'b1) //need reload + begin + if (blk4x4_intra_preload_counter == 3'b001) + blk4x4_intra_calculate_counter <= 3'b100; + else if (blk4x4_intra_calculate_counter != 0) + blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1; + end + else //do not need reload + begin + if (trigger_blk4x4_intra_pred) + blk4x4_intra_calculate_counter <= 3'b100; + else if (blk4x4_intra_calculate_counter != 0) + blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1; + end + default: //other Intra4x4 prediction modes that needs preload + if (blk4x4_intra_preload_counter == 3'b001) + blk4x4_intra_calculate_counter <= 3'b100; + else if (blk4x4_intra_calculate_counter != 0) + blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1; + endcase + else if (trigger_blk4x4_intra_pred) + blk4x4_intra_calculate_counter <= 3'b100; + else if (blk4x4_intra_calculate_counter != 0) + blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1; + end + //Chroma + else if (blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20) + case (Intra_chroma_predmode) + `Intra_chroma_DC: + if ((mbAddrB_availability && blk4x4_intra_preload_counter == 3'b001) || (!mbAddrB_availability && trigger_blk4x4_intra_pred)) + blk4x4_intra_calculate_counter <= 3'b100; + else if (blk4x4_intra_calculate_counter != 0) + blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1; + `Intra_chroma_Horizontal: + if (trigger_blk4x4_intra_pred) + blk4x4_intra_calculate_counter <= 3'b100; + else if (blk4x4_intra_calculate_counter != 0) + blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1; + `Intra_chroma_Vertical: + if (blk4x4_intra_preload_counter == 3'b001) + blk4x4_intra_calculate_counter <= 3'b100; + else if (blk4x4_intra_calculate_counter != 0) + blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1; + `Intra_chroma_Plane: //plane + if (blk4x4_intra_precompute_counter == 4'b0001) + blk4x4_intra_calculate_counter <= 3'b100; + else if (blk4x4_intra_calculate_counter != 0) + blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1; + endcase + else + begin + if (trigger_blk4x4_intra_pred) + blk4x4_intra_calculate_counter <= 3'b100; + else if (blk4x4_intra_calculate_counter != 0) + blk4x4_intra_calculate_counter <= blk4x4_intra_calculate_counter - 1; + end + + assign end_of_one_blk4x4_intra = (blk4x4_intra_calculate_counter == 3'd1)? 1'b1:1'b0; + //---------------------------------------------------------------------------------------- + //1.Preload + // For intra4x4,preload_counter == 3'b010 means preload mbAddrC or mbAddrD + // preload_counter == 3'b001 means preload mbAddrB + //---------------------------------------------------------------------------------------- + wire [6:0] Intra_mbAddrB_RAM_addr_bp; + reg [5:0] Intra_mbAddrB_RAM_addr_sp; + reg [1:0] Intra_mbAddrB_RAM_addr_ip; + + wire Intra_mbAddrB_RAM_rd_for_mbAddrD; + assign Intra_mbAddrB_RAM_rd_for_mbAddrD = (blk4x4_sum_counter == 3'b0 && + (blk4x4_rec_counter == 15 || blk4x4_rec_counter == 19 || blk4x4_rec_counter == 23) && + mb_num_h != 10 && mb_num_v != 0 && !NextMB_IsSkip)? 1'b1:1'b0; + + assign Intra_mbAddrB_RAM_rd = ((blk4x4_intra_preload_counter != 0 && blk4x4_intra_preload_counter != 1) || Intra_mbAddrB_RAM_rd_for_mbAddrD)? 1'b1:1'b0; + + // base pointer, [43:0] luma, [65:44] Chroma Cb, [87:66] Chroma Cr + assign Intra_mbAddrB_RAM_addr_bp = (Intra_mbAddrB_RAM_rd)? ((blk4x4_rec_counter > 15)? ((blk4x4_rec_counter > 19)? 7'd66:7'd44):0):0; + + // shift pointer,x2 for chroma,x4 for luma + always @ (Intra_mbAddrB_RAM_rd_for_mbAddrD or Intra_mbAddrB_RAM_rd or mb_num_h or + blk4x4_rec_counter or Intra4x4_predmode or blk4x4_intra_preload_counter) + if (Intra_mbAddrB_RAM_rd_for_mbAddrD) + Intra_mbAddrB_RAM_addr_sp <= (blk4x4_rec_counter < 16)? {mb_num_h,2'b0}:{1'b0,mb_num_h,1'b0}; + else if (Intra_mbAddrB_RAM_rd) + begin + if (blk4x4_rec_counter < 16) + Intra_mbAddrB_RAM_addr_sp <= ((Intra4x4_predmode == `Intra4x4_Diagonal_Down_Left + || Intra4x4_predmode == `Intra4x4_Vertical_Left) && blk4x4_rec_counter == 5 + && blk4x4_intra_preload_counter == 3'b011)? //read for mbAddrC + {(mb_num_h + 1),2'b0}:{mb_num_h,2'b0}; + else + Intra_mbAddrB_RAM_addr_sp <= {1'b0,mb_num_h,1'b0}; + end + else + Intra_mbAddrB_RAM_addr_sp <= 0; + + // pointer for relative address of each 4x4 block inside a MB + always @ (Intra_mbAddrB_RAM_rd or blk4x4_rec_counter or blk4x4_intra_preload_counter or + mb_type_general[3:2] or Intra4x4_predmode or Intra_mbAddrB_RAM_rd_for_mbAddrD) + if (blk4x4_rec_counter < 16 && Intra_mbAddrB_RAM_rd) //luma + begin + if (blk4x4_intra_preload_counter != 0 && blk4x4_intra_preload_counter != 1) + begin + if (mb_type_general[3:2] == 2'b10) //Intra16x16 + case (blk4x4_intra_preload_counter) + 3'b101:Intra_mbAddrB_RAM_addr_ip <= 0; + 3'b100:Intra_mbAddrB_RAM_addr_ip <= 2'b01; + 3'b011:Intra_mbAddrB_RAM_addr_ip <= 2'b10; + 3'b010:Intra_mbAddrB_RAM_addr_ip <= 2'b11; + default:Intra_mbAddrB_RAM_addr_ip <= 0; + endcase + else //Intra4x4 + begin + if (blk4x4_intra_preload_counter == 3'b010) //For mbAddrB + case (blk4x4_rec_counter) + 0:Intra_mbAddrB_RAM_addr_ip <= 0; + 1:Intra_mbAddrB_RAM_addr_ip <= 2'b01; + 4:Intra_mbAddrB_RAM_addr_ip <= 2'b10; + 5:Intra_mbAddrB_RAM_addr_ip <= 2'b11; + default:Intra_mbAddrB_RAM_addr_ip <= 0; + endcase + else if (Intra4x4_predmode == `Intra4x4_Diagonal_Down_Left + || Intra4x4_predmode == `Intra4x4_Vertical_Left) //For mbAddrC + case (blk4x4_rec_counter) + 0:Intra_mbAddrB_RAM_addr_ip <= 2'b01; + 1:Intra_mbAddrB_RAM_addr_ip <= 2'b10; + 4:Intra_mbAddrB_RAM_addr_ip <= 2'b11; + 5:Intra_mbAddrB_RAM_addr_ip <= 2'b00; + default:Intra_mbAddrB_RAM_addr_ip <= 0; + endcase + else //For mbAddrD + case (blk4x4_rec_counter) + 1:Intra_mbAddrB_RAM_addr_ip <= 2'b00; + 4:Intra_mbAddrB_RAM_addr_ip <= 2'b01; + 5:Intra_mbAddrB_RAM_addr_ip <= 2'b10; + default:Intra_mbAddrB_RAM_addr_ip <= 0; + endcase + end + end + else if (Intra_mbAddrB_RAM_rd_for_mbAddrD) + Intra_mbAddrB_RAM_addr_ip <= 2'b11; + else + Intra_mbAddrB_RAM_addr_ip <= 0; + end + else if (Intra_mbAddrB_RAM_rd) //chroma + Intra_mbAddrB_RAM_addr_ip <= (blk4x4_intra_preload_counter != 0 && blk4x4_intra_preload_counter != 1)? {1'b0,~blk4x4_intra_preload_counter[0]}:2'b01; + else + Intra_mbAddrB_RAM_addr_ip <= 0; + + // pointer for each 4x4 block + assign Intra_mbAddrB_RAM_rd_addr = Intra_mbAddrB_RAM_addr_bp + Intra_mbAddrB_RAM_addr_sp + Intra_mbAddrB_RAM_addr_ip; + + //---------------------------------------------------------------------------------------- + //2.Precomputation + // For Intra16x16 Luma Plane + // cycle11: x1 + x3 | + // cycle10: x2 + x5 | + // cycle9 : x4 + x6 | + // cycle8 : x8 + x7 | Vertical,V For Intra Chroma Plane + // cycle7 : calculate c cycle7: x1 + x3 | + // cycle6 : x1 + x3 | cycle6: x2 + x4 | Vertical,V + // cycle5 : x2 + x5 | cycle5: calculate c + // cycle4 : x4 + x6 | cycle4: x1 + x3 | + // cycle3 : x8 + x7 | Horizontal,H cycle3: x2 + x4 | Horizontal,H + // cycle2 : calculate a & b cycle2 : calculate a & b + // cycle1 : seed cycle1 : seed + //---------------------------------------------------------------------------------------- + // 2.1 precomputation for HV: + reg [14:0] plane_HV_prev_in; + reg [7:0] plane_HV_A1,plane_HV_A2,plane_HV_B1,plane_HV_B2; + reg [1:0] plane_HV_shifter1_len,plane_HV_shifter2_len; + reg plane_HV_mux1_sel,plane_HV_mux2_sel; + reg plane_HV_Is7; + wire [14:0] plane_HV_out; + reg [14:0] plane_HV_out_reg; + + plane_HV_precomputation plane_HV_precomputation ( + .prev_in(plane_HV_prev_in), + .A1(plane_HV_A1), + .A2(plane_HV_A2), + .B1(plane_HV_B1), + .B2(plane_HV_B2), + .shifter1_len(plane_HV_shifter1_len), + .shifter2_len(plane_HV_shifter2_len), + .mux1_sel(plane_HV_mux1_sel), + .mux2_sel(plane_HV_mux2_sel), + .Is7(plane_HV_Is7), + .HV_out(plane_HV_out) + ); + always @ (blk4x4_intra_precompute_counter or mb_type_general[2] or blk4x4_rec_counter or plane_HV_out_reg + or Intra_mbAddrA_reg0 or Intra_mbAddrA_reg1 or Intra_mbAddrA_reg2 or Intra_mbAddrA_reg3 + or Intra_mbAddrA_reg4 or Intra_mbAddrA_reg5 or Intra_mbAddrA_reg6 or Intra_mbAddrA_reg7 + or Intra_mbAddrA_reg8 or Intra_mbAddrA_reg9 or Intra_mbAddrA_reg10 or Intra_mbAddrA_reg11 + or Intra_mbAddrA_reg12 or Intra_mbAddrA_reg13 or Intra_mbAddrA_reg14 or Intra_mbAddrA_reg15 + or Intra_mbAddrB_reg0 or Intra_mbAddrB_reg1 or Intra_mbAddrB_reg2 or Intra_mbAddrB_reg3 + or Intra_mbAddrB_reg4 or Intra_mbAddrB_reg5 or Intra_mbAddrB_reg6 or Intra_mbAddrB_reg7 + or Intra_mbAddrB_reg8 or Intra_mbAddrB_reg9 or Intra_mbAddrB_reg10 or Intra_mbAddrB_reg11 + or Intra_mbAddrB_reg12 or Intra_mbAddrB_reg13 or Intra_mbAddrB_reg14 or Intra_mbAddrB_reg15 + or Intra_mbAddrD_window) + //Intra16x16 plane + if (mb_type_general[2] == 1'b0 && blk4x4_rec_counter == 0) + case (blk4x4_intra_precompute_counter) + 11,6: // x1,x3 + begin + plane_HV_prev_in <= 0; plane_HV_Is7 <= 1'b0; + plane_HV_A1 <= (blk4x4_intra_precompute_counter == 11)? Intra_mbAddrA_reg8 :Intra_mbAddrB_reg8; + plane_HV_A2 <= (blk4x4_intra_precompute_counter == 11)? Intra_mbAddrA_reg6 :Intra_mbAddrB_reg6; + plane_HV_B1 <= (blk4x4_intra_precompute_counter == 11)? Intra_mbAddrA_reg10:Intra_mbAddrB_reg10; + plane_HV_B2 <= (blk4x4_intra_precompute_counter == 11)? Intra_mbAddrA_reg4 :Intra_mbAddrB_reg4; + plane_HV_shifter1_len <= 0; plane_HV_shifter2_len <= 2'b01; + plane_HV_mux1_sel <= 1'b0; plane_HV_mux2_sel <= 1'b0; + end + 10,5 : // x2,x5 + begin + plane_HV_prev_in <= plane_HV_out_reg; plane_HV_Is7 <= 1'b0; + plane_HV_A1 <= (blk4x4_intra_precompute_counter == 10)? Intra_mbAddrA_reg9 :Intra_mbAddrB_reg9; + plane_HV_A2 <= (blk4x4_intra_precompute_counter == 10)? Intra_mbAddrA_reg5 :Intra_mbAddrB_reg5; + plane_HV_B1 <= (blk4x4_intra_precompute_counter == 10)? Intra_mbAddrA_reg12:Intra_mbAddrB_reg12; + plane_HV_B2 <= (blk4x4_intra_precompute_counter == 10)? Intra_mbAddrA_reg2 :Intra_mbAddrB_reg2; + plane_HV_shifter1_len <= 2'b01; plane_HV_shifter2_len <= 2'b10; + plane_HV_mux1_sel <= 1'b1; plane_HV_mux2_sel <= 1'b0; + end + 9,4 : // x4,x6 + begin + plane_HV_prev_in <= plane_HV_out_reg; plane_HV_Is7 <= 1'b0; + plane_HV_A1 <= (blk4x4_intra_precompute_counter == 9)? Intra_mbAddrA_reg11:Intra_mbAddrB_reg11; + plane_HV_A2 <= (blk4x4_intra_precompute_counter == 9)? Intra_mbAddrA_reg3 :Intra_mbAddrB_reg3; + plane_HV_B1 <= (blk4x4_intra_precompute_counter == 9)? Intra_mbAddrA_reg13:Intra_mbAddrB_reg13; + plane_HV_B2 <= (blk4x4_intra_precompute_counter == 9)? Intra_mbAddrA_reg1 :Intra_mbAddrB_reg1; + plane_HV_shifter1_len <= 2'b10; plane_HV_shifter2_len <= 2'b10; + plane_HV_mux1_sel <= 1'b1; plane_HV_mux2_sel <= 1'b1; + end + 8,3 : // x8,x7 + begin + plane_HV_prev_in <= plane_HV_out_reg; plane_HV_Is7 <= 1'b1; + plane_HV_A1 <= (blk4x4_intra_precompute_counter == 8)? Intra_mbAddrA_reg15:Intra_mbAddrB_reg15; + plane_HV_A2 <= Intra_mbAddrD_window; + plane_HV_B1 <= (blk4x4_intra_precompute_counter == 8)? Intra_mbAddrA_reg14:Intra_mbAddrB_reg14; + plane_HV_B2 <= (blk4x4_intra_precompute_counter == 8)? Intra_mbAddrA_reg0 :Intra_mbAddrB_reg0; + plane_HV_shifter1_len <= 2'b11; plane_HV_shifter2_len <= 2'b11; + plane_HV_mux1_sel <= 1'b1; plane_HV_mux2_sel <= 1'b0; + end + default: + begin + plane_HV_prev_in <= 0; plane_HV_Is7 <= 0; + plane_HV_A1 <= 0; plane_HV_A2 <= 0; plane_HV_B1 <= 0; plane_HV_B2 <= 0; + plane_HV_shifter1_len <= 0; plane_HV_shifter2_len <= 0; + plane_HV_mux1_sel <= 0; plane_HV_mux2_sel <= 0; + end + endcase + //Chroma Cb/Cr plane + else if (blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20) + case (blk4x4_intra_precompute_counter) + 7,4: //x1,x3 + begin + plane_HV_prev_in <= 0; plane_HV_Is7 <= 1'b0; + plane_HV_A1 <= (blk4x4_intra_precompute_counter == 7)? Intra_mbAddrA_reg4:Intra_mbAddrB_reg4; + plane_HV_A2 <= (blk4x4_intra_precompute_counter == 7)? Intra_mbAddrA_reg2:Intra_mbAddrB_reg2; + plane_HV_B1 <= (blk4x4_intra_precompute_counter == 7)? Intra_mbAddrA_reg6:Intra_mbAddrB_reg6; + plane_HV_B2 <= (blk4x4_intra_precompute_counter == 7)? Intra_mbAddrA_reg0:Intra_mbAddrB_reg0; + plane_HV_shifter1_len <= 0; plane_HV_shifter2_len <= 2'b01; + plane_HV_mux1_sel <= 1'b0; plane_HV_mux2_sel <= 1'b0; + end + 6,3: //x2,x4 + begin + plane_HV_prev_in <= plane_HV_out_reg; plane_HV_Is7 <= 1'b0; + plane_HV_A1 <= (blk4x4_intra_precompute_counter == 6)? Intra_mbAddrA_reg5:Intra_mbAddrB_reg5; + plane_HV_A2 <= (blk4x4_intra_precompute_counter == 6)? Intra_mbAddrA_reg1:Intra_mbAddrB_reg1; + plane_HV_B1 <= (blk4x4_intra_precompute_counter == 6)? Intra_mbAddrA_reg7:Intra_mbAddrB_reg7; + plane_HV_B2 <= (blk4x4_intra_precompute_counter == 6)? Intra_mbAddrD_window :Intra_mbAddrD_window; + plane_HV_shifter1_len <= 2'b01; plane_HV_shifter2_len <= 2'b01; + plane_HV_mux1_sel <= 1'b1; plane_HV_mux2_sel <= 1'b1; + end + default: + begin + plane_HV_prev_in <= 0; plane_HV_Is7 <= 0; + plane_HV_A1 <= 0; plane_HV_A2 <= 0; plane_HV_B1 <= 0; plane_HV_B2 <= 0; + plane_HV_shifter1_len <= 0; plane_HV_shifter2_len <= 0; + plane_HV_mux1_sel <= 0; plane_HV_mux2_sel <= 0; + end + endcase + else + begin + plane_HV_prev_in <= 0; plane_HV_Is7 <= 0; + plane_HV_A1 <= 0; plane_HV_A2 <= 0; plane_HV_B1 <= 0; plane_HV_B2 <= 0; + plane_HV_shifter1_len <= 0; plane_HV_shifter2_len <= 0; + plane_HV_mux1_sel <= 0; plane_HV_mux2_sel <= 0; + end + + wire Is_HV_latch; + assign Is_HV_latch = ((blk4x4_rec_counter == 0 && blk4x4_intra_precompute_counter != 7 && blk4x4_intra_precompute_counter != 2 && + blk4x4_intra_precompute_counter != 1 && blk4x4_intra_precompute_counter != 0) || ( + (blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20) && (blk4x4_intra_precompute_counter != 5 && + blk4x4_intra_precompute_counter != 2 && blk4x4_intra_precompute_counter != 1 && blk4x4_intra_precompute_counter != 0))); + always @ (posedge clk) + if (reset_n == 1'b0) + plane_HV_out_reg <= 0; + else if (Is_HV_latch) + plane_HV_out_reg <= plane_HV_out; + + // 2.2 precomputation for b,c + reg [14:0] plane_bc_in; + reg plane_bc_IsLuma; + wire [11:0] plane_bc; + plane_bc_precomputation plane_bc_precomputation ( + .HV_in(plane_bc_in), + .IsLuma(plane_bc_IsLuma), + .bc_out(plane_bc) + ); + always @ (mb_type_general[3:2] or Intra16x16_predmode or blk4x4_rec_counter or blk4x4_intra_precompute_counter or plane_HV_out_reg) + //Intra16x16 plane + if (mb_type_general[3:2] == 2'b10 && Intra16x16_predmode == `Intra16x16_Plane && blk4x4_rec_counter == 0) + case (blk4x4_intra_precompute_counter) + 7,2 :begin plane_bc_in <= plane_HV_out_reg; plane_bc_IsLuma <= 1'b1; end + default:begin plane_bc_in <= 0; plane_bc_IsLuma <= 1'b0; end + endcase + //Chroma Cb,Cr plane + else if (mb_type_general[3] == 1'b1 && (blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20)) + case (blk4x4_intra_precompute_counter) + 5,2 :begin plane_bc_in <= plane_HV_out_reg; plane_bc_IsLuma <= 1'b0; end + default:begin plane_bc_in <= 0; plane_bc_IsLuma <= 1'b0; end + endcase + else + begin plane_bc_in <= 0; plane_bc_IsLuma <= 1'b0; end + + wire c_latch_ena; + assign c_latch_ena = ((blk4x4_rec_counter == 0 && blk4x4_intra_precompute_counter == 7) || + ((blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20) && blk4x4_intra_precompute_counter == 5)); + always @ (posedge clk) + if (reset_n == 0) + plane_c_reg <= 0; + else if (c_latch_ena) + plane_c_reg <= plane_bc; + // 2.3 precomputation for a,and latch a & b at the same time at cycle 2 + reg [7:0] plane_a_pix_in1,plane_a_pix_in2; + wire [13:0] plane_a; + reg [13:0] plane_a_reg; + + plane_a_precomputation plane_a_precomputation( + .pix_in1(plane_a_pix_in1), + .pix_in2(plane_a_pix_in2), + .a_out(plane_a) + ); + always @ (blk4x4_rec_counter or blk4x4_intra_precompute_counter or Intra_mbAddrA_reg15 + or Intra_mbAddrB_reg15 or Intra_mbAddrA_reg7 or Intra_mbAddrB_reg7) + //Intra16x16 + if (blk4x4_rec_counter == 0 && blk4x4_intra_precompute_counter == 2) + begin + plane_a_pix_in1 <= Intra_mbAddrA_reg15; + plane_a_pix_in2 <= Intra_mbAddrB_reg15; + end + //Chroma + else if((blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20) && blk4x4_intra_precompute_counter == 2) + begin + plane_a_pix_in1 <= Intra_mbAddrA_reg7; + plane_a_pix_in2 <= Intra_mbAddrB_reg7; + end + else + begin + plane_a_pix_in1 <= 0; + plane_a_pix_in2 <= 0; + end + + wire ab_latch_ena; + assign ab_latch_ena = (blk4x4_intra_precompute_counter == 2); + always @ (posedge clk) + if (reset_n == 1'b0) + begin + plane_a_reg <= 0; + plane_b_reg <= 0; + end + else if (ab_latch_ena) + begin + plane_a_reg <= plane_a; + plane_b_reg <= plane_bc; + end + // 2.4 precomputation for main seed @ blk4x4_intra_precompute_counter == 1 + wire [13:0] main_seed_a; + wire [11:0] main_seed_b,main_seed_c; + wire main_seed_IsIntra16x16; + + main_seed_precomputation main_seed_precomputation ( + .a(main_seed_a), + .b(main_seed_b), + .c(main_seed_c), + .IsIntra16x16(main_seed_IsIntra16x16), + .main_seed(main_seed) + ); + assign main_seed_a = (blk4x4_intra_precompute_counter == 1)? plane_a_reg:0; + assign main_seed_b = (blk4x4_intra_precompute_counter == 1)? plane_b_reg:0; + assign main_seed_c = (blk4x4_intra_precompute_counter == 1)? plane_c_reg:0; + assign main_seed_IsIntra16x16 = (blk4x4_intra_precompute_counter == 1)? ((blk4x4_rec_counter == 0)? 1'b1:1'b0):1'b0; + + //---------------------------------------------------------------------------------------- + //3.calculation: by Intra_pred_PE.v + //---------------------------------------------------------------------------------------- + +endmodule + +module plane_a_precomputation (pix_in1,pix_in2,a_out); + input [7:0] pix_in1,pix_in2; + output [13:0] a_out; + + wire [8:0] sum; + assign sum = pix_in1 + pix_in2; + assign a_out = {1'b0,sum,4'b0}; +endmodule + +module plane_bc_precomputation (HV_in,IsLuma,bc_out); + input [14:0] HV_in; + input IsLuma; + output [11:0] bc_out; + + wire [16:0] multiply_4or16; + wire [16:0] product; + wire [5:0] addend; + wire [16:0] sum; + + assign multiply_4or16 = (IsLuma)? {HV_in,2'b0}:{HV_in[12:0],4'b0}; + assign product = multiply_4or16 + {{2{HV_in[14]}},HV_in}; + assign addend = (IsLuma)? 6'b100000:6'b010000; //32 for luma,16 for chroma + assign sum = product + addend; + assign bc_out = (IsLuma)? {sum[16],sum[16:6]}:sum[16:5]; + +endmodule + +module plane_HV_precomputation (prev_in,A1,A2,B1,B2,shifter1_len,shifter2_len,mux1_sel,mux2_sel,Is7,HV_out); + input [14:0] prev_in; + input [7:0] A1,A2,B1,B2; + input [1:0] shifter1_len,shifter2_len; + input mux1_sel,mux2_sel; + input Is7; + output [14:0] HV_out; + + wire [7:0] neg_A2; + wire signed [8:0] A1_minus_A2; + wire signed [11:0] shifter1_out; + wire [11:0] mux1_out; + wire [14:0] adder1_out; + wire [7:0] neg_B2; + wire signed [8:0] B1_minus_B2; + wire signed [11:0] shifter2_out; + wire [9:0] mux2_out; + wire [9:0] neg_mux2_out; + wire [11:0] adder2_out; + //Left part,multiply by 1,2,4,8 + assign neg_A2 = ~A2; + assign A1_minus_A2 = {1'b0,A1} + {1'b1,neg_A2} + 1; + assign shifter1_out = A1_minus_A2 <<< shifter1_len; + assign mux1_out = (mux1_sel == 1'b0)? {{3{A1_minus_A2[8]}},A1_minus_A2}:shifter1_out; + assign adder1_out = prev_in + {{3{mux1_out[11]}},mux1_out}; + //Right part,multiply by 3,5,6,7 + assign neg_B2 = ~B2; + assign B1_minus_B2 = {1'b0,B1} + {1'b1,neg_B2} + 1; + assign shifter2_out = B1_minus_B2 <<< shifter2_len; + assign mux2_out = (mux2_sel == 1'b0)? {B1_minus_B2[8],B1_minus_B2}:{B1_minus_B2,1'b0}; + assign neg_mux2_out = (Is7 == 1'b1)? (~mux2_out + 1):mux2_out; + assign adder2_out = shifter2_out + {{2{neg_mux2_out[9]}},neg_mux2_out}; + assign HV_out = adder1_out + {{3{adder2_out[11]}},adder2_out}; +endmodule + +module main_seed_precomputation (a,b,c,IsIntra16x16,main_seed); + input [13:0] a; + input [11:0] b,c; + input IsIntra16x16; + output [15:0] main_seed; + + wire [14:0] b_x8_or_x4; + wire [14:0] c_x8_or_x4; + wire [11:0] neg_b; + wire [14:0] b_x7_or_x3; + wire [15:0] neg_b_x7_or_x3; + wire [15:0] neg_c_x8_or_x4; + + assign b_x8_or_x4 = (IsIntra16x16)? {b[11:0],3'b0}:{b[11],b[11:0],2'b0}; + assign c_x8_or_x4 = (IsIntra16x16)? {c[11:0],3'b0}:{c[11],c[11:0],2'b0}; + assign neg_b = ~ b; + assign b_x7_or_x3 = b_x8_or_x4 + {{3{neg_b[11]}},neg_b} + 1; + assign neg_b_x7_or_x3 = {~b_x7_or_x3[14],~b_x7_or_x3} + 1; + assign neg_c_x8_or_x4 = {~c_x8_or_x4[14],~c_x8_or_x4} + 1; + assign main_seed = {a[13],a[13],a} + (neg_c_x8_or_x4 + neg_b_x7_or_x3); +endmodule + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demo_chip_rtl/rtl/nova/trunk/src/Intra_pred_reg_ctrl.v b/demo_chip_rtl/rtl/nova/trunk/src/Intra_pred_reg_ctrl.v new file mode 100644 index 0000000..8974ba5 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/Intra_pred_reg_ctrl.v @@ -0,0 +1,839 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : Intra_pred_reg_ctrl.v +// Generated : Sep 25, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Prepare the appropriate registers for PE0 ~ PE3 +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module Intra_pred_reg_ctrl (reset_n,gclk_intra_mbAddrA_luma,gclk_intra_mbAddrA_Cb, + gclk_intra_mbAddrA_Cr,gclk_intra_mbAddrB,gclk_intra_mbAddrC_luma,gclk_intra_mbAddrD,gclk_seed, + mbAddrA_availability,mbAddrC_availability,blk4x4_rec_counter,blk4x4_sum_counter, + blk4x4_intra_preload_counter,blk4x4_intra_precompute_counter,blk4x4_intra_calculate_counter, + mb_type_general,Intra4x4_predmode,Intra16x16_predmode,Intra_chroma_predmode, + + Intra_mbAddrB_RAM_dout,sum_right_column_reg, + blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out, + main_seed,PE0_sum_out,PE3_sum_out, + + Intra_mbAddrA_window0,Intra_mbAddrA_window1,Intra_mbAddrA_window2,Intra_mbAddrA_window3, + Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3, + Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7, + Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11, + Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15, + + Intra_mbAddrB_window0,Intra_mbAddrB_window1,Intra_mbAddrB_window2,Intra_mbAddrB_window3, + Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3, + Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7, + Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11, + Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15, + + Intra_mbAddrC_window0,Intra_mbAddrC_window1,Intra_mbAddrC_window2,Intra_mbAddrC_window3,Intra_mbAddrD_window, + seed); + input reset_n; + input gclk_intra_mbAddrA_luma; + input gclk_intra_mbAddrA_Cb; + input gclk_intra_mbAddrA_Cr; + input gclk_intra_mbAddrB; + input gclk_intra_mbAddrC_luma; + input gclk_intra_mbAddrD; + input gclk_seed; + input mbAddrA_availability; + input mbAddrC_availability; + input [4:0] blk4x4_rec_counter; + input [2:0] blk4x4_sum_counter; + input [2:0] blk4x4_intra_preload_counter; + input [3:0] blk4x4_intra_precompute_counter; + input [2:0] blk4x4_intra_calculate_counter; + input [3:0] mb_type_general; + input [3:0] Intra4x4_predmode; + input [1:0] Intra16x16_predmode; + input [1:0] Intra_chroma_predmode; + input [31:0] Intra_mbAddrB_RAM_dout; + input [23:0] sum_right_column_reg; + input [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out; + input [15:0] main_seed; + input [15:0] PE0_sum_out,PE3_sum_out; + + output [7:0] Intra_mbAddrA_window0,Intra_mbAddrA_window1,Intra_mbAddrA_window2,Intra_mbAddrA_window3; + output [7:0] Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3; + output [7:0] Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7; + output [7:0] Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11; + output [7:0] Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15; + + output [7:0] Intra_mbAddrB_window0,Intra_mbAddrB_window1,Intra_mbAddrB_window2,Intra_mbAddrB_window3; + output [7:0] Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3; + output [7:0] Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7; + output [7:0] Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11; + output [7:0] Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15; + + output [7:0] Intra_mbAddrC_window0,Intra_mbAddrC_window1,Intra_mbAddrC_window2,Intra_mbAddrC_window3; + output [7:0] Intra_mbAddrD_window; + output [15:0] seed; + + reg [7:0] Intra_mbAddrA_luma_reg0, Intra_mbAddrA_luma_reg1, Intra_mbAddrA_luma_reg2, Intra_mbAddrA_luma_reg3; + reg [7:0] Intra_mbAddrA_luma_reg4, Intra_mbAddrA_luma_reg5, Intra_mbAddrA_luma_reg6, Intra_mbAddrA_luma_reg7; + reg [7:0] Intra_mbAddrA_luma_reg8, Intra_mbAddrA_luma_reg9, Intra_mbAddrA_luma_reg10,Intra_mbAddrA_luma_reg11; + reg [7:0] Intra_mbAddrA_luma_reg12,Intra_mbAddrA_luma_reg13,Intra_mbAddrA_luma_reg14,Intra_mbAddrA_luma_reg15; + reg [7:0] Intra_mbAddrA_Cb_reg0,Intra_mbAddrA_Cb_reg1,Intra_mbAddrA_Cb_reg2,Intra_mbAddrA_Cb_reg3; + reg [7:0] Intra_mbAddrA_Cb_reg4,Intra_mbAddrA_Cb_reg5,Intra_mbAddrA_Cb_reg6,Intra_mbAddrA_Cb_reg7; + reg [7:0] Intra_mbAddrA_Cr_reg0,Intra_mbAddrA_Cr_reg1,Intra_mbAddrA_Cr_reg2,Intra_mbAddrA_Cr_reg3; + reg [7:0] Intra_mbAddrA_Cr_reg4,Intra_mbAddrA_Cr_reg5,Intra_mbAddrA_Cr_reg6,Intra_mbAddrA_Cr_reg7; + reg [7:0] Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3; + reg [7:0] Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7; + reg [7:0] Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11; + reg [7:0] Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15; + reg [7:0] Intra_mbAddrA_window0,Intra_mbAddrA_window1,Intra_mbAddrA_window2,Intra_mbAddrA_window3; + + reg [7:0] Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3; + reg [7:0] Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7; + reg [7:0] Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11; + reg [7:0] Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15; + reg [7:0] Intra_mbAddrB_window0,Intra_mbAddrB_window1,Intra_mbAddrB_window2,Intra_mbAddrB_window3; + + reg [7:0] Intra_mbAddrC_reg0,Intra_mbAddrC_reg1,Intra_mbAddrC_reg2,Intra_mbAddrC_reg3; + reg [7:0] Intra_mbAddrC_window0,Intra_mbAddrC_window1,Intra_mbAddrC_window2,Intra_mbAddrC_window3; + + reg [7:0] Intra_mbAddrD_reg0,Intra_mbAddrD_reg1,Intra_mbAddrD_reg2; + reg [7:0] Intra_mbAddrD_reg3,Intra_mbAddrD_reg4; + reg [7:0] Intra_mbAddrD_LeftMB_luma_reg,Intra_mbAddrD_LeftMB_Cb_reg,Intra_mbAddrD_LeftMB_Cr_reg; + reg [7:0] Intra_mbAddrD_window; + + reg [15:0] seed_0,seed_1,seed_2,seed_3; + reg [15:0] seed; + //--------------------------------------------------------------------- + //Intra_mbAddrA_luma_reg0 ~ 15 + //Intra_mbAddrA_Cb_reg0 ~ 7 + //Intra_mbAddrA_Cr_reg0 ~ 7 + //--------------------------------------------------------------------- + always @ (posedge gclk_intra_mbAddrA_luma or negedge reset_n) + if (reset_n == 1'b0) + begin + Intra_mbAddrA_luma_reg0 <= 0; Intra_mbAddrA_luma_reg1 <= 0; Intra_mbAddrA_luma_reg2 <= 0; + Intra_mbAddrA_luma_reg3 <= 0; Intra_mbAddrA_luma_reg4 <= 0; Intra_mbAddrA_luma_reg5 <= 0; + Intra_mbAddrA_luma_reg6 <= 0; Intra_mbAddrA_luma_reg7 <= 0; Intra_mbAddrA_luma_reg8 <= 0; + Intra_mbAddrA_luma_reg9 <= 0; Intra_mbAddrA_luma_reg10 <= 0; Intra_mbAddrA_luma_reg11 <= 0; + Intra_mbAddrA_luma_reg12 <= 0; Intra_mbAddrA_luma_reg13 <= 0; Intra_mbAddrA_luma_reg14 <= 0; + Intra_mbAddrA_luma_reg15 <= 0; + end + else + case (blk4x4_rec_counter) + 0,1,4,5: + begin + Intra_mbAddrA_luma_reg0 <= sum_right_column_reg[7:0]; + Intra_mbAddrA_luma_reg1 <= sum_right_column_reg[15:8]; + Intra_mbAddrA_luma_reg2 <= sum_right_column_reg[23:16]; + Intra_mbAddrA_luma_reg3 <= blk4x4_sum_PE3_out; + end + 2,3,6,7: + begin + Intra_mbAddrA_luma_reg4 <= sum_right_column_reg[7:0]; + Intra_mbAddrA_luma_reg5 <= sum_right_column_reg[15:8]; + Intra_mbAddrA_luma_reg6 <= sum_right_column_reg[23:16]; + Intra_mbAddrA_luma_reg7 <= blk4x4_sum_PE3_out; + end + 8,9,12,13: + begin + Intra_mbAddrA_luma_reg8 <= sum_right_column_reg[7:0]; + Intra_mbAddrA_luma_reg9 <= sum_right_column_reg[15:8]; + Intra_mbAddrA_luma_reg10 <= sum_right_column_reg[23:16]; + Intra_mbAddrA_luma_reg11 <= blk4x4_sum_PE3_out; + end + 10,11,14,15: + begin + Intra_mbAddrA_luma_reg12 <= sum_right_column_reg[7:0]; + Intra_mbAddrA_luma_reg13 <= sum_right_column_reg[15:8]; + Intra_mbAddrA_luma_reg14 <= sum_right_column_reg[23:16]; + Intra_mbAddrA_luma_reg15 <= blk4x4_sum_PE3_out; + end + endcase + + always @ (posedge gclk_intra_mbAddrA_Cb or negedge reset_n) + if (reset_n == 1'b0) + begin + Intra_mbAddrA_Cb_reg0 <= 0; Intra_mbAddrA_Cb_reg1 <= 0; Intra_mbAddrA_Cb_reg2 <= 0; + Intra_mbAddrA_Cb_reg3 <= 0; Intra_mbAddrA_Cb_reg4 <= 0; Intra_mbAddrA_Cb_reg5 <= 0; + Intra_mbAddrA_Cb_reg6 <= 0; Intra_mbAddrA_Cb_reg7 <= 0; + end + else if (blk4x4_rec_counter == 17) + begin + Intra_mbAddrA_Cb_reg0 <= sum_right_column_reg[7:0]; + Intra_mbAddrA_Cb_reg1 <= sum_right_column_reg[15:8]; + Intra_mbAddrA_Cb_reg2 <= sum_right_column_reg[23:16]; + Intra_mbAddrA_Cb_reg3 <= blk4x4_sum_PE3_out; + end + else + begin + Intra_mbAddrA_Cb_reg4 <= sum_right_column_reg[7:0]; + Intra_mbAddrA_Cb_reg5 <= sum_right_column_reg[15:8]; + Intra_mbAddrA_Cb_reg6 <= sum_right_column_reg[23:16]; + Intra_mbAddrA_Cb_reg7 <= blk4x4_sum_PE3_out; + end + + always @ (posedge gclk_intra_mbAddrA_Cr or negedge reset_n) + if (reset_n == 1'b0) + begin + Intra_mbAddrA_Cr_reg0 <= 0; Intra_mbAddrA_Cr_reg1 <= 0; Intra_mbAddrA_Cr_reg2 <= 0; + Intra_mbAddrA_Cr_reg3 <= 0; Intra_mbAddrA_Cr_reg4 <= 0; Intra_mbAddrA_Cr_reg5 <= 0; + Intra_mbAddrA_Cr_reg6 <= 0; Intra_mbAddrA_Cr_reg7 <= 0; + end + else if (blk4x4_rec_counter == 21) + begin + Intra_mbAddrA_Cr_reg0 <= sum_right_column_reg[7:0]; + Intra_mbAddrA_Cr_reg1 <= sum_right_column_reg[15:8]; + Intra_mbAddrA_Cr_reg2 <= sum_right_column_reg[23:16]; + Intra_mbAddrA_Cr_reg3 <= blk4x4_sum_PE3_out; + end + else + begin + Intra_mbAddrA_Cr_reg4 <= sum_right_column_reg[7:0]; + Intra_mbAddrA_Cr_reg5 <= sum_right_column_reg[15:8]; + Intra_mbAddrA_Cr_reg6 <= sum_right_column_reg[23:16]; + Intra_mbAddrA_Cr_reg7 <= blk4x4_sum_PE3_out; + end + //--------------------------------------------------------------------- + //Intra_mbAddrB_reg0 ~ 15 + //--------------------------------------------------------------------- + always @ (posedge gclk_intra_mbAddrB or negedge reset_n) + if (reset_n == 1'b0) + begin + Intra_mbAddrB_reg0 <= 0; Intra_mbAddrB_reg1 <= 0; Intra_mbAddrB_reg2 <= 0; + Intra_mbAddrB_reg3 <= 0; Intra_mbAddrB_reg4 <= 0; Intra_mbAddrB_reg5 <= 0; + Intra_mbAddrB_reg6 <= 0; Intra_mbAddrB_reg7 <= 0; Intra_mbAddrB_reg8 <= 0; + Intra_mbAddrB_reg9 <= 0; Intra_mbAddrB_reg10 <= 0; Intra_mbAddrB_reg11 <= 0; + Intra_mbAddrB_reg12 <= 0; Intra_mbAddrB_reg13 <= 0; Intra_mbAddrB_reg14 <= 0; + Intra_mbAddrB_reg15 <= 0; + end + //Intra4x4 + else if (mb_type_general[3:2] == 2'b11 && blk4x4_rec_counter < 16) + begin + // blk 0,1,4,5,load from RAM + if (blk4x4_intra_preload_counter == 3'b001) + case (blk4x4_rec_counter) + 0: + begin + Intra_mbAddrB_reg0 <= Intra_mbAddrB_RAM_dout[7:0]; + Intra_mbAddrB_reg1 <= Intra_mbAddrB_RAM_dout[15:8]; + Intra_mbAddrB_reg2 <= Intra_mbAddrB_RAM_dout[23:16]; + Intra_mbAddrB_reg3 <= Intra_mbAddrB_RAM_dout[31:24]; + end + 1: + begin + Intra_mbAddrB_reg4 <= Intra_mbAddrB_RAM_dout[7:0]; + Intra_mbAddrB_reg5 <= Intra_mbAddrB_RAM_dout[15:8]; + Intra_mbAddrB_reg6 <= Intra_mbAddrB_RAM_dout[23:16]; + Intra_mbAddrB_reg7 <= Intra_mbAddrB_RAM_dout[31:24]; + end + 4: + begin + Intra_mbAddrB_reg8 <= Intra_mbAddrB_RAM_dout[7:0]; + Intra_mbAddrB_reg9 <= Intra_mbAddrB_RAM_dout[15:8]; + Intra_mbAddrB_reg10 <= Intra_mbAddrB_RAM_dout[23:16]; + Intra_mbAddrB_reg11 <= Intra_mbAddrB_RAM_dout[31:24]; + end + 5: + begin + Intra_mbAddrB_reg12 <= Intra_mbAddrB_RAM_dout[7:0]; + Intra_mbAddrB_reg13 <= Intra_mbAddrB_RAM_dout[15:8]; + Intra_mbAddrB_reg14 <= Intra_mbAddrB_RAM_dout[23:16]; + Intra_mbAddrB_reg15 <= Intra_mbAddrB_RAM_dout[31:24]; + end + endcase + //other blocks,from blk4x4_sum output + else if ((blk4x4_rec_counter != 10 || blk4x4_rec_counter != 11 || blk4x4_rec_counter != 14 || + blk4x4_rec_counter != 15) && blk4x4_sum_counter == 3'd3) + case (blk4x4_rec_counter) + 0,2,8: + begin + Intra_mbAddrB_reg0 <= blk4x4_sum_PE0_out; + Intra_mbAddrB_reg1 <= blk4x4_sum_PE1_out; + Intra_mbAddrB_reg2 <= blk4x4_sum_PE2_out; + Intra_mbAddrB_reg3 <= blk4x4_sum_PE3_out; + end + 1,3,9: + begin + Intra_mbAddrB_reg4 <= blk4x4_sum_PE0_out; + Intra_mbAddrB_reg5 <= blk4x4_sum_PE1_out; + Intra_mbAddrB_reg6 <= blk4x4_sum_PE2_out; + Intra_mbAddrB_reg7 <= blk4x4_sum_PE3_out; + end + 4,6,12: + begin + Intra_mbAddrB_reg8 <= blk4x4_sum_PE0_out; + Intra_mbAddrB_reg9 <= blk4x4_sum_PE1_out; + Intra_mbAddrB_reg10 <= blk4x4_sum_PE2_out; + Intra_mbAddrB_reg11 <= blk4x4_sum_PE3_out; + end + 5,7,13: + begin + Intra_mbAddrB_reg12 <= blk4x4_sum_PE0_out; + Intra_mbAddrB_reg13 <= blk4x4_sum_PE1_out; + Intra_mbAddrB_reg14 <= blk4x4_sum_PE2_out; + Intra_mbAddrB_reg15 <= blk4x4_sum_PE3_out; + end + endcase + end + //Intra16x16 + else if (mb_type_general[3:2] == 2'b10 && blk4x4_rec_counter < 16) + case (blk4x4_intra_preload_counter) + 3'b100: + begin + Intra_mbAddrB_reg0 <= Intra_mbAddrB_RAM_dout[7:0]; + Intra_mbAddrB_reg1 <= Intra_mbAddrB_RAM_dout[15:8]; + Intra_mbAddrB_reg2 <= Intra_mbAddrB_RAM_dout[23:16]; + Intra_mbAddrB_reg3 <= Intra_mbAddrB_RAM_dout[31:24]; + end + 3'b011: + begin + Intra_mbAddrB_reg4 <= Intra_mbAddrB_RAM_dout[7:0]; + Intra_mbAddrB_reg5 <= Intra_mbAddrB_RAM_dout[15:8]; + Intra_mbAddrB_reg6 <= Intra_mbAddrB_RAM_dout[23:16]; + Intra_mbAddrB_reg7 <= Intra_mbAddrB_RAM_dout[31:24]; + end + 3'b010: + begin + Intra_mbAddrB_reg8 <= Intra_mbAddrB_RAM_dout[7:0]; + Intra_mbAddrB_reg9 <= Intra_mbAddrB_RAM_dout[15:8]; + Intra_mbAddrB_reg10 <= Intra_mbAddrB_RAM_dout[23:16]; + Intra_mbAddrB_reg11 <= Intra_mbAddrB_RAM_dout[31:24]; + end + 3'b001: + begin + Intra_mbAddrB_reg12 <= Intra_mbAddrB_RAM_dout[7:0]; + Intra_mbAddrB_reg13 <= Intra_mbAddrB_RAM_dout[15:8]; + Intra_mbAddrB_reg14 <= Intra_mbAddrB_RAM_dout[23:16]; + Intra_mbAddrB_reg15 <= Intra_mbAddrB_RAM_dout[31:24]; + end + endcase + //Chroma + else if (mb_type_general[3] == 1'b1 && blk4x4_rec_counter > 15) + begin + if (blk4x4_intra_preload_counter == 3'b010) + begin + Intra_mbAddrB_reg0 <= Intra_mbAddrB_RAM_dout[7:0]; + Intra_mbAddrB_reg1 <= Intra_mbAddrB_RAM_dout[15:8]; + Intra_mbAddrB_reg2 <= Intra_mbAddrB_RAM_dout[23:16]; + Intra_mbAddrB_reg3 <= Intra_mbAddrB_RAM_dout[31:24]; + end + else if (blk4x4_intra_preload_counter == 3'b001) + begin + Intra_mbAddrB_reg4 <= Intra_mbAddrB_RAM_dout[7:0]; + Intra_mbAddrB_reg5 <= Intra_mbAddrB_RAM_dout[15:8]; + Intra_mbAddrB_reg6 <= Intra_mbAddrB_RAM_dout[23:16]; + Intra_mbAddrB_reg7 <= Intra_mbAddrB_RAM_dout[31:24]; + end + end + //-------------------------------------------------------- + //Intra_mbAddrC_reg0 ~ 3,only useful for Intra4x4 with + // blkIdx = 0/1/4/5 + //-------------------------------------------------------- + + always @ (posedge gclk_intra_mbAddrC_luma or negedge reset_n) + if (reset_n == 1'b0) + begin + Intra_mbAddrC_reg0 <= 0; Intra_mbAddrC_reg1 <= 0; + Intra_mbAddrC_reg2 <= 0; Intra_mbAddrC_reg3 <= 0; + end + else + begin + Intra_mbAddrC_reg0 <= Intra_mbAddrB_RAM_dout[7:0]; + Intra_mbAddrC_reg1 <= Intra_mbAddrB_RAM_dout[15:8]; + Intra_mbAddrC_reg2 <= Intra_mbAddrB_RAM_dout[23:16]; + Intra_mbAddrC_reg3 <= Intra_mbAddrB_RAM_dout[31:24]; + end + //-------------------------------------------------------- + //Intra_mbAddrD_reg0 ~ 5 + //Intra_mbAddrD_LeftMB_reg + //-------------------------------------------------------- + always @ (posedge gclk_intra_mbAddrD or negedge reset_n) + if (reset_n == 1'b0) + Intra_mbAddrD_LeftMB_luma_reg <= 0; + else if (blk4x4_rec_counter == 15) + Intra_mbAddrD_LeftMB_luma_reg <= Intra_mbAddrB_RAM_dout[31:24]; + else if (mb_type_general[3:2] == 2'b11 && blk4x4_sum_counter == 3'd3) //Intra4x4 + case (blk4x4_rec_counter) + 0:Intra_mbAddrD_LeftMB_luma_reg <= Intra_mbAddrA_reg3; + 2:Intra_mbAddrD_LeftMB_luma_reg <= Intra_mbAddrA_reg7; + 8:Intra_mbAddrD_LeftMB_luma_reg <= Intra_mbAddrA_reg11; + endcase + + always @ (posedge gclk_intra_mbAddrD or negedge reset_n) + if (reset_n == 1'b0) + Intra_mbAddrD_LeftMB_Cb_reg <= 0; + else if (blk4x4_rec_counter == 19) + Intra_mbAddrD_LeftMB_Cb_reg <= Intra_mbAddrB_RAM_dout[31:24]; + + always @ (posedge gclk_intra_mbAddrD or negedge reset_n) + if (reset_n == 1'b0) + Intra_mbAddrD_LeftMB_Cr_reg <= 0; + else if (blk4x4_rec_counter == 23) + Intra_mbAddrD_LeftMB_Cr_reg <= Intra_mbAddrB_RAM_dout[31:24]; + + always @ (posedge gclk_intra_mbAddrD or negedge reset_n) + if (reset_n == 1'b0) + begin + Intra_mbAddrD_reg0 <= 0; Intra_mbAddrD_reg1 <= 0; Intra_mbAddrD_reg2 <= 0; + Intra_mbAddrD_reg3 <= 0; Intra_mbAddrD_reg4 <= 0; + end + else if (mb_type_general[3:2] == 2'b11) + begin + //load from Intra_mbAddrB_RAM for blk 1/4/5 + if (blk4x4_intra_preload_counter == 3'b010) + case (blk4x4_rec_counter) + 1:Intra_mbAddrD_reg1 <= Intra_mbAddrB_RAM_dout[31:24]; + 4:Intra_mbAddrD_reg4 <= Intra_mbAddrB_RAM_dout[31:24]; + 5:Intra_mbAddrD_reg0 <= Intra_mbAddrB_RAM_dout[31:24]; + endcase + //update Intra_mbAddrD_reg by pixels already decoded from left up blk4x4 + //After sum of blk0/1/4, update Intra_mbAddrD_reg0/1/2 for blkIdx 3 /6 /7 + //After sum of blk2/3/6, update Intra_mbAddrD_reg3/4/5 for blkIdx 9 /12/13 + //After sum of blk8/9/12,update Intra_mbAddrD_reg0/1/2 for blkIdx 11/14/15 + else + case (blk4x4_rec_counter) + 0,6 :Intra_mbAddrD_reg0 <= blk4x4_sum_PE3_out; + 1,8 :Intra_mbAddrD_reg1 <= blk4x4_sum_PE3_out; + 2,12:Intra_mbAddrD_reg2 <= blk4x4_sum_PE3_out; + 3 :Intra_mbAddrD_reg3 <= blk4x4_sum_PE3_out; + 4,9 :Intra_mbAddrD_reg4 <= blk4x4_sum_PE3_out; + endcase + end + //--------------------------- + //sliding window output + //--------------------------- + //Intra_mbAddrA_reg0 ~ 15 + always @ (mb_type_general[3:2] or blk4x4_rec_counter or blk4x4_intra_calculate_counter or + blk4x4_intra_precompute_counter or Intra16x16_predmode or Intra_chroma_predmode + or mbAddrA_availability + + or Intra_mbAddrA_luma_reg0 or Intra_mbAddrA_luma_reg1 or Intra_mbAddrA_luma_reg2 + or Intra_mbAddrA_luma_reg3 or Intra_mbAddrA_luma_reg4 or Intra_mbAddrA_luma_reg5 + or Intra_mbAddrA_luma_reg6 or Intra_mbAddrA_luma_reg7 or Intra_mbAddrA_luma_reg8 + or Intra_mbAddrA_luma_reg9 or Intra_mbAddrA_luma_reg10 or Intra_mbAddrA_luma_reg11 + or Intra_mbAddrA_luma_reg12 or Intra_mbAddrA_luma_reg13 or Intra_mbAddrA_luma_reg14 + or Intra_mbAddrA_luma_reg15 + + or Intra_mbAddrA_Cb_reg0 or Intra_mbAddrA_Cb_reg1 or Intra_mbAddrA_Cb_reg2 + or Intra_mbAddrA_Cb_reg3 or Intra_mbAddrA_Cb_reg4 or Intra_mbAddrA_Cb_reg5 + or Intra_mbAddrA_Cb_reg6 or Intra_mbAddrA_Cb_reg7 + + or Intra_mbAddrA_Cr_reg0 or Intra_mbAddrA_Cr_reg1 or Intra_mbAddrA_Cr_reg2 + or Intra_mbAddrA_Cr_reg3 or Intra_mbAddrA_Cr_reg4 or Intra_mbAddrA_Cr_reg5 + or Intra_mbAddrA_Cr_reg6 or Intra_mbAddrA_Cr_reg7) + if (mb_type_general[3] == 1'b1) + begin + //Intra4x4 + //Intra16x16_Horizontal,Intra16x16_DC,Intra16x16_Plane + if (blk4x4_rec_counter < 16 && + (mb_type_general[2] == 1'b1 || (mb_type_general[2] == 1'b0 && ( + (Intra16x16_predmode == `Intra16x16_Horizontal && blk4x4_intra_calculate_counter != 0) || + (Intra16x16_predmode == `Intra16x16_DC && blk4x4_intra_calculate_counter != 0 && mbAddrA_availability == 1'b1) || + (Intra16x16_predmode == `Intra16x16_Plane && blk4x4_intra_precompute_counter != 0))))) + begin + Intra_mbAddrA_reg0 <= Intra_mbAddrA_luma_reg0; + Intra_mbAddrA_reg1 <= Intra_mbAddrA_luma_reg1; + Intra_mbAddrA_reg2 <= Intra_mbAddrA_luma_reg2; + Intra_mbAddrA_reg3 <= Intra_mbAddrA_luma_reg3; + Intra_mbAddrA_reg4 <= Intra_mbAddrA_luma_reg4; + Intra_mbAddrA_reg5 <= Intra_mbAddrA_luma_reg5; + Intra_mbAddrA_reg6 <= Intra_mbAddrA_luma_reg6; + Intra_mbAddrA_reg7 <= Intra_mbAddrA_luma_reg7; + Intra_mbAddrA_reg8 <= Intra_mbAddrA_luma_reg8; + Intra_mbAddrA_reg9 <= Intra_mbAddrA_luma_reg9; + Intra_mbAddrA_reg10 <= Intra_mbAddrA_luma_reg10; + Intra_mbAddrA_reg11 <= Intra_mbAddrA_luma_reg11; + Intra_mbAddrA_reg12 <= Intra_mbAddrA_luma_reg12; + Intra_mbAddrA_reg13 <= Intra_mbAddrA_luma_reg13; + Intra_mbAddrA_reg14 <= Intra_mbAddrA_luma_reg14; + Intra_mbAddrA_reg15 <= Intra_mbAddrA_luma_reg15; + end + //Chroma Cb + else if (blk4x4_rec_counter > 15 && blk4x4_rec_counter < 20 && ( + (Intra_chroma_predmode == `Intra_chroma_Horizontal && blk4x4_intra_calculate_counter != 0) || + (Intra_chroma_predmode == `Intra_chroma_DC && blk4x4_intra_calculate_counter != 0 && mbAddrA_availability == 1'b1) || + (Intra_chroma_predmode == `Intra_chroma_Plane && blk4x4_intra_precompute_counter != 0))) + begin + Intra_mbAddrA_reg0 <= Intra_mbAddrA_Cb_reg0; + Intra_mbAddrA_reg1 <= Intra_mbAddrA_Cb_reg1; + Intra_mbAddrA_reg2 <= Intra_mbAddrA_Cb_reg2; + Intra_mbAddrA_reg3 <= Intra_mbAddrA_Cb_reg3; + Intra_mbAddrA_reg4 <= Intra_mbAddrA_Cb_reg4; + Intra_mbAddrA_reg5 <= Intra_mbAddrA_Cb_reg5; + Intra_mbAddrA_reg6 <= Intra_mbAddrA_Cb_reg6; + Intra_mbAddrA_reg7 <= Intra_mbAddrA_Cb_reg7; + Intra_mbAddrA_reg8 <= 0; Intra_mbAddrA_reg9 <= 0; + Intra_mbAddrA_reg10 <= 0; Intra_mbAddrA_reg11 <= 0; + Intra_mbAddrA_reg12 <= 0; Intra_mbAddrA_reg13 <= 0; + Intra_mbAddrA_reg14 <= 0; Intra_mbAddrA_reg15 <= 0; + end + //Chroma Cr + else if (blk4x4_rec_counter > 19 && blk4x4_rec_counter < 24 && ( + (Intra_chroma_predmode == `Intra_chroma_Horizontal && blk4x4_intra_calculate_counter != 0) || + (Intra_chroma_predmode == `Intra_chroma_DC && blk4x4_intra_calculate_counter != 0 && mbAddrA_availability == 1'b1) || + (Intra_chroma_predmode == `Intra_chroma_Plane && blk4x4_intra_precompute_counter != 0))) + begin + Intra_mbAddrA_reg0 <= Intra_mbAddrA_Cr_reg0; + Intra_mbAddrA_reg1 <= Intra_mbAddrA_Cr_reg1; + Intra_mbAddrA_reg2 <= Intra_mbAddrA_Cr_reg2; + Intra_mbAddrA_reg3 <= Intra_mbAddrA_Cr_reg3; + Intra_mbAddrA_reg4 <= Intra_mbAddrA_Cr_reg4; + Intra_mbAddrA_reg5 <= Intra_mbAddrA_Cr_reg5; + Intra_mbAddrA_reg6 <= Intra_mbAddrA_Cr_reg6; + Intra_mbAddrA_reg7 <= Intra_mbAddrA_Cr_reg7; + Intra_mbAddrA_reg8 <= 0; Intra_mbAddrA_reg9 <= 0; + Intra_mbAddrA_reg10 <= 0; Intra_mbAddrA_reg11 <= 0; + Intra_mbAddrA_reg12 <= 0; Intra_mbAddrA_reg13 <= 0; + Intra_mbAddrA_reg14 <= 0; Intra_mbAddrA_reg15 <= 0; + end + else + begin + Intra_mbAddrA_reg0 <= 0; Intra_mbAddrA_reg1 <= 0; + Intra_mbAddrA_reg2 <= 0; Intra_mbAddrA_reg3 <= 0; + Intra_mbAddrA_reg4 <= 0; Intra_mbAddrA_reg5 <= 0; + Intra_mbAddrA_reg6 <= 0; Intra_mbAddrA_reg7 <= 0; + Intra_mbAddrA_reg8 <= 0; Intra_mbAddrA_reg9 <= 0; + Intra_mbAddrA_reg10 <= 0; Intra_mbAddrA_reg11 <= 0; + Intra_mbAddrA_reg12 <= 0; Intra_mbAddrA_reg13 <= 0; + Intra_mbAddrA_reg14 <= 0; Intra_mbAddrA_reg15 <= 0; + end + end + else + begin + Intra_mbAddrA_reg0 <= 0; Intra_mbAddrA_reg1 <= 0; + Intra_mbAddrA_reg2 <= 0; Intra_mbAddrA_reg3 <= 0; + Intra_mbAddrA_reg4 <= 0; Intra_mbAddrA_reg5 <= 0; + Intra_mbAddrA_reg6 <= 0; Intra_mbAddrA_reg7 <= 0; + Intra_mbAddrA_reg8 <= 0; Intra_mbAddrA_reg9 <= 0; + Intra_mbAddrA_reg10 <= 0; Intra_mbAddrA_reg11 <= 0; + Intra_mbAddrA_reg12 <= 0; Intra_mbAddrA_reg13 <= 0; + Intra_mbAddrA_reg14 <= 0; Intra_mbAddrA_reg15 <= 0; + end + //Intra_mbAddrA_window0 ~ 3 + always @ (mb_type_general or Intra16x16_predmode or Intra_chroma_predmode + or blk4x4_intra_calculate_counter or blk4x4_rec_counter or mbAddrA_availability + + or Intra_mbAddrA_reg0 or Intra_mbAddrA_reg1 or Intra_mbAddrA_reg2 or Intra_mbAddrA_reg3 + or Intra_mbAddrA_reg4 or Intra_mbAddrA_reg5 or Intra_mbAddrA_reg6 or Intra_mbAddrA_reg7 + or Intra_mbAddrA_reg8 or Intra_mbAddrA_reg9 or Intra_mbAddrA_reg10 or Intra_mbAddrA_reg11 + or Intra_mbAddrA_reg12 or Intra_mbAddrA_reg13 or Intra_mbAddrA_reg14 or Intra_mbAddrA_reg15 + + or Intra_mbAddrA_Cb_reg0 or Intra_mbAddrA_Cb_reg1 or Intra_mbAddrA_Cb_reg2 or Intra_mbAddrA_Cb_reg3 + or Intra_mbAddrA_Cb_reg4 or Intra_mbAddrA_Cb_reg5 or Intra_mbAddrA_Cb_reg6 or Intra_mbAddrA_Cb_reg7 + or Intra_mbAddrA_Cr_reg0 or Intra_mbAddrA_Cr_reg1 or Intra_mbAddrA_Cr_reg2 or Intra_mbAddrA_Cr_reg3 + or Intra_mbAddrA_Cr_reg4 or Intra_mbAddrA_Cr_reg5 or Intra_mbAddrA_Cr_reg6 or Intra_mbAddrA_Cr_reg7) + if (mb_type_general[3] == 1'b1) + begin + //Intra4x4 && Intra16x16_horizontal + if (blk4x4_rec_counter < 16 && blk4x4_intra_calculate_counter != 0 && + (mb_type_general[2] == 1'b1 || ( + (mb_type_general[2] == 1'b0 && Intra16x16_predmode == `Intra16x16_Horizontal)))) + case (blk4x4_rec_counter) + 0,1,4,5: + begin + Intra_mbAddrA_window0 <= Intra_mbAddrA_reg0; Intra_mbAddrA_window1 <= Intra_mbAddrA_reg1; + Intra_mbAddrA_window2 <= Intra_mbAddrA_reg2; Intra_mbAddrA_window3 <= Intra_mbAddrA_reg3; + end + 2,3,6,7: + begin + Intra_mbAddrA_window0 <= Intra_mbAddrA_reg4; Intra_mbAddrA_window1 <= Intra_mbAddrA_reg5; + Intra_mbAddrA_window2 <= Intra_mbAddrA_reg6; Intra_mbAddrA_window3 <= Intra_mbAddrA_reg7; + end + 8,9,12,13: + begin + Intra_mbAddrA_window0 <= Intra_mbAddrA_reg8; Intra_mbAddrA_window1 <= Intra_mbAddrA_reg9; + Intra_mbAddrA_window2 <= Intra_mbAddrA_reg10;Intra_mbAddrA_window3 <= Intra_mbAddrA_reg11; + end + 10,11,14,15: + begin + Intra_mbAddrA_window0 <= Intra_mbAddrA_reg12;Intra_mbAddrA_window1 <= Intra_mbAddrA_reg13; + Intra_mbAddrA_window2 <= Intra_mbAddrA_reg14;Intra_mbAddrA_window3 <= Intra_mbAddrA_reg15; + end + default: + begin + Intra_mbAddrA_window0 <= 0;Intra_mbAddrA_window1 <= 0; + Intra_mbAddrA_window2 <= 0;Intra_mbAddrA_window3 <= 0; + end + endcase + //Chroma Cb/Cr Horizontal & DC + else if (blk4x4_rec_counter > 15 && blk4x4_intra_calculate_counter != 0 && + (Intra_chroma_predmode == `Intra_chroma_Horizontal || (Intra_chroma_predmode == `Intra_chroma_DC && mbAddrA_availability))) + case (blk4x4_rec_counter) + 16,17: + begin + Intra_mbAddrA_window0 <= Intra_mbAddrA_Cb_reg0; + Intra_mbAddrA_window1 <= Intra_mbAddrA_Cb_reg1; + Intra_mbAddrA_window2 <= Intra_mbAddrA_Cb_reg2; + Intra_mbAddrA_window3 <= Intra_mbAddrA_Cb_reg3; + end + 18,19: + begin + Intra_mbAddrA_window0 <= Intra_mbAddrA_Cb_reg4; + Intra_mbAddrA_window1 <= Intra_mbAddrA_Cb_reg5; + Intra_mbAddrA_window2 <= Intra_mbAddrA_Cb_reg6; + Intra_mbAddrA_window3 <= Intra_mbAddrA_Cb_reg7; + end + 20,21: + begin + Intra_mbAddrA_window0 <= Intra_mbAddrA_Cr_reg0; + Intra_mbAddrA_window1 <= Intra_mbAddrA_Cr_reg1; + Intra_mbAddrA_window2 <= Intra_mbAddrA_Cr_reg2; + Intra_mbAddrA_window3 <= Intra_mbAddrA_Cr_reg3; + end + 22,23: + begin + Intra_mbAddrA_window0 <= Intra_mbAddrA_Cr_reg4; + Intra_mbAddrA_window1 <= Intra_mbAddrA_Cr_reg5; + Intra_mbAddrA_window2 <= Intra_mbAddrA_Cr_reg6; + Intra_mbAddrA_window3 <= Intra_mbAddrA_Cr_reg7; + end + default: + begin + Intra_mbAddrA_window0 <= 0;Intra_mbAddrA_window1 <= 0; + Intra_mbAddrA_window2 <= 0;Intra_mbAddrA_window3 <= 0; + end + endcase + else + begin + Intra_mbAddrA_window0 <= 0;Intra_mbAddrA_window1 <= 0; + Intra_mbAddrA_window2 <= 0;Intra_mbAddrA_window3 <= 0; + end + end + else + begin + Intra_mbAddrA_window0 <= 0;Intra_mbAddrA_window1 <= 0; + Intra_mbAddrA_window2 <= 0;Intra_mbAddrA_window3 <= 0; + end + + + //Intra_mbAddrB_window0 ~ 3 + always @ (mb_type_general or Intra16x16_predmode or Intra_chroma_predmode + or blk4x4_intra_calculate_counter or blk4x4_rec_counter + or Intra_mbAddrB_reg0 or Intra_mbAddrB_reg1 or Intra_mbAddrB_reg2 + or Intra_mbAddrB_reg3 or Intra_mbAddrB_reg4 or Intra_mbAddrB_reg5 + or Intra_mbAddrB_reg6 or Intra_mbAddrB_reg7 or Intra_mbAddrB_reg8 + or Intra_mbAddrB_reg9 or Intra_mbAddrB_reg10 or Intra_mbAddrB_reg11 + or Intra_mbAddrB_reg12 or Intra_mbAddrB_reg13 or Intra_mbAddrB_reg14 + or Intra_mbAddrB_reg15) + if (mb_type_general[3] == 1'b1) + begin + //Intra4x4 && Intra16x16_Vertical + if (blk4x4_rec_counter < 16 && blk4x4_intra_calculate_counter != 0 && + (mb_type_general[2] == 1'b1 || ( + (mb_type_general[2] == 1'b0 && Intra16x16_predmode == `Intra16x16_Vertical)))) + case (blk4x4_rec_counter) + 0,2,8,10: + begin + Intra_mbAddrB_window0 <= Intra_mbAddrB_reg0; + Intra_mbAddrB_window1 <= Intra_mbAddrB_reg1; + Intra_mbAddrB_window2 <= Intra_mbAddrB_reg2; + Intra_mbAddrB_window3 <= Intra_mbAddrB_reg3; + end + 1,3,9,11: + begin + Intra_mbAddrB_window0 <= Intra_mbAddrB_reg4; + Intra_mbAddrB_window1 <= Intra_mbAddrB_reg5; + Intra_mbAddrB_window2 <= Intra_mbAddrB_reg6; + Intra_mbAddrB_window3 <= Intra_mbAddrB_reg7; + end + 4,6,12,14: + begin + Intra_mbAddrB_window0 <= Intra_mbAddrB_reg8; + Intra_mbAddrB_window1 <= Intra_mbAddrB_reg9; + Intra_mbAddrB_window2 <= Intra_mbAddrB_reg10; + Intra_mbAddrB_window3 <= Intra_mbAddrB_reg11; + end + 5,7,13,15: + begin + Intra_mbAddrB_window0 <= Intra_mbAddrB_reg12; + Intra_mbAddrB_window1 <= Intra_mbAddrB_reg13; + Intra_mbAddrB_window2 <= Intra_mbAddrB_reg14; + Intra_mbAddrB_window3 <= Intra_mbAddrB_reg15; + end + default: + begin + Intra_mbAddrB_window0 <= 0;Intra_mbAddrB_window1 <= 0; + Intra_mbAddrB_window2 <= 0;Intra_mbAddrB_window3 <= 0; + end + endcase + //Chroma Cb/Cr Vertical and DC + else if (blk4x4_rec_counter > 15 && blk4x4_rec_counter < 24 && + (Intra_chroma_predmode == `Intra_chroma_Vertical || Intra_chroma_predmode == `Intra_chroma_DC) && blk4x4_intra_calculate_counter != 0) + case (blk4x4_rec_counter) + 16,18,20,22: + begin + Intra_mbAddrB_window0 <= Intra_mbAddrB_reg0; + Intra_mbAddrB_window1 <= Intra_mbAddrB_reg1; + Intra_mbAddrB_window2 <= Intra_mbAddrB_reg2; + Intra_mbAddrB_window3 <= Intra_mbAddrB_reg3; + end + 17,19,21,23: + begin + Intra_mbAddrB_window0 <= Intra_mbAddrB_reg4; + Intra_mbAddrB_window1 <= Intra_mbAddrB_reg5; + Intra_mbAddrB_window2 <= Intra_mbAddrB_reg6; + Intra_mbAddrB_window3 <= Intra_mbAddrB_reg7; + end + default: + begin + Intra_mbAddrB_window0 <= 0;Intra_mbAddrB_window1 <= 0; + Intra_mbAddrB_window2 <= 0;Intra_mbAddrB_window3 <= 0; + end + endcase + else + begin + Intra_mbAddrB_window0 <= 0;Intra_mbAddrB_window1 <= 0; + Intra_mbAddrB_window2 <= 0;Intra_mbAddrB_window3 <= 0; + end + end + else + begin + Intra_mbAddrB_window0 <= 0;Intra_mbAddrB_window1 <= 0; + Intra_mbAddrB_window2 <= 0;Intra_mbAddrB_window3 <= 0; + end + //Intra_mbAddrC_window0 ~ 3 + always @ (mb_type_general[3:2] or blk4x4_intra_calculate_counter or blk4x4_rec_counter or Intra4x4_predmode + or Intra_mbAddrC_reg0 or Intra_mbAddrC_reg1 or Intra_mbAddrC_reg2 or Intra_mbAddrC_reg3 + or Intra_mbAddrB_reg4 or Intra_mbAddrB_reg5 or Intra_mbAddrB_reg6 or Intra_mbAddrB_reg7 + or Intra_mbAddrB_reg8 or Intra_mbAddrB_reg9 or Intra_mbAddrB_reg10 or Intra_mbAddrB_reg11 + or Intra_mbAddrB_reg12 or Intra_mbAddrB_reg13 or Intra_mbAddrB_reg14 or Intra_mbAddrB_reg15 + or mbAddrC_availability or Intra_mbAddrB_window3) + if (mb_type_general[3:2] == 2'b11 && blk4x4_intra_calculate_counter != 0 && ( + Intra4x4_predmode == `Intra4x4_Diagonal_Down_Left || Intra4x4_predmode == `Intra4x4_Vertical_Left) && blk4x4_rec_counter < 16) + case (blk4x4_rec_counter) + 0,1,4: + begin + Intra_mbAddrC_window0 <= Intra_mbAddrC_reg0; + Intra_mbAddrC_window1 <= Intra_mbAddrC_reg1; + Intra_mbAddrC_window2 <= Intra_mbAddrC_reg2; + Intra_mbAddrC_window3 <= Intra_mbAddrC_reg3; + end + 5: + begin + Intra_mbAddrC_window0 <= (mbAddrC_availability)? Intra_mbAddrC_reg0:Intra_mbAddrB_reg15; + Intra_mbAddrC_window1 <= (mbAddrC_availability)? Intra_mbAddrC_reg1:Intra_mbAddrB_reg15; + Intra_mbAddrC_window2 <= (mbAddrC_availability)? Intra_mbAddrC_reg2:Intra_mbAddrB_reg15; + Intra_mbAddrC_window3 <= (mbAddrC_availability)? Intra_mbAddrC_reg3:Intra_mbAddrB_reg15; + end + 2,8,10: + begin + Intra_mbAddrC_window0 <= Intra_mbAddrB_reg4; + Intra_mbAddrC_window1 <= Intra_mbAddrB_reg5; + Intra_mbAddrC_window2 <= Intra_mbAddrB_reg6; + Intra_mbAddrC_window3 <= Intra_mbAddrB_reg7; + end + 9: + begin + Intra_mbAddrC_window0 <= Intra_mbAddrB_reg8; + Intra_mbAddrC_window1 <= Intra_mbAddrB_reg9; + Intra_mbAddrC_window2 <= Intra_mbAddrB_reg10; + Intra_mbAddrC_window3 <= Intra_mbAddrB_reg11; + end + 6,12,14: + begin + Intra_mbAddrC_window0 <= Intra_mbAddrB_reg12; + Intra_mbAddrC_window1 <= Intra_mbAddrB_reg13; + Intra_mbAddrC_window2 <= Intra_mbAddrB_reg14; + Intra_mbAddrC_window3 <= Intra_mbAddrB_reg15; + end + 3,11,7,13,15: + begin + Intra_mbAddrC_window0 <= Intra_mbAddrB_window3; + Intra_mbAddrC_window1 <= Intra_mbAddrB_window3; + Intra_mbAddrC_window2 <= Intra_mbAddrB_window3; + Intra_mbAddrC_window3 <= Intra_mbAddrB_window3; + end + default: + begin + Intra_mbAddrC_window0 <= 0; Intra_mbAddrC_window1 <= 0; + Intra_mbAddrC_window2 <= 0; Intra_mbAddrC_window3 <= 0; + end + endcase + else + begin + Intra_mbAddrC_window0 <= 0; Intra_mbAddrC_window1 <= 0; + Intra_mbAddrC_window2 <= 0; Intra_mbAddrC_window3 <= 0; + end + + //Intra_mbAddrD_window + always @ (mb_type_general[3:2] or blk4x4_rec_counter + or blk4x4_intra_calculate_counter or blk4x4_intra_precompute_counter + or Intra4x4_predmode or Intra16x16_predmode or Intra_chroma_predmode + or Intra_mbAddrD_reg0 or Intra_mbAddrD_reg1 or Intra_mbAddrD_reg2 + or Intra_mbAddrD_reg3 or Intra_mbAddrD_reg4 + or Intra_mbAddrD_LeftMB_luma_reg or Intra_mbAddrD_LeftMB_Cb_reg or Intra_mbAddrD_LeftMB_Cr_reg) + //Intra + if (mb_type_general[3] == 1'b1 && (blk4x4_intra_calculate_counter != 0 || blk4x4_intra_precompute_counter != 0)) + begin + //Intra luma + if (blk4x4_rec_counter[4] == 1'b0) + begin + //Intra4x4 luma + if (mb_type_general[2] == 1'b1 && (Intra4x4_predmode == `Intra4x4_Diagonal_Down_Right || + Intra4x4_predmode == `Intra4x4_Vertical_Right || + Intra4x4_predmode == `Intra4x4_Horizontal_Down)) + case (blk4x4_rec_counter[3:0]) + 0,2,8,10:Intra_mbAddrD_window <= Intra_mbAddrD_LeftMB_luma_reg; + 3,5,13 :Intra_mbAddrD_window <= Intra_mbAddrD_reg0; + 1,6,11 :Intra_mbAddrD_window <= Intra_mbAddrD_reg1; + 9,15 :Intra_mbAddrD_window <= Intra_mbAddrD_reg2; + 12 :Intra_mbAddrD_window <= Intra_mbAddrD_reg3; + 4,7,14 :Intra_mbAddrD_window <= Intra_mbAddrD_reg4; + endcase + //Intra16x16 + else + Intra_mbAddrD_window <= (Intra16x16_predmode == `Intra16x16_Plane)? Intra_mbAddrD_LeftMB_luma_reg:0; + end + //Intra chroma + else if (blk4x4_rec_counter > 15 && Intra_chroma_predmode == `Intra_chroma_Plane) + Intra_mbAddrD_window <= (blk4x4_rec_counter < 20)? Intra_mbAddrD_LeftMB_Cb_reg:Intra_mbAddrD_LeftMB_Cr_reg; + else + Intra_mbAddrD_window <= 0; + end + //Inter + else + Intra_mbAddrD_window <= 0; + + //seed + always @ (posedge gclk_seed or negedge reset_n) + if (reset_n == 1'b0) + begin + seed_0 <= 0; seed_1 <= 0; seed_2 <= 0; + end + else if (blk4x4_intra_precompute_counter == 1) + seed_0 <= main_seed; + else + case (blk4x4_rec_counter) + 0,2,8,16,20 :seed_0 <= PE3_sum_out; + 1,9 :seed_1 <= PE0_sum_out; + 3,11 :seed_2 <= PE0_sum_out; + endcase + + always @ (mb_type_general[3:2] or Intra16x16_predmode or Intra_chroma_predmode + or blk4x4_intra_calculate_counter or blk4x4_rec_counter or seed_0 or seed_1 or seed_2) + if (mb_type_general[3:2] == 2'b10 && Intra16x16_predmode == `Intra16x16_Plane && blk4x4_intra_calculate_counter == 4 && blk4x4_rec_counter < 16) + case (blk4x4_rec_counter) + 0,2,8,10:seed <= seed_0; + 4,12 :seed <= seed_1; + 6,14 :seed <= seed_2; + default :seed <= 0; + endcase + else if (mb_type_general[3] == 1'b1 && Intra_chroma_predmode == `Intra_chroma_Plane && blk4x4_intra_calculate_counter == 4 && blk4x4_rec_counter > 15) + if (blk4x4_rec_counter[0] == 1'b0) //16,18,20,22 + seed <= seed_0; + else + seed <= 0; + else + seed <= 0; + +endmodule + + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/Intra_pred_top.v b/demo_chip_rtl/rtl/nova/trunk/src/Intra_pred_top.v new file mode 100644 index 0000000..4fc626b --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/Intra_pred_top.v @@ -0,0 +1,334 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : Intra_pred_top.v +// Generated : Sep 30,2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Top module of Intra prediction +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module Intra_pred_top (clk,reset_n, + gclk_intra_mbAddrA_luma,gclk_intra_mbAddrA_Cb,gclk_intra_mbAddrA_Cr,gclk_intra_mbAddrB, + gclk_intra_mbAddrC_luma,gclk_intra_mbAddrD,gclk_seed,gclk_Intra_mbAddrB_RAM, + mb_num_h,mb_num_v,mb_type_general,NextMB_IsSkip, + Intra16x16_predmode,Intra4x4_predmode_CurrMb,Intra_chroma_predmode, + blk4x4_rec_counter,trigger_blk4x4_intra_pred,blk4x4_sum_counter, + sum_right_column_reg,blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out, + blk4x4_pred_output0, blk4x4_pred_output1, blk4x4_pred_output2, + blk4x4_pred_output4, blk4x4_pred_output5, blk4x4_pred_output6, + blk4x4_pred_output8, blk4x4_pred_output9, blk4x4_pred_output10, + blk4x4_pred_output12,blk4x4_pred_output13,blk4x4_pred_output14, + Intra_mbAddrB_RAM_wr,Intra_mbAddrB_RAM_wr_addr,Intra_mbAddrB_RAM_din, + + PE0_out,PE1_out,PE2_out,PE3_out,Intra4x4_predmode, + blk4x4_intra_preload_counter,blk4x4_intra_precompute_counter,blk4x4_intra_calculate_counter, + end_of_one_blk4x4_intra,Intra_mbAddrB_RAM_rd + ); + input clk,reset_n; + input gclk_intra_mbAddrA_luma; + input gclk_intra_mbAddrA_Cb; + input gclk_intra_mbAddrA_Cr; + input gclk_intra_mbAddrB; + input gclk_intra_mbAddrC_luma; + input gclk_intra_mbAddrD; + input gclk_seed; + input gclk_Intra_mbAddrB_RAM; + input [3:0] mb_num_h; + input [3:0] mb_num_v; + input [3:0] mb_type_general; + input NextMB_IsSkip; + input [1:0] Intra16x16_predmode; + input [63:0] Intra4x4_predmode_CurrMb; + input [1:0] Intra_chroma_predmode; + input [4:0] blk4x4_rec_counter; + input trigger_blk4x4_intra_pred; + input [2:0] blk4x4_sum_counter; + input [23:0] sum_right_column_reg; + input [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out; + input [7:0] blk4x4_pred_output0, blk4x4_pred_output1, blk4x4_pred_output2; + input [7:0] blk4x4_pred_output4, blk4x4_pred_output5, blk4x4_pred_output6; + input [7:0] blk4x4_pred_output8, blk4x4_pred_output9, blk4x4_pred_output10; + input [7:0] blk4x4_pred_output12,blk4x4_pred_output13,blk4x4_pred_output14; + input Intra_mbAddrB_RAM_wr; + input [6:0] Intra_mbAddrB_RAM_wr_addr; + input [31:0] Intra_mbAddrB_RAM_din; + + output [7:0] PE0_out; + output [7:0] PE1_out; + output [7:0] PE2_out; + output [7:0] PE3_out; + output [3:0] Intra4x4_predmode; + output [2:0] blk4x4_intra_preload_counter; + output [3:0] blk4x4_intra_precompute_counter; + output [2:0] blk4x4_intra_calculate_counter; + output end_of_one_blk4x4_intra; + output Intra_mbAddrB_RAM_rd; + + wire blkAddrA_availability,blkAddrB_availability; + wire mbAddrA_availability,mbAddrB_availability,mbAddrC_availability; + wire [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out; + wire [15:0] PE0_sum_out,PE3_sum_out; + wire Intra_mbAddrB_RAM_rd; + wire [6:0] Intra_mbAddrB_RAM_rd_addr; + wire [31:0] Intra_mbAddrB_RAM_dout; + + wire [7:0] Intra_mbAddrA_window0,Intra_mbAddrA_window1,Intra_mbAddrA_window2,Intra_mbAddrA_window3; + wire [7:0] Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3; + wire [7:0] Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7; + wire [7:0] Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11; + wire [7:0] Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15; + + wire [7:0] Intra_mbAddrB_window0,Intra_mbAddrB_window1,Intra_mbAddrB_window2,Intra_mbAddrB_window3; + wire [7:0] Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3; + wire [7:0] Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7; + wire [7:0] Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11; + wire [7:0] Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15; + + wire [7:0] Intra_mbAddrC_window0,Intra_mbAddrC_window1,Intra_mbAddrC_window2,Intra_mbAddrC_window3; + wire [7:0] Intra_mbAddrD_window; + wire [15:0] main_seed,seed; + wire [11:0] plane_b_reg,plane_c_reg; + + Intra_pred_pipeline Intra_pred_pipeline ( + .clk(clk), + .reset_n(reset_n), + .mb_type_general(mb_type_general), + .blk4x4_rec_counter(blk4x4_rec_counter), + .trigger_blk4x4_intra_pred(trigger_blk4x4_intra_pred), + .mb_num_v(mb_num_v), + .mb_num_h(mb_num_h), + .blk4x4_sum_counter(blk4x4_sum_counter), + .NextMB_IsSkip(NextMB_IsSkip), + .Intra16x16_predmode(Intra16x16_predmode), + .Intra4x4_predmode_CurrMb(Intra4x4_predmode_CurrMb), + .Intra_chroma_predmode(Intra_chroma_predmode), + .Intra_mbAddrA_reg0(Intra_mbAddrA_reg0), + .Intra_mbAddrA_reg1(Intra_mbAddrA_reg1), + .Intra_mbAddrA_reg2(Intra_mbAddrA_reg2), + .Intra_mbAddrA_reg3(Intra_mbAddrA_reg3), + .Intra_mbAddrA_reg4(Intra_mbAddrA_reg4), + .Intra_mbAddrA_reg5(Intra_mbAddrA_reg5), + .Intra_mbAddrA_reg6(Intra_mbAddrA_reg6), + .Intra_mbAddrA_reg7(Intra_mbAddrA_reg7), + .Intra_mbAddrA_reg8(Intra_mbAddrA_reg8), + .Intra_mbAddrA_reg9(Intra_mbAddrA_reg9), + .Intra_mbAddrA_reg10(Intra_mbAddrA_reg10), + .Intra_mbAddrA_reg11(Intra_mbAddrA_reg11), + .Intra_mbAddrA_reg12(Intra_mbAddrA_reg12), + .Intra_mbAddrA_reg13(Intra_mbAddrA_reg13), + .Intra_mbAddrA_reg14(Intra_mbAddrA_reg14), + .Intra_mbAddrA_reg15(Intra_mbAddrA_reg15), + .Intra_mbAddrB_reg0(Intra_mbAddrB_reg0), + .Intra_mbAddrB_reg1(Intra_mbAddrB_reg1), + .Intra_mbAddrB_reg2(Intra_mbAddrB_reg2), + .Intra_mbAddrB_reg3(Intra_mbAddrB_reg3), + .Intra_mbAddrB_reg4(Intra_mbAddrB_reg4), + .Intra_mbAddrB_reg5(Intra_mbAddrB_reg5), + .Intra_mbAddrB_reg6(Intra_mbAddrB_reg6), + .Intra_mbAddrB_reg7(Intra_mbAddrB_reg7), + .Intra_mbAddrB_reg8(Intra_mbAddrB_reg8), + .Intra_mbAddrB_reg9(Intra_mbAddrB_reg9), + .Intra_mbAddrB_reg10(Intra_mbAddrB_reg10), + .Intra_mbAddrB_reg11(Intra_mbAddrB_reg11), + .Intra_mbAddrB_reg12(Intra_mbAddrB_reg12), + .Intra_mbAddrB_reg13(Intra_mbAddrB_reg13), + .Intra_mbAddrB_reg14(Intra_mbAddrB_reg14), + .Intra_mbAddrB_reg15(Intra_mbAddrB_reg15), + .Intra_mbAddrD_window(Intra_mbAddrD_window), + + .Intra4x4_predmode(Intra4x4_predmode), + .blk4x4_intra_preload_counter(blk4x4_intra_preload_counter), + .blk4x4_intra_precompute_counter(blk4x4_intra_precompute_counter), + .blk4x4_intra_calculate_counter(blk4x4_intra_calculate_counter), + .end_of_one_blk4x4_intra(end_of_one_blk4x4_intra), + .blkAddrA_availability(blkAddrA_availability), + .blkAddrB_availability(blkAddrB_availability), + .mbAddrA_availability(mbAddrA_availability), + .mbAddrB_availability(mbAddrB_availability), + .mbAddrC_availability(mbAddrC_availability), + .main_seed(main_seed), + .plane_b_reg(plane_b_reg), + .plane_c_reg(plane_c_reg), + .Intra_mbAddrB_RAM_rd(Intra_mbAddrB_RAM_rd), + .Intra_mbAddrB_RAM_rd_addr(Intra_mbAddrB_RAM_rd_addr) + ); + + Intra_pred_reg_ctrl Intra_pred_reg_ctrl ( + .reset_n(reset_n), + .gclk_intra_mbAddrA_luma(gclk_intra_mbAddrA_luma), + .gclk_intra_mbAddrA_Cb(gclk_intra_mbAddrA_Cb), + .gclk_intra_mbAddrA_Cr(gclk_intra_mbAddrA_Cr), + .gclk_intra_mbAddrB(gclk_intra_mbAddrB), + .gclk_intra_mbAddrC_luma(gclk_intra_mbAddrC_luma), + .gclk_intra_mbAddrD(gclk_intra_mbAddrD), + .gclk_seed(gclk_seed), + .mbAddrA_availability(mbAddrA_availability), + .mbAddrC_availability(mbAddrC_availability), + .blk4x4_rec_counter(blk4x4_rec_counter), + .blk4x4_sum_counter(blk4x4_sum_counter), + .blk4x4_intra_preload_counter(blk4x4_intra_preload_counter), + .blk4x4_intra_precompute_counter(blk4x4_intra_precompute_counter), + .blk4x4_intra_calculate_counter(blk4x4_intra_calculate_counter), + .mb_type_general(mb_type_general), + .Intra4x4_predmode(Intra4x4_predmode), + .Intra16x16_predmode(Intra16x16_predmode), + .Intra_chroma_predmode(Intra_chroma_predmode), + .Intra_mbAddrB_RAM_dout(Intra_mbAddrB_RAM_dout), + .sum_right_column_reg(sum_right_column_reg), + .blk4x4_sum_PE0_out(blk4x4_sum_PE0_out), + .blk4x4_sum_PE1_out(blk4x4_sum_PE1_out), + .blk4x4_sum_PE2_out(blk4x4_sum_PE2_out), + .blk4x4_sum_PE3_out(blk4x4_sum_PE3_out), + .main_seed(main_seed), + .PE0_sum_out(PE0_sum_out), + .PE3_sum_out(PE3_sum_out), + + .Intra_mbAddrA_window0(Intra_mbAddrA_window0), + .Intra_mbAddrA_window1(Intra_mbAddrA_window1), + .Intra_mbAddrA_window2(Intra_mbAddrA_window2), + .Intra_mbAddrA_window3(Intra_mbAddrA_window3), + .Intra_mbAddrA_reg0(Intra_mbAddrA_reg0), + .Intra_mbAddrA_reg1(Intra_mbAddrA_reg1), + .Intra_mbAddrA_reg2(Intra_mbAddrA_reg2), + .Intra_mbAddrA_reg3(Intra_mbAddrA_reg3), + .Intra_mbAddrA_reg4(Intra_mbAddrA_reg4), + .Intra_mbAddrA_reg5(Intra_mbAddrA_reg5), + .Intra_mbAddrA_reg6(Intra_mbAddrA_reg6), + .Intra_mbAddrA_reg7(Intra_mbAddrA_reg7), + .Intra_mbAddrA_reg8(Intra_mbAddrA_reg8), + .Intra_mbAddrA_reg9(Intra_mbAddrA_reg9), + .Intra_mbAddrA_reg10(Intra_mbAddrA_reg10), + .Intra_mbAddrA_reg11(Intra_mbAddrA_reg11), + .Intra_mbAddrA_reg12(Intra_mbAddrA_reg12), + .Intra_mbAddrA_reg13(Intra_mbAddrA_reg13), + .Intra_mbAddrA_reg14(Intra_mbAddrA_reg14), + .Intra_mbAddrA_reg15(Intra_mbAddrA_reg15), + .Intra_mbAddrB_window0(Intra_mbAddrB_window0), + .Intra_mbAddrB_window1(Intra_mbAddrB_window1), + .Intra_mbAddrB_window2(Intra_mbAddrB_window2), + .Intra_mbAddrB_window3(Intra_mbAddrB_window3), + .Intra_mbAddrB_reg0(Intra_mbAddrB_reg0), + .Intra_mbAddrB_reg1(Intra_mbAddrB_reg1), + .Intra_mbAddrB_reg2(Intra_mbAddrB_reg2), + .Intra_mbAddrB_reg3(Intra_mbAddrB_reg3), + .Intra_mbAddrB_reg4(Intra_mbAddrB_reg4), + .Intra_mbAddrB_reg5(Intra_mbAddrB_reg5), + .Intra_mbAddrB_reg6(Intra_mbAddrB_reg6), + .Intra_mbAddrB_reg7(Intra_mbAddrB_reg7), + .Intra_mbAddrB_reg8(Intra_mbAddrB_reg8), + .Intra_mbAddrB_reg9(Intra_mbAddrB_reg9), + .Intra_mbAddrB_reg10(Intra_mbAddrB_reg10), + .Intra_mbAddrB_reg11(Intra_mbAddrB_reg11), + .Intra_mbAddrB_reg12(Intra_mbAddrB_reg12), + .Intra_mbAddrB_reg13(Intra_mbAddrB_reg13), + .Intra_mbAddrB_reg14(Intra_mbAddrB_reg14), + .Intra_mbAddrB_reg15(Intra_mbAddrB_reg15), + .Intra_mbAddrC_window0(Intra_mbAddrC_window0), + .Intra_mbAddrC_window1(Intra_mbAddrC_window1), + .Intra_mbAddrC_window2(Intra_mbAddrC_window2), + .Intra_mbAddrC_window3(Intra_mbAddrC_window3), + .Intra_mbAddrD_window(Intra_mbAddrD_window), + .seed(seed) + ); + + Intra_pred_PE Intra_pred_PE ( + .clk(clk), + .reset_n(reset_n), + .mb_type_general(mb_type_general), + .blk4x4_rec_counter(blk4x4_rec_counter), + .blk4x4_intra_calculate_counter(blk4x4_intra_calculate_counter), + .Intra4x4_predmode(Intra4x4_predmode), + .Intra16x16_predmode(Intra16x16_predmode), + .Intra_chroma_predmode(Intra_chroma_predmode), + .blkAddrA_availability(blkAddrA_availability), + .blkAddrB_availability(blkAddrB_availability), + .mbAddrA_availability(mbAddrA_availability), + .mbAddrB_availability(mbAddrB_availability), + .Intra_mbAddrA_window0({8'b0,Intra_mbAddrA_window0}), + .Intra_mbAddrA_window1({8'b0,Intra_mbAddrA_window1}), + .Intra_mbAddrA_window2({8'b0,Intra_mbAddrA_window2}), + .Intra_mbAddrA_window3({8'b0,Intra_mbAddrA_window3}), + .Intra_mbAddrB_window0({8'b0,Intra_mbAddrB_window0}), + .Intra_mbAddrB_window1({8'b0,Intra_mbAddrB_window1}), + .Intra_mbAddrB_window2({8'b0,Intra_mbAddrB_window2}), + .Intra_mbAddrB_window3({8'b0,Intra_mbAddrB_window3}), + .Intra_mbAddrC_window0({8'b0,Intra_mbAddrC_window0}), + .Intra_mbAddrC_window1({8'b0,Intra_mbAddrC_window1}), + .Intra_mbAddrC_window2({8'b0,Intra_mbAddrC_window2}), + .Intra_mbAddrC_window3({8'b0,Intra_mbAddrC_window3}), + .Intra_mbAddrD_window({8'b0,Intra_mbAddrD_window}), + .Intra_mbAddrA_reg0({8'b0,Intra_mbAddrA_reg0}), + .Intra_mbAddrA_reg1({8'b0,Intra_mbAddrA_reg1}), + .Intra_mbAddrA_reg2({8'b0,Intra_mbAddrA_reg2}), + .Intra_mbAddrA_reg3({8'b0,Intra_mbAddrA_reg3}), + .Intra_mbAddrA_reg4({8'b0,Intra_mbAddrA_reg4}), + .Intra_mbAddrA_reg5({8'b0,Intra_mbAddrA_reg5}), + .Intra_mbAddrA_reg6({8'b0,Intra_mbAddrA_reg6}), + .Intra_mbAddrA_reg7({8'b0,Intra_mbAddrA_reg7}), + .Intra_mbAddrA_reg8({8'b0,Intra_mbAddrA_reg8}), + .Intra_mbAddrA_reg9({8'b0,Intra_mbAddrA_reg9}), + .Intra_mbAddrA_reg10({8'b0,Intra_mbAddrA_reg10}), + .Intra_mbAddrA_reg11({8'b0,Intra_mbAddrA_reg11}), + .Intra_mbAddrA_reg12({8'b0,Intra_mbAddrA_reg12}), + .Intra_mbAddrA_reg13({8'b0,Intra_mbAddrA_reg13}), + .Intra_mbAddrA_reg14({8'b0,Intra_mbAddrA_reg14}), + .Intra_mbAddrA_reg15({8'b0,Intra_mbAddrA_reg15}), + .Intra_mbAddrB_reg0({8'b0,Intra_mbAddrB_reg0}), + .Intra_mbAddrB_reg1({8'b0,Intra_mbAddrB_reg1}), + .Intra_mbAddrB_reg2({8'b0,Intra_mbAddrB_reg2}), + .Intra_mbAddrB_reg3({8'b0,Intra_mbAddrB_reg3}), + .Intra_mbAddrB_reg4({8'b0,Intra_mbAddrB_reg4}), + .Intra_mbAddrB_reg5({8'b0,Intra_mbAddrB_reg5}), + .Intra_mbAddrB_reg6({8'b0,Intra_mbAddrB_reg6}), + .Intra_mbAddrB_reg7({8'b0,Intra_mbAddrB_reg7}), + .Intra_mbAddrB_reg8({8'b0,Intra_mbAddrB_reg8}), + .Intra_mbAddrB_reg9({8'b0,Intra_mbAddrB_reg9}), + .Intra_mbAddrB_reg10({8'b0,Intra_mbAddrB_reg10}), + .Intra_mbAddrB_reg11({8'b0,Intra_mbAddrB_reg11}), + .Intra_mbAddrB_reg12({8'b0,Intra_mbAddrB_reg12}), + .Intra_mbAddrB_reg13({8'b0,Intra_mbAddrB_reg13}), + .Intra_mbAddrB_reg14({8'b0,Intra_mbAddrB_reg14}), + .Intra_mbAddrB_reg15({8'b0,Intra_mbAddrB_reg15}), + .blk4x4_pred_output0({8'b0,blk4x4_pred_output0}), + .blk4x4_pred_output1({8'b0,blk4x4_pred_output1}), + .blk4x4_pred_output2({8'b0,blk4x4_pred_output2}), + .blk4x4_pred_output4({8'b0,blk4x4_pred_output4}), + .blk4x4_pred_output5({8'b0,blk4x4_pred_output5}), + .blk4x4_pred_output6({8'b0,blk4x4_pred_output6}), + .blk4x4_pred_output8({8'b0,blk4x4_pred_output8}), + .blk4x4_pred_output9({8'b0,blk4x4_pred_output9}), + .blk4x4_pred_output10({8'b0,blk4x4_pred_output10}), + .blk4x4_pred_output12({8'b0,blk4x4_pred_output12}), + .blk4x4_pred_output13({8'b0,blk4x4_pred_output13}), + .blk4x4_pred_output14({8'b0,blk4x4_pred_output14}), + .seed(seed), + .b(plane_b_reg), + .c(plane_c_reg), + + .PE0_out(PE0_out), + .PE1_out(PE1_out), + .PE2_out(PE2_out), + .PE3_out(PE3_out), + .PE0_sum_out(PE0_sum_out), + .PE3_sum_out(PE3_sum_out) + ); + ram_sync_1r_sync_1w #(`Intra_mbAddrB_RAM_data_width,`Intra_mbAddrB_RAM_data_depth) + Intra_mbAddrB_RAM ( + .clk(gclk_Intra_mbAddrB_RAM), + .rst_n(reset_n), + .wr_n(~Intra_mbAddrB_RAM_wr), + .rd_n(~Intra_mbAddrB_RAM_rd), + .wr_addr(Intra_mbAddrB_RAM_wr_addr), + .rd_addr(Intra_mbAddrB_RAM_rd_addr), + .data_in(Intra_mbAddrB_RAM_din), + .data_out(Intra_mbAddrB_RAM_dout) + ); +endmodule \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/NumCoeffTrailingOnes_decoding.v b/demo_chip_rtl/rtl/nova/trunk/src/NumCoeffTrailingOnes_decoding.v new file mode 100644 index 0000000..57a2866 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/NumCoeffTrailingOnes_decoding.v @@ -0,0 +1,678 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : NumCoeffTrailingOnes_decoding.v +// Generated : June 8, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Decoding for Table 9-5 on Page159 of H.264/AVC standard 2003 +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module NumCoeffTrailingOnes_decoding (clk,reset_n,cavlc_decoder_state,heading_one_pos,BitStream_buffer_output, + nC,TrailingOnes,TotalCoeff,NumCoeffTrailingOnes_len); + input clk,reset_n; + input [3:0] cavlc_decoder_state; + input [3:0] heading_one_pos; + input [15:0] BitStream_buffer_output; + input [4:0] nC; + output [1:0] TrailingOnes; + output [4:0] TotalCoeff; + output [4:0] NumCoeffTrailingOnes_len; + reg [1:0] TrailingOnes; + reg [4:0] TotalCoeff; + reg [4:0] NumCoeffTrailingOnes_len; + + reg [1:0] TrailingOnes_reg; + reg [4:0] TotalCoeff_reg; + + wire nC_0to2,nC_2to4,nC_4to8,nC_n1,nC_GE8; + wire nC_0to2_t0,nC_0to2_t1,nC_0to2_t2,nC_0to2_t3; + wire nC_2to4_t0,nC_2to4_t1,nC_2to4_t2,nC_2to4_t3; + wire nC_4to8_t0,nC_4to8_t1; + wire nC_n1_t0; + //Select nC values to choose table + assign nC_0to2 = (cavlc_decoder_state == `NumCoeffTrailingOnes_LUT && (nC == 5'd0 || nC == 5'd1)); + assign nC_2to4 = (cavlc_decoder_state == `NumCoeffTrailingOnes_LUT && (nC == 5'd2 || nC == 5'd3)); + assign nC_4to8 = (cavlc_decoder_state == `NumCoeffTrailingOnes_LUT && (nC == 5'd4 || nC == 5'd5 || nC == 5'd6 || nC == 5'd7)); + assign nC_n1 = (cavlc_decoder_state == `NumCoeffTrailingOnes_LUT && (nC == 5'd31)); + assign nC_GE8 = (cavlc_decoder_state == `NumCoeffTrailingOnes_LUT && !nC_0to2 && !nC_2to4 && !nC_4to8 && !nC_n1); + + //1.nC_0to2 t0 ~ t4 sub-table selection + assign nC_0to2_t0 = (nC_0to2 && (heading_one_pos == 4'd0 || heading_one_pos == 4'd1 || heading_one_pos == 4'd2)); + assign nC_0to2_t1 = (nC_0to2 && (heading_one_pos == 4'd3 || heading_one_pos == 4'd4)); + assign nC_0to2_t2 = (nC_0to2 && (heading_one_pos == 4'd5 || heading_one_pos == 4'd6 || heading_one_pos == 4'd7 || heading_one_pos == 4'd8)); + assign nC_0to2_t3 = (nC_0to2 && (heading_one_pos == 4'd9 || heading_one_pos == 4'd10)); + //2.nC_2to4 t0 ~ t4 sub-table selection + assign nC_2to4_t0 = (nC_2to4 && (heading_one_pos == 4'd0 || heading_one_pos == 4'd1)); + assign nC_2to4_t1 = (nC_2to4 && (heading_one_pos == 4'd2 || heading_one_pos == 4'd3)); + assign nC_2to4_t2 = (nC_2to4 && (heading_one_pos == 4'd4 || heading_one_pos == 4'd5 || heading_one_pos == 4'd6)); + assign nC_2to4_t3 = (nC_2to4 && (heading_one_pos == 4'd7 || heading_one_pos == 4'd8)); + //3.nC_4to8 t0 ~ t2 sub-table selection + assign nC_4to8_t0 = (nC_4to8 && heading_one_pos == 4'd0); + assign nC_4to8_t1 = (nC_4to8 && (heading_one_pos == 4'd1 || heading_one_pos == 4'd2 || heading_one_pos == 4'd3 || heading_one_pos == 4'd4)); + //4.nC_GE8:single table, NO sub-table selection + //5.nC_n1 t0 ~ t1 sub-table selection + assign nC_n1_t0 = (nC_n1 && (heading_one_pos == 4'd0 || heading_one_pos == 4'd1 || heading_one_pos == 4'd2)); + + //NumCoeffTrailingOnes_len + always @ (nC_0to2 or nC_2to4 or nC_4to8 or nC_GE8 or nC_n1 or heading_one_pos or BitStream_buffer_output) + if (nC_0to2) + case (heading_one_pos) + 0 :NumCoeffTrailingOnes_len <= 5'd1; + 1 :NumCoeffTrailingOnes_len <= 5'd2; + 2 :NumCoeffTrailingOnes_len <= 5'd3; + 3 :NumCoeffTrailingOnes_len <= (BitStream_buffer_output[11] == 1)? 5'd5:5'd6; + 4 :NumCoeffTrailingOnes_len <= (BitStream_buffer_output[10] == 1)? 5'd6:5'd7; + 5 :NumCoeffTrailingOnes_len <= 5'd8; + 6 :NumCoeffTrailingOnes_len <= 5'd9; + 7 :NumCoeffTrailingOnes_len <= 5'd10; + 8 :NumCoeffTrailingOnes_len <= 5'd11; + 9 :NumCoeffTrailingOnes_len <= 5'd13; + 10:NumCoeffTrailingOnes_len <= 5'd14; + 11:NumCoeffTrailingOnes_len <= 5'd15; + 12:NumCoeffTrailingOnes_len <= 5'd16; + 13:NumCoeffTrailingOnes_len <= 5'd16; + 14:NumCoeffTrailingOnes_len <= 5'd15; + default:NumCoeffTrailingOnes_len <= 5'd0; + endcase + else if (nC_2to4) + case (heading_one_pos) + 0 :NumCoeffTrailingOnes_len <= 5'd2; + 1 :NumCoeffTrailingOnes_len <= (BitStream_buffer_output[13] == 1)? 5'd3:5'd4; + 2 :NumCoeffTrailingOnes_len <= (BitStream_buffer_output[12] == 1)? 5'd5:5'd6; + 3 :NumCoeffTrailingOnes_len <= 5'd6; + 4 :NumCoeffTrailingOnes_len <= 5'd7; + 5 :NumCoeffTrailingOnes_len <= 5'd8; + 6 :NumCoeffTrailingOnes_len <= 5'd9; + 7 :NumCoeffTrailingOnes_len <= 5'd11; + 8 :NumCoeffTrailingOnes_len <= 5'd12; + 9 :NumCoeffTrailingOnes_len <= 5'd13; + 10:NumCoeffTrailingOnes_len <= (BitStream_buffer_output[4] == 1)? 5'd13:5'd14; + 11:NumCoeffTrailingOnes_len <= 5'd14; + 12:NumCoeffTrailingOnes_len <= 5'd13; + default:NumCoeffTrailingOnes_len <= 5'd0; + endcase + else if (nC_n1) + case (heading_one_pos) + 0:NumCoeffTrailingOnes_len <= 5'd1; + 1:NumCoeffTrailingOnes_len <= 5'd2; + 2:NumCoeffTrailingOnes_len <= 5'd3; + 3:NumCoeffTrailingOnes_len <= 5'd6; + 4:NumCoeffTrailingOnes_len <= 5'd6; + 5:NumCoeffTrailingOnes_len <= 5'd7; + 6:NumCoeffTrailingOnes_len <= 5'd8; + default:NumCoeffTrailingOnes_len <= 5'd7; + endcase + else if (nC_4to8) + case (heading_one_pos) + 0 :NumCoeffTrailingOnes_len <= 5'd4; + 1 :NumCoeffTrailingOnes_len <= 5'd5; + 2 :NumCoeffTrailingOnes_len <= 5'd6; + 3 :NumCoeffTrailingOnes_len <= 5'd7; + 4 :NumCoeffTrailingOnes_len <= 5'd8; + 5 :NumCoeffTrailingOnes_len <= 5'd9; + 6 :NumCoeffTrailingOnes_len <= (BitStream_buffer_output[8:7] == 2'b11)? 5'd9:5'd10; + 7 :NumCoeffTrailingOnes_len <= 5'd10; + 8 :NumCoeffTrailingOnes_len <= 5'd10; + 9 :NumCoeffTrailingOnes_len <= 5'd10; + 10:NumCoeffTrailingOnes_len <= 5'd10; + default:NumCoeffTrailingOnes_len <= 5'd0; + endcase + else if (nC_GE8) + NumCoeffTrailingOnes_len <= 5'd6; + else + NumCoeffTrailingOnes_len <= 0; + + + //TrailingOnes + always @ (posedge clk) + if (reset_n == 0) + TrailingOnes_reg <= 0; + else if (cavlc_decoder_state == `NumCoeffTrailingOnes_LUT) + TrailingOnes_reg <= TrailingOnes; + + always @ (nC_0to2 or nC_2to4 or nC_4to8 or nC_n1 or nC_GE8 + or nC_0to2_t0 or nC_0to2_t1 or nC_0to2_t2 or nC_0to2_t3 + or nC_2to4_t0 or nC_2to4_t1 or nC_2to4_t2 or nC_2to4_t3 + or nC_4to8_t0 or nC_4to8_t1 or nC_n1_t0 + or TrailingOnes_reg or heading_one_pos or BitStream_buffer_output) + if (nC_0to2) + begin + if (nC_0to2_t0) + TrailingOnes <= heading_one_pos[1:0]; + else if (nC_0to2_t1) + begin + if (heading_one_pos == 4'd3 && !BitStream_buffer_output[11]) + TrailingOnes <= (BitStream_buffer_output[10])? 2'd0:2'd1; + else if (heading_one_pos == 4'd4 && BitStream_buffer_output[10:9] == 2'b01) + TrailingOnes <= 2'd2; + else + TrailingOnes <= 2'd3; + end + else if (nC_0to2_t2) + begin + if (heading_one_pos == 4'd5) + case (BitStream_buffer_output[9:8]) + 2'b00:TrailingOnes <= 2'd3; + 2'b01:TrailingOnes <= 2'd2; + 2'b10:TrailingOnes <= 2'd1; + 2'b11:TrailingOnes <= 2'd0; + endcase + else if (heading_one_pos == 4'd6) + case (BitStream_buffer_output[8:7]) + 2'b00:TrailingOnes <= 2'd3; + 2'b01:TrailingOnes <= 2'd2; + 2'b10:TrailingOnes <= 2'd1; + 2'b11:TrailingOnes <= 2'd0; + endcase + else if (heading_one_pos == 4'd7) + case (BitStream_buffer_output[7:6]) + 2'b00:TrailingOnes <= 2'd3; + 2'b01:TrailingOnes <= 2'd2; + 2'b10:TrailingOnes <= 2'd1; + 2'b11:TrailingOnes <= 2'd0; + endcase + else + case (BitStream_buffer_output[6:5]) + 2'b00:TrailingOnes <= 2'd3; + 2'b01:TrailingOnes <= 2'd2; + 2'b10:TrailingOnes <= 2'd1; + 2'b11:TrailingOnes <= 2'd0; + endcase + end + else if (nC_0to2_t3) + begin + if (heading_one_pos == 4'd9) + case (BitStream_buffer_output[4:3]) + 2'b00:TrailingOnes <= (BitStream_buffer_output[5])? 2'd3:2'd0; + 2'b10:TrailingOnes <= 2'd1; + 2'b01:TrailingOnes <= 2'd2; + 2'b11:TrailingOnes <= 2'd0; + endcase + else + case (BitStream_buffer_output[3:2]) + 2'b00:TrailingOnes <= 2'd3; + 2'b01:TrailingOnes <= 2'd2; + 2'b10:TrailingOnes <= 2'd1; + 2'b11:TrailingOnes <= 2'd0; + endcase + end + else + begin + if ((heading_one_pos == 4'd11 && BitStream_buffer_output[2:1] == 2'b11) || + (heading_one_pos == 4'd12 && BitStream_buffer_output[1:0] == 2'b11) || + (heading_one_pos == 4'd13 && (BitStream_buffer_output[1:0] == 2'b00 || BitStream_buffer_output[1:0] == 2'b11))) + TrailingOnes <= 2'd0; + else if ((heading_one_pos == 4'd11 && BitStream_buffer_output[2:1] == 2'b10) || + (heading_one_pos == 4'd12 && BitStream_buffer_output[1:0] == 2'b10) || + (heading_one_pos == 4'd13 && BitStream_buffer_output[1:0] == 2'b10) || + heading_one_pos == 4'd14) + TrailingOnes <= 2'd1; + else if ((heading_one_pos == 4'd11 && BitStream_buffer_output[2:1] == 2'b01) || + (heading_one_pos == 4'd12 && BitStream_buffer_output[1:0] == 2'b01) || + (heading_one_pos == 4'd13 && BitStream_buffer_output[1:0] == 2'b01)) + TrailingOnes <= 2'd2; + else + TrailingOnes <= 2'd3; + end + end + else if (nC_2to4) + begin + if (nC_2to4_t0) + begin + if (heading_one_pos == 4'd0) + TrailingOnes <= {1'b0,~BitStream_buffer_output[14]}; + else + TrailingOnes <= (BitStream_buffer_output[13])? 2'd2:2'd3; + end + else if (nC_2to4_t1) + begin + if ((heading_one_pos == 4'd2 && BitStream_buffer_output[12:10] == 3'b011) || + (heading_one_pos == 4'd3 && BitStream_buffer_output[11:10] == 2'b11)) + TrailingOnes <= 2'd0; + else if ((heading_one_pos == 4'd2 && (BitStream_buffer_output[12:11] == 2'b11 || BitStream_buffer_output[12:10] == 3'b010)) || + (heading_one_pos == 4'd3 && BitStream_buffer_output[11:10] == 2'b10)) + TrailingOnes <= 2'd1; + else if ((heading_one_pos == 4'd2 && BitStream_buffer_output[12:10] == 3'b001) || + (heading_one_pos == 4'd3 && BitStream_buffer_output[11:10] == 2'b01)) + TrailingOnes <= 2'd2; + else + TrailingOnes <= 2'd3; + end + else if (nC_2to4_t2) + begin + if (heading_one_pos == 4'd4) + case (BitStream_buffer_output[10:9]) + 2'b00:TrailingOnes <= 2'd3; + 2'b01:TrailingOnes <= 2'd2; + 2'b10:TrailingOnes <= 2'd1; + 2'b11:TrailingOnes <= 2'd0; + endcase + else if (heading_one_pos == 4'd5) + case (BitStream_buffer_output[9:8]) + 2'b00:TrailingOnes <= 2'd0; + 2'b01:TrailingOnes <= 2'd2; + 2'b10:TrailingOnes <= 2'd1; + 2'b11:TrailingOnes <= 2'd0; + endcase + else + case (BitStream_buffer_output[8:7]) + 2'b00:TrailingOnes <= 2'd3; + 2'b01:TrailingOnes <= 2'd2; + 2'b10:TrailingOnes <= 2'd1; + 2'b11:TrailingOnes <= 2'd0; + endcase + end + else if (nC_2to4_t3) + begin + if ((heading_one_pos == 4'd7 && BitStream_buffer_output[6:5] == 2'b11) || + (heading_one_pos == 4'd8 && (BitStream_buffer_output[5:4] == 2'b11 || BitStream_buffer_output[6:4] == 3'b000))) + TrailingOnes <= 2'd0; + else if ((heading_one_pos == 4'd7 && BitStream_buffer_output[6:5] == 2'b10) || + (heading_one_pos == 4'd8 && BitStream_buffer_output[5:4] == 2'b10)) + TrailingOnes <= 2'd1; + else if ((heading_one_pos == 4'd7 && BitStream_buffer_output[6:5] == 2'b01) || + (heading_one_pos == 4'd8 && BitStream_buffer_output[5:4] == 2'b01)) + TrailingOnes <= 2'd2; + else + TrailingOnes <= 2'd3; + end + else + begin + if ((heading_one_pos == 4'd9 && BitStream_buffer_output[4:3] == 2'b11) || + (heading_one_pos == 4'd10 && (BitStream_buffer_output[4:3] == 2'b11 || BitStream_buffer_output[4:2] == 3'b001)) || + (heading_one_pos == 4'd11 && BitStream_buffer_output[3:2] == 2'b11)) + TrailingOnes <= 2'd0; + else if ((heading_one_pos == 4'd9 && BitStream_buffer_output[4:3] == 2'b10) || + (heading_one_pos == 4'd10 && (BitStream_buffer_output[4:2] == 3'b000 || BitStream_buffer_output[4:2] == 3'b011)) || + (heading_one_pos == 4'd11 && BitStream_buffer_output[3:2] == 2'b10)) + TrailingOnes <= 2'd1; + else if ((heading_one_pos == 4'd9 && BitStream_buffer_output[4:3] == 2'b01) || + (heading_one_pos == 4'd10 && (BitStream_buffer_output[4:3] == 2'b10 || BitStream_buffer_output[4:2] == 3'b010)) || + (heading_one_pos == 4'd11 && BitStream_buffer_output[3:2] == 2'b01)) + TrailingOnes <= 2'd2; + else + TrailingOnes <= 2'd3; + end + end + else if (nC_n1) + begin + if (nC_n1_t0) + begin + if (BitStream_buffer_output[15]) TrailingOnes <= 2'd1; + else if (BitStream_buffer_output[14]) TrailingOnes <= 2'd0; + else TrailingOnes <= 2'd2; + end + else + begin + if ((heading_one_pos == 4'd3 && (BitStream_buffer_output[11:10] == 2'b00 || BitStream_buffer_output[11:10] == 2'b11)) || + heading_one_pos == 4'd4) + TrailingOnes <= 2'd0; + else if ((heading_one_pos == 4'd3 && BitStream_buffer_output[11:10] == 2'b10) || + (heading_one_pos == 4'd5 && BitStream_buffer_output[9]) || + (heading_one_pos == 4'd6 && BitStream_buffer_output[8])) + TrailingOnes <= 2'd1; + else if ((heading_one_pos == 4'd5 && !BitStream_buffer_output[9]) || + (heading_one_pos == 4'd6 && !BitStream_buffer_output[8])) + TrailingOnes <= 2'd2; + else + TrailingOnes <= 2'd3; + end + end + else if (nC_4to8) + begin + if (nC_4to8_t0) + begin + if (BitStream_buffer_output[14:12] == 3'b111) TrailingOnes <= 2'd0; + else if (BitStream_buffer_output[14:12] == 3'b110) TrailingOnes <= 2'd1; + else if (BitStream_buffer_output[14:12] == 3'b101) TrailingOnes <= 2'd2; + else TrailingOnes <= 2'd3; + end + else if (nC_4to8_t1) + begin + if ((heading_one_pos == 4'd1 && + (BitStream_buffer_output[13:11] == 3'b000 || BitStream_buffer_output[13:11] == 3'b010 || + BitStream_buffer_output[13:11] == 3'b100 || BitStream_buffer_output[13:11] == 3'b111)) || + (heading_one_pos == 4'd2 && BitStream_buffer_output[11:10] == 2'b10 ) || + (heading_one_pos == 4'd3 && BitStream_buffer_output[11:9] == 3'b110) || + (heading_one_pos == 4'd4 && BitStream_buffer_output[9:8] == 2'b10 )) + TrailingOnes <= 2'd1; + else if ( + (heading_one_pos == 4'd1 && (BitStream_buffer_output[13:11] == 3'b001 || BitStream_buffer_output[13:11] == 3'b011 || BitStream_buffer_output[13:11] == 3'b110))|| + (heading_one_pos == 4'd2 && BitStream_buffer_output[11:10] == 2'b01) || + (heading_one_pos == 4'd3 && (BitStream_buffer_output[11:9] == 3'b010 || BitStream_buffer_output[11:9] == 3'b101))|| + (heading_one_pos == 4'd4 && BitStream_buffer_output[9:8] == 2'b01)) + TrailingOnes <= 2'd2; + else if ( + (heading_one_pos == 4'd1 && BitStream_buffer_output[13:11] == 3'b101) || + (heading_one_pos == 4'd2 && BitStream_buffer_output[12:10] == 3'b100) || + (heading_one_pos == 4'd3 && BitStream_buffer_output[11:9] == 3'b100) || + (heading_one_pos == 4'd4 && BitStream_buffer_output[9:8] == 2'b00)) + TrailingOnes <= 2'd3; + else + TrailingOnes <= 2'd0; + end + else + begin + if ((heading_one_pos == 4'd5 && BitStream_buffer_output[8:7] == 2'b10) || + (heading_one_pos == 4'd6 && (BitStream_buffer_output[8:7] == 2'b11 || BitStream_buffer_output[7:6] == 2'b00)) || + (heading_one_pos == 4'd7 && BitStream_buffer_output[7:6] == 2'b00)) + TrailingOnes <= 2'd1; + else if ( + (heading_one_pos == 4'd5 && BitStream_buffer_output[8:7] == 2'b01) || + (heading_one_pos == 4'd6 && BitStream_buffer_output[8:6] == 3'b011) || + (heading_one_pos == 4'd7 && BitStream_buffer_output[7:6] == 2'b11) || + (heading_one_pos == 4'd8 && BitStream_buffer_output[6])) + TrailingOnes <= 2'd2; + else if ( + (heading_one_pos == 4'd5 && BitStream_buffer_output[9:7] == 3'b100) || + (heading_one_pos == 4'd6 && BitStream_buffer_output[8:6] == 3'b010) || + (heading_one_pos == 4'd7 && BitStream_buffer_output[7:6] == 2'b10) || + (heading_one_pos == 4'd8 && !BitStream_buffer_output[6])) + TrailingOnes <= 2'd3; + else + TrailingOnes <= 2'd0; + end + end + else if (nC_GE8) + begin + if (BitStream_buffer_output[15:10] == 6'b0 || heading_one_pos == 4'd4) + TrailingOnes <= 2'd0; + else if (heading_one_pos == 4'd5) + TrailingOnes <= 2'd1; + else + TrailingOnes <= BitStream_buffer_output[11:10]; + end + else + TrailingOnes <= TrailingOnes_reg; + + //TotalCoeff + always @ (posedge clk) + if (reset_n == 0) + TotalCoeff_reg <= 0; + else if (cavlc_decoder_state == `NumCoeffTrailingOnes_LUT) + TotalCoeff_reg <= TotalCoeff; + + always @ (nC_0to2 or nC_2to4 or nC_4to8 or nC_n1 or nC_GE8 + or nC_0to2_t0 or nC_0to2_t1 or nC_0to2_t2 or nC_0to2_t3 + or nC_2to4_t0 or nC_2to4_t1 or nC_2to4_t2 or nC_2to4_t3 + or nC_4to8_t0 or nC_4to8_t1 or nC_n1_t0 + or TotalCoeff_reg or heading_one_pos or BitStream_buffer_output) + if (nC_0to2) + begin + if (nC_0to2_t0) + TotalCoeff <= {3'b0,heading_one_pos[1:0]}; + else if (nC_0to2_t1) + begin + if (heading_one_pos == 4'd3) + case (BitStream_buffer_output[11:10]) + 2'b00 :TotalCoeff <= 5'd2; + 2'b01 :TotalCoeff <= 5'd1; + default:TotalCoeff <= 5'd3; + endcase + else + case (BitStream_buffer_output[10:9]) + 2'b00 :TotalCoeff <= 5'd5; + 2'b01 :TotalCoeff <= 5'd3; + default:TotalCoeff <= 5'd4; + endcase + end + else if (nC_0to2_t2) + begin + if (heading_one_pos == 4'd5) + case (BitStream_buffer_output[9:8]) + 2'b00:TotalCoeff <= 5'd6; + 2'b01:TotalCoeff <= 5'd4; + 2'b10:TotalCoeff <= 5'd3; + 2'b11:TotalCoeff <= 5'd2; + endcase + else if (heading_one_pos == 4'd6) + case (BitStream_buffer_output[8:7]) + 2'b00:TotalCoeff <= 5'd7; + 2'b01:TotalCoeff <= 5'd5; + 2'b10:TotalCoeff <= 5'd4; + 2'b11:TotalCoeff <= 5'd3; + endcase + else if (heading_one_pos == 4'd7) + case (BitStream_buffer_output[7:6]) + 2'b00:TotalCoeff <= 5'd8; + 2'b01:TotalCoeff <= 5'd6; + 2'b10:TotalCoeff <= 5'd5; + 2'b11:TotalCoeff <= 5'd4; + endcase + else + case (BitStream_buffer_output[6:5]) + 2'b00:TotalCoeff <= 5'd9; + 2'b01:TotalCoeff <= 5'd7; + 2'b10:TotalCoeff <= 5'd6; + 2'b11:TotalCoeff <= 5'd5; + endcase + end + else if (nC_0to2_t3) + begin + if (heading_one_pos == 4'd9) + case (BitStream_buffer_output[5:3]) + 3'b001 :TotalCoeff <= 5'd9; + 3'b011,3'b110:TotalCoeff <= 5'd7; + 3'b100 :TotalCoeff <= 5'd10; + 3'b111 :TotalCoeff <= 5'd6; + default :TotalCoeff <= 5'd8; + endcase + else + case (BitStream_buffer_output[4:2]) + 3'b000 :TotalCoeff <= 5'd12; + 3'b001,3'b100:TotalCoeff <= 5'd11; + 3'b110,3'b111:TotalCoeff <= 5'd9; + default :TotalCoeff <= 5'd10; + endcase + end + else + begin + if (heading_one_pos == 4'd11) + case (BitStream_buffer_output[3:1]) + 3'b000 :TotalCoeff <= 5'd14; + 3'b001,3'b100:TotalCoeff <= 5'd13; + 3'b110,3'b111:TotalCoeff <= 5'd11; + default :TotalCoeff <= 5'd12; + endcase + else if (heading_one_pos == 4'd12) + case (BitStream_buffer_output[2:0]) + 3'b000 :TotalCoeff <= 5'd16; + 3'b011,3'b101,3'b110:TotalCoeff <= 5'd14; + 3'b111 :TotalCoeff <= 5'd13; + default :TotalCoeff <= 5'd15; + endcase + else if (heading_one_pos == 4'd13) + TotalCoeff <= (BitStream_buffer_output[1:0] == 2'b11)? 5'd15:5'd16; + else + TotalCoeff <= 5'd13; + end + end + else if (nC_2to4) + begin + if (nC_2to4_t0) + begin + if (heading_one_pos == 4'd0) + TotalCoeff <= {4'b0,~BitStream_buffer_output[14]}; + else + case (BitStream_buffer_output[13:12]) + 2'b00 :TotalCoeff <= 5'd4; + 2'b01 :TotalCoeff <= 5'd3; + default:TotalCoeff <= 5'd2; + endcase + end + else if (nC_2to4_t1) + begin + if (heading_one_pos == 4'd2) + case (BitStream_buffer_output[12:11]) + 2'b00:TotalCoeff <= (BitStream_buffer_output[10])? 5'd3:5'd6; + 2'b01:TotalCoeff <= (BitStream_buffer_output[10])? 5'd1:5'd3; + 2'b10:TotalCoeff <= 5'd5; + 2'b11:TotalCoeff <= 5'd2; + endcase + else + case (BitStream_buffer_output[11:10]) + 2'b00 :TotalCoeff <= 5'd7; + 2'b11 :TotalCoeff <= 5'd2; + default:TotalCoeff <= 5'd4; + endcase + end + else if (nC_2to4_t2) + begin + if (heading_one_pos == 4'd4) + case (BitStream_buffer_output[10:9]) + 2'b00 :TotalCoeff <= 5'd8; + 2'b11 :TotalCoeff <= 5'd3; + default:TotalCoeff <= 5'd5; + endcase + else if (heading_one_pos == 4'd5) + case (BitStream_buffer_output[9:8]) + 2'b00 :TotalCoeff <= 5'd5; + 2'b11 :TotalCoeff <= 5'd4; + default:TotalCoeff <= 5'd6; + endcase + else + case (BitStream_buffer_output[8:7]) + 2'b00 :TotalCoeff <= 5'd9; + 2'b11 :TotalCoeff <= 5'd6; + default:TotalCoeff <= 5'd7; + endcase + end + else if (nC_2to4_t3) + begin + if (heading_one_pos == 4'd7) + case (BitStream_buffer_output[7:5]) + 3'b000 :TotalCoeff <= 5'd11; + 3'b001,3'b010:TotalCoeff <= 5'd9; + 3'b100 :TotalCoeff <= 5'd10; + 3'b111 :TotalCoeff <= 5'd7; + default :TotalCoeff <= 5'd8; + endcase + else + case (BitStream_buffer_output[6:4]) + 3'b000,3'b001,3'b010:TotalCoeff <= 5'd11; + 3'b100 :TotalCoeff <= 5'd12; + 3'b111 :TotalCoeff <= 5'd9; + default :TotalCoeff <= 5'd10; + endcase + end + else + begin + if (heading_one_pos == 4'd9) + case (BitStream_buffer_output[5:3]) + 3'b000 :TotalCoeff <= 5'd14; + 3'b101,3'b110,3'b111:TotalCoeff <= 5'd12; + default :TotalCoeff <= 5'd13; + endcase + else if (heading_one_pos == 4'd10) + TotalCoeff <= (BitStream_buffer_output[4:2] == 3'b0 || BitStream_buffer_output[4:2] == 3'b001 || BitStream_buffer_output[4:2] == 3'b010)? 5'd15:5'd14; + else if (heading_one_pos == 4'd11) + TotalCoeff <= 5'd16; + else + TotalCoeff <= 5'd15; + end + end + else if (nC_n1) + begin + if (nC_n1_t0) + begin + if (BitStream_buffer_output[15]) TotalCoeff <= 5'd1; + else if (BitStream_buffer_output[14]) TotalCoeff <= 5'd0; + else TotalCoeff <= 5'd2; + end + else + begin + if (heading_one_pos == 4'd3) + case (BitStream_buffer_output[11:10]) + 2'b01 :TotalCoeff <= 5'd3; + 2'b11 :TotalCoeff <= 5'd1; + default:TotalCoeff <= 5'd2; + endcase + else if (heading_one_pos == 4'd4) + TotalCoeff <= (BitStream_buffer_output[10])? 5'd3:5'd4; + else if (heading_one_pos == 4'd5) + TotalCoeff <= 5'd3; + else + TotalCoeff <= 5'd4; + end + end + else if (nC_4to8) + begin + if (nC_4to8_t0) + TotalCoeff <= {2'b0,~BitStream_buffer_output[14:12]}; + else if (nC_4to8_t1) + begin + if (heading_one_pos == 4'd1) + case (BitStream_buffer_output[13:11]) + 3'b000,3'b001:TotalCoeff <= 5'd5; + 3'b010,3'b011:TotalCoeff <= 5'd4; + 3'b101 :TotalCoeff <= 5'd8; + 3'b111 :TotalCoeff <= 5'd2; + default :TotalCoeff <= 5'd3; + endcase + else if (heading_one_pos == 4'd2) + case (BitStream_buffer_output[12:10]) + 3'b000 :TotalCoeff <= 5'd3; + 3'b001,3'b010:TotalCoeff <= 5'd7; + 3'b011 :TotalCoeff <= 5'd2; + 3'b100 :TotalCoeff <= 5'd9; + 3'b111 :TotalCoeff <= 5'd1; + default :TotalCoeff <= 5'd6; + endcase + else if (heading_one_pos == 4'd3) + case (BitStream_buffer_output[11:9]) + 3'b000 :TotalCoeff <= 5'd7; + 3'b001 :TotalCoeff <= 5'd6; + 3'b010 :TotalCoeff <= 5'd9; + 3'b011 :TotalCoeff <= 5'd5; + 3'b100 :TotalCoeff <= 5'd10; + 3'b111 :TotalCoeff <= 5'd4; + default:TotalCoeff <= 5'd8; + endcase + else + case (BitStream_buffer_output[10:8]) + 3'b000 :TotalCoeff <= 5'd12; + 3'b001,3'b100:TotalCoeff <= 5'd11; + 3'b010,3'b101:TotalCoeff <= 5'd10; + 3'b111 :TotalCoeff <= 5'd8; + default :TotalCoeff <= 5'd9; + endcase + end + else + begin + if (heading_one_pos == 4'd5) + case (BitStream_buffer_output[9:7]) + 3'b001,3'b100 :TotalCoeff <= 5'd13; + 3'b011,3'b110 :TotalCoeff <= 5'd11; + 3'b111 :TotalCoeff <= 5'd10; + default :TotalCoeff <= 5'd12; + endcase + else if (heading_one_pos == 4'd6) + case (BitStream_buffer_output[8:6]) + 3'b000 :TotalCoeff <= 5'd15; + 3'b101,3'b110,3'b111:TotalCoeff <= 5'd13; + default :TotalCoeff <= 5'd14; + endcase + else if (heading_one_pos == 4'd7) + TotalCoeff <= (BitStream_buffer_output[7:6] == 2'b00)? 5'd16:5'd15; + else + TotalCoeff <= 5'd16; + end + end + else if (nC_GE8) + begin + if (heading_one_pos == 4'd4) + TotalCoeff <= 5'd0; + else + TotalCoeff <= BitStream_buffer_output[15:12] + 1; + end + else + TotalCoeff <= TotalCoeff_reg; +endmodule \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/QP_decoding.v b/demo_chip_rtl/rtl/nova/trunk/src/QP_decoding.v new file mode 100644 index 0000000..64354ff --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/QP_decoding.v @@ -0,0 +1,70 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : QP_decoding.v +// Generated : June 7, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// QPy:the luma quantisation parameter +// QPi:the intermediate quantisation parameter derived from QPy +// QPc:the chroma quantisation parameter derived from QPi on Table 8-13,Page136 +//------------------------------------------------------------------------------------------------- +// Revise log +// 1. March 21,2006 +// Input signals slice_qp_delta and mb_qp_delta are removed, using +// exp_golomb_decoding_output_5to0 instead since these two signals are latched at clock +// rising edge which is too late for computation. So use exp_golomb_decoding_output_5to0 directly +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module QP_decoding (clk,reset_n,slice_header_state,slice_data_state,pic_init_qp_minus26, + exp_golomb_decoding_output_5to0,chroma_qp_index_offset,QPy,QPc); + input clk,reset_n; + input [3:0] slice_header_state; + input [3:0] slice_data_state; + input [5:0] pic_init_qp_minus26; + input [5:0] exp_golomb_decoding_output_5to0; + input [4:0] chroma_qp_index_offset; + output [5:0] QPy,QPc; + reg [5:0] QPy,QPc; + + always @ (posedge clk) + if (reset_n == 0) + QPy <= 0; + else if (slice_header_state == `slice_qp_delta_s) + QPy <= 26 + pic_init_qp_minus26 + exp_golomb_decoding_output_5to0; + else if (slice_data_state == `mb_qp_delta_s) + QPy <= QPy + exp_golomb_decoding_output_5to0; + + wire [5:0] QPi; + assign QPi = QPy + {1'b0,chroma_qp_index_offset}; + always @ (posedge clk) + if (reset_n == 0) + QPc <= 0; + else + begin + if (QPi < 30) + QPc <= QPi; + else + case (QPi) + 30 :QPc <= 29; + 31 :QPc <= 30; + 32 :QPc <= 31; + 33,34 :QPc <= 32; + 35 :QPc <= 33; + 36,37 :QPc <= 34; + 38,39 :QPc <= 35; + 40,41 :QPc <= 36; + 42,43,44:QPc <= 37; + 45,46,47:QPc <= 38; + default :QPc <= 39; + endcase + end +endmodule + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/bitstream_gclk_gen.v b/demo_chip_rtl/rtl/nova/trunk/src/bitstream_gclk_gen.v new file mode 100644 index 0000000..cbf8e35 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/bitstream_gclk_gen.v @@ -0,0 +1,333 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : bitstream_gclk_gen.v +// Generated : Jan 9,2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Gated clock generation module for bitstream controller +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module bitstream_gclk_gen (clk,reset_n,freq_ctrl0,freq_ctrl1,parser_state,nal_unit_state,slice_layer_wo_partitioning_state, + slice_header_state,slice_data_state,seq_parameter_set_state,pic_parameter_set_state,residual_state,cavlc_decoder_state, + mb_num,TotalCoeff,start_code_prefix_found,pc_2to0,deblocking_filter_control_present_flag, + disable_deblocking_filter_idc,end_of_one_residual_block, + Intra4x4PredMode_mbAddrB_cs_n,mvx_mbAddrB_cs_n,mvy_mbAddrB_cs_n,mvx_mbAddrC_cs_n,mvy_mbAddrC_cs_n, + LumaLevel_mbAddrB_cs_n,ChromaLevel_Cb_mbAddrB_cs_n,ChromaLevel_Cr_mbAddrB_cs_n, + trigger_CAVLC,blk4x4_rec_counter,end_of_DCBlk_IQIT,end_of_one_blk4x4_sum,end_of_MB_DEC,disable_DF,bs_dec_counter, + + gclk_parser,gclk_nal,gclk_slice,gclk_sps,gclk_pps, + gclk_slice_header,gclk_slice_data,gclk_residual,gclk_cavlc, + gclk_Intra4x4PredMode_mbAddrB_RF, + gclk_mvx_mbAddrB_RF,gclk_mvy_mbAddrB_RF,gclk_mvx_mbAddrC_RF,gclk_mvy_mbAddrC_RF, + gclk_LumaLevel_mbAddrB_RF,gclk_ChromaLevel_Cb_mbAddrB_RF,gclk_ChromaLevel_Cr_mbAddrB_RF,gclk_bs_dec, + end_of_one_frame); + input clk; + input reset_n; + input freq_ctrl0; + input freq_ctrl1; + input [1:0] parser_state; + input [2:0] nal_unit_state; + input [1:0] slice_layer_wo_partitioning_state; + input [3:0] slice_header_state; + input [3:0] slice_data_state; + input [3:0] seq_parameter_set_state; + input [3:0] pic_parameter_set_state; + input [3:0] residual_state; + input [3:0] cavlc_decoder_state; + input [6:0] mb_num; + input [4:0] TotalCoeff; + input start_code_prefix_found; + input [2:0] pc_2to0; + input deblocking_filter_control_present_flag; + input [1:0] disable_deblocking_filter_idc; + input end_of_one_residual_block; + input Intra4x4PredMode_mbAddrB_cs_n; + input mvx_mbAddrB_cs_n; + input mvy_mbAddrB_cs_n; + input mvx_mbAddrC_cs_n; + input mvy_mbAddrC_cs_n; + input LumaLevel_mbAddrB_cs_n; + input ChromaLevel_Cb_mbAddrB_cs_n; + input ChromaLevel_Cr_mbAddrB_cs_n; + input trigger_CAVLC; + input [4:0] blk4x4_rec_counter; + input end_of_DCBlk_IQIT; + input end_of_one_blk4x4_sum; + input end_of_MB_DEC; + input disable_DF; + input [1:0] bs_dec_counter; + + output gclk_parser; + output gclk_nal; + output gclk_slice; + output gclk_sps; + output gclk_pps; + output gclk_slice_header; + output gclk_slice_data; + output gclk_residual; + output gclk_cavlc; + output gclk_Intra4x4PredMode_mbAddrB_RF; + output gclk_mvx_mbAddrB_RF; + output gclk_mvy_mbAddrB_RF; + output gclk_mvx_mbAddrC_RF; + output gclk_mvy_mbAddrC_RF; + output gclk_LumaLevel_mbAddrB_RF; + output gclk_ChromaLevel_Cb_mbAddrB_RF; + output gclk_ChromaLevel_Cr_mbAddrB_RF; + output gclk_bs_dec; + output end_of_one_frame; + + //Input pin freq_ctrl0 & freq_ctrl1 can be used to adjust frequency after the chip is fabricated + reg [16:0] cycles_per_frame; + always @ (freq_ctrl0 or freq_ctrl1) + case ({freq_ctrl1,freq_ctrl0}) + 2'b00:cycles_per_frame <= `cycles_per_frame0; + 2'b01:cycles_per_frame <= `cycles_per_frame1; + 2'b11:cycles_per_frame <= `cycles_per_frame3; + default:cycles_per_frame <= `cycles_per_frame2; + endcase + + //--------------------------------------------------------------------------------- + // decoding rate control + //--------------------------------------------------------------------------------- + reg [16:0] frame_cycle_counter; + reg end_of_one_frame; + always @ (posedge clk) + if (reset_n == 1'b0) + begin + frame_cycle_counter <= 0; + end_of_one_frame <= 1'b0; + end + else if (parser_state == `start_code_prefix) + begin + frame_cycle_counter <= 0; + end_of_one_frame <= 1'b0; + end + else if (frame_cycle_counter < cycles_per_frame) + begin + frame_cycle_counter <= frame_cycle_counter + 1; + end_of_one_frame <= 1'b0; + end + else + begin + frame_cycle_counter <= 0; + end_of_one_frame <= 1'b1; + end + //PPS and SPS doesn't need rate control,so after PPS/SPS decoding,bitstream parser should continue + //without waiting for "end_of_one_frame" signal when parser_state == rst_parser. + //PPS_SPS_complete is used to identify whether next nal_unit to be decoded is PPS/SPS or normal frame + reg PPS_SPS_complete; + always @ (posedge gclk_slice or negedge reset_n) + if (reset_n == 1'b0) + PPS_SPS_complete <= 1'b0; + else if (slice_layer_wo_partitioning_state == `slice_header) + PPS_SPS_complete <= 1'b1; + + //1.gclk_parser + wire parser_ena; + reg l_parser_ena; + wire gclk_parser; + assign parser_ena = ( + (parser_state == `rst_parser && (!PPS_SPS_complete || (PPS_SPS_complete && end_of_one_frame))) || + (parser_state == `start_code_prefix && start_code_prefix_found == 1'b1) || + (nal_unit_state == `rbsp_trailing_one_bit && pc_2to0 == 3'b000) || + nal_unit_state == `rbsp_trailing_zero_bits)? 1'b1:1'b0; + always @ (clk or parser_ena) + if (!clk) l_parser_ena <= parser_ena; + assign gclk_parser = l_parser_ena & clk; + + //2.gclk_nal + //including rate control for end of one frame + wire nal_ena; + reg l_nal_ena; + wire gclk_nal; + assign nal_ena = (parser_state == `nal_unit && ( + nal_unit_state == `rst_nal_unit || + nal_unit_state == `forbidden_zero_bit_2_nal_unit_type || + (((slice_data_state == `skip_run_duration && end_of_MB_DEC)|| slice_data_state == `mb_num_update) + && mb_num == 98) || + seq_parameter_set_state == `vui_parameter_present_flag_s || + pic_parameter_set_state == `deblocking_filter_control_2_redundant_pic_cnt_present_flag || + nal_unit_state == `rbsp_trailing_one_bit || + nal_unit_state == `rbsp_trailing_zero_bits))? 1'b1:1'b0; + always @ (clk or nal_ena) + if (!clk) l_nal_ena <= nal_ena; + assign gclk_nal = l_nal_ena & clk; + + //3.gclk_slice:for slice_layer_wo_partitioning_state FSM + wire slice_ena; + reg l_slice_ena; + wire gclk_slice; + assign slice_ena = ( + (nal_unit_state == `slice_layer_non_IDR_rbsp || nal_unit_state == `slice_layer_IDR_rbsp) && + (slice_layer_wo_partitioning_state == `rst_slice_layer_wo_partitioning || + (slice_header_state == `slice_qp_delta_s && deblocking_filter_control_present_flag == 1'b0) || + (slice_header_state == `disable_deblocking_filter_idc_s && disable_deblocking_filter_idc == 2'b01) || + slice_header_state == `slice_beta_offset_div2_s || + (((slice_data_state == `skip_run_duration && end_of_MB_DEC) || slice_data_state == `mb_num_update) + && mb_num == 98)))? 1'b1:1'b0; + always @ (clk or slice_ena) + if (!clk) l_slice_ena <= slice_ena; + assign gclk_slice = l_slice_ena & clk; + + //4.gclk_sps + wire sps_ena; + reg l_sps_ena; + wire gclk_sps; + assign sps_ena = (nal_unit_state == `seq_parameter_set_rbsp)? 1'b1:1'b0; + always @ (clk or sps_ena) + if (!clk) l_sps_ena <= sps_ena; + assign gclk_sps = l_sps_ena & clk; + + //5.gclk_pps + wire pps_ena; + reg l_pps_ena; + wire gclk_pps; + + assign pps_ena = (nal_unit_state == `pic_parameter_set_rbsp)? 1'b1:1'b0; + always @ (clk or pps_ena) + if (!clk) l_pps_ena <= pps_ena; + assign gclk_pps = l_pps_ena & clk; + + //6.gclk_slice_header + wire slice_header_ena; + reg l_slice_header_ena; + wire gclk_slice_header; + assign slice_header_ena = (slice_layer_wo_partitioning_state == `slice_header)? 1'b1:1'b0; + always @ (clk or slice_header_ena) + if (!clk) l_slice_header_ena <= slice_header_ena; + assign gclk_slice_header = l_slice_header_ena & clk; + + //7.gclk_slice_data + //including rate control for skipped macroblock:skip_run_duration + //including rate control for normal macroblock:mb_num_update + wire slice_data_ena; + reg l_slice_data_ena; + wire gclk_slice_data; + assign slice_data_ena = (slice_layer_wo_partitioning_state == `slice_data && ( + (slice_data_state != `skip_run_duration && slice_data_state != `residual) || + (slice_data_state == `skip_run_duration && end_of_MB_DEC == 1'b1) || + (slice_data_state == `residual && end_of_MB_DEC == 1'b1)))? 1'b1:1'b0; + always @ (clk or slice_data_ena) + if (!clk) l_slice_data_ena <= slice_data_ena; + assign gclk_slice_data = l_slice_data_ena & clk; + + //8.gclk_residual + wire residual_ena; + reg l_residual_ena; + wire gclk_residual; + + assign residual_ena = (slice_data_state == `residual && + (residual_state == `rst_residual || + + ((residual_state == `Intra16x16DCLevel_s || residual_state == `ChromaDCLevel_Cb_s + || residual_state == `ChromaDCLevel_Cr_s) && + ((end_of_one_residual_block == 1 && TotalCoeff == 0) || end_of_DCBlk_IQIT)) || + + ((residual_state == `Intra16x16ACLevel_s || residual_state == `Intra16x16ACLevel_0_s + || residual_state == `LumaLevel_s || residual_state == `LumaLevel_0_s) + && blk4x4_rec_counter == 15 && end_of_one_blk4x4_sum == 1) || + (residual_state == `ChromaACLevel_Cb_s && blk4x4_rec_counter == 19 && end_of_one_blk4x4_sum == 1) || + (residual_state == `ChromaACLevel_Cr_s && blk4x4_rec_counter == 23 && end_of_one_blk4x4_sum == 1) || + (residual_state == `ChromaACLevel_0_s && blk4x4_rec_counter == 23 && end_of_one_blk4x4_sum == 1)))? 1'b1:1'b0; + + always @ (clk or residual_ena) + if (!clk) l_residual_ena <= residual_ena; + assign gclk_residual = l_residual_ena & clk; + + //9.gclk_cavlc + wire cavlc_ena; + reg l_cavlc_ena; + wire gclk_cavlc; + assign cavlc_ena = (slice_data_state == `residual && (cavlc_decoder_state != `rst_cavlc_decoder || + (cavlc_decoder_state == `rst_cavlc_decoder && trigger_CAVLC)))? 1'b1:1'b0; + + always @ (clk or cavlc_ena) + if (!clk) l_cavlc_ena <= cavlc_ena; + assign gclk_cavlc = l_cavlc_ena & clk; + + //---------------------------------------------------------------------- + //gclk for bitstream controller register file + //---------------------------------------------------------------------- + //1.gclk_Intra4x4PredMode_mbAddrB_RF + reg l_Intra4x4PredMode_mbAddrB_RF_ena; + wire gclk_Intra4x4PredMode_mbAddrB_RF; + always @ (clk or Intra4x4PredMode_mbAddrB_cs_n) + if (!clk) l_Intra4x4PredMode_mbAddrB_RF_ena <= ~Intra4x4PredMode_mbAddrB_cs_n; + assign gclk_Intra4x4PredMode_mbAddrB_RF = clk & l_Intra4x4PredMode_mbAddrB_RF_ena; + + //2.gclk_mvx_mbAddrB_RF + reg l_mvx_mbAddrB_RF_ena; + wire gclk_mvx_mbAddrB_RF; + always @ (clk or mvx_mbAddrB_cs_n) + if (!clk) l_mvx_mbAddrB_RF_ena <= ~mvx_mbAddrB_cs_n; + assign gclk_mvx_mbAddrB_RF = clk & l_mvx_mbAddrB_RF_ena; + + //3.gclk_mvy_mbAddrB_RF + reg l_mvy_mbAddrB_RF_ena; + wire gclk_mvy_mbAddrB_RF; + always @ (clk or mvy_mbAddrB_cs_n) + if (!clk) l_mvy_mbAddrB_RF_ena <= ~mvy_mbAddrB_cs_n; + assign gclk_mvy_mbAddrB_RF = clk & l_mvy_mbAddrB_RF_ena; + + //4.gclk_mvx_mbAddrC_RF + reg l_mvx_mbAddrC_RF_ena; + wire gclk_mvx_mbAddrC_RF; + always @ (clk or mvx_mbAddrC_cs_n) + if (!clk) l_mvx_mbAddrC_RF_ena <= ~mvx_mbAddrC_cs_n; + assign gclk_mvx_mbAddrC_RF = clk & l_mvx_mbAddrC_RF_ena; + + //5.gclk_mvy_mbAddrC_RF + reg l_mvy_mbAddrC_RF_ena; + wire gclk_mvy_mbAddrC_RF; + always @ (clk or mvy_mbAddrC_cs_n) + if (!clk) l_mvy_mbAddrC_RF_ena <= ~mvy_mbAddrC_cs_n; + assign gclk_mvy_mbAddrC_RF = clk & l_mvy_mbAddrC_RF_ena; + //---------------------------------------------------------------------- + //gclk for CAVLC_decoder related regfiles + //---------------------------------------------------------------------- + //1.gclk_LumaLevel_mbAddrB_RF + reg l_LumaLevel_mbAddrB_RF_ena; + wire gclk_LumaLevel_mbAddrB_RF; + always @ (clk or LumaLevel_mbAddrB_cs_n) + if (!clk) l_LumaLevel_mbAddrB_RF_ena <= ~LumaLevel_mbAddrB_cs_n; + assign gclk_LumaLevel_mbAddrB_RF = clk & l_LumaLevel_mbAddrB_RF_ena; + + //2.gclk_ChromaLevel_Cb_mbAddrB_RF + reg l_ChromaLevel_Cb_mbAddrB_RF_ena; + wire gclk_ChromaLevel_Cb_mbAddrB_RF; + always @ (clk or ChromaLevel_Cb_mbAddrB_cs_n) + if (!clk) l_ChromaLevel_Cb_mbAddrB_RF_ena <= ~ChromaLevel_Cb_mbAddrB_cs_n; + assign gclk_ChromaLevel_Cb_mbAddrB_RF = clk & l_ChromaLevel_Cb_mbAddrB_RF_ena; + + //3.gclk_ChromaLevel_Cr_mbAddrB_RF + reg l_ChromaLevel_Cr_mbAddrB_RF_ena; + wire gclk_ChromaLevel_Cr_mbAddrB_RF; + always @ (clk or ChromaLevel_Cr_mbAddrB_cs_n) + if (!clk) l_ChromaLevel_Cr_mbAddrB_RF_ena <= ~ChromaLevel_Cr_mbAddrB_cs_n; + assign gclk_ChromaLevel_Cr_mbAddrB_RF = clk & l_ChromaLevel_Cr_mbAddrB_RF_ena; + + //---------------------------------------------------------------------- + //gclk for boundary strength decoding + //---------------------------------------------------------------------- + wire bs_dec_ena; + reg l_bs_dec_ena; + wire gclk_bs_dec; + + assign bs_dec_ena = ((end_of_MB_DEC == 1'b1 && disable_DF == 1'b0) || bs_dec_counter != 0)? 1'b1:1'b0; + always @ (clk or bs_dec_ena) + if (!clk) l_bs_dec_ena <= bs_dec_ena; + assign gclk_bs_dec = l_bs_dec_ena & clk; + +endmodule + + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/bs_decoding.v b/demo_chip_rtl/rtl/nova/trunk/src/bs_decoding.v new file mode 100644 index 0000000..68313c4 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/bs_decoding.v @@ -0,0 +1,906 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : bs_decoding.v +// Generated : Nov 17,2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Deblocking Filter Boundary Strength decoding +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module bs_decoding (clk,reset_n,gclk_bs_dec,gclk_end_of_MB_DEC,end_of_MB_DEC,end_of_one_blk4x4_sum,mb_num_h,mb_num_v, + disable_DF,blk4x4_rec_counter,CodedBlockPatternLuma,mb_type_general,slice_data_state,residual_state, + MBTypeGen_mbAddrA,MBTypeGen_mbAddrB_reg,end_of_one_residual_block,TotalCoeff, + curr_DC_IsZero,Is_skipMB_mv_calc, + mvx_mbAddrA,mvy_mbAddrA,mvx_mbAddrB_dout,mvy_mbAddrB_dout, + mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3,mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3, + + bs_dec_counter,end_of_BS_DEC,mv_mbAddrB_rd_for_DF, + bs_V0,bs_V1,bs_V2,bs_V3,bs_H0,bs_H1,bs_H2,bs_H3 + ); + input clk; + input reset_n; + input gclk_bs_dec; + input gclk_end_of_MB_DEC; + input end_of_MB_DEC; + input end_of_one_blk4x4_sum; + input [3:0] mb_num_h; + input [3:0] mb_num_v; + input [4:0] blk4x4_rec_counter; + input disable_DF; + input [3:0] CodedBlockPatternLuma; + input [3:0] mb_type_general; + input [3:0] slice_data_state; + input [3:0] residual_state; + input [1:0] MBTypeGen_mbAddrA; + input [21:0] MBTypeGen_mbAddrB_reg; + input end_of_one_residual_block; + input [4:0] TotalCoeff; + input curr_DC_IsZero; + input Is_skipMB_mv_calc; + input [31:0] mvx_mbAddrA,mvy_mbAddrA,mvx_mbAddrB_dout,mvy_mbAddrB_dout; + input [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3; + input [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3; + + output [1:0] bs_dec_counter; + output end_of_BS_DEC; + output mv_mbAddrB_rd_for_DF; + output [11:0] bs_V0,bs_V1,bs_V2,bs_V3,bs_H0,bs_H1,bs_H2,bs_H3; + + reg [11:0] bs_V0,bs_V1,bs_V2,bs_V3,bs_H0,bs_H1,bs_H2,bs_H3; + + //------------------------------------------- + //mb_type_general needs to be latched for DF + //------------------------------------------- + reg [3:0] mb_type_general_DF; + always @ (posedge clk) + if (reset_n == 1'b0) + mb_type_general_DF <= 4'b0; + else if (!disable_DF && end_of_one_blk4x4_sum && blk4x4_rec_counter == 5'd22) + mb_type_general_DF <= mb_type_general; + + reg [1:0] MB_inter_size; + always @ (mb_type_general_DF) + if (mb_type_general_DF[3] == 1'b0) + case (mb_type_general_DF[2:0]) + 3'b000,3'b101:MB_inter_size <= `I16x16; + 3'b001 :MB_inter_size <= `I16x8; + 3'b010 :MB_inter_size <= `I8x16; + default :MB_inter_size <= `I8x8; + endcase + else //Although it should be Intra,but we have no other choice + MB_inter_size <= `I8x8; + + reg [1:0] MBTypeGen_mbAddrB; + always @ (mb_num_h or MBTypeGen_mbAddrB_reg) + case (mb_num_h) + 0: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[1:0]; + 1: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[3:2]; + 2: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[5:4]; + 3: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[7:6]; + 4: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[9:8]; + 5: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[11:10]; + 6: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[13:12]; + 7: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[15:14]; + 8: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[17:16]; + 9: MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[19:18]; + 10:MBTypeGen_mbAddrB <= MBTypeGen_mbAddrB_reg[21:20]; + default:MBTypeGen_mbAddrB <= 0; + endcase + + reg [1:0] bs_dec_counter; + always @ (posedge gclk_bs_dec or negedge reset_n) + if (reset_n == 1'b0) + bs_dec_counter <= 0; + else + bs_dec_counter <= bs_dec_counter - 1; + + assign end_of_BS_DEC = (bs_dec_counter == 2'd1)? 1'b1:1'b0; + + wire mvx_V0_diff_GE4,mvx_V1_diff_GE4,mvx_V2_diff_GE4,mvx_V3_diff_GE4; + wire mvy_V0_diff_GE4,mvy_V1_diff_GE4,mvy_V2_diff_GE4,mvy_V3_diff_GE4; + wire mvx_H0_diff_GE4,mvx_H1_diff_GE4,mvx_H2_diff_GE4,mvx_H3_diff_GE4; + wire mvy_H0_diff_GE4,mvy_H1_diff_GE4,mvy_H2_diff_GE4,mvy_H3_diff_GE4; + + + //-------------------------------------------------------------------- + //If current MB is Inter,derive current MB non-zero coeff information + //No need to do this for P_skip or Intra.No need for chroma,either. + //-------------------------------------------------------------------- + reg [15:0] currMB_coeff;//whether each 4x4blk of current MB has at least one non-zero transform coeff + //currMB_coeff is organized in zig-zag order,according to blk4x4_rec_counter + //= 1'b1:this 4x4blk has at least one non-zero transform coeff + //= 1'b0:this 4x4blk has all 16 zero transform coeff + //only useful for Inter (excluding P_skip) MB + always @ (posedge clk) + if (reset_n == 1'b0) + currMB_coeff <= 16'd0; + else if (!disable_DF) + begin + //need to be reset evey MB + //Since only Inter MB needs currMB_coeff,we can use "coded_block_pattern_s" state as timing slot + if (slice_data_state == `coded_block_pattern_s) + currMB_coeff <= 16'd0; + else if (mb_type_general[3] == 1'b0 && mb_type_general[2:0] != 3'b101) //Inter but not P_skip + case (residual_state) + `Intra16x16ACLevel_s: + if (end_of_one_residual_block) + case (blk4x4_rec_counter[3:0]) + 4'd0 :currMB_coeff[0] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1; + 4'd1 :currMB_coeff[1] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1; + 4'd2 :currMB_coeff[2] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1; + 4'd3 :currMB_coeff[3] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1; + 4'd4 :currMB_coeff[4] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1; + 4'd5 :currMB_coeff[5] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1; + 4'd6 :currMB_coeff[6] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1; + 4'd7 :currMB_coeff[7] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1; + 4'd8 :currMB_coeff[8] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1; + 4'd9 :currMB_coeff[9] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1; + 4'd10:currMB_coeff[10] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1; + 4'd11:currMB_coeff[11] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1; + 4'd12:currMB_coeff[12] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1; + 4'd13:currMB_coeff[13] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1; + 4'd14:currMB_coeff[14] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1; + 4'd15:currMB_coeff[15] <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b0:1'b1; + endcase + `Intra16x16ACLevel_0_s: + case (blk4x4_rec_counter[3:0]) + 4'd0:currMB_coeff[0] <= ~curr_DC_IsZero; + 4'd1:currMB_coeff[1] <= ~curr_DC_IsZero; + 4'd2:currMB_coeff[2] <= ~curr_DC_IsZero; + 4'd3:currMB_coeff[3] <= ~curr_DC_IsZero; + 4'd4:currMB_coeff[4] <= ~curr_DC_IsZero; + 4'd5:currMB_coeff[5] <= ~curr_DC_IsZero; + 4'd6:currMB_coeff[6] <= ~curr_DC_IsZero; + 4'd7:currMB_coeff[7] <= ~curr_DC_IsZero; + 4'd8:currMB_coeff[8] <= ~curr_DC_IsZero; + 4'd9:currMB_coeff[9] <= ~curr_DC_IsZero; + 4'd10:currMB_coeff[10] <= ~curr_DC_IsZero; + 4'd11:currMB_coeff[11] <= ~curr_DC_IsZero; + 4'd12:currMB_coeff[12] <= ~curr_DC_IsZero; + 4'd13:currMB_coeff[13] <= ~curr_DC_IsZero; + 4'd14:currMB_coeff[14] <= ~curr_DC_IsZero; + 4'd15:currMB_coeff[15] <= ~curr_DC_IsZero; + endcase + `LumaLevel_s: + case (blk4x4_rec_counter[3:0]) + 4'd0 :if (CodedBlockPatternLuma[0] == 1'b0) currMB_coeff[0] <= 1'b0; + else if (end_of_one_residual_block) currMB_coeff[0] <= (TotalCoeff == 0)? 1'b0:1'b1; + 4'd1 :if (CodedBlockPatternLuma[0] == 1'b0) currMB_coeff[1] <= 1'b0; + else if (end_of_one_residual_block) currMB_coeff[1] <= (TotalCoeff == 0)? 1'b0:1'b1; + 4'd2 :if (CodedBlockPatternLuma[0] == 1'b0) currMB_coeff[2] <= 1'b0; + else if (end_of_one_residual_block) currMB_coeff[2] <= (TotalCoeff == 0)? 1'b0:1'b1; + 4'd3 :if (CodedBlockPatternLuma[0] == 1'b0) currMB_coeff[3] <= 1'b0; + else if (end_of_one_residual_block) currMB_coeff[3] <= (TotalCoeff == 0)? 1'b0:1'b1; + 4'd4 :if (CodedBlockPatternLuma[1] == 1'b0) currMB_coeff[4] <= 1'b0; + else if (end_of_one_residual_block) currMB_coeff[4] <= (TotalCoeff == 0)? 1'b0:1'b1; + 4'd5 :if (CodedBlockPatternLuma[1] == 1'b0) currMB_coeff[5] <= 1'b0; + else if (end_of_one_residual_block) currMB_coeff[5] <= (TotalCoeff == 0)? 1'b0:1'b1; + 4'd6 :if (CodedBlockPatternLuma[1] == 1'b0) currMB_coeff[6] <= 1'b0; + else if (end_of_one_residual_block) currMB_coeff[6] <= (TotalCoeff == 0)? 1'b0:1'b1; + 4'd7 :if (CodedBlockPatternLuma[1] == 1'b0) currMB_coeff[7] <= 1'b0; + else if (end_of_one_residual_block) currMB_coeff[7] <= (TotalCoeff == 0)? 1'b0:1'b1; + 4'd8 :if (CodedBlockPatternLuma[2] == 1'b0) currMB_coeff[8] <= 1'b0; + else if (end_of_one_residual_block) currMB_coeff[8] <= (TotalCoeff == 0)? 1'b0:1'b1; + 4'd9 :if (CodedBlockPatternLuma[2] == 1'b0) currMB_coeff[9] <= 1'b0; + else if (end_of_one_residual_block) currMB_coeff[9] <= (TotalCoeff == 0)? 1'b0:1'b1; + 4'd10:if (CodedBlockPatternLuma[2] == 1'b0) currMB_coeff[10] <= 1'b0; + else if (end_of_one_residual_block) currMB_coeff[10] <= (TotalCoeff == 0)? 1'b0:1'b1; + 4'd11:if (CodedBlockPatternLuma[2] == 1'b0) currMB_coeff[11] <= 1'b0; + else if (end_of_one_residual_block) currMB_coeff[11] <= (TotalCoeff == 0)? 1'b0:1'b1; + 4'd12:if (CodedBlockPatternLuma[3] == 1'b0) currMB_coeff[12] <= 1'b0; + else if (end_of_one_residual_block) currMB_coeff[12] <= (TotalCoeff == 0)? 1'b0:1'b1; + 4'd13:if (CodedBlockPatternLuma[3] == 1'b0) currMB_coeff[13] <= 1'b0; + else if (end_of_one_residual_block) currMB_coeff[13] <= (TotalCoeff == 0)? 1'b0:1'b1; + 4'd14:if (CodedBlockPatternLuma[3] == 1'b0) currMB_coeff[14] <= 1'b0; + else if (end_of_one_residual_block) currMB_coeff[14] <= (TotalCoeff == 0)? 1'b0:1'b1; + 4'd15:if (CodedBlockPatternLuma[3] == 1'b0) currMB_coeff[15] <= 1'b0; + else if (end_of_one_residual_block) currMB_coeff[15] <= (TotalCoeff == 0)? 1'b0:1'b1; + endcase + `LumaLevel_0_s:currMB_coeff <= 16'd0; + endcase + end + + //whether each 4x4blk of MB at mbAddrB has at least one non-zero transform coeff + reg [43:0] mbAddrB_coeff_reg; + always @ (posedge gclk_end_of_MB_DEC or negedge reset_n) + if (reset_n == 1'b0) + mbAddrB_coeff_reg <= 44'd0; + else if (!disable_DF && mb_type_general[3] == 1'b0 && mb_type_general[2:0] != 3'b101 && mb_num_v != 8) //Inter but not P_skip + case (mb_num_h) + 4'd0 :mbAddrB_coeff_reg[3:0] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]}; + 4'd1 :mbAddrB_coeff_reg[7:4] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]}; + 4'd2 :mbAddrB_coeff_reg[11:8] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]}; + 4'd3 :mbAddrB_coeff_reg[15:12] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]}; + 4'd4 :mbAddrB_coeff_reg[19:16] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]}; + 4'd5 :mbAddrB_coeff_reg[23:20] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]}; + 4'd6 :mbAddrB_coeff_reg[27:24] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]}; + 4'd7 :mbAddrB_coeff_reg[31:28] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]}; + 4'd8 :mbAddrB_coeff_reg[35:32] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]}; + 4'd9 :mbAddrB_coeff_reg[39:36] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]}; + 4'd10:mbAddrB_coeff_reg[43:40] <= {currMB_coeff[15],currMB_coeff[14],currMB_coeff[11],currMB_coeff[10]}; + endcase + //------------------------------------------------- + //backup mbAddrA coding information to derive bs_V0 + //------------------------------------------------- + reg [3:0] mbAddrA_coeff; + reg [31:0] mbAddrA_mvx; + reg [31:0] mbAddrA_mvy; + always @ (posedge clk) + if (reset_n == 1'b0) + begin + mbAddrA_coeff <= 4'b0; + mbAddrA_mvx <= 32'b0; + mbAddrA_mvy <= 32'b0; + end + else if (!disable_DF && mb_num_h != 0 && + ((mb_type_general == `MB_P_skip && Is_skipMB_mv_calc && MBTypeGen_mbAddrA[1] == 1'b0) //Current MB is P_skip + || (slice_data_state == `mb_type_s && mb_type_general[3] == 1'b0))) //Current MB is Inter + begin + mbAddrA_mvx <= mvx_mbAddrA; mbAddrA_mvy <= mvy_mbAddrA; + //if mbAddrA is Inter (not P_skip),back up non-zero residual coeff information + if (MBTypeGen_mbAddrA[0] == 1'b0) mbAddrA_coeff <= {currMB_coeff[15],currMB_coeff[13],currMB_coeff[7],currMB_coeff[5]}; + end + //------------------------------------------------- + //backup mbAddrB coding information to derive bs_H0 + //------------------------------------------------- + + //1)For P_skip,at "Is_skipMB_mv_calc", no matter DF is enabled or not,mvx_mbAddrB/mvy_mbAddrB should be read to + // derive current motion vector + //2)For Inter other than P_skip, mvx_mbAddrB/mvy_mbAddrB are read at mb_pred or sub_mb_pred state.So we add a new + // signal "mv_mbAddrB_rd_for_DF" at "slice_data_state == `mb_type_s" + assign mv_mbAddrB_rd_for_DF = (!disable_DF && slice_data_state == `mb_type_s && mb_type_general[3] == 1'b0 && mb_num_v != 0); + reg [3:0] mbAddrB_coeff; + reg [31:0] mbAddrB_mvx; + reg [31:0] mbAddrB_mvy; + always @ (posedge clk) + if (reset_n == 1'b0) + begin + mbAddrB_coeff <= 4'b0; + mbAddrB_mvx <= 32'b0; + mbAddrB_mvy <= 32'b0; + end + else if (!disable_DF && mb_num_v != 0 && + ((mb_type_general == `MB_P_skip && Is_skipMB_mv_calc && MBTypeGen_mbAddrB[1] == 1'b0) //Current MB is P_skip + || (slice_data_state == `mb_type_s && mb_type_general[3] == 1'b0))) //Current MB is Inter + begin + mbAddrB_mvx <= mvx_mbAddrB_dout; mbAddrB_mvy <= mvy_mbAddrB_dout; + //if mbAddrB is Inter (not P_skip),back up non-zero residual coeff information + if (MBTypeGen_mbAddrB[0] == 1'b0) + case (mb_num_h) + 4'd0 :mbAddrB_coeff <= mbAddrB_coeff_reg[3:0]; + 4'd1 :mbAddrB_coeff <= mbAddrB_coeff_reg[7:4]; + 4'd2 :mbAddrB_coeff <= mbAddrB_coeff_reg[11:8]; + 4'd3 :mbAddrB_coeff <= mbAddrB_coeff_reg[15:12]; + 4'd4 :mbAddrB_coeff <= mbAddrB_coeff_reg[19:16]; + 4'd5 :mbAddrB_coeff <= mbAddrB_coeff_reg[23:20]; + 4'd6 :mbAddrB_coeff <= mbAddrB_coeff_reg[27:24]; + 4'd7 :mbAddrB_coeff <= mbAddrB_coeff_reg[31:28]; + 4'd8 :mbAddrB_coeff <= mbAddrB_coeff_reg[35:32]; + 4'd9 :mbAddrB_coeff <= mbAddrB_coeff_reg[39:36]; + 4'd10:mbAddrB_coeff <= mbAddrB_coeff_reg[43:40]; + endcase + end + + always @ (posedge gclk_bs_dec or negedge reset_n) + if (reset_n == 1'b0) + begin + bs_V0 <= 0; bs_V1 <= 0; bs_V2 <= 0; bs_V3 <= 0; + bs_H0 <= 0; bs_H1 <= 0; bs_H2 <= 0; bs_H3 <= 0; + end + //----------------------- + //Current MB is P_skip + //----------------------- + else if (mb_type_general_DF == `MB_P_skip) + case (bs_dec_counter) + 2'b00: + begin + //V0 + if (mb_num_h == 0) //edge of frame,bs = 0 + bs_V0 <= 12'b0; + else if (MBTypeGen_mbAddrA[1] == 1'b1) //mbAddrA is Intra,bs = 4 + bs_V0 <= 12'b100100100100; + else if (MBTypeGen_mbAddrA == `MB_addrA_addrB_P_skip) //mbAddrA is P_skip + bs_V0 <= (mvx_V0_diff_GE4 || mvy_V0_diff_GE4)? 12'b001001001001:12'b0; + else //mbAddrA is Inter + begin + bs_V0[2:0] <= (mbAddrA_coeff[0])? 3'd2:(mvx_V0_diff_GE4 || mvy_V0_diff_GE4)? 3'd1:3'd0; + bs_V0[5:3] <= (mbAddrA_coeff[1])? 3'd2:(mvx_V1_diff_GE4 || mvy_V1_diff_GE4)? 3'd1:3'd0; + bs_V0[8:6] <= (mbAddrA_coeff[2])? 3'd2:(mvx_V2_diff_GE4 || mvy_V2_diff_GE4)? 3'd1:3'd0; + bs_V0[11:9] <= (mbAddrA_coeff[3])? 3'd2:(mvx_V3_diff_GE4 || mvy_V3_diff_GE4)? 3'd1:3'd0; + end + //H0 + if (mb_num_v == 0) //edge of frame,bs = 0 + bs_H0 <= 12'b0; + else if (MBTypeGen_mbAddrB[1] == 1'b1) //mbAddrB is Intra,bs=4 + bs_H0 <= 12'b100100100100; + else if (MBTypeGen_mbAddrB == `MB_addrA_addrB_P_skip) //mbAddrB is P_skip + bs_H0 <= (mvx_H0_diff_GE4 || mvy_H0_diff_GE4)? 12'b001001001001:12'b0; + else + begin + bs_H0[2:0] <= (mbAddrB_coeff[0])? 3'd2:(mvx_H0_diff_GE4 || mvy_H0_diff_GE4)? 3'd1:3'd0; + bs_H0[5:3] <= (mbAddrB_coeff[1])? 3'd2:(mvx_H1_diff_GE4 || mvy_H1_diff_GE4)? 3'd1:3'd0; + bs_H0[8:6] <= (mbAddrB_coeff[2])? 3'd2:(mvx_H2_diff_GE4 || mvy_H2_diff_GE4)? 3'd1:3'd0; + bs_H0[11:9] <= (mbAddrB_coeff[3])? 3'd2:(mvx_H3_diff_GE4 || mvy_H3_diff_GE4)? 3'd1:3'd0; + end + end + 2'b11:begin bs_V1 <= 0; bs_H1 <= 0; end + 2'b10:begin bs_V2 <= 0; bs_H2 <= 0; end + 2'b01:begin bs_V3 <= 0; bs_H3 <= 0; end + endcase + //-------------------- + //Current MB is Intra + //----------------------- + else if (mb_type_general_DF[3] == 1'b1) + case (bs_dec_counter) + 2'b00: + begin + bs_V0 <= (mb_num_h == 0)? 12'b0:12'b100100100100; + bs_H0 <= (mb_num_v == 0)? 12'b0:12'b100100100100; + end + 2'b11:begin bs_V1 <= 12'b011011011011; bs_H1 <= 12'b011011011011; end + 2'b10:begin bs_V2 <= 12'b011011011011; bs_H2 <= 12'b011011011011; end + 2'b01:begin bs_V3 <= 12'b011011011011; bs_H3 <= 12'b011011011011; end + endcase + //----------------------- + //Current MB is Inter + //----------------------- + else + case (bs_dec_counter) + 2'b00: //V0,H0 + begin + //V0 + if (mb_num_h == 0) //edge of frame,bs = 0 + bs_V0 <= 12'b0; + else if (MBTypeGen_mbAddrA[1] == 1'b1) //mbAddrA is Intra,bs = 4 + bs_V0 <= 12'b100100100100; + else if (MBTypeGen_mbAddrA == `MB_addrA_addrB_P_skip) //mbAddrA is P_skip + begin + bs_V0[2:0] <= (currMB_coeff[0])? 3'd2:(mvx_V0_diff_GE4 || mvy_V0_diff_GE4)? 3'd1:3'd0; + bs_V0[5:3] <= (currMB_coeff[2])? 3'd2:(mvx_V1_diff_GE4 || mvy_V1_diff_GE4)? 3'd1:3'd0; + bs_V0[8:6] <= (currMB_coeff[8])? 3'd2:(mvx_V2_diff_GE4 || mvy_V2_diff_GE4)? 3'd1:3'd0; + bs_V0[11:9] <= (currMB_coeff[10])? 3'd2:(mvx_V3_diff_GE4 || mvy_V3_diff_GE4)? 3'd1:3'd0; + end + else //mbAddrA is Inter + begin + bs_V0[2:0] <= (mbAddrA_coeff[0] || currMB_coeff[0])? 3'd2:(mvx_V0_diff_GE4 || mvy_V0_diff_GE4)? 3'd1:3'd0; + bs_V0[5:3] <= (mbAddrA_coeff[1] || currMB_coeff[2])? 3'd2:(mvx_V1_diff_GE4 || mvy_V1_diff_GE4)? 3'd1:3'd0; + bs_V0[8:6] <= (mbAddrA_coeff[2] || currMB_coeff[8])? 3'd2:(mvx_V2_diff_GE4 || mvy_V2_diff_GE4)? 3'd1:3'd0; + bs_V0[11:9] <= (mbAddrA_coeff[3] || currMB_coeff[10])? 3'd2:(mvx_V3_diff_GE4 || mvy_V3_diff_GE4)? 3'd1:3'd0; + end + //H0 + if (mb_num_v == 0) //edge of frame,bs = 0 + bs_H0 <= 12'b0; + else if (MBTypeGen_mbAddrB[1] == 1'b1) //mbAddrB is Intra,bs = 4 + bs_H0 <= 12'b100100100100; + else if (MBTypeGen_mbAddrB == `MB_addrA_addrB_P_skip) //mbAddrB is P_skip + begin + bs_H0[2:0] <= (currMB_coeff[0])? 3'd2:(mvx_H0_diff_GE4 || mvy_H0_diff_GE4)? 3'd1:3'd0; + bs_H0[5:3] <= (currMB_coeff[1])? 3'd2:(mvx_H1_diff_GE4 || mvy_H1_diff_GE4)? 3'd1:3'd0; + bs_H0[8:6] <= (currMB_coeff[4])? 3'd2:(mvx_H2_diff_GE4 || mvy_H2_diff_GE4)? 3'd1:3'd0; + bs_H0[11:9] <= (currMB_coeff[5])? 3'd2:(mvx_H3_diff_GE4 || mvy_H3_diff_GE4)? 3'd1:3'd0; + end + else //mbAddrB is Inter + begin + bs_H0[2:0] <= (mbAddrB_coeff[0] || currMB_coeff[0])? 3'd2:(mvx_H0_diff_GE4 || mvy_H0_diff_GE4)? 3'd1:3'd0; + bs_H0[5:3] <= (mbAddrB_coeff[1] || currMB_coeff[1])? 3'd2:(mvx_H1_diff_GE4 || mvy_H1_diff_GE4)? 3'd1:3'd0; + bs_H0[8:6] <= (mbAddrB_coeff[2] || currMB_coeff[4])? 3'd2:(mvx_H2_diff_GE4 || mvy_H2_diff_GE4)? 3'd1:3'd0; + bs_H0[11:9] <= (mbAddrB_coeff[3] || currMB_coeff[5])? 3'd2:(mvx_H3_diff_GE4 || mvy_H3_diff_GE4)? 3'd1:3'd0; + end + end + 2'b11://V1,H1 + begin + bs_V1[2:0] <= (currMB_coeff[0] || currMB_coeff[1])? 3'd2:(MB_inter_size != `I8x8)? + 0:(mvx_V0_diff_GE4 || mvy_V0_diff_GE4)? 3'd1:3'd0; + + bs_V1[5:3] <= (currMB_coeff[2] || currMB_coeff[3])? 3'd2:(MB_inter_size != `I8x8)? + 0:(mvx_V1_diff_GE4 || mvy_V1_diff_GE4)? 3'd1:3'd0; + + bs_V1[8:6] <= (currMB_coeff[8] || currMB_coeff[9])? 3'd2:(MB_inter_size != `I8x8)? + 0:(mvx_V2_diff_GE4 || mvy_V2_diff_GE4)? 3'd1:3'd0; + + bs_V1[11:9] <= (currMB_coeff[10] || currMB_coeff[11])? 3'd2:(MB_inter_size != `I8x8)? + 0:(mvx_V3_diff_GE4 || mvy_V3_diff_GE4)? 3'd1:3'd0; + + bs_H1[2:0] <= (currMB_coeff[0] || currMB_coeff[2])? 3'd2:(MB_inter_size != `I8x8)? + 0:(mvx_H0_diff_GE4 || mvy_H0_diff_GE4)? 3'd1:3'd0; + + bs_H1[5:3] <= (currMB_coeff[1] || currMB_coeff[3])? 3'd2:(MB_inter_size != `I8x8)? + 0:(mvx_H1_diff_GE4 || mvy_H1_diff_GE4)? 3'd1:3'd0; + + bs_H1[8:6] <= (currMB_coeff[4] || currMB_coeff[6])? 3'd2:(MB_inter_size != `I8x8)? + 0:(mvx_H2_diff_GE4 || mvy_H2_diff_GE4)? 3'd1:3'd0; + bs_H1[11:9] <= (currMB_coeff[5] || currMB_coeff[7])? 3'd2:(MB_inter_size != `I8x8)? + 0:(mvx_H3_diff_GE4 || mvy_H3_diff_GE4)? 3'd1:3'd0; + end + 2'b10://V2,H2 + begin + bs_V2[2:0] <= (currMB_coeff[1] || currMB_coeff[4])? 3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? + 0:(mvx_V0_diff_GE4 || mvy_V0_diff_GE4)? 3'd1:3'd0; + + bs_V2[5:3] <= (currMB_coeff[3] || currMB_coeff[6])? 3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? + 0:(mvx_V1_diff_GE4 || mvy_V1_diff_GE4)? 3'd1:3'd0; + + bs_V2[8:6] <= (currMB_coeff[9] || currMB_coeff[12])? 3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? + 0:(mvx_V2_diff_GE4 || mvy_V2_diff_GE4)? 3'd1:3'd0; + + bs_V2[11:9] <= (currMB_coeff[11] || currMB_coeff[14])? 3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? + 0:(mvx_V3_diff_GE4 || mvy_V3_diff_GE4)? 3'd1:3'd0; + + bs_H2[2:0] <= (currMB_coeff[2] || currMB_coeff[8])? 3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? + 0:(mvx_H0_diff_GE4 || mvy_H0_diff_GE4)? 3'd1:3'd0; + + bs_H2[5:3] <= (currMB_coeff[3] || currMB_coeff[9])? 3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? + 0:(mvx_H1_diff_GE4 || mvy_H1_diff_GE4)? 3'd1:3'd0; + + bs_H2[8:6] <= (currMB_coeff[6] || currMB_coeff[12])? 3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? + 0:(mvx_H2_diff_GE4 || mvy_H2_diff_GE4)? 3'd1:3'd0; + + bs_H2[11:9] <= (currMB_coeff[7] || currMB_coeff[13])? 3'd2:(MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? + 0:(mvx_H3_diff_GE4 || mvy_H3_diff_GE4)? 3'd1:3'd0; + end + 2'b01://V3,H3 + begin + bs_V3[2:0] <= (currMB_coeff[4] || currMB_coeff[5])? 3'd2:(MB_inter_size != `I8x8)? + 0:(mvx_V0_diff_GE4 || mvy_V0_diff_GE4)? 3'd1:3'd0; + + bs_V3[5:3] <= (currMB_coeff[6] || currMB_coeff[7])? 3'd2:(MB_inter_size != `I8x8)? + 0:(mvx_V1_diff_GE4 || mvy_V1_diff_GE4)? 3'd1:3'd0; + + bs_V3[8:6] <= (currMB_coeff[12] || currMB_coeff[13])? 3'd2:(MB_inter_size != `I8x8)? + 0:(mvx_V2_diff_GE4 || mvy_V2_diff_GE4)? 3'd1:3'd0; + + bs_V3[11:9] <= (currMB_coeff[14] || currMB_coeff[15])? 3'd2:(MB_inter_size != `I8x8)? + 0:(mvx_V3_diff_GE4 || mvy_V3_diff_GE4)? 3'd1:3'd0; + + bs_H3[2:0] <= (currMB_coeff[8] || currMB_coeff[10])? 3'd2:(MB_inter_size != `I8x8)? + 0:(mvx_H0_diff_GE4 || mvy_H0_diff_GE4)? 3'd1:3'd0; + + bs_H3[5:3] <= (currMB_coeff[9] || currMB_coeff[11])? 3'd2:(MB_inter_size != `I8x8)? + 0:(mvx_H1_diff_GE4 || mvy_H1_diff_GE4)? 3'd1:3'd0; + + bs_H3[8:6] <= (currMB_coeff[12] || currMB_coeff[14])? 3'd2:(MB_inter_size != `I8x8)? + 0:(mvx_H2_diff_GE4 || mvy_H2_diff_GE4)? 3'd1:3'd0; + + bs_H3[11:9] <= (currMB_coeff[13] || currMB_coeff[15])? 3'd2:(MB_inter_size != `I8x8)? + 0:(mvx_H3_diff_GE4 || mvy_H3_diff_GE4)? 3'd1:3'd0; + end + endcase + + reg [7:0] mvx_V0_diff_a,mvx_V0_diff_b; + reg [7:0] mvx_V1_diff_a,mvx_V1_diff_b; + reg [7:0] mvx_V2_diff_a,mvx_V2_diff_b; + reg [7:0] mvx_V3_diff_a,mvx_V3_diff_b; + reg [7:0] mvy_V0_diff_a,mvy_V0_diff_b; + reg [7:0] mvy_V1_diff_a,mvy_V1_diff_b; + reg [7:0] mvy_V2_diff_a,mvy_V2_diff_b; + reg [7:0] mvy_V3_diff_a,mvy_V3_diff_b; + + reg [7:0] mvx_H0_diff_a,mvx_H0_diff_b; + reg [7:0] mvx_H1_diff_a,mvx_H1_diff_b; + reg [7:0] mvx_H2_diff_a,mvx_H2_diff_b; + reg [7:0] mvx_H3_diff_a,mvx_H3_diff_b; + reg [7:0] mvy_H0_diff_a,mvy_H0_diff_b; + reg [7:0] mvy_H1_diff_a,mvy_H1_diff_b; + reg [7:0] mvy_H2_diff_a,mvy_H2_diff_b; + reg [7:0] mvy_H3_diff_a,mvy_H3_diff_b; + + mv_diff_GE4 mvx_V0_diff (.mv_a(mvx_V0_diff_a),.mv_b(mvx_V0_diff_b),.diff_GE4(mvx_V0_diff_GE4)); + mv_diff_GE4 mvx_V1_diff (.mv_a(mvx_V1_diff_a),.mv_b(mvx_V1_diff_b),.diff_GE4(mvx_V1_diff_GE4)); + mv_diff_GE4 mvx_V2_diff (.mv_a(mvx_V2_diff_a),.mv_b(mvx_V2_diff_b),.diff_GE4(mvx_V2_diff_GE4)); + mv_diff_GE4 mvx_V3_diff (.mv_a(mvx_V3_diff_a),.mv_b(mvx_V3_diff_b),.diff_GE4(mvx_V3_diff_GE4)); + mv_diff_GE4 mvy_V0_diff (.mv_a(mvy_V0_diff_a),.mv_b(mvy_V0_diff_b),.diff_GE4(mvy_V0_diff_GE4)); + mv_diff_GE4 mvy_V1_diff (.mv_a(mvy_V1_diff_a),.mv_b(mvy_V1_diff_b),.diff_GE4(mvy_V1_diff_GE4)); + mv_diff_GE4 mvy_V2_diff (.mv_a(mvy_V2_diff_a),.mv_b(mvy_V2_diff_b),.diff_GE4(mvy_V2_diff_GE4)); + mv_diff_GE4 mvy_V3_diff (.mv_a(mvy_V3_diff_a),.mv_b(mvy_V3_diff_b),.diff_GE4(mvy_V3_diff_GE4)); + + mv_diff_GE4 mvx_H0_diff (.mv_a(mvx_H0_diff_a),.mv_b(mvx_H0_diff_b),.diff_GE4(mvx_H0_diff_GE4)); + mv_diff_GE4 mvx_H1_diff (.mv_a(mvx_H1_diff_a),.mv_b(mvx_H1_diff_b),.diff_GE4(mvx_H1_diff_GE4)); + mv_diff_GE4 mvx_H2_diff (.mv_a(mvx_H2_diff_a),.mv_b(mvx_H2_diff_b),.diff_GE4(mvx_H2_diff_GE4)); + mv_diff_GE4 mvx_H3_diff (.mv_a(mvx_H3_diff_a),.mv_b(mvx_H3_diff_b),.diff_GE4(mvx_H3_diff_GE4)); + mv_diff_GE4 mvy_H0_diff (.mv_a(mvy_H0_diff_a),.mv_b(mvy_H0_diff_b),.diff_GE4(mvy_H0_diff_GE4)); + mv_diff_GE4 mvy_H1_diff (.mv_a(mvy_H1_diff_a),.mv_b(mvy_H1_diff_b),.diff_GE4(mvy_H1_diff_GE4)); + mv_diff_GE4 mvy_H2_diff (.mv_a(mvy_H2_diff_a),.mv_b(mvy_H2_diff_b),.diff_GE4(mvy_H2_diff_GE4)); + mv_diff_GE4 mvy_H3_diff (.mv_a(mvy_H3_diff_a),.mv_b(mvy_H3_diff_b),.diff_GE4(mvy_H3_diff_GE4)); + + always @ (end_of_MB_DEC or disable_DF or bs_dec_counter or mb_type_general_DF + or mb_num_h or MB_inter_size or MBTypeGen_mbAddrA + or mbAddrA_mvx or mvx_CurrMb0 or mvx_CurrMb1 or mvx_CurrMb2 or mvx_CurrMb3 + or mbAddrA_mvy or mvy_CurrMb0 or mvy_CurrMb1 or mvy_CurrMb2 or mvy_CurrMb3) + if ((end_of_MB_DEC && disable_DF == 1'b0) || bs_dec_counter != 0) + begin + //----------------------- + //Current MB is P_skip + //----------------------- + if (mb_type_general_DF == `MB_P_skip && bs_dec_counter == 2'b00)//V0 + begin + if (mb_num_h != 0 && MBTypeGen_mbAddrA == `MB_addrA_addrB_P_skip) //mbAddrA is P_skip + begin + mvx_V0_diff_a <= mbAddrA_mvx[7:0]; mvx_V0_diff_b <= mvx_CurrMb0[7:0]; + mvx_V1_diff_a <= 0; mvx_V1_diff_b <= 0; + mvx_V2_diff_a <= 0; mvx_V2_diff_b <= 0; + mvx_V3_diff_a <= 0; mvx_V3_diff_b <= 0; + mvy_V0_diff_a <= mbAddrA_mvy[7:0]; mvy_V0_diff_b <= mvy_CurrMb0[7:0]; + mvy_V1_diff_a <= 0; mvy_V1_diff_b <= 0; + mvy_V2_diff_a <= 0; mvy_V2_diff_b <= 0; + mvy_V3_diff_a <= 0; mvy_V3_diff_b <= 0; + end + else if (mb_num_h != 0 && MBTypeGen_mbAddrA == `MB_addrA_addrB_Inter) //mbAddrA is Inter + begin + mvx_V0_diff_a <= mbAddrA_mvx[7:0]; mvx_V0_diff_b <= mvx_CurrMb0[7:0]; + mvx_V1_diff_a <= mbAddrA_mvx[15:8]; mvx_V1_diff_b <= mvx_CurrMb0[7:0]; + mvx_V2_diff_a <= mbAddrA_mvx[23:16];mvx_V2_diff_b <= mvx_CurrMb0[7:0]; + mvx_V3_diff_a <= mbAddrA_mvx[31:24];mvx_V3_diff_b <= mvx_CurrMb0[7:0]; + mvy_V0_diff_a <= mbAddrA_mvy[7:0]; mvy_V0_diff_b <= mvy_CurrMb0[7:0]; + mvy_V1_diff_a <= mbAddrA_mvy[15:8]; mvy_V1_diff_b <= mvy_CurrMb0[7:0]; + mvy_V2_diff_a <= mbAddrA_mvy[23:16];mvy_V2_diff_b <= mvy_CurrMb0[7:0]; + mvy_V3_diff_a <= mbAddrA_mvy[31:24];mvy_V3_diff_b <= mvy_CurrMb0[7:0]; + end + else + begin + mvx_V0_diff_a <= 0; mvx_V0_diff_b <= 0; + mvx_V1_diff_a <= 0; mvx_V1_diff_b <= 0; + mvx_V2_diff_a <= 0; mvx_V2_diff_b <= 0; + mvx_V3_diff_a <= 0; mvx_V3_diff_b <= 0; + mvy_V0_diff_a <= 0; mvy_V0_diff_b <= 0; + mvy_V1_diff_a <= 0; mvy_V1_diff_b <= 0; + mvy_V2_diff_a <= 0; mvy_V2_diff_b <= 0; + mvy_V3_diff_a <= 0; mvy_V3_diff_b <= 0; + end + end + //----------------------- + //Current MB is Inter + //----------------------- + else if (mb_type_general_DF[3] == 1'b0) + case (bs_dec_counter) + 2'b00: //V0 + if (mb_num_h != 0 && (MBTypeGen_mbAddrA[1] == 1'b0)) //mbAddrA is P_skip or Inter + begin + mvx_V0_diff_a <= mbAddrA_mvx[7:0]; mvx_V0_diff_b <= mvx_CurrMb0[7:0]; + + mvx_V1_diff_a <= mbAddrA_mvx[15:8]; + mvx_V1_diff_b <= (MB_inter_size == `I16x16)? mvx_CurrMb0[7:0]:mvx_CurrMb0[23:16]; + + mvx_V2_diff_a <= mbAddrA_mvx[23:16]; + mvx_V2_diff_b <= (MB_inter_size == `I16x16)? mvx_CurrMb0[7:0]:mvx_CurrMb2[7:0]; + + mvx_V3_diff_a <= mbAddrA_mvx[31:24]; + mvx_V3_diff_b <= (MB_inter_size == `I16x16)? mvx_CurrMb0[7:0]:mvx_CurrMb2[23:16]; + + mvy_V0_diff_a <= mbAddrA_mvy[7:0]; mvy_V0_diff_b <= mvy_CurrMb0[7:0]; + + mvy_V1_diff_a <= mbAddrA_mvy[15:8]; + mvy_V1_diff_b <= (MB_inter_size == `I16x16)? mvy_CurrMb0[7:0]:mvy_CurrMb0[23:16]; + + mvy_V2_diff_a <= mbAddrA_mvy[23:16]; + mvy_V2_diff_b <= (MB_inter_size == `I16x16)? mvy_CurrMb0[7:0]:mvy_CurrMb2[7:0]; + + mvy_V3_diff_a <= mbAddrA_mvy[31:24]; + mvy_V3_diff_b <= (MB_inter_size == `I16x16)? mvy_CurrMb0[7:0]:mvy_CurrMb2[23:16]; + end + else + begin + mvx_V0_diff_a <= 0; mvx_V0_diff_b <= 0; + mvx_V1_diff_a <= 0; mvx_V1_diff_b <= 0; + mvx_V2_diff_a <= 0; mvx_V2_diff_b <= 0; + mvx_V3_diff_a <= 0; mvx_V3_diff_b <= 0; + mvy_V0_diff_a <= 0; mvy_V0_diff_b <= 0; + mvy_V1_diff_a <= 0; mvy_V1_diff_b <= 0; + mvy_V2_diff_a <= 0; mvy_V2_diff_b <= 0; + mvy_V3_diff_a <= 0; mvy_V3_diff_b <= 0; + end + 2'b11: //V1 + begin + mvx_V0_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb0[7:0]; + mvx_V0_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb0[15:8]; + mvx_V1_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb0[23:16]; + mvx_V1_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb0[31:24]; + mvx_V2_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb2[7:0]; + mvx_V2_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb2[15:8]; + mvx_V3_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb2[23:16]; + mvx_V3_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb2[31:24]; + + mvy_V0_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb0[7:0]; + mvy_V0_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb0[15:8]; + mvy_V1_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb0[23:16]; + mvy_V1_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb0[31:24]; + mvy_V2_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb2[7:0]; + mvy_V2_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb2[15:8]; + mvy_V3_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb2[23:16]; + mvy_V3_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb2[31:24]; + end + 2'b10: //V2 + begin + mvx_V0_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvx_CurrMb0[15:8]; + mvx_V0_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvx_CurrMb1[7:0]; + mvx_V1_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvx_CurrMb0[31:24]; + mvx_V1_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvx_CurrMb1[23:16]; + mvx_V2_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvx_CurrMb2[15:8]; + mvx_V2_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvx_CurrMb3[7:0]; + mvx_V3_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvx_CurrMb2[31:24]; + mvx_V3_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvx_CurrMb3[23:16]; + mvy_V0_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvy_CurrMb0[15:8]; + mvy_V0_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvy_CurrMb1[7:0]; + mvy_V1_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvy_CurrMb0[31:24]; + mvy_V1_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvy_CurrMb1[23:16]; + mvy_V2_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvy_CurrMb2[15:8]; + mvy_V2_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvy_CurrMb3[7:0]; + mvy_V3_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvy_CurrMb2[31:24]; + mvy_V3_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I16x8)? 0:mvy_CurrMb3[23:16]; + end + 2'b01: //V3 + begin + mvx_V0_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb1[7:0]; + mvx_V0_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb1[15:8]; + mvx_V1_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb1[23:16]; + mvx_V1_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb1[31:24]; + mvx_V2_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb3[7:0]; + mvx_V2_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb3[15:8]; + mvx_V3_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb3[23:16]; + mvx_V3_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb3[31:24]; + + mvy_V0_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb1[7:0]; + mvy_V0_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb1[15:8]; + mvy_V1_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb1[23:16]; + mvy_V1_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb1[31:24]; + mvy_V2_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb3[7:0]; + mvy_V2_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb3[15:8]; + mvy_V3_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb3[23:16]; + mvy_V3_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb3[31:24]; + end + endcase + else + begin + mvx_V0_diff_a <= 0; mvx_V0_diff_b <= 0; + mvx_V1_diff_a <= 0; mvx_V1_diff_b <= 0; + mvx_V2_diff_a <= 0; mvx_V2_diff_b <= 0; + mvx_V3_diff_a <= 0; mvx_V3_diff_b <= 0; + mvy_V0_diff_a <= 0; mvy_V0_diff_b <= 0; + mvy_V1_diff_a <= 0; mvy_V1_diff_b <= 0; + mvy_V2_diff_a <= 0; mvy_V2_diff_b <= 0; + mvy_V3_diff_a <= 0; mvy_V3_diff_b <= 0; + end + end + else + begin + mvx_V0_diff_a <= 0; mvx_V0_diff_b <= 0; + mvx_V1_diff_a <= 0; mvx_V1_diff_b <= 0; + mvx_V2_diff_a <= 0; mvx_V2_diff_b <= 0; + mvx_V3_diff_a <= 0; mvx_V3_diff_b <= 0; + mvy_V0_diff_a <= 0; mvy_V0_diff_b <= 0; + mvy_V1_diff_a <= 0; mvy_V1_diff_b <= 0; + mvy_V2_diff_a <= 0; mvy_V2_diff_b <= 0; + mvy_V3_diff_a <= 0; mvy_V3_diff_b <= 0; + end + + + always @ (end_of_MB_DEC or disable_DF or bs_dec_counter or mb_type_general_DF + or mb_num_v or MBTypeGen_mbAddrB or MB_inter_size + or mbAddrB_mvx or mvx_CurrMb0 or mvx_CurrMb1 or mvx_CurrMb2 or mvx_CurrMb3 + or mbAddrB_mvy or mvy_CurrMb0 or mvy_CurrMb1 or mvy_CurrMb2 or mvy_CurrMb3) + if ((end_of_MB_DEC && disable_DF == 1'b0) || bs_dec_counter != 0) + begin + //----------------------- + //Current MB is P_skip + //----------------------- + if (mb_type_general_DF == `MB_P_skip && bs_dec_counter == 2'b00) //H0 + begin + if (mb_num_v != 0 && MBTypeGen_mbAddrB == `MB_addrA_addrB_P_skip) //mbAddrB is P_skip + begin + mvx_H0_diff_a <= mbAddrB_mvx[31:24]; mvx_H0_diff_b <= mvx_CurrMb0[7:0]; + mvx_H1_diff_a <= 0; mvx_H1_diff_b <= 0; + mvx_H2_diff_a <= 0; mvx_H2_diff_b <= 0; + mvx_H3_diff_a <= 0; mvx_H3_diff_b <= 0; + mvy_H0_diff_a <= mbAddrB_mvy[31:24]; mvy_H0_diff_b <= mvy_CurrMb0[7:0]; + mvy_H1_diff_a <= 0; mvy_H1_diff_b <= 0; + mvy_H2_diff_a <= 0; mvy_H2_diff_b <= 0; + mvy_H3_diff_a <= 0; mvy_H3_diff_b <= 0; + end + else if (mb_num_v != 0 && MBTypeGen_mbAddrB == 2'b00) //mbAddrB is Inter + begin + mvx_H0_diff_a <= mbAddrB_mvx[31:24]; mvx_H0_diff_b <= mvx_CurrMb0[7:0]; + mvx_H1_diff_a <= mbAddrB_mvx[23:16]; mvx_H1_diff_b <= mvx_CurrMb0[7:0]; + mvx_H2_diff_a <= mbAddrB_mvx[15:8]; mvx_H2_diff_b <= mvx_CurrMb0[7:0]; + mvx_H3_diff_a <= mbAddrB_mvx[7:0]; mvx_H3_diff_b <= mvx_CurrMb0[7:0]; + mvy_H0_diff_a <= mbAddrB_mvy[31:24]; mvy_H0_diff_b <= mvy_CurrMb0[7:0]; + mvy_H1_diff_a <= mbAddrB_mvy[23:16]; mvy_H1_diff_b <= mvy_CurrMb0[7:0]; + mvy_H2_diff_a <= mbAddrB_mvy[15:8]; mvy_H2_diff_b <= mvy_CurrMb0[7:0]; + mvy_H3_diff_a <= mbAddrB_mvy[7:0]; mvy_H3_diff_b <= mvy_CurrMb0[7:0]; + end + else + begin + mvx_H0_diff_a <= 0; mvx_H0_diff_b <= 0; + mvx_H1_diff_a <= 0; mvx_H1_diff_b <= 0; + mvx_H2_diff_a <= 0; mvx_H2_diff_b <= 0; + mvx_H3_diff_a <= 0; mvx_H3_diff_b <= 0; + mvy_H0_diff_a <= 0; mvy_H0_diff_b <= 0; + mvy_H1_diff_a <= 0; mvy_H1_diff_b <= 0; + mvy_H2_diff_a <= 0; mvy_H2_diff_b <= 0; + mvy_H3_diff_a <= 0; mvy_H3_diff_b <= 0; + end + end + //----------------------- + //Current MB is Inter + //----------------------- + else if (mb_type_general_DF[3] == 1'b0) + case (bs_dec_counter) + 2'b00: //H0 + if (mb_num_v != 0 && (MBTypeGen_mbAddrB[1] == 1'b0))//mbAddrB is P_skip or Inter + begin + mvx_H0_diff_a <= mbAddrB_mvx[31:24]; mvx_H0_diff_b <= mvx_CurrMb0[7:0]; + + mvx_H1_diff_a <= mbAddrB_mvx[23:16]; + mvx_H1_diff_b <= (MB_inter_size == `I16x16)? mvx_CurrMb0[7:0]:mvx_CurrMb0[15:8]; + + mvx_H2_diff_a <= mbAddrB_mvx[15:8]; + mvx_H2_diff_b <= (MB_inter_size == `I16x16)? mvx_CurrMb0[7:0]:mvx_CurrMb1[7:0]; + + mvx_H3_diff_a <= mbAddrB_mvx[7:0]; + mvx_H3_diff_b <= (MB_inter_size == `I16x16)? mvx_CurrMb0[7:0]:mvx_CurrMb1[15:8]; + + mvy_H0_diff_a <= mbAddrB_mvy[31:24]; mvy_H0_diff_b <= mvy_CurrMb0[7:0]; + + mvy_H1_diff_a <= mbAddrB_mvy[23:16]; + mvy_H1_diff_b <= (MB_inter_size == `I16x16)? mvy_CurrMb0[7:0]:mvy_CurrMb0[15:8]; + + mvy_H2_diff_a <= mbAddrB_mvy[15:8]; + mvy_H2_diff_b <= (MB_inter_size == `I16x16)? mvy_CurrMb0[7:0]:mvy_CurrMb1[7:0]; + + mvy_H3_diff_a <= mbAddrB_mvy[7:0]; + mvy_H3_diff_b <= (MB_inter_size == `I16x16)? mvy_CurrMb0[7:0]:mvy_CurrMb1[15:8]; + end + else + begin + mvx_H0_diff_a <= 0; mvx_H0_diff_b <= 0; + mvx_H1_diff_a <= 0; mvx_H1_diff_b <= 0; + mvx_H2_diff_a <= 0; mvx_H2_diff_b <= 0; + mvx_H3_diff_a <= 0; mvx_H3_diff_b <= 0; + mvy_H0_diff_a <= 0; mvy_H0_diff_b <= 0; + mvy_H1_diff_a <= 0; mvy_H1_diff_b <= 0; + mvy_H2_diff_a <= 0; mvy_H2_diff_b <= 0; + mvy_H3_diff_a <= 0; mvy_H3_diff_b <= 0; + end + 2'b11: //H1 + begin + mvx_H0_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb0[7:0]; + mvx_H0_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb0[23:16]; + mvx_H1_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb0[15:8]; + mvx_H1_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb0[31:24]; + mvx_H2_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb1[7:0]; + mvx_H2_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb1[23:16]; + mvx_H3_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb1[15:8]; + mvx_H3_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb1[31:24]; + + mvy_H0_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb0[7:0]; + mvy_H0_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb0[23:16]; + mvy_H1_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb0[15:8]; + mvy_H1_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb0[31:24]; + mvy_H2_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb1[7:0]; + mvy_H2_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb1[23:16]; + mvy_H3_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb1[15:8]; + mvy_H3_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb1[31:24]; + end + 2'b10: //H2 + begin + mvx_H0_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvx_CurrMb0[23:16]; + mvx_H0_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvx_CurrMb2[7:0]; + mvx_H1_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvx_CurrMb0[31:24]; + mvx_H1_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvx_CurrMb2[15:8]; + mvx_H2_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvx_CurrMb1[23:16]; + mvx_H2_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvx_CurrMb3[7:0]; + mvx_H3_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvx_CurrMb1[31:24]; + mvx_H3_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvx_CurrMb3[15:8]; + + mvy_H0_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvy_CurrMb0[23:16]; + mvy_H0_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvy_CurrMb2[7:0]; + mvy_H1_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvy_CurrMb0[31:24]; + mvy_H1_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvy_CurrMb2[15:8]; + mvy_H2_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvy_CurrMb1[23:16]; + mvy_H2_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvy_CurrMb3[7:0]; + mvy_H3_diff_a <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvy_CurrMb1[31:24]; + mvy_H3_diff_b <= (MB_inter_size == `I16x16 || MB_inter_size == `I8x16)? 0:mvy_CurrMb3[15:8]; + + end + 2'b01: //H3 + begin + mvx_H0_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb2[7:0]; + mvx_H0_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb2[23:16]; + mvx_H1_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb2[15:8]; + mvx_H1_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb2[31:24]; + mvx_H2_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb3[7:0]; + mvx_H2_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb3[23:16]; + mvx_H3_diff_a <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb3[15:8]; + mvx_H3_diff_b <= (MB_inter_size != `I8x8)? 0:mvx_CurrMb3[31:24]; + + mvy_H0_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb2[7:0]; + mvy_H0_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb2[23:16]; + mvy_H1_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb2[15:8]; + mvy_H1_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb2[31:24]; + mvy_H2_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb3[7:0]; + mvy_H2_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb3[23:16]; + mvy_H3_diff_a <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb3[15:8]; + mvy_H3_diff_b <= (MB_inter_size != `I8x8)? 0:mvy_CurrMb3[31:24]; + end + endcase + else + begin + mvx_H0_diff_a <= 0; mvx_H0_diff_b <= 0; + mvx_H1_diff_a <= 0; mvx_H1_diff_b <= 0; + mvx_H2_diff_a <= 0; mvx_H2_diff_b <= 0; + mvx_H3_diff_a <= 0; mvx_H3_diff_b <= 0; + mvy_H0_diff_a <= 0; mvy_H0_diff_b <= 0; + mvy_H1_diff_a <= 0; mvy_H1_diff_b <= 0; + mvy_H2_diff_a <= 0; mvy_H2_diff_b <= 0; + mvy_H3_diff_a <= 0; mvy_H3_diff_b <= 0; + end + end + else + begin + mvx_H0_diff_a <= 0; mvx_H0_diff_b <= 0; + mvx_H1_diff_a <= 0; mvx_H1_diff_b <= 0; + mvx_H2_diff_a <= 0; mvx_H2_diff_b <= 0; + mvx_H3_diff_a <= 0; mvx_H3_diff_b <= 0; + mvy_H0_diff_a <= 0; mvy_H0_diff_b <= 0; + mvy_H1_diff_a <= 0; mvy_H1_diff_b <= 0; + mvy_H2_diff_a <= 0; mvy_H2_diff_b <= 0; + mvy_H3_diff_a <= 0; mvy_H3_diff_b <= 0; + end + /* + // synopsys translate_off + integer tracefile; + integer pic_num; + wire [6:0] mb_num; + assign mb_num = mb_num_v * 11 + mb_num_h; + + initial + begin + tracefile = $fopen("bs_trace.txt"); + end + reg bs_dec_will_end; + always @ (posedge clk) + if (bs_dec_counter == 2'b01) + bs_dec_will_end <= 1'b1; + else + bs_dec_will_end <= 1'b0; + always @ (posedge clk or negedge reset_n) + if (reset_n == 1'b0) + pic_num <= 0; + else if (bs_dec_will_end) + begin + $fdisplay (tracefile, "-------------------------------"); + if (mb_num == 0) + $fdisplay (tracefile, " Pic_num = %3d,MB_num = 98",(pic_num - 1)); + else + $fdisplay (tracefile, " Pic_num = %3d,MB_num = %3d",pic_num,(mb_num - 1)); + $fdisplay (tracefile, " Vertical Edge 0:Bs = %d,%d,%d,%d",bs_V0[2:0],bs_V0[5:3],bs_V0[8:6],bs_V0[11:9]); + $fdisplay (tracefile, " Vertical Edge 1:Bs = %d,%d,%d,%d",bs_V1[2:0],bs_V1[5:3],bs_V1[8:6],bs_V1[11:9]); + $fdisplay (tracefile, " Vertical Edge 2:Bs = %d,%d,%d,%d",bs_V2[2:0],bs_V2[5:3],bs_V2[8:6],bs_V2[11:9]); + $fdisplay (tracefile, " Vertical Edge 3:Bs = %d,%d,%d,%d",bs_V3[2:0],bs_V3[5:3],bs_V3[8:6],bs_V3[11:9]); + $fdisplay (tracefile, " Horizontal Edge 0:Bs = %d,%d,%d,%d",bs_H0[2:0],bs_H0[5:3],bs_H0[8:6],bs_H0[11:9]); + $fdisplay (tracefile, " Horizontal Edge 1:Bs = %d,%d,%d,%d",bs_H1[2:0],bs_H1[5:3],bs_H1[8:6],bs_H1[11:9]); + $fdisplay (tracefile, " Horizontal Edge 2:Bs = %d,%d,%d,%d",bs_H2[2:0],bs_H2[5:3],bs_H2[8:6],bs_H2[11:9]); + $fdisplay (tracefile, " Horizontal Edge 3:Bs = %d,%d,%d,%d",bs_H3[2:0],bs_H3[5:3],bs_H3[8:6],bs_H3[11:9]); + if (mb_num == 98) + pic_num <= pic_num + 1; + end + // synopsys translate_on + */ +endmodule + +module mv_diff_GE4 (mv_a,mv_b,diff_GE4); + input [7:0] mv_a,mv_b; + output diff_GE4; + wire [7:0] diff_tmp; + wire [6:0] diff; + assign diff_tmp = mv_a + ~ mv_b + 1; + assign diff = (diff_tmp[7] == 1'b1)? (~diff_tmp[6:0] + 1):diff_tmp[6:0]; + assign diff_GE4 = (diff[6:2] != 0)? 1'b1:1'b0; +endmodule + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/cavlc_consumed_bits_decoding.v b/demo_chip_rtl/rtl/nova/trunk/src/cavlc_consumed_bits_decoding.v new file mode 100644 index 0000000..046fd92 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/cavlc_consumed_bits_decoding.v @@ -0,0 +1,42 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : cavlc_consumed_bits_decoding.v +// Generated : June 12,2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Calculate the consumed bit length of CAVLC decoder of each clock cycle +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module cavlc_consumed_bits_decoding (cavlc_decoder_state,NumCoeffTrailingOnes_len,TrailingOnes, + heading_one_pos,levelSuffixSize,total_zeros_len,run_of_zeros_len,cavlc_consumed_bits_len); + input [3:0] cavlc_decoder_state; + input [4:0] NumCoeffTrailingOnes_len; + input [1:0] TrailingOnes; + input [3:0] heading_one_pos; + input [3:0] levelSuffixSize; + input [3:0] total_zeros_len; + input [3:0] run_of_zeros_len; + output [4:0] cavlc_consumed_bits_len; + reg [4:0] cavlc_consumed_bits_len; + + always @ (cavlc_decoder_state or NumCoeffTrailingOnes_len or TrailingOnes or heading_one_pos or + levelSuffixSize or total_zeros_len or run_of_zeros_len) + case (cavlc_decoder_state) + `NumCoeffTrailingOnes_LUT:cavlc_consumed_bits_len <= NumCoeffTrailingOnes_len; + `TrailingOnesSignFlag :cavlc_consumed_bits_len <= TrailingOnes; + `LevelPrefix :cavlc_consumed_bits_len <= heading_one_pos + 1; + `LevelSuffix :cavlc_consumed_bits_len <= levelSuffixSize; + `total_zeros_LUT :cavlc_consumed_bits_len <= total_zeros_len; + `run_before_LUT :cavlc_consumed_bits_len <= run_of_zeros_len; + default :cavlc_consumed_bits_len <= 0; + endcase +endmodule + diff --git a/demo_chip_rtl/rtl/nova/trunk/src/cavlc_decoder.v b/demo_chip_rtl/rtl/nova/trunk/src/cavlc_decoder.v new file mode 100644 index 0000000..de22b8c --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/cavlc_decoder.v @@ -0,0 +1,288 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : cavlc_decoder.v +// Generated : June 12,2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// cavlc_decoder top module +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module cavlc_decoder (clk,reset_n,gclk_end_of_MB_DEC, + gclk_LumaLevel_mbAddrB_RF,gclk_ChromaLevel_Cb_mbAddrB_RF,gclk_ChromaLevel_Cr_mbAddrB_RF, + slice_data_state,residual_state,cavlc_decoder_state,mb_num_h,mb_num_v,i8x8,i4x4,i4x4_CbCr, + i_level,i_run,i_TotalCoeff,coeffNum, + heading_one_pos,BitStream_buffer_output, + CodedBlockPatternLuma,CodedBlockPatternChroma,suffix_length_initialized,IsRunLoop, + + Luma_8x8_AllZeroCoeff_mbAddrA,LumaLevel_mbAddrA,LumaLevel_CurrMb0,LumaLevel_CurrMb1,LumaLevel_CurrMb2,LumaLevel_CurrMb3, + LumaLevel_mbAddrB_dout,LumaLevel_mbAddrB_cs_n,ChromaLevel_Cb_mbAddrB_cs_n,ChromaLevel_Cr_mbAddrB_cs_n, + end_of_one_residual_block,end_of_NonZeroCoeff_CAVLC, + cavlc_consumed_bits_len,TotalCoeff,TrailingOnes,maxNumCoeff,zerosLeft,run, + coeffLevel_0,coeffLevel_1,coeffLevel_2, coeffLevel_3, coeffLevel_4, coeffLevel_5, coeffLevel_6, coeffLevel_7, + coeffLevel_8,coeffLevel_9,coeffLevel_10,coeffLevel_11,coeffLevel_12,coeffLevel_13,coeffLevel_14,coeffLevel_15); + input clk,reset_n; + input gclk_end_of_MB_DEC; + input gclk_LumaLevel_mbAddrB_RF; + input gclk_ChromaLevel_Cb_mbAddrB_RF; + input gclk_ChromaLevel_Cr_mbAddrB_RF; + input [3:0] slice_data_state; + input [3:0] residual_state; + input [3:0] cavlc_decoder_state; + input [3:0] mb_num_h; + input [3:0] mb_num_v; + input [1:0] i8x8; + input [1:0] i4x4; + input [1:0] i4x4_CbCr; + input [3:0] i_level; + input [3:0] i_run; + input [3:0] i_TotalCoeff; + input [3:0] coeffNum; + input [3:0] heading_one_pos; + input [15:0] BitStream_buffer_output; + input [3:0] CodedBlockPatternLuma; + input [1:0] CodedBlockPatternChroma; + input suffix_length_initialized; + input IsRunLoop; + + output [1:0] Luma_8x8_AllZeroCoeff_mbAddrA; + output [19:0] LumaLevel_mbAddrA; + output [19:0] LumaLevel_CurrMb0,LumaLevel_CurrMb1,LumaLevel_CurrMb2,LumaLevel_CurrMb3; + output [19:0] LumaLevel_mbAddrB_dout; + output LumaLevel_mbAddrB_cs_n; + output ChromaLevel_Cb_mbAddrB_cs_n; + output ChromaLevel_Cr_mbAddrB_cs_n; + output end_of_one_residual_block; + output end_of_NonZeroCoeff_CAVLC; + output [4:0] cavlc_consumed_bits_len; + output [4:0] TotalCoeff; + output [1:0] TrailingOnes; + output [4:0] maxNumCoeff; + output [3:0] zerosLeft; + output [3:0] run; + output [8:0] coeffLevel_0, coeffLevel_1, coeffLevel_2,coeffLevel_3, coeffLevel_4, coeffLevel_5, coeffLevel_6; + output [8:0] coeffLevel_7, coeffLevel_8, coeffLevel_9,coeffLevel_10,coeffLevel_11,coeffLevel_12,coeffLevel_13; + output [8:0] coeffLevel_14,coeffLevel_15; + + wire LumaLevel_mbAddrB_cs_n,LumaLevel_mbAddrB_wr_n; + wire [3:0] LumaLevel_mbAddrB_rd_addr,LumaLevel_mbAddrB_wr_addr; + wire [19:0] LumaLevel_mbAddrB_din; + wire [19:0] LumaLevel_mbAddrB_dout; + wire ChromaLevel_Cb_mbAddrB_cs_n,ChromaLevel_Cb_mbAddrB_wr_n; + wire [3:0] ChromaLevel_Cb_mbAddrB_rd_addr,ChromaLevel_Cb_mbAddrB_wr_addr; + wire [9:0] ChromaLevel_Cb_mbAddrB_din; + wire [9:0] ChromaLevel_Cb_mbAddrB_dout; + wire ChromaLevel_Cr_mbAddrB_cs_n,ChromaLevel_Cr_mbAddrB_wr_n; + wire [3:0] ChromaLevel_Cr_mbAddrB_rd_addr,ChromaLevel_Cr_mbAddrB_wr_addr; + wire [9:0] ChromaLevel_Cr_mbAddrB_din; + wire [9:0] ChromaLevel_Cr_mbAddrB_dout; + wire [4:0] nC; + wire [4:0] NumCoeffTrailingOnes_len; + wire [3:0] levelSuffixSize; + wire [8:0] level_0,level_1,level_2, level_3, level_4, level_5, level_6, level_7; + wire [8:0] level_8,level_9,level_10,level_11,level_12,level_13,level_14,level_15; + wire [3:0] total_zeros; + wire [3:0] total_zeros_len; + wire [3:0] run_of_zeros_len; + + nC_decoding nC_decoding ( + .clk(clk), + .reset_n(reset_n), + .gclk_end_of_MB_DEC(gclk_end_of_MB_DEC), + .cavlc_decoder_state(cavlc_decoder_state), + .residual_state(residual_state), + .slice_data_state(slice_data_state), + .mb_num_h(mb_num_h), + .mb_num_v(mb_num_v), + .i8x8(i8x8), + .i4x4(i4x4), + .i4x4_CbCr(i4x4_CbCr), + .CodedBlockPatternLuma(CodedBlockPatternLuma), + .CodedBlockPatternChroma(CodedBlockPatternChroma), + .LumaLevel_mbAddrB_dout(LumaLevel_mbAddrB_dout), + .ChromaLevel_Cb_mbAddrB_dout(ChromaLevel_Cb_mbAddrB_dout), + .ChromaLevel_Cr_mbAddrB_dout(ChromaLevel_Cr_mbAddrB_dout), + .end_of_one_residual_block(end_of_one_residual_block), + .TotalCoeff(TotalCoeff), + + .nC(nC), + .Luma_8x8_AllZeroCoeff_mbAddrA(Luma_8x8_AllZeroCoeff_mbAddrA), + .LumaLevel_mbAddrA(LumaLevel_mbAddrA), + .LumaLevel_CurrMb0(LumaLevel_CurrMb0), + .LumaLevel_CurrMb1(LumaLevel_CurrMb1), + .LumaLevel_CurrMb2(LumaLevel_CurrMb2), + .LumaLevel_CurrMb3(LumaLevel_CurrMb3), + .LumaLevel_mbAddrB_cs_n(LumaLevel_mbAddrB_cs_n), + .LumaLevel_mbAddrB_wr_n(LumaLevel_mbAddrB_wr_n), + .LumaLevel_mbAddrB_rd_addr(LumaLevel_mbAddrB_rd_addr), + .LumaLevel_mbAddrB_wr_addr(LumaLevel_mbAddrB_wr_addr), + .LumaLevel_mbAddrB_din(LumaLevel_mbAddrB_din), + .ChromaLevel_Cb_mbAddrB_cs_n(ChromaLevel_Cb_mbAddrB_cs_n), + .ChromaLevel_Cb_mbAddrB_wr_n(ChromaLevel_Cb_mbAddrB_wr_n), + .ChromaLevel_Cb_mbAddrB_rd_addr(ChromaLevel_Cb_mbAddrB_rd_addr), + .ChromaLevel_Cb_mbAddrB_wr_addr(ChromaLevel_Cb_mbAddrB_wr_addr), + .ChromaLevel_Cb_mbAddrB_din(ChromaLevel_Cb_mbAddrB_din), + .ChromaLevel_Cr_mbAddrB_cs_n(ChromaLevel_Cr_mbAddrB_cs_n), + .ChromaLevel_Cr_mbAddrB_wr_n(ChromaLevel_Cr_mbAddrB_wr_n), + .ChromaLevel_Cr_mbAddrB_rd_addr(ChromaLevel_Cr_mbAddrB_rd_addr), + .ChromaLevel_Cr_mbAddrB_wr_addr(ChromaLevel_Cr_mbAddrB_wr_addr), + .ChromaLevel_Cr_mbAddrB_din(ChromaLevel_Cr_mbAddrB_din) + ); + ram_async_1r_sync_1w # (`LumaLevel_mbAddrB_RF_data_width,`LumaLevel_mbAddrB_RF_data_depth) + LumaLevel_mbAddrB_RF( + .clk(gclk_LumaLevel_mbAddrB_RF), + .rst_n(reset_n), + .cs_n(LumaLevel_mbAddrB_cs_n), + .wr_n(LumaLevel_mbAddrB_wr_n), + .rd_addr(LumaLevel_mbAddrB_rd_addr), + .wr_addr(LumaLevel_mbAddrB_wr_addr), + .data_in(LumaLevel_mbAddrB_din), + .data_out(LumaLevel_mbAddrB_dout) + ); + ram_async_1r_sync_1w # (`ChromaLevel_Cb_mbAddrB_RF_data_width,`ChromaLevel_Cb_mbAddrB_RF_data_depth) + ChromaLevel_Cb_mbAddrB_RF( + .clk(gclk_ChromaLevel_Cb_mbAddrB_RF), + .rst_n(reset_n), + .cs_n(ChromaLevel_Cb_mbAddrB_cs_n), + .wr_n(ChromaLevel_Cb_mbAddrB_wr_n), + .rd_addr(ChromaLevel_Cb_mbAddrB_rd_addr), + .wr_addr(ChromaLevel_Cb_mbAddrB_wr_addr), + .data_in(ChromaLevel_Cb_mbAddrB_din), + .data_out(ChromaLevel_Cb_mbAddrB_dout) + ); + ram_async_1r_sync_1w # (`ChromaLevel_Cr_mbAddrB_RF_data_width,`ChromaLevel_Cr_mbAddrB_RF_data_depth) + ChromaLevel_Cr_mbAddrB_RF( + .clk(gclk_ChromaLevel_Cr_mbAddrB_RF), + .rst_n(reset_n), + .cs_n(ChromaLevel_Cr_mbAddrB_cs_n), + .wr_n(ChromaLevel_Cr_mbAddrB_wr_n), + .rd_addr(ChromaLevel_Cr_mbAddrB_rd_addr), + .wr_addr(ChromaLevel_Cr_mbAddrB_wr_addr), + .data_in(ChromaLevel_Cr_mbAddrB_din), + .data_out(ChromaLevel_Cr_mbAddrB_dout) + ); + NumCoeffTrailingOnes_decoding NumCoeffTrailingOnes_decoding( + .clk(clk), + .reset_n(reset_n), + .cavlc_decoder_state(cavlc_decoder_state), + .heading_one_pos(heading_one_pos), + .BitStream_buffer_output(BitStream_buffer_output), + .nC(nC), + .TrailingOnes(TrailingOnes), + .TotalCoeff(TotalCoeff), + .NumCoeffTrailingOnes_len(NumCoeffTrailingOnes_len) + ); + level_decoding level_decoding( + .clk(clk), + .reset_n(reset_n), + .cavlc_decoder_state(cavlc_decoder_state), + .heading_one_pos(heading_one_pos), + .suffix_length_initialized(suffix_length_initialized), + .i_level(i_level), + .TotalCoeff(TotalCoeff), + .TrailingOnes(TrailingOnes), + .BitStream_buffer_output(BitStream_buffer_output), + .levelSuffixSize(levelSuffixSize), + .level_0(level_0), + .level_1(level_1), + .level_2(level_2), + .level_3(level_3), + .level_4(level_4), + .level_5(level_5), + .level_6(level_6), + .level_7(level_7), + .level_8(level_8), + .level_9(level_9), + .level_10(level_10), + .level_11(level_11), + .level_12(level_12), + .level_13(level_13), + .level_14(level_14), + .level_15(level_15) + ); + total_zeros_decoding total_zeros_decoding( + .clk(clk), + .reset_n(reset_n), + .residual_state(residual_state), + .cavlc_decoder_state(cavlc_decoder_state), + .TotalCoeff_3to0(TotalCoeff[3:0]), + .heading_one_pos(heading_one_pos), + .BitStream_buffer_output(BitStream_buffer_output), + .maxNumCoeff(maxNumCoeff), + .total_zeros(total_zeros), + .total_zeros_len(total_zeros_len) + ); + run_decoding run_decoding( + .clk(clk), + .reset_n(reset_n), + .cavlc_decoder_state(cavlc_decoder_state), + .BitStream_buffer_output(BitStream_buffer_output), + .total_zeros(total_zeros), + .level_0(level_0), + .level_1(level_1), + .level_2(level_2), + .level_3(level_3), + .level_4(level_4), + .level_5(level_5), + .level_6(level_6), + .level_7(level_7), + .level_8(level_8), + .level_9(level_9), + .level_10(level_10), + .level_11(level_11), + .level_12(level_12), + .level_13(level_13), + .level_14(level_14), + .level_15(level_15), + .TotalCoeff(TotalCoeff), + .i_run(i_run), + .i_TotalCoeff(i_TotalCoeff), + .coeffNum(coeffNum), + .IsRunLoop(IsRunLoop), + + .run_of_zeros_len(run_of_zeros_len), + .zerosLeft(zerosLeft), + .run(run), + .coeffLevel_0(coeffLevel_0), + .coeffLevel_1(coeffLevel_1), + .coeffLevel_2(coeffLevel_2), + .coeffLevel_3(coeffLevel_3), + .coeffLevel_4(coeffLevel_4), + .coeffLevel_5(coeffLevel_5), + .coeffLevel_6(coeffLevel_6), + .coeffLevel_7(coeffLevel_7), + .coeffLevel_8(coeffLevel_8), + .coeffLevel_9(coeffLevel_9), + .coeffLevel_10(coeffLevel_10), + .coeffLevel_11(coeffLevel_11), + .coeffLevel_12(coeffLevel_12), + .coeffLevel_13(coeffLevel_13), + .coeffLevel_14(coeffLevel_14), + .coeffLevel_15(coeffLevel_15) + ); + end_of_blk_decoding end_of_blk_decoding( + .reset_n(reset_n), + .cavlc_decoder_state(cavlc_decoder_state), + .TotalCoeff(TotalCoeff), + .i_TotalCoeff(i_TotalCoeff), + .end_of_one_residual_block(end_of_one_residual_block), + .end_of_NonZeroCoeff_CAVLC(end_of_NonZeroCoeff_CAVLC) + ); + cavlc_consumed_bits_decoding cavlc_consumed_bits_decoding( + .cavlc_decoder_state(cavlc_decoder_state), + .NumCoeffTrailingOnes_len(NumCoeffTrailingOnes_len), + .TrailingOnes(TrailingOnes), + .heading_one_pos(heading_one_pos), + .levelSuffixSize(levelSuffixSize), + .total_zeros_len(total_zeros_len), + .run_of_zeros_len(run_of_zeros_len), + .cavlc_consumed_bits_len(cavlc_consumed_bits_len) + ); +endmodule \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/dependent_variable_decoding.v b/demo_chip_rtl/rtl/nova/trunk/src/dependent_variable_decoding.v new file mode 100644 index 0000000..b37f861 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/dependent_variable_decoding.v @@ -0,0 +1,55 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : dependent_variable_decoding.v +// Generated : June 6,2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// for u(v) decoding as frame_num,pic_order_cnt_lsb +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module dependent_variable_decoding (slice_header_state,log2_max_frame_num_minus4, + log2_max_pic_order_cnt_lsb_minus4,BitStream_buffer_output, + dependent_variable_len,dependent_variable_decoding_output); + input [3:0] slice_header_state; + input [3:0] log2_max_frame_num_minus4; + input [3:0] log2_max_pic_order_cnt_lsb_minus4; + input [15:0] BitStream_buffer_output; + output [3:0] dependent_variable_len; + output [9:0] dependent_variable_decoding_output; + reg [3:0] dependent_variable_len; + reg [9:0] dependent_variable_decoding_output; + + always @ (slice_header_state or log2_max_frame_num_minus4 or log2_max_pic_order_cnt_lsb_minus4) + if (slice_header_state == `frame_num_s) + dependent_variable_len <= log2_max_frame_num_minus4 + 4; + else if (slice_header_state == `pic_order_cnt_lsb_s) + dependent_variable_len <= log2_max_pic_order_cnt_lsb_minus4 + 4; + else + dependent_variable_len <= 0; + + always @ (slice_header_state or dependent_variable_len or BitStream_buffer_output) + if (slice_header_state == `frame_num_s || slice_header_state == `pic_order_cnt_lsb_s) + case (dependent_variable_len) + 4 :dependent_variable_decoding_output <= {6'b0,BitStream_buffer_output[15:12]}; + 5 :dependent_variable_decoding_output <= {5'b0,BitStream_buffer_output[15:11]}; + 6 :dependent_variable_decoding_output <= {4'b0,BitStream_buffer_output[15:10]}; + 7 :dependent_variable_decoding_output <= {3'b0,BitStream_buffer_output[15:9]}; + 8 :dependent_variable_decoding_output <= {2'b0,BitStream_buffer_output[15:8]}; + 9 :dependent_variable_decoding_output <= {1'b0,BitStream_buffer_output[15:7]}; + 10:dependent_variable_decoding_output <= BitStream_buffer_output[15:6]; + default:dependent_variable_decoding_output <= 0; + endcase + else + dependent_variable_decoding_output <= 0; +endmodule + + + diff --git a/demo_chip_rtl/rtl/nova/trunk/src/end_of_blk_decoding.v b/demo_chip_rtl/rtl/nova/trunk/src/end_of_blk_decoding.v new file mode 100644 index 0000000..e92989c --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/end_of_blk_decoding.v @@ -0,0 +1,64 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : end_of_blk_decoding.v +// Generated : June 12, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Decoding end_of_one_residual_block signal for 1 cycle duration +// 1)for BitStream_parser_FSM to update signals such as i4x4 and direct state switch +// 2)for nC_decoding to update LumaLevel/ChromaLevel CurrMb,mbAddrA,mbAddrB +// Decoding end_of_residual signal for 1 cycle duration +// 1)for nC_decoding to update general control regs such as Luma_8x8_AllZeroCoeff_mbAddrA,Luma_8x8_AllZeroCoeff_mbAddrB_reg,Chroma_8x8_AllZeroCoeff_mbAddrA,Chroma_8x8_AllZeroCoeff_mbAddrB_reg +// 2)Note:for P_skip MBs,their general control regs as *8x8_ALLZeroCoeff* are directly controlled by the state instead of end_of_residual signal +//------------------------------------------------------------------------------------------------- +// Revise log +// 1. March 24,2006 +// Add signal end_of_NonZeroCoeff_CAVLC for IQIT to update res_AC/res_DC/... signals. +// end_of_NonZeroCoeff_CAVLC:combinational logic,active one cycle at the end of CAVLC decoding of one non zero coefficient residual. +// 2. March 29,2006 +// Add signal lumaDC_IsAllZero,ChromaDC_Cb_IsAllZero,ChromaDC_Cr_IsAllZero to deal with special case:zero DC coeff,but non-zero AC coeff +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module end_of_blk_decoding (reset_n,cavlc_decoder_state, + TotalCoeff,i_TotalCoeff,end_of_one_residual_block,end_of_NonZeroCoeff_CAVLC + ); + input reset_n; + input [3:0] cavlc_decoder_state; + input [4:0] TotalCoeff; + input [3:0] i_TotalCoeff; + output end_of_one_residual_block; + output end_of_NonZeroCoeff_CAVLC; + + reg end_of_one_residual_block; + reg end_of_NonZeroCoeff_CAVLC; + reg lumaDC_IsAllZero; + reg ChromaDC_Cb_IsAllZero; + reg ChromaDC_Cr_IsAllZero; + + always @ (reset_n or cavlc_decoder_state or TotalCoeff or i_TotalCoeff) + if (reset_n == 0) + end_of_one_residual_block <= 0; + else if (cavlc_decoder_state == `NumCoeffTrailingOnes_LUT && TotalCoeff == 0) + end_of_one_residual_block <= 1; + else if (cavlc_decoder_state == `LevelRunCombination && i_TotalCoeff == 0) + end_of_one_residual_block <= 1; + else + end_of_one_residual_block <= 0; + + always @ (reset_n or cavlc_decoder_state or i_TotalCoeff) + if (reset_n == 0) + end_of_NonZeroCoeff_CAVLC <= 0; + else if (cavlc_decoder_state == `LevelRunCombination && i_TotalCoeff == 0) + end_of_NonZeroCoeff_CAVLC <= 1; + else + end_of_NonZeroCoeff_CAVLC <= 0; + +endmodule \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/exp_golomb_decoding.v b/demo_chip_rtl/rtl/nova/trunk/src/exp_golomb_decoding.v new file mode 100644 index 0000000..660a92d --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/exp_golomb_decoding.v @@ -0,0 +1,152 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : exp_golomb_decoding.v +// Generated : June 6, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Exp-Golomb code decoding +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module exp_golomb_decoding (reset_n,heading_one_pos,BitStream_buffer_output,num_ref_idx_l0_active_minus1, + slice_header_state,slice_data_state,mb_pred_state,sub_mb_pred_state, + seq_parameter_set_state,pic_parameter_set_state,exp_golomb_decoding_output,exp_golomb_len); + input reset_n; + input [3:0] heading_one_pos; + input [15:0] BitStream_buffer_output; + input [2:0] num_ref_idx_l0_active_minus1; + input [3:0] slice_header_state; + input [3:0] slice_data_state; + input [2:0] mb_pred_state; + input [1:0] sub_mb_pred_state; + input [3:0] seq_parameter_set_state; + input [3:0] pic_parameter_set_state; + output [7:0] exp_golomb_decoding_output; + output [3:0] exp_golomb_len; + + reg [7:0] exp_golomb_decoding_output; + reg [3:0] exp_golomb_len; + + parameter rst_exp_golomb_sel = 2'b00; + parameter ue = 2'b01; + parameter se = 2'b10; + parameter te = 2'b11; + + reg [7:0] codeNum; + reg [1:0] exp_golomb_sel; + + always @ (exp_golomb_sel or heading_one_pos or BitStream_buffer_output) + if (exp_golomb_sel != rst_exp_golomb_sel) + case (heading_one_pos) + 0:codeNum <= 0; + 1:codeNum <= {6'b0,BitStream_buffer_output[14:13]} - 1; + 2:codeNum <= {5'b0,BitStream_buffer_output[13:11]} - 1; + 3:codeNum <= {4'b0,BitStream_buffer_output[12:9]} - 1; + 4:codeNum <= {3'b0,BitStream_buffer_output[11:7]} - 1; + 5:codeNum <= {2'b0,BitStream_buffer_output[10:5]} - 1; + 6:codeNum <= {1'b0,BitStream_buffer_output[9:3]} - 1; + 7:codeNum <= BitStream_buffer_output[8:1] - 1; + default:codeNum <= 0; + endcase + else + codeNum <= 0; + + wire [2:0] te_range; + assign te_range = num_ref_idx_l0_active_minus1 + 1; + always @ (exp_golomb_sel or heading_one_pos or te_range) + case (exp_golomb_sel) + ue,se:exp_golomb_len <= (heading_one_pos << 1) + 1; + te :exp_golomb_len <= (te_range == 2)? 1:((heading_one_pos << 1) + 1); + default:exp_golomb_len <= 0; + endcase + + wire [7:0] codeNum_se_tmp; + assign codeNum_se_tmp = codeNum >> 1; + always @ (exp_golomb_sel or codeNum or codeNum_se_tmp or te_range) + case (exp_golomb_sel) + ue:exp_golomb_decoding_output <= codeNum; + se: + case (codeNum[0]) + 1:exp_golomb_decoding_output <= (codeNum + 1) >> 1; + 0:exp_golomb_decoding_output <= ~codeNum_se_tmp + 1; + endcase + te: + if (te_range == 2) exp_golomb_decoding_output <= (codeNum == 0)? 8'd0:8'd1; + else exp_golomb_decoding_output <= codeNum; + default:exp_golomb_decoding_output <= 0; + endcase + + always @ (reset_n or slice_header_state or slice_data_state or mb_pred_state or sub_mb_pred_state or + seq_parameter_set_state or pic_parameter_set_state) + if (reset_n == 0) + exp_golomb_sel <= rst_exp_golomb_sel; + else if (slice_header_state != `rst_slice_header) + case (slice_header_state) + `first_mb_in_slice_s :exp_golomb_sel <= ue; + `slice_type_s :exp_golomb_sel <= ue; + `pic_parameter_set_id_slice_header_s:exp_golomb_sel <= ue; + `idr_pic_id_s :exp_golomb_sel <= ue; + `slice_qp_delta_s :exp_golomb_sel <= se; + `disable_deblocking_filter_idc_s :exp_golomb_sel <= ue; + `slice_alpha_c0_offset_div2_s :exp_golomb_sel <= se; + `slice_beta_offset_div2_s :exp_golomb_sel <= ue; + default :exp_golomb_sel <= rst_exp_golomb_sel; + endcase + else if (slice_data_state != `rst_slice_data) + case (slice_data_state) + `mb_skip_run_s :exp_golomb_sel <= ue; + `mb_type_s :exp_golomb_sel <= ue; + `sub_mb_pred: + case (sub_mb_pred_state) + `sub_mb_type_s :exp_golomb_sel <= ue; + `sub_ref_idx_l0_s:exp_golomb_sel <= te; + `sub_mvd_l0_s :exp_golomb_sel <= se; + default :exp_golomb_sel <= rst_exp_golomb_sel; + endcase + `mb_pred: + case (mb_pred_state) + `intra_chroma_pred_mode_s:exp_golomb_sel <= ue; + `ref_idx_l0_s :exp_golomb_sel <= te; + `mvd_l0_s :exp_golomb_sel <= se; + default :exp_golomb_sel <= rst_exp_golomb_sel; + endcase + `coded_block_pattern_s :exp_golomb_sel <= ue; + `mb_qp_delta_s :exp_golomb_sel <= se; + default :exp_golomb_sel <= rst_exp_golomb_sel; + endcase + else if (seq_parameter_set_state != `rst_seq_parameter_set) + case (seq_parameter_set_state) + `seq_parameter_set_id_sps_s :exp_golomb_sel <= ue; + `log2_max_frame_num_minus4_s :exp_golomb_sel <= ue; + `pic_order_cnt_type_s :exp_golomb_sel <= ue; + `log2_max_pic_order_cnt_lsb_minus4_s:exp_golomb_sel <= ue; + `num_ref_frames_s :exp_golomb_sel <= ue; + `pic_width_in_mbs_minus1_s :exp_golomb_sel <= ue; + `pic_height_in_map_units_minus1_s :exp_golomb_sel <= ue; + default :exp_golomb_sel <= rst_exp_golomb_sel; + endcase + else if (pic_parameter_set_state != `rst_pic_parameter_set) + case (pic_parameter_set_state) + `pic_parameter_set_id_pps_s :exp_golomb_sel <= ue; + `seq_parameter_set_id_pps_s :exp_golomb_sel <= ue; + `num_slice_groups_minus1_s :exp_golomb_sel <= ue; + `num_ref_idx_l0_active_minus1_pps_s:exp_golomb_sel <= ue; + `num_ref_idx_l1_active_minus1_pps_s:exp_golomb_sel <= ue; + `pic_init_qp_minus26_s :exp_golomb_sel <= se; + `pic_init_qs_minus26_s :exp_golomb_sel <= se; + `chroma_qp_index_offset_s :exp_golomb_sel <= se; + default :exp_golomb_sel <= rst_exp_golomb_sel; + endcase + else + exp_golomb_sel <= rst_exp_golomb_sel; + +endmodule + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/ext_RAM_ctrl.v b/demo_chip_rtl/rtl/nova/trunk/src/ext_RAM_ctrl.v new file mode 100644 index 0000000..2f9f2fa --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/ext_RAM_ctrl.v @@ -0,0 +1,97 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : ext_frame_RAM1_wrapper.v +// Generated : Nov 28,2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Controller for ext_frame_RAM +// Rread as ref_frame_RAM before Inter Prediction +// Write as dis_frame_RAM after Deblocking Filter +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module ext_RAM_ctrl (clk,reset_n,end_of_one_frame,ref_frame_RAM_rd,ref_frame_RAM_rd_addr,dis_frame_RAM_wr, + dis_frame_RAM_wr_addr,ref_frame_RAM_dout, + ext_frame_RAM0_cs_n,ext_frame_RAM0_wr,ext_frame_RAM0_addr,ext_frame_RAM0_data, + ext_frame_RAM1_cs_n,ext_frame_RAM1_wr,ext_frame_RAM1_addr,ext_frame_RAM1_data); + input clk,reset_n; + input end_of_one_frame; + input ref_frame_RAM_rd; + input [13:0] ref_frame_RAM_rd_addr; + input dis_frame_RAM_wr; + input [13:0] dis_frame_RAM_wr_addr; + //input [31:0] dis_frame_RAM_din; + input [31:0] ext_frame_RAM0_data; + input [31:0] ext_frame_RAM1_data; + + output [31:0] ref_frame_RAM_dout; + + output ext_frame_RAM0_cs_n; + output ext_frame_RAM0_wr; + output [13:0] ext_frame_RAM0_addr; + + output ext_frame_RAM1_cs_n; + output ext_frame_RAM1_wr; + output [13:0] ext_frame_RAM1_addr; + + reg ext_frame_RAM_sel; //0:ext_frame_RAM0 as dis_frame_RAM to be written + //0:ext_frame_RAM1 as ref_frame_RAM to be read + //1:ext_frame_RAM0 as ref_frame_RAM to be read + //1:ext_frame_RAM1 as dis_frame_RAM to be written + always @ (posedge clk) + if (reset_n == 1'b0) + ext_frame_RAM_sel <= 1'b0; + else if (end_of_one_frame) + ext_frame_RAM_sel <= ~ ext_frame_RAM_sel; + + reg [31:0] ref_frame_RAM_dout; + + reg ext_frame_RAM0_cs_n; + reg ext_frame_RAM0_wr; + reg [13:0] ext_frame_RAM0_addr; + + reg ext_frame_RAM1_cs_n; + reg ext_frame_RAM1_wr; + reg [13:0] ext_frame_RAM1_addr; + + always @ (ext_frame_RAM_sel or + ref_frame_RAM_rd or ref_frame_RAM_rd_addr or ext_frame_RAM0_data or ext_frame_RAM1_data or + dis_frame_RAM_wr or dis_frame_RAM_wr_addr) + case (ext_frame_RAM_sel) + 1'b0: + begin + //ext_frame_RAM0 as dis_frame_RAM to be written + ext_frame_RAM0_cs_n <= !dis_frame_RAM_wr; ext_frame_RAM0_wr <= dis_frame_RAM_wr; + ext_frame_RAM0_addr <= dis_frame_RAM_wr_addr; + + //ext_frame_RAM1 as ref_frame_RAM to be read + ext_frame_RAM1_cs_n <= !ref_frame_RAM_rd; ext_frame_RAM1_wr <= 1'b0; + ext_frame_RAM1_addr <= ref_frame_RAM_rd_addr; + + ref_frame_RAM_dout <= ext_frame_RAM1_data; + end + 1'b1: + begin + //ext_frame_RAM0 as ref_frame_RAM to be read + ext_frame_RAM0_cs_n <= !ref_frame_RAM_rd; ext_frame_RAM0_wr <= 1'b0; + ext_frame_RAM0_addr <= ref_frame_RAM_rd_addr; + + //ext_frame_RAM1 as dis_frame_RAM to be written + ext_frame_RAM1_cs_n <= !dis_frame_RAM_wr; ext_frame_RAM1_wr <= dis_frame_RAM_wr; + ext_frame_RAM1_addr <= dis_frame_RAM_wr_addr; + + ref_frame_RAM_dout <= ext_frame_RAM0_data; + end + endcase + //assign ext_frame_RAM0_data = (!ext_frame_RAM_sel && dis_frame_RAM_wr)? dis_frame_RAM_din:32'bz; + //assign ext_frame_RAM1_data = ( ext_frame_RAM_sel && dis_frame_RAM_wr)? dis_frame_RAM_din:32'bz; +endmodule + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/ext_frame_RAM0_wrapper.v b/demo_chip_rtl/rtl/nova/trunk/src/ext_frame_RAM0_wrapper.v new file mode 100644 index 0000000..ee62bce --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/ext_frame_RAM0_wrapper.v @@ -0,0 +1,135 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : ext_frame_RAM0_wrapper.v +// Generated : April 23,2006 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// SRAM beha model for external RAM tween reconstruction and deblocking filter (9504x32bit) +// Sync Read,Sync Write +//------------------------------------------------------------------------------------------------- +// Revise log +// 1.July 23,2006 +// Change the ext_frame_RAM0 from async read to sync read. +// +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module ext_frame_RAM0_wrapper (clk,reset_n,ext_frame_RAM0_cs_n,ext_frame_RAM0_wr,ext_frame_RAM0_addr,dis_frame_RAM_din,ext_frame_RAM0_data, + pic_num,slice_header_s6); + input clk; + input reset_n; + input ext_frame_RAM0_cs_n; + input ext_frame_RAM0_wr; + input [13:0] ext_frame_RAM0_addr; + input [31:0] dis_frame_RAM_din; + input [5:0] pic_num; + input slice_header_s6; + output [31:0] ext_frame_RAM0_data; + + reg [31:0] ext_frame_RAM0 [0:9503]; + reg [31:0] ext_frame_RAM0_data; + + always @ (posedge clk) + if (!ext_frame_RAM0_cs_n && ext_frame_RAM0_wr) + ext_frame_RAM0[ext_frame_RAM0_addr] <= dis_frame_RAM_din; + + //assign ext_frame_RAM0_data = (!ext_frame_RAM0_cs_n && !ext_frame_RAM0_wr)? ext_frame_RAM0[ext_frame_RAM0_addr]:32'bz; + always @ (posedge clk) + if (!ext_frame_RAM0_cs_n && !ext_frame_RAM0_wr) + ext_frame_RAM0_data <= ext_frame_RAM0[ext_frame_RAM0_addr]; + + + // synopsys translate_off + integer tracefile_display; + integer tracefile_verify; + integer mb_num; + integer j; + reg [31:0] luma_out0,luma_out1,luma_out2,luma_out3; + reg [31:0] Cb_out0,Cb_out1; + reg [31:0] Cr_out0,Cr_out1; + reg [8:0] pic_num_ext; + + parameter display = 1; + parameter verify = 1; + + always @ (negedge reset_n or pic_num) + if (reset_n == 1'b0) + pic_num_ext <= 0; + else + pic_num_ext <= pic_num_ext + 1; + + + always @ (posedge clk) + if (slice_header_s6 == 1'b1 && pic_num[0] == 1'b1) + begin + if (display == 1'b1) //display + begin + tracefile_display = $fopen("nova_display.log","a"); + for (j= 0; j < 9504; j= j + 1) + begin + $fdisplay (tracefile_display,"%h",ext_frame_RAM0[j]); + end + $fclose(tracefile_display); + end + if (verify == 1'b1) //verify + begin + tracefile_verify = $fopen("nova_MB_output.log","a"); + for (mb_num = 0;mb_num < 99; mb_num = mb_num + 1) + begin + $fdisplay (tracefile_verify,"-------------------------------------------"); + $fdisplay (tracefile_verify," Pic_num = %3d,MB_num = %3d",pic_num_ext - 1,mb_num); + $fdisplay (tracefile_verify,"-------------------------------------------"); + $fdisplay (tracefile_verify," luma 16x16 block:"); + for (j = 0; j < 16; j = j + 1) + begin + luma_out0 = ext_frame_RAM0[(mb_num/11)*704+(mb_num%11)*4+j*44]; + luma_out1 = ext_frame_RAM0[(mb_num/11)*704+(mb_num%11)*4+j*44+1]; + luma_out2 = ext_frame_RAM0[(mb_num/11)*704+(mb_num%11)*4+j*44+2]; + luma_out3 = ext_frame_RAM0[(mb_num/11)*704+(mb_num%11)*4+j*44+3]; + + $fdisplay (tracefile_verify," %3H %3H %3H %3H | %3H %3H %3H %3H | %3H %3H %3H %3H | %3H %3H %3H %3H", + luma_out0[7:0],luma_out0[15:8],luma_out0[23:16],luma_out0[31:24], + luma_out1[7:0],luma_out1[15:8],luma_out1[23:16],luma_out1[31:24], + luma_out2[7:0],luma_out2[15:8],luma_out2[23:16],luma_out2[31:24], + luma_out3[7:0],luma_out3[15:8],luma_out3[23:16],luma_out3[31:24]); + + if (j == 3 || j == 7 || j == 11) + $fdisplay (tracefile_verify, ""); + end + $fdisplay (tracefile_verify," Chroma Cb 8x8 block:"); + for (j = 0; j < 8; j = j + 1) + begin + Cb_out0 = ext_frame_RAM0[6336+(mb_num/11)*176+(mb_num%11)*2+j*22]; + Cb_out1 = ext_frame_RAM0[6336+(mb_num/11)*176+(mb_num%11)*2+j*22+1]; + + $fdisplay (tracefile_verify, " %3H %3H %3H %3H | %3H %3H %3H %3H", + Cb_out0[7:0],Cb_out0[15:8],Cb_out0[23:16],Cb_out0[31:24], + Cb_out1[7:0],Cb_out1[15:8],Cb_out1[23:16],Cb_out1[31:24]); + if (j == 3) + $fdisplay (tracefile_verify, ""); + end + $fdisplay (tracefile_verify," Chroma Cr 8x8 block:"); + for (j = 0; j < 8; j = j + 1) + begin + Cr_out0 = ext_frame_RAM0[7920+(mb_num/11)*176+(mb_num%11)*2+j*22]; + Cr_out1 = ext_frame_RAM0[7920+(mb_num/11)*176+(mb_num%11)*2+j*22+1]; + + $fdisplay (tracefile_verify, " %3H %3H %3H %3H | %3H %3H %3H %3H", + Cr_out0[7:0],Cr_out0[15:8],Cr_out0[23:16],Cr_out0[31:24], + Cr_out1[7:0],Cr_out1[15:8],Cr_out1[23:16],Cr_out1[31:24]); + if (j == 3) + $fdisplay (tracefile_verify, ""); + end + end + $fclose(tracefile_verify); + end + end + // synopsys translate_on +endmodule \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/ext_frame_RAM1_wrapper.v b/demo_chip_rtl/rtl/nova/trunk/src/ext_frame_RAM1_wrapper.v new file mode 100644 index 0000000..16e0ad4 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/ext_frame_RAM1_wrapper.v @@ -0,0 +1,134 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : ext_frame_RAM1_wrapper.v +// Generated : April 23,2006 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// SRAM beha model for external RAM tween reconstruction and deblocking filter (9504x32bit) +// Sync Read,Sync Write +//------------------------------------------------------------------------------------------------- +// Revise log +// 1.July 23,2006 +// Change the ext_frame_RAM1 from async read to sync read. +// +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module ext_frame_RAM1_wrapper (clk,reset_n,ext_frame_RAM1_cs_n,ext_frame_RAM1_wr,ext_frame_RAM1_addr,dis_frame_RAM_din,ext_frame_RAM1_data, + pic_num,slice_header_s6); + input clk; + input reset_n; + input ext_frame_RAM1_cs_n; + input ext_frame_RAM1_wr; + input [13:0] ext_frame_RAM1_addr; + input [31:0] dis_frame_RAM_din; + input [5:0] pic_num; + input slice_header_s6; + output [31:0] ext_frame_RAM1_data; + + reg [31:0] ext_frame_RAM1 [0:9503]; + reg [31:0] ext_frame_RAM1_data; + + always @ (posedge clk) + if (!ext_frame_RAM1_cs_n && ext_frame_RAM1_wr) + ext_frame_RAM1[ext_frame_RAM1_addr] <= dis_frame_RAM_din; + + //assign ext_frame_RAM1_data = (!ext_frame_RAM1_cs_n && !ext_frame_RAM1_wr)? ext_frame_RAM1[ext_frame_RAM1_addr]:32'bz; + + always @ (posedge clk) + if (!ext_frame_RAM1_cs_n && !ext_frame_RAM1_wr) + ext_frame_RAM1_data <= ext_frame_RAM1[ext_frame_RAM1_addr]; + + // synopsys translate_off + integer tracefile_display; + integer tracefile_verify; + integer mb_num; + integer j; + reg [31:0] luma_out0,luma_out1,luma_out2,luma_out3; + reg [31:0] Cb_out0,Cb_out1; + reg [31:0] Cr_out0,Cr_out1; + reg [8:0] pic_num_ext; + + parameter display = 1; + parameter verify = 1; + +always @ (negedge reset_n or pic_num) + if (reset_n == 1'b0) + pic_num_ext <= 0; + else + pic_num_ext <= pic_num_ext + 1; + + always @ (posedge clk) + if (slice_header_s6 == 1'b1 && pic_num[0] == 1'b0 && pic_num_ext != 0) + begin + if (display == 1'b1) //display + begin + tracefile_display = $fopen("nova_display.log","a"); + for (j= 0; j < 9504; j= j + 1) + begin + $fdisplay (tracefile_display,"%h",ext_frame_RAM1[j]); + end + $fclose(tracefile_display); + end + if (verify == 1'b1) //verify + begin + tracefile_verify = $fopen("nova_MB_output.log","a"); + for (mb_num = 0;mb_num < 99; mb_num = mb_num + 1) + begin + $fdisplay (tracefile_verify,"-------------------------------------------"); + $fdisplay (tracefile_verify," Pic_num = %3d,MB_num = %3d",pic_num_ext - 1,mb_num); + $fdisplay (tracefile_verify,"-------------------------------------------"); + $fdisplay (tracefile_verify," luma 16x16 block:"); + for (j = 0; j < 16; j = j + 1) + begin + luma_out0 = ext_frame_RAM1[(mb_num/11)*704+(mb_num%11)*4+j*44]; + luma_out1 = ext_frame_RAM1[(mb_num/11)*704+(mb_num%11)*4+j*44+1]; + luma_out2 = ext_frame_RAM1[(mb_num/11)*704+(mb_num%11)*4+j*44+2]; + luma_out3 = ext_frame_RAM1[(mb_num/11)*704+(mb_num%11)*4+j*44+3]; + + $fdisplay (tracefile_verify," %3H %3H %3H %3H | %3H %3H %3H %3H | %3H %3H %3H %3H | %3H %3H %3H %3H", + luma_out0[7:0],luma_out0[15:8],luma_out0[23:16],luma_out0[31:24], + luma_out1[7:0],luma_out1[15:8],luma_out1[23:16],luma_out1[31:24], + luma_out2[7:0],luma_out2[15:8],luma_out2[23:16],luma_out2[31:24], + luma_out3[7:0],luma_out3[15:8],luma_out3[23:16],luma_out3[31:24]); + + if (j == 3 || j == 7 || j == 11) + $fdisplay (tracefile_verify, ""); + end + $fdisplay (tracefile_verify," Chroma Cb 8x8 block:"); + for (j = 0; j < 8; j = j + 1) + begin + Cb_out0 = ext_frame_RAM1[6336+(mb_num/11)*176+(mb_num%11)*2+j*22]; + Cb_out1 = ext_frame_RAM1[6336+(mb_num/11)*176+(mb_num%11)*2+j*22+1]; + + $fdisplay (tracefile_verify, " %3H %3H %3H %3H | %3H %3H %3H %3H", + Cb_out0[7:0],Cb_out0[15:8],Cb_out0[23:16],Cb_out0[31:24], + Cb_out1[7:0],Cb_out1[15:8],Cb_out1[23:16],Cb_out1[31:24]); + if (j == 3) + $fdisplay (tracefile_verify, ""); + end + $fdisplay (tracefile_verify," Chroma Cr 8x8 block:"); + for (j = 0; j < 8; j = j + 1) + begin + Cr_out0 = ext_frame_RAM1[7920+(mb_num/11)*176+(mb_num%11)*2+j*22]; + Cr_out1 = ext_frame_RAM1[7920+(mb_num/11)*176+(mb_num%11)*2+j*22+1]; + + $fdisplay (tracefile_verify, " %3H %3H %3H %3H | %3H %3H %3H %3H", + Cr_out0[7:0],Cr_out0[15:8],Cr_out0[23:16],Cr_out0[31:24], + Cr_out1[7:0],Cr_out1[15:8],Cr_out1[23:16],Cr_out1[31:24]); + if (j == 3) + $fdisplay (tracefile_verify, ""); + end + end + $fclose(tracefile_verify); + end + end + // synopsys translate_on +endmodule \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/heading_one_detector.v b/demo_chip_rtl/rtl/nova/trunk/src/heading_one_detector.v new file mode 100644 index 0000000..f47134a --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/heading_one_detector.v @@ -0,0 +1,60 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : heading_one_detector.v +// Generated : June 6, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Priority based heading one detection +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module heading_one_detector (heading_one_en,BitStream_buffer_output,heading_one_pos); + input heading_one_en; + input [15:0] BitStream_buffer_output; + output [3:0] heading_one_pos; + reg [3:0] heading_one_pos; + + always @ (heading_one_en or BitStream_buffer_output) + if (heading_one_en == 1'b0) + begin + if (BitStream_buffer_output[15] == 1'b1 || BitStream_buffer_output[14] == 1'b1) + begin + if (BitStream_buffer_output[15] == 1'b1) heading_one_pos <= 0; + else heading_one_pos <= 4'd1; + end + else if (BitStream_buffer_output[13] == 1'b1 || BitStream_buffer_output[12] == 1'b1 || + BitStream_buffer_output[11] == 1'b1 || BitStream_buffer_output[10] == 1'b1) + begin + if (BitStream_buffer_output[13] == 1'b1) heading_one_pos <= 4'd2; + else if (BitStream_buffer_output[12] == 1'b1) heading_one_pos <= 4'd3; + else if (BitStream_buffer_output[11] == 1'b1) heading_one_pos <= 4'd4; + else heading_one_pos <= 4'd5; + end + else + begin + if (BitStream_buffer_output[9] == 1'b1) heading_one_pos <= 4'd6; + else if (BitStream_buffer_output[8] == 1'b1) heading_one_pos <= 4'd7; + else if (BitStream_buffer_output[7] == 1'b1) heading_one_pos <= 4'd8; + else if (BitStream_buffer_output[6] == 1'b1) heading_one_pos <= 4'd9; + else if (BitStream_buffer_output[5] == 1'b1) heading_one_pos <= 4'd10; + else if (BitStream_buffer_output[4] == 1'b1) heading_one_pos <= 4'd11; + else if (BitStream_buffer_output[3] == 1'b1) heading_one_pos <= 4'd12; + else if (BitStream_buffer_output[2] == 1'b1) heading_one_pos <= 4'd13; + else if (BitStream_buffer_output[1] == 1'b1) heading_one_pos <= 4'd14; + else heading_one_pos <= 4'd15; + end + end + else + heading_one_pos <= 0; +endmodule + + + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/hybrid_pipeline_ctrl.v b/demo_chip_rtl/rtl/nova/trunk/src/hybrid_pipeline_ctrl.v new file mode 100644 index 0000000..901c367 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/hybrid_pipeline_ctrl.v @@ -0,0 +1,265 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : hybrid_pipeline_ctrl.v +// Generated : Sept 5, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Control 4x4 block level pipeline for reconstruction +// Receive the 1cycle end_of_xxx signal(combinational) +// Generated the 1cycle trigger_xxx signal +//------------------------------------------------------------------------------------------------- +// Revise log +// 1.April 11,2006 +// Modify the 1cycle trigger_xxx signal from registers to combinational logic to save decoding clock cycles +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module hybrid_pipeline_ctrl (clk,reset_n,mb_num_h,mb_num_v,blk4x4_rec_counter,CodedBlockPatternLuma,CodedBlockPatternChroma, + mb_type_general,slice_data_state,residual_state,TotalCoeff,Is_skip_run_entry,skip_mv_calc, + end_of_one_residual_block,end_of_DCBlk_IQIT,end_of_ACBlk4x4_IQIT,end_of_one_blk4x4_intra,end_of_one_blk4x4_inter, + end_of_one_blk4x4_sum,end_of_MB_DF,disable_DF, + + curr_CBPLuma_IsZero,end_of_MB_DEC,trigger_CAVLC,trigger_blk4x4_intra_pred, + trigger_blk4x4_inter_pred,trigger_blk4x4_rec_sum); + input clk,reset_n; + input [3:0] mb_num_h; + input [3:0] mb_num_v; + input [4:0] blk4x4_rec_counter; + input [3:0] CodedBlockPatternLuma; + input [1:0] CodedBlockPatternChroma; + input [3:0] mb_type_general; + input [3:0] slice_data_state; + input [3:0] residual_state; + input [4:0] TotalCoeff; + input Is_skip_run_entry; + input skip_mv_calc; + input end_of_one_residual_block; + input end_of_DCBlk_IQIT; + input end_of_ACBlk4x4_IQIT; + input end_of_one_blk4x4_intra,end_of_one_blk4x4_inter,end_of_one_blk4x4_sum; + input end_of_MB_DF; + input disable_DF; + + output curr_CBPLuma_IsZero; + output end_of_MB_DEC; + output trigger_CAVLC; + output trigger_blk4x4_intra_pred,trigger_blk4x4_inter_pred; + output trigger_blk4x4_rec_sum; + + //change trigger_blk4x4_intra_pred from combination to reg + reg trigger_CAVLC; //combination + reg trigger_blk4x4_intra_pred; //reg + reg trigger_blk4x4_inter_pred; //reg + reg trigger_blk4x4_rec_sum; //combination + + //CBPLuma only make sense for residual_state == LumaLevel_s + //CBPLuma is derived to help judge whether res_blk4x4_IsAllZero caused by CodedBlockPattern != 4'b1111 + reg curr_CBPLuma_IsZero; + always @ (blk4x4_rec_counter or CodedBlockPatternLuma) + if (blk4x4_rec_counter < 16) + case (blk4x4_rec_counter[3:2]) + 2'b00:curr_CBPLuma_IsZero <= !CodedBlockPatternLuma[0]; + 2'b01:curr_CBPLuma_IsZero <= !CodedBlockPatternLuma[1]; + 2'b10:curr_CBPLuma_IsZero <= !CodedBlockPatternLuma[2]; + 2'b11:curr_CBPLuma_IsZero <= !CodedBlockPatternLuma[3]; + endcase + else + curr_CBPLuma_IsZero <= 0; + //--------------------------------------------------------------------------------- + //signals to trigger: + // 1.4x4 blk CAVLC + // 2.4x4 Intra Prediction + // 3.4x4 Inter Prediction + // 4.4x4 reconstruction sum + // 5.16x16 deblocking filter + // All the trigger_xxx signals are generated by sequential logic + //--------------------------------------------------------------------------------- + + //1. trigger_CAVLC: when reconstruction is dealing with skip_run or zero residual (construction + // only from inter/intra prediction) blocks,CAVLC decoder,as well as whole bitstream parsing FSM, + // needs to be stalled and wait until the reconstruction process of previous + + always @ (slice_data_state or residual_state or mb_type_general[3:2] or CodedBlockPatternLuma + or CodedBlockPatternChroma or end_of_one_residual_block or end_of_DCBlk_IQIT or end_of_one_blk4x4_sum + or blk4x4_rec_counter or TotalCoeff or curr_CBPLuma_IsZero) + // Entry + if (slice_data_state == `residual && residual_state == `rst_residual) + begin + if (mb_type_general[3:2] == 2'b10) //Intra16x16:first block must be DC + trigger_CAVLC <= 1'b1; + else if (CodedBlockPatternLuma[0] == 1'b0) //First 8x8 block has no residuals + trigger_CAVLC <= 1'b0; + else //normal case + trigger_CAVLC <= 1'b1; + end + // End of one DC + else if ((residual_state == `Intra16x16DCLevel_s || residual_state == `ChromaDCLevel_Cb_s || + residual_state == `ChromaDCLevel_Cr_s) && ((end_of_one_residual_block && TotalCoeff == 0)|| end_of_DCBlk_IQIT)) + case (residual_state) + `Intra16x16DCLevel_s: //end of luma DC + trigger_CAVLC <= (CodedBlockPatternLuma[0] == 1'b0)? 1'b0:1'b1; + `ChromaDCLevel_Cb_s: //end of chroma DC Cb,trigger chroma DC Cr now! + trigger_CAVLC <= 1'b1; + `ChromaDCLevel_Cr_s: //end of chroma DC Cr + trigger_CAVLC <= (CodedBlockPatternChroma == 2'b01)? 1'b0:1'b1; + default:trigger_CAVLC <= 1'b0; + endcase + // End of skip or normal + else if (end_of_one_blk4x4_sum) + begin + if (slice_data_state == `skip_run_duration) + trigger_CAVLC <= 1'b0; + else + case (blk4x4_rec_counter) + 0,1,2,4,5,6,8,9,10,12,13,14:trigger_CAVLC <= (curr_CBPLuma_IsZero)? 1'b0:1'b1; + 3 :trigger_CAVLC <= (CodedBlockPatternLuma[1])? 1'b1:1'b0; + 7 :trigger_CAVLC <= (CodedBlockPatternLuma[2])? 1'b1:1'b0; + 11:trigger_CAVLC <= (CodedBlockPatternLuma[3])? 1'b1:1'b0; + 15:trigger_CAVLC <= (CodedBlockPatternChroma == 0)? 1'b0:1'b1; + 23:trigger_CAVLC <= 1'b0; + default:trigger_CAVLC <= (CodedBlockPatternChroma == 2)? 1'b1:1'b0; + endcase + end + else + trigger_CAVLC <= 1'b0; + + //end_of_MB_rec:end of one MB reconstruction + wire end_of_MB_rec; + assign end_of_MB_rec = (blk4x4_rec_counter == 5'd23 && end_of_one_blk4x4_sum == 1'b1)? 1'b1:1'b0; + + //MB_needs_DF: identify whether this MB needs to be deblocking filtered + reg MB_needs_DF; + always @ (posedge clk) + if (reset_n == 1'b0) + MB_needs_DF <= 1'b0; + else if (end_of_MB_DEC == 1'b1 && !disable_DF) + MB_needs_DF <= 1'b1; + else if (end_of_MB_DEC == 1'b1 && disable_DF) + MB_needs_DF <= 1'b0; + //MB_rec_DF_align:latch the first arrival of end_of_MB_rec and end_of_MB_DF + reg MB_rec_DF_align; + always @ (posedge clk) + if (reset_n == 1'b0) + MB_rec_DF_align <= 1'b0; + else if (end_of_MB_DEC) + MB_rec_DF_align <= 1'b0; + else if (MB_needs_DF && (end_of_MB_rec || end_of_MB_DF == 1'b1)) + MB_rec_DF_align <= 1'b1; + + + //end_of_MB_DEC:end of one macroblock decoding (end of both reconstruction and previous MB's deblocking + // (if previous MB needs deblocking)),generated by combinational logic + reg end_of_MB_DEC; + always @ (MB_needs_DF or end_of_MB_rec or end_of_MB_DF or MB_rec_DF_align or mb_num_h or mb_num_v) + if (MB_needs_DF == 1'b1) + begin + if (end_of_MB_rec && end_of_MB_DF) //arrive simultaneously + end_of_MB_DEC <= 1'b1; + else if (MB_rec_DF_align == 1'b1 && (end_of_MB_rec || end_of_MB_DF)) + end_of_MB_DEC <= 1'b1; + else if (mb_num_h == 0 && mb_num_v == 0 && end_of_MB_rec)//first MB has no correspinding DF process + end_of_MB_DEC <= 1'b1; + else + end_of_MB_DEC <= 1'b0; + end + else + end_of_MB_DEC <= (end_of_MB_rec)? 1'b1:1'b0; + + //2. trigger_blk4x4_intra_pred + wire trigger_blk4x4_intra_pred_tmp; + assign trigger_blk4x4_intra_pred_tmp = (mb_type_general[3] && ((slice_data_state == `residual && + residual_state == `rst_residual) || (end_of_one_blk4x4_sum && blk4x4_rec_counter != 23)))? 1'b1:1'b0; + + always @ (posedge clk) + if (reset_n == 1'b0) + trigger_blk4x4_intra_pred <= 1'b0; + else + trigger_blk4x4_intra_pred <= trigger_blk4x4_intra_pred_tmp; + + //3. trigger_blk4x4_inter_pred + always @ (posedge clk) + if (reset_n == 1'b0) + trigger_blk4x4_inter_pred <= 1'b0; + //For skip_run_duration + // 1.trigger inter pred when entering skip_run_duration after mb_skip_run_s state + else if (Is_skip_run_entry) + trigger_blk4x4_inter_pred <= 1'b1; + // 2.trigger inter pred during skip_run_duration + else if (slice_data_state == `skip_run_duration) + begin + if (skip_mv_calc) + trigger_blk4x4_inter_pred <= 1'b1; + else + trigger_blk4x4_inter_pred <= (end_of_one_blk4x4_sum && blk4x4_rec_counter != 23)? 1'b1:1'b0; + end + //For normal case:inside residual_state + // 1.entry + else if (slice_data_state == `residual && residual_state == `rst_residual && !mb_type_general[3]) + trigger_blk4x4_inter_pred <= 1'b1; + // 2.end of normal + else if (end_of_one_blk4x4_sum && blk4x4_rec_counter != 23 && !mb_type_general[3]) + trigger_blk4x4_inter_pred <= 1'b1; + else + trigger_blk4x4_inter_pred <= 1'b0; + + //4. trigger reconstruction sum + // Need to align the output of residual(IQIT) and predition(inter/intra) + wire end_of_one_blk4x4_pred; + wire end_of_one_blk4x4_res; //end of one zero or non-zero AC blk4x4 IQIT (NOT DC!) + reg blk4x4_res_pred_align; + + assign end_of_one_blk4x4_pred = (end_of_one_blk4x4_inter || end_of_one_blk4x4_intra); + assign end_of_one_blk4x4_res = (((residual_state == `Intra16x16ACLevel_s || residual_state == `LumaLevel_s || + residual_state == `ChromaACLevel_Cb_s || residual_state == `ChromaACLevel_Cr_s) && + (end_of_one_residual_block && TotalCoeff == 0)) || end_of_ACBlk4x4_IQIT)? 1'b1:1'b0; + + //align the completion of prediction and residual decoding + always @ (posedge clk) + if (reset_n == 1'b0) + blk4x4_res_pred_align <= 0; + else if (trigger_blk4x4_rec_sum == 1'b1) + blk4x4_res_pred_align <= 1'b0; + else if (end_of_one_blk4x4_res && end_of_one_blk4x4_pred) //arrive simultaneously,no align + blk4x4_res_pred_align <= 1'b0; + else if (end_of_one_blk4x4_res || end_of_one_blk4x4_pred) + blk4x4_res_pred_align <= 1'b1; + + + always @ (slice_data_state or residual_state or curr_CBPLuma_IsZero or blk4x4_res_pred_align or + end_of_one_blk4x4_pred or end_of_one_blk4x4_res) + if (slice_data_state == `skip_run_duration) + trigger_blk4x4_rec_sum <= (end_of_one_blk4x4_pred)? 1'b1:1'b0; + // Normal + else if (residual_state == `Intra16x16ACLevel_s || residual_state == `LumaLevel_s || + residual_state == `ChromaACLevel_Cb_s || residual_state == `ChromaACLevel_Cr_s) + begin + if (curr_CBPLuma_IsZero) + trigger_blk4x4_rec_sum <= (blk4x4_res_pred_align)? 1'b1:end_of_one_blk4x4_pred; + else if (end_of_one_blk4x4_res && end_of_one_blk4x4_pred) //arrive simultaneously + trigger_blk4x4_rec_sum <= 1'b1; + else if ((end_of_one_blk4x4_res || end_of_one_blk4x4_pred) && blk4x4_res_pred_align) + trigger_blk4x4_rec_sum <= 1'b1; + else + trigger_blk4x4_rec_sum <= 1'b0; + end + // zero blocks + else if (residual_state == `Intra16x16ACLevel_0_s || residual_state == `LumaLevel_0_s + || residual_state == `ChromaACLevel_0_s) + trigger_blk4x4_rec_sum <= (end_of_one_blk4x4_pred || blk4x4_res_pred_align)? 1'b1:1'b0; + else + trigger_blk4x4_rec_sum <= 1'b0; + + //5.trigger Deblocking Filter + //assign trigger_MB_DF = (end_of_MB_DEC == 1'b1 && !disable_DF)? 1'b1:1'b0; + +endmodule + + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/level_decoding.v b/demo_chip_rtl/rtl/nova/trunk/src/level_decoding.v new file mode 100644 index 0000000..e87a141 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/level_decoding.v @@ -0,0 +1,206 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : level_decoding.v +// Generated : June 9, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Devive the level_prefix,level_suffix,suffixLength,levelSuffixSize,levelCode +// In systemC,levelSuffixSize is decoded @LevelPrefix,in RTL,now changed to @LevelSuffix +// level_suffix[7:0],levelCode[7:0],level[8:0] +// 1. level_abs_tmp[8:0]:|levelCode+2| or |-levelCode-1| | reg +// 2. level_abs [7:0]:level_abs_tmp >> 1 and latched, used for suffixLength calculation | wire +// 3. level_tmp [8:0]:2's complement, equals (levelCode+2)>>1 or (-levelCode-1)>>1 | wire +// 4. level_0 ~ level_15:According to i_level,level_tmp is assigned to level_[i_level] | reg +// level_0 ~ level_15 are 2's complement +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module level_decoding (clk,reset_n,cavlc_decoder_state,heading_one_pos,suffix_length_initialized,i_level, + TotalCoeff,TrailingOnes,BitStream_buffer_output, + levelSuffixSize, + level_0,level_1,level_2, level_3, level_4, level_5, level_6, level_7, + level_8,level_9,level_10,level_11,level_12,level_13,level_14,level_15); + input clk,reset_n; + input [3:0] cavlc_decoder_state; + input [3:0] heading_one_pos; + input suffix_length_initialized; + input [3:0] i_level; + input [4:0] TotalCoeff; + input [1:0] TrailingOnes; + input [15:0] BitStream_buffer_output; + output [3:0] levelSuffixSize; + output [8:0] level_0,level_1,level_2,level_3,level_4,level_5,level_6,level_7; + output [8:0] level_8,level_9,level_10,level_11,level_12,level_13,level_14,level_15; + + reg [3:0] levelSuffixSize; + reg [8:0] level_0,level_1,level_2,level_3,level_4,level_5,level_6,level_7; + reg [8:0] level_8,level_9,level_10,level_11,level_12,level_13,level_14,level_15; + + reg [3:0] level_prefix; + reg [3:0] suffixLength; + reg [11:0] level_suffix; + reg [8:0] levelCode; + reg [8:0] level_tmp; + reg [7:0] level_abs; + + wire [8:0] levelCode_tmp; + + //@LevelPrefix,latch the result + always @ (posedge clk) + if (reset_n == 0) + level_prefix <= 0; + else if (cavlc_decoder_state == `LevelPrefix) + level_prefix <= heading_one_pos; + //@LevelPrefix,latch the result + always @ (posedge clk) + if (reset_n == 0) + suffixLength <= 0; + else if (cavlc_decoder_state == `LevelPrefix) + begin + if (suffix_length_initialized == 1'b0) + suffixLength <= (TotalCoeff > 10 && TrailingOnes < 3)? 4'd1:4'd0; + //Revise log:March 26,2006 + //else if (suffixLength == 0 && ((level_abs > (8'd3 << (suffixLength - 1))) && suffixLength < 6)) + else if (suffixLength == 0 && level_abs > 8'd3) + suffixLength <= 4'd2; + else if (suffixLength == 0) + suffixLength <= 4'd1; + else if ((level_abs > (8'd3 << (suffixLength - 1))) && suffixLength < 6) + suffixLength <= suffixLength + 1; + end + //@LevelSuffix,temporary result + always @ (cavlc_decoder_state or level_prefix or suffixLength) + if (cavlc_decoder_state == `LevelSuffix) + begin + if (level_prefix == 14 && suffixLength == 0) + levelSuffixSize <= 4; + else if (level_prefix == 4'd15) + levelSuffixSize <= 4'd12; + else + levelSuffixSize <= suffixLength; + end + else + levelSuffixSize <= 0; + //@LevelSuffix,temporay result + always @ (cavlc_decoder_state or levelSuffixSize or BitStream_buffer_output) + if (cavlc_decoder_state == `LevelSuffix) + begin + if (levelSuffixSize == 0) + level_suffix <= 0; + else + case (levelSuffixSize) + 1 :level_suffix <= {11'b0,BitStream_buffer_output[15]}; + 2 :level_suffix <= {10'b0,BitStream_buffer_output[15:14]}; + 3 :level_suffix <= {9'b0,BitStream_buffer_output[15:13]}; + 4 :level_suffix <= {8'b0,BitStream_buffer_output[15:12]}; + 5 :level_suffix <= {7'b0,BitStream_buffer_output[15:11]}; + 6 :level_suffix <= {6'b0,BitStream_buffer_output[15:10]}; + 7 :level_suffix <= {5'b0,BitStream_buffer_output[15:9]}; + 8 :level_suffix <= {4'b0,BitStream_buffer_output[15:8]}; + 9 :level_suffix <= {3'b0,BitStream_buffer_output[15:7]}; + 10:level_suffix <= {2'b0,BitStream_buffer_output[15:6]}; + 11:level_suffix <= {1'b0,BitStream_buffer_output[15:5]}; + 12:level_suffix <= BitStream_buffer_output[15:4]; + default:level_suffix <= 0; + endcase + end + else + level_suffix <= 0; + + assign levelCode_tmp = (cavlc_decoder_state == `LevelSuffix)? ((level_prefix << suffixLength) + level_suffix):0; + + always @ (cavlc_decoder_state or level_prefix or suffixLength or i_level or TrailingOnes or levelCode_tmp) + if (cavlc_decoder_state == `LevelSuffix) + begin + if (level_prefix == 15 && suffixLength == 0 && i_level == {2'b0,TrailingOnes} && TrailingOnes < 3) + levelCode <= levelCode_tmp + 17; + else if (level_prefix == 15 && suffixLength == 0) + levelCode <= levelCode_tmp + 15; + else if (i_level == {2'b0,TrailingOnes} && TrailingOnes < 3) + levelCode <= levelCode_tmp + 2; + else + levelCode <= levelCode_tmp; + end + else + levelCode <= 0; + //We need an additional "level_abs" signal here in order to upgrade suffixLength for next codeword,but for + //trailingones,no need to do so since abs(+1/-1) will never greater than (3<<(suffixLength-1)). + + //level_abs_tmp:absolute value of level + reg [8:0] level_abs_tmp; + always @ (cavlc_decoder_state or levelCode) + if (cavlc_decoder_state == `LevelSuffix) + begin + if (levelCode[0] == 1'b0) //even + level_abs_tmp <= levelCode + 2; + else + level_abs_tmp <= levelCode + 1; + end + else + level_abs_tmp <= 0; + + //level_abs:latched absolute value of level,for upgrading of suffixLength + always @ (posedge clk) + if (reset_n == 0) + level_abs <= 0; + else if (cavlc_decoder_state == `LevelSuffix) + level_abs <= level_abs_tmp[8:1]; + + always @ (cavlc_decoder_state or levelCode or level_abs_tmp) + if (cavlc_decoder_state == `LevelSuffix) + begin + if (levelCode[0] == 1'b0) //even + level_tmp <= {1'b0,level_abs_tmp[8:1]}; + else + level_tmp <= {1'b1,~levelCode[8:1]}; + end + else + level_tmp <= 0; + + always @ (posedge clk) + if (reset_n == 0) + begin + level_0 <= 0; level_1 <= 0; level_2 <= 0; level_3 <= 0; + level_4 <= 0; level_5 <= 0; level_6 <= 0; level_7 <= 0; + level_8 <= 0; level_9 <= 0; level_10<= 0; level_11<= 0; + level_12<= 0; level_13<= 0; level_14<= 0; level_15<= 0; + end + else if (cavlc_decoder_state == `TrailingOnesSignFlag) + begin + level_0 <= (BitStream_buffer_output[15] == 0)? 9'b000000001:9'b111111111; + if (TrailingOnes > 1) + level_1 <= (BitStream_buffer_output[14] == 0)? 9'b000000001:9'b111111111; + if (TrailingOnes == 3) + level_2 <= (BitStream_buffer_output[13] == 0)? 9'b000000001:9'b111111111; + end + else if (cavlc_decoder_state == `LevelSuffix) + case (i_level) + 0 :level_0 <= level_tmp; + 1 :level_1 <= level_tmp; + 2 :level_2 <= level_tmp; + 3 :level_3 <= level_tmp; + 4 :level_4 <= level_tmp; + 5 :level_5 <= level_tmp; + 6 :level_6 <= level_tmp; + 7 :level_7 <= level_tmp; + 8 :level_8 <= level_tmp; + 9 :level_9 <= level_tmp; + 10:level_10<= level_tmp; + 11:level_11<= level_tmp; + 12:level_12<= level_tmp; + 13:level_13<= level_tmp; + 14:level_14<= level_tmp; + 15:level_15<= level_tmp; + endcase +endmodule + + + + diff --git a/demo_chip_rtl/rtl/nova/trunk/src/nC_decoding.v b/demo_chip_rtl/rtl/nova/trunk/src/nC_decoding.v new file mode 100644 index 0000000..98fd884 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/nC_decoding.v @@ -0,0 +1,761 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : nC_decoding.v +// Generated : May 18, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Devive the number of none-zero coeff during nC decoding for TotalCoeff & TrailingOnes LUT +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module nC_decoding (clk,reset_n,gclk_end_of_MB_DEC, + cavlc_decoder_state,residual_state,slice_data_state, + mb_num_h,mb_num_v,i8x8,i4x4,i4x4_CbCr,CodedBlockPatternLuma,CodedBlockPatternChroma, + LumaLevel_mbAddrB_dout,ChromaLevel_Cb_mbAddrB_dout,ChromaLevel_Cr_mbAddrB_dout, + end_of_one_residual_block,TotalCoeff, + + nC, + Luma_8x8_AllZeroCoeff_mbAddrA,LumaLevel_mbAddrA, + LumaLevel_CurrMb0,LumaLevel_CurrMb1,LumaLevel_CurrMb2,LumaLevel_CurrMb3, + LumaLevel_mbAddrB_cs_n,LumaLevel_mbAddrB_wr_n,LumaLevel_mbAddrB_rd_addr, + LumaLevel_mbAddrB_wr_addr,LumaLevel_mbAddrB_din, + ChromaLevel_Cb_mbAddrB_cs_n,ChromaLevel_Cb_mbAddrB_wr_n,ChromaLevel_Cb_mbAddrB_rd_addr, + ChromaLevel_Cb_mbAddrB_wr_addr,ChromaLevel_Cb_mbAddrB_din, + ChromaLevel_Cr_mbAddrB_cs_n,ChromaLevel_Cr_mbAddrB_wr_n,ChromaLevel_Cr_mbAddrB_rd_addr, + ChromaLevel_Cr_mbAddrB_wr_addr,ChromaLevel_Cr_mbAddrB_din); + + input clk,reset_n; + input gclk_end_of_MB_DEC; + input [3:0] cavlc_decoder_state; + input [3:0] residual_state; + input [3:0] slice_data_state; + input [3:0] mb_num_h; + input [3:0] mb_num_v; + input [1:0] i8x8,i4x4; + input [1:0] i4x4_CbCr; + input [3:0] CodedBlockPatternLuma; + input [1:0] CodedBlockPatternChroma; + input [19:0] LumaLevel_mbAddrB_dout; + input [9:0] ChromaLevel_Cb_mbAddrB_dout,ChromaLevel_Cr_mbAddrB_dout; + input end_of_one_residual_block; + input [4:0] TotalCoeff; + + output [4:0] nC; + output [1:0] Luma_8x8_AllZeroCoeff_mbAddrA; + output [19:0] LumaLevel_mbAddrA; + output [19:0] LumaLevel_CurrMb0,LumaLevel_CurrMb1,LumaLevel_CurrMb2,LumaLevel_CurrMb3; + output LumaLevel_mbAddrB_cs_n,LumaLevel_mbAddrB_wr_n; + output [3:0] LumaLevel_mbAddrB_rd_addr,LumaLevel_mbAddrB_wr_addr; + output [19:0]LumaLevel_mbAddrB_din; + output ChromaLevel_Cb_mbAddrB_cs_n,ChromaLevel_Cb_mbAddrB_wr_n; + output [3:0] ChromaLevel_Cb_mbAddrB_rd_addr,ChromaLevel_Cb_mbAddrB_wr_addr; + output [9:0] ChromaLevel_Cb_mbAddrB_din; + output ChromaLevel_Cr_mbAddrB_cs_n,ChromaLevel_Cr_mbAddrB_wr_n; + output [3:0] ChromaLevel_Cr_mbAddrB_rd_addr,ChromaLevel_Cr_mbAddrB_wr_addr; + output [9:0] ChromaLevel_Cr_mbAddrB_din; + + reg [4:0] nC; + reg LumaLevel_mbAddrB_cs_n,LumaLevel_mbAddrB_wr_n; + reg [3:0] LumaLevel_mbAddrB_rd_addr,LumaLevel_mbAddrB_wr_addr; + reg [19:0]LumaLevel_mbAddrB_din; + reg ChromaLevel_Cb_mbAddrB_cs_n,ChromaLevel_Cb_mbAddrB_wr_n; + reg [3:0] ChromaLevel_Cb_mbAddrB_rd_addr,ChromaLevel_Cb_mbAddrB_wr_addr; + reg [9:0] ChromaLevel_Cb_mbAddrB_din; + reg ChromaLevel_Cr_mbAddrB_cs_n,ChromaLevel_Cr_mbAddrB_wr_n; + reg [3:0] ChromaLevel_Cr_mbAddrB_rd_addr,ChromaLevel_Cr_mbAddrB_wr_addr; + reg [9:0] ChromaLevel_Cr_mbAddrB_din; + + reg nA_availability,nB_availability; + reg nA_availability_reg,nB_availability_reg; + reg [4:0] nA,nB; + reg [19:0] LumaLevel_mbAddrA; + reg [19:0] LumaLevel_CurrMb0,LumaLevel_CurrMb1,LumaLevel_CurrMb2,LumaLevel_CurrMb3; + reg [19:0] ChromaLevel_Cb_CurrMb; + reg [9:0] ChromaLevel_Cb_mbAddrA; + reg [19:0] ChromaLevel_Cr_CurrMb; + reg [9:0] ChromaLevel_Cr_mbAddrA; + reg [1:0] Luma_8x8_AllZeroCoeff_mbAddrA; + reg [0:21] Luma_8x8_AllZeroCoeff_mbAddrB_reg; + reg [0:1] Luma_8x8_AllZeroCoeff_mbAddrB; + reg Chroma_8x8_AllZeroCoeff_mbAddrA; + reg [10:0] Chroma_8x8_AllZeroCoeff_mbAddrB_reg; + reg Chroma_8x8_AllZeroCoeff_mbAddrB; + + always @ (mb_num_h or Luma_8x8_AllZeroCoeff_mbAddrB_reg) + case (mb_num_h) + 0 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[0:1]; + 1 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[2:3]; + 2 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[4:5]; + 3 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[6:7]; + 4 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[8:9]; + 5 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[10:11]; + 6 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[12:13]; + 7 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[14:15]; + 8 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[16:17]; + 9 :Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[18:19]; + 10:Luma_8x8_AllZeroCoeff_mbAddrB <= Luma_8x8_AllZeroCoeff_mbAddrB_reg[20:21]; + default:Luma_8x8_AllZeroCoeff_mbAddrB <= 0; + endcase + always @ (mb_num_h or Chroma_8x8_AllZeroCoeff_mbAddrB_reg) + case (mb_num_h) + 0 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[0]; + 1 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[1]; + 2 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[2]; + 3 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[3]; + 4 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[4]; + 5 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[5]; + 6 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[6]; + 7 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[7]; + 8 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[8]; + 9 :Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[9]; + 10:Chroma_8x8_AllZeroCoeff_mbAddrB <= Chroma_8x8_AllZeroCoeff_mbAddrB_reg[10]; + default:Chroma_8x8_AllZeroCoeff_mbAddrB <= 0; + endcase + //---------------------------- + //Update 8x8_AllZero registers + //---------------------------- + always @ (posedge gclk_end_of_MB_DEC or negedge reset_n) + if (reset_n == 0) + Luma_8x8_AllZeroCoeff_mbAddrA <= 0; + else if (slice_data_state == `skip_run_duration) + Luma_8x8_AllZeroCoeff_mbAddrA <= 0; + else //update 8x8_AllZero reg when finished one MB residual parsing + begin + Luma_8x8_AllZeroCoeff_mbAddrA[0] <= (CodedBlockPatternLuma[1] == 0)? 1'b0:1'b1; + Luma_8x8_AllZeroCoeff_mbAddrA[1] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1; + end + always @ (posedge gclk_end_of_MB_DEC or negedge reset_n) + if (reset_n == 0) + Luma_8x8_AllZeroCoeff_mbAddrB_reg <= 0; + else if (slice_data_state == `skip_run_duration) + case (mb_num_h) + 0 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[0:1] <= 0; + 1 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[2:3] <= 0; + 2 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[4:5] <= 0; + 3 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[6:7] <= 0; + 4 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[8:9] <= 0; + 5 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[10:11] <= 0; + 6 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[12:13] <= 0; + 7 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[14:15] <= 0; + 8 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[16:17] <= 0; + 9 :Luma_8x8_AllZeroCoeff_mbAddrB_reg[18:19] <= 0; + 10:Luma_8x8_AllZeroCoeff_mbAddrB_reg[20:21] <= 0; + endcase + else //update 8x8_AllZero reg when finished one MB residual parsing + case (mb_num_h) + 0: + begin + Luma_8x8_AllZeroCoeff_mbAddrB_reg [0] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1; + Luma_8x8_AllZeroCoeff_mbAddrB_reg [1] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1; + end + 1: + begin + Luma_8x8_AllZeroCoeff_mbAddrB_reg [2] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1; + Luma_8x8_AllZeroCoeff_mbAddrB_reg [3] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1; + end + 2: + begin + Luma_8x8_AllZeroCoeff_mbAddrB_reg [4] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1; + Luma_8x8_AllZeroCoeff_mbAddrB_reg [5] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1; + end + 3: + begin + Luma_8x8_AllZeroCoeff_mbAddrB_reg [6] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1; + Luma_8x8_AllZeroCoeff_mbAddrB_reg [7] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1; + end + 4: + begin + Luma_8x8_AllZeroCoeff_mbAddrB_reg [8] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1; + Luma_8x8_AllZeroCoeff_mbAddrB_reg [9] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1; + end + 5: + begin + Luma_8x8_AllZeroCoeff_mbAddrB_reg [10] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1; + Luma_8x8_AllZeroCoeff_mbAddrB_reg [11] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1; + end + 6: + begin + Luma_8x8_AllZeroCoeff_mbAddrB_reg [12] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1; + Luma_8x8_AllZeroCoeff_mbAddrB_reg [13] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1; + end + 7: + begin + Luma_8x8_AllZeroCoeff_mbAddrB_reg [14] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1; + Luma_8x8_AllZeroCoeff_mbAddrB_reg [15] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1; + end + 8: + begin + Luma_8x8_AllZeroCoeff_mbAddrB_reg [16] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1; + Luma_8x8_AllZeroCoeff_mbAddrB_reg [17] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1; + end + 9: + begin + Luma_8x8_AllZeroCoeff_mbAddrB_reg [18] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1; + Luma_8x8_AllZeroCoeff_mbAddrB_reg [19] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1; + end + 10: + begin + Luma_8x8_AllZeroCoeff_mbAddrB_reg [20] <= (CodedBlockPatternLuma[2] == 0)? 1'b0:1'b1; + Luma_8x8_AllZeroCoeff_mbAddrB_reg [21] <= (CodedBlockPatternLuma[3] == 0)? 1'b0:1'b1; + end + endcase + always @ (posedge gclk_end_of_MB_DEC or negedge reset_n) + if (reset_n == 0) + Chroma_8x8_AllZeroCoeff_mbAddrA <= 0; + else if (slice_data_state == `skip_run_duration) + Chroma_8x8_AllZeroCoeff_mbAddrA <= 0; + else //update 8x8_AllZero reg when finished one MB residual parsing + Chroma_8x8_AllZeroCoeff_mbAddrA <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1; + always @ (posedge gclk_end_of_MB_DEC or negedge reset_n) + if (reset_n == 0) + Chroma_8x8_AllZeroCoeff_mbAddrB_reg <= 0; + else if (slice_data_state == `skip_run_duration) + case (mb_num_h) + 0 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[0] <= 0; + 1 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[1] <= 0; + 2 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[2] <= 0; + 3 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[3] <= 0; + 4 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[4] <= 0; + 5 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[5] <= 0; + 6 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[6] <= 0; + 7 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[7] <= 0; + 8 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[8] <= 0; + 9 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[9] <= 0; + 10:Chroma_8x8_AllZeroCoeff_mbAddrB_reg[10] <= 0; + endcase + else if (mb_num_v != 8) + case (mb_num_h) + 0 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[0] <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1; + 1 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[1] <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1; + 2 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[2] <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1; + 3 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[3] <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1; + 4 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[4] <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1; + 5 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[5] <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1; + 6 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[6] <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1; + 7 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[7] <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1; + 8 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[8] <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1; + 9 :Chroma_8x8_AllZeroCoeff_mbAddrB_reg[9] <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1; + 10:Chroma_8x8_AllZeroCoeff_mbAddrB_reg[10] <= (CodedBlockPatternChroma != 2 )? 1'b0:1'b1; + endcase + //------------------- + //nA_availability + //------------------- + always @ (posedge clk) + if (reset_n == 0) + nA_availability_reg <= 0; + else if (cavlc_decoder_state == `nAnB_decoding_s) + nA_availability_reg <= nA_availability; + always @ (reset_n or cavlc_decoder_state or residual_state or mb_num_h or i8x8 or i4x4 or i4x4_CbCr or nA_availability_reg) + if (reset_n == 1'b0) + nA_availability <= 1'b0; + else if (cavlc_decoder_state == `nAnB_decoding_s) + case (residual_state) + //luma + `Intra16x16DCLevel_s:nA_availability <= (mb_num_h == 0)? 1'b0:1'b1; + `Intra16x16ACLevel_s,`LumaLevel_s: + if ((i8x8 == 0 || i8x8 == 2) && (i4x4 == 0 || i4x4 == 2)) + nA_availability <= (mb_num_h == 0)? 1'b0:1'b1; + else + nA_availability <= 1'b1; + //chroma + `ChromaACLevel_Cb_s,`ChromaACLevel_Cr_s: + nA_availability <= (mb_num_h == 0 && i4x4_CbCr[0] == 0)? 1'b0:1'b1; + default:nA_availability <= 1'b0; + endcase + else + nA_availability <= nA_availability_reg; + //------------------- + //nB_availability + //------------------- + always @ (posedge clk) + if (reset_n == 0) + nB_availability_reg <= 0; + else if (cavlc_decoder_state == `nAnB_decoding_s) + nB_availability_reg <= nB_availability; + always @ (reset_n or cavlc_decoder_state or residual_state or mb_num_v or i8x8 or i4x4 or i4x4_CbCr + or nB_availability_reg) + if (reset_n == 1'b0) + nB_availability <= 1'b0; + else if (cavlc_decoder_state == `nAnB_decoding_s) + case (residual_state) + //luma + `Intra16x16DCLevel_s:nB_availability <= (mb_num_v == 0)? 1'b0:1'b1; + `Intra16x16ACLevel_s,`LumaLevel_s: + if ((i8x8 == 0 || i8x8 == 1) && (i4x4 == 0 || i4x4 == 1)) + nB_availability <= (mb_num_v == 0)? 1'b0:1'b1; + else + nB_availability <= 1'b1; + //chroma + `ChromaACLevel_Cb_s,`ChromaACLevel_Cr_s: + nB_availability <= (mb_num_v == 0 && i4x4_CbCr[1] == 0)? 1'b0:1'b1; + default:nB_availability <= 1'b0; + endcase + else + nB_availability <= nB_availability_reg; + //------------ + //Derive nA + //------------ + always @ (posedge clk) + if (reset_n == 0) + nA <= 0; + else if (cavlc_decoder_state == `nAnB_decoding_s && nA_availability == 1) + case (residual_state) + //luma + `Intra16x16DCLevel_s:nA <= (Luma_8x8_AllZeroCoeff_mbAddrA[0] == 0)? 0:LumaLevel_mbAddrA[4:0]; + `Intra16x16ACLevel_s,`LumaLevel_s: + case (i8x8) + 0: + case (i4x4) + 0:nA <= (Luma_8x8_AllZeroCoeff_mbAddrA[0] == 0)? 0:LumaLevel_mbAddrA[4:0]; + 1:nA <= LumaLevel_CurrMb0[4:0]; + 2:nA <= (Luma_8x8_AllZeroCoeff_mbAddrA[0] == 0)? 0:LumaLevel_mbAddrA[9:5]; + 3:nA <= LumaLevel_CurrMb0[14:10]; + endcase + 1: + case (i4x4) + 0:nA <= (CodedBlockPatternLuma[0] == 0)? 0:LumaLevel_CurrMb0[9:5]; + 1:nA <= LumaLevel_CurrMb1[4:0]; + 2:nA <= (CodedBlockPatternLuma[0] == 0)? 0:LumaLevel_CurrMb0[19:15]; + 3:nA <= LumaLevel_CurrMb1[14:10]; + endcase + 2: + case (i4x4) + 0:nA <= (Luma_8x8_AllZeroCoeff_mbAddrA[1] == 0)? 0:LumaLevel_mbAddrA[14:10]; + 1:nA <= LumaLevel_CurrMb2[4:0]; + 2:nA <= (Luma_8x8_AllZeroCoeff_mbAddrA[1] == 0)? 0:LumaLevel_mbAddrA[19:15]; + 3:nA <= LumaLevel_CurrMb2[14:10]; + endcase + 3: + case (i4x4) + 0:nA <= (CodedBlockPatternLuma[2] == 0)? 0:LumaLevel_CurrMb2[9:5]; + 1:nA <= LumaLevel_CurrMb3[4:0]; + 2:nA <= (CodedBlockPatternLuma[2] == 0)? 0:LumaLevel_CurrMb2[19:15]; + 3:nA <= LumaLevel_CurrMb3[14:10]; + endcase + endcase + //chroma + `ChromaACLevel_Cb_s: + case (i4x4_CbCr) + 2'b00:nA <= (Chroma_8x8_AllZeroCoeff_mbAddrA == 0)? 0:ChromaLevel_Cb_mbAddrA[4:0]; + 2'b10:nA <= (Chroma_8x8_AllZeroCoeff_mbAddrA == 0)? 0:ChromaLevel_Cb_mbAddrA[9:5]; + 2'b01:nA <= (CodedBlockPatternChroma != 2)? 0:ChromaLevel_Cb_CurrMb[4:0]; + 2'b11:nA <= (CodedBlockPatternChroma != 2)? 0:ChromaLevel_Cb_CurrMb[14:10]; + endcase + `ChromaACLevel_Cr_s: + case (i4x4_CbCr) + 2'b00:nA <= (Chroma_8x8_AllZeroCoeff_mbAddrA == 0)? 0:ChromaLevel_Cr_mbAddrA[4:0]; + 2'b10:nA <= (Chroma_8x8_AllZeroCoeff_mbAddrA == 0)? 0:ChromaLevel_Cr_mbAddrA[9:5]; + 2'b01:nA <= (CodedBlockPatternChroma != 2)? 0:ChromaLevel_Cr_CurrMb[4:0]; + 2'b11:nA <= (CodedBlockPatternChroma != 2)? 0:ChromaLevel_Cr_CurrMb[14:10]; + endcase + endcase + else if (cavlc_decoder_state == `nAnB_decoding_s && nA_availability == 0) + nA <= 0; + //------------ + //Derive nB + //------------ + always @ (posedge clk) + if (reset_n == 0) + nB <= 0; + else if (cavlc_decoder_state == `nAnB_decoding_s && nB_availability == 1) + case (residual_state) + `Intra16x16DCLevel_s: + nB <= (Luma_8x8_AllZeroCoeff_mbAddrB[0] == 0)? 0:LumaLevel_mbAddrB_dout[19:15]; + `Intra16x16ACLevel_s,`LumaLevel_s: + case (i8x8) + 0: + case (i4x4) + 0:nB <= (Luma_8x8_AllZeroCoeff_mbAddrB[0] == 0)? 0:LumaLevel_mbAddrB_dout[19:15]; + 1:nB <= (Luma_8x8_AllZeroCoeff_mbAddrB[0] == 0)? 0:LumaLevel_mbAddrB_dout[14:10]; + 2:nB <= LumaLevel_CurrMb0[4:0]; + 3:nB <= LumaLevel_CurrMb0[9:5]; + endcase + 1: + case (i4x4) + 0:nB <= (Luma_8x8_AllZeroCoeff_mbAddrB[1] == 0)? 0:LumaLevel_mbAddrB_dout[9:5]; + 1:nB <= (Luma_8x8_AllZeroCoeff_mbAddrB[1] == 0)? 0:LumaLevel_mbAddrB_dout[4:0]; + 2:nB <= LumaLevel_CurrMb1[4:0]; + 3:nB <= LumaLevel_CurrMb1[9:5]; + endcase + 2: + case (i4x4) + 0:nB <= (CodedBlockPatternLuma[0] == 0)? 0:LumaLevel_CurrMb0[14:10]; + 1:nB <= (CodedBlockPatternLuma[0] == 0)? 0:LumaLevel_CurrMb0[19:15]; + 2:nB <= LumaLevel_CurrMb2[4:0]; + 3:nB <= LumaLevel_CurrMb2[9:5]; + endcase + 3: + case (i4x4) + 0:nB <= (CodedBlockPatternLuma[1] == 0)? 0:LumaLevel_CurrMb1[14:10]; + 1:nB <= (CodedBlockPatternLuma[1] == 0)? 0:LumaLevel_CurrMb1[19:15]; + 2:nB <= LumaLevel_CurrMb3[4:0]; + 3:nB <= LumaLevel_CurrMb3[9:5]; + endcase + endcase + `ChromaACLevel_Cb_s: + case (i4x4_CbCr) + 0:nB <= (Chroma_8x8_AllZeroCoeff_mbAddrB == 0)? 0:ChromaLevel_Cb_mbAddrB_dout[9:5]; + 1:nB <= (Chroma_8x8_AllZeroCoeff_mbAddrB == 0)? 0:ChromaLevel_Cb_mbAddrB_dout[4:0]; + 2:nB <= ChromaLevel_Cb_CurrMb[4:0]; + 3:nB <= ChromaLevel_Cb_CurrMb[9:5]; + endcase + `ChromaACLevel_Cr_s: + case (i4x4_CbCr) + 0:nB <= (Chroma_8x8_AllZeroCoeff_mbAddrB == 0)? 0:ChromaLevel_Cr_mbAddrB_dout[9:5]; + 1:nB <= (Chroma_8x8_AllZeroCoeff_mbAddrB == 0)? 0:ChromaLevel_Cr_mbAddrB_dout[4:0]; + 2:nB <= ChromaLevel_Cr_CurrMb[4:0]; + 3:nB <= ChromaLevel_Cr_CurrMb[9:5]; + endcase + default: nB <= 0; + endcase + else if (cavlc_decoder_state == `nAnB_decoding_s && nB_availability == 0) + nB <= 0; + //------------ + //Derive nC + //------------ + always @ (posedge clk) + if (reset_n == 0) + nC <= 0; + else if (cavlc_decoder_state == `nC_decoding_s) + begin + if (residual_state == `ChromaDCLevel_Cb_s || residual_state == `ChromaDCLevel_Cr_s) + nC <= 5'b11111; + else if (nA_availability == 1 && nB_availability == 1) + nC <= (nA + nB + 1) >> 1; + else + nC <= nA + nB; + end + //----------------------- + //LumaLevel_CurrMb write + //----------------------- + always @ (posedge clk) + if (reset_n == 0) + begin + LumaLevel_CurrMb0 <= 0; LumaLevel_CurrMb1 <= 0; + LumaLevel_CurrMb2 <= 0; LumaLevel_CurrMb3 <= 0; + end + else if (end_of_one_residual_block == 1 && (residual_state == `Intra16x16ACLevel_s || + residual_state == `LumaLevel_s)) + case (i8x8) + 0: + case (i4x4) + 0:LumaLevel_CurrMb0[4:0] <= TotalCoeff; + 1:LumaLevel_CurrMb0[9:5] <= TotalCoeff; + 2:LumaLevel_CurrMb0[14:10] <= TotalCoeff; + 3:LumaLevel_CurrMb0[19:15] <= TotalCoeff; + endcase + 1: + case (i4x4) + 0:LumaLevel_CurrMb1[4:0] <= TotalCoeff; + 1:LumaLevel_CurrMb1[9:5] <= TotalCoeff; + 2:LumaLevel_CurrMb1[14:10] <= TotalCoeff; + 3:LumaLevel_CurrMb1[19:15] <= TotalCoeff; + endcase + 2: + case (i4x4) + 0:LumaLevel_CurrMb2[4:0] <= TotalCoeff; + 1:LumaLevel_CurrMb2[9:5] <= TotalCoeff; + 2:LumaLevel_CurrMb2[14:10] <= TotalCoeff; + 3:LumaLevel_CurrMb2[19:15] <= TotalCoeff; + endcase + 3: + case (i4x4) + 0:LumaLevel_CurrMb3[4:0] <= TotalCoeff; + 1:LumaLevel_CurrMb3[9:5] <= TotalCoeff; + 2:LumaLevel_CurrMb3[14:10] <= TotalCoeff; + 3:LumaLevel_CurrMb3[19:15] <= TotalCoeff; + endcase + endcase + //--------------------------- + //ChromaLevel_Cb_CurrMb write + //--------------------------- + always @ (posedge clk) + if (reset_n == 0) + ChromaLevel_Cb_CurrMb <= 0; + else if (end_of_one_residual_block == 1 && residual_state == `ChromaACLevel_Cb_s) + case (i4x4_CbCr) + 0:ChromaLevel_Cb_CurrMb[4:0] <= TotalCoeff; + 1:ChromaLevel_Cb_CurrMb[9:5] <= TotalCoeff; + 2:ChromaLevel_Cb_CurrMb[14:10] <= TotalCoeff; + 3:ChromaLevel_Cb_CurrMb[19:15] <= TotalCoeff; + endcase + //--------------------------- + //ChromaLevel_Cr_CurrMb write + //--------------------------- + always @ (posedge clk) + if (reset_n == 0) + ChromaLevel_Cr_CurrMb <= 0; + else if (end_of_one_residual_block == 1 && residual_state == `ChromaACLevel_Cr_s) + case (i4x4_CbCr) + 0:ChromaLevel_Cr_CurrMb[4:0] <= TotalCoeff; + 1:ChromaLevel_Cr_CurrMb[9:5] <= TotalCoeff; + 2:ChromaLevel_Cr_CurrMb[14:10] <= TotalCoeff; + 3:ChromaLevel_Cr_CurrMb[19:15] <= TotalCoeff; + endcase + //----------------------- + //LumaLevel_mbAddrA write + //----------------------- + always @ (posedge clk) + if (reset_n == 0) + LumaLevel_mbAddrA <= 0; + else if (end_of_one_residual_block == 1 && (residual_state == `Intra16x16ACLevel_s || residual_state == `LumaLevel_s) && mb_num_h != 10) + case (i8x8) + 1: + case (i4x4) + 1:LumaLevel_mbAddrA[4:0] <= TotalCoeff; + 3:LumaLevel_mbAddrA[9:5] <= TotalCoeff; + endcase + 3: + case (i4x4) + 1:LumaLevel_mbAddrA[14:10] <= TotalCoeff; + 3:LumaLevel_mbAddrA[19:15] <= TotalCoeff; + endcase + endcase + //---------------------------- + //ChromaLevel_Cb_mbAddrA write + //---------------------------- + always @ (posedge clk) + if (reset_n == 0) + ChromaLevel_Cb_mbAddrA <= 0; + else if (end_of_one_residual_block == 1 && residual_state == `ChromaACLevel_Cb_s && mb_num_h != 10) + begin + if (i4x4_CbCr == 1) + ChromaLevel_Cb_mbAddrA[4:0] <= TotalCoeff; + if (i4x4_CbCr == 3) + ChromaLevel_Cb_mbAddrA[9:5] <= TotalCoeff; + end + //---------------------------- + //ChromaLevel_Cr_mbAddrA write + //---------------------------- + always @ (posedge clk) + if (reset_n == 0) + ChromaLevel_Cr_mbAddrA <= 0; + else if (end_of_one_residual_block == 1 && residual_state == `ChromaACLevel_Cr_s && mb_num_h != 10) + begin + if (i4x4_CbCr == 1) + ChromaLevel_Cr_mbAddrA[4:0] <= TotalCoeff; + if (i4x4_CbCr == 3) + ChromaLevel_Cr_mbAddrA[9:5] <= TotalCoeff; + end + //------------------------------ + //LumaLevel_mbAddrB read & write + //------------------------------ + always @ (reset_n or cavlc_decoder_state or residual_state or nB_availability or + Luma_8x8_AllZeroCoeff_mbAddrB or i8x8 or i4x4 or end_of_one_residual_block or + mb_num_v or mb_num_h or CodedBlockPatternLuma or LumaLevel_CurrMb2 or LumaLevel_CurrMb3 or TotalCoeff) + if (reset_n == 0) + begin + LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1; + LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0; + LumaLevel_mbAddrB_din <= 0; + end + //--read-- + else if (cavlc_decoder_state == `nAnB_decoding_s && nB_availability == 1) //read + case (residual_state) + `Intra16x16DCLevel_s: + if (Luma_8x8_AllZeroCoeff_mbAddrB == 0) + begin + LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1; + LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0; + LumaLevel_mbAddrB_din <= 0; + end + else + begin + LumaLevel_mbAddrB_cs_n <= 0; LumaLevel_mbAddrB_wr_n <= 1; + LumaLevel_mbAddrB_rd_addr <= mb_num_h; LumaLevel_mbAddrB_wr_addr <= 0; + LumaLevel_mbAddrB_din <= 0; + end + `Intra16x16ACLevel_s,`LumaLevel_s: + case (i8x8) + 0: + if (Luma_8x8_AllZeroCoeff_mbAddrB[0] == 0) + begin + LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1; + LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0; + LumaLevel_mbAddrB_din <= 0; + end + else + begin + LumaLevel_mbAddrB_cs_n <= 0; LumaLevel_mbAddrB_wr_n <= 1; + LumaLevel_mbAddrB_rd_addr <= mb_num_h; LumaLevel_mbAddrB_wr_addr <= 0; + LumaLevel_mbAddrB_din <= 0; + end + 1: + if (Luma_8x8_AllZeroCoeff_mbAddrB[1] == 0) + begin + LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1; + LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0; + LumaLevel_mbAddrB_din <= 0; + end + else + begin + LumaLevel_mbAddrB_cs_n <= 0; LumaLevel_mbAddrB_wr_n <= 1; + LumaLevel_mbAddrB_rd_addr <= mb_num_h; LumaLevel_mbAddrB_wr_addr <= 0; + LumaLevel_mbAddrB_din <= 0; + end + default: + begin + LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1; + LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0; + LumaLevel_mbAddrB_din <= 0; + end + endcase + default: + begin + LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1; + LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0; + LumaLevel_mbAddrB_din <= 0; + end + endcase + //--write-- + else if ((residual_state == `Intra16x16ACLevel_s || residual_state == `LumaLevel_s) && end_of_one_residual_block == 1 && mb_num_v != 8) + case (CodedBlockPatternLuma[3:2]) + 2'b00: + begin + LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1; + LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0; + LumaLevel_mbAddrB_din <= 0; + end + 2'b10,2'b11: + if (i8x8 == 3 && i4x4 == 3) + begin + LumaLevel_mbAddrB_cs_n <= 0; LumaLevel_mbAddrB_wr_n <= 0; + LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= mb_num_h; + LumaLevel_mbAddrB_din <= (CodedBlockPatternLuma[3:2] == 2'b10)? + {10'b0, LumaLevel_CurrMb3[14:10],TotalCoeff}: + {LumaLevel_CurrMb2[14:10],LumaLevel_CurrMb2[19:15],LumaLevel_CurrMb3[14:10],TotalCoeff}; + end + else + begin + LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1; + LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0; + LumaLevel_mbAddrB_din <= 0; + end + 2'b01: + if (i8x8 == 2 && i4x4 == 3) + begin + LumaLevel_mbAddrB_cs_n <= 0; LumaLevel_mbAddrB_wr_n <= 0; + LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= mb_num_h; + LumaLevel_mbAddrB_din <= {LumaLevel_CurrMb2[14:10],TotalCoeff,10'b0}; + end + else + begin + LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1; + LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0; + LumaLevel_mbAddrB_din <= 0; + end + endcase + else + begin + LumaLevel_mbAddrB_cs_n <= 1; LumaLevel_mbAddrB_wr_n <= 1; + LumaLevel_mbAddrB_rd_addr <= 0; LumaLevel_mbAddrB_wr_addr <= 0; + LumaLevel_mbAddrB_din <= 0; + end + //----------------------------------- + //ChromaLevel_Cb_mbAddrB read & write + //----------------------------------- + always @ (reset_n or cavlc_decoder_state or residual_state or nB_availability or i4x4_CbCr or ChromaLevel_Cb_CurrMb + or Chroma_8x8_AllZeroCoeff_mbAddrB or mb_num_h or mb_num_v or TotalCoeff or end_of_one_residual_block) + if (reset_n == 0) + begin + ChromaLevel_Cb_mbAddrB_cs_n <= 1; ChromaLevel_Cb_mbAddrB_wr_n <= 1; + ChromaLevel_Cb_mbAddrB_rd_addr <= 0; ChromaLevel_Cb_mbAddrB_wr_addr <= 0; + ChromaLevel_Cb_mbAddrB_din <= 0; + end + //--read-- + else if (cavlc_decoder_state == `nAnB_decoding_s && nB_availability == 1 && + residual_state == `ChromaACLevel_Cb_s) + begin + if (i4x4_CbCr[1] == 0 && Chroma_8x8_AllZeroCoeff_mbAddrB == 1) + begin + ChromaLevel_Cb_mbAddrB_cs_n <= 0; ChromaLevel_Cb_mbAddrB_wr_n <= 1; + ChromaLevel_Cb_mbAddrB_rd_addr <= mb_num_h; ChromaLevel_Cb_mbAddrB_wr_addr <= 0; + ChromaLevel_Cb_mbAddrB_din <= 0; + end + else + begin + ChromaLevel_Cb_mbAddrB_cs_n <= 1; ChromaLevel_Cb_mbAddrB_wr_n <= 1; + ChromaLevel_Cb_mbAddrB_rd_addr <= 0; ChromaLevel_Cb_mbAddrB_wr_addr <= 0; + ChromaLevel_Cb_mbAddrB_din <= 0; + end + end + //--write-- + else if (residual_state == `ChromaACLevel_Cb_s && end_of_one_residual_block == 1 && mb_num_v != 8) + begin + if (i4x4_CbCr == 3) + begin + ChromaLevel_Cb_mbAddrB_cs_n <= 0; ChromaLevel_Cb_mbAddrB_wr_n <= 0; + ChromaLevel_Cb_mbAddrB_rd_addr <= 0; ChromaLevel_Cb_mbAddrB_wr_addr <= mb_num_h; + ChromaLevel_Cb_mbAddrB_din <= {ChromaLevel_Cb_CurrMb[14:10],TotalCoeff}; + end + else + begin + ChromaLevel_Cb_mbAddrB_cs_n <= 1; ChromaLevel_Cb_mbAddrB_wr_n <= 1; + ChromaLevel_Cb_mbAddrB_rd_addr <= 0; ChromaLevel_Cb_mbAddrB_wr_addr <= 0; + ChromaLevel_Cb_mbAddrB_din <= 0; + end + end + else + begin + ChromaLevel_Cb_mbAddrB_cs_n <= 1; ChromaLevel_Cb_mbAddrB_wr_n <= 1; + ChromaLevel_Cb_mbAddrB_rd_addr <= 0; ChromaLevel_Cb_mbAddrB_wr_addr <= 0; + ChromaLevel_Cb_mbAddrB_din <= 0; + end + //----------------------------------- + //ChromaLevel_Cr_mbAddrB read & write + //----------------------------------- + always @ (reset_n or cavlc_decoder_state or residual_state or nB_availability or i4x4_CbCr + or ChromaLevel_Cr_CurrMb or Chroma_8x8_AllZeroCoeff_mbAddrB or mb_num_h or mb_num_v or TotalCoeff + or end_of_one_residual_block) + if (reset_n == 0) + begin + ChromaLevel_Cr_mbAddrB_cs_n <= 1; ChromaLevel_Cr_mbAddrB_wr_n <= 1; + ChromaLevel_Cr_mbAddrB_rd_addr <= 0; ChromaLevel_Cr_mbAddrB_wr_addr <= 0; + ChromaLevel_Cr_mbAddrB_din <= 0; + end + //--read-- + else if (cavlc_decoder_state == `nAnB_decoding_s && nB_availability == 1 && residual_state == `ChromaACLevel_Cr_s) //read + begin + if (i4x4_CbCr[1] == 0 && Chroma_8x8_AllZeroCoeff_mbAddrB == 1) + begin + ChromaLevel_Cr_mbAddrB_cs_n <= 0; ChromaLevel_Cr_mbAddrB_wr_n <= 1; + ChromaLevel_Cr_mbAddrB_rd_addr <= mb_num_h; ChromaLevel_Cr_mbAddrB_wr_addr <= 0; + ChromaLevel_Cr_mbAddrB_din <= 0; + end + else + begin + ChromaLevel_Cr_mbAddrB_cs_n <= 1; ChromaLevel_Cr_mbAddrB_wr_n <= 1; + ChromaLevel_Cr_mbAddrB_rd_addr <= 0; ChromaLevel_Cr_mbAddrB_wr_addr <= 0; + ChromaLevel_Cr_mbAddrB_din <= 0; + end + end + //--write-- + else if (residual_state == `ChromaACLevel_Cr_s && end_of_one_residual_block == 1 && mb_num_v != 8) + begin + if (i4x4_CbCr == 3) + begin + ChromaLevel_Cr_mbAddrB_cs_n <= 0; ChromaLevel_Cr_mbAddrB_wr_n <= 0; + ChromaLevel_Cr_mbAddrB_rd_addr <= 0; ChromaLevel_Cr_mbAddrB_wr_addr <= mb_num_h; + ChromaLevel_Cr_mbAddrB_din <= {ChromaLevel_Cr_CurrMb[14:10],TotalCoeff}; + end + else + begin + ChromaLevel_Cr_mbAddrB_cs_n <= 1; ChromaLevel_Cr_mbAddrB_wr_n <= 1; + ChromaLevel_Cr_mbAddrB_rd_addr <= 0; ChromaLevel_Cr_mbAddrB_wr_addr <= 0; + ChromaLevel_Cr_mbAddrB_din <= 0; + end + end + else + begin + ChromaLevel_Cr_mbAddrB_cs_n <= 1; ChromaLevel_Cr_mbAddrB_wr_n <= 1; + ChromaLevel_Cr_mbAddrB_rd_addr <= 0; ChromaLevel_Cr_mbAddrB_wr_addr <= 0; + ChromaLevel_Cr_mbAddrB_din <= 0; + end +endmodule diff --git a/demo_chip_rtl/rtl/nova/trunk/src/nova.v b/demo_chip_rtl/rtl/nova/trunk/src/nova.v new file mode 100644 index 0000000..377b6e6 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/nova.v @@ -0,0 +1,259 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : nova.v +// Generated : Feb 25,2006 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Top module of nova design, including two main blocks: BitStream controller and reconstruction datapath +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module nova (clk,reset_n,BitStream_buffer_input,BitStream_ram_ren,BitStream_ram_addr, + pic_num,pin_disable_DF,freq_ctrl0,freq_ctrl1, + ext_frame_RAM0_cs_n,ext_frame_RAM0_wr,ext_frame_RAM0_addr,ext_frame_RAM0_data, + ext_frame_RAM1_cs_n,ext_frame_RAM1_wr,ext_frame_RAM1_addr,ext_frame_RAM1_data, + dis_frame_RAM_din, + + slice_header_s6 + ); + input clk,reset_n; + input [15:0] BitStream_buffer_input; + input pin_disable_DF; + input freq_ctrl0; + input freq_ctrl1; + + output BitStream_ram_ren; + output [16:0] BitStream_ram_addr; + output [5:0] pic_num; + //---ext_frame_RAM0--- + output ext_frame_RAM0_cs_n; + output ext_frame_RAM0_wr; + output [13:0] ext_frame_RAM0_addr; + //inout [31:0] ext_frame_RAM0_data; + input [31:0] ext_frame_RAM0_data; + + //---ext_frame_RAM1--- + output ext_frame_RAM1_cs_n; + output ext_frame_RAM1_wr; + output [13:0] ext_frame_RAM1_addr; + //inout [31:0] ext_frame_RAM1_data; + input [31:0] ext_frame_RAM1_data; + + output [31:0] dis_frame_RAM_din; + output slice_header_s6; + + wire trigger_CAVLC; + wire end_of_NonZeroCoeff_CAVLC; + wire end_of_DCBlk_IQIT; + wire end_of_one_blk4x4_sum; + wire end_of_MB_DEC; + wire gclk_end_of_MB_DEC; + wire end_of_one_residual_block; + wire end_of_one_frame; + wire Is_skip_run_entry; + wire Is_skip_run_end; + wire skip_mv_calc; + wire [3:0] mb_type_general; + wire [3:0] mb_num_h; + wire [3:0] mb_num_v; + wire NextMB_IsSkip; + wire LowerMB_IsSkip; + wire [4:0] blk4x4_rec_counter; + wire [3:0] slice_data_state; + wire [3:0] residual_state; + wire [3:0] cavlc_decoder_state; + wire [1:0] Intra16x16_predmode; + wire [63:0] Intra4x4_predmode_CurrMb; + wire [1:0] Intra_chroma_predmode; + wire [5:0] QPy; + wire [5:0] QPc; + wire [1:0] i4x4_CbCr; + wire [3:0] slice_alpha_c0_offset_div2; + wire [3:0] slice_beta_offset_div2; + wire [3:0] CodedBlockPatternLuma; + wire [1:0] CodedBlockPatternChroma; + wire [4:0] TotalCoeff; + wire disable_DF; + wire [8:0] coeffLevel_0, coeffLevel_1, coeffLevel_2,coeffLevel_3, coeffLevel_4, coeffLevel_5; + wire [8:0] coeffLevel_6, coeffLevel_7, coeffLevel_8, coeffLevel_9,coeffLevel_10,coeffLevel_11; + wire [8:0] coeffLevel_12,coeffLevel_13,coeffLevel_14,coeffLevel_15; + wire mv_is16x16; + wire [3:0] mv_below8x8; + wire [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3; + wire [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3; + wire [11:0] bs_V0,bs_V1,bs_V2,bs_V3; + wire [11:0] bs_H0,bs_H1,bs_H2,bs_H3; + wire curr_DC_IsZero; + wire end_of_BS_DEC; + + BitStream_controller BitStream_controller ( + .clk(clk), + .reset_n(reset_n), + .freq_ctrl0(freq_ctrl0), + .freq_ctrl1(freq_ctrl1), + .BitStream_buffer_input(BitStream_buffer_input), + .pin_disable_DF(pin_disable_DF), + .trigger_CAVLC(trigger_CAVLC), + .blk4x4_rec_counter(blk4x4_rec_counter), + .end_of_DCBlk_IQIT(end_of_DCBlk_IQIT), + .end_of_one_blk4x4_sum(end_of_one_blk4x4_sum), + .end_of_MB_DEC(end_of_MB_DEC), + .gclk_end_of_MB_DEC(gclk_end_of_MB_DEC), + .curr_DC_IsZero(curr_DC_IsZero), + + .BitStream_ram_ren(BitStream_ram_ren), + .BitStream_ram_addr(BitStream_ram_addr), + .pic_num(pic_num), + .mb_type_general(mb_type_general), + .mb_num_h(mb_num_h), + .mb_num_v(mb_num_v), + .NextMB_IsSkip(NextMB_IsSkip), + .LowerMB_IsSkip(LowerMB_IsSkip), + .slice_data_state(slice_data_state), + .residual_state(residual_state), + .cavlc_decoder_state(cavlc_decoder_state), + .end_of_one_residual_block(end_of_one_residual_block), + .end_of_NonZeroCoeff_CAVLC(end_of_NonZeroCoeff_CAVLC), + .end_of_one_frame(end_of_one_frame), + .Intra16x16_predmode(Intra16x16_predmode), + .Intra4x4_predmode_CurrMb(Intra4x4_predmode_CurrMb), + .Intra_chroma_predmode(Intra_chroma_predmode), + .QPy(QPy), + .QPc(QPc), + .i4x4_CbCr(i4x4_CbCr), + .slice_alpha_c0_offset_div2(slice_alpha_c0_offset_div2), + .slice_beta_offset_div2(slice_beta_offset_div2), + .CodedBlockPatternLuma(CodedBlockPatternLuma), + .CodedBlockPatternChroma(CodedBlockPatternChroma), + .TotalCoeff(TotalCoeff), + .Is_skip_run_entry(Is_skip_run_entry), + .skip_mv_calc(skip_mv_calc), + .disable_DF(disable_DF), + .coeffLevel_0(coeffLevel_0), + .coeffLevel_1(coeffLevel_1), + .coeffLevel_2(coeffLevel_2), + .coeffLevel_3(coeffLevel_3), + .coeffLevel_4(coeffLevel_4), + .coeffLevel_5(coeffLevel_5), + .coeffLevel_6(coeffLevel_6), + .coeffLevel_7(coeffLevel_7), + .coeffLevel_8(coeffLevel_8), + .coeffLevel_9(coeffLevel_9), + .coeffLevel_10(coeffLevel_10), + .coeffLevel_11(coeffLevel_11), + .coeffLevel_12(coeffLevel_12), + .coeffLevel_13(coeffLevel_13), + .coeffLevel_14(coeffLevel_14), + .coeffLevel_15(coeffLevel_15), + .mv_is16x16(mv_is16x16), + .mv_below8x8(mv_below8x8), + .mvx_CurrMb0(mvx_CurrMb0), + .mvx_CurrMb1(mvx_CurrMb1), + .mvx_CurrMb2(mvx_CurrMb2), + .mvx_CurrMb3(mvx_CurrMb3), + .mvy_CurrMb0(mvy_CurrMb0), + .mvy_CurrMb1(mvy_CurrMb1), + .mvy_CurrMb2(mvy_CurrMb2), + .mvy_CurrMb3(mvy_CurrMb3), + .end_of_BS_DEC(end_of_BS_DEC), + .bs_V0(bs_V0), + .bs_V1(bs_V1), + .bs_V2(bs_V2), + .bs_V3(bs_V3), + .bs_H0(bs_H0), + .bs_H1(bs_H1), + .bs_H2(bs_H2), + .bs_H3(bs_H3), + + .slice_header_s6(slice_header_s6) + ); + reconstruction reconstruction ( + .clk(clk), + .reset_n(reset_n), + .mb_type_general(mb_type_general), + .mb_num_h(mb_num_h), + .mb_num_v(mb_num_v), + .NextMB_IsSkip(NextMB_IsSkip), + .LowerMB_IsSkip(LowerMB_IsSkip), + .slice_data_state(slice_data_state), + .residual_state(residual_state), + .cavlc_decoder_state(cavlc_decoder_state), + .end_of_one_residual_block(end_of_one_residual_block), + .end_of_NonZeroCoeff_CAVLC(end_of_NonZeroCoeff_CAVLC), + .end_of_one_frame(end_of_one_frame), + .Intra16x16_predmode(Intra16x16_predmode), + .Intra4x4_predmode_CurrMb(Intra4x4_predmode_CurrMb), + .Intra_chroma_predmode(Intra_chroma_predmode), + .QPy(QPy), + .QPc(QPc), + .i4x4_CbCr(i4x4_CbCr), + .slice_alpha_c0_offset_div2(slice_alpha_c0_offset_div2), + .slice_beta_offset_div2(slice_beta_offset_div2), + .CodedBlockPatternLuma(CodedBlockPatternLuma), + .CodedBlockPatternChroma(CodedBlockPatternChroma), + .TotalCoeff(TotalCoeff), + .Is_skip_run_entry(Is_skip_run_entry), + .skip_mv_calc(skip_mv_calc), + .disable_DF(disable_DF), + .coeffLevel_0(coeffLevel_0), + .coeffLevel_1(coeffLevel_1), + .coeffLevel_2(coeffLevel_2), + .coeffLevel_3(coeffLevel_3), + .coeffLevel_4(coeffLevel_4), + .coeffLevel_5(coeffLevel_5), + .coeffLevel_6(coeffLevel_6), + .coeffLevel_7(coeffLevel_7), + .coeffLevel_8(coeffLevel_8), + .coeffLevel_9(coeffLevel_9), + .coeffLevel_10(coeffLevel_10), + .coeffLevel_11(coeffLevel_11), + .coeffLevel_12(coeffLevel_12), + .coeffLevel_13(coeffLevel_13), + .coeffLevel_14(coeffLevel_14), + .coeffLevel_15(coeffLevel_15), + .mv_is16x16(mv_is16x16), + .mv_below8x8(mv_below8x8), + .mvx_CurrMb0(mvx_CurrMb0), + .mvx_CurrMb1(mvx_CurrMb1), + .mvx_CurrMb2(mvx_CurrMb2), + .mvx_CurrMb3(mvx_CurrMb3), + .mvy_CurrMb0(mvy_CurrMb0), + .mvy_CurrMb1(mvy_CurrMb1), + .mvy_CurrMb2(mvy_CurrMb2), + .mvy_CurrMb3(mvy_CurrMb3), + .end_of_BS_DEC(end_of_BS_DEC), + .bs_V0(bs_V0), + .bs_V1(bs_V1), + .bs_V2(bs_V2), + .bs_V3(bs_V3), + .bs_H0(bs_H0), + .bs_H1(bs_H1), + .bs_H2(bs_H2), + .bs_H3(bs_H3), + + .trigger_CAVLC(trigger_CAVLC), + .blk4x4_rec_counter(blk4x4_rec_counter), + .end_of_DCBlk_IQIT(end_of_DCBlk_IQIT), + .end_of_one_blk4x4_sum(end_of_one_blk4x4_sum), + .end_of_MB_DEC(end_of_MB_DEC), + .gclk_end_of_MB_DEC(gclk_end_of_MB_DEC), + .curr_DC_IsZero(curr_DC_IsZero), + .ext_frame_RAM0_cs_n(ext_frame_RAM0_cs_n), + .ext_frame_RAM0_wr(ext_frame_RAM0_wr), + .ext_frame_RAM0_addr(ext_frame_RAM0_addr), + .ext_frame_RAM0_data(ext_frame_RAM0_data), + .ext_frame_RAM1_cs_n(ext_frame_RAM1_cs_n), + .ext_frame_RAM1_wr(ext_frame_RAM1_wr), + .ext_frame_RAM1_addr(ext_frame_RAM1_addr), + .ext_frame_RAM1_data(ext_frame_RAM1_data), + .dis_frame_RAM_din(dis_frame_RAM_din) + ); + +endmodule diff --git a/demo_chip_rtl/rtl/nova/trunk/src/nova_defines.v b/demo_chip_rtl/rtl/nova/trunk/src/nova_defines.v new file mode 100644 index 0000000..df4f9f8 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/nova_defines.v @@ -0,0 +1,309 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : nova_defines.v +// Generated : April 20,2008 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Global parameters of nova +//------------------------------------------------------------------------------------------------- + +//------------------------------------------------------------------------------------------------- +//BitStream_controller parameters +//------------------------------------------------------------------------------------------------- + +//---Beha_BitStream_ram.v--- +`define Beha_Bitstream_ram_size 131071 //Beha_Bitstream_ram size + +//bitstream_gclk_gen +//Assume running at 1.5MHz,so 50,000 cycles is needed for each frame +//1)50,000 cycles are not enough for foreman300,8th frame.So increase to 51,000 cycles +//2)51,000 cycles are not enough for foreman300,11th frame.So increase to 51,500 cycles +//3)51,500 cycles are not enough for foreman300,38th frame.So increase to 52,000 cycles +//4)52,000 cycles are not enough for foreman300,66th frame.So increase to 52,500 cycles +//5)52,500 cycles are not enough for foreman300,138th frame.So increase to 55,000 cycles +//6)55,000 cycles are not enough for foreman300,223th frame.So increase to 56,000 cycles +//After ext_frame_RAM is changed from async read (the FPGA does not support async read mode)to sync read, +//the cycles required to decode each frame increased +//7)56,000 cycles are not enough for foreman300,138th frame.So increase to 56,500 cycles +//8)56,500 cycles are not enough for foreman300,223th frame.So increase to 57,300 cycles +`define cycles_per_frame0 17'd45000 +`define cycles_per_frame1 17'd50000 //fast enough for akiyo300 +`define cycles_per_frame2 17'd57300 //preferred frequency for most critical sequence:foreman300 +`define cycles_per_frame3 17'd70000 + +//---pc_decoding--- +`define rst_consumed_bits_sel 3'b000 +`define exp_golomb 3'b001 +`define fixed_length 3'b011 +`define dependent_variable 3'b010 +`define cavlc_consumed 3'b110 +`define trailing_bits 3'b111 +`define pcm_alignment 3'b101 + +//---syntax_decoding--- +//mb_type_general +`define MB_Inter16x16 4'b0000 +`define MB_Inter16x8 4'b0001 +`define MB_Inter8x16 4'b0010 +`define MB_P_8x8 4'b0011 +`define MB_P_8x8ref0 4'b0100 +`define MB_P_skip 4'b0101 +`define MB_I_PCM 4'b0110 +`define MB_type_reserved0 4'b0111 +`define MB_Intra16x16_CBPChroma0 4'b1000 +`define MB_Intra16x16_CBPChroma1 4'b1001 +`define MB_Intra16x16_CBPChroma2 4'b1010 +`define MB_type_reserved1 4'b1011 +`define MB_Intra4x4 4'b1100 +`define MB_type_reserved2 4'b1101 +`define MB_type_reserved3 4'b1110 +`define MB_type_rst 4'b1111 + +//MBTypeGen_mbAddrA,MBTypeGen_mbAddrB_reg +`define MB_addrA_addrB_Inter 2'b00 +`define MB_addrA_addrB_P_skip 2'b01 +`define MB_addrA_addrB_Intra16x16 2'b10 +`define MB_addrA_addrB_Intra4x4 2'b11 + +//MBTypeGen_mbAddrD +`define MB_addrD_Inter_P_skip 1'b0 +`define MB_addrD_Intra 1'b1 + +//Gray-encoded FSM states to reduce power consumption during state switching +`define rst_parser 2'b00 +`define start_code_prefix 2'b01 +`define nal_unit 2'b11 + +`define rst_nal_unit 3'b000 +`define forbidden_zero_bit_2_nal_unit_type 3'b001 +`define slice_layer_non_IDR_rbsp 3'b011 +`define slice_layer_IDR_rbsp 3'b010 +`define seq_parameter_set_rbsp 3'b110 +`define pic_parameter_set_rbsp 3'b111 +`define rbsp_trailing_one_bit 3'b101 +`define rbsp_trailing_zero_bits 3'b100 + +`define rst_slice_layer_wo_partitioning 2'b00 +`define slice_header 2'b01 +`define slice_data 2'b11 + +`define rst_seq_parameter_set 4'b0000 +`define fixed_header 4'b0001 +`define level_idc_s 4'b0011 +`define seq_parameter_set_id_sps_s 4'b0010 +`define log2_max_frame_num_minus4_s 4'b0110 +`define pic_order_cnt_type_s 4'b0111 +`define log2_max_pic_order_cnt_lsb_minus4_s 4'b0101 +`define num_ref_frames_s 4'b0100 +`define gaps_in_frame_num_value_allowed_flag_s 4'b1100 +`define pic_width_in_mbs_minus1_s 4'b1101 +`define pic_height_in_map_units_minus1_s 4'b1111 +`define frame_mbs_only_flag_2_frame_cropping_flag 4'b1110 +`define vui_parameter_present_flag_s 4'b1010 + +`define rst_pic_parameter_set 4'b0000 +`define pic_parameter_set_id_pps_s 4'b0001 +`define seq_parameter_set_id_pps_s 4'b0011 +`define entropy_coding_mode_flag_2_pic_order_present_flag 4'b0010 +`define num_slice_groups_minus1_s 4'b0110 +`define num_ref_idx_l0_active_minus1_pps_s 4'b0111 +`define num_ref_idx_l1_active_minus1_pps_s 4'b0101 +`define weighted_pred_flag_2_weighted_bipred_idc 4'b0100 +`define pic_init_qp_minus26_s 4'b1100 +`define pic_init_qs_minus26_s 4'b1101 +`define chroma_qp_index_offset_s 4'b1111 +`define deblocking_filter_control_2_redundant_pic_cnt_present_flag 4'b1110 + +`define rst_slice_header 4'b0000 +`define first_mb_in_slice_s 4'b0001 +`define slice_type_s 4'b0011 +`define pic_parameter_set_id_slice_header_s 4'b0010 +`define frame_num_s 4'b0110 +`define idr_pic_id_s 4'b0111 +`define pic_order_cnt_lsb_s 4'b0101 +`define num_ref_idx_active_override_flag_s 4'b0100 +`define num_ref_idx_l0_active_minus1_slice_header_s 4'b1100 +`define ref_pic_list_reordering 4'b1101 +`define dec_ref_pic_marking 4'b1111 +`define slice_qp_delta_s 4'b1110 +`define disable_deblocking_filter_idc_s 4'b1010 +`define slice_alpha_c0_offset_div2_s 4'b1011 +`define slice_beta_offset_div2_s 4'b1001 + +//ref_pic_list_reordering_state +`define rst_ref_pic_list_reordering 3'b000 +`define ref_pic_list_reordering_flag_l0_s 3'b001 + +//dec_ref_pic_marking_state +`define rst_dec_ref_pic_marking 2'b00 +`define no_output_of_prior_pics_flag_2_long_term_reference_flag 2'b01 +`define adaptive_ref_pic_marking_mode_flag_s 2'b11 + +`define rst_slice_data 4'b0000 +`define mb_skip_run_s 4'b0001 +`define skip_run_duration 4'b0011 +`define mb_type_s 4'b0010 +`define pcm_alignment_zero_bit_s 4'b0110 +`define pcm_byte_s 4'b0111 +`define sub_mb_pred 4'b0101 +`define mb_pred 4'b0100 +`define coded_block_pattern_s 4'b1100 +`define mb_qp_delta_s 4'b1101 +`define residual 4'b1111 +`define mb_num_update 4'b1110 + +//mb_pred_state +`define rst_mb_pred 3'b000 +`define prev_intra4x4_pred_mode_flag_s 3'b001 +`define rem_intra4x4_pred_mode_s 3'b011 +`define intra_chroma_pred_mode_s 3'b010 +`define ref_idx_l0_s 3'b110 +`define mvd_l0_s 3'b111 + +//sub_mb_pred_state +`define rst_sub_mb_pred 2'b00 +`define sub_mb_type_s 2'b01 +`define sub_ref_idx_l0_s 2'b11 +`define sub_mvd_l0_s 2'b10 + +`define rst_residual 4'b0000 +`define Intra16x16DCLevel_s 4'b0001 +`define Intra16x16ACLevel_s 4'b0011 +`define Intra16x16ACLevel_0_s 4'b0010 +`define LumaLevel_s 4'b0110 +`define LumaLevel_0_s 4'b0111 +`define ChromaDCLevel_Cb_s 4'b0101 +`define ChromaDCLevel_Cr_s 4'b0100 +`define ChromaACLevel_Cb_s 4'b1100 +`define ChromaACLevel_Cr_s 4'b1101 +`define ChromaACLevel_0_s 4'b1110 + +`define rst_cavlc_decoder 4'b0000 +`define nAnB_decoding_s 4'b0001 +`define nC_decoding_s 4'b0011 +`define NumCoeffTrailingOnes_LUT 4'b0010 +`define TrailingOnesSignFlag 4'b0110 +`define LevelPrefix 4'b0111 +`define LevelSuffix 4'b0101 +`define total_zeros_LUT 4'b0100 +`define run_before_LUT 4'b1100 +`define RunOfZeros 4'b1101 +`define LevelRunCombination 4'b1111 + +//---LumaLevel_mbAddrB_RF--- +`define LumaLevel_mbAddrB_RF_data_width 20 +`define LumaLevel_mbAddrB_RF_data_depth 11 +//---ChromaLevel_Cb_mbAddrB_RF--- +`define ChromaLevel_Cb_mbAddrB_RF_data_width 10 +`define ChromaLevel_Cb_mbAddrB_RF_data_depth 11 +//---ChromaLevel_Cr_mbAddrB_RF--- +`define ChromaLevel_Cr_mbAddrB_RF_data_width 10 +`define ChromaLevel_Cr_mbAddrB_RF_data_depth 11 + +//---Intra4x4_PredMode_RF--- +`define Intra4x4_PredMode_RF_data_width 16 +`define Intra4x4_PredMode_RF_data_depth 11 + +//---mvx_mbAddrB_RF--- +`define mvx_mbAddrB_RF_data_width 32 +`define mvx_mbAddrB_RF_data_depth 11 +//---mvy_mbAddrB_RF--- +`define mvy_mbAddrB_RF_data_width 32 +`define mvy_mbAddrB_RF_data_depth 11 +//---mvx_mbAddrC_RF--- +`define mvx_mbAddrC_RF_data_width 8 +`define mvx_mbAddrC_RF_data_depth 10 +//---mvy_mbAddrC_RF--- +`define mvy_mbAddrC_RF_data_width 8 +`define mvy_mbAddrC_RF_data_depth 10 + +//------------------------------------------------------------------------------------------------- +//Intra prediction parameters +//------------------------------------------------------------------------------------------------- + +//---Intra_mbAddrB_RAM--- +`define Intra_mbAddrB_RAM_data_width 32 +`define Intra_mbAddrB_RAM_data_depth 88 + +//---Intra_pred_PE,Intra_pred_pipeline,Intra_pred_reg_ctrl--- +`define Intra4x4_Vertical 4'b0000 +`define Intra4x4_Horizontal 4'b0001 +`define Intra4x4_DC 4'b0010 +`define Intra4x4_Diagonal_Down_Left 4'b0011 +`define Intra4x4_Diagonal_Down_Right 4'b0100 +`define Intra4x4_Vertical_Right 4'b0101 +`define Intra4x4_Horizontal_Down 4'b0110 +`define Intra4x4_Vertical_Left 4'b0111 +`define Intra4x4_Horizontal_Up 4'b1000 + +`define Intra16x16_Vertical 2'b00 +`define Intra16x16_Horizontal 2'b01 +`define Intra16x16_DC 2'b10 +`define Intra16x16_Plane 2'b11 + +`define Intra_chroma_DC 2'b00 +`define Intra_chroma_Horizontal 2'b01 +`define Intra_chroma_Vertical 2'b10 +`define Intra_chroma_Plane 2'b11 + +//------------------------------------------------------------------------------------------------- +//Inter prediction parameters +//------------------------------------------------------------------------------------------------- + +//---Inter_pred_LPE,Inter_pred_pipeline,Inter_pred_reg_ctrl,Inter_pred_sliding_window--- +`define pos_Int 4'b0000 +`define pos_a 4'b0100 +`define pos_b 4'b1000 +`define pos_c 4'b1100 +`define pos_d 4'b0001 +`define pos_e 4'b0101 +`define pos_f 4'b1001 +`define pos_g 4'b1101 +`define pos_h 4'b0010 +`define pos_i 4'b0110 +`define pos_j 4'b1010 +`define pos_k 4'b1110 +`define pos_n 4'b0011 +`define pos_p 4'b0111 +`define pos_q 4'b1011 +`define pos_r 4'b1111 + +//---Inter_pred_pipeline +`define pic_width 8'd176 +`define pic_height 8'd144 +`define half_pic_width 7'd88 +`define half_pic_height 7'd72 + +//------------------------------------------------------------------------------------------------- +//Deblocking filter parameters +//------------------------------------------------------------------------------------------------- + +//---bs_decoding--- +`define I8x8 2'b00 //size of inter prediction partitions +`define I16x8 2'b01 +`define I8x16 2'b10 +`define I16x16 2'b11 + +//---DF_mbAddrA_RAM--- +`define DF_mbAddrA_RAM_data_width 32 +`define DF_mbAddrA_RAM_data_depth 32 + +//---DF_mbAddrB_RAM--- +`define DF_mbAddrB_RAM_data_width 32 +`define DF_mbAddrB_RAM_data_depth 352 + +//---rec_DF_RAM0--- +`define rec_DF_RAM0_data_width 32 +`define rec_DF_RAM0_data_depth 96 + +//---rec_DF_RAM1--- +`define rec_DF_RAM1_data_width 32 +`define rec_DF_RAM1_data_depth 96 + +//------------------------------------------------------------------------------------------------- +//Hybrid pipeline control parameters +//------------------------------------------------------------------------------------------------- + diff --git a/demo_chip_rtl/rtl/nova/trunk/src/nova_tb.v b/demo_chip_rtl/rtl/nova/trunk/src/nova_tb.v new file mode 100644 index 0000000..b7fbcd8 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/nova_tb.v @@ -0,0 +1,108 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : nova_tb.v +// Generated : March 13,2006 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Testbench for nova +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module nova_tb; + + reg clk; + reg reset_n; + reg pin_disable_DF; + reg freq_ctrl0; + reg freq_ctrl1; + + wire BitStream_ram_ren; + wire [16:0] BitStream_ram_addr; + wire [15:0] BitStream_buffer_input; + wire [5:0] pic_num; + wire [6:0] mb_num; + + wire [13:0] ext_frame_RAM0_addr; + wire [31:0] ext_frame_RAM0_data; + wire [13:0] ext_frame_RAM1_addr; + wire [31:0] ext_frame_RAM1_data; + wire [31:0] dis_frame_RAM_din; + + wire [15:0] temp; + assign temp = dis_frame_RAM_din[15:0]; + + //for debug only + wire slice_header_s6; + + Beha_BitStream_ram Beha_BitStream_ram ( + .clk(clk), + .BitStream_ram_ren(BitStream_ram_ren), + .BitStream_ram_addr(BitStream_ram_addr), + .BitStream_ram_data(BitStream_buffer_input) + ); + ext_frame_RAM0_wrapper ext_frame_RAM0_wrapper ( + .clk(clk), + .reset_n(reset_n), + .ext_frame_RAM0_cs_n(ext_frame_RAM0_cs_n), + .ext_frame_RAM0_wr(ext_frame_RAM0_wr), + .ext_frame_RAM0_addr(ext_frame_RAM0_addr), + .dis_frame_RAM_din(dis_frame_RAM_din), + .ext_frame_RAM0_data(ext_frame_RAM0_data), + .pic_num(pic_num), + .slice_header_s6(slice_header_s6) + ); + ext_frame_RAM1_wrapper ext_frame_RAM1_wrapper ( + .clk(clk), + .reset_n(reset_n), + .ext_frame_RAM1_cs_n(ext_frame_RAM1_cs_n), + .ext_frame_RAM1_wr(ext_frame_RAM1_wr), + .ext_frame_RAM1_addr(ext_frame_RAM1_addr), + .dis_frame_RAM_din(dis_frame_RAM_din), + .ext_frame_RAM1_data(ext_frame_RAM1_data), + .pic_num(pic_num), + .slice_header_s6(slice_header_s6) + ); + nova nova ( + .clk(clk), + .reset_n(reset_n), + .freq_ctrl0(freq_ctrl0), + .freq_ctrl1(freq_ctrl1), + .BitStream_buffer_input(BitStream_buffer_input), + .BitStream_ram_ren(BitStream_ram_ren), + .BitStream_ram_addr(BitStream_ram_addr), + .pic_num(pic_num), + .pin_disable_DF(pin_disable_DF), + .ext_frame_RAM0_cs_n(ext_frame_RAM0_cs_n), + .ext_frame_RAM0_wr(ext_frame_RAM0_wr), + .ext_frame_RAM0_addr(ext_frame_RAM0_addr), + .ext_frame_RAM0_data(ext_frame_RAM0_data), + .ext_frame_RAM1_cs_n(ext_frame_RAM1_cs_n), + .ext_frame_RAM1_wr(ext_frame_RAM1_wr), + .ext_frame_RAM1_addr(ext_frame_RAM1_addr), + .ext_frame_RAM1_data(ext_frame_RAM1_data), + .dis_frame_RAM_din(dis_frame_RAM_din), + .slice_header_s6(slice_header_s6) + ); + + initial + begin + clk = 1'b1; + reset_n = 1'b1; + pin_disable_DF = 1'b0; + freq_ctrl0 = 1'b0; + freq_ctrl1 = 1'b1; + #1100 reset_n = 1'b0; + #1000 reset_n = 1'b1; + end + + always + #340 clk = ~clk; + +endmodule diff --git a/demo_chip_rtl/rtl/nova/trunk/src/pc_decoding.v b/demo_chip_rtl/rtl/nova/trunk/src/pc_decoding.v new file mode 100644 index 0000000..48a658d --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/pc_decoding.v @@ -0,0 +1,204 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : pc_decoding.v +// Generated : June 6, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Decoding program counter for bitstream_buffer +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module pc_decoding (clk,reset_n,parser_state,nal_unit_state,slice_header_state,ref_pic_list_reordering_state, + dec_ref_pic_marking_state,slice_data_state,sub_mb_pred_state,mb_pred_state,seq_parameter_set_state, + pic_parameter_set_state,exp_golomb_len,dependent_variable_len,cavlc_consumed_bits_len, + pc); + input clk,reset_n; + input [1:0] parser_state; + input [2:0] nal_unit_state; + input [3:0] slice_header_state; + input [2:0] ref_pic_list_reordering_state; + input [1:0] dec_ref_pic_marking_state; + input [3:0] slice_data_state; + input [1:0] sub_mb_pred_state; + input [2:0] mb_pred_state; + input [3:0] seq_parameter_set_state; + input [3:0] pic_parameter_set_state; + input [3:0] exp_golomb_len; + input [3:0] dependent_variable_len; + input [4:0] cavlc_consumed_bits_len; + output [6:0] pc; + reg [6:0] pc; + + reg [2:0] consumed_bits_sel; + reg [4:0] FixedLen; + + always @ (reset_n or parser_state or nal_unit_state or slice_header_state or ref_pic_list_reordering_state or + dec_ref_pic_marking_state or slice_data_state or sub_mb_pred_state or mb_pred_state or + seq_parameter_set_state or pic_parameter_set_state) + if (reset_n == 0) + consumed_bits_sel <= `rst_consumed_bits_sel; + else if (parser_state == `start_code_prefix) + consumed_bits_sel <= `fixed_length; + else if (nal_unit_state == `forbidden_zero_bit_2_nal_unit_type) + consumed_bits_sel <= `fixed_length; + else if (slice_header_state != `rst_slice_header) + case (slice_header_state) + `first_mb_in_slice_s :consumed_bits_sel <= `exp_golomb; + `slice_type_s :consumed_bits_sel <= `exp_golomb; + `pic_parameter_set_id_slice_header_s :consumed_bits_sel <= `exp_golomb; + `frame_num_s :consumed_bits_sel <= `dependent_variable; + `idr_pic_id_s :consumed_bits_sel <= `exp_golomb; + `pic_order_cnt_lsb_s :consumed_bits_sel <= `dependent_variable; + `num_ref_idx_active_override_flag_s :consumed_bits_sel <= `fixed_length; + `num_ref_idx_l0_active_minus1_slice_header_s:consumed_bits_sel <= `exp_golomb; + `ref_pic_list_reordering: + case (ref_pic_list_reordering_state) + `ref_pic_list_reordering_flag_l0_s:consumed_bits_sel <= `fixed_length; + default :consumed_bits_sel <= `rst_consumed_bits_sel; + endcase + `dec_ref_pic_marking: + case (dec_ref_pic_marking_state) + `no_output_of_prior_pics_flag_2_long_term_reference_flag:consumed_bits_sel <= `fixed_length; + `adaptive_ref_pic_marking_mode_flag_s :consumed_bits_sel <= `fixed_length; + default :consumed_bits_sel <= `rst_consumed_bits_sel; + endcase + `slice_qp_delta_s :consumed_bits_sel <= `exp_golomb; + `disable_deblocking_filter_idc_s:consumed_bits_sel <= `exp_golomb; + `slice_alpha_c0_offset_div2_s :consumed_bits_sel <= `exp_golomb; + `slice_beta_offset_div2_s :consumed_bits_sel <= `exp_golomb; + default :consumed_bits_sel <= `rst_consumed_bits_sel; + endcase + else if (slice_data_state != `rst_slice_data) + case (slice_data_state) + `mb_skip_run_s :consumed_bits_sel <= `exp_golomb; + `mb_type_s :consumed_bits_sel <= `exp_golomb; + `pcm_alignment_zero_bit_s:consumed_bits_sel <= `exp_golomb; + `pcm_byte_s :consumed_bits_sel <= `pcm_alignment; + `sub_mb_pred: + case (sub_mb_pred_state) + `rst_sub_mb_pred:consumed_bits_sel <= `rst_consumed_bits_sel; + default :consumed_bits_sel <= `exp_golomb; + endcase + `mb_pred: + case (mb_pred_state) + `prev_intra4x4_pred_mode_flag_s:consumed_bits_sel <= `fixed_length; + `rem_intra4x4_pred_mode_s :consumed_bits_sel <= `fixed_length; + `intra_chroma_pred_mode_s :consumed_bits_sel <= `exp_golomb; + `ref_idx_l0_s :consumed_bits_sel <= `exp_golomb; + `mvd_l0_s :consumed_bits_sel <= `exp_golomb; + default :consumed_bits_sel <= `rst_consumed_bits_sel; + endcase + `coded_block_pattern_s:consumed_bits_sel <= `exp_golomb; + `mb_qp_delta_s :consumed_bits_sel <= `exp_golomb; + `residual :consumed_bits_sel <= `cavlc_consumed; + default :consumed_bits_sel <= `rst_consumed_bits_sel; + endcase + else if (seq_parameter_set_state != `rst_seq_parameter_set) + case (seq_parameter_set_state) + `fixed_header :consumed_bits_sel <= `fixed_length; + `level_idc_s :consumed_bits_sel <= `fixed_length; + `seq_parameter_set_id_sps_s :consumed_bits_sel <= `exp_golomb; + `log2_max_frame_num_minus4_s :consumed_bits_sel <= `exp_golomb; + `pic_order_cnt_type_s :consumed_bits_sel <= `exp_golomb; + `log2_max_pic_order_cnt_lsb_minus4_s :consumed_bits_sel <= `exp_golomb; + `num_ref_frames_s :consumed_bits_sel <= `exp_golomb; + `gaps_in_frame_num_value_allowed_flag_s :consumed_bits_sel <= `fixed_length; + `pic_width_in_mbs_minus1_s :consumed_bits_sel <= `exp_golomb; + `pic_height_in_map_units_minus1_s :consumed_bits_sel <= `exp_golomb; + `frame_mbs_only_flag_2_frame_cropping_flag:consumed_bits_sel <= `fixed_length; + `vui_parameter_present_flag_s :consumed_bits_sel <= `fixed_length; + default :consumed_bits_sel <= `rst_consumed_bits_sel; + endcase + else if (pic_parameter_set_state != `rst_pic_parameter_set) + case (pic_parameter_set_state) + `pic_parameter_set_id_pps_s :consumed_bits_sel <= `exp_golomb; + `seq_parameter_set_id_pps_s :consumed_bits_sel <= `exp_golomb; + `entropy_coding_mode_flag_2_pic_order_present_flag :consumed_bits_sel <= `fixed_length; + `num_slice_groups_minus1_s :consumed_bits_sel <= `exp_golomb; + `num_ref_idx_l0_active_minus1_pps_s :consumed_bits_sel <= `exp_golomb; + `num_ref_idx_l1_active_minus1_pps_s :consumed_bits_sel <= `exp_golomb; + `weighted_pred_flag_2_weighted_bipred_idc :consumed_bits_sel <= `fixed_length; + `pic_init_qp_minus26_s :consumed_bits_sel <= `exp_golomb; + `pic_init_qs_minus26_s :consumed_bits_sel <= `exp_golomb; + `chroma_qp_index_offset_s :consumed_bits_sel <= `exp_golomb; + `deblocking_filter_control_2_redundant_pic_cnt_present_flag:consumed_bits_sel <= `fixed_length; + default :consumed_bits_sel <= `rst_consumed_bits_sel; + endcase + else if (nal_unit_state == `rbsp_trailing_one_bit) + consumed_bits_sel <= `fixed_length; + else if (nal_unit_state == `rbsp_trailing_zero_bits) + consumed_bits_sel <= `trailing_bits; + else + consumed_bits_sel <= `rst_consumed_bits_sel; + + always @ (reset_n or parser_state or nal_unit_state or slice_header_state or ref_pic_list_reordering_state or + dec_ref_pic_marking_state or slice_data_state or mb_pred_state or seq_parameter_set_state or pic_parameter_set_state) + if (reset_n == 0) + FixedLen <= 0; + else + begin + if (parser_state == `start_code_prefix) + FixedLen <= 5'd16; + else if (nal_unit_state == `forbidden_zero_bit_2_nal_unit_type) + FixedLen <= 8; + else if (slice_header_state == `num_ref_idx_active_override_flag_s) + FixedLen <= 1; + else if (ref_pic_list_reordering_state == `ref_pic_list_reordering_flag_l0_s) + FixedLen <= 1; + else if (dec_ref_pic_marking_state == `no_output_of_prior_pics_flag_2_long_term_reference_flag) + FixedLen <= 2; + else if (dec_ref_pic_marking_state == `adaptive_ref_pic_marking_mode_flag_s) + FixedLen <= 1; + else if (slice_data_state == `pcm_byte_s) + FixedLen <= 5'd16; + else if (mb_pred_state == `prev_intra4x4_pred_mode_flag_s) + FixedLen <= 1; + else if (mb_pred_state == `rem_intra4x4_pred_mode_s) + FixedLen <= 3; + else if (seq_parameter_set_state == `fixed_header) + FixedLen <= 5'd16; + else if (seq_parameter_set_state == `level_idc_s) + FixedLen <= 8; + else if (seq_parameter_set_state == `gaps_in_frame_num_value_allowed_flag_s) + FixedLen <= 1; + else if (seq_parameter_set_state == `frame_mbs_only_flag_2_frame_cropping_flag) + FixedLen <= 3; + else if (seq_parameter_set_state == `vui_parameter_present_flag_s) + FixedLen <= 1; + else if (pic_parameter_set_state == `entropy_coding_mode_flag_2_pic_order_present_flag) + FixedLen <= 2; + else if (pic_parameter_set_state == `weighted_pred_flag_2_weighted_bipred_idc) + FixedLen <= 3; + else if (pic_parameter_set_state == `deblocking_filter_control_2_redundant_pic_cnt_present_flag) + FixedLen <= 3; + else if (nal_unit_state == `rbsp_trailing_one_bit) + FixedLen <= 1; + else + FixedLen <= 1; + end + + reg [6:0] pc_reg; + always @ (consumed_bits_sel or pc_reg or exp_golomb_len or dependent_variable_len or + cavlc_consumed_bits_len or FixedLen) + case (consumed_bits_sel) + `exp_golomb :pc <= pc_reg + exp_golomb_len; + `dependent_variable:pc <= pc_reg + dependent_variable_len; + `cavlc_consumed :pc <= pc_reg + cavlc_consumed_bits_len; + `fixed_length :pc <= pc_reg + FixedLen; + `trailing_bits :pc <= (pc_reg[2:0] == 3'b000)? pc_reg:{{pc_reg[6:3] + 1},3'b0}; + `pcm_alignment :pc <= (pc_reg[2:0] == 3'b000)? pc_reg:{{pc_reg[6:3] + 1},3'b0}; + default :pc <= pc_reg; + endcase + always @ (posedge clk) + pc_reg <= (reset_n == 0)? 0:pc; + +endmodule + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/ram_async_1r_sync_1w.v b/demo_chip_rtl/rtl/nova/trunk/src/ram_async_1r_sync_1w.v new file mode 100644 index 0000000..5952a86 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/ram_async_1r_sync_1w.v @@ -0,0 +1,81 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : ram_async_1r_sync_1w.v +// Generated : April 25,2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Synch Write, Asynch Read RAM, NOT synthesizable +// In real silicon, use register file (DFF) instead of RAM +// legal range:data_width [ 1 to 128 ] +// legal range:data_depth [ 2 to 256 ] +// Input data :data_in[data_width-1:0] +// Output data:data_out[data_width-1:0] +// Read Address :rd_addr[addr_width-1:0] +// Write Address:wr_addr[addr_width-1:0] +// Write enable (active low): wr_n +// Chip select (active low): cs_n +// Reset (active low): rst_n +// Clock:clk +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" +module ram_async_1r_sync_1w (clk, rst_n, cs_n, wr_n, rd_addr, wr_addr, data_in, data_out); + + parameter data_width = 4; //will be overrided during module instantiation + parameter data_depth = 8; //will be overrided during module instantiation + + `define addr_width ((data_depth>16)?((data_depth>64)?((data_depth>128)?8:7):((data_depth>32)?6:5)):((data_depth>4)?((data_depth>8)?4:3):((data_depth>2)?2:1))) + + input clk; + input rst_n; + input cs_n; + input wr_n; + input [data_width-1:0] data_in; + input [`addr_width-1:0] rd_addr; + input [`addr_width-1:0] wr_addr; + output [data_width-1:0] data_out; + + reg [data_width-1:0] ram [data_depth-1:0]; + + //data_width & data_depth check + initial + begin:parameter_check + integer param_error_flag; + param_error_flag = 0; + + if ( (data_width < 1) || (data_width > 128) ) + begin + param_error_flag = 1; + $display("Error: %m :\n Invalid value (%d) for parameter data_width (legal range: 1 to 128)",data_width ); + end + + if ( (data_depth < 2) || (data_depth > 256 ) ) + begin + param_error_flag = 1; + $display("Error: %m :\n Invalid value (%d) for parameter data_depth (legal range: 2 to 256 )",data_depth ); + end + + if ( param_error_flag == 1) + begin + $display("%m :\n Simulation aborted due to invalid parameter value(s)"); + $finish; + end + + end // end data_width & data_depth check + + //read + assign data_out = ((rd_addr ^ rd_addr) !== {`addr_width{1'b0}})? {data_width{1'bx}} : ((rd_addr >= data_depth)? {data_width{1'b0}} : ram[rd_addr] ); + + //write + always @ (posedge clk) + if (!cs_n && !wr_n) + ram[wr_addr] <= data_in; + +endmodule + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/ram_sync_1r_sync_1w.v b/demo_chip_rtl/rtl/nova/trunk/src/ram_sync_1r_sync_1w.v new file mode 100644 index 0000000..753b0b1 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/ram_sync_1r_sync_1w.v @@ -0,0 +1,94 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : ram_sync_1r_sync_1w.v +// Generated : April 25,2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Synch Write, Synch Read RAM, NOT synthesizable +// In real silicon, use customized RAM instead of DFF +// legal range:data_width [ 1 to 256 ] +// legal range:data_depth [ 2 to 1024 ] +// Input data :data_in[data_width-1:0] +// Output data:data_out[data_width-1:0] +// Read Address :rd_addr[addr_width-1:0] +// Write Address:wr_addr[addr_width-1:0] +// Write enable (active low): wr_n +// Chip select (active low): cs_n +// Reset (active low): rst_n +// Clock:clk +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module ram_sync_1r_sync_1w (clk, rst_n, wr_n, rd_n, wr_addr, rd_addr, data_in, data_out); + + parameter data_width = 4; //will be overrided during module instantiation + parameter data_depth = 8; //will be overrided during module instantiation + + `define addr_width ((data_depth>32)?((data_depth>256)?((data_depth>512)?10:9):((data_depth>128)?8:((data_depth>64)?7:6))):((data_depth>8) ?((data_depth>16) ?5:4) :((data_depth>4) ?3:((data_depth>2) ?1:0)))) + + input clk; + input rst_n; + input wr_n; + input rd_n; + input [`addr_width-1:0] wr_addr; + input [`addr_width-1:0] rd_addr; + input [data_width-1:0] data_in; + output [data_width-1:0] data_out; + + reg [data_width-1:0] data_out; + reg [data_width-1:0] ram [data_depth-1:0]; + + //data_width, data_depth, simultaneously read/write check + initial + begin:parameter_check + integer param_error_flag; + param_error_flag = 0; + + if ( (data_width < 1) || (data_width > 256) ) + begin + param_error_flag = 1; + $display("Error: %m :\n Invalid value (%d) for parameter data_width (legal range: 1 to 256)",data_width ); + end + + if ( (data_depth < 2) || (data_depth > 1024 ) ) + begin + param_error_flag = 1; + $display("Error: %m :\n Invalid value (%d) for parameter data_depth (legal range: 2 to 1024 )",data_depth ); + end + + /* + if ( (cs_n == 1'b0 && wr_n == 1'b0 && rd_n == 1'b0 ) ) + begin + param_error_flag = 1; + $display("Error: %m :\n Not allowed! RAM simultaneously read and write occur"); + end + */ + if ( param_error_flag == 1) + begin + $display("%m :\n Simulation aborted due to invalid parameter value(s)"); + $finish; + end + + end // end data_width & data_depth check + + //read + always @ (posedge clk or negedge rst_n) + if (rst_n == 1'b0) + data_out <= 0; + else if (!rd_n) + data_out <= ram[rd_addr]; + + //write + always @ (posedge clk) + if (!wr_n) + ram[wr_addr] <= data_in; + +endmodule + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/rec_DF_RAM_ctrl.v b/demo_chip_rtl/rtl/nova/trunk/src/rec_DF_RAM_ctrl.v new file mode 100644 index 0000000..70bb696 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/rec_DF_RAM_ctrl.v @@ -0,0 +1,173 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : rec_DF_RAM_ctrl.v +// Generated : Nov 3, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Controller for rec_DF_RAM0 & rec_DF_RAM1,single port SRAM +// write during reconstruction,read during DF +// assume "_wr" & "_rd" are both high active +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module rec_DF_RAM_ctrl (clk,reset_n,disable_DF,end_of_MB_DEC, + DF_edge_counter_MR,one_edge_counter_MR, + blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out, + blk4x4_sum_counter,blk4x4_rec_counter_2_raster_order,rec_DF_RAM0_dout,rec_DF_RAM1_dout, + + rec_DF_RAM_dout, + rec_DF_RAM0_wr,rec_DF_RAM0_rd,rec_DF_RAM0_addr,rec_DF_RAM0_din, + rec_DF_RAM1_wr,rec_DF_RAM1_rd,rec_DF_RAM1_addr,rec_DF_RAM1_din); + input clk,reset_n; + input disable_DF; + input end_of_MB_DEC; + input [5:0] DF_edge_counter_MR; + input [1:0] one_edge_counter_MR; + input [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out; + input [2:0] blk4x4_sum_counter; + input [4:0] blk4x4_rec_counter_2_raster_order; + input [31:0] rec_DF_RAM0_dout,rec_DF_RAM1_dout; + + output [31:0] rec_DF_RAM_dout; + output rec_DF_RAM0_wr; + output rec_DF_RAM0_rd; + output [6:0]rec_DF_RAM0_addr; + output [31:0] rec_DF_RAM0_din; + output rec_DF_RAM1_wr; + output rec_DF_RAM1_rd; + output [6:0]rec_DF_RAM1_addr; + output [31:0] rec_DF_RAM1_din; + + reg rec_DF_RAM0_wr; + reg rec_DF_RAM0_rd; + reg [6:0]rec_DF_RAM0_addr; + reg [31:0] rec_DF_RAM0_din; + reg rec_DF_RAM1_wr; + reg rec_DF_RAM1_rd; + reg [6:0]rec_DF_RAM1_addr; + reg [31:0] rec_DF_RAM1_din; + //----------------------------------------------------------------- + //Write:after reconstruction + //----------------------------------------------------------------- + wire rec_DF_RAM_wr; + wire [4:0] rec_DF_RAM_wr_addr_blk4x4; + wire [1:0] rec_DF_RAM_wr_addr_offset; + wire [6:0] rec_DF_RAM_wr_addr; + wire [31:0] rec_DF_RAM_din; + + assign rec_DF_RAM_wr = !disable_DF && (blk4x4_sum_counter[2] != 1'b1); + assign rec_DF_RAM_wr_addr_blk4x4 = {5{rec_DF_RAM_wr}} & blk4x4_rec_counter_2_raster_order; + assign rec_DF_RAM_wr_addr_offset = {2{rec_DF_RAM_wr}} & blk4x4_sum_counter[1:0]; + assign rec_DF_RAM_wr_addr = {rec_DF_RAM_wr_addr_blk4x4,2'b0} + rec_DF_RAM_wr_addr_offset; + assign rec_DF_RAM_din = (rec_DF_RAM_wr)? {blk4x4_sum_PE3_out,blk4x4_sum_PE2_out,blk4x4_sum_PE1_out,blk4x4_sum_PE0_out}:0; + //----------------------------------------------------------------- + //Read:during deblocking filter + //----------------------------------------------------------------- + wire rec_DF_RAM_rd; + reg [4:0] rec_DF_RAM_rd_addr_blk4x4; + wire [1:0] rec_DF_RAM_rd_addr_offset; + wire [6:0] rec_DF_RAM_rd_addr; + + assign rec_DF_RAM_rd = ((DF_edge_counter_MR[5] == 1'b0 && (DF_edge_counter_MR[3:0] == 4'd0 || + DF_edge_counter_MR[3:0] == 4'd1 || DF_edge_counter_MR[3:0] == 4'd2 || DF_edge_counter_MR[3:0] == 4'd3 || + DF_edge_counter_MR[3:0] == 4'd6 || DF_edge_counter_MR[3:0] == 4'd7 || DF_edge_counter_MR[3:0] == 4'd10|| + DF_edge_counter_MR[3:0] == 4'd11)) || (DF_edge_counter_MR[5] == 1'b1 && DF_edge_counter_MR[2] == 1'b0)); + + always @ (rec_DF_RAM_rd or DF_edge_counter_MR) + if (rec_DF_RAM_rd) + case (DF_edge_counter_MR) + 6'd0 :rec_DF_RAM_rd_addr_blk4x4 <= 5'd0; + 6'd1 :rec_DF_RAM_rd_addr_blk4x4 <= 5'd1; + 6'd2 :rec_DF_RAM_rd_addr_blk4x4 <= 5'd4; + 6'd3 :rec_DF_RAM_rd_addr_blk4x4 <= 5'd5; + 6'd6 :rec_DF_RAM_rd_addr_blk4x4 <= 5'd2; + 6'd7 :rec_DF_RAM_rd_addr_blk4x4 <= 5'd6; + 6'd10:rec_DF_RAM_rd_addr_blk4x4 <= 5'd3; + 6'd11:rec_DF_RAM_rd_addr_blk4x4 <= 5'd7; + 6'd16:rec_DF_RAM_rd_addr_blk4x4 <= 5'd8; + 6'd17:rec_DF_RAM_rd_addr_blk4x4 <= 5'd9; + 6'd18:rec_DF_RAM_rd_addr_blk4x4 <= 5'd12; + 6'd19:rec_DF_RAM_rd_addr_blk4x4 <= 5'd13; + 6'd22:rec_DF_RAM_rd_addr_blk4x4 <= 5'd10; + 6'd23:rec_DF_RAM_rd_addr_blk4x4 <= 5'd14; + 6'd26:rec_DF_RAM_rd_addr_blk4x4 <= 5'd11; + 6'd27:rec_DF_RAM_rd_addr_blk4x4 <= 5'd15; + 6'd32:rec_DF_RAM_rd_addr_blk4x4 <= 5'd16; + 6'd33:rec_DF_RAM_rd_addr_blk4x4 <= 5'd17; + 6'd34:rec_DF_RAM_rd_addr_blk4x4 <= 5'd18; + 6'd35:rec_DF_RAM_rd_addr_blk4x4 <= 5'd19; + 6'd40:rec_DF_RAM_rd_addr_blk4x4 <= 5'd20; + 6'd41:rec_DF_RAM_rd_addr_blk4x4 <= 5'd21; + 6'd42:rec_DF_RAM_rd_addr_blk4x4 <= 5'd22; + 6'd43:rec_DF_RAM_rd_addr_blk4x4 <= 5'd23; + default:rec_DF_RAM_rd_addr_blk4x4 <= 0; + endcase + else + rec_DF_RAM_rd_addr_blk4x4 <= 0; + + assign rec_DF_RAM_rd_addr_offset = one_edge_counter_MR; + assign rec_DF_RAM_rd_addr = {rec_DF_RAM_rd_addr_blk4x4,2'b0} + rec_DF_RAM_rd_addr_offset; + + //---------------------------------------------------------------------------------- + //Generate control signals for rec_DF_RAM0 & rec_DF_RAM1 + //---------------------------------------------------------------------------------- + reg rec_DF_RAM_sel; //0:rec_DF_RAM0 at reconstruction stage + //0:rec_DF_RAM1 at DF stage + //1:rec_DF_RAM0 at DF stage + //1:rec_DF_RAM1 at reconstruction stage + always @ (posedge clk) + if (reset_n == 1'b0) + rec_DF_RAM_sel <= 1'b0; + else if (end_of_MB_DEC) + rec_DF_RAM_sel <= ~ rec_DF_RAM_sel; + + assign rec_DF_RAM_dout = (rec_DF_RAM_sel == 1'b0)? rec_DF_RAM1_dout:rec_DF_RAM0_dout; + + always @ (rec_DF_RAM_sel + or rec_DF_RAM_wr or rec_DF_RAM_wr_addr or rec_DF_RAM_din + or rec_DF_RAM_rd or rec_DF_RAM_rd_addr) + case (rec_DF_RAM_sel) + 1'b0: //rec_DF_RAM0 at reconstruction stage,rec_DF_RAM1 at DF stage + begin + rec_DF_RAM0_wr <= rec_DF_RAM_wr; + rec_DF_RAM0_rd <= 1'b0; + rec_DF_RAM0_addr <= rec_DF_RAM_wr_addr; + rec_DF_RAM0_din <= rec_DF_RAM_din; + + rec_DF_RAM1_wr <= 1'b0; + rec_DF_RAM1_rd <= rec_DF_RAM_rd; + rec_DF_RAM1_addr <= rec_DF_RAM_rd_addr; + rec_DF_RAM1_din <= 0; + end + 1'b1: //rec_DF_RAM0 at DF stage,rec_DF_RAM1 at reconstruction stage + begin + rec_DF_RAM0_wr <= 1'b0; + rec_DF_RAM0_rd <= rec_DF_RAM_rd; + rec_DF_RAM0_addr <= rec_DF_RAM_rd_addr; + rec_DF_RAM0_din <= 0; + + rec_DF_RAM1_wr <= rec_DF_RAM_wr; + rec_DF_RAM1_rd <= 1'b0; + rec_DF_RAM1_addr <= rec_DF_RAM_wr_addr; + rec_DF_RAM1_din <= rec_DF_RAM_din; + end + endcase +endmodule + + + + + + + + + + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/rec_gclk_gen.v b/demo_chip_rtl/rtl/nova/trunk/src/rec_gclk_gen.v new file mode 100644 index 0000000..1d4214c --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/rec_gclk_gen.v @@ -0,0 +1,427 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : rec_gclk_gen.v +// Generated : Jan 3, 2006 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Gated clock generation module for reconstruction +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module rec_gclk_gen(clk, + //IQIT + end_of_NonZeroCoeff_CAVLC,OneD_counter,TwoD_counter,rescale_counter, + rounding_counter,residual_state,cavlc_decoder_state, + gclk_1D,gclk_2D,gclk_rescale,gclk_rounding, + //Intra pred + mb_num_h,mb_num_v,NextMB_IsSkip, + mb_type_general,blk4x4_rec_counter,blk4x4_sum_counter,blk4x4_intra_preload_counter, + blk4x4_intra_precompute_counter,blk4x4_intra_calculate_counter, + Intra4x4_predmode,Intra16x16_predmode,Intra_chroma_predmode, + gclk_intra_mbAddrA_luma,gclk_intra_mbAddrA_Cb,gclk_intra_mbAddrA_Cr, + gclk_intra_mbAddrB,gclk_intra_mbAddrC_luma,gclk_intra_mbAddrD,gclk_seed, + //Inter pred + blk4x4_inter_preload_counter,gclk_Inter_ref_rf, + //sum + Inter_blk4x4_pred_output_valid,gclk_pred_output,gclk_blk4x4_sum, + //Deblocking filter + end_of_MB_DEC,end_of_BS_DEC,DF_duration, + gclk_end_of_MB_DEC,gclk_DF, + //memory + Intra_mbAddrB_RAM_rd,Intra_mbAddrB_RAM_wr,gclk_Intra_mbAddrB_RAM, + rec_DF_RAM0_cs_n,gclk_rec_DF_RAM0, + rec_DF_RAM1_cs_n,gclk_rec_DF_RAM1, + DF_mbAddrA_RF_rd,DF_mbAddrA_RF_wr,gclk_DF_mbAddrA_RF, + DF_mbAddrB_RAM_rd,DF_mbAddrB_RAM_wr,gclk_DF_mbAddrB_RAM + ); + input clk; + //IQIT + input end_of_NonZeroCoeff_CAVLC; + input [2:0] OneD_counter; + input [2:0] TwoD_counter; + input [2:0] rescale_counter; + input [2:0] rounding_counter; + input [3:0] residual_state; + input [3:0] cavlc_decoder_state; + output gclk_1D; + output gclk_2D; + output gclk_rescale; + output gclk_rounding; + //Intra pred + input [3:0] mb_num_h; + input [3:0] mb_num_v; + input NextMB_IsSkip; + input [3:0] mb_type_general; + input [4:0] blk4x4_rec_counter; + input [2:0] blk4x4_sum_counter; + input [2:0] blk4x4_intra_preload_counter; + input [3:0] blk4x4_intra_precompute_counter; + input [2:0] blk4x4_intra_calculate_counter; + input [3:0] Intra4x4_predmode; + input [1:0] Intra16x16_predmode; + input [1:0] Intra_chroma_predmode; + output gclk_intra_mbAddrA_luma; + output gclk_intra_mbAddrA_Cb; + output gclk_intra_mbAddrA_Cr; + output gclk_intra_mbAddrB; + output gclk_intra_mbAddrC_luma; + output gclk_intra_mbAddrD; + output gclk_seed; + //Inter pred + input [5:0] blk4x4_inter_preload_counter; + output gclk_Inter_ref_rf; + //sum + input [1:0] Inter_blk4x4_pred_output_valid; + output gclk_pred_output; + output gclk_blk4x4_sum; + //DF + input end_of_MB_DEC; + input end_of_BS_DEC; + input DF_duration; + output gclk_end_of_MB_DEC; + output gclk_DF; + //memory + input Intra_mbAddrB_RAM_rd; + input Intra_mbAddrB_RAM_wr; + output gclk_Intra_mbAddrB_RAM; + input rec_DF_RAM0_cs_n; + output gclk_rec_DF_RAM0; + input rec_DF_RAM1_cs_n; + output gclk_rec_DF_RAM1; + input DF_mbAddrA_RF_rd,DF_mbAddrA_RF_wr; + output gclk_DF_mbAddrA_RF; + input DF_mbAddrB_RAM_rd,DF_mbAddrB_RAM_wr; + output gclk_DF_mbAddrB_RAM; + + parameter rst_residual = 4'b0000; + parameter Intra16x16DCLevel_s = 4'b0001; + parameter Intra16x16ACLevel_s = 4'b0011; + parameter Intra16x16ACLevel_0_s = 4'b0010; + parameter LumaLevel_s = 4'b0110; + parameter LumaLevel_0_s = 4'b0111; + parameter ChromaDCLevel_Cb_s = 4'b0101; + parameter ChromaDCLevel_Cr_s = 4'b0100; + parameter ChromaACLevel_Cb_s = 4'b1100; + parameter ChromaACLevel_Cr_s = 4'b1101; + + parameter Intra4x4_Vertical = 4'b0000; + parameter Intra4x4_Horizontal = 4'b0001; + parameter Intra4x4_DC = 4'b0010; + parameter Intra4x4_Diagonal_Down_Left = 4'b0011; + parameter Intra4x4_Diagonal_Down_Right = 4'b0100; + parameter Intra4x4_Vertical_Right = 4'b0101; + parameter Intra4x4_Horizontal_Down = 4'b0110; + parameter Intra4x4_Vertical_Left = 4'b0111; + parameter Intra4x4_Horizontal_Up = 4'b1000; + + parameter Intra16x16_Plane = 2'b11; + parameter Intra_chroma_Plane = 2'b11; + + parameter NumCoeffTrailingOnes_LUT = 4'b0010; + //------------------------------------------------- + //IQIT + //------------------------------------------------- + //gclk_end_of_one_residual_block + //reg l_end_of_one_residual_block; + //wire gclk_end_of_one_residual_block; + //always @ (clk or end_of_one_residual_block) + // if (!clk) l_end_of_one_residual_block <= end_of_one_residual_block; + //assign gclk_end_of_one_residual_block = clk & l_end_of_one_residual_block; + + //gclk_endof1NonZeroCoeffResBlk + //reg l_end_of_NonZeroCoeff_CAVLC; + //wire gclk_endof1NonZeroCoeffResBlk; + //always @ (clk or end_of_NonZeroCoeff_CAVLC) + // if (!clk) l_end_of_NonZeroCoeff_CAVLC <= end_of_NonZeroCoeff_CAVLC; + //assign gclk_endof1NonZeroCoeffResBlk = clk & l_end_of_NonZeroCoeff_CAVLC; + + //gclk_1D + wire OneD_en; + reg l_OneD_en; + wire gclk_1D; + assign OneD_en = ( + // trap DC case after CAVLC:residual_state is still available now + (end_of_NonZeroCoeff_CAVLC == 1'b1 && cavlc_decoder_state != `NumCoeffTrailingOnes_LUT && + (residual_state == `Intra16x16DCLevel_s || residual_state == `ChromaDCLevel_Cb_s || + residual_state == `ChromaDCLevel_Cr_s)) || + // trap AC case after rescale:residual_state is still available now + ((residual_state == `Intra16x16ACLevel_s || residual_state == `LumaLevel_s || residual_state == `ChromaACLevel_Cb_s || + residual_state == `ChromaACLevel_Cr_s) && rescale_counter == 3'b100) || + // trap internal loop + OneD_counter != 0); + always @ (clk or OneD_en) + if (!clk) l_OneD_en <= OneD_en; + assign gclk_1D = clk & l_OneD_en; + + //gclk_2D + wire TwoD_en; + reg l_TwoD_en; + wire gclk_2D; + assign TwoD_en = ((OneD_counter == 3'b001 && residual_state != `ChromaDCLevel_Cb_s && residual_state != `ChromaDCLevel_Cr_s) + || TwoD_counter != 0); + always @ (clk or TwoD_en) + if (!clk) l_TwoD_en <= TwoD_en; + assign gclk_2D = clk & l_TwoD_en; + + //gclk_rescale + wire rescale_en; + reg l_rescale_en; + wire gclk_rescale; + assign rescale_en = ( + //trap AC after CAVLC except all zero coeffs case + (end_of_NonZeroCoeff_CAVLC == 1'b1 && cavlc_decoder_state != `NumCoeffTrailingOnes_LUT && ( + residual_state == `Intra16x16ACLevel_s || residual_state == `LumaLevel_s || + residual_state == `ChromaACLevel_Cb_s || residual_state == `ChromaACLevel_Cr_s)) || + //trap DC case after IDCT,chromaDC:after 1D-IDCT,lumaDC:after 2D-IDCT + ((residual_state == `Intra16x16DCLevel_s && TwoD_counter == 3'b100) || + ((residual_state == `ChromaDCLevel_Cb_s || residual_state == `ChromaDCLevel_Cr_s) && OneD_counter == 3'b001)) || + //trap internal loop + rescale_counter != 0); + always @ (clk or rescale_en) + if (!clk) l_rescale_en <= rescale_en; + and gc_rescale (gclk_rescale,clk,l_rescale_en); + + //gclk_rounding + wire rounding_en; + reg l_rounding_en; + wire gclk_rounding; + assign rounding_en = (((residual_state == `Intra16x16ACLevel_s || residual_state == `LumaLevel_s || + residual_state == `ChromaACLevel_Cb_s || residual_state == `ChromaACLevel_Cr_s) && TwoD_counter == 3'b100) + || rounding_counter !=0)?1'b1:1'b0; + always @ (clk or rounding_en) + if (!clk) l_rounding_en <= rounding_en; + assign gclk_rounding = clk & l_rounding_en; + //------------------------------------------------- + //Intra pred + //------------------------------------------------- + //1.gclk_intra_mbAddrA_luma @ Intra_pred_reg_ctrl.v + // For intra pred,update after every blk4x4 is summed + // For inter pred,update after blk4x4 5,7,13,15 is summed + wire intra_mbAddrA_luma_ena; + reg l_intra_mbAddrA_luma_ena; + wire gclk_intra_mbAddrA_luma; + wire Is_LumaRightMostBlk4x4; + + assign Is_LumaRightMostBlk4x4 = (blk4x4_rec_counter == 5 || blk4x4_rec_counter == 7 || + blk4x4_rec_counter == 13 || blk4x4_rec_counter == 15); + + assign intra_mbAddrA_luma_ena = (blk4x4_rec_counter < 16 && blk4x4_sum_counter == 3'd3 && ( + //Intra4x4:update when every blk4x4 summed + (mb_type_general[3:2] == 2'b11 && !(mb_num_h == 10 && Is_LumaRightMostBlk4x4)) || + //Intra16x16 && Inter (including skip MB):update when blk4x4 5/7/13/15 is summed + //and NextMB_IsSkip is false + (mb_type_general[3:2] != 2'b11 && mb_num_h != 10 && Is_LumaRightMostBlk4x4 && !NextMB_IsSkip))); + always @ (clk or intra_mbAddrA_luma_ena) + if (!clk) l_intra_mbAddrA_luma_ena <= intra_mbAddrA_luma_ena; + assign gclk_intra_mbAddrA_luma = l_intra_mbAddrA_luma_ena & clk; + + //2.gclk_intra_mbAddrA_Cb @ Intra_pred_reg_ctrl.v + wire intra_mbAddrA_Cb_ena; + reg l_intra_mbAddrA_Cb_ena; + wire gclk_intra_mbAddrA_Cb; + wire Is_CbRightMostBlk4x4; + assign Is_CbRightMostBlk4x4 = (blk4x4_rec_counter == 17 || blk4x4_rec_counter == 19); + + assign intra_mbAddrA_Cb_ena = (blk4x4_sum_counter == 3'd3 && ( + //Intra4x4 + (mb_type_general[3:2] == 2'b11 && mb_num_h != 10 && Is_CbRightMostBlk4x4) || + //Intra16x16 && Inter (including skip MB) + (mb_type_general[3:2] != 2'b11 && mb_num_h != 10 && Is_CbRightMostBlk4x4 && !NextMB_IsSkip))); + always @ (clk or intra_mbAddrA_Cb_ena) + if (!clk) l_intra_mbAddrA_Cb_ena <= intra_mbAddrA_Cb_ena; + assign gclk_intra_mbAddrA_Cb = l_intra_mbAddrA_Cb_ena & clk; + + //3.gclk_intra_mbAddrA_Cr @ Intra_pred_reg_ctrl.v + wire intra_mbAddrA_Cr_ena; + reg l_intra_mbAddrA_Cr_ena; + wire gclk_intra_mbAddrA_Cr; + wire Is_CrRightMostBlk4x4; + assign Is_CrRightMostBlk4x4 = (blk4x4_rec_counter == 21 || blk4x4_rec_counter == 23); + assign intra_mbAddrA_Cr_ena = (blk4x4_sum_counter == 3'd3 && ( + //Intra4x4 + (mb_type_general[3:2] == 2'b11 && mb_num_h != 10 && Is_CrRightMostBlk4x4) || + //Intra16x16 && Inter (including skip MB) + (mb_type_general[3:2] != 2'b11 && mb_num_h != 10 && Is_CrRightMostBlk4x4 && !NextMB_IsSkip))); + always @ (clk or intra_mbAddrA_Cr_ena) + if (!clk) l_intra_mbAddrA_Cr_ena <= intra_mbAddrA_Cr_ena; + assign gclk_intra_mbAddrA_Cr = l_intra_mbAddrA_Cr_ena & clk; + + //4.gclk_intra_mbAddrB @ Intra_pred_reg_ctrl.v + // Control the write of Intra_mbAddrB_reg0 ~ reg 15 + wire intra_mbAddrB_ena; + reg l_intra_mbAddrB_ena; + wire gclk_intra_mbAddrB; + assign intra_mbAddrB_ena = ( + // Intra4x4 + (mb_type_general[3:2] == 2'b11 && blk4x4_rec_counter < 16 && + (blk4x4_intra_preload_counter == 1 || blk4x4_sum_counter[2] != 1'b1)) || + // Intra16x16 + (mb_type_general[3:2] == 2'b10 && blk4x4_rec_counter < 16 && blk4x4_intra_preload_counter !=0) || + // Intra chroma + (mb_type_general[3] == 1'b1 && blk4x4_rec_counter > 15 && blk4x4_intra_preload_counter !=0)); + always @ (clk or intra_mbAddrB_ena) + if (!clk) l_intra_mbAddrB_ena <= intra_mbAddrB_ena; + assign gclk_intra_mbAddrB = l_intra_mbAddrB_ena & clk; + + //5.gclk_intra_mbAddrC_luma @ Intra_pred_reg_ctrl.v + //1)For blkIdx=0/1/4/5,Intra_mbAddrC_reg are loaded from Intra_mbAddrB_RAM + //2)For blkIdx other than 0/1/4/5,Intra_mbAddrC_reg directly obtained from Intra_mbAddrB_reg + wire intra_mbAddrC_luma_ena; + reg l_intra_mbAddrC_luma_ena; + wire gclk_intra_mbAddrC_luma; + assign intra_mbAddrC_luma_ena = (mb_type_general[3:2] == 2'b11 && (Intra4x4_predmode == Intra4x4_Diagonal_Down_Left + || Intra4x4_predmode == Intra4x4_Vertical_Left) && blk4x4_intra_preload_counter == 3'b010); + always @ (clk or intra_mbAddrC_luma_ena) + if (!clk) l_intra_mbAddrC_luma_ena <= intra_mbAddrC_luma_ena; + assign gclk_intra_mbAddrC_luma = l_intra_mbAddrC_luma_ena & clk; + + //6.gclk_intra_mbAddrD @ Intra_pred_reg_ctrl.v + //1)For Intra4x4 blkIdx=1/4/5 or Intra16x16 & Chrom plane mode,Intra mbAddrD regs are loaded from + // Intra_mbAddrB_RAM. + //2)For blkIdx other than 1/4/5,Intra mbAddrD reg are updated during sum + wire intra_mbAddrD_ena; + reg l_intra_mbAddrD_ena; + wire gclk_intra_mbAddrD; + assign intra_mbAddrD_ena = ( + //1.Update when blkIdx = 15,19,23,from Intra_mbAddrB_RAM + // In reality,sum_counter = 0/1/2/3 are all OK for update,we choose sum_counter = 0 here + (blk4x4_sum_counter == 3'd1 && mb_num_h != 10 && mb_num_v != 0 && !NextMB_IsSkip && + (blk4x4_rec_counter == 15 || blk4x4_rec_counter == 19 || blk4x4_rec_counter == 23)) || + (mb_type_general[3:2] == 2'b11 && ( + //2.For blk4x4 1/4/5 mbAddrD reg update from Intra_mbAddrB_RAM + (blk4x4_intra_preload_counter == 3'b010 && + (Intra4x4_predmode == Intra4x4_Diagonal_Down_Right || Intra4x4_predmode == Intra4x4_Vertical_Right + || Intra4x4_predmode == Intra4x4_Horizontal_Down)) || + //3.For other blk4x4 mbAddrD reg update from sum output + (blk4x4_sum_counter == 3'd3 && ( + blk4x4_rec_counter == 0 || blk4x4_rec_counter == 1 || blk4x4_rec_counter == 4 || + blk4x4_rec_counter == 2 || blk4x4_rec_counter == 3 || blk4x4_rec_counter == 6 || + blk4x4_rec_counter == 8 || blk4x4_rec_counter == 9 || blk4x4_rec_counter == 12))))); + always @ (clk or intra_mbAddrD_ena) + if (!clk) l_intra_mbAddrD_ena <= intra_mbAddrD_ena; + assign gclk_intra_mbAddrD = l_intra_mbAddrD_ena & clk; + + //7.gclk_seed @ Intra_pred_reg_ctrl.v + wire seed_ena; + reg l_seed_ena; + wire gclk_seed; + //assign seed_ena = (blk4x4_intra_precompute_counter == 1 || ((Intra16x16_predmode == Intra16x16_Plane || + //Intra_chroma_predmode == Intra_chroma_Plane) && blk4x4_intra_calculate_counter == 3)); + + assign seed_ena = (blk4x4_intra_precompute_counter == 1 || ( + (Intra16x16_predmode == Intra16x16_Plane && ( + ((blk4x4_rec_counter == 0 || blk4x4_rec_counter == 2 || blk4x4_rec_counter == 8) && + blk4x4_intra_calculate_counter == 3'b100) || + ((blk4x4_rec_counter == 1 || blk4x4_rec_counter == 3 || blk4x4_rec_counter == 9 || + blk4x4_rec_counter == 11) && blk4x4_intra_calculate_counter == 3'b001))) || + (Intra_chroma_predmode == Intra_chroma_Plane && ( + (blk4x4_rec_counter == 16 || blk4x4_rec_counter == 20) && blk4x4_intra_calculate_counter == 3'b100)))); + + always @ (clk or seed_ena) + if (!clk) l_seed_ena <= seed_ena; + assign gclk_seed = l_seed_ena & clk; + + //------------------------------------------------- + //Inter pred + //------------------------------------------------- + wire Inter_ref_rf_ena; + reg l_Inter_ref_rf_ena; + wire gclk_Inter_ref_rf; + assign Inter_ref_rf_ena = (blk4x4_inter_preload_counter == 0)? 1'b0:1'b1; + always @ (clk or Inter_ref_rf_ena) + if (!clk) l_Inter_ref_rf_ena <= Inter_ref_rf_ena; + assign gclk_Inter_ref_rf = l_Inter_ref_rf_ena & clk; + + //------------------------------------------------- + //sum + //------------------------------------------------- + //1.gclk_pred_output + wire pred_output_ena; + reg l_pred_output_ena; + wire gclk_pred_output; + assign pred_output_ena = (blk4x4_intra_calculate_counter != 0 || Inter_blk4x4_pred_output_valid != 0)? 1'b1:1'b0; + always @ (clk or pred_output_ena) + if (!clk) l_pred_output_ena <= pred_output_ena; + assign gclk_pred_output = l_pred_output_ena & clk; + + //2.gclk_blk4x4_sum + wire blk4x4_sum_ena; + reg l_blk4x4_sum_ena; + wire gclk_blk4x4_sum; + assign blk4x4_sum_ena = (blk4x4_sum_counter[2] != 1'b1); + always @ (clk or blk4x4_sum_ena) + if (!clk) l_blk4x4_sum_ena <= blk4x4_sum_ena; + assign gclk_blk4x4_sum = l_blk4x4_sum_ena & clk; + + //------------------------------------------------- + //deblocking filter + //------------------------------------------------- + //1.gclk_end_of_MB_DEC + reg l_end_of_MB_DEC; + wire gclk_end_of_MB_DEC; + always @ (clk or end_of_MB_DEC) + if (!clk) l_end_of_MB_DEC <= end_of_MB_DEC; + assign gclk_end_of_MB_DEC = l_end_of_MB_DEC & clk; + //2.gclk_DF + wire DF_ena; + reg l_DF_ena; + assign DF_ena = DF_duration | end_of_BS_DEC; + always @ (clk or DF_ena) + if (!clk) l_DF_ena <= DF_ena; + assign gclk_DF = l_DF_ena & clk; + + //------------------------------------------------- + //memory + //------------------------------------------------- + //gclk_Intra_mbAddrB_RAM + wire Intra_mbAddrB_RAM_ena; + reg l_Intra_mbAddrB_RAM_ena; + wire gclk_Intra_mbAddrB_RAM; + assign Intra_mbAddrB_RAM_ena = Intra_mbAddrB_RAM_rd | Intra_mbAddrB_RAM_wr; + always @ (clk or Intra_mbAddrB_RAM_ena) + if (!clk) l_Intra_mbAddrB_RAM_ena <= Intra_mbAddrB_RAM_ena; + assign gclk_Intra_mbAddrB_RAM = clk & l_Intra_mbAddrB_RAM_ena; + + //gclk_rec_DF_RAM0 + reg l_rec_DF_RAM0_ena; + wire gclk_rec_DF_RAM0; + always @ (clk or rec_DF_RAM0_cs_n) + if (!clk) l_rec_DF_RAM0_ena <= !rec_DF_RAM0_cs_n; + assign gclk_rec_DF_RAM0 = clk & l_rec_DF_RAM0_ena; + + //gclk_rec_DF_RAM1 + reg l_rec_DF_RAM1_ena; + wire gclk_rec_DF_RAM1; + always @ (clk or rec_DF_RAM1_cs_n) + if (!clk) l_rec_DF_RAM1_ena <= !rec_DF_RAM1_cs_n; + assign gclk_rec_DF_RAM1 = clk & l_rec_DF_RAM1_ena; + + //gclk_DF_mbAddrA_RF + wire DF_mbAddrA_RF_ena; + reg l_DF_mbAddrA_RF_ena; + wire gclk_DF_mbAddrA_RF; + assign DF_mbAddrA_RF_ena = DF_mbAddrA_RF_rd | DF_mbAddrA_RF_wr; + always @ (clk or DF_mbAddrA_RF_ena) + if (!clk) l_DF_mbAddrA_RF_ena <= DF_mbAddrA_RF_ena; + assign gclk_DF_mbAddrA_RF = clk & l_DF_mbAddrA_RF_ena; + + //gclk_DF_mbAddrB_RAM + wire DF_mbAddrB_RAM_ena; + reg l_DF_mbAddrB_RAM_ena; + wire gclk_DF_mbAddrB_RAM; + assign DF_mbAddrB_RAM_ena = DF_mbAddrB_RAM_rd | DF_mbAddrB_RAM_wr; + always @ (clk or DF_mbAddrB_RAM_ena) + if (!clk) l_DF_mbAddrB_RAM_ena <= DF_mbAddrB_RAM_ena; + assign gclk_DF_mbAddrB_RAM = clk & l_DF_mbAddrB_RAM_ena; + + +endmodule + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/reconstruction.v b/demo_chip_rtl/rtl/nova/trunk/src/reconstruction.v new file mode 100644 index 0000000..178ea1f --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/reconstruction.v @@ -0,0 +1,626 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : reconstruction.v +// Generated : Jan 3,2006 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// reconstruction top module,including: +// rec_gclk_gen +// hybrid_pipeline_ctrl +// IQIT +// Intra_pred_top +// sum +// DF_top +// rec_DF_RAM_ctrl +// rec_DF_RAM0 +// rec_DF_RAM1 +// ext_RAM_ctrl +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module reconstruction (clk,reset_n,mb_type_general,mb_num_h,mb_num_v,NextMB_IsSkip,LowerMB_IsSkip, + slice_data_state,residual_state,cavlc_decoder_state, + end_of_one_residual_block,end_of_NonZeroCoeff_CAVLC,end_of_one_frame, + Intra16x16_predmode,Intra4x4_predmode_CurrMb,Intra_chroma_predmode, + QPy,QPc,i4x4_CbCr,slice_alpha_c0_offset_div2,slice_beta_offset_div2, + CodedBlockPatternLuma,CodedBlockPatternChroma,TotalCoeff,Is_skip_run_entry, + skip_mv_calc,disable_DF, + + coeffLevel_0,coeffLevel_1,coeffLevel_2, coeffLevel_3, coeffLevel_4, coeffLevel_5, coeffLevel_6, coeffLevel_7, + coeffLevel_8,coeffLevel_9,coeffLevel_10,coeffLevel_11,coeffLevel_12,coeffLevel_13,coeffLevel_14,coeffLevel_15, + mv_is16x16,mv_below8x8, + mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3,mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3, + end_of_BS_DEC,bs_V0,bs_V1,bs_V2,bs_V3,bs_H0,bs_H1,bs_H2,bs_H3, + + trigger_CAVLC,blk4x4_rec_counter,end_of_DCBlk_IQIT,end_of_one_blk4x4_sum, + end_of_MB_DEC,gclk_end_of_MB_DEC,curr_DC_IsZero, + ext_frame_RAM0_cs_n,ext_frame_RAM0_wr,ext_frame_RAM0_addr,ext_frame_RAM0_data, + ext_frame_RAM1_cs_n,ext_frame_RAM1_wr,ext_frame_RAM1_addr,ext_frame_RAM1_data, + dis_frame_RAM_din + ); + input clk; + input reset_n; + input [3:0] mb_type_general; + input [3:0] mb_num_h; + input [3:0] mb_num_v; + input NextMB_IsSkip; + input LowerMB_IsSkip; + input [3:0] slice_data_state; + input [3:0] residual_state; + input [3:0] cavlc_decoder_state; + input end_of_one_residual_block; + input end_of_NonZeroCoeff_CAVLC; + input end_of_one_frame; + input [1:0] Intra16x16_predmode; + input [63:0] Intra4x4_predmode_CurrMb; + input [1:0] Intra_chroma_predmode; + input [5:0] QPy; + input [5:0] QPc; + input [1:0] i4x4_CbCr; + input [3:0] slice_alpha_c0_offset_div2; + input [3:0] slice_beta_offset_div2; + input [3:0] CodedBlockPatternLuma; + input [1:0] CodedBlockPatternChroma; + input [4:0] TotalCoeff; + input Is_skip_run_entry; + input skip_mv_calc; + input disable_DF; + input [8:0] coeffLevel_0, coeffLevel_1, coeffLevel_2,coeffLevel_3, coeffLevel_4, coeffLevel_5; + input [8:0] coeffLevel_6, coeffLevel_7, coeffLevel_8, coeffLevel_9,coeffLevel_10,coeffLevel_11; + input [8:0] coeffLevel_12,coeffLevel_13,coeffLevel_14,coeffLevel_15; + input mv_is16x16; + input [3:0] mv_below8x8; + input [31:0] mvx_CurrMb0,mvx_CurrMb1,mvx_CurrMb2,mvx_CurrMb3; + input [31:0] mvy_CurrMb0,mvy_CurrMb1,mvy_CurrMb2,mvy_CurrMb3; + input end_of_BS_DEC; + input [11:0] bs_V0,bs_V1,bs_V2,bs_V3; + input [11:0] bs_H0,bs_H1,bs_H2,bs_H3; + input [31:0] ext_frame_RAM0_data; + input [31:0] ext_frame_RAM1_data; + + output trigger_CAVLC; + output [4:0] blk4x4_rec_counter; + output end_of_DCBlk_IQIT; + output end_of_one_blk4x4_sum; + output end_of_MB_DEC; + output gclk_end_of_MB_DEC; + output curr_DC_IsZero; + + output ext_frame_RAM0_cs_n; + output ext_frame_RAM0_wr; + output [13:0] ext_frame_RAM0_addr; + + output ext_frame_RAM1_cs_n; + output ext_frame_RAM1_wr; + output [13:0] ext_frame_RAM1_addr; + + output [31:0] dis_frame_RAM_din; + + wire gclk_endof1resblk; + wire gclk_1D; + wire gclk_2D; + wire gclk_rescale; + wire gclk_rounding; + wire gclk_intra_mbAddrA_luma; + wire gclk_intra_mbAddrA_Cb; + wire gclk_intra_mbAddrA_Cr; + wire gclk_intra_mbAddrB; + wire gclk_intra_mbAddrC_luma; + wire gclk_intra_mbAddrD; + wire gclk_seed; + wire gclk_Inter_ref_rf; + wire gclk_pred_output; + wire gclk_blk4x4_sum; + wire gclk_DF; + wire gclk_end_of_MB_DEC; + + wire curr_CBPLuma_IsZero; + wire curr_DC_IsZero; + wire end_of_ACBlk4x4_IQIT; + wire end_of_one_blk4x4_intra; + wire end_of_one_blk4x4_inter; + wire end_of_one_blk4x4_sum; + wire end_of_MB_DF; + wire end_of_MB_DEC; + wire trigger_blk4x4_intra_pred; + wire trigger_blk4x4_inter_pred; + wire trigger_blk4x4_rec_sum; + wire [15:0] res_luma_DConly; + wire res_chroma_DConly; + wire res_AC; + wire res_DC; + wire res_luma; + wire [2:0] OneD_counter; + wire [2:0] TwoD_counter; + wire [2:0] rescale_counter; + wire [2:0] rounding_counter; + wire [2:0] blk4x4_intra_preload_counter; + wire [3:0] blk4x4_intra_precompute_counter; + wire [2:0] blk4x4_intra_calculate_counter; + wire [5:0] blk4x4_inter_preload_counter; + wire [3:0] blk4x4_inter_calculate_counter; + wire [1:0] Inter_chroma2x2_counter; + wire [4:0] blk4x4_rec_counter; + wire [2:0] blk4x4_sum_counter; + wire [4:0] blk4x4_rec_counter_2_raster_order; + wire [5:0] DF_edge_counter_MR; + wire [1:0] one_edge_counter_MR; + wire [1:0] Inter_blk4x4_pred_output_valid; + wire mv_below8x8_curr; + wire [3:0] pos_FracL; + + wire [3:0] Intra4x4_predmode; + wire [8:0] IQIT_output_0, IQIT_output_1, IQIT_output_2, IQIT_output_3; + wire [8:0] IQIT_output_4, IQIT_output_5, IQIT_output_6, IQIT_output_7; + wire [8:0] IQIT_output_8, IQIT_output_9, IQIT_output_10,IQIT_output_11; + wire [8:0] IQIT_output_12,IQIT_output_13,IQIT_output_14,IQIT_output_15; + wire [7:0] Intra_pred_PE0_out,Intra_pred_PE1_out,Intra_pred_PE2_out,Intra_pred_PE3_out; + wire [7:0] Inter_pred_out0,Inter_pred_out1,Inter_pred_out2,Inter_pred_out3; + wire [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out; + wire [7:0] blk4x4_pred_output0, blk4x4_pred_output1, blk4x4_pred_output2; + wire [7:0] blk4x4_pred_output4, blk4x4_pred_output5, blk4x4_pred_output6; + wire [7:0] blk4x4_pred_output8, blk4x4_pred_output9, blk4x4_pred_output10; + wire [7:0] blk4x4_pred_output12,blk4x4_pred_output13,blk4x4_pred_output14; + wire [8:0] curr_DC_scaled; + wire [23:0] sum_right_column_reg; + + wire DF_duration; + wire gclk_Intra_mbAddrB_RAM; + wire Intra_mbAddrB_RAM_rd; + wire Intra_mbAddrB_RAM_wr; + wire [6:0] Intra_mbAddrB_RAM_rd_addr,Intra_mbAddrB_RAM_wr_addr; + wire [31:0] Intra_mbAddrB_RAM_din; + wire [31:0] Intra_mbAddrB_RAM_dout; + wire gclk_DF_mbAddrA_RF; + wire DF_mbAddrA_RF_rd; + wire DF_mbAddrA_RF_wr; + wire [4:0] DF_mbAddrA_RF_rd_addr; + wire [4:0] DF_mbAddrA_RF_wr_addr; + wire [31:0] DF_mbAddrA_RF_din; + wire [31:0] DF_mbAddrA_RF_dout; + wire gclk_DF_mbAddrB_RAM; + wire DF_mbAddrB_RAM_rd,DF_mbAddrB_RAM_wr; + wire [8:0] DF_mbAddrB_RAM_addr; + wire [31:0] DF_mbAddrB_RAM_din; + wire [31:0] DF_mbAddrB_RAM_dout; + wire gclk_rec_DF_RAM0,gclk_rec_DF_RAM1; + wire [31:0] rec_DF_RAM_dout; + wire rec_DF_RAM0_wr,rec_DF_RAM1_wr; + wire rec_DF_RAM0_rd,rec_DF_RAM1_rd; + wire [6:0] rec_DF_RAM0_addr,rec_DF_RAM1_addr; + wire [31:0] rec_DF_RAM0_din,rec_DF_RAM1_din; + wire [31:0] rec_DF_RAM0_dout,rec_DF_RAM1_dout; + wire dis_frame_RAM_wr; + wire [13:0] dis_frame_RAM_wr_addr; + wire [31:0] dis_frame_RAM_din; + wire ref_frame_RAM_rd; + wire [13:0] ref_frame_RAM_rd_addr; + wire [31:0] ref_frame_RAM_dout; + + + rec_gclk_gen rec_gclk_gen ( + .clk(clk), + .end_of_NonZeroCoeff_CAVLC(end_of_NonZeroCoeff_CAVLC), + .OneD_counter(OneD_counter), + .TwoD_counter(TwoD_counter), + .rescale_counter(rescale_counter), + .rounding_counter(rounding_counter), + .residual_state(residual_state), + .cavlc_decoder_state(cavlc_decoder_state), + .gclk_1D(gclk_1D), + .gclk_2D(gclk_2D), + .gclk_rescale(gclk_rescale), + .gclk_rounding(gclk_rounding), + .mb_num_h(mb_num_h), + .mb_num_v(mb_num_v), + .NextMB_IsSkip(NextMB_IsSkip), + .mb_type_general(mb_type_general), + .blk4x4_rec_counter(blk4x4_rec_counter), + .blk4x4_sum_counter(blk4x4_sum_counter), + .blk4x4_intra_preload_counter(blk4x4_intra_preload_counter), + .blk4x4_intra_precompute_counter(blk4x4_intra_precompute_counter), + .blk4x4_intra_calculate_counter(blk4x4_intra_calculate_counter), + .Intra4x4_predmode(Intra4x4_predmode), + .Intra16x16_predmode(Intra16x16_predmode), + .Intra_chroma_predmode(Intra_chroma_predmode), + .gclk_intra_mbAddrA_luma(gclk_intra_mbAddrA_luma), + .gclk_intra_mbAddrA_Cb(gclk_intra_mbAddrA_Cb), + .gclk_intra_mbAddrA_Cr(gclk_intra_mbAddrA_Cr), + .gclk_intra_mbAddrB(gclk_intra_mbAddrB), + .gclk_intra_mbAddrC_luma(gclk_intra_mbAddrC_luma), + .gclk_intra_mbAddrD(gclk_intra_mbAddrD), + .gclk_seed(gclk_seed), + .blk4x4_inter_preload_counter(blk4x4_inter_preload_counter), + .gclk_Inter_ref_rf(gclk_Inter_ref_rf), + .Inter_blk4x4_pred_output_valid(Inter_blk4x4_pred_output_valid), + .gclk_pred_output(gclk_pred_output), + .gclk_blk4x4_sum(gclk_blk4x4_sum), + .end_of_MB_DEC(end_of_MB_DEC), + .end_of_BS_DEC(end_of_BS_DEC), + .DF_duration(DF_duration), + .gclk_end_of_MB_DEC(gclk_end_of_MB_DEC), + .gclk_DF(gclk_DF), + .Intra_mbAddrB_RAM_rd(Intra_mbAddrB_RAM_rd), + .Intra_mbAddrB_RAM_wr(Intra_mbAddrB_RAM_wr), + .gclk_Intra_mbAddrB_RAM(gclk_Intra_mbAddrB_RAM), + .rec_DF_RAM0_cs_n(rec_DF_RAM0_cs_n), + .gclk_rec_DF_RAM0(gclk_rec_DF_RAM0), + .rec_DF_RAM1_cs_n(rec_DF_RAM1_cs_n), + .gclk_rec_DF_RAM1(gclk_rec_DF_RAM1), + .DF_mbAddrA_RF_rd(DF_mbAddrA_RF_rd), + .DF_mbAddrA_RF_wr(DF_mbAddrA_RF_wr), + .gclk_DF_mbAddrA_RF(gclk_DF_mbAddrA_RF), + .DF_mbAddrB_RAM_rd(DF_mbAddrB_RAM_rd), + .DF_mbAddrB_RAM_wr(DF_mbAddrB_RAM_wr), + .gclk_DF_mbAddrB_RAM(gclk_DF_mbAddrB_RAM) + ); + hybrid_pipeline_ctrl hybrid_pipeline_ctrl ( + .clk(clk), + .reset_n(reset_n), + .mb_num_h(mb_num_h), + .mb_num_v(mb_num_v), + .blk4x4_rec_counter(blk4x4_rec_counter), + .CodedBlockPatternLuma(CodedBlockPatternLuma), + .CodedBlockPatternChroma(CodedBlockPatternChroma), + .mb_type_general(mb_type_general), + .slice_data_state(slice_data_state), + .residual_state(residual_state), + .TotalCoeff(TotalCoeff), + .Is_skip_run_entry(Is_skip_run_entry), + .skip_mv_calc(skip_mv_calc), + .end_of_one_residual_block(end_of_one_residual_block), + .end_of_DCBlk_IQIT(end_of_DCBlk_IQIT), + .end_of_ACBlk4x4_IQIT(end_of_ACBlk4x4_IQIT), + .end_of_one_blk4x4_intra(end_of_one_blk4x4_intra), + .end_of_one_blk4x4_inter(end_of_one_blk4x4_inter), + .end_of_one_blk4x4_sum(end_of_one_blk4x4_sum), + .end_of_MB_DF(end_of_MB_DF), + .disable_DF(disable_DF), + + .curr_CBPLuma_IsZero(curr_CBPLuma_IsZero), + .end_of_MB_DEC(end_of_MB_DEC), + .trigger_CAVLC(trigger_CAVLC), + .trigger_blk4x4_intra_pred(trigger_blk4x4_intra_pred), + .trigger_blk4x4_inter_pred(trigger_blk4x4_inter_pred), + .trigger_blk4x4_rec_sum(trigger_blk4x4_rec_sum) + ); + IQIT IQIT ( + .clk(clk), + .reset_n(reset_n), + .TotalCoeff(TotalCoeff), + .blk4x4_rec_counter(blk4x4_rec_counter), + .gclk_1D(gclk_1D), + .gclk_2D(gclk_2D), + .gclk_rescale(gclk_rescale), + .gclk_rounding(gclk_rounding), + .residual_state(residual_state), + .cavlc_decoder_state(cavlc_decoder_state), + .end_of_one_residual_block(end_of_one_residual_block), + .end_of_NonZeroCoeff_CAVLC(end_of_NonZeroCoeff_CAVLC), + .QPy(QPy), + .QPc(QPc), + .i4x4_CbCr(i4x4_CbCr), + .coeffLevel_ext_0({{7{coeffLevel_0[8]}},coeffLevel_0}), + .coeffLevel_ext_1({{7{coeffLevel_1[8]}},coeffLevel_1}), + .coeffLevel_ext_2({{7{coeffLevel_2[8]}},coeffLevel_2}), + .coeffLevel_ext_3({{7{coeffLevel_3[8]}},coeffLevel_3}), + .coeffLevel_ext_4({{7{coeffLevel_4[8]}},coeffLevel_4}), + .coeffLevel_ext_5({{7{coeffLevel_5[8]}},coeffLevel_5}), + .coeffLevel_ext_6({{7{coeffLevel_6[8]}},coeffLevel_6}), + .coeffLevel_ext_7({{7{coeffLevel_7[8]}},coeffLevel_7}), + .coeffLevel_ext_8({{7{coeffLevel_8[8]}},coeffLevel_8}), + .coeffLevel_ext_9({{7{coeffLevel_9[8]}},coeffLevel_9}), + .coeffLevel_ext_10({{7{coeffLevel_10[8]}},coeffLevel_10}), + .coeffLevel_ext_11({{7{coeffLevel_11[8]}},coeffLevel_11}), + .coeffLevel_ext_12({{7{coeffLevel_12[8]}},coeffLevel_12}), + .coeffLevel_ext_13({{7{coeffLevel_13[8]}},coeffLevel_13}), + .coeffLevel_ext_14({{7{coeffLevel_14[8]}},coeffLevel_14}), + .coeffLevel_ext_15({{7{coeffLevel_15[8]}},coeffLevel_15}), + + .OneD_counter(OneD_counter), + .TwoD_counter(TwoD_counter), + .rescale_counter(rescale_counter), + .rounding_counter(rounding_counter), + .curr_DC_IsZero(curr_DC_IsZero), + .curr_DC_scaled(curr_DC_scaled), + .rounding_output_0(IQIT_output_0), + .rounding_output_1(IQIT_output_1), + .rounding_output_2(IQIT_output_2), + .rounding_output_3(IQIT_output_3), + .rounding_output_4(IQIT_output_4), + .rounding_output_5(IQIT_output_5), + .rounding_output_6(IQIT_output_6), + .rounding_output_7(IQIT_output_7), + .rounding_output_8(IQIT_output_8), + .rounding_output_9(IQIT_output_9), + .rounding_output_10(IQIT_output_10), + .rounding_output_11(IQIT_output_11), + .rounding_output_12(IQIT_output_12), + .rounding_output_13(IQIT_output_13), + .rounding_output_14(IQIT_output_14), + .rounding_output_15(IQIT_output_15), + .end_of_ACBlk4x4_IQIT(end_of_ACBlk4x4_IQIT), + .end_of_DCBlk_IQIT(end_of_DCBlk_IQIT) + ); + Intra_pred_top Intra_pred_top ( + .clk(clk), + .reset_n(reset_n), + .gclk_intra_mbAddrA_luma(gclk_intra_mbAddrA_luma), + .gclk_intra_mbAddrA_Cb(gclk_intra_mbAddrA_Cb), + .gclk_intra_mbAddrA_Cr(gclk_intra_mbAddrA_Cr), + .gclk_intra_mbAddrB(gclk_intra_mbAddrB), + .gclk_intra_mbAddrC_luma(gclk_intra_mbAddrC_luma), + .gclk_intra_mbAddrD(gclk_intra_mbAddrD), + .gclk_seed(gclk_seed), + .gclk_Intra_mbAddrB_RAM(gclk_Intra_mbAddrB_RAM), + .mb_num_h(mb_num_h), + .mb_num_v(mb_num_v), + .mb_type_general(mb_type_general), + .NextMB_IsSkip(NextMB_IsSkip), + .Intra16x16_predmode(Intra16x16_predmode), + .Intra4x4_predmode_CurrMb(Intra4x4_predmode_CurrMb), + .Intra_chroma_predmode(Intra_chroma_predmode), + .blk4x4_rec_counter(blk4x4_rec_counter), + .trigger_blk4x4_intra_pred(trigger_blk4x4_intra_pred), + .blk4x4_sum_counter(blk4x4_sum_counter), + .sum_right_column_reg(sum_right_column_reg), + .blk4x4_sum_PE0_out(blk4x4_sum_PE0_out), + .blk4x4_sum_PE1_out(blk4x4_sum_PE1_out), + .blk4x4_sum_PE2_out(blk4x4_sum_PE2_out), + .blk4x4_sum_PE3_out(blk4x4_sum_PE3_out), + .blk4x4_pred_output0(blk4x4_pred_output0), + .blk4x4_pred_output1(blk4x4_pred_output1), + .blk4x4_pred_output2(blk4x4_pred_output2), + .blk4x4_pred_output4(blk4x4_pred_output4), + .blk4x4_pred_output5(blk4x4_pred_output5), + .blk4x4_pred_output6(blk4x4_pred_output6), + .blk4x4_pred_output8(blk4x4_pred_output8), + .blk4x4_pred_output9(blk4x4_pred_output9), + .blk4x4_pred_output10(blk4x4_pred_output10), + .blk4x4_pred_output12(blk4x4_pred_output12), + .blk4x4_pred_output13(blk4x4_pred_output13), + .blk4x4_pred_output14(blk4x4_pred_output14), + .Intra_mbAddrB_RAM_wr(Intra_mbAddrB_RAM_wr), + .Intra_mbAddrB_RAM_wr_addr(Intra_mbAddrB_RAM_wr_addr), + .Intra_mbAddrB_RAM_din(Intra_mbAddrB_RAM_din), + + .PE0_out(Intra_pred_PE0_out), + .PE1_out(Intra_pred_PE1_out), + .PE2_out(Intra_pred_PE2_out), + .PE3_out(Intra_pred_PE3_out), + .Intra4x4_predmode(Intra4x4_predmode), + .blk4x4_intra_preload_counter(blk4x4_intra_preload_counter), + .blk4x4_intra_precompute_counter(blk4x4_intra_precompute_counter), + .blk4x4_intra_calculate_counter(blk4x4_intra_calculate_counter), + .end_of_one_blk4x4_intra(end_of_one_blk4x4_intra), + .Intra_mbAddrB_RAM_rd(Intra_mbAddrB_RAM_rd) + ); + Inter_pred_top Inter_pred_top ( + .clk(clk), + .gclk_Inter_ref_rf(gclk_Inter_ref_rf), + .reset_n(reset_n), + .mb_num_h(mb_num_h), + .mb_num_v(mb_num_v), + .trigger_blk4x4_inter_pred(trigger_blk4x4_inter_pred), + .blk4x4_rec_counter(blk4x4_rec_counter), + .mb_type_general_bit3(mb_type_general[3]), + .mv_is16x16(mv_is16x16), + .mv_below8x8(mv_below8x8), + .mvx_CurrMb0(mvx_CurrMb0), + .mvx_CurrMb1(mvx_CurrMb1), + .mvx_CurrMb2(mvx_CurrMb2), + .mvx_CurrMb3(mvx_CurrMb3), + .mvy_CurrMb0(mvy_CurrMb0), + .mvy_CurrMb1(mvy_CurrMb1), + .mvy_CurrMb2(mvy_CurrMb2), + .mvy_CurrMb3(mvy_CurrMb3), + .ref_frame_RAM_dout(ref_frame_RAM_dout), + + .Inter_pred_out0(Inter_pred_out0), + .Inter_pred_out1(Inter_pred_out1), + .Inter_pred_out2(Inter_pred_out2), + .Inter_pred_out3(Inter_pred_out3), + .blk4x4_inter_preload_counter(blk4x4_inter_preload_counter), + .blk4x4_inter_calculate_counter(blk4x4_inter_calculate_counter), + .Inter_chroma2x2_counter(Inter_chroma2x2_counter), + .mv_below8x8_curr(mv_below8x8_curr), + .pos_FracL(pos_FracL), + .end_of_one_blk4x4_inter(end_of_one_blk4x4_inter), + .Inter_blk4x4_pred_output_valid(Inter_blk4x4_pred_output_valid), + .ref_frame_RAM_rd(ref_frame_RAM_rd), + .ref_frame_RAM_rd_addr(ref_frame_RAM_rd_addr) + ); + sum sum ( + .clk(clk), + .reset_n(reset_n), + .slice_data_state(slice_data_state), + .residual_state(residual_state), + .TotalCoeff(TotalCoeff), + .curr_CBPLuma_IsZero(curr_CBPLuma_IsZero), + .CodedBlockPatternChroma(CodedBlockPatternChroma), + .curr_DC_IsZero(curr_DC_IsZero), + .curr_DC_scaled(curr_DC_scaled), + .gclk_pred_output(gclk_pred_output), + .gclk_blk4x4_sum(gclk_blk4x4_sum), + .trigger_blk4x4_rec_sum(trigger_blk4x4_rec_sum), + .IQIT_output_0(IQIT_output_0), + .IQIT_output_1(IQIT_output_1), + .IQIT_output_2(IQIT_output_2), + .IQIT_output_3(IQIT_output_3), + .IQIT_output_4(IQIT_output_4), + .IQIT_output_5(IQIT_output_5), + .IQIT_output_6(IQIT_output_6), + .IQIT_output_7(IQIT_output_7), + .IQIT_output_8(IQIT_output_8), + .IQIT_output_9(IQIT_output_9), + .IQIT_output_10(IQIT_output_10), + .IQIT_output_11(IQIT_output_11), + .IQIT_output_12(IQIT_output_12), + .IQIT_output_13(IQIT_output_13), + .IQIT_output_14(IQIT_output_14), + .IQIT_output_15(IQIT_output_15), + .mb_type_general(mb_type_general), + .Intra4x4_predmode(Intra4x4_predmode), + .Intra16x16_predmode(Intra16x16_predmode), + .Intra_chroma_predmode(Intra_chroma_predmode), + .Intra_pred_PE0_out(Intra_pred_PE0_out), + .Intra_pred_PE1_out(Intra_pred_PE1_out), + .Intra_pred_PE2_out(Intra_pred_PE2_out), + .Intra_pred_PE3_out(Intra_pred_PE3_out), + .blk4x4_intra_calculate_counter(blk4x4_intra_calculate_counter), + .Inter_pred_out0(Inter_pred_out0), + .Inter_pred_out1(Inter_pred_out1), + .Inter_pred_out2(Inter_pred_out2), + .Inter_pred_out3(Inter_pred_out3), + .blk4x4_inter_calculate_counter(blk4x4_inter_calculate_counter), + .Inter_chroma2x2_counter(Inter_chroma2x2_counter), + .Inter_blk4x4_pred_output_valid(Inter_blk4x4_pred_output_valid), + .mv_below8x8_curr(mv_below8x8_curr), + .pos_FracL(pos_FracL), + .mb_num_h(mb_num_h), + .mb_num_v(mb_num_v), + .LowerMB_IsSkip(LowerMB_IsSkip), + + .end_of_one_blk4x4_sum(end_of_one_blk4x4_sum), + .blk4x4_sum_counter(blk4x4_sum_counter), + .blk4x4_rec_counter(blk4x4_rec_counter), + .blk4x4_sum_PE0_out(blk4x4_sum_PE0_out), + .blk4x4_sum_PE1_out(blk4x4_sum_PE1_out), + .blk4x4_sum_PE2_out(blk4x4_sum_PE2_out), + .blk4x4_sum_PE3_out(blk4x4_sum_PE3_out), + .blk4x4_rec_counter_2_raster_order(blk4x4_rec_counter_2_raster_order), + .sum_right_column_reg(sum_right_column_reg), + .blk4x4_pred_output0(blk4x4_pred_output0), + .blk4x4_pred_output1(blk4x4_pred_output1), + .blk4x4_pred_output2(blk4x4_pred_output2), + .blk4x4_pred_output4(blk4x4_pred_output4), + .blk4x4_pred_output5(blk4x4_pred_output5), + .blk4x4_pred_output6(blk4x4_pred_output6), + .blk4x4_pred_output8(blk4x4_pred_output8), + .blk4x4_pred_output9(blk4x4_pred_output9), + .blk4x4_pred_output10(blk4x4_pred_output10), + .blk4x4_pred_output12(blk4x4_pred_output12), + .blk4x4_pred_output13(blk4x4_pred_output13), + .blk4x4_pred_output14(blk4x4_pred_output14), + .Intra_mbAddrB_RAM_wr(Intra_mbAddrB_RAM_wr), + .Intra_mbAddrB_RAM_wr_addr(Intra_mbAddrB_RAM_wr_addr), + .Intra_mbAddrB_RAM_din(Intra_mbAddrB_RAM_din) + ); + DF_top DF_top ( + .clk(clk), + .reset_n(reset_n), + .gclk_DF(gclk_DF), + .gclk_end_of_MB_DEC(gclk_end_of_MB_DEC), + .gclk_DF_mbAddrA_RF(gclk_DF_mbAddrA_RF), + .gclk_DF_mbAddrB_RAM(gclk_DF_mbAddrB_RAM), + .end_of_BS_DEC(end_of_BS_DEC), + .disable_DF(disable_DF), + .mb_num_h(mb_num_h), + .mb_num_v(mb_num_v), + .bs_V0(bs_V0), + .bs_V1(bs_V1), + .bs_V2(bs_V2), + .bs_V3(bs_V3), + .bs_H0(bs_H0), + .bs_H1(bs_H1), + .bs_H2(bs_H2), + .bs_H3(bs_H3), + .QPy(QPy), + .QPc(QPc), + .slice_alpha_c0_offset_div2(slice_alpha_c0_offset_div2), + .slice_beta_offset_div2(slice_beta_offset_div2), + .blk4x4_sum_counter(blk4x4_sum_counter), + .blk4x4_rec_counter_2_raster_order(blk4x4_rec_counter_2_raster_order), + .rec_DF_RAM_dout(rec_DF_RAM_dout), + .blk4x4_sum_PE0_out(blk4x4_sum_PE0_out), + .blk4x4_sum_PE1_out(blk4x4_sum_PE1_out), + .blk4x4_sum_PE2_out(blk4x4_sum_PE2_out), + .blk4x4_sum_PE3_out(blk4x4_sum_PE3_out), + + .DF_duration(DF_duration), + .end_of_MB_DF(end_of_MB_DF), + .DF_edge_counter_MR(DF_edge_counter_MR), + .one_edge_counter_MR(one_edge_counter_MR), + .DF_mbAddrA_RF_rd(DF_mbAddrA_RF_rd), + .DF_mbAddrA_RF_wr(DF_mbAddrA_RF_wr), + .DF_mbAddrB_RAM_rd(DF_mbAddrB_RAM_rd), + .DF_mbAddrB_RAM_wr(DF_mbAddrB_RAM_wr), + .dis_frame_RAM_wr(dis_frame_RAM_wr), + .dis_frame_RAM_wr_addr(dis_frame_RAM_wr_addr), + .dis_frame_RAM_din(dis_frame_RAM_din) + ); + rec_DF_RAM_ctrl rec_DF_RAM_ctrl ( + .clk(clk), + .reset_n(reset_n), + .disable_DF(disable_DF), + .end_of_MB_DEC(end_of_MB_DEC), + .DF_edge_counter_MR(DF_edge_counter_MR), + .one_edge_counter_MR(one_edge_counter_MR), + .blk4x4_sum_PE0_out(blk4x4_sum_PE0_out), + .blk4x4_sum_PE1_out(blk4x4_sum_PE1_out), + .blk4x4_sum_PE2_out(blk4x4_sum_PE2_out), + .blk4x4_sum_PE3_out(blk4x4_sum_PE3_out), + .blk4x4_sum_counter(blk4x4_sum_counter), + .blk4x4_rec_counter_2_raster_order(blk4x4_rec_counter_2_raster_order), + .rec_DF_RAM0_dout(rec_DF_RAM0_dout), + .rec_DF_RAM1_dout(rec_DF_RAM1_dout), + + .rec_DF_RAM_dout(rec_DF_RAM_dout), + .rec_DF_RAM0_wr(rec_DF_RAM0_wr), + .rec_DF_RAM0_rd(rec_DF_RAM0_rd), + .rec_DF_RAM0_addr(rec_DF_RAM0_addr), + .rec_DF_RAM0_din(rec_DF_RAM0_din), + .rec_DF_RAM1_wr(rec_DF_RAM1_wr), + .rec_DF_RAM1_rd(rec_DF_RAM1_rd), + .rec_DF_RAM1_addr(rec_DF_RAM1_addr), + .rec_DF_RAM1_din(rec_DF_RAM1_din) + ); + ram_sync_1r_sync_1w #(`rec_DF_RAM0_data_width,`rec_DF_RAM0_data_depth) + rec_DF_RAM0 ( + .clk(gclk_rec_DF_RAM0), + .rst_n(reset_n), + .wr_n(~rec_DF_RAM0_wr), + .rd_n(~rec_DF_RAM0_rd), + .wr_addr(rec_DF_RAM0_addr), + .rd_addr(rec_DF_RAM0_addr), + .data_in(rec_DF_RAM0_din), + .data_out(rec_DF_RAM0_dout) + ); + ram_sync_1r_sync_1w #(`rec_DF_RAM1_data_width,`rec_DF_RAM1_data_depth) + rec_DF_RAM1 ( + .clk(gclk_rec_DF_RAM1), + .rst_n(reset_n), + .wr_n(~rec_DF_RAM1_wr), + .rd_n(~rec_DF_RAM1_rd), + .wr_addr(rec_DF_RAM1_addr), + .rd_addr(rec_DF_RAM1_addr), + .data_in(rec_DF_RAM1_din), + .data_out(rec_DF_RAM1_dout) + ); + ext_RAM_ctrl ext_RAM_ctrl( + .clk(clk), + .reset_n(reset_n), + .end_of_one_frame(end_of_one_frame), + .ref_frame_RAM_rd(ref_frame_RAM_rd), + .ref_frame_RAM_rd_addr(ref_frame_RAM_rd_addr), + .dis_frame_RAM_wr(dis_frame_RAM_wr), + .dis_frame_RAM_wr_addr(dis_frame_RAM_wr_addr), + //.dis_frame_RAM_din(dis_frame_RAM_din), + .ref_frame_RAM_dout(ref_frame_RAM_dout), + .ext_frame_RAM0_cs_n(ext_frame_RAM0_cs_n), + .ext_frame_RAM0_wr(ext_frame_RAM0_wr), + .ext_frame_RAM0_addr(ext_frame_RAM0_addr), + .ext_frame_RAM0_data(ext_frame_RAM0_data), + .ext_frame_RAM1_cs_n(ext_frame_RAM1_cs_n), + .ext_frame_RAM1_wr(ext_frame_RAM1_wr), + .ext_frame_RAM1_addr(ext_frame_RAM1_addr), + .ext_frame_RAM1_data(ext_frame_RAM1_data) + ); +endmodule \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/run_decoding.v b/demo_chip_rtl/rtl/nova/trunk/src/run_decoding.v new file mode 100644 index 0000000..ab5a77d --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/run_decoding.v @@ -0,0 +1,299 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : run_decoding.v +// Generated : June 11, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Decoding the all the remaining syntax for CAVLC +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module run_decoding (clk,reset_n,cavlc_decoder_state,BitStream_buffer_output,total_zeros, + level_0,level_1,level_2,level_3,level_4,level_5,level_6,level_7, + level_8,level_9,level_10,level_11,level_12,level_13,level_14,level_15, + TotalCoeff,i_run,i_TotalCoeff,coeffNum,IsRunLoop, + + run_of_zeros_len,zerosLeft,run, + coeffLevel_0,coeffLevel_1,coeffLevel_2, coeffLevel_3, coeffLevel_4, coeffLevel_5, coeffLevel_6, coeffLevel_7, + coeffLevel_8,coeffLevel_9,coeffLevel_10,coeffLevel_11,coeffLevel_12,coeffLevel_13,coeffLevel_14,coeffLevel_15); + input clk,reset_n; + input [3:0] cavlc_decoder_state; + input [15:0] BitStream_buffer_output; + input [3:0] total_zeros; + input [8:0] level_0,level_1,level_2,level_3,level_4,level_5,level_6,level_7; + input [8:0] level_8,level_9,level_10,level_11,level_12,level_13,level_14,level_15; + input [4:0] TotalCoeff; + input [3:0] i_run; + input [3:0] i_TotalCoeff; + input [3:0] coeffNum; + input IsRunLoop; + output [3:0] run_of_zeros_len; + output [3:0] zerosLeft; + output [3:0] run; + output [8:0] coeffLevel_0, coeffLevel_1, coeffLevel_2,coeffLevel_3, coeffLevel_4, coeffLevel_5, coeffLevel_6; + output [8:0] coeffLevel_7, coeffLevel_8, coeffLevel_9,coeffLevel_10,coeffLevel_11,coeffLevel_12,coeffLevel_13; + output [8:0] coeffLevel_14,coeffLevel_15; + + reg [3:0] run_of_zeros_len; + reg [3:0] zerosLeft; + reg [3:0] run; + reg [8:0] coeffLevel_0, coeffLevel_1, coeffLevel_2,coeffLevel_3, coeffLevel_4, coeffLevel_5, coeffLevel_6; + reg [8:0] coeffLevel_7, coeffLevel_8, coeffLevel_9,coeffLevel_10,coeffLevel_11,coeffLevel_12,coeffLevel_13; + reg [8:0] coeffLevel_14,coeffLevel_15; + + reg [3:0] run_before; + reg [3:0] zerosLeft_reg; + reg [3:0] run_0,run_1,run_2,run_3,run_4,run_5,run_6,run_7; + reg [3:0] run_8,run_9,run_10,run_11,run_12,run_13,run_14,run_15; + reg [8:0] level_output; + + //decoding Table 9-10 + always @ (cavlc_decoder_state or zerosLeft or BitStream_buffer_output) + if (cavlc_decoder_state == `run_before_LUT) + case (zerosLeft) + 0:run_of_zeros_len <= 0;//special case added for "total_zeros==0" + 1:run_of_zeros_len <= 1; + 2:run_of_zeros_len <= (BitStream_buffer_output[15] == 1)? 4'd1:4'd2; + 3:run_of_zeros_len <= 2; + 4:run_of_zeros_len <= (BitStream_buffer_output[15:14] == 2'b00)? 4'd3:4'd2; + 5:run_of_zeros_len <= (BitStream_buffer_output[15] == 1)? 4'd2:4'd3; + 6:run_of_zeros_len <= (BitStream_buffer_output[15:14] == 2'b11)? 4'd2:4'd3; + default: + if (BitStream_buffer_output[15] == 1 || BitStream_buffer_output[14] == 1 || BitStream_buffer_output[13] == 1) + run_of_zeros_len <= 3; + else if (BitStream_buffer_output[15:12] == 1) run_of_zeros_len <= 4; + else if (BitStream_buffer_output[15:11] == 1) run_of_zeros_len <= 5; + else if (BitStream_buffer_output[15:10] == 1) run_of_zeros_len <= 6; + else if (BitStream_buffer_output[15:9] == 1) run_of_zeros_len <= 7; + else if (BitStream_buffer_output[15:8] == 1) run_of_zeros_len <= 4'd8; + else if (BitStream_buffer_output[15:7] == 1) run_of_zeros_len <= 4'd9; + else if (BitStream_buffer_output[15:6] == 1) run_of_zeros_len <= 4'd10; + else if (BitStream_buffer_output[15:5] == 1) run_of_zeros_len <= 4'd11; + else run_of_zeros_len <= 0; + endcase + else + run_of_zeros_len <= 0; + + always @ (posedge clk) + if (reset_n == 0) + run_before <= 0; + else if (cavlc_decoder_state == `run_before_LUT) + case (zerosLeft) + 0:run_before <= 0;//special case added for "total_zeros==0" + 1:run_before <= (BitStream_buffer_output[15] == 0)? 4'd1:4'd0; + 2:if (BitStream_buffer_output[15] == 1) run_before <= 0; + else if (BitStream_buffer_output[15:14] == 2'b01) run_before <= 1; + else run_before <= 2; + 3:case (BitStream_buffer_output[15:14]) + 2'b00:run_before <= 3; + 2'b01:run_before <= 2; + 2'b10:run_before <= 1; + 2'b11:run_before <= 0; + endcase + 4:case (BitStream_buffer_output[15:14]) + 2'b00:run_before <= (BitStream_buffer_output[13] == 1)? 4'd3:4'd4; + 2'b01:run_before <= 2; + 2'b10:run_before <= 1; + 2'b11:run_before <= 0; + endcase + 5:case (BitStream_buffer_output[15:14]) + 2'b00:run_before <= (BitStream_buffer_output[13] == 1)? 4'd4:4'd5; + 2'b01:run_before <= (BitStream_buffer_output[13] == 1)? 4'd2:4'd3; + 2'b10:run_before <= 1; + 2'b11:run_before <= 0; + endcase + 6:casex (BitStream_buffer_output[15:13]) + 3'b11x:run_before <= 0; + 3'b000:run_before <= 1; + 3'b001:run_before <= 2; + 3'b011:run_before <= 3; + 3'b010:run_before <= 4; + 3'b101:run_before <= 5; + 3'b100:run_before <= 6; + endcase + default: + case (BitStream_buffer_output[15:13]) + 3'b000:run_before <= run_of_zeros_len + 3; + 3'b111:run_before <= 0; + 3'b110:run_before <= 1; + 3'b101:run_before <= 2; + 3'b100:run_before <= 3; + 3'b011:run_before <= 4; + 3'b010:run_before <= 5; + 3'b001:run_before <= 6; + endcase + endcase + + always @ (cavlc_decoder_state or total_zeros or run_before or zerosLeft_reg or IsRunLoop) + if (cavlc_decoder_state == `run_before_LUT) + zerosLeft <= (IsRunLoop == 0)? total_zeros:zerosLeft_reg; + else if (cavlc_decoder_state == `RunOfZeros) + zerosLeft <= zerosLeft_reg - run_before; + else + zerosLeft <= 0; + + always @ (posedge clk) + if (reset_n == 0) + zerosLeft_reg <= 0; + else if (cavlc_decoder_state == `run_before_LUT || cavlc_decoder_state == `RunOfZeros) + zerosLeft_reg <= zerosLeft; + + always @ (posedge clk) + if (reset_n == 0) + begin + run_0 <= 0; run_1 <= 0; run_2 <= 0; run_3 <= 0; + run_4 <= 0; run_5 <= 0; run_6 <= 0; run_7 <= 0; + run_8 <= 0; run_9 <= 0; run_10 <= 0; run_11 <= 0; + run_12 <= 0; run_13 <= 0; run_14 <= 0; run_15 <= 0; + end + //reset run0 ~ run15 for each 4x4 CAVLC as early as nAnB_decoding_s stage + else if (cavlc_decoder_state == `nAnB_decoding_s) + begin + run_0 <= 0; run_1 <= 0; run_2 <= 0; run_3 <= 0; + run_4 <= 0; run_5 <= 0; run_6 <= 0; run_7 <= 0; + run_8 <= 0; run_9 <= 0; run_10 <= 0; run_11 <= 0; + run_12 <= 0; run_13 <= 0; run_14 <= 0; run_15 <= 0; + end + else if (cavlc_decoder_state == `RunOfZeros) + begin + if (TotalCoeff == 1) + run_0 <= total_zeros; + else if (total_zeros == 0) + begin + run_0 <= 0; run_1 <= 0; run_2 <= 0; run_3 <= 0; + run_4 <= 0; run_5 <= 0; run_6 <= 0; run_7 <= 0; + run_8 <= 0; run_9 <= 0; run_10 <= 0; run_11 <= 0; + run_12 <= 0; run_13 <= 0; run_14 <= 0; run_15 <= 0; + end + else if ({1'b0,i_run} == TotalCoeff - 2) + case (i_run) + 0 :begin run_0 <= run_before; run_1 <= zerosLeft; end + 1 :begin run_1 <= run_before; run_2 <= zerosLeft; end + 2 :begin run_2 <= run_before; run_3 <= zerosLeft; end + 3 :begin run_3 <= run_before; run_4 <= zerosLeft; end + 4 :begin run_4 <= run_before; run_5 <= zerosLeft; end + 5 :begin run_5 <= run_before; run_6 <= zerosLeft; end + 6 :begin run_6 <= run_before; run_7 <= zerosLeft; end + 7 :begin run_7 <= run_before; run_8 <= zerosLeft; end + 8 :begin run_8 <= run_before; run_9 <= zerosLeft; end + 9 :begin run_9 <= run_before; run_10<= zerosLeft; end + 10:begin run_10<= run_before; run_11<= zerosLeft; end + 11:begin run_11<= run_before; run_12<= zerosLeft; end + 12:begin run_12<= run_before; run_13<= zerosLeft; end + 13:begin run_13<= run_before; run_14<= zerosLeft; end + endcase + else + case (i_run) + 0 :run_0 <= run_before; + 1 :run_1 <= run_before; + 2 :run_2 <= run_before; + 3 :run_3 <= run_before; + 4 :run_4 <= run_before; + 5 :run_5 <= run_before; + 6 :run_6 <= run_before; + 7 :run_7 <= run_before; + 8 :run_8 <= run_before; + 9 :run_9 <= run_before; + 10:run_10<= run_before; + 11:run_11<= run_before; + 12:run_12<= run_before; + 13:run_13<= run_before; + endcase + end + always @ (cavlc_decoder_state or i_TotalCoeff or run_0 or run_1 or run_2 or run_3 or run_4 or + run_5 or run_6 or run_7 or run_8 or run_9 or run_10 or run_11 or run_12 or run_13 or run_14) + if (cavlc_decoder_state == `LevelRunCombination) + case (i_TotalCoeff) //coeffNum = coeffNum + run[i_TotalCoeff-1] + 1; + 0 :run <= run_0; + 1 :run <= run_1; + 2 :run <= run_2; + 3 :run <= run_3; + 4 :run <= run_4; + 5 :run <= run_5; + 6 :run <= run_6; + 7 :run <= run_7; + 8 :run <= run_8; + 9 :run <= run_9; + 10:run <= run_10; + 11:run <= run_11; + 12:run <= run_12; + 13:run <= run_13; + 14:run <= run_14; + default:run <= 0; + endcase + else + run <= 0; + + always @ (i_TotalCoeff or level_0 or level_1 or level_2 or level_3 or level_4 or level_5 or level_6 or + level_7 or level_8 or level_9 or level_10 or level_11 or level_12 or level_13 or level_14 or level_15) + case (i_TotalCoeff) + 0 :level_output <= level_0; + 1 :level_output <= level_1; + 2 :level_output <= level_2; + 3 :level_output <= level_3; + 4 :level_output <= level_4; + 5 :level_output <= level_5; + 6 :level_output <= level_6; + 7 :level_output <= level_7; + 8 :level_output <= level_8; + 9 :level_output <= level_9; + 10:level_output <= level_10; + 11:level_output <= level_11; + 12:level_output <= level_12; + 13:level_output <= level_13; + 14:level_output <= level_14; + 15:level_output <= level_15; + endcase + + + always @ (posedge clk) + if (reset_n == 0) + begin + coeffLevel_0 <= 0; coeffLevel_1 <= 0; coeffLevel_2 <= 0; coeffLevel_3 <= 0; + coeffLevel_4 <= 0; coeffLevel_5 <= 0; coeffLevel_6 <= 0; coeffLevel_7 <= 0; + coeffLevel_8 <= 0; coeffLevel_9 <= 0; coeffLevel_10 <= 0; coeffLevel_11 <= 0; + coeffLevel_12 <= 0; coeffLevel_13 <= 0; coeffLevel_14 <= 0; coeffLevel_15 <= 0; + end + //Revise log: March 24,2006 + //change reset coeffLevel_0 ~ 14 at total_zeros_LUT stage + //else if (cavlc_decoder_state == RunOfZeros && //reset coeffLevel_0 ~ 14 only at last RunOfZeros + // (i_run == TotalCoeff - 1 || i_run == TotalCoeff - 2 || zerosLeft == 0)) + else if (cavlc_decoder_state == `total_zeros_LUT) + begin + coeffLevel_0 <= 0; coeffLevel_1 <= 0; coeffLevel_2 <= 0; coeffLevel_3 <= 0; + coeffLevel_4 <= 0; coeffLevel_5 <= 0; coeffLevel_6 <= 0; coeffLevel_7 <= 0; + coeffLevel_8 <= 0; coeffLevel_9 <= 0; coeffLevel_10 <= 0; coeffLevel_11 <= 0; + coeffLevel_12 <= 0; coeffLevel_13 <= 0; coeffLevel_14 <= 0; coeffLevel_15 <= 0; + end + else if (cavlc_decoder_state == `LevelRunCombination) + begin + case (coeffNum) + 0 :coeffLevel_0 <= level_output; + 1 :coeffLevel_1 <= level_output; + 2 :coeffLevel_2 <= level_output; + 3 :coeffLevel_3 <= level_output; + 4 :coeffLevel_4 <= level_output; + 5 :coeffLevel_5 <= level_output; + 6 :coeffLevel_6 <= level_output; + 7 :coeffLevel_7 <= level_output; + 8 :coeffLevel_8 <= level_output; + 9 :coeffLevel_9 <= level_output; + 10:coeffLevel_10<= level_output; + 11:coeffLevel_11<= level_output; + 12:coeffLevel_12<= level_output; + 13:coeffLevel_13<= level_output; + 14:coeffLevel_14<= level_output; + 15:coeffLevel_15<= level_output; + endcase + end + endmodule + + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/sum.v b/demo_chip_rtl/rtl/nova/trunk/src/sum.v new file mode 100644 index 0000000..13b0a3d --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/sum.v @@ -0,0 +1,510 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : sum.v +// Generated : Oct 29, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Sum module for residual + prediction +// Including output transpose and Intra_mbAddrB_RAM write control +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module sum (clk,reset_n,slice_data_state,residual_state,TotalCoeff,curr_CBPLuma_IsZero,CodedBlockPatternChroma, + curr_DC_IsZero,curr_DC_scaled,gclk_pred_output,gclk_blk4x4_sum,trigger_blk4x4_rec_sum, + IQIT_output_0, IQIT_output_1, IQIT_output_2, IQIT_output_3, + IQIT_output_4, IQIT_output_5, IQIT_output_6, IQIT_output_7, + IQIT_output_8, IQIT_output_9, IQIT_output_10,IQIT_output_11, + IQIT_output_12,IQIT_output_13,IQIT_output_14,IQIT_output_15, + mb_type_general,Intra4x4_predmode,Intra16x16_predmode,Intra_chroma_predmode, + Intra_pred_PE0_out,Intra_pred_PE1_out,Intra_pred_PE2_out,Intra_pred_PE3_out,blk4x4_intra_calculate_counter, + Inter_pred_out0,Inter_pred_out1,Inter_pred_out2,Inter_pred_out3,blk4x4_inter_calculate_counter,Inter_chroma2x2_counter, + Inter_blk4x4_pred_output_valid,mv_below8x8_curr,pos_FracL,mb_num_v,mb_num_h,LowerMB_IsSkip, + + end_of_one_blk4x4_sum,blk4x4_sum_counter,blk4x4_rec_counter, + blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out, + sum_right_column_reg,blk4x4_rec_counter_2_raster_order, + blk4x4_pred_output0, blk4x4_pred_output1, blk4x4_pred_output2, + blk4x4_pred_output4, blk4x4_pred_output5, blk4x4_pred_output6, + blk4x4_pred_output8, blk4x4_pred_output9, blk4x4_pred_output10, + blk4x4_pred_output12,blk4x4_pred_output13,blk4x4_pred_output14, + Intra_mbAddrB_RAM_wr,Intra_mbAddrB_RAM_wr_addr,Intra_mbAddrB_RAM_din + ); + input clk,reset_n; + input [3:0] slice_data_state; + input [3:0] residual_state; + input [4:0] TotalCoeff; + input curr_CBPLuma_IsZero; + input [1:0] CodedBlockPatternChroma; + input curr_DC_IsZero; + input [8:0] curr_DC_scaled; + input gclk_pred_output; + input gclk_blk4x4_sum; + input trigger_blk4x4_rec_sum; + //residual from IQIT + input [8:0] IQIT_output_0, IQIT_output_1, IQIT_output_2, IQIT_output_3; + input [8:0] IQIT_output_4, IQIT_output_5, IQIT_output_6, IQIT_output_7; + input [8:0] IQIT_output_8, IQIT_output_9, IQIT_output_10,IQIT_output_11; + input [8:0] IQIT_output_12,IQIT_output_13,IQIT_output_14,IQIT_output_15; + //Intra prediction output + input [3:0] mb_type_general; + input [3:0] Intra4x4_predmode; + input [1:0] Intra16x16_predmode; + input [1:0] Intra_chroma_predmode; + input [7:0] Intra_pred_PE0_out,Intra_pred_PE1_out,Intra_pred_PE2_out,Intra_pred_PE3_out; + input [2:0] blk4x4_intra_calculate_counter; + //Inter prediction output + input [7:0] Inter_pred_out0,Inter_pred_out1,Inter_pred_out2,Inter_pred_out3; + input [1:0] Inter_blk4x4_pred_output_valid; + input mv_below8x8_curr; + input [3:0] pos_FracL; + input [3:0] blk4x4_inter_calculate_counter; + input [1:0] Inter_chroma2x2_counter; + input [3:0] mb_num_h,mb_num_v; + input LowerMB_IsSkip; + + output end_of_one_blk4x4_sum; + output [2:0] blk4x4_sum_counter; + output [4:0] blk4x4_rec_counter; + output [7:0] blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out; + output [23:0] sum_right_column_reg; + output [4:0] blk4x4_rec_counter_2_raster_order; + output [7:0] blk4x4_pred_output0, blk4x4_pred_output1, blk4x4_pred_output2; + output [7:0] blk4x4_pred_output4, blk4x4_pred_output5, blk4x4_pred_output6; + output [7:0] blk4x4_pred_output8, blk4x4_pred_output9, blk4x4_pred_output10; + output [7:0] blk4x4_pred_output12,blk4x4_pred_output13,blk4x4_pred_output14; + output Intra_mbAddrB_RAM_wr; + output [6:0] Intra_mbAddrB_RAM_wr_addr; + output [31:0] Intra_mbAddrB_RAM_din; + + reg [2:0] blk4x4_sum_counter; + reg [4:0] blk4x4_rec_counter; + reg [4:0] blk4x4_rec_counter_2_raster_order; + reg [23:0] sum_right_column_reg; + + reg [7:0] blk4x4_pred_output0, blk4x4_pred_output1, blk4x4_pred_output2, blk4x4_pred_output3; + reg [7:0] blk4x4_pred_output4, blk4x4_pred_output5, blk4x4_pred_output6, blk4x4_pred_output7; + reg [7:0] blk4x4_pred_output8, blk4x4_pred_output9, blk4x4_pred_output10,blk4x4_pred_output11; + reg [7:0] blk4x4_pred_output12,blk4x4_pred_output13,blk4x4_pred_output14,blk4x4_pred_output15; + + + always @ (posedge gclk_pred_output or negedge reset_n) + if (reset_n == 1'b0) + begin blk4x4_pred_output0 <= 0; blk4x4_pred_output1 <= 0; blk4x4_pred_output2 <= 0; blk4x4_pred_output3 <= 0; + blk4x4_pred_output4 <= 0; blk4x4_pred_output5 <= 0; blk4x4_pred_output6 <= 0; blk4x4_pred_output7 <= 0; + blk4x4_pred_output8 <= 0; blk4x4_pred_output9 <= 0; blk4x4_pred_output10 <= 0; blk4x4_pred_output11 <= 0; + blk4x4_pred_output12 <= 0; blk4x4_pred_output13<= 0; blk4x4_pred_output14 <= 0; blk4x4_pred_output15 <= 0; end + else if (blk4x4_intra_calculate_counter != 0) + begin + //Intra4x4DC or chromaDC intra prediction:output valid only at cycle3 by PE0 + if ((mb_type_general[3:2] == 2'b11 && blk4x4_rec_counter < 16 && Intra4x4_predmode == `Intra4x4_DC) || + (mb_type_general[3] == 1'b1 && blk4x4_rec_counter > 15 && Intra_chroma_predmode == `Intra_chroma_DC)) + begin + if (blk4x4_intra_calculate_counter == 3'd3) //Intra4x4DC or chromaDC completes calculation at cycle3 by PE0 + begin + blk4x4_pred_output0 <= Intra_pred_PE0_out; blk4x4_pred_output1 <= Intra_pred_PE0_out; + blk4x4_pred_output2 <= Intra_pred_PE0_out; blk4x4_pred_output3 <= Intra_pred_PE0_out; + blk4x4_pred_output4 <= Intra_pred_PE0_out; blk4x4_pred_output5 <= Intra_pred_PE0_out; + blk4x4_pred_output6 <= Intra_pred_PE0_out; blk4x4_pred_output7 <= Intra_pred_PE0_out; + blk4x4_pred_output8 <= Intra_pred_PE0_out; blk4x4_pred_output9 <= Intra_pred_PE0_out; + blk4x4_pred_output10 <= Intra_pred_PE0_out; blk4x4_pred_output11 <= Intra_pred_PE0_out; + blk4x4_pred_output12 <= Intra_pred_PE0_out; blk4x4_pred_output13 <= Intra_pred_PE0_out; + blk4x4_pred_output14 <= Intra_pred_PE0_out; blk4x4_pred_output15 <= Intra_pred_PE0_out; + end + end + //Intra16x16DC intra prediction:output valid only at cycle1 by PE0 + else if (mb_type_general[3:2] == 2'b10 && blk4x4_rec_counter < 16 && Intra16x16_predmode == `Intra16x16_DC) + begin + if (blk4x4_rec_counter == 0 && blk4x4_intra_calculate_counter == 3'd1) + begin + blk4x4_pred_output0 <= Intra_pred_PE0_out; blk4x4_pred_output1 <= Intra_pred_PE0_out; + blk4x4_pred_output2 <= Intra_pred_PE0_out; blk4x4_pred_output3 <= Intra_pred_PE0_out; + blk4x4_pred_output4 <= Intra_pred_PE0_out; blk4x4_pred_output5 <= Intra_pred_PE0_out; + blk4x4_pred_output6 <= Intra_pred_PE0_out; blk4x4_pred_output7 <= Intra_pred_PE0_out; + blk4x4_pred_output8 <= Intra_pred_PE0_out; blk4x4_pred_output9 <= Intra_pred_PE0_out; + blk4x4_pred_output10 <= Intra_pred_PE0_out; blk4x4_pred_output11 <= Intra_pred_PE0_out; + blk4x4_pred_output12 <= Intra_pred_PE0_out; blk4x4_pred_output13 <= Intra_pred_PE0_out; + blk4x4_pred_output14 <= Intra_pred_PE0_out; blk4x4_pred_output15 <= Intra_pred_PE0_out; + end + end + //Besides above DC intra prediction case,other intra prediction modes output valid from cycle4 ~ cycle1 + else + case (blk4x4_intra_calculate_counter) + 3'd4:begin blk4x4_pred_output0 <= Intra_pred_PE0_out; blk4x4_pred_output4 <= Intra_pred_PE1_out; + blk4x4_pred_output8 <= Intra_pred_PE2_out; blk4x4_pred_output12 <= Intra_pred_PE3_out; end + 3'd3:begin blk4x4_pred_output1 <= Intra_pred_PE0_out; blk4x4_pred_output5 <= Intra_pred_PE1_out; + blk4x4_pred_output9 <= Intra_pred_PE2_out; blk4x4_pred_output13 <= Intra_pred_PE3_out; end + 3'd2:begin blk4x4_pred_output2 <= Intra_pred_PE0_out; blk4x4_pred_output6 <= Intra_pred_PE1_out; + blk4x4_pred_output10 <= Intra_pred_PE2_out; blk4x4_pred_output14 <= Intra_pred_PE3_out; end + 3'd1:begin blk4x4_pred_output3 <= Intra_pred_PE0_out; blk4x4_pred_output7 <= Intra_pred_PE1_out; + blk4x4_pred_output11 <= Intra_pred_PE2_out; blk4x4_pred_output15 <= Intra_pred_PE3_out; end + endcase + end + //Inter luma prediction output store + else if (Inter_blk4x4_pred_output_valid == 2'b01) + begin + if (pos_FracL == `pos_i || pos_FracL == `pos_k) + case (blk4x4_inter_calculate_counter) + 4'd7:begin blk4x4_pred_output0 <= Inter_pred_out0; blk4x4_pred_output4 <= Inter_pred_out1; + blk4x4_pred_output8 <= Inter_pred_out2; blk4x4_pred_output12 <= Inter_pred_out3; end + 4'd5:begin blk4x4_pred_output1 <= Inter_pred_out0; blk4x4_pred_output5 <= Inter_pred_out1; + blk4x4_pred_output9 <= Inter_pred_out2; blk4x4_pred_output13 <= Inter_pred_out3; end + 4'd3:begin blk4x4_pred_output2 <= Inter_pred_out0; blk4x4_pred_output6 <= Inter_pred_out1; + blk4x4_pred_output10 <= Inter_pred_out2; blk4x4_pred_output14 <= Inter_pred_out3; end + 4'd1:begin blk4x4_pred_output3 <= Inter_pred_out0; blk4x4_pred_output7 <= Inter_pred_out1; + blk4x4_pred_output11 <= Inter_pred_out2; blk4x4_pred_output15 <= Inter_pred_out3; end + endcase + else + case (blk4x4_inter_calculate_counter) + 4'd4:begin blk4x4_pred_output0 <= Inter_pred_out0; blk4x4_pred_output4 <= Inter_pred_out1; + blk4x4_pred_output8 <= Inter_pred_out2; blk4x4_pred_output12 <= Inter_pred_out3; end + 4'd3:begin blk4x4_pred_output1 <= Inter_pred_out0; blk4x4_pred_output5 <= Inter_pred_out1; + blk4x4_pred_output9 <= Inter_pred_out2; blk4x4_pred_output13 <= Inter_pred_out3; end + 4'd2:begin blk4x4_pred_output2 <= Inter_pred_out0; blk4x4_pred_output6 <= Inter_pred_out1; + blk4x4_pred_output10 <= Inter_pred_out2; blk4x4_pred_output14 <= Inter_pred_out3; end + 4'd1:begin blk4x4_pred_output3 <= Inter_pred_out0; blk4x4_pred_output7 <= Inter_pred_out1; + blk4x4_pred_output11 <= Inter_pred_out2; blk4x4_pred_output15 <= Inter_pred_out3; end + endcase + end + //Inter chroma prediction output store + else if (Inter_blk4x4_pred_output_valid == 2'b10) + case (mv_below8x8_curr) + 1'b1: + case (Inter_chroma2x2_counter) + 2'b11: + begin + blk4x4_pred_output0 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out0:0; + blk4x4_pred_output1 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out1:0; + blk4x4_pred_output4 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out2:0; + blk4x4_pred_output5 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out3:0; + end + 2'b10: + begin + blk4x4_pred_output2 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out0:0; + blk4x4_pred_output3 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out1:0; + blk4x4_pred_output6 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out2:0; + blk4x4_pred_output7 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out3:0; + end + 2'b01: + begin + blk4x4_pred_output8 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out0:0; + blk4x4_pred_output9 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out1:0; + blk4x4_pred_output12 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out2:0; + blk4x4_pred_output13 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out3:0; + end + 2'b00: + begin + blk4x4_pred_output10 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out0:0; + blk4x4_pred_output11 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out1:0; + blk4x4_pred_output14 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out2:0; + blk4x4_pred_output15 <= (blk4x4_inter_calculate_counter != 0)? Inter_pred_out3:0; + end + endcase + 1'b0: + case (blk4x4_inter_calculate_counter) + 4'd4:begin blk4x4_pred_output0 <= Inter_pred_out0; blk4x4_pred_output1 <= Inter_pred_out1; + blk4x4_pred_output4 <= Inter_pred_out2; blk4x4_pred_output5 <= Inter_pred_out3; end + 4'd3:begin blk4x4_pred_output2 <= Inter_pred_out0; blk4x4_pred_output3 <= Inter_pred_out1; + blk4x4_pred_output6 <= Inter_pred_out2; blk4x4_pred_output7 <= Inter_pred_out3; end + 4'd2:begin blk4x4_pred_output8 <= Inter_pred_out0; blk4x4_pred_output9 <= Inter_pred_out1; + blk4x4_pred_output12 <= Inter_pred_out2; blk4x4_pred_output13 <= Inter_pred_out3; end + 4'd1:begin blk4x4_pred_output10 <= Inter_pred_out0; blk4x4_pred_output11 <= Inter_pred_out1; + blk4x4_pred_output14 <= Inter_pred_out2; blk4x4_pred_output15 <= Inter_pred_out3; end + endcase + endcase + + //------------------------------------------------------ + //blk4x4_sum_counter + //------------------------------------------------------ + always @ (posedge clk) + if (reset_n == 1'b0) + blk4x4_sum_counter <= 3'd4; + else if (trigger_blk4x4_rec_sum == 1'b1) + blk4x4_sum_counter <= 3'd0; + else if (blk4x4_sum_counter != 3'd4) + blk4x4_sum_counter <= blk4x4_sum_counter + 1; + + assign end_of_one_blk4x4_sum = (blk4x4_sum_counter == 3'd3)? 1'b1:1'b0; + //------------------------------------------------------ + //blk4x4_rec_counter + //------------------------------------------------------ + always @ (posedge clk) + if (reset_n == 1'b0) + blk4x4_rec_counter <= 0; + else if (blk4x4_sum_counter == 3'd3) + blk4x4_rec_counter <= (blk4x4_rec_counter == 5'd23)? 5'd0:(blk4x4_rec_counter + 1); + //------------------------------------------------------ + //reconstruction sum + //------------------------------------------------------ + + //Note:since res_blk4x4_IsAllZero has a higer priority over res_blk4x4_OnlyDC,the conditions + //to assign res_blk4x4_OnlyDC is NOT complete (but when take current assigned res_blk4x4_IsAllZero + //value into account, res_blk4x4_OnlyDC is correct!) + + //res_blk4x4_IsAllZero:curr_DC_IsZero? curr_CBPLuma_IsZero? TotalCoeff is zero? CBPChroma is zero or one? + + reg res_blk4x4_IsAllZero; + reg res_blk4x4_onlyDC; + always @ (slice_data_state or residual_state or curr_DC_IsZero or TotalCoeff + or curr_DC_IsZero or curr_CBPLuma_IsZero or CodedBlockPatternChroma) + if (slice_data_state == `skip_run_duration) + begin + res_blk4x4_IsAllZero <= 1'b1; + res_blk4x4_onlyDC <= 1'b0; + end + else + case (residual_state) + `Intra16x16ACLevel_0_s: + begin + res_blk4x4_IsAllZero <= (curr_DC_IsZero)? 1'b1:1'b0; + res_blk4x4_onlyDC <= (curr_DC_IsZero)? 1'b0:1'b1; + end + `Intra16x16ACLevel_s,`ChromaACLevel_Cb_s,`ChromaACLevel_Cr_s: + begin + res_blk4x4_IsAllZero <= (TotalCoeff == 0 && curr_DC_IsZero)? 1'b1:1'b0; + res_blk4x4_onlyDC <= (TotalCoeff == 0)? 1'b1:1'b0; + end + `LumaLevel_0_s: + begin + res_blk4x4_IsAllZero <= 1'b1; + res_blk4x4_onlyDC <= 1'b0; + end + `LumaLevel_s: + begin + res_blk4x4_IsAllZero <= (TotalCoeff == 0 || curr_CBPLuma_IsZero)? 1'b1:1'b0; + res_blk4x4_onlyDC <= 1'b0; + end + `ChromaACLevel_0_s: //CodedBlockPatternChroma == 0 or 1 + if (CodedBlockPatternChroma == 0) //CodedBlockPatternChroma == 0 + begin + res_blk4x4_IsAllZero <= 1'b1; + res_blk4x4_onlyDC <= 1'b0; + end + else //CodedBlockPatternChroma == 1 + begin + res_blk4x4_IsAllZero <= (curr_DC_IsZero)? 1'b1:1'b0; + res_blk4x4_onlyDC <= (curr_DC_IsZero)? 1'b0:1'b1; + end + default: + begin + res_blk4x4_IsAllZero <= 1'b0; + res_blk4x4_onlyDC <= 1'b0; + end + endcase + + reg [8:0] sum_PE0_a,sum_PE1_a,sum_PE2_a,sum_PE3_a; + reg [7:0] sum_PE0_b,sum_PE1_b,sum_PE2_b,sum_PE3_b; + wire sum_PE_bypass; //only one bypass signal for all sum_PE0 ~ sum_PE3 + assign sum_PE_bypass = (blk4x4_sum_counter != 3'd4 && !res_blk4x4_IsAllZero)? 1'b0:1'b1; + + sum_PE sum_PE0 ( + .a(sum_PE0_a), + .b(sum_PE0_b), + .bypass(sum_PE_bypass), + .c(blk4x4_sum_PE0_out) + ); + sum_PE sum_PE1 ( + .a(sum_PE1_a), + .b(sum_PE1_b), + .bypass(sum_PE_bypass), + .c(blk4x4_sum_PE1_out) + ); + sum_PE sum_PE2 ( + .a(sum_PE2_a), + .b(sum_PE2_b), + .bypass(sum_PE_bypass), + .c(blk4x4_sum_PE2_out) + ); + sum_PE sum_PE3 ( + .a(sum_PE3_a), + .b(sum_PE3_b), + .bypass(sum_PE_bypass), + .c(blk4x4_sum_PE3_out) + ); + + // only for statistical purpose + // synopsys translate_off + integer number_of_IsAllZero; + integer number_of_onlyDC; + initial + begin + number_of_IsAllZero = 0; + number_of_onlyDC = 0; + end + always @ (blk4x4_sum_counter) + if (blk4x4_sum_counter == 3'd2) + begin + if (res_blk4x4_IsAllZero == 1'b1) number_of_IsAllZero <= number_of_IsAllZero + 1; + else if (res_blk4x4_onlyDC == 1'b1) number_of_onlyDC <= number_of_onlyDC + 1; + end + // synopsys translate_on + + always @ (blk4x4_sum_counter or res_blk4x4_IsAllZero or res_blk4x4_onlyDC or curr_DC_scaled or + IQIT_output_0 or IQIT_output_1 or IQIT_output_2 or IQIT_output_3 or + IQIT_output_4 or IQIT_output_5 or IQIT_output_6 or IQIT_output_7 or + IQIT_output_8 or IQIT_output_9 or IQIT_output_10 or IQIT_output_11 or + IQIT_output_12 or IQIT_output_13 or IQIT_output_14 or IQIT_output_15) + if (res_blk4x4_IsAllZero) + begin sum_PE0_a <= 0; sum_PE1_a <= 0; sum_PE2_a <= 0; sum_PE3_a <= 0; end + else if (res_blk4x4_onlyDC) + begin sum_PE0_a <= curr_DC_scaled; sum_PE1_a <= curr_DC_scaled; + sum_PE2_a <= curr_DC_scaled; sum_PE3_a <= curr_DC_scaled; end + else + case (blk4x4_sum_counter) + 0:begin sum_PE0_a <= IQIT_output_0; sum_PE1_a <= IQIT_output_1; + sum_PE2_a <= IQIT_output_2; sum_PE3_a <= IQIT_output_3; end + 1:begin sum_PE0_a <= IQIT_output_4; sum_PE1_a <= IQIT_output_5; + sum_PE2_a <= IQIT_output_6; sum_PE3_a <= IQIT_output_7; end + 2:begin sum_PE0_a <= IQIT_output_8; sum_PE1_a <= IQIT_output_9; + sum_PE2_a <= IQIT_output_10;sum_PE3_a <= IQIT_output_11; end + 3:begin sum_PE0_a <= IQIT_output_12;sum_PE1_a <= IQIT_output_13; + sum_PE2_a <= IQIT_output_14;sum_PE3_a <= IQIT_output_15; end + default:begin sum_PE0_a <= 0; sum_PE1_a <= 0; sum_PE2_a <= 0; sum_PE3_a <= 0; end + endcase + always @ (blk4x4_sum_counter or + blk4x4_pred_output0 or blk4x4_pred_output1 or blk4x4_pred_output2 or blk4x4_pred_output3 or + blk4x4_pred_output4 or blk4x4_pred_output5 or blk4x4_pred_output6 or blk4x4_pred_output7 or + blk4x4_pred_output8 or blk4x4_pred_output9 or blk4x4_pred_output10 or blk4x4_pred_output11 or + blk4x4_pred_output12 or blk4x4_pred_output13 or blk4x4_pred_output14 or blk4x4_pred_output15) + case (blk4x4_sum_counter) + 0:begin sum_PE0_b <= blk4x4_pred_output0; sum_PE1_b <= blk4x4_pred_output1; + sum_PE2_b <= blk4x4_pred_output2; sum_PE3_b <= blk4x4_pred_output3; end + 1:begin sum_PE0_b <= blk4x4_pred_output4; sum_PE1_b <= blk4x4_pred_output5; + sum_PE2_b <= blk4x4_pred_output6; sum_PE3_b <= blk4x4_pred_output7; end + 2:begin sum_PE0_b <= blk4x4_pred_output8; sum_PE1_b <= blk4x4_pred_output9; + sum_PE2_b <= blk4x4_pred_output10;sum_PE3_b <= blk4x4_pred_output11; end + 3:begin sum_PE0_b <= blk4x4_pred_output12;sum_PE1_b <= blk4x4_pred_output13; + sum_PE2_b <= blk4x4_pred_output14;sum_PE3_b <= blk4x4_pred_output15; end + default:begin sum_PE0_b <= 0; sum_PE1_b <= 0; sum_PE2_b <= 0; sum_PE3_b <= 0; end + endcase + //---------------------------------------------------------------------- + //sum right most column latch for Intra mbAddrA + //---------------------------------------------------------------------- + //sum_right_column_reg: + always @ (posedge gclk_blk4x4_sum or negedge reset_n) + if (reset_n == 0) + sum_right_column_reg <= 0; + else + case (blk4x4_sum_counter) + 3'd0:sum_right_column_reg[7:0] <= blk4x4_sum_PE3_out; + 3'd1:sum_right_column_reg[15:8] <= blk4x4_sum_PE3_out; + 3'd2:sum_right_column_reg[23:16] <= blk4x4_sum_PE3_out; + endcase + + //blk4x4_rec_counter_2_raster_order: + //change from double-z order to raster order + always @ (blk4x4_rec_counter) + case (blk4x4_rec_counter) + 5'd2 :blk4x4_rec_counter_2_raster_order <= 5'd4; + 5'd3 :blk4x4_rec_counter_2_raster_order <= 5'd5; + 5'd4 :blk4x4_rec_counter_2_raster_order <= 5'd2; + 5'd5 :blk4x4_rec_counter_2_raster_order <= 5'd3; + 5'd10:blk4x4_rec_counter_2_raster_order <= 5'd12; + 5'd11:blk4x4_rec_counter_2_raster_order <= 5'd13; + 5'd12:blk4x4_rec_counter_2_raster_order <= 5'd10; + 5'd13:blk4x4_rec_counter_2_raster_order <= 5'd11; + default:blk4x4_rec_counter_2_raster_order <= blk4x4_rec_counter; + endcase + //---------------------------------------------------------------------- + //Intra_mbAddrB_RAM write control + //---------------------------------------------------------------------- + wire Is_blk4x4_rec_bottom; + assign Is_blk4x4_rec_bottom = (blk4x4_rec_counter == 5'd10 || blk4x4_rec_counter == 5'd11 || + blk4x4_rec_counter == 5'd14 || blk4x4_rec_counter == 5'd15 || blk4x4_rec_counter == 5'd18 || + blk4x4_rec_counter == 5'd19 || blk4x4_rec_counter == 5'd22 || blk4x4_rec_counter == 5'd23); + + assign Intra_mbAddrB_RAM_wr = (mb_num_v != 4'd8 && blk4x4_sum_counter == 3'd3 && Is_blk4x4_rec_bottom && !LowerMB_IsSkip); + assign Intra_mbAddrB_RAM_din = (Intra_mbAddrB_RAM_wr)? {blk4x4_sum_PE3_out,blk4x4_sum_PE2_out,blk4x4_sum_PE1_out,blk4x4_sum_PE0_out}:0; + + // base pointer, [43:0] luma, [65:44] Chroma Cb, [87:66] Chroma Cr + reg [6:0] Intra_mbAddrB_RAM_addr_bp; + always @ (Intra_mbAddrB_RAM_wr or blk4x4_rec_counter[4] or blk4x4_rec_counter[2]) + if (Intra_mbAddrB_RAM_wr) + begin + if (blk4x4_rec_counter[4] == 1'b0) Intra_mbAddrB_RAM_addr_bp <= 0; + else if (blk4x4_rec_counter[2] == 1'b0) Intra_mbAddrB_RAM_addr_bp <= 7'd44; + else Intra_mbAddrB_RAM_addr_bp <= 7'd66; + end + else Intra_mbAddrB_RAM_addr_bp <= 0; + + // shift pointer,x2 for chroma,x4 for luma + wire [5:0] Intra_mbAddrB_RAM_addr_sp; + assign Intra_mbAddrB_RAM_addr_sp = (Intra_mbAddrB_RAM_wr && blk4x4_rec_counter[4] == 1'b1)? + {1'b0,mb_num_h,1'b0}:{mb_num_h,2'b0}; + // pointer for relative address of each 4x4 block inside a MB + reg [1:0] Intra_mbAddrB_RAM_addr_ip; + always @ (Intra_mbAddrB_RAM_wr or blk4x4_rec_counter[4] or blk4x4_rec_counter[2:0]) + if (Intra_mbAddrB_RAM_wr) + begin + if (blk4x4_rec_counter[4] == 1'b0) + case (blk4x4_rec_counter[2:0]) + 3'b010:Intra_mbAddrB_RAM_addr_ip <= 2'd0; + 3'b011:Intra_mbAddrB_RAM_addr_ip <= 2'd1; + 3'b110:Intra_mbAddrB_RAM_addr_ip <= 2'd2; + 3'b111:Intra_mbAddrB_RAM_addr_ip <= 2'd3; + default:Intra_mbAddrB_RAM_addr_ip <= 0; + endcase + else + Intra_mbAddrB_RAM_addr_ip <= {1'b0,blk4x4_rec_counter[0]}; + end + else + Intra_mbAddrB_RAM_addr_ip <= 0; + + assign Intra_mbAddrB_RAM_wr_addr = Intra_mbAddrB_RAM_addr_bp + Intra_mbAddrB_RAM_addr_sp + Intra_mbAddrB_RAM_addr_ip; + + /* + // synopsys translate_off + integer tracefile; + initial + begin + tracefile = $fopen("nova_sum_output.log"); + end + + wire [6:0] mb_num; + assign mb_num = mb_num_v * 11 + mb_num_h; + + wire [1:0] blk4x4_rec_counter_M4; + assign blk4x4_rec_counter_M4 = blk4x4_rec_counter[1:0]; + + reg [8:0] pic_num; + always @ (reset_n or mb_num) + if (reset_n == 1'b0) + pic_num <= 9'b111111111; + else if (mb_num == 0) + pic_num <= pic_num + 1; + + always @ (posedge clk) + if (blk4x4_sum_counter == 0) + begin + $fdisplay (tracefile,"------------------------ Pic = %3d, MB = %3d -------------------------",pic_num,mb_num); + if (blk4x4_rec_counter < 16) + $fdisplay (tracefile," [Luma] blk4x4Idx = %2d",blk4x4_rec_counter); + else + $fdisplay (tracefile," [Chroma] blk4x4Idx = %2d",blk4x4_rec_counter_M4); + $fdisplay (tracefile," Sum output: %8d %8d %8d %8d",blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out); + end + else if (blk4x4_sum_counter != 3'd4) + $fdisplay (tracefile," %8d %8d %8d %8d",blk4x4_sum_PE0_out,blk4x4_sum_PE1_out,blk4x4_sum_PE2_out,blk4x4_sum_PE3_out); + // synopsys translate_on + */ + +endmodule + +module sum_PE (a,b,bypass,c); + input [8:0] a; //for residual from IQIT + input [7:0] b; //for prediction from intra or inter + input bypass; + output [7:0] c; + + wire [9:0] sum; + + assign sum = (bypass)? 0:({2'b0,b} + {a[8],a}); + assign c = (bypass)? b:((sum[9] == 1'b1)? 0:((sum[8] == 1'b1)? 8'd255:sum[7:0])); +endmodule + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/syntax_decoding.v b/demo_chip_rtl/rtl/nova/trunk/src/syntax_decoding.v new file mode 100644 index 0000000..daa91a9 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/syntax_decoding.v @@ -0,0 +1,622 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : syntax_decoding.v +// Generated : May 23, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Decoding each sytax inside the bitstream +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module syntax_decoding (clk,reset_n,mb_num_h,mb_num_v,end_of_MB_DEC,pin_disable_DF, + parser_state,nal_unit_state,seq_parameter_set_state,pic_parameter_set_state, + slice_header_state,slice_data_state,mb_pred_state,sub_mb_pred_state, + exp_golomb_decoding_output,BitStream_buffer_output,dependent_variable_decoding_output,mbPartIdx, + + nal_unit_type,start_code_prefix_found, + deblocking_filter_control_present_flag,disable_deblocking_filter_idc,disable_DF, + slice_alpha_c0_offset_div2,slice_beta_offset_div2, + mb_skip_run,NumMbPart,NumSubMbPart, + MBTypeGen_mbAddrA,MBTypeGen_mbAddrD,MBTypeGen_mbAddrB_reg, + log2_max_frame_num_minus4,log2_max_pic_order_cnt_lsb_minus4,constrained_intra_pred_flag, + num_ref_idx_active_override_flag,num_ref_idx_l0_active_minus1, + slice_type,mb_type,mb_type_general,sub_mb_type,Intra16x16_predmode,intra_chroma_pred_mode, + pic_init_qp_minus26,chroma_qp_index_offset, + rem_intra4x4_pred_mode,prev_intra4x4_pred_mode_flag,mvd,mv_below8x8); + input clk,reset_n; + input [3:0] mb_num_h,mb_num_v; + input end_of_MB_DEC; + input pin_disable_DF; + input [1:0] parser_state; + input [2:0] nal_unit_state; + input [3:0] seq_parameter_set_state; + input [3:0] pic_parameter_set_state; + input [3:0] slice_header_state; + input [3:0] slice_data_state; + input [2:0] mb_pred_state; + input [1:0] sub_mb_pred_state; + input [15:0] BitStream_buffer_output; + input [7:0] exp_golomb_decoding_output; + input [9:0] dependent_variable_decoding_output; + input [1:0] mbPartIdx; + + output [4:0] nal_unit_type; + output start_code_prefix_found; + output deblocking_filter_control_present_flag; + output [1:0] disable_deblocking_filter_idc; + output disable_DF; + output [3:0] slice_alpha_c0_offset_div2; + output [3:0] slice_beta_offset_div2; + output [6:0] mb_skip_run; + output [2:0] NumMbPart; + output [2:0] NumSubMbPart; + output [1:0] MBTypeGen_mbAddrA; + output MBTypeGen_mbAddrD; + output [21:0] MBTypeGen_mbAddrB_reg; + output [3:0] log2_max_frame_num_minus4; + output [3:0] log2_max_pic_order_cnt_lsb_minus4; + output constrained_intra_pred_flag; + output num_ref_idx_active_override_flag; + output [2:0] num_ref_idx_l0_active_minus1; + output [2:0] slice_type; + output [4:0] mb_type; + output [3:0] mb_type_general; + output [1:0] Intra16x16_predmode; + output [1:0] intra_chroma_pred_mode; + output [1:0] sub_mb_type; + output [5:0] pic_init_qp_minus26; + output [4:0] chroma_qp_index_offset; + output [2:0] rem_intra4x4_pred_mode; + output prev_intra4x4_pred_mode_flag; + output [7:0] mvd; + output [3:0] mv_below8x8; + //-------------------------- + //start_code_prefix + //-------------------------- + reg start_code_prefix_found; + always @ (parser_state or BitStream_buffer_output) + if (parser_state == `start_code_prefix) + begin + if (BitStream_buffer_output == 16'b0000000000000001) + start_code_prefix_found <= 1; + else + start_code_prefix_found <= 0; + end + else + start_code_prefix_found <= 0; + //-------------------------- + //nal_unit + //-------------------------- + reg forbidden_zero_bit; + reg [1:0] nal_ref_idc; + reg [4:0] nal_unit_type_reg; + wire [4:0] nal_unit_type; + assign nal_unit_type = (nal_unit_state == `forbidden_zero_bit_2_nal_unit_type)? BitStream_buffer_output[12:8]:nal_unit_type_reg; + always @ (posedge clk) + if (reset_n == 0) + begin + forbidden_zero_bit <= 0; + nal_ref_idc <= 0; + nal_unit_type_reg <= 0; + end + else if (nal_unit_state == `forbidden_zero_bit_2_nal_unit_type) + begin + forbidden_zero_bit <= BitStream_buffer_output[15]; + nal_ref_idc <= BitStream_buffer_output[14:13]; + nal_unit_type_reg <= nal_unit_type; + end + //-------------------------- + //seq_parameter_set + //-------------------------- + reg [7:0] profile_idc; + reg constraint_set0_flag,constraint_set1_flag,constraint_set2_flag,constraint_set3_flag; + reg [3:0] reserved_zero_4bits; + reg [7:0] level_idc; + reg [4:0] seq_parameter_set_id_sps; + reg [3:0] log2_max_frame_num_minus4; + reg [1:0] pic_order_cnt_type; + reg [3:0] log2_max_pic_order_cnt_lsb_minus4; + reg [2:0] num_ref_frames; //however,we only support 1 reference frame currently + reg gaps_in_frame_num_value_allowed_flag; + reg [3:0] pic_width_in_mbs_minus1; + reg [3:0] pic_height_in_map_units_minus1; + reg frame_mbs_only_flag; + reg direct_8x8_inference_flag; + reg frame_cropping_flag; + reg vui_parameter_present_flag; + always @ (posedge clk) + if (reset_n == 0) + begin + profile_idc <= 0; + constraint_set0_flag <= 0; + constraint_set1_flag <= 0; + constraint_set2_flag <= 0; + constraint_set3_flag <= 0; + reserved_zero_4bits <= 0; + level_idc <= 0; + seq_parameter_set_id_sps <= 0; + log2_max_frame_num_minus4 <= 0; + pic_order_cnt_type <= 0; + log2_max_pic_order_cnt_lsb_minus4 <= 0; + num_ref_frames <= 0; + gaps_in_frame_num_value_allowed_flag <= 0; + pic_width_in_mbs_minus1 <= 0; + pic_height_in_map_units_minus1 <= 0; + frame_mbs_only_flag <= 0; + direct_8x8_inference_flag <= 0; + frame_cropping_flag <= 0; + vui_parameter_present_flag <= 0; + end + else + case (seq_parameter_set_state) + `fixed_header: + begin + profile_idc <= BitStream_buffer_output[15:8]; + constraint_set0_flag <= BitStream_buffer_output[7]; + constraint_set1_flag <= BitStream_buffer_output[6]; + constraint_set2_flag <= BitStream_buffer_output[5]; + constraint_set3_flag <= BitStream_buffer_output[4]; + reserved_zero_4bits <= BitStream_buffer_output[3:0]; + end + `level_idc_s :level_idc <= BitStream_buffer_output[15:8]; + `seq_parameter_set_id_sps_s :seq_parameter_set_id_sps <= exp_golomb_decoding_output[4:0]; + `log2_max_frame_num_minus4_s :log2_max_frame_num_minus4 <= exp_golomb_decoding_output[3:0]; + `pic_order_cnt_type_s :pic_order_cnt_type <= exp_golomb_decoding_output[1:0]; + `log2_max_pic_order_cnt_lsb_minus4_s :log2_max_pic_order_cnt_lsb_minus4 <= exp_golomb_decoding_output[3:0]; + `num_ref_frames_s :num_ref_frames <= exp_golomb_decoding_output[0]; + `gaps_in_frame_num_value_allowed_flag_s:gaps_in_frame_num_value_allowed_flag <= BitStream_buffer_output[15]; + `pic_width_in_mbs_minus1_s :pic_width_in_mbs_minus1 <= exp_golomb_decoding_output[3:0]; + `pic_height_in_map_units_minus1_s :pic_height_in_map_units_minus1 <= exp_golomb_decoding_output[3:0]; + `frame_mbs_only_flag_2_frame_cropping_flag: + begin + frame_mbs_only_flag <= BitStream_buffer_output[15]; + direct_8x8_inference_flag <= BitStream_buffer_output[14]; + frame_cropping_flag <= BitStream_buffer_output[13]; + end + `vui_parameter_present_flag_s:vui_parameter_present_flag <= BitStream_buffer_output[15]; + endcase + //-------------------------- + //pic_parameter_set + //-------------------------- + reg [7:0] pic_parameter_set_id_pps; + reg [4:0] seq_parameter_set_id_pps; + reg entropy_coding_mode_flag; + reg pic_order_present_flag; + reg [2:0] num_slice_groups_minus1; + reg [2:0] num_ref_idx_l0_active_minus1; + reg [2:0] num_ref_idx_l1_active_minus1; + reg weighted_pred_flag; + reg [1:0] weighted_bipred_idc; + reg [5:0] pic_init_qp_minus26,pic_init_qs_minus26; + reg [4:0] chroma_qp_index_offset; + reg deblocking_filter_control_present_flag; + reg constrained_intra_pred_flag; + reg redundant_pic_cnt_present_flag; + always @ (posedge clk) + if (reset_n == 0) + begin + pic_parameter_set_id_pps <= 0; + seq_parameter_set_id_pps <= 0; + entropy_coding_mode_flag <= 0; + pic_order_present_flag <= 0; + num_slice_groups_minus1 <= 0; + num_ref_idx_l0_active_minus1 <= 0; + num_ref_idx_l1_active_minus1 <= 0; + weighted_pred_flag <= 0; + weighted_bipred_idc <= 0; + pic_init_qp_minus26 <= 0; + pic_init_qs_minus26 <= 0; + chroma_qp_index_offset <= 0; + deblocking_filter_control_present_flag <= 0; + constrained_intra_pred_flag <= 0; + redundant_pic_cnt_present_flag <= 0; + end + else + case (pic_parameter_set_state) + `pic_parameter_set_id_pps_s:pic_parameter_set_id_pps <= exp_golomb_decoding_output[7:0]; + `seq_parameter_set_id_pps_s:seq_parameter_set_id_pps <= exp_golomb_decoding_output[4:0]; + `entropy_coding_mode_flag_2_pic_order_present_flag: + begin + entropy_coding_mode_flag <= BitStream_buffer_output[15]; + pic_order_present_flag <= BitStream_buffer_output[14]; + end + `num_slice_groups_minus1_s :num_slice_groups_minus1 <= exp_golomb_decoding_output[2:0]; + `num_ref_idx_l0_active_minus1_pps_s:num_ref_idx_l0_active_minus1 <= exp_golomb_decoding_output[2:0]; + `num_ref_idx_l1_active_minus1_pps_s:num_ref_idx_l1_active_minus1 <= exp_golomb_decoding_output[2:0]; + `weighted_pred_flag_2_weighted_bipred_idc: + begin + weighted_pred_flag <= BitStream_buffer_output[15]; + weighted_bipred_idc <= BitStream_buffer_output[14:13]; + end + `pic_init_qp_minus26_s :pic_init_qp_minus26 <= exp_golomb_decoding_output[5:0]; + `pic_init_qs_minus26_s :pic_init_qs_minus26 <= exp_golomb_decoding_output[5:0]; + `chroma_qp_index_offset_s:chroma_qp_index_offset <= exp_golomb_decoding_output[4:0]; + `deblocking_filter_control_2_redundant_pic_cnt_present_flag: + begin + deblocking_filter_control_present_flag <= BitStream_buffer_output[15]; + constrained_intra_pred_flag <= BitStream_buffer_output[14]; + redundant_pic_cnt_present_flag <= BitStream_buffer_output[13]; + end + endcase + //-------------------------- + //slice_header + //-------------------------- + reg first_mb_in_slice; + reg [2:0] slice_type; + reg [7:0] pic_parameter_set_id_slice_header; + reg [3:0] frame_num; + reg idr_pic_id; + reg [9:0] pic_order_cnt_lsb; + reg num_ref_idx_active_override_flag; + reg [1:0] disable_deblocking_filter_idc; + reg [3:0] slice_alpha_c0_offset_div2_dec; + reg [3:0] slice_beta_offset_div2_dec; + always @ (posedge clk) + if (reset_n == 0) + begin + first_mb_in_slice <= 0; + slice_type <= 0; + pic_parameter_set_id_slice_header <= 0; + frame_num <= 0; + idr_pic_id <= 0; + pic_order_cnt_lsb <= 0; + num_ref_idx_active_override_flag <= 0; + disable_deblocking_filter_idc <= 0; + slice_alpha_c0_offset_div2_dec <= 0; + slice_beta_offset_div2_dec <= 0; + end + else + case (slice_header_state) + `first_mb_in_slice_s :first_mb_in_slice <= exp_golomb_decoding_output[0]; + `slice_type_s :slice_type <= exp_golomb_decoding_output[2:0]; + `pic_parameter_set_id_slice_header_s:pic_parameter_set_id_slice_header <= exp_golomb_decoding_output; + `frame_num_s :frame_num <= dependent_variable_decoding_output[3:0]; + `idr_pic_id_s :idr_pic_id <= exp_golomb_decoding_output[0]; + `pic_order_cnt_lsb_s :pic_order_cnt_lsb <= dependent_variable_decoding_output[9:0]; + `num_ref_idx_active_override_flag_s :num_ref_idx_active_override_flag <= BitStream_buffer_output[15]; + //num_ref_idx_l0_active_minus1_slice_header_s: + //slice_qp_delta_s:slice_qp_delta <= exp_golomb_decoding_output[5:0]; + `disable_deblocking_filter_idc_s :disable_deblocking_filter_idc <= exp_golomb_decoding_output[1:0]; + `slice_alpha_c0_offset_div2_s :slice_alpha_c0_offset_div2_dec <= exp_golomb_decoding_output[3:0]; + `slice_beta_offset_div2_s :slice_beta_offset_div2_dec <= exp_golomb_decoding_output[3:0]; + //slice_group_change_cycle_s: + endcase + + wire [3:0] slice_alpha_c0_offset_div2; + wire [3:0] slice_beta_offset_div2; + assign slice_alpha_c0_offset_div2 = {4{deblocking_filter_control_present_flag}} & slice_alpha_c0_offset_div2_dec; + assign slice_beta_offset_div2 = {4{deblocking_filter_control_present_flag}} & slice_beta_offset_div2_dec; + + reg sw_disable_DF; + always @ (posedge clk) + if (reset_n == 0) + sw_disable_DF <= 0; + else if (slice_header_state == `disable_deblocking_filter_idc_s && disable_deblocking_filter_idc == 1) + sw_disable_DF <= 1; + else + sw_disable_DF <= 0; + + assign disable_DF = sw_disable_DF | pin_disable_DF; + //-------------------------- + //slice_data + //-------------------------- + wire [6:0] mb_skip_run; + reg [6:0] mb_skip_run_reg; + reg [4:0] mb_type; + reg [3:0] mb_type_general; + reg [3:0] mb_type_general_reg; + reg [1:0] Intra16x16_predmode; + + //mb_type_general + assign mb_skip_run = (slice_data_state == `mb_skip_run_s)? exp_golomb_decoding_output[6:0]:mb_skip_run_reg; + always @ (slice_data_state or slice_type or exp_golomb_decoding_output or mb_type_general_reg) + if (slice_data_state == `skip_run_duration) + mb_type_general <= `MB_P_skip; + else if (slice_data_state == `mb_type_s) + begin + if (slice_type == 2 || slice_type == 7) //I slice + case (exp_golomb_decoding_output) + 0: mb_type_general <= `MB_Intra4x4; + 1,2,3,4,13,14,15,16: mb_type_general <= `MB_Intra16x16_CBPChroma0; + 5,6,7,8,17,18,19,20: mb_type_general <= `MB_Intra16x16_CBPChroma1; + 9,10,11,12,21,22,23,24: mb_type_general <= `MB_Intra16x16_CBPChroma2; + default: mb_type_general <= `MB_Inter16x16; + endcase + else //P slice + case (exp_golomb_decoding_output) + 0: mb_type_general <= `MB_Inter16x16; + 1: mb_type_general <= `MB_Inter16x8; + 2: mb_type_general <= `MB_Inter8x16; + 3: mb_type_general <= `MB_P_8x8; + 4: mb_type_general <= `MB_P_8x8ref0; + 5: mb_type_general <= `MB_Intra4x4; + 6,7,8,9,18,19,20,21: mb_type_general <= `MB_Intra16x16_CBPChroma0; + 10,11,12,13,22,23,24,25:mb_type_general <= `MB_Intra16x16_CBPChroma1; + 14,15,16,17,26,27,28,29:mb_type_general <= `MB_Intra16x16_CBPChroma0; + default: mb_type_general <= `MB_Inter16x8; + endcase + end + else + mb_type_general <= mb_type_general_reg; + + //Intra16x16_predmode + always @ (posedge clk) + if (reset_n == 0) + Intra16x16_predmode <= 2'b0; + else if (slice_data_state == `mb_type_s) + begin + if (slice_type == 2 || slice_type == 7) //I slice + begin + if (exp_golomb_decoding_output != 0) + case (exp_golomb_decoding_output[1:0]) + 2'b00:Intra16x16_predmode <= 2'b11; + 2'b01:Intra16x16_predmode <= 2'b00; + 2'b10:Intra16x16_predmode <= 2'b01; + 2'b11:Intra16x16_predmode <= 2'b10; + endcase + end + else if (exp_golomb_decoding_output[4:0] > 5) //P slice + case (exp_golomb_decoding_output[1:0]) + 2'b00:Intra16x16_predmode <= 2'b10; + 2'b01:Intra16x16_predmode <= 2'b11; + 2'b10:Intra16x16_predmode <= 2'b00; + 2'b11:Intra16x16_predmode <= 2'b01; + endcase + end + + always @ (posedge clk) + if (reset_n == 0) + begin + mb_skip_run_reg <= 0; + mb_type <= 0; + mb_type_general_reg <= `MB_type_rst; + end + else + case (slice_data_state) + `mb_skip_run_s:mb_skip_run_reg <= mb_skip_run; + `skip_run_duration: + begin + mb_type <= 5'd31; + mb_type_general_reg <= mb_type_general; + end + `mb_type_s: + begin + mb_type <= exp_golomb_decoding_output[4:0]; + mb_type_general_reg <= mb_type_general; + end + //pcm_byte_s: --> Currently no deal with it + //coded_block_pattern_s: --> See CodedBlockPattern_decoding.v + //mb_qp_delta_s:mb_qp_delta <= exp_golomb_decoding_output; + endcase + //Update MBTypeGen information + reg [1:0] MBTypeGen_mbAddrA; + reg MBTypeGen_mbAddrD_tmp; + reg MBTypeGen_mbAddrD; + reg [21:0] MBTypeGen_mbAddrB_reg; + always @ (posedge clk) + if (reset_n == 0) + begin + MBTypeGen_mbAddrA <= 0; + MBTypeGen_mbAddrD_tmp <= 0; + MBTypeGen_mbAddrB_reg <= 0; + end + else if (slice_data_state == `skip_run_duration && end_of_MB_DEC)//for P_skip + begin + if (mb_num_h != 10) + MBTypeGen_mbAddrA <= `MB_addrA_addrB_P_skip; + if (mb_num_h == 9) + MBTypeGen_mbAddrD_tmp <= 1'b0; + if (mb_num_v != 8) + case (mb_num_h) + 0:MBTypeGen_mbAddrB_reg[1:0] <= `MB_addrA_addrB_P_skip;1:MBTypeGen_mbAddrB_reg[3:2] <= `MB_addrA_addrB_P_skip; + 2:MBTypeGen_mbAddrB_reg[5:4] <= `MB_addrA_addrB_P_skip;3:MBTypeGen_mbAddrB_reg[7:6] <= `MB_addrA_addrB_P_skip; + 4:MBTypeGen_mbAddrB_reg[9:8] <= `MB_addrA_addrB_P_skip;5:MBTypeGen_mbAddrB_reg[11:10] <= `MB_addrA_addrB_P_skip; + 6:MBTypeGen_mbAddrB_reg[13:12] <= `MB_addrA_addrB_P_skip;7:MBTypeGen_mbAddrB_reg[15:14] <= `MB_addrA_addrB_P_skip; + 8:MBTypeGen_mbAddrB_reg[17:16] <= `MB_addrA_addrB_P_skip;9:MBTypeGen_mbAddrB_reg[19:18] <= `MB_addrA_addrB_P_skip; + 10:MBTypeGen_mbAddrB_reg[21:20] <= `MB_addrA_addrB_P_skip; + endcase + end + else if (slice_data_state == `mb_num_update) + begin + if (mb_num_h != 10) + begin + if (mb_type_general[3] == 1'b0) + MBTypeGen_mbAddrA <= `MB_addrA_addrB_Inter; + else if (mb_type_general[3:2] == 2'b10) + MBTypeGen_mbAddrA <= `MB_addrA_addrB_Intra16x16; + else if (mb_type_general == `MB_Intra4x4) + MBTypeGen_mbAddrA <= `MB_addrA_addrB_Intra4x4; + end + if (mb_num_h == 9) + MBTypeGen_mbAddrD_tmp <= mb_type_general[3]; + if (mb_num_v != 8) + begin + if (mb_type_general[3] == 1'b0) + case (mb_num_h) + 0:MBTypeGen_mbAddrB_reg[1:0] <= `MB_addrA_addrB_Inter; 1:MBTypeGen_mbAddrB_reg[3:2] <= `MB_addrA_addrB_Inter; + 2:MBTypeGen_mbAddrB_reg[5:4] <= `MB_addrA_addrB_Inter; 3:MBTypeGen_mbAddrB_reg[7:6] <= `MB_addrA_addrB_Inter; + 4:MBTypeGen_mbAddrB_reg[9:8] <= `MB_addrA_addrB_Inter; 5:MBTypeGen_mbAddrB_reg[11:10] <= `MB_addrA_addrB_Inter; + 6:MBTypeGen_mbAddrB_reg[13:12] <= `MB_addrA_addrB_Inter; 7:MBTypeGen_mbAddrB_reg[15:14] <= `MB_addrA_addrB_Inter; + 8:MBTypeGen_mbAddrB_reg[17:16] <= `MB_addrA_addrB_Inter; 9:MBTypeGen_mbAddrB_reg[19:18] <= `MB_addrA_addrB_Inter; + 10:MBTypeGen_mbAddrB_reg[21:20]<= `MB_addrA_addrB_Inter; + endcase + else if (mb_type_general[3:2] == 2'b10) + case (mb_num_h) + 0:MBTypeGen_mbAddrB_reg[1:0] <= `MB_addrA_addrB_Intra16x16; 1:MBTypeGen_mbAddrB_reg[3:2] <= `MB_addrA_addrB_Intra16x16; + 2:MBTypeGen_mbAddrB_reg[5:4] <= `MB_addrA_addrB_Intra16x16; 3:MBTypeGen_mbAddrB_reg[7:6] <= `MB_addrA_addrB_Intra16x16; + 4:MBTypeGen_mbAddrB_reg[9:8] <= `MB_addrA_addrB_Intra16x16; 5:MBTypeGen_mbAddrB_reg[11:10] <= `MB_addrA_addrB_Intra16x16; + 6:MBTypeGen_mbAddrB_reg[13:12] <= `MB_addrA_addrB_Intra16x16; 7:MBTypeGen_mbAddrB_reg[15:14] <= `MB_addrA_addrB_Intra16x16; + 8:MBTypeGen_mbAddrB_reg[17:16] <= `MB_addrA_addrB_Intra16x16; 9:MBTypeGen_mbAddrB_reg[19:18] <= `MB_addrA_addrB_Intra16x16; + 10:MBTypeGen_mbAddrB_reg[21:20]<= `MB_addrA_addrB_Intra16x16; + endcase + else if (mb_type_general == `MB_Intra4x4) + case (mb_num_h) + 0:MBTypeGen_mbAddrB_reg[1:0] <= `MB_addrA_addrB_Intra4x4; 1:MBTypeGen_mbAddrB_reg[3:2] <= `MB_addrA_addrB_Intra4x4; + 2:MBTypeGen_mbAddrB_reg[5:4] <= `MB_addrA_addrB_Intra4x4; 3:MBTypeGen_mbAddrB_reg[7:6] <= `MB_addrA_addrB_Intra4x4; + 4:MBTypeGen_mbAddrB_reg[9:8] <= `MB_addrA_addrB_Intra4x4; 5:MBTypeGen_mbAddrB_reg[11:10] <= `MB_addrA_addrB_Intra4x4; + 6:MBTypeGen_mbAddrB_reg[13:12] <= `MB_addrA_addrB_Intra4x4; 7:MBTypeGen_mbAddrB_reg[15:14] <= `MB_addrA_addrB_Intra4x4; + 8:MBTypeGen_mbAddrB_reg[17:16] <= `MB_addrA_addrB_Intra4x4; 9:MBTypeGen_mbAddrB_reg[19:18] <= `MB_addrA_addrB_Intra4x4; + 10:MBTypeGen_mbAddrB_reg[21:20]<= `MB_addrA_addrB_Intra4x4; + endcase + end + end + + always @ (posedge clk) + if (reset_n == 1'b0) + MBTypeGen_mbAddrD <= 0; + else if (mb_num_h == 0) + MBTypeGen_mbAddrD <= MBTypeGen_mbAddrD_tmp; + + //---------------------------------------------------------------------- + //mb_pred & sub_mb_pred + // --> Also refer to Intra4x4_PredMode_decoding.v & Inter_mv_decoding.v + //---------------------------------------------------------------------- + wire prev_intra4x4_pred_mode_flag; + reg prev_intra4x4_pred_mode_flag_reg; + wire [2:0] rem_intra4x4_pred_mode; + reg [2:0] rem_intra4x4_pred_mode_reg; + reg [1:0] intra_chroma_pred_mode; + wire [7:0] mvd; + reg [7:0] mvd_reg; + reg [7:0] sub_mb_type_reg; + assign prev_intra4x4_pred_mode_flag = (mb_pred_state == `prev_intra4x4_pred_mode_flag_s)? BitStream_buffer_output[15]:prev_intra4x4_pred_mode_flag_reg; + assign rem_intra4x4_pred_mode = (mb_pred_state == `rem_intra4x4_pred_mode_s)? BitStream_buffer_output[15:13]:rem_intra4x4_pred_mode_reg; + assign mvd = ((mb_pred_state == `mvd_l0_s) || (sub_mb_pred_state == `sub_mvd_l0_s))? exp_golomb_decoding_output[7:0]:mvd_reg; + always @ (posedge clk) + if (reset_n == 0) + begin + prev_intra4x4_pred_mode_flag_reg <= 0; + rem_intra4x4_pred_mode_reg <= 0; + intra_chroma_pred_mode <= 0; + mvd_reg <= 0; + sub_mb_type_reg <= 0; + end + else + begin + case (mb_pred_state) + `prev_intra4x4_pred_mode_flag_s:prev_intra4x4_pred_mode_flag_reg <= prev_intra4x4_pred_mode_flag; + `rem_intra4x4_pred_mode_s :rem_intra4x4_pred_mode_reg <= rem_intra4x4_pred_mode; + `intra_chroma_pred_mode_s :intra_chroma_pred_mode <= exp_golomb_decoding_output[1:0]; + //ref_idx_l0_s: --> only 1 reference frame,so never jump into this state + `mvd_l0_s: mvd_reg <= mvd; + endcase + case (sub_mb_pred_state) + `sub_mb_type_s: + case (mbPartIdx) + 0:sub_mb_type_reg[1:0] <= exp_golomb_decoding_output[1:0]; + 1:sub_mb_type_reg[3:2] <= exp_golomb_decoding_output[1:0]; + 2:sub_mb_type_reg[5:4] <= exp_golomb_decoding_output[1:0]; + 3:sub_mb_type_reg[7:6] <= exp_golomb_decoding_output[1:0]; + endcase + //sub_ref_idx_l0_s: --> only 1 reference frame,so never jump into this state + `sub_mvd_l0_s: mvd_reg <= mvd; + endcase + end + reg [2:0] NumMbPart; + reg [2:0] NumSubMbPart; + reg [1:0] sub_mb_type; + always @ (sub_mb_pred_state or sub_mb_type_reg or mbPartIdx) + if (sub_mb_pred_state == `sub_mvd_l0_s) + case (mbPartIdx) + 0:sub_mb_type <= sub_mb_type_reg[1:0]; + 1:sub_mb_type <= sub_mb_type_reg[3:2]; + 2:sub_mb_type <= sub_mb_type_reg[5:4]; + 3:sub_mb_type <= sub_mb_type_reg[7:6]; + endcase + else + sub_mb_type <= 0; + always @ (mb_pred_state or mb_type_general or sub_mb_pred_state) + if (mb_pred_state == `mvd_l0_s) + case (mb_type_general) + 0:NumMbPart <= 3'd1; + default:NumMbPart <= 3'd2; + endcase + else if (sub_mb_pred_state == `sub_mvd_l0_s) + NumMbPart <= 3'd4; + else + NumMbPart <= 3'd0; + always @ (sub_mb_pred_state or mbPartIdx or sub_mb_type_reg) + if (sub_mb_pred_state == `sub_mvd_l0_s) + case (mbPartIdx) + 0: + case (sub_mb_type_reg[1:0]) + 2'b00 :NumSubMbPart <= 3'd1; + 2'b01,2'b10:NumSubMbPart <= 3'd2; + 2'b11 :NumSubMbPart <= 3'd4; + endcase + 1: + case (sub_mb_type_reg[3:2]) + 2'b00 :NumSubMbPart <= 3'd1; + 2'b01,2'b10:NumSubMbPart <= 3'd2; + 2'b11 :NumSubMbPart <= 3'd4; + endcase + 2: + case (sub_mb_type_reg[5:4]) + 2'b00 :NumSubMbPart <= 3'd1; + 2'b01,2'b10:NumSubMbPart <= 3'd2; + 2'b11 :NumSubMbPart <= 3'd4; + endcase + 3: + case (sub_mb_type_reg[7:6]) + 2'b00 :NumSubMbPart <= 3'd1; + 2'b01,2'b10:NumSubMbPart <= 3'd2; + 2'b11 :NumSubMbPart <= 3'd4; + endcase + endcase + else + NumSubMbPart <= 0; + + //mv_below8x8 + reg [3:0] mv_below8x8; + always @ (posedge clk) + if (reset_n == 1'b0) + mv_below8x8 <= 4'b0; + else if (sub_mb_pred_state == `sub_mb_type_s) + case (mbPartIdx) + 0:mv_below8x8[0] <= (exp_golomb_decoding_output[1:0] == 2'b00)? 1'b0:1'b1; + 1:mv_below8x8[1] <= (exp_golomb_decoding_output[1:0] == 2'b00)? 1'b0:1'b1; + 2:mv_below8x8[2] <= (exp_golomb_decoding_output[1:0] == 2'b00)? 1'b0:1'b1; + 3:mv_below8x8[3] <= (exp_golomb_decoding_output[1:0] == 2'b00)? 1'b0:1'b1; + endcase + else if (slice_data_state == `mb_pred || slice_data_state == `skip_run_duration) + mv_below8x8 <= 4'b0; + +endmodule + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/src/timescale.v b/demo_chip_rtl/rtl/nova/trunk/src/timescale.v new file mode 100644 index 0000000..b0f520d --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/timescale.v @@ -0,0 +1,13 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : timescale.v +// Generated : April 20, 2008 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Time scale for the entire design +//------------------------------------------------------------------------------------------------- + +`timescale 1ns/1ns diff --git a/demo_chip_rtl/rtl/nova/trunk/src/total_zeros_decoding.v b/demo_chip_rtl/rtl/nova/trunk/src/total_zeros_decoding.v new file mode 100644 index 0000000..13fccf9 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/src/total_zeros_decoding.v @@ -0,0 +1,400 @@ +//-------------------------------------------------------------------------------------------------- +// Design : nova +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// File : total_zeros_decoding.v +// Generated : June 9, 2005 +// Copyright (C) 2008 Ke Xu +//------------------------------------------------------------------------------------------------- +// Description +// Decoding total_zeros from Table9-7,Table9-8,Table9-9 of H.264/AVC standard 2003 +//------------------------------------------------------------------------------------------------- + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on +`include "nova_defines.v" + +module total_zeros_decoding (clk,reset_n,residual_state,cavlc_decoder_state,TotalCoeff_3to0,heading_one_pos, + BitStream_buffer_output,maxNumCoeff,total_zeros,total_zeros_len); + input clk,reset_n; + input [3:0] residual_state; + input [3:0] cavlc_decoder_state; + input [3:0] TotalCoeff_3to0; + input [3:0] heading_one_pos; + input [15:0] BitStream_buffer_output; + output [4:0] maxNumCoeff; + output [3:0] total_zeros; + output [3:0] total_zeros_len; + reg [4:0] maxNumCoeff; + reg [3:0] total_zeros; + reg [3:0] total_zeros_len; + + reg [3:0] total_zeros_reg; + always @ (posedge clk) + if (reset_n == 0) + maxNumCoeff <= 0; + else + case (residual_state) + `Intra16x16DCLevel_s:maxNumCoeff <= 5'd16; + `Intra16x16ACLevel_s:maxNumCoeff <= 15; + `LumaLevel_s :maxNumCoeff <= 5'd16; + `ChromaDCLevel_Cb_s :maxNumCoeff <= 4; + `ChromaDCLevel_Cr_s :maxNumCoeff <= 4; + `ChromaACLevel_Cb_s :maxNumCoeff <= 15; + `ChromaACLevel_Cr_s :maxNumCoeff <= 15; + endcase + + //total_zeros_len + always @ (cavlc_decoder_state or maxNumCoeff or TotalCoeff_3to0 or heading_one_pos or BitStream_buffer_output) + if (cavlc_decoder_state == `total_zeros_LUT) + begin + if (maxNumCoeff == 4) + case (TotalCoeff_3to0) + 1:if (heading_one_pos == 0) total_zeros_len <= 1; + else if (heading_one_pos == 1) total_zeros_len <= 2; + else total_zeros_len <= 3; + 2:if (heading_one_pos == 0) total_zeros_len <= 1; + else total_zeros_len <= 2; + 3: total_zeros_len <= 1; + default: total_zeros_len <= 0; + endcase + else + case (TotalCoeff_3to0) + 1:if (heading_one_pos == 0) total_zeros_len <= 1; + else if (heading_one_pos == 8) total_zeros_len <= 4'd9; + else total_zeros_len <= heading_one_pos + 2; + 2:if (heading_one_pos == 0) total_zeros_len <= 4'd3; + else if (heading_one_pos == 1) + total_zeros_len <= (BitStream_buffer_output[13] == 1'b1)? 4'd3:4'd4; + else if (heading_one_pos == 2) total_zeros_len <= 4; + else if (heading_one_pos == 3) total_zeros_len <= 5; + else if (heading_one_pos == 4) total_zeros_len <= 6; + else total_zeros_len <= 6; + 3:if (heading_one_pos == 0) total_zeros_len <= 4'd3; + else if (heading_one_pos == 1) + total_zeros_len <= (BitStream_buffer_output[13] == 1'b1)? 4'd3:4'd4; + else if (heading_one_pos == 2) total_zeros_len <= 4; + else if (heading_one_pos == 3) total_zeros_len <= 5; + else if (heading_one_pos == 4) total_zeros_len <= 5; + else total_zeros_len <= 4'd6; + 4:if (heading_one_pos == 0) total_zeros_len <= 3; + else if (heading_one_pos == 1) + total_zeros_len <= (BitStream_buffer_output[13] == 1'b1)? 4'd3:4'd4; + else if (heading_one_pos == 2) total_zeros_len <= 4; + else if (heading_one_pos == 3) total_zeros_len <= 5; + else total_zeros_len <= 5; + 5:if (heading_one_pos == 0) total_zeros_len <= 4'd3; + else if (heading_one_pos == 1) + total_zeros_len <= (BitStream_buffer_output[13] == 1'b1)? 4'd3:4'd4; + else if (heading_one_pos == 2) total_zeros_len <= 4; + else if (heading_one_pos == 3) total_zeros_len <= 4; + else total_zeros_len <= 5; + 6:if (heading_one_pos == 0 || heading_one_pos == 1 || heading_one_pos ==2) + total_zeros_len <= 3; + else if (heading_one_pos == 3) total_zeros_len <= 4; + else if (heading_one_pos == 4) total_zeros_len <= 5; + else total_zeros_len <= 6; + 7:if (heading_one_pos == 0 && BitStream_buffer_output[14] == 1) + total_zeros_len <= 2; + else if (heading_one_pos == 0 || heading_one_pos == 1 || heading_one_pos == 2) + total_zeros_len <= 3; + else if (heading_one_pos == 3) total_zeros_len <= 4; + else if (heading_one_pos == 4) total_zeros_len <= 5; + else total_zeros_len <= 6; + 8:if (heading_one_pos == 0) total_zeros_len <= 2; + else if (heading_one_pos == 1 || heading_one_pos == 2) + total_zeros_len <= 3; + else if (heading_one_pos == 3) total_zeros_len <= 4; + else if (heading_one_pos == 4) total_zeros_len <= 5; + else total_zeros_len <= 6; + 9:if (heading_one_pos == 0 || heading_one_pos == 1) + total_zeros_len <= 2; + else if (heading_one_pos == 2) total_zeros_len <= 3; + else if (heading_one_pos == 3) total_zeros_len <= 4; + else if (heading_one_pos == 4) total_zeros_len <= 5; + else total_zeros_len <= 6; + 10:if (heading_one_pos == 0 || heading_one_pos == 1) + total_zeros_len <= 2; + else if (heading_one_pos == 2) total_zeros_len <= 3; + else if (heading_one_pos == 3) total_zeros_len <= 4; + else total_zeros_len <= 5; + 11:if (heading_one_pos == 0) total_zeros_len <= 1; + else if (heading_one_pos == 1 || heading_one_pos == 2) + total_zeros_len <= 3; + else total_zeros_len <= 4; + 12:if (heading_one_pos == 0 || heading_one_pos == 1 || heading_one_pos == 2 || heading_one_pos == 3) + total_zeros_len <= heading_one_pos + 1; + else total_zeros_len <= 4; + 13:if (heading_one_pos == 0 || heading_one_pos == 1 || heading_one_pos == 2) + total_zeros_len <= heading_one_pos + 1; + else total_zeros_len <= 3; + 14:if (heading_one_pos == 0) total_zeros_len <= 1; + else total_zeros_len <= 2; + 15:total_zeros_len <= 1; + default:total_zeros_len <= 0; + endcase + end + else + total_zeros_len <= 0; + + //total_zeros + wire total_zeros_t0,total_zeros_t1; + assign total_zeros_t0 = (cavlc_decoder_state == `total_zeros_LUT && maxNumCoeff != 4); //Table 9-7,9-8 + assign total_zeros_t1 = (cavlc_decoder_state == `total_zeros_LUT && maxNumCoeff == 4); //Table 9-9 + always @ (total_zeros_t0 or total_zeros_t1 or TotalCoeff_3to0 or heading_one_pos + or BitStream_buffer_output or total_zeros_reg) + if (total_zeros_t0) + case (TotalCoeff_3to0) + 1: + if (heading_one_pos == 4'd0) + total_zeros <= 4'd0; + else if (heading_one_pos == 4'd1) + total_zeros <= (BitStream_buffer_output[13])? 4'd1:4'd2; + else if (heading_one_pos == 4'd2) + total_zeros <= (BitStream_buffer_output[12])? 4'd3:4'd4; + else if (heading_one_pos == 4'd3) + total_zeros <= (BitStream_buffer_output[11])? 4'd5:4'd6; + else if (heading_one_pos == 4'd4) + total_zeros <= (BitStream_buffer_output[10])? 4'd7:4'd8; + else if (heading_one_pos == 4'd5) + total_zeros <= (BitStream_buffer_output[9])? 4'd9:4'd10; + else if (heading_one_pos == 4'd6) + total_zeros <= (BitStream_buffer_output[8])? 4'd11:4'd12; + else if (heading_one_pos == 4'd7) + total_zeros <= (BitStream_buffer_output[7])? 4'd13:4'd14; + else + total_zeros <= 4'd15; + 2: + if (heading_one_pos == 4'd0) + total_zeros <= {2'b0,~BitStream_buffer_output[14:13]}; + else if (heading_one_pos == 4'd1) + case (BitStream_buffer_output[13:12]) + 2'b01:total_zeros <= 4'd5; + 2'b00:total_zeros <= 4'd6; + default:total_zeros <= 4'd4; + endcase + else if (heading_one_pos == 4'd2) + total_zeros <= (BitStream_buffer_output[12])? 4'd7:4'd8; + else if (heading_one_pos == 4'd3) + total_zeros <= (BitStream_buffer_output[11])? 4'd9:4'd10; + else if (heading_one_pos == 4'd4) + total_zeros <= (BitStream_buffer_output[10])? 4'd11:4'd12; + else if (heading_one_pos == 4'd5) + total_zeros <= 4'd13; + else + total_zeros <= 4'd14; + 3: + if (heading_one_pos == 4'd0) + case (BitStream_buffer_output[14:13]) + 2'b00:total_zeros <= 4'd6; + 2'b01:total_zeros <= 4'd3; + 2'b10:total_zeros <= 4'd2; + 2'b11:total_zeros <= 4'd1; + endcase + else if (heading_one_pos == 4'd1) + case (BitStream_buffer_output[13:12]) + 2'b00:total_zeros <= 4'd4; + 2'b01:total_zeros <= 4'd0; + default:total_zeros <= 4'd7; + endcase + else if (heading_one_pos == 4'd2) + total_zeros <= (BitStream_buffer_output[12])? 4'd5:4'd8; + else if (heading_one_pos == 4'd3) + total_zeros <= (BitStream_buffer_output[11])? 4'd9:4'd10; + else if (heading_one_pos == 4'd4) + total_zeros <= 4'd12; + else if (heading_one_pos == 4'd5) + total_zeros <= 4'd11; + else + total_zeros <= 4'd13; + 4: + if (heading_one_pos == 4'd0) + case (BitStream_buffer_output[14:13]) + 2'b00:total_zeros <= 4'd6; + 2'b01:total_zeros <= 4'd5; + 2'b10:total_zeros <= 4'd4; + 2'b11:total_zeros <= 4'd1; + endcase + else if (heading_one_pos == 4'd1) + case (BitStream_buffer_output[13:12]) + 2'b00:total_zeros <= 4'd3; + 2'b01:total_zeros <= 4'd2; + default:total_zeros <= 4'd8; + endcase + else if (heading_one_pos == 4'd2) + total_zeros <= (BitStream_buffer_output[12])? 4'd7:4'd9; + else if (heading_one_pos == 4'd3) + total_zeros <= (BitStream_buffer_output[11])? 4'd0:4'd10; + else if (heading_one_pos == 4'd4) + total_zeros <= 4'd11; + else + total_zeros <= 4'd12; + 5: + if (heading_one_pos == 4'd0) + case (BitStream_buffer_output[14:13]) + 2'b00:total_zeros <= 4'd6; + 2'b01:total_zeros <= 4'd5; + 2'b10:total_zeros <= 4'd4; + 2'b11:total_zeros <= 4'd3; + endcase + else if (heading_one_pos == 4'd1) + case (BitStream_buffer_output[13:12]) + 2'b00:total_zeros <= 4'd1; + 2'b01:total_zeros <= 4'd0; + default:total_zeros <= 4'd7; + endcase + else if (heading_one_pos == 4'd2) + total_zeros <= (BitStream_buffer_output[12])? 4'd2:4'd8; + else if (heading_one_pos == 4'd3) + total_zeros <= 4'd10; + else if (heading_one_pos == 4'd4) + total_zeros <= 4'd9; + else + total_zeros <= 4'd11; + 6: + if (heading_one_pos == 4'd0) + case (BitStream_buffer_output[14:13]) + 2'b00:total_zeros <= 4'd5; + 2'b01:total_zeros <= 4'd4; + 2'b10:total_zeros <= 4'd3; + 2'b11:total_zeros <= 4'd2; + endcase + else if (heading_one_pos == 4'd1) + total_zeros <= (BitStream_buffer_output[13])? 4'd6:4'd7; + else if (heading_one_pos == 4'd2) + total_zeros <= 4'd9; + else if (heading_one_pos == 4'd3) + total_zeros <= 4'd8; + else if (heading_one_pos == 4'd4) + total_zeros <= 4'd1; + else if (heading_one_pos == 4'd5) + total_zeros <= 4'd0; + else + total_zeros <= 4'd10; + 7: + if (heading_one_pos == 4'd0) + case (BitStream_buffer_output[14:13]) + 2'b00:total_zeros <= 4'd3; + 2'b01:total_zeros <= 4'd2; + default:total_zeros <= 4'd5; + endcase + else if (heading_one_pos == 4'd1) + total_zeros <= (BitStream_buffer_output[13])? 4'd4:4'd6; + else if (heading_one_pos == 4'd2) + total_zeros <= 4'd8; + else if (heading_one_pos == 4'd3) + total_zeros <= 4'd7; + else if (heading_one_pos == 4'd4) + total_zeros <= 4'd1; + else if (heading_one_pos == 4'd5) + total_zeros <= 4'd0; + else + total_zeros <= 4'd9; + 8: + if (heading_one_pos == 4'd0) + total_zeros <= (BitStream_buffer_output[14])? 4'd4:4'd5; + else if (heading_one_pos == 4'd1) + total_zeros <= (BitStream_buffer_output[13])? 4'd3:4'd6; + else if (heading_one_pos == 4'd2) + total_zeros <= 4'd7; + else if (heading_one_pos == 4'd3) + total_zeros <= 4'd1; + else if (heading_one_pos == 4'd4) + total_zeros <= 4'd2; + else if (heading_one_pos == 4'd5) + total_zeros <= 4'd0; + else + total_zeros <= 4'd8; + 9: + if (heading_one_pos == 4'd0) + total_zeros <= (BitStream_buffer_output[14])? 4'd3:4'd4; + else if (heading_one_pos == 4'd1) + total_zeros <= 4'd6; + else if (heading_one_pos == 4'd2) + total_zeros <= 4'd5; + else if (heading_one_pos == 4'd3) + total_zeros <= 4'd2; + else if (heading_one_pos == 4'd4) + total_zeros <= 4'd7; + else if (heading_one_pos == 4'd5) + total_zeros <= 4'd0; + else + total_zeros <= 4'd1; + 10: + if (heading_one_pos == 4'd0) + total_zeros <= (BitStream_buffer_output[14])? 4'd3:4'd4; + else if (heading_one_pos == 4'd1) + total_zeros <= 4'd5; + else if (heading_one_pos == 4'd2) + total_zeros <= 4'd2; + else if (heading_one_pos == 4'd3) + total_zeros <= 4'd6; + else if (heading_one_pos == 4'd4) + total_zeros <= 4'd0; + else + total_zeros <= 4'd1; + 11: + if (heading_one_pos == 4'd0) + total_zeros <= 4'd4; + else if (heading_one_pos == 4'd1) + total_zeros <= (BitStream_buffer_output[13])? 4'd5:4'd3; + else if (heading_one_pos == 4'd2) + total_zeros <= 4'd2; + else if (heading_one_pos == 4'd3) + total_zeros <= 4'd1; + else + total_zeros <= 4'd0; + 12: + if (heading_one_pos == 4'd0) + total_zeros <= 4'd3; + else if (heading_one_pos == 4'd1) + total_zeros <= 4'd2; + else if (heading_one_pos == 4'd2) + total_zeros <= 4'd4; + else if (heading_one_pos == 4'd3) + total_zeros <= 4'd1; + else + total_zeros <= 4'd0; + 13: + if (heading_one_pos == 4'd0) + total_zeros <= 4'd2; + else if (heading_one_pos == 4'd1) + total_zeros <= 4'd3; + else if (heading_one_pos == 4'd2) + total_zeros <= 4'd1; + else + total_zeros <= 4'd0; + 14: + if (heading_one_pos == 4'd0) + total_zeros <= 4'd2; + else if (heading_one_pos == 4'd1) + total_zeros <= 4'd1; + else + total_zeros <= 4'd0; + default:total_zeros <= (heading_one_pos == 4'd0)? 4'd1:4'd0; + endcase + else if (total_zeros_t1) + case (TotalCoeff_3to0) + 1:if (heading_one_pos == 4'd0) total_zeros <= 4'd0; + else if (heading_one_pos == 4'd1) total_zeros <= 4'd1; + else if (heading_one_pos == 4'd2) total_zeros <= 4'd2; + else total_zeros <= 4'd3; + 2:if (heading_one_pos == 4'd0) total_zeros <= 4'd0; + else if (heading_one_pos == 4'd1) total_zeros <= 4'd1; + else total_zeros <= 4'd2; + 3:total_zeros <= {3'b0,~BitStream_buffer_output[15]}; + default:total_zeros <= 0; + endcase + else + total_zeros <= total_zeros_reg; + + always @ (posedge clk) + if (reset_n == 0) + total_zeros_reg <= 0; + else if (cavlc_decoder_state == `total_zeros_LUT) + total_zeros_reg <= total_zeros; + +endmodule + + diff --git a/demo_chip_rtl/rtl/nova/trunk/test/bin2hex.pl b/demo_chip_rtl/rtl/nova/trunk/test/bin2hex.pl new file mode 100644 index 0000000..9fd4bfb --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/test/bin2hex.pl @@ -0,0 +1,35 @@ +#! /usr/bin/perl + +# Author(s) : Ke Xu +# Email : eexuke@yahoo.com +# Description: Convert binary .264 file to text format +# Usage : bin2hex.pl xxx.264 +# Copyright (C) 2008 Ke Xu + +open STDOUT, ">akiyo300_1ref.txt" || die "Can't open output file:$!\n"; +if (open(BINFILE,"<".$ARGV[0])) +{ + binmode(BINFILE); + $s = ''; + $i = 0; + while (!eof(BINFILE)) + { + if ($i >= 2) + { + printf "%s\n",$s; + $s = ''; + $i = 0; + } + else + { + $i++; + $s .= sprintf("%02X",ord(getc(BINFILE))); + } + } + ###if last line of BINFILE is less than 16 byte + if ($i < 2) + { + printf "%s",$s; + } + close (BINFILE); +} diff --git a/demo_chip_rtl/rtl/nova/trunk/test/bitstream/akiyo300_1ref.txt b/demo_chip_rtl/rtl/nova/trunk/test/bitstream/akiyo300_1ref.txt new file mode 100644 index 0000000..703af5d --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/test/bitstream/akiyo300_1ref.txt @@ -0,0 +1,131072 @@ +0000 +0001 +6742 +001E +E741 +6272 +0000 +0001 +68CE +3880 +0000 +0001 +6588 +8400 +09BC +447E +9FC4 +0000 +803E +651B +DC99 +961C +1B09 +77E1 +2CA1 +4BC0 +8801 +8520 +6FC6 +7B8B +FFFF +0857 +5E17 +2B5A +A104 +2F94 +07C7 +8130 +1852 +8670 +0005 +65E3 +9C59 +7FFF +E687 +FBDF +EA02 +2F81 +20B8 +B3DC +B4F0 +F387 +E16F +77E2 +04A8 +6D1F +C721 +3C3C +90BF +B74F +FF2C +4711 +F2FC +3B73 +61B9 +3D55 +AE06 +0002 +B408 +2135 +8238 +1F0F +1E00 +0477 +07DC +5BFC +4FFE +8BDE +063D +DF17 +588C +A31B +BEAF +FE81 +1438 +F7F3 +278F +F8D6 +6833 +EB6B +8BFE +114F +C6EF +C769 +F4E1 +2001 +6038 +824B +01B6 +C46D +F85B +089B +C29C +D34F +EF7F +8416 +2A8B +98BD +C004 +BBC5 +24F0 +61BE +56CB +687B +1BD7 +6DA3 +6555 +B583 +940C +006C +0F73 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+0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 +0000 \ No newline at end of file diff --git a/demo_chip_rtl/rtl/nova/trunk/test/hex2bin.cpp b/demo_chip_rtl/rtl/nova/trunk/test/hex2bin.cpp new file mode 100644 index 0000000..72fe798 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/test/hex2bin.cpp @@ -0,0 +1,27 @@ +// Author(s) : Ke Xu +// Email : eexuke@yahoo.com +// Description: Convert text file to binary (.yuv) file +// Copyright (C) 2008 Ke Xu + +#include +int main () +{ + int buffer; + int i; + FILE * inFile; + FILE * outFile; + inFile = fopen ("C:/xxx/xxx/nova_display.log","r"); + outFile = fopen ("C:/xxx/xxx/nova300.yuv", "w+b"); + + //1 frame:9504 x 32bit + //300 frame:9504 x 300 x 32 bit = 2851200 x 32bit + for (i = 0; i < 2851200; i++) + { + fscanf (inFile,"%x",&buffer); + fwrite (&buffer,4,1,outFile); + } + fclose (inFile); + fclose (outFile); + return 0; +} + diff --git a/demo_chip_rtl/rtl/nova/trunk/test/readme.txt b/demo_chip_rtl/rtl/nova/trunk/test/readme.txt new file mode 100644 index 0000000..97e56f8 --- /dev/null +++ b/demo_chip_rtl/rtl/nova/trunk/test/readme.txt @@ -0,0 +1,5 @@ +bin2hex.pl :convert binary .264 into text format. + +hex2bin.cpp:convert text format to binary .264. + +bitstream folder:encoded bitstream .264 should be converted first by bin2hex.pl while .txt can be directly read into verilog. \ No newline at end of file diff --git a/demo_chip_rtl/rtl/usb/trunk/doc/README.txt b/demo_chip_rtl/rtl/usb/trunk/doc/README.txt new file mode 100644 index 0000000..a3fea07 --- /dev/null +++ b/demo_chip_rtl/rtl/usb/trunk/doc/README.txt @@ -0,0 +1,41 @@ + +The USB 2.0 Function Project Page is: +http://www.opencores.org/cores/usb/ + +To find out more about me (Rudolf Usselmann), please visit: +http://www.asics.ws + +Directory Structure +------------------- +[core_root] + | + +-doc Documentation + | + +-bench--+ Test Bench + | +- verilog Verilog Sources + | +-vhdl VHDL Sources + | + +-rtl----+ Core RTL Sources + | +-verilog Verilog Sources + | +-vhdl VHDL Sources + | + +-sim----+ + | +-rtl_sim---+ Functional verification Directory + | | +-bin Makefiles/Run Scripts + | | +-run Working Directory + | | + | +-gate_sim--+ Functional & Timing Gate Level + | | Verification Directory + | +-bin Makefiles/Run Scripts + | +-run Working Directory + | + +-lint--+ Lint Directory Tree + | +-bin Makefiles/Run Scripts + | +-run Working Directory + | +-log Linter log & result files + | + +-syn---+ Synthesis Directory Tree + | +-bin Synthesis Scripts + | +-run Working Directory + | +-log Synthesis log files + | +-out Synthesis Output diff --git a/demo_chip_rtl/rtl/usb/trunk/doc/STATUS.txt b/demo_chip_rtl/rtl/usb/trunk/doc/STATUS.txt new file mode 100644 index 0000000..903daaa --- /dev/null +++ b/demo_chip_rtl/rtl/usb/trunk/doc/STATUS.txt @@ -0,0 +1,44 @@ +This file describes the current status of the checked in HDL code. +Please submit all bugs/comments/suggestions regarding the USB core +to: usb@opencores.org + +Need Help +--------- +I'm looking for help in verifying the core. If you think you can help, +please send an email to the list or to me directly. + + +STATUS +====== + +Update (8/2/2001) +----------------- +- Changed Directory Structure + +Initial Release (31/3/2001) +--------------------------- +- This is the second officially available release of the core +- It is still under active development +- Please do not modify the sources ! +- Things that are not implemented yet, or are known not to work yet: + - There is no logic in the core to "help" suspending it. I'm not + quite sure yet what to do in this area. (Suggestions welcomed !) + - There has been very little testing done on the core + +Initial Release (28/2/2001) +--------------------------- +- This is the very first officially available release of the core +- It is still under active development +- Please do not modify the sources ! +- Things that are not implemented yet, or are known not to work yet: + - UTMI line/link control interface is not implemented yet. This includes: + - Detection of attach/detach + - Speed negotiation (Full/High Speed) + - USB reset + - USB suspend + - There is no logic in the core to "help" suspending it. I'm not + quite sure yet what to do in this area. (Suggestions welcomed !) + - There is no easy way to configure the core (number of endpoints, + buffer size) + - There has been absolutely no testing done on the core + diff --git a/demo_chip_rtl/rtl/usb/trunk/doc/usb_doc.pdf b/demo_chip_rtl/rtl/usb/trunk/doc/usb_doc.pdf new file mode 100644 index 0000000..e689b33 Binary files /dev/null and b/demo_chip_rtl/rtl/usb/trunk/doc/usb_doc.pdf differ diff --git a/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_crc16.v b/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_crc16.v new file mode 100644 index 0000000..674f2b2 --- /dev/null +++ b/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_crc16.v @@ -0,0 +1,106 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// USB CRC5 and CRC16 Modules //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/usb/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2003 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: usbf_crc16.v,v 1.2 2003-10-17 02:36:57 rudi Exp $ +// +// $Date: 2003-10-17 02:36:57 $ +// $Revision: 1.2 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.1 2001/08/03 05:30:09 rudi +// +// +// 1) Reorganized directory structure +// +// Revision 1.0 2001/03/07 09:17:12 rudi +// +// +// Changed all revisions to revision 1.0. This is because OpenCores CVS +// interface could not handle the original '0.1' revision .... +// +// Revision 0.1.0.1 2001/02/28 08:10:42 rudi +// Initial Release +// +// + +`include "usbf_defines.v" + +/////////////////////////////////////////////////////////////////// +// +// CRC16 +// +/////////////////////////////////////////////////////////////////// + +module usbf_crc16(crc_in, din, crc_out); +input [15:0] crc_in; +input [7:0] din; +output [15:0] crc_out; + +assign crc_out[0] = din[7] ^ din[6] ^ din[5] ^ din[4] ^ din[3] ^ + din[2] ^ din[1] ^ din[0] ^ crc_in[8] ^ crc_in[9] ^ + crc_in[10] ^ crc_in[11] ^ crc_in[12] ^ crc_in[13] ^ + crc_in[14] ^ crc_in[15]; +assign crc_out[1] = din[7] ^ din[6] ^ din[5] ^ din[4] ^ din[3] ^ din[2] ^ + din[1] ^ crc_in[9] ^ crc_in[10] ^ crc_in[11] ^ + crc_in[12] ^ crc_in[13] ^ crc_in[14] ^ crc_in[15]; +assign crc_out[2] = din[1] ^ din[0] ^ crc_in[8] ^ crc_in[9]; +assign crc_out[3] = din[2] ^ din[1] ^ crc_in[9] ^ crc_in[10]; +assign crc_out[4] = din[3] ^ din[2] ^ crc_in[10] ^ crc_in[11]; +assign crc_out[5] = din[4] ^ din[3] ^ crc_in[11] ^ crc_in[12]; +assign crc_out[6] = din[5] ^ din[4] ^ crc_in[12] ^ crc_in[13]; +assign crc_out[7] = din[6] ^ din[5] ^ crc_in[13] ^ crc_in[14]; +assign crc_out[8] = din[7] ^ din[6] ^ crc_in[0] ^ crc_in[14] ^ crc_in[15]; +assign crc_out[9] = din[7] ^ crc_in[1] ^ crc_in[15]; +assign crc_out[10] = crc_in[2]; +assign crc_out[11] = crc_in[3]; +assign crc_out[12] = crc_in[4]; +assign crc_out[13] = crc_in[5]; +assign crc_out[14] = crc_in[6]; +assign crc_out[15] = din[7] ^ din[6] ^ din[5] ^ din[4] ^ din[3] ^ din[2] ^ + din[1] ^ din[0] ^ crc_in[7] ^ crc_in[8] ^ crc_in[9] ^ + crc_in[10] ^ crc_in[11] ^ crc_in[12] ^ crc_in[13] ^ + crc_in[14] ^ crc_in[15]; + +endmodule + diff --git a/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_crc5.v b/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_crc5.v new file mode 100644 index 0000000..487141c --- /dev/null +++ b/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_crc5.v @@ -0,0 +1,97 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// USB CRC5 and CRC16 Modules //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/usb/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2003 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: usbf_crc5.v,v 1.2 2003-10-17 02:36:57 rudi Exp $ +// +// $Date: 2003-10-17 02:36:57 $ +// $Revision: 1.2 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.1 2001/08/03 05:30:09 rudi +// +// +// 1) Reorganized directory structure +// +// Revision 1.0 2001/03/07 09:17:12 rudi +// +// +// Changed all revisions to revision 1.0. This is because OpenCores CVS +// interface could not handle the original '0.1' revision .... +// +// Revision 0.1.0.1 2001/02/28 08:10:42 rudi +// Initial Release +// +// + +`include "usbf_defines.v" + +/////////////////////////////////////////////////////////////////// +// +// CRC5 +// +/////////////////////////////////////////////////////////////////// + +module usbf_crc5(crc_in, din, crc_out); +input [4:0] crc_in; +input [10:0] din; +output [4:0] crc_out; + +assign crc_out[0] = din[10] ^ din[9] ^ din[6] ^ din[5] ^ din[3] ^ + din[0] ^ crc_in[0] ^ crc_in[3] ^ crc_in[4]; + +assign crc_out[1] = din[10] ^ din[7] ^ din[6] ^ din[4] ^ din[1] ^ + crc_in[0] ^ crc_in[1] ^ crc_in[4]; + +assign crc_out[2] = din[10] ^ din[9] ^ din[8] ^ din[7] ^ din[6] ^ + din[3] ^ din[2] ^ din[0] ^ crc_in[0] ^ crc_in[1] ^ + crc_in[2] ^ crc_in[3] ^ crc_in[4]; + +assign crc_out[3] = din[10] ^ din[9] ^ din[8] ^ din[7] ^ din[4] ^ din[3] ^ + din[1] ^ crc_in[1] ^ crc_in[2] ^ crc_in[3] ^ crc_in[4]; + +assign crc_out[4] = din[10] ^ din[9] ^ din[8] ^ din[5] ^ din[4] ^ din[2] ^ + crc_in[2] ^ crc_in[3] ^ crc_in[4]; + +endmodule + diff --git a/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_defines.v b/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_defines.v new file mode 100644 index 0000000..8d0f17b --- /dev/null +++ b/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_defines.v @@ -0,0 +1,285 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// USB function defines file //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/usb/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2003 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: usbf_defines.v,v 1.6 2003-10-17 02:36:57 rudi Exp $ +// +// $Date: 2003-10-17 02:36:57 $ +// $Revision: 1.6 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.5 2001/11/04 12:22:43 rudi +// +// - Fixed previous fix (brocke something else ...) +// - Majore Synthesis cleanup +// +// Revision 1.4 2001/09/23 08:39:33 rudi +// +// Renamed DEBUG and VERBOSE_DEBUG to USBF_DEBUG and USBF_VERBOSE_DEBUG ... +// +// Revision 1.3 2001/09/13 13:14:02 rudi +// +// Fixed a problem that would sometimes prevent the core to come out of +// reset and immediately be operational ... +// +// Revision 1.2 2001/08/10 08:48:33 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// +// Revision 1.1 2001/08/03 05:30:09 rudi +// +// +// 1) Reorganized directory structure +// +// Revision 1.2 2001/03/31 13:00:52 rudi +// +// - Added Core configuration +// - Added handling of OUT packets less than MAX_PL_SZ in DMA mode +// - Modified WISHBONE interface and sync logic +// - Moved SSRAM outside the core (added interface) +// - Many small bug fixes ... +// +// Revision 1.0 2001/03/07 09:17:12 rudi +// +// +// Changed all revisions to revision 1.0. This is because OpenCores CVS +// interface could not handle the original '0.1' revision .... +// +// Revision 0.2 2001/03/07 09:08:13 rudi +// +// Added USB control signaling (Line Status) block. Fixed some minor +// typos, added resume bit and signal. +// +// Revision 0.1.0.1 2001/02/28 08:11:35 rudi +// Initial Release +// +// + +`timescale 1ns / 10ps + +// Uncomment the lines below to get various levels of debugging +// verbosity ... +`define USBF_DEBUG +//`define USBF_VERBOSE_DEBUG + +// Uncomment the line below to run the test bench +// Comment it out to use your own address parameters ... +`define USBF_TEST_IMPL + +// For each endpoint that should actually be instantiated, +// set the below define value to a one. Uncomment the define +// statement for unused endpoints. The endpoints should be +// sequential, e.q. 1,2,3. I have not tested what happens if +// you select endpoints in a non sequential manner e.g. 1,4,6 +// Actual (logical) endpoint IDs are set by the software. There +// is no correlation between the physical endpoint number (below) +// and the actual (logical) endpoint number. +`ifdef USBF_TEST_IMPL + // Do not modify this section + // this is to run the test bench + `define USBF_HAVE_EP1 1 + `define USBF_HAVE_EP2 1 + `define USBF_HAVE_EP3 1 +`else + // Modify this section to suit your implementation + `define USBF_HAVE_EP1 1 + `define USBF_HAVE_EP2 1 + `define USBF_HAVE_EP3 1 + //`define USBF_HAVE_EP4 1 + //`define USBF_HAVE_EP5 1 + //`define USBF_HAVE_EP6 1 + //`define USBF_HAVE_EP7 1 + //`define USBF_HAVE_EP8 1 + //`define USBF_HAVE_EP9 1 + //`define USBF_HAVE_EP10 1 + //`define USBF_HAVE_EP11 1 + //`define USBF_HAVE_EP12 1 + //`define USBF_HAVE_EP13 1 + //`define USBF_HAVE_EP14 1 + //`define USBF_HAVE_EP15 1 +`endif + + +// Highest address line number that goes to the USB core +// Typically only A0 through A17 are needed, where A17 +// selects between the internal buffer memory and the +// register file. +// Implementations may choose to have a more complex address +// decoding .... + +`ifdef USBF_TEST_IMPL + // Do not modify this section + // this is to run the test bench + `define USBF_UFC_HADR 17 + `define USBF_RF_SEL (!wb_addr_i[17]) + `define USBF_MEM_SEL (wb_addr_i[17]) + `define USBF_SSRAM_HADR 14 + //`define USBF_ASYNC_RESET + +`else + // Modify this section to suit your implementation + `define USBF_UFC_HADR 12 + // Address Decoding for Register File select + `define USBF_RF_SEL (!wb_addr_i[12]) + // Address Decoding for Buffer Memory select + `define USBF_MEM_SEL (wb_addr_i[12]) + `define USBF_SSRAM_HADR 9 + // The next statement determines if reset is async or sync. + // If the define is uncommented the reset will be ASYNC. + //`define USBF_ASYNC_RESET +`endif + + +///////////////////////////////////////////////////////////////////// +// +// Items below this point should NOT be modified by the end user +// UNLESS you know exactly what you are doing ! +// Modify at you own risk !!! +// +///////////////////////////////////////////////////////////////////// + +// PID Encodings +`define USBF_T_PID_OUT 4'b0001 +`define USBF_T_PID_IN 4'b1001 +`define USBF_T_PID_SOF 4'b0101 +`define USBF_T_PID_SETUP 4'b1101 +`define USBF_T_PID_DATA0 4'b0011 +`define USBF_T_PID_DATA1 4'b1011 +`define USBF_T_PID_DATA2 4'b0111 +`define USBF_T_PID_MDATA 4'b1111 +`define USBF_T_PID_ACK 4'b0010 +`define USBF_T_PID_NACK 4'b1010 +`define USBF_T_PID_STALL 4'b1110 +`define USBF_T_PID_NYET 4'b0110 +`define USBF_T_PID_PRE 4'b1100 +`define USBF_T_PID_ERR 4'b1100 +`define USBF_T_PID_SPLIT 4'b1000 +`define USBF_T_PID_PING 4'b0100 +`define USBF_T_PID_RES 4'b0000 + +// The HMS_DEL is a constant for the "Half Micro Second" +// Clock pulse generator. This constant specifies how many +// Phy clocks there are between two hms_clock pulses. This +// constant plus 2 represents the actual delay. +// Example: For a 60 Mhz (16.667 nS period) Phy Clock, the +// delay must be 30 phy clocks: 500ns / 16.667nS = 30 clocks +`define USBF_HMS_DEL 5'h1c + +// After sending Data in response to an IN token from host, the +// host must reply with an ack. The host has 622nS in Full Speed +// mode and 400nS in High Speed mode to reply. RX_ACK_TO_VAL_FS +// and RX_ACK_TO_VAL_HS are the numbers of UTMI clock cycles +// minus 2 for Full and High Speed modes. +`define USBF_RX_ACK_TO_VAL_FS 8'd36 +`define USBF_RX_ACK_TO_VAL_HS 8'd22 + + +// After sending an OUT token the host must send a data packet. +// The host has 622nS in Full Speed mode and 400nS in High Speed +// mode to send the data packet. +// TX_DATA_TO_VAL_FS and TX_DATA_TO_VAL_HS are is the numbers of +// UTMI clock cycles minus 2. +`define USBF_TX_DATA_TO_VAL_FS 8'd36 +`define USBF_TX_DATA_TO_VAL_HS 8'd22 + + +// -------------------------------------------------- +// USB Line state & Speed Negotiation Time Values + + +// Prescaler Clear value. +// The prescaler generates a 0.25uS pulse, from a nominal PHY clock of +// 60 Mhz. 250nS/16.667ns=15. The prescaler has to be cleared every 15 +// cycles. Due to the pipeline, subtract 2 from 15, resulting in 13 cycles. +// !!! This is the only place that needs to be changed if a PHY with different +// !!! clock output is used. +`define USBF_T1_PS_250_NS 4'd13 + +// uS counter representation of 2.5uS (2.5/0.25=10) +`define USBF_T1_C_2_5_US 8'd10 + +// uS counter clear value +// The uS counter counts the time in 0.25uS intervals. It also generates +// a count enable to the mS counter, every 62.5 uS. +// The clear value is 62.5uS/0.25uS=250 cycles. +`define USBF_T1_C_62_5_US 8'd250 + +// mS counter representation of 3.0mS (3.0/0.0625=48) +`define USBF_T1_C_3_0_MS 8'd48 + +// mS counter representation of 3.125mS (3.125/0.0625=50) +`define USBF_T1_C_3_125_MS 8'd50 + +// mS counter representation of 5mS (5/0.0625=80) +`define USBF_T1_C_5_MS 8'd80 + +// Multi purpose Counter Prescaler, generate 2.5 uS period +// 2500/16.667ns=150 (minus 2 for pipeline) +`define USBF_T2_C_2_5_US 8'd148 + +// Generate 0.5mS period from the 2.5 uS clock +// 500/2.5 = 200 +`define USBF_T2_C_0_5_MS 8'd200 + +// Indicate when internal wakeup has completed +// me_cnt counts 0.5 mS intervals. E.g.: 5.0mS are (5/0.5) 10 ticks +// Must be 0 =< 10 mS +`define USBF_T2_C_WAKEUP 8'd10 + +// Indicate when 100uS have passed +// me_ps2 counts 2.5uS intervals. 100uS are (100/2.5) 40 ticks +`define USBF_T2_C_100_US 8'd40 + +// Indicate when 1.0 mS have passed +// me_cnt counts 0.5 mS intervals. 1.0mS are (1/0.5) 2 ticks +`define USBF_T2_C_1_0_MS 8'd2 + +// Indicate when 1.2 mS have passed +// me_cnt counts 0.5 mS intervals. 1.2mS are (1.2/0.5) 2 ticks +`define USBF_T2_C_1_2_MS 8'd2 + +// Indicate when 100 mS have passed +// me_cnt counts 0.5 mS intervals. 100mS are (100/0.5) 200 ticks +`define USBF_T2_C_100_MS 8'd200 + diff --git a/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_ep_rf.v b/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_ep_rf.v new file mode 100644 index 0000000..76a7af2 --- /dev/null +++ b/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_ep_rf.v @@ -0,0 +1,507 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Endpoint register File //// +//// This module contains all registers for ONE endpoint //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/usb/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2003 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: usbf_ep_rf.v,v 1.4 2003-10-17 02:36:57 rudi Exp $ +// +// $Date: 2003-10-17 02:36:57 $ +// $Revision: 1.4 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.3 2001/11/04 12:22:44 rudi +// +// - Fixed previous fix (brocke something else ...) +// - Majore Synthesis cleanup +// +// Revision 1.2 2001/11/03 03:26:22 rudi +// +// - Fixed several interrupt and error condition reporting bugs +// +// Revision 1.1 2001/08/03 05:30:09 rudi +// +// +// 1) Reorganized directory structure +// +// Revision 1.2 2001/03/31 13:00:51 rudi +// +// - Added Core configuration +// - Added handling of OUT packets less than MAX_PL_SZ in DMA mode +// - Modified WISHBONE interface and sync logic +// - Moved SSRAM outside the core (added interface) +// - Many small bug fixes ... +// +// Revision 1.0 2001/03/07 09:17:12 rudi +// +// +// Changed all revisions to revision 1.0. This is because OpenCores CVS +// interface could not handle the original '0.1' revision .... +// +// Revision 0.1.0.1 2001/02/28 08:10:44 rudi +// Initial Release +// +// + +`include "usbf_defines.v" + +// Endpoint register File +module usbf_ep_rf(clk, wclk, rst, + + // Wishbone Interface + adr, re, we, din, dout, inta, intb, + dma_req, dma_ack, + + // Internal Interface + + idin, + ep_sel, ep_match, + buf0_rl, buf0_set, buf1_set, + uc_bsel_set, uc_dpd_set, + + int_buf1_set, int_buf0_set, int_upid_set, + int_crc16_set, int_to_set, int_seqerr_set, + out_to_small, + + csr, buf0, buf1, dma_in_buf_sz1, dma_out_buf_avail + ); + +input clk, wclk, rst; +input [1:0] adr; +input re; +input we; +input [31:0] din; +output [31:0] dout; +output inta, intb; +output dma_req; +input dma_ack; + +input [31:0] idin; // Data Input +input [3:0] ep_sel; // Endpoint Number Input +output ep_match; // Asserted to indicate a ep no is matched +input buf0_rl; // Reload Buf 0 with original values + +input buf0_set; // Write to buf 0 +input buf1_set; // Write to buf 1 +input uc_bsel_set; // Write to the uc_bsel field +input uc_dpd_set; // Write to the uc_dpd field +input int_buf1_set; // Set buf1 full/empty interrupt +input int_buf0_set; // Set buf0 full/empty interrupt +input int_upid_set; // Set unsupported PID interrupt +input int_crc16_set; // Set CRC16 error interrupt +input int_to_set; // Set time out interrupt +input int_seqerr_set; // Set PID sequence error interrupt +input out_to_small; // OUT packet was to small for DMA operation + +output [31:0] csr; // Internal CSR Output +output [31:0] buf0; // Internal Buf 0 Output +output [31:0] buf1; // Internal Buf 1 Output +output dma_in_buf_sz1; // Indicates that the DMA IN buffer has 1 max_pl_sz + // packet available +output dma_out_buf_avail;// Indicates that there is space for at least + // one MAX_PL_SZ packet in the buffer + +/////////////////////////////////////////////////////////////////// +// +// Local Wires and Registers +// + +reg [31:0] dout; + +// CSR +reg [12:0] csr0; +reg ots_stop; +reg [12:0] csr1; +reg [1:0] uc_bsel, uc_dpd; + +reg [5:0] iena, ienb; // Interrupt enables +reg [6:0] int_stat; // Interrupt status + +wire we0, we1, we2, we3; +reg [31:0] buf0; +reg [31:0] buf1; +reg [31:0] buf0_orig; + +reg inta, intb; + +// DMA Logic Registers +reg [11:0] dma_out_cnt; +wire dma_out_cnt_is_zero; +reg dma_out_buf_avail; +reg [11:0] dma_out_left; + +reg [11:0] dma_in_cnt; +reg dma_in_buf_sz1; + +reg dma_req_r; +wire dma_req_d; +wire dma_req_in_d; +wire dma_req_out_d; +reg r1, r2, r4, r5; +wire dma_ack_i; +reg dma_req_out_hold, dma_req_in_hold ; +reg [11:0] buf0_orig_m3; +wire dma_req_hold; +reg set_r; +reg ep_match_r; +reg int_re; + +// Aliases +wire [31:0] csr; +wire [31:0] int; +wire dma_en; +wire [10:0] max_pl_sz; +wire ep_in; +wire ep_out; + +assign csr = {uc_bsel, uc_dpd, csr1, 1'h0, ots_stop, csr0}; +assign int = {2'h0, iena, 2'h0,ienb, 9'h0, int_stat}; +assign dma_en = csr[15]; +assign max_pl_sz = csr[10:0]; +assign ep_in = csr[27:26]==2'b01; +assign ep_out = csr[27:26]==2'b10; + +/////////////////////////////////////////////////////////////////// +// +// WISHBONE Access +// + +always @(adr or csr or int or buf0 or buf1) + case(adr) // synopsys full_case parallel_case + 2'h0: dout = csr; + 2'h1: dout = int; + 2'h2: dout = buf0; + 2'h3: dout = buf1; + endcase + +assign we0 = (adr==2'h0) & we; +assign we1 = (adr==2'h1) & we; +assign we2 = (adr==2'h2) & we; +assign we3 = (adr==2'h3) & we; + +// Endpoint CSR Register +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) + begin + csr0 <= 13'h0; + csr1 <= 13'h0; + ots_stop <= 1'b0; + end + else + if(we0) + begin + csr0 <= din[12:0]; + ots_stop <= din[13]; + csr1 <= din[27:15]; + end + else + if(ots_stop && out_to_small) + csr1[8:7] <= 2'b01; + +// Endpoint Interrupt Register +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) + begin + ienb <= 6'h0; + iena <= 6'h0; + end + else + if(we1) + begin + ienb <= din[21:16]; + iena <= din[29:24]; + end + +// Endpoint Buffer Registers +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) buf0 <= 32'hffff_ffff; + else + if(we2) buf0 <= din; + else + if(ep_match_r && buf0_rl) buf0 <= buf0_orig; + else + if(ep_match_r && buf0_set) buf0 <= idin; + +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) buf1 <= 32'hffff_ffff; + else + if(we3) buf1 <= din; + else + if(ep_match_r && + (buf1_set || out_to_small)) buf1 <= idin; + +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) buf0_orig <= 32'hffff_ffff; + else + if(we2) buf0_orig <= din; + +/////////////////////////////////////////////////////////////////// +// +// Internal Access +// + + +// Indicates that this register file matches the current +// endpoint from token +assign ep_match = (ep_sel == csr[21:18]); + +always @(posedge clk) + ep_match_r <= ep_match; + +always @(posedge clk) + int_re <= re & (adr == 2'h1); + +// Interrupt Sources +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) int_stat <= 7'h0; + else + if(int_re) int_stat <= 7'h0; + else + if(ep_match_r) + begin + if(out_to_small) int_stat[6] <= 1'b1; + if(int_seqerr_set) int_stat[5] <= 1'b1; + if(int_buf1_set) int_stat[4] <= 1'b1; + if(int_buf0_set) int_stat[3] <= 1'b1; + if(int_upid_set) int_stat[2] <= 1'b1; + if(int_crc16_set) int_stat[1] <= 1'b1; + if(int_to_set) int_stat[0] <= 1'b1; + end + +// PID toggle track bits +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) uc_dpd <= 2'h0; + else + if(ep_match_r && uc_dpd_set) uc_dpd <= idin[3:2]; + +// Buffer toggle track bits +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) uc_bsel <= 2'h0; + else + if(ep_match_r && uc_bsel_set) uc_bsel <= idin[1:0]; + +/////////////////////////////////////////////////////////////////// +// +// Endpoint Interrupt Generation +// + +always @(posedge wclk) + inta <= (int_stat[0] & iena[0]) | + (int_stat[1] & iena[1]) | + (int_stat[2] & iena[2]) | + (int_stat[3] & iena[3]) | + (int_stat[4] & iena[3]) | + (int_stat[5] & iena[4]) | + (int_stat[6] & iena[5]); + +always @(posedge wclk) + intb <= (int_stat[0] & ienb[0]) | + (int_stat[1] & ienb[1]) | + (int_stat[2] & ienb[2]) | + (int_stat[3] & ienb[3]) | + (int_stat[4] & ienb[3]) | + (int_stat[5] & ienb[4]) | + (int_stat[6] & ienb[5]); + +/////////////////////////////////////////////////////////////////// +// +// Endpoint DMA Request Logic +// + +// DMA OUT endpoint counter +always @(posedge clk) + if(!dma_en) dma_out_cnt <= 12'h0; + else + if(dma_ack_i) dma_out_cnt <= dma_out_cnt - 12'h1; + else + if(ep_match_r && (set_r || buf0_set || buf0_rl)) + dma_out_cnt <= dma_out_cnt + {3'h0, max_pl_sz[10:2]}; + +// If buf0_set or buf0_rl was asserted at the same time as dma_ack_i +// remember it and perform the add next cycle ... +always @(posedge clk) + set_r <= dma_ack_i & (buf0_set | buf0_rl); + +// This signal is used to keep dma_req asserted when we know there is +// plenty of data in the buffer. +// When the buffer is "low", we do one dma_req and wait to see if there +// is more data and repeat until the buffer is empty. +// This is because of the sync logic - it has to propagate first +// before we can determine that the buffer is really empty. +always @(posedge wclk) + dma_req_out_hold <= |dma_out_cnt[11:2] & ep_out; + +assign dma_out_cnt_is_zero = dma_out_cnt == 12'h0; + +// DMA IN endpoint counter +always @(posedge clk) + if(!dma_en) dma_in_cnt <= 12'h0; + else + if(dma_ack_i) dma_in_cnt <= dma_in_cnt + 12'h1; + else + if(ep_match_r && (set_r || buf0_set || buf0_rl)) + dma_in_cnt <= dma_in_cnt - {3'h0, max_pl_sz[10:2]}; + +// Indicates to Protocol Engine when we have gotten at least one packet in to buffer +// This is for IN transfers only +always @(posedge clk) + dma_in_buf_sz1 <= (dma_in_cnt >= {3'h0,max_pl_sz[10:2]}) & + (max_pl_sz[10:0] != 11'h0); + +// Indicates to Protocol Engine that there is space for at least one MAX_PL_SZ +// packet in buffer. OUT transfers only. +always @(posedge clk) + dma_out_left <= (buf0_orig[30:19] - dma_out_cnt); + +always @(posedge clk) + dma_out_buf_avail <= (dma_out_left >= {3'h0, max_pl_sz[10:2]}); + +// DMA Request Generation +assign dma_req_d = dma_en & (dma_req_in_d | dma_req_out_d); + +// For OUT +assign dma_req_out_d = ep_out & !dma_out_cnt_is_zero; + +// FOR IN +assign dma_req_in_d = ep_in & (dma_in_cnt < buf0_orig[30:19]); + + +always @(posedge wclk) + buf0_orig_m3 <= buf0_orig[30:19] - 12'h3; + +reg dma_req_in_hold2; + +always @(posedge wclk) + dma_req_in_hold2 <= (dma_in_cnt < buf0_orig_m3); + +always @(posedge wclk) + dma_req_in_hold <= ep_in & |buf0_orig[30:21]; + +assign dma_req_hold = ep_out ? dma_req_out_hold : (dma_req_in_hold & dma_req_in_hold2); + +// Generate a Sync. Request +assign dma_req = dma_req_r; + +`ifdef USBF_ASYNC_RESET +always @(posedge wclk or negedge rst) +`else +always @(posedge wclk) +`endif + if(!rst) dma_req_r <= 1'b0; + else + if(r1 && !r2) dma_req_r <= 1'b1; + else + if(dma_ack && !dma_req_hold) dma_req_r <= 1'b0; + +always @(posedge wclk) + r1 <= dma_req_d & !r2 & !r4 & !r5; + +`ifdef USBF_ASYNC_RESET +always @(posedge wclk or negedge rst) +`else +always @(posedge wclk) +`endif + if(!rst) r2 <= 1'b0; + else + if(r1) r2 <= 1'b1; + else + if(r4) r2 <= 1'b0; + +// Synchronize ACK +reg dma_ack_wr1; +reg dma_ack_clr1; + +`ifdef USBF_ASYNC_RESET +always @(posedge wclk or negedge rst) +`else +always @(posedge wclk) +`endif + if(!rst) dma_ack_wr1 <= 1'b0; + else + if(dma_ack) dma_ack_wr1 <= 1'b1; + else + if(dma_ack_clr1) dma_ack_wr1 <= 1'b0; + +always @(posedge wclk) + dma_ack_clr1 <= r4; + +always @(posedge clk) + r4 <= dma_ack_wr1; + +always @(posedge clk) + r5 <= r4; + +assign dma_ack_i = r5; + +endmodule + diff --git a/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_ep_rf_dummy.v b/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_ep_rf_dummy.v new file mode 100644 index 0000000..9c0da57 --- /dev/null +++ b/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_ep_rf_dummy.v @@ -0,0 +1,143 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Dummy Endpoint register File //// +//// This module contains termination for registers in ONE //// +//// endpoint. It is used to replace the actual endpoint //// +//// register file for non existing endpoints. //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/usb/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2003 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: usbf_ep_rf_dummy.v,v 1.2 2003-10-17 02:36:57 rudi Exp $ +// +// $Date: 2003-10-17 02:36:57 $ +// $Revision: 1.2 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.1 2001/08/03 05:30:09 rudi +// +// +// 1) Reorganized directory structure +// +// Revision 1.1 2001/03/31 12:45:13 rudi +// +// This is the endpoint register file for non existing endpoints. It will be used for +// endpoints that are commented out in the usd_defines.v file. +// It will terminate all outputs to a known good level ... +// +// +// + +`include "usbf_defines.v" + +// Endpoint register File +module usbf_ep_rf_dummy( + clk, wclk, rst, + + // Wishbone Interface + adr, re, we, din, dout, inta, intb, + dma_req, dma_ack, + + // Internal Interface + + idin, + ep_sel, ep_match, + buf0_rl, buf0_set, buf1_set, + uc_bsel_set, uc_dpd_set, + + int_buf1_set, int_buf0_set, int_upid_set, + int_crc16_set, int_to_set, int_seqerr_set, + out_to_small, + + csr, buf0, buf1, dma_in_buf_sz1, dma_out_buf_avail + ); + +input clk, wclk, rst; +input [1:0] adr; +input re; +input we; +input [31:0] din; +output [31:0] dout; +output inta, intb; +output dma_req; +input dma_ack; + +input [31:0] idin; // Data Input +input [3:0] ep_sel; // Endpoint Number Input +output ep_match; // Asserted to indicate a ep no is matched +input buf0_rl; // Reload Buf 0 with original values + +input buf0_set; // Write to buf 0 +input buf1_set; // Write to buf 1 +input uc_bsel_set; // Write to the uc_bsel field +input uc_dpd_set; // Write to the uc_dpd field +input int_buf1_set; // Set buf1 full/empty interrupt +input int_buf0_set; // Set buf0 full/empty interrupt +input int_upid_set; // Set unsupported PID interrupt +input int_crc16_set; // Set CRC16 error interrupt +input int_to_set; // Set time out interrupt +input int_seqerr_set; // Set PID sequence error interrupt +input out_to_small; // OUT packet was to small for DMA operation + +output [31:0] csr; // Internal CSR Output +output [31:0] buf0; // Internal Buf 0 Output +output [31:0] buf1; // Internal Buf 1 Output +output dma_in_buf_sz1; // Indicates that the DMA IN buffer has 1 max_pl_sz + // packet available +output dma_out_buf_avail;// Indicates that there is space for at least + // one MAX_PL_SZ packet in the buffer + +/////////////////////////////////////////////////////////////////// +// +// Internal Access +// + +assign dout = 32'h0; +assign inta = 1'b0; +assign intb = 1'b0; +assign dma_req = 1'b0; +assign ep_match = 1'b0; +assign csr = 32'h0; +assign buf0 = 32'hffff_ffff; +assign buf1 = 32'hffff_ffff; +assign dma_in_buf_sz1 = 1'b0; +assign dma_out_buf_avail = 1'b0; + +endmodule + diff --git a/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_idma.v b/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_idma.v new file mode 100644 index 0000000..2ec0450 --- /dev/null +++ b/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_idma.v @@ -0,0 +1,627 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Internal DMA Engine //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/usb/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2003 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: usbf_idma.v,v 1.8 2003-10-17 02:36:57 rudi Exp $ +// +// $Date: 2003-10-17 02:36:57 $ +// $Revision: 1.8 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.7 2001/11/04 12:22:45 rudi +// +// - Fixed previous fix (brocke something else ...) +// - Majore Synthesis cleanup +// +// Revision 1.6 2001/11/03 03:26:22 rudi +// +// - Fixed several interrupt and error condition reporting bugs +// +// Revision 1.5 2001/09/24 01:15:28 rudi +// +// Changed reset to be active high async. +// +// Revision 1.4 2001/09/23 08:39:33 rudi +// +// Renamed DEBUG and VERBOSE_DEBUG to USBF_DEBUG and USBF_VERBOSE_DEBUG ... +// +// Revision 1.3 2001/09/19 14:38:57 rudi +// +// Fixed TxValid handling bug. +// +// Revision 1.2 2001/09/13 13:14:02 rudi +// +// Fixed a problem that would sometimes prevent the core to come out of +// reset and immediately be operational ... +// +// Revision 1.1 2001/08/03 05:30:09 rudi +// +// +// 1) Reorganized directory structure +// +// Revision 1.2 2001/03/31 13:00:51 rudi +// +// - Added Core configuration +// - Added handling of OUT packets less than MAX_PL_SZ in DMA mode +// - Modified WISHBONE interface and sync logic +// - Moved SSRAM outside the core (added interface) +// - Many small bug fixes ... +// +// Revision 1.0 2001/03/07 09:17:12 rudi +// +// +// Changed all revisions to revision 1.0. This is because OpenCores CVS +// interface could not handle the original '0.1' revision .... +// +// Revision 0.1.0.1 2001/02/28 08:10:50 rudi +// Initial Release +// +// + +`include "usbf_defines.v" + +module usbf_idma( clk, rst, + + // Packet Disassembler/Assembler interface + rx_data_st, rx_data_valid, rx_data_done, + send_data, tx_data_st, rd_next, + + // Protocol Engine + rx_dma_en, tx_dma_en, + abort, idma_done, + buf_size, dma_en, + send_zero_length, + + // Register File Manager Interface + adr, size, sizu_c, + + // Memory Arb interface + madr, mdout, mdin, mwe, mreq, mack + ); + +parameter SSRAM_HADR = 14; + +// Packet Disassembler/Assembler interface +input clk, rst; +input [7:0] rx_data_st; +input rx_data_valid; +input rx_data_done; +output send_data; +output [7:0] tx_data_st; +input rd_next; + +// Protocol Engine +input rx_dma_en; // Allows the data to be stored +input tx_dma_en; // Allows for data to be retrieved +input abort; // Abort Transfer (time_out, crc_err or rx_error) +output idma_done; // DMA is done +input [13:0] buf_size; // Actual buffer size +input dma_en; // External DMA enabled +input send_zero_length; + +// Register File Manager Interface +input [SSRAM_HADR + 2:0] adr; // Byte Address +input [13:0] size; // Size in bytes +output [10:0] sizu_c; // Up and Down counting size registers, used to update + +// Memory Arb interface +output [SSRAM_HADR:0] madr; // word address +output [31:0] mdout; +input [31:0] mdin; +output mwe; +output mreq; +input mack; + +/////////////////////////////////////////////////////////////////// +// +// Local Wires and Registers +// + +parameter [7:0] // synopsys enum state + IDLE = 8'b00000001, + WAIT_MRD = 8'b00000010, + MEM_WR = 8'b00000100, + MEM_WR1 = 8'b00001000, + MEM_WR2 = 8'b00010000, + MEM_RD1 = 8'b00100000, + MEM_RD2 = 8'b01000000, + MEM_RD3 = 8'b10000000; + +reg [7:0] /* synopsys enum state */ state, next_state; +// synopsys state_vector state + +reg tx_dma_en_r, rx_dma_en_r; + +reg [SSRAM_HADR:0] adr_cw; // Internal word address counter +reg [2:0] adr_cb; // Internal byte address counter +reg [SSRAM_HADR:0] adrw_next; // next address +reg [SSRAM_HADR:0] adrw_next1; // next address (after overrun check) +reg [SSRAM_HADR:0] last_buf_adr; // Last Buffer Address +reg [2:0] adrb_next; // next byte address +reg [13:0] sizd_c; // Internal size counter +reg [10:0] sizu_c; // Internal size counter +wire adr_incw; +wire adr_incb; +wire siz_dec; +wire siz_inc; + +reg word_done; // Indicates that a word has been + // assembled +reg mreq_d; // Memory request from State Machine +reg [31:0] dtmp_r; // Temp data assembly register +reg [31:0] dout_r; // Data output register +reg mwe_d; // Memory Write enable +reg dtmp_sel; // Selects tmp data register for pre-fetch + +reg sizd_is_zero; // Indicates when all bytes have been + // transferred +wire sizd_is_zero_d; + +reg [7:0] tx_data_st; // Data output to packet assembler +reg [31:0] rd_buf0, rd_buf1; // Mem Rd. buffers for TX +reg rd_first; // Indicates initial fill of buffers + +reg idma_done; // DMA transfer is done + +reg mack_r; +wire send_data; // Enable UTMI Transmitter +reg send_data_r; + +reg word_done_r; +reg wr_last; +reg wr_last_en; +reg wr_done; +reg wr_done_r; +reg dtmp_sel_r; +reg mwe; +reg rx_data_done_r2; +wire fill_buf0, fill_buf1; +wire adrb_is_3; + +reg rx_data_done_r; +reg rx_data_valid_r; +reg [7:0] rx_data_st_r; + +reg send_zero_length_r; + +/////////////////////////////////////////////////////////////////// +// +// Memory Arb interface +// + +// Memory Request +assign mreq = (mreq_d & !mack_r) | word_done_r; + +// Output Data +assign mdout = dout_r; + +// Memory Address +assign madr = adr_cw; + +always @(posedge clk) + mwe <= mwe_d; + +always @(posedge clk) + mack_r <= mreq & mack; + +/////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +always @(posedge clk) + rx_data_valid_r <= rx_data_valid; + +always @(posedge clk) + rx_data_st_r <= rx_data_st; + +always @(posedge clk) + rx_data_done_r <= rx_data_done; + +always @(posedge clk) + rx_data_done_r2 <= rx_data_done_r; + +// Generate one cycle pulses for tx and rx dma enable +always @(posedge clk) + tx_dma_en_r <= tx_dma_en; + +always @(posedge clk) + rx_dma_en_r <= rx_dma_en; + +always @(posedge clk) + send_zero_length_r <= send_zero_length; + +// address counter +always @(posedge clk) + if(rx_dma_en_r || tx_dma_en_r) adr_cw <= adr[SSRAM_HADR + 2:2]; + else adr_cw <= adrw_next1; + +always @(posedge clk) + last_buf_adr <= adr + { {SSRAM_HADR+2-13{1'b0}}, buf_size }; + +always @(dma_en or adrw_next or last_buf_adr) + if(adrw_next == last_buf_adr && dma_en) adrw_next1 = {SSRAM_HADR+1{1'b0}}; + else adrw_next1 = adrw_next; + +always @(adr_incw or adr_cw) + if(adr_incw) adrw_next = adr_cw + {{SSRAM_HADR{1'b0}}, 1'b1}; + else adrw_next = adr_cw; + +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) adr_cb <= 3'h0; + else + if(rx_dma_en_r || tx_dma_en_r) adr_cb <= adr[2:0]; + else adr_cb <= adrb_next; + +always @(adr_incb or adr_cb) + if(adr_incb) adrb_next = adr_cb + 3'h1; + else adrb_next = adr_cb; + +assign adr_incb = rx_data_valid_r | rd_next; +assign adr_incw = !dtmp_sel_r & mack_r; + +// Size Counter (counting backward from input size) +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) sizd_c <= 14'h3fff; + else + if(tx_dma_en || tx_dma_en_r) sizd_c <= size; + else + if(siz_dec) sizd_c <= sizd_c - 14'h1; + +assign siz_dec = (rd_first & mack_r) | (rd_next & (sizd_c != 14'h0)); + +assign sizd_is_zero_d = sizd_c == 14'h0; + +always @(posedge clk) + sizd_is_zero <= sizd_is_zero_d; + +// Size Counter (counting up from zero) +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) sizu_c <= 11'h0; + else + // Do I need to add "abort" in the next line ??? + if(rx_dma_en_r) sizu_c <= 11'h0; + else + if(siz_inc) sizu_c <= sizu_c + 11'h1; + +assign siz_inc = rx_data_valid_r; + +// DMA Done Indicator +always @(posedge clk) + idma_done <= (rx_data_done_r | sizd_is_zero_d); // & !tx_dma_en; + +/////////////////////////////////////////////////////////////////// +// +// RX Logic +// + +always @(posedge clk) + dtmp_sel_r <= dtmp_sel; + +// Memory data input +always @(posedge clk) + if(dtmp_sel_r) dtmp_r <= mdin; + else + if(rx_data_valid_r) + begin + if(adr_cb[1:0] == 2'h0) dtmp_r[07:00] <= rx_data_st_r; + if(adr_cb[1:0] == 2'h1) dtmp_r[15:08] <= rx_data_st_r; + if(adr_cb[1:0] == 2'h2) dtmp_r[23:16] <= rx_data_st_r; + if(adr_cb[1:0] == 2'h3) dtmp_r[31:24] <= rx_data_st_r; + end + +always @(posedge clk) + word_done <= ((adr_cb[1:0] == 2'h3) & rx_data_valid_r) | wr_last; + +always @(posedge clk) + word_done_r <= word_done & !word_done_r; + +// Store output data and address when we got a word +always @(posedge clk) + if(word_done) dout_r <= dtmp_r; + +always @(posedge clk) + wr_last <= (adr_cb[1:0] != 2'h0) & !rx_data_valid_r & wr_last_en; + +always @(posedge clk) + wr_done_r <= rx_data_done_r; + +always @(posedge clk) + wr_done <= wr_done_r; + +/////////////////////////////////////////////////////////////////// +// +// TX Logic +// + +// Fill TX Buffers +always @(posedge clk) + if(fill_buf0) rd_buf0 <= mdin; + +always @(posedge clk) + if(fill_buf1) rd_buf1 <= mdin; + +always @(adrb_next or rd_buf0 or rd_buf1) + case(adrb_next[2:0]) // synopsys full_case parallel_case + 3'h0: tx_data_st = rd_buf0[07:00]; + 3'h1: tx_data_st = rd_buf0[15:08]; + 3'h2: tx_data_st = rd_buf0[23:16]; + 3'h3: tx_data_st = rd_buf0[31:24]; + 3'h4: tx_data_st = rd_buf1[07:00]; + 3'h5: tx_data_st = rd_buf1[15:08]; + 3'h6: tx_data_st = rd_buf1[23:16]; + 3'h7: tx_data_st = rd_buf1[31:24]; + endcase + +assign fill_buf0 = !adr_cw[0] & mack_r; +assign fill_buf1 = adr_cw[0] & mack_r; + +assign adrb_is_3 = adr_cb[1:0] == 2'h3; + +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) send_data_r <= 1'b0; + else + if(rd_first) send_data_r <= 1'b1; + else + if(((sizd_c==14'h1) && rd_next) || sizd_is_zero_d) send_data_r <= 1'b0; + +assign send_data = send_data_r | send_zero_length_r; + +/////////////////////////////////////////////////////////////////// +// +// IDMA Load/Store State Machine +// + +// store incoming data to memory until rx_data done +// First pre-fetch data from memory, so that bytes can be stuffed properly + +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) state <= IDLE; + else state <= next_state; + +always @(state or mack_r or abort or rx_dma_en_r or tx_dma_en_r or + sizd_is_zero or wr_last or wr_done or rx_data_done_r2 or + rd_next or adrb_is_3 or send_zero_length_r) + begin + next_state = state; // Default do not change state + mreq_d = 1'b0; + mwe_d = 1'b0; + rd_first = 1'b0; + dtmp_sel = 1'b0; + wr_last_en = 1'b0; + + case(state) // synopsys full_case parallel_case + IDLE: + begin + +// synopsys translate_off +`ifdef USBF_VERBOSE_DEBUG +$display("IDMA: Entered IDLE state (%t)", $time); +`endif +`ifdef USBF_DEBUG +if(rst) +begin +if(rx_dma_en_r === 1'bx) $display("ERROR: IDMA: IDLE: rx_dma_en_r is unknown. (%t)", $time); +if(tx_dma_en_r === 1'bx) $display("ERROR: IDMA: IDLE: tx_dma_en_r is unknown. (%t)", $time); +if(abort === 1'bx) $display("ERROR: IDMA: IDLE: abort is unknown. (%t)", $time); +end +`endif +// synopsys translate_on + + if(rx_dma_en_r && !abort) + begin + next_state = WAIT_MRD; + end + if(tx_dma_en_r && !abort && !send_zero_length_r) + begin + next_state = MEM_RD1; + end + end + + WAIT_MRD: // Pre-fetch a word from memory + begin + +// synopsys translate_off +`ifdef USBF_VERBOSE_DEBUG +$display("IDMA: Entered WAIT_MRD state (%t)", $time); +`endif +`ifdef USBF_DEBUG +if(abort === 1'bx) $display("ERROR: IDMA: WAIT_MRD: abort is unknown. (%t)", $time); +if(mack_r === 1'bx) $display("ERROR: IDMA: WAIT_MRD: mack_r is unknown. (%t)", $time); +`endif +// synopsys translate_on + + if(abort) next_state = IDLE; + else + if(mack_r) next_state = MEM_WR; + else + begin + dtmp_sel = 1'b1; + mreq_d = 1'b1; + end + end + + MEM_WR: + begin + +// synopsys translate_off +`ifdef USBF_VERBOSE_DEBUG +$display("IDMA: Entered MEM_WR state (%t)", $time); +`endif +`ifdef USBF_DEBUG +if(abort === 1'bx) $display("ERROR: IDMA: MEM_WR: abort is unknown. (%t)", $time); +if(rx_data_done_r2 === 1'bx) $display("ERROR: IDMA: MEM_WR: rx_data_done_r2 is unknown. (%t)", $time); +`endif +// synopsys translate_on + + mwe_d = 1'b1; + if(abort) next_state = IDLE; + else + if(rx_data_done_r2) + begin + wr_last_en = 1'b1; + next_state = MEM_WR1; + end + + end + MEM_WR1: + begin + +// synopsys translate_off +`ifdef USBF_VERBOSE_DEBUG +$display("IDMA: Entered MEM_WR1 state (%t)", $time); +`endif +`ifdef USBF_DEBUG +if(abort === 1'bx) $display("ERROR: IDMA: MEM_WR1: abort is unknown. (%t)", $time); +if(wr_last === 1'bx) $display("ERROR: IDMA: MEM_WR1: wr_last is unknown. (%t)", $time); +if(wr_done === 1'bx) $display("ERROR: IDMA: MEM_WR1: wr_done is unknown. (%t)", $time); +`endif +// synopsys translate_on + + mwe_d = 1'b1; + wr_last_en = 1'b1; + if(abort) next_state = IDLE; + else + if(wr_last) next_state = MEM_WR2; + else + if(wr_done) next_state = IDLE; + end + + MEM_WR2: + begin + +// synopsys translate_off +`ifdef USBF_VERBOSE_DEBUG +$display("IDMA: Entered MEM_WR2 state (%t)", $time); +`endif +`ifdef USBF_DEBUG +if(mack_r === 1'bx) $display("ERROR: IDMA: MEM_WR2: mack_r is unknown. (%t)", $time); +`endif +// synopsys translate_on + + mwe_d = 1'b1; + if(mack_r) next_state = IDLE; + end + + MEM_RD1: + begin + +// synopsys translate_off +`ifdef USBF_VERBOSE_DEBUG +$display("IDMA: Entered MEM_RD1 state (%t)", $time); +`endif +`ifdef USBF_DEBUG +if(abort === 1'bx) $display("ERROR: IDMA: MEM_RD1: abort is unknown. (%t)", $time); +if(mack_r === 1'bx) $display("ERROR: IDMA: MEM_RD1: mack_r is unknown. (%t)", $time); +`endif +// synopsys translate_on + + mreq_d = 1'b1; + if(mack_r) rd_first = 1'b1; + if(abort) next_state = IDLE; + else + if(mack_r) next_state = MEM_RD2; + end + MEM_RD2: + begin + +// synopsys translate_off +`ifdef USBF_VERBOSE_DEBUG +$display("IDMA: Entered MEM_RD2 state (%t)", $time); +`endif +`ifdef USBF_DEBUG +if(abort === 1'bx) $display("ERROR: IDMA: MEM_RD2: abort is unknown. (%t)", $time); +if(mack_r === 1'bx) $display("ERROR: IDMA: MEM_RD2: mack_r is unknown. (%t)", $time); +`endif +// synopsys translate_on + + mreq_d = 1'b1; + if(abort) next_state = IDLE; + else + if(mack_r) next_state = MEM_RD3; + end + MEM_RD3: + begin + +// synopsys translate_off +`ifdef USBF_VERBOSE_DEBUG +$display("IDMA: Entered MEM_RD3 state (%t)", $time); +`endif +`ifdef USBF_DEBUG +if(abort === 1'bx) $display("ERROR: IDMA: MEM_RD3: abort is unknown. (%t)", $time); +if(sizd_is_zero===1'bx) $display("ERROR: IDMA: MEM_RD3: sizd_is_zero is unknown. (%t)", $time); +if(adrb_is_3 === 1'bx) $display("ERROR: IDMA: MEM_RD3: adrb_is_3 is unknown. (%t)", $time); +if(rd_next === 1'bx) $display("ERROR: IDMA: MEM_RD3: rd_next is unknown. (%t)", $time); +`endif +// synopsys translate_on + + if(sizd_is_zero || abort) next_state = IDLE; + else + if(adrb_is_3 && rd_next) next_state = MEM_RD2; + end + endcase + + end + +endmodule + diff --git a/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_mem_arb.v b/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_mem_arb.v new file mode 100644 index 0000000..183d17e --- /dev/null +++ b/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_mem_arb.v @@ -0,0 +1,187 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Memory Buffer Arbiter //// +//// Arbitrates between the internal DMA and external bus //// +//// interface for the internal buffer memory //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/usb/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2003 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: usbf_mem_arb.v,v 1.3 2003-10-17 02:36:57 rudi Exp $ +// +// $Date: 2003-10-17 02:36:57 $ +// $Revision: 1.3 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.2 2001/11/04 12:22:45 rudi +// +// - Fixed previous fix (brocke something else ...) +// - Majore Synthesis cleanup +// +// Revision 1.1 2001/08/03 05:30:09 rudi +// +// +// 1) Reorganized directory structure +// +// Revision 1.2 2001/03/31 13:00:51 rudi +// +// - Added Core configuration +// - Added handling of OUT packets less than MAX_PL_SZ in DMA mode +// - Modified WISHBONE interface and sync logic +// - Moved SSRAM outside the core (added interface) +// - Many small bug fixes ... +// +// Revision 1.0 2001/03/07 09:17:12 rudi +// +// +// Changed all revisions to revision 1.0. This is because OpenCores CVS +// interface could not handle the original '0.1' revision .... +// +// Revision 0.1.0.1 2001/02/28 08:10:52 rudi +// Initial Release +// +// + +`include "usbf_defines.v" + +module usbf_mem_arb( phy_clk, wclk, rst, + + // SSRAM Interface + sram_adr, sram_din, sram_dout, sram_re, sram_we, + + // IDMA Memory Interface + madr, mdout, mdin, mwe, mreq, mack, + + // WISHBONE Memory Interface + wadr, wdout, wdin, wwe, wreq, wack + + ); + +parameter SSRAM_HADR = 14; + +input phy_clk, wclk, rst; + +output [SSRAM_HADR:0] sram_adr; +input [31:0] sram_din; +output [31:0] sram_dout; +output sram_re, sram_we; + +input [SSRAM_HADR:0] madr; +output [31:0] mdout; +input [31:0] mdin; +input mwe; +input mreq; +output mack; + +input [SSRAM_HADR:0] wadr; +output [31:0] wdout; +input [31:0] wdin; +input wwe; +input wreq; +output wack; + +/////////////////////////////////////////////////////////////////// +// +// Local Wires and Registers +// + +wire wsel; +reg [SSRAM_HADR:0] sram_adr; +reg [31:0] sram_dout; +reg sram_we; +wire mack; +wire mcyc; +reg wack_r; + +/////////////////////////////////////////////////////////////////// +// +// Memory Arbiter Logic +// + +// IDMA has always first priority + +// ----------------------------------------- +// Ctrl Signals + +assign wsel = (wreq | wack) & !mreq; + +// ----------------------------------------- +// SSRAM Specific +// Data Path +always @(wsel or wdin or mdin) + if(wsel) sram_dout = wdin; + else sram_dout = mdin; + +// Address Path +always @(wsel or wadr or madr) + if(wsel) sram_adr = wadr; + else sram_adr = madr; + +// Write Enable Path +always @(wsel or wwe or wreq or mwe or mcyc) + if(wsel) sram_we = wreq & wwe; + else sram_we = mwe & mcyc; + +assign sram_re = 1'b1; + +// ----------------------------------------- +// IDMA specific + +assign mdout = sram_din; + +assign mack = mreq; + +assign mcyc = mack; // Qualifier for writes + +// ----------------------------------------- +// WISHBONE specific +assign wdout = sram_din; + +assign wack = wack_r & !mreq; + +`ifdef USBF_ASYNC_RESET +always @(posedge phy_clk or negedge rst) +`else +always @(posedge phy_clk) +`endif + if(!rst) wack_r <= 1'b0; + else wack_r <= wreq & !mreq & !wack; + +endmodule + diff --git a/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_pa.v b/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_pa.v new file mode 100644 index 0000000..b37c140 --- /dev/null +++ b/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_pa.v @@ -0,0 +1,377 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Packet Assembler //// +//// Assembles Token and Data USB packets //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/usb/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2003 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: usbf_pa.v,v 1.6 2003-10-17 02:36:57 rudi Exp $ +// +// $Date: 2003-10-17 02:36:57 $ +// $Revision: 1.6 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.5 2001/11/04 12:22:45 rudi +// +// - Fixed previous fix (brocke something else ...) +// - Majore Synthesis cleanup +// +// Revision 1.4 2001/09/24 01:15:28 rudi +// +// Changed reset to be active high async. +// +// Revision 1.3 2001/09/19 14:38:57 rudi +// +// Fixed TxValid handling bug. +// +// Revision 1.2 2001/08/10 08:48:33 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// +// Revision 1.1 2001/08/03 05:30:09 rudi +// +// +// 1) Reorganized directory structure +// +// Revision 1.0 2001/03/07 09:17:12 rudi +// +// +// Changed all revisions to revision 1.0. This is because OpenCores CVS +// interface could not handle the original '0.1' revision .... +// +// Revision 0.1.0.1 2001/02/28 08:10:54 rudi +// Initial Release +// +// + +`include "usbf_defines.v" + +module usbf_pa( clk, rst, + + // UTMI TX I/F + tx_data, tx_valid, tx_valid_last, tx_ready, + tx_first, + + // Protocol Engine Interface + send_token, token_pid_sel, + send_data, data_pid_sel, + send_zero_length, + + // IDMA Interface + tx_data_st, rd_next + ); + +input clk, rst; + +// UTMI TX Interface +output [7:0] tx_data; +output tx_valid; +output tx_valid_last; +input tx_ready; +output tx_first; + +// Protocol Engine Interface +input send_token; +input [1:0] token_pid_sel; +input send_data; +input [1:0] data_pid_sel; +input send_zero_length; + +// IDMA Interface +input [7:0] tx_data_st; +output rd_next; + +/////////////////////////////////////////////////////////////////// +// +// Local Wires and Registers +// + +parameter [4:0] // synopsys enum state + IDLE = 5'b00001, + DATA = 5'b00010, + CRC1 = 5'b00100, + CRC2 = 5'b01000, + WAIT = 5'b10000; + +reg [4:0] /* synopsys enum state */ state, next_state; +// synopsys state_vector state + +reg last; +reg rd_next; + +reg [7:0] token_pid, data_pid; // PIDs from selectors +reg [7:0] tx_data_d; +reg [7:0] tx_data_data; +reg dsel; +reg tx_valid_d; +reg send_token_r; +reg [7:0] tx_spec_data; +reg crc_sel1, crc_sel2; +reg tx_first_r; +reg send_data_r; +wire crc16_clr; +reg [15:0] crc16; +wire [15:0] crc16_next; +wire [15:0] crc16_rev; +wire crc16_add; +reg send_data_r2; +reg tx_valid_r; +reg tx_valid_r1; +reg zero_length_r; +reg send_zero_length_r; + +/////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +always @(posedge clk) + send_zero_length_r <= send_zero_length; + +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) zero_length_r <= 1'b0; + else + if(last) zero_length_r <= 1'b0; + else + if(crc16_clr) zero_length_r <= send_zero_length_r; + +always @(posedge clk) + tx_valid_r1 <= tx_valid; + +always @(posedge clk) + tx_valid_r <= tx_valid_r1; + +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) send_token_r <= 1'b0; + else + if(send_token) send_token_r <= 1'b1; + else + if(tx_ready) send_token_r <= 1'b0; + +// PID Select +always @(token_pid_sel) + case(token_pid_sel) // synopsys full_case parallel_case + 2'd0: token_pid = { ~`USBF_T_PID_ACK, `USBF_T_PID_ACK}; + 2'd1: token_pid = { ~`USBF_T_PID_NACK, `USBF_T_PID_NACK}; + 2'd2: token_pid = {~`USBF_T_PID_STALL, `USBF_T_PID_STALL}; + 2'd3: token_pid = { ~`USBF_T_PID_NYET, `USBF_T_PID_NYET}; + endcase + +always @(data_pid_sel) + case(data_pid_sel) // synopsys full_case parallel_case + 2'd0: data_pid = { ~`USBF_T_PID_DATA0, `USBF_T_PID_DATA0}; + 2'd1: data_pid = { ~`USBF_T_PID_DATA1, `USBF_T_PID_DATA1}; + 2'd2: data_pid = { ~`USBF_T_PID_DATA2, `USBF_T_PID_DATA2}; + 2'd3: data_pid = { ~`USBF_T_PID_MDATA, `USBF_T_PID_MDATA}; + endcase + +// Data path Muxes + +always @(send_token or send_token_r or token_pid or tx_data_data) + if(send_token || send_token_r) tx_data_d = token_pid; + else tx_data_d = tx_data_data; + +always @(dsel or tx_data_st or tx_spec_data) + if(dsel) tx_data_data = tx_spec_data; + else tx_data_data = tx_data_st; + +always @(crc_sel1 or crc_sel2 or data_pid or crc16_rev) + if(!crc_sel1 && !crc_sel2) tx_spec_data = data_pid; + else + if(crc_sel1) tx_spec_data = crc16_rev[15:8]; // CRC 1 + else tx_spec_data = crc16_rev[7:0]; // CRC 2 + +assign tx_data = tx_data_d; + +// TX Valid assignment +assign tx_valid_last = send_token | last; +assign tx_valid = tx_valid_d; + +always @(posedge clk) + tx_first_r <= send_token | send_data; + +assign tx_first = (send_token | send_data) & ! tx_first_r; + +// CRC Logic +always @(posedge clk) + send_data_r <= send_data; + +always @(posedge clk) + send_data_r2 <= send_data_r; + +assign crc16_clr = send_data & !send_data_r; + +assign crc16_add = !zero_length_r & (send_data_r & !send_data_r2) | (rd_next & !crc_sel1); + +always @(posedge clk) + if(crc16_clr) crc16 <= 16'hffff; + else + if(crc16_add) crc16 <= crc16_next; + + +usbf_crc16 u1( + .crc_in( crc16 ), + .din( {tx_data_st[0], tx_data_st[1], + tx_data_st[2], tx_data_st[3], + tx_data_st[4], tx_data_st[5], + tx_data_st[6], tx_data_st[7]} ), + .crc_out( crc16_next ) ); + +assign crc16_rev[15] = ~crc16[8]; +assign crc16_rev[14] = ~crc16[9]; +assign crc16_rev[13] = ~crc16[10]; +assign crc16_rev[12] = ~crc16[11]; +assign crc16_rev[11] = ~crc16[12]; +assign crc16_rev[10] = ~crc16[13]; +assign crc16_rev[9] = ~crc16[14]; +assign crc16_rev[8] = ~crc16[15]; +assign crc16_rev[7] = ~crc16[0]; +assign crc16_rev[6] = ~crc16[1]; +assign crc16_rev[5] = ~crc16[2]; +assign crc16_rev[4] = ~crc16[3]; +assign crc16_rev[3] = ~crc16[4]; +assign crc16_rev[2] = ~crc16[5]; +assign crc16_rev[1] = ~crc16[6]; +assign crc16_rev[0] = ~crc16[7]; + +/////////////////////////////////////////////////////////////////// +// +// Transmit/Encode state machine +// + +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) state <= IDLE; + else state <= next_state; + +always @(state or send_data or tx_ready or tx_valid_r or send_zero_length_r) + begin + next_state = state; // Default don't change current state + tx_valid_d = 1'b0; + dsel = 1'b0; + rd_next = 1'b0; + last = 1'b0; + crc_sel1 = 1'b0; + crc_sel2 = 1'b0; + case(state) // synopsys full_case parallel_case + IDLE: + begin + if(send_zero_length_r && send_data) + begin + tx_valid_d = 1'b1; + next_state = WAIT; + dsel = 1'b1; + end + else + if(send_data) // Send DATA packet + begin + tx_valid_d = 1'b1; + next_state = DATA; + dsel = 1'b1; + end + end + DATA: + begin + if(tx_ready && tx_valid_r) + rd_next = 1'b1; + + tx_valid_d = 1'b1; + if(!send_data && tx_ready && tx_valid_r) + begin + dsel = 1'b1; + crc_sel1 = 1'b1; + next_state = CRC1; + end + end + WAIT: // In case of early tx_ready ... + begin + crc_sel1 = 1'b1; + dsel = 1'b1; + tx_valid_d = 1'b1; + next_state = CRC1; + end + CRC1: + begin + dsel = 1'b1; + tx_valid_d = 1'b1; + if(tx_ready) + begin + last = 1'b1; + crc_sel2 = 1'b1; + next_state = CRC2; + end + else + begin + tx_valid_d = 1'b1; + crc_sel1 = 1'b1; + end + + end + CRC2: + begin + dsel = 1'b1; + crc_sel2 = 1'b1; + if(tx_ready) + begin + next_state = IDLE; + end + else + begin + last = 1'b1; + end + + end + endcase + end + +endmodule + diff --git a/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_pd.v b/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_pd.v new file mode 100644 index 0000000..ebdff09 --- /dev/null +++ b/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_pd.v @@ -0,0 +1,428 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Packet Disassembler //// +//// Disassembles Token and Data USB packets //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/usb/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2003 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: usbf_pd.v,v 1.7 2003-10-17 02:36:57 rudi Exp $ +// +// $Date: 2003-10-17 02:36:57 $ +// $Revision: 1.7 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.5 2001/11/03 03:26:22 rudi +// +// - Fixed several interrupt and error condition reporting bugs +// +// Revision 1.4 2001/09/24 01:15:28 rudi +// +// Changed reset to be active high async. +// +// Revision 1.3 2001/09/10 15:54:20 rudi +// +// Fixed crc5 checking. +// +// Revision 1.2 2001/08/10 08:48:33 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// +// Revision 1.1 2001/08/03 05:30:09 rudi +// +// +// 1) Reorganized directory structure +// +// Revision 1.2 2001/03/31 13:00:51 rudi +// +// - Added Core configuration +// - Added handling of OUT packets less than MAX_PL_SZ in DMA mode +// - Modified WISHBONE interface and sync logic +// - Moved SSRAM outside the core (added interface) +// - Many small bug fixes ... +// +// Revision 1.0 2001/03/07 09:17:12 rudi +// +// +// Changed all revisions to revision 1.0. This is because OpenCores CVS +// interface could not handle the original '0.1' revision .... +// +// Revision 0.1.0.1 2001/02/28 08:10:59 rudi +// Initial Release +// +// + +`include "usbf_defines.v" + +module usbf_pd( clk, rst, + + // UTMI RX I/F + rx_data, rx_valid, rx_active, rx_err, + + // PID Information + pid_OUT, pid_IN, pid_SOF, pid_SETUP, + pid_DATA0, pid_DATA1, pid_DATA2, pid_MDATA, + pid_ACK, pid_NACK, pid_STALL, pid_NYET, + pid_PRE, pid_ERR, pid_SPLIT, pid_PING, + pid_cks_err, + + // Token Information + token_fadr, token_endp, token_valid, crc5_err, + frame_no, + + // Receive Data Output + rx_data_st, rx_data_valid, rx_data_done, crc16_err, + + // Misc. + seq_err + ); + +input clk, rst; + + //UTMI RX Interface +input [7:0] rx_data; +input rx_valid, rx_active, rx_err; + + // Decoded PIDs (used when token_valid is asserted) +output pid_OUT, pid_IN, pid_SOF, pid_SETUP; +output pid_DATA0, pid_DATA1, pid_DATA2, pid_MDATA; +output pid_ACK, pid_NACK, pid_STALL, pid_NYET; +output pid_PRE, pid_ERR, pid_SPLIT, pid_PING; +output pid_cks_err; // Indicates a PID checksum error + + +output [6:0] token_fadr; // Function address from token +output [3:0] token_endp; // Endpoint number from token +output token_valid; // Token is valid +output crc5_err; // Token crc5 error +output [10:0] frame_no; // Frame number for SOF tokens + +output [7:0] rx_data_st; // Data to memory store unit +output rx_data_valid; // Data on rx_data_st is valid +output rx_data_done; // Indicates end of a transfer +output crc16_err; // Data packet CRC 16 error + +output seq_err; // State Machine Sequence Error + +/////////////////////////////////////////////////////////////////// +// +// Local Wires and Registers +// + +parameter [3:0] // synopsys enum state + IDLE = 4'b0001, + ACTIVE = 4'b0010, + TOKEN = 4'b0100, + DATA = 4'b1000; + +reg [3:0] /* synopsys enum state */ state, next_state; +// synopsys state_vector state + +reg [7:0] pid; // Packet PDI +reg pid_le_sm; // PID Load enable from State Machine +wire pid_ld_en; // Enable loading of PID (all conditions) +wire pid_cks_err; // Indicates a pid checksum err + + // Decoded PID values +wire pid_OUT, pid_IN, pid_SOF, pid_SETUP; +wire pid_DATA0, pid_DATA1, pid_DATA2, pid_MDATA; +wire pid_ACK, pid_NACK, pid_STALL, pid_NYET; +wire pid_PRE, pid_ERR, pid_SPLIT, pid_PING, pid_RES; +wire pid_TOKEN; // All TOKEN packet that we recognize +wire pid_DATA; // All DATA packets that we recognize + +reg [7:0] token0, token1; // Token Registers +reg token_le_1, token_le_2; // Latch enables for token storage registers +wire [4:0] token_crc5; + +reg [7:0] d0, d1, d2; // Data path delay line (used to filter out crcs) +reg data_valid_d; // Data Valid output from State Machine +reg data_done; // Data cycle complete output from State Machine +reg data_valid0; // Data valid delay line +reg rxv1; +reg rxv2; + +reg seq_err; // State machine sequence error + +reg got_pid_ack; + +reg token_valid_r1; +reg token_valid_str1; + +reg rx_active_r; + +wire [4:0] crc5_out; +wire [4:0] crc5_out2; +wire crc16_clr; +reg [15:0] crc16_sum; +wire [15:0] crc16_out; + +/////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +// PID Decoding Logic +assign pid_ld_en = pid_le_sm & rx_active & rx_valid; + +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) pid <= 8'hf0; + else + if(pid_ld_en) pid <= rx_data; + +assign pid_cks_err = (pid[3:0] != ~pid[7:4]); + +assign pid_OUT = pid[3:0] == `USBF_T_PID_OUT; +assign pid_IN = pid[3:0] == `USBF_T_PID_IN; +assign pid_SOF = pid[3:0] == `USBF_T_PID_SOF; +assign pid_SETUP = pid[3:0] == `USBF_T_PID_SETUP; +assign pid_DATA0 = pid[3:0] == `USBF_T_PID_DATA0; +assign pid_DATA1 = pid[3:0] == `USBF_T_PID_DATA1; +assign pid_DATA2 = pid[3:0] == `USBF_T_PID_DATA2; +assign pid_MDATA = pid[3:0] == `USBF_T_PID_MDATA; +assign pid_ACK = pid[3:0] == `USBF_T_PID_ACK; +assign pid_NACK = pid[3:0] == `USBF_T_PID_NACK; +assign pid_STALL = pid[3:0] == `USBF_T_PID_STALL; +assign pid_NYET = pid[3:0] == `USBF_T_PID_NYET; +assign pid_PRE = pid[3:0] == `USBF_T_PID_PRE; +assign pid_ERR = pid[3:0] == `USBF_T_PID_ERR; +assign pid_SPLIT = pid[3:0] == `USBF_T_PID_SPLIT; +assign pid_PING = pid[3:0] == `USBF_T_PID_PING; +assign pid_RES = pid[3:0] == `USBF_T_PID_RES; + +assign pid_TOKEN = pid_OUT | pid_IN | pid_SOF | pid_SETUP | pid_PING; +assign pid_DATA = pid_DATA0 | pid_DATA1 | pid_DATA2 | pid_MDATA; + +// Token Decoding LOGIC +always @(posedge clk) + if(token_le_1) token0 <= rx_data; + +always @(posedge clk) + if(token_le_2) token1 <= rx_data; + +always @(posedge clk) + token_valid_r1 <= token_le_2; + +always @(posedge clk) + token_valid_str1 <= token_valid_r1 | got_pid_ack; + +assign token_valid = token_valid_str1; + +// CRC 5 should perform the check in one cycle (flow through logic) +// 11 bits and crc5 input, 1 bit output +assign crc5_err = token_valid & (crc5_out2 != token_crc5); + +usbf_crc5 u0( + .crc_in( 5'h1f ), + .din( { token_fadr[0], + token_fadr[1], + token_fadr[2], + token_fadr[3], + token_fadr[4], + token_fadr[5], + token_fadr[6], + token_endp[0], + token_endp[1], + token_endp[2], + token_endp[3] } ), + .crc_out( crc5_out ) ); + +// Invert and reverse result bits +assign crc5_out2 = ~{crc5_out[0], crc5_out[1], crc5_out[2], crc5_out[3], + crc5_out[4]}; + +assign frame_no = { token1[2:0], token0}; +assign token_fadr = token0[6:0]; +assign token_endp = {token1[2:0], token0[7]}; +assign token_crc5 = token1[7:3]; + +// Data receiving logic +// build a delay line and stop when we are about to get crc +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) rxv1 <= 1'b0; + else + if(data_valid_d) rxv1 <= 1'b1; + else + if(data_done) rxv1 <= 1'b0; + +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) rxv2 <= 1'b0; + else + if(rxv1 && data_valid_d)rxv2 <= 1'b1; + else + if(data_done) rxv2 <= 1'b0; + +always @(posedge clk) + data_valid0 <= rxv2 & data_valid_d; + +always @(posedge clk) + begin + if(data_valid_d) d0 <= rx_data; + if(data_valid_d) d1 <= d0; + if(data_valid_d) d2 <= d1; + end + +assign rx_data_st = d2; +assign rx_data_valid = data_valid0; +assign rx_data_done = data_done; + +// crc16 accumulates rx_data as long as data_valid_d is asserted. +// when data_done is asserted, crc16 reports status, and resets itself +// next cycle. +always @(posedge clk) + rx_active_r <= rx_active; + +assign crc16_clr = rx_active & !rx_active_r; + +always @(posedge clk) + if(crc16_clr) crc16_sum <= 16'hffff; + else + if(data_valid_d) crc16_sum <= crc16_out; + +usbf_crc16 u1( + .crc_in( crc16_sum ), + .din( {rx_data[0], rx_data[1], rx_data[2], rx_data[3], + rx_data[4], rx_data[5], rx_data[6], rx_data[7]} ), + .crc_out( crc16_out ) ); + +// Verify against polynomial +assign crc16_err = data_done & (crc16_sum != 16'h800d); + +/////////////////////////////////////////////////////////////////// +// +// Receive/Decode State machine +// + +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) state <= IDLE; + else state <= next_state; + +always @(state or rx_valid or rx_active or rx_err or pid_ACK or pid_TOKEN + or pid_DATA) + begin + next_state = state; // Default don't change current state + pid_le_sm = 1'b0; + token_le_1 = 1'b0; + token_le_2 = 1'b0; + data_valid_d = 1'b0; + data_done = 1'b0; + seq_err = 1'b0; + got_pid_ack = 1'b0; + case(state) // synopsys full_case parallel_case + IDLE: + begin + pid_le_sm = 1'b1; + if(rx_valid && rx_active) next_state = ACTIVE; + end + ACTIVE: + begin + // Received a ACK from Host + if(pid_ACK && !rx_err) + begin + got_pid_ack = 1'b1; + if(!rx_active) next_state = IDLE; + end + else + // Receiving a TOKEN + if(pid_TOKEN && rx_valid && rx_active && !rx_err) + begin + token_le_1 = 1'b1; + next_state = TOKEN; + end + else + // Receiving DATA + if(pid_DATA && rx_valid && rx_active && !rx_err) + begin + data_valid_d = 1'b1; + next_state = DATA; + end + else + if( !rx_active || rx_err || + (rx_valid && !(pid_TOKEN || pid_DATA)) ) + begin + seq_err = !rx_err; + if(!rx_active) next_state = IDLE; + end + end + TOKEN: + begin + if(rx_valid && rx_active && !rx_err) + begin + token_le_2 = 1'b1; + next_state = IDLE; + end + else + if(!rx_active || rx_err) + begin + seq_err = !rx_err; + if(!rx_active) next_state = IDLE; + end + end + DATA: + begin + if(rx_valid && rx_active && !rx_err) data_valid_d = 1'b1; + if(!rx_active || rx_err) + begin + data_done = 1'b1; + if(!rx_active) next_state = IDLE; + end + end + + endcase + end + +endmodule + diff --git a/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_pe.v b/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_pe.v new file mode 100644 index 0000000..42ad191 --- /dev/null +++ b/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_pe.v @@ -0,0 +1,1086 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Protocol Engine //// +//// Performs automatic protocol functions //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/usb/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2003 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: usbf_pe.v,v 1.8 2003-10-17 02:36:57 rudi Exp $ +// +// $Date: 2003-10-17 02:36:57 $ +// $Revision: 1.8 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.7 2001/11/04 12:22:45 rudi +// +// - Fixed previous fix (brocke something else ...) +// - Majore Synthesis cleanup +// +// Revision 1.6 2001/11/03 03:26:22 rudi +// +// - Fixed several interrupt and error condition reporting bugs +// +// Revision 1.5 2001/09/24 01:15:28 rudi +// +// Changed reset to be active high async. +// +// Revision 1.4 2001/09/23 08:39:33 rudi +// +// Renamed DEBUG and VERBOSE_DEBUG to USBF_DEBUG and USBF_VERBOSE_DEBUG ... +// +// Revision 1.3 2001/09/13 13:14:02 rudi +// +// Fixed a problem that would sometimes prevent the core to come out of +// reset and immediately be operational ... +// +// Revision 1.2 2001/08/10 08:48:33 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// +// Revision 1.1 2001/08/03 05:30:09 rudi +// +// +// 1) Reorganized directory structure +// +// Revision 1.2 2001/03/31 13:00:51 rudi +// +// - Added Core configuration +// - Added handling of OUT packets less than MAX_PL_SZ in DMA mode +// - Modified WISHBONE interface and sync logic +// - Moved SSRAM outside the core (added interface) +// - Many small bug fixes ... +// +// Revision 1.0 2001/03/07 09:17:12 rudi +// +// +// Changed all revisions to revision 1.0. This is because OpenCores CVS +// interface could not handle the original '0.1' revision .... +// +// Revision 0.2 2001/03/07 09:08:13 rudi +// +// Added USB control signaling (Line Status) block. Fixed some minor +// typos, added resume bit and signal. +// +// Revision 0.1.0.1 2001/02/28 08:11:07 rudi +// Initial Release +// +// + +`include "usbf_defines.v" + +module usbf_pe( clk, rst, + + // UTMI Interfaces + tx_valid, rx_active, + + // PID Information + pid_OUT, pid_IN, pid_SOF, pid_SETUP, + pid_DATA0, pid_DATA1, pid_DATA2, pid_MDATA, + pid_ACK, pid_NACK, pid_STALL, pid_NYET, + pid_PRE, pid_ERR, pid_SPLIT, pid_PING, + + // Speed Mode + mode_hs, + + // Token Information + token_valid, crc5_err, + + // Receive Data Output + rx_data_valid, rx_data_done, crc16_err, + + // Packet Assembler Interface + send_token, token_pid_sel, + data_pid_sel, send_zero_length, + + // IDMA Interface + rx_dma_en, tx_dma_en, + abort, idma_done, + adr, size, buf_size, + sizu_c, dma_en, + + // Register File Interface + fsel, idin, + dma_in_buf_sz1, dma_out_buf_avail, + ep_sel, match, nse_err, + buf0_rl, buf0_set, buf1_set, + uc_bsel_set, uc_dpd_set, + + int_buf1_set, int_buf0_set, int_upid_set, + int_crc16_set, int_to_set, int_seqerr_set, + out_to_small, + + csr, buf0, buf1 + + ); + +parameter SSRAM_HADR = 14; + +input clk, rst; +input tx_valid, rx_active; + +// Packet Disassembler Interface + // Decoded PIDs (used when token_valid is asserted) +input pid_OUT, pid_IN, pid_SOF, pid_SETUP; +input pid_DATA0, pid_DATA1, pid_DATA2, pid_MDATA; +input pid_ACK, pid_NACK, pid_STALL, pid_NYET; +input pid_PRE, pid_ERR, pid_SPLIT, pid_PING; + +input mode_hs; +input token_valid; // Token is valid +input crc5_err; // Token crc5 error + +input rx_data_valid; // Data on rx_data_st is valid +input rx_data_done; // Indicates end of a transfer +input crc16_err; // Data packet CRC 16 error + +// Packet Assembler Interface +output send_token; +output [1:0] token_pid_sel; +output [1:0] data_pid_sel; +output send_zero_length; + +// IDMA Interface +output rx_dma_en; // Allows the data to be stored +output tx_dma_en; // Allows for data to be retrieved +output abort; // Abort Transfer (time_out, crc_err or rx_error) +input idma_done; // DMA is done indicator +output [SSRAM_HADR + 2:0] adr; // Byte Address +output [13:0] size; // Size in bytes +output [13:0] buf_size; // Actual buffer size +input [10:0] sizu_c; // Up and Down counting size registers, used to update +output dma_en; // USB external DMA mode enabled + +// Register File interface +input fsel; // This function is selected +output [31:0] idin; // Data Output +input [3:0] ep_sel; // Endpoint Number Input +input match; // Endpoint Matched +output nse_err; // no such endpoint error +input dma_in_buf_sz1, dma_out_buf_avail; + +output buf0_rl; // Reload Buf 0 with original values +output buf0_set; // Write to buf 0 +output buf1_set; // Write to buf 1 +output uc_bsel_set; // Write to the uc_bsel field +output uc_dpd_set; // Write to the uc_dpd field +output int_buf1_set; // Set buf1 full/empty interrupt +output int_buf0_set; // Set buf0 full/empty interrupt +output int_upid_set; // Set unsupported PID interrupt +output int_crc16_set; // Set CRC16 error interrupt +output int_to_set; // Set time out interrupt +output int_seqerr_set; // Set PID sequence error interrupt +output out_to_small; // OUT packet was to small for DMA operation + +input [31:0] csr; // Internal CSR Output +input [31:0] buf0; // Internal Buf 0 Output +input [31:0] buf1; // Internal Buf 1 Output + + + +/////////////////////////////////////////////////////////////////// +// +// Local Wires and Registers +// + +// tx token decoding +parameter ACK = 0, + NACK = 1, + STALL = 2, + NYET = 3; + +// State decoding +parameter [9:0] // synopsys enum state + IDLE = 10'b000000_0001, + TOKEN = 10'b000000_0010, + IN = 10'b000000_0100, + IN2 = 10'b000000_1000, + OUT = 10'b000001_0000, + OUT2A = 10'b000010_0000, + OUT2B = 10'b000100_0000, + UPDATEW = 10'b001000_0000, + UPDATE = 10'b010000_0000, + UPDATE2 = 10'b100000_0000; + +reg [1:0] token_pid_sel; +reg [1:0] token_pid_sel_d; +reg send_token; +reg send_token_d; +reg rx_dma_en, tx_dma_en; +reg int_seqerr_set_d; +reg int_seqerr_set; +reg int_upid_set; + +reg match_r; + +// Endpoint Decoding +wire IN_ep, OUT_ep, CTRL_ep; // Endpoint Types +wire txfr_iso, txfr_bulk; // Transfer Types +wire ep_disabled, ep_stall; // Endpoint forced conditions + +wire lrg_ok, sml_ok; // Packet size acceptance +wire [1:0] tr_fr; // Number of transfers per micro-frame +wire [10:0] max_pl_sz; // Max payload size + +wire [1:0] uc_dpd, uc_bsel; + +// Buffer checks +wire buf_sel; +reg buf0_na, buf1_na; +wire [SSRAM_HADR + 2:0] buf0_adr, buf1_adr; +wire [13:0] buf0_sz, buf1_sz; +reg [9:0] /* synopsys enum state */ state, next_state; +// synopsys state_vector state + +// PID next and current decoders +reg [1:0] next_dpid; +reg [1:0] this_dpid; +reg pid_seq_err; +wire [1:0] tr_fr_d; + +wire [13:0] size_next; +wire buf_smaller; + +reg [SSRAM_HADR + 2:0] adr; +reg [13:0] new_size; +reg [13:0] new_sizeb; +reg buffer_full; +reg buffer_empty; +wire [SSRAM_HADR + 2:0] new_adr; +reg buffer_done; + +reg no_bufs0, no_bufs1; +wire no_bufs; + +// After sending Data in response to an IN token from host, the +// host must reply with an ack. The host has XXXnS to reply. +// "rx_ack_to" indicates when this time has expired. +// rx_ack_to_clr, clears the timer +reg rx_ack_to_clr; +reg rx_ack_to_clr_d; +reg rx_ack_to; +reg [7:0] rx_ack_to_cnt; + +// After sending a OUT token the host must send a data packet. +// The host has XX nS to send the packet. "tx_data_to" indicates +// when this time has expired. +// tx_data_to_clr, clears the timer +wire tx_data_to_clr; +reg tx_data_to; +reg [7:0] tx_data_to_cnt; + +wire [7:0] rx_ack_to_val, tx_data_to_val; + +reg int_set_en; + +wire [1:0] next_bsel; +reg buf_set_d; +reg uc_stat_set_d; +reg [31:0] idin; +reg buf0_set, buf1_set; +reg uc_bsel_set; +reg uc_dpd_set; +reg buf0_rl_d; +reg buf0_rl; +wire no_buf0_dma; +reg buf0_st_max; +reg buf1_st_max; + +reg [SSRAM_HADR + 2:0] adr_r; +reg [13:0] size_next_r; + +reg in_token; +reg out_token; +reg setup_token; + +wire in_op, out_op; // Indicate a IN or OUT operation +reg to_small; // Indicates a "to small packer" error +reg to_large; // Indicates a "to large packer" error + +reg buffer_overflow; +reg [1:0] allow_pid; + +reg nse_err; +reg out_to_small, out_to_small_r; +reg abort; + +reg buf0_not_aloc, buf1_not_aloc; + +reg send_zero_length; + +/////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +// Endpoint/CSR Decoding +assign IN_ep = csr[27:26]==2'b01; +assign OUT_ep = csr[27:26]==2'b10; +assign CTRL_ep = csr[27:26]==2'b00; + +assign txfr_iso = csr[25:24]==2'b01; +assign txfr_bulk = csr[25:24]==2'b10; + +assign ep_disabled = csr[23:22]==2'b01; +assign ep_stall = csr[23:22]==2'b10; + +assign lrg_ok = csr[17]; +assign sml_ok = csr[16]; +assign dma_en = csr[15] & !CTRL_ep; + +assign tr_fr = csr[12:11]; +assign max_pl_sz = csr[10:0]; + +assign uc_dpd = csr[29:28]; +assign uc_bsel = csr[31:30]; + +// Buffer decoding and allocation checks +assign buf0_adr = buf0[SSRAM_HADR + 2:0]; +assign buf1_adr = buf1[SSRAM_HADR + 2:0]; +assign buf0_sz = buf0[30:17]; +assign buf1_sz = buf1[30:17]; + +// Buffers Not Available +always @(posedge clk) + buf0_na <= buf0[31] | ( &buf0_adr ); + +always @(posedge clk) + buf1_na <= buf1[31] | ( &buf1_adr ); + +// Buffer Not Allocated +always @(posedge clk) + buf0_not_aloc <= &buf0_adr; + +always @(posedge clk) + buf1_not_aloc <= &buf1_adr; + +always @(posedge clk) + match_r <= match; + +// No Such Endpoint Indicator +always @(posedge clk) + nse_err <= token_valid & (pid_OUT | pid_IN | pid_SETUP) & !match; + +always @(posedge clk) + send_token <= send_token_d; + +always @(posedge clk) + token_pid_sel <= token_pid_sel_d; + +/////////////////////////////////////////////////////////////////// +// +// Data Pid Sequencer +// + +assign tr_fr_d = mode_hs ? tr_fr : 2'h0; + +always @(posedge clk) // tr/mf:ep/type:tr/type:last dpd + casex({tr_fr_d,csr[27:26],csr[25:24],uc_dpd}) // synopsys full_case parallel_case + 8'b0?_01_01_??: next_dpid <= 2'b00; // ISO txfr. IN, 1 tr/mf + + 8'b10_01_01_?0: next_dpid <= 2'b01; // ISO txfr. IN, 2 tr/mf + 8'b10_01_01_?1: next_dpid <= 2'b00; // ISO txfr. IN, 2 tr/mf + + 8'b11_01_01_00: next_dpid <= 2'b01; // ISO txfr. IN, 3 tr/mf + 8'b11_01_01_01: next_dpid <= 2'b10; // ISO txfr. IN, 3 tr/mf + 8'b11_01_01_10: next_dpid <= 2'b00; // ISO txfr. IN, 3 tr/mf + + 8'b0?_10_01_??: next_dpid <= 2'b00; // ISO txfr. OUT, 1 tr/mf + + 8'b10_10_01_??: // ISO txfr. OUT, 2 tr/mf + begin // Resynchronize in case of PID error + case({pid_MDATA, pid_DATA1}) // synopsys full_case parallel_case + 2'b10: next_dpid <= 2'b01; + 2'b01: next_dpid <= 2'b00; + endcase + end + + 8'b11_10_01_00: // ISO txfr. OUT, 3 tr/mf + begin // Resynchronize in case of PID error + case({pid_MDATA, pid_DATA2}) // synopsys full_case parallel_case + 2'b10: next_dpid <= 2'b01; + 2'b01: next_dpid <= 2'b00; + endcase + end + 8'b11_10_01_01: // ISO txfr. OUT, 3 tr/mf + begin // Resynchronize in case of PID error + case({pid_MDATA, pid_DATA2}) // synopsys full_case parallel_case + 2'b10: next_dpid <= 2'b10; + 2'b01: next_dpid <= 2'b00; + endcase + end + 8'b11_10_01_10: // ISO txfr. OUT, 3 tr/mf + begin // Resynchronize in case of PID error + case({pid_MDATA, pid_DATA2}) // synopsys full_case parallel_case + 2'b10: next_dpid <= 2'b01; + 2'b01: next_dpid <= 2'b00; + endcase + end + + 8'b??_01_00_?0, // IN/OUT endpoint only + 8'b??_10_00_?0: next_dpid <= 2'b01; // INT transfers + + 8'b??_01_00_?1, // IN/OUT endpoint only + 8'b??_10_00_?1: next_dpid <= 2'b00; // INT transfers + + 8'b??_01_10_?0, // IN/OUT endpoint only + 8'b??_10_10_?0: next_dpid <= 2'b01; // BULK transfers + + 8'b??_01_10_?1, // IN/OUT endpoint only + 8'b??_10_10_?1: next_dpid <= 2'b00; // BULK transfers + + 8'b??_00_??_??: // CTRL Endpoint + casex({setup_token, in_op, out_op, uc_dpd}) // synopsys full_case parallel_case + 5'b1_??_??: next_dpid <= 2'b11; // SETUP operation + 5'b0_10_0?: next_dpid <= 2'b11; // IN operation + 5'b0_10_1?: next_dpid <= 2'b01; // IN operation + 5'b0_01_?0: next_dpid <= 2'b11; // OUT operation + 5'b0_01_?1: next_dpid <= 2'b10; // OUT operation + endcase + + endcase + +// Current PID decoder + +// Allow any PID for ISO. transfers when mode full speed or tr_fr is zero +always @(pid_DATA0 or pid_DATA1 or pid_DATA2 or pid_MDATA) + case({pid_DATA0, pid_DATA1, pid_DATA2, pid_MDATA} ) // synopsys full_case parallel_case + 4'b1000: allow_pid = 2'b00; + 4'b0100: allow_pid = 2'b01; + 4'b0010: allow_pid = 2'b10; + 4'b0001: allow_pid = 2'b11; + endcase + +always @(posedge clk) // tf/mf:ep/type:tr/type:last dpd + casex({tr_fr_d,csr[27:26],csr[25:24],uc_dpd}) // synopsys full_case parallel_case + 8'b0?_01_01_??: this_dpid <= 2'b00; // ISO txfr. IN, 1 tr/mf + + 8'b10_01_01_?0: this_dpid <= 2'b01; // ISO txfr. IN, 2 tr/mf + 8'b10_01_01_?1: this_dpid <= 2'b00; // ISO txfr. IN, 2 tr/mf + + 8'b11_01_01_00: this_dpid <= 2'b10; // ISO txfr. IN, 3 tr/mf + 8'b11_01_01_01: this_dpid <= 2'b01; // ISO txfr. IN, 3 tr/mf + 8'b11_01_01_10: this_dpid <= 2'b00; // ISO txfr. IN, 3 tr/mf + + 8'b00_10_01_??: this_dpid <= allow_pid; // ISO txfr. OUT, 0 tr/mf + 8'b01_10_01_??: this_dpid <= 2'b00; // ISO txfr. OUT, 1 tr/mf + + 8'b10_10_01_?0: this_dpid <= 2'b11; // ISO txfr. OUT, 2 tr/mf + 8'b10_10_01_?1: this_dpid <= 2'b01; // ISO txfr. OUT, 2 tr/mf + + 8'b11_10_01_00: this_dpid <= 2'b11; // ISO txfr. OUT, 3 tr/mf + 8'b11_10_01_01: this_dpid <= 2'b11; // ISO txfr. OUT, 3 tr/mf + 8'b11_10_01_10: this_dpid <= 2'b10; // ISO txfr. OUT, 3 tr/mf + + 8'b??_01_00_?0, // IN/OUT endpoint only + 8'b??_10_00_?0: this_dpid <= 2'b00; // INT transfers + 8'b??_01_00_?1, // IN/OUT endpoint only + 8'b??_10_00_?1: this_dpid <= 2'b01; // INT transfers + + 8'b??_01_10_?0, // IN/OUT endpoint only + 8'b??_10_10_?0: this_dpid <= 2'b00; // BULK transfers + 8'b??_01_10_?1, // IN/OUT endpoint only + 8'b??_10_10_?1: this_dpid <= 2'b01; // BULK transfers + + 8'b??_00_??_??: // CTRL Endpoint + casex({setup_token,in_op, out_op, uc_dpd}) // synopsys full_case parallel_case + 5'b1_??_??: this_dpid <= 2'b00; // SETUP operation + 5'b0_10_0?: this_dpid <= 2'b00; // IN operation + 5'b0_10_1?: this_dpid <= 2'b01; // IN operation + 5'b0_01_?0: this_dpid <= 2'b00; // OUT operation + 5'b0_01_?1: this_dpid <= 2'b01; // OUT operation + endcase + endcase + +// Assign PID for outgoing packets +assign data_pid_sel = this_dpid; + +// Verify PID for incoming data packets +always @(posedge clk) + pid_seq_err <= !( (this_dpid==2'b00 & pid_DATA0) | + (this_dpid==2'b01 & pid_DATA1) | + (this_dpid==2'b10 & pid_DATA2) | + (this_dpid==2'b11 & pid_MDATA) ); + +/////////////////////////////////////////////////////////////////// +// +// IDMA Setup & src/dst buffer select +// + +// For Control endpoints things are different: +// buffer0 is used for OUT (incoming) data packets +// buffer1 is used for IN (outgoing) data packets + +// Keep track of last token for control endpoints +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) in_token <= 1'b0; + else + if(pid_IN) in_token <= 1'b1; + else + if(pid_OUT || pid_SETUP) in_token <= 1'b0; + +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) out_token <= 1'b0; + else + if(pid_OUT || pid_SETUP) out_token <= 1'b1; + else + if(pid_IN) out_token <= 1'b0; + +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) setup_token <= 1'b0; + else + if(pid_SETUP) setup_token <= 1'b1; + else + if(pid_OUT || pid_IN) setup_token <= 1'b0; + +// Indicates if we are performing an IN operation +assign in_op = IN_ep | (CTRL_ep & in_token); + +// Indicates if we are performing an OUT operation +assign out_op = OUT_ep | (CTRL_ep & out_token); + +// Select buffer: buf_sel==0 buffer0; buf_sel==1 buffer1 +assign buf_sel = dma_en ? 1'b0 : CTRL_ep ? in_token : ((uc_bsel[0] | buf0_na) & !buf1_na); + +// Select Address for IDMA +always @(posedge clk) + adr <= buf_sel ? buf1_adr : buf0_adr; + +// Size from Buffer +assign buf_size = buf_sel ? buf1_sz : buf0_sz; + +// Determine which is smaller: buffer or max_pl_sz +assign buf_smaller = buf_size < {3'h0, max_pl_sz}; + +// Determine actual size for this transfer (for IDMA) IN endpoint only +// (OUT endpoint uses sizeu_c from IDMA) +assign size_next = buf_smaller ? buf_size : max_pl_sz; +assign size = size_next; // "size" is an output for IDMA + +// Buffer Full (only for OUT endpoints) +// Indicates that there is not enough space in the buffer for one +// more max_pl_sz packet +always @(posedge clk) + buffer_full <= new_size < {3'h0, max_pl_sz}; + +// Buffer Empty (only for IN endpoints) +// Indicates that there are zero bytes left in the buffer +always @(posedge clk) + buffer_empty <= (new_size == 14'h0); + +// Joint buffer full/empty flag This is the "USED" flag +always @(posedge clk) + buffer_done <= in_op ? buffer_empty : buffer_full; + +// No More buffer space at all (For high speed out - issue NYET) +assign no_buf0_dma = dma_en & + ((IN_ep & !dma_in_buf_sz1) | (OUT_ep & !dma_out_buf_avail)); + +always @(posedge clk) + buf0_st_max <= (buf0_sz < {3'h0, max_pl_sz}); + +always @(posedge clk) + buf1_st_max <= (buf1_sz < {3'h0, max_pl_sz}); + +always @(posedge clk) + no_bufs0 <= buf0_na | no_buf0_dma | + (buf_sel ? buf0_st_max : (buffer_full & !dma_en)); + +always @(posedge clk) + no_bufs1 <= buf1_na | (buf_sel ? buffer_full : buf1_st_max); + +assign no_bufs = no_bufs0 & no_bufs1; + +// New Size (to be written to register file) +always @(posedge clk) + new_sizeb <= (out_op && dma_en) ? max_pl_sz : (in_op ? size_next : sizu_c); + +always @(posedge clk) + new_size <= buf_size - new_sizeb; + + +// New Buffer Address (to be written to register file) +always @(posedge clk) + adr_r <= adr; + +always @(posedge clk) + size_next_r <= size_next; + +assign new_adr = adr_r[SSRAM_HADR + 2:0] + + ((out_op && dma_en) ? {{SSRAM_HADR + 2-10{1'b0}}, max_pl_sz[10:0]} : + (in_op ? {{SSRAM_HADR + 2-13{1'b0}}, size_next_r[13:0] } : + { {SSRAM_HADR + 2-10{1'b0}}, sizu_c[10:0]})); + +// Buffer Overflow +always @(posedge clk) + buffer_overflow <= ( {3'h0, sizu_c} > buf_size) & rx_data_valid; + + +// OUT packet smaller than MAX_PL_SZ in DMA operation +always @(posedge clk) + out_to_small_r <= uc_stat_set_d & out_op & dma_en & (sizu_c != max_pl_sz); + +always @(posedge clk) + out_to_small <= out_to_small_r; + +/////////////////////////////////////////////////////////////////// +// +// Determine if packet is to small or to large +// This is used to NACK and ignore packet for OUT endpoints +// + +always @(posedge clk) + to_small <= !sml_ok & (sizu_c < max_pl_sz); + +always @(posedge clk) + to_large <= !lrg_ok & (sizu_c > max_pl_sz); + +/////////////////////////////////////////////////////////////////// +// +// Register File Update Logic +// + +assign next_bsel = dma_en ? 2'h0 : buffer_done ? uc_bsel + 2'h1 : uc_bsel; // FIX_ME + +always @(posedge clk) + idin[31:17] <= out_to_small_r ? {4'h0,sizu_c} : {buffer_done,new_size}; + +always @(posedge clk) + idin[SSRAM_HADR + 2:4] <= out_to_small_r ? buf0_adr[SSRAM_HADR + 2:4] : + new_adr[SSRAM_HADR + 2:4]; + +always @(posedge clk) + if(buf_set_d) idin[3:0] <= new_adr[3:0]; + else + if(out_to_small_r) idin[3:0] <= buf0_adr[3:0]; + else idin[3:0] <= {next_dpid, next_bsel}; + +always @(posedge clk) + buf0_set <= !buf_sel & buf_set_d; + +always @(posedge clk) + buf1_set <= buf_sel & buf_set_d; + +always @(posedge clk) + uc_bsel_set <= uc_stat_set_d; + +always @(posedge clk) + uc_dpd_set <= uc_stat_set_d; + +always @(posedge clk) + buf0_rl <= buf0_rl_d; + +// Abort signal +always @(posedge clk) + abort <= buffer_overflow | (match & (state != IDLE) ) | (match_r & to_large); + +/////////////////////////////////////////////////////////////////// +// +// TIME OUT TIMERS +// + +// After sending Data in response to an IN token from host, the +// host must reply with an ack. The host has 622nS in Full Speed +// mode and 400nS in High Speed mode to reply. +// "rx_ack_to" indicates when this time has expired. +// rx_ack_to_clr, clears the timer + +always @(posedge clk) + rx_ack_to_clr <= tx_valid | rx_ack_to_clr_d; + +always @(posedge clk) + if(rx_ack_to_clr) rx_ack_to_cnt <= 8'h0; + else rx_ack_to_cnt <= rx_ack_to_cnt + 8'h1; + +always @(posedge clk) + rx_ack_to <= (rx_ack_to_cnt == rx_ack_to_val); + +assign rx_ack_to_val = mode_hs ? `USBF_RX_ACK_TO_VAL_HS : `USBF_RX_ACK_TO_VAL_FS; + +// After sending a OUT token the host must send a data packet. +// The host has 622nS in Full Speed mode and 400nS in High Speed +// mode to send the data packet. +// "tx_data_to" indicates when this time has expired. +// "tx_data_to_clr" clears the timer + +assign tx_data_to_clr = rx_active; + +always @(posedge clk) + if(tx_data_to_clr) tx_data_to_cnt <= 8'h0; + else tx_data_to_cnt <= tx_data_to_cnt + 8'h1; + +always @(posedge clk) + tx_data_to <= (tx_data_to_cnt == tx_data_to_val); + +assign tx_data_to_val = mode_hs ? `USBF_TX_DATA_TO_VAL_HS : `USBF_TX_DATA_TO_VAL_FS; + +/////////////////////////////////////////////////////////////////// +// +// Interrupts +// +reg pid_OUT_r, pid_IN_r, pid_PING_r, pid_SETUP_r; + +assign int_buf1_set = !buf_sel & buffer_done & int_set_en & !buf1_not_aloc; +assign int_buf0_set = buf_sel & buffer_done & int_set_en & !buf0_not_aloc; + +always @(posedge clk) + pid_OUT_r <= pid_OUT; + +always @(posedge clk) + pid_IN_r <= pid_IN; + +always @(posedge clk) + pid_PING_r <= pid_PING; + +always @(posedge clk) + pid_SETUP_r <= pid_SETUP; + +always @(posedge clk) + int_upid_set <= match_r & !pid_SOF & ( + ( OUT_ep & !(pid_OUT_r | pid_PING_r)) | + ( IN_ep & !pid_IN_r) | + (CTRL_ep & !(pid_IN_r | pid_OUT_r | pid_PING_r | pid_SETUP_r)) + ); + +assign int_to_set = ((state == IN2) & rx_ack_to) | ((state == OUT) & tx_data_to); + +assign int_crc16_set = rx_data_done & crc16_err; + +always @(posedge clk) + int_seqerr_set <= int_seqerr_set_d; + +/////////////////////////////////////////////////////////////////// +// +// Main Protocol State Machine +// + +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) state <= IDLE; + else + if(match) state <= IDLE; + else state <= next_state; + +always @(state or ep_stall or buf0_na or buf1_na or + pid_seq_err or idma_done or token_valid or pid_ACK or rx_data_done or + tx_data_to or crc16_err or ep_disabled or no_bufs or mode_hs + or dma_en or rx_ack_to or pid_PING or txfr_iso or to_small or to_large or + CTRL_ep or pid_IN or pid_OUT or IN_ep or OUT_ep or pid_SETUP or pid_SOF + or match_r or abort or buffer_done or no_buf0_dma or max_pl_sz) + begin + next_state = state; + token_pid_sel_d = ACK; + send_token_d = 1'b0; + rx_dma_en = 1'b0; + tx_dma_en = 1'b0; + buf_set_d = 1'b0; + uc_stat_set_d = 1'b0; + buf0_rl_d = 1'b0; + int_set_en = 1'b0; + rx_ack_to_clr_d = 1'b1; + int_seqerr_set_d = 1'b0; + send_zero_length = 1'b0; + + case(state) // synopsys full_case parallel_case + IDLE: + begin +// synopsys translate_off +`ifdef USBF_VERBOSE_DEBUG + $display("PE: Entered state IDLE (%t)", $time); +`endif +`ifdef USBF_DEBUG + if(rst && match_r && !ep_disabled && !pid_SOF) + begin + if(match_r === 1'bx) $display("ERROR: IDLE: match_r is unknown. (%t)", $time); + if(ep_disabled === 1'bx)$display("ERROR: IDLE: ep_disabled is unknown. (%t)", $time); + if(pid_SOF === 1'bx) $display("ERROR: IDLE: pid_SOF is unknown. (%t)", $time); + if(ep_stall === 1'bx) $display("ERROR: IDLE: ep_stall is unknown. (%t)", $time); + if(buf0_na === 1'bx) $display("ERROR: IDLE: buf0_na is unknown. (%t)", $time); + if(buf1_na === 1'bx) $display("ERROR: IDLE: buf1_na is unknown. (%t)", $time); + if(no_buf0_dma === 1'bx)$display("ERROR: IDLE: no_buf0_dma is unknown. (%t)", $time); + if(CTRL_ep === 1'bx) $display("ERROR: IDLE: CTRL_ep is unknown. (%t)", $time); + if(pid_IN === 1'bx) $display("ERROR: IDLE: pid_IN is unknown. (%t)", $time); + if(pid_OUT === 1'bx) $display("ERROR: IDLE: pid_OUT is unknown. (%t)", $time); + if(pid_SETUP === 1'bx) $display("ERROR: IDLE: pid_SETUP is unknown. (%t)", $time); + if(pid_PING === 1'bx) $display("ERROR: IDLE: pid_PING is unknown. (%t)", $time); + if(mode_hs === 1'bx) $display("ERROR: IDLE: mode_hs is unknown. (%t)", $time); + if(IN_ep === 1'bx) $display("ERROR: IDLE: IN_ep is unknown. (%t)", $time); + if(OUT_ep === 1'bx) $display("ERROR: IDLE: OUT_ep is unknown. (%t)", $time); + end +`endif +// synopsys translate_on + + if(match_r && !ep_disabled && !pid_SOF) + begin + if(ep_stall) // Halt Forced send STALL + begin + token_pid_sel_d = STALL; + send_token_d = 1'b1; + next_state = TOKEN; + end + else + if( (buf0_na && buf1_na) || no_buf0_dma || + (CTRL_ep && pid_IN && buf1_na) || + (CTRL_ep && pid_OUT && buf0_na) + ) + begin // No buffers send NAK + token_pid_sel_d = NACK; + send_token_d = 1'b1; + next_state = TOKEN; + end + else + if(pid_PING && mode_hs) + begin + token_pid_sel_d = ACK; + send_token_d = 1'b1; + next_state = TOKEN; + end + else + if(IN_ep || (CTRL_ep && pid_IN)) + begin + if(max_pl_sz == 11'h0) send_zero_length = 1'b1; + tx_dma_en = 1'b1; + next_state = IN; + end + else + if(OUT_ep || (CTRL_ep && (pid_OUT || pid_SETUP))) + begin + rx_dma_en = 1'b1; + next_state = OUT; + end + end + end + + TOKEN: + begin +// synopsys translate_off +`ifdef USBF_VERBOSE_DEBUG + $display("PE: Entered state TOKEN (%t)", $time); +`endif +// synopsys translate_on + next_state = IDLE; + end + + IN: + begin +// synopsys translate_off +`ifdef USBF_VERBOSE_DEBUG + $display("PE: Entered state IN (%t)", $time); +`endif +`ifdef USBF_DEBUG + if(idma_done === 1'bx) $display("ERROR: IN: idma_done is unknown. (%t)", $time); + if(txfr_iso === 1'bx) $display("ERROR: IN: txfr_iso is unknown. (%t)", $time); +`endif +// synopsys translate_on + rx_ack_to_clr_d = 1'b0; + if(idma_done) + begin + if(txfr_iso) next_state = UPDATE; + else next_state = IN2; + end + + end + IN2: + begin +// synopsys translate_off +`ifdef USBF_VERBOSE_DEBUG + $display("PE: Entered state IN2 (%t)", $time); +`endif +`ifdef USBF_DEBUG + if(rx_ack_to === 1'bx) $display("ERROR: IN2: rx_ack_to is unknown. (%t)", $time); + if(token_valid === 1'bx)$display("ERROR: IN2: token_valid is unknown. (%t)", $time); + if(pid_ACK === 1'bx) $display("ERROR: IN2: pid_ACK is unknown. (%t)", $time); +`endif +// synopsys translate_on + rx_ack_to_clr_d = 1'b0; + // Wait for ACK from HOST or Timeout + if(rx_ack_to) next_state = IDLE; + else + if(token_valid && pid_ACK) + begin + next_state = UPDATE; + end + end + + OUT: + begin +// synopsys translate_off +`ifdef USBF_VERBOSE_DEBUG + $display("PE: Entered state OUT (%t)", $time); +`endif +`ifdef USBF_DEBUG + if(tx_data_to === 1'bx) $display("ERROR: OUT: tx_data_to is unknown. (%t)", $time); + if(crc16_err === 1'bx) $display("ERROR: OUT: crc16_err is unknown. (%t)", $time); + if(abort === 1'bx) $display("ERROR: OUT: abort is unknown. (%t)", $time); + if(rx_data_done === 1'bx)$display("ERROR: OUT: rx_data_done is unknown. (%t)", $time); + if(txfr_iso === 1'bx) $display("ERROR: OUT: txfr_iso is unknown. (%t)", $time); + if(pid_seq_err === 1'bx)$display("ERROR: OUT: rx_data_done is unknown. (%t)", $time); +`endif +// synopsys translate_on + if(tx_data_to || crc16_err || abort ) + next_state = IDLE; + else + if(rx_data_done) + begin // Send Ack + if(txfr_iso) + begin + if(pid_seq_err) int_seqerr_set_d = 1'b1; + next_state = UPDATEW; + end + else next_state = OUT2A; + end + end + + OUT2A: + begin // This is a delay State to NACK to small or to + // large packets. this state could be skipped +// synopsys translate_off +`ifdef USBF_VERBOSE_DEBUG + $display("PE: Entered state OUT2A (%t)", $time); +`endif +`ifdef USBF_DEBUG + if(abort === 1'bx) $display("ERROR: OUT2A: abort is unknown. (%t)", $time); +`endif +// synopsys translate_on + if(abort) next_state = IDLE; + else next_state = OUT2B; + end + OUT2B: + begin // Send ACK/NACK/NYET +// synopsys translate_off +`ifdef USBF_VERBOSE_DEBUG + $display("PE: Entered state OUT2B (%t)", $time); +`endif +`ifdef USBF_DEBUG + if(abort === 1'bx) $display("ERROR: OUT2B: abort is unknown. (%t)", $time); + if(to_small === 1'bx) $display("ERROR: OUT2B: to_small is unknown. (%t)", $time); + if(to_large === 1'bx) $display("ERROR: OUT2B: to_large is unknown. (%t)", $time); + if(pid_seq_err === 1'bx)$display("ERROR: OUT2B: rx_data_done is unknown. (%t)", $time); + if(mode_hs === 1'bx) $display("ERROR: OUT2B: mode_hs is unknown. (%t)", $time); + if(no_bufs === 1'bx) $display("ERROR: OUT2B: no_bufs is unknown. (%t)", $time); +`endif +// synopsys translate_on + if(abort) next_state = IDLE; + else + if(to_small || to_large) + begin + token_pid_sel_d = NACK; + next_state = IDLE; + end + else + if(pid_seq_err) + begin + token_pid_sel_d = ACK; + send_token_d = 1'b1; + next_state = IDLE; + end + else + begin + if(mode_hs && no_bufs) token_pid_sel_d = NYET; + else token_pid_sel_d = ACK; + send_token_d = 1'b1; + next_state = UPDATE; + end + end + + UPDATEW: + begin +// synopsys translate_off +`ifdef USBF_VERBOSE_DEBUG + $display("PE: Entered state UPDATEW (%t)", $time); +`endif +// synopsys translate_on + next_state = UPDATE; + end + UPDATE: + begin +// synopsys translate_off +`ifdef USBF_VERBOSE_DEBUG + $display("PE: Entered state UPDATE (%t)", $time); +`endif +`ifdef USBF_DEBUG + if(buffer_done === 1'bx) $display("ERROR: UPDATE: buffer_done is unknown. (%t)", $time); + if(dma_en === 1'bx) $display("ERROR: UPDATE: dma_en is unknown. (%t)", $time); +`endif +// synopsys translate_on + // Interrupts + int_set_en = 1'b1; + // Buffer (used, size, adr) set or reload + if(buffer_done && dma_en) + begin + buf0_rl_d = 1'b1; + end + else + begin + buf_set_d = 1'b1; + end + next_state = UPDATE2; + end + UPDATE2: // Update Register File & state + begin +// synopsys translate_off +`ifdef USBF_VERBOSE_DEBUG + $display("PE: Entered state UPDATE2 (%t)", $time); +`endif +// synopsys translate_on + // pid sequence & buffer usage + uc_stat_set_d = 1'b1; + next_state = IDLE; + end + endcase + end + +endmodule + diff --git a/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_pl.v b/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_pl.v new file mode 100644 index 0000000..96e8137 --- /dev/null +++ b/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_pl.v @@ -0,0 +1,474 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Protocol Layer //// +//// This block is typically referred to as the SEI in USB //// +//// Specification. It encapsulates the Packet Assembler, //// +//// disassembler, protocol engine and internal DMA //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/usb/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2003 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: usbf_pl.v,v 1.5 2003-10-17 02:36:57 rudi Exp $ +// +// $Date: 2003-10-17 02:36:57 $ +// $Revision: 1.5 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.4 2001/11/04 12:22:45 rudi +// +// - Fixed previous fix (brocke something else ...) +// - Majore Synthesis cleanup +// +// Revision 1.3 2001/09/24 01:15:28 rudi +// +// Changed reset to be active high async. +// +// Revision 1.2 2001/08/10 08:48:33 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// +// Revision 1.1 2001/08/03 05:30:09 rudi +// +// +// 1) Reorganized directory structure +// +// Revision 1.2 2001/03/31 13:00:52 rudi +// +// - Added Core configuration +// - Added handling of OUT packets less than MAX_PL_SZ in DMA mode +// - Modified WISHBONE interface and sync logic +// - Moved SSRAM outside the core (added interface) +// - Many small bug fixes ... +// +// Revision 1.0 2001/03/07 09:17:12 rudi +// +// +// Changed all revisions to revision 1.0. This is because OpenCores CVS +// interface could not handle the original '0.1' revision .... +// +// Revision 0.1.0.1 2001/02/28 08:11:11 rudi +// Initial Release +// +// + +`include "usbf_defines.v" + +module usbf_pl( clk, rst, + + // UTMI Interface + rx_data, rx_valid, rx_active, rx_err, + tx_data, tx_valid, tx_valid_last, tx_ready, + tx_first, tx_valid_out, + mode_hs, usb_reset, usb_suspend, usb_attached, + + // memory interface + madr, mdout, mdin, mwe, mreq, mack, + + // Register File Interface + fa, idin, + ep_sel, match, + dma_in_buf_sz1, dma_out_buf_avail, + buf0_rl, buf0_set, buf1_set, + uc_bsel_set, uc_dpd_set, + + int_buf1_set, int_buf0_set, int_upid_set, + int_crc16_set, int_to_set, int_seqerr_set, + out_to_small, csr, buf0, buf1, + + // Misc + frm_nat, + pid_cs_err, nse_err, + crc5_err + ); + +parameter SSRAM_HADR = 14; + +// UTMI Interface +input clk, rst; +input [7:0] rx_data; +input rx_valid, rx_active, rx_err; +output [7:0] tx_data; +output tx_valid; +output tx_valid_last; +input tx_ready; +output tx_first; +input tx_valid_out; +input mode_hs; // High Speed Mode +input usb_reset; // USB Reset +input usb_suspend; // USB Suspend +input usb_attached; // Attached to USB + +// Memory Arbiter Interface +output [SSRAM_HADR:0] madr; // word address +output [31:0] mdout; +input [31:0] mdin; +output mwe; +output mreq; +input mack; + +// Register File interface +input [6:0] fa; // Function Address (as set by the controller) +output [31:0] idin; // Data Input +output [3:0] ep_sel; // Endpoint Number Input +input match; // Endpoint Matched +input dma_in_buf_sz1; +input dma_out_buf_avail; +output nse_err; // no such endpoint error + +output buf0_rl; // Reload Buf 0 with original values +output buf0_set; // Write to buf 0 +output buf1_set; // Write to buf 1 +output uc_bsel_set; // Write to the uc_bsel field +output uc_dpd_set; // Write to the uc_dpd field +output int_buf1_set; // Set buf1 full/empty interrupt +output int_buf0_set; // Set buf0 full/empty interrupt +output int_upid_set; // Set unsupported PID interrupt +output int_crc16_set; // Set CRC16 error interrupt +output int_to_set; // Set time out interrupt +output int_seqerr_set; // Set PID sequence error interrupt +output out_to_small; // OUT packet was to small for DMA operation + +input [31:0] csr; // Internal CSR Output +input [31:0] buf0; // Internal Buf 0 Output +input [31:0] buf1; // Internal Buf 1 Output + +// Misc +output pid_cs_err; // pid checksum error +output crc5_err; // crc5 error +output [31:0] frm_nat; + +/////////////////////////////////////////////////////////////////// +// +// Local Wires and Registers +// + +// Packet Disassembler Interface +wire clk, rst; +wire [7:0] rx_data; +wire pid_OUT, pid_IN, pid_SOF, pid_SETUP; +wire pid_DATA0, pid_DATA1, pid_DATA2, pid_MDATA; +wire pid_ACK, pid_NACK, pid_STALL, pid_NYET; +wire pid_PRE, pid_ERR, pid_SPLIT, pid_PING; +wire [6:0] token_fadr; +wire token_valid; +wire crc5_err; +wire [10:0] frame_no; +wire [7:0] rx_data_st; +wire rx_data_valid; +wire rx_data_done; +wire crc16_err; +wire rx_seq_err; + +// Packet Assembler Interface +wire send_token; +wire [1:0] token_pid_sel; +wire send_data; +wire [1:0] data_pid_sel; +wire [7:0] tx_data_st; +wire rd_next; + +// IDMA Interface +wire rx_dma_en; // Allows the data to be stored +wire tx_dma_en; // Allows for data to be retrieved +wire abort; // Abort Transfer (time_out, crc_err or rx_error) +wire idma_done; // DMA is done +wire [SSRAM_HADR + 2:0] adr; // Byte Address +wire [13:0] size; // Size in bytes +wire [10:0] sizu_c; // Up and Down counting size registers, used + // to update +wire [13:0] buf_size; // Actual buffer size +wire dma_en; // external dma enabled + +// Memory Arbiter Interface +wire [SSRAM_HADR:0] madr; // word address +wire [31:0] mdout; +wire [31:0] mdin; +wire mwe; +wire mreq; +wire mack; + +// Local signals +wire pid_bad, pid_bad1, pid_bad2; + +reg hms_clk; // 0.5 Micro Second Clock +reg [4:0] hms_cnt; +reg [10:0] frame_no_r; // Current Frame Number register +wire frame_no_we; +reg frame_no_same; // Indicates current and prev. frame numbers + // are equal +reg [3:0] mfm_cnt; // Micro Frame Counter +reg [11:0] sof_time; // Time since last sof +reg clr_sof_time; +wire fsel; // This Function is selected +wire match_o; + +reg frame_no_we_r; + +/////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +// PIDs we should never receive +assign pid_bad1 = pid_ACK | pid_NACK | pid_STALL | pid_NYET | pid_PRE | + pid_ERR | pid_SPLIT; + +// PIDs we should never get in full speed mode (high speed mode only) +assign pid_bad2 = !mode_hs & pid_PING; + +// All bad pids +assign pid_bad = pid_bad1 | pid_bad2; + +assign match_o = !pid_bad & fsel & match & token_valid & !crc5_err; + +// Frame Number (from SOF token) +assign frame_no_we = token_valid & !crc5_err & pid_SOF; + +always @(posedge clk) + frame_no_we_r <= frame_no_we; + +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) frame_no_r <= 11'h0; + else + if(frame_no_we_r) frame_no_r <= frame_no; + +// Micro Frame Counter +always @(posedge clk) + frame_no_same <= frame_no_we & (frame_no_r == frame_no); + +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) mfm_cnt <= 4'h0; + else + if(frame_no_we_r && !frame_no_same) + mfm_cnt <= 4'h0; + else + if(frame_no_same) mfm_cnt <= mfm_cnt + 4'h1; + +//SOF delay counter +always @(posedge clk) + clr_sof_time <= frame_no_we; + +always @(posedge clk) + if(clr_sof_time) sof_time <= 12'h0; + else + if(hms_clk) sof_time <= sof_time + 12'h1; + +assign frm_nat = {mfm_cnt, 1'b0, frame_no_r, 4'h0, sof_time}; + +// 0.5 Micro Seconds Clock Generator +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) hms_cnt <= 5'h0; + else + if(hms_clk || frame_no_we_r) hms_cnt <= 5'h0; + else hms_cnt <= hms_cnt + 5'h1; + +always @(posedge clk) + hms_clk <= (hms_cnt == `USBF_HMS_DEL); + +/////////////////////////////////////////////////////////////////// + +// This function is addressed +assign fsel = (token_fadr == fa); + +/////////////////////////////////////////////////////////////////// +// +// Module Instantiations +// + +//Packet Decoder +usbf_pd u0( .clk( clk ), + .rst( rst ), + .rx_data( rx_data ), + .rx_valid( rx_valid ), + .rx_active( rx_active ), + .rx_err( rx_err ), + .pid_OUT( pid_OUT ), + .pid_IN( pid_IN ), + .pid_SOF( pid_SOF ), + .pid_SETUP( pid_SETUP ), + .pid_DATA0( pid_DATA0 ), + .pid_DATA1( pid_DATA1 ), + .pid_DATA2( pid_DATA2 ), + .pid_MDATA( pid_MDATA ), + .pid_ACK( pid_ACK ), + .pid_NACK( pid_NACK ), + .pid_STALL( pid_STALL ), + .pid_NYET( pid_NYET ), + .pid_PRE( pid_PRE ), + .pid_ERR( pid_ERR ), + .pid_SPLIT( pid_SPLIT ), + .pid_PING( pid_PING ), + .pid_cks_err( pid_cs_err ), + .token_fadr( token_fadr ), + .token_endp( ep_sel ), + .token_valid( token_valid ), + .crc5_err( crc5_err ), + .frame_no( frame_no ), + .rx_data_st( rx_data_st ), + .rx_data_valid( rx_data_valid ), + .rx_data_done( rx_data_done ), + .crc16_err( crc16_err ), + .seq_err( rx_seq_err ) + ); + +// Packet Assembler +usbf_pa u1( .clk( clk ), + .rst( rst ), + .tx_data( tx_data ), + .tx_valid( tx_valid ), + .tx_valid_last( tx_valid_last ), + .tx_ready( tx_ready ), + .tx_first( tx_first ), + .send_token( send_token ), + .token_pid_sel( token_pid_sel ), + .send_data( send_data ), + .data_pid_sel( data_pid_sel ), + .send_zero_length( send_zero_length ), + .tx_data_st( tx_data_st ), + .rd_next( rd_next ) + ); + +// Internal DMA / Memory Arbiter Interface +usbf_idma #(SSRAM_HADR) + u2( .clk( clk ), + .rst( rst ), + .rx_data_st( rx_data_st ), + .rx_data_valid( rx_data_valid ), + .rx_data_done( rx_data_done ), + .send_data( send_data ), + .tx_data_st( tx_data_st ), + .rd_next( rd_next ), + .rx_dma_en( rx_dma_en ), + .tx_dma_en( tx_dma_en ), + .abort( abort ), + .idma_done( idma_done ), + .adr( adr ), + .size( size ), + .buf_size( buf_size ), + .dma_en( dma_en ), + .send_zero_length( send_zero_length ), + .madr( madr ), + .sizu_c( sizu_c ), + .mdout( mdout ), + .mdin( mdin ), + .mwe( mwe ), + .mreq( mreq ), + .mack( mack ) + ); + +// Protocol Engine +usbf_pe #(SSRAM_HADR) + u3( .clk( clk ), + .rst( rst ), + .tx_valid( tx_valid_out ), + .rx_active( rx_active ), + .pid_OUT( pid_OUT ), + .pid_IN( pid_IN ), + .pid_SOF( pid_SOF ), + .pid_SETUP( pid_SETUP ), + .pid_DATA0( pid_DATA0 ), + .pid_DATA1( pid_DATA1 ), + .pid_DATA2( pid_DATA2 ), + .pid_MDATA( pid_MDATA ), + .pid_ACK( pid_ACK ), + .pid_NACK( pid_NACK ), + .pid_STALL( pid_STALL ), + .pid_NYET( pid_NYET ), + .pid_PRE( pid_PRE ), + .pid_ERR( pid_ERR ), + .pid_SPLIT( pid_SPLIT ), + .pid_PING( pid_PING ), + .mode_hs( mode_hs ), + .token_valid( token_valid ), + .crc5_err( crc5_err ), + .rx_data_valid( rx_data_valid ), + .rx_data_done( rx_data_done ), + .crc16_err( crc16_err ), + .send_token( send_token ), + .token_pid_sel( token_pid_sel ), + .data_pid_sel( data_pid_sel ), + .send_zero_length( send_zero_length ), + .rx_dma_en( rx_dma_en ), + .tx_dma_en( tx_dma_en ), + .abort( abort ), + .idma_done( idma_done ), + .adr( adr ), + .size( size ), + .buf_size( buf_size ), + .sizu_c( sizu_c ), + .dma_en( dma_en ), + .fsel( fsel ), + .idin( idin ), + .ep_sel( ep_sel ), + .match( match_o ), + .dma_in_buf_sz1( dma_in_buf_sz1 ), + .dma_out_buf_avail( dma_out_buf_avail ), + .nse_err( nse_err ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( csr ), + .buf0( buf0 ), + .buf1( buf1 ) + ); + +endmodule + diff --git a/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_rf.v b/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_rf.v new file mode 100644 index 0000000..b02f5da --- /dev/null +++ b/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_rf.v @@ -0,0 +1,1900 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// Register File //// +//// This module contains all top level registers and //// +//// instantiates the register files for endpoints //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/usb/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2003 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: usbf_rf.v,v 1.6 2003-10-17 02:36:57 rudi Exp $ +// +// $Date: 2003-10-17 02:36:57 $ +// $Revision: 1.6 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.5 2001/11/04 12:22:45 rudi +// +// - Fixed previous fix (brocke something else ...) +// - Majore Synthesis cleanup +// +// Revision 1.4 2001/11/03 03:26:23 rudi +// +// - Fixed several interrupt and error condition reporting bugs +// +// Revision 1.3 2001/09/24 01:15:28 rudi +// +// Changed reset to be active high async. +// +// Revision 1.2 2001/08/10 08:48:33 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// +// Revision 1.1 2001/08/03 05:30:09 rudi +// +// +// 1) Reorganized directory structure +// +// Revision 1.2 2001/03/31 13:00:52 rudi +// +// - Added Core configuration +// - Added handling of OUT packets less than MAX_PL_SZ in DMA mode +// - Modified WISHBONE interface and sync logic +// - Moved SSRAM outside the core (added interface) +// - Many small bug fixes ... +// +// Revision 1.0 2001/03/07 09:17:12 rudi +// +// +// Changed all revisions to revision 1.0. This is because OpenCores CVS +// interface could not handle the original '0.1' revision .... +// +// Revision 0.2 2001/03/07 09:08:13 rudi +// +// Added USB controll signaling (Line Status) block. Fixed some minor +// typos, added resume bit and signal. +// +// Revision 0.1.0.1 2001/02/28 08:11:32 rudi +// Initial Release +// +// + +`include "usbf_defines.v" + +// Endpoint register File +module usbf_rf( clk, wclk, rst, + + // Wishbone Interface + adr, re, we, din, dout, inta, intb, + dma_req, dma_ack, + + // Internal Interface + idin, + ep_sel, match, + buf0_rl, buf0_set, buf1_set, + uc_bsel_set, uc_dpd_set, + + int_buf1_set, int_buf0_set, int_upid_set, + int_crc16_set, int_to_set, int_seqerr_set, + out_to_small, + + csr, buf0, buf1, + funct_adr, + dma_in_buf_sz1, dma_out_buf_avail, + + // Misc + frm_nat, + utmi_vend_stat, utmi_vend_ctrl, utmi_vend_wr, + line_stat, usb_attached, mode_hs, suspend, + attached, usb_reset, pid_cs_err, nse_err, + crc5_err, rx_err, rf_resume_req + ); + +input clk, wclk, rst; +input [6:0] adr; +input re; +input we; +input [31:0] din; +output [31:0] dout; +output inta, intb; +output [15:0] dma_req; +input [15:0] dma_ack; + +input [31:0] idin; // Data Input +input [3:0] ep_sel; // Endpoint Number Input +output match; // Endpoint Matched +input buf0_rl; // Reload Buf 0 with original values + +input buf0_set; // Write to buf 0 +input buf1_set; // Write to buf 1 +input uc_bsel_set; // Write to the uc_bsel field +input uc_dpd_set; // Write to the uc_dpd field +input int_buf1_set; // Set buf1 full/empty interrupt +input int_buf0_set; // Set buf0 full/empty interrupt +input int_upid_set; // Set unsupported PID interrupt +input int_crc16_set; // Set CRC16 error interrupt +input int_to_set; // Set time out interrupt +input int_seqerr_set; // Set PID Sequence Error Interrupt +input out_to_small; // OUT packet was to small for DMA operation + +output [31:0] csr; // Internal CSR Output +output [31:0] buf0; // Internal Buf 0 Output +output [31:0] buf1; // Internal Buf 1 Output +output [6:0] funct_adr; // Function Address +output dma_in_buf_sz1, dma_out_buf_avail; + +input [31:0] frm_nat; + +input [7:0] utmi_vend_stat; // UTMI Vendor C/S bus +output [3:0] utmi_vend_ctrl; +output utmi_vend_wr; + +input [1:0] line_stat; // Below are signals for interrupt generation +input usb_attached; +input mode_hs; +input suspend; +input attached; +input usb_reset; +input nse_err; +input pid_cs_err; +input crc5_err; +input rx_err; +output rf_resume_req; + +/////////////////////////////////////////////////////////////////// +// +// Local Wires and Registers +// + +wire [31:0] ep0_dout, ep1_dout, ep2_dout, ep3_dout; +wire [31:0] ep4_dout, ep5_dout, ep6_dout, ep7_dout; +wire [31:0] ep8_dout, ep9_dout, ep10_dout, ep11_dout; +wire [31:0] ep12_dout, ep13_dout, ep14_dout, ep15_dout; + +wire ep0_re, ep1_re, ep2_re, ep3_re; +wire ep4_re, ep5_re, ep6_re, ep7_re; +wire ep8_re, ep9_re, ep10_re, ep11_re; +wire ep12_re, ep13_re, ep14_re, ep15_re; + +wire ep0_we, ep1_we, ep2_we, ep3_we; +wire ep4_we, ep5_we, ep6_we, ep7_we; +wire ep8_we, ep9_we, ep10_we, ep11_we; +wire ep12_we, ep13_we, ep14_we, ep15_we; + +wire ep0_inta, ep1_inta, ep2_inta, ep3_inta; +wire ep4_inta, ep5_inta, ep6_inta, ep7_inta; +wire ep8_inta, ep9_inta, ep10_inta, ep11_inta; +wire ep12_inta, ep13_inta, ep14_inta, ep15_inta; + +wire ep0_intb, ep1_intb, ep2_intb, ep3_intb; +wire ep4_intb, ep5_intb, ep6_intb, ep7_intb; +wire ep8_intb, ep9_intb, ep10_intb, ep11_intb; +wire ep12_intb, ep13_intb, ep14_intb, ep15_intb; + +wire ep0_match, ep1_match, ep2_match, ep3_match; +wire ep4_match, ep5_match, ep6_match, ep7_match; +wire ep8_match, ep9_match, ep10_match, ep11_match; +wire ep12_match, ep13_match, ep14_match, ep15_match; + +wire [31:0] ep0_csr, ep1_csr, ep2_csr, ep3_csr; +wire [31:0] ep4_csr, ep5_csr, ep6_csr, ep7_csr; +wire [31:0] ep8_csr, ep9_csr, ep10_csr, ep11_csr; +wire [31:0] ep12_csr, ep13_csr, ep14_csr, ep15_csr; + +wire [31:0] ep0_buf0, ep1_buf0, ep2_buf0, ep3_buf0; +wire [31:0] ep4_buf0, ep5_buf0, ep6_buf0, ep7_buf0; +wire [31:0] ep8_buf0, ep9_buf0, ep10_buf0, ep11_buf0; +wire [31:0] ep12_buf0, ep13_buf0, ep14_buf0, ep15_buf0; + +wire [31:0] ep0_buf1, ep1_buf1, ep2_buf1, ep3_buf1; +wire [31:0] ep4_buf1, ep5_buf1, ep6_buf1, ep7_buf1; +wire [31:0] ep8_buf1, ep9_buf1, ep10_buf1, ep11_buf1; +wire [31:0] ep12_buf1, ep13_buf1, ep14_buf1, ep15_buf1; + +wire ep0_dma_in_buf_sz1, ep1_dma_in_buf_sz1; +wire ep2_dma_in_buf_sz1, ep3_dma_in_buf_sz1; +wire ep4_dma_in_buf_sz1, ep5_dma_in_buf_sz1; +wire ep6_dma_in_buf_sz1, ep7_dma_in_buf_sz1; +wire ep8_dma_in_buf_sz1, ep9_dma_in_buf_sz1; +wire ep10_dma_in_buf_sz1, ep11_dma_in_buf_sz1; +wire ep12_dma_in_buf_sz1, ep13_dma_in_buf_sz1; +wire ep14_dma_in_buf_sz1, ep15_dma_in_buf_sz1; + +wire ep0_dma_out_buf_avail, ep1_dma_out_buf_avail; +wire ep2_dma_out_buf_avail, ep3_dma_out_buf_avail; +wire ep4_dma_out_buf_avail, ep5_dma_out_buf_avail; +wire ep6_dma_out_buf_avail, ep7_dma_out_buf_avail; +wire ep8_dma_out_buf_avail, ep9_dma_out_buf_avail; +wire ep10_dma_out_buf_avail, ep11_dma_out_buf_avail; +wire ep12_dma_out_buf_avail, ep13_dma_out_buf_avail; +wire ep14_dma_out_buf_avail, ep15_dma_out_buf_avail; + +reg dma_in_buf_sz1; +reg dma_out_buf_avail; + +reg [31:0] dtmp; +reg [31:0] dout; + +wire [31:0] main_csr; +reg [6:0] funct_adr; +reg [8:0] intb_msk, inta_msk; + +reg match_r1; +reg [31:0] csr; +reg [31:0] buf0; +reg [31:0] buf1; + +reg [3:0] utmi_vend_ctrl; +reg utmi_vend_wr; +reg [7:0] utmi_vend_stat_r; + +reg int_src_re; +reg [8:0] int_srcb; +reg [15:0] int_srca; +reg attach_r, attach_r1; +wire attach, deattach; +reg suspend_r, suspend_r1; +wire suspend_start, suspend_end; +reg usb_reset_r; +reg rx_err_r; +reg nse_err_r; +reg pid_cs_err_r; +reg crc5_err_r; + +reg rf_resume_req_r, rf_resume_req; + +wire inta_ep, intb_ep; +wire inta_rf, intb_rf; +reg inta, intb; + +/////////////////////////////////////////////////////////////////// +// +// WISHBONE Access +// + +// Main CSR Alias +assign main_csr = {27'h0, line_stat, usb_attached, mode_hs, suspend}; + +// Read Registers Logic +always @(adr or main_csr or funct_adr or inta_msk or intb_msk or int_srca + or int_srcb or frm_nat or utmi_vend_stat_r) + case(adr[2:0]) // synopsys full_case parallel_case + 3'h0: dtmp = main_csr; + 3'h1: dtmp = { 25'h0, funct_adr}; + 3'h2: dtmp = { 7'h0, intb_msk, 7'h0, inta_msk}; + 3'h3: dtmp = { 3'h0, int_srcb, 4'h0, int_srca}; + 3'h4: dtmp = frm_nat; + 3'h5: dtmp = { 24'h0, utmi_vend_stat_r}; + endcase + +// Interrupt Source Read Register +always @(posedge wclk) + int_src_re <= adr[6:0] == 7'h3 & re; + +// UTMI Vendor Control Stuff +always @(posedge wclk) + utmi_vend_stat_r <= utmi_vend_stat; + +reg utmi_vend_wr_r; +`ifdef USBF_ASYNC_RESET +always @(posedge wclk or negedge rst) +`else +always @(posedge wclk) +`endif + if(!rst) utmi_vend_wr_r <= 1'b0; + else + if(adr[6:0] == 7'h5 && we) utmi_vend_wr_r <= 1'b1; + else + if(utmi_vend_wr) utmi_vend_wr_r <= 1'b0; + +always @(posedge clk) // Second Stage sync + utmi_vend_wr <= utmi_vend_wr_r; + + +reg [3:0] utmi_vend_ctrl_r; +always @(posedge wclk) + if(adr[6:0] == 7'h5 && we) utmi_vend_ctrl_r <= din[3:0]; + +always @(posedge clk) // Second Stage sync + utmi_vend_ctrl <= utmi_vend_ctrl_r; + +// Resume Request +`ifdef USBF_ASYNC_RESET +always @(posedge wclk or negedge rst) +`else +always @(posedge wclk) +`endif + if(!rst) rf_resume_req_r <= 1'b0; + else + if(adr[6:0] == 7'h0 && we) rf_resume_req_r <= din[5]; + else + if(rf_resume_req) rf_resume_req_r <= 1'b0; + +always @(posedge clk) // Second Stage sync + rf_resume_req <= rf_resume_req_r; + +// Function Address Register +`ifdef USBF_ASYNC_RESET +always @(posedge wclk or negedge rst) +`else +always @(posedge wclk) +`endif + if(!rst) funct_adr <= 7'h0; + else + if(adr[6:0] == 7'h1 && we) funct_adr <= din[6:0]; + +// Interrup Mask Register +`ifdef USBF_ASYNC_RESET +always @(posedge wclk or negedge rst) +`else +always @(posedge wclk) +`endif + if(!rst) + begin + inta_msk <= 9'h0; + intb_msk <= 9'h0; + end + else + if(adr[6:0] == 7'h2 && we) + begin + intb_msk <= din[24:16]; + inta_msk <= din[08:00]; + end + +always @(posedge wclk) + case(adr[6:2]) // synopsys full_case parallel_case + 5'h00: dout <= dtmp; // Addr: 0h + 5'h01: dout <= dtmp; + 5'h02: dout <= 32'h0; + 5'h03: dout <= 32'h0; + 5'h04: dout <= ep0_dout; + 5'h05: dout <= ep1_dout; + 5'h06: dout <= ep2_dout; + 5'h07: dout <= ep3_dout; + 5'h08: dout <= ep4_dout; + 5'h09: dout <= ep5_dout; + 5'h0a: dout <= ep6_dout; + 5'h0b: dout <= ep7_dout; + 5'h0c: dout <= ep8_dout; + 5'h0d: dout <= ep9_dout; + 5'h0e: dout <= ep10_dout; + 5'h0f: dout <= ep11_dout; + 5'h10: dout <= ep12_dout; + 5'h11: dout <= ep13_dout; + 5'h12: dout <= ep14_dout; + 5'h13: dout <= ep15_dout; + endcase + +assign ep0_re = (adr[6:2] == 5'h04) & re; +assign ep1_re = (adr[6:2] == 5'h05) & re; +assign ep2_re = (adr[6:2] == 5'h06) & re; +assign ep3_re = (adr[6:2] == 5'h07) & re; +assign ep4_re = (adr[6:2] == 5'h08) & re; +assign ep5_re = (adr[6:2] == 5'h09) & re; +assign ep6_re = (adr[6:2] == 5'h0a) & re; +assign ep7_re = (adr[6:2] == 5'h0b) & re; +assign ep8_re = (adr[6:2] == 5'h0c) & re; +assign ep9_re = (adr[6:2] == 5'h0d) & re; +assign ep10_re = (adr[6:2] == 5'h0e) & re; +assign ep11_re = (adr[6:2] == 5'h0f) & re; +assign ep12_re = (adr[6:2] == 5'h10) & re; +assign ep13_re = (adr[6:2] == 5'h11) & re; +assign ep14_re = (adr[6:2] == 5'h12) & re; +assign ep15_re = (adr[6:2] == 5'h13) & re; + +assign ep0_we = (adr[6:2] == 5'h04) & we; +assign ep1_we = (adr[6:2] == 5'h05) & we; +assign ep2_we = (adr[6:2] == 5'h06) & we; +assign ep3_we = (adr[6:2] == 5'h07) & we; +assign ep4_we = (adr[6:2] == 5'h08) & we; +assign ep5_we = (adr[6:2] == 5'h09) & we; +assign ep6_we = (adr[6:2] == 5'h0a) & we; +assign ep7_we = (adr[6:2] == 5'h0b) & we; +assign ep8_we = (adr[6:2] == 5'h0c) & we; +assign ep9_we = (adr[6:2] == 5'h0d) & we; +assign ep10_we = (adr[6:2] == 5'h0e) & we; +assign ep11_we = (adr[6:2] == 5'h0f) & we; +assign ep12_we = (adr[6:2] == 5'h10) & we; +assign ep13_we = (adr[6:2] == 5'h11) & we; +assign ep14_we = (adr[6:2] == 5'h12) & we; +assign ep15_we = (adr[6:2] == 5'h13) & we; + +/////////////////////////////////////////////////////////////////// +// +// Internal Access +// + +assign match = match_r1; + +always @(posedge clk) + match_r1 <= ep0_match | ep1_match | ep2_match | ep3_match | + ep4_match | ep5_match | ep6_match | ep7_match | + ep8_match | ep9_match | ep10_match | ep11_match | + ep12_match | ep13_match | ep14_match | ep15_match; + +always @(posedge clk) + if(ep0_match) csr <= ep0_csr; + else + if(ep1_match) csr <= ep1_csr; + else + if(ep2_match) csr <= ep2_csr; + else + if(ep3_match) csr <= ep3_csr; + else + if(ep4_match) csr <= ep4_csr; + else + if(ep5_match) csr <= ep5_csr; + else + if(ep6_match) csr <= ep6_csr; + else + if(ep7_match) csr <= ep7_csr; + else + if(ep8_match) csr <= ep8_csr; + else + if(ep9_match) csr <= ep9_csr; + else + if(ep10_match) csr <= ep10_csr; + else + if(ep11_match) csr <= ep11_csr; + else + if(ep12_match) csr <= ep12_csr; + else + if(ep13_match) csr <= ep13_csr; + else + if(ep14_match) csr <= ep14_csr; + else + if(ep15_match) csr <= ep15_csr; + +always @(posedge clk) + if(ep0_match) buf0 <= ep0_buf0; + else + if(ep1_match) buf0 <= ep1_buf0; + else + if(ep2_match) buf0 <= ep2_buf0; + else + if(ep3_match) buf0 <= ep3_buf0; + else + if(ep4_match) buf0 <= ep4_buf0; + else + if(ep5_match) buf0 <= ep5_buf0; + else + if(ep6_match) buf0 <= ep6_buf0; + else + if(ep7_match) buf0 <= ep7_buf0; + else + if(ep8_match) buf0 <= ep8_buf0; + else + if(ep9_match) buf0 <= ep9_buf0; + else + if(ep10_match) buf0 <= ep10_buf0; + else + if(ep11_match) buf0 <= ep11_buf0; + else + if(ep12_match) buf0 <= ep12_buf0; + else + if(ep13_match) buf0 <= ep13_buf0; + else + if(ep14_match) buf0 <= ep14_buf0; + else + if(ep15_match) buf0 <= ep15_buf0; + +always @(posedge clk) + if(ep0_match) buf1 <= ep0_buf1; + else + if(ep1_match) buf1 <= ep1_buf1; + else + if(ep2_match) buf1 <= ep2_buf1; + else + if(ep3_match) buf1 <= ep3_buf1; + else + if(ep4_match) buf1 <= ep4_buf1; + else + if(ep5_match) buf1 <= ep5_buf1; + else + if(ep6_match) buf1 <= ep6_buf1; + else + if(ep7_match) buf1 <= ep7_buf1; + else + if(ep8_match) buf1 <= ep8_buf1; + else + if(ep9_match) buf1 <= ep9_buf1; + else + if(ep10_match) buf1 <= ep10_buf1; + else + if(ep11_match) buf1 <= ep11_buf1; + else + if(ep12_match) buf1 <= ep12_buf1; + else + if(ep13_match) buf1 <= ep13_buf1; + else + if(ep14_match) buf1 <= ep14_buf1; + else + if(ep15_match) buf1 <= ep15_buf1; + +always @(posedge clk) + if(ep0_match) dma_in_buf_sz1 <= ep0_dma_in_buf_sz1; + else + if(ep1_match) dma_in_buf_sz1 <= ep1_dma_in_buf_sz1; + else + if(ep2_match) dma_in_buf_sz1 <= ep2_dma_in_buf_sz1; + else + if(ep3_match) dma_in_buf_sz1 <= ep3_dma_in_buf_sz1; + else + if(ep4_match) dma_in_buf_sz1 <= ep4_dma_in_buf_sz1; + else + if(ep5_match) dma_in_buf_sz1 <= ep5_dma_in_buf_sz1; + else + if(ep6_match) dma_in_buf_sz1 <= ep6_dma_in_buf_sz1; + else + if(ep7_match) dma_in_buf_sz1 <= ep7_dma_in_buf_sz1; + else + if(ep8_match) dma_in_buf_sz1 <= ep8_dma_in_buf_sz1; + else + if(ep9_match) dma_in_buf_sz1 <= ep9_dma_in_buf_sz1; + else + if(ep10_match) dma_in_buf_sz1 <= ep10_dma_in_buf_sz1; + else + if(ep11_match) dma_in_buf_sz1 <= ep11_dma_in_buf_sz1; + else + if(ep12_match) dma_in_buf_sz1 <= ep12_dma_in_buf_sz1; + else + if(ep13_match) dma_in_buf_sz1 <= ep13_dma_in_buf_sz1; + else + if(ep14_match) dma_in_buf_sz1 <= ep14_dma_in_buf_sz1; + else + if(ep15_match) dma_in_buf_sz1 <= ep15_dma_in_buf_sz1; + +always @(posedge clk) + if(ep0_match) dma_out_buf_avail <= ep0_dma_out_buf_avail; + else + if(ep1_match) dma_out_buf_avail <= ep1_dma_out_buf_avail; + else + if(ep2_match) dma_out_buf_avail <= ep2_dma_out_buf_avail; + else + if(ep3_match) dma_out_buf_avail <= ep3_dma_out_buf_avail; + else + if(ep4_match) dma_out_buf_avail <= ep4_dma_out_buf_avail; + else + if(ep5_match) dma_out_buf_avail <= ep5_dma_out_buf_avail; + else + if(ep6_match) dma_out_buf_avail <= ep6_dma_out_buf_avail; + else + if(ep7_match) dma_out_buf_avail <= ep7_dma_out_buf_avail; + else + if(ep8_match) dma_out_buf_avail <= ep8_dma_out_buf_avail; + else + if(ep9_match) dma_out_buf_avail <= ep9_dma_out_buf_avail; + else + if(ep10_match) dma_out_buf_avail <= ep10_dma_out_buf_avail; + else + if(ep11_match) dma_out_buf_avail <= ep11_dma_out_buf_avail; + else + if(ep12_match) dma_out_buf_avail <= ep12_dma_out_buf_avail; + else + if(ep13_match) dma_out_buf_avail <= ep13_dma_out_buf_avail; + else + if(ep14_match) dma_out_buf_avail <= ep14_dma_out_buf_avail; + else + if(ep15_match) dma_out_buf_avail <= ep15_dma_out_buf_avail; + + +/////////////////////////////////////////////////////////////////// +// +// Interrupt Generation +// + +always @(posedge wclk) + attach_r <= usb_attached; + +always @(posedge wclk) + attach_r1 <= attach_r; + +always @(posedge wclk) + suspend_r <= suspend; + +always @(posedge wclk) + suspend_r1 <= suspend_r; + +always @(posedge wclk) + usb_reset_r <= usb_reset; + +always @(posedge wclk) + rx_err_r <= rx_err; + +always @(posedge wclk) + nse_err_r <= nse_err; + +always @(posedge wclk) + pid_cs_err_r <= pid_cs_err; + +always @(posedge wclk) + crc5_err_r <= crc5_err; + +assign attach = !attach_r1 & attach_r; +assign deattach = attach_r1 & !attach_r; +assign suspend_start = !suspend_r1 & suspend_r; +assign suspend_end = suspend_r1 & !suspend_r; + +`ifdef USBF_ASYNC_RESET +always @(posedge wclk or negedge rst) +`else +always @(posedge wclk) +`endif + if(!rst) int_srcb[8] <= 1'b0; + else + if(int_src_re) int_srcb[8] <= 1'b0; + else + if(usb_reset_r) int_srcb[8] <= 1'b1; + +`ifdef USBF_ASYNC_RESET +always @(posedge wclk or negedge rst) +`else +always @(posedge wclk) +`endif + if(!rst) int_srcb[7] <= 1'b0; + else + if(int_src_re) int_srcb[7] <= 1'b0; + else + if(rx_err_r) int_srcb[7] <= 1'b1; + +`ifdef USBF_ASYNC_RESET +always @(posedge wclk or negedge rst) +`else +always @(posedge wclk) +`endif + if(!rst) int_srcb[6] <= 1'b0; + else + if(int_src_re) int_srcb[6] <= 1'b0; + else + if(deattach) int_srcb[6] <= 1'b1; + +`ifdef USBF_ASYNC_RESET +always @(posedge wclk or negedge rst) +`else +always @(posedge wclk) +`endif + if(!rst) int_srcb[5] <= 1'b0; + else + if(int_src_re) int_srcb[5] <= 1'b0; + else + if(attach) int_srcb[5] <= 1'b1; + +`ifdef USBF_ASYNC_RESET +always @(posedge wclk or negedge rst) +`else +always @(posedge wclk) +`endif + if(!rst) int_srcb[4] <= 1'b0; + else + if(int_src_re) int_srcb[4] <= 1'b0; + else + if(suspend_end) int_srcb[4] <= 1'b1; + +`ifdef USBF_ASYNC_RESET +always @(posedge wclk or negedge rst) +`else +always @(posedge wclk) +`endif + if(!rst) int_srcb[3] <= 1'b0; + else + if(int_src_re) int_srcb[3] <= 1'b0; + else + if(suspend_start) int_srcb[3] <= 1'b1; + +`ifdef USBF_ASYNC_RESET +always @(posedge wclk or negedge rst) +`else +always @(posedge wclk) +`endif + if(!rst) int_srcb[2] <= 1'b0; + else + if(int_src_re) int_srcb[2] <= 1'b0; + else + if(nse_err_r) int_srcb[2] <= 1'b1; + +`ifdef USBF_ASYNC_RESET +always @(posedge wclk or negedge rst) +`else +always @(posedge wclk) +`endif + if(!rst) int_srcb[1] <= 1'b0; + else + if(int_src_re) int_srcb[1] <= 1'b0; + else + if(pid_cs_err_r) int_srcb[1] <= 1'b1; + +`ifdef USBF_ASYNC_RESET +always @(posedge wclk or negedge rst) +`else +always @(posedge wclk) +`endif + if(!rst) int_srcb[0] <= 1'b0; + else + if(int_src_re) int_srcb[0] <= 1'b0; + else + if(crc5_err_r) int_srcb[0] <= 1'b1; + +always @(posedge wclk) + begin + int_srca[15] <= ep15_inta | ep15_intb; + int_srca[14] <= ep14_inta | ep14_intb; + int_srca[13] <= ep13_inta | ep13_intb; + int_srca[12] <= ep12_inta | ep12_intb; + int_srca[11] <= ep11_inta | ep11_intb; + int_srca[10] <= ep10_inta | ep10_intb; + int_srca[09] <= ep9_inta | ep9_intb; + int_srca[08] <= ep8_inta | ep8_intb; + int_srca[07] <= ep7_inta | ep7_intb; + int_srca[06] <= ep6_inta | ep6_intb; + int_srca[05] <= ep5_inta | ep5_intb; + int_srca[04] <= ep4_inta | ep4_intb; + int_srca[03] <= ep3_inta | ep3_intb; + int_srca[02] <= ep2_inta | ep2_intb; + int_srca[01] <= ep1_inta | ep1_intb; + int_srca[00] <= ep0_inta | ep0_intb; + end + +assign inta_ep =ep0_inta | ep1_inta | ep2_inta | ep3_inta | + ep4_inta | ep5_inta | ep6_inta | ep7_inta | + ep8_inta | ep9_inta | ep10_inta | ep11_inta | + ep12_inta | ep13_inta | ep14_inta | ep15_inta; + +assign intb_ep =ep0_intb | ep1_intb | ep2_intb | ep3_intb | + ep4_intb | ep5_intb | ep6_intb | ep7_intb | + ep8_intb | ep9_intb | ep10_intb | ep11_intb | + ep12_intb | ep13_intb | ep14_intb | ep15_intb; + +assign inta_rf = |(int_srcb & inta_msk); +assign intb_rf = |(int_srcb & intb_msk); + +always @(posedge wclk) + inta <= inta_ep | inta_rf; + +always @(posedge wclk) + intb <= intb_ep | intb_rf; + +/////////////////////////////////////////////////////////////////// +// +// Endpoint Register Files +// + +usbf_ep_rf u0( + .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep0_re ), + .we( ep0_we ), + .din( din ), + .dout( ep0_dout ), + .inta( ep0_inta ), + .intb( ep0_intb ), + .dma_req( dma_req[0] ), + .dma_ack( dma_ack[0] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep0_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep0_csr ), + .buf0( ep0_buf0 ), + .buf1( ep0_buf1 ), + .dma_in_buf_sz1( ep0_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep0_dma_out_buf_avail ) + ); + +`ifdef USBF_HAVE_EP1 +usbf_ep_rf u1( + .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep1_re ), + .we( ep1_we ), + .din( din ), + .dout( ep1_dout ), + .inta( ep1_inta ), + .intb( ep1_intb ), + .dma_req( dma_req[1] ), + .dma_ack( dma_ack[1] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep1_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep1_csr ), + .buf0( ep1_buf0 ), + .buf1( ep1_buf1 ), + .dma_in_buf_sz1( ep1_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep1_dma_out_buf_avail ) + ); + +`else +usbf_ep_rf_dummy u1( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep1_re ), + .we( ep1_we ), + .din( din ), + .dout( ep1_dout ), + .inta( ep1_inta ), + .intb( ep1_intb ), + .dma_req( dma_req[1] ), + .dma_ack( dma_ack[1] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep1_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep1_csr ), + .buf0( ep1_buf0 ), + .buf1( ep1_buf1 ), + .dma_in_buf_sz1( ep1_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep1_dma_out_buf_avail ) + ); +`endif + +`ifdef USBF_HAVE_EP2 +usbf_ep_rf u2( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep2_re ), + .we( ep2_we ), + .din( din ), + .dout( ep2_dout ), + .inta( ep2_inta ), + .intb( ep2_intb ), + .dma_req( dma_req[2] ), + .dma_ack( dma_ack[2] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep2_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep2_csr ), + .buf0( ep2_buf0 ), + .buf1( ep2_buf1 ), + .dma_in_buf_sz1( ep2_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep2_dma_out_buf_avail ) + ); + +`else +usbf_ep_rf_dummy u2( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep2_re ), + .we( ep2_we ), + .din( din ), + .dout( ep2_dout ), + .inta( ep2_inta ), + .intb( ep2_intb ), + .dma_req( dma_req[2] ), + .dma_ack( dma_ack[2] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep2_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep2_csr ), + .buf0( ep2_buf0 ), + .buf1( ep2_buf1 ), + .dma_in_buf_sz1( ep2_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep2_dma_out_buf_avail ) + ); +`endif + +`ifdef USBF_HAVE_EP3 +usbf_ep_rf u3( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep3_re ), + .we( ep3_we ), + .din( din ), + .dout( ep3_dout ), + .inta( ep3_inta ), + .intb( ep3_intb ), + .dma_req( dma_req[3] ), + .dma_ack( dma_ack[3] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep3_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep3_csr ), + .buf0( ep3_buf0 ), + .buf1( ep3_buf1 ), + .dma_in_buf_sz1( ep3_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep3_dma_out_buf_avail ) + ); + +`else +usbf_ep_rf_dummy u3( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep3_re ), + .we( ep3_we ), + .din( din ), + .dout( ep3_dout ), + .inta( ep3_inta ), + .intb( ep3_intb ), + .dma_req( dma_req[3] ), + .dma_ack( dma_ack[3] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep3_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep3_csr ), + .buf0( ep3_buf0 ), + .buf1( ep3_buf1 ), + .dma_in_buf_sz1( ep3_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep3_dma_out_buf_avail ) + ); +`endif + +`ifdef USBF_HAVE_EP4 +usbf_ep_rf u4( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep4_re ), + .we( ep4_we ), + .din( din ), + .dout( ep4_dout ), + .inta( ep4_inta ), + .intb( ep4_intb ), + .dma_req( dma_req[4] ), + .dma_ack( dma_ack[4] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep4_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep4_csr ), + .buf0( ep4_buf0 ), + .buf1( ep4_buf1 ), + .dma_in_buf_sz1( ep4_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep4_dma_out_buf_avail ) + ); + +`else +usbf_ep_rf_dummy u4( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep4_re ), + .we( ep4_we ), + .din( din ), + .dout( ep4_dout ), + .inta( ep4_inta ), + .intb( ep4_intb ), + .dma_req( dma_req[4] ), + .dma_ack( dma_ack[4] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep4_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep4_csr ), + .buf0( ep4_buf0 ), + .buf1( ep4_buf1 ), + .dma_in_buf_sz1( ep4_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep4_dma_out_buf_avail ) + ); +`endif + +`ifdef USBF_HAVE_EP5 +usbf_ep_rf u5( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep5_re ), + .we( ep5_we ), + .din( din ), + .dout( ep5_dout ), + .inta( ep5_inta ), + .intb( ep5_intb ), + .dma_req( dma_req[5] ), + .dma_ack( dma_ack[5] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep5_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep5_csr ), + .buf0( ep5_buf0 ), + .buf1( ep5_buf1 ), + .dma_in_buf_sz1( ep5_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep5_dma_out_buf_avail ) + ); + +`else +usbf_ep_rf_dummy u5( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep5_re ), + .we( ep5_we ), + .din( din ), + .dout( ep5_dout ), + .inta( ep5_inta ), + .intb( ep5_intb ), + .dma_req( dma_req[5] ), + .dma_ack( dma_ack[5] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep5_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep5_csr ), + .buf0( ep5_buf0 ), + .buf1( ep5_buf1 ), + .dma_in_buf_sz1( ep5_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep5_dma_out_buf_avail ) + ); +`endif + +`ifdef USBF_HAVE_EP6 +usbf_ep_rf u6( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep6_re ), + .we( ep6_we ), + .din( din ), + .dout( ep6_dout ), + .inta( ep6_inta ), + .intb( ep6_intb ), + .dma_req( dma_req[6] ), + .dma_ack( dma_ack[6] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep6_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep6_csr ), + .buf0( ep6_buf0 ), + .buf1( ep6_buf1 ), + .dma_in_buf_sz1( ep6_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep6_dma_out_buf_avail ) + ); + +`else +usbf_ep_rf_dummy u6( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep6_re ), + .we( ep6_we ), + .din( din ), + .dout( ep6_dout ), + .inta( ep6_inta ), + .intb( ep6_intb ), + .dma_req( dma_req[6] ), + .dma_ack( dma_ack[6] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep6_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep6_csr ), + .buf0( ep6_buf0 ), + .buf1( ep6_buf1 ), + .dma_in_buf_sz1( ep6_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep6_dma_out_buf_avail ) + ); +`endif + +`ifdef USBF_HAVE_EP7 +usbf_ep_rf u7( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep7_re ), + .we( ep7_we ), + .din( din ), + .dout( ep7_dout ), + .inta( ep7_inta ), + .intb( ep7_intb ), + .dma_req( dma_req[7] ), + .dma_ack( dma_ack[7] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep7_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep7_csr ), + .buf0( ep7_buf0 ), + .buf1( ep7_buf1 ), + .dma_in_buf_sz1( ep7_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep7_dma_out_buf_avail ) + ); + +`else +usbf_ep_rf_dummy u7( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep7_re ), + .we( ep7_we ), + .din( din ), + .dout( ep7_dout ), + .inta( ep7_inta ), + .intb( ep7_intb ), + .dma_req( dma_req[7] ), + .dma_ack( dma_ack[7] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep7_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep7_csr ), + .buf0( ep7_buf0 ), + .buf1( ep7_buf1 ), + .dma_in_buf_sz1( ep7_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep7_dma_out_buf_avail ) + ); +`endif + +`ifdef USBF_HAVE_EP8 +usbf_ep_rf u8( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep8_re ), + .we( ep8_we ), + .din( din ), + .dout( ep8_dout ), + .inta( ep8_inta ), + .intb( ep8_intb ), + .dma_req( dma_req[8] ), + .dma_ack( dma_ack[8] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep8_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep8_csr ), + .buf0( ep8_buf0 ), + .buf1( ep8_buf1 ), + .dma_in_buf_sz1( ep8_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep8_dma_out_buf_avail ) + ); + +`else +usbf_ep_rf_dummy u8( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep8_re ), + .we( ep8_we ), + .din( din ), + .dout( ep8_dout ), + .inta( ep8_inta ), + .intb( ep8_intb ), + .dma_req( dma_req[8] ), + .dma_ack( dma_ack[8] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep8_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep8_csr ), + .buf0( ep8_buf0 ), + .buf1( ep8_buf1 ), + .dma_in_buf_sz1( ep8_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep8_dma_out_buf_avail ) + ); +`endif + +`ifdef USBF_HAVE_EP9 +usbf_ep_rf u9( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep9_re ), + .we( ep9_we ), + .din( din ), + .dout( ep9_dout ), + .inta( ep9_inta ), + .intb( ep9_intb ), + .dma_req( dma_req[9] ), + .dma_ack( dma_ack[9] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep9_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep9_csr ), + .buf0( ep9_buf0 ), + .buf1( ep9_buf1 ), + .dma_in_buf_sz1( ep9_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep9_dma_out_buf_avail ) + ); + +`else +usbf_ep_rf_dummy u9( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep9_re ), + .we( ep9_we ), + .din( din ), + .dout( ep9_dout ), + .inta( ep9_inta ), + .intb( ep9_intb ), + .dma_req( dma_req[9] ), + .dma_ack( dma_ack[9] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep9_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep9_csr ), + .buf0( ep9_buf0 ), + .buf1( ep9_buf1 ), + .dma_in_buf_sz1( ep9_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep9_dma_out_buf_avail ) + ); +`endif + +`ifdef USBF_HAVE_EP10 +usbf_ep_rf u10( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep10_re ), + .we( ep10_we ), + .din( din ), + .dout( ep10_dout ), + .inta( ep10_inta ), + .intb( ep10_intb ), + .dma_req( dma_req[10] ), + .dma_ack( dma_ack[10] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep10_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep10_csr ), + .buf0( ep10_buf0 ), + .buf1( ep10_buf1 ), + .dma_in_buf_sz1( ep10_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep10_dma_out_buf_avail ) + ); + +`else +usbf_ep_rf_dummy u10( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep10_re ), + .we( ep10_we ), + .din( din ), + .dout( ep10_dout ), + .inta( ep10_inta ), + .intb( ep10_intb ), + .dma_req( dma_req[10] ), + .dma_ack( dma_ack[10] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep10_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep10_csr ), + .buf0( ep10_buf0 ), + .buf1( ep10_buf1 ), + .dma_in_buf_sz1( ep10_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep10_dma_out_buf_avail ) + ); +`endif + +`ifdef USBF_HAVE_EP11 +usbf_ep_rf u11( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep11_re ), + .we( ep11_we ), + .din( din ), + .dout( ep11_dout ), + .inta( ep11_inta ), + .intb( ep11_intb ), + .dma_req( dma_req[11] ), + .dma_ack( dma_ack[11] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep11_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep11_csr ), + .buf0( ep11_buf0 ), + .buf1( ep11_buf1 ), + .dma_in_buf_sz1( ep11_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep11_dma_out_buf_avail ) + ); + +`else +usbf_ep_rf_dummy u11( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep11_re ), + .we( ep11_we ), + .din( din ), + .dout( ep11_dout ), + .inta( ep11_inta ), + .intb( ep11_intb ), + .dma_req( dma_req[11] ), + .dma_ack( dma_ack[11] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep11_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep11_csr ), + .buf0( ep11_buf0 ), + .buf1( ep11_buf1 ), + .dma_in_buf_sz1( ep11_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep11_dma_out_buf_avail ) + ); +`endif + +`ifdef USBF_HAVE_EP12 +usbf_ep_rf u12( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep12_re ), + .we( ep12_we ), + .din( din ), + .dout( ep12_dout ), + .inta( ep12_inta ), + .intb( ep12_intb ), + .dma_req( dma_req[12] ), + .dma_ack( dma_ack[12] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep12_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep12_csr ), + .buf0( ep12_buf0 ), + .buf1( ep12_buf1 ), + .dma_in_buf_sz1( ep12_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep12_dma_out_buf_avail ) + ); + +`else +usbf_ep_rf_dummy u12( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep12_re ), + .we( ep12_we ), + .din( din ), + .dout( ep12_dout ), + .inta( ep12_inta ), + .intb( ep12_intb ), + .dma_req( dma_req[12] ), + .dma_ack( dma_ack[12] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep12_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep12_csr ), + .buf0( ep12_buf0 ), + .buf1( ep12_buf1 ), + .dma_in_buf_sz1( ep12_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep12_dma_out_buf_avail ) + ); +`endif + +`ifdef USBF_HAVE_EP13 +usbf_ep_rf u13( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep13_re ), + .we( ep13_we ), + .din( din ), + .dout( ep13_dout ), + .inta( ep13_inta ), + .intb( ep13_intb ), + .dma_req( dma_req[13] ), + .dma_ack( dma_ack[13] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep13_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep13_csr ), + .buf0( ep13_buf0 ), + .buf1( ep13_buf1 ), + .dma_in_buf_sz1( ep13_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep13_dma_out_buf_avail ) + ); + +`else +usbf_ep_rf_dummy u13( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep13_re ), + .we( ep13_we ), + .din( din ), + .dout( ep13_dout ), + .inta( ep13_inta ), + .intb( ep13_intb ), + .dma_req( dma_req[13] ), + .dma_ack( dma_ack[13] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep13_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep13_csr ), + .buf0( ep13_buf0 ), + .buf1( ep13_buf1 ), + .dma_in_buf_sz1( ep13_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep13_dma_out_buf_avail ) + ); +`endif + +`ifdef USBF_HAVE_EP14 +usbf_ep_rf u14( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep14_re ), + .we( ep14_we ), + .din( din ), + .dout( ep14_dout ), + .inta( ep14_inta ), + .intb( ep14_intb ), + .dma_req( dma_req[14] ), + .dma_ack( dma_ack[14] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep14_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep14_csr ), + .buf0( ep14_buf0 ), + .buf1( ep14_buf1 ), + .dma_in_buf_sz1( ep14_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep14_dma_out_buf_avail ) + ); + +`else +usbf_ep_rf_dummy u14( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep14_re ), + .we( ep14_we ), + .din( din ), + .dout( ep14_dout ), + .inta( ep14_inta ), + .intb( ep14_intb ), + .dma_req( dma_req[14] ), + .dma_ack( dma_ack[14] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep14_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep14_csr ), + .buf0( ep14_buf0 ), + .buf1( ep14_buf1 ), + .dma_in_buf_sz1( ep14_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep14_dma_out_buf_avail ) + ); +`endif + +`ifdef USBF_HAVE_EP15 +usbf_ep_rf u15( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep15_re ), + .we( ep15_we ), + .din( din ), + .dout( ep15_dout ), + .inta( ep15_inta ), + .intb( ep15_intb ), + .dma_req( dma_req[15] ), + .dma_ack( dma_ack[15] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep15_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep15_csr ), + .buf0( ep15_buf0 ), + .buf1( ep15_buf1 ), + .dma_in_buf_sz1( ep15_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep15_dma_out_buf_avail ) + ); + +`else +usbf_ep_rf_dummy u15( .clk( clk ), + .wclk( wclk ), + .rst( rst ), + .adr( adr[1:0] ), + .re( ep15_re ), + .we( ep15_we ), + .din( din ), + .dout( ep15_dout ), + .inta( ep15_inta ), + .intb( ep15_intb ), + .dma_req( dma_req[15] ), + .dma_ack( dma_ack[15] ), + .idin( idin ), + .ep_sel( ep_sel ), + .ep_match( ep15_match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( ep15_csr ), + .buf0( ep15_buf0 ), + .buf1( ep15_buf1 ), + .dma_in_buf_sz1( ep15_dma_in_buf_sz1 ), + .dma_out_buf_avail( ep15_dma_out_buf_avail ) + ); +`endif + +endmodule + diff --git a/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_top.v b/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_top.v new file mode 100644 index 0000000..475abf4 --- /dev/null +++ b/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_top.v @@ -0,0 +1,619 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// USB function core //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/usb/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2003 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: usbf_top.v,v 1.7 2003-11-11 07:15:16 rudi Exp $ +// +// $Date: 2003-11-11 07:15:16 $ +// $Revision: 1.7 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.6 2003/10/17 02:36:57 rudi +// - Disabling bit stuffing and NRZI encoding during speed negotiation +// - Now the core can send zero size packets +// - Fixed register addresses for some of the higher endpoints +// (conversion between decimal/hex was wrong) +// - The core now does properly evaluate the function address to +// determine if the packet was intended for it. +// - Various other minor bugs and typos +// +// Revision 1.5 2001/11/04 12:22:45 rudi +// +// - Fixed previous fix (brocke something else ...) +// - Majore Synthesis cleanup +// +// Revision 1.4 2001/11/03 03:26:23 rudi +// +// - Fixed several interrupt and error condition reporting bugs +// +// Revision 1.3 2001/09/24 01:15:28 rudi +// +// Changed reset to be active high async. +// +// Revision 1.2 2001/08/10 08:48:33 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// +// Revision 1.1 2001/08/03 05:30:09 rudi +// +// +// 1) Reorganized directory structure +// +// Revision 1.2 2001/03/31 13:00:52 rudi +// +// - Added Core configuration +// - Added handling of OUT packets less than MAX_PL_SZ in DMA mode +// - Modified WISHBONE interface and sync logic +// - Moved SSRAM outside the core (added interface) +// - Many small bug fixes ... +// +// Revision 1.0 2001/03/07 09:17:12 rudi +// +// +// Changed all revisions to revision 1.0. This is because OpenCores CVS +// interface could not handle the original '0.1' revision .... +// +// Revision 0.2 2001/03/07 09:08:13 rudi +// +// Added USB control signaling (Line Status) block. Fixed some minor +// typos, added resume bit and signal. +// +// Revision 0.1.0.1 2001/02/28 08:11:40 rudi +// Initial Release +// +// + +`include "usbf_defines.v" + +module usbf_top(// WISHBONE Interface + clk_i, rst_i, wb_addr_i, wb_data_i, wb_data_o, + wb_ack_o, wb_we_i, wb_stb_i, wb_cyc_i, inta_o, intb_o, + dma_req_o, dma_ack_i, susp_o, resume_req_i, + + // UTMI Interface + phy_clk_pad_i, phy_rst_pad_o, + DataOut_pad_o, TxValid_pad_o, TxReady_pad_i, + + RxValid_pad_i, RxActive_pad_i, RxError_pad_i, + DataIn_pad_i, XcvSelect_pad_o, TermSel_pad_o, + SuspendM_pad_o, LineState_pad_i, + + OpMode_pad_o, usb_vbus_pad_i, + VControl_Load_pad_o, VControl_pad_o, VStatus_pad_i, + + // Buffer Memory Interface + sram_adr_o, sram_data_i, sram_data_o, sram_re_o, sram_we_o + + ); + +parameter SSRAM_HADR = `USBF_SSRAM_HADR; +input clk_i; +input rst_i; +input [`USBF_UFC_HADR:0] wb_addr_i; +input [31:0] wb_data_i; +output [31:0] wb_data_o; +output wb_ack_o; +input wb_we_i; +input wb_stb_i; +input wb_cyc_i; +output inta_o; +output intb_o; +output [15:0] dma_req_o; +input [15:0] dma_ack_i; +output susp_o; +input resume_req_i; + +input phy_clk_pad_i; +output phy_rst_pad_o; + +output [7:0] DataOut_pad_o; +output TxValid_pad_o; +input TxReady_pad_i; + +input [7:0] DataIn_pad_i; +input RxValid_pad_i; +input RxActive_pad_i; +input RxError_pad_i; + +output XcvSelect_pad_o; +output TermSel_pad_o; +output SuspendM_pad_o; +input [1:0] LineState_pad_i; +output [1:0] OpMode_pad_o; +input usb_vbus_pad_i; +output VControl_Load_pad_o; +output [3:0] VControl_pad_o; +input [7:0] VStatus_pad_i; + +output [SSRAM_HADR:0] sram_adr_o; +input [31:0] sram_data_i; +output [31:0] sram_data_o; +output sram_re_o; +output sram_we_o; + +/////////////////////////////////////////////////////////////////// +// +// Local Wires and Registers +// + +// UTMI Interface +wire [7:0] rx_data; +wire rx_valid, rx_active, rx_err; +wire [7:0] tx_data; +wire tx_valid; +wire tx_ready; +wire tx_first; +wire tx_valid_last; + +// Misc UTMI USB status +wire mode_hs; // High Speed Mode +wire usb_reset; // USB Reset +wire usb_suspend; // USB Sleep +wire usb_attached; // Attached to USB +wire resume_req; // Resume Request + +// Memory Arbiter Interface +wire [SSRAM_HADR:0] madr; // word address +wire [31:0] mdout; +wire [31:0] mdin; +wire mwe; +wire mreq; +wire mack; +wire rst; + +// Wishbone Memory interface +wire [`USBF_UFC_HADR:0] ma_adr; +wire [31:0] ma2wb_d; +wire [31:0] wb2ma_d; +wire ma_we; +wire ma_req; +wire ma_ack; + +// WISHBONE Register File interface +wire rf_re; +wire rf_we; +wire [31:0] wb2rf_d; +wire [31:0] rf2wb_d; + +// Internal Register File Interface +wire [6:0] funct_adr; // This functions address (set by controller) +wire [31:0] idin; // Data Input +wire [3:0] ep_sel; // Endpoint Number Input +wire match; // Endpoint Matched +wire dma_in_buf_sz1; +wire dma_out_buf_avail; +wire buf0_rl; // Reload Buf 0 with original values +wire buf0_set; // Write to buf 0 +wire buf1_set; // Write to buf 1 +wire uc_bsel_set; // Write to the uc_bsel field +wire uc_dpd_set; // Write to the uc_dpd field +wire int_buf1_set; // Set buf1 full/empty interrupt +wire int_buf0_set; // Set buf0 full/empty interrupt +wire int_upid_set; // Set unsupported PID interrupt +wire int_crc16_set; // Set CRC16 error interrupt +wire int_to_set; // Set time out interrupt +wire int_seqerr_set; // Set PID sequence error interrupt +wire out_to_small; // OUT packet was to small for DMA operation +wire [31:0] csr; // Internal CSR Output +wire [31:0] buf0; // Internal Buf 0 Output +wire [31:0] buf1; // Internal Buf 1 Output +wire [31:0] frm_nat; // Frame Number and Time Register +wire nse_err; // No Such Endpoint Error +wire pid_cs_err; // PID CS error +wire crc5_err; // CRC5 Error +wire rf_resume_req; // Resume Request From main CSR + +reg susp_o; +reg [1:0] LineState_r; // Added to make a full synchronizer +reg [7:0] VStatus_r; // Added to make a full synchronizer + +/////////////////////////////////////////////////////////////////// +// +// Misc Logic +// +assign rst = rst_i; +assign phy_rst_pad_o = rst_i; +assign resume_req = resume_req_i; + +always @(posedge clk_i) + susp_o <= usb_suspend; + +always @(posedge phy_clk_pad_i) // First Stage Synchronizer + LineState_r <= LineState_pad_i; + +always @(posedge phy_clk_pad_i) // First Stage Synchronizer + VStatus_r <= VStatus_pad_i; + +/////////////////////////////////////////////////////////////////// +// +// Module Instantiations +// + +reg resume_req_r; +reg suspend_clr_wr; +wire suspend_clr; + +always @(posedge clk_i) + suspend_clr_wr <= suspend_clr; + +`ifdef USBF_ASYNC_RESET +always @(posedge clk_i or negedge rst) +`else +always @(posedge clk_i) +`endif + if(!rst) resume_req_r <= 1'b0; + else + if(suspend_clr_wr) resume_req_r <= 1'b0; + else + if(resume_req) resume_req_r <= 1'b1; + + +// UTMI Interface +usbf_utmi_if u0( + .phy_clk( phy_clk_pad_i ), + .rst( rst ), + .DataOut( DataOut_pad_o ), + .TxValid( TxValid_pad_o ), + .TxReady( TxReady_pad_i ), + .RxValid( RxValid_pad_i ), + .RxActive( RxActive_pad_i ), + .RxError( RxError_pad_i ), + .DataIn( DataIn_pad_i ), + .XcvSelect( XcvSelect_pad_o ), + .TermSel( TermSel_pad_o ), + .SuspendM( SuspendM_pad_o ), + .LineState( LineState_pad_i ), + .OpMode( OpMode_pad_o ), + .usb_vbus( usb_vbus_pad_i ), + .rx_data( rx_data ), + .rx_valid( rx_valid ), + .rx_active( rx_active ), + .rx_err( rx_err ), + .tx_data( tx_data ), + .tx_valid( tx_valid ), + .tx_valid_last( tx_valid_last ), + .tx_ready( tx_ready ), + .tx_first( tx_first ), + .mode_hs( mode_hs ), + .usb_reset( usb_reset ), + .usb_suspend( usb_suspend ), + .usb_attached( usb_attached ), + .resume_req( resume_req_r ), + .suspend_clr( suspend_clr ) + ); + +// Protocol Layer +usbf_pl #(SSRAM_HADR) + u1( .clk( phy_clk_pad_i ), + .rst( rst ), + .rx_data( rx_data ), + .rx_valid( rx_valid ), + .rx_active( rx_active ), + .rx_err( rx_err ), + .tx_data( tx_data ), + .tx_valid( tx_valid ), + .tx_valid_last( tx_valid_last ), + .tx_ready( tx_ready ), + .tx_first( tx_first ), + .tx_valid_out( TxValid_pad_o ), + .mode_hs( mode_hs ), + .usb_reset( usb_reset ), + .usb_suspend( usb_suspend ), + .usb_attached( usb_attached ), + .madr( madr ), + .mdout( mdout ), + .mdin( mdin ), + .mwe( mwe ), + .mreq( mreq ), + .mack( mack ), + .fa( funct_adr ), + .dma_in_buf_sz1( dma_in_buf_sz1 ), + .dma_out_buf_avail( dma_out_buf_avail ), + .idin( idin ), + .ep_sel( ep_sel ), + .match( match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( csr ), + .buf0( buf0 ), + .buf1( buf1 ), + .frm_nat( frm_nat ), + .pid_cs_err( pid_cs_err ), + .nse_err( nse_err ), + .crc5_err( crc5_err ) + ); + +// Memory Arbiter +usbf_mem_arb #(SSRAM_HADR) + u2( .phy_clk( phy_clk_pad_i ), + .wclk( clk_i ), + .rst( rst ), + + .sram_adr( sram_adr_o ), + .sram_din( sram_data_i ), + .sram_dout( sram_data_o ), + .sram_re( sram_re_o ), + .sram_we( sram_we_o ), + + .madr( madr ), + .mdout( mdin ), + .mdin( mdout ), + .mwe( mwe ), + .mreq( mreq ), + .mack( mack ), + + .wadr( ma_adr[SSRAM_HADR + 2:2] ), + .wdout( ma2wb_d ), + .wdin( wb2ma_d ), + .wwe( ma_we ), + .wreq( ma_req ), + .wack( ma_ack ) + ); + +// Register File +usbf_rf u4( .clk( phy_clk_pad_i ), + .wclk( clk_i ), + .rst( rst ), + + .adr( ma_adr[8:2] ), + .re( rf_re ), + .we( rf_we ), + .din( wb2rf_d ), + .dout( rf2wb_d ), + + .inta( inta_o ), + .intb( intb_o ), + .dma_req( dma_req_o ), + .dma_ack( dma_ack_i ), + .idin( idin ), + .ep_sel( ep_sel ), + .match( match ), + .buf0_rl( buf0_rl ), + .buf0_set( buf0_set ), + .buf1_set( buf1_set ), + .uc_bsel_set( uc_bsel_set ), + .uc_dpd_set( uc_dpd_set ), + .int_buf1_set( int_buf1_set ), + .int_buf0_set( int_buf0_set ), + .int_upid_set( int_upid_set ), + .int_crc16_set( int_crc16_set ), + .int_to_set( int_to_set ), + .int_seqerr_set( int_seqerr_set ), + .out_to_small( out_to_small ), + .csr( csr ), + .buf0( buf0 ), + .buf1( buf1 ), + .funct_adr( funct_adr ), + .dma_in_buf_sz1( dma_in_buf_sz1 ), + .dma_out_buf_avail( dma_out_buf_avail ), + .frm_nat( frm_nat ), + .utmi_vend_stat( VStatus_r ), + .utmi_vend_ctrl( VControl_pad_o ), + .utmi_vend_wr( VControl_Load_pad_o ), + .line_stat( LineState_r ), + .usb_attached( usb_attached ), + .mode_hs( mode_hs ), + .suspend( usb_suspend ), + .attached( usb_attached ), + .usb_reset( usb_reset ), + .pid_cs_err( pid_cs_err ), + .nse_err( nse_err ), + .crc5_err( crc5_err ), + .rx_err( rx_err ), + .rf_resume_req( rf_resume_req ) + ); + + +// WISHBONE Interface +usbf_wb u5( .phy_clk( phy_clk_pad_i ), + .wb_clk( clk_i ), + .rst( rst ), + .wb_addr_i( wb_addr_i ), + .wb_data_i( wb_data_i ), + .wb_data_o( wb_data_o ), + .wb_ack_o( wb_ack_o ), + .wb_we_i( wb_we_i ), + .wb_stb_i( wb_stb_i ), + .wb_cyc_i( wb_cyc_i ), + + .ma_adr( ma_adr ), + .ma_dout( wb2ma_d ), + .ma_din( ma2wb_d ), + .ma_we( ma_we ), + .ma_req( ma_req ), + .ma_ack( ma_ack ), + + .rf_re( rf_re ), + .rf_we( rf_we ), + .rf_dout( wb2rf_d ), + .rf_din( rf2wb_d ) + ); + + +/////////////////////////////////////////////////////////////////// +// +// Initialization +// This section does not add any functionality. It is only provided +// to make sure that the core is configured properly and to provide +// configuration information for simulations. +// + +// synopsys translate_off +integer ep_cnt, ep_cnt2; +reg [15:0] ep_check; +initial + begin + $display("\n"); + ep_cnt = 1; + ep_cnt2 = 0; + ep_check = 0; + +`ifdef USBF_HAVE_EP1 + ep_cnt = ep_cnt + 1; + ep_check[ep_cnt2] = 1; +`endif +ep_cnt2 = ep_cnt2 + 1; +`ifdef USBF_HAVE_EP2 + if(!ep_check[ep_cnt2-1]) + $display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1); + ep_cnt = ep_cnt + 1; + ep_check[ep_cnt2] = 1; +`endif +ep_cnt2 = ep_cnt2 + 1; +`ifdef USBF_HAVE_EP3 + if(!ep_check[ep_cnt2-1]) + $display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1); + ep_cnt = ep_cnt + 1; + ep_check[ep_cnt2] = 1; +`endif +ep_cnt2 = ep_cnt2 + 1; +`ifdef USBF_HAVE_EP4 + if(!ep_check[ep_cnt2-1]) + $display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1); + ep_cnt = ep_cnt + 1; + ep_check[ep_cnt2] = 1; +`endif +ep_cnt2 = ep_cnt2 + 1; +`ifdef USBF_HAVE_EP5 + if(!ep_check[ep_cnt2-1]) + $display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1); + ep_cnt = ep_cnt + 1; + ep_check[ep_cnt2] = 1; +`endif +ep_cnt2 = ep_cnt2 + 1; +`ifdef USBF_HAVE_EP6 + if(!ep_check[ep_cnt2-1]) + $display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1); + ep_cnt = ep_cnt + 1; + ep_check[ep_cnt2] = 1; +`endif +ep_cnt2 = ep_cnt2 + 1; +`ifdef USBF_HAVE_EP7 + if(!ep_check[ep_cnt2-1]) + $display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1); + ep_cnt = ep_cnt + 1; + ep_check[ep_cnt2] = 1; +`endif +ep_cnt2 = ep_cnt2 + 1; +`ifdef USBF_HAVE_EP8 + if(!ep_check[ep_cnt2-1]) + $display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1); + ep_cnt = ep_cnt + 1; + ep_check[ep_cnt2] = 1; +`endif +ep_cnt2 = ep_cnt2 + 1; +`ifdef USBF_HAVE_EP9 + if(!ep_check[ep_cnt2-1]) + $display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1); + ep_cnt = ep_cnt + 1; + ep_check[ep_cnt2] = 1; +`endif +ep_cnt2 = ep_cnt2 + 1; +`ifdef USBF_HAVE_EP10 + if(!ep_check[ep_cnt2-1]) + $display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1); + ep_cnt = ep_cnt + 1; + ep_check[ep_cnt2] = 1; +`endif +ep_cnt2 = ep_cnt2 + 1; +`ifdef USBF_HAVE_EP11 + if(!ep_check[ep_cnt2-1]) + $display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1); + ep_cnt = ep_cnt + 1; + ep_check[ep_cnt2] = 1; +`endif +ep_cnt2 = ep_cnt2 + 1; +`ifdef USBF_HAVE_EP12 + if(!ep_check[ep_cnt2-1]) + $display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1); + ep_cnt = ep_cnt + 1; + ep_check[ep_cnt2] = 1; +`endif +ep_cnt2 = ep_cnt2 + 1; +`ifdef USBF_HAVE_EP13 + if(!ep_check[ep_cnt2-1]) + $display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1); + ep_cnt = ep_cnt + 1; + ep_check[ep_cnt2] = 1; +`endif +ep_cnt2 = ep_cnt2 + 1; +`ifdef USBF_HAVE_EP14 + if(!ep_check[ep_cnt2-1]) + $display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1); + ep_cnt = ep_cnt + 1; + ep_check[ep_cnt2] = 1; +`endif +ep_cnt2 = ep_cnt2 + 1; +`ifdef USBF_HAVE_EP15 + if(!ep_check[ep_cnt2-1]) + $display("ERROR: USBF_TOP: Endpoint %0d not defined but endpoint %0d defined", ep_cnt2, ep_cnt2+1); + ep_cnt = ep_cnt + 1; + ep_check[ep_cnt2] = 1; +`endif + + $display(""); + $display("INFO: USB Function core instantiated (%m)"); + $display(" Supported Endpoints: %0d (0 through %0d)",ep_cnt, ep_cnt-1); + $display(" WISHBONE Address bus size: A%0d:0", `USBF_UFC_HADR ); + $display(" SSRAM Address bus size: A%0d:0", SSRAM_HADR ); + $display(" Buffer Memory Size: %0d bytes", (1< `USBF_T1_C_2_5_US); + +always @(posedge clk) // Smaller Than 3 mS (Actual Time will be 0-2.9375mS) + T1_st_3_0_mS <= !idle_cnt_clr & (idle_cnt1 < `USBF_T1_C_3_0_MS); + +always @(posedge clk) // Greater Than 3 mS (Actual Time will be T0+3.0625mS) + T1_gt_3_0_mS <= !idle_cnt_clr & (idle_cnt1 > `USBF_T1_C_3_0_MS); + +always @(posedge clk) // Greater Than 3.125 mS (Actual Time will be T0+3.1875uS) + T1_gt_3_125_mS <= !idle_cnt_clr & (idle_cnt1 > `USBF_T1_C_3_125_MS); + +always @(posedge clk) // Greater Than 3.125 mS (Actual Time will be T0+3.1875uS) + T1_gt_5_0_mS <= !idle_cnt_clr & (idle_cnt1 > `USBF_T1_C_5_MS); + +// --------------------------------------------------------- +// Misc Events Counter + +// Pre-scaler - 2.5uS +always @(posedge clk) + if(me_cnt_clr || me_ps_2_5_us) me_ps <= 8'h0; + else me_ps <= me_ps + 8'h1; + +always @(posedge clk) // Generate a pulse every 2.5 uS + me_ps_2_5_us <= (me_ps == `USBF_T2_C_2_5_US); + +// Second Pre-scaler - 0.5mS +always @(posedge clk) + if(me_cnt_clr || me_ps2_0_5_ms ) me_ps2 <= 8'h0; + else + if(me_ps_2_5_us) me_ps2 <= me_ps2 + 8'h1; + +always @(posedge clk) // Generate a pulse every 0.5 mS + me_ps2_0_5_ms <= (me_ps2 == `USBF_T2_C_0_5_MS) & !me_ps2_0_5_ms; + +// final misc Counter +always @(posedge clk) + if(me_cnt_clr) me_cnt <= 8'h0; + else + if(!me_cnt_100_ms && me_ps2_0_5_ms) me_cnt <= me_cnt + 8'h1; + +always @(posedge clk) // Indicate when 100uS have passed + T2_gt_100_uS <= !me_cnt_clr & (me_ps2 > `USBF_T2_C_100_US); // Actual Time: 102.5 uS + +always @(posedge clk) // Indicate when wakeup period has passed + T2_wakeup <= !me_cnt_clr & (me_cnt > `USBF_T2_C_WAKEUP); + +always @(posedge clk) // Indicate when 1 mS has passed + T2_gt_1_0_mS <= !me_cnt_clr & (me_cnt > `USBF_T2_C_1_0_MS); // Actual Time: 1.5 mS + +always @(posedge clk) // Indicate when 1.2 mS has passed + T2_gt_1_2_mS <= !me_cnt_clr & (me_cnt > `USBF_T2_C_1_2_MS); // Actual Time: 1.5 mS + +always @(posedge clk) // Generate a pulse after 100 mS + me_cnt_100_ms <= !me_cnt_clr & (me_cnt == `USBF_T2_C_100_MS); // Actual Time: 100 mS + +// --------------------------------------------------------- +// Chirp Counter + +always @(posedge clk) + if(chirp_cnt_clr) chirp_cnt <= 3'h0; + else + if(chirp_cnt_inc) chirp_cnt <= chirp_cnt + 3'h1; + +always @(posedge clk) + chirp_cnt_is_6 <= (chirp_cnt == 3'h6); + +/////////////////////////////////////////////////////////////////// +// +// Main State Machine +// + +`ifdef USBF_ASYNC_RESET +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) state <= POR; + else + if(usb_vbus) state <= POR; + else state <= next_state; + +always @(state or mode_hs or idle_long or resume_req_s or me_cnt_100_ms or + j_long or k_long or se0_long or ls_se0 or + T1_gt_2_5_uS or T1_st_3_0_mS or T1_gt_3_0_mS or + T1_gt_5_0_mS or T2_gt_100_uS or T2_wakeup or T2_gt_1_0_mS or + T2_gt_1_2_mS or chirp_cnt_is_6) + begin + next_state = state; // Default don't change state + + mode_set_hs = 1'b0; + mode_set_fs = 1'b0; + suspend_set = 1'b0; + suspend_clr = 1'b0; + attached_set = 1'b0; + attached_clr = 1'b0; + usb_reset_d = 1'b0; + + fs_term_on = 1'b0; + fs_term_off = 1'b0; + xcv_set_hs = 1'b0; + xcv_set_fs = 1'b0; + bit_stuff_on = 1'b0; + bit_stuff_off = 1'b0; + + idle_cnt_clr = 1'b0; + me_cnt_clr = 1'b0; + drive_k_d = 1'b0; + chirp_cnt_clr = 1'b0; + chirp_cnt_inc = 1'b0; + + case(state) // synopsys full_case parallel_case + POR: // Power On/Reset + begin + me_cnt_clr = 1'b1; + xcv_set_fs = 1'b1; + fs_term_on = 1'b1; + mode_set_fs = 1'b1; + attached_clr = 1'b1; + bit_stuff_on = 1'b0; + suspend_clr = 1'b1; + next_state = ATTACH; + end + + NORMAL: // Normal Operation + begin + if(!mode_hs && T1_gt_2_5_uS && T1_st_3_0_mS && !idle_long) + begin + me_cnt_clr = 1'b1; + next_state = RESET; + end + else + if(!mode_hs && T1_gt_3_0_mS) + begin + idle_cnt_clr = 1'b1; + suspend_set = 1'b1; + next_state = SUSPEND; + end + else + if(mode_hs && T1_gt_3_0_mS) + begin // Switch to FS mode, and decide + // if it's a RESET or SUSPEND + me_cnt_clr = 1'b1; + xcv_set_fs = 1'b1; + fs_term_on = 1'b1; + next_state = RES_SUSP; + end + end + + RES_SUSP: // Decide if it's a Reset or Suspend Signaling + begin // We are now in FS mode, wait 100uS first + if(T2_gt_100_uS && se0_long) + begin + me_cnt_clr = 1'b1; + next_state = RESET; + end + else + if(T2_gt_100_uS && j_long) + begin + idle_cnt_clr = 1'b1; + suspend_set = 1'b1; + next_state = SUSPEND; + end + end + + SUSPEND: // In Suspend + begin + if(T1_gt_2_5_uS && se0_long) + begin + suspend_clr = 1'b1; + me_cnt_clr = 1'b1; + next_state = RESET; + end + else + if(k_long) // Start Resuming + next_state = RESUME; + else + if(T1_gt_5_0_mS && resume_req_s) + next_state = RESUME_REQUEST; + end + + RESUME: + begin + suspend_clr = 1'b1; + if(ls_se0) + begin + if(mode_hs) + begin // Switch Back to HS mode + xcv_set_hs = 1'b1; + fs_term_off = 1'b1; + end + bit_stuff_on = 1'b1; // Enable Bit Stuffing and NRZI encoding + me_cnt_clr = 1'b1; + next_state = RESUME_WAIT; + end + end + + RESUME_WAIT: + begin + if(T2_gt_100_uS) next_state = NORMAL; + end + + RESUME_REQUEST: // Function Resume Request + begin + suspend_clr = 1'b1; + // Wait for internal wake up + if(T2_wakeup) + begin + fs_term_on = 1'b1; // Switch Termination to Full Speed + bit_stuff_off = 1'b1; // disable Bit Stuffing and NRZI encoding + me_cnt_clr = 1'b1; + next_state = RESUME_SIG; + end + end + + RESUME_SIG: // Signal resume + begin + // Drive Resume ('K') for 1-15 mS + drive_k_d = 1'b1; + // Stop driving after 1.5 mS + if(T2_gt_1_0_mS) next_state = RESUME; + end + + ATTACH: // Attach To USB Detected + begin + idle_cnt_clr = 1'b1; + if(me_cnt_100_ms) + //if(me_cnt_100_ms && j_long) + begin + attached_set = 1'b1; + next_state = NORMAL; + end + /* + if(me_cnt_100_ms && se0_long) + begin + attached_set = 1'b1; + me_cnt_clr = 1'b1; + next_state = RESET; + end + */ + end + + RESET: // In Reset + begin + usb_reset_d = 1'b1; // Assert Internal USB Reset + xcv_set_hs = 1'b1; // Switch xcvr to HS mode + fs_term_on = 1'b1; // Turn FS termination On + mode_set_fs = 1'b1; // Change mode to FS + bit_stuff_off = 1'b1; // disable Bit Stuffing and NRZI encoding + // Get out of reset after 1.5 mS + if(T2_gt_1_0_mS) + begin + me_cnt_clr = 1'b1; + next_state = SPEED_NEG; + end + end + + SPEED_NEG: // Speed Negotiation + begin + drive_k_d = 1'b1; + chirp_cnt_clr = 1'b1; + // Start looking for 'K' after 1.5 mS + if(T2_gt_1_2_mS) next_state = SPEED_NEG_K; + end + + SPEED_NEG_K: + begin + if(chirp_cnt_is_6) next_state = SPEED_NEG_HS; + else + begin + if(k_long) + begin + chirp_cnt_inc = 1'b1; + next_state = SPEED_NEG_J; + end + if(se0_long) + next_state = SPEED_NEG_FS; + end + end + + SPEED_NEG_J: + begin + if(chirp_cnt_is_6) next_state = SPEED_NEG_HS; + else + begin + if(j_long) + begin + chirp_cnt_inc = 1'b1; + next_state = SPEED_NEG_K; + end + if(se0_long) + next_state = SPEED_NEG_FS; + end + end + + SPEED_NEG_HS: + begin + bit_stuff_on = 1'b1; // Enable Bit Stuffing and NRZI encoding + xcv_set_hs = 1'b1; // Switch xcvr to HS mode + fs_term_off = 1'b1; // Turn FS termination Off + mode_set_hs = 1'b1; // Change mode to HS + if(se0_long) next_state = NORMAL; + end + + SPEED_NEG_FS: + begin + bit_stuff_on = 1'b1; // Enable Bit Stuffing and NRZI encoding + xcv_set_fs = 1'b1; // Switch xcvr to FS mode + fs_term_on = 1'b1; // Turn FS termination On + mode_set_fs = 1'b1; // Change mode to FS + next_state = NORMAL; + end + + endcase + end + +endmodule + diff --git a/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_wb.v b/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_wb.v new file mode 100644 index 0000000..36d772d --- /dev/null +++ b/demo_chip_rtl/rtl/usb/trunk/rtl/verilog/usbf_wb.v @@ -0,0 +1,273 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Interface //// +//// This is the external bus interface, that is WISHBONE //// +//// SoC compliant. //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/usb/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2003 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: usbf_wb.v,v 1.4 2003-10-17 02:36:57 rudi Exp $ +// +// $Date: 2003-10-17 02:36:57 $ +// $Revision: 1.4 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.3 2001/09/24 01:15:28 rudi +// +// Changed reset to be active high async. +// +// Revision 1.2 2001/08/10 08:48:33 rudi +// +// - Changed IO names to be more clear. +// - Uniquifyed define names to be core specific. +// +// Revision 1.1 2001/08/03 05:30:09 rudi +// +// +// 1) Reorganized directory structure +// +// Revision 1.2 2001/03/31 13:00:52 rudi +// +// - Added Core configuration +// - Added handling of OUT packets less than MAX_PL_SZ in DMA mode +// - Modified WISHBONE interface and sync logic +// - Moved SSRAM outside the core (added interface) +// - Many small bug fixes ... +// +// Revision 1.0 2001/03/07 09:17:12 rudi +// +// +// Changed all revisions to revision 1.0. This is because OpenCores CVS +// interface could not handle the original '0.1' revision .... +// +// Revision 0.1.0.1 2001/02/28 08:11:47 rudi +// Initial Release +// +// + +`include "usbf_defines.v" + +module usbf_wb( // WISHBONE Interface + wb_clk, phy_clk, rst, wb_addr_i, wb_data_i, wb_data_o, + wb_ack_o, wb_we_i, wb_stb_i, wb_cyc_i, + + // Memory Arbiter Interface + ma_adr, ma_dout, ma_din, ma_we, ma_req, ma_ack, + + // Register File interface + rf_re, rf_we, rf_din, rf_dout); + +input wb_clk, phy_clk; +input rst; +input [`USBF_UFC_HADR:0] wb_addr_i; +input [31:0] wb_data_i; +output [31:0] wb_data_o; +output wb_ack_o; +input wb_we_i; +input wb_stb_i; +input wb_cyc_i; + +// Memory Arbiter Interface +output [`USBF_UFC_HADR:0] ma_adr; +output [31:0] ma_dout; +input [31:0] ma_din; +output ma_we; +output ma_req; +input ma_ack; + +// Register File interface +output rf_re; +output rf_we; +input [31:0] rf_din; +output [31:0] rf_dout; + +/////////////////////////////////////////////////////////////////// +// +// Local Wires and Registers +// + +parameter [5:0] // synopsys enum state + IDLE = 6'b00_0001, + MA_WR = 6'b00_0010, + MA_RD = 6'b00_0100, + W0 = 6'b00_1000, + W1 = 6'b01_0000, + W2 = 6'b10_0000; + +reg [5:0] /* synopsys enum state */ state, next_state; +// synopsys state_vector state + +reg wb_req_s1; +reg wb_ack_d, wb_ack_s1, wb_ack_s1a, wb_ack_s2; +reg ma_we; +reg rf_re, rf_we_d; +reg ma_req; +reg wb_ack_o; +reg [31:0] wb_data_o; + +/////////////////////////////////////////////////////////////////// +// +// Interface Logic +// + +assign ma_adr = wb_addr_i; +assign ma_dout = wb_data_i; +assign rf_dout = wb_data_i; + +always @(posedge wb_clk) + if( `USBF_RF_SEL ) wb_data_o <= rf_din; + else wb_data_o <= ma_din; + +// Sync WISHBONE Request +always @(posedge phy_clk) + wb_req_s1 <= wb_stb_i & wb_cyc_i; + +// Sync WISHBONE Ack +always @(posedge wb_clk) + wb_ack_s1 <= wb_ack_d; + +always @(posedge wb_clk) + wb_ack_o <= wb_ack_s1 & !wb_ack_s2 & !wb_ack_o; + +always @(posedge wb_clk) + wb_ack_s1a <= wb_ack_s1; + +always @(posedge wb_clk) + wb_ack_s2 <= wb_ack_s1a; + +assign rf_we = rf_we_d; + +/////////////////////////////////////////////////////////////////// +// +// Interface State Machine +// + +`ifdef USBF_ASYNC_RESET +always @(posedge phy_clk or negedge rst) +`else +always @(posedge phy_clk) +`endif + if(!rst) state <= IDLE; + else state <= next_state; + +always @(state or wb_req_s1 or wb_addr_i or ma_ack or wb_we_i) + begin + next_state = state; + ma_req = 1'b0; + ma_we = 1'b0; + wb_ack_d = 1'b0; + rf_re = 1'b0; + rf_we_d = 1'b0; + + case(state) // synopsys full_case parallel_case + IDLE: + begin + if(wb_req_s1 && `USBF_MEM_SEL && wb_we_i) + begin + ma_req = 1'b1; + ma_we = 1'b1; + next_state = MA_WR; + end + if(wb_req_s1 && `USBF_MEM_SEL && !wb_we_i) + begin + ma_req = 1'b1; + next_state = MA_RD; + end + if(wb_req_s1 && `USBF_RF_SEL && wb_we_i) + begin + rf_we_d = 1'b1; + next_state = W0; + end + if(wb_req_s1 && `USBF_RF_SEL && !wb_we_i) + begin + rf_re = 1'b1; + next_state = W0; + end + end + + MA_WR: + begin + if(!ma_ack) + begin + ma_req = 1'b1; + ma_we = 1'b1; + end + else + begin + wb_ack_d = 1'b1; + next_state = W1; + end + end + + MA_RD: + begin + if(!ma_ack) + begin + ma_req = 1'b1; + end + else + begin + wb_ack_d = 1'b1; + next_state = W1; + end + end + + W0: + begin + wb_ack_d = 1'b1; + next_state = W1; + end + + W1: + begin + next_state = W2; + end + + W2: + begin + next_state = IDLE; + end + + endcase + end + +endmodule + diff --git a/demo_chip_rtl/rtl/usb/trunk/syn/bin/comp.dc b/demo_chip_rtl/rtl/usb/trunk/syn/bin/comp.dc new file mode 100644 index 0000000..3f3bb71 --- /dev/null +++ b/demo_chip_rtl/rtl/usb/trunk/syn/bin/comp.dc @@ -0,0 +1,129 @@ +############################################################################### +# +# Actual Synthesis Script +# +# This script does the actual synthesis +# +# Author: Rudolf Usselmann +# rudi@asics.ws +# +# Revision: +# 3/7/01 RU Initial Sript +# +# +############################################################################### + +# ============================================== +# Setup Design Parameters +source ../bin/design_spec.dc + +# ============================================== +# Setup Libraries +source ../bin/lib_spec.dc + +# ============================================== +# Setup File IO + +set junk_file /dev/null +append log_file ../log/$active_design "_cmp.log" +append pre_comp_db_file ../out/$design_name "_pre.db" +append post_comp_db_file ../out/$design_name ".db" +append post_syn_verilog_file ../out/$design_name "_ps.v" + +sh rm -f $log_file + +# ============================================== +# Setup Misc Variables + +set hdlin_enable_vpp true ;# Important - this enables 'ifdefs + +# Turn off automatic wire load selection, as this always (WHY ???) defaults to "zero_load" +#set auto_wire_load_selection false + +# ============================================== +# Read Design + +echo "+++++++++ Reading Design ..." >> $log_file +read_file $pre_comp_db_file >> $log_file + +# ============================================== +# Operating conditions + +echo "+++++++++ Setting up Operation Conditions ..." >> $log_file +current_design $design_name +set_operating_conditions WORST >> $log_file +#set_wire_load_mode enclosed >> $log_file +set_wire_load_mode top >> $log_file +set_wire_load_model -name suggested_40K >> $log_file + +# ============================================== +# Setup Clocks and Resets + +echo "+++++++++ Setting up Clocks ..." >> $log_file + +set_drive 0 [find port {*clk_i}] + +# !!! Phy Clock !!! +set clock_period2 16 +create_clock -period $clock_period2 phy_clk +set_clock_skew -uncertainty 0.5 phy_clk +set_clock_transition 0.9 phy_clk +set_dont_touch_network phy_clk + +# !!! WISHBONE Clock !!! +set clock_period 5 +create_clock -period $clock_period clk_i +set_clock_skew -uncertainty 0.1 clk_i +set_clock_transition 0.5 clk_i +set_dont_touch_network clk_i + +# !!! Reset !!! +set_drive 0 [find port {rst*}] +set_dont_touch_network [find port {rst*}] + +# ============================================== +# Setup IOs + +echo "+++++++++ Setting up IOs ..." >> $log_file + +# Need to spell out external IOs + +set_driving_cell -cell NAND2D2 -pin Z [all_inputs] >> $junk_file +set_load 0.2 [all_outputs] + +set_input_delay -max 1 -clock clk_i [all_inputs] +set_output_delay -max 1 -clock clk_i [all_outputs] + +set_input_delay -max 1 -clock phy_clk [all_inputs] +set_output_delay -max 1 -clock phy_clk [all_outputs] + +# ============================================== +# Setup Area Constrains +set_max_area 0.0 + +# ============================================== +# Force Ultra +set_ultra_optimization -f + +# ============================================== +# Compile Design + +echo "+++++++++ Starting Compile ..." >> $log_file +#compile -map_effort medium -area_effort medium -ungroup_all >> $log_file +compile -map_effort low -area_effort low >> $log_file +#compile -map_effort high -area_effort high -auto_ungroup >> $log_file + +# ============================================== +# Write Out the optimized design + +echo "+++++++++ Saving Optimized Design ..." >> $log_file +write_file -format verilog -output $post_syn_verilog_file +write_file -hierarchy -format db -output $post_comp_db_file + +# ============================================== +# Create Some Basic Reports + +echo "+++++++++ Reporting Final Results ..." >> $log_file +report_timing -nworst 10 >> $log_file +report_area >> $log_file + diff --git a/demo_chip_rtl/rtl/usb/trunk/syn/bin/design_spec.dc b/demo_chip_rtl/rtl/usb/trunk/syn/bin/design_spec.dc new file mode 100644 index 0000000..8a06d3e --- /dev/null +++ b/demo_chip_rtl/rtl/usb/trunk/syn/bin/design_spec.dc @@ -0,0 +1,26 @@ +############################################################################### +# +# Design Specification +# +# Author: Rudolf Usselmann +# rudi@asics.ws +# +# Revision: +# 3/7/01 RU Initial Sript +# +# +############################################################################### + +# ============================================== +# Setup Design Parameters + +set design_files {usbf_crc5 usbf_crc16 usbf_mem_arb usbf_ep_rf usbf_pa usbf_ep_rf_dummy usbf_pd usbf_rf usbf_utmi_ls usbf_utmi_if usbf_idma usbf_pe usbf_wb usbf_pl usbf_top} +set design_name usbf_top +set active_design usbf_top + +# Next Statement defines all clocks and resets in the design +set special_net {rst_i clk_i phy_clk} + +# Source Directory +set hdl_src_dir ../../rtl/verilog/ + diff --git a/demo_chip_rtl/rtl/usb/trunk/syn/bin/lib_spec.dc b/demo_chip_rtl/rtl/usb/trunk/syn/bin/lib_spec.dc new file mode 100644 index 0000000..5e8ac6e --- /dev/null +++ b/demo_chip_rtl/rtl/usb/trunk/syn/bin/lib_spec.dc @@ -0,0 +1,36 @@ +############################################################################### +# +# Library Specification +# +# Author: Rudolf Usselmann +# rudi@asics.ws +# +# Revision: +# 3/7/01 RU Initial Sript +# +# +############################################################################### + +# ============================================== +# Setup Libraries + +set search_path [list $search_path . \ + /tools/dc_libraries/umc/umc_0.18/UMCL18U250D2_2.1/design_compiler/ \ + $hdl_src_dir] + +set snps [getenv "SYNOPSYS"] + +set synthetic_library "" +append synthetic_library $snps "/libraries/syn/dw01.sldb " +append synthetic_library $snps "/libraries/syn/dw02.sldb " +append synthetic_library $snps "/libraries/syn/dw03.sldb " +append synthetic_library $snps "/libraries/syn/dw04.sldb " +append synthetic_library $snps "/libraries/syn/dw05.sldb " +append synthetic_library $snps "/libraries/syn/dw06.sldb " +append synthetic_library $snps "/libraries/syn/dw07.sldb " + +set target_library { umcl18u250t2_typ.db } +set link_library "" +append link_library $target_library " " $synthetic_library +set symbol_library { umcl18u250t2.sdb } + diff --git a/demo_chip_rtl/rtl/usb/trunk/syn/bin/read.dc b/demo_chip_rtl/rtl/usb/trunk/syn/bin/read.dc new file mode 100644 index 0000000..050e3f1 --- /dev/null +++ b/demo_chip_rtl/rtl/usb/trunk/syn/bin/read.dc @@ -0,0 +1,66 @@ +############################################################################### +# +# Pre Synthesis Script +# +# This script only reads in the design and saves it in a DB file +# +# Author: Rudolf Usselmann +# rudi@asics.ws +# +# Revision: +# 3/7/01 RU Initial Sript +# +# +############################################################################### + +# ============================================== +# Setup Design Parameters +source ../bin/design_spec.dc + +# ============================================== +# Setup Libraries +source ../bin/lib_spec.dc + +# ============================================== +# Setup File IO + +append log_file ../log/$active_design "_pre.log" +append pre_comp_db_file ../out/$design_name "_pre.db" +sh rm -f $log_file + +# ============================================== +# Setup Misc Variables + +set hdlin_enable_vpp true ;# Important - this enables 'ifdefs + +# ============================================== +# Read Design + +echo "+++++++++ Analyzing all design files ..." >> $log_file + +foreach module $design_files { + echo "+++++++++ Reading: $module" >> $log_file + echo +++++++++ Reading: $module + set module_file_name "" + append module_file_name $module ".v" + analyze -f verilog $module_file_name >> $log_file + elaborate $module >> $log_file + } + +set current_design $active_design + +echo "+++++++++ Linking Design ..." >> $log_file +link >> $log_file + +echo "+++++++++ Uniquifying Design ..." >> $log_file +uniquify >> $log_file + +echo "+++++++++ Checking Design ..." >> $log_file +check_design >> $log_file + +# ============================================== +# Save Design +echo "+++++++++ Saving Design ..." >> $log_file +write_file -hierarchy -format db -output $pre_comp_db_file + + diff --git a/demo_chip_rtl/rtl/usb_phy/tags/start/doc/README.txt b/demo_chip_rtl/rtl/usb_phy/tags/start/doc/README.txt new file mode 100644 index 0000000..348c5f6 --- /dev/null +++ b/demo_chip_rtl/rtl/usb_phy/tags/start/doc/README.txt @@ -0,0 +1,67 @@ + +USB 1.1 PHY +========== + +Status +------ +This core is done. It was tested with a USB 1.1 core I have written on +a XESS XCV800 board with a a Philips PDIUSBP11A transceiver. +I have NOT yet tested it with my USB 2.0 Function IP core. + +Test Bench +---------- +There is no test bench, period ! +Please don't email me asking for one, unless you want to hire me to +write one ! As I said above I have tested this core in real hardware and +it works just fine. + +Documentation +------------- +Sorry, there is none. I just don't have the time to write it. I have tried +to follow the UTMI interface specification from USB 2.0 with one exception: +I have not added any error checking in the RX PHY, hence the RxError pin +is permanently tide to ground. + +Misc +---- +The USB 1.1 Phy Project Page is: +http://www.opencores.org/cores/usb_phy + +To find out more about me (Rudolf Usselmann), please visit: +http://www.asics.ws + + +Directory Structure +------------------- +[core_root] + | + +-doc Documentation + | + +-bench--+ Test Bench + | +- verilog Verilog Sources + | +-vhdl VHDL Sources + | + +-rtl----+ Core RTL Sources + | +-verilog Verilog Sources + | +-vhdl VHDL Sources + | + +-sim----+ + | +-rtl_sim---+ Functional verification Directory + | | +-bin Makefiles/Run Scripts + | | +-run Working Directory + | | + | +-gate_sim--+ Functional & Timing Gate Level + | | Verification Directory + | +-bin Makefiles/Run Scripts + | +-run Working Directory + | + +-lint--+ Lint Directory Tree + | +-bin Makefiles/Run Scripts + | +-run Working Directory + | +-log Linter log & result files + | + +-syn---+ Synthesis Directory Tree + | +-bin Synthesis Scripts + | +-run Working Directory + | +-log Synthesis log files + | +-out Synthesis Output diff --git a/demo_chip_rtl/rtl/usb_phy/tags/start/rtl/verilog/timescale.v b/demo_chip_rtl/rtl/usb_phy/tags/start/rtl/verilog/timescale.v new file mode 100644 index 0000000..ff9e265 --- /dev/null +++ b/demo_chip_rtl/rtl/usb_phy/tags/start/rtl/verilog/timescale.v @@ -0,0 +1 @@ +`timescale 1ns / 10ps diff --git a/demo_chip_rtl/rtl/usb_phy/tags/start/rtl/verilog/usb_phy.v b/demo_chip_rtl/rtl/usb_phy/tags/start/rtl/verilog/usb_phy.v new file mode 100644 index 0000000..e8e43c7 --- /dev/null +++ b/demo_chip_rtl/rtl/usb_phy/tags/start/rtl/verilog/usb_phy.v @@ -0,0 +1,165 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// USB 1.1 PHY //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/usb_phy/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: usb_phy.v,v 1.1.1.1 2002-09-16 14:26:59 rudi Exp $ +// +// $Date: 2002-09-16 14:26:59 $ +// $Revision: 1.1.1.1 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// +// +// +// +// +// +// + +`include "timescale.v" + +module usbf_phy(clk, rst, phy_tx_mode, usb_rst, + + // Transciever Interface + txdp, txdn, txoe, + rxd, rxdp, rxdn, + + // UTMI Interface + DataOut_i, TxValid_i, TxReady_o, RxValid_o, + RxActive_o, RxError_o, DataIn_o, LineState_o + ); + +input clk; +input rst; +input phy_tx_mode; +output usb_rst; +output txdp, txdn, txoe; +input rxd, rxdp, rxdn; +input [7:0] DataOut_i; +input TxValid_i; +output TxReady_o; +output [7:0] DataIn_o; +output RxValid_o; +output RxActive_o; +output RxError_o; +output [1:0] LineState_o; + +/////////////////////////////////////////////////////////////////// +// +// Local Wires and Registers +// + +reg [5:0] rst_cnt; +reg usb_rst; +wire reset; + +/////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +assign reset = rst & ~usb_rst; + +/////////////////////////////////////////////////////////////////// +// +// TX Phy +// + +usb_tx_phy i_tx_phy( + .clk( clk ), + .rst( reset ), + .fs_ce( fs_ce ), + .phy_mode( phy_tx_mode ), + + // Transciever Interface + .txdp( txdp ), + .txdn( txdn ), + .txoe( txoe ), + + // UTMI Interface + .DataOut_i( DataOut_i ), + .TxValid_i( TxValid_i ), + .TxReady_o( TxReady_o ) + ); + +/////////////////////////////////////////////////////////////////// +// +// RX Phy and DPLL +// + +usb_rx_phy i_rx_phy( + .clk( clk ), + .rst( reset ), + .fs_ce( fs_ce ), + + // Transciever Interface + .rxd( rxd ), + .rxdp( rxdp ), + .rxdn( rxdn ), + + // UTMI Interface + .DataIn_o( DataIn_o ), + .RxValid_o( RxValid_o ), + .RxActive_o( RxActive_o ), + .RxError_o( RxError_o ), + .RxEn_i( txoe ), + .LineState( LineState_o ) + ); + +/////////////////////////////////////////////////////////////////// +// +// Generate an USB Reset is we see SE0 for at least 2.5uS +// + +always @(posedge clk) + if(!rst) rst_cnt <= #1 5'h0; + else + if(LineState_o != 2'h0) rst_cnt <= #1 5'h0; + else + if(!usb_rst & fs_ce) rst_cnt <= #1 rst_cnt + 5'h1; + +always @(posedge clk) + usb_rst <= #1 (rst_cnt == 5'd31); + +endmodule + diff --git a/demo_chip_rtl/rtl/usb_phy/tags/start/rtl/verilog/usb_rx_phy.v b/demo_chip_rtl/rtl/usb_phy/tags/start/rtl/verilog/usb_rx_phy.v new file mode 100644 index 0000000..caa62e2 --- /dev/null +++ b/demo_chip_rtl/rtl/usb_phy/tags/start/rtl/verilog/usb_rx_phy.v @@ -0,0 +1,411 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// USB 1.1 PHY //// +//// RX & DPLL //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/usb_phy/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: usb_rx_phy.v,v 1.1.1.1 2002-09-16 14:27:01 rudi Exp $ +// +// $Date: 2002-09-16 14:27:01 $ +// $Revision: 1.1.1.1 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// +// +// +// +// +// +// + +`include "timescale.v" + +module usb_rx_phy( clk, rst, fs_ce, + + // Transciever Interface + rxd, rxdp, rxdn, + + // UTMI Interface + RxValid_o, RxActive_o, RxError_o, DataIn_o, + RxEn_i, LineState); + +input clk; +input rst; +output fs_ce; +input rxd, rxdp, rxdn; +output [7:0] DataIn_o; +output RxValid_o; +output RxActive_o; +output RxError_o; +input RxEn_i; +output [1:0] LineState; + +/////////////////////////////////////////////////////////////////// +// +// Local Wires and Registers +// + +reg rxd_t1, rxd_s1, rxd_s; +reg rxdp_t1, rxdp_s1, rxdp_s; +reg rxdn_t1, rxdn_s1, rxdn_s; +reg synced_d; +wire k, j, se0; +reg rx_en; +reg rx_active; +reg [2:0] bit_cnt; +reg rx_valid1, rx_valid; +reg shift_en; +reg sd_r; +reg sd_nrzi; +reg [7:0] hold_reg; +wire drop_bit; // Indicates a stuffed bit +reg [2:0] one_cnt; + +reg [1:0] dpll_state, dpll_next_state; +reg fs_ce_d, fs_ce; +wire change; +reg rxdp_s1r, rxdn_s1r; +wire lock_en; +reg fs_ce_r1, fs_ce_r2, fs_ce_r3; +reg [2:0] fs_state, fs_next_state; +reg rx_valid_r; + +/////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +assign RxActive_o = rx_active; +assign RxValid_o = rx_valid; +assign RxError_o = 0; +assign DataIn_o = hold_reg; +assign LineState = {rxdp_s1, rxdn_s1}; + +always @(posedge clk) + rx_en <= #1 RxEn_i; + +/////////////////////////////////////////////////////////////////// +// +// Synchronize Inputs +// + +// First synchronize to the local system clock to +// avoid metastability outside the sync block (*_s1) +// Second synchronise to the internal bit clock (*_s) +always @(posedge clk) + rxd_t1 <= #1 rxd; + +always @(posedge clk) + rxd_s1 <= #1 rxd_t1; + +always @(posedge clk) + rxd_s <= #1 rxd_s1; + +always @(posedge clk) + rxdp_t1 <= #1 rxdp; + +always @(posedge clk) + rxdp_s1 <= #1 rxdp_t1; + +always @(posedge clk) + rxdp_s <= #1 rxdp_s1; + +always @(posedge clk) + rxdn_t1 <= #1 rxdn; + +always @(posedge clk) + rxdn_s1 <= #1 rxdn_t1; + +always @(posedge clk) + rxdn_s <= #1 rxdn_s1; + +assign k = !rxdp_s & rxdn_s; +assign j = rxdp_s & !rxdn_s; +assign se0 = !rxdp_s & !rxdn_s; + +/////////////////////////////////////////////////////////////////// +// +// DPLL +// + +// This design uses a clock enable to do 12Mhz timing and not a +// real 12Mhz clock. Everything always runs at 48Mhz. We want to +// make sure however, that the clock enable is always exactly in +// the middle between two virtual 12Mhz rising edges. +// We monitor rxdp and rxdn for any changes and do the appropiate +// adjustments. +// In addition to the locking done in the dpll FSM, we adjust the +// final latch enable to compensate for various sync registers ... + +// Allow lockinf only when we are receiving +assign lock_en = rx_en; + +// Edge detector +always @(posedge clk) + rxdp_s1r <= #1 rxdp_s1; + +always @(posedge clk) + rxdn_s1r <= #1 rxdn_s1; + +assign change = (rxdp_s1r != rxdp_s1) | (rxdn_s1r != rxdn_s1); + +// DPLL FSM +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) dpll_state <= #1 2'h1; + else dpll_state <= #1 dpll_next_state; + +always @(dpll_state or lock_en or change) + begin + fs_ce_d = 1'b0; + case(dpll_state) // synopsys full_case parallel_case + 2'h0: + if(lock_en & change) dpll_next_state = 3'h0; + else dpll_next_state = 3'h1; + 2'h1:begin + fs_ce_d = 1'b1; + //if(lock_en & change) dpll_next_state = 3'h0; + if(lock_en & change) dpll_next_state = 3'h3; + else dpll_next_state = 3'h2; + end + 2'h2: + if(lock_en & change) dpll_next_state = 3'h0; + else dpll_next_state = 3'h3; + 2'h3: + if(lock_en & change) dpll_next_state = 3'h0; + else dpll_next_state = 3'h0; + endcase + end + +// Compensate for sync registers at the input - allign full speed +// clock enable to be in the middle between two bit changes ... +always @(posedge clk) + fs_ce_r1 <= #1 fs_ce_d; + +always @(posedge clk) + fs_ce_r2 <= #1 fs_ce_r1; + +always @(posedge clk) + fs_ce_r3 <= #1 fs_ce_r2; + +always @(posedge clk) + fs_ce <= #1 fs_ce_r3; + +/////////////////////////////////////////////////////////////////// +// +// Find Sync Pattern FSM +// + +parameter FS_IDLE = 3'h0, + K1 = 3'h1, + J1 = 3'h2, + K2 = 3'h3, + J2 = 3'h4, + K3 = 3'h5, + J3 = 3'h6, + K4 = 3'h7; + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) fs_state <= #1 FS_IDLE; + else fs_state <= #1 fs_next_state; + +always @(fs_state or fs_ce or k or j or rx_en) + begin + synced_d = 1'b0; + fs_next_state = fs_state; + if(fs_ce) + case(fs_state) // synopsys full_case parallel_case + FS_IDLE: + begin + if(k & rx_en) fs_next_state = K1; + end + K1: + begin + if(j & rx_en) fs_next_state = J1; + else fs_next_state = FS_IDLE; + end + J1: + begin + if(k & rx_en) fs_next_state = K2; + else fs_next_state = FS_IDLE; + end + K2: + begin + if(j & rx_en) fs_next_state = J2; + else fs_next_state = FS_IDLE; + end + J2: + begin + if(k & rx_en) fs_next_state = K3; + else fs_next_state = FS_IDLE; + end + K3: + begin + if(j & rx_en) fs_next_state = J3; + else + if(k & rx_en) fs_next_state = K4; // Allow missing one J + else fs_next_state = FS_IDLE; + end + J3: + begin + if(k & rx_en) fs_next_state = K4; + else fs_next_state = FS_IDLE; + end + K4: + begin + if(k) synced_d = 1'b1; + fs_next_state = FS_IDLE; + end + endcase + end + +/////////////////////////////////////////////////////////////////// +// +// Generate RxActive +// + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) rx_active <= #1 1'b0; + else + if(synced_d & rx_en) rx_active <= #1 1'b1; + else + if(se0 & rx_valid_r ) rx_active <= #1 1'b0; + +always @(posedge clk) + if(rx_valid) rx_valid_r <= #1 1'b1; + else + if(fs_ce) rx_valid_r <= #1 1'b0; + +/////////////////////////////////////////////////////////////////// +// +// NRZI Decoder +// + +always @(posedge clk) + if(fs_ce) sd_r <= #1 rxd_s; + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) sd_nrzi <= #1 1'b0; + else + if(rx_active & fs_ce) sd_nrzi <= #1 !(rxd_s ^ sd_r); + +/////////////////////////////////////////////////////////////////// +// +// Bit Stuff Detect +// + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) one_cnt <= #1 3'h0; + else + if(!shift_en) one_cnt <= #1 3'h0; + else + if(fs_ce) + begin + if(!sd_nrzi | drop_bit) one_cnt <= #1 3'h0; + else one_cnt <= #1 one_cnt + 3'h1; + end + +assign drop_bit = (one_cnt==3'h6); + +/////////////////////////////////////////////////////////////////// +// +// Serial => Parallel converter +// + +always @(posedge clk) + if(fs_ce) shift_en <= #1 synced_d | rx_active; + +always @(posedge clk) + if(fs_ce & shift_en & !drop_bit) + hold_reg <= #1 {sd_nrzi, hold_reg[7:1]}; + +/////////////////////////////////////////////////////////////////// +// +// Generate RxValid +// + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) bit_cnt <= #1 3'b0; + else + if(!shift_en) bit_cnt <= #1 3'h0; + else + if(fs_ce & !drop_bit) bit_cnt <= #1 bit_cnt + 3'h1; + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) rx_valid1 <= #1 1'b0; + else + if(fs_ce & !drop_bit & (bit_cnt==3'h7)) rx_valid1 <= #1 1'b1; + else + if(rx_valid1 & fs_ce & !drop_bit) rx_valid1 <= #1 1'b0; + +always @(posedge clk) + rx_valid <= #1 !drop_bit & rx_valid1 & fs_ce; + +endmodule + diff --git a/demo_chip_rtl/rtl/usb_phy/tags/start/rtl/verilog/usb_tx_phy.v b/demo_chip_rtl/rtl/usb_phy/tags/start/rtl/verilog/usb_tx_phy.v new file mode 100644 index 0000000..0ac03a6 --- /dev/null +++ b/demo_chip_rtl/rtl/usb_phy/tags/start/rtl/verilog/usb_tx_phy.v @@ -0,0 +1,451 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// USB 1.1 PHY //// +//// TX //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/usb_phy/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: usb_tx_phy.v,v 1.1.1.1 2002-09-16 14:27:02 rudi Exp $ +// +// $Date: 2002-09-16 14:27:02 $ +// $Revision: 1.1.1.1 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// +// +// +// +// +// + +`include "timescale.v" + +module usb_tx_phy( + clk, rst, fs_ce, phy_mode, + + // Transciever Interface + txdp, txdn, txoe, + + // UTMI Interface + DataOut_i, TxValid_i, TxReady_o + ); + +input clk; +input rst; +input fs_ce; +input phy_mode; +output txdp, txdn, txoe; +input [7:0] DataOut_i; +input TxValid_i; +output TxReady_o; + +/////////////////////////////////////////////////////////////////// +// +// Local Wires and Registers +// + +parameter IDLE = 3'd0, + SOP = 3'h1, + DATA = 3'h2, + EOP1 = 3'h3, + EOP2 = 3'h4, + WAIT = 3'h5; + +reg TxReady_o; +reg [2:0] state, next_state; +reg tx_ready; +reg tx_ready_d; +reg ld_sop_d; +reg ld_data_d; +reg ld_eop_d; +reg tx_ip; +reg tx_ip_sync; +reg [2:0] bit_cnt; +reg [7:0] hold_reg; +reg sd_raw_o; +wire hold; +reg data_done; +reg sft_done; +reg sft_done_r; +wire sft_done_e; +reg ld_data; +wire eop_done; +reg [2:0] one_cnt; +wire stuff; +reg sd_bs_o; +reg sd_nrzi_o; +reg append_eop; +reg append_eop_sync1; +reg append_eop_sync2; +reg append_eop_sync3; +reg txdp, txdn; +reg txoe_r1, txoe_r2; +reg txoe; + +/////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +always @(posedge clk) + tx_ready <= #1 tx_ready_d; + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) TxReady_o <= #1 1'b0; + else TxReady_o <= #1 tx_ready_d & TxValid_i; + +always @(posedge clk) + ld_data <= #1 ld_data_d; + +/////////////////////////////////////////////////////////////////// +// +// Transmit in progress indicator +// + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) tx_ip <= #1 1'b0; + else + if(ld_sop_d) tx_ip <= #1 1'b1; + else + if(eop_done) tx_ip <= #1 1'b0; + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) tx_ip_sync <= #1 1'b0; + else + if(fs_ce) tx_ip_sync <= #1 tx_ip; + +// data_done helps us to catch cases where TxValid drops due to +// packet end and then gets re-asserted as a new packet starts. +// We might not see this because we are still transmitting. +// data_done should solve those cases ... +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) data_done <= #1 1'b0; + else + if(TxValid_i & ! tx_ip) data_done <= #1 1'b1; + else + if(!TxValid_i) data_done <= #1 1'b0; + +/////////////////////////////////////////////////////////////////// +// +// Shift Register +// + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) bit_cnt <= #1 3'h0; + else + if(!tx_ip_sync) bit_cnt <= #1 3'h0; + else + if(fs_ce & !hold) bit_cnt <= #1 bit_cnt + 3'h1; + +assign hold = stuff; + +always @(posedge clk) + if(!tx_ip_sync) sd_raw_o <= #1 1'b0; + else + case(bit_cnt) // synopsys full_case parallel_case + 3'h0: sd_raw_o <= #1 hold_reg[0]; + 3'h1: sd_raw_o <= #1 hold_reg[1]; + 3'h2: sd_raw_o <= #1 hold_reg[2]; + 3'h3: sd_raw_o <= #1 hold_reg[3]; + 3'h4: sd_raw_o <= #1 hold_reg[4]; + 3'h5: sd_raw_o <= #1 hold_reg[5]; + 3'h6: sd_raw_o <= #1 hold_reg[6]; + 3'h7: sd_raw_o <= #1 hold_reg[7]; + endcase + +always @(posedge clk) + sft_done <= #1 !hold & (bit_cnt == 3'h7); + +always @(posedge clk) + sft_done_r <= #1 sft_done; + +assign sft_done_e = sft_done & !sft_done_r; + +// Out Data Hold Register +always @(posedge clk) + if(ld_sop_d) hold_reg <= #1 8'h80; + else + if(ld_data) hold_reg <= #1 DataOut_i; + +/////////////////////////////////////////////////////////////////// +// +// Bit Stuffer +// + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) one_cnt <= #1 3'h0; + else + if(!tx_ip_sync) one_cnt <= #1 3'h0; + else + if(fs_ce) + begin + if(!sd_raw_o | stuff) one_cnt <= #1 3'h0; + else one_cnt <= #1 one_cnt + 3'h1; + end + +assign stuff = (one_cnt==3'h6); + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) sd_bs_o <= #1 1'h0; + else + if(fs_ce) sd_bs_o <= #1 !tx_ip_sync ? 1'b0 : + (stuff ? 1'b0 : sd_raw_o); + +/////////////////////////////////////////////////////////////////// +// +// NRZI Encoder +// + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) sd_nrzi_o <= #1 1'b1; + else + if(!tx_ip_sync | !txoe_r1) sd_nrzi_o <= #1 1'b1; + else + if(fs_ce) sd_nrzi_o <= #1 sd_bs_o ? sd_nrzi_o : ~sd_nrzi_o; + +/////////////////////////////////////////////////////////////////// +// +// EOP append logic +// + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) append_eop <= #1 1'b0; + else + if(ld_eop_d) append_eop <= #1 1'b1; + else + if(append_eop_sync2) append_eop <= #1 1'b0; + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) append_eop_sync1 <= #1 1'b0; + else + if(fs_ce) append_eop_sync1 <= #1 append_eop; + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) append_eop_sync2 <= #1 1'b0; + else + if(fs_ce) append_eop_sync2 <= #1 append_eop_sync1; + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) append_eop_sync3 <= #1 1'b0; + else + if(fs_ce) append_eop_sync3 <= #1 append_eop_sync2; + +assign eop_done = append_eop_sync3; + +/////////////////////////////////////////////////////////////////// +// +// Output Enable Logic +// + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) txoe_r1 <= #1 1'b0; + else + if(fs_ce) txoe_r1 <= #1 tx_ip_sync; + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) txoe_r2 <= #1 1'b0; + else + if(fs_ce) txoe_r2 <= #1 txoe_r1; + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) txoe <= #1 1'b1; + else + if(fs_ce) txoe <= #1 !(txoe_r1 | txoe_r2); + +/////////////////////////////////////////////////////////////////// +// +// Output Registers +// + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) txdp <= #1 1'b1; + else + if(fs_ce) txdp <= #1 phy_mode ? + (!append_eop_sync3 & sd_nrzi_o) : + sd_nrzi_o; + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) txdn <= #1 1'b0; + else + if(fs_ce) txdn <= #1 phy_mode ? + (!append_eop_sync3 & ~sd_nrzi_o) : + append_eop_sync3; + +/////////////////////////////////////////////////////////////////// +// +// Tx Statemashine +// + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) state <= #1 IDLE; + else state <= #1 next_state; + +always @(state or TxValid_i or data_done or sft_done_e or eop_done or fs_ce) + begin + next_state = state; + tx_ready_d = 1'b0; + + ld_sop_d = 1'b0; + ld_data_d = 1'b0; + ld_eop_d = 1'b0; + + case(state) // synopsys full_case parallel_case + IDLE: + begin + if(TxValid_i) + begin + ld_sop_d = 1'b1; + next_state = SOP; + end + end + SOP: + begin + if(sft_done_e) + begin + tx_ready_d = 1'b1; + ld_data_d = 1'b1; + next_state = DATA; + end + end + DATA: + begin + if(!data_done & sft_done_e) + begin + ld_eop_d = 1'b1; + next_state = EOP1; + end + + if(data_done & sft_done_e) + begin + tx_ready_d = 1'b1; + ld_data_d = 1'b1; + end + end + EOP1: + begin + if(eop_done) next_state = EOP2; + end + EOP2: + begin + if(!eop_done & fs_ce) next_state = WAIT; + end + WAIT: + begin + if(fs_ce) next_state = IDLE; + end + endcase + + end + +endmodule + diff --git a/demo_chip_rtl/rtl/usb_phy/trunk/doc/README.txt b/demo_chip_rtl/rtl/usb_phy/trunk/doc/README.txt new file mode 100644 index 0000000..60ff5cf --- /dev/null +++ b/demo_chip_rtl/rtl/usb_phy/trunk/doc/README.txt @@ -0,0 +1,99 @@ + +USB 1.1 PHY +========== + +Status +------ +This core is done. It was tested with a USB 1.1 core I have written on +a XESS XCV800 board with a a Philips PDIUSBP11A transceiver. +I have NOT yet tested it with my USB 2.0 Function IP core. + +Test Bench +---------- +There is no test bench, period ! As I said above I have tested this core +in real hardware and it works just fine. + +Documentation +------------- +Sorry, there is none. I just don't have the time to write it. I have tried +to follow the UTMI interface specification from USB 2.0. +'phy_mode' selects between single ended and differential tx_phy output. See +Philips ISP 1105 transceiver data sheet for an explanation of it's MODE +select pin (see Note below). +Currently this PHY only operates in Full-Speed mode. Required clock frequency +is 48MHz, from which the 12MHz USB transmit and receive clocks are derived. + +RxError reports the following errors: + - sync errors + Could not synchronize to incoming bit stream + - Bit Stuff Error + Stuff bit had the wrong value (expected '0' got '1') + - Byte Error + Got a EOP (se0) before finished assembling a full byteAll of those errors + are or'ed together and reported via RxError. + +Note: +1) "phy_tx_mode" selects the PHY Transmit Mode: +When phy_tx_mode is '0' the outputs are encoded as: + txdn, txdp + 0 0 Differential Logic '0' + 0 1 Differential Logic '1' + 1 0 Single Ended '0' + 1 1 Single Ended '0' + +When phy_tx_mode is '1' the outputs are encoded as: + txdn, txdp + 0 0 Single Ended '0' + 0 1 Differential Logic '1' + 1 0 Differential Logic '0' + 1 1 Illegal State + +See PHILIPS Transceiver Data Sheet for: ISP1105, ISP1106 and ISP1107 +for more details. + +2) "usb_rst" Indicates a USB Bus Reset (this output is also or'ed with + the reset input). + +Misc +---- +The USB 1.1 Phy Project Page is: +http://www.opencores.org/cores/usb_phy + +To find out more about me (Rudolf Usselmann), please visit: +http://www.asics.ws + + +Directory Structure +------------------- +[core_root] + | + +-doc Documentation + | + +-bench--+ Test Bench + | +-verilog Verilog Sources + | +-vhdl VHDL Sources + | + +-rtl----+ Core RTL Sources + | +-verilog Verilog Sources + | +-vhdl VHDL Sources + | + +-sim----+ + | +-rtl_sim---+ Functional verification Directory + | | +-bin Makefiles/Run Scripts + | | +-run Working Directory + | | + | +-gate_sim--+ Functional & Timing Gate Level + | | Verification Directory + | +-bin Makefiles/Run Scripts + | +-run Working Directory + | + +-lint--+ Lint Directory Tree + | +-bin Makefiles/Run Scripts + | +-run Working Directory + | +-log Linter log & result files + | + +-syn---+ Synthesis Directory Tree + | +-bin Synthesis Scripts + | +-run Working Directory + | +-log Synthesis log files + | +-out Synthesis Output diff --git a/demo_chip_rtl/rtl/usb_phy/trunk/rtl/verilog/timescale.v b/demo_chip_rtl/rtl/usb_phy/trunk/rtl/verilog/timescale.v new file mode 100644 index 0000000..ff9e265 --- /dev/null +++ b/demo_chip_rtl/rtl/usb_phy/trunk/rtl/verilog/timescale.v @@ -0,0 +1 @@ +`timescale 1ns / 10ps diff --git a/demo_chip_rtl/rtl/usb_phy/trunk/rtl/verilog/usb_phy.v b/demo_chip_rtl/rtl/usb_phy/trunk/rtl/verilog/usb_phy.v new file mode 100644 index 0000000..5ff0454 --- /dev/null +++ b/demo_chip_rtl/rtl/usb_phy/trunk/rtl/verilog/usb_phy.v @@ -0,0 +1,179 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// USB 1.1 PHY //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/usb_phy/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: usb_phy.v,v 1.4 2003-10-21 05:58:40 rudi Exp $ +// +// $Date: 2003-10-21 05:58:40 $ +// $Revision: 1.4 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.3 2003/10/19 17:40:13 rudi +// - Made core more robust against line noise +// - Added Error Checking and Reporting +// (See README.txt for more info) +// +// Revision 1.2 2002/09/16 16:06:37 rudi +// Changed top level name to be consistent ... +// +// Revision 1.1.1.1 2002/09/16 14:26:59 rudi +// Created Directory Structure +// +// +// +// +// +// +// +// + +`include "timescale.v" + +module usb_phy(clk, rst, phy_tx_mode, usb_rst, + + // Transciever Interface + txdp, txdn, txoe, + rxd, rxdp, rxdn, + + // UTMI Interface + DataOut_i, TxValid_i, TxReady_o, RxValid_o, + RxActive_o, RxError_o, DataIn_o, LineState_o + ); + +input clk; +input rst; +input phy_tx_mode; +output usb_rst; +output txdp, txdn, txoe; +input rxd, rxdp, rxdn; +input [7:0] DataOut_i; +input TxValid_i; +output TxReady_o; +output [7:0] DataIn_o; +output RxValid_o; +output RxActive_o; +output RxError_o; +output [1:0] LineState_o; + +/////////////////////////////////////////////////////////////////// +// +// Local Wires and Registers +// + +reg [4:0] rst_cnt; +reg usb_rst; +wire fs_ce; +wire rst; + +/////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +/////////////////////////////////////////////////////////////////// +// +// TX Phy +// + +usb_tx_phy i_tx_phy( + .clk( clk ), + .rst( rst ), + .fs_ce( fs_ce ), + .phy_mode( phy_tx_mode ), + + // Transciever Interface + .txdp( txdp ), + .txdn( txdn ), + .txoe( txoe ), + + // UTMI Interface + .DataOut_i( DataOut_i ), + .TxValid_i( TxValid_i ), + .TxReady_o( TxReady_o ) + ); + +/////////////////////////////////////////////////////////////////// +// +// RX Phy and DPLL +// + +usb_rx_phy i_rx_phy( + .clk( clk ), + .rst( rst ), + .fs_ce( fs_ce ), + + // Transciever Interface + .rxd( rxd ), + .rxdp( rxdp ), + .rxdn( rxdn ), + + // UTMI Interface + .DataIn_o( DataIn_o ), + .RxValid_o( RxValid_o ), + .RxActive_o( RxActive_o ), + .RxError_o( RxError_o ), + .RxEn_i( txoe ), + .LineState( LineState_o ) + ); + +/////////////////////////////////////////////////////////////////// +// +// Generate an USB Reset is we see SE0 for at least 2.5uS +// + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) rst_cnt <= 5'h0; + else + if(LineState_o != 2'h0) rst_cnt <= 5'h0; + else + if(!usb_rst && fs_ce) rst_cnt <= rst_cnt + 5'h1; + +always @(posedge clk) + usb_rst <= (rst_cnt == 5'h1f); + +endmodule + diff --git a/demo_chip_rtl/rtl/usb_phy/trunk/rtl/verilog/usb_rx_phy.v b/demo_chip_rtl/rtl/usb_phy/trunk/rtl/verilog/usb_rx_phy.v new file mode 100644 index 0000000..7a8110f --- /dev/null +++ b/demo_chip_rtl/rtl/usb_phy/trunk/rtl/verilog/usb_rx_phy.v @@ -0,0 +1,449 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// USB 1.1 PHY //// +//// RX & DPLL //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/usb_phy/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: usb_rx_phy.v,v 1.5 2004-10-19 09:29:07 rudi Exp $ +// +// $Date: 2004-10-19 09:29:07 $ +// $Revision: 1.5 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.4 2003/12/02 04:56:00 rudi +// Fixed a bug reported by Karl C. Posch from Graz University of Technology. Thanks Karl ! +// +// Revision 1.3 2003/10/19 18:07:45 rudi +// - Fixed Sync Error to be only checked/generated during the sync phase +// +// Revision 1.2 2003/10/19 17:40:13 rudi +// - Made core more robust against line noise +// - Added Error Checking and Reporting +// (See README.txt for more info) +// +// Revision 1.1.1.1 2002/09/16 14:27:01 rudi +// Created Directory Structure +// +// +// +// +// +// +// +// + +`include "timescale.v" + +module usb_rx_phy( clk, rst, fs_ce, + + // Transciever Interface + rxd, rxdp, rxdn, + + // UTMI Interface + RxValid_o, RxActive_o, RxError_o, DataIn_o, + RxEn_i, LineState); + +input clk; +input rst; +output fs_ce; +input rxd, rxdp, rxdn; +output [7:0] DataIn_o; +output RxValid_o; +output RxActive_o; +output RxError_o; +input RxEn_i; +output [1:0] LineState; + +/////////////////////////////////////////////////////////////////// +// +// Local Wires and Registers +// + +reg rxd_s0, rxd_s1, rxd_s; +reg rxdp_s0, rxdp_s1, rxdp_s, rxdp_s_r; +reg rxdn_s0, rxdn_s1, rxdn_s, rxdn_s_r; +reg synced_d; +wire k, j, se0; +reg rxd_r; +reg rx_en; +reg rx_active; +reg [2:0] bit_cnt; +reg rx_valid1, rx_valid; +reg shift_en; +reg sd_r; +reg sd_nrzi; +reg [7:0] hold_reg; +wire drop_bit; // Indicates a stuffed bit +reg [2:0] one_cnt; + +reg [1:0] dpll_state, dpll_next_state; +reg fs_ce_d; +reg fs_ce; +wire change; +wire lock_en; +reg [2:0] fs_state, fs_next_state; +reg rx_valid_r; +reg sync_err_d, sync_err; +reg bit_stuff_err; +reg se0_r, byte_err; +reg se0_s; + +/////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +assign RxActive_o = rx_active; +assign RxValid_o = rx_valid; +assign RxError_o = sync_err | bit_stuff_err | byte_err; +assign DataIn_o = hold_reg; +assign LineState = {rxdn_s1, rxdp_s1}; + +always @(posedge clk) rx_en <= RxEn_i; +always @(posedge clk) sync_err <= !rx_active & sync_err_d; + +/////////////////////////////////////////////////////////////////// +// +// Synchronize Inputs +// + +// First synchronize to the local system clock to +// avoid metastability outside the sync block (*_s0). +// Then make sure we see the signal for at least two +// clock cycles stable to avoid glitches and noise + +always @(posedge clk) rxd_s0 <= rxd; +always @(posedge clk) rxd_s1 <= rxd_s0; +always @(posedge clk) // Avoid detecting Line Glitches and noise + if(rxd_s0 && rxd_s1) rxd_s <= 1'b1; + else + if(!rxd_s0 && !rxd_s1) rxd_s <= 1'b0; + +always @(posedge clk) rxdp_s0 <= rxdp; +always @(posedge clk) rxdp_s1 <= rxdp_s0; +always @(posedge clk) rxdp_s_r <= rxdp_s0 & rxdp_s1; +always @(posedge clk) rxdp_s <= (rxdp_s0 & rxdp_s1) | rxdp_s_r; // Avoid detecting Line Glitches and noise + +always @(posedge clk) rxdn_s0 <= rxdn; +always @(posedge clk) rxdn_s1 <= rxdn_s0; +always @(posedge clk) rxdn_s_r <= rxdn_s0 & rxdn_s1; +always @(posedge clk) rxdn_s <= (rxdn_s0 & rxdn_s1) | rxdn_s_r; // Avoid detecting Line Glitches and noise + +assign k = !rxdp_s & rxdn_s; +assign j = rxdp_s & !rxdn_s; +assign se0 = !rxdp_s & !rxdn_s; + +always @(posedge clk) if(fs_ce) se0_s <= se0; + +/////////////////////////////////////////////////////////////////// +// +// DPLL +// + +// This design uses a clock enable to do 12Mhz timing and not a +// real 12Mhz clock. Everything always runs at 48Mhz. We want to +// make sure however, that the clock enable is always exactly in +// the middle between two virtual 12Mhz rising edges. +// We monitor rxdp and rxdn for any changes and do the appropiate +// adjustments. +// In addition to the locking done in the dpll FSM, we adjust the +// final latch enable to compensate for various sync registers ... + +// Allow lockinf only when we are receiving +assign lock_en = rx_en; + +always @(posedge clk) rxd_r <= rxd_s; + +// Edge detector +assign change = rxd_r != rxd_s; + +// DPLL FSM +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) dpll_state <= 2'h1; + else dpll_state <= dpll_next_state; + +always @(dpll_state or lock_en or change) + begin + fs_ce_d = 1'b0; + case(dpll_state) // synopsys full_case parallel_case + 2'h0: + if(lock_en && change) dpll_next_state = 2'h0; + else dpll_next_state = 2'h1; + 2'h1:begin + fs_ce_d = 1'b1; + if(lock_en && change) dpll_next_state = 2'h3; + else dpll_next_state = 2'h2; + end + 2'h2: + if(lock_en && change) dpll_next_state = 2'h0; + else dpll_next_state = 2'h3; + 2'h3: + if(lock_en && change) dpll_next_state = 2'h0; + else dpll_next_state = 2'h0; + endcase + end + +// Compensate for sync registers at the input - allign full speed +// clock enable to be in the middle between two bit changes ... +reg fs_ce_r1, fs_ce_r2; + +always @(posedge clk) fs_ce_r1 <= fs_ce_d; +always @(posedge clk) fs_ce_r2 <= fs_ce_r1; +always @(posedge clk) fs_ce <= fs_ce_r2; + + +/////////////////////////////////////////////////////////////////// +// +// Find Sync Pattern FSM +// + +parameter FS_IDLE = 3'h0, + K1 = 3'h1, + J1 = 3'h2, + K2 = 3'h3, + J2 = 3'h4, + K3 = 3'h5, + J3 = 3'h6, + K4 = 3'h7; + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) fs_state <= FS_IDLE; + else fs_state <= fs_next_state; + +always @(fs_state or fs_ce or k or j or rx_en or rx_active or se0 or se0_s) + begin + synced_d = 1'b0; + sync_err_d = 1'b0; + fs_next_state = fs_state; + if(fs_ce && !rx_active && !se0 && !se0_s) + case(fs_state) // synopsys full_case parallel_case + FS_IDLE: + begin + if(k && rx_en) fs_next_state = K1; + end + K1: + begin + if(j && rx_en) fs_next_state = J1; + else + begin + sync_err_d = 1'b1; + fs_next_state = FS_IDLE; + end + end + J1: + begin + if(k && rx_en) fs_next_state = K2; + else + begin + sync_err_d = 1'b1; + fs_next_state = FS_IDLE; + end + end + K2: + begin + if(j && rx_en) fs_next_state = J2; + else + begin + sync_err_d = 1'b1; + fs_next_state = FS_IDLE; + end + end + J2: + begin + if(k && rx_en) fs_next_state = K3; + else + begin + sync_err_d = 1'b1; + fs_next_state = FS_IDLE; + end + end + K3: + begin + if(j && rx_en) fs_next_state = J3; + else + if(k && rx_en) + begin + fs_next_state = FS_IDLE; // Allow missing first K-J + synced_d = 1'b1; + end + else + begin + sync_err_d = 1'b1; + fs_next_state = FS_IDLE; + end + end + J3: + begin + if(k && rx_en) fs_next_state = K4; + else + begin + sync_err_d = 1'b1; + fs_next_state = FS_IDLE; + end + end + K4: + begin + if(k) synced_d = 1'b1; + fs_next_state = FS_IDLE; + end + endcase + end + +/////////////////////////////////////////////////////////////////// +// +// Generate RxActive +// + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) rx_active <= 1'b0; + else + if(synced_d && rx_en) rx_active <= 1'b1; + else + if(se0 && rx_valid_r) rx_active <= 1'b0; + +always @(posedge clk) + if(rx_valid) rx_valid_r <= 1'b1; + else + if(fs_ce) rx_valid_r <= 1'b0; + +/////////////////////////////////////////////////////////////////// +// +// NRZI Decoder +// + +always @(posedge clk) + if(fs_ce) sd_r <= rxd_s; + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) sd_nrzi <= 1'b0; + else + if(!rx_active) sd_nrzi <= 1'b1; + else + if(rx_active && fs_ce) sd_nrzi <= !(rxd_s ^ sd_r); + +/////////////////////////////////////////////////////////////////// +// +// Bit Stuff Detect +// + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) one_cnt <= 3'h0; + else + if(!shift_en) one_cnt <= 3'h0; + else + if(fs_ce) + begin + if(!sd_nrzi || drop_bit) one_cnt <= 3'h0; + else one_cnt <= one_cnt + 3'h1; + end + +assign drop_bit = (one_cnt==3'h6); + +always @(posedge clk) bit_stuff_err <= drop_bit & sd_nrzi & fs_ce & !se0 & rx_active; // Bit Stuff Error + +/////////////////////////////////////////////////////////////////// +// +// Serial => Parallel converter +// + +always @(posedge clk) + if(fs_ce) shift_en <= synced_d | rx_active; + +always @(posedge clk) + if(fs_ce && shift_en && !drop_bit) + hold_reg <= {sd_nrzi, hold_reg[7:1]}; + +/////////////////////////////////////////////////////////////////// +// +// Generate RxValid +// + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) bit_cnt <= 3'b0; + else + if(!shift_en) bit_cnt <= 3'h0; + else + if(fs_ce && !drop_bit) bit_cnt <= bit_cnt + 3'h1; + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) rx_valid1 <= 1'b0; + else + if(fs_ce && !drop_bit && (bit_cnt==3'h7)) rx_valid1 <= 1'b1; + else + if(rx_valid1 && fs_ce && !drop_bit) rx_valid1 <= 1'b0; + +always @(posedge clk) rx_valid <= !drop_bit & rx_valid1 & fs_ce; + +always @(posedge clk) se0_r <= se0; + +always @(posedge clk) byte_err <= se0 & !se0_r & (|bit_cnt[2:1]) & rx_active; + +endmodule + diff --git a/demo_chip_rtl/rtl/usb_phy/trunk/rtl/verilog/usb_tx_phy.v b/demo_chip_rtl/rtl/usb_phy/trunk/rtl/verilog/usb_tx_phy.v new file mode 100644 index 0000000..eaf4a90 --- /dev/null +++ b/demo_chip_rtl/rtl/usb_phy/trunk/rtl/verilog/usb_tx_phy.v @@ -0,0 +1,462 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// USB 1.1 PHY //// +//// TX //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://www.opencores.org/cores/usb_phy/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: usb_tx_phy.v,v 1.4 2004-10-19 09:29:07 rudi Exp $ +// +// $Date: 2004-10-19 09:29:07 $ +// $Revision: 1.4 $ +// $Author: rudi $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.3 2003/10/21 05:58:41 rudi +// usb_rst is no longer or'ed with the incomming reset internally. +// Now usb_rst is simply an output, the application can decide how +// to utilize it. +// +// Revision 1.2 2003/10/19 17:40:13 rudi +// - Made core more robust against line noise +// - Added Error Checking and Reporting +// (See README.txt for more info) +// +// Revision 1.1.1.1 2002/09/16 14:27:02 rudi +// Created Directory Structure +// +// +// +// +// +// +// + +`include "timescale.v" + +module usb_tx_phy( + clk, rst, fs_ce, phy_mode, + + // Transciever Interface + txdp, txdn, txoe, + + // UTMI Interface + DataOut_i, TxValid_i, TxReady_o + ); + +input clk; +input rst; +input fs_ce; +input phy_mode; +output txdp, txdn, txoe; +input [7:0] DataOut_i; +input TxValid_i; +output TxReady_o; + +/////////////////////////////////////////////////////////////////// +// +// Local Wires and Registers +// + +parameter IDLE = 3'd0, + SOP = 3'h1, + DATA = 3'h2, + EOP1 = 3'h3, + EOP2 = 3'h4, + WAIT = 3'h5; + +reg TxReady_o; +reg [2:0] state, next_state; +reg tx_ready_d; +reg ld_sop_d; +reg ld_data_d; +reg ld_eop_d; +reg tx_ip; +reg tx_ip_sync; +reg [2:0] bit_cnt; +reg [7:0] hold_reg; +reg [7:0] hold_reg_d; + +reg sd_raw_o; +wire hold; +reg data_done; +reg sft_done; +reg sft_done_r; +wire sft_done_e; +reg ld_data; +wire eop_done; +reg [2:0] one_cnt; +wire stuff; +reg sd_bs_o; +reg sd_nrzi_o; +reg append_eop; +reg append_eop_sync1; +reg append_eop_sync2; +reg append_eop_sync3; +reg append_eop_sync4; +reg txdp, txdn; +reg txoe_r1, txoe_r2; +reg txoe; + +/////////////////////////////////////////////////////////////////// +// +// Misc Logic +// + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) TxReady_o <= 1'b0; + else TxReady_o <= tx_ready_d & TxValid_i; + +always @(posedge clk) ld_data <= ld_data_d; + +/////////////////////////////////////////////////////////////////// +// +// Transmit in progress indicator +// + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) tx_ip <= 1'b0; + else + if(ld_sop_d) tx_ip <= 1'b1; + else + if(eop_done) tx_ip <= 1'b0; + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) tx_ip_sync <= 1'b0; + else + if(fs_ce) tx_ip_sync <= tx_ip; + +// data_done helps us to catch cases where TxValid drops due to +// packet end and then gets re-asserted as a new packet starts. +// We might not see this because we are still transmitting. +// data_done should solve those cases ... +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) data_done <= 1'b0; + else + if(TxValid_i && ! tx_ip) data_done <= 1'b1; + else + if(!TxValid_i) data_done <= 1'b0; + +/////////////////////////////////////////////////////////////////// +// +// Shift Register +// + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) bit_cnt <= 3'h0; + else + if(!tx_ip_sync) bit_cnt <= 3'h0; + else + if(fs_ce && !hold) bit_cnt <= bit_cnt + 3'h1; + +assign hold = stuff; + +always @(posedge clk) + if(!tx_ip_sync) sd_raw_o <= 1'b0; + else + case(bit_cnt) // synopsys full_case parallel_case + 3'h0: sd_raw_o <= hold_reg_d[0]; + 3'h1: sd_raw_o <= hold_reg_d[1]; + 3'h2: sd_raw_o <= hold_reg_d[2]; + 3'h3: sd_raw_o <= hold_reg_d[3]; + 3'h4: sd_raw_o <= hold_reg_d[4]; + 3'h5: sd_raw_o <= hold_reg_d[5]; + 3'h6: sd_raw_o <= hold_reg_d[6]; + 3'h7: sd_raw_o <= hold_reg_d[7]; + endcase + +always @(posedge clk) + sft_done <= !hold & (bit_cnt == 3'h7); + +always @(posedge clk) + sft_done_r <= sft_done; + +assign sft_done_e = sft_done & !sft_done_r; + +// Out Data Hold Register +always @(posedge clk) + if(ld_sop_d) hold_reg <= 8'h80; + else + if(ld_data) hold_reg <= DataOut_i; + +always @(posedge clk) hold_reg_d <= hold_reg; + +/////////////////////////////////////////////////////////////////// +// +// Bit Stuffer +// + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) one_cnt <= 3'h0; + else + if(!tx_ip_sync) one_cnt <= 3'h0; + else + if(fs_ce) + begin + if(!sd_raw_o || stuff) one_cnt <= 3'h0; + else one_cnt <= one_cnt + 3'h1; + end + +assign stuff = (one_cnt==3'h6); + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) sd_bs_o <= 1'h0; + else + if(fs_ce) sd_bs_o <= !tx_ip_sync ? 1'b0 : (stuff ? 1'b0 : sd_raw_o); + +/////////////////////////////////////////////////////////////////// +// +// NRZI Encoder +// + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) sd_nrzi_o <= 1'b1; + else + if(!tx_ip_sync || !txoe_r1) sd_nrzi_o <= 1'b1; + else + if(fs_ce) sd_nrzi_o <= sd_bs_o ? sd_nrzi_o : ~sd_nrzi_o; + +/////////////////////////////////////////////////////////////////// +// +// EOP append logic +// + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) append_eop <= 1'b0; + else + if(ld_eop_d) append_eop <= 1'b1; + else + if(append_eop_sync2) append_eop <= 1'b0; + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) append_eop_sync1 <= 1'b0; + else + if(fs_ce) append_eop_sync1 <= append_eop; + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) append_eop_sync2 <= 1'b0; + else + if(fs_ce) append_eop_sync2 <= append_eop_sync1; + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) append_eop_sync3 <= 1'b0; + else + if(fs_ce) append_eop_sync3 <= append_eop_sync2 | + (append_eop_sync3 & !append_eop_sync4); // Make sure always 2 bit wide + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) append_eop_sync4 <= 1'b0; + else + if(fs_ce) append_eop_sync4 <= append_eop_sync3; + +assign eop_done = append_eop_sync3; + +/////////////////////////////////////////////////////////////////// +// +// Output Enable Logic +// + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) txoe_r1 <= 1'b0; + else + if(fs_ce) txoe_r1 <= tx_ip_sync; + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) txoe_r2 <= 1'b0; + else + if(fs_ce) txoe_r2 <= txoe_r1; + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) txoe <= 1'b1; + else + if(fs_ce) txoe <= !(txoe_r1 | txoe_r2); + +/////////////////////////////////////////////////////////////////// +// +// Output Registers +// + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) txdp <= 1'b1; + else + if(fs_ce) txdp <= phy_mode ? + (!append_eop_sync3 & sd_nrzi_o) : + sd_nrzi_o; + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) txdn <= 1'b0; + else + if(fs_ce) txdn <= phy_mode ? + (!append_eop_sync3 & ~sd_nrzi_o) : + append_eop_sync3; + +/////////////////////////////////////////////////////////////////// +// +// Tx Statemashine +// + +`ifdef USB_ASYNC_REST +always @(posedge clk or negedge rst) +`else +always @(posedge clk) +`endif + if(!rst) state <= IDLE; + else state <= next_state; + +always @(state or TxValid_i or data_done or sft_done_e or eop_done or fs_ce) + begin + next_state = state; + tx_ready_d = 1'b0; + + ld_sop_d = 1'b0; + ld_data_d = 1'b0; + ld_eop_d = 1'b0; + + case(state) // synopsys full_case parallel_case + IDLE: + if(TxValid_i) + begin + ld_sop_d = 1'b1; + next_state = SOP; + end + SOP: + if(sft_done_e) + begin + tx_ready_d = 1'b1; + ld_data_d = 1'b1; + next_state = DATA; + end + DATA: + begin + if(!data_done && sft_done_e) + begin + ld_eop_d = 1'b1; + next_state = EOP1; + end + + if(data_done && sft_done_e) + begin + tx_ready_d = 1'b1; + ld_data_d = 1'b1; + end + end + EOP1: + if(eop_done) next_state = EOP2; + EOP2: + if(!eop_done && fs_ce) next_state = WAIT; + WAIT: + if(fs_ce) next_state = IDLE; + endcase + end + +endmodule + diff --git a/docs/LICENSE_Nangate.txt b/docs/LICENSE_Nangate.txt new file mode 100755 index 0000000..4fb35f0 --- /dev/null +++ b/docs/LICENSE_Nangate.txt @@ -0,0 +1,16 @@ +The Open Cell Library is intended for use by universities, other research activities, educational programs and Si2.org members. +However allowed, the Open Cell Library is not intended for commercial use. If you use the Open Cell Library for demonstration of commercial EDA tools +it is required to mention, indicate that the library was developped by Nangate. + +If you have questions or concerns then please contact us at openlibrary@nangate.com + +The Open Cell Library is provided by Nangate under the following License: + +Nangate Open Cell Library License, Version 1.0. February 20, 2008 + +Permission is hereby granted, free of charge, to any person or organization obtaining a copy of the Open Cell Library and accompanying documentation (the "Library") covered by this license to use, reproduce, display, distribute, execute, and transmit the Library, and to prepare derivative works of the Library, and to permit third-parties to whom the Library is furnished to do so, all subject to the following: + +The copyright notices in the Library and this entire statement, including the above license grant, this restriction and the following disclaimer, must be included in all copies of the Library, in whole or in part, and all derivative works of the Library, unless such copies or derivative works are solely in the form of machine-executable object code generated by a source language processor. The library has been generated using a non-optimized open PDK and is not suited for any commercial purpose. Measuring or benchmarking the Library against any other library or standard cell set is prohibited. Any meaningful library benchmarking must be done in collaboration with Nangate or other providers of optimized and production-ready PDKs. + +THE LIBRARY IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR ANYONE DISTRIBUTING THE LIBRARY BE LIABLE FOR ANY DAMAGES OR OTHER LIABILITY, WHETHER IN CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE LIBRARY OR THE USE OR OTHER DEALINGS IN THE LIBRARY. + diff --git a/libs/.MemGen_16_10.memlib.swp b/libs/.MemGen_16_10.memlib.swp new file mode 100644 index 0000000..61eb106 Binary files /dev/null and b/libs/.MemGen_16_10.memlib.swp differ diff --git a/libs/MemGen_16_10.memlib b/libs/MemGen_16_10.memlib new file mode 100644 index 0000000..f7dc956 --- /dev/null +++ b/libs/MemGen_16_10.memlib @@ -0,0 +1,35 @@ +Core (MemGen_16_10) { + Memory { + Port (clock) { + Function = Clock; + } + Port (chip_en) { + Function = Select; + Polarity = activeHigh; + } + Port (rd_en) { + Function = ReadEnable; + Polarity = activeHigh; + } + Port (wr_en) { + Function = WriteEnable; + Polarity = activeHigh; + } + Port (addr[9:0]) { + Function = Address; + } + Port (wr_data[15:0]) { + Function = Data; + Direction = Input; + } + Port (rd_data[15:0]) { + Function = Data; + Direction = Output; + } + AddressCounter { + Function (address) { + CountRange = [0 1023]; + } + } + } +} diff --git a/libs/NCSU_FreePDK_45nm.ptf b/libs/NCSU_FreePDK_45nm.ptf new file mode 100755 index 0000000..be33adc --- /dev/null +++ b/libs/NCSU_FreePDK_45nm.ptf @@ -0,0 +1,6777 @@ +process_technology ( master_techFreePDK45 ) { + + capacitance_unit : ff + resistance_unit : ohm + inductance_unit : nH + voltage_unit : V + current_unit : mA + power_unit : mW + length_unit : um + per_length_unit : um + thickness_unit : um + height_unit : um + area_unit : um2 + + nom_process : 1.00 + nom_temperature : 25.00 + nom_voltage : 1.20 + + half_node_scale_factor : 1.00 + + /////////////////////////////////////////////////////////////////////// + // Dielectric-type Dielectric-name Thickness Dielectric-constant // + /////////////////////////////////////////////////////////////////////// + + dielectric_stack { + planar metal10_diel_b 2.000000 2.500000; + planar metal10_diel_a 2.000000 2.500000; + planar metal9_diel_b 2.000000 2.500000; + planar metal9_diel_a 2.000000 2.500000; + planar metal8_diel_b 0.820000 2.500000; + planar metal8_diel_a 0.800000 2.500000; + planar metal7_diel_b 0.820000 2.500000; + planar metal7_diel_a 0.800000 2.500000; + planar metal6_diel_b 0.290000 2.500000; + planar metal6_diel_a 0.280000 2.500000; + planar metal5_diel_b 0.290000 2.500000; + planar metal5_diel_a 0.280000 2.500000; + planar metal4_diel_b 0.290000 2.500000; + planar metal4_diel_a 0.280000 2.500000; + planar metal3_diel_b 0.120000 2.500000; + planar metal3_diel_a 0.140000 2.500000; + planar metal2_diel_b 0.120000 2.500000; + planar metal2_diel_a 0.140000 2.500000; + planar metal1_diel_b 0.120000 2.500000; + planar metal1_diel_a 0.130000 2.500000; + planar poly_diel_b 0.085000 2.500000; + planar poly_diel_a 0.085000 2.500000; + planar field_active_diel 0.100000 3.900000; + planar field_base_diel 0.100000 3.900000; + } + + //////////////////////////////////////////// + // Layer-name Thickness Height // + //////////////////////////////////////////// + + layer_stack { + metal10 2.000000 10.090000; + metal9 2.000000 6.090000; + metal8 0.800000 4.470000; + metal7 0.800000 2.850000; + metal6 0.280000 2.280000; + metal5 0.280000 1.710000; + metal4 0.280000 1.140000; + metal3 0.140000 0.880000; + metal2 0.140000 0.620000; + metal1 0.130000 0.370000; + poly 0.085000 0.200000; + } + + capacitance_lut_template(capacitance_template_WxS) { + variable_1 : width; + variable_2 : spacing; + index_1 (" 1, 2, 3, 4, 5 "); + index_2 (" 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 "); + etched : false; + infinite_spacing : true; + } + + capacitance_lut_template(capacitance_template_etched_WxS) { + variable_1 : width; + variable_2 : spacing; + index_1 (" 1, 2, 3, 4, 5 "); + index_2 (" 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 "); + etched : true; + infinite_spacing : true; + } + + cross_capacitance_lut_template(cross_capacitance_template_WxS) { + variable_1 : width; + variable_2 : spacing; + variable_3 : cross_width; + variable_4 : cross_spacing; + index_1 (" 1, 2, 3, 4, 5 "); + index_2 (" 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 "); + index_3 (" 1, 2, 3, 4, 5 "); + index_4 (" 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 "); + etched : false; + infinite_spacing : true; + } + + cross_capacitance_lut_template(cross_capacitance_template_etched_WxS) { + variable_1 : width; + variable_2 : spacing; + variable_3 : cross_width; + variable_4 : cross_spacing; + index_1 (" 1, 2, 3, 4, 5 "); + index_2 (" 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 "); + index_3 (" 1, 2, 3, 4, 5 "); + index_4 (" 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 "); + etched : true; + infinite_spacing : true; + } + + layer (metal10) { + resistance: 0.030000 + + capacitance () { + top_plane: AIR; + bottom_plane: metal9; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.8000, 0.9000, 1.5000, 1.6000, 3.2000 "); + index_2 (" 0.8000, 0.9000, 1.2000, 1.5000, 1.8000, 2.7000, 4.0500, 6.0750, \ + 9.1125, 13.6688, 20.5031, 30.7547, 3075.4688 "); + values (" 0.07632, 0.06890, 0.05358, 0.04392, 0.03718, 0.02508, 0.01593, 0.00904, \ + 0.00419, 0.00139, 0.00027, 0.00003, 0.00000, 0.07692, 0.06947, 0.05406, \ + 0.04433, 0.03755, 0.02533, 0.01609, 0.00913, 0.00423, 0.00140, 0.00028, \ + 0.00003, 0.00000, 0.07954, 0.07194, 0.05617, 0.04616, 0.03914, 0.02645, \ + 0.01681, 0.00953, 0.00442, 0.00146, 0.00029, 0.00003, 0.00000, 0.07986, \ + 0.07224, 0.05643, 0.04638, 0.03934, 0.02659, 0.01690, 0.00958, 0.00444, \ + 0.00147, 0.00029, 0.00003, 0.00000, 0.08275, 0.07499, 0.05880, 0.04844, \ + 0.04115, 0.02787, 0.01772, 0.01004, 0.00465, 0.00154, 0.00030, 0.00003, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.8000, 0.9000, 1.5000, 1.6000, 3.2000 "); + index_2 (" 0.8000, 0.9000, 1.2000, 1.5000, 1.8000, 2.7000, 4.0500, 6.0750, \ + 9.1125, 13.6688, 20.5031, 30.7547, 3075.4688 "); + values (" 0.02011, 0.02105, 0.02372, 0.02621, 0.02854, 0.03472, 0.04215, 0.05027, \ + 0.05778, 0.06293, 0.06518, 0.06572, 0.06552, 0.02110, 0.02203, 0.02469, \ + 0.02718, 0.02952, 0.03573, 0.04322, 0.05141, 0.05899, 0.06419, 0.06646, \ + 0.06701, 0.06680, 0.02700, 0.02792, 0.03059, 0.03311, 0.03549, 0.04187, \ + 0.04962, 0.05813, 0.06602, 0.07145, 0.07381, 0.07439, 0.07418, 0.02799, \ + 0.02891, 0.03159, 0.03411, 0.03651, 0.04291, 0.05068, 0.05924, 0.06717, \ + 0.07262, 0.07500, 0.07557, 0.07537, 0.04451, 0.04546, 0.04820, 0.05079, \ + 0.05325, 0.05987, 0.06797, 0.07691, 0.08520, 0.09091, 0.09340, 0.09400, \ + 0.09380 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: metal8; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.8000, 0.9000, 1.5000, 1.6000, 3.2000 "); + index_2 (" 0.8000, 0.9000, 1.2000, 1.5000, 1.8000, 2.7000, 4.0500, 6.0750, \ + 9.1125, 13.6688, 20.5031, 30.7547, 3075.4688 "); + values (" 0.07973, 0.07241, 0.05736, 0.04791, 0.04135, 0.02955, 0.02047, 0.01323, \ + 0.00751, 0.00341, 0.00108, 0.00020, 0.00000, 0.08046, 0.07310, 0.05796, \ + 0.04843, 0.04182, 0.02989, 0.02069, 0.01336, 0.00757, 0.00344, 0.00109, \ + 0.00020, 0.00000, 0.08380, 0.07628, 0.06071, 0.05084, 0.04394, 0.03141, \ + 0.02168, 0.01394, 0.00788, 0.00358, 0.00114, 0.00021, 0.00000, 0.08422, \ + 0.07668, 0.06106, 0.05115, 0.04421, 0.03160, 0.02181, 0.01402, 0.00792, \ + 0.00359, 0.00114, 0.00021, 0.00000, 0.08826, 0.08052, 0.06438, 0.05405, \ + 0.04676, 0.03339, 0.02296, 0.01469, 0.00828, 0.00375, 0.00119, 0.00022, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.8000, 0.9000, 1.5000, 1.6000, 3.2000 "); + index_2 (" 0.8000, 0.9000, 1.2000, 1.5000, 1.8000, 2.7000, 4.0500, 6.0750, \ + 9.1125, 13.6688, 20.5031, 30.7547, 3075.4688 "); + values (" 0.01031, 0.01076, 0.01203, 0.01320, 0.01429, 0.01727, 0.02131, 0.02669, \ + 0.03314, 0.03940, 0.04368, 0.04548, 0.04571, 0.01072, 0.01116, 0.01239, \ + 0.01354, 0.01462, 0.01761, 0.02169, 0.02713, 0.03365, 0.03996, 0.04428, \ + 0.04609, 0.04633, 0.01292, 0.01331, 0.01446, 0.01557, 0.01666, 0.01975, \ + 0.02405, 0.02977, 0.03658, 0.04314, 0.04763, 0.04951, 0.04976, 0.01327, \ + 0.01366, 0.01481, 0.01592, 0.01701, 0.02012, 0.02445, 0.03021, 0.03705, \ + 0.04365, 0.04816, 0.05005, 0.05031, 0.01925, 0.01966, 0.02086, 0.02205, \ + 0.02321, 0.02657, 0.03124, 0.03736, 0.04456, 0.05145, 0.05615, 0.05812, \ + 0.05840 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: metal7; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.8000, 0.9000, 1.5000, 1.6000, 3.2000 "); + index_2 (" 0.8000, 0.9000, 1.2000, 1.5000, 1.8000, 2.7000, 4.0500, 6.0750, \ + 9.1125, 13.6688, 20.5031, 30.7547, 3075.4688 "); + values (" 0.08049, 0.07320, 0.05821, 0.04882, 0.04231, 0.03065, 0.02173, 0.01459, \ + 0.00882, 0.00444, 0.00166, 0.00039, 0.00000, 0.08124, 0.07391, 0.05883, \ + 0.04936, 0.04280, 0.03101, 0.02197, 0.01474, 0.00890, 0.00448, 0.00167, \ + 0.00039, 0.00000, 0.08472, 0.07722, 0.06172, 0.05192, 0.04507, 0.03268, \ + 0.02309, 0.01542, 0.00928, 0.00467, 0.00174, 0.00041, 0.00000, 0.08517, \ + 0.07765, 0.06209, 0.05225, 0.04537, 0.03289, 0.02323, 0.01551, 0.00933, \ + 0.00469, 0.00175, 0.00041, 0.00000, 0.08961, 0.08189, 0.06580, 0.05552, \ + 0.04827, 0.03499, 0.02462, 0.01635, 0.00980, 0.00491, 0.00183, 0.00043, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.8000, 0.9000, 1.5000, 1.6000, 3.2000 "); + index_2 (" 0.8000, 0.9000, 1.2000, 1.5000, 1.8000, 2.7000, 4.0500, 6.0750, \ + 9.1125, 13.6688, 20.5031, 30.7547, 3075.4688 "); + values (" 0.00837, 0.00875, 0.00980, 0.01075, 0.01162, 0.01395, 0.01707, 0.02136, \ + 0.02689, 0.03288, 0.03769, 0.04019, 0.04084, 0.00871, 0.00907, 0.01008, \ + 0.01101, 0.01186, 0.01418, 0.01733, 0.02167, 0.02726, 0.03330, 0.03815, \ + 0.04067, 0.04133, 0.01043, 0.01074, 0.01163, 0.01248, 0.01330, 0.01564, \ + 0.01895, 0.02353, 0.02939, 0.03569, 0.04074, 0.04336, 0.04404, 0.01069, \ + 0.01099, 0.01187, 0.01272, 0.01354, 0.01589, 0.01923, 0.02384, 0.02974, \ + 0.03607, 0.04114, 0.04378, 0.04447, 0.01492, 0.01522, 0.01612, 0.01700, \ + 0.01787, 0.02042, 0.02406, 0.02903, 0.03529, 0.04194, 0.04725, 0.05001, \ + 0.05073 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: metal6; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.8000, 0.9000, 1.5000, 1.6000, 3.2000 "); + index_2 (" 0.8000, 0.9000, 1.2000, 1.5000, 1.8000, 2.7000, 4.0500, 6.0750, \ + 9.1125, 13.6688, 20.5031, 30.7547, 3075.4688 "); + values (" 0.08085, 0.07357, 0.05861, 0.04924, 0.04276, 0.03116, 0.02232, 0.01526, \ + 0.00952, 0.00505, 0.00205, 0.00055, 0.00000, 0.08161, 0.07429, 0.05924, \ + 0.04979, 0.04325, 0.03153, 0.02258, 0.01542, 0.00961, 0.00510, 0.00207, \ + 0.00055, 0.00000, 0.08514, 0.07765, 0.06218, 0.05240, 0.04559, 0.03326, \ + 0.02376, 0.01616, 0.01004, 0.00531, 0.00216, 0.00058, 0.00000, 0.08560, \ + 0.07809, 0.06256, 0.05275, 0.04589, 0.03349, 0.02391, 0.01626, 0.01009, \ + 0.00534, 0.00217, 0.00058, 0.00000, 0.09023, 0.08252, 0.06646, 0.05620, \ + 0.04897, 0.03575, 0.02544, 0.01721, 0.01063, 0.00561, 0.00228, 0.00061, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.8000, 0.9000, 1.5000, 1.6000, 3.2000 "); + index_2 (" 0.8000, 0.9000, 1.2000, 1.5000, 1.8000, 2.7000, 4.0500, 6.0750, \ + 9.1125, 13.6688, 20.5031, 30.7547, 3075.4688 "); + values (" 0.00747, 0.00782, 0.00877, 0.00964, 0.01043, 0.01250, 0.01522, 0.01897, \ + 0.02395, 0.02965, 0.03461, 0.03751, 0.03848, 0.00778, 0.00811, 0.00903, \ + 0.00987, 0.01064, 0.01269, 0.01542, 0.01922, 0.02425, 0.03000, 0.03501, \ + 0.03793, 0.03892, 0.00933, 0.00961, 0.01039, 0.01114, 0.01185, 0.01388, \ + 0.01673, 0.02074, 0.02604, 0.03203, 0.03725, 0.04028, 0.04131, 0.00956, \ + 0.00983, 0.01060, 0.01134, 0.01206, 0.01408, 0.01696, 0.02100, 0.02633, \ + 0.03236, 0.03760, 0.04065, 0.04169, 0.01310, 0.01336, 0.01412, 0.01488, \ + 0.01562, 0.01780, 0.02094, 0.02533, 0.03101, 0.03737, 0.04287, 0.04608, \ + 0.04717 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.8000, 0.9000, 1.5000, 1.6000, 3.2000 "); + index_2 (" 0.8000, 0.9000, 1.2000, 1.5000, 1.8000, 2.7000, 4.0500, 6.0750, \ + 9.1125, 13.6688, 20.5031, 30.7547, 3075.4688 "); + values (" 0.08144, 0.07418, 0.05926, 0.04993, 0.04348, 0.03197, 0.02326, 0.01636, \ + 0.01073, 0.00621, 0.00291, 0.00096, 0.00000, 0.08222, 0.07491, 0.05990, \ + 0.05049, 0.04398, 0.03235, 0.02353, 0.01654, 0.01084, 0.00627, 0.00293, \ + 0.00097, 0.00000, 0.08582, 0.07834, 0.06290, 0.05317, 0.04639, 0.03417, \ + 0.02482, 0.01738, 0.01135, 0.00655, 0.00306, 0.00101, 0.00000, 0.08628, \ + 0.07879, 0.06330, 0.05352, 0.04671, 0.03442, 0.02499, 0.01749, 0.01141, \ + 0.00658, 0.00307, 0.00102, 0.00000, 0.09117, 0.08347, 0.06745, 0.05724, \ + 0.05006, 0.03695, 0.02677, 0.01865, 0.01212, 0.00697, 0.00325, 0.00108, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.8000, 0.9000, 1.5000, 1.6000, 3.2000 "); + index_2 (" 0.8000, 0.9000, 1.2000, 1.5000, 1.8000, 2.7000, 4.0500, 6.0750, \ + 9.1125, 13.6688, 20.5031, 30.7547, 3075.4688 "); + values (" 0.00602, 0.00632, 0.00714, 0.00789, 0.00856, 0.01029, 0.01246, 0.01538, \ + 0.01938, 0.02433, 0.02929, 0.03282, 0.03463, 0.00630, 0.00658, 0.00737, \ + 0.00809, 0.00874, 0.01044, 0.01260, 0.01554, 0.01959, 0.02459, 0.02959, \ + 0.03315, 0.03498, 0.00764, 0.00787, 0.00852, 0.00913, 0.00970, 0.01129, \ + 0.01349, 0.01659, 0.02084, 0.02607, 0.03128, 0.03500, 0.03691, 0.00783, \ + 0.00805, 0.00869, 0.00928, 0.00985, 0.01144, 0.01364, 0.01677, 0.02105, \ + 0.02631, 0.03155, 0.03528, 0.03721, 0.01050, 0.01070, 0.01127, 0.01184, \ + 0.01240, 0.01404, 0.01642, 0.01981, 0.02442, 0.03002, 0.03556, 0.03950, \ + 0.04153 "); + } + } + } + + layer (metal9) { + resistance: 0.030000 + + capacitance () { + top_plane: metal10; + bottom_plane: metal8; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.8000, 0.9000, 1.5000, 1.6000, 3.2000 "); + index_2 (" 0.8000, 0.9000, 1.2000, 1.5000, 1.8000, 2.7000, 4.0500, 6.0750, \ + 9.1125, 13.6688, 20.5031, 30.7547, 3075.4688 "); + values (" 0.06581, 0.05816, 0.04229, 0.03223, 0.02526, 0.01314, 0.00535, 0.00146, \ + 0.00022, 0.00001, 0.00000, 0.00000, 0.00000, 0.06600, 0.05833, 0.04242, \ + 0.03233, 0.02534, 0.01318, 0.00536, 0.00146, 0.00022, 0.00001, 0.00000, \ + 0.00000, 0.00000, 0.06662, 0.05889, 0.04284, 0.03266, 0.02559, 0.01332, \ + 0.00542, 0.00148, 0.00022, 0.00001, 0.00000, 0.00000, 0.00000, 0.06667, \ + 0.05894, 0.04287, 0.03268, 0.02561, 0.01333, 0.00543, 0.00148, 0.00022, \ + 0.00001, 0.00000, 0.00000, 0.00000, 0.06696, 0.05920, 0.04307, 0.03284, \ + 0.02574, 0.01340, 0.00546, 0.00149, 0.00022, 0.00001, 0.00000, 0.00000, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.8000, 0.9000, 1.5000, 1.6000, 3.2000 "); + index_2 (" 0.8000, 0.9000, 1.2000, 1.5000, 1.8000, 2.7000, 4.0500, 6.0750, \ + 9.1125, 13.6688, 20.5031, 30.7547, 3075.4688 "); + values (" 0.05787, 0.06066, 0.06849, 0.07548, 0.08172, 0.09622, 0.10872, 0.11609, \ + 0.11864, 0.11908, 0.11911, 0.11915, 0.11875, 0.06159, 0.06439, 0.07224, \ + 0.07925, 0.08552, 0.10005, 0.11259, 0.11998, 0.12255, 0.12299, 0.12302, \ + 0.12306, 0.12266, 0.08410, 0.08694, 0.09488, 0.10196, 0.10828, 0.12296, \ + 0.13562, 0.14309, 0.14568, 0.14613, 0.14616, 0.14620, 0.14580, 0.08787, \ + 0.09071, 0.09866, 0.10575, 0.11208, 0.12676, 0.13943, 0.14691, 0.14951, \ + 0.14995, 0.14998, 0.15003, 0.14962, 0.14861, 0.15147, 0.15946, 0.16658, \ + 0.17294, 0.18768, 0.20042, 0.20794, 0.21054, 0.21099, 0.21102, 0.21107, \ + 0.21066 "); + } + } + + capacitance () { + top_plane: metal10; + bottom_plane: metal7; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.8000, 0.9000, 1.5000, 1.6000, 3.2000 "); + index_2 (" 0.8000, 0.9000, 1.2000, 1.5000, 1.8000, 2.7000, 4.0500, 6.0750, \ + 9.1125, 13.6688, 20.5031, 30.7547, 3075.4688 "); + values (" 0.07181, 0.06422, 0.04843, 0.03835, 0.03125, 0.01844, 0.00919, 0.00343, \ + 0.00081, 0.00010, 0.00000, 0.00000, 0.00000, 0.07218, 0.06456, 0.04870, \ + 0.03855, 0.03142, 0.01853, 0.00924, 0.00345, 0.00082, 0.00010, 0.00000, \ + 0.00000, 0.00000, 0.07354, 0.06580, 0.04965, 0.03931, 0.03203, 0.01888, \ + 0.00941, 0.00351, 0.00083, 0.00010, 0.00000, 0.00000, 0.00000, 0.07366, \ + 0.06591, 0.04974, 0.03938, 0.03209, 0.01891, 0.00943, 0.00352, 0.00083, \ + 0.00010, 0.00000, 0.00000, 0.00000, 0.07444, 0.06662, 0.05028, 0.03981, \ + 0.03244, 0.01912, 0.00952, 0.00355, 0.00084, 0.00010, 0.00000, 0.00000, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.8000, 0.9000, 1.5000, 1.6000, 3.2000 "); + index_2 (" 0.8000, 0.9000, 1.2000, 1.5000, 1.8000, 2.7000, 4.0500, 6.0750, \ + 9.1125, 13.6688, 20.5031, 30.7547, 3075.4688 "); + values (" 0.03274, 0.03440, 0.03924, 0.04385, 0.04821, 0.05960, 0.07182, 0.08164, \ + 0.08676, 0.08825, 0.08845, 0.08849, 0.08816, 0.03458, 0.03625, 0.04113, \ + 0.04577, 0.05017, 0.06162, 0.07391, 0.08378, 0.08892, 0.09042, 0.09062, \ + 0.09066, 0.09033, 0.04599, 0.04771, 0.05274, 0.05751, 0.06201, 0.07371, \ + 0.08623, 0.09628, 0.10152, 0.10305, 0.10326, 0.10329, 0.10295, 0.04793, \ + 0.04966, 0.05470, 0.05948, 0.06399, 0.07572, 0.08826, 0.09833, 0.10358, \ + 0.10511, 0.10532, 0.10535, 0.10502, 0.07972, 0.08149, 0.08663, 0.09149, \ + 0.09606, 0.10794, 0.12062, 0.13079, 0.13609, 0.13763, 0.13785, 0.13788, \ + 0.13754 "); + } + } + + capacitance () { + top_plane: metal10; + bottom_plane: metal6; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.8000, 0.9000, 1.5000, 1.6000, 3.2000 "); + index_2 (" 0.8000, 0.9000, 1.2000, 1.5000, 1.8000, 2.7000, 4.0500, 6.0750, \ + 9.1125, 13.6688, 20.5031, 30.7547, 3075.4688 "); + values (" 0.07305, 0.06552, 0.04987, 0.03989, 0.03288, 0.02018, 0.01080, 0.00455, \ + 0.00130, 0.00021, 0.00001, 0.00000, 0.00000, 0.07350, 0.06593, 0.05019, \ + 0.04016, 0.03311, 0.02032, 0.01088, 0.00458, 0.00131, 0.00021, 0.00001, \ + 0.00000, 0.00000, 0.07525, 0.06755, 0.05149, 0.04123, 0.03400, 0.02087, \ + 0.01118, 0.00471, 0.00135, 0.00022, 0.00002, 0.00000, 0.00000, 0.07543, \ + 0.06771, 0.05163, 0.04134, 0.03409, 0.02093, 0.01121, 0.00473, 0.00136, \ + 0.00022, 0.00002, 0.00000, 0.00000, 0.07678, 0.06897, 0.05265, 0.04219, \ + 0.03480, 0.02138, 0.01146, 0.00483, 0.00139, 0.00022, 0.00002, 0.00000, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.8000, 0.9000, 1.5000, 1.6000, 3.2000 "); + index_2 (" 0.8000, 0.9000, 1.2000, 1.5000, 1.8000, 2.7000, 4.0500, 6.0750, \ + 9.1125, 13.6688, 20.5031, 30.7547, 3075.4688 "); + values (" 0.02905, 0.03048, 0.03467, 0.03866, 0.04246, 0.05254, 0.06389, 0.07393, \ + 0.08006, 0.08231, 0.08273, 0.08278, 0.08247, 0.03060, 0.03205, 0.03626, \ + 0.04028, 0.04410, 0.05425, 0.06567, 0.07578, 0.08196, 0.08422, 0.08465, \ + 0.08470, 0.08438, 0.04021, 0.04170, 0.04604, 0.05017, 0.05410, 0.06452, \ + 0.07624, 0.08661, 0.09297, 0.09530, 0.09573, 0.09579, 0.09547, 0.04185, \ + 0.04334, 0.04769, 0.05184, 0.05579, 0.06623, 0.07798, 0.08839, 0.09476, \ + 0.09710, 0.09753, 0.09759, 0.09727, 0.06886, 0.07040, 0.07486, 0.07911, \ + 0.08314, 0.09382, 0.10580, 0.11643, 0.12294, 0.12533, 0.12578, 0.12583, \ + 0.12551 "); + } + } + + capacitance () { + top_plane: metal10; + bottom_plane: metal5; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.8000, 0.9000, 1.5000, 1.6000, 3.2000 "); + index_2 (" 0.8000, 0.9000, 1.2000, 1.5000, 1.8000, 2.7000, 4.0500, 6.0750, \ + 9.1125, 13.6688, 20.5031, 30.7547, 3075.4688 "); + values (" 0.07344, 0.06592, 0.05032, 0.04039, 0.03342, 0.02080, 0.01143, 0.00504, \ + 0.00156, 0.00028, 0.00002, 0.00000, 0.00000, 0.07391, 0.06636, 0.05068, \ + 0.04069, 0.03367, 0.02096, 0.01152, 0.00508, 0.00157, 0.00029, 0.00002, \ + 0.00000, 0.00000, 0.07581, 0.06812, 0.05211, 0.04188, 0.03468, 0.02161, \ + 0.01189, 0.00525, 0.00163, 0.00030, 0.00003, 0.00000, 0.00000, 0.07601, \ + 0.06831, 0.05227, 0.04201, 0.03479, 0.02168, 0.01193, 0.00527, 0.00164, \ + 0.00030, 0.00003, 0.00000, 0.00000, 0.07763, 0.06983, 0.05353, 0.04308, \ + 0.03570, 0.02228, 0.01227, 0.00543, 0.00169, 0.00031, 0.00003, 0.00000, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.8000, 0.9000, 1.5000, 1.6000, 3.2000 "); + index_2 (" 0.8000, 0.9000, 1.2000, 1.5000, 1.8000, 2.7000, 4.0500, 6.0750, \ + 9.1125, 13.6688, 20.5031, 30.7547, 3075.4688 "); + values (" 0.02796, 0.02933, 0.03331, 0.03711, 0.04072, 0.05032, 0.06127, 0.07127, \ + 0.07775, 0.08035, 0.08090, 0.08097, 0.08066, 0.02944, 0.03081, 0.03482, \ + 0.03863, 0.04227, 0.05194, 0.06296, 0.07303, 0.07956, 0.08218, 0.08274, \ + 0.08281, 0.08250, 0.03851, 0.03992, 0.04403, 0.04796, 0.05169, 0.06162, \ + 0.07296, 0.08332, 0.09007, 0.09278, 0.09336, 0.09343, 0.09312, 0.04005, \ + 0.04147, 0.04560, 0.04953, 0.05328, 0.06324, 0.07461, 0.08501, 0.09178, \ + 0.09450, 0.09508, 0.09516, 0.09484, 0.06555, 0.06700, 0.07124, 0.07528, \ + 0.07912, 0.08933, 0.10098, 0.11166, 0.11863, 0.12144, 0.12204, 0.12211, \ + 0.12179 "); + } + } + + capacitance () { + top_plane: metal10; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.8000, 0.9000, 1.5000, 1.6000, 3.2000 "); + index_2 (" 0.8000, 0.9000, 1.2000, 1.5000, 1.8000, 2.7000, 4.0500, 6.0750, \ + 9.1125, 13.6688, 20.5031, 30.7547, 3075.4688 "); + values (" 0.07419, 0.06671, 0.05121, 0.04138, 0.03450, 0.02209, 0.01283, 0.00629, \ + 0.00234, 0.00057, 0.00007, 0.00000, 0.00000, 0.07471, 0.06719, 0.05161, \ + 0.04172, 0.03480, 0.02229, 0.01296, 0.00636, 0.00237, 0.00058, 0.00007, \ + 0.00000, 0.00000, 0.07689, 0.06924, 0.05334, 0.04321, 0.03609, 0.02320, \ + 0.01353, 0.00667, 0.00249, 0.00061, 0.00008, 0.00000, 0.00000, 0.07715, \ + 0.06948, 0.05355, 0.04338, 0.03625, 0.02331, 0.01360, 0.00670, 0.00251, \ + 0.00061, 0.00008, 0.00000, 0.00000, 0.07945, 0.07168, 0.05545, 0.04505, \ + 0.03772, 0.02437, 0.01429, 0.00708, 0.00266, 0.00065, 0.00008, 0.00000, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.8000, 0.9000, 1.5000, 1.6000, 3.2000 "); + index_2 (" 0.8000, 0.9000, 1.2000, 1.5000, 1.8000, 2.7000, 4.0500, 6.0750, \ + 9.1125, 13.6688, 20.5031, 30.7547, 3075.4688 "); + values (" 0.02595, 0.02719, 0.03081, 0.03423, 0.03747, 0.04608, 0.05604, 0.06565, \ + 0.07269, 0.07620, 0.07723, 0.07741, 0.07711, 0.02727, 0.02852, 0.03215, \ + 0.03558, 0.03884, 0.04750, 0.05753, 0.06722, 0.07433, 0.07788, 0.07892, \ + 0.07910, 0.07881, 0.03537, 0.03664, 0.04032, 0.04382, 0.04715, 0.05603, \ + 0.06637, 0.07641, 0.08384, 0.08756, 0.08867, 0.08885, 0.08855, 0.03674, \ + 0.03801, 0.04170, 0.04521, 0.04855, 0.05745, 0.06783, 0.07792, 0.08538, \ + 0.08913, 0.09024, 0.09042, 0.09013, 0.05927, 0.06056, 0.06433, 0.06792, \ + 0.07134, 0.08050, 0.09123, 0.10175, 0.10960, 0.11357, 0.11475, 0.11494, \ + 0.11464 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: metal8; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.8000, 0.9000, 1.5000, 1.6000, 3.2000 "); + index_2 (" 0.8000, 0.9000, 1.2000, 1.5000, 1.8000, 2.7000, 4.0500, 6.0750, \ + 9.1125, 13.6688, 20.5031, 30.7547, 3075.4688 "); + values (" 0.07049, 0.06302, 0.04766, 0.03806, 0.03148, 0.02010, 0.01228, 0.00708, \ + 0.00371, 0.00162, 0.00051, 0.00009, 0.00000, 0.07093, 0.06344, 0.04804, \ + 0.03841, 0.03181, 0.02038, 0.01250, 0.00723, 0.00380, 0.00166, 0.00052, \ + 0.00010, 0.00000, 0.07308, 0.06553, 0.04996, 0.04021, 0.03350, 0.02181, \ + 0.01363, 0.00803, 0.00428, 0.00188, 0.00059, 0.00011, 0.00000, 0.07338, \ + 0.06582, 0.05024, 0.04047, 0.03374, 0.02202, 0.01380, 0.00815, 0.00435, \ + 0.00192, 0.00060, 0.00011, 0.00000, 0.07713, 0.06949, 0.05368, 0.04372, \ + 0.03683, 0.02468, 0.01593, 0.00968, 0.00527, 0.00235, 0.00074, 0.00014, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.8000, 0.9000, 1.5000, 1.6000, 3.2000 "); + index_2 (" 0.8000, 0.9000, 1.2000, 1.5000, 1.8000, 2.7000, 4.0500, 6.0750, \ + 9.1125, 13.6688, 20.5031, 30.7547, 3075.4688 "); + values (" 0.04474, 0.04679, 0.05239, 0.05724, 0.06147, 0.07115, 0.08029, 0.08792, \ + 0.09365, 0.09756, 0.09977, 0.10066, 0.10051, 0.04753, 0.04957, 0.05514, \ + 0.05995, 0.06416, 0.07382, 0.08298, 0.09068, 0.09650, 0.10050, 0.10276, \ + 0.10368, 0.10353, 0.06396, 0.06593, 0.07133, 0.07602, 0.08013, 0.08970, \ + 0.09899, 0.10704, 0.11335, 0.11781, 0.12036, 0.12140, 0.12128, 0.06666, \ + 0.06862, 0.07400, 0.07867, 0.08278, 0.09233, 0.10164, 0.10975, 0.11613, \ + 0.12065, 0.12325, 0.12430, 0.12419, 0.10922, 0.11112, 0.11635, 0.12091, \ + 0.12494, 0.13447, 0.14406, 0.15282, 0.16013, 0.16553, 0.16870, 0.16998, \ + 0.16992 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: metal7; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.8000, 0.9000, 1.5000, 1.6000, 3.2000 "); + index_2 (" 0.8000, 0.9000, 1.2000, 1.5000, 1.8000, 2.7000, 4.0500, 6.0750, \ + 9.1125, 13.6688, 20.5031, 30.7547, 3075.4688 "); + values (" 0.07694, 0.06954, 0.05427, 0.04465, 0.03797, 0.02609, 0.01735, 0.01093, \ + 0.00629, 0.00308, 0.00114, 0.00027, 0.00000, 0.07755, 0.07012, 0.05477, \ + 0.04509, 0.03838, 0.02642, 0.01760, 0.01111, 0.00640, 0.00314, 0.00116, \ + 0.00027, 0.00000, 0.08035, 0.07279, 0.05714, 0.04725, 0.04036, 0.02802, \ + 0.01884, 0.01200, 0.00697, 0.00343, 0.00127, 0.00030, 0.00000, 0.08072, \ + 0.07314, 0.05746, 0.04754, 0.04063, 0.02824, 0.01902, 0.01213, 0.00705, \ + 0.00348, 0.00129, 0.00030, 0.00000, 0.08484, 0.07715, 0.06115, 0.05098, \ + 0.04385, 0.03096, 0.02120, 0.01374, 0.00809, 0.00401, 0.00149, 0.00035, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.8000, 0.9000, 1.5000, 1.6000, 3.2000 "); + index_2 (" 0.8000, 0.9000, 1.2000, 1.5000, 1.8000, 2.7000, 4.0500, 6.0750, \ + 9.1125, 13.6688, 20.5031, 30.7547, 3075.4688 "); + values (" 0.01839, 0.01930, 0.02193, 0.02437, 0.02665, 0.03254, 0.03932, 0.04638, \ + 0.05298, 0.05840, 0.06207, 0.06385, 0.06415, 0.01935, 0.02026, 0.02286, \ + 0.02527, 0.02753, 0.03340, 0.04020, 0.04731, 0.05398, 0.05949, 0.06323, \ + 0.06503, 0.06535, 0.02488, 0.02574, 0.02822, 0.03054, 0.03273, 0.03853, \ + 0.04539, 0.05274, 0.05979, 0.06572, 0.06980, 0.07177, 0.07214, 0.02577, \ + 0.02663, 0.02909, 0.03140, 0.03359, 0.03937, 0.04624, 0.05362, 0.06073, \ + 0.06673, 0.07085, 0.07285, 0.07322, 0.03966, 0.04046, 0.04282, 0.04505, \ + 0.04717, 0.05290, 0.05989, 0.06768, 0.07546, 0.08223, 0.08696, 0.08927, \ + 0.08974 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: metal6; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.8000, 0.9000, 1.5000, 1.6000, 3.2000 "); + index_2 (" 0.8000, 0.9000, 1.2000, 1.5000, 1.8000, 2.7000, 4.0500, 6.0750, \ + 9.1125, 13.6688, 20.5031, 30.7547, 3075.4688 "); + values (" 0.07849, 0.07114, 0.05600, 0.04649, 0.03989, 0.02814, 0.01939, 0.01277, \ + 0.00773, 0.00403, 0.00162, 0.00043, 0.00000, 0.07917, 0.07178, 0.05656, \ + 0.04699, 0.04035, 0.02850, 0.01966, 0.01296, 0.00786, 0.00410, 0.00165, \ + 0.00044, 0.00000, 0.08231, 0.07479, 0.05923, 0.04940, 0.04256, 0.03027, \ + 0.02103, 0.01394, 0.00849, 0.00444, 0.00179, 0.00048, 0.00000, 0.08272, \ + 0.07518, 0.05959, 0.04973, 0.04286, 0.03052, 0.02122, 0.01408, 0.00858, \ + 0.00449, 0.00181, 0.00048, 0.00000, 0.08734, 0.07965, 0.06368, 0.05351, \ + 0.04637, 0.03343, 0.02351, 0.01576, 0.00968, 0.00509, 0.00206, 0.00055, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.8000, 0.9000, 1.5000, 1.6000, 3.2000 "); + index_2 (" 0.8000, 0.9000, 1.2000, 1.5000, 1.8000, 2.7000, 4.0500, 6.0750, \ + 9.1125, 13.6688, 20.5031, 30.7547, 3075.4688 "); + values (" 0.01398, 0.01467, 0.01665, 0.01849, 0.02021, 0.02471, 0.03011, 0.03619, \ + 0.04249, 0.04829, 0.05265, 0.05502, 0.05570, 0.01467, 0.01535, 0.01730, \ + 0.01911, 0.02081, 0.02529, 0.03069, 0.03682, 0.04319, 0.04906, 0.05350, \ + 0.05590, 0.05660, 0.01854, 0.01917, 0.02097, 0.02267, 0.02429, 0.02867, \ + 0.03413, 0.04047, 0.04719, 0.05346, 0.05825, 0.06085, 0.06162, 0.01915, \ + 0.01977, 0.02155, 0.02325, 0.02486, 0.02923, 0.03470, 0.04107, 0.04783, \ + 0.05417, 0.05900, 0.06164, 0.06241, 0.02846, 0.02903, 0.03071, 0.03234, \ + 0.03390, 0.03823, 0.04383, 0.05056, 0.05791, 0.06495, 0.07040, 0.07339, \ + 0.07429 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: metal5; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.8000, 0.9000, 1.5000, 1.6000, 3.2000 "); + index_2 (" 0.8000, 0.9000, 1.2000, 1.5000, 1.8000, 2.7000, 4.0500, 6.0750, \ + 9.1125, 13.6688, 20.5031, 30.7547, 3075.4688 "); + values (" 0.07903, 0.07169, 0.05660, 0.04713, 0.04058, 0.02890, 0.02019, 0.01354, \ + 0.00839, 0.00450, 0.00189, 0.00053, 0.00000, 0.07973, 0.07236, 0.05718, \ + 0.04765, 0.04105, 0.02927, 0.02047, 0.01374, 0.00852, 0.00458, 0.00192, \ + 0.00054, 0.00000, 0.08299, 0.07548, 0.05997, 0.05017, 0.04336, 0.03113, \ + 0.02190, 0.01476, 0.00918, 0.00494, 0.00207, 0.00058, 0.00000, 0.08342, \ + 0.07590, 0.06034, 0.05052, 0.04367, 0.03139, 0.02210, 0.01490, 0.00928, \ + 0.00499, 0.00209, 0.00059, 0.00000, 0.08827, 0.08059, 0.06463, 0.05447, \ + 0.04735, 0.03442, 0.02447, 0.01664, 0.01041, 0.00562, 0.00236, 0.00067, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.8000, 0.9000, 1.5000, 1.6000, 3.2000 "); + index_2 (" 0.8000, 0.9000, 1.2000, 1.5000, 1.8000, 2.7000, 4.0500, 6.0750, \ + 9.1125, 13.6688, 20.5031, 30.7547, 3075.4688 "); + values (" 0.01254, 0.01317, 0.01495, 0.01660, 0.01813, 0.02215, 0.02700, 0.03260, \ + 0.03864, 0.04448, 0.04911, 0.05178, 0.05267, 0.01316, 0.01377, 0.01552, \ + 0.01713, 0.01865, 0.02264, 0.02749, 0.03312, 0.03923, 0.04515, 0.04985, \ + 0.05256, 0.05347, 0.01655, 0.01710, 0.01869, 0.02019, 0.02161, 0.02548, \ + 0.03037, 0.03621, 0.04265, 0.04896, 0.05401, 0.05693, 0.05793, 0.01708, \ + 0.01762, 0.01919, 0.02068, 0.02209, 0.02595, 0.03085, 0.03671, 0.04320, \ + 0.04957, 0.05467, 0.05762, 0.05863, 0.02497, 0.02547, 0.02693, 0.02834, \ + 0.02971, 0.03353, 0.03856, 0.04477, 0.05182, 0.05887, 0.06458, 0.06790, \ + 0.06906 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.8000, 0.9000, 1.5000, 1.6000, 3.2000 "); + index_2 (" 0.8000, 0.9000, 1.2000, 1.5000, 1.8000, 2.7000, 4.0500, 6.0750, \ + 9.1125, 13.6688, 20.5031, 30.7547, 3075.4688 "); + values (" 0.08020, 0.07291, 0.05793, 0.04855, 0.04208, 0.03060, 0.02207, 0.01548, \ + 0.01018, 0.00592, 0.00277, 0.00092, 0.00000, 0.08094, 0.07361, 0.05855, \ + 0.04911, 0.04259, 0.03101, 0.02238, 0.01571, 0.01033, 0.00600, 0.00281, \ + 0.00093, 0.00000, 0.08446, 0.07698, 0.06156, 0.05186, 0.04512, 0.03307, \ + 0.02397, 0.01685, 0.01109, 0.00644, 0.00301, 0.00100, 0.00000, 0.08493, \ + 0.07744, 0.06198, 0.05224, 0.04547, 0.03335, 0.02420, 0.01701, 0.01119, \ + 0.00650, 0.00304, 0.00101, 0.00000, 0.09034, 0.08268, 0.06678, 0.05668, \ + 0.04960, 0.03676, 0.02685, 0.01894, 0.01247, 0.00723, 0.00338, 0.00112, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.8000, 0.9000, 1.5000, 1.6000, 3.2000 "); + index_2 (" 0.8000, 0.9000, 1.2000, 1.5000, 1.8000, 2.7000, 4.0500, 6.0750, \ + 9.1125, 13.6688, 20.5031, 30.7547, 3075.4688 "); + values (" 0.00952, 0.01001, 0.01139, 0.01267, 0.01384, 0.01688, 0.02050, 0.02480, \ + 0.02987, 0.03545, 0.04058, 0.04407, 0.04576, 0.01000, 0.01047, 0.01182, \ + 0.01306, 0.01421, 0.01720, 0.02081, 0.02513, 0.03026, 0.03590, 0.04110, \ + 0.04464, 0.04636, 0.01253, 0.01293, 0.01410, 0.01520, 0.01624, 0.01903, \ + 0.02260, 0.02707, 0.03248, 0.03849, 0.04404, 0.04782, 0.04967, 0.01290, \ + 0.01330, 0.01445, 0.01553, 0.01655, 0.01933, 0.02289, 0.02739, 0.03284, \ + 0.03890, 0.04450, 0.04832, 0.05019, 0.01814, 0.01848, 0.01948, 0.02046, \ + 0.02140, 0.02409, 0.02775, 0.03256, 0.03852, 0.04519, 0.05139, 0.05562, \ + 0.05772 "); + } + } + } + + layer (metal8) { + resistance: 0.075000 + + capacitance () { + top_plane: metal9; + bottom_plane: metal7; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.05816, 0.04643, 0.03813, 0.02327, 0.01237, 0.01014, 0.00514, 0.00144, \ + 0.00022, 0.00002, 0.00000, 0.00000, 0.00000, 0.05862, 0.04679, 0.03843, \ + 0.02344, 0.01246, 0.01021, 0.00518, 0.00145, 0.00023, 0.00002, 0.00000, \ + 0.00000, 0.00000, 0.05924, 0.04729, 0.03883, 0.02368, 0.01258, 0.01031, \ + 0.00523, 0.00146, 0.00023, 0.00002, 0.00000, 0.00000, 0.00000, 0.05934, \ + 0.04737, 0.03889, 0.02372, 0.01260, 0.01033, 0.00524, 0.00147, 0.00023, \ + 0.00002, 0.00000, 0.00000, 0.00000, 0.05952, 0.04751, 0.03901, 0.02379, \ + 0.01264, 0.01036, 0.00525, 0.00147, 0.00023, 0.00002, 0.00000, 0.00000, \ + 0.00000, 0.05952, 0.04751, 0.03901, 0.02379, 0.01264, 0.01036, 0.00525, \ + 0.00147, 0.00023, 0.00002, 0.00000, 0.00000, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.04236, 0.04670, 0.05081, 0.06192, 0.07468, 0.07794, 0.08613, 0.09320, \ + 0.09569, 0.09613, 0.09615, 0.09588, 0.09589, 0.04754, 0.05193, 0.05608, \ + 0.06730, 0.08015, 0.08344, 0.09169, 0.09881, 0.10132, 0.10176, 0.10178, \ + 0.10151, 0.10151, 0.06340, 0.06787, 0.07209, 0.08345, 0.09645, 0.09977, \ + 0.10810, 0.11529, 0.11782, 0.11827, 0.11829, 0.11801, 0.11802, 0.06875, \ + 0.07323, 0.07746, 0.08885, 0.10186, 0.10519, 0.11354, 0.12073, 0.12327, \ + 0.12371, 0.12374, 0.12346, 0.12347, 0.10104, 0.10554, 0.10980, 0.12123, \ + 0.13429, 0.13762, 0.14599, 0.15320, 0.15575, 0.15620, 0.15622, 0.15594, \ + 0.15595, 0.10642, 0.11093, 0.11519, 0.12662, 0.13968, 0.14301, 0.15138, \ + 0.15859, 0.16114, 0.16159, 0.16161, 0.16133, 0.16134 "); + } + } + + capacitance () { + top_plane: metal9; + bottom_plane: metal6; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.06139, 0.04987, 0.04175, 0.02722, 0.01631, 0.01398, 0.00838, 0.00332, \ + 0.00088, 0.00013, 0.00001, 0.00000, 0.00000, 0.06219, 0.05055, 0.04235, \ + 0.02763, 0.01657, 0.01420, 0.00852, 0.00338, 0.00089, 0.00013, 0.00001, \ + 0.00000, 0.00000, 0.06364, 0.05181, 0.04344, 0.02840, 0.01706, 0.01462, \ + 0.00878, 0.00349, 0.00092, 0.00013, 0.00001, 0.00000, 0.00000, 0.06395, \ + 0.05208, 0.04368, 0.02857, 0.01717, 0.01472, 0.00884, 0.00352, 0.00093, \ + 0.00013, 0.00001, 0.00000, 0.00000, 0.06493, 0.05294, 0.04444, 0.02912, \ + 0.01752, 0.01503, 0.00904, 0.00360, 0.00095, 0.00014, 0.00001, 0.00000, \ + 0.00000, 0.06500, 0.05300, 0.04450, 0.02916, 0.01755, 0.01505, 0.00905, \ + 0.00361, 0.00095, 0.00014, 0.00001, 0.00000, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.03201, 0.03515, 0.03814, 0.04639, 0.05656, 0.05938, 0.06721, 0.07586, \ + 0.08061, 0.08215, 0.08240, 0.08217, 0.08217, 0.03554, 0.03871, 0.04174, \ + 0.05009, 0.06039, 0.06324, 0.07119, 0.07997, 0.08479, 0.08637, 0.08662, \ + 0.08638, 0.08639, 0.04643, 0.04967, 0.05276, 0.06130, 0.07184, 0.07477, \ + 0.08292, 0.09196, 0.09694, 0.09857, 0.09884, 0.09859, 0.09860, 0.05013, \ + 0.05338, 0.05649, 0.06508, 0.07567, 0.07861, 0.08681, 0.09590, 0.10092, \ + 0.10256, 0.10283, 0.10258, 0.10259, 0.07273, 0.07603, 0.07919, 0.08791, \ + 0.09867, 0.10167, 0.11002, 0.11930, 0.12443, 0.12611, 0.12638, 0.12614, \ + 0.12614, 0.07653, 0.07984, 0.08300, 0.09173, 0.10251, 0.10551, 0.11387, \ + 0.12316, 0.12830, 0.12999, 0.13026, 0.13002, 0.13002 "); + } + } + + capacitance () { + top_plane: metal9; + bottom_plane: metal5; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.06195, 0.05049, 0.04242, 0.02803, 0.01724, 0.01493, 0.00932, 0.00406, \ + 0.00125, 0.00023, 0.00002, 0.00000, 0.00000, 0.06283, 0.05125, 0.04309, \ + 0.02851, 0.01756, 0.01521, 0.00951, 0.00415, 0.00128, 0.00024, 0.00002, \ + 0.00000, 0.00000, 0.06450, 0.05273, 0.04441, 0.02948, 0.01823, 0.01580, \ + 0.00990, 0.00433, 0.00134, 0.00025, 0.00002, 0.00000, 0.00000, 0.06489, \ + 0.05307, 0.04472, 0.02971, 0.01838, 0.01594, 0.01000, 0.00438, 0.00136, \ + 0.00025, 0.00002, 0.00000, 0.00000, 0.06624, 0.05428, 0.04581, 0.03055, \ + 0.01896, 0.01645, 0.01035, 0.00455, 0.00141, 0.00026, 0.00002, 0.00000, \ + 0.00000, 0.06636, 0.05439, 0.04591, 0.03063, 0.01902, 0.01650, 0.01038, \ + 0.00456, 0.00142, 0.00026, 0.00002, 0.00000, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.03046, 0.03339, 0.03619, 0.04387, 0.05335, 0.05600, 0.06347, 0.07215, \ + 0.07746, 0.07954, 0.07998, 0.07978, 0.07978, 0.03374, 0.03670, 0.03951, \ + 0.04728, 0.05687, 0.05956, 0.06715, 0.07597, 0.08140, 0.08353, 0.08398, \ + 0.08377, 0.08378, 0.04381, 0.04682, 0.04969, 0.05760, 0.06743, 0.07019, \ + 0.07801, 0.08716, 0.09281, 0.09505, 0.09552, 0.09531, 0.09531, 0.04723, \ + 0.05024, 0.05312, 0.06108, 0.07096, 0.07373, 0.08161, 0.09083, 0.09655, \ + 0.09880, 0.09928, 0.09907, 0.09908, 0.06807, 0.07112, 0.07405, 0.08214, \ + 0.09222, 0.09506, 0.10313, 0.11264, 0.11857, 0.12092, 0.12142, 0.12120, \ + 0.12121, 0.07158, 0.07464, 0.07757, 0.08567, 0.09577, 0.09861, 0.10671, \ + 0.11625, 0.12219, 0.12455, 0.12505, 0.12484, 0.12485 "); + } + } + + capacitance () { + top_plane: metal9; + bottom_plane: metal4; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.06229, 0.05086, 0.04283, 0.02853, 0.01784, 0.01555, 0.00997, 0.00463, \ + 0.00160, 0.00035, 0.00004, 0.00000, 0.00000, 0.06321, 0.05167, 0.04355, \ + 0.02906, 0.01821, 0.01588, 0.01020, 0.00474, 0.00164, 0.00036, 0.00004, \ + 0.00000, 0.00000, 0.06503, 0.05329, 0.04501, 0.03017, 0.01900, 0.01659, \ + 0.01070, 0.00500, 0.00174, 0.00038, 0.00004, 0.00000, 0.00000, 0.06547, \ + 0.05368, 0.04536, 0.03045, 0.01920, 0.01677, 0.01083, 0.00507, 0.00176, \ + 0.00039, 0.00004, 0.00000, 0.00000, 0.06709, 0.05516, 0.04672, 0.03152, \ + 0.01998, 0.01747, 0.01133, 0.00534, 0.00186, 0.00041, 0.00005, 0.00000, \ + 0.00000, 0.06725, 0.05531, 0.04686, 0.03163, 0.02006, 0.01755, 0.01138, \ + 0.00536, 0.00188, 0.00042, 0.00005, 0.00000, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.02955, 0.03238, 0.03505, 0.04239, 0.05143, 0.05396, 0.06114, 0.06971, \ + 0.07533, 0.07784, 0.07849, 0.07833, 0.07834, 0.03270, 0.03553, 0.03823, \ + 0.04563, 0.05477, 0.05733, 0.06462, 0.07336, 0.07911, 0.08168, 0.08236, \ + 0.08219, 0.08220, 0.04230, 0.04516, 0.04789, 0.05542, 0.06476, 0.06739, \ + 0.07492, 0.08401, 0.09006, 0.09278, 0.09350, 0.09334, 0.09334, 0.04555, \ + 0.04842, 0.05115, 0.05871, 0.06810, 0.07075, 0.07834, 0.08751, 0.09364, \ + 0.09640, 0.09712, 0.09696, 0.09697, 0.06530, 0.06821, 0.07098, 0.07865, \ + 0.08824, 0.09095, 0.09877, 0.10831, 0.11473, 0.11765, 0.11841, 0.11825, \ + 0.11826, 0.06863, 0.07153, 0.07431, 0.08199, 0.09160, 0.09433, 0.10217, \ + 0.11174, 0.11820, 0.12113, 0.12191, 0.12175, 0.12175 "); + } + } + + capacitance () { + top_plane: metal9; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.06273, 0.05133, 0.04333, 0.02915, 0.01861, 0.01636, 0.01087, 0.00550, \ + 0.00224, 0.00065, 0.00011, 0.00001, 0.00000, 0.06369, 0.05219, 0.04411, \ + 0.02974, 0.01905, 0.01676, 0.01116, 0.00567, 0.00231, 0.00068, 0.00012, \ + 0.00001, 0.00000, 0.06568, 0.05399, 0.04576, 0.03106, 0.02004, 0.01766, \ + 0.01184, 0.00607, 0.00250, 0.00073, 0.00013, 0.00001, 0.00000, 0.06618, \ + 0.05445, 0.04618, 0.03140, 0.02030, 0.01790, 0.01202, 0.00618, 0.00255, \ + 0.00075, 0.00013, 0.00001, 0.00000, 0.06820, 0.05632, 0.04792, 0.03284, \ + 0.02143, 0.01894, 0.01282, 0.00667, 0.00278, 0.00082, 0.00014, 0.00001, \ + 0.00000, 0.06842, 0.05653, 0.04812, 0.03301, 0.02156, 0.01907, 0.01292, \ + 0.00673, 0.00281, 0.00083, 0.00015, 0.00001, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.02841, 0.03112, 0.03367, 0.04061, 0.04908, 0.05144, 0.05819, 0.06644, \ + 0.07231, 0.07542, 0.07653, 0.07651, 0.07653, 0.03142, 0.03412, 0.03668, \ + 0.04365, 0.05218, 0.05458, 0.06142, 0.06983, 0.07586, 0.07908, 0.08023, \ + 0.08022, 0.08024, 0.04050, 0.04319, 0.04575, 0.05278, 0.06147, 0.06392, \ + 0.07097, 0.07976, 0.08616, 0.08962, 0.09087, 0.09087, 0.09090, 0.04354, \ + 0.04623, 0.04880, 0.05584, 0.06456, 0.06703, 0.07414, 0.08302, 0.08952, \ + 0.09305, 0.09433, 0.09434, 0.09436, 0.06195, 0.06465, 0.06723, 0.07433, \ + 0.08321, 0.08574, 0.09308, 0.10240, 0.10934, 0.11317, 0.11457, 0.11460, \ + 0.11462, 0.06504, 0.06774, 0.07031, 0.07742, 0.08632, 0.08886, 0.09624, \ + 0.10561, 0.11260, 0.11647, 0.11788, 0.11791, 0.11794 "); + } + } + + capacitance () { + top_plane: metal10; + bottom_plane: metal7; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.06281, 0.05142, 0.04343, 0.02927, 0.01876, 0.01652, 0.01104, 0.00569, \ + 0.00239, 0.00074, 0.00014, 0.00001, 0.00000, 0.06378, 0.05229, 0.04422, \ + 0.02987, 0.01921, 0.01693, 0.01135, 0.00587, 0.00248, 0.00077, 0.00015, \ + 0.00001, 0.00000, 0.06581, 0.05412, 0.04590, 0.03123, 0.02024, 0.01787, \ + 0.01207, 0.00631, 0.00269, 0.00084, 0.00016, 0.00001, 0.00000, 0.06632, \ + 0.05459, 0.04634, 0.03158, 0.02052, 0.01813, 0.01227, 0.00643, 0.00275, \ + 0.00086, 0.00017, 0.00001, 0.00000, 0.06842, 0.05655, 0.04816, 0.03311, \ + 0.02172, 0.01925, 0.01314, 0.00698, 0.00301, 0.00095, 0.00018, 0.00002, \ + 0.00000, 0.06865, 0.05677, 0.04838, 0.03329, 0.02187, 0.01939, 0.01325, \ + 0.00704, 0.00305, 0.00096, 0.00019, 0.00002, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.02819, 0.03088, 0.03342, 0.04030, 0.04866, 0.05099, 0.05764, 0.06581, \ + 0.07169, 0.07492, 0.07615, 0.07618, 0.07621, 0.03119, 0.03387, 0.03640, \ + 0.04330, 0.05172, 0.05408, 0.06083, 0.06916, 0.07520, 0.07854, 0.07982, \ + 0.07986, 0.07989, 0.04018, 0.04284, 0.04538, 0.05231, 0.06087, 0.06329, \ + 0.07024, 0.07894, 0.08537, 0.08898, 0.09036, 0.09043, 0.09046, 0.04319, \ + 0.04585, 0.04838, 0.05533, 0.06392, 0.06635, 0.07336, 0.08215, 0.08869, \ + 0.09237, 0.09379, 0.09386, 0.09390, 0.06135, 0.06402, 0.06655, 0.07354, \ + 0.08228, 0.08477, 0.09201, 0.10124, 0.10825, 0.11227, 0.11384, 0.11394, \ + 0.11398, 0.06440, 0.06706, 0.06959, 0.07659, 0.08535, 0.08784, 0.09511, \ + 0.10440, 0.11147, 0.11553, 0.11711, 0.11722, 0.11726 "); + } + } + + capacitance () { + top_plane: metal10; + bottom_plane: metal6; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.06641, 0.05523, 0.04741, 0.03357, 0.02319, 0.02091, 0.01515, 0.00893, \ + 0.00440, 0.00164, 0.00040, 0.00005, 0.00000, 0.06769, 0.05638, 0.04845, \ + 0.03439, 0.02379, 0.02146, 0.01557, 0.00918, 0.00453, 0.00169, 0.00041, \ + 0.00005, 0.00000, 0.07046, 0.05890, 0.05077, 0.03622, 0.02515, 0.02271, \ + 0.01651, 0.00976, 0.00484, 0.00181, 0.00044, 0.00005, 0.00000, 0.07117, \ + 0.05954, 0.05136, 0.03669, 0.02551, 0.02303, 0.01675, 0.00992, 0.00492, \ + 0.00184, 0.00045, 0.00006, 0.00000, 0.07398, 0.06213, 0.05375, 0.03863, \ + 0.02698, 0.02439, 0.01780, 0.01058, 0.00527, 0.00198, 0.00048, 0.00006, \ + 0.00000, 0.07428, 0.06241, 0.05401, 0.03885, 0.02715, 0.02455, 0.01792, \ + 0.01066, 0.00531, 0.00200, 0.00049, 0.00006, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.01697, 0.01849, 0.01993, 0.02391, 0.02916, 0.03075, 0.03572, 0.04313, \ + 0.05013, 0.05516, 0.05763, 0.05816, 0.05827, 0.01842, 0.01990, 0.02131, \ + 0.02529, 0.03059, 0.03220, 0.03727, 0.04485, 0.05202, 0.05719, 0.05974, \ + 0.06028, 0.06039, 0.02264, 0.02408, 0.02548, 0.02949, 0.03495, 0.03662, \ + 0.04190, 0.04984, 0.05741, 0.06291, 0.06563, 0.06623, 0.06635, 0.02405, \ + 0.02549, 0.02689, 0.03092, 0.03642, 0.03810, 0.04344, 0.05148, 0.05916, \ + 0.06474, 0.06751, 0.06812, 0.06824, 0.03272, 0.03418, 0.03560, 0.03973, \ + 0.04542, 0.04717, 0.05274, 0.06119, 0.06931, 0.07527, 0.07825, 0.07892, \ + 0.07904, 0.03420, 0.03566, 0.03709, 0.04123, 0.04694, 0.04870, 0.05430, \ + 0.06279, 0.07097, 0.07697, 0.07998, 0.08065, 0.08078 "); + } + } + + capacitance () { + top_plane: metal10; + bottom_plane: metal5; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.06713, 0.05600, 0.04823, 0.03452, 0.02428, 0.02203, 0.01633, 0.01005, \ + 0.00526, 0.00212, 0.00057, 0.00008, 0.00000, 0.06847, 0.05722, 0.04934, \ + 0.03541, 0.02494, 0.02264, 0.01679, 0.01034, 0.00541, 0.00218, 0.00059, \ + 0.00008, 0.00000, 0.07145, 0.05993, 0.05185, 0.03742, 0.02646, 0.02403, \ + 0.01785, 0.01100, 0.00577, 0.00233, 0.00063, 0.00009, 0.00000, 0.07222, \ + 0.06064, 0.05250, 0.03794, 0.02685, 0.02440, 0.01813, 0.01118, 0.00587, \ + 0.00237, 0.00064, 0.00009, 0.00000, 0.07536, 0.06354, 0.05519, 0.04013, \ + 0.02853, 0.02594, 0.01931, 0.01193, 0.00628, 0.00254, 0.00069, 0.00010, \ + 0.00000, 0.07571, 0.06386, 0.05549, 0.04038, 0.02872, 0.02612, 0.01945, \ + 0.01202, 0.00632, 0.00256, 0.00069, 0.00010, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.01503, 0.01637, 0.01762, 0.02105, 0.02554, 0.02691, 0.03126, 0.03804, \ + 0.04497, 0.05048, 0.05351, 0.05433, 0.05450, 0.01627, 0.01755, 0.01877, \ + 0.02216, 0.02668, 0.02807, 0.03251, 0.03945, 0.04655, 0.05221, 0.05533, \ + 0.05618, 0.05636, 0.01975, 0.02097, 0.02215, 0.02553, 0.03017, 0.03161, \ + 0.03625, 0.04356, 0.05107, 0.05709, 0.06042, 0.06133, 0.06152, 0.02090, \ + 0.02210, 0.02328, 0.02667, 0.03136, 0.03281, 0.03751, 0.04491, 0.05254, \ + 0.05864, 0.06203, 0.06296, 0.06315, 0.02789, 0.02911, 0.03031, 0.03379, \ + 0.03866, 0.04019, 0.04512, 0.05295, 0.06104, 0.06755, 0.07117, 0.07219, \ + 0.07239, 0.02909, 0.03031, 0.03151, 0.03501, 0.03991, 0.04144, 0.04640, \ + 0.05428, 0.06242, 0.06899, 0.07264, 0.07366, 0.07387 "); + } + } + + capacitance () { + top_plane: metal10; + bottom_plane: metal4; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.06761, 0.05651, 0.04876, 0.03514, 0.02500, 0.02279, 0.01716, 0.01090, \ + 0.00598, 0.00257, 0.00076, 0.00012, 0.00000, 0.06898, 0.05776, 0.04992, \ + 0.03607, 0.02571, 0.02344, 0.01766, 0.01121, 0.00615, 0.00265, 0.00078, \ + 0.00013, 0.00000, 0.07208, 0.06060, 0.05254, 0.03821, 0.02735, 0.02494, \ + 0.01882, 0.01196, 0.00656, 0.00282, 0.00083, 0.00013, 0.00000, 0.07289, \ + 0.06135, 0.05324, 0.03877, 0.02778, 0.02534, 0.01912, 0.01215, 0.00667, \ + 0.00287, 0.00085, 0.00014, 0.00000, 0.07629, 0.06449, 0.05617, 0.04118, \ + 0.02964, 0.02706, 0.02045, 0.01301, 0.00715, 0.00308, 0.00091, 0.00015, \ + 0.00000, 0.07667, 0.06485, 0.05650, 0.04145, 0.02985, 0.02726, 0.02061, \ + 0.01311, 0.00720, 0.00310, 0.00091, 0.00015, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.01380, 0.01502, 0.01617, 0.01927, 0.02329, 0.02451, 0.02841, 0.03465, \ + 0.04137, 0.04713, 0.05062, 0.05174, 0.05200, 0.01492, 0.01609, 0.01719, \ + 0.02023, 0.02426, 0.02549, 0.02947, 0.03586, 0.04275, 0.04868, 0.05227, \ + 0.05342, 0.05369, 0.01800, 0.01908, 0.02012, 0.02311, 0.02721, 0.02849, \ + 0.03266, 0.03940, 0.04671, 0.05301, 0.05684, 0.05808, 0.05836, 0.01899, \ + 0.02005, 0.02109, 0.02408, 0.02822, 0.02951, 0.03373, 0.04056, 0.04798, \ + 0.05439, 0.05828, 0.05954, 0.05983, 0.02497, 0.02603, 0.02708, 0.03014, \ + 0.03445, 0.03581, 0.04026, 0.04752, 0.05543, 0.06227, 0.06643, 0.06780, \ + 0.06811, 0.02599, 0.02706, 0.02811, 0.03118, 0.03551, 0.03688, 0.04136, \ + 0.04868, 0.05664, 0.06353, 0.06773, 0.06911, 0.06942 "); + } + } + + capacitance () { + top_plane: metal10; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.06830, 0.05723, 0.04952, 0.03600, 0.02601, 0.02384, 0.01835, 0.01221, \ + 0.00722, 0.00348, 0.00121, 0.00025, 0.00000, 0.06971, 0.05852, 0.05071, \ + 0.03698, 0.02678, 0.02455, 0.01891, 0.01258, 0.00744, 0.00359, 0.00124, \ + 0.00025, 0.00000, 0.07293, 0.06150, 0.05349, 0.03928, 0.02859, 0.02624, \ + 0.02024, 0.01347, 0.00797, 0.00384, 0.00133, 0.00027, 0.00000, 0.07380, \ + 0.06231, 0.05424, 0.03991, 0.02908, 0.02669, 0.02060, 0.01371, 0.00811, \ + 0.00391, 0.00135, 0.00028, 0.00000, 0.07755, 0.06580, 0.05752, 0.04265, \ + 0.03126, 0.02872, 0.02220, 0.01478, 0.00874, 0.00421, 0.00146, 0.00030, \ + 0.00000, 0.07799, 0.06622, 0.05791, 0.04298, 0.03152, 0.02896, 0.02239, \ + 0.01492, 0.00881, 0.00424, 0.00147, 0.00030, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.01206, 0.01316, 0.01418, 0.01691, 0.02035, 0.02137, 0.02465, 0.02998, \ + 0.03610, 0.04200, 0.04620, 0.04796, 0.04848, 0.01308, 0.01411, 0.01508, \ + 0.01771, 0.02111, 0.02214, 0.02546, 0.03092, 0.03720, 0.04327, 0.04760, \ + 0.04941, 0.04994, 0.01572, 0.01664, 0.01752, 0.02001, 0.02340, 0.02446, \ + 0.02791, 0.03367, 0.04036, 0.04683, 0.05145, 0.05340, 0.05397, 0.01653, \ + 0.01743, 0.01830, 0.02077, 0.02418, 0.02524, 0.02874, 0.03459, 0.04139, \ + 0.04797, 0.05267, 0.05465, 0.05523, 0.02127, 0.02214, 0.02299, 0.02547, \ + 0.02899, 0.03011, 0.03381, 0.04006, 0.04736, 0.05443, 0.05949, 0.06163, \ + 0.06225, 0.02207, 0.02294, 0.02379, 0.02628, 0.02981, 0.03094, 0.03467, \ + 0.04097, 0.04834, 0.05547, 0.06057, 0.06274, 0.06336 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: metal7; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.06381, 0.05246, 0.04450, 0.03044, 0.02007, 0.01787, 0.01253, 0.00733, \ + 0.00403, 0.00211, 0.00104, 0.00045, 0.00000, 0.06481, 0.05336, 0.04532, \ + 0.03110, 0.02060, 0.01837, 0.01294, 0.00763, 0.00424, 0.00224, 0.00111, \ + 0.00048, 0.00000, 0.06696, 0.05534, 0.04716, 0.03265, 0.02188, 0.01958, \ + 0.01398, 0.00842, 0.00478, 0.00258, 0.00130, 0.00056, 0.00000, 0.06753, \ + 0.05587, 0.04766, 0.03308, 0.02225, 0.01994, 0.01429, 0.00866, 0.00495, \ + 0.00269, 0.00136, 0.00059, 0.00000, 0.07010, 0.05831, 0.05001, 0.03518, \ + 0.02410, 0.02172, 0.01585, 0.00992, 0.00587, 0.00329, 0.00170, 0.00075, \ + 0.00000, 0.07044, 0.05863, 0.05032, 0.03547, 0.02436, 0.02197, 0.01608, \ + 0.01011, 0.00601, 0.00338, 0.00176, 0.00077, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.02565, 0.02821, 0.03061, 0.03713, 0.04497, 0.04713, 0.05326, 0.06070, \ + 0.06623, 0.06975, 0.07182, 0.07279, 0.07370, 0.02855, 0.03109, 0.03348, \ + 0.03997, 0.04780, 0.04997, 0.05612, 0.06366, 0.06932, 0.07298, 0.07515, \ + 0.07619, 0.07716, 0.03715, 0.03964, 0.04199, 0.04839, 0.05616, 0.05833, \ + 0.06453, 0.07226, 0.07824, 0.08225, 0.08471, 0.08594, 0.08709, 0.03999, \ + 0.04246, 0.04480, 0.05117, 0.05892, 0.06109, 0.06729, 0.07508, 0.08115, \ + 0.08526, 0.08781, 0.08910, 0.09031, 0.05674, 0.05914, 0.06142, 0.06762, \ + 0.07525, 0.07740, 0.08363, 0.09165, 0.09817, 0.10280, 0.10583, 0.10748, \ + 0.10900, 0.05949, 0.06188, 0.06415, 0.07033, 0.07794, 0.08009, 0.08633, \ + 0.09438, 0.10095, 0.10567, 0.10876, 0.11047, 0.11204 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: metal6; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.06776, 0.05663, 0.04885, 0.03513, 0.02489, 0.02267, 0.01709, 0.01116, \ + 0.00684, 0.00391, 0.00206, 0.00095, 0.00000, 0.06907, 0.05781, 0.04993, \ + 0.03599, 0.02557, 0.02330, 0.01761, 0.01154, 0.00710, 0.00408, 0.00216, \ + 0.00099, 0.00000, 0.07196, 0.06045, 0.05237, 0.03799, 0.02717, 0.02480, \ + 0.01886, 0.01250, 0.00780, 0.00454, 0.00244, 0.00113, 0.00000, 0.07272, \ + 0.06115, 0.05302, 0.03854, 0.02761, 0.02522, 0.01922, 0.01278, 0.00800, \ + 0.00468, 0.00252, 0.00117, 0.00000, 0.07597, 0.06420, 0.05590, 0.04102, \ + 0.02972, 0.02723, 0.02096, 0.01419, 0.00907, 0.00543, 0.00297, 0.00139, \ + 0.00000, 0.07637, 0.06458, 0.05626, 0.04134, 0.03000, 0.02750, 0.02121, \ + 0.01439, 0.00923, 0.00554, 0.00304, 0.00143, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.01359, 0.01495, 0.01624, 0.01983, 0.02449, 0.02588, 0.03016, 0.03635, \ + 0.04219, 0.04690, 0.05022, 0.05218, 0.05408, 0.01495, 0.01627, 0.01753, \ + 0.02108, 0.02572, 0.02711, 0.03140, 0.03765, 0.04359, 0.04843, 0.05186, \ + 0.05393, 0.05592, 0.01882, 0.02008, 0.02130, 0.02475, 0.02934, 0.03072, \ + 0.03502, 0.04138, 0.04756, 0.05271, 0.05646, 0.05878, 0.06103, 0.02008, \ + 0.02132, 0.02253, 0.02596, 0.03053, 0.03191, 0.03621, 0.04259, 0.04883, \ + 0.05407, 0.05791, 0.06031, 0.06264, 0.02741, 0.02860, 0.02976, 0.03308, \ + 0.03755, 0.03891, 0.04319, 0.04966, 0.05617, 0.06184, 0.06616, 0.06897, \ + 0.07175, 0.02861, 0.02979, 0.03095, 0.03424, 0.03870, 0.04006, 0.04433, \ + 0.05081, 0.05736, 0.06309, 0.06748, 0.07035, 0.07320 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: metal5; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.06863, 0.05756, 0.04984, 0.03625, 0.02616, 0.02397, 0.01846, 0.01250, \ + 0.00799, 0.00476, 0.00260, 0.00124, 0.00000, 0.07001, 0.05881, 0.05098, \ + 0.03718, 0.02689, 0.02465, 0.01901, 0.01291, 0.00828, 0.00495, 0.00272, \ + 0.00129, 0.00000, 0.07310, 0.06165, 0.05361, 0.03935, 0.02864, 0.02629, \ + 0.02038, 0.01396, 0.00904, 0.00547, 0.00303, 0.00145, 0.00000, 0.07392, \ + 0.06240, 0.05432, 0.03994, 0.02912, 0.02675, 0.02077, 0.01426, 0.00927, \ + 0.00562, 0.00313, 0.00150, 0.00000, 0.07750, 0.06575, 0.05748, 0.04267, \ + 0.03141, 0.02893, 0.02265, 0.01576, 0.01041, 0.00643, 0.00363, 0.00176, \ + 0.00000, 0.07793, 0.06617, 0.05788, 0.04302, 0.03172, 0.02922, 0.02291, \ + 0.01598, 0.01058, 0.00655, 0.00371, 0.00180, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.01129, 0.01243, 0.01352, 0.01652, 0.02043, 0.02159, 0.02523, 0.03067, \ + 0.03615, 0.04097, 0.04467, 0.04707, 0.04953, 0.01242, 0.01352, 0.01457, \ + 0.01751, 0.02138, 0.02254, 0.02617, 0.03165, 0.03722, 0.04216, 0.04599, \ + 0.04850, 0.05107, 0.01556, 0.01658, 0.01758, 0.02039, 0.02416, 0.02531, \ + 0.02894, 0.03450, 0.04027, 0.04551, 0.04965, 0.05243, 0.05530, 0.01655, \ + 0.01756, 0.01854, 0.02133, 0.02508, 0.02622, 0.02984, 0.03542, 0.04125, \ + 0.04657, 0.05080, 0.05366, 0.05663, 0.02226, 0.02321, 0.02414, 0.02680, \ + 0.03044, 0.03156, 0.03516, 0.04080, 0.04687, 0.05258, 0.05727, 0.06056, \ + 0.06404, 0.02318, 0.02412, 0.02505, 0.02769, 0.03132, 0.03244, 0.03603, \ + 0.04168, 0.04777, 0.05354, 0.05830, 0.06166, 0.06521 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: metal4; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.06924, 0.05821, 0.05052, 0.03704, 0.02706, 0.02489, 0.01945, 0.01353, \ + 0.00894, 0.00553, 0.00313, 0.00153, 0.00000, 0.07066, 0.05950, 0.05171, \ + 0.03800, 0.02783, 0.02561, 0.02004, 0.01398, 0.00926, 0.00574, 0.00326, \ + 0.00160, 0.00000, 0.07388, 0.06246, 0.05446, 0.04029, 0.02968, 0.02736, \ + 0.02151, 0.01510, 0.01008, 0.00631, 0.00361, 0.00178, 0.00000, 0.07475, \ + 0.06326, 0.05521, 0.04092, 0.03020, 0.02785, 0.02192, 0.01542, 0.01033, \ + 0.00647, 0.00371, 0.00184, 0.00000, 0.07855, 0.06684, 0.05859, 0.04384, \ + 0.03265, 0.03018, 0.02393, 0.01702, 0.01155, 0.00734, 0.00427, 0.00213, \ + 0.00000, 0.07902, 0.06729, 0.05902, 0.04422, 0.03298, 0.03050, 0.02421, \ + 0.01725, 0.01173, 0.00747, 0.00435, 0.00217, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.00974, 0.01075, 0.01170, 0.01434, 0.01775, 0.01877, 0.02195, 0.02678, \ + 0.03184, 0.03658, 0.04052, 0.04328, 0.04630, 0.01073, 0.01170, 0.01262, \ + 0.01518, 0.01854, 0.01955, 0.02271, 0.02757, 0.03270, 0.03756, 0.04162, \ + 0.04449, 0.04764, 0.01344, 0.01432, 0.01518, 0.01759, 0.02083, 0.02181, \ + 0.02494, 0.02985, 0.03515, 0.04029, 0.04466, 0.04781, 0.05131, 0.01428, \ + 0.01515, 0.01599, 0.01836, 0.02157, 0.02255, 0.02567, 0.03058, 0.03594, \ + 0.04115, 0.04561, 0.04885, 0.05245, 0.01902, 0.01982, 0.02060, 0.02283, \ + 0.02590, 0.02686, 0.02994, 0.03489, 0.04045, 0.04602, 0.05093, 0.05461, \ + 0.05878, 0.01977, 0.02056, 0.02133, 0.02355, 0.02661, 0.02756, 0.03063, \ + 0.03559, 0.04118, 0.04680, 0.05177, 0.05552, 0.05977 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.07015, 0.05919, 0.05156, 0.03822, 0.02842, 0.02630, 0.02099, 0.01521, \ + 0.01063, 0.00702, 0.00426, 0.00225, 0.00000, 0.07164, 0.06054, 0.05281, \ + 0.03924, 0.02924, 0.02708, 0.02164, 0.01571, 0.01100, 0.00728, 0.00443, \ + 0.00234, 0.00000, 0.07504, 0.06368, 0.05573, 0.04170, 0.03125, 0.02898, \ + 0.02326, 0.01697, 0.01194, 0.00794, 0.00485, 0.00257, 0.00000, 0.07596, \ + 0.06454, 0.05654, 0.04239, 0.03182, 0.02952, 0.02372, 0.01733, 0.01221, \ + 0.00814, 0.00498, 0.00264, 0.00000, 0.08010, 0.06844, 0.06024, 0.04561, \ + 0.03456, 0.03213, 0.02597, 0.01914, 0.01360, 0.00914, 0.00563, 0.00301, \ + 0.00000, 0.08063, 0.06894, 0.06072, 0.04604, 0.03493, 0.03248, 0.02628, \ + 0.01939, 0.01380, 0.00928, 0.00573, 0.00306, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.00743, 0.00824, 0.00901, 0.01115, 0.01390, 0.01472, 0.01726, 0.02113, \ + 0.02531, 0.02958, 0.03363, 0.03694, 0.04126, 0.00824, 0.00902, 0.00976, \ + 0.01182, 0.01450, 0.01530, 0.01780, 0.02166, 0.02588, 0.03025, 0.03441, \ + 0.03784, 0.04232, 0.01041, 0.01111, 0.01178, 0.01367, 0.01618, 0.01694, \ + 0.01936, 0.02318, 0.02751, 0.03210, 0.03655, 0.04028, 0.04519, 0.01107, \ + 0.01175, 0.01240, 0.01425, 0.01671, 0.01747, 0.01986, 0.02368, 0.02803, \ + 0.03269, 0.03722, 0.04103, 0.04608, 0.01462, 0.01522, 0.01580, 0.01746, \ + 0.01974, 0.02045, 0.02275, 0.02653, 0.03103, 0.03598, 0.04093, 0.04519, \ + 0.05092, 0.01516, 0.01575, 0.01632, 0.01796, 0.02022, 0.02093, 0.02321, \ + 0.02700, 0.03151, 0.03651, 0.04151, 0.04583, 0.05167 "); + } + } + } + + layer (metal7) { + resistance: 0.075000 + + capacitance () { + top_plane: metal8; + bottom_plane: metal6; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.05185, 0.04018, 0.03202, 0.01780, 0.00815, 0.00635, 0.00269, 0.00054, \ + 0.00005, 0.00000, 0.00000, 0.00000, 0.00000, 0.05209, 0.04038, 0.03218, \ + 0.01789, 0.00820, 0.00639, 0.00271, 0.00054, 0.00005, 0.00000, 0.00000, \ + 0.00000, 0.00000, 0.05240, 0.04063, 0.03239, 0.01801, 0.00826, 0.00643, \ + 0.00273, 0.00055, 0.00005, 0.00000, 0.00000, 0.00000, 0.00000, 0.05246, \ + 0.04067, 0.03242, 0.01803, 0.00827, 0.00644, 0.00273, 0.00055, 0.00005, \ + 0.00000, 0.00000, 0.00000, 0.00000, 0.05255, 0.04075, 0.03248, 0.01807, \ + 0.00828, 0.00646, 0.00274, 0.00055, 0.00005, 0.00000, 0.00000, 0.00000, \ + 0.00000, 0.05255, 0.04074, 0.03248, 0.01807, 0.00828, 0.00646, 0.00274, \ + 0.00055, 0.00005, 0.00000, 0.00000, 0.00000, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.07642, 0.08310, 0.08902, 0.10356, 0.11751, 0.12060, 0.12729, 0.13174, \ + 0.13275, 0.13284, 0.13282, 0.13255, 0.13256, 0.08664, 0.09335, 0.09930, \ + 0.11389, 0.12791, 0.13101, 0.13774, 0.14222, 0.14323, 0.14332, 0.14330, \ + 0.14303, 0.14303, 0.11745, 0.12420, 0.13019, 0.14488, 0.15898, 0.16210, \ + 0.16888, 0.17338, 0.17441, 0.17450, 0.17448, 0.17420, 0.17421, 0.12776, \ + 0.13452, 0.14051, 0.15521, 0.16932, 0.17245, 0.17923, 0.18375, 0.18477, \ + 0.18486, 0.18485, 0.18457, 0.18457, 0.18970, 0.19647, 0.20248, 0.21720, \ + 0.23134, 0.23448, 0.24127, 0.24579, 0.24682, 0.24691, 0.24690, 0.24661, \ + 0.24662, 0.20002, 0.20679, 0.21279, 0.22752, 0.24165, 0.24479, 0.25158, \ + 0.25611, 0.25714, 0.25723, 0.25721, 0.25693, 0.25694 "); + } + } + + capacitance () { + top_plane: metal8; + bottom_plane: metal5; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.05836, 0.04664, 0.03835, 0.02350, 0.01258, 0.01034, 0.00530, 0.00151, \ + 0.00024, 0.00002, 0.00000, 0.00000, 0.00000, 0.05884, 0.04701, 0.03866, \ + 0.02368, 0.01268, 0.01042, 0.00534, 0.00152, 0.00024, 0.00002, 0.00000, \ + 0.00000, 0.00000, 0.05950, 0.04754, 0.03909, 0.02394, 0.01281, 0.01053, \ + 0.00539, 0.00154, 0.00024, 0.00002, 0.00000, 0.00000, 0.00000, 0.05960, \ + 0.04763, 0.03916, 0.02398, 0.01283, 0.01055, 0.00540, 0.00154, 0.00025, \ + 0.00002, 0.00000, 0.00000, 0.00000, 0.05981, 0.04779, 0.03929, 0.02406, \ + 0.01287, 0.01058, 0.00542, 0.00154, 0.00025, 0.00002, 0.00000, 0.00000, \ + 0.00000, 0.05981, 0.04779, 0.03929, 0.02406, 0.01287, 0.01058, 0.00542, \ + 0.00154, 0.00025, 0.00002, 0.00000, 0.00000, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.04148, 0.04573, 0.04976, 0.06068, 0.07330, 0.07655, 0.08476, 0.09195, \ + 0.09454, 0.09501, 0.09504, 0.09477, 0.09477, 0.04652, 0.05082, 0.05490, \ + 0.06593, 0.07865, 0.08192, 0.09020, 0.09743, 0.10005, 0.10052, 0.10055, \ + 0.10028, 0.10028, 0.06198, 0.06636, 0.07051, 0.08169, 0.09456, 0.09787, \ + 0.10623, 0.11354, 0.11619, 0.11667, 0.11669, 0.11642, 0.11642, 0.06720, \ + 0.07160, 0.07576, 0.08696, 0.09985, 0.10317, 0.11154, 0.11886, 0.12151, \ + 0.12199, 0.12202, 0.12174, 0.12175, 0.09873, 0.10315, 0.10733, 0.11858, \ + 0.13152, 0.13485, 0.14325, 0.15059, 0.15325, 0.15373, 0.15376, 0.15348, \ + 0.15348, 0.10399, 0.10841, 0.11259, 0.12385, 0.13679, 0.14011, 0.14851, \ + 0.15586, 0.15851, 0.15899, 0.15902, 0.15874, 0.15875 "); + } + } + + capacitance () { + top_plane: metal8; + bottom_plane: metal4; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.06051, 0.04891, 0.04073, 0.02605, 0.01505, 0.01272, 0.00723, 0.00255, \ + 0.00056, 0.00006, 0.00000, 0.00000, 0.00000, 0.06120, 0.04949, 0.04122, \ + 0.02637, 0.01524, 0.01288, 0.00732, 0.00259, 0.00057, 0.00006, 0.00000, \ + 0.00000, 0.00000, 0.06235, 0.05046, 0.04205, 0.02692, 0.01556, 0.01315, \ + 0.00748, 0.00264, 0.00058, 0.00006, 0.00000, 0.00000, 0.00000, 0.06258, \ + 0.05066, 0.04222, 0.02703, 0.01563, 0.01321, 0.00751, 0.00265, 0.00058, \ + 0.00006, 0.00000, 0.00000, 0.00000, 0.06320, 0.05118, 0.04267, 0.02732, \ + 0.01580, 0.01336, 0.00760, 0.00269, 0.00059, 0.00007, 0.00000, 0.00000, \ + 0.00000, 0.06322, 0.05120, 0.04269, 0.02734, 0.01581, 0.01337, 0.00761, \ + 0.00269, 0.00059, 0.00007, 0.00000, 0.00000, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.03447, 0.03792, 0.04121, 0.05028, 0.06133, 0.06434, 0.07248, 0.08082, \ + 0.08477, 0.08581, 0.08593, 0.08568, 0.08568, 0.03840, 0.04189, 0.04523, \ + 0.05442, 0.06559, 0.06864, 0.07687, 0.08531, 0.08932, 0.09037, 0.09049, \ + 0.09024, 0.09024, 0.05054, 0.05412, 0.05753, 0.06692, 0.07833, 0.08143, \ + 0.08983, 0.09844, 0.10254, 0.10362, 0.10375, 0.10348, 0.10349, 0.05467, \ + 0.05826, 0.06169, 0.07112, 0.08257, 0.08568, 0.09412, 0.10277, 0.10688, \ + 0.10796, 0.10809, 0.10783, 0.10783, 0.07980, 0.08343, 0.08691, 0.09645, \ + 0.10802, 0.11117, 0.11969, 0.12844, 0.13260, 0.13370, 0.13383, 0.13356, \ + 0.13357, 0.08401, 0.08765, 0.09113, 0.10068, 0.11226, 0.11541, 0.12394, \ + 0.13269, 0.13686, 0.13795, 0.13808, 0.13782, 0.13782 "); + } + } + + capacitance () { + top_plane: metal8; + bottom_plane: metal3; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.06124, 0.04971, 0.04159, 0.02704, 0.01612, 0.01379, 0.00820, 0.00320, \ + 0.00082, 0.00011, 0.00001, 0.00000, 0.00000, 0.06202, 0.05038, 0.04217, \ + 0.02744, 0.01637, 0.01400, 0.00834, 0.00325, 0.00083, 0.00012, 0.00001, \ + 0.00000, 0.00000, 0.06344, 0.05160, 0.04323, 0.02818, 0.01683, 0.01441, \ + 0.00859, 0.00336, 0.00086, 0.00012, 0.00001, 0.00000, 0.00000, 0.06374, \ + 0.05186, 0.04346, 0.02834, 0.01694, 0.01449, 0.00864, 0.00338, 0.00087, \ + 0.00012, 0.00001, 0.00000, 0.00000, 0.06467, 0.05267, 0.04417, 0.02885, \ + 0.01726, 0.01477, 0.00882, 0.00345, 0.00089, 0.00012, 0.00001, 0.00000, \ + 0.00000, 0.06473, 0.05273, 0.04422, 0.02888, 0.01728, 0.01480, 0.00883, \ + 0.00346, 0.00089, 0.00012, 0.00001, 0.00000, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.03233, 0.03550, 0.03853, 0.04690, 0.05718, 0.06003, 0.06791, 0.07653, \ + 0.08116, 0.08262, 0.08285, 0.08261, 0.08261, 0.03591, 0.03912, 0.04219, \ + 0.05065, 0.06107, 0.06395, 0.07194, 0.08068, 0.08539, 0.08688, 0.08711, \ + 0.08687, 0.08687, 0.04696, 0.05024, 0.05337, 0.06203, 0.07269, 0.07564, \ + 0.08384, 0.09283, 0.09768, 0.09922, 0.09946, 0.09921, 0.09921, 0.05071, \ + 0.05401, 0.05716, 0.06586, 0.07657, 0.07954, 0.08778, 0.09682, 0.10170, \ + 0.10325, 0.10349, 0.10324, 0.10325, 0.07364, 0.07699, 0.08019, 0.08902, \ + 0.09990, 0.10292, 0.11130, 0.12051, 0.12550, 0.12708, 0.12733, 0.12708, \ + 0.12708, 0.07750, 0.08085, 0.08405, 0.09289, 0.10379, 0.10681, 0.11520, \ + 0.12443, 0.12943, 0.13101, 0.13126, 0.13101, 0.13101 "); + } + } + + capacitance () { + top_plane: metal8; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.06211, 0.05066, 0.04262, 0.02829, 0.01757, 0.01527, 0.00968, 0.00437, \ + 0.00144, 0.00029, 0.00003, 0.00000, 0.00000, 0.06301, 0.05145, 0.04332, \ + 0.02880, 0.01792, 0.01558, 0.00989, 0.00448, 0.00147, 0.00030, 0.00003, \ + 0.00000, 0.00000, 0.06478, 0.05302, 0.04473, 0.02986, 0.01866, 0.01624, \ + 0.01035, 0.00470, 0.00155, 0.00032, 0.00003, 0.00000, 0.00000, 0.06519, \ + 0.05339, 0.04506, 0.03011, 0.01884, 0.01640, 0.01046, 0.00476, 0.00157, \ + 0.00032, 0.00003, 0.00000, 0.00000, 0.06670, 0.05475, 0.04631, 0.03108, \ + 0.01953, 0.01702, 0.01089, 0.00498, 0.00165, 0.00034, 0.00003, 0.00000, \ + 0.00000, 0.06684, 0.05489, 0.04643, 0.03118, 0.01960, 0.01708, 0.01094, \ + 0.00500, 0.00166, 0.00034, 0.00003, 0.00000, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.02994, 0.03281, 0.03554, 0.04302, 0.05224, 0.05482, 0.06213, 0.07074, \ + 0.07624, 0.07856, 0.07911, 0.07892, 0.07893, 0.03314, 0.03603, 0.03877, \ + 0.04633, 0.05565, 0.05827, 0.06569, 0.07447, 0.08009, 0.08246, 0.08303, \ + 0.08284, 0.08285, 0.04294, 0.04586, 0.04865, 0.05634, 0.06588, 0.06857, \ + 0.07623, 0.08535, 0.09124, 0.09374, 0.09434, 0.09415, 0.09415, 0.04625, \ + 0.04918, 0.05198, 0.05970, 0.06930, 0.07201, 0.07972, 0.08893, 0.09488, \ + 0.09742, 0.09802, 0.09784, 0.09784, 0.06646, 0.06943, 0.07227, 0.08012, \ + 0.08992, 0.09269, 0.10063, 0.11016, 0.11637, 0.11903, 0.11967, 0.11948, \ + 0.11948, 0.06987, 0.07284, 0.07568, 0.08354, 0.09336, 0.09614, 0.10410, \ + 0.11367, 0.11991, 0.12258, 0.12322, 0.12303, 0.12304 "); + } + } + + capacitance () { + top_plane: metal9; + bottom_plane: metal6; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.05551, 0.04411, 0.03617, 0.02233, 0.01255, 0.01057, 0.00604, 0.00227, \ + 0.00058, 0.00008, 0.00000, 0.00000, 0.00000, 0.05618, 0.04471, 0.03671, \ + 0.02274, 0.01283, 0.01081, 0.00619, 0.00234, 0.00060, 0.00009, 0.00001, \ + 0.00000, 0.00000, 0.05757, 0.04597, 0.03785, 0.02361, 0.01342, 0.01134, \ + 0.00654, 0.00248, 0.00064, 0.00009, 0.00001, 0.00000, 0.00000, 0.05792, \ + 0.04628, 0.03813, 0.02382, 0.01357, 0.01147, 0.00662, 0.00252, 0.00065, \ + 0.00009, 0.00001, 0.00000, 0.00000, 0.05919, 0.04744, 0.03919, 0.02463, \ + 0.01413, 0.01196, 0.00694, 0.00266, 0.00069, 0.00010, 0.00001, 0.00000, \ + 0.00000, 0.05931, 0.04755, 0.03929, 0.02471, 0.01418, 0.01201, 0.00697, \ + 0.00267, 0.00069, 0.00010, 0.00001, 0.00000, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.06487, 0.07017, 0.07481, 0.08624, 0.09792, 0.10080, 0.10800, 0.11497, \ + 0.11832, 0.11934, 0.11949, 0.11924, 0.11924, 0.07318, 0.07848, 0.08313, \ + 0.09461, 0.10640, 0.10931, 0.11664, 0.12377, 0.12721, 0.12826, 0.12842, \ + 0.12817, 0.12817, 0.09818, 0.10349, 0.10817, 0.11977, 0.13181, 0.13481, \ + 0.14240, 0.14987, 0.15352, 0.15464, 0.15481, 0.15455, 0.15456, 0.10655, \ + 0.11187, 0.11656, 0.12819, 0.14029, 0.14331, 0.15097, 0.15852, 0.16223, \ + 0.16337, 0.16354, 0.16328, 0.16329, 0.15705, 0.16241, 0.16714, 0.17891, \ + 0.19126, 0.19436, 0.20228, 0.21015, 0.21405, 0.21526, 0.21544, 0.21518, \ + 0.21519, 0.16550, 0.17086, 0.17559, 0.18739, 0.19976, 0.20287, 0.21081, \ + 0.21871, 0.22263, 0.22385, 0.22403, 0.22377, 0.22378 "); + } + } + + capacitance () { + top_plane: metal9; + bottom_plane: metal5; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.06213, 0.05067, 0.04261, 0.02822, 0.01742, 0.01510, 0.00945, 0.00413, \ + 0.00128, 0.00023, 0.00002, 0.00000, 0.00000, 0.06302, 0.05144, 0.04329, \ + 0.02871, 0.01774, 0.01538, 0.00964, 0.00422, 0.00131, 0.00024, 0.00002, \ + 0.00000, 0.00000, 0.06472, 0.05294, 0.04462, 0.02969, 0.01840, 0.01597, \ + 0.01003, 0.00441, 0.00137, 0.00025, 0.00002, 0.00000, 0.00000, 0.06511, \ + 0.05328, 0.04493, 0.02992, 0.01856, 0.01611, 0.01013, 0.00445, 0.00138, \ + 0.00025, 0.00002, 0.00000, 0.00000, 0.06645, 0.05449, 0.04602, 0.03074, \ + 0.01913, 0.01661, 0.01047, 0.00461, 0.00144, 0.00026, 0.00002, 0.00000, \ + 0.00000, 0.06657, 0.05459, 0.04612, 0.03082, 0.01918, 0.01666, 0.01050, \ + 0.00463, 0.00144, 0.00027, 0.00002, 0.00000, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.02964, 0.03250, 0.03522, 0.04274, 0.05209, 0.05471, 0.06217, 0.07089, \ + 0.07628, 0.07840, 0.07886, 0.07865, 0.07865, 0.03281, 0.03568, 0.03843, \ + 0.04603, 0.05550, 0.05816, 0.06573, 0.07460, 0.08011, 0.08228, 0.08274, \ + 0.08253, 0.08254, 0.04253, 0.04545, 0.04826, 0.05602, 0.06572, 0.06846, \ + 0.07626, 0.08545, 0.09119, 0.09346, 0.09394, 0.09373, 0.09374, 0.04583, \ + 0.04877, 0.05158, 0.05938, 0.06914, 0.07189, 0.07975, 0.08902, 0.09481, \ + 0.09710, 0.09759, 0.09738, 0.09739, 0.06600, 0.06899, 0.07185, 0.07978, \ + 0.08974, 0.09256, 0.10061, 0.11016, 0.11616, 0.11854, 0.11905, 0.11884, \ + 0.11884, 0.06940, 0.07239, 0.07526, 0.08321, 0.09318, 0.09601, 0.10408, \ + 0.11366, 0.11967, 0.12207, 0.12258, 0.12236, 0.12237 "); + } + } + + capacitance () { + top_plane: metal9; + bottom_plane: metal4; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.06438, 0.05305, 0.04509, 0.03089, 0.02008, 0.01770, 0.01177, 0.00574, \ + 0.00206, 0.00046, 0.00005, 0.00000, 0.00000, 0.06547, 0.05401, 0.04594, \ + 0.03150, 0.02049, 0.01806, 0.01201, 0.00586, 0.00210, 0.00047, 0.00005, \ + 0.00000, 0.00000, 0.06765, 0.05592, 0.04765, 0.03275, 0.02132, 0.01880, \ + 0.01251, 0.00610, 0.00219, 0.00049, 0.00006, 0.00000, 0.00000, 0.06815, \ + 0.05637, 0.04805, 0.03304, 0.02152, 0.01898, 0.01263, 0.00616, 0.00221, \ + 0.00050, 0.00006, 0.00000, 0.00000, 0.06987, 0.05790, 0.04942, 0.03406, \ + 0.02221, 0.01959, 0.01304, 0.00637, 0.00229, 0.00052, 0.00006, 0.00000, \ + 0.00000, 0.07001, 0.05803, 0.04954, 0.03415, 0.02227, 0.01965, 0.01308, \ + 0.00639, 0.00230, 0.00052, 0.00006, 0.00000, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.02237, 0.02444, 0.02643, 0.03207, 0.03954, 0.04176, 0.04847, 0.05738, \ + 0.06396, 0.06713, 0.06799, 0.06787, 0.06788, 0.02446, 0.02654, 0.02855, \ + 0.03427, 0.04186, 0.04412, 0.05096, 0.06004, 0.06676, 0.07000, 0.07087, \ + 0.07075, 0.07075, 0.03094, 0.03306, 0.03513, 0.04104, 0.04891, 0.05126, \ + 0.05835, 0.06778, 0.07477, 0.07815, 0.07907, 0.07895, 0.07895, 0.03316, \ + 0.03530, 0.03739, 0.04334, 0.05128, 0.05365, 0.06080, 0.07032, 0.07737, \ + 0.08079, 0.08171, 0.08159, 0.08159, 0.04701, 0.04922, 0.05136, 0.05750, \ + 0.06568, 0.06811, 0.07548, 0.08529, 0.09258, 0.09611, 0.09707, 0.09695, \ + 0.09695, 0.04938, 0.05159, 0.05374, 0.05989, 0.06809, 0.07053, 0.07792, \ + 0.08776, 0.09507, 0.09861, 0.09957, 0.09945, 0.09946 "); + } + } + + capacitance () { + top_plane: metal9; + bottom_plane: metal3; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.06519, 0.05392, 0.04602, 0.03194, 0.02123, 0.01887, 0.01290, 0.00665, \ + 0.00259, 0.00065, 0.00009, 0.00000, 0.00000, 0.06636, 0.05496, 0.04695, \ + 0.03263, 0.02170, 0.01928, 0.01319, 0.00679, 0.00264, 0.00067, 0.00009, \ + 0.00000, 0.00000, 0.06877, 0.05710, 0.04887, 0.03405, 0.02267, 0.02015, \ + 0.01378, 0.00710, 0.00276, 0.00070, 0.00009, 0.00000, 0.00000, 0.06935, \ + 0.05761, 0.04933, 0.03439, 0.02290, 0.02035, 0.01392, 0.00717, 0.00279, \ + 0.00070, 0.00009, 0.00000, 0.00000, 0.07136, 0.05941, 0.05095, 0.03560, \ + 0.02373, 0.02108, 0.01442, 0.00743, 0.00289, 0.00073, 0.00010, 0.00000, \ + 0.00000, 0.07154, 0.05957, 0.05109, 0.03571, 0.02380, 0.02115, 0.01446, \ + 0.00745, 0.00290, 0.00073, 0.00010, 0.00000, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.02007, 0.02187, 0.02361, 0.02852, 0.03514, 0.03714, 0.04333, 0.05202, \ + 0.05903, 0.06281, 0.06399, 0.06395, 0.06396, 0.02183, 0.02363, 0.02537, \ + 0.03036, 0.03709, 0.03914, 0.04545, 0.05432, 0.06148, 0.06534, 0.06654, \ + 0.06650, 0.06651, 0.02725, 0.02909, 0.03088, 0.03603, 0.04305, 0.04517, \ + 0.05176, 0.06100, 0.06848, 0.07251, 0.07377, 0.07373, 0.07374, 0.02912, \ + 0.03096, 0.03277, 0.03798, 0.04506, 0.04721, 0.05386, 0.06319, 0.07074, \ + 0.07482, 0.07609, 0.07605, 0.07606, 0.04081, 0.04272, 0.04460, 0.05000, \ + 0.05734, 0.05957, 0.06646, 0.07613, 0.08394, 0.08817, 0.08948, 0.08944, \ + 0.08945, 0.04282, 0.04474, 0.04662, 0.05204, 0.05941, 0.06165, 0.06856, \ + 0.07826, 0.08610, 0.09034, 0.09165, 0.09162, 0.09163 "); + } + } + + capacitance () { + top_plane: metal9; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.06619, 0.05500, 0.04718, 0.03331, 0.02283, 0.02051, 0.01463, 0.00823, \ + 0.00368, 0.00114, 0.00021, 0.00002, 0.00000, 0.06747, 0.05615, 0.04822, \ + 0.03411, 0.02339, 0.02102, 0.01499, 0.00843, 0.00377, 0.00117, 0.00021, \ + 0.00002, 0.00000, 0.07021, 0.05862, 0.05046, 0.03583, 0.02462, 0.02212, \ + 0.01577, 0.00887, 0.00396, 0.00123, 0.00022, 0.00002, 0.00000, 0.07089, \ + 0.05923, 0.05102, 0.03626, 0.02492, 0.02240, 0.01597, 0.00898, 0.00401, \ + 0.00124, 0.00022, 0.00002, 0.00000, 0.07345, 0.06155, 0.05313, 0.03790, \ + 0.02609, 0.02345, 0.01672, 0.00939, 0.00420, 0.00130, 0.00023, 0.00002, \ + 0.00000, 0.07370, 0.06178, 0.05334, 0.03806, 0.02621, 0.02356, 0.01680, \ + 0.00943, 0.00422, 0.00131, 0.00024, 0.00002, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.01735, 0.01887, 0.02031, 0.02435, 0.02980, 0.03147, 0.03676, 0.04471, \ + 0.05201, 0.05678, 0.05869, 0.05888, 0.05892, 0.01878, 0.02026, 0.02169, \ + 0.02576, 0.03130, 0.03300, 0.03841, 0.04654, 0.05402, 0.05889, 0.06085, \ + 0.06105, 0.06108, 0.02301, 0.02449, 0.02594, 0.03012, 0.03588, 0.03767, \ + 0.04334, 0.05187, 0.05973, 0.06486, 0.06691, 0.06713, 0.06717, 0.02445, \ + 0.02594, 0.02740, 0.03161, 0.03744, 0.03925, 0.04499, 0.05362, 0.06157, \ + 0.06676, 0.06884, 0.06907, 0.06910, 0.03351, 0.03505, 0.03656, 0.04095, \ + 0.04705, 0.04894, 0.05495, 0.06399, 0.07230, 0.07773, 0.07991, 0.08014, \ + 0.08018, 0.03508, 0.03662, 0.03814, 0.04255, 0.04868, 0.05058, 0.05662, \ + 0.06570, 0.07405, 0.07950, 0.08169, 0.08193, 0.08197 "); + } + } + + capacitance () { + top_plane: metal10; + bottom_plane: metal6; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.05648, 0.04517, 0.03732, 0.02374, 0.01424, 0.01231, 0.00786, 0.00388, \ + 0.00164, 0.00055, 0.00013, 0.00002, 0.00000, 0.05727, 0.04590, 0.03800, \ + 0.02430, 0.01467, 0.01272, 0.00816, 0.00407, 0.00174, 0.00059, 0.00014, \ + 0.00002, 0.00000, 0.05909, 0.04760, 0.03959, 0.02564, 0.01574, 0.01371, \ + 0.00893, 0.00454, 0.00197, 0.00068, 0.00016, 0.00002, 0.00000, 0.05959, \ + 0.04807, 0.04003, 0.02602, 0.01604, 0.01399, 0.00915, 0.00468, 0.00204, \ + 0.00070, 0.00016, 0.00002, 0.00000, 0.06182, 0.05018, 0.04204, 0.02775, \ + 0.01746, 0.01531, 0.01020, 0.00535, 0.00239, 0.00083, 0.00020, 0.00002, \ + 0.00000, 0.06210, 0.05045, 0.04229, 0.02798, 0.01764, 0.01549, 0.01034, \ + 0.00544, 0.00244, 0.00085, 0.00020, 0.00002, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.06227, 0.06728, 0.07161, 0.08212, 0.09266, 0.09526, 0.10185, 0.10874, \ + 0.11295, 0.11510, 0.11596, 0.11594, 0.11598, 0.07022, 0.07519, 0.07950, \ + 0.08999, 0.10058, 0.10320, 0.10989, 0.11697, 0.12135, 0.12362, 0.12453, \ + 0.12452, 0.12456, 0.09390, 0.09880, 0.10307, 0.11352, 0.12424, 0.12692, \ + 0.13387, 0.14139, 0.14619, 0.14875, 0.14980, 0.14983, 0.14987, 0.10177, \ + 0.10666, 0.11092, 0.12137, 0.13212, 0.13482, 0.14184, 0.14948, 0.15441, \ + 0.15705, 0.15814, 0.15818, 0.15822, 0.14891, 0.15377, 0.15801, 0.16847, \ + 0.17940, 0.18218, 0.18951, 0.19773, 0.20323, 0.20630, 0.20759, 0.20768, \ + 0.20774, 0.15676, 0.16162, 0.16586, 0.17632, 0.18727, 0.19006, 0.19743, \ + 0.20572, 0.21130, 0.21443, 0.21575, 0.21585, 0.21591 "); + } + } + + capacitance () { + top_plane: metal10; + bottom_plane: metal5; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.06326, 0.05189, 0.04392, 0.02980, 0.01936, 0.01712, 0.01168, 0.00631, \ + 0.00290, 0.00106, 0.00027, 0.00004, 0.00000, 0.06425, 0.05278, 0.04473, \ + 0.03044, 0.01984, 0.01757, 0.01203, 0.00653, 0.00302, 0.00111, 0.00028, \ + 0.00004, 0.00000, 0.06637, 0.05471, 0.04651, 0.03189, 0.02097, 0.01862, \ + 0.01285, 0.00707, 0.00331, 0.00122, 0.00031, 0.00004, 0.00000, 0.06691, \ + 0.05521, 0.04697, 0.03228, 0.02128, 0.01891, 0.01308, 0.00722, 0.00339, \ + 0.00126, 0.00032, 0.00005, 0.00000, 0.06921, 0.05736, 0.04900, 0.03402, \ + 0.02270, 0.02024, 0.01416, 0.00794, 0.00380, 0.00143, 0.00037, 0.00005, \ + 0.00000, 0.06948, 0.05762, 0.04925, 0.03423, 0.02288, 0.02041, 0.01430, \ + 0.00804, 0.00385, 0.00145, 0.00038, 0.00005, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.02668, 0.02925, 0.03166, 0.03821, 0.04616, 0.04839, 0.05475, 0.06267, \ + 0.06860, 0.07214, 0.07373, 0.07398, 0.07406, 0.02952, 0.03206, 0.03446, \ + 0.04101, 0.04900, 0.05125, 0.05769, 0.06576, 0.07186, 0.07553, 0.07719, \ + 0.07746, 0.07754, 0.03795, 0.04046, 0.04284, 0.04938, 0.05746, 0.05975, \ + 0.06637, 0.07479, 0.08128, 0.08527, 0.08711, 0.08743, 0.08752, 0.04075, \ + 0.04326, 0.04564, 0.05217, 0.06028, 0.06257, 0.06924, 0.07776, 0.08436, \ + 0.08844, 0.09033, 0.09066, 0.09076, 0.05760, 0.06008, 0.06245, 0.06898, \ + 0.07718, 0.07952, 0.08640, 0.09534, 0.10246, 0.10697, 0.10911, 0.10952, \ + 0.10963, 0.06041, 0.06288, 0.06525, 0.07179, 0.08000, 0.08235, 0.08925, \ + 0.09824, 0.10543, 0.11001, 0.11217, 0.11259, 0.11271 "); + } + } + + capacitance () { + top_plane: metal10; + bottom_plane: metal4; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.06564, 0.05440, 0.04653, 0.03259, 0.02215, 0.01988, 0.01421, 0.00826, \ + 0.00411, 0.00162, 0.00045, 0.00007, 0.00000, 0.06683, 0.05547, 0.04750, \ + 0.03335, 0.02272, 0.02041, 0.01461, 0.00852, 0.00425, 0.00168, 0.00047, \ + 0.00007, 0.00000, 0.06940, 0.05780, 0.04964, 0.03506, 0.02403, 0.02161, \ + 0.01555, 0.00913, 0.00459, 0.00183, 0.00051, 0.00008, 0.00000, 0.07005, \ + 0.05839, 0.05019, 0.03551, 0.02438, 0.02193, 0.01580, 0.00930, 0.00469, \ + 0.00187, 0.00053, 0.00008, 0.00000, 0.07271, 0.06086, 0.05249, 0.03742, \ + 0.02590, 0.02336, 0.01694, 0.01007, 0.00514, 0.00207, 0.00059, 0.00009, \ + 0.00000, 0.07301, 0.06114, 0.05275, 0.03765, 0.02609, 0.02353, 0.01709, \ + 0.01017, 0.00520, 0.00210, 0.00059, 0.00009, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.01910, 0.02089, 0.02257, 0.02724, 0.03326, 0.03503, 0.04042, 0.04799, \ + 0.05462, 0.05919, 0.06152, 0.06210, 0.06225, 0.02089, 0.02264, 0.02431, \ + 0.02897, 0.03502, 0.03681, 0.04229, 0.05000, 0.05680, 0.06152, 0.06393, \ + 0.06453, 0.06469, 0.02613, 0.02784, 0.02949, 0.03415, 0.04031, 0.04215, \ + 0.04781, 0.05586, 0.06305, 0.06810, 0.07072, 0.07139, 0.07157, 0.02787, \ + 0.02957, 0.03122, 0.03589, 0.04208, 0.04394, 0.04963, 0.05777, 0.06507, \ + 0.07022, 0.07289, 0.07359, 0.07377, 0.03843, 0.04013, 0.04178, 0.04649, \ + 0.05280, 0.05470, 0.06058, 0.06910, 0.07687, 0.08246, 0.08541, 0.08620, \ + 0.08640, 0.04020, 0.04190, 0.04356, 0.04828, 0.05459, 0.05650, 0.06241, \ + 0.07097, 0.07880, 0.08445, 0.08743, 0.08824, 0.08844 "); + } + } + + capacitance () { + top_plane: metal10; + bottom_plane: metal3; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.06653, 0.05535, 0.04753, 0.03372, 0.02339, 0.02113, 0.01545, 0.00934, \ + 0.00487, 0.00203, 0.00060, 0.00010, 0.00000, 0.06780, 0.05649, 0.04858, \ + 0.03455, 0.02401, 0.02170, 0.01589, 0.00962, 0.00503, 0.00210, 0.00062, \ + 0.00011, 0.00000, 0.07059, 0.05904, 0.05092, 0.03643, 0.02545, 0.02303, \ + 0.01692, 0.01029, 0.00541, 0.00227, 0.00067, 0.00011, 0.00000, 0.07131, \ + 0.05970, 0.05153, 0.03692, 0.02583, 0.02338, 0.01719, 0.01048, 0.00552, \ + 0.00232, 0.00069, 0.00012, 0.00000, 0.07425, 0.06242, 0.05406, 0.03902, \ + 0.02748, 0.02492, 0.01842, 0.01131, 0.00600, 0.00254, 0.00076, 0.00013, \ + 0.00000, 0.07458, 0.06273, 0.05435, 0.03927, 0.02768, 0.02511, 0.01857, \ + 0.01141, 0.00607, 0.00257, 0.00077, 0.00013, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.01660, 0.01812, 0.01956, 0.02352, 0.02867, 0.03021, 0.03500, 0.04209, \ + 0.04883, 0.05390, 0.05669, 0.05752, 0.05773, 0.01807, 0.01955, 0.02096, \ + 0.02489, 0.03006, 0.03162, 0.03649, 0.04373, 0.05064, 0.05586, 0.05874, \ + 0.05960, 0.05982, 0.02229, 0.02371, 0.02509, 0.02900, 0.03428, 0.03588, \ + 0.04093, 0.04850, 0.05580, 0.06138, 0.06449, 0.06544, 0.06568, 0.02368, \ + 0.02510, 0.02647, 0.03039, 0.03569, 0.03731, 0.04240, 0.05006, 0.05747, \ + 0.06314, 0.06632, 0.06729, 0.06754, 0.03212, 0.03353, 0.03491, 0.03888, \ + 0.04432, 0.04599, 0.05127, 0.05931, 0.06718, 0.07330, 0.07678, 0.07786, \ + 0.07813, 0.03355, 0.03496, 0.03634, 0.04032, 0.04577, 0.04744, 0.05276, \ + 0.06084, 0.06877, 0.07494, 0.07846, 0.07956, 0.07983 "); + } + } + + capacitance () { + top_plane: metal10; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.06771, 0.05660, 0.04886, 0.03525, 0.02513, 0.02293, 0.01735, 0.01118, \ + 0.00635, 0.00293, 0.00098, 0.00020, 0.00000, 0.06907, 0.05784, 0.05001, \ + 0.03617, 0.02585, 0.02359, 0.01786, 0.01152, 0.00655, 0.00303, 0.00101, \ + 0.00020, 0.00000, 0.07216, 0.06069, 0.05264, 0.03833, 0.02752, 0.02514, \ + 0.01908, 0.01233, 0.00702, 0.00325, 0.00109, 0.00022, 0.00000, 0.07298, \ + 0.06144, 0.05334, 0.03891, 0.02797, 0.02556, 0.01941, 0.01255, 0.00715, \ + 0.00332, 0.00112, 0.00022, 0.00000, 0.07644, 0.06466, 0.05635, 0.04141, \ + 0.02995, 0.02740, 0.02087, 0.01354, 0.00774, 0.00360, 0.00122, 0.00025, \ + 0.00000, 0.07684, 0.06503, 0.05670, 0.04171, 0.03019, 0.02762, 0.02105, \ + 0.01366, 0.00782, 0.00364, 0.00123, 0.00025, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.01348, 0.01471, 0.01586, 0.01897, 0.02295, 0.02415, 0.02795, 0.03396, \ + 0.04040, 0.04607, 0.04976, 0.05117, 0.05158, 0.01463, 0.01579, 0.01689, \ + 0.01993, 0.02391, 0.02512, 0.02898, 0.03512, 0.04173, 0.04756, 0.05136, \ + 0.05282, 0.05324, 0.01774, 0.01881, 0.01985, 0.02279, 0.02680, 0.02804, \ + 0.03205, 0.03851, 0.04552, 0.05173, 0.05580, 0.05739, 0.05784, 0.01872, \ + 0.01978, 0.02081, 0.02374, 0.02777, 0.02902, 0.03308, 0.03962, 0.04674, \ + 0.05306, 0.05721, 0.05882, 0.05929, 0.02460, 0.02564, 0.02666, 0.02962, \ + 0.03377, 0.03508, 0.03933, 0.04626, 0.05385, 0.06065, 0.06514, 0.06692, \ + 0.06743, 0.02559, 0.02663, 0.02765, 0.03062, 0.03479, 0.03610, 0.04039, \ + 0.04736, 0.05501, 0.06187, 0.06641, 0.06820, 0.06872 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: metal6; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.05708, 0.04580, 0.03797, 0.02444, 0.01498, 0.01307, 0.00864, 0.00468, \ + 0.00242, 0.00122, 0.00060, 0.00026, 0.00000, 0.05789, 0.04655, 0.03867, \ + 0.02503, 0.01546, 0.01352, 0.00901, 0.00494, 0.00258, 0.00131, 0.00065, \ + 0.00029, 0.00000, 0.05979, 0.04833, 0.04035, 0.02649, 0.01668, 0.01467, \ + 0.00997, 0.00564, 0.00304, 0.00158, 0.00079, 0.00036, 0.00000, 0.06032, \ + 0.04883, 0.04083, 0.02691, 0.01704, 0.01502, 0.01025, 0.00585, 0.00318, \ + 0.00167, 0.00084, 0.00038, 0.00000, 0.06283, 0.05124, 0.04314, 0.02899, \ + 0.01885, 0.01675, 0.01175, 0.00699, 0.00398, 0.00217, 0.00112, 0.00051, \ + 0.00000, 0.06317, 0.05156, 0.04346, 0.02928, 0.01911, 0.01700, 0.01197, \ + 0.00717, 0.00410, 0.00225, 0.00117, 0.00054, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.06068, 0.06561, 0.06987, 0.08019, 0.09054, 0.09308, 0.09954, 0.10629, \ + 0.11045, 0.11277, 0.11400, 0.11442, 0.11496, 0.06857, 0.07345, 0.07769, \ + 0.08796, 0.09832, 0.10087, 0.10740, 0.11429, 0.11861, 0.12106, 0.12237, \ + 0.12285, 0.12344, 0.09202, 0.09682, 0.10100, 0.11116, 0.12152, 0.12411, \ + 0.13078, 0.13801, 0.14273, 0.14552, 0.14707, 0.14769, 0.14842, 0.09979, \ + 0.10458, 0.10873, 0.11887, 0.12923, 0.13182, 0.13854, 0.14586, 0.15069, \ + 0.15358, 0.15521, 0.15588, 0.15666, 0.14613, 0.15084, 0.15493, 0.16494, \ + 0.17529, 0.17791, 0.18479, 0.19255, 0.19794, 0.20137, 0.20342, 0.20438, \ + 0.20543, 0.15381, 0.15851, 0.16259, 0.17258, 0.18293, 0.18555, 0.19246, \ + 0.20027, 0.20574, 0.20925, 0.21136, 0.21237, 0.21347 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: metal5; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.06404, 0.05270, 0.04475, 0.03070, 0.02032, 0.01811, 0.01274, 0.00746, \ + 0.00409, 0.00214, 0.00107, 0.00049, 0.00000, 0.06506, 0.05361, 0.04558, \ + 0.03136, 0.02085, 0.01861, 0.01314, 0.00776, 0.00430, 0.00227, 0.00114, \ + 0.00052, 0.00000, 0.06724, 0.05561, 0.04744, 0.03292, 0.02213, 0.01982, \ + 0.01417, 0.00854, 0.00484, 0.00261, 0.00134, 0.00061, 0.00000, 0.06782, \ + 0.05614, 0.04794, 0.03335, 0.02250, 0.02017, 0.01447, 0.00878, 0.00501, \ + 0.00272, 0.00140, 0.00064, 0.00000, 0.07038, 0.05858, 0.05027, 0.03543, \ + 0.02432, 0.02192, 0.01601, 0.01001, 0.00592, 0.00332, 0.00175, 0.00082, \ + 0.00000, 0.07071, 0.05890, 0.05058, 0.03571, 0.02457, 0.02217, 0.01624, \ + 0.01020, 0.00606, 0.00342, 0.00181, 0.00085, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.02470, 0.02717, 0.02949, 0.03581, 0.04348, 0.04561, 0.05170, 0.05919, \ + 0.06481, 0.06840, 0.07046, 0.07141, 0.07240, 0.02747, 0.02992, 0.03223, \ + 0.03853, 0.04619, 0.04833, 0.05445, 0.06203, 0.06779, 0.07150, 0.07367, \ + 0.07468, 0.07574, 0.03569, 0.03809, 0.04037, 0.04658, 0.05421, 0.05635, \ + 0.06252, 0.07029, 0.07636, 0.08041, 0.08285, 0.08405, 0.08530, 0.03840, \ + 0.04079, 0.04305, 0.04924, 0.05685, 0.05899, 0.06517, 0.07299, 0.07914, \ + 0.08329, 0.08582, 0.08708, 0.08839, 0.05445, 0.05677, 0.05898, 0.06503, \ + 0.07252, 0.07465, 0.08085, 0.08889, 0.09546, 0.10011, 0.10310, 0.10470, \ + 0.10636, 0.05709, 0.05940, 0.06160, 0.06763, 0.07511, 0.07724, 0.08343, \ + 0.09150, 0.09813, 0.10285, 0.10591, 0.10757, 0.10928 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: metal4; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.06658, 0.05537, 0.04752, 0.03365, 0.02330, 0.02105, 0.01547, 0.00967, \ + 0.00563, 0.00309, 0.00159, 0.00074, 0.00000, 0.06779, 0.05645, 0.04851, \ + 0.03444, 0.02391, 0.02162, 0.01593, 0.01001, 0.00587, 0.00324, 0.00168, \ + 0.00079, 0.00000, 0.07042, 0.05885, 0.05073, 0.03625, 0.02535, 0.02298, \ + 0.01707, 0.01088, 0.00649, 0.00364, 0.00192, 0.00091, 0.00000, 0.07110, \ + 0.05948, 0.05131, 0.03673, 0.02576, 0.02336, 0.01740, 0.01113, 0.00668, \ + 0.00377, 0.00200, 0.00094, 0.00000, 0.07402, 0.06222, 0.05390, 0.03898, \ + 0.02768, 0.02521, 0.01901, 0.01244, 0.00767, 0.00445, 0.00241, 0.00116, \ + 0.00000, 0.07437, 0.06256, 0.05423, 0.03928, 0.02794, 0.02546, 0.01924, \ + 0.01263, 0.00782, 0.00456, 0.00248, 0.00119, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.01675, 0.01842, 0.02002, 0.02444, 0.03013, 0.03180, 0.03684, 0.04379, \ + 0.04982, 0.05420, 0.05698, 0.05845, 0.05995, 0.01848, 0.02012, 0.02169, \ + 0.02609, 0.03178, 0.03345, 0.03852, 0.04554, 0.05168, 0.05619, 0.05909, \ + 0.06064, 0.06222, 0.02352, 0.02511, 0.02665, 0.03098, 0.03665, 0.03833, \ + 0.04343, 0.05059, 0.05699, 0.06182, 0.06501, 0.06678, 0.06860, 0.02517, \ + 0.02676, 0.02829, 0.03260, 0.03826, 0.03993, 0.04504, 0.05223, 0.05869, \ + 0.06362, 0.06689, 0.06873, 0.07063, 0.03496, 0.03650, 0.03799, 0.04220, \ + 0.04775, 0.04941, 0.05451, 0.06181, 0.06859, 0.07396, 0.07770, 0.07991, \ + 0.08224, 0.03657, 0.03810, 0.03958, 0.04378, 0.04931, 0.05097, 0.05606, \ + 0.06338, 0.07020, 0.07563, 0.07943, 0.08171, 0.08410 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: metal3; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.06757, 0.05642, 0.04863, 0.03490, 0.02465, 0.02242, 0.01683, 0.01089, \ + 0.00659, 0.00373, 0.00197, 0.00094, 0.00000, 0.06886, 0.05758, 0.04970, \ + 0.03574, 0.02531, 0.02303, 0.01733, 0.01126, 0.00685, 0.00389, 0.00207, \ + 0.00099, 0.00000, 0.07172, 0.06019, 0.05211, 0.03772, 0.02688, 0.02451, \ + 0.01856, 0.01219, 0.00752, 0.00434, 0.00234, 0.00113, 0.00000, 0.07246, \ + 0.06088, 0.05275, 0.03825, 0.02731, 0.02492, 0.01890, 0.01246, 0.00772, \ + 0.00448, 0.00242, 0.00117, 0.00000, 0.07565, 0.06387, 0.05556, 0.04067, \ + 0.02936, 0.02687, 0.02060, 0.01383, 0.00877, 0.00521, 0.00288, 0.00141, \ + 0.00000, 0.07604, 0.06424, 0.05592, 0.04099, 0.02963, 0.02713, 0.02083, \ + 0.01403, 0.00892, 0.00532, 0.00295, 0.00145, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.01402, 0.01541, 0.01674, 0.02044, 0.02526, 0.02670, 0.03111, 0.03750, \ + 0.04345, 0.04813, 0.05131, 0.05312, 0.05500, 0.01542, 0.01678, 0.01809, \ + 0.02175, 0.02655, 0.02798, 0.03242, 0.03887, 0.04492, 0.04973, 0.05303, \ + 0.05493, 0.05690, 0.01945, 0.02075, 0.02201, 0.02559, 0.03036, 0.03179, \ + 0.03626, 0.04282, 0.04911, 0.05422, 0.05782, 0.05996, 0.06221, 0.02075, \ + 0.02205, 0.02330, 0.02686, 0.03161, 0.03305, 0.03751, 0.04410, 0.05045, \ + 0.05565, 0.05934, 0.06155, 0.06388, 0.02845, 0.02969, 0.03091, 0.03437, \ + 0.03904, 0.04045, 0.04491, 0.05159, 0.05820, 0.06381, 0.06796, 0.07056, \ + 0.07337, 0.02971, 0.03095, 0.03216, 0.03560, 0.04026, 0.04167, 0.04612, \ + 0.05281, 0.05945, 0.06513, 0.06933, 0.07200, 0.07488 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.06894, 0.05788, 0.05018, 0.03667, 0.02664, 0.02446, 0.01898, 0.01302, \ + 0.00843, 0.00510, 0.00286, 0.00143, 0.00000, 0.07034, 0.05915, 0.05135, \ + 0.03761, 0.02739, 0.02516, 0.01956, 0.01345, 0.00874, 0.00531, 0.00298, \ + 0.00149, 0.00000, 0.07350, 0.06207, 0.05406, 0.03985, 0.02919, 0.02685, \ + 0.02096, 0.01452, 0.00952, 0.00584, 0.00332, 0.00167, 0.00000, 0.07435, \ + 0.06285, 0.05479, 0.04046, 0.02969, 0.02733, 0.02136, 0.01482, 0.00975, \ + 0.00600, 0.00342, 0.00173, 0.00000, 0.07804, 0.06631, 0.05805, 0.04327, \ + 0.03204, 0.02956, 0.02328, 0.01635, 0.01093, 0.00685, 0.00396, 0.00203, \ + 0.00000, 0.07849, 0.06674, 0.05846, 0.04363, 0.03235, 0.02985, 0.02354, \ + 0.01657, 0.01110, 0.00697, 0.00404, 0.00207, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.4000, 0.5000, 0.8000, 0.9000, 1.5000, 1.6000 "); + index_2 (" 0.4000, 0.5000, 0.6000, 0.9000, 1.3500, 1.5000, 2.0250, 3.0375, \ + 4.5563, 6.8344, 10.2516, 15.3773, 1537.7344 "); + values (" 0.01042, 0.01148, 0.01249, 0.01529, 0.01892, 0.02001, 0.02341, 0.02861, \ + 0.03397, 0.03880, 0.04258, 0.04507, 0.04789, 0.01147, 0.01249, 0.01347, \ + 0.01620, 0.01978, 0.02086, 0.02427, 0.02950, 0.03494, 0.03989, 0.04379, \ + 0.04638, 0.04933, 0.01436, 0.01530, 0.01622, 0.01881, 0.02231, 0.02337, \ + 0.02677, 0.03207, 0.03769, 0.04291, 0.04712, 0.04998, 0.05327, 0.01527, \ + 0.01620, 0.01710, 0.01966, 0.02313, 0.02420, 0.02759, 0.03290, 0.03857, \ + 0.04387, 0.04816, 0.05110, 0.05450, 0.02045, 0.02132, 0.02218, 0.02463, \ + 0.02799, 0.02904, 0.03240, 0.03776, 0.04364, 0.04929, 0.05402, 0.05738, \ + 0.06135, 0.02129, 0.02215, 0.02300, 0.02544, 0.02879, 0.02984, 0.03319, \ + 0.03856, 0.04445, 0.05016, 0.05494, 0.05837, 0.06243 "); + } + } + } + + layer (metal6) { + resistance: 0.210000 + + capacitance () { + top_plane: metal7; + bottom_plane: metal5; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.05924, 0.03873, 0.02882, 0.02365, 0.01261, 0.01137, 0.00528, 0.00266, \ + 0.00150, 0.00033, 0.00024, 0.00002, 0.00000, 0.00000, 0.00000, 0.06023, \ + 0.03939, 0.02930, 0.02404, 0.01281, 0.01155, 0.00536, 0.00271, 0.00152, \ + 0.00033, 0.00024, 0.00002, 0.00000, 0.00000, 0.00000, 0.06027, 0.03941, \ + 0.02932, 0.02405, 0.01282, 0.01156, 0.00536, 0.00271, 0.00152, 0.00033, \ + 0.00024, 0.00002, 0.00000, 0.00000, 0.00000, 0.06055, 0.03960, 0.02945, \ + 0.02416, 0.01287, 0.01161, 0.00538, 0.00272, 0.00153, 0.00033, 0.00024, \ + 0.00002, 0.00000, 0.00000, 0.00000, 0.06053, 0.03959, 0.02945, 0.02415, \ + 0.01287, 0.01160, 0.00538, 0.00272, 0.00153, 0.00033, 0.00024, 0.00002, \ + 0.00000, 0.00000, 0.00000, 0.06055, 0.03960, 0.02945, 0.02416, 0.01287, \ + 0.01161, 0.00538, 0.00272, 0.00153, 0.00033, 0.00024, 0.00002, 0.00000, \ + 0.00000, 0.00000, 0.06055, 0.03960, 0.02945, 0.02416, 0.01287, 0.01161, \ + 0.00538, 0.00272, 0.00153, 0.00033, 0.00024, 0.00002, 0.00000, 0.00000, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.04216, 0.05055, 0.05708, 0.06162, 0.07440, 0.07619, 0.08596, 0.09090, \ + 0.09329, 0.09561, 0.09584, 0.09627, 0.09628, 0.09637, 0.09636, 0.06145, \ + 0.07008, 0.07677, 0.08140, 0.09441, 0.09623, 0.10616, 0.11116, 0.11359, \ + 0.11595, 0.11618, 0.11663, 0.11663, 0.11669, 0.11669, 0.06296, 0.07160, \ + 0.07829, 0.08293, 0.09594, 0.09777, 0.10770, 0.11271, 0.11513, 0.11750, \ + 0.11773, 0.11817, 0.11817, 0.11824, 0.11823, 0.09639, 0.10509, 0.11183, \ + 0.11649, 0.12957, 0.13140, 0.14137, 0.14640, 0.14884, 0.15121, 0.15144, \ + 0.15189, 0.15189, 0.15195, 0.15194, 0.10552, 0.11423, 0.12096, 0.12562, \ + 0.13870, 0.14053, 0.15050, 0.15553, 0.15797, 0.16034, 0.16057, 0.16102, \ + 0.16102, 0.16108, 0.16108, 0.15742, 0.16613, 0.17286, 0.17753, 0.19061, \ + 0.19244, 0.20241, 0.20744, 0.20988, 0.21225, 0.21248, 0.21293, 0.21293, \ + 0.21299, 0.21299, 0.24902, 0.25772, 0.26446, 0.26912, 0.28221, 0.28403, \ + 0.29401, 0.29904, 0.30148, 0.30386, 0.30408, 0.30453, 0.30454, 0.30451, \ + 0.30459 "); + } + } + + capacitance () { + top_plane: metal7; + bottom_plane: metal4; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.06297, 0.04297, 0.03336, 0.02835, 0.01743, 0.01615, 0.00941, 0.00597, \ + 0.00411, 0.00155, 0.00126, 0.00023, 0.00002, 0.00000, 0.00000, 0.06533, \ + 0.04481, 0.03489, 0.02970, 0.01834, 0.01700, 0.00995, 0.00633, 0.00436, \ + 0.00165, 0.00135, 0.00025, 0.00002, 0.00000, 0.00000, 0.06546, 0.04491, \ + 0.03498, 0.02977, 0.01839, 0.01705, 0.00998, 0.00635, 0.00438, 0.00166, \ + 0.00135, 0.00025, 0.00002, 0.00000, 0.00000, 0.06706, 0.04621, 0.03608, \ + 0.03075, 0.01906, 0.01769, 0.01039, 0.00662, 0.00457, 0.00174, 0.00142, \ + 0.00026, 0.00002, 0.00000, 0.00000, 0.06726, 0.04638, 0.03623, 0.03088, \ + 0.01916, 0.01778, 0.01045, 0.00666, 0.00460, 0.00175, 0.00143, 0.00026, \ + 0.00002, 0.00000, 0.00000, 0.06792, 0.04692, 0.03669, 0.03130, 0.01945, \ + 0.01805, 0.01062, 0.00678, 0.00468, 0.00178, 0.00145, 0.00027, 0.00002, \ + 0.00000, 0.00000, 0.06816, 0.04712, 0.03687, 0.03146, 0.01956, 0.01815, \ + 0.01069, 0.00682, 0.00471, 0.00180, 0.00146, 0.00027, 0.00002, 0.00000, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.03040, 0.03611, 0.04061, 0.04380, 0.05332, 0.05475, 0.06351, 0.06903, \ + 0.07234, 0.07710, 0.07770, 0.07978, 0.08021, 0.08026, 0.08026, 0.04271, \ + 0.04856, 0.05320, 0.05647, 0.06632, 0.06780, 0.07693, 0.08271, 0.08620, \ + 0.09124, 0.09188, 0.09410, 0.09456, 0.09458, 0.09458, 0.04368, 0.04954, \ + 0.05418, 0.05746, 0.06732, 0.06881, 0.07796, 0.08375, 0.08725, 0.09231, \ + 0.09294, 0.09518, 0.09564, 0.09566, 0.09566, 0.06531, 0.07127, 0.07600, \ + 0.07935, 0.08944, 0.09097, 0.10039, 0.10639, 0.11001, 0.11529, 0.11596, \ + 0.11830, 0.11878, 0.11879, 0.11879, 0.07128, 0.07726, 0.08200, 0.08536, \ + 0.09549, 0.09702, 0.10649, 0.11251, 0.11616, 0.12147, 0.12213, 0.12449, \ + 0.12498, 0.12499, 0.12499, 0.10558, 0.11161, 0.11639, 0.11979, 0.13002, \ + 0.13157, 0.14115, 0.14726, 0.15096, 0.15637, 0.15705, 0.15945, 0.15995, \ + 0.15996, 0.15996, 0.16667, 0.17271, 0.17752, 0.18092, 0.19120, 0.19275, \ + 0.20238, 0.20852, 0.21224, 0.21768, 0.21836, 0.22078, 0.22129, 0.22132, \ + 0.22130 "); + } + } + + capacitance () { + top_plane: metal7; + bottom_plane: metal3; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.06355, 0.04366, 0.03414, 0.02920, 0.01845, 0.01720, 0.01055, 0.00708, \ + 0.00514, 0.00228, 0.00192, 0.00049, 0.00007, 0.00000, 0.00000, 0.06620, \ + 0.04580, 0.03598, 0.03085, 0.01966, 0.01834, 0.01134, 0.00765, 0.00557, \ + 0.00249, 0.00210, 0.00054, 0.00008, 0.00000, 0.00000, 0.06635, 0.04593, \ + 0.03609, 0.03095, 0.01973, 0.01841, 0.01139, 0.00768, 0.00560, 0.00250, \ + 0.00212, 0.00054, 0.00008, 0.00000, 0.00000, 0.06846, 0.04772, 0.03767, \ + 0.03239, 0.02081, 0.01944, 0.01212, 0.00822, 0.00601, 0.00270, 0.00229, \ + 0.00058, 0.00008, 0.00000, 0.00000, 0.06879, 0.04801, 0.03793, 0.03263, \ + 0.02100, 0.01962, 0.01225, 0.00831, 0.00608, 0.00274, 0.00232, 0.00059, \ + 0.00008, 0.00000, 0.00000, 0.07000, 0.04906, 0.03887, 0.03350, 0.02166, \ + 0.02026, 0.01270, 0.00865, 0.00634, 0.00287, 0.00243, 0.00062, 0.00009, \ + 0.00000, 0.00000, 0.07070, 0.04967, 0.03942, 0.03400, 0.02205, 0.02062, \ + 0.01296, 0.00884, 0.00649, 0.00294, 0.00249, 0.00064, 0.00009, 0.00001, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.02886, 0.03420, 0.03838, 0.04131, 0.05007, 0.05139, 0.05952, 0.06480, \ + 0.06809, 0.07323, 0.07393, 0.07677, 0.07763, 0.07777, 0.07777, 0.04026, \ + 0.04564, 0.04989, 0.05289, 0.06189, 0.06326, 0.07175, 0.07731, 0.08081, \ + 0.08634, 0.08710, 0.09021, 0.09115, 0.09127, 0.09127, 0.04114, 0.04653, \ + 0.05078, 0.05379, 0.06280, 0.06417, 0.07268, 0.07826, 0.08178, 0.08733, \ + 0.08809, 0.09121, 0.09216, 0.09228, 0.09228, 0.06089, 0.06633, 0.07063, \ + 0.07368, 0.08291, 0.08432, 0.09314, 0.09898, 0.10268, 0.10860, 0.10942, \ + 0.11279, 0.11382, 0.11394, 0.11395, 0.06633, 0.07177, 0.07609, 0.07915, \ + 0.08841, 0.08982, 0.09870, 0.10459, 0.10833, 0.11431, 0.11514, 0.11855, \ + 0.11960, 0.11972, 0.11973, 0.09755, 0.10304, 0.10740, 0.11050, 0.11990, \ + 0.12134, 0.13042, 0.13647, 0.14033, 0.14654, 0.14740, 0.15098, 0.15208, \ + 0.15220, 0.15221, 0.15343, 0.15896, 0.16335, 0.16648, 0.17597, 0.17743, \ + 0.18662, 0.19277, 0.19670, 0.20304, 0.20393, 0.20759, 0.20872, 0.20889, \ + 0.20886 "); + } + } + + capacitance () { + top_plane: metal7; + bottom_plane: metal2; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.06376, 0.04390, 0.03441, 0.02949, 0.01882, 0.01757, 0.01098, 0.00752, \ + 0.00557, 0.00263, 0.00226, 0.00066, 0.00011, 0.00001, 0.00000, 0.06649, \ + 0.04614, 0.03636, 0.03125, 0.02013, 0.01883, 0.01188, 0.00819, 0.00609, \ + 0.00291, 0.00250, 0.00073, 0.00013, 0.00001, 0.00000, 0.06665, 0.04627, \ + 0.03647, 0.03136, 0.02021, 0.01891, 0.01193, 0.00823, 0.00613, 0.00293, \ + 0.00251, 0.00073, 0.00013, 0.00001, 0.00000, 0.06896, 0.04826, 0.03825, \ + 0.03299, 0.02148, 0.02012, 0.01283, 0.00891, 0.00666, 0.00321, 0.00276, \ + 0.00081, 0.00014, 0.00001, 0.00000, 0.06934, 0.04860, 0.03856, 0.03328, \ + 0.02171, 0.02035, 0.01300, 0.00904, 0.00677, 0.00327, 0.00281, 0.00083, \ + 0.00014, 0.00001, 0.00000, 0.07082, 0.04992, 0.03976, 0.03440, 0.02260, \ + 0.02120, 0.01363, 0.00952, 0.00715, 0.00348, 0.00299, 0.00089, 0.00016, \ + 0.00001, 0.00000, 0.07183, 0.05082, 0.04057, 0.03516, 0.02320, 0.02178, \ + 0.01406, 0.00986, 0.00742, 0.00362, 0.00312, 0.00093, 0.00016, 0.00001, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.02833, 0.03356, 0.03764, 0.04050, 0.04898, 0.05026, 0.05815, 0.06330, \ + 0.06653, 0.07173, 0.07246, 0.07559, 0.07669, 0.07691, 0.07692, 0.03946, \ + 0.04469, 0.04881, 0.05171, 0.06041, 0.06172, 0.06994, 0.07536, 0.07882, \ + 0.08444, 0.08524, 0.08870, 0.08992, 0.09014, 0.09015, 0.04032, 0.04556, \ + 0.04967, 0.05258, 0.06128, 0.06261, 0.07084, 0.07628, 0.07975, 0.08540, \ + 0.08620, 0.08968, 0.09091, 0.09113, 0.09114, 0.05943, 0.06469, 0.06884, \ + 0.07178, 0.08066, 0.08202, 0.09055, 0.09627, 0.09995, 0.10602, 0.10689, \ + 0.11070, 0.11207, 0.11230, 0.11232, 0.06468, 0.06994, 0.07410, 0.07704, \ + 0.08596, 0.08732, 0.09591, 0.10169, 0.10540, 0.11155, 0.11244, 0.11631, \ + 0.11770, 0.11794, 0.11796, 0.09477, 0.10006, 0.10426, 0.10723, 0.11629, \ + 0.11768, 0.12650, 0.13247, 0.13633, 0.14279, 0.14372, 0.14783, 0.14933, \ + 0.14957, 0.14960, 0.14866, 0.15399, 0.15822, 0.16123, 0.17040, 0.17181, \ + 0.18079, 0.18689, 0.19086, 0.19752, 0.19848, 0.20276, 0.20432, 0.20463, \ + 0.20460 "); + } + } + + capacitance () { + top_plane: metal7; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.06407, 0.04424, 0.03479, 0.02989, 0.01932, 0.01809, 0.01159, 0.00817, \ + 0.00623, 0.00324, 0.00284, 0.00103, 0.00026, 0.00003, 0.00000, 0.06690, \ + 0.04661, 0.03687, 0.03181, 0.02081, 0.01952, 0.01267, 0.00902, 0.00692, \ + 0.00365, 0.00321, 0.00117, 0.00029, 0.00004, 0.00000, 0.06707, 0.04675, \ + 0.03700, 0.03192, 0.02090, 0.01961, 0.01274, 0.00907, 0.00697, 0.00368, \ + 0.00323, 0.00118, 0.00030, 0.00004, 0.00000, 0.06965, 0.04902, 0.03906, \ + 0.03385, 0.02246, 0.02112, 0.01391, 0.01002, 0.00775, 0.00415, 0.00366, \ + 0.00135, 0.00034, 0.00005, 0.00000, 0.07010, 0.04944, 0.03946, 0.03422, \ + 0.02277, 0.02142, 0.01415, 0.01021, 0.00792, 0.00426, 0.00375, 0.00139, \ + 0.00035, 0.00005, 0.00000, 0.07205, 0.05121, 0.04110, 0.03578, 0.02407, \ + 0.02268, 0.01516, 0.01103, 0.00860, 0.00468, 0.00414, 0.00155, 0.00040, \ + 0.00005, 0.00000, 0.07370, 0.05273, 0.04252, 0.03713, 0.02521, 0.02379, \ + 0.01605, 0.01176, 0.00922, 0.00507, 0.00449, 0.00170, 0.00044, 0.00006, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.02753, 0.03264, 0.03660, 0.03937, 0.04753, 0.04875, 0.05626, 0.06119, \ + 0.06431, 0.06947, 0.07023, 0.07370, 0.07524, 0.07570, 0.07577, 0.03838, \ + 0.04342, 0.04737, 0.05014, 0.05841, 0.05966, 0.06745, 0.07263, 0.07597, \ + 0.08157, 0.08240, 0.08630, 0.08806, 0.08855, 0.08863, 0.03921, 0.04425, \ + 0.04819, 0.05097, 0.05924, 0.06050, 0.06830, 0.07349, 0.07685, 0.08248, \ + 0.08332, 0.08724, 0.08901, 0.08951, 0.08959, 0.05750, 0.06250, 0.06644, \ + 0.06922, 0.07760, 0.07888, 0.08694, 0.09240, 0.09597, 0.10210, 0.10302, \ + 0.10742, 0.10945, 0.11001, 0.11011, 0.06249, 0.06748, 0.07142, 0.07420, \ + 0.08260, 0.08388, 0.09200, 0.09751, 0.10113, 0.10735, 0.10829, 0.11279, \ + 0.11488, 0.11546, 0.11556, 0.09097, 0.09595, 0.09990, 0.10270, 0.11121, \ + 0.11251, 0.12085, 0.12659, 0.13038, 0.13703, 0.13804, 0.14296, 0.14528, \ + 0.14594, 0.14605, 0.14179, 0.14681, 0.15079, 0.15361, 0.16224, 0.16357, \ + 0.17211, 0.17805, 0.18201, 0.18902, 0.19010, 0.19540, 0.19793, 0.19870, \ + 0.19878 "); + } + } + + capacitance () { + top_plane: metal8; + bottom_plane: metal5; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.06396, 0.04412, 0.03466, 0.02976, 0.01916, 0.01792, 0.01139, 0.00796, \ + 0.00601, 0.00302, 0.00263, 0.00088, 0.00019, 0.00002, 0.00000, 0.06677, \ + 0.04646, 0.03671, 0.03163, 0.02059, 0.01930, 0.01241, 0.00875, 0.00664, \ + 0.00339, 0.00295, 0.00100, 0.00022, 0.00002, 0.00000, 0.06693, 0.04660, \ + 0.03683, 0.03175, 0.02068, 0.01939, 0.01248, 0.00880, 0.00668, 0.00341, \ + 0.00297, 0.00100, 0.00022, 0.00002, 0.00000, 0.06943, 0.04878, 0.03880, \ + 0.03358, 0.02215, 0.02080, 0.01356, 0.00964, 0.00738, 0.00381, 0.00333, \ + 0.00114, 0.00025, 0.00003, 0.00000, 0.06986, 0.04918, 0.03917, 0.03392, \ + 0.02243, 0.02108, 0.01377, 0.00982, 0.00752, 0.00390, 0.00341, 0.00116, \ + 0.00026, 0.00003, 0.00000, 0.07165, 0.05079, 0.04066, 0.03533, 0.02358, \ + 0.02218, 0.01463, 0.01050, 0.00809, 0.00423, 0.00371, 0.00128, 0.00028, \ + 0.00003, 0.00000, 0.07306, 0.05207, 0.04184, 0.03644, 0.02450, 0.02308, \ + 0.01533, 0.01106, 0.00855, 0.00451, 0.00395, 0.00137, 0.00031, 0.00004, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.02781, 0.03296, 0.03696, 0.03975, 0.04800, 0.04924, 0.05688, 0.06188, \ + 0.06505, 0.07024, 0.07099, 0.07437, 0.07576, 0.07611, 0.07616, 0.03874, \ + 0.04384, 0.04784, 0.05065, 0.05906, 0.06033, 0.06826, 0.07353, 0.07692, \ + 0.08255, 0.08338, 0.08715, 0.08872, 0.08909, 0.08914, 0.03958, 0.04468, \ + 0.04868, 0.05149, 0.05991, 0.06118, 0.06913, 0.07441, 0.07782, 0.08348, \ + 0.08431, 0.08811, 0.08969, 0.09006, 0.09011, 0.05813, 0.06321, 0.06721, \ + 0.07005, 0.07859, 0.07990, 0.08813, 0.09369, 0.09730, 0.10345, 0.10436, \ + 0.10858, 0.11037, 0.11079, 0.11084, 0.06320, 0.06828, 0.07228, 0.07512, \ + 0.08369, 0.08500, 0.09329, 0.09890, 0.10256, 0.10880, 0.10973, 0.11404, \ + 0.11587, 0.11630, 0.11636, 0.09221, 0.09730, 0.10133, 0.10419, 0.11288, \ + 0.11422, 0.12274, 0.12857, 0.13240, 0.13902, 0.14001, 0.14468, 0.14669, \ + 0.14716, 0.14722, 0.14409, 0.14921, 0.15328, 0.15617, 0.16499, 0.16635, \ + 0.17506, 0.18107, 0.18504, 0.19197, 0.19302, 0.19797, 0.20013, 0.20068, \ + 0.20070 "); + } + } + + capacitance () { + top_plane: metal8; + bottom_plane: metal4; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.06827, 0.04889, 0.03972, 0.03498, 0.02464, 0.02341, 0.01666, 0.01279, \ + 0.01040, 0.00621, 0.00558, 0.00236, 0.00069, 0.00011, 0.00000, 0.07227, \ + 0.05228, 0.04270, 0.03771, 0.02672, 0.02540, 0.01813, 0.01394, 0.01134, \ + 0.00678, 0.00610, 0.00258, 0.00075, 0.00012, 0.00000, 0.07252, 0.05248, \ + 0.04289, 0.03788, 0.02684, 0.02552, 0.01822, 0.01401, 0.01139, 0.00682, \ + 0.00613, 0.00260, 0.00076, 0.00012, 0.00000, 0.07621, 0.05565, 0.04570, \ + 0.04047, 0.02885, 0.02744, 0.01966, 0.01514, 0.01233, 0.00740, 0.00666, \ + 0.00283, 0.00083, 0.00013, 0.00000, 0.07683, 0.05620, 0.04620, 0.04093, \ + 0.02921, 0.02780, 0.01993, 0.01535, 0.01251, 0.00751, 0.00676, 0.00288, \ + 0.00084, 0.00014, 0.00000, 0.07915, 0.05825, 0.04805, 0.04265, 0.03057, \ + 0.02910, 0.02093, 0.01615, 0.01318, 0.00794, 0.00715, 0.00305, 0.00089, \ + 0.00015, 0.00000, 0.08072, 0.05965, 0.04933, 0.04385, 0.03154, 0.03004, \ + 0.02166, 0.01674, 0.01367, 0.00825, 0.00743, 0.00318, 0.00093, 0.00016, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.01473, 0.01728, 0.01926, 0.02066, 0.02508, 0.02579, 0.03067, 0.03449, \ + 0.03730, 0.04314, 0.04413, 0.04969, 0.05293, 0.05404, 0.05427, 0.01908, \ + 0.02143, 0.02334, 0.02473, 0.02924, 0.02998, 0.03513, 0.03920, 0.04223, \ + 0.04852, 0.04960, 0.05565, 0.05919, 0.06039, 0.06064, 0.01940, 0.02174, \ + 0.02365, 0.02504, 0.02957, 0.03031, 0.03547, 0.03956, 0.04261, 0.04892, \ + 0.05001, 0.05609, 0.05965, 0.06085, 0.06111, 0.02647, 0.02881, 0.03076, \ + 0.03218, 0.03688, 0.03766, 0.04311, 0.04746, 0.05071, 0.05748, 0.05864, \ + 0.06522, 0.06909, 0.07039, 0.07067, 0.02845, 0.03080, 0.03275, 0.03419, \ + 0.03893, 0.03970, 0.04522, 0.04962, 0.05290, 0.05975, 0.06093, 0.06760, \ + 0.07153, 0.07286, 0.07314, 0.04009, 0.04249, 0.04449, 0.04596, 0.05085, \ + 0.05166, 0.05738, 0.06196, 0.06538, 0.07256, 0.07379, 0.08082, 0.08497, \ + 0.08639, 0.08669, 0.06164, 0.06408, 0.06613, 0.06763, 0.07263, 0.07346, \ + 0.07933, 0.08404, 0.08756, 0.09498, 0.09625, 0.10354, 0.10787, 0.10947, \ + 0.10966 "); + } + } + + capacitance () { + top_plane: metal8; + bottom_plane: metal3; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.06912, 0.04985, 0.04076, 0.03608, 0.02592, 0.02473, 0.01813, 0.01433, \ + 0.01195, 0.00762, 0.00695, 0.00329, 0.00111, 0.00022, 0.00000, 0.07336, \ + 0.05348, 0.04400, 0.03907, 0.02826, 0.02697, 0.01984, 0.01569, 0.01307, \ + 0.00835, 0.00761, 0.00359, 0.00122, 0.00024, 0.00000, 0.07363, 0.05371, \ + 0.04421, 0.03926, 0.02841, 0.02711, 0.01995, 0.01578, 0.01315, 0.00839, \ + 0.00765, 0.00361, 0.00122, 0.00024, 0.00000, 0.07777, 0.05732, 0.04745, \ + 0.04226, 0.03078, 0.02939, 0.02168, 0.01716, 0.01430, 0.00913, 0.00833, \ + 0.00393, 0.00133, 0.00027, 0.00000, 0.07851, 0.05797, 0.04804, 0.04282, \ + 0.03122, 0.02982, 0.02201, 0.01742, 0.01452, 0.00927, 0.00845, 0.00400, \ + 0.00135, 0.00027, 0.00000, 0.08133, 0.06048, 0.05032, 0.04494, 0.03291, \ + 0.03145, 0.02326, 0.01842, 0.01536, 0.00981, 0.00895, 0.00423, 0.00143, \ + 0.00029, 0.00000, 0.08329, 0.06223, 0.05191, 0.04643, 0.03411, 0.03260, \ + 0.02415, 0.01914, 0.01596, 0.01020, 0.00930, 0.00440, 0.00149, 0.00031, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.01253, 0.01472, 0.01639, 0.01756, 0.02118, 0.02175, 0.02572, 0.02890, \ + 0.03132, 0.03667, 0.03763, 0.04351, 0.04756, 0.04928, 0.04974, 0.01610, \ + 0.01801, 0.01954, 0.02065, 0.02424, 0.02483, 0.02900, 0.03239, 0.03502, \ + 0.04080, 0.04185, 0.04826, 0.05269, 0.05455, 0.05505, 0.01635, 0.01825, \ + 0.01978, 0.02088, 0.02448, 0.02507, 0.02925, 0.03266, 0.03530, 0.04111, \ + 0.04217, 0.04861, 0.05306, 0.05493, 0.05543, 0.02170, 0.02352, 0.02504, \ + 0.02615, 0.02987, 0.03049, 0.03493, 0.03860, 0.04143, 0.04772, 0.04886, \ + 0.05585, 0.06068, 0.06271, 0.06326, 0.02316, 0.02499, 0.02652, 0.02764, \ + 0.03139, 0.03201, 0.03651, 0.04023, 0.04310, 0.04948, 0.05063, 0.05773, \ + 0.06263, 0.06470, 0.06526, 0.03187, 0.03374, 0.03531, 0.03647, 0.04038, \ + 0.04104, 0.04576, 0.04967, 0.05269, 0.05942, 0.06064, 0.06813, 0.07332, \ + 0.07551, 0.07610, 0.04834, 0.05026, 0.05189, 0.05309, 0.05713, 0.05782, \ + 0.06271, 0.06677, 0.06991, 0.07688, 0.07815, 0.08593, 0.09133, 0.09372, \ + 0.09423 "); + } + } + + capacitance () { + top_plane: metal8; + bottom_plane: metal2; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.06946, 0.05023, 0.04117, 0.03651, 0.02642, 0.02523, 0.01872, 0.01497, \ + 0.01261, 0.00828, 0.00760, 0.00380, 0.00139, 0.00031, 0.00000, 0.07378, \ + 0.05394, 0.04449, 0.03959, 0.02886, 0.02758, 0.02053, 0.01643, 0.01383, \ + 0.00909, 0.00834, 0.00415, 0.00152, 0.00034, 0.00000, 0.07405, 0.05417, \ + 0.04470, 0.03978, 0.02901, 0.02773, 0.02065, 0.01652, 0.01391, 0.00914, \ + 0.00838, 0.00418, 0.00153, 0.00034, 0.00000, 0.07836, 0.05795, 0.04812, \ + 0.04296, 0.03155, 0.03018, 0.02253, 0.01804, 0.01519, 0.00997, 0.00915, \ + 0.00456, 0.00166, 0.00037, 0.00000, 0.07914, 0.05865, 0.04876, 0.04356, \ + 0.03204, 0.03065, 0.02290, 0.01833, 0.01544, 0.01014, 0.00930, 0.00463, \ + 0.00169, 0.00038, 0.00000, 0.08221, 0.06139, 0.05126, 0.04590, 0.03392, \ + 0.03246, 0.02430, 0.01947, 0.01639, 0.01077, 0.00988, 0.00492, 0.00180, \ + 0.00040, 0.00000, 0.08444, 0.06339, 0.05309, 0.04762, 0.03531, 0.03380, \ + 0.02535, 0.02031, 0.01711, 0.01123, 0.01030, 0.00513, 0.00187, 0.00043, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.01167, 0.01374, 0.01532, 0.01641, 0.01976, 0.02029, 0.02392, 0.02683, \ + 0.02906, 0.03409, 0.03502, 0.04088, 0.04526, 0.04733, 0.04797, 0.01503, \ + 0.01678, 0.01819, 0.01920, 0.02246, 0.02300, 0.02677, 0.02987, 0.03229, \ + 0.03774, 0.03875, 0.04516, 0.04995, 0.05220, 0.05290, 0.01526, 0.01700, \ + 0.01840, 0.01941, 0.02267, 0.02321, 0.02699, 0.03011, 0.03254, 0.03802, \ + 0.03903, 0.04548, 0.05028, 0.05255, 0.05325, 0.02003, 0.02167, 0.02304, \ + 0.02404, 0.02738, 0.02794, 0.03196, 0.03531, 0.03792, 0.04387, 0.04498, \ + 0.05199, 0.05722, 0.05968, 0.06045, 0.02132, 0.02296, 0.02433, 0.02534, \ + 0.02871, 0.02927, 0.03334, 0.03674, 0.03940, 0.04544, 0.04656, 0.05368, \ + 0.05900, 0.06150, 0.06228, 0.02896, 0.03063, 0.03204, 0.03308, 0.03659, \ + 0.03719, 0.04148, 0.04508, 0.04789, 0.05429, 0.05548, 0.06303, 0.06867, \ + 0.07133, 0.07216, 0.04351, 0.04524, 0.04670, 0.04778, 0.05144, 0.05206, \ + 0.05654, 0.06029, 0.06323, 0.06991, 0.07115, 0.07902, 0.08491, 0.08779, \ + 0.08854 "); + } + } + + capacitance () { + top_plane: metal8; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.07003, 0.05085, 0.04182, 0.03719, 0.02718, 0.02601, 0.01962, 0.01596, \ + 0.01367, 0.00942, 0.00874, 0.00481, 0.00204, 0.00057, 0.00000, 0.07442, \ + 0.05464, 0.04524, 0.04037, 0.02977, 0.02851, 0.02160, 0.01760, 0.01506, \ + 0.01038, 0.00963, 0.00528, 0.00224, 0.00063, 0.00000, 0.07470, 0.05488, \ + 0.04546, 0.04058, 0.02993, 0.02867, 0.02173, 0.01770, 0.01515, 0.01044, \ + 0.00969, 0.00532, 0.00225, 0.00063, 0.00000, 0.07923, 0.05890, 0.04912, \ + 0.04401, 0.03274, 0.03139, 0.02388, 0.01948, 0.01668, 0.01150, 0.01066, \ + 0.00584, 0.00248, 0.00070, 0.00000, 0.08009, 0.05968, 0.04984, 0.04469, \ + 0.03330, 0.03193, 0.02431, 0.01984, 0.01699, 0.01171, 0.01086, 0.00595, \ + 0.00252, 0.00071, 0.00000, 0.08358, 0.06283, 0.05275, 0.04742, 0.03556, \ + 0.03412, 0.02606, 0.02128, 0.01823, 0.01257, 0.01165, 0.00638, 0.00271, \ + 0.00076, 0.00000, 0.08640, 0.06540, 0.05512, 0.04967, 0.03743, 0.03593, \ + 0.02752, 0.02249, 0.01927, 0.01328, 0.01231, 0.00674, 0.00286, 0.00081, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.01025, 0.01216, 0.01362, 0.01462, 0.01765, 0.01811, 0.02127, 0.02376, \ + 0.02567, 0.03008, 0.03092, 0.03650, 0.04127, 0.04404, 0.04521, 0.01337, \ + 0.01494, 0.01619, 0.01707, 0.01989, 0.02035, 0.02354, 0.02616, 0.02823, \ + 0.03300, 0.03392, 0.04003, 0.04526, 0.04828, 0.04957, 0.01357, 0.01513, \ + 0.01637, 0.01725, 0.02006, 0.02052, 0.02372, 0.02635, 0.02842, 0.03322, \ + 0.03414, 0.04029, 0.04554, 0.04859, 0.04988, 0.01766, 0.01905, 0.02019, \ + 0.02103, 0.02382, 0.02428, 0.02764, 0.03046, 0.03269, 0.03792, 0.03892, \ + 0.04565, 0.05141, 0.05474, 0.05616, 0.01871, 0.02009, 0.02123, 0.02207, \ + 0.02487, 0.02533, 0.02873, 0.03159, 0.03386, 0.03918, 0.04020, 0.04704, \ + 0.05290, 0.05630, 0.05775, 0.02483, 0.02620, 0.02736, 0.02822, 0.03111, \ + 0.03161, 0.03518, 0.03823, 0.04065, 0.04633, 0.04742, 0.05475, 0.06103, \ + 0.06467, 0.06622, 0.03646, 0.03788, 0.03908, 0.03997, 0.04301, 0.04352, \ + 0.04729, 0.05050, 0.05306, 0.05907, 0.06022, 0.06797, 0.07459, 0.07853, \ + 0.08007 "); + } + } + + capacitance () { + top_plane: metal9; + bottom_plane: metal5; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.06435, 0.04454, 0.03510, 0.03021, 0.01969, 0.01847, 0.01203, 0.00866, \ + 0.00674, 0.00375, 0.00335, 0.00144, 0.00049, 0.00012, 0.00000, 0.06721, \ + 0.04695, 0.03725, 0.03221, 0.02128, 0.02001, 0.01324, 0.00964, 0.00757, \ + 0.00429, 0.00385, 0.00168, 0.00058, 0.00014, 0.00000, 0.06739, 0.04710, \ + 0.03739, 0.03233, 0.02138, 0.02011, 0.01332, 0.00971, 0.00762, 0.00433, \ + 0.00388, 0.00169, 0.00059, 0.00014, 0.00000, 0.07013, 0.04955, 0.03964, \ + 0.03446, 0.02317, 0.02184, 0.01473, 0.01089, 0.00864, 0.00502, 0.00451, \ + 0.00202, 0.00071, 0.00017, 0.00000, 0.07064, 0.05003, 0.04009, 0.03489, \ + 0.02355, 0.02221, 0.01504, 0.01115, 0.00887, 0.00518, 0.00466, 0.00209, \ + 0.00074, 0.00018, 0.00000, 0.07295, 0.05217, 0.04211, 0.03682, 0.02523, \ + 0.02385, 0.01641, 0.01232, 0.00990, 0.00590, 0.00533, 0.00245, 0.00088, \ + 0.00021, 0.00000, 0.07527, 0.05435, 0.04418, 0.03882, 0.02700, 0.02558, \ + 0.01790, 0.01361, 0.01103, 0.00672, 0.00609, 0.00286, 0.00105, 0.00026, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.02683, 0.03188, 0.03579, 0.03851, 0.04650, 0.04769, 0.05498, 0.05973, \ + 0.06275, 0.06779, 0.06854, 0.07213, 0.07399, 0.07476, 0.07500, 0.03757, \ + 0.04251, 0.04636, 0.04906, 0.05707, 0.05827, 0.06576, 0.07073, 0.07395, \ + 0.07942, 0.08024, 0.08430, 0.08646, 0.08733, 0.08762, 0.03839, 0.04332, \ + 0.04717, 0.04987, 0.05787, 0.05908, 0.06658, 0.07156, 0.07479, 0.08029, \ + 0.08112, 0.08521, 0.08739, 0.08827, 0.08856, 0.05622, 0.06105, 0.06484, \ + 0.06752, 0.07554, 0.07676, 0.08445, 0.08967, 0.09309, 0.09909, 0.10001, \ + 0.10466, 0.10723, 0.10828, 0.10864, 0.06104, 0.06586, 0.06964, 0.07231, \ + 0.08034, 0.08156, 0.08929, 0.09455, 0.09802, 0.10412, 0.10506, 0.10984, \ + 0.11249, 0.11359, 0.11396, 0.08840, 0.09316, 0.09693, 0.09959, 0.10766, \ + 0.10890, 0.11680, 0.12227, 0.12593, 0.13248, 0.13352, 0.13885, 0.14193, \ + 0.14324, 0.14368, 0.13684, 0.14161, 0.14537, 0.14805, 0.15619, 0.15745, \ + 0.16554, 0.17122, 0.17507, 0.18211, 0.18324, 0.18920, 0.19275, 0.19434, \ + 0.19483 "); + } + } + + capacitance () { + top_plane: metal9; + bottom_plane: metal4; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.06883, 0.04949, 0.04034, 0.03562, 0.02535, 0.02414, 0.01751, 0.01374, \ + 0.01142, 0.00733, 0.00671, 0.00339, 0.00136, 0.00038, 0.00000, 0.07288, \ + 0.05293, 0.04341, 0.03844, 0.02757, 0.02628, 0.01917, 0.01510, 0.01257, \ + 0.00812, 0.00744, 0.00378, 0.00152, 0.00043, 0.00000, 0.07313, 0.05315, \ + 0.04360, 0.03862, 0.02771, 0.02641, 0.01927, 0.01518, 0.01265, 0.00817, \ + 0.00749, 0.00380, 0.00153, 0.00043, 0.00000, 0.07704, 0.05656, 0.04668, \ + 0.04149, 0.03003, 0.02865, 0.02105, 0.01666, 0.01392, 0.00907, 0.00832, \ + 0.00427, 0.00174, 0.00050, 0.00000, 0.07774, 0.05719, 0.04726, 0.04204, \ + 0.03048, 0.02910, 0.02141, 0.01696, 0.01419, 0.00926, 0.00850, 0.00437, \ + 0.00179, 0.00051, 0.00000, 0.08057, 0.05975, 0.04963, 0.04428, 0.03237, \ + 0.03093, 0.02292, 0.01825, 0.01532, 0.01009, 0.00928, 0.00483, 0.00199, \ + 0.00057, 0.00000, 0.08303, 0.06203, 0.05177, 0.04633, 0.03416, 0.03268, \ + 0.02441, 0.01954, 0.01648, 0.01095, 0.01009, 0.00531, 0.00221, 0.00065, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.01334, 0.01576, 0.01765, 0.01898, 0.02313, 0.02379, 0.02823, 0.03165, \ + 0.03416, 0.03943, 0.04035, 0.04574, 0.04949, 0.05136, 0.05214, 0.01753, \ + 0.01972, 0.02149, 0.02276, 0.02685, 0.02751, 0.03209, 0.03568, 0.03837, \ + 0.04401, 0.04501, 0.05091, 0.05506, 0.05714, 0.05802, 0.01783, 0.02001, \ + 0.02177, 0.02305, 0.02714, 0.02780, 0.03238, 0.03599, 0.03868, 0.04436, \ + 0.04535, 0.05129, 0.05546, 0.05755, 0.05844, 0.02426, 0.02635, 0.02808, \ + 0.02933, 0.03346, 0.03414, 0.03889, 0.04268, 0.04553, 0.05161, 0.05269, \ + 0.05917, 0.06381, 0.06616, 0.06718, 0.02600, 0.02808, 0.02980, 0.03106, \ + 0.03520, 0.03588, 0.04067, 0.04449, 0.04737, 0.05353, 0.05463, 0.06122, \ + 0.06596, 0.06838, 0.06942, 0.03601, 0.03809, 0.03981, 0.04108, 0.04528, \ + 0.04598, 0.05089, 0.05486, 0.05786, 0.06435, 0.06550, 0.07258, 0.07776, \ + 0.08045, 0.08162, 0.05418, 0.05626, 0.05800, 0.05928, 0.06353, 0.06424, \ + 0.06928, 0.07337, 0.07649, 0.08329, 0.08452, 0.09209, 0.09773, 0.10083, \ + 0.10203 "); + } + } + + capacitance () { + top_plane: metal9; + bottom_plane: metal3; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.06977, 0.05054, 0.04149, 0.03683, 0.02674, 0.02555, 0.01908, 0.01538, \ + 0.01308, 0.00890, 0.00824, 0.00453, 0.00199, 0.00063, 0.00000, 0.07407, \ + 0.05423, 0.04480, 0.03990, 0.02921, 0.02794, 0.02097, 0.01695, 0.01442, \ + 0.00984, 0.00911, 0.00501, 0.00222, 0.00070, 0.00000, 0.07434, 0.05447, \ + 0.04501, 0.04009, 0.02937, 0.02809, 0.02109, 0.01705, 0.01451, 0.00990, \ + 0.00917, 0.00504, 0.00223, 0.00070, 0.00000, 0.07868, 0.05830, 0.04849, \ + 0.04336, 0.03204, 0.03068, 0.02315, 0.01877, 0.01600, 0.01096, 0.01016, \ + 0.00562, 0.00250, 0.00079, 0.00000, 0.07949, 0.05904, 0.04917, 0.04400, \ + 0.03257, 0.03120, 0.02357, 0.01912, 0.01631, 0.01118, 0.01037, 0.00574, \ + 0.00256, 0.00081, 0.00000, 0.08281, 0.06204, 0.05195, 0.04663, 0.03477, \ + 0.03333, 0.02532, 0.02060, 0.01761, 0.01213, 0.01126, 0.00627, 0.00281, \ + 0.00090, 0.00000, 0.08565, 0.06466, 0.05440, 0.04896, 0.03678, 0.03529, \ + 0.02696, 0.02202, 0.01887, 0.01306, 0.01214, 0.00681, 0.00307, 0.00099, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.01092, 0.01296, 0.01453, 0.01562, 0.01897, 0.01950, 0.02304, 0.02580, \ + 0.02788, 0.03251, 0.03337, 0.03883, 0.04325, 0.04583, 0.04710, 0.01433, \ + 0.01607, 0.01746, 0.01846, 0.02163, 0.02215, 0.02573, 0.02862, 0.03085, \ + 0.03583, 0.03676, 0.04273, 0.04759, 0.05043, 0.05185, 0.01456, 0.01629, \ + 0.01767, 0.01866, 0.02183, 0.02235, 0.02594, 0.02883, 0.03107, 0.03608, \ + 0.03701, 0.04301, 0.04790, 0.05076, 0.05219, 0.01931, 0.02088, 0.02218, \ + 0.02313, 0.02627, 0.02679, 0.03050, 0.03357, 0.03595, 0.04135, 0.04236, \ + 0.04891, 0.05431, 0.05750, 0.05910, 0.02054, 0.02210, 0.02340, 0.02435, \ + 0.02749, 0.02801, 0.03176, 0.03486, 0.03727, 0.04275, 0.04378, 0.05044, \ + 0.05595, 0.05921, 0.06085, 0.02765, 0.02920, 0.03050, 0.03145, 0.03466, \ + 0.03520, 0.03909, 0.04233, 0.04487, 0.05068, 0.05177, 0.05891, 0.06487, \ + 0.06845, 0.07026, 0.04078, 0.04235, 0.04366, 0.04464, 0.04793, 0.04849, \ + 0.05250, 0.05588, 0.05853, 0.06464, 0.06580, 0.07340, 0.07982, 0.08382, \ + 0.08572 "); + } + } + + capacitance () { + top_plane: metal9; + bottom_plane: metal2; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.07015, 0.05097, 0.04194, 0.03731, 0.02729, 0.02611, 0.01971, 0.01607, \ + 0.01380, 0.00963, 0.00896, 0.00514, 0.00238, 0.00080, 0.00000, 0.07453, \ + 0.05474, 0.04534, 0.04046, 0.02985, 0.02860, 0.02171, 0.01773, 0.01523, \ + 0.01065, 0.00992, 0.00568, 0.00264, 0.00089, 0.00000, 0.07481, 0.05498, \ + 0.04555, 0.04067, 0.03002, 0.02876, 0.02183, 0.01784, 0.01532, 0.01071, \ + 0.00998, 0.00572, 0.00266, 0.00089, 0.00000, 0.07931, 0.05898, 0.04921, \ + 0.04410, 0.03285, 0.03150, 0.02405, 0.01969, 0.01694, 0.01187, 0.01106, \ + 0.00635, 0.00297, 0.00100, 0.00000, 0.08016, 0.05976, 0.04993, 0.04478, \ + 0.03342, 0.03206, 0.02450, 0.02008, 0.01728, 0.01212, 0.01129, 0.00649, \ + 0.00304, 0.00102, 0.00000, 0.08373, 0.06299, 0.05293, 0.04762, 0.03581, \ + 0.03438, 0.02640, 0.02169, 0.01870, 0.01315, 0.01226, 0.00708, 0.00332, \ + 0.00112, 0.00000, 0.08683, 0.06585, 0.05561, 0.05017, 0.03800, 0.03651, \ + 0.02819, 0.02322, 0.02006, 0.01416, 0.01321, 0.00766, 0.00361, 0.00124, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.00996, 0.01186, 0.01332, 0.01433, 0.01741, 0.01789, 0.02110, 0.02358, \ + 0.02546, 0.02973, 0.03053, 0.03585, 0.04050, 0.04345, 0.04506, 0.01312, \ + 0.01472, 0.01598, 0.01688, 0.01973, 0.02019, 0.02338, 0.02596, 0.02797, \ + 0.03256, 0.03343, 0.03925, 0.04435, 0.04760, 0.04939, 0.01333, 0.01491, \ + 0.01617, 0.01706, 0.01990, 0.02036, 0.02356, 0.02614, 0.02816, 0.03277, \ + 0.03365, 0.03950, 0.04463, 0.04789, 0.04970, 0.01754, 0.01893, 0.02008, \ + 0.02091, 0.02368, 0.02414, 0.02742, 0.03015, 0.03230, 0.03729, 0.03824, \ + 0.04464, 0.05029, 0.05392, 0.05594, 0.01860, 0.01998, 0.02112, 0.02195, \ + 0.02471, 0.02517, 0.02848, 0.03125, 0.03343, 0.03849, 0.03946, 0.04598, \ + 0.05174, 0.05545, 0.05751, 0.02467, 0.02602, 0.02715, 0.02798, 0.03080, \ + 0.03127, 0.03472, 0.03763, 0.03993, 0.04532, 0.04636, 0.05335, 0.05959, \ + 0.06364, 0.06591, 0.03591, 0.03727, 0.03843, 0.03928, 0.04218, 0.04268, \ + 0.04626, 0.04931, 0.05173, 0.05744, 0.05853, 0.06599, 0.07270, 0.07718, \ + 0.07957 "); + } + } + + capacitance () { + top_plane: metal9; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.07080, 0.05169, 0.04271, 0.03810, 0.02818, 0.02702, 0.02073, 0.01718, \ + 0.01497, 0.01090, 0.01025, 0.00634, 0.00327, 0.00126, 0.00000, 0.07529, \ + 0.05556, 0.04620, 0.04137, 0.03087, 0.02964, 0.02288, 0.01901, 0.01657, \ + 0.01208, 0.01135, 0.00701, 0.00362, 0.00140, 0.00000, 0.07557, 0.05581, \ + 0.04643, 0.04158, 0.03105, 0.02981, 0.02302, 0.01913, 0.01668, 0.01216, \ + 0.01143, 0.00706, 0.00364, 0.00140, 0.00000, 0.08029, 0.06002, 0.05031, \ + 0.04524, 0.03413, 0.03280, 0.02549, 0.02123, 0.01854, 0.01353, 0.01272, \ + 0.00785, 0.00406, 0.00157, 0.00000, 0.08121, 0.06087, 0.05111, 0.04600, \ + 0.03477, 0.03343, 0.02601, 0.02168, 0.01894, 0.01382, 0.01299, 0.00803, \ + 0.00415, 0.00160, 0.00000, 0.08518, 0.06451, 0.05450, 0.04922, 0.03753, \ + 0.03611, 0.02824, 0.02360, 0.02063, 0.01508, 0.01418, 0.00877, 0.00453, \ + 0.00175, 0.00000, 0.08884, 0.06791, 0.05769, 0.05228, 0.04017, 0.03869, \ + 0.03041, 0.02547, 0.02229, 0.01633, 0.01535, 0.00950, 0.00492, 0.00192, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.00835, 0.01004, 0.01134, 0.01225, 0.01497, 0.01539, 0.01814, 0.02021, \ + 0.02177, 0.02534, 0.02603, 0.03084, 0.03562, 0.03922, 0.04173, 0.01119, \ + 0.01259, 0.01368, 0.01445, 0.01687, 0.01725, 0.01988, 0.02197, 0.02361, \ + 0.02743, 0.02818, 0.03345, 0.03869, 0.04265, 0.04542, 0.01138, 0.01276, \ + 0.01384, 0.01461, 0.01700, 0.01739, 0.02001, 0.02211, 0.02375, 0.02759, \ + 0.02834, 0.03364, 0.03891, 0.04289, 0.04568, 0.01491, 0.01606, 0.01699, \ + 0.01767, 0.01988, 0.02025, 0.02286, 0.02505, 0.02678, 0.03094, 0.03176, \ + 0.03758, 0.04340, 0.04781, 0.05092, 0.01576, 0.01687, 0.01779, 0.01845, \ + 0.02065, 0.02101, 0.02364, 0.02585, 0.02761, 0.03184, 0.03267, 0.03860, \ + 0.04454, 0.04904, 0.05222, 0.02035, 0.02141, 0.02229, 0.02294, 0.02514, \ + 0.02551, 0.02823, 0.03056, 0.03243, 0.03697, 0.03787, 0.04428, 0.05073, \ + 0.05564, 0.05912, 0.02873, 0.02979, 0.03069, 0.03135, 0.03363, 0.03402, \ + 0.03687, 0.03934, 0.04134, 0.04620, 0.04716, 0.05407, 0.06103, 0.06643, \ + 0.07012 "); + } + } + + capacitance () { + top_plane: metal10; + bottom_plane: metal5; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.06461, 0.04482, 0.03539, 0.03051, 0.02000, 0.01878, 0.01236, 0.00899, \ + 0.00709, 0.00411, 0.00371, 0.00179, 0.00078, 0.00030, 0.00000, 0.06750, \ + 0.04726, 0.03757, 0.03253, 0.02164, 0.02037, 0.01363, 0.01006, 0.00800, \ + 0.00476, 0.00431, 0.00213, 0.00095, 0.00036, 0.00000, 0.06768, 0.04741, \ + 0.03770, 0.03266, 0.02174, 0.02047, 0.01372, 0.01013, 0.00807, 0.00480, \ + 0.00435, 0.00215, 0.00096, 0.00037, 0.00000, 0.07048, 0.04992, 0.04003, \ + 0.03487, 0.02364, 0.02232, 0.01527, 0.01147, 0.00925, 0.00567, 0.00516, \ + 0.00263, 0.00121, 0.00047, 0.00000, 0.07102, 0.05043, 0.04052, 0.03534, \ + 0.02405, 0.02273, 0.01562, 0.01178, 0.00953, 0.00587, 0.00536, 0.00275, \ + 0.00127, 0.00050, 0.00000, 0.07352, 0.05278, 0.04276, 0.03750, 0.02598, \ + 0.02462, 0.01727, 0.01324, 0.01085, 0.00689, 0.00632, 0.00336, 0.00160, \ + 0.00065, 0.00000, 0.07635, 0.05549, 0.04536, 0.04003, 0.02830, 0.02690, \ + 0.01931, 0.01508, 0.01254, 0.00823, 0.00759, 0.00421, 0.00209, 0.00087, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.02616, 0.03115, 0.03502, 0.03772, 0.04564, 0.04682, 0.05404, 0.05874, \ + 0.06172, 0.06667, 0.06741, 0.07098, 0.07294, 0.07392, 0.07452, 0.03683, \ + 0.04171, 0.04551, 0.04818, 0.05608, 0.05727, 0.06463, 0.06950, 0.07265, \ + 0.07798, 0.07879, 0.08282, 0.08511, 0.08625, 0.08699, 0.03764, 0.04251, \ + 0.04631, 0.04898, 0.05687, 0.05806, 0.06543, 0.07031, 0.07347, 0.07883, \ + 0.07965, 0.08371, 0.08602, 0.08717, 0.08792, 0.05529, 0.06004, 0.06376, \ + 0.06638, 0.07422, 0.07541, 0.08288, 0.08793, 0.09125, 0.09706, 0.09796, \ + 0.10258, 0.10534, 0.10677, 0.10773, 0.06004, 0.06476, 0.06847, 0.07108, \ + 0.07890, 0.08009, 0.08758, 0.09267, 0.09602, 0.10193, 0.10285, 0.10760, \ + 0.11046, 0.11196, 0.11298, 0.08680, 0.09144, 0.09509, 0.09766, 0.10545, \ + 0.10664, 0.11423, 0.11948, 0.12298, 0.12931, 0.13032, 0.13566, 0.13905, \ + 0.14091, 0.14222, 0.13368, 0.13826, 0.14187, 0.14443, 0.15221, 0.15341, \ + 0.16111, 0.16653, 0.17020, 0.17701, 0.17812, 0.18418, 0.18826, 0.19067, \ + 0.19238 "); + } + } + + capacitance () { + top_plane: metal10; + bottom_plane: metal4; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.06923, 0.04992, 0.04079, 0.03608, 0.02582, 0.02462, 0.01800, 0.01426, \ + 0.01197, 0.00794, 0.00733, 0.00406, 0.00197, 0.00081, 0.00000, 0.07331, \ + 0.05338, 0.04387, 0.03891, 0.02808, 0.02679, 0.01972, 0.01570, 0.01321, \ + 0.00885, 0.00818, 0.00458, 0.00225, 0.00093, 0.00000, 0.07356, 0.05360, \ + 0.04406, 0.03909, 0.02822, 0.02693, 0.01983, 0.01579, 0.01329, 0.00891, \ + 0.00824, 0.00461, 0.00227, 0.00094, 0.00000, 0.07751, 0.05706, 0.04720, \ + 0.04203, 0.03063, 0.02927, 0.02175, 0.01742, 0.01475, 0.01001, 0.00928, \ + 0.00528, 0.00264, 0.00111, 0.00000, 0.07824, 0.05772, 0.04781, 0.04261, \ + 0.03112, 0.02975, 0.02215, 0.01778, 0.01506, 0.01025, 0.00951, 0.00544, \ + 0.00273, 0.00116, 0.00000, 0.08127, 0.06049, 0.05040, 0.04508, 0.03326, \ + 0.03184, 0.02394, 0.01937, 0.01651, 0.01140, 0.01061, 0.00619, 0.00318, \ + 0.00137, 0.00000, 0.08424, 0.06329, 0.05308, 0.04767, 0.03561, 0.03414, \ + 0.02600, 0.02124, 0.01824, 0.01283, 0.01198, 0.00717, 0.00378, 0.00168, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.01234, 0.01468, 0.01651, 0.01781, 0.02187, 0.02251, 0.02686, 0.03018, \ + 0.03260, 0.03761, 0.03848, 0.04359, 0.04733, 0.04950, 0.05112, 0.01645, \ + 0.01858, 0.02030, 0.02153, 0.02550, 0.02614, 0.03055, 0.03397, 0.03652, \ + 0.04182, 0.04275, 0.04832, 0.05246, 0.05490, 0.05677, 0.01675, 0.01887, \ + 0.02058, 0.02181, 0.02578, 0.02642, 0.03083, 0.03426, 0.03681, 0.04213, \ + 0.04306, 0.04867, 0.05283, 0.05529, 0.05717, 0.02304, 0.02504, 0.02669, \ + 0.02789, 0.03181, 0.03245, 0.03692, 0.04046, 0.04310, 0.04873, 0.04973, \ + 0.05582, 0.06047, 0.06329, 0.06553, 0.02471, 0.02670, 0.02834, 0.02953, \ + 0.03344, 0.03408, 0.03856, 0.04212, 0.04478, 0.05047, 0.05148, 0.05767, \ + 0.06243, 0.06535, 0.06766, 0.03416, 0.03609, 0.03770, 0.03887, 0.04275, \ + 0.04339, 0.04791, 0.05153, 0.05427, 0.06021, 0.06127, 0.06791, 0.07317, \ + 0.07651, 0.07925, 0.05074, 0.05264, 0.05422, 0.05538, 0.05923, 0.05987, \ + 0.06440, 0.06809, 0.07091, 0.07710, 0.07822, 0.08537, 0.09123, 0.09522, \ + 0.09846 "); + } + } + + capacitance () { + top_plane: metal10; + bottom_plane: metal3; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.07023, 0.05105, 0.04201, 0.03737, 0.02730, 0.02612, 0.01967, 0.01600, \ + 0.01372, 0.00961, 0.00897, 0.00535, 0.00279, 0.00122, 0.00000, 0.07457, \ + 0.05477, 0.04534, 0.04046, 0.02980, 0.02854, 0.02161, 0.01764, 0.01515, \ + 0.01068, 0.00997, 0.00598, 0.00314, 0.00138, 0.00000, 0.07485, 0.05500, \ + 0.04556, 0.04065, 0.02996, 0.02869, 0.02174, 0.01774, 0.01525, 0.01075, \ + 0.01004, 0.00602, 0.00317, 0.00139, 0.00000, 0.07923, 0.05888, 0.04910, \ + 0.04398, 0.03272, 0.03137, 0.02393, 0.01962, 0.01692, 0.01202, 0.01124, \ + 0.00681, 0.00363, 0.00162, 0.00000, 0.08006, 0.05964, 0.04980, 0.04465, \ + 0.03328, 0.03192, 0.02439, 0.02002, 0.01728, 0.01229, 0.01151, 0.00699, \ + 0.00373, 0.00167, 0.00000, 0.08357, 0.06284, 0.05279, 0.04749, 0.03573, \ + 0.03431, 0.02642, 0.02180, 0.01889, 0.01357, 0.01272, 0.00784, 0.00425, \ + 0.00193, 0.00000, 0.08692, 0.06598, 0.05577, 0.05037, 0.03829, 0.03682, \ + 0.02863, 0.02379, 0.02072, 0.01507, 0.01416, 0.00888, 0.00491, 0.00228, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.00977, 0.01168, 0.01318, 0.01423, 0.01747, 0.01798, 0.02143, 0.02409, \ + 0.02607, 0.03039, 0.03118, 0.03621, 0.04047, 0.04333, 0.04574, 0.01306, \ + 0.01472, 0.01605, 0.01701, 0.02006, 0.02055, 0.02397, 0.02668, 0.02875, \ + 0.03332, 0.03416, 0.03963, 0.04430, 0.04748, 0.05022, 0.01328, 0.01493, \ + 0.01626, 0.01721, 0.02026, 0.02075, 0.02416, 0.02688, 0.02895, 0.03354, \ + 0.03438, 0.03987, 0.04458, 0.04777, 0.05053, 0.01789, 0.01938, 0.02061, \ + 0.02150, 0.02443, 0.02492, 0.02834, 0.03113, 0.03328, 0.03814, 0.03905, \ + 0.04500, 0.05019, 0.05380, 0.05700, 0.01907, 0.02054, 0.02175, 0.02264, \ + 0.02556, 0.02604, 0.02947, 0.03228, 0.03445, 0.03936, 0.04028, 0.04632, \ + 0.05162, 0.05533, 0.05863, 0.02564, 0.02705, 0.02823, 0.02909, 0.03198, \ + 0.03246, 0.03593, 0.03880, 0.04104, 0.04618, 0.04715, 0.05360, 0.05939, \ + 0.06354, 0.06735, 0.03721, 0.03859, 0.03975, 0.04060, 0.04348, 0.04396, \ + 0.04746, 0.05040, 0.05271, 0.05806, 0.05908, 0.06598, 0.07232, 0.07711, \ + 0.08151 "); + } + } + + capacitance () { + top_plane: metal10; + bottom_plane: metal2; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.07065, 0.05152, 0.04252, 0.03790, 0.02791, 0.02674, 0.02036, 0.01674, \ + 0.01449, 0.01040, 0.00976, 0.00604, 0.00328, 0.00149, 0.00000, 0.07508, \ + 0.05532, 0.04594, 0.04108, 0.03050, 0.02925, 0.02240, 0.01847, 0.01601, \ + 0.01155, 0.01084, 0.00673, 0.00368, 0.00168, 0.00000, 0.07536, 0.05556, \ + 0.04616, 0.04128, 0.03067, 0.02941, 0.02253, 0.01859, 0.01612, 0.01162, \ + 0.01091, 0.00678, 0.00370, 0.00169, 0.00000, 0.07991, 0.05960, 0.04986, \ + 0.04476, 0.03358, 0.03224, 0.02487, 0.02060, 0.01791, 0.01299, 0.01221, \ + 0.00764, 0.00422, 0.00195, 0.00000, 0.08079, 0.06041, 0.05060, 0.04547, \ + 0.03418, 0.03283, 0.02537, 0.02103, 0.01830, 0.01329, 0.01249, 0.00784, \ + 0.00434, 0.00200, 0.00000, 0.08452, 0.06383, 0.05381, 0.04853, 0.03681, \ + 0.03540, 0.02755, 0.02294, 0.02003, 0.01466, 0.01380, 0.00874, 0.00490, \ + 0.00229, 0.00000, 0.08813, 0.06721, 0.05701, 0.05161, 0.03955, 0.03809, \ + 0.02990, 0.02505, 0.02196, 0.01623, 0.01531, 0.00983, 0.00560, 0.00268, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.00872, 0.01048, 0.01185, 0.01281, 0.01577, 0.01623, 0.01934, 0.02173, \ + 0.02351, 0.02745, 0.02818, 0.03300, 0.03739, 0.04057, 0.04350, 0.01174, \ + 0.01324, 0.01444, 0.01530, 0.01802, 0.01846, 0.02149, 0.02389, 0.02574, \ + 0.02989, 0.03067, 0.03590, 0.04070, 0.04423, 0.04753, 0.01194, 0.01343, \ + 0.01463, 0.01548, 0.01819, 0.01863, 0.02165, 0.02406, 0.02591, 0.03007, \ + 0.03085, 0.03611, 0.04094, 0.04449, 0.04781, 0.01601, 0.01732, 0.01839, \ + 0.01917, 0.02172, 0.02215, 0.02514, 0.02760, 0.02951, 0.03392, 0.03476, \ + 0.04046, 0.04577, 0.04975, 0.05357, 0.01702, 0.01830, 0.01936, 0.02013, \ + 0.02266, 0.02308, 0.02608, 0.02855, 0.03048, 0.03493, 0.03579, 0.04158, \ + 0.04700, 0.05108, 0.05501, 0.02257, 0.02378, 0.02479, 0.02553, 0.02802, \ + 0.02844, 0.03145, 0.03398, 0.03598, 0.04066, 0.04155, 0.04774, 0.05365, \ + 0.05818, 0.06267, 0.03226, 0.03344, 0.03443, 0.03516, 0.03765, 0.03807, \ + 0.04112, 0.04372, 0.04579, 0.05068, 0.05163, 0.05824, 0.06468, 0.06984, \ + 0.07498 "); + } + } + + capacitance () { + top_plane: metal10; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.07135, 0.05231, 0.04337, 0.03879, 0.02892, 0.02777, 0.02151, 0.01798, \ + 0.01579, 0.01180, 0.01117, 0.00741, 0.00438, 0.00218, 0.00000, 0.07594, \ + 0.05625, 0.04692, 0.04210, 0.03165, 0.03042, 0.02370, 0.01987, 0.01748, \ + 0.01311, 0.01241, 0.00823, 0.00488, 0.00243, 0.00000, 0.07622, 0.05650, \ + 0.04715, 0.04231, 0.03182, 0.03059, 0.02384, 0.02000, 0.01759, 0.01319, \ + 0.01249, 0.00829, 0.00491, 0.00245, 0.00000, 0.08100, 0.06077, 0.05108, \ + 0.04603, 0.03497, 0.03366, 0.02642, 0.02225, 0.01962, 0.01477, 0.01399, \ + 0.00932, 0.00555, 0.00279, 0.00000, 0.08194, 0.06164, 0.05189, 0.04680, \ + 0.03564, 0.03431, 0.02698, 0.02274, 0.02006, 0.01512, 0.01433, 0.00955, \ + 0.00570, 0.00286, 0.00000, 0.08607, 0.06544, 0.05547, 0.05022, 0.03862, \ + 0.03723, 0.02948, 0.02494, 0.02206, 0.01671, 0.01584, 0.01062, 0.00637, \ + 0.00323, 0.00000, 0.09023, 0.06935, 0.05918, 0.05380, 0.04180, 0.04035, \ + 0.03221, 0.02738, 0.02429, 0.01852, 0.01757, 0.01187, 0.00719, 0.00369, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.00696, 0.00846, 0.00964, 0.01046, 0.01301, 0.01341, 0.01604, 0.01802, \ + 0.01948, 0.02272, 0.02333, 0.02752, 0.03183, 0.03551, 0.03970, 0.00958, \ + 0.01085, 0.01186, 0.01258, 0.01484, 0.01520, 0.01766, 0.01959, 0.02107, \ + 0.02443, 0.02507, 0.02961, 0.03431, 0.03836, 0.04303, 0.00975, 0.01101, \ + 0.01201, 0.01272, 0.01497, 0.01533, 0.01778, 0.01971, 0.02119, 0.02455, \ + 0.02520, 0.02976, 0.03449, 0.03856, 0.04326, 0.01311, 0.01416, 0.01502, \ + 0.01563, 0.01764, 0.01797, 0.02030, 0.02221, 0.02371, 0.02724, 0.02793, \ + 0.03287, 0.03807, 0.04260, 0.04794, 0.01390, 0.01492, 0.01575, 0.01635, \ + 0.01833, 0.01865, 0.02097, 0.02288, 0.02438, 0.02795, 0.02865, 0.03367, \ + 0.03898, 0.04362, 0.04909, 0.01802, 0.01894, 0.01970, 0.02026, 0.02213, \ + 0.02245, 0.02473, 0.02667, 0.02823, 0.03197, 0.03272, 0.03811, 0.04388, \ + 0.04900, 0.05516, 0.02490, 0.02577, 0.02651, 0.02705, 0.02891, 0.02922, \ + 0.03154, 0.03354, 0.03516, 0.03912, 0.03991, 0.04571, 0.05200, 0.05774, \ + 0.06469 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: metal5; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.06486, 0.04509, 0.03567, 0.03080, 0.02030, 0.01908, 0.01265, 0.00928, \ + 0.00736, 0.00436, 0.00395, 0.00199, 0.00096, 0.00046, 0.00000, 0.06778, \ + 0.04755, 0.03787, 0.03284, 0.02196, 0.02069, 0.01396, 0.01039, 0.00832, \ + 0.00505, 0.00460, 0.00238, 0.00118, 0.00057, 0.00000, 0.06795, 0.04770, \ + 0.03801, 0.03297, 0.02207, 0.02080, 0.01405, 0.01046, 0.00839, 0.00510, \ + 0.00464, 0.00241, 0.00119, 0.00058, 0.00000, 0.07079, 0.05026, 0.04038, \ + 0.03522, 0.02401, 0.02269, 0.01565, 0.01186, 0.00964, 0.00604, 0.00553, \ + 0.00298, 0.00153, 0.00076, 0.00000, 0.07134, 0.05078, 0.04087, 0.03570, \ + 0.02444, 0.02311, 0.01602, 0.01218, 0.00993, 0.00627, 0.00575, 0.00313, \ + 0.00162, 0.00081, 0.00000, 0.07392, 0.05320, 0.04319, 0.03794, 0.02645, \ + 0.02509, 0.01777, 0.01375, 0.01137, 0.00741, 0.00684, 0.00389, 0.00210, \ + 0.00110, 0.00000, 0.07693, 0.05609, 0.04598, 0.04066, 0.02898, 0.02759, \ + 0.02004, 0.01584, 0.01331, 0.00904, 0.00841, 0.00504, 0.00289, 0.00159, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.02552, 0.03045, 0.03428, 0.03695, 0.04481, 0.04598, 0.05320, 0.05792, \ + 0.06092, 0.06596, 0.06671, 0.07037, 0.07239, 0.07341, 0.07432, 0.03611, \ + 0.04094, 0.04471, 0.04734, 0.05518, 0.05636, 0.06369, 0.06857, 0.07173, \ + 0.07713, 0.07795, 0.08206, 0.08440, 0.08559, 0.08674, 0.03692, 0.04174, \ + 0.04550, 0.04814, 0.05597, 0.05715, 0.06449, 0.06937, 0.07254, 0.07797, \ + 0.07880, 0.08293, 0.08530, 0.08650, 0.08766, 0.05445, 0.05915, 0.06283, \ + 0.06542, 0.07318, 0.07436, 0.08179, 0.08682, 0.09014, 0.09597, 0.09688, \ + 0.10154, 0.10434, 0.10582, 0.10736, 0.05916, 0.06384, 0.06750, 0.07009, \ + 0.07783, 0.07901, 0.08645, 0.09151, 0.09486, 0.10077, 0.10170, 0.10648, \ + 0.10938, 0.11094, 0.11258, 0.08572, 0.09030, 0.09390, 0.09645, 0.10414, \ + 0.10532, 0.11282, 0.11800, 0.12147, 0.12775, 0.12876, 0.13408, 0.13749, \ + 0.13942, 0.14163, 0.13208, 0.13659, 0.14014, 0.14266, 0.15028, 0.15146, \ + 0.15901, 0.16431, 0.16791, 0.17458, 0.17566, 0.18163, 0.18571, 0.18824, \ + 0.19139 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: metal4; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.06962, 0.05034, 0.04123, 0.03653, 0.02631, 0.02510, 0.01850, 0.01475, \ + 0.01245, 0.00840, 0.00779, 0.00449, 0.00238, 0.00119, 0.00000, 0.07374, \ + 0.05383, 0.04433, 0.03939, 0.02858, 0.02729, 0.02024, 0.01622, 0.01374, \ + 0.00937, 0.00870, 0.00508, 0.00274, 0.00139, 0.00000, 0.07399, 0.05405, \ + 0.04453, 0.03957, 0.02872, 0.02743, 0.02036, 0.01632, 0.01382, 0.00943, \ + 0.00876, 0.00512, 0.00276, 0.00141, 0.00000, 0.07798, 0.05755, 0.04770, \ + 0.04254, 0.03117, 0.02981, 0.02231, 0.01801, 0.01534, 0.01061, 0.00989, \ + 0.00591, 0.00327, 0.00171, 0.00000, 0.07872, 0.05822, 0.04832, 0.04313, \ + 0.03168, 0.03030, 0.02273, 0.01838, 0.01568, 0.01088, 0.01015, 0.00609, \ + 0.00340, 0.00178, 0.00000, 0.08182, 0.06106, 0.05098, 0.04567, 0.03389, \ + 0.03247, 0.02462, 0.02007, 0.01724, 0.01218, 0.01140, 0.00703, 0.00404, \ + 0.00219, 0.00000, 0.08496, 0.06404, 0.05385, 0.04846, 0.03644, 0.03499, \ + 0.02691, 0.02219, 0.01924, 0.01391, 0.01308, 0.00836, 0.00502, 0.00285, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.01137, 0.01360, 0.01537, 0.01663, 0.02059, 0.02122, 0.02551, 0.02882, \ + 0.03124, 0.03627, 0.03715, 0.04232, 0.04608, 0.04828, 0.05064, 0.01538, \ + 0.01743, 0.01909, 0.02029, 0.02416, 0.02479, 0.02912, 0.03252, 0.03504, \ + 0.04033, 0.04126, 0.04683, 0.05096, 0.05342, 0.05618, 0.01567, 0.01771, \ + 0.01937, 0.02057, 0.02444, 0.02506, 0.02940, 0.03279, 0.03532, 0.04063, \ + 0.04156, 0.04716, 0.05131, 0.05379, 0.05658, 0.02184, 0.02378, 0.02538, \ + 0.02655, 0.03036, 0.03099, 0.03537, 0.03884, 0.04144, 0.04699, 0.04797, \ + 0.05397, 0.05854, 0.06138, 0.06475, 0.02348, 0.02541, 0.02700, 0.02816, \ + 0.03197, 0.03259, 0.03697, 0.04045, 0.04307, 0.04866, 0.04965, 0.05573, \ + 0.06040, 0.06332, 0.06684, 0.03272, 0.03460, 0.03616, 0.03730, 0.04106, \ + 0.04168, 0.04605, 0.04956, 0.05222, 0.05796, 0.05899, 0.06540, 0.07050, \ + 0.07383, 0.07814, 0.04880, 0.05062, 0.05213, 0.05324, 0.05693, 0.05754, \ + 0.06186, 0.06537, 0.06804, 0.07391, 0.07497, 0.08173, 0.08734, 0.09132, \ + 0.09679 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: metal3; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.07069, 0.05155, 0.04255, 0.03792, 0.02790, 0.02672, 0.02028, 0.01661, \ + 0.01433, 0.01021, 0.00956, 0.00592, 0.00335, 0.00176, 0.00000, 0.07509, \ + 0.05532, 0.04591, 0.04104, 0.03041, 0.02916, 0.02225, 0.01828, 0.01580, \ + 0.01132, 0.01062, 0.00663, 0.00380, 0.00202, 0.00000, 0.07537, 0.05555, \ + 0.04613, 0.04124, 0.03058, 0.02931, 0.02238, 0.01839, 0.01590, 0.01140, \ + 0.01069, 0.00667, 0.00383, 0.00204, 0.00000, 0.07980, 0.05947, 0.04970, \ + 0.04460, 0.03337, 0.03202, 0.02461, 0.02032, 0.01763, 0.01275, 0.01198, \ + 0.00759, 0.00444, 0.00241, 0.00000, 0.08064, 0.06024, 0.05042, 0.04527, \ + 0.03394, 0.03259, 0.02508, 0.02074, 0.01801, 0.01305, 0.01227, 0.00780, \ + 0.00458, 0.00250, 0.00000, 0.08421, 0.06351, 0.05347, 0.04818, 0.03646, \ + 0.03505, 0.02720, 0.02262, 0.01973, 0.01447, 0.01364, 0.00884, 0.00532, \ + 0.00299, 0.00000, 0.08773, 0.06682, 0.05663, 0.05124, 0.03922, 0.03776, \ + 0.02964, 0.02486, 0.02184, 0.01629, 0.01541, 0.01026, 0.00640, 0.00374, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.00863, 0.01040, 0.01180, 0.01279, 0.01590, 0.01640, 0.01977, 0.02240, \ + 0.02438, 0.02871, 0.02951, 0.03455, 0.03877, 0.04161, 0.04504, 0.01176, \ + 0.01333, 0.01459, 0.01550, 0.01844, 0.01892, 0.02225, 0.02492, 0.02696, \ + 0.03149, 0.03233, 0.03773, 0.04232, 0.04544, 0.04937, 0.01198, 0.01354, \ + 0.01480, 0.01570, 0.01863, 0.01911, 0.02244, 0.02511, 0.02715, 0.03170, \ + 0.03254, 0.03796, 0.04257, 0.04572, 0.04968, 0.01645, 0.01787, 0.01904, \ + 0.01990, 0.02272, 0.02319, 0.02651, 0.02922, 0.03132, 0.03606, 0.03694, \ + 0.04272, 0.04772, 0.05125, 0.05592, 0.01760, 0.01900, 0.02016, 0.02101, \ + 0.02382, 0.02428, 0.02760, 0.03033, 0.03243, 0.03721, 0.03810, 0.04394, \ + 0.04903, 0.05264, 0.05749, 0.02399, 0.02533, 0.02645, 0.02728, 0.03004, \ + 0.03050, 0.03382, 0.03656, 0.03870, 0.04359, 0.04451, 0.05062, 0.05609, \ + 0.06010, 0.06586, 0.03506, 0.03636, 0.03745, 0.03825, 0.04095, 0.04140, \ + 0.04468, 0.04742, 0.04956, 0.05452, 0.05546, 0.06182, 0.06769, 0.07229, \ + 0.07937 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: metal2; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.07114, 0.05206, 0.04310, 0.03851, 0.02857, 0.02740, 0.02104, 0.01743, \ + 0.01518, 0.01107, 0.01042, 0.00669, 0.00393, 0.00213, 0.00000, 0.07566, \ + 0.05593, 0.04657, 0.04172, 0.03118, 0.02994, 0.02311, 0.01919, 0.01674, \ + 0.01227, 0.01156, 0.00746, 0.00443, 0.00243, 0.00000, 0.07594, 0.05617, \ + 0.04679, 0.04193, 0.03135, 0.03010, 0.02325, 0.01931, 0.01684, 0.01235, \ + 0.01164, 0.00751, 0.00446, 0.00245, 0.00000, 0.08054, 0.06026, 0.05053, \ + 0.04545, 0.03429, 0.03296, 0.02562, 0.02136, 0.01869, 0.01380, 0.01302, \ + 0.00850, 0.00513, 0.00287, 0.00000, 0.08143, 0.06107, 0.05129, 0.04617, \ + 0.03491, 0.03356, 0.02613, 0.02181, 0.01910, 0.01413, 0.01334, 0.00873, \ + 0.00529, 0.00297, 0.00000, 0.08523, 0.06456, 0.05455, 0.04928, 0.03760, \ + 0.03620, 0.02839, 0.02382, 0.02093, 0.01564, 0.01479, 0.00984, 0.00609, \ + 0.00350, 0.00000, 0.08900, 0.06811, 0.05793, 0.05255, 0.04054, 0.03908, \ + 0.03096, 0.02617, 0.02314, 0.01753, 0.01663, 0.01132, 0.00722, 0.00430, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.00750, 0.00909, 0.01035, 0.01124, 0.01403, 0.01448, 0.01749, 0.01985, \ + 0.02162, 0.02557, 0.02630, 0.03112, 0.03543, 0.03855, 0.04265, 0.01031, \ + 0.01171, 0.01283, 0.01364, 0.01623, 0.01665, 0.01958, 0.02194, 0.02376, \ + 0.02786, 0.02863, 0.03378, 0.03843, 0.04185, 0.04652, 0.01051, 0.01189, \ + 0.01301, 0.01381, 0.01639, 0.01681, 0.01974, 0.02210, 0.02392, 0.02803, \ + 0.02880, 0.03397, 0.03865, 0.04209, 0.04679, 0.01441, 0.01565, 0.01666, \ + 0.01740, 0.01984, 0.02025, 0.02313, 0.02551, 0.02736, 0.03164, 0.03245, \ + 0.03793, 0.04299, 0.04681, 0.05230, 0.01540, 0.01661, 0.01761, 0.01834, \ + 0.02076, 0.02116, 0.02404, 0.02642, 0.02828, 0.03259, 0.03341, 0.03895, \ + 0.04409, 0.04800, 0.05367, 0.02076, 0.02191, 0.02287, 0.02357, 0.02593, \ + 0.02633, 0.02919, 0.03159, 0.03348, 0.03788, 0.03873, 0.04451, 0.04999, \ + 0.05429, 0.06095, 0.02997, 0.03107, 0.03200, 0.03268, 0.03498, 0.03537, \ + 0.03820, 0.04059, 0.04248, 0.04695, 0.04781, 0.05380, 0.05965, 0.06450, \ + 0.07256 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.07191, 0.05294, 0.04406, 0.03952, 0.02973, 0.02859, 0.02237, 0.01885, \ + 0.01667, 0.01266, 0.01202, 0.00825, 0.00524, 0.00306, 0.00000, 0.07662, \ + 0.05698, 0.04768, 0.04289, 0.03249, 0.03127, 0.02459, 0.02077, 0.01838, \ + 0.01402, 0.01332, 0.00916, 0.00585, 0.00344, 0.00000, 0.07691, 0.05723, \ + 0.04792, 0.04310, 0.03267, 0.03144, 0.02473, 0.02090, 0.01850, 0.01411, \ + 0.01340, 0.00922, 0.00590, 0.00347, 0.00000, 0.08178, 0.06158, 0.05191, \ + 0.04687, 0.03586, 0.03455, 0.02735, 0.02319, 0.02058, 0.01577, 0.01499, \ + 0.01038, 0.00671, 0.00400, 0.00000, 0.08274, 0.06246, 0.05273, 0.04766, \ + 0.03654, 0.03521, 0.02791, 0.02369, 0.02104, 0.01614, 0.01535, 0.01065, \ + 0.00690, 0.00412, 0.00000, 0.08693, 0.06632, 0.05637, 0.05113, 0.03957, \ + 0.03818, 0.03048, 0.02598, 0.02314, 0.01787, 0.01701, 0.01192, 0.00783, \ + 0.00476, 0.00000, 0.09124, 0.07039, 0.06024, 0.05488, 0.04294, 0.04149, \ + 0.03342, 0.02866, 0.02563, 0.01999, 0.01907, 0.01357, 0.00910, 0.00569, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000, 1.5000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5000, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.00559, 0.00686, 0.00788, 0.00860, 0.01090, 0.01126, 0.01374, 0.01565, \ + 0.01709, 0.02033, 0.02094, 0.02512, 0.02928, 0.03276, 0.03846, 0.00788, \ + 0.00900, 0.00991, 0.01055, 0.01263, 0.01297, 0.01530, 0.01716, 0.01860, \ + 0.02190, 0.02254, 0.02695, 0.03140, 0.03518, 0.04158, 0.00804, 0.00915, \ + 0.01005, 0.01069, 0.01276, 0.01309, 0.01541, 0.01727, 0.01872, 0.02202, \ + 0.02265, 0.02708, 0.03155, 0.03535, 0.04180, 0.01115, 0.01211, 0.01290, \ + 0.01347, 0.01534, 0.01565, 0.01785, 0.01968, 0.02111, 0.02449, 0.02515, \ + 0.02981, 0.03460, 0.03876, 0.04615, 0.01191, 0.01284, 0.01360, 0.01416, \ + 0.01600, 0.01631, 0.01849, 0.02031, 0.02174, 0.02514, 0.02580, 0.03050, \ + 0.03537, 0.03961, 0.04722, 0.01584, 0.01669, 0.01739, 0.01791, 0.01965, \ + 0.01994, 0.02207, 0.02387, 0.02530, 0.02875, 0.02943, 0.03432, 0.03947, \ + 0.04408, 0.05282, 0.02228, 0.02307, 0.02373, 0.02422, 0.02589, 0.02618, \ + 0.02825, 0.03004, 0.03147, 0.03496, 0.03565, 0.04069, 0.04612, 0.05120, \ + 0.06151 "); + } + } + } + + layer (metal5) { + resistance: 0.210000 + + capacitance () { + top_plane: metal6; + bottom_plane: metal4; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.05924, 0.03873, 0.02365, 0.01261, 0.00528, 0.00150, 0.00024, 0.00002, \ + 0.00000, 0.00000, 0.00000, 0.06027, 0.03941, 0.02405, 0.01282, 0.00536, \ + 0.00152, 0.00024, 0.00002, 0.00000, 0.00000, 0.00000, 0.06053, 0.03959, \ + 0.02415, 0.01287, 0.00538, 0.00153, 0.00024, 0.00002, 0.00000, 0.00000, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.04216, 0.05055, 0.06162, 0.07440, 0.08596, 0.09329, 0.09584, 0.09627, \ + 0.09628, 0.09637, 0.09636, 0.06296, 0.07160, 0.08293, 0.09594, 0.10770, \ + 0.11513, 0.11773, 0.11817, 0.11817, 0.11824, 0.11823, 0.10552, 0.11423, \ + 0.12562, 0.13870, 0.15050, 0.15797, 0.16057, 0.16102, 0.16102, 0.16108, \ + 0.16108 "); + } + } + + capacitance () { + top_plane: metal6; + bottom_plane: metal3; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.06250, 0.04241, 0.02767, 0.01664, 0.00862, 0.00348, 0.00094, 0.00014, \ + 0.00001, 0.00000, 0.00000, 0.06473, 0.04410, 0.02886, 0.01740, 0.00904, \ + 0.00366, 0.00099, 0.00015, 0.00001, 0.00000, 0.00000, 0.06612, 0.04519, \ + 0.02965, 0.01792, 0.00933, 0.00378, 0.00102, 0.00015, 0.00001, 0.00000, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.03170, 0.03774, 0.04591, 0.05601, 0.06665, 0.07548, 0.08037, 0.08199, \ + 0.08225, 0.08228, 0.08228, 0.04586, 0.05210, 0.06055, 0.07101, 0.08208, \ + 0.09130, 0.09643, 0.09815, 0.09842, 0.09843, 0.09842, 0.07541, 0.08179, \ + 0.09042, 0.10112, 0.11248, 0.12197, 0.12727, 0.12905, 0.12934, 0.12933, \ + 0.12933 "); + } + } + + capacitance () { + top_plane: metal6; + bottom_plane: metal2; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.06315, 0.04318, 0.02861, 0.01773, 0.00974, 0.00439, 0.00143, 0.00029, \ + 0.00003, 0.00000, 0.00000, 0.06573, 0.04522, 0.03013, 0.01878, 0.01039, \ + 0.00471, 0.00154, 0.00031, 0.00003, 0.00000, 0.00000, 0.06771, 0.04686, \ + 0.03139, 0.01968, 0.01095, 0.00499, 0.00164, 0.00033, 0.00003, 0.00000, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.02993, 0.03552, 0.04303, 0.05232, 0.06230, 0.07109, 0.07662, 0.07891, \ + 0.07944, 0.07950, 0.07950, 0.04289, 0.04860, 0.05632, 0.06594, 0.07637, \ + 0.08564, 0.09154, 0.09402, 0.09459, 0.09463, 0.09463, 0.06975, 0.07557, \ + 0.08346, 0.09334, 0.10416, 0.11386, 0.12010, 0.12274, 0.12335, 0.12338, \ + 0.12338 "); + } + } + + capacitance () { + top_plane: metal6; + bottom_plane: metal1; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.06350, 0.04360, 0.02912, 0.01836, 0.01045, 0.00504, 0.00185, 0.00046, \ + 0.00006, 0.00000, 0.00000, 0.06627, 0.04584, 0.03085, 0.01961, 0.01126, \ + 0.00548, 0.00203, 0.00050, 0.00007, 0.00000, 0.00000, 0.06865, 0.04786, \ + 0.03247, 0.02083, 0.01207, 0.00593, 0.00222, 0.00055, 0.00007, 0.00000, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.02900, 0.03436, 0.04152, 0.05034, 0.05987, 0.06847, 0.07429, 0.07706, \ + 0.07786, 0.07798, 0.07799, 0.04136, 0.04679, 0.05410, 0.06319, 0.07314, \ + 0.08227, 0.08854, 0.09158, 0.09247, 0.09257, 0.09258, 0.06675, 0.07224, \ + 0.07968, 0.08902, 0.09938, 0.10903, 0.11578, 0.11909, 0.12007, 0.12018, \ + 0.12018 "); + } + } + + capacitance () { + top_plane: metal6; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.06383, 0.04398, 0.02958, 0.01894, 0.01112, 0.00572, 0.00238, 0.00073, \ + 0.00014, 0.00001, 0.00000, 0.06675, 0.04639, 0.03150, 0.02038, 0.01213, \ + 0.00632, 0.00267, 0.00082, 0.00015, 0.00001, 0.00000, 0.06953, 0.04881, \ + 0.03351, 0.02197, 0.01327, 0.00703, 0.00301, 0.00093, 0.00018, 0.00002, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.02815, 0.03335, 0.04023, 0.04863, 0.05769, 0.06600, 0.07194, 0.07516, \ + 0.07636, 0.07662, 0.07664, 0.04005, 0.04524, 0.05218, 0.06078, 0.07022, \ + 0.07906, 0.08553, 0.08913, 0.09048, 0.09074, 0.09077, 0.06414, 0.06933, \ + 0.07635, 0.08514, 0.09497, 0.10439, 0.11148, 0.11551, 0.11705, 0.11735, \ + 0.11738 "); + } + } + + capacitance () { + top_plane: metal7; + bottom_plane: metal4; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.06297, 0.04297, 0.02835, 0.01743, 0.00941, 0.00411, 0.00126, 0.00023, \ + 0.00002, 0.00000, 0.00000, 0.06546, 0.04491, 0.02977, 0.01839, 0.00998, \ + 0.00438, 0.00135, 0.00025, 0.00002, 0.00000, 0.00000, 0.06726, 0.04638, \ + 0.03088, 0.01916, 0.01045, 0.00460, 0.00143, 0.00026, 0.00002, 0.00000, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.03040, 0.03611, 0.04380, 0.05332, 0.06351, 0.07234, 0.07770, 0.07978, \ + 0.08021, 0.08026, 0.08026, 0.04368, 0.04954, 0.05746, 0.06732, 0.07796, \ + 0.08725, 0.09294, 0.09518, 0.09564, 0.09566, 0.09565, 0.07128, 0.07726, \ + 0.08536, 0.09549, 0.10649, 0.11615, 0.12213, 0.12449, 0.12497, 0.12499, \ + 0.12498 "); + } + } + + capacitance () { + top_plane: metal7; + bottom_plane: metal3; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.06645, 0.04684, 0.03257, 0.02177, 0.01337, 0.00703, 0.00281, 0.00074, \ + 0.00011, 0.00000, 0.00000, 0.07005, 0.04972, 0.03473, 0.02325, 0.01427, \ + 0.00750, 0.00300, 0.00079, 0.00011, 0.00001, 0.00000, 0.07290, 0.05203, \ + 0.03646, 0.02444, 0.01501, 0.00788, 0.00315, 0.00083, 0.00012, 0.00001, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.01946, 0.02286, 0.02759, 0.03398, 0.04197, 0.05063, 0.05779, 0.06180, \ + 0.06311, 0.06326, 0.06327, 0.02629, 0.02976, 0.03471, 0.04148, 0.04998, \ + 0.05919, 0.06683, 0.07111, 0.07251, 0.07264, 0.07265, 0.04106, 0.04471, \ + 0.04992, 0.05705, 0.06599, 0.07567, 0.08369, 0.08819, 0.08966, 0.08978, \ + 0.08979 "); + } + } + + capacitance () { + top_plane: metal7; + bottom_plane: metal2; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.06720, 0.04771, 0.03361, 0.02298, 0.01468, 0.00825, 0.00367, 0.00114, \ + 0.00020, 0.00001, 0.00000, 0.07112, 0.05092, 0.03606, 0.02472, 0.01580, \ + 0.00887, 0.00395, 0.00122, 0.00022, 0.00002, 0.00000, 0.07453, 0.05374, \ + 0.03825, 0.02628, 0.01680, 0.00942, 0.00419, 0.00129, 0.00023, 0.00002, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.01744, 0.02041, 0.02448, 0.02999, 0.03704, 0.04509, 0.05244, 0.05720, \ + 0.05909, 0.05942, 0.05944, 0.02315, 0.02610, 0.03031, 0.03614, 0.04367, \ + 0.05230, 0.06019, 0.06531, 0.06734, 0.06766, 0.06769, 0.03532, 0.03841, \ + 0.04286, 0.04904, 0.05705, 0.06621, 0.07459, 0.08002, 0.08218, 0.08251, \ + 0.08255 "); + } + } + + capacitance () { + top_plane: metal7; + bottom_plane: metal1; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.06764, 0.04821, 0.03420, 0.02369, 0.01551, 0.00910, 0.00436, 0.00152, \ + 0.00032, 0.00003, 0.00000, 0.07173, 0.05160, 0.03685, 0.02563, 0.01680, \ + 0.00985, 0.00472, 0.00164, 0.00035, 0.00003, 0.00000, 0.07552, 0.05479, \ + 0.03937, 0.02748, 0.01804, 0.01058, 0.00507, 0.00176, 0.00037, 0.00004, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.01630, 0.01906, 0.02280, 0.02780, 0.03423, 0.04176, 0.04904, 0.05422, \ + 0.05662, 0.05715, 0.05722, 0.02147, 0.02414, 0.02794, 0.03320, 0.04006, \ + 0.04816, 0.05601, 0.06163, 0.06421, 0.06477, 0.06484, 0.03222, 0.03498, \ + 0.03897, 0.04456, 0.05189, 0.06055, 0.06896, 0.07500, 0.07777, 0.07836, \ + 0.07844 "); + } + } + + capacitance () { + top_plane: metal7; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.06808, 0.04869, 0.03476, 0.02437, 0.01633, 0.01001, 0.00519, 0.00207, \ + 0.00054, 0.00008, 0.00000, 0.07229, 0.05223, 0.03758, 0.02649, 0.01781, \ + 0.01093, 0.00568, 0.00226, 0.00060, 0.00008, 0.00000, 0.07645, 0.05580, \ + 0.04048, 0.02870, 0.01936, 0.01191, 0.00621, 0.00248, 0.00065, 0.00009, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.01519, 0.01779, 0.02126, 0.02583, 0.03165, 0.03856, 0.04556, 0.05106, \ + 0.05404, 0.05494, 0.05509, 0.01997, 0.02240, 0.02583, 0.03056, 0.03674, \ + 0.04417, 0.05176, 0.05775, 0.06101, 0.06198, 0.06215, 0.02947, 0.03193, \ + 0.03549, 0.04047, 0.04707, 0.05507, 0.06328, 0.06981, 0.07338, 0.07443, \ + 0.07461 "); + } + } + + capacitance () { + top_plane: metal8; + bottom_plane: metal4; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.06415, 0.04433, 0.02999, 0.01943, 0.01172, 0.00639, 0.00299, 0.00114, \ + 0.00031, 0.00005, 0.00000, 0.06716, 0.04686, 0.03205, 0.02105, 0.01291, \ + 0.00717, 0.00342, 0.00132, 0.00036, 0.00006, 0.00000, 0.07027, 0.04962, \ + 0.03443, 0.02301, 0.01442, 0.00820, 0.00401, 0.00158, 0.00044, 0.00007, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.02733, 0.03242, 0.03912, 0.04721, 0.05586, 0.06382, 0.06970, 0.07323, \ + 0.07488, 0.07542, 0.07552, 0.03896, 0.04396, 0.05062, 0.05881, 0.06775, \ + 0.07620, 0.08264, 0.08664, 0.08854, 0.08914, 0.08926, 0.06202, 0.06696, \ + 0.07359, 0.08188, 0.09114, 0.10015, 0.10730, 0.11191, 0.11418, 0.11490, \ + 0.11504 "); + } + } + + capacitance () { + top_plane: metal8; + bottom_plane: metal3; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.06790, 0.04846, 0.03446, 0.02405, 0.01607, 0.00993, 0.00534, 0.00235, \ + 0.00075, 0.00015, 0.00000, 0.07197, 0.05188, 0.03722, 0.02616, 0.01759, \ + 0.01093, 0.00593, 0.00262, 0.00084, 0.00016, 0.00000, 0.07608, 0.05544, \ + 0.04018, 0.02852, 0.01935, 0.01215, 0.00666, 0.00297, 0.00096, 0.00019, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.01575, 0.01855, 0.02231, 0.02719, 0.03322, 0.04007, 0.04676, 0.05198, \ + 0.05506, 0.05622, 0.05653, 0.02109, 0.02371, 0.02738, 0.03234, 0.03865, \ + 0.04596, 0.05318, 0.05894, 0.06236, 0.06365, 0.06398, 0.03145, 0.03405, \ + 0.03776, 0.04287, 0.04949, 0.05728, 0.06513, 0.07151, 0.07537, 0.07684, \ + 0.07723 "); + } + } + + capacitance () { + top_plane: metal8; + bottom_plane: metal2; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.06879, 0.04947, 0.03563, 0.02538, 0.01752, 0.01136, 0.00652, 0.00309, \ + 0.00108, 0.00024, 0.00000, 0.07316, 0.05318, 0.03866, 0.02775, 0.01926, \ + 0.01252, 0.00721, 0.00342, 0.00120, 0.00026, 0.00000, 0.07779, 0.05723, \ + 0.04205, 0.03044, 0.02127, 0.01390, 0.00805, 0.00385, 0.00136, 0.00030, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.01339, 0.01576, 0.01888, 0.02289, 0.02789, 0.03387, 0.04027, 0.04590, \ + 0.04967, 0.05130, 0.05178, 0.01767, 0.01978, 0.02273, 0.02673, 0.03196, \ + 0.03837, 0.04530, 0.05149, 0.05565, 0.05744, 0.05799, 0.02552, 0.02757, \ + 0.03052, 0.03466, 0.04020, 0.04710, 0.05466, 0.06150, 0.06615, 0.06817, \ + 0.06878 "); + } + } + + capacitance () { + top_plane: metal8; + bottom_plane: metal1; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.06935, 0.05009, 0.03633, 0.02620, 0.01846, 0.01236, 0.00743, 0.00375, \ + 0.00142, 0.00034, 0.00000, 0.07386, 0.05396, 0.03954, 0.02874, 0.02036, \ + 0.01365, 0.00823, 0.00415, 0.00157, 0.00038, 0.00000, 0.07885, 0.05835, \ + 0.04324, 0.03171, 0.02260, 0.01520, 0.00919, 0.00464, 0.00177, 0.00043, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.01197, 0.01412, 0.01691, 0.02043, 0.02479, 0.03009, 0.03608, 0.04181, \ + 0.04606, 0.04812, 0.04883, 0.01575, 0.01759, 0.02013, 0.02357, 0.02808, \ + 0.03377, 0.04028, 0.04658, 0.05126, 0.05353, 0.05431, 0.02226, 0.02398, \ + 0.02648, 0.03000, 0.03480, 0.04097, 0.04811, 0.05509, 0.06030, 0.06284, \ + 0.06373 "); + } + } + + capacitance () { + top_plane: metal8; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.06993, 0.05073, 0.03705, 0.02702, 0.01943, 0.01346, 0.00853, 0.00465, \ + 0.00195, 0.00054, 0.00000, 0.07457, 0.05473, 0.04041, 0.02974, 0.02150, \ + 0.01491, 0.00946, 0.00514, 0.00216, 0.00060, 0.00000, 0.07989, 0.05946, \ + 0.04445, 0.03304, 0.02403, 0.01671, 0.01060, 0.00576, 0.00242, 0.00068, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.01051, 0.01246, 0.01497, 0.01808, 0.02183, 0.02638, 0.03175, 0.03735, \ + 0.04203, 0.04469, 0.04580, 0.01391, 0.01551, 0.01770, 0.02061, 0.02441, \ + 0.02927, 0.03511, 0.04128, 0.04644, 0.04937, 0.05060, 0.01927, 0.02070, \ + 0.02276, 0.02567, 0.02968, 0.03497, 0.04143, 0.04830, 0.05405, 0.05733, \ + 0.05871 "); + } + } + + capacitance () { + top_plane: metal9; + bottom_plane: metal4; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.06441, 0.04461, 0.03029, 0.01976, 0.01211, 0.00684, 0.00345, 0.00154, \ + 0.00056, 0.00015, 0.00000, 0.06746, 0.04718, 0.03241, 0.02147, 0.01342, \ + 0.00775, 0.00402, 0.00182, 0.00068, 0.00019, 0.00000, 0.07073, 0.05013, \ + 0.03501, 0.02368, 0.01520, 0.00906, 0.00486, 0.00227, 0.00087, 0.00024, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.02666, 0.03169, 0.03830, 0.04627, 0.05472, 0.06245, 0.06820, 0.07178, \ + 0.07369, 0.07453, 0.07484, 0.03819, 0.04311, 0.04963, 0.05760, 0.06625, \ + 0.07439, 0.08067, 0.08476, 0.08700, 0.08797, 0.08835, 0.06076, 0.06554, \ + 0.07195, 0.07991, 0.08877, 0.09741, 0.10439, 0.10917, 0.11192, 0.11315, \ + 0.11364 "); + } + } + + capacitance () { + top_plane: metal9; + bottom_plane: metal3; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.06826, 0.04884, 0.03486, 0.02448, 0.01657, 0.01053, 0.00602, 0.00299, \ + 0.00121, 0.00036, 0.00000, 0.07235, 0.05229, 0.03767, 0.02668, 0.01822, \ + 0.01168, 0.00676, 0.00340, 0.00139, 0.00042, 0.00000, 0.07662, 0.05603, \ + 0.04084, 0.02928, 0.02025, 0.01318, 0.00777, 0.00398, 0.00166, 0.00051, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.01486, 0.01759, 0.02126, 0.02601, 0.03179, 0.03826, 0.04457, 0.04967, \ + 0.05301, 0.05464, 0.05538, 0.02011, 0.02265, 0.02618, 0.03091, 0.03685, \ + 0.04368, 0.05046, 0.05609, 0.05983, 0.06168, 0.06254, 0.03002, 0.03247, \ + 0.03594, 0.04069, 0.04681, 0.05402, 0.06137, 0.06765, 0.07196, 0.07415, \ + 0.07518 "); + } + } + + capacitance () { + top_plane: metal9; + bottom_plane: metal2; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.06920, 0.04990, 0.03608, 0.02587, 0.01808, 0.01203, 0.00729, 0.00386, \ + 0.00167, 0.00053, 0.00000, 0.07359, 0.05364, 0.03916, 0.02831, 0.01993, \ + 0.01333, 0.00814, 0.00434, 0.00189, 0.00060, 0.00000, 0.07837, 0.05786, \ + 0.04275, 0.03124, 0.02221, 0.01501, 0.00927, 0.00500, 0.00221, 0.00071, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.01238, 0.01466, 0.01769, 0.02157, 0.02633, 0.03189, 0.03781, 0.04318, \ + 0.04714, 0.04930, 0.05038, 0.01657, 0.01860, 0.02141, 0.02519, 0.03003, \ + 0.03591, 0.04229, 0.04819, 0.05259, 0.05501, 0.05624, 0.02400, 0.02589, \ + 0.02861, 0.03238, 0.03740, 0.04364, 0.05057, 0.05712, 0.06212, 0.06492, \ + 0.06638 "); + } + } + + capacitance () { + top_plane: metal9; + bottom_plane: metal1; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.06979, 0.05057, 0.03684, 0.02674, 0.01907, 0.01308, 0.00828, 0.00462, \ + 0.00211, 0.00071, 0.00000, 0.07434, 0.05447, 0.04009, 0.02935, 0.02108, \ + 0.01452, 0.00923, 0.00516, 0.00237, 0.00081, 0.00000, 0.07946, 0.05901, \ + 0.04398, 0.03255, 0.02358, 0.01636, 0.01048, 0.00591, 0.00274, 0.00094, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.01086, 0.01290, 0.01559, 0.01898, 0.02310, 0.02797, 0.03341, 0.03877, \ + 0.04313, 0.04575, 0.04719, 0.01454, 0.01629, 0.01869, 0.02191, 0.02604, \ + 0.03117, 0.03704, 0.04293, 0.04776, 0.05067, 0.05231, 0.02064, 0.02222, \ + 0.02448, 0.02764, 0.03190, 0.03737, 0.04378, 0.05032, 0.05576, 0.05911, \ + 0.06101 "); + } + } + + capacitance () { + top_plane: metal9; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.07042, 0.05127, 0.03763, 0.02764, 0.02010, 0.01424, 0.00946, 0.00564, \ + 0.00279, 0.00103, 0.00000, 0.07511, 0.05531, 0.04102, 0.03041, 0.02228, \ + 0.01584, 0.01055, 0.00628, 0.00312, 0.00116, 0.00000, 0.08056, 0.06018, \ + 0.04524, 0.03393, 0.02508, 0.01793, 0.01199, 0.00717, 0.00357, 0.00134, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.00928, 0.01110, 0.01348, 0.01644, 0.01996, 0.02407, 0.02882, 0.03392, \ + 0.03858, 0.04178, 0.04385, 0.01254, 0.01405, 0.01609, 0.01879, 0.02221, \ + 0.02649, 0.03162, 0.03721, 0.04236, 0.04591, 0.04823, 0.01752, 0.01880, \ + 0.02063, 0.02318, 0.02665, 0.03121, 0.03683, 0.04306, 0.04885, 0.05289, \ + 0.05556 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: metal4; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.06486, 0.04508, 0.03080, 0.02030, 0.01266, 0.00737, 0.00396, 0.00200, \ + 0.00096, 0.00045, 0.00000, 0.06795, 0.04770, 0.03297, 0.02208, 0.01406, \ + 0.00840, 0.00465, 0.00241, 0.00119, 0.00058, 0.00000, 0.07135, 0.05079, \ + 0.03571, 0.02445, 0.01604, 0.00995, 0.00576, 0.00313, 0.00162, 0.00081, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.02553, 0.03046, 0.03696, 0.04482, 0.05321, 0.06092, 0.06671, 0.07038, \ + 0.07241, 0.07343, 0.07434, 0.03693, 0.04175, 0.04815, 0.05598, 0.06449, \ + 0.07254, 0.07880, 0.08295, 0.08532, 0.08653, 0.08769, 0.05917, 0.06385, \ + 0.07009, 0.07783, 0.08644, 0.09486, 0.10171, 0.10650, 0.10942, 0.11098, \ + 0.11261 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: metal3; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.06888, 0.04951, 0.03558, 0.02524, 0.01735, 0.01133, 0.00683, 0.00379, \ + 0.00195, 0.00095, 0.00000, 0.07303, 0.05301, 0.03843, 0.02749, 0.01908, \ + 0.01260, 0.00773, 0.00436, 0.00229, 0.00114, 0.00000, 0.07741, 0.05687, \ + 0.04173, 0.03024, 0.02131, 0.01435, 0.00903, 0.00527, 0.00286, 0.00148, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.01330, 0.01589, 0.01941, 0.02401, 0.02966, 0.03602, 0.04222, 0.04724, \ + 0.05064, 0.05251, 0.05441, 0.01841, 0.02083, 0.02422, 0.02878, 0.03451, \ + 0.04110, 0.04766, 0.05313, 0.05691, 0.05904, 0.06132, 0.02802, 0.03034, \ + 0.03364, 0.03814, 0.04393, 0.05071, 0.05765, 0.06365, 0.06797, 0.07052, \ + 0.07345 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: metal2; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.06992, 0.05068, 0.03692, 0.02676, 0.01900, 0.01297, 0.00826, 0.00485, \ + 0.00260, 0.00131, 0.00000, 0.07438, 0.05448, 0.04005, 0.02925, 0.02093, \ + 0.01439, 0.00927, 0.00551, 0.00301, 0.00154, 0.00000, 0.07928, 0.05880, \ + 0.04375, 0.03232, 0.02339, 0.01631, 0.01070, 0.00651, 0.00367, 0.00194, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.01060, 0.01270, 0.01553, 0.01924, 0.02386, 0.02928, 0.03502, 0.04021, \ + 0.04413, 0.04651, 0.04910, 0.01461, 0.01650, 0.01915, 0.02274, 0.02737, \ + 0.03298, 0.03903, 0.04464, 0.04895, 0.05162, 0.05466, 0.02174, 0.02351, \ + 0.02604, 0.02956, 0.03422, 0.03999, 0.04637, 0.05246, 0.05729, 0.06040, \ + 0.06421 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: metal1; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.07058, 0.05144, 0.03779, 0.02775, 0.02011, 0.01415, 0.00938, 0.00576, \ + 0.00323, 0.00168, 0.00000, 0.07524, 0.05541, 0.04109, 0.03041, 0.02219, \ + 0.01570, 0.01050, 0.00650, 0.00370, 0.00195, 0.00000, 0.08047, 0.06006, \ + 0.04509, 0.03374, 0.02487, 0.01779, 0.01206, 0.00761, 0.00444, 0.00241, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.00890, 0.01071, 0.01316, 0.01635, 0.02031, 0.02502, 0.03025, 0.03533, \ + 0.03954, 0.04232, 0.04561, 0.01233, 0.01393, 0.01616, 0.01917, 0.02308, \ + 0.02792, 0.03340, 0.03888, 0.04347, 0.04656, 0.05038, 0.01813, 0.01958, \ + 0.02166, 0.02455, 0.02845, 0.03342, 0.03919, 0.04510, 0.05019, 0.05374, \ + 0.05842 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.07131, 0.05226, 0.03873, 0.02882, 0.02134, 0.01551, 0.01077, 0.00701, \ + 0.00418, 0.00229, 0.00000, 0.07615, 0.05641, 0.04219, 0.03165, 0.02358, \ + 0.01721, 0.01202, 0.00786, 0.00473, 0.00262, 0.00000, 0.08173, 0.06139, \ + 0.04651, 0.03529, 0.02654, 0.01953, 0.01377, 0.00912, 0.00559, 0.00317, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2800, 0.5600 "); + index_2 (" 0.1400, 0.2100, 0.3150, 0.4725, 0.7088, 1.0631, 1.5947, 2.3920, \ + 3.5880, 5.3821, 538.2070 "); + values (" 0.00709, 0.00861, 0.01067, 0.01336, 0.01667, 0.02062, 0.02512, 0.02983, \ + 0.03416, 0.03739, 0.04178, 0.00997, 0.01130, 0.01313, 0.01559, 0.01877, \ + 0.02275, 0.02744, 0.03248, 0.03717, 0.04073, 0.04575, 0.01462, 0.01576, \ + 0.01740, 0.01968, 0.02278, 0.02680, 0.03171, 0.03712, 0.04226, 0.04628, \ + 0.05230 "); + } + } + } + + layer (metal4) { + resistance: 0.210000 + + capacitance () { + top_plane: metal5; + bottom_plane: metal3; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.05409, 0.03360, 0.02388, 0.01892, 0.00886, 0.00781, 0.00303, 0.00130, \ + 0.00064, 0.00007, 0.00000, 0.00000, 0.00000, 0.00000, 0.05460, 0.03393, \ + 0.02413, 0.01912, 0.00896, 0.00790, 0.00307, 0.00132, 0.00065, 0.00007, \ + 0.00000, 0.00000, 0.00000, 0.00000, 0.05462, 0.03395, 0.02414, 0.01913, \ + 0.00897, 0.00790, 0.00307, 0.00132, 0.00065, 0.00007, 0.00000, 0.00000, \ + 0.00000, 0.00000, 0.05477, 0.03404, 0.02421, 0.01918, 0.00899, 0.00792, \ + 0.00308, 0.00132, 0.00065, 0.00007, 0.00000, 0.00000, 0.00000, 0.00000, \ + 0.05475, 0.03404, 0.02420, 0.01918, 0.00899, 0.00792, 0.00308, 0.00132, \ + 0.00065, 0.00007, 0.00000, 0.00000, 0.00000, 0.00000, 0.05476, 0.03404, \ + 0.02421, 0.01918, 0.00899, 0.00792, 0.00308, 0.00132, 0.00065, 0.00007, \ + 0.00000, 0.00000, 0.00000, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.06910, 0.08108, 0.08965, 0.09530, 0.10938, 0.11116, 0.11965, 0.12323, \ + 0.12476, 0.12589, 0.12597, 0.12592, 0.12624, 0.12623, 0.10271, 0.11483, \ + 0.12348, 0.12919, 0.14341, 0.14521, 0.15378, 0.15740, 0.15894, 0.16010, \ + 0.16017, 0.16013, 0.16043, 0.16042, 0.10531, 0.11743, 0.12609, 0.13180, \ + 0.14603, 0.14782, 0.15640, 0.16003, 0.16156, 0.16272, 0.16280, 0.16275, \ + 0.16305, 0.16304, 0.16260, 0.17476, 0.18344, 0.18916, 0.20343, 0.20523, \ + 0.21384, 0.21747, 0.21901, 0.22016, 0.22024, 0.22020, 0.22049, 0.22049, \ + 0.17822, 0.19038, 0.19905, 0.20478, 0.21904, 0.22084, 0.22945, 0.23308, \ + 0.23462, 0.23578, 0.23586, 0.23581, 0.23611, 0.23610, 0.26688, 0.27904, \ + 0.28772, 0.29345, 0.30771, 0.30951, 0.31812, 0.32175, 0.32329, 0.32445, \ + 0.32453, 0.32448, 0.32478, 0.32478 "); + } + } + + capacitance () { + top_plane: metal5; + bottom_plane: metal2; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.06052, 0.04011, 0.03024, 0.02508, 0.01394, 0.01267, 0.00626, 0.00335, \ + 0.00198, 0.00037, 0.00003, 0.00000, 0.00000, 0.00000, 0.06185, 0.04103, \ + 0.03093, 0.02564, 0.01425, 0.01295, 0.00639, 0.00343, 0.00203, 0.00038, \ + 0.00003, 0.00000, 0.00000, 0.00000, 0.06191, 0.04107, 0.03096, 0.02567, \ + 0.01426, 0.01296, 0.00640, 0.00343, 0.00203, 0.00038, 0.00003, 0.00000, \ + 0.00000, 0.00000, 0.06239, 0.04139, 0.03121, 0.02587, 0.01437, 0.01306, \ + 0.00645, 0.00346, 0.00204, 0.00038, 0.00003, 0.00000, 0.00000, 0.00000, \ + 0.06239, 0.04140, 0.03121, 0.02587, 0.01437, 0.01306, 0.00645, 0.00346, \ + 0.00204, 0.00038, 0.00003, 0.00000, 0.00000, 0.00000, 0.06244, 0.04143, \ + 0.03124, 0.02589, 0.01438, 0.01307, 0.00646, 0.00346, 0.00205, 0.00038, \ + 0.00003, 0.00000, 0.00000, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.03771, 0.04519, 0.05108, 0.05522, 0.06719, 0.06892, 0.07871, 0.08399, \ + 0.08671, 0.08995, 0.09063, 0.09067, 0.09071, 0.09071, 0.05448, 0.06222, \ + 0.06829, 0.07254, 0.08479, 0.08656, 0.09656, 0.10196, 0.10473, 0.10804, \ + 0.10874, 0.10879, 0.10880, 0.10880, 0.05580, 0.06354, 0.06962, 0.07387, \ + 0.08614, 0.08791, 0.09792, 0.10333, 0.10610, 0.10942, 0.11011, 0.11016, \ + 0.11017, 0.11017, 0.08513, 0.09297, 0.09912, 0.10340, 0.11578, 0.11755, \ + 0.12765, 0.13309, 0.13588, 0.13922, 0.13993, 0.13997, 0.13998, 0.13998, \ + 0.09317, 0.10102, 0.10716, 0.11145, 0.12383, 0.12561, 0.13570, 0.14115, \ + 0.14394, 0.14728, 0.14799, 0.14803, 0.14804, 0.14804, 0.13890, 0.14676, \ + 0.15291, 0.15720, 0.16959, 0.17137, 0.18147, 0.18692, 0.18971, 0.19306, \ + 0.19376, 0.19381, 0.19382, 0.19382 "); + } + } + + capacitance () { + top_plane: metal5; + bottom_plane: metal1; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.06232, 0.04218, 0.03247, 0.02740, 0.01634, 0.01505, 0.00832, 0.00499, \ + 0.00327, 0.00084, 0.00012, 0.00001, 0.00000, 0.00000, 0.06435, 0.04370, \ + 0.03370, 0.02845, 0.01700, 0.01566, 0.00868, 0.00522, 0.00341, 0.00088, \ + 0.00012, 0.00001, 0.00000, 0.00000, 0.06446, 0.04378, 0.03376, 0.02851, \ + 0.01703, 0.01569, 0.00870, 0.00523, 0.00342, 0.00088, 0.00012, 0.00001, \ + 0.00000, 0.00000, 0.06561, 0.04467, 0.03449, 0.02913, 0.01743, 0.01606, \ + 0.00892, 0.00536, 0.00351, 0.00091, 0.00013, 0.00001, 0.00000, 0.00000, \ + 0.06572, 0.04475, 0.03456, 0.02920, 0.01748, 0.01611, 0.00894, 0.00537, \ + 0.00352, 0.00091, 0.00013, 0.00001, 0.00000, 0.00000, 0.06604, 0.04500, \ + 0.03477, 0.02938, 0.01759, 0.01621, 0.00900, 0.00541, 0.00354, 0.00092, \ + 0.00013, 0.00001, 0.00000, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.03225, 0.03842, 0.04331, 0.04678, 0.05709, 0.05863, 0.06788, 0.07348, \ + 0.07668, 0.08137, 0.08284, 0.08306, 0.08308, 0.08308, 0.04570, 0.05209, \ + 0.05715, 0.06072, 0.07139, 0.07298, 0.08257, 0.08838, 0.09170, 0.09661, \ + 0.09815, 0.09838, 0.09838, 0.09838, 0.04676, 0.05316, 0.05822, 0.06181, \ + 0.07249, 0.07408, 0.08369, 0.08951, 0.09284, 0.09775, 0.09931, 0.09954, \ + 0.09953, 0.09953, 0.07052, 0.07704, 0.08220, 0.08585, 0.09674, 0.09837, \ + 0.10818, 0.11413, 0.11754, 0.12258, 0.12417, 0.12441, 0.12439, 0.12439, \ + 0.07708, 0.08361, 0.08878, 0.09244, 0.10335, 0.10498, 0.11482, 0.12078, \ + 0.12420, 0.12926, 0.13086, 0.13109, 0.13108, 0.13108, 0.11459, 0.12116, \ + 0.12636, 0.13004, 0.14101, 0.14265, 0.15254, 0.15854, 0.16199, 0.16708, \ + 0.16869, 0.16893, 0.16891, 0.16891 "); + } + } + + capacitance () { + top_plane: metal5; + bottom_plane: poly; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.06297, 0.04295, 0.03334, 0.02832, 0.01740, 0.01613, 0.00939, 0.00595, \ + 0.00409, 0.00126, 0.00023, 0.00002, 0.00000, 0.00000, 0.06532, 0.04479, \ + 0.03487, 0.02967, 0.01831, 0.01698, 0.00993, 0.00631, 0.00434, 0.00134, \ + 0.00025, 0.00002, 0.00000, 0.00000, 0.06545, 0.04489, 0.03495, 0.02974, \ + 0.01836, 0.01702, 0.00996, 0.00633, 0.00436, 0.00134, 0.00025, 0.00002, \ + 0.00000, 0.00000, 0.06705, 0.04618, 0.03605, 0.03072, 0.01903, 0.01766, \ + 0.01036, 0.00660, 0.00455, 0.00141, 0.00026, 0.00002, 0.00000, 0.00000, \ + 0.06725, 0.04635, 0.03620, 0.03085, 0.01913, 0.01775, 0.01042, 0.00664, \ + 0.00458, 0.00142, 0.00026, 0.00002, 0.00000, 0.00000, 0.06791, 0.04689, \ + 0.03666, 0.03127, 0.01942, 0.01802, 0.01060, 0.00676, 0.00466, 0.00144, \ + 0.00026, 0.00002, 0.00000, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.03045, 0.03616, 0.04067, 0.04386, 0.05339, 0.05482, 0.06359, 0.06911, \ + 0.07241, 0.07776, 0.07983, 0.08026, 0.08030, 0.08030, 0.04277, 0.04863, \ + 0.05327, 0.05655, 0.06641, 0.06790, 0.07703, 0.08281, 0.08629, 0.09196, \ + 0.09417, 0.09463, 0.09465, 0.09464, 0.04374, 0.04961, 0.05425, 0.05754, \ + 0.06741, 0.06890, 0.07806, 0.08385, 0.08735, 0.09303, 0.09525, 0.09571, \ + 0.09572, 0.09572, 0.06540, 0.07137, 0.07611, 0.07947, 0.08957, 0.09110, \ + 0.10053, 0.10653, 0.11015, 0.11607, 0.11840, 0.11888, 0.11889, 0.11888, \ + 0.07139, 0.07737, 0.08212, 0.08549, 0.09563, 0.09716, 0.10663, 0.11266, \ + 0.11630, 0.12226, 0.12460, 0.12509, 0.12509, 0.12509, 0.10574, 0.11177, \ + 0.11657, 0.11996, 0.13021, 0.13176, 0.14135, 0.14746, 0.15116, 0.15722, \ + 0.15961, 0.16011, 0.16011, 0.16011 "); + } + } + + capacitance () { + top_plane: metal5; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.06334, 0.04339, 0.03384, 0.02887, 0.01805, 0.01679, 0.01010, 0.00663, \ + 0.00471, 0.00163, 0.00036, 0.00004, 0.00000, 0.00000, 0.06588, 0.04542, \ + 0.03557, 0.03041, 0.01914, 0.01782, 0.01079, 0.00711, 0.00507, 0.00177, \ + 0.00039, 0.00005, 0.00000, 0.00000, 0.06602, 0.04554, 0.03566, 0.03049, \ + 0.01920, 0.01788, 0.01083, 0.00714, 0.00509, 0.00178, 0.00040, 0.00005, \ + 0.00000, 0.00000, 0.06794, 0.04713, 0.03705, 0.03175, 0.02012, 0.01874, \ + 0.01142, 0.00755, 0.00540, 0.00189, 0.00042, 0.00005, 0.00000, 0.00000, \ + 0.06822, 0.04738, 0.03726, 0.03194, 0.02026, 0.01888, 0.01151, 0.00762, \ + 0.00545, 0.00191, 0.00043, 0.00005, 0.00000, 0.00000, 0.06919, 0.04821, \ + 0.03800, 0.03261, 0.02075, 0.01935, 0.01183, 0.00785, 0.00562, 0.00198, \ + 0.00044, 0.00005, 0.00000, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.02945, 0.03492, 0.03922, 0.04225, 0.05129, 0.05266, 0.06104, 0.06644, \ + 0.06975, 0.07543, 0.07797, 0.07863, 0.07871, 0.07871, 0.04118, 0.04674, \ + 0.05113, 0.05423, 0.06356, 0.06497, 0.07373, 0.07940, 0.08291, 0.08900, \ + 0.09174, 0.09246, 0.09252, 0.09252, 0.04209, 0.04766, 0.05205, 0.05516, \ + 0.06451, 0.06592, 0.07470, 0.08038, 0.08391, 0.09002, 0.09278, 0.09349, \ + 0.09355, 0.09355, 0.06254, 0.06818, 0.07265, 0.07582, 0.08539, 0.08685, \ + 0.09593, 0.10186, 0.10555, 0.11201, 0.11495, 0.11572, 0.11577, 0.11577, \ + 0.06818, 0.07383, 0.07832, 0.08149, 0.09110, 0.09256, 0.10170, 0.10767, \ + 0.11139, 0.11790, 0.12087, 0.12165, 0.12171, 0.12171, 0.10059, 0.10630, \ + 0.11083, 0.11404, 0.12378, 0.12527, 0.13457, 0.14068, 0.14449, 0.15119, \ + 0.15426, 0.15507, 0.15512, 0.15513 "); + } + } + + capacitance () { + top_plane: metal6; + bottom_plane: metal3; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.05760, 0.03766, 0.02825, 0.02343, 0.01331, 0.01218, 0.00649, 0.00383, \ + 0.00250, 0.00065, 0.00010, 0.00001, 0.00000, 0.00000, 0.05951, 0.03922, \ + 0.02958, 0.02462, 0.01413, 0.01294, 0.00697, 0.00414, 0.00270, 0.00071, \ + 0.00011, 0.00001, 0.00000, 0.00000, 0.05963, 0.03931, 0.02966, 0.02468, \ + 0.01417, 0.01299, 0.00699, 0.00416, 0.00271, 0.00072, 0.00011, 0.00001, \ + 0.00000, 0.00000, 0.06113, 0.04056, 0.03073, 0.02564, 0.01483, 0.01361, \ + 0.00738, 0.00440, 0.00288, 0.00076, 0.00011, 0.00001, 0.00000, 0.00000, \ + 0.06134, 0.04073, 0.03088, 0.02578, 0.01493, 0.01370, 0.00744, 0.00444, \ + 0.00291, 0.00077, 0.00011, 0.00001, 0.00000, 0.00000, 0.06201, 0.04129, \ + 0.03136, 0.02621, 0.01523, 0.01398, 0.00761, 0.00455, 0.00298, 0.00079, \ + 0.00012, 0.00001, 0.00000, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.05752, 0.06681, 0.07342, 0.07784, 0.08944, 0.09104, 0.09973, 0.10457, \ + 0.10723, 0.11081, 0.11192, 0.11206, 0.11235, 0.11234, 0.08406, 0.09340, \ + 0.10009, 0.10459, 0.11650, 0.11816, 0.12726, 0.13238, 0.13521, 0.13908, \ + 0.14029, 0.14046, 0.14072, 0.14071, 0.08611, 0.09546, 0.10215, 0.10665, \ + 0.11859, 0.12024, 0.12937, 0.13450, 0.13735, 0.14124, 0.14245, 0.14262, \ + 0.14288, 0.14287, 0.13152, 0.14095, 0.14773, 0.15230, 0.16451, 0.16621, \ + 0.17567, 0.18104, 0.18402, 0.18814, 0.18945, 0.18963, 0.18988, 0.18987, \ + 0.14396, 0.15341, 0.16020, 0.16478, 0.17704, 0.17874, 0.18825, 0.19365, \ + 0.19666, 0.20082, 0.20213, 0.20232, 0.20257, 0.20257, 0.21499, 0.22449, \ + 0.23133, 0.23595, 0.24833, 0.25007, 0.25972, 0.26523, 0.26830, 0.27256, \ + 0.27391, 0.27410, 0.27436, 0.27435 "); + } + } + + capacitance () { + top_plane: metal6; + bottom_plane: metal2; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.06431, 0.04440, 0.03484, 0.02984, 0.01886, 0.01756, 0.01060, 0.00693, \ + 0.00489, 0.00162, 0.00033, 0.00003, 0.00000, 0.00000, 0.06698, 0.04648, \ + 0.03656, 0.03135, 0.01987, 0.01851, 0.01120, 0.00733, 0.00517, 0.00172, \ + 0.00035, 0.00003, 0.00000, 0.00000, 0.06713, 0.04659, 0.03665, 0.03143, \ + 0.01992, 0.01856, 0.01124, 0.00736, 0.00519, 0.00172, 0.00035, 0.00003, \ + 0.00000, 0.00000, 0.06891, 0.04802, 0.03785, 0.03249, 0.02065, 0.01924, \ + 0.01167, 0.00765, 0.00540, 0.00180, 0.00036, 0.00004, 0.00000, 0.00000, \ + 0.06913, 0.04820, 0.03801, 0.03263, 0.02075, 0.01933, 0.01173, 0.00769, \ + 0.00543, 0.00181, 0.00037, 0.00004, 0.00000, 0.00000, 0.06981, 0.04876, \ + 0.03849, 0.03306, 0.02104, 0.01961, 0.01191, 0.00781, 0.00552, 0.00184, \ + 0.00037, 0.00004, 0.00000, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.02584, 0.03064, 0.03449, 0.03725, 0.04578, 0.04710, 0.05546, 0.06102, \ + 0.06449, 0.07051, 0.07310, 0.07371, 0.07373, 0.07373, 0.03568, 0.04063, \ + 0.04463, 0.04749, 0.05637, 0.05775, 0.06650, 0.07233, 0.07598, 0.08235, \ + 0.08510, 0.08574, 0.08575, 0.08575, 0.03645, 0.04142, 0.04542, 0.04830, \ + 0.05719, 0.05857, 0.06734, 0.07318, 0.07685, 0.08323, 0.08599, 0.08664, \ + 0.08664, 0.08664, 0.05402, 0.05912, 0.06323, 0.06618, 0.07532, 0.07674, \ + 0.08579, 0.09184, 0.09563, 0.10227, 0.10515, 0.10582, 0.10582, 0.10582, \ + 0.05891, 0.06402, 0.06815, 0.07111, 0.08029, 0.08171, 0.09081, 0.09688, \ + 0.10069, 0.10736, 0.11026, 0.11094, 0.11093, 0.11093, 0.08706, 0.09222, \ + 0.09640, 0.09939, 0.10867, 0.11012, 0.11932, 0.12547, 0.12934, 0.13612, \ + 0.13906, 0.13976, 0.13975, 0.13975 "); + } + } + + capacitance () { + top_plane: metal6; + bottom_plane: metal1; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.06624, 0.04659, 0.03719, 0.03228, 0.02144, 0.02014, 0.01303, 0.00907, \ + 0.00674, 0.00263, 0.00067, 0.00009, 0.00000, 0.00000, 0.06957, 0.04924, \ + 0.03942, 0.03425, 0.02278, 0.02140, 0.01385, 0.00963, 0.00716, 0.00279, \ + 0.00071, 0.00010, 0.00000, 0.00000, 0.06976, 0.04939, 0.03954, 0.03436, \ + 0.02285, 0.02147, 0.01389, 0.00967, 0.00718, 0.00280, 0.00071, 0.00010, \ + 0.00000, 0.00000, 0.07218, 0.05133, 0.04118, 0.03581, 0.02384, 0.02240, \ + 0.01449, 0.01008, 0.00749, 0.00292, 0.00074, 0.00010, 0.00000, 0.00000, \ + 0.07249, 0.05159, 0.04140, 0.03600, 0.02398, 0.02253, 0.01458, 0.01014, \ + 0.00753, 0.00294, 0.00075, 0.00010, 0.00000, 0.00000, 0.07342, 0.05234, \ + 0.04204, 0.03657, 0.02437, 0.02290, 0.01481, 0.01030, 0.00765, 0.00299, \ + 0.00076, 0.00010, 0.00000, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.02006, 0.02359, 0.02644, 0.02851, 0.03514, 0.03621, 0.04336, 0.04858, \ + 0.05212, 0.05919, 0.06301, 0.06421, 0.06432, 0.06433, 0.02670, 0.03031, \ + 0.03329, 0.03546, 0.04245, 0.04358, 0.05116, 0.05668, 0.06044, 0.06794, \ + 0.07200, 0.07327, 0.07337, 0.07338, 0.02723, 0.03085, 0.03383, 0.03600, \ + 0.04302, 0.04415, 0.05175, 0.05730, 0.06107, 0.06859, 0.07267, 0.07394, \ + 0.07404, 0.07404, 0.03933, 0.04309, 0.04621, 0.04848, 0.05580, 0.05698, \ + 0.06491, 0.07069, 0.07461, 0.08246, 0.08671, 0.08804, 0.08813, 0.08814, \ + 0.04275, 0.04654, 0.04968, 0.05196, 0.05933, 0.06052, 0.06850, 0.07431, \ + 0.07825, 0.08614, 0.09042, 0.09176, 0.09185, 0.09186, 0.06273, 0.06660, \ + 0.06979, 0.07212, 0.07962, 0.08083, 0.08894, 0.09485, 0.09885, 0.10687, \ + 0.11122, 0.11257, 0.11266, 0.11267 "); + } + } + + capacitance () { + top_plane: metal6; + bottom_plane: poly; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.06699, 0.04744, 0.03814, 0.03329, 0.02261, 0.02133, 0.01427, 0.01026, \ + 0.00785, 0.00338, 0.00099, 0.00016, 0.00001, 0.00000, 0.07061, 0.05039, \ + 0.04065, 0.03553, 0.02418, 0.02281, 0.01526, 0.01097, 0.00839, 0.00361, \ + 0.00105, 0.00017, 0.00001, 0.00000, 0.07082, 0.05056, 0.04079, 0.03566, \ + 0.02427, 0.02289, 0.01532, 0.01101, 0.00842, 0.00362, 0.00106, 0.00017, \ + 0.00001, 0.00000, 0.07366, 0.05288, 0.04278, 0.03743, 0.02551, 0.02407, \ + 0.01610, 0.01157, 0.00884, 0.00380, 0.00111, 0.00018, 0.00001, 0.00000, \ + 0.07406, 0.05322, 0.04307, 0.03769, 0.02570, 0.02425, 0.01622, 0.01165, \ + 0.00890, 0.00383, 0.00112, 0.00018, 0.00001, 0.00000, 0.07530, 0.05424, \ + 0.04395, 0.03848, 0.02625, 0.02476, 0.01656, 0.01189, 0.00909, 0.00391, \ + 0.00114, 0.00019, 0.00001, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.01804, 0.02113, 0.02360, 0.02539, 0.03116, 0.03210, 0.03850, 0.04335, \ + 0.04677, 0.05410, 0.05863, 0.06031, 0.06056, 0.06058, 0.02362, 0.02671, \ + 0.02927, 0.03113, 0.03723, 0.03822, 0.04504, 0.05020, 0.05385, 0.06167, \ + 0.06651, 0.06831, 0.06855, 0.06858, 0.02406, 0.02716, 0.02972, 0.03159, \ + 0.03770, 0.03870, 0.04554, 0.05072, 0.05438, 0.06223, 0.06709, 0.06890, \ + 0.06914, 0.06916, 0.03412, 0.03735, 0.04003, 0.04199, 0.04842, 0.04947, \ + 0.05667, 0.06212, 0.06595, 0.07419, 0.07930, 0.08119, 0.08144, 0.08146, \ + 0.03699, 0.04024, 0.04294, 0.04492, 0.05140, 0.05245, 0.05971, 0.06520, \ + 0.06907, 0.07736, 0.08250, 0.08441, 0.08466, 0.08468, 0.05385, 0.05718, \ + 0.05996, 0.06199, 0.06863, 0.06971, 0.07714, 0.08275, 0.08669, 0.09516, \ + 0.10041, 0.10236, 0.10260, 0.10263 "); + } + } + + capacitance () { + top_plane: metal6; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.06744, 0.04796, 0.03871, 0.03390, 0.02334, 0.02207, 0.01510, 0.01111, \ + 0.00867, 0.00401, 0.00131, 0.00025, 0.00002, 0.00000, 0.07123, 0.05108, \ + 0.04140, 0.03632, 0.02508, 0.02373, 0.01624, 0.01194, 0.00932, 0.00430, \ + 0.00141, 0.00027, 0.00002, 0.00000, 0.07145, 0.05126, 0.04156, 0.03646, \ + 0.02518, 0.02382, 0.01630, 0.01199, 0.00935, 0.00432, 0.00141, 0.00027, \ + 0.00002, 0.00000, 0.07459, 0.05388, 0.04382, 0.03850, 0.02665, 0.02522, \ + 0.01726, 0.01269, 0.00990, 0.00457, 0.00149, 0.00029, 0.00002, 0.00000, \ + 0.07506, 0.05428, 0.04417, 0.03882, 0.02688, 0.02544, 0.01742, 0.01280, \ + 0.00999, 0.00461, 0.00151, 0.00029, 0.00003, 0.00000, 0.07660, 0.05558, \ + 0.04530, 0.03984, 0.02762, 0.02614, 0.01790, 0.01315, 0.01026, 0.00474, \ + 0.00155, 0.00030, 0.00003, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.01687, 0.01972, 0.02198, 0.02361, 0.02886, 0.02971, 0.03559, 0.04013, \ + 0.04338, 0.05072, 0.05571, 0.05784, 0.05825, 0.05830, 0.02189, 0.02469, \ + 0.02700, 0.02868, 0.03419, 0.03510, 0.04136, 0.04620, 0.04970, 0.05756, \ + 0.06293, 0.06521, 0.06564, 0.06568, 0.02228, 0.02508, 0.02739, 0.02908, \ + 0.03461, 0.03552, 0.04181, 0.04667, 0.05018, 0.05807, 0.06345, 0.06575, \ + 0.06618, 0.06622, 0.03117, 0.03407, 0.03648, 0.03825, 0.04408, 0.04504, \ + 0.05168, 0.05682, 0.06053, 0.06887, 0.07457, 0.07700, 0.07744, 0.07749, \ + 0.03370, 0.03663, 0.03906, 0.04084, 0.04672, 0.04768, 0.05439, 0.05958, \ + 0.06332, 0.07174, 0.07748, 0.07994, 0.08038, 0.08043, 0.04867, 0.05167, \ + 0.05418, 0.05602, 0.06208, 0.06307, 0.06997, 0.07531, 0.07915, 0.08779, \ + 0.09369, 0.09621, 0.09666, 0.09672 "); + } + } + + capacitance () { + top_plane: metal7; + bottom_plane: metal3; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.05824, 0.03844, 0.02914, 0.02439, 0.01446, 0.01335, 0.00772, 0.00498, \ + 0.00353, 0.00127, 0.00031, 0.00004, 0.00000, 0.00000, 0.06052, 0.04039, \ + 0.03086, 0.02597, 0.01566, 0.01449, 0.00851, 0.00556, 0.00397, 0.00144, \ + 0.00036, 0.00005, 0.00000, 0.00000, 0.06067, 0.04051, 0.03097, 0.02607, \ + 0.01573, 0.01456, 0.00856, 0.00559, 0.00399, 0.00145, 0.00036, 0.00005, \ + 0.00000, 0.00000, 0.06283, 0.04239, 0.03266, 0.02763, 0.01694, 0.01571, \ + 0.00938, 0.00619, 0.00445, 0.00164, 0.00041, 0.00006, 0.00000, 0.00000, \ + 0.06320, 0.04273, 0.03296, 0.02792, 0.01716, 0.01593, 0.00954, 0.00631, \ + 0.00454, 0.00168, 0.00042, 0.00006, 0.00000, 0.00000, 0.06463, 0.04400, \ + 0.03411, 0.02899, 0.01799, 0.01672, 0.01011, 0.00673, 0.00486, 0.00182, \ + 0.00046, 0.00006, 0.00000, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.05577, 0.06461, 0.07083, 0.07497, 0.08577, 0.08725, 0.09545, 0.10021, \ + 0.10296, 0.10724, 0.10911, 0.10963, 0.10998, 0.10998, 0.08117, 0.08996, \ + 0.09618, 0.10035, 0.11137, 0.11291, 0.12152, 0.12660, 0.12959, 0.13434, \ + 0.13648, 0.13709, 0.13743, 0.13743, 0.08313, 0.09191, 0.09813, 0.10231, \ + 0.11335, 0.11489, 0.12352, 0.12862, 0.13163, 0.13641, 0.13857, 0.13918, \ + 0.13951, 0.13951, 0.12618, 0.13497, 0.14123, 0.14545, 0.15673, 0.15832, \ + 0.16736, 0.17280, 0.17605, 0.18133, 0.18376, 0.18446, 0.18480, 0.18480, \ + 0.13795, 0.14674, 0.15301, 0.15724, 0.16857, 0.17017, 0.17928, 0.18479, \ + 0.18808, 0.19345, 0.19594, 0.19666, 0.19700, 0.19700, 0.20507, 0.21390, \ + 0.22022, 0.22449, 0.23602, 0.23765, 0.24705, 0.25279, 0.25625, 0.26197, \ + 0.26466, 0.26544, 0.26579, 0.26579 "); + } + } + + capacitance () { + top_plane: metal7; + bottom_plane: metal2; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.06507, 0.04528, 0.03583, 0.03092, 0.02018, 0.01891, 0.01210, 0.00843, \ + 0.00632, 0.00262, 0.00077, 0.00013, 0.00001, 0.00000, 0.06808, 0.04774, \ + 0.03794, 0.03281, 0.02156, 0.02023, 0.01303, 0.00912, 0.00686, 0.00287, \ + 0.00085, 0.00015, 0.00001, 0.00000, 0.06826, 0.04788, 0.03806, 0.03292, \ + 0.02164, 0.02031, 0.01309, 0.00917, 0.00689, 0.00288, 0.00085, 0.00015, \ + 0.00001, 0.00000, 0.07068, 0.04993, 0.03987, 0.03457, 0.02290, 0.02150, \ + 0.01396, 0.00982, 0.00741, 0.00312, 0.00093, 0.00016, 0.00001, 0.00000, \ + 0.07106, 0.05026, 0.04017, 0.03485, 0.02312, 0.02172, 0.01411, 0.00994, \ + 0.00750, 0.00317, 0.00094, 0.00016, 0.00001, 0.00000, 0.07248, 0.05151, \ + 0.04129, 0.03589, 0.02393, 0.02249, 0.01469, 0.01037, 0.00785, 0.00333, \ + 0.00099, 0.00017, 0.00001, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.02385, 0.02821, 0.03166, 0.03412, 0.04166, 0.04283, 0.05030, 0.05543, \ + 0.05877, 0.06522, 0.06880, 0.07010, 0.07032, 0.07034, 0.03260, 0.03698, \ + 0.04050, 0.04301, 0.05080, 0.05201, 0.05983, 0.06523, 0.06879, 0.07572, \ + 0.07964, 0.08107, 0.08128, 0.08130, 0.03328, 0.03767, 0.04119, 0.04371, \ + 0.05150, 0.05272, 0.06055, 0.06597, 0.06955, 0.07651, 0.08044, 0.08188, \ + 0.08210, 0.08212, 0.04853, 0.05297, 0.05655, 0.05912, 0.06711, 0.06836, \ + 0.07650, 0.08218, 0.08594, 0.09337, 0.09763, 0.09919, 0.09942, 0.09944, \ + 0.05275, 0.05720, 0.06079, 0.06336, 0.07139, 0.07265, 0.08084, 0.08657, \ + 0.09036, 0.09788, 0.10219, 0.10378, 0.10401, 0.10403, 0.07705, 0.08154, \ + 0.08517, 0.08778, 0.09595, 0.09723, 0.10561, 0.11151, 0.11544, 0.12326, \ + 0.12779, 0.12947, 0.12971, 0.12974 "); + } + } + + capacitance () { + top_plane: metal7; + bottom_plane: metal1; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.06709, 0.04755, 0.03826, 0.03344, 0.02284, 0.02158, 0.01466, 0.01074, \ + 0.00838, 0.00391, 0.00133, 0.00028, 0.00003, 0.00000, 0.07074, 0.05056, \ + 0.04086, 0.03578, 0.02455, 0.02321, 0.01580, 0.01160, 0.00905, 0.00423, \ + 0.00144, 0.00030, 0.00003, 0.00000, 0.07095, 0.05074, 0.04101, 0.03591, \ + 0.02465, 0.02330, 0.01587, 0.01165, 0.00909, 0.00425, 0.00145, 0.00030, \ + 0.00003, 0.00000, 0.07400, 0.05329, 0.04324, 0.03794, 0.02616, 0.02474, \ + 0.01690, 0.01242, 0.00971, 0.00456, 0.00156, 0.00033, 0.00003, 0.00000, \ + 0.07446, 0.05370, 0.04360, 0.03827, 0.02641, 0.02498, 0.01707, 0.01256, \ + 0.00982, 0.00461, 0.00158, 0.00033, 0.00003, 0.00000, 0.07611, 0.05512, \ + 0.04487, 0.03943, 0.02730, 0.02583, 0.01769, 0.01303, 0.01020, 0.00480, \ + 0.00164, 0.00035, 0.00003, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.01787, 0.02097, 0.02343, 0.02519, 0.03081, 0.03171, 0.03783, 0.04243, \ + 0.04568, 0.05281, 0.05759, 0.05971, 0.06016, 0.06022, 0.02348, 0.02652, \ + 0.02902, 0.03083, 0.03668, 0.03763, 0.04411, 0.04900, 0.05247, 0.06013, \ + 0.06531, 0.06760, 0.06807, 0.06813, 0.02391, 0.02696, 0.02945, 0.03127, \ + 0.03714, 0.03809, 0.04459, 0.04950, 0.05299, 0.06067, 0.06588, 0.06818, \ + 0.06865, 0.06871, 0.03373, 0.03685, 0.03943, 0.04131, 0.04742, 0.04842, \ + 0.05523, 0.06041, 0.06409, 0.07226, 0.07782, 0.08030, 0.08080, 0.08086, \ + 0.03650, 0.03963, 0.04222, 0.04411, 0.05027, 0.05127, 0.05815, 0.06337, \ + 0.06709, 0.07533, 0.08096, 0.08347, 0.08398, 0.08404, 0.05267, 0.05586, \ + 0.05851, 0.06045, 0.06676, 0.06779, 0.07486, 0.08024, 0.08407, 0.09261, \ + 0.09846, 0.10108, 0.10161, 0.10168 "); + } + } + + capacitance () { + top_plane: metal7; + bottom_plane: poly; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.06789, 0.04847, 0.03927, 0.03450, 0.02406, 0.02282, 0.01596, 0.01203, \ + 0.00960, 0.00481, 0.00180, 0.00043, 0.00005, 0.00000, 0.07182, 0.05175, \ + 0.04213, 0.03710, 0.02599, 0.02466, 0.01728, 0.01302, 0.01039, 0.00521, \ + 0.00195, 0.00047, 0.00006, 0.00000, 0.07206, 0.05195, 0.04230, 0.03726, \ + 0.02611, 0.02477, 0.01736, 0.01308, 0.01044, 0.00524, 0.00196, 0.00047, \ + 0.00006, 0.00000, 0.07551, 0.05487, 0.04487, 0.03960, 0.02786, 0.02644, \ + 0.01856, 0.01399, 0.01117, 0.00561, 0.00210, 0.00050, 0.00006, 0.00000, \ + 0.07607, 0.05535, 0.04530, 0.03999, 0.02816, 0.02673, 0.01877, 0.01415, \ + 0.01130, 0.00568, 0.00213, 0.00051, 0.00006, 0.00000, 0.07801, 0.05703, \ + 0.04679, 0.04136, 0.02920, 0.02772, 0.01949, 0.01470, 0.01175, 0.00591, \ + 0.00222, 0.00053, 0.00006, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.01570, 0.01836, 0.02045, 0.02194, 0.02670, 0.02747, 0.03278, 0.03693, \ + 0.03997, 0.04712, 0.05250, 0.05522, 0.05593, 0.05603, 0.02029, 0.02282, \ + 0.02489, 0.02640, 0.03135, 0.03216, 0.03781, 0.04224, 0.04551, 0.05321, \ + 0.05903, 0.06197, 0.06273, 0.06284, 0.02063, 0.02316, 0.02524, 0.02675, \ + 0.03171, 0.03253, 0.03819, 0.04265, 0.04593, 0.05366, 0.05951, 0.06247, \ + 0.06322, 0.06334, 0.02845, 0.03103, 0.03318, 0.03475, 0.03995, 0.04081, \ + 0.04681, 0.05155, 0.05503, 0.06327, 0.06954, 0.07271, 0.07351, 0.07363, \ + 0.03067, 0.03326, 0.03542, 0.03701, 0.04226, 0.04312, 0.04919, 0.05397, \ + 0.05750, 0.06583, 0.07216, 0.07536, 0.07618, 0.07630, 0.04375, 0.04642, \ + 0.04865, 0.05028, 0.05570, 0.05660, 0.06288, 0.06784, 0.07149, 0.08013, \ + 0.08671, 0.09005, 0.09089, 0.09102 "); + } + } + + capacitance () { + top_plane: metal7; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.06839, 0.04903, 0.03989, 0.03516, 0.02484, 0.02361, 0.01684, 0.01293, \ + 0.01050, 0.00555, 0.00225, 0.00060, 0.00008, 0.00000, 0.07248, 0.05249, \ + 0.04292, 0.03793, 0.02693, 0.02561, 0.01830, 0.01405, 0.01140, 0.00603, \ + 0.00244, 0.00065, 0.00009, 0.00000, 0.07273, 0.05269, 0.04311, 0.03810, \ + 0.02706, 0.02574, 0.01839, 0.01412, 0.01145, 0.00606, 0.00245, 0.00065, \ + 0.00009, 0.00000, 0.07647, 0.05589, 0.04594, 0.04069, 0.02903, 0.02762, \ + 0.01976, 0.01517, 0.01231, 0.00651, 0.00263, 0.00070, 0.00010, 0.00000, \ + 0.07709, 0.05644, 0.04643, 0.04114, 0.02937, 0.02795, 0.02001, 0.01536, \ + 0.01246, 0.00659, 0.00267, 0.00071, 0.00010, 0.00000, 0.07933, 0.05838, \ + 0.04816, 0.04274, 0.03059, 0.02911, 0.02086, 0.01602, 0.01299, 0.00687, \ + 0.00278, 0.00074, 0.00010, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.01440, 0.01683, 0.01872, 0.02005, 0.02429, 0.02497, 0.02973, 0.03352, \ + 0.03634, 0.04332, 0.04903, 0.05224, 0.05323, 0.05340, 0.01846, 0.02070, \ + 0.02253, 0.02386, 0.02822, 0.02894, 0.03400, 0.03805, 0.04111, 0.04864, \ + 0.05484, 0.05832, 0.05937, 0.05956, 0.01876, 0.02100, 0.02283, 0.02416, \ + 0.02853, 0.02925, 0.03433, 0.03840, 0.04147, 0.04903, 0.05526, 0.05876, \ + 0.05982, 0.06001, 0.02544, 0.02769, 0.02957, 0.03095, 0.03554, 0.03630, \ + 0.04171, 0.04607, 0.04935, 0.05745, 0.06413, 0.06789, 0.06902, 0.06922, \ + 0.02733, 0.02959, 0.03148, 0.03287, 0.03751, 0.03828, 0.04375, 0.04816, \ + 0.05148, 0.05968, 0.06645, 0.07025, 0.07139, 0.07160, 0.03854, 0.04088, \ + 0.04283, 0.04428, 0.04910, 0.04991, 0.05561, 0.06021, 0.06367, 0.07221, \ + 0.07925, 0.08322, 0.08441, 0.08462 "); + } + } + + capacitance () { + top_plane: metal8; + bottom_plane: metal3; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.05873, 0.03898, 0.02973, 0.02503, 0.01523, 0.01414, 0.00860, 0.00590, \ + 0.00444, 0.00203, 0.00079, 0.00024, 0.00004, 0.00000, 0.06117, 0.04112, \ + 0.03168, 0.02685, 0.01670, 0.01556, 0.00970, 0.00677, 0.00515, 0.00242, \ + 0.00096, 0.00029, 0.00006, 0.00000, 0.06133, 0.04126, 0.03181, 0.02697, \ + 0.01680, 0.01565, 0.00977, 0.00683, 0.00520, 0.00245, 0.00097, 0.00030, \ + 0.00006, 0.00000, 0.06394, 0.04362, 0.03399, 0.02903, 0.01852, 0.01732, \ + 0.01109, 0.00789, 0.00610, 0.00296, 0.00121, 0.00037, 0.00007, 0.00000, \ + 0.06445, 0.04410, 0.03444, 0.02946, 0.01888, 0.01768, 0.01138, 0.00813, \ + 0.00630, 0.00308, 0.00126, 0.00039, 0.00007, 0.00000, 0.06670, 0.04618, \ + 0.03640, 0.03133, 0.02049, 0.01924, 0.01265, 0.00919, 0.00720, 0.00362, \ + 0.00152, 0.00048, 0.00009, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.05450, 0.06316, 0.06920, 0.07320, 0.08352, 0.08494, 0.09271, 0.09725, \ + 0.09993, 0.10434, 0.10673, 0.10781, 0.10847, 0.10855, 0.07943, 0.08791, \ + 0.09386, 0.09783, 0.10823, 0.10968, 0.11776, 0.12260, 0.12552, 0.13049, \ + 0.13330, 0.13462, 0.13534, 0.13545, 0.08134, 0.08980, 0.09575, 0.09972, \ + 0.11013, 0.11158, 0.11968, 0.12454, 0.12748, 0.13248, 0.13532, 0.13666, \ + 0.13738, 0.13749, 0.12301, 0.13137, 0.13728, 0.14124, 0.15176, 0.15325, \ + 0.16169, 0.16689, 0.17008, 0.17576, 0.17913, 0.18078, 0.18162, 0.18176, \ + 0.13434, 0.14268, 0.14858, 0.15254, 0.16309, 0.16457, 0.17309, 0.17836, \ + 0.18161, 0.18742, 0.19092, 0.19264, 0.19351, 0.19366, 0.19864, 0.20694, \ + 0.21284, 0.21681, 0.22748, 0.22900, 0.23781, 0.24337, 0.24686, 0.25330, \ + 0.25735, 0.25941, 0.26041, 0.26060 "); + } + } + + capacitance () { + top_plane: metal8; + bottom_plane: metal2; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.06569, 0.04596, 0.03656, 0.03169, 0.02111, 0.01987, 0.01324, 0.00967, \ + 0.00760, 0.00382, 0.00162, 0.00053, 0.00011, 0.00000, 0.06885, 0.04860, \ + 0.03888, 0.03382, 0.02278, 0.02148, 0.01448, 0.01068, 0.00844, 0.00432, \ + 0.00185, 0.00061, 0.00013, 0.00000, 0.06903, 0.04875, 0.03903, 0.03395, \ + 0.02288, 0.02158, 0.01456, 0.01074, 0.00849, 0.00435, 0.00187, 0.00061, \ + 0.00013, 0.00000, 0.07191, 0.05128, 0.04132, 0.03610, 0.02466, 0.02330, \ + 0.01594, 0.01189, 0.00948, 0.00496, 0.00216, 0.00072, 0.00015, 0.00000, \ + 0.07242, 0.05176, 0.04177, 0.03653, 0.02502, 0.02365, 0.01623, 0.01213, \ + 0.00969, 0.00509, 0.00223, 0.00075, 0.00016, 0.00000, 0.07465, 0.05381, \ + 0.04369, 0.03836, 0.02659, 0.02519, 0.01751, 0.01321, 0.01063, 0.00569, \ + 0.00254, 0.00086, 0.00018, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.02227, 0.02644, 0.02971, 0.03202, 0.03899, 0.04006, 0.04685, 0.05150, \ + 0.05457, 0.06079, 0.06488, 0.06703, 0.06783, 0.06806, 0.03059, 0.03466, \ + 0.03789, 0.04019, 0.04723, 0.04832, 0.05532, 0.06019, 0.06345, 0.07018, \ + 0.07473, 0.07718, 0.07809, 0.07835, 0.03123, 0.03529, 0.03852, 0.04082, \ + 0.04786, 0.04895, 0.05596, 0.06084, 0.06412, 0.07088, 0.07546, 0.07793, \ + 0.07885, 0.07911, 0.04512, 0.04912, 0.05232, 0.05461, 0.06170, 0.06280, \ + 0.07001, 0.07511, 0.07857, 0.08589, 0.09102, 0.09386, 0.09493, 0.09524, \ + 0.04890, 0.05288, 0.05608, 0.05837, 0.06546, 0.06657, 0.07382, 0.07896, \ + 0.08246, 0.08989, 0.09514, 0.09806, 0.09917, 0.09950, 0.07039, 0.07435, \ + 0.07754, 0.07982, 0.08697, 0.08810, 0.09550, 0.10083, 0.10450, 0.11243, \ + 0.11819, 0.12150, 0.12278, 0.12316 "); + } + } + + capacitance () { + top_plane: metal8; + bottom_plane: metal1; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.06782, 0.04834, 0.03911, 0.03432, 0.02389, 0.02266, 0.01593, 0.01216, \ + 0.00987, 0.00540, 0.00248, 0.00087, 0.00020, 0.00000, 0.07160, 0.05151, \ + 0.04190, 0.03688, 0.02587, 0.02456, 0.01739, 0.01333, 0.01086, 0.00600, \ + 0.00278, 0.00099, 0.00023, 0.00000, 0.07183, 0.05171, 0.04207, 0.03704, \ + 0.02599, 0.02468, 0.01748, 0.01341, 0.01092, 0.00604, 0.00280, 0.00100, \ + 0.00023, 0.00000, 0.07530, 0.05472, 0.04478, 0.03955, 0.02802, 0.02663, \ + 0.01902, 0.01468, 0.01202, 0.00673, 0.00316, 0.00113, 0.00027, 0.00000, \ + 0.07591, 0.05527, 0.04528, 0.04003, 0.02841, 0.02702, 0.01933, 0.01494, \ + 0.01224, 0.00688, 0.00324, 0.00117, 0.00027, 0.00000, 0.07836, 0.05749, \ + 0.04734, 0.04198, 0.03005, 0.02861, 0.02065, 0.01606, 0.01322, 0.00752, \ + 0.00358, 0.00130, 0.00031, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.01602, 0.01892, 0.02120, 0.02282, 0.02787, 0.02866, 0.03401, 0.03801, \ + 0.04085, 0.04738, 0.05246, 0.05554, 0.05682, 0.05724, 0.02125, 0.02398, \ + 0.02619, 0.02778, 0.03286, 0.03368, 0.03922, 0.04343, 0.04646, 0.05348, \ + 0.05905, 0.06248, 0.06392, 0.06439, 0.02163, 0.02436, 0.02657, 0.02816, \ + 0.03325, 0.03407, 0.03962, 0.04384, 0.04688, 0.05394, 0.05954, 0.06299, \ + 0.06444, 0.06491, 0.03014, 0.03282, 0.03501, 0.03661, 0.04177, 0.04261, \ + 0.04837, 0.05279, 0.05600, 0.06356, 0.06970, 0.07356, 0.07521, 0.07575, \ + 0.03247, 0.03514, 0.03734, 0.03893, 0.04411, 0.04495, 0.05075, 0.05521, \ + 0.05845, 0.06611, 0.07236, 0.07632, 0.07800, 0.07857, 0.04586, 0.04852, \ + 0.05073, 0.05233, 0.05757, 0.05843, 0.06436, 0.06897, 0.07235, 0.08044, \ + 0.08717, 0.09152, 0.09340, 0.09404 "); + } + } + + capacitance () { + top_plane: metal8; + bottom_plane: poly; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.06871, 0.04935, 0.04019, 0.03547, 0.02519, 0.02397, 0.01732, 0.01354, \ + 0.01121, 0.00648, 0.00316, 0.00119, 0.00030, 0.00000, 0.07276, 0.05278, \ + 0.04324, 0.03827, 0.02738, 0.02609, 0.01895, 0.01486, 0.01232, 0.00716, \ + 0.00351, 0.00133, 0.00033, 0.00000, 0.07300, 0.05299, 0.04343, 0.03845, \ + 0.02752, 0.02622, 0.01905, 0.01494, 0.01239, 0.00721, 0.00353, 0.00134, \ + 0.00034, 0.00000, 0.07687, 0.05636, 0.04647, 0.04127, 0.02978, 0.02840, \ + 0.02077, 0.01635, 0.01360, 0.00798, 0.00394, 0.00151, 0.00038, 0.00000, \ + 0.07756, 0.05698, 0.04704, 0.04180, 0.03022, 0.02883, 0.02111, 0.01663, \ + 0.01385, 0.00814, 0.00403, 0.00154, 0.00039, 0.00000, 0.08030, 0.05945, \ + 0.04931, 0.04395, 0.03200, 0.03056, 0.02252, 0.01782, 0.01488, 0.00882, \ + 0.00441, 0.00170, 0.00043, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.01366, 0.01611, 0.01803, 0.01937, 0.02357, 0.02423, 0.02874, 0.03224, \ + 0.03481, 0.04112, 0.04658, 0.05026, 0.05197, 0.05258, 0.01788, 0.02011, \ + 0.02190, 0.02319, 0.02736, 0.02804, 0.03272, 0.03640, 0.03915, 0.04595, \ + 0.05192, 0.05598, 0.05787, 0.05856, 0.01819, 0.02040, 0.02219, 0.02348, \ + 0.02765, 0.02833, 0.03302, 0.03671, 0.03948, 0.04630, 0.05231, 0.05640, \ + 0.05830, 0.05899, 0.02473, 0.02687, 0.02864, 0.02992, 0.03416, 0.03486, \ + 0.03975, 0.04365, 0.04657, 0.05391, 0.06045, 0.06498, 0.06712, 0.06790, \ + 0.02651, 0.02865, 0.03041, 0.03171, 0.03596, 0.03666, 0.04159, 0.04553, \ + 0.04849, 0.05592, 0.06258, 0.06720, 0.06939, 0.07019, 0.03684, 0.03898, \ + 0.04076, 0.04207, 0.04640, 0.04712, 0.05220, 0.05629, 0.05938, 0.06722, \ + 0.07434, 0.07937, 0.08178, 0.08267 "); + } + } + + capacitance () { + top_plane: metal8; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.06928, 0.04998, 0.04089, 0.03620, 0.02603, 0.02483, 0.01827, 0.01453, \ + 0.01220, 0.00735, 0.00378, 0.00151, 0.00041, 0.00000, 0.07348, 0.05358, \ + 0.04410, 0.03917, 0.02838, 0.02710, 0.02004, 0.01596, 0.01341, 0.00812, \ + 0.00418, 0.00167, 0.00045, 0.00000, 0.07374, 0.05380, 0.04430, 0.03935, \ + 0.02853, 0.02724, 0.02015, 0.01606, 0.01349, 0.00817, 0.00421, 0.00168, \ + 0.00046, 0.00000, 0.07788, 0.05743, 0.04758, 0.04241, 0.03100, 0.02963, \ + 0.02203, 0.01760, 0.01482, 0.00902, 0.00467, 0.00188, 0.00051, 0.00000, \ + 0.07864, 0.05812, 0.04821, 0.04300, 0.03148, 0.03010, 0.02240, 0.01791, \ + 0.01509, 0.00919, 0.00477, 0.00192, 0.00052, 0.00000, 0.08166, 0.06084, \ + 0.05071, 0.04536, 0.03344, 0.03199, 0.02394, 0.01920, 0.01621, 0.00994, \ + 0.00519, 0.00211, 0.00057, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.01219, 0.01440, 0.01611, 0.01730, 0.02098, 0.02156, 0.02551, 0.02861, \ + 0.03093, 0.03690, 0.04249, 0.04661, 0.04871, 0.04954, 0.01590, 0.01783, \ + 0.01938, 0.02050, 0.02409, 0.02467, 0.02874, 0.03200, 0.03450, 0.04093, \ + 0.04704, 0.05158, 0.05389, 0.05482, 0.01616, 0.01808, 0.01963, 0.02074, \ + 0.02432, 0.02491, 0.02899, 0.03226, 0.03477, 0.04123, 0.04737, 0.05194, \ + 0.05427, 0.05520, 0.02160, 0.02341, 0.02491, 0.02600, 0.02962, 0.03023, \ + 0.03449, 0.03796, 0.04063, 0.04760, 0.05429, 0.05933, 0.06192, 0.06297, \ + 0.02306, 0.02486, 0.02636, 0.02746, 0.03110, 0.03170, 0.03600, 0.03952, \ + 0.04222, 0.04929, 0.05609, 0.06122, 0.06388, 0.06495, 0.03154, 0.03335, \ + 0.03486, 0.03598, 0.03971, 0.04033, 0.04479, 0.04847, 0.05130, 0.05877, \ + 0.06605, 0.07159, 0.07449, 0.07567 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: metal3; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.05920, 0.03948, 0.03025, 0.02556, 0.01579, 0.01470, 0.00917, 0.00646, \ + 0.00500, 0.00255, 0.00124, 0.00058, 0.00027, 0.00000, 0.06170, 0.04169, \ + 0.03227, 0.02746, 0.01737, 0.01623, 0.01040, 0.00748, 0.00587, 0.00310, \ + 0.00155, 0.00075, 0.00036, 0.00000, 0.06186, 0.04184, 0.03241, 0.02759, \ + 0.01747, 0.01634, 0.01049, 0.00755, 0.00593, 0.00314, 0.00158, 0.00076, \ + 0.00036, 0.00000, 0.06463, 0.04436, 0.03477, 0.02984, 0.01942, 0.01823, \ + 0.01206, 0.00890, 0.00711, 0.00393, 0.00206, 0.00104, 0.00051, 0.00000, \ + 0.06519, 0.04490, 0.03528, 0.03033, 0.01985, 0.01866, 0.01243, 0.00921, \ + 0.00739, 0.00413, 0.00219, 0.00111, 0.00055, 0.00000, 0.06782, 0.04738, \ + 0.03765, 0.03262, 0.02190, 0.02066, 0.01417, 0.01075, 0.00877, 0.00514, \ + 0.00286, 0.00152, 0.00079, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.05329, 0.06183, 0.06779, 0.07174, 0.08196, 0.08336, 0.09109, 0.09563, \ + 0.09831, 0.10279, 0.10531, 0.10659, 0.10748, 0.10803, 0.07806, 0.08641, \ + 0.09226, 0.09617, 0.10639, 0.10781, 0.11576, 0.12054, 0.12344, 0.12845, \ + 0.13141, 0.13297, 0.13401, 0.13473, 0.07994, 0.08829, 0.09414, 0.09804, \ + 0.10826, 0.10968, 0.11765, 0.12245, 0.12536, 0.13040, 0.13339, 0.13498, \ + 0.13602, 0.13675, 0.12121, 0.12940, 0.13517, 0.13904, 0.14927, 0.15071, \ + 0.15891, 0.16397, 0.16711, 0.17277, 0.17633, 0.17832, 0.17961, 0.18064, \ + 0.13239, 0.14055, 0.14630, 0.15016, 0.16039, 0.16183, 0.17008, 0.17520, \ + 0.17838, 0.18418, 0.18786, 0.18996, 0.19131, 0.19243, 0.19560, 0.20368, \ + 0.20938, 0.21321, 0.22346, 0.22492, 0.23335, 0.23871, 0.24209, 0.24847, \ + 0.25276, 0.25536, 0.25705, 0.25864 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: metal2; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.06633, 0.04665, 0.03728, 0.03242, 0.02189, 0.02066, 0.01406, 0.01051, \ + 0.00845, 0.00468, 0.00241, 0.00117, 0.00056, 0.00000, 0.06955, 0.04934, \ + 0.03966, 0.03462, 0.02365, 0.02236, 0.01544, 0.01168, 0.00947, 0.00537, \ + 0.00283, 0.00141, 0.00068, 0.00000, 0.06974, 0.04950, 0.03981, 0.03476, \ + 0.02376, 0.02247, 0.01553, 0.01175, 0.00953, 0.00542, 0.00286, 0.00143, \ + 0.00069, 0.00000, 0.07276, 0.05219, 0.04228, 0.03709, 0.02576, 0.02441, \ + 0.01717, 0.01319, 0.01082, 0.00635, 0.00347, 0.00179, 0.00090, 0.00000, \ + 0.07333, 0.05272, 0.04278, 0.03758, 0.02619, 0.02484, 0.01754, 0.01352, \ + 0.01112, 0.00657, 0.00362, 0.00189, 0.00095, 0.00000, 0.07594, 0.05516, \ + 0.04511, 0.03983, 0.02821, 0.02682, 0.01930, 0.01510, 0.01258, 0.00769, \ + 0.00441, 0.00240, 0.00125, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.02066, 0.02468, 0.02785, 0.03009, 0.03690, 0.03794, 0.04457, 0.04912, \ + 0.05212, 0.05824, 0.06237, 0.06477, 0.06596, 0.06708, 0.02882, 0.03275, \ + 0.03587, 0.03809, 0.04487, 0.04592, 0.05266, 0.05734, 0.06049, 0.06701, \ + 0.07159, 0.07433, 0.07571, 0.07709, 0.02944, 0.03336, 0.03648, 0.03870, \ + 0.04548, 0.04653, 0.05327, 0.05796, 0.06112, 0.06767, 0.07228, 0.07503, \ + 0.07643, 0.07783, 0.04294, 0.04676, 0.04981, 0.05199, 0.05871, 0.05976, \ + 0.06656, 0.07137, 0.07464, 0.08163, 0.08675, 0.08995, 0.09165, 0.09345, \ + 0.04657, 0.05037, 0.05341, 0.05558, 0.06228, 0.06332, 0.07013, 0.07497, \ + 0.07826, 0.08534, 0.09057, 0.09388, 0.09565, 0.09756, 0.06699, 0.07070, \ + 0.07368, 0.07582, 0.08245, 0.08349, 0.09033, 0.09526, 0.09865, 0.10611, \ + 0.11185, 0.11565, 0.11782, 0.12032 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: metal1; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.06861, 0.04919, 0.03999, 0.03522, 0.02484, 0.02362, 0.01694, 0.01320, \ + 0.01095, 0.00652, 0.00358, 0.00182, 0.00088, 0.00000, 0.07245, 0.05242, \ + 0.04284, 0.03784, 0.02691, 0.02562, 0.01853, 0.01454, 0.01211, 0.00734, \ + 0.00409, 0.00212, 0.00105, 0.00000, 0.07269, 0.05261, 0.04301, 0.03801, \ + 0.02704, 0.02574, 0.01863, 0.01463, 0.01219, 0.00739, 0.00413, 0.00215, \ + 0.00106, 0.00000, 0.07630, 0.05578, 0.04588, 0.04069, 0.02927, 0.02791, \ + 0.02043, 0.01619, 0.01359, 0.00843, 0.00484, 0.00259, 0.00132, 0.00000, \ + 0.07696, 0.05638, 0.04645, 0.04123, 0.02974, 0.02836, 0.02082, 0.01653, \ + 0.01391, 0.00867, 0.00501, 0.00270, 0.00138, 0.00000, 0.07978, 0.05899, \ + 0.04890, 0.04359, 0.03182, 0.03041, 0.02262, 0.01816, 0.01541, 0.00986, \ + 0.00588, 0.00329, 0.00174, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.01405, 0.01677, 0.01894, 0.02048, 0.02533, 0.02610, 0.03125, 0.03508, \ + 0.03780, 0.04405, 0.04900, 0.05227, 0.05403, 0.05580, 0.01911, 0.02169, \ + 0.02378, 0.02529, 0.03010, 0.03087, 0.03610, 0.04005, 0.04289, 0.04949, \ + 0.05486, 0.05849, 0.06049, 0.06259, 0.01949, 0.02206, 0.02415, 0.02565, \ + 0.03046, 0.03124, 0.03647, 0.04042, 0.04327, 0.04989, 0.05529, 0.05895, \ + 0.06096, 0.06309, 0.02762, 0.03012, 0.03216, 0.03364, 0.03841, 0.03918, \ + 0.04446, 0.04850, 0.05144, 0.05840, 0.06425, 0.06834, 0.07069, 0.07332, \ + 0.02981, 0.03229, 0.03432, 0.03580, 0.04055, 0.04132, 0.04661, 0.05067, \ + 0.05361, 0.06063, 0.06658, 0.07077, 0.07320, 0.07596, 0.04214, 0.04456, \ + 0.04654, 0.04799, 0.05269, 0.05345, 0.05873, 0.06283, 0.06584, 0.07311, \ + 0.07945, 0.08411, 0.08695, 0.09041 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: poly; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.06960, 0.05031, 0.04120, 0.03650, 0.02628, 0.02507, 0.01847, 0.01473, \ + 0.01243, 0.00778, 0.00448, 0.00236, 0.00118, 0.00000, 0.07373, 0.05381, \ + 0.04431, 0.03936, 0.02855, 0.02727, 0.02023, 0.01621, 0.01372, 0.00869, \ + 0.00506, 0.00272, 0.00138, 0.00000, 0.07398, 0.05402, 0.04450, 0.03954, \ + 0.02870, 0.02741, 0.02034, 0.01630, 0.01381, 0.00875, 0.00510, 0.00275, \ + 0.00139, 0.00000, 0.07798, 0.05753, 0.04769, 0.04252, 0.03116, 0.02980, \ + 0.02230, 0.01800, 0.01533, 0.00988, 0.00589, 0.00325, 0.00169, 0.00000, \ + 0.07872, 0.05820, 0.04831, 0.04312, 0.03166, 0.03029, 0.02272, 0.01837, \ + 0.01566, 0.01013, 0.00607, 0.00337, 0.00176, 0.00000, 0.08183, 0.06105, \ + 0.05098, 0.04566, 0.03388, 0.03246, 0.02461, 0.02006, 0.01723, 0.01138, \ + 0.00700, 0.00401, 0.00216, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.01143, 0.01367, 0.01545, 0.01671, 0.02069, 0.02132, 0.02563, 0.02894, \ + 0.03136, 0.03728, 0.04246, 0.04623, 0.04843, 0.05076, 0.01546, 0.01752, \ + 0.01919, 0.02040, 0.02428, 0.02491, 0.02926, 0.03265, 0.03518, 0.04141, \ + 0.04700, 0.05114, 0.05360, 0.05633, 0.01575, 0.01780, 0.01947, 0.02067, \ + 0.02455, 0.02518, 0.02953, 0.03293, 0.03547, 0.04172, 0.04733, 0.05149, \ + 0.05398, 0.05673, 0.02195, 0.02390, 0.02551, 0.02668, 0.03051, 0.03114, \ + 0.03553, 0.03901, 0.04161, 0.04817, 0.05419, 0.05878, 0.06162, 0.06495, \ + 0.02360, 0.02554, 0.02713, 0.02830, 0.03212, 0.03275, 0.03714, 0.04064, \ + 0.04325, 0.04986, 0.05596, 0.06065, 0.06357, 0.06705, 0.03289, 0.03477, \ + 0.03634, 0.03748, 0.04126, 0.04188, 0.04627, 0.04980, 0.05246, 0.05926, \ + 0.06571, 0.07082, 0.07415, 0.07841 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.07026, 0.05105, 0.04201, 0.03735, 0.02725, 0.02606, 0.01955, 0.01585, \ + 0.01355, 0.00881, 0.00528, 0.00289, 0.00148, 0.00000, 0.07456, 0.05472, \ + 0.04528, 0.04037, 0.02968, 0.02841, 0.02144, 0.01744, 0.01495, 0.00980, \ + 0.00593, 0.00330, 0.00171, 0.00000, 0.07483, 0.05495, 0.04548, 0.04057, \ + 0.02983, 0.02856, 0.02156, 0.01754, 0.01504, 0.00987, 0.00598, 0.00333, \ + 0.00172, 0.00000, 0.07910, 0.05871, 0.04891, 0.04378, 0.03249, 0.03114, \ + 0.02368, 0.01937, 0.01668, 0.01109, 0.00683, 0.00389, 0.00206, 0.00000, \ + 0.07990, 0.05944, 0.04959, 0.04442, 0.03304, 0.03167, 0.02413, 0.01977, \ + 0.01704, 0.01136, 0.00703, 0.00402, 0.00214, 0.00000, 0.08328, 0.06254, \ + 0.05248, 0.04718, 0.03542, 0.03400, 0.02614, 0.02156, 0.01869, 0.01267, \ + 0.00802, 0.00471, 0.00259, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.1400, 0.2700, 0.2800, 0.5000, 0.5600, 0.9000 "); + index_2 (" 0.1400, 0.2100, 0.2700, 0.3150, 0.4725, 0.5000, 0.7088, 0.9000, \ + 1.0631, 1.5947, 2.3920, 3.5880, 5.3821, 538.2070 "); + values (" 0.00975, 0.01170, 0.01325, 0.01434, 0.01778, 0.01833, 0.02206, 0.02497, \ + 0.02713, 0.03263, 0.03780, 0.04189, 0.04446, 0.04737, 0.01321, 0.01496, \ + 0.01638, 0.01741, 0.02071, 0.02124, 0.02497, 0.02794, 0.03019, 0.03596, \ + 0.04152, 0.04597, 0.04883, 0.05218, 0.01346, 0.01520, 0.01661, 0.01763, \ + 0.02093, 0.02146, 0.02519, 0.02816, 0.03041, 0.03620, 0.04179, 0.04626, \ + 0.04914, 0.05253, 0.01856, 0.02018, 0.02152, 0.02249, 0.02571, 0.02624, \ + 0.02999, 0.03302, 0.03534, 0.04140, 0.04736, 0.05225, 0.05550, 0.05954, \ + 0.01989, 0.02150, 0.02283, 0.02380, 0.02700, 0.02753, 0.03128, 0.03432, \ + 0.03665, 0.04276, 0.04879, 0.05378, 0.05711, 0.06131, 0.02737, 0.02892, \ + 0.03021, 0.03116, 0.03432, 0.03485, 0.03860, 0.04168, 0.04404, 0.05032, \ + 0.05666, 0.06204, 0.06578, 0.07083 "); + } + } + } + + layer (metal3) { + resistance: 0.250000 + + capacitance () { + top_plane: metal4; + bottom_plane: metal2; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.05741, 0.04373, 0.03672, 0.02161, 0.01082, 0.00818, 0.00409, 0.00128, \ + 0.00100, 0.00013, 0.00006, 0.00001, 0.00000, 0.00000, 0.00000, 0.00000, \ + 0.05773, 0.04398, 0.03692, 0.02172, 0.01088, 0.00822, 0.00411, 0.00128, \ + 0.00100, 0.00013, 0.00006, 0.00001, 0.00000, 0.00000, 0.00000, 0.00000, \ + 0.05804, 0.04422, 0.03712, 0.02183, 0.01093, 0.00826, 0.00413, 0.00129, \ + 0.00101, 0.00013, 0.00006, 0.00001, 0.00000, 0.00000, 0.00000, 0.00000, \ + 0.05814, 0.04429, 0.03718, 0.02187, 0.01095, 0.00827, 0.00414, 0.00129, \ + 0.00101, 0.00013, 0.00006, 0.00001, 0.00000, 0.00000, 0.00000, 0.00000, \ + 0.05815, 0.04430, 0.03719, 0.02187, 0.01095, 0.00827, 0.00414, 0.00129, \ + 0.00101, 0.00013, 0.00006, 0.00001, 0.00000, 0.00000, 0.00000, 0.00000, \ + 0.05816, 0.04431, 0.03719, 0.02188, 0.01095, 0.00828, 0.00414, 0.00129, \ + 0.00101, 0.00013, 0.00006, 0.00001, 0.00000, 0.00000, 0.00000, 0.00000, \ + 0.05815, 0.04430, 0.03719, 0.02187, 0.01095, 0.00828, 0.00414, 0.00129, \ + 0.00101, 0.00013, 0.00006, 0.00001, 0.00000, 0.00000, 0.00000, 0.00000, \ + 0.05816, 0.04430, 0.03719, 0.02187, 0.01095, 0.00828, 0.00414, 0.00129, \ + 0.00101, 0.00013, 0.00006, 0.00001, 0.00000, 0.00000, 0.00000, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.05019, 0.05590, 0.06004, 0.07264, 0.08637, 0.09060, 0.09763, 0.10327, \ + 0.10389, 0.10565, 0.10561, 0.10587, 0.10575, 0.10584, 0.10596, 0.10595, \ + 0.05742, 0.06319, 0.06737, 0.08005, 0.09386, 0.09811, 0.10518, 0.11084, \ + 0.11146, 0.11324, 0.11320, 0.11346, 0.11335, 0.11343, 0.11353, 0.11353, \ + 0.07566, 0.08150, 0.08571, 0.09849, 0.11237, 0.11664, 0.12375, 0.12943, \ + 0.13006, 0.13184, 0.13181, 0.13206, 0.13195, 0.13204, 0.13213, 0.13213, \ + 0.12354, 0.12939, 0.13362, 0.14642, 0.16033, 0.16461, 0.17173, 0.17742, \ + 0.17805, 0.17984, 0.17980, 0.18006, 0.17995, 0.18003, 0.18013, 0.18012, \ + 0.12722, 0.13308, 0.13731, 0.15011, 0.16402, 0.16830, 0.17542, 0.18111, \ + 0.18174, 0.18353, 0.18349, 0.18375, 0.18364, 0.18373, 0.18382, 0.18382, \ + 0.20839, 0.21424, 0.21847, 0.23128, 0.24519, 0.24947, 0.25659, 0.26229, \ + 0.26291, 0.26470, 0.26467, 0.26492, 0.26481, 0.26490, 0.26499, 0.26499, \ + 0.35597, 0.36183, 0.36606, 0.37886, 0.39277, 0.39705, 0.40417, 0.40987, \ + 0.41049, 0.41228, 0.41225, 0.41250, 0.41239, 0.41248, 0.41245, 0.41257, \ + 0.57734, 0.58319, 0.58742, 0.60023, 0.61414, 0.61842, 0.62554, 0.63123, \ + 0.63186, 0.63365, 0.63362, 0.63387, 0.63376, 0.63385, 0.63382, 0.63394 "); + } + } + + capacitance () { + top_plane: metal4; + bottom_plane: metal1; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.06188, 0.04851, 0.04169, 0.02696, 0.01605, 0.01317, 0.00824, 0.00389, \ + 0.00332, 0.00091, 0.00055, 0.00014, 0.00004, 0.00001, 0.00000, 0.00000, \ + 0.06272, 0.04923, 0.04233, 0.02742, 0.01635, 0.01342, 0.00841, 0.00397, \ + 0.00339, 0.00093, 0.00057, 0.00014, 0.00004, 0.00001, 0.00000, 0.00000, \ + 0.06403, 0.05037, 0.04336, 0.02817, 0.01685, 0.01385, 0.00870, 0.00412, \ + 0.00352, 0.00096, 0.00059, 0.00015, 0.00004, 0.00001, 0.00000, 0.00000, \ + 0.06548, 0.05164, 0.04453, 0.02904, 0.01743, 0.01435, 0.00903, 0.00429, \ + 0.00367, 0.00101, 0.00061, 0.00015, 0.00004, 0.00001, 0.00000, 0.00000, \ + 0.06554, 0.05170, 0.04458, 0.02908, 0.01746, 0.01437, 0.00905, 0.00430, \ + 0.00367, 0.00101, 0.00062, 0.00016, 0.00004, 0.00001, 0.00000, 0.00000, \ + 0.06611, 0.05220, 0.04503, 0.02942, 0.01769, 0.01456, 0.00918, 0.00436, \ + 0.00373, 0.00102, 0.00063, 0.00016, 0.00004, 0.00001, 0.00000, 0.00000, \ + 0.06621, 0.05229, 0.04512, 0.02948, 0.01773, 0.01460, 0.00920, 0.00438, \ + 0.00374, 0.00103, 0.00063, 0.00016, 0.00004, 0.00001, 0.00000, 0.00000, \ + 0.06622, 0.05230, 0.04512, 0.02949, 0.01773, 0.01460, 0.00921, 0.00438, \ + 0.00374, 0.00103, 0.00063, 0.00016, 0.00004, 0.00001, 0.00000, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.03514, 0.03897, 0.04176, 0.05050, 0.06098, 0.06460, 0.07162, 0.07912, \ + 0.08020, 0.08486, 0.08545, 0.08641, 0.08655, 0.08667, 0.08671, 0.08671, \ + 0.03968, 0.04354, 0.04636, 0.05519, 0.06579, 0.06947, 0.07660, 0.08423, \ + 0.08533, 0.09009, 0.09070, 0.09168, 0.09183, 0.09194, 0.09197, 0.09197, \ + 0.05120, 0.05511, 0.05797, 0.06694, 0.07775, 0.08151, 0.08882, 0.09668, \ + 0.09782, 0.10274, 0.10339, 0.10440, 0.10456, 0.10468, 0.10469, 0.10469, \ + 0.08193, 0.08590, 0.08881, 0.09795, 0.10900, 0.11286, 0.12039, 0.12852, \ + 0.12969, 0.13482, 0.13550, 0.13656, 0.13673, 0.13685, 0.13685, 0.13685, \ + 0.08432, 0.08830, 0.09120, 0.10035, 0.11142, 0.11528, 0.12282, 0.13096, \ + 0.13214, 0.13727, 0.13795, 0.13901, 0.13918, 0.13930, 0.13930, 0.13930, \ + 0.13736, 0.14137, 0.14430, 0.15352, 0.16469, 0.16859, 0.17621, 0.18446, \ + 0.18565, 0.19087, 0.19156, 0.19264, 0.19281, 0.19293, 0.19293, 0.19293, \ + 0.23438, 0.23840, 0.24133, 0.25057, 0.26176, 0.26567, 0.27331, 0.28157, \ + 0.28277, 0.28800, 0.28870, 0.28977, 0.28995, 0.29007, 0.29007, 0.29007, \ + 0.38002, 0.38403, 0.38697, 0.39621, 0.40740, 0.41130, 0.41895, 0.42721, \ + 0.42841, 0.43364, 0.43434, 0.43541, 0.43559, 0.43571, 0.43571, 0.43571 "); + } + } + + capacitance () { + top_plane: metal4; + bottom_plane: poly; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.06262, 0.04933, 0.04258, 0.02805, 0.01735, 0.01452, 0.00962, 0.00511, \ + 0.00449, 0.00159, 0.00108, 0.00037, 0.00013, 0.00005, 0.00000, 0.00000, \ + 0.06357, 0.05017, 0.04334, 0.02863, 0.01776, 0.01488, 0.00989, 0.00527, \ + 0.00463, 0.00164, 0.00111, 0.00038, 0.00013, 0.00005, 0.00000, 0.00000, \ + 0.06519, 0.05162, 0.04468, 0.02968, 0.01853, 0.01556, 0.01039, 0.00557, \ + 0.00490, 0.00175, 0.00119, 0.00041, 0.00014, 0.00005, 0.00000, 0.00000, \ + 0.06737, 0.05361, 0.04654, 0.03118, 0.01966, 0.01656, 0.01114, 0.00602, \ + 0.00531, 0.00191, 0.00130, 0.00045, 0.00015, 0.00006, 0.00000, 0.00000, \ + 0.06748, 0.05371, 0.04663, 0.03126, 0.01972, 0.01661, 0.01118, 0.00605, \ + 0.00533, 0.00192, 0.00131, 0.00045, 0.00015, 0.00006, 0.00000, 0.00000, \ + 0.06881, 0.05493, 0.04778, 0.03219, 0.02042, 0.01724, 0.01165, 0.00633, \ + 0.00558, 0.00202, 0.00138, 0.00047, 0.00016, 0.00006, 0.00000, 0.00000, \ + 0.06932, 0.05540, 0.04822, 0.03256, 0.02070, 0.01748, 0.01183, 0.00645, \ + 0.00568, 0.00206, 0.00141, 0.00048, 0.00017, 0.00006, 0.00000, 0.00000, \ + 0.06940, 0.05547, 0.04829, 0.03262, 0.02074, 0.01752, 0.01186, 0.00646, \ + 0.00570, 0.00207, 0.00141, 0.00049, 0.00017, 0.00006, 0.00000, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.03315, 0.03668, 0.03926, 0.04724, 0.05675, 0.06007, 0.06658, 0.07393, \ + 0.07505, 0.08044, 0.08133, 0.08287, 0.08329, 0.08352, 0.08363, 0.08363, \ + 0.03733, 0.04088, 0.04346, 0.05149, 0.06110, 0.06445, 0.07108, 0.07858, \ + 0.07973, 0.08528, 0.08620, 0.08778, 0.08823, 0.08847, 0.08856, 0.08856, \ + 0.04784, 0.05140, 0.05399, 0.06210, 0.07188, 0.07531, 0.08214, 0.08993, \ + 0.09113, 0.09697, 0.09796, 0.09965, 0.10013, 0.10037, 0.10046, 0.10046, \ + 0.07563, 0.07921, 0.08183, 0.09006, 0.10008, 0.10362, 0.11074, 0.11897, \ + 0.12025, 0.12653, 0.12762, 0.12945, 0.12999, 0.13025, 0.13034, 0.13034, \ + 0.07779, 0.08137, 0.08399, 0.09223, 0.10226, 0.10581, 0.11295, 0.12119, \ + 0.12248, 0.12879, 0.12988, 0.13172, 0.13226, 0.13252, 0.13261, 0.13261, \ + 0.12576, 0.12938, 0.13202, 0.14036, 0.15057, 0.15420, 0.16153, 0.17004, \ + 0.17137, 0.17796, 0.17912, 0.18105, 0.18162, 0.18190, 0.18198, 0.18199, \ + 0.21408, 0.21772, 0.22038, 0.22876, 0.23905, 0.24271, 0.25011, 0.25874, \ + 0.26009, 0.26679, 0.26797, 0.26993, 0.27053, 0.27080, 0.27091, 0.27089, \ + 0.34703, 0.35067, 0.35334, 0.36173, 0.37203, 0.37570, 0.38311, 0.39175, \ + 0.39310, 0.39982, 0.40100, 0.40297, 0.40357, 0.40385, 0.40395, 0.40394 "); + } + } + + capacitance () { + top_plane: metal4; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.06295, 0.04969, 0.04295, 0.02851, 0.01792, 0.01513, 0.01029, 0.00579, \ + 0.00516, 0.00209, 0.00150, 0.00062, 0.00025, 0.00011, 0.00001, 0.00000, \ + 0.06393, 0.05056, 0.04376, 0.02914, 0.01840, 0.01555, 0.01062, 0.00600, \ + 0.00535, 0.00217, 0.00157, 0.00065, 0.00027, 0.00012, 0.00001, 0.00000, \ + 0.06567, 0.05214, 0.04523, 0.03034, 0.01931, 0.01637, 0.01126, 0.00642, \ + 0.00573, 0.00235, 0.00170, 0.00070, 0.00029, 0.00013, 0.00001, 0.00000, \ + 0.06823, 0.05451, 0.04747, 0.03221, 0.02079, 0.01772, 0.01232, 0.00712, \ + 0.00637, 0.00266, 0.00193, 0.00080, 0.00033, 0.00015, 0.00001, 0.00000, \ + 0.06837, 0.05464, 0.04759, 0.03232, 0.02087, 0.01780, 0.01238, 0.00716, \ + 0.00641, 0.00268, 0.00194, 0.00080, 0.00033, 0.00015, 0.00001, 0.00000, \ + 0.07025, 0.05640, 0.04927, 0.03375, 0.02202, 0.01884, 0.01321, 0.00772, \ + 0.00692, 0.00292, 0.00213, 0.00089, 0.00037, 0.00016, 0.00001, 0.00000, \ + 0.07130, 0.05739, 0.05022, 0.03457, 0.02268, 0.01944, 0.01369, 0.00805, \ + 0.00722, 0.00307, 0.00224, 0.00093, 0.00039, 0.00017, 0.00002, 0.00000, \ + 0.07158, 0.05766, 0.05047, 0.03478, 0.02285, 0.01960, 0.01382, 0.00813, \ + 0.00730, 0.00311, 0.00227, 0.00095, 0.00040, 0.00017, 0.00002, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.03230, 0.03575, 0.03824, 0.04593, 0.05503, 0.05819, 0.06442, 0.07153, \ + 0.07264, 0.07821, 0.07922, 0.08109, 0.08175, 0.08211, 0.08234, 0.08235, \ + 0.03638, 0.03981, 0.04230, 0.05002, 0.05918, 0.06238, 0.06871, 0.07597, \ + 0.07711, 0.08285, 0.08391, 0.08584, 0.08655, 0.08692, 0.08714, 0.08715, \ + 0.04652, 0.04994, 0.05243, 0.06016, 0.06945, 0.07272, 0.07922, 0.08679, \ + 0.08798, 0.09408, 0.09523, 0.09731, 0.09808, 0.09848, 0.09870, 0.09872, \ + 0.07308, 0.07649, 0.07897, 0.08677, 0.09624, 0.09960, 0.10641, 0.11446, \ + 0.11574, 0.12243, 0.12373, 0.12607, 0.12696, 0.12740, 0.12765, 0.12767, \ + 0.07513, 0.07854, 0.08103, 0.08883, 0.09831, 0.10168, 0.10850, 0.11658, \ + 0.11787, 0.12459, 0.12590, 0.12825, 0.12914, 0.12959, 0.12984, 0.12987, \ + 0.12070, 0.12413, 0.12664, 0.13452, 0.14418, 0.14764, 0.15470, 0.16315, \ + 0.16452, 0.17170, 0.17313, 0.17569, 0.17668, 0.17717, 0.17744, 0.17747, \ + 0.20474, 0.20819, 0.21072, 0.21867, 0.22845, 0.23197, 0.23916, 0.24783, \ + 0.24924, 0.25670, 0.25819, 0.26088, 0.26192, 0.26243, 0.26275, 0.26275, \ + 0.33166, 0.33512, 0.33765, 0.34562, 0.35544, 0.35897, 0.36620, 0.37493, \ + 0.37635, 0.38387, 0.38539, 0.38810, 0.38916, 0.38968, 0.39000, 0.39000 "); + } + } + + capacitance () { + top_plane: metal5; + bottom_plane: metal2; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.06279, 0.04952, 0.04278, 0.02830, 0.01766, 0.01485, 0.00998, 0.00547, \ + 0.00484, 0.00183, 0.00128, 0.00048, 0.00018, 0.00007, 0.00000, 0.00000, \ + 0.06377, 0.05038, 0.04357, 0.02891, 0.01811, 0.01525, 0.01028, 0.00565, \ + 0.00500, 0.00190, 0.00133, 0.00050, 0.00019, 0.00007, 0.00000, 0.00000, \ + 0.06545, 0.05190, 0.04498, 0.03004, 0.01895, 0.01600, 0.01085, 0.00601, \ + 0.00532, 0.00204, 0.00143, 0.00054, 0.00020, 0.00008, 0.00000, 0.00000, \ + 0.06784, 0.05410, 0.04704, 0.03174, 0.02026, 0.01718, 0.01175, 0.00658, \ + 0.00584, 0.00227, 0.00159, 0.00060, 0.00023, 0.00009, 0.00001, 0.00000, \ + 0.06797, 0.05421, 0.04715, 0.03183, 0.02033, 0.01724, 0.01180, 0.00661, \ + 0.00587, 0.00228, 0.00160, 0.00060, 0.00023, 0.00009, 0.00001, 0.00000, \ + 0.06957, 0.05570, 0.04856, 0.03300, 0.02124, 0.01806, 0.01243, 0.00702, \ + 0.00624, 0.00244, 0.00172, 0.00065, 0.00024, 0.00010, 0.00001, 0.00000, \ + 0.07031, 0.05640, 0.04922, 0.03356, 0.02167, 0.01845, 0.01274, 0.00721, \ + 0.00641, 0.00252, 0.00178, 0.00067, 0.00025, 0.00010, 0.00001, 0.00000, \ + 0.07046, 0.05654, 0.04935, 0.03367, 0.02176, 0.01852, 0.01279, 0.00725, \ + 0.00645, 0.00253, 0.00179, 0.00068, 0.00025, 0.00010, 0.00001, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.03270, 0.03619, 0.03872, 0.04653, 0.05583, 0.05906, 0.06542, 0.07266, \ + 0.07378, 0.07929, 0.08024, 0.08196, 0.08250, 0.08279, 0.08294, 0.08295, \ + 0.03682, 0.04031, 0.04284, 0.05070, 0.06006, 0.06333, 0.06981, 0.07720, \ + 0.07834, 0.08402, 0.08503, 0.08680, 0.08737, 0.08766, 0.08781, 0.08781, \ + 0.04713, 0.05061, 0.05315, 0.06105, 0.07057, 0.07391, 0.08058, 0.08827, \ + 0.08947, 0.09548, 0.09656, 0.09845, 0.09907, 0.09939, 0.09953, 0.09953, \ + 0.07425, 0.07774, 0.08029, 0.08828, 0.09802, 0.10147, 0.10844, 0.11660, \ + 0.11789, 0.12442, 0.12562, 0.12771, 0.12841, 0.12875, 0.12890, 0.12891, \ + 0.07635, 0.07984, 0.08239, 0.09039, 0.10014, 0.10360, 0.11059, 0.11877, \ + 0.12006, 0.12662, 0.12783, 0.12993, 0.13064, 0.13098, 0.13113, 0.13114, \ + 0.12306, 0.12658, 0.12915, 0.13725, 0.14719, 0.15074, 0.15793, 0.16645, \ + 0.16780, 0.17473, 0.17602, 0.17827, 0.17903, 0.17940, 0.17955, 0.17956, \ + 0.20917, 0.21272, 0.21531, 0.22347, 0.23350, 0.23709, 0.24440, 0.25306, \ + 0.25445, 0.26155, 0.26289, 0.26520, 0.26600, 0.26637, 0.26655, 0.26654, \ + 0.33900, 0.34255, 0.34515, 0.35332, 0.36337, 0.36697, 0.37430, 0.38300, \ + 0.38438, 0.39152, 0.39287, 0.39519, 0.39599, 0.39637, 0.39655, 0.39654 "); + } + } + + capacitance () { + top_plane: metal5; + bottom_plane: metal1; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.06774, 0.05476, 0.04820, 0.03411, 0.02356, 0.02067, 0.01539, 0.00988, \ + 0.00902, 0.00435, 0.00330, 0.00154, 0.00071, 0.00034, 0.00004, 0.00000, \ + 0.06917, 0.05604, 0.04938, 0.03503, 0.02424, 0.02126, 0.01584, 0.01017, \ + 0.00929, 0.00448, 0.00340, 0.00159, 0.00073, 0.00035, 0.00004, 0.00000, \ + 0.07177, 0.05837, 0.05154, 0.03673, 0.02548, 0.02237, 0.01668, 0.01071, \ + 0.00978, 0.00472, 0.00359, 0.00167, 0.00077, 0.00037, 0.00004, 0.00000, \ + 0.07535, 0.06163, 0.05456, 0.03914, 0.02728, 0.02397, 0.01790, 0.01151, \ + 0.01051, 0.00509, 0.00387, 0.00180, 0.00083, 0.00040, 0.00004, 0.00000, \ + 0.07553, 0.06178, 0.05471, 0.03926, 0.02736, 0.02405, 0.01796, 0.01155, \ + 0.01055, 0.00510, 0.00389, 0.00181, 0.00083, 0.00040, 0.00004, 0.00000, \ + 0.07758, 0.06366, 0.05647, 0.04069, 0.02844, 0.02501, 0.01870, 0.01204, \ + 0.01100, 0.00533, 0.00406, 0.00189, 0.00087, 0.00042, 0.00004, 0.00000, \ + 0.07838, 0.06441, 0.05718, 0.04127, 0.02889, 0.02541, 0.01901, 0.01225, \ + 0.01120, 0.00543, 0.00414, 0.00193, 0.00089, 0.00043, 0.00005, 0.00000, \ + 0.07853, 0.06455, 0.05731, 0.04138, 0.02897, 0.02548, 0.01907, 0.01229, \ + 0.01123, 0.00545, 0.00415, 0.00193, 0.00089, 0.00043, 0.00005, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.01662, 0.01827, 0.01947, 0.02332, 0.02846, 0.03046, 0.03499, 0.04138, \ + 0.04254, 0.04976, 0.05153, 0.05488, 0.05650, 0.05728, 0.05783, 0.05790, \ + 0.01819, 0.01980, 0.02098, 0.02484, 0.03004, 0.03209, 0.03672, 0.04326, \ + 0.04446, 0.05187, 0.05370, 0.05714, 0.05881, 0.05961, 0.06017, 0.06025, \ + 0.02200, 0.02359, 0.02476, 0.02866, 0.03404, 0.03617, 0.04099, 0.04784, \ + 0.04910, 0.05688, 0.05882, 0.06245, 0.06420, 0.06505, 0.06563, 0.06571, \ + 0.03231, 0.03393, 0.03514, 0.03921, 0.04488, 0.04712, 0.05225, 0.05955, \ + 0.06089, 0.06922, 0.07130, 0.07520, 0.07710, 0.07801, 0.07863, 0.07871, \ + 0.03313, 0.03476, 0.03597, 0.04005, 0.04573, 0.04798, 0.05313, 0.06045, \ + 0.06180, 0.07015, 0.07223, 0.07615, 0.07806, 0.07897, 0.07959, 0.07968, \ + 0.05194, 0.05362, 0.05487, 0.05908, 0.06495, 0.06729, 0.07262, 0.08022, \ + 0.08162, 0.09030, 0.09248, 0.09657, 0.09856, 0.09951, 0.10016, 0.10025, \ + 0.08759, 0.08929, 0.09056, 0.09483, 0.10079, 0.10316, 0.10858, 0.11629, \ + 0.11771, 0.12654, 0.12876, 0.13291, 0.13495, 0.13592, 0.13671, 0.13667, \ + 0.14171, 0.14341, 0.14468, 0.14897, 0.15494, 0.15732, 0.16275, 0.17048, \ + 0.17190, 0.18076, 0.18298, 0.18715, 0.18919, 0.19017, 0.19096, 0.19093 "); + } + } + + capacitance () { + top_plane: metal5; + bottom_plane: poly; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.06875, 0.05585, 0.04934, 0.03544, 0.02513, 0.02231, 0.01716, 0.01168, \ + 0.01081, 0.00581, 0.00461, 0.00242, 0.00125, 0.00066, 0.00010, 0.00000, \ + 0.07027, 0.05722, 0.05062, 0.03646, 0.02591, 0.02301, 0.01770, 0.01205, \ + 0.01115, 0.00600, 0.00475, 0.00250, 0.00129, 0.00069, 0.00010, 0.00000, \ + 0.07312, 0.05982, 0.05305, 0.03844, 0.02740, 0.02435, 0.01875, 0.01276, \ + 0.01180, 0.00635, 0.00503, 0.00263, 0.00136, 0.00072, 0.00011, 0.00000, \ + 0.07738, 0.06372, 0.05671, 0.04142, 0.02968, 0.02640, 0.02035, 0.01384, \ + 0.01280, 0.00688, 0.00546, 0.00285, 0.00147, 0.00078, 0.00011, 0.00000, \ + 0.07760, 0.06392, 0.05690, 0.04158, 0.02980, 0.02651, 0.02043, 0.01389, \ + 0.01285, 0.00691, 0.00548, 0.00286, 0.00148, 0.00079, 0.00011, 0.00000, \ + 0.08033, 0.06644, 0.05927, 0.04352, 0.03129, 0.02785, 0.02147, 0.01460, \ + 0.01350, 0.00726, 0.00576, 0.00300, 0.00155, 0.00083, 0.00012, 0.00000, \ + 0.08151, 0.06753, 0.06030, 0.04438, 0.03194, 0.02843, 0.02193, 0.01491, \ + 0.01379, 0.00741, 0.00588, 0.00307, 0.00159, 0.00084, 0.00013, 0.00000, \ + 0.08172, 0.06772, 0.06048, 0.04453, 0.03206, 0.02854, 0.02201, 0.01496, \ + 0.01384, 0.00743, 0.00590, 0.00308, 0.00159, 0.00085, 0.00013, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.01398, 0.01537, 0.01635, 0.01947, 0.02356, 0.02515, 0.02880, 0.03419, \ + 0.03523, 0.04212, 0.04403, 0.04793, 0.05013, 0.05132, 0.05240, 0.05260, \ + 0.01526, 0.01658, 0.01752, 0.02060, 0.02469, 0.02631, 0.03004, 0.03558, \ + 0.03664, 0.04374, 0.04571, 0.04972, 0.05199, 0.05321, 0.05432, 0.05453, \ + 0.01819, 0.01943, 0.02034, 0.02337, 0.02757, 0.02924, 0.03315, 0.03897, \ + 0.04010, 0.04758, 0.04967, 0.05392, 0.05632, 0.05760, 0.05877, 0.05899, \ + 0.02572, 0.02695, 0.02788, 0.03101, 0.03545, 0.03724, 0.04144, 0.04774, \ + 0.04895, 0.05705, 0.05931, 0.06391, 0.06651, 0.06790, 0.06916, 0.06940, \ + 0.02632, 0.02756, 0.02848, 0.03162, 0.03607, 0.03787, 0.04209, 0.04842, \ + 0.04963, 0.05777, 0.06003, 0.06465, 0.06726, 0.06866, 0.06992, 0.07016, \ + 0.04022, 0.04151, 0.04248, 0.04576, 0.05044, 0.05233, 0.05677, 0.06343, \ + 0.06470, 0.07324, 0.07562, 0.08048, 0.08322, 0.08468, 0.08600, 0.08625, \ + 0.06726, 0.06859, 0.06957, 0.07294, 0.07773, 0.07968, 0.08422, 0.09102, \ + 0.09233, 0.10105, 0.10348, 0.10843, 0.11123, 0.11272, 0.11420, 0.11433, \ + 0.10872, 0.11005, 0.11104, 0.11442, 0.11923, 0.12118, 0.12575, 0.13257, \ + 0.13388, 0.14263, 0.14507, 0.15004, 0.15285, 0.15435, 0.15584, 0.15596 "); + } + } + + capacitance () { + top_plane: metal5; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.06927, 0.05639, 0.04991, 0.03608, 0.02588, 0.02311, 0.01806, 0.01269, \ + 0.01183, 0.00680, 0.00554, 0.00314, 0.00176, 0.00102, 0.00019, 0.00000, \ + 0.07081, 0.05779, 0.05122, 0.03715, 0.02671, 0.02387, 0.01866, 0.01311, \ + 0.01222, 0.00702, 0.00572, 0.00325, 0.00182, 0.00105, 0.00020, 0.00000, \ + 0.07376, 0.06049, 0.05375, 0.03924, 0.02834, 0.02534, 0.01984, 0.01394, \ + 0.01299, 0.00746, 0.00608, 0.00344, 0.00193, 0.00111, 0.00021, 0.00000, \ + 0.07836, 0.06474, 0.05776, 0.04257, 0.03095, 0.02772, 0.02174, 0.01527, \ + 0.01423, 0.00817, 0.00666, 0.00376, 0.00211, 0.00122, 0.00023, 0.00000, \ + 0.07860, 0.06497, 0.05797, 0.04275, 0.03109, 0.02784, 0.02184, 0.01534, \ + 0.01430, 0.00821, 0.00669, 0.00378, 0.00212, 0.00122, 0.00023, 0.00000, \ + 0.08185, 0.06799, 0.06084, 0.04515, 0.03299, 0.02956, 0.02322, 0.01631, \ + 0.01520, 0.00873, 0.00711, 0.00402, 0.00226, 0.00130, 0.00024, 0.00000, \ + 0.08351, 0.06954, 0.06232, 0.04641, 0.03398, 0.03047, 0.02394, 0.01683, \ + 0.01568, 0.00900, 0.00734, 0.00414, 0.00233, 0.00134, 0.00026, 0.00000, \ + 0.08390, 0.06991, 0.06266, 0.04670, 0.03422, 0.03068, 0.02411, 0.01695, \ + 0.01579, 0.00906, 0.00739, 0.00417, 0.00234, 0.00135, 0.00026, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.01269, 0.01397, 0.01488, 0.01774, 0.02138, 0.02278, 0.02599, 0.03076, \ + 0.03169, 0.03812, 0.03999, 0.04404, 0.04656, 0.04803, 0.04962, 0.05001, \ + 0.01388, 0.01509, 0.01595, 0.01872, 0.02233, 0.02375, 0.02702, 0.03192, \ + 0.03287, 0.03949, 0.04143, 0.04559, 0.04819, 0.04971, 0.05135, 0.05175, \ + 0.01651, 0.01761, 0.01842, 0.02108, 0.02473, 0.02619, 0.02959, 0.03474, \ + 0.03576, 0.04275, 0.04481, 0.04924, 0.05200, 0.05360, 0.05533, 0.05576, \ + 0.02290, 0.02397, 0.02476, 0.02745, 0.03126, 0.03281, 0.03648, 0.04208, \ + 0.04318, 0.05081, 0.05305, 0.05790, 0.06091, 0.06266, 0.06455, 0.06502, \ + 0.02340, 0.02447, 0.02526, 0.02796, 0.03179, 0.03334, 0.03702, 0.04265, \ + 0.04375, 0.05141, 0.05367, 0.05854, 0.06156, 0.06332, 0.06522, 0.06569, \ + 0.03502, 0.03612, 0.03694, 0.03976, 0.04379, 0.04544, 0.04935, 0.05533, \ + 0.05650, 0.06464, 0.06704, 0.07220, 0.07542, 0.07729, 0.07930, 0.07980, \ + 0.05788, 0.05902, 0.05987, 0.06278, 0.06695, 0.06866, 0.07269, 0.07887, \ + 0.08007, 0.08847, 0.09095, 0.09627, 0.09958, 0.10151, 0.10371, 0.10410, \ + 0.09334, 0.09449, 0.09535, 0.09828, 0.10248, 0.10420, 0.10827, 0.11449, \ + 0.11570, 0.12416, 0.12665, 0.13202, 0.13535, 0.13729, 0.13951, 0.13990 "); + } + } + + capacitance () { + top_plane: metal6; + bottom_plane: metal2; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.06328, 0.05004, 0.04332, 0.02894, 0.01844, 0.01568, 0.01092, 0.00647, \ + 0.00583, 0.00269, 0.00205, 0.00101, 0.00051, 0.00027, 0.00004, 0.00000, \ + 0.06428, 0.05094, 0.04416, 0.02961, 0.01897, 0.01616, 0.01130, 0.00673, \ + 0.00608, 0.00282, 0.00215, 0.00107, 0.00054, 0.00029, 0.00005, 0.00000, \ + 0.06611, 0.05261, 0.04573, 0.03092, 0.02002, 0.01713, 0.01208, 0.00729, \ + 0.00659, 0.00310, 0.00238, 0.00118, 0.00060, 0.00032, 0.00005, 0.00000, \ + 0.06900, 0.05532, 0.04832, 0.03317, 0.02187, 0.01885, 0.01351, 0.00832, \ + 0.00756, 0.00365, 0.00282, 0.00142, 0.00073, 0.00039, 0.00006, 0.00000, \ + 0.06917, 0.05548, 0.04847, 0.03330, 0.02199, 0.01895, 0.01360, 0.00839, \ + 0.00762, 0.00369, 0.00285, 0.00143, 0.00074, 0.00040, 0.00006, 0.00000, \ + 0.07169, 0.05788, 0.05078, 0.03535, 0.02372, 0.02057, 0.01496, 0.00941, \ + 0.00858, 0.00425, 0.00331, 0.00168, 0.00087, 0.00047, 0.00008, 0.00000, \ + 0.07363, 0.05974, 0.05259, 0.03698, 0.02512, 0.02188, 0.01608, 0.01025, \ + 0.00938, 0.00472, 0.00369, 0.00190, 0.00099, 0.00054, 0.00009, 0.00000, \ + 0.07450, 0.06058, 0.05340, 0.03771, 0.02575, 0.02247, 0.01659, 0.01064, \ + 0.00974, 0.00494, 0.00387, 0.00200, 0.00104, 0.00057, 0.00009, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.03146, 0.03484, 0.03729, 0.04478, 0.05355, 0.05657, 0.06252, 0.06935, \ + 0.07042, 0.07598, 0.07707, 0.07920, 0.08012, 0.08067, 0.08116, 0.08124, \ + 0.03547, 0.03883, 0.04126, 0.04874, 0.05753, 0.06058, 0.06661, 0.07358, \ + 0.07468, 0.08043, 0.08158, 0.08379, 0.08477, 0.08534, 0.08584, 0.08593, \ + 0.04538, 0.04869, 0.05109, 0.05851, 0.06737, 0.07047, 0.07664, 0.08389, \ + 0.08505, 0.09117, 0.09243, 0.09485, 0.09594, 0.09657, 0.09711, 0.09722, \ + 0.07091, 0.07417, 0.07654, 0.08393, 0.09288, 0.09605, 0.10248, 0.11020, \ + 0.11146, 0.11827, 0.11972, 0.12254, 0.12385, 0.12459, 0.12524, 0.12537, \ + 0.07288, 0.07613, 0.07850, 0.08589, 0.09485, 0.09802, 0.10447, 0.11222, \ + 0.11348, 0.12034, 0.12180, 0.12464, 0.12596, 0.12671, 0.12737, 0.12750, \ + 0.11621, 0.11946, 0.12182, 0.12924, 0.13832, 0.14157, 0.14825, 0.15644, \ + 0.15779, 0.16531, 0.16696, 0.17019, 0.17174, 0.17261, 0.17339, 0.17355, \ + 0.19583, 0.19909, 0.20147, 0.20895, 0.21816, 0.22149, 0.22836, 0.23691, \ + 0.23834, 0.24639, 0.24820, 0.25176, 0.25351, 0.25448, 0.25539, 0.25554, \ + 0.31643, 0.31970, 0.32209, 0.32961, 0.33889, 0.34226, 0.34923, 0.35793, \ + 0.35940, 0.36769, 0.36958, 0.37328, 0.37512, 0.37614, 0.37710, 0.37726 "); + } + } + + capacitance () { + top_plane: metal6; + bottom_plane: metal1; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.06842, 0.05547, 0.04893, 0.03493, 0.02454, 0.02171, 0.01658, 0.01124, \ + 0.01041, 0.00572, 0.00462, 0.00258, 0.00146, 0.00085, 0.00017, 0.00000, \ + 0.06987, 0.05678, 0.05014, 0.03590, 0.02528, 0.02238, 0.01712, 0.01162, \ + 0.01076, 0.00593, 0.00478, 0.00268, 0.00152, 0.00089, 0.00018, 0.00000, \ + 0.07258, 0.05924, 0.05244, 0.03778, 0.02673, 0.02370, 0.01817, 0.01238, \ + 0.01146, 0.00635, 0.00513, 0.00287, 0.00163, 0.00096, 0.00020, 0.00000, \ + 0.07665, 0.06299, 0.05598, 0.04072, 0.02906, 0.02583, 0.01991, 0.01365, \ + 0.01266, 0.00708, 0.00574, 0.00323, 0.00184, 0.00108, 0.00022, 0.00000, \ + 0.07686, 0.06319, 0.05617, 0.04088, 0.02919, 0.02595, 0.02001, 0.01372, \ + 0.01273, 0.00712, 0.00577, 0.00325, 0.00185, 0.00109, 0.00022, 0.00000, \ + 0.07981, 0.06595, 0.05880, 0.04315, 0.03106, 0.02768, 0.02146, 0.01482, \ + 0.01377, 0.00777, 0.00632, 0.00358, 0.00205, 0.00121, 0.00025, 0.00000, \ + 0.08175, 0.06781, 0.06060, 0.04475, 0.03243, 0.02896, 0.02256, 0.01567, \ + 0.01457, 0.00829, 0.00675, 0.00385, 0.00221, 0.00131, 0.00028, 0.00000, \ + 0.08258, 0.06860, 0.06137, 0.04545, 0.03303, 0.02952, 0.02304, 0.01604, \ + 0.01492, 0.00851, 0.00695, 0.00397, 0.00228, 0.00135, 0.00029, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.01493, 0.01647, 0.01758, 0.02112, 0.02571, 0.02746, 0.03140, 0.03696, \ + 0.03799, 0.04461, 0.04638, 0.05000, 0.05209, 0.05330, 0.05461, 0.05497, \ + 0.01641, 0.01790, 0.01898, 0.02246, 0.02705, 0.02882, 0.03283, 0.03851, \ + 0.03957, 0.04638, 0.04820, 0.05192, 0.05410, 0.05536, 0.05671, 0.05708, \ + 0.01989, 0.02130, 0.02234, 0.02576, 0.03040, 0.03222, 0.03635, 0.04227, \ + 0.04339, 0.05055, 0.05249, 0.05647, 0.05880, 0.06014, 0.06158, 0.06198, \ + 0.02868, 0.03007, 0.03109, 0.03454, 0.03932, 0.04121, 0.04557, 0.05188, \ + 0.05306, 0.06082, 0.06294, 0.06734, 0.06993, 0.07144, 0.07307, 0.07353, \ + 0.02937, 0.03076, 0.03178, 0.03523, 0.04002, 0.04192, 0.04628, 0.05262, \ + 0.05380, 0.06159, 0.06373, 0.06815, 0.07076, 0.07227, 0.07391, 0.07438, \ + 0.04487, 0.04627, 0.04731, 0.05082, 0.05573, 0.05769, 0.06222, 0.06885, \ + 0.07011, 0.07838, 0.08068, 0.08546, 0.08832, 0.08999, 0.09181, 0.09232, \ + 0.07414, 0.07556, 0.07661, 0.08018, 0.08518, 0.08719, 0.09185, 0.09871, \ + 0.10001, 0.10867, 0.11109, 0.11615, 0.11921, 0.12099, 0.12309, 0.12352, \ + 0.11910, 0.12053, 0.12159, 0.12519, 0.13025, 0.13228, 0.13700, 0.14396, \ + 0.14529, 0.15411, 0.15659, 0.16178, 0.16492, 0.16676, 0.16892, 0.16937 "); + } + } + + capacitance () { + top_plane: metal6; + bottom_plane: poly; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.06954, 0.05667, 0.05019, 0.03638, 0.02621, 0.02346, 0.01846, 0.01319, \ + 0.01234, 0.00742, 0.00617, 0.00374, 0.00227, 0.00142, 0.00034, 0.00000, \ + 0.07109, 0.05807, 0.05150, 0.03745, 0.02706, 0.02423, 0.01909, 0.01364, \ + 0.01277, 0.00768, 0.00638, 0.00388, 0.00235, 0.00147, 0.00036, 0.00000, \ + 0.07404, 0.06079, 0.05405, 0.03958, 0.02874, 0.02577, 0.02035, 0.01456, \ + 0.01363, 0.00820, 0.00683, 0.00413, 0.00251, 0.00157, 0.00038, 0.00000, \ + 0.07875, 0.06516, 0.05820, 0.04307, 0.03155, 0.02835, 0.02246, 0.01611, \ + 0.01509, 0.00911, 0.00759, 0.00461, 0.00280, 0.00176, 0.00043, 0.00000, \ + 0.07901, 0.06540, 0.05843, 0.04327, 0.03170, 0.02849, 0.02258, 0.01620, \ + 0.01517, 0.00916, 0.00764, 0.00463, 0.00282, 0.00177, 0.00043, 0.00000, \ + 0.08262, 0.06878, 0.06165, 0.04604, 0.03397, 0.03058, 0.02432, 0.01751, \ + 0.01641, 0.00994, 0.00830, 0.00505, 0.00308, 0.00193, 0.00047, 0.00000, \ + 0.08490, 0.07095, 0.06374, 0.04788, 0.03551, 0.03202, 0.02553, 0.01844, \ + 0.01729, 0.01051, 0.00878, 0.00535, 0.00327, 0.00206, 0.00051, 0.00000, \ + 0.08577, 0.07179, 0.06455, 0.04860, 0.03613, 0.03260, 0.02602, 0.01882, \ + 0.01765, 0.01075, 0.00899, 0.00548, 0.00335, 0.00211, 0.00053, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.01201, 0.01327, 0.01417, 0.01698, 0.02053, 0.02187, 0.02491, 0.02938, \ + 0.03024, 0.03625, 0.03803, 0.04198, 0.04458, 0.04621, 0.04826, 0.04897, \ + 0.01320, 0.01439, 0.01524, 0.01795, 0.02144, 0.02278, 0.02587, 0.03043, \ + 0.03132, 0.03750, 0.03935, 0.04341, 0.04610, 0.04779, 0.04991, 0.05064, \ + 0.01582, 0.01689, 0.01767, 0.02023, 0.02369, 0.02506, 0.02823, 0.03301, \ + 0.03395, 0.04047, 0.04243, 0.04677, 0.04964, 0.05143, 0.05369, 0.05448, \ + 0.02191, 0.02291, 0.02365, 0.02616, 0.02970, 0.03113, 0.03451, 0.03967, \ + 0.04068, 0.04780, 0.04995, 0.05474, 0.05791, 0.05990, 0.06242, 0.06330, \ + 0.02238, 0.02338, 0.02412, 0.02663, 0.03018, 0.03161, 0.03500, 0.04018, \ + 0.04120, 0.04836, 0.05051, 0.05533, 0.05852, 0.06052, 0.06306, 0.06394, \ + 0.03303, 0.03404, 0.03480, 0.03738, 0.04108, 0.04258, 0.04616, 0.05166, \ + 0.05274, 0.06039, 0.06272, 0.06791, 0.07137, 0.07354, 0.07631, 0.07728, \ + 0.05376, 0.05480, 0.05558, 0.05824, 0.06205, 0.06361, 0.06731, 0.07304, \ + 0.07417, 0.08219, 0.08463, 0.09008, 0.09374, 0.09605, 0.09911, 0.10003, \ + 0.08610, 0.08715, 0.08794, 0.09063, 0.09449, 0.09608, 0.09984, 0.10566, \ + 0.10681, 0.11497, 0.11746, 0.12303, 0.12677, 0.12913, 0.13227, 0.13321 "); + } + } + + capacitance () { + top_plane: metal6; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.07013, 0.05730, 0.05085, 0.03712, 0.02706, 0.02435, 0.01945, 0.01429, \ + 0.01346, 0.00854, 0.00725, 0.00465, 0.00298, 0.00196, 0.00055, 0.00000, \ + 0.07171, 0.05874, 0.05219, 0.03823, 0.02795, 0.02518, 0.02013, 0.01480, \ + 0.01394, 0.00884, 0.00751, 0.00482, 0.00309, 0.00203, 0.00057, 0.00000, \ + 0.07476, 0.06155, 0.05484, 0.04047, 0.02976, 0.02684, 0.02152, 0.01583, \ + 0.01491, 0.00946, 0.00804, 0.00515, 0.00330, 0.00217, 0.00061, 0.00000, \ + 0.07979, 0.06624, 0.05931, 0.04429, 0.03288, 0.02972, 0.02391, 0.01763, \ + 0.01661, 0.01055, 0.00897, 0.00574, 0.00368, 0.00242, 0.00068, 0.00000, \ + 0.08008, 0.06651, 0.05956, 0.04450, 0.03306, 0.02989, 0.02405, 0.01774, \ + 0.01671, 0.01061, 0.00902, 0.00577, 0.00370, 0.00243, 0.00068, 0.00000, \ + 0.08418, 0.07038, 0.06327, 0.04772, 0.03572, 0.03235, 0.02611, 0.01930, \ + 0.01819, 0.01156, 0.00983, 0.00629, 0.00404, 0.00266, 0.00075, 0.00000, \ + 0.08693, 0.07299, 0.06578, 0.04994, 0.03758, 0.03408, 0.02757, 0.02041, \ + 0.01924, 0.01225, 0.01042, 0.00667, 0.00429, 0.00282, 0.00081, 0.00000, \ + 0.08796, 0.07398, 0.06673, 0.05078, 0.03829, 0.03475, 0.02814, 0.02085, \ + 0.01966, 0.01252, 0.01065, 0.00682, 0.00439, 0.00289, 0.00082, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.01052, 0.01166, 0.01248, 0.01500, 0.01812, 0.01928, 0.02188, 0.02569, \ + 0.02644, 0.03181, 0.03349, 0.03741, 0.04022, 0.04210, 0.04476, 0.04588, \ + 0.01161, 0.01268, 0.01343, 0.01583, 0.01886, 0.02001, 0.02262, 0.02651, \ + 0.02728, 0.03281, 0.03455, 0.03858, 0.04148, 0.04343, 0.04618, 0.04734, \ + 0.01393, 0.01487, 0.01554, 0.01773, 0.02066, 0.02181, 0.02447, 0.02852, \ + 0.02934, 0.03518, 0.03703, 0.04135, 0.04444, 0.04651, 0.04944, 0.05068, \ + 0.01894, 0.01977, 0.02038, 0.02245, 0.02537, 0.02655, 0.02937, 0.03376, \ + 0.03464, 0.04107, 0.04311, 0.04789, 0.05132, 0.05362, 0.05688, 0.05827, \ + 0.01931, 0.02014, 0.02075, 0.02282, 0.02574, 0.02693, 0.02976, 0.03417, \ + 0.03505, 0.04152, 0.04357, 0.04838, 0.05182, 0.05413, 0.05742, 0.05881, \ + 0.02772, 0.02855, 0.02917, 0.03128, 0.03433, 0.03559, 0.03859, 0.04333, \ + 0.04428, 0.05126, 0.05349, 0.05870, 0.06245, 0.06496, 0.06855, 0.07007, \ + 0.04434, 0.04519, 0.04583, 0.04803, 0.05121, 0.05253, 0.05569, 0.06068, \ + 0.06168, 0.06905, 0.07141, 0.07691, 0.08088, 0.08354, 0.08745, 0.08896, \ + 0.07072, 0.07159, 0.07224, 0.07448, 0.07772, 0.07906, 0.08228, 0.08738, \ + 0.08840, 0.09592, 0.09833, 0.10395, 0.10801, 0.11072, 0.11472, 0.11627 "); + } + } + + capacitance () { + top_plane: metal7; + bottom_plane: metal2; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.06347, 0.05024, 0.04352, 0.02916, 0.01869, 0.01595, 0.01121, 0.00679, \ + 0.00616, 0.00302, 0.00238, 0.00129, 0.00073, 0.00044, 0.00011, 0.00000, \ + 0.06448, 0.05115, 0.04437, 0.02984, 0.01923, 0.01645, 0.01162, 0.00709, \ + 0.00644, 0.00318, 0.00251, 0.00137, 0.00078, 0.00047, 0.00011, 0.00000, \ + 0.06633, 0.05284, 0.04597, 0.03120, 0.02034, 0.01747, 0.01247, 0.00772, \ + 0.00703, 0.00354, 0.00280, 0.00154, 0.00088, 0.00054, 0.00013, 0.00000, \ + 0.06935, 0.05569, 0.04870, 0.03360, 0.02238, 0.01938, 0.01409, 0.00895, \ + 0.00820, 0.00426, 0.00341, 0.00191, 0.00111, 0.00068, 0.00017, 0.00000, \ + 0.06953, 0.05586, 0.04886, 0.03375, 0.02250, 0.01950, 0.01419, 0.00903, \ + 0.00827, 0.00431, 0.00345, 0.00193, 0.00113, 0.00069, 0.00017, 0.00000, \ + 0.07238, 0.05859, 0.05151, 0.03615, 0.02460, 0.02147, 0.01591, 0.01039, \ + 0.00956, 0.00515, 0.00416, 0.00238, 0.00140, 0.00087, 0.00022, 0.00000, \ + 0.07496, 0.06110, 0.05396, 0.03841, 0.02661, 0.02338, 0.01761, 0.01175, \ + 0.01086, 0.00603, 0.00492, 0.00286, 0.00171, 0.00107, 0.00027, 0.00000, \ + 0.07654, 0.06263, 0.05546, 0.03980, 0.02786, 0.02458, 0.01867, 0.01262, \ + 0.01170, 0.00660, 0.00541, 0.00318, 0.00192, 0.00120, 0.00031, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.03097, 0.03432, 0.03675, 0.04417, 0.05285, 0.05583, 0.06167, 0.06835, \ + 0.06940, 0.07488, 0.07597, 0.07816, 0.07919, 0.07983, 0.08053, 0.08075, \ + 0.03496, 0.03829, 0.04070, 0.04810, 0.05677, 0.05977, 0.06568, 0.07249, \ + 0.07356, 0.07923, 0.08038, 0.08266, 0.08375, 0.08443, 0.08516, 0.08539, \ + 0.04480, 0.04808, 0.05044, 0.05776, 0.06644, 0.06947, 0.07550, 0.08255, \ + 0.08369, 0.08972, 0.09098, 0.09349, 0.09472, 0.09547, 0.09629, 0.09655, \ + 0.06997, 0.07316, 0.07548, 0.08270, 0.09139, 0.09447, 0.10070, 0.10819, \ + 0.10942, 0.11615, 0.11762, 0.12057, 0.12208, 0.12299, 0.12401, 0.12436, \ + 0.07190, 0.07508, 0.07740, 0.08461, 0.09331, 0.09639, 0.10264, 0.11016, \ + 0.11139, 0.11816, 0.11964, 0.12262, 0.12415, 0.12507, 0.12611, 0.12646, \ + 0.11420, 0.11735, 0.11965, 0.12683, 0.13560, 0.13874, 0.14519, 0.15312, \ + 0.15445, 0.16192, 0.16363, 0.16711, 0.16895, 0.17008, 0.17137, 0.17182, \ + 0.19147, 0.19462, 0.19692, 0.20412, 0.21299, 0.21619, 0.22283, 0.23116, \ + 0.23257, 0.24073, 0.24266, 0.24663, 0.24882, 0.25016, 0.25177, 0.25229, \ + 0.30833, 0.31149, 0.31380, 0.32104, 0.32999, 0.33324, 0.34001, 0.34859, \ + 0.35005, 0.35863, 0.36071, 0.36499, 0.36740, 0.36889, 0.37069, 0.37128 "); + } + } + + capacitance () { + top_plane: metal7; + bottom_plane: metal1; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.06870, 0.05576, 0.04923, 0.03526, 0.02489, 0.02207, 0.01698, 0.01172, \ + 0.01090, 0.00628, 0.00518, 0.00311, 0.00191, 0.00123, 0.00035, 0.00000, \ + 0.07016, 0.05708, 0.05045, 0.03623, 0.02565, 0.02277, 0.01755, 0.01213, \ + 0.01128, 0.00652, 0.00538, 0.00325, 0.00200, 0.00129, 0.00036, 0.00000, \ + 0.07288, 0.05956, 0.05277, 0.03814, 0.02715, 0.02414, 0.01867, 0.01296, \ + 0.01207, 0.00702, 0.00581, 0.00351, 0.00217, 0.00140, 0.00040, 0.00000, \ + 0.07707, 0.06343, 0.05643, 0.04123, 0.02966, 0.02646, 0.02061, 0.01445, \ + 0.01348, 0.00795, 0.00661, 0.00403, 0.00251, 0.00163, 0.00046, 0.00000, \ + 0.07730, 0.06364, 0.05664, 0.04141, 0.02980, 0.02659, 0.02073, 0.01454, \ + 0.01356, 0.00801, 0.00666, 0.00406, 0.00253, 0.00165, 0.00047, 0.00000, \ + 0.08057, 0.06674, 0.05961, 0.04403, 0.03203, 0.02868, 0.02254, 0.01598, \ + 0.01494, 0.00896, 0.00749, 0.00462, 0.00291, 0.00190, 0.00055, 0.00000, \ + 0.08315, 0.06923, 0.06203, 0.04624, 0.03399, 0.03055, 0.02419, 0.01734, \ + 0.01625, 0.00989, 0.00830, 0.00518, 0.00329, 0.00216, 0.00064, 0.00000, \ + 0.08466, 0.07069, 0.06346, 0.04757, 0.03518, 0.03168, 0.02521, 0.01819, \ + 0.01706, 0.01047, 0.00881, 0.00553, 0.00353, 0.00232, 0.00069, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.01421, 0.01572, 0.01681, 0.02028, 0.02476, 0.02646, 0.03025, 0.03554, \ + 0.03652, 0.04282, 0.04452, 0.04809, 0.05027, 0.05161, 0.05330, 0.05400, \ + 0.01568, 0.01714, 0.01819, 0.02160, 0.02606, 0.02777, 0.03160, 0.03699, \ + 0.03799, 0.04446, 0.04622, 0.04989, 0.05216, 0.05355, 0.05531, 0.05605, \ + 0.01911, 0.02048, 0.02149, 0.02480, 0.02925, 0.03099, 0.03490, 0.04050, \ + 0.04154, 0.04834, 0.05021, 0.05414, 0.05657, 0.05806, 0.05997, 0.06078, \ + 0.02757, 0.02889, 0.02986, 0.03313, 0.03762, 0.03940, 0.04348, 0.04938, \ + 0.05050, 0.05784, 0.05989, 0.06425, 0.06700, 0.06870, 0.07091, 0.07186, \ + 0.02822, 0.02954, 0.03051, 0.03378, 0.03828, 0.04006, 0.04414, 0.05006, \ + 0.05118, 0.05855, 0.06061, 0.06501, 0.06777, 0.06949, 0.07171, 0.07268, \ + 0.04270, 0.04401, 0.04497, 0.04824, 0.05280, 0.05462, 0.05883, 0.06500, \ + 0.06617, 0.07403, 0.07627, 0.08109, 0.08418, 0.08612, 0.08868, 0.08980, \ + 0.06965, 0.07096, 0.07193, 0.07522, 0.07983, 0.08169, 0.08600, 0.09239, \ + 0.09362, 0.10192, 0.10432, 0.10955, 0.11296, 0.11512, 0.11814, 0.11931, \ + 0.11094, 0.11225, 0.11323, 0.11655, 0.12122, 0.12311, 0.12749, 0.13404, \ + 0.13530, 0.14388, 0.14638, 0.15186, 0.15547, 0.15777, 0.16102, 0.16230 "); + } + } + + capacitance () { + top_plane: metal7; + bottom_plane: poly; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.06988, 0.05703, 0.05056, 0.03677, 0.02663, 0.02389, 0.01893, 0.01373, \ + 0.01291, 0.00807, 0.00684, 0.00440, 0.00287, 0.00193, 0.00061, 0.00000, \ + 0.07144, 0.05844, 0.05187, 0.03784, 0.02749, 0.02468, 0.01958, 0.01422, \ + 0.01337, 0.00837, 0.00709, 0.00458, 0.00299, 0.00201, 0.00064, 0.00000, \ + 0.07441, 0.06117, 0.05444, 0.04000, 0.02922, 0.02627, 0.02091, 0.01522, \ + 0.01430, 0.00899, 0.00762, 0.00491, 0.00321, 0.00217, 0.00069, 0.00000, \ + 0.07922, 0.06565, 0.05870, 0.04363, 0.03219, 0.02903, 0.02321, 0.01698, \ + 0.01598, 0.01010, 0.00859, 0.00556, 0.00365, 0.00247, 0.00079, 0.00000, \ + 0.07949, 0.06591, 0.05894, 0.04384, 0.03236, 0.02918, 0.02335, 0.01709, \ + 0.01608, 0.01017, 0.00865, 0.00560, 0.00368, 0.00249, 0.00079, 0.00000, \ + 0.08342, 0.06962, 0.06250, 0.04696, 0.03498, 0.03163, 0.02544, 0.01873, \ + 0.01765, 0.01125, 0.00960, 0.00625, 0.00413, 0.00281, 0.00090, 0.00000, \ + 0.08633, 0.07240, 0.06521, 0.04940, 0.03711, 0.03364, 0.02721, 0.02017, \ + 0.01903, 0.01223, 0.01047, 0.00686, 0.00456, 0.00311, 0.00102, 0.00000, \ + 0.08786, 0.07389, 0.06666, 0.05074, 0.03830, 0.03478, 0.02822, 0.02101, \ + 0.01984, 0.01282, 0.01099, 0.00723, 0.00481, 0.00329, 0.00108, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.01117, 0.01238, 0.01325, 0.01597, 0.01941, 0.02071, 0.02360, 0.02778, \ + 0.02858, 0.03416, 0.03583, 0.03962, 0.04224, 0.04397, 0.04646, 0.04770, \ + 0.01233, 0.01347, 0.01430, 0.01692, 0.02028, 0.02157, 0.02448, 0.02873, \ + 0.02955, 0.03529, 0.03702, 0.04090, 0.04361, 0.04541, 0.04800, 0.04929, \ + 0.01489, 0.01592, 0.01667, 0.01912, 0.02240, 0.02369, 0.02664, 0.03104, \ + 0.03191, 0.03794, 0.03978, 0.04394, 0.04683, 0.04875, 0.05152, 0.05292, \ + 0.02069, 0.02162, 0.02231, 0.02464, 0.02789, 0.02920, 0.03229, 0.03699, \ + 0.03791, 0.04447, 0.04649, 0.05109, 0.05432, 0.05647, 0.05962, 0.06122, \ + 0.02112, 0.02205, 0.02274, 0.02506, 0.02832, 0.02963, 0.03273, 0.03745, \ + 0.03837, 0.04497, 0.04699, 0.05162, 0.05487, 0.05704, 0.06021, 0.06182, \ + 0.03077, 0.03169, 0.03238, 0.03472, 0.03805, 0.03942, 0.04264, 0.04762, \ + 0.04861, 0.05566, 0.05786, 0.06290, 0.06647, 0.06887, 0.07244, 0.07427, \ + 0.04920, 0.05014, 0.05083, 0.05321, 0.05663, 0.05803, 0.06136, 0.06655, \ + 0.06759, 0.07504, 0.07737, 0.08278, 0.08665, 0.08927, 0.09331, 0.09525, \ + 0.07790, 0.07884, 0.07955, 0.08196, 0.08543, 0.08685, 0.09025, 0.09557, \ + 0.09663, 0.10432, 0.10674, 0.11237, 0.11642, 0.11917, 0.12344, 0.12550 "); + } + } + + capacitance () { + top_plane: metal7; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.07051, 0.05770, 0.05126, 0.03756, 0.02753, 0.02484, 0.01997, 0.01489, \ + 0.01408, 0.00926, 0.00800, 0.00541, 0.00369, 0.00259, 0.00090, 0.00000, \ + 0.07211, 0.05915, 0.05261, 0.03867, 0.02844, 0.02567, 0.02068, 0.01543, \ + 0.01459, 0.00960, 0.00829, 0.00562, 0.00384, 0.00269, 0.00094, 0.00000, \ + 0.07518, 0.06198, 0.05528, 0.04094, 0.03029, 0.02739, 0.02213, 0.01654, \ + 0.01564, 0.01031, 0.00891, 0.00603, 0.00411, 0.00289, 0.00101, 0.00000, \ + 0.08030, 0.06678, 0.05986, 0.04489, 0.03357, 0.03044, 0.02471, 0.01855, \ + 0.01755, 0.01161, 0.01004, 0.00680, 0.00466, 0.00327, 0.00115, 0.00000, \ + 0.08060, 0.06705, 0.06012, 0.04512, 0.03376, 0.03062, 0.02487, 0.01867, \ + 0.01767, 0.01169, 0.01011, 0.00685, 0.00469, 0.00329, 0.00116, 0.00000, \ + 0.08502, 0.07124, 0.06415, 0.04867, 0.03676, 0.03343, 0.02727, 0.02057, \ + 0.01948, 0.01294, 0.01121, 0.00761, 0.00523, 0.00368, 0.00130, 0.00000, \ + 0.08838, 0.07446, 0.06727, 0.05148, 0.03919, 0.03573, 0.02928, 0.02218, \ + 0.02102, 0.01404, 0.01218, 0.00830, 0.00572, 0.00403, 0.00144, 0.00000, \ + 0.09007, 0.07609, 0.06886, 0.05293, 0.04048, 0.03694, 0.03036, 0.02307, \ + 0.02188, 0.01465, 0.01273, 0.00869, 0.00600, 0.00424, 0.00152, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.00958, 0.01066, 0.01144, 0.01386, 0.01686, 0.01797, 0.02043, 0.02395, \ + 0.02464, 0.02953, 0.03107, 0.03475, 0.03750, 0.03944, 0.04254, 0.04436, \ + 0.01063, 0.01164, 0.01237, 0.01467, 0.01757, 0.01866, 0.02111, 0.02468, \ + 0.02537, 0.03040, 0.03200, 0.03577, 0.03861, 0.04063, 0.04384, 0.04573, \ + 0.01288, 0.01378, 0.01442, 0.01650, 0.01925, 0.02031, 0.02275, 0.02643, \ + 0.02716, 0.03245, 0.03415, 0.03819, 0.04123, 0.04337, 0.04680, 0.04884, \ + 0.01761, 0.01838, 0.01894, 0.02082, 0.02346, 0.02452, 0.02704, 0.03096, \ + 0.03174, 0.03753, 0.03940, 0.04389, 0.04727, 0.04967, 0.05355, 0.05586, \ + 0.01795, 0.01871, 0.01927, 0.02115, 0.02379, 0.02485, 0.02738, 0.03131, \ + 0.03210, 0.03791, 0.03980, 0.04431, 0.04771, 0.05013, 0.05403, 0.05636, \ + 0.02539, 0.02612, 0.02667, 0.02854, 0.03123, 0.03234, 0.03499, 0.03918, \ + 0.04003, 0.04631, 0.04836, 0.05330, 0.05704, 0.05971, 0.06405, 0.06666, \ + 0.03973, 0.04048, 0.04104, 0.04296, 0.04574, 0.04689, 0.04967, 0.05409, \ + 0.05498, 0.06167, 0.06387, 0.06916, 0.07321, 0.07610, 0.08094, 0.08372, \ + 0.06249, 0.06325, 0.06382, 0.06578, 0.06863, 0.06981, 0.07265, 0.07720, \ + 0.07812, 0.08504, 0.08731, 0.09281, 0.09703, 0.10005, 0.10512, 0.10806 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: metal2; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.06394, 0.05072, 0.04403, 0.02969, 0.01925, 0.01651, 0.01177, 0.00735, \ + 0.00672, 0.00355, 0.00289, 0.00177, 0.00117, 0.00084, 0.00039, 0.00000, \ + 0.06497, 0.05165, 0.04488, 0.03039, 0.01981, 0.01703, 0.01221, 0.00768, \ + 0.00703, 0.00375, 0.00306, 0.00189, 0.00126, 0.00091, 0.00042, 0.00000, \ + 0.06685, 0.05338, 0.04652, 0.03178, 0.02097, 0.01811, 0.01313, 0.00840, \ + 0.00771, 0.00421, 0.00346, 0.00216, 0.00145, 0.00105, 0.00050, 0.00000, \ + 0.06998, 0.05635, 0.04938, 0.03433, 0.02318, 0.02020, 0.01497, 0.00988, \ + 0.00913, 0.00521, 0.00435, 0.00279, 0.00193, 0.00142, 0.00069, 0.00000, \ + 0.07018, 0.05653, 0.04955, 0.03449, 0.02332, 0.02034, 0.01509, 0.00998, \ + 0.00923, 0.00528, 0.00441, 0.00284, 0.00196, 0.00145, 0.00071, 0.00000, \ + 0.07338, 0.05962, 0.05257, 0.03728, 0.02584, 0.02275, 0.01727, 0.01183, \ + 0.01101, 0.00663, 0.00562, 0.00376, 0.00267, 0.00202, 0.00103, 0.00000, \ + 0.07689, 0.06306, 0.05596, 0.04050, 0.02884, 0.02566, 0.01998, 0.01422, \ + 0.01335, 0.00850, 0.00735, 0.00515, 0.00380, 0.00296, 0.00162, 0.00000, \ + 0.08013, 0.06626, 0.05913, 0.04357, 0.03177, 0.02853, 0.02271, 0.01672, \ + 0.01580, 0.01059, 0.00932, 0.00681, 0.00522, 0.00418, 0.00245, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.02977, 0.03305, 0.03543, 0.04274, 0.05130, 0.05425, 0.06005, 0.06672, \ + 0.06778, 0.07329, 0.07441, 0.07666, 0.07777, 0.07849, 0.07942, 0.08021, \ + 0.03372, 0.03699, 0.03935, 0.04662, 0.05517, 0.05813, 0.06399, 0.07075, \ + 0.07183, 0.07751, 0.07868, 0.08102, 0.08220, 0.08296, 0.08394, 0.08480, \ + 0.04345, 0.04666, 0.04898, 0.05616, 0.06469, 0.06766, 0.07359, 0.08055, \ + 0.08167, 0.08768, 0.08895, 0.09153, 0.09285, 0.09370, 0.09481, 0.09582, \ + 0.06826, 0.07138, 0.07364, 0.08067, 0.08912, 0.09211, 0.09815, 0.10543, \ + 0.10662, 0.11323, 0.11470, 0.11771, 0.11934, 0.12039, 0.12184, 0.12324, \ + 0.07015, 0.07327, 0.07553, 0.08255, 0.09099, 0.09398, 0.10003, 0.10733, \ + 0.10853, 0.11517, 0.11665, 0.11969, 0.12134, 0.12241, 0.12387, 0.12531, \ + 0.11143, 0.11448, 0.11670, 0.12361, 0.13201, 0.13501, 0.14116, 0.14875, \ + 0.15002, 0.15726, 0.15896, 0.16251, 0.16454, 0.16587, 0.16781, 0.16990, \ + 0.18584, 0.18884, 0.19103, 0.19786, 0.20622, 0.20923, 0.21547, 0.22333, \ + 0.22466, 0.23254, 0.23447, 0.23859, 0.24109, 0.24278, 0.24542, 0.24865, \ + 0.29695, 0.29993, 0.30210, 0.30889, 0.31722, 0.32024, 0.32653, 0.33458, \ + 0.33597, 0.34432, 0.34644, 0.35107, 0.35401, 0.35604, 0.35943, 0.36431 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: metal1; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.06943, 0.05652, 0.05001, 0.03608, 0.02576, 0.02296, 0.01789, 0.01265, \ + 0.01183, 0.00725, 0.00615, 0.00408, 0.00285, 0.00211, 0.00102, 0.00000, \ + 0.07091, 0.05785, 0.05124, 0.03707, 0.02653, 0.02367, 0.01847, 0.01309, \ + 0.01226, 0.00754, 0.00641, 0.00428, 0.00299, 0.00222, 0.00108, 0.00000, \ + 0.07367, 0.06036, 0.05359, 0.03901, 0.02807, 0.02508, 0.01966, 0.01402, \ + 0.01314, 0.00817, 0.00697, 0.00467, 0.00330, 0.00246, 0.00121, 0.00000, \ + 0.07796, 0.06434, 0.05737, 0.04223, 0.03074, 0.02758, 0.02181, 0.01577, \ + 0.01482, 0.00942, 0.00810, 0.00554, 0.00397, 0.00301, 0.00152, 0.00000, \ + 0.07820, 0.06457, 0.05758, 0.04241, 0.03090, 0.02773, 0.02194, 0.01588, \ + 0.01492, 0.00950, 0.00817, 0.00560, 0.00402, 0.00305, 0.00155, 0.00000, \ + 0.08181, 0.06801, 0.06091, 0.04541, 0.03354, 0.03025, 0.02422, 0.01783, \ + 0.01682, 0.01102, 0.00957, 0.00672, 0.00493, 0.00381, 0.00201, 0.00000, \ + 0.08533, 0.07145, 0.06429, 0.04861, 0.03651, 0.03313, 0.02691, 0.02026, \ + 0.01920, 0.01302, 0.01145, 0.00830, 0.00626, 0.00495, 0.00277, 0.00000, \ + 0.08851, 0.07458, 0.06739, 0.05161, 0.03937, 0.03594, 0.02960, 0.02275, \ + 0.02165, 0.01518, 0.01351, 0.01010, 0.00784, 0.00634, 0.00377, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.01241, 0.01381, 0.01483, 0.01812, 0.02243, 0.02408, 0.02777, 0.03291, \ + 0.03386, 0.03996, 0.04160, 0.04508, 0.04727, 0.04868, 0.05073, 0.05278, \ + 0.01382, 0.01518, 0.01617, 0.01941, 0.02369, 0.02534, 0.02904, 0.03425, \ + 0.03522, 0.04143, 0.04313, 0.04669, 0.04896, 0.05042, 0.05257, 0.05474, \ + 0.01713, 0.01843, 0.01938, 0.02252, 0.02677, 0.02842, 0.03216, 0.03748, \ + 0.03848, 0.04492, 0.04670, 0.05049, 0.05291, 0.05448, 0.05681, 0.05925, \ + 0.02528, 0.02652, 0.02743, 0.03048, 0.03468, 0.03634, 0.04012, 0.04558, \ + 0.04661, 0.05341, 0.05532, 0.05947, 0.06218, 0.06398, 0.06672, 0.06976, \ + 0.02590, 0.02713, 0.02804, 0.03109, 0.03529, 0.03694, 0.04073, 0.04620, \ + 0.04723, 0.05404, 0.05596, 0.06013, 0.06286, 0.06467, 0.06744, 0.07053, \ + 0.03938, 0.04057, 0.04146, 0.04443, 0.04856, 0.05020, 0.05398, 0.05953, \ + 0.06058, 0.06767, 0.06972, 0.07423, 0.07728, 0.07934, 0.08264, 0.08664, \ + 0.06345, 0.06460, 0.06546, 0.06836, 0.07240, 0.07402, 0.07777, 0.08335, \ + 0.08442, 0.09176, 0.09393, 0.09880, 0.10221, 0.10458, 0.10865, 0.11401, \ + 0.09900, 0.10013, 0.10097, 0.10380, 0.10778, 0.10939, 0.11312, 0.11872, \ + 0.11980, 0.12732, 0.12959, 0.13476, 0.13849, 0.14113, 0.14589, 0.15318 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: poly; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.07075, 0.05795, 0.05151, 0.03780, 0.02772, 0.02500, 0.02006, 0.01489, \ + 0.01407, 0.00930, 0.00809, 0.00569, 0.00414, 0.00316, 0.00161, 0.00000, \ + 0.07235, 0.05939, 0.05285, 0.03889, 0.02859, 0.02580, 0.02073, 0.01542, \ + 0.01457, 0.00966, 0.00840, 0.00593, 0.00433, 0.00331, 0.00169, 0.00000, \ + 0.07538, 0.06217, 0.05546, 0.04108, 0.03036, 0.02743, 0.02212, 0.01651, \ + 0.01561, 0.01041, 0.00908, 0.00642, 0.00471, 0.00362, 0.00187, 0.00000, \ + 0.08030, 0.06676, 0.05983, 0.04482, 0.03347, 0.03034, 0.02462, 0.01852, \ + 0.01755, 0.01185, 0.01039, 0.00744, 0.00553, 0.00429, 0.00227, 0.00000, \ + 0.08058, 0.06702, 0.06008, 0.04504, 0.03366, 0.03052, 0.02477, 0.01865, \ + 0.01767, 0.01195, 0.01048, 0.00751, 0.00558, 0.00433, 0.00230, 0.00000, \ + 0.08483, 0.07106, 0.06397, 0.04852, 0.03668, 0.03338, 0.02732, 0.02081, \ + 0.01976, 0.01361, 0.01202, 0.00876, 0.00662, 0.00521, 0.00286, 0.00000, \ + 0.08867, 0.07479, 0.06763, 0.05194, 0.03980, 0.03640, 0.03012, 0.02331, \ + 0.02221, 0.01568, 0.01397, 0.01043, 0.00805, 0.00646, 0.00373, 0.00000, \ + 0.09187, 0.07794, 0.07074, 0.05494, 0.04266, 0.03921, 0.03280, 0.02580, \ + 0.02466, 0.01786, 0.01606, 0.01228, 0.00970, 0.00794, 0.00482, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.00900, 0.01006, 0.01083, 0.01330, 0.01652, 0.01775, 0.02053, 0.02453, \ + 0.02530, 0.03057, 0.03213, 0.03568, 0.03819, 0.03992, 0.04274, 0.04593, \ + 0.01006, 0.01108, 0.01181, 0.01421, 0.01736, 0.01858, 0.02135, 0.02539, \ + 0.02616, 0.03152, 0.03313, 0.03675, 0.03934, 0.04113, 0.04405, 0.04740, \ + 0.01246, 0.01339, 0.01408, 0.01633, 0.01939, 0.02059, 0.02334, 0.02744, \ + 0.02824, 0.03377, 0.03546, 0.03929, 0.04203, 0.04392, 0.04706, 0.05075, \ + 0.01794, 0.01879, 0.01942, 0.02153, 0.02447, 0.02566, 0.02843, 0.03262, \ + 0.03344, 0.03926, 0.04105, 0.04520, 0.04821, 0.05033, 0.05391, 0.05837, \ + 0.01835, 0.01919, 0.01982, 0.02192, 0.02486, 0.02604, 0.02882, 0.03302, \ + 0.03384, 0.03967, 0.04147, 0.04564, 0.04866, 0.05079, 0.05440, 0.05891, \ + 0.02705, 0.02786, 0.02846, 0.03050, 0.03339, 0.03456, 0.03733, 0.04159, \ + 0.04243, 0.04847, 0.05037, 0.05481, 0.05810, 0.06046, 0.06458, 0.07016, \ + 0.04263, 0.04341, 0.04399, 0.04596, 0.04879, 0.04994, 0.05268, 0.05695, \ + 0.05780, 0.06398, 0.06595, 0.07064, 0.07421, 0.07681, 0.08164, 0.08877, \ + 0.06560, 0.06636, 0.06692, 0.06884, 0.07160, 0.07274, 0.07544, 0.07969, \ + 0.08054, 0.08680, 0.08882, 0.09371, 0.09749, 0.10032, 0.10575, 0.11493 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.07149, 0.05874, 0.05234, 0.03876, 0.02881, 0.02614, 0.02131, 0.01626, \ + 0.01545, 0.01071, 0.00948, 0.00695, 0.00524, 0.00411, 0.00221, 0.00000, \ + 0.07314, 0.06024, 0.05374, 0.03989, 0.02974, 0.02700, 0.02203, 0.01683, \ + 0.01600, 0.01111, 0.00983, 0.00723, 0.00546, 0.00429, 0.00231, 0.00000, \ + 0.07631, 0.06315, 0.05648, 0.04220, 0.03162, 0.02875, 0.02354, 0.01803, \ + 0.01715, 0.01195, 0.01059, 0.00780, 0.00591, 0.00466, 0.00253, 0.00000, \ + 0.08156, 0.06806, 0.06116, 0.04626, 0.03503, 0.03194, 0.02630, 0.02028, \ + 0.01932, 0.01359, 0.01208, 0.00896, 0.00685, 0.00544, 0.00301, 0.00000, \ + 0.08186, 0.06835, 0.06144, 0.04650, 0.03523, 0.03214, 0.02647, 0.02042, \ + 0.01945, 0.01369, 0.01218, 0.00904, 0.00692, 0.00549, 0.00305, 0.00000, \ + 0.08659, 0.07285, 0.06578, 0.05039, 0.03862, 0.03534, 0.02932, 0.02282, \ + 0.02178, 0.01552, 0.01388, 0.01043, 0.00807, 0.00648, 0.00369, 0.00000, \ + 0.09087, 0.07700, 0.06984, 0.05416, 0.04204, 0.03864, 0.03235, 0.02550, \ + 0.02439, 0.01771, 0.01594, 0.01219, 0.00961, 0.00783, 0.00466, 0.00000, \ + 0.09421, 0.08028, 0.07308, 0.05727, 0.04498, 0.04152, 0.03508, 0.02803, \ + 0.02688, 0.01992, 0.01806, 0.01408, 0.01130, 0.00936, 0.00582, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.00715, 0.00804, 0.00869, 0.01077, 0.01348, 0.01450, 0.01682, 0.02016, \ + 0.02080, 0.02534, 0.02675, 0.03009, 0.03262, 0.03447, 0.03778, 0.04207, \ + 0.00805, 0.00890, 0.00952, 0.01153, 0.01415, 0.01515, 0.01744, 0.02079, \ + 0.02144, 0.02604, 0.02749, 0.03088, 0.03349, 0.03540, 0.03882, 0.04330, \ + 0.01006, 0.01084, 0.01140, 0.01325, 0.01574, 0.01671, 0.01895, 0.02230, \ + 0.02297, 0.02769, 0.02920, 0.03278, 0.03553, 0.03754, 0.04119, 0.04608, \ + 0.01444, 0.01511, 0.01561, 0.01727, 0.01959, 0.02052, 0.02272, 0.02611, \ + 0.02678, 0.03172, 0.03332, 0.03718, 0.04018, 0.04240, 0.04651, 0.05230, \ + 0.01476, 0.01542, 0.01591, 0.01757, 0.01988, 0.02081, 0.02301, 0.02640, \ + 0.02707, 0.03203, 0.03363, 0.03750, 0.04051, 0.04275, 0.04688, 0.05274, \ + 0.02130, 0.02191, 0.02237, 0.02394, 0.02617, 0.02709, 0.02927, 0.03270, \ + 0.03339, 0.03852, 0.04020, 0.04432, 0.04757, 0.05001, 0.05464, 0.06170, \ + 0.03283, 0.03342, 0.03386, 0.03538, 0.03756, 0.03846, 0.04062, 0.04406, \ + 0.04475, 0.04999, 0.05174, 0.05605, 0.05952, 0.06218, 0.06744, 0.07618, \ + 0.04989, 0.05047, 0.05089, 0.05236, 0.05449, 0.05537, 0.05749, 0.06090, \ + 0.06160, 0.06687, 0.06865, 0.07309, 0.07673, 0.07956, 0.08532, 0.09619 "); + } + } + } + + layer (metal2) { + resistance: 0.250000 + + capacitance () { + top_plane: metal3; + bottom_plane: metal1; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.05741, 0.04373, 0.03672, 0.02161, 0.01082, 0.00818, 0.00409, 0.00128, \ + 0.00100, 0.00013, 0.00006, 0.00001, 0.00000, 0.00000, 0.00000, 0.00000, \ + 0.05773, 0.04398, 0.03692, 0.02172, 0.01088, 0.00822, 0.00411, 0.00128, \ + 0.00100, 0.00013, 0.00006, 0.00001, 0.00000, 0.00000, 0.00000, 0.00000, \ + 0.05804, 0.04422, 0.03712, 0.02183, 0.01093, 0.00826, 0.00413, 0.00129, \ + 0.00101, 0.00013, 0.00006, 0.00001, 0.00000, 0.00000, 0.00000, 0.00000, \ + 0.05814, 0.04429, 0.03718, 0.02187, 0.01095, 0.00827, 0.00414, 0.00129, \ + 0.00101, 0.00013, 0.00006, 0.00001, 0.00000, 0.00000, 0.00000, 0.00000, \ + 0.05815, 0.04430, 0.03719, 0.02187, 0.01095, 0.00827, 0.00414, 0.00129, \ + 0.00101, 0.00013, 0.00006, 0.00001, 0.00000, 0.00000, 0.00000, 0.00000, \ + 0.05816, 0.04431, 0.03719, 0.02188, 0.01095, 0.00828, 0.00414, 0.00129, \ + 0.00101, 0.00013, 0.00006, 0.00001, 0.00000, 0.00000, 0.00000, 0.00000, \ + 0.05815, 0.04430, 0.03719, 0.02187, 0.01095, 0.00828, 0.00414, 0.00129, \ + 0.00101, 0.00013, 0.00006, 0.00001, 0.00000, 0.00000, 0.00000, 0.00000, \ + 0.05816, 0.04430, 0.03719, 0.02187, 0.01095, 0.00828, 0.00414, 0.00129, \ + 0.00101, 0.00013, 0.00006, 0.00001, 0.00000, 0.00000, 0.00000, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.05019, 0.05590, 0.06004, 0.07264, 0.08637, 0.09060, 0.09763, 0.10327, \ + 0.10389, 0.10565, 0.10561, 0.10587, 0.10575, 0.10584, 0.10596, 0.10595, \ + 0.05742, 0.06319, 0.06737, 0.08005, 0.09386, 0.09811, 0.10518, 0.11084, \ + 0.11146, 0.11324, 0.11320, 0.11346, 0.11335, 0.11343, 0.11353, 0.11353, \ + 0.07566, 0.08150, 0.08571, 0.09849, 0.11237, 0.11664, 0.12375, 0.12943, \ + 0.13006, 0.13184, 0.13181, 0.13206, 0.13195, 0.13204, 0.13213, 0.13213, \ + 0.12354, 0.12939, 0.13362, 0.14642, 0.16033, 0.16461, 0.17173, 0.17742, \ + 0.17805, 0.17984, 0.17980, 0.18006, 0.17995, 0.18003, 0.18013, 0.18012, \ + 0.12722, 0.13308, 0.13731, 0.15011, 0.16402, 0.16830, 0.17542, 0.18111, \ + 0.18174, 0.18353, 0.18349, 0.18375, 0.18364, 0.18373, 0.18382, 0.18382, \ + 0.20839, 0.21424, 0.21847, 0.23128, 0.24519, 0.24947, 0.25659, 0.26229, \ + 0.26291, 0.26470, 0.26467, 0.26492, 0.26481, 0.26490, 0.26499, 0.26499, \ + 0.35597, 0.36183, 0.36606, 0.37886, 0.39277, 0.39705, 0.40417, 0.40987, \ + 0.41049, 0.41228, 0.41225, 0.41250, 0.41239, 0.41248, 0.41245, 0.41257, \ + 0.57734, 0.58319, 0.58742, 0.60023, 0.61414, 0.61842, 0.62554, 0.63123, \ + 0.63186, 0.63365, 0.63362, 0.63387, 0.63376, 0.63385, 0.63382, 0.63394 "); + } + } + + capacitance () { + top_plane: metal3; + bottom_plane: poly; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.06159, 0.04819, 0.04135, 0.02655, 0.01558, 0.01270, 0.00778, 0.00353, \ + 0.00298, 0.00075, 0.00044, 0.00010, 0.00002, 0.00001, 0.00000, 0.00000, \ + 0.06239, 0.04886, 0.04195, 0.02696, 0.01585, 0.01291, 0.00793, 0.00360, \ + 0.00304, 0.00076, 0.00045, 0.00010, 0.00002, 0.00001, 0.00000, 0.00000, \ + 0.06359, 0.04990, 0.04287, 0.02763, 0.01627, 0.01327, 0.00816, 0.00371, \ + 0.00314, 0.00079, 0.00047, 0.00011, 0.00002, 0.00001, 0.00000, 0.00000, \ + 0.06481, 0.05096, 0.04383, 0.02832, 0.01672, 0.01365, 0.00841, 0.00383, \ + 0.00324, 0.00082, 0.00048, 0.00011, 0.00003, 0.00001, 0.00000, 0.00000, \ + 0.06486, 0.05100, 0.04387, 0.02835, 0.01674, 0.01366, 0.00842, 0.00383, \ + 0.00324, 0.00082, 0.00048, 0.00011, 0.00003, 0.00001, 0.00000, 0.00000, \ + 0.06527, 0.05136, 0.04419, 0.02858, 0.01689, 0.01379, 0.00850, 0.00387, \ + 0.00328, 0.00083, 0.00049, 0.00011, 0.00003, 0.00001, 0.00000, 0.00000, \ + 0.06532, 0.05140, 0.04423, 0.02861, 0.01691, 0.01381, 0.00851, 0.00388, \ + 0.00328, 0.00083, 0.00049, 0.00011, 0.00003, 0.00001, 0.00000, 0.00000, \ + 0.06532, 0.05141, 0.04424, 0.02861, 0.01691, 0.01381, 0.00851, 0.00388, \ + 0.00328, 0.00083, 0.00049, 0.00011, 0.00003, 0.00001, 0.00000, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.03595, 0.03989, 0.04278, 0.05181, 0.06263, 0.06636, 0.07350, 0.08097, \ + 0.08202, 0.08637, 0.08687, 0.08769, 0.08777, 0.08787, 0.08791, 0.08791, \ + 0.04064, 0.04463, 0.04754, 0.05668, 0.06762, 0.07140, 0.07865, 0.08624, \ + 0.08731, 0.09174, 0.09226, 0.09309, 0.09317, 0.09328, 0.09330, 0.09330, \ + 0.05257, 0.05662, 0.05957, 0.06886, 0.08002, 0.08387, 0.09130, 0.09909, \ + 0.10018, 0.10475, 0.10529, 0.10615, 0.10624, 0.10634, 0.10635, 0.10635, \ + 0.08441, 0.08853, 0.09154, 0.10100, 0.11238, 0.11632, 0.12393, 0.13193, \ + 0.13305, 0.13777, 0.13833, 0.13922, 0.13932, 0.13942, 0.13942, 0.13942, \ + 0.08689, 0.09101, 0.09402, 0.10348, 0.11488, 0.11882, 0.12643, 0.13444, \ + 0.13557, 0.14030, 0.14086, 0.14174, 0.14184, 0.14194, 0.14195, 0.14194, \ + 0.14176, 0.14591, 0.14893, 0.15846, 0.16992, 0.17389, 0.18157, 0.18965, \ + 0.19079, 0.19556, 0.19613, 0.19702, 0.19712, 0.19723, 0.19723, 0.19723, \ + 0.24195, 0.24610, 0.24913, 0.25866, 0.27014, 0.27411, 0.28180, 0.28989, \ + 0.29103, 0.29581, 0.29638, 0.29727, 0.29737, 0.29748, 0.29747, 0.29748, \ + 0.39228, 0.39643, 0.39946, 0.40899, 0.42047, 0.42445, 0.43213, 0.44022, \ + 0.44136, 0.44614, 0.44671, 0.44760, 0.44771, 0.44781, 0.44780, 0.44781 "); + } + } + + capacitance () { + top_plane: metal3; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.06251, 0.04921, 0.04244, 0.02788, 0.01715, 0.01431, 0.00941, 0.00492, \ + 0.00430, 0.00147, 0.00099, 0.00033, 0.00011, 0.00004, 0.00000, 0.00000, \ + 0.06344, 0.05003, 0.04319, 0.02844, 0.01755, 0.01466, 0.00966, 0.00506, \ + 0.00443, 0.00152, 0.00102, 0.00034, 0.00011, 0.00004, 0.00000, 0.00000, \ + 0.06502, 0.05143, 0.04448, 0.02945, 0.01827, 0.01530, 0.01013, 0.00534, \ + 0.00468, 0.00161, 0.00108, 0.00036, 0.00012, 0.00004, 0.00000, 0.00000, \ + 0.06709, 0.05331, 0.04623, 0.03086, 0.01932, 0.01622, 0.01081, 0.00575, \ + 0.00504, 0.00175, 0.00118, 0.00039, 0.00013, 0.00005, 0.00000, 0.00000, \ + 0.06719, 0.05341, 0.04632, 0.03093, 0.01937, 0.01627, 0.01085, 0.00577, \ + 0.00506, 0.00176, 0.00119, 0.00039, 0.00013, 0.00005, 0.00000, 0.00000, \ + 0.06840, 0.05451, 0.04736, 0.03177, 0.02000, 0.01682, 0.01126, 0.00602, \ + 0.00528, 0.00185, 0.00125, 0.00041, 0.00014, 0.00005, 0.00000, 0.00000, \ + 0.06885, 0.05493, 0.04775, 0.03209, 0.02024, 0.01704, 0.01142, 0.00611, \ + 0.00537, 0.00188, 0.00127, 0.00042, 0.00014, 0.00005, 0.00000, 0.00000, \ + 0.06891, 0.05499, 0.04781, 0.03214, 0.02027, 0.01707, 0.01144, 0.00613, \ + 0.00538, 0.00189, 0.00127, 0.00042, 0.00014, 0.00005, 0.00000, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.03346, 0.03704, 0.03964, 0.04774, 0.05741, 0.06077, 0.06737, 0.07475, \ + 0.07587, 0.08116, 0.08200, 0.08344, 0.08382, 0.08403, 0.08412, 0.08412, \ + 0.03769, 0.04129, 0.04390, 0.05206, 0.06182, 0.06523, 0.07194, 0.07947, \ + 0.08061, 0.08605, 0.08693, 0.08842, 0.08881, 0.08902, 0.08911, 0.08910, \ + 0.04835, 0.05197, 0.05460, 0.06284, 0.07278, 0.07627, 0.08318, 0.09099, \ + 0.09219, 0.09790, 0.09884, 0.10041, 0.10084, 0.10106, 0.10113, 0.10113, \ + 0.07658, 0.08023, 0.08289, 0.09125, 0.10144, 0.10504, 0.11223, 0.12046, \ + 0.12173, 0.12785, 0.12888, 0.13058, 0.13106, 0.13129, 0.13136, 0.13136, \ + 0.07877, 0.08242, 0.08508, 0.09346, 0.10366, 0.10726, 0.11447, 0.12272, \ + 0.12399, 0.13014, 0.13117, 0.13288, 0.13335, 0.13359, 0.13365, 0.13366, \ + 0.12750, 0.13119, 0.13387, 0.14235, 0.15271, 0.15639, 0.16378, 0.17228, \ + 0.17359, 0.17999, 0.18107, 0.18286, 0.18337, 0.18361, 0.18368, 0.18368, \ + 0.21714, 0.22084, 0.22354, 0.23206, 0.24249, 0.24620, 0.25365, 0.26225, \ + 0.26357, 0.27007, 0.27118, 0.27299, 0.27351, 0.27376, 0.27384, 0.27383, \ + 0.35201, 0.35571, 0.35841, 0.36694, 0.37738, 0.38109, 0.38855, 0.39716, \ + 0.39849, 0.40500, 0.40611, 0.40793, 0.40845, 0.40870, 0.40878, 0.40877 "); + } + } + + capacitance () { + top_plane: metal4; + bottom_plane: metal1; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.06188, 0.04851, 0.04169, 0.02696, 0.01605, 0.01317, 0.00824, 0.00389, \ + 0.00332, 0.00091, 0.00055, 0.00014, 0.00004, 0.00001, 0.00000, 0.00000, \ + 0.06272, 0.04923, 0.04233, 0.02742, 0.01635, 0.01342, 0.00841, 0.00397, \ + 0.00339, 0.00093, 0.00057, 0.00014, 0.00004, 0.00001, 0.00000, 0.00000, \ + 0.06403, 0.05037, 0.04336, 0.02817, 0.01685, 0.01385, 0.00870, 0.00412, \ + 0.00352, 0.00096, 0.00059, 0.00015, 0.00004, 0.00001, 0.00000, 0.00000, \ + 0.06548, 0.05164, 0.04453, 0.02904, 0.01743, 0.01435, 0.00903, 0.00429, \ + 0.00367, 0.00101, 0.00061, 0.00015, 0.00004, 0.00001, 0.00000, 0.00000, \ + 0.06554, 0.05170, 0.04458, 0.02908, 0.01746, 0.01437, 0.00905, 0.00430, \ + 0.00367, 0.00101, 0.00062, 0.00015, 0.00004, 0.00001, 0.00000, 0.00000, \ + 0.06611, 0.05220, 0.04503, 0.02942, 0.01769, 0.01456, 0.00918, 0.00436, \ + 0.00373, 0.00102, 0.00063, 0.00016, 0.00004, 0.00001, 0.00000, 0.00000, \ + 0.06621, 0.05229, 0.04512, 0.02948, 0.01773, 0.01460, 0.00920, 0.00438, \ + 0.00374, 0.00103, 0.00063, 0.00016, 0.00004, 0.00001, 0.00000, 0.00000, \ + 0.06622, 0.05230, 0.04512, 0.02949, 0.01773, 0.01460, 0.00920, 0.00438, \ + 0.00374, 0.00103, 0.00063, 0.00016, 0.00004, 0.00001, 0.00000, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.03514, 0.03897, 0.04176, 0.05050, 0.06097, 0.06460, 0.07162, 0.07912, \ + 0.08020, 0.08486, 0.08545, 0.08641, 0.08655, 0.08667, 0.08671, 0.08671, \ + 0.03968, 0.04354, 0.04636, 0.05519, 0.06579, 0.06946, 0.07660, 0.08423, \ + 0.08533, 0.09009, 0.09070, 0.09168, 0.09182, 0.09194, 0.09197, 0.09197, \ + 0.05120, 0.05511, 0.05797, 0.06694, 0.07775, 0.08151, 0.08882, 0.09668, \ + 0.09782, 0.10274, 0.10339, 0.10441, 0.10456, 0.10468, 0.10469, 0.10469, \ + 0.08193, 0.08590, 0.08880, 0.09795, 0.10900, 0.11286, 0.12039, 0.12852, \ + 0.12969, 0.13482, 0.13550, 0.13656, 0.13673, 0.13685, 0.13685, 0.13685, \ + 0.08432, 0.08830, 0.09120, 0.10035, 0.11142, 0.11528, 0.12282, 0.13096, \ + 0.13213, 0.13727, 0.13795, 0.13901, 0.13918, 0.13930, 0.13931, 0.13930, \ + 0.13736, 0.14137, 0.14430, 0.15352, 0.16469, 0.16859, 0.17621, 0.18446, \ + 0.18565, 0.19087, 0.19156, 0.19264, 0.19281, 0.19293, 0.19293, 0.19293, \ + 0.23438, 0.23840, 0.24133, 0.25057, 0.26176, 0.26567, 0.27331, 0.28157, \ + 0.28277, 0.28800, 0.28870, 0.28977, 0.28995, 0.29007, 0.29007, 0.29007, \ + 0.38002, 0.38403, 0.38697, 0.39621, 0.40740, 0.41130, 0.41894, 0.42721, \ + 0.42840, 0.43364, 0.43433, 0.43541, 0.43558, 0.43571, 0.43571, 0.43571 "); + } + } + + capacitance () { + top_plane: metal4; + bottom_plane: poly; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.06630, 0.05320, 0.04654, 0.03214, 0.02122, 0.01821, 0.01276, 0.00729, \ + 0.00648, 0.00245, 0.00169, 0.00059, 0.00020, 0.00007, 0.00000, 0.00000, \ + 0.06757, 0.05431, 0.04754, 0.03287, 0.02172, 0.01864, 0.01306, 0.00745, \ + 0.00662, 0.00250, 0.00173, 0.00061, 0.00021, 0.00008, 0.00000, 0.00000, \ + 0.06972, 0.05619, 0.04925, 0.03414, 0.02256, 0.01936, 0.01357, 0.00774, \ + 0.00688, 0.00260, 0.00179, 0.00063, 0.00022, 0.00008, 0.00000, 0.00000, \ + 0.07220, 0.05837, 0.05124, 0.03560, 0.02355, 0.02020, 0.01415, 0.00807, \ + 0.00717, 0.00271, 0.00187, 0.00065, 0.00022, 0.00008, 0.00000, 0.00000, \ + 0.07230, 0.05846, 0.05132, 0.03566, 0.02359, 0.02024, 0.01418, 0.00808, \ + 0.00718, 0.00271, 0.00187, 0.00065, 0.00023, 0.00008, 0.00000, 0.00000, \ + 0.07323, 0.05927, 0.05205, 0.03620, 0.02395, 0.02054, 0.01439, 0.00820, \ + 0.00729, 0.00275, 0.00190, 0.00066, 0.00023, 0.00008, 0.00000, 0.00000, \ + 0.07338, 0.05941, 0.05218, 0.03630, 0.02401, 0.02060, 0.01443, 0.00822, \ + 0.00731, 0.00276, 0.00190, 0.00066, 0.00023, 0.00008, 0.00000, 0.00000, \ + 0.07339, 0.05942, 0.05219, 0.03630, 0.02401, 0.02060, 0.01443, 0.00822, \ + 0.00731, 0.00276, 0.00190, 0.00066, 0.00023, 0.00008, 0.00000, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.02044, 0.02252, 0.02405, 0.02912, 0.03596, 0.03860, 0.04439, 0.05200, \ + 0.05330, 0.06031, 0.06170, 0.06394, 0.06471, 0.06502, 0.06510, 0.06510, \ + 0.02251, 0.02460, 0.02615, 0.03131, 0.03827, 0.04097, 0.04690, 0.05467, \ + 0.05600, 0.06316, 0.06459, 0.06688, 0.06767, 0.06798, 0.06805, 0.06806, \ + 0.02784, 0.02998, 0.03157, 0.03689, 0.04413, 0.04693, 0.05308, 0.06115, \ + 0.06252, 0.06996, 0.07145, 0.07383, 0.07464, 0.07497, 0.07503, 0.07503, \ + 0.04273, 0.04497, 0.04664, 0.05221, 0.05979, 0.06272, 0.06915, 0.07756, \ + 0.07899, 0.08674, 0.08830, 0.09078, 0.09163, 0.09196, 0.09202, 0.09202, \ + 0.04392, 0.04617, 0.04783, 0.05342, 0.06101, 0.06394, 0.07039, 0.07882, \ + 0.08024, 0.08801, 0.08957, 0.09205, 0.09290, 0.09324, 0.09329, 0.09330, \ + 0.07074, 0.07304, 0.07474, 0.08044, 0.08817, 0.09115, 0.09770, 0.10625, \ + 0.10770, 0.11558, 0.11717, 0.11968, 0.12055, 0.12089, 0.12094, 0.12094, \ + 0.12038, 0.12269, 0.12440, 0.13012, 0.13787, 0.14086, 0.14743, 0.15600, \ + 0.15746, 0.16536, 0.16695, 0.16947, 0.17034, 0.17068, 0.17084, 0.17073, \ + 0.19498, 0.19729, 0.19900, 0.20472, 0.21247, 0.21546, 0.22203, 0.23061, \ + 0.23206, 0.23996, 0.24155, 0.24408, 0.24494, 0.24528, 0.24545, 0.24534 "); + } + } + + capacitance () { + top_plane: metal4; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.06738, 0.05437, 0.04779, 0.03363, 0.02297, 0.02004, 0.01469, 0.00915, \ + 0.00829, 0.00374, 0.00277, 0.00119, 0.00050, 0.00022, 0.00002, 0.00000, \ + 0.06877, 0.05561, 0.04893, 0.03449, 0.02360, 0.02059, 0.01510, 0.00940, \ + 0.00852, 0.00384, 0.00284, 0.00122, 0.00052, 0.00023, 0.00002, 0.00000, \ + 0.07127, 0.05784, 0.05098, 0.03608, 0.02473, 0.02159, 0.01584, 0.00986, \ + 0.00894, 0.00403, 0.00298, 0.00128, 0.00054, 0.00024, 0.00002, 0.00000, \ + 0.07455, 0.06080, 0.05371, 0.03822, 0.02627, 0.02294, 0.01685, 0.01049, \ + 0.00951, 0.00430, 0.00318, 0.00136, 0.00058, 0.00025, 0.00002, 0.00000, \ + 0.07471, 0.06093, 0.05384, 0.03832, 0.02634, 0.02301, 0.01689, 0.01052, \ + 0.00954, 0.00431, 0.00319, 0.00137, 0.00058, 0.00025, 0.00002, 0.00000, \ + 0.07639, 0.06245, 0.05525, 0.03943, 0.02716, 0.02372, 0.01743, 0.01085, \ + 0.00984, 0.00445, 0.00330, 0.00141, 0.00060, 0.00026, 0.00002, 0.00000, \ + 0.07691, 0.06293, 0.05570, 0.03979, 0.02742, 0.02396, 0.01760, 0.01097, \ + 0.00994, 0.00450, 0.00333, 0.00143, 0.00060, 0.00027, 0.00002, 0.00000, \ + 0.07698, 0.06300, 0.05576, 0.03984, 0.02746, 0.02399, 0.01763, 0.01098, \ + 0.00996, 0.00450, 0.00334, 0.00143, 0.00060, 0.00027, 0.00002, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.01756, 0.01930, 0.02057, 0.02469, 0.03024, 0.03241, 0.03729, 0.04408, \ + 0.04530, 0.05260, 0.05431, 0.05738, 0.05872, 0.05933, 0.05968, 0.05972, \ + 0.01923, 0.02094, 0.02220, 0.02636, 0.03200, 0.03421, 0.03921, 0.04616, \ + 0.04741, 0.05491, 0.05666, 0.05981, 0.06119, 0.06182, 0.06217, 0.06221, \ + 0.02336, 0.02508, 0.02634, 0.03059, 0.03644, 0.03875, 0.04395, 0.05122, \ + 0.05253, 0.06037, 0.06222, 0.06553, 0.06698, 0.06764, 0.06799, 0.06803, \ + 0.03474, 0.03651, 0.03783, 0.04228, 0.04846, 0.05089, 0.05641, 0.06412, \ + 0.06550, 0.07383, 0.07580, 0.07932, 0.08087, 0.08157, 0.08194, 0.08198, \ + 0.03565, 0.03743, 0.03875, 0.04321, 0.04940, 0.05184, 0.05738, 0.06511, \ + 0.06650, 0.07485, 0.07682, 0.08035, 0.08191, 0.08260, 0.08297, 0.08301, \ + 0.05644, 0.05827, 0.05963, 0.06424, 0.07061, 0.07313, 0.07884, 0.08680, \ + 0.08823, 0.09684, 0.09888, 0.10252, 0.10413, 0.10485, 0.10523, 0.10527, \ + 0.09557, 0.09743, 0.09880, 0.10345, 0.10990, 0.11244, 0.11820, 0.12624, \ + 0.12768, 0.13638, 0.13844, 0.14212, 0.14375, 0.14448, 0.14499, 0.14490, \ + 0.15471, 0.15657, 0.15795, 0.16260, 0.16906, 0.17160, 0.17737, 0.18542, \ + 0.18686, 0.19557, 0.19764, 0.20132, 0.20295, 0.20368, 0.20419, 0.20411 "); + } + } + + capacitance () { + top_plane: metal5; + bottom_plane: metal1; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.06308, 0.04983, 0.04311, 0.02869, 0.01815, 0.01537, 0.01056, 0.00608, \ + 0.00544, 0.00232, 0.00172, 0.00076, 0.00034, 0.00016, 0.00002, 0.00000, \ + 0.06408, 0.05072, 0.04393, 0.02934, 0.01864, 0.01582, 0.01091, 0.00631, \ + 0.00565, 0.00243, 0.00179, 0.00080, 0.00036, 0.00017, 0.00002, 0.00000, \ + 0.06586, 0.05234, 0.04545, 0.03059, 0.01962, 0.01670, 0.01161, 0.00678, \ + 0.00609, 0.00265, 0.00196, 0.00087, 0.00039, 0.00018, 0.00002, 0.00000, \ + 0.06856, 0.05486, 0.04784, 0.03263, 0.02125, 0.01820, 0.01282, 0.00761, \ + 0.00686, 0.00304, 0.00226, 0.00101, 0.00046, 0.00022, 0.00002, 0.00000, \ + 0.06872, 0.05500, 0.04797, 0.03274, 0.02135, 0.01829, 0.01289, 0.00766, \ + 0.00690, 0.00306, 0.00228, 0.00102, 0.00046, 0.00022, 0.00002, 0.00000, \ + 0.07086, 0.05702, 0.04991, 0.03442, 0.02272, 0.01955, 0.01392, 0.00838, \ + 0.00757, 0.00341, 0.00255, 0.00115, 0.00052, 0.00025, 0.00003, 0.00000, \ + 0.07222, 0.05832, 0.05115, 0.03551, 0.02363, 0.02038, 0.01460, 0.00887, \ + 0.00802, 0.00364, 0.00273, 0.00124, 0.00056, 0.00027, 0.00003, 0.00000, \ + 0.07266, 0.05874, 0.05156, 0.03586, 0.02392, 0.02065, 0.01482, 0.00902, \ + 0.00816, 0.00372, 0.00279, 0.00126, 0.00057, 0.00027, 0.00003, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.03195, 0.03536, 0.03783, 0.04543, 0.05437, 0.05747, 0.06358, 0.07057, \ + 0.07167, 0.07726, 0.07831, 0.08031, 0.08108, 0.08151, 0.08182, 0.08185, \ + 0.03599, 0.03939, 0.04185, 0.04945, 0.05844, 0.06157, 0.06777, 0.07492, \ + 0.07605, 0.08182, 0.08293, 0.08499, 0.08581, 0.08626, 0.08657, 0.08660, \ + 0.04602, 0.04939, 0.05183, 0.05943, 0.06852, 0.07171, 0.07808, 0.08552, \ + 0.08670, 0.09284, 0.09405, 0.09629, 0.09720, 0.09768, 0.09801, 0.09804, \ + 0.07211, 0.07545, 0.07788, 0.08550, 0.09475, 0.09803, 0.10468, 0.11261, \ + 0.11389, 0.12068, 0.12205, 0.12461, 0.12567, 0.12622, 0.12659, 0.12664, \ + 0.07412, 0.07746, 0.07990, 0.08752, 0.09678, 0.10006, 0.10673, 0.11469, \ + 0.11597, 0.12280, 0.12418, 0.12676, 0.12782, 0.12838, 0.12876, 0.12880, \ + 0.11872, 0.12207, 0.12452, 0.13220, 0.14163, 0.14501, 0.15192, 0.16029, \ + 0.16166, 0.16903, 0.17057, 0.17341, 0.17462, 0.17524, 0.17566, 0.17571, \ + 0.20093, 0.20431, 0.20677, 0.21453, 0.22408, 0.22753, 0.23460, 0.24326, \ + 0.24468, 0.25242, 0.25405, 0.25708, 0.25838, 0.25905, 0.25953, 0.25956, \ + 0.32528, 0.32866, 0.33114, 0.33892, 0.34852, 0.35199, 0.35912, 0.36786, \ + 0.36930, 0.37716, 0.37882, 0.38191, 0.38325, 0.38392, 0.38442, 0.38445 "); + } + } + + capacitance () { + top_plane: metal5; + bottom_plane: poly; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.06776, 0.05477, 0.04821, 0.03412, 0.02360, 0.02073, 0.01552, 0.01013, \ + 0.00930, 0.00472, 0.00368, 0.00186, 0.00094, 0.00050, 0.00007, 0.00000, \ + 0.06917, 0.05604, 0.04937, 0.03503, 0.02429, 0.02135, 0.01600, 0.01046, \ + 0.00960, 0.00488, 0.00381, 0.00193, 0.00098, 0.00052, 0.00007, 0.00000, \ + 0.07175, 0.05836, 0.05154, 0.03677, 0.02559, 0.02252, 0.01692, 0.01109, \ + 0.01018, 0.00520, 0.00406, 0.00206, 0.00104, 0.00055, 0.00008, 0.00000, \ + 0.07544, 0.06174, 0.05470, 0.03935, 0.02759, 0.02433, 0.01836, 0.01209, \ + 0.01111, 0.00572, 0.00448, 0.00227, 0.00116, 0.00061, 0.00009, 0.00000, \ + 0.07563, 0.06191, 0.05486, 0.03948, 0.02770, 0.02442, 0.01844, 0.01214, \ + 0.01116, 0.00574, 0.00450, 0.00229, 0.00116, 0.00061, 0.00009, 0.00000, \ + 0.07807, 0.06418, 0.05701, 0.04130, 0.02915, 0.02575, 0.01952, 0.01292, \ + 0.01189, 0.00616, 0.00483, 0.00246, 0.00126, 0.00066, 0.00010, 0.00000, \ + 0.07942, 0.06546, 0.05824, 0.04237, 0.03003, 0.02656, 0.02019, 0.01341, \ + 0.01234, 0.00642, 0.00504, 0.00258, 0.00132, 0.00070, 0.00010, 0.00000, \ + 0.07984, 0.06586, 0.05862, 0.04270, 0.03031, 0.02682, 0.02040, 0.01356, \ + 0.01249, 0.00650, 0.00511, 0.00261, 0.00133, 0.00071, 0.00011, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.01663, 0.01832, 0.01954, 0.02347, 0.02863, 0.03061, 0.03504, 0.04121, \ + 0.04233, 0.04927, 0.05101, 0.05440, 0.05617, 0.05710, 0.05790, 0.05804, \ + 0.01827, 0.01991, 0.02111, 0.02503, 0.03022, 0.03223, 0.03676, 0.04306, \ + 0.04421, 0.05135, 0.05315, 0.05664, 0.05847, 0.05943, 0.06025, 0.06040, \ + 0.02221, 0.02381, 0.02499, 0.02890, 0.03422, 0.03630, 0.04099, 0.04757, \ + 0.04878, 0.05628, 0.05819, 0.06190, 0.06385, 0.06487, 0.06574, 0.06590, \ + 0.03258, 0.03419, 0.03539, 0.03940, 0.04492, 0.04710, 0.05205, 0.05905, \ + 0.06034, 0.06843, 0.07051, 0.07458, 0.07673, 0.07785, 0.07881, 0.07900, \ + 0.03340, 0.03502, 0.03621, 0.04023, 0.04576, 0.04794, 0.05290, 0.05993, \ + 0.06123, 0.06935, 0.07144, 0.07552, 0.07768, 0.07881, 0.07978, 0.07996, \ + 0.05193, 0.05357, 0.05479, 0.05890, 0.06459, 0.06684, 0.07199, 0.07932, \ + 0.08068, 0.08924, 0.09147, 0.09583, 0.09815, 0.09937, 0.10042, 0.10061, \ + 0.08688, 0.08854, 0.08978, 0.09395, 0.09975, 0.10205, 0.10731, 0.11484, \ + 0.11623, 0.12508, 0.12738, 0.13192, 0.13435, 0.13562, 0.13684, 0.13692, \ + 0.14024, 0.14191, 0.14315, 0.14735, 0.15318, 0.15550, 0.16079, 0.16838, \ + 0.16979, 0.17872, 0.18106, 0.18565, 0.18811, 0.18940, 0.19064, 0.19072 "); + } + } + + capacitance () { + top_plane: metal5; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.06904, 0.05614, 0.04964, 0.03578, 0.02552, 0.02274, 0.01766, 0.01228, \ + 0.01142, 0.00646, 0.00524, 0.00294, 0.00164, 0.00094, 0.00017, 0.00000, \ + 0.07056, 0.05752, 0.05093, 0.03682, 0.02633, 0.02347, 0.01824, 0.01268, \ + 0.01180, 0.00668, 0.00542, 0.00305, 0.00170, 0.00097, 0.00018, 0.00000, \ + 0.07345, 0.06016, 0.05341, 0.03885, 0.02791, 0.02490, 0.01938, 0.01349, \ + 0.01254, 0.00711, 0.00577, 0.00323, 0.00180, 0.00103, 0.00019, 0.00000, \ + 0.07790, 0.06427, 0.05728, 0.04207, 0.03043, 0.02719, 0.02122, 0.01479, \ + 0.01376, 0.00781, 0.00634, 0.00355, 0.00198, 0.00114, 0.00021, 0.00000, \ + 0.07814, 0.06449, 0.05749, 0.04224, 0.03057, 0.02731, 0.02132, 0.01486, \ + 0.01382, 0.00785, 0.00637, 0.00357, 0.00199, 0.00114, 0.00021, 0.00000, \ + 0.08128, 0.06742, 0.06026, 0.04458, 0.03243, 0.02901, 0.02269, 0.01584, \ + 0.01474, 0.00838, 0.00681, 0.00382, 0.00213, 0.00123, 0.00023, 0.00000, \ + 0.08297, 0.06900, 0.06178, 0.04588, 0.03348, 0.02998, 0.02347, 0.01641, \ + 0.01527, 0.00869, 0.00707, 0.00397, 0.00222, 0.00128, 0.00024, 0.00000, \ + 0.08344, 0.06945, 0.06220, 0.04625, 0.03378, 0.03025, 0.02370, 0.01657, \ + 0.01542, 0.00878, 0.00714, 0.00401, 0.00224, 0.00129, 0.00025, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.01328, 0.01463, 0.01559, 0.01861, 0.02249, 0.02398, 0.02739, 0.03240, \ + 0.03336, 0.03990, 0.04176, 0.04572, 0.04811, 0.04950, 0.05097, 0.05133, \ + 0.01454, 0.01581, 0.01673, 0.01967, 0.02354, 0.02505, 0.02852, 0.03366, \ + 0.03465, 0.04138, 0.04330, 0.04737, 0.04985, 0.05128, 0.05280, 0.05317, \ + 0.01737, 0.01855, 0.01941, 0.02226, 0.02617, 0.02772, 0.03133, 0.03673, \ + 0.03777, 0.04488, 0.04692, 0.05126, 0.05389, 0.05540, 0.05701, 0.05740, \ + 0.02435, 0.02549, 0.02635, 0.02923, 0.03331, 0.03495, 0.03882, 0.04465, \ + 0.04578, 0.05352, 0.05575, 0.06049, 0.06338, 0.06504, 0.06681, 0.06724, \ + 0.02490, 0.02604, 0.02690, 0.02979, 0.03388, 0.03553, 0.03941, 0.04527, \ + 0.04640, 0.05417, 0.05641, 0.06117, 0.06408, 0.06575, 0.06752, 0.06796, \ + 0.03750, 0.03868, 0.03956, 0.04257, 0.04684, 0.04858, 0.05268, 0.05887, \ + 0.06008, 0.06832, 0.07070, 0.07578, 0.07888, 0.08067, 0.08257, 0.08304, \ + 0.06203, 0.06325, 0.06415, 0.06724, 0.07164, 0.07344, 0.07766, 0.08406, \ + 0.08530, 0.09382, 0.09629, 0.10155, 0.10477, 0.10662, 0.10872, 0.10909, \ + 0.09996, 0.10118, 0.10209, 0.10521, 0.10965, 0.11146, 0.11572, 0.12217, \ + 0.12343, 0.13203, 0.13452, 0.13983, 0.14308, 0.14496, 0.14708, 0.14745 "); + } + } + + capacitance () { + top_plane: metal6; + bottom_plane: metal1; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.06338, 0.05014, 0.04343, 0.02905, 0.01857, 0.01583, 0.01108, 0.00665, \ + 0.00602, 0.00287, 0.00223, 0.00116, 0.00063, 0.00036, 0.00007, 0.00000, \ + 0.06439, 0.05105, 0.04427, 0.02973, 0.01911, 0.01632, 0.01147, 0.00693, \ + 0.00628, 0.00302, 0.00235, 0.00123, 0.00067, 0.00038, 0.00008, 0.00000, \ + 0.06622, 0.05273, 0.04585, 0.03107, 0.02019, 0.01731, 0.01230, 0.00753, \ + 0.00684, 0.00334, 0.00261, 0.00137, 0.00075, 0.00043, 0.00009, 0.00000, \ + 0.06919, 0.05552, 0.04853, 0.03341, 0.02215, 0.01914, 0.01383, 0.00867, \ + 0.00792, 0.00399, 0.00314, 0.00168, 0.00092, 0.00054, 0.00011, 0.00000, \ + 0.06936, 0.05569, 0.04868, 0.03355, 0.02227, 0.01925, 0.01393, 0.00874, \ + 0.00798, 0.00403, 0.00318, 0.00170, 0.00094, 0.00054, 0.00011, 0.00000, \ + 0.07207, 0.05827, 0.05119, 0.03579, 0.02421, 0.02107, 0.01549, 0.00995, \ + 0.00912, 0.00473, 0.00376, 0.00204, 0.00114, 0.00066, 0.00013, 0.00000, \ + 0.07436, 0.06048, 0.05334, 0.03776, 0.02593, 0.02270, 0.01691, 0.01106, \ + 0.01017, 0.00541, 0.00433, 0.00238, 0.00134, 0.00078, 0.00016, 0.00000, \ + 0.07558, 0.06166, 0.05449, 0.03882, 0.02686, 0.02358, 0.01768, 0.01167, \ + 0.01075, 0.00578, 0.00464, 0.00257, 0.00145, 0.00085, 0.00018, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.03119, 0.03456, 0.03699, 0.04444, 0.05315, 0.05615, 0.06203, 0.06877, \ + 0.06983, 0.07535, 0.07644, 0.07861, 0.07960, 0.08020, 0.08081, 0.08095, \ + 0.03519, 0.03854, 0.04095, 0.04838, 0.05710, 0.06012, 0.06608, 0.07295, \ + 0.07404, 0.07974, 0.08089, 0.08315, 0.08420, 0.08483, 0.08546, 0.08561, \ + 0.04506, 0.04835, 0.05073, 0.05809, 0.06684, 0.06989, 0.07598, 0.08312, \ + 0.08426, 0.09034, 0.09160, 0.09409, 0.09526, 0.09596, 0.09665, 0.09682, \ + 0.07037, 0.07359, 0.07593, 0.08322, 0.09202, 0.09514, 0.10146, 0.10905, \ + 0.11029, 0.11706, 0.11853, 0.12144, 0.12286, 0.12370, 0.12455, 0.12477, \ + 0.07231, 0.07553, 0.07787, 0.08515, 0.09396, 0.09708, 0.10342, 0.11103, \ + 0.11228, 0.11910, 0.12058, 0.12351, 0.12495, 0.12580, 0.12666, 0.12688, \ + 0.11505, 0.11825, 0.12057, 0.12785, 0.13676, 0.13995, 0.14650, 0.15455, \ + 0.15589, 0.16340, 0.16509, 0.16847, 0.17020, 0.17121, 0.17226, 0.17254, \ + 0.19335, 0.19655, 0.19888, 0.20621, 0.21523, 0.21849, 0.22524, 0.23368, \ + 0.23511, 0.24324, 0.24513, 0.24893, 0.25093, 0.25210, 0.25336, 0.25366, \ + 0.31191, 0.31512, 0.31746, 0.32483, 0.33394, 0.33724, 0.34411, 0.35276, \ + 0.35423, 0.36270, 0.36469, 0.36872, 0.37087, 0.37213, 0.37351, 0.37383 "); + } + } + + capacitance () { + top_plane: metal6; + bottom_plane: poly; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.06818, 0.05520, 0.04864, 0.03459, 0.02415, 0.02131, 0.01619, 0.01091, \ + 0.01010, 0.00557, 0.00451, 0.00258, 0.00150, 0.00092, 0.00021, 0.00000, \ + 0.06960, 0.05647, 0.04982, 0.03553, 0.02487, 0.02197, 0.01671, 0.01129, \ + 0.01045, 0.00578, 0.00468, 0.00269, 0.00157, 0.00096, 0.00022, 0.00000, \ + 0.07221, 0.05885, 0.05204, 0.03734, 0.02628, 0.02325, 0.01776, 0.01205, \ + 0.01116, 0.00622, 0.00505, 0.00290, 0.00170, 0.00104, 0.00024, 0.00000, \ + 0.07615, 0.06249, 0.05548, 0.04022, 0.02860, 0.02539, 0.01953, 0.01338, \ + 0.01242, 0.00702, 0.00573, 0.00332, 0.00196, 0.00120, 0.00029, 0.00000, \ + 0.07636, 0.06269, 0.05566, 0.04038, 0.02873, 0.02551, 0.01963, 0.01346, \ + 0.01249, 0.00707, 0.00577, 0.00335, 0.00198, 0.00121, 0.00029, 0.00000, \ + 0.07936, 0.06551, 0.05837, 0.04276, 0.03074, 0.02739, 0.02124, 0.01472, \ + 0.01369, 0.00786, 0.00645, 0.00377, 0.00224, 0.00138, 0.00033, 0.00000, \ + 0.08161, 0.06768, 0.06048, 0.04468, 0.03241, 0.02897, 0.02262, 0.01583, \ + 0.01475, 0.00857, 0.00706, 0.00417, 0.00249, 0.00154, 0.00038, 0.00000, \ + 0.08278, 0.06881, 0.06158, 0.04568, 0.03330, 0.02981, 0.02336, 0.01642, \ + 0.01531, 0.00895, 0.00739, 0.00438, 0.00263, 0.00163, 0.00040, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.01560, 0.01724, 0.01842, 0.02221, 0.02712, 0.02898, 0.03311, 0.03881, \ + 0.03985, 0.04638, 0.04807, 0.05153, 0.05353, 0.05471, 0.05605, 0.05649, \ + 0.01721, 0.01880, 0.01995, 0.02370, 0.02860, 0.03048, 0.03467, 0.04048, \ + 0.04155, 0.04825, 0.05001, 0.05357, 0.05565, 0.05687, 0.05827, 0.05873, \ + 0.02102, 0.02254, 0.02366, 0.02733, 0.03227, 0.03419, 0.03849, 0.04453, \ + 0.04564, 0.05269, 0.05455, 0.05837, 0.06061, 0.06193, 0.06343, 0.06394, \ + 0.03066, 0.03214, 0.03324, 0.03691, 0.04194, 0.04391, 0.04840, 0.05479, \ + 0.05597, 0.06359, 0.06565, 0.06989, 0.07242, 0.07392, 0.07566, 0.07625, \ + 0.03141, 0.03289, 0.03399, 0.03766, 0.04269, 0.04467, 0.04917, 0.05558, \ + 0.05676, 0.06442, 0.06648, 0.07075, 0.07330, 0.07481, 0.07656, 0.07715, \ + 0.04809, 0.04957, 0.05067, 0.05436, 0.05947, 0.06150, 0.06614, 0.07283, \ + 0.07408, 0.08224, 0.08448, 0.08916, 0.09200, 0.09370, 0.09570, 0.09638, \ + 0.07918, 0.08067, 0.08178, 0.08551, 0.09070, 0.09277, 0.09753, 0.10447, \ + 0.10577, 0.11438, 0.11677, 0.12182, 0.12492, 0.12679, 0.12914, 0.12979, \ + 0.12682, 0.12832, 0.12944, 0.13320, 0.13845, 0.14055, 0.14538, 0.15246, \ + 0.15379, 0.16265, 0.16512, 0.17036, 0.17361, 0.17557, 0.17805, 0.17874 "); + } + } + + capacitance () { + top_plane: metal6; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.06953, 0.05666, 0.05017, 0.03635, 0.02616, 0.02340, 0.01841, 0.01316, \ + 0.01233, 0.00748, 0.00625, 0.00387, 0.00241, 0.00155, 0.00042, 0.00000, \ + 0.07107, 0.05805, 0.05147, 0.03740, 0.02700, 0.02417, 0.01904, 0.01362, \ + 0.01276, 0.00775, 0.00648, 0.00402, 0.00251, 0.00162, 0.00044, 0.00000, \ + 0.07400, 0.06074, 0.05400, 0.03951, 0.02868, 0.02571, 0.02030, 0.01456, \ + 0.01364, 0.00831, 0.00696, 0.00431, 0.00269, 0.00174, 0.00047, 0.00000, \ + 0.07868, 0.06509, 0.05812, 0.04301, 0.03151, 0.02832, 0.02247, 0.01619, \ + 0.01518, 0.00929, 0.00780, 0.00485, 0.00304, 0.00197, 0.00054, 0.00000, \ + 0.07894, 0.06533, 0.05835, 0.04321, 0.03167, 0.02847, 0.02259, 0.01628, \ + 0.01527, 0.00935, 0.00785, 0.00488, 0.00306, 0.00198, 0.00054, 0.00000, \ + 0.08263, 0.06880, 0.06168, 0.04610, 0.03407, 0.03070, 0.02448, 0.01774, \ + 0.01665, 0.01027, 0.00864, 0.00540, 0.00340, 0.00221, 0.00061, 0.00000, \ + 0.08519, 0.07126, 0.06405, 0.04822, 0.03590, 0.03242, 0.02596, 0.01892, \ + 0.01777, 0.01103, 0.00930, 0.00584, 0.00369, 0.00240, 0.00067, 0.00000, \ + 0.08639, 0.07241, 0.06517, 0.04924, 0.03678, 0.03326, 0.02670, 0.01951, \ + 0.01834, 0.01142, 0.00964, 0.00606, 0.00384, 0.00250, 0.00070, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.01204, 0.01332, 0.01424, 0.01711, 0.02075, 0.02213, 0.02522, 0.02971, \ + 0.03057, 0.03649, 0.03823, 0.04208, 0.04464, 0.04627, 0.04843, 0.04929, \ + 0.01326, 0.01447, 0.01534, 0.01812, 0.02170, 0.02308, 0.02620, 0.03078, \ + 0.03166, 0.03775, 0.03955, 0.04351, 0.04616, 0.04785, 0.05009, 0.05099, \ + 0.01597, 0.01707, 0.01787, 0.02050, 0.02403, 0.02542, 0.02862, 0.03339, \ + 0.03432, 0.04073, 0.04264, 0.04689, 0.04971, 0.05152, 0.05391, 0.05488, \ + 0.02227, 0.02329, 0.02405, 0.02659, 0.03017, 0.03160, 0.03497, 0.04009, \ + 0.04108, 0.04807, 0.05017, 0.05486, 0.05802, 0.06004, 0.06274, 0.06384, \ + 0.02275, 0.02377, 0.02452, 0.02707, 0.03065, 0.03209, 0.03547, 0.04060, \ + 0.04161, 0.04862, 0.05073, 0.05545, 0.05863, 0.06066, 0.06338, 0.06449, \ + 0.03355, 0.03457, 0.03533, 0.03792, 0.04160, 0.04310, 0.04665, 0.05207, \ + 0.05314, 0.06065, 0.06293, 0.06805, 0.07153, 0.07377, 0.07679, 0.07804, \ + 0.05427, 0.05531, 0.05608, 0.05873, 0.06252, 0.06406, 0.06773, 0.07338, \ + 0.07450, 0.08241, 0.08482, 0.09028, 0.09401, 0.09643, 0.09983, 0.10107, \ + 0.08652, 0.08757, 0.08835, 0.09103, 0.09488, 0.09645, 0.10019, 0.10596, \ + 0.10710, 0.11520, 0.11769, 0.12332, 0.12718, 0.12968, 0.13322, 0.13453 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: metal1; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.06394, 0.05072, 0.04402, 0.02969, 0.01924, 0.01650, 0.01176, 0.00734, \ + 0.00671, 0.00354, 0.00289, 0.00177, 0.00117, 0.00084, 0.00039, 0.00000, \ + 0.06496, 0.05164, 0.04488, 0.03038, 0.01980, 0.01702, 0.01220, 0.00767, \ + 0.00702, 0.00375, 0.00306, 0.00189, 0.00126, 0.00090, 0.00042, 0.00000, \ + 0.06684, 0.05337, 0.04651, 0.03178, 0.02096, 0.01810, 0.01313, 0.00839, \ + 0.00770, 0.00421, 0.00346, 0.00216, 0.00145, 0.00105, 0.00050, 0.00000, \ + 0.06997, 0.05634, 0.04936, 0.03432, 0.02317, 0.02020, 0.01496, 0.00988, \ + 0.00913, 0.00521, 0.00435, 0.00279, 0.00192, 0.00142, 0.00069, 0.00000, \ + 0.07017, 0.05652, 0.04954, 0.03448, 0.02331, 0.02033, 0.01508, 0.00998, \ + 0.00922, 0.00528, 0.00441, 0.00284, 0.00196, 0.00145, 0.00071, 0.00000, \ + 0.07336, 0.05961, 0.05255, 0.03727, 0.02583, 0.02274, 0.01726, 0.01182, \ + 0.01101, 0.00662, 0.00562, 0.00376, 0.00267, 0.00202, 0.00103, 0.00000, \ + 0.07687, 0.06305, 0.05595, 0.04049, 0.02883, 0.02566, 0.01997, 0.01422, \ + 0.01334, 0.00850, 0.00735, 0.00515, 0.00380, 0.00296, 0.00162, 0.00000, \ + 0.08012, 0.06625, 0.05912, 0.04357, 0.03176, 0.02853, 0.02270, 0.01672, \ + 0.01579, 0.01059, 0.00932, 0.00681, 0.00521, 0.00418, 0.00245, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.02976, 0.03305, 0.03543, 0.04273, 0.05130, 0.05425, 0.06005, 0.06672, \ + 0.06778, 0.07329, 0.07440, 0.07665, 0.07776, 0.07848, 0.07942, 0.08020, \ + 0.03372, 0.03698, 0.03934, 0.04662, 0.05517, 0.05813, 0.06399, 0.07075, \ + 0.07183, 0.07750, 0.07867, 0.08101, 0.08219, 0.08295, 0.08394, 0.08479, \ + 0.04345, 0.04666, 0.04898, 0.05616, 0.06469, 0.06766, 0.07359, 0.08055, \ + 0.08167, 0.08767, 0.08895, 0.09152, 0.09284, 0.09369, 0.09480, 0.09581, \ + 0.06826, 0.07138, 0.07364, 0.08067, 0.08912, 0.09211, 0.09815, 0.10543, \ + 0.10662, 0.11322, 0.11469, 0.11770, 0.11933, 0.12038, 0.12183, 0.12323, \ + 0.07016, 0.07327, 0.07553, 0.08255, 0.09100, 0.09398, 0.10003, 0.10733, \ + 0.10852, 0.11516, 0.11664, 0.11968, 0.12133, 0.12240, 0.12387, 0.12530, \ + 0.11144, 0.11449, 0.11670, 0.12361, 0.13201, 0.13501, 0.14116, 0.14874, \ + 0.15001, 0.15726, 0.15896, 0.16250, 0.16453, 0.16586, 0.16780, 0.16989, \ + 0.18584, 0.18884, 0.19103, 0.19786, 0.20622, 0.20923, 0.21547, 0.22332, \ + 0.22466, 0.23253, 0.23446, 0.23858, 0.24108, 0.24277, 0.24541, 0.24864, \ + 0.29695, 0.29993, 0.30210, 0.30889, 0.31722, 0.32024, 0.32653, 0.33458, \ + 0.33597, 0.34432, 0.34644, 0.35106, 0.35400, 0.35604, 0.35943, 0.36430 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: poly; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.06899, 0.05604, 0.04951, 0.03551, 0.02512, 0.02230, 0.01721, 0.01198, \ + 0.01118, 0.00671, 0.00565, 0.00370, 0.00256, 0.00188, 0.00090, 0.00000, \ + 0.07043, 0.05734, 0.05070, 0.03646, 0.02586, 0.02298, 0.01777, 0.01241, \ + 0.01158, 0.00699, 0.00590, 0.00389, 0.00269, 0.00199, 0.00096, 0.00000, \ + 0.07309, 0.05975, 0.05296, 0.03832, 0.02734, 0.02434, 0.01891, 0.01330, \ + 0.01243, 0.00759, 0.00643, 0.00426, 0.00298, 0.00221, 0.00108, 0.00000, \ + 0.07718, 0.06355, 0.05656, 0.04139, 0.02989, 0.02673, 0.02098, 0.01499, \ + 0.01406, 0.00879, 0.00752, 0.00509, 0.00362, 0.00273, 0.00137, 0.00000, \ + 0.07741, 0.06376, 0.05677, 0.04157, 0.03005, 0.02687, 0.02111, 0.01510, \ + 0.01416, 0.00887, 0.00760, 0.00515, 0.00367, 0.00277, 0.00139, 0.00000, \ + 0.08089, 0.06709, 0.05998, 0.04449, 0.03263, 0.02935, 0.02335, 0.01703, \ + 0.01603, 0.01036, 0.00897, 0.00624, 0.00455, 0.00350, 0.00184, 0.00000, \ + 0.08437, 0.07050, 0.06334, 0.04766, 0.03559, 0.03222, 0.02604, 0.01945, \ + 0.01840, 0.01235, 0.01083, 0.00780, 0.00586, 0.00461, 0.00257, 0.00000, \ + 0.08756, 0.07364, 0.06644, 0.05067, 0.03846, 0.03504, 0.02873, 0.02195, \ + 0.02086, 0.01451, 0.01288, 0.00958, 0.00742, 0.00598, 0.00354, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.01357, 0.01510, 0.01621, 0.01980, 0.02451, 0.02630, 0.03028, 0.03574, \ + 0.03673, 0.04295, 0.04458, 0.04796, 0.05002, 0.05133, 0.05319, 0.05501, \ + 0.01512, 0.01661, 0.01770, 0.02125, 0.02593, 0.02773, 0.03173, 0.03726, \ + 0.03826, 0.04461, 0.04629, 0.04975, 0.05190, 0.05326, 0.05521, 0.05714, \ + 0.01880, 0.02024, 0.02129, 0.02476, 0.02942, 0.03123, 0.03526, 0.04091, \ + 0.04195, 0.04854, 0.05030, 0.05400, 0.05629, 0.05776, 0.05989, 0.06206, \ + 0.02799, 0.02937, 0.03039, 0.03377, 0.03839, 0.04019, 0.04428, 0.05008, \ + 0.05115, 0.05811, 0.06002, 0.06408, 0.06668, 0.06836, 0.07089, 0.07365, \ + 0.02869, 0.03007, 0.03108, 0.03446, 0.03907, 0.04088, 0.04497, 0.05077, \ + 0.05185, 0.05883, 0.06074, 0.06483, 0.06744, 0.06914, 0.07170, 0.07450, \ + 0.04394, 0.04527, 0.04625, 0.04955, 0.05408, 0.05587, 0.05996, 0.06585, \ + 0.06695, 0.07424, 0.07629, 0.08074, 0.08369, 0.08565, 0.08872, 0.09239, \ + 0.07113, 0.07242, 0.07338, 0.07659, 0.08104, 0.08281, 0.08687, 0.09282, \ + 0.09394, 0.10152, 0.10371, 0.10855, 0.11188, 0.11416, 0.11802, 0.12301, \ + 0.11135, 0.11262, 0.11356, 0.11671, 0.12110, 0.12286, 0.12690, 0.13288, \ + 0.13403, 0.14182, 0.14412, 0.14930, 0.15296, 0.15553, 0.16011, 0.16698 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.07053, 0.05771, 0.05126, 0.03751, 0.02739, 0.02465, 0.01969, 0.01451, \ + 0.01369, 0.00894, 0.00775, 0.00539, 0.00389, 0.00295, 0.00149, 0.00000, \ + 0.07211, 0.05913, 0.05258, 0.03859, 0.02825, 0.02544, 0.02036, 0.01502, \ + 0.01418, 0.00929, 0.00805, 0.00562, 0.00407, 0.00310, 0.00156, 0.00000, \ + 0.07510, 0.06187, 0.05515, 0.04073, 0.02998, 0.02704, 0.02171, 0.01609, \ + 0.01519, 0.01001, 0.00870, 0.00610, 0.00444, 0.00339, 0.00173, 0.00000, \ + 0.07992, 0.06636, 0.05943, 0.04440, 0.03303, 0.02989, 0.02416, 0.01807, \ + 0.01710, 0.01143, 0.00999, 0.00709, 0.00523, 0.00404, 0.00211, 0.00000, \ + 0.08019, 0.06662, 0.05967, 0.04462, 0.03321, 0.03006, 0.02431, 0.01819, \ + 0.01721, 0.01152, 0.01007, 0.00716, 0.00528, 0.00408, 0.00214, 0.00000, \ + 0.08435, 0.07057, 0.06348, 0.04802, 0.03617, 0.03288, 0.02682, 0.02032, \ + 0.01928, 0.01316, 0.01159, 0.00839, 0.00630, 0.00494, 0.00268, 0.00000, \ + 0.08814, 0.07426, 0.06710, 0.05141, 0.03928, 0.03588, 0.02960, 0.02281, \ + 0.02171, 0.01522, 0.01353, 0.01004, 0.00772, 0.00617, 0.00353, 0.00000, \ + 0.09134, 0.07741, 0.07021, 0.05441, 0.04214, 0.03868, 0.03228, 0.02530, \ + 0.02417, 0.01740, 0.01561, 0.01188, 0.00935, 0.00763, 0.00460, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0700, 0.0900, 0.1050, 0.1575, 0.2363, 0.2700, 0.3544, 0.5000, \ + 0.5316, 0.7973, 0.9000, 1.1960, 1.5000, 1.7940, 2.6910, 269.1035 "); + values (" 0.00956, 0.01068, 0.01149, 0.01409, 0.01749, 0.01878, 0.02170, 0.02590, \ + 0.02670, 0.03214, 0.03374, 0.03731, 0.03978, 0.04147, 0.04416, 0.04711, \ + 0.01068, 0.01175, 0.01253, 0.01506, 0.01839, 0.01967, 0.02259, 0.02683, \ + 0.02764, 0.03318, 0.03482, 0.03846, 0.04102, 0.04276, 0.04555, 0.04866, \ + 0.01322, 0.01421, 0.01493, 0.01732, 0.02056, 0.02184, 0.02475, 0.02906, \ + 0.02990, 0.03562, 0.03734, 0.04120, 0.04391, 0.04576, 0.04877, 0.05219, \ + 0.01909, 0.02000, 0.02067, 0.02293, 0.02607, 0.02733, 0.03027, 0.03468, \ + 0.03554, 0.04157, 0.04340, 0.04759, 0.05058, 0.05266, 0.05610, 0.06027, \ + 0.01953, 0.02043, 0.02110, 0.02335, 0.02649, 0.02775, 0.03069, 0.03511, \ + 0.03597, 0.04201, 0.04385, 0.04806, 0.05107, 0.05316, 0.05663, 0.06085, \ + 0.02894, 0.02981, 0.03045, 0.03264, 0.03572, 0.03697, 0.03991, 0.04440, \ + 0.04528, 0.05155, 0.05349, 0.05799, 0.06127, 0.06360, 0.06759, 0.07285, \ + 0.04579, 0.04663, 0.04725, 0.04937, 0.05239, 0.05362, 0.05653, 0.06103, \ + 0.06193, 0.06835, 0.07038, 0.07515, 0.07872, 0.08131, 0.08603, 0.09280, \ + 0.07066, 0.07147, 0.07208, 0.07415, 0.07710, 0.07831, 0.08119, 0.08567, \ + 0.08657, 0.09309, 0.09518, 0.10016, 0.10398, 0.10680, 0.11213, 0.12093 "); + } + } + } + + layer (metal1) { + resistance: 0.380000 + + capacitance () { + top_plane: metal2; + bottom_plane: poly; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0650, 0.0900, 0.0975, 0.1462, 0.2194, 0.2700, 0.3291, 0.4936, \ + 0.5000, 0.7404, 0.9000, 1.1106, 1.5000, 1.6659, 2.4988, 249.8818 "); + values (" 0.05612, 0.03899, 0.03546, 0.02048, 0.00993, 0.00618, 0.00357, 0.00081, \ + 0.00076, 0.00009, 0.00002, 0.00000, 0.00000, 0.00000, 0.00000, 0.00000, \ + 0.05637, 0.03916, 0.03562, 0.02056, 0.00997, 0.00621, 0.00358, 0.00081, \ + 0.00076, 0.00009, 0.00002, 0.00000, 0.00000, 0.00000, 0.00000, 0.00000, \ + 0.05658, 0.03931, 0.03575, 0.02064, 0.01001, 0.00623, 0.00360, 0.00082, \ + 0.00076, 0.00009, 0.00002, 0.00000, 0.00000, 0.00000, 0.00000, 0.00000, \ + 0.05663, 0.03935, 0.03579, 0.02066, 0.01002, 0.00624, 0.00360, 0.00082, \ + 0.00076, 0.00009, 0.00002, 0.00000, 0.00000, 0.00000, 0.00000, 0.00000, \ + 0.05664, 0.03935, 0.03579, 0.02066, 0.01002, 0.00624, 0.00360, 0.00082, \ + 0.00076, 0.00009, 0.00002, 0.00000, 0.00000, 0.00000, 0.00000, 0.00000, \ + 0.05662, 0.03934, 0.03578, 0.02066, 0.01002, 0.00624, 0.00360, 0.00082, \ + 0.00076, 0.00009, 0.00002, 0.00000, 0.00000, 0.00000, 0.00000, 0.00000, \ + 0.05664, 0.03935, 0.03579, 0.02066, 0.01002, 0.00624, 0.00360, 0.00082, \ + 0.00076, 0.00009, 0.00002, 0.00000, 0.00000, 0.00000, 0.00000, 0.00000, \ + 0.05664, 0.03935, 0.03579, 0.02066, 0.01002, 0.00624, 0.00360, 0.00082, \ + 0.00076, 0.00009, 0.00002, 0.00000, 0.00000, 0.00000, 0.00000, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0650, 0.0900, 0.0975, 0.1462, 0.2194, 0.2700, 0.3291, 0.4936, \ + 0.5000, 0.7404, 0.9000, 1.1106, 1.5000, 1.6659, 2.4988, 249.8818 "); + values (" 0.05792, 0.06622, 0.06861, 0.08193, 0.09595, 0.10228, 0.10687, 0.11258, \ + 0.11239, 0.11402, 0.11399, 0.11416, 0.11407, 0.11413, 0.11430, 0.11429, \ + 0.06672, 0.07508, 0.07748, 0.09087, 0.10496, 0.11131, 0.11592, 0.12165, \ + 0.12147, 0.12310, 0.12308, 0.12325, 0.12315, 0.12321, 0.12337, 0.12336, \ + 0.08881, 0.09723, 0.09964, 0.11310, 0.12724, 0.13362, 0.13824, 0.14399, \ + 0.14381, 0.14545, 0.14542, 0.14559, 0.14550, 0.14556, 0.14571, 0.14571, \ + 0.14658, 0.15501, 0.15742, 0.17090, 0.18505, 0.19144, 0.19607, 0.20182, \ + 0.20164, 0.20328, 0.20326, 0.20343, 0.20333, 0.20339, 0.20355, 0.20355, \ + 0.15102, 0.15946, 0.16187, 0.17535, 0.18951, 0.19589, 0.20052, 0.20627, \ + 0.20609, 0.20774, 0.20771, 0.20788, 0.20778, 0.20785, 0.20801, 0.20800, \ + 0.24891, 0.25735, 0.25976, 0.27323, 0.28739, 0.29378, 0.29840, 0.30416, \ + 0.30397, 0.30562, 0.30559, 0.30576, 0.30567, 0.30573, 0.30589, 0.30588, \ + 0.42687, 0.43531, 0.43772, 0.45120, 0.46536, 0.47174, 0.47637, 0.48212, \ + 0.48194, 0.48358, 0.48356, 0.48373, 0.48364, 0.48369, 0.48366, 0.48385, \ + 0.69381, 0.70225, 0.70467, 0.71814, 0.73230, 0.73869, 0.74332, 0.74907, \ + 0.74889, 0.75053, 0.75051, 0.75068, 0.75058, 0.75064, 0.75061, 0.75080 "); + } + } + + capacitance () { + top_plane: metal2; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0650, 0.0900, 0.0975, 0.1462, 0.2194, 0.2700, 0.3291, 0.4936, \ + 0.5000, 0.7404, 0.9000, 1.1106, 1.5000, 1.6659, 2.4988, 249.8818 "); + values (" 0.06204, 0.04523, 0.04177, 0.02694, 0.01592, 0.01154, 0.00805, 0.00316, \ + 0.00304, 0.00083, 0.00036, 0.00012, 0.00002, 0.00001, 0.00000, 0.00000, \ + 0.06285, 0.04588, 0.04238, 0.02737, 0.01620, 0.01175, 0.00821, 0.00323, \ + 0.00311, 0.00085, 0.00037, 0.00013, 0.00002, 0.00001, 0.00000, 0.00000, \ + 0.06406, 0.04687, 0.04332, 0.02807, 0.01666, 0.01210, 0.00847, 0.00335, \ + 0.00322, 0.00088, 0.00038, 0.00013, 0.00002, 0.00001, 0.00000, 0.00000, \ + 0.06530, 0.04793, 0.04433, 0.02882, 0.01717, 0.01250, 0.00877, 0.00348, \ + 0.00334, 0.00092, 0.00040, 0.00014, 0.00002, 0.00001, 0.00000, 0.00000, \ + 0.06536, 0.04798, 0.04438, 0.02885, 0.01719, 0.01251, 0.00878, 0.00348, \ + 0.00335, 0.00092, 0.00040, 0.00014, 0.00002, 0.00001, 0.00000, 0.00000, \ + 0.06580, 0.04836, 0.04474, 0.02913, 0.01738, 0.01266, 0.00889, 0.00353, \ + 0.00340, 0.00094, 0.00041, 0.00014, 0.00002, 0.00001, 0.00000, 0.00000, \ + 0.06590, 0.04845, 0.04482, 0.02919, 0.01742, 0.01269, 0.00891, 0.00354, \ + 0.00341, 0.00094, 0.00041, 0.00014, 0.00002, 0.00001, 0.00000, 0.00000, \ + 0.06591, 0.04845, 0.04483, 0.02920, 0.01743, 0.01269, 0.00892, 0.00354, \ + 0.00341, 0.00094, 0.00041, 0.00014, 0.00002, 0.00001, 0.00000, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0650, 0.0900, 0.0975, 0.1462, 0.2194, 0.2700, 0.3291, 0.4936, \ + 0.5000, 0.7404, 0.9000, 1.1106, 1.5000, 1.6659, 2.4988, 249.8818 "); + values (" 0.03600, 0.04115, 0.04265, 0.05152, 0.06222, 0.06798, 0.07309, 0.08169, \ + 0.08175, 0.08622, 0.08709, 0.08766, 0.08783, 0.08789, 0.08792, 0.08791, \ + 0.04085, 0.04606, 0.04758, 0.05654, 0.06738, 0.07321, 0.07840, 0.08715, \ + 0.08721, 0.09176, 0.09266, 0.09324, 0.09342, 0.09348, 0.09349, 0.09349, \ + 0.05319, 0.05848, 0.06002, 0.06912, 0.08016, 0.08611, 0.09143, 0.10043, \ + 0.10050, 0.10520, 0.10613, 0.10674, 0.10692, 0.10698, 0.10698, 0.10698, \ + 0.08609, 0.09145, 0.09302, 0.10227, 0.11353, 0.11962, 0.12508, 0.13435, \ + 0.13444, 0.13931, 0.14029, 0.14092, 0.14111, 0.14117, 0.14116, 0.14116, \ + 0.08864, 0.09401, 0.09558, 0.10484, 0.11611, 0.12220, 0.12767, 0.13695, \ + 0.13704, 0.14192, 0.14290, 0.14352, 0.14372, 0.14378, 0.14377, 0.14377, \ + 0.14526, 0.15067, 0.15224, 0.16157, 0.17292, 0.17907, 0.18459, 0.19397, \ + 0.19407, 0.19900, 0.20000, 0.20064, 0.20084, 0.20090, 0.20089, 0.20089, \ + 0.24868, 0.25410, 0.25567, 0.26501, 0.27638, 0.28254, 0.28807, 0.29748, \ + 0.29757, 0.30252, 0.30352, 0.30416, 0.30436, 0.30442, 0.30442, 0.30441, \ + 0.40390, 0.40932, 0.41089, 0.42023, 0.43160, 0.43776, 0.44330, 0.45270, \ + 0.45279, 0.45775, 0.45875, 0.45939, 0.45959, 0.45965, 0.45964, 0.45964 "); + } + } + + capacitance () { + top_plane: metal3; + bottom_plane: poly; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0650, 0.0900, 0.0975, 0.1462, 0.2194, 0.2700, 0.3291, 0.4936, \ + 0.5000, 0.7404, 0.9000, 1.1106, 1.5000, 1.6659, 2.4988, 249.8818 "); + values (" 0.06056, 0.04380, 0.04037, 0.02574, 0.01505, 0.01087, 0.00758, 0.00301, \ + 0.00290, 0.00081, 0.00036, 0.00013, 0.00002, 0.00001, 0.00000, 0.00000, \ + 0.06134, 0.04445, 0.04098, 0.02619, 0.01536, 0.01111, 0.00776, 0.00309, \ + 0.00297, 0.00084, 0.00037, 0.00013, 0.00002, 0.00001, 0.00000, 0.00000, \ + 0.06259, 0.04551, 0.04199, 0.02696, 0.01588, 0.01151, 0.00807, 0.00322, \ + 0.00310, 0.00087, 0.00039, 0.00013, 0.00002, 0.00001, 0.00000, 0.00000, \ + 0.06405, 0.04677, 0.04320, 0.02788, 0.01651, 0.01201, 0.00843, 0.00339, \ + 0.00326, 0.00092, 0.00041, 0.00014, 0.00002, 0.00001, 0.00000, 0.00000, \ + 0.06412, 0.04682, 0.04325, 0.02792, 0.01654, 0.01203, 0.00845, 0.00339, \ + 0.00327, 0.00092, 0.00041, 0.00014, 0.00002, 0.00001, 0.00000, 0.00000, \ + 0.06469, 0.04731, 0.04372, 0.02828, 0.01678, 0.01222, 0.00859, 0.00346, \ + 0.00333, 0.00094, 0.00042, 0.00015, 0.00002, 0.00001, 0.00000, 0.00000, \ + 0.06482, 0.04742, 0.04382, 0.02835, 0.01684, 0.01226, 0.00862, 0.00347, \ + 0.00334, 0.00095, 0.00042, 0.00015, 0.00002, 0.00001, 0.00000, 0.00000, \ + 0.06483, 0.04743, 0.04383, 0.02836, 0.01684, 0.01226, 0.00863, 0.00347, \ + 0.00334, 0.00095, 0.00042, 0.00015, 0.00002, 0.00001, 0.00000, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0650, 0.0900, 0.0975, 0.1462, 0.2194, 0.2700, 0.3291, 0.4936, \ + 0.5000, 0.7404, 0.9000, 1.1106, 1.5000, 1.6659, 2.4988, 249.8818 "); + values (" 0.04351, 0.04943, 0.05113, 0.06081, 0.07186, 0.07758, 0.08249, 0.09069, \ + 0.09068, 0.09495, 0.09575, 0.09634, 0.09648, 0.09655, 0.09667, 0.09666, \ + 0.04961, 0.05555, 0.05726, 0.06702, 0.07818, 0.08399, 0.08898, 0.09734, \ + 0.09734, 0.10170, 0.10253, 0.10313, 0.10329, 0.10336, 0.10345, 0.10345, \ + 0.06494, 0.07093, 0.07266, 0.08252, 0.09389, 0.09983, 0.10497, 0.11361, \ + 0.11362, 0.11816, 0.11904, 0.11966, 0.11983, 0.11990, 0.11999, 0.11998, \ + 0.10551, 0.11157, 0.11332, 0.12334, 0.13496, 0.14107, 0.14638, 0.15537, \ + 0.15539, 0.16014, 0.16107, 0.16173, 0.16191, 0.16198, 0.16206, 0.16206, \ + 0.10866, 0.11472, 0.11647, 0.12650, 0.13814, 0.14425, 0.14957, 0.15857, \ + 0.15859, 0.16335, 0.16429, 0.16494, 0.16512, 0.16519, 0.16528, 0.16527, \ + 0.17839, 0.18449, 0.18626, 0.19636, 0.20811, 0.21428, 0.21968, 0.22881, \ + 0.22884, 0.23368, 0.23464, 0.23530, 0.23549, 0.23556, 0.23564, 0.23564, \ + 0.30579, 0.31190, 0.31367, 0.32379, 0.33555, 0.34175, 0.34715, 0.35632, \ + 0.35634, 0.36120, 0.36216, 0.36283, 0.36302, 0.36309, 0.36309, 0.36317, \ + 0.49700, 0.50311, 0.50488, 0.51500, 0.52677, 0.53296, 0.53837, 0.54753, \ + 0.54756, 0.55242, 0.55338, 0.55405, 0.55424, 0.55431, 0.55431, 0.55439 "); + } + } + + capacitance () { + top_plane: metal3; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0650, 0.0900, 0.0975, 0.1462, 0.2194, 0.2700, 0.3291, 0.4936, \ + 0.5000, 0.7404, 0.9000, 1.1106, 1.5000, 1.6659, 2.4988, 249.8818 "); + values (" 0.06663, 0.05020, 0.04684, 0.03244, 0.02152, 0.01695, 0.01308, 0.00676, \ + 0.00658, 0.00264, 0.00145, 0.00067, 0.00016, 0.00009, 0.00000, 0.00000, \ + 0.06793, 0.05130, 0.04788, 0.03321, 0.02206, 0.01737, 0.01340, 0.00693, \ + 0.00674, 0.00270, 0.00149, 0.00069, 0.00017, 0.00009, 0.00000, 0.00000, \ + 0.07013, 0.05315, 0.04965, 0.03455, 0.02297, 0.01810, 0.01397, 0.00722, \ + 0.00703, 0.00282, 0.00155, 0.00071, 0.00017, 0.00010, 0.00000, 0.00000, \ + 0.07269, 0.05534, 0.05174, 0.03613, 0.02407, 0.01896, 0.01464, 0.00757, \ + 0.00737, 0.00295, 0.00162, 0.00075, 0.00018, 0.00010, 0.00000, 0.00000, \ + 0.07279, 0.05543, 0.05183, 0.03619, 0.02411, 0.01900, 0.01467, 0.00758, \ + 0.00738, 0.00296, 0.00163, 0.00075, 0.00018, 0.00010, 0.00000, 0.00000, \ + 0.07377, 0.05627, 0.05263, 0.03680, 0.02453, 0.01933, 0.01492, 0.00771, \ + 0.00751, 0.00301, 0.00166, 0.00076, 0.00019, 0.00010, 0.00000, 0.00000, \ + 0.07398, 0.05645, 0.05280, 0.03693, 0.02462, 0.01940, 0.01498, 0.00774, \ + 0.00753, 0.00302, 0.00166, 0.00076, 0.00019, 0.00010, 0.00001, 0.00000, \ + 0.07400, 0.05646, 0.05281, 0.03694, 0.02462, 0.01940, 0.01498, 0.00774, \ + 0.00754, 0.00302, 0.00166, 0.00076, 0.00019, 0.00010, 0.00001, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0650, 0.0900, 0.0975, 0.1462, 0.2194, 0.2700, 0.3291, 0.4936, \ + 0.5000, 0.7404, 0.9000, 1.1106, 1.5000, 1.6659, 2.4988, 249.8818 "); + values (" 0.02105, 0.02384, 0.02466, 0.02970, 0.03646, 0.04059, 0.04480, 0.05365, \ + 0.05385, 0.06077, 0.06300, 0.06461, 0.06563, 0.06581, 0.06592, 0.06592, \ + 0.02329, 0.02609, 0.02691, 0.03203, 0.03893, 0.04315, 0.04746, 0.05651, \ + 0.05672, 0.06381, 0.06609, 0.06774, 0.06879, 0.06897, 0.06907, 0.06908, \ + 0.02902, 0.03188, 0.03272, 0.03799, 0.04515, 0.04953, 0.05401, 0.06343, \ + 0.06366, 0.07102, 0.07341, 0.07513, 0.07622, 0.07641, 0.07650, 0.07651, \ + 0.04492, 0.04790, 0.04879, 0.05429, 0.06179, 0.06638, 0.07108, 0.08094, \ + 0.08118, 0.08889, 0.09139, 0.09319, 0.09434, 0.09453, 0.09462, 0.09463, \ + 0.04619, 0.04918, 0.05006, 0.05558, 0.06309, 0.06769, 0.07240, 0.08227, \ + 0.08252, 0.09024, 0.09275, 0.09455, 0.09570, 0.09589, 0.09598, 0.09599, \ + 0.07476, 0.07781, 0.07871, 0.08434, 0.09200, 0.09669, 0.10148, 0.11152, \ + 0.11177, 0.11963, 0.12218, 0.12401, 0.12518, 0.12538, 0.12547, 0.12548, \ + 0.12763, 0.13070, 0.13161, 0.13726, 0.14495, 0.14965, 0.15446, 0.16454, \ + 0.16479, 0.17267, 0.17523, 0.17707, 0.17825, 0.17844, 0.17864, 0.17854, \ + 0.20712, 0.21019, 0.21109, 0.21675, 0.22444, 0.22914, 0.23395, 0.24403, \ + 0.24428, 0.25216, 0.25473, 0.25657, 0.25774, 0.25794, 0.25814, 0.25803 "); + } + } + + capacitance () { + top_plane: metal4; + bottom_plane: poly; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0650, 0.0900, 0.0975, 0.1462, 0.2194, 0.2700, 0.3291, 0.4936, \ + 0.5000, 0.7404, 0.9000, 1.1106, 1.5000, 1.6659, 2.4988, 249.8818 "); + values (" 0.06132, 0.04467, 0.04128, 0.02686, 0.01639, 0.01229, 0.00902, 0.00424, \ + 0.00411, 0.00155, 0.00084, 0.00039, 0.00010, 0.00006, 0.00000, 0.00000, \ + 0.06222, 0.04546, 0.04203, 0.02745, 0.01683, 0.01265, 0.00931, 0.00440, \ + 0.00427, 0.00162, 0.00088, 0.00041, 0.00010, 0.00006, 0.00000, 0.00000, \ + 0.06382, 0.04687, 0.04339, 0.02856, 0.01767, 0.01335, 0.00988, 0.00472, \ + 0.00458, 0.00175, 0.00096, 0.00044, 0.00011, 0.00006, 0.00000, 0.00000, \ + 0.06613, 0.04895, 0.04541, 0.03024, 0.01897, 0.01444, 0.01077, 0.00522, \ + 0.00507, 0.00196, 0.00108, 0.00050, 0.00013, 0.00007, 0.00000, 0.00000, \ + 0.06625, 0.04906, 0.04551, 0.03032, 0.01903, 0.01449, 0.01081, 0.00525, \ + 0.00510, 0.00197, 0.00108, 0.00050, 0.00013, 0.00007, 0.00000, 0.00000, \ + 0.06774, 0.05041, 0.04683, 0.03143, 0.01989, 0.01522, 0.01140, 0.00558, \ + 0.00543, 0.00212, 0.00116, 0.00054, 0.00014, 0.00008, 0.00000, 0.00000, \ + 0.06841, 0.05102, 0.04742, 0.03192, 0.02027, 0.01554, 0.01167, 0.00574, \ + 0.00558, 0.00218, 0.00120, 0.00056, 0.00014, 0.00008, 0.00000, 0.00000, \ + 0.06853, 0.05112, 0.04752, 0.03200, 0.02033, 0.01559, 0.01171, 0.00576, \ + 0.00560, 0.00219, 0.00121, 0.00056, 0.00014, 0.00008, 0.00000, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0650, 0.0900, 0.0975, 0.1462, 0.2194, 0.2700, 0.3291, 0.4936, \ + 0.5000, 0.7404, 0.9000, 1.1106, 1.5000, 1.6659, 2.4988, 249.8818 "); + values (" 0.04145, 0.04698, 0.04856, 0.05748, 0.06756, 0.07282, 0.07740, 0.08551, \ + 0.08553, 0.09052, 0.09180, 0.09282, 0.09336, 0.09350, 0.09369, 0.09369, \ + 0.04716, 0.05268, 0.05426, 0.06320, 0.07337, 0.07869, 0.08336, 0.09166, \ + 0.09169, 0.09684, 0.09819, 0.09924, 0.09981, 0.09995, 0.10013, 0.10014, \ + 0.06139, 0.06689, 0.06847, 0.07745, 0.08777, 0.09322, 0.09804, 0.10672, \ + 0.10677, 0.11224, 0.11370, 0.11484, 0.11546, 0.11560, 0.11579, 0.11579, \ + 0.09866, 0.10417, 0.10576, 0.11483, 0.12538, 0.13104, 0.13611, 0.14537, \ + 0.14544, 0.15142, 0.15306, 0.15433, 0.15504, 0.15520, 0.15539, 0.15539, \ + 0.10155, 0.10706, 0.10865, 0.11772, 0.12829, 0.13396, 0.13904, 0.14834, \ + 0.14840, 0.15441, 0.15606, 0.15734, 0.15805, 0.15821, 0.15840, 0.15840, \ + 0.16553, 0.17109, 0.17269, 0.18186, 0.19263, 0.19844, 0.20369, 0.21338, \ + 0.21346, 0.21981, 0.22158, 0.22294, 0.22371, 0.22388, 0.22408, 0.22408, \ + 0.28308, 0.28867, 0.29028, 0.29951, 0.31037, 0.31624, 0.32157, 0.33143, \ + 0.33152, 0.33802, 0.33984, 0.34124, 0.34204, 0.34221, 0.34235, 0.34242, \ + 0.46002, 0.46561, 0.46722, 0.47646, 0.48734, 0.49322, 0.49856, 0.50845, \ + 0.50854, 0.51506, 0.51690, 0.51830, 0.51911, 0.51928, 0.51942, 0.51949 "); + } + } + + capacitance () { + top_plane: metal4; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0650, 0.0900, 0.0975, 0.1462, 0.2194, 0.2700, 0.3291, 0.4936, \ + 0.5000, 0.7404, 0.9000, 1.1106, 1.5000, 1.6659, 2.4988, 249.8818 "); + values (" 0.06757, 0.05124, 0.04792, 0.03372, 0.02307, 0.01863, 0.01484, 0.00851, \ + 0.00832, 0.00397, 0.00247, 0.00134, 0.00044, 0.00028, 0.00003, 0.00000, \ + 0.06898, 0.05246, 0.04908, 0.03463, 0.02373, 0.01917, 0.01528, 0.00877, \ + 0.00857, 0.00409, 0.00254, 0.00139, 0.00046, 0.00029, 0.00003, 0.00000, \ + 0.07148, 0.05464, 0.05117, 0.03629, 0.02495, 0.02018, 0.01611, 0.00925, \ + 0.00905, 0.00433, 0.00269, 0.00146, 0.00048, 0.00030, 0.00003, 0.00000, \ + 0.07486, 0.05761, 0.05404, 0.03859, 0.02668, 0.02161, 0.01728, 0.00996, \ + 0.00974, 0.00467, 0.00291, 0.00158, 0.00052, 0.00033, 0.00003, 0.00000, \ + 0.07502, 0.05776, 0.05418, 0.03870, 0.02676, 0.02168, 0.01734, 0.00999, \ + 0.00977, 0.00469, 0.00292, 0.00159, 0.00052, 0.00033, 0.00003, 0.00000, \ + 0.07686, 0.05940, 0.05577, 0.04000, 0.02775, 0.02252, 0.01803, 0.01040, \ + 0.01018, 0.00489, 0.00305, 0.00166, 0.00055, 0.00034, 0.00003, 0.00000, \ + 0.07759, 0.06005, 0.05640, 0.04052, 0.02814, 0.02285, 0.01830, 0.01057, \ + 0.01035, 0.00497, 0.00311, 0.00169, 0.00056, 0.00035, 0.00004, 0.00000, \ + 0.07770, 0.06015, 0.05650, 0.04060, 0.02821, 0.02290, 0.01835, 0.01060, \ + 0.01037, 0.00499, 0.00311, 0.00169, 0.00056, 0.00035, 0.00004, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0650, 0.0900, 0.0975, 0.1462, 0.2194, 0.2700, 0.3291, 0.4936, \ + 0.5000, 0.7404, 0.9000, 1.1106, 1.5000, 1.6659, 2.4988, 249.8818 "); + values (" 0.01859, 0.02101, 0.02171, 0.02598, 0.03163, 0.03510, 0.03870, 0.04662, \ + 0.04682, 0.05387, 0.05655, 0.05874, 0.06053, 0.06089, 0.06134, 0.06139, \ + 0.02049, 0.02287, 0.02357, 0.02785, 0.03359, 0.03714, 0.04081, 0.04894, \ + 0.04914, 0.05638, 0.05915, 0.06140, 0.06325, 0.06362, 0.06408, 0.06413, \ + 0.02518, 0.02755, 0.02825, 0.03259, 0.03852, 0.04220, 0.04603, 0.05454, \ + 0.05476, 0.06236, 0.06528, 0.06768, 0.06963, 0.07002, 0.07049, 0.07055, \ + 0.03788, 0.04032, 0.04104, 0.04555, 0.05176, 0.05565, 0.05971, 0.06876, \ + 0.06901, 0.07714, 0.08029, 0.08287, 0.08498, 0.08540, 0.08590, 0.08596, \ + 0.03889, 0.04133, 0.04206, 0.04658, 0.05280, 0.05670, 0.06077, 0.06985, \ + 0.07010, 0.07826, 0.08142, 0.08401, 0.08612, 0.08654, 0.08704, 0.08711, \ + 0.06182, 0.06432, 0.06506, 0.06971, 0.07613, 0.08015, 0.08437, 0.09377, \ + 0.09403, 0.10250, 0.10579, 0.10849, 0.11070, 0.11114, 0.11166, 0.11173, \ + 0.10491, 0.10745, 0.10820, 0.11290, 0.11940, 0.12346, 0.12774, 0.13726, \ + 0.13753, 0.14613, 0.14947, 0.15221, 0.15447, 0.15491, 0.15557, 0.15552, \ + 0.17014, 0.17268, 0.17343, 0.17814, 0.18465, 0.18872, 0.19300, 0.20255, \ + 0.20282, 0.21143, 0.21478, 0.21754, 0.21980, 0.22024, 0.22090, 0.22085 "); + } + } + + capacitance () { + top_plane: metal5; + bottom_plane: poly; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0650, 0.0900, 0.0975, 0.1462, 0.2194, 0.2700, 0.3291, 0.4936, \ + 0.5000, 0.7404, 0.9000, 1.1106, 1.5000, 1.6659, 2.4988, 249.8818 "); + values (" 0.06180, 0.04521, 0.04182, 0.02750, 0.01719, 0.01317, 0.00996, 0.00522, \ + 0.00509, 0.00237, 0.00152, 0.00089, 0.00035, 0.00024, 0.00004, 0.00000, \ + 0.06275, 0.04604, 0.04263, 0.02817, 0.01771, 0.01362, 0.01034, 0.00547, \ + 0.00533, 0.00250, 0.00161, 0.00095, 0.00038, 0.00026, 0.00004, 0.00000, \ + 0.06451, 0.04763, 0.04418, 0.02950, 0.01878, 0.01455, 0.01115, 0.00599, \ + 0.00585, 0.00279, 0.00181, 0.00106, 0.00043, 0.00029, 0.00005, 0.00000, \ + 0.06740, 0.05031, 0.04680, 0.03179, 0.02070, 0.01624, 0.01261, 0.00699, \ + 0.00683, 0.00336, 0.00220, 0.00131, 0.00053, 0.00036, 0.00006, 0.00000, \ + 0.06757, 0.05047, 0.04695, 0.03192, 0.02081, 0.01634, 0.01270, 0.00705, \ + 0.00689, 0.00339, 0.00222, 0.00132, 0.00053, 0.00037, 0.00006, 0.00000, \ + 0.07008, 0.05283, 0.04927, 0.03399, 0.02257, 0.01793, 0.01410, 0.00803, \ + 0.00786, 0.00396, 0.00262, 0.00157, 0.00064, 0.00045, 0.00007, 0.00000, \ + 0.07202, 0.05466, 0.05107, 0.03562, 0.02397, 0.01919, 0.01522, 0.00883, \ + 0.00865, 0.00444, 0.00296, 0.00179, 0.00074, 0.00051, 0.00009, 0.00000, \ + 0.07284, 0.05544, 0.05184, 0.03632, 0.02458, 0.01974, 0.01570, 0.00918, \ + 0.00899, 0.00465, 0.00311, 0.00189, 0.00078, 0.00054, 0.00009, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0650, 0.0900, 0.0975, 0.1462, 0.2194, 0.2700, 0.3291, 0.4936, \ + 0.5000, 0.7404, 0.9000, 1.1106, 1.5000, 1.6659, 2.4988, 249.8818 "); + values (" 0.04019, 0.04556, 0.04709, 0.05566, 0.06522, 0.07016, 0.07447, 0.08220, \ + 0.08222, 0.08733, 0.08886, 0.09020, 0.09121, 0.09148, 0.09198, 0.09206, \ + 0.04577, 0.05110, 0.05262, 0.06115, 0.07074, 0.07574, 0.08011, 0.08802, \ + 0.08805, 0.09335, 0.09495, 0.09636, 0.09744, 0.09772, 0.09824, 0.09832, \ + 0.05952, 0.06477, 0.06627, 0.07474, 0.08439, 0.08946, 0.09397, 0.10225, \ + 0.10230, 0.10797, 0.10975, 0.11131, 0.11253, 0.11284, 0.11341, 0.11350, \ + 0.09496, 0.10013, 0.10162, 0.11006, 0.11981, 0.12505, 0.12977, 0.13868, \ + 0.13876, 0.14515, 0.14724, 0.14909, 0.15059, 0.15096, 0.15164, 0.15176, \ + 0.09769, 0.10286, 0.10434, 0.11278, 0.12254, 0.12779, 0.13253, 0.14147, \ + 0.14155, 0.14798, 0.15010, 0.15196, 0.15348, 0.15386, 0.15455, 0.15467, \ + 0.15783, 0.16299, 0.16448, 0.17294, 0.18286, 0.18825, 0.19318, 0.20270, \ + 0.20280, 0.20990, 0.21233, 0.21448, 0.21629, 0.21674, 0.21755, 0.21770, \ + 0.26809, 0.27327, 0.27477, 0.28330, 0.29335, 0.29887, 0.30397, 0.31394, \ + 0.31406, 0.32170, 0.32439, 0.32677, 0.32882, 0.32933, 0.33019, 0.33041, \ + 0.43471, 0.43992, 0.44142, 0.44999, 0.46012, 0.46569, 0.47086, 0.48103, \ + 0.48116, 0.48902, 0.49182, 0.49431, 0.49647, 0.49700, 0.49791, 0.49815 "); + } + } + + capacitance () { + top_plane: metal5; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0650, 0.0900, 0.0975, 0.1462, 0.2194, 0.2700, 0.3291, 0.4936, \ + 0.5000, 0.7404, 0.9000, 1.1106, 1.5000, 1.6659, 2.4988, 249.8818 "); + values (" 0.06824, 0.05197, 0.04865, 0.03456, 0.02407, 0.01974, 0.01606, 0.00992, \ + 0.00973, 0.00535, 0.00370, 0.00236, 0.00106, 0.00077, 0.00015, 0.00000, \ + 0.06969, 0.05322, 0.04986, 0.03553, 0.02482, 0.02037, 0.01660, 0.01028, \ + 0.01008, 0.00555, 0.00385, 0.00246, 0.00111, 0.00080, 0.00016, 0.00000, \ + 0.07233, 0.05557, 0.05212, 0.03739, 0.02627, 0.02162, 0.01767, 0.01099, \ + 0.01079, 0.00598, 0.00416, 0.00265, 0.00120, 0.00087, 0.00017, 0.00000, \ + 0.07627, 0.05912, 0.05557, 0.04029, 0.02859, 0.02365, 0.01942, 0.01221, \ + 0.01199, 0.00671, 0.00471, 0.00302, 0.00138, 0.00100, 0.00020, 0.00000, \ + 0.07648, 0.05931, 0.05576, 0.04045, 0.02872, 0.02377, 0.01952, 0.01228, \ + 0.01206, 0.00676, 0.00474, 0.00304, 0.00139, 0.00100, 0.00020, 0.00000, \ + 0.07932, 0.06193, 0.05833, 0.04269, 0.03059, 0.02543, 0.02099, 0.01333, \ + 0.01310, 0.00743, 0.00524, 0.00337, 0.00155, 0.00112, 0.00023, 0.00000, \ + 0.08124, 0.06375, 0.06010, 0.04428, 0.03195, 0.02666, 0.02209, 0.01414, \ + 0.01390, 0.00794, 0.00562, 0.00364, 0.00168, 0.00122, 0.00026, 0.00000, \ + 0.08203, 0.06449, 0.06084, 0.04494, 0.03252, 0.02718, 0.02255, 0.01448, \ + 0.01424, 0.00816, 0.00579, 0.00375, 0.00174, 0.00126, 0.00026, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0650, 0.0900, 0.0975, 0.1462, 0.2194, 0.2700, 0.3291, 0.4936, \ + 0.5000, 0.7404, 0.9000, 1.1106, 1.5000, 1.6659, 2.4988, 249.8818 "); + values (" 0.01688, 0.01914, 0.01980, 0.02372, 0.02879, 0.03184, 0.03499, 0.04197, \ + 0.04215, 0.04871, 0.05146, 0.05394, 0.05641, 0.05702, 0.05819, 0.05850, \ + 0.01867, 0.02087, 0.02151, 0.02539, 0.03047, 0.03357, 0.03677, 0.04391, \ + 0.04410, 0.05084, 0.05369, 0.05624, 0.05882, 0.05945, 0.06067, 0.06100, \ + 0.02294, 0.02506, 0.02568, 0.02950, 0.03465, 0.03783, 0.04114, 0.04860, \ + 0.04880, 0.05591, 0.05894, 0.06170, 0.06446, 0.06514, 0.06646, 0.06681, \ + 0.03388, 0.03597, 0.03659, 0.04044, 0.04572, 0.04904, 0.05252, 0.06047, \ + 0.06069, 0.06841, 0.07175, 0.07482, 0.07794, 0.07871, 0.08021, 0.08063, \ + 0.03473, 0.03682, 0.03744, 0.04130, 0.04659, 0.04991, 0.05340, 0.06137, \ + 0.06160, 0.06935, 0.07271, 0.07580, 0.07894, 0.07972, 0.08123, 0.08165, \ + 0.05388, 0.05599, 0.05662, 0.06053, 0.06595, 0.06937, 0.07299, 0.08135, \ + 0.08160, 0.08985, 0.09348, 0.09685, 0.10031, 0.10118, 0.10287, 0.10335, \ + 0.08981, 0.09195, 0.09258, 0.09654, 0.10206, 0.10556, 0.10929, 0.11793, \ + 0.11819, 0.12682, 0.13066, 0.13424, 0.13797, 0.13890, 0.14086, 0.14126, \ + 0.14481, 0.14696, 0.14759, 0.15159, 0.15716, 0.16069, 0.16447, 0.17324, \ + 0.17350, 0.18229, 0.18622, 0.18990, 0.19373, 0.19468, 0.19671, 0.19713 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: poly; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0650, 0.0900, 0.0975, 0.1462, 0.2194, 0.2700, 0.3291, 0.4936, \ + 0.5000, 0.7404, 0.9000, 1.1106, 1.5000, 1.6659, 2.4988, 249.8818 "); + values (" 0.06241, 0.04584, 0.04247, 0.02819, 0.01792, 0.01392, 0.01073, 0.00601, \ + 0.00587, 0.00313, 0.00223, 0.00154, 0.00089, 0.00073, 0.00034, 0.00000, \ + 0.06338, 0.04670, 0.04330, 0.02889, 0.01849, 0.01442, 0.01117, 0.00632, \ + 0.00618, 0.00333, 0.00239, 0.00167, 0.00096, 0.00079, 0.00037, 0.00000, \ + 0.06520, 0.04836, 0.04491, 0.03030, 0.01967, 0.01549, 0.01212, 0.00702, \ + 0.00687, 0.00379, 0.00275, 0.00193, 0.00114, 0.00094, 0.00044, 0.00000, \ + 0.06836, 0.05132, 0.04782, 0.03292, 0.02196, 0.01758, 0.01402, 0.00848, \ + 0.00832, 0.00481, 0.00358, 0.00257, 0.00157, 0.00131, 0.00064, 0.00000, \ + 0.06856, 0.05151, 0.04801, 0.03308, 0.02211, 0.01772, 0.01414, 0.00858, \ + 0.00842, 0.00488, 0.00364, 0.00262, 0.00160, 0.00134, 0.00065, 0.00000, \ + 0.07179, 0.05461, 0.05107, 0.03594, 0.02469, 0.02014, 0.01638, 0.01041, \ + 0.01023, 0.00626, 0.00480, 0.00356, 0.00226, 0.00192, 0.00099, 0.00000, \ + 0.07538, 0.05810, 0.05454, 0.03924, 0.02776, 0.02307, 0.01916, 0.01279, \ + 0.01261, 0.00817, 0.00647, 0.00498, 0.00333, 0.00288, 0.00159, 0.00000, \ + 0.07866, 0.06133, 0.05775, 0.04235, 0.03074, 0.02595, 0.02193, 0.01529, \ + 0.01509, 0.01030, 0.00840, 0.00667, 0.00470, 0.00413, 0.00244, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0650, 0.0900, 0.0975, 0.1462, 0.2194, 0.2700, 0.3291, 0.4936, \ + 0.5000, 0.7404, 0.9000, 1.1106, 1.5000, 1.6659, 2.4988, 249.8818 "); + values (" 0.03864, 0.04389, 0.04539, 0.05379, 0.06317, 0.06801, 0.07224, 0.07986, \ + 0.07988, 0.08499, 0.08658, 0.08802, 0.08926, 0.08962, 0.09051, 0.09120, \ + 0.04415, 0.04937, 0.05085, 0.05920, 0.06857, 0.07345, 0.07772, 0.08547, \ + 0.08550, 0.09078, 0.09245, 0.09395, 0.09529, 0.09567, 0.09661, 0.09736, \ + 0.05772, 0.06284, 0.06430, 0.07253, 0.08188, 0.08679, 0.09114, 0.09917, \ + 0.09922, 0.10484, 0.10668, 0.10837, 0.10988, 0.11032, 0.11140, 0.11230, \ + 0.09238, 0.09737, 0.09880, 0.10688, 0.11618, 0.12115, 0.12562, 0.13412, \ + 0.13419, 0.14046, 0.14264, 0.14466, 0.14658, 0.14714, 0.14855, 0.14985, \ + 0.09503, 0.10001, 0.10144, 0.10952, 0.11881, 0.12378, 0.12826, 0.13679, \ + 0.13686, 0.14317, 0.14537, 0.14742, 0.14937, 0.14993, 0.15136, 0.15269, \ + 0.15297, 0.15788, 0.15929, 0.16726, 0.17653, 0.18156, 0.18615, 0.19511, \ + 0.19521, 0.20217, 0.20473, 0.20717, 0.20964, 0.21036, 0.21227, 0.21427, \ + 0.25770, 0.26255, 0.26395, 0.27186, 0.28111, 0.28618, 0.29087, 0.30023, \ + 0.30035, 0.30797, 0.31094, 0.31382, 0.31693, 0.31786, 0.32042, 0.32367, \ + 0.41436, 0.41918, 0.42056, 0.42843, 0.43767, 0.44276, 0.44752, 0.45717, \ + 0.45730, 0.46542, 0.46872, 0.47200, 0.47571, 0.47685, 0.48017, 0.48512 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0650, 0.0900, 0.0975, 0.1462, 0.2194, 0.2700, 0.3291, 0.4936, \ + 0.5000, 0.7404, 0.9000, 1.1106, 1.5000, 1.6659, 2.4988, 249.8818 "); + values (" 0.06917, 0.05294, 0.04964, 0.03560, 0.02518, 0.02089, 0.01726, 0.01122, \ + 0.01103, 0.00672, 0.00508, 0.00370, 0.00224, 0.00187, 0.00089, 0.00000, \ + 0.07064, 0.05422, 0.05087, 0.03660, 0.02597, 0.02157, 0.01785, 0.01165, \ + 0.01146, 0.00702, 0.00532, 0.00389, 0.00237, 0.00198, 0.00095, 0.00000, \ + 0.07334, 0.05662, 0.05319, 0.03853, 0.02752, 0.02294, 0.01906, 0.01255, \ + 0.01235, 0.00765, 0.00584, 0.00429, 0.00265, 0.00222, 0.00108, 0.00000, \ + 0.07752, 0.06043, 0.05691, 0.04174, 0.03021, 0.02537, 0.02125, 0.01427, \ + 0.01405, 0.00893, 0.00692, 0.00516, 0.00327, 0.00276, 0.00138, 0.00000, \ + 0.07776, 0.06065, 0.05712, 0.04193, 0.03037, 0.02552, 0.02139, 0.01438, \ + 0.01416, 0.00901, 0.00699, 0.00522, 0.00331, 0.00280, 0.00141, 0.00000, \ + 0.08132, 0.06402, 0.06043, 0.04495, 0.03306, 0.02803, 0.02372, 0.01633, \ + 0.01610, 0.01057, 0.00835, 0.00637, 0.00417, 0.00357, 0.00187, 0.00000, \ + 0.08490, 0.06749, 0.06387, 0.04821, 0.03609, 0.03093, 0.02649, 0.01877, \ + 0.01853, 0.01262, 0.01020, 0.00798, 0.00545, 0.00473, 0.00264, 0.00000, \ + 0.08811, 0.07064, 0.06701, 0.05125, 0.03900, 0.03376, 0.02922, 0.02128, \ + 0.02103, 0.01483, 0.01224, 0.00982, 0.00698, 0.00615, 0.00366, 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0700, 0.0900, 0.1400, 0.2700, 0.2800, 0.5000, 0.9000, 1.5000 "); + index_2 (" 0.0650, 0.0900, 0.0975, 0.1462, 0.2194, 0.2700, 0.3291, 0.4936, \ + 0.5000, 0.7404, 0.9000, 1.1106, 1.5000, 1.6659, 2.4988, 249.8818 "); + values (" 0.01456, 0.01667, 0.01728, 0.02098, 0.02579, 0.02868, 0.03166, 0.03820, \ + 0.03837, 0.04451, 0.04713, 0.04957, 0.05224, 0.05297, 0.05483, 0.05663, \ + 0.01629, 0.01834, 0.01894, 0.02258, 0.02737, 0.03029, 0.03328, 0.03991, \ + 0.04009, 0.04636, 0.04906, 0.05157, 0.05434, 0.05511, 0.05706, 0.05897, \ + 0.02039, 0.02236, 0.02294, 0.02650, 0.03126, 0.03419, 0.03722, 0.04403, \ + 0.04422, 0.05073, 0.05359, 0.05629, 0.05927, 0.06010, 0.06224, 0.06441, \ + 0.03061, 0.03250, 0.03306, 0.03653, 0.04126, 0.04420, 0.04729, 0.05431, \ + 0.05451, 0.06142, 0.06452, 0.06752, 0.07092, 0.07189, 0.07446, 0.07723, \ + 0.03138, 0.03328, 0.03384, 0.03730, 0.04202, 0.04497, 0.04805, 0.05509, \ + 0.05529, 0.06222, 0.06534, 0.06835, 0.07178, 0.07275, 0.07535, 0.07818, \ + 0.04836, 0.05020, 0.05074, 0.05413, 0.05880, 0.06173, 0.06483, 0.07199, \ + 0.07221, 0.07946, 0.08282, 0.08613, 0.09001, 0.09114, 0.09429, 0.09803, \ + 0.07877, 0.08056, 0.08109, 0.08441, 0.08899, 0.09189, 0.09499, 0.10225, \ + 0.10247, 0.11002, 0.11361, 0.11723, 0.12164, 0.12297, 0.12692, 0.13206, \ + 0.12386, 0.12562, 0.12615, 0.12941, 0.13393, 0.13682, 0.13991, 0.14722, \ + 0.14745, 0.15522, 0.15900, 0.16288, 0.16775, 0.16925, 0.17393, 0.18103 "); + } + } + } + + layer (poly) { + resistance: 7.800000 + + capacitance () { + top_plane: metal1; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0500, 0.1000, 0.2000 "); + index_2 (" 0.0750, 0.1125, 0.1687, 0.2531, 0.3797, 0.5695, 0.8543, 1.2814, \ + 1.9222, 2.8833, 288.3252 "); + values (" 0.04024, 0.02567, 0.01469, 0.00693, 0.00240, 0.00052, 0.00006, 0.00000, \ + 0.00000, 0.00000, 0.00000, 0.04222, 0.02703, 0.01552, 0.00736, 0.00255, \ + 0.00055, 0.00006, 0.00000, 0.00000, 0.00000, 0.00000, 0.04337, 0.02784, \ + 0.01602, 0.00761, 0.00264, 0.00057, 0.00006, 0.00000, 0.00000, 0.00000, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0500, 0.1000, 0.2000 "); + index_2 (" 0.0750, 0.1125, 0.1687, 0.2531, 0.3797, 0.5695, 0.8543, 1.2814, \ + 1.9222, 2.8833, 288.3252 "); + values (" 0.05273, 0.06348, 0.07589, 0.08767, 0.09591, 0.09967, 0.10062, 0.10092, \ + 0.10070, 0.10072, 0.10073, 0.07338, 0.08457, 0.09755, 0.10993, 0.11866, \ + 0.12265, 0.12367, 0.12396, 0.12372, 0.12374, 0.12375, 0.11593, 0.12739, \ + 0.14071, 0.15346, 0.16247, 0.16661, 0.16766, 0.16796, 0.16771, 0.16774, \ + 0.16775 "); + } + } + + capacitance () { + top_plane: metal2; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0500, 0.1000, 0.2000 "); + index_2 (" 0.0750, 0.1125, 0.1687, 0.2531, 0.3797, 0.5695, 0.8543, 1.2814, \ + 1.9222, 2.8833, 288.3252 "); + values (" 0.04589, 0.03178, 0.02083, 0.01223, 0.00594, 0.00211, 0.00048, 0.00005, \ + 0.00000, 0.00000, 0.00000, 0.04932, 0.03431, 0.02253, 0.01326, 0.00644, \ + 0.00230, 0.00051, 0.00006, 0.00000, 0.00000, 0.00000, 0.05192, 0.03627, \ + 0.02387, 0.01406, 0.00684, 0.00245, 0.00055, 0.00006, 0.00000, 0.00000, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0500, 0.1000, 0.2000 "); + index_2 (" 0.0750, 0.1125, 0.1687, 0.2531, 0.3797, 0.5695, 0.8543, 1.2814, \ + 1.9222, 2.8833, 288.3252 "); + values (" 0.03258, 0.03910, 0.04753, 0.05741, 0.06699, 0.07393, 0.07720, 0.07820, \ + 0.07809, 0.07811, 0.07812, 0.04300, 0.04991, 0.05894, 0.06955, 0.07990, \ + 0.08740, 0.09096, 0.09202, 0.09191, 0.09192, 0.09193, 0.06540, 0.07266, \ + 0.08218, 0.09339, 0.10433, 0.11228, 0.11607, 0.11719, 0.11707, 0.11709, \ + 0.11709 "); + } + } + + capacitance () { + top_plane: metal3; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0500, 0.1000, 0.2000 "); + index_2 (" 0.0750, 0.1125, 0.1687, 0.2531, 0.3797, 0.5695, 0.8543, 1.2814, \ + 1.9222, 2.8833, 288.3252 "); + values (" 0.04678, 0.03285, 0.02213, 0.01373, 0.00743, 0.00324, 0.00104, 0.00021, \ + 0.00002, 0.00000, 0.00000, 0.05058, 0.03579, 0.02425, 0.01514, 0.00824, \ + 0.00363, 0.00116, 0.00023, 0.00002, 0.00000, 0.00000, 0.05400, 0.03852, \ + 0.02630, 0.01655, 0.00910, 0.00405, 0.00131, 0.00026, 0.00002, 0.00000, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0500, 0.1000, 0.2000 "); + index_2 (" 0.0750, 0.1125, 0.1687, 0.2531, 0.3797, 0.5695, 0.8543, 1.2814, \ + 1.9222, 2.8833, 288.3252 "); + values (" 0.03017, 0.03605, 0.04356, 0.05241, 0.06135, 0.06855, 0.07279, 0.07459, \ + 0.07477, 0.07483, 0.07483, 0.03938, 0.04548, 0.05344, 0.06291, 0.07261, \ + 0.08052, 0.08525, 0.08725, 0.08746, 0.08752, 0.08752, 0.05878, 0.06512, \ + 0.07347, 0.08353, 0.09394, 0.10256, 0.10781, 0.11004, 0.11030, 0.11036, \ + 0.11036 "); + } + } + + capacitance () { + top_plane: metal4; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0500, 0.1000, 0.2000 "); + index_2 (" 0.0750, 0.1125, 0.1687, 0.2531, 0.3797, 0.5695, 0.8543, 1.2814, \ + 1.9222, 2.8833, 288.3252 "); + values (" 0.04711, 0.03322, 0.02258, 0.01429, 0.00805, 0.00383, 0.00145, 0.00039, \ + 0.00006, 0.00000, 0.00000, 0.05101, 0.03629, 0.02486, 0.01587, 0.00904, \ + 0.00435, 0.00166, 0.00045, 0.00007, 0.00000, 0.00000, 0.05474, 0.03935, \ + 0.02724, 0.01761, 0.01019, 0.00500, 0.00194, 0.00053, 0.00008, 0.00001, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0500, 0.1000, 0.2000 "); + index_2 (" 0.0750, 0.1125, 0.1687, 0.2531, 0.3797, 0.5695, 0.8543, 1.2814, \ + 1.9222, 2.8833, 288.3252 "); + values (" 0.02930, 0.03503, 0.04227, 0.05073, 0.05931, 0.06639, 0.07087, 0.07311, \ + 0.07358, 0.07372, 0.07373, 0.03822, 0.04407, 0.05166, 0.06067, 0.06995, \ + 0.07775, 0.08281, 0.08533, 0.08589, 0.08604, 0.08605, 0.05665, 0.06266, \ + 0.07056, 0.08007, 0.09004, 0.09861, 0.10434, 0.10725, 0.10795, 0.10812, \ + 0.10813 "); + } + } + + capacitance () { + top_plane: AIR; + bottom_plane: SUBSTRATE; + lateral_capacitance (capacitance_template_WxS) { + index_1 (" 0.0500, 0.1000, 0.2000 "); + index_2 (" 0.0750, 0.1125, 0.1687, 0.2531, 0.3797, 0.5695, 0.8543, 1.2814, \ + 1.9222, 2.8833, 288.3252 "); + values (" 0.04795, 0.03412, 0.02354, 0.01532, 0.00917, 0.00496, 0.00246, 0.00115, \ + 0.00052, 0.00024, 0.00000, 0.05194, 0.03730, 0.02598, 0.01713, 0.01043, \ + 0.00578, 0.00294, 0.00141, 0.00065, 0.00030, 0.00000, 0.05600, 0.04074, \ + 0.02881, 0.01938, 0.01214, 0.00699, 0.00371, 0.00186, 0.00089, 0.00042, \ + 0.00000 "); + } + ground_capacitance (capacitance_template_WxS) { + index_1 (" 0.0500, 0.1000, 0.2000 "); + index_2 (" 0.0750, 0.1125, 0.1687, 0.2531, 0.3797, 0.5695, 0.8543, 1.2814, \ + 1.9222, 2.8833, 288.3252 "); + values (" 0.02712, 0.03266, 0.03967, 0.04783, 0.05606, 0.06293, 0.06751, 0.07019, \ + 0.07127, 0.07187, 0.07235, 0.03581, 0.04139, 0.04860, 0.05711, 0.06586, \ + 0.07333, 0.07850, 0.08156, 0.08288, 0.08361, 0.08423, 0.05331, 0.05891, \ + 0.06621, 0.07498, 0.08418, 0.09229, 0.09816, 0.10181, 0.10354, 0.10450, \ + 0.10537 "); + } + } + } + + layer (via9) { + resistance : 0.500000; + } + layer (via8) { + resistance : 1.000000; + } + layer (via7) { + resistance : 1.000000; + } + layer (via6) { + resistance : 3.000000; + } + layer (via5) { + resistance : 3.000000; + } + layer (via4) { + resistance : 3.000000; + } + layer (via3) { + resistance : 5.000000; + } + layer (via2) { + resistance : 5.000000; + } + layer (via1) { + resistance : 5.000000; + } + layer (contact) { + resistance : 25.000000; + } + layer (diffco) { + resistance : 30.000000; + } + +} diff --git a/libs/fastscan/.NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib.swo b/libs/fastscan/.NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib.swo new file mode 100644 index 0000000..c1fe9e0 Binary files /dev/null and b/libs/fastscan/.NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib.swo differ diff --git a/libs/fastscan/.NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib.swp b/libs/fastscan/.NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib.swp new file mode 100644 index 0000000..d570175 Binary files /dev/null and b/libs/fastscan/.NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib.swp differ diff --git a/libs/fastscan/.NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib.swp b/libs/fastscan/.NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib.swp new file mode 100644 index 0000000..a7c3127 Binary files /dev/null and b/libs/fastscan/.NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib.swp differ diff --git a/libs/fastscan/IO.fslib b/libs/fastscan/IO.fslib new file mode 100755 index 0000000..751a109 --- /dev/null +++ b/libs/fastscan/IO.fslib @@ -0,0 +1,43 @@ + +library_format_version = 9; + +array_delimiter = "[]"; + + +// +// *********************************************************************** +// *********** Models holding Liberty information ****************** +// *********************************************************************** +// + + +model PADBID + (C, I, OEN, PAD) +( + model_source = liberty_cell; + cell_type = pad; + + input (I) ( pad_to_pad; ) + input (OEN) ( pad_enable_low; ) + inout (PAD) ( pad_pad_io; ) + output (C) ( pad_from_pad; ) + ( + primitive = _buf (PAD, C); + primitive = _tsl (I, OEN, PAD); + ) +) // end model PADBID + + +model PADCLK + (C, PAD) +( + model_source = liberty_cell; + cell_type = pad; + simulation_function = buffer; + + input (PAD) ( pad_from_io; ) + output (C) ( pad_from_pad; ) + ( + primitive = _buf (PAD, C); + ) +) // end model PADCLK diff --git a/libs/fastscan/LowPowerOpenCellLibrary_low_temp_ccs.fslib b/libs/fastscan/LowPowerOpenCellLibrary_low_temp_ccs.fslib new file mode 100755 index 0000000..c0e8f62 --- /dev/null +++ b/libs/fastscan/LowPowerOpenCellLibrary_low_temp_ccs.fslib @@ -0,0 +1,583 @@ +// +// *********************************************************************** +// Copyright Mentor Graphics Corporation +// All Rights Reserved +// For use only with Mentor Graphics Tessent tools +// *********************************************************************** +// File Type: Tessent Cell Library +// Generated by: Tessent Shell -- write_cell_library +// Tool Version: 2019.4 +// Tool Build Date: Wed Nov 20 21:14:16 GMT 2019 +// *********************************************************************** +// Library Created : Local Time = Tue Jun 30 00:33:32 2020 +// GMT = Tue Jun 30 07:33:32 2020 + + +library_format_version = 9; + +array_delimiter = "[]"; + + +// +// *********************************************************************** +// *********** Models holding Liberty information ****************** +// *********************************************************************** +// + + +model AON_BUF_X1 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model AON_BUF_X1 + + +model AON_BUF_X2 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model AON_BUF_X2 + + +model AON_BUF_X4 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model AON_BUF_X4 + + +model AON_INV_X1 + (A, Z) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _inv (A, Z); + ) +) // end model AON_INV_X1 + + +model AON_INV_X2 + (A, Z) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _inv (A, Z); + ) +) // end model AON_INV_X2 + + +model AON_INV_X4 + (A, Z) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _inv (A, Z); + ) +) // end model AON_INV_X4 + + +model HEADER_OE_X1 + (SLEEP, SLEEPOUT) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (SLEEP) ( ) + output (SLEEPOUT) ( ) + ( + primitive = _buf (SLEEP, SLEEPOUT); + ) +) // end model HEADER_OE_X1 + + +model HEADER_OE_X2 + (SLEEP, SLEEPOUT) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (SLEEP) ( ) + output (SLEEPOUT) ( ) + ( + primitive = _buf (SLEEP, SLEEPOUT); + ) +) // end model HEADER_OE_X2 + + +model HEADER_OE_X4 + (SLEEP, SLEEPOUT) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (SLEEP) ( ) + output (SLEEPOUT) ( ) + ( + primitive = _buf (SLEEP, SLEEPOUT); + ) +) // end model HEADER_OE_X4 + + +model HEADER_X1 + (SLEEP) +( + model_source = liberty_cell; + cell_type = prohibited; + + input (SLEEP) ( ) + ( + // Empty Model + ) +) // end model HEADER_X1 + + +model HEADER_X2 + (SLEEP) +( + model_source = liberty_cell; + cell_type = prohibited; + + input (SLEEP) ( ) + ( + // Empty Model + ) +) // end model HEADER_X2 + + +model HEADER_X4 + (SLEEP) +( + model_source = liberty_cell; + cell_type = prohibited; + + input (SLEEP) ( ) + ( + // Empty Model + ) +) // end model HEADER_X4 + + +model ISO_FENCE0N_X1 + (A, EN, Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = and; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _and (A, EN, Z); + ) +) // end model ISO_FENCE0N_X1 + + +model ISO_FENCE0N_X2 + (A, EN, Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = and; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _and (A, EN, Z); + ) +) // end model ISO_FENCE0N_X2 + + +model ISO_FENCE0N_X4 + (A, EN, Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = and; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _and (A, EN, Z); + ) +) // end model ISO_FENCE0N_X4 + + +model ISO_FENCE0_X1 + (A, EN, Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = nor; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _inv (net_0, Z); + primitive = _or (A, EN, net_0); + ) +) // end model ISO_FENCE0_X1 + + +model ISO_FENCE0_X2 + (A, EN, Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = nor; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _inv (net_0, Z); + primitive = _or (A, EN, net_0); + ) +) // end model ISO_FENCE0_X2 + + +model ISO_FENCE0_X4 + (A, EN, Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = nor; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _inv (net_0, Z); + primitive = _or (A, EN, net_0); + ) +) // end model ISO_FENCE0_X4 + + +model ISO_FENCE1N_X1 + (A, EN, Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = nand; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _inv (net_0, Z); + primitive = _and (A, EN, net_0); + ) +) // end model ISO_FENCE1N_X1 + + +model ISO_FENCE1N_X2 + (A, EN, Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = nand; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _inv (net_0, Z); + primitive = _and (A, EN, net_0); + ) +) // end model ISO_FENCE1N_X2 + + +model ISO_FENCE1N_X4 + (A, EN, Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = nand; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _inv (net_0, Z); + primitive = _and (A, EN, net_0); + ) +) // end model ISO_FENCE1N_X4 + + +model ISO_FENCE1_X1 + (A, EN, Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = or; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _or (A, EN, Z); + ) +) // end model ISO_FENCE1_X1 + + +model ISO_FENCE1_X2 + (A, EN, Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = or; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _or (A, EN, Z); + ) +) // end model ISO_FENCE1_X2 + + +model ISO_FENCE1_X4 + (A, EN, Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = or; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _or (A, EN, Z); + ) +) // end model ISO_FENCE1_X4 + + +model LS_HLEN_X1 + (A, ISOLN, Z) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A) ( ) + input (ISOLN) ( ) + output (Z) ( ) + ( + primitive = _and (A, ISOLN, Z); + ) +) // end model LS_HLEN_X1 + + +model LS_HLEN_X2 + (A, ISOLN, Z) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A) ( ) + input (ISOLN) ( ) + output (Z) ( ) + ( + primitive = _and (A, ISOLN, Z); + ) +) // end model LS_HLEN_X2 + + +model LS_HLEN_X4 + (A, ISOLN, Z) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A) ( ) + input (ISOLN) ( ) + output (Z) ( ) + ( + primitive = _and (A, ISOLN, Z); + ) +) // end model LS_HLEN_X4 + + +model LS_HL_X1 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model LS_HL_X1 + + +model LS_HL_X2 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model LS_HL_X2 + + +model LS_HL_X4 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model LS_HL_X4 + + +model LS_LHEN_X1 + (A, ISOLN, Z) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A) ( ) + input (ISOLN) ( ) + output (Z) ( ) + ( + primitive = _and (A, ISOLN, Z); + ) +) // end model LS_LHEN_X1 + + +model LS_LHEN_X2 + (A, ISOLN, Z) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A) ( ) + input (ISOLN) ( ) + output (Z) ( ) + ( + primitive = _and (A, ISOLN, Z); + ) +) // end model LS_LHEN_X2 + + +model LS_LHEN_X4 + (A, ISOLN, Z) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A) ( ) + input (ISOLN) ( ) + output (Z) ( ) + ( + primitive = _and (A, ISOLN, Z); + ) +) // end model LS_LHEN_X4 + + +model LS_LH_X1 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model LS_LH_X1 + + +model LS_LH_X2 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model LS_LH_X2 + + +model LS_LH_X4 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model LS_LH_X4 diff --git a/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib b/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib new file mode 100755 index 0000000..c0e8f62 --- /dev/null +++ b/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib @@ -0,0 +1,583 @@ +// +// *********************************************************************** +// Copyright Mentor Graphics Corporation +// All Rights Reserved +// For use only with Mentor Graphics Tessent tools +// *********************************************************************** +// File Type: Tessent Cell Library +// Generated by: Tessent Shell -- write_cell_library +// Tool Version: 2019.4 +// Tool Build Date: Wed Nov 20 21:14:16 GMT 2019 +// *********************************************************************** +// Library Created : Local Time = Tue Jun 30 00:33:32 2020 +// GMT = Tue Jun 30 07:33:32 2020 + + +library_format_version = 9; + +array_delimiter = "[]"; + + +// +// *********************************************************************** +// *********** Models holding Liberty information ****************** +// *********************************************************************** +// + + +model AON_BUF_X1 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model AON_BUF_X1 + + +model AON_BUF_X2 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model AON_BUF_X2 + + +model AON_BUF_X4 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model AON_BUF_X4 + + +model AON_INV_X1 + (A, Z) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _inv (A, Z); + ) +) // end model AON_INV_X1 + + +model AON_INV_X2 + (A, Z) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _inv (A, Z); + ) +) // end model AON_INV_X2 + + +model AON_INV_X4 + (A, Z) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _inv (A, Z); + ) +) // end model AON_INV_X4 + + +model HEADER_OE_X1 + (SLEEP, SLEEPOUT) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (SLEEP) ( ) + output (SLEEPOUT) ( ) + ( + primitive = _buf (SLEEP, SLEEPOUT); + ) +) // end model HEADER_OE_X1 + + +model HEADER_OE_X2 + (SLEEP, SLEEPOUT) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (SLEEP) ( ) + output (SLEEPOUT) ( ) + ( + primitive = _buf (SLEEP, SLEEPOUT); + ) +) // end model HEADER_OE_X2 + + +model HEADER_OE_X4 + (SLEEP, SLEEPOUT) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (SLEEP) ( ) + output (SLEEPOUT) ( ) + ( + primitive = _buf (SLEEP, SLEEPOUT); + ) +) // end model HEADER_OE_X4 + + +model HEADER_X1 + (SLEEP) +( + model_source = liberty_cell; + cell_type = prohibited; + + input (SLEEP) ( ) + ( + // Empty Model + ) +) // end model HEADER_X1 + + +model HEADER_X2 + (SLEEP) +( + model_source = liberty_cell; + cell_type = prohibited; + + input (SLEEP) ( ) + ( + // Empty Model + ) +) // end model HEADER_X2 + + +model HEADER_X4 + (SLEEP) +( + model_source = liberty_cell; + cell_type = prohibited; + + input (SLEEP) ( ) + ( + // Empty Model + ) +) // end model HEADER_X4 + + +model ISO_FENCE0N_X1 + (A, EN, Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = and; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _and (A, EN, Z); + ) +) // end model ISO_FENCE0N_X1 + + +model ISO_FENCE0N_X2 + (A, EN, Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = and; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _and (A, EN, Z); + ) +) // end model ISO_FENCE0N_X2 + + +model ISO_FENCE0N_X4 + (A, EN, Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = and; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _and (A, EN, Z); + ) +) // end model ISO_FENCE0N_X4 + + +model ISO_FENCE0_X1 + (A, EN, Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = nor; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _inv (net_0, Z); + primitive = _or (A, EN, net_0); + ) +) // end model ISO_FENCE0_X1 + + +model ISO_FENCE0_X2 + (A, EN, Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = nor; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _inv (net_0, Z); + primitive = _or (A, EN, net_0); + ) +) // end model ISO_FENCE0_X2 + + +model ISO_FENCE0_X4 + (A, EN, Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = nor; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _inv (net_0, Z); + primitive = _or (A, EN, net_0); + ) +) // end model ISO_FENCE0_X4 + + +model ISO_FENCE1N_X1 + (A, EN, Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = nand; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _inv (net_0, Z); + primitive = _and (A, EN, net_0); + ) +) // end model ISO_FENCE1N_X1 + + +model ISO_FENCE1N_X2 + (A, EN, Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = nand; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _inv (net_0, Z); + primitive = _and (A, EN, net_0); + ) +) // end model ISO_FENCE1N_X2 + + +model ISO_FENCE1N_X4 + (A, EN, Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = nand; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _inv (net_0, Z); + primitive = _and (A, EN, net_0); + ) +) // end model ISO_FENCE1N_X4 + + +model ISO_FENCE1_X1 + (A, EN, Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = or; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _or (A, EN, Z); + ) +) // end model ISO_FENCE1_X1 + + +model ISO_FENCE1_X2 + (A, EN, Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = or; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _or (A, EN, Z); + ) +) // end model ISO_FENCE1_X2 + + +model ISO_FENCE1_X4 + (A, EN, Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = or; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _or (A, EN, Z); + ) +) // end model ISO_FENCE1_X4 + + +model LS_HLEN_X1 + (A, ISOLN, Z) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A) ( ) + input (ISOLN) ( ) + output (Z) ( ) + ( + primitive = _and (A, ISOLN, Z); + ) +) // end model LS_HLEN_X1 + + +model LS_HLEN_X2 + (A, ISOLN, Z) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A) ( ) + input (ISOLN) ( ) + output (Z) ( ) + ( + primitive = _and (A, ISOLN, Z); + ) +) // end model LS_HLEN_X2 + + +model LS_HLEN_X4 + (A, ISOLN, Z) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A) ( ) + input (ISOLN) ( ) + output (Z) ( ) + ( + primitive = _and (A, ISOLN, Z); + ) +) // end model LS_HLEN_X4 + + +model LS_HL_X1 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model LS_HL_X1 + + +model LS_HL_X2 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model LS_HL_X2 + + +model LS_HL_X4 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model LS_HL_X4 + + +model LS_LHEN_X1 + (A, ISOLN, Z) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A) ( ) + input (ISOLN) ( ) + output (Z) ( ) + ( + primitive = _and (A, ISOLN, Z); + ) +) // end model LS_LHEN_X1 + + +model LS_LHEN_X2 + (A, ISOLN, Z) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A) ( ) + input (ISOLN) ( ) + output (Z) ( ) + ( + primitive = _and (A, ISOLN, Z); + ) +) // end model LS_LHEN_X2 + + +model LS_LHEN_X4 + (A, ISOLN, Z) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A) ( ) + input (ISOLN) ( ) + output (Z) ( ) + ( + primitive = _and (A, ISOLN, Z); + ) +) // end model LS_LHEN_X4 + + +model LS_LH_X1 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model LS_LH_X1 + + +model LS_LH_X2 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model LS_LH_X2 + + +model LS_LH_X4 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model LS_LH_X4 diff --git a/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib b/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib new file mode 100755 index 0000000..9a5a02a --- /dev/null +++ b/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib @@ -0,0 +1,583 @@ +// +// *********************************************************************** +// Copyright Mentor Graphics Corporation +// All Rights Reserved +// For use only with Mentor Graphics Tessent tools +// *********************************************************************** +// File Type: Tessent Cell Library +// Generated by: Tessent Shell -- write_cell_library +// Tool Version: 2019.4 +// Tool Build Date: Wed Nov 20 21:14:16 GMT 2019 +// *********************************************************************** +// Library Created : Local Time = Tue Jun 30 00:33:33 2020 +// GMT = Tue Jun 30 07:33:33 2020 + + +library_format_version = 9; + +array_delimiter = "[]"; + + +// +// *********************************************************************** +// *********** Models holding Liberty information ****************** +// *********************************************************************** +// + + +model AON_BUF_X1 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model AON_BUF_X1 + + +model AON_BUF_X2 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model AON_BUF_X2 + + +model AON_BUF_X4 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model AON_BUF_X4 + + +model AON_INV_X1 + (A, Z) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _inv (A, Z); + ) +) // end model AON_INV_X1 + + +model AON_INV_X2 + (A, Z) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _inv (A, Z); + ) +) // end model AON_INV_X2 + + +model AON_INV_X4 + (A, Z) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _inv (A, Z); + ) +) // end model AON_INV_X4 + + +model HEADER_OE_X1 + (SLEEP, SLEEPOUT) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (SLEEP) ( ) + output (SLEEPOUT) ( ) + ( + primitive = _buf (SLEEP, SLEEPOUT); + ) +) // end model HEADER_OE_X1 + + +model HEADER_OE_X2 + (SLEEP, SLEEPOUT) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (SLEEP) ( ) + output (SLEEPOUT) ( ) + ( + primitive = _buf (SLEEP, SLEEPOUT); + ) +) // end model HEADER_OE_X2 + + +model HEADER_OE_X4 + (SLEEP, SLEEPOUT) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (SLEEP) ( ) + output (SLEEPOUT) ( ) + ( + primitive = _buf (SLEEP, SLEEPOUT); + ) +) // end model HEADER_OE_X4 + + +model HEADER_X1 + (SLEEP) +( + model_source = liberty_cell; + cell_type = prohibited; + + input (SLEEP) ( ) + ( + // Empty Model + ) +) // end model HEADER_X1 + + +model HEADER_X2 + (SLEEP) +( + model_source = liberty_cell; + cell_type = prohibited; + + input (SLEEP) ( ) + ( + // Empty Model + ) +) // end model HEADER_X2 + + +model HEADER_X4 + (SLEEP) +( + model_source = liberty_cell; + cell_type = prohibited; + + input (SLEEP) ( ) + ( + // Empty Model + ) +) // end model HEADER_X4 + + +model ISO_FENCE0N_X1 + (A, EN, Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = and; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _and (A, EN, Z); + ) +) // end model ISO_FENCE0N_X1 + + +model ISO_FENCE0N_X2 + (A, EN, Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = and; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _and (A, EN, Z); + ) +) // end model ISO_FENCE0N_X2 + + +model ISO_FENCE0N_X4 + (A, EN, Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = and; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _and (A, EN, Z); + ) +) // end model ISO_FENCE0N_X4 + + +model ISO_FENCE0_X1 + (A, EN, Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = nor; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _inv (net_0, Z); + primitive = _or (A, EN, net_0); + ) +) // end model ISO_FENCE0_X1 + + +model ISO_FENCE0_X2 + (A, EN, Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = nor; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _inv (net_0, Z); + primitive = _or (A, EN, net_0); + ) +) // end model ISO_FENCE0_X2 + + +model ISO_FENCE0_X4 + (A, EN, Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = nor; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _inv (net_0, Z); + primitive = _or (A, EN, net_0); + ) +) // end model ISO_FENCE0_X4 + + +model ISO_FENCE1N_X1 + (A, EN, Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = nand; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _inv (net_0, Z); + primitive = _and (A, EN, net_0); + ) +) // end model ISO_FENCE1N_X1 + + +model ISO_FENCE1N_X2 + (A, EN, Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = nand; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _inv (net_0, Z); + primitive = _and (A, EN, net_0); + ) +) // end model ISO_FENCE1N_X2 + + +model ISO_FENCE1N_X4 + (A, EN, Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = nand; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _inv (net_0, Z); + primitive = _and (A, EN, net_0); + ) +) // end model ISO_FENCE1N_X4 + + +model ISO_FENCE1_X1 + (A, EN, Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = or; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _or (A, EN, Z); + ) +) // end model ISO_FENCE1_X1 + + +model ISO_FENCE1_X2 + (A, EN, Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = or; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _or (A, EN, Z); + ) +) // end model ISO_FENCE1_X2 + + +model ISO_FENCE1_X4 + (A, EN, Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = or; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _or (A, EN, Z); + ) +) // end model ISO_FENCE1_X4 + + +model LS_HLEN_X1 + (A, ISOLN, Z) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A) ( ) + input (ISOLN) ( ) + output (Z) ( ) + ( + primitive = _and (A, ISOLN, Z); + ) +) // end model LS_HLEN_X1 + + +model LS_HLEN_X2 + (A, ISOLN, Z) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A) ( ) + input (ISOLN) ( ) + output (Z) ( ) + ( + primitive = _and (A, ISOLN, Z); + ) +) // end model LS_HLEN_X2 + + +model LS_HLEN_X4 + (A, ISOLN, Z) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A) ( ) + input (ISOLN) ( ) + output (Z) ( ) + ( + primitive = _and (A, ISOLN, Z); + ) +) // end model LS_HLEN_X4 + + +model LS_HL_X1 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model LS_HL_X1 + + +model LS_HL_X2 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model LS_HL_X2 + + +model LS_HL_X4 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model LS_HL_X4 + + +model LS_LHEN_X1 + (A, ISOLN, Z) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A) ( ) + input (ISOLN) ( ) + output (Z) ( ) + ( + primitive = _and (A, ISOLN, Z); + ) +) // end model LS_LHEN_X1 + + +model LS_LHEN_X2 + (A, ISOLN, Z) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A) ( ) + input (ISOLN) ( ) + output (Z) ( ) + ( + primitive = _and (A, ISOLN, Z); + ) +) // end model LS_LHEN_X2 + + +model LS_LHEN_X4 + (A, ISOLN, Z) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A) ( ) + input (ISOLN) ( ) + output (Z) ( ) + ( + primitive = _and (A, ISOLN, Z); + ) +) // end model LS_LHEN_X4 + + +model LS_LH_X1 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model LS_LH_X1 + + +model LS_LH_X2 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model LS_LH_X2 + + +model LS_LH_X4 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model LS_LH_X4 diff --git a/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib b/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib new file mode 100755 index 0000000..86c9bea --- /dev/null +++ b/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib @@ -0,0 +1,2665 @@ +// +// *********************************************************************** +// Copyright Mentor Graphics Corporation +// All Rights Reserved +// For use only with Mentor Graphics Tessent tools +// *********************************************************************** +// File Type: Tessent Cell Library +// Generated by: Tessent Shell -- write_cell_library +// Tool Version: 2019.4 +// Tool Build Date: Wed Nov 20 21:14:16 GMT 2019 +// *********************************************************************** +// Library Created : Local Time = Tue Jun 30 00:33:33 2020 +// GMT = Tue Jun 30 07:33:33 2020 + + +library_format_version = 9; + +array_delimiter = "[]"; + + +// +// *********************************************************************** +// *********** Models holding Liberty information ****************** +// *********************************************************************** +// + + +model AND2_X1_HVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _and (A1, A2, ZN); + ) +) // end model AND2_X1_HVT + + +model AND2_X2_HVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _and (A1, A2, ZN); + ) +) // end model AND2_X2_HVT + + +model AND2_X4_HVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _and (A1, A2, ZN); + ) +) // end model AND2_X4_HVT + + +model AND3_X1_HVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A3, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model AND3_X1_HVT + + +model AND3_X2_HVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A3, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model AND3_X2_HVT + + +model AND3_X4_HVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A3, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model AND3_X4_HVT + + +model AND4_X1_HVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A4, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model AND4_X1_HVT + + +model AND4_X2_HVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A4, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model AND4_X2_HVT + + +model AND4_X4_HVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A4, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model AND4_X4_HVT + + +model ANTENNA_X1_HVT + (A) +( + model_source = liberty_cell; + cell_type = prohibited; + + input (A) ( ) + ( + // Empty Model + ) +) // end model ANTENNA_X1_HVT + + +model AOI211_X1_HVT + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A, net_0); + primitive = _or (net_2, B, net_1); + primitive = _and (C1, C2, net_2); + ) +) // end model AOI211_X1_HVT + + +model AOI211_X2_HVT + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A, net_0); + primitive = _or (net_2, B, net_1); + primitive = _and (C1, C2, net_2); + ) +) // end model AOI211_X2_HVT + + +model AOI211_X4_HVT + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _or (net_3, A, net_2); + primitive = _or (net_4, B, net_3); + primitive = _and (C1, C2, net_4); + ) +) // end model AOI211_X4_HVT + + +model AOI21_X1_HVT + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A, net_1, net_0); + primitive = _and (B1, B2, net_1); + ) +) // end model AOI21_X1_HVT + + +model AOI21_X2_HVT + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A, net_1, net_0); + primitive = _and (B1, B2, net_1); + ) +) // end model AOI21_X2_HVT + + +model AOI21_X4_HVT + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A, net_1, net_0); + primitive = _and (B1, B2, net_1); + ) +) // end model AOI21_X4_HVT + + +model AOI221_X1_HVT + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_3, net_0); + primitive = _or (net_2, A, net_1); + primitive = _and (C1, C2, net_2); + primitive = _and (B1, B2, net_3); + ) +) // end model AOI221_X1_HVT + + +model AOI221_X2_HVT + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_3, net_0); + primitive = _or (net_2, A, net_1); + primitive = _and (C1, C2, net_2); + primitive = _and (B1, B2, net_3); + ) +) // end model AOI221_X2_HVT + + +model AOI221_X4_HVT + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _or (net_3, net_5, net_2); + primitive = _or (net_4, A, net_3); + primitive = _and (C1, C2, net_4); + primitive = _and (B1, B2, net_5); + ) +) // end model AOI221_X4_HVT + + +model AOI222_X1_HVT + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_4, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (A1, A2, net_2); + primitive = _and (B1, B2, net_3); + primitive = _and (C1, C2, net_4); + ) +) // end model AOI222_X1_HVT + + +model AOI222_X2_HVT + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_4, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (A1, A2, net_2); + primitive = _and (B1, B2, net_3); + primitive = _and (C1, C2, net_4); + ) +) // end model AOI222_X2_HVT + + +model AOI222_X4_HVT + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _or (net_3, net_6, net_2); + primitive = _or (net_4, net_5, net_3); + primitive = _and (A1, A2, net_4); + primitive = _and (B1, B2, net_5); + primitive = _and (C1, C2, net_6); + ) +) // end model AOI222_X4_HVT + + +model AOI22_X1_HVT + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (A1, A2, net_1); + primitive = _and (B1, B2, net_2); + ) +) // end model AOI22_X1_HVT + + +model AOI22_X2_HVT + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (A1, A2, net_1); + primitive = _and (B1, B2, net_2); + ) +) // end model AOI22_X2_HVT + + +model AOI22_X4_HVT + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (A1, A2, net_1); + primitive = _and (B1, B2, net_2); + ) +) // end model AOI22_X4_HVT + + +model BUF_X16_HVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X16_HVT + + +model BUF_X1_HVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X1_HVT + + +model BUF_X2_HVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X2_HVT + + +model BUF_X32_HVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X32_HVT + + +model BUF_X4_HVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X4_HVT + + +model BUF_X8_HVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X8_HVT + + +model CLKBUF_X1_HVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model CLKBUF_X1_HVT + + +model CLKBUF_X2_HVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model CLKBUF_X2_HVT + + +model CLKBUF_X3_HVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model CLKBUF_X3_HVT + + +model "CLKGATETST_X1_HVT_$_IQ" + (CK, E, SE, IQ) +( + model_source = liberty_cell_statetable; + + input (CK) ( ) + input (E) ( ) + input (SE) ( ) + output (IQ) ( ) + ( + primitive = _dlat ( , , clock_net, net_0, IQ, ); + primitive = _inv (CK, clock_net); + primitive = _or (E, SE, net_0); + ) +) // end model CLKGATETST_X1_HVT_$_IQ + + +model CLKGATETST_X1_HVT + (CK, E, GCK, SE) +( + model_source = liberty_cell; + cell_type = clock_gating_and; + simulation_function = clock_gating_and; + + input (CK) ( clock_in; ) + input (E) ( func_enable; ) + input (SE) ( test_enable; ) + output (GCK) ( clock_out; ) + ( + instance = "CLKGATETST_X1_HVT_$_IQ" (CK, E, SE, IQ); + primitive = _and (IQ, CK, GCK); + ) +) // end model CLKGATETST_X1_HVT + + +model "CLKGATETST_X2_HVT_$_IQ" + (CK, E, SE, IQ) +( + model_source = liberty_cell_statetable; + + input (CK) ( ) + input (E) ( ) + input (SE) ( ) + output (IQ) ( ) + ( + primitive = _dlat ( , , clock_net, net_0, IQ, ); + primitive = _inv (CK, clock_net); + primitive = _or (E, SE, net_0); + ) +) // end model CLKGATETST_X2_HVT_$_IQ + + +model CLKGATETST_X2_HVT + (CK, E, GCK, SE) +( + model_source = liberty_cell; + cell_type = clock_gating_and; + simulation_function = clock_gating_and; + + input (CK) ( clock_in; ) + input (E) ( func_enable; ) + input (SE) ( test_enable; ) + output (GCK) ( clock_out; ) + ( + instance = "CLKGATETST_X2_HVT_$_IQ" (CK, E, SE, IQ); + primitive = _and (IQ, CK, GCK); + ) +) // end model CLKGATETST_X2_HVT + + +model "CLKGATETST_X4_HVT_$_IQ" + (CK, E, SE, IQ) +( + model_source = liberty_cell_statetable; + + input (CK) ( ) + input (E) ( ) + input (SE) ( ) + output (IQ) ( ) + ( + primitive = _dlat ( , , clock_net, net_0, IQ, ); + primitive = _inv (CK, clock_net); + primitive = _or (E, SE, net_0); + ) +) // end model CLKGATETST_X4_HVT_$_IQ + + +model CLKGATETST_X4_HVT + (CK, E, GCK, SE) +( + model_source = liberty_cell; + cell_type = clock_gating_and; + simulation_function = clock_gating_and; + + input (CK) ( clock_in; ) + input (E) ( func_enable; ) + input (SE) ( test_enable; ) + output (GCK) ( clock_out; ) + ( + instance = "CLKGATETST_X4_HVT_$_IQ" (CK, E, SE, IQ); + primitive = _and (IQ, CK, GCK); + ) +) // end model CLKGATETST_X4_HVT + + +model "CLKGATETST_X8_HVT_$_IQ" + (CK, E, SE, IQ) +( + model_source = liberty_cell_statetable; + + input (CK) ( ) + input (E) ( ) + input (SE) ( ) + output (IQ) ( ) + ( + primitive = _dlat ( , , clock_net, net_0, IQ, ); + primitive = _inv (CK, clock_net); + primitive = _or (E, SE, net_0); + ) +) // end model CLKGATETST_X8_HVT_$_IQ + + +model CLKGATETST_X8_HVT + (CK, E, GCK, SE) +( + model_source = liberty_cell; + cell_type = clock_gating_and; + simulation_function = clock_gating_and; + + input (CK) ( clock_in; ) + input (E) ( func_enable; ) + input (SE) ( test_enable; ) + output (GCK) ( clock_out; ) + ( + instance = "CLKGATETST_X8_HVT_$_IQ" (CK, E, SE, IQ); + primitive = _and (IQ, CK, GCK); + ) +) // end model CLKGATETST_X8_HVT + + +model "CLKGATE_X1_HVT_$_IQ" + (CK, E, IQ) +( + model_source = liberty_cell_statetable; + simulation_function = latch; + + input (CK) ( active_low_clock; ) + input (E) ( data_in; ) + output (IQ) ( data_out; ) + ( + primitive = _dlat ( , , clock_net, E, IQ, ); + primitive = _inv (CK, clock_net); + ) +) // end model CLKGATE_X1_HVT_$_IQ + + +model CLKGATE_X1_HVT + (CK, E, GCK) +( + model_source = liberty_cell; + + input (CK) ( active_low_clock; ) + input (E) ( ) + output (GCK) ( ) + ( + instance = "CLKGATE_X1_HVT_$_IQ" (CK, E, IQ); + primitive = _and (CK, IQ, GCK); + ) +) // end model CLKGATE_X1_HVT + + +model "CLKGATE_X2_HVT_$_IQ" + (CK, E, IQ) +( + model_source = liberty_cell_statetable; + simulation_function = latch; + + input (CK) ( active_low_clock; ) + input (E) ( data_in; ) + output (IQ) ( data_out; ) + ( + primitive = _dlat ( , , clock_net, E, IQ, ); + primitive = _inv (CK, clock_net); + ) +) // end model CLKGATE_X2_HVT_$_IQ + + +model CLKGATE_X2_HVT + (CK, E, GCK) +( + model_source = liberty_cell; + + input (CK) ( active_low_clock; ) + input (E) ( ) + output (GCK) ( ) + ( + instance = "CLKGATE_X2_HVT_$_IQ" (CK, E, IQ); + primitive = _and (CK, IQ, GCK); + ) +) // end model CLKGATE_X2_HVT + + +model "CLKGATE_X4_HVT_$_IQ" + (CK, E, IQ) +( + model_source = liberty_cell_statetable; + simulation_function = latch; + + input (CK) ( active_low_clock; ) + input (E) ( data_in; ) + output (IQ) ( data_out; ) + ( + primitive = _dlat ( , , clock_net, E, IQ, ); + primitive = _inv (CK, clock_net); + ) +) // end model CLKGATE_X4_HVT_$_IQ + + +model CLKGATE_X4_HVT + (CK, E, GCK) +( + model_source = liberty_cell; + + input (CK) ( active_low_clock; ) + input (E) ( ) + output (GCK) ( ) + ( + instance = "CLKGATE_X4_HVT_$_IQ" (CK, E, IQ); + primitive = _and (CK, IQ, GCK); + ) +) // end model CLKGATE_X4_HVT + + +model "CLKGATE_X8_HVT_$_IQ" + (CK, E, IQ) +( + model_source = liberty_cell_statetable; + simulation_function = latch; + + input (CK) ( active_low_clock; ) + input (E) ( data_in; ) + output (IQ) ( data_out; ) + ( + primitive = _dlat ( , , clock_net, E, IQ, ); + primitive = _inv (CK, clock_net); + ) +) // end model CLKGATE_X8_HVT_$_IQ + + +model CLKGATE_X8_HVT + (CK, E, GCK) +( + model_source = liberty_cell; + + input (CK) ( active_low_clock; ) + input (E) ( ) + output (GCK) ( ) + ( + instance = "CLKGATE_X8_HVT_$_IQ" (CK, E, IQ); + primitive = _and (CK, IQ, GCK); + ) +) // end model CLKGATE_X8_HVT + + +model DFFRS_X1_HVT + (CK, D, Q, QN, + RN, SN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFFRS_X1_HVT, SDFFRS_X2_HVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SN) ( active_low_set; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff (net_0, net_1, CK, D, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _inv (RN, net_1); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFRS_X1_HVT + + +model DFFRS_X2_HVT + (CK, D, Q, QN, + RN, SN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFFRS_X2_HVT, SDFFRS_X1_HVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SN) ( active_low_set; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff (net_0, net_1, CK, D, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _inv (RN, net_1); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFRS_X2_HVT + + +model DFFR_X1_HVT + (CK, D, Q, QN, + RN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFFR_X1_HVT, SDFFR_X2_HVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff ( , net_0, CK, D, IQ, IQN); + primitive = _inv (RN, net_0); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFR_X1_HVT + + +model DFFR_X2_HVT + (CK, D, Q, QN, + RN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFFR_X2_HVT, SDFFR_X1_HVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff ( , net_0, CK, D, IQ, IQN); + primitive = _inv (RN, net_0); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFR_X2_HVT + + +model DFFS_X1_HVT + (CK, D, Q, QN, + SN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFFS_X1_HVT, SDFFS_X2_HVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SN) ( active_low_set; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff (net_0, , CK, D, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFS_X1_HVT + + +model DFFS_X2_HVT + (CK, D, Q, QN, + SN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFFS_X2_HVT, SDFFS_X1_HVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SN) ( active_low_set; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff (net_0, , CK, D, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFS_X2_HVT + + +model DFF_X1_HVT + (CK, D, Q, QN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFF_X1_HVT, SDFF_X2_HVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff ( , , CK, D, IQ, IQN); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFF_X1_HVT + + +model DFF_X2_HVT + (CK, D, Q, QN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFF_X1_HVT, SDFF_X2_HVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff ( , , CK, D, IQ, IQN); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFF_X2_HVT + + +model DLH_X1_HVT + (D, G, Q) +( + model_source = liberty_cell; + cell_type = latch; + simulation_function = latch; + + input (D) ( data_in; ) + input (G) ( active_high_clock; ) + output (Q) ( data_out; ) + ( + primitive = _dlat ( , , G, D, IQ, ); + primitive = _buf (IQ, Q); + ) +) // end model DLH_X1_HVT + + +model DLH_X2_HVT + (D, G, Q) +( + model_source = liberty_cell; + cell_type = latch; + simulation_function = latch; + + input (D) ( data_in; ) + input (G) ( active_high_clock; ) + output (Q) ( data_out; ) + ( + primitive = _dlat ( , , G, D, IQ, ); + primitive = _buf (IQ, Q); + ) +) // end model DLH_X2_HVT + + +model DLL_X1_HVT + (D, GN, Q) +( + model_source = liberty_cell; + cell_type = latch; + simulation_function = latch; + + input (D) ( data_in; ) + input (GN) ( active_low_clock; ) + output (Q) ( data_out; ) + ( + primitive = _dlat ( , , net_0, D, IQ, ); + primitive = _inv (GN, net_0); + primitive = _buf (IQ, Q); + ) +) // end model DLL_X1_HVT + + +model DLL_X2_HVT + (D, GN, Q) +( + model_source = liberty_cell; + cell_type = latch; + simulation_function = latch; + + input (D) ( data_in; ) + input (GN) ( active_low_clock; ) + output (Q) ( data_out; ) + ( + primitive = _dlat ( , , net_0, D, IQ, ); + primitive = _inv (GN, net_0); + primitive = _buf (IQ, Q); + ) +) // end model DLL_X2_HVT + + +model FA_X1_HVT + (A, B, CI, CO, + S) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (CI) ( ) + output (CO) ( ) + output (S) ( ) + ( + primitive = _or (net_0, net_1, CO); + primitive = _and (A, B, net_0); + primitive = _and (CI, net_2, net_1); + primitive = _or (A, B, net_2); + primitive = _xor (CI, net_3, S); + primitive = _xor (A, B, net_3); + ) +) // end model FA_X1_HVT + + +model FILLCELL_X16_HVT + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X16_HVT + + +model FILLCELL_X1_HVT + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X1_HVT + + +model FILLCELL_X2_HVT + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X2_HVT + + +model FILLCELL_X32_HVT + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X32_HVT + + +model FILLCELL_X4_HVT + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X4_HVT + + +model FILLCELL_X8_HVT + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X8_HVT + + +model HA_X1_HVT + (A, B, CO, S) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + output (CO) ( ) + output (S) ( ) + ( + primitive = _and (A, B, CO); + primitive = _xor (A, B, S); + ) +) // end model HA_X1_HVT + + +model INV_X16_HVT + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X16_HVT + + +model INV_X1_HVT + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X1_HVT + + +model INV_X2_HVT + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X2_HVT + + +model INV_X32_HVT + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X32_HVT + + +model INV_X4_HVT + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X4_HVT + + +model INV_X8_HVT + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X8_HVT + + +model LOGIC0_X1_HVT + (Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = tie0; + + output (Z) ( ) + ( + primitive = _tie0 (Z); + ) +) // end model LOGIC0_X1_HVT + + +model LOGIC1_X1_HVT + (Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = tie1; + + output (Z) ( ) + ( + primitive = _tie1 (Z); + ) +) // end model LOGIC1_X1_HVT + + +model MUX2_X1_HVT + (A, B, S, Z) +( + model_source = liberty_cell; + cell_type = mux; + simulation_function = mux; + + input (A) ( mux_in0; ) + input (B) ( mux_in1; ) + input (S) ( mux_select; ) + output (Z) ( mux_out; ) + ( + primitive = _or (net_0, net_1, Z); + primitive = _and (S, B, net_0); + primitive = _and (A, net_2, net_1); + primitive = _inv (S, net_2); + ) +) // end model MUX2_X1_HVT + + +model MUX2_X2_HVT + (A, B, S, Z) +( + model_source = liberty_cell; + cell_type = mux; + simulation_function = mux; + + input (A) ( mux_in0; ) + input (B) ( mux_in1; ) + input (S) ( mux_select; ) + output (Z) ( mux_out; ) + ( + primitive = _or (net_0, net_1, Z); + primitive = _and (S, B, net_0); + primitive = _and (A, net_2, net_1); + primitive = _inv (S, net_2); + ) +) // end model MUX2_X2_HVT + + +model NAND2_X1_HVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model NAND2_X1_HVT + + +model NAND2_X2_HVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model NAND2_X2_HVT + + +model NAND2_X4_HVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model NAND2_X4_HVT + + +model NAND3_X1_HVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model NAND3_X1_HVT + + +model NAND3_X2_HVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model NAND3_X2_HVT + + +model NAND3_X4_HVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model NAND3_X4_HVT + + +model NAND4_X1_HVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A4, net_0); + primitive = _and (net_2, A3, net_1); + primitive = _and (A1, A2, net_2); + ) +) // end model NAND4_X1_HVT + + +model NAND4_X2_HVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A4, net_0); + primitive = _and (net_2, A3, net_1); + primitive = _and (A1, A2, net_2); + ) +) // end model NAND4_X2_HVT + + +model NAND4_X4_HVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A4, net_0); + primitive = _and (net_2, A3, net_1); + primitive = _and (A1, A2, net_2); + ) +) // end model NAND4_X4_HVT + + +model NOR2_X1_HVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model NOR2_X1_HVT + + +model NOR2_X2_HVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model NOR2_X2_HVT + + +model NOR2_X4_HVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model NOR2_X4_HVT + + +model NOR3_X1_HVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model NOR3_X1_HVT + + +model NOR3_X2_HVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model NOR3_X2_HVT + + +model NOR3_X4_HVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model NOR3_X4_HVT + + +model NOR4_X1_HVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A4, net_0); + primitive = _or (net_2, A3, net_1); + primitive = _or (A1, A2, net_2); + ) +) // end model NOR4_X1_HVT + + +model NOR4_X2_HVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A4, net_0); + primitive = _or (net_2, A3, net_1); + primitive = _or (A1, A2, net_2); + ) +) // end model NOR4_X2_HVT + + +model NOR4_X4_HVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A4, net_0); + primitive = _or (net_2, A3, net_1); + primitive = _or (A1, A2, net_2); + ) +) // end model NOR4_X4_HVT + + +model OAI211_X1_HVT + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, B, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + ) +) // end model OAI211_X1_HVT + + +model OAI211_X2_HVT + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, B, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + ) +) // end model OAI211_X2_HVT + + +model OAI211_X4_HVT + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, B, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + ) +) // end model OAI211_X4_HVT + + +model OAI21_X1_HVT + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A, net_1, net_0); + primitive = _or (B1, B2, net_1); + ) +) // end model OAI21_X1_HVT + + +model OAI21_X2_HVT + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A, net_1, net_0); + primitive = _or (B1, B2, net_1); + ) +) // end model OAI21_X2_HVT + + +model OAI21_X4_HVT + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A, net_1, net_0); + primitive = _or (B1, B2, net_1); + ) +) // end model OAI21_X4_HVT + + +model OAI221_X1_HVT + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_3, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + primitive = _or (B1, B2, net_3); + ) +) // end model OAI221_X1_HVT + + +model OAI221_X2_HVT + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_3, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + primitive = _or (B1, B2, net_3); + ) +) // end model OAI221_X2_HVT + + +model OAI221_X4_HVT + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _and (net_3, net_5, net_2); + primitive = _and (net_4, A, net_3); + primitive = _or (C1, C2, net_4); + primitive = _or (B1, B2, net_5); + ) +) // end model OAI221_X4_HVT + + +model OAI222_X1_HVT + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_4, net_0); + primitive = _and (net_2, net_3, net_1); + primitive = _or (A1, A2, net_2); + primitive = _or (B1, B2, net_3); + primitive = _or (C1, C2, net_4); + ) +) // end model OAI222_X1_HVT + + +model OAI222_X2_HVT + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_4, net_0); + primitive = _and (net_2, net_3, net_1); + primitive = _or (A1, A2, net_2); + primitive = _or (B1, B2, net_3); + primitive = _or (C1, C2, net_4); + ) +) // end model OAI222_X2_HVT + + +model OAI222_X4_HVT + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _and (net_3, net_6, net_2); + primitive = _and (net_4, net_5, net_3); + primitive = _or (A1, A2, net_4); + primitive = _or (B1, B2, net_5); + primitive = _or (C1, C2, net_6); + ) +) // end model OAI222_X4_HVT + + +model OAI22_X1_HVT + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_2, net_0); + primitive = _or (A1, A2, net_1); + primitive = _or (B1, B2, net_2); + ) +) // end model OAI22_X1_HVT + + +model OAI22_X2_HVT + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_2, net_0); + primitive = _or (A1, A2, net_1); + primitive = _or (B1, B2, net_2); + ) +) // end model OAI22_X2_HVT + + +model OAI22_X4_HVT + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_2, net_0); + primitive = _or (A1, A2, net_1); + primitive = _or (B1, B2, net_2); + ) +) // end model OAI22_X4_HVT + + +model OAI33_X1_HVT + (A1, A2, A3, B1, + B2, B3, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (B1) ( ) + input (B2) ( ) + input (B3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_3, net_0); + primitive = _or (net_2, A3, net_1); + primitive = _or (A1, A2, net_2); + primitive = _or (net_4, B3, net_3); + primitive = _or (B1, B2, net_4); + ) +) // end model OAI33_X1_HVT + + +model OR2_X1_HVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _or (A1, A2, ZN); + ) +) // end model OR2_X1_HVT + + +model OR2_X2_HVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _or (A1, A2, ZN); + ) +) // end model OR2_X2_HVT + + +model OR2_X4_HVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _or (A1, A2, ZN); + ) +) // end model OR2_X4_HVT + + +model OR3_X1_HVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A3, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model OR3_X1_HVT + + +model OR3_X2_HVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A3, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model OR3_X2_HVT + + +model OR3_X4_HVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A3, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model OR3_X4_HVT + + +model OR4_X1_HVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A4, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model OR4_X1_HVT + + +model OR4_X2_HVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A4, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model OR4_X2_HVT + + +model OR4_X4_HVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A4, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model OR4_X4_HVT + + +model SDFFRS_X1_HVT + (CK, D, Q, QN, + RN, SE, SI, SN) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFFRS_X1_HVT, DFFRS_X2_HVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + input (SN) ( active_low_set; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff (net_0, net_1, CK, net_2, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _inv (RN, net_1); + primitive = _or (net_3, net_4, net_2); + primitive = _and (SE, SI, net_3); + primitive = _and (D, net_5, net_4); + primitive = _inv (SE, net_5); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFRS_X1_HVT + + +model SDFFRS_X2_HVT + (CK, D, Q, QN, + RN, SE, SI, SN) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFFRS_X2_HVT, DFFRS_X1_HVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + input (SN) ( active_low_set; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff (net_0, net_1, CK, net_2, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _inv (RN, net_1); + primitive = _or (net_3, net_4, net_2); + primitive = _and (SE, SI, net_3); + primitive = _and (D, net_5, net_4); + primitive = _inv (SE, net_5); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFRS_X2_HVT + + +model SDFFR_X1_HVT + (CK, D, Q, QN, + RN, SE, SI) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFFR_X1_HVT, DFFR_X2_HVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff ( , net_0, CK, net_1, IQ, IQN); + primitive = _inv (RN, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (SE, SI, net_2); + primitive = _and (D, net_4, net_3); + primitive = _inv (SE, net_4); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFR_X1_HVT + + +model SDFFR_X2_HVT + (CK, D, Q, QN, + RN, SE, SI) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFFR_X2_HVT, DFFR_X1_HVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff ( , net_0, CK, net_1, IQ, IQN); + primitive = _inv (RN, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (SE, SI, net_2); + primitive = _and (D, net_4, net_3); + primitive = _inv (SE, net_4); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFR_X2_HVT + + +model SDFFS_X1_HVT + (CK, D, Q, QN, + SE, SI, SN) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFFS_X1_HVT, DFFS_X2_HVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + input (SN) ( active_low_set; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff (net_0, , CK, net_1, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (SE, SI, net_2); + primitive = _and (D, net_4, net_3); + primitive = _inv (SE, net_4); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFS_X1_HVT + + +model SDFFS_X2_HVT + (CK, D, Q, QN, + SE, SI, SN) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFFS_X2_HVT, DFFS_X1_HVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + input (SN) ( active_low_set; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff (net_0, , CK, net_1, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (SE, SI, net_2); + primitive = _and (D, net_4, net_3); + primitive = _inv (SE, net_4); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFS_X2_HVT + + +model SDFF_X1_HVT + (CK, D, Q, QN, + SE, SI) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFF_X1_HVT, DFF_X2_HVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff ( , , CK, net_0, IQ, IQN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (SE, SI, net_1); + primitive = _and (D, net_3, net_2); + primitive = _inv (SE, net_3); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFF_X1_HVT + + +model SDFF_X2_HVT + (CK, D, Q, QN, + SE, SI) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFF_X1_HVT, DFF_X2_HVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff ( , , CK, net_0, IQ, IQN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (SE, SI, net_1); + primitive = _and (D, net_3, net_2); + primitive = _inv (SE, net_3); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFF_X2_HVT + + +model TBUF_X16_HVT + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X16_HVT + + +model TBUF_X1_HVT + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X1_HVT + + +model TBUF_X2_HVT + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X2_HVT + + +model TBUF_X4_HVT + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X4_HVT + + +model TBUF_X8_HVT + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X8_HVT + + +model TINV_X1_HVT + (EN, I, ZN) +( + model_source = liberty_cell; + + input (EN) ( ) + input (I) ( ) + output (ZN) ( ) + ( + primitive = _tsl (net_0, EN, ZN); + primitive = _inv (I, net_0); + ) +) // end model TINV_X1_HVT + + +model TLAT_X1_HVT + (D, G, OE, Q) +( + model_source = liberty_cell; + + input (D) ( ) + input (G) ( active_high_clock; ) + input (OE) ( ) + output (Q) ( ) + ( + primitive = _dlat ( , , G, D, IQ, ); + primitive = _tsl (IQ, net_0, Q); + primitive = _inv (OE, net_0); + ) +) // end model TLAT_X1_HVT + + +model XNOR2_X1_HVT + (A, B, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _xor (A, B, net_0); + ) +) // end model XNOR2_X1_HVT + + +model XNOR2_X2_HVT + (A, B, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _xor (A, B, net_0); + ) +) // end model XNOR2_X2_HVT + + +model XOR2_X1_HVT + (A, B, Z) +( + model_source = liberty_cell; + cell_type = xor; + simulation_function = xor; + + input (A) ( ) + input (B) ( ) + output (Z) ( ) + ( + primitive = _xor (A, B, Z); + ) +) // end model XOR2_X1_HVT + + +model XOR2_X2_HVT + (A, B, Z) +( + model_source = liberty_cell; + cell_type = xor; + simulation_function = xor; + + input (A) ( ) + input (B) ( ) + output (Z) ( ) + ( + primitive = _xor (A, B, Z); + ) +) // end model XOR2_X2_HVT diff --git a/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.fslib b/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.fslib new file mode 100755 index 0000000..7f836a7 --- /dev/null +++ b/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.fslib @@ -0,0 +1,2665 @@ +// +// *********************************************************************** +// Copyright Mentor Graphics Corporation +// All Rights Reserved +// For use only with Mentor Graphics Tessent tools +// *********************************************************************** +// File Type: Tessent Cell Library +// Generated by: Tessent Shell -- write_cell_library +// Tool Version: 2019.4 +// Tool Build Date: Wed Nov 20 21:14:16 GMT 2019 +// *********************************************************************** +// Library Created : Local Time = Tue Jun 30 00:33:33 2020 +// GMT = Tue Jun 30 07:33:33 2020 + + +library_format_version = 9; + +array_delimiter = "[]"; + + +// +// *********************************************************************** +// *********** Models holding Liberty information ****************** +// *********************************************************************** +// + + +model AND2_X1_HVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _and (A1, A2, ZN); + ) +) // end model AND2_X1_HVT + + +model AND2_X2_HVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _and (A1, A2, ZN); + ) +) // end model AND2_X2_HVT + + +model AND2_X4_HVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _and (A1, A2, ZN); + ) +) // end model AND2_X4_HVT + + +model AND3_X1_HVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A3, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model AND3_X1_HVT + + +model AND3_X2_HVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A3, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model AND3_X2_HVT + + +model AND3_X4_HVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A3, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model AND3_X4_HVT + + +model AND4_X1_HVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A4, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model AND4_X1_HVT + + +model AND4_X2_HVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A4, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model AND4_X2_HVT + + +model AND4_X4_HVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A4, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model AND4_X4_HVT + + +model ANTENNA_X1_HVT + (A) +( + model_source = liberty_cell; + cell_type = prohibited; + + input (A) ( ) + ( + // Empty Model + ) +) // end model ANTENNA_X1_HVT + + +model AOI211_X1_HVT + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A, net_0); + primitive = _or (net_2, B, net_1); + primitive = _and (C1, C2, net_2); + ) +) // end model AOI211_X1_HVT + + +model AOI211_X2_HVT + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A, net_0); + primitive = _or (net_2, B, net_1); + primitive = _and (C1, C2, net_2); + ) +) // end model AOI211_X2_HVT + + +model AOI211_X4_HVT + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _or (net_3, A, net_2); + primitive = _or (net_4, B, net_3); + primitive = _and (C1, C2, net_4); + ) +) // end model AOI211_X4_HVT + + +model AOI21_X1_HVT + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A, net_1, net_0); + primitive = _and (B1, B2, net_1); + ) +) // end model AOI21_X1_HVT + + +model AOI21_X2_HVT + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A, net_1, net_0); + primitive = _and (B1, B2, net_1); + ) +) // end model AOI21_X2_HVT + + +model AOI21_X4_HVT + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A, net_1, net_0); + primitive = _and (B1, B2, net_1); + ) +) // end model AOI21_X4_HVT + + +model AOI221_X1_HVT + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_3, net_0); + primitive = _or (net_2, A, net_1); + primitive = _and (C1, C2, net_2); + primitive = _and (B1, B2, net_3); + ) +) // end model AOI221_X1_HVT + + +model AOI221_X2_HVT + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_3, net_0); + primitive = _or (net_2, A, net_1); + primitive = _and (C1, C2, net_2); + primitive = _and (B1, B2, net_3); + ) +) // end model AOI221_X2_HVT + + +model AOI221_X4_HVT + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _or (net_3, net_5, net_2); + primitive = _or (net_4, A, net_3); + primitive = _and (C1, C2, net_4); + primitive = _and (B1, B2, net_5); + ) +) // end model AOI221_X4_HVT + + +model AOI222_X1_HVT + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_4, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (A1, A2, net_2); + primitive = _and (B1, B2, net_3); + primitive = _and (C1, C2, net_4); + ) +) // end model AOI222_X1_HVT + + +model AOI222_X2_HVT + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_4, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (A1, A2, net_2); + primitive = _and (B1, B2, net_3); + primitive = _and (C1, C2, net_4); + ) +) // end model AOI222_X2_HVT + + +model AOI222_X4_HVT + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _or (net_3, net_6, net_2); + primitive = _or (net_4, net_5, net_3); + primitive = _and (A1, A2, net_4); + primitive = _and (B1, B2, net_5); + primitive = _and (C1, C2, net_6); + ) +) // end model AOI222_X4_HVT + + +model AOI22_X1_HVT + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (A1, A2, net_1); + primitive = _and (B1, B2, net_2); + ) +) // end model AOI22_X1_HVT + + +model AOI22_X2_HVT + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (A1, A2, net_1); + primitive = _and (B1, B2, net_2); + ) +) // end model AOI22_X2_HVT + + +model AOI22_X4_HVT + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (A1, A2, net_1); + primitive = _and (B1, B2, net_2); + ) +) // end model AOI22_X4_HVT + + +model BUF_X16_HVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X16_HVT + + +model BUF_X1_HVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X1_HVT + + +model BUF_X2_HVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X2_HVT + + +model BUF_X32_HVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X32_HVT + + +model BUF_X4_HVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X4_HVT + + +model BUF_X8_HVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X8_HVT + + +model CLKBUF_X1_HVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model CLKBUF_X1_HVT + + +model CLKBUF_X2_HVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model CLKBUF_X2_HVT + + +model CLKBUF_X3_HVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model CLKBUF_X3_HVT + + +model "CLKGATETST_X1_HVT_$_IQ" + (CK, E, SE, IQ) +( + model_source = liberty_cell_statetable; + + input (CK) ( ) + input (E) ( ) + input (SE) ( ) + output (IQ) ( ) + ( + primitive = _dlat ( , , clock_net, net_0, IQ, ); + primitive = _inv (CK, clock_net); + primitive = _or (E, SE, net_0); + ) +) // end model CLKGATETST_X1_HVT_$_IQ + + +model CLKGATETST_X1_HVT + (CK, E, GCK, SE) +( + model_source = liberty_cell; + cell_type = clock_gating_and; + simulation_function = clock_gating_and; + + input (CK) ( clock_in; ) + input (E) ( func_enable; ) + input (SE) ( test_enable; ) + output (GCK) ( clock_out; ) + ( + instance = "CLKGATETST_X1_HVT_$_IQ" (CK, E, SE, IQ); + primitive = _and (IQ, CK, GCK); + ) +) // end model CLKGATETST_X1_HVT + + +model "CLKGATETST_X2_HVT_$_IQ" + (CK, E, SE, IQ) +( + model_source = liberty_cell_statetable; + + input (CK) ( ) + input (E) ( ) + input (SE) ( ) + output (IQ) ( ) + ( + primitive = _dlat ( , , clock_net, net_0, IQ, ); + primitive = _inv (CK, clock_net); + primitive = _or (E, SE, net_0); + ) +) // end model CLKGATETST_X2_HVT_$_IQ + + +model CLKGATETST_X2_HVT + (CK, E, GCK, SE) +( + model_source = liberty_cell; + cell_type = clock_gating_and; + simulation_function = clock_gating_and; + + input (CK) ( clock_in; ) + input (E) ( func_enable; ) + input (SE) ( test_enable; ) + output (GCK) ( clock_out; ) + ( + instance = "CLKGATETST_X2_HVT_$_IQ" (CK, E, SE, IQ); + primitive = _and (IQ, CK, GCK); + ) +) // end model CLKGATETST_X2_HVT + + +model "CLKGATETST_X4_HVT_$_IQ" + (CK, E, SE, IQ) +( + model_source = liberty_cell_statetable; + + input (CK) ( ) + input (E) ( ) + input (SE) ( ) + output (IQ) ( ) + ( + primitive = _dlat ( , , clock_net, net_0, IQ, ); + primitive = _inv (CK, clock_net); + primitive = _or (E, SE, net_0); + ) +) // end model CLKGATETST_X4_HVT_$_IQ + + +model CLKGATETST_X4_HVT + (CK, E, GCK, SE) +( + model_source = liberty_cell; + cell_type = clock_gating_and; + simulation_function = clock_gating_and; + + input (CK) ( clock_in; ) + input (E) ( func_enable; ) + input (SE) ( test_enable; ) + output (GCK) ( clock_out; ) + ( + instance = "CLKGATETST_X4_HVT_$_IQ" (CK, E, SE, IQ); + primitive = _and (IQ, CK, GCK); + ) +) // end model CLKGATETST_X4_HVT + + +model "CLKGATETST_X8_HVT_$_IQ" + (CK, E, SE, IQ) +( + model_source = liberty_cell_statetable; + + input (CK) ( ) + input (E) ( ) + input (SE) ( ) + output (IQ) ( ) + ( + primitive = _dlat ( , , clock_net, net_0, IQ, ); + primitive = _inv (CK, clock_net); + primitive = _or (E, SE, net_0); + ) +) // end model CLKGATETST_X8_HVT_$_IQ + + +model CLKGATETST_X8_HVT + (CK, E, GCK, SE) +( + model_source = liberty_cell; + cell_type = clock_gating_and; + simulation_function = clock_gating_and; + + input (CK) ( clock_in; ) + input (E) ( func_enable; ) + input (SE) ( test_enable; ) + output (GCK) ( clock_out; ) + ( + instance = "CLKGATETST_X8_HVT_$_IQ" (CK, E, SE, IQ); + primitive = _and (IQ, CK, GCK); + ) +) // end model CLKGATETST_X8_HVT + + +model "CLKGATE_X1_HVT_$_IQ" + (CK, E, IQ) +( + model_source = liberty_cell_statetable; + simulation_function = latch; + + input (CK) ( active_low_clock; ) + input (E) ( data_in; ) + output (IQ) ( data_out; ) + ( + primitive = _dlat ( , , clock_net, E, IQ, ); + primitive = _inv (CK, clock_net); + ) +) // end model CLKGATE_X1_HVT_$_IQ + + +model CLKGATE_X1_HVT + (CK, E, GCK) +( + model_source = liberty_cell; + + input (CK) ( active_low_clock; ) + input (E) ( ) + output (GCK) ( ) + ( + instance = "CLKGATE_X1_HVT_$_IQ" (CK, E, IQ); + primitive = _and (CK, IQ, GCK); + ) +) // end model CLKGATE_X1_HVT + + +model "CLKGATE_X2_HVT_$_IQ" + (CK, E, IQ) +( + model_source = liberty_cell_statetable; + simulation_function = latch; + + input (CK) ( active_low_clock; ) + input (E) ( data_in; ) + output (IQ) ( data_out; ) + ( + primitive = _dlat ( , , clock_net, E, IQ, ); + primitive = _inv (CK, clock_net); + ) +) // end model CLKGATE_X2_HVT_$_IQ + + +model CLKGATE_X2_HVT + (CK, E, GCK) +( + model_source = liberty_cell; + + input (CK) ( active_low_clock; ) + input (E) ( ) + output (GCK) ( ) + ( + instance = "CLKGATE_X2_HVT_$_IQ" (CK, E, IQ); + primitive = _and (CK, IQ, GCK); + ) +) // end model CLKGATE_X2_HVT + + +model "CLKGATE_X4_HVT_$_IQ" + (CK, E, IQ) +( + model_source = liberty_cell_statetable; + simulation_function = latch; + + input (CK) ( active_low_clock; ) + input (E) ( data_in; ) + output (IQ) ( data_out; ) + ( + primitive = _dlat ( , , clock_net, E, IQ, ); + primitive = _inv (CK, clock_net); + ) +) // end model CLKGATE_X4_HVT_$_IQ + + +model CLKGATE_X4_HVT + (CK, E, GCK) +( + model_source = liberty_cell; + + input (CK) ( active_low_clock; ) + input (E) ( ) + output (GCK) ( ) + ( + instance = "CLKGATE_X4_HVT_$_IQ" (CK, E, IQ); + primitive = _and (CK, IQ, GCK); + ) +) // end model CLKGATE_X4_HVT + + +model "CLKGATE_X8_HVT_$_IQ" + (CK, E, IQ) +( + model_source = liberty_cell_statetable; + simulation_function = latch; + + input (CK) ( active_low_clock; ) + input (E) ( data_in; ) + output (IQ) ( data_out; ) + ( + primitive = _dlat ( , , clock_net, E, IQ, ); + primitive = _inv (CK, clock_net); + ) +) // end model CLKGATE_X8_HVT_$_IQ + + +model CLKGATE_X8_HVT + (CK, E, GCK) +( + model_source = liberty_cell; + + input (CK) ( active_low_clock; ) + input (E) ( ) + output (GCK) ( ) + ( + instance = "CLKGATE_X8_HVT_$_IQ" (CK, E, IQ); + primitive = _and (CK, IQ, GCK); + ) +) // end model CLKGATE_X8_HVT + + +model DFFRS_X1_HVT + (CK, D, Q, QN, + RN, SN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFFRS_X1_HVT, SDFFRS_X2_HVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SN) ( active_low_set; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff (net_0, net_1, CK, D, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _inv (RN, net_1); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFRS_X1_HVT + + +model DFFRS_X2_HVT + (CK, D, Q, QN, + RN, SN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFFRS_X2_HVT, SDFFRS_X1_HVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SN) ( active_low_set; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff (net_0, net_1, CK, D, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _inv (RN, net_1); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFRS_X2_HVT + + +model DFFR_X1_HVT + (CK, D, Q, QN, + RN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFFR_X1_HVT, SDFFR_X2_HVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff ( , net_0, CK, D, IQ, IQN); + primitive = _inv (RN, net_0); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFR_X1_HVT + + +model DFFR_X2_HVT + (CK, D, Q, QN, + RN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFFR_X2_HVT, SDFFR_X1_HVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff ( , net_0, CK, D, IQ, IQN); + primitive = _inv (RN, net_0); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFR_X2_HVT + + +model DFFS_X1_HVT + (CK, D, Q, QN, + SN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFFS_X1_HVT, SDFFS_X2_HVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SN) ( active_low_set; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff (net_0, , CK, D, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFS_X1_HVT + + +model DFFS_X2_HVT + (CK, D, Q, QN, + SN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFFS_X2_HVT, SDFFS_X1_HVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SN) ( active_low_set; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff (net_0, , CK, D, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFS_X2_HVT + + +model DFF_X1_HVT + (CK, D, Q, QN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFF_X1_HVT, SDFF_X2_HVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff ( , , CK, D, IQ, IQN); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFF_X1_HVT + + +model DFF_X2_HVT + (CK, D, Q, QN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFF_X2_HVT, SDFF_X1_HVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff ( , , CK, D, IQ, IQN); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFF_X2_HVT + + +model DLH_X1_HVT + (D, G, Q) +( + model_source = liberty_cell; + cell_type = latch; + simulation_function = latch; + + input (D) ( data_in; ) + input (G) ( active_high_clock; ) + output (Q) ( data_out; ) + ( + primitive = _dlat ( , , G, D, IQ, ); + primitive = _buf (IQ, Q); + ) +) // end model DLH_X1_HVT + + +model DLH_X2_HVT + (D, G, Q) +( + model_source = liberty_cell; + cell_type = latch; + simulation_function = latch; + + input (D) ( data_in; ) + input (G) ( active_high_clock; ) + output (Q) ( data_out; ) + ( + primitive = _dlat ( , , G, D, IQ, ); + primitive = _buf (IQ, Q); + ) +) // end model DLH_X2_HVT + + +model DLL_X1_HVT + (D, GN, Q) +( + model_source = liberty_cell; + cell_type = latch; + simulation_function = latch; + + input (D) ( data_in; ) + input (GN) ( active_low_clock; ) + output (Q) ( data_out; ) + ( + primitive = _dlat ( , , net_0, D, IQ, ); + primitive = _inv (GN, net_0); + primitive = _buf (IQ, Q); + ) +) // end model DLL_X1_HVT + + +model DLL_X2_HVT + (D, GN, Q) +( + model_source = liberty_cell; + cell_type = latch; + simulation_function = latch; + + input (D) ( data_in; ) + input (GN) ( active_low_clock; ) + output (Q) ( data_out; ) + ( + primitive = _dlat ( , , net_0, D, IQ, ); + primitive = _inv (GN, net_0); + primitive = _buf (IQ, Q); + ) +) // end model DLL_X2_HVT + + +model FA_X1_HVT + (A, B, CI, CO, + S) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (CI) ( ) + output (CO) ( ) + output (S) ( ) + ( + primitive = _or (net_0, net_1, CO); + primitive = _and (A, B, net_0); + primitive = _and (CI, net_2, net_1); + primitive = _or (A, B, net_2); + primitive = _xor (CI, net_3, S); + primitive = _xor (A, B, net_3); + ) +) // end model FA_X1_HVT + + +model FILLCELL_X16_HVT + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X16_HVT + + +model FILLCELL_X1_HVT + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X1_HVT + + +model FILLCELL_X2_HVT + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X2_HVT + + +model FILLCELL_X32_HVT + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X32_HVT + + +model FILLCELL_X4_HVT + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X4_HVT + + +model FILLCELL_X8_HVT + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X8_HVT + + +model HA_X1_HVT + (A, B, CO, S) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + output (CO) ( ) + output (S) ( ) + ( + primitive = _and (A, B, CO); + primitive = _xor (A, B, S); + ) +) // end model HA_X1_HVT + + +model INV_X16_HVT + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X16_HVT + + +model INV_X1_HVT + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X1_HVT + + +model INV_X2_HVT + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X2_HVT + + +model INV_X32_HVT + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X32_HVT + + +model INV_X4_HVT + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X4_HVT + + +model INV_X8_HVT + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X8_HVT + + +model LOGIC0_X1_HVT + (Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = tie0; + + output (Z) ( ) + ( + primitive = _tie0 (Z); + ) +) // end model LOGIC0_X1_HVT + + +model LOGIC1_X1_HVT + (Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = tie1; + + output (Z) ( ) + ( + primitive = _tie1 (Z); + ) +) // end model LOGIC1_X1_HVT + + +model MUX2_X1_HVT + (A, B, S, Z) +( + model_source = liberty_cell; + cell_type = mux; + simulation_function = mux; + + input (A) ( mux_in0; ) + input (B) ( mux_in1; ) + input (S) ( mux_select; ) + output (Z) ( mux_out; ) + ( + primitive = _or (net_0, net_1, Z); + primitive = _and (S, B, net_0); + primitive = _and (A, net_2, net_1); + primitive = _inv (S, net_2); + ) +) // end model MUX2_X1_HVT + + +model MUX2_X2_HVT + (A, B, S, Z) +( + model_source = liberty_cell; + cell_type = mux; + simulation_function = mux; + + input (A) ( mux_in0; ) + input (B) ( mux_in1; ) + input (S) ( mux_select; ) + output (Z) ( mux_out; ) + ( + primitive = _or (net_0, net_1, Z); + primitive = _and (S, B, net_0); + primitive = _and (A, net_2, net_1); + primitive = _inv (S, net_2); + ) +) // end model MUX2_X2_HVT + + +model NAND2_X1_HVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model NAND2_X1_HVT + + +model NAND2_X2_HVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model NAND2_X2_HVT + + +model NAND2_X4_HVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model NAND2_X4_HVT + + +model NAND3_X1_HVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model NAND3_X1_HVT + + +model NAND3_X2_HVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model NAND3_X2_HVT + + +model NAND3_X4_HVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model NAND3_X4_HVT + + +model NAND4_X1_HVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A4, net_0); + primitive = _and (net_2, A3, net_1); + primitive = _and (A1, A2, net_2); + ) +) // end model NAND4_X1_HVT + + +model NAND4_X2_HVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A4, net_0); + primitive = _and (net_2, A3, net_1); + primitive = _and (A1, A2, net_2); + ) +) // end model NAND4_X2_HVT + + +model NAND4_X4_HVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A4, net_0); + primitive = _and (net_2, A3, net_1); + primitive = _and (A1, A2, net_2); + ) +) // end model NAND4_X4_HVT + + +model NOR2_X1_HVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model NOR2_X1_HVT + + +model NOR2_X2_HVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model NOR2_X2_HVT + + +model NOR2_X4_HVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model NOR2_X4_HVT + + +model NOR3_X1_HVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model NOR3_X1_HVT + + +model NOR3_X2_HVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model NOR3_X2_HVT + + +model NOR3_X4_HVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model NOR3_X4_HVT + + +model NOR4_X1_HVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A4, net_0); + primitive = _or (net_2, A3, net_1); + primitive = _or (A1, A2, net_2); + ) +) // end model NOR4_X1_HVT + + +model NOR4_X2_HVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A4, net_0); + primitive = _or (net_2, A3, net_1); + primitive = _or (A1, A2, net_2); + ) +) // end model NOR4_X2_HVT + + +model NOR4_X4_HVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A4, net_0); + primitive = _or (net_2, A3, net_1); + primitive = _or (A1, A2, net_2); + ) +) // end model NOR4_X4_HVT + + +model OAI211_X1_HVT + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, B, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + ) +) // end model OAI211_X1_HVT + + +model OAI211_X2_HVT + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, B, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + ) +) // end model OAI211_X2_HVT + + +model OAI211_X4_HVT + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, B, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + ) +) // end model OAI211_X4_HVT + + +model OAI21_X1_HVT + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A, net_1, net_0); + primitive = _or (B1, B2, net_1); + ) +) // end model OAI21_X1_HVT + + +model OAI21_X2_HVT + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A, net_1, net_0); + primitive = _or (B1, B2, net_1); + ) +) // end model OAI21_X2_HVT + + +model OAI21_X4_HVT + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A, net_1, net_0); + primitive = _or (B1, B2, net_1); + ) +) // end model OAI21_X4_HVT + + +model OAI221_X1_HVT + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_3, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + primitive = _or (B1, B2, net_3); + ) +) // end model OAI221_X1_HVT + + +model OAI221_X2_HVT + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_3, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + primitive = _or (B1, B2, net_3); + ) +) // end model OAI221_X2_HVT + + +model OAI221_X4_HVT + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _and (net_3, net_5, net_2); + primitive = _and (net_4, A, net_3); + primitive = _or (C1, C2, net_4); + primitive = _or (B1, B2, net_5); + ) +) // end model OAI221_X4_HVT + + +model OAI222_X1_HVT + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_4, net_0); + primitive = _and (net_2, net_3, net_1); + primitive = _or (A1, A2, net_2); + primitive = _or (B1, B2, net_3); + primitive = _or (C1, C2, net_4); + ) +) // end model OAI222_X1_HVT + + +model OAI222_X2_HVT + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_4, net_0); + primitive = _and (net_2, net_3, net_1); + primitive = _or (A1, A2, net_2); + primitive = _or (B1, B2, net_3); + primitive = _or (C1, C2, net_4); + ) +) // end model OAI222_X2_HVT + + +model OAI222_X4_HVT + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _and (net_3, net_6, net_2); + primitive = _and (net_4, net_5, net_3); + primitive = _or (A1, A2, net_4); + primitive = _or (B1, B2, net_5); + primitive = _or (C1, C2, net_6); + ) +) // end model OAI222_X4_HVT + + +model OAI22_X1_HVT + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_2, net_0); + primitive = _or (A1, A2, net_1); + primitive = _or (B1, B2, net_2); + ) +) // end model OAI22_X1_HVT + + +model OAI22_X2_HVT + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_2, net_0); + primitive = _or (A1, A2, net_1); + primitive = _or (B1, B2, net_2); + ) +) // end model OAI22_X2_HVT + + +model OAI22_X4_HVT + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_2, net_0); + primitive = _or (A1, A2, net_1); + primitive = _or (B1, B2, net_2); + ) +) // end model OAI22_X4_HVT + + +model OAI33_X1_HVT + (A1, A2, A3, B1, + B2, B3, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (B1) ( ) + input (B2) ( ) + input (B3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_3, net_0); + primitive = _or (net_2, A3, net_1); + primitive = _or (A1, A2, net_2); + primitive = _or (net_4, B3, net_3); + primitive = _or (B1, B2, net_4); + ) +) // end model OAI33_X1_HVT + + +model OR2_X1_HVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _or (A1, A2, ZN); + ) +) // end model OR2_X1_HVT + + +model OR2_X2_HVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _or (A1, A2, ZN); + ) +) // end model OR2_X2_HVT + + +model OR2_X4_HVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _or (A1, A2, ZN); + ) +) // end model OR2_X4_HVT + + +model OR3_X1_HVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A3, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model OR3_X1_HVT + + +model OR3_X2_HVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A3, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model OR3_X2_HVT + + +model OR3_X4_HVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A3, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model OR3_X4_HVT + + +model OR4_X1_HVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A4, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model OR4_X1_HVT + + +model OR4_X2_HVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A4, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model OR4_X2_HVT + + +model OR4_X4_HVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A4, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model OR4_X4_HVT + + +model SDFFRS_X1_HVT + (CK, D, Q, QN, + RN, SE, SI, SN) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFFRS_X1_HVT, DFFRS_X2_HVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + input (SN) ( active_low_set; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff (net_0, net_1, CK, net_2, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _inv (RN, net_1); + primitive = _or (net_3, net_4, net_2); + primitive = _and (SE, SI, net_3); + primitive = _and (D, net_5, net_4); + primitive = _inv (SE, net_5); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFRS_X1_HVT + + +model SDFFRS_X2_HVT + (CK, D, Q, QN, + RN, SE, SI, SN) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFFRS_X2_HVT, DFFRS_X1_HVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + input (SN) ( active_low_set; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff (net_0, net_1, CK, net_2, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _inv (RN, net_1); + primitive = _or (net_3, net_4, net_2); + primitive = _and (SE, SI, net_3); + primitive = _and (D, net_5, net_4); + primitive = _inv (SE, net_5); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFRS_X2_HVT + + +model SDFFR_X1_HVT + (CK, D, Q, QN, + RN, SE, SI) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFFR_X1_HVT, DFFR_X2_HVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff ( , net_0, CK, net_1, IQ, IQN); + primitive = _inv (RN, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (SE, SI, net_2); + primitive = _and (D, net_4, net_3); + primitive = _inv (SE, net_4); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFR_X1_HVT + + +model SDFFR_X2_HVT + (CK, D, Q, QN, + RN, SE, SI) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFFR_X2_HVT, DFFR_X1_HVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff ( , net_0, CK, net_1, IQ, IQN); + primitive = _inv (RN, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (SE, SI, net_2); + primitive = _and (D, net_4, net_3); + primitive = _inv (SE, net_4); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFR_X2_HVT + + +model SDFFS_X1_HVT + (CK, D, Q, QN, + SE, SI, SN) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFFS_X1_HVT, DFFS_X2_HVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + input (SN) ( active_low_set; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff (net_0, , CK, net_1, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (SE, SI, net_2); + primitive = _and (D, net_4, net_3); + primitive = _inv (SE, net_4); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFS_X1_HVT + + +model SDFFS_X2_HVT + (CK, D, Q, QN, + SE, SI, SN) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFFS_X2_HVT, DFFS_X1_HVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + input (SN) ( active_low_set; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff (net_0, , CK, net_1, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (SE, SI, net_2); + primitive = _and (D, net_4, net_3); + primitive = _inv (SE, net_4); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFS_X2_HVT + + +model SDFF_X1_HVT + (CK, D, Q, QN, + SE, SI) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFF_X1_HVT, DFF_X2_HVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff ( , , CK, net_0, IQ, IQN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (SE, SI, net_1); + primitive = _and (D, net_3, net_2); + primitive = _inv (SE, net_3); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFF_X1_HVT + + +model SDFF_X2_HVT + (CK, D, Q, QN, + SE, SI) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFF_X2_HVT, DFF_X1_HVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff ( , , CK, net_0, IQ, IQN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (SE, SI, net_1); + primitive = _and (D, net_3, net_2); + primitive = _inv (SE, net_3); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFF_X2_HVT + + +model TBUF_X16_HVT + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X16_HVT + + +model TBUF_X1_HVT + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X1_HVT + + +model TBUF_X2_HVT + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X2_HVT + + +model TBUF_X4_HVT + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X4_HVT + + +model TBUF_X8_HVT + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X8_HVT + + +model TINV_X1_HVT + (EN, I, ZN) +( + model_source = liberty_cell; + + input (EN) ( ) + input (I) ( ) + output (ZN) ( ) + ( + primitive = _tsl (net_0, EN, ZN); + primitive = _inv (I, net_0); + ) +) // end model TINV_X1_HVT + + +model TLAT_X1_HVT + (D, G, OE, Q) +( + model_source = liberty_cell; + + input (D) ( ) + input (G) ( active_high_clock; ) + input (OE) ( ) + output (Q) ( ) + ( + primitive = _dlat ( , , G, D, IQ, ); + primitive = _tsl (IQ, net_0, Q); + primitive = _inv (OE, net_0); + ) +) // end model TLAT_X1_HVT + + +model XNOR2_X1_HVT + (A, B, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _xor (A, B, net_0); + ) +) // end model XNOR2_X1_HVT + + +model XNOR2_X2_HVT + (A, B, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _xor (A, B, net_0); + ) +) // end model XNOR2_X2_HVT + + +model XOR2_X1_HVT + (A, B, Z) +( + model_source = liberty_cell; + cell_type = xor; + simulation_function = xor; + + input (A) ( ) + input (B) ( ) + output (Z) ( ) + ( + primitive = _xor (A, B, Z); + ) +) // end model XOR2_X1_HVT + + +model XOR2_X2_HVT + (A, B, Z) +( + model_source = liberty_cell; + cell_type = xor; + simulation_function = xor; + + input (A) ( ) + input (B) ( ) + output (Z) ( ) + ( + primitive = _xor (A, B, Z); + ) +) // end model XOR2_X2_HVT diff --git a/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib b/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib new file mode 100755 index 0000000..b7ee961 --- /dev/null +++ b/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib @@ -0,0 +1,2665 @@ +// +// *********************************************************************** +// Copyright Mentor Graphics Corporation +// All Rights Reserved +// For use only with Mentor Graphics Tessent tools +// *********************************************************************** +// File Type: Tessent Cell Library +// Generated by: Tessent Shell -- write_cell_library +// Tool Version: 2019.4 +// Tool Build Date: Wed Nov 20 21:14:16 GMT 2019 +// *********************************************************************** +// Library Created : Local Time = Tue Jun 30 00:33:34 2020 +// GMT = Tue Jun 30 07:33:34 2020 + + +library_format_version = 9; + +array_delimiter = "[]"; + + +// +// *********************************************************************** +// *********** Models holding Liberty information ****************** +// *********************************************************************** +// + + +model AND2_X1_LVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _and (A1, A2, ZN); + ) +) // end model AND2_X1_LVT + + +model AND2_X2_LVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _and (A1, A2, ZN); + ) +) // end model AND2_X2_LVT + + +model AND2_X4_LVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _and (A1, A2, ZN); + ) +) // end model AND2_X4_LVT + + +model AND3_X1_LVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A3, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model AND3_X1_LVT + + +model AND3_X2_LVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A3, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model AND3_X2_LVT + + +model AND3_X4_LVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A3, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model AND3_X4_LVT + + +model AND4_X1_LVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A4, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model AND4_X1_LVT + + +model AND4_X2_LVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A4, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model AND4_X2_LVT + + +model AND4_X4_LVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A4, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model AND4_X4_LVT + + +model ANTENNA_X1_LVT + (A) +( + model_source = liberty_cell; + cell_type = prohibited; + + input (A) ( ) + ( + // Empty Model + ) +) // end model ANTENNA_X1_LVT + + +model AOI211_X1_LVT + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A, net_0); + primitive = _or (net_2, B, net_1); + primitive = _and (C1, C2, net_2); + ) +) // end model AOI211_X1_LVT + + +model AOI211_X2_LVT + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A, net_0); + primitive = _or (net_2, B, net_1); + primitive = _and (C1, C2, net_2); + ) +) // end model AOI211_X2_LVT + + +model AOI211_X4_LVT + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _or (net_3, A, net_2); + primitive = _or (net_4, B, net_3); + primitive = _and (C1, C2, net_4); + ) +) // end model AOI211_X4_LVT + + +model AOI21_X1_LVT + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A, net_1, net_0); + primitive = _and (B1, B2, net_1); + ) +) // end model AOI21_X1_LVT + + +model AOI21_X2_LVT + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A, net_1, net_0); + primitive = _and (B1, B2, net_1); + ) +) // end model AOI21_X2_LVT + + +model AOI21_X4_LVT + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A, net_1, net_0); + primitive = _and (B1, B2, net_1); + ) +) // end model AOI21_X4_LVT + + +model AOI221_X1_LVT + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_3, net_0); + primitive = _or (net_2, A, net_1); + primitive = _and (C1, C2, net_2); + primitive = _and (B1, B2, net_3); + ) +) // end model AOI221_X1_LVT + + +model AOI221_X2_LVT + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_3, net_0); + primitive = _or (net_2, A, net_1); + primitive = _and (C1, C2, net_2); + primitive = _and (B1, B2, net_3); + ) +) // end model AOI221_X2_LVT + + +model AOI221_X4_LVT + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _or (net_3, net_5, net_2); + primitive = _or (net_4, A, net_3); + primitive = _and (C1, C2, net_4); + primitive = _and (B1, B2, net_5); + ) +) // end model AOI221_X4_LVT + + +model AOI222_X1_LVT + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_4, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (A1, A2, net_2); + primitive = _and (B1, B2, net_3); + primitive = _and (C1, C2, net_4); + ) +) // end model AOI222_X1_LVT + + +model AOI222_X2_LVT + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_4, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (A1, A2, net_2); + primitive = _and (B1, B2, net_3); + primitive = _and (C1, C2, net_4); + ) +) // end model AOI222_X2_LVT + + +model AOI222_X4_LVT + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _or (net_3, net_6, net_2); + primitive = _or (net_4, net_5, net_3); + primitive = _and (A1, A2, net_4); + primitive = _and (B1, B2, net_5); + primitive = _and (C1, C2, net_6); + ) +) // end model AOI222_X4_LVT + + +model AOI22_X1_LVT + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (A1, A2, net_1); + primitive = _and (B1, B2, net_2); + ) +) // end model AOI22_X1_LVT + + +model AOI22_X2_LVT + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (A1, A2, net_1); + primitive = _and (B1, B2, net_2); + ) +) // end model AOI22_X2_LVT + + +model AOI22_X4_LVT + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (A1, A2, net_1); + primitive = _and (B1, B2, net_2); + ) +) // end model AOI22_X4_LVT + + +model BUF_X16_LVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X16_LVT + + +model BUF_X1_LVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X1_LVT + + +model BUF_X2_LVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X2_LVT + + +model BUF_X32_LVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X32_LVT + + +model BUF_X4_LVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X4_LVT + + +model BUF_X8_LVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X8_LVT + + +model CLKBUF_X1_LVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model CLKBUF_X1_LVT + + +model CLKBUF_X2_LVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model CLKBUF_X2_LVT + + +model CLKBUF_X3_LVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model CLKBUF_X3_LVT + + +model "CLKGATETST_X1_LVT_$_IQ" + (CK, E, SE, IQ) +( + model_source = liberty_cell_statetable; + + input (CK) ( ) + input (E) ( ) + input (SE) ( ) + output (IQ) ( ) + ( + primitive = _dlat ( , , clock_net, net_0, IQ, ); + primitive = _inv (CK, clock_net); + primitive = _or (E, SE, net_0); + ) +) // end model CLKGATETST_X1_LVT_$_IQ + + +model CLKGATETST_X1_LVT + (CK, E, GCK, SE) +( + model_source = liberty_cell; + cell_type = clock_gating_and; + simulation_function = clock_gating_and; + + input (CK) ( clock_in; ) + input (E) ( func_enable; ) + input (SE) ( test_enable; ) + output (GCK) ( clock_out; ) + ( + instance = "CLKGATETST_X1_LVT_$_IQ" (CK, E, SE, IQ); + primitive = _and (IQ, CK, GCK); + ) +) // end model CLKGATETST_X1_LVT + + +model "CLKGATETST_X2_LVT_$_IQ" + (CK, E, SE, IQ) +( + model_source = liberty_cell_statetable; + + input (CK) ( ) + input (E) ( ) + input (SE) ( ) + output (IQ) ( ) + ( + primitive = _dlat ( , , clock_net, net_0, IQ, ); + primitive = _inv (CK, clock_net); + primitive = _or (E, SE, net_0); + ) +) // end model CLKGATETST_X2_LVT_$_IQ + + +model CLKGATETST_X2_LVT + (CK, E, GCK, SE) +( + model_source = liberty_cell; + cell_type = clock_gating_and; + simulation_function = clock_gating_and; + + input (CK) ( clock_in; ) + input (E) ( func_enable; ) + input (SE) ( test_enable; ) + output (GCK) ( clock_out; ) + ( + instance = "CLKGATETST_X2_LVT_$_IQ" (CK, E, SE, IQ); + primitive = _and (IQ, CK, GCK); + ) +) // end model CLKGATETST_X2_LVT + + +model "CLKGATETST_X4_LVT_$_IQ" + (CK, E, SE, IQ) +( + model_source = liberty_cell_statetable; + + input (CK) ( ) + input (E) ( ) + input (SE) ( ) + output (IQ) ( ) + ( + primitive = _dlat ( , , clock_net, net_0, IQ, ); + primitive = _inv (CK, clock_net); + primitive = _or (E, SE, net_0); + ) +) // end model CLKGATETST_X4_LVT_$_IQ + + +model CLKGATETST_X4_LVT + (CK, E, GCK, SE) +( + model_source = liberty_cell; + cell_type = clock_gating_and; + simulation_function = clock_gating_and; + + input (CK) ( clock_in; ) + input (E) ( func_enable; ) + input (SE) ( test_enable; ) + output (GCK) ( clock_out; ) + ( + instance = "CLKGATETST_X4_LVT_$_IQ" (CK, E, SE, IQ); + primitive = _and (IQ, CK, GCK); + ) +) // end model CLKGATETST_X4_LVT + + +model "CLKGATETST_X8_LVT_$_IQ" + (CK, E, SE, IQ) +( + model_source = liberty_cell_statetable; + + input (CK) ( ) + input (E) ( ) + input (SE) ( ) + output (IQ) ( ) + ( + primitive = _dlat ( , , clock_net, net_0, IQ, ); + primitive = _inv (CK, clock_net); + primitive = _or (E, SE, net_0); + ) +) // end model CLKGATETST_X8_LVT_$_IQ + + +model CLKGATETST_X8_LVT + (CK, E, GCK, SE) +( + model_source = liberty_cell; + cell_type = clock_gating_and; + simulation_function = clock_gating_and; + + input (CK) ( clock_in; ) + input (E) ( func_enable; ) + input (SE) ( test_enable; ) + output (GCK) ( clock_out; ) + ( + instance = "CLKGATETST_X8_LVT_$_IQ" (CK, E, SE, IQ); + primitive = _and (IQ, CK, GCK); + ) +) // end model CLKGATETST_X8_LVT + + +model "CLKGATE_X1_LVT_$_IQ" + (CK, E, IQ) +( + model_source = liberty_cell_statetable; + simulation_function = latch; + + input (CK) ( active_low_clock; ) + input (E) ( data_in; ) + output (IQ) ( data_out; ) + ( + primitive = _dlat ( , , clock_net, E, IQ, ); + primitive = _inv (CK, clock_net); + ) +) // end model CLKGATE_X1_LVT_$_IQ + + +model CLKGATE_X1_LVT + (CK, E, GCK) +( + model_source = liberty_cell; + + input (CK) ( active_low_clock; ) + input (E) ( ) + output (GCK) ( ) + ( + instance = "CLKGATE_X1_LVT_$_IQ" (CK, E, IQ); + primitive = _and (CK, IQ, GCK); + ) +) // end model CLKGATE_X1_LVT + + +model "CLKGATE_X2_LVT_$_IQ" + (CK, E, IQ) +( + model_source = liberty_cell_statetable; + simulation_function = latch; + + input (CK) ( active_low_clock; ) + input (E) ( data_in; ) + output (IQ) ( data_out; ) + ( + primitive = _dlat ( , , clock_net, E, IQ, ); + primitive = _inv (CK, clock_net); + ) +) // end model CLKGATE_X2_LVT_$_IQ + + +model CLKGATE_X2_LVT + (CK, E, GCK) +( + model_source = liberty_cell; + + input (CK) ( active_low_clock; ) + input (E) ( ) + output (GCK) ( ) + ( + instance = "CLKGATE_X2_LVT_$_IQ" (CK, E, IQ); + primitive = _and (CK, IQ, GCK); + ) +) // end model CLKGATE_X2_LVT + + +model "CLKGATE_X4_LVT_$_IQ" + (CK, E, IQ) +( + model_source = liberty_cell_statetable; + simulation_function = latch; + + input (CK) ( active_low_clock; ) + input (E) ( data_in; ) + output (IQ) ( data_out; ) + ( + primitive = _dlat ( , , clock_net, E, IQ, ); + primitive = _inv (CK, clock_net); + ) +) // end model CLKGATE_X4_LVT_$_IQ + + +model CLKGATE_X4_LVT + (CK, E, GCK) +( + model_source = liberty_cell; + + input (CK) ( active_low_clock; ) + input (E) ( ) + output (GCK) ( ) + ( + instance = "CLKGATE_X4_LVT_$_IQ" (CK, E, IQ); + primitive = _and (CK, IQ, GCK); + ) +) // end model CLKGATE_X4_LVT + + +model "CLKGATE_X8_LVT_$_IQ" + (CK, E, IQ) +( + model_source = liberty_cell_statetable; + simulation_function = latch; + + input (CK) ( active_low_clock; ) + input (E) ( data_in; ) + output (IQ) ( data_out; ) + ( + primitive = _dlat ( , , clock_net, E, IQ, ); + primitive = _inv (CK, clock_net); + ) +) // end model CLKGATE_X8_LVT_$_IQ + + +model CLKGATE_X8_LVT + (CK, E, GCK) +( + model_source = liberty_cell; + + input (CK) ( active_low_clock; ) + input (E) ( ) + output (GCK) ( ) + ( + instance = "CLKGATE_X8_LVT_$_IQ" (CK, E, IQ); + primitive = _and (CK, IQ, GCK); + ) +) // end model CLKGATE_X8_LVT + + +model DFFRS_X1_LVT + (CK, D, Q, QN, + RN, SN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFFRS_X1_LVT, SDFFRS_X2_LVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SN) ( active_low_set; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff (net_0, net_1, CK, D, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _inv (RN, net_1); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFRS_X1_LVT + + +model DFFRS_X2_LVT + (CK, D, Q, QN, + RN, SN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFFRS_X2_LVT, SDFFRS_X1_LVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SN) ( active_low_set; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff (net_0, net_1, CK, D, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _inv (RN, net_1); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFRS_X2_LVT + + +model DFFR_X1_LVT + (CK, D, Q, QN, + RN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFFR_X1_LVT, SDFFR_X2_LVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff ( , net_0, CK, D, IQ, IQN); + primitive = _inv (RN, net_0); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFR_X1_LVT + + +model DFFR_X2_LVT + (CK, D, Q, QN, + RN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFFR_X2_LVT, SDFFR_X1_LVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff ( , net_0, CK, D, IQ, IQN); + primitive = _inv (RN, net_0); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFR_X2_LVT + + +model DFFS_X1_LVT + (CK, D, Q, QN, + SN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFFS_X1_LVT, SDFFS_X2_LVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SN) ( active_low_set; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff (net_0, , CK, D, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFS_X1_LVT + + +model DFFS_X2_LVT + (CK, D, Q, QN, + SN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFFS_X2_LVT, SDFFS_X1_LVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SN) ( active_low_set; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff (net_0, , CK, D, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFS_X2_LVT + + +model DFF_X1_LVT + (CK, D, Q, QN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFF_X1_LVT, SDFF_X2_LVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff ( , , CK, D, IQ, IQN); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFF_X1_LVT + + +model DFF_X2_LVT + (CK, D, Q, QN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFF_X2_LVT, SDFF_X1_LVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff ( , , CK, D, IQ, IQN); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFF_X2_LVT + + +model DLH_X1_LVT + (D, G, Q) +( + model_source = liberty_cell; + cell_type = latch; + simulation_function = latch; + + input (D) ( data_in; ) + input (G) ( active_high_clock; ) + output (Q) ( data_out; ) + ( + primitive = _dlat ( , , G, D, IQ, ); + primitive = _buf (IQ, Q); + ) +) // end model DLH_X1_LVT + + +model DLH_X2_LVT + (D, G, Q) +( + model_source = liberty_cell; + cell_type = latch; + simulation_function = latch; + + input (D) ( data_in; ) + input (G) ( active_high_clock; ) + output (Q) ( data_out; ) + ( + primitive = _dlat ( , , G, D, IQ, ); + primitive = _buf (IQ, Q); + ) +) // end model DLH_X2_LVT + + +model DLL_X1_LVT + (D, GN, Q) +( + model_source = liberty_cell; + cell_type = latch; + simulation_function = latch; + + input (D) ( data_in; ) + input (GN) ( active_low_clock; ) + output (Q) ( data_out; ) + ( + primitive = _dlat ( , , net_0, D, IQ, ); + primitive = _inv (GN, net_0); + primitive = _buf (IQ, Q); + ) +) // end model DLL_X1_LVT + + +model DLL_X2_LVT + (D, GN, Q) +( + model_source = liberty_cell; + cell_type = latch; + simulation_function = latch; + + input (D) ( data_in; ) + input (GN) ( active_low_clock; ) + output (Q) ( data_out; ) + ( + primitive = _dlat ( , , net_0, D, IQ, ); + primitive = _inv (GN, net_0); + primitive = _buf (IQ, Q); + ) +) // end model DLL_X2_LVT + + +model FA_X1_LVT + (A, B, CI, CO, + S) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (CI) ( ) + output (CO) ( ) + output (S) ( ) + ( + primitive = _or (net_0, net_1, CO); + primitive = _and (A, B, net_0); + primitive = _and (CI, net_2, net_1); + primitive = _or (A, B, net_2); + primitive = _xor (CI, net_3, S); + primitive = _xor (A, B, net_3); + ) +) // end model FA_X1_LVT + + +model FILLCELL_X16_LVT + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X16_LVT + + +model FILLCELL_X1_LVT + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X1_LVT + + +model FILLCELL_X2_LVT + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X2_LVT + + +model FILLCELL_X32_LVT + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X32_LVT + + +model FILLCELL_X4_LVT + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X4_LVT + + +model FILLCELL_X8_LVT + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X8_LVT + + +model HA_X1_LVT + (A, B, CO, S) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + output (CO) ( ) + output (S) ( ) + ( + primitive = _and (A, B, CO); + primitive = _xor (A, B, S); + ) +) // end model HA_X1_LVT + + +model INV_X16_LVT + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X16_LVT + + +model INV_X1_LVT + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X1_LVT + + +model INV_X2_LVT + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X2_LVT + + +model INV_X32_LVT + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X32_LVT + + +model INV_X4_LVT + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X4_LVT + + +model INV_X8_LVT + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X8_LVT + + +model LOGIC0_X1_LVT + (Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = tie0; + + output (Z) ( ) + ( + primitive = _tie0 (Z); + ) +) // end model LOGIC0_X1_LVT + + +model LOGIC1_X1_LVT + (Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = tie1; + + output (Z) ( ) + ( + primitive = _tie1 (Z); + ) +) // end model LOGIC1_X1_LVT + + +model MUX2_X1_LVT + (A, B, S, Z) +( + model_source = liberty_cell; + cell_type = mux; + simulation_function = mux; + + input (A) ( mux_in0; ) + input (B) ( mux_in1; ) + input (S) ( mux_select; ) + output (Z) ( mux_out; ) + ( + primitive = _or (net_0, net_1, Z); + primitive = _and (S, B, net_0); + primitive = _and (A, net_2, net_1); + primitive = _inv (S, net_2); + ) +) // end model MUX2_X1_LVT + + +model MUX2_X2_LVT + (A, B, S, Z) +( + model_source = liberty_cell; + cell_type = mux; + simulation_function = mux; + + input (A) ( mux_in0; ) + input (B) ( mux_in1; ) + input (S) ( mux_select; ) + output (Z) ( mux_out; ) + ( + primitive = _or (net_0, net_1, Z); + primitive = _and (S, B, net_0); + primitive = _and (A, net_2, net_1); + primitive = _inv (S, net_2); + ) +) // end model MUX2_X2_LVT + + +model NAND2_X1_LVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model NAND2_X1_LVT + + +model NAND2_X2_LVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model NAND2_X2_LVT + + +model NAND2_X4_LVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model NAND2_X4_LVT + + +model NAND3_X1_LVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model NAND3_X1_LVT + + +model NAND3_X2_LVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model NAND3_X2_LVT + + +model NAND3_X4_LVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model NAND3_X4_LVT + + +model NAND4_X1_LVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A4, net_0); + primitive = _and (net_2, A3, net_1); + primitive = _and (A1, A2, net_2); + ) +) // end model NAND4_X1_LVT + + +model NAND4_X2_LVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A4, net_0); + primitive = _and (net_2, A3, net_1); + primitive = _and (A1, A2, net_2); + ) +) // end model NAND4_X2_LVT + + +model NAND4_X4_LVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A4, net_0); + primitive = _and (net_2, A3, net_1); + primitive = _and (A1, A2, net_2); + ) +) // end model NAND4_X4_LVT + + +model NOR2_X1_LVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model NOR2_X1_LVT + + +model NOR2_X2_LVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model NOR2_X2_LVT + + +model NOR2_X4_LVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model NOR2_X4_LVT + + +model NOR3_X1_LVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model NOR3_X1_LVT + + +model NOR3_X2_LVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model NOR3_X2_LVT + + +model NOR3_X4_LVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model NOR3_X4_LVT + + +model NOR4_X1_LVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A4, net_0); + primitive = _or (net_2, A3, net_1); + primitive = _or (A1, A2, net_2); + ) +) // end model NOR4_X1_LVT + + +model NOR4_X2_LVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A4, net_0); + primitive = _or (net_2, A3, net_1); + primitive = _or (A1, A2, net_2); + ) +) // end model NOR4_X2_LVT + + +model NOR4_X4_LVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A4, net_0); + primitive = _or (net_2, A3, net_1); + primitive = _or (A1, A2, net_2); + ) +) // end model NOR4_X4_LVT + + +model OAI211_X1_LVT + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, B, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + ) +) // end model OAI211_X1_LVT + + +model OAI211_X2_LVT + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, B, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + ) +) // end model OAI211_X2_LVT + + +model OAI211_X4_LVT + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, B, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + ) +) // end model OAI211_X4_LVT + + +model OAI21_X1_LVT + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A, net_1, net_0); + primitive = _or (B1, B2, net_1); + ) +) // end model OAI21_X1_LVT + + +model OAI21_X2_LVT + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A, net_1, net_0); + primitive = _or (B1, B2, net_1); + ) +) // end model OAI21_X2_LVT + + +model OAI21_X4_LVT + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A, net_1, net_0); + primitive = _or (B1, B2, net_1); + ) +) // end model OAI21_X4_LVT + + +model OAI221_X1_LVT + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_3, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + primitive = _or (B1, B2, net_3); + ) +) // end model OAI221_X1_LVT + + +model OAI221_X2_LVT + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_3, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + primitive = _or (B1, B2, net_3); + ) +) // end model OAI221_X2_LVT + + +model OAI221_X4_LVT + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _and (net_3, net_5, net_2); + primitive = _and (net_4, A, net_3); + primitive = _or (C1, C2, net_4); + primitive = _or (B1, B2, net_5); + ) +) // end model OAI221_X4_LVT + + +model OAI222_X1_LVT + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_4, net_0); + primitive = _and (net_2, net_3, net_1); + primitive = _or (A1, A2, net_2); + primitive = _or (B1, B2, net_3); + primitive = _or (C1, C2, net_4); + ) +) // end model OAI222_X1_LVT + + +model OAI222_X2_LVT + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_4, net_0); + primitive = _and (net_2, net_3, net_1); + primitive = _or (A1, A2, net_2); + primitive = _or (B1, B2, net_3); + primitive = _or (C1, C2, net_4); + ) +) // end model OAI222_X2_LVT + + +model OAI222_X4_LVT + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _and (net_3, net_6, net_2); + primitive = _and (net_4, net_5, net_3); + primitive = _or (A1, A2, net_4); + primitive = _or (B1, B2, net_5); + primitive = _or (C1, C2, net_6); + ) +) // end model OAI222_X4_LVT + + +model OAI22_X1_LVT + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_2, net_0); + primitive = _or (A1, A2, net_1); + primitive = _or (B1, B2, net_2); + ) +) // end model OAI22_X1_LVT + + +model OAI22_X2_LVT + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_2, net_0); + primitive = _or (A1, A2, net_1); + primitive = _or (B1, B2, net_2); + ) +) // end model OAI22_X2_LVT + + +model OAI22_X4_LVT + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_2, net_0); + primitive = _or (A1, A2, net_1); + primitive = _or (B1, B2, net_2); + ) +) // end model OAI22_X4_LVT + + +model OAI33_X1_LVT + (A1, A2, A3, B1, + B2, B3, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (B1) ( ) + input (B2) ( ) + input (B3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_3, net_0); + primitive = _or (net_2, A3, net_1); + primitive = _or (A1, A2, net_2); + primitive = _or (net_4, B3, net_3); + primitive = _or (B1, B2, net_4); + ) +) // end model OAI33_X1_LVT + + +model OR2_X1_LVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _or (A1, A2, ZN); + ) +) // end model OR2_X1_LVT + + +model OR2_X2_LVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _or (A1, A2, ZN); + ) +) // end model OR2_X2_LVT + + +model OR2_X4_LVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _or (A1, A2, ZN); + ) +) // end model OR2_X4_LVT + + +model OR3_X1_LVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A3, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model OR3_X1_LVT + + +model OR3_X2_LVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A3, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model OR3_X2_LVT + + +model OR3_X4_LVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A3, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model OR3_X4_LVT + + +model OR4_X1_LVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A4, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model OR4_X1_LVT + + +model OR4_X2_LVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A4, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model OR4_X2_LVT + + +model OR4_X4_LVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A4, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model OR4_X4_LVT + + +model SDFFRS_X1_LVT + (CK, D, Q, QN, + RN, SE, SI, SN) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFFRS_X1_LVT, DFFRS_X2_LVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + input (SN) ( active_low_set; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff (net_0, net_1, CK, net_2, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _inv (RN, net_1); + primitive = _or (net_3, net_4, net_2); + primitive = _and (SE, SI, net_3); + primitive = _and (D, net_5, net_4); + primitive = _inv (SE, net_5); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFRS_X1_LVT + + +model SDFFRS_X2_LVT + (CK, D, Q, QN, + RN, SE, SI, SN) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFFRS_X2_LVT, DFFRS_X1_LVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + input (SN) ( active_low_set; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff (net_0, net_1, CK, net_2, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _inv (RN, net_1); + primitive = _or (net_3, net_4, net_2); + primitive = _and (SE, SI, net_3); + primitive = _and (D, net_5, net_4); + primitive = _inv (SE, net_5); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFRS_X2_LVT + + +model SDFFR_X1_LVT + (CK, D, Q, QN, + RN, SE, SI) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFFR_X1_LVT, DFFR_X2_LVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff ( , net_0, CK, net_1, IQ, IQN); + primitive = _inv (RN, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (SE, SI, net_2); + primitive = _and (D, net_4, net_3); + primitive = _inv (SE, net_4); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFR_X1_LVT + + +model SDFFR_X2_LVT + (CK, D, Q, QN, + RN, SE, SI) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFFR_X2_LVT, DFFR_X1_LVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff ( , net_0, CK, net_1, IQ, IQN); + primitive = _inv (RN, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (SE, SI, net_2); + primitive = _and (D, net_4, net_3); + primitive = _inv (SE, net_4); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFR_X2_LVT + + +model SDFFS_X1_LVT + (CK, D, Q, QN, + SE, SI, SN) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFFS_X1_LVT, DFFS_X2_LVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + input (SN) ( active_low_set; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff (net_0, , CK, net_1, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (SE, SI, net_2); + primitive = _and (D, net_4, net_3); + primitive = _inv (SE, net_4); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFS_X1_LVT + + +model SDFFS_X2_LVT + (CK, D, Q, QN, + SE, SI, SN) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFFS_X2_LVT, DFFS_X1_LVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + input (SN) ( active_low_set; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff (net_0, , CK, net_1, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (SE, SI, net_2); + primitive = _and (D, net_4, net_3); + primitive = _inv (SE, net_4); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFS_X2_LVT + + +model SDFF_X1_LVT + (CK, D, Q, QN, + SE, SI) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFF_X1_LVT, DFF_X2_LVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff ( , , CK, net_0, IQ, IQN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (SE, SI, net_1); + primitive = _and (D, net_3, net_2); + primitive = _inv (SE, net_3); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFF_X1_LVT + + +model SDFF_X2_LVT + (CK, D, Q, QN, + SE, SI) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFF_X2_LVT, DFF_X1_LVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff ( , , CK, net_0, IQ, IQN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (SE, SI, net_1); + primitive = _and (D, net_3, net_2); + primitive = _inv (SE, net_3); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFF_X2_LVT + + +model TBUF_X16_LVT + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X16_LVT + + +model TBUF_X1_LVT + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X1_LVT + + +model TBUF_X2_LVT + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X2_LVT + + +model TBUF_X4_LVT + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X4_LVT + + +model TBUF_X8_LVT + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X8_LVT + + +model TINV_X1_LVT + (EN, I, ZN) +( + model_source = liberty_cell; + + input (EN) ( ) + input (I) ( ) + output (ZN) ( ) + ( + primitive = _tsl (net_0, EN, ZN); + primitive = _inv (I, net_0); + ) +) // end model TINV_X1_LVT + + +model TLAT_X1_LVT + (D, G, OE, Q) +( + model_source = liberty_cell; + + input (D) ( ) + input (G) ( active_high_clock; ) + input (OE) ( ) + output (Q) ( ) + ( + primitive = _dlat ( , , G, D, IQ, ); + primitive = _tsl (IQ, net_0, Q); + primitive = _inv (OE, net_0); + ) +) // end model TLAT_X1_LVT + + +model XNOR2_X1_LVT + (A, B, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _xor (A, B, net_0); + ) +) // end model XNOR2_X1_LVT + + +model XNOR2_X2_LVT + (A, B, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _xor (A, B, net_0); + ) +) // end model XNOR2_X2_LVT + + +model XOR2_X1_LVT + (A, B, Z) +( + model_source = liberty_cell; + cell_type = xor; + simulation_function = xor; + + input (A) ( ) + input (B) ( ) + output (Z) ( ) + ( + primitive = _xor (A, B, Z); + ) +) // end model XOR2_X1_LVT + + +model XOR2_X2_LVT + (A, B, Z) +( + model_source = liberty_cell; + cell_type = xor; + simulation_function = xor; + + input (A) ( ) + input (B) ( ) + output (Z) ( ) + ( + primitive = _xor (A, B, Z); + ) +) // end model XOR2_X2_LVT diff --git a/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib b/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib new file mode 100755 index 0000000..b7ee961 --- /dev/null +++ b/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib @@ -0,0 +1,2665 @@ +// +// *********************************************************************** +// Copyright Mentor Graphics Corporation +// All Rights Reserved +// For use only with Mentor Graphics Tessent tools +// *********************************************************************** +// File Type: Tessent Cell Library +// Generated by: Tessent Shell -- write_cell_library +// Tool Version: 2019.4 +// Tool Build Date: Wed Nov 20 21:14:16 GMT 2019 +// *********************************************************************** +// Library Created : Local Time = Tue Jun 30 00:33:34 2020 +// GMT = Tue Jun 30 07:33:34 2020 + + +library_format_version = 9; + +array_delimiter = "[]"; + + +// +// *********************************************************************** +// *********** Models holding Liberty information ****************** +// *********************************************************************** +// + + +model AND2_X1_LVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _and (A1, A2, ZN); + ) +) // end model AND2_X1_LVT + + +model AND2_X2_LVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _and (A1, A2, ZN); + ) +) // end model AND2_X2_LVT + + +model AND2_X4_LVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _and (A1, A2, ZN); + ) +) // end model AND2_X4_LVT + + +model AND3_X1_LVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A3, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model AND3_X1_LVT + + +model AND3_X2_LVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A3, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model AND3_X2_LVT + + +model AND3_X4_LVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A3, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model AND3_X4_LVT + + +model AND4_X1_LVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A4, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model AND4_X1_LVT + + +model AND4_X2_LVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A4, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model AND4_X2_LVT + + +model AND4_X4_LVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A4, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model AND4_X4_LVT + + +model ANTENNA_X1_LVT + (A) +( + model_source = liberty_cell; + cell_type = prohibited; + + input (A) ( ) + ( + // Empty Model + ) +) // end model ANTENNA_X1_LVT + + +model AOI211_X1_LVT + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A, net_0); + primitive = _or (net_2, B, net_1); + primitive = _and (C1, C2, net_2); + ) +) // end model AOI211_X1_LVT + + +model AOI211_X2_LVT + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A, net_0); + primitive = _or (net_2, B, net_1); + primitive = _and (C1, C2, net_2); + ) +) // end model AOI211_X2_LVT + + +model AOI211_X4_LVT + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _or (net_3, A, net_2); + primitive = _or (net_4, B, net_3); + primitive = _and (C1, C2, net_4); + ) +) // end model AOI211_X4_LVT + + +model AOI21_X1_LVT + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A, net_1, net_0); + primitive = _and (B1, B2, net_1); + ) +) // end model AOI21_X1_LVT + + +model AOI21_X2_LVT + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A, net_1, net_0); + primitive = _and (B1, B2, net_1); + ) +) // end model AOI21_X2_LVT + + +model AOI21_X4_LVT + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A, net_1, net_0); + primitive = _and (B1, B2, net_1); + ) +) // end model AOI21_X4_LVT + + +model AOI221_X1_LVT + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_3, net_0); + primitive = _or (net_2, A, net_1); + primitive = _and (C1, C2, net_2); + primitive = _and (B1, B2, net_3); + ) +) // end model AOI221_X1_LVT + + +model AOI221_X2_LVT + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_3, net_0); + primitive = _or (net_2, A, net_1); + primitive = _and (C1, C2, net_2); + primitive = _and (B1, B2, net_3); + ) +) // end model AOI221_X2_LVT + + +model AOI221_X4_LVT + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _or (net_3, net_5, net_2); + primitive = _or (net_4, A, net_3); + primitive = _and (C1, C2, net_4); + primitive = _and (B1, B2, net_5); + ) +) // end model AOI221_X4_LVT + + +model AOI222_X1_LVT + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_4, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (A1, A2, net_2); + primitive = _and (B1, B2, net_3); + primitive = _and (C1, C2, net_4); + ) +) // end model AOI222_X1_LVT + + +model AOI222_X2_LVT + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_4, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (A1, A2, net_2); + primitive = _and (B1, B2, net_3); + primitive = _and (C1, C2, net_4); + ) +) // end model AOI222_X2_LVT + + +model AOI222_X4_LVT + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _or (net_3, net_6, net_2); + primitive = _or (net_4, net_5, net_3); + primitive = _and (A1, A2, net_4); + primitive = _and (B1, B2, net_5); + primitive = _and (C1, C2, net_6); + ) +) // end model AOI222_X4_LVT + + +model AOI22_X1_LVT + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (A1, A2, net_1); + primitive = _and (B1, B2, net_2); + ) +) // end model AOI22_X1_LVT + + +model AOI22_X2_LVT + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (A1, A2, net_1); + primitive = _and (B1, B2, net_2); + ) +) // end model AOI22_X2_LVT + + +model AOI22_X4_LVT + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (A1, A2, net_1); + primitive = _and (B1, B2, net_2); + ) +) // end model AOI22_X4_LVT + + +model BUF_X16_LVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X16_LVT + + +model BUF_X1_LVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X1_LVT + + +model BUF_X2_LVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X2_LVT + + +model BUF_X32_LVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X32_LVT + + +model BUF_X4_LVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X4_LVT + + +model BUF_X8_LVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X8_LVT + + +model CLKBUF_X1_LVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model CLKBUF_X1_LVT + + +model CLKBUF_X2_LVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model CLKBUF_X2_LVT + + +model CLKBUF_X3_LVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model CLKBUF_X3_LVT + + +model "CLKGATETST_X1_LVT_$_IQ" + (CK, E, SE, IQ) +( + model_source = liberty_cell_statetable; + + input (CK) ( ) + input (E) ( ) + input (SE) ( ) + output (IQ) ( ) + ( + primitive = _dlat ( , , clock_net, net_0, IQ, ); + primitive = _inv (CK, clock_net); + primitive = _or (E, SE, net_0); + ) +) // end model CLKGATETST_X1_LVT_$_IQ + + +model CLKGATETST_X1_LVT + (CK, E, GCK, SE) +( + model_source = liberty_cell; + cell_type = clock_gating_and; + simulation_function = clock_gating_and; + + input (CK) ( clock_in; ) + input (E) ( func_enable; ) + input (SE) ( test_enable; ) + output (GCK) ( clock_out; ) + ( + instance = "CLKGATETST_X1_LVT_$_IQ" (CK, E, SE, IQ); + primitive = _and (IQ, CK, GCK); + ) +) // end model CLKGATETST_X1_LVT + + +model "CLKGATETST_X2_LVT_$_IQ" + (CK, E, SE, IQ) +( + model_source = liberty_cell_statetable; + + input (CK) ( ) + input (E) ( ) + input (SE) ( ) + output (IQ) ( ) + ( + primitive = _dlat ( , , clock_net, net_0, IQ, ); + primitive = _inv (CK, clock_net); + primitive = _or (E, SE, net_0); + ) +) // end model CLKGATETST_X2_LVT_$_IQ + + +model CLKGATETST_X2_LVT + (CK, E, GCK, SE) +( + model_source = liberty_cell; + cell_type = clock_gating_and; + simulation_function = clock_gating_and; + + input (CK) ( clock_in; ) + input (E) ( func_enable; ) + input (SE) ( test_enable; ) + output (GCK) ( clock_out; ) + ( + instance = "CLKGATETST_X2_LVT_$_IQ" (CK, E, SE, IQ); + primitive = _and (IQ, CK, GCK); + ) +) // end model CLKGATETST_X2_LVT + + +model "CLKGATETST_X4_LVT_$_IQ" + (CK, E, SE, IQ) +( + model_source = liberty_cell_statetable; + + input (CK) ( ) + input (E) ( ) + input (SE) ( ) + output (IQ) ( ) + ( + primitive = _dlat ( , , clock_net, net_0, IQ, ); + primitive = _inv (CK, clock_net); + primitive = _or (E, SE, net_0); + ) +) // end model CLKGATETST_X4_LVT_$_IQ + + +model CLKGATETST_X4_LVT + (CK, E, GCK, SE) +( + model_source = liberty_cell; + cell_type = clock_gating_and; + simulation_function = clock_gating_and; + + input (CK) ( clock_in; ) + input (E) ( func_enable; ) + input (SE) ( test_enable; ) + output (GCK) ( clock_out; ) + ( + instance = "CLKGATETST_X4_LVT_$_IQ" (CK, E, SE, IQ); + primitive = _and (IQ, CK, GCK); + ) +) // end model CLKGATETST_X4_LVT + + +model "CLKGATETST_X8_LVT_$_IQ" + (CK, E, SE, IQ) +( + model_source = liberty_cell_statetable; + + input (CK) ( ) + input (E) ( ) + input (SE) ( ) + output (IQ) ( ) + ( + primitive = _dlat ( , , clock_net, net_0, IQ, ); + primitive = _inv (CK, clock_net); + primitive = _or (E, SE, net_0); + ) +) // end model CLKGATETST_X8_LVT_$_IQ + + +model CLKGATETST_X8_LVT + (CK, E, GCK, SE) +( + model_source = liberty_cell; + cell_type = clock_gating_and; + simulation_function = clock_gating_and; + + input (CK) ( clock_in; ) + input (E) ( func_enable; ) + input (SE) ( test_enable; ) + output (GCK) ( clock_out; ) + ( + instance = "CLKGATETST_X8_LVT_$_IQ" (CK, E, SE, IQ); + primitive = _and (IQ, CK, GCK); + ) +) // end model CLKGATETST_X8_LVT + + +model "CLKGATE_X1_LVT_$_IQ" + (CK, E, IQ) +( + model_source = liberty_cell_statetable; + simulation_function = latch; + + input (CK) ( active_low_clock; ) + input (E) ( data_in; ) + output (IQ) ( data_out; ) + ( + primitive = _dlat ( , , clock_net, E, IQ, ); + primitive = _inv (CK, clock_net); + ) +) // end model CLKGATE_X1_LVT_$_IQ + + +model CLKGATE_X1_LVT + (CK, E, GCK) +( + model_source = liberty_cell; + + input (CK) ( active_low_clock; ) + input (E) ( ) + output (GCK) ( ) + ( + instance = "CLKGATE_X1_LVT_$_IQ" (CK, E, IQ); + primitive = _and (CK, IQ, GCK); + ) +) // end model CLKGATE_X1_LVT + + +model "CLKGATE_X2_LVT_$_IQ" + (CK, E, IQ) +( + model_source = liberty_cell_statetable; + simulation_function = latch; + + input (CK) ( active_low_clock; ) + input (E) ( data_in; ) + output (IQ) ( data_out; ) + ( + primitive = _dlat ( , , clock_net, E, IQ, ); + primitive = _inv (CK, clock_net); + ) +) // end model CLKGATE_X2_LVT_$_IQ + + +model CLKGATE_X2_LVT + (CK, E, GCK) +( + model_source = liberty_cell; + + input (CK) ( active_low_clock; ) + input (E) ( ) + output (GCK) ( ) + ( + instance = "CLKGATE_X2_LVT_$_IQ" (CK, E, IQ); + primitive = _and (CK, IQ, GCK); + ) +) // end model CLKGATE_X2_LVT + + +model "CLKGATE_X4_LVT_$_IQ" + (CK, E, IQ) +( + model_source = liberty_cell_statetable; + simulation_function = latch; + + input (CK) ( active_low_clock; ) + input (E) ( data_in; ) + output (IQ) ( data_out; ) + ( + primitive = _dlat ( , , clock_net, E, IQ, ); + primitive = _inv (CK, clock_net); + ) +) // end model CLKGATE_X4_LVT_$_IQ + + +model CLKGATE_X4_LVT + (CK, E, GCK) +( + model_source = liberty_cell; + + input (CK) ( active_low_clock; ) + input (E) ( ) + output (GCK) ( ) + ( + instance = "CLKGATE_X4_LVT_$_IQ" (CK, E, IQ); + primitive = _and (CK, IQ, GCK); + ) +) // end model CLKGATE_X4_LVT + + +model "CLKGATE_X8_LVT_$_IQ" + (CK, E, IQ) +( + model_source = liberty_cell_statetable; + simulation_function = latch; + + input (CK) ( active_low_clock; ) + input (E) ( data_in; ) + output (IQ) ( data_out; ) + ( + primitive = _dlat ( , , clock_net, E, IQ, ); + primitive = _inv (CK, clock_net); + ) +) // end model CLKGATE_X8_LVT_$_IQ + + +model CLKGATE_X8_LVT + (CK, E, GCK) +( + model_source = liberty_cell; + + input (CK) ( active_low_clock; ) + input (E) ( ) + output (GCK) ( ) + ( + instance = "CLKGATE_X8_LVT_$_IQ" (CK, E, IQ); + primitive = _and (CK, IQ, GCK); + ) +) // end model CLKGATE_X8_LVT + + +model DFFRS_X1_LVT + (CK, D, Q, QN, + RN, SN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFFRS_X1_LVT, SDFFRS_X2_LVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SN) ( active_low_set; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff (net_0, net_1, CK, D, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _inv (RN, net_1); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFRS_X1_LVT + + +model DFFRS_X2_LVT + (CK, D, Q, QN, + RN, SN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFFRS_X2_LVT, SDFFRS_X1_LVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SN) ( active_low_set; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff (net_0, net_1, CK, D, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _inv (RN, net_1); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFRS_X2_LVT + + +model DFFR_X1_LVT + (CK, D, Q, QN, + RN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFFR_X1_LVT, SDFFR_X2_LVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff ( , net_0, CK, D, IQ, IQN); + primitive = _inv (RN, net_0); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFR_X1_LVT + + +model DFFR_X2_LVT + (CK, D, Q, QN, + RN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFFR_X2_LVT, SDFFR_X1_LVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff ( , net_0, CK, D, IQ, IQN); + primitive = _inv (RN, net_0); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFR_X2_LVT + + +model DFFS_X1_LVT + (CK, D, Q, QN, + SN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFFS_X1_LVT, SDFFS_X2_LVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SN) ( active_low_set; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff (net_0, , CK, D, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFS_X1_LVT + + +model DFFS_X2_LVT + (CK, D, Q, QN, + SN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFFS_X2_LVT, SDFFS_X1_LVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SN) ( active_low_set; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff (net_0, , CK, D, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFS_X2_LVT + + +model DFF_X1_LVT + (CK, D, Q, QN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFF_X1_LVT, SDFF_X2_LVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff ( , , CK, D, IQ, IQN); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFF_X1_LVT + + +model DFF_X2_LVT + (CK, D, Q, QN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFF_X2_LVT, SDFF_X1_LVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff ( , , CK, D, IQ, IQN); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFF_X2_LVT + + +model DLH_X1_LVT + (D, G, Q) +( + model_source = liberty_cell; + cell_type = latch; + simulation_function = latch; + + input (D) ( data_in; ) + input (G) ( active_high_clock; ) + output (Q) ( data_out; ) + ( + primitive = _dlat ( , , G, D, IQ, ); + primitive = _buf (IQ, Q); + ) +) // end model DLH_X1_LVT + + +model DLH_X2_LVT + (D, G, Q) +( + model_source = liberty_cell; + cell_type = latch; + simulation_function = latch; + + input (D) ( data_in; ) + input (G) ( active_high_clock; ) + output (Q) ( data_out; ) + ( + primitive = _dlat ( , , G, D, IQ, ); + primitive = _buf (IQ, Q); + ) +) // end model DLH_X2_LVT + + +model DLL_X1_LVT + (D, GN, Q) +( + model_source = liberty_cell; + cell_type = latch; + simulation_function = latch; + + input (D) ( data_in; ) + input (GN) ( active_low_clock; ) + output (Q) ( data_out; ) + ( + primitive = _dlat ( , , net_0, D, IQ, ); + primitive = _inv (GN, net_0); + primitive = _buf (IQ, Q); + ) +) // end model DLL_X1_LVT + + +model DLL_X2_LVT + (D, GN, Q) +( + model_source = liberty_cell; + cell_type = latch; + simulation_function = latch; + + input (D) ( data_in; ) + input (GN) ( active_low_clock; ) + output (Q) ( data_out; ) + ( + primitive = _dlat ( , , net_0, D, IQ, ); + primitive = _inv (GN, net_0); + primitive = _buf (IQ, Q); + ) +) // end model DLL_X2_LVT + + +model FA_X1_LVT + (A, B, CI, CO, + S) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (CI) ( ) + output (CO) ( ) + output (S) ( ) + ( + primitive = _or (net_0, net_1, CO); + primitive = _and (A, B, net_0); + primitive = _and (CI, net_2, net_1); + primitive = _or (A, B, net_2); + primitive = _xor (CI, net_3, S); + primitive = _xor (A, B, net_3); + ) +) // end model FA_X1_LVT + + +model FILLCELL_X16_LVT + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X16_LVT + + +model FILLCELL_X1_LVT + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X1_LVT + + +model FILLCELL_X2_LVT + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X2_LVT + + +model FILLCELL_X32_LVT + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X32_LVT + + +model FILLCELL_X4_LVT + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X4_LVT + + +model FILLCELL_X8_LVT + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X8_LVT + + +model HA_X1_LVT + (A, B, CO, S) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + output (CO) ( ) + output (S) ( ) + ( + primitive = _and (A, B, CO); + primitive = _xor (A, B, S); + ) +) // end model HA_X1_LVT + + +model INV_X16_LVT + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X16_LVT + + +model INV_X1_LVT + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X1_LVT + + +model INV_X2_LVT + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X2_LVT + + +model INV_X32_LVT + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X32_LVT + + +model INV_X4_LVT + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X4_LVT + + +model INV_X8_LVT + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X8_LVT + + +model LOGIC0_X1_LVT + (Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = tie0; + + output (Z) ( ) + ( + primitive = _tie0 (Z); + ) +) // end model LOGIC0_X1_LVT + + +model LOGIC1_X1_LVT + (Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = tie1; + + output (Z) ( ) + ( + primitive = _tie1 (Z); + ) +) // end model LOGIC1_X1_LVT + + +model MUX2_X1_LVT + (A, B, S, Z) +( + model_source = liberty_cell; + cell_type = mux; + simulation_function = mux; + + input (A) ( mux_in0; ) + input (B) ( mux_in1; ) + input (S) ( mux_select; ) + output (Z) ( mux_out; ) + ( + primitive = _or (net_0, net_1, Z); + primitive = _and (S, B, net_0); + primitive = _and (A, net_2, net_1); + primitive = _inv (S, net_2); + ) +) // end model MUX2_X1_LVT + + +model MUX2_X2_LVT + (A, B, S, Z) +( + model_source = liberty_cell; + cell_type = mux; + simulation_function = mux; + + input (A) ( mux_in0; ) + input (B) ( mux_in1; ) + input (S) ( mux_select; ) + output (Z) ( mux_out; ) + ( + primitive = _or (net_0, net_1, Z); + primitive = _and (S, B, net_0); + primitive = _and (A, net_2, net_1); + primitive = _inv (S, net_2); + ) +) // end model MUX2_X2_LVT + + +model NAND2_X1_LVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model NAND2_X1_LVT + + +model NAND2_X2_LVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model NAND2_X2_LVT + + +model NAND2_X4_LVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model NAND2_X4_LVT + + +model NAND3_X1_LVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model NAND3_X1_LVT + + +model NAND3_X2_LVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model NAND3_X2_LVT + + +model NAND3_X4_LVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model NAND3_X4_LVT + + +model NAND4_X1_LVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A4, net_0); + primitive = _and (net_2, A3, net_1); + primitive = _and (A1, A2, net_2); + ) +) // end model NAND4_X1_LVT + + +model NAND4_X2_LVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A4, net_0); + primitive = _and (net_2, A3, net_1); + primitive = _and (A1, A2, net_2); + ) +) // end model NAND4_X2_LVT + + +model NAND4_X4_LVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A4, net_0); + primitive = _and (net_2, A3, net_1); + primitive = _and (A1, A2, net_2); + ) +) // end model NAND4_X4_LVT + + +model NOR2_X1_LVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model NOR2_X1_LVT + + +model NOR2_X2_LVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model NOR2_X2_LVT + + +model NOR2_X4_LVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model NOR2_X4_LVT + + +model NOR3_X1_LVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model NOR3_X1_LVT + + +model NOR3_X2_LVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model NOR3_X2_LVT + + +model NOR3_X4_LVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model NOR3_X4_LVT + + +model NOR4_X1_LVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A4, net_0); + primitive = _or (net_2, A3, net_1); + primitive = _or (A1, A2, net_2); + ) +) // end model NOR4_X1_LVT + + +model NOR4_X2_LVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A4, net_0); + primitive = _or (net_2, A3, net_1); + primitive = _or (A1, A2, net_2); + ) +) // end model NOR4_X2_LVT + + +model NOR4_X4_LVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A4, net_0); + primitive = _or (net_2, A3, net_1); + primitive = _or (A1, A2, net_2); + ) +) // end model NOR4_X4_LVT + + +model OAI211_X1_LVT + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, B, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + ) +) // end model OAI211_X1_LVT + + +model OAI211_X2_LVT + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, B, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + ) +) // end model OAI211_X2_LVT + + +model OAI211_X4_LVT + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, B, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + ) +) // end model OAI211_X4_LVT + + +model OAI21_X1_LVT + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A, net_1, net_0); + primitive = _or (B1, B2, net_1); + ) +) // end model OAI21_X1_LVT + + +model OAI21_X2_LVT + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A, net_1, net_0); + primitive = _or (B1, B2, net_1); + ) +) // end model OAI21_X2_LVT + + +model OAI21_X4_LVT + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A, net_1, net_0); + primitive = _or (B1, B2, net_1); + ) +) // end model OAI21_X4_LVT + + +model OAI221_X1_LVT + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_3, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + primitive = _or (B1, B2, net_3); + ) +) // end model OAI221_X1_LVT + + +model OAI221_X2_LVT + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_3, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + primitive = _or (B1, B2, net_3); + ) +) // end model OAI221_X2_LVT + + +model OAI221_X4_LVT + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _and (net_3, net_5, net_2); + primitive = _and (net_4, A, net_3); + primitive = _or (C1, C2, net_4); + primitive = _or (B1, B2, net_5); + ) +) // end model OAI221_X4_LVT + + +model OAI222_X1_LVT + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_4, net_0); + primitive = _and (net_2, net_3, net_1); + primitive = _or (A1, A2, net_2); + primitive = _or (B1, B2, net_3); + primitive = _or (C1, C2, net_4); + ) +) // end model OAI222_X1_LVT + + +model OAI222_X2_LVT + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_4, net_0); + primitive = _and (net_2, net_3, net_1); + primitive = _or (A1, A2, net_2); + primitive = _or (B1, B2, net_3); + primitive = _or (C1, C2, net_4); + ) +) // end model OAI222_X2_LVT + + +model OAI222_X4_LVT + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _and (net_3, net_6, net_2); + primitive = _and (net_4, net_5, net_3); + primitive = _or (A1, A2, net_4); + primitive = _or (B1, B2, net_5); + primitive = _or (C1, C2, net_6); + ) +) // end model OAI222_X4_LVT + + +model OAI22_X1_LVT + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_2, net_0); + primitive = _or (A1, A2, net_1); + primitive = _or (B1, B2, net_2); + ) +) // end model OAI22_X1_LVT + + +model OAI22_X2_LVT + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_2, net_0); + primitive = _or (A1, A2, net_1); + primitive = _or (B1, B2, net_2); + ) +) // end model OAI22_X2_LVT + + +model OAI22_X4_LVT + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_2, net_0); + primitive = _or (A1, A2, net_1); + primitive = _or (B1, B2, net_2); + ) +) // end model OAI22_X4_LVT + + +model OAI33_X1_LVT + (A1, A2, A3, B1, + B2, B3, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (B1) ( ) + input (B2) ( ) + input (B3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_3, net_0); + primitive = _or (net_2, A3, net_1); + primitive = _or (A1, A2, net_2); + primitive = _or (net_4, B3, net_3); + primitive = _or (B1, B2, net_4); + ) +) // end model OAI33_X1_LVT + + +model OR2_X1_LVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _or (A1, A2, ZN); + ) +) // end model OR2_X1_LVT + + +model OR2_X2_LVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _or (A1, A2, ZN); + ) +) // end model OR2_X2_LVT + + +model OR2_X4_LVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _or (A1, A2, ZN); + ) +) // end model OR2_X4_LVT + + +model OR3_X1_LVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A3, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model OR3_X1_LVT + + +model OR3_X2_LVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A3, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model OR3_X2_LVT + + +model OR3_X4_LVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A3, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model OR3_X4_LVT + + +model OR4_X1_LVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A4, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model OR4_X1_LVT + + +model OR4_X2_LVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A4, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model OR4_X2_LVT + + +model OR4_X4_LVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A4, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model OR4_X4_LVT + + +model SDFFRS_X1_LVT + (CK, D, Q, QN, + RN, SE, SI, SN) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFFRS_X1_LVT, DFFRS_X2_LVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + input (SN) ( active_low_set; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff (net_0, net_1, CK, net_2, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _inv (RN, net_1); + primitive = _or (net_3, net_4, net_2); + primitive = _and (SE, SI, net_3); + primitive = _and (D, net_5, net_4); + primitive = _inv (SE, net_5); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFRS_X1_LVT + + +model SDFFRS_X2_LVT + (CK, D, Q, QN, + RN, SE, SI, SN) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFFRS_X2_LVT, DFFRS_X1_LVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + input (SN) ( active_low_set; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff (net_0, net_1, CK, net_2, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _inv (RN, net_1); + primitive = _or (net_3, net_4, net_2); + primitive = _and (SE, SI, net_3); + primitive = _and (D, net_5, net_4); + primitive = _inv (SE, net_5); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFRS_X2_LVT + + +model SDFFR_X1_LVT + (CK, D, Q, QN, + RN, SE, SI) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFFR_X1_LVT, DFFR_X2_LVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff ( , net_0, CK, net_1, IQ, IQN); + primitive = _inv (RN, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (SE, SI, net_2); + primitive = _and (D, net_4, net_3); + primitive = _inv (SE, net_4); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFR_X1_LVT + + +model SDFFR_X2_LVT + (CK, D, Q, QN, + RN, SE, SI) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFFR_X2_LVT, DFFR_X1_LVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff ( , net_0, CK, net_1, IQ, IQN); + primitive = _inv (RN, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (SE, SI, net_2); + primitive = _and (D, net_4, net_3); + primitive = _inv (SE, net_4); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFR_X2_LVT + + +model SDFFS_X1_LVT + (CK, D, Q, QN, + SE, SI, SN) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFFS_X1_LVT, DFFS_X2_LVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + input (SN) ( active_low_set; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff (net_0, , CK, net_1, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (SE, SI, net_2); + primitive = _and (D, net_4, net_3); + primitive = _inv (SE, net_4); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFS_X1_LVT + + +model SDFFS_X2_LVT + (CK, D, Q, QN, + SE, SI, SN) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFFS_X2_LVT, DFFS_X1_LVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + input (SN) ( active_low_set; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff (net_0, , CK, net_1, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (SE, SI, net_2); + primitive = _and (D, net_4, net_3); + primitive = _inv (SE, net_4); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFS_X2_LVT + + +model SDFF_X1_LVT + (CK, D, Q, QN, + SE, SI) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFF_X1_LVT, DFF_X2_LVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff ( , , CK, net_0, IQ, IQN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (SE, SI, net_1); + primitive = _and (D, net_3, net_2); + primitive = _inv (SE, net_3); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFF_X1_LVT + + +model SDFF_X2_LVT + (CK, D, Q, QN, + SE, SI) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFF_X2_LVT, DFF_X1_LVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff ( , , CK, net_0, IQ, IQN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (SE, SI, net_1); + primitive = _and (D, net_3, net_2); + primitive = _inv (SE, net_3); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFF_X2_LVT + + +model TBUF_X16_LVT + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X16_LVT + + +model TBUF_X1_LVT + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X1_LVT + + +model TBUF_X2_LVT + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X2_LVT + + +model TBUF_X4_LVT + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X4_LVT + + +model TBUF_X8_LVT + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X8_LVT + + +model TINV_X1_LVT + (EN, I, ZN) +( + model_source = liberty_cell; + + input (EN) ( ) + input (I) ( ) + output (ZN) ( ) + ( + primitive = _tsl (net_0, EN, ZN); + primitive = _inv (I, net_0); + ) +) // end model TINV_X1_LVT + + +model TLAT_X1_LVT + (D, G, OE, Q) +( + model_source = liberty_cell; + + input (D) ( ) + input (G) ( active_high_clock; ) + input (OE) ( ) + output (Q) ( ) + ( + primitive = _dlat ( , , G, D, IQ, ); + primitive = _tsl (IQ, net_0, Q); + primitive = _inv (OE, net_0); + ) +) // end model TLAT_X1_LVT + + +model XNOR2_X1_LVT + (A, B, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _xor (A, B, net_0); + ) +) // end model XNOR2_X1_LVT + + +model XNOR2_X2_LVT + (A, B, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _xor (A, B, net_0); + ) +) // end model XNOR2_X2_LVT + + +model XOR2_X1_LVT + (A, B, Z) +( + model_source = liberty_cell; + cell_type = xor; + simulation_function = xor; + + input (A) ( ) + input (B) ( ) + output (Z) ( ) + ( + primitive = _xor (A, B, Z); + ) +) // end model XOR2_X1_LVT + + +model XOR2_X2_LVT + (A, B, Z) +( + model_source = liberty_cell; + cell_type = xor; + simulation_function = xor; + + input (A) ( ) + input (B) ( ) + output (Z) ( ) + ( + primitive = _xor (A, B, Z); + ) +) // end model XOR2_X2_LVT diff --git a/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib b/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib new file mode 100755 index 0000000..414a170 --- /dev/null +++ b/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib @@ -0,0 +1,2665 @@ +// +// *********************************************************************** +// Copyright Mentor Graphics Corporation +// All Rights Reserved +// For use only with Mentor Graphics Tessent tools +// *********************************************************************** +// File Type: Tessent Cell Library +// Generated by: Tessent Shell -- write_cell_library +// Tool Version: 2019.4 +// Tool Build Date: Wed Nov 20 21:14:16 GMT 2019 +// *********************************************************************** +// Library Created : Local Time = Tue Jun 30 00:33:28 2020 +// GMT = Tue Jun 30 07:33:28 2020 + + +library_format_version = 9; + +array_delimiter = "[]"; + + +// +// *********************************************************************** +// *********** Models holding Liberty information ****************** +// *********************************************************************** +// + + +model AND2_X1_SVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _and (A1, A2, ZN); + ) +) // end model AND2_X1_SVT + + +model AND2_X2_SVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _and (A1, A2, ZN); + ) +) // end model AND2_X2_SVT + + +model AND2_X4_SVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _and (A1, A2, ZN); + ) +) // end model AND2_X4_SVT + + +model AND3_X1_SVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A3, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model AND3_X1_SVT + + +model AND3_X2_SVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A3, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model AND3_X2_SVT + + +model AND3_X4_SVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A3, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model AND3_X4_SVT + + +model AND4_X1_SVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A4, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model AND4_X1_SVT + + +model AND4_X2_SVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A4, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model AND4_X2_SVT + + +model AND4_X4_SVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A4, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model AND4_X4_SVT + + +model ANTENNA_X1_SVT + (A) +( + model_source = liberty_cell; + cell_type = prohibited; + + input (A) ( ) + ( + // Empty Model + ) +) // end model ANTENNA_X1_SVT + + +model AOI211_X1_SVT + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A, net_0); + primitive = _or (net_2, B, net_1); + primitive = _and (C1, C2, net_2); + ) +) // end model AOI211_X1_SVT + + +model AOI211_X2_SVT + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A, net_0); + primitive = _or (net_2, B, net_1); + primitive = _and (C1, C2, net_2); + ) +) // end model AOI211_X2_SVT + + +model AOI211_X4_SVT + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _or (net_3, A, net_2); + primitive = _or (net_4, B, net_3); + primitive = _and (C1, C2, net_4); + ) +) // end model AOI211_X4_SVT + + +model AOI21_X1_SVT + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A, net_1, net_0); + primitive = _and (B1, B2, net_1); + ) +) // end model AOI21_X1_SVT + + +model AOI21_X2_SVT + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A, net_1, net_0); + primitive = _and (B1, B2, net_1); + ) +) // end model AOI21_X2_SVT + + +model AOI21_X4_SVT + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A, net_1, net_0); + primitive = _and (B1, B2, net_1); + ) +) // end model AOI21_X4_SVT + + +model AOI221_X1_SVT + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_3, net_0); + primitive = _or (net_2, A, net_1); + primitive = _and (C1, C2, net_2); + primitive = _and (B1, B2, net_3); + ) +) // end model AOI221_X1_SVT + + +model AOI221_X2_SVT + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_3, net_0); + primitive = _or (net_2, A, net_1); + primitive = _and (C1, C2, net_2); + primitive = _and (B1, B2, net_3); + ) +) // end model AOI221_X2_SVT + + +model AOI221_X4_SVT + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _or (net_3, net_5, net_2); + primitive = _or (net_4, A, net_3); + primitive = _and (C1, C2, net_4); + primitive = _and (B1, B2, net_5); + ) +) // end model AOI221_X4_SVT + + +model AOI222_X1_SVT + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_4, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (A1, A2, net_2); + primitive = _and (B1, B2, net_3); + primitive = _and (C1, C2, net_4); + ) +) // end model AOI222_X1_SVT + + +model AOI222_X2_SVT + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_4, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (A1, A2, net_2); + primitive = _and (B1, B2, net_3); + primitive = _and (C1, C2, net_4); + ) +) // end model AOI222_X2_SVT + + +model AOI222_X4_SVT + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _or (net_3, net_6, net_2); + primitive = _or (net_4, net_5, net_3); + primitive = _and (A1, A2, net_4); + primitive = _and (B1, B2, net_5); + primitive = _and (C1, C2, net_6); + ) +) // end model AOI222_X4_SVT + + +model AOI22_X1_SVT + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (A1, A2, net_1); + primitive = _and (B1, B2, net_2); + ) +) // end model AOI22_X1_SVT + + +model AOI22_X2_SVT + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (A1, A2, net_1); + primitive = _and (B1, B2, net_2); + ) +) // end model AOI22_X2_SVT + + +model AOI22_X4_SVT + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (A1, A2, net_1); + primitive = _and (B1, B2, net_2); + ) +) // end model AOI22_X4_SVT + + +model BUF_X16_SVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X16_SVT + + +model BUF_X1_SVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X1_SVT + + +model BUF_X2_SVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X2_SVT + + +model BUF_X32_SVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X32_SVT + + +model BUF_X4_SVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X4_SVT + + +model BUF_X8_SVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X8_SVT + + +model CLKBUF_X1_SVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model CLKBUF_X1_SVT + + +model CLKBUF_X2_SVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model CLKBUF_X2_SVT + + +model CLKBUF_X3_SVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model CLKBUF_X3_SVT + + +model "CLKGATETST_X1_SVT_$_IQ" + (CK, E, SE, IQ) +( + model_source = liberty_cell_statetable; + + input (CK) ( ) + input (E) ( ) + input (SE) ( ) + output (IQ) ( ) + ( + primitive = _dlat ( , , clock_net, net_0, IQ, ); + primitive = _inv (CK, clock_net); + primitive = _or (E, SE, net_0); + ) +) // end model CLKGATETST_X1_SVT_$_IQ + + +model CLKGATETST_X1_SVT + (CK, E, GCK, SE) +( + model_source = liberty_cell; + cell_type = clock_gating_and; + simulation_function = clock_gating_and; + + input (CK) ( clock_in; ) + input (E) ( func_enable; ) + input (SE) ( test_enable; ) + output (GCK) ( clock_out; ) + ( + instance = "CLKGATETST_X1_SVT_$_IQ" (CK, E, SE, IQ); + primitive = _and (IQ, CK, GCK); + ) +) // end model CLKGATETST_X1_SVT + + +model "CLKGATETST_X2_SVT_$_IQ" + (CK, E, SE, IQ) +( + model_source = liberty_cell_statetable; + + input (CK) ( ) + input (E) ( ) + input (SE) ( ) + output (IQ) ( ) + ( + primitive = _dlat ( , , clock_net, net_0, IQ, ); + primitive = _inv (CK, clock_net); + primitive = _or (E, SE, net_0); + ) +) // end model CLKGATETST_X2_SVT_$_IQ + + +model CLKGATETST_X2_SVT + (CK, E, GCK, SE) +( + model_source = liberty_cell; + cell_type = clock_gating_and; + simulation_function = clock_gating_and; + + input (CK) ( clock_in; ) + input (E) ( func_enable; ) + input (SE) ( test_enable; ) + output (GCK) ( clock_out; ) + ( + instance = "CLKGATETST_X2_SVT_$_IQ" (CK, E, SE, IQ); + primitive = _and (IQ, CK, GCK); + ) +) // end model CLKGATETST_X2_SVT + + +model "CLKGATETST_X4_SVT_$_IQ" + (CK, E, SE, IQ) +( + model_source = liberty_cell_statetable; + + input (CK) ( ) + input (E) ( ) + input (SE) ( ) + output (IQ) ( ) + ( + primitive = _dlat ( , , clock_net, net_0, IQ, ); + primitive = _inv (CK, clock_net); + primitive = _or (E, SE, net_0); + ) +) // end model CLKGATETST_X4_SVT_$_IQ + + +model CLKGATETST_X4_SVT + (CK, E, GCK, SE) +( + model_source = liberty_cell; + cell_type = clock_gating_and; + simulation_function = clock_gating_and; + + input (CK) ( clock_in; ) + input (E) ( func_enable; ) + input (SE) ( test_enable; ) + output (GCK) ( clock_out; ) + ( + instance = "CLKGATETST_X4_SVT_$_IQ" (CK, E, SE, IQ); + primitive = _and (IQ, CK, GCK); + ) +) // end model CLKGATETST_X4_SVT + + +model "CLKGATETST_X8_SVT_$_IQ" + (CK, E, SE, IQ) +( + model_source = liberty_cell_statetable; + + input (CK) ( ) + input (E) ( ) + input (SE) ( ) + output (IQ) ( ) + ( + primitive = _dlat ( , , clock_net, net_0, IQ, ); + primitive = _inv (CK, clock_net); + primitive = _or (E, SE, net_0); + ) +) // end model CLKGATETST_X8_SVT_$_IQ + + +model CLKGATETST_X8_SVT + (CK, E, GCK, SE) +( + model_source = liberty_cell; + cell_type = clock_gating_and; + simulation_function = clock_gating_and; + + input (CK) ( clock_in; ) + input (E) ( func_enable; ) + input (SE) ( test_enable; ) + output (GCK) ( clock_out; ) + ( + instance = "CLKGATETST_X8_SVT_$_IQ" (CK, E, SE, IQ); + primitive = _and (IQ, CK, GCK); + ) +) // end model CLKGATETST_X8_SVT + + +model "CLKGATE_X1_SVT_$_IQ" + (CK, E, IQ) +( + model_source = liberty_cell_statetable; + simulation_function = latch; + + input (CK) ( active_low_clock; ) + input (E) ( data_in; ) + output (IQ) ( data_out; ) + ( + primitive = _dlat ( , , clock_net, E, IQ, ); + primitive = _inv (CK, clock_net); + ) +) // end model CLKGATE_X1_SVT_$_IQ + + +model CLKGATE_X1_SVT + (CK, E, GCK) +( + model_source = liberty_cell; + + input (CK) ( active_low_clock; ) + input (E) ( ) + output (GCK) ( ) + ( + instance = "CLKGATE_X1_SVT_$_IQ" (CK, E, IQ); + primitive = _and (CK, IQ, GCK); + ) +) // end model CLKGATE_X1_SVT + + +model "CLKGATE_X2_SVT_$_IQ" + (CK, E, IQ) +( + model_source = liberty_cell_statetable; + simulation_function = latch; + + input (CK) ( active_low_clock; ) + input (E) ( data_in; ) + output (IQ) ( data_out; ) + ( + primitive = _dlat ( , , clock_net, E, IQ, ); + primitive = _inv (CK, clock_net); + ) +) // end model CLKGATE_X2_SVT_$_IQ + + +model CLKGATE_X2_SVT + (CK, E, GCK) +( + model_source = liberty_cell; + + input (CK) ( active_low_clock; ) + input (E) ( ) + output (GCK) ( ) + ( + instance = "CLKGATE_X2_SVT_$_IQ" (CK, E, IQ); + primitive = _and (CK, IQ, GCK); + ) +) // end model CLKGATE_X2_SVT + + +model "CLKGATE_X4_SVT_$_IQ" + (CK, E, IQ) +( + model_source = liberty_cell_statetable; + simulation_function = latch; + + input (CK) ( active_low_clock; ) + input (E) ( data_in; ) + output (IQ) ( data_out; ) + ( + primitive = _dlat ( , , clock_net, E, IQ, ); + primitive = _inv (CK, clock_net); + ) +) // end model CLKGATE_X4_SVT_$_IQ + + +model CLKGATE_X4_SVT + (CK, E, GCK) +( + model_source = liberty_cell; + + input (CK) ( active_low_clock; ) + input (E) ( ) + output (GCK) ( ) + ( + instance = "CLKGATE_X4_SVT_$_IQ" (CK, E, IQ); + primitive = _and (CK, IQ, GCK); + ) +) // end model CLKGATE_X4_SVT + + +model "CLKGATE_X8_SVT_$_IQ" + (CK, E, IQ) +( + model_source = liberty_cell_statetable; + simulation_function = latch; + + input (CK) ( active_low_clock; ) + input (E) ( data_in; ) + output (IQ) ( data_out; ) + ( + primitive = _dlat ( , , clock_net, E, IQ, ); + primitive = _inv (CK, clock_net); + ) +) // end model CLKGATE_X8_SVT_$_IQ + + +model CLKGATE_X8_SVT + (CK, E, GCK) +( + model_source = liberty_cell; + + input (CK) ( active_low_clock; ) + input (E) ( ) + output (GCK) ( ) + ( + instance = "CLKGATE_X8_SVT_$_IQ" (CK, E, IQ); + primitive = _and (CK, IQ, GCK); + ) +) // end model CLKGATE_X8_SVT + + +model DFFRS_X1_SVT + (CK, D, Q, QN, + RN, SN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFFRS_X1_SVT, SDFFRS_X2_SVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SN) ( active_low_set; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff (net_0, net_1, CK, D, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _inv (RN, net_1); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFRS_X1_SVT + + +model DFFRS_X2_SVT + (CK, D, Q, QN, + RN, SN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFFRS_X2_SVT, SDFFRS_X1_SVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SN) ( active_low_set; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff (net_0, net_1, CK, D, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _inv (RN, net_1); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFRS_X2_SVT + + +model DFFR_X1_SVT + (CK, D, Q, QN, + RN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFFR_X1_SVT, SDFFR_X2_SVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff ( , net_0, CK, D, IQ, IQN); + primitive = _inv (RN, net_0); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFR_X1_SVT + + +model DFFR_X2_SVT + (CK, D, Q, QN, + RN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFFR_X2_SVT, SDFFR_X1_SVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff ( , net_0, CK, D, IQ, IQN); + primitive = _inv (RN, net_0); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFR_X2_SVT + + +model DFFS_X1_SVT + (CK, D, Q, QN, + SN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFFS_X2_SVT, SDFFS_X1_SVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SN) ( active_low_set; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff (net_0, , CK, D, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFS_X1_SVT + + +model DFFS_X2_SVT + (CK, D, Q, QN, + SN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFFS_X2_SVT, SDFFS_X1_SVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SN) ( active_low_set; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff (net_0, , CK, D, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFS_X2_SVT + + +model DFF_X1_SVT + (CK, D, Q, QN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFF_X1_SVT, SDFF_X2_SVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff ( , , CK, D, IQ, IQN); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFF_X1_SVT + + +model DFF_X2_SVT + (CK, D, Q, QN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFF_X2_SVT, SDFF_X1_SVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff ( , , CK, D, IQ, IQN); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFF_X2_SVT + + +model DLH_X1_SVT + (D, G, Q) +( + model_source = liberty_cell; + cell_type = latch; + simulation_function = latch; + + input (D) ( data_in; ) + input (G) ( active_high_clock; ) + output (Q) ( data_out; ) + ( + primitive = _dlat ( , , G, D, IQ, ); + primitive = _buf (IQ, Q); + ) +) // end model DLH_X1_SVT + + +model DLH_X2_SVT + (D, G, Q) +( + model_source = liberty_cell; + cell_type = latch; + simulation_function = latch; + + input (D) ( data_in; ) + input (G) ( active_high_clock; ) + output (Q) ( data_out; ) + ( + primitive = _dlat ( , , G, D, IQ, ); + primitive = _buf (IQ, Q); + ) +) // end model DLH_X2_SVT + + +model DLL_X1_SVT + (D, GN, Q) +( + model_source = liberty_cell; + cell_type = latch; + simulation_function = latch; + + input (D) ( data_in; ) + input (GN) ( active_low_clock; ) + output (Q) ( data_out; ) + ( + primitive = _dlat ( , , net_0, D, IQ, ); + primitive = _inv (GN, net_0); + primitive = _buf (IQ, Q); + ) +) // end model DLL_X1_SVT + + +model DLL_X2_SVT + (D, GN, Q) +( + model_source = liberty_cell; + cell_type = latch; + simulation_function = latch; + + input (D) ( data_in; ) + input (GN) ( active_low_clock; ) + output (Q) ( data_out; ) + ( + primitive = _dlat ( , , net_0, D, IQ, ); + primitive = _inv (GN, net_0); + primitive = _buf (IQ, Q); + ) +) // end model DLL_X2_SVT + + +model FA_X1_SVT + (A, B, CI, CO, + S) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (CI) ( ) + output (CO) ( ) + output (S) ( ) + ( + primitive = _or (net_0, net_1, CO); + primitive = _and (A, B, net_0); + primitive = _and (CI, net_2, net_1); + primitive = _or (A, B, net_2); + primitive = _xor (CI, net_3, S); + primitive = _xor (A, B, net_3); + ) +) // end model FA_X1_SVT + + +model FILLCELL_X16_SVT + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X16_SVT + + +model FILLCELL_X1_SVT + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X1_SVT + + +model FILLCELL_X2_SVT + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X2_SVT + + +model FILLCELL_X32_SVT + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X32_SVT + + +model FILLCELL_X4_SVT + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X4_SVT + + +model FILLCELL_X8_SVT + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X8_SVT + + +model HA_X1_SVT + (A, B, CO, S) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + output (CO) ( ) + output (S) ( ) + ( + primitive = _and (A, B, CO); + primitive = _xor (A, B, S); + ) +) // end model HA_X1_SVT + + +model INV_X16_SVT + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X16_SVT + + +model INV_X1_SVT + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X1_SVT + + +model INV_X2_SVT + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X2_SVT + + +model INV_X32_SVT + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X32_SVT + + +model INV_X4_SVT + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X4_SVT + + +model INV_X8_SVT + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X8_SVT + + +model LOGIC0_X1_SVT + (Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = tie0; + + output (Z) ( ) + ( + primitive = _tie0 (Z); + ) +) // end model LOGIC0_X1_SVT + + +model LOGIC1_X1_SVT + (Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = tie1; + + output (Z) ( ) + ( + primitive = _tie1 (Z); + ) +) // end model LOGIC1_X1_SVT + + +model MUX2_X1_SVT + (A, B, S, Z) +( + model_source = liberty_cell; + cell_type = mux; + simulation_function = mux; + + input (A) ( mux_in0; ) + input (B) ( mux_in1; ) + input (S) ( mux_select; ) + output (Z) ( mux_out; ) + ( + primitive = _or (net_0, net_1, Z); + primitive = _and (S, B, net_0); + primitive = _and (A, net_2, net_1); + primitive = _inv (S, net_2); + ) +) // end model MUX2_X1_SVT + + +model MUX2_X2_SVT + (A, B, S, Z) +( + model_source = liberty_cell; + cell_type = mux; + simulation_function = mux; + + input (A) ( mux_in0; ) + input (B) ( mux_in1; ) + input (S) ( mux_select; ) + output (Z) ( mux_out; ) + ( + primitive = _or (net_0, net_1, Z); + primitive = _and (S, B, net_0); + primitive = _and (A, net_2, net_1); + primitive = _inv (S, net_2); + ) +) // end model MUX2_X2_SVT + + +model NAND2_X1_SVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model NAND2_X1_SVT + + +model NAND2_X2_SVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model NAND2_X2_SVT + + +model NAND2_X4_SVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model NAND2_X4_SVT + + +model NAND3_X1_SVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model NAND3_X1_SVT + + +model NAND3_X2_SVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model NAND3_X2_SVT + + +model NAND3_X4_SVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model NAND3_X4_SVT + + +model NAND4_X1_SVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A4, net_0); + primitive = _and (net_2, A3, net_1); + primitive = _and (A1, A2, net_2); + ) +) // end model NAND4_X1_SVT + + +model NAND4_X2_SVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A4, net_0); + primitive = _and (net_2, A3, net_1); + primitive = _and (A1, A2, net_2); + ) +) // end model NAND4_X2_SVT + + +model NAND4_X4_SVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A4, net_0); + primitive = _and (net_2, A3, net_1); + primitive = _and (A1, A2, net_2); + ) +) // end model NAND4_X4_SVT + + +model NOR2_X1_SVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model NOR2_X1_SVT + + +model NOR2_X2_SVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model NOR2_X2_SVT + + +model NOR2_X4_SVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model NOR2_X4_SVT + + +model NOR3_X1_SVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model NOR3_X1_SVT + + +model NOR3_X2_SVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model NOR3_X2_SVT + + +model NOR3_X4_SVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model NOR3_X4_SVT + + +model NOR4_X1_SVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A4, net_0); + primitive = _or (net_2, A3, net_1); + primitive = _or (A1, A2, net_2); + ) +) // end model NOR4_X1_SVT + + +model NOR4_X2_SVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A4, net_0); + primitive = _or (net_2, A3, net_1); + primitive = _or (A1, A2, net_2); + ) +) // end model NOR4_X2_SVT + + +model NOR4_X4_SVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A4, net_0); + primitive = _or (net_2, A3, net_1); + primitive = _or (A1, A2, net_2); + ) +) // end model NOR4_X4_SVT + + +model OAI211_X1_SVT + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, B, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + ) +) // end model OAI211_X1_SVT + + +model OAI211_X2_SVT + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, B, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + ) +) // end model OAI211_X2_SVT + + +model OAI211_X4_SVT + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, B, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + ) +) // end model OAI211_X4_SVT + + +model OAI21_X1_SVT + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A, net_1, net_0); + primitive = _or (B1, B2, net_1); + ) +) // end model OAI21_X1_SVT + + +model OAI21_X2_SVT + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A, net_1, net_0); + primitive = _or (B1, B2, net_1); + ) +) // end model OAI21_X2_SVT + + +model OAI21_X4_SVT + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A, net_1, net_0); + primitive = _or (B1, B2, net_1); + ) +) // end model OAI21_X4_SVT + + +model OAI221_X1_SVT + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_3, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + primitive = _or (B1, B2, net_3); + ) +) // end model OAI221_X1_SVT + + +model OAI221_X2_SVT + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_3, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + primitive = _or (B1, B2, net_3); + ) +) // end model OAI221_X2_SVT + + +model OAI221_X4_SVT + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _and (net_3, net_5, net_2); + primitive = _and (net_4, A, net_3); + primitive = _or (C1, C2, net_4); + primitive = _or (B1, B2, net_5); + ) +) // end model OAI221_X4_SVT + + +model OAI222_X1_SVT + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_4, net_0); + primitive = _and (net_2, net_3, net_1); + primitive = _or (A1, A2, net_2); + primitive = _or (B1, B2, net_3); + primitive = _or (C1, C2, net_4); + ) +) // end model OAI222_X1_SVT + + +model OAI222_X2_SVT + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_4, net_0); + primitive = _and (net_2, net_3, net_1); + primitive = _or (A1, A2, net_2); + primitive = _or (B1, B2, net_3); + primitive = _or (C1, C2, net_4); + ) +) // end model OAI222_X2_SVT + + +model OAI222_X4_SVT + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _and (net_3, net_6, net_2); + primitive = _and (net_4, net_5, net_3); + primitive = _or (A1, A2, net_4); + primitive = _or (B1, B2, net_5); + primitive = _or (C1, C2, net_6); + ) +) // end model OAI222_X4_SVT + + +model OAI22_X1_SVT + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_2, net_0); + primitive = _or (A1, A2, net_1); + primitive = _or (B1, B2, net_2); + ) +) // end model OAI22_X1_SVT + + +model OAI22_X2_SVT + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_2, net_0); + primitive = _or (A1, A2, net_1); + primitive = _or (B1, B2, net_2); + ) +) // end model OAI22_X2_SVT + + +model OAI22_X4_SVT + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_2, net_0); + primitive = _or (A1, A2, net_1); + primitive = _or (B1, B2, net_2); + ) +) // end model OAI22_X4_SVT + + +model OAI33_X1_SVT + (A1, A2, A3, B1, + B2, B3, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (B1) ( ) + input (B2) ( ) + input (B3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_3, net_0); + primitive = _or (net_2, A3, net_1); + primitive = _or (A1, A2, net_2); + primitive = _or (net_4, B3, net_3); + primitive = _or (B1, B2, net_4); + ) +) // end model OAI33_X1_SVT + + +model OR2_X1_SVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _or (A1, A2, ZN); + ) +) // end model OR2_X1_SVT + + +model OR2_X2_SVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _or (A1, A2, ZN); + ) +) // end model OR2_X2_SVT + + +model OR2_X4_SVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _or (A1, A2, ZN); + ) +) // end model OR2_X4_SVT + + +model OR3_X1_SVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A3, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model OR3_X1_SVT + + +model OR3_X2_SVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A3, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model OR3_X2_SVT + + +model OR3_X4_SVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A3, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model OR3_X4_SVT + + +model OR4_X1_SVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A4, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model OR4_X1_SVT + + +model OR4_X2_SVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A4, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model OR4_X2_SVT + + +model OR4_X4_SVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A4, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model OR4_X4_SVT + + +model SDFFRS_X1_SVT + (CK, D, Q, QN, + RN, SE, SI, SN) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFFRS_X1_SVT, DFFRS_X2_SVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + input (SN) ( active_low_set; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff (net_0, net_1, CK, net_2, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _inv (RN, net_1); + primitive = _or (net_3, net_4, net_2); + primitive = _and (SE, SI, net_3); + primitive = _and (D, net_5, net_4); + primitive = _inv (SE, net_5); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFRS_X1_SVT + + +model SDFFRS_X2_SVT + (CK, D, Q, QN, + RN, SE, SI, SN) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFFRS_X2_SVT, DFFRS_X1_SVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + input (SN) ( active_low_set; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff (net_0, net_1, CK, net_2, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _inv (RN, net_1); + primitive = _or (net_3, net_4, net_2); + primitive = _and (SE, SI, net_3); + primitive = _and (D, net_5, net_4); + primitive = _inv (SE, net_5); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFRS_X2_SVT + + +model SDFFR_X1_SVT + (CK, D, Q, QN, + RN, SE, SI) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFFR_X1_SVT, DFFR_X2_SVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff ( , net_0, CK, net_1, IQ, IQN); + primitive = _inv (RN, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (SE, SI, net_2); + primitive = _and (D, net_4, net_3); + primitive = _inv (SE, net_4); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFR_X1_SVT + + +model SDFFR_X2_SVT + (CK, D, Q, QN, + RN, SE, SI) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFFR_X2_SVT, DFFR_X1_SVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff ( , net_0, CK, net_1, IQ, IQN); + primitive = _inv (RN, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (SE, SI, net_2); + primitive = _and (D, net_4, net_3); + primitive = _inv (SE, net_4); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFR_X2_SVT + + +model SDFFS_X1_SVT + (CK, D, Q, QN, + SE, SI, SN) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFFS_X1_SVT, DFFS_X2_SVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + input (SN) ( active_low_set; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff (net_0, , CK, net_1, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (SE, SI, net_2); + primitive = _and (D, net_4, net_3); + primitive = _inv (SE, net_4); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFS_X1_SVT + + +model SDFFS_X2_SVT + (CK, D, Q, QN, + SE, SI, SN) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFFS_X1_SVT, DFFS_X2_SVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + input (SN) ( active_low_set; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff (net_0, , CK, net_1, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (SE, SI, net_2); + primitive = _and (D, net_4, net_3); + primitive = _inv (SE, net_4); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFS_X2_SVT + + +model SDFF_X1_SVT + (CK, D, Q, QN, + SE, SI) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFF_X1_SVT, DFF_X2_SVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff ( , , CK, net_0, IQ, IQN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (SE, SI, net_1); + primitive = _and (D, net_3, net_2); + primitive = _inv (SE, net_3); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFF_X1_SVT + + +model SDFF_X2_SVT + (CK, D, Q, QN, + SE, SI) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFF_X2_SVT, DFF_X1_SVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff ( , , CK, net_0, IQ, IQN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (SE, SI, net_1); + primitive = _and (D, net_3, net_2); + primitive = _inv (SE, net_3); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFF_X2_SVT + + +model TBUF_X16_SVT + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X16_SVT + + +model TBUF_X1_SVT + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X1_SVT + + +model TBUF_X2_SVT + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X2_SVT + + +model TBUF_X4_SVT + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X4_SVT + + +model TBUF_X8_SVT + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X8_SVT + + +model TINV_X1_SVT + (EN, I, ZN) +( + model_source = liberty_cell; + + input (EN) ( ) + input (I) ( ) + output (ZN) ( ) + ( + primitive = _tsl (net_0, EN, ZN); + primitive = _inv (I, net_0); + ) +) // end model TINV_X1_SVT + + +model TLAT_X1_SVT + (D, G, OE, Q) +( + model_source = liberty_cell; + + input (D) ( ) + input (G) ( active_high_clock; ) + input (OE) ( ) + output (Q) ( ) + ( + primitive = _dlat ( , , G, D, IQ, ); + primitive = _tsl (IQ, net_0, Q); + primitive = _inv (OE, net_0); + ) +) // end model TLAT_X1_SVT + + +model XNOR2_X1_SVT + (A, B, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _xor (A, B, net_0); + ) +) // end model XNOR2_X1_SVT + + +model XNOR2_X2_SVT + (A, B, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _xor (A, B, net_0); + ) +) // end model XNOR2_X2_SVT + + +model XOR2_X1_SVT + (A, B, Z) +( + model_source = liberty_cell; + cell_type = xor; + simulation_function = xor; + + input (A) ( ) + input (B) ( ) + output (Z) ( ) + ( + primitive = _xor (A, B, Z); + ) +) // end model XOR2_X1_SVT + + +model XOR2_X2_SVT + (A, B, Z) +( + model_source = liberty_cell; + cell_type = xor; + simulation_function = xor; + + input (A) ( ) + input (B) ( ) + output (Z) ( ) + ( + primitive = _xor (A, B, Z); + ) +) // end model XOR2_X2_SVT diff --git a/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib b/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib new file mode 100755 index 0000000..45b61f1 --- /dev/null +++ b/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib @@ -0,0 +1,2665 @@ +// +// *********************************************************************** +// Copyright Mentor Graphics Corporation +// All Rights Reserved +// For use only with Mentor Graphics Tessent tools +// *********************************************************************** +// File Type: Tessent Cell Library +// Generated by: Tessent Shell -- write_cell_library +// Tool Version: 2019.4 +// Tool Build Date: Wed Nov 20 21:14:16 GMT 2019 +// *********************************************************************** +// Library Created : Local Time = Tue Jun 30 00:33:34 2020 +// GMT = Tue Jun 30 07:33:34 2020 + + +library_format_version = 9; + +array_delimiter = "[]"; + + +// +// *********************************************************************** +// *********** Models holding Liberty information ****************** +// *********************************************************************** +// + + +model AND2_X1_SVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _and (A1, A2, ZN); + ) +) // end model AND2_X1_SVT + + +model AND2_X2_SVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _and (A1, A2, ZN); + ) +) // end model AND2_X2_SVT + + +model AND2_X4_SVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _and (A1, A2, ZN); + ) +) // end model AND2_X4_SVT + + +model AND3_X1_SVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A3, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model AND3_X1_SVT + + +model AND3_X2_SVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A3, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model AND3_X2_SVT + + +model AND3_X4_SVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A3, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model AND3_X4_SVT + + +model AND4_X1_SVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A4, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model AND4_X1_SVT + + +model AND4_X2_SVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A4, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model AND4_X2_SVT + + +model AND4_X4_SVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A4, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model AND4_X4_SVT + + +model ANTENNA_X1_SVT + (A) +( + model_source = liberty_cell; + cell_type = prohibited; + + input (A) ( ) + ( + // Empty Model + ) +) // end model ANTENNA_X1_SVT + + +model AOI211_X1_SVT + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A, net_0); + primitive = _or (net_2, B, net_1); + primitive = _and (C1, C2, net_2); + ) +) // end model AOI211_X1_SVT + + +model AOI211_X2_SVT + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A, net_0); + primitive = _or (net_2, B, net_1); + primitive = _and (C1, C2, net_2); + ) +) // end model AOI211_X2_SVT + + +model AOI211_X4_SVT + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _or (net_3, A, net_2); + primitive = _or (net_4, B, net_3); + primitive = _and (C1, C2, net_4); + ) +) // end model AOI211_X4_SVT + + +model AOI21_X1_SVT + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A, net_1, net_0); + primitive = _and (B1, B2, net_1); + ) +) // end model AOI21_X1_SVT + + +model AOI21_X2_SVT + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A, net_1, net_0); + primitive = _and (B1, B2, net_1); + ) +) // end model AOI21_X2_SVT + + +model AOI21_X4_SVT + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A, net_1, net_0); + primitive = _and (B1, B2, net_1); + ) +) // end model AOI21_X4_SVT + + +model AOI221_X1_SVT + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_3, net_0); + primitive = _or (net_2, A, net_1); + primitive = _and (C1, C2, net_2); + primitive = _and (B1, B2, net_3); + ) +) // end model AOI221_X1_SVT + + +model AOI221_X2_SVT + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_3, net_0); + primitive = _or (net_2, A, net_1); + primitive = _and (C1, C2, net_2); + primitive = _and (B1, B2, net_3); + ) +) // end model AOI221_X2_SVT + + +model AOI221_X4_SVT + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _or (net_3, net_5, net_2); + primitive = _or (net_4, A, net_3); + primitive = _and (C1, C2, net_4); + primitive = _and (B1, B2, net_5); + ) +) // end model AOI221_X4_SVT + + +model AOI222_X1_SVT + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_4, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (A1, A2, net_2); + primitive = _and (B1, B2, net_3); + primitive = _and (C1, C2, net_4); + ) +) // end model AOI222_X1_SVT + + +model AOI222_X2_SVT + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_4, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (A1, A2, net_2); + primitive = _and (B1, B2, net_3); + primitive = _and (C1, C2, net_4); + ) +) // end model AOI222_X2_SVT + + +model AOI222_X4_SVT + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _or (net_3, net_6, net_2); + primitive = _or (net_4, net_5, net_3); + primitive = _and (A1, A2, net_4); + primitive = _and (B1, B2, net_5); + primitive = _and (C1, C2, net_6); + ) +) // end model AOI222_X4_SVT + + +model AOI22_X1_SVT + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (A1, A2, net_1); + primitive = _and (B1, B2, net_2); + ) +) // end model AOI22_X1_SVT + + +model AOI22_X2_SVT + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (A1, A2, net_1); + primitive = _and (B1, B2, net_2); + ) +) // end model AOI22_X2_SVT + + +model AOI22_X4_SVT + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (A1, A2, net_1); + primitive = _and (B1, B2, net_2); + ) +) // end model AOI22_X4_SVT + + +model BUF_X16_SVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X16_SVT + + +model BUF_X1_SVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X1_SVT + + +model BUF_X2_SVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X2_SVT + + +model BUF_X32_SVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X32_SVT + + +model BUF_X4_SVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X4_SVT + + +model BUF_X8_SVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X8_SVT + + +model CLKBUF_X1_SVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model CLKBUF_X1_SVT + + +model CLKBUF_X2_SVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model CLKBUF_X2_SVT + + +model CLKBUF_X3_SVT + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model CLKBUF_X3_SVT + + +model "CLKGATETST_X1_SVT_$_IQ" + (CK, E, SE, IQ) +( + model_source = liberty_cell_statetable; + + input (CK) ( ) + input (E) ( ) + input (SE) ( ) + output (IQ) ( ) + ( + primitive = _dlat ( , , clock_net, net_0, IQ, ); + primitive = _inv (CK, clock_net); + primitive = _or (E, SE, net_0); + ) +) // end model CLKGATETST_X1_SVT_$_IQ + + +model CLKGATETST_X1_SVT + (CK, E, GCK, SE) +( + model_source = liberty_cell; + cell_type = clock_gating_and; + simulation_function = clock_gating_and; + + input (CK) ( clock_in; ) + input (E) ( func_enable; ) + input (SE) ( test_enable; ) + output (GCK) ( clock_out; ) + ( + instance = "CLKGATETST_X1_SVT_$_IQ" (CK, E, SE, IQ); + primitive = _and (IQ, CK, GCK); + ) +) // end model CLKGATETST_X1_SVT + + +model "CLKGATETST_X2_SVT_$_IQ" + (CK, E, SE, IQ) +( + model_source = liberty_cell_statetable; + + input (CK) ( ) + input (E) ( ) + input (SE) ( ) + output (IQ) ( ) + ( + primitive = _dlat ( , , clock_net, net_0, IQ, ); + primitive = _inv (CK, clock_net); + primitive = _or (E, SE, net_0); + ) +) // end model CLKGATETST_X2_SVT_$_IQ + + +model CLKGATETST_X2_SVT + (CK, E, GCK, SE) +( + model_source = liberty_cell; + cell_type = clock_gating_and; + simulation_function = clock_gating_and; + + input (CK) ( clock_in; ) + input (E) ( func_enable; ) + input (SE) ( test_enable; ) + output (GCK) ( clock_out; ) + ( + instance = "CLKGATETST_X2_SVT_$_IQ" (CK, E, SE, IQ); + primitive = _and (IQ, CK, GCK); + ) +) // end model CLKGATETST_X2_SVT + + +model "CLKGATETST_X4_SVT_$_IQ" + (CK, E, SE, IQ) +( + model_source = liberty_cell_statetable; + + input (CK) ( ) + input (E) ( ) + input (SE) ( ) + output (IQ) ( ) + ( + primitive = _dlat ( , , clock_net, net_0, IQ, ); + primitive = _inv (CK, clock_net); + primitive = _or (E, SE, net_0); + ) +) // end model CLKGATETST_X4_SVT_$_IQ + + +model CLKGATETST_X4_SVT + (CK, E, GCK, SE) +( + model_source = liberty_cell; + cell_type = clock_gating_and; + simulation_function = clock_gating_and; + + input (CK) ( clock_in; ) + input (E) ( func_enable; ) + input (SE) ( test_enable; ) + output (GCK) ( clock_out; ) + ( + instance = "CLKGATETST_X4_SVT_$_IQ" (CK, E, SE, IQ); + primitive = _and (IQ, CK, GCK); + ) +) // end model CLKGATETST_X4_SVT + + +model "CLKGATETST_X8_SVT_$_IQ" + (CK, E, SE, IQ) +( + model_source = liberty_cell_statetable; + + input (CK) ( ) + input (E) ( ) + input (SE) ( ) + output (IQ) ( ) + ( + primitive = _dlat ( , , clock_net, net_0, IQ, ); + primitive = _inv (CK, clock_net); + primitive = _or (E, SE, net_0); + ) +) // end model CLKGATETST_X8_SVT_$_IQ + + +model CLKGATETST_X8_SVT + (CK, E, GCK, SE) +( + model_source = liberty_cell; + cell_type = clock_gating_and; + simulation_function = clock_gating_and; + + input (CK) ( clock_in; ) + input (E) ( func_enable; ) + input (SE) ( test_enable; ) + output (GCK) ( clock_out; ) + ( + instance = "CLKGATETST_X8_SVT_$_IQ" (CK, E, SE, IQ); + primitive = _and (IQ, CK, GCK); + ) +) // end model CLKGATETST_X8_SVT + + +model "CLKGATE_X1_SVT_$_IQ" + (CK, E, IQ) +( + model_source = liberty_cell_statetable; + simulation_function = latch; + + input (CK) ( active_low_clock; ) + input (E) ( data_in; ) + output (IQ) ( data_out; ) + ( + primitive = _dlat ( , , clock_net, E, IQ, ); + primitive = _inv (CK, clock_net); + ) +) // end model CLKGATE_X1_SVT_$_IQ + + +model CLKGATE_X1_SVT + (CK, E, GCK) +( + model_source = liberty_cell; + + input (CK) ( active_low_clock; ) + input (E) ( ) + output (GCK) ( ) + ( + instance = "CLKGATE_X1_SVT_$_IQ" (CK, E, IQ); + primitive = _and (CK, IQ, GCK); + ) +) // end model CLKGATE_X1_SVT + + +model "CLKGATE_X2_SVT_$_IQ" + (CK, E, IQ) +( + model_source = liberty_cell_statetable; + simulation_function = latch; + + input (CK) ( active_low_clock; ) + input (E) ( data_in; ) + output (IQ) ( data_out; ) + ( + primitive = _dlat ( , , clock_net, E, IQ, ); + primitive = _inv (CK, clock_net); + ) +) // end model CLKGATE_X2_SVT_$_IQ + + +model CLKGATE_X2_SVT + (CK, E, GCK) +( + model_source = liberty_cell; + + input (CK) ( active_low_clock; ) + input (E) ( ) + output (GCK) ( ) + ( + instance = "CLKGATE_X2_SVT_$_IQ" (CK, E, IQ); + primitive = _and (CK, IQ, GCK); + ) +) // end model CLKGATE_X2_SVT + + +model "CLKGATE_X4_SVT_$_IQ" + (CK, E, IQ) +( + model_source = liberty_cell_statetable; + simulation_function = latch; + + input (CK) ( active_low_clock; ) + input (E) ( data_in; ) + output (IQ) ( data_out; ) + ( + primitive = _dlat ( , , clock_net, E, IQ, ); + primitive = _inv (CK, clock_net); + ) +) // end model CLKGATE_X4_SVT_$_IQ + + +model CLKGATE_X4_SVT + (CK, E, GCK) +( + model_source = liberty_cell; + + input (CK) ( active_low_clock; ) + input (E) ( ) + output (GCK) ( ) + ( + instance = "CLKGATE_X4_SVT_$_IQ" (CK, E, IQ); + primitive = _and (CK, IQ, GCK); + ) +) // end model CLKGATE_X4_SVT + + +model "CLKGATE_X8_SVT_$_IQ" + (CK, E, IQ) +( + model_source = liberty_cell_statetable; + simulation_function = latch; + + input (CK) ( active_low_clock; ) + input (E) ( data_in; ) + output (IQ) ( data_out; ) + ( + primitive = _dlat ( , , clock_net, E, IQ, ); + primitive = _inv (CK, clock_net); + ) +) // end model CLKGATE_X8_SVT_$_IQ + + +model CLKGATE_X8_SVT + (CK, E, GCK) +( + model_source = liberty_cell; + + input (CK) ( active_low_clock; ) + input (E) ( ) + output (GCK) ( ) + ( + instance = "CLKGATE_X8_SVT_$_IQ" (CK, E, IQ); + primitive = _and (CK, IQ, GCK); + ) +) // end model CLKGATE_X8_SVT + + +model DFFRS_X1_SVT + (CK, D, Q, QN, + RN, SN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFFRS_X1_SVT, SDFFRS_X2_SVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SN) ( active_low_set; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff (net_0, net_1, CK, D, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _inv (RN, net_1); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFRS_X1_SVT + + +model DFFRS_X2_SVT + (CK, D, Q, QN, + RN, SN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFFRS_X2_SVT, SDFFRS_X1_SVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SN) ( active_low_set; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff (net_0, net_1, CK, D, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _inv (RN, net_1); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFRS_X2_SVT + + +model DFFR_X1_SVT + (CK, D, Q, QN, + RN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFFR_X1_SVT, SDFFR_X2_SVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff ( , net_0, CK, D, IQ, IQN); + primitive = _inv (RN, net_0); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFR_X1_SVT + + +model DFFR_X2_SVT + (CK, D, Q, QN, + RN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFFR_X2_SVT, SDFFR_X1_SVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff ( , net_0, CK, D, IQ, IQN); + primitive = _inv (RN, net_0); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFR_X2_SVT + + +model DFFS_X1_SVT + (CK, D, Q, QN, + SN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFFS_X1_SVT, SDFFS_X2_SVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SN) ( active_low_set; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff (net_0, , CK, D, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFS_X1_SVT + + +model DFFS_X2_SVT + (CK, D, Q, QN, + SN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFFS_X2_SVT, SDFFS_X1_SVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SN) ( active_low_set; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff (net_0, , CK, D, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFS_X2_SVT + + +model DFF_X1_SVT + (CK, D, Q, QN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFF_X1_SVT, SDFF_X2_SVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff ( , , CK, D, IQ, IQN); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFF_X1_SVT + + +model DFF_X2_SVT + (CK, D, Q, QN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + scan_equivalents = SDFF_X2_SVT, SDFF_X1_SVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff ( , , CK, D, IQ, IQN); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFF_X2_SVT + + +model DLH_X1_SVT + (D, G, Q) +( + model_source = liberty_cell; + cell_type = latch; + simulation_function = latch; + + input (D) ( data_in; ) + input (G) ( active_high_clock; ) + output (Q) ( data_out; ) + ( + primitive = _dlat ( , , G, D, IQ, ); + primitive = _buf (IQ, Q); + ) +) // end model DLH_X1_SVT + + +model DLH_X2_SVT + (D, G, Q) +( + model_source = liberty_cell; + cell_type = latch; + simulation_function = latch; + + input (D) ( data_in; ) + input (G) ( active_high_clock; ) + output (Q) ( data_out; ) + ( + primitive = _dlat ( , , G, D, IQ, ); + primitive = _buf (IQ, Q); + ) +) // end model DLH_X2_SVT + + +model DLL_X1_SVT + (D, GN, Q) +( + model_source = liberty_cell; + cell_type = latch; + simulation_function = latch; + + input (D) ( data_in; ) + input (GN) ( active_low_clock; ) + output (Q) ( data_out; ) + ( + primitive = _dlat ( , , net_0, D, IQ, ); + primitive = _inv (GN, net_0); + primitive = _buf (IQ, Q); + ) +) // end model DLL_X1_SVT + + +model DLL_X2_SVT + (D, GN, Q) +( + model_source = liberty_cell; + cell_type = latch; + simulation_function = latch; + + input (D) ( data_in; ) + input (GN) ( active_low_clock; ) + output (Q) ( data_out; ) + ( + primitive = _dlat ( , , net_0, D, IQ, ); + primitive = _inv (GN, net_0); + primitive = _buf (IQ, Q); + ) +) // end model DLL_X2_SVT + + +model FA_X1_SVT + (A, B, CI, CO, + S) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (CI) ( ) + output (CO) ( ) + output (S) ( ) + ( + primitive = _or (net_0, net_1, CO); + primitive = _and (A, B, net_0); + primitive = _and (CI, net_2, net_1); + primitive = _or (A, B, net_2); + primitive = _xor (CI, net_3, S); + primitive = _xor (A, B, net_3); + ) +) // end model FA_X1_SVT + + +model FILLCELL_X16_SVT + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X16_SVT + + +model FILLCELL_X1_SVT + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X1_SVT + + +model FILLCELL_X2_SVT + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X2_SVT + + +model FILLCELL_X32_SVT + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X32_SVT + + +model FILLCELL_X4_SVT + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X4_SVT + + +model FILLCELL_X8_SVT + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X8_SVT + + +model HA_X1_SVT + (A, B, CO, S) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + output (CO) ( ) + output (S) ( ) + ( + primitive = _and (A, B, CO); + primitive = _xor (A, B, S); + ) +) // end model HA_X1_SVT + + +model INV_X16_SVT + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X16_SVT + + +model INV_X1_SVT + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X1_SVT + + +model INV_X2_SVT + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X2_SVT + + +model INV_X32_SVT + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X32_SVT + + +model INV_X4_SVT + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X4_SVT + + +model INV_X8_SVT + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X8_SVT + + +model LOGIC0_X1_SVT + (Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = tie0; + + output (Z) ( ) + ( + primitive = _tie0 (Z); + ) +) // end model LOGIC0_X1_SVT + + +model LOGIC1_X1_SVT + (Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = tie1; + + output (Z) ( ) + ( + primitive = _tie1 (Z); + ) +) // end model LOGIC1_X1_SVT + + +model MUX2_X1_SVT + (A, B, S, Z) +( + model_source = liberty_cell; + cell_type = mux; + simulation_function = mux; + + input (A) ( mux_in0; ) + input (B) ( mux_in1; ) + input (S) ( mux_select; ) + output (Z) ( mux_out; ) + ( + primitive = _or (net_0, net_1, Z); + primitive = _and (S, B, net_0); + primitive = _and (A, net_2, net_1); + primitive = _inv (S, net_2); + ) +) // end model MUX2_X1_SVT + + +model MUX2_X2_SVT + (A, B, S, Z) +( + model_source = liberty_cell; + cell_type = mux; + simulation_function = mux; + + input (A) ( mux_in0; ) + input (B) ( mux_in1; ) + input (S) ( mux_select; ) + output (Z) ( mux_out; ) + ( + primitive = _or (net_0, net_1, Z); + primitive = _and (S, B, net_0); + primitive = _and (A, net_2, net_1); + primitive = _inv (S, net_2); + ) +) // end model MUX2_X2_SVT + + +model NAND2_X1_SVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model NAND2_X1_SVT + + +model NAND2_X2_SVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model NAND2_X2_SVT + + +model NAND2_X4_SVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model NAND2_X4_SVT + + +model NAND3_X1_SVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model NAND3_X1_SVT + + +model NAND3_X2_SVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model NAND3_X2_SVT + + +model NAND3_X4_SVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model NAND3_X4_SVT + + +model NAND4_X1_SVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A4, net_0); + primitive = _and (net_2, A3, net_1); + primitive = _and (A1, A2, net_2); + ) +) // end model NAND4_X1_SVT + + +model NAND4_X2_SVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A4, net_0); + primitive = _and (net_2, A3, net_1); + primitive = _and (A1, A2, net_2); + ) +) // end model NAND4_X2_SVT + + +model NAND4_X4_SVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A4, net_0); + primitive = _and (net_2, A3, net_1); + primitive = _and (A1, A2, net_2); + ) +) // end model NAND4_X4_SVT + + +model NOR2_X1_SVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model NOR2_X1_SVT + + +model NOR2_X2_SVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model NOR2_X2_SVT + + +model NOR2_X4_SVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model NOR2_X4_SVT + + +model NOR3_X1_SVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model NOR3_X1_SVT + + +model NOR3_X2_SVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model NOR3_X2_SVT + + +model NOR3_X4_SVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model NOR3_X4_SVT + + +model NOR4_X1_SVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A4, net_0); + primitive = _or (net_2, A3, net_1); + primitive = _or (A1, A2, net_2); + ) +) // end model NOR4_X1_SVT + + +model NOR4_X2_SVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A4, net_0); + primitive = _or (net_2, A3, net_1); + primitive = _or (A1, A2, net_2); + ) +) // end model NOR4_X2_SVT + + +model NOR4_X4_SVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A4, net_0); + primitive = _or (net_2, A3, net_1); + primitive = _or (A1, A2, net_2); + ) +) // end model NOR4_X4_SVT + + +model OAI211_X1_SVT + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, B, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + ) +) // end model OAI211_X1_SVT + + +model OAI211_X2_SVT + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, B, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + ) +) // end model OAI211_X2_SVT + + +model OAI211_X4_SVT + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, B, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + ) +) // end model OAI211_X4_SVT + + +model OAI21_X1_SVT + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A, net_1, net_0); + primitive = _or (B1, B2, net_1); + ) +) // end model OAI21_X1_SVT + + +model OAI21_X2_SVT + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A, net_1, net_0); + primitive = _or (B1, B2, net_1); + ) +) // end model OAI21_X2_SVT + + +model OAI21_X4_SVT + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A, net_1, net_0); + primitive = _or (B1, B2, net_1); + ) +) // end model OAI21_X4_SVT + + +model OAI221_X1_SVT + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_3, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + primitive = _or (B1, B2, net_3); + ) +) // end model OAI221_X1_SVT + + +model OAI221_X2_SVT + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_3, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + primitive = _or (B1, B2, net_3); + ) +) // end model OAI221_X2_SVT + + +model OAI221_X4_SVT + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _and (net_3, net_5, net_2); + primitive = _and (net_4, A, net_3); + primitive = _or (C1, C2, net_4); + primitive = _or (B1, B2, net_5); + ) +) // end model OAI221_X4_SVT + + +model OAI222_X1_SVT + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_4, net_0); + primitive = _and (net_2, net_3, net_1); + primitive = _or (A1, A2, net_2); + primitive = _or (B1, B2, net_3); + primitive = _or (C1, C2, net_4); + ) +) // end model OAI222_X1_SVT + + +model OAI222_X2_SVT + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_4, net_0); + primitive = _and (net_2, net_3, net_1); + primitive = _or (A1, A2, net_2); + primitive = _or (B1, B2, net_3); + primitive = _or (C1, C2, net_4); + ) +) // end model OAI222_X2_SVT + + +model OAI222_X4_SVT + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _and (net_3, net_6, net_2); + primitive = _and (net_4, net_5, net_3); + primitive = _or (A1, A2, net_4); + primitive = _or (B1, B2, net_5); + primitive = _or (C1, C2, net_6); + ) +) // end model OAI222_X4_SVT + + +model OAI22_X1_SVT + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_2, net_0); + primitive = _or (A1, A2, net_1); + primitive = _or (B1, B2, net_2); + ) +) // end model OAI22_X1_SVT + + +model OAI22_X2_SVT + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_2, net_0); + primitive = _or (A1, A2, net_1); + primitive = _or (B1, B2, net_2); + ) +) // end model OAI22_X2_SVT + + +model OAI22_X4_SVT + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_2, net_0); + primitive = _or (A1, A2, net_1); + primitive = _or (B1, B2, net_2); + ) +) // end model OAI22_X4_SVT + + +model OAI33_X1_SVT + (A1, A2, A3, B1, + B2, B3, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (B1) ( ) + input (B2) ( ) + input (B3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_3, net_0); + primitive = _or (net_2, A3, net_1); + primitive = _or (A1, A2, net_2); + primitive = _or (net_4, B3, net_3); + primitive = _or (B1, B2, net_4); + ) +) // end model OAI33_X1_SVT + + +model OR2_X1_SVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _or (A1, A2, ZN); + ) +) // end model OR2_X1_SVT + + +model OR2_X2_SVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _or (A1, A2, ZN); + ) +) // end model OR2_X2_SVT + + +model OR2_X4_SVT + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _or (A1, A2, ZN); + ) +) // end model OR2_X4_SVT + + +model OR3_X1_SVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A3, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model OR3_X1_SVT + + +model OR3_X2_SVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A3, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model OR3_X2_SVT + + +model OR3_X4_SVT + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A3, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model OR3_X4_SVT + + +model OR4_X1_SVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A4, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model OR4_X1_SVT + + +model OR4_X2_SVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A4, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model OR4_X2_SVT + + +model OR4_X4_SVT + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A4, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model OR4_X4_SVT + + +model SDFFRS_X1_SVT + (CK, D, Q, QN, + RN, SE, SI, SN) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFFRS_X1_SVT, DFFRS_X2_SVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + input (SN) ( active_low_set; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff (net_0, net_1, CK, net_2, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _inv (RN, net_1); + primitive = _or (net_3, net_4, net_2); + primitive = _and (SE, SI, net_3); + primitive = _and (D, net_5, net_4); + primitive = _inv (SE, net_5); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFRS_X1_SVT + + +model SDFFRS_X2_SVT + (CK, D, Q, QN, + RN, SE, SI, SN) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFFRS_X2_SVT, DFFRS_X1_SVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + input (SN) ( active_low_set; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff (net_0, net_1, CK, net_2, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _inv (RN, net_1); + primitive = _or (net_3, net_4, net_2); + primitive = _and (SE, SI, net_3); + primitive = _and (D, net_5, net_4); + primitive = _inv (SE, net_5); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFRS_X2_SVT + + +model SDFFR_X1_SVT + (CK, D, Q, QN, + RN, SE, SI) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFFR_X1_SVT, DFFR_X2_SVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff ( , net_0, CK, net_1, IQ, IQN); + primitive = _inv (RN, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (SE, SI, net_2); + primitive = _and (D, net_4, net_3); + primitive = _inv (SE, net_4); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFR_X1_SVT + + +model SDFFR_X2_SVT + (CK, D, Q, QN, + RN, SE, SI) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFFR_X2_SVT, DFFR_X1_SVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff ( , net_0, CK, net_1, IQ, IQN); + primitive = _inv (RN, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (SE, SI, net_2); + primitive = _and (D, net_4, net_3); + primitive = _inv (SE, net_4); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFR_X2_SVT + + +model SDFFS_X1_SVT + (CK, D, Q, QN, + SE, SI, SN) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFFS_X1_SVT, DFFS_X2_SVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + input (SN) ( active_low_set; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff (net_0, , CK, net_1, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (SE, SI, net_2); + primitive = _and (D, net_4, net_3); + primitive = _inv (SE, net_4); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFS_X1_SVT + + +model SDFFS_X2_SVT + (CK, D, Q, QN, + SE, SI, SN) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFFS_X2_SVT, DFFS_X1_SVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + input (SN) ( active_low_set; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff (net_0, , CK, net_1, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (SE, SI, net_2); + primitive = _and (D, net_4, net_3); + primitive = _inv (SE, net_4); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFS_X2_SVT + + +model SDFF_X1_SVT + (CK, D, Q, QN, + SE, SI) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFF_X1_SVT, DFF_X2_SVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff ( , , CK, net_0, IQ, IQN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (SE, SI, net_1); + primitive = _and (D, net_3, net_2); + primitive = _inv (SE, net_3); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFF_X1_SVT + + +model SDFF_X2_SVT + (CK, D, Q, QN, + SE, SI) +( + model_source = liberty_cell; + cell_type = scan_cell; + simulation_function = scan_cell; + nonscan_equivalents = DFF_X2_SVT, DFF_X1_SVT; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SE) ( scan_enable; ) + input (SI) ( scan_in; ) + output (Q) ( scan_out; ) + output (QN) ( scan_out_inv; ) + ( + primitive = _dff ( , , CK, net_0, IQ, IQN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (SE, SI, net_1); + primitive = _and (D, net_3, net_2); + primitive = _inv (SE, net_3); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFF_X2_SVT + + +model TBUF_X16_SVT + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X16_SVT + + +model TBUF_X1_SVT + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X1_SVT + + +model TBUF_X2_SVT + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X2_SVT + + +model TBUF_X4_SVT + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X4_SVT + + +model TBUF_X8_SVT + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X8_SVT + + +model TINV_X1_SVT + (EN, I, ZN) +( + model_source = liberty_cell; + + input (EN) ( ) + input (I) ( ) + output (ZN) ( ) + ( + primitive = _tsl (net_0, EN, ZN); + primitive = _inv (I, net_0); + ) +) // end model TINV_X1_SVT + + +model TLAT_X1_SVT + (D, G, OE, Q) +( + model_source = liberty_cell; + + input (D) ( ) + input (G) ( active_high_clock; ) + input (OE) ( ) + output (Q) ( ) + ( + primitive = _dlat ( , , G, D, IQ, ); + primitive = _tsl (IQ, net_0, Q); + primitive = _inv (OE, net_0); + ) +) // end model TLAT_X1_SVT + + +model XNOR2_X1_SVT + (A, B, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _xor (A, B, net_0); + ) +) // end model XNOR2_X1_SVT + + +model XNOR2_X2_SVT + (A, B, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _xor (A, B, net_0); + ) +) // end model XNOR2_X2_SVT + + +model XOR2_X1_SVT + (A, B, Z) +( + model_source = liberty_cell; + cell_type = xor; + simulation_function = xor; + + input (A) ( ) + input (B) ( ) + output (Z) ( ) + ( + primitive = _xor (A, B, Z); + ) +) // end model XOR2_X1_SVT + + +model XOR2_X2_SVT + (A, B, Z) +( + model_source = liberty_cell; + cell_type = xor; + simulation_function = xor; + + input (A) ( ) + input (B) ( ) + output (Z) ( ) + ( + primitive = _xor (A, B, Z); + ) +) // end model XOR2_X2_SVT diff --git a/libs/fastscan/NangateOpenCellLibrary_low_temp_ccs.fslib b/libs/fastscan/NangateOpenCellLibrary_low_temp_ccs.fslib new file mode 100755 index 0000000..b93fdf0 --- /dev/null +++ b/libs/fastscan/NangateOpenCellLibrary_low_temp_ccs.fslib @@ -0,0 +1,2633 @@ +// +// *********************************************************************** +// Copyright Mentor Graphics Corporation +// All Rights Reserved +// For use only with Mentor Graphics Tessent tools +// *********************************************************************** +// File Type: Tessent Cell Library +// Generated by: Tessent Shell -- write_cell_library +// Tool Version: 2019.4 +// Tool Build Date: Wed Nov 20 21:14:16 GMT 2019 +// *********************************************************************** +// Library Created : Local Time = Tue Jun 30 00:33:30 2020 +// GMT = Tue Jun 30 07:33:30 2020 + + +library_format_version = 9; + +array_delimiter = "[]"; + + +// +// *********************************************************************** +// *********** Models holding Liberty information ****************** +// *********************************************************************** +// + + +model AND2_X1 + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _and (A1, A2, ZN); + ) +) // end model AND2_X1 + + +model AND2_X2 + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _and (A1, A2, ZN); + ) +) // end model AND2_X2 + + +model AND2_X4 + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _and (A1, A2, ZN); + ) +) // end model AND2_X4 + + +model AND3_X1 + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A3, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model AND3_X1 + + +model AND3_X2 + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A3, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model AND3_X2 + + +model AND3_X4 + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A3, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model AND3_X4 + + +model AND4_X1 + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A4, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model AND4_X1 + + +model AND4_X2 + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A4, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model AND4_X2 + + +model AND4_X4 + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A4, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model AND4_X4 + + +model ANTENNA_X1 + (A) +( + model_source = liberty_cell; + cell_type = prohibited; + + input (A) ( ) + ( + // Empty Model + ) +) // end model ANTENNA_X1 + + +model AOI211_X1 + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A, net_0); + primitive = _or (net_2, B, net_1); + primitive = _and (C1, C2, net_2); + ) +) // end model AOI211_X1 + + +model AOI211_X2 + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A, net_0); + primitive = _or (net_2, B, net_1); + primitive = _and (C1, C2, net_2); + ) +) // end model AOI211_X2 + + +model AOI211_X4 + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _or (net_3, A, net_2); + primitive = _or (net_4, B, net_3); + primitive = _and (C1, C2, net_4); + ) +) // end model AOI211_X4 + + +model AOI21_X1 + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A, net_1, net_0); + primitive = _and (B1, B2, net_1); + ) +) // end model AOI21_X1 + + +model AOI21_X2 + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A, net_1, net_0); + primitive = _and (B1, B2, net_1); + ) +) // end model AOI21_X2 + + +model AOI21_X4 + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A, net_1, net_0); + primitive = _and (B1, B2, net_1); + ) +) // end model AOI21_X4 + + +model AOI221_X1 + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_3, net_0); + primitive = _or (net_2, A, net_1); + primitive = _and (C1, C2, net_2); + primitive = _and (B1, B2, net_3); + ) +) // end model AOI221_X1 + + +model AOI221_X2 + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_3, net_0); + primitive = _or (net_2, A, net_1); + primitive = _and (C1, C2, net_2); + primitive = _and (B1, B2, net_3); + ) +) // end model AOI221_X2 + + +model AOI221_X4 + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _or (net_3, net_5, net_2); + primitive = _or (net_4, A, net_3); + primitive = _and (C1, C2, net_4); + primitive = _and (B1, B2, net_5); + ) +) // end model AOI221_X4 + + +model AOI222_X1 + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_4, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (A1, A2, net_2); + primitive = _and (B1, B2, net_3); + primitive = _and (C1, C2, net_4); + ) +) // end model AOI222_X1 + + +model AOI222_X2 + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_4, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (A1, A2, net_2); + primitive = _and (B1, B2, net_3); + primitive = _and (C1, C2, net_4); + ) +) // end model AOI222_X2 + + +model AOI222_X4 + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _or (net_3, net_6, net_2); + primitive = _or (net_4, net_5, net_3); + primitive = _and (A1, A2, net_4); + primitive = _and (B1, B2, net_5); + primitive = _and (C1, C2, net_6); + ) +) // end model AOI222_X4 + + +model AOI22_X1 + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (A1, A2, net_1); + primitive = _and (B1, B2, net_2); + ) +) // end model AOI22_X1 + + +model AOI22_X2 + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (A1, A2, net_1); + primitive = _and (B1, B2, net_2); + ) +) // end model AOI22_X2 + + +model AOI22_X4 + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (A1, A2, net_1); + primitive = _and (B1, B2, net_2); + ) +) // end model AOI22_X4 + + +model BUF_X1 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X1 + + +model BUF_X16 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X16 + + +model BUF_X2 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X2 + + +model BUF_X32 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X32 + + +model BUF_X4 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X4 + + +model BUF_X8 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X8 + + +model CLKBUF_X1 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model CLKBUF_X1 + + +model CLKBUF_X2 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model CLKBUF_X2 + + +model CLKBUF_X3 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model CLKBUF_X3 + + +model "CLKGATETST_X1_$_IQ" + (CK, E, SE, IQ) +( + model_source = liberty_cell_statetable; + + input (CK) ( ) + input (E) ( ) + input (SE) ( ) + output (IQ) ( ) + ( + primitive = _dlat ( , , clock_net, net_0, IQ, ); + primitive = _inv (CK, clock_net); + primitive = _or (E, SE, net_0); + ) +) // end model CLKGATETST_X1_$_IQ + + +model CLKGATETST_X1 + (CK, E, GCK, SE) +( + model_source = liberty_cell; + cell_type = clock_gating_and; + simulation_function = clock_gating_and; + + input (CK) ( clock_in; ) + input (E) ( func_enable; ) + input (SE) ( test_enable; ) + output (GCK) ( clock_out; ) + ( + instance = "CLKGATETST_X1_$_IQ" (CK, E, SE, IQ); + primitive = _and (IQ, CK, GCK); + ) +) // end model CLKGATETST_X1 + + +model "CLKGATETST_X2_$_IQ" + (CK, E, SE, IQ) +( + model_source = liberty_cell_statetable; + + input (CK) ( ) + input (E) ( ) + input (SE) ( ) + output (IQ) ( ) + ( + primitive = _dlat ( , , clock_net, net_0, IQ, ); + primitive = _inv (CK, clock_net); + primitive = _or (E, SE, net_0); + ) +) // end model CLKGATETST_X2_$_IQ + + +model CLKGATETST_X2 + (CK, E, GCK, SE) +( + model_source = liberty_cell; + cell_type = clock_gating_and; + simulation_function = clock_gating_and; + + input (CK) ( clock_in; ) + input (E) ( func_enable; ) + input (SE) ( test_enable; ) + output (GCK) ( clock_out; ) + ( + instance = "CLKGATETST_X2_$_IQ" (CK, E, SE, IQ); + primitive = _and (IQ, CK, GCK); + ) +) // end model CLKGATETST_X2 + + +model "CLKGATETST_X4_$_IQ" + (CK, E, SE, IQ) +( + model_source = liberty_cell_statetable; + + input (CK) ( ) + input (E) ( ) + input (SE) ( ) + output (IQ) ( ) + ( + primitive = _dlat ( , , clock_net, net_0, IQ, ); + primitive = _inv (CK, clock_net); + primitive = _or (E, SE, net_0); + ) +) // end model CLKGATETST_X4_$_IQ + + +model CLKGATETST_X4 + (CK, E, GCK, SE) +( + model_source = liberty_cell; + cell_type = clock_gating_and; + simulation_function = clock_gating_and; + + input (CK) ( clock_in; ) + input (E) ( func_enable; ) + input (SE) ( test_enable; ) + output (GCK) ( clock_out; ) + ( + instance = "CLKGATETST_X4_$_IQ" (CK, E, SE, IQ); + primitive = _and (IQ, CK, GCK); + ) +) // end model CLKGATETST_X4 + + +model "CLKGATETST_X8_$_IQ" + (CK, E, SE, IQ) +( + model_source = liberty_cell_statetable; + + input (CK) ( ) + input (E) ( ) + input (SE) ( ) + output (IQ) ( ) + ( + primitive = _dlat ( , , clock_net, net_0, IQ, ); + primitive = _inv (CK, clock_net); + primitive = _or (E, SE, net_0); + ) +) // end model CLKGATETST_X8_$_IQ + + +model CLKGATETST_X8 + (CK, E, GCK, SE) +( + model_source = liberty_cell; + cell_type = clock_gating_and; + simulation_function = clock_gating_and; + + input (CK) ( clock_in; ) + input (E) ( func_enable; ) + input (SE) ( test_enable; ) + output (GCK) ( clock_out; ) + ( + instance = "CLKGATETST_X8_$_IQ" (CK, E, SE, IQ); + primitive = _and (IQ, CK, GCK); + ) +) // end model CLKGATETST_X8 + + +model "CLKGATE_X1_$_IQ" + (CK, E, IQ) +( + model_source = liberty_cell_statetable; + simulation_function = latch; + + input (CK) ( active_low_clock; ) + input (E) ( data_in; ) + output (IQ) ( data_out; ) + ( + primitive = _dlat ( , , clock_net, E, IQ, ); + primitive = _inv (CK, clock_net); + ) +) // end model CLKGATE_X1_$_IQ + + +model CLKGATE_X1 + (CK, E, GCK) +( + model_source = liberty_cell; + + input (CK) ( active_low_clock; ) + input (E) ( ) + output (GCK) ( ) + ( + instance = "CLKGATE_X1_$_IQ" (CK, E, IQ); + primitive = _and (CK, IQ, GCK); + ) +) // end model CLKGATE_X1 + + +model "CLKGATE_X2_$_IQ" + (CK, E, IQ) +( + model_source = liberty_cell_statetable; + simulation_function = latch; + + input (CK) ( active_low_clock; ) + input (E) ( data_in; ) + output (IQ) ( data_out; ) + ( + primitive = _dlat ( , , clock_net, E, IQ, ); + primitive = _inv (CK, clock_net); + ) +) // end model CLKGATE_X2_$_IQ + + +model CLKGATE_X2 + (CK, E, GCK) +( + model_source = liberty_cell; + + input (CK) ( active_low_clock; ) + input (E) ( ) + output (GCK) ( ) + ( + instance = "CLKGATE_X2_$_IQ" (CK, E, IQ); + primitive = _and (CK, IQ, GCK); + ) +) // end model CLKGATE_X2 + + +model "CLKGATE_X4_$_IQ" + (CK, E, IQ) +( + model_source = liberty_cell_statetable; + simulation_function = latch; + + input (CK) ( active_low_clock; ) + input (E) ( data_in; ) + output (IQ) ( data_out; ) + ( + primitive = _dlat ( , , clock_net, E, IQ, ); + primitive = _inv (CK, clock_net); + ) +) // end model CLKGATE_X4_$_IQ + + +model CLKGATE_X4 + (CK, E, GCK) +( + model_source = liberty_cell; + + input (CK) ( active_low_clock; ) + input (E) ( ) + output (GCK) ( ) + ( + instance = "CLKGATE_X4_$_IQ" (CK, E, IQ); + primitive = _and (CK, IQ, GCK); + ) +) // end model CLKGATE_X4 + + +model "CLKGATE_X8_$_IQ" + (CK, E, IQ) +( + model_source = liberty_cell_statetable; + simulation_function = latch; + + input (CK) ( active_low_clock; ) + input (E) ( data_in; ) + output (IQ) ( data_out; ) + ( + primitive = _dlat ( , , clock_net, E, IQ, ); + primitive = _inv (CK, clock_net); + ) +) // end model CLKGATE_X8_$_IQ + + +model CLKGATE_X8 + (CK, E, GCK) +( + model_source = liberty_cell; + + input (CK) ( active_low_clock; ) + input (E) ( ) + output (GCK) ( ) + ( + instance = "CLKGATE_X8_$_IQ" (CK, E, IQ); + primitive = _and (CK, IQ, GCK); + ) +) // end model CLKGATE_X8 + + +model DFFRS_X1 + (CK, D, Q, QN, + RN, SN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SN) ( active_low_set; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff (net_0, net_1, CK, D, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _inv (RN, net_1); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFRS_X1 + + +model DFFRS_X2 + (CK, D, Q, QN, + RN, SN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SN) ( active_low_set; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff (net_0, net_1, CK, D, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _inv (RN, net_1); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFRS_X2 + + +model DFFR_X1 + (CK, D, Q, QN, + RN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff ( , net_0, CK, D, IQ, IQN); + primitive = _inv (RN, net_0); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFR_X1 + + +model DFFR_X2 + (CK, D, Q, QN, + RN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff ( , net_0, CK, D, IQ, IQN); + primitive = _inv (RN, net_0); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFR_X2 + + +model DFFS_X1 + (CK, D, Q, QN, + SN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SN) ( active_low_set; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff (net_0, , CK, D, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFS_X1 + + +model DFFS_X2 + (CK, D, Q, QN, + SN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SN) ( active_low_set; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff (net_0, , CK, D, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFS_X2 + + +model DFF_X1 + (CK, D, Q, QN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff ( , , CK, D, IQ, IQN); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFF_X1 + + +model DFF_X2 + (CK, D, Q, QN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff ( , , CK, D, IQ, IQN); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFF_X2 + + +model DLH_X1 + (D, G, Q) +( + model_source = liberty_cell; + cell_type = latch; + simulation_function = latch; + + input (D) ( data_in; ) + input (G) ( active_high_clock; ) + output (Q) ( data_out; ) + ( + primitive = _dlat ( , , G, D, IQ, ); + primitive = _buf (IQ, Q); + ) +) // end model DLH_X1 + + +model DLH_X2 + (D, G, Q) +( + model_source = liberty_cell; + cell_type = latch; + simulation_function = latch; + + input (D) ( data_in; ) + input (G) ( active_high_clock; ) + output (Q) ( data_out; ) + ( + primitive = _dlat ( , , G, D, IQ, ); + primitive = _buf (IQ, Q); + ) +) // end model DLH_X2 + + +model DLL_X1 + (D, GN, Q) +( + model_source = liberty_cell; + cell_type = latch; + simulation_function = latch; + + input (D) ( data_in; ) + input (GN) ( active_low_clock; ) + output (Q) ( data_out; ) + ( + primitive = _dlat ( , , net_0, D, IQ, ); + primitive = _inv (GN, net_0); + primitive = _buf (IQ, Q); + ) +) // end model DLL_X1 + + +model DLL_X2 + (D, GN, Q) +( + model_source = liberty_cell; + cell_type = latch; + simulation_function = latch; + + input (D) ( data_in; ) + input (GN) ( active_low_clock; ) + output (Q) ( data_out; ) + ( + primitive = _dlat ( , , net_0, D, IQ, ); + primitive = _inv (GN, net_0); + primitive = _buf (IQ, Q); + ) +) // end model DLL_X2 + + +model FA_X1 + (A, B, CI, CO, + S) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (CI) ( ) + output (CO) ( ) + output (S) ( ) + ( + primitive = _or (net_0, net_1, CO); + primitive = _and (A, B, net_0); + primitive = _and (CI, net_2, net_1); + primitive = _or (A, B, net_2); + primitive = _xor (CI, net_3, S); + primitive = _xor (A, B, net_3); + ) +) // end model FA_X1 + + +model FILLCELL_X1 + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X1 + + +model FILLCELL_X16 + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X16 + + +model FILLCELL_X2 + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X2 + + +model FILLCELL_X32 + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X32 + + +model FILLCELL_X4 + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X4 + + +model FILLCELL_X8 + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X8 + + +model HA_X1 + (A, B, CO, S) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + output (CO) ( ) + output (S) ( ) + ( + primitive = _and (A, B, CO); + primitive = _xor (A, B, S); + ) +) // end model HA_X1 + + +model INV_X1 + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X1 + + +model INV_X16 + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X16 + + +model INV_X2 + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X2 + + +model INV_X32 + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X32 + + +model INV_X4 + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X4 + + +model INV_X8 + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X8 + + +model LOGIC0_X1 + (Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = tie0; + + output (Z) ( ) + ( + primitive = _tie0 (Z); + ) +) // end model LOGIC0_X1 + + +model LOGIC1_X1 + (Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = tie1; + + output (Z) ( ) + ( + primitive = _tie1 (Z); + ) +) // end model LOGIC1_X1 + + +model MUX2_X1 + (A, B, S, Z) +( + model_source = liberty_cell; + cell_type = mux; + simulation_function = mux; + + input (A) ( mux_in0; ) + input (B) ( mux_in1; ) + input (S) ( mux_select; ) + output (Z) ( mux_out; ) + ( + primitive = _or (net_0, net_1, Z); + primitive = _and (S, B, net_0); + primitive = _and (A, net_2, net_1); + primitive = _inv (S, net_2); + ) +) // end model MUX2_X1 + + +model MUX2_X2 + (A, B, S, Z) +( + model_source = liberty_cell; + cell_type = mux; + simulation_function = mux; + + input (A) ( mux_in0; ) + input (B) ( mux_in1; ) + input (S) ( mux_select; ) + output (Z) ( mux_out; ) + ( + primitive = _or (net_0, net_1, Z); + primitive = _and (S, B, net_0); + primitive = _and (A, net_2, net_1); + primitive = _inv (S, net_2); + ) +) // end model MUX2_X2 + + +model NAND2_X1 + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model NAND2_X1 + + +model NAND2_X2 + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model NAND2_X2 + + +model NAND2_X4 + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model NAND2_X4 + + +model NAND3_X1 + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model NAND3_X1 + + +model NAND3_X2 + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model NAND3_X2 + + +model NAND3_X4 + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model NAND3_X4 + + +model NAND4_X1 + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A4, net_0); + primitive = _and (net_2, A3, net_1); + primitive = _and (A1, A2, net_2); + ) +) // end model NAND4_X1 + + +model NAND4_X2 + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A4, net_0); + primitive = _and (net_2, A3, net_1); + primitive = _and (A1, A2, net_2); + ) +) // end model NAND4_X2 + + +model NAND4_X4 + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A4, net_0); + primitive = _and (net_2, A3, net_1); + primitive = _and (A1, A2, net_2); + ) +) // end model NAND4_X4 + + +model NOR2_X1 + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model NOR2_X1 + + +model NOR2_X2 + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model NOR2_X2 + + +model NOR2_X4 + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model NOR2_X4 + + +model NOR3_X1 + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model NOR3_X1 + + +model NOR3_X2 + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model NOR3_X2 + + +model NOR3_X4 + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model NOR3_X4 + + +model NOR4_X1 + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A4, net_0); + primitive = _or (net_2, A3, net_1); + primitive = _or (A1, A2, net_2); + ) +) // end model NOR4_X1 + + +model NOR4_X2 + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A4, net_0); + primitive = _or (net_2, A3, net_1); + primitive = _or (A1, A2, net_2); + ) +) // end model NOR4_X2 + + +model NOR4_X4 + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A4, net_0); + primitive = _or (net_2, A3, net_1); + primitive = _or (A1, A2, net_2); + ) +) // end model NOR4_X4 + + +model OAI211_X1 + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, B, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + ) +) // end model OAI211_X1 + + +model OAI211_X2 + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, B, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + ) +) // end model OAI211_X2 + + +model OAI211_X4 + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, B, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + ) +) // end model OAI211_X4 + + +model OAI21_X1 + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A, net_1, net_0); + primitive = _or (B1, B2, net_1); + ) +) // end model OAI21_X1 + + +model OAI21_X2 + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A, net_1, net_0); + primitive = _or (B1, B2, net_1); + ) +) // end model OAI21_X2 + + +model OAI21_X4 + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A, net_1, net_0); + primitive = _or (B1, B2, net_1); + ) +) // end model OAI21_X4 + + +model OAI221_X1 + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_3, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + primitive = _or (B1, B2, net_3); + ) +) // end model OAI221_X1 + + +model OAI221_X2 + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_3, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + primitive = _or (B1, B2, net_3); + ) +) // end model OAI221_X2 + + +model OAI221_X4 + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _and (net_3, net_5, net_2); + primitive = _and (net_4, A, net_3); + primitive = _or (C1, C2, net_4); + primitive = _or (B1, B2, net_5); + ) +) // end model OAI221_X4 + + +model OAI222_X1 + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_4, net_0); + primitive = _and (net_2, net_3, net_1); + primitive = _or (A1, A2, net_2); + primitive = _or (B1, B2, net_3); + primitive = _or (C1, C2, net_4); + ) +) // end model OAI222_X1 + + +model OAI222_X2 + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_4, net_0); + primitive = _and (net_2, net_3, net_1); + primitive = _or (A1, A2, net_2); + primitive = _or (B1, B2, net_3); + primitive = _or (C1, C2, net_4); + ) +) // end model OAI222_X2 + + +model OAI222_X4 + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _and (net_3, net_6, net_2); + primitive = _and (net_4, net_5, net_3); + primitive = _or (A1, A2, net_4); + primitive = _or (B1, B2, net_5); + primitive = _or (C1, C2, net_6); + ) +) // end model OAI222_X4 + + +model OAI22_X1 + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_2, net_0); + primitive = _or (A1, A2, net_1); + primitive = _or (B1, B2, net_2); + ) +) // end model OAI22_X1 + + +model OAI22_X2 + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_2, net_0); + primitive = _or (A1, A2, net_1); + primitive = _or (B1, B2, net_2); + ) +) // end model OAI22_X2 + + +model OAI22_X4 + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_2, net_0); + primitive = _or (A1, A2, net_1); + primitive = _or (B1, B2, net_2); + ) +) // end model OAI22_X4 + + +model OAI33_X1 + (A1, A2, A3, B1, + B2, B3, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (B1) ( ) + input (B2) ( ) + input (B3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_3, net_0); + primitive = _or (net_2, A3, net_1); + primitive = _or (A1, A2, net_2); + primitive = _or (net_4, B3, net_3); + primitive = _or (B1, B2, net_4); + ) +) // end model OAI33_X1 + + +model OR2_X1 + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _or (A1, A2, ZN); + ) +) // end model OR2_X1 + + +model OR2_X2 + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _or (A1, A2, ZN); + ) +) // end model OR2_X2 + + +model OR2_X4 + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _or (A1, A2, ZN); + ) +) // end model OR2_X4 + + +model OR3_X1 + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A3, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model OR3_X1 + + +model OR3_X2 + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A3, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model OR3_X2 + + +model OR3_X4 + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A3, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model OR3_X4 + + +model OR4_X1 + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A4, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model OR4_X1 + + +model OR4_X2 + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A4, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model OR4_X2 + + +model OR4_X4 + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A4, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model OR4_X4 + + +model SDFFRS_X1 + (CK, D, Q, QN, + RN, SE, SI, SN) +( + model_source = liberty_cell; + + input (CK) ( posedge_clock; ) + input (D) ( ) + input (RN) ( active_low_reset; ) + input (SE) ( ) + input (SI) ( ) + input (SN) ( active_low_set; ) + output (Q) ( ) + output (QN) ( ) + ( + primitive = _dff (net_0, net_1, CK, net_2, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _inv (RN, net_1); + primitive = _or (net_3, net_4, net_2); + primitive = _and (SE, SI, net_3); + primitive = _and (D, net_5, net_4); + primitive = _inv (SE, net_5); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFRS_X1 + + +model SDFFRS_X2 + (CK, D, Q, QN, + RN, SE, SI, SN) +( + model_source = liberty_cell; + + input (CK) ( posedge_clock; ) + input (D) ( ) + input (RN) ( active_low_reset; ) + input (SE) ( ) + input (SI) ( ) + input (SN) ( active_low_set; ) + output (Q) ( ) + output (QN) ( ) + ( + primitive = _dff (net_0, net_1, CK, net_2, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _inv (RN, net_1); + primitive = _or (net_3, net_4, net_2); + primitive = _and (SE, SI, net_3); + primitive = _and (D, net_5, net_4); + primitive = _inv (SE, net_5); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFRS_X2 + + +model SDFFR_X1 + (CK, D, Q, QN, + RN, SE, SI) +( + model_source = liberty_cell; + + input (CK) ( posedge_clock; ) + input (D) ( ) + input (RN) ( active_low_reset; ) + input (SE) ( ) + input (SI) ( ) + output (Q) ( ) + output (QN) ( ) + ( + primitive = _dff ( , net_0, CK, net_1, IQ, IQN); + primitive = _inv (RN, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (SE, SI, net_2); + primitive = _and (D, net_4, net_3); + primitive = _inv (SE, net_4); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFR_X1 + + +model SDFFR_X2 + (CK, D, Q, QN, + RN, SE, SI) +( + model_source = liberty_cell; + + input (CK) ( posedge_clock; ) + input (D) ( ) + input (RN) ( active_low_reset; ) + input (SE) ( ) + input (SI) ( ) + output (Q) ( ) + output (QN) ( ) + ( + primitive = _dff ( , net_0, CK, net_1, IQ, IQN); + primitive = _inv (RN, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (SE, SI, net_2); + primitive = _and (D, net_4, net_3); + primitive = _inv (SE, net_4); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFR_X2 + + +model SDFFS_X1 + (CK, D, Q, QN, + SE, SI, SN) +( + model_source = liberty_cell; + + input (CK) ( posedge_clock; ) + input (D) ( ) + input (SE) ( ) + input (SI) ( ) + input (SN) ( active_low_set; ) + output (Q) ( ) + output (QN) ( ) + ( + primitive = _dff (net_0, , CK, net_1, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (SE, SI, net_2); + primitive = _and (D, net_4, net_3); + primitive = _inv (SE, net_4); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFS_X1 + + +model SDFFS_X2 + (CK, D, Q, QN, + SE, SI, SN) +( + model_source = liberty_cell; + + input (CK) ( posedge_clock; ) + input (D) ( ) + input (SE) ( ) + input (SI) ( ) + input (SN) ( active_low_set; ) + output (Q) ( ) + output (QN) ( ) + ( + primitive = _dff (net_0, , CK, net_1, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (SE, SI, net_2); + primitive = _and (D, net_4, net_3); + primitive = _inv (SE, net_4); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFS_X2 + + +model SDFF_X1 + (CK, D, Q, QN, + SE, SI) +( + model_source = liberty_cell; + + input (CK) ( posedge_clock; ) + input (D) ( ) + input (SE) ( ) + input (SI) ( ) + output (Q) ( ) + output (QN) ( ) + ( + primitive = _dff ( , , CK, net_0, IQ, IQN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (SE, SI, net_1); + primitive = _and (D, net_3, net_2); + primitive = _inv (SE, net_3); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFF_X1 + + +model SDFF_X2 + (CK, D, Q, QN, + SE, SI) +( + model_source = liberty_cell; + + input (CK) ( posedge_clock; ) + input (D) ( ) + input (SE) ( ) + input (SI) ( ) + output (Q) ( ) + output (QN) ( ) + ( + primitive = _dff ( , , CK, net_0, IQ, IQN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (SE, SI, net_1); + primitive = _and (D, net_3, net_2); + primitive = _inv (SE, net_3); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFF_X2 + + +model TBUF_X1 + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X1 + + +model TBUF_X16 + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X16 + + +model TBUF_X2 + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X2 + + +model TBUF_X4 + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X4 + + +model TBUF_X8 + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X8 + + +model TINV_X1 + (EN, I, ZN) +( + model_source = liberty_cell; + + input (EN) ( ) + input (I) ( ) + output (ZN) ( ) + ( + primitive = _tsl (net_0, EN, ZN); + primitive = _inv (I, net_0); + ) +) // end model TINV_X1 + + +model TLAT_X1 + (D, G, OE, Q) +( + model_source = liberty_cell; + + input (D) ( ) + input (G) ( active_high_clock; ) + input (OE) ( ) + output (Q) ( ) + ( + primitive = _dlat ( , , G, D, IQ, ); + primitive = _tsl (IQ, net_0, Q); + primitive = _inv (OE, net_0); + ) +) // end model TLAT_X1 + + +model XNOR2_X1 + (A, B, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _xor (A, B, net_0); + ) +) // end model XNOR2_X1 + + +model XNOR2_X2 + (A, B, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _xor (A, B, net_0); + ) +) // end model XNOR2_X2 + + +model XOR2_X1 + (A, B, Z) +( + model_source = liberty_cell; + cell_type = xor; + simulation_function = xor; + + input (A) ( ) + input (B) ( ) + output (Z) ( ) + ( + primitive = _xor (A, B, Z); + ) +) // end model XOR2_X1 + + +model XOR2_X2 + (A, B, Z) +( + model_source = liberty_cell; + cell_type = xor; + simulation_function = xor; + + input (A) ( ) + input (B) ( ) + output (Z) ( ) + ( + primitive = _xor (A, B, Z); + ) +) // end model XOR2_X2 diff --git a/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib b/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib new file mode 100755 index 0000000..4318bb0 --- /dev/null +++ b/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib @@ -0,0 +1,2633 @@ +// +// *********************************************************************** +// Copyright Mentor Graphics Corporation +// All Rights Reserved +// For use only with Mentor Graphics Tessent tools +// *********************************************************************** +// File Type: Tessent Cell Library +// Generated by: Tessent Shell -- write_cell_library +// Tool Version: 2019.4 +// Tool Build Date: Wed Nov 20 21:14:16 GMT 2019 +// *********************************************************************** +// Library Created : Local Time = Tue Jun 30 00:33:32 2020 +// GMT = Tue Jun 30 07:33:32 2020 + + +library_format_version = 9; + +array_delimiter = "[]"; + + +// +// *********************************************************************** +// *********** Models holding Liberty information ****************** +// *********************************************************************** +// + + +model AND2_X1 + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _and (A1, A2, ZN); + ) +) // end model AND2_X1 + + +model AND2_X2 + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _and (A1, A2, ZN); + ) +) // end model AND2_X2 + + +model AND2_X4 + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _and (A1, A2, ZN); + ) +) // end model AND2_X4 + + +model AND3_X1 + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A3, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model AND3_X1 + + +model AND3_X2 + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A3, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model AND3_X2 + + +model AND3_X4 + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A3, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model AND3_X4 + + +model AND4_X1 + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A4, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model AND4_X1 + + +model AND4_X2 + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A4, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model AND4_X2 + + +model AND4_X4 + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = and; + simulation_function = and; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _and (net_0, A4, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model AND4_X4 + + +model ANTENNA_X1 + (A) +( + model_source = liberty_cell; + cell_type = prohibited; + + input (A) ( ) + ( + // Empty Model + ) +) // end model ANTENNA_X1 + + +model AOI211_X1 + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A, net_0); + primitive = _or (net_2, B, net_1); + primitive = _and (C1, C2, net_2); + ) +) // end model AOI211_X1 + + +model AOI211_X2 + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A, net_0); + primitive = _or (net_2, B, net_1); + primitive = _and (C1, C2, net_2); + ) +) // end model AOI211_X2 + + +model AOI211_X4 + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _or (net_3, A, net_2); + primitive = _or (net_4, B, net_3); + primitive = _and (C1, C2, net_4); + ) +) // end model AOI211_X4 + + +model AOI21_X1 + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A, net_1, net_0); + primitive = _and (B1, B2, net_1); + ) +) // end model AOI21_X1 + + +model AOI21_X2 + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A, net_1, net_0); + primitive = _and (B1, B2, net_1); + ) +) // end model AOI21_X2 + + +model AOI21_X4 + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A, net_1, net_0); + primitive = _and (B1, B2, net_1); + ) +) // end model AOI21_X4 + + +model AOI221_X1 + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_3, net_0); + primitive = _or (net_2, A, net_1); + primitive = _and (C1, C2, net_2); + primitive = _and (B1, B2, net_3); + ) +) // end model AOI221_X1 + + +model AOI221_X2 + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_3, net_0); + primitive = _or (net_2, A, net_1); + primitive = _and (C1, C2, net_2); + primitive = _and (B1, B2, net_3); + ) +) // end model AOI221_X2 + + +model AOI221_X4 + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _or (net_3, net_5, net_2); + primitive = _or (net_4, A, net_3); + primitive = _and (C1, C2, net_4); + primitive = _and (B1, B2, net_5); + ) +) // end model AOI221_X4 + + +model AOI222_X1 + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_4, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (A1, A2, net_2); + primitive = _and (B1, B2, net_3); + primitive = _and (C1, C2, net_4); + ) +) // end model AOI222_X1 + + +model AOI222_X2 + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_4, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (A1, A2, net_2); + primitive = _and (B1, B2, net_3); + primitive = _and (C1, C2, net_4); + ) +) // end model AOI222_X2 + + +model AOI222_X4 + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _or (net_3, net_6, net_2); + primitive = _or (net_4, net_5, net_3); + primitive = _and (A1, A2, net_4); + primitive = _and (B1, B2, net_5); + primitive = _and (C1, C2, net_6); + ) +) // end model AOI222_X4 + + +model AOI22_X1 + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (A1, A2, net_1); + primitive = _and (B1, B2, net_2); + ) +) // end model AOI22_X1 + + +model AOI22_X2 + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (A1, A2, net_1); + primitive = _and (B1, B2, net_2); + ) +) // end model AOI22_X2 + + +model AOI22_X4 + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (A1, A2, net_1); + primitive = _and (B1, B2, net_2); + ) +) // end model AOI22_X4 + + +model BUF_X1 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X1 + + +model BUF_X16 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X16 + + +model BUF_X2 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X2 + + +model BUF_X32 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X32 + + +model BUF_X4 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X4 + + +model BUF_X8 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model BUF_X8 + + +model CLKBUF_X1 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model CLKBUF_X1 + + +model CLKBUF_X2 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model CLKBUF_X2 + + +model CLKBUF_X3 + (A, Z) +( + model_source = liberty_cell; + cell_type = buffer; + simulation_function = buffer; + + input (A) ( ) + output (Z) ( ) + ( + primitive = _buf (A, Z); + ) +) // end model CLKBUF_X3 + + +model "CLKGATETST_X1_$_IQ" + (CK, E, SE, IQ) +( + model_source = liberty_cell_statetable; + + input (CK) ( ) + input (E) ( ) + input (SE) ( ) + output (IQ) ( ) + ( + primitive = _dlat ( , , clock_net, net_0, IQ, ); + primitive = _inv (CK, clock_net); + primitive = _or (E, SE, net_0); + ) +) // end model CLKGATETST_X1_$_IQ + + +model CLKGATETST_X1 + (CK, E, GCK, SE) +( + model_source = liberty_cell; + cell_type = clock_gating_and; + simulation_function = clock_gating_and; + + input (CK) ( clock_in; ) + input (E) ( func_enable; ) + input (SE) ( test_enable; ) + output (GCK) ( clock_out; ) + ( + instance = "CLKGATETST_X1_$_IQ" (CK, E, SE, IQ); + primitive = _and (IQ, CK, GCK); + ) +) // end model CLKGATETST_X1 + + +model "CLKGATETST_X2_$_IQ" + (CK, E, SE, IQ) +( + model_source = liberty_cell_statetable; + + input (CK) ( ) + input (E) ( ) + input (SE) ( ) + output (IQ) ( ) + ( + primitive = _dlat ( , , clock_net, net_0, IQ, ); + primitive = _inv (CK, clock_net); + primitive = _or (E, SE, net_0); + ) +) // end model CLKGATETST_X2_$_IQ + + +model CLKGATETST_X2 + (CK, E, GCK, SE) +( + model_source = liberty_cell; + cell_type = clock_gating_and; + simulation_function = clock_gating_and; + + input (CK) ( clock_in; ) + input (E) ( func_enable; ) + input (SE) ( test_enable; ) + output (GCK) ( clock_out; ) + ( + instance = "CLKGATETST_X2_$_IQ" (CK, E, SE, IQ); + primitive = _and (IQ, CK, GCK); + ) +) // end model CLKGATETST_X2 + + +model "CLKGATETST_X4_$_IQ" + (CK, E, SE, IQ) +( + model_source = liberty_cell_statetable; + + input (CK) ( ) + input (E) ( ) + input (SE) ( ) + output (IQ) ( ) + ( + primitive = _dlat ( , , clock_net, net_0, IQ, ); + primitive = _inv (CK, clock_net); + primitive = _or (E, SE, net_0); + ) +) // end model CLKGATETST_X4_$_IQ + + +model CLKGATETST_X4 + (CK, E, GCK, SE) +( + model_source = liberty_cell; + cell_type = clock_gating_and; + simulation_function = clock_gating_and; + + input (CK) ( clock_in; ) + input (E) ( func_enable; ) + input (SE) ( test_enable; ) + output (GCK) ( clock_out; ) + ( + instance = "CLKGATETST_X4_$_IQ" (CK, E, SE, IQ); + primitive = _and (IQ, CK, GCK); + ) +) // end model CLKGATETST_X4 + + +model "CLKGATETST_X8_$_IQ" + (CK, E, SE, IQ) +( + model_source = liberty_cell_statetable; + + input (CK) ( ) + input (E) ( ) + input (SE) ( ) + output (IQ) ( ) + ( + primitive = _dlat ( , , clock_net, net_0, IQ, ); + primitive = _inv (CK, clock_net); + primitive = _or (E, SE, net_0); + ) +) // end model CLKGATETST_X8_$_IQ + + +model CLKGATETST_X8 + (CK, E, GCK, SE) +( + model_source = liberty_cell; + cell_type = clock_gating_and; + simulation_function = clock_gating_and; + + input (CK) ( clock_in; ) + input (E) ( func_enable; ) + input (SE) ( test_enable; ) + output (GCK) ( clock_out; ) + ( + instance = "CLKGATETST_X8_$_IQ" (CK, E, SE, IQ); + primitive = _and (IQ, CK, GCK); + ) +) // end model CLKGATETST_X8 + + +model "CLKGATE_X1_$_IQ" + (CK, E, IQ) +( + model_source = liberty_cell_statetable; + simulation_function = latch; + + input (CK) ( active_low_clock; ) + input (E) ( data_in; ) + output (IQ) ( data_out; ) + ( + primitive = _dlat ( , , clock_net, E, IQ, ); + primitive = _inv (CK, clock_net); + ) +) // end model CLKGATE_X1_$_IQ + + +model CLKGATE_X1 + (CK, E, GCK) +( + model_source = liberty_cell; + + input (CK) ( active_low_clock; ) + input (E) ( ) + output (GCK) ( ) + ( + instance = "CLKGATE_X1_$_IQ" (CK, E, IQ); + primitive = _and (CK, IQ, GCK); + ) +) // end model CLKGATE_X1 + + +model "CLKGATE_X2_$_IQ" + (CK, E, IQ) +( + model_source = liberty_cell_statetable; + simulation_function = latch; + + input (CK) ( active_low_clock; ) + input (E) ( data_in; ) + output (IQ) ( data_out; ) + ( + primitive = _dlat ( , , clock_net, E, IQ, ); + primitive = _inv (CK, clock_net); + ) +) // end model CLKGATE_X2_$_IQ + + +model CLKGATE_X2 + (CK, E, GCK) +( + model_source = liberty_cell; + + input (CK) ( active_low_clock; ) + input (E) ( ) + output (GCK) ( ) + ( + instance = "CLKGATE_X2_$_IQ" (CK, E, IQ); + primitive = _and (CK, IQ, GCK); + ) +) // end model CLKGATE_X2 + + +model "CLKGATE_X4_$_IQ" + (CK, E, IQ) +( + model_source = liberty_cell_statetable; + simulation_function = latch; + + input (CK) ( active_low_clock; ) + input (E) ( data_in; ) + output (IQ) ( data_out; ) + ( + primitive = _dlat ( , , clock_net, E, IQ, ); + primitive = _inv (CK, clock_net); + ) +) // end model CLKGATE_X4_$_IQ + + +model CLKGATE_X4 + (CK, E, GCK) +( + model_source = liberty_cell; + + input (CK) ( active_low_clock; ) + input (E) ( ) + output (GCK) ( ) + ( + instance = "CLKGATE_X4_$_IQ" (CK, E, IQ); + primitive = _and (CK, IQ, GCK); + ) +) // end model CLKGATE_X4 + + +model "CLKGATE_X8_$_IQ" + (CK, E, IQ) +( + model_source = liberty_cell_statetable; + simulation_function = latch; + + input (CK) ( active_low_clock; ) + input (E) ( data_in; ) + output (IQ) ( data_out; ) + ( + primitive = _dlat ( , , clock_net, E, IQ, ); + primitive = _inv (CK, clock_net); + ) +) // end model CLKGATE_X8_$_IQ + + +model CLKGATE_X8 + (CK, E, GCK) +( + model_source = liberty_cell; + + input (CK) ( active_low_clock; ) + input (E) ( ) + output (GCK) ( ) + ( + instance = "CLKGATE_X8_$_IQ" (CK, E, IQ); + primitive = _and (CK, IQ, GCK); + ) +) // end model CLKGATE_X8 + + +model DFFRS_X1 + (CK, D, Q, QN, + RN, SN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SN) ( active_low_set; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff (net_0, net_1, CK, D, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _inv (RN, net_1); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFRS_X1 + + +model DFFRS_X2 + (CK, D, Q, QN, + RN, SN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + input (SN) ( active_low_set; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff (net_0, net_1, CK, D, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _inv (RN, net_1); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFRS_X2 + + +model DFFR_X1 + (CK, D, Q, QN, + RN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff ( , net_0, CK, D, IQ, IQN); + primitive = _inv (RN, net_0); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFR_X1 + + +model DFFR_X2 + (CK, D, Q, QN, + RN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (RN) ( active_low_reset; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff ( , net_0, CK, D, IQ, IQN); + primitive = _inv (RN, net_0); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFR_X2 + + +model DFFS_X1 + (CK, D, Q, QN, + SN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SN) ( active_low_set; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff (net_0, , CK, D, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFS_X1 + + +model DFFS_X2 + (CK, D, Q, QN, + SN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + input (SN) ( active_low_set; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff (net_0, , CK, D, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFFS_X2 + + +model DFF_X1 + (CK, D, Q, QN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff ( , , CK, D, IQ, IQN); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFF_X1 + + +model DFF_X2 + (CK, D, Q, QN) +( + model_source = liberty_cell; + cell_type = dff; + simulation_function = dff; + + input (CK) ( posedge_clock; ) + input (D) ( data_in; ) + output (Q) ( data_out; ) + output (QN) ( data_out_inv; ) + ( + primitive = _dff ( , , CK, D, IQ, IQN); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model DFF_X2 + + +model DLH_X1 + (D, G, Q) +( + model_source = liberty_cell; + cell_type = latch; + simulation_function = latch; + + input (D) ( data_in; ) + input (G) ( active_high_clock; ) + output (Q) ( data_out; ) + ( + primitive = _dlat ( , , G, D, IQ, ); + primitive = _buf (IQ, Q); + ) +) // end model DLH_X1 + + +model DLH_X2 + (D, G, Q) +( + model_source = liberty_cell; + cell_type = latch; + simulation_function = latch; + + input (D) ( data_in; ) + input (G) ( active_high_clock; ) + output (Q) ( data_out; ) + ( + primitive = _dlat ( , , G, D, IQ, ); + primitive = _buf (IQ, Q); + ) +) // end model DLH_X2 + + +model DLL_X1 + (D, GN, Q) +( + model_source = liberty_cell; + cell_type = latch; + simulation_function = latch; + + input (D) ( data_in; ) + input (GN) ( active_low_clock; ) + output (Q) ( data_out; ) + ( + primitive = _dlat ( , , net_0, D, IQ, ); + primitive = _inv (GN, net_0); + primitive = _buf (IQ, Q); + ) +) // end model DLL_X1 + + +model DLL_X2 + (D, GN, Q) +( + model_source = liberty_cell; + cell_type = latch; + simulation_function = latch; + + input (D) ( data_in; ) + input (GN) ( active_low_clock; ) + output (Q) ( data_out; ) + ( + primitive = _dlat ( , , net_0, D, IQ, ); + primitive = _inv (GN, net_0); + primitive = _buf (IQ, Q); + ) +) // end model DLL_X2 + + +model FA_X1 + (A, B, CI, CO, + S) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (CI) ( ) + output (CO) ( ) + output (S) ( ) + ( + primitive = _or (net_0, net_1, CO); + primitive = _and (A, B, net_0); + primitive = _and (CI, net_2, net_1); + primitive = _or (A, B, net_2); + primitive = _xor (CI, net_3, S); + primitive = _xor (A, B, net_3); + ) +) // end model FA_X1 + + +model FILLCELL_X1 + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X1 + + +model FILLCELL_X16 + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X16 + + +model FILLCELL_X2 + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X2 + + +model FILLCELL_X32 + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X32 + + +model FILLCELL_X4 + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X4 + + +model FILLCELL_X8 + ( ) +( + model_source = liberty_cell; + cell_type = prohibited; + +) // end model FILLCELL_X8 + + +model HA_X1 + (A, B, CO, S) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + output (CO) ( ) + output (S) ( ) + ( + primitive = _and (A, B, CO); + primitive = _xor (A, B, S); + ) +) // end model HA_X1 + + +model INV_X1 + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X1 + + +model INV_X16 + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X16 + + +model INV_X2 + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X2 + + +model INV_X32 + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X32 + + +model INV_X4 + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X4 + + +model INV_X8 + (A, ZN) +( + model_source = liberty_cell; + cell_type = inverter; + simulation_function = inverter; + + input (A) ( ) + output (ZN) ( ) + ( + primitive = _inv (A, ZN); + ) +) // end model INV_X8 + + +model LOGIC0_X1 + (Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = tie0; + + output (Z) ( ) + ( + primitive = _tie0 (Z); + ) +) // end model LOGIC0_X1 + + +model LOGIC1_X1 + (Z) +( + model_source = liberty_cell; + cell_type = prohibited; + simulation_function = tie1; + + output (Z) ( ) + ( + primitive = _tie1 (Z); + ) +) // end model LOGIC1_X1 + + +model MUX2_X1 + (A, B, S, Z) +( + model_source = liberty_cell; + cell_type = mux; + simulation_function = mux; + + input (A) ( mux_in0; ) + input (B) ( mux_in1; ) + input (S) ( mux_select; ) + output (Z) ( mux_out; ) + ( + primitive = _or (net_0, net_1, Z); + primitive = _and (S, B, net_0); + primitive = _and (A, net_2, net_1); + primitive = _inv (S, net_2); + ) +) // end model MUX2_X1 + + +model MUX2_X2 + (A, B, S, Z) +( + model_source = liberty_cell; + cell_type = mux; + simulation_function = mux; + + input (A) ( mux_in0; ) + input (B) ( mux_in1; ) + input (S) ( mux_select; ) + output (Z) ( mux_out; ) + ( + primitive = _or (net_0, net_1, Z); + primitive = _and (S, B, net_0); + primitive = _and (A, net_2, net_1); + primitive = _inv (S, net_2); + ) +) // end model MUX2_X2 + + +model NAND2_X1 + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model NAND2_X1 + + +model NAND2_X2 + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model NAND2_X2 + + +model NAND2_X4 + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A1, A2, net_0); + ) +) // end model NAND2_X4 + + +model NAND3_X1 + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model NAND3_X1 + + +model NAND3_X2 + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model NAND3_X2 + + +model NAND3_X4 + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A3, net_0); + primitive = _and (A1, A2, net_1); + ) +) // end model NAND3_X4 + + +model NAND4_X1 + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A4, net_0); + primitive = _and (net_2, A3, net_1); + primitive = _and (A1, A2, net_2); + ) +) // end model NAND4_X1 + + +model NAND4_X2 + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A4, net_0); + primitive = _and (net_2, A3, net_1); + primitive = _and (A1, A2, net_2); + ) +) // end model NAND4_X2 + + +model NAND4_X4 + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nand; + simulation_function = nand; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, A4, net_0); + primitive = _and (net_2, A3, net_1); + primitive = _and (A1, A2, net_2); + ) +) // end model NAND4_X4 + + +model NOR2_X1 + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model NOR2_X1 + + +model NOR2_X2 + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model NOR2_X2 + + +model NOR2_X4 + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model NOR2_X4 + + +model NOR3_X1 + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model NOR3_X1 + + +model NOR3_X2 + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model NOR3_X2 + + +model NOR3_X4 + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model NOR3_X4 + + +model NOR4_X1 + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A4, net_0); + primitive = _or (net_2, A3, net_1); + primitive = _or (A1, A2, net_2); + ) +) // end model NOR4_X1 + + +model NOR4_X2 + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A4, net_0); + primitive = _or (net_2, A3, net_1); + primitive = _or (A1, A2, net_2); + ) +) // end model NOR4_X2 + + +model NOR4_X4 + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = nor; + simulation_function = nor; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _or (net_1, A4, net_0); + primitive = _or (net_2, A3, net_1); + primitive = _or (A1, A2, net_2); + ) +) // end model NOR4_X4 + + +model OAI211_X1 + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, B, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + ) +) // end model OAI211_X1 + + +model OAI211_X2 + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, B, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + ) +) // end model OAI211_X2 + + +model OAI211_X4 + (A, B, C1, C2, + ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, B, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + ) +) // end model OAI211_X4 + + +model OAI21_X1 + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A, net_1, net_0); + primitive = _or (B1, B2, net_1); + ) +) // end model OAI21_X1 + + +model OAI21_X2 + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A, net_1, net_0); + primitive = _or (B1, B2, net_1); + ) +) // end model OAI21_X2 + + +model OAI21_X4 + (A, B1, B2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (A, net_1, net_0); + primitive = _or (B1, B2, net_1); + ) +) // end model OAI21_X4 + + +model OAI221_X1 + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_3, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + primitive = _or (B1, B2, net_3); + ) +) // end model OAI221_X1 + + +model OAI221_X2 + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_3, net_0); + primitive = _and (net_2, A, net_1); + primitive = _or (C1, C2, net_2); + primitive = _or (B1, B2, net_3); + ) +) // end model OAI221_X2 + + +model OAI221_X4 + (A, B1, B2, C1, + C2, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _and (net_3, net_5, net_2); + primitive = _and (net_4, A, net_3); + primitive = _or (C1, C2, net_4); + primitive = _or (B1, B2, net_5); + ) +) // end model OAI221_X4 + + +model OAI222_X1 + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_4, net_0); + primitive = _and (net_2, net_3, net_1); + primitive = _or (A1, A2, net_2); + primitive = _or (B1, B2, net_3); + primitive = _or (C1, C2, net_4); + ) +) // end model OAI222_X1 + + +model OAI222_X2 + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_4, net_0); + primitive = _and (net_2, net_3, net_1); + primitive = _or (A1, A2, net_2); + primitive = _or (B1, B2, net_3); + primitive = _or (C1, C2, net_4); + ) +) // end model OAI222_X2 + + +model OAI222_X4 + (A1, A2, B1, B2, + C1, C2, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + input (C1) ( ) + input (C2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _inv (net_1, net_0); + primitive = _inv (net_2, net_1); + primitive = _and (net_3, net_6, net_2); + primitive = _and (net_4, net_5, net_3); + primitive = _or (A1, A2, net_4); + primitive = _or (B1, B2, net_5); + primitive = _or (C1, C2, net_6); + ) +) // end model OAI222_X4 + + +model OAI22_X1 + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_2, net_0); + primitive = _or (A1, A2, net_1); + primitive = _or (B1, B2, net_2); + ) +) // end model OAI22_X1 + + +model OAI22_X2 + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_2, net_0); + primitive = _or (A1, A2, net_1); + primitive = _or (B1, B2, net_2); + ) +) // end model OAI22_X2 + + +model OAI22_X4 + (A1, A2, B1, B2, + ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (B1) ( ) + input (B2) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_2, net_0); + primitive = _or (A1, A2, net_1); + primitive = _or (B1, B2, net_2); + ) +) // end model OAI22_X4 + + +model OAI33_X1 + (A1, A2, A3, B1, + B2, B3, ZN) +( + model_source = liberty_cell; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (B1) ( ) + input (B2) ( ) + input (B3) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _and (net_1, net_3, net_0); + primitive = _or (net_2, A3, net_1); + primitive = _or (A1, A2, net_2); + primitive = _or (net_4, B3, net_3); + primitive = _or (B1, B2, net_4); + ) +) // end model OAI33_X1 + + +model OR2_X1 + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _or (A1, A2, ZN); + ) +) // end model OR2_X1 + + +model OR2_X2 + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _or (A1, A2, ZN); + ) +) // end model OR2_X2 + + +model OR2_X4 + (A1, A2, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + output (ZN) ( ) + ( + primitive = _or (A1, A2, ZN); + ) +) // end model OR2_X4 + + +model OR3_X1 + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A3, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model OR3_X1 + + +model OR3_X2 + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A3, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model OR3_X2 + + +model OR3_X4 + (A1, A2, A3, ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A3, ZN); + primitive = _or (A1, A2, net_0); + ) +) // end model OR3_X4 + + +model OR4_X1 + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A4, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model OR4_X1 + + +model OR4_X2 + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A4, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model OR4_X2 + + +model OR4_X4 + (A1, A2, A3, A4, + ZN) +( + model_source = liberty_cell; + cell_type = or; + simulation_function = or; + + input (A1) ( ) + input (A2) ( ) + input (A3) ( ) + input (A4) ( ) + output (ZN) ( ) + ( + primitive = _or (net_0, A4, ZN); + primitive = _or (net_1, A3, net_0); + primitive = _or (A1, A2, net_1); + ) +) // end model OR4_X4 + + +model SDFFRS_X1 + (CK, D, Q, QN, + RN, SE, SI, SN) +( + model_source = liberty_cell; + + input (CK) ( posedge_clock; ) + input (D) ( ) + input (RN) ( active_low_reset; ) + input (SE) ( ) + input (SI) ( ) + input (SN) ( active_low_set; ) + output (Q) ( ) + output (QN) ( ) + ( + primitive = _dff (net_0, net_1, CK, net_2, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _inv (RN, net_1); + primitive = _or (net_3, net_4, net_2); + primitive = _and (SE, SI, net_3); + primitive = _and (D, net_5, net_4); + primitive = _inv (SE, net_5); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFRS_X1 + + +model SDFFRS_X2 + (CK, D, Q, QN, + RN, SE, SI, SN) +( + model_source = liberty_cell; + + input (CK) ( posedge_clock; ) + input (D) ( ) + input (RN) ( active_low_reset; ) + input (SE) ( ) + input (SI) ( ) + input (SN) ( active_low_set; ) + output (Q) ( ) + output (QN) ( ) + ( + primitive = _dff (net_0, net_1, CK, net_2, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _inv (RN, net_1); + primitive = _or (net_3, net_4, net_2); + primitive = _and (SE, SI, net_3); + primitive = _and (D, net_5, net_4); + primitive = _inv (SE, net_5); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFRS_X2 + + +model SDFFR_X1 + (CK, D, Q, QN, + RN, SE, SI) +( + model_source = liberty_cell; + + input (CK) ( posedge_clock; ) + input (D) ( ) + input (RN) ( active_low_reset; ) + input (SE) ( ) + input (SI) ( ) + output (Q) ( ) + output (QN) ( ) + ( + primitive = _dff ( , net_0, CK, net_1, IQ, IQN); + primitive = _inv (RN, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (SE, SI, net_2); + primitive = _and (D, net_4, net_3); + primitive = _inv (SE, net_4); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFR_X1 + + +model SDFFR_X2 + (CK, D, Q, QN, + RN, SE, SI) +( + model_source = liberty_cell; + + input (CK) ( posedge_clock; ) + input (D) ( ) + input (RN) ( active_low_reset; ) + input (SE) ( ) + input (SI) ( ) + output (Q) ( ) + output (QN) ( ) + ( + primitive = _dff ( , net_0, CK, net_1, IQ, IQN); + primitive = _inv (RN, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (SE, SI, net_2); + primitive = _and (D, net_4, net_3); + primitive = _inv (SE, net_4); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFR_X2 + + +model SDFFS_X1 + (CK, D, Q, QN, + SE, SI, SN) +( + model_source = liberty_cell; + + input (CK) ( posedge_clock; ) + input (D) ( ) + input (SE) ( ) + input (SI) ( ) + input (SN) ( active_low_set; ) + output (Q) ( ) + output (QN) ( ) + ( + primitive = _dff (net_0, , CK, net_1, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (SE, SI, net_2); + primitive = _and (D, net_4, net_3); + primitive = _inv (SE, net_4); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFS_X1 + + +model SDFFS_X2 + (CK, D, Q, QN, + SE, SI, SN) +( + model_source = liberty_cell; + + input (CK) ( posedge_clock; ) + input (D) ( ) + input (SE) ( ) + input (SI) ( ) + input (SN) ( active_low_set; ) + output (Q) ( ) + output (QN) ( ) + ( + primitive = _dff (net_0, , CK, net_1, IQ, IQN); + primitive = _inv (SN, net_0); + primitive = _or (net_2, net_3, net_1); + primitive = _and (SE, SI, net_2); + primitive = _and (D, net_4, net_3); + primitive = _inv (SE, net_4); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFFS_X2 + + +model SDFF_X1 + (CK, D, Q, QN, + SE, SI) +( + model_source = liberty_cell; + + input (CK) ( posedge_clock; ) + input (D) ( ) + input (SE) ( ) + input (SI) ( ) + output (Q) ( ) + output (QN) ( ) + ( + primitive = _dff ( , , CK, net_0, IQ, IQN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (SE, SI, net_1); + primitive = _and (D, net_3, net_2); + primitive = _inv (SE, net_3); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFF_X1 + + +model SDFF_X2 + (CK, D, Q, QN, + SE, SI) +( + model_source = liberty_cell; + + input (CK) ( posedge_clock; ) + input (D) ( ) + input (SE) ( ) + input (SI) ( ) + output (Q) ( ) + output (QN) ( ) + ( + primitive = _dff ( , , CK, net_0, IQ, IQN); + primitive = _or (net_1, net_2, net_0); + primitive = _and (SE, SI, net_1); + primitive = _and (D, net_3, net_2); + primitive = _inv (SE, net_3); + primitive = _buf (IQ, Q); + primitive = _buf (IQN, QN); + ) +) // end model SDFF_X2 + + +model TBUF_X1 + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X1 + + +model TBUF_X16 + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X16 + + +model TBUF_X2 + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X2 + + +model TBUF_X4 + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X4 + + +model TBUF_X8 + (A, EN, Z) +( + model_source = liberty_cell; + + input (A) ( ) + input (EN) ( ) + output (Z) ( ) + ( + primitive = _tsl (A, EN, Z); + ) +) // end model TBUF_X8 + + +model TINV_X1 + (EN, I, ZN) +( + model_source = liberty_cell; + + input (EN) ( ) + input (I) ( ) + output (ZN) ( ) + ( + primitive = _tsl (net_0, EN, ZN); + primitive = _inv (I, net_0); + ) +) // end model TINV_X1 + + +model TLAT_X1 + (D, G, OE, Q) +( + model_source = liberty_cell; + + input (D) ( ) + input (G) ( active_high_clock; ) + input (OE) ( ) + output (Q) ( ) + ( + primitive = _dlat ( , , G, D, IQ, ); + primitive = _tsl (IQ, net_0, Q); + primitive = _inv (OE, net_0); + ) +) // end model TLAT_X1 + + +model XNOR2_X1 + (A, B, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _xor (A, B, net_0); + ) +) // end model XNOR2_X1 + + +model XNOR2_X2 + (A, B, ZN) +( + model_source = liberty_cell; + + input (A) ( ) + input (B) ( ) + output (ZN) ( ) + ( + primitive = _inv (net_0, ZN); + primitive = _xor (A, B, net_0); + ) +) // end model XNOR2_X2 + + +model XOR2_X1 + (A, B, Z) +( + model_source = liberty_cell; + cell_type = xor; + simulation_function = xor; + + input (A) ( ) + input (B) ( ) + output (Z) ( ) + ( + primitive = _xor (A, B, Z); + ) +) // end model XOR2_X1 + + +model XOR2_X2 + (A, B, Z) +( + model_source = liberty_cell; + cell_type = xor; + simulation_function = xor; + + input (A) ( ) + input (B) ( ) + output (Z) ( ) + ( + primitive = _xor (A, B, Z); + ) +) // end model XOR2_X2 diff --git a/libs/fastscan/PLL.fslib b/libs/fastscan/PLL.fslib new file mode 100755 index 0000000..2436bfb --- /dev/null +++ b/libs/fastscan/PLL.fslib @@ -0,0 +1,57 @@ + + +library_format_version = 9; + +array_delimiter = "[]"; + + +// +// *********************************************************************** +// *********** Models holding Liberty information ****************** +// *********************************************************************** +// + + +model PLL + (BYPASS, DIVF0, DIVF1, DIVF2, + DIVF3, DIVF4, DIVF5, DIVF6, + DIVF7, DIVQ0, DIVQ1, DIVQ2, + DIVR0, DIVR1, DIVR2, DIVR3, + DIVR4, DIVR5, FB, FSE, + LOCK, PLLOUT, RANGE0, RANGE1, + RANGE2, REF, RESET) +( + model_source = liberty_cell; + cell_type = prohibited; + + input (BYPASS) ( ) + input (DIVF0) ( ) + input (DIVF1) ( ) + input (DIVF2) ( ) + input (DIVF3) ( ) + input (DIVF4) ( ) + input (DIVF5) ( ) + input (DIVF6) ( ) + input (DIVF7) ( ) + input (DIVQ0) ( ) + input (DIVQ1) ( ) + input (DIVQ2) ( ) + input (DIVR0) ( ) + input (DIVR1) ( ) + input (DIVR2) ( ) + input (DIVR3) ( ) + input (DIVR4) ( ) + input (DIVR5) ( ) + input (FB) ( ) + input (FSE) ( ) + input (RANGE0) ( ) + input (RANGE1) ( ) + input (RANGE2) ( ) + input (REF) ( ) + input (RESET) ( ) + output (LOCK) ( ) + output (PLLOUT) ( ) + ( + // Empty Model + ) +) // end model PLL diff --git a/libs/nangate_mvt.odb b/libs/nangate_mvt.odb new file mode 100644 index 0000000..2535c22 Binary files /dev/null and b/libs/nangate_mvt.odb differ diff --git a/oasys.cmd.00 b/oasys.cmd.00 new file mode 100644 index 0000000..4d662d3 --- /dev/null +++ b/oasys.cmd.00 @@ -0,0 +1,16 @@ +#-------------------------------------------------------------------- +# date : Thu May 28 17:27:15 CEST 2026 +# ppid/pid : 2483642/2483652 +# hostname : efiapps0.ads1.fh-nuernberg.de +# arch/os : x86_64/Linux-4.18.0-553.123.1.el8_10.x86_64 +# install : /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1 +# currdir : /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock +# logfile : /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.log.00 +# tmpdir : /tmp/oasys.2483642/ +#-------------------------------------------------------------------- +# Starting Interactive Session +source scripts_risc_v/1_read_design.tcl +source scripts_risc_v/2_synthesize_optimize.tcl +#-------------------------------------------------------------------- +# End Session at Thu May 28 17:29:09 CEST 2026 +#-------------------------------------------------------------------- diff --git a/oasys.cmd.01 b/oasys.cmd.01 new file mode 100644 index 0000000..a287923 --- /dev/null +++ b/oasys.cmd.01 @@ -0,0 +1,16 @@ +#-------------------------------------------------------------------- +# date : Fri May 29 09:08:47 CEST 2026 +# ppid/pid : 2567124/2567134 +# hostname : efiapps0.ads1.fh-nuernberg.de +# arch/os : x86_64/Linux-4.18.0-553.123.1.el8_10.x86_64 +# install : /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1 +# currdir : /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock +# logfile : /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.log.01 +# tmpdir : /tmp/oasys.2567124/ +#-------------------------------------------------------------------- +# Starting Interactive Session +source scripts_risc_v/1_read_design.tcl +source scripts_risc_v/2_synthesize_optimize.tcl +#-------------------------------------------------------------------- +# End Session at Fri May 29 09:10:06 CEST 2026 +#-------------------------------------------------------------------- diff --git a/oasys.cmd.02 b/oasys.cmd.02 new file mode 100644 index 0000000..abe71fc --- /dev/null +++ b/oasys.cmd.02 @@ -0,0 +1,16 @@ +#-------------------------------------------------------------------- +# date : Fri May 29 09:12:11 CEST 2026 +# ppid/pid : 2567737/2567747 +# hostname : efiapps0.ads1.fh-nuernberg.de +# arch/os : x86_64/Linux-4.18.0-553.123.1.el8_10.x86_64 +# install : /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1 +# currdir : /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock +# logfile : /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.log.02 +# tmpdir : /tmp/oasys.2567737/ +#-------------------------------------------------------------------- +# Starting Interactive Session +source scripts_risc_v/1_read_design.tcl +source scripts_risc_v/2_synthesize_optimize.tcl +#-------------------------------------------------------------------- +# End Session at Fri May 29 09:12:46 CEST 2026 +#-------------------------------------------------------------------- diff --git a/oasys.cmd.03 b/oasys.cmd.03 new file mode 100644 index 0000000..0bef5b4 --- /dev/null +++ b/oasys.cmd.03 @@ -0,0 +1,34 @@ +#-------------------------------------------------------------------- +# date : Fri May 29 09:13:55 CEST 2026 +# ppid/pid : 2568101/2568111 +# hostname : efiapps0.ads1.fh-nuernberg.de +# arch/os : x86_64/Linux-4.18.0-553.123.1.el8_10.x86_64 +# install : /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1 +# currdir : /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock +# logfile : /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.log.03 +# tmpdir : /tmp/oasys.2568101/ +#-------------------------------------------------------------------- +# Starting Interactive Session +source scripts_risc_v/1_read_design.tcl +source scripts_risc_v/2_synthesize_optimize.tcl +report_library_cells +report_library_cells -standard +report_cells +get_library +get_target_library +library -help +get -help +get_lib_files +check_library +get_target_library +get_lib_pins +get_lib_pins -DFF_X1_LVT +get_lib_pins -of_objects DFF_X1_LVT +get_lib_pins -filter DFF_X1_LVT +get_lib_pins NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.lib DFF_X1_LVT +get_lib_pins NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.lib DFF_X1_LVTNangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.l +exot +exit +#-------------------------------------------------------------------- +# End Session at Fri May 29 09:53:51 CEST 2026 +#-------------------------------------------------------------------- diff --git a/oasys.log.00 b/oasys.log.00 new file mode 100644 index 0000000..4d92739 --- /dev/null +++ b/oasys.log.00 @@ -0,0 +1,1572 @@ +******************************************************************* +* Oasys-RTL™ - release 2022.2.R1 * +* * +* This material contains trade secrets or otherwise confidential * +* information owned by Siemens Industry Software Inc. or its * +* affiliates (collectively, "SISW"), or its licensors. Access to * +* and use of this information is strictly limited as set forth * +* in the Customer’s applicable agreements with SISW. * +* * +* Unpublished work. © 2023 Siemens * +* * +* Program : ../bin/Linux-x86_64-O/oasysGui * +* Version : 22.2-p002 * +* Date : Mon Jan 16 21:36:23 PST 2023 * +* Build : releases/22.2-54756.0-CentOS_6.5-O * +******************************************************************* + config sdc-v1.7-cpd cli cmd explore mxdb o2n fp rta mpg-m-w dft +loading: oa2tessent-d ctl verify edit bt upf-c aos conc ipc-l vcd o2pp prot int oa2ap +checked out license: psyncore + + date : Thu May 28 17:27:15 CEST 2026 + ppid/pid : 2483642/2483652 + hostname : efiapps0.ads1.fh-nuernberg.de + arch/os : x86_64/Linux-4.18.0-553.123.1.el8_10.x86_64 + install : /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1 + currdir : /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock + logfile : /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.log.00 + tmpdir : /tmp/oasys.2483642/ +> source /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/tcl/library/history.tcl +> source scripts_risc_v/1_read_design.tcl +> source scripts_risc_v/init_design.tcl +> config_shell -echo true +> config_report timing -format {cell edge arrival delay arc_delay net_delay slew net_load load fanout location power_domain} +> source scripts_risc_v/demo_chip_design_files.tcl + +----------------------------- + +Done setting design variables + +----------------------------- + +> read_db ./libs/nangate_mvt.odb +info: Reading '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/nangate_mvt.odb' [UFILE-107] + starting at 00:00:00(cpu)/0:01:18(wall) 102MB(vsz)/470MB(peak) +extracting odb ... finished at 00:00:00(cpu)/0:01:18(wall) 102MB(vsz)/470MB(peak) + Write Date : Mon, 21 Jun 2021 13:47:25 -0700 + Host : orw-ericc-r78 (64bit) + Tool Version : 21.1-p004 (60,9-71,11) + Tool Date : Fri Jun 11 12:44:10 PDT 2021 + Tool Build : 52545.0-O + Design Name : + Comment : +loading environment ... finished at 00:00:00(cpu)/0:01:18(wall) 102MB(vsz)/470MB(peak) +loading libraries ... finished at 00:00:01(cpu)/0:01:18(wall) 114MB(vsz)/476MB(peak) +all done +> create_threshold_voltage_group HVT -lib_cells {NangateOpenCellLibrary_45nm_HVT_0p85/AND2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND2_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND3_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND3_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND3_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND4_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND4_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND4_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/ANTENNA_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI21_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI21_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI21_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI22_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI22_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI22_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI211_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI211_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI211_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI221_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI221_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI221_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI222_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI222_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI222_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X16_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X32_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKBUF_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKBUF_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKBUF_X3_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFRS_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFRS_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFR_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFR_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFS_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFS_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFF_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFF_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLH_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLH_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLL_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLL_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FA_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X16_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X32_HVT NangateOpenCellLibrary_45nm_HVT_0p85/HA_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X16_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X32_HVT NangateOpenCellLibrary_45nm_HVT_0p85/LOGIC0_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/LOGIC1_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/MUX2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/MUX2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND2_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND3_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND3_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND3_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND4_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND4_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND4_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR2_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR3_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR3_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR3_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR4_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR4_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR4_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI21_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI21_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI21_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI22_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI22_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI22_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI33_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI211_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI211_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI211_X4_HVT ...(34 more)} +> create_threshold_voltage_group SVT -lib_cells {NangateOpenCellLibrary_45nm_SVT_0p85/AND2_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND2_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND2_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND3_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND3_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND3_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND4_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND4_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND4_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/ANTENNA_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI21_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI21_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI21_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI22_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI22_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI22_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI211_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI211_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI211_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI221_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI221_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI221_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI222_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI222_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI222_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X8_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X16_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X32_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKBUF_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKBUF_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKBUF_X3_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATETST_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATETST_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATETST_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATETST_X8_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATE_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATE_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATE_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATE_X8_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFFRS_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFFRS_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFFR_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFFR_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFFS_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFF_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFF_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DLH_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DLH_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DLL_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DLL_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FA_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X8_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X16_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X32_SVT NangateOpenCellLibrary_45nm_SVT_0p85/HA_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X8_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X16_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X32_SVT NangateOpenCellLibrary_45nm_SVT_0p85/LOGIC0_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/LOGIC1_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/MUX2_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/MUX2_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND2_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND2_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND2_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND3_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND3_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND3_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND4_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND4_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND4_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR2_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR2_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR2_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR3_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR3_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR3_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR4_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR4_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR4_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI21_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI21_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI21_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI22_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI22_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI22_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI33_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI211_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI211_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI211_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI221_X1_SVT ...(34 more)} +> create_threshold_voltage_group LVT -lib_cells {NangateOpenCellLibrary_45nm_LVT_0p85/AND2_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND2_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND2_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND3_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND3_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND3_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND4_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND4_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND4_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/ANTENNA_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI21_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI21_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI21_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI22_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI22_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI22_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI211_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI211_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI211_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI221_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI221_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI221_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI222_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI222_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI222_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/BUF_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/BUF_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/BUF_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/BUF_X8_LVT NangateOpenCellLibrary_45nm_LVT_0p85/BUF_X16_LVT NangateOpenCellLibrary_45nm_LVT_0p85/BUF_X32_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKBUF_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKBUF_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKBUF_X3_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATETST_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATETST_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATETST_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATETST_X8_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATE_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATE_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATE_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATE_X8_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFFRS_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFFRS_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFFR_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFFR_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFFS_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFFS_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFF_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFF_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DLH_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DLH_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DLL_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DLL_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/FA_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/FILLCELL_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/FILLCELL_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/FILLCELL_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/FILLCELL_X8_LVT NangateOpenCellLibrary_45nm_LVT_0p85/FILLCELL_X16_LVT NangateOpenCellLibrary_45nm_LVT_0p85/FILLCELL_X32_LVT NangateOpenCellLibrary_45nm_LVT_0p85/HA_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/INV_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/INV_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/INV_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/INV_X8_LVT NangateOpenCellLibrary_45nm_LVT_0p85/INV_X16_LVT NangateOpenCellLibrary_45nm_LVT_0p85/INV_X32_LVT NangateOpenCellLibrary_45nm_LVT_0p85/LOGIC0_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/LOGIC1_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/MUX2_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/MUX2_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND2_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND2_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND2_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND3_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND3_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND3_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND4_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND4_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND4_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR2_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR2_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR2_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR3_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR3_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR3_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR4_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR4_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR4_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI21_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI21_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI21_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI22_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI22_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI22_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI33_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI211_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI211_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI211_X4_LVT ...(34 more)} +> report_operating_conditions +Report Operating conditions: +-----+---------------+--------+-------------+------------------------------------+--------+--------+----------- + |Name |Default?|Type |Library |Process |Voltage |Temperature +-----+---------------+--------+-------------+------------------------------------+--------+--------+----------- +1 |typical | |standard cell|IO |1.000000|1.100000| 27.000000 +2 |TYP | |standard cell|PLL_TYP |1.000000|0.900000| 25.000000 +3 |typical | |standard cell|MemGen_16_10 |1.000000|1.800000| 25.000000 +4 |worst_low_0p85V| |standard cell|NangateOpenCellLibrary_45nm_HVT_0p85|1.000000|0.850000| -40.000000 +5 |worst_low | |standard cell|NangateOpenCellLibrary_45nm_HVT |1.000000|0.950000| -40.000000 +-----+---------------+--------+-------------+------------------------------------+--------+--------+----------- +> config_tolerance -blackbox true -connection_mismatch true -missing_physical_library true -continue_on_error false +> read_verilog -sv {alu.sv cpu.sv decoder.sv MemGen_32_11.sv main_mem.sv pc.sv reg_file.sv} -include ./riscv_rtl/hw/rtl +info: File 'alu.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/./riscv_rtl/hw/rtl/alu.sv' using search_path variable. [CMD-126] +info: File 'cpu.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/./riscv_rtl/hw/rtl/cpu.sv' using search_path variable. [CMD-126] +info: File 'decoder.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/./riscv_rtl/hw/rtl/decoder.sv' using search_path variable. [CMD-126] +info: File 'MemGen_32_11.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/./riscv_rtl/hw/rtl/MemGen_32_11.sv' using search_path variable. [CMD-126] +info: File 'main_mem.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/./riscv_rtl/hw/rtl/main_mem.sv' using search_path variable. [CMD-126] +info: File 'pc.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/./riscv_rtl/hw/rtl/pc.sv' using search_path variable. [CMD-126] +info: File 'reg_file.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/./riscv_rtl/hw/rtl/reg_file.sv' using search_path variable. [CMD-126] +> set_max_route_layer 10 +Top-most available layer for routing set to metal10 +> set_dont_use {IO/PADBID IO/PADCLK PLL_TYP/PLL MemGen_16_10/MemGen_16_10 NangateOpenCellLibrary_45nm_HVT_0p85/AND2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND2_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND3_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND3_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND3_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND4_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND4_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND4_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/ANTENNA_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI21_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI21_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI21_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI22_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI22_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI22_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI211_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI211_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI211_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI221_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI221_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI221_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI222_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI222_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI222_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X16_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X32_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKBUF_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKBUF_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKBUF_X3_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFRS_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFRS_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFR_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFR_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFS_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFS_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFF_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFF_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLH_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLH_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLL_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLL_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FA_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X16_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X32_HVT NangateOpenCellLibrary_45nm_HVT_0p85/HA_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X16_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X32_HVT NangateOpenCellLibrary_45nm_HVT_0p85/LOGIC0_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/LOGIC1_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/MUX2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/MUX2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND2_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND3_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND3_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND3_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND4_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND4_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND4_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR2_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR3_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR3_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR3_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR4_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR4_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR4_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI21_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI21_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI21_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI22_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI22_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI22_X4_HVT ...(306 more)} false + +----------------------------- + +Done preparing design for synthesis + +----------------------------- + +> source scripts_risc_v/2_synthesize_optimize.tcl +> synthesize -module cpu -map_to_scan +starting synthesize at 00:00:01(cpu)/0:01:24(wall) 120MB(vsz)/480MB(peak) +warning: skipping cell ANTENNA_X1_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell FILLCELL_X1_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell FILLCELL_X2_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell FILLCELL_X4_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell FILLCELL_X8_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell FILLCELL_X16_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell FILLCELL_X32_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell LOGIC0_X1_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell LOGIC1_X1_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell ANTENNA_X1_HVT in the library since it does not have delay arcs [NL-215] +-------> Message [NL-215] suppressed 44 times +info: clock-gating cell for posedge FFs = CLKGATE_X1_LVT in target library 'default' [POWER-112] +info: no clock-gating cell found in target library 'default' for negedge FFs for the given specification [POWER-113] +info: clock_gating minimum_width = 4, maximum_fanout = 2147483647, num_stages = 2147483647, sequential_cell = (null), control_port = (null), control_point = none, observability = no, use_discrete_cells = no, create_multi_stage = no, merge_multi_stage = no, exclude_instantiated_clock_gates = no, log = (null), allow_clock_inversion = no [POWER-111] +info: synthesizing module 'cpu' (depth 1) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/cpu.sv:17)[7]) [VLOG-400] +info: synthesizing module 'decoder' (depth 2) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/decoder.sv:17)[7]) [VLOG-400] +info: synthesizing module 'alu' (depth 3) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/alu.sv:16)[7]) [VLOG-400] +info: done synthesizing module 'alu' (depth 3) (1#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/alu.sv:16)[7]) [VLOG-401] +info: done synthesizing module 'decoder' (depth 2) (2#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/decoder.sv:17)[7]) [VLOG-401] +info: synthesizing module 'reg_file' (depth 2) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/reg_file.sv:15)[7]) [VLOG-400] +warning: target library has multiple operating conditions defined, but no default has been set. Assuming default voltage 0.85V, temperature -40.00 and process 1.00 [LIB-218] +info: done synthesizing module 'reg_file' (depth 2) (3#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/reg_file.sv:15)[7]) [VLOG-401] +info: synthesizing module 'pc' (depth 2) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/pc.sv:16)[7]) [VLOG-400] +info: done synthesizing module 'pc' (depth 2) (4#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/pc.sv:16)[7]) [VLOG-401] +info: synthesizing module 'main_mem' (depth 2) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:18)[7]) [VLOG-400] +info: synthesizing module 'MemGen_32_11' (depth 3) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/MemGen_32_11.sv:1)[7]) [VLOG-400] +info: done synthesizing module 'MemGen_32_11' (depth 3) (5#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/MemGen_32_11.sv:1)[7]) [VLOG-401] +warning: always_comb on 'DRData' did not result in combinational logic ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:110)[8], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:113)[16], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:114)[16], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:118)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:119)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:120)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:121)[17]) [SYN-112] +warning: inferring latch for variable 'DRData' ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:110)[8], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:113)[16], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:114)[16], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:118)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:119)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:120)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:121)[17]) [VLOG-566] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +-------> Message [POWER-102] suppressed 22 times +info: done synthesizing module 'main_mem' (depth 2) (6#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:18)[7]) [VLOG-401] +info: done synthesizing module 'cpu' (depth 1) (7#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/cpu.sv:17)[7]) [VLOG-401] +finished synthesize at 00:00:02(cpu)/0:01:25(wall) 175MB(vsz)/532MB(peak) +> set_route_layer_max_usage metal2 0.5 +> set_route_layer_max_usage metal3 0.8 +> set_route_layer_max_usage metal6 0.8 +> write_db ./output/odb/riscv_chip.syn.odb +info: design 'cpu' has no physical info [WRITE-120] +warning: WrSdc.. design 'cpu' has no timing constraints [TA-118] +> read_sdc -verbose ./constraints/riscv.sdc +> create_clock -name clk_25mhz -period 40.000 -waveform { 0 20 } clk_25mhz +> set_clock_uncertainty -setup 0.5 clk_25mhz +> set_clock_uncertainty -hold 0.2 clk_25mhz +> set_clock_transition 0.1 clk_25mhz +> set_input_delay -clock clk_25mhz -max 2.0 { btn[6] btn[5] btn[4] btn[3] btn[2] btn[1] btn[0] } +> set_input_delay -clock clk_25mhz -min 0.5 { btn[6] btn[5] btn[4] btn[3] btn[2] btn[1] btn[0] } +> set_output_delay -clock clk_25mhz -max 2.0 { led[7] led[6] led[5] led[4] led[3] led[2] led[1] led[0] } +> set_output_delay -clock clk_25mhz -min 0.5 { led[7] led[6] led[5] led[4] led[3] led[2] led[1] led[0] } +> set_false_path -from btn[0] +# set_false_path -from btn[0] +> set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 { btn[6] btn[5] btn[4] btn[3] btn[2] btn[1] btn[0] } +> set_load 0.05 { led[7] led[6] led[5] led[4] led[3] led[2] led[1] led[0] } +> current_design +> set_max_fanout 20 cpu +> current_design +> set_max_transition 0.5 cpu +info: 'set_max_fanout' command ignored 1 time(s) [SDC-148] +info: 'set_max_transition' command ignored 1 time(s) [SDC-150] +> report_design_metrics +Report Physical info: +------------------------+--------+-----------+------------ + | |Area (squm)|Leakage (uW) +------------------------+--------+-----------+------------ +Design Name |cpu | | + Total Instances | 7261| 60155| 625.778 + Macros | 4| 46249| 518.216 + Pads | 0| 0| 0.000 + Phys | 0| 0| 0.000 + Blackboxes | 0| 0| 0.000 + Cells | 7257| 13906| 107.562 + Buffers | 0| 0| 0.000 + Inverters | 640| 340| 4.488 + Clock-Gates | 31| 107| 0.667 + Combinational | 5423| 6454| 51.129 + Latches | 32| 85| 0.602 + FlipFlops | 1131| 6919| 50.677 + Single-Bit FF | 1131| 6919| 50.677 + Multi-Bit FF | 0| 0| 0.000 + Clock-Gated | 992| | + Bits | 1131| 6919| 50.677 + Load-Enabled | 0| | + Clock-Gated | 992| | + Tristate Pin Count | 0| | +Physical Info |Unplaced| | + Chip Size (mm x mm) | | 0| + Fixed Cell Area | | 0| + Phys Only | 0| 0| + Placeable Area | | 0| + Movable Cell Area | | 60155| + Utilization (%) | | | + Chip Utilization (%) | | | + Total Wire Length (mm)| 0.000| | + Longest Wire (mm) | | | + Average Wire (mm) | | | +------------------------+--------+-----------+------------ +> check_timing +Report Check Timing: +-----+------------------------------+------+--------+------+----------------------------------------------- + |Item |Errors|Warnings|Status|Description +-----+------------------------------+------+--------+------+----------------------------------------------- +1 |no_clock_defined | 0| 0|Passed|No clock is defined in the design +2 |invalid_generated_clock | 0| 0|Passed|Generated clock is not sourced by a valid clock +3 |unconstrained_IO | 0| 0|Passed|Unconstrained IO pin +4 |unexpected_assertion | 0| 0|Passed|Found unexpected timing assertion +5 |trigger_pin_without_required | 0| 32|Passed|Trigger pin does not get required data +6 |setup_pin_without_data | 0| 0|Passed|Setup pin does not get arriving data +7 |setup_pin_with_clock | 0| 0|Passed|Setup pin has clock signal arriving +8 |clock_pin_with_multiple_clocks| 0| 0|Passed|Clock pin has multiple clock signals +9 |clock_pin_without_clock | 0| 1|Passed|Clock pin does not have clock signal +10 |clock_pin_with_data | 0| 1|Passed|Clock pin has data signal arriving +-----+------------------------------+------+--------+------+----------------------------------------------- +> all_inputs +> group_path -name I2R -from { btn[6] btn[5] btn[4] btn[3] btn[2] btn[1] btn[0] clk_25mhz } +# group_path -from {btn[6]} {btn[5]} {btn[4]} {btn[3]} {btn[2]} {btn[1]} {btn[0]} clk_25mhz +> all_inputs +> all_outputs +> group_path -name I2O -from { btn[6] btn[5] btn[4] btn[3] btn[2] btn[1] btn[0] clk_25mhz } -to { led[7] led[6] led[5] led[4] led[3] led[2] led[1] led[0] } +# group_path -from {btn[6]} {btn[5]} {btn[4]} {btn[3]} {btn[2]} {btn[1]} {btn[0]} clk_25mhz -to {led[7]} {led[6]} {led[5]} {led[4]} {led[3]} {led[2]} {led[1]} {led[0]} +> all_outputs +> group_path -name R2O -to { led[7] led[6] led[5] led[4] led[3] led[2] led[1] led[0] } +# group_path -to {led[7]} {led[6]} {led[5]} {led[4]} {led[3]} {led[2]} {led[1]} {led[0]} +> report_path_groups +Report Path Groups: +-----+-------+------+---------+--------- + | Path |Weight|Critical |Worst + | Group | |Range(ps)|Slack(ps) +-----+-------+------+---------+--------- +1 |default| 1.000| 0.0| 17832.1 +2 |I2R | 1.000| 0.0| +3 |I2O | 1.000| 0.0| +4 |R2O | 1.000| 0.0| 36153.7 +-----+-------+------+---------+--------- +> optimize -virtual +starting optimize at 00:00:03(cpu)/0:01:27(wall) 183MB(vsz)/532MB(peak) +info: mapped 0 flop(s) to scan cells, excluded 0 is_dont_scan flop(s) and 0 is_dont_touch flop(s) +Log file for child PID=2483733: /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.etc.00/oasys.w1.00.log +Log file for child PID=2483737: /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.etc.00/oasys.w2.00.log +Log file for child PID=2483744: /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.etc.00/oasys.w3.00.log +Log file for child PID=2483750: /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.etc.00/oasys.w4.00.log +info: optimized '' area changed 0.0squm (x1), total 13904.4squm (#1, 0 secs) +info: dissolving instance 'thePC' of module 'pc' in module 'cpu__GC0' [NL-146] +info: optimized 'cpu__GC0' area changed -1457.9squm (x1), total 12446.4squm (#2) +info: optimized 'reg_file__GB1' area changed -841.1squm (x1), total 11605.3squm (#3) +info: optimized 'reg_file__always' area changed -83.5squm (x1), total 11521.8squm (#4) +info: optimized 'main_mem__GC0' area changed -90.4squm (x1), total 11431.3squm (#5) +info: optimized 'MemGen_32_11__block' area changed -2.4squm (x1), total 11429.0squm (#6) +info: optimized '' area changed 0.0squm (x1), total 11429.0squm (#7, 0 secs) +info: optimized 'cpu__GC0' area changed 0.0squm (x1), total 11429.0squm (#8) +info: optimized 'MemGen_32_11__block' area changed 0.0squm (x1), total 11429.0squm (#9) +info: optimized '' area changed 0.0squm (x1), total 11429.0squm (#10, 0 secs) +done optimizing area at 00:00:15(cpu)/0:01:33(wall) 182MB(vsz)/566MB(peak) +Splitting congested rtl-partitions +info: Target library/cell information has changed that further may change timing results. [TA-159] +info: optimizing design 'cpu' - propagating constants +info: optimized '' area changed 0.0squm (x1), total 11429.0squm (#1, 0 secs) +info: set slack mode to optimize shift +info: resetting all path groups +info: activated path group default @ 18015.8ps +info: suspended path group I2R @ ps +info: suspended path group I2O @ ps +info: activated path group R2O @ 36338.3ps +info: finished path group default @ 18015.8ps +info: finished path group R2O @ 36338.3ps +info: reactivating path groups +info: reactivated path group default @ 18015.8ps +info: reactivated path group R2O @ 36338.3ps +info: finished path group default @ 18015.8ps +info: finished path group R2O @ 36338.3ps +info: set slack mode to normal +info: done with all path groups +info: restore all path groups +info: starting area recovery on module cpu +info: optimized 'cpu__GC0' area recovered 0.00squm (x1), total 0.00squm (1#5), 0.03 secs +info: optimized 'main_mem__GC0' area recovered 0.00squm (x1), total 0.00squm (2#5), 0.05 secs +info: optimized 'MemGen_32_11__block' area recovered 0.00squm (x1), total 0.00squm (3#5), 0.01 secs +info: optimized 'reg_file__always' area recovered 0.00squm (x1), total 0.00squm (4#5), 0.01 secs +info: optimized 'reg_file__GB1' area recovered 0.00squm (x1), total 0.00squm (5#5), 0.03 secs +info: area recovery done, total area reduction: 0.00squm (0.00%), final slack: 18015.8ps (delta: 0.0ps) (0 secs) +done optimizing virtual at 00:00:16(cpu)/0:01:34(wall) 198MB(vsz)/566MB(peak) +finished optimize at 00:00:16(cpu)/0:01:34(wall) 198MB(vsz)/566MB(peak) +> write_db ./output/odb/riscv_chip.virtual_opt.odb +> report_timing +Report for group default +-------------------------------------------------------------------------------------------------------------------------------------- +Startpoint: theMem/IRData_reg[18]/Q + (Clocked by clk_25mhz R) +Endpoint: theMem/mem_addr_reg[5]/D + (Clocked by clk_25mhz F) +Path Group: default +Data required time: 19227.4 + (Clock shift: 20000.0, minus Uncertainty: 500.0, plus Latency 0.0, minus Setup time: 272.6) +Data arrival time: 1211.5 +Slack: 18015.8 +Logic depth: 46 +-------------------------------------------------------------------------------------------------------------------------------------- + Arrival Arc Net Net Total fan- +Path Module/Cell Edge Time Delay Delay Delay Slew Load Load out Location + (ps) (ps) (ps) (ps) (ps) (ff) (ff) (#) (um,um) +-------------------------------------------------------------------------------------------------------------------------------------- +clk_25mhz {create_clock} r 0.0 0.0 0.0 0.0 0.0 100 +theMem/IRData_reg[18]/CK->Q + SDFF_X1_LVT* rr 84.9 84.9 84.9 0.0 100.0 10.6 73.4 11 +theRegisters/i_1_0_1371/A->ZN + INV_X8_LVT rf 87.6 2.7 2.7 0.0 10.2 2.1 13.2 3 +theRegisters/i_1_0_1339/A2->ZN + NAND3_X4_LVT fr 101.6 14.0 14.0 0.0 1.0 2.5 17.5 4 +theRegisters/i_1_0_1321/A2->ZN + NOR2_X4_LVT* rf 120.6 19.0 19.0 0.0 12.1 29.7 130.1 32 +theRegisters/i_1_0_722/B1->ZN + AOI22_X4_LVT* fr 164.9 44.3 44.3 0.0 10.2 0.7 23.4 1 +theRegisters/i_1_0_721/A->ZN + INV_X8_LVT rf 167.0 2.1 2.1 0.0 10.2 0.8 3.0 1 +theRegisters/i_1_0_718/A->ZN + AOI221_X2_LVT fr 224.3 57.3 57.3 0.0 0.6 0.9 4.4 1 +theRegisters/i_1_0_716/A3->ZN + NAND4_X4_LVT rf 239.7 15.4 15.4 0.0 34.6 0.9 3.1 1 +theRegisters/i_1_0_715/A->ZN + AOI221_X2_LVT fr 297.1 57.4 57.4 0.0 6.8 0.9 4.3 1 +theRegisters/i_1_0_704/A2->ZN + NAND4_X4_LVT rf 317.6 20.5 20.5 0.0 34.4 5.9 16.7 3 +theDecoder/i_0_133/C2->ZN + AOI222_X4_LVT fr 428.0 110.5 110.5 0.0 12.2 0.8 23.5 1 +theDecoder/i_0_132/A->ZN INV_X32_LVT rf 431.2 3.1 3.1 0.0 10.9 5.4 65.3 7 +theDecoder/theALU/i_0_706/B1->ZN + OAI22_X4_LVT* fr 474.4 43.2 43.2 0.0 1.4 1.5 25.9 2 +theDecoder/theALU/i_0_705/A->ZN + INV_X8_LVT rf 476.5 2.2 2.2 0.0 10.2 0.6 4.2 1 +theDecoder/theALU/i_0_42/A->ZN + OAI21_X2_LVT fr 485.6 9.1 9.1 0.0 0.6 0.8 2.5 1 +theDecoder/theALU/i_0_40/C1->ZN + AOI211_X2_LVT rf 491.3 5.6 5.6 0.0 11.6 0.8 2.9 1 +theDecoder/theALU/i_0_39/B->ZN + AOI211_X2_LVT fr 538.7 47.4 47.4 0.0 3.3 0.9 3.0 1 +theDecoder/theALU/i_0_38/B2->ZN + OAI222_X2_LVT rf 555.6 16.9 16.9 0.0 27.7 0.9 2.9 1 +theDecoder/theALU/i_0_37/C2->ZN + AOI221_X2_LVT fr 599.5 43.8 43.8 0.0 8.4 0.9 4.2 1 +theDecoder/theALU/i_0_35/B1->ZN + OAI22_X4_LVT* rf 613.4 13.9 13.9 0.0 34.0 0.7 23.4 1 +theDecoder/theALU/i_0_34/A->ZN + INV_X8_LVT fr 617.9 4.5 4.5 0.0 10.2 0.6 4.1 1 +theDecoder/theALU/i_0_33/A->ZN + AOI21_X4_LVT rf 620.5 2.6 2.6 0.0 2.4 0.8 3.0 1 +theDecoder/theALU/i_0_32/C2->ZN + OAI222_X2_LVT fr 659.0 38.5 38.5 0.0 2.6 0.9 3.3 1 +theDecoder/theALU/i_0_31/A->ZN + OAI221_X2_LVT rf 675.0 16.0 16.0 0.0 29.2 0.8 4.0 1 +theDecoder/theALU/i_0_28/B1->ZN + AOI21_X4_LVT fr 690.5 15.5 15.5 0.0 8.2 0.8 3.0 1 +theDecoder/theALU/i_0_27/A->ZN + AOI221_X2_LVT rf 694.7 4.2 4.2 0.0 13.5 0.9 2.9 1 +theDecoder/theALU/i_0_26/B->ZN + AOI211_X2_LVT fr 746.9 52.2 52.2 0.0 5.3 0.8 4.6 1 +theDecoder/theALU/i_0_25/B2->ZN + OAI22_X2_LVT rf 756.6 9.7 9.7 0.0 31.8 0.8 2.7 1 +theDecoder/theALU/i_0_24/C2->ZN + AOI211_X2_LVT fr 791.0 34.4 34.4 0.0 4.0 0.9 3.1 1 +theDecoder/theALU/i_0_23/A->ZN + AOI221_X2_LVT rf 796.7 5.8 5.8 0.0 27.8 0.9 3.1 1 +theDecoder/theALU/i_0_22/A->ZN + AOI221_X2_LVT fr 850.4 53.7 53.7 0.0 5.4 0.9 3.1 1 +theDecoder/theALU/i_0_21/A->ZN + AOI221_X2_LVT rf 856.5 6.1 6.1 0.0 31.2 0.9 3.1 1 +theDecoder/theALU/i_0_20/C2->ZN + OAI222_X2_LVT fr 895.2 38.8 38.8 0.0 5.4 0.9 3.3 1 +theDecoder/theALU/i_0_19/A->ZN + OAI221_X2_LVT rf 911.8 16.6 16.6 0.0 29.2 0.9 4.7 1 +theDecoder/theALU/i_0_18/B2->ZN + AOI22_X4_LVT fr 942.1 30.3 30.3 0.0 8.6 0.8 4.4 1 +theDecoder/theALU/i_0_17/B2->ZN + OAI21_X4_LVT rf 948.5 6.4 6.4 0.0 16.9 0.7 4.3 1 +theDecoder/theALU/i_0_16/A->ZN + OAI21_X4_LVT fr 958.3 9.8 9.8 0.0 3.6 0.7 3.9 1 +theDecoder/theALU/i_0_13/B1->ZN + AOI21_X4_LVT rf 963.5 5.3 5.3 0.0 12.5 0.8 4.4 1 +theDecoder/theALU/i_0_12/A4->ZN + NOR4_X2_LVT fr 1020.0 56.5 56.5 0.0 2.9 0.8 2.8 1 +theDecoder/theALU/i_0_0/A3->ZN + OR3_X4_LVT rr 1036.6 16.6 16.6 0.0 29.1 0.7 14.7 2 +theDecoder/i_0_114/B->ZN XNOR2_X2_LVT rf 1043.2 6.5 6.5 0.0 7.8 0.7 4.3 1 +theDecoder/i_0_113/B1->ZN + AOI22_X4_LVT fr 1069.7 26.5 26.5 0.0 5.1 0.8 4.4 1 +theDecoder/i_0_111/A2->ZN + AOI22_X4_LVT rf 1076.1 6.4 6.4 0.0 16.9 0.7 4.3 1 +theDecoder/i_0_110/A2->ZN + NAND2_X4_LVT* fr 1095.3 19.2 19.2 0.0 4.4 9.0 37.6 13 +i_0_0_60/S->Z MUX2_X2_LVT* rf 1161.7 66.4 66.4 0.0 10.2 11.1 66.7 3 +theMem/i_0_0_11/B2->ZN AOI22_X4_LVT* fr 1209.5 47.8 47.8 0.0 10.2 0.7 23.4 1 +theMem/i_0_0_10/A->ZN INV_X8_LVT rf 1211.5 2.0 2.0 0.0 10.2 0.8 1.8 1 +theMem/mem_addr_reg[5]/D SDFF_X1_LVT f 1211.5 0.0 0.0 0.5 +-------------------------------------------------------------------------------------------------------------------------------------- +Report for group I2R +Report for group I2O +Report for group R2O +-------------------------------------------------------------------------------------------------------------------------------------- +Startpoint: theMem/IRData_reg[18]/Q + (Clocked by clk_25mhz R) +Endpoint: led[7] + (Clocked by clk_25mhz R) +Path Group: R2O +Data required time: 37500.0 + (Clock shift: 40000.0, minus Uncertainty: 500.0, plus Latency 0.0, minus Out delay: 2000.0) +Data arrival time: 1161.7 +Slack: 36338.3 +Logic depth: 44 +-------------------------------------------------------------------------------------------------------------------------------------- + Arrival Arc Net Net Total fan- +Path Module/Cell Edge Time Delay Delay Delay Slew Load Load out Location + (ps) (ps) (ps) (ps) (ps) (ff) (ff) (#) (um,um) +-------------------------------------------------------------------------------------------------------------------------------------- +clk_25mhz {create_clock} r 0.0 0.0 0.0 0.0 0.0 100 +theMem/IRData_reg[18]/CK->Q + SDFF_X1_LVT* rr 84.9 84.9 84.9 0.0 100.0 10.6 73.4 11 +theRegisters/i_1_0_1371/A->ZN + INV_X8_LVT rf 87.6 2.7 2.7 0.0 10.2 2.1 13.2 3 +theRegisters/i_1_0_1339/A2->ZN + NAND3_X4_LVT fr 101.6 14.0 14.0 0.0 1.0 2.5 17.5 4 +theRegisters/i_1_0_1321/A2->ZN + NOR2_X4_LVT* rf 120.6 19.0 19.0 0.0 12.1 29.7 130.1 32 +theRegisters/i_1_0_722/B1->ZN + AOI22_X4_LVT* fr 164.9 44.3 44.3 0.0 10.2 0.7 23.4 1 +theRegisters/i_1_0_721/A->ZN + INV_X8_LVT rf 167.0 2.1 2.1 0.0 10.2 0.8 3.0 1 +theRegisters/i_1_0_718/A->ZN + AOI221_X2_LVT fr 224.3 57.3 57.3 0.0 0.6 0.9 4.4 1 +theRegisters/i_1_0_716/A3->ZN + NAND4_X4_LVT rf 239.7 15.4 15.4 0.0 34.6 0.9 3.1 1 +theRegisters/i_1_0_715/A->ZN + AOI221_X2_LVT fr 297.1 57.4 57.4 0.0 6.8 0.9 4.3 1 +theRegisters/i_1_0_704/A2->ZN + NAND4_X4_LVT rf 317.6 20.5 20.5 0.0 34.4 5.9 16.7 3 +theDecoder/i_0_133/C2->ZN + AOI222_X4_LVT fr 428.0 110.5 110.5 0.0 12.2 0.8 23.5 1 +theDecoder/i_0_132/A->ZN INV_X32_LVT rf 431.2 3.1 3.1 0.0 10.9 5.4 65.3 7 +theDecoder/theALU/i_0_706/B1->ZN + OAI22_X4_LVT* fr 474.4 43.2 43.2 0.0 1.4 1.5 25.9 2 +theDecoder/theALU/i_0_705/A->ZN + INV_X8_LVT rf 476.5 2.2 2.2 0.0 10.2 0.6 4.2 1 +theDecoder/theALU/i_0_42/A->ZN + OAI21_X2_LVT fr 485.6 9.1 9.1 0.0 0.6 0.8 2.5 1 +theDecoder/theALU/i_0_40/C1->ZN + AOI211_X2_LVT rf 491.3 5.6 5.6 0.0 11.6 0.8 2.9 1 +theDecoder/theALU/i_0_39/B->ZN + AOI211_X2_LVT fr 538.7 47.4 47.4 0.0 3.3 0.9 3.0 1 +theDecoder/theALU/i_0_38/B2->ZN + OAI222_X2_LVT rf 555.6 16.9 16.9 0.0 27.7 0.9 2.9 1 +theDecoder/theALU/i_0_37/C2->ZN + AOI221_X2_LVT fr 599.5 43.8 43.8 0.0 8.4 0.9 4.2 1 +theDecoder/theALU/i_0_35/B1->ZN + OAI22_X4_LVT* rf 613.4 13.9 13.9 0.0 34.0 0.7 23.4 1 +theDecoder/theALU/i_0_34/A->ZN + INV_X8_LVT fr 617.9 4.5 4.5 0.0 10.2 0.6 4.1 1 +theDecoder/theALU/i_0_33/A->ZN + AOI21_X4_LVT rf 620.5 2.6 2.6 0.0 2.4 0.8 3.0 1 +theDecoder/theALU/i_0_32/C2->ZN + OAI222_X2_LVT fr 659.0 38.5 38.5 0.0 2.6 0.9 3.3 1 +theDecoder/theALU/i_0_31/A->ZN + OAI221_X2_LVT rf 675.0 16.0 16.0 0.0 29.2 0.8 4.0 1 +theDecoder/theALU/i_0_28/B1->ZN + AOI21_X4_LVT fr 690.5 15.5 15.5 0.0 8.2 0.8 3.0 1 +theDecoder/theALU/i_0_27/A->ZN + AOI221_X2_LVT rf 694.7 4.2 4.2 0.0 13.5 0.9 2.9 1 +theDecoder/theALU/i_0_26/B->ZN + AOI211_X2_LVT fr 746.9 52.2 52.2 0.0 5.3 0.8 4.6 1 +theDecoder/theALU/i_0_25/B2->ZN + OAI22_X2_LVT rf 756.6 9.7 9.7 0.0 31.8 0.8 2.7 1 +theDecoder/theALU/i_0_24/C2->ZN + AOI211_X2_LVT fr 791.0 34.4 34.4 0.0 4.0 0.9 3.1 1 +theDecoder/theALU/i_0_23/A->ZN + AOI221_X2_LVT rf 796.7 5.8 5.8 0.0 27.8 0.9 3.1 1 +theDecoder/theALU/i_0_22/A->ZN + AOI221_X2_LVT fr 850.4 53.7 53.7 0.0 5.4 0.9 3.1 1 +theDecoder/theALU/i_0_21/A->ZN + AOI221_X2_LVT rf 856.5 6.1 6.1 0.0 31.2 0.9 3.1 1 +theDecoder/theALU/i_0_20/C2->ZN + OAI222_X2_LVT fr 895.2 38.8 38.8 0.0 5.4 0.9 3.3 1 +theDecoder/theALU/i_0_19/A->ZN + OAI221_X2_LVT rf 911.8 16.6 16.6 0.0 29.2 0.9 4.7 1 +theDecoder/theALU/i_0_18/B2->ZN + AOI22_X4_LVT fr 942.1 30.3 30.3 0.0 8.6 0.8 4.4 1 +theDecoder/theALU/i_0_17/B2->ZN + OAI21_X4_LVT rf 948.5 6.4 6.4 0.0 16.9 0.7 4.3 1 +theDecoder/theALU/i_0_16/A->ZN + OAI21_X4_LVT fr 958.3 9.8 9.8 0.0 3.6 0.7 3.9 1 +theDecoder/theALU/i_0_13/B1->ZN + AOI21_X4_LVT rf 963.5 5.3 5.3 0.0 12.5 0.8 4.4 1 +theDecoder/theALU/i_0_12/A4->ZN + NOR4_X2_LVT fr 1020.0 56.5 56.5 0.0 2.9 0.8 2.8 1 +theDecoder/theALU/i_0_0/A3->ZN + OR3_X4_LVT rr 1036.6 16.6 16.6 0.0 29.1 0.7 14.7 2 +theDecoder/i_0_114/B->ZN XNOR2_X2_LVT rf 1043.2 6.5 6.5 0.0 7.8 0.7 4.3 1 +theDecoder/i_0_113/B1->ZN + AOI22_X4_LVT fr 1069.7 26.5 26.5 0.0 5.1 0.8 4.4 1 +theDecoder/i_0_111/A2->ZN + AOI22_X4_LVT rf 1076.1 6.4 6.4 0.0 16.9 0.7 4.3 1 +theDecoder/i_0_110/A2->ZN + NAND2_X4_LVT* fr 1095.3 19.2 19.2 0.0 4.4 9.0 37.6 13 +i_0_0_60/S->Z MUX2_X2_LVT* rf 1161.7 66.4 66.4 0.0 10.2 11.1 66.7 3 +led[7] f 1161.7 0.0 0.0 10.2 +-------------------------------------------------------------------------------------------------------------------------------------- +> report_path_groups +Report Path Groups: +-----+-------+------+---------+--------- + | Path |Weight|Critical |Worst + | Group | |Range(ps)|Slack(ps) +-----+-------+------+---------+--------- +1 |default| 1.000| 0.0| 18015.8 +2 |I2R | 1.000| 0.0| +3 |I2O | 1.000| 0.0| +4 |R2O | 1.000| 0.0| 36338.3 +-----+-------+------+---------+--------- + +------------------------------------- + +Synthesis and optimization complete + +------------------------------------- + +INFO::Running oasys Tessent DFT flow +> source scripts_risc_v/oasys_tessent_dft.tcl +INFO::using /applications/SiemensEDA/siemenseda2023/tessent/bin/tessent build to run the Tessent DFT flow +> config_tessent -exec_path /applications/SiemensEDA/siemenseda2023/tessent/bin/tessent +> define_test_clock -pin clk_25mhz +> define_test_pin -pin scan_en -scan_mode 1 -default_scan_enable -create_port +Adding Test pin scan_en to top Module +> set_dont_scan theMem true +> define_test_pin -name reset -pin {btn[0]} -scan_mode 1 +> check_dft -auto_test_clock -auto_test_pins +starting check_dft at 00:00:16(cpu)/0:01:35(wall) 198MB(vsz)/566MB(peak) +Checking DFT rules for 'cpu' + Running DFT TDRC iteration 1 + Total 1131 scanModels/flops with 12% scanable (139 pass, 992 fail, 0 nonScan or excludeScan) +Report Check DFT: +-----+---------------------+------+--------+------+------------------------------------------- + |Item |Errors|Warnings|Status|Description +-----+---------------------+------+--------+------+------------------------------------------- +1 |internal_clock | 0| 0|Passed|Internal Clock +2 |constant_clock | 0| 0|Passed|Constant Clock +3 |non_clock_PI | 0| 0|Passed|Non-Clock PI +4 |blocking_clock_gate | 0| 31|Failed|Blocking clock gate +5 |internal_async | 0| 0|Passed|Internal Async. Set/Reset control +6 |constant_active_async| 0| 0|Passed|Constant active Async. Set/Reset signal +7 |non_test_PI | 0| 0|Passed|Unconstrained PI driving Async/ Set/Reset +8 |async_clock_conflict | 0| 0|Passed|Async. Set/Reset signal and Clock conflict +9 |parallel_scan_clock | 0| 0|Passed|Clock pin of unsupported parallel-scan flop +-----+---------------------+------+--------+------+------------------------------------------- +Design has 31 DFT violation(s) +finished check_dft at 00:00:17(cpu)/0:01:35(wall) 198MB(vsz)/566MB(peak) +> write_db ./output/odb/riscv.tessent_pre_fix.odb +> fix_dft_violations -type all -test_clock clk_25mhz -test_control scan_en +Created 0 gates to fix Async violation(s) +Created 0 muxes to fix clock violation(s) +Replaced 31 clock-gating cells to fix clock-gating violation(s) +> report_dft_violations +Report DftViolations: +-----+-------------------+-----------------------------------------------+-------------------- + | Type | Pin | Affected Registers +-----+-------------------+-----------------------------------------------+-------------------- +1 |blocking clock gate|theRegisters/clk_gate_registers_reg[1]_reg/GCK | 32 +2 |blocking clock gate|theRegisters/clk_gate_registers_reg[2]_reg/GCK | 32 +3 |blocking clock gate|theRegisters/clk_gate_registers_reg[3]_reg/GCK | 32 +4 |blocking clock gate|theRegisters/clk_gate_registers_reg[4]_reg/GCK | 32 +5 |blocking clock gate|theRegisters/clk_gate_registers_reg[5]_reg/GCK | 32 +6 |blocking clock gate|theRegisters/clk_gate_registers_reg[6]_reg/GCK | 32 +7 |blocking clock gate|theRegisters/clk_gate_registers_reg[7]_reg/GCK | 32 +8 |blocking clock gate|theRegisters/clk_gate_registers_reg[8]_reg/GCK | 32 +9 |blocking clock gate|theRegisters/clk_gate_registers_reg[9]_reg/GCK | 32 +10 |blocking clock gate|theRegisters/clk_gate_registers_reg[10]_reg/GCK| 32 +11 |blocking clock gate|theRegisters/clk_gate_registers_reg[11]_reg/GCK| 32 +12 |blocking clock gate|theRegisters/clk_gate_registers_reg[12]_reg/GCK| 32 +13 |blocking clock gate|theRegisters/clk_gate_registers_reg[13]_reg/GCK| 32 +14 |blocking clock gate|theRegisters/clk_gate_registers_reg[14]_reg/GCK| 32 +15 |blocking clock gate|theRegisters/clk_gate_registers_reg[15]_reg/GCK| 32 +16 |blocking clock gate|theRegisters/clk_gate_registers_reg[16]_reg/GCK| 32 +17 |blocking clock gate|theRegisters/clk_gate_registers_reg[17]_reg/GCK| 32 +18 |blocking clock gate|theRegisters/clk_gate_registers_reg[18]_reg/GCK| 32 +19 |blocking clock gate|theRegisters/clk_gate_registers_reg[19]_reg/GCK| 32 +20 |blocking clock gate|theRegisters/clk_gate_registers_reg[20]_reg/GCK| 32 +21 |blocking clock gate|theRegisters/clk_gate_registers_reg[21]_reg/GCK| 32 +22 |blocking clock gate|theRegisters/clk_gate_registers_reg[22]_reg/GCK| 32 +23 |blocking clock gate|theRegisters/clk_gate_registers_reg[23]_reg/GCK| 32 +24 |blocking clock gate|theRegisters/clk_gate_registers_reg[24]_reg/GCK| 32 +25 |blocking clock gate|theRegisters/clk_gate_registers_reg[25]_reg/GCK| 32 +26 |blocking clock gate|theRegisters/clk_gate_registers_reg[26]_reg/GCK| 32 +27 |blocking clock gate|theRegisters/clk_gate_registers_reg[27]_reg/GCK| 32 +28 |blocking clock gate|theRegisters/clk_gate_registers_reg[28]_reg/GCK| 32 +29 |blocking clock gate|theRegisters/clk_gate_registers_reg[29]_reg/GCK| 32 +30 |blocking clock gate|theRegisters/clk_gate_registers_reg[30]_reg/GCK| 32 +31 |blocking clock gate|theRegisters/clk_gate_registers_reg[31]_reg/GCK| 32 +-----+-------------------+-----------------------------------------------+-------------------- +> optimize +starting optimize at 00:00:17(cpu)/0:01:36(wall) 198MB(vsz)/566MB(peak) +info: mapped 107 flop(s) to scan cells, excluded 107 is_dont_scan flop(s) and 0 is_dont_touch flop(s) +info: Target library/cell information has changed that further may change timing results. [TA-159] +info: optimizing design 'cpu' - propagating constants +info: optimized '' area changed 0.0squm (x1), total 11274.7squm (#1, 0 secs) +info: set slack mode to optimize shift +info: resetting all path groups +info: activated path group default @ 18139.2ps +info: suspended path group I2R @ ps +info: suspended path group I2O @ ps +info: activated path group R2O @ 36317.8ps +info: finished path group default @ 18139.2ps +info: finished path group R2O @ 36317.8ps +info: reactivating path groups +info: reactivated path group default @ 18139.2ps +info: reactivated path group R2O @ 36317.8ps +info: finished path group default @ 18139.2ps +info: finished path group R2O @ 36317.8ps +info: set slack mode to normal +info: done with all path groups +info: restore all path groups +info: starting area recovery on module cpu +info: optimized 'cpu__GC0' area recovered 0.00squm (x1), total 0.00squm (1#5), 0.04 secs +info: optimized 'main_mem__GC0' area recovered 0.00squm (x1), total 0.00squm (2#5), 0.04 secs +info: optimized 'MemGen_32_11__block' area recovered 0.00squm (x1), total 0.00squm (3#5), 0.00 secs +info: optimized 'reg_file__always' area recovered 0.00squm (x1), total 0.00squm (4#5), 0.01 secs +info: optimized 'reg_file__GB1' area recovered 0.00squm (x1), total 0.00squm (5#5), 0.02 secs +info: area recovery done, total area reduction: 0.00squm (0.00%), final slack: 18139.2ps (delta: 0.0ps) (0 secs) +done optimizing virtual at 00:00:18(cpu)/0:01:37(wall) 203MB(vsz)/566MB(peak) +info: floorplan : total 4 movable macros and 0 fixed macros +info: creating tracks for 10 routing layers [FP-148] +info: start floorplan stage 0 [FP-145] +info: end floorplan stage 0 [FP-145] +info: start floorplan stage 1 [FP-145] +info: end floorplan stage 1 [FP-145] +info: start rtl partition placement [PLACE-114] +info: placement mode : raw [PLACE-115] +info: set slack mode to weight modified +info: set slack mode to normal +info: set slack mode to optimize shift +info: timing-driven placement : ON [PLACE-116] +info: congestion-driven placement : ON [PLACE-117] +info: placement movable objects : macros 0 , rtl partitions 5, cells 0 [PLACE-118] +info: start placement stage 0 [PLACE-111] +info: end placement stage 0 [PLACE-111] +info: set slack mode to normal +info: cell density map (bin size 20 x 20 rows), maximum utilization: 170.00% average utilization: 13.98% [PLACE-153] +info: 9.00% bins with overflow, average overflow 18.49% [PLACE-154] +info: P-D: 0.090% (0.185 ~ 0.700) +Total Wire Length = 77698.10 +Average Wire = 58.60 +Longest Wire = 352.69 +Shortest Wire = 0.00 +WNS = 18139.5ps +info: placing 17 unplaced IO Pins +info: start rtl partition placement [PLACE-114] +info: placement mode : raw [PLACE-115] +info: set slack mode to weight modified +info: set slack mode to normal +info: set slack mode to optimize shift +info: timing-driven placement : ON [PLACE-116] +info: congestion-driven placement : ON [PLACE-117] +info: placement movable objects : macros 0 , rtl partitions 5, cells 0 [PLACE-118] +info: start placement stage 0 [PLACE-111] +info: end placement stage 0 [PLACE-111] +info: set slack mode to normal +info: cell density map (bin size 20 x 20 rows), maximum utilization: 90.53% average utilization: 14.23% [PLACE-153] +info: 0.00% bins with overflow, average overflow 0.00% [PLACE-154] +info: P-D: 0.000% (0.000 ~ 0.000) +Total Wire Length = 115431.45 +Average Wire = 87.05 +Longest Wire = 426.66 +Shortest Wire = 10.50 +WNS = 18131.2ps +info: 0 power/ground pre-route segments processed. [PLACE-144] +info: 0 routing blockages processed. [PLACE-145] +info: replaced @ 18131.2ps +done optimize placement at 00:00:21(cpu)/0:01:39(wall) 404MB(vsz)/822MB(peak) +info: cell density map (bin size 20 x 20 rows), maximum utilization: 90.53% average utilization: 14.23% [PLACE-153] +info: 0.00% bins with overflow, average overflow 0.00% [PLACE-154] +info: set slack mode to optimize shift +info: resetting all path groups +info: activated path group default @ 18131.2ps +info: suspended path group I2R @ ps +info: suspended path group I2O @ ps +info: activated path group R2O @ 36309.8ps +info: finished path group default @ 18131.2ps +info: finished path group R2O @ 36309.8ps +info: reactivating path groups +info: reactivated path group default @ 18131.2ps +info: reactivated path group R2O @ 36309.8ps +info: finished path group default @ 18131.2ps +info: finished path group R2O @ 36309.8ps +info: cell density map (bin size 20 x 20 rows), maximum utilization: 90.53% average utilization: 14.23% [PLACE-153] +info: 0.00% bins with overflow, average overflow 0.00% [PLACE-154] +info: 0 power/ground pre-route segments processed. [PLACE-144] +info: 0 routing blockages processed. [PLACE-145] +info: set slack mode to normal +info: done with all path groups +info: restore all path groups +info: (0) optimizing 'theMem/i_0/IAddr[5]' (path group default) @ 18131.2ps(1/1) (4 secs) +finished optimize at 00:00:21(cpu)/0:01:39(wall) 404MB(vsz)/822MB(peak) +> write_db ./output/odb/riscv.tessent_post_fix.odb +> write_verilog ./output/riscv.tessent_post_fix.v +info: writing Verilog file './output/riscv.tessent_post_fix.v' for module 'cpu' [WRITE-100] +> config_tessent -library {./libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib ./libs/fastscan/NangateOpenCellLibrary_low_temp_ccs.fslib ./libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib ./libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib ./libs/fastscan/LowPowerOpenCellLibrary_low_temp_ccs.fslib ./libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib ./libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.fslib ./libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib ./libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib ./libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib ./libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib ./libs/fastscan/PLL.fslib ./libs/fastscan/IO.fslib} + +--------------check dft--------------- +> check_dft +starting check_dft at 00:00:22(cpu)/0:01:40(wall) 395MB(vsz)/822MB(peak) +Checking DFT rules for 'cpu' + Running DFT TDRC iteration 1 + Total 1131 scanModels/flops with 90% scanable (1024 pass, 0 fail, 107 nonScan or excludeScan) +Report Check DFT: +-----+---------------------+------+--------+------+------------------------------------------- + |Item |Errors|Warnings|Status|Description +-----+---------------------+------+--------+------+------------------------------------------- +1 |internal_clock | 0| 0|Passed|Internal Clock +2 |constant_clock | 0| 0|Passed|Constant Clock +3 |non_clock_PI | 0| 0|Passed|Non-Clock PI +4 |blocking_clock_gate | 0| 0|Passed|Blocking clock gate +5 |internal_async | 0| 0|Passed|Internal Async. Set/Reset control +6 |constant_active_async| 0| 0|Passed|Constant active Async. Set/Reset signal +7 |non_test_PI | 0| 0|Passed|Unconstrained PI driving Async/ Set/Reset +8 |async_clock_conflict | 0| 0|Passed|Async. Set/Reset signal and Clock conflict +9 |parallel_scan_clock | 0| 0|Passed|Clock pin of unsupported parallel-scan flop +-----+---------------------+------+--------+------+------------------------------------------- +Design has 0 DFT violation(s) +finished check_dft at 00:00:22(cpu)/0:01:40(wall) 395MB(vsz)/822MB(peak) + +--------------define Scan-Chains--------------- +> define_scan_chain -scan_in SI_1 -scan_out SO_1 -create_port +Defining Scan Chain scanChain_1( si:SI_1, so:SO_1) +Adding Scan-in pin SI_1 to top Module +Adding Scan-out pin SO_1 to top Module +> define_scan_chain -scan_in SI_2 -scan_out SO_2 -create_port +Defining Scan Chain scanChain_2( si:SI_2, so:SO_2) +Adding Scan-in pin SI_2 to top Module +Adding Scan-out pin SO_2 to top Module +> define_scan_chain -scan_in SI_3 -scan_out SO_3 -create_port +Defining Scan Chain scanChain_3( si:SI_3, so:SO_3) +Adding Scan-in pin SI_3 to top Module +Adding Scan-out pin SO_3 to top Module +> define_scan_chain -scan_in SI_4 -scan_out SO_4 -create_port +Defining Scan Chain scanChain_4( si:SI_4, so:SO_4) +Adding Scan-in pin SI_4 to top Module +Adding Scan-out pin SO_4 to top Module + +----------run_tessent_scan---------------- +> run_tessent_scan +info: writing Verilog file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/Scan_0/oasys_netlist.v' for module 'cpu' [WRITE-100] +starting check_dft at 00:00:22(cpu)/0:01:40(wall) 395MB(vsz)/822MB(peak) +Checking DFT rules for 'cpu' + Running DFT TDRC iteration 1 + Total 1131 scanModels/flops with 90% scanable (1024 pass, 0 fail, 107 nonScan or excludeScan) +Report Check DFT: +-----+---------------------+------+--------+------+------------------------------------------- + |Item |Errors|Warnings|Status|Description +-----+---------------------+------+--------+------+------------------------------------------- +1 |internal_clock | 0| 0|Passed|Internal Clock +2 |constant_clock | 0| 0|Passed|Constant Clock +3 |non_clock_PI | 0| 0|Passed|Non-Clock PI +4 |blocking_clock_gate | 0| 0|Passed|Blocking clock gate +5 |internal_async | 0| 0|Passed|Internal Async. Set/Reset control +6 |constant_active_async| 0| 0|Passed|Constant active Async. Set/Reset signal +7 |non_test_PI | 0| 0|Passed|Unconstrained PI driving Async/ Set/Reset +8 |async_clock_conflict | 0| 0|Passed|Async. Set/Reset signal and Clock conflict +9 |parallel_scan_clock | 0| 0|Passed|Clock pin of unsupported parallel-scan flop +-----+---------------------+------+--------+------+------------------------------------------- +Design has 0 DFT violation(s) +finished check_dft at 00:00:22(cpu)/0:01:40(wall) 395MB(vsz)/822MB(peak) + Configuring 4 scan chain(s) + Configuring DEFAULT DFT partition + Enabling physical aware scan chains + Configuring 4 scan chain(s) for 1024 scan instance(s) in 1 test clock domain(s) + Domain clk_25mhz has 1024 flop(s) (1024 rise, 0 fall), 4 chain(s) (4,0) + Assigning chain scanChain_1 to domain clk_25mhz (edge: rise) (capacity: 256) + Assigning chain scanChain_2 to domain clk_25mhz (edge: rise) (capacity: 256) + Assigning chain scanChain_3 to domain clk_25mhz (edge: rise) (capacity: 256) + Assigning chain scanChain_4 to domain clk_25mhz (edge: rise) (capacity: 256) +info: writing Sdc file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/Scan_0/oasys.sdc' for design 'cpu' [WRITE-104] +info: Parameter 'tessentScandefFilePath' set to '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/Scan_0/cpu.scandef' [PARAM-104] + +************************************************************************************************************************************************************************************** + TESSENT EXECUTION BEGINS + Invoking Tessent Executable : /applications/SiemensEDA/siemenseda2023/tessent_2023.4-p1/bin/tessent + DoFile : /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/Scan_0/scan.do +************************************************************************************************************************************************************************************** + +/applications/SiemensEDA/siemenseda2023/tessent_2023.4-p1/bin/tessent -shell -dofile /tmp/oasys.2483642/.tmpTessentFile -log_file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/Scan_0/scan.log -replace +// Tessent Shell 2023.4-p1 Mon Feb 19 16:22:02 GMT 2024 +// Unpublished work. Copyright 2024 Siemens +// +// This material contains trade secrets or otherwise confidential +// information owned by Siemens Industry Software Inc. or its affiliates +// (collectively, "SISW"), or its licensors. Access to and use of this +// information is strictly limited as set forth in the Customer's +// applicable agreements with SISW. +// +// Siemens software executing under x86-64 Linux on Thu May 28 17:28:57 CEST 2026. +// 64 bit version +// Host: efiapps0.ads1.fh-nuernberg.de (12 x 3.5 GHz, 48014 MB RAM, 24575 MB Swap) +// +// command: if {[catch {source /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/Scan_0/scan.do} msg]} { +// puts "$msg" +// puts "TESSENT_ER_ORTL" } +// sub-command: set_context dft -scan -no_rtl -design_id Scan_0 +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_low_temp_ccs.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_low_temp_ccs.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_low_temp_ccs.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_low_temp_ccs.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_low_temp_ccs.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_low_temp_ccs.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/PLL.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/PLL.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/PLL.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/IO.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/IO.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/IO.fslib +// sub-command: set_module_matching_options -suffix_pattern_list {[_]+[0-9]+[_]+[0-9]+} -regexp -append +// sub-command: set_module_matching_options -suffix_pattern_list {[_]+[A-Z]+} -regexp -append +// sub-command: set_module_matching_options -suffix_pattern_list {[_]+[0-9]+[_]+[0-9]+[_]+[A-Z]+} -regexp -append +// sub-command: read_verilog /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/Scan_0/oasys_netlist.v +// sub-command: set_tsdb_output_directory /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/tsdb_outdir +// sub-command: read_sdc /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/Scan_0/oasys.sdc +// Command 'read_sdc' requires an elaborated design. Automatically elaborating the design ... +// Note: 640 duplicate cell library models were read. The last model read of the same name was kept. +// To see detailed messages per duplicate model, issue 'set_cell_library_options -report_duplicate_models on' +// before issuing 'read_cell_library'. +// Warning: 1 cell library model contained 2 floating model outputs. +// To see detailed messages per model, issue 'set_cell_library_options -report_floating_nets on' +// before issuing 'read_cell_library'. +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X1' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X2' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X4' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X8' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X1_HVT' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X2_HVT' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X4_HVT' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X8_HVT' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X1_SVT' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X2_SVT' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X4_SVT' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X8_SVT' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X1_LVT' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X2_LVT' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X4_LVT' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X8_LVT' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' +// Note: Top design is 'cpu'. +// Warning: Undefined modules were found. +// Before using "set_system_mode" or "create_flat_model", you must either define +// the missing modules using "read_verilog" and/or "read_cell_library", or use the +// following command to treat them as black boxes: + add_black_boxes -modules { \ + MemGen_16_10 \ + } +// You can also use "add_black_boxes -auto" to black box all undefined modules but +// it is recommended that you do not add this command to your dofile. Doing so may +// unintentionally black-box new undefined modules in future runs. +// Warning: 32 cases: Unused net in DFT library model +// Warning: 110 cases: Undriven net in netlist module +// Warning: 1 case: Floating input on instance in netlist +// Warning: 47 cases: Net in netlist not connected +// Note: Issue set_current_design with the -show_elaboration_warnings option to see more details about previous warnings +// Design elaboration successful. +// Reading SDC file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/Scan_0/oasys.sdc ... +// Finished reading SDC file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/Scan_0/oasys.sdc. +// Read SDC summary: 1 false path, 0 multi-cycle paths, 0 erroneous paths +// 0 disable timings, 0 case analysis, 0 clock groups +// sub-command: set_current_design cpu -show_elaboration_warnings +// Warning: Undefined modules were found. +// Before using "set_system_mode" or "create_flat_model", you must either define +// the missing modules using "read_verilog" and/or "read_cell_library", or use the +// following command to treat them as black boxes: + add_black_boxes -modules { \ + MemGen_16_10 \ + } +// You can also use "add_black_boxes -auto" to black box all undefined modules but +// it is recommended that you do not add this command to your dofile. Doing so may +// unintentionally black-box new undefined modules in future runs. +// Warning: Net 'SO_1' in module 'cpu' is not driven +// Warning: Net 'SO_2' in module 'cpu' is not driven +// Warning: Net 'SO_3' in module 'cpu' is not driven +// Warning: Net 'SO_4' in module 'cpu' is not driven +// Warning: Net 'DAddr[31]' in module 'cpu' has no pins +// Warning: Net 'DAddr[30]' in module 'cpu' has no pins +// Warning: Net 'DAddr[29]' in module 'cpu' has no pins +// Warning: Net 'DAddr[28]' in module 'cpu' has no pins +// Warning: Net 'DAddr[27]' in module 'cpu' has no pins +// Warning: Net 'DAddr[26]' in module 'cpu' has no pins +// Warning: Net 'DAddr[25]' in module 'cpu' has no pins +// Warning: Net 'DAddr[24]' in module 'cpu' has no pins +// Warning: Net 'DAddr[23]' in module 'cpu' has no pins +// Warning: Net 'DAddr[22]' in module 'cpu' has no pins +// Warning: Net 'DAddr[21]' in module 'cpu' has no pins +// Warning: Net 'DAddr[20]' in module 'cpu' has no pins +// Warning: Net 'DAddr[19]' in module 'cpu' has no pins +// Warning: Net 'DAddr[18]' in module 'cpu' has no pins +// Warning: Net 'DAddr[17]' in module 'cpu' has no pins +// Warning: Net 'DAddr[16]' in module 'cpu' has no pins +// Warning: Net 'DAddr[15]' in module 'cpu' has no pins +// Warning: Net 'DAddr[14]' in module 'cpu' has no pins +// Warning: Net 'DAddr[13]' in module 'cpu' has no pins +// Warning: Net 'NextPC[31]' in module 'cpu' has no pins +// Warning: Net 'NextPC[30]' in module 'cpu' has no pins +// Warning: Net 'NextPC[29]' in module 'cpu' has no pins +// Warning: Net 'NextPC[28]' in module 'cpu' has no pins +// Warning: Net 'NextPC[27]' in module 'cpu' has no pins +// Warning: Net 'NextPC[26]' in module 'cpu' has no pins +// Warning: Net 'NextPC[25]' in module 'cpu' has no pins +// Warning: Net 'NextPC[24]' in module 'cpu' has no pins +// Warning: Net 'NextPC[23]' in module 'cpu' has no pins +// Warning: Net 'NextPC[22]' in module 'cpu' has no pins +// Warning: Net 'NextPC[21]' in module 'cpu' has no pins +// Warning: Net 'NextPC[20]' in module 'cpu' has no pins +// Warning: Net 'NextPC[19]' in module 'cpu' has no pins +// Warning: Net 'NextPC[18]' in module 'cpu' has no pins +// Warning: Net 'NextPC[17]' in module 'cpu' has no pins +// Warning: Net 'NextPC[16]' in module 'cpu' has no pins +// Warning: Net 'NextPC[15]' in module 'cpu' has no pins +// Warning: Net 'NextPC[14]' in module 'cpu' has no pins +// Warning: Net 'NextPC[13]' in module 'cpu' has no pins +// Warning: Net 'NextPC[7]' in module 'cpu' has no pins +// Warning: Net 'NextPC[6]' in module 'cpu' has no pins +// Warning: Net 'NextPC[5]' in module 'cpu' has no pins +// Warning: Net 'NextPC[4]' in module 'cpu' has no pins +// Warning: Net 'NextPC[3]' in module 'cpu' has no pins +// Warning: Net 'NextPC[2]' in module 'cpu' has no pins +// Warning: Net 'NextPC[1]' in module 'cpu' has no pins +// Warning: Net 'NextPC[0]' in module 'cpu' has no pins +// Warning: Net 'uc_0' in module 'cpu' is not driven +// Warning: Net 'uc_1' in module 'cpu' is not driven +// Warning: Net 'uc_2' in module 'cpu' is not driven +// Warning: Net 'uc_3' in module 'cpu' is not driven +// Warning: Net 'uc_4' in module 'cpu' is not driven +// Warning: Net 'uc_5' in module 'cpu' is not driven +// Warning: Net 'uc_6' in module 'cpu' is not driven +// Warning: Net 'uc_7' in module 'cpu' is not driven +// Warning: Net 'uc_8' in module 'cpu' is not driven +// Warning: Net 'uc_9' in module 'cpu' is not driven +// Warning: Net 'uc_10' in module 'cpu' is not driven +// Warning: Net 'uc_11' in module 'cpu' is not driven +// Warning: Net 'uc_12' in module 'cpu' is not driven +// Warning: Net 'uc_13' in module 'cpu' is not driven +// Warning: Net 'uc_14' in module 'cpu' is not driven +// Warning: Net 'uc_15' in module 'cpu' is not driven +// Warning: Net 'uc_16' in module 'cpu' is not driven +// Warning: Net 'uc_17' in module 'cpu' is not driven +// Warning: Net 'uc_18' in module 'cpu' is not driven +// Warning: Net 'uc_19' in module 'cpu' is not driven +// Warning: Net 'uc_20' in module 'cpu' is not driven +// Warning: Net 'uc_21' in module 'cpu' is not driven +// Warning: Net 'uc_22' in module 'cpu' is not driven +// Warning: Net 'uc_23' in module 'cpu' is not driven +// Warning: Net 'uc_24' in module 'cpu' is not driven +// Warning: Net 'uc_25' in module 'cpu' is not driven +// Warning: Net 'uc_26' in module 'cpu' is not driven +// Warning: Net 'uc_27' in module 'cpu' is not driven +// Warning: Net 'uc_28' in module 'cpu' is not driven +// Warning: Net 'uc_29' in module 'cpu' is not driven +// Warning: Net 'uc_30' in module 'cpu' is not driven +// Warning: Net 'uc_31' in module 'cpu' is not driven +// Warning: Net 'uc_32' in module 'cpu' is not driven +// Warning: Net 'uc_33' in module 'cpu' is not driven +// Warning: Net 'uc_34' in module 'cpu' is not driven +// Warning: Net 'uc_35' in module 'cpu' is not driven +// Warning: Net 'uc_36' in module 'cpu' is not driven +// Warning: Net 'uc_37' in module 'cpu' is not driven +// Warning: Net 'uc_38' in module 'cpu' is not driven +// Warning: Net 'uc_39' in module 'cpu' is not driven +// Warning: Floating input 'chip_en' at instance 'RAM' in module 'main_mem' +// Warning: Net 'mem_sel[1]' in module 'MemGen_32_11' has no pins +// Warning: Net 'DAddr[31]' in module 'decoder' is not driven +// Warning: Net 'DAddr[30]' in module 'decoder' is not driven +// Warning: Net 'DAddr[29]' in module 'decoder' is not driven +// Warning: Net 'DAddr[28]' in module 'decoder' is not driven +// Warning: Net 'DAddr[27]' in module 'decoder' is not driven +// Warning: Net 'DAddr[26]' in module 'decoder' is not driven +// Warning: Net 'DAddr[25]' in module 'decoder' is not driven +// Warning: Net 'DAddr[24]' in module 'decoder' is not driven +// Warning: Net 'DAddr[23]' in module 'decoder' is not driven +// Warning: Net 'DAddr[22]' in module 'decoder' is not driven +// Warning: Net 'DAddr[21]' in module 'decoder' is not driven +// Warning: Net 'DAddr[20]' in module 'decoder' is not driven +// Warning: Net 'DAddr[19]' in module 'decoder' is not driven +// Warning: Net 'DAddr[18]' in module 'decoder' is not driven +// Warning: Net 'DAddr[17]' in module 'decoder' is not driven +// Warning: Net 'DAddr[16]' in module 'decoder' is not driven +// Warning: Net 'DAddr[15]' in module 'decoder' is not driven +// Warning: Net 'DAddr[14]' in module 'decoder' is not driven +// Warning: Net 'DAddr[13]' in module 'decoder' is not driven +// Warning: Net 'WData[31]' in module 'decoder' is not driven +// Warning: Net 'WData[30]' in module 'decoder' is not driven +// Warning: Net 'WData[29]' in module 'decoder' is not driven +// Warning: Net 'WData[28]' in module 'decoder' is not driven +// Warning: Net 'WData[27]' in module 'decoder' is not driven +// Warning: Net 'WData[26]' in module 'decoder' is not driven +// Warning: Net 'WData[25]' in module 'decoder' is not driven +// Warning: Net 'WData[24]' in module 'decoder' is not driven +// Warning: Net 'WData[23]' in module 'decoder' is not driven +// Warning: Net 'WData[22]' in module 'decoder' is not driven +// Warning: Net 'WData[21]' in module 'decoder' is not driven +// Warning: Net 'WData[20]' in module 'decoder' is not driven +// Warning: Net 'WData[19]' in module 'decoder' is not driven +// Warning: Net 'WData[18]' in module 'decoder' is not driven +// Warning: Net 'WData[17]' in module 'decoder' is not driven +// Warning: Net 'WData[16]' in module 'decoder' is not driven +// Warning: Net 'WData[15]' in module 'decoder' is not driven +// Warning: Net 'WData[14]' in module 'decoder' is not driven +// Warning: Net 'WData[13]' in module 'decoder' is not driven +// Warning: Net 'WData[12]' in module 'decoder' is not driven +// Warning: Net 'WData[11]' in module 'decoder' is not driven +// Warning: Net 'WData[10]' in module 'decoder' is not driven +// Warning: Net 'WData[9]' in module 'decoder' is not driven +// Warning: Net 'WData[8]' in module 'decoder' is not driven +// Warning: Net 'WData[7]' in module 'decoder' is not driven +// Warning: Net 'WData[6]' in module 'decoder' is not driven +// Warning: Net 'WData[5]' in module 'decoder' is not driven +// Warning: Net 'WData[4]' in module 'decoder' is not driven +// Warning: Net 'WData[3]' in module 'decoder' is not driven +// Warning: Net 'WData[2]' in module 'decoder' is not driven +// Warning: Net 'WData[1]' in module 'decoder' is not driven +// Warning: Net 'WData[0]' in module 'decoder' is not driven +// Warning: Net 'Rs1[4]' in module 'decoder' is not driven +// Warning: Net 'Rs1[3]' in module 'decoder' is not driven +// Warning: Net 'Rs1[2]' in module 'decoder' is not driven +// Warning: Net 'Rs1[1]' in module 'decoder' is not driven +// Warning: Net 'Rs1[0]' in module 'decoder' is not driven +// Warning: Net 'Rs2[4]' in module 'decoder' is not driven +// Warning: Net 'Rs2[3]' in module 'decoder' is not driven +// Warning: Net 'Rs2[2]' in module 'decoder' is not driven +// Warning: Net 'Rs2[1]' in module 'decoder' is not driven +// Warning: Net 'Rs2[0]' in module 'decoder' is not driven +// Warning: Net 'Rd[4]' in module 'decoder' is not driven +// Warning: Net 'Rd[3]' in module 'decoder' is not driven +// Warning: Net 'Rd[2]' in module 'decoder' is not driven +// Warning: Net 'Rd[1]' in module 'decoder' is not driven +// Warning: Net 'Rd[0]' in module 'decoder' is not driven +// sub-command: set_design_level physical_block +// sub-command: set_shift_register_identification off +// sub-command: add_nonscan_instances -instances "{/theMem/\IRData_reg[31] } {/theMem/\IRData_reg[30] } {/theMem/\IRData_reg[29] } {/theMem/\IRData_reg[28] } {/theMem/\IRData_reg[27] } {/theMem/\IRData_reg[26] } {/theMem/\IRData_reg[25] } {/theMem/\IRData_reg[24] } {/theMem/\IRData_reg[23] } {/theMem/\IRData_reg[22] } {/theMem/\IRData_reg[21] } {/theMem/\IRData_reg[20] } {/theMem/\IRData_reg[19] } {/theMem/\IRData_reg[18] } {/theMem/\IRData_reg[17] } {/theMem/\IRData_reg[16] } {/theMem/\IRData_reg[15] } {/theMem/\IRData_reg[14] } {/theMem/\IRData_reg[13] } {/theMem/\IRData_reg[12] } {/theMem/\IRData_reg[11] } {/theMem/\IRData_reg[10] } {/theMem/\IRData_reg[9] } {/theMem/\IRData_reg[8] } {/theMem/\IRData_reg[7] } {/theMem/\IRData_reg[6] } {/theMem/\IRData_reg[5] } {/theMem/\IRData_reg[4] } {/theMem/\IRData_reg[3] } {/theMem/\IRData_reg[2] } {/theMem/\IRData_reg[1] } {/theMem/\IRData_reg[0] } {/theMem/\mem_addr_reg[10] } {/theMem/\mem_addr_reg[9] } {/theMem/\mem_addr_reg[8] } {/theMem/\mem_addr_reg[7] } {/theMem/\mem_addr_reg[6] } {/theMem/\mem_addr_reg[5] } {/theMem/\mem_addr_reg[4] } {/theMem/\mem_addr_reg[3] } {/theMem/\mem_addr_reg[2] } {/theMem/\mem_addr_reg[1] } {/theMem/\mem_addr_reg[0] } {/theMem/\drTmp_reg[31] } {/theMem/\drTmp_reg[30] } {/theMem/\drTmp_reg[29] } {/theMem/\drTmp_reg[28] } {/theMem/\drTmp_reg[27] } {/theMem/\drTmp_reg[26] } {/theMem/\drTmp_reg[25] } {/theMem/\drTmp_reg[24] } {/theMem/\drTmp_reg[23] } {/theMem/\drTmp_reg[22] } {/theMem/\drTmp_reg[21] } {/theMem/\drTmp_reg[20] } {/theMem/\drTmp_reg[19] } {/theMem/\drTmp_reg[18] } {/theMem/\drTmp_reg[17] } {/theMem/\drTmp_reg[16] } {/theMem/\drTmp_reg[15] } {/theMem/\drTmp_reg[14] } {/theMem/\drTmp_reg[13] } {/theMem/\drTmp_reg[12] } {/theMem/\drTmp_reg[11] } {/theMem/\drTmp_reg[10] } {/theMem/\drTmp_reg[9] } {/theMem/\drTmp_reg[8] } {/theMem/\drTmp_reg[7] } {/theMem/\drTmp_reg[6] } {/theMem/\drTmp_reg[5] } {/theMem/\drTmp_reg[4] } {/theMem/\drTmp_reg[3] } {/theMem/\drTmp_reg[2] } {/theMem/\drTmp_reg[1] } {/theMem/\drTmp_reg[0] } {/theMem/\mem_wdata_reg[31] } {/theMem/\mem_wdata_reg[30] } {/theMem/\mem_wdata_reg[29] } {/theMem/\mem_wdata_reg[28] } {/theMem/\mem_wdata_reg[27] } {/theMem/\mem_wdata_reg[26] } {/theMem/\mem_wdata_reg[25] } {/theMem/\mem_wdata_reg[24] } {/theMem/\mem_wdata_reg[23] } {/theMem/\mem_wdata_reg[22] } {/theMem/\mem_wdata_reg[21] } {/theMem/\mem_wdata_reg[20] } {/theMem/\mem_wdata_reg[19] } {/theMem/\mem_wdata_reg[18] } {/theMem/\mem_wdata_reg[17] } {/theMem/\mem_wdata_reg[16] } {/theMem/\mem_wdata_reg[15] } {/theMem/\mem_wdata_reg[14] } {/theMem/\mem_wdata_reg[13] } {/theMem/\mem_wdata_reg[12] } {/theMem/\mem_wdata_reg[11] } {/theMem/\mem_wdata_reg[10] } {/theMem/\mem_wdata_reg[9] } {/theMem/\mem_wdata_reg[8] } {/theMem/\mem_wdata_reg[7] } {/theMem/\mem_wdata_reg[6] } {/theMem/\mem_wdata_reg[5] } {/theMem/\mem_wdata_reg[4] } {/theMem/\mem_wdata_reg[3] } {/theMem/\mem_wdata_reg[2] } {/theMem/\mem_wdata_reg[1] } {/theMem/\mem_wdata_reg[0] } " +// sub-command: add_clocks 0 " clk_25mhz " +// sub-command: set_scan_enable scan_en -active high +// sub-command: add_input_constraints btn[0] -C1 +// sub-command: set_scan_enable scan_en -active high -cluster_name scanChain_1 +// sub-command: set_scan_enable scan_en -active high -cluster_name scanChain_2 +// sub-command: set_scan_enable scan_en -active high -cluster_name scanChain_3 +// sub-command: set_scan_enable scan_en -active high -cluster_name scanChain_4 +// sub-command: add_black_boxes -modules " MemGen_16_10 " +// sub-command: set_scan_insertion_options -single_clock_edge_chains on -si_port_format oas_ts_si[%d] -so_port_format oas_ts_so[%d] +// sub-command: set_system_mode analysis +// Warning: Rule FN1 violation occurs 157 times +// Warning: Rule FP13 violation occurs 1 times +// Flattening process completed, cell instances=4379, gates=18234, PIs=13, POs=12, CPU time=0.09 sec. +// --------------------------------------------------------------------------- +// Begin circuit learning analyses. +// -------------------------------- +// Learning completed, CPU time=0.01 sec. +// --------------------------------------------------------------------------- +// Begin scan chain identification process, memory elements = 1194, +// sequential library cells = 1194. +// --------------------------------------------------------------------------- +// Warning: Model 'DLH_X1_LVT' has no muxscan scan equivalent and is treated as nonscan model +// ------------------------------------------------------------------------------ +// 170 sequential library cells are treated as non-scan. +// ------------------------------------------------------------------------------ +// 63 sequential library cells missing mux-scan equivalent. +// 107 sequential library cells defined non-scan. +// --------------------------------------------------------------------------- +// Begin scannability rules checking for 1024 sequential library cells. +// --------------------------------------------------------------------------- +// 1024 sequential library cells identified as scannable. +// --------------------------------------------------------------------------- +// Begin transparent latch checking for 63 latches. +// --------------------------------------------------------------------------- +// Warning: 32 latches not transparent due to uncontrollable. (D6) +// Number transparent latches = 31. +// --------------------------------------------------------------------------- +// Begin scan clock rules checking. +// --------------------------------------------------------------------------- +// 1 scan clock/set/reset lines have been identified. +// All scan clocks successfully passed off-state check. +// 1131 sequential cells passed clock stability checking. +// There were 43 clock rule C3 fails (clock may capture data affected by its captured data). +// Note: Trailing edge triggered device can capture data affected by leading edge. +// --------------------------------------------------------------------------- +// 170 non-scan memory elements are identified. +// --------------------------------------------------------------------------- +// 32 non-scan memory elements are identified as TIE-X. (D5) +// 107 non-scan memory elements are identified as INIT-X. (D5) +// 31 non-scan memory elements are identified as TLA. (D5) +// --------------------------------------------------------------------------- +// Number of targeted sequential library cells = 1024 +// Warning: The tool may require a shift-capture clock during insertion, +// but no 'shift_capture_clock' DFT signal was identified +// and no TCLK source was specified using the command 'set_scan_signals -tclk'. +// Note: The system clock 'clk_25mhz' will be used as the shift-capture clock, if needed. +// sub-command: report_drc_rules +C3: #fails=43 handling=note (clock may capture data affected by its captured data) +D5: #fails=170 handling=warning (non-scan memory element) +D6: #fails=32 handling=warning (non-transparent non-scan latches) +// sub-command: create_scan_chain_family scanChain_1 -include_elements "{/\thePC_CurrentPC_reg[0] } {/\thePC_CurrentPC_reg[10] } {/\thePC_CurrentPC_reg[11] } {/\thePC_CurrentPC_reg[12] } {/\thePC_CurrentPC_reg[13] } {/\thePC_CurrentPC_reg[14] } {/\thePC_CurrentPC_reg[15] } {/\thePC_CurrentPC_reg[16] } {/\thePC_CurrentPC_reg[17] } {/\thePC_CurrentPC_reg[18] } {/\thePC_CurrentPC_reg[19] } {/\thePC_CurrentPC_reg[1] } {/\thePC_CurrentPC_reg[20] } {/\thePC_CurrentPC_reg[21] } {/\thePC_CurrentPC_reg[22] } {/\thePC_CurrentPC_reg[23] } {/\thePC_CurrentPC_reg[24] } {/\thePC_CurrentPC_reg[25] } {/\thePC_CurrentPC_reg[26] } {/\thePC_CurrentPC_reg[27] } {/\thePC_CurrentPC_reg[28] } {/\thePC_CurrentPC_reg[29] } {/\thePC_CurrentPC_reg[2] } {/\thePC_CurrentPC_reg[30] } {/\thePC_CurrentPC_reg[31] } {/\thePC_CurrentPC_reg[3] } {/\thePC_CurrentPC_reg[4] } {/\thePC_CurrentPC_reg[5] } {/\thePC_CurrentPC_reg[6] } {/\thePC_CurrentPC_reg[7] } {/\thePC_CurrentPC_reg[8] } {/\thePC_CurrentPC_reg[9] } {/theRegisters/\registers_reg[10][0] } {/theRegisters/\registers_reg[10][10] } {/theRegisters/\registers_reg[10][11] } {/theRegisters/\registers_reg[10][12] } {/theRegisters/\registers_reg[10][13] } {/theRegisters/\registers_reg[10][14] } {/theRegisters/\registers_reg[10][15] } {/theRegisters/\registers_reg[10][16] } {/theRegisters/\registers_reg[10][17] } {/theRegisters/\registers_reg[10][18] } {/theRegisters/\registers_reg[10][19] } {/theRegisters/\registers_reg[10][1] } {/theRegisters/\registers_reg[10][20] } {/theRegisters/\registers_reg[10][21] } {/theRegisters/\registers_reg[10][22] } {/theRegisters/\registers_reg[10][23] } {/theRegisters/\registers_reg[10][24] } {/theRegisters/\registers_reg[10][25] } {/theRegisters/\registers_reg[10][26] } {/theRegisters/\registers_reg[10][27] } {/theRegisters/\registers_reg[10][28] } {/theRegisters/\registers_reg[10][29] } {/theRegisters/\registers_reg[10][2] } {/theRegisters/\registers_reg[10][30] } {/theRegisters/\registers_reg[10][31] } {/theRegisters/\registers_reg[10][3] } {/theRegisters/\registers_reg[10][4] } {/theRegisters/\registers_reg[10][5] } {/theRegisters/\registers_reg[10][6] } {/theRegisters/\registers_reg[10][7] } {/theRegisters/\registers_reg[10][8] } {/theRegisters/\registers_reg[10][9] } {/theRegisters/\registers_reg[11][0] } {/theRegisters/\registers_reg[11][10] } {/theRegisters/\registers_reg[11][11] } {/theRegisters/\registers_reg[11][12] } {/theRegisters/\registers_reg[11][13] } {/theRegisters/\registers_reg[11][14] } {/theRegisters/\registers_reg[11][15] } {/theRegisters/\registers_reg[11][16] } {/theRegisters/\registers_reg[11][17] } {/theRegisters/\registers_reg[11][18] } {/theRegisters/\registers_reg[11][19] } {/theRegisters/\registers_reg[11][1] } {/theRegisters/\registers_reg[11][20] } {/theRegisters/\registers_reg[11][21] } {/theRegisters/\registers_reg[11][22] } {/theRegisters/\registers_reg[11][23] } {/theRegisters/\registers_reg[11][24] } {/theRegisters/\registers_reg[11][25] } {/theRegisters/\registers_reg[11][26] } {/theRegisters/\registers_reg[11][27] } {/theRegisters/\registers_reg[11][28] } {/theRegisters/\registers_reg[11][29] } {/theRegisters/\registers_reg[11][2] } {/theRegisters/\registers_reg[11][30] } {/theRegisters/\registers_reg[11][31] } {/theRegisters/\registers_reg[11][3] } {/theRegisters/\registers_reg[11][4] } {/theRegisters/\registers_reg[11][5] } {/theRegisters/\registers_reg[11][6] } {/theRegisters/\registers_reg[11][7] } {/theRegisters/\registers_reg[11][8] } {/theRegisters/\registers_reg[11][9] } {/theRegisters/\registers_reg[12][0] } {/theRegisters/\registers_reg[12][10] } {/theRegisters/\registers_reg[12][11] } {/theRegisters/\registers_reg[12][12] } {/theRegisters/\registers_reg[12][13] } {/theRegisters/\registers_reg[12][14] } {/theRegisters/\registers_reg[12][15] } {/theRegisters/\registers_reg[12][16] } {/theRegisters/\registers_reg[12][17] } {/theRegisters/\registers_reg[12][18] } {/theRegisters/\registers_reg[12][19] } {/theRegisters/\registers_reg[12][1] } {/theRegisters/\registers_reg[12][20] } {/theRegisters/\registers_reg[12][21] } {/theRegisters/\registers_reg[12][22] } {/theRegisters/\registers_reg[12][23] } {/theRegisters/\registers_reg[12][24] } {/theRegisters/\registers_reg[12][25] } {/theRegisters/\registers_reg[12][26] } {/theRegisters/\registers_reg[12][27] } {/theRegisters/\registers_reg[12][28] } {/theRegisters/\registers_reg[12][29] } {/theRegisters/\registers_reg[12][2] } {/theRegisters/\registers_reg[12][30] } {/theRegisters/\registers_reg[12][31] } {/theRegisters/\registers_reg[12][3] } {/theRegisters/\registers_reg[12][4] } {/theRegisters/\registers_reg[12][5] } {/theRegisters/\registers_reg[12][6] } {/theRegisters/\registers_reg[12][7] } {/theRegisters/\registers_reg[12][8] } {/theRegisters/\registers_reg[12][9] } {/theRegisters/\registers_reg[13][0] } {/theRegisters/\registers_reg[13][10] } {/theRegisters/\registers_reg[13][11] } {/theRegisters/\registers_reg[13][12] } {/theRegisters/\registers_reg[13][13] } {/theRegisters/\registers_reg[13][14] } {/theRegisters/\registers_reg[13][15] } {/theRegisters/\registers_reg[13][16] } {/theRegisters/\registers_reg[13][17] } {/theRegisters/\registers_reg[13][18] } {/theRegisters/\registers_reg[13][19] } {/theRegisters/\registers_reg[13][1] } {/theRegisters/\registers_reg[13][20] } {/theRegisters/\registers_reg[13][21] } {/theRegisters/\registers_reg[13][22] } {/theRegisters/\registers_reg[13][23] } {/theRegisters/\registers_reg[13][24] } {/theRegisters/\registers_reg[13][25] } {/theRegisters/\registers_reg[13][26] } {/theRegisters/\registers_reg[13][27] } {/theRegisters/\registers_reg[13][28] } {/theRegisters/\registers_reg[13][29] } {/theRegisters/\registers_reg[13][2] } {/theRegisters/\registers_reg[13][30] } {/theRegisters/\registers_reg[13][31] } {/theRegisters/\registers_reg[13][3] } {/theRegisters/\registers_reg[13][4] } {/theRegisters/\registers_reg[13][5] } {/theRegisters/\registers_reg[13][6] } {/theRegisters/\registers_reg[13][7] } {/theRegisters/\registers_reg[13][8] } {/theRegisters/\registers_reg[13][9] } {/theRegisters/\registers_reg[14][0] } {/theRegisters/\registers_reg[14][10] } {/theRegisters/\registers_reg[14][11] } {/theRegisters/\registers_reg[14][12] } {/theRegisters/\registers_reg[14][13] } {/theRegisters/\registers_reg[14][14] } {/theRegisters/\registers_reg[14][15] } {/theRegisters/\registers_reg[14][16] } {/theRegisters/\registers_reg[14][17] } {/theRegisters/\registers_reg[14][18] } {/theRegisters/\registers_reg[14][19] } {/theRegisters/\registers_reg[14][1] } {/theRegisters/\registers_reg[14][20] } {/theRegisters/\registers_reg[14][21] } {/theRegisters/\registers_reg[14][22] } {/theRegisters/\registers_reg[14][23] } {/theRegisters/\registers_reg[14][24] } {/theRegisters/\registers_reg[14][25] } {/theRegisters/\registers_reg[14][26] } {/theRegisters/\registers_reg[14][27] } {/theRegisters/\registers_reg[14][28] } {/theRegisters/\registers_reg[14][29] } {/theRegisters/\registers_reg[14][2] } {/theRegisters/\registers_reg[14][30] } {/theRegisters/\registers_reg[14][31] } {/theRegisters/\registers_reg[14][3] } {/theRegisters/\registers_reg[14][4] } {/theRegisters/\registers_reg[14][5] } {/theRegisters/\registers_reg[14][6] } {/theRegisters/\registers_reg[14][7] } {/theRegisters/\registers_reg[14][8] } {/theRegisters/\registers_reg[14][9] } {/theRegisters/\registers_reg[15][0] } {/theRegisters/\registers_reg[15][10] } {/theRegisters/\registers_reg[15][11] } {/theRegisters/\registers_reg[15][12] } {/theRegisters/\registers_reg[15][13] } {/theRegisters/\registers_reg[15][14] } {/theRegisters/\registers_reg[15][15] } {/theRegisters/\registers_reg[15][16] } {/theRegisters/\registers_reg[15][17] } {/theRegisters/\registers_reg[15][18] } {/theRegisters/\registers_reg[15][19] } {/theRegisters/\registers_reg[15][1] } {/theRegisters/\registers_reg[15][20] } {/theRegisters/\registers_reg[15][21] } {/theRegisters/\registers_reg[15][22] } {/theRegisters/\registers_reg[15][23] } {/theRegisters/\registers_reg[15][24] } {/theRegisters/\registers_reg[15][25] } {/theRegisters/\registers_reg[15][26] } {/theRegisters/\registers_reg[15][27] } {/theRegisters/\registers_reg[15][28] } {/theRegisters/\registers_reg[15][29] } {/theRegisters/\registers_reg[15][2] } {/theRegisters/\registers_reg[15][30] } {/theRegisters/\registers_reg[15][31] } {/theRegisters/\registers_reg[15][3] } {/theRegisters/\registers_reg[15][4] } {/theRegisters/\registers_reg[15][5] } {/theRegisters/\registers_reg[15][6] } {/theRegisters/\registers_reg[15][7] } {/theRegisters/\registers_reg[15][8] } {/theRegisters/\registers_reg[15][9] } {/theRegisters/\registers_reg[16][0] } {/theRegisters/\registers_reg[16][10] } {/theRegisters/\registers_reg[16][11] } {/theRegisters/\registers_reg[16][12] } {/theRegisters/\registers_reg[16][13] } {/theRegisters/\registers_reg[16][14] } {/theRegisters/\registers_reg[16][15] } {/theRegisters/\registers_reg[16][16] } {/theRegisters/\registers_reg[16][17] } {/theRegisters/\registers_reg[16][18] } {/theRegisters/\registers_reg[16][19] } {/theRegisters/\registers_reg[16][1] } {/theRegisters/\registers_reg[16][20] } {/theRegisters/\registers_reg[16][21] } {/theRegisters/\registers_reg[16][22] } {/theRegisters/\registers_reg[16][23] } {/theRegisters/\registers_reg[16][24] } {/theRegisters/\registers_reg[16][25] } {/theRegisters/\registers_reg[16][26] } {/theRegisters/\registers_reg[16][27] } {/theRegisters/\registers_reg[16][28] } {/theRegisters/\registers_reg[16][29] } {/theRegisters/\registers_reg[16][2] } {/theRegisters/\registers_reg[16][30] } {/theRegisters/\registers_reg[16][31] } {/theRegisters/\registers_reg[16][3] } {/theRegisters/\registers_reg[16][4] } {/theRegisters/\registers_reg[16][5] } {/theRegisters/\registers_reg[16][6] } {/theRegisters/\registers_reg[16][7] } {/theRegisters/\registers_reg[16][8] } {/theRegisters/\registers_reg[16][9] } " -si_connections "SI_1 " -so_connections "SO_1 " -chain_count 1 +// sub-command: create_scan_chain_family scanChain_2 -include_elements "{/theRegisters/\registers_reg[17][0] } {/theRegisters/\registers_reg[17][10] } {/theRegisters/\registers_reg[17][11] } {/theRegisters/\registers_reg[17][12] } {/theRegisters/\registers_reg[17][13] } {/theRegisters/\registers_reg[17][14] } {/theRegisters/\registers_reg[17][15] } {/theRegisters/\registers_reg[17][16] } {/theRegisters/\registers_reg[17][17] } {/theRegisters/\registers_reg[17][18] } {/theRegisters/\registers_reg[17][19] } {/theRegisters/\registers_reg[17][1] } {/theRegisters/\registers_reg[17][20] } {/theRegisters/\registers_reg[17][21] } {/theRegisters/\registers_reg[17][22] } {/theRegisters/\registers_reg[17][23] } {/theRegisters/\registers_reg[17][24] } {/theRegisters/\registers_reg[17][25] } {/theRegisters/\registers_reg[17][26] } {/theRegisters/\registers_reg[17][27] } {/theRegisters/\registers_reg[17][28] } {/theRegisters/\registers_reg[17][29] } {/theRegisters/\registers_reg[17][2] } {/theRegisters/\registers_reg[17][30] } {/theRegisters/\registers_reg[17][31] } {/theRegisters/\registers_reg[17][3] } {/theRegisters/\registers_reg[17][4] } {/theRegisters/\registers_reg[17][5] } {/theRegisters/\registers_reg[17][6] } {/theRegisters/\registers_reg[17][7] } {/theRegisters/\registers_reg[17][8] } {/theRegisters/\registers_reg[17][9] } {/theRegisters/\registers_reg[18][0] } {/theRegisters/\registers_reg[18][10] } {/theRegisters/\registers_reg[18][11] } {/theRegisters/\registers_reg[18][12] } {/theRegisters/\registers_reg[18][13] } {/theRegisters/\registers_reg[18][14] } {/theRegisters/\registers_reg[18][15] } {/theRegisters/\registers_reg[18][16] } {/theRegisters/\registers_reg[18][17] } {/theRegisters/\registers_reg[18][18] } {/theRegisters/\registers_reg[18][19] } {/theRegisters/\registers_reg[18][1] } {/theRegisters/\registers_reg[18][20] } {/theRegisters/\registers_reg[18][21] } {/theRegisters/\registers_reg[18][22] } {/theRegisters/\registers_reg[18][23] } {/theRegisters/\registers_reg[18][24] } {/theRegisters/\registers_reg[18][25] } {/theRegisters/\registers_reg[18][26] } {/theRegisters/\registers_reg[18][27] } {/theRegisters/\registers_reg[18][28] } {/theRegisters/\registers_reg[18][29] } {/theRegisters/\registers_reg[18][2] } {/theRegisters/\registers_reg[18][30] } {/theRegisters/\registers_reg[18][31] } {/theRegisters/\registers_reg[18][3] } {/theRegisters/\registers_reg[18][4] } {/theRegisters/\registers_reg[18][5] } {/theRegisters/\registers_reg[18][6] } {/theRegisters/\registers_reg[18][7] } {/theRegisters/\registers_reg[18][8] } {/theRegisters/\registers_reg[18][9] } {/theRegisters/\registers_reg[19][0] } {/theRegisters/\registers_reg[19][10] } {/theRegisters/\registers_reg[19][11] } {/theRegisters/\registers_reg[19][12] } {/theRegisters/\registers_reg[19][13] } {/theRegisters/\registers_reg[19][14] } {/theRegisters/\registers_reg[19][15] } {/theRegisters/\registers_reg[19][16] } {/theRegisters/\registers_reg[19][17] } {/theRegisters/\registers_reg[19][18] } {/theRegisters/\registers_reg[19][19] } {/theRegisters/\registers_reg[19][1] } {/theRegisters/\registers_reg[19][20] } {/theRegisters/\registers_reg[19][21] } {/theRegisters/\registers_reg[19][22] } {/theRegisters/\registers_reg[19][23] } {/theRegisters/\registers_reg[19][24] } {/theRegisters/\registers_reg[19][25] } {/theRegisters/\registers_reg[19][26] } {/theRegisters/\registers_reg[19][27] } {/theRegisters/\registers_reg[19][28] } {/theRegisters/\registers_reg[19][29] } {/theRegisters/\registers_reg[19][2] } {/theRegisters/\registers_reg[19][30] } {/theRegisters/\registers_reg[19][31] } {/theRegisters/\registers_reg[19][3] } {/theRegisters/\registers_reg[19][4] } {/theRegisters/\registers_reg[19][5] } {/theRegisters/\registers_reg[19][6] } {/theRegisters/\registers_reg[19][7] } {/theRegisters/\registers_reg[19][8] } {/theRegisters/\registers_reg[19][9] } {/theRegisters/\registers_reg[1][0] } {/theRegisters/\registers_reg[1][10] } {/theRegisters/\registers_reg[1][11] } {/theRegisters/\registers_reg[1][12] } {/theRegisters/\registers_reg[1][13] } {/theRegisters/\registers_reg[1][14] } {/theRegisters/\registers_reg[1][15] } {/theRegisters/\registers_reg[1][16] } {/theRegisters/\registers_reg[1][17] } {/theRegisters/\registers_reg[1][18] } {/theRegisters/\registers_reg[1][19] } {/theRegisters/\registers_reg[1][1] } {/theRegisters/\registers_reg[1][20] } {/theRegisters/\registers_reg[1][21] } {/theRegisters/\registers_reg[1][22] } {/theRegisters/\registers_reg[1][23] } {/theRegisters/\registers_reg[1][24] } {/theRegisters/\registers_reg[1][25] } {/theRegisters/\registers_reg[1][26] } {/theRegisters/\registers_reg[1][27] } {/theRegisters/\registers_reg[1][28] } {/theRegisters/\registers_reg[1][29] } {/theRegisters/\registers_reg[1][2] } {/theRegisters/\registers_reg[1][30] } {/theRegisters/\registers_reg[1][31] } {/theRegisters/\registers_reg[1][3] } {/theRegisters/\registers_reg[1][4] } {/theRegisters/\registers_reg[1][5] } {/theRegisters/\registers_reg[1][6] } {/theRegisters/\registers_reg[1][7] } {/theRegisters/\registers_reg[1][8] } {/theRegisters/\registers_reg[1][9] } {/theRegisters/\registers_reg[20][0] } {/theRegisters/\registers_reg[20][10] } {/theRegisters/\registers_reg[20][11] } {/theRegisters/\registers_reg[20][12] } {/theRegisters/\registers_reg[20][13] } {/theRegisters/\registers_reg[20][14] } {/theRegisters/\registers_reg[20][15] } {/theRegisters/\registers_reg[20][16] } {/theRegisters/\registers_reg[20][17] } {/theRegisters/\registers_reg[20][18] } {/theRegisters/\registers_reg[20][19] } {/theRegisters/\registers_reg[20][1] } {/theRegisters/\registers_reg[20][20] } {/theRegisters/\registers_reg[20][21] } {/theRegisters/\registers_reg[20][22] } {/theRegisters/\registers_reg[20][23] } {/theRegisters/\registers_reg[20][24] } {/theRegisters/\registers_reg[20][25] } {/theRegisters/\registers_reg[20][26] } {/theRegisters/\registers_reg[20][27] } {/theRegisters/\registers_reg[20][28] } {/theRegisters/\registers_reg[20][29] } {/theRegisters/\registers_reg[20][2] } {/theRegisters/\registers_reg[20][30] } {/theRegisters/\registers_reg[20][31] } {/theRegisters/\registers_reg[20][3] } {/theRegisters/\registers_reg[20][4] } {/theRegisters/\registers_reg[20][5] } {/theRegisters/\registers_reg[20][6] } {/theRegisters/\registers_reg[20][7] } {/theRegisters/\registers_reg[20][8] } {/theRegisters/\registers_reg[20][9] } {/theRegisters/\registers_reg[21][0] } {/theRegisters/\registers_reg[21][10] } {/theRegisters/\registers_reg[21][11] } {/theRegisters/\registers_reg[21][12] } {/theRegisters/\registers_reg[21][13] } {/theRegisters/\registers_reg[21][14] } {/theRegisters/\registers_reg[21][15] } {/theRegisters/\registers_reg[21][16] } {/theRegisters/\registers_reg[21][17] } {/theRegisters/\registers_reg[21][18] } {/theRegisters/\registers_reg[21][19] } {/theRegisters/\registers_reg[21][1] } {/theRegisters/\registers_reg[21][20] } {/theRegisters/\registers_reg[21][21] } {/theRegisters/\registers_reg[21][22] } {/theRegisters/\registers_reg[21][23] } {/theRegisters/\registers_reg[21][24] } {/theRegisters/\registers_reg[21][25] } {/theRegisters/\registers_reg[21][26] } {/theRegisters/\registers_reg[21][27] } {/theRegisters/\registers_reg[21][28] } {/theRegisters/\registers_reg[21][29] } {/theRegisters/\registers_reg[21][2] } {/theRegisters/\registers_reg[21][30] } {/theRegisters/\registers_reg[21][31] } {/theRegisters/\registers_reg[21][3] } {/theRegisters/\registers_reg[21][4] } {/theRegisters/\registers_reg[21][5] } {/theRegisters/\registers_reg[21][6] } {/theRegisters/\registers_reg[21][7] } {/theRegisters/\registers_reg[21][8] } {/theRegisters/\registers_reg[21][9] } {/theRegisters/\registers_reg[22][0] } {/theRegisters/\registers_reg[22][10] } {/theRegisters/\registers_reg[22][11] } {/theRegisters/\registers_reg[22][12] } {/theRegisters/\registers_reg[22][13] } {/theRegisters/\registers_reg[22][14] } {/theRegisters/\registers_reg[22][15] } {/theRegisters/\registers_reg[22][16] } {/theRegisters/\registers_reg[22][17] } {/theRegisters/\registers_reg[22][18] } {/theRegisters/\registers_reg[22][19] } {/theRegisters/\registers_reg[22][1] } {/theRegisters/\registers_reg[22][20] } {/theRegisters/\registers_reg[22][21] } {/theRegisters/\registers_reg[22][22] } {/theRegisters/\registers_reg[22][23] } {/theRegisters/\registers_reg[22][24] } {/theRegisters/\registers_reg[22][25] } {/theRegisters/\registers_reg[22][26] } {/theRegisters/\registers_reg[22][27] } {/theRegisters/\registers_reg[22][28] } {/theRegisters/\registers_reg[22][29] } {/theRegisters/\registers_reg[22][2] } {/theRegisters/\registers_reg[22][30] } {/theRegisters/\registers_reg[22][31] } {/theRegisters/\registers_reg[22][3] } {/theRegisters/\registers_reg[22][4] } {/theRegisters/\registers_reg[22][5] } {/theRegisters/\registers_reg[22][6] } {/theRegisters/\registers_reg[22][7] } {/theRegisters/\registers_reg[22][8] } {/theRegisters/\registers_reg[22][9] } {/theRegisters/\registers_reg[23][0] } {/theRegisters/\registers_reg[23][10] } {/theRegisters/\registers_reg[23][11] } {/theRegisters/\registers_reg[23][12] } {/theRegisters/\registers_reg[23][13] } {/theRegisters/\registers_reg[23][14] } {/theRegisters/\registers_reg[23][15] } {/theRegisters/\registers_reg[23][16] } {/theRegisters/\registers_reg[23][17] } {/theRegisters/\registers_reg[23][18] } {/theRegisters/\registers_reg[23][19] } {/theRegisters/\registers_reg[23][1] } {/theRegisters/\registers_reg[23][20] } {/theRegisters/\registers_reg[23][21] } {/theRegisters/\registers_reg[23][22] } {/theRegisters/\registers_reg[23][23] } {/theRegisters/\registers_reg[23][24] } {/theRegisters/\registers_reg[23][25] } {/theRegisters/\registers_reg[23][26] } {/theRegisters/\registers_reg[23][27] } {/theRegisters/\registers_reg[23][28] } {/theRegisters/\registers_reg[23][29] } {/theRegisters/\registers_reg[23][2] } {/theRegisters/\registers_reg[23][30] } {/theRegisters/\registers_reg[23][31] } {/theRegisters/\registers_reg[23][3] } {/theRegisters/\registers_reg[23][4] } {/theRegisters/\registers_reg[23][5] } {/theRegisters/\registers_reg[23][6] } {/theRegisters/\registers_reg[23][7] } {/theRegisters/\registers_reg[23][8] } {/theRegisters/\registers_reg[23][9] } " -si_connections "SI_2 " -so_connections "SO_2 " -chain_count 1 +// sub-command: create_scan_chain_family scanChain_3 -include_elements "{/theRegisters/\registers_reg[24][0] } {/theRegisters/\registers_reg[24][10] } {/theRegisters/\registers_reg[24][11] } {/theRegisters/\registers_reg[24][12] } {/theRegisters/\registers_reg[24][13] } {/theRegisters/\registers_reg[24][14] } {/theRegisters/\registers_reg[24][15] } {/theRegisters/\registers_reg[24][16] } {/theRegisters/\registers_reg[24][17] } {/theRegisters/\registers_reg[24][18] } {/theRegisters/\registers_reg[24][19] } {/theRegisters/\registers_reg[24][1] } {/theRegisters/\registers_reg[24][20] } {/theRegisters/\registers_reg[24][21] } {/theRegisters/\registers_reg[24][22] } {/theRegisters/\registers_reg[24][23] } {/theRegisters/\registers_reg[24][24] } {/theRegisters/\registers_reg[24][25] } {/theRegisters/\registers_reg[24][26] } {/theRegisters/\registers_reg[24][27] } {/theRegisters/\registers_reg[24][28] } {/theRegisters/\registers_reg[24][29] } {/theRegisters/\registers_reg[24][2] } {/theRegisters/\registers_reg[24][30] } {/theRegisters/\registers_reg[24][31] } {/theRegisters/\registers_reg[24][3] } {/theRegisters/\registers_reg[24][4] } {/theRegisters/\registers_reg[24][5] } {/theRegisters/\registers_reg[24][6] } {/theRegisters/\registers_reg[24][7] } {/theRegisters/\registers_reg[24][8] } {/theRegisters/\registers_reg[24][9] } {/theRegisters/\registers_reg[25][0] } {/theRegisters/\registers_reg[25][10] } {/theRegisters/\registers_reg[25][11] } {/theRegisters/\registers_reg[25][12] } {/theRegisters/\registers_reg[25][13] } {/theRegisters/\registers_reg[25][14] } {/theRegisters/\registers_reg[25][15] } {/theRegisters/\registers_reg[25][16] } {/theRegisters/\registers_reg[25][17] } {/theRegisters/\registers_reg[25][18] } {/theRegisters/\registers_reg[25][19] } {/theRegisters/\registers_reg[25][1] } {/theRegisters/\registers_reg[25][20] } {/theRegisters/\registers_reg[25][21] } {/theRegisters/\registers_reg[25][22] } {/theRegisters/\registers_reg[25][23] } {/theRegisters/\registers_reg[25][24] } {/theRegisters/\registers_reg[25][25] } {/theRegisters/\registers_reg[25][26] } {/theRegisters/\registers_reg[25][27] } {/theRegisters/\registers_reg[25][28] } {/theRegisters/\registers_reg[25][29] } {/theRegisters/\registers_reg[25][2] } {/theRegisters/\registers_reg[25][30] } {/theRegisters/\registers_reg[25][31] } {/theRegisters/\registers_reg[25][3] } {/theRegisters/\registers_reg[25][4] } {/theRegisters/\registers_reg[25][5] } {/theRegisters/\registers_reg[25][6] } {/theRegisters/\registers_reg[25][7] } {/theRegisters/\registers_reg[25][8] } {/theRegisters/\registers_reg[25][9] } {/theRegisters/\registers_reg[26][0] } {/theRegisters/\registers_reg[26][10] } {/theRegisters/\registers_reg[26][11] } {/theRegisters/\registers_reg[26][12] } {/theRegisters/\registers_reg[26][13] } {/theRegisters/\registers_reg[26][14] } {/theRegisters/\registers_reg[26][15] } {/theRegisters/\registers_reg[26][16] } {/theRegisters/\registers_reg[26][17] } {/theRegisters/\registers_reg[26][18] } {/theRegisters/\registers_reg[26][19] } {/theRegisters/\registers_reg[26][1] } {/theRegisters/\registers_reg[26][20] } {/theRegisters/\registers_reg[26][21] } {/theRegisters/\registers_reg[26][22] } {/theRegisters/\registers_reg[26][23] } {/theRegisters/\registers_reg[26][24] } {/theRegisters/\registers_reg[26][25] } {/theRegisters/\registers_reg[26][26] } {/theRegisters/\registers_reg[26][27] } {/theRegisters/\registers_reg[26][28] } {/theRegisters/\registers_reg[26][29] } {/theRegisters/\registers_reg[26][2] } {/theRegisters/\registers_reg[26][30] } {/theRegisters/\registers_reg[26][31] } {/theRegisters/\registers_reg[26][3] } {/theRegisters/\registers_reg[26][4] } {/theRegisters/\registers_reg[26][5] } {/theRegisters/\registers_reg[26][6] } {/theRegisters/\registers_reg[26][7] } {/theRegisters/\registers_reg[26][8] } {/theRegisters/\registers_reg[26][9] } {/theRegisters/\registers_reg[27][0] } {/theRegisters/\registers_reg[27][10] } {/theRegisters/\registers_reg[27][11] } {/theRegisters/\registers_reg[27][12] } {/theRegisters/\registers_reg[27][13] } {/theRegisters/\registers_reg[27][14] } {/theRegisters/\registers_reg[27][15] } {/theRegisters/\registers_reg[27][16] } {/theRegisters/\registers_reg[27][17] } {/theRegisters/\registers_reg[27][18] } {/theRegisters/\registers_reg[27][19] } {/theRegisters/\registers_reg[27][1] } {/theRegisters/\registers_reg[27][20] } {/theRegisters/\registers_reg[27][21] } {/theRegisters/\registers_reg[27][22] } {/theRegisters/\registers_reg[27][23] } {/theRegisters/\registers_reg[27][24] } {/theRegisters/\registers_reg[27][25] } {/theRegisters/\registers_reg[27][26] } {/theRegisters/\registers_reg[27][27] } {/theRegisters/\registers_reg[27][28] } {/theRegisters/\registers_reg[27][29] } {/theRegisters/\registers_reg[27][2] } {/theRegisters/\registers_reg[27][30] } {/theRegisters/\registers_reg[27][31] } {/theRegisters/\registers_reg[27][3] } {/theRegisters/\registers_reg[27][4] } {/theRegisters/\registers_reg[27][5] } {/theRegisters/\registers_reg[27][6] } {/theRegisters/\registers_reg[27][7] } {/theRegisters/\registers_reg[27][8] } {/theRegisters/\registers_reg[27][9] } {/theRegisters/\registers_reg[28][0] } {/theRegisters/\registers_reg[28][10] } {/theRegisters/\registers_reg[28][11] } {/theRegisters/\registers_reg[28][12] } {/theRegisters/\registers_reg[28][13] } {/theRegisters/\registers_reg[28][14] } {/theRegisters/\registers_reg[28][15] } {/theRegisters/\registers_reg[28][16] } {/theRegisters/\registers_reg[28][17] } {/theRegisters/\registers_reg[28][18] } {/theRegisters/\registers_reg[28][19] } {/theRegisters/\registers_reg[28][1] } {/theRegisters/\registers_reg[28][20] } {/theRegisters/\registers_reg[28][21] } {/theRegisters/\registers_reg[28][22] } {/theRegisters/\registers_reg[28][23] } {/theRegisters/\registers_reg[28][24] } {/theRegisters/\registers_reg[28][25] } {/theRegisters/\registers_reg[28][26] } {/theRegisters/\registers_reg[28][27] } {/theRegisters/\registers_reg[28][28] } {/theRegisters/\registers_reg[28][29] } {/theRegisters/\registers_reg[28][2] } {/theRegisters/\registers_reg[28][30] } {/theRegisters/\registers_reg[28][31] } {/theRegisters/\registers_reg[28][3] } {/theRegisters/\registers_reg[28][4] } {/theRegisters/\registers_reg[28][5] } {/theRegisters/\registers_reg[28][6] } {/theRegisters/\registers_reg[28][7] } {/theRegisters/\registers_reg[28][8] } {/theRegisters/\registers_reg[28][9] } {/theRegisters/\registers_reg[29][0] } {/theRegisters/\registers_reg[29][10] } {/theRegisters/\registers_reg[29][11] } {/theRegisters/\registers_reg[29][12] } {/theRegisters/\registers_reg[29][13] } {/theRegisters/\registers_reg[29][14] } {/theRegisters/\registers_reg[29][15] } {/theRegisters/\registers_reg[29][16] } {/theRegisters/\registers_reg[29][17] } {/theRegisters/\registers_reg[29][18] } {/theRegisters/\registers_reg[29][19] } {/theRegisters/\registers_reg[29][1] } {/theRegisters/\registers_reg[29][20] } {/theRegisters/\registers_reg[29][21] } {/theRegisters/\registers_reg[29][22] } {/theRegisters/\registers_reg[29][23] } {/theRegisters/\registers_reg[29][24] } {/theRegisters/\registers_reg[29][25] } {/theRegisters/\registers_reg[29][26] } {/theRegisters/\registers_reg[29][27] } {/theRegisters/\registers_reg[29][28] } {/theRegisters/\registers_reg[29][29] } {/theRegisters/\registers_reg[29][2] } {/theRegisters/\registers_reg[29][30] } {/theRegisters/\registers_reg[29][31] } {/theRegisters/\registers_reg[29][3] } {/theRegisters/\registers_reg[29][4] } {/theRegisters/\registers_reg[29][5] } {/theRegisters/\registers_reg[29][6] } {/theRegisters/\registers_reg[29][7] } {/theRegisters/\registers_reg[29][8] } {/theRegisters/\registers_reg[29][9] } {/theRegisters/\registers_reg[2][0] } {/theRegisters/\registers_reg[2][10] } {/theRegisters/\registers_reg[2][11] } {/theRegisters/\registers_reg[2][12] } {/theRegisters/\registers_reg[2][13] } {/theRegisters/\registers_reg[2][14] } {/theRegisters/\registers_reg[2][15] } {/theRegisters/\registers_reg[2][16] } {/theRegisters/\registers_reg[2][17] } {/theRegisters/\registers_reg[2][18] } {/theRegisters/\registers_reg[2][19] } {/theRegisters/\registers_reg[2][1] } {/theRegisters/\registers_reg[2][20] } {/theRegisters/\registers_reg[2][21] } {/theRegisters/\registers_reg[2][22] } {/theRegisters/\registers_reg[2][23] } {/theRegisters/\registers_reg[2][24] } {/theRegisters/\registers_reg[2][25] } {/theRegisters/\registers_reg[2][26] } {/theRegisters/\registers_reg[2][27] } {/theRegisters/\registers_reg[2][28] } {/theRegisters/\registers_reg[2][29] } {/theRegisters/\registers_reg[2][2] } {/theRegisters/\registers_reg[2][30] } {/theRegisters/\registers_reg[2][31] } {/theRegisters/\registers_reg[2][3] } {/theRegisters/\registers_reg[2][4] } {/theRegisters/\registers_reg[2][5] } {/theRegisters/\registers_reg[2][6] } {/theRegisters/\registers_reg[2][7] } {/theRegisters/\registers_reg[2][8] } {/theRegisters/\registers_reg[2][9] } {/theRegisters/\registers_reg[30][0] } {/theRegisters/\registers_reg[30][10] } {/theRegisters/\registers_reg[30][11] } {/theRegisters/\registers_reg[30][12] } {/theRegisters/\registers_reg[30][13] } {/theRegisters/\registers_reg[30][14] } {/theRegisters/\registers_reg[30][15] } {/theRegisters/\registers_reg[30][16] } {/theRegisters/\registers_reg[30][17] } {/theRegisters/\registers_reg[30][18] } {/theRegisters/\registers_reg[30][19] } {/theRegisters/\registers_reg[30][1] } {/theRegisters/\registers_reg[30][20] } {/theRegisters/\registers_reg[30][21] } {/theRegisters/\registers_reg[30][22] } {/theRegisters/\registers_reg[30][23] } {/theRegisters/\registers_reg[30][24] } {/theRegisters/\registers_reg[30][25] } {/theRegisters/\registers_reg[30][26] } {/theRegisters/\registers_reg[30][27] } {/theRegisters/\registers_reg[30][28] } {/theRegisters/\registers_reg[30][29] } {/theRegisters/\registers_reg[30][2] } {/theRegisters/\registers_reg[30][30] } {/theRegisters/\registers_reg[30][31] } {/theRegisters/\registers_reg[30][3] } {/theRegisters/\registers_reg[30][4] } {/theRegisters/\registers_reg[30][5] } {/theRegisters/\registers_reg[30][6] } {/theRegisters/\registers_reg[30][7] } {/theRegisters/\registers_reg[30][8] } {/theRegisters/\registers_reg[30][9] } " -si_connections "SI_3 " -so_connections "SO_3 " -chain_count 1 +// sub-command: create_scan_chain_family scanChain_4 -include_elements "{/theRegisters/\registers_reg[31][0] } {/theRegisters/\registers_reg[31][10] } {/theRegisters/\registers_reg[31][11] } {/theRegisters/\registers_reg[31][12] } {/theRegisters/\registers_reg[31][13] } {/theRegisters/\registers_reg[31][14] } {/theRegisters/\registers_reg[31][15] } {/theRegisters/\registers_reg[31][16] } {/theRegisters/\registers_reg[31][17] } {/theRegisters/\registers_reg[31][18] } {/theRegisters/\registers_reg[31][19] } {/theRegisters/\registers_reg[31][1] } {/theRegisters/\registers_reg[31][20] } {/theRegisters/\registers_reg[31][21] } {/theRegisters/\registers_reg[31][22] } {/theRegisters/\registers_reg[31][23] } {/theRegisters/\registers_reg[31][24] } {/theRegisters/\registers_reg[31][25] } {/theRegisters/\registers_reg[31][26] } {/theRegisters/\registers_reg[31][27] } {/theRegisters/\registers_reg[31][28] } {/theRegisters/\registers_reg[31][29] } {/theRegisters/\registers_reg[31][2] } {/theRegisters/\registers_reg[31][30] } {/theRegisters/\registers_reg[31][31] } {/theRegisters/\registers_reg[31][3] } {/theRegisters/\registers_reg[31][4] } {/theRegisters/\registers_reg[31][5] } {/theRegisters/\registers_reg[31][6] } {/theRegisters/\registers_reg[31][7] } {/theRegisters/\registers_reg[31][8] } {/theRegisters/\registers_reg[31][9] } {/theRegisters/\registers_reg[3][0] } {/theRegisters/\registers_reg[3][10] } {/theRegisters/\registers_reg[3][11] } {/theRegisters/\registers_reg[3][12] } {/theRegisters/\registers_reg[3][13] } {/theRegisters/\registers_reg[3][14] } {/theRegisters/\registers_reg[3][15] } {/theRegisters/\registers_reg[3][16] } {/theRegisters/\registers_reg[3][17] } {/theRegisters/\registers_reg[3][18] } {/theRegisters/\registers_reg[3][19] } {/theRegisters/\registers_reg[3][1] } {/theRegisters/\registers_reg[3][20] } {/theRegisters/\registers_reg[3][21] } {/theRegisters/\registers_reg[3][22] } {/theRegisters/\registers_reg[3][23] } {/theRegisters/\registers_reg[3][24] } {/theRegisters/\registers_reg[3][25] } {/theRegisters/\registers_reg[3][26] } {/theRegisters/\registers_reg[3][27] } {/theRegisters/\registers_reg[3][28] } {/theRegisters/\registers_reg[3][29] } {/theRegisters/\registers_reg[3][2] } {/theRegisters/\registers_reg[3][30] } {/theRegisters/\registers_reg[3][31] } {/theRegisters/\registers_reg[3][3] } {/theRegisters/\registers_reg[3][4] } {/theRegisters/\registers_reg[3][5] } {/theRegisters/\registers_reg[3][6] } {/theRegisters/\registers_reg[3][7] } {/theRegisters/\registers_reg[3][8] } {/theRegisters/\registers_reg[3][9] } {/theRegisters/\registers_reg[4][0] } {/theRegisters/\registers_reg[4][10] } {/theRegisters/\registers_reg[4][11] } {/theRegisters/\registers_reg[4][12] } {/theRegisters/\registers_reg[4][13] } {/theRegisters/\registers_reg[4][14] } {/theRegisters/\registers_reg[4][15] } {/theRegisters/\registers_reg[4][16] } {/theRegisters/\registers_reg[4][17] } {/theRegisters/\registers_reg[4][18] } {/theRegisters/\registers_reg[4][19] } {/theRegisters/\registers_reg[4][1] } {/theRegisters/\registers_reg[4][20] } {/theRegisters/\registers_reg[4][21] } {/theRegisters/\registers_reg[4][22] } {/theRegisters/\registers_reg[4][23] } {/theRegisters/\registers_reg[4][24] } {/theRegisters/\registers_reg[4][25] } {/theRegisters/\registers_reg[4][26] } {/theRegisters/\registers_reg[4][27] } {/theRegisters/\registers_reg[4][28] } {/theRegisters/\registers_reg[4][29] } {/theRegisters/\registers_reg[4][2] } {/theRegisters/\registers_reg[4][30] } {/theRegisters/\registers_reg[4][31] } {/theRegisters/\registers_reg[4][3] } {/theRegisters/\registers_reg[4][4] } {/theRegisters/\registers_reg[4][5] } {/theRegisters/\registers_reg[4][6] } {/theRegisters/\registers_reg[4][7] } {/theRegisters/\registers_reg[4][8] } {/theRegisters/\registers_reg[4][9] } {/theRegisters/\registers_reg[5][0] } {/theRegisters/\registers_reg[5][10] } {/theRegisters/\registers_reg[5][11] } {/theRegisters/\registers_reg[5][12] } {/theRegisters/\registers_reg[5][13] } {/theRegisters/\registers_reg[5][14] } {/theRegisters/\registers_reg[5][15] } {/theRegisters/\registers_reg[5][16] } {/theRegisters/\registers_reg[5][17] } {/theRegisters/\registers_reg[5][18] } {/theRegisters/\registers_reg[5][19] } {/theRegisters/\registers_reg[5][1] } {/theRegisters/\registers_reg[5][20] } {/theRegisters/\registers_reg[5][21] } {/theRegisters/\registers_reg[5][22] } {/theRegisters/\registers_reg[5][23] } {/theRegisters/\registers_reg[5][24] } {/theRegisters/\registers_reg[5][25] } {/theRegisters/\registers_reg[5][26] } {/theRegisters/\registers_reg[5][27] } {/theRegisters/\registers_reg[5][28] } {/theRegisters/\registers_reg[5][29] } {/theRegisters/\registers_reg[5][2] } {/theRegisters/\registers_reg[5][30] } {/theRegisters/\registers_reg[5][31] } {/theRegisters/\registers_reg[5][3] } {/theRegisters/\registers_reg[5][4] } {/theRegisters/\registers_reg[5][5] } {/theRegisters/\registers_reg[5][6] } {/theRegisters/\registers_reg[5][7] } {/theRegisters/\registers_reg[5][8] } {/theRegisters/\registers_reg[5][9] } {/theRegisters/\registers_reg[6][0] } {/theRegisters/\registers_reg[6][10] } {/theRegisters/\registers_reg[6][11] } {/theRegisters/\registers_reg[6][12] } {/theRegisters/\registers_reg[6][13] } {/theRegisters/\registers_reg[6][14] } {/theRegisters/\registers_reg[6][15] } {/theRegisters/\registers_reg[6][16] } {/theRegisters/\registers_reg[6][17] } {/theRegisters/\registers_reg[6][18] } {/theRegisters/\registers_reg[6][19] } {/theRegisters/\registers_reg[6][1] } {/theRegisters/\registers_reg[6][20] } {/theRegisters/\registers_reg[6][21] } {/theRegisters/\registers_reg[6][22] } {/theRegisters/\registers_reg[6][23] } {/theRegisters/\registers_reg[6][24] } {/theRegisters/\registers_reg[6][25] } {/theRegisters/\registers_reg[6][26] } {/theRegisters/\registers_reg[6][27] } {/theRegisters/\registers_reg[6][28] } {/theRegisters/\registers_reg[6][29] } {/theRegisters/\registers_reg[6][2] } {/theRegisters/\registers_reg[6][30] } {/theRegisters/\registers_reg[6][31] } {/theRegisters/\registers_reg[6][3] } {/theRegisters/\registers_reg[6][4] } {/theRegisters/\registers_reg[6][5] } {/theRegisters/\registers_reg[6][6] } {/theRegisters/\registers_reg[6][7] } {/theRegisters/\registers_reg[6][8] } {/theRegisters/\registers_reg[6][9] } {/theRegisters/\registers_reg[7][0] } {/theRegisters/\registers_reg[7][10] } {/theRegisters/\registers_reg[7][11] } {/theRegisters/\registers_reg[7][12] } {/theRegisters/\registers_reg[7][13] } {/theRegisters/\registers_reg[7][14] } {/theRegisters/\registers_reg[7][15] } {/theRegisters/\registers_reg[7][16] } {/theRegisters/\registers_reg[7][17] } {/theRegisters/\registers_reg[7][18] } {/theRegisters/\registers_reg[7][19] } {/theRegisters/\registers_reg[7][1] } {/theRegisters/\registers_reg[7][20] } {/theRegisters/\registers_reg[7][21] } {/theRegisters/\registers_reg[7][22] } {/theRegisters/\registers_reg[7][23] } {/theRegisters/\registers_reg[7][24] } {/theRegisters/\registers_reg[7][25] } {/theRegisters/\registers_reg[7][26] } {/theRegisters/\registers_reg[7][27] } {/theRegisters/\registers_reg[7][28] } {/theRegisters/\registers_reg[7][29] } {/theRegisters/\registers_reg[7][2] } {/theRegisters/\registers_reg[7][30] } {/theRegisters/\registers_reg[7][31] } {/theRegisters/\registers_reg[7][3] } {/theRegisters/\registers_reg[7][4] } {/theRegisters/\registers_reg[7][5] } {/theRegisters/\registers_reg[7][6] } {/theRegisters/\registers_reg[7][7] } {/theRegisters/\registers_reg[7][8] } {/theRegisters/\registers_reg[7][9] } {/theRegisters/\registers_reg[8][0] } {/theRegisters/\registers_reg[8][10] } {/theRegisters/\registers_reg[8][11] } {/theRegisters/\registers_reg[8][12] } {/theRegisters/\registers_reg[8][13] } {/theRegisters/\registers_reg[8][14] } {/theRegisters/\registers_reg[8][15] } {/theRegisters/\registers_reg[8][16] } {/theRegisters/\registers_reg[8][17] } {/theRegisters/\registers_reg[8][18] } {/theRegisters/\registers_reg[8][19] } {/theRegisters/\registers_reg[8][1] } {/theRegisters/\registers_reg[8][20] } {/theRegisters/\registers_reg[8][21] } {/theRegisters/\registers_reg[8][22] } {/theRegisters/\registers_reg[8][23] } {/theRegisters/\registers_reg[8][24] } {/theRegisters/\registers_reg[8][25] } {/theRegisters/\registers_reg[8][26] } {/theRegisters/\registers_reg[8][27] } {/theRegisters/\registers_reg[8][28] } {/theRegisters/\registers_reg[8][29] } {/theRegisters/\registers_reg[8][2] } {/theRegisters/\registers_reg[8][30] } {/theRegisters/\registers_reg[8][31] } {/theRegisters/\registers_reg[8][3] } {/theRegisters/\registers_reg[8][4] } {/theRegisters/\registers_reg[8][5] } {/theRegisters/\registers_reg[8][6] } {/theRegisters/\registers_reg[8][7] } {/theRegisters/\registers_reg[8][8] } {/theRegisters/\registers_reg[8][9] } {/theRegisters/\registers_reg[9][0] } {/theRegisters/\registers_reg[9][10] } {/theRegisters/\registers_reg[9][11] } {/theRegisters/\registers_reg[9][12] } {/theRegisters/\registers_reg[9][13] } {/theRegisters/\registers_reg[9][14] } {/theRegisters/\registers_reg[9][15] } {/theRegisters/\registers_reg[9][16] } {/theRegisters/\registers_reg[9][17] } {/theRegisters/\registers_reg[9][18] } {/theRegisters/\registers_reg[9][19] } {/theRegisters/\registers_reg[9][1] } {/theRegisters/\registers_reg[9][20] } {/theRegisters/\registers_reg[9][21] } {/theRegisters/\registers_reg[9][22] } {/theRegisters/\registers_reg[9][23] } {/theRegisters/\registers_reg[9][24] } {/theRegisters/\registers_reg[9][25] } {/theRegisters/\registers_reg[9][26] } {/theRegisters/\registers_reg[9][27] } {/theRegisters/\registers_reg[9][28] } {/theRegisters/\registers_reg[9][29] } {/theRegisters/\registers_reg[9][2] } {/theRegisters/\registers_reg[9][30] } {/theRegisters/\registers_reg[9][31] } {/theRegisters/\registers_reg[9][3] } {/theRegisters/\registers_reg[9][4] } {/theRegisters/\registers_reg[9][5] } {/theRegisters/\registers_reg[9][6] } {/theRegisters/\registers_reg[9][7] } {/theRegisters/\registers_reg[9][8] } {/theRegisters/\registers_reg[9][9] } " -si_connections "SI_4 " -so_connections "SO_4 " -chain_count 1 +// sub-command: analyze_scan_chains +// Chain allocation of 'unwrapped' mode completed: +// 4 distributed chains of size 256 +// sub-command: insert_test_logic -write_in_tsdb on +============================= +Test Logic Insertion Summary: +============================= + + Structural Data: + ---------------- + Added top-level port count: 0 + Added instance count: 8 + + Logical Data: + ------------- + Added retiming logic count: 4 + Added scan chain count (unwrapped): 4 + +// Warning: Flattened model deleted. +// +// Writing out netlist and related files in /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design +// sub-command: report_scan_chains + +=============================== +Scan Chains Created by the Tool +=============================== + + Scan mode 'unwrapped' scan chains: + ---------------------------------- + + Cluster 'scanChain_1' chains: + ----------------------------- + chain = scanChain_1 group = dummy input = /SI_1 output = /SO_1 length = 256 + + Cluster 'scanChain_2' chains: + ----------------------------- + chain = scanChain_2 group = dummy input = /SI_2 output = /SO_2 length = 256 + + Cluster 'scanChain_3' chains: + ----------------------------- + chain = scanChain_3 group = dummy input = /SI_3 output = /SO_3 length = 256 + + Cluster 'scanChain_4' chains: + ----------------------------- + chain = scanChain_4 group = dummy input = /SI_4 output = /SO_4 length = 256 + + +// sub-command: write_scan_order /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/Scan_0/cpu.scandef -use_escaping_rule Lefdef -replace +// sub-command: write_design -output_file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/Scan_0/post_scan.v -replace +// command: exit + +************************************************************************************************************************************************************************************** + TESSENT EXECUTION ENDS HERE ! +************************************************************************************************************************************************************************************** + +Dumping current design to /tmp/oasys.2483642/dft_eco/cpu +> write_db /tmp/oasys.2483642/dft_eco/cpu +info: Target library/cell information has changed that further may change timing results. [TA-159] +info: Successfully traced scan chain (scan_in: 'SI_1', scan_out: 'SO_1' with 258 elements ) [DFT-354] +info: Successfully traced scan chain (scan_in: 'SI_2', scan_out: 'SO_2' with 258 elements ) [DFT-354] +info: Successfully traced scan chain (scan_in: 'SI_3', scan_out: 'SO_3' with 258 elements ) [DFT-354] +info: Successfully traced scan chain (scan_in: 'SI_4', scan_out: 'SO_4' with 258 elements ) [DFT-354] +> write_db ./output/odb/riscv.tessent_post_scan.odb +> write_verilog ./output/riscv.tessent_post_scan.v +info: writing Verilog file './output/riscv.tessent_post_scan.v' for module 'cpu' [WRITE-100] + +----------report_power---------------- +> report_power +Report Power (instances with prefix '*' are included in total) : +-----+----------------------------------------+--------------------+---------------------+-------------------+----------------- + | Instance | Internal Power (uW)| Switching Power (uW)| Leakage Power (uW)| Total Power (uW) +-----+----------------------------------------+--------------------+---------------------+-------------------+----------------- +1 |*theMem | 4965.347656| 97.271141| 528.368530| 5590.987793 +2 |*theRegisters | 2937.885254| 65.439415| 75.000534| 3078.325195 +3 |*theDecoder | 3306.815674| 29.696104| 69.466927| 3405.978516 +4 |*thePC_i_0 | 102.036263| 0.516853| 0.818020| 103.371140 +5 |*thePC_CurrentPC_reg[31] | 6.132826| 0.115208| 0.000019| 6.248054 +6 |*thePC_CurrentPC_reg[30] | 6.132829| 0.122289| 0.000019| 6.255136 +7 |*thePC_CurrentPC_reg[29] | 6.132829| 0.122289| 0.000019| 6.255136 +8 |*thePC_CurrentPC_reg[28] | 6.132829| 0.122289| 0.000019| 6.255136 +9 |*thePC_CurrentPC_reg[27] | 6.132829| 0.122289| 0.000019| 6.255136 +10 |*thePC_CurrentPC_reg[26] | 6.132829| 0.122289| 0.000019| 6.255136 +11 |*thePC_CurrentPC_reg[25] | 6.132829| 0.122289| 0.000019| 6.255136 +12 |*thePC_CurrentPC_reg[24] | 6.132829| 0.122289| 0.000019| 6.255136 +13 |*thePC_CurrentPC_reg[23] | 6.132829| 0.122289| 0.000019| 6.255136 +14 |*thePC_CurrentPC_reg[22] | 6.132829| 0.122289| 0.000019| 6.255136 +15 |*thePC_CurrentPC_reg[21] | 6.135628| 0.207666| 0.000019| 6.343312 +16 |*thePC_CurrentPC_reg[20] | 6.132829| 0.122289| 0.000019| 6.255136 +17 |*thePC_CurrentPC_reg[19] | 6.132828| 0.121340| 0.000019| 6.254188 +18 |*thePC_CurrentPC_reg[18] | 6.132828| 0.121340| 0.000019| 6.254188 +19 |*thePC_CurrentPC_reg[17] | 6.132828| 0.121340| 0.000019| 6.254188 +20 |*thePC_CurrentPC_reg[16] | 6.132828| 0.121340| 0.000019| 6.254188 +21 |*thePC_CurrentPC_reg[15] | 6.132826| 0.115029| 0.000019| 6.247873 +22 |*thePC_CurrentPC_reg[14] | 6.132828| 0.121340| 0.000019| 6.254188 +23 |*thePC_CurrentPC_reg[13] | 6.135591| 0.206718| 0.000019| 6.342327 +24 |*thePC_CurrentPC_reg[12] | 6.132828| 0.121340| 0.000019| 6.254188 +25 |*thePC_CurrentPC_reg[11] | 6.132828| 0.120392| 0.000019| 6.253239 +26 |*thePC_CurrentPC_reg[10] | 6.132827| 0.115675| 0.000019| 6.248520 +27 |*thePC_CurrentPC_reg[9] | 6.132827| 0.115675| 0.000019| 6.248520 +28 |*thePC_CurrentPC_reg[8] | 6.132827| 0.115675| 0.000019| 6.248520 +29 |*thePC_CurrentPC_reg[7] | 6.132825| 0.109358| 0.000019| 6.242202 +30 |*thePC_CurrentPC_reg[6] | 6.132825| 0.109358| 0.000019| 6.242202 +31 |*thePC_CurrentPC_reg[5] | 6.132825| 0.109358| 0.000019| 6.242202 +32 |*thePC_CurrentPC_reg[4] | 6.132825| 0.109358| 0.000019| 6.242202 +33 |*thePC_CurrentPC_reg[3] | 6.132825| 0.109358| 0.000019| 6.242202 +34 |*thePC_CurrentPC_reg[2] | 6.136212| 0.222482| 0.000019| 6.358713 +35 |*thePC_CurrentPC_reg[1] | 6.132825| 0.110713| 0.000019| 6.243557 +36 |*thePC_CurrentPC_reg[0] | 6.132828| 0.121456| 0.000019| 6.254303 +37 |*i_0_0_0 | 3.636180| 0.005795| 0.056141| 3.698117 +38 |*i_0_0_1 | 3.630034| 0.075574| 0.049831| 3.755438 +39 |*i_0_0_2 | 3.589001| 0.005720| 0.056141| 3.650862 +40 |*i_0_0_3 | 3.579433| 0.074593| 0.049831| 3.703857 +41 |*i_0_0_4 | 4.765921| 0.005811| 0.038697| 4.810430 +42 |*i_0_0_5 | 4.765921| 0.005811| 0.038697| 4.810430 +43 |*i_0_0_6 | 4.765921| 0.005811| 0.038697| 4.810430 +44 |*i_0_0_7 | 4.765921| 0.005811| 0.038697| 4.810430 +45 |*i_0_0_8 | 4.765921| 0.005811| 0.038697| 4.810430 +46 |*i_0_0_9 | 4.765921| 0.005811| 0.038697| 4.810430 +47 |*i_0_0_10 | 4.760734| 0.005811| 0.038697| 4.805242 +48 |*i_0_0_11 | 4.760734| 0.005811| 0.038697| 4.805242 +49 |*i_0_0_12 | 4.760734| 0.005811| 0.038697| 4.805242 +50 |*i_0_0_13 | 4.760734| 0.005811| 0.038697| 4.805242 +51 |*i_0_0_14 | 4.760734| 0.005811| 0.038697| 4.805242 +52 |*i_0_0_15 | 3.589408| 0.005721| 0.056141| 3.651270 +53 |*i_0_0_16 | 3.579309| 0.074602| 0.049831| 3.703742 +54 |*i_0_0_17 | 3.589739| 0.005721| 0.056141| 3.651601 +55 |*i_0_0_18 | 3.579648| 0.074608| 0.049831| 3.704087 +56 |*i_0_0_19 | 3.590052| 0.005722| 0.056141| 3.651915 +57 |*i_0_0_20 | 3.579969| 0.074615| 0.049831| 3.704415 +58 |*i_0_0_21 | 3.590306| 0.005722| 0.056141| 3.652169 +59 |*i_0_0_22 | 3.580231| 0.074620| 0.049831| 3.704682 +60 |*i_0_0_23 | 3.590506| 0.005722| 0.056141| 3.652370 +61 |*i_0_0_24 | 3.580436| 0.074625| 0.049831| 3.704891 +62 |*i_0_0_25 | 3.590656| 0.005723| 0.056141| 3.652520 +63 |*i_0_0_26 | 3.580589| 0.074627| 0.049831| 3.705047 +64 |*i_0_0_27 | 3.590823| 0.005723| 0.056141| 3.652687 +65 |*i_0_0_28 | 3.580760| 0.074631| 0.049831| 3.705222 +66 |*i_0_0_29 | 3.590933| 0.005723| 0.056141| 3.652797 +67 |*i_0_0_30 | 3.580874| 0.074633| 0.049831| 3.705338 +68 |*i_0_0_31 | 3.590987| 0.005723| 0.056141| 3.652852 +69 |*i_0_0_32 | 3.580929| 0.074634| 0.049831| 3.705395 +70 |*i_0_0_33 | 3.591065| 0.005723| 0.056141| 3.652930 +71 |*i_0_0_34 | 3.581009| 0.074636| 0.049831| 3.705476 +72 |*i_0_0_35 | 3.591195| 0.005724| 0.056141| 3.653060 +73 |*i_0_0_36 | 3.581142| 0.074639| 0.049831| 3.705612 +74 |*i_0_0_37 | 3.591303| 0.005724| 0.056141| 3.653168 +75 |*i_0_0_38 | 3.581253| 0.074641| 0.049831| 3.705725 +76 |*i_0_0_39 | 3.591386| 0.005724| 0.056141| 3.653251 +77 |*i_0_0_40 | 3.581338| 0.074643| 0.049831| 3.705812 +78 |*i_0_0_41 | 3.591435| 0.005724| 0.056141| 3.653301 +79 |*i_0_0_42 | 3.581389| 0.074644| 0.049831| 3.705863 +80 |*i_0_0_43 | 3.591419| 0.005724| 0.056141| 3.653284 +81 |*i_0_0_44 | 3.581372| 0.074644| 0.049831| 3.705847 +82 |*i_0_0_45 | 3.591433| 0.005724| 0.056141| 3.653298 +83 |*i_0_0_46 | 3.581386| 0.074644| 0.049831| 3.705861 +84 |*i_0_0_47 | 3.591558| 0.005724| 0.056141| 3.653424 +85 |*i_0_0_48 | 3.581515| 0.074646| 0.049831| 3.705992 +86 |*i_0_0_49 | 3.591676| 0.005724| 0.056141| 3.653541 +87 |*i_0_0_50 | 3.581635| 0.074649| 0.049831| 3.706115 +88 |*i_0_0_51 | 3.591723| 0.005724| 0.056141| 3.653588 +89 |*i_0_0_52 | 3.581872| 0.074650| 0.049831| 3.706352 +90 |*i_0_0_53 | 0.270481| 0.031764| 0.181711| 0.483956 +91 |*i_0_0_54 | 8.109213| 0.417922| 0.187759| 8.714894 +92 |*i_0_0_55 | 4.662969| 0.392350| 0.167543| 5.222862 +93 |*i_0_0_56 | 4.661758| 0.392909| 0.167809| 5.222477 +94 |*i_0_0_57 | 4.661533| 0.392163| 0.167455| 5.221151 +95 |*i_0_0_58 | 4.661815| 0.393097| 0.167897| 5.222809 +96 |*i_0_0_59 | 4.661477| 0.391976| 0.167366| 5.220819 +97 |*i_0_0_60 | 4.661870| 0.393283| 0.167986| 5.223139 +98 |*i_0_0_61 | 4.263187| 0.064498| 0.029698| 4.357384 +99 |*i_0_0_62 | 4.263187| 0.064498| 0.029698| 4.357384 +100 |*i_0_0_63 | 4.263187| 0.064498| 0.029698| 4.357384 +101 |*i_0_0_64 | 4.263187| 0.064498| 0.029698| 4.357384 +102 |*i_0_0_65 | 4.263187| 0.064498| 0.029698| 4.357384 +103 |*i_0_0_66 | 892.076904| 9.773184| 0.224563| 902.074707 +104 |*tessent_persistent_cell_buf_extsi1225_i| 12.245425| 0.023904| 0.084228| 12.353557 +105 | | | | | +106 |*TOTAL | 12673.423828| 211.665421| 678.138367| 13563.228516 +-----+----------------------------------------+--------------------+---------------------+-------------------+----------------- + +----------report_path_groups---------------- +> report_path_groups +Report Path Groups: +-----+-------+------+---------+--------- + | Path |Weight|Critical |Worst + | Group | |Range(ps)|Slack(ps) +-----+-------+------+---------+--------- +1 |default| 1.000| 0.0| 18131.2 +2 |I2R | 1.000| 0.0| +3 |I2O | 1.000| 0.0| +4 |R2O | 1.000| 0.0| 36309.8 +-----+-------+------+---------+--------- + +----------report_scan_chains---------------- +> report_scan_chains +Report ScanChains: +--------+-----------+--------------+--------+-----------+-----------+--------------+------------------+--------+--------+---------+-----------+---------- + Index | Chain | ScanInstance | Length | TestClock | ClockEdge | Comp. Chains | Max Comp. Length | Lockup | ScanIn | ScanOut | Partition | ScanMode +--------+-----------+--------------+--------+-----------+-----------+--------------+------------------+--------+--------+---------+-----------+---------- + 1|scanChain_1| 258 | 256|clk_25mhz |rise | - | - | 1|SI_1 |SO_1 | - | + 2|scanChain_2| 258 | 256|clk_25mhz |rise | - | - | 1|SI_2 |SO_2 | - | + 3|scanChain_3| 258 | 256|clk_25mhz |rise | - | - | 1|SI_3 |SO_3 | - | + 4|scanChain_4| 258 | 256|clk_25mhz |rise | - | - | 1|SI_4 |SO_4 | - | +--------+-----------+--------------+--------+-----------+-----------+--------------+------------------+--------+--------+---------+-----------+---------- + +----------report_timing---------------- +> report_timing +Report for group default +-------------------------------------------------------------------------------------------------------------------------------------- +Startpoint: theMem/IRData_reg[18]/Q + (Clocked by clk_25mhz R) +Endpoint: theMem/mem_addr_reg[5]/D + (Clocked by clk_25mhz F) +Path Group: default +Data required time: 19371.2 + (Clock shift: 20000.0, minus Uncertainty: 500.0, plus Latency 0.0, minus Setup time: 128.8) +Data arrival time: 1240.0 +Slack: 18131.2 +Logic depth: 46 +-------------------------------------------------------------------------------------------------------------------------------------- + Arrival Arc Net Net Total fan- +Path Module/Cell Edge Time Delay Delay Delay Slew Load Load out Location + (ps) (ps) (ps) (ps) (ps) (ff) (ff) (#) (um,um) +-------------------------------------------------------------------------------------------------------------------------------------- +clk_25mhz {create_clock} r 0.0 0.0 0.0 0.0 0.0 100 101, 0 +theMem/IRData_reg[18]/CK->Q + DFF_X1_LVT* rr 106.0 106.0 106.0 0.0 100.0 15.2 77.1 10 175, 106 +theRegisters/i_1_0_1371/A->ZN + INV_X8_LVT rf 108.7 2.7 2.7 0.0 10.2 2.1 13.2 3 168, 158 +theRegisters/i_1_0_1339/A2->ZN + NAND3_X4_LVT fr 122.7 14.0 14.0 0.0 1.0 2.5 17.5 4 168, 158 +theRegisters/i_1_0_1321/A2->ZN + NOR2_X4_LVT* rf 141.6 19.0 19.0 0.0 12.1 29.7 130.1 32 168, 158 +theRegisters/i_1_0_722/B1->ZN + AOI22_X4_LVT* fr 186.0 44.3 44.3 0.0 10.2 0.7 23.4 1 168, 158 +theRegisters/i_1_0_721/A->ZN + INV_X8_LVT rf 188.1 2.1 2.1 0.0 10.2 0.8 3.0 1 168, 158 +theRegisters/i_1_0_718/A->ZN + AOI221_X2_LVT fr 245.4 57.3 57.3 0.0 0.6 0.9 4.4 1 168, 158 +theRegisters/i_1_0_716/A3->ZN + NAND4_X4_LVT rf 260.8 15.4 15.4 0.0 34.6 0.9 3.1 1 168, 158 +theRegisters/i_1_0_715/A->ZN + AOI221_X2_LVT fr 318.1 57.4 57.4 0.0 6.8 0.9 4.3 1 168, 158 +theRegisters/i_1_0_704/A2->ZN + NAND4_X4_LVT* rf 342.3 24.2 24.2 0.0 34.4 14.1 24.9 3 168, 158 +theDecoder/i_0_133/C2->ZN + AOI222_X4_LVT fr 452.6 110.3 110.3 0.0 10.2 0.8 23.5 1 129, 89 +theDecoder/i_0_132/A->ZN INV_X32_LVT rf 455.7 3.1 3.1 0.0 10.9 5.4 65.3 7 129, 89 +theDecoder/theALU/i_0_706/B1->ZN + OAI22_X4_LVT* fr 498.9 43.2 43.2 0.0 1.4 1.5 25.9 2 129, 89 +theDecoder/theALU/i_0_705/A->ZN + INV_X8_LVT rf 501.1 2.2 2.2 0.0 10.2 0.6 4.2 1 129, 89 +theDecoder/theALU/i_0_42/A->ZN + OAI21_X2_LVT fr 510.2 9.1 9.1 0.0 0.6 0.8 2.5 1 129, 89 +theDecoder/theALU/i_0_40/C1->ZN + AOI211_X2_LVT rf 515.8 5.6 5.6 0.0 11.6 0.8 2.9 1 129, 89 +theDecoder/theALU/i_0_39/B->ZN + AOI211_X2_LVT fr 563.3 47.4 47.4 0.0 3.3 0.9 3.0 1 129, 89 +theDecoder/theALU/i_0_38/B2->ZN + OAI222_X2_LVT rf 580.2 16.9 16.9 0.0 27.7 0.9 2.9 1 129, 89 +theDecoder/theALU/i_0_37/C2->ZN + AOI221_X2_LVT fr 624.0 43.8 43.8 0.0 8.4 0.9 4.2 1 129, 89 +theDecoder/theALU/i_0_35/B1->ZN + OAI22_X4_LVT* rf 637.9 13.9 13.9 0.0 34.0 0.7 23.4 1 129, 89 +theDecoder/theALU/i_0_34/A->ZN + INV_X8_LVT fr 642.4 4.5 4.5 0.0 10.2 0.6 4.1 1 129, 89 +theDecoder/theALU/i_0_33/A->ZN + AOI21_X4_LVT rf 645.0 2.6 2.6 0.0 2.4 0.8 3.0 1 129, 89 +theDecoder/theALU/i_0_32/C2->ZN + OAI222_X2_LVT fr 683.5 38.5 38.5 0.0 2.6 0.9 3.3 1 129, 89 +theDecoder/theALU/i_0_31/A->ZN + OAI221_X2_LVT rf 699.6 16.0 16.0 0.0 29.2 0.8 4.0 1 129, 89 +theDecoder/theALU/i_0_28/B1->ZN + AOI21_X4_LVT fr 715.0 15.5 15.5 0.0 8.2 0.8 3.0 1 129, 89 +theDecoder/theALU/i_0_27/A->ZN + AOI221_X2_LVT rf 719.3 4.2 4.2 0.0 13.5 0.9 2.9 1 129, 89 +theDecoder/theALU/i_0_26/B->ZN + AOI211_X2_LVT fr 771.5 52.2 52.2 0.0 5.3 0.8 4.6 1 129, 89 +theDecoder/theALU/i_0_25/B2->ZN + OAI22_X2_LVT rf 781.1 9.7 9.7 0.0 31.8 0.8 2.7 1 129, 89 +theDecoder/theALU/i_0_24/C2->ZN + AOI211_X2_LVT fr 815.5 34.4 34.4 0.0 4.0 0.9 3.1 1 129, 89 +theDecoder/theALU/i_0_23/A->ZN + AOI221_X2_LVT rf 821.3 5.8 5.8 0.0 27.8 0.9 3.1 1 129, 89 +theDecoder/theALU/i_0_22/A->ZN + AOI221_X2_LVT fr 874.9 53.7 53.7 0.0 5.4 0.9 3.1 1 129, 89 +theDecoder/theALU/i_0_21/A->ZN + AOI221_X2_LVT rf 881.0 6.1 6.1 0.0 31.2 0.9 3.1 1 129, 89 +theDecoder/theALU/i_0_20/C2->ZN + OAI222_X2_LVT fr 919.8 38.8 38.8 0.0 5.4 0.9 3.3 1 129, 89 +theDecoder/theALU/i_0_19/A->ZN + OAI221_X2_LVT rf 936.3 16.6 16.6 0.0 29.2 0.9 4.7 1 129, 89 +theDecoder/theALU/i_0_18/B2->ZN + AOI22_X4_LVT fr 966.6 30.3 30.3 0.0 8.6 0.8 4.4 1 129, 89 +theDecoder/theALU/i_0_17/B2->ZN + OAI21_X4_LVT rf 973.1 6.4 6.4 0.0 16.9 0.7 4.3 1 129, 89 +theDecoder/theALU/i_0_16/A->ZN + OAI21_X4_LVT fr 982.8 9.8 9.8 0.0 3.6 0.7 3.9 1 129, 89 +theDecoder/theALU/i_0_13/B1->ZN + AOI21_X4_LVT rf 988.1 5.3 5.3 0.0 12.5 0.8 4.4 1 129, 89 +theDecoder/theALU/i_0_12/A4->ZN + NOR4_X2_LVT fr 1044.5 56.5 56.5 0.0 2.9 0.8 2.8 1 129, 89 +theDecoder/theALU/i_0_0/A3->ZN + OR3_X4_LVT rr 1062.9 18.3 18.3 0.0 29.1 0.7 18.9 2 129, 89 +theDecoder/i_0_114/B->ZN XNOR2_X2_LVT rf 1069.5 6.7 6.7 0.0 9.3 0.7 4.3 1 129, 89 +theDecoder/i_0_113/B1->ZN + AOI22_X4_LVT fr 1096.0 26.5 26.5 0.0 5.1 0.8 4.4 1 129, 89 +theDecoder/i_0_111/A2->ZN + AOI22_X4_LVT rf 1102.4 6.4 6.4 0.0 16.9 0.7 4.3 1 129, 89 +theDecoder/i_0_110/A2->ZN + NAND2_X4_LVT* fr 1121.6 19.2 19.2 0.0 4.4 9.0 37.6 13 129, 89 +i_0_0_60/S->Z MUX2_X2_LVT* rf 1190.2 68.6 68.6 0.0 10.2 32.0 87.6 3 129, 89 +theMem/i_0_0_11/B2->ZN AOI22_X4_LVT* fr 1238.0 47.8 47.8 0.0 10.2 0.7 23.4 1 175, 106 +theMem/i_0_0_10/A->ZN INV_X8_LVT rf 1240.0 2.0 2.0 0.0 10.2 0.7 1.7 1 175, 106 +theMem/mem_addr_reg[5]/D DFF_X1_LVT f 1240.0 0.0 0.0 0.5 175, 106 +-------------------------------------------------------------------------------------------------------------------------------------- +Report for group I2R +Report for group I2O +Report for group R2O +-------------------------------------------------------------------------------------------------------------------------------------- +Startpoint: theMem/IRData_reg[18]/Q + (Clocked by clk_25mhz R) +Endpoint: led[7] + (Clocked by clk_25mhz R) +Path Group: R2O +Data required time: 37500.0 + (Clock shift: 40000.0, minus Uncertainty: 500.0, plus Latency 0.0, minus Out delay: 2000.0) +Data arrival time: 1190.2 +Slack: 36309.8 +Logic depth: 44 +-------------------------------------------------------------------------------------------------------------------------------------- + Arrival Arc Net Net Total fan- +Path Module/Cell Edge Time Delay Delay Delay Slew Load Load out Location + (ps) (ps) (ps) (ps) (ps) (ff) (ff) (#) (um,um) +-------------------------------------------------------------------------------------------------------------------------------------- +clk_25mhz {create_clock} r 0.0 0.0 0.0 0.0 0.0 100 101, 0 +theMem/IRData_reg[18]/CK->Q + DFF_X1_LVT* rr 106.0 106.0 106.0 0.0 100.0 15.2 77.1 10 175, 106 +theRegisters/i_1_0_1371/A->ZN + INV_X8_LVT rf 108.7 2.7 2.7 0.0 10.2 2.1 13.2 3 168, 158 +theRegisters/i_1_0_1339/A2->ZN + NAND3_X4_LVT fr 122.7 14.0 14.0 0.0 1.0 2.5 17.5 4 168, 158 +theRegisters/i_1_0_1321/A2->ZN + NOR2_X4_LVT* rf 141.6 19.0 19.0 0.0 12.1 29.7 130.1 32 168, 158 +theRegisters/i_1_0_722/B1->ZN + AOI22_X4_LVT* fr 186.0 44.3 44.3 0.0 10.2 0.7 23.4 1 168, 158 +theRegisters/i_1_0_721/A->ZN + INV_X8_LVT rf 188.1 2.1 2.1 0.0 10.2 0.8 3.0 1 168, 158 +theRegisters/i_1_0_718/A->ZN + AOI221_X2_LVT fr 245.4 57.3 57.3 0.0 0.6 0.9 4.4 1 168, 158 +theRegisters/i_1_0_716/A3->ZN + NAND4_X4_LVT rf 260.8 15.4 15.4 0.0 34.6 0.9 3.1 1 168, 158 +theRegisters/i_1_0_715/A->ZN + AOI221_X2_LVT fr 318.1 57.4 57.4 0.0 6.8 0.9 4.3 1 168, 158 +theRegisters/i_1_0_704/A2->ZN + NAND4_X4_LVT* rf 342.3 24.2 24.2 0.0 34.4 14.1 24.9 3 168, 158 +theDecoder/i_0_133/C2->ZN + AOI222_X4_LVT fr 452.6 110.3 110.3 0.0 10.2 0.8 23.5 1 129, 89 +theDecoder/i_0_132/A->ZN INV_X32_LVT rf 455.7 3.1 3.1 0.0 10.9 5.4 65.3 7 129, 89 +theDecoder/theALU/i_0_706/B1->ZN + OAI22_X4_LVT* fr 498.9 43.2 43.2 0.0 1.4 1.5 25.9 2 129, 89 +theDecoder/theALU/i_0_705/A->ZN + INV_X8_LVT rf 501.1 2.2 2.2 0.0 10.2 0.6 4.2 1 129, 89 +theDecoder/theALU/i_0_42/A->ZN + OAI21_X2_LVT fr 510.2 9.1 9.1 0.0 0.6 0.8 2.5 1 129, 89 +theDecoder/theALU/i_0_40/C1->ZN + AOI211_X2_LVT rf 515.8 5.6 5.6 0.0 11.6 0.8 2.9 1 129, 89 +theDecoder/theALU/i_0_39/B->ZN + AOI211_X2_LVT fr 563.3 47.4 47.4 0.0 3.3 0.9 3.0 1 129, 89 +theDecoder/theALU/i_0_38/B2->ZN + OAI222_X2_LVT rf 580.2 16.9 16.9 0.0 27.7 0.9 2.9 1 129, 89 +theDecoder/theALU/i_0_37/C2->ZN + AOI221_X2_LVT fr 624.0 43.8 43.8 0.0 8.4 0.9 4.2 1 129, 89 +theDecoder/theALU/i_0_35/B1->ZN + OAI22_X4_LVT* rf 637.9 13.9 13.9 0.0 34.0 0.7 23.4 1 129, 89 +theDecoder/theALU/i_0_34/A->ZN + INV_X8_LVT fr 642.4 4.5 4.5 0.0 10.2 0.6 4.1 1 129, 89 +theDecoder/theALU/i_0_33/A->ZN + AOI21_X4_LVT rf 645.0 2.6 2.6 0.0 2.4 0.8 3.0 1 129, 89 +theDecoder/theALU/i_0_32/C2->ZN + OAI222_X2_LVT fr 683.5 38.5 38.5 0.0 2.6 0.9 3.3 1 129, 89 +theDecoder/theALU/i_0_31/A->ZN + OAI221_X2_LVT rf 699.6 16.0 16.0 0.0 29.2 0.8 4.0 1 129, 89 +theDecoder/theALU/i_0_28/B1->ZN + AOI21_X4_LVT fr 715.0 15.5 15.5 0.0 8.2 0.8 3.0 1 129, 89 +theDecoder/theALU/i_0_27/A->ZN + AOI221_X2_LVT rf 719.3 4.2 4.2 0.0 13.5 0.9 2.9 1 129, 89 +theDecoder/theALU/i_0_26/B->ZN + AOI211_X2_LVT fr 771.5 52.2 52.2 0.0 5.3 0.8 4.6 1 129, 89 +theDecoder/theALU/i_0_25/B2->ZN + OAI22_X2_LVT rf 781.1 9.7 9.7 0.0 31.8 0.8 2.7 1 129, 89 +theDecoder/theALU/i_0_24/C2->ZN + AOI211_X2_LVT fr 815.5 34.4 34.4 0.0 4.0 0.9 3.1 1 129, 89 +theDecoder/theALU/i_0_23/A->ZN + AOI221_X2_LVT rf 821.3 5.8 5.8 0.0 27.8 0.9 3.1 1 129, 89 +theDecoder/theALU/i_0_22/A->ZN + AOI221_X2_LVT fr 874.9 53.7 53.7 0.0 5.4 0.9 3.1 1 129, 89 +theDecoder/theALU/i_0_21/A->ZN + AOI221_X2_LVT rf 881.0 6.1 6.1 0.0 31.2 0.9 3.1 1 129, 89 +theDecoder/theALU/i_0_20/C2->ZN + OAI222_X2_LVT fr 919.8 38.8 38.8 0.0 5.4 0.9 3.3 1 129, 89 +theDecoder/theALU/i_0_19/A->ZN + OAI221_X2_LVT rf 936.3 16.6 16.6 0.0 29.2 0.9 4.7 1 129, 89 +theDecoder/theALU/i_0_18/B2->ZN + AOI22_X4_LVT fr 966.6 30.3 30.3 0.0 8.6 0.8 4.4 1 129, 89 +theDecoder/theALU/i_0_17/B2->ZN + OAI21_X4_LVT rf 973.1 6.4 6.4 0.0 16.9 0.7 4.3 1 129, 89 +theDecoder/theALU/i_0_16/A->ZN + OAI21_X4_LVT fr 982.8 9.8 9.8 0.0 3.6 0.7 3.9 1 129, 89 +theDecoder/theALU/i_0_13/B1->ZN + AOI21_X4_LVT rf 988.1 5.3 5.3 0.0 12.5 0.8 4.4 1 129, 89 +theDecoder/theALU/i_0_12/A4->ZN + NOR4_X2_LVT fr 1044.5 56.5 56.5 0.0 2.9 0.8 2.8 1 129, 89 +theDecoder/theALU/i_0_0/A3->ZN + OR3_X4_LVT rr 1062.9 18.3 18.3 0.0 29.1 0.7 18.9 2 129, 89 +theDecoder/i_0_114/B->ZN XNOR2_X2_LVT rf 1069.5 6.7 6.7 0.0 9.3 0.7 4.3 1 129, 89 +theDecoder/i_0_113/B1->ZN + AOI22_X4_LVT fr 1096.0 26.5 26.5 0.0 5.1 0.8 4.4 1 129, 89 +theDecoder/i_0_111/A2->ZN + AOI22_X4_LVT rf 1102.4 6.4 6.4 0.0 16.9 0.7 4.3 1 129, 89 +theDecoder/i_0_110/A2->ZN + NAND2_X4_LVT* fr 1121.6 19.2 19.2 0.0 4.4 9.0 37.6 13 129, 89 +i_0_0_60/S->Z MUX2_X2_LVT* rf 1190.2 68.6 68.6 0.0 10.2 32.0 87.6 3 129, 89 +led[7] f 1190.2 0.0 0.0 10.2 119, 257 +-------------------------------------------------------------------------------------------------------------------------------------- + +------------------------------------- + + Tessent DFT complete + +------------------------------------- + diff --git a/oasys.log.01 b/oasys.log.01 new file mode 100644 index 0000000..d3b058d --- /dev/null +++ b/oasys.log.01 @@ -0,0 +1,1572 @@ +******************************************************************* +* Oasys-RTL™ - release 2022.2.R1 * +* * +* This material contains trade secrets or otherwise confidential * +* information owned by Siemens Industry Software Inc. or its * +* affiliates (collectively, "SISW"), or its licensors. Access to * +* and use of this information is strictly limited as set forth * +* in the Customer’s applicable agreements with SISW. * +* * +* Unpublished work. © 2023 Siemens * +* * +* Program : ../bin/Linux-x86_64-O/oasysGui * +* Version : 22.2-p002 * +* Date : Mon Jan 16 21:36:23 PST 2023 * +* Build : releases/22.2-54756.0-CentOS_6.5-O * +******************************************************************* + config sdc-v1.7-cpd cli cmd explore mxdb o2n fp rta mpg-m-w dft +loading: oa2tessent-d ctl verify edit bt upf-c aos conc ipc-l vcd o2pp prot int oa2ap +checked out license: psyncore + + date : Fri May 29 09:08:47 CEST 2026 + ppid/pid : 2567124/2567134 + hostname : efiapps0.ads1.fh-nuernberg.de + arch/os : x86_64/Linux-4.18.0-553.123.1.el8_10.x86_64 + install : /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1 + currdir : /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock + logfile : /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.log.01 + tmpdir : /tmp/oasys.2567124/ +> source /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/tcl/library/history.tcl +> source scripts_risc_v/1_read_design.tcl +> source scripts_risc_v/init_design.tcl +> config_shell -echo true +> config_report timing -format {cell edge arrival delay arc_delay net_delay slew net_load load fanout location power_domain} +> source scripts_risc_v/demo_chip_design_files.tcl + +----------------------------- + +Done setting design variables + +----------------------------- + +> read_db ./libs/nangate_mvt.odb +info: Reading '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/nangate_mvt.odb' [UFILE-107] + starting at 00:00:00(cpu)/0:00:39(wall) 94MB(vsz)/470MB(peak) +extracting odb ... finished at 00:00:00(cpu)/0:00:39(wall) 94MB(vsz)/470MB(peak) + Write Date : Mon, 21 Jun 2021 13:47:25 -0700 + Host : orw-ericc-r78 (64bit) + Tool Version : 21.1-p004 (60,9-71,11) + Tool Date : Fri Jun 11 12:44:10 PDT 2021 + Tool Build : 52545.0-O + Design Name : + Comment : +loading environment ... finished at 00:00:00(cpu)/0:00:39(wall) 94MB(vsz)/470MB(peak) +loading libraries ... finished at 00:00:01(cpu)/0:00:39(wall) 107MB(vsz)/476MB(peak) +all done +> create_threshold_voltage_group HVT -lib_cells {NangateOpenCellLibrary_45nm_HVT_0p85/AND2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND2_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND3_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND3_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND3_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND4_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND4_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND4_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/ANTENNA_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI21_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI21_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI21_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI22_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI22_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI22_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI211_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI211_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI211_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI221_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI221_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI221_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI222_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI222_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI222_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X16_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X32_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKBUF_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKBUF_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKBUF_X3_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFRS_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFRS_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFR_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFR_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFS_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFS_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFF_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFF_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLH_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLH_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLL_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLL_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FA_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X16_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X32_HVT NangateOpenCellLibrary_45nm_HVT_0p85/HA_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X16_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X32_HVT NangateOpenCellLibrary_45nm_HVT_0p85/LOGIC0_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/LOGIC1_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/MUX2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/MUX2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND2_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND3_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND3_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND3_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND4_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND4_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND4_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR2_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR3_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR3_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR3_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR4_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR4_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR4_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI21_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI21_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI21_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI22_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI22_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI22_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI33_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI211_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI211_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI211_X4_HVT ...(34 more)} +> create_threshold_voltage_group SVT -lib_cells {NangateOpenCellLibrary_45nm_SVT_0p85/AND2_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND2_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND2_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND3_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND3_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND3_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND4_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND4_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND4_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/ANTENNA_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI21_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI21_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI21_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI22_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI22_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI22_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI211_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI211_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI211_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI221_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI221_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI221_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI222_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI222_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI222_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X8_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X16_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X32_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKBUF_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKBUF_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKBUF_X3_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATETST_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATETST_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATETST_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATETST_X8_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATE_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATE_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATE_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATE_X8_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFFRS_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFFRS_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFFR_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFFR_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFFS_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFF_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFF_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DLH_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DLH_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DLL_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DLL_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FA_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X8_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X16_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X32_SVT NangateOpenCellLibrary_45nm_SVT_0p85/HA_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X8_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X16_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X32_SVT NangateOpenCellLibrary_45nm_SVT_0p85/LOGIC0_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/LOGIC1_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/MUX2_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/MUX2_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND2_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND2_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND2_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND3_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND3_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND3_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND4_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND4_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND4_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR2_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR2_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR2_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR3_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR3_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR3_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR4_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR4_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR4_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI21_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI21_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI21_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI22_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI22_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI22_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI33_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI211_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI211_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI211_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI221_X1_SVT ...(34 more)} +> create_threshold_voltage_group LVT -lib_cells {NangateOpenCellLibrary_45nm_LVT_0p85/AND2_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND2_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND2_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND3_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND3_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND3_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND4_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND4_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND4_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/ANTENNA_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI21_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI21_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI21_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI22_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI22_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI22_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI211_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI211_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI211_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI221_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI221_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI221_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI222_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI222_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI222_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/BUF_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/BUF_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/BUF_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/BUF_X8_LVT NangateOpenCellLibrary_45nm_LVT_0p85/BUF_X16_LVT NangateOpenCellLibrary_45nm_LVT_0p85/BUF_X32_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKBUF_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKBUF_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKBUF_X3_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATETST_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATETST_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATETST_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATETST_X8_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATE_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATE_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATE_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATE_X8_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFFRS_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFFRS_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFFR_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFFR_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFFS_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFFS_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFF_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFF_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DLH_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DLH_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DLL_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DLL_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/FA_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/FILLCELL_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/FILLCELL_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/FILLCELL_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/FILLCELL_X8_LVT NangateOpenCellLibrary_45nm_LVT_0p85/FILLCELL_X16_LVT NangateOpenCellLibrary_45nm_LVT_0p85/FILLCELL_X32_LVT NangateOpenCellLibrary_45nm_LVT_0p85/HA_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/INV_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/INV_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/INV_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/INV_X8_LVT NangateOpenCellLibrary_45nm_LVT_0p85/INV_X16_LVT NangateOpenCellLibrary_45nm_LVT_0p85/INV_X32_LVT NangateOpenCellLibrary_45nm_LVT_0p85/LOGIC0_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/LOGIC1_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/MUX2_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/MUX2_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND2_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND2_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND2_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND3_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND3_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND3_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND4_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND4_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND4_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR2_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR2_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR2_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR3_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR3_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR3_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR4_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR4_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR4_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI21_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI21_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI21_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI22_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI22_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI22_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI33_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI211_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI211_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI211_X4_LVT ...(34 more)} +> report_operating_conditions +Report Operating conditions: +-----+---------------+--------+-------------+------------------------------------+--------+--------+----------- + |Name |Default?|Type |Library |Process |Voltage |Temperature +-----+---------------+--------+-------------+------------------------------------+--------+--------+----------- +1 |typical | |standard cell|IO |1.000000|1.100000| 27.000000 +2 |TYP | |standard cell|PLL_TYP |1.000000|0.900000| 25.000000 +3 |typical | |standard cell|MemGen_16_10 |1.000000|1.800000| 25.000000 +4 |worst_low_0p85V| |standard cell|NangateOpenCellLibrary_45nm_HVT_0p85|1.000000|0.850000| -40.000000 +5 |worst_low | |standard cell|NangateOpenCellLibrary_45nm_HVT |1.000000|0.950000| -40.000000 +-----+---------------+--------+-------------+------------------------------------+--------+--------+----------- +> config_tolerance -blackbox true -connection_mismatch true -missing_physical_library true -continue_on_error false +> read_verilog -sv {alu.sv cpu.sv decoder.sv MemGen_32_11.sv main_mem.sv pc.sv reg_file.sv} -include ./riscv_rtl/hw/rtl +info: File 'alu.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/./riscv_rtl/hw/rtl/alu.sv' using search_path variable. [CMD-126] +info: File 'cpu.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/./riscv_rtl/hw/rtl/cpu.sv' using search_path variable. [CMD-126] +info: File 'decoder.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/./riscv_rtl/hw/rtl/decoder.sv' using search_path variable. [CMD-126] +info: File 'MemGen_32_11.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/./riscv_rtl/hw/rtl/MemGen_32_11.sv' using search_path variable. [CMD-126] +info: File 'main_mem.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/./riscv_rtl/hw/rtl/main_mem.sv' using search_path variable. [CMD-126] +info: File 'pc.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/./riscv_rtl/hw/rtl/pc.sv' using search_path variable. [CMD-126] +info: File 'reg_file.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/./riscv_rtl/hw/rtl/reg_file.sv' using search_path variable. [CMD-126] +> set_max_route_layer 10 +Top-most available layer for routing set to metal10 +> set_dont_use {IO/PADBID IO/PADCLK PLL_TYP/PLL MemGen_16_10/MemGen_16_10 NangateOpenCellLibrary_45nm_HVT_0p85/AND2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND2_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND3_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND3_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND3_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND4_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND4_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND4_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/ANTENNA_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI21_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI21_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI21_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI22_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI22_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI22_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI211_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI211_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI211_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI221_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI221_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI221_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI222_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI222_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI222_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X16_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X32_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKBUF_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKBUF_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKBUF_X3_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFRS_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFRS_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFR_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFR_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFS_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFS_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFF_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFF_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLH_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLH_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLL_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLL_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FA_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X16_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X32_HVT NangateOpenCellLibrary_45nm_HVT_0p85/HA_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X16_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X32_HVT NangateOpenCellLibrary_45nm_HVT_0p85/LOGIC0_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/LOGIC1_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/MUX2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/MUX2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND2_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND3_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND3_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND3_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND4_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND4_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND4_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR2_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR3_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR3_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR3_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR4_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR4_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR4_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI21_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI21_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI21_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI22_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI22_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI22_X4_HVT ...(306 more)} false + +----------------------------- + +Done preparing design for synthesis + +----------------------------- + +> source scripts_risc_v/2_synthesize_optimize.tcl +> synthesize -module cpu -map_to_scan +starting synthesize at 00:00:01(cpu)/0:00:48(wall) 112MB(vsz)/480MB(peak) +warning: skipping cell ANTENNA_X1_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell FILLCELL_X1_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell FILLCELL_X2_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell FILLCELL_X4_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell FILLCELL_X8_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell FILLCELL_X16_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell FILLCELL_X32_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell LOGIC0_X1_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell LOGIC1_X1_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell ANTENNA_X1_HVT in the library since it does not have delay arcs [NL-215] +-------> Message [NL-215] suppressed 44 times +info: clock-gating cell for posedge FFs = CLKGATE_X1_LVT in target library 'default' [POWER-112] +info: no clock-gating cell found in target library 'default' for negedge FFs for the given specification [POWER-113] +info: clock_gating minimum_width = 4, maximum_fanout = 2147483647, num_stages = 2147483647, sequential_cell = (null), control_port = (null), control_point = none, observability = no, use_discrete_cells = no, create_multi_stage = no, merge_multi_stage = no, exclude_instantiated_clock_gates = no, log = (null), allow_clock_inversion = no [POWER-111] +info: synthesizing module 'cpu' (depth 1) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/cpu.sv:17)[7]) [VLOG-400] +info: synthesizing module 'decoder' (depth 2) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/decoder.sv:17)[7]) [VLOG-400] +info: synthesizing module 'alu' (depth 3) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/alu.sv:16)[7]) [VLOG-400] +info: done synthesizing module 'alu' (depth 3) (1#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/alu.sv:16)[7]) [VLOG-401] +info: done synthesizing module 'decoder' (depth 2) (2#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/decoder.sv:17)[7]) [VLOG-401] +info: synthesizing module 'reg_file' (depth 2) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/reg_file.sv:15)[7]) [VLOG-400] +warning: target library has multiple operating conditions defined, but no default has been set. Assuming default voltage 0.85V, temperature -40.00 and process 1.00 [LIB-218] +info: done synthesizing module 'reg_file' (depth 2) (3#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/reg_file.sv:15)[7]) [VLOG-401] +info: synthesizing module 'pc' (depth 2) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/pc.sv:16)[7]) [VLOG-400] +info: done synthesizing module 'pc' (depth 2) (4#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/pc.sv:16)[7]) [VLOG-401] +info: synthesizing module 'main_mem' (depth 2) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:18)[7]) [VLOG-400] +info: synthesizing module 'MemGen_32_11' (depth 3) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/MemGen_32_11.sv:1)[7]) [VLOG-400] +info: done synthesizing module 'MemGen_32_11' (depth 3) (5#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/MemGen_32_11.sv:1)[7]) [VLOG-401] +warning: always_comb on 'DRData' did not result in combinational logic ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:110)[8], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:113)[16], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:114)[16], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:118)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:119)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:120)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:121)[17]) [SYN-112] +warning: inferring latch for variable 'DRData' ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:110)[8], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:113)[16], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:114)[16], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:118)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:119)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:120)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:121)[17]) [VLOG-566] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +-------> Message [POWER-102] suppressed 22 times +info: done synthesizing module 'main_mem' (depth 2) (6#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:18)[7]) [VLOG-401] +info: done synthesizing module 'cpu' (depth 1) (7#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/cpu.sv:17)[7]) [VLOG-401] +finished synthesize at 00:00:02(cpu)/0:00:50(wall) 162MB(vsz)/532MB(peak) +> set_route_layer_max_usage metal2 0.5 +> set_route_layer_max_usage metal3 0.8 +> set_route_layer_max_usage metal6 0.8 +> write_db ./output/odb/riscv_chip.syn.odb +info: design 'cpu' has no physical info [WRITE-120] +warning: WrSdc.. design 'cpu' has no timing constraints [TA-118] +> read_sdc -verbose ./constraints/riscv.sdc +> create_clock -name clk_25mhz -period 40.000 -waveform { 0 20 } clk_25mhz +> set_clock_uncertainty -setup 0.5 clk_25mhz +> set_clock_uncertainty -hold 0.2 clk_25mhz +> set_clock_transition 0.1 clk_25mhz +> set_input_delay -clock clk_25mhz -max 2.0 { btn[6] btn[5] btn[4] btn[3] btn[2] btn[1] btn[0] } +> set_input_delay -clock clk_25mhz -min 0.5 { btn[6] btn[5] btn[4] btn[3] btn[2] btn[1] btn[0] } +> set_output_delay -clock clk_25mhz -max 2.0 { led[7] led[6] led[5] led[4] led[3] led[2] led[1] led[0] } +> set_output_delay -clock clk_25mhz -min 0.5 { led[7] led[6] led[5] led[4] led[3] led[2] led[1] led[0] } +> set_false_path -from btn[0] +# set_false_path -from btn[0] +> set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 { btn[6] btn[5] btn[4] btn[3] btn[2] btn[1] btn[0] } +> set_load 0.05 { led[7] led[6] led[5] led[4] led[3] led[2] led[1] led[0] } +> current_design +> set_max_fanout 20 cpu +> current_design +> set_max_transition 0.5 cpu +info: 'set_max_fanout' command ignored 1 time(s) [SDC-148] +info: 'set_max_transition' command ignored 1 time(s) [SDC-150] +> report_design_metrics +Report Physical info: +------------------------+--------+-----------+------------ + | |Area (squm)|Leakage (uW) +------------------------+--------+-----------+------------ +Design Name |cpu | | + Total Instances | 7261| 60155| 625.778 + Macros | 4| 46249| 518.216 + Pads | 0| 0| 0.000 + Phys | 0| 0| 0.000 + Blackboxes | 0| 0| 0.000 + Cells | 7257| 13906| 107.562 + Buffers | 0| 0| 0.000 + Inverters | 640| 340| 4.488 + Clock-Gates | 31| 107| 0.667 + Combinational | 5423| 6454| 51.129 + Latches | 32| 85| 0.602 + FlipFlops | 1131| 6919| 50.677 + Single-Bit FF | 1131| 6919| 50.677 + Multi-Bit FF | 0| 0| 0.000 + Clock-Gated | 992| | + Bits | 1131| 6919| 50.677 + Load-Enabled | 0| | + Clock-Gated | 992| | + Tristate Pin Count | 0| | +Physical Info |Unplaced| | + Chip Size (mm x mm) | | 0| + Fixed Cell Area | | 0| + Phys Only | 0| 0| + Placeable Area | | 0| + Movable Cell Area | | 60155| + Utilization (%) | | | + Chip Utilization (%) | | | + Total Wire Length (mm)| 0.000| | + Longest Wire (mm) | | | + Average Wire (mm) | | | +------------------------+--------+-----------+------------ +> check_timing +Report Check Timing: +-----+------------------------------+------+--------+------+----------------------------------------------- + |Item |Errors|Warnings|Status|Description +-----+------------------------------+------+--------+------+----------------------------------------------- +1 |no_clock_defined | 0| 0|Passed|No clock is defined in the design +2 |invalid_generated_clock | 0| 0|Passed|Generated clock is not sourced by a valid clock +3 |unconstrained_IO | 0| 0|Passed|Unconstrained IO pin +4 |unexpected_assertion | 0| 0|Passed|Found unexpected timing assertion +5 |trigger_pin_without_required | 0| 32|Passed|Trigger pin does not get required data +6 |setup_pin_without_data | 0| 0|Passed|Setup pin does not get arriving data +7 |setup_pin_with_clock | 0| 0|Passed|Setup pin has clock signal arriving +8 |clock_pin_with_multiple_clocks| 0| 0|Passed|Clock pin has multiple clock signals +9 |clock_pin_without_clock | 0| 1|Passed|Clock pin does not have clock signal +10 |clock_pin_with_data | 0| 1|Passed|Clock pin has data signal arriving +-----+------------------------------+------+--------+------+----------------------------------------------- +> all_inputs +> group_path -name I2R -from { btn[6] btn[5] btn[4] btn[3] btn[2] btn[1] btn[0] clk_25mhz } +# group_path -from {btn[6]} {btn[5]} {btn[4]} {btn[3]} {btn[2]} {btn[1]} {btn[0]} clk_25mhz +> all_inputs +> all_outputs +> group_path -name I2O -from { btn[6] btn[5] btn[4] btn[3] btn[2] btn[1] btn[0] clk_25mhz } -to { led[7] led[6] led[5] led[4] led[3] led[2] led[1] led[0] } +# group_path -from {btn[6]} {btn[5]} {btn[4]} {btn[3]} {btn[2]} {btn[1]} {btn[0]} clk_25mhz -to {led[7]} {led[6]} {led[5]} {led[4]} {led[3]} {led[2]} {led[1]} {led[0]} +> all_outputs +> group_path -name R2O -to { led[7] led[6] led[5] led[4] led[3] led[2] led[1] led[0] } +# group_path -to {led[7]} {led[6]} {led[5]} {led[4]} {led[3]} {led[2]} {led[1]} {led[0]} +> report_path_groups +Report Path Groups: +-----+-------+------+---------+--------- + | Path |Weight|Critical |Worst + | Group | |Range(ps)|Slack(ps) +-----+-------+------+---------+--------- +1 |default| 1.000| 0.0| 17832.1 +2 |I2R | 1.000| 0.0| +3 |I2O | 1.000| 0.0| +4 |R2O | 1.000| 0.0| 36153.7 +-----+-------+------+---------+--------- +> optimize -virtual +starting optimize at 00:00:03(cpu)/0:00:51(wall) 172MB(vsz)/532MB(peak) +info: mapped 0 flop(s) to scan cells, excluded 0 is_dont_scan flop(s) and 0 is_dont_touch flop(s) +Log file for child PID=2567207: /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.etc.01/oasys.w1.01.log +Log file for child PID=2567213: /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.etc.01/oasys.w2.01.log +Log file for child PID=2567220: /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.etc.01/oasys.w3.01.log +Log file for child PID=2567225: /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.etc.01/oasys.w4.01.log +info: optimized '' area changed 0.0squm (x1), total 13904.4squm (#1, 0 secs) +info: dissolving instance 'thePC' of module 'pc' in module 'cpu__GC0' [NL-146] +info: optimized 'cpu__GC0' area changed -1457.9squm (x1), total 12446.4squm (#2) +info: optimized 'reg_file__GB1' area changed -841.1squm (x1), total 11605.3squm (#3) +info: optimized 'reg_file__always' area changed -83.5squm (x1), total 11521.8squm (#4) +info: optimized 'main_mem__GC0' area changed -90.4squm (x1), total 11431.3squm (#5) +info: optimized 'MemGen_32_11__block' area changed -2.4squm (x1), total 11429.0squm (#6) +info: optimized '' area changed 0.0squm (x1), total 11429.0squm (#7, 0 secs) +info: optimized 'cpu__GC0' area changed 0.0squm (x1), total 11429.0squm (#8) +info: optimized 'MemGen_32_11__block' area changed 0.0squm (x1), total 11429.0squm (#9) +info: optimized '' area changed 0.0squm (x1), total 11429.0squm (#10, 0 secs) +done optimizing area at 00:00:15(cpu)/0:00:58(wall) 169MB(vsz)/566MB(peak) +Splitting congested rtl-partitions +info: Target library/cell information has changed that further may change timing results. [TA-159] +info: optimizing design 'cpu' - propagating constants +info: optimized '' area changed 0.0squm (x1), total 11429.0squm (#1, 1 secs) +info: set slack mode to optimize shift +info: resetting all path groups +info: activated path group default @ 18015.8ps +info: suspended path group I2R @ ps +info: suspended path group I2O @ ps +info: activated path group R2O @ 36338.3ps +info: finished path group default @ 18015.8ps +info: finished path group R2O @ 36338.3ps +info: reactivating path groups +info: reactivated path group default @ 18015.8ps +info: reactivated path group R2O @ 36338.3ps +info: finished path group default @ 18015.8ps +info: finished path group R2O @ 36338.3ps +info: set slack mode to normal +info: done with all path groups +info: restore all path groups +info: starting area recovery on module cpu +info: optimized 'cpu__GC0' area recovered 0.00squm (x1), total 0.00squm (1#5), 0.04 secs +info: optimized 'main_mem__GC0' area recovered 0.00squm (x1), total 0.00squm (2#5), 0.04 secs +info: optimized 'MemGen_32_11__block' area recovered 0.00squm (x1), total 0.00squm (3#5), 0.00 secs +info: optimized 'reg_file__always' area recovered 0.00squm (x1), total 0.00squm (4#5), 0.01 secs +info: optimized 'reg_file__GB1' area recovered 0.00squm (x1), total 0.00squm (5#5), 0.03 secs +info: area recovery done, total area reduction: 0.00squm (0.00%), final slack: 18015.8ps (delta: 0.0ps) (0 secs) +done optimizing virtual at 00:00:16(cpu)/0:00:59(wall) 186MB(vsz)/566MB(peak) +finished optimize at 00:00:16(cpu)/0:00:59(wall) 186MB(vsz)/566MB(peak) +> write_db ./output/odb/riscv_chip.virtual_opt.odb +> report_timing +Report for group default +-------------------------------------------------------------------------------------------------------------------------------------- +Startpoint: theMem/IRData_reg[18]/Q + (Clocked by clk_25mhz R) +Endpoint: theMem/mem_addr_reg[5]/D + (Clocked by clk_25mhz F) +Path Group: default +Data required time: 19227.4 + (Clock shift: 20000.0, minus Uncertainty: 500.0, plus Latency 0.0, minus Setup time: 272.6) +Data arrival time: 1211.5 +Slack: 18015.8 +Logic depth: 46 +-------------------------------------------------------------------------------------------------------------------------------------- + Arrival Arc Net Net Total fan- +Path Module/Cell Edge Time Delay Delay Delay Slew Load Load out Location + (ps) (ps) (ps) (ps) (ps) (ff) (ff) (#) (um,um) +-------------------------------------------------------------------------------------------------------------------------------------- +clk_25mhz {create_clock} r 0.0 0.0 0.0 0.0 0.0 100 +theMem/IRData_reg[18]/CK->Q + SDFF_X1_LVT* rr 84.9 84.9 84.9 0.0 100.0 10.6 73.4 11 +theRegisters/i_1_0_1371/A->ZN + INV_X8_LVT rf 87.6 2.7 2.7 0.0 10.2 2.1 13.2 3 +theRegisters/i_1_0_1339/A2->ZN + NAND3_X4_LVT fr 101.6 14.0 14.0 0.0 1.0 2.5 17.5 4 +theRegisters/i_1_0_1321/A2->ZN + NOR2_X4_LVT* rf 120.6 19.0 19.0 0.0 12.1 29.7 130.1 32 +theRegisters/i_1_0_722/B1->ZN + AOI22_X4_LVT* fr 164.9 44.3 44.3 0.0 10.2 0.7 23.4 1 +theRegisters/i_1_0_721/A->ZN + INV_X8_LVT rf 167.0 2.1 2.1 0.0 10.2 0.8 3.0 1 +theRegisters/i_1_0_718/A->ZN + AOI221_X2_LVT fr 224.3 57.3 57.3 0.0 0.6 0.9 4.4 1 +theRegisters/i_1_0_716/A3->ZN + NAND4_X4_LVT rf 239.7 15.4 15.4 0.0 34.6 0.9 3.1 1 +theRegisters/i_1_0_715/A->ZN + AOI221_X2_LVT fr 297.1 57.4 57.4 0.0 6.8 0.9 4.3 1 +theRegisters/i_1_0_704/A2->ZN + NAND4_X4_LVT rf 317.6 20.5 20.5 0.0 34.4 5.9 16.7 3 +theDecoder/i_0_133/C2->ZN + AOI222_X4_LVT fr 428.0 110.5 110.5 0.0 12.2 0.8 23.5 1 +theDecoder/i_0_132/A->ZN INV_X32_LVT rf 431.2 3.1 3.1 0.0 10.9 5.4 65.3 7 +theDecoder/theALU/i_0_706/B1->ZN + OAI22_X4_LVT* fr 474.4 43.2 43.2 0.0 1.4 1.5 25.9 2 +theDecoder/theALU/i_0_705/A->ZN + INV_X8_LVT rf 476.5 2.2 2.2 0.0 10.2 0.6 4.2 1 +theDecoder/theALU/i_0_42/A->ZN + OAI21_X2_LVT fr 485.6 9.1 9.1 0.0 0.6 0.8 2.5 1 +theDecoder/theALU/i_0_40/C1->ZN + AOI211_X2_LVT rf 491.3 5.6 5.6 0.0 11.6 0.8 2.9 1 +theDecoder/theALU/i_0_39/B->ZN + AOI211_X2_LVT fr 538.7 47.4 47.4 0.0 3.3 0.9 3.0 1 +theDecoder/theALU/i_0_38/B2->ZN + OAI222_X2_LVT rf 555.6 16.9 16.9 0.0 27.7 0.9 2.9 1 +theDecoder/theALU/i_0_37/C2->ZN + AOI221_X2_LVT fr 599.5 43.8 43.8 0.0 8.4 0.9 4.2 1 +theDecoder/theALU/i_0_35/B1->ZN + OAI22_X4_LVT* rf 613.4 13.9 13.9 0.0 34.0 0.7 23.4 1 +theDecoder/theALU/i_0_34/A->ZN + INV_X8_LVT fr 617.9 4.5 4.5 0.0 10.2 0.6 4.1 1 +theDecoder/theALU/i_0_33/A->ZN + AOI21_X4_LVT rf 620.5 2.6 2.6 0.0 2.4 0.8 3.0 1 +theDecoder/theALU/i_0_32/C2->ZN + OAI222_X2_LVT fr 659.0 38.5 38.5 0.0 2.6 0.9 3.3 1 +theDecoder/theALU/i_0_31/A->ZN + OAI221_X2_LVT rf 675.0 16.0 16.0 0.0 29.2 0.8 4.0 1 +theDecoder/theALU/i_0_28/B1->ZN + AOI21_X4_LVT fr 690.5 15.5 15.5 0.0 8.2 0.8 3.0 1 +theDecoder/theALU/i_0_27/A->ZN + AOI221_X2_LVT rf 694.7 4.2 4.2 0.0 13.5 0.9 2.9 1 +theDecoder/theALU/i_0_26/B->ZN + AOI211_X2_LVT fr 746.9 52.2 52.2 0.0 5.3 0.8 4.6 1 +theDecoder/theALU/i_0_25/B2->ZN + OAI22_X2_LVT rf 756.6 9.7 9.7 0.0 31.8 0.8 2.7 1 +theDecoder/theALU/i_0_24/C2->ZN + AOI211_X2_LVT fr 791.0 34.4 34.4 0.0 4.0 0.9 3.1 1 +theDecoder/theALU/i_0_23/A->ZN + AOI221_X2_LVT rf 796.7 5.8 5.8 0.0 27.8 0.9 3.1 1 +theDecoder/theALU/i_0_22/A->ZN + AOI221_X2_LVT fr 850.4 53.7 53.7 0.0 5.4 0.9 3.1 1 +theDecoder/theALU/i_0_21/A->ZN + AOI221_X2_LVT rf 856.5 6.1 6.1 0.0 31.2 0.9 3.1 1 +theDecoder/theALU/i_0_20/C2->ZN + OAI222_X2_LVT fr 895.2 38.8 38.8 0.0 5.4 0.9 3.3 1 +theDecoder/theALU/i_0_19/A->ZN + OAI221_X2_LVT rf 911.8 16.6 16.6 0.0 29.2 0.9 4.7 1 +theDecoder/theALU/i_0_18/B2->ZN + AOI22_X4_LVT fr 942.1 30.3 30.3 0.0 8.6 0.8 4.4 1 +theDecoder/theALU/i_0_17/B2->ZN + OAI21_X4_LVT rf 948.5 6.4 6.4 0.0 16.9 0.7 4.3 1 +theDecoder/theALU/i_0_16/A->ZN + OAI21_X4_LVT fr 958.3 9.8 9.8 0.0 3.6 0.7 3.9 1 +theDecoder/theALU/i_0_13/B1->ZN + AOI21_X4_LVT rf 963.5 5.3 5.3 0.0 12.5 0.8 4.4 1 +theDecoder/theALU/i_0_12/A4->ZN + NOR4_X2_LVT fr 1020.0 56.5 56.5 0.0 2.9 0.8 2.8 1 +theDecoder/theALU/i_0_0/A3->ZN + OR3_X4_LVT rr 1036.6 16.6 16.6 0.0 29.1 0.7 14.7 2 +theDecoder/i_0_114/B->ZN XNOR2_X2_LVT rf 1043.2 6.5 6.5 0.0 7.8 0.7 4.3 1 +theDecoder/i_0_113/B1->ZN + AOI22_X4_LVT fr 1069.7 26.5 26.5 0.0 5.1 0.8 4.4 1 +theDecoder/i_0_111/A2->ZN + AOI22_X4_LVT rf 1076.1 6.4 6.4 0.0 16.9 0.7 4.3 1 +theDecoder/i_0_110/A2->ZN + NAND2_X4_LVT* fr 1095.3 19.2 19.2 0.0 4.4 9.0 37.6 13 +i_0_0_60/S->Z MUX2_X2_LVT* rf 1161.7 66.4 66.4 0.0 10.2 11.1 66.7 3 +theMem/i_0_0_11/B2->ZN AOI22_X4_LVT* fr 1209.5 47.8 47.8 0.0 10.2 0.7 23.4 1 +theMem/i_0_0_10/A->ZN INV_X8_LVT rf 1211.5 2.0 2.0 0.0 10.2 0.8 1.8 1 +theMem/mem_addr_reg[5]/D SDFF_X1_LVT f 1211.5 0.0 0.0 0.5 +-------------------------------------------------------------------------------------------------------------------------------------- +Report for group I2R +Report for group I2O +Report for group R2O +-------------------------------------------------------------------------------------------------------------------------------------- +Startpoint: theMem/IRData_reg[18]/Q + (Clocked by clk_25mhz R) +Endpoint: led[7] + (Clocked by clk_25mhz R) +Path Group: R2O +Data required time: 37500.0 + (Clock shift: 40000.0, minus Uncertainty: 500.0, plus Latency 0.0, minus Out delay: 2000.0) +Data arrival time: 1161.7 +Slack: 36338.3 +Logic depth: 44 +-------------------------------------------------------------------------------------------------------------------------------------- + Arrival Arc Net Net Total fan- +Path Module/Cell Edge Time Delay Delay Delay Slew Load Load out Location + (ps) (ps) (ps) (ps) (ps) (ff) (ff) (#) (um,um) +-------------------------------------------------------------------------------------------------------------------------------------- +clk_25mhz {create_clock} r 0.0 0.0 0.0 0.0 0.0 100 +theMem/IRData_reg[18]/CK->Q + SDFF_X1_LVT* rr 84.9 84.9 84.9 0.0 100.0 10.6 73.4 11 +theRegisters/i_1_0_1371/A->ZN + INV_X8_LVT rf 87.6 2.7 2.7 0.0 10.2 2.1 13.2 3 +theRegisters/i_1_0_1339/A2->ZN + NAND3_X4_LVT fr 101.6 14.0 14.0 0.0 1.0 2.5 17.5 4 +theRegisters/i_1_0_1321/A2->ZN + NOR2_X4_LVT* rf 120.6 19.0 19.0 0.0 12.1 29.7 130.1 32 +theRegisters/i_1_0_722/B1->ZN + AOI22_X4_LVT* fr 164.9 44.3 44.3 0.0 10.2 0.7 23.4 1 +theRegisters/i_1_0_721/A->ZN + INV_X8_LVT rf 167.0 2.1 2.1 0.0 10.2 0.8 3.0 1 +theRegisters/i_1_0_718/A->ZN + AOI221_X2_LVT fr 224.3 57.3 57.3 0.0 0.6 0.9 4.4 1 +theRegisters/i_1_0_716/A3->ZN + NAND4_X4_LVT rf 239.7 15.4 15.4 0.0 34.6 0.9 3.1 1 +theRegisters/i_1_0_715/A->ZN + AOI221_X2_LVT fr 297.1 57.4 57.4 0.0 6.8 0.9 4.3 1 +theRegisters/i_1_0_704/A2->ZN + NAND4_X4_LVT rf 317.6 20.5 20.5 0.0 34.4 5.9 16.7 3 +theDecoder/i_0_133/C2->ZN + AOI222_X4_LVT fr 428.0 110.5 110.5 0.0 12.2 0.8 23.5 1 +theDecoder/i_0_132/A->ZN INV_X32_LVT rf 431.2 3.1 3.1 0.0 10.9 5.4 65.3 7 +theDecoder/theALU/i_0_706/B1->ZN + OAI22_X4_LVT* fr 474.4 43.2 43.2 0.0 1.4 1.5 25.9 2 +theDecoder/theALU/i_0_705/A->ZN + INV_X8_LVT rf 476.5 2.2 2.2 0.0 10.2 0.6 4.2 1 +theDecoder/theALU/i_0_42/A->ZN + OAI21_X2_LVT fr 485.6 9.1 9.1 0.0 0.6 0.8 2.5 1 +theDecoder/theALU/i_0_40/C1->ZN + AOI211_X2_LVT rf 491.3 5.6 5.6 0.0 11.6 0.8 2.9 1 +theDecoder/theALU/i_0_39/B->ZN + AOI211_X2_LVT fr 538.7 47.4 47.4 0.0 3.3 0.9 3.0 1 +theDecoder/theALU/i_0_38/B2->ZN + OAI222_X2_LVT rf 555.6 16.9 16.9 0.0 27.7 0.9 2.9 1 +theDecoder/theALU/i_0_37/C2->ZN + AOI221_X2_LVT fr 599.5 43.8 43.8 0.0 8.4 0.9 4.2 1 +theDecoder/theALU/i_0_35/B1->ZN + OAI22_X4_LVT* rf 613.4 13.9 13.9 0.0 34.0 0.7 23.4 1 +theDecoder/theALU/i_0_34/A->ZN + INV_X8_LVT fr 617.9 4.5 4.5 0.0 10.2 0.6 4.1 1 +theDecoder/theALU/i_0_33/A->ZN + AOI21_X4_LVT rf 620.5 2.6 2.6 0.0 2.4 0.8 3.0 1 +theDecoder/theALU/i_0_32/C2->ZN + OAI222_X2_LVT fr 659.0 38.5 38.5 0.0 2.6 0.9 3.3 1 +theDecoder/theALU/i_0_31/A->ZN + OAI221_X2_LVT rf 675.0 16.0 16.0 0.0 29.2 0.8 4.0 1 +theDecoder/theALU/i_0_28/B1->ZN + AOI21_X4_LVT fr 690.5 15.5 15.5 0.0 8.2 0.8 3.0 1 +theDecoder/theALU/i_0_27/A->ZN + AOI221_X2_LVT rf 694.7 4.2 4.2 0.0 13.5 0.9 2.9 1 +theDecoder/theALU/i_0_26/B->ZN + AOI211_X2_LVT fr 746.9 52.2 52.2 0.0 5.3 0.8 4.6 1 +theDecoder/theALU/i_0_25/B2->ZN + OAI22_X2_LVT rf 756.6 9.7 9.7 0.0 31.8 0.8 2.7 1 +theDecoder/theALU/i_0_24/C2->ZN + AOI211_X2_LVT fr 791.0 34.4 34.4 0.0 4.0 0.9 3.1 1 +theDecoder/theALU/i_0_23/A->ZN + AOI221_X2_LVT rf 796.7 5.8 5.8 0.0 27.8 0.9 3.1 1 +theDecoder/theALU/i_0_22/A->ZN + AOI221_X2_LVT fr 850.4 53.7 53.7 0.0 5.4 0.9 3.1 1 +theDecoder/theALU/i_0_21/A->ZN + AOI221_X2_LVT rf 856.5 6.1 6.1 0.0 31.2 0.9 3.1 1 +theDecoder/theALU/i_0_20/C2->ZN + OAI222_X2_LVT fr 895.2 38.8 38.8 0.0 5.4 0.9 3.3 1 +theDecoder/theALU/i_0_19/A->ZN + OAI221_X2_LVT rf 911.8 16.6 16.6 0.0 29.2 0.9 4.7 1 +theDecoder/theALU/i_0_18/B2->ZN + AOI22_X4_LVT fr 942.1 30.3 30.3 0.0 8.6 0.8 4.4 1 +theDecoder/theALU/i_0_17/B2->ZN + OAI21_X4_LVT rf 948.5 6.4 6.4 0.0 16.9 0.7 4.3 1 +theDecoder/theALU/i_0_16/A->ZN + OAI21_X4_LVT fr 958.3 9.8 9.8 0.0 3.6 0.7 3.9 1 +theDecoder/theALU/i_0_13/B1->ZN + AOI21_X4_LVT rf 963.5 5.3 5.3 0.0 12.5 0.8 4.4 1 +theDecoder/theALU/i_0_12/A4->ZN + NOR4_X2_LVT fr 1020.0 56.5 56.5 0.0 2.9 0.8 2.8 1 +theDecoder/theALU/i_0_0/A3->ZN + OR3_X4_LVT rr 1036.6 16.6 16.6 0.0 29.1 0.7 14.7 2 +theDecoder/i_0_114/B->ZN XNOR2_X2_LVT rf 1043.2 6.5 6.5 0.0 7.8 0.7 4.3 1 +theDecoder/i_0_113/B1->ZN + AOI22_X4_LVT fr 1069.7 26.5 26.5 0.0 5.1 0.8 4.4 1 +theDecoder/i_0_111/A2->ZN + AOI22_X4_LVT rf 1076.1 6.4 6.4 0.0 16.9 0.7 4.3 1 +theDecoder/i_0_110/A2->ZN + NAND2_X4_LVT* fr 1095.3 19.2 19.2 0.0 4.4 9.0 37.6 13 +i_0_0_60/S->Z MUX2_X2_LVT* rf 1161.7 66.4 66.4 0.0 10.2 11.1 66.7 3 +led[7] f 1161.7 0.0 0.0 10.2 +-------------------------------------------------------------------------------------------------------------------------------------- +> report_path_groups +Report Path Groups: +-----+-------+------+---------+--------- + | Path |Weight|Critical |Worst + | Group | |Range(ps)|Slack(ps) +-----+-------+------+---------+--------- +1 |default| 1.000| 0.0| 18015.8 +2 |I2R | 1.000| 0.0| +3 |I2O | 1.000| 0.0| +4 |R2O | 1.000| 0.0| 36338.3 +-----+-------+------+---------+--------- + +------------------------------------- + +Synthesis and optimization complete + +------------------------------------- + +INFO::Running oasys Tessent DFT flow +> source scripts_risc_v/oasys_tessent_dft.tcl +INFO::using /applications/SiemensEDA/siemenseda2023/tessent/bin/tessent build to run the Tessent DFT flow +> config_tessent -exec_path /applications/SiemensEDA/siemenseda2023/tessent/bin/tessent +> define_test_clock -pin clk_25mhz +> define_test_pin -pin scan_en -scan_mode 1 -default_scan_enable -create_port +Adding Test pin scan_en to top Module +> set_dont_scan theMem true +> define_test_pin -name reset -pin {btn[0]} -scan_mode 1 +> check_dft -auto_test_clock -auto_test_pins +starting check_dft at 00:00:17(cpu)/0:00:59(wall) 186MB(vsz)/566MB(peak) +Checking DFT rules for 'cpu' + Running DFT TDRC iteration 1 + Total 1131 scanModels/flops with 12% scanable (139 pass, 992 fail, 0 nonScan or excludeScan) +Report Check DFT: +-----+---------------------+------+--------+------+------------------------------------------- + |Item |Errors|Warnings|Status|Description +-----+---------------------+------+--------+------+------------------------------------------- +1 |internal_clock | 0| 0|Passed|Internal Clock +2 |constant_clock | 0| 0|Passed|Constant Clock +3 |non_clock_PI | 0| 0|Passed|Non-Clock PI +4 |blocking_clock_gate | 0| 31|Failed|Blocking clock gate +5 |internal_async | 0| 0|Passed|Internal Async. Set/Reset control +6 |constant_active_async| 0| 0|Passed|Constant active Async. Set/Reset signal +7 |non_test_PI | 0| 0|Passed|Unconstrained PI driving Async/ Set/Reset +8 |async_clock_conflict | 0| 0|Passed|Async. Set/Reset signal and Clock conflict +9 |parallel_scan_clock | 0| 0|Passed|Clock pin of unsupported parallel-scan flop +-----+---------------------+------+--------+------+------------------------------------------- +Design has 31 DFT violation(s) +finished check_dft at 00:00:17(cpu)/0:00:59(wall) 186MB(vsz)/566MB(peak) +> write_db ./output/odb/riscv.tessent_pre_fix.odb +> fix_dft_violations -type all -test_clock clk_25mhz -test_control scan_en +Created 0 gates to fix Async violation(s) +Created 0 muxes to fix clock violation(s) +Replaced 31 clock-gating cells to fix clock-gating violation(s) +> report_dft_violations +Report DftViolations: +-----+-------------------+-----------------------------------------------+-------------------- + | Type | Pin | Affected Registers +-----+-------------------+-----------------------------------------------+-------------------- +1 |blocking clock gate|theRegisters/clk_gate_registers_reg[1]_reg/GCK | 32 +2 |blocking clock gate|theRegisters/clk_gate_registers_reg[2]_reg/GCK | 32 +3 |blocking clock gate|theRegisters/clk_gate_registers_reg[3]_reg/GCK | 32 +4 |blocking clock gate|theRegisters/clk_gate_registers_reg[4]_reg/GCK | 32 +5 |blocking clock gate|theRegisters/clk_gate_registers_reg[5]_reg/GCK | 32 +6 |blocking clock gate|theRegisters/clk_gate_registers_reg[6]_reg/GCK | 32 +7 |blocking clock gate|theRegisters/clk_gate_registers_reg[7]_reg/GCK | 32 +8 |blocking clock gate|theRegisters/clk_gate_registers_reg[8]_reg/GCK | 32 +9 |blocking clock gate|theRegisters/clk_gate_registers_reg[9]_reg/GCK | 32 +10 |blocking clock gate|theRegisters/clk_gate_registers_reg[10]_reg/GCK| 32 +11 |blocking clock gate|theRegisters/clk_gate_registers_reg[11]_reg/GCK| 32 +12 |blocking clock gate|theRegisters/clk_gate_registers_reg[12]_reg/GCK| 32 +13 |blocking clock gate|theRegisters/clk_gate_registers_reg[13]_reg/GCK| 32 +14 |blocking clock gate|theRegisters/clk_gate_registers_reg[14]_reg/GCK| 32 +15 |blocking clock gate|theRegisters/clk_gate_registers_reg[15]_reg/GCK| 32 +16 |blocking clock gate|theRegisters/clk_gate_registers_reg[16]_reg/GCK| 32 +17 |blocking clock gate|theRegisters/clk_gate_registers_reg[17]_reg/GCK| 32 +18 |blocking clock gate|theRegisters/clk_gate_registers_reg[18]_reg/GCK| 32 +19 |blocking clock gate|theRegisters/clk_gate_registers_reg[19]_reg/GCK| 32 +20 |blocking clock gate|theRegisters/clk_gate_registers_reg[20]_reg/GCK| 32 +21 |blocking clock gate|theRegisters/clk_gate_registers_reg[21]_reg/GCK| 32 +22 |blocking clock gate|theRegisters/clk_gate_registers_reg[22]_reg/GCK| 32 +23 |blocking clock gate|theRegisters/clk_gate_registers_reg[23]_reg/GCK| 32 +24 |blocking clock gate|theRegisters/clk_gate_registers_reg[24]_reg/GCK| 32 +25 |blocking clock gate|theRegisters/clk_gate_registers_reg[25]_reg/GCK| 32 +26 |blocking clock gate|theRegisters/clk_gate_registers_reg[26]_reg/GCK| 32 +27 |blocking clock gate|theRegisters/clk_gate_registers_reg[27]_reg/GCK| 32 +28 |blocking clock gate|theRegisters/clk_gate_registers_reg[28]_reg/GCK| 32 +29 |blocking clock gate|theRegisters/clk_gate_registers_reg[29]_reg/GCK| 32 +30 |blocking clock gate|theRegisters/clk_gate_registers_reg[30]_reg/GCK| 32 +31 |blocking clock gate|theRegisters/clk_gate_registers_reg[31]_reg/GCK| 32 +-----+-------------------+-----------------------------------------------+-------------------- +> optimize +starting optimize at 00:00:18(cpu)/0:01:00(wall) 186MB(vsz)/566MB(peak) +info: mapped 107 flop(s) to scan cells, excluded 107 is_dont_scan flop(s) and 0 is_dont_touch flop(s) +info: Target library/cell information has changed that further may change timing results. [TA-159] +info: optimizing design 'cpu' - propagating constants +info: optimized '' area changed 0.0squm (x1), total 11274.7squm (#1, 0 secs) +info: set slack mode to optimize shift +info: resetting all path groups +info: activated path group default @ 18139.2ps +info: suspended path group I2R @ ps +info: suspended path group I2O @ ps +info: activated path group R2O @ 36317.8ps +info: finished path group default @ 18139.2ps +info: finished path group R2O @ 36317.8ps +info: reactivating path groups +info: reactivated path group default @ 18139.2ps +info: reactivated path group R2O @ 36317.8ps +info: finished path group default @ 18139.2ps +info: finished path group R2O @ 36317.8ps +info: set slack mode to normal +info: done with all path groups +info: restore all path groups +info: starting area recovery on module cpu +info: optimized 'cpu__GC0' area recovered 0.00squm (x1), total 0.00squm (1#5), 0.04 secs +info: optimized 'main_mem__GC0' area recovered 0.00squm (x1), total 0.00squm (2#5), 0.04 secs +info: optimized 'MemGen_32_11__block' area recovered 0.00squm (x1), total 0.00squm (3#5), 0.01 secs +info: optimized 'reg_file__always' area recovered 0.00squm (x1), total 0.00squm (4#5), 0.01 secs +info: optimized 'reg_file__GB1' area recovered 0.00squm (x1), total 0.00squm (5#5), 0.03 secs +info: area recovery done, total area reduction: 0.00squm (0.00%), final slack: 18139.2ps (delta: 0.0ps) (0 secs) +done optimizing virtual at 00:00:19(cpu)/0:01:01(wall) 190MB(vsz)/566MB(peak) +info: floorplan : total 4 movable macros and 0 fixed macros +info: creating tracks for 10 routing layers [FP-148] +info: start floorplan stage 0 [FP-145] +info: end floorplan stage 0 [FP-145] +info: start floorplan stage 1 [FP-145] +info: end floorplan stage 1 [FP-145] +info: start rtl partition placement [PLACE-114] +info: placement mode : raw [PLACE-115] +info: set slack mode to weight modified +info: set slack mode to normal +info: set slack mode to optimize shift +info: timing-driven placement : ON [PLACE-116] +info: congestion-driven placement : ON [PLACE-117] +info: placement movable objects : macros 0 , rtl partitions 5, cells 0 [PLACE-118] +info: start placement stage 0 [PLACE-111] +info: end placement stage 0 [PLACE-111] +info: set slack mode to normal +info: cell density map (bin size 20 x 20 rows), maximum utilization: 170.00% average utilization: 13.98% [PLACE-153] +info: 9.00% bins with overflow, average overflow 18.49% [PLACE-154] +info: P-D: 0.090% (0.185 ~ 0.700) +Total Wire Length = 77698.10 +Average Wire = 58.60 +Longest Wire = 352.69 +Shortest Wire = 0.00 +WNS = 18139.5ps +info: placing 17 unplaced IO Pins +info: start rtl partition placement [PLACE-114] +info: placement mode : raw [PLACE-115] +info: set slack mode to weight modified +info: set slack mode to normal +info: set slack mode to optimize shift +info: timing-driven placement : ON [PLACE-116] +info: congestion-driven placement : ON [PLACE-117] +info: placement movable objects : macros 0 , rtl partitions 5, cells 0 [PLACE-118] +info: start placement stage 0 [PLACE-111] +info: end placement stage 0 [PLACE-111] +info: set slack mode to normal +info: cell density map (bin size 20 x 20 rows), maximum utilization: 90.53% average utilization: 14.23% [PLACE-153] +info: 0.00% bins with overflow, average overflow 0.00% [PLACE-154] +info: P-D: 0.000% (0.000 ~ 0.000) +Total Wire Length = 115431.45 +Average Wire = 87.05 +Longest Wire = 426.66 +Shortest Wire = 10.50 +WNS = 18131.2ps +info: 0 power/ground pre-route segments processed. [PLACE-144] +info: 0 routing blockages processed. [PLACE-145] +info: replaced @ 18131.2ps +done optimize placement at 00:00:22(cpu)/0:01:04(wall) 378MB(vsz)/822MB(peak) +info: cell density map (bin size 20 x 20 rows), maximum utilization: 90.53% average utilization: 14.23% [PLACE-153] +info: 0.00% bins with overflow, average overflow 0.00% [PLACE-154] +info: set slack mode to optimize shift +info: resetting all path groups +info: activated path group default @ 18131.2ps +info: suspended path group I2R @ ps +info: suspended path group I2O @ ps +info: activated path group R2O @ 36309.8ps +info: finished path group default @ 18131.2ps +info: finished path group R2O @ 36309.8ps +info: reactivating path groups +info: reactivated path group default @ 18131.2ps +info: reactivated path group R2O @ 36309.8ps +info: finished path group default @ 18131.2ps +info: finished path group R2O @ 36309.8ps +info: cell density map (bin size 20 x 20 rows), maximum utilization: 90.53% average utilization: 14.23% [PLACE-153] +info: 0.00% bins with overflow, average overflow 0.00% [PLACE-154] +info: 0 power/ground pre-route segments processed. [PLACE-144] +info: 0 routing blockages processed. [PLACE-145] +info: set slack mode to normal +info: done with all path groups +info: restore all path groups +info: (0) optimizing 'theMem/i_0/IAddr[5]' (path group default) @ 18131.2ps(1/1) (4 secs) +finished optimize at 00:00:22(cpu)/0:01:04(wall) 378MB(vsz)/822MB(peak) +> write_db ./output/odb/riscv.tessent_post_fix.odb +> write_verilog ./output/riscv.tessent_post_fix.v +info: writing Verilog file './output/riscv.tessent_post_fix.v' for module 'cpu' [WRITE-100] +> config_tessent -library {./libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib ./libs/fastscan/NangateOpenCellLibrary_low_temp_ccs.fslib ./libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib ./libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib ./libs/fastscan/LowPowerOpenCellLibrary_low_temp_ccs.fslib ./libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib ./libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.fslib ./libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib ./libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib ./libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib ./libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib ./libs/fastscan/PLL.fslib ./libs/fastscan/IO.fslib} + +--------------check dft--------------- +> check_dft +starting check_dft at 00:00:22(cpu)/0:01:05(wall) 369MB(vsz)/822MB(peak) +Checking DFT rules for 'cpu' + Running DFT TDRC iteration 1 + Total 1131 scanModels/flops with 90% scanable (1024 pass, 0 fail, 107 nonScan or excludeScan) +Report Check DFT: +-----+---------------------+------+--------+------+------------------------------------------- + |Item |Errors|Warnings|Status|Description +-----+---------------------+------+--------+------+------------------------------------------- +1 |internal_clock | 0| 0|Passed|Internal Clock +2 |constant_clock | 0| 0|Passed|Constant Clock +3 |non_clock_PI | 0| 0|Passed|Non-Clock PI +4 |blocking_clock_gate | 0| 0|Passed|Blocking clock gate +5 |internal_async | 0| 0|Passed|Internal Async. Set/Reset control +6 |constant_active_async| 0| 0|Passed|Constant active Async. Set/Reset signal +7 |non_test_PI | 0| 0|Passed|Unconstrained PI driving Async/ Set/Reset +8 |async_clock_conflict | 0| 0|Passed|Async. Set/Reset signal and Clock conflict +9 |parallel_scan_clock | 0| 0|Passed|Clock pin of unsupported parallel-scan flop +-----+---------------------+------+--------+------+------------------------------------------- +Design has 0 DFT violation(s) +finished check_dft at 00:00:23(cpu)/0:01:05(wall) 369MB(vsz)/822MB(peak) + +--------------define Scan-Chains--------------- +> define_scan_chain -scan_in SI_1 -scan_out SO_1 -create_port +Defining Scan Chain scanChain_1( si:SI_1, so:SO_1) +Adding Scan-in pin SI_1 to top Module +Adding Scan-out pin SO_1 to top Module +> define_scan_chain -scan_in SI_2 -scan_out SO_2 -create_port +Defining Scan Chain scanChain_2( si:SI_2, so:SO_2) +Adding Scan-in pin SI_2 to top Module +Adding Scan-out pin SO_2 to top Module +> define_scan_chain -scan_in SI_3 -scan_out SO_3 -create_port +Defining Scan Chain scanChain_3( si:SI_3, so:SO_3) +Adding Scan-in pin SI_3 to top Module +Adding Scan-out pin SO_3 to top Module +> define_scan_chain -scan_in SI_4 -scan_out SO_4 -create_port +Defining Scan Chain scanChain_4( si:SI_4, so:SO_4) +Adding Scan-in pin SI_4 to top Module +Adding Scan-out pin SO_4 to top Module + +----------run_tessent_scan---------------- +> run_tessent_scan +info: writing Verilog file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.01/Scan_0/oasys_netlist.v' for module 'cpu' [WRITE-100] +starting check_dft at 00:00:23(cpu)/0:01:05(wall) 368MB(vsz)/822MB(peak) +Checking DFT rules for 'cpu' + Running DFT TDRC iteration 1 + Total 1131 scanModels/flops with 90% scanable (1024 pass, 0 fail, 107 nonScan or excludeScan) +Report Check DFT: +-----+---------------------+------+--------+------+------------------------------------------- + |Item |Errors|Warnings|Status|Description +-----+---------------------+------+--------+------+------------------------------------------- +1 |internal_clock | 0| 0|Passed|Internal Clock +2 |constant_clock | 0| 0|Passed|Constant Clock +3 |non_clock_PI | 0| 0|Passed|Non-Clock PI +4 |blocking_clock_gate | 0| 0|Passed|Blocking clock gate +5 |internal_async | 0| 0|Passed|Internal Async. Set/Reset control +6 |constant_active_async| 0| 0|Passed|Constant active Async. Set/Reset signal +7 |non_test_PI | 0| 0|Passed|Unconstrained PI driving Async/ Set/Reset +8 |async_clock_conflict | 0| 0|Passed|Async. Set/Reset signal and Clock conflict +9 |parallel_scan_clock | 0| 0|Passed|Clock pin of unsupported parallel-scan flop +-----+---------------------+------+--------+------+------------------------------------------- +Design has 0 DFT violation(s) +finished check_dft at 00:00:23(cpu)/0:01:05(wall) 368MB(vsz)/822MB(peak) + Configuring 4 scan chain(s) + Configuring DEFAULT DFT partition + Enabling physical aware scan chains + Configuring 4 scan chain(s) for 1024 scan instance(s) in 1 test clock domain(s) + Domain clk_25mhz has 1024 flop(s) (1024 rise, 0 fall), 4 chain(s) (4,0) + Assigning chain scanChain_1 to domain clk_25mhz (edge: rise) (capacity: 256) + Assigning chain scanChain_2 to domain clk_25mhz (edge: rise) (capacity: 256) + Assigning chain scanChain_3 to domain clk_25mhz (edge: rise) (capacity: 256) + Assigning chain scanChain_4 to domain clk_25mhz (edge: rise) (capacity: 256) +info: writing Sdc file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.01/Scan_0/oasys.sdc' for design 'cpu' [WRITE-104] +info: Parameter 'tessentScandefFilePath' set to '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.01/Scan_0/cpu.scandef' [PARAM-104] + +************************************************************************************************************************************************************************************** + TESSENT EXECUTION BEGINS + Invoking Tessent Executable : /applications/SiemensEDA/siemenseda2023/tessent_2023.4-p1/bin/tessent + DoFile : /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.01/Scan_0/scan.do +************************************************************************************************************************************************************************************** + +/applications/SiemensEDA/siemenseda2023/tessent_2023.4-p1/bin/tessent -shell -dofile /tmp/oasys.2567124/.tmpTessentFile -log_file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.01/Scan_0/scan.log -replace +// Tessent Shell 2023.4-p1 Mon Feb 19 16:22:02 GMT 2024 +// Unpublished work. Copyright 2024 Siemens +// +// This material contains trade secrets or otherwise confidential +// information owned by Siemens Industry Software Inc. or its affiliates +// (collectively, "SISW"), or its licensors. Access to and use of this +// information is strictly limited as set forth in the Customer's +// applicable agreements with SISW. +// +// Siemens software executing under x86-64 Linux on Fri May 29 09:09:54 CEST 2026. +// 64 bit version +// Host: efiapps0.ads1.fh-nuernberg.de (12 x 3.5 GHz, 48014 MB RAM, 24575 MB Swap) +// +// command: if {[catch {source /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.01/Scan_0/scan.do} msg]} { +// puts "$msg" +// puts "TESSENT_ER_ORTL" } +// sub-command: set_context dft -scan -no_rtl -design_id Scan_0 +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_low_temp_ccs.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_low_temp_ccs.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_low_temp_ccs.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_low_temp_ccs.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_low_temp_ccs.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_low_temp_ccs.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/PLL.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/PLL.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/PLL.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/IO.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/IO.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/IO.fslib +// sub-command: set_module_matching_options -suffix_pattern_list {[_]+[0-9]+[_]+[0-9]+} -regexp -append +// sub-command: set_module_matching_options -suffix_pattern_list {[_]+[A-Z]+} -regexp -append +// sub-command: set_module_matching_options -suffix_pattern_list {[_]+[0-9]+[_]+[0-9]+[_]+[A-Z]+} -regexp -append +// sub-command: read_verilog /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.01/Scan_0/oasys_netlist.v +// sub-command: set_tsdb_output_directory /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.01/tsdb_outdir +// sub-command: read_sdc /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.01/Scan_0/oasys.sdc +// Command 'read_sdc' requires an elaborated design. Automatically elaborating the design ... +// Note: 640 duplicate cell library models were read. The last model read of the same name was kept. +// To see detailed messages per duplicate model, issue 'set_cell_library_options -report_duplicate_models on' +// before issuing 'read_cell_library'. +// Warning: 1 cell library model contained 2 floating model outputs. +// To see detailed messages per model, issue 'set_cell_library_options -report_floating_nets on' +// before issuing 'read_cell_library'. +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X1' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X2' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X4' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X8' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X1_HVT' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X2_HVT' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X4_HVT' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X8_HVT' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X1_SVT' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X2_SVT' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X4_SVT' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X8_SVT' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X1_LVT' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X2_LVT' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X4_LVT' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X8_LVT' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' +// Note: Top design is 'cpu'. +// Warning: Undefined modules were found. +// Before using "set_system_mode" or "create_flat_model", you must either define +// the missing modules using "read_verilog" and/or "read_cell_library", or use the +// following command to treat them as black boxes: + add_black_boxes -modules { \ + MemGen_16_10 \ + } +// You can also use "add_black_boxes -auto" to black box all undefined modules but +// it is recommended that you do not add this command to your dofile. Doing so may +// unintentionally black-box new undefined modules in future runs. +// Warning: 32 cases: Unused net in DFT library model +// Warning: 110 cases: Undriven net in netlist module +// Warning: 1 case: Floating input on instance in netlist +// Warning: 47 cases: Net in netlist not connected +// Note: Issue set_current_design with the -show_elaboration_warnings option to see more details about previous warnings +// Design elaboration successful. +// Reading SDC file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.01/Scan_0/oasys.sdc ... +// Finished reading SDC file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.01/Scan_0/oasys.sdc. +// Read SDC summary: 1 false path, 0 multi-cycle paths, 0 erroneous paths +// 0 disable timings, 0 case analysis, 0 clock groups +// sub-command: set_current_design cpu -show_elaboration_warnings +// Warning: Undefined modules were found. +// Before using "set_system_mode" or "create_flat_model", you must either define +// the missing modules using "read_verilog" and/or "read_cell_library", or use the +// following command to treat them as black boxes: + add_black_boxes -modules { \ + MemGen_16_10 \ + } +// You can also use "add_black_boxes -auto" to black box all undefined modules but +// it is recommended that you do not add this command to your dofile. Doing so may +// unintentionally black-box new undefined modules in future runs. +// Warning: Net 'SO_1' in module 'cpu' is not driven +// Warning: Net 'SO_2' in module 'cpu' is not driven +// Warning: Net 'SO_3' in module 'cpu' is not driven +// Warning: Net 'SO_4' in module 'cpu' is not driven +// Warning: Net 'DAddr[31]' in module 'cpu' has no pins +// Warning: Net 'DAddr[30]' in module 'cpu' has no pins +// Warning: Net 'DAddr[29]' in module 'cpu' has no pins +// Warning: Net 'DAddr[28]' in module 'cpu' has no pins +// Warning: Net 'DAddr[27]' in module 'cpu' has no pins +// Warning: Net 'DAddr[26]' in module 'cpu' has no pins +// Warning: Net 'DAddr[25]' in module 'cpu' has no pins +// Warning: Net 'DAddr[24]' in module 'cpu' has no pins +// Warning: Net 'DAddr[23]' in module 'cpu' has no pins +// Warning: Net 'DAddr[22]' in module 'cpu' has no pins +// Warning: Net 'DAddr[21]' in module 'cpu' has no pins +// Warning: Net 'DAddr[20]' in module 'cpu' has no pins +// Warning: Net 'DAddr[19]' in module 'cpu' has no pins +// Warning: Net 'DAddr[18]' in module 'cpu' has no pins +// Warning: Net 'DAddr[17]' in module 'cpu' has no pins +// Warning: Net 'DAddr[16]' in module 'cpu' has no pins +// Warning: Net 'DAddr[15]' in module 'cpu' has no pins +// Warning: Net 'DAddr[14]' in module 'cpu' has no pins +// Warning: Net 'DAddr[13]' in module 'cpu' has no pins +// Warning: Net 'NextPC[31]' in module 'cpu' has no pins +// Warning: Net 'NextPC[30]' in module 'cpu' has no pins +// Warning: Net 'NextPC[29]' in module 'cpu' has no pins +// Warning: Net 'NextPC[28]' in module 'cpu' has no pins +// Warning: Net 'NextPC[27]' in module 'cpu' has no pins +// Warning: Net 'NextPC[26]' in module 'cpu' has no pins +// Warning: Net 'NextPC[25]' in module 'cpu' has no pins +// Warning: Net 'NextPC[24]' in module 'cpu' has no pins +// Warning: Net 'NextPC[23]' in module 'cpu' has no pins +// Warning: Net 'NextPC[22]' in module 'cpu' has no pins +// Warning: Net 'NextPC[21]' in module 'cpu' has no pins +// Warning: Net 'NextPC[20]' in module 'cpu' has no pins +// Warning: Net 'NextPC[19]' in module 'cpu' has no pins +// Warning: Net 'NextPC[18]' in module 'cpu' has no pins +// Warning: Net 'NextPC[17]' in module 'cpu' has no pins +// Warning: Net 'NextPC[16]' in module 'cpu' has no pins +// Warning: Net 'NextPC[15]' in module 'cpu' has no pins +// Warning: Net 'NextPC[14]' in module 'cpu' has no pins +// Warning: Net 'NextPC[13]' in module 'cpu' has no pins +// Warning: Net 'NextPC[7]' in module 'cpu' has no pins +// Warning: Net 'NextPC[6]' in module 'cpu' has no pins +// Warning: Net 'NextPC[5]' in module 'cpu' has no pins +// Warning: Net 'NextPC[4]' in module 'cpu' has no pins +// Warning: Net 'NextPC[3]' in module 'cpu' has no pins +// Warning: Net 'NextPC[2]' in module 'cpu' has no pins +// Warning: Net 'NextPC[1]' in module 'cpu' has no pins +// Warning: Net 'NextPC[0]' in module 'cpu' has no pins +// Warning: Net 'uc_0' in module 'cpu' is not driven +// Warning: Net 'uc_1' in module 'cpu' is not driven +// Warning: Net 'uc_2' in module 'cpu' is not driven +// Warning: Net 'uc_3' in module 'cpu' is not driven +// Warning: Net 'uc_4' in module 'cpu' is not driven +// Warning: Net 'uc_5' in module 'cpu' is not driven +// Warning: Net 'uc_6' in module 'cpu' is not driven +// Warning: Net 'uc_7' in module 'cpu' is not driven +// Warning: Net 'uc_8' in module 'cpu' is not driven +// Warning: Net 'uc_9' in module 'cpu' is not driven +// Warning: Net 'uc_10' in module 'cpu' is not driven +// Warning: Net 'uc_11' in module 'cpu' is not driven +// Warning: Net 'uc_12' in module 'cpu' is not driven +// Warning: Net 'uc_13' in module 'cpu' is not driven +// Warning: Net 'uc_14' in module 'cpu' is not driven +// Warning: Net 'uc_15' in module 'cpu' is not driven +// Warning: Net 'uc_16' in module 'cpu' is not driven +// Warning: Net 'uc_17' in module 'cpu' is not driven +// Warning: Net 'uc_18' in module 'cpu' is not driven +// Warning: Net 'uc_19' in module 'cpu' is not driven +// Warning: Net 'uc_20' in module 'cpu' is not driven +// Warning: Net 'uc_21' in module 'cpu' is not driven +// Warning: Net 'uc_22' in module 'cpu' is not driven +// Warning: Net 'uc_23' in module 'cpu' is not driven +// Warning: Net 'uc_24' in module 'cpu' is not driven +// Warning: Net 'uc_25' in module 'cpu' is not driven +// Warning: Net 'uc_26' in module 'cpu' is not driven +// Warning: Net 'uc_27' in module 'cpu' is not driven +// Warning: Net 'uc_28' in module 'cpu' is not driven +// Warning: Net 'uc_29' in module 'cpu' is not driven +// Warning: Net 'uc_30' in module 'cpu' is not driven +// Warning: Net 'uc_31' in module 'cpu' is not driven +// Warning: Net 'uc_32' in module 'cpu' is not driven +// Warning: Net 'uc_33' in module 'cpu' is not driven +// Warning: Net 'uc_34' in module 'cpu' is not driven +// Warning: Net 'uc_35' in module 'cpu' is not driven +// Warning: Net 'uc_36' in module 'cpu' is not driven +// Warning: Net 'uc_37' in module 'cpu' is not driven +// Warning: Net 'uc_38' in module 'cpu' is not driven +// Warning: Net 'uc_39' in module 'cpu' is not driven +// Warning: Floating input 'chip_en' at instance 'RAM' in module 'main_mem' +// Warning: Net 'mem_sel[1]' in module 'MemGen_32_11' has no pins +// Warning: Net 'DAddr[31]' in module 'decoder' is not driven +// Warning: Net 'DAddr[30]' in module 'decoder' is not driven +// Warning: Net 'DAddr[29]' in module 'decoder' is not driven +// Warning: Net 'DAddr[28]' in module 'decoder' is not driven +// Warning: Net 'DAddr[27]' in module 'decoder' is not driven +// Warning: Net 'DAddr[26]' in module 'decoder' is not driven +// Warning: Net 'DAddr[25]' in module 'decoder' is not driven +// Warning: Net 'DAddr[24]' in module 'decoder' is not driven +// Warning: Net 'DAddr[23]' in module 'decoder' is not driven +// Warning: Net 'DAddr[22]' in module 'decoder' is not driven +// Warning: Net 'DAddr[21]' in module 'decoder' is not driven +// Warning: Net 'DAddr[20]' in module 'decoder' is not driven +// Warning: Net 'DAddr[19]' in module 'decoder' is not driven +// Warning: Net 'DAddr[18]' in module 'decoder' is not driven +// Warning: Net 'DAddr[17]' in module 'decoder' is not driven +// Warning: Net 'DAddr[16]' in module 'decoder' is not driven +// Warning: Net 'DAddr[15]' in module 'decoder' is not driven +// Warning: Net 'DAddr[14]' in module 'decoder' is not driven +// Warning: Net 'DAddr[13]' in module 'decoder' is not driven +// Warning: Net 'WData[31]' in module 'decoder' is not driven +// Warning: Net 'WData[30]' in module 'decoder' is not driven +// Warning: Net 'WData[29]' in module 'decoder' is not driven +// Warning: Net 'WData[28]' in module 'decoder' is not driven +// Warning: Net 'WData[27]' in module 'decoder' is not driven +// Warning: Net 'WData[26]' in module 'decoder' is not driven +// Warning: Net 'WData[25]' in module 'decoder' is not driven +// Warning: Net 'WData[24]' in module 'decoder' is not driven +// Warning: Net 'WData[23]' in module 'decoder' is not driven +// Warning: Net 'WData[22]' in module 'decoder' is not driven +// Warning: Net 'WData[21]' in module 'decoder' is not driven +// Warning: Net 'WData[20]' in module 'decoder' is not driven +// Warning: Net 'WData[19]' in module 'decoder' is not driven +// Warning: Net 'WData[18]' in module 'decoder' is not driven +// Warning: Net 'WData[17]' in module 'decoder' is not driven +// Warning: Net 'WData[16]' in module 'decoder' is not driven +// Warning: Net 'WData[15]' in module 'decoder' is not driven +// Warning: Net 'WData[14]' in module 'decoder' is not driven +// Warning: Net 'WData[13]' in module 'decoder' is not driven +// Warning: Net 'WData[12]' in module 'decoder' is not driven +// Warning: Net 'WData[11]' in module 'decoder' is not driven +// Warning: Net 'WData[10]' in module 'decoder' is not driven +// Warning: Net 'WData[9]' in module 'decoder' is not driven +// Warning: Net 'WData[8]' in module 'decoder' is not driven +// Warning: Net 'WData[7]' in module 'decoder' is not driven +// Warning: Net 'WData[6]' in module 'decoder' is not driven +// Warning: Net 'WData[5]' in module 'decoder' is not driven +// Warning: Net 'WData[4]' in module 'decoder' is not driven +// Warning: Net 'WData[3]' in module 'decoder' is not driven +// Warning: Net 'WData[2]' in module 'decoder' is not driven +// Warning: Net 'WData[1]' in module 'decoder' is not driven +// Warning: Net 'WData[0]' in module 'decoder' is not driven +// Warning: Net 'Rs1[4]' in module 'decoder' is not driven +// Warning: Net 'Rs1[3]' in module 'decoder' is not driven +// Warning: Net 'Rs1[2]' in module 'decoder' is not driven +// Warning: Net 'Rs1[1]' in module 'decoder' is not driven +// Warning: Net 'Rs1[0]' in module 'decoder' is not driven +// Warning: Net 'Rs2[4]' in module 'decoder' is not driven +// Warning: Net 'Rs2[3]' in module 'decoder' is not driven +// Warning: Net 'Rs2[2]' in module 'decoder' is not driven +// Warning: Net 'Rs2[1]' in module 'decoder' is not driven +// Warning: Net 'Rs2[0]' in module 'decoder' is not driven +// Warning: Net 'Rd[4]' in module 'decoder' is not driven +// Warning: Net 'Rd[3]' in module 'decoder' is not driven +// Warning: Net 'Rd[2]' in module 'decoder' is not driven +// Warning: Net 'Rd[1]' in module 'decoder' is not driven +// Warning: Net 'Rd[0]' in module 'decoder' is not driven +// sub-command: set_design_level physical_block +// sub-command: set_shift_register_identification off +// sub-command: add_nonscan_instances -instances "{/theMem/\IRData_reg[31] } {/theMem/\IRData_reg[30] } {/theMem/\IRData_reg[29] } {/theMem/\IRData_reg[28] } {/theMem/\IRData_reg[27] } {/theMem/\IRData_reg[26] } {/theMem/\IRData_reg[25] } {/theMem/\IRData_reg[24] } {/theMem/\IRData_reg[23] } {/theMem/\IRData_reg[22] } {/theMem/\IRData_reg[21] } {/theMem/\IRData_reg[20] } {/theMem/\IRData_reg[19] } {/theMem/\IRData_reg[18] } {/theMem/\IRData_reg[17] } {/theMem/\IRData_reg[16] } {/theMem/\IRData_reg[15] } {/theMem/\IRData_reg[14] } {/theMem/\IRData_reg[13] } {/theMem/\IRData_reg[12] } {/theMem/\IRData_reg[11] } {/theMem/\IRData_reg[10] } {/theMem/\IRData_reg[9] } {/theMem/\IRData_reg[8] } {/theMem/\IRData_reg[7] } {/theMem/\IRData_reg[6] } {/theMem/\IRData_reg[5] } {/theMem/\IRData_reg[4] } {/theMem/\IRData_reg[3] } {/theMem/\IRData_reg[2] } {/theMem/\IRData_reg[1] } {/theMem/\IRData_reg[0] } {/theMem/\mem_addr_reg[10] } {/theMem/\mem_addr_reg[9] } {/theMem/\mem_addr_reg[8] } {/theMem/\mem_addr_reg[7] } {/theMem/\mem_addr_reg[6] } {/theMem/\mem_addr_reg[5] } {/theMem/\mem_addr_reg[4] } {/theMem/\mem_addr_reg[3] } {/theMem/\mem_addr_reg[2] } {/theMem/\mem_addr_reg[1] } {/theMem/\mem_addr_reg[0] } {/theMem/\drTmp_reg[31] } {/theMem/\drTmp_reg[30] } {/theMem/\drTmp_reg[29] } {/theMem/\drTmp_reg[28] } {/theMem/\drTmp_reg[27] } {/theMem/\drTmp_reg[26] } {/theMem/\drTmp_reg[25] } {/theMem/\drTmp_reg[24] } {/theMem/\drTmp_reg[23] } {/theMem/\drTmp_reg[22] } {/theMem/\drTmp_reg[21] } {/theMem/\drTmp_reg[20] } {/theMem/\drTmp_reg[19] } {/theMem/\drTmp_reg[18] } {/theMem/\drTmp_reg[17] } {/theMem/\drTmp_reg[16] } {/theMem/\drTmp_reg[15] } {/theMem/\drTmp_reg[14] } {/theMem/\drTmp_reg[13] } {/theMem/\drTmp_reg[12] } {/theMem/\drTmp_reg[11] } {/theMem/\drTmp_reg[10] } {/theMem/\drTmp_reg[9] } {/theMem/\drTmp_reg[8] } {/theMem/\drTmp_reg[7] } {/theMem/\drTmp_reg[6] } {/theMem/\drTmp_reg[5] } {/theMem/\drTmp_reg[4] } {/theMem/\drTmp_reg[3] } {/theMem/\drTmp_reg[2] } {/theMem/\drTmp_reg[1] } {/theMem/\drTmp_reg[0] } {/theMem/\mem_wdata_reg[31] } {/theMem/\mem_wdata_reg[30] } {/theMem/\mem_wdata_reg[29] } {/theMem/\mem_wdata_reg[28] } {/theMem/\mem_wdata_reg[27] } {/theMem/\mem_wdata_reg[26] } {/theMem/\mem_wdata_reg[25] } {/theMem/\mem_wdata_reg[24] } {/theMem/\mem_wdata_reg[23] } {/theMem/\mem_wdata_reg[22] } {/theMem/\mem_wdata_reg[21] } {/theMem/\mem_wdata_reg[20] } {/theMem/\mem_wdata_reg[19] } {/theMem/\mem_wdata_reg[18] } {/theMem/\mem_wdata_reg[17] } {/theMem/\mem_wdata_reg[16] } {/theMem/\mem_wdata_reg[15] } {/theMem/\mem_wdata_reg[14] } {/theMem/\mem_wdata_reg[13] } {/theMem/\mem_wdata_reg[12] } {/theMem/\mem_wdata_reg[11] } {/theMem/\mem_wdata_reg[10] } {/theMem/\mem_wdata_reg[9] } {/theMem/\mem_wdata_reg[8] } {/theMem/\mem_wdata_reg[7] } {/theMem/\mem_wdata_reg[6] } {/theMem/\mem_wdata_reg[5] } {/theMem/\mem_wdata_reg[4] } {/theMem/\mem_wdata_reg[3] } {/theMem/\mem_wdata_reg[2] } {/theMem/\mem_wdata_reg[1] } {/theMem/\mem_wdata_reg[0] } " +// sub-command: add_clocks 0 " clk_25mhz " +// sub-command: set_scan_enable scan_en -active high +// sub-command: add_input_constraints btn[0] -C1 +// sub-command: set_scan_enable scan_en -active high -cluster_name scanChain_1 +// sub-command: set_scan_enable scan_en -active high -cluster_name scanChain_2 +// sub-command: set_scan_enable scan_en -active high -cluster_name scanChain_3 +// sub-command: set_scan_enable scan_en -active high -cluster_name scanChain_4 +// sub-command: add_black_boxes -modules " MemGen_16_10 " +// sub-command: set_scan_insertion_options -single_clock_edge_chains on -si_port_format oas_ts_si[%d] -so_port_format oas_ts_so[%d] +// sub-command: set_system_mode analysis +// Warning: Rule FN1 violation occurs 157 times +// Warning: Rule FP13 violation occurs 1 times +// Flattening process completed, cell instances=4379, gates=18234, PIs=13, POs=12, CPU time=0.09 sec. +// --------------------------------------------------------------------------- +// Begin circuit learning analyses. +// -------------------------------- +// Learning completed, CPU time=0.01 sec. +// --------------------------------------------------------------------------- +// Begin scan chain identification process, memory elements = 1194, +// sequential library cells = 1194. +// --------------------------------------------------------------------------- +// Warning: Model 'DLH_X1_LVT' has no muxscan scan equivalent and is treated as nonscan model +// ------------------------------------------------------------------------------ +// 170 sequential library cells are treated as non-scan. +// ------------------------------------------------------------------------------ +// 63 sequential library cells missing mux-scan equivalent. +// 107 sequential library cells defined non-scan. +// --------------------------------------------------------------------------- +// Begin scannability rules checking for 1024 sequential library cells. +// --------------------------------------------------------------------------- +// 1024 sequential library cells identified as scannable. +// --------------------------------------------------------------------------- +// Begin transparent latch checking for 63 latches. +// --------------------------------------------------------------------------- +// Warning: 32 latches not transparent due to uncontrollable. (D6) +// Number transparent latches = 31. +// --------------------------------------------------------------------------- +// Begin scan clock rules checking. +// --------------------------------------------------------------------------- +// 1 scan clock/set/reset lines have been identified. +// All scan clocks successfully passed off-state check. +// 1131 sequential cells passed clock stability checking. +// There were 43 clock rule C3 fails (clock may capture data affected by its captured data). +// Note: Trailing edge triggered device can capture data affected by leading edge. +// --------------------------------------------------------------------------- +// 170 non-scan memory elements are identified. +// --------------------------------------------------------------------------- +// 32 non-scan memory elements are identified as TIE-X. (D5) +// 107 non-scan memory elements are identified as INIT-X. (D5) +// 31 non-scan memory elements are identified as TLA. (D5) +// --------------------------------------------------------------------------- +// Number of targeted sequential library cells = 1024 +// Warning: The tool may require a shift-capture clock during insertion, +// but no 'shift_capture_clock' DFT signal was identified +// and no TCLK source was specified using the command 'set_scan_signals -tclk'. +// Note: The system clock 'clk_25mhz' will be used as the shift-capture clock, if needed. +// sub-command: report_drc_rules +C3: #fails=43 handling=note (clock may capture data affected by its captured data) +D5: #fails=170 handling=warning (non-scan memory element) +D6: #fails=32 handling=warning (non-transparent non-scan latches) +// sub-command: create_scan_chain_family scanChain_1 -include_elements "{/\thePC_CurrentPC_reg[0] } {/\thePC_CurrentPC_reg[10] } {/\thePC_CurrentPC_reg[11] } {/\thePC_CurrentPC_reg[12] } {/\thePC_CurrentPC_reg[13] } {/\thePC_CurrentPC_reg[14] } {/\thePC_CurrentPC_reg[15] } {/\thePC_CurrentPC_reg[16] } {/\thePC_CurrentPC_reg[17] } {/\thePC_CurrentPC_reg[18] } {/\thePC_CurrentPC_reg[19] } {/\thePC_CurrentPC_reg[1] } {/\thePC_CurrentPC_reg[20] } {/\thePC_CurrentPC_reg[21] } {/\thePC_CurrentPC_reg[22] } {/\thePC_CurrentPC_reg[23] } {/\thePC_CurrentPC_reg[24] } {/\thePC_CurrentPC_reg[25] } {/\thePC_CurrentPC_reg[26] } {/\thePC_CurrentPC_reg[27] } {/\thePC_CurrentPC_reg[28] } {/\thePC_CurrentPC_reg[29] } {/\thePC_CurrentPC_reg[2] } {/\thePC_CurrentPC_reg[30] } {/\thePC_CurrentPC_reg[31] } {/\thePC_CurrentPC_reg[3] } {/\thePC_CurrentPC_reg[4] } {/\thePC_CurrentPC_reg[5] } {/\thePC_CurrentPC_reg[6] } {/\thePC_CurrentPC_reg[7] } {/\thePC_CurrentPC_reg[8] } {/\thePC_CurrentPC_reg[9] } {/theRegisters/\registers_reg[10][0] } {/theRegisters/\registers_reg[10][10] } {/theRegisters/\registers_reg[10][11] } {/theRegisters/\registers_reg[10][12] } {/theRegisters/\registers_reg[10][13] } {/theRegisters/\registers_reg[10][14] } {/theRegisters/\registers_reg[10][15] } {/theRegisters/\registers_reg[10][16] } {/theRegisters/\registers_reg[10][17] } {/theRegisters/\registers_reg[10][18] } {/theRegisters/\registers_reg[10][19] } {/theRegisters/\registers_reg[10][1] } {/theRegisters/\registers_reg[10][20] } {/theRegisters/\registers_reg[10][21] } {/theRegisters/\registers_reg[10][22] } {/theRegisters/\registers_reg[10][23] } {/theRegisters/\registers_reg[10][24] } {/theRegisters/\registers_reg[10][25] } {/theRegisters/\registers_reg[10][26] } {/theRegisters/\registers_reg[10][27] } {/theRegisters/\registers_reg[10][28] } {/theRegisters/\registers_reg[10][29] } {/theRegisters/\registers_reg[10][2] } {/theRegisters/\registers_reg[10][30] } {/theRegisters/\registers_reg[10][31] } {/theRegisters/\registers_reg[10][3] } {/theRegisters/\registers_reg[10][4] } {/theRegisters/\registers_reg[10][5] } {/theRegisters/\registers_reg[10][6] } {/theRegisters/\registers_reg[10][7] } {/theRegisters/\registers_reg[10][8] } {/theRegisters/\registers_reg[10][9] } {/theRegisters/\registers_reg[11][0] } {/theRegisters/\registers_reg[11][10] } {/theRegisters/\registers_reg[11][11] } {/theRegisters/\registers_reg[11][12] } {/theRegisters/\registers_reg[11][13] } {/theRegisters/\registers_reg[11][14] } {/theRegisters/\registers_reg[11][15] } {/theRegisters/\registers_reg[11][16] } {/theRegisters/\registers_reg[11][17] } {/theRegisters/\registers_reg[11][18] } {/theRegisters/\registers_reg[11][19] } {/theRegisters/\registers_reg[11][1] } {/theRegisters/\registers_reg[11][20] } {/theRegisters/\registers_reg[11][21] } {/theRegisters/\registers_reg[11][22] } {/theRegisters/\registers_reg[11][23] } {/theRegisters/\registers_reg[11][24] } {/theRegisters/\registers_reg[11][25] } {/theRegisters/\registers_reg[11][26] } {/theRegisters/\registers_reg[11][27] } {/theRegisters/\registers_reg[11][28] } {/theRegisters/\registers_reg[11][29] } {/theRegisters/\registers_reg[11][2] } {/theRegisters/\registers_reg[11][30] } {/theRegisters/\registers_reg[11][31] } {/theRegisters/\registers_reg[11][3] } {/theRegisters/\registers_reg[11][4] } {/theRegisters/\registers_reg[11][5] } {/theRegisters/\registers_reg[11][6] } {/theRegisters/\registers_reg[11][7] } {/theRegisters/\registers_reg[11][8] } {/theRegisters/\registers_reg[11][9] } {/theRegisters/\registers_reg[12][0] } {/theRegisters/\registers_reg[12][10] } {/theRegisters/\registers_reg[12][11] } {/theRegisters/\registers_reg[12][12] } {/theRegisters/\registers_reg[12][13] } {/theRegisters/\registers_reg[12][14] } {/theRegisters/\registers_reg[12][15] } {/theRegisters/\registers_reg[12][16] } {/theRegisters/\registers_reg[12][17] } {/theRegisters/\registers_reg[12][18] } {/theRegisters/\registers_reg[12][19] } {/theRegisters/\registers_reg[12][1] } {/theRegisters/\registers_reg[12][20] } {/theRegisters/\registers_reg[12][21] } {/theRegisters/\registers_reg[12][22] } {/theRegisters/\registers_reg[12][23] } {/theRegisters/\registers_reg[12][24] } {/theRegisters/\registers_reg[12][25] } {/theRegisters/\registers_reg[12][26] } {/theRegisters/\registers_reg[12][27] } {/theRegisters/\registers_reg[12][28] } {/theRegisters/\registers_reg[12][29] } {/theRegisters/\registers_reg[12][2] } {/theRegisters/\registers_reg[12][30] } {/theRegisters/\registers_reg[12][31] } {/theRegisters/\registers_reg[12][3] } {/theRegisters/\registers_reg[12][4] } {/theRegisters/\registers_reg[12][5] } {/theRegisters/\registers_reg[12][6] } {/theRegisters/\registers_reg[12][7] } {/theRegisters/\registers_reg[12][8] } {/theRegisters/\registers_reg[12][9] } {/theRegisters/\registers_reg[13][0] } {/theRegisters/\registers_reg[13][10] } {/theRegisters/\registers_reg[13][11] } {/theRegisters/\registers_reg[13][12] } {/theRegisters/\registers_reg[13][13] } {/theRegisters/\registers_reg[13][14] } {/theRegisters/\registers_reg[13][15] } {/theRegisters/\registers_reg[13][16] } {/theRegisters/\registers_reg[13][17] } {/theRegisters/\registers_reg[13][18] } {/theRegisters/\registers_reg[13][19] } {/theRegisters/\registers_reg[13][1] } {/theRegisters/\registers_reg[13][20] } {/theRegisters/\registers_reg[13][21] } {/theRegisters/\registers_reg[13][22] } {/theRegisters/\registers_reg[13][23] } {/theRegisters/\registers_reg[13][24] } {/theRegisters/\registers_reg[13][25] } {/theRegisters/\registers_reg[13][26] } {/theRegisters/\registers_reg[13][27] } {/theRegisters/\registers_reg[13][28] } {/theRegisters/\registers_reg[13][29] } {/theRegisters/\registers_reg[13][2] } {/theRegisters/\registers_reg[13][30] } {/theRegisters/\registers_reg[13][31] } {/theRegisters/\registers_reg[13][3] } {/theRegisters/\registers_reg[13][4] } {/theRegisters/\registers_reg[13][5] } {/theRegisters/\registers_reg[13][6] } {/theRegisters/\registers_reg[13][7] } {/theRegisters/\registers_reg[13][8] } {/theRegisters/\registers_reg[13][9] } {/theRegisters/\registers_reg[14][0] } {/theRegisters/\registers_reg[14][10] } {/theRegisters/\registers_reg[14][11] } {/theRegisters/\registers_reg[14][12] } {/theRegisters/\registers_reg[14][13] } {/theRegisters/\registers_reg[14][14] } {/theRegisters/\registers_reg[14][15] } {/theRegisters/\registers_reg[14][16] } {/theRegisters/\registers_reg[14][17] } {/theRegisters/\registers_reg[14][18] } {/theRegisters/\registers_reg[14][19] } {/theRegisters/\registers_reg[14][1] } {/theRegisters/\registers_reg[14][20] } {/theRegisters/\registers_reg[14][21] } {/theRegisters/\registers_reg[14][22] } {/theRegisters/\registers_reg[14][23] } {/theRegisters/\registers_reg[14][24] } {/theRegisters/\registers_reg[14][25] } {/theRegisters/\registers_reg[14][26] } {/theRegisters/\registers_reg[14][27] } {/theRegisters/\registers_reg[14][28] } {/theRegisters/\registers_reg[14][29] } {/theRegisters/\registers_reg[14][2] } {/theRegisters/\registers_reg[14][30] } {/theRegisters/\registers_reg[14][31] } {/theRegisters/\registers_reg[14][3] } {/theRegisters/\registers_reg[14][4] } {/theRegisters/\registers_reg[14][5] } {/theRegisters/\registers_reg[14][6] } {/theRegisters/\registers_reg[14][7] } {/theRegisters/\registers_reg[14][8] } {/theRegisters/\registers_reg[14][9] } {/theRegisters/\registers_reg[15][0] } {/theRegisters/\registers_reg[15][10] } {/theRegisters/\registers_reg[15][11] } {/theRegisters/\registers_reg[15][12] } {/theRegisters/\registers_reg[15][13] } {/theRegisters/\registers_reg[15][14] } {/theRegisters/\registers_reg[15][15] } {/theRegisters/\registers_reg[15][16] } {/theRegisters/\registers_reg[15][17] } {/theRegisters/\registers_reg[15][18] } {/theRegisters/\registers_reg[15][19] } {/theRegisters/\registers_reg[15][1] } {/theRegisters/\registers_reg[15][20] } {/theRegisters/\registers_reg[15][21] } {/theRegisters/\registers_reg[15][22] } {/theRegisters/\registers_reg[15][23] } {/theRegisters/\registers_reg[15][24] } {/theRegisters/\registers_reg[15][25] } {/theRegisters/\registers_reg[15][26] } {/theRegisters/\registers_reg[15][27] } {/theRegisters/\registers_reg[15][28] } {/theRegisters/\registers_reg[15][29] } {/theRegisters/\registers_reg[15][2] } {/theRegisters/\registers_reg[15][30] } {/theRegisters/\registers_reg[15][31] } {/theRegisters/\registers_reg[15][3] } {/theRegisters/\registers_reg[15][4] } {/theRegisters/\registers_reg[15][5] } {/theRegisters/\registers_reg[15][6] } {/theRegisters/\registers_reg[15][7] } {/theRegisters/\registers_reg[15][8] } {/theRegisters/\registers_reg[15][9] } {/theRegisters/\registers_reg[16][0] } {/theRegisters/\registers_reg[16][10] } {/theRegisters/\registers_reg[16][11] } {/theRegisters/\registers_reg[16][12] } {/theRegisters/\registers_reg[16][13] } {/theRegisters/\registers_reg[16][14] } {/theRegisters/\registers_reg[16][15] } {/theRegisters/\registers_reg[16][16] } {/theRegisters/\registers_reg[16][17] } {/theRegisters/\registers_reg[16][18] } {/theRegisters/\registers_reg[16][19] } {/theRegisters/\registers_reg[16][1] } {/theRegisters/\registers_reg[16][20] } {/theRegisters/\registers_reg[16][21] } {/theRegisters/\registers_reg[16][22] } {/theRegisters/\registers_reg[16][23] } {/theRegisters/\registers_reg[16][24] } {/theRegisters/\registers_reg[16][25] } {/theRegisters/\registers_reg[16][26] } {/theRegisters/\registers_reg[16][27] } {/theRegisters/\registers_reg[16][28] } {/theRegisters/\registers_reg[16][29] } {/theRegisters/\registers_reg[16][2] } {/theRegisters/\registers_reg[16][30] } {/theRegisters/\registers_reg[16][31] } {/theRegisters/\registers_reg[16][3] } {/theRegisters/\registers_reg[16][4] } {/theRegisters/\registers_reg[16][5] } {/theRegisters/\registers_reg[16][6] } {/theRegisters/\registers_reg[16][7] } {/theRegisters/\registers_reg[16][8] } {/theRegisters/\registers_reg[16][9] } " -si_connections "SI_1 " -so_connections "SO_1 " -chain_count 1 +// sub-command: create_scan_chain_family scanChain_2 -include_elements "{/theRegisters/\registers_reg[17][0] } {/theRegisters/\registers_reg[17][10] } {/theRegisters/\registers_reg[17][11] } {/theRegisters/\registers_reg[17][12] } {/theRegisters/\registers_reg[17][13] } {/theRegisters/\registers_reg[17][14] } {/theRegisters/\registers_reg[17][15] } {/theRegisters/\registers_reg[17][16] } {/theRegisters/\registers_reg[17][17] } {/theRegisters/\registers_reg[17][18] } {/theRegisters/\registers_reg[17][19] } {/theRegisters/\registers_reg[17][1] } {/theRegisters/\registers_reg[17][20] } {/theRegisters/\registers_reg[17][21] } {/theRegisters/\registers_reg[17][22] } {/theRegisters/\registers_reg[17][23] } {/theRegisters/\registers_reg[17][24] } {/theRegisters/\registers_reg[17][25] } {/theRegisters/\registers_reg[17][26] } {/theRegisters/\registers_reg[17][27] } {/theRegisters/\registers_reg[17][28] } {/theRegisters/\registers_reg[17][29] } {/theRegisters/\registers_reg[17][2] } {/theRegisters/\registers_reg[17][30] } {/theRegisters/\registers_reg[17][31] } {/theRegisters/\registers_reg[17][3] } {/theRegisters/\registers_reg[17][4] } {/theRegisters/\registers_reg[17][5] } {/theRegisters/\registers_reg[17][6] } {/theRegisters/\registers_reg[17][7] } {/theRegisters/\registers_reg[17][8] } {/theRegisters/\registers_reg[17][9] } {/theRegisters/\registers_reg[18][0] } {/theRegisters/\registers_reg[18][10] } {/theRegisters/\registers_reg[18][11] } {/theRegisters/\registers_reg[18][12] } {/theRegisters/\registers_reg[18][13] } {/theRegisters/\registers_reg[18][14] } {/theRegisters/\registers_reg[18][15] } {/theRegisters/\registers_reg[18][16] } {/theRegisters/\registers_reg[18][17] } {/theRegisters/\registers_reg[18][18] } {/theRegisters/\registers_reg[18][19] } {/theRegisters/\registers_reg[18][1] } {/theRegisters/\registers_reg[18][20] } {/theRegisters/\registers_reg[18][21] } {/theRegisters/\registers_reg[18][22] } {/theRegisters/\registers_reg[18][23] } {/theRegisters/\registers_reg[18][24] } {/theRegisters/\registers_reg[18][25] } {/theRegisters/\registers_reg[18][26] } {/theRegisters/\registers_reg[18][27] } {/theRegisters/\registers_reg[18][28] } {/theRegisters/\registers_reg[18][29] } {/theRegisters/\registers_reg[18][2] } {/theRegisters/\registers_reg[18][30] } {/theRegisters/\registers_reg[18][31] } {/theRegisters/\registers_reg[18][3] } {/theRegisters/\registers_reg[18][4] } {/theRegisters/\registers_reg[18][5] } {/theRegisters/\registers_reg[18][6] } {/theRegisters/\registers_reg[18][7] } {/theRegisters/\registers_reg[18][8] } {/theRegisters/\registers_reg[18][9] } {/theRegisters/\registers_reg[19][0] } {/theRegisters/\registers_reg[19][10] } {/theRegisters/\registers_reg[19][11] } {/theRegisters/\registers_reg[19][12] } {/theRegisters/\registers_reg[19][13] } {/theRegisters/\registers_reg[19][14] } {/theRegisters/\registers_reg[19][15] } {/theRegisters/\registers_reg[19][16] } {/theRegisters/\registers_reg[19][17] } {/theRegisters/\registers_reg[19][18] } {/theRegisters/\registers_reg[19][19] } {/theRegisters/\registers_reg[19][1] } {/theRegisters/\registers_reg[19][20] } {/theRegisters/\registers_reg[19][21] } {/theRegisters/\registers_reg[19][22] } {/theRegisters/\registers_reg[19][23] } {/theRegisters/\registers_reg[19][24] } {/theRegisters/\registers_reg[19][25] } {/theRegisters/\registers_reg[19][26] } {/theRegisters/\registers_reg[19][27] } {/theRegisters/\registers_reg[19][28] } {/theRegisters/\registers_reg[19][29] } {/theRegisters/\registers_reg[19][2] } {/theRegisters/\registers_reg[19][30] } {/theRegisters/\registers_reg[19][31] } {/theRegisters/\registers_reg[19][3] } {/theRegisters/\registers_reg[19][4] } {/theRegisters/\registers_reg[19][5] } {/theRegisters/\registers_reg[19][6] } {/theRegisters/\registers_reg[19][7] } {/theRegisters/\registers_reg[19][8] } {/theRegisters/\registers_reg[19][9] } {/theRegisters/\registers_reg[1][0] } {/theRegisters/\registers_reg[1][10] } {/theRegisters/\registers_reg[1][11] } {/theRegisters/\registers_reg[1][12] } {/theRegisters/\registers_reg[1][13] } {/theRegisters/\registers_reg[1][14] } {/theRegisters/\registers_reg[1][15] } {/theRegisters/\registers_reg[1][16] } {/theRegisters/\registers_reg[1][17] } {/theRegisters/\registers_reg[1][18] } {/theRegisters/\registers_reg[1][19] } {/theRegisters/\registers_reg[1][1] } {/theRegisters/\registers_reg[1][20] } {/theRegisters/\registers_reg[1][21] } {/theRegisters/\registers_reg[1][22] } {/theRegisters/\registers_reg[1][23] } {/theRegisters/\registers_reg[1][24] } {/theRegisters/\registers_reg[1][25] } {/theRegisters/\registers_reg[1][26] } {/theRegisters/\registers_reg[1][27] } {/theRegisters/\registers_reg[1][28] } {/theRegisters/\registers_reg[1][29] } {/theRegisters/\registers_reg[1][2] } {/theRegisters/\registers_reg[1][30] } {/theRegisters/\registers_reg[1][31] } {/theRegisters/\registers_reg[1][3] } {/theRegisters/\registers_reg[1][4] } {/theRegisters/\registers_reg[1][5] } {/theRegisters/\registers_reg[1][6] } {/theRegisters/\registers_reg[1][7] } {/theRegisters/\registers_reg[1][8] } {/theRegisters/\registers_reg[1][9] } {/theRegisters/\registers_reg[20][0] } {/theRegisters/\registers_reg[20][10] } {/theRegisters/\registers_reg[20][11] } {/theRegisters/\registers_reg[20][12] } {/theRegisters/\registers_reg[20][13] } {/theRegisters/\registers_reg[20][14] } {/theRegisters/\registers_reg[20][15] } {/theRegisters/\registers_reg[20][16] } {/theRegisters/\registers_reg[20][17] } {/theRegisters/\registers_reg[20][18] } {/theRegisters/\registers_reg[20][19] } {/theRegisters/\registers_reg[20][1] } {/theRegisters/\registers_reg[20][20] } {/theRegisters/\registers_reg[20][21] } {/theRegisters/\registers_reg[20][22] } {/theRegisters/\registers_reg[20][23] } {/theRegisters/\registers_reg[20][24] } {/theRegisters/\registers_reg[20][25] } {/theRegisters/\registers_reg[20][26] } {/theRegisters/\registers_reg[20][27] } {/theRegisters/\registers_reg[20][28] } {/theRegisters/\registers_reg[20][29] } {/theRegisters/\registers_reg[20][2] } {/theRegisters/\registers_reg[20][30] } {/theRegisters/\registers_reg[20][31] } {/theRegisters/\registers_reg[20][3] } {/theRegisters/\registers_reg[20][4] } {/theRegisters/\registers_reg[20][5] } {/theRegisters/\registers_reg[20][6] } {/theRegisters/\registers_reg[20][7] } {/theRegisters/\registers_reg[20][8] } {/theRegisters/\registers_reg[20][9] } {/theRegisters/\registers_reg[21][0] } {/theRegisters/\registers_reg[21][10] } {/theRegisters/\registers_reg[21][11] } {/theRegisters/\registers_reg[21][12] } {/theRegisters/\registers_reg[21][13] } {/theRegisters/\registers_reg[21][14] } {/theRegisters/\registers_reg[21][15] } {/theRegisters/\registers_reg[21][16] } {/theRegisters/\registers_reg[21][17] } {/theRegisters/\registers_reg[21][18] } {/theRegisters/\registers_reg[21][19] } {/theRegisters/\registers_reg[21][1] } {/theRegisters/\registers_reg[21][20] } {/theRegisters/\registers_reg[21][21] } {/theRegisters/\registers_reg[21][22] } {/theRegisters/\registers_reg[21][23] } {/theRegisters/\registers_reg[21][24] } {/theRegisters/\registers_reg[21][25] } {/theRegisters/\registers_reg[21][26] } {/theRegisters/\registers_reg[21][27] } {/theRegisters/\registers_reg[21][28] } {/theRegisters/\registers_reg[21][29] } {/theRegisters/\registers_reg[21][2] } {/theRegisters/\registers_reg[21][30] } {/theRegisters/\registers_reg[21][31] } {/theRegisters/\registers_reg[21][3] } {/theRegisters/\registers_reg[21][4] } {/theRegisters/\registers_reg[21][5] } {/theRegisters/\registers_reg[21][6] } {/theRegisters/\registers_reg[21][7] } {/theRegisters/\registers_reg[21][8] } {/theRegisters/\registers_reg[21][9] } {/theRegisters/\registers_reg[22][0] } {/theRegisters/\registers_reg[22][10] } {/theRegisters/\registers_reg[22][11] } {/theRegisters/\registers_reg[22][12] } {/theRegisters/\registers_reg[22][13] } {/theRegisters/\registers_reg[22][14] } {/theRegisters/\registers_reg[22][15] } {/theRegisters/\registers_reg[22][16] } {/theRegisters/\registers_reg[22][17] } {/theRegisters/\registers_reg[22][18] } {/theRegisters/\registers_reg[22][19] } {/theRegisters/\registers_reg[22][1] } {/theRegisters/\registers_reg[22][20] } {/theRegisters/\registers_reg[22][21] } {/theRegisters/\registers_reg[22][22] } {/theRegisters/\registers_reg[22][23] } {/theRegisters/\registers_reg[22][24] } {/theRegisters/\registers_reg[22][25] } {/theRegisters/\registers_reg[22][26] } {/theRegisters/\registers_reg[22][27] } {/theRegisters/\registers_reg[22][28] } {/theRegisters/\registers_reg[22][29] } {/theRegisters/\registers_reg[22][2] } {/theRegisters/\registers_reg[22][30] } {/theRegisters/\registers_reg[22][31] } {/theRegisters/\registers_reg[22][3] } {/theRegisters/\registers_reg[22][4] } {/theRegisters/\registers_reg[22][5] } {/theRegisters/\registers_reg[22][6] } {/theRegisters/\registers_reg[22][7] } {/theRegisters/\registers_reg[22][8] } {/theRegisters/\registers_reg[22][9] } {/theRegisters/\registers_reg[23][0] } {/theRegisters/\registers_reg[23][10] } {/theRegisters/\registers_reg[23][11] } {/theRegisters/\registers_reg[23][12] } {/theRegisters/\registers_reg[23][13] } {/theRegisters/\registers_reg[23][14] } {/theRegisters/\registers_reg[23][15] } {/theRegisters/\registers_reg[23][16] } {/theRegisters/\registers_reg[23][17] } {/theRegisters/\registers_reg[23][18] } {/theRegisters/\registers_reg[23][19] } {/theRegisters/\registers_reg[23][1] } {/theRegisters/\registers_reg[23][20] } {/theRegisters/\registers_reg[23][21] } {/theRegisters/\registers_reg[23][22] } {/theRegisters/\registers_reg[23][23] } {/theRegisters/\registers_reg[23][24] } {/theRegisters/\registers_reg[23][25] } {/theRegisters/\registers_reg[23][26] } {/theRegisters/\registers_reg[23][27] } {/theRegisters/\registers_reg[23][28] } {/theRegisters/\registers_reg[23][29] } {/theRegisters/\registers_reg[23][2] } {/theRegisters/\registers_reg[23][30] } {/theRegisters/\registers_reg[23][31] } {/theRegisters/\registers_reg[23][3] } {/theRegisters/\registers_reg[23][4] } {/theRegisters/\registers_reg[23][5] } {/theRegisters/\registers_reg[23][6] } {/theRegisters/\registers_reg[23][7] } {/theRegisters/\registers_reg[23][8] } {/theRegisters/\registers_reg[23][9] } " -si_connections "SI_2 " -so_connections "SO_2 " -chain_count 1 +// sub-command: create_scan_chain_family scanChain_3 -include_elements "{/theRegisters/\registers_reg[24][0] } {/theRegisters/\registers_reg[24][10] } {/theRegisters/\registers_reg[24][11] } {/theRegisters/\registers_reg[24][12] } {/theRegisters/\registers_reg[24][13] } {/theRegisters/\registers_reg[24][14] } {/theRegisters/\registers_reg[24][15] } {/theRegisters/\registers_reg[24][16] } {/theRegisters/\registers_reg[24][17] } {/theRegisters/\registers_reg[24][18] } {/theRegisters/\registers_reg[24][19] } {/theRegisters/\registers_reg[24][1] } {/theRegisters/\registers_reg[24][20] } {/theRegisters/\registers_reg[24][21] } {/theRegisters/\registers_reg[24][22] } {/theRegisters/\registers_reg[24][23] } {/theRegisters/\registers_reg[24][24] } {/theRegisters/\registers_reg[24][25] } {/theRegisters/\registers_reg[24][26] } {/theRegisters/\registers_reg[24][27] } {/theRegisters/\registers_reg[24][28] } {/theRegisters/\registers_reg[24][29] } {/theRegisters/\registers_reg[24][2] } {/theRegisters/\registers_reg[24][30] } {/theRegisters/\registers_reg[24][31] } {/theRegisters/\registers_reg[24][3] } {/theRegisters/\registers_reg[24][4] } {/theRegisters/\registers_reg[24][5] } {/theRegisters/\registers_reg[24][6] } {/theRegisters/\registers_reg[24][7] } {/theRegisters/\registers_reg[24][8] } {/theRegisters/\registers_reg[24][9] } {/theRegisters/\registers_reg[25][0] } {/theRegisters/\registers_reg[25][10] } {/theRegisters/\registers_reg[25][11] } {/theRegisters/\registers_reg[25][12] } {/theRegisters/\registers_reg[25][13] } {/theRegisters/\registers_reg[25][14] } {/theRegisters/\registers_reg[25][15] } {/theRegisters/\registers_reg[25][16] } {/theRegisters/\registers_reg[25][17] } {/theRegisters/\registers_reg[25][18] } {/theRegisters/\registers_reg[25][19] } {/theRegisters/\registers_reg[25][1] } {/theRegisters/\registers_reg[25][20] } {/theRegisters/\registers_reg[25][21] } {/theRegisters/\registers_reg[25][22] } {/theRegisters/\registers_reg[25][23] } {/theRegisters/\registers_reg[25][24] } {/theRegisters/\registers_reg[25][25] } {/theRegisters/\registers_reg[25][26] } {/theRegisters/\registers_reg[25][27] } {/theRegisters/\registers_reg[25][28] } {/theRegisters/\registers_reg[25][29] } {/theRegisters/\registers_reg[25][2] } {/theRegisters/\registers_reg[25][30] } {/theRegisters/\registers_reg[25][31] } {/theRegisters/\registers_reg[25][3] } {/theRegisters/\registers_reg[25][4] } {/theRegisters/\registers_reg[25][5] } {/theRegisters/\registers_reg[25][6] } {/theRegisters/\registers_reg[25][7] } {/theRegisters/\registers_reg[25][8] } {/theRegisters/\registers_reg[25][9] } {/theRegisters/\registers_reg[26][0] } {/theRegisters/\registers_reg[26][10] } {/theRegisters/\registers_reg[26][11] } {/theRegisters/\registers_reg[26][12] } {/theRegisters/\registers_reg[26][13] } {/theRegisters/\registers_reg[26][14] } {/theRegisters/\registers_reg[26][15] } {/theRegisters/\registers_reg[26][16] } {/theRegisters/\registers_reg[26][17] } {/theRegisters/\registers_reg[26][18] } {/theRegisters/\registers_reg[26][19] } {/theRegisters/\registers_reg[26][1] } {/theRegisters/\registers_reg[26][20] } {/theRegisters/\registers_reg[26][21] } {/theRegisters/\registers_reg[26][22] } {/theRegisters/\registers_reg[26][23] } {/theRegisters/\registers_reg[26][24] } {/theRegisters/\registers_reg[26][25] } {/theRegisters/\registers_reg[26][26] } {/theRegisters/\registers_reg[26][27] } {/theRegisters/\registers_reg[26][28] } {/theRegisters/\registers_reg[26][29] } {/theRegisters/\registers_reg[26][2] } {/theRegisters/\registers_reg[26][30] } {/theRegisters/\registers_reg[26][31] } {/theRegisters/\registers_reg[26][3] } {/theRegisters/\registers_reg[26][4] } {/theRegisters/\registers_reg[26][5] } {/theRegisters/\registers_reg[26][6] } {/theRegisters/\registers_reg[26][7] } {/theRegisters/\registers_reg[26][8] } {/theRegisters/\registers_reg[26][9] } {/theRegisters/\registers_reg[27][0] } {/theRegisters/\registers_reg[27][10] } {/theRegisters/\registers_reg[27][11] } {/theRegisters/\registers_reg[27][12] } {/theRegisters/\registers_reg[27][13] } {/theRegisters/\registers_reg[27][14] } {/theRegisters/\registers_reg[27][15] } {/theRegisters/\registers_reg[27][16] } {/theRegisters/\registers_reg[27][17] } {/theRegisters/\registers_reg[27][18] } {/theRegisters/\registers_reg[27][19] } {/theRegisters/\registers_reg[27][1] } {/theRegisters/\registers_reg[27][20] } {/theRegisters/\registers_reg[27][21] } {/theRegisters/\registers_reg[27][22] } {/theRegisters/\registers_reg[27][23] } {/theRegisters/\registers_reg[27][24] } {/theRegisters/\registers_reg[27][25] } {/theRegisters/\registers_reg[27][26] } {/theRegisters/\registers_reg[27][27] } {/theRegisters/\registers_reg[27][28] } {/theRegisters/\registers_reg[27][29] } {/theRegisters/\registers_reg[27][2] } {/theRegisters/\registers_reg[27][30] } {/theRegisters/\registers_reg[27][31] } {/theRegisters/\registers_reg[27][3] } {/theRegisters/\registers_reg[27][4] } {/theRegisters/\registers_reg[27][5] } {/theRegisters/\registers_reg[27][6] } {/theRegisters/\registers_reg[27][7] } {/theRegisters/\registers_reg[27][8] } {/theRegisters/\registers_reg[27][9] } {/theRegisters/\registers_reg[28][0] } {/theRegisters/\registers_reg[28][10] } {/theRegisters/\registers_reg[28][11] } {/theRegisters/\registers_reg[28][12] } {/theRegisters/\registers_reg[28][13] } {/theRegisters/\registers_reg[28][14] } {/theRegisters/\registers_reg[28][15] } {/theRegisters/\registers_reg[28][16] } {/theRegisters/\registers_reg[28][17] } {/theRegisters/\registers_reg[28][18] } {/theRegisters/\registers_reg[28][19] } {/theRegisters/\registers_reg[28][1] } {/theRegisters/\registers_reg[28][20] } {/theRegisters/\registers_reg[28][21] } {/theRegisters/\registers_reg[28][22] } {/theRegisters/\registers_reg[28][23] } {/theRegisters/\registers_reg[28][24] } {/theRegisters/\registers_reg[28][25] } {/theRegisters/\registers_reg[28][26] } {/theRegisters/\registers_reg[28][27] } {/theRegisters/\registers_reg[28][28] } {/theRegisters/\registers_reg[28][29] } {/theRegisters/\registers_reg[28][2] } {/theRegisters/\registers_reg[28][30] } {/theRegisters/\registers_reg[28][31] } {/theRegisters/\registers_reg[28][3] } {/theRegisters/\registers_reg[28][4] } {/theRegisters/\registers_reg[28][5] } {/theRegisters/\registers_reg[28][6] } {/theRegisters/\registers_reg[28][7] } {/theRegisters/\registers_reg[28][8] } {/theRegisters/\registers_reg[28][9] } {/theRegisters/\registers_reg[29][0] } {/theRegisters/\registers_reg[29][10] } {/theRegisters/\registers_reg[29][11] } {/theRegisters/\registers_reg[29][12] } {/theRegisters/\registers_reg[29][13] } {/theRegisters/\registers_reg[29][14] } {/theRegisters/\registers_reg[29][15] } {/theRegisters/\registers_reg[29][16] } {/theRegisters/\registers_reg[29][17] } {/theRegisters/\registers_reg[29][18] } {/theRegisters/\registers_reg[29][19] } {/theRegisters/\registers_reg[29][1] } {/theRegisters/\registers_reg[29][20] } {/theRegisters/\registers_reg[29][21] } {/theRegisters/\registers_reg[29][22] } {/theRegisters/\registers_reg[29][23] } {/theRegisters/\registers_reg[29][24] } {/theRegisters/\registers_reg[29][25] } {/theRegisters/\registers_reg[29][26] } {/theRegisters/\registers_reg[29][27] } {/theRegisters/\registers_reg[29][28] } {/theRegisters/\registers_reg[29][29] } {/theRegisters/\registers_reg[29][2] } {/theRegisters/\registers_reg[29][30] } {/theRegisters/\registers_reg[29][31] } {/theRegisters/\registers_reg[29][3] } {/theRegisters/\registers_reg[29][4] } {/theRegisters/\registers_reg[29][5] } {/theRegisters/\registers_reg[29][6] } {/theRegisters/\registers_reg[29][7] } {/theRegisters/\registers_reg[29][8] } {/theRegisters/\registers_reg[29][9] } {/theRegisters/\registers_reg[2][0] } {/theRegisters/\registers_reg[2][10] } {/theRegisters/\registers_reg[2][11] } {/theRegisters/\registers_reg[2][12] } {/theRegisters/\registers_reg[2][13] } {/theRegisters/\registers_reg[2][14] } {/theRegisters/\registers_reg[2][15] } {/theRegisters/\registers_reg[2][16] } {/theRegisters/\registers_reg[2][17] } {/theRegisters/\registers_reg[2][18] } {/theRegisters/\registers_reg[2][19] } {/theRegisters/\registers_reg[2][1] } {/theRegisters/\registers_reg[2][20] } {/theRegisters/\registers_reg[2][21] } {/theRegisters/\registers_reg[2][22] } {/theRegisters/\registers_reg[2][23] } {/theRegisters/\registers_reg[2][24] } {/theRegisters/\registers_reg[2][25] } {/theRegisters/\registers_reg[2][26] } {/theRegisters/\registers_reg[2][27] } {/theRegisters/\registers_reg[2][28] } {/theRegisters/\registers_reg[2][29] } {/theRegisters/\registers_reg[2][2] } {/theRegisters/\registers_reg[2][30] } {/theRegisters/\registers_reg[2][31] } {/theRegisters/\registers_reg[2][3] } {/theRegisters/\registers_reg[2][4] } {/theRegisters/\registers_reg[2][5] } {/theRegisters/\registers_reg[2][6] } {/theRegisters/\registers_reg[2][7] } {/theRegisters/\registers_reg[2][8] } {/theRegisters/\registers_reg[2][9] } {/theRegisters/\registers_reg[30][0] } {/theRegisters/\registers_reg[30][10] } {/theRegisters/\registers_reg[30][11] } {/theRegisters/\registers_reg[30][12] } {/theRegisters/\registers_reg[30][13] } {/theRegisters/\registers_reg[30][14] } {/theRegisters/\registers_reg[30][15] } {/theRegisters/\registers_reg[30][16] } {/theRegisters/\registers_reg[30][17] } {/theRegisters/\registers_reg[30][18] } {/theRegisters/\registers_reg[30][19] } {/theRegisters/\registers_reg[30][1] } {/theRegisters/\registers_reg[30][20] } {/theRegisters/\registers_reg[30][21] } {/theRegisters/\registers_reg[30][22] } {/theRegisters/\registers_reg[30][23] } {/theRegisters/\registers_reg[30][24] } {/theRegisters/\registers_reg[30][25] } {/theRegisters/\registers_reg[30][26] } {/theRegisters/\registers_reg[30][27] } {/theRegisters/\registers_reg[30][28] } {/theRegisters/\registers_reg[30][29] } {/theRegisters/\registers_reg[30][2] } {/theRegisters/\registers_reg[30][30] } {/theRegisters/\registers_reg[30][31] } {/theRegisters/\registers_reg[30][3] } {/theRegisters/\registers_reg[30][4] } {/theRegisters/\registers_reg[30][5] } {/theRegisters/\registers_reg[30][6] } {/theRegisters/\registers_reg[30][7] } {/theRegisters/\registers_reg[30][8] } {/theRegisters/\registers_reg[30][9] } " -si_connections "SI_3 " -so_connections "SO_3 " -chain_count 1 +// sub-command: create_scan_chain_family scanChain_4 -include_elements "{/theRegisters/\registers_reg[31][0] } {/theRegisters/\registers_reg[31][10] } {/theRegisters/\registers_reg[31][11] } {/theRegisters/\registers_reg[31][12] } {/theRegisters/\registers_reg[31][13] } {/theRegisters/\registers_reg[31][14] } {/theRegisters/\registers_reg[31][15] } {/theRegisters/\registers_reg[31][16] } {/theRegisters/\registers_reg[31][17] } {/theRegisters/\registers_reg[31][18] } {/theRegisters/\registers_reg[31][19] } {/theRegisters/\registers_reg[31][1] } {/theRegisters/\registers_reg[31][20] } {/theRegisters/\registers_reg[31][21] } {/theRegisters/\registers_reg[31][22] } {/theRegisters/\registers_reg[31][23] } {/theRegisters/\registers_reg[31][24] } {/theRegisters/\registers_reg[31][25] } {/theRegisters/\registers_reg[31][26] } {/theRegisters/\registers_reg[31][27] } {/theRegisters/\registers_reg[31][28] } {/theRegisters/\registers_reg[31][29] } {/theRegisters/\registers_reg[31][2] } {/theRegisters/\registers_reg[31][30] } {/theRegisters/\registers_reg[31][31] } {/theRegisters/\registers_reg[31][3] } {/theRegisters/\registers_reg[31][4] } {/theRegisters/\registers_reg[31][5] } {/theRegisters/\registers_reg[31][6] } {/theRegisters/\registers_reg[31][7] } {/theRegisters/\registers_reg[31][8] } {/theRegisters/\registers_reg[31][9] } {/theRegisters/\registers_reg[3][0] } {/theRegisters/\registers_reg[3][10] } {/theRegisters/\registers_reg[3][11] } {/theRegisters/\registers_reg[3][12] } {/theRegisters/\registers_reg[3][13] } {/theRegisters/\registers_reg[3][14] } {/theRegisters/\registers_reg[3][15] } {/theRegisters/\registers_reg[3][16] } {/theRegisters/\registers_reg[3][17] } {/theRegisters/\registers_reg[3][18] } {/theRegisters/\registers_reg[3][19] } {/theRegisters/\registers_reg[3][1] } {/theRegisters/\registers_reg[3][20] } {/theRegisters/\registers_reg[3][21] } {/theRegisters/\registers_reg[3][22] } {/theRegisters/\registers_reg[3][23] } {/theRegisters/\registers_reg[3][24] } {/theRegisters/\registers_reg[3][25] } {/theRegisters/\registers_reg[3][26] } {/theRegisters/\registers_reg[3][27] } {/theRegisters/\registers_reg[3][28] } {/theRegisters/\registers_reg[3][29] } {/theRegisters/\registers_reg[3][2] } {/theRegisters/\registers_reg[3][30] } {/theRegisters/\registers_reg[3][31] } {/theRegisters/\registers_reg[3][3] } {/theRegisters/\registers_reg[3][4] } {/theRegisters/\registers_reg[3][5] } {/theRegisters/\registers_reg[3][6] } {/theRegisters/\registers_reg[3][7] } {/theRegisters/\registers_reg[3][8] } {/theRegisters/\registers_reg[3][9] } {/theRegisters/\registers_reg[4][0] } {/theRegisters/\registers_reg[4][10] } {/theRegisters/\registers_reg[4][11] } {/theRegisters/\registers_reg[4][12] } {/theRegisters/\registers_reg[4][13] } {/theRegisters/\registers_reg[4][14] } {/theRegisters/\registers_reg[4][15] } {/theRegisters/\registers_reg[4][16] } {/theRegisters/\registers_reg[4][17] } {/theRegisters/\registers_reg[4][18] } {/theRegisters/\registers_reg[4][19] } {/theRegisters/\registers_reg[4][1] } {/theRegisters/\registers_reg[4][20] } {/theRegisters/\registers_reg[4][21] } {/theRegisters/\registers_reg[4][22] } {/theRegisters/\registers_reg[4][23] } {/theRegisters/\registers_reg[4][24] } {/theRegisters/\registers_reg[4][25] } {/theRegisters/\registers_reg[4][26] } {/theRegisters/\registers_reg[4][27] } {/theRegisters/\registers_reg[4][28] } {/theRegisters/\registers_reg[4][29] } {/theRegisters/\registers_reg[4][2] } {/theRegisters/\registers_reg[4][30] } {/theRegisters/\registers_reg[4][31] } {/theRegisters/\registers_reg[4][3] } {/theRegisters/\registers_reg[4][4] } {/theRegisters/\registers_reg[4][5] } {/theRegisters/\registers_reg[4][6] } {/theRegisters/\registers_reg[4][7] } {/theRegisters/\registers_reg[4][8] } {/theRegisters/\registers_reg[4][9] } {/theRegisters/\registers_reg[5][0] } {/theRegisters/\registers_reg[5][10] } {/theRegisters/\registers_reg[5][11] } {/theRegisters/\registers_reg[5][12] } {/theRegisters/\registers_reg[5][13] } {/theRegisters/\registers_reg[5][14] } {/theRegisters/\registers_reg[5][15] } {/theRegisters/\registers_reg[5][16] } {/theRegisters/\registers_reg[5][17] } {/theRegisters/\registers_reg[5][18] } {/theRegisters/\registers_reg[5][19] } {/theRegisters/\registers_reg[5][1] } {/theRegisters/\registers_reg[5][20] } {/theRegisters/\registers_reg[5][21] } {/theRegisters/\registers_reg[5][22] } {/theRegisters/\registers_reg[5][23] } {/theRegisters/\registers_reg[5][24] } {/theRegisters/\registers_reg[5][25] } {/theRegisters/\registers_reg[5][26] } {/theRegisters/\registers_reg[5][27] } {/theRegisters/\registers_reg[5][28] } {/theRegisters/\registers_reg[5][29] } {/theRegisters/\registers_reg[5][2] } {/theRegisters/\registers_reg[5][30] } {/theRegisters/\registers_reg[5][31] } {/theRegisters/\registers_reg[5][3] } {/theRegisters/\registers_reg[5][4] } {/theRegisters/\registers_reg[5][5] } {/theRegisters/\registers_reg[5][6] } {/theRegisters/\registers_reg[5][7] } {/theRegisters/\registers_reg[5][8] } {/theRegisters/\registers_reg[5][9] } {/theRegisters/\registers_reg[6][0] } {/theRegisters/\registers_reg[6][10] } {/theRegisters/\registers_reg[6][11] } {/theRegisters/\registers_reg[6][12] } {/theRegisters/\registers_reg[6][13] } {/theRegisters/\registers_reg[6][14] } {/theRegisters/\registers_reg[6][15] } {/theRegisters/\registers_reg[6][16] } {/theRegisters/\registers_reg[6][17] } {/theRegisters/\registers_reg[6][18] } {/theRegisters/\registers_reg[6][19] } {/theRegisters/\registers_reg[6][1] } {/theRegisters/\registers_reg[6][20] } {/theRegisters/\registers_reg[6][21] } {/theRegisters/\registers_reg[6][22] } {/theRegisters/\registers_reg[6][23] } {/theRegisters/\registers_reg[6][24] } {/theRegisters/\registers_reg[6][25] } {/theRegisters/\registers_reg[6][26] } {/theRegisters/\registers_reg[6][27] } {/theRegisters/\registers_reg[6][28] } {/theRegisters/\registers_reg[6][29] } {/theRegisters/\registers_reg[6][2] } {/theRegisters/\registers_reg[6][30] } {/theRegisters/\registers_reg[6][31] } {/theRegisters/\registers_reg[6][3] } {/theRegisters/\registers_reg[6][4] } {/theRegisters/\registers_reg[6][5] } {/theRegisters/\registers_reg[6][6] } {/theRegisters/\registers_reg[6][7] } {/theRegisters/\registers_reg[6][8] } {/theRegisters/\registers_reg[6][9] } {/theRegisters/\registers_reg[7][0] } {/theRegisters/\registers_reg[7][10] } {/theRegisters/\registers_reg[7][11] } {/theRegisters/\registers_reg[7][12] } {/theRegisters/\registers_reg[7][13] } {/theRegisters/\registers_reg[7][14] } {/theRegisters/\registers_reg[7][15] } {/theRegisters/\registers_reg[7][16] } {/theRegisters/\registers_reg[7][17] } {/theRegisters/\registers_reg[7][18] } {/theRegisters/\registers_reg[7][19] } {/theRegisters/\registers_reg[7][1] } {/theRegisters/\registers_reg[7][20] } {/theRegisters/\registers_reg[7][21] } {/theRegisters/\registers_reg[7][22] } {/theRegisters/\registers_reg[7][23] } {/theRegisters/\registers_reg[7][24] } {/theRegisters/\registers_reg[7][25] } {/theRegisters/\registers_reg[7][26] } {/theRegisters/\registers_reg[7][27] } {/theRegisters/\registers_reg[7][28] } {/theRegisters/\registers_reg[7][29] } {/theRegisters/\registers_reg[7][2] } {/theRegisters/\registers_reg[7][30] } {/theRegisters/\registers_reg[7][31] } {/theRegisters/\registers_reg[7][3] } {/theRegisters/\registers_reg[7][4] } {/theRegisters/\registers_reg[7][5] } {/theRegisters/\registers_reg[7][6] } {/theRegisters/\registers_reg[7][7] } {/theRegisters/\registers_reg[7][8] } {/theRegisters/\registers_reg[7][9] } {/theRegisters/\registers_reg[8][0] } {/theRegisters/\registers_reg[8][10] } {/theRegisters/\registers_reg[8][11] } {/theRegisters/\registers_reg[8][12] } {/theRegisters/\registers_reg[8][13] } {/theRegisters/\registers_reg[8][14] } {/theRegisters/\registers_reg[8][15] } {/theRegisters/\registers_reg[8][16] } {/theRegisters/\registers_reg[8][17] } {/theRegisters/\registers_reg[8][18] } {/theRegisters/\registers_reg[8][19] } {/theRegisters/\registers_reg[8][1] } {/theRegisters/\registers_reg[8][20] } {/theRegisters/\registers_reg[8][21] } {/theRegisters/\registers_reg[8][22] } {/theRegisters/\registers_reg[8][23] } {/theRegisters/\registers_reg[8][24] } {/theRegisters/\registers_reg[8][25] } {/theRegisters/\registers_reg[8][26] } {/theRegisters/\registers_reg[8][27] } {/theRegisters/\registers_reg[8][28] } {/theRegisters/\registers_reg[8][29] } {/theRegisters/\registers_reg[8][2] } {/theRegisters/\registers_reg[8][30] } {/theRegisters/\registers_reg[8][31] } {/theRegisters/\registers_reg[8][3] } {/theRegisters/\registers_reg[8][4] } {/theRegisters/\registers_reg[8][5] } {/theRegisters/\registers_reg[8][6] } {/theRegisters/\registers_reg[8][7] } {/theRegisters/\registers_reg[8][8] } {/theRegisters/\registers_reg[8][9] } {/theRegisters/\registers_reg[9][0] } {/theRegisters/\registers_reg[9][10] } {/theRegisters/\registers_reg[9][11] } {/theRegisters/\registers_reg[9][12] } {/theRegisters/\registers_reg[9][13] } {/theRegisters/\registers_reg[9][14] } {/theRegisters/\registers_reg[9][15] } {/theRegisters/\registers_reg[9][16] } {/theRegisters/\registers_reg[9][17] } {/theRegisters/\registers_reg[9][18] } {/theRegisters/\registers_reg[9][19] } {/theRegisters/\registers_reg[9][1] } {/theRegisters/\registers_reg[9][20] } {/theRegisters/\registers_reg[9][21] } {/theRegisters/\registers_reg[9][22] } {/theRegisters/\registers_reg[9][23] } {/theRegisters/\registers_reg[9][24] } {/theRegisters/\registers_reg[9][25] } {/theRegisters/\registers_reg[9][26] } {/theRegisters/\registers_reg[9][27] } {/theRegisters/\registers_reg[9][28] } {/theRegisters/\registers_reg[9][29] } {/theRegisters/\registers_reg[9][2] } {/theRegisters/\registers_reg[9][30] } {/theRegisters/\registers_reg[9][31] } {/theRegisters/\registers_reg[9][3] } {/theRegisters/\registers_reg[9][4] } {/theRegisters/\registers_reg[9][5] } {/theRegisters/\registers_reg[9][6] } {/theRegisters/\registers_reg[9][7] } {/theRegisters/\registers_reg[9][8] } {/theRegisters/\registers_reg[9][9] } " -si_connections "SI_4 " -so_connections "SO_4 " -chain_count 1 +// sub-command: analyze_scan_chains +// Chain allocation of 'unwrapped' mode completed: +// 4 distributed chains of size 256 +// sub-command: insert_test_logic -write_in_tsdb on +============================= +Test Logic Insertion Summary: +============================= + + Structural Data: + ---------------- + Added top-level port count: 0 + Added instance count: 8 + + Logical Data: + ------------- + Added retiming logic count: 4 + Added scan chain count (unwrapped): 4 + +// Warning: Flattened model deleted. +// +// Writing out netlist and related files in /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.01/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design +// sub-command: report_scan_chains + +=============================== +Scan Chains Created by the Tool +=============================== + + Scan mode 'unwrapped' scan chains: + ---------------------------------- + + Cluster 'scanChain_1' chains: + ----------------------------- + chain = scanChain_1 group = dummy input = /SI_1 output = /SO_1 length = 256 + + Cluster 'scanChain_2' chains: + ----------------------------- + chain = scanChain_2 group = dummy input = /SI_2 output = /SO_2 length = 256 + + Cluster 'scanChain_3' chains: + ----------------------------- + chain = scanChain_3 group = dummy input = /SI_3 output = /SO_3 length = 256 + + Cluster 'scanChain_4' chains: + ----------------------------- + chain = scanChain_4 group = dummy input = /SI_4 output = /SO_4 length = 256 + + +// sub-command: write_scan_order /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.01/Scan_0/cpu.scandef -use_escaping_rule Lefdef -replace +// sub-command: write_design -output_file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.01/Scan_0/post_scan.v -replace +// command: exit + +************************************************************************************************************************************************************************************** + TESSENT EXECUTION ENDS HERE ! +************************************************************************************************************************************************************************************** + +Dumping current design to /tmp/oasys.2567124/dft_eco/cpu +> write_db /tmp/oasys.2567124/dft_eco/cpu +info: Target library/cell information has changed that further may change timing results. [TA-159] +info: Successfully traced scan chain (scan_in: 'SI_1', scan_out: 'SO_1' with 258 elements ) [DFT-354] +info: Successfully traced scan chain (scan_in: 'SI_2', scan_out: 'SO_2' with 258 elements ) [DFT-354] +info: Successfully traced scan chain (scan_in: 'SI_3', scan_out: 'SO_3' with 258 elements ) [DFT-354] +info: Successfully traced scan chain (scan_in: 'SI_4', scan_out: 'SO_4' with 258 elements ) [DFT-354] +> write_db ./output/odb/riscv.tessent_post_scan.odb +> write_verilog ./output/riscv.tessent_post_scan.v +info: writing Verilog file './output/riscv.tessent_post_scan.v' for module 'cpu' [WRITE-100] + +----------report_power---------------- +> report_power +Report Power (instances with prefix '*' are included in total) : +-----+----------------------------------------+--------------------+---------------------+-------------------+----------------- + | Instance | Internal Power (uW)| Switching Power (uW)| Leakage Power (uW)| Total Power (uW) +-----+----------------------------------------+--------------------+---------------------+-------------------+----------------- +1 |*theMem | 4965.347656| 97.271141| 528.368530| 5590.987793 +2 |*theRegisters | 2937.885254| 65.439415| 75.000534| 3078.325195 +3 |*theDecoder | 3306.815674| 29.696104| 69.466927| 3405.978516 +4 |*thePC_i_0 | 102.036263| 0.516853| 0.818020| 103.371140 +5 |*thePC_CurrentPC_reg[31] | 6.132826| 0.115208| 0.000019| 6.248054 +6 |*thePC_CurrentPC_reg[30] | 6.132829| 0.122289| 0.000019| 6.255136 +7 |*thePC_CurrentPC_reg[29] | 6.132829| 0.122289| 0.000019| 6.255136 +8 |*thePC_CurrentPC_reg[28] | 6.132829| 0.122289| 0.000019| 6.255136 +9 |*thePC_CurrentPC_reg[27] | 6.132829| 0.122289| 0.000019| 6.255136 +10 |*thePC_CurrentPC_reg[26] | 6.132829| 0.122289| 0.000019| 6.255136 +11 |*thePC_CurrentPC_reg[25] | 6.132829| 0.122289| 0.000019| 6.255136 +12 |*thePC_CurrentPC_reg[24] | 6.132829| 0.122289| 0.000019| 6.255136 +13 |*thePC_CurrentPC_reg[23] | 6.132829| 0.122289| 0.000019| 6.255136 +14 |*thePC_CurrentPC_reg[22] | 6.132829| 0.122289| 0.000019| 6.255136 +15 |*thePC_CurrentPC_reg[21] | 6.135628| 0.207666| 0.000019| 6.343312 +16 |*thePC_CurrentPC_reg[20] | 6.132829| 0.122289| 0.000019| 6.255136 +17 |*thePC_CurrentPC_reg[19] | 6.132828| 0.121340| 0.000019| 6.254188 +18 |*thePC_CurrentPC_reg[18] | 6.132828| 0.121340| 0.000019| 6.254188 +19 |*thePC_CurrentPC_reg[17] | 6.132828| 0.121340| 0.000019| 6.254188 +20 |*thePC_CurrentPC_reg[16] | 6.132828| 0.121340| 0.000019| 6.254188 +21 |*thePC_CurrentPC_reg[15] | 6.132826| 0.115029| 0.000019| 6.247873 +22 |*thePC_CurrentPC_reg[14] | 6.132828| 0.121340| 0.000019| 6.254188 +23 |*thePC_CurrentPC_reg[13] | 6.135591| 0.206718| 0.000019| 6.342327 +24 |*thePC_CurrentPC_reg[12] | 6.132828| 0.121340| 0.000019| 6.254188 +25 |*thePC_CurrentPC_reg[11] | 6.132828| 0.120392| 0.000019| 6.253239 +26 |*thePC_CurrentPC_reg[10] | 6.132827| 0.115675| 0.000019| 6.248520 +27 |*thePC_CurrentPC_reg[9] | 6.132827| 0.115675| 0.000019| 6.248520 +28 |*thePC_CurrentPC_reg[8] | 6.132827| 0.115675| 0.000019| 6.248520 +29 |*thePC_CurrentPC_reg[7] | 6.132825| 0.109358| 0.000019| 6.242202 +30 |*thePC_CurrentPC_reg[6] | 6.132825| 0.109358| 0.000019| 6.242202 +31 |*thePC_CurrentPC_reg[5] | 6.132825| 0.109358| 0.000019| 6.242202 +32 |*thePC_CurrentPC_reg[4] | 6.132825| 0.109358| 0.000019| 6.242202 +33 |*thePC_CurrentPC_reg[3] | 6.132825| 0.109358| 0.000019| 6.242202 +34 |*thePC_CurrentPC_reg[2] | 6.136212| 0.222482| 0.000019| 6.358713 +35 |*thePC_CurrentPC_reg[1] | 6.132825| 0.110713| 0.000019| 6.243557 +36 |*thePC_CurrentPC_reg[0] | 6.132828| 0.121456| 0.000019| 6.254303 +37 |*i_0_0_0 | 3.636180| 0.005795| 0.056141| 3.698117 +38 |*i_0_0_1 | 3.630034| 0.075574| 0.049831| 3.755438 +39 |*i_0_0_2 | 3.589001| 0.005720| 0.056141| 3.650862 +40 |*i_0_0_3 | 3.579433| 0.074593| 0.049831| 3.703857 +41 |*i_0_0_4 | 4.765921| 0.005811| 0.038697| 4.810430 +42 |*i_0_0_5 | 4.765921| 0.005811| 0.038697| 4.810430 +43 |*i_0_0_6 | 4.765921| 0.005811| 0.038697| 4.810430 +44 |*i_0_0_7 | 4.765921| 0.005811| 0.038697| 4.810430 +45 |*i_0_0_8 | 4.765921| 0.005811| 0.038697| 4.810430 +46 |*i_0_0_9 | 4.765921| 0.005811| 0.038697| 4.810430 +47 |*i_0_0_10 | 4.760734| 0.005811| 0.038697| 4.805242 +48 |*i_0_0_11 | 4.760734| 0.005811| 0.038697| 4.805242 +49 |*i_0_0_12 | 4.760734| 0.005811| 0.038697| 4.805242 +50 |*i_0_0_13 | 4.760734| 0.005811| 0.038697| 4.805242 +51 |*i_0_0_14 | 4.760734| 0.005811| 0.038697| 4.805242 +52 |*i_0_0_15 | 3.589408| 0.005721| 0.056141| 3.651270 +53 |*i_0_0_16 | 3.579309| 0.074602| 0.049831| 3.703742 +54 |*i_0_0_17 | 3.589739| 0.005721| 0.056141| 3.651601 +55 |*i_0_0_18 | 3.579648| 0.074608| 0.049831| 3.704087 +56 |*i_0_0_19 | 3.590052| 0.005722| 0.056141| 3.651915 +57 |*i_0_0_20 | 3.579969| 0.074615| 0.049831| 3.704415 +58 |*i_0_0_21 | 3.590306| 0.005722| 0.056141| 3.652169 +59 |*i_0_0_22 | 3.580231| 0.074620| 0.049831| 3.704682 +60 |*i_0_0_23 | 3.590506| 0.005722| 0.056141| 3.652370 +61 |*i_0_0_24 | 3.580436| 0.074625| 0.049831| 3.704891 +62 |*i_0_0_25 | 3.590656| 0.005723| 0.056141| 3.652520 +63 |*i_0_0_26 | 3.580589| 0.074627| 0.049831| 3.705047 +64 |*i_0_0_27 | 3.590823| 0.005723| 0.056141| 3.652687 +65 |*i_0_0_28 | 3.580760| 0.074631| 0.049831| 3.705222 +66 |*i_0_0_29 | 3.590933| 0.005723| 0.056141| 3.652797 +67 |*i_0_0_30 | 3.580874| 0.074633| 0.049831| 3.705338 +68 |*i_0_0_31 | 3.590987| 0.005723| 0.056141| 3.652852 +69 |*i_0_0_32 | 3.580929| 0.074634| 0.049831| 3.705395 +70 |*i_0_0_33 | 3.591065| 0.005723| 0.056141| 3.652930 +71 |*i_0_0_34 | 3.581009| 0.074636| 0.049831| 3.705476 +72 |*i_0_0_35 | 3.591195| 0.005724| 0.056141| 3.653060 +73 |*i_0_0_36 | 3.581142| 0.074639| 0.049831| 3.705612 +74 |*i_0_0_37 | 3.591303| 0.005724| 0.056141| 3.653168 +75 |*i_0_0_38 | 3.581253| 0.074641| 0.049831| 3.705725 +76 |*i_0_0_39 | 3.591386| 0.005724| 0.056141| 3.653251 +77 |*i_0_0_40 | 3.581338| 0.074643| 0.049831| 3.705812 +78 |*i_0_0_41 | 3.591435| 0.005724| 0.056141| 3.653301 +79 |*i_0_0_42 | 3.581389| 0.074644| 0.049831| 3.705863 +80 |*i_0_0_43 | 3.591419| 0.005724| 0.056141| 3.653284 +81 |*i_0_0_44 | 3.581372| 0.074644| 0.049831| 3.705847 +82 |*i_0_0_45 | 3.591433| 0.005724| 0.056141| 3.653298 +83 |*i_0_0_46 | 3.581386| 0.074644| 0.049831| 3.705861 +84 |*i_0_0_47 | 3.591558| 0.005724| 0.056141| 3.653424 +85 |*i_0_0_48 | 3.581515| 0.074646| 0.049831| 3.705992 +86 |*i_0_0_49 | 3.591676| 0.005724| 0.056141| 3.653541 +87 |*i_0_0_50 | 3.581635| 0.074649| 0.049831| 3.706115 +88 |*i_0_0_51 | 3.591723| 0.005724| 0.056141| 3.653588 +89 |*i_0_0_52 | 3.581872| 0.074650| 0.049831| 3.706352 +90 |*i_0_0_53 | 0.270481| 0.031764| 0.181711| 0.483956 +91 |*i_0_0_54 | 8.109213| 0.417922| 0.187759| 8.714894 +92 |*i_0_0_55 | 4.662969| 0.392350| 0.167543| 5.222862 +93 |*i_0_0_56 | 4.661758| 0.392909| 0.167809| 5.222477 +94 |*i_0_0_57 | 4.661533| 0.392163| 0.167455| 5.221151 +95 |*i_0_0_58 | 4.661815| 0.393097| 0.167897| 5.222809 +96 |*i_0_0_59 | 4.661477| 0.391976| 0.167366| 5.220819 +97 |*i_0_0_60 | 4.661870| 0.393283| 0.167986| 5.223139 +98 |*i_0_0_61 | 4.263187| 0.064498| 0.029698| 4.357384 +99 |*i_0_0_62 | 4.263187| 0.064498| 0.029698| 4.357384 +100 |*i_0_0_63 | 4.263187| 0.064498| 0.029698| 4.357384 +101 |*i_0_0_64 | 4.263187| 0.064498| 0.029698| 4.357384 +102 |*i_0_0_65 | 4.263187| 0.064498| 0.029698| 4.357384 +103 |*i_0_0_66 | 892.076904| 9.773184| 0.224563| 902.074707 +104 |*tessent_persistent_cell_buf_extsi1225_i| 12.245425| 0.023904| 0.084228| 12.353557 +105 | | | | | +106 |*TOTAL | 12673.423828| 211.665421| 678.138367| 13563.228516 +-----+----------------------------------------+--------------------+---------------------+-------------------+----------------- + +----------report_path_groups---------------- +> report_path_groups +Report Path Groups: +-----+-------+------+---------+--------- + | Path |Weight|Critical |Worst + | Group | |Range(ps)|Slack(ps) +-----+-------+------+---------+--------- +1 |default| 1.000| 0.0| 18131.2 +2 |I2R | 1.000| 0.0| +3 |I2O | 1.000| 0.0| +4 |R2O | 1.000| 0.0| 36309.8 +-----+-------+------+---------+--------- + +----------report_scan_chains---------------- +> report_scan_chains +Report ScanChains: +--------+-----------+--------------+--------+-----------+-----------+--------------+------------------+--------+--------+---------+-----------+---------- + Index | Chain | ScanInstance | Length | TestClock | ClockEdge | Comp. Chains | Max Comp. Length | Lockup | ScanIn | ScanOut | Partition | ScanMode +--------+-----------+--------------+--------+-----------+-----------+--------------+------------------+--------+--------+---------+-----------+---------- + 1|scanChain_1| 258 | 256|clk_25mhz |rise | - | - | 1|SI_1 |SO_1 | - | + 2|scanChain_2| 258 | 256|clk_25mhz |rise | - | - | 1|SI_2 |SO_2 | - | + 3|scanChain_3| 258 | 256|clk_25mhz |rise | - | - | 1|SI_3 |SO_3 | - | + 4|scanChain_4| 258 | 256|clk_25mhz |rise | - | - | 1|SI_4 |SO_4 | - | +--------+-----------+--------------+--------+-----------+-----------+--------------+------------------+--------+--------+---------+-----------+---------- + +----------report_timing---------------- +> report_timing +Report for group default +-------------------------------------------------------------------------------------------------------------------------------------- +Startpoint: theMem/IRData_reg[18]/Q + (Clocked by clk_25mhz R) +Endpoint: theMem/mem_addr_reg[5]/D + (Clocked by clk_25mhz F) +Path Group: default +Data required time: 19371.2 + (Clock shift: 20000.0, minus Uncertainty: 500.0, plus Latency 0.0, minus Setup time: 128.8) +Data arrival time: 1240.0 +Slack: 18131.2 +Logic depth: 46 +-------------------------------------------------------------------------------------------------------------------------------------- + Arrival Arc Net Net Total fan- +Path Module/Cell Edge Time Delay Delay Delay Slew Load Load out Location + (ps) (ps) (ps) (ps) (ps) (ff) (ff) (#) (um,um) +-------------------------------------------------------------------------------------------------------------------------------------- +clk_25mhz {create_clock} r 0.0 0.0 0.0 0.0 0.0 100 101, 0 +theMem/IRData_reg[18]/CK->Q + DFF_X1_LVT* rr 106.0 106.0 106.0 0.0 100.0 15.2 77.1 10 175, 106 +theRegisters/i_1_0_1371/A->ZN + INV_X8_LVT rf 108.7 2.7 2.7 0.0 10.2 2.1 13.2 3 168, 158 +theRegisters/i_1_0_1339/A2->ZN + NAND3_X4_LVT fr 122.7 14.0 14.0 0.0 1.0 2.5 17.5 4 168, 158 +theRegisters/i_1_0_1321/A2->ZN + NOR2_X4_LVT* rf 141.6 19.0 19.0 0.0 12.1 29.7 130.1 32 168, 158 +theRegisters/i_1_0_722/B1->ZN + AOI22_X4_LVT* fr 186.0 44.3 44.3 0.0 10.2 0.7 23.4 1 168, 158 +theRegisters/i_1_0_721/A->ZN + INV_X8_LVT rf 188.1 2.1 2.1 0.0 10.2 0.8 3.0 1 168, 158 +theRegisters/i_1_0_718/A->ZN + AOI221_X2_LVT fr 245.4 57.3 57.3 0.0 0.6 0.9 4.4 1 168, 158 +theRegisters/i_1_0_716/A3->ZN + NAND4_X4_LVT rf 260.8 15.4 15.4 0.0 34.6 0.9 3.1 1 168, 158 +theRegisters/i_1_0_715/A->ZN + AOI221_X2_LVT fr 318.1 57.4 57.4 0.0 6.8 0.9 4.3 1 168, 158 +theRegisters/i_1_0_704/A2->ZN + NAND4_X4_LVT* rf 342.3 24.2 24.2 0.0 34.4 14.1 24.9 3 168, 158 +theDecoder/i_0_133/C2->ZN + AOI222_X4_LVT fr 452.6 110.3 110.3 0.0 10.2 0.8 23.5 1 129, 89 +theDecoder/i_0_132/A->ZN INV_X32_LVT rf 455.7 3.1 3.1 0.0 10.9 5.4 65.3 7 129, 89 +theDecoder/theALU/i_0_706/B1->ZN + OAI22_X4_LVT* fr 498.9 43.2 43.2 0.0 1.4 1.5 25.9 2 129, 89 +theDecoder/theALU/i_0_705/A->ZN + INV_X8_LVT rf 501.1 2.2 2.2 0.0 10.2 0.6 4.2 1 129, 89 +theDecoder/theALU/i_0_42/A->ZN + OAI21_X2_LVT fr 510.2 9.1 9.1 0.0 0.6 0.8 2.5 1 129, 89 +theDecoder/theALU/i_0_40/C1->ZN + AOI211_X2_LVT rf 515.8 5.6 5.6 0.0 11.6 0.8 2.9 1 129, 89 +theDecoder/theALU/i_0_39/B->ZN + AOI211_X2_LVT fr 563.3 47.4 47.4 0.0 3.3 0.9 3.0 1 129, 89 +theDecoder/theALU/i_0_38/B2->ZN + OAI222_X2_LVT rf 580.2 16.9 16.9 0.0 27.7 0.9 2.9 1 129, 89 +theDecoder/theALU/i_0_37/C2->ZN + AOI221_X2_LVT fr 624.0 43.8 43.8 0.0 8.4 0.9 4.2 1 129, 89 +theDecoder/theALU/i_0_35/B1->ZN + OAI22_X4_LVT* rf 637.9 13.9 13.9 0.0 34.0 0.7 23.4 1 129, 89 +theDecoder/theALU/i_0_34/A->ZN + INV_X8_LVT fr 642.4 4.5 4.5 0.0 10.2 0.6 4.1 1 129, 89 +theDecoder/theALU/i_0_33/A->ZN + AOI21_X4_LVT rf 645.0 2.6 2.6 0.0 2.4 0.8 3.0 1 129, 89 +theDecoder/theALU/i_0_32/C2->ZN + OAI222_X2_LVT fr 683.5 38.5 38.5 0.0 2.6 0.9 3.3 1 129, 89 +theDecoder/theALU/i_0_31/A->ZN + OAI221_X2_LVT rf 699.6 16.0 16.0 0.0 29.2 0.8 4.0 1 129, 89 +theDecoder/theALU/i_0_28/B1->ZN + AOI21_X4_LVT fr 715.0 15.5 15.5 0.0 8.2 0.8 3.0 1 129, 89 +theDecoder/theALU/i_0_27/A->ZN + AOI221_X2_LVT rf 719.3 4.2 4.2 0.0 13.5 0.9 2.9 1 129, 89 +theDecoder/theALU/i_0_26/B->ZN + AOI211_X2_LVT fr 771.5 52.2 52.2 0.0 5.3 0.8 4.6 1 129, 89 +theDecoder/theALU/i_0_25/B2->ZN + OAI22_X2_LVT rf 781.1 9.7 9.7 0.0 31.8 0.8 2.7 1 129, 89 +theDecoder/theALU/i_0_24/C2->ZN + AOI211_X2_LVT fr 815.5 34.4 34.4 0.0 4.0 0.9 3.1 1 129, 89 +theDecoder/theALU/i_0_23/A->ZN + AOI221_X2_LVT rf 821.3 5.8 5.8 0.0 27.8 0.9 3.1 1 129, 89 +theDecoder/theALU/i_0_22/A->ZN + AOI221_X2_LVT fr 874.9 53.7 53.7 0.0 5.4 0.9 3.1 1 129, 89 +theDecoder/theALU/i_0_21/A->ZN + AOI221_X2_LVT rf 881.0 6.1 6.1 0.0 31.2 0.9 3.1 1 129, 89 +theDecoder/theALU/i_0_20/C2->ZN + OAI222_X2_LVT fr 919.8 38.8 38.8 0.0 5.4 0.9 3.3 1 129, 89 +theDecoder/theALU/i_0_19/A->ZN + OAI221_X2_LVT rf 936.3 16.6 16.6 0.0 29.2 0.9 4.7 1 129, 89 +theDecoder/theALU/i_0_18/B2->ZN + AOI22_X4_LVT fr 966.6 30.3 30.3 0.0 8.6 0.8 4.4 1 129, 89 +theDecoder/theALU/i_0_17/B2->ZN + OAI21_X4_LVT rf 973.1 6.4 6.4 0.0 16.9 0.7 4.3 1 129, 89 +theDecoder/theALU/i_0_16/A->ZN + OAI21_X4_LVT fr 982.8 9.8 9.8 0.0 3.6 0.7 3.9 1 129, 89 +theDecoder/theALU/i_0_13/B1->ZN + AOI21_X4_LVT rf 988.1 5.3 5.3 0.0 12.5 0.8 4.4 1 129, 89 +theDecoder/theALU/i_0_12/A4->ZN + NOR4_X2_LVT fr 1044.5 56.5 56.5 0.0 2.9 0.8 2.8 1 129, 89 +theDecoder/theALU/i_0_0/A3->ZN + OR3_X4_LVT rr 1062.9 18.3 18.3 0.0 29.1 0.7 18.9 2 129, 89 +theDecoder/i_0_114/B->ZN XNOR2_X2_LVT rf 1069.5 6.7 6.7 0.0 9.3 0.7 4.3 1 129, 89 +theDecoder/i_0_113/B1->ZN + AOI22_X4_LVT fr 1096.0 26.5 26.5 0.0 5.1 0.8 4.4 1 129, 89 +theDecoder/i_0_111/A2->ZN + AOI22_X4_LVT rf 1102.4 6.4 6.4 0.0 16.9 0.7 4.3 1 129, 89 +theDecoder/i_0_110/A2->ZN + NAND2_X4_LVT* fr 1121.6 19.2 19.2 0.0 4.4 9.0 37.6 13 129, 89 +i_0_0_60/S->Z MUX2_X2_LVT* rf 1190.2 68.6 68.6 0.0 10.2 32.0 87.6 3 129, 89 +theMem/i_0_0_11/B2->ZN AOI22_X4_LVT* fr 1238.0 47.8 47.8 0.0 10.2 0.7 23.4 1 175, 106 +theMem/i_0_0_10/A->ZN INV_X8_LVT rf 1240.0 2.0 2.0 0.0 10.2 0.7 1.7 1 175, 106 +theMem/mem_addr_reg[5]/D DFF_X1_LVT f 1240.0 0.0 0.0 0.5 175, 106 +-------------------------------------------------------------------------------------------------------------------------------------- +Report for group I2R +Report for group I2O +Report for group R2O +-------------------------------------------------------------------------------------------------------------------------------------- +Startpoint: theMem/IRData_reg[18]/Q + (Clocked by clk_25mhz R) +Endpoint: led[7] + (Clocked by clk_25mhz R) +Path Group: R2O +Data required time: 37500.0 + (Clock shift: 40000.0, minus Uncertainty: 500.0, plus Latency 0.0, minus Out delay: 2000.0) +Data arrival time: 1190.2 +Slack: 36309.8 +Logic depth: 44 +-------------------------------------------------------------------------------------------------------------------------------------- + Arrival Arc Net Net Total fan- +Path Module/Cell Edge Time Delay Delay Delay Slew Load Load out Location + (ps) (ps) (ps) (ps) (ps) (ff) (ff) (#) (um,um) +-------------------------------------------------------------------------------------------------------------------------------------- +clk_25mhz {create_clock} r 0.0 0.0 0.0 0.0 0.0 100 101, 0 +theMem/IRData_reg[18]/CK->Q + DFF_X1_LVT* rr 106.0 106.0 106.0 0.0 100.0 15.2 77.1 10 175, 106 +theRegisters/i_1_0_1371/A->ZN + INV_X8_LVT rf 108.7 2.7 2.7 0.0 10.2 2.1 13.2 3 168, 158 +theRegisters/i_1_0_1339/A2->ZN + NAND3_X4_LVT fr 122.7 14.0 14.0 0.0 1.0 2.5 17.5 4 168, 158 +theRegisters/i_1_0_1321/A2->ZN + NOR2_X4_LVT* rf 141.6 19.0 19.0 0.0 12.1 29.7 130.1 32 168, 158 +theRegisters/i_1_0_722/B1->ZN + AOI22_X4_LVT* fr 186.0 44.3 44.3 0.0 10.2 0.7 23.4 1 168, 158 +theRegisters/i_1_0_721/A->ZN + INV_X8_LVT rf 188.1 2.1 2.1 0.0 10.2 0.8 3.0 1 168, 158 +theRegisters/i_1_0_718/A->ZN + AOI221_X2_LVT fr 245.4 57.3 57.3 0.0 0.6 0.9 4.4 1 168, 158 +theRegisters/i_1_0_716/A3->ZN + NAND4_X4_LVT rf 260.8 15.4 15.4 0.0 34.6 0.9 3.1 1 168, 158 +theRegisters/i_1_0_715/A->ZN + AOI221_X2_LVT fr 318.1 57.4 57.4 0.0 6.8 0.9 4.3 1 168, 158 +theRegisters/i_1_0_704/A2->ZN + NAND4_X4_LVT* rf 342.3 24.2 24.2 0.0 34.4 14.1 24.9 3 168, 158 +theDecoder/i_0_133/C2->ZN + AOI222_X4_LVT fr 452.6 110.3 110.3 0.0 10.2 0.8 23.5 1 129, 89 +theDecoder/i_0_132/A->ZN INV_X32_LVT rf 455.7 3.1 3.1 0.0 10.9 5.4 65.3 7 129, 89 +theDecoder/theALU/i_0_706/B1->ZN + OAI22_X4_LVT* fr 498.9 43.2 43.2 0.0 1.4 1.5 25.9 2 129, 89 +theDecoder/theALU/i_0_705/A->ZN + INV_X8_LVT rf 501.1 2.2 2.2 0.0 10.2 0.6 4.2 1 129, 89 +theDecoder/theALU/i_0_42/A->ZN + OAI21_X2_LVT fr 510.2 9.1 9.1 0.0 0.6 0.8 2.5 1 129, 89 +theDecoder/theALU/i_0_40/C1->ZN + AOI211_X2_LVT rf 515.8 5.6 5.6 0.0 11.6 0.8 2.9 1 129, 89 +theDecoder/theALU/i_0_39/B->ZN + AOI211_X2_LVT fr 563.3 47.4 47.4 0.0 3.3 0.9 3.0 1 129, 89 +theDecoder/theALU/i_0_38/B2->ZN + OAI222_X2_LVT rf 580.2 16.9 16.9 0.0 27.7 0.9 2.9 1 129, 89 +theDecoder/theALU/i_0_37/C2->ZN + AOI221_X2_LVT fr 624.0 43.8 43.8 0.0 8.4 0.9 4.2 1 129, 89 +theDecoder/theALU/i_0_35/B1->ZN + OAI22_X4_LVT* rf 637.9 13.9 13.9 0.0 34.0 0.7 23.4 1 129, 89 +theDecoder/theALU/i_0_34/A->ZN + INV_X8_LVT fr 642.4 4.5 4.5 0.0 10.2 0.6 4.1 1 129, 89 +theDecoder/theALU/i_0_33/A->ZN + AOI21_X4_LVT rf 645.0 2.6 2.6 0.0 2.4 0.8 3.0 1 129, 89 +theDecoder/theALU/i_0_32/C2->ZN + OAI222_X2_LVT fr 683.5 38.5 38.5 0.0 2.6 0.9 3.3 1 129, 89 +theDecoder/theALU/i_0_31/A->ZN + OAI221_X2_LVT rf 699.6 16.0 16.0 0.0 29.2 0.8 4.0 1 129, 89 +theDecoder/theALU/i_0_28/B1->ZN + AOI21_X4_LVT fr 715.0 15.5 15.5 0.0 8.2 0.8 3.0 1 129, 89 +theDecoder/theALU/i_0_27/A->ZN + AOI221_X2_LVT rf 719.3 4.2 4.2 0.0 13.5 0.9 2.9 1 129, 89 +theDecoder/theALU/i_0_26/B->ZN + AOI211_X2_LVT fr 771.5 52.2 52.2 0.0 5.3 0.8 4.6 1 129, 89 +theDecoder/theALU/i_0_25/B2->ZN + OAI22_X2_LVT rf 781.1 9.7 9.7 0.0 31.8 0.8 2.7 1 129, 89 +theDecoder/theALU/i_0_24/C2->ZN + AOI211_X2_LVT fr 815.5 34.4 34.4 0.0 4.0 0.9 3.1 1 129, 89 +theDecoder/theALU/i_0_23/A->ZN + AOI221_X2_LVT rf 821.3 5.8 5.8 0.0 27.8 0.9 3.1 1 129, 89 +theDecoder/theALU/i_0_22/A->ZN + AOI221_X2_LVT fr 874.9 53.7 53.7 0.0 5.4 0.9 3.1 1 129, 89 +theDecoder/theALU/i_0_21/A->ZN + AOI221_X2_LVT rf 881.0 6.1 6.1 0.0 31.2 0.9 3.1 1 129, 89 +theDecoder/theALU/i_0_20/C2->ZN + OAI222_X2_LVT fr 919.8 38.8 38.8 0.0 5.4 0.9 3.3 1 129, 89 +theDecoder/theALU/i_0_19/A->ZN + OAI221_X2_LVT rf 936.3 16.6 16.6 0.0 29.2 0.9 4.7 1 129, 89 +theDecoder/theALU/i_0_18/B2->ZN + AOI22_X4_LVT fr 966.6 30.3 30.3 0.0 8.6 0.8 4.4 1 129, 89 +theDecoder/theALU/i_0_17/B2->ZN + OAI21_X4_LVT rf 973.1 6.4 6.4 0.0 16.9 0.7 4.3 1 129, 89 +theDecoder/theALU/i_0_16/A->ZN + OAI21_X4_LVT fr 982.8 9.8 9.8 0.0 3.6 0.7 3.9 1 129, 89 +theDecoder/theALU/i_0_13/B1->ZN + AOI21_X4_LVT rf 988.1 5.3 5.3 0.0 12.5 0.8 4.4 1 129, 89 +theDecoder/theALU/i_0_12/A4->ZN + NOR4_X2_LVT fr 1044.5 56.5 56.5 0.0 2.9 0.8 2.8 1 129, 89 +theDecoder/theALU/i_0_0/A3->ZN + OR3_X4_LVT rr 1062.9 18.3 18.3 0.0 29.1 0.7 18.9 2 129, 89 +theDecoder/i_0_114/B->ZN XNOR2_X2_LVT rf 1069.5 6.7 6.7 0.0 9.3 0.7 4.3 1 129, 89 +theDecoder/i_0_113/B1->ZN + AOI22_X4_LVT fr 1096.0 26.5 26.5 0.0 5.1 0.8 4.4 1 129, 89 +theDecoder/i_0_111/A2->ZN + AOI22_X4_LVT rf 1102.4 6.4 6.4 0.0 16.9 0.7 4.3 1 129, 89 +theDecoder/i_0_110/A2->ZN + NAND2_X4_LVT* fr 1121.6 19.2 19.2 0.0 4.4 9.0 37.6 13 129, 89 +i_0_0_60/S->Z MUX2_X2_LVT* rf 1190.2 68.6 68.6 0.0 10.2 32.0 87.6 3 129, 89 +led[7] f 1190.2 0.0 0.0 10.2 119, 257 +-------------------------------------------------------------------------------------------------------------------------------------- + +------------------------------------- + + Tessent DFT complete + +------------------------------------- + diff --git a/oasys.log.02 b/oasys.log.02 new file mode 100644 index 0000000..6a58ed6 --- /dev/null +++ b/oasys.log.02 @@ -0,0 +1,1570 @@ +******************************************************************* +* Oasys-RTL™ - release 2022.2.R1 * +* * +* This material contains trade secrets or otherwise confidential * +* information owned by Siemens Industry Software Inc. or its * +* affiliates (collectively, "SISW"), or its licensors. Access to * +* and use of this information is strictly limited as set forth * +* in the Customer’s applicable agreements with SISW. * +* * +* Unpublished work. © 2023 Siemens * +* * +* Program : ../bin/Linux-x86_64-O/oasysGui * +* Version : 22.2-p002 * +* Date : Mon Jan 16 21:36:23 PST 2023 * +* Build : releases/22.2-54756.0-CentOS_6.5-O * +******************************************************************* + config sdc-v1.7-cpd cli cmd explore mxdb o2n fp rta mpg-m-w dft +loading: oa2tessent-d ctl verify edit bt upf-c aos conc ipc-l vcd o2pp prot int oa2ap +checked out license: psyncore + + date : Fri May 29 09:12:11 CEST 2026 + ppid/pid : 2567737/2567747 + hostname : efiapps0.ads1.fh-nuernberg.de + arch/os : x86_64/Linux-4.18.0-553.123.1.el8_10.x86_64 + install : /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1 + currdir : /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock + logfile : /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.log.02 + tmpdir : /tmp/oasys.2567737/ +> source /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/tcl/library/history.tcl +> source scripts_risc_v/1_read_design.tcl +> source scripts_risc_v/init_design.tcl +> config_shell -echo true +> config_report timing -format {cell edge arrival delay arc_delay net_delay slew net_load load fanout location power_domain} +> source scripts_risc_v/demo_chip_design_files.tcl + +----------------------------- + +Done setting design variables + +----------------------------- + +> read_db ./libs/nangate_mvt.odb +info: Reading '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/nangate_mvt.odb' [UFILE-107] + starting at 00:00:00(cpu)/0:00:03(wall) 94MB(vsz)/470MB(peak) +extracting odb ... finished at 00:00:00(cpu)/0:00:03(wall) 94MB(vsz)/470MB(peak) + Write Date : Mon, 21 Jun 2021 13:47:25 -0700 + Host : orw-ericc-r78 (64bit) + Tool Version : 21.1-p004 (60,9-71,11) + Tool Date : Fri Jun 11 12:44:10 PDT 2021 + Tool Build : 52545.0-O + Design Name : + Comment : +loading environment ... finished at 00:00:00(cpu)/0:00:03(wall) 94MB(vsz)/470MB(peak) +loading libraries ... finished at 00:00:01(cpu)/0:00:03(wall) 107MB(vsz)/476MB(peak) +all done +> create_threshold_voltage_group SVT -lib_cells {NangateOpenCellLibrary_45nm_SVT_0p85/AND2_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND2_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND2_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND3_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND3_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND3_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND4_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND4_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND4_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/ANTENNA_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI21_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI21_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI21_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI22_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI22_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI22_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI211_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI211_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI211_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI221_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI221_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI221_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI222_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI222_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI222_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X8_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X16_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X32_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKBUF_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKBUF_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKBUF_X3_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATETST_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATETST_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATETST_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATETST_X8_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATE_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATE_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATE_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATE_X8_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFFRS_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFFRS_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFFR_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFFR_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFFS_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFF_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFF_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DLH_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DLH_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DLL_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DLL_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FA_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X8_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X16_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X32_SVT NangateOpenCellLibrary_45nm_SVT_0p85/HA_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X8_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X16_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X32_SVT NangateOpenCellLibrary_45nm_SVT_0p85/LOGIC0_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/LOGIC1_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/MUX2_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/MUX2_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND2_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND2_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND2_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND3_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND3_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND3_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND4_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND4_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND4_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR2_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR2_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR2_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR3_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR3_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR3_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR4_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR4_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR4_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI21_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI21_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI21_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI22_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI22_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI22_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI33_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI211_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI211_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI211_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI221_X1_SVT ...(34 more)} +> report_operating_conditions +Report Operating conditions: +-----+---------------+--------+-------------+------------------------------------+--------+--------+----------- + |Name |Default?|Type |Library |Process |Voltage |Temperature +-----+---------------+--------+-------------+------------------------------------+--------+--------+----------- +1 |typical | |standard cell|IO |1.000000|1.100000| 27.000000 +2 |TYP | |standard cell|PLL_TYP |1.000000|0.900000| 25.000000 +3 |typical | |standard cell|MemGen_16_10 |1.000000|1.800000| 25.000000 +4 |worst_low_0p85V| |standard cell|NangateOpenCellLibrary_45nm_HVT_0p85|1.000000|0.850000| -40.000000 +5 |worst_low | |standard cell|NangateOpenCellLibrary_45nm_HVT |1.000000|0.950000| -40.000000 +-----+---------------+--------+-------------+------------------------------------+--------+--------+----------- +> config_tolerance -blackbox true -connection_mismatch true -missing_physical_library true -continue_on_error false +> read_verilog -sv {alu.sv cpu.sv decoder.sv MemGen_32_11.sv main_mem.sv pc.sv reg_file.sv} -include ./riscv_rtl/hw/rtl +info: File 'alu.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/./riscv_rtl/hw/rtl/alu.sv' using search_path variable. [CMD-126] +info: File 'cpu.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/./riscv_rtl/hw/rtl/cpu.sv' using search_path variable. [CMD-126] +info: File 'decoder.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/./riscv_rtl/hw/rtl/decoder.sv' using search_path variable. [CMD-126] +info: File 'MemGen_32_11.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/./riscv_rtl/hw/rtl/MemGen_32_11.sv' using search_path variable. [CMD-126] +info: File 'main_mem.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/./riscv_rtl/hw/rtl/main_mem.sv' using search_path variable. [CMD-126] +info: File 'pc.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/./riscv_rtl/hw/rtl/pc.sv' using search_path variable. [CMD-126] +info: File 'reg_file.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/./riscv_rtl/hw/rtl/reg_file.sv' using search_path variable. [CMD-126] +> set_max_route_layer 10 +Top-most available layer for routing set to metal10 +> set_dont_use {IO/PADBID IO/PADCLK PLL_TYP/PLL MemGen_16_10/MemGen_16_10 NangateOpenCellLibrary_45nm_HVT_0p85/AND2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND2_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND3_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND3_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND3_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND4_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND4_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND4_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/ANTENNA_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI21_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI21_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI21_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI22_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI22_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI22_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI211_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI211_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI211_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI221_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI221_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI221_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI222_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI222_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI222_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X16_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X32_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKBUF_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKBUF_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKBUF_X3_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFRS_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFRS_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFR_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFR_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFS_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFS_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFF_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFF_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLH_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLH_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLL_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLL_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FA_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X16_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X32_HVT NangateOpenCellLibrary_45nm_HVT_0p85/HA_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X16_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X32_HVT NangateOpenCellLibrary_45nm_HVT_0p85/LOGIC0_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/LOGIC1_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/MUX2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/MUX2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND2_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND3_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND3_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND3_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND4_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND4_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND4_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR2_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR3_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR3_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR3_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR4_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR4_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR4_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI21_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI21_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI21_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI22_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI22_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI22_X4_HVT ...(306 more)} false + +----------------------------- + +Done preparing design for synthesis + +----------------------------- + +> source scripts_risc_v/2_synthesize_optimize.tcl +> synthesize -module cpu -map_to_scan +starting synthesize at 00:00:01(cpu)/0:00:06(wall) 113MB(vsz)/480MB(peak) +warning: skipping cell ANTENNA_X1_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell FILLCELL_X1_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell FILLCELL_X2_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell FILLCELL_X4_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell FILLCELL_X8_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell FILLCELL_X16_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell FILLCELL_X32_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell LOGIC0_X1_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell LOGIC1_X1_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell ANTENNA_X1_HVT in the library since it does not have delay arcs [NL-215] +-------> Message [NL-215] suppressed 44 times +info: clock-gating cell for posedge FFs = CLKGATE_X1_LVT in target library 'default' [POWER-112] +info: no clock-gating cell found in target library 'default' for negedge FFs for the given specification [POWER-113] +info: clock_gating minimum_width = 4, maximum_fanout = 2147483647, num_stages = 2147483647, sequential_cell = (null), control_port = (null), control_point = none, observability = no, use_discrete_cells = no, create_multi_stage = no, merge_multi_stage = no, exclude_instantiated_clock_gates = no, log = (null), allow_clock_inversion = no [POWER-111] +info: synthesizing module 'cpu' (depth 1) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/cpu.sv:17)[7]) [VLOG-400] +info: synthesizing module 'decoder' (depth 2) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/decoder.sv:17)[7]) [VLOG-400] +info: synthesizing module 'alu' (depth 3) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/alu.sv:16)[7]) [VLOG-400] +info: done synthesizing module 'alu' (depth 3) (1#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/alu.sv:16)[7]) [VLOG-401] +info: done synthesizing module 'decoder' (depth 2) (2#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/decoder.sv:17)[7]) [VLOG-401] +info: synthesizing module 'reg_file' (depth 2) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/reg_file.sv:15)[7]) [VLOG-400] +warning: target library has multiple operating conditions defined, but no default has been set. Assuming default voltage 0.85V, temperature -40.00 and process 1.00 [LIB-218] +info: done synthesizing module 'reg_file' (depth 2) (3#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/reg_file.sv:15)[7]) [VLOG-401] +info: synthesizing module 'pc' (depth 2) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/pc.sv:16)[7]) [VLOG-400] +info: done synthesizing module 'pc' (depth 2) (4#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/pc.sv:16)[7]) [VLOG-401] +info: synthesizing module 'main_mem' (depth 2) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:18)[7]) [VLOG-400] +info: synthesizing module 'MemGen_32_11' (depth 3) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/MemGen_32_11.sv:1)[7]) [VLOG-400] +info: done synthesizing module 'MemGen_32_11' (depth 3) (5#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/MemGen_32_11.sv:1)[7]) [VLOG-401] +warning: always_comb on 'DRData' did not result in combinational logic ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:110)[8], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:113)[16], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:114)[16], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:118)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:119)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:120)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:121)[17]) [SYN-112] +warning: inferring latch for variable 'DRData' ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:110)[8], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:113)[16], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:114)[16], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:118)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:119)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:120)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:121)[17]) [VLOG-566] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +-------> Message [POWER-102] suppressed 22 times +info: done synthesizing module 'main_mem' (depth 2) (6#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:18)[7]) [VLOG-401] +info: done synthesizing module 'cpu' (depth 1) (7#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/cpu.sv:17)[7]) [VLOG-401] +finished synthesize at 00:00:02(cpu)/0:00:07(wall) 162MB(vsz)/530MB(peak) +> set_route_layer_max_usage metal2 0.5 +> set_route_layer_max_usage metal3 0.8 +> set_route_layer_max_usage metal6 0.8 +> write_db ./output/odb/riscv_chip.syn.odb +info: design 'cpu' has no physical info [WRITE-120] +warning: WrSdc.. design 'cpu' has no timing constraints [TA-118] +> read_sdc -verbose ./constraints/riscv.sdc +> create_clock -name clk_25mhz -period 40.000 -waveform { 0 20 } clk_25mhz +> set_clock_uncertainty -setup 0.5 clk_25mhz +> set_clock_uncertainty -hold 0.2 clk_25mhz +> set_clock_transition 0.1 clk_25mhz +> set_input_delay -clock clk_25mhz -max 2.0 { btn[6] btn[5] btn[4] btn[3] btn[2] btn[1] btn[0] } +> set_input_delay -clock clk_25mhz -min 0.5 { btn[6] btn[5] btn[4] btn[3] btn[2] btn[1] btn[0] } +> set_output_delay -clock clk_25mhz -max 2.0 { led[7] led[6] led[5] led[4] led[3] led[2] led[1] led[0] } +> set_output_delay -clock clk_25mhz -min 0.5 { led[7] led[6] led[5] led[4] led[3] led[2] led[1] led[0] } +> set_false_path -from btn[0] +# set_false_path -from btn[0] +> set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 { btn[6] btn[5] btn[4] btn[3] btn[2] btn[1] btn[0] } +> set_load 0.05 { led[7] led[6] led[5] led[4] led[3] led[2] led[1] led[0] } +> current_design +> set_max_fanout 20 cpu +> current_design +> set_max_transition 0.5 cpu +info: 'set_max_fanout' command ignored 1 time(s) [SDC-148] +info: 'set_max_transition' command ignored 1 time(s) [SDC-150] +> report_design_metrics +Report Physical info: +------------------------+--------+-----------+------------ + | |Area (squm)|Leakage (uW) +------------------------+--------+-----------+------------ +Design Name |cpu | | + Total Instances | 7261| 60155| 625.778 + Macros | 4| 46249| 518.216 + Pads | 0| 0| 0.000 + Phys | 0| 0| 0.000 + Blackboxes | 0| 0| 0.000 + Cells | 7257| 13906| 107.562 + Buffers | 0| 0| 0.000 + Inverters | 640| 340| 4.488 + Clock-Gates | 31| 107| 0.667 + Combinational | 5423| 6454| 51.129 + Latches | 32| 85| 0.602 + FlipFlops | 1131| 6919| 50.677 + Single-Bit FF | 1131| 6919| 50.677 + Multi-Bit FF | 0| 0| 0.000 + Clock-Gated | 992| | + Bits | 1131| 6919| 50.677 + Load-Enabled | 0| | + Clock-Gated | 992| | + Tristate Pin Count | 0| | +Physical Info |Unplaced| | + Chip Size (mm x mm) | | 0| + Fixed Cell Area | | 0| + Phys Only | 0| 0| + Placeable Area | | 0| + Movable Cell Area | | 60155| + Utilization (%) | | | + Chip Utilization (%) | | | + Total Wire Length (mm)| 0.000| | + Longest Wire (mm) | | | + Average Wire (mm) | | | +------------------------+--------+-----------+------------ +> check_timing +Report Check Timing: +-----+------------------------------+------+--------+------+----------------------------------------------- + |Item |Errors|Warnings|Status|Description +-----+------------------------------+------+--------+------+----------------------------------------------- +1 |no_clock_defined | 0| 0|Passed|No clock is defined in the design +2 |invalid_generated_clock | 0| 0|Passed|Generated clock is not sourced by a valid clock +3 |unconstrained_IO | 0| 0|Passed|Unconstrained IO pin +4 |unexpected_assertion | 0| 0|Passed|Found unexpected timing assertion +5 |trigger_pin_without_required | 0| 32|Passed|Trigger pin does not get required data +6 |setup_pin_without_data | 0| 0|Passed|Setup pin does not get arriving data +7 |setup_pin_with_clock | 0| 0|Passed|Setup pin has clock signal arriving +8 |clock_pin_with_multiple_clocks| 0| 0|Passed|Clock pin has multiple clock signals +9 |clock_pin_without_clock | 0| 1|Passed|Clock pin does not have clock signal +10 |clock_pin_with_data | 0| 1|Passed|Clock pin has data signal arriving +-----+------------------------------+------+--------+------+----------------------------------------------- +> all_inputs +> group_path -name I2R -from { btn[6] btn[5] btn[4] btn[3] btn[2] btn[1] btn[0] clk_25mhz } +# group_path -from {btn[6]} {btn[5]} {btn[4]} {btn[3]} {btn[2]} {btn[1]} {btn[0]} clk_25mhz +> all_inputs +> all_outputs +> group_path -name I2O -from { btn[6] btn[5] btn[4] btn[3] btn[2] btn[1] btn[0] clk_25mhz } -to { led[7] led[6] led[5] led[4] led[3] led[2] led[1] led[0] } +# group_path -from {btn[6]} {btn[5]} {btn[4]} {btn[3]} {btn[2]} {btn[1]} {btn[0]} clk_25mhz -to {led[7]} {led[6]} {led[5]} {led[4]} {led[3]} {led[2]} {led[1]} {led[0]} +> all_outputs +> group_path -name R2O -to { led[7] led[6] led[5] led[4] led[3] led[2] led[1] led[0] } +# group_path -to {led[7]} {led[6]} {led[5]} {led[4]} {led[3]} {led[2]} {led[1]} {led[0]} +> report_path_groups +Report Path Groups: +-----+-------+------+---------+--------- + | Path |Weight|Critical |Worst + | Group | |Range(ps)|Slack(ps) +-----+-------+------+---------+--------- +1 |default| 1.000| 0.0| 17832.1 +2 |I2R | 1.000| 0.0| +3 |I2O | 1.000| 0.0| +4 |R2O | 1.000| 0.0| 36153.7 +-----+-------+------+---------+--------- +> optimize -virtual +starting optimize at 00:00:03(cpu)/0:00:08(wall) 168MB(vsz)/530MB(peak) +info: mapped 0 flop(s) to scan cells, excluded 0 is_dont_scan flop(s) and 0 is_dont_touch flop(s) +Log file for child PID=2567791: /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.etc.02/oasys.w1.02.log +Log file for child PID=2567797: /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.etc.02/oasys.w2.02.log +Log file for child PID=2567802: /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.etc.02/oasys.w3.02.log +Log file for child PID=2567810: /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.etc.02/oasys.w4.02.log +info: optimized '' area changed 0.0squm (x1), total 13904.4squm (#1, 0 secs) +info: dissolving instance 'thePC' of module 'pc' in module 'cpu__GC0' [NL-146] +info: optimized 'cpu__GC0' area changed -1457.9squm (x1), total 12446.4squm (#2) +info: optimized 'reg_file__GB1' area changed -841.1squm (x1), total 11605.3squm (#3) +info: optimized 'reg_file__always' area changed -83.5squm (x1), total 11521.8squm (#4) +info: optimized 'main_mem__GC0' area changed -90.4squm (x1), total 11431.3squm (#5) +info: optimized 'MemGen_32_11__block' area changed -2.4squm (x1), total 11429.0squm (#6) +info: optimized '' area changed 0.0squm (x1), total 11429.0squm (#7, 0 secs) +info: optimized 'cpu__GC0' area changed 0.0squm (x1), total 11429.0squm (#8) +info: optimized 'MemGen_32_11__block' area changed 0.0squm (x1), total 11429.0squm (#9) +info: optimized '' area changed 0.0squm (x1), total 11429.0squm (#10, 0 secs) +done optimizing area at 00:00:15(cpu)/0:00:15(wall) 169MB(vsz)/566MB(peak) +Splitting congested rtl-partitions +info: Target library/cell information has changed that further may change timing results. [TA-159] +info: optimizing design 'cpu' - propagating constants +info: optimized '' area changed 0.0squm (x1), total 11429.0squm (#1, 0 secs) +info: set slack mode to optimize shift +info: resetting all path groups +info: activated path group default @ 18015.8ps +info: suspended path group I2R @ ps +info: suspended path group I2O @ ps +info: activated path group R2O @ 36338.3ps +info: finished path group default @ 18015.8ps +info: finished path group R2O @ 36338.3ps +info: reactivating path groups +info: reactivated path group default @ 18015.8ps +info: reactivated path group R2O @ 36338.3ps +info: finished path group default @ 18015.8ps +info: finished path group R2O @ 36338.3ps +info: set slack mode to normal +info: done with all path groups +info: restore all path groups +info: starting area recovery on module cpu +info: optimized 'cpu__GC0' area recovered 0.00squm (x1), total 0.00squm (1#5), 0.03 secs +info: optimized 'main_mem__GC0' area recovered 0.00squm (x1), total 0.00squm (2#5), 0.05 secs +info: optimized 'MemGen_32_11__block' area recovered 0.00squm (x1), total 0.00squm (3#5), 0.00 secs +info: optimized 'reg_file__always' area recovered 0.00squm (x1), total 0.00squm (4#5), 0.01 secs +info: optimized 'reg_file__GB1' area recovered 0.00squm (x1), total 0.00squm (5#5), 0.02 secs +info: area recovery done, total area reduction: 0.00squm (0.00%), final slack: 18015.8ps (delta: 0.0ps) (0 secs) +done optimizing virtual at 00:00:16(cpu)/0:00:16(wall) 185MB(vsz)/566MB(peak) +finished optimize at 00:00:16(cpu)/0:00:16(wall) 185MB(vsz)/566MB(peak) +> write_db ./output/odb/riscv_chip.virtual_opt.odb +> report_timing +Report for group default +-------------------------------------------------------------------------------------------------------------------------------------- +Startpoint: theMem/IRData_reg[18]/Q + (Clocked by clk_25mhz R) +Endpoint: theMem/mem_addr_reg[5]/D + (Clocked by clk_25mhz F) +Path Group: default +Data required time: 19227.4 + (Clock shift: 20000.0, minus Uncertainty: 500.0, plus Latency 0.0, minus Setup time: 272.6) +Data arrival time: 1211.5 +Slack: 18015.8 +Logic depth: 46 +-------------------------------------------------------------------------------------------------------------------------------------- + Arrival Arc Net Net Total fan- +Path Module/Cell Edge Time Delay Delay Delay Slew Load Load out Location + (ps) (ps) (ps) (ps) (ps) (ff) (ff) (#) (um,um) +-------------------------------------------------------------------------------------------------------------------------------------- +clk_25mhz {create_clock} r 0.0 0.0 0.0 0.0 0.0 100 +theMem/IRData_reg[18]/CK->Q + SDFF_X1_LVT* rr 84.9 84.9 84.9 0.0 100.0 10.6 73.4 11 +theRegisters/i_1_0_1371/A->ZN + INV_X8_LVT rf 87.6 2.7 2.7 0.0 10.2 2.1 13.2 3 +theRegisters/i_1_0_1339/A2->ZN + NAND3_X4_LVT fr 101.6 14.0 14.0 0.0 1.0 2.5 17.5 4 +theRegisters/i_1_0_1321/A2->ZN + NOR2_X4_LVT* rf 120.6 19.0 19.0 0.0 12.1 29.7 130.1 32 +theRegisters/i_1_0_722/B1->ZN + AOI22_X4_LVT* fr 164.9 44.3 44.3 0.0 10.2 0.7 23.4 1 +theRegisters/i_1_0_721/A->ZN + INV_X8_LVT rf 167.0 2.1 2.1 0.0 10.2 0.8 3.0 1 +theRegisters/i_1_0_718/A->ZN + AOI221_X2_LVT fr 224.3 57.3 57.3 0.0 0.6 0.9 4.4 1 +theRegisters/i_1_0_716/A3->ZN + NAND4_X4_LVT rf 239.7 15.4 15.4 0.0 34.6 0.9 3.1 1 +theRegisters/i_1_0_715/A->ZN + AOI221_X2_LVT fr 297.1 57.4 57.4 0.0 6.8 0.9 4.3 1 +theRegisters/i_1_0_704/A2->ZN + NAND4_X4_LVT rf 317.6 20.5 20.5 0.0 34.4 5.9 16.7 3 +theDecoder/i_0_133/C2->ZN + AOI222_X4_LVT fr 428.0 110.5 110.5 0.0 12.2 0.8 23.5 1 +theDecoder/i_0_132/A->ZN INV_X32_LVT rf 431.2 3.1 3.1 0.0 10.9 5.4 65.3 7 +theDecoder/theALU/i_0_706/B1->ZN + OAI22_X4_LVT* fr 474.4 43.2 43.2 0.0 1.4 1.5 25.9 2 +theDecoder/theALU/i_0_705/A->ZN + INV_X8_LVT rf 476.5 2.2 2.2 0.0 10.2 0.6 4.2 1 +theDecoder/theALU/i_0_42/A->ZN + OAI21_X2_LVT fr 485.6 9.1 9.1 0.0 0.6 0.8 2.5 1 +theDecoder/theALU/i_0_40/C1->ZN + AOI211_X2_LVT rf 491.3 5.6 5.6 0.0 11.6 0.8 2.9 1 +theDecoder/theALU/i_0_39/B->ZN + AOI211_X2_LVT fr 538.7 47.4 47.4 0.0 3.3 0.9 3.0 1 +theDecoder/theALU/i_0_38/B2->ZN + OAI222_X2_LVT rf 555.6 16.9 16.9 0.0 27.7 0.9 2.9 1 +theDecoder/theALU/i_0_37/C2->ZN + AOI221_X2_LVT fr 599.5 43.8 43.8 0.0 8.4 0.9 4.2 1 +theDecoder/theALU/i_0_35/B1->ZN + OAI22_X4_LVT* rf 613.4 13.9 13.9 0.0 34.0 0.7 23.4 1 +theDecoder/theALU/i_0_34/A->ZN + INV_X8_LVT fr 617.9 4.5 4.5 0.0 10.2 0.6 4.1 1 +theDecoder/theALU/i_0_33/A->ZN + AOI21_X4_LVT rf 620.5 2.6 2.6 0.0 2.4 0.8 3.0 1 +theDecoder/theALU/i_0_32/C2->ZN + OAI222_X2_LVT fr 659.0 38.5 38.5 0.0 2.6 0.9 3.3 1 +theDecoder/theALU/i_0_31/A->ZN + OAI221_X2_LVT rf 675.0 16.0 16.0 0.0 29.2 0.8 4.0 1 +theDecoder/theALU/i_0_28/B1->ZN + AOI21_X4_LVT fr 690.5 15.5 15.5 0.0 8.2 0.8 3.0 1 +theDecoder/theALU/i_0_27/A->ZN + AOI221_X2_LVT rf 694.7 4.2 4.2 0.0 13.5 0.9 2.9 1 +theDecoder/theALU/i_0_26/B->ZN + AOI211_X2_LVT fr 746.9 52.2 52.2 0.0 5.3 0.8 4.6 1 +theDecoder/theALU/i_0_25/B2->ZN + OAI22_X2_LVT rf 756.6 9.7 9.7 0.0 31.8 0.8 2.7 1 +theDecoder/theALU/i_0_24/C2->ZN + AOI211_X2_LVT fr 791.0 34.4 34.4 0.0 4.0 0.9 3.1 1 +theDecoder/theALU/i_0_23/A->ZN + AOI221_X2_LVT rf 796.7 5.8 5.8 0.0 27.8 0.9 3.1 1 +theDecoder/theALU/i_0_22/A->ZN + AOI221_X2_LVT fr 850.4 53.7 53.7 0.0 5.4 0.9 3.1 1 +theDecoder/theALU/i_0_21/A->ZN + AOI221_X2_LVT rf 856.5 6.1 6.1 0.0 31.2 0.9 3.1 1 +theDecoder/theALU/i_0_20/C2->ZN + OAI222_X2_LVT fr 895.2 38.8 38.8 0.0 5.4 0.9 3.3 1 +theDecoder/theALU/i_0_19/A->ZN + OAI221_X2_LVT rf 911.8 16.6 16.6 0.0 29.2 0.9 4.7 1 +theDecoder/theALU/i_0_18/B2->ZN + AOI22_X4_LVT fr 942.1 30.3 30.3 0.0 8.6 0.8 4.4 1 +theDecoder/theALU/i_0_17/B2->ZN + OAI21_X4_LVT rf 948.5 6.4 6.4 0.0 16.9 0.7 4.3 1 +theDecoder/theALU/i_0_16/A->ZN + OAI21_X4_LVT fr 958.3 9.8 9.8 0.0 3.6 0.7 3.9 1 +theDecoder/theALU/i_0_13/B1->ZN + AOI21_X4_LVT rf 963.5 5.3 5.3 0.0 12.5 0.8 4.4 1 +theDecoder/theALU/i_0_12/A4->ZN + NOR4_X2_LVT fr 1020.0 56.5 56.5 0.0 2.9 0.8 2.8 1 +theDecoder/theALU/i_0_0/A3->ZN + OR3_X4_LVT rr 1036.6 16.6 16.6 0.0 29.1 0.7 14.7 2 +theDecoder/i_0_114/B->ZN XNOR2_X2_LVT rf 1043.2 6.5 6.5 0.0 7.8 0.7 4.3 1 +theDecoder/i_0_113/B1->ZN + AOI22_X4_LVT fr 1069.7 26.5 26.5 0.0 5.1 0.8 4.4 1 +theDecoder/i_0_111/A2->ZN + AOI22_X4_LVT rf 1076.1 6.4 6.4 0.0 16.9 0.7 4.3 1 +theDecoder/i_0_110/A2->ZN + NAND2_X4_LVT* fr 1095.3 19.2 19.2 0.0 4.4 9.0 37.6 13 +i_0_0_60/S->Z MUX2_X2_LVT* rf 1161.7 66.4 66.4 0.0 10.2 11.1 66.7 3 +theMem/i_0_0_11/B2->ZN AOI22_X4_LVT* fr 1209.5 47.8 47.8 0.0 10.2 0.7 23.4 1 +theMem/i_0_0_10/A->ZN INV_X8_LVT rf 1211.5 2.0 2.0 0.0 10.2 0.8 1.8 1 +theMem/mem_addr_reg[5]/D SDFF_X1_LVT f 1211.5 0.0 0.0 0.5 +-------------------------------------------------------------------------------------------------------------------------------------- +Report for group I2R +Report for group I2O +Report for group R2O +-------------------------------------------------------------------------------------------------------------------------------------- +Startpoint: theMem/IRData_reg[18]/Q + (Clocked by clk_25mhz R) +Endpoint: led[7] + (Clocked by clk_25mhz R) +Path Group: R2O +Data required time: 37500.0 + (Clock shift: 40000.0, minus Uncertainty: 500.0, plus Latency 0.0, minus Out delay: 2000.0) +Data arrival time: 1161.7 +Slack: 36338.3 +Logic depth: 44 +-------------------------------------------------------------------------------------------------------------------------------------- + Arrival Arc Net Net Total fan- +Path Module/Cell Edge Time Delay Delay Delay Slew Load Load out Location + (ps) (ps) (ps) (ps) (ps) (ff) (ff) (#) (um,um) +-------------------------------------------------------------------------------------------------------------------------------------- +clk_25mhz {create_clock} r 0.0 0.0 0.0 0.0 0.0 100 +theMem/IRData_reg[18]/CK->Q + SDFF_X1_LVT* rr 84.9 84.9 84.9 0.0 100.0 10.6 73.4 11 +theRegisters/i_1_0_1371/A->ZN + INV_X8_LVT rf 87.6 2.7 2.7 0.0 10.2 2.1 13.2 3 +theRegisters/i_1_0_1339/A2->ZN + NAND3_X4_LVT fr 101.6 14.0 14.0 0.0 1.0 2.5 17.5 4 +theRegisters/i_1_0_1321/A2->ZN + NOR2_X4_LVT* rf 120.6 19.0 19.0 0.0 12.1 29.7 130.1 32 +theRegisters/i_1_0_722/B1->ZN + AOI22_X4_LVT* fr 164.9 44.3 44.3 0.0 10.2 0.7 23.4 1 +theRegisters/i_1_0_721/A->ZN + INV_X8_LVT rf 167.0 2.1 2.1 0.0 10.2 0.8 3.0 1 +theRegisters/i_1_0_718/A->ZN + AOI221_X2_LVT fr 224.3 57.3 57.3 0.0 0.6 0.9 4.4 1 +theRegisters/i_1_0_716/A3->ZN + NAND4_X4_LVT rf 239.7 15.4 15.4 0.0 34.6 0.9 3.1 1 +theRegisters/i_1_0_715/A->ZN + AOI221_X2_LVT fr 297.1 57.4 57.4 0.0 6.8 0.9 4.3 1 +theRegisters/i_1_0_704/A2->ZN + NAND4_X4_LVT rf 317.6 20.5 20.5 0.0 34.4 5.9 16.7 3 +theDecoder/i_0_133/C2->ZN + AOI222_X4_LVT fr 428.0 110.5 110.5 0.0 12.2 0.8 23.5 1 +theDecoder/i_0_132/A->ZN INV_X32_LVT rf 431.2 3.1 3.1 0.0 10.9 5.4 65.3 7 +theDecoder/theALU/i_0_706/B1->ZN + OAI22_X4_LVT* fr 474.4 43.2 43.2 0.0 1.4 1.5 25.9 2 +theDecoder/theALU/i_0_705/A->ZN + INV_X8_LVT rf 476.5 2.2 2.2 0.0 10.2 0.6 4.2 1 +theDecoder/theALU/i_0_42/A->ZN + OAI21_X2_LVT fr 485.6 9.1 9.1 0.0 0.6 0.8 2.5 1 +theDecoder/theALU/i_0_40/C1->ZN + AOI211_X2_LVT rf 491.3 5.6 5.6 0.0 11.6 0.8 2.9 1 +theDecoder/theALU/i_0_39/B->ZN + AOI211_X2_LVT fr 538.7 47.4 47.4 0.0 3.3 0.9 3.0 1 +theDecoder/theALU/i_0_38/B2->ZN + OAI222_X2_LVT rf 555.6 16.9 16.9 0.0 27.7 0.9 2.9 1 +theDecoder/theALU/i_0_37/C2->ZN + AOI221_X2_LVT fr 599.5 43.8 43.8 0.0 8.4 0.9 4.2 1 +theDecoder/theALU/i_0_35/B1->ZN + OAI22_X4_LVT* rf 613.4 13.9 13.9 0.0 34.0 0.7 23.4 1 +theDecoder/theALU/i_0_34/A->ZN + INV_X8_LVT fr 617.9 4.5 4.5 0.0 10.2 0.6 4.1 1 +theDecoder/theALU/i_0_33/A->ZN + AOI21_X4_LVT rf 620.5 2.6 2.6 0.0 2.4 0.8 3.0 1 +theDecoder/theALU/i_0_32/C2->ZN + OAI222_X2_LVT fr 659.0 38.5 38.5 0.0 2.6 0.9 3.3 1 +theDecoder/theALU/i_0_31/A->ZN + OAI221_X2_LVT rf 675.0 16.0 16.0 0.0 29.2 0.8 4.0 1 +theDecoder/theALU/i_0_28/B1->ZN + AOI21_X4_LVT fr 690.5 15.5 15.5 0.0 8.2 0.8 3.0 1 +theDecoder/theALU/i_0_27/A->ZN + AOI221_X2_LVT rf 694.7 4.2 4.2 0.0 13.5 0.9 2.9 1 +theDecoder/theALU/i_0_26/B->ZN + AOI211_X2_LVT fr 746.9 52.2 52.2 0.0 5.3 0.8 4.6 1 +theDecoder/theALU/i_0_25/B2->ZN + OAI22_X2_LVT rf 756.6 9.7 9.7 0.0 31.8 0.8 2.7 1 +theDecoder/theALU/i_0_24/C2->ZN + AOI211_X2_LVT fr 791.0 34.4 34.4 0.0 4.0 0.9 3.1 1 +theDecoder/theALU/i_0_23/A->ZN + AOI221_X2_LVT rf 796.7 5.8 5.8 0.0 27.8 0.9 3.1 1 +theDecoder/theALU/i_0_22/A->ZN + AOI221_X2_LVT fr 850.4 53.7 53.7 0.0 5.4 0.9 3.1 1 +theDecoder/theALU/i_0_21/A->ZN + AOI221_X2_LVT rf 856.5 6.1 6.1 0.0 31.2 0.9 3.1 1 +theDecoder/theALU/i_0_20/C2->ZN + OAI222_X2_LVT fr 895.2 38.8 38.8 0.0 5.4 0.9 3.3 1 +theDecoder/theALU/i_0_19/A->ZN + OAI221_X2_LVT rf 911.8 16.6 16.6 0.0 29.2 0.9 4.7 1 +theDecoder/theALU/i_0_18/B2->ZN + AOI22_X4_LVT fr 942.1 30.3 30.3 0.0 8.6 0.8 4.4 1 +theDecoder/theALU/i_0_17/B2->ZN + OAI21_X4_LVT rf 948.5 6.4 6.4 0.0 16.9 0.7 4.3 1 +theDecoder/theALU/i_0_16/A->ZN + OAI21_X4_LVT fr 958.3 9.8 9.8 0.0 3.6 0.7 3.9 1 +theDecoder/theALU/i_0_13/B1->ZN + AOI21_X4_LVT rf 963.5 5.3 5.3 0.0 12.5 0.8 4.4 1 +theDecoder/theALU/i_0_12/A4->ZN + NOR4_X2_LVT fr 1020.0 56.5 56.5 0.0 2.9 0.8 2.8 1 +theDecoder/theALU/i_0_0/A3->ZN + OR3_X4_LVT rr 1036.6 16.6 16.6 0.0 29.1 0.7 14.7 2 +theDecoder/i_0_114/B->ZN XNOR2_X2_LVT rf 1043.2 6.5 6.5 0.0 7.8 0.7 4.3 1 +theDecoder/i_0_113/B1->ZN + AOI22_X4_LVT fr 1069.7 26.5 26.5 0.0 5.1 0.8 4.4 1 +theDecoder/i_0_111/A2->ZN + AOI22_X4_LVT rf 1076.1 6.4 6.4 0.0 16.9 0.7 4.3 1 +theDecoder/i_0_110/A2->ZN + NAND2_X4_LVT* fr 1095.3 19.2 19.2 0.0 4.4 9.0 37.6 13 +i_0_0_60/S->Z MUX2_X2_LVT* rf 1161.7 66.4 66.4 0.0 10.2 11.1 66.7 3 +led[7] f 1161.7 0.0 0.0 10.2 +-------------------------------------------------------------------------------------------------------------------------------------- +> report_path_groups +Report Path Groups: +-----+-------+------+---------+--------- + | Path |Weight|Critical |Worst + | Group | |Range(ps)|Slack(ps) +-----+-------+------+---------+--------- +1 |default| 1.000| 0.0| 18015.8 +2 |I2R | 1.000| 0.0| +3 |I2O | 1.000| 0.0| +4 |R2O | 1.000| 0.0| 36338.3 +-----+-------+------+---------+--------- + +------------------------------------- + +Synthesis and optimization complete + +------------------------------------- + +INFO::Running oasys Tessent DFT flow +> source scripts_risc_v/oasys_tessent_dft.tcl +INFO::using /applications/SiemensEDA/siemenseda2023/tessent/bin/tessent build to run the Tessent DFT flow +> config_tessent -exec_path /applications/SiemensEDA/siemenseda2023/tessent/bin/tessent +> define_test_clock -pin clk_25mhz +> define_test_pin -pin scan_en -scan_mode 1 -default_scan_enable -create_port +Adding Test pin scan_en to top Module +> set_dont_scan theMem true +> define_test_pin -name reset -pin {btn[0]} -scan_mode 1 +> check_dft -auto_test_clock -auto_test_pins +starting check_dft at 00:00:17(cpu)/0:00:16(wall) 185MB(vsz)/566MB(peak) +Checking DFT rules for 'cpu' + Running DFT TDRC iteration 1 + Total 1131 scanModels/flops with 12% scanable (139 pass, 992 fail, 0 nonScan or excludeScan) +Report Check DFT: +-----+---------------------+------+--------+------+------------------------------------------- + |Item |Errors|Warnings|Status|Description +-----+---------------------+------+--------+------+------------------------------------------- +1 |internal_clock | 0| 0|Passed|Internal Clock +2 |constant_clock | 0| 0|Passed|Constant Clock +3 |non_clock_PI | 0| 0|Passed|Non-Clock PI +4 |blocking_clock_gate | 0| 31|Failed|Blocking clock gate +5 |internal_async | 0| 0|Passed|Internal Async. Set/Reset control +6 |constant_active_async| 0| 0|Passed|Constant active Async. Set/Reset signal +7 |non_test_PI | 0| 0|Passed|Unconstrained PI driving Async/ Set/Reset +8 |async_clock_conflict | 0| 0|Passed|Async. Set/Reset signal and Clock conflict +9 |parallel_scan_clock | 0| 0|Passed|Clock pin of unsupported parallel-scan flop +-----+---------------------+------+--------+------+------------------------------------------- +Design has 31 DFT violation(s) +finished check_dft at 00:00:17(cpu)/0:00:17(wall) 185MB(vsz)/566MB(peak) +> write_db ./output/odb/riscv.tessent_pre_fix.odb +> fix_dft_violations -type all -test_clock clk_25mhz -test_control scan_en +Created 0 gates to fix Async violation(s) +Created 0 muxes to fix clock violation(s) +Replaced 31 clock-gating cells to fix clock-gating violation(s) +> report_dft_violations +Report DftViolations: +-----+-------------------+-----------------------------------------------+-------------------- + | Type | Pin | Affected Registers +-----+-------------------+-----------------------------------------------+-------------------- +1 |blocking clock gate|theRegisters/clk_gate_registers_reg[1]_reg/GCK | 32 +2 |blocking clock gate|theRegisters/clk_gate_registers_reg[2]_reg/GCK | 32 +3 |blocking clock gate|theRegisters/clk_gate_registers_reg[3]_reg/GCK | 32 +4 |blocking clock gate|theRegisters/clk_gate_registers_reg[4]_reg/GCK | 32 +5 |blocking clock gate|theRegisters/clk_gate_registers_reg[5]_reg/GCK | 32 +6 |blocking clock gate|theRegisters/clk_gate_registers_reg[6]_reg/GCK | 32 +7 |blocking clock gate|theRegisters/clk_gate_registers_reg[7]_reg/GCK | 32 +8 |blocking clock gate|theRegisters/clk_gate_registers_reg[8]_reg/GCK | 32 +9 |blocking clock gate|theRegisters/clk_gate_registers_reg[9]_reg/GCK | 32 +10 |blocking clock gate|theRegisters/clk_gate_registers_reg[10]_reg/GCK| 32 +11 |blocking clock gate|theRegisters/clk_gate_registers_reg[11]_reg/GCK| 32 +12 |blocking clock gate|theRegisters/clk_gate_registers_reg[12]_reg/GCK| 32 +13 |blocking clock gate|theRegisters/clk_gate_registers_reg[13]_reg/GCK| 32 +14 |blocking clock gate|theRegisters/clk_gate_registers_reg[14]_reg/GCK| 32 +15 |blocking clock gate|theRegisters/clk_gate_registers_reg[15]_reg/GCK| 32 +16 |blocking clock gate|theRegisters/clk_gate_registers_reg[16]_reg/GCK| 32 +17 |blocking clock gate|theRegisters/clk_gate_registers_reg[17]_reg/GCK| 32 +18 |blocking clock gate|theRegisters/clk_gate_registers_reg[18]_reg/GCK| 32 +19 |blocking clock gate|theRegisters/clk_gate_registers_reg[19]_reg/GCK| 32 +20 |blocking clock gate|theRegisters/clk_gate_registers_reg[20]_reg/GCK| 32 +21 |blocking clock gate|theRegisters/clk_gate_registers_reg[21]_reg/GCK| 32 +22 |blocking clock gate|theRegisters/clk_gate_registers_reg[22]_reg/GCK| 32 +23 |blocking clock gate|theRegisters/clk_gate_registers_reg[23]_reg/GCK| 32 +24 |blocking clock gate|theRegisters/clk_gate_registers_reg[24]_reg/GCK| 32 +25 |blocking clock gate|theRegisters/clk_gate_registers_reg[25]_reg/GCK| 32 +26 |blocking clock gate|theRegisters/clk_gate_registers_reg[26]_reg/GCK| 32 +27 |blocking clock gate|theRegisters/clk_gate_registers_reg[27]_reg/GCK| 32 +28 |blocking clock gate|theRegisters/clk_gate_registers_reg[28]_reg/GCK| 32 +29 |blocking clock gate|theRegisters/clk_gate_registers_reg[29]_reg/GCK| 32 +30 |blocking clock gate|theRegisters/clk_gate_registers_reg[30]_reg/GCK| 32 +31 |blocking clock gate|theRegisters/clk_gate_registers_reg[31]_reg/GCK| 32 +-----+-------------------+-----------------------------------------------+-------------------- +> optimize +starting optimize at 00:00:18(cpu)/0:00:17(wall) 185MB(vsz)/566MB(peak) +info: mapped 107 flop(s) to scan cells, excluded 107 is_dont_scan flop(s) and 0 is_dont_touch flop(s) +info: Target library/cell information has changed that further may change timing results. [TA-159] +info: optimizing design 'cpu' - propagating constants +info: optimized '' area changed 0.0squm (x1), total 11274.7squm (#1, 0 secs) +info: set slack mode to optimize shift +info: resetting all path groups +info: activated path group default @ 18139.2ps +info: suspended path group I2R @ ps +info: suspended path group I2O @ ps +info: activated path group R2O @ 36317.8ps +info: finished path group default @ 18139.2ps +info: finished path group R2O @ 36317.8ps +info: reactivating path groups +info: reactivated path group default @ 18139.2ps +info: reactivated path group R2O @ 36317.8ps +info: finished path group default @ 18139.2ps +info: finished path group R2O @ 36317.8ps +info: set slack mode to normal +info: done with all path groups +info: restore all path groups +info: starting area recovery on module cpu +info: optimized 'cpu__GC0' area recovered 0.00squm (x1), total 0.00squm (1#5), 0.04 secs +info: optimized 'main_mem__GC0' area recovered 0.00squm (x1), total 0.00squm (2#5), 0.04 secs +info: optimized 'MemGen_32_11__block' area recovered 0.00squm (x1), total 0.00squm (3#5), 0.00 secs +info: optimized 'reg_file__always' area recovered 0.00squm (x1), total 0.00squm (4#5), 0.01 secs +info: optimized 'reg_file__GB1' area recovered 0.00squm (x1), total 0.00squm (5#5), 0.03 secs +info: area recovery done, total area reduction: 0.00squm (0.00%), final slack: 18139.2ps (delta: 0.0ps) (0 secs) +done optimizing virtual at 00:00:18(cpu)/0:00:18(wall) 189MB(vsz)/566MB(peak) +info: floorplan : total 4 movable macros and 0 fixed macros +info: creating tracks for 10 routing layers [FP-148] +info: start floorplan stage 0 [FP-145] +info: end floorplan stage 0 [FP-145] +info: start floorplan stage 1 [FP-145] +info: end floorplan stage 1 [FP-145] +info: start rtl partition placement [PLACE-114] +info: placement mode : raw [PLACE-115] +info: set slack mode to weight modified +info: set slack mode to normal +info: set slack mode to optimize shift +info: timing-driven placement : ON [PLACE-116] +info: congestion-driven placement : ON [PLACE-117] +info: placement movable objects : macros 0 , rtl partitions 5, cells 0 [PLACE-118] +info: start placement stage 0 [PLACE-111] +info: end placement stage 0 [PLACE-111] +info: set slack mode to normal +info: cell density map (bin size 20 x 20 rows), maximum utilization: 170.00% average utilization: 13.98% [PLACE-153] +info: 9.00% bins with overflow, average overflow 18.49% [PLACE-154] +info: P-D: 0.090% (0.185 ~ 0.700) +Total Wire Length = 77698.10 +Average Wire = 58.60 +Longest Wire = 352.69 +Shortest Wire = 0.00 +WNS = 18139.5ps +info: placing 17 unplaced IO Pins +info: start rtl partition placement [PLACE-114] +info: placement mode : raw [PLACE-115] +info: set slack mode to weight modified +info: set slack mode to normal +info: set slack mode to optimize shift +info: timing-driven placement : ON [PLACE-116] +info: congestion-driven placement : ON [PLACE-117] +info: placement movable objects : macros 0 , rtl partitions 5, cells 0 [PLACE-118] +info: start placement stage 0 [PLACE-111] +info: end placement stage 0 [PLACE-111] +info: set slack mode to normal +info: cell density map (bin size 20 x 20 rows), maximum utilization: 90.53% average utilization: 14.23% [PLACE-153] +info: 0.00% bins with overflow, average overflow 0.00% [PLACE-154] +info: P-D: 0.000% (0.000 ~ 0.000) +Total Wire Length = 115431.45 +Average Wire = 87.05 +Longest Wire = 426.66 +Shortest Wire = 10.50 +WNS = 18131.2ps +info: 0 power/ground pre-route segments processed. [PLACE-144] +info: 0 routing blockages processed. [PLACE-145] +info: replaced @ 18131.2ps +done optimize placement at 00:00:22(cpu)/0:00:21(wall) 375MB(vsz)/822MB(peak) +info: cell density map (bin size 20 x 20 rows), maximum utilization: 90.53% average utilization: 14.23% [PLACE-153] +info: 0.00% bins with overflow, average overflow 0.00% [PLACE-154] +info: set slack mode to optimize shift +info: resetting all path groups +info: activated path group default @ 18131.2ps +info: suspended path group I2R @ ps +info: suspended path group I2O @ ps +info: activated path group R2O @ 36309.8ps +info: finished path group default @ 18131.2ps +info: finished path group R2O @ 36309.8ps +info: reactivating path groups +info: reactivated path group default @ 18131.2ps +info: reactivated path group R2O @ 36309.8ps +info: finished path group default @ 18131.2ps +info: finished path group R2O @ 36309.8ps +info: cell density map (bin size 20 x 20 rows), maximum utilization: 90.53% average utilization: 14.23% [PLACE-153] +info: 0.00% bins with overflow, average overflow 0.00% [PLACE-154] +info: 0 power/ground pre-route segments processed. [PLACE-144] +info: 0 routing blockages processed. [PLACE-145] +info: set slack mode to normal +info: done with all path groups +info: restore all path groups +info: (0) optimizing 'theMem/i_0/IAddr[5]' (path group default) @ 18131.2ps(1/1) (4 secs) +finished optimize at 00:00:22(cpu)/0:00:21(wall) 375MB(vsz)/822MB(peak) +> write_db ./output/odb/riscv.tessent_post_fix.odb +> write_verilog ./output/riscv.tessent_post_fix.v +info: writing Verilog file './output/riscv.tessent_post_fix.v' for module 'cpu' [WRITE-100] +> config_tessent -library {./libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib ./libs/fastscan/NangateOpenCellLibrary_low_temp_ccs.fslib ./libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib ./libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib ./libs/fastscan/LowPowerOpenCellLibrary_low_temp_ccs.fslib ./libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib ./libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.fslib ./libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib ./libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib ./libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib ./libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib ./libs/fastscan/PLL.fslib ./libs/fastscan/IO.fslib} + +--------------check dft--------------- +> check_dft +starting check_dft at 00:00:23(cpu)/0:00:22(wall) 368MB(vsz)/822MB(peak) +Checking DFT rules for 'cpu' + Running DFT TDRC iteration 1 + Total 1131 scanModels/flops with 90% scanable (1024 pass, 0 fail, 107 nonScan or excludeScan) +Report Check DFT: +-----+---------------------+------+--------+------+------------------------------------------- + |Item |Errors|Warnings|Status|Description +-----+---------------------+------+--------+------+------------------------------------------- +1 |internal_clock | 0| 0|Passed|Internal Clock +2 |constant_clock | 0| 0|Passed|Constant Clock +3 |non_clock_PI | 0| 0|Passed|Non-Clock PI +4 |blocking_clock_gate | 0| 0|Passed|Blocking clock gate +5 |internal_async | 0| 0|Passed|Internal Async. Set/Reset control +6 |constant_active_async| 0| 0|Passed|Constant active Async. Set/Reset signal +7 |non_test_PI | 0| 0|Passed|Unconstrained PI driving Async/ Set/Reset +8 |async_clock_conflict | 0| 0|Passed|Async. Set/Reset signal and Clock conflict +9 |parallel_scan_clock | 0| 0|Passed|Clock pin of unsupported parallel-scan flop +-----+---------------------+------+--------+------+------------------------------------------- +Design has 0 DFT violation(s) +finished check_dft at 00:00:23(cpu)/0:00:22(wall) 368MB(vsz)/822MB(peak) + +--------------define Scan-Chains--------------- +> define_scan_chain -scan_in SI_1 -scan_out SO_1 -create_port +Defining Scan Chain scanChain_1( si:SI_1, so:SO_1) +Adding Scan-in pin SI_1 to top Module +Adding Scan-out pin SO_1 to top Module +> define_scan_chain -scan_in SI_2 -scan_out SO_2 -create_port +Defining Scan Chain scanChain_2( si:SI_2, so:SO_2) +Adding Scan-in pin SI_2 to top Module +Adding Scan-out pin SO_2 to top Module +> define_scan_chain -scan_in SI_3 -scan_out SO_3 -create_port +Defining Scan Chain scanChain_3( si:SI_3, so:SO_3) +Adding Scan-in pin SI_3 to top Module +Adding Scan-out pin SO_3 to top Module +> define_scan_chain -scan_in SI_4 -scan_out SO_4 -create_port +Defining Scan Chain scanChain_4( si:SI_4, so:SO_4) +Adding Scan-in pin SI_4 to top Module +Adding Scan-out pin SO_4 to top Module + +----------run_tessent_scan---------------- +> run_tessent_scan +info: writing Verilog file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.02/Scan_0/oasys_netlist.v' for module 'cpu' [WRITE-100] +starting check_dft at 00:00:23(cpu)/0:00:22(wall) 368MB(vsz)/822MB(peak) +Checking DFT rules for 'cpu' + Running DFT TDRC iteration 1 + Total 1131 scanModels/flops with 90% scanable (1024 pass, 0 fail, 107 nonScan or excludeScan) +Report Check DFT: +-----+---------------------+------+--------+------+------------------------------------------- + |Item |Errors|Warnings|Status|Description +-----+---------------------+------+--------+------+------------------------------------------- +1 |internal_clock | 0| 0|Passed|Internal Clock +2 |constant_clock | 0| 0|Passed|Constant Clock +3 |non_clock_PI | 0| 0|Passed|Non-Clock PI +4 |blocking_clock_gate | 0| 0|Passed|Blocking clock gate +5 |internal_async | 0| 0|Passed|Internal Async. Set/Reset control +6 |constant_active_async| 0| 0|Passed|Constant active Async. Set/Reset signal +7 |non_test_PI | 0| 0|Passed|Unconstrained PI driving Async/ Set/Reset +8 |async_clock_conflict | 0| 0|Passed|Async. Set/Reset signal and Clock conflict +9 |parallel_scan_clock | 0| 0|Passed|Clock pin of unsupported parallel-scan flop +-----+---------------------+------+--------+------+------------------------------------------- +Design has 0 DFT violation(s) +finished check_dft at 00:00:23(cpu)/0:00:22(wall) 368MB(vsz)/822MB(peak) + Configuring 4 scan chain(s) + Configuring DEFAULT DFT partition + Enabling physical aware scan chains + Configuring 4 scan chain(s) for 1024 scan instance(s) in 1 test clock domain(s) + Domain clk_25mhz has 1024 flop(s) (1024 rise, 0 fall), 4 chain(s) (4,0) + Assigning chain scanChain_1 to domain clk_25mhz (edge: rise) (capacity: 256) + Assigning chain scanChain_2 to domain clk_25mhz (edge: rise) (capacity: 256) + Assigning chain scanChain_3 to domain clk_25mhz (edge: rise) (capacity: 256) + Assigning chain scanChain_4 to domain clk_25mhz (edge: rise) (capacity: 256) +info: writing Sdc file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.02/Scan_0/oasys.sdc' for design 'cpu' [WRITE-104] +info: Parameter 'tessentScandefFilePath' set to '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.02/Scan_0/cpu.scandef' [PARAM-104] + +************************************************************************************************************************************************************************************** + TESSENT EXECUTION BEGINS + Invoking Tessent Executable : /applications/SiemensEDA/siemenseda2023/tessent_2023.4-p1/bin/tessent + DoFile : /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.02/Scan_0/scan.do +************************************************************************************************************************************************************************************** + +/applications/SiemensEDA/siemenseda2023/tessent_2023.4-p1/bin/tessent -shell -dofile /tmp/oasys.2567737/.tmpTessentFile -log_file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.02/Scan_0/scan.log -replace +// Tessent Shell 2023.4-p1 Mon Feb 19 16:22:02 GMT 2024 +// Unpublished work. Copyright 2024 Siemens +// +// This material contains trade secrets or otherwise confidential +// information owned by Siemens Industry Software Inc. or its affiliates +// (collectively, "SISW"), or its licensors. Access to and use of this +// information is strictly limited as set forth in the Customer's +// applicable agreements with SISW. +// +// Siemens software executing under x86-64 Linux on Fri May 29 09:12:34 CEST 2026. +// 64 bit version +// Host: efiapps0.ads1.fh-nuernberg.de (12 x 3.5 GHz, 48014 MB RAM, 24575 MB Swap) +// +// command: if {[catch {source /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.02/Scan_0/scan.do} msg]} { +// puts "$msg" +// puts "TESSENT_ER_ORTL" } +// sub-command: set_context dft -scan -no_rtl -design_id Scan_0 +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_low_temp_ccs.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_low_temp_ccs.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_low_temp_ccs.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_low_temp_ccs.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_low_temp_ccs.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_low_temp_ccs.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/PLL.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/PLL.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/PLL.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/IO.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/IO.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/IO.fslib +// sub-command: set_module_matching_options -suffix_pattern_list {[_]+[0-9]+[_]+[0-9]+} -regexp -append +// sub-command: set_module_matching_options -suffix_pattern_list {[_]+[A-Z]+} -regexp -append +// sub-command: set_module_matching_options -suffix_pattern_list {[_]+[0-9]+[_]+[0-9]+[_]+[A-Z]+} -regexp -append +// sub-command: read_verilog /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.02/Scan_0/oasys_netlist.v +// sub-command: set_tsdb_output_directory /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.02/tsdb_outdir +// sub-command: read_sdc /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.02/Scan_0/oasys.sdc +// Command 'read_sdc' requires an elaborated design. Automatically elaborating the design ... +// Note: 640 duplicate cell library models were read. The last model read of the same name was kept. +// To see detailed messages per duplicate model, issue 'set_cell_library_options -report_duplicate_models on' +// before issuing 'read_cell_library'. +// Warning: 1 cell library model contained 2 floating model outputs. +// To see detailed messages per model, issue 'set_cell_library_options -report_floating_nets on' +// before issuing 'read_cell_library'. +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X1' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X2' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X4' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X8' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X1_HVT' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X2_HVT' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X4_HVT' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X8_HVT' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X1_SVT' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X2_SVT' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X4_SVT' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X8_SVT' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X1_LVT' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X2_LVT' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X4_LVT' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X8_LVT' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' +// Note: Top design is 'cpu'. +// Warning: Undefined modules were found. +// Before using "set_system_mode" or "create_flat_model", you must either define +// the missing modules using "read_verilog" and/or "read_cell_library", or use the +// following command to treat them as black boxes: + add_black_boxes -modules { \ + MemGen_16_10 \ + } +// You can also use "add_black_boxes -auto" to black box all undefined modules but +// it is recommended that you do not add this command to your dofile. Doing so may +// unintentionally black-box new undefined modules in future runs. +// Warning: 32 cases: Unused net in DFT library model +// Warning: 110 cases: Undriven net in netlist module +// Warning: 1 case: Floating input on instance in netlist +// Warning: 47 cases: Net in netlist not connected +// Note: Issue set_current_design with the -show_elaboration_warnings option to see more details about previous warnings +// Design elaboration successful. +// Reading SDC file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.02/Scan_0/oasys.sdc ... +// Finished reading SDC file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.02/Scan_0/oasys.sdc. +// Read SDC summary: 1 false path, 0 multi-cycle paths, 0 erroneous paths +// 0 disable timings, 0 case analysis, 0 clock groups +// sub-command: set_current_design cpu -show_elaboration_warnings +// Warning: Undefined modules were found. +// Before using "set_system_mode" or "create_flat_model", you must either define +// the missing modules using "read_verilog" and/or "read_cell_library", or use the +// following command to treat them as black boxes: + add_black_boxes -modules { \ + MemGen_16_10 \ + } +// You can also use "add_black_boxes -auto" to black box all undefined modules but +// it is recommended that you do not add this command to your dofile. Doing so may +// unintentionally black-box new undefined modules in future runs. +// Warning: Net 'SO_1' in module 'cpu' is not driven +// Warning: Net 'SO_2' in module 'cpu' is not driven +// Warning: Net 'SO_3' in module 'cpu' is not driven +// Warning: Net 'SO_4' in module 'cpu' is not driven +// Warning: Net 'DAddr[31]' in module 'cpu' has no pins +// Warning: Net 'DAddr[30]' in module 'cpu' has no pins +// Warning: Net 'DAddr[29]' in module 'cpu' has no pins +// Warning: Net 'DAddr[28]' in module 'cpu' has no pins +// Warning: Net 'DAddr[27]' in module 'cpu' has no pins +// Warning: Net 'DAddr[26]' in module 'cpu' has no pins +// Warning: Net 'DAddr[25]' in module 'cpu' has no pins +// Warning: Net 'DAddr[24]' in module 'cpu' has no pins +// Warning: Net 'DAddr[23]' in module 'cpu' has no pins +// Warning: Net 'DAddr[22]' in module 'cpu' has no pins +// Warning: Net 'DAddr[21]' in module 'cpu' has no pins +// Warning: Net 'DAddr[20]' in module 'cpu' has no pins +// Warning: Net 'DAddr[19]' in module 'cpu' has no pins +// Warning: Net 'DAddr[18]' in module 'cpu' has no pins +// Warning: Net 'DAddr[17]' in module 'cpu' has no pins +// Warning: Net 'DAddr[16]' in module 'cpu' has no pins +// Warning: Net 'DAddr[15]' in module 'cpu' has no pins +// Warning: Net 'DAddr[14]' in module 'cpu' has no pins +// Warning: Net 'DAddr[13]' in module 'cpu' has no pins +// Warning: Net 'NextPC[31]' in module 'cpu' has no pins +// Warning: Net 'NextPC[30]' in module 'cpu' has no pins +// Warning: Net 'NextPC[29]' in module 'cpu' has no pins +// Warning: Net 'NextPC[28]' in module 'cpu' has no pins +// Warning: Net 'NextPC[27]' in module 'cpu' has no pins +// Warning: Net 'NextPC[26]' in module 'cpu' has no pins +// Warning: Net 'NextPC[25]' in module 'cpu' has no pins +// Warning: Net 'NextPC[24]' in module 'cpu' has no pins +// Warning: Net 'NextPC[23]' in module 'cpu' has no pins +// Warning: Net 'NextPC[22]' in module 'cpu' has no pins +// Warning: Net 'NextPC[21]' in module 'cpu' has no pins +// Warning: Net 'NextPC[20]' in module 'cpu' has no pins +// Warning: Net 'NextPC[19]' in module 'cpu' has no pins +// Warning: Net 'NextPC[18]' in module 'cpu' has no pins +// Warning: Net 'NextPC[17]' in module 'cpu' has no pins +// Warning: Net 'NextPC[16]' in module 'cpu' has no pins +// Warning: Net 'NextPC[15]' in module 'cpu' has no pins +// Warning: Net 'NextPC[14]' in module 'cpu' has no pins +// Warning: Net 'NextPC[13]' in module 'cpu' has no pins +// Warning: Net 'NextPC[7]' in module 'cpu' has no pins +// Warning: Net 'NextPC[6]' in module 'cpu' has no pins +// Warning: Net 'NextPC[5]' in module 'cpu' has no pins +// Warning: Net 'NextPC[4]' in module 'cpu' has no pins +// Warning: Net 'NextPC[3]' in module 'cpu' has no pins +// Warning: Net 'NextPC[2]' in module 'cpu' has no pins +// Warning: Net 'NextPC[1]' in module 'cpu' has no pins +// Warning: Net 'NextPC[0]' in module 'cpu' has no pins +// Warning: Net 'uc_0' in module 'cpu' is not driven +// Warning: Net 'uc_1' in module 'cpu' is not driven +// Warning: Net 'uc_2' in module 'cpu' is not driven +// Warning: Net 'uc_3' in module 'cpu' is not driven +// Warning: Net 'uc_4' in module 'cpu' is not driven +// Warning: Net 'uc_5' in module 'cpu' is not driven +// Warning: Net 'uc_6' in module 'cpu' is not driven +// Warning: Net 'uc_7' in module 'cpu' is not driven +// Warning: Net 'uc_8' in module 'cpu' is not driven +// Warning: Net 'uc_9' in module 'cpu' is not driven +// Warning: Net 'uc_10' in module 'cpu' is not driven +// Warning: Net 'uc_11' in module 'cpu' is not driven +// Warning: Net 'uc_12' in module 'cpu' is not driven +// Warning: Net 'uc_13' in module 'cpu' is not driven +// Warning: Net 'uc_14' in module 'cpu' is not driven +// Warning: Net 'uc_15' in module 'cpu' is not driven +// Warning: Net 'uc_16' in module 'cpu' is not driven +// Warning: Net 'uc_17' in module 'cpu' is not driven +// Warning: Net 'uc_18' in module 'cpu' is not driven +// Warning: Net 'uc_19' in module 'cpu' is not driven +// Warning: Net 'uc_20' in module 'cpu' is not driven +// Warning: Net 'uc_21' in module 'cpu' is not driven +// Warning: Net 'uc_22' in module 'cpu' is not driven +// Warning: Net 'uc_23' in module 'cpu' is not driven +// Warning: Net 'uc_24' in module 'cpu' is not driven +// Warning: Net 'uc_25' in module 'cpu' is not driven +// Warning: Net 'uc_26' in module 'cpu' is not driven +// Warning: Net 'uc_27' in module 'cpu' is not driven +// Warning: Net 'uc_28' in module 'cpu' is not driven +// Warning: Net 'uc_29' in module 'cpu' is not driven +// Warning: Net 'uc_30' in module 'cpu' is not driven +// Warning: Net 'uc_31' in module 'cpu' is not driven +// Warning: Net 'uc_32' in module 'cpu' is not driven +// Warning: Net 'uc_33' in module 'cpu' is not driven +// Warning: Net 'uc_34' in module 'cpu' is not driven +// Warning: Net 'uc_35' in module 'cpu' is not driven +// Warning: Net 'uc_36' in module 'cpu' is not driven +// Warning: Net 'uc_37' in module 'cpu' is not driven +// Warning: Net 'uc_38' in module 'cpu' is not driven +// Warning: Net 'uc_39' in module 'cpu' is not driven +// Warning: Floating input 'chip_en' at instance 'RAM' in module 'main_mem' +// Warning: Net 'mem_sel[1]' in module 'MemGen_32_11' has no pins +// Warning: Net 'DAddr[31]' in module 'decoder' is not driven +// Warning: Net 'DAddr[30]' in module 'decoder' is not driven +// Warning: Net 'DAddr[29]' in module 'decoder' is not driven +// Warning: Net 'DAddr[28]' in module 'decoder' is not driven +// Warning: Net 'DAddr[27]' in module 'decoder' is not driven +// Warning: Net 'DAddr[26]' in module 'decoder' is not driven +// Warning: Net 'DAddr[25]' in module 'decoder' is not driven +// Warning: Net 'DAddr[24]' in module 'decoder' is not driven +// Warning: Net 'DAddr[23]' in module 'decoder' is not driven +// Warning: Net 'DAddr[22]' in module 'decoder' is not driven +// Warning: Net 'DAddr[21]' in module 'decoder' is not driven +// Warning: Net 'DAddr[20]' in module 'decoder' is not driven +// Warning: Net 'DAddr[19]' in module 'decoder' is not driven +// Warning: Net 'DAddr[18]' in module 'decoder' is not driven +// Warning: Net 'DAddr[17]' in module 'decoder' is not driven +// Warning: Net 'DAddr[16]' in module 'decoder' is not driven +// Warning: Net 'DAddr[15]' in module 'decoder' is not driven +// Warning: Net 'DAddr[14]' in module 'decoder' is not driven +// Warning: Net 'DAddr[13]' in module 'decoder' is not driven +// Warning: Net 'WData[31]' in module 'decoder' is not driven +// Warning: Net 'WData[30]' in module 'decoder' is not driven +// Warning: Net 'WData[29]' in module 'decoder' is not driven +// Warning: Net 'WData[28]' in module 'decoder' is not driven +// Warning: Net 'WData[27]' in module 'decoder' is not driven +// Warning: Net 'WData[26]' in module 'decoder' is not driven +// Warning: Net 'WData[25]' in module 'decoder' is not driven +// Warning: Net 'WData[24]' in module 'decoder' is not driven +// Warning: Net 'WData[23]' in module 'decoder' is not driven +// Warning: Net 'WData[22]' in module 'decoder' is not driven +// Warning: Net 'WData[21]' in module 'decoder' is not driven +// Warning: Net 'WData[20]' in module 'decoder' is not driven +// Warning: Net 'WData[19]' in module 'decoder' is not driven +// Warning: Net 'WData[18]' in module 'decoder' is not driven +// Warning: Net 'WData[17]' in module 'decoder' is not driven +// Warning: Net 'WData[16]' in module 'decoder' is not driven +// Warning: Net 'WData[15]' in module 'decoder' is not driven +// Warning: Net 'WData[14]' in module 'decoder' is not driven +// Warning: Net 'WData[13]' in module 'decoder' is not driven +// Warning: Net 'WData[12]' in module 'decoder' is not driven +// Warning: Net 'WData[11]' in module 'decoder' is not driven +// Warning: Net 'WData[10]' in module 'decoder' is not driven +// Warning: Net 'WData[9]' in module 'decoder' is not driven +// Warning: Net 'WData[8]' in module 'decoder' is not driven +// Warning: Net 'WData[7]' in module 'decoder' is not driven +// Warning: Net 'WData[6]' in module 'decoder' is not driven +// Warning: Net 'WData[5]' in module 'decoder' is not driven +// Warning: Net 'WData[4]' in module 'decoder' is not driven +// Warning: Net 'WData[3]' in module 'decoder' is not driven +// Warning: Net 'WData[2]' in module 'decoder' is not driven +// Warning: Net 'WData[1]' in module 'decoder' is not driven +// Warning: Net 'WData[0]' in module 'decoder' is not driven +// Warning: Net 'Rs1[4]' in module 'decoder' is not driven +// Warning: Net 'Rs1[3]' in module 'decoder' is not driven +// Warning: Net 'Rs1[2]' in module 'decoder' is not driven +// Warning: Net 'Rs1[1]' in module 'decoder' is not driven +// Warning: Net 'Rs1[0]' in module 'decoder' is not driven +// Warning: Net 'Rs2[4]' in module 'decoder' is not driven +// Warning: Net 'Rs2[3]' in module 'decoder' is not driven +// Warning: Net 'Rs2[2]' in module 'decoder' is not driven +// Warning: Net 'Rs2[1]' in module 'decoder' is not driven +// Warning: Net 'Rs2[0]' in module 'decoder' is not driven +// Warning: Net 'Rd[4]' in module 'decoder' is not driven +// Warning: Net 'Rd[3]' in module 'decoder' is not driven +// Warning: Net 'Rd[2]' in module 'decoder' is not driven +// Warning: Net 'Rd[1]' in module 'decoder' is not driven +// Warning: Net 'Rd[0]' in module 'decoder' is not driven +// sub-command: set_design_level physical_block +// sub-command: set_shift_register_identification off +// sub-command: add_nonscan_instances -instances "{/theMem/\IRData_reg[31] } {/theMem/\IRData_reg[30] } {/theMem/\IRData_reg[29] } {/theMem/\IRData_reg[28] } {/theMem/\IRData_reg[27] } {/theMem/\IRData_reg[26] } {/theMem/\IRData_reg[25] } {/theMem/\IRData_reg[24] } {/theMem/\IRData_reg[23] } {/theMem/\IRData_reg[22] } {/theMem/\IRData_reg[21] } {/theMem/\IRData_reg[20] } {/theMem/\IRData_reg[19] } {/theMem/\IRData_reg[18] } {/theMem/\IRData_reg[17] } {/theMem/\IRData_reg[16] } {/theMem/\IRData_reg[15] } {/theMem/\IRData_reg[14] } {/theMem/\IRData_reg[13] } {/theMem/\IRData_reg[12] } {/theMem/\IRData_reg[11] } {/theMem/\IRData_reg[10] } {/theMem/\IRData_reg[9] } {/theMem/\IRData_reg[8] } {/theMem/\IRData_reg[7] } {/theMem/\IRData_reg[6] } {/theMem/\IRData_reg[5] } {/theMem/\IRData_reg[4] } {/theMem/\IRData_reg[3] } {/theMem/\IRData_reg[2] } {/theMem/\IRData_reg[1] } {/theMem/\IRData_reg[0] } {/theMem/\mem_addr_reg[10] } {/theMem/\mem_addr_reg[9] } {/theMem/\mem_addr_reg[8] } {/theMem/\mem_addr_reg[7] } {/theMem/\mem_addr_reg[6] } {/theMem/\mem_addr_reg[5] } {/theMem/\mem_addr_reg[4] } {/theMem/\mem_addr_reg[3] } {/theMem/\mem_addr_reg[2] } {/theMem/\mem_addr_reg[1] } {/theMem/\mem_addr_reg[0] } {/theMem/\drTmp_reg[31] } {/theMem/\drTmp_reg[30] } {/theMem/\drTmp_reg[29] } {/theMem/\drTmp_reg[28] } {/theMem/\drTmp_reg[27] } {/theMem/\drTmp_reg[26] } {/theMem/\drTmp_reg[25] } {/theMem/\drTmp_reg[24] } {/theMem/\drTmp_reg[23] } {/theMem/\drTmp_reg[22] } {/theMem/\drTmp_reg[21] } {/theMem/\drTmp_reg[20] } {/theMem/\drTmp_reg[19] } {/theMem/\drTmp_reg[18] } {/theMem/\drTmp_reg[17] } {/theMem/\drTmp_reg[16] } {/theMem/\drTmp_reg[15] } {/theMem/\drTmp_reg[14] } {/theMem/\drTmp_reg[13] } {/theMem/\drTmp_reg[12] } {/theMem/\drTmp_reg[11] } {/theMem/\drTmp_reg[10] } {/theMem/\drTmp_reg[9] } {/theMem/\drTmp_reg[8] } {/theMem/\drTmp_reg[7] } {/theMem/\drTmp_reg[6] } {/theMem/\drTmp_reg[5] } {/theMem/\drTmp_reg[4] } {/theMem/\drTmp_reg[3] } {/theMem/\drTmp_reg[2] } {/theMem/\drTmp_reg[1] } {/theMem/\drTmp_reg[0] } {/theMem/\mem_wdata_reg[31] } {/theMem/\mem_wdata_reg[30] } {/theMem/\mem_wdata_reg[29] } {/theMem/\mem_wdata_reg[28] } {/theMem/\mem_wdata_reg[27] } {/theMem/\mem_wdata_reg[26] } {/theMem/\mem_wdata_reg[25] } {/theMem/\mem_wdata_reg[24] } {/theMem/\mem_wdata_reg[23] } {/theMem/\mem_wdata_reg[22] } {/theMem/\mem_wdata_reg[21] } {/theMem/\mem_wdata_reg[20] } {/theMem/\mem_wdata_reg[19] } {/theMem/\mem_wdata_reg[18] } {/theMem/\mem_wdata_reg[17] } {/theMem/\mem_wdata_reg[16] } {/theMem/\mem_wdata_reg[15] } {/theMem/\mem_wdata_reg[14] } {/theMem/\mem_wdata_reg[13] } {/theMem/\mem_wdata_reg[12] } {/theMem/\mem_wdata_reg[11] } {/theMem/\mem_wdata_reg[10] } {/theMem/\mem_wdata_reg[9] } {/theMem/\mem_wdata_reg[8] } {/theMem/\mem_wdata_reg[7] } {/theMem/\mem_wdata_reg[6] } {/theMem/\mem_wdata_reg[5] } {/theMem/\mem_wdata_reg[4] } {/theMem/\mem_wdata_reg[3] } {/theMem/\mem_wdata_reg[2] } {/theMem/\mem_wdata_reg[1] } {/theMem/\mem_wdata_reg[0] } " +// sub-command: add_clocks 0 " clk_25mhz " +// sub-command: set_scan_enable scan_en -active high +// sub-command: add_input_constraints btn[0] -C1 +// sub-command: set_scan_enable scan_en -active high -cluster_name scanChain_1 +// sub-command: set_scan_enable scan_en -active high -cluster_name scanChain_2 +// sub-command: set_scan_enable scan_en -active high -cluster_name scanChain_3 +// sub-command: set_scan_enable scan_en -active high -cluster_name scanChain_4 +// sub-command: add_black_boxes -modules " MemGen_16_10 " +// sub-command: set_scan_insertion_options -single_clock_edge_chains on -si_port_format oas_ts_si[%d] -so_port_format oas_ts_so[%d] +// sub-command: set_system_mode analysis +// Warning: Rule FN1 violation occurs 157 times +// Warning: Rule FP13 violation occurs 1 times +// Flattening process completed, cell instances=4379, gates=18234, PIs=13, POs=12, CPU time=0.09 sec. +// --------------------------------------------------------------------------- +// Begin circuit learning analyses. +// -------------------------------- +// Learning completed, CPU time=0.01 sec. +// --------------------------------------------------------------------------- +// Begin scan chain identification process, memory elements = 1194, +// sequential library cells = 1194. +// --------------------------------------------------------------------------- +// Warning: Model 'DLH_X1_LVT' has no muxscan scan equivalent and is treated as nonscan model +// ------------------------------------------------------------------------------ +// 170 sequential library cells are treated as non-scan. +// ------------------------------------------------------------------------------ +// 63 sequential library cells missing mux-scan equivalent. +// 107 sequential library cells defined non-scan. +// --------------------------------------------------------------------------- +// Begin scannability rules checking for 1024 sequential library cells. +// --------------------------------------------------------------------------- +// 1024 sequential library cells identified as scannable. +// --------------------------------------------------------------------------- +// Begin transparent latch checking for 63 latches. +// --------------------------------------------------------------------------- +// Warning: 32 latches not transparent due to uncontrollable. (D6) +// Number transparent latches = 31. +// --------------------------------------------------------------------------- +// Begin scan clock rules checking. +// --------------------------------------------------------------------------- +// 1 scan clock/set/reset lines have been identified. +// All scan clocks successfully passed off-state check. +// 1131 sequential cells passed clock stability checking. +// There were 43 clock rule C3 fails (clock may capture data affected by its captured data). +// Note: Trailing edge triggered device can capture data affected by leading edge. +// --------------------------------------------------------------------------- +// 170 non-scan memory elements are identified. +// --------------------------------------------------------------------------- +// 32 non-scan memory elements are identified as TIE-X. (D5) +// 107 non-scan memory elements are identified as INIT-X. (D5) +// 31 non-scan memory elements are identified as TLA. (D5) +// --------------------------------------------------------------------------- +// Number of targeted sequential library cells = 1024 +// Warning: The tool may require a shift-capture clock during insertion, +// but no 'shift_capture_clock' DFT signal was identified +// and no TCLK source was specified using the command 'set_scan_signals -tclk'. +// Note: The system clock 'clk_25mhz' will be used as the shift-capture clock, if needed. +// sub-command: report_drc_rules +C3: #fails=43 handling=note (clock may capture data affected by its captured data) +D5: #fails=170 handling=warning (non-scan memory element) +D6: #fails=32 handling=warning (non-transparent non-scan latches) +// sub-command: create_scan_chain_family scanChain_1 -include_elements "{/\thePC_CurrentPC_reg[0] } {/\thePC_CurrentPC_reg[10] } {/\thePC_CurrentPC_reg[11] } {/\thePC_CurrentPC_reg[12] } {/\thePC_CurrentPC_reg[13] } {/\thePC_CurrentPC_reg[14] } {/\thePC_CurrentPC_reg[15] } {/\thePC_CurrentPC_reg[16] } {/\thePC_CurrentPC_reg[17] } {/\thePC_CurrentPC_reg[18] } {/\thePC_CurrentPC_reg[19] } {/\thePC_CurrentPC_reg[1] } {/\thePC_CurrentPC_reg[20] } {/\thePC_CurrentPC_reg[21] } {/\thePC_CurrentPC_reg[22] } {/\thePC_CurrentPC_reg[23] } {/\thePC_CurrentPC_reg[24] } {/\thePC_CurrentPC_reg[25] } {/\thePC_CurrentPC_reg[26] } {/\thePC_CurrentPC_reg[27] } {/\thePC_CurrentPC_reg[28] } {/\thePC_CurrentPC_reg[29] } {/\thePC_CurrentPC_reg[2] } {/\thePC_CurrentPC_reg[30] } {/\thePC_CurrentPC_reg[31] } {/\thePC_CurrentPC_reg[3] } {/\thePC_CurrentPC_reg[4] } {/\thePC_CurrentPC_reg[5] } {/\thePC_CurrentPC_reg[6] } {/\thePC_CurrentPC_reg[7] } {/\thePC_CurrentPC_reg[8] } {/\thePC_CurrentPC_reg[9] } {/theRegisters/\registers_reg[10][0] } {/theRegisters/\registers_reg[10][10] } {/theRegisters/\registers_reg[10][11] } {/theRegisters/\registers_reg[10][12] } {/theRegisters/\registers_reg[10][13] } {/theRegisters/\registers_reg[10][14] } {/theRegisters/\registers_reg[10][15] } {/theRegisters/\registers_reg[10][16] } {/theRegisters/\registers_reg[10][17] } {/theRegisters/\registers_reg[10][18] } {/theRegisters/\registers_reg[10][19] } {/theRegisters/\registers_reg[10][1] } {/theRegisters/\registers_reg[10][20] } {/theRegisters/\registers_reg[10][21] } {/theRegisters/\registers_reg[10][22] } {/theRegisters/\registers_reg[10][23] } {/theRegisters/\registers_reg[10][24] } {/theRegisters/\registers_reg[10][25] } {/theRegisters/\registers_reg[10][26] } {/theRegisters/\registers_reg[10][27] } {/theRegisters/\registers_reg[10][28] } {/theRegisters/\registers_reg[10][29] } {/theRegisters/\registers_reg[10][2] } {/theRegisters/\registers_reg[10][30] } {/theRegisters/\registers_reg[10][31] } {/theRegisters/\registers_reg[10][3] } {/theRegisters/\registers_reg[10][4] } {/theRegisters/\registers_reg[10][5] } {/theRegisters/\registers_reg[10][6] } {/theRegisters/\registers_reg[10][7] } {/theRegisters/\registers_reg[10][8] } {/theRegisters/\registers_reg[10][9] } {/theRegisters/\registers_reg[11][0] } {/theRegisters/\registers_reg[11][10] } {/theRegisters/\registers_reg[11][11] } {/theRegisters/\registers_reg[11][12] } {/theRegisters/\registers_reg[11][13] } {/theRegisters/\registers_reg[11][14] } {/theRegisters/\registers_reg[11][15] } {/theRegisters/\registers_reg[11][16] } {/theRegisters/\registers_reg[11][17] } {/theRegisters/\registers_reg[11][18] } {/theRegisters/\registers_reg[11][19] } {/theRegisters/\registers_reg[11][1] } {/theRegisters/\registers_reg[11][20] } {/theRegisters/\registers_reg[11][21] } {/theRegisters/\registers_reg[11][22] } {/theRegisters/\registers_reg[11][23] } {/theRegisters/\registers_reg[11][24] } {/theRegisters/\registers_reg[11][25] } {/theRegisters/\registers_reg[11][26] } {/theRegisters/\registers_reg[11][27] } {/theRegisters/\registers_reg[11][28] } {/theRegisters/\registers_reg[11][29] } {/theRegisters/\registers_reg[11][2] } {/theRegisters/\registers_reg[11][30] } {/theRegisters/\registers_reg[11][31] } {/theRegisters/\registers_reg[11][3] } {/theRegisters/\registers_reg[11][4] } {/theRegisters/\registers_reg[11][5] } {/theRegisters/\registers_reg[11][6] } {/theRegisters/\registers_reg[11][7] } {/theRegisters/\registers_reg[11][8] } {/theRegisters/\registers_reg[11][9] } {/theRegisters/\registers_reg[12][0] } {/theRegisters/\registers_reg[12][10] } {/theRegisters/\registers_reg[12][11] } {/theRegisters/\registers_reg[12][12] } {/theRegisters/\registers_reg[12][13] } {/theRegisters/\registers_reg[12][14] } {/theRegisters/\registers_reg[12][15] } {/theRegisters/\registers_reg[12][16] } {/theRegisters/\registers_reg[12][17] } {/theRegisters/\registers_reg[12][18] } {/theRegisters/\registers_reg[12][19] } {/theRegisters/\registers_reg[12][1] } {/theRegisters/\registers_reg[12][20] } {/theRegisters/\registers_reg[12][21] } {/theRegisters/\registers_reg[12][22] } {/theRegisters/\registers_reg[12][23] } {/theRegisters/\registers_reg[12][24] } {/theRegisters/\registers_reg[12][25] } {/theRegisters/\registers_reg[12][26] } {/theRegisters/\registers_reg[12][27] } {/theRegisters/\registers_reg[12][28] } {/theRegisters/\registers_reg[12][29] } {/theRegisters/\registers_reg[12][2] } {/theRegisters/\registers_reg[12][30] } {/theRegisters/\registers_reg[12][31] } {/theRegisters/\registers_reg[12][3] } {/theRegisters/\registers_reg[12][4] } {/theRegisters/\registers_reg[12][5] } {/theRegisters/\registers_reg[12][6] } {/theRegisters/\registers_reg[12][7] } {/theRegisters/\registers_reg[12][8] } {/theRegisters/\registers_reg[12][9] } {/theRegisters/\registers_reg[13][0] } {/theRegisters/\registers_reg[13][10] } {/theRegisters/\registers_reg[13][11] } {/theRegisters/\registers_reg[13][12] } {/theRegisters/\registers_reg[13][13] } {/theRegisters/\registers_reg[13][14] } {/theRegisters/\registers_reg[13][15] } {/theRegisters/\registers_reg[13][16] } {/theRegisters/\registers_reg[13][17] } {/theRegisters/\registers_reg[13][18] } {/theRegisters/\registers_reg[13][19] } {/theRegisters/\registers_reg[13][1] } {/theRegisters/\registers_reg[13][20] } {/theRegisters/\registers_reg[13][21] } {/theRegisters/\registers_reg[13][22] } {/theRegisters/\registers_reg[13][23] } {/theRegisters/\registers_reg[13][24] } {/theRegisters/\registers_reg[13][25] } {/theRegisters/\registers_reg[13][26] } {/theRegisters/\registers_reg[13][27] } {/theRegisters/\registers_reg[13][28] } {/theRegisters/\registers_reg[13][29] } {/theRegisters/\registers_reg[13][2] } {/theRegisters/\registers_reg[13][30] } {/theRegisters/\registers_reg[13][31] } {/theRegisters/\registers_reg[13][3] } {/theRegisters/\registers_reg[13][4] } {/theRegisters/\registers_reg[13][5] } {/theRegisters/\registers_reg[13][6] } {/theRegisters/\registers_reg[13][7] } {/theRegisters/\registers_reg[13][8] } {/theRegisters/\registers_reg[13][9] } {/theRegisters/\registers_reg[14][0] } {/theRegisters/\registers_reg[14][10] } {/theRegisters/\registers_reg[14][11] } {/theRegisters/\registers_reg[14][12] } {/theRegisters/\registers_reg[14][13] } {/theRegisters/\registers_reg[14][14] } {/theRegisters/\registers_reg[14][15] } {/theRegisters/\registers_reg[14][16] } {/theRegisters/\registers_reg[14][17] } {/theRegisters/\registers_reg[14][18] } {/theRegisters/\registers_reg[14][19] } {/theRegisters/\registers_reg[14][1] } {/theRegisters/\registers_reg[14][20] } {/theRegisters/\registers_reg[14][21] } {/theRegisters/\registers_reg[14][22] } {/theRegisters/\registers_reg[14][23] } {/theRegisters/\registers_reg[14][24] } {/theRegisters/\registers_reg[14][25] } {/theRegisters/\registers_reg[14][26] } {/theRegisters/\registers_reg[14][27] } {/theRegisters/\registers_reg[14][28] } {/theRegisters/\registers_reg[14][29] } {/theRegisters/\registers_reg[14][2] } {/theRegisters/\registers_reg[14][30] } {/theRegisters/\registers_reg[14][31] } {/theRegisters/\registers_reg[14][3] } {/theRegisters/\registers_reg[14][4] } {/theRegisters/\registers_reg[14][5] } {/theRegisters/\registers_reg[14][6] } {/theRegisters/\registers_reg[14][7] } {/theRegisters/\registers_reg[14][8] } {/theRegisters/\registers_reg[14][9] } {/theRegisters/\registers_reg[15][0] } {/theRegisters/\registers_reg[15][10] } {/theRegisters/\registers_reg[15][11] } {/theRegisters/\registers_reg[15][12] } {/theRegisters/\registers_reg[15][13] } {/theRegisters/\registers_reg[15][14] } {/theRegisters/\registers_reg[15][15] } {/theRegisters/\registers_reg[15][16] } {/theRegisters/\registers_reg[15][17] } {/theRegisters/\registers_reg[15][18] } {/theRegisters/\registers_reg[15][19] } {/theRegisters/\registers_reg[15][1] } {/theRegisters/\registers_reg[15][20] } {/theRegisters/\registers_reg[15][21] } {/theRegisters/\registers_reg[15][22] } {/theRegisters/\registers_reg[15][23] } {/theRegisters/\registers_reg[15][24] } {/theRegisters/\registers_reg[15][25] } {/theRegisters/\registers_reg[15][26] } {/theRegisters/\registers_reg[15][27] } {/theRegisters/\registers_reg[15][28] } {/theRegisters/\registers_reg[15][29] } {/theRegisters/\registers_reg[15][2] } {/theRegisters/\registers_reg[15][30] } {/theRegisters/\registers_reg[15][31] } {/theRegisters/\registers_reg[15][3] } {/theRegisters/\registers_reg[15][4] } {/theRegisters/\registers_reg[15][5] } {/theRegisters/\registers_reg[15][6] } {/theRegisters/\registers_reg[15][7] } {/theRegisters/\registers_reg[15][8] } {/theRegisters/\registers_reg[15][9] } {/theRegisters/\registers_reg[16][0] } {/theRegisters/\registers_reg[16][10] } {/theRegisters/\registers_reg[16][11] } {/theRegisters/\registers_reg[16][12] } {/theRegisters/\registers_reg[16][13] } {/theRegisters/\registers_reg[16][14] } {/theRegisters/\registers_reg[16][15] } {/theRegisters/\registers_reg[16][16] } {/theRegisters/\registers_reg[16][17] } {/theRegisters/\registers_reg[16][18] } {/theRegisters/\registers_reg[16][19] } {/theRegisters/\registers_reg[16][1] } {/theRegisters/\registers_reg[16][20] } {/theRegisters/\registers_reg[16][21] } {/theRegisters/\registers_reg[16][22] } {/theRegisters/\registers_reg[16][23] } {/theRegisters/\registers_reg[16][24] } {/theRegisters/\registers_reg[16][25] } {/theRegisters/\registers_reg[16][26] } {/theRegisters/\registers_reg[16][27] } {/theRegisters/\registers_reg[16][28] } {/theRegisters/\registers_reg[16][29] } {/theRegisters/\registers_reg[16][2] } {/theRegisters/\registers_reg[16][30] } {/theRegisters/\registers_reg[16][31] } {/theRegisters/\registers_reg[16][3] } {/theRegisters/\registers_reg[16][4] } {/theRegisters/\registers_reg[16][5] } {/theRegisters/\registers_reg[16][6] } {/theRegisters/\registers_reg[16][7] } {/theRegisters/\registers_reg[16][8] } {/theRegisters/\registers_reg[16][9] } " -si_connections "SI_1 " -so_connections "SO_1 " -chain_count 1 +// sub-command: create_scan_chain_family scanChain_2 -include_elements "{/theRegisters/\registers_reg[17][0] } {/theRegisters/\registers_reg[17][10] } {/theRegisters/\registers_reg[17][11] } {/theRegisters/\registers_reg[17][12] } {/theRegisters/\registers_reg[17][13] } {/theRegisters/\registers_reg[17][14] } {/theRegisters/\registers_reg[17][15] } {/theRegisters/\registers_reg[17][16] } {/theRegisters/\registers_reg[17][17] } {/theRegisters/\registers_reg[17][18] } {/theRegisters/\registers_reg[17][19] } {/theRegisters/\registers_reg[17][1] } {/theRegisters/\registers_reg[17][20] } {/theRegisters/\registers_reg[17][21] } {/theRegisters/\registers_reg[17][22] } {/theRegisters/\registers_reg[17][23] } {/theRegisters/\registers_reg[17][24] } {/theRegisters/\registers_reg[17][25] } {/theRegisters/\registers_reg[17][26] } {/theRegisters/\registers_reg[17][27] } {/theRegisters/\registers_reg[17][28] } {/theRegisters/\registers_reg[17][29] } {/theRegisters/\registers_reg[17][2] } {/theRegisters/\registers_reg[17][30] } {/theRegisters/\registers_reg[17][31] } {/theRegisters/\registers_reg[17][3] } {/theRegisters/\registers_reg[17][4] } {/theRegisters/\registers_reg[17][5] } {/theRegisters/\registers_reg[17][6] } {/theRegisters/\registers_reg[17][7] } {/theRegisters/\registers_reg[17][8] } {/theRegisters/\registers_reg[17][9] } {/theRegisters/\registers_reg[18][0] } {/theRegisters/\registers_reg[18][10] } {/theRegisters/\registers_reg[18][11] } {/theRegisters/\registers_reg[18][12] } {/theRegisters/\registers_reg[18][13] } {/theRegisters/\registers_reg[18][14] } {/theRegisters/\registers_reg[18][15] } {/theRegisters/\registers_reg[18][16] } {/theRegisters/\registers_reg[18][17] } {/theRegisters/\registers_reg[18][18] } {/theRegisters/\registers_reg[18][19] } {/theRegisters/\registers_reg[18][1] } {/theRegisters/\registers_reg[18][20] } {/theRegisters/\registers_reg[18][21] } {/theRegisters/\registers_reg[18][22] } {/theRegisters/\registers_reg[18][23] } {/theRegisters/\registers_reg[18][24] } {/theRegisters/\registers_reg[18][25] } {/theRegisters/\registers_reg[18][26] } {/theRegisters/\registers_reg[18][27] } {/theRegisters/\registers_reg[18][28] } {/theRegisters/\registers_reg[18][29] } {/theRegisters/\registers_reg[18][2] } {/theRegisters/\registers_reg[18][30] } {/theRegisters/\registers_reg[18][31] } {/theRegisters/\registers_reg[18][3] } {/theRegisters/\registers_reg[18][4] } {/theRegisters/\registers_reg[18][5] } {/theRegisters/\registers_reg[18][6] } {/theRegisters/\registers_reg[18][7] } {/theRegisters/\registers_reg[18][8] } {/theRegisters/\registers_reg[18][9] } {/theRegisters/\registers_reg[19][0] } {/theRegisters/\registers_reg[19][10] } {/theRegisters/\registers_reg[19][11] } {/theRegisters/\registers_reg[19][12] } {/theRegisters/\registers_reg[19][13] } {/theRegisters/\registers_reg[19][14] } {/theRegisters/\registers_reg[19][15] } {/theRegisters/\registers_reg[19][16] } {/theRegisters/\registers_reg[19][17] } {/theRegisters/\registers_reg[19][18] } {/theRegisters/\registers_reg[19][19] } {/theRegisters/\registers_reg[19][1] } {/theRegisters/\registers_reg[19][20] } {/theRegisters/\registers_reg[19][21] } {/theRegisters/\registers_reg[19][22] } {/theRegisters/\registers_reg[19][23] } {/theRegisters/\registers_reg[19][24] } {/theRegisters/\registers_reg[19][25] } {/theRegisters/\registers_reg[19][26] } {/theRegisters/\registers_reg[19][27] } {/theRegisters/\registers_reg[19][28] } {/theRegisters/\registers_reg[19][29] } {/theRegisters/\registers_reg[19][2] } {/theRegisters/\registers_reg[19][30] } {/theRegisters/\registers_reg[19][31] } {/theRegisters/\registers_reg[19][3] } {/theRegisters/\registers_reg[19][4] } {/theRegisters/\registers_reg[19][5] } {/theRegisters/\registers_reg[19][6] } {/theRegisters/\registers_reg[19][7] } {/theRegisters/\registers_reg[19][8] } {/theRegisters/\registers_reg[19][9] } {/theRegisters/\registers_reg[1][0] } {/theRegisters/\registers_reg[1][10] } {/theRegisters/\registers_reg[1][11] } {/theRegisters/\registers_reg[1][12] } {/theRegisters/\registers_reg[1][13] } {/theRegisters/\registers_reg[1][14] } {/theRegisters/\registers_reg[1][15] } {/theRegisters/\registers_reg[1][16] } {/theRegisters/\registers_reg[1][17] } {/theRegisters/\registers_reg[1][18] } {/theRegisters/\registers_reg[1][19] } {/theRegisters/\registers_reg[1][1] } {/theRegisters/\registers_reg[1][20] } {/theRegisters/\registers_reg[1][21] } {/theRegisters/\registers_reg[1][22] } {/theRegisters/\registers_reg[1][23] } {/theRegisters/\registers_reg[1][24] } {/theRegisters/\registers_reg[1][25] } {/theRegisters/\registers_reg[1][26] } {/theRegisters/\registers_reg[1][27] } {/theRegisters/\registers_reg[1][28] } {/theRegisters/\registers_reg[1][29] } {/theRegisters/\registers_reg[1][2] } {/theRegisters/\registers_reg[1][30] } {/theRegisters/\registers_reg[1][31] } {/theRegisters/\registers_reg[1][3] } {/theRegisters/\registers_reg[1][4] } {/theRegisters/\registers_reg[1][5] } {/theRegisters/\registers_reg[1][6] } {/theRegisters/\registers_reg[1][7] } {/theRegisters/\registers_reg[1][8] } {/theRegisters/\registers_reg[1][9] } {/theRegisters/\registers_reg[20][0] } {/theRegisters/\registers_reg[20][10] } {/theRegisters/\registers_reg[20][11] } {/theRegisters/\registers_reg[20][12] } {/theRegisters/\registers_reg[20][13] } {/theRegisters/\registers_reg[20][14] } {/theRegisters/\registers_reg[20][15] } {/theRegisters/\registers_reg[20][16] } {/theRegisters/\registers_reg[20][17] } {/theRegisters/\registers_reg[20][18] } {/theRegisters/\registers_reg[20][19] } {/theRegisters/\registers_reg[20][1] } {/theRegisters/\registers_reg[20][20] } {/theRegisters/\registers_reg[20][21] } {/theRegisters/\registers_reg[20][22] } {/theRegisters/\registers_reg[20][23] } {/theRegisters/\registers_reg[20][24] } {/theRegisters/\registers_reg[20][25] } {/theRegisters/\registers_reg[20][26] } {/theRegisters/\registers_reg[20][27] } {/theRegisters/\registers_reg[20][28] } {/theRegisters/\registers_reg[20][29] } {/theRegisters/\registers_reg[20][2] } {/theRegisters/\registers_reg[20][30] } {/theRegisters/\registers_reg[20][31] } {/theRegisters/\registers_reg[20][3] } {/theRegisters/\registers_reg[20][4] } {/theRegisters/\registers_reg[20][5] } {/theRegisters/\registers_reg[20][6] } {/theRegisters/\registers_reg[20][7] } {/theRegisters/\registers_reg[20][8] } {/theRegisters/\registers_reg[20][9] } {/theRegisters/\registers_reg[21][0] } {/theRegisters/\registers_reg[21][10] } {/theRegisters/\registers_reg[21][11] } {/theRegisters/\registers_reg[21][12] } {/theRegisters/\registers_reg[21][13] } {/theRegisters/\registers_reg[21][14] } {/theRegisters/\registers_reg[21][15] } {/theRegisters/\registers_reg[21][16] } {/theRegisters/\registers_reg[21][17] } {/theRegisters/\registers_reg[21][18] } {/theRegisters/\registers_reg[21][19] } {/theRegisters/\registers_reg[21][1] } {/theRegisters/\registers_reg[21][20] } {/theRegisters/\registers_reg[21][21] } {/theRegisters/\registers_reg[21][22] } {/theRegisters/\registers_reg[21][23] } {/theRegisters/\registers_reg[21][24] } {/theRegisters/\registers_reg[21][25] } {/theRegisters/\registers_reg[21][26] } {/theRegisters/\registers_reg[21][27] } {/theRegisters/\registers_reg[21][28] } {/theRegisters/\registers_reg[21][29] } {/theRegisters/\registers_reg[21][2] } {/theRegisters/\registers_reg[21][30] } {/theRegisters/\registers_reg[21][31] } {/theRegisters/\registers_reg[21][3] } {/theRegisters/\registers_reg[21][4] } {/theRegisters/\registers_reg[21][5] } {/theRegisters/\registers_reg[21][6] } {/theRegisters/\registers_reg[21][7] } {/theRegisters/\registers_reg[21][8] } {/theRegisters/\registers_reg[21][9] } {/theRegisters/\registers_reg[22][0] } {/theRegisters/\registers_reg[22][10] } {/theRegisters/\registers_reg[22][11] } {/theRegisters/\registers_reg[22][12] } {/theRegisters/\registers_reg[22][13] } {/theRegisters/\registers_reg[22][14] } {/theRegisters/\registers_reg[22][15] } {/theRegisters/\registers_reg[22][16] } {/theRegisters/\registers_reg[22][17] } {/theRegisters/\registers_reg[22][18] } {/theRegisters/\registers_reg[22][19] } {/theRegisters/\registers_reg[22][1] } {/theRegisters/\registers_reg[22][20] } {/theRegisters/\registers_reg[22][21] } {/theRegisters/\registers_reg[22][22] } {/theRegisters/\registers_reg[22][23] } {/theRegisters/\registers_reg[22][24] } {/theRegisters/\registers_reg[22][25] } {/theRegisters/\registers_reg[22][26] } {/theRegisters/\registers_reg[22][27] } {/theRegisters/\registers_reg[22][28] } {/theRegisters/\registers_reg[22][29] } {/theRegisters/\registers_reg[22][2] } {/theRegisters/\registers_reg[22][30] } {/theRegisters/\registers_reg[22][31] } {/theRegisters/\registers_reg[22][3] } {/theRegisters/\registers_reg[22][4] } {/theRegisters/\registers_reg[22][5] } {/theRegisters/\registers_reg[22][6] } {/theRegisters/\registers_reg[22][7] } {/theRegisters/\registers_reg[22][8] } {/theRegisters/\registers_reg[22][9] } {/theRegisters/\registers_reg[23][0] } {/theRegisters/\registers_reg[23][10] } {/theRegisters/\registers_reg[23][11] } {/theRegisters/\registers_reg[23][12] } {/theRegisters/\registers_reg[23][13] } {/theRegisters/\registers_reg[23][14] } {/theRegisters/\registers_reg[23][15] } {/theRegisters/\registers_reg[23][16] } {/theRegisters/\registers_reg[23][17] } {/theRegisters/\registers_reg[23][18] } {/theRegisters/\registers_reg[23][19] } {/theRegisters/\registers_reg[23][1] } {/theRegisters/\registers_reg[23][20] } {/theRegisters/\registers_reg[23][21] } {/theRegisters/\registers_reg[23][22] } {/theRegisters/\registers_reg[23][23] } {/theRegisters/\registers_reg[23][24] } {/theRegisters/\registers_reg[23][25] } {/theRegisters/\registers_reg[23][26] } {/theRegisters/\registers_reg[23][27] } {/theRegisters/\registers_reg[23][28] } {/theRegisters/\registers_reg[23][29] } {/theRegisters/\registers_reg[23][2] } {/theRegisters/\registers_reg[23][30] } {/theRegisters/\registers_reg[23][31] } {/theRegisters/\registers_reg[23][3] } {/theRegisters/\registers_reg[23][4] } {/theRegisters/\registers_reg[23][5] } {/theRegisters/\registers_reg[23][6] } {/theRegisters/\registers_reg[23][7] } {/theRegisters/\registers_reg[23][8] } {/theRegisters/\registers_reg[23][9] } " -si_connections "SI_2 " -so_connections "SO_2 " -chain_count 1 +// sub-command: create_scan_chain_family scanChain_3 -include_elements "{/theRegisters/\registers_reg[24][0] } {/theRegisters/\registers_reg[24][10] } {/theRegisters/\registers_reg[24][11] } {/theRegisters/\registers_reg[24][12] } {/theRegisters/\registers_reg[24][13] } {/theRegisters/\registers_reg[24][14] } {/theRegisters/\registers_reg[24][15] } {/theRegisters/\registers_reg[24][16] } {/theRegisters/\registers_reg[24][17] } {/theRegisters/\registers_reg[24][18] } {/theRegisters/\registers_reg[24][19] } {/theRegisters/\registers_reg[24][1] } {/theRegisters/\registers_reg[24][20] } {/theRegisters/\registers_reg[24][21] } {/theRegisters/\registers_reg[24][22] } {/theRegisters/\registers_reg[24][23] } {/theRegisters/\registers_reg[24][24] } {/theRegisters/\registers_reg[24][25] } {/theRegisters/\registers_reg[24][26] } {/theRegisters/\registers_reg[24][27] } {/theRegisters/\registers_reg[24][28] } {/theRegisters/\registers_reg[24][29] } {/theRegisters/\registers_reg[24][2] } {/theRegisters/\registers_reg[24][30] } {/theRegisters/\registers_reg[24][31] } {/theRegisters/\registers_reg[24][3] } {/theRegisters/\registers_reg[24][4] } {/theRegisters/\registers_reg[24][5] } {/theRegisters/\registers_reg[24][6] } {/theRegisters/\registers_reg[24][7] } {/theRegisters/\registers_reg[24][8] } {/theRegisters/\registers_reg[24][9] } {/theRegisters/\registers_reg[25][0] } {/theRegisters/\registers_reg[25][10] } {/theRegisters/\registers_reg[25][11] } {/theRegisters/\registers_reg[25][12] } {/theRegisters/\registers_reg[25][13] } {/theRegisters/\registers_reg[25][14] } {/theRegisters/\registers_reg[25][15] } {/theRegisters/\registers_reg[25][16] } {/theRegisters/\registers_reg[25][17] } {/theRegisters/\registers_reg[25][18] } {/theRegisters/\registers_reg[25][19] } {/theRegisters/\registers_reg[25][1] } {/theRegisters/\registers_reg[25][20] } {/theRegisters/\registers_reg[25][21] } {/theRegisters/\registers_reg[25][22] } {/theRegisters/\registers_reg[25][23] } {/theRegisters/\registers_reg[25][24] } {/theRegisters/\registers_reg[25][25] } {/theRegisters/\registers_reg[25][26] } {/theRegisters/\registers_reg[25][27] } {/theRegisters/\registers_reg[25][28] } {/theRegisters/\registers_reg[25][29] } {/theRegisters/\registers_reg[25][2] } {/theRegisters/\registers_reg[25][30] } {/theRegisters/\registers_reg[25][31] } {/theRegisters/\registers_reg[25][3] } {/theRegisters/\registers_reg[25][4] } {/theRegisters/\registers_reg[25][5] } {/theRegisters/\registers_reg[25][6] } {/theRegisters/\registers_reg[25][7] } {/theRegisters/\registers_reg[25][8] } {/theRegisters/\registers_reg[25][9] } {/theRegisters/\registers_reg[26][0] } {/theRegisters/\registers_reg[26][10] } {/theRegisters/\registers_reg[26][11] } {/theRegisters/\registers_reg[26][12] } {/theRegisters/\registers_reg[26][13] } {/theRegisters/\registers_reg[26][14] } {/theRegisters/\registers_reg[26][15] } {/theRegisters/\registers_reg[26][16] } {/theRegisters/\registers_reg[26][17] } {/theRegisters/\registers_reg[26][18] } {/theRegisters/\registers_reg[26][19] } {/theRegisters/\registers_reg[26][1] } {/theRegisters/\registers_reg[26][20] } {/theRegisters/\registers_reg[26][21] } {/theRegisters/\registers_reg[26][22] } {/theRegisters/\registers_reg[26][23] } {/theRegisters/\registers_reg[26][24] } {/theRegisters/\registers_reg[26][25] } {/theRegisters/\registers_reg[26][26] } {/theRegisters/\registers_reg[26][27] } {/theRegisters/\registers_reg[26][28] } {/theRegisters/\registers_reg[26][29] } {/theRegisters/\registers_reg[26][2] } {/theRegisters/\registers_reg[26][30] } {/theRegisters/\registers_reg[26][31] } {/theRegisters/\registers_reg[26][3] } {/theRegisters/\registers_reg[26][4] } {/theRegisters/\registers_reg[26][5] } {/theRegisters/\registers_reg[26][6] } {/theRegisters/\registers_reg[26][7] } {/theRegisters/\registers_reg[26][8] } {/theRegisters/\registers_reg[26][9] } {/theRegisters/\registers_reg[27][0] } {/theRegisters/\registers_reg[27][10] } {/theRegisters/\registers_reg[27][11] } {/theRegisters/\registers_reg[27][12] } {/theRegisters/\registers_reg[27][13] } {/theRegisters/\registers_reg[27][14] } {/theRegisters/\registers_reg[27][15] } {/theRegisters/\registers_reg[27][16] } {/theRegisters/\registers_reg[27][17] } {/theRegisters/\registers_reg[27][18] } {/theRegisters/\registers_reg[27][19] } {/theRegisters/\registers_reg[27][1] } {/theRegisters/\registers_reg[27][20] } {/theRegisters/\registers_reg[27][21] } {/theRegisters/\registers_reg[27][22] } {/theRegisters/\registers_reg[27][23] } {/theRegisters/\registers_reg[27][24] } {/theRegisters/\registers_reg[27][25] } {/theRegisters/\registers_reg[27][26] } {/theRegisters/\registers_reg[27][27] } {/theRegisters/\registers_reg[27][28] } {/theRegisters/\registers_reg[27][29] } {/theRegisters/\registers_reg[27][2] } {/theRegisters/\registers_reg[27][30] } {/theRegisters/\registers_reg[27][31] } {/theRegisters/\registers_reg[27][3] } {/theRegisters/\registers_reg[27][4] } {/theRegisters/\registers_reg[27][5] } {/theRegisters/\registers_reg[27][6] } {/theRegisters/\registers_reg[27][7] } {/theRegisters/\registers_reg[27][8] } {/theRegisters/\registers_reg[27][9] } {/theRegisters/\registers_reg[28][0] } {/theRegisters/\registers_reg[28][10] } {/theRegisters/\registers_reg[28][11] } {/theRegisters/\registers_reg[28][12] } {/theRegisters/\registers_reg[28][13] } {/theRegisters/\registers_reg[28][14] } {/theRegisters/\registers_reg[28][15] } {/theRegisters/\registers_reg[28][16] } {/theRegisters/\registers_reg[28][17] } {/theRegisters/\registers_reg[28][18] } {/theRegisters/\registers_reg[28][19] } {/theRegisters/\registers_reg[28][1] } {/theRegisters/\registers_reg[28][20] } {/theRegisters/\registers_reg[28][21] } {/theRegisters/\registers_reg[28][22] } {/theRegisters/\registers_reg[28][23] } {/theRegisters/\registers_reg[28][24] } {/theRegisters/\registers_reg[28][25] } {/theRegisters/\registers_reg[28][26] } {/theRegisters/\registers_reg[28][27] } {/theRegisters/\registers_reg[28][28] } {/theRegisters/\registers_reg[28][29] } {/theRegisters/\registers_reg[28][2] } {/theRegisters/\registers_reg[28][30] } {/theRegisters/\registers_reg[28][31] } {/theRegisters/\registers_reg[28][3] } {/theRegisters/\registers_reg[28][4] } {/theRegisters/\registers_reg[28][5] } {/theRegisters/\registers_reg[28][6] } {/theRegisters/\registers_reg[28][7] } {/theRegisters/\registers_reg[28][8] } {/theRegisters/\registers_reg[28][9] } {/theRegisters/\registers_reg[29][0] } {/theRegisters/\registers_reg[29][10] } {/theRegisters/\registers_reg[29][11] } {/theRegisters/\registers_reg[29][12] } {/theRegisters/\registers_reg[29][13] } {/theRegisters/\registers_reg[29][14] } {/theRegisters/\registers_reg[29][15] } {/theRegisters/\registers_reg[29][16] } {/theRegisters/\registers_reg[29][17] } {/theRegisters/\registers_reg[29][18] } {/theRegisters/\registers_reg[29][19] } {/theRegisters/\registers_reg[29][1] } {/theRegisters/\registers_reg[29][20] } {/theRegisters/\registers_reg[29][21] } {/theRegisters/\registers_reg[29][22] } {/theRegisters/\registers_reg[29][23] } {/theRegisters/\registers_reg[29][24] } {/theRegisters/\registers_reg[29][25] } {/theRegisters/\registers_reg[29][26] } {/theRegisters/\registers_reg[29][27] } {/theRegisters/\registers_reg[29][28] } {/theRegisters/\registers_reg[29][29] } {/theRegisters/\registers_reg[29][2] } {/theRegisters/\registers_reg[29][30] } {/theRegisters/\registers_reg[29][31] } {/theRegisters/\registers_reg[29][3] } {/theRegisters/\registers_reg[29][4] } {/theRegisters/\registers_reg[29][5] } {/theRegisters/\registers_reg[29][6] } {/theRegisters/\registers_reg[29][7] } {/theRegisters/\registers_reg[29][8] } {/theRegisters/\registers_reg[29][9] } {/theRegisters/\registers_reg[2][0] } {/theRegisters/\registers_reg[2][10] } {/theRegisters/\registers_reg[2][11] } {/theRegisters/\registers_reg[2][12] } {/theRegisters/\registers_reg[2][13] } {/theRegisters/\registers_reg[2][14] } {/theRegisters/\registers_reg[2][15] } {/theRegisters/\registers_reg[2][16] } {/theRegisters/\registers_reg[2][17] } {/theRegisters/\registers_reg[2][18] } {/theRegisters/\registers_reg[2][19] } {/theRegisters/\registers_reg[2][1] } {/theRegisters/\registers_reg[2][20] } {/theRegisters/\registers_reg[2][21] } {/theRegisters/\registers_reg[2][22] } {/theRegisters/\registers_reg[2][23] } {/theRegisters/\registers_reg[2][24] } {/theRegisters/\registers_reg[2][25] } {/theRegisters/\registers_reg[2][26] } {/theRegisters/\registers_reg[2][27] } {/theRegisters/\registers_reg[2][28] } {/theRegisters/\registers_reg[2][29] } {/theRegisters/\registers_reg[2][2] } {/theRegisters/\registers_reg[2][30] } {/theRegisters/\registers_reg[2][31] } {/theRegisters/\registers_reg[2][3] } {/theRegisters/\registers_reg[2][4] } {/theRegisters/\registers_reg[2][5] } {/theRegisters/\registers_reg[2][6] } {/theRegisters/\registers_reg[2][7] } {/theRegisters/\registers_reg[2][8] } {/theRegisters/\registers_reg[2][9] } {/theRegisters/\registers_reg[30][0] } {/theRegisters/\registers_reg[30][10] } {/theRegisters/\registers_reg[30][11] } {/theRegisters/\registers_reg[30][12] } {/theRegisters/\registers_reg[30][13] } {/theRegisters/\registers_reg[30][14] } {/theRegisters/\registers_reg[30][15] } {/theRegisters/\registers_reg[30][16] } {/theRegisters/\registers_reg[30][17] } {/theRegisters/\registers_reg[30][18] } {/theRegisters/\registers_reg[30][19] } {/theRegisters/\registers_reg[30][1] } {/theRegisters/\registers_reg[30][20] } {/theRegisters/\registers_reg[30][21] } {/theRegisters/\registers_reg[30][22] } {/theRegisters/\registers_reg[30][23] } {/theRegisters/\registers_reg[30][24] } {/theRegisters/\registers_reg[30][25] } {/theRegisters/\registers_reg[30][26] } {/theRegisters/\registers_reg[30][27] } {/theRegisters/\registers_reg[30][28] } {/theRegisters/\registers_reg[30][29] } {/theRegisters/\registers_reg[30][2] } {/theRegisters/\registers_reg[30][30] } {/theRegisters/\registers_reg[30][31] } {/theRegisters/\registers_reg[30][3] } {/theRegisters/\registers_reg[30][4] } {/theRegisters/\registers_reg[30][5] } {/theRegisters/\registers_reg[30][6] } {/theRegisters/\registers_reg[30][7] } {/theRegisters/\registers_reg[30][8] } {/theRegisters/\registers_reg[30][9] } " -si_connections "SI_3 " -so_connections "SO_3 " -chain_count 1 +// sub-command: create_scan_chain_family scanChain_4 -include_elements "{/theRegisters/\registers_reg[31][0] } {/theRegisters/\registers_reg[31][10] } {/theRegisters/\registers_reg[31][11] } {/theRegisters/\registers_reg[31][12] } {/theRegisters/\registers_reg[31][13] } {/theRegisters/\registers_reg[31][14] } {/theRegisters/\registers_reg[31][15] } {/theRegisters/\registers_reg[31][16] } {/theRegisters/\registers_reg[31][17] } {/theRegisters/\registers_reg[31][18] } {/theRegisters/\registers_reg[31][19] } {/theRegisters/\registers_reg[31][1] } {/theRegisters/\registers_reg[31][20] } {/theRegisters/\registers_reg[31][21] } {/theRegisters/\registers_reg[31][22] } {/theRegisters/\registers_reg[31][23] } {/theRegisters/\registers_reg[31][24] } {/theRegisters/\registers_reg[31][25] } {/theRegisters/\registers_reg[31][26] } {/theRegisters/\registers_reg[31][27] } {/theRegisters/\registers_reg[31][28] } {/theRegisters/\registers_reg[31][29] } {/theRegisters/\registers_reg[31][2] } {/theRegisters/\registers_reg[31][30] } {/theRegisters/\registers_reg[31][31] } {/theRegisters/\registers_reg[31][3] } {/theRegisters/\registers_reg[31][4] } {/theRegisters/\registers_reg[31][5] } {/theRegisters/\registers_reg[31][6] } {/theRegisters/\registers_reg[31][7] } {/theRegisters/\registers_reg[31][8] } {/theRegisters/\registers_reg[31][9] } {/theRegisters/\registers_reg[3][0] } {/theRegisters/\registers_reg[3][10] } {/theRegisters/\registers_reg[3][11] } {/theRegisters/\registers_reg[3][12] } {/theRegisters/\registers_reg[3][13] } {/theRegisters/\registers_reg[3][14] } {/theRegisters/\registers_reg[3][15] } {/theRegisters/\registers_reg[3][16] } {/theRegisters/\registers_reg[3][17] } {/theRegisters/\registers_reg[3][18] } {/theRegisters/\registers_reg[3][19] } {/theRegisters/\registers_reg[3][1] } {/theRegisters/\registers_reg[3][20] } {/theRegisters/\registers_reg[3][21] } {/theRegisters/\registers_reg[3][22] } {/theRegisters/\registers_reg[3][23] } {/theRegisters/\registers_reg[3][24] } {/theRegisters/\registers_reg[3][25] } {/theRegisters/\registers_reg[3][26] } {/theRegisters/\registers_reg[3][27] } {/theRegisters/\registers_reg[3][28] } {/theRegisters/\registers_reg[3][29] } {/theRegisters/\registers_reg[3][2] } {/theRegisters/\registers_reg[3][30] } {/theRegisters/\registers_reg[3][31] } {/theRegisters/\registers_reg[3][3] } {/theRegisters/\registers_reg[3][4] } {/theRegisters/\registers_reg[3][5] } {/theRegisters/\registers_reg[3][6] } {/theRegisters/\registers_reg[3][7] } {/theRegisters/\registers_reg[3][8] } {/theRegisters/\registers_reg[3][9] } {/theRegisters/\registers_reg[4][0] } {/theRegisters/\registers_reg[4][10] } {/theRegisters/\registers_reg[4][11] } {/theRegisters/\registers_reg[4][12] } {/theRegisters/\registers_reg[4][13] } {/theRegisters/\registers_reg[4][14] } {/theRegisters/\registers_reg[4][15] } {/theRegisters/\registers_reg[4][16] } {/theRegisters/\registers_reg[4][17] } {/theRegisters/\registers_reg[4][18] } {/theRegisters/\registers_reg[4][19] } {/theRegisters/\registers_reg[4][1] } {/theRegisters/\registers_reg[4][20] } {/theRegisters/\registers_reg[4][21] } {/theRegisters/\registers_reg[4][22] } {/theRegisters/\registers_reg[4][23] } {/theRegisters/\registers_reg[4][24] } {/theRegisters/\registers_reg[4][25] } {/theRegisters/\registers_reg[4][26] } {/theRegisters/\registers_reg[4][27] } {/theRegisters/\registers_reg[4][28] } {/theRegisters/\registers_reg[4][29] } {/theRegisters/\registers_reg[4][2] } {/theRegisters/\registers_reg[4][30] } {/theRegisters/\registers_reg[4][31] } {/theRegisters/\registers_reg[4][3] } {/theRegisters/\registers_reg[4][4] } {/theRegisters/\registers_reg[4][5] } {/theRegisters/\registers_reg[4][6] } {/theRegisters/\registers_reg[4][7] } {/theRegisters/\registers_reg[4][8] } {/theRegisters/\registers_reg[4][9] } {/theRegisters/\registers_reg[5][0] } {/theRegisters/\registers_reg[5][10] } {/theRegisters/\registers_reg[5][11] } {/theRegisters/\registers_reg[5][12] } {/theRegisters/\registers_reg[5][13] } {/theRegisters/\registers_reg[5][14] } {/theRegisters/\registers_reg[5][15] } {/theRegisters/\registers_reg[5][16] } {/theRegisters/\registers_reg[5][17] } {/theRegisters/\registers_reg[5][18] } {/theRegisters/\registers_reg[5][19] } {/theRegisters/\registers_reg[5][1] } {/theRegisters/\registers_reg[5][20] } {/theRegisters/\registers_reg[5][21] } {/theRegisters/\registers_reg[5][22] } {/theRegisters/\registers_reg[5][23] } {/theRegisters/\registers_reg[5][24] } {/theRegisters/\registers_reg[5][25] } {/theRegisters/\registers_reg[5][26] } {/theRegisters/\registers_reg[5][27] } {/theRegisters/\registers_reg[5][28] } {/theRegisters/\registers_reg[5][29] } {/theRegisters/\registers_reg[5][2] } {/theRegisters/\registers_reg[5][30] } {/theRegisters/\registers_reg[5][31] } {/theRegisters/\registers_reg[5][3] } {/theRegisters/\registers_reg[5][4] } {/theRegisters/\registers_reg[5][5] } {/theRegisters/\registers_reg[5][6] } {/theRegisters/\registers_reg[5][7] } {/theRegisters/\registers_reg[5][8] } {/theRegisters/\registers_reg[5][9] } {/theRegisters/\registers_reg[6][0] } {/theRegisters/\registers_reg[6][10] } {/theRegisters/\registers_reg[6][11] } {/theRegisters/\registers_reg[6][12] } {/theRegisters/\registers_reg[6][13] } {/theRegisters/\registers_reg[6][14] } {/theRegisters/\registers_reg[6][15] } {/theRegisters/\registers_reg[6][16] } {/theRegisters/\registers_reg[6][17] } {/theRegisters/\registers_reg[6][18] } {/theRegisters/\registers_reg[6][19] } {/theRegisters/\registers_reg[6][1] } {/theRegisters/\registers_reg[6][20] } {/theRegisters/\registers_reg[6][21] } {/theRegisters/\registers_reg[6][22] } {/theRegisters/\registers_reg[6][23] } {/theRegisters/\registers_reg[6][24] } {/theRegisters/\registers_reg[6][25] } {/theRegisters/\registers_reg[6][26] } {/theRegisters/\registers_reg[6][27] } {/theRegisters/\registers_reg[6][28] } {/theRegisters/\registers_reg[6][29] } {/theRegisters/\registers_reg[6][2] } {/theRegisters/\registers_reg[6][30] } {/theRegisters/\registers_reg[6][31] } {/theRegisters/\registers_reg[6][3] } {/theRegisters/\registers_reg[6][4] } {/theRegisters/\registers_reg[6][5] } {/theRegisters/\registers_reg[6][6] } {/theRegisters/\registers_reg[6][7] } {/theRegisters/\registers_reg[6][8] } {/theRegisters/\registers_reg[6][9] } {/theRegisters/\registers_reg[7][0] } {/theRegisters/\registers_reg[7][10] } {/theRegisters/\registers_reg[7][11] } {/theRegisters/\registers_reg[7][12] } {/theRegisters/\registers_reg[7][13] } {/theRegisters/\registers_reg[7][14] } {/theRegisters/\registers_reg[7][15] } {/theRegisters/\registers_reg[7][16] } {/theRegisters/\registers_reg[7][17] } {/theRegisters/\registers_reg[7][18] } {/theRegisters/\registers_reg[7][19] } {/theRegisters/\registers_reg[7][1] } {/theRegisters/\registers_reg[7][20] } {/theRegisters/\registers_reg[7][21] } {/theRegisters/\registers_reg[7][22] } {/theRegisters/\registers_reg[7][23] } {/theRegisters/\registers_reg[7][24] } {/theRegisters/\registers_reg[7][25] } {/theRegisters/\registers_reg[7][26] } {/theRegisters/\registers_reg[7][27] } {/theRegisters/\registers_reg[7][28] } {/theRegisters/\registers_reg[7][29] } {/theRegisters/\registers_reg[7][2] } {/theRegisters/\registers_reg[7][30] } {/theRegisters/\registers_reg[7][31] } {/theRegisters/\registers_reg[7][3] } {/theRegisters/\registers_reg[7][4] } {/theRegisters/\registers_reg[7][5] } {/theRegisters/\registers_reg[7][6] } {/theRegisters/\registers_reg[7][7] } {/theRegisters/\registers_reg[7][8] } {/theRegisters/\registers_reg[7][9] } {/theRegisters/\registers_reg[8][0] } {/theRegisters/\registers_reg[8][10] } {/theRegisters/\registers_reg[8][11] } {/theRegisters/\registers_reg[8][12] } {/theRegisters/\registers_reg[8][13] } {/theRegisters/\registers_reg[8][14] } {/theRegisters/\registers_reg[8][15] } {/theRegisters/\registers_reg[8][16] } {/theRegisters/\registers_reg[8][17] } {/theRegisters/\registers_reg[8][18] } {/theRegisters/\registers_reg[8][19] } {/theRegisters/\registers_reg[8][1] } {/theRegisters/\registers_reg[8][20] } {/theRegisters/\registers_reg[8][21] } {/theRegisters/\registers_reg[8][22] } {/theRegisters/\registers_reg[8][23] } {/theRegisters/\registers_reg[8][24] } {/theRegisters/\registers_reg[8][25] } {/theRegisters/\registers_reg[8][26] } {/theRegisters/\registers_reg[8][27] } {/theRegisters/\registers_reg[8][28] } {/theRegisters/\registers_reg[8][29] } {/theRegisters/\registers_reg[8][2] } {/theRegisters/\registers_reg[8][30] } {/theRegisters/\registers_reg[8][31] } {/theRegisters/\registers_reg[8][3] } {/theRegisters/\registers_reg[8][4] } {/theRegisters/\registers_reg[8][5] } {/theRegisters/\registers_reg[8][6] } {/theRegisters/\registers_reg[8][7] } {/theRegisters/\registers_reg[8][8] } {/theRegisters/\registers_reg[8][9] } {/theRegisters/\registers_reg[9][0] } {/theRegisters/\registers_reg[9][10] } {/theRegisters/\registers_reg[9][11] } {/theRegisters/\registers_reg[9][12] } {/theRegisters/\registers_reg[9][13] } {/theRegisters/\registers_reg[9][14] } {/theRegisters/\registers_reg[9][15] } {/theRegisters/\registers_reg[9][16] } {/theRegisters/\registers_reg[9][17] } {/theRegisters/\registers_reg[9][18] } {/theRegisters/\registers_reg[9][19] } {/theRegisters/\registers_reg[9][1] } {/theRegisters/\registers_reg[9][20] } {/theRegisters/\registers_reg[9][21] } {/theRegisters/\registers_reg[9][22] } {/theRegisters/\registers_reg[9][23] } {/theRegisters/\registers_reg[9][24] } {/theRegisters/\registers_reg[9][25] } {/theRegisters/\registers_reg[9][26] } {/theRegisters/\registers_reg[9][27] } {/theRegisters/\registers_reg[9][28] } {/theRegisters/\registers_reg[9][29] } {/theRegisters/\registers_reg[9][2] } {/theRegisters/\registers_reg[9][30] } {/theRegisters/\registers_reg[9][31] } {/theRegisters/\registers_reg[9][3] } {/theRegisters/\registers_reg[9][4] } {/theRegisters/\registers_reg[9][5] } {/theRegisters/\registers_reg[9][6] } {/theRegisters/\registers_reg[9][7] } {/theRegisters/\registers_reg[9][8] } {/theRegisters/\registers_reg[9][9] } " -si_connections "SI_4 " -so_connections "SO_4 " -chain_count 1 +// sub-command: analyze_scan_chains +// Chain allocation of 'unwrapped' mode completed: +// 4 distributed chains of size 256 +// sub-command: insert_test_logic -write_in_tsdb on +============================= +Test Logic Insertion Summary: +============================= + + Structural Data: + ---------------- + Added top-level port count: 0 + Added instance count: 8 + + Logical Data: + ------------- + Added retiming logic count: 4 + Added scan chain count (unwrapped): 4 + +// Warning: Flattened model deleted. +// +// Writing out netlist and related files in /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.02/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design +// sub-command: report_scan_chains + +=============================== +Scan Chains Created by the Tool +=============================== + + Scan mode 'unwrapped' scan chains: + ---------------------------------- + + Cluster 'scanChain_1' chains: + ----------------------------- + chain = scanChain_1 group = dummy input = /SI_1 output = /SO_1 length = 256 + + Cluster 'scanChain_2' chains: + ----------------------------- + chain = scanChain_2 group = dummy input = /SI_2 output = /SO_2 length = 256 + + Cluster 'scanChain_3' chains: + ----------------------------- + chain = scanChain_3 group = dummy input = /SI_3 output = /SO_3 length = 256 + + Cluster 'scanChain_4' chains: + ----------------------------- + chain = scanChain_4 group = dummy input = /SI_4 output = /SO_4 length = 256 + + +// sub-command: write_scan_order /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.02/Scan_0/cpu.scandef -use_escaping_rule Lefdef -replace +// sub-command: write_design -output_file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.02/Scan_0/post_scan.v -replace +// command: exit + +************************************************************************************************************************************************************************************** + TESSENT EXECUTION ENDS HERE ! +************************************************************************************************************************************************************************************** + +Dumping current design to /tmp/oasys.2567737/dft_eco/cpu +> write_db /tmp/oasys.2567737/dft_eco/cpu +info: Target library/cell information has changed that further may change timing results. [TA-159] +info: Successfully traced scan chain (scan_in: 'SI_1', scan_out: 'SO_1' with 258 elements ) [DFT-354] +info: Successfully traced scan chain (scan_in: 'SI_2', scan_out: 'SO_2' with 258 elements ) [DFT-354] +info: Successfully traced scan chain (scan_in: 'SI_3', scan_out: 'SO_3' with 258 elements ) [DFT-354] +info: Successfully traced scan chain (scan_in: 'SI_4', scan_out: 'SO_4' with 258 elements ) [DFT-354] +> write_db ./output/odb/riscv.tessent_post_scan.odb +> write_verilog ./output/riscv.tessent_post_scan.v +info: writing Verilog file './output/riscv.tessent_post_scan.v' for module 'cpu' [WRITE-100] + +----------report_power---------------- +> report_power +Report Power (instances with prefix '*' are included in total) : +-----+----------------------------------------+--------------------+---------------------+-------------------+----------------- + | Instance | Internal Power (uW)| Switching Power (uW)| Leakage Power (uW)| Total Power (uW) +-----+----------------------------------------+--------------------+---------------------+-------------------+----------------- +1 |*theMem | 4965.347656| 97.271141| 528.368530| 5590.987793 +2 |*theRegisters | 2937.847412| 65.430710| 75.000534| 3078.278564 +3 |*theDecoder | 3306.815674| 29.696104| 69.466927| 3405.978516 +4 |*thePC_i_0 | 102.036263| 0.516853| 0.818020| 103.371140 +5 |*thePC_CurrentPC_reg[31] | 6.132826| 0.115208| 0.000019| 6.248054 +6 |*thePC_CurrentPC_reg[30] | 6.132829| 0.122289| 0.000019| 6.255136 +7 |*thePC_CurrentPC_reg[29] | 6.132829| 0.122289| 0.000019| 6.255136 +8 |*thePC_CurrentPC_reg[28] | 6.132829| 0.122289| 0.000019| 6.255136 +9 |*thePC_CurrentPC_reg[27] | 6.132829| 0.122289| 0.000019| 6.255136 +10 |*thePC_CurrentPC_reg[26] | 6.132829| 0.122289| 0.000019| 6.255136 +11 |*thePC_CurrentPC_reg[25] | 6.132829| 0.122289| 0.000019| 6.255136 +12 |*thePC_CurrentPC_reg[24] | 6.132829| 0.122289| 0.000019| 6.255136 +13 |*thePC_CurrentPC_reg[23] | 6.132829| 0.122289| 0.000019| 6.255136 +14 |*thePC_CurrentPC_reg[22] | 6.132829| 0.122289| 0.000019| 6.255136 +15 |*thePC_CurrentPC_reg[21] | 6.135628| 0.207666| 0.000019| 6.343312 +16 |*thePC_CurrentPC_reg[20] | 6.132829| 0.122289| 0.000019| 6.255136 +17 |*thePC_CurrentPC_reg[19] | 6.132828| 0.121340| 0.000019| 6.254188 +18 |*thePC_CurrentPC_reg[18] | 6.132828| 0.121340| 0.000019| 6.254188 +19 |*thePC_CurrentPC_reg[17] | 6.132828| 0.121340| 0.000019| 6.254188 +20 |*thePC_CurrentPC_reg[16] | 6.132828| 0.121340| 0.000019| 6.254188 +21 |*thePC_CurrentPC_reg[15] | 6.132826| 0.115029| 0.000019| 6.247873 +22 |*thePC_CurrentPC_reg[14] | 6.132828| 0.121340| 0.000019| 6.254188 +23 |*thePC_CurrentPC_reg[13] | 6.135591| 0.206718| 0.000019| 6.342327 +24 |*thePC_CurrentPC_reg[12] | 6.132828| 0.121340| 0.000019| 6.254188 +25 |*thePC_CurrentPC_reg[11] | 6.132828| 0.120392| 0.000019| 6.253239 +26 |*thePC_CurrentPC_reg[10] | 6.132827| 0.115675| 0.000019| 6.248520 +27 |*thePC_CurrentPC_reg[9] | 6.132827| 0.115675| 0.000019| 6.248520 +28 |*thePC_CurrentPC_reg[8] | 6.132827| 0.115675| 0.000019| 6.248520 +29 |*thePC_CurrentPC_reg[7] | 6.132825| 0.109358| 0.000019| 6.242202 +30 |*thePC_CurrentPC_reg[6] | 6.132825| 0.109358| 0.000019| 6.242202 +31 |*thePC_CurrentPC_reg[5] | 6.132825| 0.109358| 0.000019| 6.242202 +32 |*thePC_CurrentPC_reg[4] | 6.132825| 0.109358| 0.000019| 6.242202 +33 |*thePC_CurrentPC_reg[3] | 6.132825| 0.109358| 0.000019| 6.242202 +34 |*thePC_CurrentPC_reg[2] | 6.136212| 0.222482| 0.000019| 6.358713 +35 |*thePC_CurrentPC_reg[1] | 6.132825| 0.110713| 0.000019| 6.243557 +36 |*thePC_CurrentPC_reg[0] | 6.132828| 0.121456| 0.000019| 6.254303 +37 |*i_0_0_0 | 3.636180| 0.005795| 0.056141| 3.698117 +38 |*i_0_0_1 | 3.630034| 0.075574| 0.049831| 3.755438 +39 |*i_0_0_2 | 3.589001| 0.005720| 0.056141| 3.650862 +40 |*i_0_0_3 | 3.579433| 0.074593| 0.049831| 3.703857 +41 |*i_0_0_4 | 4.765921| 0.005811| 0.038697| 4.810430 +42 |*i_0_0_5 | 4.765921| 0.005811| 0.038697| 4.810430 +43 |*i_0_0_6 | 4.765921| 0.005811| 0.038697| 4.810430 +44 |*i_0_0_7 | 4.765921| 0.005811| 0.038697| 4.810430 +45 |*i_0_0_8 | 4.765921| 0.005811| 0.038697| 4.810430 +46 |*i_0_0_9 | 4.765921| 0.005811| 0.038697| 4.810430 +47 |*i_0_0_10 | 4.760734| 0.005811| 0.038697| 4.805242 +48 |*i_0_0_11 | 4.760734| 0.005811| 0.038697| 4.805242 +49 |*i_0_0_12 | 4.760734| 0.005811| 0.038697| 4.805242 +50 |*i_0_0_13 | 4.760734| 0.005811| 0.038697| 4.805242 +51 |*i_0_0_14 | 4.760734| 0.005811| 0.038697| 4.805242 +52 |*i_0_0_15 | 3.589408| 0.005721| 0.056141| 3.651270 +53 |*i_0_0_16 | 3.579309| 0.074602| 0.049831| 3.703742 +54 |*i_0_0_17 | 3.589739| 0.005721| 0.056141| 3.651601 +55 |*i_0_0_18 | 3.579648| 0.074608| 0.049831| 3.704087 +56 |*i_0_0_19 | 3.590052| 0.005722| 0.056141| 3.651915 +57 |*i_0_0_20 | 3.579969| 0.074615| 0.049831| 3.704415 +58 |*i_0_0_21 | 3.590306| 0.005722| 0.056141| 3.652169 +59 |*i_0_0_22 | 3.580231| 0.074620| 0.049831| 3.704682 +60 |*i_0_0_23 | 3.590506| 0.005722| 0.056141| 3.652370 +61 |*i_0_0_24 | 3.580436| 0.074625| 0.049831| 3.704891 +62 |*i_0_0_25 | 3.590656| 0.005723| 0.056141| 3.652520 +63 |*i_0_0_26 | 3.580589| 0.074627| 0.049831| 3.705047 +64 |*i_0_0_27 | 3.590823| 0.005723| 0.056141| 3.652687 +65 |*i_0_0_28 | 3.580760| 0.074631| 0.049831| 3.705222 +66 |*i_0_0_29 | 3.590933| 0.005723| 0.056141| 3.652797 +67 |*i_0_0_30 | 3.580874| 0.074633| 0.049831| 3.705338 +68 |*i_0_0_31 | 3.590987| 0.005723| 0.056141| 3.652852 +69 |*i_0_0_32 | 3.580929| 0.074634| 0.049831| 3.705395 +70 |*i_0_0_33 | 3.591065| 0.005723| 0.056141| 3.652930 +71 |*i_0_0_34 | 3.581009| 0.074636| 0.049831| 3.705476 +72 |*i_0_0_35 | 3.591195| 0.005724| 0.056141| 3.653060 +73 |*i_0_0_36 | 3.581142| 0.074639| 0.049831| 3.705612 +74 |*i_0_0_37 | 3.591303| 0.005724| 0.056141| 3.653168 +75 |*i_0_0_38 | 3.581253| 0.074641| 0.049831| 3.705725 +76 |*i_0_0_39 | 3.591386| 0.005724| 0.056141| 3.653251 +77 |*i_0_0_40 | 3.581338| 0.074643| 0.049831| 3.705812 +78 |*i_0_0_41 | 3.591435| 0.005724| 0.056141| 3.653301 +79 |*i_0_0_42 | 3.581389| 0.074644| 0.049831| 3.705863 +80 |*i_0_0_43 | 3.591419| 0.005724| 0.056141| 3.653284 +81 |*i_0_0_44 | 3.581372| 0.074644| 0.049831| 3.705847 +82 |*i_0_0_45 | 3.591433| 0.005724| 0.056141| 3.653298 +83 |*i_0_0_46 | 3.581386| 0.074644| 0.049831| 3.705861 +84 |*i_0_0_47 | 3.591558| 0.005724| 0.056141| 3.653424 +85 |*i_0_0_48 | 3.581515| 0.074646| 0.049831| 3.705992 +86 |*i_0_0_49 | 3.591676| 0.005724| 0.056141| 3.653541 +87 |*i_0_0_50 | 3.581635| 0.074649| 0.049831| 3.706115 +88 |*i_0_0_51 | 3.591723| 0.005724| 0.056141| 3.653588 +89 |*i_0_0_52 | 3.581872| 0.074650| 0.049831| 3.706352 +90 |*i_0_0_53 | 0.270481| 0.031764| 0.181711| 0.483956 +91 |*i_0_0_54 | 8.109213| 0.417922| 0.187759| 8.714894 +92 |*i_0_0_55 | 4.662969| 0.392350| 0.167543| 5.222862 +93 |*i_0_0_56 | 4.661758| 0.392909| 0.167809| 5.222477 +94 |*i_0_0_57 | 4.661533| 0.392163| 0.167455| 5.221151 +95 |*i_0_0_58 | 4.661815| 0.393097| 0.167897| 5.222809 +96 |*i_0_0_59 | 4.661477| 0.391976| 0.167366| 5.220819 +97 |*i_0_0_60 | 4.661870| 0.393283| 0.167986| 5.223139 +98 |*i_0_0_61 | 4.263187| 0.064498| 0.029698| 4.357384 +99 |*i_0_0_62 | 4.263187| 0.064498| 0.029698| 4.357384 +100 |*i_0_0_63 | 4.263187| 0.064498| 0.029698| 4.357384 +101 |*i_0_0_64 | 4.263187| 0.064498| 0.029698| 4.357384 +102 |*i_0_0_65 | 4.263187| 0.064498| 0.029698| 4.357384 +103 |*i_0_0_66 | 892.076904| 9.773184| 0.224563| 902.074707 +104 |*tessent_persistent_cell_buf_extsi1225_i| 12.245425| 0.023904| 0.084228| 12.353557 +105 | | | | | +106 |*TOTAL | 12673.386719| 211.656723| 678.138367| 13563.180664 +-----+----------------------------------------+--------------------+---------------------+-------------------+----------------- + +----------report_path_groups---------------- +> report_path_groups +Report Path Groups: +-----+-------+------+---------+--------- + | Path |Weight|Critical |Worst + | Group | |Range(ps)|Slack(ps) +-----+-------+------+---------+--------- +1 |default| 1.000| 0.0| 18131.2 +2 |I2R | 1.000| 0.0| +3 |I2O | 1.000| 0.0| +4 |R2O | 1.000| 0.0| 36309.8 +-----+-------+------+---------+--------- + +----------report_scan_chains---------------- +> report_scan_chains +Report ScanChains: +--------+-----------+--------------+--------+-----------+-----------+--------------+------------------+--------+--------+---------+-----------+---------- + Index | Chain | ScanInstance | Length | TestClock | ClockEdge | Comp. Chains | Max Comp. Length | Lockup | ScanIn | ScanOut | Partition | ScanMode +--------+-----------+--------------+--------+-----------+-----------+--------------+------------------+--------+--------+---------+-----------+---------- + 1|scanChain_1| 258 | 256|clk_25mhz |rise | - | - | 1|SI_1 |SO_1 | - | + 2|scanChain_2| 258 | 256|clk_25mhz |rise | - | - | 1|SI_2 |SO_2 | - | + 3|scanChain_3| 258 | 256|clk_25mhz |rise | - | - | 1|SI_3 |SO_3 | - | + 4|scanChain_4| 258 | 256|clk_25mhz |rise | - | - | 1|SI_4 |SO_4 | - | +--------+-----------+--------------+--------+-----------+-----------+--------------+------------------+--------+--------+---------+-----------+---------- + +----------report_timing---------------- +> report_timing +Report for group default +-------------------------------------------------------------------------------------------------------------------------------------- +Startpoint: theMem/IRData_reg[18]/Q + (Clocked by clk_25mhz R) +Endpoint: theMem/mem_addr_reg[5]/D + (Clocked by clk_25mhz F) +Path Group: default +Data required time: 19371.2 + (Clock shift: 20000.0, minus Uncertainty: 500.0, plus Latency 0.0, minus Setup time: 128.8) +Data arrival time: 1240.0 +Slack: 18131.2 +Logic depth: 46 +-------------------------------------------------------------------------------------------------------------------------------------- + Arrival Arc Net Net Total fan- +Path Module/Cell Edge Time Delay Delay Delay Slew Load Load out Location + (ps) (ps) (ps) (ps) (ps) (ff) (ff) (#) (um,um) +-------------------------------------------------------------------------------------------------------------------------------------- +clk_25mhz {create_clock} r 0.0 0.0 0.0 0.0 0.0 100 101, 0 +theMem/IRData_reg[18]/CK->Q + DFF_X1_LVT* rr 106.0 106.0 106.0 0.0 100.0 15.2 77.1 10 175, 106 +theRegisters/i_1_0_1371/A->ZN + INV_X8_LVT rf 108.7 2.7 2.7 0.0 10.2 2.1 13.2 3 168, 158 +theRegisters/i_1_0_1339/A2->ZN + NAND3_X4_LVT fr 122.7 14.0 14.0 0.0 1.0 2.5 17.5 4 168, 158 +theRegisters/i_1_0_1321/A2->ZN + NOR2_X4_LVT* rf 141.6 19.0 19.0 0.0 12.1 29.7 130.1 32 168, 158 +theRegisters/i_1_0_722/B1->ZN + AOI22_X4_LVT* fr 186.0 44.3 44.3 0.0 10.2 0.7 23.4 1 168, 158 +theRegisters/i_1_0_721/A->ZN + INV_X8_LVT rf 188.1 2.1 2.1 0.0 10.2 0.8 3.0 1 168, 158 +theRegisters/i_1_0_718/A->ZN + AOI221_X2_LVT fr 245.4 57.3 57.3 0.0 0.6 0.9 4.4 1 168, 158 +theRegisters/i_1_0_716/A3->ZN + NAND4_X4_LVT rf 260.8 15.4 15.4 0.0 34.6 0.9 3.1 1 168, 158 +theRegisters/i_1_0_715/A->ZN + AOI221_X2_LVT fr 318.1 57.4 57.4 0.0 6.8 0.9 4.3 1 168, 158 +theRegisters/i_1_0_704/A2->ZN + NAND4_X4_LVT* rf 342.3 24.2 24.2 0.0 34.4 14.1 24.9 3 168, 158 +theDecoder/i_0_133/C2->ZN + AOI222_X4_LVT fr 452.6 110.3 110.3 0.0 10.2 0.8 23.5 1 129, 89 +theDecoder/i_0_132/A->ZN INV_X32_LVT rf 455.7 3.1 3.1 0.0 10.9 5.4 65.3 7 129, 89 +theDecoder/theALU/i_0_706/B1->ZN + OAI22_X4_LVT* fr 498.9 43.2 43.2 0.0 1.4 1.5 25.9 2 129, 89 +theDecoder/theALU/i_0_705/A->ZN + INV_X8_LVT rf 501.1 2.2 2.2 0.0 10.2 0.6 4.2 1 129, 89 +theDecoder/theALU/i_0_42/A->ZN + OAI21_X2_LVT fr 510.2 9.1 9.1 0.0 0.6 0.8 2.5 1 129, 89 +theDecoder/theALU/i_0_40/C1->ZN + AOI211_X2_LVT rf 515.8 5.6 5.6 0.0 11.6 0.8 2.9 1 129, 89 +theDecoder/theALU/i_0_39/B->ZN + AOI211_X2_LVT fr 563.3 47.4 47.4 0.0 3.3 0.9 3.0 1 129, 89 +theDecoder/theALU/i_0_38/B2->ZN + OAI222_X2_LVT rf 580.2 16.9 16.9 0.0 27.7 0.9 2.9 1 129, 89 +theDecoder/theALU/i_0_37/C2->ZN + AOI221_X2_LVT fr 624.0 43.8 43.8 0.0 8.4 0.9 4.2 1 129, 89 +theDecoder/theALU/i_0_35/B1->ZN + OAI22_X4_LVT* rf 637.9 13.9 13.9 0.0 34.0 0.7 23.4 1 129, 89 +theDecoder/theALU/i_0_34/A->ZN + INV_X8_LVT fr 642.4 4.5 4.5 0.0 10.2 0.6 4.1 1 129, 89 +theDecoder/theALU/i_0_33/A->ZN + AOI21_X4_LVT rf 645.0 2.6 2.6 0.0 2.4 0.8 3.0 1 129, 89 +theDecoder/theALU/i_0_32/C2->ZN + OAI222_X2_LVT fr 683.5 38.5 38.5 0.0 2.6 0.9 3.3 1 129, 89 +theDecoder/theALU/i_0_31/A->ZN + OAI221_X2_LVT rf 699.6 16.0 16.0 0.0 29.2 0.8 4.0 1 129, 89 +theDecoder/theALU/i_0_28/B1->ZN + AOI21_X4_LVT fr 715.0 15.5 15.5 0.0 8.2 0.8 3.0 1 129, 89 +theDecoder/theALU/i_0_27/A->ZN + AOI221_X2_LVT rf 719.3 4.2 4.2 0.0 13.5 0.9 2.9 1 129, 89 +theDecoder/theALU/i_0_26/B->ZN + AOI211_X2_LVT fr 771.5 52.2 52.2 0.0 5.3 0.8 4.6 1 129, 89 +theDecoder/theALU/i_0_25/B2->ZN + OAI22_X2_LVT rf 781.1 9.7 9.7 0.0 31.8 0.8 2.7 1 129, 89 +theDecoder/theALU/i_0_24/C2->ZN + AOI211_X2_LVT fr 815.5 34.4 34.4 0.0 4.0 0.9 3.1 1 129, 89 +theDecoder/theALU/i_0_23/A->ZN + AOI221_X2_LVT rf 821.3 5.8 5.8 0.0 27.8 0.9 3.1 1 129, 89 +theDecoder/theALU/i_0_22/A->ZN + AOI221_X2_LVT fr 874.9 53.7 53.7 0.0 5.4 0.9 3.1 1 129, 89 +theDecoder/theALU/i_0_21/A->ZN + AOI221_X2_LVT rf 881.0 6.1 6.1 0.0 31.2 0.9 3.1 1 129, 89 +theDecoder/theALU/i_0_20/C2->ZN + OAI222_X2_LVT fr 919.8 38.8 38.8 0.0 5.4 0.9 3.3 1 129, 89 +theDecoder/theALU/i_0_19/A->ZN + OAI221_X2_LVT rf 936.3 16.6 16.6 0.0 29.2 0.9 4.7 1 129, 89 +theDecoder/theALU/i_0_18/B2->ZN + AOI22_X4_LVT fr 966.6 30.3 30.3 0.0 8.6 0.8 4.4 1 129, 89 +theDecoder/theALU/i_0_17/B2->ZN + OAI21_X4_LVT rf 973.1 6.4 6.4 0.0 16.9 0.7 4.3 1 129, 89 +theDecoder/theALU/i_0_16/A->ZN + OAI21_X4_LVT fr 982.8 9.8 9.8 0.0 3.6 0.7 3.9 1 129, 89 +theDecoder/theALU/i_0_13/B1->ZN + AOI21_X4_LVT rf 988.1 5.3 5.3 0.0 12.5 0.8 4.4 1 129, 89 +theDecoder/theALU/i_0_12/A4->ZN + NOR4_X2_LVT fr 1044.5 56.5 56.5 0.0 2.9 0.8 2.8 1 129, 89 +theDecoder/theALU/i_0_0/A3->ZN + OR3_X4_LVT rr 1062.9 18.3 18.3 0.0 29.1 0.7 18.9 2 129, 89 +theDecoder/i_0_114/B->ZN XNOR2_X2_LVT rf 1069.5 6.7 6.7 0.0 9.3 0.7 4.3 1 129, 89 +theDecoder/i_0_113/B1->ZN + AOI22_X4_LVT fr 1096.0 26.5 26.5 0.0 5.1 0.8 4.4 1 129, 89 +theDecoder/i_0_111/A2->ZN + AOI22_X4_LVT rf 1102.4 6.4 6.4 0.0 16.9 0.7 4.3 1 129, 89 +theDecoder/i_0_110/A2->ZN + NAND2_X4_LVT* fr 1121.6 19.2 19.2 0.0 4.4 9.0 37.6 13 129, 89 +i_0_0_60/S->Z MUX2_X2_LVT* rf 1190.2 68.6 68.6 0.0 10.2 32.0 87.6 3 129, 89 +theMem/i_0_0_11/B2->ZN AOI22_X4_LVT* fr 1238.0 47.8 47.8 0.0 10.2 0.7 23.4 1 175, 106 +theMem/i_0_0_10/A->ZN INV_X8_LVT rf 1240.0 2.0 2.0 0.0 10.2 0.7 1.7 1 175, 106 +theMem/mem_addr_reg[5]/D DFF_X1_LVT f 1240.0 0.0 0.0 0.5 175, 106 +-------------------------------------------------------------------------------------------------------------------------------------- +Report for group I2R +Report for group I2O +Report for group R2O +-------------------------------------------------------------------------------------------------------------------------------------- +Startpoint: theMem/IRData_reg[18]/Q + (Clocked by clk_25mhz R) +Endpoint: led[7] + (Clocked by clk_25mhz R) +Path Group: R2O +Data required time: 37500.0 + (Clock shift: 40000.0, minus Uncertainty: 500.0, plus Latency 0.0, minus Out delay: 2000.0) +Data arrival time: 1190.2 +Slack: 36309.8 +Logic depth: 44 +-------------------------------------------------------------------------------------------------------------------------------------- + Arrival Arc Net Net Total fan- +Path Module/Cell Edge Time Delay Delay Delay Slew Load Load out Location + (ps) (ps) (ps) (ps) (ps) (ff) (ff) (#) (um,um) +-------------------------------------------------------------------------------------------------------------------------------------- +clk_25mhz {create_clock} r 0.0 0.0 0.0 0.0 0.0 100 101, 0 +theMem/IRData_reg[18]/CK->Q + DFF_X1_LVT* rr 106.0 106.0 106.0 0.0 100.0 15.2 77.1 10 175, 106 +theRegisters/i_1_0_1371/A->ZN + INV_X8_LVT rf 108.7 2.7 2.7 0.0 10.2 2.1 13.2 3 168, 158 +theRegisters/i_1_0_1339/A2->ZN + NAND3_X4_LVT fr 122.7 14.0 14.0 0.0 1.0 2.5 17.5 4 168, 158 +theRegisters/i_1_0_1321/A2->ZN + NOR2_X4_LVT* rf 141.6 19.0 19.0 0.0 12.1 29.7 130.1 32 168, 158 +theRegisters/i_1_0_722/B1->ZN + AOI22_X4_LVT* fr 186.0 44.3 44.3 0.0 10.2 0.7 23.4 1 168, 158 +theRegisters/i_1_0_721/A->ZN + INV_X8_LVT rf 188.1 2.1 2.1 0.0 10.2 0.8 3.0 1 168, 158 +theRegisters/i_1_0_718/A->ZN + AOI221_X2_LVT fr 245.4 57.3 57.3 0.0 0.6 0.9 4.4 1 168, 158 +theRegisters/i_1_0_716/A3->ZN + NAND4_X4_LVT rf 260.8 15.4 15.4 0.0 34.6 0.9 3.1 1 168, 158 +theRegisters/i_1_0_715/A->ZN + AOI221_X2_LVT fr 318.1 57.4 57.4 0.0 6.8 0.9 4.3 1 168, 158 +theRegisters/i_1_0_704/A2->ZN + NAND4_X4_LVT* rf 342.3 24.2 24.2 0.0 34.4 14.1 24.9 3 168, 158 +theDecoder/i_0_133/C2->ZN + AOI222_X4_LVT fr 452.6 110.3 110.3 0.0 10.2 0.8 23.5 1 129, 89 +theDecoder/i_0_132/A->ZN INV_X32_LVT rf 455.7 3.1 3.1 0.0 10.9 5.4 65.3 7 129, 89 +theDecoder/theALU/i_0_706/B1->ZN + OAI22_X4_LVT* fr 498.9 43.2 43.2 0.0 1.4 1.5 25.9 2 129, 89 +theDecoder/theALU/i_0_705/A->ZN + INV_X8_LVT rf 501.1 2.2 2.2 0.0 10.2 0.6 4.2 1 129, 89 +theDecoder/theALU/i_0_42/A->ZN + OAI21_X2_LVT fr 510.2 9.1 9.1 0.0 0.6 0.8 2.5 1 129, 89 +theDecoder/theALU/i_0_40/C1->ZN + AOI211_X2_LVT rf 515.8 5.6 5.6 0.0 11.6 0.8 2.9 1 129, 89 +theDecoder/theALU/i_0_39/B->ZN + AOI211_X2_LVT fr 563.3 47.4 47.4 0.0 3.3 0.9 3.0 1 129, 89 +theDecoder/theALU/i_0_38/B2->ZN + OAI222_X2_LVT rf 580.2 16.9 16.9 0.0 27.7 0.9 2.9 1 129, 89 +theDecoder/theALU/i_0_37/C2->ZN + AOI221_X2_LVT fr 624.0 43.8 43.8 0.0 8.4 0.9 4.2 1 129, 89 +theDecoder/theALU/i_0_35/B1->ZN + OAI22_X4_LVT* rf 637.9 13.9 13.9 0.0 34.0 0.7 23.4 1 129, 89 +theDecoder/theALU/i_0_34/A->ZN + INV_X8_LVT fr 642.4 4.5 4.5 0.0 10.2 0.6 4.1 1 129, 89 +theDecoder/theALU/i_0_33/A->ZN + AOI21_X4_LVT rf 645.0 2.6 2.6 0.0 2.4 0.8 3.0 1 129, 89 +theDecoder/theALU/i_0_32/C2->ZN + OAI222_X2_LVT fr 683.5 38.5 38.5 0.0 2.6 0.9 3.3 1 129, 89 +theDecoder/theALU/i_0_31/A->ZN + OAI221_X2_LVT rf 699.6 16.0 16.0 0.0 29.2 0.8 4.0 1 129, 89 +theDecoder/theALU/i_0_28/B1->ZN + AOI21_X4_LVT fr 715.0 15.5 15.5 0.0 8.2 0.8 3.0 1 129, 89 +theDecoder/theALU/i_0_27/A->ZN + AOI221_X2_LVT rf 719.3 4.2 4.2 0.0 13.5 0.9 2.9 1 129, 89 +theDecoder/theALU/i_0_26/B->ZN + AOI211_X2_LVT fr 771.5 52.2 52.2 0.0 5.3 0.8 4.6 1 129, 89 +theDecoder/theALU/i_0_25/B2->ZN + OAI22_X2_LVT rf 781.1 9.7 9.7 0.0 31.8 0.8 2.7 1 129, 89 +theDecoder/theALU/i_0_24/C2->ZN + AOI211_X2_LVT fr 815.5 34.4 34.4 0.0 4.0 0.9 3.1 1 129, 89 +theDecoder/theALU/i_0_23/A->ZN + AOI221_X2_LVT rf 821.3 5.8 5.8 0.0 27.8 0.9 3.1 1 129, 89 +theDecoder/theALU/i_0_22/A->ZN + AOI221_X2_LVT fr 874.9 53.7 53.7 0.0 5.4 0.9 3.1 1 129, 89 +theDecoder/theALU/i_0_21/A->ZN + AOI221_X2_LVT rf 881.0 6.1 6.1 0.0 31.2 0.9 3.1 1 129, 89 +theDecoder/theALU/i_0_20/C2->ZN + OAI222_X2_LVT fr 919.8 38.8 38.8 0.0 5.4 0.9 3.3 1 129, 89 +theDecoder/theALU/i_0_19/A->ZN + OAI221_X2_LVT rf 936.3 16.6 16.6 0.0 29.2 0.9 4.7 1 129, 89 +theDecoder/theALU/i_0_18/B2->ZN + AOI22_X4_LVT fr 966.6 30.3 30.3 0.0 8.6 0.8 4.4 1 129, 89 +theDecoder/theALU/i_0_17/B2->ZN + OAI21_X4_LVT rf 973.1 6.4 6.4 0.0 16.9 0.7 4.3 1 129, 89 +theDecoder/theALU/i_0_16/A->ZN + OAI21_X4_LVT fr 982.8 9.8 9.8 0.0 3.6 0.7 3.9 1 129, 89 +theDecoder/theALU/i_0_13/B1->ZN + AOI21_X4_LVT rf 988.1 5.3 5.3 0.0 12.5 0.8 4.4 1 129, 89 +theDecoder/theALU/i_0_12/A4->ZN + NOR4_X2_LVT fr 1044.5 56.5 56.5 0.0 2.9 0.8 2.8 1 129, 89 +theDecoder/theALU/i_0_0/A3->ZN + OR3_X4_LVT rr 1062.9 18.3 18.3 0.0 29.1 0.7 18.9 2 129, 89 +theDecoder/i_0_114/B->ZN XNOR2_X2_LVT rf 1069.5 6.7 6.7 0.0 9.3 0.7 4.3 1 129, 89 +theDecoder/i_0_113/B1->ZN + AOI22_X4_LVT fr 1096.0 26.5 26.5 0.0 5.1 0.8 4.4 1 129, 89 +theDecoder/i_0_111/A2->ZN + AOI22_X4_LVT rf 1102.4 6.4 6.4 0.0 16.9 0.7 4.3 1 129, 89 +theDecoder/i_0_110/A2->ZN + NAND2_X4_LVT* fr 1121.6 19.2 19.2 0.0 4.4 9.0 37.6 13 129, 89 +i_0_0_60/S->Z MUX2_X2_LVT* rf 1190.2 68.6 68.6 0.0 10.2 32.0 87.6 3 129, 89 +led[7] f 1190.2 0.0 0.0 10.2 119, 257 +-------------------------------------------------------------------------------------------------------------------------------------- + +------------------------------------- + + Tessent DFT complete + +------------------------------------- + diff --git a/oasys.log.03 b/oasys.log.03 new file mode 100644 index 0000000..137b777 --- /dev/null +++ b/oasys.log.03 @@ -0,0 +1,2470 @@ +******************************************************************* +* Oasys-RTL™ - release 2022.2.R1 * +* * +* This material contains trade secrets or otherwise confidential * +* information owned by Siemens Industry Software Inc. or its * +* affiliates (collectively, "SISW"), or its licensors. Access to * +* and use of this information is strictly limited as set forth * +* in the Customer’s applicable agreements with SISW. * +* * +* Unpublished work. © 2023 Siemens * +* * +* Program : ../bin/Linux-x86_64-O/oasysGui * +* Version : 22.2-p002 * +* Date : Mon Jan 16 21:36:23 PST 2023 * +* Build : releases/22.2-54756.0-CentOS_6.5-O * +******************************************************************* + config sdc-v1.7-cpd cli cmd explore mxdb o2n fp rta mpg-m-w dft +loading: oa2tessent-d ctl verify edit bt upf-c aos conc ipc-l vcd o2pp prot int oa2ap +checked out license: psyncore + + date : Fri May 29 09:13:55 CEST 2026 + ppid/pid : 2568101/2568111 + hostname : efiapps0.ads1.fh-nuernberg.de + arch/os : x86_64/Linux-4.18.0-553.123.1.el8_10.x86_64 + install : /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1 + currdir : /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock + logfile : /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.log.03 + tmpdir : /tmp/oasys.2568101/ +> source /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/tcl/library/history.tcl +> source scripts_risc_v/1_read_design.tcl +> source scripts_risc_v/init_design.tcl +> config_shell -echo true +> config_report timing -format {cell edge arrival delay arc_delay net_delay slew net_load load fanout location power_domain} +> source scripts_risc_v/demo_chip_design_files.tcl + +----------------------------- + +Done setting design variables + +----------------------------- + +> read_db ./libs/nangate_mvt.odb +info: Reading '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/nangate_mvt.odb' [UFILE-107] + starting at 00:00:00(cpu)/0:00:02(wall) 97MB(vsz)/470MB(peak) +extracting odb ... finished at 00:00:00(cpu)/0:00:03(wall) 97MB(vsz)/470MB(peak) + Write Date : Mon, 21 Jun 2021 13:47:25 -0700 + Host : orw-ericc-r78 (64bit) + Tool Version : 21.1-p004 (60,9-71,11) + Tool Date : Fri Jun 11 12:44:10 PDT 2021 + Tool Build : 52545.0-O + Design Name : + Comment : +loading environment ... finished at 00:00:00(cpu)/0:00:03(wall) 97MB(vsz)/470MB(peak) +loading libraries ... finished at 00:00:01(cpu)/0:00:03(wall) 108MB(vsz)/476MB(peak) +all done +> create_threshold_voltage_group SVT -lib_cells {NangateOpenCellLibrary_45nm_SVT_0p85/AND2_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND2_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND2_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND3_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND3_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND3_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND4_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND4_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND4_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/ANTENNA_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI21_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI21_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI21_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI22_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI22_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI22_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI211_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI211_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI211_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI221_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI221_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI221_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI222_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI222_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI222_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X8_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X16_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X32_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKBUF_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKBUF_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKBUF_X3_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATETST_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATETST_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATETST_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATETST_X8_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATE_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATE_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATE_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATE_X8_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFFRS_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFFRS_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFFR_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFFR_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFFS_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFF_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFF_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DLH_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DLH_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DLL_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DLL_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FA_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X8_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X16_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X32_SVT NangateOpenCellLibrary_45nm_SVT_0p85/HA_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X8_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X16_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X32_SVT NangateOpenCellLibrary_45nm_SVT_0p85/LOGIC0_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/LOGIC1_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/MUX2_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/MUX2_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND2_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND2_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND2_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND3_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND3_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND3_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND4_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND4_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND4_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR2_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR2_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR2_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR3_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR3_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR3_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR4_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR4_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR4_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI21_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI21_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI21_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI22_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI22_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI22_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI33_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI211_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI211_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI211_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI221_X1_SVT ...(34 more)} +> report_operating_conditions +Report Operating conditions: +-----+---------------+--------+-------------+------------------------------------+--------+--------+----------- + |Name |Default?|Type |Library |Process |Voltage |Temperature +-----+---------------+--------+-------------+------------------------------------+--------+--------+----------- +1 |typical | |standard cell|IO |1.000000|1.100000| 27.000000 +2 |TYP | |standard cell|PLL_TYP |1.000000|0.900000| 25.000000 +3 |typical | |standard cell|MemGen_16_10 |1.000000|1.800000| 25.000000 +4 |worst_low_0p85V| |standard cell|NangateOpenCellLibrary_45nm_HVT_0p85|1.000000|0.850000| -40.000000 +5 |worst_low | |standard cell|NangateOpenCellLibrary_45nm_HVT |1.000000|0.950000| -40.000000 +-----+---------------+--------+-------------+------------------------------------+--------+--------+----------- +> config_tolerance -blackbox true -connection_mismatch true -missing_physical_library true -continue_on_error false +> read_verilog -sv {alu.sv cpu.sv decoder.sv MemGen_32_11.sv main_mem.sv pc.sv reg_file.sv} -include ./riscv_rtl/hw/rtl +info: File 'alu.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/./riscv_rtl/hw/rtl/alu.sv' using search_path variable. [CMD-126] +info: File 'cpu.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/./riscv_rtl/hw/rtl/cpu.sv' using search_path variable. [CMD-126] +info: File 'decoder.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/./riscv_rtl/hw/rtl/decoder.sv' using search_path variable. [CMD-126] +info: File 'MemGen_32_11.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/./riscv_rtl/hw/rtl/MemGen_32_11.sv' using search_path variable. [CMD-126] +info: File 'main_mem.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/./riscv_rtl/hw/rtl/main_mem.sv' using search_path variable. [CMD-126] +info: File 'pc.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/./riscv_rtl/hw/rtl/pc.sv' using search_path variable. [CMD-126] +info: File 'reg_file.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/./riscv_rtl/hw/rtl/reg_file.sv' using search_path variable. [CMD-126] +> set_max_route_layer 10 +Top-most available layer for routing set to metal10 +> set_dont_use {IO/PADBID IO/PADCLK PLL_TYP/PLL MemGen_16_10/MemGen_16_10 NangateOpenCellLibrary_45nm_HVT_0p85/AND2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND2_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND3_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND3_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND3_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND4_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND4_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND4_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/ANTENNA_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI21_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI21_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI21_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI22_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI22_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI22_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI211_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI211_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI211_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI221_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI221_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI221_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI222_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI222_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI222_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X16_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X32_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKBUF_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKBUF_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKBUF_X3_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFRS_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFRS_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFR_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFR_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFS_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFS_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFF_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFF_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLH_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLH_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLL_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLL_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FA_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X16_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X32_HVT NangateOpenCellLibrary_45nm_HVT_0p85/HA_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X16_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X32_HVT NangateOpenCellLibrary_45nm_HVT_0p85/LOGIC0_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/LOGIC1_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/MUX2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/MUX2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND2_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND3_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND3_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND3_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND4_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND4_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND4_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR2_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR3_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR3_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR3_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR4_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR4_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR4_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI21_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI21_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI21_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI22_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI22_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI22_X4_HVT ...(306 more)} false + +----------------------------- + +Done preparing design for synthesis + +----------------------------- + +> source scripts_risc_v/2_synthesize_optimize.tcl +> synthesize -module cpu -map_to_scan +starting synthesize at 00:00:01(cpu)/0:00:05(wall) 114MB(vsz)/480MB(peak) +warning: skipping cell ANTENNA_X1_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell FILLCELL_X1_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell FILLCELL_X2_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell FILLCELL_X4_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell FILLCELL_X8_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell FILLCELL_X16_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell FILLCELL_X32_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell LOGIC0_X1_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell LOGIC1_X1_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell ANTENNA_X1_HVT in the library since it does not have delay arcs [NL-215] +-------> Message [NL-215] suppressed 44 times +info: clock-gating cell for posedge FFs = CLKGATE_X1_LVT in target library 'default' [POWER-112] +info: no clock-gating cell found in target library 'default' for negedge FFs for the given specification [POWER-113] +info: clock_gating minimum_width = 4, maximum_fanout = 2147483647, num_stages = 2147483647, sequential_cell = (null), control_port = (null), control_point = none, observability = no, use_discrete_cells = no, create_multi_stage = no, merge_multi_stage = no, exclude_instantiated_clock_gates = no, log = (null), allow_clock_inversion = no [POWER-111] +info: synthesizing module 'cpu' (depth 1) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/cpu.sv:17)[7]) [VLOG-400] +info: synthesizing module 'decoder' (depth 2) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/decoder.sv:17)[7]) [VLOG-400] +info: synthesizing module 'alu' (depth 3) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/alu.sv:16)[7]) [VLOG-400] +info: done synthesizing module 'alu' (depth 3) (1#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/alu.sv:16)[7]) [VLOG-401] +info: done synthesizing module 'decoder' (depth 2) (2#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/decoder.sv:17)[7]) [VLOG-401] +info: synthesizing module 'reg_file' (depth 2) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/reg_file.sv:15)[7]) [VLOG-400] +warning: target library has multiple operating conditions defined, but no default has been set. Assuming default voltage 0.85V, temperature -40.00 and process 1.00 [LIB-218] +info: done synthesizing module 'reg_file' (depth 2) (3#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/reg_file.sv:15)[7]) [VLOG-401] +info: synthesizing module 'pc' (depth 2) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/pc.sv:16)[7]) [VLOG-400] +info: done synthesizing module 'pc' (depth 2) (4#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/pc.sv:16)[7]) [VLOG-401] +info: synthesizing module 'main_mem' (depth 2) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:18)[7]) [VLOG-400] +info: synthesizing module 'MemGen_32_11' (depth 3) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/MemGen_32_11.sv:1)[7]) [VLOG-400] +info: done synthesizing module 'MemGen_32_11' (depth 3) (5#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/MemGen_32_11.sv:1)[7]) [VLOG-401] +warning: always_comb on 'DRData' did not result in combinational logic ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:110)[8], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:113)[16], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:114)[16], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:118)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:119)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:120)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:121)[17]) [SYN-112] +warning: inferring latch for variable 'DRData' ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:110)[8], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:113)[16], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:114)[16], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:118)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:119)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:120)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:121)[17]) [VLOG-566] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +-------> Message [POWER-102] suppressed 22 times +info: done synthesizing module 'main_mem' (depth 2) (6#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/main_mem.sv:18)[7]) [VLOG-401] +info: done synthesizing module 'cpu' (depth 1) (7#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/riscv_rtl/hw/rtl/cpu.sv:17)[7]) [VLOG-401] +finished synthesize at 00:00:02(cpu)/0:00:06(wall) 167MB(vsz)/530MB(peak) +> set_route_layer_max_usage metal2 0.5 +> set_route_layer_max_usage metal3 0.8 +> set_route_layer_max_usage metal6 0.8 +> write_db ./output/odb/riscv_chip.syn.odb +info: design 'cpu' has no physical info [WRITE-120] +warning: WrSdc.. design 'cpu' has no timing constraints [TA-118] +> read_sdc -verbose ./constraints/riscv.sdc +> create_clock -name clk_25mhz -period 40.000 -waveform { 0 20 } clk_25mhz +> set_clock_uncertainty -setup 0.5 clk_25mhz +> set_clock_uncertainty -hold 0.2 clk_25mhz +> set_clock_transition 0.1 clk_25mhz +> set_input_delay -clock clk_25mhz -max 2.0 { btn[6] btn[5] btn[4] btn[3] btn[2] btn[1] btn[0] } +> set_input_delay -clock clk_25mhz -min 0.5 { btn[6] btn[5] btn[4] btn[3] btn[2] btn[1] btn[0] } +> set_output_delay -clock clk_25mhz -max 2.0 { led[7] led[6] led[5] led[4] led[3] led[2] led[1] led[0] } +> set_output_delay -clock clk_25mhz -min 0.5 { led[7] led[6] led[5] led[4] led[3] led[2] led[1] led[0] } +> set_false_path -from btn[0] +# set_false_path -from btn[0] +> set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 { btn[6] btn[5] btn[4] btn[3] btn[2] btn[1] btn[0] } +> set_load 0.05 { led[7] led[6] led[5] led[4] led[3] led[2] led[1] led[0] } +> current_design +> set_max_fanout 20 cpu +> current_design +> set_max_transition 0.5 cpu +info: 'set_max_fanout' command ignored 1 time(s) [SDC-148] +info: 'set_max_transition' command ignored 1 time(s) [SDC-150] +> report_design_metrics +Report Physical info: +------------------------+--------+-----------+------------ + | |Area (squm)|Leakage (uW) +------------------------+--------+-----------+------------ +Design Name |cpu | | + Total Instances | 7261| 60155| 625.778 + Macros | 4| 46249| 518.216 + Pads | 0| 0| 0.000 + Phys | 0| 0| 0.000 + Blackboxes | 0| 0| 0.000 + Cells | 7257| 13906| 107.562 + Buffers | 0| 0| 0.000 + Inverters | 640| 340| 4.488 + Clock-Gates | 31| 107| 0.667 + Combinational | 5423| 6454| 51.129 + Latches | 32| 85| 0.602 + FlipFlops | 1131| 6919| 50.677 + Single-Bit FF | 1131| 6919| 50.677 + Multi-Bit FF | 0| 0| 0.000 + Clock-Gated | 992| | + Bits | 1131| 6919| 50.677 + Load-Enabled | 0| | + Clock-Gated | 992| | + Tristate Pin Count | 0| | +Physical Info |Unplaced| | + Chip Size (mm x mm) | | 0| + Fixed Cell Area | | 0| + Phys Only | 0| 0| + Placeable Area | | 0| + Movable Cell Area | | 60155| + Utilization (%) | | | + Chip Utilization (%) | | | + Total Wire Length (mm)| 0.000| | + Longest Wire (mm) | | | + Average Wire (mm) | | | +------------------------+--------+-----------+------------ +> check_timing +Report Check Timing: +-----+------------------------------+------+--------+------+----------------------------------------------- + |Item |Errors|Warnings|Status|Description +-----+------------------------------+------+--------+------+----------------------------------------------- +1 |no_clock_defined | 0| 0|Passed|No clock is defined in the design +2 |invalid_generated_clock | 0| 0|Passed|Generated clock is not sourced by a valid clock +3 |unconstrained_IO | 0| 0|Passed|Unconstrained IO pin +4 |unexpected_assertion | 0| 0|Passed|Found unexpected timing assertion +5 |trigger_pin_without_required | 0| 32|Passed|Trigger pin does not get required data +6 |setup_pin_without_data | 0| 0|Passed|Setup pin does not get arriving data +7 |setup_pin_with_clock | 0| 0|Passed|Setup pin has clock signal arriving +8 |clock_pin_with_multiple_clocks| 0| 0|Passed|Clock pin has multiple clock signals +9 |clock_pin_without_clock | 0| 1|Passed|Clock pin does not have clock signal +10 |clock_pin_with_data | 0| 1|Passed|Clock pin has data signal arriving +-----+------------------------------+------+--------+------+----------------------------------------------- +> all_inputs +> group_path -name I2R -from { btn[6] btn[5] btn[4] btn[3] btn[2] btn[1] btn[0] clk_25mhz } +# group_path -from {btn[6]} {btn[5]} {btn[4]} {btn[3]} {btn[2]} {btn[1]} {btn[0]} clk_25mhz +> all_inputs +> all_outputs +> group_path -name I2O -from { btn[6] btn[5] btn[4] btn[3] btn[2] btn[1] btn[0] clk_25mhz } -to { led[7] led[6] led[5] led[4] led[3] led[2] led[1] led[0] } +# group_path -from {btn[6]} {btn[5]} {btn[4]} {btn[3]} {btn[2]} {btn[1]} {btn[0]} clk_25mhz -to {led[7]} {led[6]} {led[5]} {led[4]} {led[3]} {led[2]} {led[1]} {led[0]} +> all_outputs +> group_path -name R2O -to { led[7] led[6] led[5] led[4] led[3] led[2] led[1] led[0] } +# group_path -to {led[7]} {led[6]} {led[5]} {led[4]} {led[3]} {led[2]} {led[1]} {led[0]} +> report_path_groups +Report Path Groups: +-----+-------+------+---------+--------- + | Path |Weight|Critical |Worst + | Group | |Range(ps)|Slack(ps) +-----+-------+------+---------+--------- +1 |default| 1.000| 0.0| 17832.1 +2 |I2R | 1.000| 0.0| +3 |I2O | 1.000| 0.0| +4 |R2O | 1.000| 0.0| 36153.7 +-----+-------+------+---------+--------- +> optimize -virtual +starting optimize at 00:00:03(cpu)/0:00:07(wall) 174MB(vsz)/530MB(peak) +info: mapped 0 flop(s) to scan cells, excluded 0 is_dont_scan flop(s) and 0 is_dont_touch flop(s) +Log file for child PID=2568141: /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.etc.03/oasys.w1.03.log +Log file for child PID=2568145: /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.etc.03/oasys.w2.03.log +Log file for child PID=2568152: /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.etc.03/oasys.w3.03.log +Log file for child PID=2568158: /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.etc.03/oasys.w4.03.log +info: optimized '' area changed 0.0squm (x1), total 13904.4squm (#1, 0 secs) +info: dissolving instance 'thePC' of module 'pc' in module 'cpu__GC0' [NL-146] +info: optimized 'cpu__GC0' area changed -1457.9squm (x1), total 12446.4squm (#2) +info: optimized 'reg_file__GB1' area changed -841.1squm (x1), total 11605.3squm (#3) +info: optimized 'reg_file__always' area changed -83.5squm (x1), total 11521.8squm (#4) +info: optimized 'main_mem__GC0' area changed -90.4squm (x1), total 11431.3squm (#5) +info: optimized 'MemGen_32_11__block' area changed -2.4squm (x1), total 11429.0squm (#6) +info: optimized '' area changed 0.0squm (x1), total 11429.0squm (#7, 0 secs) +info: optimized 'cpu__GC0' area changed 0.0squm (x1), total 11429.0squm (#8) +info: optimized 'MemGen_32_11__block' area changed 0.0squm (x1), total 11429.0squm (#9) +info: optimized '' area changed 0.0squm (x1), total 11429.0squm (#10, 0 secs) +done optimizing area at 00:00:15(cpu)/0:00:14(wall) 176MB(vsz)/566MB(peak) +Splitting congested rtl-partitions +info: Target library/cell information has changed that further may change timing results. [TA-159] +info: optimizing design 'cpu' - propagating constants +info: optimized '' area changed 0.0squm (x1), total 11429.0squm (#1, 0 secs) +info: set slack mode to optimize shift +info: resetting all path groups +info: activated path group default @ 18015.8ps +info: suspended path group I2R @ ps +info: suspended path group I2O @ ps +info: activated path group R2O @ 36338.3ps +info: finished path group default @ 18015.8ps +info: finished path group R2O @ 36338.3ps +info: reactivating path groups +info: reactivated path group default @ 18015.8ps +info: reactivated path group R2O @ 36338.3ps +info: finished path group default @ 18015.8ps +info: finished path group R2O @ 36338.3ps +info: set slack mode to normal +info: done with all path groups +info: restore all path groups +info: starting area recovery on module cpu +info: optimized 'cpu__GC0' area recovered 0.00squm (x1), total 0.00squm (1#5), 0.04 secs +info: optimized 'main_mem__GC0' area recovered 0.00squm (x1), total 0.00squm (2#5), 0.04 secs +info: optimized 'MemGen_32_11__block' area recovered 0.00squm (x1), total 0.00squm (3#5), 0.00 secs +info: optimized 'reg_file__always' area recovered 0.00squm (x1), total 0.00squm (4#5), 0.00 secs +info: optimized 'reg_file__GB1' area recovered 0.00squm (x1), total 0.00squm (5#5), 0.02 secs +info: area recovery done, total area reduction: 0.00squm (0.00%), final slack: 18015.8ps (delta: 0.0ps) (0 secs) +done optimizing virtual at 00:00:16(cpu)/0:00:15(wall) 194MB(vsz)/566MB(peak) +finished optimize at 00:00:16(cpu)/0:00:15(wall) 194MB(vsz)/566MB(peak) +> write_db ./output/odb/riscv_chip.virtual_opt.odb +> report_timing +Report for group default +-------------------------------------------------------------------------------------------------------------------------------------- +Startpoint: theMem/IRData_reg[18]/Q + (Clocked by clk_25mhz R) +Endpoint: theMem/mem_addr_reg[5]/D + (Clocked by clk_25mhz F) +Path Group: default +Data required time: 19227.4 + (Clock shift: 20000.0, minus Uncertainty: 500.0, plus Latency 0.0, minus Setup time: 272.6) +Data arrival time: 1211.5 +Slack: 18015.8 +Logic depth: 46 +-------------------------------------------------------------------------------------------------------------------------------------- + Arrival Arc Net Net Total fan- +Path Module/Cell Edge Time Delay Delay Delay Slew Load Load out Location + (ps) (ps) (ps) (ps) (ps) (ff) (ff) (#) (um,um) +-------------------------------------------------------------------------------------------------------------------------------------- +clk_25mhz {create_clock} r 0.0 0.0 0.0 0.0 0.0 100 +theMem/IRData_reg[18]/CK->Q + SDFF_X1_LVT* rr 84.9 84.9 84.9 0.0 100.0 10.6 73.4 11 +theRegisters/i_1_0_1371/A->ZN + INV_X8_LVT rf 87.6 2.7 2.7 0.0 10.2 2.1 13.2 3 +theRegisters/i_1_0_1339/A2->ZN + NAND3_X4_LVT fr 101.6 14.0 14.0 0.0 1.0 2.5 17.5 4 +theRegisters/i_1_0_1321/A2->ZN + NOR2_X4_LVT* rf 120.6 19.0 19.0 0.0 12.1 29.7 130.1 32 +theRegisters/i_1_0_722/B1->ZN + AOI22_X4_LVT* fr 164.9 44.3 44.3 0.0 10.2 0.7 23.4 1 +theRegisters/i_1_0_721/A->ZN + INV_X8_LVT rf 167.0 2.1 2.1 0.0 10.2 0.8 3.0 1 +theRegisters/i_1_0_718/A->ZN + AOI221_X2_LVT fr 224.3 57.3 57.3 0.0 0.6 0.9 4.4 1 +theRegisters/i_1_0_716/A3->ZN + NAND4_X4_LVT rf 239.7 15.4 15.4 0.0 34.6 0.9 3.1 1 +theRegisters/i_1_0_715/A->ZN + AOI221_X2_LVT fr 297.1 57.4 57.4 0.0 6.8 0.9 4.3 1 +theRegisters/i_1_0_704/A2->ZN + NAND4_X4_LVT rf 317.6 20.5 20.5 0.0 34.4 5.9 16.7 3 +theDecoder/i_0_133/C2->ZN + AOI222_X4_LVT fr 428.0 110.5 110.5 0.0 12.2 0.8 23.5 1 +theDecoder/i_0_132/A->ZN INV_X32_LVT rf 431.2 3.1 3.1 0.0 10.9 5.4 65.3 7 +theDecoder/theALU/i_0_706/B1->ZN + OAI22_X4_LVT* fr 474.4 43.2 43.2 0.0 1.4 1.5 25.9 2 +theDecoder/theALU/i_0_705/A->ZN + INV_X8_LVT rf 476.5 2.2 2.2 0.0 10.2 0.6 4.2 1 +theDecoder/theALU/i_0_42/A->ZN + OAI21_X2_LVT fr 485.6 9.1 9.1 0.0 0.6 0.8 2.5 1 +theDecoder/theALU/i_0_40/C1->ZN + AOI211_X2_LVT rf 491.3 5.6 5.6 0.0 11.6 0.8 2.9 1 +theDecoder/theALU/i_0_39/B->ZN + AOI211_X2_LVT fr 538.7 47.4 47.4 0.0 3.3 0.9 3.0 1 +theDecoder/theALU/i_0_38/B2->ZN + OAI222_X2_LVT rf 555.6 16.9 16.9 0.0 27.7 0.9 2.9 1 +theDecoder/theALU/i_0_37/C2->ZN + AOI221_X2_LVT fr 599.5 43.8 43.8 0.0 8.4 0.9 4.2 1 +theDecoder/theALU/i_0_35/B1->ZN + OAI22_X4_LVT* rf 613.4 13.9 13.9 0.0 34.0 0.7 23.4 1 +theDecoder/theALU/i_0_34/A->ZN + INV_X8_LVT fr 617.9 4.5 4.5 0.0 10.2 0.6 4.1 1 +theDecoder/theALU/i_0_33/A->ZN + AOI21_X4_LVT rf 620.5 2.6 2.6 0.0 2.4 0.8 3.0 1 +theDecoder/theALU/i_0_32/C2->ZN + OAI222_X2_LVT fr 659.0 38.5 38.5 0.0 2.6 0.9 3.3 1 +theDecoder/theALU/i_0_31/A->ZN + OAI221_X2_LVT rf 675.0 16.0 16.0 0.0 29.2 0.8 4.0 1 +theDecoder/theALU/i_0_28/B1->ZN + AOI21_X4_LVT fr 690.5 15.5 15.5 0.0 8.2 0.8 3.0 1 +theDecoder/theALU/i_0_27/A->ZN + AOI221_X2_LVT rf 694.7 4.2 4.2 0.0 13.5 0.9 2.9 1 +theDecoder/theALU/i_0_26/B->ZN + AOI211_X2_LVT fr 746.9 52.2 52.2 0.0 5.3 0.8 4.6 1 +theDecoder/theALU/i_0_25/B2->ZN + OAI22_X2_LVT rf 756.6 9.7 9.7 0.0 31.8 0.8 2.7 1 +theDecoder/theALU/i_0_24/C2->ZN + AOI211_X2_LVT fr 791.0 34.4 34.4 0.0 4.0 0.9 3.1 1 +theDecoder/theALU/i_0_23/A->ZN + AOI221_X2_LVT rf 796.7 5.8 5.8 0.0 27.8 0.9 3.1 1 +theDecoder/theALU/i_0_22/A->ZN + AOI221_X2_LVT fr 850.4 53.7 53.7 0.0 5.4 0.9 3.1 1 +theDecoder/theALU/i_0_21/A->ZN + AOI221_X2_LVT rf 856.5 6.1 6.1 0.0 31.2 0.9 3.1 1 +theDecoder/theALU/i_0_20/C2->ZN + OAI222_X2_LVT fr 895.2 38.8 38.8 0.0 5.4 0.9 3.3 1 +theDecoder/theALU/i_0_19/A->ZN + OAI221_X2_LVT rf 911.8 16.6 16.6 0.0 29.2 0.9 4.7 1 +theDecoder/theALU/i_0_18/B2->ZN + AOI22_X4_LVT fr 942.1 30.3 30.3 0.0 8.6 0.8 4.4 1 +theDecoder/theALU/i_0_17/B2->ZN + OAI21_X4_LVT rf 948.5 6.4 6.4 0.0 16.9 0.7 4.3 1 +theDecoder/theALU/i_0_16/A->ZN + OAI21_X4_LVT fr 958.3 9.8 9.8 0.0 3.6 0.7 3.9 1 +theDecoder/theALU/i_0_13/B1->ZN + AOI21_X4_LVT rf 963.5 5.3 5.3 0.0 12.5 0.8 4.4 1 +theDecoder/theALU/i_0_12/A4->ZN + NOR4_X2_LVT fr 1020.0 56.5 56.5 0.0 2.9 0.8 2.8 1 +theDecoder/theALU/i_0_0/A3->ZN + OR3_X4_LVT rr 1036.6 16.6 16.6 0.0 29.1 0.7 14.7 2 +theDecoder/i_0_114/B->ZN XNOR2_X2_LVT rf 1043.2 6.5 6.5 0.0 7.8 0.7 4.3 1 +theDecoder/i_0_113/B1->ZN + AOI22_X4_LVT fr 1069.7 26.5 26.5 0.0 5.1 0.8 4.4 1 +theDecoder/i_0_111/A2->ZN + AOI22_X4_LVT rf 1076.1 6.4 6.4 0.0 16.9 0.7 4.3 1 +theDecoder/i_0_110/A2->ZN + NAND2_X4_LVT* fr 1095.3 19.2 19.2 0.0 4.4 9.0 37.6 13 +i_0_0_60/S->Z MUX2_X2_LVT* rf 1161.7 66.4 66.4 0.0 10.2 11.1 66.7 3 +theMem/i_0_0_11/B2->ZN AOI22_X4_LVT* fr 1209.5 47.8 47.8 0.0 10.2 0.7 23.4 1 +theMem/i_0_0_10/A->ZN INV_X8_LVT rf 1211.5 2.0 2.0 0.0 10.2 0.8 1.8 1 +theMem/mem_addr_reg[5]/D SDFF_X1_LVT f 1211.5 0.0 0.0 0.5 +-------------------------------------------------------------------------------------------------------------------------------------- +Report for group I2R +Report for group I2O +Report for group R2O +-------------------------------------------------------------------------------------------------------------------------------------- +Startpoint: theMem/IRData_reg[18]/Q + (Clocked by clk_25mhz R) +Endpoint: led[7] + (Clocked by clk_25mhz R) +Path Group: R2O +Data required time: 37500.0 + (Clock shift: 40000.0, minus Uncertainty: 500.0, plus Latency 0.0, minus Out delay: 2000.0) +Data arrival time: 1161.7 +Slack: 36338.3 +Logic depth: 44 +-------------------------------------------------------------------------------------------------------------------------------------- + Arrival Arc Net Net Total fan- +Path Module/Cell Edge Time Delay Delay Delay Slew Load Load out Location + (ps) (ps) (ps) (ps) (ps) (ff) (ff) (#) (um,um) +-------------------------------------------------------------------------------------------------------------------------------------- +clk_25mhz {create_clock} r 0.0 0.0 0.0 0.0 0.0 100 +theMem/IRData_reg[18]/CK->Q + SDFF_X1_LVT* rr 84.9 84.9 84.9 0.0 100.0 10.6 73.4 11 +theRegisters/i_1_0_1371/A->ZN + INV_X8_LVT rf 87.6 2.7 2.7 0.0 10.2 2.1 13.2 3 +theRegisters/i_1_0_1339/A2->ZN + NAND3_X4_LVT fr 101.6 14.0 14.0 0.0 1.0 2.5 17.5 4 +theRegisters/i_1_0_1321/A2->ZN + NOR2_X4_LVT* rf 120.6 19.0 19.0 0.0 12.1 29.7 130.1 32 +theRegisters/i_1_0_722/B1->ZN + AOI22_X4_LVT* fr 164.9 44.3 44.3 0.0 10.2 0.7 23.4 1 +theRegisters/i_1_0_721/A->ZN + INV_X8_LVT rf 167.0 2.1 2.1 0.0 10.2 0.8 3.0 1 +theRegisters/i_1_0_718/A->ZN + AOI221_X2_LVT fr 224.3 57.3 57.3 0.0 0.6 0.9 4.4 1 +theRegisters/i_1_0_716/A3->ZN + NAND4_X4_LVT rf 239.7 15.4 15.4 0.0 34.6 0.9 3.1 1 +theRegisters/i_1_0_715/A->ZN + AOI221_X2_LVT fr 297.1 57.4 57.4 0.0 6.8 0.9 4.3 1 +theRegisters/i_1_0_704/A2->ZN + NAND4_X4_LVT rf 317.6 20.5 20.5 0.0 34.4 5.9 16.7 3 +theDecoder/i_0_133/C2->ZN + AOI222_X4_LVT fr 428.0 110.5 110.5 0.0 12.2 0.8 23.5 1 +theDecoder/i_0_132/A->ZN INV_X32_LVT rf 431.2 3.1 3.1 0.0 10.9 5.4 65.3 7 +theDecoder/theALU/i_0_706/B1->ZN + OAI22_X4_LVT* fr 474.4 43.2 43.2 0.0 1.4 1.5 25.9 2 +theDecoder/theALU/i_0_705/A->ZN + INV_X8_LVT rf 476.5 2.2 2.2 0.0 10.2 0.6 4.2 1 +theDecoder/theALU/i_0_42/A->ZN + OAI21_X2_LVT fr 485.6 9.1 9.1 0.0 0.6 0.8 2.5 1 +theDecoder/theALU/i_0_40/C1->ZN + AOI211_X2_LVT rf 491.3 5.6 5.6 0.0 11.6 0.8 2.9 1 +theDecoder/theALU/i_0_39/B->ZN + AOI211_X2_LVT fr 538.7 47.4 47.4 0.0 3.3 0.9 3.0 1 +theDecoder/theALU/i_0_38/B2->ZN + OAI222_X2_LVT rf 555.6 16.9 16.9 0.0 27.7 0.9 2.9 1 +theDecoder/theALU/i_0_37/C2->ZN + AOI221_X2_LVT fr 599.5 43.8 43.8 0.0 8.4 0.9 4.2 1 +theDecoder/theALU/i_0_35/B1->ZN + OAI22_X4_LVT* rf 613.4 13.9 13.9 0.0 34.0 0.7 23.4 1 +theDecoder/theALU/i_0_34/A->ZN + INV_X8_LVT fr 617.9 4.5 4.5 0.0 10.2 0.6 4.1 1 +theDecoder/theALU/i_0_33/A->ZN + AOI21_X4_LVT rf 620.5 2.6 2.6 0.0 2.4 0.8 3.0 1 +theDecoder/theALU/i_0_32/C2->ZN + OAI222_X2_LVT fr 659.0 38.5 38.5 0.0 2.6 0.9 3.3 1 +theDecoder/theALU/i_0_31/A->ZN + OAI221_X2_LVT rf 675.0 16.0 16.0 0.0 29.2 0.8 4.0 1 +theDecoder/theALU/i_0_28/B1->ZN + AOI21_X4_LVT fr 690.5 15.5 15.5 0.0 8.2 0.8 3.0 1 +theDecoder/theALU/i_0_27/A->ZN + AOI221_X2_LVT rf 694.7 4.2 4.2 0.0 13.5 0.9 2.9 1 +theDecoder/theALU/i_0_26/B->ZN + AOI211_X2_LVT fr 746.9 52.2 52.2 0.0 5.3 0.8 4.6 1 +theDecoder/theALU/i_0_25/B2->ZN + OAI22_X2_LVT rf 756.6 9.7 9.7 0.0 31.8 0.8 2.7 1 +theDecoder/theALU/i_0_24/C2->ZN + AOI211_X2_LVT fr 791.0 34.4 34.4 0.0 4.0 0.9 3.1 1 +theDecoder/theALU/i_0_23/A->ZN + AOI221_X2_LVT rf 796.7 5.8 5.8 0.0 27.8 0.9 3.1 1 +theDecoder/theALU/i_0_22/A->ZN + AOI221_X2_LVT fr 850.4 53.7 53.7 0.0 5.4 0.9 3.1 1 +theDecoder/theALU/i_0_21/A->ZN + AOI221_X2_LVT rf 856.5 6.1 6.1 0.0 31.2 0.9 3.1 1 +theDecoder/theALU/i_0_20/C2->ZN + OAI222_X2_LVT fr 895.2 38.8 38.8 0.0 5.4 0.9 3.3 1 +theDecoder/theALU/i_0_19/A->ZN + OAI221_X2_LVT rf 911.8 16.6 16.6 0.0 29.2 0.9 4.7 1 +theDecoder/theALU/i_0_18/B2->ZN + AOI22_X4_LVT fr 942.1 30.3 30.3 0.0 8.6 0.8 4.4 1 +theDecoder/theALU/i_0_17/B2->ZN + OAI21_X4_LVT rf 948.5 6.4 6.4 0.0 16.9 0.7 4.3 1 +theDecoder/theALU/i_0_16/A->ZN + OAI21_X4_LVT fr 958.3 9.8 9.8 0.0 3.6 0.7 3.9 1 +theDecoder/theALU/i_0_13/B1->ZN + AOI21_X4_LVT rf 963.5 5.3 5.3 0.0 12.5 0.8 4.4 1 +theDecoder/theALU/i_0_12/A4->ZN + NOR4_X2_LVT fr 1020.0 56.5 56.5 0.0 2.9 0.8 2.8 1 +theDecoder/theALU/i_0_0/A3->ZN + OR3_X4_LVT rr 1036.6 16.6 16.6 0.0 29.1 0.7 14.7 2 +theDecoder/i_0_114/B->ZN XNOR2_X2_LVT rf 1043.2 6.5 6.5 0.0 7.8 0.7 4.3 1 +theDecoder/i_0_113/B1->ZN + AOI22_X4_LVT fr 1069.7 26.5 26.5 0.0 5.1 0.8 4.4 1 +theDecoder/i_0_111/A2->ZN + AOI22_X4_LVT rf 1076.1 6.4 6.4 0.0 16.9 0.7 4.3 1 +theDecoder/i_0_110/A2->ZN + NAND2_X4_LVT* fr 1095.3 19.2 19.2 0.0 4.4 9.0 37.6 13 +i_0_0_60/S->Z MUX2_X2_LVT* rf 1161.7 66.4 66.4 0.0 10.2 11.1 66.7 3 +led[7] f 1161.7 0.0 0.0 10.2 +-------------------------------------------------------------------------------------------------------------------------------------- +> report_path_groups +Report Path Groups: +-----+-------+------+---------+--------- + | Path |Weight|Critical |Worst + | Group | |Range(ps)|Slack(ps) +-----+-------+------+---------+--------- +1 |default| 1.000| 0.0| 18015.8 +2 |I2R | 1.000| 0.0| +3 |I2O | 1.000| 0.0| +4 |R2O | 1.000| 0.0| 36338.3 +-----+-------+------+---------+--------- + +------------------------------------- + +Synthesis and optimization complete + +------------------------------------- + +INFO::Running oasys Tessent DFT flow +> source scripts_risc_v/oasys_tessent_dft.tcl +INFO::using /applications/SiemensEDA/siemenseda2023/tessent/bin/tessent build to run the Tessent DFT flow +> config_tessent -exec_path /applications/SiemensEDA/siemenseda2023/tessent/bin/tessent +> define_test_clock -pin clk_25mhz +> define_test_pin -pin scan_en -scan_mode 1 -default_scan_enable -create_port +Adding Test pin scan_en to top Module +> set_dont_scan theMem true +> define_test_pin -name reset -pin {btn[0]} -scan_mode 1 +> check_dft -auto_test_clock -auto_test_pins +starting check_dft at 00:00:16(cpu)/0:00:15(wall) 194MB(vsz)/566MB(peak) +Checking DFT rules for 'cpu' + Running DFT TDRC iteration 1 + Total 1131 scanModels/flops with 12% scanable (139 pass, 992 fail, 0 nonScan or excludeScan) +Report Check DFT: +-----+---------------------+------+--------+------+------------------------------------------- + |Item |Errors|Warnings|Status|Description +-----+---------------------+------+--------+------+------------------------------------------- +1 |internal_clock | 0| 0|Passed|Internal Clock +2 |constant_clock | 0| 0|Passed|Constant Clock +3 |non_clock_PI | 0| 0|Passed|Non-Clock PI +4 |blocking_clock_gate | 0| 31|Failed|Blocking clock gate +5 |internal_async | 0| 0|Passed|Internal Async. Set/Reset control +6 |constant_active_async| 0| 0|Passed|Constant active Async. Set/Reset signal +7 |non_test_PI | 0| 0|Passed|Unconstrained PI driving Async/ Set/Reset +8 |async_clock_conflict | 0| 0|Passed|Async. Set/Reset signal and Clock conflict +9 |parallel_scan_clock | 0| 0|Passed|Clock pin of unsupported parallel-scan flop +-----+---------------------+------+--------+------+------------------------------------------- +Design has 31 DFT violation(s) +finished check_dft at 00:00:17(cpu)/0:00:15(wall) 194MB(vsz)/566MB(peak) +> write_db ./output/odb/riscv.tessent_pre_fix.odb +> fix_dft_violations -type all -test_clock clk_25mhz -test_control scan_en +Created 0 gates to fix Async violation(s) +Created 0 muxes to fix clock violation(s) +Replaced 31 clock-gating cells to fix clock-gating violation(s) +> report_dft_violations +Report DftViolations: +-----+-------------------+-----------------------------------------------+-------------------- + | Type | Pin | Affected Registers +-----+-------------------+-----------------------------------------------+-------------------- +1 |blocking clock gate|theRegisters/clk_gate_registers_reg[1]_reg/GCK | 32 +2 |blocking clock gate|theRegisters/clk_gate_registers_reg[2]_reg/GCK | 32 +3 |blocking clock gate|theRegisters/clk_gate_registers_reg[3]_reg/GCK | 32 +4 |blocking clock gate|theRegisters/clk_gate_registers_reg[4]_reg/GCK | 32 +5 |blocking clock gate|theRegisters/clk_gate_registers_reg[5]_reg/GCK | 32 +6 |blocking clock gate|theRegisters/clk_gate_registers_reg[6]_reg/GCK | 32 +7 |blocking clock gate|theRegisters/clk_gate_registers_reg[7]_reg/GCK | 32 +8 |blocking clock gate|theRegisters/clk_gate_registers_reg[8]_reg/GCK | 32 +9 |blocking clock gate|theRegisters/clk_gate_registers_reg[9]_reg/GCK | 32 +10 |blocking clock gate|theRegisters/clk_gate_registers_reg[10]_reg/GCK| 32 +11 |blocking clock gate|theRegisters/clk_gate_registers_reg[11]_reg/GCK| 32 +12 |blocking clock gate|theRegisters/clk_gate_registers_reg[12]_reg/GCK| 32 +13 |blocking clock gate|theRegisters/clk_gate_registers_reg[13]_reg/GCK| 32 +14 |blocking clock gate|theRegisters/clk_gate_registers_reg[14]_reg/GCK| 32 +15 |blocking clock gate|theRegisters/clk_gate_registers_reg[15]_reg/GCK| 32 +16 |blocking clock gate|theRegisters/clk_gate_registers_reg[16]_reg/GCK| 32 +17 |blocking clock gate|theRegisters/clk_gate_registers_reg[17]_reg/GCK| 32 +18 |blocking clock gate|theRegisters/clk_gate_registers_reg[18]_reg/GCK| 32 +19 |blocking clock gate|theRegisters/clk_gate_registers_reg[19]_reg/GCK| 32 +20 |blocking clock gate|theRegisters/clk_gate_registers_reg[20]_reg/GCK| 32 +21 |blocking clock gate|theRegisters/clk_gate_registers_reg[21]_reg/GCK| 32 +22 |blocking clock gate|theRegisters/clk_gate_registers_reg[22]_reg/GCK| 32 +23 |blocking clock gate|theRegisters/clk_gate_registers_reg[23]_reg/GCK| 32 +24 |blocking clock gate|theRegisters/clk_gate_registers_reg[24]_reg/GCK| 32 +25 |blocking clock gate|theRegisters/clk_gate_registers_reg[25]_reg/GCK| 32 +26 |blocking clock gate|theRegisters/clk_gate_registers_reg[26]_reg/GCK| 32 +27 |blocking clock gate|theRegisters/clk_gate_registers_reg[27]_reg/GCK| 32 +28 |blocking clock gate|theRegisters/clk_gate_registers_reg[28]_reg/GCK| 32 +29 |blocking clock gate|theRegisters/clk_gate_registers_reg[29]_reg/GCK| 32 +30 |blocking clock gate|theRegisters/clk_gate_registers_reg[30]_reg/GCK| 32 +31 |blocking clock gate|theRegisters/clk_gate_registers_reg[31]_reg/GCK| 32 +-----+-------------------+-----------------------------------------------+-------------------- +> optimize +starting optimize at 00:00:17(cpu)/0:00:16(wall) 194MB(vsz)/566MB(peak) +info: mapped 107 flop(s) to scan cells, excluded 107 is_dont_scan flop(s) and 0 is_dont_touch flop(s) +info: Target library/cell information has changed that further may change timing results. [TA-159] +info: optimizing design 'cpu' - propagating constants +info: optimized '' area changed 0.0squm (x1), total 11274.7squm (#1, 0 secs) +info: set slack mode to optimize shift +info: resetting all path groups +info: activated path group default @ 18139.2ps +info: suspended path group I2R @ ps +info: suspended path group I2O @ ps +info: activated path group R2O @ 36317.8ps +info: finished path group default @ 18139.2ps +info: finished path group R2O @ 36317.8ps +info: reactivating path groups +info: reactivated path group default @ 18139.2ps +info: reactivated path group R2O @ 36317.8ps +info: finished path group default @ 18139.2ps +info: finished path group R2O @ 36317.8ps +info: set slack mode to normal +info: done with all path groups +info: restore all path groups +info: starting area recovery on module cpu +info: optimized 'cpu__GC0' area recovered 0.00squm (x1), total 0.00squm (1#5), 0.03 secs +info: optimized 'main_mem__GC0' area recovered 0.00squm (x1), total 0.00squm (2#5), 0.05 secs +info: optimized 'MemGen_32_11__block' area recovered 0.00squm (x1), total 0.00squm (3#5), 0.00 secs +info: optimized 'reg_file__always' area recovered 0.00squm (x1), total 0.00squm (4#5), 0.01 secs +info: optimized 'reg_file__GB1' area recovered 0.00squm (x1), total 0.00squm (5#5), 0.02 secs +info: area recovery done, total area reduction: 0.00squm (0.00%), final slack: 18139.2ps (delta: 0.0ps) (0 secs) +done optimizing virtual at 00:00:18(cpu)/0:00:17(wall) 199MB(vsz)/566MB(peak) +info: floorplan : total 4 movable macros and 0 fixed macros +info: creating tracks for 10 routing layers [FP-148] +info: start floorplan stage 0 [FP-145] +info: end floorplan stage 0 [FP-145] +info: start floorplan stage 1 [FP-145] +info: end floorplan stage 1 [FP-145] +info: start rtl partition placement [PLACE-114] +info: placement mode : raw [PLACE-115] +info: set slack mode to weight modified +info: set slack mode to normal +info: set slack mode to optimize shift +info: timing-driven placement : ON [PLACE-116] +info: congestion-driven placement : ON [PLACE-117] +info: placement movable objects : macros 0 , rtl partitions 5, cells 0 [PLACE-118] +info: start placement stage 0 [PLACE-111] +info: end placement stage 0 [PLACE-111] +info: set slack mode to normal +info: cell density map (bin size 20 x 20 rows), maximum utilization: 170.00% average utilization: 13.98% [PLACE-153] +info: 9.00% bins with overflow, average overflow 18.49% [PLACE-154] +info: P-D: 0.090% (0.185 ~ 0.700) +Total Wire Length = 77698.10 +Average Wire = 58.60 +Longest Wire = 352.69 +Shortest Wire = 0.00 +WNS = 18139.5ps +info: placing 17 unplaced IO Pins +info: start rtl partition placement [PLACE-114] +info: placement mode : raw [PLACE-115] +info: set slack mode to weight modified +info: set slack mode to normal +info: set slack mode to optimize shift +info: timing-driven placement : ON [PLACE-116] +info: congestion-driven placement : ON [PLACE-117] +info: placement movable objects : macros 0 , rtl partitions 5, cells 0 [PLACE-118] +info: start placement stage 0 [PLACE-111] +info: end placement stage 0 [PLACE-111] +info: set slack mode to normal +info: cell density map (bin size 20 x 20 rows), maximum utilization: 90.53% average utilization: 14.23% [PLACE-153] +info: 0.00% bins with overflow, average overflow 0.00% [PLACE-154] +info: P-D: 0.000% (0.000 ~ 0.000) +Total Wire Length = 115431.45 +Average Wire = 87.05 +Longest Wire = 426.66 +Shortest Wire = 10.50 +WNS = 18131.2ps +info: 0 power/ground pre-route segments processed. [PLACE-144] +info: 0 routing blockages processed. [PLACE-145] +info: replaced @ 18131.2ps +done optimize placement at 00:00:21(cpu)/0:00:20(wall) 387MB(vsz)/822MB(peak) +info: cell density map (bin size 20 x 20 rows), maximum utilization: 90.53% average utilization: 14.23% [PLACE-153] +info: 0.00% bins with overflow, average overflow 0.00% [PLACE-154] +info: set slack mode to optimize shift +info: resetting all path groups +info: activated path group default @ 18131.2ps +info: suspended path group I2R @ ps +info: suspended path group I2O @ ps +info: activated path group R2O @ 36309.8ps +info: finished path group default @ 18131.2ps +info: finished path group R2O @ 36309.8ps +info: reactivating path groups +info: reactivated path group default @ 18131.2ps +info: reactivated path group R2O @ 36309.8ps +info: finished path group default @ 18131.2ps +info: finished path group R2O @ 36309.8ps +info: cell density map (bin size 20 x 20 rows), maximum utilization: 90.53% average utilization: 14.23% [PLACE-153] +info: 0.00% bins with overflow, average overflow 0.00% [PLACE-154] +info: 0 power/ground pre-route segments processed. [PLACE-144] +info: 0 routing blockages processed. [PLACE-145] +info: set slack mode to normal +info: done with all path groups +info: restore all path groups +info: (0) optimizing 'theMem/i_0/IAddr[5]' (path group default) @ 18131.2ps(1/1) (4 secs) +finished optimize at 00:00:22(cpu)/0:00:20(wall) 387MB(vsz)/822MB(peak) +> write_db ./output/odb/riscv.tessent_post_fix.odb +> write_verilog ./output/riscv.tessent_post_fix.v +info: writing Verilog file './output/riscv.tessent_post_fix.v' for module 'cpu' [WRITE-100] +> config_tessent -library {./libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib ./libs/fastscan/NangateOpenCellLibrary_low_temp_ccs.fslib ./libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib ./libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib ./libs/fastscan/LowPowerOpenCellLibrary_low_temp_ccs.fslib ./libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib ./libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.fslib ./libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib ./libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib ./libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib ./libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib ./libs/fastscan/PLL.fslib ./libs/fastscan/IO.fslib} + +--------------check dft--------------- +> check_dft +starting check_dft at 00:00:22(cpu)/0:00:21(wall) 377MB(vsz)/822MB(peak) +Checking DFT rules for 'cpu' + Running DFT TDRC iteration 1 + Total 1131 scanModels/flops with 90% scanable (1024 pass, 0 fail, 107 nonScan or excludeScan) +Report Check DFT: +-----+---------------------+------+--------+------+------------------------------------------- + |Item |Errors|Warnings|Status|Description +-----+---------------------+------+--------+------+------------------------------------------- +1 |internal_clock | 0| 0|Passed|Internal Clock +2 |constant_clock | 0| 0|Passed|Constant Clock +3 |non_clock_PI | 0| 0|Passed|Non-Clock PI +4 |blocking_clock_gate | 0| 0|Passed|Blocking clock gate +5 |internal_async | 0| 0|Passed|Internal Async. Set/Reset control +6 |constant_active_async| 0| 0|Passed|Constant active Async. Set/Reset signal +7 |non_test_PI | 0| 0|Passed|Unconstrained PI driving Async/ Set/Reset +8 |async_clock_conflict | 0| 0|Passed|Async. Set/Reset signal and Clock conflict +9 |parallel_scan_clock | 0| 0|Passed|Clock pin of unsupported parallel-scan flop +-----+---------------------+------+--------+------+------------------------------------------- +Design has 0 DFT violation(s) +finished check_dft at 00:00:22(cpu)/0:00:21(wall) 377MB(vsz)/822MB(peak) + +--------------define Scan-Chains--------------- +> define_scan_chain -scan_in SI_1 -scan_out SO_1 -create_port +Defining Scan Chain scanChain_1( si:SI_1, so:SO_1) +Adding Scan-in pin SI_1 to top Module +Adding Scan-out pin SO_1 to top Module +> define_scan_chain -scan_in SI_2 -scan_out SO_2 -create_port +Defining Scan Chain scanChain_2( si:SI_2, so:SO_2) +Adding Scan-in pin SI_2 to top Module +Adding Scan-out pin SO_2 to top Module +> define_scan_chain -scan_in SI_3 -scan_out SO_3 -create_port +Defining Scan Chain scanChain_3( si:SI_3, so:SO_3) +Adding Scan-in pin SI_3 to top Module +Adding Scan-out pin SO_3 to top Module +> define_scan_chain -scan_in SI_4 -scan_out SO_4 -create_port +Defining Scan Chain scanChain_4( si:SI_4, so:SO_4) +Adding Scan-in pin SI_4 to top Module +Adding Scan-out pin SO_4 to top Module + +----------run_tessent_scan---------------- +> run_tessent_scan +info: writing Verilog file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.03/Scan_0/oasys_netlist.v' for module 'cpu' [WRITE-100] +starting check_dft at 00:00:22(cpu)/0:00:21(wall) 377MB(vsz)/822MB(peak) +Checking DFT rules for 'cpu' + Running DFT TDRC iteration 1 + Total 1131 scanModels/flops with 90% scanable (1024 pass, 0 fail, 107 nonScan or excludeScan) +Report Check DFT: +-----+---------------------+------+--------+------+------------------------------------------- + |Item |Errors|Warnings|Status|Description +-----+---------------------+------+--------+------+------------------------------------------- +1 |internal_clock | 0| 0|Passed|Internal Clock +2 |constant_clock | 0| 0|Passed|Constant Clock +3 |non_clock_PI | 0| 0|Passed|Non-Clock PI +4 |blocking_clock_gate | 0| 0|Passed|Blocking clock gate +5 |internal_async | 0| 0|Passed|Internal Async. Set/Reset control +6 |constant_active_async| 0| 0|Passed|Constant active Async. Set/Reset signal +7 |non_test_PI | 0| 0|Passed|Unconstrained PI driving Async/ Set/Reset +8 |async_clock_conflict | 0| 0|Passed|Async. Set/Reset signal and Clock conflict +9 |parallel_scan_clock | 0| 0|Passed|Clock pin of unsupported parallel-scan flop +-----+---------------------+------+--------+------+------------------------------------------- +Design has 0 DFT violation(s) +finished check_dft at 00:00:22(cpu)/0:00:21(wall) 377MB(vsz)/822MB(peak) + Configuring 4 scan chain(s) + Configuring DEFAULT DFT partition + Enabling physical aware scan chains + Configuring 4 scan chain(s) for 1024 scan instance(s) in 1 test clock domain(s) + Domain clk_25mhz has 1024 flop(s) (1024 rise, 0 fall), 4 chain(s) (4,0) + Assigning chain scanChain_1 to domain clk_25mhz (edge: rise) (capacity: 256) + Assigning chain scanChain_2 to domain clk_25mhz (edge: rise) (capacity: 256) + Assigning chain scanChain_3 to domain clk_25mhz (edge: rise) (capacity: 256) + Assigning chain scanChain_4 to domain clk_25mhz (edge: rise) (capacity: 256) +info: writing Sdc file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.03/Scan_0/oasys.sdc' for design 'cpu' [WRITE-104] +info: Parameter 'tessentScandefFilePath' set to '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.03/Scan_0/cpu.scandef' [PARAM-104] + +************************************************************************************************************************************************************************************** + TESSENT EXECUTION BEGINS + Invoking Tessent Executable : /applications/SiemensEDA/siemenseda2023/tessent_2023.4-p1/bin/tessent + DoFile : /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.03/Scan_0/scan.do +************************************************************************************************************************************************************************************** + +/applications/SiemensEDA/siemenseda2023/tessent_2023.4-p1/bin/tessent -shell -dofile /tmp/oasys.2568101/.tmpTessentFile -log_file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.03/Scan_0/scan.log -replace +// Tessent Shell 2023.4-p1 Mon Feb 19 16:22:02 GMT 2024 +// Unpublished work. Copyright 2024 Siemens +// +// This material contains trade secrets or otherwise confidential +// information owned by Siemens Industry Software Inc. or its affiliates +// (collectively, "SISW"), or its licensors. Access to and use of this +// information is strictly limited as set forth in the Customer's +// applicable agreements with SISW. +// +// Siemens software executing under x86-64 Linux on Fri May 29 09:14:17 CEST 2026. +// 64 bit version +// Host: efiapps0.ads1.fh-nuernberg.de (12 x 3.5 GHz, 48014 MB RAM, 24575 MB Swap) +// +// command: if {[catch {source /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.03/Scan_0/scan.do} msg]} { +// puts "$msg" +// puts "TESSENT_ER_ORTL" } +// sub-command: set_context dft -scan -no_rtl -design_id Scan_0 +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_low_temp_ccs.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_low_temp_ccs.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_low_temp_ccs.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_low_temp_ccs.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_low_temp_ccs.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_low_temp_ccs.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/PLL.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/PLL.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/PLL.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/IO.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/IO.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/IO.fslib +// sub-command: set_module_matching_options -suffix_pattern_list {[_]+[0-9]+[_]+[0-9]+} -regexp -append +// sub-command: set_module_matching_options -suffix_pattern_list {[_]+[A-Z]+} -regexp -append +// sub-command: set_module_matching_options -suffix_pattern_list {[_]+[0-9]+[_]+[0-9]+[_]+[A-Z]+} -regexp -append +// sub-command: read_verilog /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.03/Scan_0/oasys_netlist.v +// sub-command: set_tsdb_output_directory /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.03/tsdb_outdir +// sub-command: read_sdc /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.03/Scan_0/oasys.sdc +// Command 'read_sdc' requires an elaborated design. Automatically elaborating the design ... +// Note: 640 duplicate cell library models were read. The last model read of the same name was kept. +// To see detailed messages per duplicate model, issue 'set_cell_library_options -report_duplicate_models on' +// before issuing 'read_cell_library'. +// Warning: 1 cell library model contained 2 floating model outputs. +// To see detailed messages per model, issue 'set_cell_library_options -report_floating_nets on' +// before issuing 'read_cell_library'. +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X1' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X2' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X4' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X8' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X1_HVT' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X2_HVT' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X4_HVT' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X8_HVT' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X1_SVT' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X2_SVT' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X4_SVT' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X8_SVT' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X1_LVT' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X2_LVT' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X4_LVT' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X8_LVT' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' +// Note: Top design is 'cpu'. +// Warning: Undefined modules were found. +// Before using "set_system_mode" or "create_flat_model", you must either define +// the missing modules using "read_verilog" and/or "read_cell_library", or use the +// following command to treat them as black boxes: + add_black_boxes -modules { \ + MemGen_16_10 \ + } +// You can also use "add_black_boxes -auto" to black box all undefined modules but +// it is recommended that you do not add this command to your dofile. Doing so may +// unintentionally black-box new undefined modules in future runs. +// Warning: 32 cases: Unused net in DFT library model +// Warning: 110 cases: Undriven net in netlist module +// Warning: 1 case: Floating input on instance in netlist +// Warning: 47 cases: Net in netlist not connected +// Note: Issue set_current_design with the -show_elaboration_warnings option to see more details about previous warnings +// Design elaboration successful. +// Reading SDC file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.03/Scan_0/oasys.sdc ... +// Finished reading SDC file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.03/Scan_0/oasys.sdc. +// Read SDC summary: 1 false path, 0 multi-cycle paths, 0 erroneous paths +// 0 disable timings, 0 case analysis, 0 clock groups +// sub-command: set_current_design cpu -show_elaboration_warnings +// Warning: Undefined modules were found. +// Before using "set_system_mode" or "create_flat_model", you must either define +// the missing modules using "read_verilog" and/or "read_cell_library", or use the +// following command to treat them as black boxes: + add_black_boxes -modules { \ + MemGen_16_10 \ + } +// You can also use "add_black_boxes -auto" to black box all undefined modules but +// it is recommended that you do not add this command to your dofile. Doing so may +// unintentionally black-box new undefined modules in future runs. +// Warning: Net 'SO_1' in module 'cpu' is not driven +// Warning: Net 'SO_2' in module 'cpu' is not driven +// Warning: Net 'SO_3' in module 'cpu' is not driven +// Warning: Net 'SO_4' in module 'cpu' is not driven +// Warning: Net 'DAddr[31]' in module 'cpu' has no pins +// Warning: Net 'DAddr[30]' in module 'cpu' has no pins +// Warning: Net 'DAddr[29]' in module 'cpu' has no pins +// Warning: Net 'DAddr[28]' in module 'cpu' has no pins +// Warning: Net 'DAddr[27]' in module 'cpu' has no pins +// Warning: Net 'DAddr[26]' in module 'cpu' has no pins +// Warning: Net 'DAddr[25]' in module 'cpu' has no pins +// Warning: Net 'DAddr[24]' in module 'cpu' has no pins +// Warning: Net 'DAddr[23]' in module 'cpu' has no pins +// Warning: Net 'DAddr[22]' in module 'cpu' has no pins +// Warning: Net 'DAddr[21]' in module 'cpu' has no pins +// Warning: Net 'DAddr[20]' in module 'cpu' has no pins +// Warning: Net 'DAddr[19]' in module 'cpu' has no pins +// Warning: Net 'DAddr[18]' in module 'cpu' has no pins +// Warning: Net 'DAddr[17]' in module 'cpu' has no pins +// Warning: Net 'DAddr[16]' in module 'cpu' has no pins +// Warning: Net 'DAddr[15]' in module 'cpu' has no pins +// Warning: Net 'DAddr[14]' in module 'cpu' has no pins +// Warning: Net 'DAddr[13]' in module 'cpu' has no pins +// Warning: Net 'NextPC[31]' in module 'cpu' has no pins +// Warning: Net 'NextPC[30]' in module 'cpu' has no pins +// Warning: Net 'NextPC[29]' in module 'cpu' has no pins +// Warning: Net 'NextPC[28]' in module 'cpu' has no pins +// Warning: Net 'NextPC[27]' in module 'cpu' has no pins +// Warning: Net 'NextPC[26]' in module 'cpu' has no pins +// Warning: Net 'NextPC[25]' in module 'cpu' has no pins +// Warning: Net 'NextPC[24]' in module 'cpu' has no pins +// Warning: Net 'NextPC[23]' in module 'cpu' has no pins +// Warning: Net 'NextPC[22]' in module 'cpu' has no pins +// Warning: Net 'NextPC[21]' in module 'cpu' has no pins +// Warning: Net 'NextPC[20]' in module 'cpu' has no pins +// Warning: Net 'NextPC[19]' in module 'cpu' has no pins +// Warning: Net 'NextPC[18]' in module 'cpu' has no pins +// Warning: Net 'NextPC[17]' in module 'cpu' has no pins +// Warning: Net 'NextPC[16]' in module 'cpu' has no pins +// Warning: Net 'NextPC[15]' in module 'cpu' has no pins +// Warning: Net 'NextPC[14]' in module 'cpu' has no pins +// Warning: Net 'NextPC[13]' in module 'cpu' has no pins +// Warning: Net 'NextPC[7]' in module 'cpu' has no pins +// Warning: Net 'NextPC[6]' in module 'cpu' has no pins +// Warning: Net 'NextPC[5]' in module 'cpu' has no pins +// Warning: Net 'NextPC[4]' in module 'cpu' has no pins +// Warning: Net 'NextPC[3]' in module 'cpu' has no pins +// Warning: Net 'NextPC[2]' in module 'cpu' has no pins +// Warning: Net 'NextPC[1]' in module 'cpu' has no pins +// Warning: Net 'NextPC[0]' in module 'cpu' has no pins +// Warning: Net 'uc_0' in module 'cpu' is not driven +// Warning: Net 'uc_1' in module 'cpu' is not driven +// Warning: Net 'uc_2' in module 'cpu' is not driven +// Warning: Net 'uc_3' in module 'cpu' is not driven +// Warning: Net 'uc_4' in module 'cpu' is not driven +// Warning: Net 'uc_5' in module 'cpu' is not driven +// Warning: Net 'uc_6' in module 'cpu' is not driven +// Warning: Net 'uc_7' in module 'cpu' is not driven +// Warning: Net 'uc_8' in module 'cpu' is not driven +// Warning: Net 'uc_9' in module 'cpu' is not driven +// Warning: Net 'uc_10' in module 'cpu' is not driven +// Warning: Net 'uc_11' in module 'cpu' is not driven +// Warning: Net 'uc_12' in module 'cpu' is not driven +// Warning: Net 'uc_13' in module 'cpu' is not driven +// Warning: Net 'uc_14' in module 'cpu' is not driven +// Warning: Net 'uc_15' in module 'cpu' is not driven +// Warning: Net 'uc_16' in module 'cpu' is not driven +// Warning: Net 'uc_17' in module 'cpu' is not driven +// Warning: Net 'uc_18' in module 'cpu' is not driven +// Warning: Net 'uc_19' in module 'cpu' is not driven +// Warning: Net 'uc_20' in module 'cpu' is not driven +// Warning: Net 'uc_21' in module 'cpu' is not driven +// Warning: Net 'uc_22' in module 'cpu' is not driven +// Warning: Net 'uc_23' in module 'cpu' is not driven +// Warning: Net 'uc_24' in module 'cpu' is not driven +// Warning: Net 'uc_25' in module 'cpu' is not driven +// Warning: Net 'uc_26' in module 'cpu' is not driven +// Warning: Net 'uc_27' in module 'cpu' is not driven +// Warning: Net 'uc_28' in module 'cpu' is not driven +// Warning: Net 'uc_29' in module 'cpu' is not driven +// Warning: Net 'uc_30' in module 'cpu' is not driven +// Warning: Net 'uc_31' in module 'cpu' is not driven +// Warning: Net 'uc_32' in module 'cpu' is not driven +// Warning: Net 'uc_33' in module 'cpu' is not driven +// Warning: Net 'uc_34' in module 'cpu' is not driven +// Warning: Net 'uc_35' in module 'cpu' is not driven +// Warning: Net 'uc_36' in module 'cpu' is not driven +// Warning: Net 'uc_37' in module 'cpu' is not driven +// Warning: Net 'uc_38' in module 'cpu' is not driven +// Warning: Net 'uc_39' in module 'cpu' is not driven +// Warning: Floating input 'chip_en' at instance 'RAM' in module 'main_mem' +// Warning: Net 'mem_sel[1]' in module 'MemGen_32_11' has no pins +// Warning: Net 'DAddr[31]' in module 'decoder' is not driven +// Warning: Net 'DAddr[30]' in module 'decoder' is not driven +// Warning: Net 'DAddr[29]' in module 'decoder' is not driven +// Warning: Net 'DAddr[28]' in module 'decoder' is not driven +// Warning: Net 'DAddr[27]' in module 'decoder' is not driven +// Warning: Net 'DAddr[26]' in module 'decoder' is not driven +// Warning: Net 'DAddr[25]' in module 'decoder' is not driven +// Warning: Net 'DAddr[24]' in module 'decoder' is not driven +// Warning: Net 'DAddr[23]' in module 'decoder' is not driven +// Warning: Net 'DAddr[22]' in module 'decoder' is not driven +// Warning: Net 'DAddr[21]' in module 'decoder' is not driven +// Warning: Net 'DAddr[20]' in module 'decoder' is not driven +// Warning: Net 'DAddr[19]' in module 'decoder' is not driven +// Warning: Net 'DAddr[18]' in module 'decoder' is not driven +// Warning: Net 'DAddr[17]' in module 'decoder' is not driven +// Warning: Net 'DAddr[16]' in module 'decoder' is not driven +// Warning: Net 'DAddr[15]' in module 'decoder' is not driven +// Warning: Net 'DAddr[14]' in module 'decoder' is not driven +// Warning: Net 'DAddr[13]' in module 'decoder' is not driven +// Warning: Net 'WData[31]' in module 'decoder' is not driven +// Warning: Net 'WData[30]' in module 'decoder' is not driven +// Warning: Net 'WData[29]' in module 'decoder' is not driven +// Warning: Net 'WData[28]' in module 'decoder' is not driven +// Warning: Net 'WData[27]' in module 'decoder' is not driven +// Warning: Net 'WData[26]' in module 'decoder' is not driven +// Warning: Net 'WData[25]' in module 'decoder' is not driven +// Warning: Net 'WData[24]' in module 'decoder' is not driven +// Warning: Net 'WData[23]' in module 'decoder' is not driven +// Warning: Net 'WData[22]' in module 'decoder' is not driven +// Warning: Net 'WData[21]' in module 'decoder' is not driven +// Warning: Net 'WData[20]' in module 'decoder' is not driven +// Warning: Net 'WData[19]' in module 'decoder' is not driven +// Warning: Net 'WData[18]' in module 'decoder' is not driven +// Warning: Net 'WData[17]' in module 'decoder' is not driven +// Warning: Net 'WData[16]' in module 'decoder' is not driven +// Warning: Net 'WData[15]' in module 'decoder' is not driven +// Warning: Net 'WData[14]' in module 'decoder' is not driven +// Warning: Net 'WData[13]' in module 'decoder' is not driven +// Warning: Net 'WData[12]' in module 'decoder' is not driven +// Warning: Net 'WData[11]' in module 'decoder' is not driven +// Warning: Net 'WData[10]' in module 'decoder' is not driven +// Warning: Net 'WData[9]' in module 'decoder' is not driven +// Warning: Net 'WData[8]' in module 'decoder' is not driven +// Warning: Net 'WData[7]' in module 'decoder' is not driven +// Warning: Net 'WData[6]' in module 'decoder' is not driven +// Warning: Net 'WData[5]' in module 'decoder' is not driven +// Warning: Net 'WData[4]' in module 'decoder' is not driven +// Warning: Net 'WData[3]' in module 'decoder' is not driven +// Warning: Net 'WData[2]' in module 'decoder' is not driven +// Warning: Net 'WData[1]' in module 'decoder' is not driven +// Warning: Net 'WData[0]' in module 'decoder' is not driven +// Warning: Net 'Rs1[4]' in module 'decoder' is not driven +// Warning: Net 'Rs1[3]' in module 'decoder' is not driven +// Warning: Net 'Rs1[2]' in module 'decoder' is not driven +// Warning: Net 'Rs1[1]' in module 'decoder' is not driven +// Warning: Net 'Rs1[0]' in module 'decoder' is not driven +// Warning: Net 'Rs2[4]' in module 'decoder' is not driven +// Warning: Net 'Rs2[3]' in module 'decoder' is not driven +// Warning: Net 'Rs2[2]' in module 'decoder' is not driven +// Warning: Net 'Rs2[1]' in module 'decoder' is not driven +// Warning: Net 'Rs2[0]' in module 'decoder' is not driven +// Warning: Net 'Rd[4]' in module 'decoder' is not driven +// Warning: Net 'Rd[3]' in module 'decoder' is not driven +// Warning: Net 'Rd[2]' in module 'decoder' is not driven +// Warning: Net 'Rd[1]' in module 'decoder' is not driven +// Warning: Net 'Rd[0]' in module 'decoder' is not driven +// sub-command: set_design_level physical_block +// sub-command: set_shift_register_identification off +// sub-command: add_nonscan_instances -instances "{/theMem/\IRData_reg[31] } {/theMem/\IRData_reg[30] } {/theMem/\IRData_reg[29] } {/theMem/\IRData_reg[28] } {/theMem/\IRData_reg[27] } {/theMem/\IRData_reg[26] } {/theMem/\IRData_reg[25] } {/theMem/\IRData_reg[24] } {/theMem/\IRData_reg[23] } {/theMem/\IRData_reg[22] } {/theMem/\IRData_reg[21] } {/theMem/\IRData_reg[20] } {/theMem/\IRData_reg[19] } {/theMem/\IRData_reg[18] } {/theMem/\IRData_reg[17] } {/theMem/\IRData_reg[16] } {/theMem/\IRData_reg[15] } {/theMem/\IRData_reg[14] } {/theMem/\IRData_reg[13] } {/theMem/\IRData_reg[12] } {/theMem/\IRData_reg[11] } {/theMem/\IRData_reg[10] } {/theMem/\IRData_reg[9] } {/theMem/\IRData_reg[8] } {/theMem/\IRData_reg[7] } {/theMem/\IRData_reg[6] } {/theMem/\IRData_reg[5] } {/theMem/\IRData_reg[4] } {/theMem/\IRData_reg[3] } {/theMem/\IRData_reg[2] } {/theMem/\IRData_reg[1] } {/theMem/\IRData_reg[0] } {/theMem/\mem_addr_reg[10] } {/theMem/\mem_addr_reg[9] } {/theMem/\mem_addr_reg[8] } {/theMem/\mem_addr_reg[7] } {/theMem/\mem_addr_reg[6] } {/theMem/\mem_addr_reg[5] } {/theMem/\mem_addr_reg[4] } {/theMem/\mem_addr_reg[3] } {/theMem/\mem_addr_reg[2] } {/theMem/\mem_addr_reg[1] } {/theMem/\mem_addr_reg[0] } {/theMem/\drTmp_reg[31] } {/theMem/\drTmp_reg[30] } {/theMem/\drTmp_reg[29] } {/theMem/\drTmp_reg[28] } {/theMem/\drTmp_reg[27] } {/theMem/\drTmp_reg[26] } {/theMem/\drTmp_reg[25] } {/theMem/\drTmp_reg[24] } {/theMem/\drTmp_reg[23] } {/theMem/\drTmp_reg[22] } {/theMem/\drTmp_reg[21] } {/theMem/\drTmp_reg[20] } {/theMem/\drTmp_reg[19] } {/theMem/\drTmp_reg[18] } {/theMem/\drTmp_reg[17] } {/theMem/\drTmp_reg[16] } {/theMem/\drTmp_reg[15] } {/theMem/\drTmp_reg[14] } {/theMem/\drTmp_reg[13] } {/theMem/\drTmp_reg[12] } {/theMem/\drTmp_reg[11] } {/theMem/\drTmp_reg[10] } {/theMem/\drTmp_reg[9] } {/theMem/\drTmp_reg[8] } {/theMem/\drTmp_reg[7] } {/theMem/\drTmp_reg[6] } {/theMem/\drTmp_reg[5] } {/theMem/\drTmp_reg[4] } {/theMem/\drTmp_reg[3] } {/theMem/\drTmp_reg[2] } {/theMem/\drTmp_reg[1] } {/theMem/\drTmp_reg[0] } {/theMem/\mem_wdata_reg[31] } {/theMem/\mem_wdata_reg[30] } {/theMem/\mem_wdata_reg[29] } {/theMem/\mem_wdata_reg[28] } {/theMem/\mem_wdata_reg[27] } {/theMem/\mem_wdata_reg[26] } {/theMem/\mem_wdata_reg[25] } {/theMem/\mem_wdata_reg[24] } {/theMem/\mem_wdata_reg[23] } {/theMem/\mem_wdata_reg[22] } {/theMem/\mem_wdata_reg[21] } {/theMem/\mem_wdata_reg[20] } {/theMem/\mem_wdata_reg[19] } {/theMem/\mem_wdata_reg[18] } {/theMem/\mem_wdata_reg[17] } {/theMem/\mem_wdata_reg[16] } {/theMem/\mem_wdata_reg[15] } {/theMem/\mem_wdata_reg[14] } {/theMem/\mem_wdata_reg[13] } {/theMem/\mem_wdata_reg[12] } {/theMem/\mem_wdata_reg[11] } {/theMem/\mem_wdata_reg[10] } {/theMem/\mem_wdata_reg[9] } {/theMem/\mem_wdata_reg[8] } {/theMem/\mem_wdata_reg[7] } {/theMem/\mem_wdata_reg[6] } {/theMem/\mem_wdata_reg[5] } {/theMem/\mem_wdata_reg[4] } {/theMem/\mem_wdata_reg[3] } {/theMem/\mem_wdata_reg[2] } {/theMem/\mem_wdata_reg[1] } {/theMem/\mem_wdata_reg[0] } " +// sub-command: add_clocks 0 " clk_25mhz " +// sub-command: set_scan_enable scan_en -active high +// sub-command: add_input_constraints btn[0] -C1 +// sub-command: set_scan_enable scan_en -active high -cluster_name scanChain_1 +// sub-command: set_scan_enable scan_en -active high -cluster_name scanChain_2 +// sub-command: set_scan_enable scan_en -active high -cluster_name scanChain_3 +// sub-command: set_scan_enable scan_en -active high -cluster_name scanChain_4 +// sub-command: add_black_boxes -modules " MemGen_16_10 " +// sub-command: set_scan_insertion_options -single_clock_edge_chains on -si_port_format oas_ts_si[%d] -so_port_format oas_ts_so[%d] +// sub-command: set_system_mode analysis +// Warning: Rule FN1 violation occurs 157 times +// Warning: Rule FP13 violation occurs 1 times +// Flattening process completed, cell instances=4379, gates=18234, PIs=13, POs=12, CPU time=0.09 sec. +// --------------------------------------------------------------------------- +// Begin circuit learning analyses. +// -------------------------------- +// Learning completed, CPU time=0.01 sec. +// --------------------------------------------------------------------------- +// Begin scan chain identification process, memory elements = 1194, +// sequential library cells = 1194. +// --------------------------------------------------------------------------- +// Warning: Model 'DLH_X1_LVT' has no muxscan scan equivalent and is treated as nonscan model +// ------------------------------------------------------------------------------ +// 170 sequential library cells are treated as non-scan. +// ------------------------------------------------------------------------------ +// 63 sequential library cells missing mux-scan equivalent. +// 107 sequential library cells defined non-scan. +// --------------------------------------------------------------------------- +// Begin scannability rules checking for 1024 sequential library cells. +// --------------------------------------------------------------------------- +// 1024 sequential library cells identified as scannable. +// --------------------------------------------------------------------------- +// Begin transparent latch checking for 63 latches. +// --------------------------------------------------------------------------- +// Warning: 32 latches not transparent due to uncontrollable. (D6) +// Number transparent latches = 31. +// --------------------------------------------------------------------------- +// Begin scan clock rules checking. +// --------------------------------------------------------------------------- +// 1 scan clock/set/reset lines have been identified. +// All scan clocks successfully passed off-state check. +// 1131 sequential cells passed clock stability checking. +// There were 43 clock rule C3 fails (clock may capture data affected by its captured data). +// Note: Trailing edge triggered device can capture data affected by leading edge. +// --------------------------------------------------------------------------- +// 170 non-scan memory elements are identified. +// --------------------------------------------------------------------------- +// 32 non-scan memory elements are identified as TIE-X. (D5) +// 107 non-scan memory elements are identified as INIT-X. (D5) +// 31 non-scan memory elements are identified as TLA. (D5) +// --------------------------------------------------------------------------- +// Number of targeted sequential library cells = 1024 +// Warning: The tool may require a shift-capture clock during insertion, +// but no 'shift_capture_clock' DFT signal was identified +// and no TCLK source was specified using the command 'set_scan_signals -tclk'. +// Note: The system clock 'clk_25mhz' will be used as the shift-capture clock, if needed. +// sub-command: report_drc_rules +C3: #fails=43 handling=note (clock may capture data affected by its captured data) +D5: #fails=170 handling=warning (non-scan memory element) +D6: #fails=32 handling=warning (non-transparent non-scan latches) +// sub-command: create_scan_chain_family scanChain_1 -include_elements "{/\thePC_CurrentPC_reg[0] } {/\thePC_CurrentPC_reg[10] } {/\thePC_CurrentPC_reg[11] } {/\thePC_CurrentPC_reg[12] } {/\thePC_CurrentPC_reg[13] } {/\thePC_CurrentPC_reg[14] } {/\thePC_CurrentPC_reg[15] } {/\thePC_CurrentPC_reg[16] } {/\thePC_CurrentPC_reg[17] } {/\thePC_CurrentPC_reg[18] } {/\thePC_CurrentPC_reg[19] } {/\thePC_CurrentPC_reg[1] } {/\thePC_CurrentPC_reg[20] } {/\thePC_CurrentPC_reg[21] } {/\thePC_CurrentPC_reg[22] } {/\thePC_CurrentPC_reg[23] } {/\thePC_CurrentPC_reg[24] } {/\thePC_CurrentPC_reg[25] } {/\thePC_CurrentPC_reg[26] } {/\thePC_CurrentPC_reg[27] } {/\thePC_CurrentPC_reg[28] } {/\thePC_CurrentPC_reg[29] } {/\thePC_CurrentPC_reg[2] } {/\thePC_CurrentPC_reg[30] } {/\thePC_CurrentPC_reg[31] } {/\thePC_CurrentPC_reg[3] } {/\thePC_CurrentPC_reg[4] } {/\thePC_CurrentPC_reg[5] } {/\thePC_CurrentPC_reg[6] } {/\thePC_CurrentPC_reg[7] } {/\thePC_CurrentPC_reg[8] } {/\thePC_CurrentPC_reg[9] } {/theRegisters/\registers_reg[10][0] } {/theRegisters/\registers_reg[10][10] } {/theRegisters/\registers_reg[10][11] } {/theRegisters/\registers_reg[10][12] } {/theRegisters/\registers_reg[10][13] } {/theRegisters/\registers_reg[10][14] } {/theRegisters/\registers_reg[10][15] } {/theRegisters/\registers_reg[10][16] } {/theRegisters/\registers_reg[10][17] } {/theRegisters/\registers_reg[10][18] } {/theRegisters/\registers_reg[10][19] } {/theRegisters/\registers_reg[10][1] } {/theRegisters/\registers_reg[10][20] } {/theRegisters/\registers_reg[10][21] } {/theRegisters/\registers_reg[10][22] } {/theRegisters/\registers_reg[10][23] } {/theRegisters/\registers_reg[10][24] } {/theRegisters/\registers_reg[10][25] } {/theRegisters/\registers_reg[10][26] } {/theRegisters/\registers_reg[10][27] } {/theRegisters/\registers_reg[10][28] } {/theRegisters/\registers_reg[10][29] } {/theRegisters/\registers_reg[10][2] } {/theRegisters/\registers_reg[10][30] } {/theRegisters/\registers_reg[10][31] } {/theRegisters/\registers_reg[10][3] } {/theRegisters/\registers_reg[10][4] } {/theRegisters/\registers_reg[10][5] } {/theRegisters/\registers_reg[10][6] } {/theRegisters/\registers_reg[10][7] } {/theRegisters/\registers_reg[10][8] } {/theRegisters/\registers_reg[10][9] } {/theRegisters/\registers_reg[11][0] } {/theRegisters/\registers_reg[11][10] } {/theRegisters/\registers_reg[11][11] } {/theRegisters/\registers_reg[11][12] } {/theRegisters/\registers_reg[11][13] } {/theRegisters/\registers_reg[11][14] } {/theRegisters/\registers_reg[11][15] } {/theRegisters/\registers_reg[11][16] } {/theRegisters/\registers_reg[11][17] } {/theRegisters/\registers_reg[11][18] } {/theRegisters/\registers_reg[11][19] } {/theRegisters/\registers_reg[11][1] } {/theRegisters/\registers_reg[11][20] } {/theRegisters/\registers_reg[11][21] } {/theRegisters/\registers_reg[11][22] } {/theRegisters/\registers_reg[11][23] } {/theRegisters/\registers_reg[11][24] } {/theRegisters/\registers_reg[11][25] } {/theRegisters/\registers_reg[11][26] } {/theRegisters/\registers_reg[11][27] } {/theRegisters/\registers_reg[11][28] } {/theRegisters/\registers_reg[11][29] } {/theRegisters/\registers_reg[11][2] } {/theRegisters/\registers_reg[11][30] } {/theRegisters/\registers_reg[11][31] } {/theRegisters/\registers_reg[11][3] } {/theRegisters/\registers_reg[11][4] } {/theRegisters/\registers_reg[11][5] } {/theRegisters/\registers_reg[11][6] } {/theRegisters/\registers_reg[11][7] } {/theRegisters/\registers_reg[11][8] } {/theRegisters/\registers_reg[11][9] } {/theRegisters/\registers_reg[12][0] } {/theRegisters/\registers_reg[12][10] } {/theRegisters/\registers_reg[12][11] } {/theRegisters/\registers_reg[12][12] } {/theRegisters/\registers_reg[12][13] } {/theRegisters/\registers_reg[12][14] } {/theRegisters/\registers_reg[12][15] } {/theRegisters/\registers_reg[12][16] } {/theRegisters/\registers_reg[12][17] } {/theRegisters/\registers_reg[12][18] } {/theRegisters/\registers_reg[12][19] } {/theRegisters/\registers_reg[12][1] } {/theRegisters/\registers_reg[12][20] } {/theRegisters/\registers_reg[12][21] } {/theRegisters/\registers_reg[12][22] } {/theRegisters/\registers_reg[12][23] } {/theRegisters/\registers_reg[12][24] } {/theRegisters/\registers_reg[12][25] } {/theRegisters/\registers_reg[12][26] } {/theRegisters/\registers_reg[12][27] } {/theRegisters/\registers_reg[12][28] } {/theRegisters/\registers_reg[12][29] } {/theRegisters/\registers_reg[12][2] } {/theRegisters/\registers_reg[12][30] } {/theRegisters/\registers_reg[12][31] } {/theRegisters/\registers_reg[12][3] } {/theRegisters/\registers_reg[12][4] } {/theRegisters/\registers_reg[12][5] } {/theRegisters/\registers_reg[12][6] } {/theRegisters/\registers_reg[12][7] } {/theRegisters/\registers_reg[12][8] } {/theRegisters/\registers_reg[12][9] } {/theRegisters/\registers_reg[13][0] } {/theRegisters/\registers_reg[13][10] } {/theRegisters/\registers_reg[13][11] } {/theRegisters/\registers_reg[13][12] } {/theRegisters/\registers_reg[13][13] } {/theRegisters/\registers_reg[13][14] } {/theRegisters/\registers_reg[13][15] } {/theRegisters/\registers_reg[13][16] } {/theRegisters/\registers_reg[13][17] } {/theRegisters/\registers_reg[13][18] } {/theRegisters/\registers_reg[13][19] } {/theRegisters/\registers_reg[13][1] } {/theRegisters/\registers_reg[13][20] } {/theRegisters/\registers_reg[13][21] } {/theRegisters/\registers_reg[13][22] } {/theRegisters/\registers_reg[13][23] } {/theRegisters/\registers_reg[13][24] } {/theRegisters/\registers_reg[13][25] } {/theRegisters/\registers_reg[13][26] } {/theRegisters/\registers_reg[13][27] } {/theRegisters/\registers_reg[13][28] } {/theRegisters/\registers_reg[13][29] } {/theRegisters/\registers_reg[13][2] } {/theRegisters/\registers_reg[13][30] } {/theRegisters/\registers_reg[13][31] } {/theRegisters/\registers_reg[13][3] } {/theRegisters/\registers_reg[13][4] } {/theRegisters/\registers_reg[13][5] } {/theRegisters/\registers_reg[13][6] } {/theRegisters/\registers_reg[13][7] } {/theRegisters/\registers_reg[13][8] } {/theRegisters/\registers_reg[13][9] } {/theRegisters/\registers_reg[14][0] } {/theRegisters/\registers_reg[14][10] } {/theRegisters/\registers_reg[14][11] } {/theRegisters/\registers_reg[14][12] } {/theRegisters/\registers_reg[14][13] } {/theRegisters/\registers_reg[14][14] } {/theRegisters/\registers_reg[14][15] } {/theRegisters/\registers_reg[14][16] } {/theRegisters/\registers_reg[14][17] } {/theRegisters/\registers_reg[14][18] } {/theRegisters/\registers_reg[14][19] } {/theRegisters/\registers_reg[14][1] } {/theRegisters/\registers_reg[14][20] } {/theRegisters/\registers_reg[14][21] } {/theRegisters/\registers_reg[14][22] } {/theRegisters/\registers_reg[14][23] } {/theRegisters/\registers_reg[14][24] } {/theRegisters/\registers_reg[14][25] } {/theRegisters/\registers_reg[14][26] } {/theRegisters/\registers_reg[14][27] } {/theRegisters/\registers_reg[14][28] } {/theRegisters/\registers_reg[14][29] } {/theRegisters/\registers_reg[14][2] } {/theRegisters/\registers_reg[14][30] } {/theRegisters/\registers_reg[14][31] } {/theRegisters/\registers_reg[14][3] } {/theRegisters/\registers_reg[14][4] } {/theRegisters/\registers_reg[14][5] } {/theRegisters/\registers_reg[14][6] } {/theRegisters/\registers_reg[14][7] } {/theRegisters/\registers_reg[14][8] } {/theRegisters/\registers_reg[14][9] } {/theRegisters/\registers_reg[15][0] } {/theRegisters/\registers_reg[15][10] } {/theRegisters/\registers_reg[15][11] } {/theRegisters/\registers_reg[15][12] } {/theRegisters/\registers_reg[15][13] } {/theRegisters/\registers_reg[15][14] } {/theRegisters/\registers_reg[15][15] } {/theRegisters/\registers_reg[15][16] } {/theRegisters/\registers_reg[15][17] } {/theRegisters/\registers_reg[15][18] } {/theRegisters/\registers_reg[15][19] } {/theRegisters/\registers_reg[15][1] } {/theRegisters/\registers_reg[15][20] } {/theRegisters/\registers_reg[15][21] } {/theRegisters/\registers_reg[15][22] } {/theRegisters/\registers_reg[15][23] } {/theRegisters/\registers_reg[15][24] } {/theRegisters/\registers_reg[15][25] } {/theRegisters/\registers_reg[15][26] } {/theRegisters/\registers_reg[15][27] } {/theRegisters/\registers_reg[15][28] } {/theRegisters/\registers_reg[15][29] } {/theRegisters/\registers_reg[15][2] } {/theRegisters/\registers_reg[15][30] } {/theRegisters/\registers_reg[15][31] } {/theRegisters/\registers_reg[15][3] } {/theRegisters/\registers_reg[15][4] } {/theRegisters/\registers_reg[15][5] } {/theRegisters/\registers_reg[15][6] } {/theRegisters/\registers_reg[15][7] } {/theRegisters/\registers_reg[15][8] } {/theRegisters/\registers_reg[15][9] } {/theRegisters/\registers_reg[16][0] } {/theRegisters/\registers_reg[16][10] } {/theRegisters/\registers_reg[16][11] } {/theRegisters/\registers_reg[16][12] } {/theRegisters/\registers_reg[16][13] } {/theRegisters/\registers_reg[16][14] } {/theRegisters/\registers_reg[16][15] } {/theRegisters/\registers_reg[16][16] } {/theRegisters/\registers_reg[16][17] } {/theRegisters/\registers_reg[16][18] } {/theRegisters/\registers_reg[16][19] } {/theRegisters/\registers_reg[16][1] } {/theRegisters/\registers_reg[16][20] } {/theRegisters/\registers_reg[16][21] } {/theRegisters/\registers_reg[16][22] } {/theRegisters/\registers_reg[16][23] } {/theRegisters/\registers_reg[16][24] } {/theRegisters/\registers_reg[16][25] } {/theRegisters/\registers_reg[16][26] } {/theRegisters/\registers_reg[16][27] } {/theRegisters/\registers_reg[16][28] } {/theRegisters/\registers_reg[16][29] } {/theRegisters/\registers_reg[16][2] } {/theRegisters/\registers_reg[16][30] } {/theRegisters/\registers_reg[16][31] } {/theRegisters/\registers_reg[16][3] } {/theRegisters/\registers_reg[16][4] } {/theRegisters/\registers_reg[16][5] } {/theRegisters/\registers_reg[16][6] } {/theRegisters/\registers_reg[16][7] } {/theRegisters/\registers_reg[16][8] } {/theRegisters/\registers_reg[16][9] } " -si_connections "SI_1 " -so_connections "SO_1 " -chain_count 1 +// sub-command: create_scan_chain_family scanChain_2 -include_elements "{/theRegisters/\registers_reg[17][0] } {/theRegisters/\registers_reg[17][10] } {/theRegisters/\registers_reg[17][11] } {/theRegisters/\registers_reg[17][12] } {/theRegisters/\registers_reg[17][13] } {/theRegisters/\registers_reg[17][14] } {/theRegisters/\registers_reg[17][15] } {/theRegisters/\registers_reg[17][16] } {/theRegisters/\registers_reg[17][17] } {/theRegisters/\registers_reg[17][18] } {/theRegisters/\registers_reg[17][19] } {/theRegisters/\registers_reg[17][1] } {/theRegisters/\registers_reg[17][20] } {/theRegisters/\registers_reg[17][21] } {/theRegisters/\registers_reg[17][22] } {/theRegisters/\registers_reg[17][23] } {/theRegisters/\registers_reg[17][24] } {/theRegisters/\registers_reg[17][25] } {/theRegisters/\registers_reg[17][26] } {/theRegisters/\registers_reg[17][27] } {/theRegisters/\registers_reg[17][28] } {/theRegisters/\registers_reg[17][29] } {/theRegisters/\registers_reg[17][2] } {/theRegisters/\registers_reg[17][30] } {/theRegisters/\registers_reg[17][31] } {/theRegisters/\registers_reg[17][3] } {/theRegisters/\registers_reg[17][4] } {/theRegisters/\registers_reg[17][5] } {/theRegisters/\registers_reg[17][6] } {/theRegisters/\registers_reg[17][7] } {/theRegisters/\registers_reg[17][8] } {/theRegisters/\registers_reg[17][9] } {/theRegisters/\registers_reg[18][0] } {/theRegisters/\registers_reg[18][10] } {/theRegisters/\registers_reg[18][11] } {/theRegisters/\registers_reg[18][12] } {/theRegisters/\registers_reg[18][13] } {/theRegisters/\registers_reg[18][14] } {/theRegisters/\registers_reg[18][15] } {/theRegisters/\registers_reg[18][16] } {/theRegisters/\registers_reg[18][17] } {/theRegisters/\registers_reg[18][18] } {/theRegisters/\registers_reg[18][19] } {/theRegisters/\registers_reg[18][1] } {/theRegisters/\registers_reg[18][20] } {/theRegisters/\registers_reg[18][21] } {/theRegisters/\registers_reg[18][22] } {/theRegisters/\registers_reg[18][23] } {/theRegisters/\registers_reg[18][24] } {/theRegisters/\registers_reg[18][25] } {/theRegisters/\registers_reg[18][26] } {/theRegisters/\registers_reg[18][27] } {/theRegisters/\registers_reg[18][28] } {/theRegisters/\registers_reg[18][29] } {/theRegisters/\registers_reg[18][2] } {/theRegisters/\registers_reg[18][30] } {/theRegisters/\registers_reg[18][31] } {/theRegisters/\registers_reg[18][3] } {/theRegisters/\registers_reg[18][4] } {/theRegisters/\registers_reg[18][5] } {/theRegisters/\registers_reg[18][6] } {/theRegisters/\registers_reg[18][7] } {/theRegisters/\registers_reg[18][8] } {/theRegisters/\registers_reg[18][9] } {/theRegisters/\registers_reg[19][0] } {/theRegisters/\registers_reg[19][10] } {/theRegisters/\registers_reg[19][11] } {/theRegisters/\registers_reg[19][12] } {/theRegisters/\registers_reg[19][13] } {/theRegisters/\registers_reg[19][14] } {/theRegisters/\registers_reg[19][15] } {/theRegisters/\registers_reg[19][16] } {/theRegisters/\registers_reg[19][17] } {/theRegisters/\registers_reg[19][18] } {/theRegisters/\registers_reg[19][19] } {/theRegisters/\registers_reg[19][1] } {/theRegisters/\registers_reg[19][20] } {/theRegisters/\registers_reg[19][21] } {/theRegisters/\registers_reg[19][22] } {/theRegisters/\registers_reg[19][23] } {/theRegisters/\registers_reg[19][24] } {/theRegisters/\registers_reg[19][25] } {/theRegisters/\registers_reg[19][26] } {/theRegisters/\registers_reg[19][27] } {/theRegisters/\registers_reg[19][28] } {/theRegisters/\registers_reg[19][29] } {/theRegisters/\registers_reg[19][2] } {/theRegisters/\registers_reg[19][30] } {/theRegisters/\registers_reg[19][31] } {/theRegisters/\registers_reg[19][3] } {/theRegisters/\registers_reg[19][4] } {/theRegisters/\registers_reg[19][5] } {/theRegisters/\registers_reg[19][6] } {/theRegisters/\registers_reg[19][7] } {/theRegisters/\registers_reg[19][8] } {/theRegisters/\registers_reg[19][9] } {/theRegisters/\registers_reg[1][0] } {/theRegisters/\registers_reg[1][10] } {/theRegisters/\registers_reg[1][11] } {/theRegisters/\registers_reg[1][12] } {/theRegisters/\registers_reg[1][13] } {/theRegisters/\registers_reg[1][14] } {/theRegisters/\registers_reg[1][15] } {/theRegisters/\registers_reg[1][16] } {/theRegisters/\registers_reg[1][17] } {/theRegisters/\registers_reg[1][18] } {/theRegisters/\registers_reg[1][19] } {/theRegisters/\registers_reg[1][1] } {/theRegisters/\registers_reg[1][20] } {/theRegisters/\registers_reg[1][21] } {/theRegisters/\registers_reg[1][22] } {/theRegisters/\registers_reg[1][23] } {/theRegisters/\registers_reg[1][24] } {/theRegisters/\registers_reg[1][25] } {/theRegisters/\registers_reg[1][26] } {/theRegisters/\registers_reg[1][27] } {/theRegisters/\registers_reg[1][28] } {/theRegisters/\registers_reg[1][29] } {/theRegisters/\registers_reg[1][2] } {/theRegisters/\registers_reg[1][30] } {/theRegisters/\registers_reg[1][31] } {/theRegisters/\registers_reg[1][3] } {/theRegisters/\registers_reg[1][4] } {/theRegisters/\registers_reg[1][5] } {/theRegisters/\registers_reg[1][6] } {/theRegisters/\registers_reg[1][7] } {/theRegisters/\registers_reg[1][8] } {/theRegisters/\registers_reg[1][9] } {/theRegisters/\registers_reg[20][0] } {/theRegisters/\registers_reg[20][10] } {/theRegisters/\registers_reg[20][11] } {/theRegisters/\registers_reg[20][12] } {/theRegisters/\registers_reg[20][13] } {/theRegisters/\registers_reg[20][14] } {/theRegisters/\registers_reg[20][15] } {/theRegisters/\registers_reg[20][16] } {/theRegisters/\registers_reg[20][17] } {/theRegisters/\registers_reg[20][18] } {/theRegisters/\registers_reg[20][19] } {/theRegisters/\registers_reg[20][1] } {/theRegisters/\registers_reg[20][20] } {/theRegisters/\registers_reg[20][21] } {/theRegisters/\registers_reg[20][22] } {/theRegisters/\registers_reg[20][23] } {/theRegisters/\registers_reg[20][24] } {/theRegisters/\registers_reg[20][25] } {/theRegisters/\registers_reg[20][26] } {/theRegisters/\registers_reg[20][27] } {/theRegisters/\registers_reg[20][28] } {/theRegisters/\registers_reg[20][29] } {/theRegisters/\registers_reg[20][2] } {/theRegisters/\registers_reg[20][30] } {/theRegisters/\registers_reg[20][31] } {/theRegisters/\registers_reg[20][3] } {/theRegisters/\registers_reg[20][4] } {/theRegisters/\registers_reg[20][5] } {/theRegisters/\registers_reg[20][6] } {/theRegisters/\registers_reg[20][7] } {/theRegisters/\registers_reg[20][8] } {/theRegisters/\registers_reg[20][9] } {/theRegisters/\registers_reg[21][0] } {/theRegisters/\registers_reg[21][10] } {/theRegisters/\registers_reg[21][11] } {/theRegisters/\registers_reg[21][12] } {/theRegisters/\registers_reg[21][13] } {/theRegisters/\registers_reg[21][14] } {/theRegisters/\registers_reg[21][15] } {/theRegisters/\registers_reg[21][16] } {/theRegisters/\registers_reg[21][17] } {/theRegisters/\registers_reg[21][18] } {/theRegisters/\registers_reg[21][19] } {/theRegisters/\registers_reg[21][1] } {/theRegisters/\registers_reg[21][20] } {/theRegisters/\registers_reg[21][21] } {/theRegisters/\registers_reg[21][22] } {/theRegisters/\registers_reg[21][23] } {/theRegisters/\registers_reg[21][24] } {/theRegisters/\registers_reg[21][25] } {/theRegisters/\registers_reg[21][26] } {/theRegisters/\registers_reg[21][27] } {/theRegisters/\registers_reg[21][28] } {/theRegisters/\registers_reg[21][29] } {/theRegisters/\registers_reg[21][2] } {/theRegisters/\registers_reg[21][30] } {/theRegisters/\registers_reg[21][31] } {/theRegisters/\registers_reg[21][3] } {/theRegisters/\registers_reg[21][4] } {/theRegisters/\registers_reg[21][5] } {/theRegisters/\registers_reg[21][6] } {/theRegisters/\registers_reg[21][7] } {/theRegisters/\registers_reg[21][8] } {/theRegisters/\registers_reg[21][9] } {/theRegisters/\registers_reg[22][0] } {/theRegisters/\registers_reg[22][10] } {/theRegisters/\registers_reg[22][11] } {/theRegisters/\registers_reg[22][12] } {/theRegisters/\registers_reg[22][13] } {/theRegisters/\registers_reg[22][14] } {/theRegisters/\registers_reg[22][15] } {/theRegisters/\registers_reg[22][16] } {/theRegisters/\registers_reg[22][17] } {/theRegisters/\registers_reg[22][18] } {/theRegisters/\registers_reg[22][19] } {/theRegisters/\registers_reg[22][1] } {/theRegisters/\registers_reg[22][20] } {/theRegisters/\registers_reg[22][21] } {/theRegisters/\registers_reg[22][22] } {/theRegisters/\registers_reg[22][23] } {/theRegisters/\registers_reg[22][24] } {/theRegisters/\registers_reg[22][25] } {/theRegisters/\registers_reg[22][26] } {/theRegisters/\registers_reg[22][27] } {/theRegisters/\registers_reg[22][28] } {/theRegisters/\registers_reg[22][29] } {/theRegisters/\registers_reg[22][2] } {/theRegisters/\registers_reg[22][30] } {/theRegisters/\registers_reg[22][31] } {/theRegisters/\registers_reg[22][3] } {/theRegisters/\registers_reg[22][4] } {/theRegisters/\registers_reg[22][5] } {/theRegisters/\registers_reg[22][6] } {/theRegisters/\registers_reg[22][7] } {/theRegisters/\registers_reg[22][8] } {/theRegisters/\registers_reg[22][9] } {/theRegisters/\registers_reg[23][0] } {/theRegisters/\registers_reg[23][10] } {/theRegisters/\registers_reg[23][11] } {/theRegisters/\registers_reg[23][12] } {/theRegisters/\registers_reg[23][13] } {/theRegisters/\registers_reg[23][14] } {/theRegisters/\registers_reg[23][15] } {/theRegisters/\registers_reg[23][16] } {/theRegisters/\registers_reg[23][17] } {/theRegisters/\registers_reg[23][18] } {/theRegisters/\registers_reg[23][19] } {/theRegisters/\registers_reg[23][1] } {/theRegisters/\registers_reg[23][20] } {/theRegisters/\registers_reg[23][21] } {/theRegisters/\registers_reg[23][22] } {/theRegisters/\registers_reg[23][23] } {/theRegisters/\registers_reg[23][24] } {/theRegisters/\registers_reg[23][25] } {/theRegisters/\registers_reg[23][26] } {/theRegisters/\registers_reg[23][27] } {/theRegisters/\registers_reg[23][28] } {/theRegisters/\registers_reg[23][29] } {/theRegisters/\registers_reg[23][2] } {/theRegisters/\registers_reg[23][30] } {/theRegisters/\registers_reg[23][31] } {/theRegisters/\registers_reg[23][3] } {/theRegisters/\registers_reg[23][4] } {/theRegisters/\registers_reg[23][5] } {/theRegisters/\registers_reg[23][6] } {/theRegisters/\registers_reg[23][7] } {/theRegisters/\registers_reg[23][8] } {/theRegisters/\registers_reg[23][9] } " -si_connections "SI_2 " -so_connections "SO_2 " -chain_count 1 +// sub-command: create_scan_chain_family scanChain_3 -include_elements "{/theRegisters/\registers_reg[24][0] } {/theRegisters/\registers_reg[24][10] } {/theRegisters/\registers_reg[24][11] } {/theRegisters/\registers_reg[24][12] } {/theRegisters/\registers_reg[24][13] } {/theRegisters/\registers_reg[24][14] } {/theRegisters/\registers_reg[24][15] } {/theRegisters/\registers_reg[24][16] } {/theRegisters/\registers_reg[24][17] } {/theRegisters/\registers_reg[24][18] } {/theRegisters/\registers_reg[24][19] } {/theRegisters/\registers_reg[24][1] } {/theRegisters/\registers_reg[24][20] } {/theRegisters/\registers_reg[24][21] } {/theRegisters/\registers_reg[24][22] } {/theRegisters/\registers_reg[24][23] } {/theRegisters/\registers_reg[24][24] } {/theRegisters/\registers_reg[24][25] } {/theRegisters/\registers_reg[24][26] } {/theRegisters/\registers_reg[24][27] } {/theRegisters/\registers_reg[24][28] } {/theRegisters/\registers_reg[24][29] } {/theRegisters/\registers_reg[24][2] } {/theRegisters/\registers_reg[24][30] } {/theRegisters/\registers_reg[24][31] } {/theRegisters/\registers_reg[24][3] } {/theRegisters/\registers_reg[24][4] } {/theRegisters/\registers_reg[24][5] } {/theRegisters/\registers_reg[24][6] } {/theRegisters/\registers_reg[24][7] } {/theRegisters/\registers_reg[24][8] } {/theRegisters/\registers_reg[24][9] } {/theRegisters/\registers_reg[25][0] } {/theRegisters/\registers_reg[25][10] } {/theRegisters/\registers_reg[25][11] } {/theRegisters/\registers_reg[25][12] } {/theRegisters/\registers_reg[25][13] } {/theRegisters/\registers_reg[25][14] } {/theRegisters/\registers_reg[25][15] } {/theRegisters/\registers_reg[25][16] } {/theRegisters/\registers_reg[25][17] } {/theRegisters/\registers_reg[25][18] } {/theRegisters/\registers_reg[25][19] } {/theRegisters/\registers_reg[25][1] } {/theRegisters/\registers_reg[25][20] } {/theRegisters/\registers_reg[25][21] } {/theRegisters/\registers_reg[25][22] } {/theRegisters/\registers_reg[25][23] } {/theRegisters/\registers_reg[25][24] } {/theRegisters/\registers_reg[25][25] } {/theRegisters/\registers_reg[25][26] } {/theRegisters/\registers_reg[25][27] } {/theRegisters/\registers_reg[25][28] } {/theRegisters/\registers_reg[25][29] } {/theRegisters/\registers_reg[25][2] } {/theRegisters/\registers_reg[25][30] } {/theRegisters/\registers_reg[25][31] } {/theRegisters/\registers_reg[25][3] } {/theRegisters/\registers_reg[25][4] } {/theRegisters/\registers_reg[25][5] } {/theRegisters/\registers_reg[25][6] } {/theRegisters/\registers_reg[25][7] } {/theRegisters/\registers_reg[25][8] } {/theRegisters/\registers_reg[25][9] } {/theRegisters/\registers_reg[26][0] } {/theRegisters/\registers_reg[26][10] } {/theRegisters/\registers_reg[26][11] } {/theRegisters/\registers_reg[26][12] } {/theRegisters/\registers_reg[26][13] } {/theRegisters/\registers_reg[26][14] } {/theRegisters/\registers_reg[26][15] } {/theRegisters/\registers_reg[26][16] } {/theRegisters/\registers_reg[26][17] } {/theRegisters/\registers_reg[26][18] } {/theRegisters/\registers_reg[26][19] } {/theRegisters/\registers_reg[26][1] } {/theRegisters/\registers_reg[26][20] } {/theRegisters/\registers_reg[26][21] } {/theRegisters/\registers_reg[26][22] } {/theRegisters/\registers_reg[26][23] } {/theRegisters/\registers_reg[26][24] } {/theRegisters/\registers_reg[26][25] } {/theRegisters/\registers_reg[26][26] } {/theRegisters/\registers_reg[26][27] } {/theRegisters/\registers_reg[26][28] } {/theRegisters/\registers_reg[26][29] } {/theRegisters/\registers_reg[26][2] } {/theRegisters/\registers_reg[26][30] } {/theRegisters/\registers_reg[26][31] } {/theRegisters/\registers_reg[26][3] } {/theRegisters/\registers_reg[26][4] } {/theRegisters/\registers_reg[26][5] } {/theRegisters/\registers_reg[26][6] } {/theRegisters/\registers_reg[26][7] } {/theRegisters/\registers_reg[26][8] } {/theRegisters/\registers_reg[26][9] } {/theRegisters/\registers_reg[27][0] } {/theRegisters/\registers_reg[27][10] } {/theRegisters/\registers_reg[27][11] } {/theRegisters/\registers_reg[27][12] } {/theRegisters/\registers_reg[27][13] } {/theRegisters/\registers_reg[27][14] } {/theRegisters/\registers_reg[27][15] } {/theRegisters/\registers_reg[27][16] } {/theRegisters/\registers_reg[27][17] } {/theRegisters/\registers_reg[27][18] } {/theRegisters/\registers_reg[27][19] } {/theRegisters/\registers_reg[27][1] } {/theRegisters/\registers_reg[27][20] } {/theRegisters/\registers_reg[27][21] } {/theRegisters/\registers_reg[27][22] } {/theRegisters/\registers_reg[27][23] } {/theRegisters/\registers_reg[27][24] } {/theRegisters/\registers_reg[27][25] } {/theRegisters/\registers_reg[27][26] } {/theRegisters/\registers_reg[27][27] } {/theRegisters/\registers_reg[27][28] } {/theRegisters/\registers_reg[27][29] } {/theRegisters/\registers_reg[27][2] } {/theRegisters/\registers_reg[27][30] } {/theRegisters/\registers_reg[27][31] } {/theRegisters/\registers_reg[27][3] } {/theRegisters/\registers_reg[27][4] } {/theRegisters/\registers_reg[27][5] } {/theRegisters/\registers_reg[27][6] } {/theRegisters/\registers_reg[27][7] } {/theRegisters/\registers_reg[27][8] } {/theRegisters/\registers_reg[27][9] } {/theRegisters/\registers_reg[28][0] } {/theRegisters/\registers_reg[28][10] } {/theRegisters/\registers_reg[28][11] } {/theRegisters/\registers_reg[28][12] } {/theRegisters/\registers_reg[28][13] } {/theRegisters/\registers_reg[28][14] } {/theRegisters/\registers_reg[28][15] } {/theRegisters/\registers_reg[28][16] } {/theRegisters/\registers_reg[28][17] } {/theRegisters/\registers_reg[28][18] } {/theRegisters/\registers_reg[28][19] } {/theRegisters/\registers_reg[28][1] } {/theRegisters/\registers_reg[28][20] } {/theRegisters/\registers_reg[28][21] } {/theRegisters/\registers_reg[28][22] } {/theRegisters/\registers_reg[28][23] } {/theRegisters/\registers_reg[28][24] } {/theRegisters/\registers_reg[28][25] } {/theRegisters/\registers_reg[28][26] } {/theRegisters/\registers_reg[28][27] } {/theRegisters/\registers_reg[28][28] } {/theRegisters/\registers_reg[28][29] } {/theRegisters/\registers_reg[28][2] } {/theRegisters/\registers_reg[28][30] } {/theRegisters/\registers_reg[28][31] } {/theRegisters/\registers_reg[28][3] } {/theRegisters/\registers_reg[28][4] } {/theRegisters/\registers_reg[28][5] } {/theRegisters/\registers_reg[28][6] } {/theRegisters/\registers_reg[28][7] } {/theRegisters/\registers_reg[28][8] } {/theRegisters/\registers_reg[28][9] } {/theRegisters/\registers_reg[29][0] } {/theRegisters/\registers_reg[29][10] } {/theRegisters/\registers_reg[29][11] } {/theRegisters/\registers_reg[29][12] } {/theRegisters/\registers_reg[29][13] } {/theRegisters/\registers_reg[29][14] } {/theRegisters/\registers_reg[29][15] } {/theRegisters/\registers_reg[29][16] } {/theRegisters/\registers_reg[29][17] } {/theRegisters/\registers_reg[29][18] } {/theRegisters/\registers_reg[29][19] } {/theRegisters/\registers_reg[29][1] } {/theRegisters/\registers_reg[29][20] } {/theRegisters/\registers_reg[29][21] } {/theRegisters/\registers_reg[29][22] } {/theRegisters/\registers_reg[29][23] } {/theRegisters/\registers_reg[29][24] } {/theRegisters/\registers_reg[29][25] } {/theRegisters/\registers_reg[29][26] } {/theRegisters/\registers_reg[29][27] } {/theRegisters/\registers_reg[29][28] } {/theRegisters/\registers_reg[29][29] } {/theRegisters/\registers_reg[29][2] } {/theRegisters/\registers_reg[29][30] } {/theRegisters/\registers_reg[29][31] } {/theRegisters/\registers_reg[29][3] } {/theRegisters/\registers_reg[29][4] } {/theRegisters/\registers_reg[29][5] } {/theRegisters/\registers_reg[29][6] } {/theRegisters/\registers_reg[29][7] } {/theRegisters/\registers_reg[29][8] } {/theRegisters/\registers_reg[29][9] } {/theRegisters/\registers_reg[2][0] } {/theRegisters/\registers_reg[2][10] } {/theRegisters/\registers_reg[2][11] } {/theRegisters/\registers_reg[2][12] } {/theRegisters/\registers_reg[2][13] } {/theRegisters/\registers_reg[2][14] } {/theRegisters/\registers_reg[2][15] } {/theRegisters/\registers_reg[2][16] } {/theRegisters/\registers_reg[2][17] } {/theRegisters/\registers_reg[2][18] } {/theRegisters/\registers_reg[2][19] } {/theRegisters/\registers_reg[2][1] } {/theRegisters/\registers_reg[2][20] } {/theRegisters/\registers_reg[2][21] } {/theRegisters/\registers_reg[2][22] } {/theRegisters/\registers_reg[2][23] } {/theRegisters/\registers_reg[2][24] } {/theRegisters/\registers_reg[2][25] } {/theRegisters/\registers_reg[2][26] } {/theRegisters/\registers_reg[2][27] } {/theRegisters/\registers_reg[2][28] } {/theRegisters/\registers_reg[2][29] } {/theRegisters/\registers_reg[2][2] } {/theRegisters/\registers_reg[2][30] } {/theRegisters/\registers_reg[2][31] } {/theRegisters/\registers_reg[2][3] } {/theRegisters/\registers_reg[2][4] } {/theRegisters/\registers_reg[2][5] } {/theRegisters/\registers_reg[2][6] } {/theRegisters/\registers_reg[2][7] } {/theRegisters/\registers_reg[2][8] } {/theRegisters/\registers_reg[2][9] } {/theRegisters/\registers_reg[30][0] } {/theRegisters/\registers_reg[30][10] } {/theRegisters/\registers_reg[30][11] } {/theRegisters/\registers_reg[30][12] } {/theRegisters/\registers_reg[30][13] } {/theRegisters/\registers_reg[30][14] } {/theRegisters/\registers_reg[30][15] } {/theRegisters/\registers_reg[30][16] } {/theRegisters/\registers_reg[30][17] } {/theRegisters/\registers_reg[30][18] } {/theRegisters/\registers_reg[30][19] } {/theRegisters/\registers_reg[30][1] } {/theRegisters/\registers_reg[30][20] } {/theRegisters/\registers_reg[30][21] } {/theRegisters/\registers_reg[30][22] } {/theRegisters/\registers_reg[30][23] } {/theRegisters/\registers_reg[30][24] } {/theRegisters/\registers_reg[30][25] } {/theRegisters/\registers_reg[30][26] } {/theRegisters/\registers_reg[30][27] } {/theRegisters/\registers_reg[30][28] } {/theRegisters/\registers_reg[30][29] } {/theRegisters/\registers_reg[30][2] } {/theRegisters/\registers_reg[30][30] } {/theRegisters/\registers_reg[30][31] } {/theRegisters/\registers_reg[30][3] } {/theRegisters/\registers_reg[30][4] } {/theRegisters/\registers_reg[30][5] } {/theRegisters/\registers_reg[30][6] } {/theRegisters/\registers_reg[30][7] } {/theRegisters/\registers_reg[30][8] } {/theRegisters/\registers_reg[30][9] } " -si_connections "SI_3 " -so_connections "SO_3 " -chain_count 1 +// sub-command: create_scan_chain_family scanChain_4 -include_elements "{/theRegisters/\registers_reg[31][0] } {/theRegisters/\registers_reg[31][10] } {/theRegisters/\registers_reg[31][11] } {/theRegisters/\registers_reg[31][12] } {/theRegisters/\registers_reg[31][13] } {/theRegisters/\registers_reg[31][14] } {/theRegisters/\registers_reg[31][15] } {/theRegisters/\registers_reg[31][16] } {/theRegisters/\registers_reg[31][17] } {/theRegisters/\registers_reg[31][18] } {/theRegisters/\registers_reg[31][19] } {/theRegisters/\registers_reg[31][1] } {/theRegisters/\registers_reg[31][20] } {/theRegisters/\registers_reg[31][21] } {/theRegisters/\registers_reg[31][22] } {/theRegisters/\registers_reg[31][23] } {/theRegisters/\registers_reg[31][24] } {/theRegisters/\registers_reg[31][25] } {/theRegisters/\registers_reg[31][26] } {/theRegisters/\registers_reg[31][27] } {/theRegisters/\registers_reg[31][28] } {/theRegisters/\registers_reg[31][29] } {/theRegisters/\registers_reg[31][2] } {/theRegisters/\registers_reg[31][30] } {/theRegisters/\registers_reg[31][31] } {/theRegisters/\registers_reg[31][3] } {/theRegisters/\registers_reg[31][4] } {/theRegisters/\registers_reg[31][5] } {/theRegisters/\registers_reg[31][6] } {/theRegisters/\registers_reg[31][7] } {/theRegisters/\registers_reg[31][8] } {/theRegisters/\registers_reg[31][9] } {/theRegisters/\registers_reg[3][0] } {/theRegisters/\registers_reg[3][10] } {/theRegisters/\registers_reg[3][11] } {/theRegisters/\registers_reg[3][12] } {/theRegisters/\registers_reg[3][13] } {/theRegisters/\registers_reg[3][14] } {/theRegisters/\registers_reg[3][15] } {/theRegisters/\registers_reg[3][16] } {/theRegisters/\registers_reg[3][17] } {/theRegisters/\registers_reg[3][18] } {/theRegisters/\registers_reg[3][19] } {/theRegisters/\registers_reg[3][1] } {/theRegisters/\registers_reg[3][20] } {/theRegisters/\registers_reg[3][21] } {/theRegisters/\registers_reg[3][22] } {/theRegisters/\registers_reg[3][23] } {/theRegisters/\registers_reg[3][24] } {/theRegisters/\registers_reg[3][25] } {/theRegisters/\registers_reg[3][26] } {/theRegisters/\registers_reg[3][27] } {/theRegisters/\registers_reg[3][28] } {/theRegisters/\registers_reg[3][29] } {/theRegisters/\registers_reg[3][2] } {/theRegisters/\registers_reg[3][30] } {/theRegisters/\registers_reg[3][31] } {/theRegisters/\registers_reg[3][3] } {/theRegisters/\registers_reg[3][4] } {/theRegisters/\registers_reg[3][5] } {/theRegisters/\registers_reg[3][6] } {/theRegisters/\registers_reg[3][7] } {/theRegisters/\registers_reg[3][8] } {/theRegisters/\registers_reg[3][9] } {/theRegisters/\registers_reg[4][0] } {/theRegisters/\registers_reg[4][10] } {/theRegisters/\registers_reg[4][11] } {/theRegisters/\registers_reg[4][12] } {/theRegisters/\registers_reg[4][13] } {/theRegisters/\registers_reg[4][14] } {/theRegisters/\registers_reg[4][15] } {/theRegisters/\registers_reg[4][16] } {/theRegisters/\registers_reg[4][17] } {/theRegisters/\registers_reg[4][18] } {/theRegisters/\registers_reg[4][19] } {/theRegisters/\registers_reg[4][1] } {/theRegisters/\registers_reg[4][20] } {/theRegisters/\registers_reg[4][21] } {/theRegisters/\registers_reg[4][22] } {/theRegisters/\registers_reg[4][23] } {/theRegisters/\registers_reg[4][24] } {/theRegisters/\registers_reg[4][25] } {/theRegisters/\registers_reg[4][26] } {/theRegisters/\registers_reg[4][27] } {/theRegisters/\registers_reg[4][28] } {/theRegisters/\registers_reg[4][29] } {/theRegisters/\registers_reg[4][2] } {/theRegisters/\registers_reg[4][30] } {/theRegisters/\registers_reg[4][31] } {/theRegisters/\registers_reg[4][3] } {/theRegisters/\registers_reg[4][4] } {/theRegisters/\registers_reg[4][5] } {/theRegisters/\registers_reg[4][6] } {/theRegisters/\registers_reg[4][7] } {/theRegisters/\registers_reg[4][8] } {/theRegisters/\registers_reg[4][9] } {/theRegisters/\registers_reg[5][0] } {/theRegisters/\registers_reg[5][10] } {/theRegisters/\registers_reg[5][11] } {/theRegisters/\registers_reg[5][12] } {/theRegisters/\registers_reg[5][13] } {/theRegisters/\registers_reg[5][14] } {/theRegisters/\registers_reg[5][15] } {/theRegisters/\registers_reg[5][16] } {/theRegisters/\registers_reg[5][17] } {/theRegisters/\registers_reg[5][18] } {/theRegisters/\registers_reg[5][19] } {/theRegisters/\registers_reg[5][1] } {/theRegisters/\registers_reg[5][20] } {/theRegisters/\registers_reg[5][21] } {/theRegisters/\registers_reg[5][22] } {/theRegisters/\registers_reg[5][23] } {/theRegisters/\registers_reg[5][24] } {/theRegisters/\registers_reg[5][25] } {/theRegisters/\registers_reg[5][26] } {/theRegisters/\registers_reg[5][27] } {/theRegisters/\registers_reg[5][28] } {/theRegisters/\registers_reg[5][29] } {/theRegisters/\registers_reg[5][2] } {/theRegisters/\registers_reg[5][30] } {/theRegisters/\registers_reg[5][31] } {/theRegisters/\registers_reg[5][3] } {/theRegisters/\registers_reg[5][4] } {/theRegisters/\registers_reg[5][5] } {/theRegisters/\registers_reg[5][6] } {/theRegisters/\registers_reg[5][7] } {/theRegisters/\registers_reg[5][8] } {/theRegisters/\registers_reg[5][9] } {/theRegisters/\registers_reg[6][0] } {/theRegisters/\registers_reg[6][10] } {/theRegisters/\registers_reg[6][11] } {/theRegisters/\registers_reg[6][12] } {/theRegisters/\registers_reg[6][13] } {/theRegisters/\registers_reg[6][14] } {/theRegisters/\registers_reg[6][15] } {/theRegisters/\registers_reg[6][16] } {/theRegisters/\registers_reg[6][17] } {/theRegisters/\registers_reg[6][18] } {/theRegisters/\registers_reg[6][19] } {/theRegisters/\registers_reg[6][1] } {/theRegisters/\registers_reg[6][20] } {/theRegisters/\registers_reg[6][21] } {/theRegisters/\registers_reg[6][22] } {/theRegisters/\registers_reg[6][23] } {/theRegisters/\registers_reg[6][24] } {/theRegisters/\registers_reg[6][25] } {/theRegisters/\registers_reg[6][26] } {/theRegisters/\registers_reg[6][27] } {/theRegisters/\registers_reg[6][28] } {/theRegisters/\registers_reg[6][29] } {/theRegisters/\registers_reg[6][2] } {/theRegisters/\registers_reg[6][30] } {/theRegisters/\registers_reg[6][31] } {/theRegisters/\registers_reg[6][3] } {/theRegisters/\registers_reg[6][4] } {/theRegisters/\registers_reg[6][5] } {/theRegisters/\registers_reg[6][6] } {/theRegisters/\registers_reg[6][7] } {/theRegisters/\registers_reg[6][8] } {/theRegisters/\registers_reg[6][9] } {/theRegisters/\registers_reg[7][0] } {/theRegisters/\registers_reg[7][10] } {/theRegisters/\registers_reg[7][11] } {/theRegisters/\registers_reg[7][12] } {/theRegisters/\registers_reg[7][13] } {/theRegisters/\registers_reg[7][14] } {/theRegisters/\registers_reg[7][15] } {/theRegisters/\registers_reg[7][16] } {/theRegisters/\registers_reg[7][17] } {/theRegisters/\registers_reg[7][18] } {/theRegisters/\registers_reg[7][19] } {/theRegisters/\registers_reg[7][1] } {/theRegisters/\registers_reg[7][20] } {/theRegisters/\registers_reg[7][21] } {/theRegisters/\registers_reg[7][22] } {/theRegisters/\registers_reg[7][23] } {/theRegisters/\registers_reg[7][24] } {/theRegisters/\registers_reg[7][25] } {/theRegisters/\registers_reg[7][26] } {/theRegisters/\registers_reg[7][27] } {/theRegisters/\registers_reg[7][28] } {/theRegisters/\registers_reg[7][29] } {/theRegisters/\registers_reg[7][2] } {/theRegisters/\registers_reg[7][30] } {/theRegisters/\registers_reg[7][31] } {/theRegisters/\registers_reg[7][3] } {/theRegisters/\registers_reg[7][4] } {/theRegisters/\registers_reg[7][5] } {/theRegisters/\registers_reg[7][6] } {/theRegisters/\registers_reg[7][7] } {/theRegisters/\registers_reg[7][8] } {/theRegisters/\registers_reg[7][9] } {/theRegisters/\registers_reg[8][0] } {/theRegisters/\registers_reg[8][10] } {/theRegisters/\registers_reg[8][11] } {/theRegisters/\registers_reg[8][12] } {/theRegisters/\registers_reg[8][13] } {/theRegisters/\registers_reg[8][14] } {/theRegisters/\registers_reg[8][15] } {/theRegisters/\registers_reg[8][16] } {/theRegisters/\registers_reg[8][17] } {/theRegisters/\registers_reg[8][18] } {/theRegisters/\registers_reg[8][19] } {/theRegisters/\registers_reg[8][1] } {/theRegisters/\registers_reg[8][20] } {/theRegisters/\registers_reg[8][21] } {/theRegisters/\registers_reg[8][22] } {/theRegisters/\registers_reg[8][23] } {/theRegisters/\registers_reg[8][24] } {/theRegisters/\registers_reg[8][25] } {/theRegisters/\registers_reg[8][26] } {/theRegisters/\registers_reg[8][27] } {/theRegisters/\registers_reg[8][28] } {/theRegisters/\registers_reg[8][29] } {/theRegisters/\registers_reg[8][2] } {/theRegisters/\registers_reg[8][30] } {/theRegisters/\registers_reg[8][31] } {/theRegisters/\registers_reg[8][3] } {/theRegisters/\registers_reg[8][4] } {/theRegisters/\registers_reg[8][5] } {/theRegisters/\registers_reg[8][6] } {/theRegisters/\registers_reg[8][7] } {/theRegisters/\registers_reg[8][8] } {/theRegisters/\registers_reg[8][9] } {/theRegisters/\registers_reg[9][0] } {/theRegisters/\registers_reg[9][10] } {/theRegisters/\registers_reg[9][11] } {/theRegisters/\registers_reg[9][12] } {/theRegisters/\registers_reg[9][13] } {/theRegisters/\registers_reg[9][14] } {/theRegisters/\registers_reg[9][15] } {/theRegisters/\registers_reg[9][16] } {/theRegisters/\registers_reg[9][17] } {/theRegisters/\registers_reg[9][18] } {/theRegisters/\registers_reg[9][19] } {/theRegisters/\registers_reg[9][1] } {/theRegisters/\registers_reg[9][20] } {/theRegisters/\registers_reg[9][21] } {/theRegisters/\registers_reg[9][22] } {/theRegisters/\registers_reg[9][23] } {/theRegisters/\registers_reg[9][24] } {/theRegisters/\registers_reg[9][25] } {/theRegisters/\registers_reg[9][26] } {/theRegisters/\registers_reg[9][27] } {/theRegisters/\registers_reg[9][28] } {/theRegisters/\registers_reg[9][29] } {/theRegisters/\registers_reg[9][2] } {/theRegisters/\registers_reg[9][30] } {/theRegisters/\registers_reg[9][31] } {/theRegisters/\registers_reg[9][3] } {/theRegisters/\registers_reg[9][4] } {/theRegisters/\registers_reg[9][5] } {/theRegisters/\registers_reg[9][6] } {/theRegisters/\registers_reg[9][7] } {/theRegisters/\registers_reg[9][8] } {/theRegisters/\registers_reg[9][9] } " -si_connections "SI_4 " -so_connections "SO_4 " -chain_count 1 +// sub-command: analyze_scan_chains +// Chain allocation of 'unwrapped' mode completed: +// 4 distributed chains of size 256 +// sub-command: insert_test_logic -write_in_tsdb on +============================= +Test Logic Insertion Summary: +============================= + + Structural Data: + ---------------- + Added top-level port count: 0 + Added instance count: 8 + + Logical Data: + ------------- + Added retiming logic count: 4 + Added scan chain count (unwrapped): 4 + +// Warning: Flattened model deleted. +// +// Writing out netlist and related files in /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.03/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design +// sub-command: report_scan_chains + +=============================== +Scan Chains Created by the Tool +=============================== + + Scan mode 'unwrapped' scan chains: + ---------------------------------- + + Cluster 'scanChain_1' chains: + ----------------------------- + chain = scanChain_1 group = dummy input = /SI_1 output = /SO_1 length = 256 + + Cluster 'scanChain_2' chains: + ----------------------------- + chain = scanChain_2 group = dummy input = /SI_2 output = /SO_2 length = 256 + + Cluster 'scanChain_3' chains: + ----------------------------- + chain = scanChain_3 group = dummy input = /SI_3 output = /SO_3 length = 256 + + Cluster 'scanChain_4' chains: + ----------------------------- + chain = scanChain_4 group = dummy input = /SI_4 output = /SO_4 length = 256 + + +// sub-command: write_scan_order /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.03/Scan_0/cpu.scandef -use_escaping_rule Lefdef -replace +// sub-command: write_design -output_file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.03/Scan_0/post_scan.v -replace +// command: exit + +************************************************************************************************************************************************************************************** + TESSENT EXECUTION ENDS HERE ! +************************************************************************************************************************************************************************************** + +Dumping current design to /tmp/oasys.2568101/dft_eco/cpu +> write_db /tmp/oasys.2568101/dft_eco/cpu +info: Target library/cell information has changed that further may change timing results. [TA-159] +info: Successfully traced scan chain (scan_in: 'SI_1', scan_out: 'SO_1' with 258 elements ) [DFT-354] +info: Successfully traced scan chain (scan_in: 'SI_2', scan_out: 'SO_2' with 258 elements ) [DFT-354] +info: Successfully traced scan chain (scan_in: 'SI_3', scan_out: 'SO_3' with 258 elements ) [DFT-354] +info: Successfully traced scan chain (scan_in: 'SI_4', scan_out: 'SO_4' with 258 elements ) [DFT-354] +> write_db ./output/odb/riscv.tessent_post_scan.odb +> write_verilog ./output/riscv.tessent_post_scan.v +info: writing Verilog file './output/riscv.tessent_post_scan.v' for module 'cpu' [WRITE-100] + +----------report_power---------------- +> report_power +Report Power (instances with prefix '*' are included in total) : +-----+----------------------------------------+--------------------+---------------------+-------------------+----------------- + | Instance | Internal Power (uW)| Switching Power (uW)| Leakage Power (uW)| Total Power (uW) +-----+----------------------------------------+--------------------+---------------------+-------------------+----------------- +1 |*theMem | 4965.347656| 97.271141| 528.368530| 5590.987793 +2 |*theRegisters | 2937.847412| 65.430710| 75.000534| 3078.278564 +3 |*theDecoder | 3306.815674| 29.696104| 69.466927| 3405.978516 +4 |*thePC_i_0 | 102.036263| 0.516853| 0.818020| 103.371140 +5 |*thePC_CurrentPC_reg[31] | 6.132826| 0.115208| 0.000019| 6.248054 +6 |*thePC_CurrentPC_reg[30] | 6.132829| 0.122289| 0.000019| 6.255136 +7 |*thePC_CurrentPC_reg[29] | 6.132829| 0.122289| 0.000019| 6.255136 +8 |*thePC_CurrentPC_reg[28] | 6.132829| 0.122289| 0.000019| 6.255136 +9 |*thePC_CurrentPC_reg[27] | 6.132829| 0.122289| 0.000019| 6.255136 +10 |*thePC_CurrentPC_reg[26] | 6.132829| 0.122289| 0.000019| 6.255136 +11 |*thePC_CurrentPC_reg[25] | 6.132829| 0.122289| 0.000019| 6.255136 +12 |*thePC_CurrentPC_reg[24] | 6.132829| 0.122289| 0.000019| 6.255136 +13 |*thePC_CurrentPC_reg[23] | 6.132829| 0.122289| 0.000019| 6.255136 +14 |*thePC_CurrentPC_reg[22] | 6.132829| 0.122289| 0.000019| 6.255136 +15 |*thePC_CurrentPC_reg[21] | 6.135628| 0.207666| 0.000019| 6.343312 +16 |*thePC_CurrentPC_reg[20] | 6.132829| 0.122289| 0.000019| 6.255136 +17 |*thePC_CurrentPC_reg[19] | 6.132828| 0.121340| 0.000019| 6.254188 +18 |*thePC_CurrentPC_reg[18] | 6.132828| 0.121340| 0.000019| 6.254188 +19 |*thePC_CurrentPC_reg[17] | 6.132828| 0.121340| 0.000019| 6.254188 +20 |*thePC_CurrentPC_reg[16] | 6.132828| 0.121340| 0.000019| 6.254188 +21 |*thePC_CurrentPC_reg[15] | 6.132826| 0.115029| 0.000019| 6.247873 +22 |*thePC_CurrentPC_reg[14] | 6.132828| 0.121340| 0.000019| 6.254188 +23 |*thePC_CurrentPC_reg[13] | 6.135591| 0.206718| 0.000019| 6.342327 +24 |*thePC_CurrentPC_reg[12] | 6.132828| 0.121340| 0.000019| 6.254188 +25 |*thePC_CurrentPC_reg[11] | 6.132828| 0.120392| 0.000019| 6.253239 +26 |*thePC_CurrentPC_reg[10] | 6.132827| 0.115675| 0.000019| 6.248520 +27 |*thePC_CurrentPC_reg[9] | 6.132827| 0.115675| 0.000019| 6.248520 +28 |*thePC_CurrentPC_reg[8] | 6.132827| 0.115675| 0.000019| 6.248520 +29 |*thePC_CurrentPC_reg[7] | 6.132825| 0.109358| 0.000019| 6.242202 +30 |*thePC_CurrentPC_reg[6] | 6.132825| 0.109358| 0.000019| 6.242202 +31 |*thePC_CurrentPC_reg[5] | 6.132825| 0.109358| 0.000019| 6.242202 +32 |*thePC_CurrentPC_reg[4] | 6.132825| 0.109358| 0.000019| 6.242202 +33 |*thePC_CurrentPC_reg[3] | 6.132825| 0.109358| 0.000019| 6.242202 +34 |*thePC_CurrentPC_reg[2] | 6.136212| 0.222482| 0.000019| 6.358713 +35 |*thePC_CurrentPC_reg[1] | 6.132825| 0.110713| 0.000019| 6.243557 +36 |*thePC_CurrentPC_reg[0] | 6.132828| 0.121456| 0.000019| 6.254303 +37 |*i_0_0_0 | 3.636180| 0.005795| 0.056141| 3.698117 +38 |*i_0_0_1 | 3.630034| 0.075574| 0.049831| 3.755438 +39 |*i_0_0_2 | 3.589001| 0.005720| 0.056141| 3.650862 +40 |*i_0_0_3 | 3.579433| 0.074593| 0.049831| 3.703857 +41 |*i_0_0_4 | 4.765921| 0.005811| 0.038697| 4.810430 +42 |*i_0_0_5 | 4.765921| 0.005811| 0.038697| 4.810430 +43 |*i_0_0_6 | 4.765921| 0.005811| 0.038697| 4.810430 +44 |*i_0_0_7 | 4.765921| 0.005811| 0.038697| 4.810430 +45 |*i_0_0_8 | 4.765921| 0.005811| 0.038697| 4.810430 +46 |*i_0_0_9 | 4.765921| 0.005811| 0.038697| 4.810430 +47 |*i_0_0_10 | 4.760734| 0.005811| 0.038697| 4.805242 +48 |*i_0_0_11 | 4.760734| 0.005811| 0.038697| 4.805242 +49 |*i_0_0_12 | 4.760734| 0.005811| 0.038697| 4.805242 +50 |*i_0_0_13 | 4.760734| 0.005811| 0.038697| 4.805242 +51 |*i_0_0_14 | 4.760734| 0.005811| 0.038697| 4.805242 +52 |*i_0_0_15 | 3.589408| 0.005721| 0.056141| 3.651270 +53 |*i_0_0_16 | 3.579309| 0.074602| 0.049831| 3.703742 +54 |*i_0_0_17 | 3.589739| 0.005721| 0.056141| 3.651601 +55 |*i_0_0_18 | 3.579648| 0.074608| 0.049831| 3.704087 +56 |*i_0_0_19 | 3.590052| 0.005722| 0.056141| 3.651915 +57 |*i_0_0_20 | 3.579969| 0.074615| 0.049831| 3.704415 +58 |*i_0_0_21 | 3.590306| 0.005722| 0.056141| 3.652169 +59 |*i_0_0_22 | 3.580231| 0.074620| 0.049831| 3.704682 +60 |*i_0_0_23 | 3.590506| 0.005722| 0.056141| 3.652370 +61 |*i_0_0_24 | 3.580436| 0.074625| 0.049831| 3.704891 +62 |*i_0_0_25 | 3.590656| 0.005723| 0.056141| 3.652520 +63 |*i_0_0_26 | 3.580589| 0.074627| 0.049831| 3.705047 +64 |*i_0_0_27 | 3.590823| 0.005723| 0.056141| 3.652687 +65 |*i_0_0_28 | 3.580760| 0.074631| 0.049831| 3.705222 +66 |*i_0_0_29 | 3.590933| 0.005723| 0.056141| 3.652797 +67 |*i_0_0_30 | 3.580874| 0.074633| 0.049831| 3.705338 +68 |*i_0_0_31 | 3.590987| 0.005723| 0.056141| 3.652852 +69 |*i_0_0_32 | 3.580929| 0.074634| 0.049831| 3.705395 +70 |*i_0_0_33 | 3.591065| 0.005723| 0.056141| 3.652930 +71 |*i_0_0_34 | 3.581009| 0.074636| 0.049831| 3.705476 +72 |*i_0_0_35 | 3.591195| 0.005724| 0.056141| 3.653060 +73 |*i_0_0_36 | 3.581142| 0.074639| 0.049831| 3.705612 +74 |*i_0_0_37 | 3.591303| 0.005724| 0.056141| 3.653168 +75 |*i_0_0_38 | 3.581253| 0.074641| 0.049831| 3.705725 +76 |*i_0_0_39 | 3.591386| 0.005724| 0.056141| 3.653251 +77 |*i_0_0_40 | 3.581338| 0.074643| 0.049831| 3.705812 +78 |*i_0_0_41 | 3.591435| 0.005724| 0.056141| 3.653301 +79 |*i_0_0_42 | 3.581389| 0.074644| 0.049831| 3.705863 +80 |*i_0_0_43 | 3.591419| 0.005724| 0.056141| 3.653284 +81 |*i_0_0_44 | 3.581372| 0.074644| 0.049831| 3.705847 +82 |*i_0_0_45 | 3.591433| 0.005724| 0.056141| 3.653298 +83 |*i_0_0_46 | 3.581386| 0.074644| 0.049831| 3.705861 +84 |*i_0_0_47 | 3.591558| 0.005724| 0.056141| 3.653424 +85 |*i_0_0_48 | 3.581515| 0.074646| 0.049831| 3.705992 +86 |*i_0_0_49 | 3.591676| 0.005724| 0.056141| 3.653541 +87 |*i_0_0_50 | 3.581635| 0.074649| 0.049831| 3.706115 +88 |*i_0_0_51 | 3.591723| 0.005724| 0.056141| 3.653588 +89 |*i_0_0_52 | 3.581872| 0.074650| 0.049831| 3.706352 +90 |*i_0_0_53 | 0.270481| 0.031764| 0.181711| 0.483956 +91 |*i_0_0_54 | 8.109213| 0.417922| 0.187759| 8.714894 +92 |*i_0_0_55 | 4.662969| 0.392350| 0.167543| 5.222862 +93 |*i_0_0_56 | 4.661758| 0.392909| 0.167809| 5.222477 +94 |*i_0_0_57 | 4.661533| 0.392163| 0.167455| 5.221151 +95 |*i_0_0_58 | 4.661815| 0.393097| 0.167897| 5.222809 +96 |*i_0_0_59 | 4.661477| 0.391976| 0.167366| 5.220819 +97 |*i_0_0_60 | 4.661870| 0.393283| 0.167986| 5.223139 +98 |*i_0_0_61 | 4.263187| 0.064498| 0.029698| 4.357384 +99 |*i_0_0_62 | 4.263187| 0.064498| 0.029698| 4.357384 +100 |*i_0_0_63 | 4.263187| 0.064498| 0.029698| 4.357384 +101 |*i_0_0_64 | 4.263187| 0.064498| 0.029698| 4.357384 +102 |*i_0_0_65 | 4.263187| 0.064498| 0.029698| 4.357384 +103 |*i_0_0_66 | 892.076904| 9.773184| 0.224563| 902.074707 +104 |*tessent_persistent_cell_buf_extsi1225_i| 12.245425| 0.023904| 0.084228| 12.353557 +105 | | | | | +106 |*TOTAL | 12673.386719| 211.656723| 678.138367| 13563.180664 +-----+----------------------------------------+--------------------+---------------------+-------------------+----------------- + +----------report_path_groups---------------- +> report_path_groups +Report Path Groups: +-----+-------+------+---------+--------- + | Path |Weight|Critical |Worst + | Group | |Range(ps)|Slack(ps) +-----+-------+------+---------+--------- +1 |default| 1.000| 0.0| 18131.2 +2 |I2R | 1.000| 0.0| +3 |I2O | 1.000| 0.0| +4 |R2O | 1.000| 0.0| 36309.8 +-----+-------+------+---------+--------- + +----------report_scan_chains---------------- +> report_scan_chains +Report ScanChains: +--------+-----------+--------------+--------+-----------+-----------+--------------+------------------+--------+--------+---------+-----------+---------- + Index | Chain | ScanInstance | Length | TestClock | ClockEdge | Comp. Chains | Max Comp. Length | Lockup | ScanIn | ScanOut | Partition | ScanMode +--------+-----------+--------------+--------+-----------+-----------+--------------+------------------+--------+--------+---------+-----------+---------- + 1|scanChain_1| 258 | 256|clk_25mhz |rise | - | - | 1|SI_1 |SO_1 | - | + 2|scanChain_2| 258 | 256|clk_25mhz |rise | - | - | 1|SI_2 |SO_2 | - | + 3|scanChain_3| 258 | 256|clk_25mhz |rise | - | - | 1|SI_3 |SO_3 | - | + 4|scanChain_4| 258 | 256|clk_25mhz |rise | - | - | 1|SI_4 |SO_4 | - | +--------+-----------+--------------+--------+-----------+-----------+--------------+------------------+--------+--------+---------+-----------+---------- + +----------report_timing---------------- +> report_timing +Report for group default +-------------------------------------------------------------------------------------------------------------------------------------- +Startpoint: theMem/IRData_reg[18]/Q + (Clocked by clk_25mhz R) +Endpoint: theMem/mem_addr_reg[5]/D + (Clocked by clk_25mhz F) +Path Group: default +Data required time: 19371.2 + (Clock shift: 20000.0, minus Uncertainty: 500.0, plus Latency 0.0, minus Setup time: 128.8) +Data arrival time: 1240.0 +Slack: 18131.2 +Logic depth: 46 +-------------------------------------------------------------------------------------------------------------------------------------- + Arrival Arc Net Net Total fan- +Path Module/Cell Edge Time Delay Delay Delay Slew Load Load out Location + (ps) (ps) (ps) (ps) (ps) (ff) (ff) (#) (um,um) +-------------------------------------------------------------------------------------------------------------------------------------- +clk_25mhz {create_clock} r 0.0 0.0 0.0 0.0 0.0 100 101, 0 +theMem/IRData_reg[18]/CK->Q + DFF_X1_LVT* rr 106.0 106.0 106.0 0.0 100.0 15.2 77.1 10 175, 106 +theRegisters/i_1_0_1371/A->ZN + INV_X8_LVT rf 108.7 2.7 2.7 0.0 10.2 2.1 13.2 3 168, 158 +theRegisters/i_1_0_1339/A2->ZN + NAND3_X4_LVT fr 122.7 14.0 14.0 0.0 1.0 2.5 17.5 4 168, 158 +theRegisters/i_1_0_1321/A2->ZN + NOR2_X4_LVT* rf 141.6 19.0 19.0 0.0 12.1 29.7 130.1 32 168, 158 +theRegisters/i_1_0_722/B1->ZN + AOI22_X4_LVT* fr 186.0 44.3 44.3 0.0 10.2 0.7 23.4 1 168, 158 +theRegisters/i_1_0_721/A->ZN + INV_X8_LVT rf 188.1 2.1 2.1 0.0 10.2 0.8 3.0 1 168, 158 +theRegisters/i_1_0_718/A->ZN + AOI221_X2_LVT fr 245.4 57.3 57.3 0.0 0.6 0.9 4.4 1 168, 158 +theRegisters/i_1_0_716/A3->ZN + NAND4_X4_LVT rf 260.8 15.4 15.4 0.0 34.6 0.9 3.1 1 168, 158 +theRegisters/i_1_0_715/A->ZN + AOI221_X2_LVT fr 318.1 57.4 57.4 0.0 6.8 0.9 4.3 1 168, 158 +theRegisters/i_1_0_704/A2->ZN + NAND4_X4_LVT* rf 342.3 24.2 24.2 0.0 34.4 14.1 24.9 3 168, 158 +theDecoder/i_0_133/C2->ZN + AOI222_X4_LVT fr 452.6 110.3 110.3 0.0 10.2 0.8 23.5 1 129, 89 +theDecoder/i_0_132/A->ZN INV_X32_LVT rf 455.7 3.1 3.1 0.0 10.9 5.4 65.3 7 129, 89 +theDecoder/theALU/i_0_706/B1->ZN + OAI22_X4_LVT* fr 498.9 43.2 43.2 0.0 1.4 1.5 25.9 2 129, 89 +theDecoder/theALU/i_0_705/A->ZN + INV_X8_LVT rf 501.1 2.2 2.2 0.0 10.2 0.6 4.2 1 129, 89 +theDecoder/theALU/i_0_42/A->ZN + OAI21_X2_LVT fr 510.2 9.1 9.1 0.0 0.6 0.8 2.5 1 129, 89 +theDecoder/theALU/i_0_40/C1->ZN + AOI211_X2_LVT rf 515.8 5.6 5.6 0.0 11.6 0.8 2.9 1 129, 89 +theDecoder/theALU/i_0_39/B->ZN + AOI211_X2_LVT fr 563.3 47.4 47.4 0.0 3.3 0.9 3.0 1 129, 89 +theDecoder/theALU/i_0_38/B2->ZN + OAI222_X2_LVT rf 580.2 16.9 16.9 0.0 27.7 0.9 2.9 1 129, 89 +theDecoder/theALU/i_0_37/C2->ZN + AOI221_X2_LVT fr 624.0 43.8 43.8 0.0 8.4 0.9 4.2 1 129, 89 +theDecoder/theALU/i_0_35/B1->ZN + OAI22_X4_LVT* rf 637.9 13.9 13.9 0.0 34.0 0.7 23.4 1 129, 89 +theDecoder/theALU/i_0_34/A->ZN + INV_X8_LVT fr 642.4 4.5 4.5 0.0 10.2 0.6 4.1 1 129, 89 +theDecoder/theALU/i_0_33/A->ZN + AOI21_X4_LVT rf 645.0 2.6 2.6 0.0 2.4 0.8 3.0 1 129, 89 +theDecoder/theALU/i_0_32/C2->ZN + OAI222_X2_LVT fr 683.5 38.5 38.5 0.0 2.6 0.9 3.3 1 129, 89 +theDecoder/theALU/i_0_31/A->ZN + OAI221_X2_LVT rf 699.6 16.0 16.0 0.0 29.2 0.8 4.0 1 129, 89 +theDecoder/theALU/i_0_28/B1->ZN + AOI21_X4_LVT fr 715.0 15.5 15.5 0.0 8.2 0.8 3.0 1 129, 89 +theDecoder/theALU/i_0_27/A->ZN + AOI221_X2_LVT rf 719.3 4.2 4.2 0.0 13.5 0.9 2.9 1 129, 89 +theDecoder/theALU/i_0_26/B->ZN + AOI211_X2_LVT fr 771.5 52.2 52.2 0.0 5.3 0.8 4.6 1 129, 89 +theDecoder/theALU/i_0_25/B2->ZN + OAI22_X2_LVT rf 781.1 9.7 9.7 0.0 31.8 0.8 2.7 1 129, 89 +theDecoder/theALU/i_0_24/C2->ZN + AOI211_X2_LVT fr 815.5 34.4 34.4 0.0 4.0 0.9 3.1 1 129, 89 +theDecoder/theALU/i_0_23/A->ZN + AOI221_X2_LVT rf 821.3 5.8 5.8 0.0 27.8 0.9 3.1 1 129, 89 +theDecoder/theALU/i_0_22/A->ZN + AOI221_X2_LVT fr 874.9 53.7 53.7 0.0 5.4 0.9 3.1 1 129, 89 +theDecoder/theALU/i_0_21/A->ZN + AOI221_X2_LVT rf 881.0 6.1 6.1 0.0 31.2 0.9 3.1 1 129, 89 +theDecoder/theALU/i_0_20/C2->ZN + OAI222_X2_LVT fr 919.8 38.8 38.8 0.0 5.4 0.9 3.3 1 129, 89 +theDecoder/theALU/i_0_19/A->ZN + OAI221_X2_LVT rf 936.3 16.6 16.6 0.0 29.2 0.9 4.7 1 129, 89 +theDecoder/theALU/i_0_18/B2->ZN + AOI22_X4_LVT fr 966.6 30.3 30.3 0.0 8.6 0.8 4.4 1 129, 89 +theDecoder/theALU/i_0_17/B2->ZN + OAI21_X4_LVT rf 973.1 6.4 6.4 0.0 16.9 0.7 4.3 1 129, 89 +theDecoder/theALU/i_0_16/A->ZN + OAI21_X4_LVT fr 982.8 9.8 9.8 0.0 3.6 0.7 3.9 1 129, 89 +theDecoder/theALU/i_0_13/B1->ZN + AOI21_X4_LVT rf 988.1 5.3 5.3 0.0 12.5 0.8 4.4 1 129, 89 +theDecoder/theALU/i_0_12/A4->ZN + NOR4_X2_LVT fr 1044.5 56.5 56.5 0.0 2.9 0.8 2.8 1 129, 89 +theDecoder/theALU/i_0_0/A3->ZN + OR3_X4_LVT rr 1062.9 18.3 18.3 0.0 29.1 0.7 18.9 2 129, 89 +theDecoder/i_0_114/B->ZN XNOR2_X2_LVT rf 1069.5 6.7 6.7 0.0 9.3 0.7 4.3 1 129, 89 +theDecoder/i_0_113/B1->ZN + AOI22_X4_LVT fr 1096.0 26.5 26.5 0.0 5.1 0.8 4.4 1 129, 89 +theDecoder/i_0_111/A2->ZN + AOI22_X4_LVT rf 1102.4 6.4 6.4 0.0 16.9 0.7 4.3 1 129, 89 +theDecoder/i_0_110/A2->ZN + NAND2_X4_LVT* fr 1121.6 19.2 19.2 0.0 4.4 9.0 37.6 13 129, 89 +i_0_0_60/S->Z MUX2_X2_LVT* rf 1190.2 68.6 68.6 0.0 10.2 32.0 87.6 3 129, 89 +theMem/i_0_0_11/B2->ZN AOI22_X4_LVT* fr 1238.0 47.8 47.8 0.0 10.2 0.7 23.4 1 175, 106 +theMem/i_0_0_10/A->ZN INV_X8_LVT rf 1240.0 2.0 2.0 0.0 10.2 0.7 1.7 1 175, 106 +theMem/mem_addr_reg[5]/D DFF_X1_LVT f 1240.0 0.0 0.0 0.5 175, 106 +-------------------------------------------------------------------------------------------------------------------------------------- +Report for group I2R +Report for group I2O +Report for group R2O +-------------------------------------------------------------------------------------------------------------------------------------- +Startpoint: theMem/IRData_reg[18]/Q + (Clocked by clk_25mhz R) +Endpoint: led[7] + (Clocked by clk_25mhz R) +Path Group: R2O +Data required time: 37500.0 + (Clock shift: 40000.0, minus Uncertainty: 500.0, plus Latency 0.0, minus Out delay: 2000.0) +Data arrival time: 1190.2 +Slack: 36309.8 +Logic depth: 44 +-------------------------------------------------------------------------------------------------------------------------------------- + Arrival Arc Net Net Total fan- +Path Module/Cell Edge Time Delay Delay Delay Slew Load Load out Location + (ps) (ps) (ps) (ps) (ps) (ff) (ff) (#) (um,um) +-------------------------------------------------------------------------------------------------------------------------------------- +clk_25mhz {create_clock} r 0.0 0.0 0.0 0.0 0.0 100 101, 0 +theMem/IRData_reg[18]/CK->Q + DFF_X1_LVT* rr 106.0 106.0 106.0 0.0 100.0 15.2 77.1 10 175, 106 +theRegisters/i_1_0_1371/A->ZN + INV_X8_LVT rf 108.7 2.7 2.7 0.0 10.2 2.1 13.2 3 168, 158 +theRegisters/i_1_0_1339/A2->ZN + NAND3_X4_LVT fr 122.7 14.0 14.0 0.0 1.0 2.5 17.5 4 168, 158 +theRegisters/i_1_0_1321/A2->ZN + NOR2_X4_LVT* rf 141.6 19.0 19.0 0.0 12.1 29.7 130.1 32 168, 158 +theRegisters/i_1_0_722/B1->ZN + AOI22_X4_LVT* fr 186.0 44.3 44.3 0.0 10.2 0.7 23.4 1 168, 158 +theRegisters/i_1_0_721/A->ZN + INV_X8_LVT rf 188.1 2.1 2.1 0.0 10.2 0.8 3.0 1 168, 158 +theRegisters/i_1_0_718/A->ZN + AOI221_X2_LVT fr 245.4 57.3 57.3 0.0 0.6 0.9 4.4 1 168, 158 +theRegisters/i_1_0_716/A3->ZN + NAND4_X4_LVT rf 260.8 15.4 15.4 0.0 34.6 0.9 3.1 1 168, 158 +theRegisters/i_1_0_715/A->ZN + AOI221_X2_LVT fr 318.1 57.4 57.4 0.0 6.8 0.9 4.3 1 168, 158 +theRegisters/i_1_0_704/A2->ZN + NAND4_X4_LVT* rf 342.3 24.2 24.2 0.0 34.4 14.1 24.9 3 168, 158 +theDecoder/i_0_133/C2->ZN + AOI222_X4_LVT fr 452.6 110.3 110.3 0.0 10.2 0.8 23.5 1 129, 89 +theDecoder/i_0_132/A->ZN INV_X32_LVT rf 455.7 3.1 3.1 0.0 10.9 5.4 65.3 7 129, 89 +theDecoder/theALU/i_0_706/B1->ZN + OAI22_X4_LVT* fr 498.9 43.2 43.2 0.0 1.4 1.5 25.9 2 129, 89 +theDecoder/theALU/i_0_705/A->ZN + INV_X8_LVT rf 501.1 2.2 2.2 0.0 10.2 0.6 4.2 1 129, 89 +theDecoder/theALU/i_0_42/A->ZN + OAI21_X2_LVT fr 510.2 9.1 9.1 0.0 0.6 0.8 2.5 1 129, 89 +theDecoder/theALU/i_0_40/C1->ZN + AOI211_X2_LVT rf 515.8 5.6 5.6 0.0 11.6 0.8 2.9 1 129, 89 +theDecoder/theALU/i_0_39/B->ZN + AOI211_X2_LVT fr 563.3 47.4 47.4 0.0 3.3 0.9 3.0 1 129, 89 +theDecoder/theALU/i_0_38/B2->ZN + OAI222_X2_LVT rf 580.2 16.9 16.9 0.0 27.7 0.9 2.9 1 129, 89 +theDecoder/theALU/i_0_37/C2->ZN + AOI221_X2_LVT fr 624.0 43.8 43.8 0.0 8.4 0.9 4.2 1 129, 89 +theDecoder/theALU/i_0_35/B1->ZN + OAI22_X4_LVT* rf 637.9 13.9 13.9 0.0 34.0 0.7 23.4 1 129, 89 +theDecoder/theALU/i_0_34/A->ZN + INV_X8_LVT fr 642.4 4.5 4.5 0.0 10.2 0.6 4.1 1 129, 89 +theDecoder/theALU/i_0_33/A->ZN + AOI21_X4_LVT rf 645.0 2.6 2.6 0.0 2.4 0.8 3.0 1 129, 89 +theDecoder/theALU/i_0_32/C2->ZN + OAI222_X2_LVT fr 683.5 38.5 38.5 0.0 2.6 0.9 3.3 1 129, 89 +theDecoder/theALU/i_0_31/A->ZN + OAI221_X2_LVT rf 699.6 16.0 16.0 0.0 29.2 0.8 4.0 1 129, 89 +theDecoder/theALU/i_0_28/B1->ZN + AOI21_X4_LVT fr 715.0 15.5 15.5 0.0 8.2 0.8 3.0 1 129, 89 +theDecoder/theALU/i_0_27/A->ZN + AOI221_X2_LVT rf 719.3 4.2 4.2 0.0 13.5 0.9 2.9 1 129, 89 +theDecoder/theALU/i_0_26/B->ZN + AOI211_X2_LVT fr 771.5 52.2 52.2 0.0 5.3 0.8 4.6 1 129, 89 +theDecoder/theALU/i_0_25/B2->ZN + OAI22_X2_LVT rf 781.1 9.7 9.7 0.0 31.8 0.8 2.7 1 129, 89 +theDecoder/theALU/i_0_24/C2->ZN + AOI211_X2_LVT fr 815.5 34.4 34.4 0.0 4.0 0.9 3.1 1 129, 89 +theDecoder/theALU/i_0_23/A->ZN + AOI221_X2_LVT rf 821.3 5.8 5.8 0.0 27.8 0.9 3.1 1 129, 89 +theDecoder/theALU/i_0_22/A->ZN + AOI221_X2_LVT fr 874.9 53.7 53.7 0.0 5.4 0.9 3.1 1 129, 89 +theDecoder/theALU/i_0_21/A->ZN + AOI221_X2_LVT rf 881.0 6.1 6.1 0.0 31.2 0.9 3.1 1 129, 89 +theDecoder/theALU/i_0_20/C2->ZN + OAI222_X2_LVT fr 919.8 38.8 38.8 0.0 5.4 0.9 3.3 1 129, 89 +theDecoder/theALU/i_0_19/A->ZN + OAI221_X2_LVT rf 936.3 16.6 16.6 0.0 29.2 0.9 4.7 1 129, 89 +theDecoder/theALU/i_0_18/B2->ZN + AOI22_X4_LVT fr 966.6 30.3 30.3 0.0 8.6 0.8 4.4 1 129, 89 +theDecoder/theALU/i_0_17/B2->ZN + OAI21_X4_LVT rf 973.1 6.4 6.4 0.0 16.9 0.7 4.3 1 129, 89 +theDecoder/theALU/i_0_16/A->ZN + OAI21_X4_LVT fr 982.8 9.8 9.8 0.0 3.6 0.7 3.9 1 129, 89 +theDecoder/theALU/i_0_13/B1->ZN + AOI21_X4_LVT rf 988.1 5.3 5.3 0.0 12.5 0.8 4.4 1 129, 89 +theDecoder/theALU/i_0_12/A4->ZN + NOR4_X2_LVT fr 1044.5 56.5 56.5 0.0 2.9 0.8 2.8 1 129, 89 +theDecoder/theALU/i_0_0/A3->ZN + OR3_X4_LVT rr 1062.9 18.3 18.3 0.0 29.1 0.7 18.9 2 129, 89 +theDecoder/i_0_114/B->ZN XNOR2_X2_LVT rf 1069.5 6.7 6.7 0.0 9.3 0.7 4.3 1 129, 89 +theDecoder/i_0_113/B1->ZN + AOI22_X4_LVT fr 1096.0 26.5 26.5 0.0 5.1 0.8 4.4 1 129, 89 +theDecoder/i_0_111/A2->ZN + AOI22_X4_LVT rf 1102.4 6.4 6.4 0.0 16.9 0.7 4.3 1 129, 89 +theDecoder/i_0_110/A2->ZN + NAND2_X4_LVT* fr 1121.6 19.2 19.2 0.0 4.4 9.0 37.6 13 129, 89 +i_0_0_60/S->Z MUX2_X2_LVT* rf 1190.2 68.6 68.6 0.0 10.2 32.0 87.6 3 129, 89 +led[7] f 1190.2 0.0 0.0 10.2 119, 257 +-------------------------------------------------------------------------------------------------------------------------------------- + +------------------------------------- + + Tessent DFT complete + +------------------------------------- + +> report_library_cells +warning: please specify atleast one of options : '-standard/-level_shifter/-multibit/-isolation/-retention'. [CMD-137] +> report_library_cells -standard +Report Standard Cells: +-----+-----------------+-----------------+------------------------------------+-----------+------------+-----------------+----------+-------- + |Cell |Family |Library |Area (squm)|Leakage (pW)|Function Type |Power Type|Rails +-----+-----------------+-----------------+------------------------------------+-----------+------------+-----------------+----------+-------- +1 |AND2_X1_LVT |AND2_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.1| 9622.03|comb | - |VDD VSS +2 |AND2_X1_LVT |AND2_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.1| 5607.33|comb | - |VDD VSS +3 |AND2_X1_SVT |AND2_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.1| 825.43|comb | - |VDD VSS +4 |AND2_X1_SVT |AND2_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.1| 14.82|comb | - |VDD VSS +5 |AND2_X1_HVT |AND2_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.1| 3.62|comb | - |VDD VSS +6 |AND2_X1_HVT |AND2_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.1| 7.16|comb | - |VDD VSS +7 |AND2_X2_LVT |AND2_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.3| 19351.74|comb | - |VDD VSS +8 |AND2_X2_LVT |AND2_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.3| 11261.98|comb | - |VDD VSS +9 |AND2_X2_SVT |AND2_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.3| 1669.75|comb | - |VDD VSS +10 |AND2_X2_SVT |AND2_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.3| 28.30|comb | - |VDD VSS +11 |AND2_X2_HVT |AND2_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.3| 6.14|comb | - |VDD VSS +12 |AND2_X2_HVT |AND2_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.3| 12.97|comb | - |VDD VSS +13 |AND2_X4_LVT |AND2_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 2.4| 38697.10|comb | - |VDD VSS +14 |AND2_X4_LVT |AND2_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 2.4| 22523.92|comb | - |VDD VSS +15 |AND2_X4_SVT |AND2_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 2.4| 3333.08|comb | - |VDD VSS +16 |AND2_X4_SVT |AND2_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 2.4| 56.61|comb | - |VDD VSS +17 |AND2_X4_HVT |AND2_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 2.4| 12.28|comb | - |VDD VSS +18 |AND2_X4_HVT |AND2_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 2.4| 25.94|comb | - |VDD VSS +19 | | | | | | | | +20 |AND3_X1_LVT |AND3_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.3| 8734.54|comb | - |VDD VSS +21 |AND3_X1_LVT |AND3_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.3| 6335.91|comb | - |VDD VSS +22 |AND3_X1_SVT |AND3_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.3| 662.57|comb | - |VDD VSS +23 |AND3_X1_SVT |AND3_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.3| 15.13|comb | - |VDD VSS +24 |AND3_X1_HVT |AND3_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.3| 3.97|comb | - |VDD VSS +25 |AND3_X1_HVT |AND3_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.3| 7.92|comb | - |VDD VSS +26 |AND3_X2_LVT |AND3_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.6| 17566.65|comb | - |VDD VSS +27 |AND3_X2_LVT |AND3_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.6| 12725.78|comb | - |VDD VSS +28 |AND3_X2_SVT |AND3_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.6| 1342.26|comb | - |VDD VSS +29 |AND3_X2_SVT |AND3_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.6| 28.60|comb | - |VDD VSS +30 |AND3_X2_HVT |AND3_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.6| 6.66|comb | - |VDD VSS +31 |AND3_X2_HVT |AND3_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.6| 14.24|comb | - |VDD VSS +32 |AND3_X4_LVT |AND3_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 2.9| 35124.21|comb | - |VDD VSS +33 |AND3_X4_LVT |AND3_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 2.9| 25451.52|comb | - |VDD VSS +34 |AND3_X4_SVT |AND3_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 2.9| 2675.42|comb | - |VDD VSS +35 |AND3_X4_SVT |AND3_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 2.9| 57.21|comb | - |VDD VSS +36 |AND3_X4_HVT |AND3_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 2.9| 13.34|comb | - |VDD VSS +37 |AND3_X4_HVT |AND3_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 2.9| 28.50|comb | - |VDD VSS +38 | | | | | | | | +39 |AND4_X1_LVT |AND4_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.6| 8072.99|comb | - |VDD VSS +40 |AND4_X1_LVT |AND4_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.6| 6704.63|comb | - |VDD VSS +41 |AND4_X1_SVT |AND4_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.6| 554.11|comb | - |VDD VSS +42 |AND4_X1_SVT |AND4_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.6| 15.28|comb | - |VDD VSS +43 |AND4_X1_HVT |AND4_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.6| 4.21|comb | - |VDD VSS +44 |AND4_X1_HVT |AND4_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.6| 8.39|comb | - |VDD VSS +45 |AND4_X2_LVT |AND4_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.9| 16232.26|comb | - |VDD VSS +46 |AND4_X2_LVT |AND4_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.9| 13466.40|comb | - |VDD VSS +47 |AND4_X2_SVT |AND4_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.9| 1123.61|comb | - |VDD VSS +48 |AND4_X2_SVT |AND4_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.9| 28.61|comb | - |VDD VSS +49 |AND4_X2_HVT |AND4_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.9| 7.00|comb | - |VDD VSS +50 |AND4_X2_HVT |AND4_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.9| 14.99|comb | - |VDD VSS +51 |AND4_X4_LVT |AND4_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 3.5| 32456.65|comb | - |VDD VSS +52 |AND4_X4_LVT |AND4_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 3.5| 26932.77|comb | - |VDD VSS +53 |AND4_X4_SVT |AND4_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 3.5| 2239.19|comb | - |VDD VSS +54 |AND4_X4_SVT |AND4_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 3.5| 57.24|comb | - |VDD VSS +55 |AND4_X4_HVT |AND4_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 3.5| 14.00|comb | - |VDD VSS +56 |AND4_X4_HVT |AND4_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 3.5| 30.00|comb | - |VDD VSS +57 | | | | | | | | +58 |AOI21_X1_LVT |AOI21_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.1| 10193.51|comb | - |VDD VSS +59 |AOI21_X1_LVT |AOI21_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.1| 6839.16|comb | - |VDD VSS +60 |AOI21_X1_SVT |AOI21_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.1| 805.86|comb | - |VDD VSS +61 |AOI21_X1_SVT |AOI21_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.1| 15.76|comb | - |VDD VSS +62 |AOI21_X1_HVT |AOI21_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.1| 4.16|comb | - |VDD VSS +63 |AOI21_X1_HVT |AOI21_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.1| 8.46|comb | - |VDD VSS +64 |AOI21_X2_LVT |AOI21_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.9| 20381.21|comb | - |VDD VSS +65 |AOI21_X2_LVT |AOI21_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.9| 13678.31|comb | - |VDD VSS +66 |AOI21_X2_SVT |AOI21_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.9| 1605.91|comb | - |VDD VSS +67 |AOI21_X2_SVT |AOI21_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.9| 31.51|comb | - |VDD VSS +68 |AOI21_X2_HVT |AOI21_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.9| 8.33|comb | - |VDD VSS +69 |AOI21_X2_HVT |AOI21_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.9| 16.90|comb | - |VDD VSS +70 |AOI21_X4_LVT |AOI21_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 3.5| 40762.39|comb | - |VDD VSS +71 |AOI21_X4_LVT |AOI21_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 3.5| 27356.59|comb | - |VDD VSS +72 |AOI21_X4_SVT |AOI21_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 3.5| 3211.80|comb | - |VDD VSS +73 |AOI21_X4_SVT |AOI21_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 3.5| 63.04|comb | - |VDD VSS +74 |AOI21_X4_HVT |AOI21_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 3.5| 16.64|comb | - |VDD VSS +75 |AOI21_X4_HVT |AOI21_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 3.5| 33.81|comb | - |VDD VSS +76 | | | | | | | | +77 |AOI22_X1_LVT |AOI22_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.3| 12027.39|comb | - |VDD VSS +78 |AOI22_X1_LVT |AOI22_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.3| 8127.63|comb | - |VDD VSS +79 |AOI22_X1_SVT |AOI22_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.3| 891.40|comb | - |VDD VSS +80 |AOI22_X1_SVT |AOI22_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.3| 17.66|comb | - |VDD VSS +81 |AOI22_X1_HVT |AOI22_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.3| 4.62|comb | - |VDD VSS +82 |AOI22_X1_HVT |AOI22_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.3| 9.62|comb | - |VDD VSS +83 |AOI22_X2_LVT |AOI22_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 2.4| 24054.78|comb | - |VDD VSS +84 |AOI22_X2_LVT |AOI22_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 2.4| 16255.25|comb | - |VDD VSS +85 |AOI22_X2_SVT |AOI22_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 2.4| 1782.80|comb | - |VDD VSS +86 |AOI22_X2_SVT |AOI22_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 2.4| 35.31|comb | - |VDD VSS +87 |AOI22_X2_HVT |AOI22_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 2.4| 9.23|comb | - |VDD VSS +88 |AOI22_X2_HVT |AOI22_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 2.4| 19.23|comb | - |VDD VSS +89 |AOI22_X4_LVT |AOI22_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 4.5| 48109.59|comb | - |VDD VSS +90 |AOI22_X4_LVT |AOI22_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 4.5| 32510.51|comb | - |VDD VSS +91 |AOI22_X4_SVT |AOI22_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 4.5| 3565.60|comb | - |VDD VSS +92 |AOI22_X4_SVT |AOI22_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 4.5| 70.63|comb | - |VDD VSS +93 |AOI22_X4_HVT |AOI22_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 4.5| 18.46|comb | - |VDD VSS +94 |AOI22_X4_HVT |AOI22_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 4.5| 38.48|comb | - |VDD VSS +95 | | | | | | | | +96 |AOI211_X1_LVT |AOI211_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.3| 10177.76|comb | - |VDD VSS +97 |AOI211_X1_LVT |AOI211_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.3| 9224.15|comb | - |VDD VSS +98 |AOI211_X1_SVT |AOI211_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.3| 669.77|comb | - |VDD VSS +99 |AOI211_X1_SVT |AOI211_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.3| 18.56|comb | - |VDD VSS +100 |AOI211_X1_HVT |AOI211_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.3| 5.20|comb | - |VDD VSS +101 |AOI211_X1_HVT |AOI211_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.3| 10.82|comb | - |VDD VSS +102 |AOI211_X2_LVT |AOI211_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 2.4| 20348.08|comb | - |VDD VSS +103 |AOI211_X2_LVT |AOI211_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 2.4| 18448.29|comb | - |VDD VSS +104 |AOI211_X2_SVT |AOI211_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 2.4| 1332.15|comb | - |VDD VSS +105 |AOI211_X2_SVT |AOI211_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 2.4| 37.11|comb | - |VDD VSS +106 |AOI211_X2_HVT |AOI211_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 2.4| 10.40|comb | - |VDD VSS +107 |AOI211_X2_HVT |AOI211_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 2.4| 21.63|comb | - |VDD VSS +108 |AOI211_X4_LVT |AOI211_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 2.9| 49644.89|comb | - |VDD VSS +109 |AOI211_X4_LVT |AOI211_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 2.9| 28100.81|comb | - |VDD VSS +110 |AOI211_X4_SVT |AOI211_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 2.9| 4436.86|comb | - |VDD VSS +111 |AOI211_X4_SVT |AOI211_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 2.9| 72.65|comb | - |VDD VSS +112 |AOI211_X4_HVT |AOI211_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 2.9| 15.89|comb | - |VDD VSS +113 |AOI211_X4_HVT |AOI211_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 2.9| 33.25|comb | - |VDD VSS +114 | | | | | | | | +115 |AOI221_X1_LVT |AOI221_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.6| 12680.55|comb | - |VDD VSS +116 |AOI221_X1_LVT |AOI221_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.6| 11089.91|comb | - |VDD VSS +117 |AOI221_X1_SVT |AOI221_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.6| 819.97|comb | - |VDD VSS +118 |AOI221_X1_SVT |AOI221_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.6| 21.66|comb | - |VDD VSS +119 |AOI221_X1_HVT |AOI221_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.6| 5.80|comb | - |VDD VSS +120 |AOI221_X1_HVT |AOI221_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.6| 12.43|comb | - |VDD VSS +121 |AOI221_X2_LVT |AOI221_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 2.9| 25368.95|comb | - |VDD VSS +122 |AOI221_X2_LVT |AOI221_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 2.9| 22179.84|comb | - |VDD VSS +123 |AOI221_X2_SVT |AOI221_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 2.9| 1647.86|comb | - |VDD VSS +124 |AOI221_X2_SVT |AOI221_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 2.9| 43.35|comb | - |VDD VSS +125 |AOI221_X2_HVT |AOI221_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 2.9| 11.61|comb | - |VDD VSS +126 |AOI221_X2_HVT |AOI221_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 2.9| 24.88|comb | - |VDD VSS +127 |AOI221_X4_LVT |AOI221_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 3.5| 52955.87|comb | - |VDD VSS +128 |AOI221_X4_LVT |AOI221_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 3.5| 29298.97|comb | - |VDD VSS +129 |AOI221_X4_SVT |AOI221_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 3.5| 4734.70|comb | - |VDD VSS +130 |AOI221_X4_SVT |AOI221_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 3.5| 75.60|comb | - |VDD VSS +131 |AOI221_X4_HVT |AOI221_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 3.5| 16.39|comb | - |VDD VSS +132 |AOI221_X4_HVT |AOI221_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 3.5| 34.50|comb | - |VDD VSS +133 | | | | | | | | +134 |AOI222_X1_LVT |AOI222_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 2.1| 15198.97|comb | - |VDD VSS +135 |AOI222_X1_LVT |AOI222_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 2.1| 12505.32|comb | - |VDD VSS +136 |AOI222_X1_SVT |AOI222_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 2.1| 990.93|comb | - |VDD VSS +137 |AOI222_X1_SVT |AOI222_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 2.1| 24.58|comb | - |VDD VSS +138 |AOI222_X1_HVT |AOI222_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 2.1| 6.61|comb | - |VDD VSS +139 |AOI222_X1_HVT |AOI222_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 2.1| 14.13|comb | - |VDD VSS +140 |AOI222_X2_LVT |AOI222_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 3.7| 30401.54|comb | - |VDD VSS +141 |AOI222_X2_LVT |AOI222_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 3.7| 25010.63|comb | - |VDD VSS +142 |AOI222_X2_HVT |AOI222_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 3.7| 13.23|comb | - |VDD VSS +143 |AOI222_X2_HVT |AOI222_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 3.7| 28.28|comb | - |VDD VSS +144 |AOI222_X2_SVT |AOI222_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 3.7| 1985.48|comb | - |VDD VSS +145 |AOI222_X2_SVT |AOI222_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 3.7| 49.19|comb | - |VDD VSS +146 |AOI222_X4_LVT |AOI222_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 3.7| 56667.64|comb | - |VDD VSS +147 |AOI222_X4_LVT |AOI222_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 3.7| 29712.97|comb | - |VDD VSS +148 |AOI222_X4_SVT |AOI222_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 3.7| 5108.67|comb | - |VDD VSS +149 |AOI222_X4_SVT |AOI222_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 3.7| 78.22|comb | - |VDD VSS +150 |AOI222_X4_HVT |AOI222_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 3.7| 17.04|comb | - |VDD VSS +151 |AOI222_X4_HVT |AOI222_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 3.7| 35.61|comb | - |VDD VSS +152 | | | | | | | | +153 |BUF_X1_LVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 0.8| 10480.25|comb | - |VDD VSS +154 |BUF_X1_LVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 0.8| 4146.26|comb | - |VDD VSS +155 |CLKBUF_X1_LVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 0.8| 5737.45|comb | - |VDD VSS +156 |CLKBUF_X1_LVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 0.8| 1895.06|comb | - |VDD VSS +157 |BUF_X1_SVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 0.8| 1050.50|comb | - |VDD VSS +158 |BUF_X1_SVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 0.8| 13.77|comb | - |VDD VSS +159 |BUF_X1_HVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 0.8| 2.95|comb | - |VDD VSS +160 |BUF_X1_HVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 0.8| 5.73|comb | - |VDD VSS +161 |CLKBUF_X1_SVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 0.8| 605.08|comb | - |VDD VSS +162 |CLKBUF_X1_SVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 0.8| 8.31|comb | - |VDD VSS +163 |CLKBUF_X1_HVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 0.8| 2.14|comb | - |VDD VSS +164 |CLKBUF_X1_HVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 0.8| 3.59|comb | - |VDD VSS +165 |BUF_X2_LVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.1| 21062.44|comb | - |VDD VSS +166 |BUF_X2_LVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.1| 8326.08|comb | - |VDD VSS +167 |CLKBUF_X2_LVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.1| 11716.23|comb | - |VDD VSS +168 |CLKBUF_X2_LVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.1| 3890.88|comb | - |VDD VSS +169 |BUF_X2_SVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.1| 2120.29|comb | - |VDD VSS +170 |BUF_X2_SVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.1| 26.75|comb | - |VDD VSS +171 |BUF_X2_HVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.1| 5.18|comb | - |VDD VSS +172 |BUF_X2_HVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.1| 10.58|comb | - |VDD VSS +173 |CLKBUF_X2_SVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.1| 1240.54|comb | - |VDD VSS +174 |CLKBUF_X2_SVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.1| 15.99|comb | - |VDD VSS +175 |CLKBUF_X2_HVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.1| 3.59|comb | - |VDD VSS +176 |CLKBUF_X2_HVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.1| 6.38|comb | - |VDD VSS +177 |CLKBUF_X3_LVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.3| 15617.05|comb | - |VDD VSS +178 |CLKBUF_X3_LVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.3| 5187.80|comb | - |VDD VSS +179 |CLKBUF_X3_SVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.3| 1648.41|comb | - |VDD VSS +180 |CLKBUF_X3_SVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.3| 21.32|comb | - |VDD VSS +181 |CLKBUF_X3_HVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.3| 4.79|comb | - |VDD VSS +182 |CLKBUF_X3_HVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.3| 8.50|comb | - |VDD VSS +183 |BUF_X4_LVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.9| 42114.11|comb | - |VDD VSS +184 |BUF_X4_LVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.9| 16652.14|comb | - |VDD VSS +185 |BUF_X4_SVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.9| 4229.82|comb | - |VDD VSS +186 |BUF_X4_SVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.9| 53.49|comb | - |VDD VSS +187 |BUF_X4_HVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.9| 10.35|comb | - |VDD VSS +188 |BUF_X4_HVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.9| 21.16|comb | - |VDD VSS +189 |BUF_X8_LVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 3.5| 84228.45|comb | - |VDD VSS +190 |BUF_X8_LVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 3.5| 33304.01|comb | - |VDD VSS +191 |BUF_X8_SVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 3.5| 8459.65|comb | - |VDD VSS +192 |BUF_X8_SVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 3.5| 107.00|comb | - |VDD VSS +193 |BUF_X8_HVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 3.5| 20.71|comb | - |VDD VSS +194 |BUF_X8_HVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 3.5| 42.34|comb | - |VDD VSS +195 |BUF_X16_LVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 6.7| 168456.86|comb | - |VDD VSS +196 |BUF_X16_LVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 6.7| 66608.16|comb | - |VDD VSS +197 |BUF_X16_SVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 6.7| 16919.32|comb | - |VDD VSS +198 |BUF_X16_SVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 6.7| 214.01|comb | - |VDD VSS +199 |BUF_X16_HVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 6.7| 41.43|comb | - |VDD VSS +200 |BUF_X16_HVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 6.7| 84.69|comb | - |VDD VSS +201 |BUF_X32_LVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 13.0| 336912.59|comb | - |VDD VSS +202 |BUF_X32_LVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 13.0| 133215.94|comb | - |VDD VSS +203 |BUF_X32_SVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 13.0| 33838.64|comb | - |VDD VSS +204 |BUF_X32_SVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 13.0| 428.04|comb | - |VDD VSS +205 |BUF_X32_HVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 13.0| 82.89|comb | - |VDD VSS +206 |BUF_X32_HVT |BUF_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 13.0| 169.39|comb | - |VDD VSS +207 | | | | | | | | +208 |CLKGATETST_X1_LVT|CLKGATETST_X1_LVT|NangateOpenCellLibrary_45nm_LVT_0p85| 4.0| 26016.72|icg | - |VDD VSS +209 |CLKGATETST_X1_LVT|CLKGATETST_X1_LVT|NangateOpenCellLibrary_45nm_LVT | 4.0| 12526.59|icg | - |VDD VSS +210 |CLKGATETST_X1_SVT|CLKGATETST_X1_LVT|NangateOpenCellLibrary_45nm_SVT_0p85| 4.0| 2387.69|icg | - |VDD VSS +211 |CLKGATETST_X1_SVT|CLKGATETST_X1_LVT|NangateOpenCellLibrary_45nm_SVT | 4.0| 40.26|icg | - |VDD VSS +212 |CLKGATETST_X1_HVT|CLKGATETST_X1_LVT|NangateOpenCellLibrary_45nm_HVT_0p85| 4.0| 11.62|icg | - |VDD VSS +213 |CLKGATETST_X1_HVT|CLKGATETST_X1_LVT|NangateOpenCellLibrary_45nm_HVT | 4.0| 20.54|icg | - |VDD VSS +214 |CLKGATETST_X2_LVT|CLKGATETST_X1_LVT|NangateOpenCellLibrary_45nm_LVT_0p85| 4.3| 34058.64|icg | - |VDD VSS +215 |CLKGATETST_X2_LVT|CLKGATETST_X1_LVT|NangateOpenCellLibrary_45nm_LVT | 4.3| 16409.94|icg | - |VDD VSS +216 |CLKGATETST_X2_SVT|CLKGATETST_X1_LVT|NangateOpenCellLibrary_45nm_SVT_0p85| 4.3| 3123.00|icg | - |VDD VSS +217 |CLKGATETST_X2_SVT|CLKGATETST_X1_LVT|NangateOpenCellLibrary_45nm_SVT | 4.3| 50.91|icg | - |VDD VSS +218 |CLKGATETST_X2_HVT|CLKGATETST_X1_LVT|NangateOpenCellLibrary_45nm_HVT_0p85| 4.3| 13.58|icg | - |VDD VSS +219 |CLKGATETST_X2_HVT|CLKGATETST_X1_LVT|NangateOpenCellLibrary_45nm_HVT | 4.3| 24.79|icg | - |VDD VSS +220 |CLKGATETST_X4_LVT|CLKGATETST_X1_LVT|NangateOpenCellLibrary_45nm_LVT_0p85| 5.3| 54355.25|icg | - |VDD VSS +221 |CLKGATETST_X4_LVT|CLKGATETST_X1_LVT|NangateOpenCellLibrary_45nm_LVT | 5.3| 26540.72|icg | - |VDD VSS +222 |CLKGATETST_X4_SVT|CLKGATETST_X1_LVT|NangateOpenCellLibrary_45nm_SVT_0p85| 5.3| 5014.38|icg | - |VDD VSS +223 |CLKGATETST_X4_SVT|CLKGATETST_X1_LVT|NangateOpenCellLibrary_45nm_SVT | 5.3| 79.38|icg | - |VDD VSS +224 |CLKGATETST_X4_HVT|CLKGATETST_X1_LVT|NangateOpenCellLibrary_45nm_HVT_0p85| 5.3| 19.40|icg | - |VDD VSS +225 |CLKGATETST_X4_HVT|CLKGATETST_X1_LVT|NangateOpenCellLibrary_45nm_HVT | 5.3| 36.84|icg | - |VDD VSS +226 |CLKGATETST_X8_LVT|CLKGATETST_X1_LVT|NangateOpenCellLibrary_45nm_LVT_0p85| 7.7| 93983.73|icg | - |VDD VSS +227 |CLKGATETST_X8_LVT|CLKGATETST_X1_LVT|NangateOpenCellLibrary_45nm_LVT | 7.7| 45890.64|icg | - |VDD VSS +228 |CLKGATETST_X8_SVT|CLKGATETST_X1_LVT|NangateOpenCellLibrary_45nm_SVT_0p85| 7.7| 8690.35|icg | - |VDD VSS +229 |CLKGATETST_X8_SVT|CLKGATETST_X1_LVT|NangateOpenCellLibrary_45nm_SVT | 7.7| 135.56|icg | - |VDD VSS +230 |CLKGATETST_X8_HVT|CLKGATETST_X1_LVT|NangateOpenCellLibrary_45nm_HVT_0p85| 7.7| 31.62|icg | - |VDD VSS +231 |CLKGATETST_X8_HVT|CLKGATETST_X1_LVT|NangateOpenCellLibrary_45nm_HVT | 7.7| 61.21|icg | - |VDD VSS +232 | | | | | | | | +233 |CLKGATE_X1_LVT |CLKGATE_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 3.5| 21501.75|icg | - |VDD VSS +234 |CLKGATE_X1_LVT |CLKGATE_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 3.5| 10199.44|icg | - |VDD VSS +235 |CLKGATE_X1_SVT |CLKGATE_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 3.5| 1993.13|icg | - |VDD VSS +236 |CLKGATE_X1_SVT |CLKGATE_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 3.5| 33.55|icg | - |VDD VSS +237 |CLKGATE_X1_HVT |CLKGATE_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 3.5| 9.75|icg | - |VDD VSS +238 |CLKGATE_X1_HVT |CLKGATE_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 3.5| 17.08|icg | - |VDD VSS +239 |CLKGATE_X2_LVT |CLKGATE_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 3.7| 29166.54|icg | - |VDD VSS +240 |CLKGATE_X2_LVT |CLKGATE_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 3.7| 13889.73|icg | - |VDD VSS +241 |CLKGATE_X2_SVT |CLKGATE_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 3.7| 2701.18|icg | - |VDD VSS +242 |CLKGATE_X2_SVT |CLKGATE_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 3.7| 43.70|icg | - |VDD VSS +243 |CLKGATE_X2_HVT |CLKGATE_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 3.7| 11.64|icg | - |VDD VSS +244 |CLKGATE_X2_HVT |CLKGATE_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 3.7| 21.16|icg | - |VDD VSS +245 |CLKGATE_X4_LVT |CLKGATE_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 4.5| 47945.85|icg | - |VDD VSS +246 |CLKGATE_X4_LVT |CLKGATE_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 4.5| 22624.05|icg | - |VDD VSS +247 |CLKGATE_X4_SVT |CLKGATE_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 4.5| 4455.46|icg | - |VDD VSS +248 |CLKGATE_X4_SVT |CLKGATE_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 4.5| 69.60|icg | - |VDD VSS +249 |CLKGATE_X4_HVT |CLKGATE_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 4.5| 17.18|icg | - |VDD VSS +250 |CLKGATE_X4_HVT |CLKGATE_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 4.5| 32.19|icg | - |VDD VSS +251 |CLKGATE_X8_LVT |CLKGATE_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 6.9| 86272.84|icg | - |VDD VSS +252 |CLKGATE_X8_LVT |CLKGATE_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 6.9| 40597.88|icg | - |VDD VSS +253 |CLKGATE_X8_SVT |CLKGATE_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 6.9| 8020.06|icg | - |VDD VSS +254 |CLKGATE_X8_SVT |CLKGATE_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 6.9| 123.17|icg | - |VDD VSS +255 |CLKGATE_X8_HVT |CLKGATE_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 6.9| 29.11|icg | - |VDD VSS +256 |CLKGATE_X8_HVT |CLKGATE_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 6.9| 55.56|icg | - |VDD VSS +257 | | | | | | | | +258 |DFFRS_X1_LVT |DFFRS_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 6.4| 40119.64|ff | - |VDD VSS +259 |DFFRS_X1_LVT |DFFRS_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 6.4| 22655.58|ff | - |VDD VSS +260 |DFFRS_X1_SVT |DFFRS_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 6.4| 3437.02|ff | - |VDD VSS +261 |DFFRS_X1_SVT |DFFRS_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 6.4| 64.30|ff | - |VDD VSS +262 |DFFRS_X1_HVT |DFFRS_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 6.4| 18.46|ff | - |VDD VSS +263 |DFFRS_X1_HVT |DFFRS_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 6.4| 33.91|ff | - |VDD VSS +264 |DFFRS_X2_LVT |DFFRS_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 6.9| 57507.37|ff | - |VDD VSS +265 |DFFRS_X2_LVT |DFFRS_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 6.9| 31646.51|ff | - |VDD VSS +266 |DFFRS_X2_SVT |DFFRS_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 6.9| 5041.01|ff | - |VDD VSS +267 |DFFRS_X2_SVT |DFFRS_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 6.9| 87.95|ff | - |VDD VSS +268 |DFFRS_X2_HVT |DFFRS_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 6.9| 22.85|ff | - |VDD VSS +269 |DFFRS_X2_HVT |DFFRS_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 6.9| 43.69|ff | - |VDD VSS +270 | | | | | | | | +271 |DFFR_X1_LVT |DFFR_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 5.3| 36444.83|ff | - |VDD VSS +272 |DFFR_X1_LVT |DFFR_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 5.3| 18971.26|ff | - |VDD VSS +273 |DFFR_X1_SVT |DFFR_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 5.3| 3271.13|ff | - |VDD VSS +274 |DFFR_X1_SVT |DFFR_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 5.3| 55.93|ff | - |VDD VSS +275 |DFFR_X1_HVT |DFFR_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 5.3| 15.42|ff | - |VDD VSS +276 |DFFR_X1_HVT |DFFR_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 5.3| 28.46|ff | - |VDD VSS +277 |DFFR_X2_LVT |DFFR_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 5.9| 54504.59|ff | - |VDD VSS +278 |DFFR_X2_LVT |DFFR_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 5.9| 27126.62|ff | - |VDD VSS +279 |DFFR_X2_SVT |DFFR_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 5.9| 5006.63|ff | - |VDD VSS +280 |DFFR_X2_SVT |DFFR_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 5.9| 79.14|ff | - |VDD VSS +281 |DFFR_X2_HVT |DFFR_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 5.9| 19.73|ff | - |VDD VSS +282 |DFFR_X2_HVT |DFFR_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 5.9| 37.86|ff | - |VDD VSS +283 | | | | | | | | +284 |DFFS_X1_LVT |DFFS_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 5.3| 36395.78|ff | - |VDD VSS +285 |DFFS_X1_LVT |DFFS_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 5.3| 18380.86|ff | - |VDD VSS +286 |DFFS_X1_SVT |DFFS_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 5.3| 3291.44|ff | - |VDD VSS +287 |DFFS_X1_SVT |DFFS_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 5.3| 55.25|ff | - |VDD VSS +288 |DFFS_X1_HVT |DFFS_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 5.3| 15.28|ff | - |VDD VSS +289 |DFFS_X1_HVT |DFFS_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 5.3| 27.98|ff | - |VDD VSS +290 |DFFS_X2_LVT |DFFS_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 5.6| 53660.12|ff | - |VDD VSS +291 |DFFS_X2_LVT |DFFS_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 5.6| 25632.13|ff | - |VDD VSS +292 |DFFS_X2_SVT |DFFS_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 5.6| 3306.10|ff | - |VDD VSS +293 |DFFS_X2_SVT |DFFS_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 5.6| 77.22|ff | - |VDD VSS +294 |DFFS_X2_HVT |DFFS_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 5.6| 19.28|ff | - |VDD VSS +295 |DFFS_X2_HVT |DFFS_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 5.6| 36.04|ff | - |VDD VSS +296 | | | | | | | | +297 |DFF_X1_LVT |DFF_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 4.5| 35907.23|ff | - |VDD VSS +298 |DFF_X1_LVT |DFF_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 4.5| 16703.55|ff | - |VDD VSS +299 |DFF_X1_SVT |DFF_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 4.5| 3357.14|ff | - |VDD VSS +300 |DFF_X1_SVT |DFF_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 4.5| 52.95|ff | - |VDD VSS +301 |DFF_X1_HVT |DFF_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 4.5| 14.47|ff | - |VDD VSS +302 |DFF_X1_HVT |DFF_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 4.5| 26.22|ff | - |VDD VSS +303 |DFF_X2_LVT |DFF_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 5.1| 53526.70|ff | - |VDD VSS +304 |DFF_X2_LVT |DFF_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 5.1| 23655.11|ff | - |VDD VSS +305 |DFF_X2_SVT |DFF_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 5.1| 5121.49|ff | - |VDD VSS +306 |DFF_X2_SVT |DFF_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 5.1| 74.86|ff | - |VDD VSS +307 |DFF_X2_HVT |DFF_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 5.1| 18.44|ff | - |VDD VSS +308 |DFF_X2_HVT |DFF_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 5.1| 34.61|ff | - |VDD VSS +309 | | | | | | | | +310 |DLH_X1_LVT |DLH_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 2.7| 18802.27|latch | - |VDD VSS +311 |DLH_X1_LVT |DLH_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 2.7| 8508.37|latch | - |VDD VSS +312 |DLH_X1_SVT |DLH_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 2.7| 1782.31|latch | - |VDD VSS +313 |DLH_X1_SVT |DLH_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 2.7| 28.33|latch | - |VDD VSS +314 |DLH_X1_HVT |DLH_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 2.7| 8.04|latch | - |VDD VSS +315 |DLH_X1_HVT |DLH_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 2.7| 14.22|latch | - |VDD VSS +316 |DLH_X2_LVT |DLH_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 2.9| 26693.04|latch | - |VDD VSS +317 |DLH_X2_LVT |DLH_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 2.9| 11821.34|latch | - |VDD VSS +318 |DLH_X2_SVT |DLH_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 2.9| 2551.78|latch | - |VDD VSS +319 |DLH_X2_SVT |DLH_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 2.9| 38.28|latch | - |VDD VSS +320 |DLH_X2_HVT |DLH_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 2.9| 9.95|latch | - |VDD VSS +321 |DLH_X2_HVT |DLH_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 2.9| 18.23|latch | - |VDD VSS +322 | | | | | | | | +323 |DLL_X1_LVT |DLL_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 2.7| 18807.02|latch | - |VDD VSS +324 |DLL_X1_LVT |DLL_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 2.7| 8508.40|latch | - |VDD VSS +325 |DLL_X1_SVT |DLL_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 2.7| 1787.30|latch | - |VDD VSS +326 |DLL_X1_SVT |DLL_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 2.7| 28.34|latch | - |VDD VSS +327 |DLL_X1_HVT |DLL_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 2.7| 8.05|latch | - |VDD VSS +328 |DLL_X1_HVT |DLL_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 2.7| 14.23|latch | - |VDD VSS +329 |DLL_X2_LVT |DLL_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 2.9| 26692.74|latch | - |VDD VSS +330 |DLL_X2_LVT |DLL_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 2.9| 11821.33|latch | - |VDD VSS +331 |DLL_X2_SVT |DLL_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 2.9| 2551.76|latch | - |VDD VSS +332 |DLL_X2_SVT |DLL_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 2.9| 38.27|latch | - |VDD VSS +333 |DLL_X2_HVT |DLL_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 2.9| 9.95|latch | - |VDD VSS +334 |DLL_X2_HVT |DLL_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 2.9| 18.23|latch | - |VDD VSS +335 | | | | | | | | +336 |FA_X1_LVT |FA_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 4.3| 29541.55|multi-output comb| - |VDD VSS +337 |FA_X1_LVT |FA_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 4.3| 17741.67|multi-output comb| - |VDD VSS +338 |FA_X1_SVT |FA_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 4.3| 2442.55|multi-output comb| - |VDD VSS +339 |FA_X1_SVT |FA_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 4.3| 44.53|multi-output comb| - |VDD VSS +340 |FA_X1_HVT |FA_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 4.3| 11.45|multi-output comb| - |VDD VSS +341 |FA_X1_HVT |FA_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 4.3| 22.75|multi-output comb| - |VDD VSS +342 | | | | | | | | +343 |HA_X1_LVT |HA_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 2.7| 26033.76|multi-output comb| - |VDD VSS +344 |HA_X1_LVT |HA_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 2.7| 13428.56|multi-output comb| - |VDD VSS +345 |HA_X1_SVT |HA_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 2.7| 2332.71|multi-output comb| - |VDD VSS +346 |HA_X1_SVT |HA_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 2.7| 37.44|multi-output comb| - |VDD VSS +347 |HA_X1_HVT |HA_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 2.7| 9.28|multi-output comb| - |VDD VSS +348 |HA_X1_HVT |HA_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 2.7| 18.00|multi-output comb| - |VDD VSS +349 | | | | | | | | +350 |INV_X1_LVT |INV_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 0.5| 7012.21|comb | - |VDD VSS +351 |INV_X1_LVT |INV_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 0.5| 2775.46|comb | - |VDD VSS +352 |INV_X1_SVT |INV_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 0.5| 699.55|comb | - |VDD VSS +353 |INV_X1_SVT |INV_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 0.5| 8.92|comb | - |VDD VSS +354 |INV_X1_HVT |INV_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 0.5| 1.74|comb | - |VDD VSS +355 |INV_X1_HVT |INV_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 0.5| 3.54|comb | - |VDD VSS +356 |INV_X2_LVT |INV_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 0.8| 14035.21|comb | - |VDD VSS +357 |INV_X2_LVT |INV_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 0.8| 5550.90|comb | - |VDD VSS +358 |INV_X2_SVT |INV_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 0.8| 1409.85|comb | - |VDD VSS +359 |INV_X2_SVT |INV_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 0.8| 17.84|comb | - |VDD VSS +360 |INV_X2_HVT |INV_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 0.8| 3.45|comb | - |VDD VSS +361 |INV_X2_HVT |INV_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 0.8| 7.06|comb | - |VDD VSS +362 |INV_X4_LVT |INV_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.3| 28070.44|comb | - |VDD VSS +363 |INV_X4_LVT |INV_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.3| 11101.79|comb | - |VDD VSS +364 |INV_X4_SVT |INV_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.3| 2819.69|comb | - |VDD VSS +365 |INV_X4_SVT |INV_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.3| 35.66|comb | - |VDD VSS +366 |INV_X4_HVT |INV_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.3| 6.90|comb | - |VDD VSS +367 |INV_X4_HVT |INV_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.3| 14.11|comb | - |VDD VSS +368 |INV_X8_LVT |INV_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 2.4| 56141.14|comb | - |VDD VSS +369 |INV_X8_LVT |INV_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 2.4| 22203.35|comb | - |VDD VSS +370 |INV_X8_SVT |INV_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 2.4| 5639.40|comb | - |VDD VSS +371 |INV_X8_SVT |INV_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 2.4| 71.32|comb | - |VDD VSS +372 |INV_X8_HVT |INV_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 2.4| 13.80|comb | - |VDD VSS +373 |INV_X8_HVT |INV_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 2.4| 28.22|comb | - |VDD VSS +374 |INV_X16_LVT |INV_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 4.5| 112281.60|comb | - |VDD VSS +375 |INV_X16_LVT |INV_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 4.5| 44407.05|comb | - |VDD VSS +376 |INV_X16_SVT |INV_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 4.5| 11278.78|comb | - |VDD VSS +377 |INV_X16_SVT |INV_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 4.5| 142.68|comb | - |VDD VSS +378 |INV_X16_HVT |INV_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 4.5| 27.63|comb | - |VDD VSS +379 |INV_X16_HVT |INV_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 4.5| 56.47|comb | - |VDD VSS +380 |INV_X32_LVT |INV_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 8.8| 224563.25|comb | - |VDD VSS +381 |INV_X32_LVT |INV_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 8.8| 88814.09|comb | - |VDD VSS +382 |INV_X32_SVT |INV_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 8.8| 22557.59|comb | - |VDD VSS +383 |INV_X32_SVT |INV_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 8.8| 285.37|comb | - |VDD VSS +384 |INV_X32_HVT |INV_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 8.8| 55.28|comb | - |VDD VSS +385 |INV_X32_HVT |INV_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 8.8| 112.94|comb | - |VDD VSS +386 | | | | | | | | +387 |MUX2_X1_LVT |MUX2_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.9| 15919.84|comb | - |VDD VSS +388 |MUX2_X1_LVT |MUX2_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.9| 7783.94|comb | - |VDD VSS +389 |MUX2_X1_SVT |MUX2_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.9| 1444.87|comb | - |VDD VSS +390 |MUX2_X1_SVT |MUX2_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.9| 23.26|comb | - |VDD VSS +391 |MUX2_X1_HVT |MUX2_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.9| 6.30|comb | - |VDD VSS +392 |MUX2_X1_HVT |MUX2_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.9| 11.61|comb | - |VDD VSS +393 |MUX2_X2_LVT |MUX2_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 2.4| 29698.24|comb | - |VDD VSS +394 |MUX2_X2_LVT |MUX2_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 2.4| 14955.56|comb | - |VDD VSS +395 |MUX2_X2_SVT |MUX2_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 2.4| 2680.10|comb | - |VDD VSS +396 |MUX2_X2_SVT |MUX2_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 2.4| 40.69|comb | - |VDD VSS +397 |MUX2_X2_HVT |MUX2_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 2.4| 9.31|comb | - |VDD VSS +398 |MUX2_X2_HVT |MUX2_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 2.4| 18.82|comb | - |VDD VSS +399 | | | | | | | | +400 |NAND2_X1_LVT |NAND2_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 0.8| 7432.40|comb | - |VDD VSS +401 |NAND2_X1_LVT |NAND2_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 0.8| 3931.22|comb | - |VDD VSS +402 |NAND2_X1_SVT |NAND2_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 0.8| 625.19|comb | - |VDD VSS +403 |NAND2_X1_SVT |NAND2_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 0.8| 10.01|comb | - |VDD VSS +404 |NAND2_X1_HVT |NAND2_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 0.8| 2.42|comb | - |VDD VSS +405 |NAND2_X1_HVT |NAND2_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 0.8| 4.92|comb | - |VDD VSS +406 |NAND2_X2_LVT |NAND2_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.3| 14871.25|comb | - |VDD VSS +407 |NAND2_X2_LVT |NAND2_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.3| 7862.42|comb | - |VDD VSS +408 |NAND2_X2_SVT |NAND2_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.3| 1256.79|comb | - |VDD VSS +409 |NAND2_X2_SVT |NAND2_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.3| 20.00|comb | - |VDD VSS +410 |NAND2_X2_HVT |NAND2_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.3| 4.84|comb | - |VDD VSS +411 |NAND2_X2_HVT |NAND2_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.3| 9.82|comb | - |VDD VSS +412 |NAND2_X4_LVT |NAND2_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 2.4| 29742.48|comb | - |VDD VSS +413 |NAND2_X4_LVT |NAND2_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 2.4| 15724.80|comb | - |VDD VSS +414 |NAND2_X4_SVT |NAND2_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 2.4| 2513.59|comb | - |VDD VSS +415 |NAND2_X4_SVT |NAND2_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 2.4| 40.02|comb | - |VDD VSS +416 |NAND2_X4_HVT |NAND2_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 2.4| 9.68|comb | - |VDD VSS +417 |NAND2_X4_HVT |NAND2_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 2.4| 19.65|comb | - |VDD VSS +418 | | | | | | | | +419 |NAND3_X1_LVT |NAND3_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.1| 6708.77|comb | - |VDD VSS +420 |NAND3_X1_LVT |NAND3_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.1| 4504.89|comb | - |VDD VSS +421 |NAND3_X1_SVT |NAND3_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.1| 480.95|comb | - |VDD VSS +422 |NAND3_X1_SVT |NAND3_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.1| 10.06|comb | - |VDD VSS +423 |NAND3_X1_HVT |NAND3_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.1| 2.82|comb | - |VDD VSS +424 |NAND3_X1_HVT |NAND3_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.1| 5.68|comb | - |VDD VSS +425 |NAND3_X2_LVT |NAND3_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.9| 13426.63|comb | - |VDD VSS +426 |NAND3_X2_LVT |NAND3_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.9| 9009.79|comb | - |VDD VSS +427 |NAND3_X2_SVT |NAND3_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.9| 971.01|comb | - |VDD VSS +428 |NAND3_X2_SVT |NAND3_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.9| 20.13|comb | - |VDD VSS +429 |NAND3_X2_HVT |NAND3_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.9| 5.63|comb | - |VDD VSS +430 |NAND3_X2_HVT |NAND3_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.9| 11.36|comb | - |VDD VSS +431 |NAND3_X4_LVT |NAND3_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 3.5| 26853.26|comb | - |VDD VSS +432 |NAND3_X4_LVT |NAND3_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 3.5| 18019.56|comb | - |VDD VSS +433 |NAND3_X4_SVT |NAND3_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 3.5| 1941.99|comb | - |VDD VSS +434 |NAND3_X4_SVT |NAND3_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 3.5| 40.23|comb | - |VDD VSS +435 |NAND3_X4_HVT |NAND3_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 3.5| 11.23|comb | - |VDD VSS +436 |NAND3_X4_HVT |NAND3_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 3.5| 22.70|comb | - |VDD VSS +437 | | | | | | | | +438 |NAND4_X1_LVT |NAND4_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.3| 5908.27|comb | - |VDD VSS +439 |NAND4_X1_LVT |NAND4_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.3| 4800.43|comb | - |VDD VSS +440 |NAND4_X1_SVT |NAND4_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.3| 356.37|comb | - |VDD VSS +441 |NAND4_X1_SVT |NAND4_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.3| 9.95|comb | - |VDD VSS +442 |NAND4_X1_HVT |NAND4_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.3| 3.08|comb | - |VDD VSS +443 |NAND4_X1_HVT |NAND4_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.3| 6.18|comb | - |VDD VSS +444 |NAND4_X2_LVT |NAND4_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 2.4| 11824.66|comb | - |VDD VSS +445 |NAND4_X2_LVT |NAND4_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 2.4| 9600.86|comb | - |VDD VSS +446 |NAND4_X2_SVT |NAND4_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 2.4| 720.76|comb | - |VDD VSS +447 |NAND4_X2_SVT |NAND4_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 2.4| 19.91|comb | - |VDD VSS +448 |NAND4_X2_HVT |NAND4_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 2.4| 6.15|comb | - |VDD VSS +449 |NAND4_X2_HVT |NAND4_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 2.4| 12.35|comb | - |VDD VSS +450 |NAND4_X4_LVT |NAND4_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 4.8| 23649.18|comb | - |VDD VSS +451 |NAND4_X4_LVT |NAND4_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 4.8| 19201.62|comb | - |VDD VSS +452 |NAND4_X4_SVT |NAND4_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 4.8| 1441.48|comb | - |VDD VSS +453 |NAND4_X4_SVT |NAND4_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 4.8| 39.76|comb | - |VDD VSS +454 |NAND4_X4_HVT |NAND4_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 4.8| 12.26|comb | - |VDD VSS +455 |NAND4_X4_HVT |NAND4_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 4.8| 24.65|comb | - |VDD VSS +456 | | | | | | | | +457 |NOR2_X1_LVT |NOR2_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 0.8| 8076.81|comb | - |VDD VSS +458 |NOR2_X1_LVT |NOR2_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 0.8| 5012.31|comb | - |VDD VSS +459 |NOR2_X1_HVT |NOR2_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 0.8| 2.73|comb | - |VDD VSS +460 |NOR2_X1_HVT |NOR2_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 0.8| 5.80|comb | - |VDD VSS +461 |NOR2_X1_SVT |NOR2_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 0.8| 677.44|comb | - |VDD VSS +462 |NOR2_X1_SVT |NOR2_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 0.8| 11.84|comb | - |VDD VSS +463 |NOR2_X2_LVT |NOR2_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.3| 16163.36|comb | - |VDD VSS +464 |NOR2_X2_LVT |NOR2_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.3| 10024.62|comb | - |VDD VSS +465 |NOR2_X2_SVT |NOR2_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.3| 1364.61|comb | - |VDD VSS +466 |NOR2_X2_SVT |NOR2_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.3| 23.67|comb | - |VDD VSS +467 |NOR2_X2_HVT |NOR2_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.3| 5.44|comb | - |VDD VSS +468 |NOR2_X2_HVT |NOR2_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.3| 11.59|comb | - |VDD VSS +469 |NOR2_X4_LVT |NOR2_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 2.4| 32326.72|comb | - |VDD VSS +470 |NOR2_X4_LVT |NOR2_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 2.4| 20049.21|comb | - |VDD VSS +471 |NOR2_X4_SVT |NOR2_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 2.4| 2729.23|comb | - |VDD VSS +472 |NOR2_X4_SVT |NOR2_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 2.4| 47.32|comb | - |VDD VSS +473 |NOR2_X4_HVT |NOR2_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 2.4| 10.88|comb | - |VDD VSS +474 |NOR2_X4_HVT |NOR2_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 2.4| 23.16|comb | - |VDD VSS +475 | | | | | | | | +476 |NOR3_X1_LVT |NOR3_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.1| 7863.69|comb | - |VDD VSS +477 |NOR3_X1_LVT |NOR3_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.1| 7124.50|comb | - |VDD VSS +478 |NOR3_X1_HVT |NOR3_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.1| 3.44|comb | - |VDD VSS +479 |NOR3_X1_HVT |NOR3_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.1| 7.62|comb | - |VDD VSS +480 |NOR3_X1_SVT |NOR3_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.1| 515.66|comb | - |VDD VSS +481 |NOR3_X1_SVT |NOR3_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.1| 13.71|comb | - |VDD VSS +482 |NOR3_X2_LVT |NOR3_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.9| 15739.80|comb | - |VDD VSS +483 |NOR3_X2_LVT |NOR3_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.9| 14248.98|comb | - |VDD VSS +484 |NOR3_X2_HVT |NOR3_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.9| 6.86|comb | - |VDD VSS +485 |NOR3_X2_HVT |NOR3_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.9| 15.22|comb | - |VDD VSS +486 |NOR3_X2_SVT |NOR3_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.9| 1043.74|comb | - |VDD VSS +487 |NOR3_X2_SVT |NOR3_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.9| 27.41|comb | - |VDD VSS +488 |NOR3_X4_LVT |NOR3_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 3.7| 31479.50|comb | - |VDD VSS +489 |NOR3_X4_LVT |NOR3_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 3.7| 28497.88|comb | - |VDD VSS +490 |NOR3_X4_HVT |NOR3_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 3.7| 13.72|comb | - |VDD VSS +491 |NOR3_X4_HVT |NOR3_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 3.7| 30.45|comb | - |VDD VSS +492 |NOR3_X4_SVT |NOR3_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 3.7| 2087.47|comb | - |VDD VSS +493 |NOR3_X4_SVT |NOR3_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 3.7| 54.83|comb | - |VDD VSS +494 | | | | | | | | +495 |NOR4_X1_LVT |NOR4_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.3| 7673.18|comb | - |VDD VSS +496 |NOR4_X1_LVT |NOR4_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.3| 9237.33|comb | - |VDD VSS +497 |NOR4_X1_HVT |NOR4_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.3| 4.05|comb | - |VDD VSS +498 |NOR4_X1_HVT |NOR4_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.3| 9.32|comb | - |VDD VSS +499 |NOR4_X1_SVT |NOR4_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.3| 362.23|comb | - |VDD VSS +500 |NOR4_X1_SVT |NOR4_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.3| 15.58|comb | - |VDD VSS +501 |NOR4_X2_LVT |NOR4_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 2.4| 15358.51|comb | - |VDD VSS +502 |NOR4_X2_LVT |NOR4_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 2.4| 18474.64|comb | - |VDD VSS +503 |NOR4_X2_HVT |NOR4_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 2.4| 8.08|comb | - |VDD VSS +504 |NOR4_X2_HVT |NOR4_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 2.4| 18.62|comb | - |VDD VSS +505 |NOR4_X2_SVT |NOR4_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 2.4| 736.62|comb | - |VDD VSS +506 |NOR4_X2_SVT |NOR4_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 2.4| 31.15|comb | - |VDD VSS +507 |NOR4_X4_LVT |NOR4_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 4.8| 30716.98|comb | - |VDD VSS +508 |NOR4_X4_LVT |NOR4_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 4.8| 36949.18|comb | - |VDD VSS +509 |NOR4_X4_HVT |NOR4_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 4.8| 16.17|comb | - |VDD VSS +510 |NOR4_X4_HVT |NOR4_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 4.8| 37.25|comb | - |VDD VSS +511 |NOR4_X4_SVT |NOR4_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 4.8| 1473.24|comb | - |VDD VSS +512 |NOR4_X4_SVT |NOR4_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 4.8| 62.31|comb | - |VDD VSS +513 | | | | | | | | +514 |OAI21_X1_LVT |OAI21_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.1| 8985.11|comb | - |VDD VSS +515 |OAI21_X1_LVT |OAI21_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.1| 5333.19|comb | - |VDD VSS +516 |OAI21_X1_SVT |OAI21_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.1| 720.36|comb | - |VDD VSS +517 |OAI21_X1_SVT |OAI21_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.1| 13.37|comb | - |VDD VSS +518 |OAI21_X1_HVT |OAI21_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.1| 3.79|comb | - |VDD VSS +519 |OAI21_X1_HVT |OAI21_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.1| 7.31|comb | - |VDD VSS +520 |OAI21_X2_LVT |OAI21_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.9| 17966.38|comb | - |VDD VSS +521 |OAI21_X2_LVT |OAI21_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.9| 10666.39|comb | - |VDD VSS +522 |OAI21_X2_SVT |OAI21_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.9| 1436.88|comb | - |VDD VSS +523 |OAI21_X2_SVT |OAI21_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.9| 26.75|comb | - |VDD VSS +524 |OAI21_X2_HVT |OAI21_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.9| 7.57|comb | - |VDD VSS +525 |OAI21_X2_HVT |OAI21_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.9| 14.63|comb | - |VDD VSS +526 |OAI21_X4_LVT |OAI21_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 3.5| 35932.73|comb | - |VDD VSS +527 |OAI21_X4_LVT |OAI21_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 3.5| 21332.75|comb | - |VDD VSS +528 |OAI21_X4_SVT |OAI21_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 3.5| 2873.77|comb | - |VDD VSS +529 |OAI21_X4_SVT |OAI21_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 3.5| 53.52|comb | - |VDD VSS +530 |OAI21_X4_HVT |OAI21_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 3.5| 15.15|comb | - |VDD VSS +531 |OAI21_X4_HVT |OAI21_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 3.5| 29.27|comb | - |VDD VSS +532 | | | | | | | | +533 |OAI22_X1_LVT |OAI22_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.3| 11849.03|comb | - |VDD VSS +534 |OAI22_X1_LVT |OAI22_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.3| 8592.88|comb | - |VDD VSS +535 |OAI22_X1_SVT |OAI22_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.3| 854.23|comb | - |VDD VSS +536 |OAI22_X1_SVT |OAI22_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.3| 18.12|comb | - |VDD VSS +537 |OAI22_X1_HVT |OAI22_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.3| 4.68|comb | - |VDD VSS +538 |OAI22_X1_HVT |OAI22_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.3| 9.88|comb | - |VDD VSS +539 |OAI22_X2_LVT |OAI22_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 2.4| 23698.06|comb | - |VDD VSS +540 |OAI22_X2_LVT |OAI22_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 2.4| 17185.74|comb | - |VDD VSS +541 |OAI22_X2_SVT |OAI22_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 2.4| 1708.46|comb | - |VDD VSS +542 |OAI22_X2_SVT |OAI22_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 2.4| 36.24|comb | - |VDD VSS +543 |OAI22_X2_HVT |OAI22_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 2.4| 9.37|comb | - |VDD VSS +544 |OAI22_X2_HVT |OAI22_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 2.4| 19.76|comb | - |VDD VSS +545 |OAI22_X4_LVT |OAI22_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 4.5| 47395.96|comb | - |VDD VSS +546 |OAI22_X4_LVT |OAI22_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 4.5| 34371.46|comb | - |VDD VSS +547 |OAI22_X4_SVT |OAI22_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 4.5| 3416.92|comb | - |VDD VSS +548 |OAI22_X4_SVT |OAI22_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 4.5| 72.50|comb | - |VDD VSS +549 |OAI22_X4_HVT |OAI22_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 4.5| 18.75|comb | - |VDD VSS +550 |OAI22_X4_HVT |OAI22_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 4.5| 39.53|comb | - |VDD VSS +551 | | | | | | | | +552 |OAI33_X1_LVT |OAI33_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.9| 13302.17|comb | - |VDD VSS +553 |OAI33_X1_LVT |OAI33_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.9| 13241.92|comb | - |VDD VSS +554 |OAI33_X1_HVT |OAI33_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.9| 6.43|comb | - |VDD VSS +555 |OAI33_X1_HVT |OAI33_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.9| 14.15|comb | - |VDD VSS +556 |OAI33_X1_SVT |OAI33_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.9| 750.02|comb | - |VDD VSS +557 |OAI33_X1_SVT |OAI33_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.9| 24.00|comb | - |VDD VSS +558 | | | | | | | | +559 |OAI211_X1_LVT |OAI211_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.3| 8070.41|comb | - |VDD VSS +560 |OAI211_X1_LVT |OAI211_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.3| 5475.34|comb | - |VDD VSS +561 |OAI211_X1_SVT |OAI211_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.3| 586.42|comb | - |VDD VSS +562 |OAI211_X1_SVT |OAI211_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.3| 13.35|comb | - |VDD VSS +563 |OAI211_X1_HVT |OAI211_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.3| 4.34|comb | - |VDD VSS +564 |OAI211_X1_HVT |OAI211_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.3| 8.11|comb | - |VDD VSS +565 |OAI211_X2_LVT |OAI211_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 2.4| 16137.34|comb | - |VDD VSS +566 |OAI211_X2_LVT |OAI211_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 2.4| 10950.69|comb | - |VDD VSS +567 |OAI211_X2_SVT |OAI211_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 2.4| 1169.32|comb | - |VDD VSS +568 |OAI211_X2_SVT |OAI211_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 2.4| 26.70|comb | - |VDD VSS +569 |OAI211_X2_HVT |OAI211_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 2.4| 8.68|comb | - |VDD VSS +570 |OAI211_X2_HVT |OAI211_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 2.4| 16.23|comb | - |VDD VSS +571 |OAI211_X4_LVT |OAI211_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 4.5| 32274.72|comb | - |VDD VSS +572 |OAI211_X4_LVT |OAI211_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 4.5| 21901.31|comb | - |VDD VSS +573 |OAI211_X4_SVT |OAI211_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 4.5| 2338.62|comb | - |VDD VSS +574 |OAI211_X4_SVT |OAI211_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 4.5| 53.37|comb | - |VDD VSS +575 |OAI211_X4_HVT |OAI211_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 4.5| 17.33|comb | - |VDD VSS +576 |OAI211_X4_HVT |OAI211_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 4.5| 32.42|comb | - |VDD VSS +577 | | | | | | | | +578 |OAI221_X1_LVT |OAI221_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.6| 11134.56|comb | - |VDD VSS +579 |OAI221_X1_LVT |OAI221_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.6| 8801.06|comb | - |VDD VSS +580 |OAI221_X1_SVT |OAI221_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.6| 730.59|comb | - |VDD VSS +581 |OAI221_X1_SVT |OAI221_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.6| 18.25|comb | - |VDD VSS +582 |OAI221_X1_HVT |OAI221_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.6| 5.24|comb | - |VDD VSS +583 |OAI221_X1_HVT |OAI221_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.6| 10.71|comb | - |VDD VSS +584 |OAI221_X2_LVT |OAI221_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 2.9| 22276.41|comb | - |VDD VSS +585 |OAI221_X2_LVT |OAI221_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 2.9| 17602.13|comb | - |VDD VSS +586 |OAI221_X2_SVT |OAI221_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 2.9| 1468.47|comb | - |VDD VSS +587 |OAI221_X2_SVT |OAI221_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 2.9| 36.51|comb | - |VDD VSS +588 |OAI221_X2_HVT |OAI221_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 2.9| 10.48|comb | - |VDD VSS +589 |OAI221_X2_HVT |OAI221_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 2.9| 21.44|comb | - |VDD VSS +590 |OAI221_X4_LVT |OAI221_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 3.5| 55126.84|comb | - |VDD VSS +591 |OAI221_X4_LVT |OAI221_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 3.5| 23895.27|comb | - |VDD VSS +592 |OAI221_X4_SVT |OAI221_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 3.5| 5294.45|comb | - |VDD VSS +593 |OAI221_X4_SVT |OAI221_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 3.5| 71.34|comb | - |VDD VSS +594 |OAI221_X4_HVT |OAI221_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 3.5| 15.35|comb | - |VDD VSS +595 |OAI221_X4_HVT |OAI221_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 3.5| 31.00|comb | - |VDD VSS +596 | | | | | | | | +597 |OAI222_X1_LVT |OAI222_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 2.1| 14009.50|comb | - |VDD VSS +598 |OAI222_X1_LVT |OAI222_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 2.1| 11298.52|comb | - |VDD VSS +599 |OAI222_X1_SVT |OAI222_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 2.1| 906.51|comb | - |VDD VSS +600 |OAI222_X1_SVT |OAI222_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 2.1| 22.64|comb | - |VDD VSS +601 |OAI222_X1_HVT |OAI222_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 2.1| 6.25|comb | - |VDD VSS +602 |OAI222_X1_HVT |OAI222_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 2.1| 13.07|comb | - |VDD VSS +603 |OAI222_X2_LVT |OAI222_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 3.7| 28024.45|comb | - |VDD VSS +604 |OAI222_X2_LVT |OAI222_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 3.7| 22597.04|comb | - |VDD VSS +605 |OAI222_X2_SVT |OAI222_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 3.7| 1818.50|comb | - |VDD VSS +606 |OAI222_X2_SVT |OAI222_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 3.7| 45.29|comb | - |VDD VSS +607 |OAI222_X2_HVT |OAI222_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 3.7| 12.50|comb | - |VDD VSS +608 |OAI222_X2_HVT |OAI222_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 3.7| 26.16|comb | - |VDD VSS +609 |OAI222_X4_LVT |OAI222_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 3.7| 56806.87|comb | - |VDD VSS +610 |OAI222_X4_LVT |OAI222_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 3.7| 27393.84|comb | - |VDD VSS +611 |OAI222_X4_SVT |OAI222_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 3.7| 5258.35|comb | - |VDD VSS +612 |OAI222_X4_SVT |OAI222_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 3.7| 76.00|comb | - |VDD VSS +613 |OAI222_X4_HVT |OAI222_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 3.7| 16.52|comb | - |VDD VSS +614 |OAI222_X4_HVT |OAI222_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 3.7| 33.94|comb | - |VDD VSS +615 | | | | | | | | +616 |OR2_X1_LVT |OR2_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.1| 12071.34|comb | - |VDD VSS +617 |OR2_X1_LVT |OR2_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.1| 4361.05|comb | - |VDD VSS +618 |OR2_X1_SVT |OR2_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.1| 1225.92|comb | - |VDD VSS +619 |OR2_X1_SVT |OR2_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.1| 15.24|comb | - |VDD VSS +620 |OR2_X1_HVT |OR2_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.1| 3.49|comb | - |VDD VSS +621 |OR2_X1_HVT |OR2_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.1| 6.57|comb | - |VDD VSS +622 |OR2_X2_LVT |OR2_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.3| 24255.71|comb | - |VDD VSS +623 |OR2_X2_LVT |OR2_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.3| 8782.71|comb | - |VDD VSS +624 |OR2_X2_SVT |OR2_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.3| 2469.12|comb | - |VDD VSS +625 |OR2_X2_SVT |OR2_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.3| 29.19|comb | - |VDD VSS +626 |OR2_X2_HVT |OR2_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.3| 5.90|comb | - |VDD VSS +627 |OR2_X2_HVT |OR2_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.3| 11.84|comb | - |VDD VSS +628 |OR2_X4_LVT |OR2_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 2.4| 48501.68|comb | - |VDD VSS +629 |OR2_X4_LVT |OR2_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 2.4| 17565.34|comb | - |VDD VSS +630 |OR2_X4_SVT |OR2_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 2.4| 4928.49|comb | - |VDD VSS +631 |OR2_X4_SVT |OR2_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 2.4| 58.37|comb | - |VDD VSS +632 |OR2_X4_HVT |OR2_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 2.4| 11.79|comb | - |VDD VSS +633 |OR2_X4_HVT |OR2_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 2.4| 23.67|comb | - |VDD VSS +634 | | | | | | | | +635 |OR3_X1_LVT |OR3_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.3| 12500.44|comb | - |VDD VSS +636 |OR3_X1_LVT |OR3_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.3| 4959.28|comb | - |VDD VSS +637 |OR3_X1_HVT |OR3_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.3| 3.86|comb | - |VDD VSS +638 |OR3_X1_HVT |OR3_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.3| 7.34|comb | - |VDD VSS +639 |OR3_X1_SVT |OR3_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.3| 1240.87|comb | - |VDD VSS +640 |OR3_X1_SVT |OR3_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.3| 16.20|comb | - |VDD VSS +641 |OR3_X2_LVT |OR3_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.6| 25109.25|comb | - |VDD VSS +642 |OR3_X2_LVT |OR3_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.6| 10004.80|comb | - |VDD VSS +643 |OR3_X2_HVT |OR3_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.6| 6.47|comb | - |VDD VSS +644 |OR3_X2_HVT |OR3_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.6| 13.15|comb | - |VDD VSS +645 |OR3_X2_SVT |OR3_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.6| 2495.97|comb | - |VDD VSS +646 |OR3_X2_SVT |OR3_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.6| 30.83|comb | - |VDD VSS +647 |OR3_X4_LVT |OR3_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 2.9| 50206.10|comb | - |VDD VSS +648 |OR3_X4_LVT |OR3_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 2.9| 20009.61|comb | - |VDD VSS +649 |OR3_X4_HVT |OR3_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 2.9| 12.95|comb | - |VDD VSS +650 |OR3_X4_HVT |OR3_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 2.9| 26.32|comb | - |VDD VSS +651 |OR3_X4_SVT |OR3_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 2.9| 4979.51|comb | - |VDD VSS +652 |OR3_X4_SVT |OR3_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 2.9| 61.67|comb | - |VDD VSS +653 | | | | | | | | +654 |OR4_X1_LVT |OR4_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.6| 12672.53|comb | - |VDD VSS +655 |OR4_X1_LVT |OR4_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.6| 5780.35|comb | - |VDD VSS +656 |OR4_X1_HVT |OR4_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.6| 4.17|comb | - |VDD VSS +657 |OR4_X1_HVT |OR4_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.6| 8.10|comb | - |VDD VSS +658 |OR4_X1_SVT |OR4_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.6| 1211.75|comb | - |VDD VSS +659 |OR4_X1_SVT |OR4_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.6| 17.15|comb | - |VDD VSS +660 |OR4_X2_LVT |OR4_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.9| 25449.56|comb | - |VDD VSS +661 |OR4_X2_LVT |OR4_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.9| 11672.67|comb | - |VDD VSS +662 |OR4_X2_HVT |OR4_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.9| 7.02|comb | - |VDD VSS +663 |OR4_X2_HVT |OR4_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.9| 14.60|comb | - |VDD VSS +664 |OR4_X2_SVT |OR4_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.9| 2435.22|comb | - |VDD VSS +665 |OR4_X2_SVT |OR4_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.9| 32.58|comb | - |VDD VSS +666 |OR4_X4_LVT |OR4_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 3.5| 50886.98|comb | - |VDD VSS +667 |OR4_X4_LVT |OR4_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 3.5| 23345.31|comb | - |VDD VSS +668 |OR4_X4_HVT |OR4_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 3.5| 14.04|comb | - |VDD VSS +669 |OR4_X4_HVT |OR4_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 3.5| 29.21|comb | - |VDD VSS +670 |OR4_X4_SVT |OR4_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 3.5| 4858.25|comb | - |VDD VSS +671 |OR4_X4_SVT |OR4_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 3.5| 65.17|comb | - |VDD VSS +672 | | | | | | | | +673 |SDFFRS_X1_LVT |SDFFRS_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 7.7| 49253.68|ff | - |VDD VSS +674 |SDFFRS_X1_LVT |SDFFRS_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 7.7| 27914.20|ff | - |VDD VSS +675 |SDFFRS_X1_SVT |SDFFRS_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 7.7| 4200.09|ff | - |VDD VSS +676 |SDFFRS_X1_SVT |SDFFRS_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 7.7| 79.03|ff | - |VDD VSS +677 |SDFFRS_X1_HVT |SDFFRS_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 7.7| 23.02|ff | - |VDD VSS +678 |SDFFRS_X1_HVT |SDFFRS_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 7.7| 42.12|ff | - |VDD VSS +679 |SDFFRS_X2_LVT |SDFFRS_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 8.2| 65967.41|ff | - |VDD VSS +680 |SDFFRS_X2_LVT |SDFFRS_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 8.2| 36263.16|ff | - |VDD VSS +681 |SDFFRS_X2_SVT |SDFFRS_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 8.2| 5740.45|ff | - |VDD VSS +682 |SDFFRS_X2_SVT |SDFFRS_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 8.2| 101.55|ff | - |VDD VSS +683 |SDFFRS_X2_HVT |SDFFRS_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 8.2| 27.33|ff | - |VDD VSS +684 |SDFFRS_X2_HVT |SDFFRS_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 8.2| 51.47|ff | - |VDD VSS +685 | | | | | | | | +686 |SDFFR_X1_LVT |SDFFR_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 6.7| 44449.59|ff | - |VDD VSS +687 |SDFFR_X1_LVT |SDFFR_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 6.7| 23551.53|ff | - |VDD VSS +688 |SDFFR_X1_SVT |SDFFR_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 6.7| 3911.69|ff | - |VDD VSS +689 |SDFFR_X1_SVT |SDFFR_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 6.7| 68.71|ff | - |VDD VSS +690 |SDFFR_X1_HVT |SDFFR_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 6.7| 19.85|ff | - |VDD VSS +691 |SDFFR_X1_HVT |SDFFR_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 6.7| 36.14|ff | - |VDD VSS +692 |SDFFR_X2_LVT |SDFFR_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 6.9| 61703.57|ff | - |VDD VSS +693 |SDFFR_X2_LVT |SDFFR_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 6.9| 30805.23|ff | - |VDD VSS +694 |SDFFR_X2_HVT |SDFFR_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 6.9| 44.69|ff | - |VDD VSS +695 |SDFFR_X2_HVT |SDFFR_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 6.9| 44.69|ff | - |VDD VSS +696 |SDFFR_X2_SVT |SDFFR_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 6.9| 5619.51|ff | - |VDD VSS +697 |SDFFR_X2_SVT |SDFFR_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 6.9| 90.68|ff | - |VDD VSS +698 | | | | | | | | +699 |SDFFS_X1_LVT |SDFFS_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 6.7| 45291.00|ff | - |VDD VSS +700 |SDFFS_X1_LVT |SDFFS_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 6.7| 23968.65|ff | - |VDD VSS +701 |SDFFS_X1_SVT |SDFFS_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 6.7| 4010.54|ff | - |VDD VSS +702 |SDFFS_X1_SVT |SDFFS_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 6.7| 70.21|ff | - |VDD VSS +703 |SDFFS_X1_HVT |SDFFS_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 6.7| 19.95|ff | - |VDD VSS +704 |SDFFS_X1_HVT |SDFFS_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 6.7| 36.51|ff | - |VDD VSS +705 |SDFFS_X2_LVT |SDFFS_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 7.2| 61540.50|ff | - |VDD VSS +706 |SDFFS_X2_LVT |SDFFS_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 7.2| 30391.07|ff | - |VDD VSS +707 |SDFFS_X2_SVT |SDFFS_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 7.2| 5580.02|ff | - |VDD VSS +708 |SDFFS_X2_SVT |SDFFS_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 7.2| 90.17|ff | - |VDD VSS +709 |SDFFS_X2_HVT |SDFFS_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 7.2| 44.51|ff | - |VDD VSS +710 |SDFFS_X2_HVT |SDFFS_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 7.2| 44.51|ff | - |VDD VSS +711 | | | | | | | | +712 |SDFF_X1_LVT |SDFF_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 6.1| 44807.42|ff | - |VDD VSS +713 |SDFF_X1_LVT |SDFF_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 6.1| 21712.26|ff | - |VDD VSS +714 |SDFF_X1_SVT |SDFF_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 6.1| 4100.46|ff | - |VDD VSS +715 |SDFF_X1_SVT |SDFF_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 6.1| 67.31|ff | - |VDD VSS +716 |SDFF_X1_HVT |SDFF_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 6.1| 19.03|ff | - |VDD VSS +717 |SDFF_X1_HVT |SDFF_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 6.1| 34.32|ff | - |VDD VSS +718 |SDFF_X2_LVT |SDFF_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 6.4| 62432.24|ff | - |VDD VSS +719 |SDFF_X2_LVT |SDFF_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 6.4| 28663.83|ff | - |VDD VSS +720 |SDFF_X2_SVT |SDFF_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 6.4| 5870.17|ff | - |VDD VSS +721 |SDFF_X2_SVT |SDFF_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 6.4| 89.18|ff | - |VDD VSS +722 |SDFF_X2_HVT |SDFF_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 6.4| 22.99|ff | - |VDD VSS +723 |SDFF_X2_HVT |SDFF_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 6.4| 42.68|ff | - |VDD VSS +724 | | | | | | | | +725 |TBUF_X1_LVT |TBUF_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 2.1| 15053.89|comb | - |VDD VSS +726 |TBUF_X1_LVT |TBUF_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 2.1| 6985.73|comb | - |VDD VSS +727 |TBUF_X1_SVT |TBUF_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 2.1| 1396.15|comb | - |VDD VSS +728 |TBUF_X1_SVT |TBUF_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 2.1| 21.51|comb | - |VDD VSS +729 |TBUF_X1_HVT |TBUF_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 2.1| 5.85|comb | - |VDD VSS +730 |TBUF_X1_HVT |TBUF_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 2.1| 10.69|comb | - |VDD VSS +731 |TBUF_X2_LVT |TBUF_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 2.4| 26846.83|comb | - |VDD VSS +732 |TBUF_X2_LVT |TBUF_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 2.4| 12708.40|comb | - |VDD VSS +733 |TBUF_X2_SVT |TBUF_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 2.4| 2462.03|comb | - |VDD VSS +734 |TBUF_X2_SVT |TBUF_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 2.4| 35.55|comb | - |VDD VSS +735 |TBUF_X2_HVT |TBUF_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 2.4| 8.34|comb | - |VDD VSS +736 |TBUF_X2_HVT |TBUF_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 2.4| 16.54|comb | - |VDD VSS +737 |TBUF_X4_LVT |TBUF_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 2.9| 34700.39|comb | - |VDD VSS +738 |TBUF_X4_LVT |TBUF_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 2.9| 15102.14|comb | - |VDD VSS +739 |TBUF_X4_SVT |TBUF_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 2.9| 3253.35|comb | - |VDD VSS +740 |TBUF_X4_SVT |TBUF_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 2.9| 44.41|comb | - |VDD VSS +741 |TBUF_X4_HVT |TBUF_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 2.9| 10.31|comb | - |VDD VSS +742 |TBUF_X4_HVT |TBUF_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 2.9| 20.18|comb | - |VDD VSS +743 |TBUF_X8_LVT |TBUF_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 4.8| 69488.50|comb | - |VDD VSS +744 |TBUF_X8_LVT |TBUF_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 4.8| 30237.76|comb | - |VDD VSS +745 |TBUF_X8_SVT |TBUF_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 4.8| 6511.93|comb | - |VDD VSS +746 |TBUF_X8_SVT |TBUF_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 4.8| 88.01|comb | - |VDD VSS +747 |TBUF_X8_HVT |TBUF_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 4.8| 19.90|comb | - |VDD VSS +748 |TBUF_X8_HVT |TBUF_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 4.8| 39.47|comb | - |VDD VSS +749 |TBUF_X16_LVT |TBUF_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 6.9| 100923.81|comb | - |VDD VSS +750 |TBUF_X16_LVT |TBUF_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 6.9| 39809.90|comb | - |VDD VSS +751 |TBUF_X16_SVT |TBUF_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 6.9| 9702.92|comb | - |VDD VSS +752 |TBUF_X16_SVT |TBUF_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 6.9| 123.46|comb | - |VDD VSS +753 |TBUF_X16_HVT |TBUF_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 6.9| 27.82|comb | - |VDD VSS +754 |TBUF_X16_HVT |TBUF_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 6.9| 54.04|comb | - |VDD VSS +755 | | | | | | | | +756 |TINV_X1_LVT |TINV_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.1| 7014.86|comb | - |VDD VSS +757 |TINV_X1_LVT |TINV_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.1| 4314.66|comb | - |VDD VSS +758 |TINV_X1_SVT |TINV_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.1| 551.66|comb | - |VDD VSS +759 |TINV_X1_SVT |TINV_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.1| 10.57|comb | - |VDD VSS +760 |TINV_X1_HVT |TINV_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.1| 2.98|comb | - |VDD VSS +761 |TINV_X1_HVT |TINV_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.1| 5.71|comb | - |VDD VSS +762 | | | | | | | | +763 |TLAT_X1_LVT |TLAT_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 3.5| 19793.10|latch | - |VDD VSS +764 |TLAT_X1_LVT |TLAT_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 3.5| 11023.25|latch | - |VDD VSS +765 |TLAT_X1_SVT |TLAT_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 3.5| 1675.98|latch | - |VDD VSS +766 |TLAT_X1_SVT |TLAT_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 3.5| 31.58|latch | - |VDD VSS +767 |TLAT_X1_HVT |TLAT_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 3.5| 9.68|latch | - |VDD VSS +768 |TLAT_X1_HVT |TLAT_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 3.5| 17.32|latch | - |VDD VSS +769 | | | | | | | | +770 |XNOR2_X1_LVT |XNOR2_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.6| 15073.17|comb | - |VDD VSS +771 |XNOR2_X1_LVT |XNOR2_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.6| 8181.50|comb | - |VDD VSS +772 |XNOR2_X1_SVT |XNOR2_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.6| 1300.24|comb | - |VDD VSS +773 |XNOR2_X1_SVT |XNOR2_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.6| 21.96|comb | - |VDD VSS +774 |XNOR2_X1_HVT |XNOR2_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.6| 5.65|comb | - |VDD VSS +775 |XNOR2_X1_HVT |XNOR2_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.6| 10.92|comb | - |VDD VSS +776 |XNOR2_X2_LVT |XNOR2_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 2.7| 30237.72|comb | - |VDD VSS +777 |XNOR2_X2_LVT |XNOR2_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 2.7| 16410.38|comb | - |VDD VSS +778 |XNOR2_X2_SVT |XNOR2_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 2.7| 2603.10|comb | - |VDD VSS +779 |XNOR2_X2_SVT |XNOR2_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 2.7| 42.64|comb | - |VDD VSS +780 |XNOR2_X2_HVT |XNOR2_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 2.7| 10.25|comb | - |VDD VSS +781 |XNOR2_X2_HVT |XNOR2_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 2.7| 20.53|comb | - |VDD VSS +782 | | | | | | | | +783 |XOR2_X1_LVT |XOR2_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 1.6| 16413.58|comb | - |VDD VSS +784 |XOR2_X1_LVT |XOR2_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 1.6| 7821.25|comb | - |VDD VSS +785 |XOR2_X1_SVT |XOR2_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 1.6| 1509.17|comb | - |VDD VSS +786 |XOR2_X1_SVT |XOR2_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 1.6| 22.62|comb | - |VDD VSS +787 |XOR2_X1_HVT |XOR2_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 1.6| 5.67|comb | - |VDD VSS +788 |XOR2_X1_HVT |XOR2_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 1.6| 10.85|comb | - |VDD VSS +789 |XOR2_X2_LVT |XOR2_X1_LVT |NangateOpenCellLibrary_45nm_LVT_0p85| 2.4| 32933.52|comb | - |VDD VSS +790 |XOR2_X2_LVT |XOR2_X1_LVT |NangateOpenCellLibrary_45nm_LVT | 2.4| 15703.12|comb | - |VDD VSS +791 |XOR2_X2_SVT |XOR2_X1_LVT |NangateOpenCellLibrary_45nm_SVT_0p85| 2.4| 3028.95|comb | - |VDD VSS +792 |XOR2_X2_SVT |XOR2_X1_LVT |NangateOpenCellLibrary_45nm_SVT | 2.4| 43.95|comb | - |VDD VSS +793 |XOR2_X2_HVT |XOR2_X1_LVT |NangateOpenCellLibrary_45nm_HVT_0p85| 2.4| 10.26|comb | - |VDD VSS +794 |XOR2_X2_HVT |XOR2_X1_LVT |NangateOpenCellLibrary_45nm_HVT | 2.4| 20.38|comb | - |VDD VSS +795 | | | | | | | | +-----+-----------------+-----------------+------------------------------------+-----------+------------+-----------------+----------+-------- +> report_cells +Report Cell Usage: +-----+-----------------+-----------------+-----+----+-----+-----------+------------+------------+-----------------+------------------------------------ + |Cell |Family |Type |Data|Count|Area (squm)|Total (squm)|Leakage (nw)|Total Leakage(nw)|Library +-----+-----------------+-----------------+-----+----+-----+-----------+------------+------------+-----------------+------------------------------------ +1 |AND2_X1_LVT |AND2_X1_LVT |comb |Both| 78| 1.1| 83.0| 9.622| 750.518|NangateOpenCellLibrary_45nm_LVT_0p85 +2 |AND3_X1_LVT |AND3_X1_LVT |comb |Both| 3| 1.3| 4.0| 8.735| 26.204|NangateOpenCellLibrary_45nm_LVT_0p85 +3 |AND4_X1_LVT |AND4_X1_LVT |comb |Both| 3| 1.6| 4.8| 8.073| 24.219|NangateOpenCellLibrary_45nm_LVT_0p85 +4 |AOI211_X1_LVT |AOI211_X1_LVT |comb |Both| 21| 1.3| 27.9| 10.178| 213.733|NangateOpenCellLibrary_45nm_LVT_0p85 +5 |AOI21_X1_LVT |AOI21_X1_LVT |comb |Both| 77| 1.1| 81.9| 10.194| 784.900|NangateOpenCellLibrary_45nm_LVT_0p85 +6 |AOI221_X1_LVT |AOI221_X1_LVT |comb |Both| 189| 1.6| 301.6| 12.681| 2396.623|NangateOpenCellLibrary_45nm_LVT_0p85 +7 |AOI222_X1_LVT |AOI222_X1_LVT |comb |Both| 138| 2.1| 293.7| 15.199| 2097.457|NangateOpenCellLibrary_45nm_LVT_0p85 +8 |AOI22_X1_LVT |AOI22_X1_LVT |comb |Both| 998| 1.3| 1327.3| 12.027| 12003.334|NangateOpenCellLibrary_45nm_LVT_0p85 +9 |CLKBUF_X3_LVT |BUF_X1_LVT |comb |Both| 4| 1.3| 5.3| 15.617| 62.468|NangateOpenCellLibrary_45nm_LVT_0p85 +10 |CLKGATETST_X1_LVT|CLKGATETST_X1_LVT|comb |Both| 31| 4.0| 123.7| 26.017| 806.518|NangateOpenCellLibrary_45nm_LVT_0p85 +11 |FA_X1_LVT |FA_X1_LVT |comb |Both| 130| 4.3| 553.3| 29.542| 3840.401|NangateOpenCellLibrary_45nm_LVT_0p85 +12 |HA_X1_LVT |HA_X1_LVT |comb |Both| 33| 2.7| 87.8| 26.034| 859.114|NangateOpenCellLibrary_45nm_LVT_0p85 +13 |INV_X1_LVT |INV_X1_LVT |comb |Both| 301| 0.5| 160.1| 7.012| 2110.677|NangateOpenCellLibrary_45nm_LVT_0p85 +14 |MUX2_X1_LVT |MUX2_X1_LVT |comb |Both| 52| 1.9| 96.8| 15.920| 827.832|NangateOpenCellLibrary_45nm_LVT_0p85 +15 |NAND2_X1_LVT |NAND2_X1_LVT |comb |Both| 221| 0.8| 176.4| 7.432| 1642.559|NangateOpenCellLibrary_45nm_LVT_0p85 +16 |NAND3_X1_LVT |NAND3_X1_LVT |comb |Both| 195| 1.1| 207.5| 6.709| 1308.209|NangateOpenCellLibrary_45nm_LVT_0p85 +17 |NAND4_X1_LVT |NAND4_X1_LVT |comb |Both| 147| 1.3| 195.5| 5.908| 868.515|NangateOpenCellLibrary_45nm_LVT_0p85 +18 |NOR2_X1_LVT |NOR2_X1_LVT |comb |Both| 144| 0.8| 114.9| 8.077| 1163.061|NangateOpenCellLibrary_45nm_LVT_0p85 +19 |NOR3_X1_LVT |NOR3_X1_LVT |comb |Both| 47| 1.1| 50.0| 7.864| 369.593|NangateOpenCellLibrary_45nm_LVT_0p85 +20 |NOR4_X1_LVT |NOR4_X1_LVT |comb |Both| 14| 1.3| 18.6| 7.673| 107.425|NangateOpenCellLibrary_45nm_LVT_0p85 +21 |OAI211_X1_LVT |OAI211_X1_LVT |comb |Both| 24| 1.3| 31.9| 8.070| 193.690|NangateOpenCellLibrary_45nm_LVT_0p85 +22 |OAI21_X1_LVT |OAI21_X1_LVT |comb |Both| 119| 1.1| 126.6| 8.985| 1069.228|NangateOpenCellLibrary_45nm_LVT_0p85 +23 |OAI221_X1_LVT |OAI221_X1_LVT |comb |Both| 44| 1.6| 70.2| 11.135| 489.921|NangateOpenCellLibrary_45nm_LVT_0p85 +24 |OAI222_X1_LVT |OAI222_X1_LVT |comb |Both| 17| 2.1| 36.2| 14.010| 238.162|NangateOpenCellLibrary_45nm_LVT_0p85 +25 |OAI22_X1_LVT |OAI22_X1_LVT |comb |Both| 99| 1.3| 131.7| 11.849| 1173.054|NangateOpenCellLibrary_45nm_LVT_0p85 +26 |OAI33_X1_LVT |OAI33_X1_LVT |comb |Both| 2| 1.9| 3.7| 13.302| 26.604|NangateOpenCellLibrary_45nm_LVT_0p85 +27 |OR2_X1_LVT |OR2_X1_LVT |comb |Both| 17| 1.1| 18.1| 12.071| 205.213|NangateOpenCellLibrary_45nm_LVT_0p85 +28 |OR3_X1_LVT |OR3_X1_LVT |comb |Both| 5| 1.3| 6.7| 12.500| 62.502|NangateOpenCellLibrary_45nm_LVT_0p85 +29 |OR4_X1_LVT |OR4_X1_LVT |comb |Both| 6| 1.6| 9.6| 12.673| 76.035|NangateOpenCellLibrary_45nm_LVT_0p85 +30 |XNOR2_X1_LVT |XNOR2_X1_LVT |comb |Both| 50| 1.6| 79.8| 15.073| 753.658|NangateOpenCellLibrary_45nm_LVT_0p85 +31 |XOR2_X1_LVT |XOR2_X1_LVT |comb |Both| 11| 1.6| 17.6| 16.414| 180.549|NangateOpenCellLibrary_45nm_LVT_0p85 +32 |DFF_X1_LVT |DFF_X1_LVT |ff |Both| 107| 4.5| 483.9| 35.907| 3842.074|NangateOpenCellLibrary_45nm_LVT_0p85 +33 |SDFF_X1_LVT |SDFF_X1_LVT |ff |Both| 1024| 6.1| 6264.8| 44.807| 45882.801|NangateOpenCellLibrary_45nm_LVT_0p85 +34 |DLH_X1_LVT |DLH_X1_LVT |latch|Both| 32| 2.7| 85.1| 18.802| 601.673|NangateOpenCellLibrary_45nm_LVT_0p85 +35 |DLL_X2_LVT |DLL_X1_LVT |latch|Both| 4| 2.9| 11.7| 26.693| 106.771|NangateOpenCellLibrary_45nm_LVT_0p85 +36 |MemGen_16_10 |MemGen_16_10 |macro|Both| 4| 11562.3| 46249.1| 129554.125| 518216.500|MemGen_16_10 +-----+-----------------+-----------------+-----+----+-----+-----------+------------+------------+-----------------+------------------------------------ +> get_target_library +> get_lib_files +> check_library +Report Check Library: +-----+-------------------+------+--------+------+------------------------------------------ + |Item |Errors|Warnings|Status|Description +-----+-------------------+------+--------+------+------------------------------------------ +1 |logical_only_cell | 0| 0|Passed|Logical only cells exist in the libraries +2 |physical_only_cell | 0| 0|Passed|Physical only cells exist in the libraries +3 |no_basic_gates | 0| 0|Passed|No basic gates for synthesis or mapping +4 |no_clock_gate_cells| 0| 0|Passed|No clock-gating cells for clock-gating +5 |bad_physical_lib | 0| 0|Passed|Bad physical libraries (no layer etc.) +-----+-------------------+------+--------+------+------------------------------------------ +> get_target_library +error: incorrect argument "-DFF_X1_LVT" for "get_lib_pins" +--------------------------------------------------------------------- +Usage: + get_lib_pins + [-of_objects ] + [-regexp] + [-nocase] + [-quiet] + [-hsc ] + [-filter ] + + [-comment ] +--------------------------------------------------------------------- +error: object of unexpected type +Unknown operator in 'DFF_X1_LVT': DFF_X1_LVT +error: incorrect argument "DFF_X1_LVT" for "get_lib_pins" (too many arguments?) +--------------------------------------------------------------------- +Usage: + get_lib_pins + [-of_objects ] + [-regexp] + [-nocase] + [-quiet] + [-hsc ] + [-filter ] + + [-comment ] +--------------------------------------------------------------------- +error: incorrect argument "DFF_X1_LVTNangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.l" for "get_lib_pins" (too many arguments?) +--------------------------------------------------------------------- +Usage: + get_lib_pins + [-of_objects ] + [-regexp] + [-nocase] + [-quiet] + [-hsc ] + [-filter ] + + [-comment ] +--------------------------------------------------------------------- diff --git a/oasys.tessent.00/Scan_0/.oasys_netlist.v.swp b/oasys.tessent.00/Scan_0/.oasys_netlist.v.swp new file mode 100644 index 0000000..268cd8c Binary files /dev/null and b/oasys.tessent.00/Scan_0/.oasys_netlist.v.swp differ diff --git a/oasys.tessent.00/Scan_0/cpu.scandef b/oasys.tessent.00/Scan_0/cpu.scandef new file mode 100644 index 0000000..4c9383f --- /dev/null +++ b/oasys.tessent.00/Scan_0/cpu.scandef @@ -0,0 +1,1071 @@ +# +# DESC: ScanDEF written by Tessent Shell on Thu May 28 17:29:02 CEST 2026 +# + +VERSION 5.7 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN cpu ; +UNITS DISTANCE MICRONS 1000 ; + +SCANCHAINS 4 ; + +- scan_segment_0 + + START tessent_persistent_cell_buf_extsi1225_i Z + + FLOATING + thePC_CurrentPC_reg\[30\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[29\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[28\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[27\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[26\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[25\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[24\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[23\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[22\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[21\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[20\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[19\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[18\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[17\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[16\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[15\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[14\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[13\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[12\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[11\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[10\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[9\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[8\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[7\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[6\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[5\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[4\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[3\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[2\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[31\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[1\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[0\] ( IN SI ) ( OUT Q ) + + STOP theRegisters/ts_lockup_latchn_clkc1_intno1054_i D + # Partition constraints - clock domain: clk_25mhz(+); cluster: scanChain_1; chain type: core; scan mode(s): unwrapped + + PARTITION partition_1 MAXBITS 256 ; + + +- scan_segment_1 + + START theRegisters/tessent_persistent_cell_buf_extsi1226_i Z + + FLOATING + theRegisters/registers_reg\[1\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[0\] ( IN SI ) ( OUT Q ) + + STOP theRegisters/ts_lockup_latchn_clkc2_intno1050_i D + # Partition constraints - clock domain: clk_25mhz(+); cluster: scanChain_2; chain type: core; scan mode(s): unwrapped + + PARTITION partition_2 MAXBITS 256 ; + + +- scan_segment_2 + + START theRegisters/tessent_persistent_cell_buf_extsi1227_i Z + + FLOATING + theRegisters/registers_reg\[28\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[0\] ( IN SI ) ( OUT Q ) + + STOP theRegisters/ts_lockup_latchn_clkc3_intno1053_i D + # Partition constraints - clock domain: clk_25mhz(+); cluster: scanChain_3; chain type: core; scan mode(s): unwrapped + + PARTITION partition_3 MAXBITS 256 ; + + +- scan_segment_3 + + START theRegisters/tessent_persistent_cell_buf_extsi1228_i Z + + FLOATING + theRegisters/registers_reg\[4\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[0\] ( IN SI ) ( OUT Q ) + + STOP theRegisters/ts_lockup_latchn_clkc4_intno1051_i D + # Partition constraints - clock domain: clk_25mhz(+); cluster: scanChain_4; chain type: core; scan mode(s): unwrapped + + PARTITION partition_4 MAXBITS 256 ; + + +END SCANCHAINS + +END DESIGN diff --git a/oasys.tessent.00/Scan_0/oasys.sdc b/oasys.tessent.00/Scan_0/oasys.sdc new file mode 100644 index 0000000..c387b78 --- /dev/null +++ b/oasys.tessent.00/Scan_0/oasys.sdc @@ -0,0 +1,62 @@ +# +# Created by +# ../bin/Linux-x86_64-O/oasysGui 22.2-p002 on Thu May 28 17:28:56 2026 +# (C) Mentor Graphics Corporation +# +set_units -time ns -capacitance pf -resistance kohm -power nW -voltage V -current uA +create_clock -period 40 -waveform {0 20} -name clk_25mhz [get_ports clk_25mhz] +set_clock_transition 0.1 [get_clocks clk_25mhz] +set_clock_uncertainty -setup 0.5 [get_clocks clk_25mhz] +set_clock_uncertainty -hold 0.2 [get_clocks clk_25mhz] +set_false_path -from [get_ports {btn[0]}] +group_path -name I2R -from [list [get_ports clk_25mhz] [get_ports {btn[0]}] [get_ports {btn[1]}] [get_ports {btn[2]}] [get_ports {btn[3]}] [get_ports {btn[4]}] [get_ports {btn[5]}] [get_ports {btn[6]}]] +group_path -name I2O -from [list [get_ports clk_25mhz] [get_ports {btn[0]}] [get_ports {btn[1]}] [get_ports {btn[2]}] [get_ports {btn[3]}] [get_ports {btn[4]}] [get_ports {btn[5]}] [get_ports {btn[6]}]] -to [list [get_ports {led[0]}] [get_ports {led[1]}] [get_ports {led[2]}] [get_ports {led[3]}] [get_ports {led[4]}] [get_ports {led[5]}] [get_ports {led[6]}] [get_ports {led[7]}]] +group_path -name R2O -to [list [get_ports {led[0]}] [get_ports {led[1]}] [get_ports {led[2]}] [get_ports {led[3]}] [get_ports {led[4]}] [get_ports {led[5]}] [get_ports {led[6]}] [get_ports {led[7]}]] +set_input_delay 2 -clock clk_25mhz -max [get_ports {btn[6]}] +set_input_delay 2 -clock clk_25mhz -max [get_ports {btn[5]}] +set_input_delay 2 -clock clk_25mhz -max [get_ports {btn[4]}] +set_input_delay 2 -clock clk_25mhz -max [get_ports {btn[3]}] +set_input_delay 2 -clock clk_25mhz -max [get_ports {btn[2]}] +set_input_delay 2 -clock clk_25mhz -max [get_ports {btn[1]}] +set_input_delay 2 -clock clk_25mhz -max [get_ports {btn[0]}] +set_input_delay 0.5 -clock clk_25mhz -min [get_ports {btn[6]}] +set_input_delay 0.5 -clock clk_25mhz -min [get_ports {btn[5]}] +set_input_delay 0.5 -clock clk_25mhz -min [get_ports {btn[4]}] +set_input_delay 0.5 -clock clk_25mhz -min [get_ports {btn[3]}] +set_input_delay 0.5 -clock clk_25mhz -min [get_ports {btn[2]}] +set_input_delay 0.5 -clock clk_25mhz -min [get_ports {btn[1]}] +set_input_delay 0.5 -clock clk_25mhz -min [get_ports {btn[0]}] +set_output_delay 2 -clock clk_25mhz -max [get_ports {led[7]}] +set_output_delay 2 -clock clk_25mhz -max [get_ports {led[6]}] +set_output_delay 2 -clock clk_25mhz -max [get_ports {led[5]}] +set_output_delay 2 -clock clk_25mhz -max [get_ports {led[4]}] +set_output_delay 2 -clock clk_25mhz -max [get_ports {led[3]}] +set_output_delay 2 -clock clk_25mhz -max [get_ports {led[2]}] +set_output_delay 2 -clock clk_25mhz -max [get_ports {led[1]}] +set_output_delay 2 -clock clk_25mhz -max [get_ports {led[0]}] +set_output_delay 0.5 -clock clk_25mhz -min [get_ports {led[7]}] +set_output_delay 0.5 -clock clk_25mhz -min [get_ports {led[6]}] +set_output_delay 0.5 -clock clk_25mhz -min [get_ports {led[5]}] +set_output_delay 0.5 -clock clk_25mhz -min [get_ports {led[4]}] +set_output_delay 0.5 -clock clk_25mhz -min [get_ports {led[3]}] +set_output_delay 0.5 -clock clk_25mhz -min [get_ports {led[2]}] +set_output_delay 0.5 -clock clk_25mhz -min [get_ports {led[1]}] +set_output_delay 0.5 -clock clk_25mhz -min [get_ports {led[0]}] +set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 [get_ports {btn[6]}] +set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 [get_ports {btn[5]}] +set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 [get_ports {btn[4]}] +set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 [get_ports {btn[3]}] +set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 [get_ports {btn[2]}] +set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 [get_ports {btn[1]}] +set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 [get_ports {btn[0]}] +set_load 0.05 [get_ports {led[7]}] +set_load 0.05 [get_ports {led[6]}] +set_load 0.05 [get_ports {led[5]}] +set_load 0.05 [get_ports {led[4]}] +set_load 0.05 [get_ports {led[3]}] +set_load 0.05 [get_ports {led[2]}] +set_load 0.05 [get_ports {led[1]}] +set_load 0.05 [get_ports {led[0]}] +set_operating_conditions -library [get_libs {NangateOpenCellLibrary_45nm_LVT_0p85}] -max slow_0p85V -min slow_0p85V +set_max_fanout 20.000000 [current_design] +set_max_transition 0.500000 [current_design] diff --git a/oasys.tessent.00/Scan_0/oasys_netlist.v b/oasys.tessent.00/Scan_0/oasys_netlist.v new file mode 100644 index 0000000..96359a9 --- /dev/null +++ b/oasys.tessent.00/Scan_0/oasys_netlist.v @@ -0,0 +1,10896 @@ +/* + * Created by + ../bin/Linux-x86_64-O/oasysGui 22.2-p002 on Thu May 28 17:28:55 2026 + * (C) Mentor Graphics Corporation + */ +/* CheckSum: 514746972 */ + +module reg_file(Rs1, Rs2, Rd, RRs1, RRs2, WRd, WrReg, reset, clk, dftIn); + input [4:0]Rs1; + input [4:0]Rs2; + input [4:0]Rd; + output [31:0]RRs1; + output [31:0]RRs2; + input [31:0]WRd; + input WrReg; + input reset; + input clk; + input dftIn; + + wire [31:0]registers_1__ap; + wire n_0_0; + wire [31:0]registers_2__ap; + wire n_0_32; + wire [31:0]registers_3__ap; + wire n_0_33; + wire [31:0]registers_4__ap; + wire n_0_34; + wire [31:0]registers_5__ap; + wire n_0_35; + wire [31:0]registers_6__ap; + wire n_0_36; + wire [31:0]registers_7__ap; + wire n_0_37; + wire [31:0]registers_8__ap; + wire n_0_38; + wire [31:0]registers_9__ap; + wire n_0_39; + wire [31:0]registers_10__ap; + wire n_0_40; + wire [31:0]registers_11__ap; + wire n_0_41; + wire [31:0]registers_12__ap; + wire n_0_42; + wire [31:0]registers_13__ap; + wire n_0_43; + wire [31:0]registers_14__ap; + wire n_0_44; + wire [31:0]registers_15__ap; + wire n_0_45; + wire [31:0]registers_16__ap; + wire n_0_46; + wire [31:0]registers_17__ap; + wire n_0_47; + wire [31:0]registers_18__ap; + wire n_0_48; + wire [31:0]registers_19__ap; + wire n_0_49; + wire [31:0]registers_20__ap; + wire n_0_50; + wire [31:0]registers_21__ap; + wire n_0_51; + wire [31:0]registers_22__ap; + wire n_0_52; + wire [31:0]registers_23__ap; + wire n_0_53; + wire [31:0]registers_24__ap; + wire n_0_54; + wire [31:0]registers_25__ap; + wire n_0_55; + wire [31:0]registers_26__ap; + wire n_0_56; + wire [31:0]registers_27__ap; + wire n_0_57; + wire [31:0]registers_28__ap; + wire n_0_58; + wire [31:0]registers_29__ap; + wire n_0_59; + wire [31:0]registers_30__ap; + wire n_0_60; + wire [31:0]registers_31__ap; + wire n_0_61; + wire [31:0]registers; + wire n_0_31; + wire n_0_30; + wire n_0_29; + wire n_0_28; + wire n_0_27; + wire n_0_26; + wire n_0_25; + wire n_0_24; + wire n_0_0_0; + wire n_0_0_1; + wire n_0_23; + wire n_0_22; + wire n_0_21; + wire n_0_20; + wire n_0_19; + wire n_0_18; + wire n_0_17; + wire n_0_16; + wire n_0_0_2; + wire n_0_0_3; + wire n_0_15; + wire n_0_14; + wire n_0_13; + wire n_0_12; + wire n_0_11; + wire n_0_10; + wire n_0_9; + wire n_0_8; + wire n_0_0_4; + wire n_0_0_5; + wire n_0_7; + wire n_0_0_6; + wire n_0_6; + wire n_0_0_7; + wire n_0_5; + wire n_0_0_8; + wire n_0_4; + wire n_0_0_9; + wire n_0_0_10; + wire n_0_3; + wire n_0_0_11; + wire n_0_2; + wire n_0_0_12; + wire n_0_1; + wire n_0_0_13; + wire n_0_0_14; + wire n_0_0_15; + wire n_0_0_16; + wire n_0_0_17; + wire n_0_0_18; + wire n_0_0_19; + wire n_0_0_20; + wire n_1_0_0; + wire n_1_0_1; + wire n_1_0_2; + wire n_1_0_3; + wire n_1_0_4; + wire n_1_0_5; + wire n_1_0_6; + wire n_1_0_7; + wire n_1_0_8; + wire n_1_0_9; + wire n_1_0_10; + wire n_1_0_11; + wire n_1_0_12; + wire n_1_0_13; + wire n_1_0_14; + wire n_1_0_15; + wire n_1_0_16; + wire n_1_0_17; + wire n_1_0_18; + wire n_1_0_19; + wire n_1_0_20; + wire n_1_0_21; + wire n_1_0_22; + wire n_1_0_23; + wire n_1_0_24; + wire n_1_0_25; + wire n_1_0_26; + wire n_1_0_27; + wire n_1_0_28; + wire n_1_0_29; + wire n_1_0_30; + wire n_1_0_31; + wire n_1_0_32; + wire n_1_0_33; + wire n_1_0_34; + wire n_1_0_35; + wire n_1_0_36; + wire n_1_0_37; + wire n_1_0_38; + wire n_1_0_39; + wire n_1_0_40; + wire n_1_0_41; + wire n_1_0_42; + wire n_1_0_43; + wire n_1_0_44; + wire n_1_0_45; + wire n_1_0_46; + wire n_1_0_47; + wire n_1_0_48; + wire n_1_0_49; + wire n_1_0_50; + wire n_1_0_51; + wire n_1_0_52; + wire n_1_0_53; + wire n_1_0_54; + wire n_1_0_55; + wire n_1_0_56; + wire n_1_0_57; + wire n_1_0_58; + wire n_1_0_59; + wire n_1_0_60; + wire n_1_0_61; + wire n_1_0_62; + wire n_1_0_63; + wire n_1_0_64; + wire n_1_0_65; + wire n_1_0_66; + wire n_1_0_67; + wire n_1_0_68; + wire n_1_0_69; + wire n_1_0_70; + wire n_1_0_71; + wire n_1_0_72; + wire n_1_0_73; + wire n_1_0_74; + wire n_1_0_75; + wire n_1_0_76; + wire n_1_0_77; + wire n_1_0_78; + wire n_1_0_79; + wire n_1_0_80; + wire n_1_0_81; + wire n_1_0_82; + wire n_1_0_83; + wire n_1_0_84; + wire n_1_0_85; + wire n_1_0_86; + wire n_1_0_87; + wire n_1_0_88; + wire n_1_0_89; + wire n_1_0_90; + wire n_1_0_91; + wire n_1_0_92; + wire n_1_0_93; + wire n_1_0_94; + wire n_1_0_95; + wire n_1_0_96; + wire n_1_0_97; + wire n_1_0_98; + wire n_1_0_99; + wire n_1_0_100; + wire n_1_0_101; + wire n_1_0_102; + wire n_1_0_103; + wire n_1_0_104; + wire n_1_0_105; + wire n_1_0_106; + wire n_1_0_107; + wire n_1_0_108; + wire n_1_0_109; + wire n_1_0_110; + wire n_1_0_111; + wire n_1_0_112; + wire n_1_0_113; + wire n_1_0_114; + wire n_1_0_115; + wire n_1_0_116; + wire n_1_0_117; + wire n_1_0_118; + wire n_1_0_119; + wire n_1_0_120; + wire n_1_0_121; + wire n_1_0_122; + wire n_1_0_123; + wire n_1_0_124; + wire n_1_0_125; + wire n_1_0_126; + wire n_1_0_127; + wire n_1_0_128; + wire n_1_0_129; + wire n_1_0_130; + wire n_1_0_131; + wire n_1_0_132; + wire n_1_0_133; + wire n_1_0_134; + wire n_1_0_135; + wire n_1_0_136; + wire n_1_0_137; + wire n_1_0_138; + wire n_1_0_139; + wire n_1_0_140; + wire n_1_0_141; + wire n_1_0_142; + wire n_1_0_143; + wire n_1_0_144; + wire n_1_0_145; + wire n_1_0_146; + wire n_1_0_147; + wire n_1_0_148; + wire n_1_0_149; + wire n_1_0_150; + wire n_1_0_151; + wire n_1_0_152; + wire n_1_0_153; + wire n_1_0_154; + wire n_1_0_155; + wire n_1_0_156; + wire n_1_0_157; + wire n_1_0_158; + wire n_1_0_159; + wire n_1_0_160; + wire n_1_0_161; + wire n_1_0_162; + wire n_1_0_163; + wire n_1_0_164; + wire n_1_0_165; + wire n_1_0_166; + wire n_1_0_167; + wire n_1_0_168; + wire n_1_0_169; + wire n_1_0_170; + wire n_1_0_171; + wire n_1_0_172; + wire n_1_0_173; + wire n_1_0_174; + wire n_1_0_175; + wire n_1_0_176; + wire n_1_0_177; + wire n_1_0_178; + wire n_1_0_179; + wire n_1_0_180; + wire n_1_0_181; + wire n_1_0_182; + wire n_1_0_183; + wire n_1_0_184; + wire n_1_0_185; + wire n_1_0_186; + wire n_1_0_187; + wire n_1_0_188; + wire n_1_0_189; + wire n_1_0_190; + wire n_1_0_191; + wire n_1_0_192; + wire n_1_0_193; + wire n_1_0_194; + wire n_1_0_195; + wire n_1_0_196; + wire n_1_0_197; + wire n_1_0_198; + wire n_1_0_199; + wire n_1_0_200; + wire n_1_0_201; + wire n_1_0_202; + wire n_1_0_203; + wire n_1_0_204; + wire n_1_0_205; + wire n_1_0_206; + wire n_1_0_207; + wire n_1_0_208; + wire n_1_0_209; + wire n_1_0_210; + wire n_1_0_211; + wire n_1_0_212; + wire n_1_0_213; + wire n_1_0_214; + wire n_1_0_215; + wire n_1_0_216; + wire n_1_0_217; + wire n_1_0_218; + wire n_1_0_219; + wire n_1_0_220; + wire n_1_0_221; + wire n_1_0_222; + wire n_1_0_223; + wire n_1_0_224; + wire n_1_0_225; + wire n_1_0_226; + wire n_1_0_227; + wire n_1_0_228; + wire n_1_0_229; + wire n_1_0_230; + wire n_1_0_231; + wire n_1_0_232; + wire n_1_0_233; + wire n_1_0_234; + wire n_1_0_235; + wire n_1_0_236; + wire n_1_0_237; + wire n_1_0_238; + wire n_1_0_239; + wire n_1_0_240; + wire n_1_0_241; + wire n_1_0_242; + wire n_1_0_243; + wire n_1_0_244; + wire n_1_0_245; + wire n_1_0_246; + wire n_1_0_247; + wire n_1_0_248; + wire n_1_0_249; + wire n_1_0_250; + wire n_1_0_251; + wire n_1_0_252; + wire n_1_0_253; + wire n_1_0_254; + wire n_1_0_255; + wire n_1_0_256; + wire n_1_0_257; + wire n_1_0_258; + wire n_1_0_259; + wire n_1_0_260; + wire n_1_0_261; + wire n_1_0_262; + wire n_1_0_263; + wire n_1_0_264; + wire n_1_0_265; + wire n_1_0_266; + wire n_1_0_267; + wire n_1_0_268; + wire n_1_0_269; + wire n_1_0_270; + wire n_1_0_271; + wire n_1_0_272; + wire n_1_0_273; + wire n_1_0_274; + wire n_1_0_275; + wire n_1_0_276; + wire n_1_0_277; + wire n_1_0_278; + wire n_1_0_279; + wire n_1_0_280; + wire n_1_0_281; + wire n_1_0_282; + wire n_1_0_283; + wire n_1_0_284; + wire n_1_0_285; + wire n_1_0_286; + wire n_1_0_287; + wire n_1_0_288; + wire n_1_0_289; + wire n_1_0_290; + wire n_1_0_291; + wire n_1_0_292; + wire n_1_0_293; + wire n_1_0_294; + wire n_1_0_295; + wire n_1_0_296; + wire n_1_0_297; + wire n_1_0_298; + wire n_1_0_299; + wire n_1_0_300; + wire n_1_0_301; + wire n_1_0_302; + wire n_1_0_303; + wire n_1_0_304; + wire n_1_0_305; + wire n_1_0_306; + wire n_1_0_307; + wire n_1_0_308; + wire n_1_0_309; + wire n_1_0_310; + wire n_1_0_311; + wire n_1_0_312; + wire n_1_0_313; + wire n_1_0_314; + wire n_1_0_315; + wire n_1_0_316; + wire n_1_0_317; + wire n_1_0_318; + wire n_1_0_319; + wire n_1_0_320; + wire n_1_0_321; + wire n_1_0_322; + wire n_1_0_323; + wire n_1_0_324; + wire n_1_0_325; + wire n_1_0_326; + wire n_1_0_327; + wire n_1_0_328; + wire n_1_0_329; + wire n_1_0_330; + wire n_1_0_331; + wire n_1_0_332; + wire n_1_0_333; + wire n_1_0_334; + wire n_1_0_335; + wire n_1_0_336; + wire n_1_0_337; + wire n_1_0_338; + wire n_1_0_339; + wire n_1_0_340; + wire n_1_0_341; + wire n_1_0_342; + wire n_1_0_343; + wire n_1_0_344; + wire n_1_0_345; + wire n_1_0_346; + wire n_1_0_347; + wire n_1_0_348; + wire n_1_0_349; + wire n_1_0_350; + wire n_1_0_351; + wire n_1_0_352; + wire n_1_0_353; + wire n_1_0_354; + wire n_1_0_355; + wire n_1_0_356; + wire n_1_0_357; + wire n_1_0_358; + wire n_1_0_359; + wire n_1_0_360; + wire n_1_0_361; + wire n_1_0_362; + wire n_1_0_363; + wire n_1_0_364; + wire n_1_0_365; + wire n_1_0_366; + wire n_1_0_367; + wire n_1_0_368; + wire n_1_0_369; + wire n_1_0_370; + wire n_1_0_371; + wire n_1_0_372; + wire n_1_0_373; + wire n_1_0_374; + wire n_1_0_375; + wire n_1_0_376; + wire n_1_0_377; + wire n_1_0_378; + wire n_1_0_379; + wire n_1_0_380; + wire n_1_0_381; + wire n_1_0_382; + wire n_1_0_383; + wire n_1_0_384; + wire n_1_0_385; + wire n_1_0_386; + wire n_1_0_387; + wire n_1_0_388; + wire n_1_0_389; + wire n_1_0_390; + wire n_1_0_391; + wire n_1_0_392; + wire n_1_0_393; + wire n_1_0_394; + wire n_1_0_395; + wire n_1_0_396; + wire n_1_0_397; + wire n_1_0_398; + wire n_1_0_399; + wire n_1_0_400; + wire n_1_0_401; + wire n_1_0_402; + wire n_1_0_403; + wire n_1_0_404; + wire n_1_0_405; + wire n_1_0_406; + wire n_1_0_407; + wire n_1_0_408; + wire n_1_0_409; + wire n_1_0_410; + wire n_1_0_411; + wire n_1_0_412; + wire n_1_0_413; + wire n_1_0_414; + wire n_1_0_415; + wire n_1_0_416; + wire n_1_0_417; + wire n_1_0_418; + wire n_1_0_419; + wire n_1_0_420; + wire n_1_0_421; + wire n_1_0_422; + wire n_1_0_423; + wire n_1_0_424; + wire n_1_0_425; + wire n_1_0_426; + wire n_1_0_427; + wire n_1_0_428; + wire n_1_0_429; + wire n_1_0_430; + wire n_1_0_431; + wire n_1_0_432; + wire n_1_0_433; + wire n_1_0_434; + wire n_1_0_435; + wire n_1_0_436; + wire n_1_0_437; + wire n_1_0_438; + wire n_1_0_439; + wire n_1_0_440; + wire n_1_0_441; + wire n_1_0_442; + wire n_1_0_443; + wire n_1_0_444; + wire n_1_0_445; + wire n_1_0_446; + wire n_1_0_447; + wire n_1_0_448; + wire n_1_0_449; + wire n_1_0_450; + wire n_1_0_451; + wire n_1_0_452; + wire n_1_0_453; + wire n_1_0_454; + wire n_1_0_455; + wire n_1_0_456; + wire n_1_0_457; + wire n_1_0_458; + wire n_1_0_459; + wire n_1_0_460; + wire n_1_0_461; + wire n_1_0_462; + wire n_1_0_463; + wire n_1_0_464; + wire n_1_0_465; + wire n_1_0_466; + wire n_1_0_467; + wire n_1_0_468; + wire n_1_0_469; + wire n_1_0_470; + wire n_1_0_471; + wire n_1_0_472; + wire n_1_0_473; + wire n_1_0_474; + wire n_1_0_475; + wire n_1_0_476; + wire n_1_0_477; + wire n_1_0_478; + wire n_1_0_479; + wire n_1_0_480; + wire n_1_0_481; + wire n_1_0_482; + wire n_1_0_483; + wire n_1_0_484; + wire n_1_0_485; + wire n_1_0_486; + wire n_1_0_487; + wire n_1_0_488; + wire n_1_0_489; + wire n_1_0_490; + wire n_1_0_491; + wire n_1_0_492; + wire n_1_0_493; + wire n_1_0_494; + wire n_1_0_495; + wire n_1_0_496; + wire n_1_0_497; + wire n_1_0_498; + wire n_1_0_499; + wire n_1_0_500; + wire n_1_0_501; + wire n_1_0_502; + wire n_1_0_503; + wire n_1_0_504; + wire n_1_0_505; + wire n_1_0_506; + wire n_1_0_507; + wire n_1_0_508; + wire n_1_0_509; + wire n_1_0_510; + wire n_1_0_511; + wire n_1_0_512; + wire n_1_0_513; + wire n_1_0_514; + wire n_1_0_515; + wire n_1_0_516; + wire n_1_0_517; + wire n_1_0_518; + wire n_1_0_519; + wire n_1_0_520; + wire n_1_0_521; + wire n_1_0_522; + wire n_1_0_523; + wire n_1_0_524; + wire n_1_0_525; + wire n_1_0_526; + wire n_1_0_527; + wire n_1_0_528; + wire n_1_0_529; + wire n_1_0_530; + wire n_1_0_531; + wire n_1_0_532; + wire n_1_0_533; + wire n_1_0_534; + wire n_1_0_535; + wire n_1_0_536; + wire n_1_0_537; + wire n_1_0_538; + wire n_1_0_539; + wire n_1_0_540; + wire n_1_0_541; + wire n_1_0_542; + wire n_1_0_543; + wire n_1_0_544; + wire n_1_0_545; + wire n_1_0_546; + wire n_1_0_547; + wire n_1_0_548; + wire n_1_0_549; + wire n_1_0_550; + wire n_1_0_551; + wire n_1_0_552; + wire n_1_0_553; + wire n_1_0_554; + wire n_1_0_555; + wire n_1_0_556; + wire n_1_0_557; + wire n_1_0_558; + wire n_1_0_559; + wire n_1_0_560; + wire n_1_0_561; + wire n_1_0_562; + wire n_1_0_563; + wire n_1_0_564; + wire n_1_0_565; + wire n_1_0_566; + wire n_1_0_567; + wire n_1_0_568; + wire n_1_0_569; + wire n_1_0_570; + wire n_1_0_571; + wire n_1_0_572; + wire n_1_0_573; + wire n_1_0_574; + wire n_1_0_575; + wire n_1_0_576; + wire n_1_0_577; + wire n_1_0_578; + wire n_1_0_579; + wire n_1_0_580; + wire n_1_0_581; + wire n_1_0_582; + wire n_1_0_583; + wire n_1_0_584; + wire n_1_0_585; + wire n_1_0_586; + wire n_1_0_587; + wire n_1_0_588; + wire n_1_0_589; + wire n_1_0_590; + wire n_1_0_591; + wire n_1_0_592; + wire n_1_0_593; + wire n_1_0_594; + wire n_1_0_595; + wire n_1_0_596; + wire n_1_0_597; + wire n_1_0_598; + wire n_1_0_599; + wire n_1_0_600; + wire n_1_0_601; + wire n_1_0_602; + wire n_1_0_603; + wire n_1_0_604; + wire n_1_0_605; + wire n_1_0_606; + wire n_1_0_607; + wire n_1_0_608; + wire n_1_0_609; + wire n_1_0_610; + wire n_1_0_611; + wire n_1_0_612; + wire n_1_0_613; + wire n_1_0_614; + wire n_1_0_615; + wire n_1_0_616; + wire n_1_0_617; + wire n_1_0_618; + wire n_1_0_619; + wire n_1_0_620; + wire n_1_0_621; + wire n_1_0_622; + wire n_1_0_623; + wire n_1_0_624; + wire n_1_0_625; + wire n_1_0_626; + wire n_1_0_627; + wire n_1_0_628; + wire n_1_0_629; + wire n_1_0_630; + wire n_1_0_631; + wire n_1_0_632; + wire n_1_0_633; + wire n_1_0_634; + wire n_1_0_635; + wire n_1_0_636; + wire n_1_0_637; + wire n_1_0_638; + wire n_1_0_639; + wire n_1_0_640; + wire n_1_0_641; + wire n_1_0_642; + wire n_1_0_643; + wire n_1_0_644; + wire n_1_0_645; + wire n_1_0_646; + wire n_1_0_647; + wire n_1_0_648; + wire n_1_0_649; + wire n_1_0_650; + wire n_1_0_651; + wire n_1_0_652; + wire n_1_0_653; + wire n_1_0_654; + wire n_1_0_655; + wire n_1_0_656; + wire n_1_0_657; + wire n_1_0_658; + wire n_1_0_659; + wire n_1_0_660; + wire n_1_0_661; + wire n_1_0_662; + wire n_1_0_663; + wire n_1_0_664; + wire n_1_0_665; + wire n_1_0_666; + wire n_1_0_667; + wire n_1_0_668; + wire n_1_0_669; + wire n_1_0_670; + wire n_1_0_671; + wire n_1_0_672; + wire n_1_0_673; + wire n_1_0_674; + wire n_1_0_675; + wire n_1_0_676; + wire n_1_0_677; + wire n_1_0_678; + wire n_1_0_679; + wire n_1_0_680; + wire n_1_0_681; + wire n_1_0_682; + wire n_1_0_683; + wire n_1_0_684; + wire n_1_0_685; + wire n_1_0_686; + wire n_1_0_687; + wire n_1_0_688; + wire n_1_0_689; + wire n_1_0_690; + wire n_1_0_691; + wire n_1_0_692; + wire n_1_0_693; + wire n_1_0_694; + wire n_1_0_695; + wire n_1_0_696; + wire n_1_0_697; + wire n_1_0_698; + wire n_1_0_699; + wire n_1_0_700; + wire n_1_0_701; + wire n_1_0_702; + wire n_1_0_703; + wire n_1_0_704; + wire n_1_0_705; + wire n_1_0_706; + wire n_1_0_707; + wire n_1_0_708; + wire n_1_0_709; + wire n_1_0_710; + wire n_1_0_711; + wire n_1_0_712; + wire n_1_0_713; + wire n_1_0_714; + wire n_1_0_715; + wire n_1_0_716; + wire n_1_0_717; + wire n_1_0_718; + wire n_1_0_719; + wire n_1_0_720; + wire n_1_0_721; + wire n_1_0_722; + wire n_1_0_723; + wire n_1_0_724; + wire n_1_0_725; + wire n_1_0_726; + wire n_1_0_727; + wire n_1_0_728; + wire n_1_0_729; + wire n_1_0_730; + wire n_1_0_731; + wire n_1_0_732; + wire n_1_0_733; + wire n_1_0_734; + wire n_1_0_735; + wire n_1_0_736; + wire n_1_0_737; + wire n_1_0_738; + wire n_1_0_739; + wire n_1_0_740; + wire n_1_0_741; + wire n_1_0_742; + wire n_1_0_743; + wire n_1_0_744; + wire n_1_0_745; + wire n_1_0_746; + wire n_1_0_747; + wire n_1_0_748; + wire n_1_0_749; + wire n_1_0_750; + wire n_1_0_751; + wire n_1_0_752; + wire n_1_0_753; + wire n_1_0_754; + wire n_1_0_755; + wire n_1_0_756; + wire n_1_0_757; + wire n_1_0_758; + wire n_1_0_759; + wire n_1_0_760; + wire n_1_0_761; + wire n_1_0_762; + wire n_1_0_763; + wire n_1_0_764; + wire n_1_0_765; + wire n_1_0_766; + wire n_1_0_767; + wire n_1_0_768; + wire n_1_0_769; + wire n_1_0_770; + wire n_1_0_771; + wire n_1_0_772; + wire n_1_0_773; + wire n_1_0_774; + wire n_1_0_775; + wire n_1_0_776; + wire n_1_0_777; + wire n_1_0_778; + wire n_1_0_779; + wire n_1_0_780; + wire n_1_0_781; + wire n_1_0_782; + wire n_1_0_783; + wire n_1_0_784; + wire n_1_0_785; + wire n_1_0_786; + wire n_1_0_787; + wire n_1_0_788; + wire n_1_0_789; + wire n_1_0_790; + wire n_1_0_791; + wire n_1_0_792; + wire n_1_0_793; + wire n_1_0_794; + wire n_1_0_795; + wire n_1_0_796; + wire n_1_0_797; + wire n_1_0_798; + wire n_1_0_799; + wire n_1_0_800; + wire n_1_0_801; + wire n_1_0_802; + wire n_1_0_803; + wire n_1_0_804; + wire n_1_0_805; + wire n_1_0_806; + wire n_1_0_807; + wire n_1_0_808; + wire n_1_0_809; + wire n_1_0_810; + wire n_1_0_811; + wire n_1_0_812; + wire n_1_0_813; + wire n_1_0_814; + wire n_1_0_815; + wire n_1_0_816; + wire n_1_0_817; + wire n_1_0_818; + wire n_1_0_819; + wire n_1_0_820; + wire n_1_0_821; + wire n_1_0_822; + wire n_1_0_823; + wire n_1_0_824; + wire n_1_0_825; + wire n_1_0_826; + wire n_1_0_827; + wire n_1_0_828; + wire n_1_0_829; + wire n_1_0_830; + wire n_1_0_831; + wire n_1_0_832; + wire n_1_0_833; + wire n_1_0_834; + wire n_1_0_835; + wire n_1_0_836; + wire n_1_0_837; + wire n_1_0_838; + wire n_1_0_839; + wire n_1_0_840; + wire n_1_0_841; + wire n_1_0_842; + wire n_1_0_843; + wire n_1_0_844; + wire n_1_0_845; + wire n_1_0_846; + wire n_1_0_847; + wire n_1_0_848; + wire n_1_0_849; + wire n_1_0_850; + wire n_1_0_851; + wire n_1_0_852; + wire n_1_0_853; + wire n_1_0_854; + wire n_1_0_855; + wire n_1_0_856; + wire n_1_0_857; + wire n_1_0_858; + wire n_1_0_859; + wire n_1_0_860; + wire n_1_0_861; + wire n_1_0_862; + wire n_1_0_863; + wire n_1_0_864; + wire n_1_0_865; + wire n_1_0_866; + wire n_1_0_867; + wire n_1_0_868; + wire n_1_0_869; + wire n_1_0_870; + wire n_1_0_871; + wire n_1_0_872; + wire n_1_0_873; + wire n_1_0_874; + wire n_1_0_875; + wire n_1_0_876; + wire n_1_0_877; + wire n_1_0_878; + wire n_1_0_879; + wire n_1_0_880; + wire n_1_0_881; + wire n_1_0_882; + wire n_1_0_883; + wire n_1_0_884; + wire n_1_0_885; + wire n_1_0_886; + wire n_1_0_887; + wire n_1_0_888; + wire n_1_0_889; + wire n_1_0_890; + wire n_1_0_891; + wire n_1_0_892; + wire n_1_0_893; + wire n_1_0_894; + wire n_1_0_895; + wire n_1_0_896; + wire n_1_0_897; + wire n_1_0_898; + wire n_1_0_899; + wire n_1_0_900; + wire n_1_0_901; + wire n_1_0_902; + wire n_1_0_903; + wire n_1_0_904; + wire n_1_0_905; + wire n_1_0_906; + wire n_1_0_907; + wire n_1_0_908; + wire n_1_0_909; + wire n_1_0_910; + wire n_1_0_911; + wire n_1_0_912; + wire n_1_0_913; + wire n_1_0_914; + wire n_1_0_915; + wire n_1_0_916; + wire n_1_0_917; + wire n_1_0_918; + wire n_1_0_919; + wire n_1_0_920; + wire n_1_0_921; + wire n_1_0_922; + wire n_1_0_923; + wire n_1_0_924; + wire n_1_0_925; + wire n_1_0_926; + wire n_1_0_927; + wire n_1_0_928; + wire n_1_0_929; + wire n_1_0_930; + wire n_1_0_931; + wire n_1_0_932; + wire n_1_0_933; + wire n_1_0_934; + wire n_1_0_935; + wire n_1_0_936; + wire n_1_0_937; + wire n_1_0_938; + wire n_1_0_939; + wire n_1_0_940; + wire n_1_0_941; + wire n_1_0_942; + wire n_1_0_943; + wire n_1_0_944; + wire n_1_0_945; + wire n_1_0_946; + wire n_1_0_947; + wire n_1_0_948; + wire n_1_0_949; + wire n_1_0_950; + wire n_1_0_951; + wire n_1_0_952; + wire n_1_0_953; + wire n_1_0_954; + wire n_1_0_955; + wire n_1_0_956; + wire n_1_0_957; + wire n_1_0_958; + wire n_1_0_959; + wire n_1_0_960; + wire n_1_0_961; + wire n_1_0_962; + wire n_1_0_963; + wire n_1_0_964; + wire n_1_0_965; + wire n_1_0_966; + wire n_1_0_967; + wire n_1_0_968; + wire n_1_0_969; + wire n_1_0_970; + wire n_1_0_971; + wire n_1_0_972; + wire n_1_0_973; + wire n_1_0_974; + wire n_1_0_975; + wire n_1_0_976; + wire n_1_0_977; + wire n_1_0_978; + wire n_1_0_979; + wire n_1_0_980; + wire n_1_0_981; + wire n_1_0_982; + wire n_1_0_983; + wire n_1_0_984; + wire n_1_0_985; + wire n_1_0_986; + wire n_1_0_987; + wire n_1_0_988; + wire n_1_0_989; + wire n_1_0_990; + wire n_1_0_991; + wire n_1_0_992; + wire n_1_0_993; + wire n_1_0_994; + wire n_1_0_995; + wire n_1_0_996; + wire n_1_0_997; + wire n_1_0_998; + wire n_1_0_999; + wire n_1_0_1000; + wire n_1_0_1001; + wire n_1_0_1002; + wire n_1_0_1003; + wire n_1_0_1004; + wire n_1_0_1005; + wire n_1_0_1006; + wire n_1_0_1007; + wire n_1_0_1008; + wire n_1_0_1009; + wire n_1_0_1010; + wire n_1_0_1011; + wire n_1_0_1012; + wire n_1_0_1013; + wire n_1_0_1014; + wire n_1_0_1015; + wire n_1_0_1016; + wire n_1_0_1017; + wire n_1_0_1018; + wire n_1_0_1019; + wire n_1_0_1020; + wire n_1_0_1021; + wire n_1_0_1022; + wire n_1_0_1023; + wire n_1_0_1024; + wire n_1_0_1025; + wire n_1_0_1026; + wire n_1_0_1027; + wire n_1_0_1028; + wire n_1_0_1029; + wire n_1_0_1030; + wire n_1_0_1031; + wire n_1_0_1032; + wire n_1_0_1033; + wire n_1_0_1034; + wire n_1_0_1035; + wire n_1_0_1036; + wire n_1_0_1037; + wire n_1_0_1038; + wire n_1_0_1039; + wire n_1_0_1040; + wire n_1_0_1041; + wire n_1_0_1042; + wire n_1_0_1043; + wire n_1_0_1044; + wire n_1_0_1045; + wire n_1_0_1046; + wire n_1_0_1047; + wire n_1_0_1048; + wire n_1_0_1049; + wire n_1_0_1050; + wire n_1_0_1051; + wire n_1_0_1052; + wire n_1_0_1053; + wire n_1_0_1054; + wire n_1_0_1055; + wire n_1_0_1056; + wire n_1_0_1057; + wire n_1_0_1058; + wire n_1_0_1059; + wire n_1_0_1060; + wire n_1_0_1061; + wire n_1_0_1062; + wire n_1_0_1063; + wire n_1_0_1064; + wire n_1_0_1065; + wire n_1_0_1066; + wire n_1_0_1067; + wire n_1_0_1068; + wire n_1_0_1069; + wire n_1_0_1070; + wire n_1_0_1071; + wire n_1_0_1072; + wire n_1_0_1073; + wire n_1_0_1074; + wire n_1_0_1075; + wire n_1_0_1076; + wire n_1_0_1077; + wire n_1_0_1078; + wire n_1_0_1079; + wire n_1_0_1080; + wire n_1_0_1081; + wire n_1_0_1082; + wire n_1_0_1083; + wire n_1_0_1084; + wire n_1_0_1085; + wire n_1_0_1086; + wire n_1_0_1087; + wire n_1_0_1088; + wire n_1_0_1089; + wire n_1_0_1090; + wire n_1_0_1091; + wire n_1_0_1092; + wire n_1_0_1093; + wire n_1_0_1094; + wire n_1_0_1095; + wire n_1_0_1096; + wire n_1_0_1097; + wire n_1_0_1098; + wire n_1_0_1099; + wire n_1_0_1100; + wire n_1_0_1101; + wire n_1_0_1102; + wire n_1_0_1103; + wire n_1_0_1104; + wire n_1_0_1105; + wire n_1_0_1106; + wire n_1_0_1107; + wire n_1_0_1108; + wire n_1_0_1109; + wire n_1_0_1110; + wire n_1_0_1111; + wire n_1_0_1112; + wire n_1_0_1113; + wire n_1_0_1114; + wire n_1_0_1115; + wire n_1_0_1116; + wire n_1_0_1117; + wire n_1_0_1118; + wire n_1_0_1119; + wire n_1_0_1120; + wire n_1_0_1121; + wire n_1_0_1122; + wire n_1_0_1123; + wire n_1_0_1124; + wire n_1_0_1125; + wire n_1_0_1126; + wire n_1_0_1127; + wire n_1_0_1128; + wire n_1_0_1129; + wire n_1_0_1130; + wire n_1_0_1131; + wire n_1_0_1132; + wire n_1_0_1133; + wire n_1_0_1134; + wire n_1_0_1135; + wire n_1_0_1136; + wire n_1_0_1137; + wire n_1_0_1138; + wire n_1_0_1139; + wire n_1_0_1140; + wire n_1_0_1141; + wire n_1_0_1142; + wire n_1_0_1143; + wire n_1_0_1144; + wire n_1_0_1145; + wire n_1_0_1146; + wire n_1_0_1147; + wire n_1_0_1148; + wire n_1_0_1149; + wire n_1_0_1150; + wire n_1_0_1151; + wire n_1_0_1152; + wire n_1_0_1153; + wire n_1_0_1154; + wire n_1_0_1155; + wire n_1_0_1156; + wire n_1_0_1157; + wire n_1_0_1158; + wire n_1_0_1159; + wire n_1_0_1160; + wire n_1_0_1161; + wire n_1_0_1162; + wire n_1_0_1163; + wire n_1_0_1164; + wire n_1_0_1165; + wire n_1_0_1166; + wire n_1_0_1167; + wire n_1_0_1168; + wire n_1_0_1169; + wire n_1_0_1170; + wire n_1_0_1171; + wire n_1_0_1172; + wire n_1_0_1173; + wire n_1_0_1174; + wire n_1_0_1175; + wire n_1_0_1176; + wire n_1_0_1177; + wire n_1_0_1178; + wire n_1_0_1179; + wire n_1_0_1180; + wire n_1_0_1181; + wire n_1_0_1182; + wire n_1_0_1183; + wire n_1_0_1184; + wire n_1_0_1185; + wire n_1_0_1186; + wire n_1_0_1187; + wire n_1_0_1188; + wire n_1_0_1189; + wire n_1_0_1190; + wire n_1_0_1191; + wire n_1_0_1192; + wire n_1_0_1193; + wire n_1_0_1194; + wire n_1_0_1195; + wire n_1_0_1196; + wire n_1_0_1197; + wire n_1_0_1198; + wire n_1_0_1199; + wire n_1_0_1200; + wire n_1_0_1201; + wire n_1_0_1202; + wire n_1_0_1203; + wire n_1_0_1204; + wire n_1_0_1205; + wire n_1_0_1206; + wire n_1_0_1207; + wire n_1_0_1208; + wire n_1_0_1209; + wire n_1_0_1210; + wire n_1_0_1211; + wire n_1_0_1212; + wire n_1_0_1213; + wire n_1_0_1214; + wire n_1_0_1215; + wire n_1_0_1216; + wire n_1_0_1217; + wire n_1_0_1218; + wire n_1_0_1219; + wire n_1_0_1220; + wire n_1_0_1221; + wire n_1_0_1222; + wire n_1_0_1223; + wire n_1_0_1224; + wire n_1_0_1225; + wire n_1_0_1226; + wire n_1_0_1227; + wire n_1_0_1228; + wire n_1_0_1229; + wire n_1_0_1230; + wire n_1_0_1231; + wire n_1_0_1232; + wire n_1_0_1233; + wire n_1_0_1234; + wire n_1_0_1235; + wire n_1_0_1236; + wire n_1_0_1237; + wire n_1_0_1238; + wire n_1_0_1239; + wire n_1_0_1240; + wire n_1_0_1241; + wire n_1_0_1242; + wire n_1_0_1243; + wire n_1_0_1244; + wire n_1_0_1245; + wire n_1_0_1246; + wire n_1_0_1247; + wire n_1_0_1248; + wire n_1_0_1249; + wire n_1_0_1250; + wire n_1_0_1251; + wire n_1_0_1252; + wire n_1_0_1253; + wire n_1_0_1254; + wire n_1_0_1255; + wire n_1_0_1256; + wire n_1_0_1257; + wire n_1_0_1258; + wire n_1_0_1259; + wire n_1_0_1260; + wire n_1_0_1261; + wire n_1_0_1262; + wire n_1_0_1263; + wire n_1_0_1264; + wire n_1_0_1265; + wire n_1_0_1266; + wire n_1_0_1267; + wire n_1_0_1268; + wire n_1_0_1269; + wire n_1_0_1270; + wire n_1_0_1271; + wire n_1_0_1272; + wire n_1_0_1273; + wire n_1_0_1274; + wire n_1_0_1275; + wire n_1_0_1276; + wire n_1_0_1277; + wire n_1_0_1278; + wire n_1_0_1279; + wire n_1_0_1280; + wire n_1_0_1281; + wire n_1_0_1282; + wire n_1_0_1283; + wire n_1_0_1284; + wire n_1_0_1285; + wire n_1_0_1286; + wire n_1_0_1287; + wire n_1_0_1288; + wire n_1_0_1289; + wire n_1_0_1290; + wire n_1_0_1291; + wire n_1_0_1292; + wire n_1_0_1293; + wire n_1_0_1294; + wire n_1_0_1295; + wire n_1_0_1296; + wire n_1_0_1297; + wire n_1_0_1298; + wire n_1_0_1299; + wire n_1_0_1300; + wire n_1_0_1301; + wire n_1_0_1302; + wire n_1_0_1303; + wire n_1_0_1304; + wire n_1_0_1305; + wire n_1_0_1306; + wire n_1_0_1307; + wire n_1_0_1308; + wire n_1_0_1309; + + INV_X1_LVT i_0_0_79 (.A(reset), .ZN(n_0_0_16)); + AND2_X1_LVT i_0_0_31 (.A1(n_0_0_16), .A2(WRd[31]), .ZN(registers[31])); + INV_X1_LVT i_0_0_81 (.A(Rd[1]), .ZN(n_0_0_18)); + INV_X1_LVT i_0_0_80 (.A(Rd[0]), .ZN(n_0_0_17)); + NAND3_X1_LVT i_0_0_69 (.A1(n_0_0_18), .A2(n_0_0_17), .A3(Rd[2]), .ZN(n_0_0_9)); + NAND3_X1_LVT i_0_0_41 (.A1(Rd[3]), .A2(WrReg), .A3(Rd[4]), .ZN(n_0_0_1)); + OAI21_X1_LVT i_0_0_35 (.A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_1), .ZN(n_0_28)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[28]_reg (.CK(clk), .E(n_0_28), + .SE(dftIn), .GCK(n_0_58)); + SDFF_X1_LVT \registers_reg[28][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_28__ap[31]), .CK(n_0_58), .Q(registers_28__ap[31]), .QN()); + INV_X1_LVT i_1_0_1370 (.A(Rs1[0]), .ZN(n_1_0_1306)); + NAND3_X1_LVT i_1_0_1354 (.A1(n_1_0_1306), .A2(Rs1[3]), .A3(Rs1[4]), .ZN( + n_1_0_1290)); + INV_X1_LVT i_1_0_1373 (.A(Rs1[2]), .ZN(n_1_0_1309)); + OR2_X1_LVT i_1_0_1348 (.A1(n_1_0_1309), .A2(Rs1[1]), .ZN(n_1_0_1284)); + NOR2_X1_LVT i_1_0_1347 (.A1(n_1_0_1290), .A2(n_1_0_1284), .ZN(n_1_0_1283)); + NOR4_X1_LVT i_1_0_1342 (.A1(n_1_0_1284), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), + .ZN(n_1_0_1278)); + INV_X1_LVT i_0_0_83 (.A(WrReg), .ZN(n_0_0_20)); + OR3_X1_LVT i_0_0_77 (.A1(n_0_0_20), .A2(Rd[4]), .A3(Rd[3]), .ZN(n_0_0_14)); + OAI21_X1_LVT i_0_0_68 (.A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_9), .ZN(n_0_4)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[4]_reg (.CK(clk), .E(n_0_4), + .SE(dftIn), .GCK(n_0_34)); + SDFF_X1_LVT \registers_reg[4][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_4__ap[31]), .CK(n_0_34), .Q(registers_4__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1320 (.A1(registers_28__ap[31]), .A2(n_1_0_1283), .B1( + n_1_0_1278), .B2(registers_4__ap[31]), .ZN(n_1_0_1256)); + NAND2_X1_LVT i_0_0_70 (.A1(n_0_0_18), .A2(n_0_0_17), .ZN(n_0_0_10)); + INV_X1_LVT i_0_0_82 (.A(Rd[4]), .ZN(n_0_0_19)); + OR3_X1_LVT i_0_0_51 (.A1(n_0_0_20), .A2(n_0_0_19), .A3(Rd[3]), .ZN(n_0_0_3)); + OR2_X1_LVT i_0_0_50 (.A1(n_0_0_3), .A2(Rd[2]), .ZN(n_0_0_2)); + OAI21_X1_LVT i_0_0_49 (.A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_2), .ZN(n_0_16)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[16]_reg (.CK(clk), .E(n_0_16), + .SE(dftIn), .GCK(n_0_46)); + SDFF_X1_LVT \registers_reg[16][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_16__ap[31]), .CK(n_0_46), .Q(registers_16__ap[31]), .QN()); + INV_X1_LVT i_1_0_1371 (.A(Rs1[3]), .ZN(n_1_0_1307)); + NAND3_X1_LVT i_1_0_1363 (.A1(n_1_0_1307), .A2(n_1_0_1306), .A3(Rs1[4]), + .ZN(n_1_0_1299)); + OR2_X1_LVT i_1_0_1357 (.A1(Rs1[1]), .A2(Rs1[2]), .ZN(n_1_0_1293)); + NOR2_X1_LVT i_1_0_1331 (.A1(n_1_0_1299), .A2(n_1_0_1293), .ZN(n_1_0_1267)); + NAND2_X1_LVT i_1_0_1365 (.A1(Rs1[1]), .A2(Rs1[2]), .ZN(n_1_0_1301)); + NAND3_X1_LVT i_1_0_1344 (.A1(Rs1[4]), .A2(Rs1[3]), .A3(Rs1[0]), .ZN( + n_1_0_1280)); + NOR2_X1_LVT i_1_0_1330 (.A1(n_1_0_1301), .A2(n_1_0_1280), .ZN(n_1_0_1266)); + NAND3_X1_LVT i_0_0_63 (.A1(Rd[2]), .A2(Rd[1]), .A3(Rd[0]), .ZN(n_0_0_6)); + OAI21_X1_LVT i_0_0_32 (.A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_1), .ZN(n_0_31)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[31]_reg (.CK(clk), .E(n_0_31), + .SE(dftIn), .GCK(n_0_61)); + SDFF_X1_LVT \registers_reg[31][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_31__ap[31]), .CK(n_0_61), .Q(registers_31__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1329 (.A1(registers_16__ap[31]), .A2(n_1_0_1267), .B1( + n_1_0_1266), .B2(registers_31__ap[31]), .ZN(n_1_0_1265)); + NAND3_X1_LVT i_0_0_65 (.A1(n_0_0_17), .A2(Rd[1]), .A3(Rd[2]), .ZN(n_0_0_7)); + OAI21_X1_LVT i_0_0_64 (.A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_7), .ZN(n_0_6)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[6]_reg (.CK(clk), .E(n_0_6), + .SE(dftIn), .GCK(n_0_36)); + SDFF_X1_LVT \registers_reg[6][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_6__ap[31]), .CK(n_0_36), .Q(registers_6__ap[31]), .QN()); + NOR4_X1_LVT i_1_0_1364 (.A1(n_1_0_1301), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), + .ZN(n_1_0_1300)); + INV_X1_LVT i_1_0_1372 (.A(Rs1[4]), .ZN(n_1_0_1308)); + NAND3_X1_LVT i_1_0_1339 (.A1(n_1_0_1308), .A2(n_1_0_1307), .A3(Rs1[0]), + .ZN(n_1_0_1275)); + NOR2_X1_LVT i_1_0_1338 (.A1(n_1_0_1293), .A2(n_1_0_1275), .ZN(n_1_0_1274)); + NAND2_X1_LVT i_0_0_78 (.A1(n_0_0_18), .A2(Rd[0]), .ZN(n_0_0_15)); + OR2_X1_LVT i_0_0_76 (.A1(n_0_0_14), .A2(Rd[2]), .ZN(n_0_0_13)); + OAI21_X1_LVT i_0_0_75 (.A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_13), .ZN(n_0_1)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[1]_reg (.CK(clk), .E(n_0_1), + .SE(dftIn), .GCK(n_0_0)); + SDFF_X1_LVT \registers_reg[1][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_1__ap[31]), .CK(n_0_0), .Q(registers_1__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1319 (.A1(registers_6__ap[31]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[31]), .ZN(n_1_0_1255)); + OAI21_X1_LVT i_0_0_42 (.A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_3), .ZN(n_0_23)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[23]_reg (.CK(clk), .E(n_0_23), + .SE(dftIn), .GCK(n_0_53)); + SDFF_X1_LVT \registers_reg[23][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_23__ap[31]), .CK(n_0_53), .Q(registers_23__ap[31]), .QN()); + NAND3_X1_LVT i_1_0_1360 (.A1(n_1_0_1307), .A2(Rs1[0]), .A3(Rs1[4]), .ZN( + n_1_0_1296)); + NOR2_X1_LVT i_1_0_1328 (.A1(n_1_0_1301), .A2(n_1_0_1296), .ZN(n_1_0_1264)); + NOR2_X1_LVT i_1_0_1327 (.A1(n_1_0_1301), .A2(n_1_0_1275), .ZN(n_1_0_1263)); + OAI21_X1_LVT i_0_0_62 (.A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_6), .ZN(n_0_7)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[7]_reg (.CK(clk), .E(n_0_7), + .SE(dftIn), .GCK(n_0_37)); + SDFF_X1_LVT \registers_reg[7][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_7__ap[31]), .CK(n_0_37), .Q(registers_7__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1326 (.A1(registers_23__ap[31]), .A2(n_1_0_1264), .B1( + n_1_0_1263), .B2(registers_7__ap[31]), .ZN(n_1_0_1262)); + INV_X1_LVT i_1_0_1325 (.A(n_1_0_1262), .ZN(n_1_0_1261)); + NAND2_X1_LVT i_1_0_1362 (.A1(n_1_0_1309), .A2(Rs1[1]), .ZN(n_1_0_1298)); + NOR2_X1_LVT i_1_0_1359 (.A1(n_1_0_1298), .A2(n_1_0_1296), .ZN(n_1_0_1295)); + NAND2_X1_LVT i_0_0_72 (.A1(Rd[1]), .A2(Rd[0]), .ZN(n_0_0_11)); + OAI21_X1_LVT i_0_0_46 (.A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_2), .ZN(n_0_19)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[19]_reg (.CK(clk), .E(n_0_19), + .SE(dftIn), .GCK(n_0_49)); + SDFF_X1_LVT \registers_reg[19][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_19__ap[31]), .CK(n_0_49), .Q(registers_19__ap[31]), .QN()); + NAND3_X1_LVT i_0_0_67 (.A1(n_0_0_18), .A2(Rd[0]), .A3(Rd[2]), .ZN(n_0_0_8)); + OAI21_X1_LVT i_0_0_66 (.A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_8), .ZN(n_0_5)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[5]_reg (.CK(clk), .E(n_0_5), + .SE(dftIn), .GCK(n_0_35)); + SDFF_X1_LVT \registers_reg[5][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_5__ap[31]), .CK(n_0_35), .Q(registers_5__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1337 (.A1(n_1_0_1284), .A2(n_1_0_1275), .ZN(n_1_0_1273)); + AOI221_X1_LVT i_1_0_1318 (.A(n_1_0_1261), .B1(n_1_0_1295), .B2( + registers_19__ap[31]), .C1(registers_5__ap[31]), .C2(n_1_0_1273), .ZN( + n_1_0_1254)); + NAND2_X1_LVT i_0_0_74 (.A1(n_0_0_17), .A2(Rd[1]), .ZN(n_0_0_12)); + NAND3_X1_LVT i_0_0_61 (.A1(n_0_0_19), .A2(WrReg), .A3(Rd[3]), .ZN(n_0_0_5)); + OR2_X1_LVT i_0_0_60 (.A1(n_0_0_5), .A2(Rd[2]), .ZN(n_0_0_4)); + OAI21_X1_LVT i_0_0_57 (.A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_4), .ZN(n_0_10)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[10]_reg (.CK(clk), .E(n_0_10), + .SE(dftIn), .GCK(n_0_40)); + SDFF_X1_LVT \registers_reg[10][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_10__ap[31]), .CK(n_0_40), .Q(registers_10__ap[31]), .QN()); + NAND3_X1_LVT i_1_0_1352 (.A1(n_1_0_1308), .A2(n_1_0_1306), .A3(Rs1[3]), + .ZN(n_1_0_1288)); + NOR2_X1_LVT i_1_0_1351 (.A1(n_1_0_1298), .A2(n_1_0_1288), .ZN(n_1_0_1287)); + NOR2_X1_LVT i_1_0_1349 (.A1(n_1_0_1298), .A2(n_1_0_1290), .ZN(n_1_0_1285)); + OR2_X1_LVT i_0_0_40 (.A1(n_0_0_1), .A2(Rd[2]), .ZN(n_0_0_0)); + OAI21_X1_LVT i_0_0_37 (.A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_0), .ZN(n_0_26)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[26]_reg (.CK(clk), .E(n_0_26), + .SE(dftIn), .GCK(n_0_56)); + SDFF_X1_LVT \registers_reg[26][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_26__ap[31]), .CK(n_0_56), .Q(registers_26__ap[31]), .QN()); + OAI21_X1_LVT i_0_0_59 (.A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_4), .ZN(n_0_8)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[8]_reg (.CK(clk), .E(n_0_8), + .SE(dftIn), .GCK(n_0_38)); + SDFF_X1_LVT \registers_reg[8][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_8__ap[31]), .CK(n_0_38), .Q(registers_8__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1346 (.A1(n_1_0_1293), .A2(n_1_0_1288), .ZN(n_1_0_1282)); + AOI222_X1_LVT i_1_0_1317 (.A1(registers_10__ap[31]), .A2(n_1_0_1287), + .B1(n_1_0_1285), .B2(registers_26__ap[31]), .C1(registers_8__ap[31]), + .C2(n_1_0_1282), .ZN(n_1_0_1253)); + NAND4_X1_LVT i_1_0_1316 (.A1(n_1_0_1265), .A2(n_1_0_1255), .A3(n_1_0_1254), + .A4(n_1_0_1253), .ZN(n_1_0_1252)); + NAND3_X1_LVT i_1_0_1356 (.A1(n_1_0_1308), .A2(Rs1[3]), .A3(Rs1[0]), .ZN( + n_1_0_1292)); + NOR2_X1_LVT i_1_0_1355 (.A1(n_1_0_1293), .A2(n_1_0_1292), .ZN(n_1_0_1291)); + OAI21_X1_LVT i_0_0_58 (.A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_4), .ZN(n_0_9)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[9]_reg (.CK(clk), .E(n_0_9), + .SE(dftIn), .GCK(n_0_39)); + SDFF_X1_LVT \registers_reg[9][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_9__ap[31]), .CK(n_0_39), .Q(registers_9__ap[31]), .QN()); + OAI21_X1_LVT i_0_0_34 (.A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_1), .ZN(n_0_29)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[29]_reg (.CK(clk), .E(n_0_29), + .SE(dftIn), .GCK(n_0_59)); + SDFF_X1_LVT \registers_reg[29][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_29__ap[31]), .CK(n_0_59), .Q(registers_29__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1340 (.A1(n_1_0_1284), .A2(n_1_0_1280), .ZN(n_1_0_1276)); + AOI221_X1_LVT i_1_0_1315 (.A(n_1_0_1252), .B1(n_1_0_1291), .B2( + registers_9__ap[31]), .C1(registers_29__ap[31]), .C2(n_1_0_1276), .ZN( + n_1_0_1251)); + OAI21_X1_LVT i_0_0_47 (.A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_2), .ZN(n_0_18)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[18]_reg (.CK(clk), .E(n_0_18), + .SE(dftIn), .GCK(n_0_48)); + SDFF_X1_LVT \registers_reg[18][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_18__ap[31]), .CK(n_0_48), .Q(registers_18__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1361 (.A1(n_1_0_1299), .A2(n_1_0_1298), .ZN(n_1_0_1297)); + NOR2_X1_LVT i_1_0_1336 (.A1(n_1_0_1301), .A2(n_1_0_1290), .ZN(n_1_0_1272)); + OAI21_X1_LVT i_0_0_33 (.A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_1), .ZN(n_0_30)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[30]_reg (.CK(clk), .E(n_0_30), + .SE(dftIn), .GCK(n_0_60)); + SDFF_X1_LVT \registers_reg[30][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_30__ap[31]), .CK(n_0_60), .Q(registers_30__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1314 (.A1(registers_18__ap[31]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[31]), .ZN(n_1_0_1250)); + OAI21_X1_LVT i_0_0_39 (.A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_0), .ZN(n_0_24)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[24]_reg (.CK(clk), .E(n_0_24), + .SE(dftIn), .GCK(n_0_54)); + SDFF_X1_LVT \registers_reg[24][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_24__ap[31]), .CK(n_0_54), .Q(registers_24__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1353 (.A1(n_1_0_1293), .A2(n_1_0_1290), .ZN(n_1_0_1289)); + NOR2_X1_LVT i_1_0_1324 (.A1(n_1_0_1288), .A2(n_1_0_1284), .ZN(n_1_0_1260)); + OAI21_X1_LVT i_0_0_55 (.A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_5), .ZN(n_0_12)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[12]_reg (.CK(clk), .E(n_0_12), + .SE(dftIn), .GCK(n_0_42)); + SDFF_X1_LVT \registers_reg[12][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_12__ap[31]), .CK(n_0_42), .Q(registers_12__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1313 (.A1(registers_24__ap[31]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[31]), .ZN(n_1_0_1249)); + OAI21_X1_LVT i_0_0_43 (.A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_3), .ZN(n_0_22)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[22]_reg (.CK(clk), .E(n_0_22), + .SE(dftIn), .GCK(n_0_52)); + SDFF_X1_LVT \registers_reg[22][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_22__ap[31]), .CK(n_0_52), .Q(registers_22__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1358 (.A1(n_1_0_1301), .A2(n_1_0_1299), .ZN(n_1_0_1294)); + NOR2_X1_LVT i_1_0_1323 (.A1(n_1_0_1296), .A2(n_1_0_1284), .ZN(n_1_0_1259)); + OAI21_X1_LVT i_0_0_44 (.A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_3), .ZN(n_0_21)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[21]_reg (.CK(clk), .E(n_0_21), + .SE(dftIn), .GCK(n_0_51)); + SDFF_X1_LVT \registers_reg[21][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_21__ap[31]), .CK(n_0_51), .Q(registers_21__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1312 (.A1(registers_22__ap[31]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[31]), .ZN(n_1_0_1248)); + NAND3_X1_LVT i_1_0_1311 (.A1(n_1_0_1250), .A2(n_1_0_1249), .A3(n_1_0_1248), + .ZN(n_1_0_1247)); + NOR2_X1_LVT i_1_0_1335 (.A1(n_1_0_1296), .A2(n_1_0_1293), .ZN(n_1_0_1271)); + OAI21_X1_LVT i_0_0_48 (.A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_2), .ZN(n_0_17)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[17]_reg (.CK(clk), .E(n_0_17), + .SE(dftIn), .GCK(n_0_47)); + SDFF_X1_LVT \registers_reg[17][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_17__ap[31]), .CK(n_0_47), .Q(registers_17__ap[31]), .QN()); + OAI21_X1_LVT i_0_0_45 (.A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_3), .ZN(n_0_20)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[20]_reg (.CK(clk), .E(n_0_20), + .SE(dftIn), .GCK(n_0_50)); + SDFF_X1_LVT \registers_reg[20][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_20__ap[31]), .CK(n_0_50), .Q(registers_20__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1345 (.A1(n_1_0_1299), .A2(n_1_0_1284), .ZN(n_1_0_1281)); + AOI221_X1_LVT i_1_0_1310 (.A(n_1_0_1247), .B1(n_1_0_1271), .B2( + registers_17__ap[31]), .C1(registers_20__ap[31]), .C2(n_1_0_1281), + .ZN(n_1_0_1246)); + OAI21_X1_LVT i_0_0_36 (.A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_0), .ZN(n_0_27)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[27]_reg (.CK(clk), .E(n_0_27), + .SE(dftIn), .GCK(n_0_57)); + SDFF_X1_LVT \registers_reg[27][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_27__ap[31]), .CK(n_0_57), .Q(registers_27__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1343 (.A1(n_1_0_1298), .A2(n_1_0_1280), .ZN(n_1_0_1279)); + NOR2_X1_LVT i_1_0_1334 (.A1(n_1_0_1298), .A2(n_1_0_1292), .ZN(n_1_0_1270)); + OAI21_X1_LVT i_0_0_56 (.A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_4), .ZN(n_0_11)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[11]_reg (.CK(clk), .E(n_0_11), + .SE(dftIn), .GCK(n_0_41)); + SDFF_X1_LVT \registers_reg[11][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_11__ap[31]), .CK(n_0_41), .Q(registers_11__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1309 (.A1(registers_27__ap[31]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[31]), .ZN(n_1_0_1245)); + OAI21_X1_LVT i_0_0_54 (.A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_5), .ZN(n_0_13)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[13]_reg (.CK(clk), .E(n_0_13), + .SE(dftIn), .GCK(n_0_43)); + SDFF_X1_LVT \registers_reg[13][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_13__ap[31]), .CK(n_0_43), .Q(registers_13__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1341 (.A1(n_1_0_1292), .A2(n_1_0_1284), .ZN(n_1_0_1277)); + NOR2_X1_LVT i_1_0_1333 (.A1(n_1_0_1293), .A2(n_1_0_1280), .ZN(n_1_0_1269)); + OAI21_X1_LVT i_0_0_38 (.A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_0), .ZN(n_0_25)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[25]_reg (.CK(clk), .E(n_0_25), + .SE(dftIn), .GCK(n_0_55)); + SDFF_X1_LVT \registers_reg[25][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_25__ap[31]), .CK(n_0_55), .Q(registers_25__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1308 (.A1(registers_13__ap[31]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[31]), .ZN(n_1_0_1244)); + OAI21_X1_LVT i_0_0_52 (.A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_5), .ZN(n_0_15)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[15]_reg (.CK(clk), .E(n_0_15), + .SE(dftIn), .GCK(n_0_45)); + SDFF_X1_LVT \registers_reg[15][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_15__ap[31]), .CK(n_0_45), .Q(registers_15__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1350 (.A1(n_1_0_1301), .A2(n_1_0_1292), .ZN(n_1_0_1286)); + NOR2_X1_LVT i_1_0_1322 (.A1(n_1_0_1301), .A2(n_1_0_1288), .ZN(n_1_0_1258)); + OAI21_X1_LVT i_0_0_53 (.A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_5), .ZN(n_0_14)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[14]_reg (.CK(clk), .E(n_0_14), + .SE(dftIn), .GCK(n_0_44)); + SDFF_X1_LVT \registers_reg[14][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_14__ap[31]), .CK(n_0_44), .Q(registers_14__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1307 (.A1(registers_15__ap[31]), .A2(n_1_0_1286), .B1( + n_1_0_1258), .B2(registers_14__ap[31]), .ZN(n_1_0_1243)); + NAND3_X1_LVT i_1_0_1306 (.A1(n_1_0_1245), .A2(n_1_0_1244), .A3(n_1_0_1243), + .ZN(n_1_0_1242)); + NOR2_X1_LVT i_1_0_1321 (.A1(n_1_0_1298), .A2(n_1_0_1275), .ZN(n_1_0_1257)); + OAI21_X1_LVT i_0_0_71 (.A(n_0_0_16), .B1(n_0_0_13), .B2(n_0_0_11), .ZN(n_0_3)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[3]_reg (.CK(clk), .E(n_0_3), + .SE(dftIn), .GCK(n_0_33)); + SDFF_X1_LVT \registers_reg[3][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_3__ap[31]), .CK(n_0_33), .Q(registers_3__ap[31]), .QN()); + OAI21_X1_LVT i_0_0_73 (.A(n_0_0_16), .B1(n_0_0_13), .B2(n_0_0_12), .ZN(n_0_2)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[2]_reg (.CK(clk), .E(n_0_2), + .SE(dftIn), .GCK(n_0_32)); + SDFF_X1_LVT \registers_reg[2][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_2__ap[31]), .CK(n_0_32), .Q(registers_2__ap[31]), .QN()); + NOR4_X1_LVT i_1_0_1332 (.A1(n_1_0_1298), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), + .ZN(n_1_0_1268)); + AOI221_X1_LVT i_1_0_1305 (.A(n_1_0_1242), .B1(n_1_0_1257), .B2( + registers_3__ap[31]), .C1(registers_2__ap[31]), .C2(n_1_0_1268), .ZN( + n_1_0_1241)); + NAND4_X1_LVT i_1_0_1304 (.A1(n_1_0_1256), .A2(n_1_0_1251), .A3(n_1_0_1246), + .A4(n_1_0_1241), .ZN(RRs1[31])); + AND2_X1_LVT i_0_0_30 (.A1(n_0_0_16), .A2(WRd[30]), .ZN(registers[30])); + SDFF_X1_LVT \registers_reg[28][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_28__ap[30]), .CK(n_0_58), .Q(registers_28__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[17][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_17__ap[30]), .CK(n_0_47), .Q(registers_17__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1300 (.A1(registers_28__ap[30]), .A2(n_1_0_1283), .B1( + n_1_0_1271), .B2(registers_17__ap[30]), .ZN(n_1_0_1237)); + SDFF_X1_LVT \registers_reg[16][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_16__ap[30]), .CK(n_0_46), .Q(registers_16__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[31][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_31__ap[30]), .CK(n_0_61), .Q(registers_31__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1303 (.A1(registers_16__ap[30]), .A2(n_1_0_1267), .B1( + n_1_0_1266), .B2(registers_31__ap[30]), .ZN(n_1_0_1240)); + SDFF_X1_LVT \registers_reg[6][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_6__ap[30]), .CK(n_0_36), .Q(registers_6__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[1][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_1__ap[30]), .CK(n_0_0), .Q(registers_1__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1299 (.A1(registers_6__ap[30]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[30]), .ZN(n_1_0_1236)); + SDFF_X1_LVT \registers_reg[23][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_23__ap[30]), .CK(n_0_53), .Q(registers_23__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[7][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_7__ap[30]), .CK(n_0_37), .Q(registers_7__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1302 (.A1(registers_23__ap[30]), .A2(n_1_0_1264), .B1( + n_1_0_1263), .B2(registers_7__ap[30]), .ZN(n_1_0_1239)); + INV_X1_LVT i_1_0_1301 (.A(n_1_0_1239), .ZN(n_1_0_1238)); + SDFF_X1_LVT \registers_reg[19][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_19__ap[30]), .CK(n_0_49), .Q(registers_19__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[5][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_5__ap[30]), .CK(n_0_35), .Q(registers_5__ap[30]), .QN()); + AOI221_X1_LVT i_1_0_1298 (.A(n_1_0_1238), .B1(n_1_0_1295), .B2( + registers_19__ap[30]), .C1(registers_5__ap[30]), .C2(n_1_0_1273), .ZN( + n_1_0_1235)); + SDFF_X1_LVT \registers_reg[10][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_10__ap[30]), .CK(n_0_40), .Q(registers_10__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[26][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_26__ap[30]), .CK(n_0_56), .Q(registers_26__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[8][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_8__ap[30]), .CK(n_0_38), .Q(registers_8__ap[30]), .QN()); + AOI222_X1_LVT i_1_0_1297 (.A1(registers_10__ap[30]), .A2(n_1_0_1287), + .B1(n_1_0_1285), .B2(registers_26__ap[30]), .C1(registers_8__ap[30]), + .C2(n_1_0_1282), .ZN(n_1_0_1234)); + NAND4_X1_LVT i_1_0_1296 (.A1(n_1_0_1240), .A2(n_1_0_1236), .A3(n_1_0_1235), + .A4(n_1_0_1234), .ZN(n_1_0_1233)); + SDFF_X1_LVT \registers_reg[9][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_9__ap[30]), .CK(n_0_39), .Q(registers_9__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[29][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_29__ap[30]), .CK(n_0_59), .Q(registers_29__ap[30]), .QN()); + AOI221_X1_LVT i_1_0_1295 (.A(n_1_0_1233), .B1(n_1_0_1291), .B2( + registers_9__ap[30]), .C1(registers_29__ap[30]), .C2(n_1_0_1276), .ZN( + n_1_0_1232)); + SDFF_X1_LVT \registers_reg[18][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_18__ap[30]), .CK(n_0_48), .Q(registers_18__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[30][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_30__ap[30]), .CK(n_0_60), .Q(registers_30__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1294 (.A1(registers_18__ap[30]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[30]), .ZN(n_1_0_1231)); + SDFF_X1_LVT \registers_reg[20][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_20__ap[30]), .CK(n_0_50), .Q(registers_20__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[4][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_4__ap[30]), .CK(n_0_34), .Q(registers_4__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1293 (.A1(registers_20__ap[30]), .A2(n_1_0_1281), .B1( + n_1_0_1278), .B2(registers_4__ap[30]), .ZN(n_1_0_1230)); + SDFF_X1_LVT \registers_reg[22][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_22__ap[30]), .CK(n_0_52), .Q(registers_22__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[21][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_21__ap[30]), .CK(n_0_51), .Q(registers_21__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1292 (.A1(registers_22__ap[30]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[30]), .ZN(n_1_0_1229)); + NAND3_X1_LVT i_1_0_1291 (.A1(n_1_0_1231), .A2(n_1_0_1230), .A3(n_1_0_1229), + .ZN(n_1_0_1228)); + SDFF_X1_LVT \registers_reg[24][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_24__ap[30]), .CK(n_0_54), .Q(registers_24__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[12][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_12__ap[30]), .CK(n_0_42), .Q(registers_12__ap[30]), .QN()); + AOI221_X1_LVT i_1_0_1290 (.A(n_1_0_1228), .B1(n_1_0_1289), .B2( + registers_24__ap[30]), .C1(registers_12__ap[30]), .C2(n_1_0_1260), + .ZN(n_1_0_1227)); + SDFF_X1_LVT \registers_reg[27][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_27__ap[30]), .CK(n_0_57), .Q(registers_27__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[11][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_11__ap[30]), .CK(n_0_41), .Q(registers_11__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1289 (.A1(registers_27__ap[30]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[30]), .ZN(n_1_0_1226)); + SDFF_X1_LVT \registers_reg[13][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_13__ap[30]), .CK(n_0_43), .Q(registers_13__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[25][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_25__ap[30]), .CK(n_0_55), .Q(registers_25__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1288 (.A1(registers_13__ap[30]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[30]), .ZN(n_1_0_1225)); + SDFF_X1_LVT \registers_reg[15][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_15__ap[30]), .CK(n_0_45), .Q(registers_15__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[14][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_14__ap[30]), .CK(n_0_44), .Q(registers_14__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1287 (.A1(registers_15__ap[30]), .A2(n_1_0_1286), .B1( + n_1_0_1258), .B2(registers_14__ap[30]), .ZN(n_1_0_1224)); + NAND3_X1_LVT i_1_0_1286 (.A1(n_1_0_1226), .A2(n_1_0_1225), .A3(n_1_0_1224), + .ZN(n_1_0_1223)); + SDFF_X1_LVT \registers_reg[3][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_3__ap[30]), .CK(n_0_33), .Q(registers_3__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[2][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_2__ap[30]), .CK(n_0_32), .Q(registers_2__ap[30]), .QN()); + AOI221_X1_LVT i_1_0_1285 (.A(n_1_0_1223), .B1(n_1_0_1257), .B2( + registers_3__ap[30]), .C1(registers_2__ap[30]), .C2(n_1_0_1268), .ZN( + n_1_0_1222)); + NAND4_X1_LVT i_1_0_1284 (.A1(n_1_0_1237), .A2(n_1_0_1232), .A3(n_1_0_1227), + .A4(n_1_0_1222), .ZN(RRs1[30])); + AND2_X1_LVT i_0_0_29 (.A1(n_0_0_16), .A2(WRd[29]), .ZN(registers[29])); + SDFF_X1_LVT \registers_reg[28][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_28__ap[29]), .CK(n_0_58), .Q(registers_28__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[8][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_8__ap[29]), .CK(n_0_38), .Q(registers_8__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1282 (.A1(registers_28__ap[29]), .A2(n_1_0_1283), .B1( + n_1_0_1282), .B2(registers_8__ap[29]), .ZN(n_1_0_1220)); + SDFF_X1_LVT \registers_reg[31][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_31__ap[29]), .CK(n_0_61), .Q(registers_31__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[7][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_7__ap[29]), .CK(n_0_37), .Q(registers_7__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1283 (.A1(registers_31__ap[29]), .A2(n_1_0_1266), .B1( + n_1_0_1263), .B2(registers_7__ap[29]), .ZN(n_1_0_1221)); + SDFF_X1_LVT \registers_reg[24][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_24__ap[29]), .CK(n_0_54), .Q(registers_24__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[20][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_20__ap[29]), .CK(n_0_50), .Q(registers_20__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1281 (.A1(registers_24__ap[29]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[29]), .ZN(n_1_0_1219)); + SDFF_X1_LVT \registers_reg[19][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_19__ap[29]), .CK(n_0_49), .Q(registers_19__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[4][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_4__ap[29]), .CK(n_0_34), .Q(registers_4__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1280 (.A1(registers_19__ap[29]), .A2(n_1_0_1295), .B1( + n_1_0_1278), .B2(registers_4__ap[29]), .ZN(n_1_0_1218)); + NAND3_X1_LVT i_1_0_1279 (.A1(n_1_0_1221), .A2(n_1_0_1219), .A3(n_1_0_1218), + .ZN(n_1_0_1217)); + SDFF_X1_LVT \registers_reg[23][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_23__ap[29]), .CK(n_0_53), .Q(registers_23__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[29][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_29__ap[29]), .CK(n_0_59), .Q(registers_29__ap[29]), .QN()); + AOI221_X1_LVT i_1_0_1278 (.A(n_1_0_1217), .B1(n_1_0_1264), .B2( + registers_23__ap[29]), .C1(registers_29__ap[29]), .C2(n_1_0_1276), + .ZN(n_1_0_1216)); + SDFF_X1_LVT \registers_reg[10][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_10__ap[29]), .CK(n_0_40), .Q(registers_10__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[26][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_26__ap[29]), .CK(n_0_56), .Q(registers_26__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[25][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_25__ap[29]), .CK(n_0_55), .Q(registers_25__ap[29]), .QN()); + AOI222_X1_LVT i_1_0_1277 (.A1(registers_10__ap[29]), .A2(n_1_0_1287), + .B1(n_1_0_1285), .B2(registers_26__ap[29]), .C1(registers_25__ap[29]), + .C2(n_1_0_1269), .ZN(n_1_0_1215)); + NAND3_X1_LVT i_1_0_1276 (.A1(n_1_0_1220), .A2(n_1_0_1216), .A3(n_1_0_1215), + .ZN(n_1_0_1214)); + SDFF_X1_LVT \registers_reg[21][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_21__ap[29]), .CK(n_0_51), .Q(registers_21__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[13][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_13__ap[29]), .CK(n_0_43), .Q(registers_13__ap[29]), .QN()); + AOI221_X1_LVT i_1_0_1275 (.A(n_1_0_1214), .B1(n_1_0_1259), .B2( + registers_21__ap[29]), .C1(registers_13__ap[29]), .C2(n_1_0_1277), + .ZN(n_1_0_1213)); + SDFF_X1_LVT \registers_reg[18][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_18__ap[29]), .CK(n_0_48), .Q(registers_18__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[30][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_30__ap[29]), .CK(n_0_60), .Q(registers_30__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1274 (.A1(registers_18__ap[29]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[29]), .ZN(n_1_0_1212)); + SDFF_X1_LVT \registers_reg[17][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_17__ap[29]), .CK(n_0_47), .Q(registers_17__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[12][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_12__ap[29]), .CK(n_0_42), .Q(registers_12__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1273 (.A1(registers_17__ap[29]), .A2(n_1_0_1271), .B1( + n_1_0_1260), .B2(registers_12__ap[29]), .ZN(n_1_0_1211)); + SDFF_X1_LVT \registers_reg[15][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_15__ap[29]), .CK(n_0_45), .Q(registers_15__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[16][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_16__ap[29]), .CK(n_0_46), .Q(registers_16__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1272 (.A1(registers_15__ap[29]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[29]), .ZN(n_1_0_1210)); + NAND3_X1_LVT i_1_0_1271 (.A1(n_1_0_1212), .A2(n_1_0_1211), .A3(n_1_0_1210), + .ZN(n_1_0_1209)); + SDFF_X1_LVT \registers_reg[22][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_22__ap[29]), .CK(n_0_52), .Q(registers_22__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[5][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_5__ap[29]), .CK(n_0_35), .Q(registers_5__ap[29]), .QN()); + AOI221_X1_LVT i_1_0_1270 (.A(n_1_0_1209), .B1(n_1_0_1294), .B2( + registers_22__ap[29]), .C1(registers_5__ap[29]), .C2(n_1_0_1273), .ZN( + n_1_0_1208)); + SDFF_X1_LVT \registers_reg[9][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_9__ap[29]), .CK(n_0_39), .Q(registers_9__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[1][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_1__ap[29]), .CK(n_0_0), .Q(registers_1__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1269 (.A1(registers_9__ap[29]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[29]), .ZN(n_1_0_1207)); + SDFF_X1_LVT \registers_reg[6][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_6__ap[29]), .CK(n_0_36), .Q(registers_6__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[14][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_14__ap[29]), .CK(n_0_44), .Q(registers_14__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1268 (.A1(registers_6__ap[29]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[29]), .ZN(n_1_0_1206)); + SDFF_X1_LVT \registers_reg[27][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_27__ap[29]), .CK(n_0_57), .Q(registers_27__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[11][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_11__ap[29]), .CK(n_0_41), .Q(registers_11__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1267 (.A1(registers_27__ap[29]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[29]), .ZN(n_1_0_1205)); + NAND3_X1_LVT i_1_0_1266 (.A1(n_1_0_1207), .A2(n_1_0_1206), .A3(n_1_0_1205), + .ZN(n_1_0_1204)); + SDFF_X1_LVT \registers_reg[3][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_3__ap[29]), .CK(n_0_33), .Q(registers_3__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[2][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_2__ap[29]), .CK(n_0_32), .Q(registers_2__ap[29]), .QN()); + AOI221_X1_LVT i_1_0_1265 (.A(n_1_0_1204), .B1(n_1_0_1257), .B2( + registers_3__ap[29]), .C1(registers_2__ap[29]), .C2(n_1_0_1268), .ZN( + n_1_0_1203)); + NAND3_X1_LVT i_1_0_1264 (.A1(n_1_0_1213), .A2(n_1_0_1208), .A3(n_1_0_1203), + .ZN(RRs1[29])); + AND2_X1_LVT i_0_0_28 (.A1(n_0_0_16), .A2(WRd[28]), .ZN(registers[28])); + SDFF_X1_LVT \registers_reg[15][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_15__ap[28]), .CK(n_0_45), .Q(registers_15__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[26][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_26__ap[28]), .CK(n_0_56), .Q(registers_26__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[22][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_22__ap[28]), .CK(n_0_52), .Q(registers_22__ap[28]), .QN()); + AOI222_X1_LVT i_1_0_1263 (.A1(registers_15__ap[28]), .A2(n_1_0_1286), + .B1(n_1_0_1285), .B2(registers_26__ap[28]), .C1(registers_22__ap[28]), + .C2(n_1_0_1294), .ZN(n_1_0_1202)); + SDFF_X1_LVT \registers_reg[5][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_5__ap[28]), .CK(n_0_35), .Q(registers_5__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[12][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_12__ap[28]), .CK(n_0_42), .Q(registers_12__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1262 (.A1(registers_5__ap[28]), .A2(n_1_0_1273), .B1( + n_1_0_1260), .B2(registers_12__ap[28]), .ZN(n_1_0_1201)); + SDFF_X1_LVT \registers_reg[28][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_28__ap[28]), .CK(n_0_58), .Q(registers_28__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[14][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_14__ap[28]), .CK(n_0_44), .Q(registers_14__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1261 (.A1(registers_28__ap[28]), .A2(n_1_0_1283), .B1( + n_1_0_1258), .B2(registers_14__ap[28]), .ZN(n_1_0_1200)); + SDFF_X1_LVT \registers_reg[17][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_17__ap[28]), .CK(n_0_47), .Q(registers_17__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[2][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_2__ap[28]), .CK(n_0_32), .Q(registers_2__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1260 (.A1(registers_17__ap[28]), .A2(n_1_0_1271), .B1( + n_1_0_1268), .B2(registers_2__ap[28]), .ZN(n_1_0_1199)); + NAND3_X1_LVT i_1_0_1259 (.A1(n_1_0_1201), .A2(n_1_0_1200), .A3(n_1_0_1199), + .ZN(n_1_0_1198)); + SDFF_X1_LVT \registers_reg[9][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_9__ap[28]), .CK(n_0_39), .Q(registers_9__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[29][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_29__ap[28]), .CK(n_0_59), .Q(registers_29__ap[28]), .QN()); + AOI221_X1_LVT i_1_0_1258 (.A(n_1_0_1198), .B1(n_1_0_1291), .B2( + registers_9__ap[28]), .C1(registers_29__ap[28]), .C2(n_1_0_1276), .ZN( + n_1_0_1197)); + SDFF_X1_LVT \registers_reg[13][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_13__ap[28]), .CK(n_0_43), .Q(registers_13__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[25][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_25__ap[28]), .CK(n_0_55), .Q(registers_25__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1257 (.A1(registers_13__ap[28]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[28]), .ZN(n_1_0_1196)); + NAND3_X1_LVT i_1_0_1256 (.A1(n_1_0_1202), .A2(n_1_0_1197), .A3(n_1_0_1196), + .ZN(n_1_0_1195)); + SDFF_X1_LVT \registers_reg[4][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_4__ap[28]), .CK(n_0_34), .Q(registers_4__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[20][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_20__ap[28]), .CK(n_0_50), .Q(registers_20__ap[28]), .QN()); + AOI221_X1_LVT i_1_0_1255 (.A(n_1_0_1195), .B1(n_1_0_1278), .B2( + registers_4__ap[28]), .C1(registers_20__ap[28]), .C2(n_1_0_1281), .ZN( + n_1_0_1194)); + SDFF_X1_LVT \registers_reg[1][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_1__ap[28]), .CK(n_0_0), .Q(registers_1__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[23][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_23__ap[28]), .CK(n_0_53), .Q(registers_23__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1254 (.A1(registers_1__ap[28]), .A2(n_1_0_1274), .B1( + n_1_0_1264), .B2(registers_23__ap[28]), .ZN(n_1_0_1193)); + SDFF_X1_LVT \registers_reg[10][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_10__ap[28]), .CK(n_0_40), .Q(registers_10__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[21][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_21__ap[28]), .CK(n_0_51), .Q(registers_21__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1253 (.A1(registers_10__ap[28]), .A2(n_1_0_1287), .B1( + n_1_0_1259), .B2(registers_21__ap[28]), .ZN(n_1_0_1192)); + SDFF_X1_LVT \registers_reg[6][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_6__ap[28]), .CK(n_0_36), .Q(registers_6__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[30][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_30__ap[28]), .CK(n_0_60), .Q(registers_30__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1252 (.A1(registers_6__ap[28]), .A2(n_1_0_1300), .B1( + n_1_0_1272), .B2(registers_30__ap[28]), .ZN(n_1_0_1191)); + NAND3_X1_LVT i_1_0_1251 (.A1(n_1_0_1193), .A2(n_1_0_1192), .A3(n_1_0_1191), + .ZN(n_1_0_1190)); + SDFF_X1_LVT \registers_reg[8][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_8__ap[28]), .CK(n_0_38), .Q(registers_8__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[24][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_24__ap[28]), .CK(n_0_54), .Q(registers_24__ap[28]), .QN()); + AOI221_X1_LVT i_1_0_1250 (.A(n_1_0_1190), .B1(n_1_0_1282), .B2( + registers_8__ap[28]), .C1(registers_24__ap[28]), .C2(n_1_0_1289), .ZN( + n_1_0_1189)); + SDFF_X1_LVT \registers_reg[16][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_16__ap[28]), .CK(n_0_46), .Q(registers_16__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[3][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_3__ap[28]), .CK(n_0_33), .Q(registers_3__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1249 (.A1(registers_16__ap[28]), .A2(n_1_0_1267), .B1( + n_1_0_1257), .B2(registers_3__ap[28]), .ZN(n_1_0_1188)); + SDFF_X1_LVT \registers_reg[11][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_11__ap[28]), .CK(n_0_41), .Q(registers_11__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[31][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_31__ap[28]), .CK(n_0_61), .Q(registers_31__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1248 (.A1(registers_11__ap[28]), .A2(n_1_0_1270), .B1( + n_1_0_1266), .B2(registers_31__ap[28]), .ZN(n_1_0_1187)); + SDFF_X1_LVT \registers_reg[27][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_27__ap[28]), .CK(n_0_57), .Q(registers_27__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[7][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_7__ap[28]), .CK(n_0_37), .Q(registers_7__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1247 (.A1(registers_27__ap[28]), .A2(n_1_0_1279), .B1( + n_1_0_1263), .B2(registers_7__ap[28]), .ZN(n_1_0_1186)); + NAND3_X1_LVT i_1_0_1246 (.A1(n_1_0_1188), .A2(n_1_0_1187), .A3(n_1_0_1186), + .ZN(n_1_0_1185)); + SDFF_X1_LVT \registers_reg[19][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_19__ap[28]), .CK(n_0_49), .Q(registers_19__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[18][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_18__ap[28]), .CK(n_0_48), .Q(registers_18__ap[28]), .QN()); + AOI221_X1_LVT i_1_0_1245 (.A(n_1_0_1185), .B1(n_1_0_1295), .B2( + registers_19__ap[28]), .C1(registers_18__ap[28]), .C2(n_1_0_1297), + .ZN(n_1_0_1184)); + NAND3_X1_LVT i_1_0_1244 (.A1(n_1_0_1194), .A2(n_1_0_1189), .A3(n_1_0_1184), + .ZN(RRs1[28])); + AND2_X1_LVT i_0_0_27 (.A1(n_0_0_16), .A2(WRd[27]), .ZN(registers[27])); + SDFF_X1_LVT \registers_reg[29][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_29__ap[27]), .CK(n_0_59), .Q(registers_29__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[2][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_2__ap[27]), .CK(n_0_32), .Q(registers_2__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1242 (.A1(registers_29__ap[27]), .A2(n_1_0_1276), .B1( + n_1_0_1268), .B2(registers_2__ap[27]), .ZN(n_1_0_1182)); + SDFF_X1_LVT \registers_reg[8][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_8__ap[27]), .CK(n_0_38), .Q(registers_8__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[25][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_25__ap[27]), .CK(n_0_55), .Q(registers_25__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1243 (.A1(registers_8__ap[27]), .A2(n_1_0_1282), .B1( + n_1_0_1269), .B2(registers_25__ap[27]), .ZN(n_1_0_1183)); + SDFF_X1_LVT \registers_reg[9][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_9__ap[27]), .CK(n_0_39), .Q(registers_9__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[7][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_7__ap[27]), .CK(n_0_37), .Q(registers_7__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1241 (.A1(registers_9__ap[27]), .A2(n_1_0_1291), .B1( + n_1_0_1263), .B2(registers_7__ap[27]), .ZN(n_1_0_1181)); + SDFF_X1_LVT \registers_reg[11][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_11__ap[27]), .CK(n_0_41), .Q(registers_11__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[16][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_16__ap[27]), .CK(n_0_46), .Q(registers_16__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1240 (.A1(registers_11__ap[27]), .A2(n_1_0_1270), .B1( + n_1_0_1267), .B2(registers_16__ap[27]), .ZN(n_1_0_1180)); + NAND3_X1_LVT i_1_0_1239 (.A1(n_1_0_1183), .A2(n_1_0_1181), .A3(n_1_0_1180), + .ZN(n_1_0_1179)); + SDFF_X1_LVT \registers_reg[10][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_10__ap[27]), .CK(n_0_40), .Q(registers_10__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[6][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_6__ap[27]), .CK(n_0_36), .Q(registers_6__ap[27]), .QN()); + AOI221_X1_LVT i_1_0_1238 (.A(n_1_0_1179), .B1(n_1_0_1287), .B2( + registers_10__ap[27]), .C1(registers_6__ap[27]), .C2(n_1_0_1300), .ZN( + n_1_0_1178)); + SDFF_X1_LVT \registers_reg[1][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_1__ap[27]), .CK(n_0_0), .Q(registers_1__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[30][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_30__ap[27]), .CK(n_0_60), .Q(registers_30__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[22][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_22__ap[27]), .CK(n_0_52), .Q(registers_22__ap[27]), .QN()); + AOI222_X1_LVT i_1_0_1237 (.A1(registers_1__ap[27]), .A2(n_1_0_1274), .B1( + n_1_0_1272), .B2(registers_30__ap[27]), .C1(registers_22__ap[27]), + .C2(n_1_0_1294), .ZN(n_1_0_1177)); + NAND3_X1_LVT i_1_0_1236 (.A1(n_1_0_1182), .A2(n_1_0_1178), .A3(n_1_0_1177), + .ZN(n_1_0_1176)); + SDFF_X1_LVT \registers_reg[5][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_5__ap[27]), .CK(n_0_35), .Q(registers_5__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[28][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_28__ap[27]), .CK(n_0_58), .Q(registers_28__ap[27]), .QN()); + AOI221_X1_LVT i_1_0_1235 (.A(n_1_0_1176), .B1(n_1_0_1273), .B2( + registers_5__ap[27]), .C1(registers_28__ap[27]), .C2(n_1_0_1283), .ZN( + n_1_0_1175)); + SDFF_X1_LVT \registers_reg[4][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_4__ap[27]), .CK(n_0_34), .Q(registers_4__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[12][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_12__ap[27]), .CK(n_0_42), .Q(registers_12__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1234 (.A1(registers_4__ap[27]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[27]), .ZN(n_1_0_1174)); + SDFF_X1_LVT \registers_reg[19][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_19__ap[27]), .CK(n_0_49), .Q(registers_19__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[21][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_21__ap[27]), .CK(n_0_51), .Q(registers_21__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1233 (.A1(registers_19__ap[27]), .A2(n_1_0_1295), .B1( + n_1_0_1259), .B2(registers_21__ap[27]), .ZN(n_1_0_1173)); + SDFF_X1_LVT \registers_reg[24][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_24__ap[27]), .CK(n_0_54), .Q(registers_24__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[20][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_20__ap[27]), .CK(n_0_50), .Q(registers_20__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1232 (.A1(registers_24__ap[27]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[27]), .ZN(n_1_0_1172)); + NAND3_X1_LVT i_1_0_1231 (.A1(n_1_0_1174), .A2(n_1_0_1173), .A3(n_1_0_1172), + .ZN(n_1_0_1171)); + SDFF_X1_LVT \registers_reg[18][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_18__ap[27]), .CK(n_0_48), .Q(registers_18__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[26][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_26__ap[27]), .CK(n_0_56), .Q(registers_26__ap[27]), .QN()); + AOI221_X1_LVT i_1_0_1230 (.A(n_1_0_1171), .B1(n_1_0_1297), .B2( + registers_18__ap[27]), .C1(registers_26__ap[27]), .C2(n_1_0_1285), + .ZN(n_1_0_1170)); + SDFF_X1_LVT \registers_reg[23][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_23__ap[27]), .CK(n_0_53), .Q(registers_23__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[3][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_3__ap[27]), .CK(n_0_33), .Q(registers_3__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1229 (.A1(registers_23__ap[27]), .A2(n_1_0_1264), .B1( + n_1_0_1257), .B2(registers_3__ap[27]), .ZN(n_1_0_1169)); + SDFF_X1_LVT \registers_reg[13][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_13__ap[27]), .CK(n_0_43), .Q(registers_13__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[17][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_17__ap[27]), .CK(n_0_47), .Q(registers_17__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1228 (.A1(registers_13__ap[27]), .A2(n_1_0_1277), .B1( + n_1_0_1271), .B2(registers_17__ap[27]), .ZN(n_1_0_1168)); + SDFF_X1_LVT \registers_reg[15][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_15__ap[27]), .CK(n_0_45), .Q(registers_15__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[14][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_14__ap[27]), .CK(n_0_44), .Q(registers_14__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1227 (.A1(registers_15__ap[27]), .A2(n_1_0_1286), .B1( + n_1_0_1258), .B2(registers_14__ap[27]), .ZN(n_1_0_1167)); + NAND3_X1_LVT i_1_0_1226 (.A1(n_1_0_1169), .A2(n_1_0_1168), .A3(n_1_0_1167), + .ZN(n_1_0_1166)); + SDFF_X1_LVT \registers_reg[27][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_27__ap[27]), .CK(n_0_57), .Q(registers_27__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[31][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_31__ap[27]), .CK(n_0_61), .Q(registers_31__ap[27]), .QN()); + AOI221_X1_LVT i_1_0_1225 (.A(n_1_0_1166), .B1(n_1_0_1279), .B2( + registers_27__ap[27]), .C1(registers_31__ap[27]), .C2(n_1_0_1266), + .ZN(n_1_0_1165)); + NAND3_X1_LVT i_1_0_1224 (.A1(n_1_0_1175), .A2(n_1_0_1170), .A3(n_1_0_1165), + .ZN(RRs1[27])); + AND2_X1_LVT i_0_0_26 (.A1(n_0_0_16), .A2(WRd[26]), .ZN(registers[26])); + SDFF_X1_LVT \registers_reg[18][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_18__ap[26]), .CK(n_0_48), .Q(registers_18__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[22][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_22__ap[26]), .CK(n_0_52), .Q(registers_22__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[1][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_1__ap[26]), .CK(n_0_0), .Q(registers_1__ap[26]), .QN()); + AOI222_X1_LVT i_1_0_1223 (.A1(registers_18__ap[26]), .A2(n_1_0_1297), + .B1(n_1_0_1294), .B2(registers_22__ap[26]), .C1(registers_1__ap[26]), + .C2(n_1_0_1274), .ZN(n_1_0_1164)); + SDFF_X1_LVT \registers_reg[29][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_29__ap[26]), .CK(n_0_59), .Q(registers_29__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[2][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_2__ap[26]), .CK(n_0_32), .Q(registers_2__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1222 (.A1(registers_29__ap[26]), .A2(n_1_0_1276), .B1( + n_1_0_1268), .B2(registers_2__ap[26]), .ZN(n_1_0_1163)); + SDFF_X1_LVT \registers_reg[9][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_9__ap[26]), .CK(n_0_39), .Q(registers_9__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[7][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_7__ap[26]), .CK(n_0_37), .Q(registers_7__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1221 (.A1(registers_9__ap[26]), .A2(n_1_0_1291), .B1( + n_1_0_1263), .B2(registers_7__ap[26]), .ZN(n_1_0_1162)); + SDFF_X1_LVT \registers_reg[11][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_11__ap[26]), .CK(n_0_41), .Q(registers_11__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[25][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_25__ap[26]), .CK(n_0_55), .Q(registers_25__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1220 (.A1(registers_11__ap[26]), .A2(n_1_0_1270), .B1( + n_1_0_1269), .B2(registers_25__ap[26]), .ZN(n_1_0_1161)); + SDFF_X1_LVT \registers_reg[27][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_27__ap[26]), .CK(n_0_57), .Q(registers_27__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[16][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_16__ap[26]), .CK(n_0_46), .Q(registers_16__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1219 (.A1(registers_27__ap[26]), .A2(n_1_0_1279), .B1( + n_1_0_1267), .B2(registers_16__ap[26]), .ZN(n_1_0_1160)); + NAND3_X1_LVT i_1_0_1218 (.A1(n_1_0_1162), .A2(n_1_0_1161), .A3(n_1_0_1160), + .ZN(n_1_0_1159)); + SDFF_X1_LVT \registers_reg[31][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_31__ap[26]), .CK(n_0_61), .Q(registers_31__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[6][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_6__ap[26]), .CK(n_0_36), .Q(registers_6__ap[26]), .QN()); + AOI221_X1_LVT i_1_0_1217 (.A(n_1_0_1159), .B1(n_1_0_1266), .B2( + registers_31__ap[26]), .C1(registers_6__ap[26]), .C2(n_1_0_1300), .ZN( + n_1_0_1158)); + NAND3_X1_LVT i_1_0_1216 (.A1(n_1_0_1164), .A2(n_1_0_1163), .A3(n_1_0_1158), + .ZN(n_1_0_1157)); + SDFF_X1_LVT \registers_reg[5][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_5__ap[26]), .CK(n_0_35), .Q(registers_5__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[28][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_28__ap[26]), .CK(n_0_58), .Q(registers_28__ap[26]), .QN()); + AOI221_X1_LVT i_1_0_1215 (.A(n_1_0_1157), .B1(n_1_0_1273), .B2( + registers_5__ap[26]), .C1(registers_28__ap[26]), .C2(n_1_0_1283), .ZN( + n_1_0_1156)); + SDFF_X1_LVT \registers_reg[4][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_4__ap[26]), .CK(n_0_34), .Q(registers_4__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[12][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_12__ap[26]), .CK(n_0_42), .Q(registers_12__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1214 (.A1(registers_4__ap[26]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[26]), .ZN(n_1_0_1155)); + SDFF_X1_LVT \registers_reg[19][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_19__ap[26]), .CK(n_0_49), .Q(registers_19__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[21][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_21__ap[26]), .CK(n_0_51), .Q(registers_21__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1213 (.A1(registers_19__ap[26]), .A2(n_1_0_1295), .B1( + n_1_0_1259), .B2(registers_21__ap[26]), .ZN(n_1_0_1154)); + SDFF_X1_LVT \registers_reg[24][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_24__ap[26]), .CK(n_0_54), .Q(registers_24__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[20][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_20__ap[26]), .CK(n_0_50), .Q(registers_20__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1212 (.A1(registers_24__ap[26]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[26]), .ZN(n_1_0_1153)); + NAND3_X1_LVT i_1_0_1211 (.A1(n_1_0_1155), .A2(n_1_0_1154), .A3(n_1_0_1153), + .ZN(n_1_0_1152)); + SDFF_X1_LVT \registers_reg[26][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_26__ap[26]), .CK(n_0_56), .Q(registers_26__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[30][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_30__ap[26]), .CK(n_0_60), .Q(registers_30__ap[26]), .QN()); + AOI221_X1_LVT i_1_0_1210 (.A(n_1_0_1152), .B1(n_1_0_1285), .B2( + registers_26__ap[26]), .C1(registers_30__ap[26]), .C2(n_1_0_1272), + .ZN(n_1_0_1151)); + SDFF_X1_LVT \registers_reg[8][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_8__ap[26]), .CK(n_0_38), .Q(registers_8__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[23][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_23__ap[26]), .CK(n_0_53), .Q(registers_23__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1209 (.A1(registers_8__ap[26]), .A2(n_1_0_1282), .B1( + n_1_0_1264), .B2(registers_23__ap[26]), .ZN(n_1_0_1150)); + SDFF_X1_LVT \registers_reg[13][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_13__ap[26]), .CK(n_0_43), .Q(registers_13__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[17][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_17__ap[26]), .CK(n_0_47), .Q(registers_17__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1208 (.A1(registers_13__ap[26]), .A2(n_1_0_1277), .B1( + n_1_0_1271), .B2(registers_17__ap[26]), .ZN(n_1_0_1149)); + SDFF_X1_LVT \registers_reg[15][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_15__ap[26]), .CK(n_0_45), .Q(registers_15__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[14][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_14__ap[26]), .CK(n_0_44), .Q(registers_14__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1207 (.A1(registers_15__ap[26]), .A2(n_1_0_1286), .B1( + n_1_0_1258), .B2(registers_14__ap[26]), .ZN(n_1_0_1148)); + NAND3_X1_LVT i_1_0_1206 (.A1(n_1_0_1150), .A2(n_1_0_1149), .A3(n_1_0_1148), + .ZN(n_1_0_1147)); + SDFF_X1_LVT \registers_reg[10][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_10__ap[26]), .CK(n_0_40), .Q(registers_10__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[3][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_3__ap[26]), .CK(n_0_33), .Q(registers_3__ap[26]), .QN()); + AOI221_X1_LVT i_1_0_1205 (.A(n_1_0_1147), .B1(n_1_0_1287), .B2( + registers_10__ap[26]), .C1(registers_3__ap[26]), .C2(n_1_0_1257), .ZN( + n_1_0_1146)); + NAND3_X1_LVT i_1_0_1204 (.A1(n_1_0_1156), .A2(n_1_0_1151), .A3(n_1_0_1146), + .ZN(RRs1[26])); + AND2_X1_LVT i_0_0_25 (.A1(n_0_0_16), .A2(WRd[25]), .ZN(registers[25])); + SDFF_X1_LVT \registers_reg[17][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_17__ap[25]), .CK(n_0_47), .Q(registers_17__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[21][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_21__ap[25]), .CK(n_0_51), .Q(registers_21__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1202 (.A1(registers_17__ap[25]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[25]), .ZN(n_1_0_1144)); + SDFF_X1_LVT \registers_reg[6][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_6__ap[25]), .CK(n_0_36), .Q(registers_6__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[8][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_8__ap[25]), .CK(n_0_38), .Q(registers_8__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1203 (.A1(registers_6__ap[25]), .A2(n_1_0_1300), .B1( + n_1_0_1282), .B2(registers_8__ap[25]), .ZN(n_1_0_1145)); + SDFF_X1_LVT \registers_reg[20][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_20__ap[25]), .CK(n_0_50), .Q(registers_20__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[12][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_12__ap[25]), .CK(n_0_42), .Q(registers_12__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1201 (.A1(registers_20__ap[25]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[25]), .ZN(n_1_0_1143)); + SDFF_X1_LVT \registers_reg[5][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_5__ap[25]), .CK(n_0_35), .Q(registers_5__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[11][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_11__ap[25]), .CK(n_0_41), .Q(registers_11__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1200 (.A1(registers_5__ap[25]), .A2(n_1_0_1273), .B1( + n_1_0_1270), .B2(registers_11__ap[25]), .ZN(n_1_0_1142)); + NAND3_X1_LVT i_1_0_1199 (.A1(n_1_0_1145), .A2(n_1_0_1143), .A3(n_1_0_1142), + .ZN(n_1_0_1141)); + SDFF_X1_LVT \registers_reg[10][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_10__ap[25]), .CK(n_0_40), .Q(registers_10__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[2][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_2__ap[25]), .CK(n_0_32), .Q(registers_2__ap[25]), .QN()); + AOI221_X1_LVT i_1_0_1198 (.A(n_1_0_1141), .B1(n_1_0_1287), .B2( + registers_10__ap[25]), .C1(registers_2__ap[25]), .C2(n_1_0_1268), .ZN( + n_1_0_1140)); + SDFF_X1_LVT \registers_reg[13][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_13__ap[25]), .CK(n_0_43), .Q(registers_13__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[30][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_30__ap[25]), .CK(n_0_60), .Q(registers_30__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[22][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_22__ap[25]), .CK(n_0_52), .Q(registers_22__ap[25]), .QN()); + AOI222_X1_LVT i_1_0_1197 (.A1(registers_13__ap[25]), .A2(n_1_0_1277), + .B1(n_1_0_1272), .B2(registers_30__ap[25]), .C1(registers_22__ap[25]), + .C2(n_1_0_1294), .ZN(n_1_0_1139)); + NAND2_X1_LVT i_1_0_1196 (.A1(n_1_0_1140), .A2(n_1_0_1139), .ZN(n_1_0_1138)); + SDFF_X1_LVT \registers_reg[1][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_1__ap[25]), .CK(n_0_0), .Q(registers_1__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[28][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_28__ap[25]), .CK(n_0_58), .Q(registers_28__ap[25]), .QN()); + AOI221_X1_LVT i_1_0_1195 (.A(n_1_0_1138), .B1(n_1_0_1274), .B2( + registers_1__ap[25]), .C1(registers_28__ap[25]), .C2(n_1_0_1283), .ZN( + n_1_0_1137)); + SDFF_X1_LVT \registers_reg[18][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_18__ap[25]), .CK(n_0_48), .Q(registers_18__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[26][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_26__ap[25]), .CK(n_0_56), .Q(registers_26__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1194 (.A1(registers_18__ap[25]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[25]), .ZN(n_1_0_1136)); + SDFF_X1_LVT \registers_reg[24][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_24__ap[25]), .CK(n_0_54), .Q(registers_24__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[4][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_4__ap[25]), .CK(n_0_34), .Q(registers_4__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1193 (.A1(registers_24__ap[25]), .A2(n_1_0_1289), .B1( + n_1_0_1278), .B2(registers_4__ap[25]), .ZN(n_1_0_1135)); + SDFF_X1_LVT \registers_reg[15][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_15__ap[25]), .CK(n_0_45), .Q(registers_15__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[16][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_16__ap[25]), .CK(n_0_46), .Q(registers_16__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1192 (.A1(registers_15__ap[25]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[25]), .ZN(n_1_0_1134)); + NAND3_X1_LVT i_1_0_1191 (.A1(n_1_0_1136), .A2(n_1_0_1135), .A3(n_1_0_1134), + .ZN(n_1_0_1133)); + SDFF_X1_LVT \registers_reg[19][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_19__ap[25]), .CK(n_0_49), .Q(registers_19__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[25][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_25__ap[25]), .CK(n_0_55), .Q(registers_25__ap[25]), .QN()); + AOI221_X1_LVT i_1_0_1190 (.A(n_1_0_1133), .B1(n_1_0_1295), .B2( + registers_19__ap[25]), .C1(registers_25__ap[25]), .C2(n_1_0_1269), + .ZN(n_1_0_1132)); + SDFF_X1_LVT \registers_reg[7][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_7__ap[25]), .CK(n_0_37), .Q(registers_7__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[14][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_14__ap[25]), .CK(n_0_44), .Q(registers_14__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1189 (.A1(registers_7__ap[25]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[25]), .ZN(n_1_0_1131)); + SDFF_X1_LVT \registers_reg[9][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_9__ap[25]), .CK(n_0_39), .Q(registers_9__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[29][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_29__ap[25]), .CK(n_0_59), .Q(registers_29__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1188 (.A1(registers_9__ap[25]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[25]), .ZN(n_1_0_1130)); + SDFF_X1_LVT \registers_reg[23][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_23__ap[25]), .CK(n_0_53), .Q(registers_23__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[3][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_3__ap[25]), .CK(n_0_33), .Q(registers_3__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1187 (.A1(registers_23__ap[25]), .A2(n_1_0_1264), .B1( + n_1_0_1257), .B2(registers_3__ap[25]), .ZN(n_1_0_1129)); + NAND3_X1_LVT i_1_0_1186 (.A1(n_1_0_1131), .A2(n_1_0_1130), .A3(n_1_0_1129), + .ZN(n_1_0_1128)); + SDFF_X1_LVT \registers_reg[27][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_27__ap[25]), .CK(n_0_57), .Q(registers_27__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[31][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_31__ap[25]), .CK(n_0_61), .Q(registers_31__ap[25]), .QN()); + AOI221_X1_LVT i_1_0_1185 (.A(n_1_0_1128), .B1(n_1_0_1279), .B2( + registers_27__ap[25]), .C1(registers_31__ap[25]), .C2(n_1_0_1266), + .ZN(n_1_0_1127)); + NAND4_X1_LVT i_1_0_1184 (.A1(n_1_0_1144), .A2(n_1_0_1137), .A3(n_1_0_1132), + .A4(n_1_0_1127), .ZN(RRs1[25])); + AND2_X1_LVT i_0_0_24 (.A1(n_0_0_16), .A2(WRd[24]), .ZN(registers[24])); + SDFF_X1_LVT \registers_reg[17][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_17__ap[24]), .CK(n_0_47), .Q(registers_17__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[21][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_21__ap[24]), .CK(n_0_51), .Q(registers_21__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1182 (.A1(registers_17__ap[24]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[24]), .ZN(n_1_0_1125)); + SDFF_X1_LVT \registers_reg[6][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_6__ap[24]), .CK(n_0_36), .Q(registers_6__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[8][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_8__ap[24]), .CK(n_0_38), .Q(registers_8__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1183 (.A1(registers_6__ap[24]), .A2(n_1_0_1300), .B1( + n_1_0_1282), .B2(registers_8__ap[24]), .ZN(n_1_0_1126)); + SDFF_X1_LVT \registers_reg[20][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_20__ap[24]), .CK(n_0_50), .Q(registers_20__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[12][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_12__ap[24]), .CK(n_0_42), .Q(registers_12__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1181 (.A1(registers_20__ap[24]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[24]), .ZN(n_1_0_1124)); + SDFF_X1_LVT \registers_reg[5][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_5__ap[24]), .CK(n_0_35), .Q(registers_5__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[11][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_11__ap[24]), .CK(n_0_41), .Q(registers_11__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1180 (.A1(registers_5__ap[24]), .A2(n_1_0_1273), .B1( + n_1_0_1270), .B2(registers_11__ap[24]), .ZN(n_1_0_1123)); + NAND3_X1_LVT i_1_0_1179 (.A1(n_1_0_1126), .A2(n_1_0_1124), .A3(n_1_0_1123), + .ZN(n_1_0_1122)); + SDFF_X1_LVT \registers_reg[10][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_10__ap[24]), .CK(n_0_40), .Q(registers_10__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[2][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_2__ap[24]), .CK(n_0_32), .Q(registers_2__ap[24]), .QN()); + AOI221_X1_LVT i_1_0_1178 (.A(n_1_0_1122), .B1(n_1_0_1287), .B2( + registers_10__ap[24]), .C1(registers_2__ap[24]), .C2(n_1_0_1268), .ZN( + n_1_0_1121)); + SDFF_X1_LVT \registers_reg[13][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_13__ap[24]), .CK(n_0_43), .Q(registers_13__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[30][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_30__ap[24]), .CK(n_0_60), .Q(registers_30__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[22][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_22__ap[24]), .CK(n_0_52), .Q(registers_22__ap[24]), .QN()); + AOI222_X1_LVT i_1_0_1177 (.A1(registers_13__ap[24]), .A2(n_1_0_1277), + .B1(n_1_0_1272), .B2(registers_30__ap[24]), .C1(registers_22__ap[24]), + .C2(n_1_0_1294), .ZN(n_1_0_1120)); + NAND2_X1_LVT i_1_0_1176 (.A1(n_1_0_1121), .A2(n_1_0_1120), .ZN(n_1_0_1119)); + SDFF_X1_LVT \registers_reg[1][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_1__ap[24]), .CK(n_0_0), .Q(registers_1__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[28][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_28__ap[24]), .CK(n_0_58), .Q(registers_28__ap[24]), .QN()); + AOI221_X1_LVT i_1_0_1175 (.A(n_1_0_1119), .B1(n_1_0_1274), .B2( + registers_1__ap[24]), .C1(registers_28__ap[24]), .C2(n_1_0_1283), .ZN( + n_1_0_1118)); + SDFF_X1_LVT \registers_reg[18][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_18__ap[24]), .CK(n_0_48), .Q(registers_18__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[26][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_26__ap[24]), .CK(n_0_56), .Q(registers_26__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1174 (.A1(registers_18__ap[24]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[24]), .ZN(n_1_0_1117)); + SDFF_X1_LVT \registers_reg[24][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_24__ap[24]), .CK(n_0_54), .Q(registers_24__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[4][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_4__ap[24]), .CK(n_0_34), .Q(registers_4__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1173 (.A1(registers_24__ap[24]), .A2(n_1_0_1289), .B1( + n_1_0_1278), .B2(registers_4__ap[24]), .ZN(n_1_0_1116)); + SDFF_X1_LVT \registers_reg[15][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_15__ap[24]), .CK(n_0_45), .Q(registers_15__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[25][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_25__ap[24]), .CK(n_0_55), .Q(registers_25__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1172 (.A1(registers_15__ap[24]), .A2(n_1_0_1286), .B1( + n_1_0_1269), .B2(registers_25__ap[24]), .ZN(n_1_0_1115)); + NAND3_X1_LVT i_1_0_1171 (.A1(n_1_0_1117), .A2(n_1_0_1116), .A3(n_1_0_1115), + .ZN(n_1_0_1114)); + SDFF_X1_LVT \registers_reg[19][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_19__ap[24]), .CK(n_0_49), .Q(registers_19__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[16][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_16__ap[24]), .CK(n_0_46), .Q(registers_16__ap[24]), .QN()); + AOI221_X1_LVT i_1_0_1170 (.A(n_1_0_1114), .B1(n_1_0_1295), .B2( + registers_19__ap[24]), .C1(registers_16__ap[24]), .C2(n_1_0_1267), + .ZN(n_1_0_1113)); + SDFF_X1_LVT \registers_reg[7][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_7__ap[24]), .CK(n_0_37), .Q(registers_7__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[14][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_14__ap[24]), .CK(n_0_44), .Q(registers_14__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1169 (.A1(registers_7__ap[24]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[24]), .ZN(n_1_0_1112)); + SDFF_X1_LVT \registers_reg[9][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_9__ap[24]), .CK(n_0_39), .Q(registers_9__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[29][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_29__ap[24]), .CK(n_0_59), .Q(registers_29__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1168 (.A1(registers_9__ap[24]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[24]), .ZN(n_1_0_1111)); + SDFF_X1_LVT \registers_reg[23][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_23__ap[24]), .CK(n_0_53), .Q(registers_23__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[3][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_3__ap[24]), .CK(n_0_33), .Q(registers_3__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1167 (.A1(registers_23__ap[24]), .A2(n_1_0_1264), .B1( + n_1_0_1257), .B2(registers_3__ap[24]), .ZN(n_1_0_1110)); + NAND3_X1_LVT i_1_0_1166 (.A1(n_1_0_1112), .A2(n_1_0_1111), .A3(n_1_0_1110), + .ZN(n_1_0_1109)); + SDFF_X1_LVT \registers_reg[27][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_27__ap[24]), .CK(n_0_57), .Q(registers_27__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[31][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_31__ap[24]), .CK(n_0_61), .Q(registers_31__ap[24]), .QN()); + AOI221_X1_LVT i_1_0_1165 (.A(n_1_0_1109), .B1(n_1_0_1279), .B2( + registers_27__ap[24]), .C1(registers_31__ap[24]), .C2(n_1_0_1266), + .ZN(n_1_0_1108)); + NAND4_X1_LVT i_1_0_1164 (.A1(n_1_0_1125), .A2(n_1_0_1118), .A3(n_1_0_1113), + .A4(n_1_0_1108), .ZN(RRs1[24])); + AND2_X1_LVT i_0_0_23 (.A1(n_0_0_16), .A2(WRd[23]), .ZN(registers[23])); + SDFF_X1_LVT \registers_reg[9][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_9__ap[23]), .CK(n_0_39), .Q(registers_9__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[28][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_28__ap[23]), .CK(n_0_58), .Q(registers_28__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1163 (.A1(registers_9__ap[23]), .A2(n_1_0_1291), .B1( + n_1_0_1283), .B2(registers_28__ap[23]), .ZN(n_1_0_1107)); + SDFF_X1_LVT \registers_reg[18][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_18__ap[23]), .CK(n_0_48), .Q(registers_18__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[22][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_22__ap[23]), .CK(n_0_52), .Q(registers_22__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1160 (.A1(registers_18__ap[23]), .A2(n_1_0_1297), .B1( + n_1_0_1294), .B2(registers_22__ap[23]), .ZN(n_1_0_1104)); + SDFF_X1_LVT \registers_reg[1][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_1__ap[23]), .CK(n_0_0), .Q(registers_1__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[21][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_21__ap[23]), .CK(n_0_51), .Q(registers_21__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1159 (.A1(registers_1__ap[23]), .A2(n_1_0_1274), .B1( + n_1_0_1259), .B2(registers_21__ap[23]), .ZN(n_1_0_1103)); + NAND3_X1_LVT i_1_0_1157 (.A1(n_1_0_1107), .A2(n_1_0_1104), .A3(n_1_0_1103), + .ZN(n_1_0_1101)); + SDFF_X1_LVT \registers_reg[20][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_20__ap[23]), .CK(n_0_50), .Q(registers_20__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[19][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_19__ap[23]), .CK(n_0_49), .Q(registers_19__ap[23]), .QN()); + AOI221_X1_LVT i_1_0_1156 (.A(n_1_0_1101), .B1(n_1_0_1281), .B2( + registers_20__ap[23]), .C1(registers_19__ap[23]), .C2(n_1_0_1295), + .ZN(n_1_0_1100)); + SDFF_X1_LVT \registers_reg[26][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_26__ap[23]), .CK(n_0_56), .Q(registers_26__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[23][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_23__ap[23]), .CK(n_0_53), .Q(registers_23__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1162 (.A1(registers_26__ap[23]), .A2(n_1_0_1285), .B1( + n_1_0_1264), .B2(registers_23__ap[23]), .ZN(n_1_0_1106)); + SDFF_X1_LVT \registers_reg[29][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_29__ap[23]), .CK(n_0_59), .Q(registers_29__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[3][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_3__ap[23]), .CK(n_0_33), .Q(registers_3__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1161 (.A1(registers_29__ap[23]), .A2(n_1_0_1276), .B1( + n_1_0_1257), .B2(registers_3__ap[23]), .ZN(n_1_0_1105)); + SDFF_X1_LVT \registers_reg[30][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_30__ap[23]), .CK(n_0_60), .Q(registers_30__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[31][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_31__ap[23]), .CK(n_0_61), .Q(registers_31__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1158 (.A1(registers_30__ap[23]), .A2(n_1_0_1272), .B1( + n_1_0_1266), .B2(registers_31__ap[23]), .ZN(n_1_0_1102)); + NAND3_X1_LVT i_1_0_1155 (.A1(n_1_0_1106), .A2(n_1_0_1105), .A3(n_1_0_1102), + .ZN(n_1_0_1099)); + SDFF_X1_LVT \registers_reg[8][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_8__ap[23]), .CK(n_0_38), .Q(registers_8__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[17][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_17__ap[23]), .CK(n_0_47), .Q(registers_17__ap[23]), .QN()); + AOI221_X1_LVT i_1_0_1154 (.A(n_1_0_1099), .B1(n_1_0_1282), .B2( + registers_8__ap[23]), .C1(registers_17__ap[23]), .C2(n_1_0_1271), .ZN( + n_1_0_1098)); + SDFF_X1_LVT \registers_reg[24][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_24__ap[23]), .CK(n_0_54), .Q(registers_24__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[15][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_15__ap[23]), .CK(n_0_45), .Q(registers_15__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[14][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_14__ap[23]), .CK(n_0_44), .Q(registers_14__ap[23]), .QN()); + AOI222_X1_LVT i_1_0_1153 (.A1(registers_24__ap[23]), .A2(n_1_0_1289), + .B1(n_1_0_1286), .B2(registers_15__ap[23]), .C1(n_1_0_1258), .C2( + registers_14__ap[23]), .ZN(n_1_0_1097)); + SDFF_X1_LVT \registers_reg[16][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_16__ap[23]), .CK(n_0_46), .Q(registers_16__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[7][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_7__ap[23]), .CK(n_0_37), .Q(registers_7__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1152 (.A1(registers_16__ap[23]), .A2(n_1_0_1267), .B1( + n_1_0_1263), .B2(registers_7__ap[23]), .ZN(n_1_0_1096)); + SDFF_X1_LVT \registers_reg[6][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_6__ap[23]), .CK(n_0_36), .Q(registers_6__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[25][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_25__ap[23]), .CK(n_0_55), .Q(registers_25__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1151 (.A1(registers_6__ap[23]), .A2(n_1_0_1300), .B1( + n_1_0_1269), .B2(registers_25__ap[23]), .ZN(n_1_0_1095)); + SDFF_X1_LVT \registers_reg[27][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_27__ap[23]), .CK(n_0_57), .Q(registers_27__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[11][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_11__ap[23]), .CK(n_0_41), .Q(registers_11__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1150 (.A1(registers_27__ap[23]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[23]), .ZN(n_1_0_1094)); + SDFF_X1_LVT \registers_reg[13][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_13__ap[23]), .CK(n_0_43), .Q(registers_13__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[5][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_5__ap[23]), .CK(n_0_35), .Q(registers_5__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1149 (.A1(registers_13__ap[23]), .A2(n_1_0_1277), .B1( + n_1_0_1273), .B2(registers_5__ap[23]), .ZN(n_1_0_1093)); + SDFF_X1_LVT \registers_reg[4][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_4__ap[23]), .CK(n_0_34), .Q(registers_4__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[12][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_12__ap[23]), .CK(n_0_42), .Q(registers_12__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1148 (.A1(registers_4__ap[23]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[23]), .ZN(n_1_0_1092)); + NAND3_X1_LVT i_1_0_1147 (.A1(n_1_0_1094), .A2(n_1_0_1093), .A3(n_1_0_1092), + .ZN(n_1_0_1091)); + SDFF_X1_LVT \registers_reg[2][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_2__ap[23]), .CK(n_0_32), .Q(registers_2__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[10][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_10__ap[23]), .CK(n_0_40), .Q(registers_10__ap[23]), .QN()); + AOI221_X1_LVT i_1_0_1146 (.A(n_1_0_1091), .B1(n_1_0_1268), .B2( + registers_2__ap[23]), .C1(registers_10__ap[23]), .C2(n_1_0_1287), .ZN( + n_1_0_1090)); + AND4_X1_LVT i_1_0_1145 (.A1(n_1_0_1097), .A2(n_1_0_1096), .A3(n_1_0_1095), + .A4(n_1_0_1090), .ZN(n_1_0_1089)); + NAND3_X1_LVT i_1_0_1144 (.A1(n_1_0_1100), .A2(n_1_0_1098), .A3(n_1_0_1089), + .ZN(RRs1[23])); + AND2_X1_LVT i_0_0_22 (.A1(n_0_0_16), .A2(WRd[22]), .ZN(registers[22])); + SDFF_X1_LVT \registers_reg[17][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_17__ap[22]), .CK(n_0_47), .Q(registers_17__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[21][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_21__ap[22]), .CK(n_0_51), .Q(registers_21__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1142 (.A1(registers_17__ap[22]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[22]), .ZN(n_1_0_1087)); + SDFF_X1_LVT \registers_reg[6][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_6__ap[22]), .CK(n_0_36), .Q(registers_6__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[11][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_11__ap[22]), .CK(n_0_41), .Q(registers_11__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1143 (.A1(registers_6__ap[22]), .A2(n_1_0_1300), .B1( + n_1_0_1270), .B2(registers_11__ap[22]), .ZN(n_1_0_1088)); + SDFF_X1_LVT \registers_reg[20][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_20__ap[22]), .CK(n_0_50), .Q(registers_20__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[12][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_12__ap[22]), .CK(n_0_42), .Q(registers_12__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1141 (.A1(registers_20__ap[22]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[22]), .ZN(n_1_0_1086)); + SDFF_X1_LVT \registers_reg[10][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_10__ap[22]), .CK(n_0_40), .Q(registers_10__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[5][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_5__ap[22]), .CK(n_0_35), .Q(registers_5__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1140 (.A1(registers_10__ap[22]), .A2(n_1_0_1287), .B1( + n_1_0_1273), .B2(registers_5__ap[22]), .ZN(n_1_0_1085)); + NAND3_X1_LVT i_1_0_1139 (.A1(n_1_0_1088), .A2(n_1_0_1086), .A3(n_1_0_1085), + .ZN(n_1_0_1084)); + SDFF_X1_LVT \registers_reg[31][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_31__ap[22]), .CK(n_0_61), .Q(registers_31__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[2][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_2__ap[22]), .CK(n_0_32), .Q(registers_2__ap[22]), .QN()); + AOI221_X1_LVT i_1_0_1138 (.A(n_1_0_1084), .B1(n_1_0_1266), .B2( + registers_31__ap[22]), .C1(registers_2__ap[22]), .C2(n_1_0_1268), .ZN( + n_1_0_1083)); + SDFF_X1_LVT \registers_reg[22][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_22__ap[22]), .CK(n_0_52), .Q(registers_22__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[26][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_26__ap[22]), .CK(n_0_56), .Q(registers_26__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[13][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_13__ap[22]), .CK(n_0_43), .Q(registers_13__ap[22]), .QN()); + AOI222_X1_LVT i_1_0_1137 (.A1(registers_22__ap[22]), .A2(n_1_0_1294), + .B1(n_1_0_1285), .B2(registers_26__ap[22]), .C1(n_1_0_1277), .C2( + registers_13__ap[22]), .ZN(n_1_0_1082)); + NAND2_X1_LVT i_1_0_1136 (.A1(n_1_0_1083), .A2(n_1_0_1082), .ZN(n_1_0_1081)); + SDFF_X1_LVT \registers_reg[1][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_1__ap[22]), .CK(n_0_0), .Q(registers_1__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[28][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_28__ap[22]), .CK(n_0_58), .Q(registers_28__ap[22]), .QN()); + AOI221_X1_LVT i_1_0_1135 (.A(n_1_0_1081), .B1(n_1_0_1274), .B2( + registers_1__ap[22]), .C1(registers_28__ap[22]), .C2(n_1_0_1283), .ZN( + n_1_0_1080)); + SDFF_X1_LVT \registers_reg[18][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_18__ap[22]), .CK(n_0_48), .Q(registers_18__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[30][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_30__ap[22]), .CK(n_0_60), .Q(registers_30__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1134 (.A1(registers_18__ap[22]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[22]), .ZN(n_1_0_1079)); + SDFF_X1_LVT \registers_reg[24][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_24__ap[22]), .CK(n_0_54), .Q(registers_24__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[4][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_4__ap[22]), .CK(n_0_34), .Q(registers_4__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1133 (.A1(registers_24__ap[22]), .A2(n_1_0_1289), .B1( + n_1_0_1278), .B2(registers_4__ap[22]), .ZN(n_1_0_1078)); + SDFF_X1_LVT \registers_reg[15][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_15__ap[22]), .CK(n_0_45), .Q(registers_15__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[16][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_16__ap[22]), .CK(n_0_46), .Q(registers_16__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1132 (.A1(registers_15__ap[22]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[22]), .ZN(n_1_0_1077)); + NAND3_X1_LVT i_1_0_1131 (.A1(n_1_0_1079), .A2(n_1_0_1078), .A3(n_1_0_1077), + .ZN(n_1_0_1076)); + SDFF_X1_LVT \registers_reg[19][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_19__ap[22]), .CK(n_0_49), .Q(registers_19__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[25][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_25__ap[22]), .CK(n_0_55), .Q(registers_25__ap[22]), .QN()); + AOI221_X1_LVT i_1_0_1130 (.A(n_1_0_1076), .B1(n_1_0_1295), .B2( + registers_19__ap[22]), .C1(registers_25__ap[22]), .C2(n_1_0_1269), + .ZN(n_1_0_1075)); + SDFF_X1_LVT \registers_reg[7][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_7__ap[22]), .CK(n_0_37), .Q(registers_7__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[14][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_14__ap[22]), .CK(n_0_44), .Q(registers_14__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1129 (.A1(registers_7__ap[22]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[22]), .ZN(n_1_0_1074)); + SDFF_X1_LVT \registers_reg[9][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_9__ap[22]), .CK(n_0_39), .Q(registers_9__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[29][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_29__ap[22]), .CK(n_0_59), .Q(registers_29__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1128 (.A1(registers_9__ap[22]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[22]), .ZN(n_1_0_1073)); + SDFF_X1_LVT \registers_reg[8][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_8__ap[22]), .CK(n_0_38), .Q(registers_8__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[23][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_23__ap[22]), .CK(n_0_53), .Q(registers_23__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1127 (.A1(registers_8__ap[22]), .A2(n_1_0_1282), .B1( + n_1_0_1264), .B2(registers_23__ap[22]), .ZN(n_1_0_1072)); + NAND3_X1_LVT i_1_0_1126 (.A1(n_1_0_1074), .A2(n_1_0_1073), .A3(n_1_0_1072), + .ZN(n_1_0_1071)); + SDFF_X1_LVT \registers_reg[27][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_27__ap[22]), .CK(n_0_57), .Q(registers_27__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[3][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_3__ap[22]), .CK(n_0_33), .Q(registers_3__ap[22]), .QN()); + AOI221_X1_LVT i_1_0_1125 (.A(n_1_0_1071), .B1(n_1_0_1279), .B2( + registers_27__ap[22]), .C1(registers_3__ap[22]), .C2(n_1_0_1257), .ZN( + n_1_0_1070)); + NAND4_X1_LVT i_1_0_1124 (.A1(n_1_0_1087), .A2(n_1_0_1080), .A3(n_1_0_1075), + .A4(n_1_0_1070), .ZN(RRs1[22])); + AND2_X1_LVT i_0_0_21 (.A1(n_0_0_16), .A2(WRd[21]), .ZN(registers[21])); + SDFF_X1_LVT \registers_reg[17][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_17__ap[21]), .CK(n_0_47), .Q(registers_17__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[21][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_21__ap[21]), .CK(n_0_51), .Q(registers_21__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1122 (.A1(registers_17__ap[21]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[21]), .ZN(n_1_0_1068)); + SDFF_X1_LVT \registers_reg[6][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_6__ap[21]), .CK(n_0_36), .Q(registers_6__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[8][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_8__ap[21]), .CK(n_0_38), .Q(registers_8__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1123 (.A1(registers_6__ap[21]), .A2(n_1_0_1300), .B1( + n_1_0_1282), .B2(registers_8__ap[21]), .ZN(n_1_0_1069)); + SDFF_X1_LVT \registers_reg[20][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_20__ap[21]), .CK(n_0_50), .Q(registers_20__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[12][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_12__ap[21]), .CK(n_0_42), .Q(registers_12__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1121 (.A1(registers_20__ap[21]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[21]), .ZN(n_1_0_1067)); + SDFF_X1_LVT \registers_reg[5][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_5__ap[21]), .CK(n_0_35), .Q(registers_5__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[11][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_11__ap[21]), .CK(n_0_41), .Q(registers_11__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1120 (.A1(registers_5__ap[21]), .A2(n_1_0_1273), .B1( + n_1_0_1270), .B2(registers_11__ap[21]), .ZN(n_1_0_1066)); + NAND3_X1_LVT i_1_0_1119 (.A1(n_1_0_1069), .A2(n_1_0_1067), .A3(n_1_0_1066), + .ZN(n_1_0_1065)); + SDFF_X1_LVT \registers_reg[10][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_10__ap[21]), .CK(n_0_40), .Q(registers_10__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[2][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_2__ap[21]), .CK(n_0_32), .Q(registers_2__ap[21]), .QN()); + AOI221_X1_LVT i_1_0_1118 (.A(n_1_0_1065), .B1(n_1_0_1287), .B2( + registers_10__ap[21]), .C1(registers_2__ap[21]), .C2(n_1_0_1268), .ZN( + n_1_0_1064)); + SDFF_X1_LVT \registers_reg[13][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_13__ap[21]), .CK(n_0_43), .Q(registers_13__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[30][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_30__ap[21]), .CK(n_0_60), .Q(registers_30__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[22][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_22__ap[21]), .CK(n_0_52), .Q(registers_22__ap[21]), .QN()); + AOI222_X1_LVT i_1_0_1117 (.A1(registers_13__ap[21]), .A2(n_1_0_1277), + .B1(n_1_0_1272), .B2(registers_30__ap[21]), .C1(registers_22__ap[21]), + .C2(n_1_0_1294), .ZN(n_1_0_1063)); + NAND2_X1_LVT i_1_0_1116 (.A1(n_1_0_1064), .A2(n_1_0_1063), .ZN(n_1_0_1062)); + SDFF_X1_LVT \registers_reg[1][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_1__ap[21]), .CK(n_0_0), .Q(registers_1__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[28][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_28__ap[21]), .CK(n_0_58), .Q(registers_28__ap[21]), .QN()); + AOI221_X1_LVT i_1_0_1115 (.A(n_1_0_1062), .B1(n_1_0_1274), .B2( + registers_1__ap[21]), .C1(registers_28__ap[21]), .C2(n_1_0_1283), .ZN( + n_1_0_1061)); + SDFF_X1_LVT \registers_reg[18][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_18__ap[21]), .CK(n_0_48), .Q(registers_18__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[26][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_26__ap[21]), .CK(n_0_56), .Q(registers_26__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1114 (.A1(registers_18__ap[21]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[21]), .ZN(n_1_0_1060)); + SDFF_X1_LVT \registers_reg[24][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_24__ap[21]), .CK(n_0_54), .Q(registers_24__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[4][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_4__ap[21]), .CK(n_0_34), .Q(registers_4__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1113 (.A1(registers_24__ap[21]), .A2(n_1_0_1289), .B1( + n_1_0_1278), .B2(registers_4__ap[21]), .ZN(n_1_0_1059)); + SDFF_X1_LVT \registers_reg[15][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_15__ap[21]), .CK(n_0_45), .Q(registers_15__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[16][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_16__ap[21]), .CK(n_0_46), .Q(registers_16__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1112 (.A1(registers_15__ap[21]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[21]), .ZN(n_1_0_1058)); + NAND3_X1_LVT i_1_0_1111 (.A1(n_1_0_1060), .A2(n_1_0_1059), .A3(n_1_0_1058), + .ZN(n_1_0_1057)); + SDFF_X1_LVT \registers_reg[19][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_19__ap[21]), .CK(n_0_49), .Q(registers_19__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[25][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_25__ap[21]), .CK(n_0_55), .Q(registers_25__ap[21]), .QN()); + AOI221_X1_LVT i_1_0_1110 (.A(n_1_0_1057), .B1(n_1_0_1295), .B2( + registers_19__ap[21]), .C1(registers_25__ap[21]), .C2(n_1_0_1269), + .ZN(n_1_0_1056)); + SDFF_X1_LVT \registers_reg[7][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_7__ap[21]), .CK(n_0_37), .Q(registers_7__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[14][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_14__ap[21]), .CK(n_0_44), .Q(registers_14__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1109 (.A1(registers_7__ap[21]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[21]), .ZN(n_1_0_1055)); + SDFF_X1_LVT \registers_reg[9][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_9__ap[21]), .CK(n_0_39), .Q(registers_9__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[29][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_29__ap[21]), .CK(n_0_59), .Q(registers_29__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1108 (.A1(registers_9__ap[21]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[21]), .ZN(n_1_0_1054)); + SDFF_X1_LVT \registers_reg[23][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_23__ap[21]), .CK(n_0_53), .Q(registers_23__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[3][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_3__ap[21]), .CK(n_0_33), .Q(registers_3__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1107 (.A1(registers_23__ap[21]), .A2(n_1_0_1264), .B1( + n_1_0_1257), .B2(registers_3__ap[21]), .ZN(n_1_0_1053)); + NAND3_X1_LVT i_1_0_1106 (.A1(n_1_0_1055), .A2(n_1_0_1054), .A3(n_1_0_1053), + .ZN(n_1_0_1052)); + SDFF_X1_LVT \registers_reg[27][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_27__ap[21]), .CK(n_0_57), .Q(registers_27__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[31][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_31__ap[21]), .CK(n_0_61), .Q(registers_31__ap[21]), .QN()); + AOI221_X1_LVT i_1_0_1105 (.A(n_1_0_1052), .B1(n_1_0_1279), .B2( + registers_27__ap[21]), .C1(registers_31__ap[21]), .C2(n_1_0_1266), + .ZN(n_1_0_1051)); + NAND4_X1_LVT i_1_0_1104 (.A1(n_1_0_1068), .A2(n_1_0_1061), .A3(n_1_0_1056), + .A4(n_1_0_1051), .ZN(RRs1[21])); + AND2_X1_LVT i_0_0_20 (.A1(n_0_0_16), .A2(WRd[20]), .ZN(registers[20])); + SDFF_X1_LVT \registers_reg[17][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_17__ap[20]), .CK(n_0_47), .Q(registers_17__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[21][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_21__ap[20]), .CK(n_0_51), .Q(registers_21__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1100 (.A1(registers_17__ap[20]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[20]), .ZN(n_1_0_1047)); + SDFF_X1_LVT \registers_reg[10][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_10__ap[20]), .CK(n_0_40), .Q(registers_10__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[2][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_2__ap[20]), .CK(n_0_32), .Q(registers_2__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1103 (.A1(registers_10__ap[20]), .A2(n_1_0_1287), .B1( + n_1_0_1268), .B2(registers_2__ap[20]), .ZN(n_1_0_1050)); + SDFF_X1_LVT \registers_reg[20][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_20__ap[20]), .CK(n_0_50), .Q(registers_20__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[12][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_12__ap[20]), .CK(n_0_42), .Q(registers_12__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1099 (.A1(registers_20__ap[20]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[20]), .ZN(n_1_0_1046)); + SDFF_X1_LVT \registers_reg[15][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_15__ap[20]), .CK(n_0_45), .Q(registers_15__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[8][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_8__ap[20]), .CK(n_0_38), .Q(registers_8__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1102 (.A1(registers_15__ap[20]), .A2(n_1_0_1286), .B1( + n_1_0_1282), .B2(registers_8__ap[20]), .ZN(n_1_0_1049)); + INV_X1_LVT i_1_0_1101 (.A(n_1_0_1049), .ZN(n_1_0_1048)); + SDFF_X1_LVT \registers_reg[11][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_11__ap[20]), .CK(n_0_41), .Q(registers_11__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[5][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_5__ap[20]), .CK(n_0_35), .Q(registers_5__ap[20]), .QN()); + AOI221_X1_LVT i_1_0_1098 (.A(n_1_0_1048), .B1(n_1_0_1270), .B2( + registers_11__ap[20]), .C1(registers_5__ap[20]), .C2(n_1_0_1273), .ZN( + n_1_0_1045)); + SDFF_X1_LVT \registers_reg[13][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_13__ap[20]), .CK(n_0_43), .Q(registers_13__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[30][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_30__ap[20]), .CK(n_0_60), .Q(registers_30__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[22][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_22__ap[20]), .CK(n_0_52), .Q(registers_22__ap[20]), .QN()); + AOI222_X1_LVT i_1_0_1097 (.A1(registers_13__ap[20]), .A2(n_1_0_1277), + .B1(n_1_0_1272), .B2(registers_30__ap[20]), .C1(registers_22__ap[20]), + .C2(n_1_0_1294), .ZN(n_1_0_1044)); + NAND4_X1_LVT i_1_0_1096 (.A1(n_1_0_1050), .A2(n_1_0_1046), .A3(n_1_0_1045), + .A4(n_1_0_1044), .ZN(n_1_0_1043)); + SDFF_X1_LVT \registers_reg[1][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_1__ap[20]), .CK(n_0_0), .Q(registers_1__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[28][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_28__ap[20]), .CK(n_0_58), .Q(registers_28__ap[20]), .QN()); + AOI221_X1_LVT i_1_0_1095 (.A(n_1_0_1043), .B1(n_1_0_1274), .B2( + registers_1__ap[20]), .C1(registers_28__ap[20]), .C2(n_1_0_1283), .ZN( + n_1_0_1042)); + SDFF_X1_LVT \registers_reg[18][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_18__ap[20]), .CK(n_0_48), .Q(registers_18__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[26][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_26__ap[20]), .CK(n_0_56), .Q(registers_26__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1094 (.A1(registers_18__ap[20]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[20]), .ZN(n_1_0_1041)); + SDFF_X1_LVT \registers_reg[24][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_24__ap[20]), .CK(n_0_54), .Q(registers_24__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[4][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_4__ap[20]), .CK(n_0_34), .Q(registers_4__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1093 (.A1(registers_24__ap[20]), .A2(n_1_0_1289), .B1( + n_1_0_1278), .B2(registers_4__ap[20]), .ZN(n_1_0_1040)); + SDFF_X1_LVT \registers_reg[6][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_6__ap[20]), .CK(n_0_36), .Q(registers_6__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[25][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_25__ap[20]), .CK(n_0_55), .Q(registers_25__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1092 (.A1(registers_6__ap[20]), .A2(n_1_0_1300), .B1( + n_1_0_1269), .B2(registers_25__ap[20]), .ZN(n_1_0_1039)); + NAND3_X1_LVT i_1_0_1091 (.A1(n_1_0_1041), .A2(n_1_0_1040), .A3(n_1_0_1039), + .ZN(n_1_0_1038)); + SDFF_X1_LVT \registers_reg[19][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_19__ap[20]), .CK(n_0_49), .Q(registers_19__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[16][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_16__ap[20]), .CK(n_0_46), .Q(registers_16__ap[20]), .QN()); + AOI221_X1_LVT i_1_0_1090 (.A(n_1_0_1038), .B1(n_1_0_1295), .B2( + registers_19__ap[20]), .C1(registers_16__ap[20]), .C2(n_1_0_1267), + .ZN(n_1_0_1037)); + SDFF_X1_LVT \registers_reg[7][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_7__ap[20]), .CK(n_0_37), .Q(registers_7__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[14][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_14__ap[20]), .CK(n_0_44), .Q(registers_14__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1089 (.A1(registers_7__ap[20]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[20]), .ZN(n_1_0_1036)); + SDFF_X1_LVT \registers_reg[9][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_9__ap[20]), .CK(n_0_39), .Q(registers_9__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[29][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_29__ap[20]), .CK(n_0_59), .Q(registers_29__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1088 (.A1(registers_9__ap[20]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[20]), .ZN(n_1_0_1035)); + SDFF_X1_LVT \registers_reg[23][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_23__ap[20]), .CK(n_0_53), .Q(registers_23__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[3][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_3__ap[20]), .CK(n_0_33), .Q(registers_3__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1087 (.A1(registers_23__ap[20]), .A2(n_1_0_1264), .B1( + n_1_0_1257), .B2(registers_3__ap[20]), .ZN(n_1_0_1034)); + NAND3_X1_LVT i_1_0_1086 (.A1(n_1_0_1036), .A2(n_1_0_1035), .A3(n_1_0_1034), + .ZN(n_1_0_1033)); + SDFF_X1_LVT \registers_reg[27][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_27__ap[20]), .CK(n_0_57), .Q(registers_27__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[31][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_31__ap[20]), .CK(n_0_61), .Q(registers_31__ap[20]), .QN()); + AOI221_X1_LVT i_1_0_1085 (.A(n_1_0_1033), .B1(n_1_0_1279), .B2( + registers_27__ap[20]), .C1(registers_31__ap[20]), .C2(n_1_0_1266), + .ZN(n_1_0_1032)); + NAND4_X1_LVT i_1_0_1084 (.A1(n_1_0_1047), .A2(n_1_0_1042), .A3(n_1_0_1037), + .A4(n_1_0_1032), .ZN(RRs1[20])); + AND2_X1_LVT i_0_0_19 (.A1(n_0_0_16), .A2(WRd[19]), .ZN(registers[19])); + SDFF_X1_LVT \registers_reg[17][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_17__ap[19]), .CK(n_0_47), .Q(registers_17__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[21][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_21__ap[19]), .CK(n_0_51), .Q(registers_21__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1080 (.A1(registers_17__ap[19]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[19]), .ZN(n_1_0_1028)); + SDFF_X1_LVT \registers_reg[2][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_2__ap[19]), .CK(n_0_32), .Q(registers_2__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[31][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_31__ap[19]), .CK(n_0_61), .Q(registers_31__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1083 (.A1(registers_2__ap[19]), .A2(n_1_0_1268), .B1( + n_1_0_1266), .B2(registers_31__ap[19]), .ZN(n_1_0_1031)); + SDFF_X1_LVT \registers_reg[20][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_20__ap[19]), .CK(n_0_50), .Q(registers_20__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[12][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_12__ap[19]), .CK(n_0_42), .Q(registers_12__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1079 (.A1(registers_20__ap[19]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[19]), .ZN(n_1_0_1027)); + SDFF_X1_LVT \registers_reg[15][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_15__ap[19]), .CK(n_0_45), .Q(registers_15__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[11][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_11__ap[19]), .CK(n_0_41), .Q(registers_11__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1082 (.A1(registers_15__ap[19]), .A2(n_1_0_1286), .B1( + n_1_0_1270), .B2(registers_11__ap[19]), .ZN(n_1_0_1030)); + INV_X1_LVT i_1_0_1081 (.A(n_1_0_1030), .ZN(n_1_0_1029)); + SDFF_X1_LVT \registers_reg[27][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_27__ap[19]), .CK(n_0_57), .Q(registers_27__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[24][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_24__ap[19]), .CK(n_0_54), .Q(registers_24__ap[19]), .QN()); + AOI221_X1_LVT i_1_0_1078 (.A(n_1_0_1029), .B1(n_1_0_1279), .B2( + registers_27__ap[19]), .C1(registers_24__ap[19]), .C2(n_1_0_1289), + .ZN(n_1_0_1026)); + SDFF_X1_LVT \registers_reg[22][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_22__ap[19]), .CK(n_0_52), .Q(registers_22__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[26][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_26__ap[19]), .CK(n_0_56), .Q(registers_26__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[13][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_13__ap[19]), .CK(n_0_43), .Q(registers_13__ap[19]), .QN()); + AOI222_X1_LVT i_1_0_1077 (.A1(registers_22__ap[19]), .A2(n_1_0_1294), + .B1(n_1_0_1285), .B2(registers_26__ap[19]), .C1(n_1_0_1277), .C2( + registers_13__ap[19]), .ZN(n_1_0_1025)); + NAND4_X1_LVT i_1_0_1076 (.A1(n_1_0_1031), .A2(n_1_0_1027), .A3(n_1_0_1026), + .A4(n_1_0_1025), .ZN(n_1_0_1024)); + SDFF_X1_LVT \registers_reg[1][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_1__ap[19]), .CK(n_0_0), .Q(registers_1__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[28][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_28__ap[19]), .CK(n_0_58), .Q(registers_28__ap[19]), .QN()); + AOI221_X1_LVT i_1_0_1075 (.A(n_1_0_1024), .B1(n_1_0_1274), .B2( + registers_1__ap[19]), .C1(registers_28__ap[19]), .C2(n_1_0_1283), .ZN( + n_1_0_1023)); + SDFF_X1_LVT \registers_reg[18][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_18__ap[19]), .CK(n_0_48), .Q(registers_18__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[30][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_30__ap[19]), .CK(n_0_60), .Q(registers_30__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1074 (.A1(registers_18__ap[19]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[19]), .ZN(n_1_0_1022)); + SDFF_X1_LVT \registers_reg[4][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_4__ap[19]), .CK(n_0_34), .Q(registers_4__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[5][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_5__ap[19]), .CK(n_0_35), .Q(registers_5__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1073 (.A1(registers_4__ap[19]), .A2(n_1_0_1278), .B1( + n_1_0_1273), .B2(registers_5__ap[19]), .ZN(n_1_0_1021)); + SDFF_X1_LVT \registers_reg[6][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_6__ap[19]), .CK(n_0_36), .Q(registers_6__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[25][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_25__ap[19]), .CK(n_0_55), .Q(registers_25__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1072 (.A1(registers_6__ap[19]), .A2(n_1_0_1300), .B1( + n_1_0_1269), .B2(registers_25__ap[19]), .ZN(n_1_0_1020)); + NAND3_X1_LVT i_1_0_1071 (.A1(n_1_0_1022), .A2(n_1_0_1021), .A3(n_1_0_1020), + .ZN(n_1_0_1019)); + SDFF_X1_LVT \registers_reg[19][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_19__ap[19]), .CK(n_0_49), .Q(registers_19__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[16][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_16__ap[19]), .CK(n_0_46), .Q(registers_16__ap[19]), .QN()); + AOI221_X1_LVT i_1_0_1070 (.A(n_1_0_1019), .B1(n_1_0_1295), .B2( + registers_19__ap[19]), .C1(registers_16__ap[19]), .C2(n_1_0_1267), + .ZN(n_1_0_1018)); + SDFF_X1_LVT \registers_reg[9][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_9__ap[19]), .CK(n_0_39), .Q(registers_9__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[29][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_29__ap[19]), .CK(n_0_59), .Q(registers_29__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1069 (.A1(registers_9__ap[19]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[19]), .ZN(n_1_0_1017)); + SDFF_X1_LVT \registers_reg[8][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_8__ap[19]), .CK(n_0_38), .Q(registers_8__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[23][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_23__ap[19]), .CK(n_0_53), .Q(registers_23__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1068 (.A1(registers_8__ap[19]), .A2(n_1_0_1282), .B1( + n_1_0_1264), .B2(registers_23__ap[19]), .ZN(n_1_0_1016)); + SDFF_X1_LVT \registers_reg[7][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_7__ap[19]), .CK(n_0_37), .Q(registers_7__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[14][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_14__ap[19]), .CK(n_0_44), .Q(registers_14__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1067 (.A1(registers_7__ap[19]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[19]), .ZN(n_1_0_1015)); + NAND3_X1_LVT i_1_0_1066 (.A1(n_1_0_1017), .A2(n_1_0_1016), .A3(n_1_0_1015), + .ZN(n_1_0_1014)); + SDFF_X1_LVT \registers_reg[10][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_10__ap[19]), .CK(n_0_40), .Q(registers_10__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[3][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_3__ap[19]), .CK(n_0_33), .Q(registers_3__ap[19]), .QN()); + AOI221_X1_LVT i_1_0_1065 (.A(n_1_0_1014), .B1(n_1_0_1287), .B2( + registers_10__ap[19]), .C1(registers_3__ap[19]), .C2(n_1_0_1257), .ZN( + n_1_0_1013)); + NAND4_X1_LVT i_1_0_1064 (.A1(n_1_0_1028), .A2(n_1_0_1023), .A3(n_1_0_1018), + .A4(n_1_0_1013), .ZN(RRs1[19])); + AND2_X1_LVT i_0_0_18 (.A1(n_0_0_16), .A2(WRd[18]), .ZN(registers[18])); + SDFF_X1_LVT \registers_reg[24][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_24__ap[18]), .CK(n_0_54), .Q(registers_24__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[28][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_28__ap[18]), .CK(n_0_58), .Q(registers_28__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1062 (.A1(registers_24__ap[18]), .A2(n_1_0_1289), .B1( + n_1_0_1283), .B2(registers_28__ap[18]), .ZN(n_1_0_1011)); + SDFF_X1_LVT \registers_reg[11][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_11__ap[18]), .CK(n_0_41), .Q(registers_11__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[16][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_16__ap[18]), .CK(n_0_46), .Q(registers_16__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1063 (.A1(registers_11__ap[18]), .A2(n_1_0_1270), .B1( + n_1_0_1267), .B2(registers_16__ap[18]), .ZN(n_1_0_1012)); + SDFF_X1_LVT \registers_reg[9][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_9__ap[18]), .CK(n_0_39), .Q(registers_9__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[7][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_7__ap[18]), .CK(n_0_37), .Q(registers_7__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1061 (.A1(registers_9__ap[18]), .A2(n_1_0_1291), .B1( + n_1_0_1263), .B2(registers_7__ap[18]), .ZN(n_1_0_1010)); + SDFF_X1_LVT \registers_reg[27][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_27__ap[18]), .CK(n_0_57), .Q(registers_27__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[25][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_25__ap[18]), .CK(n_0_55), .Q(registers_25__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1060 (.A1(registers_27__ap[18]), .A2(n_1_0_1279), .B1( + n_1_0_1269), .B2(registers_25__ap[18]), .ZN(n_1_0_1009)); + NAND3_X1_LVT i_1_0_1059 (.A1(n_1_0_1012), .A2(n_1_0_1010), .A3(n_1_0_1009), + .ZN(n_1_0_1008)); + SDFF_X1_LVT \registers_reg[31][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_31__ap[18]), .CK(n_0_61), .Q(registers_31__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[6][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_6__ap[18]), .CK(n_0_36), .Q(registers_6__ap[18]), .QN()); + AOI221_X1_LVT i_1_0_1058 (.A(n_1_0_1008), .B1(n_1_0_1266), .B2( + registers_31__ap[18]), .C1(registers_6__ap[18]), .C2(n_1_0_1300), .ZN( + n_1_0_1007)); + SDFF_X1_LVT \registers_reg[22][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_22__ap[18]), .CK(n_0_52), .Q(registers_22__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[26][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_26__ap[18]), .CK(n_0_56), .Q(registers_26__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[1][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_1__ap[18]), .CK(n_0_0), .Q(registers_1__ap[18]), .QN()); + AOI222_X1_LVT i_1_0_1057 (.A1(registers_22__ap[18]), .A2(n_1_0_1294), + .B1(n_1_0_1285), .B2(registers_26__ap[18]), .C1(n_1_0_1274), .C2( + registers_1__ap[18]), .ZN(n_1_0_1006)); + NAND2_X1_LVT i_1_0_1056 (.A1(n_1_0_1007), .A2(n_1_0_1006), .ZN(n_1_0_1005)); + SDFF_X1_LVT \registers_reg[29][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_29__ap[18]), .CK(n_0_59), .Q(registers_29__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[2][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_2__ap[18]), .CK(n_0_32), .Q(registers_2__ap[18]), .QN()); + AOI221_X1_LVT i_1_0_1055 (.A(n_1_0_1005), .B1(n_1_0_1276), .B2( + registers_29__ap[18]), .C1(registers_2__ap[18]), .C2(n_1_0_1268), .ZN( + n_1_0_1004)); + SDFF_X1_LVT \registers_reg[18][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_18__ap[18]), .CK(n_0_48), .Q(registers_18__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[30][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_30__ap[18]), .CK(n_0_60), .Q(registers_30__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1054 (.A1(registers_18__ap[18]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[18]), .ZN(n_1_0_1003)); + SDFF_X1_LVT \registers_reg[4][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_4__ap[18]), .CK(n_0_34), .Q(registers_4__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[12][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_12__ap[18]), .CK(n_0_42), .Q(registers_12__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1053 (.A1(registers_4__ap[18]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[18]), .ZN(n_1_0_1002)); + SDFF_X1_LVT \registers_reg[19][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_19__ap[18]), .CK(n_0_49), .Q(registers_19__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[21][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_21__ap[18]), .CK(n_0_51), .Q(registers_21__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1052 (.A1(registers_19__ap[18]), .A2(n_1_0_1295), .B1( + n_1_0_1259), .B2(registers_21__ap[18]), .ZN(n_1_0_1001)); + NAND3_X1_LVT i_1_0_1051 (.A1(n_1_0_1003), .A2(n_1_0_1002), .A3(n_1_0_1001), + .ZN(n_1_0_1000)); + SDFF_X1_LVT \registers_reg[5][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_5__ap[18]), .CK(n_0_35), .Q(registers_5__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[20][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_20__ap[18]), .CK(n_0_50), .Q(registers_20__ap[18]), .QN()); + AOI221_X1_LVT i_1_0_1050 (.A(n_1_0_1000), .B1(n_1_0_1273), .B2( + registers_5__ap[18]), .C1(registers_20__ap[18]), .C2(n_1_0_1281), .ZN( + n_1_0_999)); + SDFF_X1_LVT \registers_reg[8][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_8__ap[18]), .CK(n_0_38), .Q(registers_8__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[23][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_23__ap[18]), .CK(n_0_53), .Q(registers_23__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1049 (.A1(registers_8__ap[18]), .A2(n_1_0_1282), .B1( + n_1_0_1264), .B2(registers_23__ap[18]), .ZN(n_1_0_998)); + SDFF_X1_LVT \registers_reg[13][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_13__ap[18]), .CK(n_0_43), .Q(registers_13__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[17][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_17__ap[18]), .CK(n_0_47), .Q(registers_17__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1048 (.A1(registers_13__ap[18]), .A2(n_1_0_1277), .B1( + n_1_0_1271), .B2(registers_17__ap[18]), .ZN(n_1_0_997)); + SDFF_X1_LVT \registers_reg[15][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_15__ap[18]), .CK(n_0_45), .Q(registers_15__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[14][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_14__ap[18]), .CK(n_0_44), .Q(registers_14__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1047 (.A1(registers_15__ap[18]), .A2(n_1_0_1286), .B1( + n_1_0_1258), .B2(registers_14__ap[18]), .ZN(n_1_0_996)); + NAND3_X1_LVT i_1_0_1046 (.A1(n_1_0_998), .A2(n_1_0_997), .A3(n_1_0_996), + .ZN(n_1_0_995)); + SDFF_X1_LVT \registers_reg[10][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_10__ap[18]), .CK(n_0_40), .Q(registers_10__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[3][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_3__ap[18]), .CK(n_0_33), .Q(registers_3__ap[18]), .QN()); + AOI221_X1_LVT i_1_0_1045 (.A(n_1_0_995), .B1(n_1_0_1287), .B2( + registers_10__ap[18]), .C1(registers_3__ap[18]), .C2(n_1_0_1257), .ZN( + n_1_0_994)); + NAND4_X1_LVT i_1_0_1044 (.A1(n_1_0_1011), .A2(n_1_0_1004), .A3(n_1_0_999), + .A4(n_1_0_994), .ZN(RRs1[18])); + AND2_X1_LVT i_0_0_17 (.A1(n_0_0_16), .A2(WRd[17]), .ZN(registers[17])); + SDFF_X1_LVT \registers_reg[17][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_17__ap[17]), .CK(n_0_47), .Q(registers_17__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[21][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_21__ap[17]), .CK(n_0_51), .Q(registers_21__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1040 (.A1(registers_17__ap[17]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[17]), .ZN(n_1_0_990)); + SDFF_X1_LVT \registers_reg[2][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_2__ap[17]), .CK(n_0_32), .Q(registers_2__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[31][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_31__ap[17]), .CK(n_0_61), .Q(registers_31__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1043 (.A1(registers_2__ap[17]), .A2(n_1_0_1268), .B1( + n_1_0_1266), .B2(registers_31__ap[17]), .ZN(n_1_0_993)); + SDFF_X1_LVT \registers_reg[20][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_20__ap[17]), .CK(n_0_50), .Q(registers_20__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[12][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_12__ap[17]), .CK(n_0_42), .Q(registers_12__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1039 (.A1(registers_20__ap[17]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[17]), .ZN(n_1_0_989)); + SDFF_X1_LVT \registers_reg[15][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_15__ap[17]), .CK(n_0_45), .Q(registers_15__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[11][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_11__ap[17]), .CK(n_0_41), .Q(registers_11__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1042 (.A1(registers_15__ap[17]), .A2(n_1_0_1286), .B1( + n_1_0_1270), .B2(registers_11__ap[17]), .ZN(n_1_0_992)); + INV_X1_LVT i_1_0_1041 (.A(n_1_0_992), .ZN(n_1_0_991)); + SDFF_X1_LVT \registers_reg[10][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_10__ap[17]), .CK(n_0_40), .Q(registers_10__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[24][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_24__ap[17]), .CK(n_0_54), .Q(registers_24__ap[17]), .QN()); + AOI221_X1_LVT i_1_0_1038 (.A(n_1_0_991), .B1(n_1_0_1287), .B2( + registers_10__ap[17]), .C1(registers_24__ap[17]), .C2(n_1_0_1289), + .ZN(n_1_0_988)); + SDFF_X1_LVT \registers_reg[22][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_22__ap[17]), .CK(n_0_52), .Q(registers_22__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[26][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_26__ap[17]), .CK(n_0_56), .Q(registers_26__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[13][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_13__ap[17]), .CK(n_0_43), .Q(registers_13__ap[17]), .QN()); + AOI222_X1_LVT i_1_0_1037 (.A1(registers_22__ap[17]), .A2(n_1_0_1294), + .B1(n_1_0_1285), .B2(registers_26__ap[17]), .C1(n_1_0_1277), .C2( + registers_13__ap[17]), .ZN(n_1_0_987)); + NAND4_X1_LVT i_1_0_1036 (.A1(n_1_0_993), .A2(n_1_0_989), .A3(n_1_0_988), + .A4(n_1_0_987), .ZN(n_1_0_986)); + SDFF_X1_LVT \registers_reg[1][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_1__ap[17]), .CK(n_0_0), .Q(registers_1__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[28][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_28__ap[17]), .CK(n_0_58), .Q(registers_28__ap[17]), .QN()); + AOI221_X1_LVT i_1_0_1035 (.A(n_1_0_986), .B1(n_1_0_1274), .B2( + registers_1__ap[17]), .C1(registers_28__ap[17]), .C2(n_1_0_1283), .ZN( + n_1_0_985)); + SDFF_X1_LVT \registers_reg[18][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_18__ap[17]), .CK(n_0_48), .Q(registers_18__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[30][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_30__ap[17]), .CK(n_0_60), .Q(registers_30__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1034 (.A1(registers_18__ap[17]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[17]), .ZN(n_1_0_984)); + SDFF_X1_LVT \registers_reg[4][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_4__ap[17]), .CK(n_0_34), .Q(registers_4__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[5][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_5__ap[17]), .CK(n_0_35), .Q(registers_5__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1033 (.A1(registers_4__ap[17]), .A2(n_1_0_1278), .B1( + n_1_0_1273), .B2(registers_5__ap[17]), .ZN(n_1_0_983)); + SDFF_X1_LVT \registers_reg[6][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_6__ap[17]), .CK(n_0_36), .Q(registers_6__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[25][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_25__ap[17]), .CK(n_0_55), .Q(registers_25__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1032 (.A1(registers_6__ap[17]), .A2(n_1_0_1300), .B1( + n_1_0_1269), .B2(registers_25__ap[17]), .ZN(n_1_0_982)); + NAND3_X1_LVT i_1_0_1031 (.A1(n_1_0_984), .A2(n_1_0_983), .A3(n_1_0_982), + .ZN(n_1_0_981)); + SDFF_X1_LVT \registers_reg[19][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_19__ap[17]), .CK(n_0_49), .Q(registers_19__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[16][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_16__ap[17]), .CK(n_0_46), .Q(registers_16__ap[17]), .QN()); + AOI221_X1_LVT i_1_0_1030 (.A(n_1_0_981), .B1(n_1_0_1295), .B2( + registers_19__ap[17]), .C1(registers_16__ap[17]), .C2(n_1_0_1267), + .ZN(n_1_0_980)); + SDFF_X1_LVT \registers_reg[7][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_7__ap[17]), .CK(n_0_37), .Q(registers_7__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[14][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_14__ap[17]), .CK(n_0_44), .Q(registers_14__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1029 (.A1(registers_7__ap[17]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[17]), .ZN(n_1_0_979)); + SDFF_X1_LVT \registers_reg[9][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_9__ap[17]), .CK(n_0_39), .Q(registers_9__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[29][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_29__ap[17]), .CK(n_0_59), .Q(registers_29__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1028 (.A1(registers_9__ap[17]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[17]), .ZN(n_1_0_978)); + SDFF_X1_LVT \registers_reg[8][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_8__ap[17]), .CK(n_0_38), .Q(registers_8__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[23][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_23__ap[17]), .CK(n_0_53), .Q(registers_23__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1027 (.A1(registers_8__ap[17]), .A2(n_1_0_1282), .B1( + n_1_0_1264), .B2(registers_23__ap[17]), .ZN(n_1_0_977)); + NAND3_X1_LVT i_1_0_1026 (.A1(n_1_0_979), .A2(n_1_0_978), .A3(n_1_0_977), + .ZN(n_1_0_976)); + SDFF_X1_LVT \registers_reg[27][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_27__ap[17]), .CK(n_0_57), .Q(registers_27__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[3][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_3__ap[17]), .CK(n_0_33), .Q(registers_3__ap[17]), .QN()); + AOI221_X1_LVT i_1_0_1025 (.A(n_1_0_976), .B1(n_1_0_1279), .B2( + registers_27__ap[17]), .C1(registers_3__ap[17]), .C2(n_1_0_1257), .ZN( + n_1_0_975)); + NAND4_X1_LVT i_1_0_1024 (.A1(n_1_0_990), .A2(n_1_0_985), .A3(n_1_0_980), + .A4(n_1_0_975), .ZN(RRs1[17])); + AND2_X1_LVT i_0_0_16 (.A1(n_0_0_16), .A2(WRd[16]), .ZN(registers[16])); + SDFF_X1_LVT \registers_reg[29][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_29__ap[16]), .CK(n_0_59), .Q(registers_29__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[2][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_2__ap[16]), .CK(n_0_32), .Q(registers_2__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1022 (.A1(registers_29__ap[16]), .A2(n_1_0_1276), .B1( + n_1_0_1268), .B2(registers_2__ap[16]), .ZN(n_1_0_973)); + SDFF_X1_LVT \registers_reg[11][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_11__ap[16]), .CK(n_0_41), .Q(registers_11__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[25][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_25__ap[16]), .CK(n_0_55), .Q(registers_25__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1023 (.A1(registers_11__ap[16]), .A2(n_1_0_1270), .B1( + n_1_0_1269), .B2(registers_25__ap[16]), .ZN(n_1_0_974)); + SDFF_X1_LVT \registers_reg[9][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_9__ap[16]), .CK(n_0_39), .Q(registers_9__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[7][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_7__ap[16]), .CK(n_0_37), .Q(registers_7__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1021 (.A1(registers_9__ap[16]), .A2(n_1_0_1291), .B1( + n_1_0_1263), .B2(registers_7__ap[16]), .ZN(n_1_0_972)); + SDFF_X1_LVT \registers_reg[10][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_10__ap[16]), .CK(n_0_40), .Q(registers_10__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[16][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_16__ap[16]), .CK(n_0_46), .Q(registers_16__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1020 (.A1(registers_10__ap[16]), .A2(n_1_0_1287), .B1( + n_1_0_1267), .B2(registers_16__ap[16]), .ZN(n_1_0_971)); + NAND3_X1_LVT i_1_0_1019 (.A1(n_1_0_974), .A2(n_1_0_972), .A3(n_1_0_971), + .ZN(n_1_0_970)); + SDFF_X1_LVT \registers_reg[31][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_31__ap[16]), .CK(n_0_61), .Q(registers_31__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[6][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_6__ap[16]), .CK(n_0_36), .Q(registers_6__ap[16]), .QN()); + AOI221_X1_LVT i_1_0_1018 (.A(n_1_0_970), .B1(n_1_0_1266), .B2( + registers_31__ap[16]), .C1(registers_6__ap[16]), .C2(n_1_0_1300), .ZN( + n_1_0_969)); + SDFF_X1_LVT \registers_reg[18][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_18__ap[16]), .CK(n_0_48), .Q(registers_18__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[22][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_22__ap[16]), .CK(n_0_52), .Q(registers_22__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[1][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_1__ap[16]), .CK(n_0_0), .Q(registers_1__ap[16]), .QN()); + AOI222_X1_LVT i_1_0_1017 (.A1(registers_18__ap[16]), .A2(n_1_0_1297), + .B1(n_1_0_1294), .B2(registers_22__ap[16]), .C1(registers_1__ap[16]), + .C2(n_1_0_1274), .ZN(n_1_0_968)); + NAND3_X1_LVT i_1_0_1016 (.A1(n_1_0_973), .A2(n_1_0_969), .A3(n_1_0_968), + .ZN(n_1_0_967)); + SDFF_X1_LVT \registers_reg[5][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_5__ap[16]), .CK(n_0_35), .Q(registers_5__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[28][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_28__ap[16]), .CK(n_0_58), .Q(registers_28__ap[16]), .QN()); + AOI221_X1_LVT i_1_0_1015 (.A(n_1_0_967), .B1(n_1_0_1273), .B2( + registers_5__ap[16]), .C1(registers_28__ap[16]), .C2(n_1_0_1283), .ZN( + n_1_0_966)); + SDFF_X1_LVT \registers_reg[4][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_4__ap[16]), .CK(n_0_34), .Q(registers_4__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[12][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_12__ap[16]), .CK(n_0_42), .Q(registers_12__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1014 (.A1(registers_4__ap[16]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[16]), .ZN(n_1_0_965)); + SDFF_X1_LVT \registers_reg[19][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_19__ap[16]), .CK(n_0_49), .Q(registers_19__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[21][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_21__ap[16]), .CK(n_0_51), .Q(registers_21__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1013 (.A1(registers_19__ap[16]), .A2(n_1_0_1295), .B1( + n_1_0_1259), .B2(registers_21__ap[16]), .ZN(n_1_0_964)); + SDFF_X1_LVT \registers_reg[24][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_24__ap[16]), .CK(n_0_54), .Q(registers_24__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[20][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_20__ap[16]), .CK(n_0_50), .Q(registers_20__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1012 (.A1(registers_24__ap[16]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[16]), .ZN(n_1_0_963)); + NAND3_X1_LVT i_1_0_1011 (.A1(n_1_0_965), .A2(n_1_0_964), .A3(n_1_0_963), + .ZN(n_1_0_962)); + SDFF_X1_LVT \registers_reg[26][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_26__ap[16]), .CK(n_0_56), .Q(registers_26__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[30][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_30__ap[16]), .CK(n_0_60), .Q(registers_30__ap[16]), .QN()); + AOI221_X1_LVT i_1_0_1010 (.A(n_1_0_962), .B1(n_1_0_1285), .B2( + registers_26__ap[16]), .C1(registers_30__ap[16]), .C2(n_1_0_1272), + .ZN(n_1_0_961)); + SDFF_X1_LVT \registers_reg[8][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_8__ap[16]), .CK(n_0_38), .Q(registers_8__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[23][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_23__ap[16]), .CK(n_0_53), .Q(registers_23__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1009 (.A1(registers_8__ap[16]), .A2(n_1_0_1282), .B1( + n_1_0_1264), .B2(registers_23__ap[16]), .ZN(n_1_0_960)); + SDFF_X1_LVT \registers_reg[13][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_13__ap[16]), .CK(n_0_43), .Q(registers_13__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[17][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_17__ap[16]), .CK(n_0_47), .Q(registers_17__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1008 (.A1(registers_13__ap[16]), .A2(n_1_0_1277), .B1( + n_1_0_1271), .B2(registers_17__ap[16]), .ZN(n_1_0_959)); + SDFF_X1_LVT \registers_reg[15][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_15__ap[16]), .CK(n_0_45), .Q(registers_15__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[14][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_14__ap[16]), .CK(n_0_44), .Q(registers_14__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1007 (.A1(registers_15__ap[16]), .A2(n_1_0_1286), .B1( + n_1_0_1258), .B2(registers_14__ap[16]), .ZN(n_1_0_958)); + NAND3_X1_LVT i_1_0_1006 (.A1(n_1_0_960), .A2(n_1_0_959), .A3(n_1_0_958), + .ZN(n_1_0_957)); + SDFF_X1_LVT \registers_reg[27][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_27__ap[16]), .CK(n_0_57), .Q(registers_27__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[3][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_3__ap[16]), .CK(n_0_33), .Q(registers_3__ap[16]), .QN()); + AOI221_X1_LVT i_1_0_1005 (.A(n_1_0_957), .B1(n_1_0_1279), .B2( + registers_27__ap[16]), .C1(registers_3__ap[16]), .C2(n_1_0_1257), .ZN( + n_1_0_956)); + NAND3_X1_LVT i_1_0_1004 (.A1(n_1_0_966), .A2(n_1_0_961), .A3(n_1_0_956), + .ZN(RRs1[16])); + AND2_X1_LVT i_0_0_15 (.A1(n_0_0_16), .A2(WRd[15]), .ZN(registers[15])); + SDFF_X1_LVT \registers_reg[17][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_17__ap[15]), .CK(n_0_47), .Q(registers_17__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[21][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_21__ap[15]), .CK(n_0_51), .Q(registers_21__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_1000 (.A1(registers_17__ap[15]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[15]), .ZN(n_1_0_952)); + SDFF_X1_LVT \registers_reg[10][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_10__ap[15]), .CK(n_0_40), .Q(registers_10__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[2][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_2__ap[15]), .CK(n_0_32), .Q(registers_2__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_1003 (.A1(registers_10__ap[15]), .A2(n_1_0_1287), .B1( + n_1_0_1268), .B2(registers_2__ap[15]), .ZN(n_1_0_955)); + SDFF_X1_LVT \registers_reg[20][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_20__ap[15]), .CK(n_0_50), .Q(registers_20__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[12][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_12__ap[15]), .CK(n_0_42), .Q(registers_12__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_999 (.A1(registers_20__ap[15]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[15]), .ZN(n_1_0_951)); + SDFF_X1_LVT \registers_reg[15][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_15__ap[15]), .CK(n_0_45), .Q(registers_15__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[8][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_8__ap[15]), .CK(n_0_38), .Q(registers_8__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_1002 (.A1(registers_15__ap[15]), .A2(n_1_0_1286), .B1( + n_1_0_1282), .B2(registers_8__ap[15]), .ZN(n_1_0_954)); + INV_X1_LVT i_1_0_1001 (.A(n_1_0_954), .ZN(n_1_0_953)); + SDFF_X1_LVT \registers_reg[11][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_11__ap[15]), .CK(n_0_41), .Q(registers_11__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[24][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_24__ap[15]), .CK(n_0_54), .Q(registers_24__ap[15]), .QN()); + AOI221_X1_LVT i_1_0_998 (.A(n_1_0_953), .B1(n_1_0_1270), .B2( + registers_11__ap[15]), .C1(registers_24__ap[15]), .C2(n_1_0_1289), + .ZN(n_1_0_950)); + SDFF_X1_LVT \registers_reg[13][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_13__ap[15]), .CK(n_0_43), .Q(registers_13__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[30][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_30__ap[15]), .CK(n_0_60), .Q(registers_30__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[22][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_22__ap[15]), .CK(n_0_52), .Q(registers_22__ap[15]), .QN()); + AOI222_X1_LVT i_1_0_997 (.A1(registers_13__ap[15]), .A2(n_1_0_1277), .B1( + n_1_0_1272), .B2(registers_30__ap[15]), .C1(registers_22__ap[15]), + .C2(n_1_0_1294), .ZN(n_1_0_949)); + NAND4_X1_LVT i_1_0_996 (.A1(n_1_0_955), .A2(n_1_0_951), .A3(n_1_0_950), + .A4(n_1_0_949), .ZN(n_1_0_948)); + SDFF_X1_LVT \registers_reg[1][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_1__ap[15]), .CK(n_0_0), .Q(registers_1__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[28][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_28__ap[15]), .CK(n_0_58), .Q(registers_28__ap[15]), .QN()); + AOI221_X1_LVT i_1_0_995 (.A(n_1_0_948), .B1(n_1_0_1274), .B2( + registers_1__ap[15]), .C1(registers_28__ap[15]), .C2(n_1_0_1283), .ZN( + n_1_0_947)); + SDFF_X1_LVT \registers_reg[18][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_18__ap[15]), .CK(n_0_48), .Q(registers_18__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[26][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_26__ap[15]), .CK(n_0_56), .Q(registers_26__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_994 (.A1(registers_18__ap[15]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[15]), .ZN(n_1_0_946)); + SDFF_X1_LVT \registers_reg[4][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_4__ap[15]), .CK(n_0_34), .Q(registers_4__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[5][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_5__ap[15]), .CK(n_0_35), .Q(registers_5__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_993 (.A1(registers_4__ap[15]), .A2(n_1_0_1278), .B1( + n_1_0_1273), .B2(registers_5__ap[15]), .ZN(n_1_0_945)); + SDFF_X1_LVT \registers_reg[6][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_6__ap[15]), .CK(n_0_36), .Q(registers_6__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[16][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_16__ap[15]), .CK(n_0_46), .Q(registers_16__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_992 (.A1(registers_6__ap[15]), .A2(n_1_0_1300), .B1( + n_1_0_1267), .B2(registers_16__ap[15]), .ZN(n_1_0_944)); + NAND3_X1_LVT i_1_0_991 (.A1(n_1_0_946), .A2(n_1_0_945), .A3(n_1_0_944), + .ZN(n_1_0_943)); + SDFF_X1_LVT \registers_reg[19][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_19__ap[15]), .CK(n_0_49), .Q(registers_19__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[25][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_25__ap[15]), .CK(n_0_55), .Q(registers_25__ap[15]), .QN()); + AOI221_X1_LVT i_1_0_990 (.A(n_1_0_943), .B1(n_1_0_1295), .B2( + registers_19__ap[15]), .C1(registers_25__ap[15]), .C2(n_1_0_1269), + .ZN(n_1_0_942)); + SDFF_X1_LVT \registers_reg[7][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_7__ap[15]), .CK(n_0_37), .Q(registers_7__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[14][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_14__ap[15]), .CK(n_0_44), .Q(registers_14__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_989 (.A1(registers_7__ap[15]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[15]), .ZN(n_1_0_941)); + SDFF_X1_LVT \registers_reg[9][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_9__ap[15]), .CK(n_0_39), .Q(registers_9__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[29][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_29__ap[15]), .CK(n_0_59), .Q(registers_29__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_988 (.A1(registers_9__ap[15]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[15]), .ZN(n_1_0_940)); + SDFF_X1_LVT \registers_reg[23][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_23__ap[15]), .CK(n_0_53), .Q(registers_23__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[3][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_3__ap[15]), .CK(n_0_33), .Q(registers_3__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_987 (.A1(registers_23__ap[15]), .A2(n_1_0_1264), .B1( + n_1_0_1257), .B2(registers_3__ap[15]), .ZN(n_1_0_939)); + NAND3_X1_LVT i_1_0_986 (.A1(n_1_0_941), .A2(n_1_0_940), .A3(n_1_0_939), + .ZN(n_1_0_938)); + SDFF_X1_LVT \registers_reg[27][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_27__ap[15]), .CK(n_0_57), .Q(registers_27__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[31][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_31__ap[15]), .CK(n_0_61), .Q(registers_31__ap[15]), .QN()); + AOI221_X1_LVT i_1_0_985 (.A(n_1_0_938), .B1(n_1_0_1279), .B2( + registers_27__ap[15]), .C1(registers_31__ap[15]), .C2(n_1_0_1266), + .ZN(n_1_0_937)); + NAND4_X1_LVT i_1_0_984 (.A1(n_1_0_952), .A2(n_1_0_947), .A3(n_1_0_942), + .A4(n_1_0_937), .ZN(RRs1[15])); + AND2_X1_LVT i_0_0_14 (.A1(n_0_0_16), .A2(WRd[14]), .ZN(registers[14])); + SDFF_X1_LVT \registers_reg[28][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_28__ap[14]), .CK(n_0_58), .Q(registers_28__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[5][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_5__ap[14]), .CK(n_0_35), .Q(registers_5__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_983 (.A1(registers_28__ap[14]), .A2(n_1_0_1283), .B1( + n_1_0_1273), .B2(registers_5__ap[14]), .ZN(n_1_0_936)); + SDFF_X1_LVT \registers_reg[18][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_18__ap[14]), .CK(n_0_48), .Q(registers_18__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[10][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_10__ap[14]), .CK(n_0_40), .Q(registers_10__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[8][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_8__ap[14]), .CK(n_0_38), .Q(registers_8__ap[14]), .QN()); + AOI222_X1_LVT i_1_0_982 (.A1(registers_18__ap[14]), .A2(n_1_0_1297), .B1( + n_1_0_1287), .B2(registers_10__ap[14]), .C1(n_1_0_1282), .C2( + registers_8__ap[14]), .ZN(n_1_0_935)); + SDFF_X1_LVT \registers_reg[9][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_9__ap[14]), .CK(n_0_39), .Q(registers_9__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[29][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_29__ap[14]), .CK(n_0_59), .Q(registers_29__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_981 (.A1(registers_9__ap[14]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[14]), .ZN(n_1_0_934)); + SDFF_X1_LVT \registers_reg[21][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_21__ap[14]), .CK(n_0_51), .Q(registers_21__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[14][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_14__ap[14]), .CK(n_0_44), .Q(registers_14__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_980 (.A1(registers_21__ap[14]), .A2(n_1_0_1259), .B1( + n_1_0_1258), .B2(registers_14__ap[14]), .ZN(n_1_0_933)); + SDFF_X1_LVT \registers_reg[16][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_16__ap[14]), .CK(n_0_46), .Q(registers_16__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[3][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_3__ap[14]), .CK(n_0_33), .Q(registers_3__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_979 (.A1(registers_16__ap[14]), .A2(n_1_0_1267), .B1( + n_1_0_1257), .B2(registers_3__ap[14]), .ZN(n_1_0_932)); + SDFF_X1_LVT \registers_reg[17][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_17__ap[14]), .CK(n_0_47), .Q(registers_17__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[31][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_31__ap[14]), .CK(n_0_61), .Q(registers_31__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_978 (.A1(registers_17__ap[14]), .A2(n_1_0_1271), .B1( + n_1_0_1266), .B2(registers_31__ap[14]), .ZN(n_1_0_931)); + SDFF_X1_LVT \registers_reg[15][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_15__ap[14]), .CK(n_0_45), .Q(registers_15__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[23][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_23__ap[14]), .CK(n_0_53), .Q(registers_23__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_977 (.A1(registers_15__ap[14]), .A2(n_1_0_1286), .B1( + n_1_0_1264), .B2(registers_23__ap[14]), .ZN(n_1_0_930)); + NAND4_X1_LVT i_1_0_976 (.A1(n_1_0_933), .A2(n_1_0_932), .A3(n_1_0_931), + .A4(n_1_0_930), .ZN(n_1_0_929)); + SDFF_X1_LVT \registers_reg[26][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_26__ap[14]), .CK(n_0_56), .Q(registers_26__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[30][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_30__ap[14]), .CK(n_0_60), .Q(registers_30__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_975 (.A1(registers_26__ap[14]), .A2(n_1_0_1285), .B1( + n_1_0_1272), .B2(registers_30__ap[14]), .ZN(n_1_0_928)); + SDFF_X1_LVT \registers_reg[20][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_20__ap[14]), .CK(n_0_50), .Q(registers_20__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[4][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_4__ap[14]), .CK(n_0_34), .Q(registers_4__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_974 (.A1(registers_20__ap[14]), .A2(n_1_0_1281), .B1( + n_1_0_1278), .B2(registers_4__ap[14]), .ZN(n_1_0_927)); + SDFF_X1_LVT \registers_reg[1][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_1__ap[14]), .CK(n_0_0), .Q(registers_1__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[2][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_2__ap[14]), .CK(n_0_32), .Q(registers_2__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_973 (.A1(registers_1__ap[14]), .A2(n_1_0_1274), .B1( + n_1_0_1268), .B2(registers_2__ap[14]), .ZN(n_1_0_926)); + SDFF_X1_LVT \registers_reg[24][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_24__ap[14]), .CK(n_0_54), .Q(registers_24__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[12][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_12__ap[14]), .CK(n_0_42), .Q(registers_12__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_972 (.A1(registers_24__ap[14]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[14]), .ZN(n_1_0_925)); + NAND4_X1_LVT i_1_0_971 (.A1(n_1_0_928), .A2(n_1_0_927), .A3(n_1_0_926), + .A4(n_1_0_925), .ZN(n_1_0_924)); + SDFF_X1_LVT \registers_reg[19][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_19__ap[14]), .CK(n_0_49), .Q(registers_19__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[22][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_22__ap[14]), .CK(n_0_52), .Q(registers_22__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_970 (.A1(registers_19__ap[14]), .A2(n_1_0_1295), .B1( + n_1_0_1294), .B2(registers_22__ap[14]), .ZN(n_1_0_923)); + SDFF_X1_LVT \registers_reg[13][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_13__ap[14]), .CK(n_0_43), .Q(registers_13__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[25][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_25__ap[14]), .CK(n_0_55), .Q(registers_25__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_969 (.A1(registers_13__ap[14]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[14]), .ZN(n_1_0_922)); + SDFF_X1_LVT \registers_reg[6][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_6__ap[14]), .CK(n_0_36), .Q(registers_6__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[7][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_7__ap[14]), .CK(n_0_37), .Q(registers_7__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_968 (.A1(registers_6__ap[14]), .A2(n_1_0_1300), .B1( + n_1_0_1263), .B2(registers_7__ap[14]), .ZN(n_1_0_921)); + SDFF_X1_LVT \registers_reg[27][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_27__ap[14]), .CK(n_0_57), .Q(registers_27__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[11][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_11__ap[14]), .CK(n_0_41), .Q(registers_11__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_967 (.A1(registers_27__ap[14]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[14]), .ZN(n_1_0_920)); + NAND4_X1_LVT i_1_0_966 (.A1(n_1_0_923), .A2(n_1_0_922), .A3(n_1_0_921), + .A4(n_1_0_920), .ZN(n_1_0_919)); + NOR3_X1_LVT i_1_0_965 (.A1(n_1_0_929), .A2(n_1_0_924), .A3(n_1_0_919), + .ZN(n_1_0_918)); + NAND4_X1_LVT i_1_0_964 (.A1(n_1_0_936), .A2(n_1_0_935), .A3(n_1_0_934), + .A4(n_1_0_918), .ZN(RRs1[14])); + AND2_X1_LVT i_0_0_13 (.A1(n_0_0_16), .A2(WRd[13]), .ZN(registers[13])); + SDFF_X1_LVT \registers_reg[28][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_28__ap[13]), .CK(n_0_58), .Q(registers_28__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[4][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_4__ap[13]), .CK(n_0_34), .Q(registers_4__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_963 (.A1(registers_28__ap[13]), .A2(n_1_0_1283), .B1( + n_1_0_1278), .B2(registers_4__ap[13]), .ZN(n_1_0_917)); + SDFF_X1_LVT \registers_reg[10][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_10__ap[13]), .CK(n_0_40), .Q(registers_10__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[26][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_26__ap[13]), .CK(n_0_56), .Q(registers_26__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[8][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_8__ap[13]), .CK(n_0_38), .Q(registers_8__ap[13]), .QN()); + AOI222_X1_LVT i_1_0_962 (.A1(registers_10__ap[13]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[13]), .C1(registers_8__ap[13]), .C2( + n_1_0_1282), .ZN(n_1_0_916)); + SDFF_X1_LVT \registers_reg[9][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_9__ap[13]), .CK(n_0_39), .Q(registers_9__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[29][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_29__ap[13]), .CK(n_0_59), .Q(registers_29__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_961 (.A1(registers_9__ap[13]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[13]), .ZN(n_1_0_915)); + SDFF_X1_LVT \registers_reg[6][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_6__ap[13]), .CK(n_0_36), .Q(registers_6__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[1][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_1__ap[13]), .CK(n_0_0), .Q(registers_1__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_960 (.A1(registers_6__ap[13]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[13]), .ZN(n_1_0_914)); + SDFF_X1_LVT \registers_reg[5][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_5__ap[13]), .CK(n_0_35), .Q(registers_5__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[3][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_3__ap[13]), .CK(n_0_33), .Q(registers_3__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_959 (.A1(registers_5__ap[13]), .A2(n_1_0_1273), .B1( + n_1_0_1257), .B2(registers_3__ap[13]), .ZN(n_1_0_913)); + SDFF_X1_LVT \registers_reg[16][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_16__ap[13]), .CK(n_0_46), .Q(registers_16__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[31][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_31__ap[13]), .CK(n_0_61), .Q(registers_31__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_958 (.A1(registers_16__ap[13]), .A2(n_1_0_1267), .B1( + n_1_0_1266), .B2(registers_31__ap[13]), .ZN(n_1_0_912)); + SDFF_X1_LVT \registers_reg[15][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_15__ap[13]), .CK(n_0_45), .Q(registers_15__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[23][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_23__ap[13]), .CK(n_0_53), .Q(registers_23__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_957 (.A1(registers_15__ap[13]), .A2(n_1_0_1286), .B1( + n_1_0_1264), .B2(registers_23__ap[13]), .ZN(n_1_0_911)); + NAND4_X1_LVT i_1_0_956 (.A1(n_1_0_914), .A2(n_1_0_913), .A3(n_1_0_912), + .A4(n_1_0_911), .ZN(n_1_0_910)); + SDFF_X1_LVT \registers_reg[18][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_18__ap[13]), .CK(n_0_48), .Q(registers_18__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[30][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_30__ap[13]), .CK(n_0_60), .Q(registers_30__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_955 (.A1(registers_18__ap[13]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[13]), .ZN(n_1_0_909)); + SDFF_X1_LVT \registers_reg[24][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_24__ap[13]), .CK(n_0_54), .Q(registers_24__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[12][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_12__ap[13]), .CK(n_0_42), .Q(registers_12__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_954 (.A1(registers_24__ap[13]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[13]), .ZN(n_1_0_908)); + SDFF_X1_LVT \registers_reg[22][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_22__ap[13]), .CK(n_0_52), .Q(registers_22__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[21][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_21__ap[13]), .CK(n_0_51), .Q(registers_21__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_953 (.A1(registers_22__ap[13]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[13]), .ZN(n_1_0_907)); + SDFF_X1_LVT \registers_reg[20][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_20__ap[13]), .CK(n_0_50), .Q(registers_20__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[17][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_17__ap[13]), .CK(n_0_47), .Q(registers_17__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_952 (.A1(registers_20__ap[13]), .A2(n_1_0_1281), .B1( + n_1_0_1271), .B2(registers_17__ap[13]), .ZN(n_1_0_906)); + NAND4_X1_LVT i_1_0_951 (.A1(n_1_0_909), .A2(n_1_0_908), .A3(n_1_0_907), + .A4(n_1_0_906), .ZN(n_1_0_905)); + SDFF_X1_LVT \registers_reg[13][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_13__ap[13]), .CK(n_0_43), .Q(registers_13__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[25][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_25__ap[13]), .CK(n_0_55), .Q(registers_25__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_950 (.A1(registers_13__ap[13]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[13]), .ZN(n_1_0_904)); + SDFF_X1_LVT \registers_reg[19][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_19__ap[13]), .CK(n_0_49), .Q(registers_19__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[2][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_2__ap[13]), .CK(n_0_32), .Q(registers_2__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_949 (.A1(registers_19__ap[13]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[13]), .ZN(n_1_0_903)); + SDFF_X1_LVT \registers_reg[7][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_7__ap[13]), .CK(n_0_37), .Q(registers_7__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[14][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_14__ap[13]), .CK(n_0_44), .Q(registers_14__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_948 (.A1(registers_7__ap[13]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[13]), .ZN(n_1_0_902)); + SDFF_X1_LVT \registers_reg[27][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_27__ap[13]), .CK(n_0_57), .Q(registers_27__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[11][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_11__ap[13]), .CK(n_0_41), .Q(registers_11__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_947 (.A1(registers_27__ap[13]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[13]), .ZN(n_1_0_901)); + NAND4_X1_LVT i_1_0_946 (.A1(n_1_0_904), .A2(n_1_0_903), .A3(n_1_0_902), + .A4(n_1_0_901), .ZN(n_1_0_900)); + NOR3_X1_LVT i_1_0_945 (.A1(n_1_0_910), .A2(n_1_0_905), .A3(n_1_0_900), + .ZN(n_1_0_899)); + NAND4_X1_LVT i_1_0_944 (.A1(n_1_0_917), .A2(n_1_0_916), .A3(n_1_0_915), + .A4(n_1_0_899), .ZN(RRs1[13])); + AND2_X1_LVT i_0_0_12 (.A1(n_0_0_16), .A2(WRd[12]), .ZN(registers[12])); + SDFF_X1_LVT \registers_reg[28][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_28__ap[12]), .CK(n_0_58), .Q(registers_28__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[17][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_17__ap[12]), .CK(n_0_47), .Q(registers_17__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_943 (.A1(registers_28__ap[12]), .A2(n_1_0_1283), .B1( + n_1_0_1271), .B2(registers_17__ap[12]), .ZN(n_1_0_898)); + SDFF_X1_LVT \registers_reg[10][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_10__ap[12]), .CK(n_0_40), .Q(registers_10__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[26][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_26__ap[12]), .CK(n_0_56), .Q(registers_26__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[8][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_8__ap[12]), .CK(n_0_38), .Q(registers_8__ap[12]), .QN()); + AOI222_X1_LVT i_1_0_942 (.A1(registers_10__ap[12]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[12]), .C1(registers_8__ap[12]), .C2( + n_1_0_1282), .ZN(n_1_0_897)); + SDFF_X1_LVT \registers_reg[9][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_9__ap[12]), .CK(n_0_39), .Q(registers_9__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[29][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_29__ap[12]), .CK(n_0_59), .Q(registers_29__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_941 (.A1(registers_9__ap[12]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[12]), .ZN(n_1_0_896)); + SDFF_X1_LVT \registers_reg[6][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_6__ap[12]), .CK(n_0_36), .Q(registers_6__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[1][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_1__ap[12]), .CK(n_0_0), .Q(registers_1__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_940 (.A1(registers_6__ap[12]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[12]), .ZN(n_1_0_895)); + SDFF_X1_LVT \registers_reg[16][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_16__ap[12]), .CK(n_0_46), .Q(registers_16__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[3][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_3__ap[12]), .CK(n_0_33), .Q(registers_3__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_939 (.A1(registers_16__ap[12]), .A2(n_1_0_1267), .B1( + n_1_0_1257), .B2(registers_3__ap[12]), .ZN(n_1_0_894)); + SDFF_X1_LVT \registers_reg[5][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_5__ap[12]), .CK(n_0_35), .Q(registers_5__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[31][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_31__ap[12]), .CK(n_0_61), .Q(registers_31__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_938 (.A1(registers_5__ap[12]), .A2(n_1_0_1273), .B1( + n_1_0_1266), .B2(registers_31__ap[12]), .ZN(n_1_0_893)); + SDFF_X1_LVT \registers_reg[15][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_15__ap[12]), .CK(n_0_45), .Q(registers_15__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[23][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_23__ap[12]), .CK(n_0_53), .Q(registers_23__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_937 (.A1(registers_15__ap[12]), .A2(n_1_0_1286), .B1( + n_1_0_1264), .B2(registers_23__ap[12]), .ZN(n_1_0_892)); + NAND4_X1_LVT i_1_0_936 (.A1(n_1_0_895), .A2(n_1_0_894), .A3(n_1_0_893), + .A4(n_1_0_892), .ZN(n_1_0_891)); + SDFF_X1_LVT \registers_reg[18][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_18__ap[12]), .CK(n_0_48), .Q(registers_18__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[30][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_30__ap[12]), .CK(n_0_60), .Q(registers_30__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_935 (.A1(registers_18__ap[12]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[12]), .ZN(n_1_0_890)); + SDFF_X1_LVT \registers_reg[20][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_20__ap[12]), .CK(n_0_50), .Q(registers_20__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[4][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_4__ap[12]), .CK(n_0_34), .Q(registers_4__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_934 (.A1(registers_20__ap[12]), .A2(n_1_0_1281), .B1( + n_1_0_1278), .B2(registers_4__ap[12]), .ZN(n_1_0_889)); + SDFF_X1_LVT \registers_reg[22][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_22__ap[12]), .CK(n_0_52), .Q(registers_22__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[21][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_21__ap[12]), .CK(n_0_51), .Q(registers_21__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_933 (.A1(registers_22__ap[12]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[12]), .ZN(n_1_0_888)); + SDFF_X1_LVT \registers_reg[24][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_24__ap[12]), .CK(n_0_54), .Q(registers_24__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[12][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_12__ap[12]), .CK(n_0_42), .Q(registers_12__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_932 (.A1(registers_24__ap[12]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[12]), .ZN(n_1_0_887)); + NAND4_X1_LVT i_1_0_931 (.A1(n_1_0_890), .A2(n_1_0_889), .A3(n_1_0_888), + .A4(n_1_0_887), .ZN(n_1_0_886)); + SDFF_X1_LVT \registers_reg[13][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_13__ap[12]), .CK(n_0_43), .Q(registers_13__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[25][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_25__ap[12]), .CK(n_0_55), .Q(registers_25__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_930 (.A1(registers_13__ap[12]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[12]), .ZN(n_1_0_885)); + SDFF_X1_LVT \registers_reg[19][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_19__ap[12]), .CK(n_0_49), .Q(registers_19__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[2][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_2__ap[12]), .CK(n_0_32), .Q(registers_2__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_929 (.A1(registers_19__ap[12]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[12]), .ZN(n_1_0_884)); + SDFF_X1_LVT \registers_reg[7][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_7__ap[12]), .CK(n_0_37), .Q(registers_7__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[14][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_14__ap[12]), .CK(n_0_44), .Q(registers_14__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_928 (.A1(registers_7__ap[12]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[12]), .ZN(n_1_0_883)); + SDFF_X1_LVT \registers_reg[27][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_27__ap[12]), .CK(n_0_57), .Q(registers_27__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[11][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_11__ap[12]), .CK(n_0_41), .Q(registers_11__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_927 (.A1(registers_27__ap[12]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[12]), .ZN(n_1_0_882)); + NAND4_X1_LVT i_1_0_926 (.A1(n_1_0_885), .A2(n_1_0_884), .A3(n_1_0_883), + .A4(n_1_0_882), .ZN(n_1_0_881)); + NOR3_X1_LVT i_1_0_925 (.A1(n_1_0_891), .A2(n_1_0_886), .A3(n_1_0_881), + .ZN(n_1_0_880)); + NAND4_X1_LVT i_1_0_924 (.A1(n_1_0_898), .A2(n_1_0_897), .A3(n_1_0_896), + .A4(n_1_0_880), .ZN(RRs1[12])); + AND2_X1_LVT i_0_0_11 (.A1(n_0_0_16), .A2(WRd[11]), .ZN(registers[11])); + SDFF_X1_LVT \registers_reg[28][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_28__ap[11]), .CK(n_0_58), .Q(registers_28__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[17][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_17__ap[11]), .CK(n_0_47), .Q(registers_17__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_923 (.A1(registers_28__ap[11]), .A2(n_1_0_1283), .B1( + n_1_0_1271), .B2(registers_17__ap[11]), .ZN(n_1_0_879)); + SDFF_X1_LVT \registers_reg[10][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_10__ap[11]), .CK(n_0_40), .Q(registers_10__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[26][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_26__ap[11]), .CK(n_0_56), .Q(registers_26__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[8][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_8__ap[11]), .CK(n_0_38), .Q(registers_8__ap[11]), .QN()); + AOI222_X1_LVT i_1_0_922 (.A1(registers_10__ap[11]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[11]), .C1(registers_8__ap[11]), .C2( + n_1_0_1282), .ZN(n_1_0_878)); + SDFF_X1_LVT \registers_reg[9][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_9__ap[11]), .CK(n_0_39), .Q(registers_9__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[29][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_29__ap[11]), .CK(n_0_59), .Q(registers_29__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_921 (.A1(registers_9__ap[11]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[11]), .ZN(n_1_0_877)); + SDFF_X1_LVT \registers_reg[6][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_6__ap[11]), .CK(n_0_36), .Q(registers_6__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[1][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_1__ap[11]), .CK(n_0_0), .Q(registers_1__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_920 (.A1(registers_6__ap[11]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[11]), .ZN(n_1_0_876)); + SDFF_X1_LVT \registers_reg[5][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_5__ap[11]), .CK(n_0_35), .Q(registers_5__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[3][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_3__ap[11]), .CK(n_0_33), .Q(registers_3__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_919 (.A1(registers_5__ap[11]), .A2(n_1_0_1273), .B1( + n_1_0_1257), .B2(registers_3__ap[11]), .ZN(n_1_0_875)); + SDFF_X1_LVT \registers_reg[16][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_16__ap[11]), .CK(n_0_46), .Q(registers_16__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[31][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_31__ap[11]), .CK(n_0_61), .Q(registers_31__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_918 (.A1(registers_16__ap[11]), .A2(n_1_0_1267), .B1( + n_1_0_1266), .B2(registers_31__ap[11]), .ZN(n_1_0_874)); + SDFF_X1_LVT \registers_reg[15][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_15__ap[11]), .CK(n_0_45), .Q(registers_15__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[23][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_23__ap[11]), .CK(n_0_53), .Q(registers_23__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_917 (.A1(registers_15__ap[11]), .A2(n_1_0_1286), .B1( + n_1_0_1264), .B2(registers_23__ap[11]), .ZN(n_1_0_873)); + NAND4_X1_LVT i_1_0_916 (.A1(n_1_0_876), .A2(n_1_0_875), .A3(n_1_0_874), + .A4(n_1_0_873), .ZN(n_1_0_872)); + SDFF_X1_LVT \registers_reg[18][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_18__ap[11]), .CK(n_0_48), .Q(registers_18__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[30][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_30__ap[11]), .CK(n_0_60), .Q(registers_30__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_915 (.A1(registers_18__ap[11]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[11]), .ZN(n_1_0_871)); + SDFF_X1_LVT \registers_reg[20][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_20__ap[11]), .CK(n_0_50), .Q(registers_20__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[4][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_4__ap[11]), .CK(n_0_34), .Q(registers_4__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_914 (.A1(registers_20__ap[11]), .A2(n_1_0_1281), .B1( + n_1_0_1278), .B2(registers_4__ap[11]), .ZN(n_1_0_870)); + SDFF_X1_LVT \registers_reg[22][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_22__ap[11]), .CK(n_0_52), .Q(registers_22__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[21][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_21__ap[11]), .CK(n_0_51), .Q(registers_21__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_913 (.A1(registers_22__ap[11]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[11]), .ZN(n_1_0_869)); + SDFF_X1_LVT \registers_reg[24][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_24__ap[11]), .CK(n_0_54), .Q(registers_24__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[12][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_12__ap[11]), .CK(n_0_42), .Q(registers_12__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_912 (.A1(registers_24__ap[11]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[11]), .ZN(n_1_0_868)); + NAND4_X1_LVT i_1_0_911 (.A1(n_1_0_871), .A2(n_1_0_870), .A3(n_1_0_869), + .A4(n_1_0_868), .ZN(n_1_0_867)); + SDFF_X1_LVT \registers_reg[13][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_13__ap[11]), .CK(n_0_43), .Q(registers_13__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[25][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_25__ap[11]), .CK(n_0_55), .Q(registers_25__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_910 (.A1(registers_13__ap[11]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[11]), .ZN(n_1_0_866)); + SDFF_X1_LVT \registers_reg[19][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_19__ap[11]), .CK(n_0_49), .Q(registers_19__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[2][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_2__ap[11]), .CK(n_0_32), .Q(registers_2__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_909 (.A1(registers_19__ap[11]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[11]), .ZN(n_1_0_865)); + SDFF_X1_LVT \registers_reg[7][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_7__ap[11]), .CK(n_0_37), .Q(registers_7__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[14][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_14__ap[11]), .CK(n_0_44), .Q(registers_14__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_908 (.A1(registers_7__ap[11]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[11]), .ZN(n_1_0_864)); + SDFF_X1_LVT \registers_reg[27][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_27__ap[11]), .CK(n_0_57), .Q(registers_27__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[11][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_11__ap[11]), .CK(n_0_41), .Q(registers_11__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_907 (.A1(registers_27__ap[11]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[11]), .ZN(n_1_0_863)); + NAND4_X1_LVT i_1_0_906 (.A1(n_1_0_866), .A2(n_1_0_865), .A3(n_1_0_864), + .A4(n_1_0_863), .ZN(n_1_0_862)); + NOR3_X1_LVT i_1_0_905 (.A1(n_1_0_872), .A2(n_1_0_867), .A3(n_1_0_862), + .ZN(n_1_0_861)); + NAND4_X1_LVT i_1_0_904 (.A1(n_1_0_879), .A2(n_1_0_878), .A3(n_1_0_877), + .A4(n_1_0_861), .ZN(RRs1[11])); + AND2_X1_LVT i_0_0_10 (.A1(n_0_0_16), .A2(WRd[10]), .ZN(registers[10])); + SDFF_X1_LVT \registers_reg[28][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_28__ap[10]), .CK(n_0_58), .Q(registers_28__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[8][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_8__ap[10]), .CK(n_0_38), .Q(registers_8__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_902 (.A1(registers_28__ap[10]), .A2(n_1_0_1283), .B1( + n_1_0_1282), .B2(registers_8__ap[10]), .ZN(n_1_0_859)); + SDFF_X1_LVT \registers_reg[31][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_31__ap[10]), .CK(n_0_61), .Q(registers_31__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[7][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_7__ap[10]), .CK(n_0_37), .Q(registers_7__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_903 (.A1(registers_31__ap[10]), .A2(n_1_0_1266), .B1( + n_1_0_1263), .B2(registers_7__ap[10]), .ZN(n_1_0_860)); + SDFF_X1_LVT \registers_reg[24][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_24__ap[10]), .CK(n_0_54), .Q(registers_24__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[20][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_20__ap[10]), .CK(n_0_50), .Q(registers_20__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_901 (.A1(registers_24__ap[10]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[10]), .ZN(n_1_0_858)); + SDFF_X1_LVT \registers_reg[4][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_4__ap[10]), .CK(n_0_34), .Q(registers_4__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[23][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_23__ap[10]), .CK(n_0_53), .Q(registers_23__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_900 (.A1(registers_4__ap[10]), .A2(n_1_0_1278), .B1( + n_1_0_1264), .B2(registers_23__ap[10]), .ZN(n_1_0_857)); + NAND3_X1_LVT i_1_0_899 (.A1(n_1_0_860), .A2(n_1_0_858), .A3(n_1_0_857), + .ZN(n_1_0_856)); + SDFF_X1_LVT \registers_reg[27][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_27__ap[10]), .CK(n_0_57), .Q(registers_27__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[29][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_29__ap[10]), .CK(n_0_59), .Q(registers_29__ap[10]), .QN()); + AOI221_X1_LVT i_1_0_898 (.A(n_1_0_856), .B1(n_1_0_1279), .B2( + registers_27__ap[10]), .C1(registers_29__ap[10]), .C2(n_1_0_1276), + .ZN(n_1_0_855)); + SDFF_X1_LVT \registers_reg[10][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_10__ap[10]), .CK(n_0_40), .Q(registers_10__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[30][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_30__ap[10]), .CK(n_0_60), .Q(registers_30__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[25][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_25__ap[10]), .CK(n_0_55), .Q(registers_25__ap[10]), .QN()); + AOI222_X1_LVT i_1_0_897 (.A1(registers_10__ap[10]), .A2(n_1_0_1287), .B1( + n_1_0_1272), .B2(registers_30__ap[10]), .C1(n_1_0_1269), .C2( + registers_25__ap[10]), .ZN(n_1_0_854)); + NAND3_X1_LVT i_1_0_896 (.A1(n_1_0_859), .A2(n_1_0_855), .A3(n_1_0_854), + .ZN(n_1_0_853)); + SDFF_X1_LVT \registers_reg[21][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_21__ap[10]), .CK(n_0_51), .Q(registers_21__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[13][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_13__ap[10]), .CK(n_0_43), .Q(registers_13__ap[10]), .QN()); + AOI221_X1_LVT i_1_0_895 (.A(n_1_0_853), .B1(n_1_0_1259), .B2( + registers_21__ap[10]), .C1(registers_13__ap[10]), .C2(n_1_0_1277), + .ZN(n_1_0_852)); + SDFF_X1_LVT \registers_reg[18][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_18__ap[10]), .CK(n_0_48), .Q(registers_18__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[26][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_26__ap[10]), .CK(n_0_56), .Q(registers_26__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_894 (.A1(registers_18__ap[10]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[10]), .ZN(n_1_0_851)); + SDFF_X1_LVT \registers_reg[17][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_17__ap[10]), .CK(n_0_47), .Q(registers_17__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[12][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_12__ap[10]), .CK(n_0_42), .Q(registers_12__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_893 (.A1(registers_17__ap[10]), .A2(n_1_0_1271), .B1( + n_1_0_1260), .B2(registers_12__ap[10]), .ZN(n_1_0_850)); + SDFF_X1_LVT \registers_reg[15][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_15__ap[10]), .CK(n_0_45), .Q(registers_15__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[5][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_5__ap[10]), .CK(n_0_35), .Q(registers_5__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_892 (.A1(registers_15__ap[10]), .A2(n_1_0_1286), .B1( + n_1_0_1273), .B2(registers_5__ap[10]), .ZN(n_1_0_849)); + NAND3_X1_LVT i_1_0_891 (.A1(n_1_0_851), .A2(n_1_0_850), .A3(n_1_0_849), + .ZN(n_1_0_848)); + SDFF_X1_LVT \registers_reg[22][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_22__ap[10]), .CK(n_0_52), .Q(registers_22__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[16][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_16__ap[10]), .CK(n_0_46), .Q(registers_16__ap[10]), .QN()); + AOI221_X1_LVT i_1_0_890 (.A(n_1_0_848), .B1(n_1_0_1294), .B2( + registers_22__ap[10]), .C1(registers_16__ap[10]), .C2(n_1_0_1267), + .ZN(n_1_0_847)); + SDFF_X1_LVT \registers_reg[9][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_9__ap[10]), .CK(n_0_39), .Q(registers_9__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[1][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_1__ap[10]), .CK(n_0_0), .Q(registers_1__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_889 (.A1(registers_9__ap[10]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[10]), .ZN(n_1_0_846)); + SDFF_X1_LVT \registers_reg[6][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_6__ap[10]), .CK(n_0_36), .Q(registers_6__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[14][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_14__ap[10]), .CK(n_0_44), .Q(registers_14__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_888 (.A1(registers_6__ap[10]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[10]), .ZN(n_1_0_845)); + SDFF_X1_LVT \registers_reg[19][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_19__ap[10]), .CK(n_0_49), .Q(registers_19__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[3][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_3__ap[10]), .CK(n_0_33), .Q(registers_3__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_887 (.A1(registers_19__ap[10]), .A2(n_1_0_1295), .B1( + n_1_0_1257), .B2(registers_3__ap[10]), .ZN(n_1_0_844)); + NAND3_X1_LVT i_1_0_886 (.A1(n_1_0_846), .A2(n_1_0_845), .A3(n_1_0_844), + .ZN(n_1_0_843)); + SDFF_X1_LVT \registers_reg[11][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_11__ap[10]), .CK(n_0_41), .Q(registers_11__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[2][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_2__ap[10]), .CK(n_0_32), .Q(registers_2__ap[10]), .QN()); + AOI221_X1_LVT i_1_0_885 (.A(n_1_0_843), .B1(n_1_0_1270), .B2( + registers_11__ap[10]), .C1(registers_2__ap[10]), .C2(n_1_0_1268), .ZN( + n_1_0_842)); + NAND3_X1_LVT i_1_0_884 (.A1(n_1_0_852), .A2(n_1_0_847), .A3(n_1_0_842), + .ZN(RRs1[10])); + AND2_X1_LVT i_0_0_9 (.A1(n_0_0_16), .A2(WRd[9]), .ZN(registers[9])); + SDFF_X1_LVT \registers_reg[13][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_13__ap[9]), .CK(n_0_43), .Q(registers_13__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[21][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_21__ap[9]), .CK(n_0_51), .Q(registers_21__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_880 (.A1(registers_13__ap[9]), .A2(n_1_0_1277), .B1( + n_1_0_1259), .B2(registers_21__ap[9]), .ZN(n_1_0_838)); + SDFF_X1_LVT \registers_reg[29][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_29__ap[9]), .CK(n_0_59), .Q(registers_29__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[23][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_23__ap[9]), .CK(n_0_53), .Q(registers_23__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_883 (.A1(registers_29__ap[9]), .A2(n_1_0_1276), .B1( + n_1_0_1264), .B2(registers_23__ap[9]), .ZN(n_1_0_841)); + SDFF_X1_LVT \registers_reg[24][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_24__ap[9]), .CK(n_0_54), .Q(registers_24__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[20][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_20__ap[9]), .CK(n_0_50), .Q(registers_20__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_879 (.A1(registers_24__ap[9]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[9]), .ZN(n_1_0_837)); + SDFF_X1_LVT \registers_reg[7][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_7__ap[9]), .CK(n_0_37), .Q(registers_7__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[3][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_3__ap[9]), .CK(n_0_33), .Q(registers_3__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_882 (.A1(registers_7__ap[9]), .A2(n_1_0_1263), .B1( + n_1_0_1257), .B2(registers_3__ap[9]), .ZN(n_1_0_840)); + INV_X1_LVT i_1_0_881 (.A(n_1_0_840), .ZN(n_1_0_839)); + SDFF_X1_LVT \registers_reg[31][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_31__ap[9]), .CK(n_0_61), .Q(registers_31__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[4][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_4__ap[9]), .CK(n_0_34), .Q(registers_4__ap[9]), .QN()); + AOI221_X1_LVT i_1_0_878 (.A(n_1_0_839), .B1(n_1_0_1266), .B2( + registers_31__ap[9]), .C1(registers_4__ap[9]), .C2(n_1_0_1278), .ZN( + n_1_0_836)); + SDFF_X1_LVT \registers_reg[10][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_10__ap[9]), .CK(n_0_40), .Q(registers_10__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[26][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_26__ap[9]), .CK(n_0_56), .Q(registers_26__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[25][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_25__ap[9]), .CK(n_0_55), .Q(registers_25__ap[9]), .QN()); + AOI222_X1_LVT i_1_0_877 (.A1(registers_10__ap[9]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[9]), .C1(registers_25__ap[9]), .C2( + n_1_0_1269), .ZN(n_1_0_835)); + NAND4_X1_LVT i_1_0_876 (.A1(n_1_0_841), .A2(n_1_0_837), .A3(n_1_0_836), + .A4(n_1_0_835), .ZN(n_1_0_834)); + SDFF_X1_LVT \registers_reg[8][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_8__ap[9]), .CK(n_0_38), .Q(registers_8__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[28][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_28__ap[9]), .CK(n_0_58), .Q(registers_28__ap[9]), .QN()); + AOI221_X1_LVT i_1_0_875 (.A(n_1_0_834), .B1(n_1_0_1282), .B2( + registers_8__ap[9]), .C1(registers_28__ap[9]), .C2(n_1_0_1283), .ZN( + n_1_0_833)); + SDFF_X1_LVT \registers_reg[18][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_18__ap[9]), .CK(n_0_48), .Q(registers_18__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[30][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_30__ap[9]), .CK(n_0_60), .Q(registers_30__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_874 (.A1(registers_18__ap[9]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[9]), .ZN(n_1_0_832)); + SDFF_X1_LVT \registers_reg[17][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_17__ap[9]), .CK(n_0_47), .Q(registers_17__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[12][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_12__ap[9]), .CK(n_0_42), .Q(registers_12__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_873 (.A1(registers_17__ap[9]), .A2(n_1_0_1271), .B1( + n_1_0_1260), .B2(registers_12__ap[9]), .ZN(n_1_0_831)); + SDFF_X1_LVT \registers_reg[15][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_15__ap[9]), .CK(n_0_45), .Q(registers_15__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[5][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_5__ap[9]), .CK(n_0_35), .Q(registers_5__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_872 (.A1(registers_15__ap[9]), .A2(n_1_0_1286), .B1( + n_1_0_1273), .B2(registers_5__ap[9]), .ZN(n_1_0_830)); + NAND3_X1_LVT i_1_0_871 (.A1(n_1_0_832), .A2(n_1_0_831), .A3(n_1_0_830), + .ZN(n_1_0_829)); + SDFF_X1_LVT \registers_reg[22][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_22__ap[9]), .CK(n_0_52), .Q(registers_22__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[16][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_16__ap[9]), .CK(n_0_46), .Q(registers_16__ap[9]), .QN()); + AOI221_X1_LVT i_1_0_870 (.A(n_1_0_829), .B1(n_1_0_1294), .B2( + registers_22__ap[9]), .C1(registers_16__ap[9]), .C2(n_1_0_1267), .ZN( + n_1_0_828)); + SDFF_X1_LVT \registers_reg[9][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_9__ap[9]), .CK(n_0_39), .Q(registers_9__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[1][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_1__ap[9]), .CK(n_0_0), .Q(registers_1__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_869 (.A1(registers_9__ap[9]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[9]), .ZN(n_1_0_827)); + SDFF_X1_LVT \registers_reg[6][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_6__ap[9]), .CK(n_0_36), .Q(registers_6__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[14][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_14__ap[9]), .CK(n_0_44), .Q(registers_14__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_868 (.A1(registers_6__ap[9]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[9]), .ZN(n_1_0_826)); + SDFF_X1_LVT \registers_reg[19][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_19__ap[9]), .CK(n_0_49), .Q(registers_19__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[2][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_2__ap[9]), .CK(n_0_32), .Q(registers_2__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_867 (.A1(registers_19__ap[9]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[9]), .ZN(n_1_0_825)); + NAND3_X1_LVT i_1_0_866 (.A1(n_1_0_827), .A2(n_1_0_826), .A3(n_1_0_825), + .ZN(n_1_0_824)); + SDFF_X1_LVT \registers_reg[11][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_11__ap[9]), .CK(n_0_41), .Q(registers_11__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[27][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_27__ap[9]), .CK(n_0_57), .Q(registers_27__ap[9]), .QN()); + AOI221_X1_LVT i_1_0_865 (.A(n_1_0_824), .B1(n_1_0_1270), .B2( + registers_11__ap[9]), .C1(registers_27__ap[9]), .C2(n_1_0_1279), .ZN( + n_1_0_823)); + NAND4_X1_LVT i_1_0_864 (.A1(n_1_0_838), .A2(n_1_0_833), .A3(n_1_0_828), + .A4(n_1_0_823), .ZN(RRs1[9])); + AND2_X1_LVT i_0_0_8 (.A1(n_0_0_16), .A2(WRd[8]), .ZN(registers[8])); + SDFF_X1_LVT \registers_reg[13][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_13__ap[8]), .CK(n_0_43), .Q(registers_13__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[21][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_21__ap[8]), .CK(n_0_51), .Q(registers_21__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_860 (.A1(registers_13__ap[8]), .A2(n_1_0_1277), .B1( + n_1_0_1259), .B2(registers_21__ap[8]), .ZN(n_1_0_819)); + SDFF_X1_LVT \registers_reg[29][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_29__ap[8]), .CK(n_0_59), .Q(registers_29__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[23][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_23__ap[8]), .CK(n_0_53), .Q(registers_23__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_863 (.A1(registers_29__ap[8]), .A2(n_1_0_1276), .B1( + n_1_0_1264), .B2(registers_23__ap[8]), .ZN(n_1_0_822)); + SDFF_X1_LVT \registers_reg[24][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_24__ap[8]), .CK(n_0_54), .Q(registers_24__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[20][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_20__ap[8]), .CK(n_0_50), .Q(registers_20__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_859 (.A1(registers_24__ap[8]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[8]), .ZN(n_1_0_818)); + SDFF_X1_LVT \registers_reg[7][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_7__ap[8]), .CK(n_0_37), .Q(registers_7__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[3][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_3__ap[8]), .CK(n_0_33), .Q(registers_3__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_862 (.A1(registers_7__ap[8]), .A2(n_1_0_1263), .B1( + n_1_0_1257), .B2(registers_3__ap[8]), .ZN(n_1_0_821)); + INV_X1_LVT i_1_0_861 (.A(n_1_0_821), .ZN(n_1_0_820)); + SDFF_X1_LVT \registers_reg[31][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_31__ap[8]), .CK(n_0_61), .Q(registers_31__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[4][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_4__ap[8]), .CK(n_0_34), .Q(registers_4__ap[8]), .QN()); + AOI221_X1_LVT i_1_0_858 (.A(n_1_0_820), .B1(n_1_0_1266), .B2( + registers_31__ap[8]), .C1(registers_4__ap[8]), .C2(n_1_0_1278), .ZN( + n_1_0_817)); + SDFF_X1_LVT \registers_reg[10][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_10__ap[8]), .CK(n_0_40), .Q(registers_10__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[26][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_26__ap[8]), .CK(n_0_56), .Q(registers_26__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[25][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_25__ap[8]), .CK(n_0_55), .Q(registers_25__ap[8]), .QN()); + AOI222_X1_LVT i_1_0_857 (.A1(registers_10__ap[8]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[8]), .C1(registers_25__ap[8]), .C2( + n_1_0_1269), .ZN(n_1_0_816)); + NAND4_X1_LVT i_1_0_856 (.A1(n_1_0_822), .A2(n_1_0_818), .A3(n_1_0_817), + .A4(n_1_0_816), .ZN(n_1_0_815)); + SDFF_X1_LVT \registers_reg[8][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_8__ap[8]), .CK(n_0_38), .Q(registers_8__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[28][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_28__ap[8]), .CK(n_0_58), .Q(registers_28__ap[8]), .QN()); + AOI221_X1_LVT i_1_0_855 (.A(n_1_0_815), .B1(n_1_0_1282), .B2( + registers_8__ap[8]), .C1(registers_28__ap[8]), .C2(n_1_0_1283), .ZN( + n_1_0_814)); + SDFF_X1_LVT \registers_reg[18][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_18__ap[8]), .CK(n_0_48), .Q(registers_18__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[30][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_30__ap[8]), .CK(n_0_60), .Q(registers_30__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_854 (.A1(registers_18__ap[8]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[8]), .ZN(n_1_0_813)); + SDFF_X1_LVT \registers_reg[17][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_17__ap[8]), .CK(n_0_47), .Q(registers_17__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[12][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_12__ap[8]), .CK(n_0_42), .Q(registers_12__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_853 (.A1(registers_17__ap[8]), .A2(n_1_0_1271), .B1( + n_1_0_1260), .B2(registers_12__ap[8]), .ZN(n_1_0_812)); + SDFF_X1_LVT \registers_reg[15][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_15__ap[8]), .CK(n_0_45), .Q(registers_15__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[5][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_5__ap[8]), .CK(n_0_35), .Q(registers_5__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_852 (.A1(registers_15__ap[8]), .A2(n_1_0_1286), .B1( + n_1_0_1273), .B2(registers_5__ap[8]), .ZN(n_1_0_811)); + NAND3_X1_LVT i_1_0_851 (.A1(n_1_0_813), .A2(n_1_0_812), .A3(n_1_0_811), + .ZN(n_1_0_810)); + SDFF_X1_LVT \registers_reg[22][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_22__ap[8]), .CK(n_0_52), .Q(registers_22__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[16][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_16__ap[8]), .CK(n_0_46), .Q(registers_16__ap[8]), .QN()); + AOI221_X1_LVT i_1_0_850 (.A(n_1_0_810), .B1(n_1_0_1294), .B2( + registers_22__ap[8]), .C1(registers_16__ap[8]), .C2(n_1_0_1267), .ZN( + n_1_0_809)); + SDFF_X1_LVT \registers_reg[9][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_9__ap[8]), .CK(n_0_39), .Q(registers_9__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[1][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_1__ap[8]), .CK(n_0_0), .Q(registers_1__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_849 (.A1(registers_9__ap[8]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[8]), .ZN(n_1_0_808)); + SDFF_X1_LVT \registers_reg[6][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_6__ap[8]), .CK(n_0_36), .Q(registers_6__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[14][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_14__ap[8]), .CK(n_0_44), .Q(registers_14__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_848 (.A1(registers_6__ap[8]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[8]), .ZN(n_1_0_807)); + SDFF_X1_LVT \registers_reg[19][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_19__ap[8]), .CK(n_0_49), .Q(registers_19__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[2][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_2__ap[8]), .CK(n_0_32), .Q(registers_2__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_847 (.A1(registers_19__ap[8]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[8]), .ZN(n_1_0_806)); + NAND3_X1_LVT i_1_0_846 (.A1(n_1_0_808), .A2(n_1_0_807), .A3(n_1_0_806), + .ZN(n_1_0_805)); + SDFF_X1_LVT \registers_reg[11][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_11__ap[8]), .CK(n_0_41), .Q(registers_11__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[27][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_27__ap[8]), .CK(n_0_57), .Q(registers_27__ap[8]), .QN()); + AOI221_X1_LVT i_1_0_845 (.A(n_1_0_805), .B1(n_1_0_1270), .B2( + registers_11__ap[8]), .C1(registers_27__ap[8]), .C2(n_1_0_1279), .ZN( + n_1_0_804)); + NAND4_X1_LVT i_1_0_844 (.A1(n_1_0_819), .A2(n_1_0_814), .A3(n_1_0_809), + .A4(n_1_0_804), .ZN(RRs1[8])); + AND2_X1_LVT i_0_0_7 (.A1(n_0_0_16), .A2(WRd[7]), .ZN(registers[7])); + SDFF_X1_LVT \registers_reg[13][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_13__ap[7]), .CK(n_0_43), .Q(registers_13__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[21][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_21__ap[7]), .CK(n_0_51), .Q(registers_21__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_843 (.A1(registers_13__ap[7]), .A2(n_1_0_1277), .B1( + n_1_0_1259), .B2(registers_21__ap[7]), .ZN(n_1_0_803)); + SDFF_X1_LVT \registers_reg[18][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_18__ap[7]), .CK(n_0_48), .Q(registers_18__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[10][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_10__ap[7]), .CK(n_0_40), .Q(registers_10__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[25][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_25__ap[7]), .CK(n_0_55), .Q(registers_25__ap[7]), .QN()); + AOI222_X1_LVT i_1_0_842 (.A1(registers_18__ap[7]), .A2(n_1_0_1297), .B1( + n_1_0_1287), .B2(registers_10__ap[7]), .C1(registers_25__ap[7]), .C2( + n_1_0_1269), .ZN(n_1_0_802)); + SDFF_X1_LVT \registers_reg[28][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_28__ap[7]), .CK(n_0_58), .Q(registers_28__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[8][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_8__ap[7]), .CK(n_0_38), .Q(registers_8__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_841 (.A1(registers_28__ap[7]), .A2(n_1_0_1283), .B1( + n_1_0_1282), .B2(registers_8__ap[7]), .ZN(n_1_0_801)); + SDFF_X1_LVT \registers_reg[24][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_24__ap[7]), .CK(n_0_54), .Q(registers_24__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[20][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_20__ap[7]), .CK(n_0_50), .Q(registers_20__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_840 (.A1(registers_24__ap[7]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[7]), .ZN(n_1_0_800)); + SDFF_X1_LVT \registers_reg[31][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_31__ap[7]), .CK(n_0_61), .Q(registers_31__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[7][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_7__ap[7]), .CK(n_0_37), .Q(registers_7__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_839 (.A1(registers_31__ap[7]), .A2(n_1_0_1266), .B1( + n_1_0_1263), .B2(registers_7__ap[7]), .ZN(n_1_0_799)); + SDFF_X1_LVT \registers_reg[17][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_17__ap[7]), .CK(n_0_47), .Q(registers_17__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[11][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_11__ap[7]), .CK(n_0_41), .Q(registers_11__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_838 (.A1(registers_17__ap[7]), .A2(n_1_0_1271), .B1( + n_1_0_1270), .B2(registers_11__ap[7]), .ZN(n_1_0_798)); + SDFF_X1_LVT \registers_reg[27][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_27__ap[7]), .CK(n_0_57), .Q(registers_27__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[29][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_29__ap[7]), .CK(n_0_59), .Q(registers_29__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_837 (.A1(registers_27__ap[7]), .A2(n_1_0_1279), .B1( + n_1_0_1276), .B2(registers_29__ap[7]), .ZN(n_1_0_797)); + NAND4_X1_LVT i_1_0_836 (.A1(n_1_0_800), .A2(n_1_0_799), .A3(n_1_0_798), + .A4(n_1_0_797), .ZN(n_1_0_796)); + SDFF_X1_LVT \registers_reg[26][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_26__ap[7]), .CK(n_0_56), .Q(registers_26__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[30][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_30__ap[7]), .CK(n_0_60), .Q(registers_30__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_835 (.A1(registers_26__ap[7]), .A2(n_1_0_1285), .B1( + n_1_0_1272), .B2(registers_30__ap[7]), .ZN(n_1_0_795)); + SDFF_X1_LVT \registers_reg[4][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_4__ap[7]), .CK(n_0_34), .Q(registers_4__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[12][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_12__ap[7]), .CK(n_0_42), .Q(registers_12__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_834 (.A1(registers_4__ap[7]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[7]), .ZN(n_1_0_794)); + SDFF_X1_LVT \registers_reg[15][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_15__ap[7]), .CK(n_0_45), .Q(registers_15__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[16][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_16__ap[7]), .CK(n_0_46), .Q(registers_16__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_833 (.A1(registers_15__ap[7]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[7]), .ZN(n_1_0_793)); + SDFF_X1_LVT \registers_reg[22][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_22__ap[7]), .CK(n_0_52), .Q(registers_22__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[5][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_5__ap[7]), .CK(n_0_35), .Q(registers_5__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_832 (.A1(registers_22__ap[7]), .A2(n_1_0_1294), .B1( + n_1_0_1273), .B2(registers_5__ap[7]), .ZN(n_1_0_792)); + NAND4_X1_LVT i_1_0_831 (.A1(n_1_0_795), .A2(n_1_0_794), .A3(n_1_0_793), + .A4(n_1_0_792), .ZN(n_1_0_791)); + SDFF_X1_LVT \registers_reg[19][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_19__ap[7]), .CK(n_0_49), .Q(registers_19__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[3][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_3__ap[7]), .CK(n_0_33), .Q(registers_3__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_830 (.A1(registers_19__ap[7]), .A2(n_1_0_1295), .B1( + n_1_0_1257), .B2(registers_3__ap[7]), .ZN(n_1_0_790)); + SDFF_X1_LVT \registers_reg[9][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_9__ap[7]), .CK(n_0_39), .Q(registers_9__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[1][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_1__ap[7]), .CK(n_0_0), .Q(registers_1__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_829 (.A1(registers_9__ap[7]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[7]), .ZN(n_1_0_789)); + SDFF_X1_LVT \registers_reg[6][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_6__ap[7]), .CK(n_0_36), .Q(registers_6__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[14][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_14__ap[7]), .CK(n_0_44), .Q(registers_14__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_828 (.A1(registers_6__ap[7]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[7]), .ZN(n_1_0_788)); + SDFF_X1_LVT \registers_reg[2][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_2__ap[7]), .CK(n_0_32), .Q(registers_2__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[23][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_23__ap[7]), .CK(n_0_53), .Q(registers_23__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_827 (.A1(registers_2__ap[7]), .A2(n_1_0_1268), .B1( + n_1_0_1264), .B2(registers_23__ap[7]), .ZN(n_1_0_787)); + NAND4_X1_LVT i_1_0_826 (.A1(n_1_0_790), .A2(n_1_0_789), .A3(n_1_0_788), + .A4(n_1_0_787), .ZN(n_1_0_786)); + NOR3_X1_LVT i_1_0_825 (.A1(n_1_0_796), .A2(n_1_0_791), .A3(n_1_0_786), + .ZN(n_1_0_785)); + NAND4_X1_LVT i_1_0_824 (.A1(n_1_0_803), .A2(n_1_0_802), .A3(n_1_0_801), + .A4(n_1_0_785), .ZN(RRs1[7])); + AND2_X1_LVT i_0_0_6 (.A1(n_0_0_16), .A2(WRd[6]), .ZN(registers[6])); + SDFF_X1_LVT \registers_reg[28][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_28__ap[6]), .CK(n_0_58), .Q(registers_28__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[17][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_17__ap[6]), .CK(n_0_47), .Q(registers_17__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_823 (.A1(registers_28__ap[6]), .A2(n_1_0_1283), .B1( + n_1_0_1271), .B2(registers_17__ap[6]), .ZN(n_1_0_784)); + SDFF_X1_LVT \registers_reg[18][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_18__ap[6]), .CK(n_0_48), .Q(registers_18__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[10][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_10__ap[6]), .CK(n_0_40), .Q(registers_10__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[8][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_8__ap[6]), .CK(n_0_38), .Q(registers_8__ap[6]), .QN()); + AOI222_X1_LVT i_1_0_822 (.A1(registers_18__ap[6]), .A2(n_1_0_1297), .B1( + n_1_0_1287), .B2(registers_10__ap[6]), .C1(registers_8__ap[6]), .C2( + n_1_0_1282), .ZN(n_1_0_783)); + SDFF_X1_LVT \registers_reg[9][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_9__ap[6]), .CK(n_0_39), .Q(registers_9__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[29][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_29__ap[6]), .CK(n_0_59), .Q(registers_29__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_821 (.A1(registers_9__ap[6]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[6]), .ZN(n_1_0_782)); + SDFF_X1_LVT \registers_reg[6][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_6__ap[6]), .CK(n_0_36), .Q(registers_6__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[1][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_1__ap[6]), .CK(n_0_0), .Q(registers_1__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_820 (.A1(registers_6__ap[6]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[6]), .ZN(n_1_0_781)); + SDFF_X1_LVT \registers_reg[15][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_15__ap[6]), .CK(n_0_45), .Q(registers_15__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[27][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_27__ap[6]), .CK(n_0_57), .Q(registers_27__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_819 (.A1(registers_15__ap[6]), .A2(n_1_0_1286), .B1( + n_1_0_1279), .B2(registers_27__ap[6]), .ZN(n_1_0_780)); + SDFF_X1_LVT \registers_reg[11][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_11__ap[6]), .CK(n_0_41), .Q(registers_11__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[16][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_16__ap[6]), .CK(n_0_46), .Q(registers_16__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_818 (.A1(registers_11__ap[6]), .A2(n_1_0_1270), .B1( + n_1_0_1267), .B2(registers_16__ap[6]), .ZN(n_1_0_779)); + SDFF_X1_LVT \registers_reg[5][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_5__ap[6]), .CK(n_0_35), .Q(registers_5__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[31][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_31__ap[6]), .CK(n_0_61), .Q(registers_31__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_817 (.A1(registers_5__ap[6]), .A2(n_1_0_1273), .B1( + n_1_0_1266), .B2(registers_31__ap[6]), .ZN(n_1_0_778)); + NAND4_X1_LVT i_1_0_816 (.A1(n_1_0_781), .A2(n_1_0_780), .A3(n_1_0_779), + .A4(n_1_0_778), .ZN(n_1_0_777)); + SDFF_X1_LVT \registers_reg[26][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_26__ap[6]), .CK(n_0_56), .Q(registers_26__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[30][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_30__ap[6]), .CK(n_0_60), .Q(registers_30__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_815 (.A1(registers_26__ap[6]), .A2(n_1_0_1285), .B1( + n_1_0_1272), .B2(registers_30__ap[6]), .ZN(n_1_0_776)); + SDFF_X1_LVT \registers_reg[20][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_20__ap[6]), .CK(n_0_50), .Q(registers_20__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[4][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_4__ap[6]), .CK(n_0_34), .Q(registers_4__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_814 (.A1(registers_20__ap[6]), .A2(n_1_0_1281), .B1( + n_1_0_1278), .B2(registers_4__ap[6]), .ZN(n_1_0_775)); + SDFF_X1_LVT \registers_reg[22][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_22__ap[6]), .CK(n_0_52), .Q(registers_22__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[21][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_21__ap[6]), .CK(n_0_51), .Q(registers_21__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_813 (.A1(registers_22__ap[6]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[6]), .ZN(n_1_0_774)); + SDFF_X1_LVT \registers_reg[24][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_24__ap[6]), .CK(n_0_54), .Q(registers_24__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[12][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_12__ap[6]), .CK(n_0_42), .Q(registers_12__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_812 (.A1(registers_24__ap[6]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[6]), .ZN(n_1_0_773)); + NAND4_X1_LVT i_1_0_811 (.A1(n_1_0_776), .A2(n_1_0_775), .A3(n_1_0_774), + .A4(n_1_0_773), .ZN(n_1_0_772)); + SDFF_X1_LVT \registers_reg[13][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_13__ap[6]), .CK(n_0_43), .Q(registers_13__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[25][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_25__ap[6]), .CK(n_0_55), .Q(registers_25__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_810 (.A1(registers_13__ap[6]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[6]), .ZN(n_1_0_771)); + SDFF_X1_LVT \registers_reg[7][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_7__ap[6]), .CK(n_0_37), .Q(registers_7__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[14][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_14__ap[6]), .CK(n_0_44), .Q(registers_14__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_809 (.A1(registers_7__ap[6]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[6]), .ZN(n_1_0_770)); + SDFF_X1_LVT \registers_reg[19][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_19__ap[6]), .CK(n_0_49), .Q(registers_19__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[3][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_3__ap[6]), .CK(n_0_33), .Q(registers_3__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_808 (.A1(registers_19__ap[6]), .A2(n_1_0_1295), .B1( + n_1_0_1257), .B2(registers_3__ap[6]), .ZN(n_1_0_769)); + SDFF_X1_LVT \registers_reg[2][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_2__ap[6]), .CK(n_0_32), .Q(registers_2__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[23][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_23__ap[6]), .CK(n_0_53), .Q(registers_23__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_807 (.A1(registers_2__ap[6]), .A2(n_1_0_1268), .B1( + n_1_0_1264), .B2(registers_23__ap[6]), .ZN(n_1_0_768)); + NAND4_X1_LVT i_1_0_806 (.A1(n_1_0_771), .A2(n_1_0_770), .A3(n_1_0_769), + .A4(n_1_0_768), .ZN(n_1_0_767)); + NOR3_X1_LVT i_1_0_805 (.A1(n_1_0_777), .A2(n_1_0_772), .A3(n_1_0_767), + .ZN(n_1_0_766)); + NAND4_X1_LVT i_1_0_804 (.A1(n_1_0_784), .A2(n_1_0_783), .A3(n_1_0_782), + .A4(n_1_0_766), .ZN(RRs1[6])); + AND2_X1_LVT i_0_0_5 (.A1(n_0_0_16), .A2(WRd[5]), .ZN(registers[5])); + SDFF_X1_LVT \registers_reg[28][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_28__ap[5]), .CK(n_0_58), .Q(registers_28__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[4][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_4__ap[5]), .CK(n_0_34), .Q(registers_4__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_803 (.A1(registers_28__ap[5]), .A2(n_1_0_1283), .B1( + n_1_0_1278), .B2(registers_4__ap[5]), .ZN(n_1_0_765)); + SDFF_X1_LVT \registers_reg[10][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_10__ap[5]), .CK(n_0_40), .Q(registers_10__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[26][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_26__ap[5]), .CK(n_0_56), .Q(registers_26__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[8][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_8__ap[5]), .CK(n_0_38), .Q(registers_8__ap[5]), .QN()); + AOI222_X1_LVT i_1_0_802 (.A1(registers_10__ap[5]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[5]), .C1(registers_8__ap[5]), .C2( + n_1_0_1282), .ZN(n_1_0_764)); + SDFF_X1_LVT \registers_reg[9][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_9__ap[5]), .CK(n_0_39), .Q(registers_9__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[29][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_29__ap[5]), .CK(n_0_59), .Q(registers_29__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_801 (.A1(registers_9__ap[5]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[5]), .ZN(n_1_0_763)); + SDFF_X1_LVT \registers_reg[6][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_6__ap[5]), .CK(n_0_36), .Q(registers_6__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[1][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_1__ap[5]), .CK(n_0_0), .Q(registers_1__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_800 (.A1(registers_6__ap[5]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[5]), .ZN(n_1_0_762)); + SDFF_X1_LVT \registers_reg[16][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_16__ap[5]), .CK(n_0_46), .Q(registers_16__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[3][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_3__ap[5]), .CK(n_0_33), .Q(registers_3__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_799 (.A1(registers_16__ap[5]), .A2(n_1_0_1267), .B1( + n_1_0_1257), .B2(registers_3__ap[5]), .ZN(n_1_0_761)); + SDFF_X1_LVT \registers_reg[5][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_5__ap[5]), .CK(n_0_35), .Q(registers_5__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[31][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_31__ap[5]), .CK(n_0_61), .Q(registers_31__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_798 (.A1(registers_5__ap[5]), .A2(n_1_0_1273), .B1( + n_1_0_1266), .B2(registers_31__ap[5]), .ZN(n_1_0_760)); + SDFF_X1_LVT \registers_reg[15][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_15__ap[5]), .CK(n_0_45), .Q(registers_15__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[23][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_23__ap[5]), .CK(n_0_53), .Q(registers_23__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_797 (.A1(registers_15__ap[5]), .A2(n_1_0_1286), .B1( + n_1_0_1264), .B2(registers_23__ap[5]), .ZN(n_1_0_759)); + NAND4_X1_LVT i_1_0_796 (.A1(n_1_0_762), .A2(n_1_0_761), .A3(n_1_0_760), + .A4(n_1_0_759), .ZN(n_1_0_758)); + SDFF_X1_LVT \registers_reg[18][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_18__ap[5]), .CK(n_0_48), .Q(registers_18__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[30][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_30__ap[5]), .CK(n_0_60), .Q(registers_30__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_795 (.A1(registers_18__ap[5]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[5]), .ZN(n_1_0_757)); + SDFF_X1_LVT \registers_reg[24][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_24__ap[5]), .CK(n_0_54), .Q(registers_24__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[12][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_12__ap[5]), .CK(n_0_42), .Q(registers_12__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_794 (.A1(registers_24__ap[5]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[5]), .ZN(n_1_0_756)); + SDFF_X1_LVT \registers_reg[22][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_22__ap[5]), .CK(n_0_52), .Q(registers_22__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[21][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_21__ap[5]), .CK(n_0_51), .Q(registers_21__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_793 (.A1(registers_22__ap[5]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[5]), .ZN(n_1_0_755)); + SDFF_X1_LVT \registers_reg[20][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_20__ap[5]), .CK(n_0_50), .Q(registers_20__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[17][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_17__ap[5]), .CK(n_0_47), .Q(registers_17__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_792 (.A1(registers_20__ap[5]), .A2(n_1_0_1281), .B1( + n_1_0_1271), .B2(registers_17__ap[5]), .ZN(n_1_0_754)); + NAND4_X1_LVT i_1_0_791 (.A1(n_1_0_757), .A2(n_1_0_756), .A3(n_1_0_755), + .A4(n_1_0_754), .ZN(n_1_0_753)); + SDFF_X1_LVT \registers_reg[13][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_13__ap[5]), .CK(n_0_43), .Q(registers_13__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[25][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_25__ap[5]), .CK(n_0_55), .Q(registers_25__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_790 (.A1(registers_13__ap[5]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[5]), .ZN(n_1_0_752)); + SDFF_X1_LVT \registers_reg[19][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_19__ap[5]), .CK(n_0_49), .Q(registers_19__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[2][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_2__ap[5]), .CK(n_0_32), .Q(registers_2__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_789 (.A1(registers_19__ap[5]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[5]), .ZN(n_1_0_751)); + SDFF_X1_LVT \registers_reg[7][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_7__ap[5]), .CK(n_0_37), .Q(registers_7__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[14][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_14__ap[5]), .CK(n_0_44), .Q(registers_14__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_788 (.A1(registers_7__ap[5]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[5]), .ZN(n_1_0_750)); + SDFF_X1_LVT \registers_reg[27][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_27__ap[5]), .CK(n_0_57), .Q(registers_27__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[11][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_11__ap[5]), .CK(n_0_41), .Q(registers_11__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_787 (.A1(registers_27__ap[5]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[5]), .ZN(n_1_0_749)); + NAND4_X1_LVT i_1_0_786 (.A1(n_1_0_752), .A2(n_1_0_751), .A3(n_1_0_750), + .A4(n_1_0_749), .ZN(n_1_0_748)); + NOR3_X1_LVT i_1_0_785 (.A1(n_1_0_758), .A2(n_1_0_753), .A3(n_1_0_748), + .ZN(n_1_0_747)); + NAND4_X1_LVT i_1_0_784 (.A1(n_1_0_765), .A2(n_1_0_764), .A3(n_1_0_763), + .A4(n_1_0_747), .ZN(RRs1[5])); + AND2_X1_LVT i_0_0_4 (.A1(n_0_0_16), .A2(WRd[4]), .ZN(registers[4])); + SDFF_X1_LVT \registers_reg[10][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_10__ap[4]), .CK(n_0_40), .Q(registers_10__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[21][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_21__ap[4]), .CK(n_0_51), .Q(registers_21__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_783 (.A1(registers_10__ap[4]), .A2(n_1_0_1287), .B1( + n_1_0_1259), .B2(registers_21__ap[4]), .ZN(n_1_0_746)); + SDFF_X1_LVT \registers_reg[9][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_9__ap[4]), .CK(n_0_39), .Q(registers_9__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[1][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_1__ap[4]), .CK(n_0_0), .Q(registers_1__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_778 (.A1(registers_9__ap[4]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[4]), .ZN(n_1_0_741)); + SDFF_X1_LVT \registers_reg[18][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_18__ap[4]), .CK(n_0_48), .Q(registers_18__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[8][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_8__ap[4]), .CK(n_0_38), .Q(registers_8__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_777 (.A1(registers_18__ap[4]), .A2(n_1_0_1297), .B1( + n_1_0_1282), .B2(registers_8__ap[4]), .ZN(n_1_0_740)); + NAND3_X1_LVT i_1_0_775 (.A1(n_1_0_746), .A2(n_1_0_741), .A3(n_1_0_740), + .ZN(n_1_0_738)); + SDFF_X1_LVT \registers_reg[22][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_22__ap[4]), .CK(n_0_52), .Q(registers_22__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[23][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_23__ap[4]), .CK(n_0_53), .Q(registers_23__ap[4]), .QN()); + AOI221_X1_LVT i_1_0_774 (.A(n_1_0_738), .B1(n_1_0_1294), .B2( + registers_22__ap[4]), .C1(registers_23__ap[4]), .C2(n_1_0_1264), .ZN( + n_1_0_737)); + SDFF_X1_LVT \registers_reg[28][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_28__ap[4]), .CK(n_0_58), .Q(registers_28__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[20][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_20__ap[4]), .CK(n_0_50), .Q(registers_20__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_782 (.A1(registers_28__ap[4]), .A2(n_1_0_1283), .B1( + n_1_0_1281), .B2(registers_20__ap[4]), .ZN(n_1_0_745)); + SDFF_X1_LVT \registers_reg[19][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_19__ap[4]), .CK(n_0_49), .Q(registers_19__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[13][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_13__ap[4]), .CK(n_0_43), .Q(registers_13__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_780 (.A1(registers_19__ap[4]), .A2(n_1_0_1295), .B1( + n_1_0_1277), .B2(registers_13__ap[4]), .ZN(n_1_0_743)); + SDFF_X1_LVT \registers_reg[26][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_26__ap[4]), .CK(n_0_56), .Q(registers_26__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[3][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_3__ap[4]), .CK(n_0_33), .Q(registers_3__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_776 (.A1(registers_26__ap[4]), .A2(n_1_0_1285), .B1( + n_1_0_1257), .B2(registers_3__ap[4]), .ZN(n_1_0_739)); + NAND3_X1_LVT i_1_0_773 (.A1(n_1_0_745), .A2(n_1_0_743), .A3(n_1_0_739), + .ZN(n_1_0_736)); + SDFF_X1_LVT \registers_reg[30][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_30__ap[4]), .CK(n_0_60), .Q(registers_30__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[31][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_31__ap[4]), .CK(n_0_61), .Q(registers_31__ap[4]), .QN()); + AOI221_X1_LVT i_1_0_772 (.A(n_1_0_736), .B1(n_1_0_1272), .B2( + registers_30__ap[4]), .C1(registers_31__ap[4]), .C2(n_1_0_1266), .ZN( + n_1_0_735)); + SDFF_X1_LVT \registers_reg[24][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_24__ap[4]), .CK(n_0_54), .Q(registers_24__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[12][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_12__ap[4]), .CK(n_0_42), .Q(registers_12__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_781 (.A1(registers_24__ap[4]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[4]), .ZN(n_1_0_744)); + SDFF_X1_LVT \registers_reg[27][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_27__ap[4]), .CK(n_0_57), .Q(registers_27__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[11][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_11__ap[4]), .CK(n_0_41), .Q(registers_11__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_779 (.A1(registers_27__ap[4]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[4]), .ZN(n_1_0_742)); + SDFF_X1_LVT \registers_reg[17][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_17__ap[4]), .CK(n_0_47), .Q(registers_17__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[7][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_7__ap[4]), .CK(n_0_37), .Q(registers_7__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[14][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_14__ap[4]), .CK(n_0_44), .Q(registers_14__ap[4]), .QN()); + AOI222_X1_LVT i_1_0_771 (.A1(registers_17__ap[4]), .A2(n_1_0_1271), .B1( + n_1_0_1263), .B2(registers_7__ap[4]), .C1(n_1_0_1258), .C2( + registers_14__ap[4]), .ZN(n_1_0_734)); + SDFF_X1_LVT \registers_reg[15][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_15__ap[4]), .CK(n_0_45), .Q(registers_15__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[16][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_16__ap[4]), .CK(n_0_46), .Q(registers_16__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_770 (.A1(registers_15__ap[4]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[4]), .ZN(n_1_0_733)); + SDFF_X1_LVT \registers_reg[4][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_4__ap[4]), .CK(n_0_34), .Q(registers_4__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[25][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_25__ap[4]), .CK(n_0_55), .Q(registers_25__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_769 (.A1(registers_4__ap[4]), .A2(n_1_0_1278), .B1( + n_1_0_1269), .B2(registers_25__ap[4]), .ZN(n_1_0_732)); + SDFF_X1_LVT \registers_reg[29][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_29__ap[4]), .CK(n_0_59), .Q(registers_29__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[2][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_2__ap[4]), .CK(n_0_32), .Q(registers_2__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_768 (.A1(registers_29__ap[4]), .A2(n_1_0_1276), .B1( + n_1_0_1268), .B2(registers_2__ap[4]), .ZN(n_1_0_731)); + NAND3_X1_LVT i_1_0_767 (.A1(n_1_0_733), .A2(n_1_0_732), .A3(n_1_0_731), + .ZN(n_1_0_730)); + SDFF_X1_LVT \registers_reg[6][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_6__ap[4]), .CK(n_0_36), .Q(registers_6__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[5][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_5__ap[4]), .CK(n_0_35), .Q(registers_5__ap[4]), .QN()); + AOI221_X1_LVT i_1_0_766 (.A(n_1_0_730), .B1(n_1_0_1300), .B2( + registers_6__ap[4]), .C1(registers_5__ap[4]), .C2(n_1_0_1273), .ZN( + n_1_0_729)); + AND4_X1_LVT i_1_0_765 (.A1(n_1_0_744), .A2(n_1_0_742), .A3(n_1_0_734), + .A4(n_1_0_729), .ZN(n_1_0_728)); + NAND3_X1_LVT i_1_0_764 (.A1(n_1_0_737), .A2(n_1_0_735), .A3(n_1_0_728), + .ZN(RRs1[4])); + AND2_X1_LVT i_0_0_3 (.A1(n_0_0_16), .A2(WRd[3]), .ZN(registers[3])); + SDFF_X1_LVT \registers_reg[28][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_28__ap[3]), .CK(n_0_58), .Q(registers_28__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[17][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_17__ap[3]), .CK(n_0_47), .Q(registers_17__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_763 (.A1(registers_28__ap[3]), .A2(n_1_0_1283), .B1( + n_1_0_1271), .B2(registers_17__ap[3]), .ZN(n_1_0_727)); + SDFF_X1_LVT \registers_reg[10][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_10__ap[3]), .CK(n_0_40), .Q(registers_10__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[26][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_26__ap[3]), .CK(n_0_56), .Q(registers_26__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[8][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_8__ap[3]), .CK(n_0_38), .Q(registers_8__ap[3]), .QN()); + AOI222_X1_LVT i_1_0_762 (.A1(registers_10__ap[3]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[3]), .C1(registers_8__ap[3]), .C2( + n_1_0_1282), .ZN(n_1_0_726)); + SDFF_X1_LVT \registers_reg[9][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_9__ap[3]), .CK(n_0_39), .Q(registers_9__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[29][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_29__ap[3]), .CK(n_0_59), .Q(registers_29__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_761 (.A1(registers_9__ap[3]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[3]), .ZN(n_1_0_725)); + SDFF_X1_LVT \registers_reg[6][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_6__ap[3]), .CK(n_0_36), .Q(registers_6__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[1][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_1__ap[3]), .CK(n_0_0), .Q(registers_1__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_760 (.A1(registers_6__ap[3]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[3]), .ZN(n_1_0_724)); + SDFF_X1_LVT \registers_reg[16][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_16__ap[3]), .CK(n_0_46), .Q(registers_16__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[3][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_3__ap[3]), .CK(n_0_33), .Q(registers_3__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_759 (.A1(registers_16__ap[3]), .A2(n_1_0_1267), .B1( + n_1_0_1257), .B2(registers_3__ap[3]), .ZN(n_1_0_723)); + SDFF_X1_LVT \registers_reg[5][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_5__ap[3]), .CK(n_0_35), .Q(registers_5__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[31][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_31__ap[3]), .CK(n_0_61), .Q(registers_31__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_758 (.A1(registers_5__ap[3]), .A2(n_1_0_1273), .B1( + n_1_0_1266), .B2(registers_31__ap[3]), .ZN(n_1_0_722)); + SDFF_X1_LVT \registers_reg[15][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_15__ap[3]), .CK(n_0_45), .Q(registers_15__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[23][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_23__ap[3]), .CK(n_0_53), .Q(registers_23__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_757 (.A1(registers_15__ap[3]), .A2(n_1_0_1286), .B1( + n_1_0_1264), .B2(registers_23__ap[3]), .ZN(n_1_0_721)); + NAND4_X1_LVT i_1_0_756 (.A1(n_1_0_724), .A2(n_1_0_723), .A3(n_1_0_722), + .A4(n_1_0_721), .ZN(n_1_0_720)); + SDFF_X1_LVT \registers_reg[18][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_18__ap[3]), .CK(n_0_48), .Q(registers_18__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[30][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_30__ap[3]), .CK(n_0_60), .Q(registers_30__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_755 (.A1(registers_18__ap[3]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[3]), .ZN(n_1_0_719)); + SDFF_X1_LVT \registers_reg[20][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_20__ap[3]), .CK(n_0_50), .Q(registers_20__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[4][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_4__ap[3]), .CK(n_0_34), .Q(registers_4__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_754 (.A1(registers_20__ap[3]), .A2(n_1_0_1281), .B1( + n_1_0_1278), .B2(registers_4__ap[3]), .ZN(n_1_0_718)); + SDFF_X1_LVT \registers_reg[22][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_22__ap[3]), .CK(n_0_52), .Q(registers_22__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[21][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_21__ap[3]), .CK(n_0_51), .Q(registers_21__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_753 (.A1(registers_22__ap[3]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[3]), .ZN(n_1_0_717)); + SDFF_X1_LVT \registers_reg[24][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_24__ap[3]), .CK(n_0_54), .Q(registers_24__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[12][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_12__ap[3]), .CK(n_0_42), .Q(registers_12__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_752 (.A1(registers_24__ap[3]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[3]), .ZN(n_1_0_716)); + NAND4_X1_LVT i_1_0_751 (.A1(n_1_0_719), .A2(n_1_0_718), .A3(n_1_0_717), + .A4(n_1_0_716), .ZN(n_1_0_715)); + SDFF_X1_LVT \registers_reg[13][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_13__ap[3]), .CK(n_0_43), .Q(registers_13__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[25][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_25__ap[3]), .CK(n_0_55), .Q(registers_25__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_750 (.A1(registers_13__ap[3]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[3]), .ZN(n_1_0_714)); + SDFF_X1_LVT \registers_reg[19][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_19__ap[3]), .CK(n_0_49), .Q(registers_19__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[2][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_2__ap[3]), .CK(n_0_32), .Q(registers_2__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_749 (.A1(registers_19__ap[3]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[3]), .ZN(n_1_0_713)); + SDFF_X1_LVT \registers_reg[7][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_7__ap[3]), .CK(n_0_37), .Q(registers_7__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[14][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_14__ap[3]), .CK(n_0_44), .Q(registers_14__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_748 (.A1(registers_7__ap[3]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[3]), .ZN(n_1_0_712)); + SDFF_X1_LVT \registers_reg[27][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_27__ap[3]), .CK(n_0_57), .Q(registers_27__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[11][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_11__ap[3]), .CK(n_0_41), .Q(registers_11__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_747 (.A1(registers_27__ap[3]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[3]), .ZN(n_1_0_711)); + NAND4_X1_LVT i_1_0_746 (.A1(n_1_0_714), .A2(n_1_0_713), .A3(n_1_0_712), + .A4(n_1_0_711), .ZN(n_1_0_710)); + NOR3_X1_LVT i_1_0_745 (.A1(n_1_0_720), .A2(n_1_0_715), .A3(n_1_0_710), + .ZN(n_1_0_709)); + NAND4_X1_LVT i_1_0_744 (.A1(n_1_0_727), .A2(n_1_0_726), .A3(n_1_0_725), + .A4(n_1_0_709), .ZN(RRs1[3])); + AND2_X1_LVT i_0_0_2 (.A1(n_0_0_16), .A2(WRd[2]), .ZN(registers[2])); + SDFF_X1_LVT \registers_reg[28][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_28__ap[2]), .CK(n_0_58), .Q(registers_28__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[4][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_4__ap[2]), .CK(n_0_34), .Q(registers_4__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_740 (.A1(registers_28__ap[2]), .A2(n_1_0_1283), .B1( + n_1_0_1278), .B2(registers_4__ap[2]), .ZN(n_1_0_705)); + SDFF_X1_LVT \registers_reg[16][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_16__ap[2]), .CK(n_0_46), .Q(registers_16__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[31][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_31__ap[2]), .CK(n_0_61), .Q(registers_31__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_743 (.A1(registers_16__ap[2]), .A2(n_1_0_1267), .B1( + n_1_0_1266), .B2(registers_31__ap[2]), .ZN(n_1_0_708)); + SDFF_X1_LVT \registers_reg[6][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_6__ap[2]), .CK(n_0_36), .Q(registers_6__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[1][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_1__ap[2]), .CK(n_0_0), .Q(registers_1__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_739 (.A1(registers_6__ap[2]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[2]), .ZN(n_1_0_704)); + SDFF_X1_LVT \registers_reg[15][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_15__ap[2]), .CK(n_0_45), .Q(registers_15__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[27][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_27__ap[2]), .CK(n_0_57), .Q(registers_27__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_742 (.A1(registers_15__ap[2]), .A2(n_1_0_1286), .B1( + n_1_0_1279), .B2(registers_27__ap[2]), .ZN(n_1_0_707)); + INV_X1_LVT i_1_0_741 (.A(n_1_0_707), .ZN(n_1_0_706)); + SDFF_X1_LVT \registers_reg[11][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_11__ap[2]), .CK(n_0_41), .Q(registers_11__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[5][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_5__ap[2]), .CK(n_0_35), .Q(registers_5__ap[2]), .QN()); + AOI221_X1_LVT i_1_0_738 (.A(n_1_0_706), .B1(n_1_0_1270), .B2( + registers_11__ap[2]), .C1(registers_5__ap[2]), .C2(n_1_0_1273), .ZN( + n_1_0_703)); + SDFF_X1_LVT \registers_reg[10][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_10__ap[2]), .CK(n_0_40), .Q(registers_10__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[30][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_30__ap[2]), .CK(n_0_60), .Q(registers_30__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[8][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_8__ap[2]), .CK(n_0_38), .Q(registers_8__ap[2]), .QN()); + AOI222_X1_LVT i_1_0_737 (.A1(registers_10__ap[2]), .A2(n_1_0_1287), .B1( + n_1_0_1272), .B2(registers_30__ap[2]), .C1(n_1_0_1282), .C2( + registers_8__ap[2]), .ZN(n_1_0_702)); + NAND4_X1_LVT i_1_0_736 (.A1(n_1_0_708), .A2(n_1_0_704), .A3(n_1_0_703), + .A4(n_1_0_702), .ZN(n_1_0_701)); + SDFF_X1_LVT \registers_reg[9][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_9__ap[2]), .CK(n_0_39), .Q(registers_9__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[29][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_29__ap[2]), .CK(n_0_59), .Q(registers_29__ap[2]), .QN()); + AOI221_X1_LVT i_1_0_735 (.A(n_1_0_701), .B1(n_1_0_1291), .B2( + registers_9__ap[2]), .C1(registers_29__ap[2]), .C2(n_1_0_1276), .ZN( + n_1_0_700)); + SDFF_X1_LVT \registers_reg[18][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_18__ap[2]), .CK(n_0_48), .Q(registers_18__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[26][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_26__ap[2]), .CK(n_0_56), .Q(registers_26__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_734 (.A1(registers_18__ap[2]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[2]), .ZN(n_1_0_699)); + SDFF_X1_LVT \registers_reg[24][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_24__ap[2]), .CK(n_0_54), .Q(registers_24__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[12][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_12__ap[2]), .CK(n_0_42), .Q(registers_12__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_733 (.A1(registers_24__ap[2]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[2]), .ZN(n_1_0_698)); + SDFF_X1_LVT \registers_reg[22][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_22__ap[2]), .CK(n_0_52), .Q(registers_22__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[21][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_21__ap[2]), .CK(n_0_51), .Q(registers_21__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_732 (.A1(registers_22__ap[2]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[2]), .ZN(n_1_0_697)); + NAND3_X1_LVT i_1_0_731 (.A1(n_1_0_699), .A2(n_1_0_698), .A3(n_1_0_697), + .ZN(n_1_0_696)); + SDFF_X1_LVT \registers_reg[17][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_17__ap[2]), .CK(n_0_47), .Q(registers_17__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[20][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_20__ap[2]), .CK(n_0_50), .Q(registers_20__ap[2]), .QN()); + AOI221_X1_LVT i_1_0_730 (.A(n_1_0_696), .B1(n_1_0_1271), .B2( + registers_17__ap[2]), .C1(registers_20__ap[2]), .C2(n_1_0_1281), .ZN( + n_1_0_695)); + SDFF_X1_LVT \registers_reg[13][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_13__ap[2]), .CK(n_0_43), .Q(registers_13__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[25][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_25__ap[2]), .CK(n_0_55), .Q(registers_25__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_729 (.A1(registers_13__ap[2]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[2]), .ZN(n_1_0_694)); + SDFF_X1_LVT \registers_reg[7][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_7__ap[2]), .CK(n_0_37), .Q(registers_7__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[14][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_14__ap[2]), .CK(n_0_44), .Q(registers_14__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_728 (.A1(registers_7__ap[2]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[2]), .ZN(n_1_0_693)); + SDFF_X1_LVT \registers_reg[19][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_19__ap[2]), .CK(n_0_49), .Q(registers_19__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[3][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_3__ap[2]), .CK(n_0_33), .Q(registers_3__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_727 (.A1(registers_19__ap[2]), .A2(n_1_0_1295), .B1( + n_1_0_1257), .B2(registers_3__ap[2]), .ZN(n_1_0_692)); + NAND3_X1_LVT i_1_0_726 (.A1(n_1_0_694), .A2(n_1_0_693), .A3(n_1_0_692), + .ZN(n_1_0_691)); + SDFF_X1_LVT \registers_reg[23][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_23__ap[2]), .CK(n_0_53), .Q(registers_23__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[2][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_2__ap[2]), .CK(n_0_32), .Q(registers_2__ap[2]), .QN()); + AOI221_X1_LVT i_1_0_725 (.A(n_1_0_691), .B1(n_1_0_1264), .B2( + registers_23__ap[2]), .C1(registers_2__ap[2]), .C2(n_1_0_1268), .ZN( + n_1_0_690)); + NAND4_X1_LVT i_1_0_724 (.A1(n_1_0_705), .A2(n_1_0_700), .A3(n_1_0_695), + .A4(n_1_0_690), .ZN(RRs1[2])); + AND2_X1_LVT i_0_0_1 (.A1(n_0_0_16), .A2(WRd[1]), .ZN(registers[1])); + SDFF_X1_LVT \registers_reg[13][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_13__ap[1]), .CK(n_0_43), .Q(registers_13__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[21][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_21__ap[1]), .CK(n_0_51), .Q(registers_21__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_720 (.A1(registers_13__ap[1]), .A2(n_1_0_1277), .B1( + n_1_0_1259), .B2(registers_21__ap[1]), .ZN(n_1_0_686)); + SDFF_X1_LVT \registers_reg[29][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_29__ap[1]), .CK(n_0_59), .Q(registers_29__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[23][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_23__ap[1]), .CK(n_0_53), .Q(registers_23__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_723 (.A1(registers_29__ap[1]), .A2(n_1_0_1276), .B1( + n_1_0_1264), .B2(registers_23__ap[1]), .ZN(n_1_0_689)); + SDFF_X1_LVT \registers_reg[24][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_24__ap[1]), .CK(n_0_54), .Q(registers_24__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[20][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_20__ap[1]), .CK(n_0_50), .Q(registers_20__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_719 (.A1(registers_24__ap[1]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[1]), .ZN(n_1_0_685)); + SDFF_X1_LVT \registers_reg[7][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_7__ap[1]), .CK(n_0_37), .Q(registers_7__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[3][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_3__ap[1]), .CK(n_0_33), .Q(registers_3__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_722 (.A1(registers_7__ap[1]), .A2(n_1_0_1263), .B1( + n_1_0_1257), .B2(registers_3__ap[1]), .ZN(n_1_0_688)); + INV_X1_LVT i_1_0_721 (.A(n_1_0_688), .ZN(n_1_0_687)); + SDFF_X1_LVT \registers_reg[31][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_31__ap[1]), .CK(n_0_61), .Q(registers_31__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[4][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_4__ap[1]), .CK(n_0_34), .Q(registers_4__ap[1]), .QN()); + AOI221_X1_LVT i_1_0_718 (.A(n_1_0_687), .B1(n_1_0_1266), .B2( + registers_31__ap[1]), .C1(registers_4__ap[1]), .C2(n_1_0_1278), .ZN( + n_1_0_684)); + SDFF_X1_LVT \registers_reg[10][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_10__ap[1]), .CK(n_0_40), .Q(registers_10__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[26][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_26__ap[1]), .CK(n_0_56), .Q(registers_26__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[25][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_25__ap[1]), .CK(n_0_55), .Q(registers_25__ap[1]), .QN()); + AOI222_X1_LVT i_1_0_717 (.A1(registers_10__ap[1]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[1]), .C1(registers_25__ap[1]), .C2( + n_1_0_1269), .ZN(n_1_0_683)); + NAND4_X1_LVT i_1_0_716 (.A1(n_1_0_689), .A2(n_1_0_685), .A3(n_1_0_684), + .A4(n_1_0_683), .ZN(n_1_0_682)); + SDFF_X1_LVT \registers_reg[8][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_8__ap[1]), .CK(n_0_38), .Q(registers_8__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[28][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_28__ap[1]), .CK(n_0_58), .Q(registers_28__ap[1]), .QN()); + AOI221_X1_LVT i_1_0_715 (.A(n_1_0_682), .B1(n_1_0_1282), .B2( + registers_8__ap[1]), .C1(registers_28__ap[1]), .C2(n_1_0_1283), .ZN( + n_1_0_681)); + SDFF_X1_LVT \registers_reg[18][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_18__ap[1]), .CK(n_0_48), .Q(registers_18__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[30][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_30__ap[1]), .CK(n_0_60), .Q(registers_30__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_714 (.A1(registers_18__ap[1]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[1]), .ZN(n_1_0_680)); + SDFF_X1_LVT \registers_reg[17][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_17__ap[1]), .CK(n_0_47), .Q(registers_17__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[12][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_12__ap[1]), .CK(n_0_42), .Q(registers_12__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_713 (.A1(registers_17__ap[1]), .A2(n_1_0_1271), .B1( + n_1_0_1260), .B2(registers_12__ap[1]), .ZN(n_1_0_679)); + SDFF_X1_LVT \registers_reg[15][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_15__ap[1]), .CK(n_0_45), .Q(registers_15__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[5][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_5__ap[1]), .CK(n_0_35), .Q(registers_5__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_712 (.A1(registers_15__ap[1]), .A2(n_1_0_1286), .B1( + n_1_0_1273), .B2(registers_5__ap[1]), .ZN(n_1_0_678)); + NAND3_X1_LVT i_1_0_711 (.A1(n_1_0_680), .A2(n_1_0_679), .A3(n_1_0_678), + .ZN(n_1_0_677)); + SDFF_X1_LVT \registers_reg[22][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_22__ap[1]), .CK(n_0_52), .Q(registers_22__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[16][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_16__ap[1]), .CK(n_0_46), .Q(registers_16__ap[1]), .QN()); + AOI221_X1_LVT i_1_0_710 (.A(n_1_0_677), .B1(n_1_0_1294), .B2( + registers_22__ap[1]), .C1(registers_16__ap[1]), .C2(n_1_0_1267), .ZN( + n_1_0_676)); + SDFF_X1_LVT \registers_reg[9][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_9__ap[1]), .CK(n_0_39), .Q(registers_9__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[1][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_1__ap[1]), .CK(n_0_0), .Q(registers_1__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_709 (.A1(registers_9__ap[1]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[1]), .ZN(n_1_0_675)); + SDFF_X1_LVT \registers_reg[6][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_6__ap[1]), .CK(n_0_36), .Q(registers_6__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[14][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_14__ap[1]), .CK(n_0_44), .Q(registers_14__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_708 (.A1(registers_6__ap[1]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[1]), .ZN(n_1_0_674)); + SDFF_X1_LVT \registers_reg[19][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_19__ap[1]), .CK(n_0_49), .Q(registers_19__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[2][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_2__ap[1]), .CK(n_0_32), .Q(registers_2__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_707 (.A1(registers_19__ap[1]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[1]), .ZN(n_1_0_673)); + NAND3_X1_LVT i_1_0_706 (.A1(n_1_0_675), .A2(n_1_0_674), .A3(n_1_0_673), + .ZN(n_1_0_672)); + SDFF_X1_LVT \registers_reg[11][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_11__ap[1]), .CK(n_0_41), .Q(registers_11__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[27][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_27__ap[1]), .CK(n_0_57), .Q(registers_27__ap[1]), .QN()); + AOI221_X1_LVT i_1_0_705 (.A(n_1_0_672), .B1(n_1_0_1270), .B2( + registers_11__ap[1]), .C1(registers_27__ap[1]), .C2(n_1_0_1279), .ZN( + n_1_0_671)); + NAND4_X1_LVT i_1_0_704 (.A1(n_1_0_686), .A2(n_1_0_681), .A3(n_1_0_676), + .A4(n_1_0_671), .ZN(RRs1[1])); + AND2_X1_LVT i_0_0_0 (.A1(n_0_0_16), .A2(WRd[0]), .ZN(registers[0])); + SDFF_X1_LVT \registers_reg[13][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_13__ap[0]), .CK(n_0_43), .Q(registers_13__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[21][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_21__ap[0]), .CK(n_0_51), .Q(registers_21__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_703 (.A1(registers_13__ap[0]), .A2(n_1_0_1277), .B1( + n_1_0_1259), .B2(registers_21__ap[0]), .ZN(n_1_0_670)); + SDFF_X1_LVT \registers_reg[10][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_10__ap[0]), .CK(n_0_40), .Q(registers_10__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[26][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_26__ap[0]), .CK(n_0_56), .Q(registers_26__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[25][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_25__ap[0]), .CK(n_0_55), .Q(registers_25__ap[0]), .QN()); + AOI222_X1_LVT i_1_0_702 (.A1(registers_10__ap[0]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[0]), .C1(registers_25__ap[0]), .C2( + n_1_0_1269), .ZN(n_1_0_669)); + SDFF_X1_LVT \registers_reg[28][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_28__ap[0]), .CK(n_0_58), .Q(registers_28__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[8][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_8__ap[0]), .CK(n_0_38), .Q(registers_8__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_701 (.A1(registers_28__ap[0]), .A2(n_1_0_1283), .B1( + n_1_0_1282), .B2(registers_8__ap[0]), .ZN(n_1_0_668)); + SDFF_X1_LVT \registers_reg[24][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_24__ap[0]), .CK(n_0_54), .Q(registers_24__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[20][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_20__ap[0]), .CK(n_0_50), .Q(registers_20__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_700 (.A1(registers_24__ap[0]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[0]), .ZN(n_1_0_667)); + SDFF_X1_LVT \registers_reg[7][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_7__ap[0]), .CK(n_0_37), .Q(registers_7__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[3][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_3__ap[0]), .CK(n_0_33), .Q(registers_3__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_699 (.A1(registers_7__ap[0]), .A2(n_1_0_1263), .B1( + n_1_0_1257), .B2(registers_3__ap[0]), .ZN(n_1_0_666)); + SDFF_X1_LVT \registers_reg[17][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_17__ap[0]), .CK(n_0_47), .Q(registers_17__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[31][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_31__ap[0]), .CK(n_0_61), .Q(registers_31__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_698 (.A1(registers_17__ap[0]), .A2(n_1_0_1271), .B1( + n_1_0_1266), .B2(registers_31__ap[0]), .ZN(n_1_0_665)); + SDFF_X1_LVT \registers_reg[29][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_29__ap[0]), .CK(n_0_59), .Q(registers_29__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[23][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_23__ap[0]), .CK(n_0_53), .Q(registers_23__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_697 (.A1(registers_29__ap[0]), .A2(n_1_0_1276), .B1( + n_1_0_1264), .B2(registers_23__ap[0]), .ZN(n_1_0_664)); + NAND4_X1_LVT i_1_0_696 (.A1(n_1_0_667), .A2(n_1_0_666), .A3(n_1_0_665), + .A4(n_1_0_664), .ZN(n_1_0_663)); + SDFF_X1_LVT \registers_reg[18][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_18__ap[0]), .CK(n_0_48), .Q(registers_18__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[30][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_30__ap[0]), .CK(n_0_60), .Q(registers_30__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_695 (.A1(registers_18__ap[0]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[0]), .ZN(n_1_0_662)); + SDFF_X1_LVT \registers_reg[4][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_4__ap[0]), .CK(n_0_34), .Q(registers_4__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[12][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_12__ap[0]), .CK(n_0_42), .Q(registers_12__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_694 (.A1(registers_4__ap[0]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[0]), .ZN(n_1_0_661)); + SDFF_X1_LVT \registers_reg[15][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_15__ap[0]), .CK(n_0_45), .Q(registers_15__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[16][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_16__ap[0]), .CK(n_0_46), .Q(registers_16__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_693 (.A1(registers_15__ap[0]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[0]), .ZN(n_1_0_660)); + SDFF_X1_LVT \registers_reg[22][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_22__ap[0]), .CK(n_0_52), .Q(registers_22__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[5][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_5__ap[0]), .CK(n_0_35), .Q(registers_5__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_692 (.A1(registers_22__ap[0]), .A2(n_1_0_1294), .B1( + n_1_0_1273), .B2(registers_5__ap[0]), .ZN(n_1_0_659)); + NAND4_X1_LVT i_1_0_691 (.A1(n_1_0_662), .A2(n_1_0_661), .A3(n_1_0_660), + .A4(n_1_0_659), .ZN(n_1_0_658)); + SDFF_X1_LVT \registers_reg[19][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_19__ap[0]), .CK(n_0_49), .Q(registers_19__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[2][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_2__ap[0]), .CK(n_0_32), .Q(registers_2__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_690 (.A1(registers_19__ap[0]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[0]), .ZN(n_1_0_657)); + SDFF_X1_LVT \registers_reg[9][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_9__ap[0]), .CK(n_0_39), .Q(registers_9__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[1][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_1__ap[0]), .CK(n_0_0), .Q(registers_1__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_689 (.A1(registers_9__ap[0]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[0]), .ZN(n_1_0_656)); + SDFF_X1_LVT \registers_reg[6][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_6__ap[0]), .CK(n_0_36), .Q(registers_6__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[14][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_14__ap[0]), .CK(n_0_44), .Q(registers_14__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_688 (.A1(registers_6__ap[0]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[0]), .ZN(n_1_0_655)); + SDFF_X1_LVT \registers_reg[27][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_27__ap[0]), .CK(n_0_57), .Q(registers_27__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[11][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_11__ap[0]), .CK(n_0_41), .Q(registers_11__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_687 (.A1(registers_27__ap[0]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[0]), .ZN(n_1_0_654)); + NAND4_X1_LVT i_1_0_686 (.A1(n_1_0_657), .A2(n_1_0_656), .A3(n_1_0_655), + .A4(n_1_0_654), .ZN(n_1_0_653)); + NOR3_X1_LVT i_1_0_685 (.A1(n_1_0_663), .A2(n_1_0_658), .A3(n_1_0_653), + .ZN(n_1_0_652)); + NAND4_X1_LVT i_1_0_684 (.A1(n_1_0_670), .A2(n_1_0_669), .A3(n_1_0_668), + .A4(n_1_0_652), .ZN(RRs1[0])); + INV_X1_LVT i_1_0_1366 (.A(Rs2[1]), .ZN(n_1_0_1302)); + NAND3_X1_LVT i_1_0_683 (.A1(n_1_0_1302), .A2(Rs2[4]), .A3(Rs2[2]), .ZN( + n_1_0_651)); + INV_X1_LVT i_1_0_1369 (.A(Rs2[3]), .ZN(n_1_0_1305)); + OR2_X1_LVT i_1_0_673 (.A1(n_1_0_1305), .A2(Rs2[0]), .ZN(n_1_0_641)); + NOR2_X1_LVT i_1_0_666 (.A1(n_1_0_651), .A2(n_1_0_641), .ZN(n_1_0_634)); + NAND2_X1_LVT i_1_0_677 (.A1(n_1_0_1305), .A2(Rs2[0]), .ZN(n_1_0_645)); + INV_X1_LVT i_1_0_1368 (.A(Rs2[2]), .ZN(n_1_0_1304)); + NAND3_X1_LVT i_1_0_662 (.A1(n_1_0_1304), .A2(n_1_0_1302), .A3(Rs2[4]), + .ZN(n_1_0_630)); + NOR2_X1_LVT i_1_0_661 (.A1(n_1_0_645), .A2(n_1_0_630), .ZN(n_1_0_629)); + AOI22_X1_LVT i_1_0_641 (.A1(registers_28__ap[31]), .A2(n_1_0_634), .B1( + n_1_0_629), .B2(registers_17__ap[31]), .ZN(n_1_0_609)); + NAND3_X1_LVT i_1_0_680 (.A1(n_1_0_1304), .A2(Rs2[4]), .A3(Rs2[1]), .ZN( + n_1_0_648)); + NOR2_X1_LVT i_1_0_672 (.A1(n_1_0_648), .A2(n_1_0_641), .ZN(n_1_0_640)); + INV_X1_LVT i_1_0_1367 (.A(Rs2[4]), .ZN(n_1_0_1303)); + NAND3_X1_LVT i_1_0_657 (.A1(n_1_0_1304), .A2(n_1_0_1303), .A3(Rs2[1]), + .ZN(n_1_0_625)); + NOR2_X1_LVT i_1_0_656 (.A1(n_1_0_641), .A2(n_1_0_625), .ZN(n_1_0_624)); + NOR4_X1_LVT i_1_0_658 (.A1(n_1_0_641), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), + .ZN(n_1_0_626)); + AOI222_X1_LVT i_1_0_640 (.A1(registers_26__ap[31]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[31]), .C1(n_1_0_626), .C2( + registers_8__ap[31]), .ZN(n_1_0_608)); + NAND2_X1_LVT i_1_0_682 (.A1(Rs2[0]), .A2(Rs2[3]), .ZN(n_1_0_650)); + NOR2_X1_LVT i_1_0_681 (.A1(n_1_0_651), .A2(n_1_0_650), .ZN(n_1_0_649)); + NOR4_X1_LVT i_1_0_649 (.A1(n_1_0_650), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), + .ZN(n_1_0_617)); + AOI22_X1_LVT i_1_0_639 (.A1(registers_29__ap[31]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[31]), .ZN(n_1_0_607)); + NOR4_X1_LVT i_1_0_676 (.A1(n_1_0_645), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), + .ZN(n_1_0_644)); + OR2_X1_LVT i_1_0_679 (.A1(Rs2[0]), .A2(Rs2[3]), .ZN(n_1_0_647)); + NAND3_X1_LVT i_1_0_660 (.A1(n_1_0_1303), .A2(Rs2[1]), .A3(Rs2[2]), .ZN( + n_1_0_628)); + NOR2_X1_LVT i_1_0_648 (.A1(n_1_0_647), .A2(n_1_0_628), .ZN(n_1_0_616)); + AOI22_X1_LVT i_1_0_638 (.A1(registers_1__ap[31]), .A2(n_1_0_644), .B1( + n_1_0_616), .B2(registers_6__ap[31]), .ZN(n_1_0_606)); + NOR2_X1_LVT i_1_0_655 (.A1(n_1_0_645), .A2(n_1_0_628), .ZN(n_1_0_623)); + NAND3_X1_LVT i_1_0_675 (.A1(Rs2[2]), .A2(Rs2[4]), .A3(Rs2[1]), .ZN(n_1_0_643)); + NOR2_X1_LVT i_1_0_647 (.A1(n_1_0_645), .A2(n_1_0_643), .ZN(n_1_0_615)); + AOI22_X1_LVT i_1_0_637 (.A1(registers_7__ap[31]), .A2(n_1_0_623), .B1( + n_1_0_615), .B2(registers_23__ap[31]), .ZN(n_1_0_605)); + NOR2_X1_LVT i_1_0_665 (.A1(n_1_0_648), .A2(n_1_0_645), .ZN(n_1_0_633)); + NOR2_X1_LVT i_1_0_646 (.A1(n_1_0_647), .A2(n_1_0_630), .ZN(n_1_0_614)); + AOI22_X1_LVT i_1_0_636 (.A1(registers_19__ap[31]), .A2(n_1_0_633), .B1( + n_1_0_614), .B2(registers_16__ap[31]), .ZN(n_1_0_604)); + NOR2_X1_LVT i_1_0_669 (.A1(n_1_0_650), .A2(n_1_0_643), .ZN(n_1_0_637)); + NAND3_X1_LVT i_1_0_671 (.A1(n_1_0_1303), .A2(n_1_0_1302), .A3(Rs2[2]), + .ZN(n_1_0_639)); + NOR2_X1_LVT i_1_0_667 (.A1(n_1_0_645), .A2(n_1_0_639), .ZN(n_1_0_635)); + AOI22_X1_LVT i_1_0_635 (.A1(registers_31__ap[31]), .A2(n_1_0_637), .B1( + n_1_0_635), .B2(registers_5__ap[31]), .ZN(n_1_0_603)); + NAND4_X1_LVT i_1_0_634 (.A1(n_1_0_606), .A2(n_1_0_605), .A3(n_1_0_604), + .A4(n_1_0_603), .ZN(n_1_0_602)); + NOR2_X1_LVT i_1_0_678 (.A1(n_1_0_648), .A2(n_1_0_647), .ZN(n_1_0_646)); + NOR2_X1_LVT i_1_0_654 (.A1(n_1_0_643), .A2(n_1_0_641), .ZN(n_1_0_622)); + AOI22_X1_LVT i_1_0_633 (.A1(registers_18__ap[31]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[31]), .ZN(n_1_0_601)); + NOR2_X1_LVT i_1_0_670 (.A1(n_1_0_647), .A2(n_1_0_639), .ZN(n_1_0_638)); + NOR2_X1_LVT i_1_0_645 (.A1(n_1_0_651), .A2(n_1_0_647), .ZN(n_1_0_613)); + AOI22_X1_LVT i_1_0_632 (.A1(registers_4__ap[31]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[31]), .ZN(n_1_0_600)); + NOR2_X1_LVT i_1_0_674 (.A1(n_1_0_647), .A2(n_1_0_643), .ZN(n_1_0_642)); + NOR2_X1_LVT i_1_0_644 (.A1(n_1_0_651), .A2(n_1_0_645), .ZN(n_1_0_612)); + AOI22_X1_LVT i_1_0_631 (.A1(registers_22__ap[31]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[31]), .ZN(n_1_0_599)); + NOR2_X1_LVT i_1_0_664 (.A1(n_1_0_641), .A2(n_1_0_639), .ZN(n_1_0_632)); + NOR2_X1_LVT i_1_0_653 (.A1(n_1_0_641), .A2(n_1_0_630), .ZN(n_1_0_621)); + AOI22_X1_LVT i_1_0_630 (.A1(registers_12__ap[31]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[31]), .ZN(n_1_0_598)); + NAND4_X1_LVT i_1_0_629 (.A1(n_1_0_601), .A2(n_1_0_600), .A3(n_1_0_599), + .A4(n_1_0_598), .ZN(n_1_0_597)); + NOR2_X1_LVT i_1_0_663 (.A1(n_1_0_650), .A2(n_1_0_639), .ZN(n_1_0_631)); + NOR2_X1_LVT i_1_0_652 (.A1(n_1_0_650), .A2(n_1_0_630), .ZN(n_1_0_620)); + AOI22_X1_LVT i_1_0_628 (.A1(registers_13__ap[31]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[31]), .ZN(n_1_0_596)); + NOR2_X1_LVT i_1_0_659 (.A1(n_1_0_650), .A2(n_1_0_628), .ZN(n_1_0_627)); + NOR2_X1_LVT i_1_0_651 (.A1(n_1_0_641), .A2(n_1_0_628), .ZN(n_1_0_619)); + AOI22_X1_LVT i_1_0_627 (.A1(registers_15__ap[31]), .A2(n_1_0_627), .B1( + n_1_0_619), .B2(registers_14__ap[31]), .ZN(n_1_0_595)); + NOR2_X1_LVT i_1_0_668 (.A1(n_1_0_650), .A2(n_1_0_648), .ZN(n_1_0_636)); + NOR2_X1_LVT i_1_0_643 (.A1(n_1_0_650), .A2(n_1_0_625), .ZN(n_1_0_611)); + AOI22_X1_LVT i_1_0_626 (.A1(registers_27__ap[31]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[31]), .ZN(n_1_0_594)); + NOR2_X1_LVT i_1_0_650 (.A1(n_1_0_647), .A2(n_1_0_625), .ZN(n_1_0_618)); + NOR2_X1_LVT i_1_0_642 (.A1(n_1_0_645), .A2(n_1_0_625), .ZN(n_1_0_610)); + AOI22_X1_LVT i_1_0_625 (.A1(registers_2__ap[31]), .A2(n_1_0_618), .B1( + n_1_0_610), .B2(registers_3__ap[31]), .ZN(n_1_0_593)); + NAND4_X1_LVT i_1_0_624 (.A1(n_1_0_596), .A2(n_1_0_595), .A3(n_1_0_594), + .A4(n_1_0_593), .ZN(n_1_0_592)); + NOR3_X1_LVT i_1_0_623 (.A1(n_1_0_602), .A2(n_1_0_597), .A3(n_1_0_592), + .ZN(n_1_0_591)); + NAND4_X1_LVT i_1_0_622 (.A1(n_1_0_609), .A2(n_1_0_608), .A3(n_1_0_607), + .A4(n_1_0_591), .ZN(RRs2[31])); + AOI22_X1_LVT i_1_0_620 (.A1(registers_29__ap[30]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[30]), .ZN(n_1_0_589)); + AOI22_X1_LVT i_1_0_621 (.A1(registers_7__ap[30]), .A2(n_1_0_623), .B1( + n_1_0_615), .B2(registers_23__ap[30]), .ZN(n_1_0_590)); + AOI22_X1_LVT i_1_0_619 (.A1(registers_1__ap[30]), .A2(n_1_0_644), .B1( + n_1_0_616), .B2(registers_6__ap[30]), .ZN(n_1_0_588)); + AOI22_X1_LVT i_1_0_618 (.A1(registers_5__ap[30]), .A2(n_1_0_635), .B1( + n_1_0_633), .B2(registers_19__ap[30]), .ZN(n_1_0_587)); + NAND3_X1_LVT i_1_0_617 (.A1(n_1_0_590), .A2(n_1_0_588), .A3(n_1_0_587), + .ZN(n_1_0_586)); + AOI221_X1_LVT i_1_0_616 (.A(n_1_0_586), .B1(n_1_0_637), .B2( + registers_31__ap[30]), .C1(registers_16__ap[30]), .C2(n_1_0_614), .ZN( + n_1_0_585)); + AOI222_X1_LVT i_1_0_615 (.A1(registers_26__ap[30]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[30]), .C1(n_1_0_626), .C2( + registers_8__ap[30]), .ZN(n_1_0_584)); + NAND3_X1_LVT i_1_0_614 (.A1(n_1_0_589), .A2(n_1_0_585), .A3(n_1_0_584), + .ZN(n_1_0_583)); + AOI221_X1_LVT i_1_0_613 (.A(n_1_0_583), .B1(n_1_0_629), .B2( + registers_17__ap[30]), .C1(registers_28__ap[30]), .C2(n_1_0_634), .ZN( + n_1_0_582)); + AOI22_X1_LVT i_1_0_612 (.A1(registers_18__ap[30]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[30]), .ZN(n_1_0_581)); + AOI22_X1_LVT i_1_0_611 (.A1(registers_4__ap[30]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[30]), .ZN(n_1_0_580)); + AOI22_X1_LVT i_1_0_610 (.A1(registers_22__ap[30]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[30]), .ZN(n_1_0_579)); + NAND3_X1_LVT i_1_0_609 (.A1(n_1_0_581), .A2(n_1_0_580), .A3(n_1_0_579), + .ZN(n_1_0_578)); + AOI221_X1_LVT i_1_0_608 (.A(n_1_0_578), .B1(n_1_0_621), .B2( + registers_24__ap[30]), .C1(registers_12__ap[30]), .C2(n_1_0_632), .ZN( + n_1_0_577)); + AOI22_X1_LVT i_1_0_607 (.A1(registers_13__ap[30]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[30]), .ZN(n_1_0_576)); + AOI22_X1_LVT i_1_0_606 (.A1(registers_15__ap[30]), .A2(n_1_0_627), .B1( + n_1_0_619), .B2(registers_14__ap[30]), .ZN(n_1_0_575)); + AOI22_X1_LVT i_1_0_605 (.A1(registers_27__ap[30]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[30]), .ZN(n_1_0_574)); + NAND3_X1_LVT i_1_0_604 (.A1(n_1_0_576), .A2(n_1_0_575), .A3(n_1_0_574), + .ZN(n_1_0_573)); + AOI221_X1_LVT i_1_0_603 (.A(n_1_0_573), .B1(n_1_0_610), .B2( + registers_3__ap[30]), .C1(registers_2__ap[30]), .C2(n_1_0_618), .ZN( + n_1_0_572)); + NAND3_X1_LVT i_1_0_602 (.A1(n_1_0_582), .A2(n_1_0_577), .A3(n_1_0_572), + .ZN(RRs2[30])); + AOI22_X1_LVT i_1_0_600 (.A1(registers_28__ap[29]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[29]), .ZN(n_1_0_570)); + AOI22_X1_LVT i_1_0_601 (.A1(registers_31__ap[29]), .A2(n_1_0_637), .B1( + n_1_0_627), .B2(registers_15__ap[29]), .ZN(n_1_0_571)); + AOI22_X1_LVT i_1_0_599 (.A1(registers_24__ap[29]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[29]), .ZN(n_1_0_569)); + AOI22_X1_LVT i_1_0_598 (.A1(registers_19__ap[29]), .A2(n_1_0_633), .B1( + n_1_0_629), .B2(registers_17__ap[29]), .ZN(n_1_0_568)); + NAND3_X1_LVT i_1_0_597 (.A1(n_1_0_571), .A2(n_1_0_569), .A3(n_1_0_568), + .ZN(n_1_0_567)); + AOI221_X1_LVT i_1_0_596 (.A(n_1_0_567), .B1(n_1_0_615), .B2( + registers_23__ap[29]), .C1(registers_29__ap[29]), .C2(n_1_0_649), .ZN( + n_1_0_566)); + AOI222_X1_LVT i_1_0_595 (.A1(registers_26__ap[29]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[29]), .C1(n_1_0_620), .C2( + registers_25__ap[29]), .ZN(n_1_0_565)); + NAND3_X1_LVT i_1_0_594 (.A1(n_1_0_570), .A2(n_1_0_566), .A3(n_1_0_565), + .ZN(n_1_0_564)); + AOI221_X1_LVT i_1_0_593 (.A(n_1_0_564), .B1(n_1_0_612), .B2( + registers_21__ap[29]), .C1(registers_13__ap[29]), .C2(n_1_0_631), .ZN( + n_1_0_563)); + AOI22_X1_LVT i_1_0_592 (.A1(registers_18__ap[29]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[29]), .ZN(n_1_0_562)); + AOI22_X1_LVT i_1_0_591 (.A1(registers_4__ap[29]), .A2(n_1_0_638), .B1( + n_1_0_632), .B2(registers_12__ap[29]), .ZN(n_1_0_561)); + AOI22_X1_LVT i_1_0_590 (.A1(registers_7__ap[29]), .A2(n_1_0_623), .B1( + n_1_0_614), .B2(registers_16__ap[29]), .ZN(n_1_0_560)); + NAND3_X1_LVT i_1_0_589 (.A1(n_1_0_562), .A2(n_1_0_561), .A3(n_1_0_560), + .ZN(n_1_0_559)); + AOI221_X1_LVT i_1_0_588 (.A(n_1_0_559), .B1(n_1_0_642), .B2( + registers_22__ap[29]), .C1(registers_5__ap[29]), .C2(n_1_0_635), .ZN( + n_1_0_558)); + AOI22_X1_LVT i_1_0_587 (.A1(registers_1__ap[29]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[29]), .ZN(n_1_0_557)); + AOI22_X1_LVT i_1_0_586 (.A1(registers_14__ap[29]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[29]), .ZN(n_1_0_556)); + AOI22_X1_LVT i_1_0_585 (.A1(registers_27__ap[29]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[29]), .ZN(n_1_0_555)); + NAND3_X1_LVT i_1_0_584 (.A1(n_1_0_557), .A2(n_1_0_556), .A3(n_1_0_555), + .ZN(n_1_0_554)); + AOI221_X1_LVT i_1_0_583 (.A(n_1_0_554), .B1(n_1_0_610), .B2( + registers_3__ap[29]), .C1(registers_2__ap[29]), .C2(n_1_0_618), .ZN( + n_1_0_553)); + NAND3_X1_LVT i_1_0_582 (.A1(n_1_0_563), .A2(n_1_0_558), .A3(n_1_0_553), + .ZN(RRs2[29])); + AOI22_X1_LVT i_1_0_581 (.A1(registers_5__ap[28]), .A2(n_1_0_635), .B1( + n_1_0_634), .B2(registers_28__ap[28]), .ZN(n_1_0_552)); + AOI222_X1_LVT i_1_0_580 (.A1(registers_26__ap[28]), .A2(n_1_0_640), .B1( + n_1_0_633), .B2(registers_19__ap[28]), .C1(n_1_0_626), .C2( + registers_8__ap[28]), .ZN(n_1_0_551)); + AOI22_X1_LVT i_1_0_579 (.A1(registers_2__ap[28]), .A2(n_1_0_618), .B1( + n_1_0_617), .B2(registers_9__ap[28]), .ZN(n_1_0_550)); + AOI22_X1_LVT i_1_0_578 (.A1(registers_7__ap[28]), .A2(n_1_0_623), .B1( + n_1_0_612), .B2(registers_21__ap[28]), .ZN(n_1_0_549)); + AOI22_X1_LVT i_1_0_577 (.A1(registers_16__ap[28]), .A2(n_1_0_614), .B1( + n_1_0_611), .B2(registers_11__ap[28]), .ZN(n_1_0_548)); + AOI22_X1_LVT i_1_0_576 (.A1(registers_31__ap[28]), .A2(n_1_0_637), .B1( + n_1_0_619), .B2(registers_14__ap[28]), .ZN(n_1_0_547)); + AOI22_X1_LVT i_1_0_575 (.A1(registers_15__ap[28]), .A2(n_1_0_627), .B1( + n_1_0_610), .B2(registers_3__ap[28]), .ZN(n_1_0_546)); + NAND4_X1_LVT i_1_0_574 (.A1(n_1_0_549), .A2(n_1_0_548), .A3(n_1_0_547), + .A4(n_1_0_546), .ZN(n_1_0_545)); + AOI22_X1_LVT i_1_0_573 (.A1(registers_22__ap[28]), .A2(n_1_0_642), .B1( + n_1_0_622), .B2(registers_30__ap[28]), .ZN(n_1_0_544)); + AOI22_X1_LVT i_1_0_572 (.A1(registers_4__ap[28]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[28]), .ZN(n_1_0_543)); + AOI22_X1_LVT i_1_0_571 (.A1(registers_29__ap[28]), .A2(n_1_0_649), .B1( + n_1_0_644), .B2(registers_1__ap[28]), .ZN(n_1_0_542)); + AOI22_X1_LVT i_1_0_570 (.A1(registers_12__ap[28]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[28]), .ZN(n_1_0_541)); + NAND4_X1_LVT i_1_0_569 (.A1(n_1_0_544), .A2(n_1_0_543), .A3(n_1_0_542), + .A4(n_1_0_541), .ZN(n_1_0_540)); + AOI22_X1_LVT i_1_0_568 (.A1(registers_13__ap[28]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[28]), .ZN(n_1_0_539)); + AOI22_X1_LVT i_1_0_567 (.A1(registers_17__ap[28]), .A2(n_1_0_629), .B1( + n_1_0_616), .B2(registers_6__ap[28]), .ZN(n_1_0_538)); + AOI22_X1_LVT i_1_0_566 (.A1(registers_10__ap[28]), .A2(n_1_0_624), .B1( + n_1_0_615), .B2(registers_23__ap[28]), .ZN(n_1_0_537)); + AOI22_X1_LVT i_1_0_565 (.A1(registers_18__ap[28]), .A2(n_1_0_646), .B1( + n_1_0_636), .B2(registers_27__ap[28]), .ZN(n_1_0_536)); + NAND4_X1_LVT i_1_0_564 (.A1(n_1_0_539), .A2(n_1_0_538), .A3(n_1_0_537), + .A4(n_1_0_536), .ZN(n_1_0_535)); + NOR3_X1_LVT i_1_0_563 (.A1(n_1_0_545), .A2(n_1_0_540), .A3(n_1_0_535), + .ZN(n_1_0_534)); + NAND4_X1_LVT i_1_0_562 (.A1(n_1_0_552), .A2(n_1_0_551), .A3(n_1_0_550), + .A4(n_1_0_534), .ZN(RRs2[28])); + AOI22_X1_LVT i_1_0_561 (.A1(registers_17__ap[27]), .A2(n_1_0_629), .B1( + n_1_0_612), .B2(registers_21__ap[27]), .ZN(n_1_0_533)); + AOI222_X1_LVT i_1_0_560 (.A1(registers_19__ap[27]), .A2(n_1_0_633), .B1( + n_1_0_631), .B2(registers_13__ap[27]), .C1(registers_30__ap[27]), .C2( + n_1_0_622), .ZN(n_1_0_532)); + AOI22_X1_LVT i_1_0_559 (.A1(registers_1__ap[27]), .A2(n_1_0_644), .B1( + n_1_0_634), .B2(registers_28__ap[27]), .ZN(n_1_0_531)); + AOI22_X1_LVT i_1_0_558 (.A1(registers_24__ap[27]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[27]), .ZN(n_1_0_530)); + AOI22_X1_LVT i_1_0_557 (.A1(registers_15__ap[27]), .A2(n_1_0_627), .B1( + n_1_0_611), .B2(registers_11__ap[27]), .ZN(n_1_0_529)); + AOI22_X1_LVT i_1_0_556 (.A1(registers_4__ap[27]), .A2(n_1_0_638), .B1( + n_1_0_636), .B2(registers_27__ap[27]), .ZN(n_1_0_528)); + AOI22_X1_LVT i_1_0_555 (.A1(registers_31__ap[27]), .A2(n_1_0_637), .B1( + n_1_0_618), .B2(registers_2__ap[27]), .ZN(n_1_0_527)); + NAND4_X1_LVT i_1_0_554 (.A1(n_1_0_530), .A2(n_1_0_529), .A3(n_1_0_528), + .A4(n_1_0_527), .ZN(n_1_0_526)); + AOI22_X1_LVT i_1_0_553 (.A1(registers_18__ap[27]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[27]), .ZN(n_1_0_525)); + AOI22_X1_LVT i_1_0_552 (.A1(registers_5__ap[27]), .A2(n_1_0_635), .B1( + n_1_0_632), .B2(registers_12__ap[27]), .ZN(n_1_0_524)); + AOI22_X1_LVT i_1_0_551 (.A1(registers_6__ap[27]), .A2(n_1_0_616), .B1( + n_1_0_614), .B2(registers_16__ap[27]), .ZN(n_1_0_523)); + AOI22_X1_LVT i_1_0_550 (.A1(registers_22__ap[27]), .A2(n_1_0_642), .B1( + n_1_0_620), .B2(registers_25__ap[27]), .ZN(n_1_0_522)); + NAND4_X1_LVT i_1_0_549 (.A1(n_1_0_525), .A2(n_1_0_524), .A3(n_1_0_523), + .A4(n_1_0_522), .ZN(n_1_0_521)); + AOI22_X1_LVT i_1_0_548 (.A1(registers_29__ap[27]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[27]), .ZN(n_1_0_520)); + AOI22_X1_LVT i_1_0_547 (.A1(registers_7__ap[27]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[27]), .ZN(n_1_0_519)); + AOI22_X1_LVT i_1_0_546 (.A1(registers_8__ap[27]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[27]), .ZN(n_1_0_518)); + AOI22_X1_LVT i_1_0_545 (.A1(registers_10__ap[27]), .A2(n_1_0_624), .B1( + n_1_0_610), .B2(registers_3__ap[27]), .ZN(n_1_0_517)); + NAND4_X1_LVT i_1_0_544 (.A1(n_1_0_520), .A2(n_1_0_519), .A3(n_1_0_518), + .A4(n_1_0_517), .ZN(n_1_0_516)); + NOR3_X1_LVT i_1_0_543 (.A1(n_1_0_526), .A2(n_1_0_521), .A3(n_1_0_516), + .ZN(n_1_0_515)); + NAND4_X1_LVT i_1_0_542 (.A1(n_1_0_533), .A2(n_1_0_532), .A3(n_1_0_531), + .A4(n_1_0_515), .ZN(RRs2[27])); + AOI22_X1_LVT i_1_0_541 (.A1(registers_17__ap[26]), .A2(n_1_0_629), .B1( + n_1_0_612), .B2(registers_21__ap[26]), .ZN(n_1_0_514)); + AOI222_X1_LVT i_1_0_540 (.A1(registers_19__ap[26]), .A2(n_1_0_633), .B1( + n_1_0_622), .B2(registers_30__ap[26]), .C1(n_1_0_631), .C2( + registers_13__ap[26]), .ZN(n_1_0_513)); + AOI22_X1_LVT i_1_0_539 (.A1(registers_1__ap[26]), .A2(n_1_0_644), .B1( + n_1_0_634), .B2(registers_28__ap[26]), .ZN(n_1_0_512)); + AOI22_X1_LVT i_1_0_538 (.A1(registers_24__ap[26]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[26]), .ZN(n_1_0_511)); + AOI22_X1_LVT i_1_0_537 (.A1(registers_15__ap[26]), .A2(n_1_0_627), .B1( + n_1_0_611), .B2(registers_11__ap[26]), .ZN(n_1_0_510)); + AOI22_X1_LVT i_1_0_536 (.A1(registers_4__ap[26]), .A2(n_1_0_638), .B1( + n_1_0_636), .B2(registers_27__ap[26]), .ZN(n_1_0_509)); + AOI22_X1_LVT i_1_0_535 (.A1(registers_31__ap[26]), .A2(n_1_0_637), .B1( + n_1_0_618), .B2(registers_2__ap[26]), .ZN(n_1_0_508)); + NAND4_X1_LVT i_1_0_534 (.A1(n_1_0_511), .A2(n_1_0_510), .A3(n_1_0_509), + .A4(n_1_0_508), .ZN(n_1_0_507)); + AOI22_X1_LVT i_1_0_533 (.A1(registers_18__ap[26]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[26]), .ZN(n_1_0_506)); + AOI22_X1_LVT i_1_0_532 (.A1(registers_5__ap[26]), .A2(n_1_0_635), .B1( + n_1_0_632), .B2(registers_12__ap[26]), .ZN(n_1_0_505)); + AOI22_X1_LVT i_1_0_531 (.A1(registers_6__ap[26]), .A2(n_1_0_616), .B1( + n_1_0_614), .B2(registers_16__ap[26]), .ZN(n_1_0_504)); + AOI22_X1_LVT i_1_0_530 (.A1(registers_22__ap[26]), .A2(n_1_0_642), .B1( + n_1_0_620), .B2(registers_25__ap[26]), .ZN(n_1_0_503)); + NAND4_X1_LVT i_1_0_529 (.A1(n_1_0_506), .A2(n_1_0_505), .A3(n_1_0_504), + .A4(n_1_0_503), .ZN(n_1_0_502)); + AOI22_X1_LVT i_1_0_528 (.A1(registers_29__ap[26]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[26]), .ZN(n_1_0_501)); + AOI22_X1_LVT i_1_0_527 (.A1(registers_7__ap[26]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[26]), .ZN(n_1_0_500)); + AOI22_X1_LVT i_1_0_526 (.A1(registers_8__ap[26]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[26]), .ZN(n_1_0_499)); + AOI22_X1_LVT i_1_0_525 (.A1(registers_10__ap[26]), .A2(n_1_0_624), .B1( + n_1_0_610), .B2(registers_3__ap[26]), .ZN(n_1_0_498)); + NAND4_X1_LVT i_1_0_524 (.A1(n_1_0_501), .A2(n_1_0_500), .A3(n_1_0_499), + .A4(n_1_0_498), .ZN(n_1_0_497)); + NOR3_X1_LVT i_1_0_523 (.A1(n_1_0_507), .A2(n_1_0_502), .A3(n_1_0_497), + .ZN(n_1_0_496)); + NAND4_X1_LVT i_1_0_522 (.A1(n_1_0_514), .A2(n_1_0_513), .A3(n_1_0_512), + .A4(n_1_0_496), .ZN(RRs2[26])); + AOI22_X1_LVT i_1_0_520 (.A1(registers_5__ap[25]), .A2(n_1_0_635), .B1( + n_1_0_634), .B2(registers_28__ap[25]), .ZN(n_1_0_494)); + AOI22_X1_LVT i_1_0_521 (.A1(registers_8__ap[25]), .A2(n_1_0_626), .B1( + n_1_0_620), .B2(registers_25__ap[25]), .ZN(n_1_0_495)); + AOI22_X1_LVT i_1_0_519 (.A1(registers_14__ap[25]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[25]), .ZN(n_1_0_493)); + AOI22_X1_LVT i_1_0_518 (.A1(registers_16__ap[25]), .A2(n_1_0_614), .B1( + n_1_0_611), .B2(registers_11__ap[25]), .ZN(n_1_0_492)); + NAND3_X1_LVT i_1_0_517 (.A1(n_1_0_495), .A2(n_1_0_493), .A3(n_1_0_492), + .ZN(n_1_0_491)); + AOI221_X1_LVT i_1_0_516 (.A(n_1_0_491), .B1(n_1_0_624), .B2( + registers_10__ap[25]), .C1(registers_6__ap[25]), .C2(n_1_0_616), .ZN( + n_1_0_490)); + AOI222_X1_LVT i_1_0_515 (.A1(registers_1__ap[25]), .A2(n_1_0_644), .B1( + n_1_0_640), .B2(registers_26__ap[25]), .C1(n_1_0_622), .C2( + registers_30__ap[25]), .ZN(n_1_0_489)); + NAND2_X1_LVT i_1_0_514 (.A1(n_1_0_490), .A2(n_1_0_489), .ZN(n_1_0_488)); + AOI221_X1_LVT i_1_0_513 (.A(n_1_0_488), .B1(n_1_0_649), .B2( + registers_29__ap[25]), .C1(registers_2__ap[25]), .C2(n_1_0_618), .ZN( + n_1_0_487)); + AOI22_X1_LVT i_1_0_512 (.A1(registers_12__ap[25]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[25]), .ZN(n_1_0_486)); + AOI22_X1_LVT i_1_0_511 (.A1(registers_22__ap[25]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[25]), .ZN(n_1_0_485)); + AOI22_X1_LVT i_1_0_510 (.A1(registers_4__ap[25]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[25]), .ZN(n_1_0_484)); + NAND3_X1_LVT i_1_0_509 (.A1(n_1_0_486), .A2(n_1_0_485), .A3(n_1_0_484), + .ZN(n_1_0_483)); + AOI221_X1_LVT i_1_0_508 (.A(n_1_0_483), .B1(n_1_0_633), .B2( + registers_19__ap[25]), .C1(registers_18__ap[25]), .C2(n_1_0_646), .ZN( + n_1_0_482)); + AOI22_X1_LVT i_1_0_507 (.A1(registers_15__ap[25]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[25]), .ZN(n_1_0_481)); + AOI22_X1_LVT i_1_0_506 (.A1(registers_23__ap[25]), .A2(n_1_0_615), .B1( + n_1_0_610), .B2(registers_3__ap[25]), .ZN(n_1_0_480)); + AOI22_X1_LVT i_1_0_505 (.A1(registers_13__ap[25]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[25]), .ZN(n_1_0_479)); + NAND3_X1_LVT i_1_0_504 (.A1(n_1_0_481), .A2(n_1_0_480), .A3(n_1_0_479), + .ZN(n_1_0_478)); + AOI221_X1_LVT i_1_0_503 (.A(n_1_0_478), .B1(n_1_0_636), .B2( + registers_27__ap[25]), .C1(registers_31__ap[25]), .C2(n_1_0_637), .ZN( + n_1_0_477)); + NAND4_X1_LVT i_1_0_502 (.A1(n_1_0_494), .A2(n_1_0_487), .A3(n_1_0_482), + .A4(n_1_0_477), .ZN(RRs2[25])); + AOI22_X1_LVT i_1_0_501 (.A1(registers_17__ap[24]), .A2(n_1_0_629), .B1( + n_1_0_612), .B2(registers_21__ap[24]), .ZN(n_1_0_476)); + AOI222_X1_LVT i_1_0_500 (.A1(registers_13__ap[24]), .A2(n_1_0_631), .B1( + n_1_0_622), .B2(registers_30__ap[24]), .C1(registers_26__ap[24]), .C2( + n_1_0_640), .ZN(n_1_0_475)); + AOI22_X1_LVT i_1_0_499 (.A1(registers_1__ap[24]), .A2(n_1_0_644), .B1( + n_1_0_634), .B2(registers_28__ap[24]), .ZN(n_1_0_474)); + AOI22_X1_LVT i_1_0_498 (.A1(registers_24__ap[24]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[24]), .ZN(n_1_0_473)); + AOI22_X1_LVT i_1_0_497 (.A1(registers_8__ap[24]), .A2(n_1_0_626), .B1( + n_1_0_616), .B2(registers_6__ap[24]), .ZN(n_1_0_472)); + AOI22_X1_LVT i_1_0_496 (.A1(registers_4__ap[24]), .A2(n_1_0_638), .B1( + n_1_0_611), .B2(registers_11__ap[24]), .ZN(n_1_0_471)); + AOI22_X1_LVT i_1_0_495 (.A1(registers_10__ap[24]), .A2(n_1_0_624), .B1( + n_1_0_618), .B2(registers_2__ap[24]), .ZN(n_1_0_470)); + NAND4_X1_LVT i_1_0_494 (.A1(n_1_0_473), .A2(n_1_0_472), .A3(n_1_0_471), + .A4(n_1_0_470), .ZN(n_1_0_469)); + AOI22_X1_LVT i_1_0_493 (.A1(registers_18__ap[24]), .A2(n_1_0_646), .B1( + n_1_0_633), .B2(registers_19__ap[24]), .ZN(n_1_0_468)); + AOI22_X1_LVT i_1_0_492 (.A1(registers_5__ap[24]), .A2(n_1_0_635), .B1( + n_1_0_632), .B2(registers_12__ap[24]), .ZN(n_1_0_467)); + AOI22_X1_LVT i_1_0_491 (.A1(registers_15__ap[24]), .A2(n_1_0_627), .B1( + n_1_0_614), .B2(registers_16__ap[24]), .ZN(n_1_0_466)); + AOI22_X1_LVT i_1_0_490 (.A1(registers_22__ap[24]), .A2(n_1_0_642), .B1( + n_1_0_620), .B2(registers_25__ap[24]), .ZN(n_1_0_465)); + NAND4_X1_LVT i_1_0_489 (.A1(n_1_0_468), .A2(n_1_0_467), .A3(n_1_0_466), + .A4(n_1_0_465), .ZN(n_1_0_464)); + AOI22_X1_LVT i_1_0_488 (.A1(registers_29__ap[24]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[24]), .ZN(n_1_0_463)); + AOI22_X1_LVT i_1_0_487 (.A1(registers_7__ap[24]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[24]), .ZN(n_1_0_462)); + AOI22_X1_LVT i_1_0_486 (.A1(registers_23__ap[24]), .A2(n_1_0_615), .B1( + n_1_0_610), .B2(registers_3__ap[24]), .ZN(n_1_0_461)); + AOI22_X1_LVT i_1_0_485 (.A1(registers_31__ap[24]), .A2(n_1_0_637), .B1( + n_1_0_636), .B2(registers_27__ap[24]), .ZN(n_1_0_460)); + NAND4_X1_LVT i_1_0_484 (.A1(n_1_0_463), .A2(n_1_0_462), .A3(n_1_0_461), + .A4(n_1_0_460), .ZN(n_1_0_459)); + NOR3_X1_LVT i_1_0_483 (.A1(n_1_0_469), .A2(n_1_0_464), .A3(n_1_0_459), + .ZN(n_1_0_458)); + NAND4_X1_LVT i_1_0_482 (.A1(n_1_0_476), .A2(n_1_0_475), .A3(n_1_0_474), + .A4(n_1_0_458), .ZN(RRs2[24])); + AOI22_X1_LVT i_1_0_481 (.A1(registers_4__ap[23]), .A2(n_1_0_638), .B1( + n_1_0_634), .B2(registers_28__ap[23]), .ZN(n_1_0_457)); + AOI222_X1_LVT i_1_0_480 (.A1(registers_18__ap[23]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[23]), .C1(n_1_0_644), .C2( + registers_1__ap[23]), .ZN(n_1_0_456)); + AOI22_X1_LVT i_1_0_479 (.A1(registers_29__ap[23]), .A2(n_1_0_649), .B1( + n_1_0_618), .B2(registers_2__ap[23]), .ZN(n_1_0_455)); + AOI22_X1_LVT i_1_0_478 (.A1(registers_14__ap[23]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[23]), .ZN(n_1_0_454)); + AOI22_X1_LVT i_1_0_477 (.A1(registers_16__ap[23]), .A2(n_1_0_614), .B1( + n_1_0_611), .B2(registers_11__ap[23]), .ZN(n_1_0_453)); + AOI22_X1_LVT i_1_0_476 (.A1(registers_27__ap[23]), .A2(n_1_0_636), .B1( + n_1_0_620), .B2(registers_25__ap[23]), .ZN(n_1_0_452)); + AOI22_X1_LVT i_1_0_475 (.A1(registers_31__ap[23]), .A2(n_1_0_637), .B1( + n_1_0_616), .B2(registers_6__ap[23]), .ZN(n_1_0_451)); + NAND4_X1_LVT i_1_0_474 (.A1(n_1_0_454), .A2(n_1_0_453), .A3(n_1_0_452), + .A4(n_1_0_451), .ZN(n_1_0_450)); + AOI22_X1_LVT i_1_0_473 (.A1(registers_26__ap[23]), .A2(n_1_0_640), .B1( + n_1_0_633), .B2(registers_19__ap[23]), .ZN(n_1_0_449)); + AOI22_X1_LVT i_1_0_472 (.A1(registers_12__ap[23]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[23]), .ZN(n_1_0_448)); + AOI22_X1_LVT i_1_0_471 (.A1(registers_22__ap[23]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[23]), .ZN(n_1_0_447)); + AOI22_X1_LVT i_1_0_470 (.A1(registers_5__ap[23]), .A2(n_1_0_635), .B1( + n_1_0_613), .B2(registers_20__ap[23]), .ZN(n_1_0_446)); + NAND4_X1_LVT i_1_0_469 (.A1(n_1_0_449), .A2(n_1_0_448), .A3(n_1_0_447), + .A4(n_1_0_446), .ZN(n_1_0_445)); + AOI22_X1_LVT i_1_0_468 (.A1(registers_15__ap[23]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[23]), .ZN(n_1_0_444)); + AOI22_X1_LVT i_1_0_467 (.A1(registers_8__ap[23]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[23]), .ZN(n_1_0_443)); + AOI22_X1_LVT i_1_0_466 (.A1(registers_13__ap[23]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[23]), .ZN(n_1_0_442)); + AOI22_X1_LVT i_1_0_465 (.A1(registers_10__ap[23]), .A2(n_1_0_624), .B1( + n_1_0_610), .B2(registers_3__ap[23]), .ZN(n_1_0_441)); + NAND4_X1_LVT i_1_0_464 (.A1(n_1_0_444), .A2(n_1_0_443), .A3(n_1_0_442), + .A4(n_1_0_441), .ZN(n_1_0_440)); + NOR3_X1_LVT i_1_0_463 (.A1(n_1_0_450), .A2(n_1_0_445), .A3(n_1_0_440), + .ZN(n_1_0_439)); + NAND4_X1_LVT i_1_0_462 (.A1(n_1_0_457), .A2(n_1_0_456), .A3(n_1_0_455), + .A4(n_1_0_439), .ZN(RRs2[23])); + AOI22_X1_LVT i_1_0_460 (.A1(registers_17__ap[22]), .A2(n_1_0_629), .B1( + n_1_0_612), .B2(registers_21__ap[22]), .ZN(n_1_0_437)); + AOI22_X1_LVT i_1_0_461 (.A1(registers_15__ap[22]), .A2(n_1_0_627), .B1( + n_1_0_626), .B2(registers_8__ap[22]), .ZN(n_1_0_438)); + AOI22_X1_LVT i_1_0_459 (.A1(registers_24__ap[22]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[22]), .ZN(n_1_0_436)); + AOI22_X1_LVT i_1_0_458 (.A1(registers_5__ap[22]), .A2(n_1_0_635), .B1( + n_1_0_611), .B2(registers_11__ap[22]), .ZN(n_1_0_435)); + NAND3_X1_LVT i_1_0_457 (.A1(n_1_0_438), .A2(n_1_0_436), .A3(n_1_0_435), + .ZN(n_1_0_434)); + AOI221_X1_LVT i_1_0_456 (.A(n_1_0_434), .B1(n_1_0_618), .B2( + registers_2__ap[22]), .C1(registers_10__ap[22]), .C2(n_1_0_624), .ZN( + n_1_0_433)); + AOI222_X1_LVT i_1_0_455 (.A1(registers_26__ap[22]), .A2(n_1_0_640), .B1( + n_1_0_622), .B2(registers_30__ap[22]), .C1(n_1_0_631), .C2( + registers_13__ap[22]), .ZN(n_1_0_432)); + NAND2_X1_LVT i_1_0_454 (.A1(n_1_0_433), .A2(n_1_0_432), .ZN(n_1_0_431)); + AOI221_X1_LVT i_1_0_453 (.A(n_1_0_431), .B1(n_1_0_644), .B2( + registers_1__ap[22]), .C1(registers_28__ap[22]), .C2(n_1_0_634), .ZN( + n_1_0_430)); + AOI22_X1_LVT i_1_0_452 (.A1(registers_18__ap[22]), .A2(n_1_0_646), .B1( + n_1_0_633), .B2(registers_19__ap[22]), .ZN(n_1_0_429)); + AOI22_X1_LVT i_1_0_451 (.A1(registers_4__ap[22]), .A2(n_1_0_638), .B1( + n_1_0_632), .B2(registers_12__ap[22]), .ZN(n_1_0_428)); + AOI22_X1_LVT i_1_0_450 (.A1(registers_6__ap[22]), .A2(n_1_0_616), .B1( + n_1_0_614), .B2(registers_16__ap[22]), .ZN(n_1_0_427)); + NAND3_X1_LVT i_1_0_449 (.A1(n_1_0_429), .A2(n_1_0_428), .A3(n_1_0_427), + .ZN(n_1_0_426)); + AOI221_X1_LVT i_1_0_448 (.A(n_1_0_426), .B1(n_1_0_620), .B2( + registers_25__ap[22]), .C1(registers_22__ap[22]), .C2(n_1_0_642), .ZN( + n_1_0_425)); + AOI22_X1_LVT i_1_0_447 (.A1(registers_29__ap[22]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[22]), .ZN(n_1_0_424)); + AOI22_X1_LVT i_1_0_446 (.A1(registers_7__ap[22]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[22]), .ZN(n_1_0_423)); + AOI22_X1_LVT i_1_0_445 (.A1(registers_23__ap[22]), .A2(n_1_0_615), .B1( + n_1_0_610), .B2(registers_3__ap[22]), .ZN(n_1_0_422)); + NAND3_X1_LVT i_1_0_444 (.A1(n_1_0_424), .A2(n_1_0_423), .A3(n_1_0_422), + .ZN(n_1_0_421)); + AOI221_X1_LVT i_1_0_443 (.A(n_1_0_421), .B1(n_1_0_636), .B2( + registers_27__ap[22]), .C1(registers_31__ap[22]), .C2(n_1_0_637), .ZN( + n_1_0_420)); + NAND4_X1_LVT i_1_0_442 (.A1(n_1_0_437), .A2(n_1_0_430), .A3(n_1_0_425), + .A4(n_1_0_420), .ZN(RRs2[22])); + AOI22_X1_LVT i_1_0_441 (.A1(registers_5__ap[21]), .A2(n_1_0_635), .B1( + n_1_0_634), .B2(registers_28__ap[21]), .ZN(n_1_0_419)); + AOI222_X1_LVT i_1_0_440 (.A1(registers_1__ap[21]), .A2(n_1_0_644), .B1( + n_1_0_640), .B2(registers_26__ap[21]), .C1(n_1_0_622), .C2( + registers_30__ap[21]), .ZN(n_1_0_418)); + AOI22_X1_LVT i_1_0_439 (.A1(registers_29__ap[21]), .A2(n_1_0_649), .B1( + n_1_0_618), .B2(registers_2__ap[21]), .ZN(n_1_0_417)); + AOI22_X1_LVT i_1_0_438 (.A1(registers_14__ap[21]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[21]), .ZN(n_1_0_416)); + AOI22_X1_LVT i_1_0_437 (.A1(registers_8__ap[21]), .A2(n_1_0_626), .B1( + n_1_0_614), .B2(registers_16__ap[21]), .ZN(n_1_0_415)); + AOI22_X1_LVT i_1_0_436 (.A1(registers_25__ap[21]), .A2(n_1_0_620), .B1( + n_1_0_611), .B2(registers_11__ap[21]), .ZN(n_1_0_414)); + AOI22_X1_LVT i_1_0_435 (.A1(registers_10__ap[21]), .A2(n_1_0_624), .B1( + n_1_0_616), .B2(registers_6__ap[21]), .ZN(n_1_0_413)); + NAND4_X1_LVT i_1_0_434 (.A1(n_1_0_416), .A2(n_1_0_415), .A3(n_1_0_414), + .A4(n_1_0_413), .ZN(n_1_0_412)); + AOI22_X1_LVT i_1_0_433 (.A1(registers_12__ap[21]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[21]), .ZN(n_1_0_411)); + AOI22_X1_LVT i_1_0_432 (.A1(registers_22__ap[21]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[21]), .ZN(n_1_0_410)); + AOI22_X1_LVT i_1_0_431 (.A1(registers_4__ap[21]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[21]), .ZN(n_1_0_409)); + AOI22_X1_LVT i_1_0_430 (.A1(registers_18__ap[21]), .A2(n_1_0_646), .B1( + n_1_0_633), .B2(registers_19__ap[21]), .ZN(n_1_0_408)); + NAND4_X1_LVT i_1_0_429 (.A1(n_1_0_411), .A2(n_1_0_410), .A3(n_1_0_409), + .A4(n_1_0_408), .ZN(n_1_0_407)); + AOI22_X1_LVT i_1_0_428 (.A1(registers_15__ap[21]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[21]), .ZN(n_1_0_406)); + AOI22_X1_LVT i_1_0_427 (.A1(registers_23__ap[21]), .A2(n_1_0_615), .B1( + n_1_0_610), .B2(registers_3__ap[21]), .ZN(n_1_0_405)); + AOI22_X1_LVT i_1_0_426 (.A1(registers_13__ap[21]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[21]), .ZN(n_1_0_404)); + AOI22_X1_LVT i_1_0_425 (.A1(registers_31__ap[21]), .A2(n_1_0_637), .B1( + n_1_0_636), .B2(registers_27__ap[21]), .ZN(n_1_0_403)); + NAND4_X1_LVT i_1_0_424 (.A1(n_1_0_406), .A2(n_1_0_405), .A3(n_1_0_404), + .A4(n_1_0_403), .ZN(n_1_0_402)); + NOR3_X1_LVT i_1_0_423 (.A1(n_1_0_412), .A2(n_1_0_407), .A3(n_1_0_402), + .ZN(n_1_0_401)); + NAND4_X1_LVT i_1_0_422 (.A1(n_1_0_419), .A2(n_1_0_418), .A3(n_1_0_417), + .A4(n_1_0_401), .ZN(RRs2[21])); + AOI22_X1_LVT i_1_0_421 (.A1(registers_17__ap[20]), .A2(n_1_0_629), .B1( + n_1_0_612), .B2(registers_21__ap[20]), .ZN(n_1_0_400)); + AOI222_X1_LVT i_1_0_420 (.A1(registers_13__ap[20]), .A2(n_1_0_631), .B1( + n_1_0_622), .B2(registers_30__ap[20]), .C1(registers_19__ap[20]), .C2( + n_1_0_633), .ZN(n_1_0_399)); + AOI22_X1_LVT i_1_0_419 (.A1(registers_1__ap[20]), .A2(n_1_0_644), .B1( + n_1_0_634), .B2(registers_28__ap[20]), .ZN(n_1_0_398)); + AOI22_X1_LVT i_1_0_418 (.A1(registers_24__ap[20]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[20]), .ZN(n_1_0_397)); + AOI22_X1_LVT i_1_0_417 (.A1(registers_6__ap[20]), .A2(n_1_0_616), .B1( + n_1_0_611), .B2(registers_11__ap[20]), .ZN(n_1_0_396)); + AOI22_X1_LVT i_1_0_416 (.A1(registers_4__ap[20]), .A2(n_1_0_638), .B1( + n_1_0_624), .B2(registers_10__ap[20]), .ZN(n_1_0_395)); + AOI22_X1_LVT i_1_0_415 (.A1(registers_31__ap[20]), .A2(n_1_0_637), .B1( + n_1_0_618), .B2(registers_2__ap[20]), .ZN(n_1_0_394)); + NAND4_X1_LVT i_1_0_414 (.A1(n_1_0_397), .A2(n_1_0_396), .A3(n_1_0_395), + .A4(n_1_0_394), .ZN(n_1_0_393)); + AOI22_X1_LVT i_1_0_413 (.A1(registers_18__ap[20]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[20]), .ZN(n_1_0_392)); + AOI22_X1_LVT i_1_0_412 (.A1(registers_5__ap[20]), .A2(n_1_0_635), .B1( + n_1_0_632), .B2(registers_12__ap[20]), .ZN(n_1_0_391)); + AOI22_X1_LVT i_1_0_411 (.A1(registers_15__ap[20]), .A2(n_1_0_627), .B1( + n_1_0_614), .B2(registers_16__ap[20]), .ZN(n_1_0_390)); + AOI22_X1_LVT i_1_0_410 (.A1(registers_22__ap[20]), .A2(n_1_0_642), .B1( + n_1_0_620), .B2(registers_25__ap[20]), .ZN(n_1_0_389)); + NAND4_X1_LVT i_1_0_409 (.A1(n_1_0_392), .A2(n_1_0_391), .A3(n_1_0_390), + .A4(n_1_0_389), .ZN(n_1_0_388)); + AOI22_X1_LVT i_1_0_408 (.A1(registers_29__ap[20]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[20]), .ZN(n_1_0_387)); + AOI22_X1_LVT i_1_0_407 (.A1(registers_7__ap[20]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[20]), .ZN(n_1_0_386)); + AOI22_X1_LVT i_1_0_406 (.A1(registers_8__ap[20]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[20]), .ZN(n_1_0_385)); + AOI22_X1_LVT i_1_0_405 (.A1(registers_27__ap[20]), .A2(n_1_0_636), .B1( + n_1_0_610), .B2(registers_3__ap[20]), .ZN(n_1_0_384)); + NAND4_X1_LVT i_1_0_404 (.A1(n_1_0_387), .A2(n_1_0_386), .A3(n_1_0_385), + .A4(n_1_0_384), .ZN(n_1_0_383)); + NOR3_X1_LVT i_1_0_403 (.A1(n_1_0_393), .A2(n_1_0_388), .A3(n_1_0_383), + .ZN(n_1_0_382)); + NAND4_X1_LVT i_1_0_402 (.A1(n_1_0_400), .A2(n_1_0_399), .A3(n_1_0_398), + .A4(n_1_0_382), .ZN(RRs2[20])); + AOI22_X1_LVT i_1_0_401 (.A1(registers_17__ap[19]), .A2(n_1_0_629), .B1( + n_1_0_612), .B2(registers_21__ap[19]), .ZN(n_1_0_381)); + AOI222_X1_LVT i_1_0_400 (.A1(registers_13__ap[19]), .A2(n_1_0_631), .B1( + n_1_0_622), .B2(registers_30__ap[19]), .C1(registers_19__ap[19]), .C2( + n_1_0_633), .ZN(n_1_0_380)); + AOI22_X1_LVT i_1_0_399 (.A1(registers_1__ap[19]), .A2(n_1_0_644), .B1( + n_1_0_634), .B2(registers_28__ap[19]), .ZN(n_1_0_379)); + AOI22_X1_LVT i_1_0_398 (.A1(registers_24__ap[19]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[19]), .ZN(n_1_0_378)); + AOI22_X1_LVT i_1_0_397 (.A1(registers_15__ap[19]), .A2(n_1_0_627), .B1( + n_1_0_611), .B2(registers_11__ap[19]), .ZN(n_1_0_377)); + AOI22_X1_LVT i_1_0_396 (.A1(registers_4__ap[19]), .A2(n_1_0_638), .B1( + n_1_0_636), .B2(registers_27__ap[19]), .ZN(n_1_0_376)); + AOI22_X1_LVT i_1_0_395 (.A1(registers_31__ap[19]), .A2(n_1_0_637), .B1( + n_1_0_618), .B2(registers_2__ap[19]), .ZN(n_1_0_375)); + NAND4_X1_LVT i_1_0_394 (.A1(n_1_0_378), .A2(n_1_0_377), .A3(n_1_0_376), + .A4(n_1_0_375), .ZN(n_1_0_374)); + AOI22_X1_LVT i_1_0_393 (.A1(registers_18__ap[19]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[19]), .ZN(n_1_0_373)); + AOI22_X1_LVT i_1_0_392 (.A1(registers_5__ap[19]), .A2(n_1_0_635), .B1( + n_1_0_632), .B2(registers_12__ap[19]), .ZN(n_1_0_372)); + AOI22_X1_LVT i_1_0_391 (.A1(registers_25__ap[19]), .A2(n_1_0_620), .B1( + n_1_0_616), .B2(registers_6__ap[19]), .ZN(n_1_0_371)); + AOI22_X1_LVT i_1_0_390 (.A1(registers_22__ap[19]), .A2(n_1_0_642), .B1( + n_1_0_614), .B2(registers_16__ap[19]), .ZN(n_1_0_370)); + NAND4_X1_LVT i_1_0_389 (.A1(n_1_0_373), .A2(n_1_0_372), .A3(n_1_0_371), + .A4(n_1_0_370), .ZN(n_1_0_369)); + AOI22_X1_LVT i_1_0_388 (.A1(registers_29__ap[19]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[19]), .ZN(n_1_0_368)); + AOI22_X1_LVT i_1_0_387 (.A1(registers_7__ap[19]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[19]), .ZN(n_1_0_367)); + AOI22_X1_LVT i_1_0_386 (.A1(registers_8__ap[19]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[19]), .ZN(n_1_0_366)); + AOI22_X1_LVT i_1_0_385 (.A1(registers_10__ap[19]), .A2(n_1_0_624), .B1( + n_1_0_610), .B2(registers_3__ap[19]), .ZN(n_1_0_365)); + NAND4_X1_LVT i_1_0_384 (.A1(n_1_0_368), .A2(n_1_0_367), .A3(n_1_0_366), + .A4(n_1_0_365), .ZN(n_1_0_364)); + NOR3_X1_LVT i_1_0_383 (.A1(n_1_0_374), .A2(n_1_0_369), .A3(n_1_0_364), + .ZN(n_1_0_363)); + NAND4_X1_LVT i_1_0_382 (.A1(n_1_0_381), .A2(n_1_0_380), .A3(n_1_0_379), + .A4(n_1_0_363), .ZN(RRs2[19])); + AOI22_X1_LVT i_1_0_380 (.A1(registers_4__ap[18]), .A2(n_1_0_638), .B1( + n_1_0_634), .B2(registers_28__ap[18]), .ZN(n_1_0_361)); + AOI22_X1_LVT i_1_0_381 (.A1(registers_8__ap[18]), .A2(n_1_0_626), .B1( + n_1_0_614), .B2(registers_16__ap[18]), .ZN(n_1_0_362)); + AOI22_X1_LVT i_1_0_379 (.A1(registers_14__ap[18]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[18]), .ZN(n_1_0_360)); + AOI22_X1_LVT i_1_0_378 (.A1(registers_25__ap[18]), .A2(n_1_0_620), .B1( + n_1_0_611), .B2(registers_11__ap[18]), .ZN(n_1_0_359)); + NAND3_X1_LVT i_1_0_377 (.A1(n_1_0_362), .A2(n_1_0_360), .A3(n_1_0_359), + .ZN(n_1_0_358)); + AOI221_X1_LVT i_1_0_376 (.A(n_1_0_358), .B1(n_1_0_624), .B2( + registers_10__ap[18]), .C1(registers_6__ap[18]), .C2(n_1_0_616), .ZN( + n_1_0_357)); + AOI222_X1_LVT i_1_0_375 (.A1(registers_1__ap[18]), .A2(n_1_0_644), .B1( + n_1_0_640), .B2(registers_26__ap[18]), .C1(n_1_0_622), .C2( + registers_30__ap[18]), .ZN(n_1_0_356)); + NAND2_X1_LVT i_1_0_374 (.A1(n_1_0_357), .A2(n_1_0_356), .ZN(n_1_0_355)); + AOI221_X1_LVT i_1_0_373 (.A(n_1_0_355), .B1(n_1_0_649), .B2( + registers_29__ap[18]), .C1(registers_2__ap[18]), .C2(n_1_0_618), .ZN( + n_1_0_354)); + AOI22_X1_LVT i_1_0_372 (.A1(registers_18__ap[18]), .A2(n_1_0_646), .B1( + n_1_0_633), .B2(registers_19__ap[18]), .ZN(n_1_0_353)); + AOI22_X1_LVT i_1_0_371 (.A1(registers_12__ap[18]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[18]), .ZN(n_1_0_352)); + AOI22_X1_LVT i_1_0_370 (.A1(registers_22__ap[18]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[18]), .ZN(n_1_0_351)); + NAND3_X1_LVT i_1_0_369 (.A1(n_1_0_353), .A2(n_1_0_352), .A3(n_1_0_351), + .ZN(n_1_0_350)); + AOI221_X1_LVT i_1_0_368 (.A(n_1_0_350), .B1(n_1_0_635), .B2( + registers_5__ap[18]), .C1(registers_20__ap[18]), .C2(n_1_0_613), .ZN( + n_1_0_349)); + AOI22_X1_LVT i_1_0_367 (.A1(registers_15__ap[18]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[18]), .ZN(n_1_0_348)); + AOI22_X1_LVT i_1_0_366 (.A1(registers_23__ap[18]), .A2(n_1_0_615), .B1( + n_1_0_610), .B2(registers_3__ap[18]), .ZN(n_1_0_347)); + AOI22_X1_LVT i_1_0_365 (.A1(registers_13__ap[18]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[18]), .ZN(n_1_0_346)); + NAND3_X1_LVT i_1_0_364 (.A1(n_1_0_348), .A2(n_1_0_347), .A3(n_1_0_346), + .ZN(n_1_0_345)); + AOI221_X1_LVT i_1_0_363 (.A(n_1_0_345), .B1(n_1_0_637), .B2( + registers_31__ap[18]), .C1(registers_27__ap[18]), .C2(n_1_0_636), .ZN( + n_1_0_344)); + NAND4_X1_LVT i_1_0_362 (.A1(n_1_0_361), .A2(n_1_0_354), .A3(n_1_0_349), + .A4(n_1_0_344), .ZN(RRs2[18])); + AOI22_X1_LVT i_1_0_358 (.A1(registers_4__ap[17]), .A2(n_1_0_638), .B1( + n_1_0_634), .B2(registers_28__ap[17]), .ZN(n_1_0_340)); + AOI22_X1_LVT i_1_0_361 (.A1(registers_31__ap[17]), .A2(n_1_0_637), .B1( + n_1_0_616), .B2(registers_6__ap[17]), .ZN(n_1_0_343)); + AOI22_X1_LVT i_1_0_357 (.A1(registers_14__ap[17]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[17]), .ZN(n_1_0_339)); + AOI22_X1_LVT i_1_0_360 (.A1(registers_25__ap[17]), .A2(n_1_0_620), .B1( + n_1_0_611), .B2(registers_11__ap[17]), .ZN(n_1_0_342)); + INV_X1_LVT i_1_0_359 (.A(n_1_0_342), .ZN(n_1_0_341)); + AOI221_X1_LVT i_1_0_356 (.A(n_1_0_341), .B1(n_1_0_614), .B2( + registers_16__ap[17]), .C1(registers_10__ap[17]), .C2(n_1_0_624), .ZN( + n_1_0_338)); + AOI222_X1_LVT i_1_0_355 (.A1(registers_1__ap[17]), .A2(n_1_0_644), .B1( + n_1_0_622), .B2(registers_30__ap[17]), .C1(registers_18__ap[17]), .C2( + n_1_0_646), .ZN(n_1_0_337)); + NAND4_X1_LVT i_1_0_354 (.A1(n_1_0_343), .A2(n_1_0_339), .A3(n_1_0_338), + .A4(n_1_0_337), .ZN(n_1_0_336)); + AOI221_X1_LVT i_1_0_353 (.A(n_1_0_336), .B1(n_1_0_649), .B2( + registers_29__ap[17]), .C1(registers_2__ap[17]), .C2(n_1_0_618), .ZN( + n_1_0_335)); + AOI22_X1_LVT i_1_0_352 (.A1(registers_26__ap[17]), .A2(n_1_0_640), .B1( + n_1_0_633), .B2(registers_19__ap[17]), .ZN(n_1_0_334)); + AOI22_X1_LVT i_1_0_351 (.A1(registers_12__ap[17]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[17]), .ZN(n_1_0_333)); + AOI22_X1_LVT i_1_0_350 (.A1(registers_22__ap[17]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[17]), .ZN(n_1_0_332)); + NAND3_X1_LVT i_1_0_349 (.A1(n_1_0_334), .A2(n_1_0_333), .A3(n_1_0_332), + .ZN(n_1_0_331)); + AOI221_X1_LVT i_1_0_348 (.A(n_1_0_331), .B1(n_1_0_635), .B2( + registers_5__ap[17]), .C1(registers_20__ap[17]), .C2(n_1_0_613), .ZN( + n_1_0_330)); + AOI22_X1_LVT i_1_0_347 (.A1(registers_15__ap[17]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[17]), .ZN(n_1_0_329)); + AOI22_X1_LVT i_1_0_346 (.A1(registers_8__ap[17]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[17]), .ZN(n_1_0_328)); + AOI22_X1_LVT i_1_0_345 (.A1(registers_13__ap[17]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[17]), .ZN(n_1_0_327)); + NAND3_X1_LVT i_1_0_344 (.A1(n_1_0_329), .A2(n_1_0_328), .A3(n_1_0_327), + .ZN(n_1_0_326)); + AOI221_X1_LVT i_1_0_343 (.A(n_1_0_326), .B1(n_1_0_636), .B2( + registers_27__ap[17]), .C1(registers_3__ap[17]), .C2(n_1_0_610), .ZN( + n_1_0_325)); + NAND4_X1_LVT i_1_0_342 (.A1(n_1_0_340), .A2(n_1_0_335), .A3(n_1_0_330), + .A4(n_1_0_325), .ZN(RRs2[17])); + AOI22_X1_LVT i_1_0_341 (.A1(registers_4__ap[16]), .A2(n_1_0_638), .B1( + n_1_0_634), .B2(registers_28__ap[16]), .ZN(n_1_0_324)); + AOI222_X1_LVT i_1_0_340 (.A1(registers_1__ap[16]), .A2(n_1_0_644), .B1( + n_1_0_633), .B2(registers_19__ap[16]), .C1(n_1_0_622), .C2( + registers_30__ap[16]), .ZN(n_1_0_323)); + AOI22_X1_LVT i_1_0_339 (.A1(registers_29__ap[16]), .A2(n_1_0_649), .B1( + n_1_0_618), .B2(registers_2__ap[16]), .ZN(n_1_0_322)); + AOI22_X1_LVT i_1_0_338 (.A1(registers_14__ap[16]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[16]), .ZN(n_1_0_321)); + AOI22_X1_LVT i_1_0_337 (.A1(registers_16__ap[16]), .A2(n_1_0_614), .B1( + n_1_0_611), .B2(registers_11__ap[16]), .ZN(n_1_0_320)); + AOI22_X1_LVT i_1_0_336 (.A1(registers_10__ap[16]), .A2(n_1_0_624), .B1( + n_1_0_620), .B2(registers_25__ap[16]), .ZN(n_1_0_319)); + AOI22_X1_LVT i_1_0_335 (.A1(registers_31__ap[16]), .A2(n_1_0_637), .B1( + n_1_0_616), .B2(registers_6__ap[16]), .ZN(n_1_0_318)); + NAND4_X1_LVT i_1_0_334 (.A1(n_1_0_321), .A2(n_1_0_320), .A3(n_1_0_319), + .A4(n_1_0_318), .ZN(n_1_0_317)); + AOI22_X1_LVT i_1_0_333 (.A1(registers_18__ap[16]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[16]), .ZN(n_1_0_316)); + AOI22_X1_LVT i_1_0_332 (.A1(registers_12__ap[16]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[16]), .ZN(n_1_0_315)); + AOI22_X1_LVT i_1_0_331 (.A1(registers_22__ap[16]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[16]), .ZN(n_1_0_314)); + AOI22_X1_LVT i_1_0_330 (.A1(registers_5__ap[16]), .A2(n_1_0_635), .B1( + n_1_0_613), .B2(registers_20__ap[16]), .ZN(n_1_0_313)); + NAND4_X1_LVT i_1_0_329 (.A1(n_1_0_316), .A2(n_1_0_315), .A3(n_1_0_314), + .A4(n_1_0_313), .ZN(n_1_0_312)); + AOI22_X1_LVT i_1_0_328 (.A1(registers_15__ap[16]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[16]), .ZN(n_1_0_311)); + AOI22_X1_LVT i_1_0_327 (.A1(registers_8__ap[16]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[16]), .ZN(n_1_0_310)); + AOI22_X1_LVT i_1_0_326 (.A1(registers_13__ap[16]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[16]), .ZN(n_1_0_309)); + AOI22_X1_LVT i_1_0_325 (.A1(registers_27__ap[16]), .A2(n_1_0_636), .B1( + n_1_0_610), .B2(registers_3__ap[16]), .ZN(n_1_0_308)); + NAND4_X1_LVT i_1_0_324 (.A1(n_1_0_311), .A2(n_1_0_310), .A3(n_1_0_309), + .A4(n_1_0_308), .ZN(n_1_0_307)); + NOR3_X1_LVT i_1_0_323 (.A1(n_1_0_317), .A2(n_1_0_312), .A3(n_1_0_307), + .ZN(n_1_0_306)); + NAND4_X1_LVT i_1_0_322 (.A1(n_1_0_324), .A2(n_1_0_323), .A3(n_1_0_322), + .A4(n_1_0_306), .ZN(RRs2[16])); + AOI22_X1_LVT i_1_0_320 (.A1(registers_5__ap[15]), .A2(n_1_0_635), .B1( + n_1_0_634), .B2(registers_28__ap[15]), .ZN(n_1_0_304)); + AOI22_X1_LVT i_1_0_321 (.A1(registers_8__ap[15]), .A2(n_1_0_626), .B1( + n_1_0_620), .B2(registers_25__ap[15]), .ZN(n_1_0_305)); + AOI22_X1_LVT i_1_0_319 (.A1(registers_14__ap[15]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[15]), .ZN(n_1_0_303)); + AOI22_X1_LVT i_1_0_318 (.A1(registers_16__ap[15]), .A2(n_1_0_614), .B1( + n_1_0_611), .B2(registers_11__ap[15]), .ZN(n_1_0_302)); + NAND3_X1_LVT i_1_0_317 (.A1(n_1_0_305), .A2(n_1_0_303), .A3(n_1_0_302), + .ZN(n_1_0_301)); + AOI221_X1_LVT i_1_0_316 (.A(n_1_0_301), .B1(n_1_0_616), .B2( + registers_6__ap[15]), .C1(registers_10__ap[15]), .C2(n_1_0_624), .ZN( + n_1_0_300)); + AOI222_X1_LVT i_1_0_315 (.A1(registers_1__ap[15]), .A2(n_1_0_644), .B1( + n_1_0_640), .B2(registers_26__ap[15]), .C1(n_1_0_622), .C2( + registers_30__ap[15]), .ZN(n_1_0_299)); + NAND2_X1_LVT i_1_0_314 (.A1(n_1_0_300), .A2(n_1_0_299), .ZN(n_1_0_298)); + AOI221_X1_LVT i_1_0_313 (.A(n_1_0_298), .B1(n_1_0_649), .B2( + registers_29__ap[15]), .C1(registers_2__ap[15]), .C2(n_1_0_618), .ZN( + n_1_0_297)); + AOI22_X1_LVT i_1_0_312 (.A1(registers_12__ap[15]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[15]), .ZN(n_1_0_296)); + AOI22_X1_LVT i_1_0_311 (.A1(registers_22__ap[15]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[15]), .ZN(n_1_0_295)); + AOI22_X1_LVT i_1_0_310 (.A1(registers_4__ap[15]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[15]), .ZN(n_1_0_294)); + NAND3_X1_LVT i_1_0_309 (.A1(n_1_0_296), .A2(n_1_0_295), .A3(n_1_0_294), + .ZN(n_1_0_293)); + AOI221_X1_LVT i_1_0_308 (.A(n_1_0_293), .B1(n_1_0_633), .B2( + registers_19__ap[15]), .C1(registers_18__ap[15]), .C2(n_1_0_646), .ZN( + n_1_0_292)); + AOI22_X1_LVT i_1_0_307 (.A1(registers_15__ap[15]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[15]), .ZN(n_1_0_291)); + AOI22_X1_LVT i_1_0_306 (.A1(registers_23__ap[15]), .A2(n_1_0_615), .B1( + n_1_0_610), .B2(registers_3__ap[15]), .ZN(n_1_0_290)); + AOI22_X1_LVT i_1_0_305 (.A1(registers_13__ap[15]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[15]), .ZN(n_1_0_289)); + NAND3_X1_LVT i_1_0_304 (.A1(n_1_0_291), .A2(n_1_0_290), .A3(n_1_0_289), + .ZN(n_1_0_288)); + AOI221_X1_LVT i_1_0_303 (.A(n_1_0_288), .B1(n_1_0_636), .B2( + registers_27__ap[15]), .C1(registers_31__ap[15]), .C2(n_1_0_637), .ZN( + n_1_0_287)); + NAND4_X1_LVT i_1_0_302 (.A1(n_1_0_304), .A2(n_1_0_297), .A3(n_1_0_292), + .A4(n_1_0_287), .ZN(RRs2[15])); + AOI22_X1_LVT i_1_0_301 (.A1(registers_28__ap[14]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[14]), .ZN(n_1_0_286)); + AOI222_X1_LVT i_1_0_300 (.A1(registers_18__ap[14]), .A2(n_1_0_646), .B1( + n_1_0_620), .B2(registers_25__ap[14]), .C1(n_1_0_618), .C2( + registers_2__ap[14]), .ZN(n_1_0_285)); + AOI22_X1_LVT i_1_0_299 (.A1(registers_24__ap[14]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[14]), .ZN(n_1_0_284)); + AOI22_X1_LVT i_1_0_298 (.A1(registers_15__ap[14]), .A2(n_1_0_627), .B1( + n_1_0_610), .B2(registers_3__ap[14]), .ZN(n_1_0_283)); + AOI22_X1_LVT i_1_0_297 (.A1(registers_4__ap[14]), .A2(n_1_0_638), .B1( + n_1_0_637), .B2(registers_31__ap[14]), .ZN(n_1_0_282)); + AOI22_X1_LVT i_1_0_296 (.A1(registers_29__ap[14]), .A2(n_1_0_649), .B1( + n_1_0_615), .B2(registers_23__ap[14]), .ZN(n_1_0_281)); + NAND4_X1_LVT i_1_0_295 (.A1(n_1_0_284), .A2(n_1_0_283), .A3(n_1_0_282), + .A4(n_1_0_281), .ZN(n_1_0_280)); + AOI221_X1_LVT i_1_0_294 (.A(n_1_0_280), .B1(n_1_0_644), .B2( + registers_1__ap[14]), .C1(registers_13__ap[14]), .C2(n_1_0_631), .ZN( + n_1_0_279)); + AOI22_X1_LVT i_1_0_293 (.A1(registers_17__ap[14]), .A2(n_1_0_629), .B1( + n_1_0_623), .B2(registers_7__ap[14]), .ZN(n_1_0_278)); + AOI22_X1_LVT i_1_0_292 (.A1(registers_5__ap[14]), .A2(n_1_0_635), .B1( + n_1_0_632), .B2(registers_12__ap[14]), .ZN(n_1_0_277)); + AOI22_X1_LVT i_1_0_291 (.A1(registers_10__ap[14]), .A2(n_1_0_624), .B1( + n_1_0_622), .B2(registers_30__ap[14]), .ZN(n_1_0_276)); + AOI22_X1_LVT i_1_0_290 (.A1(registers_26__ap[14]), .A2(n_1_0_640), .B1( + n_1_0_614), .B2(registers_16__ap[14]), .ZN(n_1_0_275)); + NAND4_X1_LVT i_1_0_289 (.A1(n_1_0_278), .A2(n_1_0_277), .A3(n_1_0_276), + .A4(n_1_0_275), .ZN(n_1_0_274)); + AOI22_X1_LVT i_1_0_288 (.A1(registers_9__ap[14]), .A2(n_1_0_617), .B1( + n_1_0_612), .B2(registers_21__ap[14]), .ZN(n_1_0_273)); + AOI22_X1_LVT i_1_0_287 (.A1(registers_14__ap[14]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[14]), .ZN(n_1_0_272)); + AOI22_X1_LVT i_1_0_286 (.A1(registers_22__ap[14]), .A2(n_1_0_642), .B1( + n_1_0_633), .B2(registers_19__ap[14]), .ZN(n_1_0_271)); + AOI22_X1_LVT i_1_0_285 (.A1(registers_27__ap[14]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[14]), .ZN(n_1_0_270)); + NAND4_X1_LVT i_1_0_284 (.A1(n_1_0_273), .A2(n_1_0_272), .A3(n_1_0_271), + .A4(n_1_0_270), .ZN(n_1_0_269)); + NOR2_X1_LVT i_1_0_283 (.A1(n_1_0_274), .A2(n_1_0_269), .ZN(n_1_0_268)); + NAND4_X1_LVT i_1_0_282 (.A1(n_1_0_286), .A2(n_1_0_285), .A3(n_1_0_279), + .A4(n_1_0_268), .ZN(RRs2[14])); + AOI22_X1_LVT i_1_0_281 (.A1(registers_18__ap[13]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[13]), .ZN(n_1_0_267)); + AOI22_X1_LVT i_1_0_280 (.A1(registers_12__ap[13]), .A2(n_1_0_632), .B1( + n_1_0_629), .B2(registers_17__ap[13]), .ZN(n_1_0_266)); + AOI22_X1_LVT i_1_0_279 (.A1(registers_7__ap[13]), .A2(n_1_0_623), .B1( + n_1_0_614), .B2(registers_16__ap[13]), .ZN(n_1_0_265)); + NAND3_X1_LVT i_1_0_277 (.A1(n_1_0_267), .A2(n_1_0_266), .A3(n_1_0_265), + .ZN(n_1_0_263)); + AOI221_X1_LVT i_1_0_276 (.A(n_1_0_263), .B1(n_1_0_642), .B2( + registers_22__ap[13]), .C1(registers_5__ap[13]), .C2(n_1_0_635), .ZN( + n_1_0_262)); + AOI22_X1_LVT i_1_0_278 (.A1(registers_13__ap[13]), .A2(n_1_0_631), .B1( + n_1_0_612), .B2(registers_21__ap[13]), .ZN(n_1_0_264)); + AOI222_X1_LVT i_1_0_275 (.A1(registers_26__ap[13]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[13]), .C1(n_1_0_620), .C2( + registers_25__ap[13]), .ZN(n_1_0_261)); + AOI22_X1_LVT i_1_0_274 (.A1(registers_28__ap[13]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[13]), .ZN(n_1_0_260)); + NAND3_X1_LVT i_1_0_273 (.A1(n_1_0_264), .A2(n_1_0_261), .A3(n_1_0_260), + .ZN(n_1_0_259)); + AOI22_X1_LVT i_1_0_272 (.A1(registers_1__ap[13]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[13]), .ZN(n_1_0_258)); + AOI22_X1_LVT i_1_0_271 (.A1(registers_19__ap[13]), .A2(n_1_0_633), .B1( + n_1_0_618), .B2(registers_2__ap[13]), .ZN(n_1_0_257)); + AOI22_X1_LVT i_1_0_270 (.A1(registers_14__ap[13]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[13]), .ZN(n_1_0_256)); + AOI22_X1_LVT i_1_0_269 (.A1(registers_27__ap[13]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[13]), .ZN(n_1_0_255)); + NAND4_X1_LVT i_1_0_268 (.A1(n_1_0_258), .A2(n_1_0_257), .A3(n_1_0_256), + .A4(n_1_0_255), .ZN(n_1_0_254)); + AOI22_X1_LVT i_1_0_267 (.A1(registers_24__ap[13]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[13]), .ZN(n_1_0_253)); + AOI22_X1_LVT i_1_0_266 (.A1(registers_4__ap[13]), .A2(n_1_0_638), .B1( + n_1_0_637), .B2(registers_31__ap[13]), .ZN(n_1_0_252)); + AOI22_X1_LVT i_1_0_265 (.A1(registers_29__ap[13]), .A2(n_1_0_649), .B1( + n_1_0_615), .B2(registers_23__ap[13]), .ZN(n_1_0_251)); + AOI22_X1_LVT i_1_0_264 (.A1(registers_15__ap[13]), .A2(n_1_0_627), .B1( + n_1_0_610), .B2(registers_3__ap[13]), .ZN(n_1_0_250)); + NAND4_X1_LVT i_1_0_263 (.A1(n_1_0_253), .A2(n_1_0_252), .A3(n_1_0_251), + .A4(n_1_0_250), .ZN(n_1_0_249)); + NOR3_X1_LVT i_1_0_262 (.A1(n_1_0_259), .A2(n_1_0_254), .A3(n_1_0_249), + .ZN(n_1_0_248)); + NAND2_X1_LVT i_1_0_261 (.A1(n_1_0_262), .A2(n_1_0_248), .ZN(RRs2[13])); + AOI22_X1_LVT i_1_0_260 (.A1(registers_18__ap[12]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[12]), .ZN(n_1_0_247)); + AOI22_X1_LVT i_1_0_259 (.A1(registers_12__ap[12]), .A2(n_1_0_632), .B1( + n_1_0_629), .B2(registers_17__ap[12]), .ZN(n_1_0_246)); + AOI22_X1_LVT i_1_0_258 (.A1(registers_5__ap[12]), .A2(n_1_0_635), .B1( + n_1_0_623), .B2(registers_7__ap[12]), .ZN(n_1_0_245)); + NAND3_X1_LVT i_1_0_256 (.A1(n_1_0_247), .A2(n_1_0_246), .A3(n_1_0_245), + .ZN(n_1_0_243)); + AOI221_X1_LVT i_1_0_255 (.A(n_1_0_243), .B1(n_1_0_642), .B2( + registers_22__ap[12]), .C1(registers_16__ap[12]), .C2(n_1_0_614), .ZN( + n_1_0_242)); + AOI22_X1_LVT i_1_0_257 (.A1(registers_13__ap[12]), .A2(n_1_0_631), .B1( + n_1_0_612), .B2(registers_21__ap[12]), .ZN(n_1_0_244)); + AOI222_X1_LVT i_1_0_254 (.A1(registers_26__ap[12]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[12]), .C1(n_1_0_620), .C2( + registers_25__ap[12]), .ZN(n_1_0_241)); + AOI22_X1_LVT i_1_0_253 (.A1(registers_28__ap[12]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[12]), .ZN(n_1_0_240)); + NAND3_X1_LVT i_1_0_252 (.A1(n_1_0_244), .A2(n_1_0_241), .A3(n_1_0_240), + .ZN(n_1_0_239)); + AOI22_X1_LVT i_1_0_251 (.A1(registers_1__ap[12]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[12]), .ZN(n_1_0_238)); + AOI22_X1_LVT i_1_0_250 (.A1(registers_19__ap[12]), .A2(n_1_0_633), .B1( + n_1_0_618), .B2(registers_2__ap[12]), .ZN(n_1_0_237)); + AOI22_X1_LVT i_1_0_249 (.A1(registers_14__ap[12]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[12]), .ZN(n_1_0_236)); + AOI22_X1_LVT i_1_0_248 (.A1(registers_27__ap[12]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[12]), .ZN(n_1_0_235)); + NAND4_X1_LVT i_1_0_247 (.A1(n_1_0_238), .A2(n_1_0_237), .A3(n_1_0_236), + .A4(n_1_0_235), .ZN(n_1_0_234)); + AOI22_X1_LVT i_1_0_246 (.A1(registers_24__ap[12]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[12]), .ZN(n_1_0_233)); + AOI22_X1_LVT i_1_0_245 (.A1(registers_4__ap[12]), .A2(n_1_0_638), .B1( + n_1_0_637), .B2(registers_31__ap[12]), .ZN(n_1_0_232)); + AOI22_X1_LVT i_1_0_244 (.A1(registers_29__ap[12]), .A2(n_1_0_649), .B1( + n_1_0_615), .B2(registers_23__ap[12]), .ZN(n_1_0_231)); + AOI22_X1_LVT i_1_0_243 (.A1(registers_15__ap[12]), .A2(n_1_0_627), .B1( + n_1_0_610), .B2(registers_3__ap[12]), .ZN(n_1_0_230)); + NAND4_X1_LVT i_1_0_242 (.A1(n_1_0_233), .A2(n_1_0_232), .A3(n_1_0_231), + .A4(n_1_0_230), .ZN(n_1_0_229)); + NOR3_X1_LVT i_1_0_241 (.A1(n_1_0_239), .A2(n_1_0_234), .A3(n_1_0_229), + .ZN(n_1_0_228)); + NAND2_X1_LVT i_1_0_240 (.A1(n_1_0_242), .A2(n_1_0_228), .ZN(RRs2[12])); + AOI22_X1_LVT i_1_0_238 (.A1(registers_29__ap[11]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[11]), .ZN(n_1_0_226)); + AOI22_X1_LVT i_1_0_239 (.A1(registers_27__ap[11]), .A2(n_1_0_636), .B1( + n_1_0_627), .B2(registers_15__ap[11]), .ZN(n_1_0_227)); + AOI22_X1_LVT i_1_0_237 (.A1(registers_1__ap[11]), .A2(n_1_0_644), .B1( + n_1_0_616), .B2(registers_6__ap[11]), .ZN(n_1_0_225)); + AOI22_X1_LVT i_1_0_236 (.A1(registers_5__ap[11]), .A2(n_1_0_635), .B1( + n_1_0_615), .B2(registers_23__ap[11]), .ZN(n_1_0_224)); + NAND3_X1_LVT i_1_0_235 (.A1(n_1_0_227), .A2(n_1_0_225), .A3(n_1_0_224), + .ZN(n_1_0_223)); + AOI221_X1_LVT i_1_0_234 (.A(n_1_0_223), .B1(n_1_0_637), .B2( + registers_31__ap[11]), .C1(registers_16__ap[11]), .C2(n_1_0_614), .ZN( + n_1_0_222)); + AOI222_X1_LVT i_1_0_233 (.A1(registers_8__ap[11]), .A2(n_1_0_626), .B1( + n_1_0_624), .B2(registers_10__ap[11]), .C1(n_1_0_622), .C2( + registers_30__ap[11]), .ZN(n_1_0_221)); + NAND3_X1_LVT i_1_0_232 (.A1(n_1_0_226), .A2(n_1_0_222), .A3(n_1_0_221), + .ZN(n_1_0_220)); + AOI221_X1_LVT i_1_0_231 (.A(n_1_0_220), .B1(n_1_0_638), .B2( + registers_4__ap[11]), .C1(registers_28__ap[11]), .C2(n_1_0_634), .ZN( + n_1_0_219)); + AOI22_X1_LVT i_1_0_230 (.A1(registers_18__ap[11]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[11]), .ZN(n_1_0_218)); + AOI22_X1_LVT i_1_0_229 (.A1(registers_12__ap[11]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[11]), .ZN(n_1_0_217)); + AOI22_X1_LVT i_1_0_228 (.A1(registers_22__ap[11]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[11]), .ZN(n_1_0_216)); + NAND3_X1_LVT i_1_0_227 (.A1(n_1_0_218), .A2(n_1_0_217), .A3(n_1_0_216), + .ZN(n_1_0_215)); + AOI221_X1_LVT i_1_0_226 (.A(n_1_0_215), .B1(n_1_0_613), .B2( + registers_20__ap[11]), .C1(registers_17__ap[11]), .C2(n_1_0_629), .ZN( + n_1_0_214)); + AOI22_X1_LVT i_1_0_225 (.A1(registers_13__ap[11]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[11]), .ZN(n_1_0_213)); + AOI22_X1_LVT i_1_0_224 (.A1(registers_7__ap[11]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[11]), .ZN(n_1_0_212)); + AOI22_X1_LVT i_1_0_223 (.A1(registers_19__ap[11]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[11]), .ZN(n_1_0_211)); + NAND3_X1_LVT i_1_0_222 (.A1(n_1_0_213), .A2(n_1_0_212), .A3(n_1_0_211), + .ZN(n_1_0_210)); + AOI221_X1_LVT i_1_0_221 (.A(n_1_0_210), .B1(n_1_0_611), .B2( + registers_11__ap[11]), .C1(registers_2__ap[11]), .C2(n_1_0_618), .ZN( + n_1_0_209)); + NAND3_X1_LVT i_1_0_220 (.A1(n_1_0_219), .A2(n_1_0_214), .A3(n_1_0_209), + .ZN(RRs2[11])); + AOI22_X1_LVT i_1_0_219 (.A1(registers_28__ap[10]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[10]), .ZN(n_1_0_208)); + AOI222_X1_LVT i_1_0_218 (.A1(registers_26__ap[10]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[10]), .C1(registers_25__ap[10]), .C2( + n_1_0_620), .ZN(n_1_0_207)); + AOI22_X1_LVT i_1_0_217 (.A1(registers_13__ap[10]), .A2(n_1_0_631), .B1( + n_1_0_612), .B2(registers_21__ap[10]), .ZN(n_1_0_206)); + AOI22_X1_LVT i_1_0_216 (.A1(registers_24__ap[10]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[10]), .ZN(n_1_0_205)); + AOI22_X1_LVT i_1_0_215 (.A1(registers_15__ap[10]), .A2(n_1_0_627), .B1( + n_1_0_610), .B2(registers_3__ap[10]), .ZN(n_1_0_204)); + AOI22_X1_LVT i_1_0_214 (.A1(registers_31__ap[10]), .A2(n_1_0_637), .B1( + n_1_0_629), .B2(registers_17__ap[10]), .ZN(n_1_0_203)); + AOI22_X1_LVT i_1_0_213 (.A1(registers_29__ap[10]), .A2(n_1_0_649), .B1( + n_1_0_615), .B2(registers_23__ap[10]), .ZN(n_1_0_202)); + NAND4_X1_LVT i_1_0_212 (.A1(n_1_0_205), .A2(n_1_0_204), .A3(n_1_0_203), + .A4(n_1_0_202), .ZN(n_1_0_201)); + AOI22_X1_LVT i_1_0_211 (.A1(registers_18__ap[10]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[10]), .ZN(n_1_0_200)); + AOI22_X1_LVT i_1_0_210 (.A1(registers_4__ap[10]), .A2(n_1_0_638), .B1( + n_1_0_632), .B2(registers_12__ap[10]), .ZN(n_1_0_199)); + AOI22_X1_LVT i_1_0_209 (.A1(registers_7__ap[10]), .A2(n_1_0_623), .B1( + n_1_0_614), .B2(registers_16__ap[10]), .ZN(n_1_0_198)); + AOI22_X1_LVT i_1_0_208 (.A1(registers_22__ap[10]), .A2(n_1_0_642), .B1( + n_1_0_635), .B2(registers_5__ap[10]), .ZN(n_1_0_197)); + NAND4_X1_LVT i_1_0_207 (.A1(n_1_0_200), .A2(n_1_0_199), .A3(n_1_0_198), + .A4(n_1_0_197), .ZN(n_1_0_196)); + AOI22_X1_LVT i_1_0_206 (.A1(registers_1__ap[10]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[10]), .ZN(n_1_0_195)); + AOI22_X1_LVT i_1_0_205 (.A1(registers_14__ap[10]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[10]), .ZN(n_1_0_194)); + AOI22_X1_LVT i_1_0_204 (.A1(registers_19__ap[10]), .A2(n_1_0_633), .B1( + n_1_0_618), .B2(registers_2__ap[10]), .ZN(n_1_0_193)); + AOI22_X1_LVT i_1_0_203 (.A1(registers_27__ap[10]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[10]), .ZN(n_1_0_192)); + NAND4_X1_LVT i_1_0_202 (.A1(n_1_0_195), .A2(n_1_0_194), .A3(n_1_0_193), + .A4(n_1_0_192), .ZN(n_1_0_191)); + NOR3_X1_LVT i_1_0_201 (.A1(n_1_0_201), .A2(n_1_0_196), .A3(n_1_0_191), + .ZN(n_1_0_190)); + NAND4_X1_LVT i_1_0_200 (.A1(n_1_0_208), .A2(n_1_0_207), .A3(n_1_0_206), + .A4(n_1_0_190), .ZN(RRs2[10])); + AOI22_X1_LVT i_1_0_196 (.A1(registers_13__ap[9]), .A2(n_1_0_631), .B1( + n_1_0_612), .B2(registers_21__ap[9]), .ZN(n_1_0_186)); + AOI22_X1_LVT i_1_0_199 (.A1(registers_29__ap[9]), .A2(n_1_0_649), .B1( + n_1_0_636), .B2(registers_27__ap[9]), .ZN(n_1_0_189)); + AOI22_X1_LVT i_1_0_195 (.A1(registers_24__ap[9]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[9]), .ZN(n_1_0_185)); + AOI22_X1_LVT i_1_0_198 (.A1(registers_31__ap[9]), .A2(n_1_0_637), .B1( + n_1_0_627), .B2(registers_15__ap[9]), .ZN(n_1_0_188)); + INV_X1_LVT i_1_0_197 (.A(n_1_0_188), .ZN(n_1_0_187)); + AOI221_X1_LVT i_1_0_194 (.A(n_1_0_187), .B1(n_1_0_615), .B2( + registers_23__ap[9]), .C1(registers_4__ap[9]), .C2(n_1_0_638), .ZN( + n_1_0_184)); + AOI222_X1_LVT i_1_0_193 (.A1(registers_18__ap[9]), .A2(n_1_0_646), .B1( + n_1_0_624), .B2(registers_10__ap[9]), .C1(registers_25__ap[9]), .C2( + n_1_0_620), .ZN(n_1_0_183)); + NAND4_X1_LVT i_1_0_192 (.A1(n_1_0_189), .A2(n_1_0_185), .A3(n_1_0_184), + .A4(n_1_0_183), .ZN(n_1_0_182)); + AOI221_X1_LVT i_1_0_191 (.A(n_1_0_182), .B1(n_1_0_626), .B2( + registers_8__ap[9]), .C1(registers_28__ap[9]), .C2(n_1_0_634), .ZN( + n_1_0_181)); + AOI22_X1_LVT i_1_0_190 (.A1(registers_26__ap[9]), .A2(n_1_0_640), .B1( + n_1_0_622), .B2(registers_30__ap[9]), .ZN(n_1_0_180)); + AOI22_X1_LVT i_1_0_189 (.A1(registers_12__ap[9]), .A2(n_1_0_632), .B1( + n_1_0_629), .B2(registers_17__ap[9]), .ZN(n_1_0_179)); + AOI22_X1_LVT i_1_0_188 (.A1(registers_5__ap[9]), .A2(n_1_0_635), .B1( + n_1_0_623), .B2(registers_7__ap[9]), .ZN(n_1_0_178)); + NAND3_X1_LVT i_1_0_187 (.A1(n_1_0_180), .A2(n_1_0_179), .A3(n_1_0_178), + .ZN(n_1_0_177)); + AOI221_X1_LVT i_1_0_186 (.A(n_1_0_177), .B1(n_1_0_642), .B2( + registers_22__ap[9]), .C1(registers_16__ap[9]), .C2(n_1_0_614), .ZN( + n_1_0_176)); + AOI22_X1_LVT i_1_0_185 (.A1(registers_1__ap[9]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[9]), .ZN(n_1_0_175)); + AOI22_X1_LVT i_1_0_184 (.A1(registers_14__ap[9]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[9]), .ZN(n_1_0_174)); + AOI22_X1_LVT i_1_0_183 (.A1(registers_19__ap[9]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[9]), .ZN(n_1_0_173)); + NAND3_X1_LVT i_1_0_182 (.A1(n_1_0_175), .A2(n_1_0_174), .A3(n_1_0_173), + .ZN(n_1_0_172)); + AOI221_X1_LVT i_1_0_181 (.A(n_1_0_172), .B1(n_1_0_611), .B2( + registers_11__ap[9]), .C1(registers_2__ap[9]), .C2(n_1_0_618), .ZN( + n_1_0_171)); + NAND4_X1_LVT i_1_0_180 (.A1(n_1_0_186), .A2(n_1_0_181), .A3(n_1_0_176), + .A4(n_1_0_171), .ZN(RRs2[9])); + AOI22_X1_LVT i_1_0_179 (.A1(registers_28__ap[8]), .A2(n_1_0_634), .B1( + n_1_0_629), .B2(registers_17__ap[8]), .ZN(n_1_0_170)); + AOI222_X1_LVT i_1_0_178 (.A1(registers_26__ap[8]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[8]), .C1(n_1_0_626), .C2( + registers_8__ap[8]), .ZN(n_1_0_169)); + AOI22_X1_LVT i_1_0_177 (.A1(registers_29__ap[8]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[8]), .ZN(n_1_0_168)); + AOI22_X1_LVT i_1_0_176 (.A1(registers_1__ap[8]), .A2(n_1_0_644), .B1( + n_1_0_616), .B2(registers_6__ap[8]), .ZN(n_1_0_167)); + AOI22_X1_LVT i_1_0_175 (.A1(registers_5__ap[8]), .A2(n_1_0_635), .B1( + n_1_0_610), .B2(registers_3__ap[8]), .ZN(n_1_0_166)); + AOI22_X1_LVT i_1_0_174 (.A1(registers_31__ap[8]), .A2(n_1_0_637), .B1( + n_1_0_614), .B2(registers_16__ap[8]), .ZN(n_1_0_165)); + AOI22_X1_LVT i_1_0_173 (.A1(registers_15__ap[8]), .A2(n_1_0_627), .B1( + n_1_0_615), .B2(registers_23__ap[8]), .ZN(n_1_0_164)); + NAND4_X1_LVT i_1_0_172 (.A1(n_1_0_167), .A2(n_1_0_166), .A3(n_1_0_165), + .A4(n_1_0_164), .ZN(n_1_0_163)); + AOI22_X1_LVT i_1_0_171 (.A1(registers_18__ap[8]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[8]), .ZN(n_1_0_162)); + AOI22_X1_LVT i_1_0_170 (.A1(registers_4__ap[8]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[8]), .ZN(n_1_0_161)); + AOI22_X1_LVT i_1_0_169 (.A1(registers_22__ap[8]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[8]), .ZN(n_1_0_160)); + AOI22_X1_LVT i_1_0_168 (.A1(registers_12__ap[8]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[8]), .ZN(n_1_0_159)); + NAND4_X1_LVT i_1_0_167 (.A1(n_1_0_162), .A2(n_1_0_161), .A3(n_1_0_160), + .A4(n_1_0_159), .ZN(n_1_0_158)); + AOI22_X1_LVT i_1_0_166 (.A1(registers_13__ap[8]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[8]), .ZN(n_1_0_157)); + AOI22_X1_LVT i_1_0_165 (.A1(registers_7__ap[8]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[8]), .ZN(n_1_0_156)); + AOI22_X1_LVT i_1_0_164 (.A1(registers_19__ap[8]), .A2(n_1_0_633), .B1( + n_1_0_618), .B2(registers_2__ap[8]), .ZN(n_1_0_155)); + AOI22_X1_LVT i_1_0_163 (.A1(registers_27__ap[8]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[8]), .ZN(n_1_0_154)); + NAND4_X1_LVT i_1_0_162 (.A1(n_1_0_157), .A2(n_1_0_156), .A3(n_1_0_155), + .A4(n_1_0_154), .ZN(n_1_0_153)); + NOR3_X1_LVT i_1_0_161 (.A1(n_1_0_163), .A2(n_1_0_158), .A3(n_1_0_153), + .ZN(n_1_0_152)); + NAND4_X1_LVT i_1_0_160 (.A1(n_1_0_170), .A2(n_1_0_169), .A3(n_1_0_168), + .A4(n_1_0_152), .ZN(RRs2[8])); + AOI22_X1_LVT i_1_0_159 (.A1(registers_28__ap[7]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[7]), .ZN(n_1_0_151)); + AOI222_X1_LVT i_1_0_158 (.A1(registers_26__ap[7]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[7]), .C1(registers_25__ap[7]), .C2( + n_1_0_620), .ZN(n_1_0_150)); + AOI22_X1_LVT i_1_0_157 (.A1(registers_24__ap[7]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[7]), .ZN(n_1_0_149)); + AOI22_X1_LVT i_1_0_156 (.A1(registers_15__ap[7]), .A2(n_1_0_627), .B1( + n_1_0_610), .B2(registers_3__ap[7]), .ZN(n_1_0_148)); + AOI22_X1_LVT i_1_0_155 (.A1(registers_31__ap[7]), .A2(n_1_0_637), .B1( + n_1_0_629), .B2(registers_17__ap[7]), .ZN(n_1_0_147)); + AOI22_X1_LVT i_1_0_154 (.A1(registers_29__ap[7]), .A2(n_1_0_649), .B1( + n_1_0_615), .B2(registers_23__ap[7]), .ZN(n_1_0_146)); + NAND4_X1_LVT i_1_0_153 (.A1(n_1_0_149), .A2(n_1_0_148), .A3(n_1_0_147), + .A4(n_1_0_146), .ZN(n_1_0_145)); + AOI221_X1_LVT i_1_0_152 (.A(n_1_0_145), .B1(n_1_0_612), .B2( + registers_21__ap[7]), .C1(registers_13__ap[7]), .C2(n_1_0_631), .ZN( + n_1_0_144)); + AOI22_X1_LVT i_1_0_151 (.A1(registers_18__ap[7]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[7]), .ZN(n_1_0_143)); + AOI22_X1_LVT i_1_0_150 (.A1(registers_4__ap[7]), .A2(n_1_0_638), .B1( + n_1_0_632), .B2(registers_12__ap[7]), .ZN(n_1_0_142)); + AOI22_X1_LVT i_1_0_149 (.A1(registers_5__ap[7]), .A2(n_1_0_635), .B1( + n_1_0_623), .B2(registers_7__ap[7]), .ZN(n_1_0_141)); + AOI22_X1_LVT i_1_0_148 (.A1(registers_22__ap[7]), .A2(n_1_0_642), .B1( + n_1_0_614), .B2(registers_16__ap[7]), .ZN(n_1_0_140)); + NAND4_X1_LVT i_1_0_147 (.A1(n_1_0_143), .A2(n_1_0_142), .A3(n_1_0_141), + .A4(n_1_0_140), .ZN(n_1_0_139)); + AOI22_X1_LVT i_1_0_146 (.A1(registers_1__ap[7]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[7]), .ZN(n_1_0_138)); + AOI22_X1_LVT i_1_0_145 (.A1(registers_14__ap[7]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[7]), .ZN(n_1_0_137)); + AOI22_X1_LVT i_1_0_144 (.A1(registers_19__ap[7]), .A2(n_1_0_633), .B1( + n_1_0_618), .B2(registers_2__ap[7]), .ZN(n_1_0_136)); + AOI22_X1_LVT i_1_0_143 (.A1(registers_27__ap[7]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[7]), .ZN(n_1_0_135)); + NAND4_X1_LVT i_1_0_142 (.A1(n_1_0_138), .A2(n_1_0_137), .A3(n_1_0_136), + .A4(n_1_0_135), .ZN(n_1_0_134)); + NOR2_X1_LVT i_1_0_141 (.A1(n_1_0_139), .A2(n_1_0_134), .ZN(n_1_0_133)); + NAND4_X1_LVT i_1_0_140 (.A1(n_1_0_151), .A2(n_1_0_150), .A3(n_1_0_144), + .A4(n_1_0_133), .ZN(RRs2[7])); + AOI22_X1_LVT i_1_0_136 (.A1(registers_13__ap[6]), .A2(n_1_0_631), .B1( + n_1_0_612), .B2(registers_21__ap[6]), .ZN(n_1_0_129)); + AOI22_X1_LVT i_1_0_139 (.A1(registers_29__ap[6]), .A2(n_1_0_649), .B1( + n_1_0_636), .B2(registers_27__ap[6]), .ZN(n_1_0_132)); + AOI22_X1_LVT i_1_0_135 (.A1(registers_24__ap[6]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[6]), .ZN(n_1_0_128)); + AOI22_X1_LVT i_1_0_138 (.A1(registers_31__ap[6]), .A2(n_1_0_637), .B1( + n_1_0_627), .B2(registers_15__ap[6]), .ZN(n_1_0_131)); + INV_X1_LVT i_1_0_137 (.A(n_1_0_131), .ZN(n_1_0_130)); + AOI221_X1_LVT i_1_0_134 (.A(n_1_0_130), .B1(n_1_0_638), .B2( + registers_4__ap[6]), .C1(registers_23__ap[6]), .C2(n_1_0_615), .ZN( + n_1_0_127)); + AOI222_X1_LVT i_1_0_133 (.A1(registers_18__ap[6]), .A2(n_1_0_646), .B1( + n_1_0_620), .B2(registers_25__ap[6]), .C1(n_1_0_624), .C2( + registers_10__ap[6]), .ZN(n_1_0_126)); + NAND4_X1_LVT i_1_0_132 (.A1(n_1_0_132), .A2(n_1_0_128), .A3(n_1_0_127), + .A4(n_1_0_126), .ZN(n_1_0_125)); + AOI221_X1_LVT i_1_0_131 (.A(n_1_0_125), .B1(n_1_0_626), .B2( + registers_8__ap[6]), .C1(registers_28__ap[6]), .C2(n_1_0_634), .ZN( + n_1_0_124)); + AOI22_X1_LVT i_1_0_130 (.A1(registers_26__ap[6]), .A2(n_1_0_640), .B1( + n_1_0_622), .B2(registers_30__ap[6]), .ZN(n_1_0_123)); + AOI22_X1_LVT i_1_0_129 (.A1(registers_12__ap[6]), .A2(n_1_0_632), .B1( + n_1_0_629), .B2(registers_17__ap[6]), .ZN(n_1_0_122)); + AOI22_X1_LVT i_1_0_128 (.A1(registers_7__ap[6]), .A2(n_1_0_623), .B1( + n_1_0_614), .B2(registers_16__ap[6]), .ZN(n_1_0_121)); + NAND3_X1_LVT i_1_0_127 (.A1(n_1_0_123), .A2(n_1_0_122), .A3(n_1_0_121), + .ZN(n_1_0_120)); + AOI221_X1_LVT i_1_0_126 (.A(n_1_0_120), .B1(n_1_0_642), .B2( + registers_22__ap[6]), .C1(registers_5__ap[6]), .C2(n_1_0_635), .ZN( + n_1_0_119)); + AOI22_X1_LVT i_1_0_125 (.A1(registers_1__ap[6]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[6]), .ZN(n_1_0_118)); + AOI22_X1_LVT i_1_0_124 (.A1(registers_14__ap[6]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[6]), .ZN(n_1_0_117)); + AOI22_X1_LVT i_1_0_123 (.A1(registers_19__ap[6]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[6]), .ZN(n_1_0_116)); + NAND3_X1_LVT i_1_0_122 (.A1(n_1_0_118), .A2(n_1_0_117), .A3(n_1_0_116), + .ZN(n_1_0_115)); + AOI221_X1_LVT i_1_0_121 (.A(n_1_0_115), .B1(n_1_0_618), .B2( + registers_2__ap[6]), .C1(registers_11__ap[6]), .C2(n_1_0_611), .ZN( + n_1_0_114)); + NAND4_X1_LVT i_1_0_120 (.A1(n_1_0_129), .A2(n_1_0_124), .A3(n_1_0_119), + .A4(n_1_0_114), .ZN(RRs2[6])); + AOI22_X1_LVT i_1_0_118 (.A1(registers_28__ap[5]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[5]), .ZN(n_1_0_112)); + AOI22_X1_LVT i_1_0_119 (.A1(registers_31__ap[5]), .A2(n_1_0_637), .B1( + n_1_0_627), .B2(registers_15__ap[5]), .ZN(n_1_0_113)); + AOI22_X1_LVT i_1_0_117 (.A1(registers_24__ap[5]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[5]), .ZN(n_1_0_111)); + AOI22_X1_LVT i_1_0_116 (.A1(registers_17__ap[5]), .A2(n_1_0_629), .B1( + n_1_0_615), .B2(registers_23__ap[5]), .ZN(n_1_0_110)); + NAND3_X1_LVT i_1_0_115 (.A1(n_1_0_113), .A2(n_1_0_111), .A3(n_1_0_110), + .ZN(n_1_0_109)); + AOI221_X1_LVT i_1_0_114 (.A(n_1_0_109), .B1(n_1_0_636), .B2( + registers_27__ap[5]), .C1(registers_29__ap[5]), .C2(n_1_0_649), .ZN( + n_1_0_108)); + AOI222_X1_LVT i_1_0_113 (.A1(registers_10__ap[5]), .A2(n_1_0_624), .B1( + n_1_0_620), .B2(registers_25__ap[5]), .C1(registers_18__ap[5]), .C2( + n_1_0_646), .ZN(n_1_0_107)); + NAND3_X1_LVT i_1_0_112 (.A1(n_1_0_112), .A2(n_1_0_108), .A3(n_1_0_107), + .ZN(n_1_0_106)); + AOI221_X1_LVT i_1_0_111 (.A(n_1_0_106), .B1(n_1_0_612), .B2( + registers_21__ap[5]), .C1(registers_13__ap[5]), .C2(n_1_0_631), .ZN( + n_1_0_105)); + AOI22_X1_LVT i_1_0_110 (.A1(registers_26__ap[5]), .A2(n_1_0_640), .B1( + n_1_0_622), .B2(registers_30__ap[5]), .ZN(n_1_0_104)); + AOI22_X1_LVT i_1_0_109 (.A1(registers_4__ap[5]), .A2(n_1_0_638), .B1( + n_1_0_632), .B2(registers_12__ap[5]), .ZN(n_1_0_103)); + AOI22_X1_LVT i_1_0_108 (.A1(registers_5__ap[5]), .A2(n_1_0_635), .B1( + n_1_0_623), .B2(registers_7__ap[5]), .ZN(n_1_0_102)); + NAND3_X1_LVT i_1_0_107 (.A1(n_1_0_104), .A2(n_1_0_103), .A3(n_1_0_102), + .ZN(n_1_0_101)); + AOI221_X1_LVT i_1_0_106 (.A(n_1_0_101), .B1(n_1_0_642), .B2( + registers_22__ap[5]), .C1(registers_16__ap[5]), .C2(n_1_0_614), .ZN( + n_1_0_100)); + AOI22_X1_LVT i_1_0_105 (.A1(registers_1__ap[5]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[5]), .ZN(n_1_0_99)); + AOI22_X1_LVT i_1_0_104 (.A1(registers_14__ap[5]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[5]), .ZN(n_1_0_98)); + AOI22_X1_LVT i_1_0_103 (.A1(registers_19__ap[5]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[5]), .ZN(n_1_0_97)); + NAND3_X1_LVT i_1_0_102 (.A1(n_1_0_99), .A2(n_1_0_98), .A3(n_1_0_97), .ZN( + n_1_0_96)); + AOI221_X1_LVT i_1_0_101 (.A(n_1_0_96), .B1(n_1_0_611), .B2( + registers_11__ap[5]), .C1(registers_2__ap[5]), .C2(n_1_0_618), .ZN( + n_1_0_95)); + NAND3_X1_LVT i_1_0_100 (.A1(n_1_0_105), .A2(n_1_0_100), .A3(n_1_0_95), + .ZN(RRs2[5])); + AOI22_X1_LVT i_1_0_99 (.A1(registers_4__ap[4]), .A2(n_1_0_638), .B1(n_1_0_634), + .B2(registers_28__ap[4]), .ZN(n_1_0_94)); + AOI222_X1_LVT i_1_0_98 (.A1(registers_8__ap[4]), .A2(n_1_0_626), .B1( + n_1_0_624), .B2(registers_10__ap[4]), .C1(n_1_0_622), .C2( + registers_30__ap[4]), .ZN(n_1_0_93)); + AOI22_X1_LVT i_1_0_97 (.A1(registers_29__ap[4]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[4]), .ZN(n_1_0_92)); + AOI22_X1_LVT i_1_0_96 (.A1(registers_1__ap[4]), .A2(n_1_0_644), .B1(n_1_0_616), + .B2(registers_6__ap[4]), .ZN(n_1_0_91)); + AOI22_X1_LVT i_1_0_95 (.A1(registers_27__ap[4]), .A2(n_1_0_636), .B1( + n_1_0_627), .B2(registers_15__ap[4]), .ZN(n_1_0_90)); + AOI22_X1_LVT i_1_0_94 (.A1(registers_23__ap[4]), .A2(n_1_0_615), .B1( + n_1_0_614), .B2(registers_16__ap[4]), .ZN(n_1_0_89)); + AOI22_X1_LVT i_1_0_93 (.A1(registers_31__ap[4]), .A2(n_1_0_637), .B1( + n_1_0_635), .B2(registers_5__ap[4]), .ZN(n_1_0_88)); + NAND4_X1_LVT i_1_0_92 (.A1(n_1_0_91), .A2(n_1_0_90), .A3(n_1_0_89), .A4( + n_1_0_88), .ZN(n_1_0_87)); + AOI22_X1_LVT i_1_0_91 (.A1(registers_18__ap[4]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[4]), .ZN(n_1_0_86)); + AOI22_X1_LVT i_1_0_90 (.A1(registers_12__ap[4]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[4]), .ZN(n_1_0_85)); + AOI22_X1_LVT i_1_0_89 (.A1(registers_22__ap[4]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[4]), .ZN(n_1_0_84)); + AOI22_X1_LVT i_1_0_88 (.A1(registers_17__ap[4]), .A2(n_1_0_629), .B1( + n_1_0_613), .B2(registers_20__ap[4]), .ZN(n_1_0_83)); + NAND4_X1_LVT i_1_0_87 (.A1(n_1_0_86), .A2(n_1_0_85), .A3(n_1_0_84), .A4( + n_1_0_83), .ZN(n_1_0_82)); + AOI22_X1_LVT i_1_0_86 (.A1(registers_13__ap[4]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[4]), .ZN(n_1_0_81)); + AOI22_X1_LVT i_1_0_85 (.A1(registers_7__ap[4]), .A2(n_1_0_623), .B1(n_1_0_619), + .B2(registers_14__ap[4]), .ZN(n_1_0_80)); + AOI22_X1_LVT i_1_0_84 (.A1(registers_19__ap[4]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[4]), .ZN(n_1_0_79)); + AOI22_X1_LVT i_1_0_83 (.A1(registers_2__ap[4]), .A2(n_1_0_618), .B1(n_1_0_611), + .B2(registers_11__ap[4]), .ZN(n_1_0_78)); + NAND4_X1_LVT i_1_0_82 (.A1(n_1_0_81), .A2(n_1_0_80), .A3(n_1_0_79), .A4( + n_1_0_78), .ZN(n_1_0_77)); + NOR3_X1_LVT i_1_0_81 (.A1(n_1_0_87), .A2(n_1_0_82), .A3(n_1_0_77), .ZN( + n_1_0_76)); + NAND4_X1_LVT i_1_0_80 (.A1(n_1_0_94), .A2(n_1_0_93), .A3(n_1_0_92), .A4( + n_1_0_76), .ZN(RRs2[4])); + AOI22_X1_LVT i_1_0_78 (.A1(registers_29__ap[3]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[3]), .ZN(n_1_0_74)); + AOI22_X1_LVT i_1_0_79 (.A1(registers_27__ap[3]), .A2(n_1_0_636), .B1( + n_1_0_627), .B2(registers_15__ap[3]), .ZN(n_1_0_75)); + AOI22_X1_LVT i_1_0_77 (.A1(registers_1__ap[3]), .A2(n_1_0_644), .B1(n_1_0_616), + .B2(registers_6__ap[3]), .ZN(n_1_0_73)); + AOI22_X1_LVT i_1_0_76 (.A1(registers_5__ap[3]), .A2(n_1_0_635), .B1(n_1_0_611), + .B2(registers_11__ap[3]), .ZN(n_1_0_72)); + NAND3_X1_LVT i_1_0_75 (.A1(n_1_0_75), .A2(n_1_0_73), .A3(n_1_0_72), .ZN( + n_1_0_71)); + AOI221_X1_LVT i_1_0_74 (.A(n_1_0_71), .B1(n_1_0_614), .B2(registers_16__ap[3]), + .C1(registers_31__ap[3]), .C2(n_1_0_637), .ZN(n_1_0_70)); + AOI222_X1_LVT i_1_0_73 (.A1(registers_8__ap[3]), .A2(n_1_0_626), .B1( + n_1_0_624), .B2(registers_10__ap[3]), .C1(n_1_0_622), .C2( + registers_30__ap[3]), .ZN(n_1_0_69)); + NAND3_X1_LVT i_1_0_72 (.A1(n_1_0_74), .A2(n_1_0_70), .A3(n_1_0_69), .ZN( + n_1_0_68)); + AOI221_X1_LVT i_1_0_71 (.A(n_1_0_68), .B1(n_1_0_638), .B2(registers_4__ap[3]), + .C1(registers_28__ap[3]), .C2(n_1_0_634), .ZN(n_1_0_67)); + AOI22_X1_LVT i_1_0_70 (.A1(registers_18__ap[3]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[3]), .ZN(n_1_0_66)); + AOI22_X1_LVT i_1_0_69 (.A1(registers_12__ap[3]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[3]), .ZN(n_1_0_65)); + AOI22_X1_LVT i_1_0_68 (.A1(registers_22__ap[3]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[3]), .ZN(n_1_0_64)); + NAND3_X1_LVT i_1_0_67 (.A1(n_1_0_66), .A2(n_1_0_65), .A3(n_1_0_64), .ZN( + n_1_0_63)); + AOI221_X1_LVT i_1_0_66 (.A(n_1_0_63), .B1(n_1_0_613), .B2(registers_20__ap[3]), + .C1(registers_17__ap[3]), .C2(n_1_0_629), .ZN(n_1_0_62)); + AOI22_X1_LVT i_1_0_65 (.A1(registers_13__ap[3]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[3]), .ZN(n_1_0_61)); + AOI22_X1_LVT i_1_0_64 (.A1(registers_7__ap[3]), .A2(n_1_0_623), .B1(n_1_0_619), + .B2(registers_14__ap[3]), .ZN(n_1_0_60)); + AOI22_X1_LVT i_1_0_63 (.A1(registers_19__ap[3]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[3]), .ZN(n_1_0_59)); + NAND3_X1_LVT i_1_0_62 (.A1(n_1_0_61), .A2(n_1_0_60), .A3(n_1_0_59), .ZN( + n_1_0_58)); + AOI221_X1_LVT i_1_0_61 (.A(n_1_0_58), .B1(n_1_0_618), .B2(registers_2__ap[3]), + .C1(registers_23__ap[3]), .C2(n_1_0_615), .ZN(n_1_0_57)); + NAND3_X1_LVT i_1_0_60 (.A1(n_1_0_67), .A2(n_1_0_62), .A3(n_1_0_57), .ZN( + RRs2[3])); + AOI22_X1_LVT i_1_0_58 (.A1(registers_29__ap[2]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[2]), .ZN(n_1_0_55)); + AOI22_X1_LVT i_1_0_59 (.A1(registers_27__ap[2]), .A2(n_1_0_636), .B1( + n_1_0_627), .B2(registers_15__ap[2]), .ZN(n_1_0_56)); + AOI22_X1_LVT i_1_0_57 (.A1(registers_1__ap[2]), .A2(n_1_0_644), .B1(n_1_0_616), + .B2(registers_6__ap[2]), .ZN(n_1_0_54)); + AOI22_X1_LVT i_1_0_56 (.A1(registers_5__ap[2]), .A2(n_1_0_635), .B1(n_1_0_615), + .B2(registers_23__ap[2]), .ZN(n_1_0_53)); + NAND3_X1_LVT i_1_0_55 (.A1(n_1_0_56), .A2(n_1_0_54), .A3(n_1_0_53), .ZN( + n_1_0_52)); + AOI221_X1_LVT i_1_0_54 (.A(n_1_0_52), .B1(n_1_0_637), .B2(registers_31__ap[2]), + .C1(registers_16__ap[2]), .C2(n_1_0_614), .ZN(n_1_0_51)); + AOI222_X1_LVT i_1_0_53 (.A1(registers_8__ap[2]), .A2(n_1_0_626), .B1( + n_1_0_624), .B2(registers_10__ap[2]), .C1(n_1_0_622), .C2( + registers_30__ap[2]), .ZN(n_1_0_50)); + NAND3_X1_LVT i_1_0_52 (.A1(n_1_0_55), .A2(n_1_0_51), .A3(n_1_0_50), .ZN( + n_1_0_49)); + AOI221_X1_LVT i_1_0_51 (.A(n_1_0_49), .B1(n_1_0_638), .B2(registers_4__ap[2]), + .C1(registers_28__ap[2]), .C2(n_1_0_634), .ZN(n_1_0_48)); + AOI22_X1_LVT i_1_0_50 (.A1(registers_18__ap[2]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[2]), .ZN(n_1_0_47)); + AOI22_X1_LVT i_1_0_49 (.A1(registers_12__ap[2]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[2]), .ZN(n_1_0_46)); + AOI22_X1_LVT i_1_0_48 (.A1(registers_22__ap[2]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[2]), .ZN(n_1_0_45)); + NAND3_X1_LVT i_1_0_47 (.A1(n_1_0_47), .A2(n_1_0_46), .A3(n_1_0_45), .ZN( + n_1_0_44)); + AOI221_X1_LVT i_1_0_46 (.A(n_1_0_44), .B1(n_1_0_629), .B2(registers_17__ap[2]), + .C1(registers_20__ap[2]), .C2(n_1_0_613), .ZN(n_1_0_43)); + AOI22_X1_LVT i_1_0_45 (.A1(registers_13__ap[2]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[2]), .ZN(n_1_0_42)); + AOI22_X1_LVT i_1_0_44 (.A1(registers_7__ap[2]), .A2(n_1_0_623), .B1(n_1_0_619), + .B2(registers_14__ap[2]), .ZN(n_1_0_41)); + AOI22_X1_LVT i_1_0_43 (.A1(registers_19__ap[2]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[2]), .ZN(n_1_0_40)); + NAND3_X1_LVT i_1_0_42 (.A1(n_1_0_42), .A2(n_1_0_41), .A3(n_1_0_40), .ZN( + n_1_0_39)); + AOI221_X1_LVT i_1_0_41 (.A(n_1_0_39), .B1(n_1_0_618), .B2(registers_2__ap[2]), + .C1(registers_11__ap[2]), .C2(n_1_0_611), .ZN(n_1_0_38)); + NAND3_X1_LVT i_1_0_40 (.A1(n_1_0_48), .A2(n_1_0_43), .A3(n_1_0_38), .ZN( + RRs2[2])); + AOI22_X1_LVT i_1_0_38 (.A1(registers_29__ap[1]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[1]), .ZN(n_1_0_36)); + AOI22_X1_LVT i_1_0_39 (.A1(registers_16__ap[1]), .A2(n_1_0_614), .B1( + n_1_0_610), .B2(registers_3__ap[1]), .ZN(n_1_0_37)); + AOI22_X1_LVT i_1_0_37 (.A1(registers_1__ap[1]), .A2(n_1_0_644), .B1(n_1_0_616), + .B2(registers_6__ap[1]), .ZN(n_1_0_35)); + AOI22_X1_LVT i_1_0_36 (.A1(registers_31__ap[1]), .A2(n_1_0_637), .B1( + n_1_0_635), .B2(registers_5__ap[1]), .ZN(n_1_0_34)); + NAND3_X1_LVT i_1_0_35 (.A1(n_1_0_37), .A2(n_1_0_35), .A3(n_1_0_34), .ZN( + n_1_0_33)); + AOI221_X1_LVT i_1_0_34 (.A(n_1_0_33), .B1(n_1_0_627), .B2(registers_15__ap[1]), + .C1(registers_23__ap[1]), .C2(n_1_0_615), .ZN(n_1_0_32)); + AOI222_X1_LVT i_1_0_33 (.A1(registers_26__ap[1]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[1]), .C1(n_1_0_626), .C2( + registers_8__ap[1]), .ZN(n_1_0_31)); + NAND3_X1_LVT i_1_0_32 (.A1(n_1_0_36), .A2(n_1_0_32), .A3(n_1_0_31), .ZN( + n_1_0_30)); + AOI221_X1_LVT i_1_0_31 (.A(n_1_0_30), .B1(n_1_0_629), .B2(registers_17__ap[1]), + .C1(registers_28__ap[1]), .C2(n_1_0_634), .ZN(n_1_0_29)); + AOI22_X1_LVT i_1_0_30 (.A1(registers_18__ap[1]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[1]), .ZN(n_1_0_28)); + AOI22_X1_LVT i_1_0_29 (.A1(registers_4__ap[1]), .A2(n_1_0_638), .B1(n_1_0_613), + .B2(registers_20__ap[1]), .ZN(n_1_0_27)); + AOI22_X1_LVT i_1_0_28 (.A1(registers_22__ap[1]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[1]), .ZN(n_1_0_26)); + NAND3_X1_LVT i_1_0_27 (.A1(n_1_0_28), .A2(n_1_0_27), .A3(n_1_0_26), .ZN( + n_1_0_25)); + AOI221_X1_LVT i_1_0_26 (.A(n_1_0_25), .B1(n_1_0_632), .B2(registers_12__ap[1]), + .C1(registers_24__ap[1]), .C2(n_1_0_621), .ZN(n_1_0_24)); + AOI22_X1_LVT i_1_0_25 (.A1(registers_13__ap[1]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[1]), .ZN(n_1_0_23)); + AOI22_X1_LVT i_1_0_24 (.A1(registers_7__ap[1]), .A2(n_1_0_623), .B1(n_1_0_619), + .B2(registers_14__ap[1]), .ZN(n_1_0_22)); + AOI22_X1_LVT i_1_0_23 (.A1(registers_19__ap[1]), .A2(n_1_0_633), .B1( + n_1_0_618), .B2(registers_2__ap[1]), .ZN(n_1_0_21)); + NAND3_X1_LVT i_1_0_22 (.A1(n_1_0_23), .A2(n_1_0_22), .A3(n_1_0_21), .ZN( + n_1_0_20)); + AOI221_X1_LVT i_1_0_21 (.A(n_1_0_20), .B1(n_1_0_611), .B2(registers_11__ap[1]), + .C1(registers_27__ap[1]), .C2(n_1_0_636), .ZN(n_1_0_19)); + NAND3_X1_LVT i_1_0_20 (.A1(n_1_0_29), .A2(n_1_0_24), .A3(n_1_0_19), .ZN( + RRs2[1])); + AOI22_X1_LVT i_1_0_19 (.A1(registers_4__ap[0]), .A2(n_1_0_638), .B1(n_1_0_634), + .B2(registers_28__ap[0]), .ZN(n_1_0_18)); + AOI222_X1_LVT i_1_0_18 (.A1(registers_8__ap[0]), .A2(n_1_0_626), .B1( + n_1_0_624), .B2(registers_10__ap[0]), .C1(n_1_0_622), .C2( + registers_30__ap[0]), .ZN(n_1_0_17)); + AOI22_X1_LVT i_1_0_17 (.A1(registers_29__ap[0]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[0]), .ZN(n_1_0_16)); + AOI22_X1_LVT i_1_0_16 (.A1(registers_1__ap[0]), .A2(n_1_0_644), .B1(n_1_0_616), + .B2(registers_6__ap[0]), .ZN(n_1_0_15)); + AOI22_X1_LVT i_1_0_15 (.A1(registers_27__ap[0]), .A2(n_1_0_636), .B1( + n_1_0_627), .B2(registers_15__ap[0]), .ZN(n_1_0_14)); + AOI22_X1_LVT i_1_0_14 (.A1(registers_23__ap[0]), .A2(n_1_0_615), .B1( + n_1_0_614), .B2(registers_16__ap[0]), .ZN(n_1_0_13)); + AOI22_X1_LVT i_1_0_13 (.A1(registers_31__ap[0]), .A2(n_1_0_637), .B1( + n_1_0_635), .B2(registers_5__ap[0]), .ZN(n_1_0_12)); + NAND4_X1_LVT i_1_0_12 (.A1(n_1_0_15), .A2(n_1_0_14), .A3(n_1_0_13), .A4( + n_1_0_12), .ZN(n_1_0_11)); + AOI22_X1_LVT i_1_0_11 (.A1(registers_18__ap[0]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[0]), .ZN(n_1_0_10)); + AOI22_X1_LVT i_1_0_10 (.A1(registers_12__ap[0]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[0]), .ZN(n_1_0_9)); + AOI22_X1_LVT i_1_0_9 (.A1(registers_22__ap[0]), .A2(n_1_0_642), .B1(n_1_0_612), + .B2(registers_21__ap[0]), .ZN(n_1_0_8)); + AOI22_X1_LVT i_1_0_8 (.A1(registers_17__ap[0]), .A2(n_1_0_629), .B1(n_1_0_613), + .B2(registers_20__ap[0]), .ZN(n_1_0_7)); + NAND4_X1_LVT i_1_0_7 (.A1(n_1_0_10), .A2(n_1_0_9), .A3(n_1_0_8), .A4(n_1_0_7), + .ZN(n_1_0_6)); + AOI22_X1_LVT i_1_0_6 (.A1(registers_13__ap[0]), .A2(n_1_0_631), .B1(n_1_0_620), + .B2(registers_25__ap[0]), .ZN(n_1_0_5)); + AOI22_X1_LVT i_1_0_5 (.A1(registers_7__ap[0]), .A2(n_1_0_623), .B1(n_1_0_619), + .B2(registers_14__ap[0]), .ZN(n_1_0_4)); + AOI22_X1_LVT i_1_0_4 (.A1(registers_19__ap[0]), .A2(n_1_0_633), .B1(n_1_0_610), + .B2(registers_3__ap[0]), .ZN(n_1_0_3)); + AOI22_X1_LVT i_1_0_3 (.A1(registers_2__ap[0]), .A2(n_1_0_618), .B1(n_1_0_611), + .B2(registers_11__ap[0]), .ZN(n_1_0_2)); + NAND4_X1_LVT i_1_0_2 (.A1(n_1_0_5), .A2(n_1_0_4), .A3(n_1_0_3), .A4(n_1_0_2), + .ZN(n_1_0_1)); + NOR3_X1_LVT i_1_0_1 (.A1(n_1_0_11), .A2(n_1_0_6), .A3(n_1_0_1), .ZN(n_1_0_0)); + NAND4_X1_LVT i_1_0_0 (.A1(n_1_0_18), .A2(n_1_0_17), .A3(n_1_0_16), .A4( + n_1_0_0), .ZN(RRs2[0])); +endmodule + +module MemGen_32_11(chip_en, clock, addr, rd_data, rd_en, wr_en, wr_data); + input chip_en; + input clock; + input [10:0]addr; + output [31:0]rd_data; + input rd_en; + input wr_en; + input [31:0]wr_data; + + wire [1:0]mem_sel; + + INV_X1_LVT i_1_3 (.A(addr[10]), .ZN(mem_sel[0])); + MemGen_16_10 genblk1_0_U_hi (.chip_en(mem_sel[0]), .wr_en(wr_en), .addr({ + addr[9], addr[8], addr[7], addr[6], addr[5], addr[4], addr[3], addr[2], + addr[1], addr[0]}), .wr_data({wr_data[31], wr_data[30], wr_data[29], + wr_data[28], wr_data[27], wr_data[26], wr_data[25], wr_data[24], + wr_data[23], wr_data[22], wr_data[21], wr_data[20], wr_data[19], + wr_data[18], wr_data[17], wr_data[16]}), .clock(clock), .rd_en(rd_en), + .rd_data({n_63, n_62, n_61, n_60, n_59, n_58, n_57, n_56, n_55, n_54, n_53, + n_52, n_51, n_50, n_49, n_48})); + MemGen_16_10 genblk1_1_U_hi (.chip_en(addr[10]), .wr_en(wr_en), .addr({ + addr[9], addr[8], addr[7], addr[6], addr[5], addr[4], addr[3], addr[2], + addr[1], addr[0]}), .wr_data({wr_data[31], wr_data[30], wr_data[29], + wr_data[28], wr_data[27], wr_data[26], wr_data[25], wr_data[24], + wr_data[23], wr_data[22], wr_data[21], wr_data[20], wr_data[19], + wr_data[18], wr_data[17], wr_data[16]}), .clock(clock), .rd_en(rd_en), + .rd_data({n_31, n_30, n_29, n_28, n_27, n_26, n_25, n_24, n_23, n_22, n_21, + n_20, n_19, n_18, n_17, n_16})); + MUX2_X1_LVT i_1_1_31 (.A(n_63), .B(n_31), .S(addr[10]), .Z(rd_data[31])); + MUX2_X1_LVT i_1_1_30 (.A(n_62), .B(n_30), .S(addr[10]), .Z(rd_data[30])); + MUX2_X1_LVT i_1_1_29 (.A(n_61), .B(n_29), .S(addr[10]), .Z(rd_data[29])); + MUX2_X1_LVT i_1_1_28 (.A(n_60), .B(n_28), .S(addr[10]), .Z(rd_data[28])); + MUX2_X1_LVT i_1_1_27 (.A(n_59), .B(n_27), .S(addr[10]), .Z(rd_data[27])); + MUX2_X1_LVT i_1_1_26 (.A(n_58), .B(n_26), .S(addr[10]), .Z(rd_data[26])); + MUX2_X1_LVT i_1_1_25 (.A(n_57), .B(n_25), .S(addr[10]), .Z(rd_data[25])); + MUX2_X1_LVT i_1_1_24 (.A(n_56), .B(n_24), .S(addr[10]), .Z(rd_data[24])); + MUX2_X1_LVT i_1_1_23 (.A(n_55), .B(n_23), .S(addr[10]), .Z(rd_data[23])); + MUX2_X1_LVT i_1_1_22 (.A(n_54), .B(n_22), .S(addr[10]), .Z(rd_data[22])); + MUX2_X1_LVT i_1_1_21 (.A(n_53), .B(n_21), .S(addr[10]), .Z(rd_data[21])); + MUX2_X1_LVT i_1_1_20 (.A(n_52), .B(n_20), .S(addr[10]), .Z(rd_data[20])); + MUX2_X1_LVT i_1_1_19 (.A(n_51), .B(n_19), .S(addr[10]), .Z(rd_data[19])); + MUX2_X1_LVT i_1_1_18 (.A(n_50), .B(n_18), .S(addr[10]), .Z(rd_data[18])); + MUX2_X1_LVT i_1_1_17 (.A(n_49), .B(n_17), .S(addr[10]), .Z(rd_data[17])); + MUX2_X1_LVT i_1_1_16 (.A(n_48), .B(n_16), .S(addr[10]), .Z(rd_data[16])); + MemGen_16_10 genblk1_0_U_lo (.chip_en(mem_sel[0]), .wr_en(wr_en), .addr({ + addr[9], addr[8], addr[7], addr[6], addr[5], addr[4], addr[3], addr[2], + addr[1], addr[0]}), .wr_data({wr_data[15], wr_data[14], wr_data[13], + wr_data[12], wr_data[11], wr_data[10], wr_data[9], wr_data[8], wr_data[7], + wr_data[6], wr_data[5], wr_data[4], wr_data[3], wr_data[2], wr_data[1], + wr_data[0]}), .clock(clock), .rd_en(rd_en), .rd_data({n_47, n_46, n_45, + n_44, n_43, n_42, n_41, n_40, n_39, n_38, n_37, n_36, n_35, n_34, n_33, + n_32})); + MemGen_16_10 genblk1_1_U_lo (.chip_en(addr[10]), .wr_en(wr_en), .addr({ + addr[9], addr[8], addr[7], addr[6], addr[5], addr[4], addr[3], addr[2], + addr[1], addr[0]}), .wr_data({wr_data[15], wr_data[14], wr_data[13], + wr_data[12], wr_data[11], wr_data[10], wr_data[9], wr_data[8], wr_data[7], + wr_data[6], wr_data[5], wr_data[4], wr_data[3], wr_data[2], wr_data[1], + wr_data[0]}), .clock(clock), .rd_en(rd_en), .rd_data({n_15, n_14, n_13, + n_12, n_11, n_10, n_9, n_8, n_7, n_6, n_5, n_4, n_3, n_2, n_1, n_0})); + MUX2_X1_LVT i_1_1_15 (.A(n_47), .B(n_15), .S(addr[10]), .Z(rd_data[15])); + MUX2_X1_LVT i_1_1_14 (.A(n_46), .B(n_14), .S(addr[10]), .Z(rd_data[14])); + MUX2_X1_LVT i_1_1_13 (.A(n_45), .B(n_13), .S(addr[10]), .Z(rd_data[13])); + MUX2_X1_LVT i_1_1_12 (.A(n_44), .B(n_12), .S(addr[10]), .Z(rd_data[12])); + MUX2_X1_LVT i_1_1_11 (.A(n_43), .B(n_11), .S(addr[10]), .Z(rd_data[11])); + MUX2_X1_LVT i_1_1_10 (.A(n_42), .B(n_10), .S(addr[10]), .Z(rd_data[10])); + MUX2_X1_LVT i_1_1_9 (.A(n_41), .B(n_9), .S(addr[10]), .Z(rd_data[9])); + MUX2_X1_LVT i_1_1_8 (.A(n_40), .B(n_8), .S(addr[10]), .Z(rd_data[8])); + MUX2_X1_LVT i_1_1_7 (.A(n_39), .B(n_7), .S(addr[10]), .Z(rd_data[7])); + MUX2_X1_LVT i_1_1_6 (.A(n_38), .B(n_6), .S(addr[10]), .Z(rd_data[6])); + MUX2_X1_LVT i_1_1_5 (.A(n_37), .B(n_5), .S(addr[10]), .Z(rd_data[5])); + MUX2_X1_LVT i_1_1_4 (.A(n_36), .B(n_4), .S(addr[10]), .Z(rd_data[4])); + MUX2_X1_LVT i_1_1_3 (.A(n_35), .B(n_3), .S(addr[10]), .Z(rd_data[3])); + MUX2_X1_LVT i_1_1_2 (.A(n_34), .B(n_2), .S(addr[10]), .Z(rd_data[2])); + MUX2_X1_LVT i_1_1_1 (.A(n_33), .B(n_1), .S(addr[10]), .Z(rd_data[1])); + MUX2_X1_LVT i_1_1_0 (.A(n_32), .B(n_0), .S(addr[10]), .Z(rd_data[0])); +endmodule + +module main_mem(clk, reset, DAddr, IAddr, DWData, DRData, IRData, DWE, DWidth); + input clk; + input reset; + input [31:0]DAddr; + input [31:0]IAddr; + input [31:0]DWData; + output [31:0]DRData; + output [31:0]IRData; + input DWE; + input [1:0]DWidth; + + wire [31:0]mem_rdata; + wire [10:0]mem_addr; + wire n_0_0; + wire n_0_0_0; + wire n_0_1; + wire n_0_0_1; + wire n_0_2; + wire n_0_0_2; + wire n_0_3; + wire n_0_0_3; + wire n_0_4; + wire n_0_0_4; + wire n_0_5; + wire n_0_0_5; + wire n_0_6; + wire n_0_0_6; + wire n_0_7; + wire n_0_0_7; + wire n_0_8; + wire n_0_0_8; + wire n_0_9; + wire n_0_0_9; + wire n_0_10; + wire n_0_0_10; + wire n_0_0_11; + wire n_0_11; + wire n_0_0_12; + wire n_0_0_13; + wire n_0_12; + wire n_0_0_14; + wire n_0_0_15; + wire n_0_13; + wire n_0_0_16; + wire n_0_0_17; + wire n_0_14; + wire n_0_0_18; + wire n_0_0_19; + wire n_0_15; + wire n_0_0_20; + wire n_0_0_21; + wire n_0_16; + wire n_0_0_22; + wire n_0_0_23; + wire n_0_17; + wire n_0_0_24; + wire n_0_0_25; + wire n_0_18; + wire n_0_0_26; + wire n_0_0_27; + wire n_0_0_28; + wire n_0_19; + wire n_0_0_29; + wire n_0_20; + wire n_0_0_30; + wire n_0_21; + wire n_0_0_31; + wire n_0_22; + wire n_0_0_32; + wire n_0_23; + wire n_0_0_33; + wire n_0_24; + wire n_0_0_34; + wire n_0_25; + wire n_0_0_35; + wire n_0_26; + wire n_0_0_36; + wire n_0_0_37; + wire n_0_27; + wire n_0_28; + wire n_0_29; + wire n_0_30; + wire n_0_31; + wire n_0_32; + wire n_0_33; + wire n_0_34; + wire n_0_35; + wire n_0_36; + wire n_0_37; + wire n_0_38; + wire n_0_39; + wire n_0_40; + wire n_0_41; + wire n_0_42; + wire n_0_65; + wire n_0_64; + wire n_0_63; + wire n_0_62; + wire n_0_61; + wire n_0_60; + wire n_0_59; + wire n_0_58; + wire n_0_0_38; + wire n_0_0_39; + wire n_0_57; + wire n_0_0_40; + wire n_0_56; + wire n_0_0_41; + wire n_0_55; + wire n_0_0_42; + wire n_0_54; + wire n_0_0_43; + wire n_0_53; + wire n_0_0_44; + wire n_0_52; + wire n_0_0_45; + wire n_0_51; + wire n_0_0_46; + wire n_0_50; + wire n_0_0_47; + wire n_0_0_48; + wire n_0_0_49; + wire n_0_0_50; + wire n_0_0_51; + wire n_0_49; + wire n_0_0_52; + wire n_0_48; + wire n_0_0_53; + wire n_0_47; + wire n_0_0_54; + wire n_0_46; + wire n_0_0_55; + wire n_0_45; + wire n_0_0_56; + wire n_0_44; + wire n_0_0_57; + wire n_0_66; + wire n_0_0_58; + wire n_0_67; + wire n_0_0_59; + wire n_0_0_60; + wire n_0_0_61; + wire n_0_68; + wire n_0_0_62; + wire n_0_0_63; + wire n_0_69; + wire n_0_0_64; + wire n_0_0_65; + wire n_0_70; + wire n_0_0_66; + wire n_0_0_67; + wire n_0_71; + wire n_0_0_68; + wire n_0_0_69; + wire n_0_72; + wire n_0_0_70; + wire n_0_0_71; + wire n_0_73; + wire n_0_0_72; + wire n_0_0_73; + wire n_0_74; + wire n_0_0_74; + wire n_0_0_75; + wire n_0_75; + wire n_0_0_76; + wire n_0_0_77; + wire n_0_0_78; + wire n_0_0_79; + wire n_0_0_80; + wire n_0_0_81; + wire n_0_0_82; + wire n_0_0_83; + wire n_0_0_84; + wire n_0_0_85; + wire n_0_0_86; + wire n_0_0_87; + wire n_0_0_88; + wire n_0_0_89; + wire n_0_0_90; + wire n_0_0_91; + wire n_0_0_92; + wire n_0_43; + wire n_0_0_93; + wire n_0_0_94; + wire n_0_76; + wire n_0_0_95; + wire [31:0]drTmp; + wire [31:0]mem_wdata; + + INV_X1_LVT i_0_0_171 (.A(DWE), .ZN(n_0)); + NOR2_X1_LVT i_0_0_163 (.A1(n_0), .A2(reset), .ZN(n_0_0_88)); + NOR2_X1_LVT i_0_0_22 (.A1(DWE), .A2(reset), .ZN(n_0_0_11)); + AOI22_X1_LVT i_0_0_21 (.A1(DAddr[12]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[12]), .ZN(n_0_0_10)); + INV_X1_LVT i_0_0_20 (.A(n_0_0_10), .ZN(n_0_10)); + INV_X1_LVT i_0_0_172 (.A(clk), .ZN(n_0_76)); + DFF_X1_LVT \mem_addr_reg[10] (.D(n_0_10), .CK(n_0_76), .Q(mem_addr[10]), + .QN()); + AOI22_X1_LVT i_0_0_19 (.A1(DAddr[11]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[11]), .ZN(n_0_0_9)); + INV_X1_LVT i_0_0_18 (.A(n_0_0_9), .ZN(n_0_9)); + DFF_X1_LVT \mem_addr_reg[9] (.D(n_0_9), .CK(n_0_76), .Q(mem_addr[9]), .QN()); + AOI22_X1_LVT i_0_0_17 (.A1(DAddr[10]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[10]), .ZN(n_0_0_8)); + INV_X1_LVT i_0_0_16 (.A(n_0_0_8), .ZN(n_0_8)); + DFF_X1_LVT \mem_addr_reg[8] (.D(n_0_8), .CK(n_0_76), .Q(mem_addr[8]), .QN()); + AOI22_X1_LVT i_0_0_15 (.A1(DAddr[9]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[9]), .ZN(n_0_0_7)); + INV_X1_LVT i_0_0_14 (.A(n_0_0_7), .ZN(n_0_7)); + DFF_X1_LVT \mem_addr_reg[7] (.D(n_0_7), .CK(n_0_76), .Q(mem_addr[7]), .QN()); + AOI22_X1_LVT i_0_0_13 (.A1(DAddr[8]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[8]), .ZN(n_0_0_6)); + INV_X1_LVT i_0_0_12 (.A(n_0_0_6), .ZN(n_0_6)); + DFF_X1_LVT \mem_addr_reg[6] (.D(n_0_6), .CK(n_0_76), .Q(mem_addr[6]), .QN()); + AOI22_X1_LVT i_0_0_11 (.A1(DAddr[7]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[7]), .ZN(n_0_0_5)); + INV_X1_LVT i_0_0_10 (.A(n_0_0_5), .ZN(n_0_5)); + DFF_X1_LVT \mem_addr_reg[5] (.D(n_0_5), .CK(n_0_76), .Q(mem_addr[5]), .QN()); + AOI22_X1_LVT i_0_0_9 (.A1(DAddr[6]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[6]), .ZN(n_0_0_4)); + INV_X1_LVT i_0_0_8 (.A(n_0_0_4), .ZN(n_0_4)); + DFF_X1_LVT \mem_addr_reg[4] (.D(n_0_4), .CK(n_0_76), .Q(mem_addr[4]), .QN()); + AOI22_X1_LVT i_0_0_7 (.A1(DAddr[5]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[5]), .ZN(n_0_0_3)); + INV_X1_LVT i_0_0_6 (.A(n_0_0_3), .ZN(n_0_3)); + DFF_X1_LVT \mem_addr_reg[3] (.D(n_0_3), .CK(n_0_76), .Q(mem_addr[3]), .QN()); + AOI22_X1_LVT i_0_0_5 (.A1(DAddr[4]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[4]), .ZN(n_0_0_2)); + INV_X1_LVT i_0_0_4 (.A(n_0_0_2), .ZN(n_0_2)); + DFF_X1_LVT \mem_addr_reg[2] (.D(n_0_2), .CK(n_0_76), .Q(mem_addr[2]), .QN()); + AOI22_X1_LVT i_0_0_3 (.A1(DAddr[3]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[3]), .ZN(n_0_0_1)); + INV_X1_LVT i_0_0_2 (.A(n_0_0_1), .ZN(n_0_1)); + DFF_X1_LVT \mem_addr_reg[1] (.D(n_0_1), .CK(n_0_76), .Q(mem_addr[1]), .QN()); + AOI22_X1_LVT i_0_0_1 (.A1(DAddr[2]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[2]), .ZN(n_0_0_0)); + INV_X1_LVT i_0_0_0 (.A(n_0_0_0), .ZN(n_0_0)); + DFF_X1_LVT \mem_addr_reg[0] (.D(n_0_0), .CK(n_0_76), .Q(mem_addr[0]), .QN()); + NOR2_X1_LVT i_0_0_162 (.A1(DWidth[1]), .A2(DAddr[1]), .ZN(n_0_0_87)); + NOR2_X1_LVT i_0_0_158 (.A1(DWidth[0]), .A2(DAddr[0]), .ZN(n_0_0_83)); + AND2_X1_LVT i_0_0_157 (.A1(n_0_0_87), .A2(n_0_0_83), .ZN(n_0_0_82)); + AND2_X1_LVT i_0_0_156 (.A1(n_0_0_88), .A2(n_0_0_82), .ZN(n_0_0_81)); + INV_X1_LVT i_0_0_173 (.A(n_0_0_88), .ZN(n_0_0_95)); + INV_X1_LVT i_0_0_169 (.A(DWidth[1]), .ZN(n_0_0_93)); + NOR3_X1_LVT i_0_0_155 (.A1(n_0_0_95), .A2(DWidth[0]), .A3(n_0_0_93), .ZN( + n_0_0_80)); + AOI22_X1_LVT i_0_0_154 (.A1(DWData[7]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[31]), .ZN(n_0_0_79)); + NAND2_X1_LVT i_0_0_168 (.A1(DWidth[0]), .A2(DWidth[1]), .ZN(n_0_43)); + INV_X1_LVT i_0_0_167 (.A(n_0_43), .ZN(n_0_0_92)); + NOR2_X1_LVT i_0_0_160 (.A1(n_0_0_95), .A2(n_0_0_92), .ZN(n_0_0_85)); + NAND2_X1_LVT i_0_0_161 (.A1(n_0_0_93), .A2(DAddr[1]), .ZN(n_0_0_86)); + NOR2_X1_LVT i_0_0_166 (.A1(DWidth[0]), .A2(DWidth[1]), .ZN(n_0_0_91)); + NAND2_X1_LVT i_0_0_164 (.A1(DAddr[0]), .A2(n_0_0_91), .ZN(n_0_0_89)); + NAND3_X1_LVT i_0_0_159 (.A1(n_0_0_85), .A2(n_0_0_86), .A3(n_0_0_89), .ZN( + n_0_0_84)); + INV_X1_LVT i_0_0_170 (.A(DWidth[0]), .ZN(n_0_0_94)); + NOR2_X1_LVT i_0_0_153 (.A1(n_0_0_94), .A2(DAddr[1]), .ZN(n_0_0_78)); + AND3_X1_LVT i_0_0_152 (.A1(n_0_0_88), .A2(n_0_0_78), .A3(n_0_0_93), .ZN( + n_0_0_77)); + AOI22_X1_LVT i_0_0_151 (.A1(n_0_0_84), .A2(mem_wdata[31]), .B1(DWData[15]), + .B2(n_0_0_77), .ZN(n_0_0_76)); + NAND2_X1_LVT i_0_0_150 (.A1(n_0_0_79), .A2(n_0_0_76), .ZN(n_0_75)); + DFF_X1_LVT \mem_wdata_reg[31] (.D(n_0_75), .CK(n_0_76), .Q(mem_wdata[31]), + .QN()); + AOI22_X1_LVT i_0_0_149 (.A1(DWData[6]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[30]), .ZN(n_0_0_75)); + AOI22_X1_LVT i_0_0_148 (.A1(n_0_0_84), .A2(mem_wdata[30]), .B1(DWData[14]), + .B2(n_0_0_77), .ZN(n_0_0_74)); + NAND2_X1_LVT i_0_0_147 (.A1(n_0_0_75), .A2(n_0_0_74), .ZN(n_0_74)); + DFF_X1_LVT \mem_wdata_reg[30] (.D(n_0_74), .CK(n_0_76), .Q(mem_wdata[30]), + .QN()); + AOI22_X1_LVT i_0_0_146 (.A1(DWData[5]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[29]), .ZN(n_0_0_73)); + AOI22_X1_LVT i_0_0_145 (.A1(n_0_0_84), .A2(mem_wdata[29]), .B1(DWData[13]), + .B2(n_0_0_77), .ZN(n_0_0_72)); + NAND2_X1_LVT i_0_0_144 (.A1(n_0_0_73), .A2(n_0_0_72), .ZN(n_0_73)); + DFF_X1_LVT \mem_wdata_reg[29] (.D(n_0_73), .CK(n_0_76), .Q(mem_wdata[29]), + .QN()); + AOI22_X1_LVT i_0_0_143 (.A1(DWData[4]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[28]), .ZN(n_0_0_71)); + AOI22_X1_LVT i_0_0_142 (.A1(n_0_0_84), .A2(mem_wdata[28]), .B1(DWData[12]), + .B2(n_0_0_77), .ZN(n_0_0_70)); + NAND2_X1_LVT i_0_0_141 (.A1(n_0_0_71), .A2(n_0_0_70), .ZN(n_0_72)); + DFF_X1_LVT \mem_wdata_reg[28] (.D(n_0_72), .CK(n_0_76), .Q(mem_wdata[28]), + .QN()); + AOI22_X1_LVT i_0_0_140 (.A1(DWData[3]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[27]), .ZN(n_0_0_69)); + AOI22_X1_LVT i_0_0_139 (.A1(n_0_0_84), .A2(mem_wdata[27]), .B1(DWData[11]), + .B2(n_0_0_77), .ZN(n_0_0_68)); + NAND2_X1_LVT i_0_0_138 (.A1(n_0_0_69), .A2(n_0_0_68), .ZN(n_0_71)); + DFF_X1_LVT \mem_wdata_reg[27] (.D(n_0_71), .CK(n_0_76), .Q(mem_wdata[27]), + .QN()); + AOI22_X1_LVT i_0_0_137 (.A1(DWData[2]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[26]), .ZN(n_0_0_67)); + AOI22_X1_LVT i_0_0_136 (.A1(n_0_0_84), .A2(mem_wdata[26]), .B1(DWData[10]), + .B2(n_0_0_77), .ZN(n_0_0_66)); + NAND2_X1_LVT i_0_0_135 (.A1(n_0_0_67), .A2(n_0_0_66), .ZN(n_0_70)); + DFF_X1_LVT \mem_wdata_reg[26] (.D(n_0_70), .CK(n_0_76), .Q(mem_wdata[26]), + .QN()); + AOI22_X1_LVT i_0_0_134 (.A1(DWData[1]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[25]), .ZN(n_0_0_65)); + AOI22_X1_LVT i_0_0_133 (.A1(n_0_0_84), .A2(mem_wdata[25]), .B1(DWData[9]), + .B2(n_0_0_77), .ZN(n_0_0_64)); + NAND2_X1_LVT i_0_0_132 (.A1(n_0_0_65), .A2(n_0_0_64), .ZN(n_0_69)); + DFF_X1_LVT \mem_wdata_reg[25] (.D(n_0_69), .CK(n_0_76), .Q(mem_wdata[25]), + .QN()); + AOI22_X1_LVT i_0_0_131 (.A1(DWData[0]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[24]), .ZN(n_0_0_63)); + AOI22_X1_LVT i_0_0_130 (.A1(n_0_0_84), .A2(mem_wdata[24]), .B1(DWData[8]), + .B2(n_0_0_77), .ZN(n_0_0_62)); + NAND2_X1_LVT i_0_0_129 (.A1(n_0_0_63), .A2(n_0_0_62), .ZN(n_0_68)); + DFF_X1_LVT \mem_wdata_reg[24] (.D(n_0_68), .CK(n_0_76), .Q(mem_wdata[24]), + .QN()); + NOR4_X1_LVT i_0_0_127 (.A1(n_0_0_95), .A2(n_0_0_83), .A3(DWidth[1]), .A4( + DAddr[1]), .ZN(n_0_0_60)); + INV_X1_LVT i_0_0_165 (.A(n_0_0_91), .ZN(n_0_0_90)); + OAI211_X1_LVT i_0_0_128 (.A(n_0_0_85), .B(n_0_0_86), .C1(n_0_0_90), .C2( + DAddr[0]), .ZN(n_0_0_61)); + AOI222_X1_LVT i_0_0_126 (.A1(DWData[7]), .A2(n_0_0_60), .B1(mem_wdata[23]), + .B2(n_0_0_61), .C1(DWData[23]), .C2(n_0_0_80), .ZN(n_0_0_59)); + INV_X1_LVT i_0_0_125 (.A(n_0_0_59), .ZN(n_0_67)); + DFF_X1_LVT \mem_wdata_reg[23] (.D(n_0_67), .CK(n_0_76), .Q(mem_wdata[23]), + .QN()); + AOI222_X1_LVT i_0_0_124 (.A1(DWData[6]), .A2(n_0_0_60), .B1(mem_wdata[22]), + .B2(n_0_0_61), .C1(DWData[22]), .C2(n_0_0_80), .ZN(n_0_0_58)); + INV_X1_LVT i_0_0_123 (.A(n_0_0_58), .ZN(n_0_66)); + DFF_X1_LVT \mem_wdata_reg[22] (.D(n_0_66), .CK(n_0_76), .Q(mem_wdata[22]), + .QN()); + AOI222_X1_LVT i_0_0_122 (.A1(DWData[5]), .A2(n_0_0_60), .B1(mem_wdata[21]), + .B2(n_0_0_61), .C1(DWData[21]), .C2(n_0_0_80), .ZN(n_0_0_57)); + INV_X1_LVT i_0_0_121 (.A(n_0_0_57), .ZN(n_0_44)); + DFF_X1_LVT \mem_wdata_reg[21] (.D(n_0_44), .CK(n_0_76), .Q(mem_wdata[21]), + .QN()); + AOI222_X1_LVT i_0_0_120 (.A1(DWData[4]), .A2(n_0_0_60), .B1(mem_wdata[20]), + .B2(n_0_0_61), .C1(DWData[20]), .C2(n_0_0_80), .ZN(n_0_0_56)); + INV_X1_LVT i_0_0_119 (.A(n_0_0_56), .ZN(n_0_45)); + DFF_X1_LVT \mem_wdata_reg[20] (.D(n_0_45), .CK(n_0_76), .Q(mem_wdata[20]), + .QN()); + AOI222_X1_LVT i_0_0_118 (.A1(DWData[3]), .A2(n_0_0_60), .B1(mem_wdata[19]), + .B2(n_0_0_61), .C1(DWData[19]), .C2(n_0_0_80), .ZN(n_0_0_55)); + INV_X1_LVT i_0_0_117 (.A(n_0_0_55), .ZN(n_0_46)); + DFF_X1_LVT \mem_wdata_reg[19] (.D(n_0_46), .CK(n_0_76), .Q(mem_wdata[19]), + .QN()); + AOI222_X1_LVT i_0_0_116 (.A1(DWData[2]), .A2(n_0_0_60), .B1(mem_wdata[18]), + .B2(n_0_0_61), .C1(DWData[18]), .C2(n_0_0_80), .ZN(n_0_0_54)); + INV_X1_LVT i_0_0_115 (.A(n_0_0_54), .ZN(n_0_47)); + DFF_X1_LVT \mem_wdata_reg[18] (.D(n_0_47), .CK(n_0_76), .Q(mem_wdata[18]), + .QN()); + AOI222_X1_LVT i_0_0_114 (.A1(DWData[1]), .A2(n_0_0_60), .B1(mem_wdata[17]), + .B2(n_0_0_61), .C1(DWData[17]), .C2(n_0_0_80), .ZN(n_0_0_53)); + INV_X1_LVT i_0_0_113 (.A(n_0_0_53), .ZN(n_0_48)); + DFF_X1_LVT \mem_wdata_reg[17] (.D(n_0_48), .CK(n_0_76), .Q(mem_wdata[17]), + .QN()); + AOI222_X1_LVT i_0_0_112 (.A1(DWData[0]), .A2(n_0_0_60), .B1(mem_wdata[16]), + .B2(n_0_0_61), .C1(DWData[16]), .C2(n_0_0_80), .ZN(n_0_0_52)); + INV_X1_LVT i_0_0_111 (.A(n_0_0_52), .ZN(n_0_49)); + DFF_X1_LVT \mem_wdata_reg[16] (.D(n_0_49), .CK(n_0_76), .Q(mem_wdata[16]), + .QN()); + NOR4_X1_LVT i_0_0_110 (.A1(n_0_0_95), .A2(n_0_0_87), .A3(n_0_0_92), .A4( + n_0_0_91), .ZN(n_0_0_51)); + NOR3_X1_LVT i_0_0_109 (.A1(n_0_0_86), .A2(DAddr[0]), .A3(DWidth[0]), .ZN( + n_0_0_50)); + AND2_X1_LVT i_0_0_108 (.A1(n_0_0_88), .A2(n_0_0_50), .ZN(n_0_0_49)); + OAI211_X1_LVT i_0_0_107 (.A(n_0_0_85), .B(n_0_0_89), .C1(DAddr[1]), .C2( + DWidth[1]), .ZN(n_0_0_48)); + AOI222_X1_LVT i_0_0_106 (.A1(DWData[15]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[7]), .C1(n_0_0_48), .C2(mem_wdata[15]), .ZN(n_0_0_47)); + INV_X1_LVT i_0_0_105 (.A(n_0_0_47), .ZN(n_0_50)); + DFF_X1_LVT \mem_wdata_reg[15] (.D(n_0_50), .CK(n_0_76), .Q(mem_wdata[15]), + .QN()); + AOI222_X1_LVT i_0_0_104 (.A1(DWData[14]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[6]), .C1(n_0_0_48), .C2(mem_wdata[14]), .ZN(n_0_0_46)); + INV_X1_LVT i_0_0_103 (.A(n_0_0_46), .ZN(n_0_51)); + DFF_X1_LVT \mem_wdata_reg[14] (.D(n_0_51), .CK(n_0_76), .Q(mem_wdata[14]), + .QN()); + AOI222_X1_LVT i_0_0_102 (.A1(DWData[13]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[5]), .C1(n_0_0_48), .C2(mem_wdata[13]), .ZN(n_0_0_45)); + INV_X1_LVT i_0_0_101 (.A(n_0_0_45), .ZN(n_0_52)); + DFF_X1_LVT \mem_wdata_reg[13] (.D(n_0_52), .CK(n_0_76), .Q(mem_wdata[13]), + .QN()); + AOI222_X1_LVT i_0_0_100 (.A1(DWData[12]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[4]), .C1(n_0_0_48), .C2(mem_wdata[12]), .ZN(n_0_0_44)); + INV_X1_LVT i_0_0_99 (.A(n_0_0_44), .ZN(n_0_53)); + DFF_X1_LVT \mem_wdata_reg[12] (.D(n_0_53), .CK(n_0_76), .Q(mem_wdata[12]), + .QN()); + AOI222_X1_LVT i_0_0_98 (.A1(DWData[11]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[3]), .C1(n_0_0_48), .C2(mem_wdata[11]), .ZN(n_0_0_43)); + INV_X1_LVT i_0_0_97 (.A(n_0_0_43), .ZN(n_0_54)); + DFF_X1_LVT \mem_wdata_reg[11] (.D(n_0_54), .CK(n_0_76), .Q(mem_wdata[11]), + .QN()); + AOI222_X1_LVT i_0_0_96 (.A1(DWData[10]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[2]), .C1(n_0_0_48), .C2(mem_wdata[10]), .ZN(n_0_0_42)); + INV_X1_LVT i_0_0_95 (.A(n_0_0_42), .ZN(n_0_55)); + DFF_X1_LVT \mem_wdata_reg[10] (.D(n_0_55), .CK(n_0_76), .Q(mem_wdata[10]), + .QN()); + AOI222_X1_LVT i_0_0_94 (.A1(DWData[9]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[1]), .C1(n_0_0_48), .C2(mem_wdata[9]), .ZN(n_0_0_41)); + INV_X1_LVT i_0_0_93 (.A(n_0_0_41), .ZN(n_0_56)); + DFF_X1_LVT \mem_wdata_reg[9] (.D(n_0_56), .CK(n_0_76), .Q(mem_wdata[9]), + .QN()); + AOI222_X1_LVT i_0_0_92 (.A1(DWData[8]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[0]), .C1(n_0_0_48), .C2(mem_wdata[8]), .ZN(n_0_0_40)); + INV_X1_LVT i_0_0_91 (.A(n_0_0_40), .ZN(n_0_57)); + DFF_X1_LVT \mem_wdata_reg[8] (.D(n_0_57), .CK(n_0_76), .Q(mem_wdata[8]), + .QN()); + AOI21_X1_LVT i_0_0_90 (.A(n_0_0_87), .B1(n_0_0_83), .B2(n_0_0_93), .ZN( + n_0_0_39)); + NAND2_X1_LVT i_0_0_89 (.A1(n_0_0_85), .A2(n_0_0_39), .ZN(n_0_0_38)); + MUX2_X1_LVT i_0_0_88 (.A(DWData[7]), .B(mem_wdata[7]), .S(n_0_0_38), .Z( + n_0_58)); + DFF_X1_LVT \mem_wdata_reg[7] (.D(n_0_58), .CK(n_0_76), .Q(mem_wdata[7]), + .QN()); + MUX2_X1_LVT i_0_0_87 (.A(DWData[6]), .B(mem_wdata[6]), .S(n_0_0_38), .Z( + n_0_59)); + DFF_X1_LVT \mem_wdata_reg[6] (.D(n_0_59), .CK(n_0_76), .Q(mem_wdata[6]), + .QN()); + MUX2_X1_LVT i_0_0_86 (.A(DWData[5]), .B(mem_wdata[5]), .S(n_0_0_38), .Z( + n_0_60)); + DFF_X1_LVT \mem_wdata_reg[5] (.D(n_0_60), .CK(n_0_76), .Q(mem_wdata[5]), + .QN()); + MUX2_X1_LVT i_0_0_85 (.A(DWData[4]), .B(mem_wdata[4]), .S(n_0_0_38), .Z( + n_0_61)); + DFF_X1_LVT \mem_wdata_reg[4] (.D(n_0_61), .CK(n_0_76), .Q(mem_wdata[4]), + .QN()); + MUX2_X1_LVT i_0_0_84 (.A(DWData[3]), .B(mem_wdata[3]), .S(n_0_0_38), .Z( + n_0_62)); + DFF_X1_LVT \mem_wdata_reg[3] (.D(n_0_62), .CK(n_0_76), .Q(mem_wdata[3]), + .QN()); + MUX2_X1_LVT i_0_0_83 (.A(DWData[2]), .B(mem_wdata[2]), .S(n_0_0_38), .Z( + n_0_63)); + DFF_X1_LVT \mem_wdata_reg[2] (.D(n_0_63), .CK(n_0_76), .Q(mem_wdata[2]), + .QN()); + MUX2_X1_LVT i_0_0_82 (.A(DWData[1]), .B(mem_wdata[1]), .S(n_0_0_38), .Z( + n_0_64)); + DFF_X1_LVT \mem_wdata_reg[1] (.D(n_0_64), .CK(n_0_76), .Q(mem_wdata[1]), + .QN()); + MUX2_X1_LVT i_0_0_81 (.A(DWData[0]), .B(mem_wdata[0]), .S(n_0_0_38), .Z( + n_0_65)); + DFF_X1_LVT \mem_wdata_reg[0] (.D(n_0_65), .CK(n_0_76), .Q(mem_wdata[0]), + .QN()); + MemGen_32_11 RAM (.chip_en(), .clock(clk), .addr(mem_addr), .rd_data( + mem_rdata), .rd_en(n_0), .wr_en(DWE), .wr_data(mem_wdata)); + DFF_X1_LVT \drTmp_reg[31] (.D(mem_rdata[31]), .CK(n_0_76), .Q(drTmp[31]), + .QN()); + AND2_X1_LVT i_0_0_80 (.A1(DWidth[1]), .A2(drTmp[31]), .ZN(n_0_42)); + DLH_X1_LVT \DRData[31] (.D(n_0_42), .G(n_0_43), .Q(DRData[31])); + DFF_X1_LVT \drTmp_reg[30] (.D(mem_rdata[30]), .CK(n_0_76), .Q(drTmp[30]), + .QN()); + AND2_X1_LVT i_0_0_79 (.A1(DWidth[1]), .A2(drTmp[30]), .ZN(n_0_41)); + DLH_X1_LVT \DRData[30] (.D(n_0_41), .G(n_0_43), .Q(DRData[30])); + DFF_X1_LVT \drTmp_reg[29] (.D(mem_rdata[29]), .CK(n_0_76), .Q(drTmp[29]), + .QN()); + AND2_X1_LVT i_0_0_78 (.A1(DWidth[1]), .A2(drTmp[29]), .ZN(n_0_40)); + DLH_X1_LVT \DRData[29] (.D(n_0_40), .G(n_0_43), .Q(DRData[29])); + DFF_X1_LVT \drTmp_reg[28] (.D(mem_rdata[28]), .CK(n_0_76), .Q(drTmp[28]), + .QN()); + AND2_X1_LVT i_0_0_77 (.A1(DWidth[1]), .A2(drTmp[28]), .ZN(n_0_39)); + DLH_X1_LVT \DRData[28] (.D(n_0_39), .G(n_0_43), .Q(DRData[28])); + DFF_X1_LVT \drTmp_reg[27] (.D(mem_rdata[27]), .CK(n_0_76), .Q(drTmp[27]), + .QN()); + AND2_X1_LVT i_0_0_76 (.A1(DWidth[1]), .A2(drTmp[27]), .ZN(n_0_38)); + DLH_X1_LVT \DRData[27] (.D(n_0_38), .G(n_0_43), .Q(DRData[27])); + DFF_X1_LVT \drTmp_reg[26] (.D(mem_rdata[26]), .CK(n_0_76), .Q(drTmp[26]), + .QN()); + AND2_X1_LVT i_0_0_75 (.A1(DWidth[1]), .A2(drTmp[26]), .ZN(n_0_37)); + DLH_X1_LVT \DRData[26] (.D(n_0_37), .G(n_0_43), .Q(DRData[26])); + DFF_X1_LVT \drTmp_reg[25] (.D(mem_rdata[25]), .CK(n_0_76), .Q(drTmp[25]), + .QN()); + AND2_X1_LVT i_0_0_74 (.A1(DWidth[1]), .A2(drTmp[25]), .ZN(n_0_36)); + DLH_X1_LVT \DRData[25] (.D(n_0_36), .G(n_0_43), .Q(DRData[25])); + DFF_X1_LVT \drTmp_reg[24] (.D(mem_rdata[24]), .CK(n_0_76), .Q(drTmp[24]), + .QN()); + AND2_X1_LVT i_0_0_73 (.A1(DWidth[1]), .A2(drTmp[24]), .ZN(n_0_35)); + DLH_X1_LVT \DRData[24] (.D(n_0_35), .G(n_0_43), .Q(DRData[24])); + DFF_X1_LVT \drTmp_reg[23] (.D(mem_rdata[23]), .CK(n_0_76), .Q(drTmp[23]), + .QN()); + AND2_X1_LVT i_0_0_72 (.A1(DWidth[1]), .A2(drTmp[23]), .ZN(n_0_34)); + DLH_X1_LVT \DRData[23] (.D(n_0_34), .G(n_0_43), .Q(DRData[23])); + DFF_X1_LVT \drTmp_reg[22] (.D(mem_rdata[22]), .CK(n_0_76), .Q(drTmp[22]), + .QN()); + AND2_X1_LVT i_0_0_71 (.A1(DWidth[1]), .A2(drTmp[22]), .ZN(n_0_33)); + DLH_X1_LVT \DRData[22] (.D(n_0_33), .G(n_0_43), .Q(DRData[22])); + DFF_X1_LVT \drTmp_reg[21] (.D(mem_rdata[21]), .CK(n_0_76), .Q(drTmp[21]), + .QN()); + AND2_X1_LVT i_0_0_70 (.A1(DWidth[1]), .A2(drTmp[21]), .ZN(n_0_32)); + DLH_X1_LVT \DRData[21] (.D(n_0_32), .G(n_0_43), .Q(DRData[21])); + DFF_X1_LVT \drTmp_reg[20] (.D(mem_rdata[20]), .CK(n_0_76), .Q(drTmp[20]), + .QN()); + AND2_X1_LVT i_0_0_69 (.A1(DWidth[1]), .A2(drTmp[20]), .ZN(n_0_31)); + DLH_X1_LVT \DRData[20] (.D(n_0_31), .G(n_0_43), .Q(DRData[20])); + DFF_X1_LVT \drTmp_reg[19] (.D(mem_rdata[19]), .CK(n_0_76), .Q(drTmp[19]), + .QN()); + AND2_X1_LVT i_0_0_68 (.A1(DWidth[1]), .A2(drTmp[19]), .ZN(n_0_30)); + DLH_X1_LVT \DRData[19] (.D(n_0_30), .G(n_0_43), .Q(DRData[19])); + DFF_X1_LVT \drTmp_reg[18] (.D(mem_rdata[18]), .CK(n_0_76), .Q(drTmp[18]), + .QN()); + AND2_X1_LVT i_0_0_67 (.A1(DWidth[1]), .A2(drTmp[18]), .ZN(n_0_29)); + DLH_X1_LVT \DRData[18] (.D(n_0_29), .G(n_0_43), .Q(DRData[18])); + DFF_X1_LVT \drTmp_reg[17] (.D(mem_rdata[17]), .CK(n_0_76), .Q(drTmp[17]), + .QN()); + AND2_X1_LVT i_0_0_66 (.A1(DWidth[1]), .A2(drTmp[17]), .ZN(n_0_28)); + DLH_X1_LVT \DRData[17] (.D(n_0_28), .G(n_0_43), .Q(DRData[17])); + DFF_X1_LVT \drTmp_reg[16] (.D(mem_rdata[16]), .CK(n_0_76), .Q(drTmp[16]), + .QN()); + AND2_X1_LVT i_0_0_65 (.A1(DWidth[1]), .A2(drTmp[16]), .ZN(n_0_27)); + DLH_X1_LVT \DRData[16] (.D(n_0_27), .G(n_0_43), .Q(DRData[16])); + NOR2_X1_LVT i_0_0_64 (.A1(n_0_0_91), .A2(n_0_0_87), .ZN(n_0_0_37)); + DFF_X1_LVT \drTmp_reg[15] (.D(mem_rdata[15]), .CK(n_0_76), .Q(drTmp[15]), + .QN()); + AOI22_X1_LVT i_0_0_63 (.A1(drTmp[31]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[15]), .ZN(n_0_0_36)); + INV_X1_LVT i_0_0_62 (.A(n_0_0_36), .ZN(n_0_26)); + DLH_X1_LVT \DRData[15] (.D(n_0_26), .G(n_0_43), .Q(DRData[15])); + DFF_X1_LVT \drTmp_reg[14] (.D(mem_rdata[14]), .CK(n_0_76), .Q(drTmp[14]), + .QN()); + AOI22_X1_LVT i_0_0_61 (.A1(drTmp[30]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[14]), .ZN(n_0_0_35)); + INV_X1_LVT i_0_0_60 (.A(n_0_0_35), .ZN(n_0_25)); + DLH_X1_LVT \DRData[14] (.D(n_0_25), .G(n_0_43), .Q(DRData[14])); + DFF_X1_LVT \drTmp_reg[13] (.D(mem_rdata[13]), .CK(n_0_76), .Q(drTmp[13]), + .QN()); + AOI22_X1_LVT i_0_0_59 (.A1(drTmp[29]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[13]), .ZN(n_0_0_34)); + INV_X1_LVT i_0_0_58 (.A(n_0_0_34), .ZN(n_0_24)); + DLH_X1_LVT \DRData[13] (.D(n_0_24), .G(n_0_43), .Q(DRData[13])); + DFF_X1_LVT \drTmp_reg[12] (.D(mem_rdata[12]), .CK(n_0_76), .Q(drTmp[12]), + .QN()); + AOI22_X1_LVT i_0_0_57 (.A1(drTmp[28]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[12]), .ZN(n_0_0_33)); + INV_X1_LVT i_0_0_56 (.A(n_0_0_33), .ZN(n_0_23)); + DLH_X1_LVT \DRData[12] (.D(n_0_23), .G(n_0_43), .Q(DRData[12])); + DFF_X1_LVT \drTmp_reg[11] (.D(mem_rdata[11]), .CK(n_0_76), .Q(drTmp[11]), + .QN()); + AOI22_X1_LVT i_0_0_55 (.A1(drTmp[27]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[11]), .ZN(n_0_0_32)); + INV_X1_LVT i_0_0_54 (.A(n_0_0_32), .ZN(n_0_22)); + DLH_X1_LVT \DRData[11] (.D(n_0_22), .G(n_0_43), .Q(DRData[11])); + DFF_X1_LVT \drTmp_reg[10] (.D(mem_rdata[10]), .CK(n_0_76), .Q(drTmp[10]), + .QN()); + AOI22_X1_LVT i_0_0_53 (.A1(drTmp[26]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[10]), .ZN(n_0_0_31)); + INV_X1_LVT i_0_0_52 (.A(n_0_0_31), .ZN(n_0_21)); + DLH_X1_LVT \DRData[10] (.D(n_0_21), .G(n_0_43), .Q(DRData[10])); + DFF_X1_LVT \drTmp_reg[9] (.D(mem_rdata[9]), .CK(n_0_76), .Q(drTmp[9]), .QN()); + AOI22_X1_LVT i_0_0_51 (.A1(drTmp[25]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[9]), .ZN(n_0_0_30)); + INV_X1_LVT i_0_0_50 (.A(n_0_0_30), .ZN(n_0_20)); + DLH_X1_LVT \DRData[9] (.D(n_0_20), .G(n_0_43), .Q(DRData[9])); + DFF_X1_LVT \drTmp_reg[8] (.D(mem_rdata[8]), .CK(n_0_76), .Q(drTmp[8]), .QN()); + AOI22_X1_LVT i_0_0_49 (.A1(drTmp[24]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[8]), .ZN(n_0_0_29)); + INV_X1_LVT i_0_0_48 (.A(n_0_0_29), .ZN(n_0_19)); + DLH_X1_LVT \DRData[8] (.D(n_0_19), .G(n_0_43), .Q(DRData[8])); + AOI22_X1_LVT i_0_0_46 (.A1(drTmp[31]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[15]), .ZN(n_0_0_27)); + AOI211_X1_LVT i_0_0_47 (.A(DAddr[1]), .B(n_0_0_83), .C1(n_0_0_94), .C2( + DWidth[1]), .ZN(n_0_0_28)); + DFF_X1_LVT \drTmp_reg[7] (.D(mem_rdata[7]), .CK(n_0_76), .Q(drTmp[7]), .QN()); + AOI22_X1_LVT i_0_0_45 (.A1(drTmp[23]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[7]), .ZN(n_0_0_26)); + NAND2_X1_LVT i_0_0_44 (.A1(n_0_0_27), .A2(n_0_0_26), .ZN(n_0_18)); + DLH_X1_LVT \DRData[7] (.D(n_0_18), .G(n_0_43), .Q(DRData[7])); + AOI22_X1_LVT i_0_0_43 (.A1(drTmp[30]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[14]), .ZN(n_0_0_25)); + DFF_X1_LVT \drTmp_reg[6] (.D(mem_rdata[6]), .CK(n_0_76), .Q(drTmp[6]), .QN()); + AOI22_X1_LVT i_0_0_42 (.A1(drTmp[22]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[6]), .ZN(n_0_0_24)); + NAND2_X1_LVT i_0_0_41 (.A1(n_0_0_25), .A2(n_0_0_24), .ZN(n_0_17)); + DLH_X1_LVT \DRData[6] (.D(n_0_17), .G(n_0_43), .Q(DRData[6])); + AOI22_X1_LVT i_0_0_40 (.A1(drTmp[29]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[13]), .ZN(n_0_0_23)); + DFF_X1_LVT \drTmp_reg[5] (.D(mem_rdata[5]), .CK(n_0_76), .Q(drTmp[5]), .QN()); + AOI22_X1_LVT i_0_0_39 (.A1(drTmp[21]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[5]), .ZN(n_0_0_22)); + NAND2_X1_LVT i_0_0_38 (.A1(n_0_0_23), .A2(n_0_0_22), .ZN(n_0_16)); + DLH_X1_LVT \DRData[5] (.D(n_0_16), .G(n_0_43), .Q(DRData[5])); + AOI22_X1_LVT i_0_0_37 (.A1(drTmp[28]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[12]), .ZN(n_0_0_21)); + DFF_X1_LVT \drTmp_reg[4] (.D(mem_rdata[4]), .CK(n_0_76), .Q(drTmp[4]), .QN()); + AOI22_X1_LVT i_0_0_36 (.A1(drTmp[20]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[4]), .ZN(n_0_0_20)); + NAND2_X1_LVT i_0_0_35 (.A1(n_0_0_21), .A2(n_0_0_20), .ZN(n_0_15)); + DLH_X1_LVT \DRData[4] (.D(n_0_15), .G(n_0_43), .Q(DRData[4])); + AOI22_X1_LVT i_0_0_34 (.A1(drTmp[27]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[11]), .ZN(n_0_0_19)); + DFF_X1_LVT \drTmp_reg[3] (.D(mem_rdata[3]), .CK(n_0_76), .Q(drTmp[3]), .QN()); + AOI22_X1_LVT i_0_0_33 (.A1(drTmp[19]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[3]), .ZN(n_0_0_18)); + NAND2_X1_LVT i_0_0_32 (.A1(n_0_0_19), .A2(n_0_0_18), .ZN(n_0_14)); + DLH_X1_LVT \DRData[3] (.D(n_0_14), .G(n_0_43), .Q(DRData[3])); + AOI22_X1_LVT i_0_0_31 (.A1(drTmp[26]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[10]), .ZN(n_0_0_17)); + DFF_X1_LVT \drTmp_reg[2] (.D(mem_rdata[2]), .CK(n_0_76), .Q(drTmp[2]), .QN()); + AOI22_X1_LVT i_0_0_30 (.A1(drTmp[18]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[2]), .ZN(n_0_0_16)); + NAND2_X1_LVT i_0_0_29 (.A1(n_0_0_17), .A2(n_0_0_16), .ZN(n_0_13)); + DLH_X1_LVT \DRData[2] (.D(n_0_13), .G(n_0_43), .Q(DRData[2])); + AOI22_X1_LVT i_0_0_28 (.A1(drTmp[25]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[9]), .ZN(n_0_0_15)); + DFF_X1_LVT \drTmp_reg[1] (.D(mem_rdata[1]), .CK(n_0_76), .Q(drTmp[1]), .QN()); + AOI22_X1_LVT i_0_0_27 (.A1(drTmp[17]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[1]), .ZN(n_0_0_14)); + NAND2_X1_LVT i_0_0_26 (.A1(n_0_0_15), .A2(n_0_0_14), .ZN(n_0_12)); + DLH_X1_LVT \DRData[1] (.D(n_0_12), .G(n_0_43), .Q(DRData[1])); + AOI22_X1_LVT i_0_0_25 (.A1(drTmp[24]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[8]), .ZN(n_0_0_13)); + DFF_X1_LVT \drTmp_reg[0] (.D(mem_rdata[0]), .CK(n_0_76), .Q(drTmp[0]), .QN()); + AOI22_X1_LVT i_0_0_24 (.A1(drTmp[16]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[0]), .ZN(n_0_0_12)); + NAND2_X1_LVT i_0_0_23 (.A1(n_0_0_13), .A2(n_0_0_12), .ZN(n_0_11)); + DLH_X1_LVT \DRData[0] (.D(n_0_11), .G(n_0_43), .Q(DRData[0])); + DFF_X1_LVT \IRData_reg[31] (.D(mem_rdata[31]), .CK(clk), .Q(IRData[31]), + .QN()); + DFF_X1_LVT \IRData_reg[30] (.D(mem_rdata[30]), .CK(clk), .Q(IRData[30]), + .QN()); + DFF_X1_LVT \IRData_reg[29] (.D(mem_rdata[29]), .CK(clk), .Q(IRData[29]), + .QN()); + DFF_X1_LVT \IRData_reg[28] (.D(mem_rdata[28]), .CK(clk), .Q(IRData[28]), + .QN()); + DFF_X1_LVT \IRData_reg[27] (.D(mem_rdata[27]), .CK(clk), .Q(IRData[27]), + .QN()); + DFF_X1_LVT \IRData_reg[26] (.D(mem_rdata[26]), .CK(clk), .Q(IRData[26]), + .QN()); + DFF_X1_LVT \IRData_reg[25] (.D(mem_rdata[25]), .CK(clk), .Q(IRData[25]), + .QN()); + DFF_X1_LVT \IRData_reg[24] (.D(mem_rdata[24]), .CK(clk), .Q(IRData[24]), + .QN()); + DFF_X1_LVT \IRData_reg[23] (.D(mem_rdata[23]), .CK(clk), .Q(IRData[23]), + .QN()); + DFF_X1_LVT \IRData_reg[22] (.D(mem_rdata[22]), .CK(clk), .Q(IRData[22]), + .QN()); + DFF_X1_LVT \IRData_reg[21] (.D(mem_rdata[21]), .CK(clk), .Q(IRData[21]), + .QN()); + DFF_X1_LVT \IRData_reg[20] (.D(mem_rdata[20]), .CK(clk), .Q(IRData[20]), + .QN()); + DFF_X1_LVT \IRData_reg[19] (.D(mem_rdata[19]), .CK(clk), .Q(IRData[19]), + .QN()); + DFF_X1_LVT \IRData_reg[18] (.D(mem_rdata[18]), .CK(clk), .Q(IRData[18]), + .QN()); + DFF_X1_LVT \IRData_reg[17] (.D(mem_rdata[17]), .CK(clk), .Q(IRData[17]), + .QN()); + DFF_X1_LVT \IRData_reg[16] (.D(mem_rdata[16]), .CK(clk), .Q(IRData[16]), + .QN()); + DFF_X1_LVT \IRData_reg[15] (.D(mem_rdata[15]), .CK(clk), .Q(IRData[15]), + .QN()); + DFF_X1_LVT \IRData_reg[14] (.D(mem_rdata[14]), .CK(clk), .Q(IRData[14]), + .QN()); + DFF_X1_LVT \IRData_reg[13] (.D(mem_rdata[13]), .CK(clk), .Q(IRData[13]), + .QN()); + DFF_X1_LVT \IRData_reg[12] (.D(mem_rdata[12]), .CK(clk), .Q(IRData[12]), + .QN()); + DFF_X1_LVT \IRData_reg[11] (.D(mem_rdata[11]), .CK(clk), .Q(IRData[11]), + .QN()); + DFF_X1_LVT \IRData_reg[10] (.D(mem_rdata[10]), .CK(clk), .Q(IRData[10]), + .QN()); + DFF_X1_LVT \IRData_reg[9] (.D(mem_rdata[9]), .CK(clk), .Q(IRData[9]), .QN()); + DFF_X1_LVT \IRData_reg[8] (.D(mem_rdata[8]), .CK(clk), .Q(IRData[8]), .QN()); + DFF_X1_LVT \IRData_reg[7] (.D(mem_rdata[7]), .CK(clk), .Q(IRData[7]), .QN()); + DFF_X1_LVT \IRData_reg[6] (.D(mem_rdata[6]), .CK(clk), .Q(IRData[6]), .QN()); + DFF_X1_LVT \IRData_reg[5] (.D(mem_rdata[5]), .CK(clk), .Q(IRData[5]), .QN()); + DFF_X1_LVT \IRData_reg[4] (.D(mem_rdata[4]), .CK(clk), .Q(IRData[4]), .QN()); + DFF_X1_LVT \IRData_reg[3] (.D(mem_rdata[3]), .CK(clk), .Q(IRData[3]), .QN()); + DFF_X1_LVT \IRData_reg[2] (.D(mem_rdata[2]), .CK(clk), .Q(IRData[2]), .QN()); + DFF_X1_LVT \IRData_reg[1] (.D(mem_rdata[1]), .CK(clk), .Q(IRData[1]), .QN()); + DFF_X1_LVT \IRData_reg[0] (.D(mem_rdata[0]), .CK(clk), .Q(IRData[0]), .QN()); +endmodule + +module alu(aluOp, aluNegAr, aluBypass, op1, op2, result, eqFlag); + input [2:0]aluOp; + input aluNegAr; + input aluBypass; + input [31:0]op1; + input [31:0]op2; + output [31:0]result; + output eqFlag; + + wire n_9_0; + wire n_9_1; + wire n_9_2; + wire n_9_3; + wire n_9_4; + wire n_9_5; + wire n_9_6; + wire n_9_7; + wire n_9_8; + wire n_9_9; + wire n_9_10; + wire n_9_11; + wire n_9_12; + wire n_9_13; + wire n_9_14; + wire n_9_15; + wire n_9_16; + wire n_9_17; + wire n_9_18; + wire n_9_19; + wire n_9_20; + wire n_9_21; + wire n_9_22; + wire n_9_23; + wire n_9_24; + wire n_9_25; + wire n_9_26; + wire n_9_27; + wire n_9_28; + wire n_9_29; + wire n_9_30; + wire n_9_31; + wire n_10_0; + wire n_10_1; + wire n_10_2; + wire n_10_3; + wire n_10_4; + wire n_10_5; + wire n_10_6; + wire n_10_7; + wire n_10_8; + wire n_10_9; + wire n_10_10; + wire n_10_11; + wire n_10_12; + wire n_10_13; + wire n_10_14; + wire n_10_15; + wire n_10_16; + wire n_10_17; + wire n_10_18; + wire n_10_19; + wire n_10_20; + wire n_10_21; + wire n_10_22; + wire n_10_23; + wire n_10_24; + wire n_10_25; + wire n_10_26; + wire n_10_27; + wire n_10_28; + wire n_10_29; + wire n_10_30; + wire n_10_31; + wire n_10_32; + wire n_10_33; + wire n_10_34; + wire n_10_35; + wire n_10_36; + wire n_10_37; + wire n_10_38; + wire n_10_39; + wire n_10_40; + wire n_10_41; + wire n_10_42; + wire n_10_43; + wire n_10_44; + wire n_10_45; + wire n_10_46; + wire n_10_47; + wire n_10_48; + wire n_10_49; + wire n_10_50; + wire n_10_51; + wire n_10_52; + wire n_10_53; + wire n_10_54; + wire n_10_55; + wire n_10_56; + wire n_10_57; + wire n_10_58; + wire n_10_59; + wire n_10_60; + wire n_10_61; + wire n_10_62; + wire n_10_63; + wire n_10_64; + wire n_10_65; + wire n_10_66; + wire n_10_67; + wire n_10_68; + wire n_10_69; + wire n_10_70; + wire n_10_71; + wire n_10_72; + wire n_10_73; + wire n_10_74; + wire n_10_75; + wire n_10_76; + wire n_10_77; + wire n_10_78; + wire n_10_79; + wire n_10_80; + wire n_10_81; + wire n_10_82; + wire n_10_83; + wire n_10_84; + wire n_10_85; + wire n_10_86; + wire n_10_87; + wire n_10_88; + wire n_10_89; + wire n_10_90; + wire n_10_91; + wire n_10_92; + wire n_10_93; + wire n_10_94; + wire n_10_95; + wire n_10_96; + wire n_10_97; + wire n_10_98; + wire n_10_99; + wire n_10_100; + wire n_10_101; + wire n_10_102; + wire n_10_103; + wire n_10_104; + wire n_10_105; + wire n_10_106; + wire n_10_107; + wire n_10_108; + wire n_10_109; + wire n_10_110; + wire n_10_111; + wire n_10_112; + wire n_10_113; + wire n_10_114; + wire n_10_115; + wire n_10_116; + wire n_10_117; + wire n_10_118; + wire n_10_119; + wire n_10_120; + wire n_10_121; + wire n_10_122; + wire n_10_123; + wire n_0_0; + wire n_0_1; + wire n_0_2; + wire n_0_3; + wire n_0_4; + wire n_0_5; + wire n_0_6; + wire n_0_7; + wire n_0_8; + wire n_0_9; + wire n_0_10; + wire n_0_11; + wire n_0_12; + wire n_0_13; + wire n_0_14; + wire n_0_15; + wire n_0_16; + wire n_0_17; + wire n_0_18; + wire n_0_19; + wire n_0_20; + wire n_0_21; + wire n_0_22; + wire n_0_23; + wire n_0_24; + wire n_0_25; + wire n_0_26; + wire n_0_27; + wire n_0_28; + wire n_0_29; + wire n_0_30; + wire n_0_31; + wire n_0_32; + wire n_0_33; + wire n_0_34; + wire n_0_35; + wire n_0_36; + wire n_0_37; + wire n_0_38; + wire n_0_39; + wire n_0_40; + wire n_0_41; + wire n_0_42; + wire n_0_43; + wire n_0_44; + wire n_0_45; + wire n_0_46; + wire n_0_47; + wire n_0_48; + wire n_0_49; + wire n_0_50; + wire n_0_51; + wire n_0_52; + wire n_0_53; + wire n_0_54; + wire n_0_55; + wire n_0_56; + wire n_0_57; + wire n_0_58; + wire n_0_59; + wire n_0_60; + wire n_0_61; + wire n_0_62; + wire n_0_63; + wire n_0_64; + wire n_0_65; + wire n_0_66; + wire n_0_67; + wire n_0_68; + wire n_0_69; + wire n_0_70; + wire n_0_71; + wire n_0_72; + wire n_0_73; + wire n_0_74; + wire n_0_75; + wire n_0_76; + wire n_0_77; + wire n_0_78; + wire n_0_79; + wire n_0_80; + wire n_0_81; + wire n_0_82; + wire n_0_83; + wire n_0_84; + wire n_0_85; + wire n_0_86; + wire n_0_87; + wire n_0_88; + wire n_0_89; + wire n_0_90; + wire n_0_91; + wire n_0_92; + wire n_0_93; + wire n_0_94; + wire n_0_95; + wire n_0_96; + wire n_0_97; + wire n_0_98; + wire n_0_99; + wire n_0_100; + wire n_0_101; + wire n_0_102; + wire n_0_103; + wire n_0_104; + wire n_0_105; + wire n_0_106; + wire n_0_107; + wire n_0_108; + wire n_0_109; + wire n_0_110; + wire n_0_111; + wire n_0_112; + wire n_0_113; + wire n_0_114; + wire n_0_115; + wire n_0_116; + wire n_0_117; + wire n_0_118; + wire n_0_119; + wire n_0_120; + wire n_0_121; + wire n_0_122; + wire n_0_123; + wire n_0_124; + wire n_0_125; + wire n_0_126; + wire n_0_127; + wire n_0_128; + wire n_0_129; + wire n_0_130; + wire n_0_131; + wire n_0_132; + wire n_0_133; + wire n_0_134; + wire n_0_135; + wire n_0_136; + wire n_0_137; + wire n_0_138; + wire n_0_139; + wire n_0_140; + wire n_0_141; + wire n_0_142; + wire n_0_143; + wire n_0_144; + wire n_0_145; + wire n_0_146; + wire n_0_147; + wire n_0_148; + wire n_0_149; + wire n_0_150; + wire n_0_151; + wire n_0_152; + wire n_0_153; + wire n_0_154; + wire n_0_155; + wire n_0_156; + wire n_0_157; + wire n_0_158; + wire n_0_159; + wire n_0_160; + wire n_0_161; + wire n_0_162; + wire n_0_163; + wire n_0_164; + wire n_0_165; + wire n_0_166; + wire n_0_167; + wire n_0_168; + wire n_0_169; + wire n_0_170; + wire n_0_171; + wire n_0_172; + wire n_0_173; + wire n_0_174; + wire n_0_175; + wire n_0_176; + wire n_0_177; + wire n_0_178; + wire n_0_179; + wire n_0_180; + wire n_0_181; + wire n_0_182; + wire n_0_183; + wire n_0_184; + wire n_0_185; + wire n_0_186; + wire n_0_187; + wire n_0_188; + wire n_0_189; + wire n_0_190; + wire n_0_191; + wire n_0_192; + wire n_0_193; + wire n_0_194; + wire n_0_195; + wire n_0_196; + wire n_0_197; + wire n_0_198; + wire n_0_199; + wire n_0_200; + wire n_0_201; + wire n_0_202; + wire n_0_203; + wire n_0_204; + wire n_0_205; + wire n_0_206; + wire n_0_207; + wire n_0_208; + wire n_0_209; + wire n_0_210; + wire n_0_211; + wire n_0_212; + wire n_0_213; + wire n_0_214; + wire n_0_215; + wire n_0_216; + wire n_0_217; + wire n_0_218; + wire n_0_219; + wire n_0_220; + wire n_0_221; + wire n_0_222; + wire n_0_223; + wire n_0_224; + wire n_0_225; + wire n_0_226; + wire n_0_227; + wire n_0_228; + wire n_0_229; + wire n_0_230; + wire n_0_231; + wire n_0_232; + wire n_0_233; + wire n_0_234; + wire n_0_235; + wire n_0_236; + wire n_0_237; + wire n_0_238; + wire n_0_239; + wire n_0_240; + wire n_0_241; + wire n_0_242; + wire n_0_243; + wire n_0_244; + wire n_0_245; + wire n_0_246; + wire n_0_247; + wire n_0_248; + wire n_0_249; + wire n_0_250; + wire n_0_251; + wire n_0_252; + wire n_0_253; + wire n_0_254; + wire n_0_255; + wire n_0_256; + wire n_0_257; + wire n_0_258; + wire n_0_259; + wire n_0_260; + wire n_0_261; + wire n_0_262; + wire n_0_263; + wire n_0_264; + wire n_0_265; + wire n_0_266; + wire n_0_267; + wire n_0_268; + wire n_0_269; + wire n_0_270; + wire n_0_271; + wire n_0_272; + wire n_0_273; + wire n_0_274; + wire n_0_275; + wire n_0_276; + wire n_0_277; + wire n_0_278; + wire n_0_279; + wire n_0_280; + wire n_0_281; + wire n_0_282; + wire n_0_283; + wire n_0_284; + wire n_0_285; + wire n_0_286; + wire n_0_287; + wire n_0_288; + wire n_0_289; + wire n_0_290; + wire n_0_291; + wire n_0_292; + wire n_0_293; + wire n_0_294; + wire n_0_295; + wire n_0_296; + wire n_0_297; + wire n_0_298; + wire n_0_299; + wire n_0_300; + wire n_0_301; + wire n_0_302; + wire n_0_303; + wire n_0_304; + wire n_0_305; + wire n_0_306; + wire n_0_307; + wire n_0_308; + wire n_0_309; + wire n_0_310; + wire n_0_311; + wire n_0_312; + wire n_0_313; + wire n_0_314; + wire n_0_315; + wire n_0_316; + wire n_0_317; + wire n_0_318; + wire n_0_319; + wire n_0_320; + wire n_0_321; + wire n_0_322; + wire n_0_323; + wire n_0_324; + wire n_0_325; + wire n_0_326; + wire n_0_327; + wire n_0_328; + wire n_0_329; + wire n_0_330; + wire n_0_331; + wire n_0_332; + wire n_0_333; + wire n_0_334; + wire n_0_335; + wire n_0_336; + wire n_0_337; + wire n_0_338; + wire n_0_339; + wire n_0_340; + wire n_0_341; + wire n_0_342; + wire n_0_343; + wire n_0_344; + wire n_0_345; + wire n_0_346; + wire n_0_347; + wire n_0_348; + wire n_0_349; + wire n_0_350; + wire n_0_351; + wire n_0_352; + wire n_0_353; + wire n_0_354; + wire n_0_355; + wire n_0_356; + wire n_0_357; + wire n_0_358; + wire n_0_359; + wire n_0_360; + wire n_0_361; + wire n_0_362; + wire n_0_363; + wire n_0_364; + wire n_0_365; + wire n_0_366; + wire n_0_367; + wire n_0_368; + wire n_0_369; + wire n_0_370; + wire n_0_371; + wire n_0_372; + wire n_0_373; + wire n_0_374; + wire n_0_375; + wire n_0_376; + wire n_0_377; + wire n_0_378; + wire n_0_379; + wire n_0_380; + wire n_0_381; + wire n_0_382; + wire n_0_383; + wire n_0_384; + wire n_0_385; + wire n_0_386; + wire n_0_387; + wire n_0_388; + wire n_0_389; + wire n_0_390; + wire n_0_391; + wire n_0_392; + wire n_0_393; + wire n_0_394; + wire n_0_395; + wire n_0_396; + wire n_0_397; + wire n_0_398; + wire n_0_399; + wire n_0_400; + wire n_0_401; + wire n_0_402; + wire n_0_403; + wire n_0_404; + wire n_0_405; + wire n_0_406; + wire n_0_407; + wire n_0_408; + wire n_0_409; + wire n_0_410; + wire n_0_411; + wire n_0_412; + wire n_0_413; + wire n_0_414; + wire n_0_415; + wire n_0_416; + wire n_0_417; + wire n_0_418; + wire n_0_419; + wire n_0_420; + wire n_0_421; + wire n_0_422; + wire n_0_423; + wire n_0_424; + wire n_0_425; + wire n_0_426; + wire n_0_427; + wire n_0_428; + wire n_0_429; + wire n_0_430; + wire n_0_431; + wire n_0_432; + wire n_0_433; + wire n_0_434; + wire n_0_435; + wire n_0_436; + wire n_0_437; + wire n_0_438; + wire n_0_439; + wire n_0_440; + wire n_0_441; + wire n_0_442; + wire n_0_443; + wire n_0_444; + wire n_0_445; + wire n_0_446; + wire n_0_447; + wire n_0_448; + wire n_0_449; + wire n_0_450; + wire n_0_451; + wire n_0_452; + wire n_0_453; + wire n_0_454; + wire n_0_455; + wire n_0_456; + wire n_0_457; + wire n_0_458; + wire n_0_459; + wire n_0_460; + wire n_0_461; + wire n_0_462; + wire n_0_463; + wire n_0_464; + wire n_0_465; + wire n_0_466; + wire n_0_467; + wire n_0_468; + wire n_0_469; + wire n_0_470; + wire n_0_471; + wire n_0_472; + wire n_0_473; + wire n_0_474; + wire n_0_475; + wire n_0_476; + wire n_0_477; + wire n_0_478; + wire n_0_479; + wire n_0_480; + wire n_0_481; + wire n_0_482; + wire n_0_483; + wire n_0_484; + wire n_0_485; + wire n_0_486; + wire n_0_487; + wire n_0_488; + wire n_0_489; + wire n_0_490; + wire n_0_491; + wire n_0_492; + wire n_0_493; + wire n_0_494; + wire n_0_495; + wire n_0_496; + wire n_0_497; + wire n_0_498; + wire n_0_499; + wire n_0_500; + wire n_0_501; + wire n_0_502; + wire n_0_503; + wire n_0_504; + wire n_0_505; + wire n_0_506; + wire n_0_507; + wire n_0_508; + wire n_0_509; + wire n_0_510; + wire n_0_511; + wire n_0_512; + wire n_0_513; + wire n_0_514; + wire n_0_515; + wire n_0_516; + wire n_0_517; + wire n_0_518; + wire n_0_519; + wire n_0_520; + wire n_0_521; + wire n_0_522; + wire n_0_523; + wire n_0_524; + wire n_0_525; + wire n_0_526; + wire n_0_527; + wire n_0_528; + wire n_0_529; + wire n_0_530; + wire n_0_531; + wire n_0_532; + wire n_0_533; + wire n_0_534; + wire n_0_535; + wire n_0_536; + wire n_0_537; + wire n_0_538; + wire n_0_539; + wire n_0_540; + wire n_0_541; + wire n_0_542; + wire n_0_543; + wire n_0_544; + wire n_0_545; + wire n_0_546; + wire n_0_547; + wire n_0_548; + wire n_0_549; + wire n_0_550; + wire n_0_551; + wire n_0_552; + wire n_0_553; + wire n_0_554; + wire n_0_555; + wire n_0_556; + wire n_0_557; + wire n_0_558; + wire n_0_559; + wire n_0_560; + wire n_0_561; + wire n_0_562; + wire n_0_563; + wire n_0_564; + wire n_0_565; + wire n_0_566; + wire n_0_567; + wire n_0_568; + wire n_0_569; + wire n_0_570; + wire n_0_571; + wire n_0_572; + wire n_0_573; + wire n_0_574; + wire n_0_575; + wire n_0_576; + wire n_0_577; + wire n_0_578; + wire n_0_579; + wire n_0_580; + wire n_0_581; + wire n_0_582; + wire n_0_583; + wire n_0_584; + wire n_0_585; + wire n_0_586; + wire n_0_587; + wire n_0_588; + wire n_0_589; + wire n_0_590; + wire n_0_591; + wire n_0_592; + wire n_0_593; + wire n_0_594; + wire n_0_595; + wire n_0_596; + wire n_0_597; + wire n_0_598; + wire n_0_599; + wire n_0_600; + wire n_0_601; + wire n_0_602; + wire n_0_603; + wire n_0_604; + wire n_0_605; + wire n_0_606; + wire n_0_607; + wire n_0_608; + wire n_0_609; + wire n_0_610; + wire n_0_611; + wire n_0_612; + wire n_0_613; + wire n_0_614; + wire n_0_615; + wire n_0_616; + wire n_0_617; + wire n_0_618; + wire n_0_619; + wire n_0_620; + wire n_0_621; + wire n_0_622; + wire n_0_623; + wire n_0_624; + wire n_0_625; + wire n_0_626; + wire n_0_627; + wire n_0_628; + wire n_0_629; + wire n_0_630; + wire n_0_631; + wire n_0_632; + wire n_0_633; + wire n_0_634; + wire n_0_635; + wire n_0_636; + wire n_0_637; + wire n_0_638; + wire n_0_639; + wire n_0_640; + wire n_0_641; + wire n_0_642; + wire n_0_643; + wire n_0_644; + wire n_0_645; + wire n_0_646; + wire n_0_647; + wire n_0_648; + wire n_0_649; + wire n_0_650; + wire n_0_651; + wire n_0_652; + wire n_0_653; + wire n_0_654; + wire n_0_655; + wire n_0_656; + wire n_0_657; + wire n_0_658; + wire n_0_659; + wire n_0_660; + wire n_0_661; + wire n_0_662; + wire n_0_663; + wire n_0_664; + wire n_0_665; + wire n_0_666; + wire n_0_667; + wire n_0_668; + wire n_0_669; + wire n_0_670; + wire n_0_671; + wire n_0_672; + wire n_0_673; + wire n_0_674; + wire n_0_675; + wire n_0_676; + wire n_0_677; + wire n_0_678; + wire n_0_679; + wire n_0_680; + wire n_0_681; + wire n_0_682; + wire n_0_683; + wire n_0_684; + wire n_0_685; + wire n_0_686; + wire n_0_687; + wire n_0_688; + wire n_0_689; + wire n_0_690; + wire n_0_691; + wire n_0_692; + wire n_0_693; + wire n_0_694; + wire n_0_695; + wire n_0_696; + wire n_0_697; + wire n_0_698; + wire n_0_699; + wire n_0_700; + wire n_0_701; + wire n_0_702; + wire n_0_703; + wire n_0_704; + wire n_0_705; + wire n_0_706; + wire n_0_707; + wire n_0_708; + wire n_0_709; + wire n_0_710; + wire n_0_711; + wire n_0_712; + wire n_0_713; + wire n_0_714; + wire n_0_715; + wire n_0_716; + wire n_0_717; + wire n_0_718; + wire n_0_719; + wire n_0_720; + wire n_0_721; + wire n_0_722; + wire n_0_723; + wire n_0_724; + wire n_0_725; + wire n_0_726; + wire n_0_727; + wire n_0_728; + wire n_0_729; + wire n_0_730; + wire n_0_731; + wire n_0_732; + wire n_0_733; + wire n_0_734; + wire n_0_735; + wire n_0_736; + wire n_0_737; + wire n_0_738; + wire n_0_739; + wire n_0_740; + + INV_X1_LVT i_0_725 (.A(op2[31]), .ZN(n_0_692)); + INV_X1_LVT i_0_724 (.A(op1[31]), .ZN(n_0_691)); + INV_X1_LVT i_0_718 (.A(aluOp[1]), .ZN(n_0_685)); + INV_X1_LVT i_0_717 (.A(aluOp[2]), .ZN(n_0_684)); + NOR2_X1_LVT i_0_599 (.A1(n_0_685), .A2(n_0_684), .ZN(n_0_567)); + INV_X1_LVT i_0_598 (.A(n_0_567), .ZN(n_0_566)); + INV_X1_LVT i_0_716 (.A(aluOp[0]), .ZN(n_0_683)); + NAND2_X1_LVT i_0_602 (.A1(aluOp[2]), .A2(aluNegAr), .ZN(n_0_570)); + OAI21_X1_LVT i_0_590 (.A(n_0_566), .B1(n_0_683), .B2(n_0_570), .ZN(n_0_558)); + INV_X1_LVT i_0_714 (.A(aluBypass), .ZN(n_0_681)); + NOR2_X1_LVT i_0_601 (.A1(n_0_684), .A2(aluOp[0]), .ZN(n_0_569)); + NAND2_X1_LVT i_0_597 (.A1(n_0_681), .A2(n_0_569), .ZN(n_0_565)); + INV_X1_LVT i_0_596 (.A(n_0_565), .ZN(n_0_564)); + OAI22_X1_LVT i_0_589 (.A1(n_0_691), .A2(n_0_558), .B1(op1[31]), .B2(n_0_564), + .ZN(n_0_557)); + NOR2_X1_LVT i_0_588 (.A1(n_0_692), .A2(n_0_557), .ZN(n_0_556)); + XNOR2_X1_LVT i_9_31 (.A(op2[31]), .B(op1[31]), .ZN(n_9_31)); + HA_X1_LVT i_9_0 (.A(op2[0]), .B(op1[0]), .CO(n_9_0), .S(n_0)); + FA_X1_LVT i_9_1 (.A(op2[1]), .B(op1[1]), .CI(n_9_0), .CO(n_9_1), .S(n_1)); + FA_X1_LVT i_9_2 (.A(op2[2]), .B(op1[2]), .CI(n_9_1), .CO(n_9_2), .S(n_2)); + FA_X1_LVT i_9_3 (.A(op2[3]), .B(op1[3]), .CI(n_9_2), .CO(n_9_3), .S(n_3)); + FA_X1_LVT i_9_4 (.A(op2[4]), .B(op1[4]), .CI(n_9_3), .CO(n_9_4), .S(n_4)); + FA_X1_LVT i_9_5 (.A(op2[5]), .B(op1[5]), .CI(n_9_4), .CO(n_9_5), .S(n_5)); + FA_X1_LVT i_9_6 (.A(op2[6]), .B(op1[6]), .CI(n_9_5), .CO(n_9_6), .S(n_6)); + FA_X1_LVT i_9_7 (.A(op2[7]), .B(op1[7]), .CI(n_9_6), .CO(n_9_7), .S(n_7)); + FA_X1_LVT i_9_8 (.A(op2[8]), .B(op1[8]), .CI(n_9_7), .CO(n_9_8), .S(n_8)); + FA_X1_LVT i_9_9 (.A(op2[9]), .B(op1[9]), .CI(n_9_8), .CO(n_9_9), .S(n_9)); + FA_X1_LVT i_9_10 (.A(op2[10]), .B(op1[10]), .CI(n_9_9), .CO(n_9_10), .S(n_10)); + FA_X1_LVT i_9_11 (.A(op2[11]), .B(op1[11]), .CI(n_9_10), .CO(n_9_11), + .S(n_11)); + FA_X1_LVT i_9_12 (.A(op2[12]), .B(op1[12]), .CI(n_9_11), .CO(n_9_12), + .S(n_12)); + FA_X1_LVT i_9_13 (.A(op2[13]), .B(op1[13]), .CI(n_9_12), .CO(n_9_13), + .S(n_13)); + FA_X1_LVT i_9_14 (.A(op2[14]), .B(op1[14]), .CI(n_9_13), .CO(n_9_14), + .S(n_14)); + FA_X1_LVT i_9_15 (.A(op2[15]), .B(op1[15]), .CI(n_9_14), .CO(n_9_15), + .S(n_15)); + FA_X1_LVT i_9_16 (.A(op2[16]), .B(op1[16]), .CI(n_9_15), .CO(n_9_16), + .S(n_16)); + FA_X1_LVT i_9_17 (.A(op2[17]), .B(op1[17]), .CI(n_9_16), .CO(n_9_17), + .S(n_17)); + FA_X1_LVT i_9_18 (.A(op2[18]), .B(op1[18]), .CI(n_9_17), .CO(n_9_18), + .S(n_18)); + FA_X1_LVT i_9_19 (.A(op2[19]), .B(op1[19]), .CI(n_9_18), .CO(n_9_19), + .S(n_19)); + FA_X1_LVT i_9_20 (.A(op2[20]), .B(op1[20]), .CI(n_9_19), .CO(n_9_20), + .S(n_20)); + FA_X1_LVT i_9_21 (.A(op2[21]), .B(op1[21]), .CI(n_9_20), .CO(n_9_21), + .S(n_21)); + FA_X1_LVT i_9_22 (.A(op2[22]), .B(op1[22]), .CI(n_9_21), .CO(n_9_22), + .S(n_22)); + FA_X1_LVT i_9_23 (.A(op2[23]), .B(op1[23]), .CI(n_9_22), .CO(n_9_23), + .S(n_23)); + FA_X1_LVT i_9_24 (.A(op2[24]), .B(op1[24]), .CI(n_9_23), .CO(n_9_24), + .S(n_24)); + FA_X1_LVT i_9_25 (.A(op2[25]), .B(op1[25]), .CI(n_9_24), .CO(n_9_25), + .S(n_25)); + FA_X1_LVT i_9_26 (.A(op2[26]), .B(op1[26]), .CI(n_9_25), .CO(n_9_26), + .S(n_26)); + FA_X1_LVT i_9_27 (.A(op2[27]), .B(op1[27]), .CI(n_9_26), .CO(n_9_27), + .S(n_27)); + FA_X1_LVT i_9_28 (.A(op2[28]), .B(op1[28]), .CI(n_9_27), .CO(n_9_28), + .S(n_28)); + FA_X1_LVT i_9_29 (.A(op2[29]), .B(op1[29]), .CI(n_9_28), .CO(n_9_29), + .S(n_29)); + FA_X1_LVT i_9_30 (.A(op2[30]), .B(op1[30]), .CI(n_9_29), .CO(n_9_30), + .S(n_30)); + XNOR2_X1_LVT i_9_32 (.A(n_9_31), .B(n_9_30), .ZN(n_31)); + NAND4_X1_LVT i_0_614 (.A1(n_0_685), .A2(n_0_681), .A3(n_0_684), .A4(n_0_683), + .ZN(n_0_582)); + NOR2_X1_LVT i_0_613 (.A1(aluNegAr), .A2(n_0_582), .ZN(n_0_581)); + INV_X1_LVT i_10_147 (.A(op2[30]), .ZN(n_10_117)); + NAND2_X1_LVT i_10_149 (.A1(n_10_117), .A2(op1[30]), .ZN(n_10_119)); + INV_X1_LVT i_10_152 (.A(n_10_119), .ZN(n_10_121)); + INV_X1_LVT i_10_130 (.A(op1[26]), .ZN(n_10_104)); + NAND2_X1_LVT i_10_131 (.A1(n_10_104), .A2(op2[26]), .ZN(n_10_105)); + INV_X1_LVT i_10_123 (.A(op2[25]), .ZN(n_10_98)); + NAND2_X1_LVT i_10_125 (.A1(n_10_98), .A2(op1[25]), .ZN(n_10_100)); + INV_X1_LVT i_10_112 (.A(op2[23]), .ZN(n_10_89)); + NAND2_X1_LVT i_10_114 (.A1(n_10_89), .A2(op1[23]), .ZN(n_10_91)); + INV_X1_LVT i_10_101 (.A(op2[21]), .ZN(n_10_80)); + NAND2_X1_LVT i_10_103 (.A1(n_10_80), .A2(op1[21]), .ZN(n_10_82)); + INV_X1_LVT i_10_48 (.A(op1[8]), .ZN(n_10_40)); + NAND2_X1_LVT i_10_49 (.A1(n_10_40), .A2(op2[8]), .ZN(n_10_41)); + INV_X1_LVT i_10_41 (.A(op2[7]), .ZN(n_10_34)); + NAND2_X1_LVT i_10_43 (.A1(n_10_34), .A2(op1[7]), .ZN(n_10_36)); + INV_X1_LVT i_10_32 (.A(op2[5]), .ZN(n_10_27)); + NOR2_X1_LVT i_10_33 (.A1(n_10_27), .A2(op1[5]), .ZN(n_10_28)); + INV_X1_LVT i_10_24 (.A(op1[4]), .ZN(n_10_20)); + NOR2_X1_LVT i_10_27 (.A1(n_10_20), .A2(op2[4]), .ZN(n_10_23)); + INV_X1_LVT i_10_17 (.A(op2[3]), .ZN(n_10_14)); + NAND2_X1_LVT i_10_19 (.A1(n_10_14), .A2(op1[3]), .ZN(n_10_16)); + INV_X1_LVT i_10_22 (.A(n_10_16), .ZN(n_10_18)); + INV_X1_LVT i_10_10 (.A(op2[2]), .ZN(n_10_8)); + NAND2_X1_LVT i_10_12 (.A1(n_10_8), .A2(op1[2]), .ZN(n_10_10)); + INV_X1_LVT i_10_3 (.A(op1[1]), .ZN(n_10_2)); + NAND2_X1_LVT i_10_5 (.A1(n_10_2), .A2(op2[1]), .ZN(n_10_4)); + INV_X1_LVT i_10_0 (.A(op1[0]), .ZN(n_10_0)); + NAND2_X1_LVT i_10_1 (.A1(n_10_0), .A2(op2[0]), .ZN(n_10_1)); + OR2_X1_LVT i_10_4 (.A1(n_10_2), .A2(op2[1]), .ZN(n_10_3)); + INV_X1_LVT i_10_8 (.A(n_10_3), .ZN(n_10_6)); + OAI21_X1_LVT i_10_9 (.A(n_10_4), .B1(n_10_1), .B2(n_10_6), .ZN(n_10_7)); + NOR2_X1_LVT i_10_11 (.A1(n_10_8), .A2(op1[2]), .ZN(n_10_9)); + OAI21_X1_LVT i_10_16 (.A(n_10_10), .B1(n_10_7), .B2(n_10_9), .ZN(n_10_13)); + OR2_X1_LVT i_10_18 (.A1(n_10_14), .A2(op1[3]), .ZN(n_10_15)); + AOI21_X1_LVT i_10_23 (.A(n_10_18), .B1(n_10_13), .B2(n_10_15), .ZN(n_10_19)); + INV_X1_LVT i_10_30 (.A(n_10_19), .ZN(n_10_25)); + NAND2_X1_LVT i_10_25 (.A1(n_10_20), .A2(op2[4]), .ZN(n_10_21)); + AOI21_X1_LVT i_10_31 (.A(n_10_23), .B1(n_10_25), .B2(n_10_21), .ZN(n_10_26)); + AOI21_X1_LVT i_10_34 (.A(n_10_28), .B1(n_10_27), .B2(op1[5]), .ZN(n_10_29)); + AOI21_X1_LVT i_10_36 (.A(n_10_28), .B1(n_10_26), .B2(n_10_29), .ZN(n_10_30)); + XOR2_X1_LVT i_10_37 (.A(op2[6]), .B(op1[6]), .Z(n_10_31)); + INV_X1_LVT i_10_39 (.A(op2[6]), .ZN(n_10_32)); + OAI22_X1_LVT i_10_40 (.A1(n_10_30), .A2(n_10_31), .B1(n_10_32), .B2(op1[6]), + .ZN(n_10_33)); + NOR2_X1_LVT i_10_42 (.A1(n_10_34), .A2(op1[7]), .ZN(n_10_35)); + OAI21_X1_LVT i_10_47 (.A(n_10_36), .B1(n_10_33), .B2(n_10_35), .ZN(n_10_39)); + OAI21_X1_LVT i_10_50 (.A(n_10_41), .B1(n_10_40), .B2(op2[8]), .ZN(n_10_42)); + OAI21_X1_LVT i_10_52 (.A(n_10_41), .B1(n_10_39), .B2(n_10_42), .ZN(n_10_43)); + XNOR2_X1_LVT i_10_53 (.A(op2[9]), .B(op1[9]), .ZN(n_10_44)); + INV_X1_LVT i_10_55 (.A(op1[9]), .ZN(n_10_45)); + AOI22_X1_LVT i_10_56 (.A1(n_10_43), .A2(n_10_44), .B1(n_10_45), .B2(op2[9]), + .ZN(n_10_46)); + XOR2_X1_LVT i_10_57 (.A(op2[10]), .B(op1[10]), .Z(n_10_47)); + INV_X1_LVT i_10_59 (.A(op2[10]), .ZN(n_10_48)); + OAI22_X1_LVT i_10_60 (.A1(n_10_46), .A2(n_10_47), .B1(n_10_48), .B2(op1[10]), + .ZN(n_10_49)); + XNOR2_X1_LVT i_10_61 (.A(op2[11]), .B(op1[11]), .ZN(n_10_50)); + INV_X1_LVT i_10_63 (.A(op1[11]), .ZN(n_10_51)); + AOI22_X1_LVT i_10_64 (.A1(n_10_49), .A2(n_10_50), .B1(n_10_51), .B2(op2[11]), + .ZN(n_10_52)); + XOR2_X1_LVT i_10_65 (.A(op2[12]), .B(op1[12]), .Z(n_10_53)); + INV_X1_LVT i_10_67 (.A(op2[12]), .ZN(n_10_54)); + OAI22_X1_LVT i_10_68 (.A1(n_10_52), .A2(n_10_53), .B1(n_10_54), .B2(op1[12]), + .ZN(n_10_55)); + XNOR2_X1_LVT i_10_69 (.A(op2[13]), .B(op1[13]), .ZN(n_10_56)); + INV_X1_LVT i_10_71 (.A(op1[13]), .ZN(n_10_57)); + AOI22_X1_LVT i_10_72 (.A1(n_10_55), .A2(n_10_56), .B1(n_10_57), .B2(op2[13]), + .ZN(n_10_58)); + XOR2_X1_LVT i_10_73 (.A(op2[14]), .B(op1[14]), .Z(n_10_59)); + INV_X1_LVT i_10_75 (.A(op2[14]), .ZN(n_10_60)); + OAI22_X1_LVT i_10_76 (.A1(n_10_58), .A2(n_10_59), .B1(n_10_60), .B2(op1[14]), + .ZN(n_10_61)); + XNOR2_X1_LVT i_10_77 (.A(op2[15]), .B(op1[15]), .ZN(n_10_62)); + INV_X1_LVT i_10_79 (.A(op1[15]), .ZN(n_10_63)); + AOI22_X1_LVT i_10_80 (.A1(n_10_61), .A2(n_10_62), .B1(n_10_63), .B2(op2[15]), + .ZN(n_10_64)); + XOR2_X1_LVT i_10_81 (.A(op2[16]), .B(op1[16]), .Z(n_10_65)); + INV_X1_LVT i_10_83 (.A(op2[16]), .ZN(n_10_66)); + OAI22_X1_LVT i_10_84 (.A1(n_10_64), .A2(n_10_65), .B1(n_10_66), .B2(op1[16]), + .ZN(n_10_67)); + XNOR2_X1_LVT i_10_85 (.A(op2[17]), .B(op1[17]), .ZN(n_10_68)); + INV_X1_LVT i_10_87 (.A(op1[17]), .ZN(n_10_69)); + AOI22_X1_LVT i_10_88 (.A1(n_10_67), .A2(n_10_68), .B1(n_10_69), .B2(op2[17]), + .ZN(n_10_70)); + XOR2_X1_LVT i_10_89 (.A(op2[18]), .B(op1[18]), .Z(n_10_71)); + INV_X1_LVT i_10_91 (.A(op2[18]), .ZN(n_10_72)); + OAI22_X1_LVT i_10_92 (.A1(n_10_70), .A2(n_10_71), .B1(n_10_72), .B2(op1[18]), + .ZN(n_10_73)); + XNOR2_X1_LVT i_10_93 (.A(op2[19]), .B(op1[19]), .ZN(n_10_74)); + INV_X1_LVT i_10_95 (.A(op1[19]), .ZN(n_10_75)); + AOI22_X1_LVT i_10_96 (.A1(n_10_73), .A2(n_10_74), .B1(n_10_75), .B2(op2[19]), + .ZN(n_10_76)); + XOR2_X1_LVT i_10_97 (.A(op2[20]), .B(op1[20]), .Z(n_10_77)); + INV_X1_LVT i_10_99 (.A(op2[20]), .ZN(n_10_78)); + OAI22_X1_LVT i_10_100 (.A1(n_10_76), .A2(n_10_77), .B1(n_10_78), .B2(op1[20]), + .ZN(n_10_79)); + NOR2_X1_LVT i_10_102 (.A1(n_10_80), .A2(op1[21]), .ZN(n_10_81)); + OAI21_X1_LVT i_10_107 (.A(n_10_82), .B1(n_10_79), .B2(n_10_81), .ZN(n_10_85)); + XOR2_X1_LVT i_10_108 (.A(op2[22]), .B(op1[22]), .Z(n_10_86)); + INV_X1_LVT i_10_110 (.A(op2[22]), .ZN(n_10_87)); + OAI22_X1_LVT i_10_111 (.A1(n_10_85), .A2(n_10_86), .B1(n_10_87), .B2(op1[22]), + .ZN(n_10_88)); + NOR2_X1_LVT i_10_113 (.A1(n_10_89), .A2(op1[23]), .ZN(n_10_90)); + OAI21_X1_LVT i_10_118 (.A(n_10_91), .B1(n_10_88), .B2(n_10_90), .ZN(n_10_94)); + XOR2_X1_LVT i_10_119 (.A(op2[24]), .B(op1[24]), .Z(n_10_95)); + INV_X1_LVT i_10_121 (.A(op2[24]), .ZN(n_10_96)); + OAI22_X1_LVT i_10_122 (.A1(n_10_94), .A2(n_10_95), .B1(n_10_96), .B2(op1[24]), + .ZN(n_10_97)); + NOR2_X1_LVT i_10_124 (.A1(n_10_98), .A2(op1[25]), .ZN(n_10_99)); + OAI21_X1_LVT i_10_129 (.A(n_10_100), .B1(n_10_97), .B2(n_10_99), .ZN(n_10_103)); + OAI21_X1_LVT i_10_132 (.A(n_10_105), .B1(n_10_104), .B2(op2[26]), .ZN( + n_10_106)); + OAI21_X1_LVT i_10_134 (.A(n_10_105), .B1(n_10_103), .B2(n_10_106), .ZN( + n_10_107)); + XNOR2_X1_LVT i_10_135 (.A(op2[27]), .B(op1[27]), .ZN(n_10_108)); + INV_X1_LVT i_10_137 (.A(op1[27]), .ZN(n_10_109)); + AOI22_X1_LVT i_10_138 (.A1(n_10_107), .A2(n_10_108), .B1(n_10_109), .B2( + op2[27]), .ZN(n_10_110)); + XOR2_X1_LVT i_10_139 (.A(op2[28]), .B(op1[28]), .Z(n_10_111)); + INV_X1_LVT i_10_141 (.A(op2[28]), .ZN(n_10_112)); + OAI22_X1_LVT i_10_142 (.A1(n_10_110), .A2(n_10_111), .B1(n_10_112), .B2( + op1[28]), .ZN(n_10_113)); + XNOR2_X1_LVT i_10_143 (.A(op2[29]), .B(op1[29]), .ZN(n_10_114)); + INV_X1_LVT i_10_145 (.A(op1[29]), .ZN(n_10_115)); + AOI22_X1_LVT i_10_146 (.A1(n_10_113), .A2(n_10_114), .B1(n_10_115), .B2( + op2[29]), .ZN(n_10_116)); + OR2_X1_LVT i_10_148 (.A1(n_10_117), .A2(op1[30]), .ZN(n_10_118)); + AOI21_X1_LVT i_10_153 (.A(n_10_121), .B1(n_10_116), .B2(n_10_118), .ZN( + n_10_122)); + XNOR2_X1_LVT i_10_154 (.A(op1[31]), .B(op2[31]), .ZN(n_10_123)); + XNOR2_X1_LVT i_10_155 (.A(n_10_122), .B(n_10_123), .ZN(n_63)); + INV_X1_LVT i_0_715 (.A(aluNegAr), .ZN(n_0_682)); + NOR2_X1_LVT i_0_612 (.A1(n_0_682), .A2(n_0_582), .ZN(n_0_580)); + AOI221_X1_LVT i_0_587 (.A(n_0_556), .B1(n_31), .B2(n_0_581), .C1(n_63), + .C2(n_0_580), .ZN(n_0_555)); + NOR3_X1_LVT i_0_654 (.A1(aluOp[1]), .A2(aluBypass), .A3(n_0_683), .ZN(n_0_622)); + NAND2_X1_LVT i_0_653 (.A1(n_0_684), .A2(n_0_622), .ZN(n_0_621)); + INV_X1_LVT i_0_734 (.A(op2[0]), .ZN(n_0_701)); + INV_X1_LVT i_0_756 (.A(op2[3]), .ZN(n_0_723)); + NOR2_X1_LVT i_0_650 (.A1(op2[4]), .A2(n_0_723), .ZN(n_0_618)); + INV_X1_LVT i_0_649 (.A(n_0_618), .ZN(n_0_617)); + NOR2_X1_LVT i_0_648 (.A1(op2[4]), .A2(op2[3]), .ZN(n_0_616)); + INV_X1_LVT i_0_647 (.A(n_0_616), .ZN(n_0_615)); + INV_X1_LVT i_0_771 (.A(op2[4]), .ZN(n_0_738)); + INV_X1_LVT i_0_767 (.A(op1[15]), .ZN(n_0_734)); + INV_X1_LVT i_0_746 (.A(op1[7]), .ZN(n_0_713)); + AOI22_X1_LVT i_0_651 (.A1(n_0_734), .A2(n_0_723), .B1(op2[3]), .B2(n_0_713), + .ZN(n_0_619)); + OAI222_X1_LVT i_0_646 (.A1(op1[23]), .A2(n_0_617), .B1(op1[31]), .B2(n_0_615), + .C1(n_0_738), .C2(n_0_619), .ZN(n_0_614)); + NOR2_X1_LVT i_0_645 (.A1(op2[2]), .A2(n_0_614), .ZN(n_0_613)); + NOR2_X1_LVT i_0_696 (.A1(op1[3]), .A2(n_0_723), .ZN(n_0_663)); + INV_X1_LVT i_0_739 (.A(op1[11]), .ZN(n_0_706)); + AOI21_X1_LVT i_0_644 (.A(n_0_663), .B1(n_0_723), .B2(n_0_706), .ZN(n_0_612)); + AOI22_X1_LVT i_0_643 (.A1(op2[4]), .A2(n_0_612), .B1(op1[27]), .B2(n_0_616), + .ZN(n_0_611)); + INV_X1_LVT i_0_722 (.A(op1[19]), .ZN(n_0_689)); + OAI21_X1_LVT i_0_642 (.A(n_0_611), .B1(n_0_689), .B2(n_0_617), .ZN(n_0_610)); + AOI21_X1_LVT i_0_641 (.A(n_0_613), .B1(op2[2]), .B2(n_0_610), .ZN(n_0_609)); + INV_X1_LVT i_0_761 (.A(op2[1]), .ZN(n_0_728)); + OAI22_X1_LVT i_0_640 (.A1(op2[4]), .A2(op1[21]), .B1(n_0_738), .B2(op1[5]), + .ZN(n_0_608)); + NAND2_X1_LVT i_0_639 (.A1(op2[3]), .A2(n_0_608), .ZN(n_0_607)); + INV_X1_LVT i_0_747 (.A(op1[13]), .ZN(n_0_714)); + NOR2_X1_LVT i_0_638 (.A1(n_0_738), .A2(op2[3]), .ZN(n_0_606)); + INV_X1_LVT i_0_743 (.A(op1[29]), .ZN(n_0_710)); + AOI221_X1_LVT i_0_636 (.A(op2[2]), .B1(n_0_714), .B2(n_0_606), .C1(n_0_710), + .C2(n_0_616), .ZN(n_0_604)); + OAI22_X1_LVT i_0_635 (.A1(op2[4]), .A2(op1[17]), .B1(n_0_738), .B2(op1[1]), + .ZN(n_0_603)); + INV_X1_LVT i_0_755 (.A(op1[9]), .ZN(n_0_722)); + INV_X1_LVT i_0_637 (.A(n_0_606), .ZN(n_0_605)); + INV_X1_LVT i_0_732 (.A(op1[25]), .ZN(n_0_699)); + OAI222_X1_LVT i_0_634 (.A1(n_0_723), .A2(n_0_603), .B1(n_0_722), .B2(n_0_605), + .C1(n_0_699), .C2(n_0_615), .ZN(n_0_602)); + AOI22_X1_LVT i_0_633 (.A1(n_0_607), .A2(n_0_604), .B1(op2[2]), .B2(n_0_602), + .ZN(n_0_601)); + OAI221_X1_LVT i_0_616 (.A(n_0_701), .B1(op2[1]), .B2(n_0_609), .C1(n_0_728), + .C2(n_0_601), .ZN(n_0_584)); + INV_X1_LVT i_0_729 (.A(op1[12]), .ZN(n_0_696)); + INV_X1_LVT i_0_731 (.A(op1[28]), .ZN(n_0_698)); + AOI22_X1_LVT i_0_622 (.A1(n_0_696), .A2(n_0_606), .B1(n_0_698), .B2(n_0_616), + .ZN(n_0_590)); + INV_X1_LVT i_0_726 (.A(op2[2]), .ZN(n_0_693)); + NOR2_X1_LVT i_0_701 (.A1(n_0_738), .A2(op1[4]), .ZN(n_0_668)); + INV_X1_LVT i_0_760 (.A(op1[20]), .ZN(n_0_727)); + AOI21_X1_LVT i_0_623 (.A(n_0_668), .B1(n_0_738), .B2(n_0_727), .ZN(n_0_591)); + OAI211_X1_LVT i_0_621 (.A(n_0_590), .B(n_0_693), .C1(n_0_723), .C2(n_0_591), + .ZN(n_0_589)); + OAI22_X1_LVT i_0_626 (.A1(op1[16]), .A2(op2[4]), .B1(n_0_738), .B2(op1[0]), + .ZN(n_0_594)); + INV_X1_LVT i_0_769 (.A(op1[24]), .ZN(n_0_736)); + OAI22_X1_LVT i_0_625 (.A1(n_0_723), .A2(n_0_594), .B1(n_0_736), .B2(n_0_615), + .ZN(n_0_593)); + AOI21_X1_LVT i_0_624 (.A(n_0_593), .B1(op1[8]), .B2(n_0_606), .ZN(n_0_592)); + OAI21_X1_LVT i_0_620 (.A(n_0_589), .B1(n_0_693), .B2(n_0_592), .ZN(n_0_588)); + INV_X1_LVT i_0_737 (.A(op1[6]), .ZN(n_0_704)); + INV_X1_LVT i_0_720 (.A(op1[22]), .ZN(n_0_687)); + OAI22_X1_LVT i_0_632 (.A1(n_0_738), .A2(n_0_704), .B1(op2[4]), .B2(n_0_687), + .ZN(n_0_600)); + OAI221_X1_LVT i_0_631 (.A(n_0_693), .B1(n_0_723), .B2(n_0_600), .C1(op1[14]), + .C2(n_0_605), .ZN(n_0_599)); + INV_X1_LVT i_0_750 (.A(op1[30]), .ZN(n_0_717)); + AOI21_X1_LVT i_0_630 (.A(n_0_599), .B1(n_0_717), .B2(n_0_616), .ZN(n_0_598)); + INV_X1_LVT i_0_738 (.A(op1[18]), .ZN(n_0_705)); + NOR2_X1_LVT i_0_628 (.A1(n_0_705), .A2(n_0_617), .ZN(n_0_596)); + INV_X1_LVT i_0_727 (.A(op1[2]), .ZN(n_0_694)); + INV_X1_LVT i_0_766 (.A(op1[10]), .ZN(n_0_733)); + OAI22_X1_LVT i_0_629 (.A1(n_0_723), .A2(n_0_694), .B1(n_0_733), .B2(op2[3]), + .ZN(n_0_597)); + AOI221_X1_LVT i_0_627 (.A(n_0_596), .B1(op1[26]), .B2(n_0_616), .C1(op2[4]), + .C2(n_0_597), .ZN(n_0_595)); + OAI21_X1_LVT i_0_619 (.A(n_0_728), .B1(n_0_693), .B2(n_0_595), .ZN(n_0_587)); + OAI22_X1_LVT i_0_618 (.A1(n_0_728), .A2(n_0_588), .B1(n_0_598), .B2(n_0_587), + .ZN(n_0_586)); + INV_X1_LVT i_0_617 (.A(n_0_586), .ZN(n_0_585)); + OAI21_X1_LVT i_0_615 (.A(n_0_584), .B1(n_0_701), .B2(n_0_585), .ZN(n_0_583)); + NOR2_X1_LVT i_0_607 (.A1(op2[4]), .A2(op2[2]), .ZN(n_0_575)); + NAND2_X1_LVT i_0_606 (.A1(n_0_723), .A2(n_0_575), .ZN(n_0_574)); + INV_X1_LVT i_0_605 (.A(n_0_574), .ZN(n_0_573)); + NAND2_X1_LVT i_0_604 (.A1(n_0_728), .A2(n_0_573), .ZN(n_0_572)); + NAND2_X1_LVT i_0_611 (.A1(aluOp[2]), .A2(n_0_622), .ZN(n_0_579)); + INV_X1_LVT i_0_610 (.A(n_0_579), .ZN(n_0_578)); + NAND2_X1_LVT i_0_594 (.A1(n_0_701), .A2(n_0_578), .ZN(n_0_562)); + NOR3_X1_LVT i_0_592 (.A1(aluNegAr), .A2(n_0_572), .A3(n_0_562), .ZN(n_0_560)); + INV_X1_LVT i_0_600 (.A(n_0_569), .ZN(n_0_568)); + OAI21_X1_LVT i_0_595 (.A(n_0_568), .B1(aluOp[1]), .B2(n_0_570), .ZN(n_0_563)); + AOI211_X1_LVT i_0_591 (.A(aluBypass), .B(n_0_560), .C1(n_0_692), .C2(n_0_563), + .ZN(n_0_559)); + OAI221_X1_LVT i_0_586 (.A(n_0_555), .B1(n_0_621), .B2(n_0_583), .C1(n_0_691), + .C2(n_0_559), .ZN(result[31])); + NAND2_X1_LVT i_10_150 (.A1(n_10_118), .A2(n_10_119), .ZN(n_10_120)); + XNOR2_X1_LVT i_10_151 (.A(n_10_116), .B(n_10_120), .ZN(n_62)); + AOI22_X1_LVT i_0_580 (.A1(n_62), .A2(n_0_580), .B1(n_30), .B2(n_0_581), + .ZN(n_0_549)); + NAND2_X1_LVT i_0_576 (.A1(aluNegAr), .A2(n_0_578), .ZN(n_0_545)); + INV_X1_LVT i_0_603 (.A(n_0_572), .ZN(n_0_571)); + NOR3_X1_LVT i_0_574 (.A1(n_0_691), .A2(n_0_545), .A3(n_0_571), .ZN(n_0_543)); + AOI22_X1_LVT i_0_573 (.A1(n_0_717), .A2(n_0_565), .B1(op1[30]), .B2(n_0_566), + .ZN(n_0_542)); + AOI21_X1_LVT i_0_572 (.A(n_0_543), .B1(op2[30]), .B2(n_0_542), .ZN(n_0_541)); + NAND2_X1_LVT i_0_579 (.A1(op2[0]), .A2(n_0_578), .ZN(n_0_548)); + NAND2_X1_LVT i_0_577 (.A1(op1[31]), .A2(n_0_571), .ZN(n_0_546)); + OAI211_X1_LVT i_0_571 (.A(n_0_549), .B(n_0_541), .C1(n_0_548), .C2(n_0_546), + .ZN(n_0_540)); + OAI221_X1_LVT i_0_581 (.A(n_0_681), .B1(op2[30]), .B2(n_0_568), .C1(n_0_572), + .C2(n_0_562), .ZN(n_0_550)); + AOI21_X1_LVT i_0_570 (.A(n_0_540), .B1(op1[30]), .B2(n_0_550), .ZN(n_0_539)); + INV_X1_LVT i_0_752 (.A(op1[23]), .ZN(n_0_719)); + OAI222_X1_LVT i_0_585 (.A1(n_0_713), .A2(n_0_605), .B1(n_0_719), .B2(n_0_615), + .C1(n_0_734), .C2(n_0_617), .ZN(n_0_554)); + AOI22_X1_LVT i_0_584 (.A1(op2[2]), .A2(n_0_554), .B1(n_0_693), .B2(n_0_610), + .ZN(n_0_553)); + OAI22_X1_LVT i_0_583 (.A1(n_0_728), .A2(n_0_553), .B1(op2[1]), .B2(n_0_601), + .ZN(n_0_552)); + AOI22_X1_LVT i_0_582 (.A1(n_0_701), .A2(n_0_585), .B1(op2[0]), .B2(n_0_552), + .ZN(n_0_551)); + OAI21_X1_LVT i_0_569 (.A(n_0_539), .B1(n_0_621), .B2(n_0_551), .ZN(result[30])); + INV_X1_LVT i_0_578 (.A(n_0_548), .ZN(n_0_547)); + NAND3_X1_LVT i_0_562 (.A1(op1[30]), .A2(n_0_571), .A3(n_0_547), .ZN(n_0_532)); + XNOR2_X1_LVT i_10_144 (.A(n_10_113), .B(n_10_114), .ZN(n_61)); + NAND2_X1_LVT i_0_558 (.A1(n_61), .A2(n_0_580), .ZN(n_0_528)); + OAI21_X1_LVT i_0_557 (.A(n_0_681), .B1(op2[29]), .B2(n_0_568), .ZN(n_0_527)); + NAND2_X1_LVT i_0_556 (.A1(op1[29]), .A2(n_0_566), .ZN(n_0_526)); + AOI22_X1_LVT i_0_555 (.A1(op1[29]), .A2(n_0_527), .B1(op2[29]), .B2(n_0_526), + .ZN(n_0_525)); + AOI21_X1_LVT i_0_554 (.A(n_0_525), .B1(n_0_710), .B2(n_0_565), .ZN(n_0_524)); + AOI211_X1_LVT i_0_553 (.A(n_0_543), .B(n_0_524), .C1(n_29), .C2(n_0_581), + .ZN(n_0_523)); + AND3_X1_LVT i_0_552 (.A1(n_0_532), .A2(n_0_528), .A3(n_0_523), .ZN(n_0_522)); + INV_X1_LVT i_0_652 (.A(n_0_621), .ZN(n_0_620)); + NAND2_X1_LVT i_0_565 (.A1(n_0_728), .A2(n_0_588), .ZN(n_0_535)); + AOI22_X1_LVT i_0_568 (.A1(n_0_723), .A2(n_0_600), .B1(op1[14]), .B2(n_0_618), + .ZN(n_0_538)); + AOI22_X1_LVT i_0_567 (.A1(n_0_693), .A2(n_0_595), .B1(op2[2]), .B2(n_0_538), + .ZN(n_0_537)); + INV_X1_LVT i_0_566 (.A(n_0_537), .ZN(n_0_536)); + OAI21_X1_LVT i_0_564 (.A(n_0_535), .B1(n_0_728), .B2(n_0_536), .ZN(n_0_534)); + OAI221_X1_LVT i_0_563 (.A(n_0_620), .B1(op2[0]), .B2(n_0_552), .C1(n_0_701), + .C2(n_0_534), .ZN(n_0_533)); + NAND2_X1_LVT i_0_561 (.A1(op2[1]), .A2(n_0_573), .ZN(n_0_531)); + INV_X1_LVT i_0_560 (.A(n_0_531), .ZN(n_0_530)); + AOI22_X1_LVT i_0_559 (.A1(op1[31]), .A2(n_0_530), .B1(op1[29]), .B2(n_0_571), + .ZN(n_0_529)); + OAI211_X1_LVT i_0_551 (.A(n_0_522), .B(n_0_533), .C1(n_0_562), .C2(n_0_529), + .ZN(result[29])); + INV_X1_LVT i_0_733 (.A(op2[28]), .ZN(n_0_700)); + AOI221_X1_LVT i_0_546 (.A(n_0_700), .B1(op1[28]), .B2(n_0_566), .C1(n_0_698), + .C2(n_0_565), .ZN(n_0_517)); + OAI21_X1_LVT i_0_543 (.A(n_0_681), .B1(op2[28]), .B2(n_0_568), .ZN(n_0_514)); + AOI22_X1_LVT i_0_542 (.A1(n_28), .A2(n_0_581), .B1(op1[28]), .B2(n_0_514), + .ZN(n_0_513)); + XNOR2_X1_LVT i_10_140 (.A(n_10_110), .B(n_10_111), .ZN(n_60)); + NAND2_X1_LVT i_0_544 (.A1(n_60), .A2(n_0_580), .ZN(n_0_515)); + NAND2_X1_LVT i_0_545 (.A1(op1[31]), .A2(n_0_574), .ZN(n_0_516)); + OAI211_X1_LVT i_0_541 (.A(n_0_513), .B(n_0_515), .C1(n_0_545), .C2(n_0_516), + .ZN(n_0_512)); + AOI22_X1_LVT i_0_540 (.A1(op1[30]), .A2(n_0_530), .B1(op1[28]), .B2(n_0_571), + .ZN(n_0_511)); + OAI22_X1_LVT i_0_539 (.A1(n_0_562), .A2(n_0_511), .B1(n_0_548), .B2(n_0_529), + .ZN(n_0_510)); + NOR3_X1_LVT i_0_538 (.A1(n_0_517), .A2(n_0_512), .A3(n_0_510), .ZN(n_0_509)); + OAI22_X1_LVT i_0_550 (.A1(n_0_714), .A2(n_0_617), .B1(op2[3]), .B2(n_0_608), + .ZN(n_0_521)); + OAI22_X1_LVT i_0_549 (.A1(op2[2]), .A2(n_0_602), .B1(n_0_693), .B2(n_0_521), + .ZN(n_0_520)); + AOI22_X1_LVT i_0_548 (.A1(op2[1]), .A2(n_0_520), .B1(n_0_728), .B2(n_0_553), + .ZN(n_0_519)); + OAI22_X1_LVT i_0_547 (.A1(op2[0]), .A2(n_0_534), .B1(n_0_701), .B2(n_0_519), + .ZN(n_0_518)); + OAI21_X1_LVT i_0_537 (.A(n_0_509), .B1(n_0_621), .B2(n_0_518), .ZN(result[28])); + XNOR2_X1_LVT i_10_136 (.A(n_10_107), .B(n_10_108), .ZN(n_59)); + AOI22_X1_LVT i_0_517 (.A1(n_27), .A2(n_0_581), .B1(n_59), .B2(n_0_580), + .ZN(n_0_489)); + INV_X1_LVT i_0_721 (.A(op1[27]), .ZN(n_0_688)); + OAI21_X1_LVT i_0_516 (.A(n_0_681), .B1(op2[27]), .B2(n_0_568), .ZN(n_0_488)); + INV_X1_LVT i_0_515 (.A(n_0_488), .ZN(n_0_487)); + OAI221_X1_LVT i_0_514 (.A(n_0_489), .B1(n_0_545), .B2(n_0_516), .C1(n_0_688), + .C2(n_0_487), .ZN(n_0_486)); + OAI21_X1_LVT i_0_530 (.A(op2[1]), .B1(n_0_710), .B2(n_0_574), .ZN(n_0_502)); + OAI21_X1_LVT i_0_529 (.A(n_0_728), .B1(n_0_688), .B2(n_0_574), .ZN(n_0_501)); + NAND2_X1_LVT i_0_528 (.A1(n_0_502), .A2(n_0_501), .ZN(n_0_500)); + AOI21_X1_LVT i_0_527 (.A(n_0_545), .B1(n_0_701), .B2(n_0_500), .ZN(n_0_499)); + NAND2_X1_LVT i_0_609 (.A1(n_0_682), .A2(n_0_578), .ZN(n_0_577)); + NOR2_X1_LVT i_0_526 (.A1(op2[4]), .A2(n_0_693), .ZN(n_0_498)); + NAND2_X1_LVT i_0_525 (.A1(n_0_723), .A2(n_0_498), .ZN(n_0_497)); + OAI22_X1_LVT i_0_523 (.A1(n_0_688), .A2(n_0_574), .B1(n_0_691), .B2(n_0_497), + .ZN(n_0_495)); + OAI21_X1_LVT i_0_522 (.A(n_0_502), .B1(op2[1]), .B2(n_0_495), .ZN(n_0_494)); + AOI21_X1_LVT i_0_521 (.A(n_0_577), .B1(n_0_701), .B2(n_0_494), .ZN(n_0_493)); + NOR2_X1_LVT i_0_520 (.A1(n_0_499), .A2(n_0_493), .ZN(n_0_492)); + AOI21_X1_LVT i_0_519 (.A(n_0_492), .B1(op2[0]), .B2(n_0_511), .ZN(n_0_491)); + AOI22_X1_LVT i_0_518 (.A1(n_0_688), .A2(n_0_565), .B1(op1[27]), .B2(n_0_566), + .ZN(n_0_490)); + AOI211_X1_LVT i_0_513 (.A(n_0_486), .B(n_0_491), .C1(op2[27]), .C2(n_0_490), + .ZN(n_0_485)); + NOR3_X1_LVT i_0_536 (.A1(op2[4]), .A2(n_0_696), .A3(n_0_723), .ZN(n_0_508)); + AOI21_X1_LVT i_0_535 (.A(n_0_508), .B1(n_0_723), .B2(n_0_591), .ZN(n_0_507)); + OAI22_X1_LVT i_0_534 (.A1(op2[2]), .A2(n_0_592), .B1(n_0_693), .B2(n_0_507), + .ZN(n_0_506)); + NOR2_X1_LVT i_0_533 (.A1(n_0_728), .A2(n_0_506), .ZN(n_0_505)); + AOI21_X1_LVT i_0_532 (.A(n_0_505), .B1(n_0_728), .B2(n_0_536), .ZN(n_0_504)); + OAI22_X1_LVT i_0_531 (.A1(n_0_701), .A2(n_0_504), .B1(op2[0]), .B2(n_0_519), + .ZN(n_0_503)); + OAI21_X1_LVT i_0_512 (.A(n_0_485), .B1(n_0_621), .B2(n_0_503), .ZN(result[27])); + OAI21_X1_LVT i_0_500 (.A(n_0_681), .B1(op2[26]), .B2(n_0_568), .ZN(n_0_473)); + NAND2_X1_LVT i_0_499 (.A1(op1[26]), .A2(n_0_473), .ZN(n_0_472)); + XNOR2_X1_LVT i_10_133 (.A(n_10_103), .B(n_10_106), .ZN(n_58)); + AOI22_X1_LVT i_0_498 (.A1(n_58), .A2(n_0_580), .B1(n_26), .B2(n_0_581), + .ZN(n_0_471)); + INV_X1_LVT i_0_744 (.A(op1[26]), .ZN(n_0_711)); + OAI221_X1_LVT i_0_501 (.A(op2[26]), .B1(op1[26]), .B2(n_0_564), .C1(n_0_711), + .C2(n_0_567), .ZN(n_0_474)); + NAND3_X1_LVT i_0_497 (.A1(n_0_472), .A2(n_0_471), .A3(n_0_474), .ZN(n_0_470)); + INV_X1_LVT i_0_524 (.A(n_0_497), .ZN(n_0_496)); + AOI22_X1_LVT i_0_505 (.A1(op1[30]), .A2(n_0_496), .B1(op1[26]), .B2(n_0_573), + .ZN(n_0_478)); + NOR2_X1_LVT i_0_504 (.A1(op2[1]), .A2(n_0_478), .ZN(n_0_477)); + AOI21_X1_LVT i_0_503 (.A(n_0_477), .B1(op1[28]), .B2(n_0_530), .ZN(n_0_476)); + NAND2_X1_LVT i_0_502 (.A1(n_0_701), .A2(n_0_476), .ZN(n_0_475)); + AOI21_X1_LVT i_0_489 (.A(n_0_577), .B1(op2[0]), .B2(n_0_494), .ZN(n_0_462)); + AOI21_X1_LVT i_0_488 (.A(n_0_470), .B1(n_0_475), .B2(n_0_462), .ZN(n_0_461)); + AOI21_X1_LVT i_0_511 (.A(n_0_616), .B1(n_0_738), .B2(n_0_706), .ZN(n_0_484)); + AOI21_X1_LVT i_0_510 (.A(n_0_484), .B1(n_0_723), .B2(op1[19]), .ZN(n_0_483)); + INV_X1_LVT i_0_757 (.A(op1[3]), .ZN(n_0_724)); + NOR2_X1_LVT i_0_687 (.A1(n_0_724), .A2(op2[3]), .ZN(n_0_654)); + INV_X1_LVT i_0_686 (.A(n_0_654), .ZN(n_0_653)); + AOI21_X1_LVT i_0_509 (.A(n_0_483), .B1(op2[4]), .B2(n_0_653), .ZN(n_0_482)); + AOI22_X1_LVT i_0_508 (.A1(n_0_693), .A2(n_0_554), .B1(op2[2]), .B2(n_0_482), + .ZN(n_0_481)); + OAI22_X1_LVT i_0_507 (.A1(n_0_728), .A2(n_0_481), .B1(op2[1]), .B2(n_0_520), + .ZN(n_0_480)); + AOI22_X1_LVT i_0_506 (.A1(op2[0]), .A2(n_0_480), .B1(n_0_701), .B2(n_0_504), + .ZN(n_0_479)); + NAND3_X1_LVT i_0_491 (.A1(op2[0]), .A2(n_0_516), .A3(n_0_500), .ZN(n_0_464)); + NAND2_X1_LVT i_0_494 (.A1(op1[31]), .A2(n_0_615), .ZN(n_0_467)); + OAI21_X1_LVT i_0_492 (.A(n_0_467), .B1(n_0_728), .B2(n_0_516), .ZN(n_0_465)); + OAI21_X1_LVT i_0_490 (.A(n_0_464), .B1(n_0_475), .B2(n_0_465), .ZN(n_0_463)); + OAI221_X1_LVT i_0_487 (.A(n_0_461), .B1(n_0_621), .B2(n_0_479), .C1(n_0_545), + .C2(n_0_463), .ZN(result[26])); + INV_X1_LVT i_10_126 (.A(n_10_100), .ZN(n_10_101)); + NOR2_X1_LVT i_10_127 (.A1(n_10_99), .A2(n_10_101), .ZN(n_10_102)); + XNOR2_X1_LVT i_10_128 (.A(n_10_97), .B(n_10_102), .ZN(n_57)); + AOI22_X1_LVT i_0_479 (.A1(n_57), .A2(n_0_580), .B1(n_25), .B2(n_0_581), + .ZN(n_0_453)); + INV_X1_LVT i_0_730 (.A(op2[25]), .ZN(n_0_697)); + AOI21_X1_LVT i_0_478 (.A(aluBypass), .B1(n_0_697), .B2(n_0_569), .ZN(n_0_452)); + AOI22_X1_LVT i_0_480 (.A1(op1[25]), .A2(n_0_567), .B1(n_0_699), .B2(n_0_564), + .ZN(n_0_454)); + OAI221_X1_LVT i_0_477 (.A(n_0_453), .B1(n_0_699), .B2(n_0_452), .C1(n_0_697), + .C2(n_0_454), .ZN(n_0_451)); + INV_X1_LVT i_0_575 (.A(n_0_545), .ZN(n_0_544)); + AOI21_X1_LVT i_0_476 (.A(n_0_451), .B1(n_0_544), .B2(n_0_465), .ZN(n_0_450)); + AOI22_X1_LVT i_0_475 (.A1(op1[29]), .A2(n_0_496), .B1(op1[25]), .B2(n_0_573), + .ZN(n_0_449)); + NAND2_X1_LVT i_0_474 (.A1(n_0_728), .A2(n_0_449), .ZN(n_0_448)); + OAI21_X1_LVT i_0_473 (.A(n_0_448), .B1(n_0_728), .B2(n_0_495), .ZN(n_0_447)); + OAI22_X1_LVT i_0_472 (.A1(n_0_548), .A2(n_0_476), .B1(n_0_562), .B2(n_0_447), + .ZN(n_0_446)); + INV_X1_LVT i_0_471 (.A(n_0_446), .ZN(n_0_445)); + OAI222_X1_LVT i_0_486 (.A1(n_0_733), .A2(n_0_617), .B1(n_0_694), .B2(n_0_605), + .C1(n_0_705), .C2(n_0_615), .ZN(n_0_460)); + NOR2_X1_LVT i_0_485 (.A1(n_0_693), .A2(n_0_460), .ZN(n_0_459)); + AOI21_X1_LVT i_0_484 (.A(n_0_459), .B1(n_0_693), .B2(n_0_538), .ZN(n_0_458)); + OAI22_X1_LVT i_0_483 (.A1(n_0_728), .A2(n_0_458), .B1(op2[1]), .B2(n_0_506), + .ZN(n_0_457)); + INV_X1_LVT i_0_482 (.A(n_0_457), .ZN(n_0_456)); + OAI221_X1_LVT i_0_481 (.A(n_0_620), .B1(n_0_701), .B2(n_0_456), .C1(op2[0]), + .C2(n_0_480), .ZN(n_0_455)); + NAND3_X1_LVT i_0_470 (.A1(n_0_450), .A2(n_0_445), .A3(n_0_455), .ZN( + result[25])); + INV_X1_LVT i_0_493 (.A(n_0_467), .ZN(n_0_466)); + OAI211_X1_LVT i_0_455 (.A(n_0_544), .B(n_0_465), .C1(op2[0]), .C2(n_0_466), + .ZN(n_0_430)); + OAI21_X1_LVT i_0_462 (.A(n_0_681), .B1(op2[24]), .B2(n_0_568), .ZN(n_0_437)); + XNOR2_X1_LVT i_10_120 (.A(n_10_94), .B(n_10_95), .ZN(n_56)); + AOI222_X1_LVT i_0_461 (.A1(op1[24]), .A2(n_0_437), .B1(n_56), .B2(n_0_580), + .C1(n_24), .C2(n_0_581), .ZN(n_0_436)); + INV_X1_LVT i_0_460 (.A(n_0_436), .ZN(n_0_435)); + AOI22_X1_LVT i_0_458 (.A1(op1[24]), .A2(n_0_573), .B1(op1[28]), .B2(n_0_496), + .ZN(n_0_433)); + OAI22_X1_LVT i_0_457 (.A1(op2[1]), .A2(n_0_433), .B1(n_0_728), .B2(n_0_478), + .ZN(n_0_432)); + INV_X1_LVT i_0_456 (.A(n_0_432), .ZN(n_0_431)); + OAI22_X1_LVT i_0_454 (.A1(n_0_562), .A2(n_0_431), .B1(n_0_548), .B2(n_0_447), + .ZN(n_0_429)); + AOI22_X1_LVT i_0_459 (.A1(n_0_736), .A2(n_0_565), .B1(op1[24]), .B2(n_0_566), + .ZN(n_0_434)); + AOI211_X1_LVT i_0_453 (.A(n_0_435), .B(n_0_429), .C1(op2[24]), .C2(n_0_434), + .ZN(n_0_428)); + NAND2_X1_LVT i_0_467 (.A1(n_0_693), .A2(n_0_521), .ZN(n_0_442)); + NOR2_X1_LVT i_0_469 (.A1(op2[3]), .A2(n_0_603), .ZN(n_0_444)); + AOI21_X1_LVT i_0_468 (.A(n_0_444), .B1(op1[9]), .B2(n_0_618), .ZN(n_0_443)); + OAI21_X1_LVT i_0_466 (.A(n_0_442), .B1(n_0_693), .B2(n_0_443), .ZN(n_0_441)); + NAND2_X1_LVT i_0_465 (.A1(op2[1]), .A2(n_0_441), .ZN(n_0_440)); + OAI21_X1_LVT i_0_464 (.A(n_0_440), .B1(op2[1]), .B2(n_0_481), .ZN(n_0_439)); + OAI221_X1_LVT i_0_463 (.A(n_0_620), .B1(op2[0]), .B2(n_0_456), .C1(n_0_701), + .C2(n_0_439), .ZN(n_0_438)); + NAND3_X1_LVT i_0_452 (.A1(n_0_430), .A2(n_0_428), .A3(n_0_438), .ZN( + result[24])); + INV_X1_LVT i_0_751 (.A(op2[23]), .ZN(n_0_718)); + AOI221_X1_LVT i_0_440 (.A(n_0_718), .B1(op1[23]), .B2(n_0_566), .C1(n_0_719), + .C2(n_0_565), .ZN(n_0_416)); + INV_X1_LVT i_10_115 (.A(n_10_91), .ZN(n_10_92)); + NOR2_X1_LVT i_10_116 (.A1(n_10_90), .A2(n_10_92), .ZN(n_10_93)); + XNOR2_X1_LVT i_10_117 (.A(n_10_88), .B(n_10_93), .ZN(n_55)); + AOI222_X1_LVT i_0_438 (.A1(n_23), .A2(n_0_581), .B1(n_0_544), .B2(n_0_466), + .C1(n_55), .C2(n_0_580), .ZN(n_0_414)); + OAI21_X1_LVT i_0_437 (.A(n_0_414), .B1(n_0_548), .B2(n_0_431), .ZN(n_0_413)); + OAI21_X1_LVT i_0_439 (.A(n_0_681), .B1(op2[23]), .B2(n_0_568), .ZN(n_0_415)); + AOI211_X1_LVT i_0_436 (.A(n_0_416), .B(n_0_413), .C1(op1[23]), .C2(n_0_415), + .ZN(n_0_412)); + AOI22_X1_LVT i_0_444 (.A1(n_0_723), .A2(n_0_719), .B1(op2[3]), .B2(n_0_691), + .ZN(n_0_420)); + AOI22_X1_LVT i_0_443 (.A1(n_0_575), .A2(n_0_420), .B1(op1[27]), .B2(n_0_496), + .ZN(n_0_419)); + AOI22_X1_LVT i_0_442 (.A1(op2[1]), .A2(n_0_449), .B1(n_0_728), .B2(n_0_419), + .ZN(n_0_418)); + INV_X1_LVT i_0_441 (.A(n_0_418), .ZN(n_0_417)); + NAND2_X1_LVT i_0_447 (.A1(n_0_728), .A2(n_0_458), .ZN(n_0_423)); + NOR2_X1_LVT i_0_451 (.A1(op2[3]), .A2(n_0_594), .ZN(n_0_427)); + AOI21_X1_LVT i_0_450 (.A(n_0_427), .B1(op1[8]), .B2(n_0_618), .ZN(n_0_426)); + OAI22_X1_LVT i_0_449 (.A1(n_0_693), .A2(n_0_426), .B1(op2[2]), .B2(n_0_507), + .ZN(n_0_425)); + INV_X1_LVT i_0_448 (.A(n_0_425), .ZN(n_0_424)); + OAI21_X1_LVT i_0_446 (.A(n_0_423), .B1(n_0_728), .B2(n_0_424), .ZN(n_0_422)); + AOI22_X1_LVT i_0_445 (.A1(op2[0]), .A2(n_0_422), .B1(n_0_701), .B2(n_0_439), + .ZN(n_0_421)); + OAI221_X1_LVT i_0_435 (.A(n_0_412), .B1(n_0_562), .B2(n_0_417), .C1(n_0_621), + .C2(n_0_421), .ZN(result[23])); + XNOR2_X1_LVT i_10_109 (.A(n_10_85), .B(n_10_86), .ZN(n_54)); + AOI22_X1_LVT i_0_419 (.A1(n_54), .A2(n_0_580), .B1(n_22), .B2(n_0_581), + .ZN(n_0_396)); + INV_X1_LVT i_0_719 (.A(op2[22]), .ZN(n_0_686)); + AOI21_X1_LVT i_0_420 (.A(aluBypass), .B1(n_0_686), .B2(n_0_569), .ZN(n_0_397)); + OAI21_X1_LVT i_0_418 (.A(n_0_396), .B1(n_0_687), .B2(n_0_397), .ZN(n_0_395)); + AOI22_X1_LVT i_0_421 (.A1(op1[22]), .A2(n_0_566), .B1(n_0_687), .B2(n_0_565), + .ZN(n_0_398)); + AOI21_X1_LVT i_0_417 (.A(n_0_395), .B1(op2[22]), .B2(n_0_398), .ZN(n_0_394)); + NAND2_X1_LVT i_0_432 (.A1(n_0_728), .A2(n_0_441), .ZN(n_0_409)); + AND2_X1_LVT i_0_434 (.A1(n_0_738), .A2(n_0_619), .ZN(n_0_411)); + AOI22_X1_LVT i_0_433 (.A1(n_0_693), .A2(n_0_482), .B1(op2[2]), .B2(n_0_411), + .ZN(n_0_410)); + OAI21_X1_LVT i_0_431 (.A(n_0_409), .B1(n_0_728), .B2(n_0_410), .ZN(n_0_408)); + OAI22_X1_LVT i_0_430 (.A1(n_0_701), .A2(n_0_408), .B1(op2[0]), .B2(n_0_422), + .ZN(n_0_407)); + AOI22_X1_LVT i_0_429 (.A1(n_0_723), .A2(n_0_687), .B1(op2[3]), .B2(n_0_717), + .ZN(n_0_406)); + AOI22_X1_LVT i_0_428 (.A1(n_0_575), .A2(n_0_406), .B1(op1[26]), .B2(n_0_496), + .ZN(n_0_405)); + AND2_X1_LVT i_0_427 (.A1(n_0_728), .A2(n_0_405), .ZN(n_0_404)); + AOI21_X1_LVT i_0_426 (.A(n_0_404), .B1(op2[1]), .B2(n_0_433), .ZN(n_0_403)); + INV_X1_LVT i_0_425 (.A(n_0_403), .ZN(n_0_402)); + OAI222_X1_LVT i_0_424 (.A1(n_0_545), .A2(n_0_467), .B1(n_0_701), .B2(n_0_417), + .C1(op2[0]), .C2(n_0_402), .ZN(n_0_401)); + NOR2_X1_LVT i_0_496 (.A1(n_0_738), .A2(n_0_691), .ZN(n_0_469)); + INV_X1_LVT i_0_495 (.A(n_0_469), .ZN(n_0_468)); + NAND3_X1_LVT i_0_423 (.A1(n_0_693), .A2(n_0_468), .A3(n_0_404), .ZN(n_0_400)); + OAI21_X1_LVT i_0_422 (.A(n_0_401), .B1(op2[0]), .B2(n_0_400), .ZN(n_0_399)); + OAI221_X1_LVT i_0_416 (.A(n_0_394), .B1(n_0_621), .B2(n_0_407), .C1(n_0_579), + .C2(n_0_399), .ZN(result[22])); + INV_X1_LVT i_0_759 (.A(op1[21]), .ZN(n_0_726)); + AOI22_X1_LVT i_0_399 (.A1(op1[21]), .A2(n_0_566), .B1(n_0_726), .B2(n_0_565), + .ZN(n_0_377)); + NOR2_X1_LVT i_0_692 (.A1(n_0_726), .A2(op2[21]), .ZN(n_0_659)); + AOI222_X1_LVT i_0_398 (.A1(op2[21]), .A2(n_0_377), .B1(n_21), .B2(n_0_581), + .C1(n_0_659), .C2(n_0_569), .ZN(n_0_376)); + INV_X1_LVT i_0_397 (.A(n_0_376), .ZN(n_0_375)); + INV_X1_LVT i_10_104 (.A(n_10_82), .ZN(n_10_83)); + NOR2_X1_LVT i_10_105 (.A1(n_10_81), .A2(n_10_83), .ZN(n_10_84)); + XNOR2_X1_LVT i_10_106 (.A(n_10_79), .B(n_10_84), .ZN(n_53)); + AOI221_X1_LVT i_0_396 (.A(n_0_375), .B1(n_53), .B2(n_0_580), .C1(op1[21]), + .C2(aluBypass), .ZN(n_0_374)); + INV_X1_LVT i_0_608 (.A(n_0_577), .ZN(n_0_576)); + NAND2_X1_LVT i_0_403 (.A1(op2[0]), .A2(n_0_402), .ZN(n_0_381)); + AND2_X1_LVT i_0_410 (.A1(op2[1]), .A2(n_0_419), .ZN(n_0_388)); + OAI22_X1_LVT i_0_408 (.A1(n_0_723), .A2(n_0_710), .B1(n_0_726), .B2(op2[3]), + .ZN(n_0_386)); + AOI22_X1_LVT i_0_407 (.A1(n_0_575), .A2(n_0_386), .B1(op1[25]), .B2(n_0_496), + .ZN(n_0_385)); + AOI21_X1_LVT i_0_395 (.A(n_0_388), .B1(n_0_728), .B2(n_0_385), .ZN(n_0_373)); + OAI211_X1_LVT i_0_394 (.A(n_0_576), .B(n_0_381), .C1(op2[0]), .C2(n_0_373), + .ZN(n_0_372)); + AOI21_X1_LVT i_0_402 (.A(n_0_381), .B1(n_0_466), .B2(n_0_400), .ZN(n_0_380)); + INV_X1_LVT i_0_401 (.A(n_0_380), .ZN(n_0_379)); + NOR2_X1_LVT i_0_409 (.A1(n_0_575), .A2(n_0_467), .ZN(n_0_387)); + INV_X1_LVT i_0_406 (.A(n_0_385), .ZN(n_0_384)); + NOR2_X1_LVT i_0_405 (.A1(n_0_387), .A2(n_0_384), .ZN(n_0_383)); + AOI22_X1_LVT i_0_404 (.A1(n_0_467), .A2(n_0_388), .B1(n_0_728), .B2(n_0_383), + .ZN(n_0_382)); + OAI211_X1_LVT i_0_400 (.A(n_0_544), .B(n_0_379), .C1(op2[0]), .C2(n_0_382), + .ZN(n_0_378)); + AOI22_X1_LVT i_0_415 (.A1(op1[14]), .A2(n_0_616), .B1(op1[6]), .B2(n_0_618), + .ZN(n_0_393)); + NOR2_X1_LVT i_0_414 (.A1(n_0_693), .A2(n_0_393), .ZN(n_0_392)); + AOI21_X1_LVT i_0_413 (.A(n_0_392), .B1(n_0_693), .B2(n_0_460), .ZN(n_0_391)); + OAI22_X1_LVT i_0_412 (.A1(n_0_728), .A2(n_0_391), .B1(op2[1]), .B2(n_0_424), + .ZN(n_0_390)); + OAI221_X1_LVT i_0_411 (.A(n_0_620), .B1(op2[0]), .B2(n_0_408), .C1(n_0_701), + .C2(n_0_390), .ZN(n_0_389)); + NAND4_X1_LVT i_0_393 (.A1(n_0_374), .A2(n_0_372), .A3(n_0_378), .A4(n_0_389), + .ZN(result[21])); + OAI221_X1_LVT i_0_388 (.A(op2[20]), .B1(n_0_727), .B2(n_0_567), .C1(op1[20]), + .C2(n_0_564), .ZN(n_0_367)); + NOR2_X1_LVT i_0_691 (.A1(n_0_727), .A2(op2[20]), .ZN(n_0_658)); + AOI22_X1_LVT i_0_387 (.A1(op1[20]), .A2(aluBypass), .B1(n_0_658), .B2(n_0_569), + .ZN(n_0_366)); + XNOR2_X1_LVT i_10_98 (.A(n_10_76), .B(n_10_77), .ZN(n_52)); + AOI22_X1_LVT i_0_386 (.A1(n_52), .A2(n_0_580), .B1(n_20), .B2(n_0_581), + .ZN(n_0_365)); + AOI221_X1_LVT i_0_392 (.A(op2[4]), .B1(n_0_727), .B2(n_0_723), .C1(op2[3]), + .C2(n_0_698), .ZN(n_0_371)); + AOI22_X1_LVT i_0_391 (.A1(op1[24]), .A2(n_0_496), .B1(n_0_693), .B2(n_0_371), + .ZN(n_0_370)); + OAI22_X1_LVT i_0_390 (.A1(op2[1]), .A2(n_0_370), .B1(n_0_728), .B2(n_0_405), + .ZN(n_0_369)); + OAI221_X1_LVT i_0_385 (.A(n_0_576), .B1(n_0_701), .B2(n_0_373), .C1(op2[0]), + .C2(n_0_369), .ZN(n_0_364)); + AND4_X1_LVT i_0_384 (.A1(n_0_367), .A2(n_0_366), .A3(n_0_365), .A4(n_0_364), + .ZN(n_0_363)); + AOI22_X1_LVT i_0_383 (.A1(op1[13]), .A2(n_0_616), .B1(op1[5]), .B2(n_0_618), + .ZN(n_0_362)); + AOI22_X1_LVT i_0_382 (.A1(op2[2]), .A2(n_0_362), .B1(n_0_693), .B2(n_0_443), + .ZN(n_0_361)); + NAND2_X1_LVT i_0_381 (.A1(op2[1]), .A2(n_0_361), .ZN(n_0_360)); + OAI21_X1_LVT i_0_380 (.A(n_0_360), .B1(op2[1]), .B2(n_0_410), .ZN(n_0_359)); + OAI221_X1_LVT i_0_379 (.A(n_0_620), .B1(n_0_701), .B2(n_0_359), .C1(op2[0]), + .C2(n_0_390), .ZN(n_0_358)); + OR2_X1_LVT i_0_389 (.A1(n_0_387), .A2(n_0_369), .ZN(n_0_368)); + AOI22_X1_LVT i_0_378 (.A1(op2[0]), .A2(n_0_382), .B1(n_0_701), .B2(n_0_368), + .ZN(n_0_357)); + OAI211_X1_LVT i_0_377 (.A(n_0_363), .B(n_0_358), .C1(n_0_545), .C2(n_0_357), + .ZN(result[20])); + OAI22_X1_LVT i_0_370 (.A1(op2[3]), .A2(n_0_689), .B1(n_0_723), .B2(n_0_688), + .ZN(n_0_350)); + AND2_X1_LVT i_0_369 (.A1(n_0_738), .A2(n_0_350), .ZN(n_0_349)); + AOI22_X1_LVT i_0_368 (.A1(n_0_498), .A2(n_0_420), .B1(n_0_693), .B2(n_0_349), + .ZN(n_0_348)); + AND2_X1_LVT i_0_367 (.A1(n_0_728), .A2(n_0_348), .ZN(n_0_347)); + AOI21_X1_LVT i_0_359 (.A(n_0_347), .B1(op2[1]), .B2(n_0_385), .ZN(n_0_339)); + OAI221_X1_LVT i_0_357 (.A(n_0_576), .B1(n_0_701), .B2(n_0_369), .C1(op2[0]), + .C2(n_0_339), .ZN(n_0_337)); + NAND2_X1_LVT i_0_363 (.A1(n_19), .A2(n_0_581), .ZN(n_0_343)); + INV_X1_LVT i_0_723 (.A(op2[19]), .ZN(n_0_690)); + AOI221_X1_LVT i_0_364 (.A(n_0_690), .B1(n_0_689), .B2(n_0_565), .C1(op1[19]), + .C2(n_0_566), .ZN(n_0_344)); + XNOR2_X1_LVT i_10_94 (.A(n_10_73), .B(n_10_74), .ZN(n_51)); + AOI221_X1_LVT i_0_361 (.A(n_0_344), .B1(op1[19]), .B2(aluBypass), .C1(n_51), + .C2(n_0_580), .ZN(n_0_341)); + NAND3_X1_LVT i_0_362 (.A1(n_0_690), .A2(op1[19]), .A3(n_0_569), .ZN(n_0_342)); + NAND3_X1_LVT i_0_360 (.A1(n_0_343), .A2(n_0_341), .A3(n_0_342), .ZN(n_0_340)); + AOI22_X1_LVT i_0_376 (.A1(op1[12]), .A2(n_0_616), .B1(op1[4]), .B2(n_0_618), + .ZN(n_0_356)); + OAI22_X1_LVT i_0_375 (.A1(n_0_693), .A2(n_0_356), .B1(op2[2]), .B2(n_0_426), + .ZN(n_0_355)); + INV_X1_LVT i_0_374 (.A(n_0_355), .ZN(n_0_354)); + OAI22_X1_LVT i_0_373 (.A1(op2[1]), .A2(n_0_391), .B1(n_0_728), .B2(n_0_354), + .ZN(n_0_353)); + AOI22_X1_LVT i_0_372 (.A1(n_0_701), .A2(n_0_359), .B1(op2[0]), .B2(n_0_353), + .ZN(n_0_352)); + INV_X1_LVT i_0_371 (.A(n_0_352), .ZN(n_0_351)); + AOI21_X1_LVT i_0_358 (.A(n_0_340), .B1(n_0_620), .B2(n_0_351), .ZN(n_0_338)); + AOI22_X1_LVT i_0_366 (.A1(n_0_468), .A2(n_0_347), .B1(op2[1]), .B2(n_0_383), + .ZN(n_0_346)); + AOI22_X1_LVT i_0_365 (.A1(n_0_701), .A2(n_0_346), .B1(op2[0]), .B2(n_0_368), + .ZN(n_0_345)); + OAI211_X1_LVT i_0_356 (.A(n_0_337), .B(n_0_338), .C1(n_0_545), .C2(n_0_345), + .ZN(result[19])); + XNOR2_X1_LVT i_10_90 (.A(n_10_70), .B(n_10_71), .ZN(n_50)); + NAND2_X1_LVT i_0_342 (.A1(n_50), .A2(n_0_580), .ZN(n_0_323)); + OAI21_X1_LVT i_0_343 (.A(n_0_681), .B1(op2[18]), .B2(n_0_568), .ZN(n_0_324)); + AOI22_X1_LVT i_0_341 (.A1(op1[18]), .A2(n_0_324), .B1(n_18), .B2(n_0_581), + .ZN(n_0_322)); + OAI221_X1_LVT i_0_340 (.A(op2[18]), .B1(n_0_705), .B2(n_0_567), .C1(op1[18]), + .C2(n_0_564), .ZN(n_0_321)); + NAND3_X1_LVT i_0_339 (.A1(n_0_323), .A2(n_0_322), .A3(n_0_321), .ZN(n_0_320)); + OAI22_X1_LVT i_0_351 (.A1(op2[3]), .A2(n_0_705), .B1(n_0_723), .B2(n_0_711), + .ZN(n_0_332)); + AND2_X1_LVT i_0_350 (.A1(n_0_738), .A2(n_0_332), .ZN(n_0_331)); + AOI22_X1_LVT i_0_349 (.A1(n_0_498), .A2(n_0_406), .B1(n_0_693), .B2(n_0_331), + .ZN(n_0_330)); + NAND2_X1_LVT i_0_348 (.A1(n_0_728), .A2(n_0_330), .ZN(n_0_329)); + NAND2_X1_LVT i_0_347 (.A1(op2[1]), .A2(n_0_370), .ZN(n_0_328)); + AND2_X1_LVT i_0_338 (.A1(n_0_329), .A2(n_0_328), .ZN(n_0_319)); + OAI22_X1_LVT i_0_337 (.A1(op2[0]), .A2(n_0_319), .B1(n_0_701), .B2(n_0_339), + .ZN(n_0_318)); + INV_X1_LVT i_0_336 (.A(n_0_318), .ZN(n_0_317)); + AOI21_X1_LVT i_0_335 (.A(n_0_320), .B1(n_0_578), .B2(n_0_317), .ZN(n_0_316)); + OAI22_X1_LVT i_0_346 (.A1(n_0_469), .A2(n_0_329), .B1(n_0_387), .B2(n_0_328), + .ZN(n_0_327)); + NAND2_X1_LVT i_0_344 (.A1(n_0_544), .A2(n_0_346), .ZN(n_0_325)); + NAND2_X1_LVT i_0_354 (.A1(n_0_728), .A2(n_0_361), .ZN(n_0_335)); + AOI22_X1_LVT i_0_355 (.A1(n_0_612), .A2(n_0_498), .B1(n_0_693), .B2(n_0_411), + .ZN(n_0_336)); + OAI21_X1_LVT i_0_353 (.A(n_0_335), .B1(n_0_728), .B2(n_0_336), .ZN(n_0_334)); + AOI22_X1_LVT i_0_352 (.A1(n_0_701), .A2(n_0_353), .B1(op2[0]), .B2(n_0_334), + .ZN(n_0_333)); + OAI221_X1_LVT i_0_334 (.A(n_0_316), .B1(n_0_327), .B2(n_0_325), .C1(n_0_621), + .C2(n_0_333), .ZN(result[18])); + NAND2_X1_LVT i_0_325 (.A1(n_17), .A2(n_0_581), .ZN(n_0_307)); + INV_X1_LVT i_0_765 (.A(op1[17]), .ZN(n_0_732)); + AOI22_X1_LVT i_0_324 (.A1(n_0_732), .A2(n_0_565), .B1(op1[17]), .B2(n_0_566), + .ZN(n_0_306)); + NOR2_X1_LVT i_0_693 (.A1(n_0_732), .A2(op2[17]), .ZN(n_0_660)); + XNOR2_X1_LVT i_10_86 (.A(n_10_67), .B(n_10_68), .ZN(n_49)); + AOI222_X1_LVT i_0_323 (.A1(op2[17]), .A2(n_0_306), .B1(n_0_660), .B2(n_0_569), + .C1(n_49), .C2(n_0_580), .ZN(n_0_305)); + OAI211_X1_LVT i_0_322 (.A(n_0_307), .B(n_0_305), .C1(n_0_732), .C2(n_0_681), + .ZN(n_0_304)); + AOI22_X1_LVT i_0_331 (.A1(op2[3]), .A2(op1[25]), .B1(op1[17]), .B2(n_0_723), + .ZN(n_0_313)); + NOR2_X1_LVT i_0_330 (.A1(op2[4]), .A2(n_0_313), .ZN(n_0_312)); + AOI22_X1_LVT i_0_329 (.A1(n_0_498), .A2(n_0_386), .B1(n_0_693), .B2(n_0_312), + .ZN(n_0_311)); + OAI22_X1_LVT i_0_328 (.A1(op2[1]), .A2(n_0_311), .B1(n_0_728), .B2(n_0_348), + .ZN(n_0_310)); + OR2_X1_LVT i_0_327 (.A1(op2[0]), .A2(n_0_310), .ZN(n_0_309)); + OAI21_X1_LVT i_0_321 (.A(n_0_576), .B1(n_0_701), .B2(n_0_319), .ZN(n_0_303)); + INV_X1_LVT i_0_320 (.A(n_0_303), .ZN(n_0_302)); + AOI21_X1_LVT i_0_319 (.A(n_0_304), .B1(n_0_309), .B2(n_0_302), .ZN(n_0_301)); + INV_X1_LVT i_0_345 (.A(n_0_327), .ZN(n_0_326)); + OAI22_X1_LVT i_0_326 (.A1(n_0_701), .A2(n_0_326), .B1(n_0_469), .B2(n_0_309), + .ZN(n_0_308)); + NOR2_X1_LVT i_0_318 (.A1(op2[2]), .A2(n_0_393), .ZN(n_0_300)); + AOI21_X1_LVT i_0_317 (.A(n_0_300), .B1(n_0_597), .B2(n_0_498), .ZN(n_0_299)); + OAI22_X1_LVT i_0_316 (.A1(n_0_728), .A2(n_0_299), .B1(op2[1]), .B2(n_0_354), + .ZN(n_0_298)); + OAI22_X1_LVT i_0_315 (.A1(op2[0]), .A2(n_0_334), .B1(n_0_701), .B2(n_0_298), + .ZN(n_0_297)); + OAI221_X1_LVT i_0_314 (.A(n_0_301), .B1(n_0_545), .B2(n_0_308), .C1(n_0_621), + .C2(n_0_297), .ZN(result[17])); + XNOR2_X1_LVT i_10_82 (.A(n_10_64), .B(n_10_65), .ZN(n_48)); + AOI22_X1_LVT i_0_301 (.A1(n_48), .A2(n_0_580), .B1(n_16), .B2(n_0_581), + .ZN(n_0_284)); + NAND2_X1_LVT i_0_333 (.A1(n_0_544), .A2(n_0_469), .ZN(n_0_315)); + INV_X1_LVT i_0_332 (.A(n_0_315), .ZN(n_0_314)); + OAI21_X1_LVT i_0_302 (.A(n_0_681), .B1(op2[16]), .B2(n_0_568), .ZN(n_0_285)); + AOI21_X1_LVT i_0_300 (.A(n_0_314), .B1(op1[16]), .B2(n_0_285), .ZN(n_0_283)); + INV_X1_LVT i_0_772 (.A(op1[16]), .ZN(n_0_739)); + OAI221_X1_LVT i_0_303 (.A(op2[16]), .B1(op1[16]), .B2(n_0_564), .C1(n_0_739), + .C2(n_0_567), .ZN(n_0_286)); + NAND3_X1_LVT i_0_299 (.A1(n_0_284), .A2(n_0_283), .A3(n_0_286), .ZN(n_0_282)); + INV_X1_LVT i_0_593 (.A(n_0_562), .ZN(n_0_561)); + OAI22_X1_LVT i_0_307 (.A1(op1[16]), .A2(op2[3]), .B1(op1[24]), .B2(n_0_723), + .ZN(n_0_290)); + NOR2_X1_LVT i_0_306 (.A1(op2[4]), .A2(n_0_290), .ZN(n_0_289)); + AOI22_X1_LVT i_0_305 (.A1(n_0_693), .A2(n_0_289), .B1(op2[2]), .B2(n_0_371), + .ZN(n_0_288)); + OAI22_X1_LVT i_0_304 (.A1(n_0_728), .A2(n_0_330), .B1(op2[1]), .B2(n_0_288), + .ZN(n_0_287)); + AOI221_X1_LVT i_0_298 (.A(n_0_282), .B1(n_0_547), .B2(n_0_310), .C1(n_0_561), + .C2(n_0_287), .ZN(n_0_281)); + INV_X1_LVT i_0_762 (.A(op1[1]), .ZN(n_0_729)); + OAI22_X1_LVT i_0_313 (.A1(n_0_722), .A2(n_0_615), .B1(n_0_729), .B2(n_0_617), + .ZN(n_0_296)); + NAND2_X1_LVT i_0_312 (.A1(op2[2]), .A2(n_0_296), .ZN(n_0_295)); + OAI21_X1_LVT i_0_311 (.A(n_0_295), .B1(op2[2]), .B2(n_0_362), .ZN(n_0_294)); + NAND2_X1_LVT i_0_310 (.A1(op2[1]), .A2(n_0_294), .ZN(n_0_293)); + OAI21_X1_LVT i_0_309 (.A(n_0_293), .B1(op2[1]), .B2(n_0_336), .ZN(n_0_292)); + OAI22_X1_LVT i_0_308 (.A1(op2[0]), .A2(n_0_298), .B1(n_0_701), .B2(n_0_292), + .ZN(n_0_291)); + OAI21_X1_LVT i_0_297 (.A(n_0_281), .B1(n_0_621), .B2(n_0_291), .ZN(result[16])); + OAI221_X1_LVT i_0_286 (.A(op2[15]), .B1(n_0_734), .B2(n_0_567), .C1(op1[15]), + .C2(n_0_564), .ZN(n_0_270)); + AOI21_X1_LVT i_0_288 (.A(n_0_314), .B1(n_15), .B2(n_0_581), .ZN(n_0_272)); + INV_X1_LVT i_0_287 (.A(n_0_272), .ZN(n_0_271)); + XNOR2_X1_LVT i_10_78 (.A(n_10_61), .B(n_10_62), .ZN(n_47)); + OAI21_X1_LVT i_0_285 (.A(n_0_681), .B1(op2[15]), .B2(n_0_568), .ZN(n_0_269)); + AOI221_X1_LVT i_0_284 (.A(n_0_271), .B1(n_47), .B2(n_0_580), .C1(op1[15]), + .C2(n_0_269), .ZN(n_0_268)); + AOI22_X1_LVT i_0_296 (.A1(op1[8]), .A2(n_0_616), .B1(op1[0]), .B2(n_0_618), + .ZN(n_0_280)); + AOI22_X1_LVT i_0_295 (.A1(op2[2]), .A2(n_0_280), .B1(n_0_693), .B2(n_0_356), + .ZN(n_0_279)); + NAND2_X1_LVT i_0_294 (.A1(op2[1]), .A2(n_0_279), .ZN(n_0_278)); + OAI21_X1_LVT i_0_293 (.A(n_0_278), .B1(op2[1]), .B2(n_0_299), .ZN(n_0_277)); + OAI221_X1_LVT i_0_292 (.A(n_0_620), .B1(n_0_701), .B2(n_0_277), .C1(op2[0]), + .C2(n_0_292), .ZN(n_0_276)); + OAI222_X1_LVT i_0_291 (.A1(n_0_719), .A2(n_0_617), .B1(n_0_691), .B2(n_0_605), + .C1(n_0_734), .C2(n_0_615), .ZN(n_0_275)); + OAI22_X1_LVT i_0_290 (.A1(n_0_693), .A2(n_0_349), .B1(op2[2]), .B2(n_0_275), + .ZN(n_0_274)); + OAI22_X1_LVT i_0_289 (.A1(op2[1]), .A2(n_0_274), .B1(n_0_728), .B2(n_0_311), + .ZN(n_0_273)); + AOI22_X1_LVT i_0_283 (.A1(n_0_561), .A2(n_0_273), .B1(n_0_547), .B2(n_0_287), + .ZN(n_0_267)); + NAND4_X1_LVT i_0_282 (.A1(n_0_270), .A2(n_0_268), .A3(n_0_276), .A4(n_0_267), + .ZN(result[15])); + NOR2_X1_LVT i_0_278 (.A1(op2[0]), .A2(n_0_277), .ZN(n_0_263)); + NAND2_X1_LVT i_0_281 (.A1(n_0_612), .A2(n_0_575), .ZN(n_0_266)); + OAI21_X1_LVT i_0_280 (.A(n_0_266), .B1(n_0_713), .B2(n_0_497), .ZN(n_0_265)); + AOI22_X1_LVT i_0_279 (.A1(op2[1]), .A2(n_0_265), .B1(n_0_728), .B2(n_0_294), + .ZN(n_0_264)); + AOI211_X1_LVT i_0_277 (.A(n_0_263), .B(n_0_621), .C1(op2[0]), .C2(n_0_264), + .ZN(n_0_262)); + INV_X1_LVT i_0_754 (.A(op1[14]), .ZN(n_0_721)); + OAI21_X1_LVT i_0_273 (.A(op2[14]), .B1(n_0_721), .B2(n_0_567), .ZN(n_0_258)); + AOI21_X1_LVT i_0_272 (.A(n_0_258), .B1(n_0_721), .B2(n_0_565), .ZN(n_0_257)); + XNOR2_X1_LVT i_10_74 (.A(n_10_58), .B(n_10_59), .ZN(n_46)); + OAI21_X1_LVT i_0_276 (.A(n_0_681), .B1(op2[14]), .B2(n_0_568), .ZN(n_0_261)); + AOI222_X1_LVT i_0_275 (.A1(n_14), .A2(n_0_581), .B1(n_46), .B2(n_0_580), + .C1(op1[14]), .C2(n_0_261), .ZN(n_0_260)); + INV_X1_LVT i_0_274 (.A(n_0_260), .ZN(n_0_259)); + OAI222_X1_LVT i_0_271 (.A1(n_0_717), .A2(n_0_605), .B1(n_0_687), .B2(n_0_617), + .C1(n_0_721), .C2(n_0_615), .ZN(n_0_256)); + OAI22_X1_LVT i_0_270 (.A1(n_0_693), .A2(n_0_331), .B1(op2[2]), .B2(n_0_256), + .ZN(n_0_255)); + AND2_X1_LVT i_0_269 (.A1(n_0_728), .A2(n_0_255), .ZN(n_0_254)); + NOR3_X1_LVT i_0_265 (.A1(op2[3]), .A2(op2[2]), .A3(op2[0]), .ZN(n_0_250)); + AOI21_X1_LVT i_0_268 (.A(n_0_254), .B1(op2[1]), .B2(n_0_288), .ZN(n_0_253)); + OAI22_X1_LVT i_0_266 (.A1(op2[0]), .A2(n_0_253), .B1(n_0_701), .B2(n_0_273), + .ZN(n_0_251)); + AOI221_X1_LVT i_0_259 (.A(n_0_579), .B1(n_0_254), .B2(n_0_250), .C1(n_0_315), + .C2(n_0_251), .ZN(n_0_244)); + OR4_X1_LVT i_0_258 (.A1(n_0_262), .A2(n_0_257), .A3(n_0_259), .A4(n_0_244), + .ZN(result[14])); + OAI221_X1_LVT i_0_245 (.A(op2[13]), .B1(op1[13]), .B2(n_0_564), .C1(n_0_714), + .C2(n_0_567), .ZN(n_0_231)); + NAND2_X1_LVT i_0_244 (.A1(n_13), .A2(n_0_581), .ZN(n_0_230)); + OAI211_X1_LVT i_0_243 (.A(n_0_231), .B(n_0_230), .C1(n_0_714), .C2(n_0_681), + .ZN(n_0_229)); + XNOR2_X1_LVT i_10_70 (.A(n_10_55), .B(n_10_56), .ZN(n_45)); + NOR2_X1_LVT i_0_695 (.A1(op2[13]), .A2(n_0_714), .ZN(n_0_662)); + AOI221_X1_LVT i_0_242 (.A(n_0_229), .B1(n_45), .B2(n_0_580), .C1(n_0_662), + .C2(n_0_569), .ZN(n_0_228)); + INV_X1_LVT i_0_267 (.A(n_0_253), .ZN(n_0_252)); + OAI222_X1_LVT i_0_257 (.A1(n_0_714), .A2(n_0_615), .B1(n_0_726), .B2(n_0_617), + .C1(n_0_710), .C2(n_0_605), .ZN(n_0_243)); + OAI22_X1_LVT i_0_256 (.A1(n_0_693), .A2(n_0_312), .B1(op2[2]), .B2(n_0_243), + .ZN(n_0_242)); + NAND2_X1_LVT i_0_255 (.A1(n_0_728), .A2(n_0_242), .ZN(n_0_241)); + NAND2_X1_LVT i_0_254 (.A1(op2[1]), .A2(n_0_274), .ZN(n_0_240)); + NAND2_X1_LVT i_0_241 (.A1(n_0_241), .A2(n_0_240), .ZN(n_0_227)); + OAI221_X1_LVT i_0_240 (.A(n_0_228), .B1(n_0_548), .B2(n_0_252), .C1(n_0_562), + .C2(n_0_227), .ZN(n_0_226)); + NAND2_X1_LVT i_0_249 (.A1(n_0_728), .A2(n_0_279), .ZN(n_0_235)); + AOI22_X1_LVT i_0_250 (.A1(n_0_597), .A2(n_0_575), .B1(op1[6]), .B2(n_0_496), + .ZN(n_0_236)); + OAI21_X1_LVT i_0_248 (.A(n_0_235), .B1(n_0_728), .B2(n_0_236), .ZN(n_0_234)); + INV_X1_LVT i_0_247 (.A(n_0_234), .ZN(n_0_233)); + AOI221_X1_LVT i_0_246 (.A(n_0_621), .B1(op2[0]), .B2(n_0_233), .C1(n_0_701), + .C2(n_0_264), .ZN(n_0_232)); + NAND2_X1_LVT i_0_264 (.A1(op2[3]), .A2(n_0_469), .ZN(n_0_249)); + AOI21_X1_LVT i_0_262 (.A(n_0_468), .B1(n_0_693), .B2(n_0_249), .ZN(n_0_247)); + INV_X1_LVT i_0_261 (.A(n_0_247), .ZN(n_0_246)); + OAI211_X1_LVT i_0_260 (.A(n_0_252), .B(n_0_246), .C1(n_0_468), .C2(n_0_254), + .ZN(n_0_245)); + OAI221_X1_LVT i_0_253 (.A(n_0_544), .B1(n_0_247), .B2(n_0_241), .C1(n_0_469), + .C2(n_0_240), .ZN(n_0_239)); + INV_X1_LVT i_0_252 (.A(n_0_239), .ZN(n_0_238)); + AOI211_X1_LVT i_0_239 (.A(n_0_226), .B(n_0_232), .C1(n_0_245), .C2(n_0_238), + .ZN(n_0_225)); + INV_X1_LVT i_0_238 (.A(n_0_225), .ZN(result[13])); + OAI221_X1_LVT i_0_232 (.A(op2[12]), .B1(n_0_696), .B2(n_0_567), .C1(op1[12]), + .C2(n_0_564), .ZN(n_0_219)); + OAI21_X1_LVT i_0_231 (.A(n_0_681), .B1(op2[12]), .B2(n_0_568), .ZN(n_0_218)); + XNOR2_X1_LVT i_10_66 (.A(n_10_52), .B(n_10_53), .ZN(n_44)); + AOI222_X1_LVT i_0_230 (.A1(n_12), .A2(n_0_581), .B1(op1[12]), .B2(n_0_218), + .C1(n_44), .C2(n_0_580), .ZN(n_0_217)); + OAI21_X1_LVT i_0_234 (.A(n_0_620), .B1(op2[1]), .B2(n_0_265), .ZN(n_0_221)); + INV_X1_LVT i_0_763 (.A(op1[5]), .ZN(n_0_730)); + OAI21_X1_LVT i_0_236 (.A(op2[2]), .B1(n_0_730), .B2(n_0_615), .ZN(n_0_223)); + OAI21_X1_LVT i_0_235 (.A(n_0_223), .B1(op2[2]), .B2(n_0_296), .ZN(n_0_222)); + AOI21_X1_LVT i_0_233 (.A(n_0_221), .B1(op2[1]), .B2(n_0_222), .ZN(n_0_220)); + NOR2_X1_LVT i_0_237 (.A1(n_0_577), .A2(n_0_227), .ZN(n_0_224)); + NOR4_X1_LVT i_0_223 (.A1(n_0_701), .A2(n_0_220), .A3(n_0_224), .A4(n_0_238), + .ZN(n_0_210)); + NAND2_X1_LVT i_0_224 (.A1(n_0_544), .A2(n_0_247), .ZN(n_0_211)); + NAND2_X1_LVT i_0_222 (.A1(n_0_701), .A2(n_0_211), .ZN(n_0_209)); + OAI22_X1_LVT i_0_229 (.A1(op2[4]), .A2(n_0_696), .B1(n_0_738), .B2(n_0_698), + .ZN(n_0_216)); + INV_X1_LVT i_0_228 (.A(n_0_216), .ZN(n_0_215)); + OAI22_X1_LVT i_0_227 (.A1(n_0_727), .A2(n_0_617), .B1(op2[3]), .B2(n_0_215), + .ZN(n_0_214)); + OAI22_X1_LVT i_0_226 (.A1(n_0_693), .A2(n_0_289), .B1(op2[2]), .B2(n_0_214), + .ZN(n_0_213)); + OAI22_X1_LVT i_0_225 (.A1(op2[1]), .A2(n_0_213), .B1(n_0_728), .B2(n_0_255), + .ZN(n_0_212)); + AOI221_X1_LVT i_0_221 (.A(n_0_209), .B1(n_0_578), .B2(n_0_212), .C1(n_0_620), + .C2(n_0_234), .ZN(n_0_208)); + OAI211_X1_LVT i_0_220 (.A(n_0_219), .B(n_0_217), .C1(n_0_210), .C2(n_0_208), + .ZN(result[12])); + OAI21_X1_LVT i_0_209 (.A(n_0_681), .B1(op2[11]), .B2(n_0_568), .ZN(n_0_197)); + AOI22_X1_LVT i_0_208 (.A1(n_11), .A2(n_0_581), .B1(op1[11]), .B2(n_0_197), + .ZN(n_0_196)); + NAND2_X1_LVT i_0_207 (.A1(n_0_211), .A2(n_0_196), .ZN(n_0_195)); + AOI22_X1_LVT i_0_210 (.A1(op1[11]), .A2(n_0_566), .B1(n_0_706), .B2(n_0_565), + .ZN(n_0_198)); + XNOR2_X1_LVT i_10_62 (.A(n_10_49), .B(n_10_50), .ZN(n_43)); + AOI221_X1_LVT i_0_206 (.A(n_0_195), .B1(op2[11]), .B2(n_0_198), .C1(n_43), + .C2(n_0_580), .ZN(n_0_194)); + AOI221_X1_LVT i_0_215 (.A(op2[3]), .B1(n_0_738), .B2(n_0_706), .C1(op2[4]), + .C2(n_0_688), .ZN(n_0_203)); + AOI21_X1_LVT i_0_214 (.A(n_0_203), .B1(op1[19]), .B2(n_0_618), .ZN(n_0_202)); + NAND2_X1_LVT i_0_213 (.A1(n_0_693), .A2(n_0_202), .ZN(n_0_201)); + OAI21_X1_LVT i_0_212 (.A(n_0_201), .B1(n_0_693), .B2(n_0_275), .ZN(n_0_200)); + OAI22_X1_LVT i_0_211 (.A1(n_0_728), .A2(n_0_242), .B1(op2[1]), .B2(n_0_200), + .ZN(n_0_199)); + AOI22_X1_LVT i_0_205 (.A1(n_0_561), .A2(n_0_199), .B1(n_0_701), .B2(n_0_220), + .ZN(n_0_193)); + NOR2_X1_LVT i_0_219 (.A1(op2[2]), .A2(n_0_280), .ZN(n_0_207)); + AOI21_X1_LVT i_0_218 (.A(n_0_207), .B1(op1[4]), .B2(n_0_496), .ZN(n_0_206)); + AOI22_X1_LVT i_0_217 (.A1(n_0_728), .A2(n_0_236), .B1(op2[1]), .B2(n_0_206), + .ZN(n_0_205)); + AOI22_X1_LVT i_0_216 (.A1(n_0_578), .A2(n_0_212), .B1(n_0_620), .B2(n_0_205), + .ZN(n_0_204)); + OAI211_X1_LVT i_0_204 (.A(n_0_194), .B(n_0_193), .C1(n_0_701), .C2(n_0_204), + .ZN(result[11])); + AOI22_X1_LVT i_0_194 (.A1(n_0_654), .A2(n_0_498), .B1(op1[7]), .B2(n_0_573), + .ZN(n_0_183)); + OAI22_X1_LVT i_0_193 (.A1(n_0_728), .A2(n_0_183), .B1(op2[1]), .B2(n_0_222), + .ZN(n_0_182)); + AOI22_X1_LVT i_0_192 (.A1(op2[0]), .A2(n_0_182), .B1(n_0_701), .B2(n_0_205), + .ZN(n_0_181)); + NOR2_X1_LVT i_0_191 (.A1(n_0_621), .A2(n_0_181), .ZN(n_0_180)); + AOI22_X1_LVT i_0_190 (.A1(op1[10]), .A2(n_0_566), .B1(n_0_733), .B2(n_0_565), + .ZN(n_0_179)); + XNOR2_X1_LVT i_10_58 (.A(n_10_46), .B(n_10_47), .ZN(n_42)); + AOI22_X1_LVT i_0_188 (.A1(op2[10]), .A2(n_0_179), .B1(n_42), .B2(n_0_580), + .ZN(n_0_177)); + OAI21_X1_LVT i_0_189 (.A(n_0_681), .B1(op2[10]), .B2(n_0_568), .ZN(n_0_178)); + AOI22_X1_LVT i_0_187 (.A1(n_10), .A2(n_0_581), .B1(op1[10]), .B2(n_0_178), + .ZN(n_0_176)); + NAND2_X1_LVT i_0_186 (.A1(n_0_177), .A2(n_0_176), .ZN(n_0_175)); + NOR2_X1_LVT i_0_203 (.A1(n_0_701), .A2(n_0_199), .ZN(n_0_192)); + NOR2_X1_LVT i_0_200 (.A1(n_0_693), .A2(n_0_256), .ZN(n_0_189)); + AOI221_X1_LVT i_0_202 (.A(n_0_596), .B1(op1[10]), .B2(n_0_616), .C1(op1[26]), + .C2(n_0_606), .ZN(n_0_191)); + AOI21_X1_LVT i_0_199 (.A(n_0_189), .B1(n_0_693), .B2(n_0_191), .ZN(n_0_188)); + OR2_X1_LVT i_0_198 (.A1(op2[1]), .A2(n_0_188), .ZN(n_0_187)); + NAND2_X1_LVT i_0_197 (.A1(op2[1]), .A2(n_0_213), .ZN(n_0_186)); + NAND2_X1_LVT i_0_185 (.A1(n_0_187), .A2(n_0_186), .ZN(n_0_174)); + AOI211_X1_LVT i_0_184 (.A(n_0_577), .B(n_0_192), .C1(n_0_701), .C2(n_0_174), + .ZN(n_0_173)); + INV_X1_LVT i_0_263 (.A(n_0_249), .ZN(n_0_248)); + OAI22_X1_LVT i_0_196 (.A1(n_0_248), .A2(n_0_187), .B1(n_0_247), .B2(n_0_186), + .ZN(n_0_185)); + AOI221_X1_LVT i_0_195 (.A(n_0_545), .B1(n_0_246), .B2(n_0_192), .C1(n_0_701), + .C2(n_0_185), .ZN(n_0_184)); + OR4_X1_LVT i_0_183 (.A1(n_0_180), .A2(n_0_175), .A3(n_0_173), .A4(n_0_184), + .ZN(result[10])); + INV_X1_LVT i_0_753 (.A(op2[9]), .ZN(n_0_720)); + AOI221_X1_LVT i_0_171 (.A(n_0_720), .B1(op1[9]), .B2(n_0_566), .C1(n_0_722), + .C2(n_0_565), .ZN(n_0_161)); + XNOR2_X1_LVT i_10_54 (.A(n_10_43), .B(n_10_44), .ZN(n_41)); + AOI22_X1_LVT i_0_172 (.A1(n_9), .A2(n_0_581), .B1(n_41), .B2(n_0_580), + .ZN(n_0_162)); + AOI21_X1_LVT i_0_170 (.A(aluBypass), .B1(n_0_720), .B2(n_0_569), .ZN(n_0_160)); + OAI21_X1_LVT i_0_169 (.A(n_0_162), .B1(n_0_722), .B2(n_0_160), .ZN(n_0_159)); + OAI222_X1_LVT i_0_182 (.A1(n_0_722), .A2(n_0_615), .B1(n_0_699), .B2(n_0_605), + .C1(n_0_732), .C2(n_0_617), .ZN(n_0_172)); + AOI22_X1_LVT i_0_181 (.A1(n_0_693), .A2(n_0_172), .B1(op2[2]), .B2(n_0_243), + .ZN(n_0_171)); + NAND2_X1_LVT i_0_180 (.A1(n_0_728), .A2(n_0_171), .ZN(n_0_170)); + NAND2_X1_LVT i_0_179 (.A1(op2[1]), .A2(n_0_200), .ZN(n_0_169)); + OAI22_X1_LVT i_0_178 (.A1(n_0_248), .A2(n_0_170), .B1(n_0_247), .B2(n_0_169), + .ZN(n_0_168)); + NOR3_X1_LVT i_0_177 (.A1(n_0_545), .A2(n_0_168), .A3(n_0_185), .ZN(n_0_167)); + NOR2_X1_LVT i_0_251 (.A1(n_0_704), .A2(n_0_615), .ZN(n_0_237)); + OAI22_X1_LVT i_0_176 (.A1(op1[2]), .A2(n_0_693), .B1(n_0_496), .B2(n_0_237), + .ZN(n_0_166)); + OAI22_X1_LVT i_0_175 (.A1(op2[1]), .A2(n_0_206), .B1(n_0_728), .B2(n_0_166), + .ZN(n_0_165)); + OAI221_X1_LVT i_0_174 (.A(n_0_620), .B1(op2[0]), .B2(n_0_182), .C1(n_0_701), + .C2(n_0_165), .ZN(n_0_164)); + NAND2_X1_LVT i_0_173 (.A1(n_0_170), .A2(n_0_169), .ZN(n_0_163)); + OAI221_X1_LVT i_0_168 (.A(n_0_164), .B1(n_0_562), .B2(n_0_163), .C1(n_0_548), + .C2(n_0_174), .ZN(n_0_158)); + OR4_X1_LVT i_0_167 (.A1(n_0_161), .A2(n_0_159), .A3(n_0_167), .A4(n_0_158), + .ZN(result[9])); + OAI21_X1_LVT i_0_160 (.A(n_0_693), .B1(n_0_730), .B2(n_0_615), .ZN(n_0_151)); + OAI21_X1_LVT i_0_159 (.A(op2[2]), .B1(n_0_729), .B2(n_0_615), .ZN(n_0_150)); + AND2_X1_LVT i_0_158 (.A1(n_0_151), .A2(n_0_150), .ZN(n_0_149)); + NAND2_X1_LVT i_0_157 (.A1(op2[1]), .A2(n_0_149), .ZN(n_0_148)); + OAI21_X1_LVT i_0_156 (.A(n_0_148), .B1(op2[1]), .B2(n_0_183), .ZN(n_0_147)); + OAI22_X1_LVT i_0_155 (.A1(op2[0]), .A2(n_0_165), .B1(n_0_701), .B2(n_0_147), + .ZN(n_0_146)); + NOR2_X1_LVT i_0_154 (.A1(n_0_621), .A2(n_0_146), .ZN(n_0_145)); + INV_X1_LVT i_0_773 (.A(op1[8]), .ZN(n_0_740)); + NOR2_X1_LVT i_0_688 (.A1(n_0_740), .A2(op2[8]), .ZN(n_0_655)); + AOI22_X1_LVT i_0_153 (.A1(op1[8]), .A2(aluBypass), .B1(n_0_655), .B2(n_0_569), + .ZN(n_0_144)); + OAI221_X1_LVT i_0_152 (.A(op2[8]), .B1(op1[8]), .B2(n_0_564), .C1(n_0_740), + .C2(n_0_567), .ZN(n_0_143)); + XNOR2_X1_LVT i_10_51 (.A(n_10_39), .B(n_10_42), .ZN(n_40)); + AOI22_X1_LVT i_0_151 (.A1(n_40), .A2(n_0_580), .B1(n_8), .B2(n_0_581), + .ZN(n_0_142)); + NAND3_X1_LVT i_0_150 (.A1(n_0_144), .A2(n_0_143), .A3(n_0_142), .ZN(n_0_141)); + OAI222_X1_LVT i_0_166 (.A1(n_0_740), .A2(n_0_615), .B1(n_0_739), .B2(n_0_617), + .C1(n_0_736), .C2(n_0_605), .ZN(n_0_157)); + OAI22_X1_LVT i_0_165 (.A1(op2[2]), .A2(n_0_157), .B1(n_0_693), .B2(n_0_214), + .ZN(n_0_156)); + NOR2_X1_LVT i_0_164 (.A1(op2[1]), .A2(n_0_156), .ZN(n_0_155)); + AOI21_X1_LVT i_0_163 (.A(n_0_155), .B1(op2[1]), .B2(n_0_188), .ZN(n_0_154)); + AND2_X1_LVT i_0_162 (.A1(n_0_701), .A2(n_0_154), .ZN(n_0_153)); + AOI211_X1_LVT i_0_149 (.A(n_0_577), .B(n_0_153), .C1(op2[0]), .C2(n_0_163), + .ZN(n_0_140)); + AOI221_X1_LVT i_0_161 (.A(n_0_545), .B1(op2[0]), .B2(n_0_168), .C1(n_0_249), + .C2(n_0_153), .ZN(n_0_152)); + OR4_X1_LVT i_0_148 (.A1(n_0_145), .A2(n_0_141), .A3(n_0_140), .A4(n_0_152), + .ZN(result[8])); + AOI22_X1_LVT i_0_138 (.A1(op1[4]), .A2(n_0_573), .B1(op1[0]), .B2(n_0_496), + .ZN(n_0_130)); + AOI22_X1_LVT i_0_137 (.A1(op2[1]), .A2(n_0_130), .B1(n_0_728), .B2(n_0_166), + .ZN(n_0_129)); + OAI22_X1_LVT i_0_136 (.A1(n_0_701), .A2(n_0_129), .B1(op2[0]), .B2(n_0_147), + .ZN(n_0_128)); + NOR2_X1_LVT i_0_135 (.A1(n_0_621), .A2(n_0_128), .ZN(n_0_127)); + OAI221_X1_LVT i_0_139 (.A(op2[7]), .B1(n_0_713), .B2(n_0_567), .C1(op1[7]), + .C2(n_0_564), .ZN(n_0_131)); + INV_X1_LVT i_10_44 (.A(n_10_36), .ZN(n_10_37)); + NOR2_X1_LVT i_10_45 (.A1(n_10_35), .A2(n_10_37), .ZN(n_10_38)); + XNOR2_X1_LVT i_10_46 (.A(n_10_33), .B(n_10_38), .ZN(n_39)); + AOI22_X1_LVT i_0_141 (.A1(n_7), .A2(n_0_581), .B1(n_39), .B2(n_0_580), + .ZN(n_0_133)); + INV_X1_LVT i_0_745 (.A(op2[7]), .ZN(n_0_712)); + AOI21_X1_LVT i_0_140 (.A(aluBypass), .B1(n_0_712), .B2(n_0_569), .ZN(n_0_132)); + OAI211_X1_LVT i_0_133 (.A(n_0_131), .B(n_0_133), .C1(n_0_713), .C2(n_0_132), + .ZN(n_0_125)); + OAI22_X1_LVT i_0_147 (.A1(n_0_734), .A2(n_0_617), .B1(n_0_713), .B2(n_0_615), + .ZN(n_0_139)); + AOI211_X1_LVT i_0_146 (.A(n_0_139), .B(n_0_248), .C1(op1[23]), .C2(n_0_606), + .ZN(n_0_138)); + OAI22_X1_LVT i_0_145 (.A1(n_0_693), .A2(n_0_202), .B1(op2[2]), .B2(n_0_138), + .ZN(n_0_137)); + NOR2_X1_LVT i_0_144 (.A1(op2[1]), .A2(n_0_137), .ZN(n_0_136)); + AOI21_X1_LVT i_0_143 (.A(n_0_136), .B1(op2[1]), .B2(n_0_171), .ZN(n_0_135)); + NAND2_X1_LVT i_0_142 (.A1(n_0_561), .A2(n_0_135), .ZN(n_0_134)); + OAI221_X1_LVT i_0_134 (.A(n_0_134), .B1(n_0_548), .B2(n_0_154), .C1(n_0_545), + .C2(n_0_249), .ZN(n_0_126)); + OR3_X1_LVT i_0_132 (.A1(n_0_127), .A2(n_0_125), .A3(n_0_126), .ZN(result[7])); + NAND2_X1_LVT i_0_124 (.A1(n_0_728), .A2(n_0_149), .ZN(n_0_117)); + OAI21_X1_LVT i_0_123 (.A(n_0_117), .B1(n_0_724), .B2(n_0_531), .ZN(n_0_116)); + OAI22_X1_LVT i_0_122 (.A1(n_0_701), .A2(n_0_116), .B1(op2[0]), .B2(n_0_129), + .ZN(n_0_115)); + NOR2_X1_LVT i_0_121 (.A1(n_0_621), .A2(n_0_115), .ZN(n_0_114)); + XNOR2_X1_LVT i_10_38 (.A(n_10_30), .B(n_10_31), .ZN(n_38)); + AOI22_X1_LVT i_0_119 (.A1(n_6), .A2(n_0_581), .B1(n_38), .B2(n_0_580), + .ZN(n_0_112)); + INV_X1_LVT i_0_735 (.A(op2[6]), .ZN(n_0_702)); + AOI21_X1_LVT i_0_120 (.A(aluBypass), .B1(n_0_702), .B2(n_0_569), .ZN(n_0_113)); + OAI21_X1_LVT i_0_118 (.A(n_0_112), .B1(n_0_704), .B2(n_0_113), .ZN(n_0_111)); + AOI221_X1_LVT i_0_117 (.A(n_0_702), .B1(n_0_704), .B2(n_0_565), .C1(op1[6]), + .C2(n_0_566), .ZN(n_0_110)); + NOR3_X1_LVT i_0_116 (.A1(n_0_114), .A2(n_0_111), .A3(n_0_110), .ZN(n_0_109)); + AOI221_X1_LVT i_0_131 (.A(n_0_237), .B1(op1[14]), .B2(n_0_618), .C1(op2[4]), + .C2(n_0_406), .ZN(n_0_124)); + NAND2_X1_LVT i_0_130 (.A1(n_0_693), .A2(n_0_124), .ZN(n_0_123)); + INV_X1_LVT i_0_201 (.A(n_0_191), .ZN(n_0_190)); + OAI21_X1_LVT i_0_129 (.A(n_0_123), .B1(n_0_693), .B2(n_0_190), .ZN(n_0_122)); + AOI22_X1_LVT i_0_128 (.A1(n_0_728), .A2(n_0_122), .B1(op2[1]), .B2(n_0_156), + .ZN(n_0_121)); + INV_X1_LVT i_0_127 (.A(n_0_121), .ZN(n_0_120)); + OAI21_X1_LVT i_0_126 (.A(n_0_248), .B1(op2[1]), .B2(n_0_123), .ZN(n_0_119)); + AND2_X1_LVT i_0_125 (.A1(n_0_120), .A2(n_0_119), .ZN(n_0_118)); + NOR2_X1_LVT i_0_115 (.A1(n_0_545), .A2(n_0_118), .ZN(n_0_108)); + AOI21_X1_LVT i_0_114 (.A(n_0_108), .B1(n_0_576), .B2(n_0_121), .ZN(n_0_107)); + AOI22_X1_LVT i_0_113 (.A1(n_0_544), .A2(n_0_248), .B1(n_0_578), .B2(n_0_135), + .ZN(n_0_106)); + OAI221_X1_LVT i_0_112 (.A(n_0_109), .B1(op2[0]), .B2(n_0_107), .C1(n_0_701), + .C2(n_0_106), .ZN(result[6])); + OAI221_X1_LVT i_0_100 (.A(op2[5]), .B1(op1[5]), .B2(n_0_564), .C1(n_0_730), + .C2(n_0_567), .ZN(n_0_94)); + INV_X1_LVT i_0_764 (.A(op2[5]), .ZN(n_0_731)); + AOI21_X1_LVT i_0_99 (.A(aluBypass), .B1(n_0_731), .B2(n_0_569), .ZN(n_0_93)); + NOR2_X1_LVT i_0_98 (.A1(n_0_730), .A2(n_0_93), .ZN(n_0_92)); + XNOR2_X1_LVT i_10_35 (.A(n_10_26), .B(n_10_29), .ZN(n_37)); + AOI221_X1_LVT i_0_97 (.A(n_0_92), .B1(n_37), .B2(n_0_580), .C1(n_5), .C2( + n_0_581), .ZN(n_0_91)); + OAI22_X1_LVT i_0_102 (.A1(n_0_694), .A2(n_0_531), .B1(op2[1]), .B2(n_0_130), + .ZN(n_0_96)); + OAI221_X1_LVT i_0_101 (.A(n_0_620), .B1(n_0_701), .B2(n_0_96), .C1(op2[0]), + .C2(n_0_116), .ZN(n_0_95)); + NAND3_X1_LVT i_0_111 (.A1(n_0_544), .A2(n_0_248), .A3(op2[2]), .ZN(n_0_105)); + NAND2_X1_LVT i_0_110 (.A1(op2[4]), .A2(n_0_386), .ZN(n_0_104)); + OAI21_X1_LVT i_0_109 (.A(n_0_104), .B1(n_0_714), .B2(n_0_617), .ZN(n_0_103)); + OAI22_X1_LVT i_0_108 (.A1(n_0_151), .A2(n_0_103), .B1(n_0_693), .B2(n_0_172), + .ZN(n_0_102)); + NOR2_X1_LVT i_0_107 (.A1(op2[1]), .A2(n_0_102), .ZN(n_0_101)); + AOI21_X1_LVT i_0_106 (.A(n_0_101), .B1(op2[1]), .B2(n_0_137), .ZN(n_0_100)); + OAI21_X1_LVT i_0_105 (.A(n_0_105), .B1(n_0_579), .B2(n_0_100), .ZN(n_0_99)); + AOI21_X1_LVT i_0_104 (.A(n_0_118), .B1(n_0_682), .B2(n_0_120), .ZN(n_0_98)); + OAI22_X1_LVT i_0_103 (.A1(n_0_547), .A2(n_0_99), .B1(n_0_701), .B2(n_0_98), + .ZN(n_0_97)); + NAND4_X1_LVT i_0_96 (.A1(n_0_94), .A2(n_0_91), .A3(n_0_95), .A4(n_0_97), + .ZN(result[5])); + INV_X1_LVT i_10_26 (.A(n_10_21), .ZN(n_10_22)); + NOR2_X1_LVT i_10_28 (.A1(n_10_22), .A2(n_10_23), .ZN(n_10_24)); + XNOR2_X1_LVT i_10_29 (.A(n_10_19), .B(n_10_24), .ZN(n_36)); + AOI222_X1_LVT i_0_89 (.A1(n_4), .A2(n_0_581), .B1(n_36), .B2(n_0_580), + .C1(n_0_668), .C2(n_0_564), .ZN(n_0_84)); + INV_X1_LVT i_0_770 (.A(op1[4]), .ZN(n_0_737)); + AOI221_X1_LVT i_0_90 (.A(aluBypass), .B1(op2[4]), .B2(n_0_567), .C1(n_0_738), + .C2(n_0_569), .ZN(n_0_85)); + OAI21_X1_LVT i_0_88 (.A(n_0_84), .B1(n_0_737), .B2(n_0_85), .ZN(n_0_83)); + NOR2_X1_LVT i_0_689 (.A1(op2[4]), .A2(n_0_737), .ZN(n_0_656)); + AOI21_X1_LVT i_0_95 (.A(n_0_616), .B1(n_0_727), .B2(n_0_723), .ZN(n_0_90)); + OAI22_X1_LVT i_0_94 (.A1(n_0_723), .A2(n_0_216), .B1(n_0_656), .B2(n_0_90), + .ZN(n_0_89)); + INV_X1_LVT i_0_93 (.A(n_0_89), .ZN(n_0_88)); + OAI22_X1_LVT i_0_92 (.A1(op2[2]), .A2(n_0_88), .B1(n_0_693), .B2(n_0_157), + .ZN(n_0_87)); + OAI221_X1_LVT i_0_91 (.A(n_0_105), .B1(n_0_728), .B2(n_0_122), .C1(op2[1]), + .C2(n_0_87), .ZN(n_0_86)); + AOI221_X1_LVT i_0_85 (.A(n_0_83), .B1(n_0_561), .B2(n_0_86), .C1(op2[0]), + .C2(n_0_99), .ZN(n_0_80)); + AOI221_X1_LVT i_0_87 (.A(n_0_574), .B1(n_0_729), .B2(op2[1]), .C1(n_0_728), + .C2(n_0_724), .ZN(n_0_82)); + OAI22_X1_LVT i_0_86 (.A1(op2[0]), .A2(n_0_96), .B1(n_0_701), .B2(n_0_82), + .ZN(n_0_81)); + OAI21_X1_LVT i_0_84 (.A(n_0_80), .B1(n_0_621), .B2(n_0_81), .ZN(result[4])); + AND2_X1_LVT i_0_81 (.A1(op2[1]), .A2(n_0_105), .ZN(n_0_77)); + NAND2_X1_LVT i_0_80 (.A1(n_0_102), .A2(n_0_77), .ZN(n_0_76)); + OAI221_X1_LVT i_0_83 (.A(n_0_693), .B1(n_0_654), .B2(n_0_484), .C1(n_0_738), + .C2(n_0_350), .ZN(n_0_79)); + OAI21_X1_LVT i_0_82 (.A(n_0_79), .B1(n_0_693), .B2(n_0_138), .ZN(n_0_78)); + OAI21_X1_LVT i_0_79 (.A(n_0_76), .B1(op2[1]), .B2(n_0_78), .ZN(n_0_75)); + NOR2_X1_LVT i_0_78 (.A1(n_0_562), .A2(n_0_75), .ZN(n_0_74)); + NAND2_X1_LVT i_10_20 (.A1(n_10_15), .A2(n_10_16), .ZN(n_10_17)); + XNOR2_X1_LVT i_10_21 (.A(n_10_13), .B(n_10_17), .ZN(n_35)); + AOI22_X1_LVT i_0_75 (.A1(n_35), .A2(n_0_580), .B1(n_3), .B2(n_0_581), + .ZN(n_0_71)); + OAI21_X1_LVT i_0_74 (.A(n_0_681), .B1(n_0_723), .B2(n_0_566), .ZN(n_0_70)); + AOI222_X1_LVT i_0_73 (.A1(n_0_654), .A2(n_0_569), .B1(n_0_663), .B2(n_0_564), + .C1(op1[3]), .C2(n_0_70), .ZN(n_0_69)); + INV_X1_LVT i_0_736 (.A(op1[0]), .ZN(n_0_703)); + OAI22_X1_LVT i_0_77 (.A1(n_0_703), .A2(n_0_531), .B1(n_0_694), .B2(n_0_572), + .ZN(n_0_73)); + OAI22_X1_LVT i_0_76 (.A1(n_0_701), .A2(n_0_73), .B1(op2[0]), .B2(n_0_82), + .ZN(n_0_72)); + OAI211_X1_LVT i_0_72 (.A(n_0_71), .B(n_0_69), .C1(n_0_621), .C2(n_0_72), + .ZN(n_0_68)); + AOI211_X1_LVT i_0_71 (.A(n_0_74), .B(n_0_68), .C1(n_0_547), .C2(n_0_86), + .ZN(n_0_67)); + INV_X1_LVT i_0_70 (.A(n_0_67), .ZN(result[3])); + NAND2_X1_LVT i_0_65 (.A1(n_2), .A2(n_0_581), .ZN(n_0_62)); + OAI221_X1_LVT i_0_66 (.A(op2[2]), .B1(op1[2]), .B2(n_0_564), .C1(n_0_694), + .C2(n_0_567), .ZN(n_0_63)); + AOI21_X1_LVT i_0_64 (.A(aluBypass), .B1(n_0_693), .B2(n_0_569), .ZN(n_0_61)); + OAI21_X1_LVT i_0_63 (.A(n_0_63), .B1(n_0_694), .B2(n_0_61), .ZN(n_0_60)); + INV_X1_LVT i_10_13 (.A(n_10_10), .ZN(n_10_11)); + NOR2_X1_LVT i_10_14 (.A1(n_10_9), .A2(n_10_11), .ZN(n_10_12)); + XNOR2_X1_LVT i_10_15 (.A(n_10_7), .B(n_10_12), .ZN(n_34)); + AOI21_X1_LVT i_0_62 (.A(n_0_60), .B1(n_34), .B2(n_0_580), .ZN(n_0_59)); + OAI211_X1_LVT i_0_57 (.A(n_0_62), .B(n_0_59), .C1(n_0_548), .C2(n_0_75), + .ZN(n_0_54)); + NOR2_X1_LVT i_0_698 (.A1(n_0_729), .A2(op2[1]), .ZN(n_0_665)); + INV_X1_LVT i_0_697 (.A(n_0_665), .ZN(n_0_664)); + OAI21_X1_LVT i_0_69 (.A(op2[0]), .B1(n_0_664), .B2(n_0_574), .ZN(n_0_66)); + OAI21_X1_LVT i_0_68 (.A(n_0_620), .B1(op2[0]), .B2(n_0_73), .ZN(n_0_65)); + INV_X1_LVT i_0_67 (.A(n_0_65), .ZN(n_0_64)); + OAI222_X1_LVT i_0_61 (.A1(op1[10]), .A2(n_0_617), .B1(op1[2]), .B2(n_0_615), + .C1(n_0_738), .C2(n_0_332), .ZN(n_0_58)); + OAI22_X1_LVT i_0_60 (.A1(op2[2]), .A2(n_0_58), .B1(n_0_693), .B2(n_0_124), + .ZN(n_0_57)); + INV_X1_LVT i_0_59 (.A(n_0_57), .ZN(n_0_56)); + AOI22_X1_LVT i_0_58 (.A1(n_0_728), .A2(n_0_56), .B1(n_0_87), .B2(n_0_77), + .ZN(n_0_55)); + AOI221_X1_LVT i_0_56 (.A(n_0_54), .B1(n_0_66), .B2(n_0_64), .C1(n_0_561), + .C2(n_0_55), .ZN(n_0_53)); + INV_X1_LVT i_0_55 (.A(n_0_53), .ZN(result[2])); + NAND2_X1_LVT i_0_54 (.A1(n_0_547), .A2(n_0_55), .ZN(n_0_52)); + AOI221_X1_LVT i_0_47 (.A(n_0_728), .B1(n_0_729), .B2(n_0_565), .C1(op1[1]), + .C2(n_0_566), .ZN(n_0_45)); + NOR2_X1_LVT i_0_700 (.A1(op1[0]), .A2(n_0_701), .ZN(n_0_667)); + AOI211_X1_LVT i_0_48 (.A(n_0_667), .B(n_0_621), .C1(n_0_729), .C2(n_0_701), + .ZN(n_0_46)); + AOI221_X1_LVT i_0_44 (.A(n_0_45), .B1(op1[1]), .B2(aluBypass), .C1(n_0_571), + .C2(n_0_46), .ZN(n_0_42)); + NAND2_X1_LVT i_10_6 (.A1(n_10_3), .A2(n_10_4), .ZN(n_10_5)); + XNOR2_X1_LVT i_10_7 (.A(n_10_5), .B(n_10_1), .ZN(n_33)); + AOI22_X1_LVT i_0_49 (.A1(n_33), .A2(n_0_580), .B1(n_1), .B2(n_0_581), + .ZN(n_0_47)); + OAI21_X1_LVT i_0_46 (.A(n_0_47), .B1(n_0_664), .B2(n_0_568), .ZN(n_0_44)); + NAND2_X1_LVT i_0_51 (.A1(op2[1]), .A2(n_0_78), .ZN(n_0_49)); + OAI222_X1_LVT i_0_53 (.A1(n_0_722), .A2(n_0_617), .B1(n_0_729), .B2(n_0_615), + .C1(n_0_738), .C2(n_0_313), .ZN(n_0_51)); + OAI22_X1_LVT i_0_52 (.A1(n_0_223), .A2(n_0_103), .B1(op2[2]), .B2(n_0_51), + .ZN(n_0_50)); + OAI21_X1_LVT i_0_50 (.A(n_0_49), .B1(op2[1]), .B2(n_0_50), .ZN(n_0_48)); + AOI21_X1_LVT i_0_45 (.A(n_0_44), .B1(n_0_561), .B2(n_0_48), .ZN(n_0_43)); + NAND3_X1_LVT i_0_43 (.A1(n_0_52), .A2(n_0_42), .A3(n_0_43), .ZN(result[1])); + OAI222_X1_LVT i_0_11 (.A1(n_0_740), .A2(n_0_617), .B1(n_0_703), .B2(n_0_615), + .C1(n_0_738), .C2(n_0_290), .ZN(n_0_10)); + OAI22_X1_LVT i_0_10 (.A1(op2[2]), .A2(n_0_10), .B1(n_0_693), .B2(n_0_88), + .ZN(n_0_9)); + OAI221_X1_LVT i_0_9 (.A(n_0_701), .B1(n_0_728), .B2(n_0_56), .C1(op2[1]), + .C2(n_0_9), .ZN(n_0_8)); + OAI21_X1_LVT i_0_8 (.A(n_0_8), .B1(n_0_701), .B2(n_0_48), .ZN(n_0_7)); + NOR2_X1_LVT i_0_7 (.A1(n_0_579), .A2(n_0_7), .ZN(n_0_6)); + OAI221_X1_LVT i_0_3 (.A(op2[0]), .B1(op1[0]), .B2(n_0_564), .C1(n_0_703), + .C2(n_0_567), .ZN(n_0_2)); + OAI21_X1_LVT i_10_2 (.A(n_10_1), .B1(n_10_0), .B2(op2[0]), .ZN(n_32)); + AOI22_X1_LVT i_0_2 (.A1(n_32), .A2(n_0_580), .B1(n_0), .B2(n_0_581), .ZN( + n_0_1)); + NAND3_X1_LVT i_0_6 (.A1(n_0_701), .A2(n_0_571), .A3(n_0_620), .ZN(n_0_5)); + OAI211_X1_LVT i_0_5 (.A(n_0_681), .B(n_0_5), .C1(op2[0]), .C2(n_0_568), + .ZN(n_0_4)); + NAND2_X1_LVT i_0_4 (.A1(op1[0]), .A2(n_0_4), .ZN(n_0_3)); + NAND3_X1_LVT i_0_1 (.A1(n_0_2), .A2(n_0_1), .A3(n_0_3), .ZN(n_0_0)); + OAI33_X1_LVT i_0_14 (.A1(n_0_692), .A2(op1[31]), .A3(n_0_683), .B1(op2[31]), + .B2(n_0_691), .B3(aluOp[0]), .ZN(n_0_13)); + INV_X1_LVT i_0_741 (.A(op2[29]), .ZN(n_0_708)); + NAND2_X1_LVT i_0_685 (.A1(op1[29]), .A2(n_0_708), .ZN(n_0_652)); + OAI22_X1_LVT i_0_713 (.A1(n_0_700), .A2(op1[28]), .B1(op1[29]), .B2(n_0_708), + .ZN(n_0_680)); + NAND2_X1_LVT i_0_694 (.A1(n_0_688), .A2(op2[27]), .ZN(n_0_661)); + INV_X1_LVT i_0_742 (.A(op2[26]), .ZN(n_0_709)); + OAI22_X1_LVT i_0_712 (.A1(n_0_699), .A2(op2[25]), .B1(n_0_736), .B2(op2[24]), + .ZN(n_0_679)); + NAND2_X1_LVT i_0_690 (.A1(n_0_727), .A2(op2[20]), .ZN(n_0_657)); + INV_X1_LVT i_0_740 (.A(op2[18]), .ZN(n_0_707)); + OAI22_X1_LVT i_0_711 (.A1(n_0_707), .A2(op1[18]), .B1(n_0_690), .B2(op1[19]), + .ZN(n_0_678)); + OAI22_X1_LVT i_0_29 (.A1(n_0_739), .A2(op2[16]), .B1(n_0_734), .B2(op2[15]), + .ZN(n_0_28)); + INV_X1_LVT i_0_728 (.A(op2[12]), .ZN(n_0_695)); + INV_X1_LVT i_0_748 (.A(op2[13]), .ZN(n_0_715)); + OAI22_X1_LVT i_0_704 (.A1(n_0_706), .A2(op2[11]), .B1(n_0_696), .B2(op2[12]), + .ZN(n_0_671)); + AOI22_X1_LVT i_0_710 (.A1(n_0_740), .A2(op2[8]), .B1(n_0_713), .B2(op2[7]), + .ZN(n_0_677)); + OAI22_X1_LVT i_0_707 (.A1(n_0_731), .A2(op1[5]), .B1(op1[6]), .B2(n_0_702), + .ZN(n_0_674)); + OAI22_X1_LVT i_0_706 (.A1(op1[2]), .A2(n_0_693), .B1(op1[1]), .B2(n_0_728), + .ZN(n_0_673)); + INV_X1_LVT i_0_705 (.A(n_0_673), .ZN(n_0_672)); + INV_X1_LVT i_0_699 (.A(n_0_667), .ZN(n_0_666)); + OAI21_X1_LVT i_0_42 (.A(n_0_672), .B1(n_0_666), .B2(n_0_665), .ZN(n_0_41)); + AOI21_X1_LVT i_0_41 (.A(n_0_654), .B1(op1[2]), .B2(n_0_693), .ZN(n_0_40)); + AOI211_X1_LVT i_0_40 (.A(n_0_668), .B(n_0_663), .C1(n_0_41), .C2(n_0_40), + .ZN(n_0_39)); + AOI211_X1_LVT i_0_39 (.A(n_0_656), .B(n_0_39), .C1(n_0_731), .C2(op1[5]), + .ZN(n_0_38)); + OAI222_X1_LVT i_0_38 (.A1(n_0_704), .A2(op2[6]), .B1(n_0_674), .B2(n_0_38), + .C1(n_0_713), .C2(op2[7]), .ZN(n_0_37)); + AOI221_X1_LVT i_0_37 (.A(n_0_655), .B1(op1[9]), .B2(n_0_720), .C1(n_0_677), + .C2(n_0_37), .ZN(n_0_36)); + INV_X1_LVT i_0_768 (.A(op2[10]), .ZN(n_0_735)); + OAI22_X1_LVT i_0_36 (.A1(n_0_735), .A2(op1[10]), .B1(op1[9]), .B2(n_0_720), + .ZN(n_0_35)); + OAI22_X1_LVT i_0_35 (.A1(op2[10]), .A2(n_0_733), .B1(n_0_36), .B2(n_0_35), + .ZN(n_0_34)); + INV_X1_LVT i_0_34 (.A(n_0_34), .ZN(n_0_33)); + AOI21_X1_LVT i_0_33 (.A(n_0_33), .B1(n_0_706), .B2(op2[11]), .ZN(n_0_32)); + OAI222_X1_LVT i_0_32 (.A1(op1[12]), .A2(n_0_695), .B1(n_0_715), .B2(op1[13]), + .C1(n_0_671), .C2(n_0_32), .ZN(n_0_31)); + OAI221_X1_LVT i_0_31 (.A(n_0_31), .B1(n_0_721), .B2(op2[14]), .C1(op2[13]), + .C2(n_0_714), .ZN(n_0_30)); + AOI22_X1_LVT i_0_30 (.A1(n_0_734), .A2(op2[15]), .B1(n_0_721), .B2(op2[14]), + .ZN(n_0_29)); + AOI21_X1_LVT i_0_28 (.A(n_0_28), .B1(n_0_30), .B2(n_0_29), .ZN(n_0_27)); + AOI221_X1_LVT i_0_27 (.A(n_0_27), .B1(n_0_732), .B2(op2[17]), .C1(n_0_739), + .C2(op2[16]), .ZN(n_0_26)); + AOI211_X1_LVT i_0_26 (.A(n_0_660), .B(n_0_26), .C1(n_0_707), .C2(op1[18]), + .ZN(n_0_25)); + OAI22_X1_LVT i_0_25 (.A1(op2[19]), .A2(n_0_689), .B1(n_0_678), .B2(n_0_25), + .ZN(n_0_24)); + AOI211_X1_LVT i_0_24 (.A(n_0_658), .B(n_0_659), .C1(n_0_657), .C2(n_0_24), + .ZN(n_0_23)); + AOI221_X1_LVT i_0_23 (.A(n_0_23), .B1(n_0_726), .B2(op2[21]), .C1(n_0_687), + .C2(op2[22]), .ZN(n_0_22)); + AOI221_X1_LVT i_0_22 (.A(n_0_22), .B1(op1[22]), .B2(n_0_686), .C1(op1[23]), + .C2(n_0_718), .ZN(n_0_21)); + AOI221_X1_LVT i_0_21 (.A(n_0_21), .B1(n_0_736), .B2(op2[24]), .C1(n_0_719), + .C2(op2[23]), .ZN(n_0_20)); + OAI222_X1_LVT i_0_20 (.A1(op1[26]), .A2(n_0_709), .B1(op1[25]), .B2(n_0_697), + .C1(n_0_679), .C2(n_0_20), .ZN(n_0_19)); + OAI221_X1_LVT i_0_19 (.A(n_0_19), .B1(n_0_711), .B2(op2[26]), .C1(n_0_688), + .C2(op2[27]), .ZN(n_0_18)); + AOI22_X1_LVT i_0_18 (.A1(n_0_700), .A2(op1[28]), .B1(n_0_661), .B2(n_0_18), + .ZN(n_0_17)); + OAI21_X1_LVT i_0_17 (.A(n_0_652), .B1(n_0_680), .B2(n_0_17), .ZN(n_0_16)); + INV_X1_LVT i_0_749 (.A(op2[30]), .ZN(n_0_716)); + OAI21_X1_LVT i_0_16 (.A(n_0_16), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_15)); + OAI22_X1_LVT i_0_708 (.A1(n_0_692), .A2(op1[31]), .B1(op2[31]), .B2(n_0_691), + .ZN(n_0_675)); + AOI21_X1_LVT i_0_15 (.A(n_0_675), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_14)); + AOI21_X1_LVT i_0_13 (.A(n_0_13), .B1(n_0_15), .B2(n_0_14), .ZN(n_0_12)); + NOR4_X1_LVT i_0_12 (.A1(n_0_685), .A2(aluOp[2]), .A3(aluBypass), .A4(n_0_12), + .ZN(n_0_11)); + OR3_X1_LVT i_0_0 (.A1(n_0_6), .A2(n_0_0), .A3(n_0_11), .ZN(result[0])); + OR4_X1_LVT i_0_703 (.A1(n_0_680), .A2(n_0_673), .A3(n_0_675), .A4(n_0_678), + .ZN(n_0_670)); + INV_X1_LVT i_0_709 (.A(n_0_677), .ZN(n_0_676)); + OR4_X1_LVT i_0_702 (.A1(n_0_679), .A2(n_0_674), .A3(n_0_676), .A4(n_0_671), + .ZN(n_0_669)); + AOI22_X1_LVT i_0_663 (.A1(n_0_688), .A2(op2[27]), .B1(op1[22]), .B2(n_0_686), + .ZN(n_0_630)); + OAI22_X1_LVT i_0_662 (.A1(n_0_694), .A2(op2[2]), .B1(op1[30]), .B2(n_0_716), + .ZN(n_0_629)); + AOI221_X1_LVT i_0_661 (.A(n_0_629), .B1(n_0_711), .B2(op2[26]), .C1(n_0_721), + .C2(op2[14]), .ZN(n_0_628)); + AOI21_X1_LVT i_0_664 (.A(n_0_660), .B1(n_0_690), .B2(op1[19]), .ZN(n_0_631)); + OAI222_X1_LVT i_0_660 (.A1(op1[12]), .A2(n_0_695), .B1(n_0_688), .B2(op2[27]), + .C1(op1[22]), .C2(n_0_686), .ZN(n_0_627)); + AOI21_X1_LVT i_0_659 (.A(n_0_663), .B1(n_0_734), .B2(op2[15]), .ZN(n_0_626)); + OAI211_X1_LVT i_0_658 (.A(n_0_666), .B(n_0_626), .C1(n_0_715), .C2(op1[13]), + .ZN(n_0_625)); + AOI211_X1_LVT i_0_657 (.A(n_0_627), .B(n_0_625), .C1(op1[23]), .C2(n_0_718), + .ZN(n_0_624)); + NAND4_X1_LVT i_0_656 (.A1(n_0_630), .A2(n_0_628), .A3(n_0_631), .A4(n_0_624), + .ZN(n_0_623)); + OAI22_X1_LVT i_0_684 (.A1(n_0_721), .A2(op2[14]), .B1(n_0_722), .B2(op2[9]), + .ZN(n_0_651)); + AOI211_X1_LVT i_0_668 (.A(n_0_651), .B(n_0_654), .C1(n_0_719), .C2(op2[23]), + .ZN(n_0_635)); + NAND2_X1_LVT i_0_667 (.A1(n_0_664), .A2(n_0_657), .ZN(n_0_634)); + NOR3_X1_LVT i_0_666 (.A1(n_0_659), .A2(n_0_656), .A3(n_0_634), .ZN(n_0_633)); + AOI21_X1_LVT i_0_671 (.A(n_0_655), .B1(n_0_739), .B2(op2[16]), .ZN(n_0_638)); + AOI21_X1_LVT i_0_670 (.A(n_0_668), .B1(n_0_736), .B2(op2[24]), .ZN(n_0_637)); + OAI22_X1_LVT i_0_673 (.A1(n_0_735), .A2(op1[10]), .B1(n_0_734), .B2(op2[15]), + .ZN(n_0_640)); + AOI221_X1_LVT i_0_672 (.A(n_0_640), .B1(n_0_732), .B2(op2[17]), .C1(n_0_731), + .C2(op1[5]), .ZN(n_0_639)); + AND3_X1_LVT i_0_669 (.A1(n_0_638), .A2(n_0_637), .A3(n_0_639), .ZN(n_0_636)); + OAI22_X1_LVT i_0_682 (.A1(n_0_703), .A2(op2[0]), .B1(n_0_704), .B2(op2[6]), + .ZN(n_0_649)); + OAI22_X1_LVT i_0_681 (.A1(op2[28]), .A2(n_0_698), .B1(op1[25]), .B2(n_0_697), + .ZN(n_0_648)); + AOI21_X1_LVT i_0_678 (.A(n_0_658), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_645)); + AOI21_X1_LVT i_0_677 (.A(n_0_662), .B1(n_0_735), .B2(op1[10]), .ZN(n_0_644)); + INV_X1_LVT i_0_758 (.A(op2[21]), .ZN(n_0_725)); + OAI22_X1_LVT i_0_683 (.A1(op1[21]), .A2(n_0_725), .B1(n_0_739), .B2(op2[16]), + .ZN(n_0_650)); + AOI221_X1_LVT i_0_676 (.A(n_0_650), .B1(n_0_722), .B2(op2[9]), .C1(op1[7]), + .C2(n_0_712), .ZN(n_0_643)); + OAI21_X1_LVT i_0_680 (.A(n_0_652), .B1(n_0_711), .B2(op2[26]), .ZN(n_0_647)); + AOI221_X1_LVT i_0_679 (.A(n_0_647), .B1(n_0_706), .B2(op2[11]), .C1(n_0_707), + .C2(op1[18]), .ZN(n_0_646)); + NAND4_X1_LVT i_0_675 (.A1(n_0_645), .A2(n_0_644), .A3(n_0_643), .A4(n_0_646), + .ZN(n_0_642)); + NOR3_X1_LVT i_0_674 (.A1(n_0_649), .A2(n_0_648), .A3(n_0_642), .ZN(n_0_641)); + NAND4_X1_LVT i_0_665 (.A1(n_0_635), .A2(n_0_633), .A3(n_0_636), .A4(n_0_641), + .ZN(n_0_632)); + NOR4_X1_LVT i_0_655 (.A1(n_0_670), .A2(n_0_669), .A3(n_0_623), .A4(n_0_632), + .ZN(eqFlag)); +endmodule + +module decoder(CurrentPC, JumpOrBranchPC, JumpOrBranch, DAddr, WData, RData, + Instruction, WrMem, DWidth, Rs1, Rs2, Rd, RRs1, RRs2, WRd, WrReg, Illegal); + input [31:0]CurrentPC; + output [31:0]JumpOrBranchPC; + output JumpOrBranch; + output [31:0]DAddr; + output [31:0]WData; + input [31:0]RData; + input [31:0]Instruction; + output WrMem; + output [1:0]DWidth; + output [4:0]Rs1; + output [4:0]Rs2; + output [4:0]Rd; + input [31:0]RRs1; + input [31:0]RRs2; + output [31:0]WRd; + output WrReg; + output Illegal; + + wire eqFlag; + wire n_5_0; + wire n_5_1; + wire n_5_2; + wire n_5_3; + wire n_5_4; + wire n_5_5; + wire n_5_6; + wire n_5_7; + wire n_5_8; + wire n_5_9; + wire n_5_10; + wire n_5_11; + wire n_5_12; + wire n_5_13; + wire n_5_14; + wire n_5_15; + wire n_5_16; + wire n_5_17; + wire n_5_18; + wire n_5_19; + wire n_5_20; + wire n_5_21; + wire n_5_22; + wire n_5_23; + wire n_5_24; + wire n_5_25; + wire n_5_26; + wire n_5_27; + wire n_5_28; + wire n_5_29; + wire n_5_30; + wire n_5_31; + wire n_5_32; + wire n_5_33; + wire n_17_0; + wire n_17_1; + wire n_17_2; + wire n_17_3; + wire n_17_4; + wire n_17_5; + wire n_17_6; + wire n_17_7; + wire n_17_8; + wire n_17_9; + wire n_17_10; + wire n_17_11; + wire n_17_12; + wire n_17_13; + wire n_17_14; + wire n_17_15; + wire n_17_16; + wire n_17_17; + wire n_17_18; + wire n_17_19; + wire n_17_20; + wire n_17_21; + wire n_17_22; + wire n_17_23; + wire n_17_24; + wire n_17_25; + wire n_17_26; + wire n_17_27; + wire n_17_28; + wire n_17_29; + wire n_17_30; + wire n_17_31; + wire n_17_32; + wire n_18_0; + wire n_18_1; + wire n_18_2; + wire n_18_3; + wire n_18_4; + wire n_18_5; + wire n_18_6; + wire n_18_7; + wire n_18_8; + wire n_18_9; + wire n_18_10; + wire n_18_11; + wire n_18_12; + wire n_18_13; + wire n_18_14; + wire n_18_15; + wire n_18_16; + wire n_18_17; + wire n_18_18; + wire n_18_19; + wire n_18_20; + wire n_18_21; + wire n_18_22; + wire n_18_23; + wire n_18_24; + wire n_18_25; + wire n_18_26; + wire n_18_27; + wire n_18_28; + wire n_18_29; + wire n_18_30; + wire n_18_31; + wire n_18_32; + wire n_0_15; + wire n_0_2; + wire n_0_16; + wire n_0_3; + wire n_0_17; + wire n_0_4; + wire n_0_18; + wire n_0_5; + wire n_0_19; + wire n_0_6; + wire n_0_20; + wire n_0_7; + wire n_0_21; + wire n_0_8; + wire n_0_22; + wire n_0_9; + wire n_0_23; + wire n_0_10; + wire n_0_24; + wire n_0_11; + wire n_0_25; + wire n_0_12; + wire n_0_26; + wire n_0_13; + wire n_0_27; + wire n_0_14; + wire n_0_28; + wire n_0_29; + wire n_0_30; + wire n_0_31; + wire n_0_32; + wire n_0_33; + wire n_0_34; + wire n_0_35; + wire n_0_36; + wire n_0_37; + wire n_0_38; + wire n_0_39; + wire n_0_40; + wire n_0_41; + wire n_0_42; + wire n_0_43; + wire n_0_44; + wire n_0_45; + wire n_0_46; + wire n_0_47; + wire n_0_48; + wire n_0_49; + wire n_0_50; + wire n_0_51; + wire n_0_52; + wire n_0_53; + wire n_0_54; + wire n_0_55; + wire n_0_56; + wire n_0_57; + wire n_0_58; + wire n_0_59; + wire n_0_60; + wire n_0_61; + wire n_0_62; + wire n_0_63; + wire n_0_64; + wire n_0_65; + wire n_0_66; + wire n_0_67; + wire n_0_68; + wire n_0_69; + wire n_0_70; + wire n_0_71; + wire n_0_72; + wire n_0_73; + wire n_0_74; + wire n_0_75; + wire n_0_76; + wire n_0_77; + wire n_0_78; + wire n_0_79; + wire n_0_80; + wire n_0_81; + wire n_0_82; + wire n_0_83; + wire n_0_84; + wire n_0_85; + wire n_0_86; + wire n_0_87; + wire n_0_88; + wire n_0_89; + wire n_0_90; + wire n_0_91; + wire n_0_92; + wire n_0_93; + wire n_0_94; + wire n_0_95; + wire n_0_96; + wire n_0_97; + wire [2:0]aluOp; + wire n_0_98; + wire n_0_99; + wire n_0_100; + wire aluNegAr; + wire n_0_101; + wire n_0_102; + wire n_0_103; + wire n_0_104; + wire n_0_105; + wire aluBypass; + wire n_0_106; + wire [31:0]op1; + wire n_0_107; + wire n_0_108; + wire n_0_109; + wire n_0_110; + wire n_0_111; + wire n_0_112; + wire n_0_113; + wire n_0_114; + wire n_0_115; + wire n_0_116; + wire n_0_117; + wire n_0_118; + wire n_0_119; + wire n_0_120; + wire n_0_121; + wire n_0_122; + wire n_0_123; + wire n_0_124; + wire n_0_125; + wire n_0_126; + wire n_0_127; + wire n_0_128; + wire n_0_129; + wire n_0_130; + wire n_0_131; + wire n_0_132; + wire n_0_133; + wire n_0_134; + wire n_0_135; + wire n_0_136; + wire n_0_137; + wire n_0_138; + wire n_0_139; + wire n_0_140; + wire n_0_141; + wire n_0_142; + wire n_0_143; + wire n_0_144; + wire n_0_145; + wire n_0_146; + wire n_0_147; + wire n_0_148; + wire n_0_149; + wire n_0_150; + wire n_0_151; + wire n_0_152; + wire n_0_153; + wire n_0_154; + wire n_0_155; + wire n_0_156; + wire n_0_157; + wire n_0_158; + wire n_0_159; + wire n_0_160; + wire n_0_161; + wire n_0_162; + wire n_0_163; + wire n_0_164; + wire n_0_165; + wire n_0_166; + wire n_0_167; + wire n_0_168; + wire n_0_169; + wire [31:0]op2; + wire n_0_170; + wire n_0_171; + wire n_0_172; + wire n_0_173; + wire n_0_174; + wire n_0_175; + wire n_0_176; + wire n_0_177; + wire n_0_178; + wire n_0_179; + wire n_0_180; + wire n_0_181; + wire n_0_182; + wire n_0_183; + wire n_0_184; + wire n_0_185; + wire n_0_186; + wire n_0_187; + wire n_0_188; + wire n_0_189; + wire n_0_190; + wire n_0_191; + wire n_0_192; + wire n_0_193; + wire n_0_194; + wire n_0_195; + wire n_0_196; + wire n_0_197; + wire n_0_198; + wire n_0_199; + wire n_0_200; + wire n_0_201; + wire n_0_202; + wire n_0_203; + wire n_0_204; + wire n_0_205; + wire n_0_206; + wire n_0_207; + wire n_0_208; + wire n_0_209; + wire n_0_210; + wire n_0_211; + wire n_0_212; + wire n_0_213; + wire n_0_214; + wire n_0_215; + wire n_0_216; + wire n_0_217; + wire n_0_218; + wire n_0_219; + wire n_0_220; + wire n_0_221; + wire n_0_222; + wire n_0_223; + wire n_0_224; + wire n_0_225; + wire n_0_226; + wire n_0_227; + wire n_0_228; + wire n_0_229; + wire n_0_230; + wire n_0_231; + wire n_0_232; + wire n_0_233; + wire n_0_234; + wire n_0_235; + wire n_0_236; + wire n_0_237; + wire n_0_238; + wire n_0_239; + wire n_0_240; + wire n_0_241; + wire n_0_242; + wire n_0_1; + wire n_0_0; + wire n_0_243; + wire n_0_244; + wire n_0_245; + wire n_0_246; + wire n_0_247; + wire n_0_248; + wire n_0_249; + + INV_X1_LVT i_18_1 (.A(CurrentPC[13]), .ZN(n_18_1)); + XNOR2_X1_LVT i_18_32 (.A(CurrentPC[31]), .B(n_18_1), .ZN(n_18_32)); + INV_X1_LVT i_18_0 (.A(Instruction[31]), .ZN(n_18_0)); + HA_X1_LVT i_18_2 (.A(Instruction[8]), .B(CurrentPC[1]), .CO(n_18_2), .S(n_63)); + FA_X1_LVT i_18_3 (.A(Instruction[9]), .B(CurrentPC[2]), .CI(n_18_2), .CO( + n_18_3), .S(n_64)); + FA_X1_LVT i_18_4 (.A(Instruction[10]), .B(CurrentPC[3]), .CI(n_18_3), + .CO(n_18_4), .S(n_65)); + FA_X1_LVT i_18_5 (.A(Instruction[11]), .B(CurrentPC[4]), .CI(n_18_4), + .CO(n_18_5), .S(n_66)); + FA_X1_LVT i_18_6 (.A(Instruction[25]), .B(CurrentPC[5]), .CI(n_18_5), + .CO(n_18_6), .S(n_67)); + FA_X1_LVT i_18_7 (.A(Instruction[26]), .B(CurrentPC[6]), .CI(n_18_6), + .CO(n_18_7), .S(n_68)); + FA_X1_LVT i_18_8 (.A(Instruction[27]), .B(CurrentPC[7]), .CI(n_18_7), + .CO(n_18_8), .S(n_69)); + FA_X1_LVT i_18_9 (.A(Instruction[28]), .B(CurrentPC[8]), .CI(n_18_8), + .CO(n_18_9), .S(n_70)); + FA_X1_LVT i_18_10 (.A(Instruction[29]), .B(CurrentPC[9]), .CI(n_18_9), + .CO(n_18_10), .S(n_71)); + FA_X1_LVT i_18_11 (.A(Instruction[30]), .B(CurrentPC[10]), .CI(n_18_10), + .CO(n_18_11), .S(n_72)); + FA_X1_LVT i_18_12 (.A(Instruction[7]), .B(CurrentPC[11]), .CI(n_18_11), + .CO(n_18_12), .S(n_73)); + FA_X1_LVT i_18_13 (.A(CurrentPC[12]), .B(Instruction[31]), .CI(n_18_12), + .CO(n_18_13), .S(n_74)); + FA_X1_LVT i_18_14 (.A(n_18_0), .B(n_18_1), .CI(n_18_13), .CO(n_18_14), + .S(n_75)); + FA_X1_LVT i_18_15 (.A(CurrentPC[14]), .B(n_18_1), .CI(n_18_14), .CO(n_18_15), + .S(n_76)); + FA_X1_LVT i_18_16 (.A(CurrentPC[15]), .B(n_18_1), .CI(n_18_15), .CO(n_18_16), + .S(n_77)); + FA_X1_LVT i_18_17 (.A(CurrentPC[16]), .B(n_18_1), .CI(n_18_16), .CO(n_18_17), + .S(n_78)); + FA_X1_LVT i_18_18 (.A(CurrentPC[17]), .B(n_18_1), .CI(n_18_17), .CO(n_18_18), + .S(n_79)); + FA_X1_LVT i_18_19 (.A(CurrentPC[18]), .B(n_18_1), .CI(n_18_18), .CO(n_18_19), + .S(n_80)); + FA_X1_LVT i_18_20 (.A(CurrentPC[19]), .B(n_18_1), .CI(n_18_19), .CO(n_18_20), + .S(n_81)); + FA_X1_LVT i_18_21 (.A(CurrentPC[20]), .B(n_18_1), .CI(n_18_20), .CO(n_18_21), + .S(n_82)); + FA_X1_LVT i_18_22 (.A(CurrentPC[21]), .B(n_18_1), .CI(n_18_21), .CO(n_18_22), + .S(n_83)); + FA_X1_LVT i_18_23 (.A(CurrentPC[22]), .B(n_18_1), .CI(n_18_22), .CO(n_18_23), + .S(n_84)); + FA_X1_LVT i_18_24 (.A(CurrentPC[23]), .B(n_18_1), .CI(n_18_23), .CO(n_18_24), + .S(n_85)); + FA_X1_LVT i_18_25 (.A(CurrentPC[24]), .B(n_18_1), .CI(n_18_24), .CO(n_18_25), + .S(n_86)); + FA_X1_LVT i_18_26 (.A(CurrentPC[25]), .B(n_18_1), .CI(n_18_25), .CO(n_18_26), + .S(n_87)); + FA_X1_LVT i_18_27 (.A(CurrentPC[26]), .B(n_18_1), .CI(n_18_26), .CO(n_18_27), + .S(n_88)); + FA_X1_LVT i_18_28 (.A(CurrentPC[27]), .B(n_18_1), .CI(n_18_27), .CO(n_18_28), + .S(n_89)); + FA_X1_LVT i_18_29 (.A(CurrentPC[28]), .B(n_18_1), .CI(n_18_28), .CO(n_18_29), + .S(n_90)); + FA_X1_LVT i_18_30 (.A(CurrentPC[29]), .B(n_18_1), .CI(n_18_29), .CO(n_18_30), + .S(n_91)); + FA_X1_LVT i_18_31 (.A(CurrentPC[30]), .B(n_18_1), .CI(n_18_30), .CO(n_18_31), + .S(n_92)); + XNOR2_X1_LVT i_18_33 (.A(n_18_32), .B(n_18_31), .ZN(n_93)); + INV_X1_LVT i_0_350 (.A(Instruction[3]), .ZN(n_0_243)); + NAND3_X1_LVT i_0_343 (.A1(n_0_243), .A2(Instruction[0]), .A3(Instruction[1]), + .ZN(n_0_238)); + OR2_X1_LVT i_0_332 (.A1(n_0_238), .A2(Instruction[2]), .ZN(n_0_228)); + INV_X1_LVT i_0_351 (.A(Instruction[5]), .ZN(n_0_244)); + NOR2_X1_LVT i_0_340 (.A1(n_0_244), .A2(Instruction[4]), .ZN(n_0_235)); + NAND2_X1_LVT i_0_329 (.A1(Instruction[6]), .A2(n_0_235), .ZN(n_0_225)); + INV_X1_LVT i_0_354 (.A(Instruction[13]), .ZN(n_0_247)); + NOR2_X1_LVT i_0_345 (.A1(n_0_247), .A2(Instruction[14]), .ZN(n_0_240)); + NOR3_X1_LVT i_0_118 (.A1(n_0_228), .A2(n_0_225), .A3(n_0_240), .ZN(n_0_99)); + NAND3_X1_LVT i_0_346 (.A1(Instruction[0]), .A2(Instruction[1]), .A3( + Instruction[2]), .ZN(n_0_241)); + NOR2_X1_LVT i_0_328 (.A1(n_0_241), .A2(n_0_225), .ZN(n_0_224)); + INV_X1_LVT i_0_356 (.A(n_0_224), .ZN(n_0_249)); + NOR2_X1_LVT i_0_108 (.A1(n_0_243), .A2(n_0_249), .ZN(n_0_91)); + INV_X1_LVT i_17_1 (.A(CurrentPC[21]), .ZN(n_17_1)); + XNOR2_X1_LVT i_17_32 (.A(CurrentPC[31]), .B(n_17_1), .ZN(n_17_32)); + INV_X1_LVT i_17_0 (.A(Instruction[31]), .ZN(n_17_0)); + HA_X1_LVT i_17_2 (.A(Instruction[21]), .B(CurrentPC[1]), .CO(n_17_2), + .S(n_32)); + FA_X1_LVT i_17_3 (.A(Instruction[22]), .B(CurrentPC[2]), .CI(n_17_2), + .CO(n_17_3), .S(n_33)); + FA_X1_LVT i_17_4 (.A(Instruction[23]), .B(CurrentPC[3]), .CI(n_17_3), + .CO(n_17_4), .S(n_34)); + FA_X1_LVT i_17_5 (.A(Instruction[24]), .B(CurrentPC[4]), .CI(n_17_4), + .CO(n_17_5), .S(n_35)); + FA_X1_LVT i_17_6 (.A(Instruction[25]), .B(CurrentPC[5]), .CI(n_17_5), + .CO(n_17_6), .S(n_36)); + FA_X1_LVT i_17_7 (.A(Instruction[26]), .B(CurrentPC[6]), .CI(n_17_6), + .CO(n_17_7), .S(n_37)); + FA_X1_LVT i_17_8 (.A(Instruction[27]), .B(CurrentPC[7]), .CI(n_17_7), + .CO(n_17_8), .S(n_38)); + FA_X1_LVT i_17_9 (.A(Instruction[28]), .B(CurrentPC[8]), .CI(n_17_8), + .CO(n_17_9), .S(n_39)); + FA_X1_LVT i_17_10 (.A(Instruction[29]), .B(CurrentPC[9]), .CI(n_17_9), + .CO(n_17_10), .S(n_40)); + FA_X1_LVT i_17_11 (.A(Instruction[30]), .B(CurrentPC[10]), .CI(n_17_10), + .CO(n_17_11), .S(n_41)); + FA_X1_LVT i_17_12 (.A(Instruction[20]), .B(CurrentPC[11]), .CI(n_17_11), + .CO(n_17_12), .S(n_42)); + FA_X1_LVT i_17_13 (.A(Instruction[12]), .B(CurrentPC[12]), .CI(n_17_12), + .CO(n_17_13), .S(n_43)); + FA_X1_LVT i_17_14 (.A(Instruction[13]), .B(CurrentPC[13]), .CI(n_17_13), + .CO(n_17_14), .S(n_44)); + FA_X1_LVT i_17_15 (.A(Instruction[14]), .B(CurrentPC[14]), .CI(n_17_14), + .CO(n_17_15), .S(n_45)); + FA_X1_LVT i_17_16 (.A(Instruction[15]), .B(CurrentPC[15]), .CI(n_17_15), + .CO(n_17_16), .S(n_46)); + FA_X1_LVT i_17_17 (.A(Instruction[16]), .B(CurrentPC[16]), .CI(n_17_16), + .CO(n_17_17), .S(n_47)); + FA_X1_LVT i_17_18 (.A(Instruction[17]), .B(CurrentPC[17]), .CI(n_17_17), + .CO(n_17_18), .S(n_48)); + FA_X1_LVT i_17_19 (.A(Instruction[18]), .B(CurrentPC[18]), .CI(n_17_18), + .CO(n_17_19), .S(n_49)); + FA_X1_LVT i_17_20 (.A(Instruction[19]), .B(CurrentPC[19]), .CI(n_17_19), + .CO(n_17_20), .S(n_50)); + FA_X1_LVT i_17_21 (.A(CurrentPC[20]), .B(Instruction[31]), .CI(n_17_20), + .CO(n_17_21), .S(n_51)); + FA_X1_LVT i_17_22 (.A(n_17_0), .B(n_17_1), .CI(n_17_21), .CO(n_17_22), + .S(n_52)); + FA_X1_LVT i_17_23 (.A(CurrentPC[22]), .B(n_17_1), .CI(n_17_22), .CO(n_17_23), + .S(n_53)); + FA_X1_LVT i_17_24 (.A(CurrentPC[23]), .B(n_17_1), .CI(n_17_23), .CO(n_17_24), + .S(n_54)); + FA_X1_LVT i_17_25 (.A(CurrentPC[24]), .B(n_17_1), .CI(n_17_24), .CO(n_17_25), + .S(n_55)); + FA_X1_LVT i_17_26 (.A(CurrentPC[25]), .B(n_17_1), .CI(n_17_25), .CO(n_17_26), + .S(n_56)); + FA_X1_LVT i_17_27 (.A(CurrentPC[26]), .B(n_17_1), .CI(n_17_26), .CO(n_17_27), + .S(n_57)); + FA_X1_LVT i_17_28 (.A(CurrentPC[27]), .B(n_17_1), .CI(n_17_27), .CO(n_17_28), + .S(n_58)); + FA_X1_LVT i_17_29 (.A(CurrentPC[28]), .B(n_17_1), .CI(n_17_28), .CO(n_17_29), + .S(n_59)); + FA_X1_LVT i_17_30 (.A(CurrentPC[29]), .B(n_17_1), .CI(n_17_29), .CO(n_17_30), + .S(n_60)); + FA_X1_LVT i_17_31 (.A(CurrentPC[30]), .B(n_17_1), .CI(n_17_30), .CO(n_17_31), + .S(n_61)); + XNOR2_X1_LVT i_17_33 (.A(n_17_32), .B(n_17_31), .ZN(n_62)); + INV_X1_LVT i_5_1 (.A(RRs1[12]), .ZN(n_5_1)); + XNOR2_X1_LVT i_5_33 (.A(RRs1[31]), .B(n_5_1), .ZN(n_5_33)); + INV_X1_LVT i_5_0 (.A(Instruction[31]), .ZN(n_5_0)); + HA_X1_LVT i_5_2 (.A(Instruction[20]), .B(RRs1[0]), .CO(n_5_2), .S(n_0)); + FA_X1_LVT i_5_3 (.A(Instruction[21]), .B(RRs1[1]), .CI(n_5_2), .CO(n_5_3), + .S(n_1)); + FA_X1_LVT i_5_4 (.A(Instruction[22]), .B(RRs1[2]), .CI(n_5_3), .CO(n_5_4), + .S(n_2)); + FA_X1_LVT i_5_5 (.A(Instruction[23]), .B(RRs1[3]), .CI(n_5_4), .CO(n_5_5), + .S(n_3)); + FA_X1_LVT i_5_6 (.A(Instruction[24]), .B(RRs1[4]), .CI(n_5_5), .CO(n_5_6), + .S(n_4)); + FA_X1_LVT i_5_7 (.A(Instruction[25]), .B(RRs1[5]), .CI(n_5_6), .CO(n_5_7), + .S(n_5)); + FA_X1_LVT i_5_8 (.A(Instruction[26]), .B(RRs1[6]), .CI(n_5_7), .CO(n_5_8), + .S(n_6)); + FA_X1_LVT i_5_9 (.A(Instruction[27]), .B(RRs1[7]), .CI(n_5_8), .CO(n_5_9), + .S(n_7)); + FA_X1_LVT i_5_10 (.A(Instruction[28]), .B(RRs1[8]), .CI(n_5_9), .CO(n_5_10), + .S(n_8)); + FA_X1_LVT i_5_11 (.A(Instruction[29]), .B(RRs1[9]), .CI(n_5_10), .CO(n_5_11), + .S(n_9)); + FA_X1_LVT i_5_12 (.A(Instruction[30]), .B(RRs1[10]), .CI(n_5_11), .CO(n_5_12), + .S(n_10)); + FA_X1_LVT i_5_13 (.A(RRs1[11]), .B(Instruction[31]), .CI(n_5_12), .CO(n_5_13), + .S(n_11)); + FA_X1_LVT i_5_14 (.A(n_5_0), .B(n_5_1), .CI(n_5_13), .CO(n_5_14), .S(n_12)); + FA_X1_LVT i_5_15 (.A(RRs1[13]), .B(n_5_1), .CI(n_5_14), .CO(n_5_15), .S(n_13)); + FA_X1_LVT i_5_16 (.A(RRs1[14]), .B(n_5_1), .CI(n_5_15), .CO(n_5_16), .S(n_14)); + FA_X1_LVT i_5_17 (.A(RRs1[15]), .B(n_5_1), .CI(n_5_16), .CO(n_5_17), .S(n_15)); + FA_X1_LVT i_5_18 (.A(RRs1[16]), .B(n_5_1), .CI(n_5_17), .CO(n_5_18), .S(n_16)); + FA_X1_LVT i_5_19 (.A(RRs1[17]), .B(n_5_1), .CI(n_5_18), .CO(n_5_19), .S(n_17)); + FA_X1_LVT i_5_20 (.A(RRs1[18]), .B(n_5_1), .CI(n_5_19), .CO(n_5_20), .S(n_18)); + FA_X1_LVT i_5_21 (.A(RRs1[19]), .B(n_5_1), .CI(n_5_20), .CO(n_5_21), .S(n_19)); + FA_X1_LVT i_5_22 (.A(RRs1[20]), .B(n_5_1), .CI(n_5_21), .CO(n_5_22), .S(n_20)); + FA_X1_LVT i_5_23 (.A(RRs1[21]), .B(n_5_1), .CI(n_5_22), .CO(n_5_23), .S(n_21)); + FA_X1_LVT i_5_24 (.A(RRs1[22]), .B(n_5_1), .CI(n_5_23), .CO(n_5_24), .S(n_22)); + FA_X1_LVT i_5_25 (.A(RRs1[23]), .B(n_5_1), .CI(n_5_24), .CO(n_5_25), .S(n_23)); + FA_X1_LVT i_5_26 (.A(RRs1[24]), .B(n_5_1), .CI(n_5_25), .CO(n_5_26), .S(n_24)); + FA_X1_LVT i_5_27 (.A(RRs1[25]), .B(n_5_1), .CI(n_5_26), .CO(n_5_27), .S(n_25)); + FA_X1_LVT i_5_28 (.A(RRs1[26]), .B(n_5_1), .CI(n_5_27), .CO(n_5_28), .S(n_26)); + FA_X1_LVT i_5_29 (.A(RRs1[27]), .B(n_5_1), .CI(n_5_28), .CO(n_5_29), .S(n_27)); + FA_X1_LVT i_5_30 (.A(RRs1[28]), .B(n_5_1), .CI(n_5_29), .CO(n_5_30), .S(n_28)); + FA_X1_LVT i_5_31 (.A(RRs1[29]), .B(n_5_1), .CI(n_5_30), .CO(n_5_31), .S(n_29)); + FA_X1_LVT i_5_32 (.A(RRs1[30]), .B(n_5_1), .CI(n_5_31), .CO(n_5_32), .S(n_30)); + XNOR2_X1_LVT i_5_34 (.A(n_5_33), .B(n_5_32), .ZN(n_31)); + NOR2_X1_LVT i_0_107 (.A1(n_0_249), .A2(Instruction[3]), .ZN(n_0_90)); + AOI222_X1_LVT i_0_106 (.A1(n_93), .A2(n_0_99), .B1(n_0_91), .B2(n_62), + .C1(n_31), .C2(n_0_90), .ZN(n_0_89)); + INV_X1_LVT i_0_355 (.A(Instruction[6]), .ZN(n_0_248)); + NAND2_X1_LVT i_0_339 (.A1(n_0_248), .A2(Instruction[4]), .ZN(n_0_234)); + INV_X1_LVT i_0_338 (.A(n_0_234), .ZN(n_0_233)); + OAI21_X1_LVT i_0_341 (.A(Instruction[13]), .B1(Instruction[14]), .B2( + Instruction[12]), .ZN(n_0_236)); + AOI211_X1_LVT i_0_337 (.A(n_0_235), .B(n_0_233), .C1(n_0_248), .C2(n_0_236), + .ZN(n_0_232)); + INV_X1_LVT i_0_352 (.A(Instruction[4]), .ZN(n_0_245)); + NAND2_X1_LVT i_0_344 (.A1(n_0_245), .A2(Instruction[2]), .ZN(n_0_239)); + AOI21_X1_LVT i_0_335 (.A(Instruction[6]), .B1(n_0_243), .B2(n_0_239), + .ZN(n_0_230)); + NOR2_X1_LVT i_0_334 (.A1(n_0_232), .A2(n_0_230), .ZN(n_0_229)); + NAND2_X1_LVT i_0_342 (.A1(n_0_241), .A2(n_0_238), .ZN(n_0_237)); + NAND2_X1_LVT i_0_336 (.A1(Instruction[6]), .A2(n_0_240), .ZN(n_0_231)); + OAI211_X1_LVT i_0_333 (.A(n_0_229), .B(n_0_237), .C1(Instruction[2]), + .C2(n_0_231), .ZN(Illegal)); + NAND2_X1_LVT i_0_109 (.A1(Illegal), .A2(CurrentPC[31]), .ZN(n_0_92)); + NAND2_X1_LVT i_0_105 (.A1(n_0_89), .A2(n_0_92), .ZN(JumpOrBranchPC[31])); + AOI222_X1_LVT i_0_103 (.A1(n_92), .A2(n_0_99), .B1(n_0_91), .B2(n_61), + .C1(n_30), .C2(n_0_90), .ZN(n_0_87)); + NAND2_X1_LVT i_0_104 (.A1(Illegal), .A2(CurrentPC[30]), .ZN(n_0_88)); + NAND2_X1_LVT i_0_102 (.A1(n_0_87), .A2(n_0_88), .ZN(JumpOrBranchPC[30])); + AOI222_X1_LVT i_0_100 (.A1(n_91), .A2(n_0_99), .B1(n_0_91), .B2(n_60), + .C1(n_29), .C2(n_0_90), .ZN(n_0_85)); + NAND2_X1_LVT i_0_101 (.A1(Illegal), .A2(CurrentPC[29]), .ZN(n_0_86)); + NAND2_X1_LVT i_0_99 (.A1(n_0_85), .A2(n_0_86), .ZN(JumpOrBranchPC[29])); + AOI222_X1_LVT i_0_97 (.A1(n_90), .A2(n_0_99), .B1(n_0_91), .B2(n_59), + .C1(n_28), .C2(n_0_90), .ZN(n_0_83)); + NAND2_X1_LVT i_0_98 (.A1(Illegal), .A2(CurrentPC[28]), .ZN(n_0_84)); + NAND2_X1_LVT i_0_96 (.A1(n_0_83), .A2(n_0_84), .ZN(JumpOrBranchPC[28])); + AOI222_X1_LVT i_0_94 (.A1(n_89), .A2(n_0_99), .B1(n_0_91), .B2(n_58), + .C1(n_27), .C2(n_0_90), .ZN(n_0_81)); + NAND2_X1_LVT i_0_95 (.A1(Illegal), .A2(CurrentPC[27]), .ZN(n_0_82)); + NAND2_X1_LVT i_0_93 (.A1(n_0_81), .A2(n_0_82), .ZN(JumpOrBranchPC[27])); + AOI222_X1_LVT i_0_91 (.A1(n_88), .A2(n_0_99), .B1(n_0_91), .B2(n_57), + .C1(n_26), .C2(n_0_90), .ZN(n_0_79)); + NAND2_X1_LVT i_0_92 (.A1(Illegal), .A2(CurrentPC[26]), .ZN(n_0_80)); + NAND2_X1_LVT i_0_90 (.A1(n_0_79), .A2(n_0_80), .ZN(JumpOrBranchPC[26])); + AOI222_X1_LVT i_0_88 (.A1(n_87), .A2(n_0_99), .B1(n_0_91), .B2(n_56), + .C1(n_25), .C2(n_0_90), .ZN(n_0_77)); + NAND2_X1_LVT i_0_89 (.A1(Illegal), .A2(CurrentPC[25]), .ZN(n_0_78)); + NAND2_X1_LVT i_0_87 (.A1(n_0_77), .A2(n_0_78), .ZN(JumpOrBranchPC[25])); + AOI222_X1_LVT i_0_85 (.A1(n_86), .A2(n_0_99), .B1(n_0_91), .B2(n_55), + .C1(n_24), .C2(n_0_90), .ZN(n_0_75)); + NAND2_X1_LVT i_0_86 (.A1(Illegal), .A2(CurrentPC[24]), .ZN(n_0_76)); + NAND2_X1_LVT i_0_84 (.A1(n_0_75), .A2(n_0_76), .ZN(JumpOrBranchPC[24])); + AOI222_X1_LVT i_0_82 (.A1(n_85), .A2(n_0_99), .B1(n_0_91), .B2(n_54), + .C1(n_23), .C2(n_0_90), .ZN(n_0_73)); + NAND2_X1_LVT i_0_83 (.A1(Illegal), .A2(CurrentPC[23]), .ZN(n_0_74)); + NAND2_X1_LVT i_0_81 (.A1(n_0_73), .A2(n_0_74), .ZN(JumpOrBranchPC[23])); + AOI222_X1_LVT i_0_79 (.A1(n_84), .A2(n_0_99), .B1(n_0_91), .B2(n_53), + .C1(n_22), .C2(n_0_90), .ZN(n_0_71)); + NAND2_X1_LVT i_0_80 (.A1(Illegal), .A2(CurrentPC[22]), .ZN(n_0_72)); + NAND2_X1_LVT i_0_78 (.A1(n_0_71), .A2(n_0_72), .ZN(JumpOrBranchPC[22])); + AOI222_X1_LVT i_0_76 (.A1(n_83), .A2(n_0_99), .B1(n_0_91), .B2(n_52), + .C1(n_21), .C2(n_0_90), .ZN(n_0_69)); + NAND2_X1_LVT i_0_77 (.A1(Illegal), .A2(CurrentPC[21]), .ZN(n_0_70)); + NAND2_X1_LVT i_0_75 (.A1(n_0_69), .A2(n_0_70), .ZN(JumpOrBranchPC[21])); + AOI222_X1_LVT i_0_73 (.A1(n_82), .A2(n_0_99), .B1(n_0_91), .B2(n_51), + .C1(n_20), .C2(n_0_90), .ZN(n_0_67)); + NAND2_X1_LVT i_0_74 (.A1(Illegal), .A2(CurrentPC[20]), .ZN(n_0_68)); + NAND2_X1_LVT i_0_72 (.A1(n_0_67), .A2(n_0_68), .ZN(JumpOrBranchPC[20])); + AOI222_X1_LVT i_0_70 (.A1(n_81), .A2(n_0_99), .B1(n_0_91), .B2(n_50), + .C1(n_19), .C2(n_0_90), .ZN(n_0_65)); + NAND2_X1_LVT i_0_71 (.A1(Illegal), .A2(CurrentPC[19]), .ZN(n_0_66)); + NAND2_X1_LVT i_0_69 (.A1(n_0_65), .A2(n_0_66), .ZN(JumpOrBranchPC[19])); + AOI222_X1_LVT i_0_67 (.A1(n_80), .A2(n_0_99), .B1(n_0_91), .B2(n_49), + .C1(n_18), .C2(n_0_90), .ZN(n_0_63)); + NAND2_X1_LVT i_0_68 (.A1(Illegal), .A2(CurrentPC[18]), .ZN(n_0_64)); + NAND2_X1_LVT i_0_66 (.A1(n_0_63), .A2(n_0_64), .ZN(JumpOrBranchPC[18])); + AOI222_X1_LVT i_0_64 (.A1(n_79), .A2(n_0_99), .B1(n_0_91), .B2(n_48), + .C1(n_17), .C2(n_0_90), .ZN(n_0_61)); + NAND2_X1_LVT i_0_65 (.A1(Illegal), .A2(CurrentPC[17]), .ZN(n_0_62)); + NAND2_X1_LVT i_0_63 (.A1(n_0_61), .A2(n_0_62), .ZN(JumpOrBranchPC[17])); + AOI222_X1_LVT i_0_61 (.A1(n_78), .A2(n_0_99), .B1(n_0_91), .B2(n_47), + .C1(n_16), .C2(n_0_90), .ZN(n_0_59)); + NAND2_X1_LVT i_0_62 (.A1(Illegal), .A2(CurrentPC[16]), .ZN(n_0_60)); + NAND2_X1_LVT i_0_60 (.A1(n_0_59), .A2(n_0_60), .ZN(JumpOrBranchPC[16])); + AOI222_X1_LVT i_0_58 (.A1(n_77), .A2(n_0_99), .B1(n_0_91), .B2(n_46), + .C1(n_15), .C2(n_0_90), .ZN(n_0_57)); + NAND2_X1_LVT i_0_59 (.A1(Illegal), .A2(CurrentPC[15]), .ZN(n_0_58)); + NAND2_X1_LVT i_0_57 (.A1(n_0_57), .A2(n_0_58), .ZN(JumpOrBranchPC[15])); + AOI222_X1_LVT i_0_55 (.A1(n_76), .A2(n_0_99), .B1(n_0_91), .B2(n_45), + .C1(n_14), .C2(n_0_90), .ZN(n_0_55)); + NAND2_X1_LVT i_0_56 (.A1(Illegal), .A2(CurrentPC[14]), .ZN(n_0_56)); + NAND2_X1_LVT i_0_54 (.A1(n_0_55), .A2(n_0_56), .ZN(JumpOrBranchPC[14])); + AOI222_X1_LVT i_0_52 (.A1(n_75), .A2(n_0_99), .B1(n_0_91), .B2(n_44), + .C1(n_13), .C2(n_0_90), .ZN(n_0_53)); + NAND2_X1_LVT i_0_53 (.A1(Illegal), .A2(CurrentPC[13]), .ZN(n_0_54)); + NAND2_X1_LVT i_0_51 (.A1(n_0_53), .A2(n_0_54), .ZN(JumpOrBranchPC[13])); + AOI222_X1_LVT i_0_49 (.A1(n_74), .A2(n_0_99), .B1(n_0_91), .B2(n_43), + .C1(n_12), .C2(n_0_90), .ZN(n_0_51)); + NAND2_X1_LVT i_0_50 (.A1(Illegal), .A2(CurrentPC[12]), .ZN(n_0_52)); + NAND2_X1_LVT i_0_48 (.A1(n_0_51), .A2(n_0_52), .ZN(JumpOrBranchPC[12])); + AOI222_X1_LVT i_0_46 (.A1(n_73), .A2(n_0_99), .B1(n_0_91), .B2(n_42), + .C1(n_11), .C2(n_0_90), .ZN(n_0_49)); + NAND2_X1_LVT i_0_47 (.A1(Illegal), .A2(CurrentPC[11]), .ZN(n_0_50)); + NAND2_X1_LVT i_0_45 (.A1(n_0_49), .A2(n_0_50), .ZN(JumpOrBranchPC[11])); + AOI222_X1_LVT i_0_43 (.A1(n_72), .A2(n_0_99), .B1(n_0_91), .B2(n_41), + .C1(n_10), .C2(n_0_90), .ZN(n_0_47)); + NAND2_X1_LVT i_0_44 (.A1(Illegal), .A2(CurrentPC[10]), .ZN(n_0_48)); + NAND2_X1_LVT i_0_42 (.A1(n_0_47), .A2(n_0_48), .ZN(JumpOrBranchPC[10])); + AOI222_X1_LVT i_0_40 (.A1(n_71), .A2(n_0_99), .B1(n_0_91), .B2(n_40), + .C1(n_9), .C2(n_0_90), .ZN(n_0_45)); + NAND2_X1_LVT i_0_41 (.A1(Illegal), .A2(CurrentPC[9]), .ZN(n_0_46)); + NAND2_X1_LVT i_0_39 (.A1(n_0_45), .A2(n_0_46), .ZN(JumpOrBranchPC[9])); + AOI222_X1_LVT i_0_37 (.A1(n_70), .A2(n_0_99), .B1(n_0_91), .B2(n_39), + .C1(n_8), .C2(n_0_90), .ZN(n_0_43)); + NAND2_X1_LVT i_0_38 (.A1(Illegal), .A2(CurrentPC[8]), .ZN(n_0_44)); + NAND2_X1_LVT i_0_36 (.A1(n_0_43), .A2(n_0_44), .ZN(JumpOrBranchPC[8])); + AOI222_X1_LVT i_0_34 (.A1(n_69), .A2(n_0_99), .B1(n_0_91), .B2(n_38), + .C1(n_7), .C2(n_0_90), .ZN(n_0_41)); + NAND2_X1_LVT i_0_35 (.A1(Illegal), .A2(CurrentPC[7]), .ZN(n_0_42)); + NAND2_X1_LVT i_0_33 (.A1(n_0_41), .A2(n_0_42), .ZN(JumpOrBranchPC[7])); + AOI222_X1_LVT i_0_31 (.A1(n_68), .A2(n_0_99), .B1(n_0_91), .B2(n_37), + .C1(n_6), .C2(n_0_90), .ZN(n_0_39)); + NAND2_X1_LVT i_0_32 (.A1(Illegal), .A2(CurrentPC[6]), .ZN(n_0_40)); + NAND2_X1_LVT i_0_30 (.A1(n_0_39), .A2(n_0_40), .ZN(JumpOrBranchPC[6])); + AOI222_X1_LVT i_0_28 (.A1(n_67), .A2(n_0_99), .B1(n_0_91), .B2(n_36), + .C1(n_5), .C2(n_0_90), .ZN(n_0_37)); + NAND2_X1_LVT i_0_29 (.A1(Illegal), .A2(CurrentPC[5]), .ZN(n_0_38)); + NAND2_X1_LVT i_0_27 (.A1(n_0_37), .A2(n_0_38), .ZN(JumpOrBranchPC[5])); + AOI222_X1_LVT i_0_25 (.A1(n_66), .A2(n_0_99), .B1(n_0_91), .B2(n_35), + .C1(n_4), .C2(n_0_90), .ZN(n_0_35)); + NAND2_X1_LVT i_0_26 (.A1(Illegal), .A2(CurrentPC[4]), .ZN(n_0_36)); + NAND2_X1_LVT i_0_24 (.A1(n_0_35), .A2(n_0_36), .ZN(JumpOrBranchPC[4])); + AOI222_X1_LVT i_0_22 (.A1(n_65), .A2(n_0_99), .B1(n_0_91), .B2(n_34), + .C1(n_3), .C2(n_0_90), .ZN(n_0_33)); + NAND2_X1_LVT i_0_23 (.A1(Illegal), .A2(CurrentPC[3]), .ZN(n_0_34)); + NAND2_X1_LVT i_0_21 (.A1(n_0_33), .A2(n_0_34), .ZN(JumpOrBranchPC[3])); + AOI222_X1_LVT i_0_19 (.A1(n_64), .A2(n_0_99), .B1(n_0_91), .B2(n_33), + .C1(n_2), .C2(n_0_90), .ZN(n_0_31)); + NAND2_X1_LVT i_0_20 (.A1(Illegal), .A2(CurrentPC[2]), .ZN(n_0_32)); + NAND2_X1_LVT i_0_18 (.A1(n_0_31), .A2(n_0_32), .ZN(JumpOrBranchPC[2])); + AOI222_X1_LVT i_0_16 (.A1(n_63), .A2(n_0_99), .B1(n_0_91), .B2(n_32), + .C1(n_1), .C2(n_0_90), .ZN(n_0_29)); + NAND2_X1_LVT i_0_17 (.A1(Illegal), .A2(CurrentPC[1]), .ZN(n_0_30)); + NAND2_X1_LVT i_0_15 (.A1(n_0_29), .A2(n_0_30), .ZN(JumpOrBranchPC[1])); + NOR2_X1_LVT i_0_112 (.A1(n_0_232), .A2(n_0_238), .ZN(n_0_94)); + OAI221_X1_LVT i_0_14 (.A(n_0_94), .B1(n_0_225), .B2(Instruction[2]), .C1( + Instruction[6]), .C2(n_0_239), .ZN(n_0_28)); + AND2_X1_LVT i_0_13 (.A1(n_0_28), .A2(CurrentPC[0]), .ZN(JumpOrBranchPC[0])); + NOR2_X1_LVT i_0_221 (.A1(Instruction[13]), .A2(Instruction[14]), .ZN(n_0_166)); + NOR3_X1_LVT i_0_293 (.A1(n_0_241), .A2(n_0_234), .A3(Instruction[3]), + .ZN(n_0_206)); + AND2_X1_LVT i_0_292 (.A1(n_0_206), .A2(n_0_244), .ZN(n_0_205)); + NOR3_X1_LVT i_0_330 (.A1(n_0_248), .A2(n_0_244), .A3(Instruction[4]), + .ZN(n_0_226)); + AOI21_X1_LVT i_0_121 (.A(n_0_205), .B1(n_0_226), .B2(n_0_237), .ZN(n_0_100)); + AND2_X1_LVT i_0_120 (.A1(Instruction[14]), .A2(n_0_100), .ZN(aluOp[2])); + OAI33_X1_LVT i_0_119 (.A1(n_0_205), .A2(n_0_247), .A3(n_0_224), .B1( + Instruction[2]), .B2(n_0_238), .B3(n_0_225), .ZN(aluOp[1])); + AOI22_X1_LVT i_0_117 (.A1(Instruction[12]), .A2(n_0_100), .B1(n_0_99), + .B2(Instruction[13]), .ZN(n_0_98)); + INV_X1_LVT i_0_116 (.A(n_0_98), .ZN(aluOp[0])); + OR2_X1_LVT i_0_327 (.A1(n_0_238), .A2(n_0_234), .ZN(n_0_223)); + NOR4_X1_LVT i_0_125 (.A1(Instruction[28]), .A2(Instruction[27]), .A3( + Instruction[26]), .A4(Instruction[25]), .ZN(n_0_103)); + INV_X1_LVT i_0_347 (.A(Instruction[30]), .ZN(n_0_242)); + NOR4_X1_LVT i_0_124 (.A1(Instruction[13]), .A2(n_0_242), .A3(Instruction[29]), + .A4(Instruction[31]), .ZN(n_0_102)); + NAND2_X1_LVT i_0_123 (.A1(n_0_103), .A2(n_0_102), .ZN(n_0_101)); + NOR3_X1_LVT i_0_127 (.A1(n_0_244), .A2(Instruction[12]), .A3(Instruction[14]), + .ZN(n_0_105)); + AOI21_X1_LVT i_0_126 (.A(n_0_105), .B1(Instruction[12]), .B2(Instruction[14]), + .ZN(n_0_104)); + NOR4_X1_LVT i_0_122 (.A1(n_0_223), .A2(n_0_101), .A3(n_0_104), .A4( + Instruction[2]), .ZN(aluNegAr)); + OR3_X1_LVT i_0_325 (.A1(n_0_228), .A2(Instruction[4]), .A3(Instruction[6]), + .ZN(n_0_222)); + NOR2_X1_LVT i_0_321 (.A1(n_0_222), .A2(Instruction[5]), .ZN(n_0_221)); + NOR3_X1_LVT i_0_224 (.A1(n_0_224), .A2(n_0_221), .A3(n_0_206), .ZN(n_0_169)); + NOR3_X1_LVT i_0_129 (.A1(n_0_234), .A2(Instruction[3]), .A3(Instruction[5]), + .ZN(n_0_106)); + NOR3_X1_LVT i_0_128 (.A1(n_0_226), .A2(n_0_169), .A3(n_0_106), .ZN(aluBypass)); + AOI22_X1_LVT i_0_223 (.A1(CurrentPC[31]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[31]), .ZN(n_0_168)); + NOR3_X1_LVT i_0_219 (.A1(n_0_247), .A2(n_0_222), .A3(Instruction[5]), + .ZN(n_0_164)); + AOI22_X1_LVT i_0_218 (.A1(RRs1[31]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[31]), .ZN(n_0_163)); + MUX2_X1_LVT i_0_222 (.A(RData[7]), .B(RData[15]), .S(Instruction[12]), + .Z(n_0_167)); + NAND3_X1_LVT i_0_220 (.A1(n_0_221), .A2(n_0_167), .A3(n_0_166), .ZN(n_0_165)); + NAND3_X1_LVT i_0_217 (.A1(n_0_168), .A2(n_0_163), .A3(n_0_165), .ZN(op1[31])); + AOI22_X1_LVT i_0_216 (.A1(RRs1[30]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[30]), .ZN(n_0_162)); + AOI22_X1_LVT i_0_215 (.A1(CurrentPC[30]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[30]), .ZN(n_0_161)); + NAND3_X1_LVT i_0_214 (.A1(n_0_162), .A2(n_0_161), .A3(n_0_165), .ZN(op1[30])); + AOI22_X1_LVT i_0_213 (.A1(RRs1[29]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[29]), .ZN(n_0_160)); + AOI22_X1_LVT i_0_212 (.A1(CurrentPC[29]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[29]), .ZN(n_0_159)); + NAND3_X1_LVT i_0_211 (.A1(n_0_160), .A2(n_0_159), .A3(n_0_165), .ZN(op1[29])); + AOI22_X1_LVT i_0_210 (.A1(RRs1[28]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[28]), .ZN(n_0_158)); + AOI22_X1_LVT i_0_209 (.A1(CurrentPC[28]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[28]), .ZN(n_0_157)); + NAND3_X1_LVT i_0_208 (.A1(n_0_158), .A2(n_0_157), .A3(n_0_165), .ZN(op1[28])); + AOI22_X1_LVT i_0_207 (.A1(RRs1[27]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[27]), .ZN(n_0_156)); + AOI22_X1_LVT i_0_206 (.A1(CurrentPC[27]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[27]), .ZN(n_0_155)); + NAND3_X1_LVT i_0_205 (.A1(n_0_156), .A2(n_0_155), .A3(n_0_165), .ZN(op1[27])); + AOI22_X1_LVT i_0_204 (.A1(RRs1[26]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[26]), .ZN(n_0_154)); + AOI22_X1_LVT i_0_203 (.A1(CurrentPC[26]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[26]), .ZN(n_0_153)); + NAND3_X1_LVT i_0_202 (.A1(n_0_154), .A2(n_0_153), .A3(n_0_165), .ZN(op1[26])); + AOI22_X1_LVT i_0_201 (.A1(RRs1[25]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[25]), .ZN(n_0_152)); + AOI22_X1_LVT i_0_200 (.A1(CurrentPC[25]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[25]), .ZN(n_0_151)); + NAND3_X1_LVT i_0_199 (.A1(n_0_152), .A2(n_0_151), .A3(n_0_165), .ZN(op1[25])); + AOI22_X1_LVT i_0_198 (.A1(RRs1[24]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[24]), .ZN(n_0_150)); + AOI22_X1_LVT i_0_197 (.A1(CurrentPC[24]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[24]), .ZN(n_0_149)); + NAND3_X1_LVT i_0_196 (.A1(n_0_150), .A2(n_0_149), .A3(n_0_165), .ZN(op1[24])); + AOI22_X1_LVT i_0_195 (.A1(RRs1[23]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[23]), .ZN(n_0_148)); + AOI22_X1_LVT i_0_194 (.A1(CurrentPC[23]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[23]), .ZN(n_0_147)); + NAND3_X1_LVT i_0_193 (.A1(n_0_148), .A2(n_0_147), .A3(n_0_165), .ZN(op1[23])); + AOI22_X1_LVT i_0_192 (.A1(RRs1[22]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[22]), .ZN(n_0_146)); + AOI22_X1_LVT i_0_191 (.A1(CurrentPC[22]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[22]), .ZN(n_0_145)); + NAND3_X1_LVT i_0_190 (.A1(n_0_146), .A2(n_0_145), .A3(n_0_165), .ZN(op1[22])); + AOI22_X1_LVT i_0_189 (.A1(RRs1[21]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[21]), .ZN(n_0_144)); + AOI22_X1_LVT i_0_188 (.A1(CurrentPC[21]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[21]), .ZN(n_0_143)); + NAND3_X1_LVT i_0_187 (.A1(n_0_144), .A2(n_0_143), .A3(n_0_165), .ZN(op1[21])); + AOI22_X1_LVT i_0_186 (.A1(RRs1[20]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[20]), .ZN(n_0_142)); + AOI22_X1_LVT i_0_185 (.A1(CurrentPC[20]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[20]), .ZN(n_0_141)); + NAND3_X1_LVT i_0_184 (.A1(n_0_142), .A2(n_0_141), .A3(n_0_165), .ZN(op1[20])); + AOI22_X1_LVT i_0_183 (.A1(RRs1[19]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[19]), .ZN(n_0_140)); + AOI22_X1_LVT i_0_182 (.A1(CurrentPC[19]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[19]), .ZN(n_0_139)); + NAND3_X1_LVT i_0_181 (.A1(n_0_140), .A2(n_0_139), .A3(n_0_165), .ZN(op1[19])); + AOI22_X1_LVT i_0_180 (.A1(RRs1[18]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[18]), .ZN(n_0_138)); + AOI22_X1_LVT i_0_179 (.A1(CurrentPC[18]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[18]), .ZN(n_0_137)); + NAND3_X1_LVT i_0_178 (.A1(n_0_138), .A2(n_0_137), .A3(n_0_165), .ZN(op1[18])); + AOI22_X1_LVT i_0_177 (.A1(RRs1[17]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[17]), .ZN(n_0_136)); + AOI22_X1_LVT i_0_176 (.A1(CurrentPC[17]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[17]), .ZN(n_0_135)); + NAND3_X1_LVT i_0_175 (.A1(n_0_136), .A2(n_0_135), .A3(n_0_165), .ZN(op1[17])); + AOI22_X1_LVT i_0_174 (.A1(RRs1[16]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[16]), .ZN(n_0_134)); + AOI22_X1_LVT i_0_173 (.A1(CurrentPC[16]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[16]), .ZN(n_0_133)); + NAND3_X1_LVT i_0_172 (.A1(n_0_134), .A2(n_0_133), .A3(n_0_165), .ZN(op1[16])); + AOI222_X1_LVT i_0_169 (.A1(CurrentPC[15]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[15]), .C1(n_0_169), .C2(RRs1[15]), .ZN(n_0_130)); + INV_X1_LVT i_0_353 (.A(Instruction[12]), .ZN(n_0_246)); + AOI211_X1_LVT i_0_171 (.A(Instruction[5]), .B(n_0_222), .C1(n_0_247), + .C2(n_0_246), .ZN(n_0_132)); + OAI211_X1_LVT i_0_170 (.A(RData[15]), .B(n_0_132), .C1(Instruction[13]), + .C2(Instruction[14]), .ZN(n_0_131)); + NAND3_X1_LVT i_0_168 (.A1(n_0_130), .A2(n_0_131), .A3(n_0_165), .ZN(op1[15])); + AOI22_X1_LVT i_0_167 (.A1(RRs1[14]), .A2(n_0_169), .B1(n_0_132), .B2( + RData[14]), .ZN(n_0_129)); + AOI22_X1_LVT i_0_166 (.A1(CurrentPC[14]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[14]), .ZN(n_0_128)); + NAND4_X1_LVT i_0_165 (.A1(n_0_221), .A2(n_0_246), .A3(RData[7]), .A4(n_0_166), + .ZN(n_0_127)); + NAND3_X1_LVT i_0_164 (.A1(n_0_129), .A2(n_0_128), .A3(n_0_127), .ZN(op1[14])); + AOI22_X1_LVT i_0_163 (.A1(RRs1[13]), .A2(n_0_169), .B1(n_0_132), .B2( + RData[13]), .ZN(n_0_126)); + AOI22_X1_LVT i_0_162 (.A1(CurrentPC[13]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[13]), .ZN(n_0_125)); + NAND3_X1_LVT i_0_161 (.A1(n_0_126), .A2(n_0_125), .A3(n_0_127), .ZN(op1[13])); + AOI22_X1_LVT i_0_160 (.A1(RRs1[12]), .A2(n_0_169), .B1(n_0_132), .B2( + RData[12]), .ZN(n_0_124)); + AOI22_X1_LVT i_0_159 (.A1(CurrentPC[12]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[12]), .ZN(n_0_123)); + NAND3_X1_LVT i_0_158 (.A1(n_0_124), .A2(n_0_123), .A3(n_0_127), .ZN(op1[12])); + AOI22_X1_LVT i_0_156 (.A1(CurrentPC[11]), .A2(n_0_224), .B1(n_0_132), + .B2(RData[11]), .ZN(n_0_121)); + NAND2_X1_LVT i_0_157 (.A1(RRs1[11]), .A2(n_0_169), .ZN(n_0_122)); + NAND3_X1_LVT i_0_155 (.A1(n_0_121), .A2(n_0_122), .A3(n_0_127), .ZN(op1[11])); + AOI22_X1_LVT i_0_153 (.A1(CurrentPC[10]), .A2(n_0_224), .B1(n_0_132), + .B2(RData[10]), .ZN(n_0_119)); + NAND2_X1_LVT i_0_154 (.A1(RRs1[10]), .A2(n_0_169), .ZN(n_0_120)); + NAND3_X1_LVT i_0_152 (.A1(n_0_119), .A2(n_0_120), .A3(n_0_127), .ZN(op1[10])); + AOI22_X1_LVT i_0_150 (.A1(CurrentPC[9]), .A2(n_0_224), .B1(n_0_132), .B2( + RData[9]), .ZN(n_0_117)); + NAND2_X1_LVT i_0_151 (.A1(RRs1[9]), .A2(n_0_169), .ZN(n_0_118)); + NAND3_X1_LVT i_0_149 (.A1(n_0_117), .A2(n_0_118), .A3(n_0_127), .ZN(op1[9])); + AOI22_X1_LVT i_0_147 (.A1(CurrentPC[8]), .A2(n_0_224), .B1(n_0_132), .B2( + RData[8]), .ZN(n_0_115)); + NAND2_X1_LVT i_0_148 (.A1(RRs1[8]), .A2(n_0_169), .ZN(n_0_116)); + NAND3_X1_LVT i_0_146 (.A1(n_0_115), .A2(n_0_116), .A3(n_0_127), .ZN(op1[8])); + AOI222_X1_LVT i_0_145 (.A1(CurrentPC[7]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[7]), .C1(n_0_169), .C2(RRs1[7]), .ZN(n_0_114)); + INV_X1_LVT i_0_144 (.A(n_0_114), .ZN(op1[7])); + AOI222_X1_LVT i_0_143 (.A1(CurrentPC[6]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[6]), .C1(n_0_169), .C2(RRs1[6]), .ZN(n_0_113)); + INV_X1_LVT i_0_142 (.A(n_0_113), .ZN(op1[6])); + AOI222_X1_LVT i_0_141 (.A1(CurrentPC[5]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[5]), .C1(n_0_169), .C2(RRs1[5]), .ZN(n_0_112)); + INV_X1_LVT i_0_140 (.A(n_0_112), .ZN(op1[5])); + AOI222_X1_LVT i_0_139 (.A1(CurrentPC[4]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[4]), .C1(n_0_169), .C2(RRs1[4]), .ZN(n_0_111)); + INV_X1_LVT i_0_138 (.A(n_0_111), .ZN(op1[4])); + AOI222_X1_LVT i_0_137 (.A1(CurrentPC[3]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[3]), .C1(n_0_169), .C2(RRs1[3]), .ZN(n_0_110)); + INV_X1_LVT i_0_136 (.A(n_0_110), .ZN(op1[3])); + AOI222_X1_LVT i_0_135 (.A1(CurrentPC[2]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[2]), .C1(n_0_169), .C2(RRs1[2]), .ZN(n_0_109)); + INV_X1_LVT i_0_134 (.A(n_0_109), .ZN(op1[2])); + AOI222_X1_LVT i_0_133 (.A1(CurrentPC[1]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[1]), .C1(n_0_169), .C2(RRs1[1]), .ZN(n_0_108)); + INV_X1_LVT i_0_132 (.A(n_0_108), .ZN(op1[1])); + AOI222_X1_LVT i_0_131 (.A1(CurrentPC[0]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[0]), .C1(n_0_169), .C2(RRs1[0]), .ZN(n_0_107)); + INV_X1_LVT i_0_130 (.A(n_0_107), .ZN(op1[0])); + NOR3_X1_LVT i_0_294 (.A1(n_0_223), .A2(Instruction[2]), .A3(Instruction[5]), + .ZN(n_0_207)); + NOR3_X1_LVT i_0_291 (.A1(n_0_224), .A2(n_0_207), .A3(n_0_205), .ZN(n_0_204)); + AOI22_X1_LVT i_0_289 (.A1(CurrentPC[31]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[31]), .ZN(n_0_202)); + NAND2_X1_LVT i_0_290 (.A1(Instruction[31]), .A2(n_0_207), .ZN(n_0_203)); + NAND2_X1_LVT i_0_288 (.A1(n_0_202), .A2(n_0_203), .ZN(op2[31])); + AOI22_X1_LVT i_0_287 (.A1(CurrentPC[30]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[30]), .ZN(n_0_201)); + NAND2_X1_LVT i_0_286 (.A1(n_0_201), .A2(n_0_203), .ZN(op2[30])); + AOI22_X1_LVT i_0_285 (.A1(CurrentPC[29]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[29]), .ZN(n_0_200)); + NAND2_X1_LVT i_0_284 (.A1(n_0_200), .A2(n_0_203), .ZN(op2[29])); + AOI22_X1_LVT i_0_283 (.A1(CurrentPC[28]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[28]), .ZN(n_0_199)); + NAND2_X1_LVT i_0_282 (.A1(n_0_199), .A2(n_0_203), .ZN(op2[28])); + AOI22_X1_LVT i_0_281 (.A1(CurrentPC[27]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[27]), .ZN(n_0_198)); + NAND2_X1_LVT i_0_280 (.A1(n_0_198), .A2(n_0_203), .ZN(op2[27])); + AOI22_X1_LVT i_0_279 (.A1(CurrentPC[26]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[26]), .ZN(n_0_197)); + NAND2_X1_LVT i_0_278 (.A1(n_0_197), .A2(n_0_203), .ZN(op2[26])); + AOI22_X1_LVT i_0_277 (.A1(CurrentPC[25]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[25]), .ZN(n_0_196)); + NAND2_X1_LVT i_0_276 (.A1(n_0_196), .A2(n_0_203), .ZN(op2[25])); + AOI22_X1_LVT i_0_275 (.A1(CurrentPC[24]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[24]), .ZN(n_0_195)); + NAND2_X1_LVT i_0_274 (.A1(n_0_195), .A2(n_0_203), .ZN(op2[24])); + AOI22_X1_LVT i_0_273 (.A1(CurrentPC[23]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[23]), .ZN(n_0_194)); + NAND2_X1_LVT i_0_272 (.A1(n_0_194), .A2(n_0_203), .ZN(op2[23])); + AOI22_X1_LVT i_0_271 (.A1(CurrentPC[22]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[22]), .ZN(n_0_193)); + NAND2_X1_LVT i_0_270 (.A1(n_0_193), .A2(n_0_203), .ZN(op2[22])); + AOI22_X1_LVT i_0_269 (.A1(CurrentPC[21]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[21]), .ZN(n_0_192)); + NAND2_X1_LVT i_0_268 (.A1(n_0_192), .A2(n_0_203), .ZN(op2[21])); + AOI22_X1_LVT i_0_267 (.A1(CurrentPC[20]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[20]), .ZN(n_0_191)); + NAND2_X1_LVT i_0_266 (.A1(n_0_191), .A2(n_0_203), .ZN(op2[20])); + AOI22_X1_LVT i_0_265 (.A1(CurrentPC[19]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[19]), .ZN(n_0_190)); + NAND2_X1_LVT i_0_264 (.A1(n_0_190), .A2(n_0_203), .ZN(op2[19])); + AOI22_X1_LVT i_0_263 (.A1(CurrentPC[18]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[18]), .ZN(n_0_189)); + NAND2_X1_LVT i_0_262 (.A1(n_0_189), .A2(n_0_203), .ZN(op2[18])); + AOI22_X1_LVT i_0_261 (.A1(CurrentPC[17]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[17]), .ZN(n_0_188)); + NAND2_X1_LVT i_0_260 (.A1(n_0_188), .A2(n_0_203), .ZN(op2[17])); + AOI22_X1_LVT i_0_259 (.A1(CurrentPC[16]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[16]), .ZN(n_0_187)); + NAND2_X1_LVT i_0_258 (.A1(n_0_187), .A2(n_0_203), .ZN(op2[16])); + AOI22_X1_LVT i_0_257 (.A1(CurrentPC[15]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[15]), .ZN(n_0_186)); + NAND2_X1_LVT i_0_256 (.A1(n_0_186), .A2(n_0_203), .ZN(op2[15])); + AOI22_X1_LVT i_0_255 (.A1(CurrentPC[14]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[14]), .ZN(n_0_185)); + NAND2_X1_LVT i_0_254 (.A1(n_0_185), .A2(n_0_203), .ZN(op2[14])); + AOI22_X1_LVT i_0_253 (.A1(CurrentPC[13]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[13]), .ZN(n_0_184)); + NAND2_X1_LVT i_0_252 (.A1(n_0_184), .A2(n_0_203), .ZN(op2[13])); + AOI22_X1_LVT i_0_251 (.A1(CurrentPC[12]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[12]), .ZN(n_0_183)); + NAND2_X1_LVT i_0_250 (.A1(n_0_183), .A2(n_0_203), .ZN(op2[12])); + AOI22_X1_LVT i_0_249 (.A1(CurrentPC[11]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[11]), .ZN(n_0_182)); + NAND2_X1_LVT i_0_248 (.A1(n_0_182), .A2(n_0_203), .ZN(op2[11])); + AOI222_X1_LVT i_0_247 (.A1(Instruction[30]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[10]), .C1(n_0_204), .C2(RRs2[10]), .ZN(n_0_181)); + INV_X1_LVT i_0_246 (.A(n_0_181), .ZN(op2[10])); + AOI222_X1_LVT i_0_245 (.A1(Instruction[29]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[9]), .C1(n_0_204), .C2(RRs2[9]), .ZN(n_0_180)); + INV_X1_LVT i_0_244 (.A(n_0_180), .ZN(op2[9])); + AOI222_X1_LVT i_0_243 (.A1(Instruction[28]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[8]), .C1(n_0_204), .C2(RRs2[8]), .ZN(n_0_179)); + INV_X1_LVT i_0_242 (.A(n_0_179), .ZN(op2[8])); + AOI222_X1_LVT i_0_241 (.A1(Instruction[27]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[7]), .C1(n_0_204), .C2(RRs2[7]), .ZN(n_0_178)); + INV_X1_LVT i_0_240 (.A(n_0_178), .ZN(op2[7])); + AOI222_X1_LVT i_0_239 (.A1(Instruction[26]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[6]), .C1(n_0_204), .C2(RRs2[6]), .ZN(n_0_177)); + INV_X1_LVT i_0_238 (.A(n_0_177), .ZN(op2[6])); + AOI222_X1_LVT i_0_237 (.A1(Instruction[25]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[5]), .C1(n_0_204), .C2(RRs2[5]), .ZN(n_0_176)); + INV_X1_LVT i_0_236 (.A(n_0_176), .ZN(op2[5])); + AOI222_X1_LVT i_0_235 (.A1(Instruction[24]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[4]), .C1(n_0_204), .C2(RRs2[4]), .ZN(n_0_175)); + INV_X1_LVT i_0_234 (.A(n_0_175), .ZN(op2[4])); + AOI222_X1_LVT i_0_233 (.A1(Instruction[23]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[3]), .C1(n_0_204), .C2(RRs2[3]), .ZN(n_0_174)); + INV_X1_LVT i_0_232 (.A(n_0_174), .ZN(op2[3])); + AOI22_X1_LVT i_0_230 (.A1(Instruction[22]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[2]), .ZN(n_0_172)); + OAI21_X1_LVT i_0_231 (.A(RRs2[2]), .B1(n_0_223), .B2(Instruction[5]), + .ZN(n_0_173)); + NAND3_X1_LVT i_0_229 (.A1(n_0_172), .A2(n_0_173), .A3(n_0_249), .ZN(op2[2])); + AOI222_X1_LVT i_0_228 (.A1(Instruction[21]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[1]), .C1(n_0_204), .C2(RRs2[1]), .ZN(n_0_171)); + INV_X1_LVT i_0_227 (.A(n_0_171), .ZN(op2[1])); + AOI222_X1_LVT i_0_226 (.A1(Instruction[20]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[0]), .C1(n_0_204), .C2(RRs2[0]), .ZN(n_0_170)); + INV_X1_LVT i_0_225 (.A(n_0_170), .ZN(op2[0])); + alu theALU (.aluOp(aluOp), .aluNegAr(aluNegAr), .aluBypass(aluBypass), + .op1(op1), .op2(op2), .result(WRd), .eqFlag(eqFlag)); + XNOR2_X1_LVT i_0_115 (.A(Instruction[12]), .B(eqFlag), .ZN(n_0_97)); + XNOR2_X1_LVT i_0_114 (.A(Instruction[12]), .B(WRd[0]), .ZN(n_0_96)); + AOI22_X1_LVT i_0_113 (.A1(n_0_166), .A2(n_0_97), .B1(n_0_96), .B2( + Instruction[14]), .ZN(n_0_95)); + AOI22_X1_LVT i_0_111 (.A1(Instruction[6]), .A2(n_0_95), .B1(Instruction[2]), + .B2(n_0_245), .ZN(n_0_93)); + NAND2_X1_LVT i_0_110 (.A1(n_0_94), .A2(n_0_93), .ZN(JumpOrBranch)); + INV_X1_LVT i_0_349 (.A(Instruction[31]), .ZN(n_0_0)); + INV_X1_LVT i_0_348 (.A(RRs1[12]), .ZN(n_0_1)); + HA_X1_LVT i_0_0 (.A(Instruction[7]), .B(RRs1[0]), .CO(n_0_2), .S(n_0_15)); + FA_X1_LVT i_0_1 (.A(Instruction[8]), .B(RRs1[1]), .CI(n_0_2), .CO(n_0_3), + .S(n_0_16)); + FA_X1_LVT i_0_2 (.A(Instruction[9]), .B(RRs1[2]), .CI(n_0_3), .CO(n_0_4), + .S(n_0_17)); + FA_X1_LVT i_0_3 (.A(Instruction[10]), .B(RRs1[3]), .CI(n_0_4), .CO(n_0_5), + .S(n_0_18)); + FA_X1_LVT i_0_4 (.A(Instruction[11]), .B(RRs1[4]), .CI(n_0_5), .CO(n_0_6), + .S(n_0_19)); + FA_X1_LVT i_0_5 (.A(Instruction[25]), .B(RRs1[5]), .CI(n_0_6), .CO(n_0_7), + .S(n_0_20)); + FA_X1_LVT i_0_6 (.A(Instruction[26]), .B(RRs1[6]), .CI(n_0_7), .CO(n_0_8), + .S(n_0_21)); + FA_X1_LVT i_0_7 (.A(Instruction[27]), .B(RRs1[7]), .CI(n_0_8), .CO(n_0_9), + .S(n_0_22)); + FA_X1_LVT i_0_8 (.A(Instruction[28]), .B(RRs1[8]), .CI(n_0_9), .CO(n_0_10), + .S(n_0_23)); + FA_X1_LVT i_0_9 (.A(Instruction[29]), .B(RRs1[9]), .CI(n_0_10), .CO(n_0_11), + .S(n_0_24)); + FA_X1_LVT i_0_10 (.A(Instruction[30]), .B(RRs1[10]), .CI(n_0_11), .CO(n_0_12), + .S(n_0_25)); + FA_X1_LVT i_0_11 (.A(RRs1[11]), .B(Instruction[31]), .CI(n_0_12), .CO(n_0_13), + .S(n_0_26)); + FA_X1_LVT i_0_12 (.A(n_0_0), .B(n_0_1), .CI(n_0_13), .CO(n_0_14), .S(n_0_27)); + NOR2_X1_LVT i_0_322 (.A1(n_0_244), .A2(n_0_222), .ZN(WrMem)); + AOI22_X1_LVT i_0_320 (.A1(n_0_27), .A2(WrMem), .B1(n_0_221), .B2(n_12), + .ZN(n_0_220)); + INV_X1_LVT i_0_319 (.A(n_0_220), .ZN(DAddr[12])); + AOI22_X1_LVT i_0_318 (.A1(n_0_26), .A2(WrMem), .B1(n_0_221), .B2(n_11), + .ZN(n_0_219)); + INV_X1_LVT i_0_317 (.A(n_0_219), .ZN(DAddr[11])); + AOI22_X1_LVT i_0_316 (.A1(n_0_25), .A2(WrMem), .B1(n_0_221), .B2(n_10), + .ZN(n_0_218)); + INV_X1_LVT i_0_315 (.A(n_0_218), .ZN(DAddr[10])); + AOI22_X1_LVT i_0_314 (.A1(n_0_24), .A2(WrMem), .B1(n_0_221), .B2(n_9), + .ZN(n_0_217)); + INV_X1_LVT i_0_313 (.A(n_0_217), .ZN(DAddr[9])); + AOI22_X1_LVT i_0_312 (.A1(n_0_23), .A2(WrMem), .B1(n_0_221), .B2(n_8), + .ZN(n_0_216)); + INV_X1_LVT i_0_311 (.A(n_0_216), .ZN(DAddr[8])); + AOI22_X1_LVT i_0_310 (.A1(n_0_22), .A2(WrMem), .B1(n_0_221), .B2(n_7), + .ZN(n_0_215)); + INV_X1_LVT i_0_309 (.A(n_0_215), .ZN(DAddr[7])); + AOI22_X1_LVT i_0_308 (.A1(n_0_21), .A2(WrMem), .B1(n_0_221), .B2(n_6), + .ZN(n_0_214)); + INV_X1_LVT i_0_307 (.A(n_0_214), .ZN(DAddr[6])); + AOI22_X1_LVT i_0_306 (.A1(n_0_20), .A2(WrMem), .B1(n_0_221), .B2(n_5), + .ZN(n_0_213)); + INV_X1_LVT i_0_305 (.A(n_0_213), .ZN(DAddr[5])); + AOI22_X1_LVT i_0_304 (.A1(n_0_19), .A2(WrMem), .B1(n_0_221), .B2(n_4), + .ZN(n_0_212)); + INV_X1_LVT i_0_303 (.A(n_0_212), .ZN(DAddr[4])); + AOI22_X1_LVT i_0_302 (.A1(n_0_18), .A2(WrMem), .B1(n_0_221), .B2(n_3), + .ZN(n_0_211)); + INV_X1_LVT i_0_301 (.A(n_0_211), .ZN(DAddr[3])); + AOI22_X1_LVT i_0_300 (.A1(n_0_17), .A2(WrMem), .B1(n_0_221), .B2(n_2), + .ZN(n_0_210)); + INV_X1_LVT i_0_299 (.A(n_0_210), .ZN(DAddr[2])); + AOI22_X1_LVT i_0_298 (.A1(n_0_16), .A2(WrMem), .B1(n_0_221), .B2(n_1), + .ZN(n_0_209)); + INV_X1_LVT i_0_297 (.A(n_0_209), .ZN(DAddr[1])); + AOI22_X1_LVT i_0_296 (.A1(n_0_15), .A2(WrMem), .B1(n_0_221), .B2(n_0), + .ZN(n_0_208)); + INV_X1_LVT i_0_295 (.A(n_0_208), .ZN(DAddr[0])); + OR2_X1_LVT i_0_324 (.A1(n_0_222), .A2(Instruction[13]), .ZN(DWidth[1])); + NOR2_X1_LVT i_0_323 (.A1(n_0_246), .A2(n_0_222), .ZN(DWidth[0])); + NAND3_X1_LVT i_0_331 (.A1(n_0_248), .A2(n_0_244), .A3(n_0_236), .ZN(n_0_227)); + OAI211_X1_LVT i_0_326 (.A(n_0_249), .B(n_0_223), .C1(n_0_228), .C2(n_0_227), + .ZN(WrReg)); +endmodule + +module cpu(led, btn, clk_25mhz, scan_en, SI_1, SO_1, SI_2, SO_2, SI_3, SO_3, + SI_4, SO_4); + output [7:0]led; + input [6:0]btn; + input clk_25mhz; + input scan_en; + input SI_1; + output SO_1; + input SI_2; + output SO_2; + input SI_3; + output SO_3; + input SI_4; + output SO_4; + + wire [31:0]Instruction; + wire [31:0]RData; + wire [31:0]RRs2; + wire [31:0]RRs1; + wire WrReg; + wire [31:0]WRd; + wire [1:0]DWidth; + wire [31:0]DAddr; + wire JumpOrBranch; + wire [31:0]JumpOrBranchPC; + wire thePC_n_1; + wire thePC_i_0_n_0; + wire thePC_n_2; + wire thePC_i_0_n_1; + wire thePC_n_3; + wire thePC_i_0_n_2; + wire thePC_n_4; + wire thePC_i_0_n_3; + wire thePC_n_5; + wire thePC_i_0_n_4; + wire thePC_n_6; + wire thePC_i_0_n_5; + wire thePC_n_7; + wire thePC_i_0_n_6; + wire thePC_n_8; + wire thePC_i_0_n_7; + wire thePC_n_9; + wire thePC_i_0_n_8; + wire thePC_n_10; + wire thePC_i_0_n_9; + wire thePC_n_11; + wire thePC_i_0_n_10; + wire thePC_n_12; + wire thePC_i_0_n_11; + wire thePC_n_13; + wire thePC_i_0_n_12; + wire thePC_n_14; + wire thePC_i_0_n_13; + wire thePC_n_15; + wire thePC_i_0_n_14; + wire thePC_n_16; + wire thePC_i_0_n_15; + wire thePC_n_17; + wire thePC_i_0_n_16; + wire thePC_n_18; + wire thePC_i_0_n_17; + wire thePC_n_19; + wire thePC_i_0_n_18; + wire thePC_n_20; + wire thePC_i_0_n_19; + wire thePC_n_21; + wire thePC_i_0_n_20; + wire thePC_n_22; + wire thePC_i_0_n_21; + wire thePC_n_23; + wire thePC_i_0_n_22; + wire thePC_n_24; + wire thePC_i_0_n_23; + wire thePC_n_25; + wire thePC_i_0_n_24; + wire thePC_n_26; + wire thePC_i_0_n_25; + wire thePC_n_27; + wire thePC_i_0_n_26; + wire thePC_n_28; + wire thePC_i_0_n_27; + wire thePC_n_29; + wire thePC_n_0; + wire [31:0]CurrentPC; + wire thePC_n_30; + wire n_0_0_0; + wire thePC_n_31; + wire n_0_0_1; + wire thePC_n_32; + wire thePC_n_33; + wire thePC_n_34; + wire thePC_n_35; + wire thePC_n_36; + wire thePC_n_37; + wire thePC_n_38; + wire thePC_n_39; + wire thePC_n_40; + wire thePC_n_41; + wire thePC_n_42; + wire thePC_n_43; + wire n_0_0_2; + wire thePC_n_44; + wire n_0_0_3; + wire thePC_n_45; + wire n_0_0_4; + wire thePC_n_46; + wire n_0_0_5; + wire thePC_n_47; + wire n_0_0_6; + wire thePC_n_48; + wire n_0_0_7; + wire thePC_n_49; + wire n_0_0_8; + wire thePC_n_50; + wire n_0_0_9; + wire thePC_n_51; + wire n_0_0_10; + wire thePC_n_52; + wire n_0_0_11; + wire thePC_n_53; + wire n_0_0_12; + wire thePC_n_54; + wire n_0_0_13; + wire thePC_n_55; + wire n_0_0_14; + wire thePC_n_56; + wire n_0_0_15; + wire thePC_n_57; + wire n_0_0_16; + wire thePC_n_58; + wire n_0_0_17; + wire thePC_n_59; + wire n_0_0_18; + wire thePC_n_60; + wire n_0_0_19; + wire thePC_n_61; + wire n_0_0_20; + wire n_0_0_21; + wire n_0_0_22; + wire [31:0]NextPC; + wire reset; + + AND2_X1_LVT i_0_0_54 (.A1(JumpOrBranch), .A2(btn[0]), .ZN(n_0_0_22)); + INV_X1_LVT i_0_0_66 (.A(btn[0]), .ZN(reset)); + NOR2_X1_LVT i_0_0_53 (.A1(reset), .A2(JumpOrBranch), .ZN(n_0_0_21)); + AOI22_X1_LVT i_0_0_50 (.A1(JumpOrBranchPC[30]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_28), .ZN(n_0_0_19)); + INV_X1_LVT i_0_0_49 (.A(n_0_0_19), .ZN(thePC_n_60)); + SDFF_X1_LVT \thePC_CurrentPC_reg[30] (.D(thePC_n_60), .SE(1'b0), .SI( + CurrentPC[30]), .CK(clk_25mhz), .Q(CurrentPC[30]), .QN()); + AOI22_X1_LVT i_0_0_48 (.A1(JumpOrBranchPC[29]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_27), .ZN(n_0_0_18)); + INV_X1_LVT i_0_0_47 (.A(n_0_0_18), .ZN(thePC_n_59)); + SDFF_X1_LVT \thePC_CurrentPC_reg[29] (.D(thePC_n_59), .SE(1'b0), .SI( + CurrentPC[29]), .CK(clk_25mhz), .Q(CurrentPC[29]), .QN()); + AOI22_X1_LVT i_0_0_46 (.A1(JumpOrBranchPC[28]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_26), .ZN(n_0_0_17)); + INV_X1_LVT i_0_0_45 (.A(n_0_0_17), .ZN(thePC_n_58)); + SDFF_X1_LVT \thePC_CurrentPC_reg[28] (.D(thePC_n_58), .SE(1'b0), .SI( + CurrentPC[28]), .CK(clk_25mhz), .Q(CurrentPC[28]), .QN()); + AOI22_X1_LVT i_0_0_44 (.A1(JumpOrBranchPC[27]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_25), .ZN(n_0_0_16)); + INV_X1_LVT i_0_0_43 (.A(n_0_0_16), .ZN(thePC_n_57)); + SDFF_X1_LVT \thePC_CurrentPC_reg[27] (.D(thePC_n_57), .SE(1'b0), .SI( + CurrentPC[27]), .CK(clk_25mhz), .Q(CurrentPC[27]), .QN()); + AOI22_X1_LVT i_0_0_42 (.A1(JumpOrBranchPC[26]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_24), .ZN(n_0_0_15)); + INV_X1_LVT i_0_0_41 (.A(n_0_0_15), .ZN(thePC_n_56)); + SDFF_X1_LVT \thePC_CurrentPC_reg[26] (.D(thePC_n_56), .SE(1'b0), .SI( + CurrentPC[26]), .CK(clk_25mhz), .Q(CurrentPC[26]), .QN()); + AOI22_X1_LVT i_0_0_40 (.A1(JumpOrBranchPC[25]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_23), .ZN(n_0_0_14)); + INV_X1_LVT i_0_0_39 (.A(n_0_0_14), .ZN(thePC_n_55)); + SDFF_X1_LVT \thePC_CurrentPC_reg[25] (.D(thePC_n_55), .SE(1'b0), .SI( + CurrentPC[25]), .CK(clk_25mhz), .Q(CurrentPC[25]), .QN()); + AOI22_X1_LVT i_0_0_38 (.A1(JumpOrBranchPC[24]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_22), .ZN(n_0_0_13)); + INV_X1_LVT i_0_0_37 (.A(n_0_0_13), .ZN(thePC_n_54)); + SDFF_X1_LVT \thePC_CurrentPC_reg[24] (.D(thePC_n_54), .SE(1'b0), .SI( + CurrentPC[24]), .CK(clk_25mhz), .Q(CurrentPC[24]), .QN()); + AOI22_X1_LVT i_0_0_36 (.A1(JumpOrBranchPC[23]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_21), .ZN(n_0_0_12)); + INV_X1_LVT i_0_0_35 (.A(n_0_0_12), .ZN(thePC_n_53)); + SDFF_X1_LVT \thePC_CurrentPC_reg[23] (.D(thePC_n_53), .SE(1'b0), .SI( + CurrentPC[23]), .CK(clk_25mhz), .Q(CurrentPC[23]), .QN()); + AOI22_X1_LVT i_0_0_34 (.A1(JumpOrBranchPC[22]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_20), .ZN(n_0_0_11)); + INV_X1_LVT i_0_0_33 (.A(n_0_0_11), .ZN(thePC_n_52)); + SDFF_X1_LVT \thePC_CurrentPC_reg[22] (.D(thePC_n_52), .SE(1'b0), .SI( + CurrentPC[22]), .CK(clk_25mhz), .Q(CurrentPC[22]), .QN()); + AOI22_X1_LVT i_0_0_32 (.A1(JumpOrBranchPC[21]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_19), .ZN(n_0_0_10)); + INV_X1_LVT i_0_0_31 (.A(n_0_0_10), .ZN(thePC_n_51)); + SDFF_X1_LVT \thePC_CurrentPC_reg[21] (.D(thePC_n_51), .SE(1'b0), .SI( + CurrentPC[21]), .CK(clk_25mhz), .Q(CurrentPC[21]), .QN()); + AOI22_X1_LVT i_0_0_30 (.A1(JumpOrBranchPC[20]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_18), .ZN(n_0_0_9)); + INV_X1_LVT i_0_0_29 (.A(n_0_0_9), .ZN(thePC_n_50)); + SDFF_X1_LVT \thePC_CurrentPC_reg[20] (.D(thePC_n_50), .SE(1'b0), .SI( + CurrentPC[20]), .CK(clk_25mhz), .Q(CurrentPC[20]), .QN()); + AOI22_X1_LVT i_0_0_28 (.A1(JumpOrBranchPC[19]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_17), .ZN(n_0_0_8)); + INV_X1_LVT i_0_0_27 (.A(n_0_0_8), .ZN(thePC_n_49)); + SDFF_X1_LVT \thePC_CurrentPC_reg[19] (.D(thePC_n_49), .SE(1'b0), .SI( + CurrentPC[19]), .CK(clk_25mhz), .Q(CurrentPC[19]), .QN()); + AOI22_X1_LVT i_0_0_26 (.A1(JumpOrBranchPC[18]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_16), .ZN(n_0_0_7)); + INV_X1_LVT i_0_0_25 (.A(n_0_0_7), .ZN(thePC_n_48)); + SDFF_X1_LVT \thePC_CurrentPC_reg[18] (.D(thePC_n_48), .SE(1'b0), .SI( + CurrentPC[18]), .CK(clk_25mhz), .Q(CurrentPC[18]), .QN()); + AOI22_X1_LVT i_0_0_24 (.A1(JumpOrBranchPC[17]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_15), .ZN(n_0_0_6)); + INV_X1_LVT i_0_0_23 (.A(n_0_0_6), .ZN(thePC_n_47)); + SDFF_X1_LVT \thePC_CurrentPC_reg[17] (.D(thePC_n_47), .SE(1'b0), .SI( + CurrentPC[17]), .CK(clk_25mhz), .Q(CurrentPC[17]), .QN()); + AOI22_X1_LVT i_0_0_22 (.A1(JumpOrBranchPC[16]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_14), .ZN(n_0_0_5)); + INV_X1_LVT i_0_0_21 (.A(n_0_0_5), .ZN(thePC_n_46)); + SDFF_X1_LVT \thePC_CurrentPC_reg[16] (.D(thePC_n_46), .SE(1'b0), .SI( + CurrentPC[16]), .CK(clk_25mhz), .Q(CurrentPC[16]), .QN()); + AOI22_X1_LVT i_0_0_20 (.A1(JumpOrBranchPC[15]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_13), .ZN(n_0_0_4)); + INV_X1_LVT i_0_0_19 (.A(n_0_0_4), .ZN(thePC_n_45)); + SDFF_X1_LVT \thePC_CurrentPC_reg[15] (.D(thePC_n_45), .SE(1'b0), .SI( + CurrentPC[15]), .CK(clk_25mhz), .Q(CurrentPC[15]), .QN()); + AOI22_X1_LVT i_0_0_18 (.A1(JumpOrBranchPC[14]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_12), .ZN(n_0_0_3)); + INV_X1_LVT i_0_0_17 (.A(n_0_0_3), .ZN(thePC_n_44)); + SDFF_X1_LVT \thePC_CurrentPC_reg[14] (.D(thePC_n_44), .SE(1'b0), .SI( + CurrentPC[14]), .CK(clk_25mhz), .Q(CurrentPC[14]), .QN()); + AOI22_X1_LVT i_0_0_16 (.A1(JumpOrBranchPC[13]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_11), .ZN(n_0_0_2)); + INV_X1_LVT i_0_0_15 (.A(n_0_0_2), .ZN(thePC_n_43)); + SDFF_X1_LVT \thePC_CurrentPC_reg[13] (.D(thePC_n_43), .SE(1'b0), .SI( + CurrentPC[13]), .CK(clk_25mhz), .Q(CurrentPC[13]), .QN()); + MUX2_X1_LVT i_0_0_65 (.A(thePC_n_10), .B(JumpOrBranchPC[12]), .S(JumpOrBranch), + .Z(NextPC[12])); + AND2_X1_LVT i_0_0_14 (.A1(NextPC[12]), .A2(btn[0]), .ZN(thePC_n_42)); + SDFF_X1_LVT \thePC_CurrentPC_reg[12] (.D(thePC_n_42), .SE(1'b0), .SI( + CurrentPC[12]), .CK(clk_25mhz), .Q(CurrentPC[12]), .QN()); + MUX2_X1_LVT i_0_0_64 (.A(thePC_n_9), .B(JumpOrBranchPC[11]), .S(JumpOrBranch), + .Z(NextPC[11])); + AND2_X1_LVT i_0_0_13 (.A1(NextPC[11]), .A2(btn[0]), .ZN(thePC_n_41)); + SDFF_X1_LVT \thePC_CurrentPC_reg[11] (.D(thePC_n_41), .SE(1'b0), .SI( + CurrentPC[11]), .CK(clk_25mhz), .Q(CurrentPC[11]), .QN()); + MUX2_X1_LVT i_0_0_63 (.A(thePC_n_8), .B(JumpOrBranchPC[10]), .S(JumpOrBranch), + .Z(NextPC[10])); + AND2_X1_LVT i_0_0_12 (.A1(NextPC[10]), .A2(btn[0]), .ZN(thePC_n_40)); + SDFF_X1_LVT \thePC_CurrentPC_reg[10] (.D(thePC_n_40), .SE(1'b0), .SI( + CurrentPC[10]), .CK(clk_25mhz), .Q(CurrentPC[10]), .QN()); + MUX2_X1_LVT i_0_0_62 (.A(thePC_n_7), .B(JumpOrBranchPC[9]), .S(JumpOrBranch), + .Z(NextPC[9])); + AND2_X1_LVT i_0_0_11 (.A1(NextPC[9]), .A2(btn[0]), .ZN(thePC_n_39)); + SDFF_X1_LVT \thePC_CurrentPC_reg[9] (.D(thePC_n_39), .SE(1'b0), .SI( + CurrentPC[9]), .CK(clk_25mhz), .Q(CurrentPC[9]), .QN()); + MUX2_X1_LVT i_0_0_61 (.A(thePC_n_6), .B(JumpOrBranchPC[8]), .S(JumpOrBranch), + .Z(NextPC[8])); + AND2_X1_LVT i_0_0_10 (.A1(NextPC[8]), .A2(btn[0]), .ZN(thePC_n_38)); + SDFF_X1_LVT \thePC_CurrentPC_reg[8] (.D(thePC_n_38), .SE(1'b0), .SI( + CurrentPC[8]), .CK(clk_25mhz), .Q(CurrentPC[8]), .QN()); + AND2_X1_LVT i_0_0_9 (.A1(led[7]), .A2(btn[0]), .ZN(thePC_n_37)); + SDFF_X1_LVT \thePC_CurrentPC_reg[7] (.D(thePC_n_37), .SE(1'b0), .SI( + CurrentPC[7]), .CK(clk_25mhz), .Q(CurrentPC[7]), .QN()); + MUX2_X1_LVT i_0_0_59 (.A(thePC_n_4), .B(JumpOrBranchPC[6]), .S(JumpOrBranch), + .Z(led[6])); + AND2_X1_LVT i_0_0_8 (.A1(led[6]), .A2(btn[0]), .ZN(thePC_n_36)); + SDFF_X1_LVT \thePC_CurrentPC_reg[6] (.D(thePC_n_36), .SE(1'b0), .SI( + CurrentPC[6]), .CK(clk_25mhz), .Q(CurrentPC[6]), .QN()); + MUX2_X1_LVT i_0_0_58 (.A(thePC_n_3), .B(JumpOrBranchPC[5]), .S(JumpOrBranch), + .Z(led[5])); + AND2_X1_LVT i_0_0_7 (.A1(led[5]), .A2(btn[0]), .ZN(thePC_n_35)); + SDFF_X1_LVT \thePC_CurrentPC_reg[5] (.D(thePC_n_35), .SE(1'b0), .SI( + CurrentPC[5]), .CK(clk_25mhz), .Q(CurrentPC[5]), .QN()); + MUX2_X1_LVT i_0_0_57 (.A(thePC_n_2), .B(JumpOrBranchPC[4]), .S(JumpOrBranch), + .Z(led[4])); + AND2_X1_LVT i_0_0_6 (.A1(led[4]), .A2(btn[0]), .ZN(thePC_n_34)); + SDFF_X1_LVT \thePC_CurrentPC_reg[4] (.D(thePC_n_34), .SE(1'b0), .SI( + CurrentPC[4]), .CK(clk_25mhz), .Q(CurrentPC[4]), .QN()); + MUX2_X1_LVT i_0_0_56 (.A(thePC_n_1), .B(JumpOrBranchPC[3]), .S(JumpOrBranch), + .Z(led[3])); + AND2_X1_LVT i_0_0_5 (.A1(led[3]), .A2(btn[0]), .ZN(thePC_n_33)); + SDFF_X1_LVT \thePC_CurrentPC_reg[3] (.D(thePC_n_33), .SE(1'b0), .SI( + CurrentPC[3]), .CK(clk_25mhz), .Q(CurrentPC[3]), .QN()); + INV_X1_LVT thePC_i_0_29 (.A(CurrentPC[2]), .ZN(thePC_n_0)); + MUX2_X1_LVT i_0_0_55 (.A(thePC_n_0), .B(JumpOrBranchPC[2]), .S(JumpOrBranch), + .Z(led[2])); + AND2_X1_LVT i_0_0_4 (.A1(led[2]), .A2(btn[0]), .ZN(thePC_n_32)); + SDFF_X1_LVT \thePC_CurrentPC_reg[2] (.D(thePC_n_32), .SE(1'b0), .SI( + CurrentPC[2]), .CK(clk_25mhz), .Q(CurrentPC[2]), .QN()); + HA_X1_LVT thePC_i_0_0 (.A(CurrentPC[3]), .B(CurrentPC[2]), .CO(thePC_i_0_n_0), + .S(thePC_n_1)); + HA_X1_LVT thePC_i_0_1 (.A(CurrentPC[4]), .B(thePC_i_0_n_0), .CO(thePC_i_0_n_1), + .S(thePC_n_2)); + HA_X1_LVT thePC_i_0_2 (.A(CurrentPC[5]), .B(thePC_i_0_n_1), .CO(thePC_i_0_n_2), + .S(thePC_n_3)); + HA_X1_LVT thePC_i_0_3 (.A(CurrentPC[6]), .B(thePC_i_0_n_2), .CO(thePC_i_0_n_3), + .S(thePC_n_4)); + HA_X1_LVT thePC_i_0_4 (.A(CurrentPC[7]), .B(thePC_i_0_n_3), .CO(thePC_i_0_n_4), + .S(thePC_n_5)); + HA_X1_LVT thePC_i_0_5 (.A(CurrentPC[8]), .B(thePC_i_0_n_4), .CO(thePC_i_0_n_5), + .S(thePC_n_6)); + HA_X1_LVT thePC_i_0_6 (.A(CurrentPC[9]), .B(thePC_i_0_n_5), .CO(thePC_i_0_n_6), + .S(thePC_n_7)); + HA_X1_LVT thePC_i_0_7 (.A(CurrentPC[10]), .B(thePC_i_0_n_6), .CO( + thePC_i_0_n_7), .S(thePC_n_8)); + HA_X1_LVT thePC_i_0_8 (.A(CurrentPC[11]), .B(thePC_i_0_n_7), .CO( + thePC_i_0_n_8), .S(thePC_n_9)); + HA_X1_LVT thePC_i_0_9 (.A(CurrentPC[12]), .B(thePC_i_0_n_8), .CO( + thePC_i_0_n_9), .S(thePC_n_10)); + HA_X1_LVT thePC_i_0_11 (.A(CurrentPC[13]), .B(thePC_i_0_n_9), .CO( + thePC_i_0_n_10), .S(thePC_n_11)); + HA_X1_LVT thePC_i_0_12 (.A(CurrentPC[14]), .B(thePC_i_0_n_10), .CO( + thePC_i_0_n_11), .S(thePC_n_12)); + HA_X1_LVT thePC_i_0_13 (.A(CurrentPC[15]), .B(thePC_i_0_n_11), .CO( + thePC_i_0_n_12), .S(thePC_n_13)); + HA_X1_LVT thePC_i_0_14 (.A(CurrentPC[16]), .B(thePC_i_0_n_12), .CO( + thePC_i_0_n_13), .S(thePC_n_14)); + HA_X1_LVT thePC_i_0_15 (.A(CurrentPC[17]), .B(thePC_i_0_n_13), .CO( + thePC_i_0_n_14), .S(thePC_n_15)); + HA_X1_LVT thePC_i_0_16 (.A(CurrentPC[18]), .B(thePC_i_0_n_14), .CO( + thePC_i_0_n_15), .S(thePC_n_16)); + HA_X1_LVT thePC_i_0_17 (.A(CurrentPC[19]), .B(thePC_i_0_n_15), .CO( + thePC_i_0_n_16), .S(thePC_n_17)); + HA_X1_LVT thePC_i_0_10 (.A(CurrentPC[20]), .B(thePC_i_0_n_16), .CO( + thePC_i_0_n_17), .S(thePC_n_18)); + HA_X1_LVT thePC_i_0_18 (.A(CurrentPC[21]), .B(thePC_i_0_n_17), .CO( + thePC_i_0_n_18), .S(thePC_n_19)); + HA_X1_LVT thePC_i_0_19 (.A(CurrentPC[22]), .B(thePC_i_0_n_18), .CO( + thePC_i_0_n_19), .S(thePC_n_20)); + HA_X1_LVT thePC_i_0_20 (.A(CurrentPC[23]), .B(thePC_i_0_n_19), .CO( + thePC_i_0_n_20), .S(thePC_n_21)); + HA_X1_LVT thePC_i_0_21 (.A(CurrentPC[24]), .B(thePC_i_0_n_20), .CO( + thePC_i_0_n_21), .S(thePC_n_22)); + HA_X1_LVT thePC_i_0_22 (.A(CurrentPC[25]), .B(thePC_i_0_n_21), .CO( + thePC_i_0_n_22), .S(thePC_n_23)); + HA_X1_LVT thePC_i_0_23 (.A(CurrentPC[26]), .B(thePC_i_0_n_22), .CO( + thePC_i_0_n_23), .S(thePC_n_24)); + HA_X1_LVT thePC_i_0_24 (.A(CurrentPC[27]), .B(thePC_i_0_n_23), .CO( + thePC_i_0_n_24), .S(thePC_n_25)); + HA_X1_LVT thePC_i_0_25 (.A(CurrentPC[28]), .B(thePC_i_0_n_24), .CO( + thePC_i_0_n_25), .S(thePC_n_26)); + HA_X1_LVT thePC_i_0_26 (.A(CurrentPC[29]), .B(thePC_i_0_n_25), .CO( + thePC_i_0_n_26), .S(thePC_n_27)); + HA_X1_LVT thePC_i_0_27 (.A(CurrentPC[30]), .B(thePC_i_0_n_26), .CO( + thePC_i_0_n_27), .S(thePC_n_28)); + XOR2_X1_LVT thePC_i_0_28 (.A(CurrentPC[31]), .B(thePC_i_0_n_27), .Z( + thePC_n_29)); + AOI22_X1_LVT i_0_0_52 (.A1(JumpOrBranchPC[31]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_29), .ZN(n_0_0_20)); + INV_X1_LVT i_0_0_51 (.A(n_0_0_20), .ZN(thePC_n_61)); + SDFF_X1_LVT \thePC_CurrentPC_reg[31] (.D(thePC_n_61), .SE(1'b0), .SI( + CurrentPC[31]), .CK(clk_25mhz), .Q(CurrentPC[31]), .QN()); + AOI22_X1_LVT i_0_0_3 (.A1(JumpOrBranchPC[1]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(CurrentPC[1]), .ZN(n_0_0_1)); + INV_X1_LVT i_0_0_2 (.A(n_0_0_1), .ZN(thePC_n_31)); + SDFF_X1_LVT \thePC_CurrentPC_reg[1] (.D(thePC_n_31), .SE(1'b0), .SI( + CurrentPC[1]), .CK(clk_25mhz), .Q(CurrentPC[1]), .QN()); + AOI22_X1_LVT i_0_0_1 (.A1(JumpOrBranchPC[0]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(CurrentPC[0]), .ZN(n_0_0_0)); + INV_X1_LVT i_0_0_0 (.A(n_0_0_0), .ZN(thePC_n_30)); + SDFF_X1_LVT \thePC_CurrentPC_reg[0] (.D(thePC_n_30), .SE(1'b0), .SI( + CurrentPC[0]), .CK(clk_25mhz), .Q(CurrentPC[0]), .QN()); + reg_file theRegisters (.Rs1({Instruction[19], Instruction[18], + Instruction[17], Instruction[16], Instruction[15]}), .Rs2({Instruction[24], + Instruction[23], Instruction[22], Instruction[21], Instruction[20]}), + .Rd({Instruction[11], Instruction[10], Instruction[9], Instruction[8], + Instruction[7]}), .RRs1(RRs1), .RRs2(RRs2), .WRd(WRd), .WrReg(WrReg), + .reset(reset), .clk(clk_25mhz), .dftIn(scan_en)); + main_mem theMem (.clk(clk_25mhz), .reset(reset), .DAddr({uc_0, uc_1, uc_2, + uc_3, uc_4, uc_5, uc_6, uc_7, uc_8, uc_9, uc_10, uc_11, uc_12, uc_13, + uc_14, uc_15, uc_16, uc_17, uc_18, DAddr[12], DAddr[11], DAddr[10], + DAddr[9], DAddr[8], DAddr[7], DAddr[6], DAddr[5], DAddr[4], DAddr[3], + DAddr[2], DAddr[1], DAddr[0]}), .IAddr({uc_19, uc_20, uc_21, uc_22, uc_23, + uc_24, uc_25, uc_26, uc_27, uc_28, uc_29, uc_30, uc_31, uc_32, uc_33, + uc_34, uc_35, uc_36, uc_37, NextPC[12], NextPC[11], NextPC[10], NextPC[9], + NextPC[8], led[7], led[6], led[5], led[4], led[3], led[2], uc_38, uc_39}), + .DWData(RRs2), .DRData(RData), .IRData(Instruction), .DWE(led[1]), + .DWidth(DWidth)); + decoder theDecoder (.CurrentPC(CurrentPC), .JumpOrBranchPC(JumpOrBranchPC), + .JumpOrBranch(JumpOrBranch), .DAddr({uc_40, uc_41, uc_42, uc_43, uc_44, + uc_45, uc_46, uc_47, uc_48, uc_49, uc_50, uc_51, uc_52, uc_53, uc_54, + uc_55, uc_56, uc_57, uc_58, DAddr[12], DAddr[11], DAddr[10], DAddr[9], + DAddr[8], DAddr[7], DAddr[6], DAddr[5], DAddr[4], DAddr[3], DAddr[2], + DAddr[1], DAddr[0]}), .WData(), .RData(RData), .Instruction(Instruction), + .WrMem(led[1]), .DWidth(DWidth), .Rs1(), .Rs2(), .Rd(), .RRs1(RRs1), + .RRs2(RRs2), .WRd(WRd), .WrReg(WrReg), .Illegal(led[0])); + MUX2_X1_LVT i_0_0_60 (.A(thePC_n_5), .B(JumpOrBranchPC[7]), .S(JumpOrBranch), + .Z(led[7])); +endmodule diff --git a/oasys.tessent.00/Scan_0/post_scan.v b/oasys.tessent.00/Scan_0/post_scan.v new file mode 100644 index 0000000..8235b48 --- /dev/null +++ b/oasys.tessent.00/Scan_0/post_scan.v @@ -0,0 +1,15792 @@ +/* Generated by Tessent Shell 2023.4-p1 at Thu May 28 17:29:02 CEST 2026 */ +module alu(aluOp, aluNegAr, aluBypass, op1, op2, result, eqFlag); + input [31:0] op1, op2; + input [2:0] aluOp; + input aluNegAr, aluBypass; + output [31:0] result; + output eqFlag; + + wire n_9_0, n_9_1, n_9_2, n_9_3, n_9_4, n_9_5, n_9_6, n_9_7, n_9_8, n_9_9, + n_9_10, n_9_11, n_9_12, n_9_13, n_9_14, n_9_15, n_9_16, n_9_17, n_9_18, + n_9_19, n_9_20, n_9_21, n_9_22, n_9_23, n_9_24, n_9_25, n_9_26, n_9_27, + n_9_28, n_9_29, n_9_30, n_9_31, n_10_0, n_10_1, n_10_2, n_10_3, n_10_4, + n_10_5, n_10_6, n_10_7, n_10_8, n_10_9, n_10_10, n_10_11, n_10_12, + n_10_13, n_10_14, n_10_15, n_10_16, n_10_17, n_10_18, n_10_19, n_10_20, + n_10_21, n_10_22, n_10_23, n_10_24, n_10_25, n_10_26, n_10_27, n_10_28, + n_10_29, n_10_30, n_10_31, n_10_32, n_10_33, n_10_34, n_10_35, n_10_36, + n_10_37, n_10_38, n_10_39, n_10_40, n_10_41, n_10_42, n_10_43, n_10_44, + n_10_45, n_10_46, n_10_47, n_10_48, n_10_49, n_10_50, n_10_51, n_10_52, + n_10_53, n_10_54, n_10_55, n_10_56, n_10_57, n_10_58, n_10_59, n_10_60, + n_10_61, n_10_62, n_10_63, n_10_64, n_10_65, n_10_66, n_10_67, n_10_68, + n_10_69, n_10_70, n_10_71, n_10_72, n_10_73, n_10_74, n_10_75, n_10_76, + n_10_77, n_10_78, n_10_79, n_10_80, n_10_81, n_10_82, n_10_83, n_10_84, + n_10_85, n_10_86, n_10_87, n_10_88, n_10_89, n_10_90, n_10_91, n_10_92, + n_10_93, n_10_94, n_10_95, n_10_96, n_10_97, n_10_98, n_10_99, n_10_100, + n_10_101, n_10_102, n_10_103, n_10_104, n_10_105, n_10_106, n_10_107, + n_10_108, n_10_109, n_10_110, n_10_111, n_10_112, n_10_113, n_10_114, + n_10_115, n_10_116, n_10_117, n_10_118, n_10_119, n_10_120, n_10_121, + n_10_122, n_10_123, n_0_0, n_0_1, n_0_2, n_0_3, n_0_4, n_0_5, n_0_6, + n_0_7, n_0_8, n_0_9, n_0_10, n_0_11, n_0_12, n_0_13, n_0_14, n_0_15, + n_0_16, n_0_17, n_0_18, n_0_19, n_0_20, n_0_21, n_0_22, n_0_23, n_0_24, + n_0_25, n_0_26, n_0_27, n_0_28, n_0_29, n_0_30, n_0_31, n_0_32, n_0_33, + n_0_34, n_0_35, n_0_36, n_0_37, n_0_38, n_0_39, n_0_40, n_0_41, n_0_42, + n_0_43, n_0_44, n_0_45, n_0_46, n_0_47, n_0_48, n_0_49, n_0_50, n_0_51, + n_0_52, n_0_53, n_0_54, n_0_55, n_0_56, n_0_57, n_0_58, n_0_59, n_0_60, + n_0_61, n_0_62, n_0_63, n_0_64, n_0_65, n_0_66, n_0_67, n_0_68, n_0_69, + n_0_70, n_0_71, n_0_72, n_0_73, n_0_74, n_0_75, n_0_76, n_0_77, n_0_78, + n_0_79, n_0_80, n_0_81, n_0_82, n_0_83, n_0_84, n_0_85, n_0_86, n_0_87, + n_0_88, n_0_89, n_0_90, n_0_91, n_0_92, n_0_93, n_0_94, n_0_95, n_0_96, + n_0_97, n_0_98, n_0_99, n_0_100, n_0_101, n_0_102, n_0_103, n_0_104, + n_0_105, n_0_106, n_0_107, n_0_108, n_0_109, n_0_110, n_0_111, n_0_112, + n_0_113, n_0_114, n_0_115, n_0_116, n_0_117, n_0_118, n_0_119, n_0_120, + n_0_121, n_0_122, n_0_123, n_0_124, n_0_125, n_0_126, n_0_127, n_0_128, + n_0_129, n_0_130, n_0_131, n_0_132, n_0_133, n_0_134, n_0_135, n_0_136, + n_0_137, n_0_138, n_0_139, n_0_140, n_0_141, n_0_142, n_0_143, n_0_144, + n_0_145, n_0_146, n_0_147, n_0_148, n_0_149, n_0_150, n_0_151, n_0_152, + n_0_153, n_0_154, n_0_155, n_0_156, n_0_157, n_0_158, n_0_159, n_0_160, + n_0_161, n_0_162, n_0_163, n_0_164, n_0_165, n_0_166, n_0_167, n_0_168, + n_0_169, n_0_170, n_0_171, n_0_172, n_0_173, n_0_174, n_0_175, n_0_176, + n_0_177, n_0_178, n_0_179, n_0_180, n_0_181, n_0_182, n_0_183, n_0_184, + n_0_185, n_0_186, n_0_187, n_0_188, n_0_189, n_0_190, n_0_191, n_0_192, + n_0_193, n_0_194, n_0_195, n_0_196, n_0_197, n_0_198, n_0_199, n_0_200, + n_0_201, n_0_202, n_0_203, n_0_204, n_0_205, n_0_206, n_0_207, n_0_208, + n_0_209, n_0_210, n_0_211, n_0_212, n_0_213, n_0_214, n_0_215, n_0_216, + n_0_217, n_0_218, n_0_219, n_0_220, n_0_221, n_0_222, n_0_223, n_0_224, + n_0_225, n_0_226, n_0_227, n_0_228, n_0_229, n_0_230, n_0_231, n_0_232, + n_0_233, n_0_234, n_0_235, n_0_236, n_0_237, n_0_238, n_0_239, n_0_240, + n_0_241, n_0_242, n_0_243, n_0_244, n_0_245, n_0_246, n_0_247, n_0_248, + n_0_249, n_0_250, n_0_251, n_0_252, n_0_253, n_0_254, n_0_255, n_0_256, + n_0_257, n_0_258, n_0_259, n_0_260, n_0_261, n_0_262, n_0_263, n_0_264, + n_0_265, n_0_266, n_0_267, n_0_268, n_0_269, n_0_270, n_0_271, n_0_272, + n_0_273, n_0_274, n_0_275, n_0_276, n_0_277, n_0_278, n_0_279, n_0_280, + n_0_281, n_0_282, n_0_283, n_0_284, n_0_285, n_0_286, n_0_287, n_0_288, + n_0_289, n_0_290, n_0_291, n_0_292, n_0_293, n_0_294, n_0_295, n_0_296, + n_0_297, n_0_298, n_0_299, n_0_300, n_0_301, n_0_302, n_0_303, n_0_304, + n_0_305, n_0_306, n_0_307, n_0_308, n_0_309, n_0_310, n_0_311, n_0_312, + n_0_313, n_0_314, n_0_315, n_0_316, n_0_317, n_0_318, n_0_319, n_0_320, + n_0_321, n_0_322, n_0_323, n_0_324, n_0_325, n_0_326, n_0_327, n_0_328, + n_0_329, n_0_330, n_0_331, n_0_332, n_0_333, n_0_334, n_0_335, n_0_336, + n_0_337, n_0_338, n_0_339, n_0_340, n_0_341, n_0_342, n_0_343, n_0_344, + n_0_345, n_0_346, n_0_347, n_0_348, n_0_349, n_0_350, n_0_351, n_0_352, + n_0_353, n_0_354, n_0_355, n_0_356, n_0_357, n_0_358, n_0_359, n_0_360, + n_0_361, n_0_362, n_0_363, n_0_364, n_0_365, n_0_366, n_0_367, n_0_368, + n_0_369, n_0_370, n_0_371, n_0_372, n_0_373, n_0_374, n_0_375, n_0_376, + n_0_377, n_0_378, n_0_379, n_0_380, n_0_381, n_0_382, n_0_383, n_0_384, + n_0_385, n_0_386, n_0_387, n_0_388, n_0_389, n_0_390, n_0_391, n_0_392, + n_0_393, n_0_394, n_0_395, n_0_396, n_0_397, n_0_398, n_0_399, n_0_400, + n_0_401, n_0_402, n_0_403, n_0_404, n_0_405, n_0_406, n_0_407, n_0_408, + n_0_409, n_0_410, n_0_411, n_0_412, n_0_413, n_0_414, n_0_415, n_0_416, + n_0_417, n_0_418, n_0_419, n_0_420, n_0_421, n_0_422, n_0_423, n_0_424, + n_0_425, n_0_426, n_0_427, n_0_428, n_0_429, n_0_430, n_0_431, n_0_432, + n_0_433, n_0_434, n_0_435, n_0_436, n_0_437, n_0_438, n_0_439, n_0_440, + n_0_441, n_0_442, n_0_443, n_0_444, n_0_445, n_0_446, n_0_447, n_0_448, + n_0_449, n_0_450, n_0_451, n_0_452, n_0_453, n_0_454, n_0_455, n_0_456, + n_0_457, n_0_458, n_0_459, n_0_460, n_0_461, n_0_462, n_0_463, n_0_464, + n_0_465, n_0_466, n_0_467, n_0_468, n_0_469, n_0_470, n_0_471, n_0_472, + n_0_473, n_0_474, n_0_475, n_0_476, n_0_477, n_0_478, n_0_479, n_0_480, + n_0_481, n_0_482, n_0_483, n_0_484, n_0_485, n_0_486, n_0_487, n_0_488, + n_0_489, n_0_490, n_0_491, n_0_492, n_0_493, n_0_494, n_0_495, n_0_496, + n_0_497, n_0_498, n_0_499, n_0_500, n_0_501, n_0_502, n_0_503, n_0_504, + n_0_505, n_0_506, n_0_507, n_0_508, n_0_509, n_0_510, n_0_511, n_0_512, + n_0_513, n_0_514, n_0_515, n_0_516, n_0_517, n_0_518, n_0_519, n_0_520, + n_0_521, n_0_522, n_0_523, n_0_524, n_0_525, n_0_526, n_0_527, n_0_528, + n_0_529, n_0_530, n_0_531, n_0_532, n_0_533, n_0_534, n_0_535, n_0_536, + n_0_537, n_0_538, n_0_539, n_0_540, n_0_541, n_0_542, n_0_543, n_0_544, + n_0_545, n_0_546, n_0_547, n_0_548, n_0_549, n_0_550, n_0_551, n_0_552, + n_0_553, n_0_554, n_0_555, n_0_556, n_0_557, n_0_558, n_0_559, n_0_560, + n_0_561, n_0_562, n_0_563, n_0_564, n_0_565, n_0_566, n_0_567, n_0_568, + n_0_569, n_0_570, n_0_571, n_0_572, n_0_573, n_0_574, n_0_575, n_0_576, + n_0_577, n_0_578, n_0_579, n_0_580, n_0_581, n_0_582, n_0_583, n_0_584, + n_0_585, n_0_586, n_0_587, n_0_588, n_0_589, n_0_590, n_0_591, n_0_592, + n_0_593, n_0_594, n_0_595, n_0_596, n_0_597, n_0_598, n_0_599, n_0_600, + n_0_601, n_0_602, n_0_603, n_0_604, n_0_605, n_0_606, n_0_607, n_0_608, + n_0_609, n_0_610, n_0_611, n_0_612, n_0_613, n_0_614, n_0_615, n_0_616, + n_0_617, n_0_618, n_0_619, n_0_620, n_0_621, n_0_622, n_0_623, n_0_624, + n_0_625, n_0_626, n_0_627, n_0_628, n_0_629, n_0_630, n_0_631, n_0_632, + n_0_633, n_0_634, n_0_635, n_0_636, n_0_637, n_0_638, n_0_639, n_0_640, + n_0_641, n_0_642, n_0_643, n_0_644, n_0_645, n_0_646, n_0_647, n_0_648, + n_0_649, n_0_650, n_0_651, n_0_652, n_0_653, n_0_654, n_0_655, n_0_656, + n_0_657, n_0_658, n_0_659, n_0_660, n_0_661, n_0_662, n_0_663, n_0_664, + n_0_665, n_0_666, n_0_667, n_0_668, n_0_669, n_0_670, n_0_671, n_0_672, + n_0_673, n_0_674, n_0_675, n_0_676, n_0_677, n_0_678, n_0_679, n_0_680, + n_0_681, n_0_682, n_0_683, n_0_684, n_0_685, n_0_686, n_0_687, n_0_688, + n_0_689, n_0_690, n_0_691, n_0_692, n_0_693, n_0_694, n_0_695, n_0_696, + n_0_697, n_0_698, n_0_699, n_0_700, n_0_701, n_0_702, n_0_703, n_0_704, + n_0_705, n_0_706, n_0_707, n_0_708, n_0_709, n_0_710, n_0_711, n_0_712, + n_0_713, n_0_714, n_0_715, n_0_716, n_0_717, n_0_718, n_0_719, n_0_720, + n_0_721, n_0_722, n_0_723, n_0_724, n_0_725, n_0_726, n_0_727, n_0_728, + n_0_729, n_0_730, n_0_731, n_0_732, n_0_733, n_0_734, n_0_735, n_0_736, + n_0_737, n_0_738, n_0_739, n_0_740, n_0, n_1, n_2, n_3, n_4, n_5, n_6, + n_7, n_8, n_9, n_10, n_11, n_12, n_13, n_14, n_15, n_16, n_17, n_18, + n_19, n_20, n_21, n_22, n_23, n_24, n_25, n_26, n_27, n_28, n_29, n_30, + n_31, n_63, n_62, n_61, n_60, n_59, n_58, n_57, n_56, n_55, n_54, n_53, + n_52, n_51, n_50, n_49, n_48, n_47, n_46, n_45, n_44, n_43, n_42, n_41, + n_40, n_39, n_38, n_37, n_36, n_35, n_34, n_33, n_32; + + INV_X1_LVT i_0_725( + .A(op2[31]), .ZN(n_0_692) + ); + INV_X1_LVT i_0_724( + .A(op1[31]), .ZN(n_0_691) + ); + INV_X1_LVT i_0_718( + .A(aluOp[1]), .ZN(n_0_685) + ); + INV_X1_LVT i_0_717( + .A(aluOp[2]), .ZN(n_0_684) + ); + NOR2_X1_LVT i_0_599( + .A1(n_0_685), .A2(n_0_684), .ZN(n_0_567) + ); + INV_X1_LVT i_0_598( + .A(n_0_567), .ZN(n_0_566) + ); + INV_X1_LVT i_0_716( + .A(aluOp[0]), .ZN(n_0_683) + ); + NAND2_X1_LVT i_0_602( + .A1(aluOp[2]), .A2(aluNegAr), .ZN(n_0_570) + ); + OAI21_X1_LVT i_0_590( + .A(n_0_566), .B1(n_0_683), .B2(n_0_570), .ZN(n_0_558) + ); + INV_X1_LVT i_0_714( + .A(aluBypass), .ZN(n_0_681) + ); + NOR2_X1_LVT i_0_601( + .A1(n_0_684), .A2(aluOp[0]), .ZN(n_0_569) + ); + NAND2_X1_LVT i_0_597( + .A1(n_0_681), .A2(n_0_569), .ZN(n_0_565) + ); + INV_X1_LVT i_0_596( + .A(n_0_565), .ZN(n_0_564) + ); + OAI22_X1_LVT i_0_589( + .A1(n_0_691), .A2(n_0_558), .B1(op1[31]), .B2(n_0_564), .ZN(n_0_557) + ); + NOR2_X1_LVT i_0_588( + .A1(n_0_692), .A2(n_0_557), .ZN(n_0_556) + ); + XNOR2_X1_LVT i_9_31( + .A(op2[31]), .B(op1[31]), .ZN(n_9_31) + ); + HA_X1_LVT i_9_0( + .A(op2[0]), .B(op1[0]), .CO(n_9_0), .S(n_0) + ); + FA_X1_LVT i_9_1( + .A(op2[1]), .B(op1[1]), .CI(n_9_0), .CO(n_9_1), .S(n_1) + ); + FA_X1_LVT i_9_2( + .A(op2[2]), .B(op1[2]), .CI(n_9_1), .CO(n_9_2), .S(n_2) + ); + FA_X1_LVT i_9_3( + .A(op2[3]), .B(op1[3]), .CI(n_9_2), .CO(n_9_3), .S(n_3) + ); + FA_X1_LVT i_9_4( + .A(op2[4]), .B(op1[4]), .CI(n_9_3), .CO(n_9_4), .S(n_4) + ); + FA_X1_LVT i_9_5( + .A(op2[5]), .B(op1[5]), .CI(n_9_4), .CO(n_9_5), .S(n_5) + ); + FA_X1_LVT i_9_6( + .A(op2[6]), .B(op1[6]), .CI(n_9_5), .CO(n_9_6), .S(n_6) + ); + FA_X1_LVT i_9_7( + .A(op2[7]), .B(op1[7]), .CI(n_9_6), .CO(n_9_7), .S(n_7) + ); + FA_X1_LVT i_9_8( + .A(op2[8]), .B(op1[8]), .CI(n_9_7), .CO(n_9_8), .S(n_8) + ); + FA_X1_LVT i_9_9( + .A(op2[9]), .B(op1[9]), .CI(n_9_8), .CO(n_9_9), .S(n_9) + ); + FA_X1_LVT i_9_10( + .A(op2[10]), .B(op1[10]), .CI(n_9_9), .CO(n_9_10), .S(n_10) + ); + FA_X1_LVT i_9_11( + .A(op2[11]), .B(op1[11]), .CI(n_9_10), .CO(n_9_11), .S(n_11) + ); + FA_X1_LVT i_9_12( + .A(op2[12]), .B(op1[12]), .CI(n_9_11), .CO(n_9_12), .S(n_12) + ); + FA_X1_LVT i_9_13( + .A(op2[13]), .B(op1[13]), .CI(n_9_12), .CO(n_9_13), .S(n_13) + ); + FA_X1_LVT i_9_14( + .A(op2[14]), .B(op1[14]), .CI(n_9_13), .CO(n_9_14), .S(n_14) + ); + FA_X1_LVT i_9_15( + .A(op2[15]), .B(op1[15]), .CI(n_9_14), .CO(n_9_15), .S(n_15) + ); + FA_X1_LVT i_9_16( + .A(op2[16]), .B(op1[16]), .CI(n_9_15), .CO(n_9_16), .S(n_16) + ); + FA_X1_LVT i_9_17( + .A(op2[17]), .B(op1[17]), .CI(n_9_16), .CO(n_9_17), .S(n_17) + ); + FA_X1_LVT i_9_18( + .A(op2[18]), .B(op1[18]), .CI(n_9_17), .CO(n_9_18), .S(n_18) + ); + FA_X1_LVT i_9_19( + .A(op2[19]), .B(op1[19]), .CI(n_9_18), .CO(n_9_19), .S(n_19) + ); + FA_X1_LVT i_9_20( + .A(op2[20]), .B(op1[20]), .CI(n_9_19), .CO(n_9_20), .S(n_20) + ); + FA_X1_LVT i_9_21( + .A(op2[21]), .B(op1[21]), .CI(n_9_20), .CO(n_9_21), .S(n_21) + ); + FA_X1_LVT i_9_22( + .A(op2[22]), .B(op1[22]), .CI(n_9_21), .CO(n_9_22), .S(n_22) + ); + FA_X1_LVT i_9_23( + .A(op2[23]), .B(op1[23]), .CI(n_9_22), .CO(n_9_23), .S(n_23) + ); + FA_X1_LVT i_9_24( + .A(op2[24]), .B(op1[24]), .CI(n_9_23), .CO(n_9_24), .S(n_24) + ); + FA_X1_LVT i_9_25( + .A(op2[25]), .B(op1[25]), .CI(n_9_24), .CO(n_9_25), .S(n_25) + ); + FA_X1_LVT i_9_26( + .A(op2[26]), .B(op1[26]), .CI(n_9_25), .CO(n_9_26), .S(n_26) + ); + FA_X1_LVT i_9_27( + .A(op2[27]), .B(op1[27]), .CI(n_9_26), .CO(n_9_27), .S(n_27) + ); + FA_X1_LVT i_9_28( + .A(op2[28]), .B(op1[28]), .CI(n_9_27), .CO(n_9_28), .S(n_28) + ); + FA_X1_LVT i_9_29( + .A(op2[29]), .B(op1[29]), .CI(n_9_28), .CO(n_9_29), .S(n_29) + ); + FA_X1_LVT i_9_30( + .A(op2[30]), .B(op1[30]), .CI(n_9_29), .CO(n_9_30), .S(n_30) + ); + XNOR2_X1_LVT i_9_32( + .A(n_9_31), .B(n_9_30), .ZN(n_31) + ); + NAND4_X1_LVT i_0_614( + .A1(n_0_685), .A2(n_0_681), .A3(n_0_684), .A4(n_0_683), .ZN(n_0_582) + ); + NOR2_X1_LVT i_0_613( + .A1(aluNegAr), .A2(n_0_582), .ZN(n_0_581) + ); + INV_X1_LVT i_10_147( + .A(op2[30]), .ZN(n_10_117) + ); + NAND2_X1_LVT i_10_149( + .A1(n_10_117), .A2(op1[30]), .ZN(n_10_119) + ); + INV_X1_LVT i_10_152( + .A(n_10_119), .ZN(n_10_121) + ); + INV_X1_LVT i_10_130( + .A(op1[26]), .ZN(n_10_104) + ); + NAND2_X1_LVT i_10_131( + .A1(n_10_104), .A2(op2[26]), .ZN(n_10_105) + ); + INV_X1_LVT i_10_123( + .A(op2[25]), .ZN(n_10_98) + ); + NAND2_X1_LVT i_10_125( + .A1(n_10_98), .A2(op1[25]), .ZN(n_10_100) + ); + INV_X1_LVT i_10_112( + .A(op2[23]), .ZN(n_10_89) + ); + NAND2_X1_LVT i_10_114( + .A1(n_10_89), .A2(op1[23]), .ZN(n_10_91) + ); + INV_X1_LVT i_10_101( + .A(op2[21]), .ZN(n_10_80) + ); + NAND2_X1_LVT i_10_103( + .A1(n_10_80), .A2(op1[21]), .ZN(n_10_82) + ); + INV_X1_LVT i_10_48( + .A(op1[8]), .ZN(n_10_40) + ); + NAND2_X1_LVT i_10_49( + .A1(n_10_40), .A2(op2[8]), .ZN(n_10_41) + ); + INV_X1_LVT i_10_41( + .A(op2[7]), .ZN(n_10_34) + ); + NAND2_X1_LVT i_10_43( + .A1(n_10_34), .A2(op1[7]), .ZN(n_10_36) + ); + INV_X1_LVT i_10_32( + .A(op2[5]), .ZN(n_10_27) + ); + NOR2_X1_LVT i_10_33( + .A1(n_10_27), .A2(op1[5]), .ZN(n_10_28) + ); + INV_X1_LVT i_10_24( + .A(op1[4]), .ZN(n_10_20) + ); + NOR2_X1_LVT i_10_27( + .A1(n_10_20), .A2(op2[4]), .ZN(n_10_23) + ); + INV_X1_LVT i_10_17( + .A(op2[3]), .ZN(n_10_14) + ); + NAND2_X1_LVT i_10_19( + .A1(n_10_14), .A2(op1[3]), .ZN(n_10_16) + ); + INV_X1_LVT i_10_22( + .A(n_10_16), .ZN(n_10_18) + ); + INV_X1_LVT i_10_10( + .A(op2[2]), .ZN(n_10_8) + ); + NAND2_X1_LVT i_10_12( + .A1(n_10_8), .A2(op1[2]), .ZN(n_10_10) + ); + INV_X1_LVT i_10_3( + .A(op1[1]), .ZN(n_10_2) + ); + NAND2_X1_LVT i_10_5( + .A1(n_10_2), .A2(op2[1]), .ZN(n_10_4) + ); + INV_X1_LVT i_10_0( + .A(op1[0]), .ZN(n_10_0) + ); + NAND2_X1_LVT i_10_1( + .A1(n_10_0), .A2(op2[0]), .ZN(n_10_1) + ); + OR2_X1_LVT i_10_4( + .A1(n_10_2), .A2(op2[1]), .ZN(n_10_3) + ); + INV_X1_LVT i_10_8( + .A(n_10_3), .ZN(n_10_6) + ); + OAI21_X1_LVT i_10_9( + .A(n_10_4), .B1(n_10_1), .B2(n_10_6), .ZN(n_10_7) + ); + NOR2_X1_LVT i_10_11( + .A1(n_10_8), .A2(op1[2]), .ZN(n_10_9) + ); + OAI21_X1_LVT i_10_16( + .A(n_10_10), .B1(n_10_7), .B2(n_10_9), .ZN(n_10_13) + ); + OR2_X1_LVT i_10_18( + .A1(n_10_14), .A2(op1[3]), .ZN(n_10_15) + ); + AOI21_X1_LVT i_10_23( + .A(n_10_18), .B1(n_10_13), .B2(n_10_15), .ZN(n_10_19) + ); + INV_X1_LVT i_10_30( + .A(n_10_19), .ZN(n_10_25) + ); + NAND2_X1_LVT i_10_25( + .A1(n_10_20), .A2(op2[4]), .ZN(n_10_21) + ); + AOI21_X1_LVT i_10_31( + .A(n_10_23), .B1(n_10_25), .B2(n_10_21), .ZN(n_10_26) + ); + AOI21_X1_LVT i_10_34( + .A(n_10_28), .B1(n_10_27), .B2(op1[5]), .ZN(n_10_29) + ); + AOI21_X1_LVT i_10_36( + .A(n_10_28), .B1(n_10_26), .B2(n_10_29), .ZN(n_10_30) + ); + XOR2_X1_LVT i_10_37( + .A(op2[6]), .B(op1[6]), .Z(n_10_31) + ); + INV_X1_LVT i_10_39( + .A(op2[6]), .ZN(n_10_32) + ); + OAI22_X1_LVT i_10_40( + .A1(n_10_30), .A2(n_10_31), .B1(n_10_32), .B2(op1[6]), .ZN(n_10_33) + ); + NOR2_X1_LVT i_10_42( + .A1(n_10_34), .A2(op1[7]), .ZN(n_10_35) + ); + OAI21_X1_LVT i_10_47( + .A(n_10_36), .B1(n_10_33), .B2(n_10_35), .ZN(n_10_39) + ); + OAI21_X1_LVT i_10_50( + .A(n_10_41), .B1(n_10_40), .B2(op2[8]), .ZN(n_10_42) + ); + OAI21_X1_LVT i_10_52( + .A(n_10_41), .B1(n_10_39), .B2(n_10_42), .ZN(n_10_43) + ); + XNOR2_X1_LVT i_10_53( + .A(op2[9]), .B(op1[9]), .ZN(n_10_44) + ); + INV_X1_LVT i_10_55( + .A(op1[9]), .ZN(n_10_45) + ); + AOI22_X1_LVT i_10_56( + .A1(n_10_43), .A2(n_10_44), .B1(n_10_45), .B2(op2[9]), .ZN(n_10_46) + ); + XOR2_X1_LVT i_10_57( + .A(op2[10]), .B(op1[10]), .Z(n_10_47) + ); + INV_X1_LVT i_10_59( + .A(op2[10]), .ZN(n_10_48) + ); + OAI22_X1_LVT i_10_60( + .A1(n_10_46), .A2(n_10_47), .B1(n_10_48), .B2(op1[10]), .ZN(n_10_49) + ); + XNOR2_X1_LVT i_10_61( + .A(op2[11]), .B(op1[11]), .ZN(n_10_50) + ); + INV_X1_LVT i_10_63( + .A(op1[11]), .ZN(n_10_51) + ); + AOI22_X1_LVT i_10_64( + .A1(n_10_49), .A2(n_10_50), .B1(n_10_51), .B2(op2[11]), .ZN(n_10_52) + ); + XOR2_X1_LVT i_10_65( + .A(op2[12]), .B(op1[12]), .Z(n_10_53) + ); + INV_X1_LVT i_10_67( + .A(op2[12]), .ZN(n_10_54) + ); + OAI22_X1_LVT i_10_68( + .A1(n_10_52), .A2(n_10_53), .B1(n_10_54), .B2(op1[12]), .ZN(n_10_55) + ); + XNOR2_X1_LVT i_10_69( + .A(op2[13]), .B(op1[13]), .ZN(n_10_56) + ); + INV_X1_LVT i_10_71( + .A(op1[13]), .ZN(n_10_57) + ); + AOI22_X1_LVT i_10_72( + .A1(n_10_55), .A2(n_10_56), .B1(n_10_57), .B2(op2[13]), .ZN(n_10_58) + ); + XOR2_X1_LVT i_10_73( + .A(op2[14]), .B(op1[14]), .Z(n_10_59) + ); + INV_X1_LVT i_10_75( + .A(op2[14]), .ZN(n_10_60) + ); + OAI22_X1_LVT i_10_76( + .A1(n_10_58), .A2(n_10_59), .B1(n_10_60), .B2(op1[14]), .ZN(n_10_61) + ); + XNOR2_X1_LVT i_10_77( + .A(op2[15]), .B(op1[15]), .ZN(n_10_62) + ); + INV_X1_LVT i_10_79( + .A(op1[15]), .ZN(n_10_63) + ); + AOI22_X1_LVT i_10_80( + .A1(n_10_61), .A2(n_10_62), .B1(n_10_63), .B2(op2[15]), .ZN(n_10_64) + ); + XOR2_X1_LVT i_10_81( + .A(op2[16]), .B(op1[16]), .Z(n_10_65) + ); + INV_X1_LVT i_10_83( + .A(op2[16]), .ZN(n_10_66) + ); + OAI22_X1_LVT i_10_84( + .A1(n_10_64), .A2(n_10_65), .B1(n_10_66), .B2(op1[16]), .ZN(n_10_67) + ); + XNOR2_X1_LVT i_10_85( + .A(op2[17]), .B(op1[17]), .ZN(n_10_68) + ); + INV_X1_LVT i_10_87( + .A(op1[17]), .ZN(n_10_69) + ); + AOI22_X1_LVT i_10_88( + .A1(n_10_67), .A2(n_10_68), .B1(n_10_69), .B2(op2[17]), .ZN(n_10_70) + ); + XOR2_X1_LVT i_10_89( + .A(op2[18]), .B(op1[18]), .Z(n_10_71) + ); + INV_X1_LVT i_10_91( + .A(op2[18]), .ZN(n_10_72) + ); + OAI22_X1_LVT i_10_92( + .A1(n_10_70), .A2(n_10_71), .B1(n_10_72), .B2(op1[18]), .ZN(n_10_73) + ); + XNOR2_X1_LVT i_10_93( + .A(op2[19]), .B(op1[19]), .ZN(n_10_74) + ); + INV_X1_LVT i_10_95( + .A(op1[19]), .ZN(n_10_75) + ); + AOI22_X1_LVT i_10_96( + .A1(n_10_73), .A2(n_10_74), .B1(n_10_75), .B2(op2[19]), .ZN(n_10_76) + ); + XOR2_X1_LVT i_10_97( + .A(op2[20]), .B(op1[20]), .Z(n_10_77) + ); + INV_X1_LVT i_10_99( + .A(op2[20]), .ZN(n_10_78) + ); + OAI22_X1_LVT i_10_100( + .A1(n_10_76), .A2(n_10_77), .B1(n_10_78), .B2(op1[20]), .ZN(n_10_79) + ); + NOR2_X1_LVT i_10_102( + .A1(n_10_80), .A2(op1[21]), .ZN(n_10_81) + ); + OAI21_X1_LVT i_10_107( + .A(n_10_82), .B1(n_10_79), .B2(n_10_81), .ZN(n_10_85) + ); + XOR2_X1_LVT i_10_108( + .A(op2[22]), .B(op1[22]), .Z(n_10_86) + ); + INV_X1_LVT i_10_110( + .A(op2[22]), .ZN(n_10_87) + ); + OAI22_X1_LVT i_10_111( + .A1(n_10_85), .A2(n_10_86), .B1(n_10_87), .B2(op1[22]), .ZN(n_10_88) + ); + NOR2_X1_LVT i_10_113( + .A1(n_10_89), .A2(op1[23]), .ZN(n_10_90) + ); + OAI21_X1_LVT i_10_118( + .A(n_10_91), .B1(n_10_88), .B2(n_10_90), .ZN(n_10_94) + ); + XOR2_X1_LVT i_10_119( + .A(op2[24]), .B(op1[24]), .Z(n_10_95) + ); + INV_X1_LVT i_10_121( + .A(op2[24]), .ZN(n_10_96) + ); + OAI22_X1_LVT i_10_122( + .A1(n_10_94), .A2(n_10_95), .B1(n_10_96), .B2(op1[24]), .ZN(n_10_97) + ); + NOR2_X1_LVT i_10_124( + .A1(n_10_98), .A2(op1[25]), .ZN(n_10_99) + ); + OAI21_X1_LVT i_10_129( + .A(n_10_100), .B1(n_10_97), .B2(n_10_99), .ZN(n_10_103) + ); + OAI21_X1_LVT i_10_132( + .A(n_10_105), .B1(n_10_104), .B2(op2[26]), .ZN(n_10_106) + ); + OAI21_X1_LVT i_10_134( + .A(n_10_105), .B1(n_10_103), .B2(n_10_106), .ZN(n_10_107) + ); + XNOR2_X1_LVT i_10_135( + .A(op2[27]), .B(op1[27]), .ZN(n_10_108) + ); + INV_X1_LVT i_10_137( + .A(op1[27]), .ZN(n_10_109) + ); + AOI22_X1_LVT i_10_138( + .A1(n_10_107), .A2(n_10_108), .B1(n_10_109), .B2(op2[27]), .ZN(n_10_110) + ); + XOR2_X1_LVT i_10_139( + .A(op2[28]), .B(op1[28]), .Z(n_10_111) + ); + INV_X1_LVT i_10_141( + .A(op2[28]), .ZN(n_10_112) + ); + OAI22_X1_LVT i_10_142( + .A1(n_10_110), .A2(n_10_111), .B1(n_10_112), .B2(op1[28]), .ZN(n_10_113) + ); + XNOR2_X1_LVT i_10_143( + .A(op2[29]), .B(op1[29]), .ZN(n_10_114) + ); + INV_X1_LVT i_10_145( + .A(op1[29]), .ZN(n_10_115) + ); + AOI22_X1_LVT i_10_146( + .A1(n_10_113), .A2(n_10_114), .B1(n_10_115), .B2(op2[29]), .ZN(n_10_116) + ); + OR2_X1_LVT i_10_148( + .A1(n_10_117), .A2(op1[30]), .ZN(n_10_118) + ); + AOI21_X1_LVT i_10_153( + .A(n_10_121), .B1(n_10_116), .B2(n_10_118), .ZN(n_10_122) + ); + XNOR2_X1_LVT i_10_154( + .A(op1[31]), .B(op2[31]), .ZN(n_10_123) + ); + XNOR2_X1_LVT i_10_155( + .A(n_10_122), .B(n_10_123), .ZN(n_63) + ); + INV_X1_LVT i_0_715( + .A(aluNegAr), .ZN(n_0_682) + ); + NOR2_X1_LVT i_0_612( + .A1(n_0_682), .A2(n_0_582), .ZN(n_0_580) + ); + AOI221_X1_LVT i_0_587( + .A(n_0_556), .B1(n_31), .B2(n_0_581), .C1(n_63), .C2(n_0_580), .ZN(n_0_555) + ); + NOR3_X1_LVT i_0_654( + .A1(aluOp[1]), .A2(aluBypass), .A3(n_0_683), .ZN(n_0_622) + ); + NAND2_X1_LVT i_0_653( + .A1(n_0_684), .A2(n_0_622), .ZN(n_0_621) + ); + INV_X1_LVT i_0_734( + .A(op2[0]), .ZN(n_0_701) + ); + INV_X1_LVT i_0_756( + .A(op2[3]), .ZN(n_0_723) + ); + NOR2_X1_LVT i_0_650( + .A1(op2[4]), .A2(n_0_723), .ZN(n_0_618) + ); + INV_X1_LVT i_0_649( + .A(n_0_618), .ZN(n_0_617) + ); + NOR2_X1_LVT i_0_648( + .A1(op2[4]), .A2(op2[3]), .ZN(n_0_616) + ); + INV_X1_LVT i_0_647( + .A(n_0_616), .ZN(n_0_615) + ); + INV_X1_LVT i_0_771( + .A(op2[4]), .ZN(n_0_738) + ); + INV_X1_LVT i_0_767( + .A(op1[15]), .ZN(n_0_734) + ); + INV_X1_LVT i_0_746( + .A(op1[7]), .ZN(n_0_713) + ); + AOI22_X1_LVT i_0_651( + .A1(n_0_734), .A2(n_0_723), .B1(op2[3]), .B2(n_0_713), .ZN(n_0_619) + ); + OAI222_X1_LVT i_0_646( + .A1(op1[23]), .A2(n_0_617), .B1(op1[31]), .B2(n_0_615), .C1(n_0_738), .C2(n_0_619), + .ZN(n_0_614) + ); + NOR2_X1_LVT i_0_645( + .A1(op2[2]), .A2(n_0_614), .ZN(n_0_613) + ); + NOR2_X1_LVT i_0_696( + .A1(op1[3]), .A2(n_0_723), .ZN(n_0_663) + ); + INV_X1_LVT i_0_739( + .A(op1[11]), .ZN(n_0_706) + ); + AOI21_X1_LVT i_0_644( + .A(n_0_663), .B1(n_0_723), .B2(n_0_706), .ZN(n_0_612) + ); + AOI22_X1_LVT i_0_643( + .A1(op2[4]), .A2(n_0_612), .B1(op1[27]), .B2(n_0_616), .ZN(n_0_611) + ); + INV_X1_LVT i_0_722( + .A(op1[19]), .ZN(n_0_689) + ); + OAI21_X1_LVT i_0_642( + .A(n_0_611), .B1(n_0_689), .B2(n_0_617), .ZN(n_0_610) + ); + AOI21_X1_LVT i_0_641( + .A(n_0_613), .B1(op2[2]), .B2(n_0_610), .ZN(n_0_609) + ); + INV_X1_LVT i_0_761( + .A(op2[1]), .ZN(n_0_728) + ); + OAI22_X1_LVT i_0_640( + .A1(op2[4]), .A2(op1[21]), .B1(n_0_738), .B2(op1[5]), .ZN(n_0_608) + ); + NAND2_X1_LVT i_0_639( + .A1(op2[3]), .A2(n_0_608), .ZN(n_0_607) + ); + INV_X1_LVT i_0_747( + .A(op1[13]), .ZN(n_0_714) + ); + NOR2_X1_LVT i_0_638( + .A1(n_0_738), .A2(op2[3]), .ZN(n_0_606) + ); + INV_X1_LVT i_0_743( + .A(op1[29]), .ZN(n_0_710) + ); + AOI221_X1_LVT i_0_636( + .A(op2[2]), .B1(n_0_714), .B2(n_0_606), .C1(n_0_710), .C2(n_0_616), .ZN(n_0_604) + ); + OAI22_X1_LVT i_0_635( + .A1(op2[4]), .A2(op1[17]), .B1(n_0_738), .B2(op1[1]), .ZN(n_0_603) + ); + INV_X1_LVT i_0_755( + .A(op1[9]), .ZN(n_0_722) + ); + INV_X1_LVT i_0_637( + .A(n_0_606), .ZN(n_0_605) + ); + INV_X1_LVT i_0_732( + .A(op1[25]), .ZN(n_0_699) + ); + OAI222_X1_LVT i_0_634( + .A1(n_0_723), .A2(n_0_603), .B1(n_0_722), .B2(n_0_605), .C1(n_0_699), .C2(n_0_615), + .ZN(n_0_602) + ); + AOI22_X1_LVT i_0_633( + .A1(n_0_607), .A2(n_0_604), .B1(op2[2]), .B2(n_0_602), .ZN(n_0_601) + ); + OAI221_X1_LVT i_0_616( + .A(n_0_701), .B1(op2[1]), .B2(n_0_609), .C1(n_0_728), .C2(n_0_601), .ZN(n_0_584) + ); + INV_X1_LVT i_0_729( + .A(op1[12]), .ZN(n_0_696) + ); + INV_X1_LVT i_0_731( + .A(op1[28]), .ZN(n_0_698) + ); + AOI22_X1_LVT i_0_622( + .A1(n_0_696), .A2(n_0_606), .B1(n_0_698), .B2(n_0_616), .ZN(n_0_590) + ); + INV_X1_LVT i_0_726( + .A(op2[2]), .ZN(n_0_693) + ); + NOR2_X1_LVT i_0_701( + .A1(n_0_738), .A2(op1[4]), .ZN(n_0_668) + ); + INV_X1_LVT i_0_760( + .A(op1[20]), .ZN(n_0_727) + ); + AOI21_X1_LVT i_0_623( + .A(n_0_668), .B1(n_0_738), .B2(n_0_727), .ZN(n_0_591) + ); + OAI211_X1_LVT i_0_621( + .A(n_0_590), .B(n_0_693), .C1(n_0_723), .C2(n_0_591), .ZN(n_0_589) + ); + OAI22_X1_LVT i_0_626( + .A1(op1[16]), .A2(op2[4]), .B1(n_0_738), .B2(op1[0]), .ZN(n_0_594) + ); + INV_X1_LVT i_0_769( + .A(op1[24]), .ZN(n_0_736) + ); + OAI22_X1_LVT i_0_625( + .A1(n_0_723), .A2(n_0_594), .B1(n_0_736), .B2(n_0_615), .ZN(n_0_593) + ); + AOI21_X1_LVT i_0_624( + .A(n_0_593), .B1(op1[8]), .B2(n_0_606), .ZN(n_0_592) + ); + OAI21_X1_LVT i_0_620( + .A(n_0_589), .B1(n_0_693), .B2(n_0_592), .ZN(n_0_588) + ); + INV_X1_LVT i_0_737( + .A(op1[6]), .ZN(n_0_704) + ); + INV_X1_LVT i_0_720( + .A(op1[22]), .ZN(n_0_687) + ); + OAI22_X1_LVT i_0_632( + .A1(n_0_738), .A2(n_0_704), .B1(op2[4]), .B2(n_0_687), .ZN(n_0_600) + ); + OAI221_X1_LVT i_0_631( + .A(n_0_693), .B1(n_0_723), .B2(n_0_600), .C1(op1[14]), .C2(n_0_605), .ZN(n_0_599) + ); + INV_X1_LVT i_0_750( + .A(op1[30]), .ZN(n_0_717) + ); + AOI21_X1_LVT i_0_630( + .A(n_0_599), .B1(n_0_717), .B2(n_0_616), .ZN(n_0_598) + ); + INV_X1_LVT i_0_738( + .A(op1[18]), .ZN(n_0_705) + ); + NOR2_X1_LVT i_0_628( + .A1(n_0_705), .A2(n_0_617), .ZN(n_0_596) + ); + INV_X1_LVT i_0_727( + .A(op1[2]), .ZN(n_0_694) + ); + INV_X1_LVT i_0_766( + .A(op1[10]), .ZN(n_0_733) + ); + OAI22_X1_LVT i_0_629( + .A1(n_0_723), .A2(n_0_694), .B1(n_0_733), .B2(op2[3]), .ZN(n_0_597) + ); + AOI221_X1_LVT i_0_627( + .A(n_0_596), .B1(op1[26]), .B2(n_0_616), .C1(op2[4]), .C2(n_0_597), .ZN(n_0_595) + ); + OAI21_X1_LVT i_0_619( + .A(n_0_728), .B1(n_0_693), .B2(n_0_595), .ZN(n_0_587) + ); + OAI22_X1_LVT i_0_618( + .A1(n_0_728), .A2(n_0_588), .B1(n_0_598), .B2(n_0_587), .ZN(n_0_586) + ); + INV_X1_LVT i_0_617( + .A(n_0_586), .ZN(n_0_585) + ); + OAI21_X1_LVT i_0_615( + .A(n_0_584), .B1(n_0_701), .B2(n_0_585), .ZN(n_0_583) + ); + NOR2_X1_LVT i_0_607( + .A1(op2[4]), .A2(op2[2]), .ZN(n_0_575) + ); + NAND2_X1_LVT i_0_606( + .A1(n_0_723), .A2(n_0_575), .ZN(n_0_574) + ); + INV_X1_LVT i_0_605( + .A(n_0_574), .ZN(n_0_573) + ); + NAND2_X1_LVT i_0_604( + .A1(n_0_728), .A2(n_0_573), .ZN(n_0_572) + ); + NAND2_X1_LVT i_0_611( + .A1(aluOp[2]), .A2(n_0_622), .ZN(n_0_579) + ); + INV_X1_LVT i_0_610( + .A(n_0_579), .ZN(n_0_578) + ); + NAND2_X1_LVT i_0_594( + .A1(n_0_701), .A2(n_0_578), .ZN(n_0_562) + ); + NOR3_X1_LVT i_0_592( + .A1(aluNegAr), .A2(n_0_572), .A3(n_0_562), .ZN(n_0_560) + ); + INV_X1_LVT i_0_600( + .A(n_0_569), .ZN(n_0_568) + ); + OAI21_X1_LVT i_0_595( + .A(n_0_568), .B1(aluOp[1]), .B2(n_0_570), .ZN(n_0_563) + ); + AOI211_X1_LVT i_0_591( + .A(aluBypass), .B(n_0_560), .C1(n_0_692), .C2(n_0_563), .ZN(n_0_559) + ); + OAI221_X1_LVT i_0_586( + .A(n_0_555), .B1(n_0_621), .B2(n_0_583), .C1(n_0_691), .C2(n_0_559), .ZN(result[31]) + ); + NAND2_X1_LVT i_10_150( + .A1(n_10_118), .A2(n_10_119), .ZN(n_10_120) + ); + XNOR2_X1_LVT i_10_151( + .A(n_10_116), .B(n_10_120), .ZN(n_62) + ); + AOI22_X1_LVT i_0_580( + .A1(n_62), .A2(n_0_580), .B1(n_30), .B2(n_0_581), .ZN(n_0_549) + ); + NAND2_X1_LVT i_0_576( + .A1(aluNegAr), .A2(n_0_578), .ZN(n_0_545) + ); + INV_X1_LVT i_0_603( + .A(n_0_572), .ZN(n_0_571) + ); + NOR3_X1_LVT i_0_574( + .A1(n_0_691), .A2(n_0_545), .A3(n_0_571), .ZN(n_0_543) + ); + AOI22_X1_LVT i_0_573( + .A1(n_0_717), .A2(n_0_565), .B1(op1[30]), .B2(n_0_566), .ZN(n_0_542) + ); + AOI21_X1_LVT i_0_572( + .A(n_0_543), .B1(op2[30]), .B2(n_0_542), .ZN(n_0_541) + ); + NAND2_X1_LVT i_0_579( + .A1(op2[0]), .A2(n_0_578), .ZN(n_0_548) + ); + NAND2_X1_LVT i_0_577( + .A1(op1[31]), .A2(n_0_571), .ZN(n_0_546) + ); + OAI211_X1_LVT i_0_571( + .A(n_0_549), .B(n_0_541), .C1(n_0_548), .C2(n_0_546), .ZN(n_0_540) + ); + OAI221_X1_LVT i_0_581( + .A(n_0_681), .B1(op2[30]), .B2(n_0_568), .C1(n_0_572), .C2(n_0_562), .ZN(n_0_550) + ); + AOI21_X1_LVT i_0_570( + .A(n_0_540), .B1(op1[30]), .B2(n_0_550), .ZN(n_0_539) + ); + INV_X1_LVT i_0_752( + .A(op1[23]), .ZN(n_0_719) + ); + OAI222_X1_LVT i_0_585( + .A1(n_0_713), .A2(n_0_605), .B1(n_0_719), .B2(n_0_615), .C1(n_0_734), .C2(n_0_617), + .ZN(n_0_554) + ); + AOI22_X1_LVT i_0_584( + .A1(op2[2]), .A2(n_0_554), .B1(n_0_693), .B2(n_0_610), .ZN(n_0_553) + ); + OAI22_X1_LVT i_0_583( + .A1(n_0_728), .A2(n_0_553), .B1(op2[1]), .B2(n_0_601), .ZN(n_0_552) + ); + AOI22_X1_LVT i_0_582( + .A1(n_0_701), .A2(n_0_585), .B1(op2[0]), .B2(n_0_552), .ZN(n_0_551) + ); + OAI21_X1_LVT i_0_569( + .A(n_0_539), .B1(n_0_621), .B2(n_0_551), .ZN(result[30]) + ); + INV_X1_LVT i_0_578( + .A(n_0_548), .ZN(n_0_547) + ); + NAND3_X1_LVT i_0_562( + .A1(op1[30]), .A2(n_0_571), .A3(n_0_547), .ZN(n_0_532) + ); + XNOR2_X1_LVT i_10_144( + .A(n_10_113), .B(n_10_114), .ZN(n_61) + ); + NAND2_X1_LVT i_0_558( + .A1(n_61), .A2(n_0_580), .ZN(n_0_528) + ); + OAI21_X1_LVT i_0_557( + .A(n_0_681), .B1(op2[29]), .B2(n_0_568), .ZN(n_0_527) + ); + NAND2_X1_LVT i_0_556( + .A1(op1[29]), .A2(n_0_566), .ZN(n_0_526) + ); + AOI22_X1_LVT i_0_555( + .A1(op1[29]), .A2(n_0_527), .B1(op2[29]), .B2(n_0_526), .ZN(n_0_525) + ); + AOI21_X1_LVT i_0_554( + .A(n_0_525), .B1(n_0_710), .B2(n_0_565), .ZN(n_0_524) + ); + AOI211_X1_LVT i_0_553( + .A(n_0_543), .B(n_0_524), .C1(n_29), .C2(n_0_581), .ZN(n_0_523) + ); + AND3_X1_LVT i_0_552( + .A1(n_0_532), .A2(n_0_528), .A3(n_0_523), .ZN(n_0_522) + ); + INV_X1_LVT i_0_652( + .A(n_0_621), .ZN(n_0_620) + ); + NAND2_X1_LVT i_0_565( + .A1(n_0_728), .A2(n_0_588), .ZN(n_0_535) + ); + AOI22_X1_LVT i_0_568( + .A1(n_0_723), .A2(n_0_600), .B1(op1[14]), .B2(n_0_618), .ZN(n_0_538) + ); + AOI22_X1_LVT i_0_567( + .A1(n_0_693), .A2(n_0_595), .B1(op2[2]), .B2(n_0_538), .ZN(n_0_537) + ); + INV_X1_LVT i_0_566( + .A(n_0_537), .ZN(n_0_536) + ); + OAI21_X1_LVT i_0_564( + .A(n_0_535), .B1(n_0_728), .B2(n_0_536), .ZN(n_0_534) + ); + OAI221_X1_LVT i_0_563( + .A(n_0_620), .B1(op2[0]), .B2(n_0_552), .C1(n_0_701), .C2(n_0_534), .ZN(n_0_533) + ); + NAND2_X1_LVT i_0_561( + .A1(op2[1]), .A2(n_0_573), .ZN(n_0_531) + ); + INV_X1_LVT i_0_560( + .A(n_0_531), .ZN(n_0_530) + ); + AOI22_X1_LVT i_0_559( + .A1(op1[31]), .A2(n_0_530), .B1(op1[29]), .B2(n_0_571), .ZN(n_0_529) + ); + OAI211_X1_LVT i_0_551( + .A(n_0_522), .B(n_0_533), .C1(n_0_562), .C2(n_0_529), .ZN(result[29]) + ); + INV_X1_LVT i_0_733( + .A(op2[28]), .ZN(n_0_700) + ); + AOI221_X1_LVT i_0_546( + .A(n_0_700), .B1(op1[28]), .B2(n_0_566), .C1(n_0_698), .C2(n_0_565), .ZN(n_0_517) + ); + OAI21_X1_LVT i_0_543( + .A(n_0_681), .B1(op2[28]), .B2(n_0_568), .ZN(n_0_514) + ); + AOI22_X1_LVT i_0_542( + .A1(n_28), .A2(n_0_581), .B1(op1[28]), .B2(n_0_514), .ZN(n_0_513) + ); + XNOR2_X1_LVT i_10_140( + .A(n_10_110), .B(n_10_111), .ZN(n_60) + ); + NAND2_X1_LVT i_0_544( + .A1(n_60), .A2(n_0_580), .ZN(n_0_515) + ); + NAND2_X1_LVT i_0_545( + .A1(op1[31]), .A2(n_0_574), .ZN(n_0_516) + ); + OAI211_X1_LVT i_0_541( + .A(n_0_513), .B(n_0_515), .C1(n_0_545), .C2(n_0_516), .ZN(n_0_512) + ); + AOI22_X1_LVT i_0_540( + .A1(op1[30]), .A2(n_0_530), .B1(op1[28]), .B2(n_0_571), .ZN(n_0_511) + ); + OAI22_X1_LVT i_0_539( + .A1(n_0_562), .A2(n_0_511), .B1(n_0_548), .B2(n_0_529), .ZN(n_0_510) + ); + NOR3_X1_LVT i_0_538( + .A1(n_0_517), .A2(n_0_512), .A3(n_0_510), .ZN(n_0_509) + ); + OAI22_X1_LVT i_0_550( + .A1(n_0_714), .A2(n_0_617), .B1(op2[3]), .B2(n_0_608), .ZN(n_0_521) + ); + OAI22_X1_LVT i_0_549( + .A1(op2[2]), .A2(n_0_602), .B1(n_0_693), .B2(n_0_521), .ZN(n_0_520) + ); + AOI22_X1_LVT i_0_548( + .A1(op2[1]), .A2(n_0_520), .B1(n_0_728), .B2(n_0_553), .ZN(n_0_519) + ); + OAI22_X1_LVT i_0_547( + .A1(op2[0]), .A2(n_0_534), .B1(n_0_701), .B2(n_0_519), .ZN(n_0_518) + ); + OAI21_X1_LVT i_0_537( + .A(n_0_509), .B1(n_0_621), .B2(n_0_518), .ZN(result[28]) + ); + XNOR2_X1_LVT i_10_136( + .A(n_10_107), .B(n_10_108), .ZN(n_59) + ); + AOI22_X1_LVT i_0_517( + .A1(n_27), .A2(n_0_581), .B1(n_59), .B2(n_0_580), .ZN(n_0_489) + ); + INV_X1_LVT i_0_721( + .A(op1[27]), .ZN(n_0_688) + ); + OAI21_X1_LVT i_0_516( + .A(n_0_681), .B1(op2[27]), .B2(n_0_568), .ZN(n_0_488) + ); + INV_X1_LVT i_0_515( + .A(n_0_488), .ZN(n_0_487) + ); + OAI221_X1_LVT i_0_514( + .A(n_0_489), .B1(n_0_545), .B2(n_0_516), .C1(n_0_688), .C2(n_0_487), .ZN(n_0_486) + ); + OAI21_X1_LVT i_0_530( + .A(op2[1]), .B1(n_0_710), .B2(n_0_574), .ZN(n_0_502) + ); + OAI21_X1_LVT i_0_529( + .A(n_0_728), .B1(n_0_688), .B2(n_0_574), .ZN(n_0_501) + ); + NAND2_X1_LVT i_0_528( + .A1(n_0_502), .A2(n_0_501), .ZN(n_0_500) + ); + AOI21_X1_LVT i_0_527( + .A(n_0_545), .B1(n_0_701), .B2(n_0_500), .ZN(n_0_499) + ); + NAND2_X1_LVT i_0_609( + .A1(n_0_682), .A2(n_0_578), .ZN(n_0_577) + ); + NOR2_X1_LVT i_0_526( + .A1(op2[4]), .A2(n_0_693), .ZN(n_0_498) + ); + NAND2_X1_LVT i_0_525( + .A1(n_0_723), .A2(n_0_498), .ZN(n_0_497) + ); + OAI22_X1_LVT i_0_523( + .A1(n_0_688), .A2(n_0_574), .B1(n_0_691), .B2(n_0_497), .ZN(n_0_495) + ); + OAI21_X1_LVT i_0_522( + .A(n_0_502), .B1(op2[1]), .B2(n_0_495), .ZN(n_0_494) + ); + AOI21_X1_LVT i_0_521( + .A(n_0_577), .B1(n_0_701), .B2(n_0_494), .ZN(n_0_493) + ); + NOR2_X1_LVT i_0_520( + .A1(n_0_499), .A2(n_0_493), .ZN(n_0_492) + ); + AOI21_X1_LVT i_0_519( + .A(n_0_492), .B1(op2[0]), .B2(n_0_511), .ZN(n_0_491) + ); + AOI22_X1_LVT i_0_518( + .A1(n_0_688), .A2(n_0_565), .B1(op1[27]), .B2(n_0_566), .ZN(n_0_490) + ); + AOI211_X1_LVT i_0_513( + .A(n_0_486), .B(n_0_491), .C1(op2[27]), .C2(n_0_490), .ZN(n_0_485) + ); + NOR3_X1_LVT i_0_536( + .A1(op2[4]), .A2(n_0_696), .A3(n_0_723), .ZN(n_0_508) + ); + AOI21_X1_LVT i_0_535( + .A(n_0_508), .B1(n_0_723), .B2(n_0_591), .ZN(n_0_507) + ); + OAI22_X1_LVT i_0_534( + .A1(op2[2]), .A2(n_0_592), .B1(n_0_693), .B2(n_0_507), .ZN(n_0_506) + ); + NOR2_X1_LVT i_0_533( + .A1(n_0_728), .A2(n_0_506), .ZN(n_0_505) + ); + AOI21_X1_LVT i_0_532( + .A(n_0_505), .B1(n_0_728), .B2(n_0_536), .ZN(n_0_504) + ); + OAI22_X1_LVT i_0_531( + .A1(n_0_701), .A2(n_0_504), .B1(op2[0]), .B2(n_0_519), .ZN(n_0_503) + ); + OAI21_X1_LVT i_0_512( + .A(n_0_485), .B1(n_0_621), .B2(n_0_503), .ZN(result[27]) + ); + OAI21_X1_LVT i_0_500( + .A(n_0_681), .B1(op2[26]), .B2(n_0_568), .ZN(n_0_473) + ); + NAND2_X1_LVT i_0_499( + .A1(op1[26]), .A2(n_0_473), .ZN(n_0_472) + ); + XNOR2_X1_LVT i_10_133( + .A(n_10_103), .B(n_10_106), .ZN(n_58) + ); + AOI22_X1_LVT i_0_498( + .A1(n_58), .A2(n_0_580), .B1(n_26), .B2(n_0_581), .ZN(n_0_471) + ); + INV_X1_LVT i_0_744( + .A(op1[26]), .ZN(n_0_711) + ); + OAI221_X1_LVT i_0_501( + .A(op2[26]), .B1(op1[26]), .B2(n_0_564), .C1(n_0_711), .C2(n_0_567), .ZN(n_0_474) + ); + NAND3_X1_LVT i_0_497( + .A1(n_0_472), .A2(n_0_471), .A3(n_0_474), .ZN(n_0_470) + ); + INV_X1_LVT i_0_524( + .A(n_0_497), .ZN(n_0_496) + ); + AOI22_X1_LVT i_0_505( + .A1(op1[30]), .A2(n_0_496), .B1(op1[26]), .B2(n_0_573), .ZN(n_0_478) + ); + NOR2_X1_LVT i_0_504( + .A1(op2[1]), .A2(n_0_478), .ZN(n_0_477) + ); + AOI21_X1_LVT i_0_503( + .A(n_0_477), .B1(op1[28]), .B2(n_0_530), .ZN(n_0_476) + ); + NAND2_X1_LVT i_0_502( + .A1(n_0_701), .A2(n_0_476), .ZN(n_0_475) + ); + AOI21_X1_LVT i_0_489( + .A(n_0_577), .B1(op2[0]), .B2(n_0_494), .ZN(n_0_462) + ); + AOI21_X1_LVT i_0_488( + .A(n_0_470), .B1(n_0_475), .B2(n_0_462), .ZN(n_0_461) + ); + AOI21_X1_LVT i_0_511( + .A(n_0_616), .B1(n_0_738), .B2(n_0_706), .ZN(n_0_484) + ); + AOI21_X1_LVT i_0_510( + .A(n_0_484), .B1(n_0_723), .B2(op1[19]), .ZN(n_0_483) + ); + INV_X1_LVT i_0_757( + .A(op1[3]), .ZN(n_0_724) + ); + NOR2_X1_LVT i_0_687( + .A1(n_0_724), .A2(op2[3]), .ZN(n_0_654) + ); + INV_X1_LVT i_0_686( + .A(n_0_654), .ZN(n_0_653) + ); + AOI21_X1_LVT i_0_509( + .A(n_0_483), .B1(op2[4]), .B2(n_0_653), .ZN(n_0_482) + ); + AOI22_X1_LVT i_0_508( + .A1(n_0_693), .A2(n_0_554), .B1(op2[2]), .B2(n_0_482), .ZN(n_0_481) + ); + OAI22_X1_LVT i_0_507( + .A1(n_0_728), .A2(n_0_481), .B1(op2[1]), .B2(n_0_520), .ZN(n_0_480) + ); + AOI22_X1_LVT i_0_506( + .A1(op2[0]), .A2(n_0_480), .B1(n_0_701), .B2(n_0_504), .ZN(n_0_479) + ); + NAND3_X1_LVT i_0_491( + .A1(op2[0]), .A2(n_0_516), .A3(n_0_500), .ZN(n_0_464) + ); + NAND2_X1_LVT i_0_494( + .A1(op1[31]), .A2(n_0_615), .ZN(n_0_467) + ); + OAI21_X1_LVT i_0_492( + .A(n_0_467), .B1(n_0_728), .B2(n_0_516), .ZN(n_0_465) + ); + OAI21_X1_LVT i_0_490( + .A(n_0_464), .B1(n_0_475), .B2(n_0_465), .ZN(n_0_463) + ); + OAI221_X1_LVT i_0_487( + .A(n_0_461), .B1(n_0_621), .B2(n_0_479), .C1(n_0_545), .C2(n_0_463), .ZN(result[26]) + ); + INV_X1_LVT i_10_126( + .A(n_10_100), .ZN(n_10_101) + ); + NOR2_X1_LVT i_10_127( + .A1(n_10_99), .A2(n_10_101), .ZN(n_10_102) + ); + XNOR2_X1_LVT i_10_128( + .A(n_10_97), .B(n_10_102), .ZN(n_57) + ); + AOI22_X1_LVT i_0_479( + .A1(n_57), .A2(n_0_580), .B1(n_25), .B2(n_0_581), .ZN(n_0_453) + ); + INV_X1_LVT i_0_730( + .A(op2[25]), .ZN(n_0_697) + ); + AOI21_X1_LVT i_0_478( + .A(aluBypass), .B1(n_0_697), .B2(n_0_569), .ZN(n_0_452) + ); + AOI22_X1_LVT i_0_480( + .A1(op1[25]), .A2(n_0_567), .B1(n_0_699), .B2(n_0_564), .ZN(n_0_454) + ); + OAI221_X1_LVT i_0_477( + .A(n_0_453), .B1(n_0_699), .B2(n_0_452), .C1(n_0_697), .C2(n_0_454), .ZN(n_0_451) + ); + INV_X1_LVT i_0_575( + .A(n_0_545), .ZN(n_0_544) + ); + AOI21_X1_LVT i_0_476( + .A(n_0_451), .B1(n_0_544), .B2(n_0_465), .ZN(n_0_450) + ); + AOI22_X1_LVT i_0_475( + .A1(op1[29]), .A2(n_0_496), .B1(op1[25]), .B2(n_0_573), .ZN(n_0_449) + ); + NAND2_X1_LVT i_0_474( + .A1(n_0_728), .A2(n_0_449), .ZN(n_0_448) + ); + OAI21_X1_LVT i_0_473( + .A(n_0_448), .B1(n_0_728), .B2(n_0_495), .ZN(n_0_447) + ); + OAI22_X1_LVT i_0_472( + .A1(n_0_548), .A2(n_0_476), .B1(n_0_562), .B2(n_0_447), .ZN(n_0_446) + ); + INV_X1_LVT i_0_471( + .A(n_0_446), .ZN(n_0_445) + ); + OAI222_X1_LVT i_0_486( + .A1(n_0_733), .A2(n_0_617), .B1(n_0_694), .B2(n_0_605), .C1(n_0_705), .C2(n_0_615), + .ZN(n_0_460) + ); + NOR2_X1_LVT i_0_485( + .A1(n_0_693), .A2(n_0_460), .ZN(n_0_459) + ); + AOI21_X1_LVT i_0_484( + .A(n_0_459), .B1(n_0_693), .B2(n_0_538), .ZN(n_0_458) + ); + OAI22_X1_LVT i_0_483( + .A1(n_0_728), .A2(n_0_458), .B1(op2[1]), .B2(n_0_506), .ZN(n_0_457) + ); + INV_X1_LVT i_0_482( + .A(n_0_457), .ZN(n_0_456) + ); + OAI221_X1_LVT i_0_481( + .A(n_0_620), .B1(n_0_701), .B2(n_0_456), .C1(op2[0]), .C2(n_0_480), .ZN(n_0_455) + ); + NAND3_X1_LVT i_0_470( + .A1(n_0_450), .A2(n_0_445), .A3(n_0_455), .ZN(result[25]) + ); + INV_X1_LVT i_0_493( + .A(n_0_467), .ZN(n_0_466) + ); + OAI211_X1_LVT i_0_455( + .A(n_0_544), .B(n_0_465), .C1(op2[0]), .C2(n_0_466), .ZN(n_0_430) + ); + OAI21_X1_LVT i_0_462( + .A(n_0_681), .B1(op2[24]), .B2(n_0_568), .ZN(n_0_437) + ); + XNOR2_X1_LVT i_10_120( + .A(n_10_94), .B(n_10_95), .ZN(n_56) + ); + AOI222_X1_LVT i_0_461( + .A1(op1[24]), .A2(n_0_437), .B1(n_56), .B2(n_0_580), .C1(n_24), .C2(n_0_581), + .ZN(n_0_436) + ); + INV_X1_LVT i_0_460( + .A(n_0_436), .ZN(n_0_435) + ); + AOI22_X1_LVT i_0_458( + .A1(op1[24]), .A2(n_0_573), .B1(op1[28]), .B2(n_0_496), .ZN(n_0_433) + ); + OAI22_X1_LVT i_0_457( + .A1(op2[1]), .A2(n_0_433), .B1(n_0_728), .B2(n_0_478), .ZN(n_0_432) + ); + INV_X1_LVT i_0_456( + .A(n_0_432), .ZN(n_0_431) + ); + OAI22_X1_LVT i_0_454( + .A1(n_0_562), .A2(n_0_431), .B1(n_0_548), .B2(n_0_447), .ZN(n_0_429) + ); + AOI22_X1_LVT i_0_459( + .A1(n_0_736), .A2(n_0_565), .B1(op1[24]), .B2(n_0_566), .ZN(n_0_434) + ); + AOI211_X1_LVT i_0_453( + .A(n_0_435), .B(n_0_429), .C1(op2[24]), .C2(n_0_434), .ZN(n_0_428) + ); + NAND2_X1_LVT i_0_467( + .A1(n_0_693), .A2(n_0_521), .ZN(n_0_442) + ); + NOR2_X1_LVT i_0_469( + .A1(op2[3]), .A2(n_0_603), .ZN(n_0_444) + ); + AOI21_X1_LVT i_0_468( + .A(n_0_444), .B1(op1[9]), .B2(n_0_618), .ZN(n_0_443) + ); + OAI21_X1_LVT i_0_466( + .A(n_0_442), .B1(n_0_693), .B2(n_0_443), .ZN(n_0_441) + ); + NAND2_X1_LVT i_0_465( + .A1(op2[1]), .A2(n_0_441), .ZN(n_0_440) + ); + OAI21_X1_LVT i_0_464( + .A(n_0_440), .B1(op2[1]), .B2(n_0_481), .ZN(n_0_439) + ); + OAI221_X1_LVT i_0_463( + .A(n_0_620), .B1(op2[0]), .B2(n_0_456), .C1(n_0_701), .C2(n_0_439), .ZN(n_0_438) + ); + NAND3_X1_LVT i_0_452( + .A1(n_0_430), .A2(n_0_428), .A3(n_0_438), .ZN(result[24]) + ); + INV_X1_LVT i_0_751( + .A(op2[23]), .ZN(n_0_718) + ); + AOI221_X1_LVT i_0_440( + .A(n_0_718), .B1(op1[23]), .B2(n_0_566), .C1(n_0_719), .C2(n_0_565), .ZN(n_0_416) + ); + INV_X1_LVT i_10_115( + .A(n_10_91), .ZN(n_10_92) + ); + NOR2_X1_LVT i_10_116( + .A1(n_10_90), .A2(n_10_92), .ZN(n_10_93) + ); + XNOR2_X1_LVT i_10_117( + .A(n_10_88), .B(n_10_93), .ZN(n_55) + ); + AOI222_X1_LVT i_0_438( + .A1(n_23), .A2(n_0_581), .B1(n_0_544), .B2(n_0_466), .C1(n_55), .C2(n_0_580), + .ZN(n_0_414) + ); + OAI21_X1_LVT i_0_437( + .A(n_0_414), .B1(n_0_548), .B2(n_0_431), .ZN(n_0_413) + ); + OAI21_X1_LVT i_0_439( + .A(n_0_681), .B1(op2[23]), .B2(n_0_568), .ZN(n_0_415) + ); + AOI211_X1_LVT i_0_436( + .A(n_0_416), .B(n_0_413), .C1(op1[23]), .C2(n_0_415), .ZN(n_0_412) + ); + AOI22_X1_LVT i_0_444( + .A1(n_0_723), .A2(n_0_719), .B1(op2[3]), .B2(n_0_691), .ZN(n_0_420) + ); + AOI22_X1_LVT i_0_443( + .A1(n_0_575), .A2(n_0_420), .B1(op1[27]), .B2(n_0_496), .ZN(n_0_419) + ); + AOI22_X1_LVT i_0_442( + .A1(op2[1]), .A2(n_0_449), .B1(n_0_728), .B2(n_0_419), .ZN(n_0_418) + ); + INV_X1_LVT i_0_441( + .A(n_0_418), .ZN(n_0_417) + ); + NAND2_X1_LVT i_0_447( + .A1(n_0_728), .A2(n_0_458), .ZN(n_0_423) + ); + NOR2_X1_LVT i_0_451( + .A1(op2[3]), .A2(n_0_594), .ZN(n_0_427) + ); + AOI21_X1_LVT i_0_450( + .A(n_0_427), .B1(op1[8]), .B2(n_0_618), .ZN(n_0_426) + ); + OAI22_X1_LVT i_0_449( + .A1(n_0_693), .A2(n_0_426), .B1(op2[2]), .B2(n_0_507), .ZN(n_0_425) + ); + INV_X1_LVT i_0_448( + .A(n_0_425), .ZN(n_0_424) + ); + OAI21_X1_LVT i_0_446( + .A(n_0_423), .B1(n_0_728), .B2(n_0_424), .ZN(n_0_422) + ); + AOI22_X1_LVT i_0_445( + .A1(op2[0]), .A2(n_0_422), .B1(n_0_701), .B2(n_0_439), .ZN(n_0_421) + ); + OAI221_X1_LVT i_0_435( + .A(n_0_412), .B1(n_0_562), .B2(n_0_417), .C1(n_0_621), .C2(n_0_421), .ZN(result[23]) + ); + XNOR2_X1_LVT i_10_109( + .A(n_10_85), .B(n_10_86), .ZN(n_54) + ); + AOI22_X1_LVT i_0_419( + .A1(n_54), .A2(n_0_580), .B1(n_22), .B2(n_0_581), .ZN(n_0_396) + ); + INV_X1_LVT i_0_719( + .A(op2[22]), .ZN(n_0_686) + ); + AOI21_X1_LVT i_0_420( + .A(aluBypass), .B1(n_0_686), .B2(n_0_569), .ZN(n_0_397) + ); + OAI21_X1_LVT i_0_418( + .A(n_0_396), .B1(n_0_687), .B2(n_0_397), .ZN(n_0_395) + ); + AOI22_X1_LVT i_0_421( + .A1(op1[22]), .A2(n_0_566), .B1(n_0_687), .B2(n_0_565), .ZN(n_0_398) + ); + AOI21_X1_LVT i_0_417( + .A(n_0_395), .B1(op2[22]), .B2(n_0_398), .ZN(n_0_394) + ); + NAND2_X1_LVT i_0_432( + .A1(n_0_728), .A2(n_0_441), .ZN(n_0_409) + ); + AND2_X1_LVT i_0_434( + .A1(n_0_738), .A2(n_0_619), .ZN(n_0_411) + ); + AOI22_X1_LVT i_0_433( + .A1(n_0_693), .A2(n_0_482), .B1(op2[2]), .B2(n_0_411), .ZN(n_0_410) + ); + OAI21_X1_LVT i_0_431( + .A(n_0_409), .B1(n_0_728), .B2(n_0_410), .ZN(n_0_408) + ); + OAI22_X1_LVT i_0_430( + .A1(n_0_701), .A2(n_0_408), .B1(op2[0]), .B2(n_0_422), .ZN(n_0_407) + ); + AOI22_X1_LVT i_0_429( + .A1(n_0_723), .A2(n_0_687), .B1(op2[3]), .B2(n_0_717), .ZN(n_0_406) + ); + AOI22_X1_LVT i_0_428( + .A1(n_0_575), .A2(n_0_406), .B1(op1[26]), .B2(n_0_496), .ZN(n_0_405) + ); + AND2_X1_LVT i_0_427( + .A1(n_0_728), .A2(n_0_405), .ZN(n_0_404) + ); + AOI21_X1_LVT i_0_426( + .A(n_0_404), .B1(op2[1]), .B2(n_0_433), .ZN(n_0_403) + ); + INV_X1_LVT i_0_425( + .A(n_0_403), .ZN(n_0_402) + ); + OAI222_X1_LVT i_0_424( + .A1(n_0_545), .A2(n_0_467), .B1(n_0_701), .B2(n_0_417), .C1(op2[0]), .C2(n_0_402), + .ZN(n_0_401) + ); + NOR2_X1_LVT i_0_496( + .A1(n_0_738), .A2(n_0_691), .ZN(n_0_469) + ); + INV_X1_LVT i_0_495( + .A(n_0_469), .ZN(n_0_468) + ); + NAND3_X1_LVT i_0_423( + .A1(n_0_693), .A2(n_0_468), .A3(n_0_404), .ZN(n_0_400) + ); + OAI21_X1_LVT i_0_422( + .A(n_0_401), .B1(op2[0]), .B2(n_0_400), .ZN(n_0_399) + ); + OAI221_X1_LVT i_0_416( + .A(n_0_394), .B1(n_0_621), .B2(n_0_407), .C1(n_0_579), .C2(n_0_399), .ZN(result[22]) + ); + INV_X1_LVT i_0_759( + .A(op1[21]), .ZN(n_0_726) + ); + AOI22_X1_LVT i_0_399( + .A1(op1[21]), .A2(n_0_566), .B1(n_0_726), .B2(n_0_565), .ZN(n_0_377) + ); + NOR2_X1_LVT i_0_692( + .A1(n_0_726), .A2(op2[21]), .ZN(n_0_659) + ); + AOI222_X1_LVT i_0_398( + .A1(op2[21]), .A2(n_0_377), .B1(n_21), .B2(n_0_581), .C1(n_0_659), .C2(n_0_569), + .ZN(n_0_376) + ); + INV_X1_LVT i_0_397( + .A(n_0_376), .ZN(n_0_375) + ); + INV_X1_LVT i_10_104( + .A(n_10_82), .ZN(n_10_83) + ); + NOR2_X1_LVT i_10_105( + .A1(n_10_81), .A2(n_10_83), .ZN(n_10_84) + ); + XNOR2_X1_LVT i_10_106( + .A(n_10_79), .B(n_10_84), .ZN(n_53) + ); + AOI221_X1_LVT i_0_396( + .A(n_0_375), .B1(n_53), .B2(n_0_580), .C1(op1[21]), .C2(aluBypass), .ZN(n_0_374) + ); + INV_X1_LVT i_0_608( + .A(n_0_577), .ZN(n_0_576) + ); + NAND2_X1_LVT i_0_403( + .A1(op2[0]), .A2(n_0_402), .ZN(n_0_381) + ); + AND2_X1_LVT i_0_410( + .A1(op2[1]), .A2(n_0_419), .ZN(n_0_388) + ); + OAI22_X1_LVT i_0_408( + .A1(n_0_723), .A2(n_0_710), .B1(n_0_726), .B2(op2[3]), .ZN(n_0_386) + ); + AOI22_X1_LVT i_0_407( + .A1(n_0_575), .A2(n_0_386), .B1(op1[25]), .B2(n_0_496), .ZN(n_0_385) + ); + AOI21_X1_LVT i_0_395( + .A(n_0_388), .B1(n_0_728), .B2(n_0_385), .ZN(n_0_373) + ); + OAI211_X1_LVT i_0_394( + .A(n_0_576), .B(n_0_381), .C1(op2[0]), .C2(n_0_373), .ZN(n_0_372) + ); + AOI21_X1_LVT i_0_402( + .A(n_0_381), .B1(n_0_466), .B2(n_0_400), .ZN(n_0_380) + ); + INV_X1_LVT i_0_401( + .A(n_0_380), .ZN(n_0_379) + ); + NOR2_X1_LVT i_0_409( + .A1(n_0_575), .A2(n_0_467), .ZN(n_0_387) + ); + INV_X1_LVT i_0_406( + .A(n_0_385), .ZN(n_0_384) + ); + NOR2_X1_LVT i_0_405( + .A1(n_0_387), .A2(n_0_384), .ZN(n_0_383) + ); + AOI22_X1_LVT i_0_404( + .A1(n_0_467), .A2(n_0_388), .B1(n_0_728), .B2(n_0_383), .ZN(n_0_382) + ); + OAI211_X1_LVT i_0_400( + .A(n_0_544), .B(n_0_379), .C1(op2[0]), .C2(n_0_382), .ZN(n_0_378) + ); + AOI22_X1_LVT i_0_415( + .A1(op1[14]), .A2(n_0_616), .B1(op1[6]), .B2(n_0_618), .ZN(n_0_393) + ); + NOR2_X1_LVT i_0_414( + .A1(n_0_693), .A2(n_0_393), .ZN(n_0_392) + ); + AOI21_X1_LVT i_0_413( + .A(n_0_392), .B1(n_0_693), .B2(n_0_460), .ZN(n_0_391) + ); + OAI22_X1_LVT i_0_412( + .A1(n_0_728), .A2(n_0_391), .B1(op2[1]), .B2(n_0_424), .ZN(n_0_390) + ); + OAI221_X1_LVT i_0_411( + .A(n_0_620), .B1(op2[0]), .B2(n_0_408), .C1(n_0_701), .C2(n_0_390), .ZN(n_0_389) + ); + NAND4_X1_LVT i_0_393( + .A1(n_0_374), .A2(n_0_372), .A3(n_0_378), .A4(n_0_389), .ZN(result[21]) + ); + OAI221_X1_LVT i_0_388( + .A(op2[20]), .B1(n_0_727), .B2(n_0_567), .C1(op1[20]), .C2(n_0_564), .ZN(n_0_367) + ); + NOR2_X1_LVT i_0_691( + .A1(n_0_727), .A2(op2[20]), .ZN(n_0_658) + ); + AOI22_X1_LVT i_0_387( + .A1(op1[20]), .A2(aluBypass), .B1(n_0_658), .B2(n_0_569), .ZN(n_0_366) + ); + XNOR2_X1_LVT i_10_98( + .A(n_10_76), .B(n_10_77), .ZN(n_52) + ); + AOI22_X1_LVT i_0_386( + .A1(n_52), .A2(n_0_580), .B1(n_20), .B2(n_0_581), .ZN(n_0_365) + ); + AOI221_X1_LVT i_0_392( + .A(op2[4]), .B1(n_0_727), .B2(n_0_723), .C1(op2[3]), .C2(n_0_698), .ZN(n_0_371) + ); + AOI22_X1_LVT i_0_391( + .A1(op1[24]), .A2(n_0_496), .B1(n_0_693), .B2(n_0_371), .ZN(n_0_370) + ); + OAI22_X1_LVT i_0_390( + .A1(op2[1]), .A2(n_0_370), .B1(n_0_728), .B2(n_0_405), .ZN(n_0_369) + ); + OAI221_X1_LVT i_0_385( + .A(n_0_576), .B1(n_0_701), .B2(n_0_373), .C1(op2[0]), .C2(n_0_369), .ZN(n_0_364) + ); + AND4_X1_LVT i_0_384( + .A1(n_0_367), .A2(n_0_366), .A3(n_0_365), .A4(n_0_364), .ZN(n_0_363) + ); + AOI22_X1_LVT i_0_383( + .A1(op1[13]), .A2(n_0_616), .B1(op1[5]), .B2(n_0_618), .ZN(n_0_362) + ); + AOI22_X1_LVT i_0_382( + .A1(op2[2]), .A2(n_0_362), .B1(n_0_693), .B2(n_0_443), .ZN(n_0_361) + ); + NAND2_X1_LVT i_0_381( + .A1(op2[1]), .A2(n_0_361), .ZN(n_0_360) + ); + OAI21_X1_LVT i_0_380( + .A(n_0_360), .B1(op2[1]), .B2(n_0_410), .ZN(n_0_359) + ); + OAI221_X1_LVT i_0_379( + .A(n_0_620), .B1(n_0_701), .B2(n_0_359), .C1(op2[0]), .C2(n_0_390), .ZN(n_0_358) + ); + OR2_X1_LVT i_0_389( + .A1(n_0_387), .A2(n_0_369), .ZN(n_0_368) + ); + AOI22_X1_LVT i_0_378( + .A1(op2[0]), .A2(n_0_382), .B1(n_0_701), .B2(n_0_368), .ZN(n_0_357) + ); + OAI211_X1_LVT i_0_377( + .A(n_0_363), .B(n_0_358), .C1(n_0_545), .C2(n_0_357), .ZN(result[20]) + ); + OAI22_X1_LVT i_0_370( + .A1(op2[3]), .A2(n_0_689), .B1(n_0_723), .B2(n_0_688), .ZN(n_0_350) + ); + AND2_X1_LVT i_0_369( + .A1(n_0_738), .A2(n_0_350), .ZN(n_0_349) + ); + AOI22_X1_LVT i_0_368( + .A1(n_0_498), .A2(n_0_420), .B1(n_0_693), .B2(n_0_349), .ZN(n_0_348) + ); + AND2_X1_LVT i_0_367( + .A1(n_0_728), .A2(n_0_348), .ZN(n_0_347) + ); + AOI21_X1_LVT i_0_359( + .A(n_0_347), .B1(op2[1]), .B2(n_0_385), .ZN(n_0_339) + ); + OAI221_X1_LVT i_0_357( + .A(n_0_576), .B1(n_0_701), .B2(n_0_369), .C1(op2[0]), .C2(n_0_339), .ZN(n_0_337) + ); + NAND2_X1_LVT i_0_363( + .A1(n_19), .A2(n_0_581), .ZN(n_0_343) + ); + INV_X1_LVT i_0_723( + .A(op2[19]), .ZN(n_0_690) + ); + AOI221_X1_LVT i_0_364( + .A(n_0_690), .B1(n_0_689), .B2(n_0_565), .C1(op1[19]), .C2(n_0_566), .ZN(n_0_344) + ); + XNOR2_X1_LVT i_10_94( + .A(n_10_73), .B(n_10_74), .ZN(n_51) + ); + AOI221_X1_LVT i_0_361( + .A(n_0_344), .B1(op1[19]), .B2(aluBypass), .C1(n_51), .C2(n_0_580), .ZN(n_0_341) + ); + NAND3_X1_LVT i_0_362( + .A1(n_0_690), .A2(op1[19]), .A3(n_0_569), .ZN(n_0_342) + ); + NAND3_X1_LVT i_0_360( + .A1(n_0_343), .A2(n_0_341), .A3(n_0_342), .ZN(n_0_340) + ); + AOI22_X1_LVT i_0_376( + .A1(op1[12]), .A2(n_0_616), .B1(op1[4]), .B2(n_0_618), .ZN(n_0_356) + ); + OAI22_X1_LVT i_0_375( + .A1(n_0_693), .A2(n_0_356), .B1(op2[2]), .B2(n_0_426), .ZN(n_0_355) + ); + INV_X1_LVT i_0_374( + .A(n_0_355), .ZN(n_0_354) + ); + OAI22_X1_LVT i_0_373( + .A1(op2[1]), .A2(n_0_391), .B1(n_0_728), .B2(n_0_354), .ZN(n_0_353) + ); + AOI22_X1_LVT i_0_372( + .A1(n_0_701), .A2(n_0_359), .B1(op2[0]), .B2(n_0_353), .ZN(n_0_352) + ); + INV_X1_LVT i_0_371( + .A(n_0_352), .ZN(n_0_351) + ); + AOI21_X1_LVT i_0_358( + .A(n_0_340), .B1(n_0_620), .B2(n_0_351), .ZN(n_0_338) + ); + AOI22_X1_LVT i_0_366( + .A1(n_0_468), .A2(n_0_347), .B1(op2[1]), .B2(n_0_383), .ZN(n_0_346) + ); + AOI22_X1_LVT i_0_365( + .A1(n_0_701), .A2(n_0_346), .B1(op2[0]), .B2(n_0_368), .ZN(n_0_345) + ); + OAI211_X1_LVT i_0_356( + .A(n_0_337), .B(n_0_338), .C1(n_0_545), .C2(n_0_345), .ZN(result[19]) + ); + XNOR2_X1_LVT i_10_90( + .A(n_10_70), .B(n_10_71), .ZN(n_50) + ); + NAND2_X1_LVT i_0_342( + .A1(n_50), .A2(n_0_580), .ZN(n_0_323) + ); + OAI21_X1_LVT i_0_343( + .A(n_0_681), .B1(op2[18]), .B2(n_0_568), .ZN(n_0_324) + ); + AOI22_X1_LVT i_0_341( + .A1(op1[18]), .A2(n_0_324), .B1(n_18), .B2(n_0_581), .ZN(n_0_322) + ); + OAI221_X1_LVT i_0_340( + .A(op2[18]), .B1(n_0_705), .B2(n_0_567), .C1(op1[18]), .C2(n_0_564), .ZN(n_0_321) + ); + NAND3_X1_LVT i_0_339( + .A1(n_0_323), .A2(n_0_322), .A3(n_0_321), .ZN(n_0_320) + ); + OAI22_X1_LVT i_0_351( + .A1(op2[3]), .A2(n_0_705), .B1(n_0_723), .B2(n_0_711), .ZN(n_0_332) + ); + AND2_X1_LVT i_0_350( + .A1(n_0_738), .A2(n_0_332), .ZN(n_0_331) + ); + AOI22_X1_LVT i_0_349( + .A1(n_0_498), .A2(n_0_406), .B1(n_0_693), .B2(n_0_331), .ZN(n_0_330) + ); + NAND2_X1_LVT i_0_348( + .A1(n_0_728), .A2(n_0_330), .ZN(n_0_329) + ); + NAND2_X1_LVT i_0_347( + .A1(op2[1]), .A2(n_0_370), .ZN(n_0_328) + ); + AND2_X1_LVT i_0_338( + .A1(n_0_329), .A2(n_0_328), .ZN(n_0_319) + ); + OAI22_X1_LVT i_0_337( + .A1(op2[0]), .A2(n_0_319), .B1(n_0_701), .B2(n_0_339), .ZN(n_0_318) + ); + INV_X1_LVT i_0_336( + .A(n_0_318), .ZN(n_0_317) + ); + AOI21_X1_LVT i_0_335( + .A(n_0_320), .B1(n_0_578), .B2(n_0_317), .ZN(n_0_316) + ); + OAI22_X1_LVT i_0_346( + .A1(n_0_469), .A2(n_0_329), .B1(n_0_387), .B2(n_0_328), .ZN(n_0_327) + ); + NAND2_X1_LVT i_0_344( + .A1(n_0_544), .A2(n_0_346), .ZN(n_0_325) + ); + NAND2_X1_LVT i_0_354( + .A1(n_0_728), .A2(n_0_361), .ZN(n_0_335) + ); + AOI22_X1_LVT i_0_355( + .A1(n_0_612), .A2(n_0_498), .B1(n_0_693), .B2(n_0_411), .ZN(n_0_336) + ); + OAI21_X1_LVT i_0_353( + .A(n_0_335), .B1(n_0_728), .B2(n_0_336), .ZN(n_0_334) + ); + AOI22_X1_LVT i_0_352( + .A1(n_0_701), .A2(n_0_353), .B1(op2[0]), .B2(n_0_334), .ZN(n_0_333) + ); + OAI221_X1_LVT i_0_334( + .A(n_0_316), .B1(n_0_327), .B2(n_0_325), .C1(n_0_621), .C2(n_0_333), .ZN(result[18]) + ); + NAND2_X1_LVT i_0_325( + .A1(n_17), .A2(n_0_581), .ZN(n_0_307) + ); + INV_X1_LVT i_0_765( + .A(op1[17]), .ZN(n_0_732) + ); + AOI22_X1_LVT i_0_324( + .A1(n_0_732), .A2(n_0_565), .B1(op1[17]), .B2(n_0_566), .ZN(n_0_306) + ); + NOR2_X1_LVT i_0_693( + .A1(n_0_732), .A2(op2[17]), .ZN(n_0_660) + ); + XNOR2_X1_LVT i_10_86( + .A(n_10_67), .B(n_10_68), .ZN(n_49) + ); + AOI222_X1_LVT i_0_323( + .A1(op2[17]), .A2(n_0_306), .B1(n_0_660), .B2(n_0_569), .C1(n_49), .C2(n_0_580), + .ZN(n_0_305) + ); + OAI211_X1_LVT i_0_322( + .A(n_0_307), .B(n_0_305), .C1(n_0_732), .C2(n_0_681), .ZN(n_0_304) + ); + AOI22_X1_LVT i_0_331( + .A1(op2[3]), .A2(op1[25]), .B1(op1[17]), .B2(n_0_723), .ZN(n_0_313) + ); + NOR2_X1_LVT i_0_330( + .A1(op2[4]), .A2(n_0_313), .ZN(n_0_312) + ); + AOI22_X1_LVT i_0_329( + .A1(n_0_498), .A2(n_0_386), .B1(n_0_693), .B2(n_0_312), .ZN(n_0_311) + ); + OAI22_X1_LVT i_0_328( + .A1(op2[1]), .A2(n_0_311), .B1(n_0_728), .B2(n_0_348), .ZN(n_0_310) + ); + OR2_X1_LVT i_0_327( + .A1(op2[0]), .A2(n_0_310), .ZN(n_0_309) + ); + OAI21_X1_LVT i_0_321( + .A(n_0_576), .B1(n_0_701), .B2(n_0_319), .ZN(n_0_303) + ); + INV_X1_LVT i_0_320( + .A(n_0_303), .ZN(n_0_302) + ); + AOI21_X1_LVT i_0_319( + .A(n_0_304), .B1(n_0_309), .B2(n_0_302), .ZN(n_0_301) + ); + INV_X1_LVT i_0_345( + .A(n_0_327), .ZN(n_0_326) + ); + OAI22_X1_LVT i_0_326( + .A1(n_0_701), .A2(n_0_326), .B1(n_0_469), .B2(n_0_309), .ZN(n_0_308) + ); + NOR2_X1_LVT i_0_318( + .A1(op2[2]), .A2(n_0_393), .ZN(n_0_300) + ); + AOI21_X1_LVT i_0_317( + .A(n_0_300), .B1(n_0_597), .B2(n_0_498), .ZN(n_0_299) + ); + OAI22_X1_LVT i_0_316( + .A1(n_0_728), .A2(n_0_299), .B1(op2[1]), .B2(n_0_354), .ZN(n_0_298) + ); + OAI22_X1_LVT i_0_315( + .A1(op2[0]), .A2(n_0_334), .B1(n_0_701), .B2(n_0_298), .ZN(n_0_297) + ); + OAI221_X1_LVT i_0_314( + .A(n_0_301), .B1(n_0_545), .B2(n_0_308), .C1(n_0_621), .C2(n_0_297), .ZN(result[17]) + ); + XNOR2_X1_LVT i_10_82( + .A(n_10_64), .B(n_10_65), .ZN(n_48) + ); + AOI22_X1_LVT i_0_301( + .A1(n_48), .A2(n_0_580), .B1(n_16), .B2(n_0_581), .ZN(n_0_284) + ); + NAND2_X1_LVT i_0_333( + .A1(n_0_544), .A2(n_0_469), .ZN(n_0_315) + ); + INV_X1_LVT i_0_332( + .A(n_0_315), .ZN(n_0_314) + ); + OAI21_X1_LVT i_0_302( + .A(n_0_681), .B1(op2[16]), .B2(n_0_568), .ZN(n_0_285) + ); + AOI21_X1_LVT i_0_300( + .A(n_0_314), .B1(op1[16]), .B2(n_0_285), .ZN(n_0_283) + ); + INV_X1_LVT i_0_772( + .A(op1[16]), .ZN(n_0_739) + ); + OAI221_X1_LVT i_0_303( + .A(op2[16]), .B1(op1[16]), .B2(n_0_564), .C1(n_0_739), .C2(n_0_567), .ZN(n_0_286) + ); + NAND3_X1_LVT i_0_299( + .A1(n_0_284), .A2(n_0_283), .A3(n_0_286), .ZN(n_0_282) + ); + INV_X1_LVT i_0_593( + .A(n_0_562), .ZN(n_0_561) + ); + OAI22_X1_LVT i_0_307( + .A1(op1[16]), .A2(op2[3]), .B1(op1[24]), .B2(n_0_723), .ZN(n_0_290) + ); + NOR2_X1_LVT i_0_306( + .A1(op2[4]), .A2(n_0_290), .ZN(n_0_289) + ); + AOI22_X1_LVT i_0_305( + .A1(n_0_693), .A2(n_0_289), .B1(op2[2]), .B2(n_0_371), .ZN(n_0_288) + ); + OAI22_X1_LVT i_0_304( + .A1(n_0_728), .A2(n_0_330), .B1(op2[1]), .B2(n_0_288), .ZN(n_0_287) + ); + AOI221_X1_LVT i_0_298( + .A(n_0_282), .B1(n_0_547), .B2(n_0_310), .C1(n_0_561), .C2(n_0_287), .ZN(n_0_281) + ); + INV_X1_LVT i_0_762( + .A(op1[1]), .ZN(n_0_729) + ); + OAI22_X1_LVT i_0_313( + .A1(n_0_722), .A2(n_0_615), .B1(n_0_729), .B2(n_0_617), .ZN(n_0_296) + ); + NAND2_X1_LVT i_0_312( + .A1(op2[2]), .A2(n_0_296), .ZN(n_0_295) + ); + OAI21_X1_LVT i_0_311( + .A(n_0_295), .B1(op2[2]), .B2(n_0_362), .ZN(n_0_294) + ); + NAND2_X1_LVT i_0_310( + .A1(op2[1]), .A2(n_0_294), .ZN(n_0_293) + ); + OAI21_X1_LVT i_0_309( + .A(n_0_293), .B1(op2[1]), .B2(n_0_336), .ZN(n_0_292) + ); + OAI22_X1_LVT i_0_308( + .A1(op2[0]), .A2(n_0_298), .B1(n_0_701), .B2(n_0_292), .ZN(n_0_291) + ); + OAI21_X1_LVT i_0_297( + .A(n_0_281), .B1(n_0_621), .B2(n_0_291), .ZN(result[16]) + ); + OAI221_X1_LVT i_0_286( + .A(op2[15]), .B1(n_0_734), .B2(n_0_567), .C1(op1[15]), .C2(n_0_564), .ZN(n_0_270) + ); + AOI21_X1_LVT i_0_288( + .A(n_0_314), .B1(n_15), .B2(n_0_581), .ZN(n_0_272) + ); + INV_X1_LVT i_0_287( + .A(n_0_272), .ZN(n_0_271) + ); + XNOR2_X1_LVT i_10_78( + .A(n_10_61), .B(n_10_62), .ZN(n_47) + ); + OAI21_X1_LVT i_0_285( + .A(n_0_681), .B1(op2[15]), .B2(n_0_568), .ZN(n_0_269) + ); + AOI221_X1_LVT i_0_284( + .A(n_0_271), .B1(n_47), .B2(n_0_580), .C1(op1[15]), .C2(n_0_269), .ZN(n_0_268) + ); + AOI22_X1_LVT i_0_296( + .A1(op1[8]), .A2(n_0_616), .B1(op1[0]), .B2(n_0_618), .ZN(n_0_280) + ); + AOI22_X1_LVT i_0_295( + .A1(op2[2]), .A2(n_0_280), .B1(n_0_693), .B2(n_0_356), .ZN(n_0_279) + ); + NAND2_X1_LVT i_0_294( + .A1(op2[1]), .A2(n_0_279), .ZN(n_0_278) + ); + OAI21_X1_LVT i_0_293( + .A(n_0_278), .B1(op2[1]), .B2(n_0_299), .ZN(n_0_277) + ); + OAI221_X1_LVT i_0_292( + .A(n_0_620), .B1(n_0_701), .B2(n_0_277), .C1(op2[0]), .C2(n_0_292), .ZN(n_0_276) + ); + OAI222_X1_LVT i_0_291( + .A1(n_0_719), .A2(n_0_617), .B1(n_0_691), .B2(n_0_605), .C1(n_0_734), .C2(n_0_615), + .ZN(n_0_275) + ); + OAI22_X1_LVT i_0_290( + .A1(n_0_693), .A2(n_0_349), .B1(op2[2]), .B2(n_0_275), .ZN(n_0_274) + ); + OAI22_X1_LVT i_0_289( + .A1(op2[1]), .A2(n_0_274), .B1(n_0_728), .B2(n_0_311), .ZN(n_0_273) + ); + AOI22_X1_LVT i_0_283( + .A1(n_0_561), .A2(n_0_273), .B1(n_0_547), .B2(n_0_287), .ZN(n_0_267) + ); + NAND4_X1_LVT i_0_282( + .A1(n_0_270), .A2(n_0_268), .A3(n_0_276), .A4(n_0_267), .ZN(result[15]) + ); + NOR2_X1_LVT i_0_278( + .A1(op2[0]), .A2(n_0_277), .ZN(n_0_263) + ); + NAND2_X1_LVT i_0_281( + .A1(n_0_612), .A2(n_0_575), .ZN(n_0_266) + ); + OAI21_X1_LVT i_0_280( + .A(n_0_266), .B1(n_0_713), .B2(n_0_497), .ZN(n_0_265) + ); + AOI22_X1_LVT i_0_279( + .A1(op2[1]), .A2(n_0_265), .B1(n_0_728), .B2(n_0_294), .ZN(n_0_264) + ); + AOI211_X1_LVT i_0_277( + .A(n_0_263), .B(n_0_621), .C1(op2[0]), .C2(n_0_264), .ZN(n_0_262) + ); + INV_X1_LVT i_0_754( + .A(op1[14]), .ZN(n_0_721) + ); + OAI21_X1_LVT i_0_273( + .A(op2[14]), .B1(n_0_721), .B2(n_0_567), .ZN(n_0_258) + ); + AOI21_X1_LVT i_0_272( + .A(n_0_258), .B1(n_0_721), .B2(n_0_565), .ZN(n_0_257) + ); + XNOR2_X1_LVT i_10_74( + .A(n_10_58), .B(n_10_59), .ZN(n_46) + ); + OAI21_X1_LVT i_0_276( + .A(n_0_681), .B1(op2[14]), .B2(n_0_568), .ZN(n_0_261) + ); + AOI222_X1_LVT i_0_275( + .A1(n_14), .A2(n_0_581), .B1(n_46), .B2(n_0_580), .C1(op1[14]), .C2(n_0_261), + .ZN(n_0_260) + ); + INV_X1_LVT i_0_274( + .A(n_0_260), .ZN(n_0_259) + ); + OAI222_X1_LVT i_0_271( + .A1(n_0_717), .A2(n_0_605), .B1(n_0_687), .B2(n_0_617), .C1(n_0_721), .C2(n_0_615), + .ZN(n_0_256) + ); + OAI22_X1_LVT i_0_270( + .A1(n_0_693), .A2(n_0_331), .B1(op2[2]), .B2(n_0_256), .ZN(n_0_255) + ); + AND2_X1_LVT i_0_269( + .A1(n_0_728), .A2(n_0_255), .ZN(n_0_254) + ); + NOR3_X1_LVT i_0_265( + .A1(op2[3]), .A2(op2[2]), .A3(op2[0]), .ZN(n_0_250) + ); + AOI21_X1_LVT i_0_268( + .A(n_0_254), .B1(op2[1]), .B2(n_0_288), .ZN(n_0_253) + ); + OAI22_X1_LVT i_0_266( + .A1(op2[0]), .A2(n_0_253), .B1(n_0_701), .B2(n_0_273), .ZN(n_0_251) + ); + AOI221_X1_LVT i_0_259( + .A(n_0_579), .B1(n_0_254), .B2(n_0_250), .C1(n_0_315), .C2(n_0_251), .ZN(n_0_244) + ); + OR4_X1_LVT i_0_258( + .A1(n_0_262), .A2(n_0_257), .A3(n_0_259), .A4(n_0_244), .ZN(result[14]) + ); + OAI221_X1_LVT i_0_245( + .A(op2[13]), .B1(op1[13]), .B2(n_0_564), .C1(n_0_714), .C2(n_0_567), .ZN(n_0_231) + ); + NAND2_X1_LVT i_0_244( + .A1(n_13), .A2(n_0_581), .ZN(n_0_230) + ); + OAI211_X1_LVT i_0_243( + .A(n_0_231), .B(n_0_230), .C1(n_0_714), .C2(n_0_681), .ZN(n_0_229) + ); + XNOR2_X1_LVT i_10_70( + .A(n_10_55), .B(n_10_56), .ZN(n_45) + ); + NOR2_X1_LVT i_0_695( + .A1(op2[13]), .A2(n_0_714), .ZN(n_0_662) + ); + AOI221_X1_LVT i_0_242( + .A(n_0_229), .B1(n_45), .B2(n_0_580), .C1(n_0_662), .C2(n_0_569), .ZN(n_0_228) + ); + INV_X1_LVT i_0_267( + .A(n_0_253), .ZN(n_0_252) + ); + OAI222_X1_LVT i_0_257( + .A1(n_0_714), .A2(n_0_615), .B1(n_0_726), .B2(n_0_617), .C1(n_0_710), .C2(n_0_605), + .ZN(n_0_243) + ); + OAI22_X1_LVT i_0_256( + .A1(n_0_693), .A2(n_0_312), .B1(op2[2]), .B2(n_0_243), .ZN(n_0_242) + ); + NAND2_X1_LVT i_0_255( + .A1(n_0_728), .A2(n_0_242), .ZN(n_0_241) + ); + NAND2_X1_LVT i_0_254( + .A1(op2[1]), .A2(n_0_274), .ZN(n_0_240) + ); + NAND2_X1_LVT i_0_241( + .A1(n_0_241), .A2(n_0_240), .ZN(n_0_227) + ); + OAI221_X1_LVT i_0_240( + .A(n_0_228), .B1(n_0_548), .B2(n_0_252), .C1(n_0_562), .C2(n_0_227), .ZN(n_0_226) + ); + NAND2_X1_LVT i_0_249( + .A1(n_0_728), .A2(n_0_279), .ZN(n_0_235) + ); + AOI22_X1_LVT i_0_250( + .A1(n_0_597), .A2(n_0_575), .B1(op1[6]), .B2(n_0_496), .ZN(n_0_236) + ); + OAI21_X1_LVT i_0_248( + .A(n_0_235), .B1(n_0_728), .B2(n_0_236), .ZN(n_0_234) + ); + INV_X1_LVT i_0_247( + .A(n_0_234), .ZN(n_0_233) + ); + AOI221_X1_LVT i_0_246( + .A(n_0_621), .B1(op2[0]), .B2(n_0_233), .C1(n_0_701), .C2(n_0_264), .ZN(n_0_232) + ); + NAND2_X1_LVT i_0_264( + .A1(op2[3]), .A2(n_0_469), .ZN(n_0_249) + ); + AOI21_X1_LVT i_0_262( + .A(n_0_468), .B1(n_0_693), .B2(n_0_249), .ZN(n_0_247) + ); + INV_X1_LVT i_0_261( + .A(n_0_247), .ZN(n_0_246) + ); + OAI211_X1_LVT i_0_260( + .A(n_0_252), .B(n_0_246), .C1(n_0_468), .C2(n_0_254), .ZN(n_0_245) + ); + OAI221_X1_LVT i_0_253( + .A(n_0_544), .B1(n_0_247), .B2(n_0_241), .C1(n_0_469), .C2(n_0_240), .ZN(n_0_239) + ); + INV_X1_LVT i_0_252( + .A(n_0_239), .ZN(n_0_238) + ); + AOI211_X1_LVT i_0_239( + .A(n_0_226), .B(n_0_232), .C1(n_0_245), .C2(n_0_238), .ZN(n_0_225) + ); + INV_X1_LVT i_0_238( + .A(n_0_225), .ZN(result[13]) + ); + OAI221_X1_LVT i_0_232( + .A(op2[12]), .B1(n_0_696), .B2(n_0_567), .C1(op1[12]), .C2(n_0_564), .ZN(n_0_219) + ); + OAI21_X1_LVT i_0_231( + .A(n_0_681), .B1(op2[12]), .B2(n_0_568), .ZN(n_0_218) + ); + XNOR2_X1_LVT i_10_66( + .A(n_10_52), .B(n_10_53), .ZN(n_44) + ); + AOI222_X1_LVT i_0_230( + .A1(n_12), .A2(n_0_581), .B1(op1[12]), .B2(n_0_218), .C1(n_44), .C2(n_0_580), + .ZN(n_0_217) + ); + OAI21_X1_LVT i_0_234( + .A(n_0_620), .B1(op2[1]), .B2(n_0_265), .ZN(n_0_221) + ); + INV_X1_LVT i_0_763( + .A(op1[5]), .ZN(n_0_730) + ); + OAI21_X1_LVT i_0_236( + .A(op2[2]), .B1(n_0_730), .B2(n_0_615), .ZN(n_0_223) + ); + OAI21_X1_LVT i_0_235( + .A(n_0_223), .B1(op2[2]), .B2(n_0_296), .ZN(n_0_222) + ); + AOI21_X1_LVT i_0_233( + .A(n_0_221), .B1(op2[1]), .B2(n_0_222), .ZN(n_0_220) + ); + NOR2_X1_LVT i_0_237( + .A1(n_0_577), .A2(n_0_227), .ZN(n_0_224) + ); + NOR4_X1_LVT i_0_223( + .A1(n_0_701), .A2(n_0_220), .A3(n_0_224), .A4(n_0_238), .ZN(n_0_210) + ); + NAND2_X1_LVT i_0_224( + .A1(n_0_544), .A2(n_0_247), .ZN(n_0_211) + ); + NAND2_X1_LVT i_0_222( + .A1(n_0_701), .A2(n_0_211), .ZN(n_0_209) + ); + OAI22_X1_LVT i_0_229( + .A1(op2[4]), .A2(n_0_696), .B1(n_0_738), .B2(n_0_698), .ZN(n_0_216) + ); + INV_X1_LVT i_0_228( + .A(n_0_216), .ZN(n_0_215) + ); + OAI22_X1_LVT i_0_227( + .A1(n_0_727), .A2(n_0_617), .B1(op2[3]), .B2(n_0_215), .ZN(n_0_214) + ); + OAI22_X1_LVT i_0_226( + .A1(n_0_693), .A2(n_0_289), .B1(op2[2]), .B2(n_0_214), .ZN(n_0_213) + ); + OAI22_X1_LVT i_0_225( + .A1(op2[1]), .A2(n_0_213), .B1(n_0_728), .B2(n_0_255), .ZN(n_0_212) + ); + AOI221_X1_LVT i_0_221( + .A(n_0_209), .B1(n_0_578), .B2(n_0_212), .C1(n_0_620), .C2(n_0_234), .ZN(n_0_208) + ); + OAI211_X1_LVT i_0_220( + .A(n_0_219), .B(n_0_217), .C1(n_0_210), .C2(n_0_208), .ZN(result[12]) + ); + OAI21_X1_LVT i_0_209( + .A(n_0_681), .B1(op2[11]), .B2(n_0_568), .ZN(n_0_197) + ); + AOI22_X1_LVT i_0_208( + .A1(n_11), .A2(n_0_581), .B1(op1[11]), .B2(n_0_197), .ZN(n_0_196) + ); + NAND2_X1_LVT i_0_207( + .A1(n_0_211), .A2(n_0_196), .ZN(n_0_195) + ); + AOI22_X1_LVT i_0_210( + .A1(op1[11]), .A2(n_0_566), .B1(n_0_706), .B2(n_0_565), .ZN(n_0_198) + ); + XNOR2_X1_LVT i_10_62( + .A(n_10_49), .B(n_10_50), .ZN(n_43) + ); + AOI221_X1_LVT i_0_206( + .A(n_0_195), .B1(op2[11]), .B2(n_0_198), .C1(n_43), .C2(n_0_580), .ZN(n_0_194) + ); + AOI221_X1_LVT i_0_215( + .A(op2[3]), .B1(n_0_738), .B2(n_0_706), .C1(op2[4]), .C2(n_0_688), .ZN(n_0_203) + ); + AOI21_X1_LVT i_0_214( + .A(n_0_203), .B1(op1[19]), .B2(n_0_618), .ZN(n_0_202) + ); + NAND2_X1_LVT i_0_213( + .A1(n_0_693), .A2(n_0_202), .ZN(n_0_201) + ); + OAI21_X1_LVT i_0_212( + .A(n_0_201), .B1(n_0_693), .B2(n_0_275), .ZN(n_0_200) + ); + OAI22_X1_LVT i_0_211( + .A1(n_0_728), .A2(n_0_242), .B1(op2[1]), .B2(n_0_200), .ZN(n_0_199) + ); + AOI22_X1_LVT i_0_205( + .A1(n_0_561), .A2(n_0_199), .B1(n_0_701), .B2(n_0_220), .ZN(n_0_193) + ); + NOR2_X1_LVT i_0_219( + .A1(op2[2]), .A2(n_0_280), .ZN(n_0_207) + ); + AOI21_X1_LVT i_0_218( + .A(n_0_207), .B1(op1[4]), .B2(n_0_496), .ZN(n_0_206) + ); + AOI22_X1_LVT i_0_217( + .A1(n_0_728), .A2(n_0_236), .B1(op2[1]), .B2(n_0_206), .ZN(n_0_205) + ); + AOI22_X1_LVT i_0_216( + .A1(n_0_578), .A2(n_0_212), .B1(n_0_620), .B2(n_0_205), .ZN(n_0_204) + ); + OAI211_X1_LVT i_0_204( + .A(n_0_194), .B(n_0_193), .C1(n_0_701), .C2(n_0_204), .ZN(result[11]) + ); + AOI22_X1_LVT i_0_194( + .A1(n_0_654), .A2(n_0_498), .B1(op1[7]), .B2(n_0_573), .ZN(n_0_183) + ); + OAI22_X1_LVT i_0_193( + .A1(n_0_728), .A2(n_0_183), .B1(op2[1]), .B2(n_0_222), .ZN(n_0_182) + ); + AOI22_X1_LVT i_0_192( + .A1(op2[0]), .A2(n_0_182), .B1(n_0_701), .B2(n_0_205), .ZN(n_0_181) + ); + NOR2_X1_LVT i_0_191( + .A1(n_0_621), .A2(n_0_181), .ZN(n_0_180) + ); + AOI22_X1_LVT i_0_190( + .A1(op1[10]), .A2(n_0_566), .B1(n_0_733), .B2(n_0_565), .ZN(n_0_179) + ); + XNOR2_X1_LVT i_10_58( + .A(n_10_46), .B(n_10_47), .ZN(n_42) + ); + AOI22_X1_LVT i_0_188( + .A1(op2[10]), .A2(n_0_179), .B1(n_42), .B2(n_0_580), .ZN(n_0_177) + ); + OAI21_X1_LVT i_0_189( + .A(n_0_681), .B1(op2[10]), .B2(n_0_568), .ZN(n_0_178) + ); + AOI22_X1_LVT i_0_187( + .A1(n_10), .A2(n_0_581), .B1(op1[10]), .B2(n_0_178), .ZN(n_0_176) + ); + NAND2_X1_LVT i_0_186( + .A1(n_0_177), .A2(n_0_176), .ZN(n_0_175) + ); + NOR2_X1_LVT i_0_203( + .A1(n_0_701), .A2(n_0_199), .ZN(n_0_192) + ); + NOR2_X1_LVT i_0_200( + .A1(n_0_693), .A2(n_0_256), .ZN(n_0_189) + ); + AOI221_X1_LVT i_0_202( + .A(n_0_596), .B1(op1[10]), .B2(n_0_616), .C1(op1[26]), .C2(n_0_606), .ZN(n_0_191) + ); + AOI21_X1_LVT i_0_199( + .A(n_0_189), .B1(n_0_693), .B2(n_0_191), .ZN(n_0_188) + ); + OR2_X1_LVT i_0_198( + .A1(op2[1]), .A2(n_0_188), .ZN(n_0_187) + ); + NAND2_X1_LVT i_0_197( + .A1(op2[1]), .A2(n_0_213), .ZN(n_0_186) + ); + NAND2_X1_LVT i_0_185( + .A1(n_0_187), .A2(n_0_186), .ZN(n_0_174) + ); + AOI211_X1_LVT i_0_184( + .A(n_0_577), .B(n_0_192), .C1(n_0_701), .C2(n_0_174), .ZN(n_0_173) + ); + INV_X1_LVT i_0_263( + .A(n_0_249), .ZN(n_0_248) + ); + OAI22_X1_LVT i_0_196( + .A1(n_0_248), .A2(n_0_187), .B1(n_0_247), .B2(n_0_186), .ZN(n_0_185) + ); + AOI221_X1_LVT i_0_195( + .A(n_0_545), .B1(n_0_246), .B2(n_0_192), .C1(n_0_701), .C2(n_0_185), .ZN(n_0_184) + ); + OR4_X1_LVT i_0_183( + .A1(n_0_180), .A2(n_0_175), .A3(n_0_173), .A4(n_0_184), .ZN(result[10]) + ); + INV_X1_LVT i_0_753( + .A(op2[9]), .ZN(n_0_720) + ); + AOI221_X1_LVT i_0_171( + .A(n_0_720), .B1(op1[9]), .B2(n_0_566), .C1(n_0_722), .C2(n_0_565), .ZN(n_0_161) + ); + XNOR2_X1_LVT i_10_54( + .A(n_10_43), .B(n_10_44), .ZN(n_41) + ); + AOI22_X1_LVT i_0_172( + .A1(n_9), .A2(n_0_581), .B1(n_41), .B2(n_0_580), .ZN(n_0_162) + ); + AOI21_X1_LVT i_0_170( + .A(aluBypass), .B1(n_0_720), .B2(n_0_569), .ZN(n_0_160) + ); + OAI21_X1_LVT i_0_169( + .A(n_0_162), .B1(n_0_722), .B2(n_0_160), .ZN(n_0_159) + ); + OAI222_X1_LVT i_0_182( + .A1(n_0_722), .A2(n_0_615), .B1(n_0_699), .B2(n_0_605), .C1(n_0_732), .C2(n_0_617), + .ZN(n_0_172) + ); + AOI22_X1_LVT i_0_181( + .A1(n_0_693), .A2(n_0_172), .B1(op2[2]), .B2(n_0_243), .ZN(n_0_171) + ); + NAND2_X1_LVT i_0_180( + .A1(n_0_728), .A2(n_0_171), .ZN(n_0_170) + ); + NAND2_X1_LVT i_0_179( + .A1(op2[1]), .A2(n_0_200), .ZN(n_0_169) + ); + OAI22_X1_LVT i_0_178( + .A1(n_0_248), .A2(n_0_170), .B1(n_0_247), .B2(n_0_169), .ZN(n_0_168) + ); + NOR3_X1_LVT i_0_177( + .A1(n_0_545), .A2(n_0_168), .A3(n_0_185), .ZN(n_0_167) + ); + NOR2_X1_LVT i_0_251( + .A1(n_0_704), .A2(n_0_615), .ZN(n_0_237) + ); + OAI22_X1_LVT i_0_176( + .A1(op1[2]), .A2(n_0_693), .B1(n_0_496), .B2(n_0_237), .ZN(n_0_166) + ); + OAI22_X1_LVT i_0_175( + .A1(op2[1]), .A2(n_0_206), .B1(n_0_728), .B2(n_0_166), .ZN(n_0_165) + ); + OAI221_X1_LVT i_0_174( + .A(n_0_620), .B1(op2[0]), .B2(n_0_182), .C1(n_0_701), .C2(n_0_165), .ZN(n_0_164) + ); + NAND2_X1_LVT i_0_173( + .A1(n_0_170), .A2(n_0_169), .ZN(n_0_163) + ); + OAI221_X1_LVT i_0_168( + .A(n_0_164), .B1(n_0_562), .B2(n_0_163), .C1(n_0_548), .C2(n_0_174), .ZN(n_0_158) + ); + OR4_X1_LVT i_0_167( + .A1(n_0_161), .A2(n_0_159), .A3(n_0_167), .A4(n_0_158), .ZN(result[9]) + ); + OAI21_X1_LVT i_0_160( + .A(n_0_693), .B1(n_0_730), .B2(n_0_615), .ZN(n_0_151) + ); + OAI21_X1_LVT i_0_159( + .A(op2[2]), .B1(n_0_729), .B2(n_0_615), .ZN(n_0_150) + ); + AND2_X1_LVT i_0_158( + .A1(n_0_151), .A2(n_0_150), .ZN(n_0_149) + ); + NAND2_X1_LVT i_0_157( + .A1(op2[1]), .A2(n_0_149), .ZN(n_0_148) + ); + OAI21_X1_LVT i_0_156( + .A(n_0_148), .B1(op2[1]), .B2(n_0_183), .ZN(n_0_147) + ); + OAI22_X1_LVT i_0_155( + .A1(op2[0]), .A2(n_0_165), .B1(n_0_701), .B2(n_0_147), .ZN(n_0_146) + ); + NOR2_X1_LVT i_0_154( + .A1(n_0_621), .A2(n_0_146), .ZN(n_0_145) + ); + INV_X1_LVT i_0_773( + .A(op1[8]), .ZN(n_0_740) + ); + NOR2_X1_LVT i_0_688( + .A1(n_0_740), .A2(op2[8]), .ZN(n_0_655) + ); + AOI22_X1_LVT i_0_153( + .A1(op1[8]), .A2(aluBypass), .B1(n_0_655), .B2(n_0_569), .ZN(n_0_144) + ); + OAI221_X1_LVT i_0_152( + .A(op2[8]), .B1(op1[8]), .B2(n_0_564), .C1(n_0_740), .C2(n_0_567), .ZN(n_0_143) + ); + XNOR2_X1_LVT i_10_51( + .A(n_10_39), .B(n_10_42), .ZN(n_40) + ); + AOI22_X1_LVT i_0_151( + .A1(n_40), .A2(n_0_580), .B1(n_8), .B2(n_0_581), .ZN(n_0_142) + ); + NAND3_X1_LVT i_0_150( + .A1(n_0_144), .A2(n_0_143), .A3(n_0_142), .ZN(n_0_141) + ); + OAI222_X1_LVT i_0_166( + .A1(n_0_740), .A2(n_0_615), .B1(n_0_739), .B2(n_0_617), .C1(n_0_736), .C2(n_0_605), + .ZN(n_0_157) + ); + OAI22_X1_LVT i_0_165( + .A1(op2[2]), .A2(n_0_157), .B1(n_0_693), .B2(n_0_214), .ZN(n_0_156) + ); + NOR2_X1_LVT i_0_164( + .A1(op2[1]), .A2(n_0_156), .ZN(n_0_155) + ); + AOI21_X1_LVT i_0_163( + .A(n_0_155), .B1(op2[1]), .B2(n_0_188), .ZN(n_0_154) + ); + AND2_X1_LVT i_0_162( + .A1(n_0_701), .A2(n_0_154), .ZN(n_0_153) + ); + AOI211_X1_LVT i_0_149( + .A(n_0_577), .B(n_0_153), .C1(op2[0]), .C2(n_0_163), .ZN(n_0_140) + ); + AOI221_X1_LVT i_0_161( + .A(n_0_545), .B1(op2[0]), .B2(n_0_168), .C1(n_0_249), .C2(n_0_153), .ZN(n_0_152) + ); + OR4_X1_LVT i_0_148( + .A1(n_0_145), .A2(n_0_141), .A3(n_0_140), .A4(n_0_152), .ZN(result[8]) + ); + AOI22_X1_LVT i_0_138( + .A1(op1[4]), .A2(n_0_573), .B1(op1[0]), .B2(n_0_496), .ZN(n_0_130) + ); + AOI22_X1_LVT i_0_137( + .A1(op2[1]), .A2(n_0_130), .B1(n_0_728), .B2(n_0_166), .ZN(n_0_129) + ); + OAI22_X1_LVT i_0_136( + .A1(n_0_701), .A2(n_0_129), .B1(op2[0]), .B2(n_0_147), .ZN(n_0_128) + ); + NOR2_X1_LVT i_0_135( + .A1(n_0_621), .A2(n_0_128), .ZN(n_0_127) + ); + OAI221_X1_LVT i_0_139( + .A(op2[7]), .B1(n_0_713), .B2(n_0_567), .C1(op1[7]), .C2(n_0_564), .ZN(n_0_131) + ); + INV_X1_LVT i_10_44( + .A(n_10_36), .ZN(n_10_37) + ); + NOR2_X1_LVT i_10_45( + .A1(n_10_35), .A2(n_10_37), .ZN(n_10_38) + ); + XNOR2_X1_LVT i_10_46( + .A(n_10_33), .B(n_10_38), .ZN(n_39) + ); + AOI22_X1_LVT i_0_141( + .A1(n_7), .A2(n_0_581), .B1(n_39), .B2(n_0_580), .ZN(n_0_133) + ); + INV_X1_LVT i_0_745( + .A(op2[7]), .ZN(n_0_712) + ); + AOI21_X1_LVT i_0_140( + .A(aluBypass), .B1(n_0_712), .B2(n_0_569), .ZN(n_0_132) + ); + OAI211_X1_LVT i_0_133( + .A(n_0_131), .B(n_0_133), .C1(n_0_713), .C2(n_0_132), .ZN(n_0_125) + ); + OAI22_X1_LVT i_0_147( + .A1(n_0_734), .A2(n_0_617), .B1(n_0_713), .B2(n_0_615), .ZN(n_0_139) + ); + AOI211_X1_LVT i_0_146( + .A(n_0_139), .B(n_0_248), .C1(op1[23]), .C2(n_0_606), .ZN(n_0_138) + ); + OAI22_X1_LVT i_0_145( + .A1(n_0_693), .A2(n_0_202), .B1(op2[2]), .B2(n_0_138), .ZN(n_0_137) + ); + NOR2_X1_LVT i_0_144( + .A1(op2[1]), .A2(n_0_137), .ZN(n_0_136) + ); + AOI21_X1_LVT i_0_143( + .A(n_0_136), .B1(op2[1]), .B2(n_0_171), .ZN(n_0_135) + ); + NAND2_X1_LVT i_0_142( + .A1(n_0_561), .A2(n_0_135), .ZN(n_0_134) + ); + OAI221_X1_LVT i_0_134( + .A(n_0_134), .B1(n_0_548), .B2(n_0_154), .C1(n_0_545), .C2(n_0_249), .ZN(n_0_126) + ); + OR3_X1_LVT i_0_132( + .A1(n_0_127), .A2(n_0_125), .A3(n_0_126), .ZN(result[7]) + ); + NAND2_X1_LVT i_0_124( + .A1(n_0_728), .A2(n_0_149), .ZN(n_0_117) + ); + OAI21_X1_LVT i_0_123( + .A(n_0_117), .B1(n_0_724), .B2(n_0_531), .ZN(n_0_116) + ); + OAI22_X1_LVT i_0_122( + .A1(n_0_701), .A2(n_0_116), .B1(op2[0]), .B2(n_0_129), .ZN(n_0_115) + ); + NOR2_X1_LVT i_0_121( + .A1(n_0_621), .A2(n_0_115), .ZN(n_0_114) + ); + XNOR2_X1_LVT i_10_38( + .A(n_10_30), .B(n_10_31), .ZN(n_38) + ); + AOI22_X1_LVT i_0_119( + .A1(n_6), .A2(n_0_581), .B1(n_38), .B2(n_0_580), .ZN(n_0_112) + ); + INV_X1_LVT i_0_735( + .A(op2[6]), .ZN(n_0_702) + ); + AOI21_X1_LVT i_0_120( + .A(aluBypass), .B1(n_0_702), .B2(n_0_569), .ZN(n_0_113) + ); + OAI21_X1_LVT i_0_118( + .A(n_0_112), .B1(n_0_704), .B2(n_0_113), .ZN(n_0_111) + ); + AOI221_X1_LVT i_0_117( + .A(n_0_702), .B1(n_0_704), .B2(n_0_565), .C1(op1[6]), .C2(n_0_566), .ZN(n_0_110) + ); + NOR3_X1_LVT i_0_116( + .A1(n_0_114), .A2(n_0_111), .A3(n_0_110), .ZN(n_0_109) + ); + AOI221_X1_LVT i_0_131( + .A(n_0_237), .B1(op1[14]), .B2(n_0_618), .C1(op2[4]), .C2(n_0_406), .ZN(n_0_124) + ); + NAND2_X1_LVT i_0_130( + .A1(n_0_693), .A2(n_0_124), .ZN(n_0_123) + ); + INV_X1_LVT i_0_201( + .A(n_0_191), .ZN(n_0_190) + ); + OAI21_X1_LVT i_0_129( + .A(n_0_123), .B1(n_0_693), .B2(n_0_190), .ZN(n_0_122) + ); + AOI22_X1_LVT i_0_128( + .A1(n_0_728), .A2(n_0_122), .B1(op2[1]), .B2(n_0_156), .ZN(n_0_121) + ); + INV_X1_LVT i_0_127( + .A(n_0_121), .ZN(n_0_120) + ); + OAI21_X1_LVT i_0_126( + .A(n_0_248), .B1(op2[1]), .B2(n_0_123), .ZN(n_0_119) + ); + AND2_X1_LVT i_0_125( + .A1(n_0_120), .A2(n_0_119), .ZN(n_0_118) + ); + NOR2_X1_LVT i_0_115( + .A1(n_0_545), .A2(n_0_118), .ZN(n_0_108) + ); + AOI21_X1_LVT i_0_114( + .A(n_0_108), .B1(n_0_576), .B2(n_0_121), .ZN(n_0_107) + ); + AOI22_X1_LVT i_0_113( + .A1(n_0_544), .A2(n_0_248), .B1(n_0_578), .B2(n_0_135), .ZN(n_0_106) + ); + OAI221_X1_LVT i_0_112( + .A(n_0_109), .B1(op2[0]), .B2(n_0_107), .C1(n_0_701), .C2(n_0_106), .ZN(result[6]) + ); + OAI221_X1_LVT i_0_100( + .A(op2[5]), .B1(op1[5]), .B2(n_0_564), .C1(n_0_730), .C2(n_0_567), .ZN(n_0_94) + ); + INV_X1_LVT i_0_764( + .A(op2[5]), .ZN(n_0_731) + ); + AOI21_X1_LVT i_0_99( + .A(aluBypass), .B1(n_0_731), .B2(n_0_569), .ZN(n_0_93) + ); + NOR2_X1_LVT i_0_98( + .A1(n_0_730), .A2(n_0_93), .ZN(n_0_92) + ); + XNOR2_X1_LVT i_10_35( + .A(n_10_26), .B(n_10_29), .ZN(n_37) + ); + AOI221_X1_LVT i_0_97( + .A(n_0_92), .B1(n_37), .B2(n_0_580), .C1(n_5), .C2(n_0_581), .ZN(n_0_91) + ); + OAI22_X1_LVT i_0_102( + .A1(n_0_694), .A2(n_0_531), .B1(op2[1]), .B2(n_0_130), .ZN(n_0_96) + ); + OAI221_X1_LVT i_0_101( + .A(n_0_620), .B1(n_0_701), .B2(n_0_96), .C1(op2[0]), .C2(n_0_116), .ZN(n_0_95) + ); + NAND3_X1_LVT i_0_111( + .A1(n_0_544), .A2(n_0_248), .A3(op2[2]), .ZN(n_0_105) + ); + NAND2_X1_LVT i_0_110( + .A1(op2[4]), .A2(n_0_386), .ZN(n_0_104) + ); + OAI21_X1_LVT i_0_109( + .A(n_0_104), .B1(n_0_714), .B2(n_0_617), .ZN(n_0_103) + ); + OAI22_X1_LVT i_0_108( + .A1(n_0_151), .A2(n_0_103), .B1(n_0_693), .B2(n_0_172), .ZN(n_0_102) + ); + NOR2_X1_LVT i_0_107( + .A1(op2[1]), .A2(n_0_102), .ZN(n_0_101) + ); + AOI21_X1_LVT i_0_106( + .A(n_0_101), .B1(op2[1]), .B2(n_0_137), .ZN(n_0_100) + ); + OAI21_X1_LVT i_0_105( + .A(n_0_105), .B1(n_0_579), .B2(n_0_100), .ZN(n_0_99) + ); + AOI21_X1_LVT i_0_104( + .A(n_0_118), .B1(n_0_682), .B2(n_0_120), .ZN(n_0_98) + ); + OAI22_X1_LVT i_0_103( + .A1(n_0_547), .A2(n_0_99), .B1(n_0_701), .B2(n_0_98), .ZN(n_0_97) + ); + NAND4_X1_LVT i_0_96( + .A1(n_0_94), .A2(n_0_91), .A3(n_0_95), .A4(n_0_97), .ZN(result[5]) + ); + INV_X1_LVT i_10_26( + .A(n_10_21), .ZN(n_10_22) + ); + NOR2_X1_LVT i_10_28( + .A1(n_10_22), .A2(n_10_23), .ZN(n_10_24) + ); + XNOR2_X1_LVT i_10_29( + .A(n_10_19), .B(n_10_24), .ZN(n_36) + ); + AOI222_X1_LVT i_0_89( + .A1(n_4), .A2(n_0_581), .B1(n_36), .B2(n_0_580), .C1(n_0_668), .C2(n_0_564), + .ZN(n_0_84) + ); + INV_X1_LVT i_0_770( + .A(op1[4]), .ZN(n_0_737) + ); + AOI221_X1_LVT i_0_90( + .A(aluBypass), .B1(op2[4]), .B2(n_0_567), .C1(n_0_738), .C2(n_0_569), .ZN(n_0_85) + ); + OAI21_X1_LVT i_0_88( + .A(n_0_84), .B1(n_0_737), .B2(n_0_85), .ZN(n_0_83) + ); + NOR2_X1_LVT i_0_689( + .A1(op2[4]), .A2(n_0_737), .ZN(n_0_656) + ); + AOI21_X1_LVT i_0_95( + .A(n_0_616), .B1(n_0_727), .B2(n_0_723), .ZN(n_0_90) + ); + OAI22_X1_LVT i_0_94( + .A1(n_0_723), .A2(n_0_216), .B1(n_0_656), .B2(n_0_90), .ZN(n_0_89) + ); + INV_X1_LVT i_0_93( + .A(n_0_89), .ZN(n_0_88) + ); + OAI22_X1_LVT i_0_92( + .A1(op2[2]), .A2(n_0_88), .B1(n_0_693), .B2(n_0_157), .ZN(n_0_87) + ); + OAI221_X1_LVT i_0_91( + .A(n_0_105), .B1(n_0_728), .B2(n_0_122), .C1(op2[1]), .C2(n_0_87), .ZN(n_0_86) + ); + AOI221_X1_LVT i_0_85( + .A(n_0_83), .B1(n_0_561), .B2(n_0_86), .C1(op2[0]), .C2(n_0_99), .ZN(n_0_80) + ); + AOI221_X1_LVT i_0_87( + .A(n_0_574), .B1(n_0_729), .B2(op2[1]), .C1(n_0_728), .C2(n_0_724), .ZN(n_0_82) + ); + OAI22_X1_LVT i_0_86( + .A1(op2[0]), .A2(n_0_96), .B1(n_0_701), .B2(n_0_82), .ZN(n_0_81) + ); + OAI21_X1_LVT i_0_84( + .A(n_0_80), .B1(n_0_621), .B2(n_0_81), .ZN(result[4]) + ); + AND2_X1_LVT i_0_81( + .A1(op2[1]), .A2(n_0_105), .ZN(n_0_77) + ); + NAND2_X1_LVT i_0_80( + .A1(n_0_102), .A2(n_0_77), .ZN(n_0_76) + ); + OAI221_X1_LVT i_0_83( + .A(n_0_693), .B1(n_0_654), .B2(n_0_484), .C1(n_0_738), .C2(n_0_350), .ZN(n_0_79) + ); + OAI21_X1_LVT i_0_82( + .A(n_0_79), .B1(n_0_693), .B2(n_0_138), .ZN(n_0_78) + ); + OAI21_X1_LVT i_0_79( + .A(n_0_76), .B1(op2[1]), .B2(n_0_78), .ZN(n_0_75) + ); + NOR2_X1_LVT i_0_78( + .A1(n_0_562), .A2(n_0_75), .ZN(n_0_74) + ); + NAND2_X1_LVT i_10_20( + .A1(n_10_15), .A2(n_10_16), .ZN(n_10_17) + ); + XNOR2_X1_LVT i_10_21( + .A(n_10_13), .B(n_10_17), .ZN(n_35) + ); + AOI22_X1_LVT i_0_75( + .A1(n_35), .A2(n_0_580), .B1(n_3), .B2(n_0_581), .ZN(n_0_71) + ); + OAI21_X1_LVT i_0_74( + .A(n_0_681), .B1(n_0_723), .B2(n_0_566), .ZN(n_0_70) + ); + AOI222_X1_LVT i_0_73( + .A1(n_0_654), .A2(n_0_569), .B1(n_0_663), .B2(n_0_564), .C1(op1[3]), .C2(n_0_70), + .ZN(n_0_69) + ); + INV_X1_LVT i_0_736( + .A(op1[0]), .ZN(n_0_703) + ); + OAI22_X1_LVT i_0_77( + .A1(n_0_703), .A2(n_0_531), .B1(n_0_694), .B2(n_0_572), .ZN(n_0_73) + ); + OAI22_X1_LVT i_0_76( + .A1(n_0_701), .A2(n_0_73), .B1(op2[0]), .B2(n_0_82), .ZN(n_0_72) + ); + OAI211_X1_LVT i_0_72( + .A(n_0_71), .B(n_0_69), .C1(n_0_621), .C2(n_0_72), .ZN(n_0_68) + ); + AOI211_X1_LVT i_0_71( + .A(n_0_74), .B(n_0_68), .C1(n_0_547), .C2(n_0_86), .ZN(n_0_67) + ); + INV_X1_LVT i_0_70( + .A(n_0_67), .ZN(result[3]) + ); + NAND2_X1_LVT i_0_65( + .A1(n_2), .A2(n_0_581), .ZN(n_0_62) + ); + OAI221_X1_LVT i_0_66( + .A(op2[2]), .B1(op1[2]), .B2(n_0_564), .C1(n_0_694), .C2(n_0_567), .ZN(n_0_63) + ); + AOI21_X1_LVT i_0_64( + .A(aluBypass), .B1(n_0_693), .B2(n_0_569), .ZN(n_0_61) + ); + OAI21_X1_LVT i_0_63( + .A(n_0_63), .B1(n_0_694), .B2(n_0_61), .ZN(n_0_60) + ); + INV_X1_LVT i_10_13( + .A(n_10_10), .ZN(n_10_11) + ); + NOR2_X1_LVT i_10_14( + .A1(n_10_9), .A2(n_10_11), .ZN(n_10_12) + ); + XNOR2_X1_LVT i_10_15( + .A(n_10_7), .B(n_10_12), .ZN(n_34) + ); + AOI21_X1_LVT i_0_62( + .A(n_0_60), .B1(n_34), .B2(n_0_580), .ZN(n_0_59) + ); + OAI211_X1_LVT i_0_57( + .A(n_0_62), .B(n_0_59), .C1(n_0_548), .C2(n_0_75), .ZN(n_0_54) + ); + NOR2_X1_LVT i_0_698( + .A1(n_0_729), .A2(op2[1]), .ZN(n_0_665) + ); + INV_X1_LVT i_0_697( + .A(n_0_665), .ZN(n_0_664) + ); + OAI21_X1_LVT i_0_69( + .A(op2[0]), .B1(n_0_664), .B2(n_0_574), .ZN(n_0_66) + ); + OAI21_X1_LVT i_0_68( + .A(n_0_620), .B1(op2[0]), .B2(n_0_73), .ZN(n_0_65) + ); + INV_X1_LVT i_0_67( + .A(n_0_65), .ZN(n_0_64) + ); + OAI222_X1_LVT i_0_61( + .A1(op1[10]), .A2(n_0_617), .B1(op1[2]), .B2(n_0_615), .C1(n_0_738), .C2(n_0_332), + .ZN(n_0_58) + ); + OAI22_X1_LVT i_0_60( + .A1(op2[2]), .A2(n_0_58), .B1(n_0_693), .B2(n_0_124), .ZN(n_0_57) + ); + INV_X1_LVT i_0_59( + .A(n_0_57), .ZN(n_0_56) + ); + AOI22_X1_LVT i_0_58( + .A1(n_0_728), .A2(n_0_56), .B1(n_0_87), .B2(n_0_77), .ZN(n_0_55) + ); + AOI221_X1_LVT i_0_56( + .A(n_0_54), .B1(n_0_66), .B2(n_0_64), .C1(n_0_561), .C2(n_0_55), .ZN(n_0_53) + ); + INV_X1_LVT i_0_55( + .A(n_0_53), .ZN(result[2]) + ); + NAND2_X1_LVT i_0_54( + .A1(n_0_547), .A2(n_0_55), .ZN(n_0_52) + ); + AOI221_X1_LVT i_0_47( + .A(n_0_728), .B1(n_0_729), .B2(n_0_565), .C1(op1[1]), .C2(n_0_566), .ZN(n_0_45) + ); + NOR2_X1_LVT i_0_700( + .A1(op1[0]), .A2(n_0_701), .ZN(n_0_667) + ); + AOI211_X1_LVT i_0_48( + .A(n_0_667), .B(n_0_621), .C1(n_0_729), .C2(n_0_701), .ZN(n_0_46) + ); + AOI221_X1_LVT i_0_44( + .A(n_0_45), .B1(op1[1]), .B2(aluBypass), .C1(n_0_571), .C2(n_0_46), .ZN(n_0_42) + ); + NAND2_X1_LVT i_10_6( + .A1(n_10_3), .A2(n_10_4), .ZN(n_10_5) + ); + XNOR2_X1_LVT i_10_7( + .A(n_10_5), .B(n_10_1), .ZN(n_33) + ); + AOI22_X1_LVT i_0_49( + .A1(n_33), .A2(n_0_580), .B1(n_1), .B2(n_0_581), .ZN(n_0_47) + ); + OAI21_X1_LVT i_0_46( + .A(n_0_47), .B1(n_0_664), .B2(n_0_568), .ZN(n_0_44) + ); + NAND2_X1_LVT i_0_51( + .A1(op2[1]), .A2(n_0_78), .ZN(n_0_49) + ); + OAI222_X1_LVT i_0_53( + .A1(n_0_722), .A2(n_0_617), .B1(n_0_729), .B2(n_0_615), .C1(n_0_738), .C2(n_0_313), + .ZN(n_0_51) + ); + OAI22_X1_LVT i_0_52( + .A1(n_0_223), .A2(n_0_103), .B1(op2[2]), .B2(n_0_51), .ZN(n_0_50) + ); + OAI21_X1_LVT i_0_50( + .A(n_0_49), .B1(op2[1]), .B2(n_0_50), .ZN(n_0_48) + ); + AOI21_X1_LVT i_0_45( + .A(n_0_44), .B1(n_0_561), .B2(n_0_48), .ZN(n_0_43) + ); + NAND3_X1_LVT i_0_43( + .A1(n_0_52), .A2(n_0_42), .A3(n_0_43), .ZN(result[1]) + ); + OAI222_X1_LVT i_0_11( + .A1(n_0_740), .A2(n_0_617), .B1(n_0_703), .B2(n_0_615), .C1(n_0_738), .C2(n_0_290), + .ZN(n_0_10) + ); + OAI22_X1_LVT i_0_10( + .A1(op2[2]), .A2(n_0_10), .B1(n_0_693), .B2(n_0_88), .ZN(n_0_9) + ); + OAI221_X1_LVT i_0_9( + .A(n_0_701), .B1(n_0_728), .B2(n_0_56), .C1(op2[1]), .C2(n_0_9), .ZN(n_0_8) + ); + OAI21_X1_LVT i_0_8( + .A(n_0_8), .B1(n_0_701), .B2(n_0_48), .ZN(n_0_7) + ); + NOR2_X1_LVT i_0_7( + .A1(n_0_579), .A2(n_0_7), .ZN(n_0_6) + ); + OAI221_X1_LVT i_0_3( + .A(op2[0]), .B1(op1[0]), .B2(n_0_564), .C1(n_0_703), .C2(n_0_567), .ZN(n_0_2) + ); + OAI21_X1_LVT i_10_2( + .A(n_10_1), .B1(n_10_0), .B2(op2[0]), .ZN(n_32) + ); + AOI22_X1_LVT i_0_2( + .A1(n_32), .A2(n_0_580), .B1(n_0), .B2(n_0_581), .ZN(n_0_1) + ); + NAND3_X1_LVT i_0_6( + .A1(n_0_701), .A2(n_0_571), .A3(n_0_620), .ZN(n_0_5) + ); + OAI211_X1_LVT i_0_5( + .A(n_0_681), .B(n_0_5), .C1(op2[0]), .C2(n_0_568), .ZN(n_0_4) + ); + NAND2_X1_LVT i_0_4( + .A1(op1[0]), .A2(n_0_4), .ZN(n_0_3) + ); + NAND3_X1_LVT i_0_1( + .A1(n_0_2), .A2(n_0_1), .A3(n_0_3), .ZN(n_0_0) + ); + OAI33_X1_LVT i_0_14( + .A1(n_0_692), .A2(op1[31]), .A3(n_0_683), .B1(op2[31]), .B2(n_0_691), .B3(aluOp[0]), + .ZN(n_0_13) + ); + INV_X1_LVT i_0_741( + .A(op2[29]), .ZN(n_0_708) + ); + NAND2_X1_LVT i_0_685( + .A1(op1[29]), .A2(n_0_708), .ZN(n_0_652) + ); + OAI22_X1_LVT i_0_713( + .A1(n_0_700), .A2(op1[28]), .B1(op1[29]), .B2(n_0_708), .ZN(n_0_680) + ); + NAND2_X1_LVT i_0_694( + .A1(n_0_688), .A2(op2[27]), .ZN(n_0_661) + ); + INV_X1_LVT i_0_742( + .A(op2[26]), .ZN(n_0_709) + ); + OAI22_X1_LVT i_0_712( + .A1(n_0_699), .A2(op2[25]), .B1(n_0_736), .B2(op2[24]), .ZN(n_0_679) + ); + NAND2_X1_LVT i_0_690( + .A1(n_0_727), .A2(op2[20]), .ZN(n_0_657) + ); + INV_X1_LVT i_0_740( + .A(op2[18]), .ZN(n_0_707) + ); + OAI22_X1_LVT i_0_711( + .A1(n_0_707), .A2(op1[18]), .B1(n_0_690), .B2(op1[19]), .ZN(n_0_678) + ); + OAI22_X1_LVT i_0_29( + .A1(n_0_739), .A2(op2[16]), .B1(n_0_734), .B2(op2[15]), .ZN(n_0_28) + ); + INV_X1_LVT i_0_728( + .A(op2[12]), .ZN(n_0_695) + ); + INV_X1_LVT i_0_748( + .A(op2[13]), .ZN(n_0_715) + ); + OAI22_X1_LVT i_0_704( + .A1(n_0_706), .A2(op2[11]), .B1(n_0_696), .B2(op2[12]), .ZN(n_0_671) + ); + AOI22_X1_LVT i_0_710( + .A1(n_0_740), .A2(op2[8]), .B1(n_0_713), .B2(op2[7]), .ZN(n_0_677) + ); + OAI22_X1_LVT i_0_707( + .A1(n_0_731), .A2(op1[5]), .B1(op1[6]), .B2(n_0_702), .ZN(n_0_674) + ); + OAI22_X1_LVT i_0_706( + .A1(op1[2]), .A2(n_0_693), .B1(op1[1]), .B2(n_0_728), .ZN(n_0_673) + ); + INV_X1_LVT i_0_705( + .A(n_0_673), .ZN(n_0_672) + ); + INV_X1_LVT i_0_699( + .A(n_0_667), .ZN(n_0_666) + ); + OAI21_X1_LVT i_0_42( + .A(n_0_672), .B1(n_0_666), .B2(n_0_665), .ZN(n_0_41) + ); + AOI21_X1_LVT i_0_41( + .A(n_0_654), .B1(op1[2]), .B2(n_0_693), .ZN(n_0_40) + ); + AOI211_X1_LVT i_0_40( + .A(n_0_668), .B(n_0_663), .C1(n_0_41), .C2(n_0_40), .ZN(n_0_39) + ); + AOI211_X1_LVT i_0_39( + .A(n_0_656), .B(n_0_39), .C1(n_0_731), .C2(op1[5]), .ZN(n_0_38) + ); + OAI222_X1_LVT i_0_38( + .A1(n_0_704), .A2(op2[6]), .B1(n_0_674), .B2(n_0_38), .C1(n_0_713), .C2(op2[7]), + .ZN(n_0_37) + ); + AOI221_X1_LVT i_0_37( + .A(n_0_655), .B1(op1[9]), .B2(n_0_720), .C1(n_0_677), .C2(n_0_37), .ZN(n_0_36) + ); + INV_X1_LVT i_0_768( + .A(op2[10]), .ZN(n_0_735) + ); + OAI22_X1_LVT i_0_36( + .A1(n_0_735), .A2(op1[10]), .B1(op1[9]), .B2(n_0_720), .ZN(n_0_35) + ); + OAI22_X1_LVT i_0_35( + .A1(op2[10]), .A2(n_0_733), .B1(n_0_36), .B2(n_0_35), .ZN(n_0_34) + ); + INV_X1_LVT i_0_34( + .A(n_0_34), .ZN(n_0_33) + ); + AOI21_X1_LVT i_0_33( + .A(n_0_33), .B1(n_0_706), .B2(op2[11]), .ZN(n_0_32) + ); + OAI222_X1_LVT i_0_32( + .A1(op1[12]), .A2(n_0_695), .B1(n_0_715), .B2(op1[13]), .C1(n_0_671), .C2(n_0_32), + .ZN(n_0_31) + ); + OAI221_X1_LVT i_0_31( + .A(n_0_31), .B1(n_0_721), .B2(op2[14]), .C1(op2[13]), .C2(n_0_714), .ZN(n_0_30) + ); + AOI22_X1_LVT i_0_30( + .A1(n_0_734), .A2(op2[15]), .B1(n_0_721), .B2(op2[14]), .ZN(n_0_29) + ); + AOI21_X1_LVT i_0_28( + .A(n_0_28), .B1(n_0_30), .B2(n_0_29), .ZN(n_0_27) + ); + AOI221_X1_LVT i_0_27( + .A(n_0_27), .B1(n_0_732), .B2(op2[17]), .C1(n_0_739), .C2(op2[16]), .ZN(n_0_26) + ); + AOI211_X1_LVT i_0_26( + .A(n_0_660), .B(n_0_26), .C1(n_0_707), .C2(op1[18]), .ZN(n_0_25) + ); + OAI22_X1_LVT i_0_25( + .A1(op2[19]), .A2(n_0_689), .B1(n_0_678), .B2(n_0_25), .ZN(n_0_24) + ); + AOI211_X1_LVT i_0_24( + .A(n_0_658), .B(n_0_659), .C1(n_0_657), .C2(n_0_24), .ZN(n_0_23) + ); + AOI221_X1_LVT i_0_23( + .A(n_0_23), .B1(n_0_726), .B2(op2[21]), .C1(n_0_687), .C2(op2[22]), .ZN(n_0_22) + ); + AOI221_X1_LVT i_0_22( + .A(n_0_22), .B1(op1[22]), .B2(n_0_686), .C1(op1[23]), .C2(n_0_718), .ZN(n_0_21) + ); + AOI221_X1_LVT i_0_21( + .A(n_0_21), .B1(n_0_736), .B2(op2[24]), .C1(n_0_719), .C2(op2[23]), .ZN(n_0_20) + ); + OAI222_X1_LVT i_0_20( + .A1(op1[26]), .A2(n_0_709), .B1(op1[25]), .B2(n_0_697), .C1(n_0_679), .C2(n_0_20), + .ZN(n_0_19) + ); + OAI221_X1_LVT i_0_19( + .A(n_0_19), .B1(n_0_711), .B2(op2[26]), .C1(n_0_688), .C2(op2[27]), .ZN(n_0_18) + ); + AOI22_X1_LVT i_0_18( + .A1(n_0_700), .A2(op1[28]), .B1(n_0_661), .B2(n_0_18), .ZN(n_0_17) + ); + OAI21_X1_LVT i_0_17( + .A(n_0_652), .B1(n_0_680), .B2(n_0_17), .ZN(n_0_16) + ); + INV_X1_LVT i_0_749( + .A(op2[30]), .ZN(n_0_716) + ); + OAI21_X1_LVT i_0_16( + .A(n_0_16), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_15) + ); + OAI22_X1_LVT i_0_708( + .A1(n_0_692), .A2(op1[31]), .B1(op2[31]), .B2(n_0_691), .ZN(n_0_675) + ); + AOI21_X1_LVT i_0_15( + .A(n_0_675), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_14) + ); + AOI21_X1_LVT i_0_13( + .A(n_0_13), .B1(n_0_15), .B2(n_0_14), .ZN(n_0_12) + ); + NOR4_X1_LVT i_0_12( + .A1(n_0_685), .A2(aluOp[2]), .A3(aluBypass), .A4(n_0_12), .ZN(n_0_11) + ); + OR3_X1_LVT i_0_0( + .A1(n_0_6), .A2(n_0_0), .A3(n_0_11), .ZN(result[0]) + ); + OR4_X1_LVT i_0_703( + .A1(n_0_680), .A2(n_0_673), .A3(n_0_675), .A4(n_0_678), .ZN(n_0_670) + ); + INV_X1_LVT i_0_709( + .A(n_0_677), .ZN(n_0_676) + ); + OR4_X1_LVT i_0_702( + .A1(n_0_679), .A2(n_0_674), .A3(n_0_676), .A4(n_0_671), .ZN(n_0_669) + ); + AOI22_X1_LVT i_0_663( + .A1(n_0_688), .A2(op2[27]), .B1(op1[22]), .B2(n_0_686), .ZN(n_0_630) + ); + OAI22_X1_LVT i_0_662( + .A1(n_0_694), .A2(op2[2]), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_629) + ); + AOI221_X1_LVT i_0_661( + .A(n_0_629), .B1(n_0_711), .B2(op2[26]), .C1(n_0_721), .C2(op2[14]), .ZN(n_0_628) + ); + AOI21_X1_LVT i_0_664( + .A(n_0_660), .B1(n_0_690), .B2(op1[19]), .ZN(n_0_631) + ); + OAI222_X1_LVT i_0_660( + .A1(op1[12]), .A2(n_0_695), .B1(n_0_688), .B2(op2[27]), .C1(op1[22]), .C2(n_0_686), + .ZN(n_0_627) + ); + AOI21_X1_LVT i_0_659( + .A(n_0_663), .B1(n_0_734), .B2(op2[15]), .ZN(n_0_626) + ); + OAI211_X1_LVT i_0_658( + .A(n_0_666), .B(n_0_626), .C1(n_0_715), .C2(op1[13]), .ZN(n_0_625) + ); + AOI211_X1_LVT i_0_657( + .A(n_0_627), .B(n_0_625), .C1(op1[23]), .C2(n_0_718), .ZN(n_0_624) + ); + NAND4_X1_LVT i_0_656( + .A1(n_0_630), .A2(n_0_628), .A3(n_0_631), .A4(n_0_624), .ZN(n_0_623) + ); + OAI22_X1_LVT i_0_684( + .A1(n_0_721), .A2(op2[14]), .B1(n_0_722), .B2(op2[9]), .ZN(n_0_651) + ); + AOI211_X1_LVT i_0_668( + .A(n_0_651), .B(n_0_654), .C1(n_0_719), .C2(op2[23]), .ZN(n_0_635) + ); + NAND2_X1_LVT i_0_667( + .A1(n_0_664), .A2(n_0_657), .ZN(n_0_634) + ); + NOR3_X1_LVT i_0_666( + .A1(n_0_659), .A2(n_0_656), .A3(n_0_634), .ZN(n_0_633) + ); + AOI21_X1_LVT i_0_671( + .A(n_0_655), .B1(n_0_739), .B2(op2[16]), .ZN(n_0_638) + ); + AOI21_X1_LVT i_0_670( + .A(n_0_668), .B1(n_0_736), .B2(op2[24]), .ZN(n_0_637) + ); + OAI22_X1_LVT i_0_673( + .A1(n_0_735), .A2(op1[10]), .B1(n_0_734), .B2(op2[15]), .ZN(n_0_640) + ); + AOI221_X1_LVT i_0_672( + .A(n_0_640), .B1(n_0_732), .B2(op2[17]), .C1(n_0_731), .C2(op1[5]), .ZN(n_0_639) + ); + AND3_X1_LVT i_0_669( + .A1(n_0_638), .A2(n_0_637), .A3(n_0_639), .ZN(n_0_636) + ); + OAI22_X1_LVT i_0_682( + .A1(n_0_703), .A2(op2[0]), .B1(n_0_704), .B2(op2[6]), .ZN(n_0_649) + ); + OAI22_X1_LVT i_0_681( + .A1(op2[28]), .A2(n_0_698), .B1(op1[25]), .B2(n_0_697), .ZN(n_0_648) + ); + AOI21_X1_LVT i_0_678( + .A(n_0_658), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_645) + ); + AOI21_X1_LVT i_0_677( + .A(n_0_662), .B1(n_0_735), .B2(op1[10]), .ZN(n_0_644) + ); + INV_X1_LVT i_0_758( + .A(op2[21]), .ZN(n_0_725) + ); + OAI22_X1_LVT i_0_683( + .A1(op1[21]), .A2(n_0_725), .B1(n_0_739), .B2(op2[16]), .ZN(n_0_650) + ); + AOI221_X1_LVT i_0_676( + .A(n_0_650), .B1(n_0_722), .B2(op2[9]), .C1(op1[7]), .C2(n_0_712), .ZN(n_0_643) + ); + OAI21_X1_LVT i_0_680( + .A(n_0_652), .B1(n_0_711), .B2(op2[26]), .ZN(n_0_647) + ); + AOI221_X1_LVT i_0_679( + .A(n_0_647), .B1(n_0_706), .B2(op2[11]), .C1(n_0_707), .C2(op1[18]), .ZN(n_0_646) + ); + NAND4_X1_LVT i_0_675( + .A1(n_0_645), .A2(n_0_644), .A3(n_0_643), .A4(n_0_646), .ZN(n_0_642) + ); + NOR3_X1_LVT i_0_674( + .A1(n_0_649), .A2(n_0_648), .A3(n_0_642), .ZN(n_0_641) + ); + NAND4_X1_LVT i_0_665( + .A1(n_0_635), .A2(n_0_633), .A3(n_0_636), .A4(n_0_641), .ZN(n_0_632) + ); + NOR4_X1_LVT i_0_655( + .A1(n_0_670), .A2(n_0_669), .A3(n_0_623), .A4(n_0_632), .ZN(eqFlag) + ); +endmodule + +module decoder(CurrentPC, JumpOrBranchPC, JumpOrBranch, DAddr, WData, RData, Instruction, + WrMem, DWidth, Rs1, Rs2, Rd, RRs1, RRs2, WRd, WrReg, Illegal); + input [31:0] CurrentPC, RData, Instruction, RRs1, RRs2; + output [31:0] JumpOrBranchPC, DAddr, WData, WRd; + output [4:0] Rs1, Rs2, Rd; + output [1:0] DWidth; + output JumpOrBranch, WrMem, WrReg, Illegal; + + wire [31:0] op1, op2; + wire [2:0] aluOp; + wire eqFlag, n_5_0, n_5_1, n_5_2, n_5_3, n_5_4, n_5_5, n_5_6, n_5_7, n_5_8, + n_5_9, n_5_10, n_5_11, n_5_12, n_5_13, n_5_14, n_5_15, n_5_16, n_5_17, + n_5_18, n_5_19, n_5_20, n_5_21, n_5_22, n_5_23, n_5_24, n_5_25, n_5_26, + n_5_27, n_5_28, n_5_29, n_5_30, n_5_31, n_5_32, n_5_33, n_17_0, n_17_1, + n_17_2, n_17_3, n_17_4, n_17_5, n_17_6, n_17_7, n_17_8, n_17_9, n_17_10, + n_17_11, n_17_12, n_17_13, n_17_14, n_17_15, n_17_16, n_17_17, n_17_18, + n_17_19, n_17_20, n_17_21, n_17_22, n_17_23, n_17_24, n_17_25, n_17_26, + n_17_27, n_17_28, n_17_29, n_17_30, n_17_31, n_17_32, n_18_0, n_18_1, + n_18_2, n_18_3, n_18_4, n_18_5, n_18_6, n_18_7, n_18_8, n_18_9, n_18_10, + n_18_11, n_18_12, n_18_13, n_18_14, n_18_15, n_18_16, n_18_17, n_18_18, + n_18_19, n_18_20, n_18_21, n_18_22, n_18_23, n_18_24, n_18_25, n_18_26, + n_18_27, n_18_28, n_18_29, n_18_30, n_18_31, n_18_32, n_0_15, n_0_2, + n_0_16, n_0_3, n_0_17, n_0_4, n_0_18, n_0_5, n_0_19, n_0_6, n_0_20, + n_0_7, n_0_21, n_0_8, n_0_22, n_0_9, n_0_23, n_0_10, n_0_24, n_0_11, + n_0_25, n_0_12, n_0_26, n_0_13, n_0_27, n_0_14, n_0_28, n_0_29, n_0_30, + n_0_31, n_0_32, n_0_33, n_0_34, n_0_35, n_0_36, n_0_37, n_0_38, n_0_39, + n_0_40, n_0_41, n_0_42, n_0_43, n_0_44, n_0_45, n_0_46, n_0_47, n_0_48, + n_0_49, n_0_50, n_0_51, n_0_52, n_0_53, n_0_54, n_0_55, n_0_56, n_0_57, + n_0_58, n_0_59, n_0_60, n_0_61, n_0_62, n_0_63, n_0_64, n_0_65, n_0_66, + n_0_67, n_0_68, n_0_69, n_0_70, n_0_71, n_0_72, n_0_73, n_0_74, n_0_75, + n_0_76, n_0_77, n_0_78, n_0_79, n_0_80, n_0_81, n_0_82, n_0_83, n_0_84, + n_0_85, n_0_86, n_0_87, n_0_88, n_0_89, n_0_90, n_0_91, n_0_92, n_0_93, + n_0_94, n_0_95, n_0_96, n_0_97, n_0_98, n_0_99, n_0_100, aluNegAr, + n_0_101, n_0_102, n_0_103, n_0_104, n_0_105, aluBypass, n_0_106, + n_0_107, n_0_108, n_0_109, n_0_110, n_0_111, n_0_112, n_0_113, n_0_114, + n_0_115, n_0_116, n_0_117, n_0_118, n_0_119, n_0_120, n_0_121, n_0_122, + n_0_123, n_0_124, n_0_125, n_0_126, n_0_127, n_0_128, n_0_129, n_0_130, + n_0_131, n_0_132, n_0_133, n_0_134, n_0_135, n_0_136, n_0_137, n_0_138, + n_0_139, n_0_140, n_0_141, n_0_142, n_0_143, n_0_144, n_0_145, n_0_146, + n_0_147, n_0_148, n_0_149, n_0_150, n_0_151, n_0_152, n_0_153, n_0_154, + n_0_155, n_0_156, n_0_157, n_0_158, n_0_159, n_0_160, n_0_161, n_0_162, + n_0_163, n_0_164, n_0_165, n_0_166, n_0_167, n_0_168, n_0_169, n_0_170, + n_0_171, n_0_172, n_0_173, n_0_174, n_0_175, n_0_176, n_0_177, n_0_178, + n_0_179, n_0_180, n_0_181, n_0_182, n_0_183, n_0_184, n_0_185, n_0_186, + n_0_187, n_0_188, n_0_189, n_0_190, n_0_191, n_0_192, n_0_193, n_0_194, + n_0_195, n_0_196, n_0_197, n_0_198, n_0_199, n_0_200, n_0_201, n_0_202, + n_0_203, n_0_204, n_0_205, n_0_206, n_0_207, n_0_208, n_0_209, n_0_210, + n_0_211, n_0_212, n_0_213, n_0_214, n_0_215, n_0_216, n_0_217, n_0_218, + n_0_219, n_0_220, n_0_221, n_0_222, n_0_223, n_0_224, n_0_225, n_0_226, + n_0_227, n_0_228, n_0_229, n_0_230, n_0_231, n_0_232, n_0_233, n_0_234, + n_0_235, n_0_236, n_0_237, n_0_238, n_0_239, n_0_240, n_0_241, n_0_242, + n_0_1, n_0_0, n_0_243, n_0_244, n_0_245, n_0_246, n_0_247, n_0_248, + n_0_249, n_63, n_64, n_65, n_66, n_67, n_68, n_69, n_70, n_71, n_72, + n_73, n_74, n_75, n_76, n_77, n_78, n_79, n_80, n_81, n_82, n_83, n_84, + n_85, n_86, n_87, n_88, n_89, n_90, n_91, n_92, n_93, n_32, n_33, n_34, + n_35, n_36, n_37, n_38, n_39, n_40, n_41, n_42, n_43, n_44, n_45, n_46, + n_47, n_48, n_49, n_50, n_51, n_52, n_53, n_54, n_55, n_56, n_57, n_58, + n_59, n_60, n_61, n_62, n_0, n_1, n_2, n_3, n_4, n_5, n_6, n_7, n_8, + n_9, n_10, n_11, n_12, n_13, n_14, n_15, n_16, n_17, n_18, n_19, n_20, + n_21, n_22, n_23, n_24, n_25, n_26, n_27, n_28, n_29, n_30, n_31; + + INV_X1_LVT i_18_1( + .A(CurrentPC[13]), .ZN(n_18_1) + ); + XNOR2_X1_LVT i_18_32( + .A(CurrentPC[31]), .B(n_18_1), .ZN(n_18_32) + ); + INV_X1_LVT i_18_0( + .A(Instruction[31]), .ZN(n_18_0) + ); + HA_X1_LVT i_18_2( + .A(Instruction[8]), .B(CurrentPC[1]), .CO(n_18_2), .S(n_63) + ); + FA_X1_LVT i_18_3( + .A(Instruction[9]), .B(CurrentPC[2]), .CI(n_18_2), .CO(n_18_3), .S(n_64) + ); + FA_X1_LVT i_18_4( + .A(Instruction[10]), .B(CurrentPC[3]), .CI(n_18_3), .CO(n_18_4), .S(n_65) + ); + FA_X1_LVT i_18_5( + .A(Instruction[11]), .B(CurrentPC[4]), .CI(n_18_4), .CO(n_18_5), .S(n_66) + ); + FA_X1_LVT i_18_6( + .A(Instruction[25]), .B(CurrentPC[5]), .CI(n_18_5), .CO(n_18_6), .S(n_67) + ); + FA_X1_LVT i_18_7( + .A(Instruction[26]), .B(CurrentPC[6]), .CI(n_18_6), .CO(n_18_7), .S(n_68) + ); + FA_X1_LVT i_18_8( + .A(Instruction[27]), .B(CurrentPC[7]), .CI(n_18_7), .CO(n_18_8), .S(n_69) + ); + FA_X1_LVT i_18_9( + .A(Instruction[28]), .B(CurrentPC[8]), .CI(n_18_8), .CO(n_18_9), .S(n_70) + ); + FA_X1_LVT i_18_10( + .A(Instruction[29]), .B(CurrentPC[9]), .CI(n_18_9), .CO(n_18_10), .S(n_71) + ); + FA_X1_LVT i_18_11( + .A(Instruction[30]), .B(CurrentPC[10]), .CI(n_18_10), .CO(n_18_11), .S(n_72) + ); + FA_X1_LVT i_18_12( + .A(Instruction[7]), .B(CurrentPC[11]), .CI(n_18_11), .CO(n_18_12), .S(n_73) + ); + FA_X1_LVT i_18_13( + .A(CurrentPC[12]), .B(Instruction[31]), .CI(n_18_12), .CO(n_18_13), .S(n_74) + ); + FA_X1_LVT i_18_14( + .A(n_18_0), .B(n_18_1), .CI(n_18_13), .CO(n_18_14), .S(n_75) + ); + FA_X1_LVT i_18_15( + .A(CurrentPC[14]), .B(n_18_1), .CI(n_18_14), .CO(n_18_15), .S(n_76) + ); + FA_X1_LVT i_18_16( + .A(CurrentPC[15]), .B(n_18_1), .CI(n_18_15), .CO(n_18_16), .S(n_77) + ); + FA_X1_LVT i_18_17( + .A(CurrentPC[16]), .B(n_18_1), .CI(n_18_16), .CO(n_18_17), .S(n_78) + ); + FA_X1_LVT i_18_18( + .A(CurrentPC[17]), .B(n_18_1), .CI(n_18_17), .CO(n_18_18), .S(n_79) + ); + FA_X1_LVT i_18_19( + .A(CurrentPC[18]), .B(n_18_1), .CI(n_18_18), .CO(n_18_19), .S(n_80) + ); + FA_X1_LVT i_18_20( + .A(CurrentPC[19]), .B(n_18_1), .CI(n_18_19), .CO(n_18_20), .S(n_81) + ); + FA_X1_LVT i_18_21( + .A(CurrentPC[20]), .B(n_18_1), .CI(n_18_20), .CO(n_18_21), .S(n_82) + ); + FA_X1_LVT i_18_22( + .A(CurrentPC[21]), .B(n_18_1), .CI(n_18_21), .CO(n_18_22), .S(n_83) + ); + FA_X1_LVT i_18_23( + .A(CurrentPC[22]), .B(n_18_1), .CI(n_18_22), .CO(n_18_23), .S(n_84) + ); + FA_X1_LVT i_18_24( + .A(CurrentPC[23]), .B(n_18_1), .CI(n_18_23), .CO(n_18_24), .S(n_85) + ); + FA_X1_LVT i_18_25( + .A(CurrentPC[24]), .B(n_18_1), .CI(n_18_24), .CO(n_18_25), .S(n_86) + ); + FA_X1_LVT i_18_26( + .A(CurrentPC[25]), .B(n_18_1), .CI(n_18_25), .CO(n_18_26), .S(n_87) + ); + FA_X1_LVT i_18_27( + .A(CurrentPC[26]), .B(n_18_1), .CI(n_18_26), .CO(n_18_27), .S(n_88) + ); + FA_X1_LVT i_18_28( + .A(CurrentPC[27]), .B(n_18_1), .CI(n_18_27), .CO(n_18_28), .S(n_89) + ); + FA_X1_LVT i_18_29( + .A(CurrentPC[28]), .B(n_18_1), .CI(n_18_28), .CO(n_18_29), .S(n_90) + ); + FA_X1_LVT i_18_30( + .A(CurrentPC[29]), .B(n_18_1), .CI(n_18_29), .CO(n_18_30), .S(n_91) + ); + FA_X1_LVT i_18_31( + .A(CurrentPC[30]), .B(n_18_1), .CI(n_18_30), .CO(n_18_31), .S(n_92) + ); + XNOR2_X1_LVT i_18_33( + .A(n_18_32), .B(n_18_31), .ZN(n_93) + ); + INV_X1_LVT i_0_350( + .A(Instruction[3]), .ZN(n_0_243) + ); + NAND3_X1_LVT i_0_343( + .A1(n_0_243), .A2(Instruction[0]), .A3(Instruction[1]), .ZN(n_0_238) + ); + OR2_X1_LVT i_0_332( + .A1(n_0_238), .A2(Instruction[2]), .ZN(n_0_228) + ); + INV_X1_LVT i_0_351( + .A(Instruction[5]), .ZN(n_0_244) + ); + NOR2_X1_LVT i_0_340( + .A1(n_0_244), .A2(Instruction[4]), .ZN(n_0_235) + ); + NAND2_X1_LVT i_0_329( + .A1(Instruction[6]), .A2(n_0_235), .ZN(n_0_225) + ); + INV_X1_LVT i_0_354( + .A(Instruction[13]), .ZN(n_0_247) + ); + NOR2_X1_LVT i_0_345( + .A1(n_0_247), .A2(Instruction[14]), .ZN(n_0_240) + ); + NOR3_X1_LVT i_0_118( + .A1(n_0_228), .A2(n_0_225), .A3(n_0_240), .ZN(n_0_99) + ); + NAND3_X1_LVT i_0_346( + .A1(Instruction[0]), .A2(Instruction[1]), .A3(Instruction[2]), .ZN(n_0_241) + ); + NOR2_X1_LVT i_0_328( + .A1(n_0_241), .A2(n_0_225), .ZN(n_0_224) + ); + INV_X1_LVT i_0_356( + .A(n_0_224), .ZN(n_0_249) + ); + NOR2_X1_LVT i_0_108( + .A1(n_0_243), .A2(n_0_249), .ZN(n_0_91) + ); + INV_X1_LVT i_17_1( + .A(CurrentPC[21]), .ZN(n_17_1) + ); + XNOR2_X1_LVT i_17_32( + .A(CurrentPC[31]), .B(n_17_1), .ZN(n_17_32) + ); + INV_X1_LVT i_17_0( + .A(Instruction[31]), .ZN(n_17_0) + ); + HA_X1_LVT i_17_2( + .A(Instruction[21]), .B(CurrentPC[1]), .CO(n_17_2), .S(n_32) + ); + FA_X1_LVT i_17_3( + .A(Instruction[22]), .B(CurrentPC[2]), .CI(n_17_2), .CO(n_17_3), .S(n_33) + ); + FA_X1_LVT i_17_4( + .A(Instruction[23]), .B(CurrentPC[3]), .CI(n_17_3), .CO(n_17_4), .S(n_34) + ); + FA_X1_LVT i_17_5( + .A(Instruction[24]), .B(CurrentPC[4]), .CI(n_17_4), .CO(n_17_5), .S(n_35) + ); + FA_X1_LVT i_17_6( + .A(Instruction[25]), .B(CurrentPC[5]), .CI(n_17_5), .CO(n_17_6), .S(n_36) + ); + FA_X1_LVT i_17_7( + .A(Instruction[26]), .B(CurrentPC[6]), .CI(n_17_6), .CO(n_17_7), .S(n_37) + ); + FA_X1_LVT i_17_8( + .A(Instruction[27]), .B(CurrentPC[7]), .CI(n_17_7), .CO(n_17_8), .S(n_38) + ); + FA_X1_LVT i_17_9( + .A(Instruction[28]), .B(CurrentPC[8]), .CI(n_17_8), .CO(n_17_9), .S(n_39) + ); + FA_X1_LVT i_17_10( + .A(Instruction[29]), .B(CurrentPC[9]), .CI(n_17_9), .CO(n_17_10), .S(n_40) + ); + FA_X1_LVT i_17_11( + .A(Instruction[30]), .B(CurrentPC[10]), .CI(n_17_10), .CO(n_17_11), .S(n_41) + ); + FA_X1_LVT i_17_12( + .A(Instruction[20]), .B(CurrentPC[11]), .CI(n_17_11), .CO(n_17_12), .S(n_42) + ); + FA_X1_LVT i_17_13( + .A(Instruction[12]), .B(CurrentPC[12]), .CI(n_17_12), .CO(n_17_13), .S(n_43) + ); + FA_X1_LVT i_17_14( + .A(Instruction[13]), .B(CurrentPC[13]), .CI(n_17_13), .CO(n_17_14), .S(n_44) + ); + FA_X1_LVT i_17_15( + .A(Instruction[14]), .B(CurrentPC[14]), .CI(n_17_14), .CO(n_17_15), .S(n_45) + ); + FA_X1_LVT i_17_16( + .A(Instruction[15]), .B(CurrentPC[15]), .CI(n_17_15), .CO(n_17_16), .S(n_46) + ); + FA_X1_LVT i_17_17( + .A(Instruction[16]), .B(CurrentPC[16]), .CI(n_17_16), .CO(n_17_17), .S(n_47) + ); + FA_X1_LVT i_17_18( + .A(Instruction[17]), .B(CurrentPC[17]), .CI(n_17_17), .CO(n_17_18), .S(n_48) + ); + FA_X1_LVT i_17_19( + .A(Instruction[18]), .B(CurrentPC[18]), .CI(n_17_18), .CO(n_17_19), .S(n_49) + ); + FA_X1_LVT i_17_20( + .A(Instruction[19]), .B(CurrentPC[19]), .CI(n_17_19), .CO(n_17_20), .S(n_50) + ); + FA_X1_LVT i_17_21( + .A(CurrentPC[20]), .B(Instruction[31]), .CI(n_17_20), .CO(n_17_21), .S(n_51) + ); + FA_X1_LVT i_17_22( + .A(n_17_0), .B(n_17_1), .CI(n_17_21), .CO(n_17_22), .S(n_52) + ); + FA_X1_LVT i_17_23( + .A(CurrentPC[22]), .B(n_17_1), .CI(n_17_22), .CO(n_17_23), .S(n_53) + ); + FA_X1_LVT i_17_24( + .A(CurrentPC[23]), .B(n_17_1), .CI(n_17_23), .CO(n_17_24), .S(n_54) + ); + FA_X1_LVT i_17_25( + .A(CurrentPC[24]), .B(n_17_1), .CI(n_17_24), .CO(n_17_25), .S(n_55) + ); + FA_X1_LVT i_17_26( + .A(CurrentPC[25]), .B(n_17_1), .CI(n_17_25), .CO(n_17_26), .S(n_56) + ); + FA_X1_LVT i_17_27( + .A(CurrentPC[26]), .B(n_17_1), .CI(n_17_26), .CO(n_17_27), .S(n_57) + ); + FA_X1_LVT i_17_28( + .A(CurrentPC[27]), .B(n_17_1), .CI(n_17_27), .CO(n_17_28), .S(n_58) + ); + FA_X1_LVT i_17_29( + .A(CurrentPC[28]), .B(n_17_1), .CI(n_17_28), .CO(n_17_29), .S(n_59) + ); + FA_X1_LVT i_17_30( + .A(CurrentPC[29]), .B(n_17_1), .CI(n_17_29), .CO(n_17_30), .S(n_60) + ); + FA_X1_LVT i_17_31( + .A(CurrentPC[30]), .B(n_17_1), .CI(n_17_30), .CO(n_17_31), .S(n_61) + ); + XNOR2_X1_LVT i_17_33( + .A(n_17_32), .B(n_17_31), .ZN(n_62) + ); + INV_X1_LVT i_5_1( + .A(RRs1[12]), .ZN(n_5_1) + ); + XNOR2_X1_LVT i_5_33( + .A(RRs1[31]), .B(n_5_1), .ZN(n_5_33) + ); + INV_X1_LVT i_5_0( + .A(Instruction[31]), .ZN(n_5_0) + ); + HA_X1_LVT i_5_2( + .A(Instruction[20]), .B(RRs1[0]), .CO(n_5_2), .S(n_0) + ); + FA_X1_LVT i_5_3( + .A(Instruction[21]), .B(RRs1[1]), .CI(n_5_2), .CO(n_5_3), .S(n_1) + ); + FA_X1_LVT i_5_4( + .A(Instruction[22]), .B(RRs1[2]), .CI(n_5_3), .CO(n_5_4), .S(n_2) + ); + FA_X1_LVT i_5_5( + .A(Instruction[23]), .B(RRs1[3]), .CI(n_5_4), .CO(n_5_5), .S(n_3) + ); + FA_X1_LVT i_5_6( + .A(Instruction[24]), .B(RRs1[4]), .CI(n_5_5), .CO(n_5_6), .S(n_4) + ); + FA_X1_LVT i_5_7( + .A(Instruction[25]), .B(RRs1[5]), .CI(n_5_6), .CO(n_5_7), .S(n_5) + ); + FA_X1_LVT i_5_8( + .A(Instruction[26]), .B(RRs1[6]), .CI(n_5_7), .CO(n_5_8), .S(n_6) + ); + FA_X1_LVT i_5_9( + .A(Instruction[27]), .B(RRs1[7]), .CI(n_5_8), .CO(n_5_9), .S(n_7) + ); + FA_X1_LVT i_5_10( + .A(Instruction[28]), .B(RRs1[8]), .CI(n_5_9), .CO(n_5_10), .S(n_8) + ); + FA_X1_LVT i_5_11( + .A(Instruction[29]), .B(RRs1[9]), .CI(n_5_10), .CO(n_5_11), .S(n_9) + ); + FA_X1_LVT i_5_12( + .A(Instruction[30]), .B(RRs1[10]), .CI(n_5_11), .CO(n_5_12), .S(n_10) + ); + FA_X1_LVT i_5_13( + .A(RRs1[11]), .B(Instruction[31]), .CI(n_5_12), .CO(n_5_13), .S(n_11) + ); + FA_X1_LVT i_5_14( + .A(n_5_0), .B(n_5_1), .CI(n_5_13), .CO(n_5_14), .S(n_12) + ); + FA_X1_LVT i_5_15( + .A(RRs1[13]), .B(n_5_1), .CI(n_5_14), .CO(n_5_15), .S(n_13) + ); + FA_X1_LVT i_5_16( + .A(RRs1[14]), .B(n_5_1), .CI(n_5_15), .CO(n_5_16), .S(n_14) + ); + FA_X1_LVT i_5_17( + .A(RRs1[15]), .B(n_5_1), .CI(n_5_16), .CO(n_5_17), .S(n_15) + ); + FA_X1_LVT i_5_18( + .A(RRs1[16]), .B(n_5_1), .CI(n_5_17), .CO(n_5_18), .S(n_16) + ); + FA_X1_LVT i_5_19( + .A(RRs1[17]), .B(n_5_1), .CI(n_5_18), .CO(n_5_19), .S(n_17) + ); + FA_X1_LVT i_5_20( + .A(RRs1[18]), .B(n_5_1), .CI(n_5_19), .CO(n_5_20), .S(n_18) + ); + FA_X1_LVT i_5_21( + .A(RRs1[19]), .B(n_5_1), .CI(n_5_20), .CO(n_5_21), .S(n_19) + ); + FA_X1_LVT i_5_22( + .A(RRs1[20]), .B(n_5_1), .CI(n_5_21), .CO(n_5_22), .S(n_20) + ); + FA_X1_LVT i_5_23( + .A(RRs1[21]), .B(n_5_1), .CI(n_5_22), .CO(n_5_23), .S(n_21) + ); + FA_X1_LVT i_5_24( + .A(RRs1[22]), .B(n_5_1), .CI(n_5_23), .CO(n_5_24), .S(n_22) + ); + FA_X1_LVT i_5_25( + .A(RRs1[23]), .B(n_5_1), .CI(n_5_24), .CO(n_5_25), .S(n_23) + ); + FA_X1_LVT i_5_26( + .A(RRs1[24]), .B(n_5_1), .CI(n_5_25), .CO(n_5_26), .S(n_24) + ); + FA_X1_LVT i_5_27( + .A(RRs1[25]), .B(n_5_1), .CI(n_5_26), .CO(n_5_27), .S(n_25) + ); + FA_X1_LVT i_5_28( + .A(RRs1[26]), .B(n_5_1), .CI(n_5_27), .CO(n_5_28), .S(n_26) + ); + FA_X1_LVT i_5_29( + .A(RRs1[27]), .B(n_5_1), .CI(n_5_28), .CO(n_5_29), .S(n_27) + ); + FA_X1_LVT i_5_30( + .A(RRs1[28]), .B(n_5_1), .CI(n_5_29), .CO(n_5_30), .S(n_28) + ); + FA_X1_LVT i_5_31( + .A(RRs1[29]), .B(n_5_1), .CI(n_5_30), .CO(n_5_31), .S(n_29) + ); + FA_X1_LVT i_5_32( + .A(RRs1[30]), .B(n_5_1), .CI(n_5_31), .CO(n_5_32), .S(n_30) + ); + XNOR2_X1_LVT i_5_34( + .A(n_5_33), .B(n_5_32), .ZN(n_31) + ); + NOR2_X1_LVT i_0_107( + .A1(n_0_249), .A2(Instruction[3]), .ZN(n_0_90) + ); + AOI222_X1_LVT i_0_106( + .A1(n_93), .A2(n_0_99), .B1(n_0_91), .B2(n_62), .C1(n_31), .C2(n_0_90), .ZN(n_0_89) + ); + INV_X1_LVT i_0_355( + .A(Instruction[6]), .ZN(n_0_248) + ); + NAND2_X1_LVT i_0_339( + .A1(n_0_248), .A2(Instruction[4]), .ZN(n_0_234) + ); + INV_X1_LVT i_0_338( + .A(n_0_234), .ZN(n_0_233) + ); + OAI21_X1_LVT i_0_341( + .A(Instruction[13]), .B1(Instruction[14]), .B2(Instruction[12]), .ZN(n_0_236) + ); + AOI211_X1_LVT i_0_337( + .A(n_0_235), .B(n_0_233), .C1(n_0_248), .C2(n_0_236), .ZN(n_0_232) + ); + INV_X1_LVT i_0_352( + .A(Instruction[4]), .ZN(n_0_245) + ); + NAND2_X1_LVT i_0_344( + .A1(n_0_245), .A2(Instruction[2]), .ZN(n_0_239) + ); + AOI21_X1_LVT i_0_335( + .A(Instruction[6]), .B1(n_0_243), .B2(n_0_239), .ZN(n_0_230) + ); + NOR2_X1_LVT i_0_334( + .A1(n_0_232), .A2(n_0_230), .ZN(n_0_229) + ); + NAND2_X1_LVT i_0_342( + .A1(n_0_241), .A2(n_0_238), .ZN(n_0_237) + ); + NAND2_X1_LVT i_0_336( + .A1(Instruction[6]), .A2(n_0_240), .ZN(n_0_231) + ); + OAI211_X1_LVT i_0_333( + .A(n_0_229), .B(n_0_237), .C1(Instruction[2]), .C2(n_0_231), .ZN(Illegal) + ); + NAND2_X1_LVT i_0_109( + .A1(Illegal), .A2(CurrentPC[31]), .ZN(n_0_92) + ); + NAND2_X1_LVT i_0_105( + .A1(n_0_89), .A2(n_0_92), .ZN(JumpOrBranchPC[31]) + ); + AOI222_X1_LVT i_0_103( + .A1(n_92), .A2(n_0_99), .B1(n_0_91), .B2(n_61), .C1(n_30), .C2(n_0_90), .ZN(n_0_87) + ); + NAND2_X1_LVT i_0_104( + .A1(Illegal), .A2(CurrentPC[30]), .ZN(n_0_88) + ); + NAND2_X1_LVT i_0_102( + .A1(n_0_87), .A2(n_0_88), .ZN(JumpOrBranchPC[30]) + ); + AOI222_X1_LVT i_0_100( + .A1(n_91), .A2(n_0_99), .B1(n_0_91), .B2(n_60), .C1(n_29), .C2(n_0_90), .ZN(n_0_85) + ); + NAND2_X1_LVT i_0_101( + .A1(Illegal), .A2(CurrentPC[29]), .ZN(n_0_86) + ); + NAND2_X1_LVT i_0_99( + .A1(n_0_85), .A2(n_0_86), .ZN(JumpOrBranchPC[29]) + ); + AOI222_X1_LVT i_0_97( + .A1(n_90), .A2(n_0_99), .B1(n_0_91), .B2(n_59), .C1(n_28), .C2(n_0_90), .ZN(n_0_83) + ); + NAND2_X1_LVT i_0_98( + .A1(Illegal), .A2(CurrentPC[28]), .ZN(n_0_84) + ); + NAND2_X1_LVT i_0_96( + .A1(n_0_83), .A2(n_0_84), .ZN(JumpOrBranchPC[28]) + ); + AOI222_X1_LVT i_0_94( + .A1(n_89), .A2(n_0_99), .B1(n_0_91), .B2(n_58), .C1(n_27), .C2(n_0_90), .ZN(n_0_81) + ); + NAND2_X1_LVT i_0_95( + .A1(Illegal), .A2(CurrentPC[27]), .ZN(n_0_82) + ); + NAND2_X1_LVT i_0_93( + .A1(n_0_81), .A2(n_0_82), .ZN(JumpOrBranchPC[27]) + ); + AOI222_X1_LVT i_0_91( + .A1(n_88), .A2(n_0_99), .B1(n_0_91), .B2(n_57), .C1(n_26), .C2(n_0_90), .ZN(n_0_79) + ); + NAND2_X1_LVT i_0_92( + .A1(Illegal), .A2(CurrentPC[26]), .ZN(n_0_80) + ); + NAND2_X1_LVT i_0_90( + .A1(n_0_79), .A2(n_0_80), .ZN(JumpOrBranchPC[26]) + ); + AOI222_X1_LVT i_0_88( + .A1(n_87), .A2(n_0_99), .B1(n_0_91), .B2(n_56), .C1(n_25), .C2(n_0_90), .ZN(n_0_77) + ); + NAND2_X1_LVT i_0_89( + .A1(Illegal), .A2(CurrentPC[25]), .ZN(n_0_78) + ); + NAND2_X1_LVT i_0_87( + .A1(n_0_77), .A2(n_0_78), .ZN(JumpOrBranchPC[25]) + ); + AOI222_X1_LVT i_0_85( + .A1(n_86), .A2(n_0_99), .B1(n_0_91), .B2(n_55), .C1(n_24), .C2(n_0_90), .ZN(n_0_75) + ); + NAND2_X1_LVT i_0_86( + .A1(Illegal), .A2(CurrentPC[24]), .ZN(n_0_76) + ); + NAND2_X1_LVT i_0_84( + .A1(n_0_75), .A2(n_0_76), .ZN(JumpOrBranchPC[24]) + ); + AOI222_X1_LVT i_0_82( + .A1(n_85), .A2(n_0_99), .B1(n_0_91), .B2(n_54), .C1(n_23), .C2(n_0_90), .ZN(n_0_73) + ); + NAND2_X1_LVT i_0_83( + .A1(Illegal), .A2(CurrentPC[23]), .ZN(n_0_74) + ); + NAND2_X1_LVT i_0_81( + .A1(n_0_73), .A2(n_0_74), .ZN(JumpOrBranchPC[23]) + ); + AOI222_X1_LVT i_0_79( + .A1(n_84), .A2(n_0_99), .B1(n_0_91), .B2(n_53), .C1(n_22), .C2(n_0_90), .ZN(n_0_71) + ); + NAND2_X1_LVT i_0_80( + .A1(Illegal), .A2(CurrentPC[22]), .ZN(n_0_72) + ); + NAND2_X1_LVT i_0_78( + .A1(n_0_71), .A2(n_0_72), .ZN(JumpOrBranchPC[22]) + ); + AOI222_X1_LVT i_0_76( + .A1(n_83), .A2(n_0_99), .B1(n_0_91), .B2(n_52), .C1(n_21), .C2(n_0_90), .ZN(n_0_69) + ); + NAND2_X1_LVT i_0_77( + .A1(Illegal), .A2(CurrentPC[21]), .ZN(n_0_70) + ); + NAND2_X1_LVT i_0_75( + .A1(n_0_69), .A2(n_0_70), .ZN(JumpOrBranchPC[21]) + ); + AOI222_X1_LVT i_0_73( + .A1(n_82), .A2(n_0_99), .B1(n_0_91), .B2(n_51), .C1(n_20), .C2(n_0_90), .ZN(n_0_67) + ); + NAND2_X1_LVT i_0_74( + .A1(Illegal), .A2(CurrentPC[20]), .ZN(n_0_68) + ); + NAND2_X1_LVT i_0_72( + .A1(n_0_67), .A2(n_0_68), .ZN(JumpOrBranchPC[20]) + ); + AOI222_X1_LVT i_0_70( + .A1(n_81), .A2(n_0_99), .B1(n_0_91), .B2(n_50), .C1(n_19), .C2(n_0_90), .ZN(n_0_65) + ); + NAND2_X1_LVT i_0_71( + .A1(Illegal), .A2(CurrentPC[19]), .ZN(n_0_66) + ); + NAND2_X1_LVT i_0_69( + .A1(n_0_65), .A2(n_0_66), .ZN(JumpOrBranchPC[19]) + ); + AOI222_X1_LVT i_0_67( + .A1(n_80), .A2(n_0_99), .B1(n_0_91), .B2(n_49), .C1(n_18), .C2(n_0_90), .ZN(n_0_63) + ); + NAND2_X1_LVT i_0_68( + .A1(Illegal), .A2(CurrentPC[18]), .ZN(n_0_64) + ); + NAND2_X1_LVT i_0_66( + .A1(n_0_63), .A2(n_0_64), .ZN(JumpOrBranchPC[18]) + ); + AOI222_X1_LVT i_0_64( + .A1(n_79), .A2(n_0_99), .B1(n_0_91), .B2(n_48), .C1(n_17), .C2(n_0_90), .ZN(n_0_61) + ); + NAND2_X1_LVT i_0_65( + .A1(Illegal), .A2(CurrentPC[17]), .ZN(n_0_62) + ); + NAND2_X1_LVT i_0_63( + .A1(n_0_61), .A2(n_0_62), .ZN(JumpOrBranchPC[17]) + ); + AOI222_X1_LVT i_0_61( + .A1(n_78), .A2(n_0_99), .B1(n_0_91), .B2(n_47), .C1(n_16), .C2(n_0_90), .ZN(n_0_59) + ); + NAND2_X1_LVT i_0_62( + .A1(Illegal), .A2(CurrentPC[16]), .ZN(n_0_60) + ); + NAND2_X1_LVT i_0_60( + .A1(n_0_59), .A2(n_0_60), .ZN(JumpOrBranchPC[16]) + ); + AOI222_X1_LVT i_0_58( + .A1(n_77), .A2(n_0_99), .B1(n_0_91), .B2(n_46), .C1(n_15), .C2(n_0_90), .ZN(n_0_57) + ); + NAND2_X1_LVT i_0_59( + .A1(Illegal), .A2(CurrentPC[15]), .ZN(n_0_58) + ); + NAND2_X1_LVT i_0_57( + .A1(n_0_57), .A2(n_0_58), .ZN(JumpOrBranchPC[15]) + ); + AOI222_X1_LVT i_0_55( + .A1(n_76), .A2(n_0_99), .B1(n_0_91), .B2(n_45), .C1(n_14), .C2(n_0_90), .ZN(n_0_55) + ); + NAND2_X1_LVT i_0_56( + .A1(Illegal), .A2(CurrentPC[14]), .ZN(n_0_56) + ); + NAND2_X1_LVT i_0_54( + .A1(n_0_55), .A2(n_0_56), .ZN(JumpOrBranchPC[14]) + ); + AOI222_X1_LVT i_0_52( + .A1(n_75), .A2(n_0_99), .B1(n_0_91), .B2(n_44), .C1(n_13), .C2(n_0_90), .ZN(n_0_53) + ); + NAND2_X1_LVT i_0_53( + .A1(Illegal), .A2(CurrentPC[13]), .ZN(n_0_54) + ); + NAND2_X1_LVT i_0_51( + .A1(n_0_53), .A2(n_0_54), .ZN(JumpOrBranchPC[13]) + ); + AOI222_X1_LVT i_0_49( + .A1(n_74), .A2(n_0_99), .B1(n_0_91), .B2(n_43), .C1(n_12), .C2(n_0_90), .ZN(n_0_51) + ); + NAND2_X1_LVT i_0_50( + .A1(Illegal), .A2(CurrentPC[12]), .ZN(n_0_52) + ); + NAND2_X1_LVT i_0_48( + .A1(n_0_51), .A2(n_0_52), .ZN(JumpOrBranchPC[12]) + ); + AOI222_X1_LVT i_0_46( + .A1(n_73), .A2(n_0_99), .B1(n_0_91), .B2(n_42), .C1(n_11), .C2(n_0_90), .ZN(n_0_49) + ); + NAND2_X1_LVT i_0_47( + .A1(Illegal), .A2(CurrentPC[11]), .ZN(n_0_50) + ); + NAND2_X1_LVT i_0_45( + .A1(n_0_49), .A2(n_0_50), .ZN(JumpOrBranchPC[11]) + ); + AOI222_X1_LVT i_0_43( + .A1(n_72), .A2(n_0_99), .B1(n_0_91), .B2(n_41), .C1(n_10), .C2(n_0_90), .ZN(n_0_47) + ); + NAND2_X1_LVT i_0_44( + .A1(Illegal), .A2(CurrentPC[10]), .ZN(n_0_48) + ); + NAND2_X1_LVT i_0_42( + .A1(n_0_47), .A2(n_0_48), .ZN(JumpOrBranchPC[10]) + ); + AOI222_X1_LVT i_0_40( + .A1(n_71), .A2(n_0_99), .B1(n_0_91), .B2(n_40), .C1(n_9), .C2(n_0_90), .ZN(n_0_45) + ); + NAND2_X1_LVT i_0_41( + .A1(Illegal), .A2(CurrentPC[9]), .ZN(n_0_46) + ); + NAND2_X1_LVT i_0_39( + .A1(n_0_45), .A2(n_0_46), .ZN(JumpOrBranchPC[9]) + ); + AOI222_X1_LVT i_0_37( + .A1(n_70), .A2(n_0_99), .B1(n_0_91), .B2(n_39), .C1(n_8), .C2(n_0_90), .ZN(n_0_43) + ); + NAND2_X1_LVT i_0_38( + .A1(Illegal), .A2(CurrentPC[8]), .ZN(n_0_44) + ); + NAND2_X1_LVT i_0_36( + .A1(n_0_43), .A2(n_0_44), .ZN(JumpOrBranchPC[8]) + ); + AOI222_X1_LVT i_0_34( + .A1(n_69), .A2(n_0_99), .B1(n_0_91), .B2(n_38), .C1(n_7), .C2(n_0_90), .ZN(n_0_41) + ); + NAND2_X1_LVT i_0_35( + .A1(Illegal), .A2(CurrentPC[7]), .ZN(n_0_42) + ); + NAND2_X1_LVT i_0_33( + .A1(n_0_41), .A2(n_0_42), .ZN(JumpOrBranchPC[7]) + ); + AOI222_X1_LVT i_0_31( + .A1(n_68), .A2(n_0_99), .B1(n_0_91), .B2(n_37), .C1(n_6), .C2(n_0_90), .ZN(n_0_39) + ); + NAND2_X1_LVT i_0_32( + .A1(Illegal), .A2(CurrentPC[6]), .ZN(n_0_40) + ); + NAND2_X1_LVT i_0_30( + .A1(n_0_39), .A2(n_0_40), .ZN(JumpOrBranchPC[6]) + ); + AOI222_X1_LVT i_0_28( + .A1(n_67), .A2(n_0_99), .B1(n_0_91), .B2(n_36), .C1(n_5), .C2(n_0_90), .ZN(n_0_37) + ); + NAND2_X1_LVT i_0_29( + .A1(Illegal), .A2(CurrentPC[5]), .ZN(n_0_38) + ); + NAND2_X1_LVT i_0_27( + .A1(n_0_37), .A2(n_0_38), .ZN(JumpOrBranchPC[5]) + ); + AOI222_X1_LVT i_0_25( + .A1(n_66), .A2(n_0_99), .B1(n_0_91), .B2(n_35), .C1(n_4), .C2(n_0_90), .ZN(n_0_35) + ); + NAND2_X1_LVT i_0_26( + .A1(Illegal), .A2(CurrentPC[4]), .ZN(n_0_36) + ); + NAND2_X1_LVT i_0_24( + .A1(n_0_35), .A2(n_0_36), .ZN(JumpOrBranchPC[4]) + ); + AOI222_X1_LVT i_0_22( + .A1(n_65), .A2(n_0_99), .B1(n_0_91), .B2(n_34), .C1(n_3), .C2(n_0_90), .ZN(n_0_33) + ); + NAND2_X1_LVT i_0_23( + .A1(Illegal), .A2(CurrentPC[3]), .ZN(n_0_34) + ); + NAND2_X1_LVT i_0_21( + .A1(n_0_33), .A2(n_0_34), .ZN(JumpOrBranchPC[3]) + ); + AOI222_X1_LVT i_0_19( + .A1(n_64), .A2(n_0_99), .B1(n_0_91), .B2(n_33), .C1(n_2), .C2(n_0_90), .ZN(n_0_31) + ); + NAND2_X1_LVT i_0_20( + .A1(Illegal), .A2(CurrentPC[2]), .ZN(n_0_32) + ); + NAND2_X1_LVT i_0_18( + .A1(n_0_31), .A2(n_0_32), .ZN(JumpOrBranchPC[2]) + ); + AOI222_X1_LVT i_0_16( + .A1(n_63), .A2(n_0_99), .B1(n_0_91), .B2(n_32), .C1(n_1), .C2(n_0_90), .ZN(n_0_29) + ); + NAND2_X1_LVT i_0_17( + .A1(Illegal), .A2(CurrentPC[1]), .ZN(n_0_30) + ); + NAND2_X1_LVT i_0_15( + .A1(n_0_29), .A2(n_0_30), .ZN(JumpOrBranchPC[1]) + ); + NOR2_X1_LVT i_0_112( + .A1(n_0_232), .A2(n_0_238), .ZN(n_0_94) + ); + OAI221_X1_LVT i_0_14( + .A(n_0_94), .B1(n_0_225), .B2(Instruction[2]), .C1(Instruction[6]), .C2(n_0_239), + .ZN(n_0_28) + ); + AND2_X1_LVT i_0_13( + .A1(n_0_28), .A2(CurrentPC[0]), .ZN(JumpOrBranchPC[0]) + ); + NOR2_X1_LVT i_0_221( + .A1(Instruction[13]), .A2(Instruction[14]), .ZN(n_0_166) + ); + NOR3_X1_LVT i_0_293( + .A1(n_0_241), .A2(n_0_234), .A3(Instruction[3]), .ZN(n_0_206) + ); + AND2_X1_LVT i_0_292( + .A1(n_0_206), .A2(n_0_244), .ZN(n_0_205) + ); + NOR3_X1_LVT i_0_330( + .A1(n_0_248), .A2(n_0_244), .A3(Instruction[4]), .ZN(n_0_226) + ); + AOI21_X1_LVT i_0_121( + .A(n_0_205), .B1(n_0_226), .B2(n_0_237), .ZN(n_0_100) + ); + AND2_X1_LVT i_0_120( + .A1(Instruction[14]), .A2(n_0_100), .ZN(aluOp[2]) + ); + OAI33_X1_LVT i_0_119( + .A1(n_0_205), .A2(n_0_247), .A3(n_0_224), .B1(Instruction[2]), .B2(n_0_238), + .B3(n_0_225), .ZN(aluOp[1]) + ); + AOI22_X1_LVT i_0_117( + .A1(Instruction[12]), .A2(n_0_100), .B1(n_0_99), .B2(Instruction[13]), .ZN(n_0_98) + ); + INV_X1_LVT i_0_116( + .A(n_0_98), .ZN(aluOp[0]) + ); + OR2_X1_LVT i_0_327( + .A1(n_0_238), .A2(n_0_234), .ZN(n_0_223) + ); + NOR4_X1_LVT i_0_125( + .A1(Instruction[28]), .A2(Instruction[27]), .A3(Instruction[26]), .A4(Instruction[25]), + .ZN(n_0_103) + ); + INV_X1_LVT i_0_347( + .A(Instruction[30]), .ZN(n_0_242) + ); + NOR4_X1_LVT i_0_124( + .A1(Instruction[13]), .A2(n_0_242), .A3(Instruction[29]), .A4(Instruction[31]), + .ZN(n_0_102) + ); + NAND2_X1_LVT i_0_123( + .A1(n_0_103), .A2(n_0_102), .ZN(n_0_101) + ); + NOR3_X1_LVT i_0_127( + .A1(n_0_244), .A2(Instruction[12]), .A3(Instruction[14]), .ZN(n_0_105) + ); + AOI21_X1_LVT i_0_126( + .A(n_0_105), .B1(Instruction[12]), .B2(Instruction[14]), .ZN(n_0_104) + ); + NOR4_X1_LVT i_0_122( + .A1(n_0_223), .A2(n_0_101), .A3(n_0_104), .A4(Instruction[2]), .ZN(aluNegAr) + ); + OR3_X1_LVT i_0_325( + .A1(n_0_228), .A2(Instruction[4]), .A3(Instruction[6]), .ZN(n_0_222) + ); + NOR2_X1_LVT i_0_321( + .A1(n_0_222), .A2(Instruction[5]), .ZN(n_0_221) + ); + NOR3_X1_LVT i_0_224( + .A1(n_0_224), .A2(n_0_221), .A3(n_0_206), .ZN(n_0_169) + ); + NOR3_X1_LVT i_0_129( + .A1(n_0_234), .A2(Instruction[3]), .A3(Instruction[5]), .ZN(n_0_106) + ); + NOR3_X1_LVT i_0_128( + .A1(n_0_226), .A2(n_0_169), .A3(n_0_106), .ZN(aluBypass) + ); + AOI22_X1_LVT i_0_223( + .A1(CurrentPC[31]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[31]), .ZN(n_0_168) + ); + NOR3_X1_LVT i_0_219( + .A1(n_0_247), .A2(n_0_222), .A3(Instruction[5]), .ZN(n_0_164) + ); + AOI22_X1_LVT i_0_218( + .A1(RRs1[31]), .A2(n_0_169), .B1(n_0_164), .B2(RData[31]), .ZN(n_0_163) + ); + MUX2_X1_LVT i_0_222( + .A(RData[7]), .B(RData[15]), .S(Instruction[12]), .Z(n_0_167) + ); + NAND3_X1_LVT i_0_220( + .A1(n_0_221), .A2(n_0_167), .A3(n_0_166), .ZN(n_0_165) + ); + NAND3_X1_LVT i_0_217( + .A1(n_0_168), .A2(n_0_163), .A3(n_0_165), .ZN(op1[31]) + ); + AOI22_X1_LVT i_0_216( + .A1(RRs1[30]), .A2(n_0_169), .B1(n_0_164), .B2(RData[30]), .ZN(n_0_162) + ); + AOI22_X1_LVT i_0_215( + .A1(CurrentPC[30]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[30]), .ZN(n_0_161) + ); + NAND3_X1_LVT i_0_214( + .A1(n_0_162), .A2(n_0_161), .A3(n_0_165), .ZN(op1[30]) + ); + AOI22_X1_LVT i_0_213( + .A1(RRs1[29]), .A2(n_0_169), .B1(n_0_164), .B2(RData[29]), .ZN(n_0_160) + ); + AOI22_X1_LVT i_0_212( + .A1(CurrentPC[29]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[29]), .ZN(n_0_159) + ); + NAND3_X1_LVT i_0_211( + .A1(n_0_160), .A2(n_0_159), .A3(n_0_165), .ZN(op1[29]) + ); + AOI22_X1_LVT i_0_210( + .A1(RRs1[28]), .A2(n_0_169), .B1(n_0_164), .B2(RData[28]), .ZN(n_0_158) + ); + AOI22_X1_LVT i_0_209( + .A1(CurrentPC[28]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[28]), .ZN(n_0_157) + ); + NAND3_X1_LVT i_0_208( + .A1(n_0_158), .A2(n_0_157), .A3(n_0_165), .ZN(op1[28]) + ); + AOI22_X1_LVT i_0_207( + .A1(RRs1[27]), .A2(n_0_169), .B1(n_0_164), .B2(RData[27]), .ZN(n_0_156) + ); + AOI22_X1_LVT i_0_206( + .A1(CurrentPC[27]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[27]), .ZN(n_0_155) + ); + NAND3_X1_LVT i_0_205( + .A1(n_0_156), .A2(n_0_155), .A3(n_0_165), .ZN(op1[27]) + ); + AOI22_X1_LVT i_0_204( + .A1(RRs1[26]), .A2(n_0_169), .B1(n_0_164), .B2(RData[26]), .ZN(n_0_154) + ); + AOI22_X1_LVT i_0_203( + .A1(CurrentPC[26]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[26]), .ZN(n_0_153) + ); + NAND3_X1_LVT i_0_202( + .A1(n_0_154), .A2(n_0_153), .A3(n_0_165), .ZN(op1[26]) + ); + AOI22_X1_LVT i_0_201( + .A1(RRs1[25]), .A2(n_0_169), .B1(n_0_164), .B2(RData[25]), .ZN(n_0_152) + ); + AOI22_X1_LVT i_0_200( + .A1(CurrentPC[25]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[25]), .ZN(n_0_151) + ); + NAND3_X1_LVT i_0_199( + .A1(n_0_152), .A2(n_0_151), .A3(n_0_165), .ZN(op1[25]) + ); + AOI22_X1_LVT i_0_198( + .A1(RRs1[24]), .A2(n_0_169), .B1(n_0_164), .B2(RData[24]), .ZN(n_0_150) + ); + AOI22_X1_LVT i_0_197( + .A1(CurrentPC[24]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[24]), .ZN(n_0_149) + ); + NAND3_X1_LVT i_0_196( + .A1(n_0_150), .A2(n_0_149), .A3(n_0_165), .ZN(op1[24]) + ); + AOI22_X1_LVT i_0_195( + .A1(RRs1[23]), .A2(n_0_169), .B1(n_0_164), .B2(RData[23]), .ZN(n_0_148) + ); + AOI22_X1_LVT i_0_194( + .A1(CurrentPC[23]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[23]), .ZN(n_0_147) + ); + NAND3_X1_LVT i_0_193( + .A1(n_0_148), .A2(n_0_147), .A3(n_0_165), .ZN(op1[23]) + ); + AOI22_X1_LVT i_0_192( + .A1(RRs1[22]), .A2(n_0_169), .B1(n_0_164), .B2(RData[22]), .ZN(n_0_146) + ); + AOI22_X1_LVT i_0_191( + .A1(CurrentPC[22]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[22]), .ZN(n_0_145) + ); + NAND3_X1_LVT i_0_190( + .A1(n_0_146), .A2(n_0_145), .A3(n_0_165), .ZN(op1[22]) + ); + AOI22_X1_LVT i_0_189( + .A1(RRs1[21]), .A2(n_0_169), .B1(n_0_164), .B2(RData[21]), .ZN(n_0_144) + ); + AOI22_X1_LVT i_0_188( + .A1(CurrentPC[21]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[21]), .ZN(n_0_143) + ); + NAND3_X1_LVT i_0_187( + .A1(n_0_144), .A2(n_0_143), .A3(n_0_165), .ZN(op1[21]) + ); + AOI22_X1_LVT i_0_186( + .A1(RRs1[20]), .A2(n_0_169), .B1(n_0_164), .B2(RData[20]), .ZN(n_0_142) + ); + AOI22_X1_LVT i_0_185( + .A1(CurrentPC[20]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[20]), .ZN(n_0_141) + ); + NAND3_X1_LVT i_0_184( + .A1(n_0_142), .A2(n_0_141), .A3(n_0_165), .ZN(op1[20]) + ); + AOI22_X1_LVT i_0_183( + .A1(RRs1[19]), .A2(n_0_169), .B1(n_0_164), .B2(RData[19]), .ZN(n_0_140) + ); + AOI22_X1_LVT i_0_182( + .A1(CurrentPC[19]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[19]), .ZN(n_0_139) + ); + NAND3_X1_LVT i_0_181( + .A1(n_0_140), .A2(n_0_139), .A3(n_0_165), .ZN(op1[19]) + ); + AOI22_X1_LVT i_0_180( + .A1(RRs1[18]), .A2(n_0_169), .B1(n_0_164), .B2(RData[18]), .ZN(n_0_138) + ); + AOI22_X1_LVT i_0_179( + .A1(CurrentPC[18]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[18]), .ZN(n_0_137) + ); + NAND3_X1_LVT i_0_178( + .A1(n_0_138), .A2(n_0_137), .A3(n_0_165), .ZN(op1[18]) + ); + AOI22_X1_LVT i_0_177( + .A1(RRs1[17]), .A2(n_0_169), .B1(n_0_164), .B2(RData[17]), .ZN(n_0_136) + ); + AOI22_X1_LVT i_0_176( + .A1(CurrentPC[17]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[17]), .ZN(n_0_135) + ); + NAND3_X1_LVT i_0_175( + .A1(n_0_136), .A2(n_0_135), .A3(n_0_165), .ZN(op1[17]) + ); + AOI22_X1_LVT i_0_174( + .A1(RRs1[16]), .A2(n_0_169), .B1(n_0_164), .B2(RData[16]), .ZN(n_0_134) + ); + AOI22_X1_LVT i_0_173( + .A1(CurrentPC[16]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[16]), .ZN(n_0_133) + ); + NAND3_X1_LVT i_0_172( + .A1(n_0_134), .A2(n_0_133), .A3(n_0_165), .ZN(op1[16]) + ); + AOI222_X1_LVT i_0_169( + .A1(CurrentPC[15]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[15]), .C1(n_0_169), + .C2(RRs1[15]), .ZN(n_0_130) + ); + INV_X1_LVT i_0_353( + .A(Instruction[12]), .ZN(n_0_246) + ); + AOI211_X1_LVT i_0_171( + .A(Instruction[5]), .B(n_0_222), .C1(n_0_247), .C2(n_0_246), .ZN(n_0_132) + ); + OAI211_X1_LVT i_0_170( + .A(RData[15]), .B(n_0_132), .C1(Instruction[13]), .C2(Instruction[14]), .ZN(n_0_131) + ); + NAND3_X1_LVT i_0_168( + .A1(n_0_130), .A2(n_0_131), .A3(n_0_165), .ZN(op1[15]) + ); + AOI22_X1_LVT i_0_167( + .A1(RRs1[14]), .A2(n_0_169), .B1(n_0_132), .B2(RData[14]), .ZN(n_0_129) + ); + AOI22_X1_LVT i_0_166( + .A1(CurrentPC[14]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[14]), .ZN(n_0_128) + ); + NAND4_X1_LVT i_0_165( + .A1(n_0_221), .A2(n_0_246), .A3(RData[7]), .A4(n_0_166), .ZN(n_0_127) + ); + NAND3_X1_LVT i_0_164( + .A1(n_0_129), .A2(n_0_128), .A3(n_0_127), .ZN(op1[14]) + ); + AOI22_X1_LVT i_0_163( + .A1(RRs1[13]), .A2(n_0_169), .B1(n_0_132), .B2(RData[13]), .ZN(n_0_126) + ); + AOI22_X1_LVT i_0_162( + .A1(CurrentPC[13]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[13]), .ZN(n_0_125) + ); + NAND3_X1_LVT i_0_161( + .A1(n_0_126), .A2(n_0_125), .A3(n_0_127), .ZN(op1[13]) + ); + AOI22_X1_LVT i_0_160( + .A1(RRs1[12]), .A2(n_0_169), .B1(n_0_132), .B2(RData[12]), .ZN(n_0_124) + ); + AOI22_X1_LVT i_0_159( + .A1(CurrentPC[12]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[12]), .ZN(n_0_123) + ); + NAND3_X1_LVT i_0_158( + .A1(n_0_124), .A2(n_0_123), .A3(n_0_127), .ZN(op1[12]) + ); + AOI22_X1_LVT i_0_156( + .A1(CurrentPC[11]), .A2(n_0_224), .B1(n_0_132), .B2(RData[11]), .ZN(n_0_121) + ); + NAND2_X1_LVT i_0_157( + .A1(RRs1[11]), .A2(n_0_169), .ZN(n_0_122) + ); + NAND3_X1_LVT i_0_155( + .A1(n_0_121), .A2(n_0_122), .A3(n_0_127), .ZN(op1[11]) + ); + AOI22_X1_LVT i_0_153( + .A1(CurrentPC[10]), .A2(n_0_224), .B1(n_0_132), .B2(RData[10]), .ZN(n_0_119) + ); + NAND2_X1_LVT i_0_154( + .A1(RRs1[10]), .A2(n_0_169), .ZN(n_0_120) + ); + NAND3_X1_LVT i_0_152( + .A1(n_0_119), .A2(n_0_120), .A3(n_0_127), .ZN(op1[10]) + ); + AOI22_X1_LVT i_0_150( + .A1(CurrentPC[9]), .A2(n_0_224), .B1(n_0_132), .B2(RData[9]), .ZN(n_0_117) + ); + NAND2_X1_LVT i_0_151( + .A1(RRs1[9]), .A2(n_0_169), .ZN(n_0_118) + ); + NAND3_X1_LVT i_0_149( + .A1(n_0_117), .A2(n_0_118), .A3(n_0_127), .ZN(op1[9]) + ); + AOI22_X1_LVT i_0_147( + .A1(CurrentPC[8]), .A2(n_0_224), .B1(n_0_132), .B2(RData[8]), .ZN(n_0_115) + ); + NAND2_X1_LVT i_0_148( + .A1(RRs1[8]), .A2(n_0_169), .ZN(n_0_116) + ); + NAND3_X1_LVT i_0_146( + .A1(n_0_115), .A2(n_0_116), .A3(n_0_127), .ZN(op1[8]) + ); + AOI222_X1_LVT i_0_145( + .A1(CurrentPC[7]), .A2(n_0_224), .B1(n_0_221), .B2(RData[7]), .C1(n_0_169), + .C2(RRs1[7]), .ZN(n_0_114) + ); + INV_X1_LVT i_0_144( + .A(n_0_114), .ZN(op1[7]) + ); + AOI222_X1_LVT i_0_143( + .A1(CurrentPC[6]), .A2(n_0_224), .B1(n_0_221), .B2(RData[6]), .C1(n_0_169), + .C2(RRs1[6]), .ZN(n_0_113) + ); + INV_X1_LVT i_0_142( + .A(n_0_113), .ZN(op1[6]) + ); + AOI222_X1_LVT i_0_141( + .A1(CurrentPC[5]), .A2(n_0_224), .B1(n_0_221), .B2(RData[5]), .C1(n_0_169), + .C2(RRs1[5]), .ZN(n_0_112) + ); + INV_X1_LVT i_0_140( + .A(n_0_112), .ZN(op1[5]) + ); + AOI222_X1_LVT i_0_139( + .A1(CurrentPC[4]), .A2(n_0_224), .B1(n_0_221), .B2(RData[4]), .C1(n_0_169), + .C2(RRs1[4]), .ZN(n_0_111) + ); + INV_X1_LVT i_0_138( + .A(n_0_111), .ZN(op1[4]) + ); + AOI222_X1_LVT i_0_137( + .A1(CurrentPC[3]), .A2(n_0_224), .B1(n_0_221), .B2(RData[3]), .C1(n_0_169), + .C2(RRs1[3]), .ZN(n_0_110) + ); + INV_X1_LVT i_0_136( + .A(n_0_110), .ZN(op1[3]) + ); + AOI222_X1_LVT i_0_135( + .A1(CurrentPC[2]), .A2(n_0_224), .B1(n_0_221), .B2(RData[2]), .C1(n_0_169), + .C2(RRs1[2]), .ZN(n_0_109) + ); + INV_X1_LVT i_0_134( + .A(n_0_109), .ZN(op1[2]) + ); + AOI222_X1_LVT i_0_133( + .A1(CurrentPC[1]), .A2(n_0_224), .B1(n_0_221), .B2(RData[1]), .C1(n_0_169), + .C2(RRs1[1]), .ZN(n_0_108) + ); + INV_X1_LVT i_0_132( + .A(n_0_108), .ZN(op1[1]) + ); + AOI222_X1_LVT i_0_131( + .A1(CurrentPC[0]), .A2(n_0_224), .B1(n_0_221), .B2(RData[0]), .C1(n_0_169), + .C2(RRs1[0]), .ZN(n_0_107) + ); + INV_X1_LVT i_0_130( + .A(n_0_107), .ZN(op1[0]) + ); + NOR3_X1_LVT i_0_294( + .A1(n_0_223), .A2(Instruction[2]), .A3(Instruction[5]), .ZN(n_0_207) + ); + NOR3_X1_LVT i_0_291( + .A1(n_0_224), .A2(n_0_207), .A3(n_0_205), .ZN(n_0_204) + ); + AOI22_X1_LVT i_0_289( + .A1(CurrentPC[31]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[31]), .ZN(n_0_202) + ); + NAND2_X1_LVT i_0_290( + .A1(Instruction[31]), .A2(n_0_207), .ZN(n_0_203) + ); + NAND2_X1_LVT i_0_288( + .A1(n_0_202), .A2(n_0_203), .ZN(op2[31]) + ); + AOI22_X1_LVT i_0_287( + .A1(CurrentPC[30]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[30]), .ZN(n_0_201) + ); + NAND2_X1_LVT i_0_286( + .A1(n_0_201), .A2(n_0_203), .ZN(op2[30]) + ); + AOI22_X1_LVT i_0_285( + .A1(CurrentPC[29]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[29]), .ZN(n_0_200) + ); + NAND2_X1_LVT i_0_284( + .A1(n_0_200), .A2(n_0_203), .ZN(op2[29]) + ); + AOI22_X1_LVT i_0_283( + .A1(CurrentPC[28]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[28]), .ZN(n_0_199) + ); + NAND2_X1_LVT i_0_282( + .A1(n_0_199), .A2(n_0_203), .ZN(op2[28]) + ); + AOI22_X1_LVT i_0_281( + .A1(CurrentPC[27]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[27]), .ZN(n_0_198) + ); + NAND2_X1_LVT i_0_280( + .A1(n_0_198), .A2(n_0_203), .ZN(op2[27]) + ); + AOI22_X1_LVT i_0_279( + .A1(CurrentPC[26]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[26]), .ZN(n_0_197) + ); + NAND2_X1_LVT i_0_278( + .A1(n_0_197), .A2(n_0_203), .ZN(op2[26]) + ); + AOI22_X1_LVT i_0_277( + .A1(CurrentPC[25]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[25]), .ZN(n_0_196) + ); + NAND2_X1_LVT i_0_276( + .A1(n_0_196), .A2(n_0_203), .ZN(op2[25]) + ); + AOI22_X1_LVT i_0_275( + .A1(CurrentPC[24]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[24]), .ZN(n_0_195) + ); + NAND2_X1_LVT i_0_274( + .A1(n_0_195), .A2(n_0_203), .ZN(op2[24]) + ); + AOI22_X1_LVT i_0_273( + .A1(CurrentPC[23]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[23]), .ZN(n_0_194) + ); + NAND2_X1_LVT i_0_272( + .A1(n_0_194), .A2(n_0_203), .ZN(op2[23]) + ); + AOI22_X1_LVT i_0_271( + .A1(CurrentPC[22]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[22]), .ZN(n_0_193) + ); + NAND2_X1_LVT i_0_270( + .A1(n_0_193), .A2(n_0_203), .ZN(op2[22]) + ); + AOI22_X1_LVT i_0_269( + .A1(CurrentPC[21]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[21]), .ZN(n_0_192) + ); + NAND2_X1_LVT i_0_268( + .A1(n_0_192), .A2(n_0_203), .ZN(op2[21]) + ); + AOI22_X1_LVT i_0_267( + .A1(CurrentPC[20]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[20]), .ZN(n_0_191) + ); + NAND2_X1_LVT i_0_266( + .A1(n_0_191), .A2(n_0_203), .ZN(op2[20]) + ); + AOI22_X1_LVT i_0_265( + .A1(CurrentPC[19]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[19]), .ZN(n_0_190) + ); + NAND2_X1_LVT i_0_264( + .A1(n_0_190), .A2(n_0_203), .ZN(op2[19]) + ); + AOI22_X1_LVT i_0_263( + .A1(CurrentPC[18]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[18]), .ZN(n_0_189) + ); + NAND2_X1_LVT i_0_262( + .A1(n_0_189), .A2(n_0_203), .ZN(op2[18]) + ); + AOI22_X1_LVT i_0_261( + .A1(CurrentPC[17]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[17]), .ZN(n_0_188) + ); + NAND2_X1_LVT i_0_260( + .A1(n_0_188), .A2(n_0_203), .ZN(op2[17]) + ); + AOI22_X1_LVT i_0_259( + .A1(CurrentPC[16]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[16]), .ZN(n_0_187) + ); + NAND2_X1_LVT i_0_258( + .A1(n_0_187), .A2(n_0_203), .ZN(op2[16]) + ); + AOI22_X1_LVT i_0_257( + .A1(CurrentPC[15]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[15]), .ZN(n_0_186) + ); + NAND2_X1_LVT i_0_256( + .A1(n_0_186), .A2(n_0_203), .ZN(op2[15]) + ); + AOI22_X1_LVT i_0_255( + .A1(CurrentPC[14]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[14]), .ZN(n_0_185) + ); + NAND2_X1_LVT i_0_254( + .A1(n_0_185), .A2(n_0_203), .ZN(op2[14]) + ); + AOI22_X1_LVT i_0_253( + .A1(CurrentPC[13]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[13]), .ZN(n_0_184) + ); + NAND2_X1_LVT i_0_252( + .A1(n_0_184), .A2(n_0_203), .ZN(op2[13]) + ); + AOI22_X1_LVT i_0_251( + .A1(CurrentPC[12]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[12]), .ZN(n_0_183) + ); + NAND2_X1_LVT i_0_250( + .A1(n_0_183), .A2(n_0_203), .ZN(op2[12]) + ); + AOI22_X1_LVT i_0_249( + .A1(CurrentPC[11]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[11]), .ZN(n_0_182) + ); + NAND2_X1_LVT i_0_248( + .A1(n_0_182), .A2(n_0_203), .ZN(op2[11]) + ); + AOI222_X1_LVT i_0_247( + .A1(Instruction[30]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[10]), .C1(n_0_204), + .C2(RRs2[10]), .ZN(n_0_181) + ); + INV_X1_LVT i_0_246( + .A(n_0_181), .ZN(op2[10]) + ); + AOI222_X1_LVT i_0_245( + .A1(Instruction[29]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[9]), .C1(n_0_204), + .C2(RRs2[9]), .ZN(n_0_180) + ); + INV_X1_LVT i_0_244( + .A(n_0_180), .ZN(op2[9]) + ); + AOI222_X1_LVT i_0_243( + .A1(Instruction[28]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[8]), .C1(n_0_204), + .C2(RRs2[8]), .ZN(n_0_179) + ); + INV_X1_LVT i_0_242( + .A(n_0_179), .ZN(op2[8]) + ); + AOI222_X1_LVT i_0_241( + .A1(Instruction[27]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[7]), .C1(n_0_204), + .C2(RRs2[7]), .ZN(n_0_178) + ); + INV_X1_LVT i_0_240( + .A(n_0_178), .ZN(op2[7]) + ); + AOI222_X1_LVT i_0_239( + .A1(Instruction[26]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[6]), .C1(n_0_204), + .C2(RRs2[6]), .ZN(n_0_177) + ); + INV_X1_LVT i_0_238( + .A(n_0_177), .ZN(op2[6]) + ); + AOI222_X1_LVT i_0_237( + .A1(Instruction[25]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[5]), .C1(n_0_204), + .C2(RRs2[5]), .ZN(n_0_176) + ); + INV_X1_LVT i_0_236( + .A(n_0_176), .ZN(op2[5]) + ); + AOI222_X1_LVT i_0_235( + .A1(Instruction[24]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[4]), .C1(n_0_204), + .C2(RRs2[4]), .ZN(n_0_175) + ); + INV_X1_LVT i_0_234( + .A(n_0_175), .ZN(op2[4]) + ); + AOI222_X1_LVT i_0_233( + .A1(Instruction[23]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[3]), .C1(n_0_204), + .C2(RRs2[3]), .ZN(n_0_174) + ); + INV_X1_LVT i_0_232( + .A(n_0_174), .ZN(op2[3]) + ); + AOI22_X1_LVT i_0_230( + .A1(Instruction[22]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[2]), .ZN(n_0_172) + ); + OAI21_X1_LVT i_0_231( + .A(RRs2[2]), .B1(n_0_223), .B2(Instruction[5]), .ZN(n_0_173) + ); + NAND3_X1_LVT i_0_229( + .A1(n_0_172), .A2(n_0_173), .A3(n_0_249), .ZN(op2[2]) + ); + AOI222_X1_LVT i_0_228( + .A1(Instruction[21]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[1]), .C1(n_0_204), + .C2(RRs2[1]), .ZN(n_0_171) + ); + INV_X1_LVT i_0_227( + .A(n_0_171), .ZN(op2[1]) + ); + AOI222_X1_LVT i_0_226( + .A1(Instruction[20]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[0]), .C1(n_0_204), + .C2(RRs2[0]), .ZN(n_0_170) + ); + INV_X1_LVT i_0_225( + .A(n_0_170), .ZN(op2[0]) + ); + alu theALU( + .aluOp(aluOp), .aluNegAr(aluNegAr), .aluBypass(aluBypass), .op1(op1), .op2(op2), + .result(WRd), .eqFlag(eqFlag) + ); + XNOR2_X1_LVT i_0_115( + .A(Instruction[12]), .B(eqFlag), .ZN(n_0_97) + ); + XNOR2_X1_LVT i_0_114( + .A(Instruction[12]), .B(WRd[0]), .ZN(n_0_96) + ); + AOI22_X1_LVT i_0_113( + .A1(n_0_166), .A2(n_0_97), .B1(n_0_96), .B2(Instruction[14]), .ZN(n_0_95) + ); + AOI22_X1_LVT i_0_111( + .A1(Instruction[6]), .A2(n_0_95), .B1(Instruction[2]), .B2(n_0_245), .ZN(n_0_93) + ); + NAND2_X1_LVT i_0_110( + .A1(n_0_94), .A2(n_0_93), .ZN(JumpOrBranch) + ); + INV_X1_LVT i_0_349( + .A(Instruction[31]), .ZN(n_0_0) + ); + INV_X1_LVT i_0_348( + .A(RRs1[12]), .ZN(n_0_1) + ); + HA_X1_LVT i_0_0( + .A(Instruction[7]), .B(RRs1[0]), .CO(n_0_2), .S(n_0_15) + ); + FA_X1_LVT i_0_1( + .A(Instruction[8]), .B(RRs1[1]), .CI(n_0_2), .CO(n_0_3), .S(n_0_16) + ); + FA_X1_LVT i_0_2( + .A(Instruction[9]), .B(RRs1[2]), .CI(n_0_3), .CO(n_0_4), .S(n_0_17) + ); + FA_X1_LVT i_0_3( + .A(Instruction[10]), .B(RRs1[3]), .CI(n_0_4), .CO(n_0_5), .S(n_0_18) + ); + FA_X1_LVT i_0_4( + .A(Instruction[11]), .B(RRs1[4]), .CI(n_0_5), .CO(n_0_6), .S(n_0_19) + ); + FA_X1_LVT i_0_5( + .A(Instruction[25]), .B(RRs1[5]), .CI(n_0_6), .CO(n_0_7), .S(n_0_20) + ); + FA_X1_LVT i_0_6( + .A(Instruction[26]), .B(RRs1[6]), .CI(n_0_7), .CO(n_0_8), .S(n_0_21) + ); + FA_X1_LVT i_0_7( + .A(Instruction[27]), .B(RRs1[7]), .CI(n_0_8), .CO(n_0_9), .S(n_0_22) + ); + FA_X1_LVT i_0_8( + .A(Instruction[28]), .B(RRs1[8]), .CI(n_0_9), .CO(n_0_10), .S(n_0_23) + ); + FA_X1_LVT i_0_9( + .A(Instruction[29]), .B(RRs1[9]), .CI(n_0_10), .CO(n_0_11), .S(n_0_24) + ); + FA_X1_LVT i_0_10( + .A(Instruction[30]), .B(RRs1[10]), .CI(n_0_11), .CO(n_0_12), .S(n_0_25) + ); + FA_X1_LVT i_0_11( + .A(RRs1[11]), .B(Instruction[31]), .CI(n_0_12), .CO(n_0_13), .S(n_0_26) + ); + FA_X1_LVT i_0_12( + .A(n_0_0), .B(n_0_1), .CI(n_0_13), .CO(n_0_14), .S(n_0_27) + ); + NOR2_X1_LVT i_0_322( + .A1(n_0_244), .A2(n_0_222), .ZN(WrMem) + ); + AOI22_X1_LVT i_0_320( + .A1(n_0_27), .A2(WrMem), .B1(n_0_221), .B2(n_12), .ZN(n_0_220) + ); + INV_X1_LVT i_0_319( + .A(n_0_220), .ZN(DAddr[12]) + ); + AOI22_X1_LVT i_0_318( + .A1(n_0_26), .A2(WrMem), .B1(n_0_221), .B2(n_11), .ZN(n_0_219) + ); + INV_X1_LVT i_0_317( + .A(n_0_219), .ZN(DAddr[11]) + ); + AOI22_X1_LVT i_0_316( + .A1(n_0_25), .A2(WrMem), .B1(n_0_221), .B2(n_10), .ZN(n_0_218) + ); + INV_X1_LVT i_0_315( + .A(n_0_218), .ZN(DAddr[10]) + ); + AOI22_X1_LVT i_0_314( + .A1(n_0_24), .A2(WrMem), .B1(n_0_221), .B2(n_9), .ZN(n_0_217) + ); + INV_X1_LVT i_0_313( + .A(n_0_217), .ZN(DAddr[9]) + ); + AOI22_X1_LVT i_0_312( + .A1(n_0_23), .A2(WrMem), .B1(n_0_221), .B2(n_8), .ZN(n_0_216) + ); + INV_X1_LVT i_0_311( + .A(n_0_216), .ZN(DAddr[8]) + ); + AOI22_X1_LVT i_0_310( + .A1(n_0_22), .A2(WrMem), .B1(n_0_221), .B2(n_7), .ZN(n_0_215) + ); + INV_X1_LVT i_0_309( + .A(n_0_215), .ZN(DAddr[7]) + ); + AOI22_X1_LVT i_0_308( + .A1(n_0_21), .A2(WrMem), .B1(n_0_221), .B2(n_6), .ZN(n_0_214) + ); + INV_X1_LVT i_0_307( + .A(n_0_214), .ZN(DAddr[6]) + ); + AOI22_X1_LVT i_0_306( + .A1(n_0_20), .A2(WrMem), .B1(n_0_221), .B2(n_5), .ZN(n_0_213) + ); + INV_X1_LVT i_0_305( + .A(n_0_213), .ZN(DAddr[5]) + ); + AOI22_X1_LVT i_0_304( + .A1(n_0_19), .A2(WrMem), .B1(n_0_221), .B2(n_4), .ZN(n_0_212) + ); + INV_X1_LVT i_0_303( + .A(n_0_212), .ZN(DAddr[4]) + ); + AOI22_X1_LVT i_0_302( + .A1(n_0_18), .A2(WrMem), .B1(n_0_221), .B2(n_3), .ZN(n_0_211) + ); + INV_X1_LVT i_0_301( + .A(n_0_211), .ZN(DAddr[3]) + ); + AOI22_X1_LVT i_0_300( + .A1(n_0_17), .A2(WrMem), .B1(n_0_221), .B2(n_2), .ZN(n_0_210) + ); + INV_X1_LVT i_0_299( + .A(n_0_210), .ZN(DAddr[2]) + ); + AOI22_X1_LVT i_0_298( + .A1(n_0_16), .A2(WrMem), .B1(n_0_221), .B2(n_1), .ZN(n_0_209) + ); + INV_X1_LVT i_0_297( + .A(n_0_209), .ZN(DAddr[1]) + ); + AOI22_X1_LVT i_0_296( + .A1(n_0_15), .A2(WrMem), .B1(n_0_221), .B2(n_0), .ZN(n_0_208) + ); + INV_X1_LVT i_0_295( + .A(n_0_208), .ZN(DAddr[0]) + ); + OR2_X1_LVT i_0_324( + .A1(n_0_222), .A2(Instruction[13]), .ZN(DWidth[1]) + ); + NOR2_X1_LVT i_0_323( + .A1(n_0_246), .A2(n_0_222), .ZN(DWidth[0]) + ); + NAND3_X1_LVT i_0_331( + .A1(n_0_248), .A2(n_0_244), .A3(n_0_236), .ZN(n_0_227) + ); + OAI211_X1_LVT i_0_326( + .A(n_0_249), .B(n_0_223), .C1(n_0_228), .C2(n_0_227), .ZN(WrReg) + ); +endmodule + +module MemGen_32_11(chip_en, clock, addr, rd_data, rd_en, wr_en, wr_data); + input [31:0] wr_data; + input [10:0] addr; + input chip_en, clock, rd_en, wr_en; + output [31:0] rd_data; + + wire [1:0] mem_sel; + wire n_63, n_62, n_61, n_60, n_59, n_58, n_57, n_56, n_55, n_54, n_53, n_52, + n_51, n_50, n_49, n_48, n_31, n_30, n_29, n_28, n_27, n_26, n_25, n_24, + n_23, n_22, n_21, n_20, n_19, n_18, n_17, n_16, n_47, n_46, n_45, n_44, + n_43, n_42, n_41, n_40, n_39, n_38, n_37, n_36, n_35, n_34, n_33, n_32, + n_15, n_14, n_13, n_12, n_11, n_10, n_9, n_8, n_7, n_6, n_5, n_4, n_3, + n_2, n_1, n_0; + + INV_X1_LVT i_1_3( + .A(addr[10]), .ZN(mem_sel[0]) + ); + MemGen_16_10 genblk1_0_U_hi( + .chip_en(mem_sel[0]), .wr_en(wr_en), .addr({addr[9], addr[8], addr[7], + addr[6], addr[5], addr[4], addr[3], addr[2], addr[1], addr[0]}), .wr_data({ + wr_data[31], wr_data[30], wr_data[29], wr_data[28], wr_data[27], + wr_data[26], wr_data[25], wr_data[24], wr_data[23], wr_data[22], + wr_data[21], wr_data[20], wr_data[19], wr_data[18], wr_data[17], + wr_data[16]}), .clock(clock), .rd_en(rd_en), .rd_data({n_63, n_62, n_61, + n_60, n_59, n_58, n_57, n_56, n_55, n_54, n_53, n_52, n_51, n_50, n_49, + n_48}) + ); + MemGen_16_10 genblk1_1_U_hi( + .chip_en(addr[10]), .wr_en(wr_en), .addr({addr[9], addr[8], addr[7], + addr[6], addr[5], addr[4], addr[3], addr[2], addr[1], addr[0]}), .wr_data({ + wr_data[31], wr_data[30], wr_data[29], wr_data[28], wr_data[27], + wr_data[26], wr_data[25], wr_data[24], wr_data[23], wr_data[22], + wr_data[21], wr_data[20], wr_data[19], wr_data[18], wr_data[17], + wr_data[16]}), .clock(clock), .rd_en(rd_en), .rd_data({n_31, n_30, n_29, + n_28, n_27, n_26, n_25, n_24, n_23, n_22, n_21, n_20, n_19, n_18, n_17, + n_16}) + ); + MUX2_X1_LVT i_1_1_31( + .A(n_63), .B(n_31), .S(addr[10]), .Z(rd_data[31]) + ); + MUX2_X1_LVT i_1_1_30( + .A(n_62), .B(n_30), .S(addr[10]), .Z(rd_data[30]) + ); + MUX2_X1_LVT i_1_1_29( + .A(n_61), .B(n_29), .S(addr[10]), .Z(rd_data[29]) + ); + MUX2_X1_LVT i_1_1_28( + .A(n_60), .B(n_28), .S(addr[10]), .Z(rd_data[28]) + ); + MUX2_X1_LVT i_1_1_27( + .A(n_59), .B(n_27), .S(addr[10]), .Z(rd_data[27]) + ); + MUX2_X1_LVT i_1_1_26( + .A(n_58), .B(n_26), .S(addr[10]), .Z(rd_data[26]) + ); + MUX2_X1_LVT i_1_1_25( + .A(n_57), .B(n_25), .S(addr[10]), .Z(rd_data[25]) + ); + MUX2_X1_LVT i_1_1_24( + .A(n_56), .B(n_24), .S(addr[10]), .Z(rd_data[24]) + ); + MUX2_X1_LVT i_1_1_23( + .A(n_55), .B(n_23), .S(addr[10]), .Z(rd_data[23]) + ); + MUX2_X1_LVT i_1_1_22( + .A(n_54), .B(n_22), .S(addr[10]), .Z(rd_data[22]) + ); + MUX2_X1_LVT i_1_1_21( + .A(n_53), .B(n_21), .S(addr[10]), .Z(rd_data[21]) + ); + MUX2_X1_LVT i_1_1_20( + .A(n_52), .B(n_20), .S(addr[10]), .Z(rd_data[20]) + ); + MUX2_X1_LVT i_1_1_19( + .A(n_51), .B(n_19), .S(addr[10]), .Z(rd_data[19]) + ); + MUX2_X1_LVT i_1_1_18( + .A(n_50), .B(n_18), .S(addr[10]), .Z(rd_data[18]) + ); + MUX2_X1_LVT i_1_1_17( + .A(n_49), .B(n_17), .S(addr[10]), .Z(rd_data[17]) + ); + MUX2_X1_LVT i_1_1_16( + .A(n_48), .B(n_16), .S(addr[10]), .Z(rd_data[16]) + ); + MemGen_16_10 genblk1_0_U_lo( + .chip_en(mem_sel[0]), .wr_en(wr_en), .addr({addr[9], addr[8], addr[7], + addr[6], addr[5], addr[4], addr[3], addr[2], addr[1], addr[0]}), .wr_data({ + wr_data[15], wr_data[14], wr_data[13], wr_data[12], wr_data[11], + wr_data[10], wr_data[9], wr_data[8], wr_data[7], wr_data[6], wr_data[5], + wr_data[4], wr_data[3], wr_data[2], wr_data[1], wr_data[0]}), .clock(clock), + .rd_en(rd_en), .rd_data({n_47, n_46, n_45, n_44, n_43, n_42, n_41, + n_40, n_39, n_38, n_37, n_36, n_35, n_34, n_33, n_32}) + ); + MemGen_16_10 genblk1_1_U_lo( + .chip_en(addr[10]), .wr_en(wr_en), .addr({addr[9], addr[8], addr[7], + addr[6], addr[5], addr[4], addr[3], addr[2], addr[1], addr[0]}), .wr_data({ + wr_data[15], wr_data[14], wr_data[13], wr_data[12], wr_data[11], + wr_data[10], wr_data[9], wr_data[8], wr_data[7], wr_data[6], wr_data[5], + wr_data[4], wr_data[3], wr_data[2], wr_data[1], wr_data[0]}), .clock(clock), + .rd_en(rd_en), .rd_data({n_15, n_14, n_13, n_12, n_11, n_10, n_9, n_8, + n_7, n_6, n_5, n_4, n_3, n_2, n_1, n_0}) + ); + MUX2_X1_LVT i_1_1_15( + .A(n_47), .B(n_15), .S(addr[10]), .Z(rd_data[15]) + ); + MUX2_X1_LVT i_1_1_14( + .A(n_46), .B(n_14), .S(addr[10]), .Z(rd_data[14]) + ); + MUX2_X1_LVT i_1_1_13( + .A(n_45), .B(n_13), .S(addr[10]), .Z(rd_data[13]) + ); + MUX2_X1_LVT i_1_1_12( + .A(n_44), .B(n_12), .S(addr[10]), .Z(rd_data[12]) + ); + MUX2_X1_LVT i_1_1_11( + .A(n_43), .B(n_11), .S(addr[10]), .Z(rd_data[11]) + ); + MUX2_X1_LVT i_1_1_10( + .A(n_42), .B(n_10), .S(addr[10]), .Z(rd_data[10]) + ); + MUX2_X1_LVT i_1_1_9( + .A(n_41), .B(n_9), .S(addr[10]), .Z(rd_data[9]) + ); + MUX2_X1_LVT i_1_1_8( + .A(n_40), .B(n_8), .S(addr[10]), .Z(rd_data[8]) + ); + MUX2_X1_LVT i_1_1_7( + .A(n_39), .B(n_7), .S(addr[10]), .Z(rd_data[7]) + ); + MUX2_X1_LVT i_1_1_6( + .A(n_38), .B(n_6), .S(addr[10]), .Z(rd_data[6]) + ); + MUX2_X1_LVT i_1_1_5( + .A(n_37), .B(n_5), .S(addr[10]), .Z(rd_data[5]) + ); + MUX2_X1_LVT i_1_1_4( + .A(n_36), .B(n_4), .S(addr[10]), .Z(rd_data[4]) + ); + MUX2_X1_LVT i_1_1_3( + .A(n_35), .B(n_3), .S(addr[10]), .Z(rd_data[3]) + ); + MUX2_X1_LVT i_1_1_2( + .A(n_34), .B(n_2), .S(addr[10]), .Z(rd_data[2]) + ); + MUX2_X1_LVT i_1_1_1( + .A(n_33), .B(n_1), .S(addr[10]), .Z(rd_data[1]) + ); + MUX2_X1_LVT i_1_1_0( + .A(n_32), .B(n_0), .S(addr[10]), .Z(rd_data[0]) + ); +endmodule + +module main_mem(clk, reset, DAddr, IAddr, DWData, DRData, IRData, DWE, DWidth); + input [31:0] DAddr, IAddr, DWData; + input [1:0] DWidth; + input clk, reset, DWE; + output [31:0] DRData, IRData; + + wire [31:0] mem_rdata, drTmp, mem_wdata; + wire [10:0] mem_addr; + wire n_0_0, n_0_0_0, n_0_1, n_0_0_1, n_0_2, n_0_0_2, n_0_3, n_0_0_3, n_0_4, + n_0_0_4, n_0_5, n_0_0_5, n_0_6, n_0_0_6, n_0_7, n_0_0_7, n_0_8, n_0_0_8, + n_0_9, n_0_0_9, n_0_10, n_0_0_10, n_0_0_11, n_0_11, n_0_0_12, n_0_0_13, + n_0_12, n_0_0_14, n_0_0_15, n_0_13, n_0_0_16, n_0_0_17, n_0_14, + n_0_0_18, n_0_0_19, n_0_15, n_0_0_20, n_0_0_21, n_0_16, n_0_0_22, + n_0_0_23, n_0_17, n_0_0_24, n_0_0_25, n_0_18, n_0_0_26, n_0_0_27, + n_0_0_28, n_0_19, n_0_0_29, n_0_20, n_0_0_30, n_0_21, n_0_0_31, n_0_22, + n_0_0_32, n_0_23, n_0_0_33, n_0_24, n_0_0_34, n_0_25, n_0_0_35, n_0_26, + n_0_0_36, n_0_0_37, n_0_27, n_0_28, n_0_29, n_0_30, n_0_31, n_0_32, + n_0_33, n_0_34, n_0_35, n_0_36, n_0_37, n_0_38, n_0_39, n_0_40, n_0_41, + n_0_42, n_0_65, n_0_64, n_0_63, n_0_62, n_0_61, n_0_60, n_0_59, n_0_58, + n_0_0_38, n_0_0_39, n_0_57, n_0_0_40, n_0_56, n_0_0_41, n_0_55, + n_0_0_42, n_0_54, n_0_0_43, n_0_53, n_0_0_44, n_0_52, n_0_0_45, n_0_51, + n_0_0_46, n_0_50, n_0_0_47, n_0_0_48, n_0_0_49, n_0_0_50, n_0_0_51, + n_0_49, n_0_0_52, n_0_48, n_0_0_53, n_0_47, n_0_0_54, n_0_46, n_0_0_55, + n_0_45, n_0_0_56, n_0_44, n_0_0_57, n_0_66, n_0_0_58, n_0_67, n_0_0_59, + n_0_0_60, n_0_0_61, n_0_68, n_0_0_62, n_0_0_63, n_0_69, n_0_0_64, + n_0_0_65, n_0_70, n_0_0_66, n_0_0_67, n_0_71, n_0_0_68, n_0_0_69, + n_0_72, n_0_0_70, n_0_0_71, n_0_73, n_0_0_72, n_0_0_73, n_0_74, + n_0_0_74, n_0_0_75, n_0_75, n_0_0_76, n_0_0_77, n_0_0_78, n_0_0_79, + n_0_0_80, n_0_0_81, n_0_0_82, n_0_0_83, n_0_0_84, n_0_0_85, n_0_0_86, + n_0_0_87, n_0_0_88, n_0_0_89, n_0_0_90, n_0_0_91, n_0_0_92, n_0_43, + n_0_0_93, n_0_0_94, n_0_76, n_0_0_95, n_0; + + INV_X1_LVT i_0_0_171( + .A(DWE), .ZN(n_0) + ); + NOR2_X1_LVT i_0_0_163( + .A1(n_0), .A2(reset), .ZN(n_0_0_88) + ); + NOR2_X1_LVT i_0_0_22( + .A1(DWE), .A2(reset), .ZN(n_0_0_11) + ); + AOI22_X1_LVT i_0_0_21( + .A1(DAddr[12]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[12]), .ZN(n_0_0_10) + ); + INV_X1_LVT i_0_0_20( + .A(n_0_0_10), .ZN(n_0_10) + ); + INV_X1_LVT i_0_0_172( + .A(clk), .ZN(n_0_76) + ); + DFF_X1_LVT \mem_addr_reg[10] ( + .CK(n_0_76), .D(n_0_10), .Q(mem_addr[10]), .QN() + ); + AOI22_X1_LVT i_0_0_19( + .A1(DAddr[11]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[11]), .ZN(n_0_0_9) + ); + INV_X1_LVT i_0_0_18( + .A(n_0_0_9), .ZN(n_0_9) + ); + DFF_X1_LVT \mem_addr_reg[9] ( + .CK(n_0_76), .D(n_0_9), .Q(mem_addr[9]), .QN() + ); + AOI22_X1_LVT i_0_0_17( + .A1(DAddr[10]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[10]), .ZN(n_0_0_8) + ); + INV_X1_LVT i_0_0_16( + .A(n_0_0_8), .ZN(n_0_8) + ); + DFF_X1_LVT \mem_addr_reg[8] ( + .CK(n_0_76), .D(n_0_8), .Q(mem_addr[8]), .QN() + ); + AOI22_X1_LVT i_0_0_15( + .A1(DAddr[9]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[9]), .ZN(n_0_0_7) + ); + INV_X1_LVT i_0_0_14( + .A(n_0_0_7), .ZN(n_0_7) + ); + DFF_X1_LVT \mem_addr_reg[7] ( + .CK(n_0_76), .D(n_0_7), .Q(mem_addr[7]), .QN() + ); + AOI22_X1_LVT i_0_0_13( + .A1(DAddr[8]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[8]), .ZN(n_0_0_6) + ); + INV_X1_LVT i_0_0_12( + .A(n_0_0_6), .ZN(n_0_6) + ); + DFF_X1_LVT \mem_addr_reg[6] ( + .CK(n_0_76), .D(n_0_6), .Q(mem_addr[6]), .QN() + ); + AOI22_X1_LVT i_0_0_11( + .A1(DAddr[7]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[7]), .ZN(n_0_0_5) + ); + INV_X1_LVT i_0_0_10( + .A(n_0_0_5), .ZN(n_0_5) + ); + DFF_X1_LVT \mem_addr_reg[5] ( + .CK(n_0_76), .D(n_0_5), .Q(mem_addr[5]), .QN() + ); + AOI22_X1_LVT i_0_0_9( + .A1(DAddr[6]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[6]), .ZN(n_0_0_4) + ); + INV_X1_LVT i_0_0_8( + .A(n_0_0_4), .ZN(n_0_4) + ); + DFF_X1_LVT \mem_addr_reg[4] ( + .CK(n_0_76), .D(n_0_4), .Q(mem_addr[4]), .QN() + ); + AOI22_X1_LVT i_0_0_7( + .A1(DAddr[5]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[5]), .ZN(n_0_0_3) + ); + INV_X1_LVT i_0_0_6( + .A(n_0_0_3), .ZN(n_0_3) + ); + DFF_X1_LVT \mem_addr_reg[3] ( + .CK(n_0_76), .D(n_0_3), .Q(mem_addr[3]), .QN() + ); + AOI22_X1_LVT i_0_0_5( + .A1(DAddr[4]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[4]), .ZN(n_0_0_2) + ); + INV_X1_LVT i_0_0_4( + .A(n_0_0_2), .ZN(n_0_2) + ); + DFF_X1_LVT \mem_addr_reg[2] ( + .CK(n_0_76), .D(n_0_2), .Q(mem_addr[2]), .QN() + ); + AOI22_X1_LVT i_0_0_3( + .A1(DAddr[3]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[3]), .ZN(n_0_0_1) + ); + INV_X1_LVT i_0_0_2( + .A(n_0_0_1), .ZN(n_0_1) + ); + DFF_X1_LVT \mem_addr_reg[1] ( + .CK(n_0_76), .D(n_0_1), .Q(mem_addr[1]), .QN() + ); + AOI22_X1_LVT i_0_0_1( + .A1(DAddr[2]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[2]), .ZN(n_0_0_0) + ); + INV_X1_LVT i_0_0_0( + .A(n_0_0_0), .ZN(n_0_0) + ); + DFF_X1_LVT \mem_addr_reg[0] ( + .CK(n_0_76), .D(n_0_0), .Q(mem_addr[0]), .QN() + ); + NOR2_X1_LVT i_0_0_162( + .A1(DWidth[1]), .A2(DAddr[1]), .ZN(n_0_0_87) + ); + NOR2_X1_LVT i_0_0_158( + .A1(DWidth[0]), .A2(DAddr[0]), .ZN(n_0_0_83) + ); + AND2_X1_LVT i_0_0_157( + .A1(n_0_0_87), .A2(n_0_0_83), .ZN(n_0_0_82) + ); + AND2_X1_LVT i_0_0_156( + .A1(n_0_0_88), .A2(n_0_0_82), .ZN(n_0_0_81) + ); + INV_X1_LVT i_0_0_173( + .A(n_0_0_88), .ZN(n_0_0_95) + ); + INV_X1_LVT i_0_0_169( + .A(DWidth[1]), .ZN(n_0_0_93) + ); + NOR3_X1_LVT i_0_0_155( + .A1(n_0_0_95), .A2(DWidth[0]), .A3(n_0_0_93), .ZN(n_0_0_80) + ); + AOI22_X1_LVT i_0_0_154( + .A1(DWData[7]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[31]), .ZN(n_0_0_79) + ); + NAND2_X1_LVT i_0_0_168( + .A1(DWidth[0]), .A2(DWidth[1]), .ZN(n_0_43) + ); + INV_X1_LVT i_0_0_167( + .A(n_0_43), .ZN(n_0_0_92) + ); + NOR2_X1_LVT i_0_0_160( + .A1(n_0_0_95), .A2(n_0_0_92), .ZN(n_0_0_85) + ); + NAND2_X1_LVT i_0_0_161( + .A1(n_0_0_93), .A2(DAddr[1]), .ZN(n_0_0_86) + ); + NOR2_X1_LVT i_0_0_166( + .A1(DWidth[0]), .A2(DWidth[1]), .ZN(n_0_0_91) + ); + NAND2_X1_LVT i_0_0_164( + .A1(DAddr[0]), .A2(n_0_0_91), .ZN(n_0_0_89) + ); + NAND3_X1_LVT i_0_0_159( + .A1(n_0_0_85), .A2(n_0_0_86), .A3(n_0_0_89), .ZN(n_0_0_84) + ); + INV_X1_LVT i_0_0_170( + .A(DWidth[0]), .ZN(n_0_0_94) + ); + NOR2_X1_LVT i_0_0_153( + .A1(n_0_0_94), .A2(DAddr[1]), .ZN(n_0_0_78) + ); + AND3_X1_LVT i_0_0_152( + .A1(n_0_0_88), .A2(n_0_0_78), .A3(n_0_0_93), .ZN(n_0_0_77) + ); + AOI22_X1_LVT i_0_0_151( + .A1(n_0_0_84), .A2(mem_wdata[31]), .B1(DWData[15]), .B2(n_0_0_77), .ZN(n_0_0_76) + ); + NAND2_X1_LVT i_0_0_150( + .A1(n_0_0_79), .A2(n_0_0_76), .ZN(n_0_75) + ); + DFF_X1_LVT \mem_wdata_reg[31] ( + .CK(n_0_76), .D(n_0_75), .Q(mem_wdata[31]), .QN() + ); + AOI22_X1_LVT i_0_0_149( + .A1(DWData[6]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[30]), .ZN(n_0_0_75) + ); + AOI22_X1_LVT i_0_0_148( + .A1(n_0_0_84), .A2(mem_wdata[30]), .B1(DWData[14]), .B2(n_0_0_77), .ZN(n_0_0_74) + ); + NAND2_X1_LVT i_0_0_147( + .A1(n_0_0_75), .A2(n_0_0_74), .ZN(n_0_74) + ); + DFF_X1_LVT \mem_wdata_reg[30] ( + .CK(n_0_76), .D(n_0_74), .Q(mem_wdata[30]), .QN() + ); + AOI22_X1_LVT i_0_0_146( + .A1(DWData[5]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[29]), .ZN(n_0_0_73) + ); + AOI22_X1_LVT i_0_0_145( + .A1(n_0_0_84), .A2(mem_wdata[29]), .B1(DWData[13]), .B2(n_0_0_77), .ZN(n_0_0_72) + ); + NAND2_X1_LVT i_0_0_144( + .A1(n_0_0_73), .A2(n_0_0_72), .ZN(n_0_73) + ); + DFF_X1_LVT \mem_wdata_reg[29] ( + .CK(n_0_76), .D(n_0_73), .Q(mem_wdata[29]), .QN() + ); + AOI22_X1_LVT i_0_0_143( + .A1(DWData[4]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[28]), .ZN(n_0_0_71) + ); + AOI22_X1_LVT i_0_0_142( + .A1(n_0_0_84), .A2(mem_wdata[28]), .B1(DWData[12]), .B2(n_0_0_77), .ZN(n_0_0_70) + ); + NAND2_X1_LVT i_0_0_141( + .A1(n_0_0_71), .A2(n_0_0_70), .ZN(n_0_72) + ); + DFF_X1_LVT \mem_wdata_reg[28] ( + .CK(n_0_76), .D(n_0_72), .Q(mem_wdata[28]), .QN() + ); + AOI22_X1_LVT i_0_0_140( + .A1(DWData[3]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[27]), .ZN(n_0_0_69) + ); + AOI22_X1_LVT i_0_0_139( + .A1(n_0_0_84), .A2(mem_wdata[27]), .B1(DWData[11]), .B2(n_0_0_77), .ZN(n_0_0_68) + ); + NAND2_X1_LVT i_0_0_138( + .A1(n_0_0_69), .A2(n_0_0_68), .ZN(n_0_71) + ); + DFF_X1_LVT \mem_wdata_reg[27] ( + .CK(n_0_76), .D(n_0_71), .Q(mem_wdata[27]), .QN() + ); + AOI22_X1_LVT i_0_0_137( + .A1(DWData[2]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[26]), .ZN(n_0_0_67) + ); + AOI22_X1_LVT i_0_0_136( + .A1(n_0_0_84), .A2(mem_wdata[26]), .B1(DWData[10]), .B2(n_0_0_77), .ZN(n_0_0_66) + ); + NAND2_X1_LVT i_0_0_135( + .A1(n_0_0_67), .A2(n_0_0_66), .ZN(n_0_70) + ); + DFF_X1_LVT \mem_wdata_reg[26] ( + .CK(n_0_76), .D(n_0_70), .Q(mem_wdata[26]), .QN() + ); + AOI22_X1_LVT i_0_0_134( + .A1(DWData[1]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[25]), .ZN(n_0_0_65) + ); + AOI22_X1_LVT i_0_0_133( + .A1(n_0_0_84), .A2(mem_wdata[25]), .B1(DWData[9]), .B2(n_0_0_77), .ZN(n_0_0_64) + ); + NAND2_X1_LVT i_0_0_132( + .A1(n_0_0_65), .A2(n_0_0_64), .ZN(n_0_69) + ); + DFF_X1_LVT \mem_wdata_reg[25] ( + .CK(n_0_76), .D(n_0_69), .Q(mem_wdata[25]), .QN() + ); + AOI22_X1_LVT i_0_0_131( + .A1(DWData[0]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[24]), .ZN(n_0_0_63) + ); + AOI22_X1_LVT i_0_0_130( + .A1(n_0_0_84), .A2(mem_wdata[24]), .B1(DWData[8]), .B2(n_0_0_77), .ZN(n_0_0_62) + ); + NAND2_X1_LVT i_0_0_129( + .A1(n_0_0_63), .A2(n_0_0_62), .ZN(n_0_68) + ); + DFF_X1_LVT \mem_wdata_reg[24] ( + .CK(n_0_76), .D(n_0_68), .Q(mem_wdata[24]), .QN() + ); + NOR4_X1_LVT i_0_0_127( + .A1(n_0_0_95), .A2(n_0_0_83), .A3(DWidth[1]), .A4(DAddr[1]), .ZN(n_0_0_60) + ); + INV_X1_LVT i_0_0_165( + .A(n_0_0_91), .ZN(n_0_0_90) + ); + OAI211_X1_LVT i_0_0_128( + .A(n_0_0_85), .B(n_0_0_86), .C1(n_0_0_90), .C2(DAddr[0]), .ZN(n_0_0_61) + ); + AOI222_X1_LVT i_0_0_126( + .A1(DWData[7]), .A2(n_0_0_60), .B1(mem_wdata[23]), .B2(n_0_0_61), .C1(DWData[23]), + .C2(n_0_0_80), .ZN(n_0_0_59) + ); + INV_X1_LVT i_0_0_125( + .A(n_0_0_59), .ZN(n_0_67) + ); + DFF_X1_LVT \mem_wdata_reg[23] ( + .CK(n_0_76), .D(n_0_67), .Q(mem_wdata[23]), .QN() + ); + AOI222_X1_LVT i_0_0_124( + .A1(DWData[6]), .A2(n_0_0_60), .B1(mem_wdata[22]), .B2(n_0_0_61), .C1(DWData[22]), + .C2(n_0_0_80), .ZN(n_0_0_58) + ); + INV_X1_LVT i_0_0_123( + .A(n_0_0_58), .ZN(n_0_66) + ); + DFF_X1_LVT \mem_wdata_reg[22] ( + .CK(n_0_76), .D(n_0_66), .Q(mem_wdata[22]), .QN() + ); + AOI222_X1_LVT i_0_0_122( + .A1(DWData[5]), .A2(n_0_0_60), .B1(mem_wdata[21]), .B2(n_0_0_61), .C1(DWData[21]), + .C2(n_0_0_80), .ZN(n_0_0_57) + ); + INV_X1_LVT i_0_0_121( + .A(n_0_0_57), .ZN(n_0_44) + ); + DFF_X1_LVT \mem_wdata_reg[21] ( + .CK(n_0_76), .D(n_0_44), .Q(mem_wdata[21]), .QN() + ); + AOI222_X1_LVT i_0_0_120( + .A1(DWData[4]), .A2(n_0_0_60), .B1(mem_wdata[20]), .B2(n_0_0_61), .C1(DWData[20]), + .C2(n_0_0_80), .ZN(n_0_0_56) + ); + INV_X1_LVT i_0_0_119( + .A(n_0_0_56), .ZN(n_0_45) + ); + DFF_X1_LVT \mem_wdata_reg[20] ( + .CK(n_0_76), .D(n_0_45), .Q(mem_wdata[20]), .QN() + ); + AOI222_X1_LVT i_0_0_118( + .A1(DWData[3]), .A2(n_0_0_60), .B1(mem_wdata[19]), .B2(n_0_0_61), .C1(DWData[19]), + .C2(n_0_0_80), .ZN(n_0_0_55) + ); + INV_X1_LVT i_0_0_117( + .A(n_0_0_55), .ZN(n_0_46) + ); + DFF_X1_LVT \mem_wdata_reg[19] ( + .CK(n_0_76), .D(n_0_46), .Q(mem_wdata[19]), .QN() + ); + AOI222_X1_LVT i_0_0_116( + .A1(DWData[2]), .A2(n_0_0_60), .B1(mem_wdata[18]), .B2(n_0_0_61), .C1(DWData[18]), + .C2(n_0_0_80), .ZN(n_0_0_54) + ); + INV_X1_LVT i_0_0_115( + .A(n_0_0_54), .ZN(n_0_47) + ); + DFF_X1_LVT \mem_wdata_reg[18] ( + .CK(n_0_76), .D(n_0_47), .Q(mem_wdata[18]), .QN() + ); + AOI222_X1_LVT i_0_0_114( + .A1(DWData[1]), .A2(n_0_0_60), .B1(mem_wdata[17]), .B2(n_0_0_61), .C1(DWData[17]), + .C2(n_0_0_80), .ZN(n_0_0_53) + ); + INV_X1_LVT i_0_0_113( + .A(n_0_0_53), .ZN(n_0_48) + ); + DFF_X1_LVT \mem_wdata_reg[17] ( + .CK(n_0_76), .D(n_0_48), .Q(mem_wdata[17]), .QN() + ); + AOI222_X1_LVT i_0_0_112( + .A1(DWData[0]), .A2(n_0_0_60), .B1(mem_wdata[16]), .B2(n_0_0_61), .C1(DWData[16]), + .C2(n_0_0_80), .ZN(n_0_0_52) + ); + INV_X1_LVT i_0_0_111( + .A(n_0_0_52), .ZN(n_0_49) + ); + DFF_X1_LVT \mem_wdata_reg[16] ( + .CK(n_0_76), .D(n_0_49), .Q(mem_wdata[16]), .QN() + ); + NOR4_X1_LVT i_0_0_110( + .A1(n_0_0_95), .A2(n_0_0_87), .A3(n_0_0_92), .A4(n_0_0_91), .ZN(n_0_0_51) + ); + NOR3_X1_LVT i_0_0_109( + .A1(n_0_0_86), .A2(DAddr[0]), .A3(DWidth[0]), .ZN(n_0_0_50) + ); + AND2_X1_LVT i_0_0_108( + .A1(n_0_0_88), .A2(n_0_0_50), .ZN(n_0_0_49) + ); + OAI211_X1_LVT i_0_0_107( + .A(n_0_0_85), .B(n_0_0_89), .C1(DAddr[1]), .C2(DWidth[1]), .ZN(n_0_0_48) + ); + AOI222_X1_LVT i_0_0_106( + .A1(DWData[15]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[7]), .C1(n_0_0_48), + .C2(mem_wdata[15]), .ZN(n_0_0_47) + ); + INV_X1_LVT i_0_0_105( + .A(n_0_0_47), .ZN(n_0_50) + ); + DFF_X1_LVT \mem_wdata_reg[15] ( + .CK(n_0_76), .D(n_0_50), .Q(mem_wdata[15]), .QN() + ); + AOI222_X1_LVT i_0_0_104( + .A1(DWData[14]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[6]), .C1(n_0_0_48), + .C2(mem_wdata[14]), .ZN(n_0_0_46) + ); + INV_X1_LVT i_0_0_103( + .A(n_0_0_46), .ZN(n_0_51) + ); + DFF_X1_LVT \mem_wdata_reg[14] ( + .CK(n_0_76), .D(n_0_51), .Q(mem_wdata[14]), .QN() + ); + AOI222_X1_LVT i_0_0_102( + .A1(DWData[13]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[5]), .C1(n_0_0_48), + .C2(mem_wdata[13]), .ZN(n_0_0_45) + ); + INV_X1_LVT i_0_0_101( + .A(n_0_0_45), .ZN(n_0_52) + ); + DFF_X1_LVT \mem_wdata_reg[13] ( + .CK(n_0_76), .D(n_0_52), .Q(mem_wdata[13]), .QN() + ); + AOI222_X1_LVT i_0_0_100( + .A1(DWData[12]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[4]), .C1(n_0_0_48), + .C2(mem_wdata[12]), .ZN(n_0_0_44) + ); + INV_X1_LVT i_0_0_99( + .A(n_0_0_44), .ZN(n_0_53) + ); + DFF_X1_LVT \mem_wdata_reg[12] ( + .CK(n_0_76), .D(n_0_53), .Q(mem_wdata[12]), .QN() + ); + AOI222_X1_LVT i_0_0_98( + .A1(DWData[11]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[3]), .C1(n_0_0_48), + .C2(mem_wdata[11]), .ZN(n_0_0_43) + ); + INV_X1_LVT i_0_0_97( + .A(n_0_0_43), .ZN(n_0_54) + ); + DFF_X1_LVT \mem_wdata_reg[11] ( + .CK(n_0_76), .D(n_0_54), .Q(mem_wdata[11]), .QN() + ); + AOI222_X1_LVT i_0_0_96( + .A1(DWData[10]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[2]), .C1(n_0_0_48), + .C2(mem_wdata[10]), .ZN(n_0_0_42) + ); + INV_X1_LVT i_0_0_95( + .A(n_0_0_42), .ZN(n_0_55) + ); + DFF_X1_LVT \mem_wdata_reg[10] ( + .CK(n_0_76), .D(n_0_55), .Q(mem_wdata[10]), .QN() + ); + AOI222_X1_LVT i_0_0_94( + .A1(DWData[9]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[1]), .C1(n_0_0_48), + .C2(mem_wdata[9]), .ZN(n_0_0_41) + ); + INV_X1_LVT i_0_0_93( + .A(n_0_0_41), .ZN(n_0_56) + ); + DFF_X1_LVT \mem_wdata_reg[9] ( + .CK(n_0_76), .D(n_0_56), .Q(mem_wdata[9]), .QN() + ); + AOI222_X1_LVT i_0_0_92( + .A1(DWData[8]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[0]), .C1(n_0_0_48), + .C2(mem_wdata[8]), .ZN(n_0_0_40) + ); + INV_X1_LVT i_0_0_91( + .A(n_0_0_40), .ZN(n_0_57) + ); + DFF_X1_LVT \mem_wdata_reg[8] ( + .CK(n_0_76), .D(n_0_57), .Q(mem_wdata[8]), .QN() + ); + AOI21_X1_LVT i_0_0_90( + .A(n_0_0_87), .B1(n_0_0_83), .B2(n_0_0_93), .ZN(n_0_0_39) + ); + NAND2_X1_LVT i_0_0_89( + .A1(n_0_0_85), .A2(n_0_0_39), .ZN(n_0_0_38) + ); + MUX2_X1_LVT i_0_0_88( + .A(DWData[7]), .B(mem_wdata[7]), .S(n_0_0_38), .Z(n_0_58) + ); + DFF_X1_LVT \mem_wdata_reg[7] ( + .CK(n_0_76), .D(n_0_58), .Q(mem_wdata[7]), .QN() + ); + MUX2_X1_LVT i_0_0_87( + .A(DWData[6]), .B(mem_wdata[6]), .S(n_0_0_38), .Z(n_0_59) + ); + DFF_X1_LVT \mem_wdata_reg[6] ( + .CK(n_0_76), .D(n_0_59), .Q(mem_wdata[6]), .QN() + ); + MUX2_X1_LVT i_0_0_86( + .A(DWData[5]), .B(mem_wdata[5]), .S(n_0_0_38), .Z(n_0_60) + ); + DFF_X1_LVT \mem_wdata_reg[5] ( + .CK(n_0_76), .D(n_0_60), .Q(mem_wdata[5]), .QN() + ); + MUX2_X1_LVT i_0_0_85( + .A(DWData[4]), .B(mem_wdata[4]), .S(n_0_0_38), .Z(n_0_61) + ); + DFF_X1_LVT \mem_wdata_reg[4] ( + .CK(n_0_76), .D(n_0_61), .Q(mem_wdata[4]), .QN() + ); + MUX2_X1_LVT i_0_0_84( + .A(DWData[3]), .B(mem_wdata[3]), .S(n_0_0_38), .Z(n_0_62) + ); + DFF_X1_LVT \mem_wdata_reg[3] ( + .CK(n_0_76), .D(n_0_62), .Q(mem_wdata[3]), .QN() + ); + MUX2_X1_LVT i_0_0_83( + .A(DWData[2]), .B(mem_wdata[2]), .S(n_0_0_38), .Z(n_0_63) + ); + DFF_X1_LVT \mem_wdata_reg[2] ( + .CK(n_0_76), .D(n_0_63), .Q(mem_wdata[2]), .QN() + ); + MUX2_X1_LVT i_0_0_82( + .A(DWData[1]), .B(mem_wdata[1]), .S(n_0_0_38), .Z(n_0_64) + ); + DFF_X1_LVT \mem_wdata_reg[1] ( + .CK(n_0_76), .D(n_0_64), .Q(mem_wdata[1]), .QN() + ); + MUX2_X1_LVT i_0_0_81( + .A(DWData[0]), .B(mem_wdata[0]), .S(n_0_0_38), .Z(n_0_65) + ); + DFF_X1_LVT \mem_wdata_reg[0] ( + .CK(n_0_76), .D(n_0_65), .Q(mem_wdata[0]), .QN() + ); + MemGen_32_11 RAM( + .chip_en(), .clock(clk), .addr(mem_addr), .rd_data(mem_rdata), .rd_en(n_0), + .wr_en(DWE), .wr_data(mem_wdata) + ); + DFF_X1_LVT \drTmp_reg[31] ( + .CK(n_0_76), .D(mem_rdata[31]), .Q(drTmp[31]), .QN() + ); + AND2_X1_LVT i_0_0_80( + .A1(DWidth[1]), .A2(drTmp[31]), .ZN(n_0_42) + ); + DLH_X1_LVT \DRData[31] ( + .D(n_0_42), .G(n_0_43), .Q(DRData[31]) + ); + DFF_X1_LVT \drTmp_reg[30] ( + .CK(n_0_76), .D(mem_rdata[30]), .Q(drTmp[30]), .QN() + ); + AND2_X1_LVT i_0_0_79( + .A1(DWidth[1]), .A2(drTmp[30]), .ZN(n_0_41) + ); + DLH_X1_LVT \DRData[30] ( + .D(n_0_41), .G(n_0_43), .Q(DRData[30]) + ); + DFF_X1_LVT \drTmp_reg[29] ( + .CK(n_0_76), .D(mem_rdata[29]), .Q(drTmp[29]), .QN() + ); + AND2_X1_LVT i_0_0_78( + .A1(DWidth[1]), .A2(drTmp[29]), .ZN(n_0_40) + ); + DLH_X1_LVT \DRData[29] ( + .D(n_0_40), .G(n_0_43), .Q(DRData[29]) + ); + DFF_X1_LVT \drTmp_reg[28] ( + .CK(n_0_76), .D(mem_rdata[28]), .Q(drTmp[28]), .QN() + ); + AND2_X1_LVT i_0_0_77( + .A1(DWidth[1]), .A2(drTmp[28]), .ZN(n_0_39) + ); + DLH_X1_LVT \DRData[28] ( + .D(n_0_39), .G(n_0_43), .Q(DRData[28]) + ); + DFF_X1_LVT \drTmp_reg[27] ( + .CK(n_0_76), .D(mem_rdata[27]), .Q(drTmp[27]), .QN() + ); + AND2_X1_LVT i_0_0_76( + .A1(DWidth[1]), .A2(drTmp[27]), .ZN(n_0_38) + ); + DLH_X1_LVT \DRData[27] ( + .D(n_0_38), .G(n_0_43), .Q(DRData[27]) + ); + DFF_X1_LVT \drTmp_reg[26] ( + .CK(n_0_76), .D(mem_rdata[26]), .Q(drTmp[26]), .QN() + ); + AND2_X1_LVT i_0_0_75( + .A1(DWidth[1]), .A2(drTmp[26]), .ZN(n_0_37) + ); + DLH_X1_LVT \DRData[26] ( + .D(n_0_37), .G(n_0_43), .Q(DRData[26]) + ); + DFF_X1_LVT \drTmp_reg[25] ( + .CK(n_0_76), .D(mem_rdata[25]), .Q(drTmp[25]), .QN() + ); + AND2_X1_LVT i_0_0_74( + .A1(DWidth[1]), .A2(drTmp[25]), .ZN(n_0_36) + ); + DLH_X1_LVT \DRData[25] ( + .D(n_0_36), .G(n_0_43), .Q(DRData[25]) + ); + DFF_X1_LVT \drTmp_reg[24] ( + .CK(n_0_76), .D(mem_rdata[24]), .Q(drTmp[24]), .QN() + ); + AND2_X1_LVT i_0_0_73( + .A1(DWidth[1]), .A2(drTmp[24]), .ZN(n_0_35) + ); + DLH_X1_LVT \DRData[24] ( + .D(n_0_35), .G(n_0_43), .Q(DRData[24]) + ); + DFF_X1_LVT \drTmp_reg[23] ( + .CK(n_0_76), .D(mem_rdata[23]), .Q(drTmp[23]), .QN() + ); + AND2_X1_LVT i_0_0_72( + .A1(DWidth[1]), .A2(drTmp[23]), .ZN(n_0_34) + ); + DLH_X1_LVT \DRData[23] ( + .D(n_0_34), .G(n_0_43), .Q(DRData[23]) + ); + DFF_X1_LVT \drTmp_reg[22] ( + .CK(n_0_76), .D(mem_rdata[22]), .Q(drTmp[22]), .QN() + ); + AND2_X1_LVT i_0_0_71( + .A1(DWidth[1]), .A2(drTmp[22]), .ZN(n_0_33) + ); + DLH_X1_LVT \DRData[22] ( + .D(n_0_33), .G(n_0_43), .Q(DRData[22]) + ); + DFF_X1_LVT \drTmp_reg[21] ( + .CK(n_0_76), .D(mem_rdata[21]), .Q(drTmp[21]), .QN() + ); + AND2_X1_LVT i_0_0_70( + .A1(DWidth[1]), .A2(drTmp[21]), .ZN(n_0_32) + ); + DLH_X1_LVT \DRData[21] ( + .D(n_0_32), .G(n_0_43), .Q(DRData[21]) + ); + DFF_X1_LVT \drTmp_reg[20] ( + .CK(n_0_76), .D(mem_rdata[20]), .Q(drTmp[20]), .QN() + ); + AND2_X1_LVT i_0_0_69( + .A1(DWidth[1]), .A2(drTmp[20]), .ZN(n_0_31) + ); + DLH_X1_LVT \DRData[20] ( + .D(n_0_31), .G(n_0_43), .Q(DRData[20]) + ); + DFF_X1_LVT \drTmp_reg[19] ( + .CK(n_0_76), .D(mem_rdata[19]), .Q(drTmp[19]), .QN() + ); + AND2_X1_LVT i_0_0_68( + .A1(DWidth[1]), .A2(drTmp[19]), .ZN(n_0_30) + ); + DLH_X1_LVT \DRData[19] ( + .D(n_0_30), .G(n_0_43), .Q(DRData[19]) + ); + DFF_X1_LVT \drTmp_reg[18] ( + .CK(n_0_76), .D(mem_rdata[18]), .Q(drTmp[18]), .QN() + ); + AND2_X1_LVT i_0_0_67( + .A1(DWidth[1]), .A2(drTmp[18]), .ZN(n_0_29) + ); + DLH_X1_LVT \DRData[18] ( + .D(n_0_29), .G(n_0_43), .Q(DRData[18]) + ); + DFF_X1_LVT \drTmp_reg[17] ( + .CK(n_0_76), .D(mem_rdata[17]), .Q(drTmp[17]), .QN() + ); + AND2_X1_LVT i_0_0_66( + .A1(DWidth[1]), .A2(drTmp[17]), .ZN(n_0_28) + ); + DLH_X1_LVT \DRData[17] ( + .D(n_0_28), .G(n_0_43), .Q(DRData[17]) + ); + DFF_X1_LVT \drTmp_reg[16] ( + .CK(n_0_76), .D(mem_rdata[16]), .Q(drTmp[16]), .QN() + ); + AND2_X1_LVT i_0_0_65( + .A1(DWidth[1]), .A2(drTmp[16]), .ZN(n_0_27) + ); + DLH_X1_LVT \DRData[16] ( + .D(n_0_27), .G(n_0_43), .Q(DRData[16]) + ); + NOR2_X1_LVT i_0_0_64( + .A1(n_0_0_91), .A2(n_0_0_87), .ZN(n_0_0_37) + ); + DFF_X1_LVT \drTmp_reg[15] ( + .CK(n_0_76), .D(mem_rdata[15]), .Q(drTmp[15]), .QN() + ); + AOI22_X1_LVT i_0_0_63( + .A1(drTmp[31]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[15]), .ZN(n_0_0_36) + ); + INV_X1_LVT i_0_0_62( + .A(n_0_0_36), .ZN(n_0_26) + ); + DLH_X1_LVT \DRData[15] ( + .D(n_0_26), .G(n_0_43), .Q(DRData[15]) + ); + DFF_X1_LVT \drTmp_reg[14] ( + .CK(n_0_76), .D(mem_rdata[14]), .Q(drTmp[14]), .QN() + ); + AOI22_X1_LVT i_0_0_61( + .A1(drTmp[30]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[14]), .ZN(n_0_0_35) + ); + INV_X1_LVT i_0_0_60( + .A(n_0_0_35), .ZN(n_0_25) + ); + DLH_X1_LVT \DRData[14] ( + .D(n_0_25), .G(n_0_43), .Q(DRData[14]) + ); + DFF_X1_LVT \drTmp_reg[13] ( + .CK(n_0_76), .D(mem_rdata[13]), .Q(drTmp[13]), .QN() + ); + AOI22_X1_LVT i_0_0_59( + .A1(drTmp[29]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[13]), .ZN(n_0_0_34) + ); + INV_X1_LVT i_0_0_58( + .A(n_0_0_34), .ZN(n_0_24) + ); + DLH_X1_LVT \DRData[13] ( + .D(n_0_24), .G(n_0_43), .Q(DRData[13]) + ); + DFF_X1_LVT \drTmp_reg[12] ( + .CK(n_0_76), .D(mem_rdata[12]), .Q(drTmp[12]), .QN() + ); + AOI22_X1_LVT i_0_0_57( + .A1(drTmp[28]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[12]), .ZN(n_0_0_33) + ); + INV_X1_LVT i_0_0_56( + .A(n_0_0_33), .ZN(n_0_23) + ); + DLH_X1_LVT \DRData[12] ( + .D(n_0_23), .G(n_0_43), .Q(DRData[12]) + ); + DFF_X1_LVT \drTmp_reg[11] ( + .CK(n_0_76), .D(mem_rdata[11]), .Q(drTmp[11]), .QN() + ); + AOI22_X1_LVT i_0_0_55( + .A1(drTmp[27]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[11]), .ZN(n_0_0_32) + ); + INV_X1_LVT i_0_0_54( + .A(n_0_0_32), .ZN(n_0_22) + ); + DLH_X1_LVT \DRData[11] ( + .D(n_0_22), .G(n_0_43), .Q(DRData[11]) + ); + DFF_X1_LVT \drTmp_reg[10] ( + .CK(n_0_76), .D(mem_rdata[10]), .Q(drTmp[10]), .QN() + ); + AOI22_X1_LVT i_0_0_53( + .A1(drTmp[26]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[10]), .ZN(n_0_0_31) + ); + INV_X1_LVT i_0_0_52( + .A(n_0_0_31), .ZN(n_0_21) + ); + DLH_X1_LVT \DRData[10] ( + .D(n_0_21), .G(n_0_43), .Q(DRData[10]) + ); + DFF_X1_LVT \drTmp_reg[9] ( + .CK(n_0_76), .D(mem_rdata[9]), .Q(drTmp[9]), .QN() + ); + AOI22_X1_LVT i_0_0_51( + .A1(drTmp[25]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[9]), .ZN(n_0_0_30) + ); + INV_X1_LVT i_0_0_50( + .A(n_0_0_30), .ZN(n_0_20) + ); + DLH_X1_LVT \DRData[9] ( + .D(n_0_20), .G(n_0_43), .Q(DRData[9]) + ); + DFF_X1_LVT \drTmp_reg[8] ( + .CK(n_0_76), .D(mem_rdata[8]), .Q(drTmp[8]), .QN() + ); + AOI22_X1_LVT i_0_0_49( + .A1(drTmp[24]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[8]), .ZN(n_0_0_29) + ); + INV_X1_LVT i_0_0_48( + .A(n_0_0_29), .ZN(n_0_19) + ); + DLH_X1_LVT \DRData[8] ( + .D(n_0_19), .G(n_0_43), .Q(DRData[8]) + ); + AOI22_X1_LVT i_0_0_46( + .A1(drTmp[31]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[15]), .ZN(n_0_0_27) + ); + AOI211_X1_LVT i_0_0_47( + .A(DAddr[1]), .B(n_0_0_83), .C1(n_0_0_94), .C2(DWidth[1]), .ZN(n_0_0_28) + ); + DFF_X1_LVT \drTmp_reg[7] ( + .CK(n_0_76), .D(mem_rdata[7]), .Q(drTmp[7]), .QN() + ); + AOI22_X1_LVT i_0_0_45( + .A1(drTmp[23]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[7]), .ZN(n_0_0_26) + ); + NAND2_X1_LVT i_0_0_44( + .A1(n_0_0_27), .A2(n_0_0_26), .ZN(n_0_18) + ); + DLH_X1_LVT \DRData[7] ( + .D(n_0_18), .G(n_0_43), .Q(DRData[7]) + ); + AOI22_X1_LVT i_0_0_43( + .A1(drTmp[30]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[14]), .ZN(n_0_0_25) + ); + DFF_X1_LVT \drTmp_reg[6] ( + .CK(n_0_76), .D(mem_rdata[6]), .Q(drTmp[6]), .QN() + ); + AOI22_X1_LVT i_0_0_42( + .A1(drTmp[22]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[6]), .ZN(n_0_0_24) + ); + NAND2_X1_LVT i_0_0_41( + .A1(n_0_0_25), .A2(n_0_0_24), .ZN(n_0_17) + ); + DLH_X1_LVT \DRData[6] ( + .D(n_0_17), .G(n_0_43), .Q(DRData[6]) + ); + AOI22_X1_LVT i_0_0_40( + .A1(drTmp[29]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[13]), .ZN(n_0_0_23) + ); + DFF_X1_LVT \drTmp_reg[5] ( + .CK(n_0_76), .D(mem_rdata[5]), .Q(drTmp[5]), .QN() + ); + AOI22_X1_LVT i_0_0_39( + .A1(drTmp[21]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[5]), .ZN(n_0_0_22) + ); + NAND2_X1_LVT i_0_0_38( + .A1(n_0_0_23), .A2(n_0_0_22), .ZN(n_0_16) + ); + DLH_X1_LVT \DRData[5] ( + .D(n_0_16), .G(n_0_43), .Q(DRData[5]) + ); + AOI22_X1_LVT i_0_0_37( + .A1(drTmp[28]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[12]), .ZN(n_0_0_21) + ); + DFF_X1_LVT \drTmp_reg[4] ( + .CK(n_0_76), .D(mem_rdata[4]), .Q(drTmp[4]), .QN() + ); + AOI22_X1_LVT i_0_0_36( + .A1(drTmp[20]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[4]), .ZN(n_0_0_20) + ); + NAND2_X1_LVT i_0_0_35( + .A1(n_0_0_21), .A2(n_0_0_20), .ZN(n_0_15) + ); + DLH_X1_LVT \DRData[4] ( + .D(n_0_15), .G(n_0_43), .Q(DRData[4]) + ); + AOI22_X1_LVT i_0_0_34( + .A1(drTmp[27]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[11]), .ZN(n_0_0_19) + ); + DFF_X1_LVT \drTmp_reg[3] ( + .CK(n_0_76), .D(mem_rdata[3]), .Q(drTmp[3]), .QN() + ); + AOI22_X1_LVT i_0_0_33( + .A1(drTmp[19]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[3]), .ZN(n_0_0_18) + ); + NAND2_X1_LVT i_0_0_32( + .A1(n_0_0_19), .A2(n_0_0_18), .ZN(n_0_14) + ); + DLH_X1_LVT \DRData[3] ( + .D(n_0_14), .G(n_0_43), .Q(DRData[3]) + ); + AOI22_X1_LVT i_0_0_31( + .A1(drTmp[26]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[10]), .ZN(n_0_0_17) + ); + DFF_X1_LVT \drTmp_reg[2] ( + .CK(n_0_76), .D(mem_rdata[2]), .Q(drTmp[2]), .QN() + ); + AOI22_X1_LVT i_0_0_30( + .A1(drTmp[18]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[2]), .ZN(n_0_0_16) + ); + NAND2_X1_LVT i_0_0_29( + .A1(n_0_0_17), .A2(n_0_0_16), .ZN(n_0_13) + ); + DLH_X1_LVT \DRData[2] ( + .D(n_0_13), .G(n_0_43), .Q(DRData[2]) + ); + AOI22_X1_LVT i_0_0_28( + .A1(drTmp[25]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[9]), .ZN(n_0_0_15) + ); + DFF_X1_LVT \drTmp_reg[1] ( + .CK(n_0_76), .D(mem_rdata[1]), .Q(drTmp[1]), .QN() + ); + AOI22_X1_LVT i_0_0_27( + .A1(drTmp[17]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[1]), .ZN(n_0_0_14) + ); + NAND2_X1_LVT i_0_0_26( + .A1(n_0_0_15), .A2(n_0_0_14), .ZN(n_0_12) + ); + DLH_X1_LVT \DRData[1] ( + .D(n_0_12), .G(n_0_43), .Q(DRData[1]) + ); + AOI22_X1_LVT i_0_0_25( + .A1(drTmp[24]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[8]), .ZN(n_0_0_13) + ); + DFF_X1_LVT \drTmp_reg[0] ( + .CK(n_0_76), .D(mem_rdata[0]), .Q(drTmp[0]), .QN() + ); + AOI22_X1_LVT i_0_0_24( + .A1(drTmp[16]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[0]), .ZN(n_0_0_12) + ); + NAND2_X1_LVT i_0_0_23( + .A1(n_0_0_13), .A2(n_0_0_12), .ZN(n_0_11) + ); + DLH_X1_LVT \DRData[0] ( + .D(n_0_11), .G(n_0_43), .Q(DRData[0]) + ); + DFF_X1_LVT \IRData_reg[31] ( + .CK(clk), .D(mem_rdata[31]), .Q(IRData[31]), .QN() + ); + DFF_X1_LVT \IRData_reg[30] ( + .CK(clk), .D(mem_rdata[30]), .Q(IRData[30]), .QN() + ); + DFF_X1_LVT \IRData_reg[29] ( + .CK(clk), .D(mem_rdata[29]), .Q(IRData[29]), .QN() + ); + DFF_X1_LVT \IRData_reg[28] ( + .CK(clk), .D(mem_rdata[28]), .Q(IRData[28]), .QN() + ); + DFF_X1_LVT \IRData_reg[27] ( + .CK(clk), .D(mem_rdata[27]), .Q(IRData[27]), .QN() + ); + DFF_X1_LVT \IRData_reg[26] ( + .CK(clk), .D(mem_rdata[26]), .Q(IRData[26]), .QN() + ); + DFF_X1_LVT \IRData_reg[25] ( + .CK(clk), .D(mem_rdata[25]), .Q(IRData[25]), .QN() + ); + DFF_X1_LVT \IRData_reg[24] ( + .CK(clk), .D(mem_rdata[24]), .Q(IRData[24]), .QN() + ); + DFF_X1_LVT \IRData_reg[23] ( + .CK(clk), .D(mem_rdata[23]), .Q(IRData[23]), .QN() + ); + DFF_X1_LVT \IRData_reg[22] ( + .CK(clk), .D(mem_rdata[22]), .Q(IRData[22]), .QN() + ); + DFF_X1_LVT \IRData_reg[21] ( + .CK(clk), .D(mem_rdata[21]), .Q(IRData[21]), .QN() + ); + DFF_X1_LVT \IRData_reg[20] ( + .CK(clk), .D(mem_rdata[20]), .Q(IRData[20]), .QN() + ); + DFF_X1_LVT \IRData_reg[19] ( + .CK(clk), .D(mem_rdata[19]), .Q(IRData[19]), .QN() + ); + DFF_X1_LVT \IRData_reg[18] ( + .CK(clk), .D(mem_rdata[18]), .Q(IRData[18]), .QN() + ); + DFF_X1_LVT \IRData_reg[17] ( + .CK(clk), .D(mem_rdata[17]), .Q(IRData[17]), .QN() + ); + DFF_X1_LVT \IRData_reg[16] ( + .CK(clk), .D(mem_rdata[16]), .Q(IRData[16]), .QN() + ); + DFF_X1_LVT \IRData_reg[15] ( + .CK(clk), .D(mem_rdata[15]), .Q(IRData[15]), .QN() + ); + DFF_X1_LVT \IRData_reg[14] ( + .CK(clk), .D(mem_rdata[14]), .Q(IRData[14]), .QN() + ); + DFF_X1_LVT \IRData_reg[13] ( + .CK(clk), .D(mem_rdata[13]), .Q(IRData[13]), .QN() + ); + DFF_X1_LVT \IRData_reg[12] ( + .CK(clk), .D(mem_rdata[12]), .Q(IRData[12]), .QN() + ); + DFF_X1_LVT \IRData_reg[11] ( + .CK(clk), .D(mem_rdata[11]), .Q(IRData[11]), .QN() + ); + DFF_X1_LVT \IRData_reg[10] ( + .CK(clk), .D(mem_rdata[10]), .Q(IRData[10]), .QN() + ); + DFF_X1_LVT \IRData_reg[9] ( + .CK(clk), .D(mem_rdata[9]), .Q(IRData[9]), .QN() + ); + DFF_X1_LVT \IRData_reg[8] ( + .CK(clk), .D(mem_rdata[8]), .Q(IRData[8]), .QN() + ); + DFF_X1_LVT \IRData_reg[7] ( + .CK(clk), .D(mem_rdata[7]), .Q(IRData[7]), .QN() + ); + DFF_X1_LVT \IRData_reg[6] ( + .CK(clk), .D(mem_rdata[6]), .Q(IRData[6]), .QN() + ); + DFF_X1_LVT \IRData_reg[5] ( + .CK(clk), .D(mem_rdata[5]), .Q(IRData[5]), .QN() + ); + DFF_X1_LVT \IRData_reg[4] ( + .CK(clk), .D(mem_rdata[4]), .Q(IRData[4]), .QN() + ); + DFF_X1_LVT \IRData_reg[3] ( + .CK(clk), .D(mem_rdata[3]), .Q(IRData[3]), .QN() + ); + DFF_X1_LVT \IRData_reg[2] ( + .CK(clk), .D(mem_rdata[2]), .Q(IRData[2]), .QN() + ); + DFF_X1_LVT \IRData_reg[1] ( + .CK(clk), .D(mem_rdata[1]), .Q(IRData[1]), .QN() + ); + DFF_X1_LVT \IRData_reg[0] ( + .CK(clk), .D(mem_rdata[0]), .Q(IRData[0]), .QN() + ); +endmodule + +module reg_file(Rs1, Rs2, Rd, RRs1, RRs2, WRd, WrReg, reset, clk, dftIn, ts_intno31, + ts_no1050, ts_no1051, ts_no1053, ts_no1054, ts_extsi1226, ts_extsi1227, + ts_extsi1228); + input [31:0] WRd; + input [4:0] Rs1, Rs2, Rd; + input WrReg, reset, clk, dftIn, ts_extsi1227, ts_extsi1228, ts_intno31, + ts_extsi1226; + output [31:0] RRs1, RRs2; + output ts_no1050, ts_no1051, ts_no1053, ts_no1054; + + wire [31:0] registers_1__ap, registers_2__ap, registers_3__ap, + registers_4__ap, registers_5__ap, registers_6__ap, + registers_7__ap, registers_8__ap, registers_9__ap, + registers_10__ap, registers_11__ap, registers_12__ap, + registers_13__ap, registers_14__ap, registers_15__ap, + registers_16__ap, registers_17__ap, registers_18__ap, + registers_19__ap, registers_20__ap, registers_21__ap, + registers_22__ap, registers_23__ap, registers_24__ap, + registers_25__ap, registers_26__ap, registers_27__ap, + registers_28__ap, registers_29__ap, registers_30__ap, + registers_31__ap, registers; + wire n_0_0, n_0_32, n_0_33, n_0_34, n_0_35, n_0_36, n_0_37, n_0_38, n_0_39, + n_0_40, n_0_41, n_0_42, n_0_43, n_0_44, n_0_45, n_0_46, n_0_47, n_0_48, + n_0_49, n_0_50, n_0_51, n_0_52, n_0_53, n_0_54, n_0_55, n_0_56, n_0_57, + n_0_58, n_0_59, n_0_60, n_0_61, n_0_31, n_0_30, n_0_29, n_0_28, n_0_27, + n_0_26, n_0_25, n_0_24, n_0_0_0, n_0_0_1, n_0_23, n_0_22, n_0_21, + n_0_20, n_0_19, n_0_18, n_0_17, n_0_16, n_0_0_2, n_0_0_3, n_0_15, + n_0_14, n_0_13, n_0_12, n_0_11, n_0_10, n_0_9, n_0_8, n_0_0_4, n_0_0_5, + n_0_7, n_0_0_6, n_0_6, n_0_0_7, n_0_5, n_0_0_8, n_0_4, n_0_0_9, + n_0_0_10, n_0_3, n_0_0_11, n_0_2, n_0_0_12, n_0_1, n_0_0_13, n_0_0_14, + n_0_0_15, n_0_0_16, n_0_0_17, n_0_0_18, n_0_0_19, n_0_0_20, n_1_0_0, + n_1_0_1, n_1_0_2, n_1_0_3, n_1_0_4, n_1_0_5, n_1_0_6, n_1_0_7, n_1_0_8, + n_1_0_9, n_1_0_10, n_1_0_11, n_1_0_12, n_1_0_13, n_1_0_14, n_1_0_15, + n_1_0_16, n_1_0_17, n_1_0_18, n_1_0_19, n_1_0_20, n_1_0_21, n_1_0_22, + n_1_0_23, n_1_0_24, n_1_0_25, n_1_0_26, n_1_0_27, n_1_0_28, n_1_0_29, + n_1_0_30, n_1_0_31, n_1_0_32, n_1_0_33, n_1_0_34, n_1_0_35, n_1_0_36, + n_1_0_37, n_1_0_38, n_1_0_39, n_1_0_40, n_1_0_41, n_1_0_42, n_1_0_43, + n_1_0_44, n_1_0_45, n_1_0_46, n_1_0_47, n_1_0_48, n_1_0_49, n_1_0_50, + n_1_0_51, n_1_0_52, n_1_0_53, n_1_0_54, n_1_0_55, n_1_0_56, n_1_0_57, + n_1_0_58, n_1_0_59, n_1_0_60, n_1_0_61, n_1_0_62, n_1_0_63, n_1_0_64, + n_1_0_65, n_1_0_66, n_1_0_67, n_1_0_68, n_1_0_69, n_1_0_70, n_1_0_71, + n_1_0_72, n_1_0_73, n_1_0_74, n_1_0_75, n_1_0_76, n_1_0_77, n_1_0_78, + n_1_0_79, n_1_0_80, n_1_0_81, n_1_0_82, n_1_0_83, n_1_0_84, n_1_0_85, + n_1_0_86, n_1_0_87, n_1_0_88, n_1_0_89, n_1_0_90, n_1_0_91, n_1_0_92, + n_1_0_93, n_1_0_94, n_1_0_95, n_1_0_96, n_1_0_97, n_1_0_98, n_1_0_99, + n_1_0_100, n_1_0_101, n_1_0_102, n_1_0_103, n_1_0_104, n_1_0_105, + n_1_0_106, n_1_0_107, n_1_0_108, n_1_0_109, n_1_0_110, n_1_0_111, + n_1_0_112, n_1_0_113, n_1_0_114, n_1_0_115, n_1_0_116, n_1_0_117, + n_1_0_118, n_1_0_119, n_1_0_120, n_1_0_121, n_1_0_122, n_1_0_123, + n_1_0_124, n_1_0_125, n_1_0_126, n_1_0_127, n_1_0_128, n_1_0_129, + n_1_0_130, n_1_0_131, n_1_0_132, n_1_0_133, n_1_0_134, n_1_0_135, + n_1_0_136, n_1_0_137, n_1_0_138, n_1_0_139, n_1_0_140, n_1_0_141, + n_1_0_142, n_1_0_143, n_1_0_144, n_1_0_145, n_1_0_146, n_1_0_147, + n_1_0_148, n_1_0_149, n_1_0_150, n_1_0_151, n_1_0_152, n_1_0_153, + n_1_0_154, n_1_0_155, n_1_0_156, n_1_0_157, n_1_0_158, n_1_0_159, + n_1_0_160, n_1_0_161, n_1_0_162, n_1_0_163, n_1_0_164, n_1_0_165, + n_1_0_166, n_1_0_167, n_1_0_168, n_1_0_169, n_1_0_170, n_1_0_171, + n_1_0_172, n_1_0_173, n_1_0_174, n_1_0_175, n_1_0_176, n_1_0_177, + n_1_0_178, n_1_0_179, n_1_0_180, n_1_0_181, n_1_0_182, n_1_0_183, + n_1_0_184, n_1_0_185, n_1_0_186, n_1_0_187, n_1_0_188, n_1_0_189, + n_1_0_190, n_1_0_191, n_1_0_192, n_1_0_193, n_1_0_194, n_1_0_195, + n_1_0_196, n_1_0_197, n_1_0_198, n_1_0_199, n_1_0_200, n_1_0_201, + n_1_0_202, n_1_0_203, n_1_0_204, n_1_0_205, n_1_0_206, n_1_0_207, + n_1_0_208, n_1_0_209, n_1_0_210, n_1_0_211, n_1_0_212, n_1_0_213, + n_1_0_214, n_1_0_215, n_1_0_216, n_1_0_217, n_1_0_218, n_1_0_219, + n_1_0_220, n_1_0_221, n_1_0_222, n_1_0_223, n_1_0_224, n_1_0_225, + n_1_0_226, n_1_0_227, n_1_0_228, n_1_0_229, n_1_0_230, n_1_0_231, + n_1_0_232, n_1_0_233, n_1_0_234, n_1_0_235, n_1_0_236, n_1_0_237, + n_1_0_238, n_1_0_239, n_1_0_240, n_1_0_241, n_1_0_242, n_1_0_243, + n_1_0_244, n_1_0_245, n_1_0_246, n_1_0_247, n_1_0_248, n_1_0_249, + n_1_0_250, n_1_0_251, n_1_0_252, n_1_0_253, n_1_0_254, n_1_0_255, + n_1_0_256, n_1_0_257, n_1_0_258, n_1_0_259, n_1_0_260, n_1_0_261, + n_1_0_262, n_1_0_263, n_1_0_264, n_1_0_265, n_1_0_266, n_1_0_267, + n_1_0_268, n_1_0_269, n_1_0_270, n_1_0_271, n_1_0_272, n_1_0_273, + n_1_0_274, n_1_0_275, n_1_0_276, n_1_0_277, n_1_0_278, n_1_0_279, + n_1_0_280, n_1_0_281, n_1_0_282, n_1_0_283, n_1_0_284, n_1_0_285, + n_1_0_286, n_1_0_287, n_1_0_288, n_1_0_289, n_1_0_290, n_1_0_291, + n_1_0_292, n_1_0_293, n_1_0_294, n_1_0_295, n_1_0_296, n_1_0_297, + n_1_0_298, n_1_0_299, n_1_0_300, n_1_0_301, n_1_0_302, n_1_0_303, + n_1_0_304, n_1_0_305, n_1_0_306, n_1_0_307, n_1_0_308, n_1_0_309, + n_1_0_310, n_1_0_311, n_1_0_312, n_1_0_313, n_1_0_314, n_1_0_315, + n_1_0_316, n_1_0_317, n_1_0_318, n_1_0_319, n_1_0_320, n_1_0_321, + n_1_0_322, n_1_0_323, n_1_0_324, n_1_0_325, n_1_0_326, n_1_0_327, + n_1_0_328, n_1_0_329, n_1_0_330, n_1_0_331, n_1_0_332, n_1_0_333, + n_1_0_334, n_1_0_335, n_1_0_336, n_1_0_337, n_1_0_338, n_1_0_339, + n_1_0_340, n_1_0_341, n_1_0_342, n_1_0_343, n_1_0_344, n_1_0_345, + n_1_0_346, n_1_0_347, n_1_0_348, n_1_0_349, n_1_0_350, n_1_0_351, + n_1_0_352, n_1_0_353, n_1_0_354, n_1_0_355, n_1_0_356, n_1_0_357, + n_1_0_358, n_1_0_359, n_1_0_360, n_1_0_361, n_1_0_362, n_1_0_363, + n_1_0_364, n_1_0_365, n_1_0_366, n_1_0_367, n_1_0_368, n_1_0_369, + n_1_0_370, n_1_0_371, n_1_0_372, n_1_0_373, n_1_0_374, n_1_0_375, + n_1_0_376, n_1_0_377, n_1_0_378, n_1_0_379, n_1_0_380, n_1_0_381, + n_1_0_382, n_1_0_383, n_1_0_384, n_1_0_385, n_1_0_386, n_1_0_387, + n_1_0_388, n_1_0_389, n_1_0_390, n_1_0_391, n_1_0_392, n_1_0_393, + n_1_0_394, n_1_0_395, n_1_0_396, n_1_0_397, n_1_0_398, n_1_0_399, + n_1_0_400, n_1_0_401, n_1_0_402, n_1_0_403, n_1_0_404, n_1_0_405, + n_1_0_406, n_1_0_407, n_1_0_408, n_1_0_409, n_1_0_410, n_1_0_411, + n_1_0_412, n_1_0_413, n_1_0_414, n_1_0_415, n_1_0_416, n_1_0_417, + n_1_0_418, n_1_0_419, n_1_0_420, n_1_0_421, n_1_0_422, n_1_0_423, + n_1_0_424, n_1_0_425, n_1_0_426, n_1_0_427, n_1_0_428, n_1_0_429, + n_1_0_430, n_1_0_431, n_1_0_432, n_1_0_433, n_1_0_434, n_1_0_435, + n_1_0_436, n_1_0_437, n_1_0_438, n_1_0_439, n_1_0_440, n_1_0_441, + n_1_0_442, n_1_0_443, n_1_0_444, n_1_0_445, n_1_0_446, n_1_0_447, + n_1_0_448, n_1_0_449, n_1_0_450, n_1_0_451, n_1_0_452, n_1_0_453, + n_1_0_454, n_1_0_455, n_1_0_456, n_1_0_457, n_1_0_458, n_1_0_459, + n_1_0_460, n_1_0_461, n_1_0_462, n_1_0_463, n_1_0_464, n_1_0_465, + n_1_0_466, n_1_0_467, n_1_0_468, n_1_0_469, n_1_0_470, n_1_0_471, + n_1_0_472, n_1_0_473, n_1_0_474, n_1_0_475, n_1_0_476, n_1_0_477, + n_1_0_478, n_1_0_479, n_1_0_480, n_1_0_481, n_1_0_482, n_1_0_483, + n_1_0_484, n_1_0_485, n_1_0_486, n_1_0_487, n_1_0_488, n_1_0_489, + n_1_0_490, n_1_0_491, n_1_0_492, n_1_0_493, n_1_0_494, n_1_0_495, + n_1_0_496, n_1_0_497, n_1_0_498, n_1_0_499, n_1_0_500, n_1_0_501, + n_1_0_502, n_1_0_503, n_1_0_504, n_1_0_505, n_1_0_506, n_1_0_507, + n_1_0_508, n_1_0_509, n_1_0_510, n_1_0_511, n_1_0_512, n_1_0_513, + n_1_0_514, n_1_0_515, n_1_0_516, n_1_0_517, n_1_0_518, n_1_0_519, + n_1_0_520, n_1_0_521, n_1_0_522, n_1_0_523, n_1_0_524, n_1_0_525, + n_1_0_526, n_1_0_527, n_1_0_528, n_1_0_529, n_1_0_530, n_1_0_531, + n_1_0_532, n_1_0_533, n_1_0_534, n_1_0_535, n_1_0_536, n_1_0_537, + n_1_0_538, n_1_0_539, n_1_0_540, n_1_0_541, n_1_0_542, n_1_0_543, + n_1_0_544, n_1_0_545, n_1_0_546, n_1_0_547, n_1_0_548, n_1_0_549, + n_1_0_550, n_1_0_551, n_1_0_552, n_1_0_553, n_1_0_554, n_1_0_555, + n_1_0_556, n_1_0_557, n_1_0_558, n_1_0_559, n_1_0_560, n_1_0_561, + n_1_0_562, n_1_0_563, n_1_0_564, n_1_0_565, n_1_0_566, n_1_0_567, + n_1_0_568, n_1_0_569, n_1_0_570, n_1_0_571, n_1_0_572, n_1_0_573, + n_1_0_574, n_1_0_575, n_1_0_576, n_1_0_577, n_1_0_578, n_1_0_579, + n_1_0_580, n_1_0_581, n_1_0_582, n_1_0_583, n_1_0_584, n_1_0_585, + n_1_0_586, n_1_0_587, n_1_0_588, n_1_0_589, n_1_0_590, n_1_0_591, + n_1_0_592, n_1_0_593, n_1_0_594, n_1_0_595, n_1_0_596, n_1_0_597, + n_1_0_598, n_1_0_599, n_1_0_600, n_1_0_601, n_1_0_602, n_1_0_603, + n_1_0_604, n_1_0_605, n_1_0_606, n_1_0_607, n_1_0_608, n_1_0_609, + n_1_0_610, n_1_0_611, n_1_0_612, n_1_0_613, n_1_0_614, n_1_0_615, + n_1_0_616, n_1_0_617, n_1_0_618, n_1_0_619, n_1_0_620, n_1_0_621, + n_1_0_622, n_1_0_623, n_1_0_624, n_1_0_625, n_1_0_626, n_1_0_627, + n_1_0_628, n_1_0_629, n_1_0_630, n_1_0_631, n_1_0_632, n_1_0_633, + n_1_0_634, n_1_0_635, n_1_0_636, n_1_0_637, n_1_0_638, n_1_0_639, + n_1_0_640, n_1_0_641, n_1_0_642, n_1_0_643, n_1_0_644, n_1_0_645, + n_1_0_646, n_1_0_647, n_1_0_648, n_1_0_649, n_1_0_650, n_1_0_651, + n_1_0_652, n_1_0_653, n_1_0_654, n_1_0_655, n_1_0_656, n_1_0_657, + n_1_0_658, n_1_0_659, n_1_0_660, n_1_0_661, n_1_0_662, n_1_0_663, + n_1_0_664, n_1_0_665, n_1_0_666, n_1_0_667, n_1_0_668, n_1_0_669, + n_1_0_670, n_1_0_671, n_1_0_672, n_1_0_673, n_1_0_674, n_1_0_675, + n_1_0_676, n_1_0_677, n_1_0_678, n_1_0_679, n_1_0_680, n_1_0_681, + n_1_0_682, n_1_0_683, n_1_0_684, n_1_0_685, n_1_0_686, n_1_0_687, + n_1_0_688, n_1_0_689, n_1_0_690, n_1_0_691, n_1_0_692, n_1_0_693, + n_1_0_694, n_1_0_695, n_1_0_696, n_1_0_697, n_1_0_698, n_1_0_699, + n_1_0_700, n_1_0_701, n_1_0_702, n_1_0_703, n_1_0_704, n_1_0_705, + n_1_0_706, n_1_0_707, n_1_0_708, n_1_0_709, n_1_0_710, n_1_0_711, + n_1_0_712, n_1_0_713, n_1_0_714, n_1_0_715, n_1_0_716, n_1_0_717, + n_1_0_718, n_1_0_719, n_1_0_720, n_1_0_721, n_1_0_722, n_1_0_723, + n_1_0_724, n_1_0_725, n_1_0_726, n_1_0_727, n_1_0_728, n_1_0_729, + n_1_0_730, n_1_0_731, n_1_0_732, n_1_0_733, n_1_0_734, n_1_0_735, + n_1_0_736, n_1_0_737, n_1_0_738, n_1_0_739, n_1_0_740, n_1_0_741, + n_1_0_742, n_1_0_743, n_1_0_744, n_1_0_745, n_1_0_746, n_1_0_747, + n_1_0_748, n_1_0_749, n_1_0_750, n_1_0_751, n_1_0_752, n_1_0_753, + n_1_0_754, n_1_0_755, n_1_0_756, n_1_0_757, n_1_0_758, n_1_0_759, + n_1_0_760, n_1_0_761, n_1_0_762, n_1_0_763, n_1_0_764, n_1_0_765, + n_1_0_766, n_1_0_767, n_1_0_768, n_1_0_769, n_1_0_770, n_1_0_771, + n_1_0_772, n_1_0_773, n_1_0_774, n_1_0_775, n_1_0_776, n_1_0_777, + n_1_0_778, n_1_0_779, n_1_0_780, n_1_0_781, n_1_0_782, n_1_0_783, + n_1_0_784, n_1_0_785, n_1_0_786, n_1_0_787, n_1_0_788, n_1_0_789, + n_1_0_790, n_1_0_791, n_1_0_792, n_1_0_793, n_1_0_794, n_1_0_795, + n_1_0_796, n_1_0_797, n_1_0_798, n_1_0_799, n_1_0_800, n_1_0_801, + n_1_0_802, n_1_0_803, n_1_0_804, n_1_0_805, n_1_0_806, n_1_0_807, + n_1_0_808, n_1_0_809, n_1_0_810, n_1_0_811, n_1_0_812, n_1_0_813, + n_1_0_814, n_1_0_815, n_1_0_816, n_1_0_817, n_1_0_818, n_1_0_819, + n_1_0_820, n_1_0_821, n_1_0_822, n_1_0_823, n_1_0_824, n_1_0_825, + n_1_0_826, n_1_0_827, n_1_0_828, n_1_0_829, n_1_0_830, n_1_0_831, + n_1_0_832, n_1_0_833, n_1_0_834, n_1_0_835, n_1_0_836, n_1_0_837, + n_1_0_838, n_1_0_839, n_1_0_840, n_1_0_841, n_1_0_842, n_1_0_843, + n_1_0_844, n_1_0_845, n_1_0_846, n_1_0_847, n_1_0_848, n_1_0_849, + n_1_0_850, n_1_0_851, n_1_0_852, n_1_0_853, n_1_0_854, n_1_0_855, + n_1_0_856, n_1_0_857, n_1_0_858, n_1_0_859, n_1_0_860, n_1_0_861, + n_1_0_862, n_1_0_863, n_1_0_864, n_1_0_865, n_1_0_866, n_1_0_867, + n_1_0_868, n_1_0_869, n_1_0_870, n_1_0_871, n_1_0_872, n_1_0_873, + n_1_0_874, n_1_0_875, n_1_0_876, n_1_0_877, n_1_0_878, n_1_0_879, + n_1_0_880, n_1_0_881, n_1_0_882, n_1_0_883, n_1_0_884, n_1_0_885, + n_1_0_886, n_1_0_887, n_1_0_888, n_1_0_889, n_1_0_890, n_1_0_891, + n_1_0_892, n_1_0_893, n_1_0_894, n_1_0_895, n_1_0_896, n_1_0_897, + n_1_0_898, n_1_0_899, n_1_0_900, n_1_0_901, n_1_0_902, n_1_0_903, + n_1_0_904, n_1_0_905, n_1_0_906, n_1_0_907, n_1_0_908, n_1_0_909, + n_1_0_910, n_1_0_911, n_1_0_912, n_1_0_913, n_1_0_914, n_1_0_915, + n_1_0_916, n_1_0_917, n_1_0_918, n_1_0_919, n_1_0_920, n_1_0_921, + n_1_0_922, n_1_0_923, n_1_0_924, n_1_0_925, n_1_0_926, n_1_0_927, + n_1_0_928, n_1_0_929, n_1_0_930, n_1_0_931, n_1_0_932, n_1_0_933, + n_1_0_934, n_1_0_935, n_1_0_936, n_1_0_937, n_1_0_938, n_1_0_939, + n_1_0_940, n_1_0_941, n_1_0_942, n_1_0_943, n_1_0_944, n_1_0_945, + n_1_0_946, n_1_0_947, n_1_0_948, n_1_0_949, n_1_0_950, n_1_0_951, + n_1_0_952, n_1_0_953, n_1_0_954, n_1_0_955, n_1_0_956, n_1_0_957, + n_1_0_958, n_1_0_959, n_1_0_960, n_1_0_961, n_1_0_962, n_1_0_963, + n_1_0_964, n_1_0_965, n_1_0_966, n_1_0_967, n_1_0_968, n_1_0_969, + n_1_0_970, n_1_0_971, n_1_0_972, n_1_0_973, n_1_0_974, n_1_0_975, + n_1_0_976, n_1_0_977, n_1_0_978, n_1_0_979, n_1_0_980, n_1_0_981, + n_1_0_982, n_1_0_983, n_1_0_984, n_1_0_985, n_1_0_986, n_1_0_987, + n_1_0_988, n_1_0_989, n_1_0_990, n_1_0_991, n_1_0_992, n_1_0_993, + n_1_0_994, n_1_0_995, n_1_0_996, n_1_0_997, n_1_0_998, n_1_0_999, + n_1_0_1000, n_1_0_1001, n_1_0_1002, n_1_0_1003, n_1_0_1004, n_1_0_1005, + n_1_0_1006, n_1_0_1007, n_1_0_1008, n_1_0_1009, n_1_0_1010, n_1_0_1011, + n_1_0_1012, n_1_0_1013, n_1_0_1014, n_1_0_1015, n_1_0_1016, n_1_0_1017, + n_1_0_1018, n_1_0_1019, n_1_0_1020, n_1_0_1021, n_1_0_1022, n_1_0_1023, + n_1_0_1024, n_1_0_1025, n_1_0_1026, n_1_0_1027, n_1_0_1028, n_1_0_1029, + n_1_0_1030, n_1_0_1031, n_1_0_1032, n_1_0_1033, n_1_0_1034, n_1_0_1035, + n_1_0_1036, n_1_0_1037, n_1_0_1038, n_1_0_1039, n_1_0_1040, n_1_0_1041, + n_1_0_1042, n_1_0_1043, n_1_0_1044, n_1_0_1045, n_1_0_1046, n_1_0_1047, + n_1_0_1048, n_1_0_1049, n_1_0_1050, n_1_0_1051, n_1_0_1052, n_1_0_1053, + n_1_0_1054, n_1_0_1055, n_1_0_1056, n_1_0_1057, n_1_0_1058, n_1_0_1059, + n_1_0_1060, n_1_0_1061, n_1_0_1062, n_1_0_1063, n_1_0_1064, n_1_0_1065, + n_1_0_1066, n_1_0_1067, n_1_0_1068, n_1_0_1069, n_1_0_1070, n_1_0_1071, + n_1_0_1072, n_1_0_1073, n_1_0_1074, n_1_0_1075, n_1_0_1076, n_1_0_1077, + n_1_0_1078, n_1_0_1079, n_1_0_1080, n_1_0_1081, n_1_0_1082, n_1_0_1083, + n_1_0_1084, n_1_0_1085, n_1_0_1086, n_1_0_1087, n_1_0_1088, n_1_0_1089, + n_1_0_1090, n_1_0_1091, n_1_0_1092, n_1_0_1093, n_1_0_1094, n_1_0_1095, + n_1_0_1096, n_1_0_1097, n_1_0_1098, n_1_0_1099, n_1_0_1100, n_1_0_1101, + n_1_0_1102, n_1_0_1103, n_1_0_1104, n_1_0_1105, n_1_0_1106, n_1_0_1107, + n_1_0_1108, n_1_0_1109, n_1_0_1110, n_1_0_1111, n_1_0_1112, n_1_0_1113, + n_1_0_1114, n_1_0_1115, n_1_0_1116, n_1_0_1117, n_1_0_1118, n_1_0_1119, + n_1_0_1120, n_1_0_1121, n_1_0_1122, n_1_0_1123, n_1_0_1124, n_1_0_1125, + n_1_0_1126, n_1_0_1127, n_1_0_1128, n_1_0_1129, n_1_0_1130, n_1_0_1131, + n_1_0_1132, n_1_0_1133, n_1_0_1134, n_1_0_1135, n_1_0_1136, n_1_0_1137, + n_1_0_1138, n_1_0_1139, n_1_0_1140, n_1_0_1141, n_1_0_1142, n_1_0_1143, + n_1_0_1144, n_1_0_1145, n_1_0_1146, n_1_0_1147, n_1_0_1148, n_1_0_1149, + n_1_0_1150, n_1_0_1151, n_1_0_1152, n_1_0_1153, n_1_0_1154, n_1_0_1155, + n_1_0_1156, n_1_0_1157, n_1_0_1158, n_1_0_1159, n_1_0_1160, n_1_0_1161, + n_1_0_1162, n_1_0_1163, n_1_0_1164, n_1_0_1165, n_1_0_1166, n_1_0_1167, + n_1_0_1168, n_1_0_1169, n_1_0_1170, n_1_0_1171, n_1_0_1172, n_1_0_1173, + n_1_0_1174, n_1_0_1175, n_1_0_1176, n_1_0_1177, n_1_0_1178, n_1_0_1179, + n_1_0_1180, n_1_0_1181, n_1_0_1182, n_1_0_1183, n_1_0_1184, n_1_0_1185, + n_1_0_1186, n_1_0_1187, n_1_0_1188, n_1_0_1189, n_1_0_1190, n_1_0_1191, + n_1_0_1192, n_1_0_1193, n_1_0_1194, n_1_0_1195, n_1_0_1196, n_1_0_1197, + n_1_0_1198, n_1_0_1199, n_1_0_1200, n_1_0_1201, n_1_0_1202, n_1_0_1203, + n_1_0_1204, n_1_0_1205, n_1_0_1206, n_1_0_1207, n_1_0_1208, n_1_0_1209, + n_1_0_1210, n_1_0_1211, n_1_0_1212, n_1_0_1213, n_1_0_1214, n_1_0_1215, + n_1_0_1216, n_1_0_1217, n_1_0_1218, n_1_0_1219, n_1_0_1220, n_1_0_1221, + n_1_0_1222, n_1_0_1223, n_1_0_1224, n_1_0_1225, n_1_0_1226, n_1_0_1227, + n_1_0_1228, n_1_0_1229, n_1_0_1230, n_1_0_1231, n_1_0_1232, n_1_0_1233, + n_1_0_1234, n_1_0_1235, n_1_0_1236, n_1_0_1237, n_1_0_1238, n_1_0_1239, + n_1_0_1240, n_1_0_1241, n_1_0_1242, n_1_0_1243, n_1_0_1244, n_1_0_1245, + n_1_0_1246, n_1_0_1247, n_1_0_1248, n_1_0_1249, n_1_0_1250, n_1_0_1251, + n_1_0_1252, n_1_0_1253, n_1_0_1254, n_1_0_1255, n_1_0_1256, n_1_0_1257, + n_1_0_1258, n_1_0_1259, n_1_0_1260, n_1_0_1261, n_1_0_1262, n_1_0_1263, + n_1_0_1264, n_1_0_1265, n_1_0_1266, n_1_0_1267, n_1_0_1268, n_1_0_1269, + n_1_0_1270, n_1_0_1271, n_1_0_1272, n_1_0_1273, n_1_0_1274, n_1_0_1275, + n_1_0_1276, n_1_0_1277, n_1_0_1278, n_1_0_1279, n_1_0_1280, n_1_0_1281, + n_1_0_1282, n_1_0_1283, n_1_0_1284, n_1_0_1285, n_1_0_1286, n_1_0_1287, + n_1_0_1288, n_1_0_1289, n_1_0_1290, n_1_0_1291, n_1_0_1292, n_1_0_1293, + n_1_0_1294, n_1_0_1295, n_1_0_1296, n_1_0_1297, n_1_0_1298, n_1_0_1299, + n_1_0_1300, n_1_0_1301, n_1_0_1302, n_1_0_1303, n_1_0_1304, n_1_0_1305, + n_1_0_1306, n_1_0_1307, n_1_0_1308, n_1_0_1309, ts_pbuf_extsi1227_, + ts_pbuf_extsi1228_, ts_pbuf_extsi1226_; + + INV_X1_LVT i_0_0_79( + .A(reset), .ZN(n_0_0_16) + ); + AND2_X1_LVT i_0_0_31( + .A1(n_0_0_16), .A2(WRd[31]), .ZN(registers[31]) + ); + INV_X1_LVT i_0_0_81( + .A(Rd[1]), .ZN(n_0_0_18) + ); + INV_X1_LVT i_0_0_80( + .A(Rd[0]), .ZN(n_0_0_17) + ); + NAND3_X1_LVT i_0_0_69( + .A1(n_0_0_18), .A2(n_0_0_17), .A3(Rd[2]), .ZN(n_0_0_9) + ); + NAND3_X1_LVT i_0_0_41( + .A1(Rd[3]), .A2(WrReg), .A3(Rd[4]), .ZN(n_0_0_1) + ); + OAI21_X1_LVT i_0_0_35( + .A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_1), .ZN(n_0_28) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[28]_reg ( + .CK(clk), .E(n_0_28), .GCK(n_0_58), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[28][31] ( + .CK(n_0_58), .D(registers[31]), .Q(registers_28__ap[31]), .QN(), .SE(dftIn), + .SI(ts_pbuf_extsi1227_) + ); + INV_X1_LVT i_1_0_1370( + .A(Rs1[0]), .ZN(n_1_0_1306) + ); + NAND3_X1_LVT i_1_0_1354( + .A1(n_1_0_1306), .A2(Rs1[3]), .A3(Rs1[4]), .ZN(n_1_0_1290) + ); + INV_X1_LVT i_1_0_1373( + .A(Rs1[2]), .ZN(n_1_0_1309) + ); + OR2_X1_LVT i_1_0_1348( + .A1(n_1_0_1309), .A2(Rs1[1]), .ZN(n_1_0_1284) + ); + NOR2_X1_LVT i_1_0_1347( + .A1(n_1_0_1290), .A2(n_1_0_1284), .ZN(n_1_0_1283) + ); + NOR4_X1_LVT i_1_0_1342( + .A1(n_1_0_1284), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), .ZN(n_1_0_1278) + ); + INV_X1_LVT i_0_0_83( + .A(WrReg), .ZN(n_0_0_20) + ); + OR3_X1_LVT i_0_0_77( + .A1(n_0_0_20), .A2(Rd[4]), .A3(Rd[3]), .ZN(n_0_0_14) + ); + OAI21_X1_LVT i_0_0_68( + .A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_9), .ZN(n_0_4) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[4]_reg ( + .CK(clk), .E(n_0_4), .GCK(n_0_34), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[4][31] ( + .CK(n_0_34), .D(registers[31]), .Q(registers_4__ap[31]), .QN(), .SE(dftIn), + .SI(ts_pbuf_extsi1228_) + ); + AOI22_X1_LVT i_1_0_1320( + .A1(registers_28__ap[31]), .A2(n_1_0_1283), .B1(n_1_0_1278), .B2(registers_4__ap[31]), + .ZN(n_1_0_1256) + ); + NAND2_X1_LVT i_0_0_70( + .A1(n_0_0_18), .A2(n_0_0_17), .ZN(n_0_0_10) + ); + INV_X1_LVT i_0_0_82( + .A(Rd[4]), .ZN(n_0_0_19) + ); + OR3_X1_LVT i_0_0_51( + .A1(n_0_0_20), .A2(n_0_0_19), .A3(Rd[3]), .ZN(n_0_0_3) + ); + OR2_X1_LVT i_0_0_50( + .A1(n_0_0_3), .A2(Rd[2]), .ZN(n_0_0_2) + ); + OAI21_X1_LVT i_0_0_49( + .A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_2), .ZN(n_0_16) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[16]_reg ( + .CK(clk), .E(n_0_16), .GCK(n_0_46), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[16][31] ( + .CK(n_0_46), .D(registers[31]), .Q(registers_16__ap[31]), .QN(), .SE(dftIn), + .SI(ts_intno31) + ); + INV_X1_LVT i_1_0_1371( + .A(Rs1[3]), .ZN(n_1_0_1307) + ); + NAND3_X1_LVT i_1_0_1363( + .A1(n_1_0_1307), .A2(n_1_0_1306), .A3(Rs1[4]), .ZN(n_1_0_1299) + ); + OR2_X1_LVT i_1_0_1357( + .A1(Rs1[1]), .A2(Rs1[2]), .ZN(n_1_0_1293) + ); + NOR2_X1_LVT i_1_0_1331( + .A1(n_1_0_1299), .A2(n_1_0_1293), .ZN(n_1_0_1267) + ); + NAND2_X1_LVT i_1_0_1365( + .A1(Rs1[1]), .A2(Rs1[2]), .ZN(n_1_0_1301) + ); + NAND3_X1_LVT i_1_0_1344( + .A1(Rs1[4]), .A2(Rs1[3]), .A3(Rs1[0]), .ZN(n_1_0_1280) + ); + NOR2_X1_LVT i_1_0_1330( + .A1(n_1_0_1301), .A2(n_1_0_1280), .ZN(n_1_0_1266) + ); + NAND3_X1_LVT i_0_0_63( + .A1(Rd[2]), .A2(Rd[1]), .A3(Rd[0]), .ZN(n_0_0_6) + ); + OAI21_X1_LVT i_0_0_32( + .A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_1), .ZN(n_0_31) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[31]_reg ( + .CK(clk), .E(n_0_31), .GCK(n_0_61), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[31][31] ( + .CK(n_0_61), .D(registers[31]), .Q(registers_31__ap[31]), .QN(), .SE(dftIn), + .SI(registers_4__ap[31]) + ); + AOI22_X1_LVT i_1_0_1329( + .A1(registers_16__ap[31]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[31]), + .ZN(n_1_0_1265) + ); + NAND3_X1_LVT i_0_0_65( + .A1(n_0_0_17), .A2(Rd[1]), .A3(Rd[2]), .ZN(n_0_0_7) + ); + OAI21_X1_LVT i_0_0_64( + .A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_7), .ZN(n_0_6) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[6]_reg ( + .CK(clk), .E(n_0_6), .GCK(n_0_36), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[6][31] ( + .CK(n_0_36), .D(registers[31]), .Q(registers_6__ap[31]), .QN(), .SE(dftIn), + .SI(registers_31__ap[31]) + ); + NOR4_X1_LVT i_1_0_1364( + .A1(n_1_0_1301), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), .ZN(n_1_0_1300) + ); + INV_X1_LVT i_1_0_1372( + .A(Rs1[4]), .ZN(n_1_0_1308) + ); + NAND3_X1_LVT i_1_0_1339( + .A1(n_1_0_1308), .A2(n_1_0_1307), .A3(Rs1[0]), .ZN(n_1_0_1275) + ); + NOR2_X1_LVT i_1_0_1338( + .A1(n_1_0_1293), .A2(n_1_0_1275), .ZN(n_1_0_1274) + ); + NAND2_X1_LVT i_0_0_78( + .A1(n_0_0_18), .A2(Rd[0]), .ZN(n_0_0_15) + ); + OR2_X1_LVT i_0_0_76( + .A1(n_0_0_14), .A2(Rd[2]), .ZN(n_0_0_13) + ); + OAI21_X1_LVT i_0_0_75( + .A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_13), .ZN(n_0_1) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[1]_reg ( + .CK(clk), .E(n_0_1), .GCK(n_0_0), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[1][31] ( + .CK(n_0_0), .D(registers[31]), .Q(registers_1__ap[31]), .QN(), .SE(dftIn), + .SI(ts_pbuf_extsi1226_) + ); + AOI22_X1_LVT i_1_0_1319( + .A1(registers_6__ap[31]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[31]), + .ZN(n_1_0_1255) + ); + OAI21_X1_LVT i_0_0_42( + .A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_3), .ZN(n_0_23) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[23]_reg ( + .CK(clk), .E(n_0_23), .GCK(n_0_53), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[23][31] ( + .CK(n_0_53), .D(registers[31]), .Q(registers_23__ap[31]), .QN(), .SE(dftIn), + .SI(registers_1__ap[31]) + ); + NAND3_X1_LVT i_1_0_1360( + .A1(n_1_0_1307), .A2(Rs1[0]), .A3(Rs1[4]), .ZN(n_1_0_1296) + ); + NOR2_X1_LVT i_1_0_1328( + .A1(n_1_0_1301), .A2(n_1_0_1296), .ZN(n_1_0_1264) + ); + NOR2_X1_LVT i_1_0_1327( + .A1(n_1_0_1301), .A2(n_1_0_1275), .ZN(n_1_0_1263) + ); + OAI21_X1_LVT i_0_0_62( + .A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_6), .ZN(n_0_7) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[7]_reg ( + .CK(clk), .E(n_0_7), .GCK(n_0_37), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[7][31] ( + .CK(n_0_37), .D(registers[31]), .Q(registers_7__ap[31]), .QN(), .SE(dftIn), + .SI(registers_6__ap[31]) + ); + AOI22_X1_LVT i_1_0_1326( + .A1(registers_23__ap[31]), .A2(n_1_0_1264), .B1(n_1_0_1263), .B2(registers_7__ap[31]), + .ZN(n_1_0_1262) + ); + INV_X1_LVT i_1_0_1325( + .A(n_1_0_1262), .ZN(n_1_0_1261) + ); + NAND2_X1_LVT i_1_0_1362( + .A1(n_1_0_1309), .A2(Rs1[1]), .ZN(n_1_0_1298) + ); + NOR2_X1_LVT i_1_0_1359( + .A1(n_1_0_1298), .A2(n_1_0_1296), .ZN(n_1_0_1295) + ); + NAND2_X1_LVT i_0_0_72( + .A1(Rd[1]), .A2(Rd[0]), .ZN(n_0_0_11) + ); + OAI21_X1_LVT i_0_0_46( + .A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_2), .ZN(n_0_19) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[19]_reg ( + .CK(clk), .E(n_0_19), .GCK(n_0_49), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[19][31] ( + .CK(n_0_49), .D(registers[31]), .Q(registers_19__ap[31]), .QN(), .SE(dftIn), + .SI(registers_23__ap[31]) + ); + NAND3_X1_LVT i_0_0_67( + .A1(n_0_0_18), .A2(Rd[0]), .A3(Rd[2]), .ZN(n_0_0_8) + ); + OAI21_X1_LVT i_0_0_66( + .A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_8), .ZN(n_0_5) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[5]_reg ( + .CK(clk), .E(n_0_5), .GCK(n_0_35), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[5][31] ( + .CK(n_0_35), .D(registers[31]), .Q(registers_5__ap[31]), .QN(), .SE(dftIn), + .SI(registers_7__ap[31]) + ); + NOR2_X1_LVT i_1_0_1337( + .A1(n_1_0_1284), .A2(n_1_0_1275), .ZN(n_1_0_1273) + ); + AOI221_X1_LVT i_1_0_1318( + .A(n_1_0_1261), .B1(n_1_0_1295), .B2(registers_19__ap[31]), .C1(registers_5__ap[31]), + .C2(n_1_0_1273), .ZN(n_1_0_1254) + ); + NAND2_X1_LVT i_0_0_74( + .A1(n_0_0_17), .A2(Rd[1]), .ZN(n_0_0_12) + ); + NAND3_X1_LVT i_0_0_61( + .A1(n_0_0_19), .A2(WrReg), .A3(Rd[3]), .ZN(n_0_0_5) + ); + OR2_X1_LVT i_0_0_60( + .A1(n_0_0_5), .A2(Rd[2]), .ZN(n_0_0_4) + ); + OAI21_X1_LVT i_0_0_57( + .A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_4), .ZN(n_0_10) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[10]_reg ( + .CK(clk), .E(n_0_10), .GCK(n_0_40), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[10][31] ( + .CK(n_0_40), .D(registers[31]), .Q(registers_10__ap[31]), .QN(), .SE(dftIn), + .SI(registers_16__ap[31]) + ); + NAND3_X1_LVT i_1_0_1352( + .A1(n_1_0_1308), .A2(n_1_0_1306), .A3(Rs1[3]), .ZN(n_1_0_1288) + ); + NOR2_X1_LVT i_1_0_1351( + .A1(n_1_0_1298), .A2(n_1_0_1288), .ZN(n_1_0_1287) + ); + NOR2_X1_LVT i_1_0_1349( + .A1(n_1_0_1298), .A2(n_1_0_1290), .ZN(n_1_0_1285) + ); + OR2_X1_LVT i_0_0_40( + .A1(n_0_0_1), .A2(Rd[2]), .ZN(n_0_0_0) + ); + OAI21_X1_LVT i_0_0_37( + .A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_0), .ZN(n_0_26) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[26]_reg ( + .CK(clk), .E(n_0_26), .GCK(n_0_56), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[26][31] ( + .CK(n_0_56), .D(registers[31]), .Q(registers_26__ap[31]), .QN(), .SE(dftIn), + .SI(registers_28__ap[31]) + ); + OAI21_X1_LVT i_0_0_59( + .A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_4), .ZN(n_0_8) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[8]_reg ( + .CK(clk), .E(n_0_8), .GCK(n_0_38), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[8][31] ( + .CK(n_0_38), .D(registers[31]), .Q(registers_8__ap[31]), .QN(), .SE(dftIn), + .SI(registers_5__ap[31]) + ); + NOR2_X1_LVT i_1_0_1346( + .A1(n_1_0_1293), .A2(n_1_0_1288), .ZN(n_1_0_1282) + ); + AOI222_X1_LVT i_1_0_1317( + .A1(registers_10__ap[31]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[31]), + .C1(registers_8__ap[31]), .C2(n_1_0_1282), .ZN(n_1_0_1253) + ); + NAND4_X1_LVT i_1_0_1316( + .A1(n_1_0_1265), .A2(n_1_0_1255), .A3(n_1_0_1254), .A4(n_1_0_1253), .ZN(n_1_0_1252) + ); + NAND3_X1_LVT i_1_0_1356( + .A1(n_1_0_1308), .A2(Rs1[3]), .A3(Rs1[0]), .ZN(n_1_0_1292) + ); + NOR2_X1_LVT i_1_0_1355( + .A1(n_1_0_1293), .A2(n_1_0_1292), .ZN(n_1_0_1291) + ); + OAI21_X1_LVT i_0_0_58( + .A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_4), .ZN(n_0_9) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[9]_reg ( + .CK(clk), .E(n_0_9), .GCK(n_0_39), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[9][31] ( + .CK(n_0_39), .D(registers[31]), .Q(registers_9__ap[31]), .QN(), .SE(dftIn), + .SI(registers_8__ap[31]) + ); + OAI21_X1_LVT i_0_0_34( + .A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_1), .ZN(n_0_29) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[29]_reg ( + .CK(clk), .E(n_0_29), .GCK(n_0_59), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[29][31] ( + .CK(n_0_59), .D(registers[31]), .Q(registers_29__ap[31]), .QN(), .SE(dftIn), + .SI(registers_26__ap[31]) + ); + NOR2_X1_LVT i_1_0_1340( + .A1(n_1_0_1284), .A2(n_1_0_1280), .ZN(n_1_0_1276) + ); + AOI221_X1_LVT i_1_0_1315( + .A(n_1_0_1252), .B1(n_1_0_1291), .B2(registers_9__ap[31]), .C1(registers_29__ap[31]), + .C2(n_1_0_1276), .ZN(n_1_0_1251) + ); + OAI21_X1_LVT i_0_0_47( + .A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_2), .ZN(n_0_18) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[18]_reg ( + .CK(clk), .E(n_0_18), .GCK(n_0_48), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[18][31] ( + .CK(n_0_48), .D(registers[31]), .Q(registers_18__ap[31]), .QN(), .SE(dftIn), + .SI(registers_19__ap[31]) + ); + NOR2_X1_LVT i_1_0_1361( + .A1(n_1_0_1299), .A2(n_1_0_1298), .ZN(n_1_0_1297) + ); + NOR2_X1_LVT i_1_0_1336( + .A1(n_1_0_1301), .A2(n_1_0_1290), .ZN(n_1_0_1272) + ); + OAI21_X1_LVT i_0_0_33( + .A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_1), .ZN(n_0_30) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[30]_reg ( + .CK(clk), .E(n_0_30), .GCK(n_0_60), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[30][31] ( + .CK(n_0_60), .D(registers[31]), .Q(registers_30__ap[31]), .QN(), .SE(dftIn), + .SI(registers_29__ap[31]) + ); + AOI22_X1_LVT i_1_0_1314( + .A1(registers_18__ap[31]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[31]), + .ZN(n_1_0_1250) + ); + OAI21_X1_LVT i_0_0_39( + .A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_0), .ZN(n_0_24) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[24]_reg ( + .CK(clk), .E(n_0_24), .GCK(n_0_54), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[24][31] ( + .CK(n_0_54), .D(registers[31]), .Q(registers_24__ap[31]), .QN(), .SE(dftIn), + .SI(registers_30__ap[31]) + ); + NOR2_X1_LVT i_1_0_1353( + .A1(n_1_0_1293), .A2(n_1_0_1290), .ZN(n_1_0_1289) + ); + NOR2_X1_LVT i_1_0_1324( + .A1(n_1_0_1288), .A2(n_1_0_1284), .ZN(n_1_0_1260) + ); + OAI21_X1_LVT i_0_0_55( + .A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_5), .ZN(n_0_12) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[12]_reg ( + .CK(clk), .E(n_0_12), .GCK(n_0_42), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[12][31] ( + .CK(n_0_42), .D(registers[31]), .Q(registers_12__ap[31]), .QN(), .SE(dftIn), + .SI(registers_10__ap[31]) + ); + AOI22_X1_LVT i_1_0_1313( + .A1(registers_24__ap[31]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[31]), + .ZN(n_1_0_1249) + ); + OAI21_X1_LVT i_0_0_43( + .A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_3), .ZN(n_0_22) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[22]_reg ( + .CK(clk), .E(n_0_22), .GCK(n_0_52), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[22][31] ( + .CK(n_0_52), .D(registers[31]), .Q(registers_22__ap[31]), .QN(), .SE(dftIn), + .SI(registers_18__ap[31]) + ); + NOR2_X1_LVT i_1_0_1358( + .A1(n_1_0_1301), .A2(n_1_0_1299), .ZN(n_1_0_1294) + ); + NOR2_X1_LVT i_1_0_1323( + .A1(n_1_0_1296), .A2(n_1_0_1284), .ZN(n_1_0_1259) + ); + OAI21_X1_LVT i_0_0_44( + .A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_3), .ZN(n_0_21) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[21]_reg ( + .CK(clk), .E(n_0_21), .GCK(n_0_51), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[21][31] ( + .CK(n_0_51), .D(registers[31]), .Q(registers_21__ap[31]), .QN(), .SE(dftIn), + .SI(registers_22__ap[31]) + ); + AOI22_X1_LVT i_1_0_1312( + .A1(registers_22__ap[31]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[31]), + .ZN(n_1_0_1248) + ); + NAND3_X1_LVT i_1_0_1311( + .A1(n_1_0_1250), .A2(n_1_0_1249), .A3(n_1_0_1248), .ZN(n_1_0_1247) + ); + NOR2_X1_LVT i_1_0_1335( + .A1(n_1_0_1296), .A2(n_1_0_1293), .ZN(n_1_0_1271) + ); + OAI21_X1_LVT i_0_0_48( + .A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_2), .ZN(n_0_17) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[17]_reg ( + .CK(clk), .E(n_0_17), .GCK(n_0_47), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[17][31] ( + .CK(n_0_47), .D(registers[31]), .Q(registers_17__ap[31]), .QN(), .SE(dftIn), + .SI(registers_21__ap[31]) + ); + OAI21_X1_LVT i_0_0_45( + .A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_3), .ZN(n_0_20) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[20]_reg ( + .CK(clk), .E(n_0_20), .GCK(n_0_50), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[20][31] ( + .CK(n_0_50), .D(registers[31]), .Q(registers_20__ap[31]), .QN(), .SE(dftIn), + .SI(registers_17__ap[31]) + ); + NOR2_X1_LVT i_1_0_1345( + .A1(n_1_0_1299), .A2(n_1_0_1284), .ZN(n_1_0_1281) + ); + AOI221_X1_LVT i_1_0_1310( + .A(n_1_0_1247), .B1(n_1_0_1271), .B2(registers_17__ap[31]), .C1(registers_20__ap[31]), + .C2(n_1_0_1281), .ZN(n_1_0_1246) + ); + OAI21_X1_LVT i_0_0_36( + .A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_0), .ZN(n_0_27) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[27]_reg ( + .CK(clk), .E(n_0_27), .GCK(n_0_57), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[27][31] ( + .CK(n_0_57), .D(registers[31]), .Q(registers_27__ap[31]), .QN(), .SE(dftIn), + .SI(registers_24__ap[31]) + ); + NOR2_X1_LVT i_1_0_1343( + .A1(n_1_0_1298), .A2(n_1_0_1280), .ZN(n_1_0_1279) + ); + NOR2_X1_LVT i_1_0_1334( + .A1(n_1_0_1298), .A2(n_1_0_1292), .ZN(n_1_0_1270) + ); + OAI21_X1_LVT i_0_0_56( + .A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_4), .ZN(n_0_11) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[11]_reg ( + .CK(clk), .E(n_0_11), .GCK(n_0_41), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[11][31] ( + .CK(n_0_41), .D(registers[31]), .Q(registers_11__ap[31]), .QN(), .SE(dftIn), + .SI(registers_12__ap[31]) + ); + AOI22_X1_LVT i_1_0_1309( + .A1(registers_27__ap[31]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[31]), + .ZN(n_1_0_1245) + ); + OAI21_X1_LVT i_0_0_54( + .A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_5), .ZN(n_0_13) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[13]_reg ( + .CK(clk), .E(n_0_13), .GCK(n_0_43), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[13][31] ( + .CK(n_0_43), .D(registers[31]), .Q(registers_13__ap[31]), .QN(), .SE(dftIn), + .SI(registers_11__ap[31]) + ); + NOR2_X1_LVT i_1_0_1341( + .A1(n_1_0_1292), .A2(n_1_0_1284), .ZN(n_1_0_1277) + ); + NOR2_X1_LVT i_1_0_1333( + .A1(n_1_0_1293), .A2(n_1_0_1280), .ZN(n_1_0_1269) + ); + OAI21_X1_LVT i_0_0_38( + .A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_0), .ZN(n_0_25) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[25]_reg ( + .CK(clk), .E(n_0_25), .GCK(n_0_55), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[25][31] ( + .CK(n_0_55), .D(registers[31]), .Q(registers_25__ap[31]), .QN(), .SE(dftIn), + .SI(registers_27__ap[31]) + ); + AOI22_X1_LVT i_1_0_1308( + .A1(registers_13__ap[31]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[31]), + .ZN(n_1_0_1244) + ); + OAI21_X1_LVT i_0_0_52( + .A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_5), .ZN(n_0_15) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[15]_reg ( + .CK(clk), .E(n_0_15), .GCK(n_0_45), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[15][31] ( + .CK(n_0_45), .D(registers[31]), .Q(registers_15__ap[31]), .QN(), .SE(dftIn), + .SI(registers_13__ap[31]) + ); + NOR2_X1_LVT i_1_0_1350( + .A1(n_1_0_1301), .A2(n_1_0_1292), .ZN(n_1_0_1286) + ); + NOR2_X1_LVT i_1_0_1322( + .A1(n_1_0_1301), .A2(n_1_0_1288), .ZN(n_1_0_1258) + ); + OAI21_X1_LVT i_0_0_53( + .A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_5), .ZN(n_0_14) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[14]_reg ( + .CK(clk), .E(n_0_14), .GCK(n_0_44), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[14][31] ( + .CK(n_0_44), .D(registers[31]), .Q(registers_14__ap[31]), .QN(), .SE(dftIn), + .SI(registers_15__ap[31]) + ); + AOI22_X1_LVT i_1_0_1307( + .A1(registers_15__ap[31]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[31]), + .ZN(n_1_0_1243) + ); + NAND3_X1_LVT i_1_0_1306( + .A1(n_1_0_1245), .A2(n_1_0_1244), .A3(n_1_0_1243), .ZN(n_1_0_1242) + ); + NOR2_X1_LVT i_1_0_1321( + .A1(n_1_0_1298), .A2(n_1_0_1275), .ZN(n_1_0_1257) + ); + OAI21_X1_LVT i_0_0_71( + .A(n_0_0_16), .B1(n_0_0_13), .B2(n_0_0_11), .ZN(n_0_3) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[3]_reg ( + .CK(clk), .E(n_0_3), .GCK(n_0_33), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[3][31] ( + .CK(n_0_33), .D(registers[31]), .Q(registers_3__ap[31]), .QN(), .SE(dftIn), + .SI(registers_9__ap[31]) + ); + OAI21_X1_LVT i_0_0_73( + .A(n_0_0_16), .B1(n_0_0_13), .B2(n_0_0_12), .ZN(n_0_2) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[2]_reg ( + .CK(clk), .E(n_0_2), .GCK(n_0_32), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[2][31] ( + .CK(n_0_32), .D(registers[31]), .Q(registers_2__ap[31]), .QN(), .SE(dftIn), + .SI(registers_25__ap[31]) + ); + NOR4_X1_LVT i_1_0_1332( + .A1(n_1_0_1298), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), .ZN(n_1_0_1268) + ); + AOI221_X1_LVT i_1_0_1305( + .A(n_1_0_1242), .B1(n_1_0_1257), .B2(registers_3__ap[31]), .C1(registers_2__ap[31]), + .C2(n_1_0_1268), .ZN(n_1_0_1241) + ); + NAND4_X1_LVT i_1_0_1304( + .A1(n_1_0_1256), .A2(n_1_0_1251), .A3(n_1_0_1246), .A4(n_1_0_1241), .ZN(RRs1[31]) + ); + AND2_X1_LVT i_0_0_30( + .A1(n_0_0_16), .A2(WRd[30]), .ZN(registers[30]) + ); + SDFF_X1_LVT \registers_reg[28][30] ( + .CK(n_0_58), .D(registers[30]), .Q(registers_28__ap[30]), .QN(), .SE(dftIn), + .SI(registers_2__ap[31]) + ); + SDFF_X1_LVT \registers_reg[17][30] ( + .CK(n_0_47), .D(registers[30]), .Q(registers_17__ap[30]), .QN(), .SE(dftIn), + .SI(registers_20__ap[31]) + ); + AOI22_X1_LVT i_1_0_1300( + .A1(registers_28__ap[30]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[30]), + .ZN(n_1_0_1237) + ); + SDFF_X1_LVT \registers_reg[16][30] ( + .CK(n_0_46), .D(registers[30]), .Q(registers_16__ap[30]), .QN(), .SE(dftIn), + .SI(registers_14__ap[31]) + ); + SDFF_X1_LVT \registers_reg[31][30] ( + .CK(n_0_61), .D(registers[30]), .Q(registers_31__ap[30]), .QN(), .SE(dftIn), + .SI(registers_3__ap[31]) + ); + AOI22_X1_LVT i_1_0_1303( + .A1(registers_16__ap[30]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[30]), + .ZN(n_1_0_1240) + ); + SDFF_X1_LVT \registers_reg[6][30] ( + .CK(n_0_36), .D(registers[30]), .Q(registers_6__ap[30]), .QN(), .SE(dftIn), + .SI(registers_31__ap[30]) + ); + SDFF_X1_LVT \registers_reg[1][30] ( + .CK(n_0_0), .D(registers[30]), .Q(registers_1__ap[30]), .QN(), .SE(dftIn), + .SI(registers_17__ap[30]) + ); + AOI22_X1_LVT i_1_0_1299( + .A1(registers_6__ap[30]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[30]), + .ZN(n_1_0_1236) + ); + SDFF_X1_LVT \registers_reg[23][30] ( + .CK(n_0_53), .D(registers[30]), .Q(registers_23__ap[30]), .QN(), .SE(dftIn), + .SI(registers_1__ap[30]) + ); + SDFF_X1_LVT \registers_reg[7][30] ( + .CK(n_0_37), .D(registers[30]), .Q(registers_7__ap[30]), .QN(), .SE(dftIn), + .SI(registers_6__ap[30]) + ); + AOI22_X1_LVT i_1_0_1302( + .A1(registers_23__ap[30]), .A2(n_1_0_1264), .B1(n_1_0_1263), .B2(registers_7__ap[30]), + .ZN(n_1_0_1239) + ); + INV_X1_LVT i_1_0_1301( + .A(n_1_0_1239), .ZN(n_1_0_1238) + ); + SDFF_X1_LVT \registers_reg[19][30] ( + .CK(n_0_49), .D(registers[30]), .Q(registers_19__ap[30]), .QN(), .SE(dftIn), + .SI(registers_23__ap[30]) + ); + SDFF_X1_LVT \registers_reg[5][30] ( + .CK(n_0_35), .D(registers[30]), .Q(registers_5__ap[30]), .QN(), .SE(dftIn), + .SI(registers_7__ap[30]) + ); + AOI221_X1_LVT i_1_0_1298( + .A(n_1_0_1238), .B1(n_1_0_1295), .B2(registers_19__ap[30]), .C1(registers_5__ap[30]), + .C2(n_1_0_1273), .ZN(n_1_0_1235) + ); + SDFF_X1_LVT \registers_reg[10][30] ( + .CK(n_0_40), .D(registers[30]), .Q(registers_10__ap[30]), .QN(), .SE(dftIn), + .SI(registers_16__ap[30]) + ); + SDFF_X1_LVT \registers_reg[26][30] ( + .CK(n_0_56), .D(registers[30]), .Q(registers_26__ap[30]), .QN(), .SE(dftIn), + .SI(registers_28__ap[30]) + ); + SDFF_X1_LVT \registers_reg[8][30] ( + .CK(n_0_38), .D(registers[30]), .Q(registers_8__ap[30]), .QN(), .SE(dftIn), + .SI(registers_5__ap[30]) + ); + AOI222_X1_LVT i_1_0_1297( + .A1(registers_10__ap[30]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[30]), + .C1(registers_8__ap[30]), .C2(n_1_0_1282), .ZN(n_1_0_1234) + ); + NAND4_X1_LVT i_1_0_1296( + .A1(n_1_0_1240), .A2(n_1_0_1236), .A3(n_1_0_1235), .A4(n_1_0_1234), .ZN(n_1_0_1233) + ); + SDFF_X1_LVT \registers_reg[9][30] ( + .CK(n_0_39), .D(registers[30]), .Q(registers_9__ap[30]), .QN(), .SE(dftIn), + .SI(registers_8__ap[30]) + ); + SDFF_X1_LVT \registers_reg[29][30] ( + .CK(n_0_59), .D(registers[30]), .Q(registers_29__ap[30]), .QN(), .SE(dftIn), + .SI(registers_26__ap[30]) + ); + AOI221_X1_LVT i_1_0_1295( + .A(n_1_0_1233), .B1(n_1_0_1291), .B2(registers_9__ap[30]), .C1(registers_29__ap[30]), + .C2(n_1_0_1276), .ZN(n_1_0_1232) + ); + SDFF_X1_LVT \registers_reg[18][30] ( + .CK(n_0_48), .D(registers[30]), .Q(registers_18__ap[30]), .QN(), .SE(dftIn), + .SI(registers_19__ap[30]) + ); + SDFF_X1_LVT \registers_reg[30][30] ( + .CK(n_0_60), .D(registers[30]), .Q(registers_30__ap[30]), .QN(), .SE(dftIn), + .SI(registers_29__ap[30]) + ); + AOI22_X1_LVT i_1_0_1294( + .A1(registers_18__ap[30]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[30]), + .ZN(n_1_0_1231) + ); + SDFF_X1_LVT \registers_reg[20][30] ( + .CK(n_0_50), .D(registers[30]), .Q(registers_20__ap[30]), .QN(), .SE(dftIn), + .SI(registers_18__ap[30]) + ); + SDFF_X1_LVT \registers_reg[4][30] ( + .CK(n_0_34), .D(registers[30]), .Q(registers_4__ap[30]), .QN(), .SE(dftIn), + .SI(registers_9__ap[30]) + ); + AOI22_X1_LVT i_1_0_1293( + .A1(registers_20__ap[30]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[30]), + .ZN(n_1_0_1230) + ); + SDFF_X1_LVT \registers_reg[22][30] ( + .CK(n_0_52), .D(registers[30]), .Q(registers_22__ap[30]), .QN(), .SE(dftIn), + .SI(registers_20__ap[30]) + ); + SDFF_X1_LVT \registers_reg[21][30] ( + .CK(n_0_51), .D(registers[30]), .Q(registers_21__ap[30]), .QN(), .SE(dftIn), + .SI(registers_22__ap[30]) + ); + AOI22_X1_LVT i_1_0_1292( + .A1(registers_22__ap[30]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[30]), + .ZN(n_1_0_1229) + ); + NAND3_X1_LVT i_1_0_1291( + .A1(n_1_0_1231), .A2(n_1_0_1230), .A3(n_1_0_1229), .ZN(n_1_0_1228) + ); + SDFF_X1_LVT \registers_reg[24][30] ( + .CK(n_0_54), .D(registers[30]), .Q(registers_24__ap[30]), .QN(), .SE(dftIn), + .SI(registers_30__ap[30]) + ); + SDFF_X1_LVT \registers_reg[12][30] ( + .CK(n_0_42), .D(registers[30]), .Q(registers_12__ap[30]), .QN(), .SE(dftIn), + .SI(registers_10__ap[30]) + ); + AOI221_X1_LVT i_1_0_1290( + .A(n_1_0_1228), .B1(n_1_0_1289), .B2(registers_24__ap[30]), .C1(registers_12__ap[30]), + .C2(n_1_0_1260), .ZN(n_1_0_1227) + ); + SDFF_X1_LVT \registers_reg[27][30] ( + .CK(n_0_57), .D(registers[30]), .Q(registers_27__ap[30]), .QN(), .SE(dftIn), + .SI(registers_24__ap[30]) + ); + SDFF_X1_LVT \registers_reg[11][30] ( + .CK(n_0_41), .D(registers[30]), .Q(registers_11__ap[30]), .QN(), .SE(dftIn), + .SI(registers_12__ap[30]) + ); + AOI22_X1_LVT i_1_0_1289( + .A1(registers_27__ap[30]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[30]), + .ZN(n_1_0_1226) + ); + SDFF_X1_LVT \registers_reg[13][30] ( + .CK(n_0_43), .D(registers[30]), .Q(registers_13__ap[30]), .QN(), .SE(dftIn), + .SI(registers_11__ap[30]) + ); + SDFF_X1_LVT \registers_reg[25][30] ( + .CK(n_0_55), .D(registers[30]), .Q(registers_25__ap[30]), .QN(), .SE(dftIn), + .SI(registers_27__ap[30]) + ); + AOI22_X1_LVT i_1_0_1288( + .A1(registers_13__ap[30]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[30]), + .ZN(n_1_0_1225) + ); + SDFF_X1_LVT \registers_reg[15][30] ( + .CK(n_0_45), .D(registers[30]), .Q(registers_15__ap[30]), .QN(), .SE(dftIn), + .SI(registers_13__ap[30]) + ); + SDFF_X1_LVT \registers_reg[14][30] ( + .CK(n_0_44), .D(registers[30]), .Q(registers_14__ap[30]), .QN(), .SE(dftIn), + .SI(registers_15__ap[30]) + ); + AOI22_X1_LVT i_1_0_1287( + .A1(registers_15__ap[30]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[30]), + .ZN(n_1_0_1224) + ); + NAND3_X1_LVT i_1_0_1286( + .A1(n_1_0_1226), .A2(n_1_0_1225), .A3(n_1_0_1224), .ZN(n_1_0_1223) + ); + SDFF_X1_LVT \registers_reg[3][30] ( + .CK(n_0_33), .D(registers[30]), .Q(registers_3__ap[30]), .QN(), .SE(dftIn), + .SI(registers_4__ap[30]) + ); + SDFF_X1_LVT \registers_reg[2][30] ( + .CK(n_0_32), .D(registers[30]), .Q(registers_2__ap[30]), .QN(), .SE(dftIn), + .SI(registers_25__ap[30]) + ); + AOI221_X1_LVT i_1_0_1285( + .A(n_1_0_1223), .B1(n_1_0_1257), .B2(registers_3__ap[30]), .C1(registers_2__ap[30]), + .C2(n_1_0_1268), .ZN(n_1_0_1222) + ); + NAND4_X1_LVT i_1_0_1284( + .A1(n_1_0_1237), .A2(n_1_0_1232), .A3(n_1_0_1227), .A4(n_1_0_1222), .ZN(RRs1[30]) + ); + AND2_X1_LVT i_0_0_29( + .A1(n_0_0_16), .A2(WRd[29]), .ZN(registers[29]) + ); + SDFF_X1_LVT \registers_reg[28][29] ( + .CK(n_0_58), .D(registers[29]), .Q(registers_28__ap[29]), .QN(), .SE(dftIn), + .SI(registers_2__ap[30]) + ); + SDFF_X1_LVT \registers_reg[8][29] ( + .CK(n_0_38), .D(registers[29]), .Q(registers_8__ap[29]), .QN(), .SE(dftIn), + .SI(registers_3__ap[30]) + ); + AOI22_X1_LVT i_1_0_1282( + .A1(registers_28__ap[29]), .A2(n_1_0_1283), .B1(n_1_0_1282), .B2(registers_8__ap[29]), + .ZN(n_1_0_1220) + ); + SDFF_X1_LVT \registers_reg[31][29] ( + .CK(n_0_61), .D(registers[29]), .Q(registers_31__ap[29]), .QN(), .SE(dftIn), + .SI(registers_8__ap[29]) + ); + SDFF_X1_LVT \registers_reg[7][29] ( + .CK(n_0_37), .D(registers[29]), .Q(registers_7__ap[29]), .QN(), .SE(dftIn), + .SI(registers_31__ap[29]) + ); + AOI22_X1_LVT i_1_0_1283( + .A1(registers_31__ap[29]), .A2(n_1_0_1266), .B1(n_1_0_1263), .B2(registers_7__ap[29]), + .ZN(n_1_0_1221) + ); + SDFF_X1_LVT \registers_reg[24][29] ( + .CK(n_0_54), .D(registers[29]), .Q(registers_24__ap[29]), .QN(), .SE(dftIn), + .SI(registers_28__ap[29]) + ); + SDFF_X1_LVT \registers_reg[20][29] ( + .CK(n_0_50), .D(registers[29]), .Q(registers_20__ap[29]), .QN(), .SE(dftIn), + .SI(registers_21__ap[30]) + ); + AOI22_X1_LVT i_1_0_1281( + .A1(registers_24__ap[29]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[29]), + .ZN(n_1_0_1219) + ); + SDFF_X1_LVT \registers_reg[19][29] ( + .CK(n_0_49), .D(registers[29]), .Q(registers_19__ap[29]), .QN(), .SE(dftIn), + .SI(registers_20__ap[29]) + ); + SDFF_X1_LVT \registers_reg[4][29] ( + .CK(n_0_34), .D(registers[29]), .Q(registers_4__ap[29]), .QN(), .SE(dftIn), + .SI(registers_7__ap[29]) + ); + AOI22_X1_LVT i_1_0_1280( + .A1(registers_19__ap[29]), .A2(n_1_0_1295), .B1(n_1_0_1278), .B2(registers_4__ap[29]), + .ZN(n_1_0_1218) + ); + NAND3_X1_LVT i_1_0_1279( + .A1(n_1_0_1221), .A2(n_1_0_1219), .A3(n_1_0_1218), .ZN(n_1_0_1217) + ); + SDFF_X1_LVT \registers_reg[23][29] ( + .CK(n_0_53), .D(registers[29]), .Q(registers_23__ap[29]), .QN(), .SE(dftIn), + .SI(registers_19__ap[29]) + ); + SDFF_X1_LVT \registers_reg[29][29] ( + .CK(n_0_59), .D(registers[29]), .Q(registers_29__ap[29]), .QN(), .SE(dftIn), + .SI(registers_24__ap[29]) + ); + AOI221_X1_LVT i_1_0_1278( + .A(n_1_0_1217), .B1(n_1_0_1264), .B2(registers_23__ap[29]), .C1(registers_29__ap[29]), + .C2(n_1_0_1276), .ZN(n_1_0_1216) + ); + SDFF_X1_LVT \registers_reg[10][29] ( + .CK(n_0_40), .D(registers[29]), .Q(registers_10__ap[29]), .QN(), .SE(dftIn), + .SI(registers_14__ap[30]) + ); + SDFF_X1_LVT \registers_reg[26][29] ( + .CK(n_0_56), .D(registers[29]), .Q(registers_26__ap[29]), .QN(), .SE(dftIn), + .SI(registers_29__ap[29]) + ); + SDFF_X1_LVT \registers_reg[25][29] ( + .CK(n_0_55), .D(registers[29]), .Q(registers_25__ap[29]), .QN(), .SE(dftIn), + .SI(registers_26__ap[29]) + ); + AOI222_X1_LVT i_1_0_1277( + .A1(registers_10__ap[29]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[29]), + .C1(registers_25__ap[29]), .C2(n_1_0_1269), .ZN(n_1_0_1215) + ); + NAND3_X1_LVT i_1_0_1276( + .A1(n_1_0_1220), .A2(n_1_0_1216), .A3(n_1_0_1215), .ZN(n_1_0_1214) + ); + SDFF_X1_LVT \registers_reg[21][29] ( + .CK(n_0_51), .D(registers[29]), .Q(registers_21__ap[29]), .QN(), .SE(dftIn), + .SI(registers_23__ap[29]) + ); + SDFF_X1_LVT \registers_reg[13][29] ( + .CK(n_0_43), .D(registers[29]), .Q(registers_13__ap[29]), .QN(), .SE(dftIn), + .SI(registers_10__ap[29]) + ); + AOI221_X1_LVT i_1_0_1275( + .A(n_1_0_1214), .B1(n_1_0_1259), .B2(registers_21__ap[29]), .C1(registers_13__ap[29]), + .C2(n_1_0_1277), .ZN(n_1_0_1213) + ); + SDFF_X1_LVT \registers_reg[18][29] ( + .CK(n_0_48), .D(registers[29]), .Q(registers_18__ap[29]), .QN(), .SE(dftIn), + .SI(registers_21__ap[29]) + ); + SDFF_X1_LVT \registers_reg[30][29] ( + .CK(n_0_60), .D(registers[29]), .Q(registers_30__ap[29]), .QN(), .SE(dftIn), + .SI(registers_25__ap[29]) + ); + AOI22_X1_LVT i_1_0_1274( + .A1(registers_18__ap[29]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[29]), + .ZN(n_1_0_1212) + ); + SDFF_X1_LVT \registers_reg[17][29] ( + .CK(n_0_47), .D(registers[29]), .Q(registers_17__ap[29]), .QN(), .SE(dftIn), + .SI(registers_18__ap[29]) + ); + SDFF_X1_LVT \registers_reg[12][29] ( + .CK(n_0_42), .D(registers[29]), .Q(registers_12__ap[29]), .QN(), .SE(dftIn), + .SI(registers_13__ap[29]) + ); + AOI22_X1_LVT i_1_0_1273( + .A1(registers_17__ap[29]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[29]), + .ZN(n_1_0_1211) + ); + SDFF_X1_LVT \registers_reg[15][29] ( + .CK(n_0_45), .D(registers[29]), .Q(registers_15__ap[29]), .QN(), .SE(dftIn), + .SI(registers_12__ap[29]) + ); + SDFF_X1_LVT \registers_reg[16][29] ( + .CK(n_0_46), .D(registers[29]), .Q(registers_16__ap[29]), .QN(), .SE(dftIn), + .SI(registers_15__ap[29]) + ); + AOI22_X1_LVT i_1_0_1272( + .A1(registers_15__ap[29]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[29]), + .ZN(n_1_0_1210) + ); + NAND3_X1_LVT i_1_0_1271( + .A1(n_1_0_1212), .A2(n_1_0_1211), .A3(n_1_0_1210), .ZN(n_1_0_1209) + ); + SDFF_X1_LVT \registers_reg[22][29] ( + .CK(n_0_52), .D(registers[29]), .Q(registers_22__ap[29]), .QN(), .SE(dftIn), + .SI(registers_17__ap[29]) + ); + SDFF_X1_LVT \registers_reg[5][29] ( + .CK(n_0_35), .D(registers[29]), .Q(registers_5__ap[29]), .QN(), .SE(dftIn), + .SI(registers_4__ap[29]) + ); + AOI221_X1_LVT i_1_0_1270( + .A(n_1_0_1209), .B1(n_1_0_1294), .B2(registers_22__ap[29]), .C1(registers_5__ap[29]), + .C2(n_1_0_1273), .ZN(n_1_0_1208) + ); + SDFF_X1_LVT \registers_reg[9][29] ( + .CK(n_0_39), .D(registers[29]), .Q(registers_9__ap[29]), .QN(), .SE(dftIn), + .SI(registers_5__ap[29]) + ); + SDFF_X1_LVT \registers_reg[1][29] ( + .CK(n_0_0), .D(registers[29]), .Q(registers_1__ap[29]), .QN(), .SE(dftIn), + .SI(registers_22__ap[29]) + ); + AOI22_X1_LVT i_1_0_1269( + .A1(registers_9__ap[29]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[29]), + .ZN(n_1_0_1207) + ); + SDFF_X1_LVT \registers_reg[6][29] ( + .CK(n_0_36), .D(registers[29]), .Q(registers_6__ap[29]), .QN(), .SE(dftIn), + .SI(registers_9__ap[29]) + ); + SDFF_X1_LVT \registers_reg[14][29] ( + .CK(n_0_44), .D(registers[29]), .Q(registers_14__ap[29]), .QN(), .SE(dftIn), + .SI(registers_16__ap[29]) + ); + AOI22_X1_LVT i_1_0_1268( + .A1(registers_6__ap[29]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[29]), + .ZN(n_1_0_1206) + ); + SDFF_X1_LVT \registers_reg[27][29] ( + .CK(n_0_57), .D(registers[29]), .Q(registers_27__ap[29]), .QN(), .SE(dftIn), + .SI(registers_30__ap[29]) + ); + SDFF_X1_LVT \registers_reg[11][29] ( + .CK(n_0_41), .D(registers[29]), .Q(registers_11__ap[29]), .QN(), .SE(dftIn), + .SI(registers_14__ap[29]) + ); + AOI22_X1_LVT i_1_0_1267( + .A1(registers_27__ap[29]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[29]), + .ZN(n_1_0_1205) + ); + NAND3_X1_LVT i_1_0_1266( + .A1(n_1_0_1207), .A2(n_1_0_1206), .A3(n_1_0_1205), .ZN(n_1_0_1204) + ); + SDFF_X1_LVT \registers_reg[3][29] ( + .CK(n_0_33), .D(registers[29]), .Q(registers_3__ap[29]), .QN(), .SE(dftIn), + .SI(registers_6__ap[29]) + ); + SDFF_X1_LVT \registers_reg[2][29] ( + .CK(n_0_32), .D(registers[29]), .Q(registers_2__ap[29]), .QN(), .SE(dftIn), + .SI(registers_27__ap[29]) + ); + AOI221_X1_LVT i_1_0_1265( + .A(n_1_0_1204), .B1(n_1_0_1257), .B2(registers_3__ap[29]), .C1(registers_2__ap[29]), + .C2(n_1_0_1268), .ZN(n_1_0_1203) + ); + NAND3_X1_LVT i_1_0_1264( + .A1(n_1_0_1213), .A2(n_1_0_1208), .A3(n_1_0_1203), .ZN(RRs1[29]) + ); + AND2_X1_LVT i_0_0_28( + .A1(n_0_0_16), .A2(WRd[28]), .ZN(registers[28]) + ); + SDFF_X1_LVT \registers_reg[15][28] ( + .CK(n_0_45), .D(registers[28]), .Q(registers_15__ap[28]), .QN(), .SE(dftIn), + .SI(registers_11__ap[29]) + ); + SDFF_X1_LVT \registers_reg[26][28] ( + .CK(n_0_56), .D(registers[28]), .Q(registers_26__ap[28]), .QN(), .SE(dftIn), + .SI(registers_2__ap[29]) + ); + SDFF_X1_LVT \registers_reg[22][28] ( + .CK(n_0_52), .D(registers[28]), .Q(registers_22__ap[28]), .QN(), .SE(dftIn), + .SI(registers_1__ap[29]) + ); + AOI222_X1_LVT i_1_0_1263( + .A1(registers_15__ap[28]), .A2(n_1_0_1286), .B1(n_1_0_1285), .B2(registers_26__ap[28]), + .C1(registers_22__ap[28]), .C2(n_1_0_1294), .ZN(n_1_0_1202) + ); + SDFF_X1_LVT \registers_reg[5][28] ( + .CK(n_0_35), .D(registers[28]), .Q(registers_5__ap[28]), .QN(), .SE(dftIn), + .SI(registers_3__ap[29]) + ); + SDFF_X1_LVT \registers_reg[12][28] ( + .CK(n_0_42), .D(registers[28]), .Q(registers_12__ap[28]), .QN(), .SE(dftIn), + .SI(registers_15__ap[28]) + ); + AOI22_X1_LVT i_1_0_1262( + .A1(registers_5__ap[28]), .A2(n_1_0_1273), .B1(n_1_0_1260), .B2(registers_12__ap[28]), + .ZN(n_1_0_1201) + ); + SDFF_X1_LVT \registers_reg[28][28] ( + .CK(n_0_58), .D(registers[28]), .Q(registers_28__ap[28]), .QN(), .SE(dftIn), + .SI(registers_26__ap[28]) + ); + SDFF_X1_LVT \registers_reg[14][28] ( + .CK(n_0_44), .D(registers[28]), .Q(registers_14__ap[28]), .QN(), .SE(dftIn), + .SI(registers_12__ap[28]) + ); + AOI22_X1_LVT i_1_0_1261( + .A1(registers_28__ap[28]), .A2(n_1_0_1283), .B1(n_1_0_1258), .B2(registers_14__ap[28]), + .ZN(n_1_0_1200) + ); + SDFF_X1_LVT \registers_reg[17][28] ( + .CK(n_0_47), .D(registers[28]), .Q(registers_17__ap[28]), .QN(), .SE(dftIn), + .SI(registers_22__ap[28]) + ); + SDFF_X1_LVT \registers_reg[2][28] ( + .CK(n_0_32), .D(registers[28]), .Q(registers_2__ap[28]), .QN(), .SE(dftIn), + .SI(registers_28__ap[28]) + ); + AOI22_X1_LVT i_1_0_1260( + .A1(registers_17__ap[28]), .A2(n_1_0_1271), .B1(n_1_0_1268), .B2(registers_2__ap[28]), + .ZN(n_1_0_1199) + ); + NAND3_X1_LVT i_1_0_1259( + .A1(n_1_0_1201), .A2(n_1_0_1200), .A3(n_1_0_1199), .ZN(n_1_0_1198) + ); + SDFF_X1_LVT \registers_reg[9][28] ( + .CK(n_0_39), .D(registers[28]), .Q(registers_9__ap[28]), .QN(), .SE(dftIn), + .SI(registers_5__ap[28]) + ); + SDFF_X1_LVT \registers_reg[29][28] ( + .CK(n_0_59), .D(registers[28]), .Q(registers_29__ap[28]), .QN(), .SE(dftIn), + .SI(registers_2__ap[28]) + ); + AOI221_X1_LVT i_1_0_1258( + .A(n_1_0_1198), .B1(n_1_0_1291), .B2(registers_9__ap[28]), .C1(registers_29__ap[28]), + .C2(n_1_0_1276), .ZN(n_1_0_1197) + ); + SDFF_X1_LVT \registers_reg[13][28] ( + .CK(n_0_43), .D(registers[28]), .Q(registers_13__ap[28]), .QN(), .SE(dftIn), + .SI(registers_14__ap[28]) + ); + SDFF_X1_LVT \registers_reg[25][28] ( + .CK(n_0_55), .D(registers[28]), .Q(registers_25__ap[28]), .QN(), .SE(dftIn), + .SI(registers_29__ap[28]) + ); + AOI22_X1_LVT i_1_0_1257( + .A1(registers_13__ap[28]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[28]), + .ZN(n_1_0_1196) + ); + NAND3_X1_LVT i_1_0_1256( + .A1(n_1_0_1202), .A2(n_1_0_1197), .A3(n_1_0_1196), .ZN(n_1_0_1195) + ); + SDFF_X1_LVT \registers_reg[4][28] ( + .CK(n_0_34), .D(registers[28]), .Q(registers_4__ap[28]), .QN(), .SE(dftIn), + .SI(registers_9__ap[28]) + ); + SDFF_X1_LVT \registers_reg[20][28] ( + .CK(n_0_50), .D(registers[28]), .Q(registers_20__ap[28]), .QN(), .SE(dftIn), + .SI(registers_17__ap[28]) + ); + AOI221_X1_LVT i_1_0_1255( + .A(n_1_0_1195), .B1(n_1_0_1278), .B2(registers_4__ap[28]), .C1(registers_20__ap[28]), + .C2(n_1_0_1281), .ZN(n_1_0_1194) + ); + SDFF_X1_LVT \registers_reg[1][28] ( + .CK(n_0_0), .D(registers[28]), .Q(registers_1__ap[28]), .QN(), .SE(dftIn), + .SI(registers_20__ap[28]) + ); + SDFF_X1_LVT \registers_reg[23][28] ( + .CK(n_0_53), .D(registers[28]), .Q(registers_23__ap[28]), .QN(), .SE(dftIn), + .SI(registers_1__ap[28]) + ); + AOI22_X1_LVT i_1_0_1254( + .A1(registers_1__ap[28]), .A2(n_1_0_1274), .B1(n_1_0_1264), .B2(registers_23__ap[28]), + .ZN(n_1_0_1193) + ); + SDFF_X1_LVT \registers_reg[10][28] ( + .CK(n_0_40), .D(registers[28]), .Q(registers_10__ap[28]), .QN(), .SE(dftIn), + .SI(registers_13__ap[28]) + ); + SDFF_X1_LVT \registers_reg[21][28] ( + .CK(n_0_51), .D(registers[28]), .Q(registers_21__ap[28]), .QN(), .SE(dftIn), + .SI(registers_23__ap[28]) + ); + AOI22_X1_LVT i_1_0_1253( + .A1(registers_10__ap[28]), .A2(n_1_0_1287), .B1(n_1_0_1259), .B2(registers_21__ap[28]), + .ZN(n_1_0_1192) + ); + SDFF_X1_LVT \registers_reg[6][28] ( + .CK(n_0_36), .D(registers[28]), .Q(registers_6__ap[28]), .QN(), .SE(dftIn), + .SI(registers_4__ap[28]) + ); + SDFF_X1_LVT \registers_reg[30][28] ( + .CK(n_0_60), .D(registers[28]), .Q(registers_30__ap[28]), .QN(), .SE(dftIn), + .SI(registers_25__ap[28]) + ); + AOI22_X1_LVT i_1_0_1252( + .A1(registers_6__ap[28]), .A2(n_1_0_1300), .B1(n_1_0_1272), .B2(registers_30__ap[28]), + .ZN(n_1_0_1191) + ); + NAND3_X1_LVT i_1_0_1251( + .A1(n_1_0_1193), .A2(n_1_0_1192), .A3(n_1_0_1191), .ZN(n_1_0_1190) + ); + SDFF_X1_LVT \registers_reg[8][28] ( + .CK(n_0_38), .D(registers[28]), .Q(registers_8__ap[28]), .QN(), .SE(dftIn), + .SI(registers_6__ap[28]) + ); + SDFF_X1_LVT \registers_reg[24][28] ( + .CK(n_0_54), .D(registers[28]), .Q(registers_24__ap[28]), .QN(), .SE(dftIn), + .SI(registers_30__ap[28]) + ); + AOI221_X1_LVT i_1_0_1250( + .A(n_1_0_1190), .B1(n_1_0_1282), .B2(registers_8__ap[28]), .C1(registers_24__ap[28]), + .C2(n_1_0_1289), .ZN(n_1_0_1189) + ); + SDFF_X1_LVT \registers_reg[16][28] ( + .CK(n_0_46), .D(registers[28]), .Q(registers_16__ap[28]), .QN(), .SE(dftIn), + .SI(registers_10__ap[28]) + ); + SDFF_X1_LVT \registers_reg[3][28] ( + .CK(n_0_33), .D(registers[28]), .Q(registers_3__ap[28]), .QN(), .SE(dftIn), + .SI(registers_8__ap[28]) + ); + AOI22_X1_LVT i_1_0_1249( + .A1(registers_16__ap[28]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[28]), + .ZN(n_1_0_1188) + ); + SDFF_X1_LVT \registers_reg[11][28] ( + .CK(n_0_41), .D(registers[28]), .Q(registers_11__ap[28]), .QN(), .SE(dftIn), + .SI(registers_16__ap[28]) + ); + SDFF_X1_LVT \registers_reg[31][28] ( + .CK(n_0_61), .D(registers[28]), .Q(registers_31__ap[28]), .QN(), .SE(dftIn), + .SI(registers_3__ap[28]) + ); + AOI22_X1_LVT i_1_0_1248( + .A1(registers_11__ap[28]), .A2(n_1_0_1270), .B1(n_1_0_1266), .B2(registers_31__ap[28]), + .ZN(n_1_0_1187) + ); + SDFF_X1_LVT \registers_reg[27][28] ( + .CK(n_0_57), .D(registers[28]), .Q(registers_27__ap[28]), .QN(), .SE(dftIn), + .SI(registers_24__ap[28]) + ); + SDFF_X1_LVT \registers_reg[7][28] ( + .CK(n_0_37), .D(registers[28]), .Q(registers_7__ap[28]), .QN(), .SE(dftIn), + .SI(registers_31__ap[28]) + ); + AOI22_X1_LVT i_1_0_1247( + .A1(registers_27__ap[28]), .A2(n_1_0_1279), .B1(n_1_0_1263), .B2(registers_7__ap[28]), + .ZN(n_1_0_1186) + ); + NAND3_X1_LVT i_1_0_1246( + .A1(n_1_0_1188), .A2(n_1_0_1187), .A3(n_1_0_1186), .ZN(n_1_0_1185) + ); + SDFF_X1_LVT \registers_reg[19][28] ( + .CK(n_0_49), .D(registers[28]), .Q(registers_19__ap[28]), .QN(), .SE(dftIn), + .SI(registers_21__ap[28]) + ); + SDFF_X1_LVT \registers_reg[18][28] ( + .CK(n_0_48), .D(registers[28]), .Q(registers_18__ap[28]), .QN(), .SE(dftIn), + .SI(registers_19__ap[28]) + ); + AOI221_X1_LVT i_1_0_1245( + .A(n_1_0_1185), .B1(n_1_0_1295), .B2(registers_19__ap[28]), .C1(registers_18__ap[28]), + .C2(n_1_0_1297), .ZN(n_1_0_1184) + ); + NAND3_X1_LVT i_1_0_1244( + .A1(n_1_0_1194), .A2(n_1_0_1189), .A3(n_1_0_1184), .ZN(RRs1[28]) + ); + AND2_X1_LVT i_0_0_27( + .A1(n_0_0_16), .A2(WRd[27]), .ZN(registers[27]) + ); + SDFF_X1_LVT \registers_reg[29][27] ( + .CK(n_0_59), .D(registers[27]), .Q(registers_29__ap[27]), .QN(), .SE(dftIn), + .SI(registers_27__ap[28]) + ); + SDFF_X1_LVT \registers_reg[2][27] ( + .CK(n_0_32), .D(registers[27]), .Q(registers_2__ap[27]), .QN(), .SE(dftIn), + .SI(registers_29__ap[27]) + ); + AOI22_X1_LVT i_1_0_1242( + .A1(registers_29__ap[27]), .A2(n_1_0_1276), .B1(n_1_0_1268), .B2(registers_2__ap[27]), + .ZN(n_1_0_1182) + ); + SDFF_X1_LVT \registers_reg[8][27] ( + .CK(n_0_38), .D(registers[27]), .Q(registers_8__ap[27]), .QN(), .SE(dftIn), + .SI(registers_7__ap[28]) + ); + SDFF_X1_LVT \registers_reg[25][27] ( + .CK(n_0_55), .D(registers[27]), .Q(registers_25__ap[27]), .QN(), .SE(dftIn), + .SI(registers_2__ap[27]) + ); + AOI22_X1_LVT i_1_0_1243( + .A1(registers_8__ap[27]), .A2(n_1_0_1282), .B1(n_1_0_1269), .B2(registers_25__ap[27]), + .ZN(n_1_0_1183) + ); + SDFF_X1_LVT \registers_reg[9][27] ( + .CK(n_0_39), .D(registers[27]), .Q(registers_9__ap[27]), .QN(), .SE(dftIn), + .SI(registers_8__ap[27]) + ); + SDFF_X1_LVT \registers_reg[7][27] ( + .CK(n_0_37), .D(registers[27]), .Q(registers_7__ap[27]), .QN(), .SE(dftIn), + .SI(registers_9__ap[27]) + ); + AOI22_X1_LVT i_1_0_1241( + .A1(registers_9__ap[27]), .A2(n_1_0_1291), .B1(n_1_0_1263), .B2(registers_7__ap[27]), + .ZN(n_1_0_1181) + ); + SDFF_X1_LVT \registers_reg[11][27] ( + .CK(n_0_41), .D(registers[27]), .Q(registers_11__ap[27]), .QN(), .SE(dftIn), + .SI(registers_11__ap[28]) + ); + SDFF_X1_LVT \registers_reg[16][27] ( + .CK(n_0_46), .D(registers[27]), .Q(registers_16__ap[27]), .QN(), .SE(dftIn), + .SI(registers_11__ap[27]) + ); + AOI22_X1_LVT i_1_0_1240( + .A1(registers_11__ap[27]), .A2(n_1_0_1270), .B1(n_1_0_1267), .B2(registers_16__ap[27]), + .ZN(n_1_0_1180) + ); + NAND3_X1_LVT i_1_0_1239( + .A1(n_1_0_1183), .A2(n_1_0_1181), .A3(n_1_0_1180), .ZN(n_1_0_1179) + ); + SDFF_X1_LVT \registers_reg[10][27] ( + .CK(n_0_40), .D(registers[27]), .Q(registers_10__ap[27]), .QN(), .SE(dftIn), + .SI(registers_16__ap[27]) + ); + SDFF_X1_LVT \registers_reg[6][27] ( + .CK(n_0_36), .D(registers[27]), .Q(registers_6__ap[27]), .QN(), .SE(dftIn), + .SI(registers_7__ap[27]) + ); + AOI221_X1_LVT i_1_0_1238( + .A(n_1_0_1179), .B1(n_1_0_1287), .B2(registers_10__ap[27]), .C1(registers_6__ap[27]), + .C2(n_1_0_1300), .ZN(n_1_0_1178) + ); + SDFF_X1_LVT \registers_reg[1][27] ( + .CK(n_0_0), .D(registers[27]), .Q(registers_1__ap[27]), .QN(), .SE(dftIn), + .SI(registers_18__ap[28]) + ); + SDFF_X1_LVT \registers_reg[30][27] ( + .CK(n_0_60), .D(registers[27]), .Q(registers_30__ap[27]), .QN(), .SE(dftIn), + .SI(registers_25__ap[27]) + ); + SDFF_X1_LVT \registers_reg[22][27] ( + .CK(n_0_52), .D(registers[27]), .Q(registers_22__ap[27]), .QN(), .SE(dftIn), + .SI(registers_1__ap[27]) + ); + AOI222_X1_LVT i_1_0_1237( + .A1(registers_1__ap[27]), .A2(n_1_0_1274), .B1(n_1_0_1272), .B2(registers_30__ap[27]), + .C1(registers_22__ap[27]), .C2(n_1_0_1294), .ZN(n_1_0_1177) + ); + NAND3_X1_LVT i_1_0_1236( + .A1(n_1_0_1182), .A2(n_1_0_1178), .A3(n_1_0_1177), .ZN(n_1_0_1176) + ); + SDFF_X1_LVT \registers_reg[5][27] ( + .CK(n_0_35), .D(registers[27]), .Q(registers_5__ap[27]), .QN(), .SE(dftIn), + .SI(registers_6__ap[27]) + ); + SDFF_X1_LVT \registers_reg[28][27] ( + .CK(n_0_58), .D(registers[27]), .Q(registers_28__ap[27]), .QN(), .SE(dftIn), + .SI(registers_30__ap[27]) + ); + AOI221_X1_LVT i_1_0_1235( + .A(n_1_0_1176), .B1(n_1_0_1273), .B2(registers_5__ap[27]), .C1(registers_28__ap[27]), + .C2(n_1_0_1283), .ZN(n_1_0_1175) + ); + SDFF_X1_LVT \registers_reg[4][27] ( + .CK(n_0_34), .D(registers[27]), .Q(registers_4__ap[27]), .QN(), .SE(dftIn), + .SI(registers_5__ap[27]) + ); + SDFF_X1_LVT \registers_reg[12][27] ( + .CK(n_0_42), .D(registers[27]), .Q(registers_12__ap[27]), .QN(), .SE(dftIn), + .SI(registers_10__ap[27]) + ); + AOI22_X1_LVT i_1_0_1234( + .A1(registers_4__ap[27]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[27]), + .ZN(n_1_0_1174) + ); + SDFF_X1_LVT \registers_reg[19][27] ( + .CK(n_0_49), .D(registers[27]), .Q(registers_19__ap[27]), .QN(), .SE(dftIn), + .SI(registers_22__ap[27]) + ); + SDFF_X1_LVT \registers_reg[21][27] ( + .CK(n_0_51), .D(registers[27]), .Q(registers_21__ap[27]), .QN(), .SE(dftIn), + .SI(registers_19__ap[27]) + ); + AOI22_X1_LVT i_1_0_1233( + .A1(registers_19__ap[27]), .A2(n_1_0_1295), .B1(n_1_0_1259), .B2(registers_21__ap[27]), + .ZN(n_1_0_1173) + ); + SDFF_X1_LVT \registers_reg[24][27] ( + .CK(n_0_54), .D(registers[27]), .Q(registers_24__ap[27]), .QN(), .SE(dftIn), + .SI(registers_28__ap[27]) + ); + SDFF_X1_LVT \registers_reg[20][27] ( + .CK(n_0_50), .D(registers[27]), .Q(registers_20__ap[27]), .QN(), .SE(dftIn), + .SI(registers_21__ap[27]) + ); + AOI22_X1_LVT i_1_0_1232( + .A1(registers_24__ap[27]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[27]), + .ZN(n_1_0_1172) + ); + NAND3_X1_LVT i_1_0_1231( + .A1(n_1_0_1174), .A2(n_1_0_1173), .A3(n_1_0_1172), .ZN(n_1_0_1171) + ); + SDFF_X1_LVT \registers_reg[18][27] ( + .CK(n_0_48), .D(registers[27]), .Q(registers_18__ap[27]), .QN(), .SE(dftIn), + .SI(registers_20__ap[27]) + ); + SDFF_X1_LVT \registers_reg[26][27] ( + .CK(n_0_56), .D(registers[27]), .Q(registers_26__ap[27]), .QN(), .SE(dftIn), + .SI(registers_24__ap[27]) + ); + AOI221_X1_LVT i_1_0_1230( + .A(n_1_0_1171), .B1(n_1_0_1297), .B2(registers_18__ap[27]), .C1(registers_26__ap[27]), + .C2(n_1_0_1285), .ZN(n_1_0_1170) + ); + SDFF_X1_LVT \registers_reg[23][27] ( + .CK(n_0_53), .D(registers[27]), .Q(registers_23__ap[27]), .QN(), .SE(dftIn), + .SI(registers_18__ap[27]) + ); + SDFF_X1_LVT \registers_reg[3][27] ( + .CK(n_0_33), .D(registers[27]), .Q(registers_3__ap[27]), .QN(), .SE(dftIn), + .SI(registers_4__ap[27]) + ); + AOI22_X1_LVT i_1_0_1229( + .A1(registers_23__ap[27]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[27]), + .ZN(n_1_0_1169) + ); + SDFF_X1_LVT \registers_reg[13][27] ( + .CK(n_0_43), .D(registers[27]), .Q(registers_13__ap[27]), .QN(), .SE(dftIn), + .SI(registers_12__ap[27]) + ); + SDFF_X1_LVT \registers_reg[17][27] ( + .CK(n_0_47), .D(registers[27]), .Q(registers_17__ap[27]), .QN(), .SE(dftIn), + .SI(registers_23__ap[27]) + ); + AOI22_X1_LVT i_1_0_1228( + .A1(registers_13__ap[27]), .A2(n_1_0_1277), .B1(n_1_0_1271), .B2(registers_17__ap[27]), + .ZN(n_1_0_1168) + ); + SDFF_X1_LVT \registers_reg[15][27] ( + .CK(n_0_45), .D(registers[27]), .Q(registers_15__ap[27]), .QN(), .SE(dftIn), + .SI(registers_13__ap[27]) + ); + SDFF_X1_LVT \registers_reg[14][27] ( + .CK(n_0_44), .D(registers[27]), .Q(registers_14__ap[27]), .QN(), .SE(dftIn), + .SI(registers_15__ap[27]) + ); + AOI22_X1_LVT i_1_0_1227( + .A1(registers_15__ap[27]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[27]), + .ZN(n_1_0_1167) + ); + NAND3_X1_LVT i_1_0_1226( + .A1(n_1_0_1169), .A2(n_1_0_1168), .A3(n_1_0_1167), .ZN(n_1_0_1166) + ); + SDFF_X1_LVT \registers_reg[27][27] ( + .CK(n_0_57), .D(registers[27]), .Q(registers_27__ap[27]), .QN(), .SE(dftIn), + .SI(registers_26__ap[27]) + ); + SDFF_X1_LVT \registers_reg[31][27] ( + .CK(n_0_61), .D(registers[27]), .Q(registers_31__ap[27]), .QN(), .SE(dftIn), + .SI(registers_3__ap[27]) + ); + AOI221_X1_LVT i_1_0_1225( + .A(n_1_0_1166), .B1(n_1_0_1279), .B2(registers_27__ap[27]), .C1(registers_31__ap[27]), + .C2(n_1_0_1266), .ZN(n_1_0_1165) + ); + NAND3_X1_LVT i_1_0_1224( + .A1(n_1_0_1175), .A2(n_1_0_1170), .A3(n_1_0_1165), .ZN(RRs1[27]) + ); + AND2_X1_LVT i_0_0_26( + .A1(n_0_0_16), .A2(WRd[26]), .ZN(registers[26]) + ); + SDFF_X1_LVT \registers_reg[18][26] ( + .CK(n_0_48), .D(registers[26]), .Q(registers_18__ap[26]), .QN(), .SE(dftIn), + .SI(registers_17__ap[27]) + ); + SDFF_X1_LVT \registers_reg[22][26] ( + .CK(n_0_52), .D(registers[26]), .Q(registers_22__ap[26]), .QN(), .SE(dftIn), + .SI(registers_18__ap[26]) + ); + SDFF_X1_LVT \registers_reg[1][26] ( + .CK(n_0_0), .D(registers[26]), .Q(registers_1__ap[26]), .QN(), .SE(dftIn), + .SI(registers_22__ap[26]) + ); + AOI222_X1_LVT i_1_0_1223( + .A1(registers_18__ap[26]), .A2(n_1_0_1297), .B1(n_1_0_1294), .B2(registers_22__ap[26]), + .C1(registers_1__ap[26]), .C2(n_1_0_1274), .ZN(n_1_0_1164) + ); + SDFF_X1_LVT \registers_reg[29][26] ( + .CK(n_0_59), .D(registers[26]), .Q(registers_29__ap[26]), .QN(), .SE(dftIn), + .SI(registers_27__ap[27]) + ); + SDFF_X1_LVT \registers_reg[2][26] ( + .CK(n_0_32), .D(registers[26]), .Q(registers_2__ap[26]), .QN(), .SE(dftIn), + .SI(registers_29__ap[26]) + ); + AOI22_X1_LVT i_1_0_1222( + .A1(registers_29__ap[26]), .A2(n_1_0_1276), .B1(n_1_0_1268), .B2(registers_2__ap[26]), + .ZN(n_1_0_1163) + ); + SDFF_X1_LVT \registers_reg[9][26] ( + .CK(n_0_39), .D(registers[26]), .Q(registers_9__ap[26]), .QN(), .SE(dftIn), + .SI(registers_31__ap[27]) + ); + SDFF_X1_LVT \registers_reg[7][26] ( + .CK(n_0_37), .D(registers[26]), .Q(registers_7__ap[26]), .QN(), .SE(dftIn), + .SI(registers_9__ap[26]) + ); + AOI22_X1_LVT i_1_0_1221( + .A1(registers_9__ap[26]), .A2(n_1_0_1291), .B1(n_1_0_1263), .B2(registers_7__ap[26]), + .ZN(n_1_0_1162) + ); + SDFF_X1_LVT \registers_reg[11][26] ( + .CK(n_0_41), .D(registers[26]), .Q(registers_11__ap[26]), .QN(), .SE(dftIn), + .SI(registers_14__ap[27]) + ); + SDFF_X1_LVT \registers_reg[25][26] ( + .CK(n_0_55), .D(registers[26]), .Q(registers_25__ap[26]), .QN(), .SE(dftIn), + .SI(registers_2__ap[26]) + ); + AOI22_X1_LVT i_1_0_1220( + .A1(registers_11__ap[26]), .A2(n_1_0_1270), .B1(n_1_0_1269), .B2(registers_25__ap[26]), + .ZN(n_1_0_1161) + ); + SDFF_X1_LVT \registers_reg[27][26] ( + .CK(n_0_57), .D(registers[26]), .Q(registers_27__ap[26]), .QN(), .SE(dftIn), + .SI(registers_25__ap[26]) + ); + SDFF_X1_LVT \registers_reg[16][26] ( + .CK(n_0_46), .D(registers[26]), .Q(registers_16__ap[26]), .QN(), .SE(dftIn), + .SI(registers_11__ap[26]) + ); + AOI22_X1_LVT i_1_0_1219( + .A1(registers_27__ap[26]), .A2(n_1_0_1279), .B1(n_1_0_1267), .B2(registers_16__ap[26]), + .ZN(n_1_0_1160) + ); + NAND3_X1_LVT i_1_0_1218( + .A1(n_1_0_1162), .A2(n_1_0_1161), .A3(n_1_0_1160), .ZN(n_1_0_1159) + ); + SDFF_X1_LVT \registers_reg[31][26] ( + .CK(n_0_61), .D(registers[26]), .Q(registers_31__ap[26]), .QN(), .SE(dftIn), + .SI(registers_7__ap[26]) + ); + SDFF_X1_LVT \registers_reg[6][26] ( + .CK(n_0_36), .D(registers[26]), .Q(registers_6__ap[26]), .QN(), .SE(dftIn), + .SI(registers_31__ap[26]) + ); + AOI221_X1_LVT i_1_0_1217( + .A(n_1_0_1159), .B1(n_1_0_1266), .B2(registers_31__ap[26]), .C1(registers_6__ap[26]), + .C2(n_1_0_1300), .ZN(n_1_0_1158) + ); + NAND3_X1_LVT i_1_0_1216( + .A1(n_1_0_1164), .A2(n_1_0_1163), .A3(n_1_0_1158), .ZN(n_1_0_1157) + ); + SDFF_X1_LVT \registers_reg[5][26] ( + .CK(n_0_35), .D(registers[26]), .Q(registers_5__ap[26]), .QN(), .SE(dftIn), + .SI(registers_6__ap[26]) + ); + SDFF_X1_LVT \registers_reg[28][26] ( + .CK(n_0_58), .D(registers[26]), .Q(registers_28__ap[26]), .QN(), .SE(dftIn), + .SI(registers_27__ap[26]) + ); + AOI221_X1_LVT i_1_0_1215( + .A(n_1_0_1157), .B1(n_1_0_1273), .B2(registers_5__ap[26]), .C1(registers_28__ap[26]), + .C2(n_1_0_1283), .ZN(n_1_0_1156) + ); + SDFF_X1_LVT \registers_reg[4][26] ( + .CK(n_0_34), .D(registers[26]), .Q(registers_4__ap[26]), .QN(), .SE(dftIn), + .SI(registers_5__ap[26]) + ); + SDFF_X1_LVT \registers_reg[12][26] ( + .CK(n_0_42), .D(registers[26]), .Q(registers_12__ap[26]), .QN(), .SE(dftIn), + .SI(registers_16__ap[26]) + ); + AOI22_X1_LVT i_1_0_1214( + .A1(registers_4__ap[26]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[26]), + .ZN(n_1_0_1155) + ); + SDFF_X1_LVT \registers_reg[19][26] ( + .CK(n_0_49), .D(registers[26]), .Q(registers_19__ap[26]), .QN(), .SE(dftIn), + .SI(registers_1__ap[26]) + ); + SDFF_X1_LVT \registers_reg[21][26] ( + .CK(n_0_51), .D(registers[26]), .Q(registers_21__ap[26]), .QN(), .SE(dftIn), + .SI(registers_19__ap[26]) + ); + AOI22_X1_LVT i_1_0_1213( + .A1(registers_19__ap[26]), .A2(n_1_0_1295), .B1(n_1_0_1259), .B2(registers_21__ap[26]), + .ZN(n_1_0_1154) + ); + SDFF_X1_LVT \registers_reg[24][26] ( + .CK(n_0_54), .D(registers[26]), .Q(registers_24__ap[26]), .QN(), .SE(dftIn), + .SI(registers_28__ap[26]) + ); + SDFF_X1_LVT \registers_reg[20][26] ( + .CK(n_0_50), .D(registers[26]), .Q(registers_20__ap[26]), .QN(), .SE(dftIn), + .SI(registers_21__ap[26]) + ); + AOI22_X1_LVT i_1_0_1212( + .A1(registers_24__ap[26]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[26]), + .ZN(n_1_0_1153) + ); + NAND3_X1_LVT i_1_0_1211( + .A1(n_1_0_1155), .A2(n_1_0_1154), .A3(n_1_0_1153), .ZN(n_1_0_1152) + ); + SDFF_X1_LVT \registers_reg[26][26] ( + .CK(n_0_56), .D(registers[26]), .Q(registers_26__ap[26]), .QN(), .SE(dftIn), + .SI(registers_24__ap[26]) + ); + SDFF_X1_LVT \registers_reg[30][26] ( + .CK(n_0_60), .D(registers[26]), .Q(registers_30__ap[26]), .QN(), .SE(dftIn), + .SI(registers_26__ap[26]) + ); + AOI221_X1_LVT i_1_0_1210( + .A(n_1_0_1152), .B1(n_1_0_1285), .B2(registers_26__ap[26]), .C1(registers_30__ap[26]), + .C2(n_1_0_1272), .ZN(n_1_0_1151) + ); + SDFF_X1_LVT \registers_reg[8][26] ( + .CK(n_0_38), .D(registers[26]), .Q(registers_8__ap[26]), .QN(), .SE(dftIn), + .SI(registers_4__ap[26]) + ); + SDFF_X1_LVT \registers_reg[23][26] ( + .CK(n_0_53), .D(registers[26]), .Q(registers_23__ap[26]), .QN(), .SE(dftIn), + .SI(registers_20__ap[26]) + ); + AOI22_X1_LVT i_1_0_1209( + .A1(registers_8__ap[26]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[26]), + .ZN(n_1_0_1150) + ); + SDFF_X1_LVT \registers_reg[13][26] ( + .CK(n_0_43), .D(registers[26]), .Q(registers_13__ap[26]), .QN(), .SE(dftIn), + .SI(registers_12__ap[26]) + ); + SDFF_X1_LVT \registers_reg[17][26] ( + .CK(n_0_47), .D(registers[26]), .Q(registers_17__ap[26]), .QN(), .SE(dftIn), + .SI(registers_23__ap[26]) + ); + AOI22_X1_LVT i_1_0_1208( + .A1(registers_13__ap[26]), .A2(n_1_0_1277), .B1(n_1_0_1271), .B2(registers_17__ap[26]), + .ZN(n_1_0_1149) + ); + SDFF_X1_LVT \registers_reg[15][26] ( + .CK(n_0_45), .D(registers[26]), .Q(registers_15__ap[26]), .QN(), .SE(dftIn), + .SI(registers_13__ap[26]) + ); + SDFF_X1_LVT \registers_reg[14][26] ( + .CK(n_0_44), .D(registers[26]), .Q(registers_14__ap[26]), .QN(), .SE(dftIn), + .SI(registers_15__ap[26]) + ); + AOI22_X1_LVT i_1_0_1207( + .A1(registers_15__ap[26]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[26]), + .ZN(n_1_0_1148) + ); + NAND3_X1_LVT i_1_0_1206( + .A1(n_1_0_1150), .A2(n_1_0_1149), .A3(n_1_0_1148), .ZN(n_1_0_1147) + ); + SDFF_X1_LVT \registers_reg[10][26] ( + .CK(n_0_40), .D(registers[26]), .Q(registers_10__ap[26]), .QN(), .SE(dftIn), + .SI(registers_14__ap[26]) + ); + SDFF_X1_LVT \registers_reg[3][26] ( + .CK(n_0_33), .D(registers[26]), .Q(registers_3__ap[26]), .QN(), .SE(dftIn), + .SI(registers_8__ap[26]) + ); + AOI221_X1_LVT i_1_0_1205( + .A(n_1_0_1147), .B1(n_1_0_1287), .B2(registers_10__ap[26]), .C1(registers_3__ap[26]), + .C2(n_1_0_1257), .ZN(n_1_0_1146) + ); + NAND3_X1_LVT i_1_0_1204( + .A1(n_1_0_1156), .A2(n_1_0_1151), .A3(n_1_0_1146), .ZN(RRs1[26]) + ); + AND2_X1_LVT i_0_0_25( + .A1(n_0_0_16), .A2(WRd[25]), .ZN(registers[25]) + ); + SDFF_X1_LVT \registers_reg[17][25] ( + .CK(n_0_47), .D(registers[25]), .Q(registers_17__ap[25]), .QN(), .SE(dftIn), + .SI(registers_17__ap[26]) + ); + SDFF_X1_LVT \registers_reg[21][25] ( + .CK(n_0_51), .D(registers[25]), .Q(registers_21__ap[25]), .QN(), .SE(dftIn), + .SI(registers_17__ap[25]) + ); + AOI22_X1_LVT i_1_0_1202( + .A1(registers_17__ap[25]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[25]), + .ZN(n_1_0_1144) + ); + SDFF_X1_LVT \registers_reg[6][25] ( + .CK(n_0_36), .D(registers[25]), .Q(registers_6__ap[25]), .QN(), .SE(dftIn), + .SI(registers_3__ap[26]) + ); + SDFF_X1_LVT \registers_reg[8][25] ( + .CK(n_0_38), .D(registers[25]), .Q(registers_8__ap[25]), .QN(), .SE(dftIn), + .SI(registers_6__ap[25]) + ); + AOI22_X1_LVT i_1_0_1203( + .A1(registers_6__ap[25]), .A2(n_1_0_1300), .B1(n_1_0_1282), .B2(registers_8__ap[25]), + .ZN(n_1_0_1145) + ); + SDFF_X1_LVT \registers_reg[20][25] ( + .CK(n_0_50), .D(registers[25]), .Q(registers_20__ap[25]), .QN(), .SE(dftIn), + .SI(registers_21__ap[25]) + ); + SDFF_X1_LVT \registers_reg[12][25] ( + .CK(n_0_42), .D(registers[25]), .Q(registers_12__ap[25]), .QN(), .SE(dftIn), + .SI(registers_10__ap[26]) + ); + AOI22_X1_LVT i_1_0_1201( + .A1(registers_20__ap[25]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[25]), + .ZN(n_1_0_1143) + ); + SDFF_X1_LVT \registers_reg[5][25] ( + .CK(n_0_35), .D(registers[25]), .Q(registers_5__ap[25]), .QN(), .SE(dftIn), + .SI(registers_8__ap[25]) + ); + SDFF_X1_LVT \registers_reg[11][25] ( + .CK(n_0_41), .D(registers[25]), .Q(registers_11__ap[25]), .QN(), .SE(dftIn), + .SI(registers_12__ap[25]) + ); + AOI22_X1_LVT i_1_0_1200( + .A1(registers_5__ap[25]), .A2(n_1_0_1273), .B1(n_1_0_1270), .B2(registers_11__ap[25]), + .ZN(n_1_0_1142) + ); + NAND3_X1_LVT i_1_0_1199( + .A1(n_1_0_1145), .A2(n_1_0_1143), .A3(n_1_0_1142), .ZN(n_1_0_1141) + ); + SDFF_X1_LVT \registers_reg[10][25] ( + .CK(n_0_40), .D(registers[25]), .Q(registers_10__ap[25]), .QN(), .SE(dftIn), + .SI(registers_11__ap[25]) + ); + SDFF_X1_LVT \registers_reg[2][25] ( + .CK(n_0_32), .D(registers[25]), .Q(registers_2__ap[25]), .QN(), .SE(dftIn), + .SI(registers_30__ap[26]) + ); + AOI221_X1_LVT i_1_0_1198( + .A(n_1_0_1141), .B1(n_1_0_1287), .B2(registers_10__ap[25]), .C1(registers_2__ap[25]), + .C2(n_1_0_1268), .ZN(n_1_0_1140) + ); + SDFF_X1_LVT \registers_reg[13][25] ( + .CK(n_0_43), .D(registers[25]), .Q(registers_13__ap[25]), .QN(), .SE(dftIn), + .SI(registers_10__ap[25]) + ); + SDFF_X1_LVT \registers_reg[30][25] ( + .CK(n_0_60), .D(registers[25]), .Q(registers_30__ap[25]), .QN(), .SE(dftIn), + .SI(registers_2__ap[25]) + ); + SDFF_X1_LVT \registers_reg[22][25] ( + .CK(n_0_52), .D(registers[25]), .Q(registers_22__ap[25]), .QN(), .SE(dftIn), + .SI(registers_20__ap[25]) + ); + AOI222_X1_LVT i_1_0_1197( + .A1(registers_13__ap[25]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[25]), + .C1(registers_22__ap[25]), .C2(n_1_0_1294), .ZN(n_1_0_1139) + ); + NAND2_X1_LVT i_1_0_1196( + .A1(n_1_0_1140), .A2(n_1_0_1139), .ZN(n_1_0_1138) + ); + SDFF_X1_LVT \registers_reg[1][25] ( + .CK(n_0_0), .D(registers[25]), .Q(registers_1__ap[25]), .QN(), .SE(dftIn), + .SI(registers_22__ap[25]) + ); + SDFF_X1_LVT \registers_reg[28][25] ( + .CK(n_0_58), .D(registers[25]), .Q(registers_28__ap[25]), .QN(), .SE(dftIn), + .SI(registers_30__ap[25]) + ); + AOI221_X1_LVT i_1_0_1195( + .A(n_1_0_1138), .B1(n_1_0_1274), .B2(registers_1__ap[25]), .C1(registers_28__ap[25]), + .C2(n_1_0_1283), .ZN(n_1_0_1137) + ); + SDFF_X1_LVT \registers_reg[18][25] ( + .CK(n_0_48), .D(registers[25]), .Q(registers_18__ap[25]), .QN(), .SE(dftIn), + .SI(registers_1__ap[25]) + ); + SDFF_X1_LVT \registers_reg[26][25] ( + .CK(n_0_56), .D(registers[25]), .Q(registers_26__ap[25]), .QN(), .SE(dftIn), + .SI(registers_28__ap[25]) + ); + AOI22_X1_LVT i_1_0_1194( + .A1(registers_18__ap[25]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[25]), + .ZN(n_1_0_1136) + ); + SDFF_X1_LVT \registers_reg[24][25] ( + .CK(n_0_54), .D(registers[25]), .Q(registers_24__ap[25]), .QN(), .SE(dftIn), + .SI(registers_26__ap[25]) + ); + SDFF_X1_LVT \registers_reg[4][25] ( + .CK(n_0_34), .D(registers[25]), .Q(registers_4__ap[25]), .QN(), .SE(dftIn), + .SI(registers_5__ap[25]) + ); + AOI22_X1_LVT i_1_0_1193( + .A1(registers_24__ap[25]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[25]), + .ZN(n_1_0_1135) + ); + SDFF_X1_LVT \registers_reg[15][25] ( + .CK(n_0_45), .D(registers[25]), .Q(registers_15__ap[25]), .QN(), .SE(dftIn), + .SI(registers_13__ap[25]) + ); + SDFF_X1_LVT \registers_reg[16][25] ( + .CK(n_0_46), .D(registers[25]), .Q(registers_16__ap[25]), .QN(), .SE(dftIn), + .SI(registers_15__ap[25]) + ); + AOI22_X1_LVT i_1_0_1192( + .A1(registers_15__ap[25]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[25]), + .ZN(n_1_0_1134) + ); + NAND3_X1_LVT i_1_0_1191( + .A1(n_1_0_1136), .A2(n_1_0_1135), .A3(n_1_0_1134), .ZN(n_1_0_1133) + ); + SDFF_X1_LVT \registers_reg[19][25] ( + .CK(n_0_49), .D(registers[25]), .Q(registers_19__ap[25]), .QN(), .SE(dftIn), + .SI(registers_18__ap[25]) + ); + SDFF_X1_LVT \registers_reg[25][25] ( + .CK(n_0_55), .D(registers[25]), .Q(registers_25__ap[25]), .QN(), .SE(dftIn), + .SI(registers_24__ap[25]) + ); + AOI221_X1_LVT i_1_0_1190( + .A(n_1_0_1133), .B1(n_1_0_1295), .B2(registers_19__ap[25]), .C1(registers_25__ap[25]), + .C2(n_1_0_1269), .ZN(n_1_0_1132) + ); + SDFF_X1_LVT \registers_reg[7][25] ( + .CK(n_0_37), .D(registers[25]), .Q(registers_7__ap[25]), .QN(), .SE(dftIn), + .SI(registers_4__ap[25]) + ); + SDFF_X1_LVT \registers_reg[14][25] ( + .CK(n_0_44), .D(registers[25]), .Q(registers_14__ap[25]), .QN(), .SE(dftIn), + .SI(registers_16__ap[25]) + ); + AOI22_X1_LVT i_1_0_1189( + .A1(registers_7__ap[25]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[25]), + .ZN(n_1_0_1131) + ); + SDFF_X1_LVT \registers_reg[9][25] ( + .CK(n_0_39), .D(registers[25]), .Q(registers_9__ap[25]), .QN(), .SE(dftIn), + .SI(registers_7__ap[25]) + ); + SDFF_X1_LVT \registers_reg[29][25] ( + .CK(n_0_59), .D(registers[25]), .Q(registers_29__ap[25]), .QN(), .SE(dftIn), + .SI(registers_25__ap[25]) + ); + AOI22_X1_LVT i_1_0_1188( + .A1(registers_9__ap[25]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[25]), + .ZN(n_1_0_1130) + ); + SDFF_X1_LVT \registers_reg[23][25] ( + .CK(n_0_53), .D(registers[25]), .Q(registers_23__ap[25]), .QN(), .SE(dftIn), + .SI(registers_19__ap[25]) + ); + SDFF_X1_LVT \registers_reg[3][25] ( + .CK(n_0_33), .D(registers[25]), .Q(registers_3__ap[25]), .QN(), .SE(dftIn), + .SI(registers_9__ap[25]) + ); + AOI22_X1_LVT i_1_0_1187( + .A1(registers_23__ap[25]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[25]), + .ZN(n_1_0_1129) + ); + NAND3_X1_LVT i_1_0_1186( + .A1(n_1_0_1131), .A2(n_1_0_1130), .A3(n_1_0_1129), .ZN(n_1_0_1128) + ); + SDFF_X1_LVT \registers_reg[27][25] ( + .CK(n_0_57), .D(registers[25]), .Q(registers_27__ap[25]), .QN(), .SE(dftIn), + .SI(registers_29__ap[25]) + ); + SDFF_X1_LVT \registers_reg[31][25] ( + .CK(n_0_61), .D(registers[25]), .Q(registers_31__ap[25]), .QN(), .SE(dftIn), + .SI(registers_3__ap[25]) + ); + AOI221_X1_LVT i_1_0_1185( + .A(n_1_0_1128), .B1(n_1_0_1279), .B2(registers_27__ap[25]), .C1(registers_31__ap[25]), + .C2(n_1_0_1266), .ZN(n_1_0_1127) + ); + NAND4_X1_LVT i_1_0_1184( + .A1(n_1_0_1144), .A2(n_1_0_1137), .A3(n_1_0_1132), .A4(n_1_0_1127), .ZN(RRs1[25]) + ); + AND2_X1_LVT i_0_0_24( + .A1(n_0_0_16), .A2(WRd[24]), .ZN(registers[24]) + ); + SDFF_X1_LVT \registers_reg[17][24] ( + .CK(n_0_47), .D(registers[24]), .Q(registers_17__ap[24]), .QN(), .SE(dftIn), + .SI(registers_23__ap[25]) + ); + SDFF_X1_LVT \registers_reg[21][24] ( + .CK(n_0_51), .D(registers[24]), .Q(registers_21__ap[24]), .QN(), .SE(dftIn), + .SI(registers_17__ap[24]) + ); + AOI22_X1_LVT i_1_0_1182( + .A1(registers_17__ap[24]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[24]), + .ZN(n_1_0_1125) + ); + SDFF_X1_LVT \registers_reg[6][24] ( + .CK(n_0_36), .D(registers[24]), .Q(registers_6__ap[24]), .QN(), .SE(dftIn), + .SI(registers_31__ap[25]) + ); + SDFF_X1_LVT \registers_reg[8][24] ( + .CK(n_0_38), .D(registers[24]), .Q(registers_8__ap[24]), .QN(), .SE(dftIn), + .SI(registers_6__ap[24]) + ); + AOI22_X1_LVT i_1_0_1183( + .A1(registers_6__ap[24]), .A2(n_1_0_1300), .B1(n_1_0_1282), .B2(registers_8__ap[24]), + .ZN(n_1_0_1126) + ); + SDFF_X1_LVT \registers_reg[20][24] ( + .CK(n_0_50), .D(registers[24]), .Q(registers_20__ap[24]), .QN(), .SE(dftIn), + .SI(registers_21__ap[24]) + ); + SDFF_X1_LVT \registers_reg[12][24] ( + .CK(n_0_42), .D(registers[24]), .Q(registers_12__ap[24]), .QN(), .SE(dftIn), + .SI(registers_14__ap[25]) + ); + AOI22_X1_LVT i_1_0_1181( + .A1(registers_20__ap[24]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[24]), + .ZN(n_1_0_1124) + ); + SDFF_X1_LVT \registers_reg[5][24] ( + .CK(n_0_35), .D(registers[24]), .Q(registers_5__ap[24]), .QN(), .SE(dftIn), + .SI(registers_8__ap[24]) + ); + SDFF_X1_LVT \registers_reg[11][24] ( + .CK(n_0_41), .D(registers[24]), .Q(registers_11__ap[24]), .QN(), .SE(dftIn), + .SI(registers_12__ap[24]) + ); + AOI22_X1_LVT i_1_0_1180( + .A1(registers_5__ap[24]), .A2(n_1_0_1273), .B1(n_1_0_1270), .B2(registers_11__ap[24]), + .ZN(n_1_0_1123) + ); + NAND3_X1_LVT i_1_0_1179( + .A1(n_1_0_1126), .A2(n_1_0_1124), .A3(n_1_0_1123), .ZN(n_1_0_1122) + ); + SDFF_X1_LVT \registers_reg[10][24] ( + .CK(n_0_40), .D(registers[24]), .Q(registers_10__ap[24]), .QN(), .SE(dftIn), + .SI(registers_11__ap[24]) + ); + SDFF_X1_LVT \registers_reg[2][24] ( + .CK(n_0_32), .D(registers[24]), .Q(registers_2__ap[24]), .QN(), .SE(dftIn), + .SI(registers_27__ap[25]) + ); + AOI221_X1_LVT i_1_0_1178( + .A(n_1_0_1122), .B1(n_1_0_1287), .B2(registers_10__ap[24]), .C1(registers_2__ap[24]), + .C2(n_1_0_1268), .ZN(n_1_0_1121) + ); + SDFF_X1_LVT \registers_reg[13][24] ( + .CK(n_0_43), .D(registers[24]), .Q(registers_13__ap[24]), .QN(), .SE(dftIn), + .SI(registers_10__ap[24]) + ); + SDFF_X1_LVT \registers_reg[30][24] ( + .CK(n_0_60), .D(registers[24]), .Q(registers_30__ap[24]), .QN(), .SE(dftIn), + .SI(registers_2__ap[24]) + ); + SDFF_X1_LVT \registers_reg[22][24] ( + .CK(n_0_52), .D(registers[24]), .Q(registers_22__ap[24]), .QN(), .SE(dftIn), + .SI(registers_20__ap[24]) + ); + AOI222_X1_LVT i_1_0_1177( + .A1(registers_13__ap[24]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[24]), + .C1(registers_22__ap[24]), .C2(n_1_0_1294), .ZN(n_1_0_1120) + ); + NAND2_X1_LVT i_1_0_1176( + .A1(n_1_0_1121), .A2(n_1_0_1120), .ZN(n_1_0_1119) + ); + SDFF_X1_LVT \registers_reg[1][24] ( + .CK(n_0_0), .D(registers[24]), .Q(registers_1__ap[24]), .QN(), .SE(dftIn), + .SI(registers_22__ap[24]) + ); + SDFF_X1_LVT \registers_reg[28][24] ( + .CK(n_0_58), .D(registers[24]), .Q(registers_28__ap[24]), .QN(), .SE(dftIn), + .SI(registers_30__ap[24]) + ); + AOI221_X1_LVT i_1_0_1175( + .A(n_1_0_1119), .B1(n_1_0_1274), .B2(registers_1__ap[24]), .C1(registers_28__ap[24]), + .C2(n_1_0_1283), .ZN(n_1_0_1118) + ); + SDFF_X1_LVT \registers_reg[18][24] ( + .CK(n_0_48), .D(registers[24]), .Q(registers_18__ap[24]), .QN(), .SE(dftIn), + .SI(registers_1__ap[24]) + ); + SDFF_X1_LVT \registers_reg[26][24] ( + .CK(n_0_56), .D(registers[24]), .Q(registers_26__ap[24]), .QN(), .SE(dftIn), + .SI(registers_28__ap[24]) + ); + AOI22_X1_LVT i_1_0_1174( + .A1(registers_18__ap[24]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[24]), + .ZN(n_1_0_1117) + ); + SDFF_X1_LVT \registers_reg[24][24] ( + .CK(n_0_54), .D(registers[24]), .Q(registers_24__ap[24]), .QN(), .SE(dftIn), + .SI(registers_26__ap[24]) + ); + SDFF_X1_LVT \registers_reg[4][24] ( + .CK(n_0_34), .D(registers[24]), .Q(registers_4__ap[24]), .QN(), .SE(dftIn), + .SI(registers_5__ap[24]) + ); + AOI22_X1_LVT i_1_0_1173( + .A1(registers_24__ap[24]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[24]), + .ZN(n_1_0_1116) + ); + SDFF_X1_LVT \registers_reg[15][24] ( + .CK(n_0_45), .D(registers[24]), .Q(registers_15__ap[24]), .QN(), .SE(dftIn), + .SI(registers_13__ap[24]) + ); + SDFF_X1_LVT \registers_reg[25][24] ( + .CK(n_0_55), .D(registers[24]), .Q(registers_25__ap[24]), .QN(), .SE(dftIn), + .SI(registers_24__ap[24]) + ); + AOI22_X1_LVT i_1_0_1172( + .A1(registers_15__ap[24]), .A2(n_1_0_1286), .B1(n_1_0_1269), .B2(registers_25__ap[24]), + .ZN(n_1_0_1115) + ); + NAND3_X1_LVT i_1_0_1171( + .A1(n_1_0_1117), .A2(n_1_0_1116), .A3(n_1_0_1115), .ZN(n_1_0_1114) + ); + SDFF_X1_LVT \registers_reg[19][24] ( + .CK(n_0_49), .D(registers[24]), .Q(registers_19__ap[24]), .QN(), .SE(dftIn), + .SI(registers_18__ap[24]) + ); + SDFF_X1_LVT \registers_reg[16][24] ( + .CK(n_0_46), .D(registers[24]), .Q(registers_16__ap[24]), .QN(), .SE(dftIn), + .SI(registers_15__ap[24]) + ); + AOI221_X1_LVT i_1_0_1170( + .A(n_1_0_1114), .B1(n_1_0_1295), .B2(registers_19__ap[24]), .C1(registers_16__ap[24]), + .C2(n_1_0_1267), .ZN(n_1_0_1113) + ); + SDFF_X1_LVT \registers_reg[7][24] ( + .CK(n_0_37), .D(registers[24]), .Q(registers_7__ap[24]), .QN(), .SE(dftIn), + .SI(registers_4__ap[24]) + ); + SDFF_X1_LVT \registers_reg[14][24] ( + .CK(n_0_44), .D(registers[24]), .Q(registers_14__ap[24]), .QN(), .SE(dftIn), + .SI(registers_16__ap[24]) + ); + AOI22_X1_LVT i_1_0_1169( + .A1(registers_7__ap[24]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[24]), + .ZN(n_1_0_1112) + ); + SDFF_X1_LVT \registers_reg[9][24] ( + .CK(n_0_39), .D(registers[24]), .Q(registers_9__ap[24]), .QN(), .SE(dftIn), + .SI(registers_7__ap[24]) + ); + SDFF_X1_LVT \registers_reg[29][24] ( + .CK(n_0_59), .D(registers[24]), .Q(registers_29__ap[24]), .QN(), .SE(dftIn), + .SI(registers_25__ap[24]) + ); + AOI22_X1_LVT i_1_0_1168( + .A1(registers_9__ap[24]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[24]), + .ZN(n_1_0_1111) + ); + SDFF_X1_LVT \registers_reg[23][24] ( + .CK(n_0_53), .D(registers[24]), .Q(registers_23__ap[24]), .QN(), .SE(dftIn), + .SI(registers_19__ap[24]) + ); + SDFF_X1_LVT \registers_reg[3][24] ( + .CK(n_0_33), .D(registers[24]), .Q(registers_3__ap[24]), .QN(), .SE(dftIn), + .SI(registers_9__ap[24]) + ); + AOI22_X1_LVT i_1_0_1167( + .A1(registers_23__ap[24]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[24]), + .ZN(n_1_0_1110) + ); + NAND3_X1_LVT i_1_0_1166( + .A1(n_1_0_1112), .A2(n_1_0_1111), .A3(n_1_0_1110), .ZN(n_1_0_1109) + ); + SDFF_X1_LVT \registers_reg[27][24] ( + .CK(n_0_57), .D(registers[24]), .Q(registers_27__ap[24]), .QN(), .SE(dftIn), + .SI(registers_29__ap[24]) + ); + SDFF_X1_LVT \registers_reg[31][24] ( + .CK(n_0_61), .D(registers[24]), .Q(registers_31__ap[24]), .QN(), .SE(dftIn), + .SI(registers_3__ap[24]) + ); + AOI221_X1_LVT i_1_0_1165( + .A(n_1_0_1109), .B1(n_1_0_1279), .B2(registers_27__ap[24]), .C1(registers_31__ap[24]), + .C2(n_1_0_1266), .ZN(n_1_0_1108) + ); + NAND4_X1_LVT i_1_0_1164( + .A1(n_1_0_1125), .A2(n_1_0_1118), .A3(n_1_0_1113), .A4(n_1_0_1108), .ZN(RRs1[24]) + ); + AND2_X1_LVT i_0_0_23( + .A1(n_0_0_16), .A2(WRd[23]), .ZN(registers[23]) + ); + SDFF_X1_LVT \registers_reg[9][23] ( + .CK(n_0_39), .D(registers[23]), .Q(registers_9__ap[23]), .QN(), .SE(dftIn), + .SI(registers_31__ap[24]) + ); + SDFF_X1_LVT \registers_reg[28][23] ( + .CK(n_0_58), .D(registers[23]), .Q(registers_28__ap[23]), .QN(), .SE(dftIn), + .SI(registers_27__ap[24]) + ); + AOI22_X1_LVT i_1_0_1163( + .A1(registers_9__ap[23]), .A2(n_1_0_1291), .B1(n_1_0_1283), .B2(registers_28__ap[23]), + .ZN(n_1_0_1107) + ); + SDFF_X1_LVT \registers_reg[18][23] ( + .CK(n_0_48), .D(registers[23]), .Q(registers_18__ap[23]), .QN(), .SE(dftIn), + .SI(registers_23__ap[24]) + ); + SDFF_X1_LVT \registers_reg[22][23] ( + .CK(n_0_52), .D(registers[23]), .Q(registers_22__ap[23]), .QN(), .SE(dftIn), + .SI(registers_18__ap[23]) + ); + AOI22_X1_LVT i_1_0_1160( + .A1(registers_18__ap[23]), .A2(n_1_0_1297), .B1(n_1_0_1294), .B2(registers_22__ap[23]), + .ZN(n_1_0_1104) + ); + SDFF_X1_LVT \registers_reg[1][23] ( + .CK(n_0_0), .D(registers[23]), .Q(registers_1__ap[23]), .QN(), .SE(dftIn), + .SI(registers_22__ap[23]) + ); + SDFF_X1_LVT \registers_reg[21][23] ( + .CK(n_0_51), .D(registers[23]), .Q(registers_21__ap[23]), .QN(), .SE(dftIn), + .SI(registers_1__ap[23]) + ); + AOI22_X1_LVT i_1_0_1159( + .A1(registers_1__ap[23]), .A2(n_1_0_1274), .B1(n_1_0_1259), .B2(registers_21__ap[23]), + .ZN(n_1_0_1103) + ); + NAND3_X1_LVT i_1_0_1157( + .A1(n_1_0_1107), .A2(n_1_0_1104), .A3(n_1_0_1103), .ZN(n_1_0_1101) + ); + SDFF_X1_LVT \registers_reg[20][23] ( + .CK(n_0_50), .D(registers[23]), .Q(registers_20__ap[23]), .QN(), .SE(dftIn), + .SI(registers_21__ap[23]) + ); + SDFF_X1_LVT \registers_reg[19][23] ( + .CK(n_0_49), .D(registers[23]), .Q(registers_19__ap[23]), .QN(), .SE(dftIn), + .SI(registers_20__ap[23]) + ); + AOI221_X1_LVT i_1_0_1156( + .A(n_1_0_1101), .B1(n_1_0_1281), .B2(registers_20__ap[23]), .C1(registers_19__ap[23]), + .C2(n_1_0_1295), .ZN(n_1_0_1100) + ); + SDFF_X1_LVT \registers_reg[26][23] ( + .CK(n_0_56), .D(registers[23]), .Q(registers_26__ap[23]), .QN(), .SE(dftIn), + .SI(registers_28__ap[23]) + ); + SDFF_X1_LVT \registers_reg[23][23] ( + .CK(n_0_53), .D(registers[23]), .Q(registers_23__ap[23]), .QN(), .SE(dftIn), + .SI(registers_19__ap[23]) + ); + AOI22_X1_LVT i_1_0_1162( + .A1(registers_26__ap[23]), .A2(n_1_0_1285), .B1(n_1_0_1264), .B2(registers_23__ap[23]), + .ZN(n_1_0_1106) + ); + SDFF_X1_LVT \registers_reg[29][23] ( + .CK(n_0_59), .D(registers[23]), .Q(registers_29__ap[23]), .QN(), .SE(dftIn), + .SI(registers_26__ap[23]) + ); + SDFF_X1_LVT \registers_reg[3][23] ( + .CK(n_0_33), .D(registers[23]), .Q(registers_3__ap[23]), .QN(), .SE(dftIn), + .SI(registers_9__ap[23]) + ); + AOI22_X1_LVT i_1_0_1161( + .A1(registers_29__ap[23]), .A2(n_1_0_1276), .B1(n_1_0_1257), .B2(registers_3__ap[23]), + .ZN(n_1_0_1105) + ); + SDFF_X1_LVT \registers_reg[30][23] ( + .CK(n_0_60), .D(registers[23]), .Q(registers_30__ap[23]), .QN(), .SE(dftIn), + .SI(registers_29__ap[23]) + ); + SDFF_X1_LVT \registers_reg[31][23] ( + .CK(n_0_61), .D(registers[23]), .Q(registers_31__ap[23]), .QN(), .SE(dftIn), + .SI(registers_3__ap[23]) + ); + AOI22_X1_LVT i_1_0_1158( + .A1(registers_30__ap[23]), .A2(n_1_0_1272), .B1(n_1_0_1266), .B2(registers_31__ap[23]), + .ZN(n_1_0_1102) + ); + NAND3_X1_LVT i_1_0_1155( + .A1(n_1_0_1106), .A2(n_1_0_1105), .A3(n_1_0_1102), .ZN(n_1_0_1099) + ); + SDFF_X1_LVT \registers_reg[8][23] ( + .CK(n_0_38), .D(registers[23]), .Q(registers_8__ap[23]), .QN(), .SE(dftIn), + .SI(registers_31__ap[23]) + ); + SDFF_X1_LVT \registers_reg[17][23] ( + .CK(n_0_47), .D(registers[23]), .Q(registers_17__ap[23]), .QN(), .SE(dftIn), + .SI(registers_23__ap[23]) + ); + AOI221_X1_LVT i_1_0_1154( + .A(n_1_0_1099), .B1(n_1_0_1282), .B2(registers_8__ap[23]), .C1(registers_17__ap[23]), + .C2(n_1_0_1271), .ZN(n_1_0_1098) + ); + SDFF_X1_LVT \registers_reg[24][23] ( + .CK(n_0_54), .D(registers[23]), .Q(registers_24__ap[23]), .QN(), .SE(dftIn), + .SI(registers_30__ap[23]) + ); + SDFF_X1_LVT \registers_reg[15][23] ( + .CK(n_0_45), .D(registers[23]), .Q(registers_15__ap[23]), .QN(), .SE(dftIn), + .SI(registers_14__ap[24]) + ); + SDFF_X1_LVT \registers_reg[14][23] ( + .CK(n_0_44), .D(registers[23]), .Q(registers_14__ap[23]), .QN(), .SE(dftIn), + .SI(registers_15__ap[23]) + ); + AOI222_X1_LVT i_1_0_1153( + .A1(registers_24__ap[23]), .A2(n_1_0_1289), .B1(n_1_0_1286), .B2(registers_15__ap[23]), + .C1(n_1_0_1258), .C2(registers_14__ap[23]), .ZN(n_1_0_1097) + ); + SDFF_X1_LVT \registers_reg[16][23] ( + .CK(n_0_46), .D(registers[23]), .Q(registers_16__ap[23]), .QN(), .SE(dftIn), + .SI(registers_14__ap[23]) + ); + SDFF_X1_LVT \registers_reg[7][23] ( + .CK(n_0_37), .D(registers[23]), .Q(registers_7__ap[23]), .QN(), .SE(dftIn), + .SI(registers_8__ap[23]) + ); + AOI22_X1_LVT i_1_0_1152( + .A1(registers_16__ap[23]), .A2(n_1_0_1267), .B1(n_1_0_1263), .B2(registers_7__ap[23]), + .ZN(n_1_0_1096) + ); + SDFF_X1_LVT \registers_reg[6][23] ( + .CK(n_0_36), .D(registers[23]), .Q(registers_6__ap[23]), .QN(), .SE(dftIn), + .SI(registers_7__ap[23]) + ); + SDFF_X1_LVT \registers_reg[25][23] ( + .CK(n_0_55), .D(registers[23]), .Q(registers_25__ap[23]), .QN(), .SE(dftIn), + .SI(registers_24__ap[23]) + ); + AOI22_X1_LVT i_1_0_1151( + .A1(registers_6__ap[23]), .A2(n_1_0_1300), .B1(n_1_0_1269), .B2(registers_25__ap[23]), + .ZN(n_1_0_1095) + ); + SDFF_X1_LVT \registers_reg[27][23] ( + .CK(n_0_57), .D(registers[23]), .Q(registers_27__ap[23]), .QN(), .SE(dftIn), + .SI(registers_25__ap[23]) + ); + SDFF_X1_LVT \registers_reg[11][23] ( + .CK(n_0_41), .D(registers[23]), .Q(registers_11__ap[23]), .QN(), .SE(dftIn), + .SI(registers_16__ap[23]) + ); + AOI22_X1_LVT i_1_0_1150( + .A1(registers_27__ap[23]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[23]), + .ZN(n_1_0_1094) + ); + SDFF_X1_LVT \registers_reg[13][23] ( + .CK(n_0_43), .D(registers[23]), .Q(registers_13__ap[23]), .QN(), .SE(dftIn), + .SI(registers_11__ap[23]) + ); + SDFF_X1_LVT \registers_reg[5][23] ( + .CK(n_0_35), .D(registers[23]), .Q(registers_5__ap[23]), .QN(), .SE(dftIn), + .SI(registers_6__ap[23]) + ); + AOI22_X1_LVT i_1_0_1149( + .A1(registers_13__ap[23]), .A2(n_1_0_1277), .B1(n_1_0_1273), .B2(registers_5__ap[23]), + .ZN(n_1_0_1093) + ); + SDFF_X1_LVT \registers_reg[4][23] ( + .CK(n_0_34), .D(registers[23]), .Q(registers_4__ap[23]), .QN(), .SE(dftIn), + .SI(registers_5__ap[23]) + ); + SDFF_X1_LVT \registers_reg[12][23] ( + .CK(n_0_42), .D(registers[23]), .Q(registers_12__ap[23]), .QN(), .SE(dftIn), + .SI(registers_13__ap[23]) + ); + AOI22_X1_LVT i_1_0_1148( + .A1(registers_4__ap[23]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[23]), + .ZN(n_1_0_1092) + ); + NAND3_X1_LVT i_1_0_1147( + .A1(n_1_0_1094), .A2(n_1_0_1093), .A3(n_1_0_1092), .ZN(n_1_0_1091) + ); + SDFF_X1_LVT \registers_reg[2][23] ( + .CK(n_0_32), .D(registers[23]), .Q(registers_2__ap[23]), .QN(), .SE(dftIn), + .SI(registers_27__ap[23]) + ); + SDFF_X1_LVT \registers_reg[10][23] ( + .CK(n_0_40), .D(registers[23]), .Q(registers_10__ap[23]), .QN(), .SE(dftIn), + .SI(registers_12__ap[23]) + ); + AOI221_X1_LVT i_1_0_1146( + .A(n_1_0_1091), .B1(n_1_0_1268), .B2(registers_2__ap[23]), .C1(registers_10__ap[23]), + .C2(n_1_0_1287), .ZN(n_1_0_1090) + ); + AND4_X1_LVT i_1_0_1145( + .A1(n_1_0_1097), .A2(n_1_0_1096), .A3(n_1_0_1095), .A4(n_1_0_1090), .ZN(n_1_0_1089) + ); + NAND3_X1_LVT i_1_0_1144( + .A1(n_1_0_1100), .A2(n_1_0_1098), .A3(n_1_0_1089), .ZN(RRs1[23]) + ); + AND2_X1_LVT i_0_0_22( + .A1(n_0_0_16), .A2(WRd[22]), .ZN(registers[22]) + ); + SDFF_X1_LVT \registers_reg[17][22] ( + .CK(n_0_47), .D(registers[22]), .Q(registers_17__ap[22]), .QN(), .SE(dftIn), + .SI(registers_17__ap[23]) + ); + SDFF_X1_LVT \registers_reg[21][22] ( + .CK(n_0_51), .D(registers[22]), .Q(registers_21__ap[22]), .QN(), .SE(dftIn), + .SI(registers_17__ap[22]) + ); + AOI22_X1_LVT i_1_0_1142( + .A1(registers_17__ap[22]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[22]), + .ZN(n_1_0_1087) + ); + SDFF_X1_LVT \registers_reg[6][22] ( + .CK(n_0_36), .D(registers[22]), .Q(registers_6__ap[22]), .QN(), .SE(dftIn), + .SI(registers_4__ap[23]) + ); + SDFF_X1_LVT \registers_reg[11][22] ( + .CK(n_0_41), .D(registers[22]), .Q(registers_11__ap[22]), .QN(), .SE(dftIn), + .SI(registers_10__ap[23]) + ); + AOI22_X1_LVT i_1_0_1143( + .A1(registers_6__ap[22]), .A2(n_1_0_1300), .B1(n_1_0_1270), .B2(registers_11__ap[22]), + .ZN(n_1_0_1088) + ); + SDFF_X1_LVT \registers_reg[20][22] ( + .CK(n_0_50), .D(registers[22]), .Q(registers_20__ap[22]), .QN(), .SE(dftIn), + .SI(registers_21__ap[22]) + ); + SDFF_X1_LVT \registers_reg[12][22] ( + .CK(n_0_42), .D(registers[22]), .Q(registers_12__ap[22]), .QN(), .SE(dftIn), + .SI(registers_11__ap[22]) + ); + AOI22_X1_LVT i_1_0_1141( + .A1(registers_20__ap[22]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[22]), + .ZN(n_1_0_1086) + ); + SDFF_X1_LVT \registers_reg[10][22] ( + .CK(n_0_40), .D(registers[22]), .Q(registers_10__ap[22]), .QN(), .SE(dftIn), + .SI(registers_12__ap[22]) + ); + SDFF_X1_LVT \registers_reg[5][22] ( + .CK(n_0_35), .D(registers[22]), .Q(registers_5__ap[22]), .QN(), .SE(dftIn), + .SI(registers_6__ap[22]) + ); + AOI22_X1_LVT i_1_0_1140( + .A1(registers_10__ap[22]), .A2(n_1_0_1287), .B1(n_1_0_1273), .B2(registers_5__ap[22]), + .ZN(n_1_0_1085) + ); + NAND3_X1_LVT i_1_0_1139( + .A1(n_1_0_1088), .A2(n_1_0_1086), .A3(n_1_0_1085), .ZN(n_1_0_1084) + ); + SDFF_X1_LVT \registers_reg[31][22] ( + .CK(n_0_61), .D(registers[22]), .Q(registers_31__ap[22]), .QN(), .SE(dftIn), + .SI(registers_5__ap[22]) + ); + SDFF_X1_LVT \registers_reg[2][22] ( + .CK(n_0_32), .D(registers[22]), .Q(registers_2__ap[22]), .QN(), .SE(dftIn), + .SI(registers_2__ap[23]) + ); + AOI221_X1_LVT i_1_0_1138( + .A(n_1_0_1084), .B1(n_1_0_1266), .B2(registers_31__ap[22]), .C1(registers_2__ap[22]), + .C2(n_1_0_1268), .ZN(n_1_0_1083) + ); + SDFF_X1_LVT \registers_reg[22][22] ( + .CK(n_0_52), .D(registers[22]), .Q(registers_22__ap[22]), .QN(), .SE(dftIn), + .SI(registers_20__ap[22]) + ); + SDFF_X1_LVT \registers_reg[26][22] ( + .CK(n_0_56), .D(registers[22]), .Q(registers_26__ap[22]), .QN(), .SE(dftIn), + .SI(registers_2__ap[22]) + ); + SDFF_X1_LVT \registers_reg[13][22] ( + .CK(n_0_43), .D(registers[22]), .Q(registers_13__ap[22]), .QN(), .SE(dftIn), + .SI(registers_10__ap[22]) + ); + AOI222_X1_LVT i_1_0_1137( + .A1(registers_22__ap[22]), .A2(n_1_0_1294), .B1(n_1_0_1285), .B2(registers_26__ap[22]), + .C1(n_1_0_1277), .C2(registers_13__ap[22]), .ZN(n_1_0_1082) + ); + NAND2_X1_LVT i_1_0_1136( + .A1(n_1_0_1083), .A2(n_1_0_1082), .ZN(n_1_0_1081) + ); + SDFF_X1_LVT \registers_reg[1][22] ( + .CK(n_0_0), .D(registers[22]), .Q(registers_1__ap[22]), .QN(), .SE(dftIn), + .SI(registers_22__ap[22]) + ); + SDFF_X1_LVT \registers_reg[28][22] ( + .CK(n_0_58), .D(registers[22]), .Q(registers_28__ap[22]), .QN(), .SE(dftIn), + .SI(registers_26__ap[22]) + ); + AOI221_X1_LVT i_1_0_1135( + .A(n_1_0_1081), .B1(n_1_0_1274), .B2(registers_1__ap[22]), .C1(registers_28__ap[22]), + .C2(n_1_0_1283), .ZN(n_1_0_1080) + ); + SDFF_X1_LVT \registers_reg[18][22] ( + .CK(n_0_48), .D(registers[22]), .Q(registers_18__ap[22]), .QN(), .SE(dftIn), + .SI(registers_1__ap[22]) + ); + SDFF_X1_LVT \registers_reg[30][22] ( + .CK(n_0_60), .D(registers[22]), .Q(registers_30__ap[22]), .QN(), .SE(dftIn), + .SI(registers_28__ap[22]) + ); + AOI22_X1_LVT i_1_0_1134( + .A1(registers_18__ap[22]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[22]), + .ZN(n_1_0_1079) + ); + SDFF_X1_LVT \registers_reg[24][22] ( + .CK(n_0_54), .D(registers[22]), .Q(registers_24__ap[22]), .QN(), .SE(dftIn), + .SI(registers_30__ap[22]) + ); + SDFF_X1_LVT \registers_reg[4][22] ( + .CK(n_0_34), .D(registers[22]), .Q(registers_4__ap[22]), .QN(), .SE(dftIn), + .SI(registers_31__ap[22]) + ); + AOI22_X1_LVT i_1_0_1133( + .A1(registers_24__ap[22]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[22]), + .ZN(n_1_0_1078) + ); + SDFF_X1_LVT \registers_reg[15][22] ( + .CK(n_0_45), .D(registers[22]), .Q(registers_15__ap[22]), .QN(), .SE(dftIn), + .SI(registers_13__ap[22]) + ); + SDFF_X1_LVT \registers_reg[16][22] ( + .CK(n_0_46), .D(registers[22]), .Q(registers_16__ap[22]), .QN(), .SE(dftIn), + .SI(registers_15__ap[22]) + ); + AOI22_X1_LVT i_1_0_1132( + .A1(registers_15__ap[22]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[22]), + .ZN(n_1_0_1077) + ); + NAND3_X1_LVT i_1_0_1131( + .A1(n_1_0_1079), .A2(n_1_0_1078), .A3(n_1_0_1077), .ZN(n_1_0_1076) + ); + SDFF_X1_LVT \registers_reg[19][22] ( + .CK(n_0_49), .D(registers[22]), .Q(registers_19__ap[22]), .QN(), .SE(dftIn), + .SI(registers_18__ap[22]) + ); + SDFF_X1_LVT \registers_reg[25][22] ( + .CK(n_0_55), .D(registers[22]), .Q(registers_25__ap[22]), .QN(), .SE(dftIn), + .SI(registers_24__ap[22]) + ); + AOI221_X1_LVT i_1_0_1130( + .A(n_1_0_1076), .B1(n_1_0_1295), .B2(registers_19__ap[22]), .C1(registers_25__ap[22]), + .C2(n_1_0_1269), .ZN(n_1_0_1075) + ); + SDFF_X1_LVT \registers_reg[7][22] ( + .CK(n_0_37), .D(registers[22]), .Q(registers_7__ap[22]), .QN(), .SE(dftIn), + .SI(registers_4__ap[22]) + ); + SDFF_X1_LVT \registers_reg[14][22] ( + .CK(n_0_44), .D(registers[22]), .Q(registers_14__ap[22]), .QN(), .SE(dftIn), + .SI(registers_16__ap[22]) + ); + AOI22_X1_LVT i_1_0_1129( + .A1(registers_7__ap[22]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[22]), + .ZN(n_1_0_1074) + ); + SDFF_X1_LVT \registers_reg[9][22] ( + .CK(n_0_39), .D(registers[22]), .Q(registers_9__ap[22]), .QN(), .SE(dftIn), + .SI(registers_7__ap[22]) + ); + SDFF_X1_LVT \registers_reg[29][22] ( + .CK(n_0_59), .D(registers[22]), .Q(registers_29__ap[22]), .QN(), .SE(dftIn), + .SI(registers_25__ap[22]) + ); + AOI22_X1_LVT i_1_0_1128( + .A1(registers_9__ap[22]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[22]), + .ZN(n_1_0_1073) + ); + SDFF_X1_LVT \registers_reg[8][22] ( + .CK(n_0_38), .D(registers[22]), .Q(registers_8__ap[22]), .QN(), .SE(dftIn), + .SI(registers_9__ap[22]) + ); + SDFF_X1_LVT \registers_reg[23][22] ( + .CK(n_0_53), .D(registers[22]), .Q(registers_23__ap[22]), .QN(), .SE(dftIn), + .SI(registers_19__ap[22]) + ); + AOI22_X1_LVT i_1_0_1127( + .A1(registers_8__ap[22]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[22]), + .ZN(n_1_0_1072) + ); + NAND3_X1_LVT i_1_0_1126( + .A1(n_1_0_1074), .A2(n_1_0_1073), .A3(n_1_0_1072), .ZN(n_1_0_1071) + ); + SDFF_X1_LVT \registers_reg[27][22] ( + .CK(n_0_57), .D(registers[22]), .Q(registers_27__ap[22]), .QN(), .SE(dftIn), + .SI(registers_29__ap[22]) + ); + SDFF_X1_LVT \registers_reg[3][22] ( + .CK(n_0_33), .D(registers[22]), .Q(registers_3__ap[22]), .QN(), .SE(dftIn), + .SI(registers_8__ap[22]) + ); + AOI221_X1_LVT i_1_0_1125( + .A(n_1_0_1071), .B1(n_1_0_1279), .B2(registers_27__ap[22]), .C1(registers_3__ap[22]), + .C2(n_1_0_1257), .ZN(n_1_0_1070) + ); + NAND4_X1_LVT i_1_0_1124( + .A1(n_1_0_1087), .A2(n_1_0_1080), .A3(n_1_0_1075), .A4(n_1_0_1070), .ZN(RRs1[22]) + ); + AND2_X1_LVT i_0_0_21( + .A1(n_0_0_16), .A2(WRd[21]), .ZN(registers[21]) + ); + SDFF_X1_LVT \registers_reg[17][21] ( + .CK(n_0_47), .D(registers[21]), .Q(registers_17__ap[21]), .QN(), .SE(dftIn), + .SI(registers_23__ap[22]) + ); + SDFF_X1_LVT \registers_reg[21][21] ( + .CK(n_0_51), .D(registers[21]), .Q(registers_21__ap[21]), .QN(), .SE(dftIn), + .SI(registers_17__ap[21]) + ); + AOI22_X1_LVT i_1_0_1122( + .A1(registers_17__ap[21]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[21]), + .ZN(n_1_0_1068) + ); + SDFF_X1_LVT \registers_reg[6][21] ( + .CK(n_0_36), .D(registers[21]), .Q(registers_6__ap[21]), .QN(), .SE(dftIn), + .SI(registers_3__ap[22]) + ); + SDFF_X1_LVT \registers_reg[8][21] ( + .CK(n_0_38), .D(registers[21]), .Q(registers_8__ap[21]), .QN(), .SE(dftIn), + .SI(registers_6__ap[21]) + ); + AOI22_X1_LVT i_1_0_1123( + .A1(registers_6__ap[21]), .A2(n_1_0_1300), .B1(n_1_0_1282), .B2(registers_8__ap[21]), + .ZN(n_1_0_1069) + ); + SDFF_X1_LVT \registers_reg[20][21] ( + .CK(n_0_50), .D(registers[21]), .Q(registers_20__ap[21]), .QN(), .SE(dftIn), + .SI(registers_21__ap[21]) + ); + SDFF_X1_LVT \registers_reg[12][21] ( + .CK(n_0_42), .D(registers[21]), .Q(registers_12__ap[21]), .QN(), .SE(dftIn), + .SI(registers_14__ap[22]) + ); + AOI22_X1_LVT i_1_0_1121( + .A1(registers_20__ap[21]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[21]), + .ZN(n_1_0_1067) + ); + SDFF_X1_LVT \registers_reg[5][21] ( + .CK(n_0_35), .D(registers[21]), .Q(registers_5__ap[21]), .QN(), .SE(dftIn), + .SI(registers_8__ap[21]) + ); + SDFF_X1_LVT \registers_reg[11][21] ( + .CK(n_0_41), .D(registers[21]), .Q(registers_11__ap[21]), .QN(), .SE(dftIn), + .SI(registers_12__ap[21]) + ); + AOI22_X1_LVT i_1_0_1120( + .A1(registers_5__ap[21]), .A2(n_1_0_1273), .B1(n_1_0_1270), .B2(registers_11__ap[21]), + .ZN(n_1_0_1066) + ); + NAND3_X1_LVT i_1_0_1119( + .A1(n_1_0_1069), .A2(n_1_0_1067), .A3(n_1_0_1066), .ZN(n_1_0_1065) + ); + SDFF_X1_LVT \registers_reg[10][21] ( + .CK(n_0_40), .D(registers[21]), .Q(registers_10__ap[21]), .QN(), .SE(dftIn), + .SI(registers_11__ap[21]) + ); + SDFF_X1_LVT \registers_reg[2][21] ( + .CK(n_0_32), .D(registers[21]), .Q(registers_2__ap[21]), .QN(), .SE(dftIn), + .SI(registers_27__ap[22]) + ); + AOI221_X1_LVT i_1_0_1118( + .A(n_1_0_1065), .B1(n_1_0_1287), .B2(registers_10__ap[21]), .C1(registers_2__ap[21]), + .C2(n_1_0_1268), .ZN(n_1_0_1064) + ); + SDFF_X1_LVT \registers_reg[13][21] ( + .CK(n_0_43), .D(registers[21]), .Q(registers_13__ap[21]), .QN(), .SE(dftIn), + .SI(registers_10__ap[21]) + ); + SDFF_X1_LVT \registers_reg[30][21] ( + .CK(n_0_60), .D(registers[21]), .Q(registers_30__ap[21]), .QN(), .SE(dftIn), + .SI(registers_2__ap[21]) + ); + SDFF_X1_LVT \registers_reg[22][21] ( + .CK(n_0_52), .D(registers[21]), .Q(registers_22__ap[21]), .QN(), .SE(dftIn), + .SI(registers_20__ap[21]) + ); + AOI222_X1_LVT i_1_0_1117( + .A1(registers_13__ap[21]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[21]), + .C1(registers_22__ap[21]), .C2(n_1_0_1294), .ZN(n_1_0_1063) + ); + NAND2_X1_LVT i_1_0_1116( + .A1(n_1_0_1064), .A2(n_1_0_1063), .ZN(n_1_0_1062) + ); + SDFF_X1_LVT \registers_reg[1][21] ( + .CK(n_0_0), .D(registers[21]), .Q(registers_1__ap[21]), .QN(), .SE(dftIn), + .SI(registers_22__ap[21]) + ); + SDFF_X1_LVT \registers_reg[28][21] ( + .CK(n_0_58), .D(registers[21]), .Q(registers_28__ap[21]), .QN(), .SE(dftIn), + .SI(registers_30__ap[21]) + ); + AOI221_X1_LVT i_1_0_1115( + .A(n_1_0_1062), .B1(n_1_0_1274), .B2(registers_1__ap[21]), .C1(registers_28__ap[21]), + .C2(n_1_0_1283), .ZN(n_1_0_1061) + ); + SDFF_X1_LVT \registers_reg[18][21] ( + .CK(n_0_48), .D(registers[21]), .Q(registers_18__ap[21]), .QN(), .SE(dftIn), + .SI(registers_1__ap[21]) + ); + SDFF_X1_LVT \registers_reg[26][21] ( + .CK(n_0_56), .D(registers[21]), .Q(registers_26__ap[21]), .QN(), .SE(dftIn), + .SI(registers_28__ap[21]) + ); + AOI22_X1_LVT i_1_0_1114( + .A1(registers_18__ap[21]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[21]), + .ZN(n_1_0_1060) + ); + SDFF_X1_LVT \registers_reg[24][21] ( + .CK(n_0_54), .D(registers[21]), .Q(registers_24__ap[21]), .QN(), .SE(dftIn), + .SI(registers_26__ap[21]) + ); + SDFF_X1_LVT \registers_reg[4][21] ( + .CK(n_0_34), .D(registers[21]), .Q(registers_4__ap[21]), .QN(), .SE(dftIn), + .SI(registers_5__ap[21]) + ); + AOI22_X1_LVT i_1_0_1113( + .A1(registers_24__ap[21]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[21]), + .ZN(n_1_0_1059) + ); + SDFF_X1_LVT \registers_reg[15][21] ( + .CK(n_0_45), .D(registers[21]), .Q(registers_15__ap[21]), .QN(), .SE(dftIn), + .SI(registers_13__ap[21]) + ); + SDFF_X1_LVT \registers_reg[16][21] ( + .CK(n_0_46), .D(registers[21]), .Q(registers_16__ap[21]), .QN(), .SE(dftIn), + .SI(registers_15__ap[21]) + ); + AOI22_X1_LVT i_1_0_1112( + .A1(registers_15__ap[21]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[21]), + .ZN(n_1_0_1058) + ); + NAND3_X1_LVT i_1_0_1111( + .A1(n_1_0_1060), .A2(n_1_0_1059), .A3(n_1_0_1058), .ZN(n_1_0_1057) + ); + SDFF_X1_LVT \registers_reg[19][21] ( + .CK(n_0_49), .D(registers[21]), .Q(registers_19__ap[21]), .QN(), .SE(dftIn), + .SI(registers_18__ap[21]) + ); + SDFF_X1_LVT \registers_reg[25][21] ( + .CK(n_0_55), .D(registers[21]), .Q(registers_25__ap[21]), .QN(), .SE(dftIn), + .SI(registers_24__ap[21]) + ); + AOI221_X1_LVT i_1_0_1110( + .A(n_1_0_1057), .B1(n_1_0_1295), .B2(registers_19__ap[21]), .C1(registers_25__ap[21]), + .C2(n_1_0_1269), .ZN(n_1_0_1056) + ); + SDFF_X1_LVT \registers_reg[7][21] ( + .CK(n_0_37), .D(registers[21]), .Q(registers_7__ap[21]), .QN(), .SE(dftIn), + .SI(registers_4__ap[21]) + ); + SDFF_X1_LVT \registers_reg[14][21] ( + .CK(n_0_44), .D(registers[21]), .Q(registers_14__ap[21]), .QN(), .SE(dftIn), + .SI(registers_16__ap[21]) + ); + AOI22_X1_LVT i_1_0_1109( + .A1(registers_7__ap[21]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[21]), + .ZN(n_1_0_1055) + ); + SDFF_X1_LVT \registers_reg[9][21] ( + .CK(n_0_39), .D(registers[21]), .Q(registers_9__ap[21]), .QN(), .SE(dftIn), + .SI(registers_7__ap[21]) + ); + SDFF_X1_LVT \registers_reg[29][21] ( + .CK(n_0_59), .D(registers[21]), .Q(registers_29__ap[21]), .QN(), .SE(dftIn), + .SI(registers_25__ap[21]) + ); + AOI22_X1_LVT i_1_0_1108( + .A1(registers_9__ap[21]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[21]), + .ZN(n_1_0_1054) + ); + SDFF_X1_LVT \registers_reg[23][21] ( + .CK(n_0_53), .D(registers[21]), .Q(registers_23__ap[21]), .QN(), .SE(dftIn), + .SI(registers_19__ap[21]) + ); + SDFF_X1_LVT \registers_reg[3][21] ( + .CK(n_0_33), .D(registers[21]), .Q(registers_3__ap[21]), .QN(), .SE(dftIn), + .SI(registers_9__ap[21]) + ); + AOI22_X1_LVT i_1_0_1107( + .A1(registers_23__ap[21]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[21]), + .ZN(n_1_0_1053) + ); + NAND3_X1_LVT i_1_0_1106( + .A1(n_1_0_1055), .A2(n_1_0_1054), .A3(n_1_0_1053), .ZN(n_1_0_1052) + ); + SDFF_X1_LVT \registers_reg[27][21] ( + .CK(n_0_57), .D(registers[21]), .Q(registers_27__ap[21]), .QN(), .SE(dftIn), + .SI(registers_29__ap[21]) + ); + SDFF_X1_LVT \registers_reg[31][21] ( + .CK(n_0_61), .D(registers[21]), .Q(registers_31__ap[21]), .QN(), .SE(dftIn), + .SI(registers_3__ap[21]) + ); + AOI221_X1_LVT i_1_0_1105( + .A(n_1_0_1052), .B1(n_1_0_1279), .B2(registers_27__ap[21]), .C1(registers_31__ap[21]), + .C2(n_1_0_1266), .ZN(n_1_0_1051) + ); + NAND4_X1_LVT i_1_0_1104( + .A1(n_1_0_1068), .A2(n_1_0_1061), .A3(n_1_0_1056), .A4(n_1_0_1051), .ZN(RRs1[21]) + ); + AND2_X1_LVT i_0_0_20( + .A1(n_0_0_16), .A2(WRd[20]), .ZN(registers[20]) + ); + SDFF_X1_LVT \registers_reg[17][20] ( + .CK(n_0_47), .D(registers[20]), .Q(registers_17__ap[20]), .QN(), .SE(dftIn), + .SI(registers_23__ap[21]) + ); + SDFF_X1_LVT \registers_reg[21][20] ( + .CK(n_0_51), .D(registers[20]), .Q(registers_21__ap[20]), .QN(), .SE(dftIn), + .SI(registers_17__ap[20]) + ); + AOI22_X1_LVT i_1_0_1100( + .A1(registers_17__ap[20]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[20]), + .ZN(n_1_0_1047) + ); + SDFF_X1_LVT \registers_reg[10][20] ( + .CK(n_0_40), .D(registers[20]), .Q(registers_10__ap[20]), .QN(), .SE(dftIn), + .SI(registers_14__ap[21]) + ); + SDFF_X1_LVT \registers_reg[2][20] ( + .CK(n_0_32), .D(registers[20]), .Q(registers_2__ap[20]), .QN(), .SE(dftIn), + .SI(registers_27__ap[21]) + ); + AOI22_X1_LVT i_1_0_1103( + .A1(registers_10__ap[20]), .A2(n_1_0_1287), .B1(n_1_0_1268), .B2(registers_2__ap[20]), + .ZN(n_1_0_1050) + ); + SDFF_X1_LVT \registers_reg[20][20] ( + .CK(n_0_50), .D(registers[20]), .Q(registers_20__ap[20]), .QN(), .SE(dftIn), + .SI(registers_21__ap[20]) + ); + SDFF_X1_LVT \registers_reg[12][20] ( + .CK(n_0_42), .D(registers[20]), .Q(registers_12__ap[20]), .QN(), .SE(dftIn), + .SI(registers_10__ap[20]) + ); + AOI22_X1_LVT i_1_0_1099( + .A1(registers_20__ap[20]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[20]), + .ZN(n_1_0_1046) + ); + SDFF_X1_LVT \registers_reg[15][20] ( + .CK(n_0_45), .D(registers[20]), .Q(registers_15__ap[20]), .QN(), .SE(dftIn), + .SI(registers_12__ap[20]) + ); + SDFF_X1_LVT \registers_reg[8][20] ( + .CK(n_0_38), .D(registers[20]), .Q(registers_8__ap[20]), .QN(), .SE(dftIn), + .SI(registers_31__ap[21]) + ); + AOI22_X1_LVT i_1_0_1102( + .A1(registers_15__ap[20]), .A2(n_1_0_1286), .B1(n_1_0_1282), .B2(registers_8__ap[20]), + .ZN(n_1_0_1049) + ); + INV_X1_LVT i_1_0_1101( + .A(n_1_0_1049), .ZN(n_1_0_1048) + ); + SDFF_X1_LVT \registers_reg[11][20] ( + .CK(n_0_41), .D(registers[20]), .Q(registers_11__ap[20]), .QN(), .SE(dftIn), + .SI(registers_15__ap[20]) + ); + SDFF_X1_LVT \registers_reg[5][20] ( + .CK(n_0_35), .D(registers[20]), .Q(registers_5__ap[20]), .QN(), .SE(dftIn), + .SI(registers_8__ap[20]) + ); + AOI221_X1_LVT i_1_0_1098( + .A(n_1_0_1048), .B1(n_1_0_1270), .B2(registers_11__ap[20]), .C1(registers_5__ap[20]), + .C2(n_1_0_1273), .ZN(n_1_0_1045) + ); + SDFF_X1_LVT \registers_reg[13][20] ( + .CK(n_0_43), .D(registers[20]), .Q(registers_13__ap[20]), .QN(), .SE(dftIn), + .SI(registers_11__ap[20]) + ); + SDFF_X1_LVT \registers_reg[30][20] ( + .CK(n_0_60), .D(registers[20]), .Q(registers_30__ap[20]), .QN(), .SE(dftIn), + .SI(registers_2__ap[20]) + ); + SDFF_X1_LVT \registers_reg[22][20] ( + .CK(n_0_52), .D(registers[20]), .Q(registers_22__ap[20]), .QN(), .SE(dftIn), + .SI(registers_20__ap[20]) + ); + AOI222_X1_LVT i_1_0_1097( + .A1(registers_13__ap[20]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[20]), + .C1(registers_22__ap[20]), .C2(n_1_0_1294), .ZN(n_1_0_1044) + ); + NAND4_X1_LVT i_1_0_1096( + .A1(n_1_0_1050), .A2(n_1_0_1046), .A3(n_1_0_1045), .A4(n_1_0_1044), .ZN(n_1_0_1043) + ); + SDFF_X1_LVT \registers_reg[1][20] ( + .CK(n_0_0), .D(registers[20]), .Q(registers_1__ap[20]), .QN(), .SE(dftIn), + .SI(registers_22__ap[20]) + ); + SDFF_X1_LVT \registers_reg[28][20] ( + .CK(n_0_58), .D(registers[20]), .Q(registers_28__ap[20]), .QN(), .SE(dftIn), + .SI(registers_30__ap[20]) + ); + AOI221_X1_LVT i_1_0_1095( + .A(n_1_0_1043), .B1(n_1_0_1274), .B2(registers_1__ap[20]), .C1(registers_28__ap[20]), + .C2(n_1_0_1283), .ZN(n_1_0_1042) + ); + SDFF_X1_LVT \registers_reg[18][20] ( + .CK(n_0_48), .D(registers[20]), .Q(registers_18__ap[20]), .QN(), .SE(dftIn), + .SI(registers_1__ap[20]) + ); + SDFF_X1_LVT \registers_reg[26][20] ( + .CK(n_0_56), .D(registers[20]), .Q(registers_26__ap[20]), .QN(), .SE(dftIn), + .SI(registers_28__ap[20]) + ); + AOI22_X1_LVT i_1_0_1094( + .A1(registers_18__ap[20]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[20]), + .ZN(n_1_0_1041) + ); + SDFF_X1_LVT \registers_reg[24][20] ( + .CK(n_0_54), .D(registers[20]), .Q(registers_24__ap[20]), .QN(), .SE(dftIn), + .SI(registers_26__ap[20]) + ); + SDFF_X1_LVT \registers_reg[4][20] ( + .CK(n_0_34), .D(registers[20]), .Q(registers_4__ap[20]), .QN(), .SE(dftIn), + .SI(registers_5__ap[20]) + ); + AOI22_X1_LVT i_1_0_1093( + .A1(registers_24__ap[20]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[20]), + .ZN(n_1_0_1040) + ); + SDFF_X1_LVT \registers_reg[6][20] ( + .CK(n_0_36), .D(registers[20]), .Q(registers_6__ap[20]), .QN(), .SE(dftIn), + .SI(registers_4__ap[20]) + ); + SDFF_X1_LVT \registers_reg[25][20] ( + .CK(n_0_55), .D(registers[20]), .Q(registers_25__ap[20]), .QN(), .SE(dftIn), + .SI(registers_24__ap[20]) + ); + AOI22_X1_LVT i_1_0_1092( + .A1(registers_6__ap[20]), .A2(n_1_0_1300), .B1(n_1_0_1269), .B2(registers_25__ap[20]), + .ZN(n_1_0_1039) + ); + NAND3_X1_LVT i_1_0_1091( + .A1(n_1_0_1041), .A2(n_1_0_1040), .A3(n_1_0_1039), .ZN(n_1_0_1038) + ); + SDFF_X1_LVT \registers_reg[19][20] ( + .CK(n_0_49), .D(registers[20]), .Q(registers_19__ap[20]), .QN(), .SE(dftIn), + .SI(registers_18__ap[20]) + ); + SDFF_X1_LVT \registers_reg[16][20] ( + .CK(n_0_46), .D(registers[20]), .Q(registers_16__ap[20]), .QN(), .SE(dftIn), + .SI(registers_13__ap[20]) + ); + AOI221_X1_LVT i_1_0_1090( + .A(n_1_0_1038), .B1(n_1_0_1295), .B2(registers_19__ap[20]), .C1(registers_16__ap[20]), + .C2(n_1_0_1267), .ZN(n_1_0_1037) + ); + SDFF_X1_LVT \registers_reg[7][20] ( + .CK(n_0_37), .D(registers[20]), .Q(registers_7__ap[20]), .QN(), .SE(dftIn), + .SI(registers_6__ap[20]) + ); + SDFF_X1_LVT \registers_reg[14][20] ( + .CK(n_0_44), .D(registers[20]), .Q(registers_14__ap[20]), .QN(), .SE(dftIn), + .SI(registers_16__ap[20]) + ); + AOI22_X1_LVT i_1_0_1089( + .A1(registers_7__ap[20]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[20]), + .ZN(n_1_0_1036) + ); + SDFF_X1_LVT \registers_reg[9][20] ( + .CK(n_0_39), .D(registers[20]), .Q(registers_9__ap[20]), .QN(), .SE(dftIn), + .SI(registers_7__ap[20]) + ); + SDFF_X1_LVT \registers_reg[29][20] ( + .CK(n_0_59), .D(registers[20]), .Q(registers_29__ap[20]), .QN(), .SE(dftIn), + .SI(registers_25__ap[20]) + ); + AOI22_X1_LVT i_1_0_1088( + .A1(registers_9__ap[20]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[20]), + .ZN(n_1_0_1035) + ); + SDFF_X1_LVT \registers_reg[23][20] ( + .CK(n_0_53), .D(registers[20]), .Q(registers_23__ap[20]), .QN(), .SE(dftIn), + .SI(registers_19__ap[20]) + ); + SDFF_X1_LVT \registers_reg[3][20] ( + .CK(n_0_33), .D(registers[20]), .Q(registers_3__ap[20]), .QN(), .SE(dftIn), + .SI(registers_9__ap[20]) + ); + AOI22_X1_LVT i_1_0_1087( + .A1(registers_23__ap[20]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[20]), + .ZN(n_1_0_1034) + ); + NAND3_X1_LVT i_1_0_1086( + .A1(n_1_0_1036), .A2(n_1_0_1035), .A3(n_1_0_1034), .ZN(n_1_0_1033) + ); + SDFF_X1_LVT \registers_reg[27][20] ( + .CK(n_0_57), .D(registers[20]), .Q(registers_27__ap[20]), .QN(), .SE(dftIn), + .SI(registers_29__ap[20]) + ); + SDFF_X1_LVT \registers_reg[31][20] ( + .CK(n_0_61), .D(registers[20]), .Q(registers_31__ap[20]), .QN(), .SE(dftIn), + .SI(registers_3__ap[20]) + ); + AOI221_X1_LVT i_1_0_1085( + .A(n_1_0_1033), .B1(n_1_0_1279), .B2(registers_27__ap[20]), .C1(registers_31__ap[20]), + .C2(n_1_0_1266), .ZN(n_1_0_1032) + ); + NAND4_X1_LVT i_1_0_1084( + .A1(n_1_0_1047), .A2(n_1_0_1042), .A3(n_1_0_1037), .A4(n_1_0_1032), .ZN(RRs1[20]) + ); + AND2_X1_LVT i_0_0_19( + .A1(n_0_0_16), .A2(WRd[19]), .ZN(registers[19]) + ); + SDFF_X1_LVT \registers_reg[17][19] ( + .CK(n_0_47), .D(registers[19]), .Q(registers_17__ap[19]), .QN(), .SE(dftIn), + .SI(registers_23__ap[20]) + ); + SDFF_X1_LVT \registers_reg[21][19] ( + .CK(n_0_51), .D(registers[19]), .Q(registers_21__ap[19]), .QN(), .SE(dftIn), + .SI(registers_17__ap[19]) + ); + AOI22_X1_LVT i_1_0_1080( + .A1(registers_17__ap[19]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[19]), + .ZN(n_1_0_1028) + ); + SDFF_X1_LVT \registers_reg[2][19] ( + .CK(n_0_32), .D(registers[19]), .Q(registers_2__ap[19]), .QN(), .SE(dftIn), + .SI(registers_27__ap[20]) + ); + SDFF_X1_LVT \registers_reg[31][19] ( + .CK(n_0_61), .D(registers[19]), .Q(registers_31__ap[19]), .QN(), .SE(dftIn), + .SI(registers_31__ap[20]) + ); + AOI22_X1_LVT i_1_0_1083( + .A1(registers_2__ap[19]), .A2(n_1_0_1268), .B1(n_1_0_1266), .B2(registers_31__ap[19]), + .ZN(n_1_0_1031) + ); + SDFF_X1_LVT \registers_reg[20][19] ( + .CK(n_0_50), .D(registers[19]), .Q(registers_20__ap[19]), .QN(), .SE(dftIn), + .SI(registers_21__ap[19]) + ); + SDFF_X1_LVT \registers_reg[12][19] ( + .CK(n_0_42), .D(registers[19]), .Q(registers_12__ap[19]), .QN(), .SE(dftIn), + .SI(registers_14__ap[20]) + ); + AOI22_X1_LVT i_1_0_1079( + .A1(registers_20__ap[19]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[19]), + .ZN(n_1_0_1027) + ); + SDFF_X1_LVT \registers_reg[15][19] ( + .CK(n_0_45), .D(registers[19]), .Q(registers_15__ap[19]), .QN(), .SE(dftIn), + .SI(registers_12__ap[19]) + ); + SDFF_X1_LVT \registers_reg[11][19] ( + .CK(n_0_41), .D(registers[19]), .Q(registers_11__ap[19]), .QN(), .SE(dftIn), + .SI(registers_15__ap[19]) + ); + AOI22_X1_LVT i_1_0_1082( + .A1(registers_15__ap[19]), .A2(n_1_0_1286), .B1(n_1_0_1270), .B2(registers_11__ap[19]), + .ZN(n_1_0_1030) + ); + INV_X1_LVT i_1_0_1081( + .A(n_1_0_1030), .ZN(n_1_0_1029) + ); + SDFF_X1_LVT \registers_reg[27][19] ( + .CK(n_0_57), .D(registers[19]), .Q(registers_27__ap[19]), .QN(), .SE(dftIn), + .SI(registers_2__ap[19]) + ); + SDFF_X1_LVT \registers_reg[24][19] ( + .CK(n_0_54), .D(registers[19]), .Q(registers_24__ap[19]), .QN(), .SE(dftIn), + .SI(registers_27__ap[19]) + ); + AOI221_X1_LVT i_1_0_1078( + .A(n_1_0_1029), .B1(n_1_0_1279), .B2(registers_27__ap[19]), .C1(registers_24__ap[19]), + .C2(n_1_0_1289), .ZN(n_1_0_1026) + ); + SDFF_X1_LVT \registers_reg[22][19] ( + .CK(n_0_52), .D(registers[19]), .Q(registers_22__ap[19]), .QN(), .SE(dftIn), + .SI(registers_20__ap[19]) + ); + SDFF_X1_LVT \registers_reg[26][19] ( + .CK(n_0_56), .D(registers[19]), .Q(registers_26__ap[19]), .QN(), .SE(dftIn), + .SI(registers_24__ap[19]) + ); + SDFF_X1_LVT \registers_reg[13][19] ( + .CK(n_0_43), .D(registers[19]), .Q(registers_13__ap[19]), .QN(), .SE(dftIn), + .SI(registers_11__ap[19]) + ); + AOI222_X1_LVT i_1_0_1077( + .A1(registers_22__ap[19]), .A2(n_1_0_1294), .B1(n_1_0_1285), .B2(registers_26__ap[19]), + .C1(n_1_0_1277), .C2(registers_13__ap[19]), .ZN(n_1_0_1025) + ); + NAND4_X1_LVT i_1_0_1076( + .A1(n_1_0_1031), .A2(n_1_0_1027), .A3(n_1_0_1026), .A4(n_1_0_1025), .ZN(n_1_0_1024) + ); + SDFF_X1_LVT \registers_reg[1][19] ( + .CK(n_0_0), .D(registers[19]), .Q(registers_1__ap[19]), .QN(), .SE(dftIn), + .SI(registers_22__ap[19]) + ); + SDFF_X1_LVT \registers_reg[28][19] ( + .CK(n_0_58), .D(registers[19]), .Q(registers_28__ap[19]), .QN(), .SE(dftIn), + .SI(registers_26__ap[19]) + ); + AOI221_X1_LVT i_1_0_1075( + .A(n_1_0_1024), .B1(n_1_0_1274), .B2(registers_1__ap[19]), .C1(registers_28__ap[19]), + .C2(n_1_0_1283), .ZN(n_1_0_1023) + ); + SDFF_X1_LVT \registers_reg[18][19] ( + .CK(n_0_48), .D(registers[19]), .Q(registers_18__ap[19]), .QN(), .SE(dftIn), + .SI(registers_1__ap[19]) + ); + SDFF_X1_LVT \registers_reg[30][19] ( + .CK(n_0_60), .D(registers[19]), .Q(registers_30__ap[19]), .QN(), .SE(dftIn), + .SI(registers_28__ap[19]) + ); + AOI22_X1_LVT i_1_0_1074( + .A1(registers_18__ap[19]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[19]), + .ZN(n_1_0_1022) + ); + SDFF_X1_LVT \registers_reg[4][19] ( + .CK(n_0_34), .D(registers[19]), .Q(registers_4__ap[19]), .QN(), .SE(dftIn), + .SI(registers_31__ap[19]) + ); + SDFF_X1_LVT \registers_reg[5][19] ( + .CK(n_0_35), .D(registers[19]), .Q(registers_5__ap[19]), .QN(), .SE(dftIn), + .SI(registers_4__ap[19]) + ); + AOI22_X1_LVT i_1_0_1073( + .A1(registers_4__ap[19]), .A2(n_1_0_1278), .B1(n_1_0_1273), .B2(registers_5__ap[19]), + .ZN(n_1_0_1021) + ); + SDFF_X1_LVT \registers_reg[6][19] ( + .CK(n_0_36), .D(registers[19]), .Q(registers_6__ap[19]), .QN(), .SE(dftIn), + .SI(registers_5__ap[19]) + ); + SDFF_X1_LVT \registers_reg[25][19] ( + .CK(n_0_55), .D(registers[19]), .Q(registers_25__ap[19]), .QN(), .SE(dftIn), + .SI(registers_30__ap[19]) + ); + AOI22_X1_LVT i_1_0_1072( + .A1(registers_6__ap[19]), .A2(n_1_0_1300), .B1(n_1_0_1269), .B2(registers_25__ap[19]), + .ZN(n_1_0_1020) + ); + NAND3_X1_LVT i_1_0_1071( + .A1(n_1_0_1022), .A2(n_1_0_1021), .A3(n_1_0_1020), .ZN(n_1_0_1019) + ); + SDFF_X1_LVT \registers_reg[19][19] ( + .CK(n_0_49), .D(registers[19]), .Q(registers_19__ap[19]), .QN(), .SE(dftIn), + .SI(registers_18__ap[19]) + ); + SDFF_X1_LVT \registers_reg[16][19] ( + .CK(n_0_46), .D(registers[19]), .Q(registers_16__ap[19]), .QN(), .SE(dftIn), + .SI(registers_13__ap[19]) + ); + AOI221_X1_LVT i_1_0_1070( + .A(n_1_0_1019), .B1(n_1_0_1295), .B2(registers_19__ap[19]), .C1(registers_16__ap[19]), + .C2(n_1_0_1267), .ZN(n_1_0_1018) + ); + SDFF_X1_LVT \registers_reg[9][19] ( + .CK(n_0_39), .D(registers[19]), .Q(registers_9__ap[19]), .QN(), .SE(dftIn), + .SI(registers_6__ap[19]) + ); + SDFF_X1_LVT \registers_reg[29][19] ( + .CK(n_0_59), .D(registers[19]), .Q(registers_29__ap[19]), .QN(), .SE(dftIn), + .SI(registers_25__ap[19]) + ); + AOI22_X1_LVT i_1_0_1069( + .A1(registers_9__ap[19]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[19]), + .ZN(n_1_0_1017) + ); + SDFF_X1_LVT \registers_reg[8][19] ( + .CK(n_0_38), .D(registers[19]), .Q(registers_8__ap[19]), .QN(), .SE(dftIn), + .SI(registers_9__ap[19]) + ); + SDFF_X1_LVT \registers_reg[23][19] ( + .CK(n_0_53), .D(registers[19]), .Q(registers_23__ap[19]), .QN(), .SE(dftIn), + .SI(registers_19__ap[19]) + ); + AOI22_X1_LVT i_1_0_1068( + .A1(registers_8__ap[19]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[19]), + .ZN(n_1_0_1016) + ); + SDFF_X1_LVT \registers_reg[7][19] ( + .CK(n_0_37), .D(registers[19]), .Q(registers_7__ap[19]), .QN(), .SE(dftIn), + .SI(registers_8__ap[19]) + ); + SDFF_X1_LVT \registers_reg[14][19] ( + .CK(n_0_44), .D(registers[19]), .Q(registers_14__ap[19]), .QN(), .SE(dftIn), + .SI(registers_16__ap[19]) + ); + AOI22_X1_LVT i_1_0_1067( + .A1(registers_7__ap[19]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[19]), + .ZN(n_1_0_1015) + ); + NAND3_X1_LVT i_1_0_1066( + .A1(n_1_0_1017), .A2(n_1_0_1016), .A3(n_1_0_1015), .ZN(n_1_0_1014) + ); + SDFF_X1_LVT \registers_reg[10][19] ( + .CK(n_0_40), .D(registers[19]), .Q(registers_10__ap[19]), .QN(), .SE(dftIn), + .SI(registers_14__ap[19]) + ); + SDFF_X1_LVT \registers_reg[3][19] ( + .CK(n_0_33), .D(registers[19]), .Q(registers_3__ap[19]), .QN(), .SE(dftIn), + .SI(registers_7__ap[19]) + ); + AOI221_X1_LVT i_1_0_1065( + .A(n_1_0_1014), .B1(n_1_0_1287), .B2(registers_10__ap[19]), .C1(registers_3__ap[19]), + .C2(n_1_0_1257), .ZN(n_1_0_1013) + ); + NAND4_X1_LVT i_1_0_1064( + .A1(n_1_0_1028), .A2(n_1_0_1023), .A3(n_1_0_1018), .A4(n_1_0_1013), .ZN(RRs1[19]) + ); + AND2_X1_LVT i_0_0_18( + .A1(n_0_0_16), .A2(WRd[18]), .ZN(registers[18]) + ); + SDFF_X1_LVT \registers_reg[24][18] ( + .CK(n_0_54), .D(registers[18]), .Q(registers_24__ap[18]), .QN(), .SE(dftIn), + .SI(registers_29__ap[19]) + ); + SDFF_X1_LVT \registers_reg[28][18] ( + .CK(n_0_58), .D(registers[18]), .Q(registers_28__ap[18]), .QN(), .SE(dftIn), + .SI(registers_24__ap[18]) + ); + AOI22_X1_LVT i_1_0_1062( + .A1(registers_24__ap[18]), .A2(n_1_0_1289), .B1(n_1_0_1283), .B2(registers_28__ap[18]), + .ZN(n_1_0_1011) + ); + SDFF_X1_LVT \registers_reg[11][18] ( + .CK(n_0_41), .D(registers[18]), .Q(registers_11__ap[18]), .QN(), .SE(dftIn), + .SI(registers_10__ap[19]) + ); + SDFF_X1_LVT \registers_reg[16][18] ( + .CK(n_0_46), .D(registers[18]), .Q(registers_16__ap[18]), .QN(), .SE(dftIn), + .SI(registers_11__ap[18]) + ); + AOI22_X1_LVT i_1_0_1063( + .A1(registers_11__ap[18]), .A2(n_1_0_1270), .B1(n_1_0_1267), .B2(registers_16__ap[18]), + .ZN(n_1_0_1012) + ); + SDFF_X1_LVT \registers_reg[9][18] ( + .CK(n_0_39), .D(registers[18]), .Q(registers_9__ap[18]), .QN(), .SE(dftIn), + .SI(registers_3__ap[19]) + ); + SDFF_X1_LVT \registers_reg[7][18] ( + .CK(n_0_37), .D(registers[18]), .Q(registers_7__ap[18]), .QN(), .SE(dftIn), + .SI(registers_9__ap[18]) + ); + AOI22_X1_LVT i_1_0_1061( + .A1(registers_9__ap[18]), .A2(n_1_0_1291), .B1(n_1_0_1263), .B2(registers_7__ap[18]), + .ZN(n_1_0_1010) + ); + SDFF_X1_LVT \registers_reg[27][18] ( + .CK(n_0_57), .D(registers[18]), .Q(registers_27__ap[18]), .QN(), .SE(dftIn), + .SI(registers_28__ap[18]) + ); + SDFF_X1_LVT \registers_reg[25][18] ( + .CK(n_0_55), .D(registers[18]), .Q(registers_25__ap[18]), .QN(), .SE(dftIn), + .SI(registers_27__ap[18]) + ); + AOI22_X1_LVT i_1_0_1060( + .A1(registers_27__ap[18]), .A2(n_1_0_1279), .B1(n_1_0_1269), .B2(registers_25__ap[18]), + .ZN(n_1_0_1009) + ); + NAND3_X1_LVT i_1_0_1059( + .A1(n_1_0_1012), .A2(n_1_0_1010), .A3(n_1_0_1009), .ZN(n_1_0_1008) + ); + SDFF_X1_LVT \registers_reg[31][18] ( + .CK(n_0_61), .D(registers[18]), .Q(registers_31__ap[18]), .QN(), .SE(dftIn), + .SI(registers_7__ap[18]) + ); + SDFF_X1_LVT \registers_reg[6][18] ( + .CK(n_0_36), .D(registers[18]), .Q(registers_6__ap[18]), .QN(), .SE(dftIn), + .SI(registers_31__ap[18]) + ); + AOI221_X1_LVT i_1_0_1058( + .A(n_1_0_1008), .B1(n_1_0_1266), .B2(registers_31__ap[18]), .C1(registers_6__ap[18]), + .C2(n_1_0_1300), .ZN(n_1_0_1007) + ); + SDFF_X1_LVT \registers_reg[22][18] ( + .CK(n_0_52), .D(registers[18]), .Q(registers_22__ap[18]), .QN(), .SE(dftIn), + .SI(registers_23__ap[19]) + ); + SDFF_X1_LVT \registers_reg[26][18] ( + .CK(n_0_56), .D(registers[18]), .Q(registers_26__ap[18]), .QN(), .SE(dftIn), + .SI(registers_25__ap[18]) + ); + SDFF_X1_LVT \registers_reg[1][18] ( + .CK(n_0_0), .D(registers[18]), .Q(registers_1__ap[18]), .QN(), .SE(dftIn), + .SI(registers_22__ap[18]) + ); + AOI222_X1_LVT i_1_0_1057( + .A1(registers_22__ap[18]), .A2(n_1_0_1294), .B1(n_1_0_1285), .B2(registers_26__ap[18]), + .C1(n_1_0_1274), .C2(registers_1__ap[18]), .ZN(n_1_0_1006) + ); + NAND2_X1_LVT i_1_0_1056( + .A1(n_1_0_1007), .A2(n_1_0_1006), .ZN(n_1_0_1005) + ); + SDFF_X1_LVT \registers_reg[29][18] ( + .CK(n_0_59), .D(registers[18]), .Q(registers_29__ap[18]), .QN(), .SE(dftIn), + .SI(registers_26__ap[18]) + ); + SDFF_X1_LVT \registers_reg[2][18] ( + .CK(n_0_32), .D(registers[18]), .Q(registers_2__ap[18]), .QN(), .SE(dftIn), + .SI(registers_29__ap[18]) + ); + AOI221_X1_LVT i_1_0_1055( + .A(n_1_0_1005), .B1(n_1_0_1276), .B2(registers_29__ap[18]), .C1(registers_2__ap[18]), + .C2(n_1_0_1268), .ZN(n_1_0_1004) + ); + SDFF_X1_LVT \registers_reg[18][18] ( + .CK(n_0_48), .D(registers[18]), .Q(registers_18__ap[18]), .QN(), .SE(dftIn), + .SI(registers_1__ap[18]) + ); + SDFF_X1_LVT \registers_reg[30][18] ( + .CK(n_0_60), .D(registers[18]), .Q(registers_30__ap[18]), .QN(), .SE(dftIn), + .SI(registers_2__ap[18]) + ); + AOI22_X1_LVT i_1_0_1054( + .A1(registers_18__ap[18]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[18]), + .ZN(n_1_0_1003) + ); + SDFF_X1_LVT \registers_reg[4][18] ( + .CK(n_0_34), .D(registers[18]), .Q(registers_4__ap[18]), .QN(), .SE(dftIn), + .SI(registers_6__ap[18]) + ); + SDFF_X1_LVT \registers_reg[12][18] ( + .CK(n_0_42), .D(registers[18]), .Q(registers_12__ap[18]), .QN(), .SE(dftIn), + .SI(registers_16__ap[18]) + ); + AOI22_X1_LVT i_1_0_1053( + .A1(registers_4__ap[18]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[18]), + .ZN(n_1_0_1002) + ); + SDFF_X1_LVT \registers_reg[19][18] ( + .CK(n_0_49), .D(registers[18]), .Q(registers_19__ap[18]), .QN(), .SE(dftIn), + .SI(registers_18__ap[18]) + ); + SDFF_X1_LVT \registers_reg[21][18] ( + .CK(n_0_51), .D(registers[18]), .Q(registers_21__ap[18]), .QN(), .SE(dftIn), + .SI(registers_19__ap[18]) + ); + AOI22_X1_LVT i_1_0_1052( + .A1(registers_19__ap[18]), .A2(n_1_0_1295), .B1(n_1_0_1259), .B2(registers_21__ap[18]), + .ZN(n_1_0_1001) + ); + NAND3_X1_LVT i_1_0_1051( + .A1(n_1_0_1003), .A2(n_1_0_1002), .A3(n_1_0_1001), .ZN(n_1_0_1000) + ); + SDFF_X1_LVT \registers_reg[5][18] ( + .CK(n_0_35), .D(registers[18]), .Q(registers_5__ap[18]), .QN(), .SE(dftIn), + .SI(registers_4__ap[18]) + ); + SDFF_X1_LVT \registers_reg[20][18] ( + .CK(n_0_50), .D(registers[18]), .Q(registers_20__ap[18]), .QN(), .SE(dftIn), + .SI(registers_21__ap[18]) + ); + AOI221_X1_LVT i_1_0_1050( + .A(n_1_0_1000), .B1(n_1_0_1273), .B2(registers_5__ap[18]), .C1(registers_20__ap[18]), + .C2(n_1_0_1281), .ZN(n_1_0_999) + ); + SDFF_X1_LVT \registers_reg[8][18] ( + .CK(n_0_38), .D(registers[18]), .Q(registers_8__ap[18]), .QN(), .SE(dftIn), + .SI(registers_5__ap[18]) + ); + SDFF_X1_LVT \registers_reg[23][18] ( + .CK(n_0_53), .D(registers[18]), .Q(registers_23__ap[18]), .QN(), .SE(dftIn), + .SI(registers_20__ap[18]) + ); + AOI22_X1_LVT i_1_0_1049( + .A1(registers_8__ap[18]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[18]), + .ZN(n_1_0_998) + ); + SDFF_X1_LVT \registers_reg[13][18] ( + .CK(n_0_43), .D(registers[18]), .Q(registers_13__ap[18]), .QN(), .SE(dftIn), + .SI(registers_12__ap[18]) + ); + SDFF_X1_LVT \registers_reg[17][18] ( + .CK(n_0_47), .D(registers[18]), .Q(registers_17__ap[18]), .QN(), .SE(dftIn), + .SI(registers_23__ap[18]) + ); + AOI22_X1_LVT i_1_0_1048( + .A1(registers_13__ap[18]), .A2(n_1_0_1277), .B1(n_1_0_1271), .B2(registers_17__ap[18]), + .ZN(n_1_0_997) + ); + SDFF_X1_LVT \registers_reg[15][18] ( + .CK(n_0_45), .D(registers[18]), .Q(registers_15__ap[18]), .QN(), .SE(dftIn), + .SI(registers_13__ap[18]) + ); + SDFF_X1_LVT \registers_reg[14][18] ( + .CK(n_0_44), .D(registers[18]), .Q(registers_14__ap[18]), .QN(), .SE(dftIn), + .SI(registers_15__ap[18]) + ); + AOI22_X1_LVT i_1_0_1047( + .A1(registers_15__ap[18]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[18]), + .ZN(n_1_0_996) + ); + NAND3_X1_LVT i_1_0_1046( + .A1(n_1_0_998), .A2(n_1_0_997), .A3(n_1_0_996), .ZN(n_1_0_995) + ); + SDFF_X1_LVT \registers_reg[10][18] ( + .CK(n_0_40), .D(registers[18]), .Q(registers_10__ap[18]), .QN(), .SE(dftIn), + .SI(registers_14__ap[18]) + ); + SDFF_X1_LVT \registers_reg[3][18] ( + .CK(n_0_33), .D(registers[18]), .Q(registers_3__ap[18]), .QN(), .SE(dftIn), + .SI(registers_8__ap[18]) + ); + AOI221_X1_LVT i_1_0_1045( + .A(n_1_0_995), .B1(n_1_0_1287), .B2(registers_10__ap[18]), .C1(registers_3__ap[18]), + .C2(n_1_0_1257), .ZN(n_1_0_994) + ); + NAND4_X1_LVT i_1_0_1044( + .A1(n_1_0_1011), .A2(n_1_0_1004), .A3(n_1_0_999), .A4(n_1_0_994), .ZN(RRs1[18]) + ); + AND2_X1_LVT i_0_0_17( + .A1(n_0_0_16), .A2(WRd[17]), .ZN(registers[17]) + ); + SDFF_X1_LVT \registers_reg[17][17] ( + .CK(n_0_47), .D(registers[17]), .Q(registers_17__ap[17]), .QN(), .SE(dftIn), + .SI(registers_17__ap[18]) + ); + SDFF_X1_LVT \registers_reg[21][17] ( + .CK(n_0_51), .D(registers[17]), .Q(registers_21__ap[17]), .QN(), .SE(dftIn), + .SI(registers_17__ap[17]) + ); + AOI22_X1_LVT i_1_0_1040( + .A1(registers_17__ap[17]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[17]), + .ZN(n_1_0_990) + ); + SDFF_X1_LVT \registers_reg[2][17] ( + .CK(n_0_32), .D(registers[17]), .Q(registers_2__ap[17]), .QN(), .SE(dftIn), + .SI(registers_30__ap[18]) + ); + SDFF_X1_LVT \registers_reg[31][17] ( + .CK(n_0_61), .D(registers[17]), .Q(registers_31__ap[17]), .QN(), .SE(dftIn), + .SI(registers_3__ap[18]) + ); + AOI22_X1_LVT i_1_0_1043( + .A1(registers_2__ap[17]), .A2(n_1_0_1268), .B1(n_1_0_1266), .B2(registers_31__ap[17]), + .ZN(n_1_0_993) + ); + SDFF_X1_LVT \registers_reg[20][17] ( + .CK(n_0_50), .D(registers[17]), .Q(registers_20__ap[17]), .QN(), .SE(dftIn), + .SI(registers_21__ap[17]) + ); + SDFF_X1_LVT \registers_reg[12][17] ( + .CK(n_0_42), .D(registers[17]), .Q(registers_12__ap[17]), .QN(), .SE(dftIn), + .SI(registers_10__ap[18]) + ); + AOI22_X1_LVT i_1_0_1039( + .A1(registers_20__ap[17]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[17]), + .ZN(n_1_0_989) + ); + SDFF_X1_LVT \registers_reg[15][17] ( + .CK(n_0_45), .D(registers[17]), .Q(registers_15__ap[17]), .QN(), .SE(dftIn), + .SI(registers_12__ap[17]) + ); + SDFF_X1_LVT \registers_reg[11][17] ( + .CK(n_0_41), .D(registers[17]), .Q(registers_11__ap[17]), .QN(), .SE(dftIn), + .SI(registers_15__ap[17]) + ); + AOI22_X1_LVT i_1_0_1042( + .A1(registers_15__ap[17]), .A2(n_1_0_1286), .B1(n_1_0_1270), .B2(registers_11__ap[17]), + .ZN(n_1_0_992) + ); + INV_X1_LVT i_1_0_1041( + .A(n_1_0_992), .ZN(n_1_0_991) + ); + SDFF_X1_LVT \registers_reg[10][17] ( + .CK(n_0_40), .D(registers[17]), .Q(registers_10__ap[17]), .QN(), .SE(dftIn), + .SI(registers_11__ap[17]) + ); + SDFF_X1_LVT \registers_reg[24][17] ( + .CK(n_0_54), .D(registers[17]), .Q(registers_24__ap[17]), .QN(), .SE(dftIn), + .SI(registers_2__ap[17]) + ); + AOI221_X1_LVT i_1_0_1038( + .A(n_1_0_991), .B1(n_1_0_1287), .B2(registers_10__ap[17]), .C1(registers_24__ap[17]), + .C2(n_1_0_1289), .ZN(n_1_0_988) + ); + SDFF_X1_LVT \registers_reg[22][17] ( + .CK(n_0_52), .D(registers[17]), .Q(registers_22__ap[17]), .QN(), .SE(dftIn), + .SI(registers_20__ap[17]) + ); + SDFF_X1_LVT \registers_reg[26][17] ( + .CK(n_0_56), .D(registers[17]), .Q(registers_26__ap[17]), .QN(), .SE(dftIn), + .SI(registers_24__ap[17]) + ); + SDFF_X1_LVT \registers_reg[13][17] ( + .CK(n_0_43), .D(registers[17]), .Q(registers_13__ap[17]), .QN(), .SE(dftIn), + .SI(registers_10__ap[17]) + ); + AOI222_X1_LVT i_1_0_1037( + .A1(registers_22__ap[17]), .A2(n_1_0_1294), .B1(n_1_0_1285), .B2(registers_26__ap[17]), + .C1(n_1_0_1277), .C2(registers_13__ap[17]), .ZN(n_1_0_987) + ); + NAND4_X1_LVT i_1_0_1036( + .A1(n_1_0_993), .A2(n_1_0_989), .A3(n_1_0_988), .A4(n_1_0_987), .ZN(n_1_0_986) + ); + SDFF_X1_LVT \registers_reg[1][17] ( + .CK(n_0_0), .D(registers[17]), .Q(registers_1__ap[17]), .QN(), .SE(dftIn), + .SI(registers_22__ap[17]) + ); + SDFF_X1_LVT \registers_reg[28][17] ( + .CK(n_0_58), .D(registers[17]), .Q(registers_28__ap[17]), .QN(), .SE(dftIn), + .SI(registers_26__ap[17]) + ); + AOI221_X1_LVT i_1_0_1035( + .A(n_1_0_986), .B1(n_1_0_1274), .B2(registers_1__ap[17]), .C1(registers_28__ap[17]), + .C2(n_1_0_1283), .ZN(n_1_0_985) + ); + SDFF_X1_LVT \registers_reg[18][17] ( + .CK(n_0_48), .D(registers[17]), .Q(registers_18__ap[17]), .QN(), .SE(dftIn), + .SI(registers_1__ap[17]) + ); + SDFF_X1_LVT \registers_reg[30][17] ( + .CK(n_0_60), .D(registers[17]), .Q(registers_30__ap[17]), .QN(), .SE(dftIn), + .SI(registers_28__ap[17]) + ); + AOI22_X1_LVT i_1_0_1034( + .A1(registers_18__ap[17]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[17]), + .ZN(n_1_0_984) + ); + SDFF_X1_LVT \registers_reg[4][17] ( + .CK(n_0_34), .D(registers[17]), .Q(registers_4__ap[17]), .QN(), .SE(dftIn), + .SI(registers_31__ap[17]) + ); + SDFF_X1_LVT \registers_reg[5][17] ( + .CK(n_0_35), .D(registers[17]), .Q(registers_5__ap[17]), .QN(), .SE(dftIn), + .SI(registers_4__ap[17]) + ); + AOI22_X1_LVT i_1_0_1033( + .A1(registers_4__ap[17]), .A2(n_1_0_1278), .B1(n_1_0_1273), .B2(registers_5__ap[17]), + .ZN(n_1_0_983) + ); + SDFF_X1_LVT \registers_reg[6][17] ( + .CK(n_0_36), .D(registers[17]), .Q(registers_6__ap[17]), .QN(), .SE(dftIn), + .SI(registers_5__ap[17]) + ); + SDFF_X1_LVT \registers_reg[25][17] ( + .CK(n_0_55), .D(registers[17]), .Q(registers_25__ap[17]), .QN(), .SE(dftIn), + .SI(registers_30__ap[17]) + ); + AOI22_X1_LVT i_1_0_1032( + .A1(registers_6__ap[17]), .A2(n_1_0_1300), .B1(n_1_0_1269), .B2(registers_25__ap[17]), + .ZN(n_1_0_982) + ); + NAND3_X1_LVT i_1_0_1031( + .A1(n_1_0_984), .A2(n_1_0_983), .A3(n_1_0_982), .ZN(n_1_0_981) + ); + SDFF_X1_LVT \registers_reg[19][17] ( + .CK(n_0_49), .D(registers[17]), .Q(registers_19__ap[17]), .QN(), .SE(dftIn), + .SI(registers_18__ap[17]) + ); + SDFF_X1_LVT \registers_reg[16][17] ( + .CK(n_0_46), .D(registers[17]), .Q(registers_16__ap[17]), .QN(), .SE(dftIn), + .SI(registers_13__ap[17]) + ); + AOI221_X1_LVT i_1_0_1030( + .A(n_1_0_981), .B1(n_1_0_1295), .B2(registers_19__ap[17]), .C1(registers_16__ap[17]), + .C2(n_1_0_1267), .ZN(n_1_0_980) + ); + SDFF_X1_LVT \registers_reg[7][17] ( + .CK(n_0_37), .D(registers[17]), .Q(registers_7__ap[17]), .QN(), .SE(dftIn), + .SI(registers_6__ap[17]) + ); + SDFF_X1_LVT \registers_reg[14][17] ( + .CK(n_0_44), .D(registers[17]), .Q(registers_14__ap[17]), .QN(), .SE(dftIn), + .SI(registers_16__ap[17]) + ); + AOI22_X1_LVT i_1_0_1029( + .A1(registers_7__ap[17]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[17]), + .ZN(n_1_0_979) + ); + SDFF_X1_LVT \registers_reg[9][17] ( + .CK(n_0_39), .D(registers[17]), .Q(registers_9__ap[17]), .QN(), .SE(dftIn), + .SI(registers_7__ap[17]) + ); + SDFF_X1_LVT \registers_reg[29][17] ( + .CK(n_0_59), .D(registers[17]), .Q(registers_29__ap[17]), .QN(), .SE(dftIn), + .SI(registers_25__ap[17]) + ); + AOI22_X1_LVT i_1_0_1028( + .A1(registers_9__ap[17]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[17]), + .ZN(n_1_0_978) + ); + SDFF_X1_LVT \registers_reg[8][17] ( + .CK(n_0_38), .D(registers[17]), .Q(registers_8__ap[17]), .QN(), .SE(dftIn), + .SI(registers_9__ap[17]) + ); + SDFF_X1_LVT \registers_reg[23][17] ( + .CK(n_0_53), .D(registers[17]), .Q(registers_23__ap[17]), .QN(), .SE(dftIn), + .SI(registers_19__ap[17]) + ); + AOI22_X1_LVT i_1_0_1027( + .A1(registers_8__ap[17]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[17]), + .ZN(n_1_0_977) + ); + NAND3_X1_LVT i_1_0_1026( + .A1(n_1_0_979), .A2(n_1_0_978), .A3(n_1_0_977), .ZN(n_1_0_976) + ); + SDFF_X1_LVT \registers_reg[27][17] ( + .CK(n_0_57), .D(registers[17]), .Q(registers_27__ap[17]), .QN(), .SE(dftIn), + .SI(registers_29__ap[17]) + ); + SDFF_X1_LVT \registers_reg[3][17] ( + .CK(n_0_33), .D(registers[17]), .Q(registers_3__ap[17]), .QN(), .SE(dftIn), + .SI(registers_8__ap[17]) + ); + AOI221_X1_LVT i_1_0_1025( + .A(n_1_0_976), .B1(n_1_0_1279), .B2(registers_27__ap[17]), .C1(registers_3__ap[17]), + .C2(n_1_0_1257), .ZN(n_1_0_975) + ); + NAND4_X1_LVT i_1_0_1024( + .A1(n_1_0_990), .A2(n_1_0_985), .A3(n_1_0_980), .A4(n_1_0_975), .ZN(RRs1[17]) + ); + AND2_X1_LVT i_0_0_16( + .A1(n_0_0_16), .A2(WRd[16]), .ZN(registers[16]) + ); + SDFF_X1_LVT \registers_reg[29][16] ( + .CK(n_0_59), .D(registers[16]), .Q(registers_29__ap[16]), .QN(), .SE(dftIn), + .SI(registers_27__ap[17]) + ); + SDFF_X1_LVT \registers_reg[2][16] ( + .CK(n_0_32), .D(registers[16]), .Q(registers_2__ap[16]), .QN(), .SE(dftIn), + .SI(registers_29__ap[16]) + ); + AOI22_X1_LVT i_1_0_1022( + .A1(registers_29__ap[16]), .A2(n_1_0_1276), .B1(n_1_0_1268), .B2(registers_2__ap[16]), + .ZN(n_1_0_973) + ); + SDFF_X1_LVT \registers_reg[11][16] ( + .CK(n_0_41), .D(registers[16]), .Q(registers_11__ap[16]), .QN(), .SE(dftIn), + .SI(registers_14__ap[17]) + ); + SDFF_X1_LVT \registers_reg[25][16] ( + .CK(n_0_55), .D(registers[16]), .Q(registers_25__ap[16]), .QN(), .SE(dftIn), + .SI(registers_2__ap[16]) + ); + AOI22_X1_LVT i_1_0_1023( + .A1(registers_11__ap[16]), .A2(n_1_0_1270), .B1(n_1_0_1269), .B2(registers_25__ap[16]), + .ZN(n_1_0_974) + ); + SDFF_X1_LVT \registers_reg[9][16] ( + .CK(n_0_39), .D(registers[16]), .Q(registers_9__ap[16]), .QN(), .SE(dftIn), + .SI(registers_3__ap[17]) + ); + SDFF_X1_LVT \registers_reg[7][16] ( + .CK(n_0_37), .D(registers[16]), .Q(registers_7__ap[16]), .QN(), .SE(dftIn), + .SI(registers_9__ap[16]) + ); + AOI22_X1_LVT i_1_0_1021( + .A1(registers_9__ap[16]), .A2(n_1_0_1291), .B1(n_1_0_1263), .B2(registers_7__ap[16]), + .ZN(n_1_0_972) + ); + SDFF_X1_LVT \registers_reg[10][16] ( + .CK(n_0_40), .D(registers[16]), .Q(registers_10__ap[16]), .QN(), .SE(dftIn), + .SI(registers_11__ap[16]) + ); + SDFF_X1_LVT \registers_reg[16][16] ( + .CK(n_0_46), .D(registers[16]), .Q(registers_16__ap[16]), .QN(), .SE(dftIn), + .SI(registers_10__ap[16]) + ); + AOI22_X1_LVT i_1_0_1020( + .A1(registers_10__ap[16]), .A2(n_1_0_1287), .B1(n_1_0_1267), .B2(registers_16__ap[16]), + .ZN(n_1_0_971) + ); + NAND3_X1_LVT i_1_0_1019( + .A1(n_1_0_974), .A2(n_1_0_972), .A3(n_1_0_971), .ZN(n_1_0_970) + ); + SDFF_X1_LVT \registers_reg[31][16] ( + .CK(n_0_61), .D(registers[16]), .Q(registers_31__ap[16]), .QN(), .SE(dftIn), + .SI(registers_7__ap[16]) + ); + SDFF_X1_LVT \registers_reg[6][16] ( + .CK(n_0_36), .D(registers[16]), .Q(registers_6__ap[16]), .QN(), .SE(dftIn), + .SI(registers_31__ap[16]) + ); + AOI221_X1_LVT i_1_0_1018( + .A(n_1_0_970), .B1(n_1_0_1266), .B2(registers_31__ap[16]), .C1(registers_6__ap[16]), + .C2(n_1_0_1300), .ZN(n_1_0_969) + ); + SDFF_X1_LVT \registers_reg[18][16] ( + .CK(n_0_48), .D(registers[16]), .Q(registers_18__ap[16]), .QN(), .SE(dftIn), + .SI(registers_23__ap[17]) + ); + SDFF_X1_LVT \registers_reg[22][16] ( + .CK(n_0_52), .D(registers[16]), .Q(registers_22__ap[16]), .QN(), .SE(dftIn), + .SI(registers_18__ap[16]) + ); + SDFF_X1_LVT \registers_reg[1][16] ( + .CK(n_0_0), .D(registers[16]), .Q(registers_1__ap[16]), .QN(), .SE(dftIn), + .SI(registers_22__ap[16]) + ); + AOI222_X1_LVT i_1_0_1017( + .A1(registers_18__ap[16]), .A2(n_1_0_1297), .B1(n_1_0_1294), .B2(registers_22__ap[16]), + .C1(registers_1__ap[16]), .C2(n_1_0_1274), .ZN(n_1_0_968) + ); + NAND3_X1_LVT i_1_0_1016( + .A1(n_1_0_973), .A2(n_1_0_969), .A3(n_1_0_968), .ZN(n_1_0_967) + ); + SDFF_X1_LVT \registers_reg[5][16] ( + .CK(n_0_35), .D(registers[16]), .Q(registers_5__ap[16]), .QN(), .SE(dftIn), + .SI(registers_6__ap[16]) + ); + SDFF_X1_LVT \registers_reg[28][16] ( + .CK(n_0_58), .D(registers[16]), .Q(registers_28__ap[16]), .QN(), .SE(dftIn), + .SI(registers_25__ap[16]) + ); + AOI221_X1_LVT i_1_0_1015( + .A(n_1_0_967), .B1(n_1_0_1273), .B2(registers_5__ap[16]), .C1(registers_28__ap[16]), + .C2(n_1_0_1283), .ZN(n_1_0_966) + ); + SDFF_X1_LVT \registers_reg[4][16] ( + .CK(n_0_34), .D(registers[16]), .Q(registers_4__ap[16]), .QN(), .SE(dftIn), + .SI(registers_5__ap[16]) + ); + SDFF_X1_LVT \registers_reg[12][16] ( + .CK(n_0_42), .D(registers[16]), .Q(registers_12__ap[16]), .QN(), .SE(dftIn), + .SI(registers_16__ap[16]) + ); + AOI22_X1_LVT i_1_0_1014( + .A1(registers_4__ap[16]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[16]), + .ZN(n_1_0_965) + ); + SDFF_X1_LVT \registers_reg[19][16] ( + .CK(n_0_49), .D(registers[16]), .Q(registers_19__ap[16]), .QN(), .SE(dftIn), + .SI(registers_1__ap[16]) + ); + SDFF_X1_LVT \registers_reg[21][16] ( + .CK(n_0_51), .D(registers[16]), .Q(registers_21__ap[16]), .QN(), .SE(dftIn), + .SI(registers_19__ap[16]) + ); + AOI22_X1_LVT i_1_0_1013( + .A1(registers_19__ap[16]), .A2(n_1_0_1295), .B1(n_1_0_1259), .B2(registers_21__ap[16]), + .ZN(n_1_0_964) + ); + SDFF_X1_LVT \registers_reg[24][16] ( + .CK(n_0_54), .D(registers[16]), .Q(registers_24__ap[16]), .QN(), .SE(dftIn), + .SI(registers_28__ap[16]) + ); + SDFF_X1_LVT \registers_reg[20][16] ( + .CK(n_0_50), .D(registers[16]), .Q(registers_20__ap[16]), .QN(), .SE(dftIn), + .SI(registers_21__ap[16]) + ); + AOI22_X1_LVT i_1_0_1012( + .A1(registers_24__ap[16]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[16]), + .ZN(n_1_0_963) + ); + NAND3_X1_LVT i_1_0_1011( + .A1(n_1_0_965), .A2(n_1_0_964), .A3(n_1_0_963), .ZN(n_1_0_962) + ); + SDFF_X1_LVT \registers_reg[26][16] ( + .CK(n_0_56), .D(registers[16]), .Q(registers_26__ap[16]), .QN(), .SE(dftIn), + .SI(registers_24__ap[16]) + ); + SDFF_X1_LVT \registers_reg[30][16] ( + .CK(n_0_60), .D(registers[16]), .Q(registers_30__ap[16]), .QN(), .SE(dftIn), + .SI(registers_26__ap[16]) + ); + AOI221_X1_LVT i_1_0_1010( + .A(n_1_0_962), .B1(n_1_0_1285), .B2(registers_26__ap[16]), .C1(registers_30__ap[16]), + .C2(n_1_0_1272), .ZN(n_1_0_961) + ); + SDFF_X1_LVT \registers_reg[8][16] ( + .CK(n_0_38), .D(registers[16]), .Q(registers_8__ap[16]), .QN(), .SE(dftIn), + .SI(registers_4__ap[16]) + ); + SDFF_X1_LVT \registers_reg[23][16] ( + .CK(n_0_53), .D(registers[16]), .Q(registers_23__ap[16]), .QN(), .SE(dftIn), + .SI(registers_20__ap[16]) + ); + AOI22_X1_LVT i_1_0_1009( + .A1(registers_8__ap[16]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[16]), + .ZN(n_1_0_960) + ); + SDFF_X1_LVT \registers_reg[13][16] ( + .CK(n_0_43), .D(registers[16]), .Q(registers_13__ap[16]), .QN(), .SE(dftIn), + .SI(registers_12__ap[16]) + ); + SDFF_X1_LVT \registers_reg[17][16] ( + .CK(n_0_47), .D(registers[16]), .Q(registers_17__ap[16]), .QN(), .SE(dftIn), + .SI(registers_23__ap[16]) + ); + AOI22_X1_LVT i_1_0_1008( + .A1(registers_13__ap[16]), .A2(n_1_0_1277), .B1(n_1_0_1271), .B2(registers_17__ap[16]), + .ZN(n_1_0_959) + ); + SDFF_X1_LVT \registers_reg[15][16] ( + .CK(n_0_45), .D(registers[16]), .Q(registers_15__ap[16]), .QN(), .SE(dftIn), + .SI(registers_13__ap[16]) + ); + SDFF_X1_LVT \registers_reg[14][16] ( + .CK(n_0_44), .D(registers[16]), .Q(registers_14__ap[16]), .QN(), .SE(dftIn), + .SI(registers_15__ap[16]) + ); + AOI22_X1_LVT i_1_0_1007( + .A1(registers_15__ap[16]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[16]), + .ZN(n_1_0_958) + ); + NAND3_X1_LVT i_1_0_1006( + .A1(n_1_0_960), .A2(n_1_0_959), .A3(n_1_0_958), .ZN(n_1_0_957) + ); + SDFF_X1_LVT \registers_reg[27][16] ( + .CK(n_0_57), .D(registers[16]), .Q(registers_27__ap[16]), .QN(), .SE(dftIn), + .SI(registers_30__ap[16]) + ); + SDFF_X1_LVT \registers_reg[3][16] ( + .CK(n_0_33), .D(registers[16]), .Q(registers_3__ap[16]), .QN(), .SE(dftIn), + .SI(registers_8__ap[16]) + ); + AOI221_X1_LVT i_1_0_1005( + .A(n_1_0_957), .B1(n_1_0_1279), .B2(registers_27__ap[16]), .C1(registers_3__ap[16]), + .C2(n_1_0_1257), .ZN(n_1_0_956) + ); + NAND3_X1_LVT i_1_0_1004( + .A1(n_1_0_966), .A2(n_1_0_961), .A3(n_1_0_956), .ZN(RRs1[16]) + ); + AND2_X1_LVT i_0_0_15( + .A1(n_0_0_16), .A2(WRd[15]), .ZN(registers[15]) + ); + SDFF_X1_LVT \registers_reg[17][15] ( + .CK(n_0_47), .D(registers[15]), .Q(registers_17__ap[15]), .QN(), .SE(dftIn), + .SI(registers_17__ap[16]) + ); + SDFF_X1_LVT \registers_reg[21][15] ( + .CK(n_0_51), .D(registers[15]), .Q(registers_21__ap[15]), .QN(), .SE(dftIn), + .SI(registers_17__ap[15]) + ); + AOI22_X1_LVT i_1_0_1000( + .A1(registers_17__ap[15]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[15]), + .ZN(n_1_0_952) + ); + SDFF_X1_LVT \registers_reg[10][15] ( + .CK(n_0_40), .D(registers[15]), .Q(registers_10__ap[15]), .QN(), .SE(dftIn), + .SI(registers_14__ap[16]) + ); + SDFF_X1_LVT \registers_reg[2][15] ( + .CK(n_0_32), .D(registers[15]), .Q(registers_2__ap[15]), .QN(), .SE(dftIn), + .SI(registers_27__ap[16]) + ); + AOI22_X1_LVT i_1_0_1003( + .A1(registers_10__ap[15]), .A2(n_1_0_1287), .B1(n_1_0_1268), .B2(registers_2__ap[15]), + .ZN(n_1_0_955) + ); + SDFF_X1_LVT \registers_reg[20][15] ( + .CK(n_0_50), .D(registers[15]), .Q(registers_20__ap[15]), .QN(), .SE(dftIn), + .SI(registers_21__ap[15]) + ); + SDFF_X1_LVT \registers_reg[12][15] ( + .CK(n_0_42), .D(registers[15]), .Q(registers_12__ap[15]), .QN(), .SE(dftIn), + .SI(registers_10__ap[15]) + ); + AOI22_X1_LVT i_1_0_999( + .A1(registers_20__ap[15]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[15]), + .ZN(n_1_0_951) + ); + SDFF_X1_LVT \registers_reg[15][15] ( + .CK(n_0_45), .D(registers[15]), .Q(registers_15__ap[15]), .QN(), .SE(dftIn), + .SI(registers_12__ap[15]) + ); + SDFF_X1_LVT \registers_reg[8][15] ( + .CK(n_0_38), .D(registers[15]), .Q(registers_8__ap[15]), .QN(), .SE(dftIn), + .SI(registers_3__ap[16]) + ); + AOI22_X1_LVT i_1_0_1002( + .A1(registers_15__ap[15]), .A2(n_1_0_1286), .B1(n_1_0_1282), .B2(registers_8__ap[15]), + .ZN(n_1_0_954) + ); + INV_X1_LVT i_1_0_1001( + .A(n_1_0_954), .ZN(n_1_0_953) + ); + SDFF_X1_LVT \registers_reg[11][15] ( + .CK(n_0_41), .D(registers[15]), .Q(registers_11__ap[15]), .QN(), .SE(dftIn), + .SI(registers_15__ap[15]) + ); + SDFF_X1_LVT \registers_reg[24][15] ( + .CK(n_0_54), .D(registers[15]), .Q(registers_24__ap[15]), .QN(), .SE(dftIn), + .SI(registers_2__ap[15]) + ); + AOI221_X1_LVT i_1_0_998( + .A(n_1_0_953), .B1(n_1_0_1270), .B2(registers_11__ap[15]), .C1(registers_24__ap[15]), + .C2(n_1_0_1289), .ZN(n_1_0_950) + ); + SDFF_X1_LVT \registers_reg[13][15] ( + .CK(n_0_43), .D(registers[15]), .Q(registers_13__ap[15]), .QN(), .SE(dftIn), + .SI(registers_11__ap[15]) + ); + SDFF_X1_LVT \registers_reg[30][15] ( + .CK(n_0_60), .D(registers[15]), .Q(registers_30__ap[15]), .QN(), .SE(dftIn), + .SI(registers_24__ap[15]) + ); + SDFF_X1_LVT \registers_reg[22][15] ( + .CK(n_0_52), .D(registers[15]), .Q(registers_22__ap[15]), .QN(), .SE(dftIn), + .SI(registers_20__ap[15]) + ); + AOI222_X1_LVT i_1_0_997( + .A1(registers_13__ap[15]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[15]), + .C1(registers_22__ap[15]), .C2(n_1_0_1294), .ZN(n_1_0_949) + ); + NAND4_X1_LVT i_1_0_996( + .A1(n_1_0_955), .A2(n_1_0_951), .A3(n_1_0_950), .A4(n_1_0_949), .ZN(n_1_0_948) + ); + SDFF_X1_LVT \registers_reg[1][15] ( + .CK(n_0_0), .D(registers[15]), .Q(registers_1__ap[15]), .QN(), .SE(dftIn), + .SI(registers_22__ap[15]) + ); + SDFF_X1_LVT \registers_reg[28][15] ( + .CK(n_0_58), .D(registers[15]), .Q(registers_28__ap[15]), .QN(), .SE(dftIn), + .SI(registers_30__ap[15]) + ); + AOI221_X1_LVT i_1_0_995( + .A(n_1_0_948), .B1(n_1_0_1274), .B2(registers_1__ap[15]), .C1(registers_28__ap[15]), + .C2(n_1_0_1283), .ZN(n_1_0_947) + ); + SDFF_X1_LVT \registers_reg[18][15] ( + .CK(n_0_48), .D(registers[15]), .Q(registers_18__ap[15]), .QN(), .SE(dftIn), + .SI(registers_1__ap[15]) + ); + SDFF_X1_LVT \registers_reg[26][15] ( + .CK(n_0_56), .D(registers[15]), .Q(registers_26__ap[15]), .QN(), .SE(dftIn), + .SI(registers_28__ap[15]) + ); + AOI22_X1_LVT i_1_0_994( + .A1(registers_18__ap[15]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[15]), + .ZN(n_1_0_946) + ); + SDFF_X1_LVT \registers_reg[4][15] ( + .CK(n_0_34), .D(registers[15]), .Q(registers_4__ap[15]), .QN(), .SE(dftIn), + .SI(registers_8__ap[15]) + ); + SDFF_X1_LVT \registers_reg[5][15] ( + .CK(n_0_35), .D(registers[15]), .Q(registers_5__ap[15]), .QN(), .SE(dftIn), + .SI(registers_4__ap[15]) + ); + AOI22_X1_LVT i_1_0_993( + .A1(registers_4__ap[15]), .A2(n_1_0_1278), .B1(n_1_0_1273), .B2(registers_5__ap[15]), + .ZN(n_1_0_945) + ); + SDFF_X1_LVT \registers_reg[6][15] ( + .CK(n_0_36), .D(registers[15]), .Q(registers_6__ap[15]), .QN(), .SE(dftIn), + .SI(registers_5__ap[15]) + ); + SDFF_X1_LVT \registers_reg[16][15] ( + .CK(n_0_46), .D(registers[15]), .Q(registers_16__ap[15]), .QN(), .SE(dftIn), + .SI(registers_13__ap[15]) + ); + AOI22_X1_LVT i_1_0_992( + .A1(registers_6__ap[15]), .A2(n_1_0_1300), .B1(n_1_0_1267), .B2(registers_16__ap[15]), + .ZN(n_1_0_944) + ); + NAND3_X1_LVT i_1_0_991( + .A1(n_1_0_946), .A2(n_1_0_945), .A3(n_1_0_944), .ZN(n_1_0_943) + ); + SDFF_X1_LVT \registers_reg[19][15] ( + .CK(n_0_49), .D(registers[15]), .Q(registers_19__ap[15]), .QN(), .SE(dftIn), + .SI(registers_18__ap[15]) + ); + SDFF_X1_LVT \registers_reg[25][15] ( + .CK(n_0_55), .D(registers[15]), .Q(registers_25__ap[15]), .QN(), .SE(dftIn), + .SI(registers_26__ap[15]) + ); + AOI221_X1_LVT i_1_0_990( + .A(n_1_0_943), .B1(n_1_0_1295), .B2(registers_19__ap[15]), .C1(registers_25__ap[15]), + .C2(n_1_0_1269), .ZN(n_1_0_942) + ); + SDFF_X1_LVT \registers_reg[7][15] ( + .CK(n_0_37), .D(registers[15]), .Q(registers_7__ap[15]), .QN(), .SE(dftIn), + .SI(registers_6__ap[15]) + ); + SDFF_X1_LVT \registers_reg[14][15] ( + .CK(n_0_44), .D(registers[15]), .Q(registers_14__ap[15]), .QN(), .SE(dftIn), + .SI(registers_16__ap[15]) + ); + AOI22_X1_LVT i_1_0_989( + .A1(registers_7__ap[15]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[15]), + .ZN(n_1_0_941) + ); + SDFF_X1_LVT \registers_reg[9][15] ( + .CK(n_0_39), .D(registers[15]), .Q(registers_9__ap[15]), .QN(), .SE(dftIn), + .SI(registers_7__ap[15]) + ); + SDFF_X1_LVT \registers_reg[29][15] ( + .CK(n_0_59), .D(registers[15]), .Q(registers_29__ap[15]), .QN(), .SE(dftIn), + .SI(registers_25__ap[15]) + ); + AOI22_X1_LVT i_1_0_988( + .A1(registers_9__ap[15]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[15]), + .ZN(n_1_0_940) + ); + SDFF_X1_LVT \registers_reg[23][15] ( + .CK(n_0_53), .D(registers[15]), .Q(registers_23__ap[15]), .QN(), .SE(dftIn), + .SI(registers_19__ap[15]) + ); + SDFF_X1_LVT \registers_reg[3][15] ( + .CK(n_0_33), .D(registers[15]), .Q(registers_3__ap[15]), .QN(), .SE(dftIn), + .SI(registers_9__ap[15]) + ); + AOI22_X1_LVT i_1_0_987( + .A1(registers_23__ap[15]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[15]), + .ZN(n_1_0_939) + ); + NAND3_X1_LVT i_1_0_986( + .A1(n_1_0_941), .A2(n_1_0_940), .A3(n_1_0_939), .ZN(n_1_0_938) + ); + SDFF_X1_LVT \registers_reg[27][15] ( + .CK(n_0_57), .D(registers[15]), .Q(registers_27__ap[15]), .QN(), .SE(dftIn), + .SI(registers_29__ap[15]) + ); + SDFF_X1_LVT \registers_reg[31][15] ( + .CK(n_0_61), .D(registers[15]), .Q(registers_31__ap[15]), .QN(), .SE(dftIn), + .SI(registers_3__ap[15]) + ); + AOI221_X1_LVT i_1_0_985( + .A(n_1_0_938), .B1(n_1_0_1279), .B2(registers_27__ap[15]), .C1(registers_31__ap[15]), + .C2(n_1_0_1266), .ZN(n_1_0_937) + ); + NAND4_X1_LVT i_1_0_984( + .A1(n_1_0_952), .A2(n_1_0_947), .A3(n_1_0_942), .A4(n_1_0_937), .ZN(RRs1[15]) + ); + AND2_X1_LVT i_0_0_14( + .A1(n_0_0_16), .A2(WRd[14]), .ZN(registers[14]) + ); + SDFF_X1_LVT \registers_reg[28][14] ( + .CK(n_0_58), .D(registers[14]), .Q(registers_28__ap[14]), .QN(), .SE(dftIn), + .SI(registers_27__ap[15]) + ); + SDFF_X1_LVT \registers_reg[5][14] ( + .CK(n_0_35), .D(registers[14]), .Q(registers_5__ap[14]), .QN(), .SE(dftIn), + .SI(registers_31__ap[15]) + ); + AOI22_X1_LVT i_1_0_983( + .A1(registers_28__ap[14]), .A2(n_1_0_1283), .B1(n_1_0_1273), .B2(registers_5__ap[14]), + .ZN(n_1_0_936) + ); + SDFF_X1_LVT \registers_reg[18][14] ( + .CK(n_0_48), .D(registers[14]), .Q(registers_18__ap[14]), .QN(), .SE(dftIn), + .SI(registers_23__ap[15]) + ); + SDFF_X1_LVT \registers_reg[10][14] ( + .CK(n_0_40), .D(registers[14]), .Q(registers_10__ap[14]), .QN(), .SE(dftIn), + .SI(registers_14__ap[15]) + ); + SDFF_X1_LVT \registers_reg[8][14] ( + .CK(n_0_38), .D(registers[14]), .Q(registers_8__ap[14]), .QN(), .SE(dftIn), + .SI(registers_5__ap[14]) + ); + AOI222_X1_LVT i_1_0_982( + .A1(registers_18__ap[14]), .A2(n_1_0_1297), .B1(n_1_0_1287), .B2(registers_10__ap[14]), + .C1(n_1_0_1282), .C2(registers_8__ap[14]), .ZN(n_1_0_935) + ); + SDFF_X1_LVT \registers_reg[9][14] ( + .CK(n_0_39), .D(registers[14]), .Q(registers_9__ap[14]), .QN(), .SE(dftIn), + .SI(registers_8__ap[14]) + ); + SDFF_X1_LVT \registers_reg[29][14] ( + .CK(n_0_59), .D(registers[14]), .Q(registers_29__ap[14]), .QN(), .SE(dftIn), + .SI(registers_28__ap[14]) + ); + AOI22_X1_LVT i_1_0_981( + .A1(registers_9__ap[14]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[14]), + .ZN(n_1_0_934) + ); + SDFF_X1_LVT \registers_reg[21][14] ( + .CK(n_0_51), .D(registers[14]), .Q(registers_21__ap[14]), .QN(), .SE(dftIn), + .SI(registers_18__ap[14]) + ); + SDFF_X1_LVT \registers_reg[14][14] ( + .CK(n_0_44), .D(registers[14]), .Q(registers_14__ap[14]), .QN(), .SE(dftIn), + .SI(registers_10__ap[14]) + ); + AOI22_X1_LVT i_1_0_980( + .A1(registers_21__ap[14]), .A2(n_1_0_1259), .B1(n_1_0_1258), .B2(registers_14__ap[14]), + .ZN(n_1_0_933) + ); + SDFF_X1_LVT \registers_reg[16][14] ( + .CK(n_0_46), .D(registers[14]), .Q(registers_16__ap[14]), .QN(), .SE(dftIn), + .SI(registers_14__ap[14]) + ); + SDFF_X1_LVT \registers_reg[3][14] ( + .CK(n_0_33), .D(registers[14]), .Q(registers_3__ap[14]), .QN(), .SE(dftIn), + .SI(registers_9__ap[14]) + ); + AOI22_X1_LVT i_1_0_979( + .A1(registers_16__ap[14]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[14]), + .ZN(n_1_0_932) + ); + SDFF_X1_LVT \registers_reg[17][14] ( + .CK(n_0_47), .D(registers[14]), .Q(registers_17__ap[14]), .QN(), .SE(dftIn), + .SI(registers_21__ap[14]) + ); + SDFF_X1_LVT \registers_reg[31][14] ( + .CK(n_0_61), .D(registers[14]), .Q(registers_31__ap[14]), .QN(), .SE(dftIn), + .SI(registers_3__ap[14]) + ); + AOI22_X1_LVT i_1_0_978( + .A1(registers_17__ap[14]), .A2(n_1_0_1271), .B1(n_1_0_1266), .B2(registers_31__ap[14]), + .ZN(n_1_0_931) + ); + SDFF_X1_LVT \registers_reg[15][14] ( + .CK(n_0_45), .D(registers[14]), .Q(registers_15__ap[14]), .QN(), .SE(dftIn), + .SI(registers_16__ap[14]) + ); + SDFF_X1_LVT \registers_reg[23][14] ( + .CK(n_0_53), .D(registers[14]), .Q(registers_23__ap[14]), .QN(), .SE(dftIn), + .SI(registers_17__ap[14]) + ); + AOI22_X1_LVT i_1_0_977( + .A1(registers_15__ap[14]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[14]), + .ZN(n_1_0_930) + ); + NAND4_X1_LVT i_1_0_976( + .A1(n_1_0_933), .A2(n_1_0_932), .A3(n_1_0_931), .A4(n_1_0_930), .ZN(n_1_0_929) + ); + SDFF_X1_LVT \registers_reg[26][14] ( + .CK(n_0_56), .D(registers[14]), .Q(registers_26__ap[14]), .QN(), .SE(dftIn), + .SI(registers_29__ap[14]) + ); + SDFF_X1_LVT \registers_reg[30][14] ( + .CK(n_0_60), .D(registers[14]), .Q(registers_30__ap[14]), .QN(), .SE(dftIn), + .SI(registers_26__ap[14]) + ); + AOI22_X1_LVT i_1_0_975( + .A1(registers_26__ap[14]), .A2(n_1_0_1285), .B1(n_1_0_1272), .B2(registers_30__ap[14]), + .ZN(n_1_0_928) + ); + SDFF_X1_LVT \registers_reg[20][14] ( + .CK(n_0_50), .D(registers[14]), .Q(registers_20__ap[14]), .QN(), .SE(dftIn), + .SI(registers_23__ap[14]) + ); + SDFF_X1_LVT \registers_reg[4][14] ( + .CK(n_0_34), .D(registers[14]), .Q(registers_4__ap[14]), .QN(), .SE(dftIn), + .SI(registers_31__ap[14]) + ); + AOI22_X1_LVT i_1_0_974( + .A1(registers_20__ap[14]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[14]), + .ZN(n_1_0_927) + ); + SDFF_X1_LVT \registers_reg[1][14] ( + .CK(n_0_0), .D(registers[14]), .Q(registers_1__ap[14]), .QN(), .SE(dftIn), + .SI(registers_20__ap[14]) + ); + SDFF_X1_LVT \registers_reg[2][14] ( + .CK(n_0_32), .D(registers[14]), .Q(registers_2__ap[14]), .QN(), .SE(dftIn), + .SI(registers_30__ap[14]) + ); + AOI22_X1_LVT i_1_0_973( + .A1(registers_1__ap[14]), .A2(n_1_0_1274), .B1(n_1_0_1268), .B2(registers_2__ap[14]), + .ZN(n_1_0_926) + ); + SDFF_X1_LVT \registers_reg[24][14] ( + .CK(n_0_54), .D(registers[14]), .Q(registers_24__ap[14]), .QN(), .SE(dftIn), + .SI(registers_2__ap[14]) + ); + SDFF_X1_LVT \registers_reg[12][14] ( + .CK(n_0_42), .D(registers[14]), .Q(registers_12__ap[14]), .QN(), .SE(dftIn), + .SI(registers_15__ap[14]) + ); + AOI22_X1_LVT i_1_0_972( + .A1(registers_24__ap[14]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[14]), + .ZN(n_1_0_925) + ); + NAND4_X1_LVT i_1_0_971( + .A1(n_1_0_928), .A2(n_1_0_927), .A3(n_1_0_926), .A4(n_1_0_925), .ZN(n_1_0_924) + ); + SDFF_X1_LVT \registers_reg[19][14] ( + .CK(n_0_49), .D(registers[14]), .Q(registers_19__ap[14]), .QN(), .SE(dftIn), + .SI(registers_1__ap[14]) + ); + SDFF_X1_LVT \registers_reg[22][14] ( + .CK(n_0_52), .D(registers[14]), .Q(registers_22__ap[14]), .QN(), .SE(dftIn), + .SI(registers_19__ap[14]) + ); + AOI22_X1_LVT i_1_0_970( + .A1(registers_19__ap[14]), .A2(n_1_0_1295), .B1(n_1_0_1294), .B2(registers_22__ap[14]), + .ZN(n_1_0_923) + ); + SDFF_X1_LVT \registers_reg[13][14] ( + .CK(n_0_43), .D(registers[14]), .Q(registers_13__ap[14]), .QN(), .SE(dftIn), + .SI(registers_12__ap[14]) + ); + SDFF_X1_LVT \registers_reg[25][14] ( + .CK(n_0_55), .D(registers[14]), .Q(registers_25__ap[14]), .QN(), .SE(dftIn), + .SI(registers_24__ap[14]) + ); + AOI22_X1_LVT i_1_0_969( + .A1(registers_13__ap[14]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[14]), + .ZN(n_1_0_922) + ); + SDFF_X1_LVT \registers_reg[6][14] ( + .CK(n_0_36), .D(registers[14]), .Q(registers_6__ap[14]), .QN(), .SE(dftIn), + .SI(registers_4__ap[14]) + ); + SDFF_X1_LVT \registers_reg[7][14] ( + .CK(n_0_37), .D(registers[14]), .Q(registers_7__ap[14]), .QN(), .SE(dftIn), + .SI(registers_6__ap[14]) + ); + AOI22_X1_LVT i_1_0_968( + .A1(registers_6__ap[14]), .A2(n_1_0_1300), .B1(n_1_0_1263), .B2(registers_7__ap[14]), + .ZN(n_1_0_921) + ); + SDFF_X1_LVT \registers_reg[27][14] ( + .CK(n_0_57), .D(registers[14]), .Q(registers_27__ap[14]), .QN(), .SE(dftIn), + .SI(registers_25__ap[14]) + ); + SDFF_X1_LVT \registers_reg[11][14] ( + .CK(n_0_41), .D(registers[14]), .Q(registers_11__ap[14]), .QN(), .SE(dftIn), + .SI(registers_13__ap[14]) + ); + AOI22_X1_LVT i_1_0_967( + .A1(registers_27__ap[14]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[14]), + .ZN(n_1_0_920) + ); + NAND4_X1_LVT i_1_0_966( + .A1(n_1_0_923), .A2(n_1_0_922), .A3(n_1_0_921), .A4(n_1_0_920), .ZN(n_1_0_919) + ); + NOR3_X1_LVT i_1_0_965( + .A1(n_1_0_929), .A2(n_1_0_924), .A3(n_1_0_919), .ZN(n_1_0_918) + ); + NAND4_X1_LVT i_1_0_964( + .A1(n_1_0_936), .A2(n_1_0_935), .A3(n_1_0_934), .A4(n_1_0_918), .ZN(RRs1[14]) + ); + AND2_X1_LVT i_0_0_13( + .A1(n_0_0_16), .A2(WRd[13]), .ZN(registers[13]) + ); + SDFF_X1_LVT \registers_reg[28][13] ( + .CK(n_0_58), .D(registers[13]), .Q(registers_28__ap[13]), .QN(), .SE(dftIn), + .SI(registers_27__ap[14]) + ); + SDFF_X1_LVT \registers_reg[4][13] ( + .CK(n_0_34), .D(registers[13]), .Q(registers_4__ap[13]), .QN(), .SE(dftIn), + .SI(registers_7__ap[14]) + ); + AOI22_X1_LVT i_1_0_963( + .A1(registers_28__ap[13]), .A2(n_1_0_1283), .B1(n_1_0_1278), .B2(registers_4__ap[13]), + .ZN(n_1_0_917) + ); + SDFF_X1_LVT \registers_reg[10][13] ( + .CK(n_0_40), .D(registers[13]), .Q(registers_10__ap[13]), .QN(), .SE(dftIn), + .SI(registers_11__ap[14]) + ); + SDFF_X1_LVT \registers_reg[26][13] ( + .CK(n_0_56), .D(registers[13]), .Q(registers_26__ap[13]), .QN(), .SE(dftIn), + .SI(registers_28__ap[13]) + ); + SDFF_X1_LVT \registers_reg[8][13] ( + .CK(n_0_38), .D(registers[13]), .Q(registers_8__ap[13]), .QN(), .SE(dftIn), + .SI(registers_4__ap[13]) + ); + AOI222_X1_LVT i_1_0_962( + .A1(registers_10__ap[13]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[13]), + .C1(registers_8__ap[13]), .C2(n_1_0_1282), .ZN(n_1_0_916) + ); + SDFF_X1_LVT \registers_reg[9][13] ( + .CK(n_0_39), .D(registers[13]), .Q(registers_9__ap[13]), .QN(), .SE(dftIn), + .SI(registers_8__ap[13]) + ); + SDFF_X1_LVT \registers_reg[29][13] ( + .CK(n_0_59), .D(registers[13]), .Q(registers_29__ap[13]), .QN(), .SE(dftIn), + .SI(registers_26__ap[13]) + ); + AOI22_X1_LVT i_1_0_961( + .A1(registers_9__ap[13]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[13]), + .ZN(n_1_0_915) + ); + SDFF_X1_LVT \registers_reg[6][13] ( + .CK(n_0_36), .D(registers[13]), .Q(registers_6__ap[13]), .QN(), .SE(dftIn), + .SI(registers_9__ap[13]) + ); + SDFF_X1_LVT \registers_reg[1][13] ( + .CK(n_0_0), .D(registers[13]), .Q(registers_1__ap[13]), .QN(), .SE(dftIn), + .SI(registers_22__ap[14]) + ); + AOI22_X1_LVT i_1_0_960( + .A1(registers_6__ap[13]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[13]), + .ZN(n_1_0_914) + ); + SDFF_X1_LVT \registers_reg[5][13] ( + .CK(n_0_35), .D(registers[13]), .Q(registers_5__ap[13]), .QN(), .SE(dftIn), + .SI(registers_6__ap[13]) + ); + SDFF_X1_LVT \registers_reg[3][13] ( + .CK(n_0_33), .D(registers[13]), .Q(registers_3__ap[13]), .QN(), .SE(dftIn), + .SI(registers_5__ap[13]) + ); + AOI22_X1_LVT i_1_0_959( + .A1(registers_5__ap[13]), .A2(n_1_0_1273), .B1(n_1_0_1257), .B2(registers_3__ap[13]), + .ZN(n_1_0_913) + ); + SDFF_X1_LVT \registers_reg[16][13] ( + .CK(n_0_46), .D(registers[13]), .Q(registers_16__ap[13]), .QN(), .SE(dftIn), + .SI(registers_10__ap[13]) + ); + SDFF_X1_LVT \registers_reg[31][13] ( + .CK(n_0_61), .D(registers[13]), .Q(registers_31__ap[13]), .QN(), .SE(dftIn), + .SI(registers_3__ap[13]) + ); + AOI22_X1_LVT i_1_0_958( + .A1(registers_16__ap[13]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[13]), + .ZN(n_1_0_912) + ); + SDFF_X1_LVT \registers_reg[15][13] ( + .CK(n_0_45), .D(registers[13]), .Q(registers_15__ap[13]), .QN(), .SE(dftIn), + .SI(registers_16__ap[13]) + ); + SDFF_X1_LVT \registers_reg[23][13] ( + .CK(n_0_53), .D(registers[13]), .Q(registers_23__ap[13]), .QN(), .SE(dftIn), + .SI(registers_1__ap[13]) + ); + AOI22_X1_LVT i_1_0_957( + .A1(registers_15__ap[13]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[13]), + .ZN(n_1_0_911) + ); + NAND4_X1_LVT i_1_0_956( + .A1(n_1_0_914), .A2(n_1_0_913), .A3(n_1_0_912), .A4(n_1_0_911), .ZN(n_1_0_910) + ); + SDFF_X1_LVT \registers_reg[18][13] ( + .CK(n_0_48), .D(registers[13]), .Q(registers_18__ap[13]), .QN(), .SE(dftIn), + .SI(registers_23__ap[13]) + ); + SDFF_X1_LVT \registers_reg[30][13] ( + .CK(n_0_60), .D(registers[13]), .Q(registers_30__ap[13]), .QN(), .SE(dftIn), + .SI(registers_29__ap[13]) + ); + AOI22_X1_LVT i_1_0_955( + .A1(registers_18__ap[13]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[13]), + .ZN(n_1_0_909) + ); + SDFF_X1_LVT \registers_reg[24][13] ( + .CK(n_0_54), .D(registers[13]), .Q(registers_24__ap[13]), .QN(), .SE(dftIn), + .SI(registers_30__ap[13]) + ); + SDFF_X1_LVT \registers_reg[12][13] ( + .CK(n_0_42), .D(registers[13]), .Q(registers_12__ap[13]), .QN(), .SE(dftIn), + .SI(registers_15__ap[13]) + ); + AOI22_X1_LVT i_1_0_954( + .A1(registers_24__ap[13]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[13]), + .ZN(n_1_0_908) + ); + SDFF_X1_LVT \registers_reg[22][13] ( + .CK(n_0_52), .D(registers[13]), .Q(registers_22__ap[13]), .QN(), .SE(dftIn), + .SI(registers_18__ap[13]) + ); + SDFF_X1_LVT \registers_reg[21][13] ( + .CK(n_0_51), .D(registers[13]), .Q(registers_21__ap[13]), .QN(), .SE(dftIn), + .SI(registers_22__ap[13]) + ); + AOI22_X1_LVT i_1_0_953( + .A1(registers_22__ap[13]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[13]), + .ZN(n_1_0_907) + ); + SDFF_X1_LVT \registers_reg[20][13] ( + .CK(n_0_50), .D(registers[13]), .Q(registers_20__ap[13]), .QN(), .SE(dftIn), + .SI(registers_21__ap[13]) + ); + SDFF_X1_LVT \registers_reg[17][13] ( + .CK(n_0_47), .D(registers[13]), .Q(registers_17__ap[13]), .QN(), .SE(dftIn), + .SI(registers_20__ap[13]) + ); + AOI22_X1_LVT i_1_0_952( + .A1(registers_20__ap[13]), .A2(n_1_0_1281), .B1(n_1_0_1271), .B2(registers_17__ap[13]), + .ZN(n_1_0_906) + ); + NAND4_X1_LVT i_1_0_951( + .A1(n_1_0_909), .A2(n_1_0_908), .A3(n_1_0_907), .A4(n_1_0_906), .ZN(n_1_0_905) + ); + SDFF_X1_LVT \registers_reg[13][13] ( + .CK(n_0_43), .D(registers[13]), .Q(registers_13__ap[13]), .QN(), .SE(dftIn), + .SI(registers_12__ap[13]) + ); + SDFF_X1_LVT \registers_reg[25][13] ( + .CK(n_0_55), .D(registers[13]), .Q(registers_25__ap[13]), .QN(), .SE(dftIn), + .SI(registers_24__ap[13]) + ); + AOI22_X1_LVT i_1_0_950( + .A1(registers_13__ap[13]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[13]), + .ZN(n_1_0_904) + ); + SDFF_X1_LVT \registers_reg[19][13] ( + .CK(n_0_49), .D(registers[13]), .Q(registers_19__ap[13]), .QN(), .SE(dftIn), + .SI(registers_17__ap[13]) + ); + SDFF_X1_LVT \registers_reg[2][13] ( + .CK(n_0_32), .D(registers[13]), .Q(registers_2__ap[13]), .QN(), .SE(dftIn), + .SI(registers_25__ap[13]) + ); + AOI22_X1_LVT i_1_0_949( + .A1(registers_19__ap[13]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[13]), + .ZN(n_1_0_903) + ); + SDFF_X1_LVT \registers_reg[7][13] ( + .CK(n_0_37), .D(registers[13]), .Q(registers_7__ap[13]), .QN(), .SE(dftIn), + .SI(registers_31__ap[13]) + ); + SDFF_X1_LVT \registers_reg[14][13] ( + .CK(n_0_44), .D(registers[13]), .Q(registers_14__ap[13]), .QN(), .SE(dftIn), + .SI(registers_13__ap[13]) + ); + AOI22_X1_LVT i_1_0_948( + .A1(registers_7__ap[13]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[13]), + .ZN(n_1_0_902) + ); + SDFF_X1_LVT \registers_reg[27][13] ( + .CK(n_0_57), .D(registers[13]), .Q(registers_27__ap[13]), .QN(), .SE(dftIn), + .SI(registers_2__ap[13]) + ); + SDFF_X1_LVT \registers_reg[11][13] ( + .CK(n_0_41), .D(registers[13]), .Q(registers_11__ap[13]), .QN(), .SE(dftIn), + .SI(registers_14__ap[13]) + ); + AOI22_X1_LVT i_1_0_947( + .A1(registers_27__ap[13]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[13]), + .ZN(n_1_0_901) + ); + NAND4_X1_LVT i_1_0_946( + .A1(n_1_0_904), .A2(n_1_0_903), .A3(n_1_0_902), .A4(n_1_0_901), .ZN(n_1_0_900) + ); + NOR3_X1_LVT i_1_0_945( + .A1(n_1_0_910), .A2(n_1_0_905), .A3(n_1_0_900), .ZN(n_1_0_899) + ); + NAND4_X1_LVT i_1_0_944( + .A1(n_1_0_917), .A2(n_1_0_916), .A3(n_1_0_915), .A4(n_1_0_899), .ZN(RRs1[13]) + ); + AND2_X1_LVT i_0_0_12( + .A1(n_0_0_16), .A2(WRd[12]), .ZN(registers[12]) + ); + SDFF_X1_LVT \registers_reg[28][12] ( + .CK(n_0_58), .D(registers[12]), .Q(registers_28__ap[12]), .QN(), .SE(dftIn), + .SI(registers_27__ap[13]) + ); + SDFF_X1_LVT \registers_reg[17][12] ( + .CK(n_0_47), .D(registers[12]), .Q(registers_17__ap[12]), .QN(), .SE(dftIn), + .SI(registers_19__ap[13]) + ); + AOI22_X1_LVT i_1_0_943( + .A1(registers_28__ap[12]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[12]), + .ZN(n_1_0_898) + ); + SDFF_X1_LVT \registers_reg[10][12] ( + .CK(n_0_40), .D(registers[12]), .Q(registers_10__ap[12]), .QN(), .SE(dftIn), + .SI(registers_11__ap[13]) + ); + SDFF_X1_LVT \registers_reg[26][12] ( + .CK(n_0_56), .D(registers[12]), .Q(registers_26__ap[12]), .QN(), .SE(dftIn), + .SI(registers_28__ap[12]) + ); + SDFF_X1_LVT \registers_reg[8][12] ( + .CK(n_0_38), .D(registers[12]), .Q(registers_8__ap[12]), .QN(), .SE(dftIn), + .SI(registers_7__ap[13]) + ); + AOI222_X1_LVT i_1_0_942( + .A1(registers_10__ap[12]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[12]), + .C1(registers_8__ap[12]), .C2(n_1_0_1282), .ZN(n_1_0_897) + ); + SDFF_X1_LVT \registers_reg[9][12] ( + .CK(n_0_39), .D(registers[12]), .Q(registers_9__ap[12]), .QN(), .SE(dftIn), + .SI(registers_8__ap[12]) + ); + SDFF_X1_LVT \registers_reg[29][12] ( + .CK(n_0_59), .D(registers[12]), .Q(registers_29__ap[12]), .QN(), .SE(dftIn), + .SI(registers_26__ap[12]) + ); + AOI22_X1_LVT i_1_0_941( + .A1(registers_9__ap[12]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[12]), + .ZN(n_1_0_896) + ); + SDFF_X1_LVT \registers_reg[6][12] ( + .CK(n_0_36), .D(registers[12]), .Q(registers_6__ap[12]), .QN(), .SE(dftIn), + .SI(registers_9__ap[12]) + ); + SDFF_X1_LVT \registers_reg[1][12] ( + .CK(n_0_0), .D(registers[12]), .Q(registers_1__ap[12]), .QN(), .SE(dftIn), + .SI(registers_17__ap[12]) + ); + AOI22_X1_LVT i_1_0_940( + .A1(registers_6__ap[12]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[12]), + .ZN(n_1_0_895) + ); + SDFF_X1_LVT \registers_reg[16][12] ( + .CK(n_0_46), .D(registers[12]), .Q(registers_16__ap[12]), .QN(), .SE(dftIn), + .SI(registers_10__ap[12]) + ); + SDFF_X1_LVT \registers_reg[3][12] ( + .CK(n_0_33), .D(registers[12]), .Q(registers_3__ap[12]), .QN(), .SE(dftIn), + .SI(registers_6__ap[12]) + ); + AOI22_X1_LVT i_1_0_939( + .A1(registers_16__ap[12]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[12]), + .ZN(n_1_0_894) + ); + SDFF_X1_LVT \registers_reg[5][12] ( + .CK(n_0_35), .D(registers[12]), .Q(registers_5__ap[12]), .QN(), .SE(dftIn), + .SI(registers_3__ap[12]) + ); + SDFF_X1_LVT \registers_reg[31][12] ( + .CK(n_0_61), .D(registers[12]), .Q(registers_31__ap[12]), .QN(), .SE(dftIn), + .SI(registers_5__ap[12]) + ); + AOI22_X1_LVT i_1_0_938( + .A1(registers_5__ap[12]), .A2(n_1_0_1273), .B1(n_1_0_1266), .B2(registers_31__ap[12]), + .ZN(n_1_0_893) + ); + SDFF_X1_LVT \registers_reg[15][12] ( + .CK(n_0_45), .D(registers[12]), .Q(registers_15__ap[12]), .QN(), .SE(dftIn), + .SI(registers_16__ap[12]) + ); + SDFF_X1_LVT \registers_reg[23][12] ( + .CK(n_0_53), .D(registers[12]), .Q(registers_23__ap[12]), .QN(), .SE(dftIn), + .SI(registers_1__ap[12]) + ); + AOI22_X1_LVT i_1_0_937( + .A1(registers_15__ap[12]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[12]), + .ZN(n_1_0_892) + ); + NAND4_X1_LVT i_1_0_936( + .A1(n_1_0_895), .A2(n_1_0_894), .A3(n_1_0_893), .A4(n_1_0_892), .ZN(n_1_0_891) + ); + SDFF_X1_LVT \registers_reg[18][12] ( + .CK(n_0_48), .D(registers[12]), .Q(registers_18__ap[12]), .QN(), .SE(dftIn), + .SI(registers_23__ap[12]) + ); + SDFF_X1_LVT \registers_reg[30][12] ( + .CK(n_0_60), .D(registers[12]), .Q(registers_30__ap[12]), .QN(), .SE(dftIn), + .SI(registers_29__ap[12]) + ); + AOI22_X1_LVT i_1_0_935( + .A1(registers_18__ap[12]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[12]), + .ZN(n_1_0_890) + ); + SDFF_X1_LVT \registers_reg[20][12] ( + .CK(n_0_50), .D(registers[12]), .Q(registers_20__ap[12]), .QN(), .SE(dftIn), + .SI(registers_18__ap[12]) + ); + SDFF_X1_LVT \registers_reg[4][12] ( + .CK(n_0_34), .D(registers[12]), .Q(registers_4__ap[12]), .QN(), .SE(dftIn), + .SI(registers_31__ap[12]) + ); + AOI22_X1_LVT i_1_0_934( + .A1(registers_20__ap[12]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[12]), + .ZN(n_1_0_889) + ); + SDFF_X1_LVT \registers_reg[22][12] ( + .CK(n_0_52), .D(registers[12]), .Q(registers_22__ap[12]), .QN(), .SE(dftIn), + .SI(registers_20__ap[12]) + ); + SDFF_X1_LVT \registers_reg[21][12] ( + .CK(n_0_51), .D(registers[12]), .Q(registers_21__ap[12]), .QN(), .SE(dftIn), + .SI(registers_22__ap[12]) + ); + AOI22_X1_LVT i_1_0_933( + .A1(registers_22__ap[12]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[12]), + .ZN(n_1_0_888) + ); + SDFF_X1_LVT \registers_reg[24][12] ( + .CK(n_0_54), .D(registers[12]), .Q(registers_24__ap[12]), .QN(), .SE(dftIn), + .SI(registers_30__ap[12]) + ); + SDFF_X1_LVT \registers_reg[12][12] ( + .CK(n_0_42), .D(registers[12]), .Q(registers_12__ap[12]), .QN(), .SE(dftIn), + .SI(registers_15__ap[12]) + ); + AOI22_X1_LVT i_1_0_932( + .A1(registers_24__ap[12]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[12]), + .ZN(n_1_0_887) + ); + NAND4_X1_LVT i_1_0_931( + .A1(n_1_0_890), .A2(n_1_0_889), .A3(n_1_0_888), .A4(n_1_0_887), .ZN(n_1_0_886) + ); + SDFF_X1_LVT \registers_reg[13][12] ( + .CK(n_0_43), .D(registers[12]), .Q(registers_13__ap[12]), .QN(), .SE(dftIn), + .SI(registers_12__ap[12]) + ); + SDFF_X1_LVT \registers_reg[25][12] ( + .CK(n_0_55), .D(registers[12]), .Q(registers_25__ap[12]), .QN(), .SE(dftIn), + .SI(registers_24__ap[12]) + ); + AOI22_X1_LVT i_1_0_930( + .A1(registers_13__ap[12]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[12]), + .ZN(n_1_0_885) + ); + SDFF_X1_LVT \registers_reg[19][12] ( + .CK(n_0_49), .D(registers[12]), .Q(registers_19__ap[12]), .QN(), .SE(dftIn), + .SI(registers_21__ap[12]) + ); + SDFF_X1_LVT \registers_reg[2][12] ( + .CK(n_0_32), .D(registers[12]), .Q(registers_2__ap[12]), .QN(), .SE(dftIn), + .SI(registers_25__ap[12]) + ); + AOI22_X1_LVT i_1_0_929( + .A1(registers_19__ap[12]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[12]), + .ZN(n_1_0_884) + ); + SDFF_X1_LVT \registers_reg[7][12] ( + .CK(n_0_37), .D(registers[12]), .Q(registers_7__ap[12]), .QN(), .SE(dftIn), + .SI(registers_4__ap[12]) + ); + SDFF_X1_LVT \registers_reg[14][12] ( + .CK(n_0_44), .D(registers[12]), .Q(registers_14__ap[12]), .QN(), .SE(dftIn), + .SI(registers_13__ap[12]) + ); + AOI22_X1_LVT i_1_0_928( + .A1(registers_7__ap[12]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[12]), + .ZN(n_1_0_883) + ); + SDFF_X1_LVT \registers_reg[27][12] ( + .CK(n_0_57), .D(registers[12]), .Q(registers_27__ap[12]), .QN(), .SE(dftIn), + .SI(registers_2__ap[12]) + ); + SDFF_X1_LVT \registers_reg[11][12] ( + .CK(n_0_41), .D(registers[12]), .Q(registers_11__ap[12]), .QN(), .SE(dftIn), + .SI(registers_14__ap[12]) + ); + AOI22_X1_LVT i_1_0_927( + .A1(registers_27__ap[12]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[12]), + .ZN(n_1_0_882) + ); + NAND4_X1_LVT i_1_0_926( + .A1(n_1_0_885), .A2(n_1_0_884), .A3(n_1_0_883), .A4(n_1_0_882), .ZN(n_1_0_881) + ); + NOR3_X1_LVT i_1_0_925( + .A1(n_1_0_891), .A2(n_1_0_886), .A3(n_1_0_881), .ZN(n_1_0_880) + ); + NAND4_X1_LVT i_1_0_924( + .A1(n_1_0_898), .A2(n_1_0_897), .A3(n_1_0_896), .A4(n_1_0_880), .ZN(RRs1[12]) + ); + AND2_X1_LVT i_0_0_11( + .A1(n_0_0_16), .A2(WRd[11]), .ZN(registers[11]) + ); + SDFF_X1_LVT \registers_reg[28][11] ( + .CK(n_0_58), .D(registers[11]), .Q(registers_28__ap[11]), .QN(), .SE(dftIn), + .SI(registers_27__ap[12]) + ); + SDFF_X1_LVT \registers_reg[17][11] ( + .CK(n_0_47), .D(registers[11]), .Q(registers_17__ap[11]), .QN(), .SE(dftIn), + .SI(registers_19__ap[12]) + ); + AOI22_X1_LVT i_1_0_923( + .A1(registers_28__ap[11]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[11]), + .ZN(n_1_0_879) + ); + SDFF_X1_LVT \registers_reg[10][11] ( + .CK(n_0_40), .D(registers[11]), .Q(registers_10__ap[11]), .QN(), .SE(dftIn), + .SI(registers_11__ap[12]) + ); + SDFF_X1_LVT \registers_reg[26][11] ( + .CK(n_0_56), .D(registers[11]), .Q(registers_26__ap[11]), .QN(), .SE(dftIn), + .SI(registers_28__ap[11]) + ); + SDFF_X1_LVT \registers_reg[8][11] ( + .CK(n_0_38), .D(registers[11]), .Q(registers_8__ap[11]), .QN(), .SE(dftIn), + .SI(registers_7__ap[12]) + ); + AOI222_X1_LVT i_1_0_922( + .A1(registers_10__ap[11]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[11]), + .C1(registers_8__ap[11]), .C2(n_1_0_1282), .ZN(n_1_0_878) + ); + SDFF_X1_LVT \registers_reg[9][11] ( + .CK(n_0_39), .D(registers[11]), .Q(registers_9__ap[11]), .QN(), .SE(dftIn), + .SI(registers_8__ap[11]) + ); + SDFF_X1_LVT \registers_reg[29][11] ( + .CK(n_0_59), .D(registers[11]), .Q(registers_29__ap[11]), .QN(), .SE(dftIn), + .SI(registers_26__ap[11]) + ); + AOI22_X1_LVT i_1_0_921( + .A1(registers_9__ap[11]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[11]), + .ZN(n_1_0_877) + ); + SDFF_X1_LVT \registers_reg[6][11] ( + .CK(n_0_36), .D(registers[11]), .Q(registers_6__ap[11]), .QN(), .SE(dftIn), + .SI(registers_9__ap[11]) + ); + SDFF_X1_LVT \registers_reg[1][11] ( + .CK(n_0_0), .D(registers[11]), .Q(registers_1__ap[11]), .QN(), .SE(dftIn), + .SI(registers_17__ap[11]) + ); + AOI22_X1_LVT i_1_0_920( + .A1(registers_6__ap[11]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[11]), + .ZN(n_1_0_876) + ); + SDFF_X1_LVT \registers_reg[5][11] ( + .CK(n_0_35), .D(registers[11]), .Q(registers_5__ap[11]), .QN(), .SE(dftIn), + .SI(registers_6__ap[11]) + ); + SDFF_X1_LVT \registers_reg[3][11] ( + .CK(n_0_33), .D(registers[11]), .Q(registers_3__ap[11]), .QN(), .SE(dftIn), + .SI(registers_5__ap[11]) + ); + AOI22_X1_LVT i_1_0_919( + .A1(registers_5__ap[11]), .A2(n_1_0_1273), .B1(n_1_0_1257), .B2(registers_3__ap[11]), + .ZN(n_1_0_875) + ); + SDFF_X1_LVT \registers_reg[16][11] ( + .CK(n_0_46), .D(registers[11]), .Q(registers_16__ap[11]), .QN(), .SE(dftIn), + .SI(registers_10__ap[11]) + ); + SDFF_X1_LVT \registers_reg[31][11] ( + .CK(n_0_61), .D(registers[11]), .Q(registers_31__ap[11]), .QN(), .SE(dftIn), + .SI(registers_3__ap[11]) + ); + AOI22_X1_LVT i_1_0_918( + .A1(registers_16__ap[11]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[11]), + .ZN(n_1_0_874) + ); + SDFF_X1_LVT \registers_reg[15][11] ( + .CK(n_0_45), .D(registers[11]), .Q(registers_15__ap[11]), .QN(), .SE(dftIn), + .SI(registers_16__ap[11]) + ); + SDFF_X1_LVT \registers_reg[23][11] ( + .CK(n_0_53), .D(registers[11]), .Q(registers_23__ap[11]), .QN(), .SE(dftIn), + .SI(registers_1__ap[11]) + ); + AOI22_X1_LVT i_1_0_917( + .A1(registers_15__ap[11]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[11]), + .ZN(n_1_0_873) + ); + NAND4_X1_LVT i_1_0_916( + .A1(n_1_0_876), .A2(n_1_0_875), .A3(n_1_0_874), .A4(n_1_0_873), .ZN(n_1_0_872) + ); + SDFF_X1_LVT \registers_reg[18][11] ( + .CK(n_0_48), .D(registers[11]), .Q(registers_18__ap[11]), .QN(), .SE(dftIn), + .SI(registers_23__ap[11]) + ); + SDFF_X1_LVT \registers_reg[30][11] ( + .CK(n_0_60), .D(registers[11]), .Q(registers_30__ap[11]), .QN(), .SE(dftIn), + .SI(registers_29__ap[11]) + ); + AOI22_X1_LVT i_1_0_915( + .A1(registers_18__ap[11]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[11]), + .ZN(n_1_0_871) + ); + SDFF_X1_LVT \registers_reg[20][11] ( + .CK(n_0_50), .D(registers[11]), .Q(registers_20__ap[11]), .QN(), .SE(dftIn), + .SI(registers_18__ap[11]) + ); + SDFF_X1_LVT \registers_reg[4][11] ( + .CK(n_0_34), .D(registers[11]), .Q(registers_4__ap[11]), .QN(), .SE(dftIn), + .SI(registers_31__ap[11]) + ); + AOI22_X1_LVT i_1_0_914( + .A1(registers_20__ap[11]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[11]), + .ZN(n_1_0_870) + ); + SDFF_X1_LVT \registers_reg[22][11] ( + .CK(n_0_52), .D(registers[11]), .Q(registers_22__ap[11]), .QN(), .SE(dftIn), + .SI(registers_20__ap[11]) + ); + SDFF_X1_LVT \registers_reg[21][11] ( + .CK(n_0_51), .D(registers[11]), .Q(registers_21__ap[11]), .QN(), .SE(dftIn), + .SI(registers_22__ap[11]) + ); + AOI22_X1_LVT i_1_0_913( + .A1(registers_22__ap[11]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[11]), + .ZN(n_1_0_869) + ); + SDFF_X1_LVT \registers_reg[24][11] ( + .CK(n_0_54), .D(registers[11]), .Q(registers_24__ap[11]), .QN(), .SE(dftIn), + .SI(registers_30__ap[11]) + ); + SDFF_X1_LVT \registers_reg[12][11] ( + .CK(n_0_42), .D(registers[11]), .Q(registers_12__ap[11]), .QN(), .SE(dftIn), + .SI(registers_15__ap[11]) + ); + AOI22_X1_LVT i_1_0_912( + .A1(registers_24__ap[11]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[11]), + .ZN(n_1_0_868) + ); + NAND4_X1_LVT i_1_0_911( + .A1(n_1_0_871), .A2(n_1_0_870), .A3(n_1_0_869), .A4(n_1_0_868), .ZN(n_1_0_867) + ); + SDFF_X1_LVT \registers_reg[13][11] ( + .CK(n_0_43), .D(registers[11]), .Q(registers_13__ap[11]), .QN(), .SE(dftIn), + .SI(registers_12__ap[11]) + ); + SDFF_X1_LVT \registers_reg[25][11] ( + .CK(n_0_55), .D(registers[11]), .Q(registers_25__ap[11]), .QN(), .SE(dftIn), + .SI(registers_24__ap[11]) + ); + AOI22_X1_LVT i_1_0_910( + .A1(registers_13__ap[11]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[11]), + .ZN(n_1_0_866) + ); + SDFF_X1_LVT \registers_reg[19][11] ( + .CK(n_0_49), .D(registers[11]), .Q(registers_19__ap[11]), .QN(), .SE(dftIn), + .SI(registers_21__ap[11]) + ); + SDFF_X1_LVT \registers_reg[2][11] ( + .CK(n_0_32), .D(registers[11]), .Q(registers_2__ap[11]), .QN(), .SE(dftIn), + .SI(registers_25__ap[11]) + ); + AOI22_X1_LVT i_1_0_909( + .A1(registers_19__ap[11]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[11]), + .ZN(n_1_0_865) + ); + SDFF_X1_LVT \registers_reg[7][11] ( + .CK(n_0_37), .D(registers[11]), .Q(registers_7__ap[11]), .QN(), .SE(dftIn), + .SI(registers_4__ap[11]) + ); + SDFF_X1_LVT \registers_reg[14][11] ( + .CK(n_0_44), .D(registers[11]), .Q(registers_14__ap[11]), .QN(), .SE(dftIn), + .SI(registers_13__ap[11]) + ); + AOI22_X1_LVT i_1_0_908( + .A1(registers_7__ap[11]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[11]), + .ZN(n_1_0_864) + ); + SDFF_X1_LVT \registers_reg[27][11] ( + .CK(n_0_57), .D(registers[11]), .Q(registers_27__ap[11]), .QN(), .SE(dftIn), + .SI(registers_2__ap[11]) + ); + SDFF_X1_LVT \registers_reg[11][11] ( + .CK(n_0_41), .D(registers[11]), .Q(registers_11__ap[11]), .QN(), .SE(dftIn), + .SI(registers_14__ap[11]) + ); + AOI22_X1_LVT i_1_0_907( + .A1(registers_27__ap[11]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[11]), + .ZN(n_1_0_863) + ); + NAND4_X1_LVT i_1_0_906( + .A1(n_1_0_866), .A2(n_1_0_865), .A3(n_1_0_864), .A4(n_1_0_863), .ZN(n_1_0_862) + ); + NOR3_X1_LVT i_1_0_905( + .A1(n_1_0_872), .A2(n_1_0_867), .A3(n_1_0_862), .ZN(n_1_0_861) + ); + NAND4_X1_LVT i_1_0_904( + .A1(n_1_0_879), .A2(n_1_0_878), .A3(n_1_0_877), .A4(n_1_0_861), .ZN(RRs1[11]) + ); + AND2_X1_LVT i_0_0_10( + .A1(n_0_0_16), .A2(WRd[10]), .ZN(registers[10]) + ); + SDFF_X1_LVT \registers_reg[28][10] ( + .CK(n_0_58), .D(registers[10]), .Q(registers_28__ap[10]), .QN(), .SE(dftIn), + .SI(registers_27__ap[11]) + ); + SDFF_X1_LVT \registers_reg[8][10] ( + .CK(n_0_38), .D(registers[10]), .Q(registers_8__ap[10]), .QN(), .SE(dftIn), + .SI(registers_7__ap[11]) + ); + AOI22_X1_LVT i_1_0_902( + .A1(registers_28__ap[10]), .A2(n_1_0_1283), .B1(n_1_0_1282), .B2(registers_8__ap[10]), + .ZN(n_1_0_859) + ); + SDFF_X1_LVT \registers_reg[31][10] ( + .CK(n_0_61), .D(registers[10]), .Q(registers_31__ap[10]), .QN(), .SE(dftIn), + .SI(registers_8__ap[10]) + ); + SDFF_X1_LVT \registers_reg[7][10] ( + .CK(n_0_37), .D(registers[10]), .Q(registers_7__ap[10]), .QN(), .SE(dftIn), + .SI(registers_31__ap[10]) + ); + AOI22_X1_LVT i_1_0_903( + .A1(registers_31__ap[10]), .A2(n_1_0_1266), .B1(n_1_0_1263), .B2(registers_7__ap[10]), + .ZN(n_1_0_860) + ); + SDFF_X1_LVT \registers_reg[24][10] ( + .CK(n_0_54), .D(registers[10]), .Q(registers_24__ap[10]), .QN(), .SE(dftIn), + .SI(registers_28__ap[10]) + ); + SDFF_X1_LVT \registers_reg[20][10] ( + .CK(n_0_50), .D(registers[10]), .Q(registers_20__ap[10]), .QN(), .SE(dftIn), + .SI(registers_19__ap[11]) + ); + AOI22_X1_LVT i_1_0_901( + .A1(registers_24__ap[10]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[10]), + .ZN(n_1_0_858) + ); + SDFF_X1_LVT \registers_reg[4][10] ( + .CK(n_0_34), .D(registers[10]), .Q(registers_4__ap[10]), .QN(), .SE(dftIn), + .SI(registers_7__ap[10]) + ); + SDFF_X1_LVT \registers_reg[23][10] ( + .CK(n_0_53), .D(registers[10]), .Q(registers_23__ap[10]), .QN(), .SE(dftIn), + .SI(registers_20__ap[10]) + ); + AOI22_X1_LVT i_1_0_900( + .A1(registers_4__ap[10]), .A2(n_1_0_1278), .B1(n_1_0_1264), .B2(registers_23__ap[10]), + .ZN(n_1_0_857) + ); + NAND3_X1_LVT i_1_0_899( + .A1(n_1_0_860), .A2(n_1_0_858), .A3(n_1_0_857), .ZN(n_1_0_856) + ); + SDFF_X1_LVT \registers_reg[27][10] ( + .CK(n_0_57), .D(registers[10]), .Q(registers_27__ap[10]), .QN(), .SE(dftIn), + .SI(registers_24__ap[10]) + ); + SDFF_X1_LVT \registers_reg[29][10] ( + .CK(n_0_59), .D(registers[10]), .Q(registers_29__ap[10]), .QN(), .SE(dftIn), + .SI(registers_27__ap[10]) + ); + AOI221_X1_LVT i_1_0_898( + .A(n_1_0_856), .B1(n_1_0_1279), .B2(registers_27__ap[10]), .C1(registers_29__ap[10]), + .C2(n_1_0_1276), .ZN(n_1_0_855) + ); + SDFF_X1_LVT \registers_reg[10][10] ( + .CK(n_0_40), .D(registers[10]), .Q(registers_10__ap[10]), .QN(), .SE(dftIn), + .SI(registers_11__ap[11]) + ); + SDFF_X1_LVT \registers_reg[30][10] ( + .CK(n_0_60), .D(registers[10]), .Q(registers_30__ap[10]), .QN(), .SE(dftIn), + .SI(registers_29__ap[10]) + ); + SDFF_X1_LVT \registers_reg[25][10] ( + .CK(n_0_55), .D(registers[10]), .Q(registers_25__ap[10]), .QN(), .SE(dftIn), + .SI(registers_30__ap[10]) + ); + AOI222_X1_LVT i_1_0_897( + .A1(registers_10__ap[10]), .A2(n_1_0_1287), .B1(n_1_0_1272), .B2(registers_30__ap[10]), + .C1(n_1_0_1269), .C2(registers_25__ap[10]), .ZN(n_1_0_854) + ); + NAND3_X1_LVT i_1_0_896( + .A1(n_1_0_859), .A2(n_1_0_855), .A3(n_1_0_854), .ZN(n_1_0_853) + ); + SDFF_X1_LVT \registers_reg[21][10] ( + .CK(n_0_51), .D(registers[10]), .Q(registers_21__ap[10]), .QN(), .SE(dftIn), + .SI(registers_23__ap[10]) + ); + SDFF_X1_LVT \registers_reg[13][10] ( + .CK(n_0_43), .D(registers[10]), .Q(registers_13__ap[10]), .QN(), .SE(dftIn), + .SI(registers_10__ap[10]) + ); + AOI221_X1_LVT i_1_0_895( + .A(n_1_0_853), .B1(n_1_0_1259), .B2(registers_21__ap[10]), .C1(registers_13__ap[10]), + .C2(n_1_0_1277), .ZN(n_1_0_852) + ); + SDFF_X1_LVT \registers_reg[18][10] ( + .CK(n_0_48), .D(registers[10]), .Q(registers_18__ap[10]), .QN(), .SE(dftIn), + .SI(registers_21__ap[10]) + ); + SDFF_X1_LVT \registers_reg[26][10] ( + .CK(n_0_56), .D(registers[10]), .Q(registers_26__ap[10]), .QN(), .SE(dftIn), + .SI(registers_25__ap[10]) + ); + AOI22_X1_LVT i_1_0_894( + .A1(registers_18__ap[10]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[10]), + .ZN(n_1_0_851) + ); + SDFF_X1_LVT \registers_reg[17][10] ( + .CK(n_0_47), .D(registers[10]), .Q(registers_17__ap[10]), .QN(), .SE(dftIn), + .SI(registers_18__ap[10]) + ); + SDFF_X1_LVT \registers_reg[12][10] ( + .CK(n_0_42), .D(registers[10]), .Q(registers_12__ap[10]), .QN(), .SE(dftIn), + .SI(registers_13__ap[10]) + ); + AOI22_X1_LVT i_1_0_893( + .A1(registers_17__ap[10]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[10]), + .ZN(n_1_0_850) + ); + SDFF_X1_LVT \registers_reg[15][10] ( + .CK(n_0_45), .D(registers[10]), .Q(registers_15__ap[10]), .QN(), .SE(dftIn), + .SI(registers_12__ap[10]) + ); + SDFF_X1_LVT \registers_reg[5][10] ( + .CK(n_0_35), .D(registers[10]), .Q(registers_5__ap[10]), .QN(), .SE(dftIn), + .SI(registers_4__ap[10]) + ); + AOI22_X1_LVT i_1_0_892( + .A1(registers_15__ap[10]), .A2(n_1_0_1286), .B1(n_1_0_1273), .B2(registers_5__ap[10]), + .ZN(n_1_0_849) + ); + NAND3_X1_LVT i_1_0_891( + .A1(n_1_0_851), .A2(n_1_0_850), .A3(n_1_0_849), .ZN(n_1_0_848) + ); + SDFF_X1_LVT \registers_reg[22][10] ( + .CK(n_0_52), .D(registers[10]), .Q(registers_22__ap[10]), .QN(), .SE(dftIn), + .SI(registers_17__ap[10]) + ); + SDFF_X1_LVT \registers_reg[16][10] ( + .CK(n_0_46), .D(registers[10]), .Q(registers_16__ap[10]), .QN(), .SE(dftIn), + .SI(registers_15__ap[10]) + ); + AOI221_X1_LVT i_1_0_890( + .A(n_1_0_848), .B1(n_1_0_1294), .B2(registers_22__ap[10]), .C1(registers_16__ap[10]), + .C2(n_1_0_1267), .ZN(n_1_0_847) + ); + SDFF_X1_LVT \registers_reg[9][10] ( + .CK(n_0_39), .D(registers[10]), .Q(registers_9__ap[10]), .QN(), .SE(dftIn), + .SI(registers_5__ap[10]) + ); + SDFF_X1_LVT \registers_reg[1][10] ( + .CK(n_0_0), .D(registers[10]), .Q(registers_1__ap[10]), .QN(), .SE(dftIn), + .SI(registers_22__ap[10]) + ); + AOI22_X1_LVT i_1_0_889( + .A1(registers_9__ap[10]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[10]), + .ZN(n_1_0_846) + ); + SDFF_X1_LVT \registers_reg[6][10] ( + .CK(n_0_36), .D(registers[10]), .Q(registers_6__ap[10]), .QN(), .SE(dftIn), + .SI(registers_9__ap[10]) + ); + SDFF_X1_LVT \registers_reg[14][10] ( + .CK(n_0_44), .D(registers[10]), .Q(registers_14__ap[10]), .QN(), .SE(dftIn), + .SI(registers_16__ap[10]) + ); + AOI22_X1_LVT i_1_0_888( + .A1(registers_6__ap[10]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[10]), + .ZN(n_1_0_845) + ); + SDFF_X1_LVT \registers_reg[19][10] ( + .CK(n_0_49), .D(registers[10]), .Q(registers_19__ap[10]), .QN(), .SE(dftIn), + .SI(registers_1__ap[10]) + ); + SDFF_X1_LVT \registers_reg[3][10] ( + .CK(n_0_33), .D(registers[10]), .Q(registers_3__ap[10]), .QN(), .SE(dftIn), + .SI(registers_6__ap[10]) + ); + AOI22_X1_LVT i_1_0_887( + .A1(registers_19__ap[10]), .A2(n_1_0_1295), .B1(n_1_0_1257), .B2(registers_3__ap[10]), + .ZN(n_1_0_844) + ); + NAND3_X1_LVT i_1_0_886( + .A1(n_1_0_846), .A2(n_1_0_845), .A3(n_1_0_844), .ZN(n_1_0_843) + ); + SDFF_X1_LVT \registers_reg[11][10] ( + .CK(n_0_41), .D(registers[10]), .Q(registers_11__ap[10]), .QN(), .SE(dftIn), + .SI(registers_14__ap[10]) + ); + SDFF_X1_LVT \registers_reg[2][10] ( + .CK(n_0_32), .D(registers[10]), .Q(registers_2__ap[10]), .QN(), .SE(dftIn), + .SI(registers_26__ap[10]) + ); + AOI221_X1_LVT i_1_0_885( + .A(n_1_0_843), .B1(n_1_0_1270), .B2(registers_11__ap[10]), .C1(registers_2__ap[10]), + .C2(n_1_0_1268), .ZN(n_1_0_842) + ); + NAND3_X1_LVT i_1_0_884( + .A1(n_1_0_852), .A2(n_1_0_847), .A3(n_1_0_842), .ZN(RRs1[10]) + ); + AND2_X1_LVT i_0_0_9( + .A1(n_0_0_16), .A2(WRd[9]), .ZN(registers[9]) + ); + SDFF_X1_LVT \registers_reg[13][9] ( + .CK(n_0_43), .D(registers[9]), .Q(registers_13__ap[9]), .QN(), .SE(dftIn), + .SI(registers_11__ap[10]) + ); + SDFF_X1_LVT \registers_reg[21][9] ( + .CK(n_0_51), .D(registers[9]), .Q(registers_21__ap[9]), .QN(), .SE(dftIn), + .SI(registers_19__ap[10]) + ); + AOI22_X1_LVT i_1_0_880( + .A1(registers_13__ap[9]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[9]), + .ZN(n_1_0_838) + ); + SDFF_X1_LVT \registers_reg[29][9] ( + .CK(n_0_59), .D(registers[9]), .Q(registers_29__ap[9]), .QN(), .SE(dftIn), + .SI(registers_2__ap[10]) + ); + SDFF_X1_LVT \registers_reg[23][9] ( + .CK(n_0_53), .D(registers[9]), .Q(registers_23__ap[9]), .QN(), .SE(dftIn), + .SI(registers_21__ap[9]) + ); + AOI22_X1_LVT i_1_0_883( + .A1(registers_29__ap[9]), .A2(n_1_0_1276), .B1(n_1_0_1264), .B2(registers_23__ap[9]), + .ZN(n_1_0_841) + ); + SDFF_X1_LVT \registers_reg[24][9] ( + .CK(n_0_54), .D(registers[9]), .Q(registers_24__ap[9]), .QN(), .SE(dftIn), + .SI(registers_29__ap[9]) + ); + SDFF_X1_LVT \registers_reg[20][9] ( + .CK(n_0_50), .D(registers[9]), .Q(registers_20__ap[9]), .QN(), .SE(dftIn), + .SI(registers_23__ap[9]) + ); + AOI22_X1_LVT i_1_0_879( + .A1(registers_24__ap[9]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[9]), + .ZN(n_1_0_837) + ); + SDFF_X1_LVT \registers_reg[7][9] ( + .CK(n_0_37), .D(registers[9]), .Q(registers_7__ap[9]), .QN(), .SE(dftIn), + .SI(registers_3__ap[10]) + ); + SDFF_X1_LVT \registers_reg[3][9] ( + .CK(n_0_33), .D(registers[9]), .Q(registers_3__ap[9]), .QN(), .SE(dftIn), + .SI(registers_7__ap[9]) + ); + AOI22_X1_LVT i_1_0_882( + .A1(registers_7__ap[9]), .A2(n_1_0_1263), .B1(n_1_0_1257), .B2(registers_3__ap[9]), + .ZN(n_1_0_840) + ); + INV_X1_LVT i_1_0_881( + .A(n_1_0_840), .ZN(n_1_0_839) + ); + SDFF_X1_LVT \registers_reg[31][9] ( + .CK(n_0_61), .D(registers[9]), .Q(registers_31__ap[9]), .QN(), .SE(dftIn), + .SI(registers_3__ap[9]) + ); + SDFF_X1_LVT \registers_reg[4][9] ( + .CK(n_0_34), .D(registers[9]), .Q(registers_4__ap[9]), .QN(), .SE(dftIn), + .SI(registers_31__ap[9]) + ); + AOI221_X1_LVT i_1_0_878( + .A(n_1_0_839), .B1(n_1_0_1266), .B2(registers_31__ap[9]), .C1(registers_4__ap[9]), + .C2(n_1_0_1278), .ZN(n_1_0_836) + ); + SDFF_X1_LVT \registers_reg[10][9] ( + .CK(n_0_40), .D(registers[9]), .Q(registers_10__ap[9]), .QN(), .SE(dftIn), + .SI(registers_13__ap[9]) + ); + SDFF_X1_LVT \registers_reg[26][9] ( + .CK(n_0_56), .D(registers[9]), .Q(registers_26__ap[9]), .QN(), .SE(dftIn), + .SI(registers_24__ap[9]) + ); + SDFF_X1_LVT \registers_reg[25][9] ( + .CK(n_0_55), .D(registers[9]), .Q(registers_25__ap[9]), .QN(), .SE(dftIn), + .SI(registers_26__ap[9]) + ); + AOI222_X1_LVT i_1_0_877( + .A1(registers_10__ap[9]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[9]), + .C1(registers_25__ap[9]), .C2(n_1_0_1269), .ZN(n_1_0_835) + ); + NAND4_X1_LVT i_1_0_876( + .A1(n_1_0_841), .A2(n_1_0_837), .A3(n_1_0_836), .A4(n_1_0_835), .ZN(n_1_0_834) + ); + SDFF_X1_LVT \registers_reg[8][9] ( + .CK(n_0_38), .D(registers[9]), .Q(registers_8__ap[9]), .QN(), .SE(dftIn), + .SI(registers_4__ap[9]) + ); + SDFF_X1_LVT \registers_reg[28][9] ( + .CK(n_0_58), .D(registers[9]), .Q(registers_28__ap[9]), .QN(), .SE(dftIn), + .SI(registers_25__ap[9]) + ); + AOI221_X1_LVT i_1_0_875( + .A(n_1_0_834), .B1(n_1_0_1282), .B2(registers_8__ap[9]), .C1(registers_28__ap[9]), + .C2(n_1_0_1283), .ZN(n_1_0_833) + ); + SDFF_X1_LVT \registers_reg[18][9] ( + .CK(n_0_48), .D(registers[9]), .Q(registers_18__ap[9]), .QN(), .SE(dftIn), + .SI(registers_20__ap[9]) + ); + SDFF_X1_LVT \registers_reg[30][9] ( + .CK(n_0_60), .D(registers[9]), .Q(registers_30__ap[9]), .QN(), .SE(dftIn), + .SI(registers_28__ap[9]) + ); + AOI22_X1_LVT i_1_0_874( + .A1(registers_18__ap[9]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[9]), + .ZN(n_1_0_832) + ); + SDFF_X1_LVT \registers_reg[17][9] ( + .CK(n_0_47), .D(registers[9]), .Q(registers_17__ap[9]), .QN(), .SE(dftIn), + .SI(registers_18__ap[9]) + ); + SDFF_X1_LVT \registers_reg[12][9] ( + .CK(n_0_42), .D(registers[9]), .Q(registers_12__ap[9]), .QN(), .SE(dftIn), + .SI(registers_10__ap[9]) + ); + AOI22_X1_LVT i_1_0_873( + .A1(registers_17__ap[9]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[9]), + .ZN(n_1_0_831) + ); + SDFF_X1_LVT \registers_reg[15][9] ( + .CK(n_0_45), .D(registers[9]), .Q(registers_15__ap[9]), .QN(), .SE(dftIn), + .SI(registers_12__ap[9]) + ); + SDFF_X1_LVT \registers_reg[5][9] ( + .CK(n_0_35), .D(registers[9]), .Q(registers_5__ap[9]), .QN(), .SE(dftIn), + .SI(registers_8__ap[9]) + ); + AOI22_X1_LVT i_1_0_872( + .A1(registers_15__ap[9]), .A2(n_1_0_1286), .B1(n_1_0_1273), .B2(registers_5__ap[9]), + .ZN(n_1_0_830) + ); + NAND3_X1_LVT i_1_0_871( + .A1(n_1_0_832), .A2(n_1_0_831), .A3(n_1_0_830), .ZN(n_1_0_829) + ); + SDFF_X1_LVT \registers_reg[22][9] ( + .CK(n_0_52), .D(registers[9]), .Q(registers_22__ap[9]), .QN(), .SE(dftIn), + .SI(registers_17__ap[9]) + ); + SDFF_X1_LVT \registers_reg[16][9] ( + .CK(n_0_46), .D(registers[9]), .Q(registers_16__ap[9]), .QN(), .SE(dftIn), + .SI(registers_15__ap[9]) + ); + AOI221_X1_LVT i_1_0_870( + .A(n_1_0_829), .B1(n_1_0_1294), .B2(registers_22__ap[9]), .C1(registers_16__ap[9]), + .C2(n_1_0_1267), .ZN(n_1_0_828) + ); + SDFF_X1_LVT \registers_reg[9][9] ( + .CK(n_0_39), .D(registers[9]), .Q(registers_9__ap[9]), .QN(), .SE(dftIn), + .SI(registers_5__ap[9]) + ); + SDFF_X1_LVT \registers_reg[1][9] ( + .CK(n_0_0), .D(registers[9]), .Q(registers_1__ap[9]), .QN(), .SE(dftIn), + .SI(registers_22__ap[9]) + ); + AOI22_X1_LVT i_1_0_869( + .A1(registers_9__ap[9]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[9]), + .ZN(n_1_0_827) + ); + SDFF_X1_LVT \registers_reg[6][9] ( + .CK(n_0_36), .D(registers[9]), .Q(registers_6__ap[9]), .QN(), .SE(dftIn), + .SI(registers_9__ap[9]) + ); + SDFF_X1_LVT \registers_reg[14][9] ( + .CK(n_0_44), .D(registers[9]), .Q(registers_14__ap[9]), .QN(), .SE(dftIn), + .SI(registers_16__ap[9]) + ); + AOI22_X1_LVT i_1_0_868( + .A1(registers_6__ap[9]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[9]), + .ZN(n_1_0_826) + ); + SDFF_X1_LVT \registers_reg[19][9] ( + .CK(n_0_49), .D(registers[9]), .Q(registers_19__ap[9]), .QN(), .SE(dftIn), + .SI(registers_1__ap[9]) + ); + SDFF_X1_LVT \registers_reg[2][9] ( + .CK(n_0_32), .D(registers[9]), .Q(registers_2__ap[9]), .QN(), .SE(dftIn), + .SI(registers_30__ap[9]) + ); + AOI22_X1_LVT i_1_0_867( + .A1(registers_19__ap[9]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[9]), + .ZN(n_1_0_825) + ); + NAND3_X1_LVT i_1_0_866( + .A1(n_1_0_827), .A2(n_1_0_826), .A3(n_1_0_825), .ZN(n_1_0_824) + ); + SDFF_X1_LVT \registers_reg[11][9] ( + .CK(n_0_41), .D(registers[9]), .Q(registers_11__ap[9]), .QN(), .SE(dftIn), + .SI(registers_14__ap[9]) + ); + SDFF_X1_LVT \registers_reg[27][9] ( + .CK(n_0_57), .D(registers[9]), .Q(registers_27__ap[9]), .QN(), .SE(dftIn), + .SI(registers_2__ap[9]) + ); + AOI221_X1_LVT i_1_0_865( + .A(n_1_0_824), .B1(n_1_0_1270), .B2(registers_11__ap[9]), .C1(registers_27__ap[9]), + .C2(n_1_0_1279), .ZN(n_1_0_823) + ); + NAND4_X1_LVT i_1_0_864( + .A1(n_1_0_838), .A2(n_1_0_833), .A3(n_1_0_828), .A4(n_1_0_823), .ZN(RRs1[9]) + ); + AND2_X1_LVT i_0_0_8( + .A1(n_0_0_16), .A2(WRd[8]), .ZN(registers[8]) + ); + SDFF_X1_LVT \registers_reg[13][8] ( + .CK(n_0_43), .D(registers[8]), .Q(registers_13__ap[8]), .QN(), .SE(dftIn), + .SI(registers_11__ap[9]) + ); + SDFF_X1_LVT \registers_reg[21][8] ( + .CK(n_0_51), .D(registers[8]), .Q(registers_21__ap[8]), .QN(), .SE(dftIn), + .SI(registers_19__ap[9]) + ); + AOI22_X1_LVT i_1_0_860( + .A1(registers_13__ap[8]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[8]), + .ZN(n_1_0_819) + ); + SDFF_X1_LVT \registers_reg[29][8] ( + .CK(n_0_59), .D(registers[8]), .Q(registers_29__ap[8]), .QN(), .SE(dftIn), + .SI(registers_27__ap[9]) + ); + SDFF_X1_LVT \registers_reg[23][8] ( + .CK(n_0_53), .D(registers[8]), .Q(registers_23__ap[8]), .QN(), .SE(dftIn), + .SI(registers_21__ap[8]) + ); + AOI22_X1_LVT i_1_0_863( + .A1(registers_29__ap[8]), .A2(n_1_0_1276), .B1(n_1_0_1264), .B2(registers_23__ap[8]), + .ZN(n_1_0_822) + ); + SDFF_X1_LVT \registers_reg[24][8] ( + .CK(n_0_54), .D(registers[8]), .Q(registers_24__ap[8]), .QN(), .SE(dftIn), + .SI(registers_29__ap[8]) + ); + SDFF_X1_LVT \registers_reg[20][8] ( + .CK(n_0_50), .D(registers[8]), .Q(registers_20__ap[8]), .QN(), .SE(dftIn), + .SI(registers_23__ap[8]) + ); + AOI22_X1_LVT i_1_0_859( + .A1(registers_24__ap[8]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[8]), + .ZN(n_1_0_818) + ); + SDFF_X1_LVT \registers_reg[7][8] ( + .CK(n_0_37), .D(registers[8]), .Q(registers_7__ap[8]), .QN(), .SE(dftIn), + .SI(registers_6__ap[9]) + ); + SDFF_X1_LVT \registers_reg[3][8] ( + .CK(n_0_33), .D(registers[8]), .Q(registers_3__ap[8]), .QN(), .SE(dftIn), + .SI(registers_7__ap[8]) + ); + AOI22_X1_LVT i_1_0_862( + .A1(registers_7__ap[8]), .A2(n_1_0_1263), .B1(n_1_0_1257), .B2(registers_3__ap[8]), + .ZN(n_1_0_821) + ); + INV_X1_LVT i_1_0_861( + .A(n_1_0_821), .ZN(n_1_0_820) + ); + SDFF_X1_LVT \registers_reg[31][8] ( + .CK(n_0_61), .D(registers[8]), .Q(registers_31__ap[8]), .QN(), .SE(dftIn), + .SI(registers_3__ap[8]) + ); + SDFF_X1_LVT \registers_reg[4][8] ( + .CK(n_0_34), .D(registers[8]), .Q(registers_4__ap[8]), .QN(), .SE(dftIn), + .SI(registers_31__ap[8]) + ); + AOI221_X1_LVT i_1_0_858( + .A(n_1_0_820), .B1(n_1_0_1266), .B2(registers_31__ap[8]), .C1(registers_4__ap[8]), + .C2(n_1_0_1278), .ZN(n_1_0_817) + ); + SDFF_X1_LVT \registers_reg[10][8] ( + .CK(n_0_40), .D(registers[8]), .Q(registers_10__ap[8]), .QN(), .SE(dftIn), + .SI(registers_13__ap[8]) + ); + SDFF_X1_LVT \registers_reg[26][8] ( + .CK(n_0_56), .D(registers[8]), .Q(registers_26__ap[8]), .QN(), .SE(dftIn), + .SI(registers_24__ap[8]) + ); + SDFF_X1_LVT \registers_reg[25][8] ( + .CK(n_0_55), .D(registers[8]), .Q(registers_25__ap[8]), .QN(), .SE(dftIn), + .SI(registers_26__ap[8]) + ); + AOI222_X1_LVT i_1_0_857( + .A1(registers_10__ap[8]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[8]), + .C1(registers_25__ap[8]), .C2(n_1_0_1269), .ZN(n_1_0_816) + ); + NAND4_X1_LVT i_1_0_856( + .A1(n_1_0_822), .A2(n_1_0_818), .A3(n_1_0_817), .A4(n_1_0_816), .ZN(n_1_0_815) + ); + SDFF_X1_LVT \registers_reg[8][8] ( + .CK(n_0_38), .D(registers[8]), .Q(registers_8__ap[8]), .QN(), .SE(dftIn), + .SI(registers_4__ap[8]) + ); + SDFF_X1_LVT \registers_reg[28][8] ( + .CK(n_0_58), .D(registers[8]), .Q(registers_28__ap[8]), .QN(), .SE(dftIn), + .SI(registers_25__ap[8]) + ); + AOI221_X1_LVT i_1_0_855( + .A(n_1_0_815), .B1(n_1_0_1282), .B2(registers_8__ap[8]), .C1(registers_28__ap[8]), + .C2(n_1_0_1283), .ZN(n_1_0_814) + ); + SDFF_X1_LVT \registers_reg[18][8] ( + .CK(n_0_48), .D(registers[8]), .Q(registers_18__ap[8]), .QN(), .SE(dftIn), + .SI(registers_20__ap[8]) + ); + SDFF_X1_LVT \registers_reg[30][8] ( + .CK(n_0_60), .D(registers[8]), .Q(registers_30__ap[8]), .QN(), .SE(dftIn), + .SI(registers_28__ap[8]) + ); + AOI22_X1_LVT i_1_0_854( + .A1(registers_18__ap[8]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[8]), + .ZN(n_1_0_813) + ); + SDFF_X1_LVT \registers_reg[17][8] ( + .CK(n_0_47), .D(registers[8]), .Q(registers_17__ap[8]), .QN(), .SE(dftIn), + .SI(registers_18__ap[8]) + ); + SDFF_X1_LVT \registers_reg[12][8] ( + .CK(n_0_42), .D(registers[8]), .Q(registers_12__ap[8]), .QN(), .SE(dftIn), + .SI(registers_10__ap[8]) + ); + AOI22_X1_LVT i_1_0_853( + .A1(registers_17__ap[8]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[8]), + .ZN(n_1_0_812) + ); + SDFF_X1_LVT \registers_reg[15][8] ( + .CK(n_0_45), .D(registers[8]), .Q(registers_15__ap[8]), .QN(), .SE(dftIn), + .SI(registers_12__ap[8]) + ); + SDFF_X1_LVT \registers_reg[5][8] ( + .CK(n_0_35), .D(registers[8]), .Q(registers_5__ap[8]), .QN(), .SE(dftIn), + .SI(registers_8__ap[8]) + ); + AOI22_X1_LVT i_1_0_852( + .A1(registers_15__ap[8]), .A2(n_1_0_1286), .B1(n_1_0_1273), .B2(registers_5__ap[8]), + .ZN(n_1_0_811) + ); + NAND3_X1_LVT i_1_0_851( + .A1(n_1_0_813), .A2(n_1_0_812), .A3(n_1_0_811), .ZN(n_1_0_810) + ); + SDFF_X1_LVT \registers_reg[22][8] ( + .CK(n_0_52), .D(registers[8]), .Q(registers_22__ap[8]), .QN(), .SE(dftIn), + .SI(registers_17__ap[8]) + ); + SDFF_X1_LVT \registers_reg[16][8] ( + .CK(n_0_46), .D(registers[8]), .Q(registers_16__ap[8]), .QN(), .SE(dftIn), + .SI(registers_15__ap[8]) + ); + AOI221_X1_LVT i_1_0_850( + .A(n_1_0_810), .B1(n_1_0_1294), .B2(registers_22__ap[8]), .C1(registers_16__ap[8]), + .C2(n_1_0_1267), .ZN(n_1_0_809) + ); + SDFF_X1_LVT \registers_reg[9][8] ( + .CK(n_0_39), .D(registers[8]), .Q(registers_9__ap[8]), .QN(), .SE(dftIn), + .SI(registers_5__ap[8]) + ); + SDFF_X1_LVT \registers_reg[1][8] ( + .CK(n_0_0), .D(registers[8]), .Q(registers_1__ap[8]), .QN(), .SE(dftIn), + .SI(registers_22__ap[8]) + ); + AOI22_X1_LVT i_1_0_849( + .A1(registers_9__ap[8]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[8]), + .ZN(n_1_0_808) + ); + SDFF_X1_LVT \registers_reg[6][8] ( + .CK(n_0_36), .D(registers[8]), .Q(registers_6__ap[8]), .QN(), .SE(dftIn), + .SI(registers_9__ap[8]) + ); + SDFF_X1_LVT \registers_reg[14][8] ( + .CK(n_0_44), .D(registers[8]), .Q(registers_14__ap[8]), .QN(), .SE(dftIn), + .SI(registers_16__ap[8]) + ); + AOI22_X1_LVT i_1_0_848( + .A1(registers_6__ap[8]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[8]), + .ZN(n_1_0_807) + ); + SDFF_X1_LVT \registers_reg[19][8] ( + .CK(n_0_49), .D(registers[8]), .Q(registers_19__ap[8]), .QN(), .SE(dftIn), + .SI(registers_1__ap[8]) + ); + SDFF_X1_LVT \registers_reg[2][8] ( + .CK(n_0_32), .D(registers[8]), .Q(registers_2__ap[8]), .QN(), .SE(dftIn), + .SI(registers_30__ap[8]) + ); + AOI22_X1_LVT i_1_0_847( + .A1(registers_19__ap[8]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[8]), + .ZN(n_1_0_806) + ); + NAND3_X1_LVT i_1_0_846( + .A1(n_1_0_808), .A2(n_1_0_807), .A3(n_1_0_806), .ZN(n_1_0_805) + ); + SDFF_X1_LVT \registers_reg[11][8] ( + .CK(n_0_41), .D(registers[8]), .Q(registers_11__ap[8]), .QN(), .SE(dftIn), + .SI(registers_14__ap[8]) + ); + SDFF_X1_LVT \registers_reg[27][8] ( + .CK(n_0_57), .D(registers[8]), .Q(registers_27__ap[8]), .QN(), .SE(dftIn), + .SI(registers_2__ap[8]) + ); + AOI221_X1_LVT i_1_0_845( + .A(n_1_0_805), .B1(n_1_0_1270), .B2(registers_11__ap[8]), .C1(registers_27__ap[8]), + .C2(n_1_0_1279), .ZN(n_1_0_804) + ); + NAND4_X1_LVT i_1_0_844( + .A1(n_1_0_819), .A2(n_1_0_814), .A3(n_1_0_809), .A4(n_1_0_804), .ZN(RRs1[8]) + ); + AND2_X1_LVT i_0_0_7( + .A1(n_0_0_16), .A2(WRd[7]), .ZN(registers[7]) + ); + SDFF_X1_LVT \registers_reg[13][7] ( + .CK(n_0_43), .D(registers[7]), .Q(registers_13__ap[7]), .QN(), .SE(dftIn), + .SI(registers_11__ap[8]) + ); + SDFF_X1_LVT \registers_reg[21][7] ( + .CK(n_0_51), .D(registers[7]), .Q(registers_21__ap[7]), .QN(), .SE(dftIn), + .SI(registers_19__ap[8]) + ); + AOI22_X1_LVT i_1_0_843( + .A1(registers_13__ap[7]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[7]), + .ZN(n_1_0_803) + ); + SDFF_X1_LVT \registers_reg[18][7] ( + .CK(n_0_48), .D(registers[7]), .Q(registers_18__ap[7]), .QN(), .SE(dftIn), + .SI(registers_21__ap[7]) + ); + SDFF_X1_LVT \registers_reg[10][7] ( + .CK(n_0_40), .D(registers[7]), .Q(registers_10__ap[7]), .QN(), .SE(dftIn), + .SI(registers_13__ap[7]) + ); + SDFF_X1_LVT \registers_reg[25][7] ( + .CK(n_0_55), .D(registers[7]), .Q(registers_25__ap[7]), .QN(), .SE(dftIn), + .SI(registers_27__ap[8]) + ); + AOI222_X1_LVT i_1_0_842( + .A1(registers_18__ap[7]), .A2(n_1_0_1297), .B1(n_1_0_1287), .B2(registers_10__ap[7]), + .C1(registers_25__ap[7]), .C2(n_1_0_1269), .ZN(n_1_0_802) + ); + SDFF_X1_LVT \registers_reg[28][7] ( + .CK(n_0_58), .D(registers[7]), .Q(registers_28__ap[7]), .QN(), .SE(dftIn), + .SI(registers_25__ap[7]) + ); + SDFF_X1_LVT \registers_reg[8][7] ( + .CK(n_0_38), .D(registers[7]), .Q(registers_8__ap[7]), .QN(), .SE(dftIn), + .SI(registers_6__ap[8]) + ); + AOI22_X1_LVT i_1_0_841( + .A1(registers_28__ap[7]), .A2(n_1_0_1283), .B1(n_1_0_1282), .B2(registers_8__ap[7]), + .ZN(n_1_0_801) + ); + SDFF_X1_LVT \registers_reg[24][7] ( + .CK(n_0_54), .D(registers[7]), .Q(registers_24__ap[7]), .QN(), .SE(dftIn), + .SI(registers_28__ap[7]) + ); + SDFF_X1_LVT \registers_reg[20][7] ( + .CK(n_0_50), .D(registers[7]), .Q(registers_20__ap[7]), .QN(), .SE(dftIn), + .SI(registers_18__ap[7]) + ); + AOI22_X1_LVT i_1_0_840( + .A1(registers_24__ap[7]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[7]), + .ZN(n_1_0_800) + ); + SDFF_X1_LVT \registers_reg[31][7] ( + .CK(n_0_61), .D(registers[7]), .Q(registers_31__ap[7]), .QN(), .SE(dftIn), + .SI(registers_8__ap[7]) + ); + SDFF_X1_LVT \registers_reg[7][7] ( + .CK(n_0_37), .D(registers[7]), .Q(registers_7__ap[7]), .QN(), .SE(dftIn), + .SI(registers_31__ap[7]) + ); + AOI22_X1_LVT i_1_0_839( + .A1(registers_31__ap[7]), .A2(n_1_0_1266), .B1(n_1_0_1263), .B2(registers_7__ap[7]), + .ZN(n_1_0_799) + ); + SDFF_X1_LVT \registers_reg[17][7] ( + .CK(n_0_47), .D(registers[7]), .Q(registers_17__ap[7]), .QN(), .SE(dftIn), + .SI(registers_20__ap[7]) + ); + SDFF_X1_LVT \registers_reg[11][7] ( + .CK(n_0_41), .D(registers[7]), .Q(registers_11__ap[7]), .QN(), .SE(dftIn), + .SI(registers_10__ap[7]) + ); + AOI22_X1_LVT i_1_0_838( + .A1(registers_17__ap[7]), .A2(n_1_0_1271), .B1(n_1_0_1270), .B2(registers_11__ap[7]), + .ZN(n_1_0_798) + ); + SDFF_X1_LVT \registers_reg[27][7] ( + .CK(n_0_57), .D(registers[7]), .Q(registers_27__ap[7]), .QN(), .SE(dftIn), + .SI(registers_24__ap[7]) + ); + SDFF_X1_LVT \registers_reg[29][7] ( + .CK(n_0_59), .D(registers[7]), .Q(registers_29__ap[7]), .QN(), .SE(dftIn), + .SI(registers_27__ap[7]) + ); + AOI22_X1_LVT i_1_0_837( + .A1(registers_27__ap[7]), .A2(n_1_0_1279), .B1(n_1_0_1276), .B2(registers_29__ap[7]), + .ZN(n_1_0_797) + ); + NAND4_X1_LVT i_1_0_836( + .A1(n_1_0_800), .A2(n_1_0_799), .A3(n_1_0_798), .A4(n_1_0_797), .ZN(n_1_0_796) + ); + SDFF_X1_LVT \registers_reg[26][7] ( + .CK(n_0_56), .D(registers[7]), .Q(registers_26__ap[7]), .QN(), .SE(dftIn), + .SI(registers_29__ap[7]) + ); + SDFF_X1_LVT \registers_reg[30][7] ( + .CK(n_0_60), .D(registers[7]), .Q(registers_30__ap[7]), .QN(), .SE(dftIn), + .SI(registers_26__ap[7]) + ); + AOI22_X1_LVT i_1_0_835( + .A1(registers_26__ap[7]), .A2(n_1_0_1285), .B1(n_1_0_1272), .B2(registers_30__ap[7]), + .ZN(n_1_0_795) + ); + SDFF_X1_LVT \registers_reg[4][7] ( + .CK(n_0_34), .D(registers[7]), .Q(registers_4__ap[7]), .QN(), .SE(dftIn), + .SI(registers_7__ap[7]) + ); + SDFF_X1_LVT \registers_reg[12][7] ( + .CK(n_0_42), .D(registers[7]), .Q(registers_12__ap[7]), .QN(), .SE(dftIn), + .SI(registers_11__ap[7]) + ); + AOI22_X1_LVT i_1_0_834( + .A1(registers_4__ap[7]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[7]), + .ZN(n_1_0_794) + ); + SDFF_X1_LVT \registers_reg[15][7] ( + .CK(n_0_45), .D(registers[7]), .Q(registers_15__ap[7]), .QN(), .SE(dftIn), + .SI(registers_12__ap[7]) + ); + SDFF_X1_LVT \registers_reg[16][7] ( + .CK(n_0_46), .D(registers[7]), .Q(registers_16__ap[7]), .QN(), .SE(dftIn), + .SI(registers_15__ap[7]) + ); + AOI22_X1_LVT i_1_0_833( + .A1(registers_15__ap[7]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[7]), + .ZN(n_1_0_793) + ); + SDFF_X1_LVT \registers_reg[22][7] ( + .CK(n_0_52), .D(registers[7]), .Q(registers_22__ap[7]), .QN(), .SE(dftIn), + .SI(registers_17__ap[7]) + ); + SDFF_X1_LVT \registers_reg[5][7] ( + .CK(n_0_35), .D(registers[7]), .Q(registers_5__ap[7]), .QN(), .SE(dftIn), + .SI(registers_4__ap[7]) + ); + AOI22_X1_LVT i_1_0_832( + .A1(registers_22__ap[7]), .A2(n_1_0_1294), .B1(n_1_0_1273), .B2(registers_5__ap[7]), + .ZN(n_1_0_792) + ); + NAND4_X1_LVT i_1_0_831( + .A1(n_1_0_795), .A2(n_1_0_794), .A3(n_1_0_793), .A4(n_1_0_792), .ZN(n_1_0_791) + ); + SDFF_X1_LVT \registers_reg[19][7] ( + .CK(n_0_49), .D(registers[7]), .Q(registers_19__ap[7]), .QN(), .SE(dftIn), + .SI(registers_22__ap[7]) + ); + SDFF_X1_LVT \registers_reg[3][7] ( + .CK(n_0_33), .D(registers[7]), .Q(registers_3__ap[7]), .QN(), .SE(dftIn), + .SI(registers_5__ap[7]) + ); + AOI22_X1_LVT i_1_0_830( + .A1(registers_19__ap[7]), .A2(n_1_0_1295), .B1(n_1_0_1257), .B2(registers_3__ap[7]), + .ZN(n_1_0_790) + ); + SDFF_X1_LVT \registers_reg[9][7] ( + .CK(n_0_39), .D(registers[7]), .Q(registers_9__ap[7]), .QN(), .SE(dftIn), + .SI(registers_3__ap[7]) + ); + SDFF_X1_LVT \registers_reg[1][7] ( + .CK(n_0_0), .D(registers[7]), .Q(registers_1__ap[7]), .QN(), .SE(dftIn), + .SI(registers_19__ap[7]) + ); + AOI22_X1_LVT i_1_0_829( + .A1(registers_9__ap[7]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[7]), + .ZN(n_1_0_789) + ); + SDFF_X1_LVT \registers_reg[6][7] ( + .CK(n_0_36), .D(registers[7]), .Q(registers_6__ap[7]), .QN(), .SE(dftIn), + .SI(registers_9__ap[7]) + ); + SDFF_X1_LVT \registers_reg[14][7] ( + .CK(n_0_44), .D(registers[7]), .Q(registers_14__ap[7]), .QN(), .SE(dftIn), + .SI(registers_16__ap[7]) + ); + AOI22_X1_LVT i_1_0_828( + .A1(registers_6__ap[7]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[7]), + .ZN(n_1_0_788) + ); + SDFF_X1_LVT \registers_reg[2][7] ( + .CK(n_0_32), .D(registers[7]), .Q(registers_2__ap[7]), .QN(), .SE(dftIn), + .SI(registers_30__ap[7]) + ); + SDFF_X1_LVT \registers_reg[23][7] ( + .CK(n_0_53), .D(registers[7]), .Q(registers_23__ap[7]), .QN(), .SE(dftIn), + .SI(registers_1__ap[7]) + ); + AOI22_X1_LVT i_1_0_827( + .A1(registers_2__ap[7]), .A2(n_1_0_1268), .B1(n_1_0_1264), .B2(registers_23__ap[7]), + .ZN(n_1_0_787) + ); + NAND4_X1_LVT i_1_0_826( + .A1(n_1_0_790), .A2(n_1_0_789), .A3(n_1_0_788), .A4(n_1_0_787), .ZN(n_1_0_786) + ); + NOR3_X1_LVT i_1_0_825( + .A1(n_1_0_796), .A2(n_1_0_791), .A3(n_1_0_786), .ZN(n_1_0_785) + ); + NAND4_X1_LVT i_1_0_824( + .A1(n_1_0_803), .A2(n_1_0_802), .A3(n_1_0_801), .A4(n_1_0_785), .ZN(RRs1[7]) + ); + AND2_X1_LVT i_0_0_6( + .A1(n_0_0_16), .A2(WRd[6]), .ZN(registers[6]) + ); + SDFF_X1_LVT \registers_reg[28][6] ( + .CK(n_0_58), .D(registers[6]), .Q(registers_28__ap[6]), .QN(), .SE(dftIn), + .SI(registers_2__ap[7]) + ); + SDFF_X1_LVT \registers_reg[17][6] ( + .CK(n_0_47), .D(registers[6]), .Q(registers_17__ap[6]), .QN(), .SE(dftIn), + .SI(registers_23__ap[7]) + ); + AOI22_X1_LVT i_1_0_823( + .A1(registers_28__ap[6]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[6]), + .ZN(n_1_0_784) + ); + SDFF_X1_LVT \registers_reg[18][6] ( + .CK(n_0_48), .D(registers[6]), .Q(registers_18__ap[6]), .QN(), .SE(dftIn), + .SI(registers_17__ap[6]) + ); + SDFF_X1_LVT \registers_reg[10][6] ( + .CK(n_0_40), .D(registers[6]), .Q(registers_10__ap[6]), .QN(), .SE(dftIn), + .SI(registers_14__ap[7]) + ); + SDFF_X1_LVT \registers_reg[8][6] ( + .CK(n_0_38), .D(registers[6]), .Q(registers_8__ap[6]), .QN(), .SE(dftIn), + .SI(registers_6__ap[7]) + ); + AOI222_X1_LVT i_1_0_822( + .A1(registers_18__ap[6]), .A2(n_1_0_1297), .B1(n_1_0_1287), .B2(registers_10__ap[6]), + .C1(registers_8__ap[6]), .C2(n_1_0_1282), .ZN(n_1_0_783) + ); + SDFF_X1_LVT \registers_reg[9][6] ( + .CK(n_0_39), .D(registers[6]), .Q(registers_9__ap[6]), .QN(), .SE(dftIn), + .SI(registers_8__ap[6]) + ); + SDFF_X1_LVT \registers_reg[29][6] ( + .CK(n_0_59), .D(registers[6]), .Q(registers_29__ap[6]), .QN(), .SE(dftIn), + .SI(registers_28__ap[6]) + ); + AOI22_X1_LVT i_1_0_821( + .A1(registers_9__ap[6]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[6]), + .ZN(n_1_0_782) + ); + SDFF_X1_LVT \registers_reg[6][6] ( + .CK(n_0_36), .D(registers[6]), .Q(registers_6__ap[6]), .QN(), .SE(dftIn), + .SI(registers_9__ap[6]) + ); + SDFF_X1_LVT \registers_reg[1][6] ( + .CK(n_0_0), .D(registers[6]), .Q(registers_1__ap[6]), .QN(), .SE(dftIn), + .SI(registers_18__ap[6]) + ); + AOI22_X1_LVT i_1_0_820( + .A1(registers_6__ap[6]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[6]), + .ZN(n_1_0_781) + ); + SDFF_X1_LVT \registers_reg[15][6] ( + .CK(n_0_45), .D(registers[6]), .Q(registers_15__ap[6]), .QN(), .SE(dftIn), + .SI(registers_10__ap[6]) + ); + SDFF_X1_LVT \registers_reg[27][6] ( + .CK(n_0_57), .D(registers[6]), .Q(registers_27__ap[6]), .QN(), .SE(dftIn), + .SI(registers_29__ap[6]) + ); + AOI22_X1_LVT i_1_0_819( + .A1(registers_15__ap[6]), .A2(n_1_0_1286), .B1(n_1_0_1279), .B2(registers_27__ap[6]), + .ZN(n_1_0_780) + ); + SDFF_X1_LVT \registers_reg[11][6] ( + .CK(n_0_41), .D(registers[6]), .Q(registers_11__ap[6]), .QN(), .SE(dftIn), + .SI(registers_15__ap[6]) + ); + SDFF_X1_LVT \registers_reg[16][6] ( + .CK(n_0_46), .D(registers[6]), .Q(registers_16__ap[6]), .QN(), .SE(dftIn), + .SI(registers_11__ap[6]) + ); + AOI22_X1_LVT i_1_0_818( + .A1(registers_11__ap[6]), .A2(n_1_0_1270), .B1(n_1_0_1267), .B2(registers_16__ap[6]), + .ZN(n_1_0_779) + ); + SDFF_X1_LVT \registers_reg[5][6] ( + .CK(n_0_35), .D(registers[6]), .Q(registers_5__ap[6]), .QN(), .SE(dftIn), + .SI(registers_6__ap[6]) + ); + SDFF_X1_LVT \registers_reg[31][6] ( + .CK(n_0_61), .D(registers[6]), .Q(registers_31__ap[6]), .QN(), .SE(dftIn), + .SI(registers_5__ap[6]) + ); + AOI22_X1_LVT i_1_0_817( + .A1(registers_5__ap[6]), .A2(n_1_0_1273), .B1(n_1_0_1266), .B2(registers_31__ap[6]), + .ZN(n_1_0_778) + ); + NAND4_X1_LVT i_1_0_816( + .A1(n_1_0_781), .A2(n_1_0_780), .A3(n_1_0_779), .A4(n_1_0_778), .ZN(n_1_0_777) + ); + SDFF_X1_LVT \registers_reg[26][6] ( + .CK(n_0_56), .D(registers[6]), .Q(registers_26__ap[6]), .QN(), .SE(dftIn), + .SI(registers_27__ap[6]) + ); + SDFF_X1_LVT \registers_reg[30][6] ( + .CK(n_0_60), .D(registers[6]), .Q(registers_30__ap[6]), .QN(), .SE(dftIn), + .SI(registers_26__ap[6]) + ); + AOI22_X1_LVT i_1_0_815( + .A1(registers_26__ap[6]), .A2(n_1_0_1285), .B1(n_1_0_1272), .B2(registers_30__ap[6]), + .ZN(n_1_0_776) + ); + SDFF_X1_LVT \registers_reg[20][6] ( + .CK(n_0_50), .D(registers[6]), .Q(registers_20__ap[6]), .QN(), .SE(dftIn), + .SI(registers_1__ap[6]) + ); + SDFF_X1_LVT \registers_reg[4][6] ( + .CK(n_0_34), .D(registers[6]), .Q(registers_4__ap[6]), .QN(), .SE(dftIn), + .SI(registers_31__ap[6]) + ); + AOI22_X1_LVT i_1_0_814( + .A1(registers_20__ap[6]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[6]), + .ZN(n_1_0_775) + ); + SDFF_X1_LVT \registers_reg[22][6] ( + .CK(n_0_52), .D(registers[6]), .Q(registers_22__ap[6]), .QN(), .SE(dftIn), + .SI(registers_20__ap[6]) + ); + SDFF_X1_LVT \registers_reg[21][6] ( + .CK(n_0_51), .D(registers[6]), .Q(registers_21__ap[6]), .QN(), .SE(dftIn), + .SI(registers_22__ap[6]) + ); + AOI22_X1_LVT i_1_0_813( + .A1(registers_22__ap[6]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[6]), + .ZN(n_1_0_774) + ); + SDFF_X1_LVT \registers_reg[24][6] ( + .CK(n_0_54), .D(registers[6]), .Q(registers_24__ap[6]), .QN(), .SE(dftIn), + .SI(registers_30__ap[6]) + ); + SDFF_X1_LVT \registers_reg[12][6] ( + .CK(n_0_42), .D(registers[6]), .Q(registers_12__ap[6]), .QN(), .SE(dftIn), + .SI(registers_16__ap[6]) + ); + AOI22_X1_LVT i_1_0_812( + .A1(registers_24__ap[6]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[6]), + .ZN(n_1_0_773) + ); + NAND4_X1_LVT i_1_0_811( + .A1(n_1_0_776), .A2(n_1_0_775), .A3(n_1_0_774), .A4(n_1_0_773), .ZN(n_1_0_772) + ); + SDFF_X1_LVT \registers_reg[13][6] ( + .CK(n_0_43), .D(registers[6]), .Q(registers_13__ap[6]), .QN(), .SE(dftIn), + .SI(registers_12__ap[6]) + ); + SDFF_X1_LVT \registers_reg[25][6] ( + .CK(n_0_55), .D(registers[6]), .Q(registers_25__ap[6]), .QN(), .SE(dftIn), + .SI(registers_24__ap[6]) + ); + AOI22_X1_LVT i_1_0_810( + .A1(registers_13__ap[6]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[6]), + .ZN(n_1_0_771) + ); + SDFF_X1_LVT \registers_reg[7][6] ( + .CK(n_0_37), .D(registers[6]), .Q(registers_7__ap[6]), .QN(), .SE(dftIn), + .SI(registers_4__ap[6]) + ); + SDFF_X1_LVT \registers_reg[14][6] ( + .CK(n_0_44), .D(registers[6]), .Q(registers_14__ap[6]), .QN(), .SE(dftIn), + .SI(registers_13__ap[6]) + ); + AOI22_X1_LVT i_1_0_809( + .A1(registers_7__ap[6]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[6]), + .ZN(n_1_0_770) + ); + SDFF_X1_LVT \registers_reg[19][6] ( + .CK(n_0_49), .D(registers[6]), .Q(registers_19__ap[6]), .QN(), .SE(dftIn), + .SI(registers_21__ap[6]) + ); + SDFF_X1_LVT \registers_reg[3][6] ( + .CK(n_0_33), .D(registers[6]), .Q(registers_3__ap[6]), .QN(), .SE(dftIn), + .SI(registers_7__ap[6]) + ); + AOI22_X1_LVT i_1_0_808( + .A1(registers_19__ap[6]), .A2(n_1_0_1295), .B1(n_1_0_1257), .B2(registers_3__ap[6]), + .ZN(n_1_0_769) + ); + SDFF_X1_LVT \registers_reg[2][6] ( + .CK(n_0_32), .D(registers[6]), .Q(registers_2__ap[6]), .QN(), .SE(dftIn), + .SI(registers_25__ap[6]) + ); + SDFF_X1_LVT \registers_reg[23][6] ( + .CK(n_0_53), .D(registers[6]), .Q(registers_23__ap[6]), .QN(), .SE(dftIn), + .SI(registers_19__ap[6]) + ); + AOI22_X1_LVT i_1_0_807( + .A1(registers_2__ap[6]), .A2(n_1_0_1268), .B1(n_1_0_1264), .B2(registers_23__ap[6]), + .ZN(n_1_0_768) + ); + NAND4_X1_LVT i_1_0_806( + .A1(n_1_0_771), .A2(n_1_0_770), .A3(n_1_0_769), .A4(n_1_0_768), .ZN(n_1_0_767) + ); + NOR3_X1_LVT i_1_0_805( + .A1(n_1_0_777), .A2(n_1_0_772), .A3(n_1_0_767), .ZN(n_1_0_766) + ); + NAND4_X1_LVT i_1_0_804( + .A1(n_1_0_784), .A2(n_1_0_783), .A3(n_1_0_782), .A4(n_1_0_766), .ZN(RRs1[6]) + ); + AND2_X1_LVT i_0_0_5( + .A1(n_0_0_16), .A2(WRd[5]), .ZN(registers[5]) + ); + SDFF_X1_LVT \registers_reg[28][5] ( + .CK(n_0_58), .D(registers[5]), .Q(registers_28__ap[5]), .QN(), .SE(dftIn), + .SI(registers_2__ap[6]) + ); + SDFF_X1_LVT \registers_reg[4][5] ( + .CK(n_0_34), .D(registers[5]), .Q(registers_4__ap[5]), .QN(), .SE(dftIn), + .SI(registers_3__ap[6]) + ); + AOI22_X1_LVT i_1_0_803( + .A1(registers_28__ap[5]), .A2(n_1_0_1283), .B1(n_1_0_1278), .B2(registers_4__ap[5]), + .ZN(n_1_0_765) + ); + SDFF_X1_LVT \registers_reg[10][5] ( + .CK(n_0_40), .D(registers[5]), .Q(registers_10__ap[5]), .QN(), .SE(dftIn), + .SI(registers_14__ap[6]) + ); + SDFF_X1_LVT \registers_reg[26][5] ( + .CK(n_0_56), .D(registers[5]), .Q(registers_26__ap[5]), .QN(), .SE(dftIn), + .SI(registers_28__ap[5]) + ); + SDFF_X1_LVT \registers_reg[8][5] ( + .CK(n_0_38), .D(registers[5]), .Q(registers_8__ap[5]), .QN(), .SE(dftIn), + .SI(registers_4__ap[5]) + ); + AOI222_X1_LVT i_1_0_802( + .A1(registers_10__ap[5]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[5]), + .C1(registers_8__ap[5]), .C2(n_1_0_1282), .ZN(n_1_0_764) + ); + SDFF_X1_LVT \registers_reg[9][5] ( + .CK(n_0_39), .D(registers[5]), .Q(registers_9__ap[5]), .QN(), .SE(dftIn), + .SI(registers_8__ap[5]) + ); + SDFF_X1_LVT \registers_reg[29][5] ( + .CK(n_0_59), .D(registers[5]), .Q(registers_29__ap[5]), .QN(), .SE(dftIn), + .SI(registers_26__ap[5]) + ); + AOI22_X1_LVT i_1_0_801( + .A1(registers_9__ap[5]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[5]), + .ZN(n_1_0_763) + ); + SDFF_X1_LVT \registers_reg[6][5] ( + .CK(n_0_36), .D(registers[5]), .Q(registers_6__ap[5]), .QN(), .SE(dftIn), + .SI(registers_9__ap[5]) + ); + SDFF_X1_LVT \registers_reg[1][5] ( + .CK(n_0_0), .D(registers[5]), .Q(registers_1__ap[5]), .QN(), .SE(dftIn), + .SI(registers_23__ap[6]) + ); + AOI22_X1_LVT i_1_0_800( + .A1(registers_6__ap[5]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[5]), + .ZN(n_1_0_762) + ); + SDFF_X1_LVT \registers_reg[16][5] ( + .CK(n_0_46), .D(registers[5]), .Q(registers_16__ap[5]), .QN(), .SE(dftIn), + .SI(registers_10__ap[5]) + ); + SDFF_X1_LVT \registers_reg[3][5] ( + .CK(n_0_33), .D(registers[5]), .Q(registers_3__ap[5]), .QN(), .SE(dftIn), + .SI(registers_6__ap[5]) + ); + AOI22_X1_LVT i_1_0_799( + .A1(registers_16__ap[5]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[5]), + .ZN(n_1_0_761) + ); + SDFF_X1_LVT \registers_reg[5][5] ( + .CK(n_0_35), .D(registers[5]), .Q(registers_5__ap[5]), .QN(), .SE(dftIn), + .SI(registers_3__ap[5]) + ); + SDFF_X1_LVT \registers_reg[31][5] ( + .CK(n_0_61), .D(registers[5]), .Q(registers_31__ap[5]), .QN(), .SE(dftIn), + .SI(registers_5__ap[5]) + ); + AOI22_X1_LVT i_1_0_798( + .A1(registers_5__ap[5]), .A2(n_1_0_1273), .B1(n_1_0_1266), .B2(registers_31__ap[5]), + .ZN(n_1_0_760) + ); + SDFF_X1_LVT \registers_reg[15][5] ( + .CK(n_0_45), .D(registers[5]), .Q(registers_15__ap[5]), .QN(), .SE(dftIn), + .SI(registers_16__ap[5]) + ); + SDFF_X1_LVT \registers_reg[23][5] ( + .CK(n_0_53), .D(registers[5]), .Q(registers_23__ap[5]), .QN(), .SE(dftIn), + .SI(registers_1__ap[5]) + ); + AOI22_X1_LVT i_1_0_797( + .A1(registers_15__ap[5]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[5]), + .ZN(n_1_0_759) + ); + NAND4_X1_LVT i_1_0_796( + .A1(n_1_0_762), .A2(n_1_0_761), .A3(n_1_0_760), .A4(n_1_0_759), .ZN(n_1_0_758) + ); + SDFF_X1_LVT \registers_reg[18][5] ( + .CK(n_0_48), .D(registers[5]), .Q(registers_18__ap[5]), .QN(), .SE(dftIn), + .SI(registers_23__ap[5]) + ); + SDFF_X1_LVT \registers_reg[30][5] ( + .CK(n_0_60), .D(registers[5]), .Q(registers_30__ap[5]), .QN(), .SE(dftIn), + .SI(registers_29__ap[5]) + ); + AOI22_X1_LVT i_1_0_795( + .A1(registers_18__ap[5]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[5]), + .ZN(n_1_0_757) + ); + SDFF_X1_LVT \registers_reg[24][5] ( + .CK(n_0_54), .D(registers[5]), .Q(registers_24__ap[5]), .QN(), .SE(dftIn), + .SI(registers_30__ap[5]) + ); + SDFF_X1_LVT \registers_reg[12][5] ( + .CK(n_0_42), .D(registers[5]), .Q(registers_12__ap[5]), .QN(), .SE(dftIn), + .SI(registers_15__ap[5]) + ); + AOI22_X1_LVT i_1_0_794( + .A1(registers_24__ap[5]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[5]), + .ZN(n_1_0_756) + ); + SDFF_X1_LVT \registers_reg[22][5] ( + .CK(n_0_52), .D(registers[5]), .Q(registers_22__ap[5]), .QN(), .SE(dftIn), + .SI(registers_18__ap[5]) + ); + SDFF_X1_LVT \registers_reg[21][5] ( + .CK(n_0_51), .D(registers[5]), .Q(registers_21__ap[5]), .QN(), .SE(dftIn), + .SI(registers_22__ap[5]) + ); + AOI22_X1_LVT i_1_0_793( + .A1(registers_22__ap[5]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[5]), + .ZN(n_1_0_755) + ); + SDFF_X1_LVT \registers_reg[20][5] ( + .CK(n_0_50), .D(registers[5]), .Q(registers_20__ap[5]), .QN(), .SE(dftIn), + .SI(registers_21__ap[5]) + ); + SDFF_X1_LVT \registers_reg[17][5] ( + .CK(n_0_47), .D(registers[5]), .Q(registers_17__ap[5]), .QN(), .SE(dftIn), + .SI(registers_20__ap[5]) + ); + AOI22_X1_LVT i_1_0_792( + .A1(registers_20__ap[5]), .A2(n_1_0_1281), .B1(n_1_0_1271), .B2(registers_17__ap[5]), + .ZN(n_1_0_754) + ); + NAND4_X1_LVT i_1_0_791( + .A1(n_1_0_757), .A2(n_1_0_756), .A3(n_1_0_755), .A4(n_1_0_754), .ZN(n_1_0_753) + ); + SDFF_X1_LVT \registers_reg[13][5] ( + .CK(n_0_43), .D(registers[5]), .Q(registers_13__ap[5]), .QN(), .SE(dftIn), + .SI(registers_12__ap[5]) + ); + SDFF_X1_LVT \registers_reg[25][5] ( + .CK(n_0_55), .D(registers[5]), .Q(registers_25__ap[5]), .QN(), .SE(dftIn), + .SI(registers_24__ap[5]) + ); + AOI22_X1_LVT i_1_0_790( + .A1(registers_13__ap[5]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[5]), + .ZN(n_1_0_752) + ); + SDFF_X1_LVT \registers_reg[19][5] ( + .CK(n_0_49), .D(registers[5]), .Q(registers_19__ap[5]), .QN(), .SE(dftIn), + .SI(registers_17__ap[5]) + ); + SDFF_X1_LVT \registers_reg[2][5] ( + .CK(n_0_32), .D(registers[5]), .Q(registers_2__ap[5]), .QN(), .SE(dftIn), + .SI(registers_25__ap[5]) + ); + AOI22_X1_LVT i_1_0_789( + .A1(registers_19__ap[5]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[5]), + .ZN(n_1_0_751) + ); + SDFF_X1_LVT \registers_reg[7][5] ( + .CK(n_0_37), .D(registers[5]), .Q(registers_7__ap[5]), .QN(), .SE(dftIn), + .SI(registers_31__ap[5]) + ); + SDFF_X1_LVT \registers_reg[14][5] ( + .CK(n_0_44), .D(registers[5]), .Q(registers_14__ap[5]), .QN(), .SE(dftIn), + .SI(registers_13__ap[5]) + ); + AOI22_X1_LVT i_1_0_788( + .A1(registers_7__ap[5]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[5]), + .ZN(n_1_0_750) + ); + SDFF_X1_LVT \registers_reg[27][5] ( + .CK(n_0_57), .D(registers[5]), .Q(registers_27__ap[5]), .QN(), .SE(dftIn), + .SI(registers_2__ap[5]) + ); + SDFF_X1_LVT \registers_reg[11][5] ( + .CK(n_0_41), .D(registers[5]), .Q(registers_11__ap[5]), .QN(), .SE(dftIn), + .SI(registers_14__ap[5]) + ); + AOI22_X1_LVT i_1_0_787( + .A1(registers_27__ap[5]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[5]), + .ZN(n_1_0_749) + ); + NAND4_X1_LVT i_1_0_786( + .A1(n_1_0_752), .A2(n_1_0_751), .A3(n_1_0_750), .A4(n_1_0_749), .ZN(n_1_0_748) + ); + NOR3_X1_LVT i_1_0_785( + .A1(n_1_0_758), .A2(n_1_0_753), .A3(n_1_0_748), .ZN(n_1_0_747) + ); + NAND4_X1_LVT i_1_0_784( + .A1(n_1_0_765), .A2(n_1_0_764), .A3(n_1_0_763), .A4(n_1_0_747), .ZN(RRs1[5]) + ); + AND2_X1_LVT i_0_0_4( + .A1(n_0_0_16), .A2(WRd[4]), .ZN(registers[4]) + ); + SDFF_X1_LVT \registers_reg[10][4] ( + .CK(n_0_40), .D(registers[4]), .Q(registers_10__ap[4]), .QN(), .SE(dftIn), + .SI(registers_11__ap[5]) + ); + SDFF_X1_LVT \registers_reg[21][4] ( + .CK(n_0_51), .D(registers[4]), .Q(registers_21__ap[4]), .QN(), .SE(dftIn), + .SI(registers_19__ap[5]) + ); + AOI22_X1_LVT i_1_0_783( + .A1(registers_10__ap[4]), .A2(n_1_0_1287), .B1(n_1_0_1259), .B2(registers_21__ap[4]), + .ZN(n_1_0_746) + ); + SDFF_X1_LVT \registers_reg[9][4] ( + .CK(n_0_39), .D(registers[4]), .Q(registers_9__ap[4]), .QN(), .SE(dftIn), + .SI(registers_7__ap[5]) + ); + SDFF_X1_LVT \registers_reg[1][4] ( + .CK(n_0_0), .D(registers[4]), .Q(registers_1__ap[4]), .QN(), .SE(dftIn), + .SI(registers_21__ap[4]) + ); + AOI22_X1_LVT i_1_0_778( + .A1(registers_9__ap[4]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[4]), + .ZN(n_1_0_741) + ); + SDFF_X1_LVT \registers_reg[18][4] ( + .CK(n_0_48), .D(registers[4]), .Q(registers_18__ap[4]), .QN(), .SE(dftIn), + .SI(registers_1__ap[4]) + ); + SDFF_X1_LVT \registers_reg[8][4] ( + .CK(n_0_38), .D(registers[4]), .Q(registers_8__ap[4]), .QN(), .SE(dftIn), + .SI(registers_9__ap[4]) + ); + AOI22_X1_LVT i_1_0_777( + .A1(registers_18__ap[4]), .A2(n_1_0_1297), .B1(n_1_0_1282), .B2(registers_8__ap[4]), + .ZN(n_1_0_740) + ); + NAND3_X1_LVT i_1_0_775( + .A1(n_1_0_746), .A2(n_1_0_741), .A3(n_1_0_740), .ZN(n_1_0_738) + ); + SDFF_X1_LVT \registers_reg[22][4] ( + .CK(n_0_52), .D(registers[4]), .Q(registers_22__ap[4]), .QN(), .SE(dftIn), + .SI(registers_18__ap[4]) + ); + SDFF_X1_LVT \registers_reg[23][4] ( + .CK(n_0_53), .D(registers[4]), .Q(registers_23__ap[4]), .QN(), .SE(dftIn), + .SI(registers_22__ap[4]) + ); + AOI221_X1_LVT i_1_0_774( + .A(n_1_0_738), .B1(n_1_0_1294), .B2(registers_22__ap[4]), .C1(registers_23__ap[4]), + .C2(n_1_0_1264), .ZN(n_1_0_737) + ); + SDFF_X1_LVT \registers_reg[28][4] ( + .CK(n_0_58), .D(registers[4]), .Q(registers_28__ap[4]), .QN(), .SE(dftIn), + .SI(registers_27__ap[5]) + ); + SDFF_X1_LVT \registers_reg[20][4] ( + .CK(n_0_50), .D(registers[4]), .Q(registers_20__ap[4]), .QN(), .SE(dftIn), + .SI(registers_23__ap[4]) + ); + AOI22_X1_LVT i_1_0_782( + .A1(registers_28__ap[4]), .A2(n_1_0_1283), .B1(n_1_0_1281), .B2(registers_20__ap[4]), + .ZN(n_1_0_745) + ); + SDFF_X1_LVT \registers_reg[19][4] ( + .CK(n_0_49), .D(registers[4]), .Q(registers_19__ap[4]), .QN(), .SE(dftIn), + .SI(registers_20__ap[4]) + ); + SDFF_X1_LVT \registers_reg[13][4] ( + .CK(n_0_43), .D(registers[4]), .Q(registers_13__ap[4]), .QN(), .SE(dftIn), + .SI(registers_10__ap[4]) + ); + AOI22_X1_LVT i_1_0_780( + .A1(registers_19__ap[4]), .A2(n_1_0_1295), .B1(n_1_0_1277), .B2(registers_13__ap[4]), + .ZN(n_1_0_743) + ); + SDFF_X1_LVT \registers_reg[26][4] ( + .CK(n_0_56), .D(registers[4]), .Q(registers_26__ap[4]), .QN(), .SE(dftIn), + .SI(registers_28__ap[4]) + ); + SDFF_X1_LVT \registers_reg[3][4] ( + .CK(n_0_33), .D(registers[4]), .Q(registers_3__ap[4]), .QN(), .SE(dftIn), + .SI(registers_8__ap[4]) + ); + AOI22_X1_LVT i_1_0_776( + .A1(registers_26__ap[4]), .A2(n_1_0_1285), .B1(n_1_0_1257), .B2(registers_3__ap[4]), + .ZN(n_1_0_739) + ); + NAND3_X1_LVT i_1_0_773( + .A1(n_1_0_745), .A2(n_1_0_743), .A3(n_1_0_739), .ZN(n_1_0_736) + ); + SDFF_X1_LVT \registers_reg[30][4] ( + .CK(n_0_60), .D(registers[4]), .Q(registers_30__ap[4]), .QN(), .SE(dftIn), + .SI(registers_26__ap[4]) + ); + SDFF_X1_LVT \registers_reg[31][4] ( + .CK(n_0_61), .D(registers[4]), .Q(registers_31__ap[4]), .QN(), .SE(dftIn), + .SI(registers_3__ap[4]) + ); + AOI221_X1_LVT i_1_0_772( + .A(n_1_0_736), .B1(n_1_0_1272), .B2(registers_30__ap[4]), .C1(registers_31__ap[4]), + .C2(n_1_0_1266), .ZN(n_1_0_735) + ); + SDFF_X1_LVT \registers_reg[24][4] ( + .CK(n_0_54), .D(registers[4]), .Q(registers_24__ap[4]), .QN(), .SE(dftIn), + .SI(registers_30__ap[4]) + ); + SDFF_X1_LVT \registers_reg[12][4] ( + .CK(n_0_42), .D(registers[4]), .Q(registers_12__ap[4]), .QN(), .SE(dftIn), + .SI(registers_13__ap[4]) + ); + AOI22_X1_LVT i_1_0_781( + .A1(registers_24__ap[4]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[4]), + .ZN(n_1_0_744) + ); + SDFF_X1_LVT \registers_reg[27][4] ( + .CK(n_0_57), .D(registers[4]), .Q(registers_27__ap[4]), .QN(), .SE(dftIn), + .SI(registers_24__ap[4]) + ); + SDFF_X1_LVT \registers_reg[11][4] ( + .CK(n_0_41), .D(registers[4]), .Q(registers_11__ap[4]), .QN(), .SE(dftIn), + .SI(registers_12__ap[4]) + ); + AOI22_X1_LVT i_1_0_779( + .A1(registers_27__ap[4]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[4]), + .ZN(n_1_0_742) + ); + SDFF_X1_LVT \registers_reg[17][4] ( + .CK(n_0_47), .D(registers[4]), .Q(registers_17__ap[4]), .QN(), .SE(dftIn), + .SI(registers_19__ap[4]) + ); + SDFF_X1_LVT \registers_reg[7][4] ( + .CK(n_0_37), .D(registers[4]), .Q(registers_7__ap[4]), .QN(), .SE(dftIn), + .SI(registers_31__ap[4]) + ); + SDFF_X1_LVT \registers_reg[14][4] ( + .CK(n_0_44), .D(registers[4]), .Q(registers_14__ap[4]), .QN(), .SE(dftIn), + .SI(registers_11__ap[4]) + ); + AOI222_X1_LVT i_1_0_771( + .A1(registers_17__ap[4]), .A2(n_1_0_1271), .B1(n_1_0_1263), .B2(registers_7__ap[4]), + .C1(n_1_0_1258), .C2(registers_14__ap[4]), .ZN(n_1_0_734) + ); + SDFF_X1_LVT \registers_reg[15][4] ( + .CK(n_0_45), .D(registers[4]), .Q(registers_15__ap[4]), .QN(), .SE(dftIn), + .SI(registers_14__ap[4]) + ); + SDFF_X1_LVT \registers_reg[16][4] ( + .CK(n_0_46), .D(registers[4]), .Q(registers_16__ap[4]), .QN(), .SE(dftIn), + .SI(registers_15__ap[4]) + ); + AOI22_X1_LVT i_1_0_770( + .A1(registers_15__ap[4]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[4]), + .ZN(n_1_0_733) + ); + SDFF_X1_LVT \registers_reg[4][4] ( + .CK(n_0_34), .D(registers[4]), .Q(registers_4__ap[4]), .QN(), .SE(dftIn), + .SI(registers_7__ap[4]) + ); + SDFF_X1_LVT \registers_reg[25][4] ( + .CK(n_0_55), .D(registers[4]), .Q(registers_25__ap[4]), .QN(), .SE(dftIn), + .SI(registers_27__ap[4]) + ); + AOI22_X1_LVT i_1_0_769( + .A1(registers_4__ap[4]), .A2(n_1_0_1278), .B1(n_1_0_1269), .B2(registers_25__ap[4]), + .ZN(n_1_0_732) + ); + SDFF_X1_LVT \registers_reg[29][4] ( + .CK(n_0_59), .D(registers[4]), .Q(registers_29__ap[4]), .QN(), .SE(dftIn), + .SI(registers_25__ap[4]) + ); + SDFF_X1_LVT \registers_reg[2][4] ( + .CK(n_0_32), .D(registers[4]), .Q(registers_2__ap[4]), .QN(), .SE(dftIn), + .SI(registers_29__ap[4]) + ); + AOI22_X1_LVT i_1_0_768( + .A1(registers_29__ap[4]), .A2(n_1_0_1276), .B1(n_1_0_1268), .B2(registers_2__ap[4]), + .ZN(n_1_0_731) + ); + NAND3_X1_LVT i_1_0_767( + .A1(n_1_0_733), .A2(n_1_0_732), .A3(n_1_0_731), .ZN(n_1_0_730) + ); + SDFF_X1_LVT \registers_reg[6][4] ( + .CK(n_0_36), .D(registers[4]), .Q(registers_6__ap[4]), .QN(), .SE(dftIn), + .SI(registers_4__ap[4]) + ); + SDFF_X1_LVT \registers_reg[5][4] ( + .CK(n_0_35), .D(registers[4]), .Q(registers_5__ap[4]), .QN(), .SE(dftIn), + .SI(registers_6__ap[4]) + ); + AOI221_X1_LVT i_1_0_766( + .A(n_1_0_730), .B1(n_1_0_1300), .B2(registers_6__ap[4]), .C1(registers_5__ap[4]), + .C2(n_1_0_1273), .ZN(n_1_0_729) + ); + AND4_X1_LVT i_1_0_765( + .A1(n_1_0_744), .A2(n_1_0_742), .A3(n_1_0_734), .A4(n_1_0_729), .ZN(n_1_0_728) + ); + NAND3_X1_LVT i_1_0_764( + .A1(n_1_0_737), .A2(n_1_0_735), .A3(n_1_0_728), .ZN(RRs1[4]) + ); + AND2_X1_LVT i_0_0_3( + .A1(n_0_0_16), .A2(WRd[3]), .ZN(registers[3]) + ); + SDFF_X1_LVT \registers_reg[28][3] ( + .CK(n_0_58), .D(registers[3]), .Q(registers_28__ap[3]), .QN(), .SE(dftIn), + .SI(registers_2__ap[4]) + ); + SDFF_X1_LVT \registers_reg[17][3] ( + .CK(n_0_47), .D(registers[3]), .Q(registers_17__ap[3]), .QN(), .SE(dftIn), + .SI(registers_17__ap[4]) + ); + AOI22_X1_LVT i_1_0_763( + .A1(registers_28__ap[3]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[3]), + .ZN(n_1_0_727) + ); + SDFF_X1_LVT \registers_reg[10][3] ( + .CK(n_0_40), .D(registers[3]), .Q(registers_10__ap[3]), .QN(), .SE(dftIn), + .SI(registers_16__ap[4]) + ); + SDFF_X1_LVT \registers_reg[26][3] ( + .CK(n_0_56), .D(registers[3]), .Q(registers_26__ap[3]), .QN(), .SE(dftIn), + .SI(registers_28__ap[3]) + ); + SDFF_X1_LVT \registers_reg[8][3] ( + .CK(n_0_38), .D(registers[3]), .Q(registers_8__ap[3]), .QN(), .SE(dftIn), + .SI(registers_5__ap[4]) + ); + AOI222_X1_LVT i_1_0_762( + .A1(registers_10__ap[3]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[3]), + .C1(registers_8__ap[3]), .C2(n_1_0_1282), .ZN(n_1_0_726) + ); + SDFF_X1_LVT \registers_reg[9][3] ( + .CK(n_0_39), .D(registers[3]), .Q(registers_9__ap[3]), .QN(), .SE(dftIn), + .SI(registers_8__ap[3]) + ); + SDFF_X1_LVT \registers_reg[29][3] ( + .CK(n_0_59), .D(registers[3]), .Q(registers_29__ap[3]), .QN(), .SE(dftIn), + .SI(registers_26__ap[3]) + ); + AOI22_X1_LVT i_1_0_761( + .A1(registers_9__ap[3]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[3]), + .ZN(n_1_0_725) + ); + SDFF_X1_LVT \registers_reg[6][3] ( + .CK(n_0_36), .D(registers[3]), .Q(registers_6__ap[3]), .QN(), .SE(dftIn), + .SI(registers_9__ap[3]) + ); + SDFF_X1_LVT \registers_reg[1][3] ( + .CK(n_0_0), .D(registers[3]), .Q(registers_1__ap[3]), .QN(), .SE(dftIn), + .SI(registers_17__ap[3]) + ); + AOI22_X1_LVT i_1_0_760( + .A1(registers_6__ap[3]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[3]), + .ZN(n_1_0_724) + ); + SDFF_X1_LVT \registers_reg[16][3] ( + .CK(n_0_46), .D(registers[3]), .Q(registers_16__ap[3]), .QN(), .SE(dftIn), + .SI(registers_10__ap[3]) + ); + SDFF_X1_LVT \registers_reg[3][3] ( + .CK(n_0_33), .D(registers[3]), .Q(registers_3__ap[3]), .QN(), .SE(dftIn), + .SI(registers_6__ap[3]) + ); + AOI22_X1_LVT i_1_0_759( + .A1(registers_16__ap[3]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[3]), + .ZN(n_1_0_723) + ); + SDFF_X1_LVT \registers_reg[5][3] ( + .CK(n_0_35), .D(registers[3]), .Q(registers_5__ap[3]), .QN(), .SE(dftIn), + .SI(registers_3__ap[3]) + ); + SDFF_X1_LVT \registers_reg[31][3] ( + .CK(n_0_61), .D(registers[3]), .Q(registers_31__ap[3]), .QN(), .SE(dftIn), + .SI(registers_5__ap[3]) + ); + AOI22_X1_LVT i_1_0_758( + .A1(registers_5__ap[3]), .A2(n_1_0_1273), .B1(n_1_0_1266), .B2(registers_31__ap[3]), + .ZN(n_1_0_722) + ); + SDFF_X1_LVT \registers_reg[15][3] ( + .CK(n_0_45), .D(registers[3]), .Q(registers_15__ap[3]), .QN(), .SE(dftIn), + .SI(registers_16__ap[3]) + ); + SDFF_X1_LVT \registers_reg[23][3] ( + .CK(n_0_53), .D(registers[3]), .Q(registers_23__ap[3]), .QN(), .SE(dftIn), + .SI(registers_1__ap[3]) + ); + AOI22_X1_LVT i_1_0_757( + .A1(registers_15__ap[3]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[3]), + .ZN(n_1_0_721) + ); + NAND4_X1_LVT i_1_0_756( + .A1(n_1_0_724), .A2(n_1_0_723), .A3(n_1_0_722), .A4(n_1_0_721), .ZN(n_1_0_720) + ); + SDFF_X1_LVT \registers_reg[18][3] ( + .CK(n_0_48), .D(registers[3]), .Q(registers_18__ap[3]), .QN(), .SE(dftIn), + .SI(registers_23__ap[3]) + ); + SDFF_X1_LVT \registers_reg[30][3] ( + .CK(n_0_60), .D(registers[3]), .Q(registers_30__ap[3]), .QN(), .SE(dftIn), + .SI(registers_29__ap[3]) + ); + AOI22_X1_LVT i_1_0_755( + .A1(registers_18__ap[3]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[3]), + .ZN(n_1_0_719) + ); + SDFF_X1_LVT \registers_reg[20][3] ( + .CK(n_0_50), .D(registers[3]), .Q(registers_20__ap[3]), .QN(), .SE(dftIn), + .SI(registers_18__ap[3]) + ); + SDFF_X1_LVT \registers_reg[4][3] ( + .CK(n_0_34), .D(registers[3]), .Q(registers_4__ap[3]), .QN(), .SE(dftIn), + .SI(registers_31__ap[3]) + ); + AOI22_X1_LVT i_1_0_754( + .A1(registers_20__ap[3]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[3]), + .ZN(n_1_0_718) + ); + SDFF_X1_LVT \registers_reg[22][3] ( + .CK(n_0_52), .D(registers[3]), .Q(registers_22__ap[3]), .QN(), .SE(dftIn), + .SI(registers_20__ap[3]) + ); + SDFF_X1_LVT \registers_reg[21][3] ( + .CK(n_0_51), .D(registers[3]), .Q(registers_21__ap[3]), .QN(), .SE(dftIn), + .SI(registers_22__ap[3]) + ); + AOI22_X1_LVT i_1_0_753( + .A1(registers_22__ap[3]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[3]), + .ZN(n_1_0_717) + ); + SDFF_X1_LVT \registers_reg[24][3] ( + .CK(n_0_54), .D(registers[3]), .Q(registers_24__ap[3]), .QN(), .SE(dftIn), + .SI(registers_30__ap[3]) + ); + SDFF_X1_LVT \registers_reg[12][3] ( + .CK(n_0_42), .D(registers[3]), .Q(registers_12__ap[3]), .QN(), .SE(dftIn), + .SI(registers_15__ap[3]) + ); + AOI22_X1_LVT i_1_0_752( + .A1(registers_24__ap[3]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[3]), + .ZN(n_1_0_716) + ); + NAND4_X1_LVT i_1_0_751( + .A1(n_1_0_719), .A2(n_1_0_718), .A3(n_1_0_717), .A4(n_1_0_716), .ZN(n_1_0_715) + ); + SDFF_X1_LVT \registers_reg[13][3] ( + .CK(n_0_43), .D(registers[3]), .Q(registers_13__ap[3]), .QN(), .SE(dftIn), + .SI(registers_12__ap[3]) + ); + SDFF_X1_LVT \registers_reg[25][3] ( + .CK(n_0_55), .D(registers[3]), .Q(registers_25__ap[3]), .QN(), .SE(dftIn), + .SI(registers_24__ap[3]) + ); + AOI22_X1_LVT i_1_0_750( + .A1(registers_13__ap[3]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[3]), + .ZN(n_1_0_714) + ); + SDFF_X1_LVT \registers_reg[19][3] ( + .CK(n_0_49), .D(registers[3]), .Q(registers_19__ap[3]), .QN(), .SE(dftIn), + .SI(registers_21__ap[3]) + ); + SDFF_X1_LVT \registers_reg[2][3] ( + .CK(n_0_32), .D(registers[3]), .Q(registers_2__ap[3]), .QN(), .SE(dftIn), + .SI(registers_25__ap[3]) + ); + AOI22_X1_LVT i_1_0_749( + .A1(registers_19__ap[3]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[3]), + .ZN(n_1_0_713) + ); + SDFF_X1_LVT \registers_reg[7][3] ( + .CK(n_0_37), .D(registers[3]), .Q(registers_7__ap[3]), .QN(), .SE(dftIn), + .SI(registers_4__ap[3]) + ); + SDFF_X1_LVT \registers_reg[14][3] ( + .CK(n_0_44), .D(registers[3]), .Q(registers_14__ap[3]), .QN(), .SE(dftIn), + .SI(registers_13__ap[3]) + ); + AOI22_X1_LVT i_1_0_748( + .A1(registers_7__ap[3]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[3]), + .ZN(n_1_0_712) + ); + SDFF_X1_LVT \registers_reg[27][3] ( + .CK(n_0_57), .D(registers[3]), .Q(registers_27__ap[3]), .QN(), .SE(dftIn), + .SI(registers_2__ap[3]) + ); + SDFF_X1_LVT \registers_reg[11][3] ( + .CK(n_0_41), .D(registers[3]), .Q(registers_11__ap[3]), .QN(), .SE(dftIn), + .SI(registers_14__ap[3]) + ); + AOI22_X1_LVT i_1_0_747( + .A1(registers_27__ap[3]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[3]), + .ZN(n_1_0_711) + ); + NAND4_X1_LVT i_1_0_746( + .A1(n_1_0_714), .A2(n_1_0_713), .A3(n_1_0_712), .A4(n_1_0_711), .ZN(n_1_0_710) + ); + NOR3_X1_LVT i_1_0_745( + .A1(n_1_0_720), .A2(n_1_0_715), .A3(n_1_0_710), .ZN(n_1_0_709) + ); + NAND4_X1_LVT i_1_0_744( + .A1(n_1_0_727), .A2(n_1_0_726), .A3(n_1_0_725), .A4(n_1_0_709), .ZN(RRs1[3]) + ); + AND2_X1_LVT i_0_0_2( + .A1(n_0_0_16), .A2(WRd[2]), .ZN(registers[2]) + ); + SDFF_X1_LVT \registers_reg[28][2] ( + .CK(n_0_58), .D(registers[2]), .Q(registers_28__ap[2]), .QN(), .SE(dftIn), + .SI(registers_27__ap[3]) + ); + SDFF_X1_LVT \registers_reg[4][2] ( + .CK(n_0_34), .D(registers[2]), .Q(registers_4__ap[2]), .QN(), .SE(dftIn), + .SI(registers_7__ap[3]) + ); + AOI22_X1_LVT i_1_0_740( + .A1(registers_28__ap[2]), .A2(n_1_0_1283), .B1(n_1_0_1278), .B2(registers_4__ap[2]), + .ZN(n_1_0_705) + ); + SDFF_X1_LVT \registers_reg[16][2] ( + .CK(n_0_46), .D(registers[2]), .Q(registers_16__ap[2]), .QN(), .SE(dftIn), + .SI(registers_11__ap[3]) + ); + SDFF_X1_LVT \registers_reg[31][2] ( + .CK(n_0_61), .D(registers[2]), .Q(registers_31__ap[2]), .QN(), .SE(dftIn), + .SI(registers_4__ap[2]) + ); + AOI22_X1_LVT i_1_0_743( + .A1(registers_16__ap[2]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[2]), + .ZN(n_1_0_708) + ); + SDFF_X1_LVT \registers_reg[6][2] ( + .CK(n_0_36), .D(registers[2]), .Q(registers_6__ap[2]), .QN(), .SE(dftIn), + .SI(registers_31__ap[2]) + ); + SDFF_X1_LVT \registers_reg[1][2] ( + .CK(n_0_0), .D(registers[2]), .Q(registers_1__ap[2]), .QN(), .SE(dftIn), + .SI(registers_19__ap[3]) + ); + AOI22_X1_LVT i_1_0_739( + .A1(registers_6__ap[2]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[2]), + .ZN(n_1_0_704) + ); + SDFF_X1_LVT \registers_reg[15][2] ( + .CK(n_0_45), .D(registers[2]), .Q(registers_15__ap[2]), .QN(), .SE(dftIn), + .SI(registers_16__ap[2]) + ); + SDFF_X1_LVT \registers_reg[27][2] ( + .CK(n_0_57), .D(registers[2]), .Q(registers_27__ap[2]), .QN(), .SE(dftIn), + .SI(registers_28__ap[2]) + ); + AOI22_X1_LVT i_1_0_742( + .A1(registers_15__ap[2]), .A2(n_1_0_1286), .B1(n_1_0_1279), .B2(registers_27__ap[2]), + .ZN(n_1_0_707) + ); + INV_X1_LVT i_1_0_741( + .A(n_1_0_707), .ZN(n_1_0_706) + ); + SDFF_X1_LVT \registers_reg[11][2] ( + .CK(n_0_41), .D(registers[2]), .Q(registers_11__ap[2]), .QN(), .SE(dftIn), + .SI(registers_15__ap[2]) + ); + SDFF_X1_LVT \registers_reg[5][2] ( + .CK(n_0_35), .D(registers[2]), .Q(registers_5__ap[2]), .QN(), .SE(dftIn), + .SI(registers_6__ap[2]) + ); + AOI221_X1_LVT i_1_0_738( + .A(n_1_0_706), .B1(n_1_0_1270), .B2(registers_11__ap[2]), .C1(registers_5__ap[2]), + .C2(n_1_0_1273), .ZN(n_1_0_703) + ); + SDFF_X1_LVT \registers_reg[10][2] ( + .CK(n_0_40), .D(registers[2]), .Q(registers_10__ap[2]), .QN(), .SE(dftIn), + .SI(registers_11__ap[2]) + ); + SDFF_X1_LVT \registers_reg[30][2] ( + .CK(n_0_60), .D(registers[2]), .Q(registers_30__ap[2]), .QN(), .SE(dftIn), + .SI(registers_27__ap[2]) + ); + SDFF_X1_LVT \registers_reg[8][2] ( + .CK(n_0_38), .D(registers[2]), .Q(registers_8__ap[2]), .QN(), .SE(dftIn), + .SI(registers_5__ap[2]) + ); + AOI222_X1_LVT i_1_0_737( + .A1(registers_10__ap[2]), .A2(n_1_0_1287), .B1(n_1_0_1272), .B2(registers_30__ap[2]), + .C1(n_1_0_1282), .C2(registers_8__ap[2]), .ZN(n_1_0_702) + ); + NAND4_X1_LVT i_1_0_736( + .A1(n_1_0_708), .A2(n_1_0_704), .A3(n_1_0_703), .A4(n_1_0_702), .ZN(n_1_0_701) + ); + SDFF_X1_LVT \registers_reg[9][2] ( + .CK(n_0_39), .D(registers[2]), .Q(registers_9__ap[2]), .QN(), .SE(dftIn), + .SI(registers_8__ap[2]) + ); + SDFF_X1_LVT \registers_reg[29][2] ( + .CK(n_0_59), .D(registers[2]), .Q(registers_29__ap[2]), .QN(), .SE(dftIn), + .SI(registers_30__ap[2]) + ); + AOI221_X1_LVT i_1_0_735( + .A(n_1_0_701), .B1(n_1_0_1291), .B2(registers_9__ap[2]), .C1(registers_29__ap[2]), + .C2(n_1_0_1276), .ZN(n_1_0_700) + ); + SDFF_X1_LVT \registers_reg[18][2] ( + .CK(n_0_48), .D(registers[2]), .Q(registers_18__ap[2]), .QN(), .SE(dftIn), + .SI(registers_1__ap[2]) + ); + SDFF_X1_LVT \registers_reg[26][2] ( + .CK(n_0_56), .D(registers[2]), .Q(registers_26__ap[2]), .QN(), .SE(dftIn), + .SI(registers_29__ap[2]) + ); + AOI22_X1_LVT i_1_0_734( + .A1(registers_18__ap[2]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[2]), + .ZN(n_1_0_699) + ); + SDFF_X1_LVT \registers_reg[24][2] ( + .CK(n_0_54), .D(registers[2]), .Q(registers_24__ap[2]), .QN(), .SE(dftIn), + .SI(registers_26__ap[2]) + ); + SDFF_X1_LVT \registers_reg[12][2] ( + .CK(n_0_42), .D(registers[2]), .Q(registers_12__ap[2]), .QN(), .SE(dftIn), + .SI(registers_10__ap[2]) + ); + AOI22_X1_LVT i_1_0_733( + .A1(registers_24__ap[2]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[2]), + .ZN(n_1_0_698) + ); + SDFF_X1_LVT \registers_reg[22][2] ( + .CK(n_0_52), .D(registers[2]), .Q(registers_22__ap[2]), .QN(), .SE(dftIn), + .SI(registers_18__ap[2]) + ); + SDFF_X1_LVT \registers_reg[21][2] ( + .CK(n_0_51), .D(registers[2]), .Q(registers_21__ap[2]), .QN(), .SE(dftIn), + .SI(registers_22__ap[2]) + ); + AOI22_X1_LVT i_1_0_732( + .A1(registers_22__ap[2]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[2]), + .ZN(n_1_0_697) + ); + NAND3_X1_LVT i_1_0_731( + .A1(n_1_0_699), .A2(n_1_0_698), .A3(n_1_0_697), .ZN(n_1_0_696) + ); + SDFF_X1_LVT \registers_reg[17][2] ( + .CK(n_0_47), .D(registers[2]), .Q(registers_17__ap[2]), .QN(), .SE(dftIn), + .SI(registers_21__ap[2]) + ); + SDFF_X1_LVT \registers_reg[20][2] ( + .CK(n_0_50), .D(registers[2]), .Q(registers_20__ap[2]), .QN(), .SE(dftIn), + .SI(registers_17__ap[2]) + ); + AOI221_X1_LVT i_1_0_730( + .A(n_1_0_696), .B1(n_1_0_1271), .B2(registers_17__ap[2]), .C1(registers_20__ap[2]), + .C2(n_1_0_1281), .ZN(n_1_0_695) + ); + SDFF_X1_LVT \registers_reg[13][2] ( + .CK(n_0_43), .D(registers[2]), .Q(registers_13__ap[2]), .QN(), .SE(dftIn), + .SI(registers_12__ap[2]) + ); + SDFF_X1_LVT \registers_reg[25][2] ( + .CK(n_0_55), .D(registers[2]), .Q(registers_25__ap[2]), .QN(), .SE(dftIn), + .SI(registers_24__ap[2]) + ); + AOI22_X1_LVT i_1_0_729( + .A1(registers_13__ap[2]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[2]), + .ZN(n_1_0_694) + ); + SDFF_X1_LVT \registers_reg[7][2] ( + .CK(n_0_37), .D(registers[2]), .Q(registers_7__ap[2]), .QN(), .SE(dftIn), + .SI(registers_9__ap[2]) + ); + SDFF_X1_LVT \registers_reg[14][2] ( + .CK(n_0_44), .D(registers[2]), .Q(registers_14__ap[2]), .QN(), .SE(dftIn), + .SI(registers_13__ap[2]) + ); + AOI22_X1_LVT i_1_0_728( + .A1(registers_7__ap[2]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[2]), + .ZN(n_1_0_693) + ); + SDFF_X1_LVT \registers_reg[19][2] ( + .CK(n_0_49), .D(registers[2]), .Q(registers_19__ap[2]), .QN(), .SE(dftIn), + .SI(registers_20__ap[2]) + ); + SDFF_X1_LVT \registers_reg[3][2] ( + .CK(n_0_33), .D(registers[2]), .Q(registers_3__ap[2]), .QN(), .SE(dftIn), + .SI(registers_7__ap[2]) + ); + AOI22_X1_LVT i_1_0_727( + .A1(registers_19__ap[2]), .A2(n_1_0_1295), .B1(n_1_0_1257), .B2(registers_3__ap[2]), + .ZN(n_1_0_692) + ); + NAND3_X1_LVT i_1_0_726( + .A1(n_1_0_694), .A2(n_1_0_693), .A3(n_1_0_692), .ZN(n_1_0_691) + ); + SDFF_X1_LVT \registers_reg[23][2] ( + .CK(n_0_53), .D(registers[2]), .Q(registers_23__ap[2]), .QN(), .SE(dftIn), + .SI(registers_19__ap[2]) + ); + SDFF_X1_LVT \registers_reg[2][2] ( + .CK(n_0_32), .D(registers[2]), .Q(registers_2__ap[2]), .QN(), .SE(dftIn), + .SI(registers_25__ap[2]) + ); + AOI221_X1_LVT i_1_0_725( + .A(n_1_0_691), .B1(n_1_0_1264), .B2(registers_23__ap[2]), .C1(registers_2__ap[2]), + .C2(n_1_0_1268), .ZN(n_1_0_690) + ); + NAND4_X1_LVT i_1_0_724( + .A1(n_1_0_705), .A2(n_1_0_700), .A3(n_1_0_695), .A4(n_1_0_690), .ZN(RRs1[2]) + ); + AND2_X1_LVT i_0_0_1( + .A1(n_0_0_16), .A2(WRd[1]), .ZN(registers[1]) + ); + SDFF_X1_LVT \registers_reg[13][1] ( + .CK(n_0_43), .D(registers[1]), .Q(registers_13__ap[1]), .QN(), .SE(dftIn), + .SI(registers_14__ap[2]) + ); + SDFF_X1_LVT \registers_reg[21][1] ( + .CK(n_0_51), .D(registers[1]), .Q(registers_21__ap[1]), .QN(), .SE(dftIn), + .SI(registers_23__ap[2]) + ); + AOI22_X1_LVT i_1_0_720( + .A1(registers_13__ap[1]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[1]), + .ZN(n_1_0_686) + ); + SDFF_X1_LVT \registers_reg[29][1] ( + .CK(n_0_59), .D(registers[1]), .Q(registers_29__ap[1]), .QN(), .SE(dftIn), + .SI(registers_2__ap[2]) + ); + SDFF_X1_LVT \registers_reg[23][1] ( + .CK(n_0_53), .D(registers[1]), .Q(registers_23__ap[1]), .QN(), .SE(dftIn), + .SI(registers_21__ap[1]) + ); + AOI22_X1_LVT i_1_0_723( + .A1(registers_29__ap[1]), .A2(n_1_0_1276), .B1(n_1_0_1264), .B2(registers_23__ap[1]), + .ZN(n_1_0_689) + ); + SDFF_X1_LVT \registers_reg[24][1] ( + .CK(n_0_54), .D(registers[1]), .Q(registers_24__ap[1]), .QN(), .SE(dftIn), + .SI(registers_29__ap[1]) + ); + SDFF_X1_LVT \registers_reg[20][1] ( + .CK(n_0_50), .D(registers[1]), .Q(registers_20__ap[1]), .QN(), .SE(dftIn), + .SI(registers_23__ap[1]) + ); + AOI22_X1_LVT i_1_0_719( + .A1(registers_24__ap[1]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[1]), + .ZN(n_1_0_685) + ); + SDFF_X1_LVT \registers_reg[7][1] ( + .CK(n_0_37), .D(registers[1]), .Q(registers_7__ap[1]), .QN(), .SE(dftIn), + .SI(registers_3__ap[2]) + ); + SDFF_X1_LVT \registers_reg[3][1] ( + .CK(n_0_33), .D(registers[1]), .Q(registers_3__ap[1]), .QN(), .SE(dftIn), + .SI(registers_7__ap[1]) + ); + AOI22_X1_LVT i_1_0_722( + .A1(registers_7__ap[1]), .A2(n_1_0_1263), .B1(n_1_0_1257), .B2(registers_3__ap[1]), + .ZN(n_1_0_688) + ); + INV_X1_LVT i_1_0_721( + .A(n_1_0_688), .ZN(n_1_0_687) + ); + SDFF_X1_LVT \registers_reg[31][1] ( + .CK(n_0_61), .D(registers[1]), .Q(registers_31__ap[1]), .QN(), .SE(dftIn), + .SI(registers_3__ap[1]) + ); + SDFF_X1_LVT \registers_reg[4][1] ( + .CK(n_0_34), .D(registers[1]), .Q(registers_4__ap[1]), .QN(), .SE(dftIn), + .SI(registers_31__ap[1]) + ); + AOI221_X1_LVT i_1_0_718( + .A(n_1_0_687), .B1(n_1_0_1266), .B2(registers_31__ap[1]), .C1(registers_4__ap[1]), + .C2(n_1_0_1278), .ZN(n_1_0_684) + ); + SDFF_X1_LVT \registers_reg[10][1] ( + .CK(n_0_40), .D(registers[1]), .Q(registers_10__ap[1]), .QN(), .SE(dftIn), + .SI(registers_13__ap[1]) + ); + SDFF_X1_LVT \registers_reg[26][1] ( + .CK(n_0_56), .D(registers[1]), .Q(registers_26__ap[1]), .QN(), .SE(dftIn), + .SI(registers_24__ap[1]) + ); + SDFF_X1_LVT \registers_reg[25][1] ( + .CK(n_0_55), .D(registers[1]), .Q(registers_25__ap[1]), .QN(), .SE(dftIn), + .SI(registers_26__ap[1]) + ); + AOI222_X1_LVT i_1_0_717( + .A1(registers_10__ap[1]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[1]), + .C1(registers_25__ap[1]), .C2(n_1_0_1269), .ZN(n_1_0_683) + ); + NAND4_X1_LVT i_1_0_716( + .A1(n_1_0_689), .A2(n_1_0_685), .A3(n_1_0_684), .A4(n_1_0_683), .ZN(n_1_0_682) + ); + SDFF_X1_LVT \registers_reg[8][1] ( + .CK(n_0_38), .D(registers[1]), .Q(registers_8__ap[1]), .QN(), .SE(dftIn), + .SI(registers_4__ap[1]) + ); + SDFF_X1_LVT \registers_reg[28][1] ( + .CK(n_0_58), .D(registers[1]), .Q(registers_28__ap[1]), .QN(), .SE(dftIn), + .SI(registers_25__ap[1]) + ); + AOI221_X1_LVT i_1_0_715( + .A(n_1_0_682), .B1(n_1_0_1282), .B2(registers_8__ap[1]), .C1(registers_28__ap[1]), + .C2(n_1_0_1283), .ZN(n_1_0_681) + ); + SDFF_X1_LVT \registers_reg[18][1] ( + .CK(n_0_48), .D(registers[1]), .Q(registers_18__ap[1]), .QN(), .SE(dftIn), + .SI(registers_20__ap[1]) + ); + SDFF_X1_LVT \registers_reg[30][1] ( + .CK(n_0_60), .D(registers[1]), .Q(registers_30__ap[1]), .QN(), .SE(dftIn), + .SI(registers_28__ap[1]) + ); + AOI22_X1_LVT i_1_0_714( + .A1(registers_18__ap[1]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[1]), + .ZN(n_1_0_680) + ); + SDFF_X1_LVT \registers_reg[17][1] ( + .CK(n_0_47), .D(registers[1]), .Q(registers_17__ap[1]), .QN(), .SE(dftIn), + .SI(registers_18__ap[1]) + ); + SDFF_X1_LVT \registers_reg[12][1] ( + .CK(n_0_42), .D(registers[1]), .Q(registers_12__ap[1]), .QN(), .SE(dftIn), + .SI(registers_10__ap[1]) + ); + AOI22_X1_LVT i_1_0_713( + .A1(registers_17__ap[1]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[1]), + .ZN(n_1_0_679) + ); + SDFF_X1_LVT \registers_reg[15][1] ( + .CK(n_0_45), .D(registers[1]), .Q(registers_15__ap[1]), .QN(), .SE(dftIn), + .SI(registers_12__ap[1]) + ); + SDFF_X1_LVT \registers_reg[5][1] ( + .CK(n_0_35), .D(registers[1]), .Q(registers_5__ap[1]), .QN(), .SE(dftIn), + .SI(registers_8__ap[1]) + ); + AOI22_X1_LVT i_1_0_712( + .A1(registers_15__ap[1]), .A2(n_1_0_1286), .B1(n_1_0_1273), .B2(registers_5__ap[1]), + .ZN(n_1_0_678) + ); + NAND3_X1_LVT i_1_0_711( + .A1(n_1_0_680), .A2(n_1_0_679), .A3(n_1_0_678), .ZN(n_1_0_677) + ); + SDFF_X1_LVT \registers_reg[22][1] ( + .CK(n_0_52), .D(registers[1]), .Q(registers_22__ap[1]), .QN(), .SE(dftIn), + .SI(registers_17__ap[1]) + ); + SDFF_X1_LVT \registers_reg[16][1] ( + .CK(n_0_46), .D(registers[1]), .Q(registers_16__ap[1]), .QN(), .SE(dftIn), + .SI(registers_15__ap[1]) + ); + AOI221_X1_LVT i_1_0_710( + .A(n_1_0_677), .B1(n_1_0_1294), .B2(registers_22__ap[1]), .C1(registers_16__ap[1]), + .C2(n_1_0_1267), .ZN(n_1_0_676) + ); + SDFF_X1_LVT \registers_reg[9][1] ( + .CK(n_0_39), .D(registers[1]), .Q(registers_9__ap[1]), .QN(), .SE(dftIn), + .SI(registers_5__ap[1]) + ); + SDFF_X1_LVT \registers_reg[1][1] ( + .CK(n_0_0), .D(registers[1]), .Q(registers_1__ap[1]), .QN(), .SE(dftIn), + .SI(registers_22__ap[1]) + ); + AOI22_X1_LVT i_1_0_709( + .A1(registers_9__ap[1]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[1]), + .ZN(n_1_0_675) + ); + SDFF_X1_LVT \registers_reg[6][1] ( + .CK(n_0_36), .D(registers[1]), .Q(registers_6__ap[1]), .QN(), .SE(dftIn), + .SI(registers_9__ap[1]) + ); + SDFF_X1_LVT \registers_reg[14][1] ( + .CK(n_0_44), .D(registers[1]), .Q(registers_14__ap[1]), .QN(), .SE(dftIn), + .SI(registers_16__ap[1]) + ); + AOI22_X1_LVT i_1_0_708( + .A1(registers_6__ap[1]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[1]), + .ZN(n_1_0_674) + ); + SDFF_X1_LVT \registers_reg[19][1] ( + .CK(n_0_49), .D(registers[1]), .Q(registers_19__ap[1]), .QN(), .SE(dftIn), + .SI(registers_1__ap[1]) + ); + SDFF_X1_LVT \registers_reg[2][1] ( + .CK(n_0_32), .D(registers[1]), .Q(registers_2__ap[1]), .QN(), .SE(dftIn), + .SI(registers_30__ap[1]) + ); + AOI22_X1_LVT i_1_0_707( + .A1(registers_19__ap[1]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[1]), + .ZN(n_1_0_673) + ); + NAND3_X1_LVT i_1_0_706( + .A1(n_1_0_675), .A2(n_1_0_674), .A3(n_1_0_673), .ZN(n_1_0_672) + ); + SDFF_X1_LVT \registers_reg[11][1] ( + .CK(n_0_41), .D(registers[1]), .Q(registers_11__ap[1]), .QN(), .SE(dftIn), + .SI(registers_14__ap[1]) + ); + SDFF_X1_LVT \registers_reg[27][1] ( + .CK(n_0_57), .D(registers[1]), .Q(registers_27__ap[1]), .QN(), .SE(dftIn), + .SI(registers_2__ap[1]) + ); + AOI221_X1_LVT i_1_0_705( + .A(n_1_0_672), .B1(n_1_0_1270), .B2(registers_11__ap[1]), .C1(registers_27__ap[1]), + .C2(n_1_0_1279), .ZN(n_1_0_671) + ); + NAND4_X1_LVT i_1_0_704( + .A1(n_1_0_686), .A2(n_1_0_681), .A3(n_1_0_676), .A4(n_1_0_671), .ZN(RRs1[1]) + ); + AND2_X1_LVT i_0_0_0( + .A1(n_0_0_16), .A2(WRd[0]), .ZN(registers[0]) + ); + SDFF_X1_LVT \registers_reg[13][0] ( + .CK(n_0_43), .D(registers[0]), .Q(registers_13__ap[0]), .QN(), .SE(dftIn), + .SI(registers_11__ap[1]) + ); + SDFF_X1_LVT \registers_reg[21][0] ( + .CK(n_0_51), .D(registers[0]), .Q(registers_21__ap[0]), .QN(), .SE(dftIn), + .SI(registers_19__ap[1]) + ); + AOI22_X1_LVT i_1_0_703( + .A1(registers_13__ap[0]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[0]), + .ZN(n_1_0_670) + ); + SDFF_X1_LVT \registers_reg[10][0] ( + .CK(n_0_40), .D(registers[0]), .Q(registers_10__ap[0]), .QN(), .SE(dftIn), + .SI(registers_13__ap[0]) + ); + SDFF_X1_LVT \registers_reg[26][0] ( + .CK(n_0_56), .D(registers[0]), .Q(registers_26__ap[0]), .QN(), .SE(dftIn), + .SI(registers_27__ap[1]) + ); + SDFF_X1_LVT \registers_reg[25][0] ( + .CK(n_0_55), .D(registers[0]), .Q(registers_25__ap[0]), .QN(), .SE(dftIn), + .SI(registers_26__ap[0]) + ); + AOI222_X1_LVT i_1_0_702( + .A1(registers_10__ap[0]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[0]), + .C1(registers_25__ap[0]), .C2(n_1_0_1269), .ZN(n_1_0_669) + ); + SDFF_X1_LVT \registers_reg[28][0] ( + .CK(n_0_58), .D(registers[0]), .Q(registers_28__ap[0]), .QN(), .SE(dftIn), + .SI(registers_25__ap[0]) + ); + SDFF_X1_LVT \registers_reg[8][0] ( + .CK(n_0_38), .D(registers[0]), .Q(registers_8__ap[0]), .QN(), .SE(dftIn), + .SI(registers_6__ap[1]) + ); + AOI22_X1_LVT i_1_0_701( + .A1(registers_28__ap[0]), .A2(n_1_0_1283), .B1(n_1_0_1282), .B2(registers_8__ap[0]), + .ZN(n_1_0_668) + ); + SDFF_X1_LVT \registers_reg[24][0] ( + .CK(n_0_54), .D(registers[0]), .Q(registers_24__ap[0]), .QN(), .SE(dftIn), + .SI(registers_28__ap[0]) + ); + SDFF_X1_LVT \registers_reg[20][0] ( + .CK(n_0_50), .D(registers[0]), .Q(registers_20__ap[0]), .QN(), .SE(dftIn), + .SI(registers_21__ap[0]) + ); + AOI22_X1_LVT i_1_0_700( + .A1(registers_24__ap[0]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[0]), + .ZN(n_1_0_667) + ); + SDFF_X1_LVT \registers_reg[7][0] ( + .CK(n_0_37), .D(registers[0]), .Q(registers_7__ap[0]), .QN(), .SE(dftIn), + .SI(registers_8__ap[0]) + ); + SDFF_X1_LVT \registers_reg[3][0] ( + .CK(n_0_33), .D(registers[0]), .Q(registers_3__ap[0]), .QN(), .SE(dftIn), + .SI(registers_7__ap[0]) + ); + AOI22_X1_LVT i_1_0_699( + .A1(registers_7__ap[0]), .A2(n_1_0_1263), .B1(n_1_0_1257), .B2(registers_3__ap[0]), + .ZN(n_1_0_666) + ); + SDFF_X1_LVT \registers_reg[17][0] ( + .CK(n_0_47), .D(registers[0]), .Q(registers_17__ap[0]), .QN(), .SE(dftIn), + .SI(registers_20__ap[0]) + ); + SDFF_X1_LVT \registers_reg[31][0] ( + .CK(n_0_61), .D(registers[0]), .Q(registers_31__ap[0]), .QN(), .SE(dftIn), + .SI(registers_3__ap[0]) + ); + AOI22_X1_LVT i_1_0_698( + .A1(registers_17__ap[0]), .A2(n_1_0_1271), .B1(n_1_0_1266), .B2(registers_31__ap[0]), + .ZN(n_1_0_665) + ); + SDFF_X1_LVT \registers_reg[29][0] ( + .CK(n_0_59), .D(registers[0]), .Q(registers_29__ap[0]), .QN(), .SE(dftIn), + .SI(registers_24__ap[0]) + ); + SDFF_X1_LVT \registers_reg[23][0] ( + .CK(n_0_53), .D(registers[0]), .Q(registers_23__ap[0]), .QN(), .SE(dftIn), + .SI(registers_17__ap[0]) + ); + AOI22_X1_LVT i_1_0_697( + .A1(registers_29__ap[0]), .A2(n_1_0_1276), .B1(n_1_0_1264), .B2(registers_23__ap[0]), + .ZN(n_1_0_664) + ); + NAND4_X1_LVT i_1_0_696( + .A1(n_1_0_667), .A2(n_1_0_666), .A3(n_1_0_665), .A4(n_1_0_664), .ZN(n_1_0_663) + ); + SDFF_X1_LVT \registers_reg[18][0] ( + .CK(n_0_48), .D(registers[0]), .Q(registers_18__ap[0]), .QN(), .SE(dftIn), + .SI(registers_23__ap[0]) + ); + SDFF_X1_LVT \registers_reg[30][0] ( + .CK(n_0_60), .D(registers[0]), .Q(registers_30__ap[0]), .QN(), .SE(dftIn), + .SI(registers_29__ap[0]) + ); + AOI22_X1_LVT i_1_0_695( + .A1(registers_18__ap[0]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[0]), + .ZN(n_1_0_662) + ); + SDFF_X1_LVT \registers_reg[4][0] ( + .CK(n_0_34), .D(registers[0]), .Q(registers_4__ap[0]), .QN(), .SE(dftIn), + .SI(registers_31__ap[0]) + ); + SDFF_X1_LVT \registers_reg[12][0] ( + .CK(n_0_42), .D(registers[0]), .Q(registers_12__ap[0]), .QN(), .SE(dftIn), + .SI(registers_10__ap[0]) + ); + AOI22_X1_LVT i_1_0_694( + .A1(registers_4__ap[0]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[0]), + .ZN(n_1_0_661) + ); + SDFF_X1_LVT \registers_reg[15][0] ( + .CK(n_0_45), .D(registers[0]), .Q(registers_15__ap[0]), .QN(), .SE(dftIn), + .SI(registers_12__ap[0]) + ); + SDFF_X1_LVT \registers_reg[16][0] ( + .CK(n_0_46), .D(registers[0]), .Q(registers_16__ap[0]), .QN(), .SE(dftIn), + .SI(registers_15__ap[0]) + ); + AOI22_X1_LVT i_1_0_693( + .A1(registers_15__ap[0]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[0]), + .ZN(n_1_0_660) + ); + SDFF_X1_LVT \registers_reg[22][0] ( + .CK(n_0_52), .D(registers[0]), .Q(registers_22__ap[0]), .QN(), .SE(dftIn), + .SI(registers_18__ap[0]) + ); + SDFF_X1_LVT \registers_reg[5][0] ( + .CK(n_0_35), .D(registers[0]), .Q(registers_5__ap[0]), .QN(), .SE(dftIn), + .SI(registers_4__ap[0]) + ); + AOI22_X1_LVT i_1_0_692( + .A1(registers_22__ap[0]), .A2(n_1_0_1294), .B1(n_1_0_1273), .B2(registers_5__ap[0]), + .ZN(n_1_0_659) + ); + NAND4_X1_LVT i_1_0_691( + .A1(n_1_0_662), .A2(n_1_0_661), .A3(n_1_0_660), .A4(n_1_0_659), .ZN(n_1_0_658) + ); + SDFF_X1_LVT \registers_reg[19][0] ( + .CK(n_0_49), .D(registers[0]), .Q(registers_19__ap[0]), .QN(), .SE(dftIn), + .SI(registers_22__ap[0]) + ); + SDFF_X1_LVT \registers_reg[2][0] ( + .CK(n_0_32), .D(registers[0]), .Q(registers_2__ap[0]), .QN(), .SE(dftIn), + .SI(registers_30__ap[0]) + ); + AOI22_X1_LVT i_1_0_690( + .A1(registers_19__ap[0]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[0]), + .ZN(n_1_0_657) + ); + SDFF_X1_LVT \registers_reg[9][0] ( + .CK(n_0_39), .D(registers[0]), .Q(registers_9__ap[0]), .QN(), .SE(dftIn), + .SI(registers_5__ap[0]) + ); + SDFF_X1_LVT \registers_reg[1][0] ( + .CK(n_0_0), .D(registers[0]), .Q(registers_1__ap[0]), .QN(), .SE(dftIn), + .SI(registers_19__ap[0]) + ); + AOI22_X1_LVT i_1_0_689( + .A1(registers_9__ap[0]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[0]), + .ZN(n_1_0_656) + ); + SDFF_X1_LVT \registers_reg[6][0] ( + .CK(n_0_36), .D(registers[0]), .Q(registers_6__ap[0]), .QN(), .SE(dftIn), + .SI(registers_9__ap[0]) + ); + SDFF_X1_LVT \registers_reg[14][0] ( + .CK(n_0_44), .D(registers[0]), .Q(registers_14__ap[0]), .QN(), .SE(dftIn), + .SI(registers_16__ap[0]) + ); + AOI22_X1_LVT i_1_0_688( + .A1(registers_6__ap[0]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[0]), + .ZN(n_1_0_655) + ); + SDFF_X1_LVT \registers_reg[27][0] ( + .CK(n_0_57), .D(registers[0]), .Q(registers_27__ap[0]), .QN(), .SE(dftIn), + .SI(registers_2__ap[0]) + ); + SDFF_X1_LVT \registers_reg[11][0] ( + .CK(n_0_41), .D(registers[0]), .Q(registers_11__ap[0]), .QN(), .SE(dftIn), + .SI(registers_14__ap[0]) + ); + AOI22_X1_LVT i_1_0_687( + .A1(registers_27__ap[0]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[0]), + .ZN(n_1_0_654) + ); + NAND4_X1_LVT i_1_0_686( + .A1(n_1_0_657), .A2(n_1_0_656), .A3(n_1_0_655), .A4(n_1_0_654), .ZN(n_1_0_653) + ); + NOR3_X1_LVT i_1_0_685( + .A1(n_1_0_663), .A2(n_1_0_658), .A3(n_1_0_653), .ZN(n_1_0_652) + ); + NAND4_X1_LVT i_1_0_684( + .A1(n_1_0_670), .A2(n_1_0_669), .A3(n_1_0_668), .A4(n_1_0_652), .ZN(RRs1[0]) + ); + INV_X1_LVT i_1_0_1366( + .A(Rs2[1]), .ZN(n_1_0_1302) + ); + NAND3_X1_LVT i_1_0_683( + .A1(n_1_0_1302), .A2(Rs2[4]), .A3(Rs2[2]), .ZN(n_1_0_651) + ); + INV_X1_LVT i_1_0_1369( + .A(Rs2[3]), .ZN(n_1_0_1305) + ); + OR2_X1_LVT i_1_0_673( + .A1(n_1_0_1305), .A2(Rs2[0]), .ZN(n_1_0_641) + ); + NOR2_X1_LVT i_1_0_666( + .A1(n_1_0_651), .A2(n_1_0_641), .ZN(n_1_0_634) + ); + NAND2_X1_LVT i_1_0_677( + .A1(n_1_0_1305), .A2(Rs2[0]), .ZN(n_1_0_645) + ); + INV_X1_LVT i_1_0_1368( + .A(Rs2[2]), .ZN(n_1_0_1304) + ); + NAND3_X1_LVT i_1_0_662( + .A1(n_1_0_1304), .A2(n_1_0_1302), .A3(Rs2[4]), .ZN(n_1_0_630) + ); + NOR2_X1_LVT i_1_0_661( + .A1(n_1_0_645), .A2(n_1_0_630), .ZN(n_1_0_629) + ); + AOI22_X1_LVT i_1_0_641( + .A1(registers_28__ap[31]), .A2(n_1_0_634), .B1(n_1_0_629), .B2(registers_17__ap[31]), + .ZN(n_1_0_609) + ); + NAND3_X1_LVT i_1_0_680( + .A1(n_1_0_1304), .A2(Rs2[4]), .A3(Rs2[1]), .ZN(n_1_0_648) + ); + NOR2_X1_LVT i_1_0_672( + .A1(n_1_0_648), .A2(n_1_0_641), .ZN(n_1_0_640) + ); + INV_X1_LVT i_1_0_1367( + .A(Rs2[4]), .ZN(n_1_0_1303) + ); + NAND3_X1_LVT i_1_0_657( + .A1(n_1_0_1304), .A2(n_1_0_1303), .A3(Rs2[1]), .ZN(n_1_0_625) + ); + NOR2_X1_LVT i_1_0_656( + .A1(n_1_0_641), .A2(n_1_0_625), .ZN(n_1_0_624) + ); + NOR4_X1_LVT i_1_0_658( + .A1(n_1_0_641), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), .ZN(n_1_0_626) + ); + AOI222_X1_LVT i_1_0_640( + .A1(registers_26__ap[31]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[31]), + .C1(n_1_0_626), .C2(registers_8__ap[31]), .ZN(n_1_0_608) + ); + NAND2_X1_LVT i_1_0_682( + .A1(Rs2[0]), .A2(Rs2[3]), .ZN(n_1_0_650) + ); + NOR2_X1_LVT i_1_0_681( + .A1(n_1_0_651), .A2(n_1_0_650), .ZN(n_1_0_649) + ); + NOR4_X1_LVT i_1_0_649( + .A1(n_1_0_650), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), .ZN(n_1_0_617) + ); + AOI22_X1_LVT i_1_0_639( + .A1(registers_29__ap[31]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[31]), + .ZN(n_1_0_607) + ); + NOR4_X1_LVT i_1_0_676( + .A1(n_1_0_645), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), .ZN(n_1_0_644) + ); + OR2_X1_LVT i_1_0_679( + .A1(Rs2[0]), .A2(Rs2[3]), .ZN(n_1_0_647) + ); + NAND3_X1_LVT i_1_0_660( + .A1(n_1_0_1303), .A2(Rs2[1]), .A3(Rs2[2]), .ZN(n_1_0_628) + ); + NOR2_X1_LVT i_1_0_648( + .A1(n_1_0_647), .A2(n_1_0_628), .ZN(n_1_0_616) + ); + AOI22_X1_LVT i_1_0_638( + .A1(registers_1__ap[31]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[31]), + .ZN(n_1_0_606) + ); + NOR2_X1_LVT i_1_0_655( + .A1(n_1_0_645), .A2(n_1_0_628), .ZN(n_1_0_623) + ); + NAND3_X1_LVT i_1_0_675( + .A1(Rs2[2]), .A2(Rs2[4]), .A3(Rs2[1]), .ZN(n_1_0_643) + ); + NOR2_X1_LVT i_1_0_647( + .A1(n_1_0_645), .A2(n_1_0_643), .ZN(n_1_0_615) + ); + AOI22_X1_LVT i_1_0_637( + .A1(registers_7__ap[31]), .A2(n_1_0_623), .B1(n_1_0_615), .B2(registers_23__ap[31]), + .ZN(n_1_0_605) + ); + NOR2_X1_LVT i_1_0_665( + .A1(n_1_0_648), .A2(n_1_0_645), .ZN(n_1_0_633) + ); + NOR2_X1_LVT i_1_0_646( + .A1(n_1_0_647), .A2(n_1_0_630), .ZN(n_1_0_614) + ); + AOI22_X1_LVT i_1_0_636( + .A1(registers_19__ap[31]), .A2(n_1_0_633), .B1(n_1_0_614), .B2(registers_16__ap[31]), + .ZN(n_1_0_604) + ); + NOR2_X1_LVT i_1_0_669( + .A1(n_1_0_650), .A2(n_1_0_643), .ZN(n_1_0_637) + ); + NAND3_X1_LVT i_1_0_671( + .A1(n_1_0_1303), .A2(n_1_0_1302), .A3(Rs2[2]), .ZN(n_1_0_639) + ); + NOR2_X1_LVT i_1_0_667( + .A1(n_1_0_645), .A2(n_1_0_639), .ZN(n_1_0_635) + ); + AOI22_X1_LVT i_1_0_635( + .A1(registers_31__ap[31]), .A2(n_1_0_637), .B1(n_1_0_635), .B2(registers_5__ap[31]), + .ZN(n_1_0_603) + ); + NAND4_X1_LVT i_1_0_634( + .A1(n_1_0_606), .A2(n_1_0_605), .A3(n_1_0_604), .A4(n_1_0_603), .ZN(n_1_0_602) + ); + NOR2_X1_LVT i_1_0_678( + .A1(n_1_0_648), .A2(n_1_0_647), .ZN(n_1_0_646) + ); + NOR2_X1_LVT i_1_0_654( + .A1(n_1_0_643), .A2(n_1_0_641), .ZN(n_1_0_622) + ); + AOI22_X1_LVT i_1_0_633( + .A1(registers_18__ap[31]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[31]), + .ZN(n_1_0_601) + ); + NOR2_X1_LVT i_1_0_670( + .A1(n_1_0_647), .A2(n_1_0_639), .ZN(n_1_0_638) + ); + NOR2_X1_LVT i_1_0_645( + .A1(n_1_0_651), .A2(n_1_0_647), .ZN(n_1_0_613) + ); + AOI22_X1_LVT i_1_0_632( + .A1(registers_4__ap[31]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[31]), + .ZN(n_1_0_600) + ); + NOR2_X1_LVT i_1_0_674( + .A1(n_1_0_647), .A2(n_1_0_643), .ZN(n_1_0_642) + ); + NOR2_X1_LVT i_1_0_644( + .A1(n_1_0_651), .A2(n_1_0_645), .ZN(n_1_0_612) + ); + AOI22_X1_LVT i_1_0_631( + .A1(registers_22__ap[31]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[31]), + .ZN(n_1_0_599) + ); + NOR2_X1_LVT i_1_0_664( + .A1(n_1_0_641), .A2(n_1_0_639), .ZN(n_1_0_632) + ); + NOR2_X1_LVT i_1_0_653( + .A1(n_1_0_641), .A2(n_1_0_630), .ZN(n_1_0_621) + ); + AOI22_X1_LVT i_1_0_630( + .A1(registers_12__ap[31]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[31]), + .ZN(n_1_0_598) + ); + NAND4_X1_LVT i_1_0_629( + .A1(n_1_0_601), .A2(n_1_0_600), .A3(n_1_0_599), .A4(n_1_0_598), .ZN(n_1_0_597) + ); + NOR2_X1_LVT i_1_0_663( + .A1(n_1_0_650), .A2(n_1_0_639), .ZN(n_1_0_631) + ); + NOR2_X1_LVT i_1_0_652( + .A1(n_1_0_650), .A2(n_1_0_630), .ZN(n_1_0_620) + ); + AOI22_X1_LVT i_1_0_628( + .A1(registers_13__ap[31]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[31]), + .ZN(n_1_0_596) + ); + NOR2_X1_LVT i_1_0_659( + .A1(n_1_0_650), .A2(n_1_0_628), .ZN(n_1_0_627) + ); + NOR2_X1_LVT i_1_0_651( + .A1(n_1_0_641), .A2(n_1_0_628), .ZN(n_1_0_619) + ); + AOI22_X1_LVT i_1_0_627( + .A1(registers_15__ap[31]), .A2(n_1_0_627), .B1(n_1_0_619), .B2(registers_14__ap[31]), + .ZN(n_1_0_595) + ); + NOR2_X1_LVT i_1_0_668( + .A1(n_1_0_650), .A2(n_1_0_648), .ZN(n_1_0_636) + ); + NOR2_X1_LVT i_1_0_643( + .A1(n_1_0_650), .A2(n_1_0_625), .ZN(n_1_0_611) + ); + AOI22_X1_LVT i_1_0_626( + .A1(registers_27__ap[31]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[31]), + .ZN(n_1_0_594) + ); + NOR2_X1_LVT i_1_0_650( + .A1(n_1_0_647), .A2(n_1_0_625), .ZN(n_1_0_618) + ); + NOR2_X1_LVT i_1_0_642( + .A1(n_1_0_645), .A2(n_1_0_625), .ZN(n_1_0_610) + ); + AOI22_X1_LVT i_1_0_625( + .A1(registers_2__ap[31]), .A2(n_1_0_618), .B1(n_1_0_610), .B2(registers_3__ap[31]), + .ZN(n_1_0_593) + ); + NAND4_X1_LVT i_1_0_624( + .A1(n_1_0_596), .A2(n_1_0_595), .A3(n_1_0_594), .A4(n_1_0_593), .ZN(n_1_0_592) + ); + NOR3_X1_LVT i_1_0_623( + .A1(n_1_0_602), .A2(n_1_0_597), .A3(n_1_0_592), .ZN(n_1_0_591) + ); + NAND4_X1_LVT i_1_0_622( + .A1(n_1_0_609), .A2(n_1_0_608), .A3(n_1_0_607), .A4(n_1_0_591), .ZN(RRs2[31]) + ); + AOI22_X1_LVT i_1_0_620( + .A1(registers_29__ap[30]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[30]), + .ZN(n_1_0_589) + ); + AOI22_X1_LVT i_1_0_621( + .A1(registers_7__ap[30]), .A2(n_1_0_623), .B1(n_1_0_615), .B2(registers_23__ap[30]), + .ZN(n_1_0_590) + ); + AOI22_X1_LVT i_1_0_619( + .A1(registers_1__ap[30]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[30]), + .ZN(n_1_0_588) + ); + AOI22_X1_LVT i_1_0_618( + .A1(registers_5__ap[30]), .A2(n_1_0_635), .B1(n_1_0_633), .B2(registers_19__ap[30]), + .ZN(n_1_0_587) + ); + NAND3_X1_LVT i_1_0_617( + .A1(n_1_0_590), .A2(n_1_0_588), .A3(n_1_0_587), .ZN(n_1_0_586) + ); + AOI221_X1_LVT i_1_0_616( + .A(n_1_0_586), .B1(n_1_0_637), .B2(registers_31__ap[30]), .C1(registers_16__ap[30]), + .C2(n_1_0_614), .ZN(n_1_0_585) + ); + AOI222_X1_LVT i_1_0_615( + .A1(registers_26__ap[30]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[30]), + .C1(n_1_0_626), .C2(registers_8__ap[30]), .ZN(n_1_0_584) + ); + NAND3_X1_LVT i_1_0_614( + .A1(n_1_0_589), .A2(n_1_0_585), .A3(n_1_0_584), .ZN(n_1_0_583) + ); + AOI221_X1_LVT i_1_0_613( + .A(n_1_0_583), .B1(n_1_0_629), .B2(registers_17__ap[30]), .C1(registers_28__ap[30]), + .C2(n_1_0_634), .ZN(n_1_0_582) + ); + AOI22_X1_LVT i_1_0_612( + .A1(registers_18__ap[30]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[30]), + .ZN(n_1_0_581) + ); + AOI22_X1_LVT i_1_0_611( + .A1(registers_4__ap[30]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[30]), + .ZN(n_1_0_580) + ); + AOI22_X1_LVT i_1_0_610( + .A1(registers_22__ap[30]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[30]), + .ZN(n_1_0_579) + ); + NAND3_X1_LVT i_1_0_609( + .A1(n_1_0_581), .A2(n_1_0_580), .A3(n_1_0_579), .ZN(n_1_0_578) + ); + AOI221_X1_LVT i_1_0_608( + .A(n_1_0_578), .B1(n_1_0_621), .B2(registers_24__ap[30]), .C1(registers_12__ap[30]), + .C2(n_1_0_632), .ZN(n_1_0_577) + ); + AOI22_X1_LVT i_1_0_607( + .A1(registers_13__ap[30]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[30]), + .ZN(n_1_0_576) + ); + AOI22_X1_LVT i_1_0_606( + .A1(registers_15__ap[30]), .A2(n_1_0_627), .B1(n_1_0_619), .B2(registers_14__ap[30]), + .ZN(n_1_0_575) + ); + AOI22_X1_LVT i_1_0_605( + .A1(registers_27__ap[30]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[30]), + .ZN(n_1_0_574) + ); + NAND3_X1_LVT i_1_0_604( + .A1(n_1_0_576), .A2(n_1_0_575), .A3(n_1_0_574), .ZN(n_1_0_573) + ); + AOI221_X1_LVT i_1_0_603( + .A(n_1_0_573), .B1(n_1_0_610), .B2(registers_3__ap[30]), .C1(registers_2__ap[30]), + .C2(n_1_0_618), .ZN(n_1_0_572) + ); + NAND3_X1_LVT i_1_0_602( + .A1(n_1_0_582), .A2(n_1_0_577), .A3(n_1_0_572), .ZN(RRs2[30]) + ); + AOI22_X1_LVT i_1_0_600( + .A1(registers_28__ap[29]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[29]), + .ZN(n_1_0_570) + ); + AOI22_X1_LVT i_1_0_601( + .A1(registers_31__ap[29]), .A2(n_1_0_637), .B1(n_1_0_627), .B2(registers_15__ap[29]), + .ZN(n_1_0_571) + ); + AOI22_X1_LVT i_1_0_599( + .A1(registers_24__ap[29]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[29]), + .ZN(n_1_0_569) + ); + AOI22_X1_LVT i_1_0_598( + .A1(registers_19__ap[29]), .A2(n_1_0_633), .B1(n_1_0_629), .B2(registers_17__ap[29]), + .ZN(n_1_0_568) + ); + NAND3_X1_LVT i_1_0_597( + .A1(n_1_0_571), .A2(n_1_0_569), .A3(n_1_0_568), .ZN(n_1_0_567) + ); + AOI221_X1_LVT i_1_0_596( + .A(n_1_0_567), .B1(n_1_0_615), .B2(registers_23__ap[29]), .C1(registers_29__ap[29]), + .C2(n_1_0_649), .ZN(n_1_0_566) + ); + AOI222_X1_LVT i_1_0_595( + .A1(registers_26__ap[29]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[29]), + .C1(n_1_0_620), .C2(registers_25__ap[29]), .ZN(n_1_0_565) + ); + NAND3_X1_LVT i_1_0_594( + .A1(n_1_0_570), .A2(n_1_0_566), .A3(n_1_0_565), .ZN(n_1_0_564) + ); + AOI221_X1_LVT i_1_0_593( + .A(n_1_0_564), .B1(n_1_0_612), .B2(registers_21__ap[29]), .C1(registers_13__ap[29]), + .C2(n_1_0_631), .ZN(n_1_0_563) + ); + AOI22_X1_LVT i_1_0_592( + .A1(registers_18__ap[29]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[29]), + .ZN(n_1_0_562) + ); + AOI22_X1_LVT i_1_0_591( + .A1(registers_4__ap[29]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[29]), + .ZN(n_1_0_561) + ); + AOI22_X1_LVT i_1_0_590( + .A1(registers_7__ap[29]), .A2(n_1_0_623), .B1(n_1_0_614), .B2(registers_16__ap[29]), + .ZN(n_1_0_560) + ); + NAND3_X1_LVT i_1_0_589( + .A1(n_1_0_562), .A2(n_1_0_561), .A3(n_1_0_560), .ZN(n_1_0_559) + ); + AOI221_X1_LVT i_1_0_588( + .A(n_1_0_559), .B1(n_1_0_642), .B2(registers_22__ap[29]), .C1(registers_5__ap[29]), + .C2(n_1_0_635), .ZN(n_1_0_558) + ); + AOI22_X1_LVT i_1_0_587( + .A1(registers_1__ap[29]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[29]), + .ZN(n_1_0_557) + ); + AOI22_X1_LVT i_1_0_586( + .A1(registers_14__ap[29]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[29]), + .ZN(n_1_0_556) + ); + AOI22_X1_LVT i_1_0_585( + .A1(registers_27__ap[29]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[29]), + .ZN(n_1_0_555) + ); + NAND3_X1_LVT i_1_0_584( + .A1(n_1_0_557), .A2(n_1_0_556), .A3(n_1_0_555), .ZN(n_1_0_554) + ); + AOI221_X1_LVT i_1_0_583( + .A(n_1_0_554), .B1(n_1_0_610), .B2(registers_3__ap[29]), .C1(registers_2__ap[29]), + .C2(n_1_0_618), .ZN(n_1_0_553) + ); + NAND3_X1_LVT i_1_0_582( + .A1(n_1_0_563), .A2(n_1_0_558), .A3(n_1_0_553), .ZN(RRs2[29]) + ); + AOI22_X1_LVT i_1_0_581( + .A1(registers_5__ap[28]), .A2(n_1_0_635), .B1(n_1_0_634), .B2(registers_28__ap[28]), + .ZN(n_1_0_552) + ); + AOI222_X1_LVT i_1_0_580( + .A1(registers_26__ap[28]), .A2(n_1_0_640), .B1(n_1_0_633), .B2(registers_19__ap[28]), + .C1(n_1_0_626), .C2(registers_8__ap[28]), .ZN(n_1_0_551) + ); + AOI22_X1_LVT i_1_0_579( + .A1(registers_2__ap[28]), .A2(n_1_0_618), .B1(n_1_0_617), .B2(registers_9__ap[28]), + .ZN(n_1_0_550) + ); + AOI22_X1_LVT i_1_0_578( + .A1(registers_7__ap[28]), .A2(n_1_0_623), .B1(n_1_0_612), .B2(registers_21__ap[28]), + .ZN(n_1_0_549) + ); + AOI22_X1_LVT i_1_0_577( + .A1(registers_16__ap[28]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[28]), + .ZN(n_1_0_548) + ); + AOI22_X1_LVT i_1_0_576( + .A1(registers_31__ap[28]), .A2(n_1_0_637), .B1(n_1_0_619), .B2(registers_14__ap[28]), + .ZN(n_1_0_547) + ); + AOI22_X1_LVT i_1_0_575( + .A1(registers_15__ap[28]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[28]), + .ZN(n_1_0_546) + ); + NAND4_X1_LVT i_1_0_574( + .A1(n_1_0_549), .A2(n_1_0_548), .A3(n_1_0_547), .A4(n_1_0_546), .ZN(n_1_0_545) + ); + AOI22_X1_LVT i_1_0_573( + .A1(registers_22__ap[28]), .A2(n_1_0_642), .B1(n_1_0_622), .B2(registers_30__ap[28]), + .ZN(n_1_0_544) + ); + AOI22_X1_LVT i_1_0_572( + .A1(registers_4__ap[28]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[28]), + .ZN(n_1_0_543) + ); + AOI22_X1_LVT i_1_0_571( + .A1(registers_29__ap[28]), .A2(n_1_0_649), .B1(n_1_0_644), .B2(registers_1__ap[28]), + .ZN(n_1_0_542) + ); + AOI22_X1_LVT i_1_0_570( + .A1(registers_12__ap[28]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[28]), + .ZN(n_1_0_541) + ); + NAND4_X1_LVT i_1_0_569( + .A1(n_1_0_544), .A2(n_1_0_543), .A3(n_1_0_542), .A4(n_1_0_541), .ZN(n_1_0_540) + ); + AOI22_X1_LVT i_1_0_568( + .A1(registers_13__ap[28]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[28]), + .ZN(n_1_0_539) + ); + AOI22_X1_LVT i_1_0_567( + .A1(registers_17__ap[28]), .A2(n_1_0_629), .B1(n_1_0_616), .B2(registers_6__ap[28]), + .ZN(n_1_0_538) + ); + AOI22_X1_LVT i_1_0_566( + .A1(registers_10__ap[28]), .A2(n_1_0_624), .B1(n_1_0_615), .B2(registers_23__ap[28]), + .ZN(n_1_0_537) + ); + AOI22_X1_LVT i_1_0_565( + .A1(registers_18__ap[28]), .A2(n_1_0_646), .B1(n_1_0_636), .B2(registers_27__ap[28]), + .ZN(n_1_0_536) + ); + NAND4_X1_LVT i_1_0_564( + .A1(n_1_0_539), .A2(n_1_0_538), .A3(n_1_0_537), .A4(n_1_0_536), .ZN(n_1_0_535) + ); + NOR3_X1_LVT i_1_0_563( + .A1(n_1_0_545), .A2(n_1_0_540), .A3(n_1_0_535), .ZN(n_1_0_534) + ); + NAND4_X1_LVT i_1_0_562( + .A1(n_1_0_552), .A2(n_1_0_551), .A3(n_1_0_550), .A4(n_1_0_534), .ZN(RRs2[28]) + ); + AOI22_X1_LVT i_1_0_561( + .A1(registers_17__ap[27]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[27]), + .ZN(n_1_0_533) + ); + AOI222_X1_LVT i_1_0_560( + .A1(registers_19__ap[27]), .A2(n_1_0_633), .B1(n_1_0_631), .B2(registers_13__ap[27]), + .C1(registers_30__ap[27]), .C2(n_1_0_622), .ZN(n_1_0_532) + ); + AOI22_X1_LVT i_1_0_559( + .A1(registers_1__ap[27]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[27]), + .ZN(n_1_0_531) + ); + AOI22_X1_LVT i_1_0_558( + .A1(registers_24__ap[27]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[27]), + .ZN(n_1_0_530) + ); + AOI22_X1_LVT i_1_0_557( + .A1(registers_15__ap[27]), .A2(n_1_0_627), .B1(n_1_0_611), .B2(registers_11__ap[27]), + .ZN(n_1_0_529) + ); + AOI22_X1_LVT i_1_0_556( + .A1(registers_4__ap[27]), .A2(n_1_0_638), .B1(n_1_0_636), .B2(registers_27__ap[27]), + .ZN(n_1_0_528) + ); + AOI22_X1_LVT i_1_0_555( + .A1(registers_31__ap[27]), .A2(n_1_0_637), .B1(n_1_0_618), .B2(registers_2__ap[27]), + .ZN(n_1_0_527) + ); + NAND4_X1_LVT i_1_0_554( + .A1(n_1_0_530), .A2(n_1_0_529), .A3(n_1_0_528), .A4(n_1_0_527), .ZN(n_1_0_526) + ); + AOI22_X1_LVT i_1_0_553( + .A1(registers_18__ap[27]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[27]), + .ZN(n_1_0_525) + ); + AOI22_X1_LVT i_1_0_552( + .A1(registers_5__ap[27]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[27]), + .ZN(n_1_0_524) + ); + AOI22_X1_LVT i_1_0_551( + .A1(registers_6__ap[27]), .A2(n_1_0_616), .B1(n_1_0_614), .B2(registers_16__ap[27]), + .ZN(n_1_0_523) + ); + AOI22_X1_LVT i_1_0_550( + .A1(registers_22__ap[27]), .A2(n_1_0_642), .B1(n_1_0_620), .B2(registers_25__ap[27]), + .ZN(n_1_0_522) + ); + NAND4_X1_LVT i_1_0_549( + .A1(n_1_0_525), .A2(n_1_0_524), .A3(n_1_0_523), .A4(n_1_0_522), .ZN(n_1_0_521) + ); + AOI22_X1_LVT i_1_0_548( + .A1(registers_29__ap[27]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[27]), + .ZN(n_1_0_520) + ); + AOI22_X1_LVT i_1_0_547( + .A1(registers_7__ap[27]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[27]), + .ZN(n_1_0_519) + ); + AOI22_X1_LVT i_1_0_546( + .A1(registers_8__ap[27]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[27]), + .ZN(n_1_0_518) + ); + AOI22_X1_LVT i_1_0_545( + .A1(registers_10__ap[27]), .A2(n_1_0_624), .B1(n_1_0_610), .B2(registers_3__ap[27]), + .ZN(n_1_0_517) + ); + NAND4_X1_LVT i_1_0_544( + .A1(n_1_0_520), .A2(n_1_0_519), .A3(n_1_0_518), .A4(n_1_0_517), .ZN(n_1_0_516) + ); + NOR3_X1_LVT i_1_0_543( + .A1(n_1_0_526), .A2(n_1_0_521), .A3(n_1_0_516), .ZN(n_1_0_515) + ); + NAND4_X1_LVT i_1_0_542( + .A1(n_1_0_533), .A2(n_1_0_532), .A3(n_1_0_531), .A4(n_1_0_515), .ZN(RRs2[27]) + ); + AOI22_X1_LVT i_1_0_541( + .A1(registers_17__ap[26]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[26]), + .ZN(n_1_0_514) + ); + AOI222_X1_LVT i_1_0_540( + .A1(registers_19__ap[26]), .A2(n_1_0_633), .B1(n_1_0_622), .B2(registers_30__ap[26]), + .C1(n_1_0_631), .C2(registers_13__ap[26]), .ZN(n_1_0_513) + ); + AOI22_X1_LVT i_1_0_539( + .A1(registers_1__ap[26]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[26]), + .ZN(n_1_0_512) + ); + AOI22_X1_LVT i_1_0_538( + .A1(registers_24__ap[26]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[26]), + .ZN(n_1_0_511) + ); + AOI22_X1_LVT i_1_0_537( + .A1(registers_15__ap[26]), .A2(n_1_0_627), .B1(n_1_0_611), .B2(registers_11__ap[26]), + .ZN(n_1_0_510) + ); + AOI22_X1_LVT i_1_0_536( + .A1(registers_4__ap[26]), .A2(n_1_0_638), .B1(n_1_0_636), .B2(registers_27__ap[26]), + .ZN(n_1_0_509) + ); + AOI22_X1_LVT i_1_0_535( + .A1(registers_31__ap[26]), .A2(n_1_0_637), .B1(n_1_0_618), .B2(registers_2__ap[26]), + .ZN(n_1_0_508) + ); + NAND4_X1_LVT i_1_0_534( + .A1(n_1_0_511), .A2(n_1_0_510), .A3(n_1_0_509), .A4(n_1_0_508), .ZN(n_1_0_507) + ); + AOI22_X1_LVT i_1_0_533( + .A1(registers_18__ap[26]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[26]), + .ZN(n_1_0_506) + ); + AOI22_X1_LVT i_1_0_532( + .A1(registers_5__ap[26]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[26]), + .ZN(n_1_0_505) + ); + AOI22_X1_LVT i_1_0_531( + .A1(registers_6__ap[26]), .A2(n_1_0_616), .B1(n_1_0_614), .B2(registers_16__ap[26]), + .ZN(n_1_0_504) + ); + AOI22_X1_LVT i_1_0_530( + .A1(registers_22__ap[26]), .A2(n_1_0_642), .B1(n_1_0_620), .B2(registers_25__ap[26]), + .ZN(n_1_0_503) + ); + NAND4_X1_LVT i_1_0_529( + .A1(n_1_0_506), .A2(n_1_0_505), .A3(n_1_0_504), .A4(n_1_0_503), .ZN(n_1_0_502) + ); + AOI22_X1_LVT i_1_0_528( + .A1(registers_29__ap[26]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[26]), + .ZN(n_1_0_501) + ); + AOI22_X1_LVT i_1_0_527( + .A1(registers_7__ap[26]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[26]), + .ZN(n_1_0_500) + ); + AOI22_X1_LVT i_1_0_526( + .A1(registers_8__ap[26]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[26]), + .ZN(n_1_0_499) + ); + AOI22_X1_LVT i_1_0_525( + .A1(registers_10__ap[26]), .A2(n_1_0_624), .B1(n_1_0_610), .B2(registers_3__ap[26]), + .ZN(n_1_0_498) + ); + NAND4_X1_LVT i_1_0_524( + .A1(n_1_0_501), .A2(n_1_0_500), .A3(n_1_0_499), .A4(n_1_0_498), .ZN(n_1_0_497) + ); + NOR3_X1_LVT i_1_0_523( + .A1(n_1_0_507), .A2(n_1_0_502), .A3(n_1_0_497), .ZN(n_1_0_496) + ); + NAND4_X1_LVT i_1_0_522( + .A1(n_1_0_514), .A2(n_1_0_513), .A3(n_1_0_512), .A4(n_1_0_496), .ZN(RRs2[26]) + ); + AOI22_X1_LVT i_1_0_520( + .A1(registers_5__ap[25]), .A2(n_1_0_635), .B1(n_1_0_634), .B2(registers_28__ap[25]), + .ZN(n_1_0_494) + ); + AOI22_X1_LVT i_1_0_521( + .A1(registers_8__ap[25]), .A2(n_1_0_626), .B1(n_1_0_620), .B2(registers_25__ap[25]), + .ZN(n_1_0_495) + ); + AOI22_X1_LVT i_1_0_519( + .A1(registers_14__ap[25]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[25]), + .ZN(n_1_0_493) + ); + AOI22_X1_LVT i_1_0_518( + .A1(registers_16__ap[25]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[25]), + .ZN(n_1_0_492) + ); + NAND3_X1_LVT i_1_0_517( + .A1(n_1_0_495), .A2(n_1_0_493), .A3(n_1_0_492), .ZN(n_1_0_491) + ); + AOI221_X1_LVT i_1_0_516( + .A(n_1_0_491), .B1(n_1_0_624), .B2(registers_10__ap[25]), .C1(registers_6__ap[25]), + .C2(n_1_0_616), .ZN(n_1_0_490) + ); + AOI222_X1_LVT i_1_0_515( + .A1(registers_1__ap[25]), .A2(n_1_0_644), .B1(n_1_0_640), .B2(registers_26__ap[25]), + .C1(n_1_0_622), .C2(registers_30__ap[25]), .ZN(n_1_0_489) + ); + NAND2_X1_LVT i_1_0_514( + .A1(n_1_0_490), .A2(n_1_0_489), .ZN(n_1_0_488) + ); + AOI221_X1_LVT i_1_0_513( + .A(n_1_0_488), .B1(n_1_0_649), .B2(registers_29__ap[25]), .C1(registers_2__ap[25]), + .C2(n_1_0_618), .ZN(n_1_0_487) + ); + AOI22_X1_LVT i_1_0_512( + .A1(registers_12__ap[25]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[25]), + .ZN(n_1_0_486) + ); + AOI22_X1_LVT i_1_0_511( + .A1(registers_22__ap[25]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[25]), + .ZN(n_1_0_485) + ); + AOI22_X1_LVT i_1_0_510( + .A1(registers_4__ap[25]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[25]), + .ZN(n_1_0_484) + ); + NAND3_X1_LVT i_1_0_509( + .A1(n_1_0_486), .A2(n_1_0_485), .A3(n_1_0_484), .ZN(n_1_0_483) + ); + AOI221_X1_LVT i_1_0_508( + .A(n_1_0_483), .B1(n_1_0_633), .B2(registers_19__ap[25]), .C1(registers_18__ap[25]), + .C2(n_1_0_646), .ZN(n_1_0_482) + ); + AOI22_X1_LVT i_1_0_507( + .A1(registers_15__ap[25]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[25]), + .ZN(n_1_0_481) + ); + AOI22_X1_LVT i_1_0_506( + .A1(registers_23__ap[25]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[25]), + .ZN(n_1_0_480) + ); + AOI22_X1_LVT i_1_0_505( + .A1(registers_13__ap[25]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[25]), + .ZN(n_1_0_479) + ); + NAND3_X1_LVT i_1_0_504( + .A1(n_1_0_481), .A2(n_1_0_480), .A3(n_1_0_479), .ZN(n_1_0_478) + ); + AOI221_X1_LVT i_1_0_503( + .A(n_1_0_478), .B1(n_1_0_636), .B2(registers_27__ap[25]), .C1(registers_31__ap[25]), + .C2(n_1_0_637), .ZN(n_1_0_477) + ); + NAND4_X1_LVT i_1_0_502( + .A1(n_1_0_494), .A2(n_1_0_487), .A3(n_1_0_482), .A4(n_1_0_477), .ZN(RRs2[25]) + ); + AOI22_X1_LVT i_1_0_501( + .A1(registers_17__ap[24]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[24]), + .ZN(n_1_0_476) + ); + AOI222_X1_LVT i_1_0_500( + .A1(registers_13__ap[24]), .A2(n_1_0_631), .B1(n_1_0_622), .B2(registers_30__ap[24]), + .C1(registers_26__ap[24]), .C2(n_1_0_640), .ZN(n_1_0_475) + ); + AOI22_X1_LVT i_1_0_499( + .A1(registers_1__ap[24]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[24]), + .ZN(n_1_0_474) + ); + AOI22_X1_LVT i_1_0_498( + .A1(registers_24__ap[24]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[24]), + .ZN(n_1_0_473) + ); + AOI22_X1_LVT i_1_0_497( + .A1(registers_8__ap[24]), .A2(n_1_0_626), .B1(n_1_0_616), .B2(registers_6__ap[24]), + .ZN(n_1_0_472) + ); + AOI22_X1_LVT i_1_0_496( + .A1(registers_4__ap[24]), .A2(n_1_0_638), .B1(n_1_0_611), .B2(registers_11__ap[24]), + .ZN(n_1_0_471) + ); + AOI22_X1_LVT i_1_0_495( + .A1(registers_10__ap[24]), .A2(n_1_0_624), .B1(n_1_0_618), .B2(registers_2__ap[24]), + .ZN(n_1_0_470) + ); + NAND4_X1_LVT i_1_0_494( + .A1(n_1_0_473), .A2(n_1_0_472), .A3(n_1_0_471), .A4(n_1_0_470), .ZN(n_1_0_469) + ); + AOI22_X1_LVT i_1_0_493( + .A1(registers_18__ap[24]), .A2(n_1_0_646), .B1(n_1_0_633), .B2(registers_19__ap[24]), + .ZN(n_1_0_468) + ); + AOI22_X1_LVT i_1_0_492( + .A1(registers_5__ap[24]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[24]), + .ZN(n_1_0_467) + ); + AOI22_X1_LVT i_1_0_491( + .A1(registers_15__ap[24]), .A2(n_1_0_627), .B1(n_1_0_614), .B2(registers_16__ap[24]), + .ZN(n_1_0_466) + ); + AOI22_X1_LVT i_1_0_490( + .A1(registers_22__ap[24]), .A2(n_1_0_642), .B1(n_1_0_620), .B2(registers_25__ap[24]), + .ZN(n_1_0_465) + ); + NAND4_X1_LVT i_1_0_489( + .A1(n_1_0_468), .A2(n_1_0_467), .A3(n_1_0_466), .A4(n_1_0_465), .ZN(n_1_0_464) + ); + AOI22_X1_LVT i_1_0_488( + .A1(registers_29__ap[24]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[24]), + .ZN(n_1_0_463) + ); + AOI22_X1_LVT i_1_0_487( + .A1(registers_7__ap[24]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[24]), + .ZN(n_1_0_462) + ); + AOI22_X1_LVT i_1_0_486( + .A1(registers_23__ap[24]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[24]), + .ZN(n_1_0_461) + ); + AOI22_X1_LVT i_1_0_485( + .A1(registers_31__ap[24]), .A2(n_1_0_637), .B1(n_1_0_636), .B2(registers_27__ap[24]), + .ZN(n_1_0_460) + ); + NAND4_X1_LVT i_1_0_484( + .A1(n_1_0_463), .A2(n_1_0_462), .A3(n_1_0_461), .A4(n_1_0_460), .ZN(n_1_0_459) + ); + NOR3_X1_LVT i_1_0_483( + .A1(n_1_0_469), .A2(n_1_0_464), .A3(n_1_0_459), .ZN(n_1_0_458) + ); + NAND4_X1_LVT i_1_0_482( + .A1(n_1_0_476), .A2(n_1_0_475), .A3(n_1_0_474), .A4(n_1_0_458), .ZN(RRs2[24]) + ); + AOI22_X1_LVT i_1_0_481( + .A1(registers_4__ap[23]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[23]), + .ZN(n_1_0_457) + ); + AOI222_X1_LVT i_1_0_480( + .A1(registers_18__ap[23]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[23]), + .C1(n_1_0_644), .C2(registers_1__ap[23]), .ZN(n_1_0_456) + ); + AOI22_X1_LVT i_1_0_479( + .A1(registers_29__ap[23]), .A2(n_1_0_649), .B1(n_1_0_618), .B2(registers_2__ap[23]), + .ZN(n_1_0_455) + ); + AOI22_X1_LVT i_1_0_478( + .A1(registers_14__ap[23]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[23]), + .ZN(n_1_0_454) + ); + AOI22_X1_LVT i_1_0_477( + .A1(registers_16__ap[23]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[23]), + .ZN(n_1_0_453) + ); + AOI22_X1_LVT i_1_0_476( + .A1(registers_27__ap[23]), .A2(n_1_0_636), .B1(n_1_0_620), .B2(registers_25__ap[23]), + .ZN(n_1_0_452) + ); + AOI22_X1_LVT i_1_0_475( + .A1(registers_31__ap[23]), .A2(n_1_0_637), .B1(n_1_0_616), .B2(registers_6__ap[23]), + .ZN(n_1_0_451) + ); + NAND4_X1_LVT i_1_0_474( + .A1(n_1_0_454), .A2(n_1_0_453), .A3(n_1_0_452), .A4(n_1_0_451), .ZN(n_1_0_450) + ); + AOI22_X1_LVT i_1_0_473( + .A1(registers_26__ap[23]), .A2(n_1_0_640), .B1(n_1_0_633), .B2(registers_19__ap[23]), + .ZN(n_1_0_449) + ); + AOI22_X1_LVT i_1_0_472( + .A1(registers_12__ap[23]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[23]), + .ZN(n_1_0_448) + ); + AOI22_X1_LVT i_1_0_471( + .A1(registers_22__ap[23]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[23]), + .ZN(n_1_0_447) + ); + AOI22_X1_LVT i_1_0_470( + .A1(registers_5__ap[23]), .A2(n_1_0_635), .B1(n_1_0_613), .B2(registers_20__ap[23]), + .ZN(n_1_0_446) + ); + NAND4_X1_LVT i_1_0_469( + .A1(n_1_0_449), .A2(n_1_0_448), .A3(n_1_0_447), .A4(n_1_0_446), .ZN(n_1_0_445) + ); + AOI22_X1_LVT i_1_0_468( + .A1(registers_15__ap[23]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[23]), + .ZN(n_1_0_444) + ); + AOI22_X1_LVT i_1_0_467( + .A1(registers_8__ap[23]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[23]), + .ZN(n_1_0_443) + ); + AOI22_X1_LVT i_1_0_466( + .A1(registers_13__ap[23]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[23]), + .ZN(n_1_0_442) + ); + AOI22_X1_LVT i_1_0_465( + .A1(registers_10__ap[23]), .A2(n_1_0_624), .B1(n_1_0_610), .B2(registers_3__ap[23]), + .ZN(n_1_0_441) + ); + NAND4_X1_LVT i_1_0_464( + .A1(n_1_0_444), .A2(n_1_0_443), .A3(n_1_0_442), .A4(n_1_0_441), .ZN(n_1_0_440) + ); + NOR3_X1_LVT i_1_0_463( + .A1(n_1_0_450), .A2(n_1_0_445), .A3(n_1_0_440), .ZN(n_1_0_439) + ); + NAND4_X1_LVT i_1_0_462( + .A1(n_1_0_457), .A2(n_1_0_456), .A3(n_1_0_455), .A4(n_1_0_439), .ZN(RRs2[23]) + ); + AOI22_X1_LVT i_1_0_460( + .A1(registers_17__ap[22]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[22]), + .ZN(n_1_0_437) + ); + AOI22_X1_LVT i_1_0_461( + .A1(registers_15__ap[22]), .A2(n_1_0_627), .B1(n_1_0_626), .B2(registers_8__ap[22]), + .ZN(n_1_0_438) + ); + AOI22_X1_LVT i_1_0_459( + .A1(registers_24__ap[22]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[22]), + .ZN(n_1_0_436) + ); + AOI22_X1_LVT i_1_0_458( + .A1(registers_5__ap[22]), .A2(n_1_0_635), .B1(n_1_0_611), .B2(registers_11__ap[22]), + .ZN(n_1_0_435) + ); + NAND3_X1_LVT i_1_0_457( + .A1(n_1_0_438), .A2(n_1_0_436), .A3(n_1_0_435), .ZN(n_1_0_434) + ); + AOI221_X1_LVT i_1_0_456( + .A(n_1_0_434), .B1(n_1_0_618), .B2(registers_2__ap[22]), .C1(registers_10__ap[22]), + .C2(n_1_0_624), .ZN(n_1_0_433) + ); + AOI222_X1_LVT i_1_0_455( + .A1(registers_26__ap[22]), .A2(n_1_0_640), .B1(n_1_0_622), .B2(registers_30__ap[22]), + .C1(n_1_0_631), .C2(registers_13__ap[22]), .ZN(n_1_0_432) + ); + NAND2_X1_LVT i_1_0_454( + .A1(n_1_0_433), .A2(n_1_0_432), .ZN(n_1_0_431) + ); + AOI221_X1_LVT i_1_0_453( + .A(n_1_0_431), .B1(n_1_0_644), .B2(registers_1__ap[22]), .C1(registers_28__ap[22]), + .C2(n_1_0_634), .ZN(n_1_0_430) + ); + AOI22_X1_LVT i_1_0_452( + .A1(registers_18__ap[22]), .A2(n_1_0_646), .B1(n_1_0_633), .B2(registers_19__ap[22]), + .ZN(n_1_0_429) + ); + AOI22_X1_LVT i_1_0_451( + .A1(registers_4__ap[22]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[22]), + .ZN(n_1_0_428) + ); + AOI22_X1_LVT i_1_0_450( + .A1(registers_6__ap[22]), .A2(n_1_0_616), .B1(n_1_0_614), .B2(registers_16__ap[22]), + .ZN(n_1_0_427) + ); + NAND3_X1_LVT i_1_0_449( + .A1(n_1_0_429), .A2(n_1_0_428), .A3(n_1_0_427), .ZN(n_1_0_426) + ); + AOI221_X1_LVT i_1_0_448( + .A(n_1_0_426), .B1(n_1_0_620), .B2(registers_25__ap[22]), .C1(registers_22__ap[22]), + .C2(n_1_0_642), .ZN(n_1_0_425) + ); + AOI22_X1_LVT i_1_0_447( + .A1(registers_29__ap[22]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[22]), + .ZN(n_1_0_424) + ); + AOI22_X1_LVT i_1_0_446( + .A1(registers_7__ap[22]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[22]), + .ZN(n_1_0_423) + ); + AOI22_X1_LVT i_1_0_445( + .A1(registers_23__ap[22]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[22]), + .ZN(n_1_0_422) + ); + NAND3_X1_LVT i_1_0_444( + .A1(n_1_0_424), .A2(n_1_0_423), .A3(n_1_0_422), .ZN(n_1_0_421) + ); + AOI221_X1_LVT i_1_0_443( + .A(n_1_0_421), .B1(n_1_0_636), .B2(registers_27__ap[22]), .C1(registers_31__ap[22]), + .C2(n_1_0_637), .ZN(n_1_0_420) + ); + NAND4_X1_LVT i_1_0_442( + .A1(n_1_0_437), .A2(n_1_0_430), .A3(n_1_0_425), .A4(n_1_0_420), .ZN(RRs2[22]) + ); + AOI22_X1_LVT i_1_0_441( + .A1(registers_5__ap[21]), .A2(n_1_0_635), .B1(n_1_0_634), .B2(registers_28__ap[21]), + .ZN(n_1_0_419) + ); + AOI222_X1_LVT i_1_0_440( + .A1(registers_1__ap[21]), .A2(n_1_0_644), .B1(n_1_0_640), .B2(registers_26__ap[21]), + .C1(n_1_0_622), .C2(registers_30__ap[21]), .ZN(n_1_0_418) + ); + AOI22_X1_LVT i_1_0_439( + .A1(registers_29__ap[21]), .A2(n_1_0_649), .B1(n_1_0_618), .B2(registers_2__ap[21]), + .ZN(n_1_0_417) + ); + AOI22_X1_LVT i_1_0_438( + .A1(registers_14__ap[21]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[21]), + .ZN(n_1_0_416) + ); + AOI22_X1_LVT i_1_0_437( + .A1(registers_8__ap[21]), .A2(n_1_0_626), .B1(n_1_0_614), .B2(registers_16__ap[21]), + .ZN(n_1_0_415) + ); + AOI22_X1_LVT i_1_0_436( + .A1(registers_25__ap[21]), .A2(n_1_0_620), .B1(n_1_0_611), .B2(registers_11__ap[21]), + .ZN(n_1_0_414) + ); + AOI22_X1_LVT i_1_0_435( + .A1(registers_10__ap[21]), .A2(n_1_0_624), .B1(n_1_0_616), .B2(registers_6__ap[21]), + .ZN(n_1_0_413) + ); + NAND4_X1_LVT i_1_0_434( + .A1(n_1_0_416), .A2(n_1_0_415), .A3(n_1_0_414), .A4(n_1_0_413), .ZN(n_1_0_412) + ); + AOI22_X1_LVT i_1_0_433( + .A1(registers_12__ap[21]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[21]), + .ZN(n_1_0_411) + ); + AOI22_X1_LVT i_1_0_432( + .A1(registers_22__ap[21]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[21]), + .ZN(n_1_0_410) + ); + AOI22_X1_LVT i_1_0_431( + .A1(registers_4__ap[21]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[21]), + .ZN(n_1_0_409) + ); + AOI22_X1_LVT i_1_0_430( + .A1(registers_18__ap[21]), .A2(n_1_0_646), .B1(n_1_0_633), .B2(registers_19__ap[21]), + .ZN(n_1_0_408) + ); + NAND4_X1_LVT i_1_0_429( + .A1(n_1_0_411), .A2(n_1_0_410), .A3(n_1_0_409), .A4(n_1_0_408), .ZN(n_1_0_407) + ); + AOI22_X1_LVT i_1_0_428( + .A1(registers_15__ap[21]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[21]), + .ZN(n_1_0_406) + ); + AOI22_X1_LVT i_1_0_427( + .A1(registers_23__ap[21]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[21]), + .ZN(n_1_0_405) + ); + AOI22_X1_LVT i_1_0_426( + .A1(registers_13__ap[21]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[21]), + .ZN(n_1_0_404) + ); + AOI22_X1_LVT i_1_0_425( + .A1(registers_31__ap[21]), .A2(n_1_0_637), .B1(n_1_0_636), .B2(registers_27__ap[21]), + .ZN(n_1_0_403) + ); + NAND4_X1_LVT i_1_0_424( + .A1(n_1_0_406), .A2(n_1_0_405), .A3(n_1_0_404), .A4(n_1_0_403), .ZN(n_1_0_402) + ); + NOR3_X1_LVT i_1_0_423( + .A1(n_1_0_412), .A2(n_1_0_407), .A3(n_1_0_402), .ZN(n_1_0_401) + ); + NAND4_X1_LVT i_1_0_422( + .A1(n_1_0_419), .A2(n_1_0_418), .A3(n_1_0_417), .A4(n_1_0_401), .ZN(RRs2[21]) + ); + AOI22_X1_LVT i_1_0_421( + .A1(registers_17__ap[20]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[20]), + .ZN(n_1_0_400) + ); + AOI222_X1_LVT i_1_0_420( + .A1(registers_13__ap[20]), .A2(n_1_0_631), .B1(n_1_0_622), .B2(registers_30__ap[20]), + .C1(registers_19__ap[20]), .C2(n_1_0_633), .ZN(n_1_0_399) + ); + AOI22_X1_LVT i_1_0_419( + .A1(registers_1__ap[20]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[20]), + .ZN(n_1_0_398) + ); + AOI22_X1_LVT i_1_0_418( + .A1(registers_24__ap[20]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[20]), + .ZN(n_1_0_397) + ); + AOI22_X1_LVT i_1_0_417( + .A1(registers_6__ap[20]), .A2(n_1_0_616), .B1(n_1_0_611), .B2(registers_11__ap[20]), + .ZN(n_1_0_396) + ); + AOI22_X1_LVT i_1_0_416( + .A1(registers_4__ap[20]), .A2(n_1_0_638), .B1(n_1_0_624), .B2(registers_10__ap[20]), + .ZN(n_1_0_395) + ); + AOI22_X1_LVT i_1_0_415( + .A1(registers_31__ap[20]), .A2(n_1_0_637), .B1(n_1_0_618), .B2(registers_2__ap[20]), + .ZN(n_1_0_394) + ); + NAND4_X1_LVT i_1_0_414( + .A1(n_1_0_397), .A2(n_1_0_396), .A3(n_1_0_395), .A4(n_1_0_394), .ZN(n_1_0_393) + ); + AOI22_X1_LVT i_1_0_413( + .A1(registers_18__ap[20]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[20]), + .ZN(n_1_0_392) + ); + AOI22_X1_LVT i_1_0_412( + .A1(registers_5__ap[20]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[20]), + .ZN(n_1_0_391) + ); + AOI22_X1_LVT i_1_0_411( + .A1(registers_15__ap[20]), .A2(n_1_0_627), .B1(n_1_0_614), .B2(registers_16__ap[20]), + .ZN(n_1_0_390) + ); + AOI22_X1_LVT i_1_0_410( + .A1(registers_22__ap[20]), .A2(n_1_0_642), .B1(n_1_0_620), .B2(registers_25__ap[20]), + .ZN(n_1_0_389) + ); + NAND4_X1_LVT i_1_0_409( + .A1(n_1_0_392), .A2(n_1_0_391), .A3(n_1_0_390), .A4(n_1_0_389), .ZN(n_1_0_388) + ); + AOI22_X1_LVT i_1_0_408( + .A1(registers_29__ap[20]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[20]), + .ZN(n_1_0_387) + ); + AOI22_X1_LVT i_1_0_407( + .A1(registers_7__ap[20]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[20]), + .ZN(n_1_0_386) + ); + AOI22_X1_LVT i_1_0_406( + .A1(registers_8__ap[20]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[20]), + .ZN(n_1_0_385) + ); + AOI22_X1_LVT i_1_0_405( + .A1(registers_27__ap[20]), .A2(n_1_0_636), .B1(n_1_0_610), .B2(registers_3__ap[20]), + .ZN(n_1_0_384) + ); + NAND4_X1_LVT i_1_0_404( + .A1(n_1_0_387), .A2(n_1_0_386), .A3(n_1_0_385), .A4(n_1_0_384), .ZN(n_1_0_383) + ); + NOR3_X1_LVT i_1_0_403( + .A1(n_1_0_393), .A2(n_1_0_388), .A3(n_1_0_383), .ZN(n_1_0_382) + ); + NAND4_X1_LVT i_1_0_402( + .A1(n_1_0_400), .A2(n_1_0_399), .A3(n_1_0_398), .A4(n_1_0_382), .ZN(RRs2[20]) + ); + AOI22_X1_LVT i_1_0_401( + .A1(registers_17__ap[19]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[19]), + .ZN(n_1_0_381) + ); + AOI222_X1_LVT i_1_0_400( + .A1(registers_13__ap[19]), .A2(n_1_0_631), .B1(n_1_0_622), .B2(registers_30__ap[19]), + .C1(registers_19__ap[19]), .C2(n_1_0_633), .ZN(n_1_0_380) + ); + AOI22_X1_LVT i_1_0_399( + .A1(registers_1__ap[19]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[19]), + .ZN(n_1_0_379) + ); + AOI22_X1_LVT i_1_0_398( + .A1(registers_24__ap[19]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[19]), + .ZN(n_1_0_378) + ); + AOI22_X1_LVT i_1_0_397( + .A1(registers_15__ap[19]), .A2(n_1_0_627), .B1(n_1_0_611), .B2(registers_11__ap[19]), + .ZN(n_1_0_377) + ); + AOI22_X1_LVT i_1_0_396( + .A1(registers_4__ap[19]), .A2(n_1_0_638), .B1(n_1_0_636), .B2(registers_27__ap[19]), + .ZN(n_1_0_376) + ); + AOI22_X1_LVT i_1_0_395( + .A1(registers_31__ap[19]), .A2(n_1_0_637), .B1(n_1_0_618), .B2(registers_2__ap[19]), + .ZN(n_1_0_375) + ); + NAND4_X1_LVT i_1_0_394( + .A1(n_1_0_378), .A2(n_1_0_377), .A3(n_1_0_376), .A4(n_1_0_375), .ZN(n_1_0_374) + ); + AOI22_X1_LVT i_1_0_393( + .A1(registers_18__ap[19]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[19]), + .ZN(n_1_0_373) + ); + AOI22_X1_LVT i_1_0_392( + .A1(registers_5__ap[19]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[19]), + .ZN(n_1_0_372) + ); + AOI22_X1_LVT i_1_0_391( + .A1(registers_25__ap[19]), .A2(n_1_0_620), .B1(n_1_0_616), .B2(registers_6__ap[19]), + .ZN(n_1_0_371) + ); + AOI22_X1_LVT i_1_0_390( + .A1(registers_22__ap[19]), .A2(n_1_0_642), .B1(n_1_0_614), .B2(registers_16__ap[19]), + .ZN(n_1_0_370) + ); + NAND4_X1_LVT i_1_0_389( + .A1(n_1_0_373), .A2(n_1_0_372), .A3(n_1_0_371), .A4(n_1_0_370), .ZN(n_1_0_369) + ); + AOI22_X1_LVT i_1_0_388( + .A1(registers_29__ap[19]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[19]), + .ZN(n_1_0_368) + ); + AOI22_X1_LVT i_1_0_387( + .A1(registers_7__ap[19]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[19]), + .ZN(n_1_0_367) + ); + AOI22_X1_LVT i_1_0_386( + .A1(registers_8__ap[19]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[19]), + .ZN(n_1_0_366) + ); + AOI22_X1_LVT i_1_0_385( + .A1(registers_10__ap[19]), .A2(n_1_0_624), .B1(n_1_0_610), .B2(registers_3__ap[19]), + .ZN(n_1_0_365) + ); + NAND4_X1_LVT i_1_0_384( + .A1(n_1_0_368), .A2(n_1_0_367), .A3(n_1_0_366), .A4(n_1_0_365), .ZN(n_1_0_364) + ); + NOR3_X1_LVT i_1_0_383( + .A1(n_1_0_374), .A2(n_1_0_369), .A3(n_1_0_364), .ZN(n_1_0_363) + ); + NAND4_X1_LVT i_1_0_382( + .A1(n_1_0_381), .A2(n_1_0_380), .A3(n_1_0_379), .A4(n_1_0_363), .ZN(RRs2[19]) + ); + AOI22_X1_LVT i_1_0_380( + .A1(registers_4__ap[18]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[18]), + .ZN(n_1_0_361) + ); + AOI22_X1_LVT i_1_0_381( + .A1(registers_8__ap[18]), .A2(n_1_0_626), .B1(n_1_0_614), .B2(registers_16__ap[18]), + .ZN(n_1_0_362) + ); + AOI22_X1_LVT i_1_0_379( + .A1(registers_14__ap[18]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[18]), + .ZN(n_1_0_360) + ); + AOI22_X1_LVT i_1_0_378( + .A1(registers_25__ap[18]), .A2(n_1_0_620), .B1(n_1_0_611), .B2(registers_11__ap[18]), + .ZN(n_1_0_359) + ); + NAND3_X1_LVT i_1_0_377( + .A1(n_1_0_362), .A2(n_1_0_360), .A3(n_1_0_359), .ZN(n_1_0_358) + ); + AOI221_X1_LVT i_1_0_376( + .A(n_1_0_358), .B1(n_1_0_624), .B2(registers_10__ap[18]), .C1(registers_6__ap[18]), + .C2(n_1_0_616), .ZN(n_1_0_357) + ); + AOI222_X1_LVT i_1_0_375( + .A1(registers_1__ap[18]), .A2(n_1_0_644), .B1(n_1_0_640), .B2(registers_26__ap[18]), + .C1(n_1_0_622), .C2(registers_30__ap[18]), .ZN(n_1_0_356) + ); + NAND2_X1_LVT i_1_0_374( + .A1(n_1_0_357), .A2(n_1_0_356), .ZN(n_1_0_355) + ); + AOI221_X1_LVT i_1_0_373( + .A(n_1_0_355), .B1(n_1_0_649), .B2(registers_29__ap[18]), .C1(registers_2__ap[18]), + .C2(n_1_0_618), .ZN(n_1_0_354) + ); + AOI22_X1_LVT i_1_0_372( + .A1(registers_18__ap[18]), .A2(n_1_0_646), .B1(n_1_0_633), .B2(registers_19__ap[18]), + .ZN(n_1_0_353) + ); + AOI22_X1_LVT i_1_0_371( + .A1(registers_12__ap[18]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[18]), + .ZN(n_1_0_352) + ); + AOI22_X1_LVT i_1_0_370( + .A1(registers_22__ap[18]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[18]), + .ZN(n_1_0_351) + ); + NAND3_X1_LVT i_1_0_369( + .A1(n_1_0_353), .A2(n_1_0_352), .A3(n_1_0_351), .ZN(n_1_0_350) + ); + AOI221_X1_LVT i_1_0_368( + .A(n_1_0_350), .B1(n_1_0_635), .B2(registers_5__ap[18]), .C1(registers_20__ap[18]), + .C2(n_1_0_613), .ZN(n_1_0_349) + ); + AOI22_X1_LVT i_1_0_367( + .A1(registers_15__ap[18]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[18]), + .ZN(n_1_0_348) + ); + AOI22_X1_LVT i_1_0_366( + .A1(registers_23__ap[18]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[18]), + .ZN(n_1_0_347) + ); + AOI22_X1_LVT i_1_0_365( + .A1(registers_13__ap[18]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[18]), + .ZN(n_1_0_346) + ); + NAND3_X1_LVT i_1_0_364( + .A1(n_1_0_348), .A2(n_1_0_347), .A3(n_1_0_346), .ZN(n_1_0_345) + ); + AOI221_X1_LVT i_1_0_363( + .A(n_1_0_345), .B1(n_1_0_637), .B2(registers_31__ap[18]), .C1(registers_27__ap[18]), + .C2(n_1_0_636), .ZN(n_1_0_344) + ); + NAND4_X1_LVT i_1_0_362( + .A1(n_1_0_361), .A2(n_1_0_354), .A3(n_1_0_349), .A4(n_1_0_344), .ZN(RRs2[18]) + ); + AOI22_X1_LVT i_1_0_358( + .A1(registers_4__ap[17]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[17]), + .ZN(n_1_0_340) + ); + AOI22_X1_LVT i_1_0_361( + .A1(registers_31__ap[17]), .A2(n_1_0_637), .B1(n_1_0_616), .B2(registers_6__ap[17]), + .ZN(n_1_0_343) + ); + AOI22_X1_LVT i_1_0_357( + .A1(registers_14__ap[17]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[17]), + .ZN(n_1_0_339) + ); + AOI22_X1_LVT i_1_0_360( + .A1(registers_25__ap[17]), .A2(n_1_0_620), .B1(n_1_0_611), .B2(registers_11__ap[17]), + .ZN(n_1_0_342) + ); + INV_X1_LVT i_1_0_359( + .A(n_1_0_342), .ZN(n_1_0_341) + ); + AOI221_X1_LVT i_1_0_356( + .A(n_1_0_341), .B1(n_1_0_614), .B2(registers_16__ap[17]), .C1(registers_10__ap[17]), + .C2(n_1_0_624), .ZN(n_1_0_338) + ); + AOI222_X1_LVT i_1_0_355( + .A1(registers_1__ap[17]), .A2(n_1_0_644), .B1(n_1_0_622), .B2(registers_30__ap[17]), + .C1(registers_18__ap[17]), .C2(n_1_0_646), .ZN(n_1_0_337) + ); + NAND4_X1_LVT i_1_0_354( + .A1(n_1_0_343), .A2(n_1_0_339), .A3(n_1_0_338), .A4(n_1_0_337), .ZN(n_1_0_336) + ); + AOI221_X1_LVT i_1_0_353( + .A(n_1_0_336), .B1(n_1_0_649), .B2(registers_29__ap[17]), .C1(registers_2__ap[17]), + .C2(n_1_0_618), .ZN(n_1_0_335) + ); + AOI22_X1_LVT i_1_0_352( + .A1(registers_26__ap[17]), .A2(n_1_0_640), .B1(n_1_0_633), .B2(registers_19__ap[17]), + .ZN(n_1_0_334) + ); + AOI22_X1_LVT i_1_0_351( + .A1(registers_12__ap[17]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[17]), + .ZN(n_1_0_333) + ); + AOI22_X1_LVT i_1_0_350( + .A1(registers_22__ap[17]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[17]), + .ZN(n_1_0_332) + ); + NAND3_X1_LVT i_1_0_349( + .A1(n_1_0_334), .A2(n_1_0_333), .A3(n_1_0_332), .ZN(n_1_0_331) + ); + AOI221_X1_LVT i_1_0_348( + .A(n_1_0_331), .B1(n_1_0_635), .B2(registers_5__ap[17]), .C1(registers_20__ap[17]), + .C2(n_1_0_613), .ZN(n_1_0_330) + ); + AOI22_X1_LVT i_1_0_347( + .A1(registers_15__ap[17]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[17]), + .ZN(n_1_0_329) + ); + AOI22_X1_LVT i_1_0_346( + .A1(registers_8__ap[17]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[17]), + .ZN(n_1_0_328) + ); + AOI22_X1_LVT i_1_0_345( + .A1(registers_13__ap[17]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[17]), + .ZN(n_1_0_327) + ); + NAND3_X1_LVT i_1_0_344( + .A1(n_1_0_329), .A2(n_1_0_328), .A3(n_1_0_327), .ZN(n_1_0_326) + ); + AOI221_X1_LVT i_1_0_343( + .A(n_1_0_326), .B1(n_1_0_636), .B2(registers_27__ap[17]), .C1(registers_3__ap[17]), + .C2(n_1_0_610), .ZN(n_1_0_325) + ); + NAND4_X1_LVT i_1_0_342( + .A1(n_1_0_340), .A2(n_1_0_335), .A3(n_1_0_330), .A4(n_1_0_325), .ZN(RRs2[17]) + ); + AOI22_X1_LVT i_1_0_341( + .A1(registers_4__ap[16]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[16]), + .ZN(n_1_0_324) + ); + AOI222_X1_LVT i_1_0_340( + .A1(registers_1__ap[16]), .A2(n_1_0_644), .B1(n_1_0_633), .B2(registers_19__ap[16]), + .C1(n_1_0_622), .C2(registers_30__ap[16]), .ZN(n_1_0_323) + ); + AOI22_X1_LVT i_1_0_339( + .A1(registers_29__ap[16]), .A2(n_1_0_649), .B1(n_1_0_618), .B2(registers_2__ap[16]), + .ZN(n_1_0_322) + ); + AOI22_X1_LVT i_1_0_338( + .A1(registers_14__ap[16]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[16]), + .ZN(n_1_0_321) + ); + AOI22_X1_LVT i_1_0_337( + .A1(registers_16__ap[16]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[16]), + .ZN(n_1_0_320) + ); + AOI22_X1_LVT i_1_0_336( + .A1(registers_10__ap[16]), .A2(n_1_0_624), .B1(n_1_0_620), .B2(registers_25__ap[16]), + .ZN(n_1_0_319) + ); + AOI22_X1_LVT i_1_0_335( + .A1(registers_31__ap[16]), .A2(n_1_0_637), .B1(n_1_0_616), .B2(registers_6__ap[16]), + .ZN(n_1_0_318) + ); + NAND4_X1_LVT i_1_0_334( + .A1(n_1_0_321), .A2(n_1_0_320), .A3(n_1_0_319), .A4(n_1_0_318), .ZN(n_1_0_317) + ); + AOI22_X1_LVT i_1_0_333( + .A1(registers_18__ap[16]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[16]), + .ZN(n_1_0_316) + ); + AOI22_X1_LVT i_1_0_332( + .A1(registers_12__ap[16]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[16]), + .ZN(n_1_0_315) + ); + AOI22_X1_LVT i_1_0_331( + .A1(registers_22__ap[16]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[16]), + .ZN(n_1_0_314) + ); + AOI22_X1_LVT i_1_0_330( + .A1(registers_5__ap[16]), .A2(n_1_0_635), .B1(n_1_0_613), .B2(registers_20__ap[16]), + .ZN(n_1_0_313) + ); + NAND4_X1_LVT i_1_0_329( + .A1(n_1_0_316), .A2(n_1_0_315), .A3(n_1_0_314), .A4(n_1_0_313), .ZN(n_1_0_312) + ); + AOI22_X1_LVT i_1_0_328( + .A1(registers_15__ap[16]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[16]), + .ZN(n_1_0_311) + ); + AOI22_X1_LVT i_1_0_327( + .A1(registers_8__ap[16]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[16]), + .ZN(n_1_0_310) + ); + AOI22_X1_LVT i_1_0_326( + .A1(registers_13__ap[16]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[16]), + .ZN(n_1_0_309) + ); + AOI22_X1_LVT i_1_0_325( + .A1(registers_27__ap[16]), .A2(n_1_0_636), .B1(n_1_0_610), .B2(registers_3__ap[16]), + .ZN(n_1_0_308) + ); + NAND4_X1_LVT i_1_0_324( + .A1(n_1_0_311), .A2(n_1_0_310), .A3(n_1_0_309), .A4(n_1_0_308), .ZN(n_1_0_307) + ); + NOR3_X1_LVT i_1_0_323( + .A1(n_1_0_317), .A2(n_1_0_312), .A3(n_1_0_307), .ZN(n_1_0_306) + ); + NAND4_X1_LVT i_1_0_322( + .A1(n_1_0_324), .A2(n_1_0_323), .A3(n_1_0_322), .A4(n_1_0_306), .ZN(RRs2[16]) + ); + AOI22_X1_LVT i_1_0_320( + .A1(registers_5__ap[15]), .A2(n_1_0_635), .B1(n_1_0_634), .B2(registers_28__ap[15]), + .ZN(n_1_0_304) + ); + AOI22_X1_LVT i_1_0_321( + .A1(registers_8__ap[15]), .A2(n_1_0_626), .B1(n_1_0_620), .B2(registers_25__ap[15]), + .ZN(n_1_0_305) + ); + AOI22_X1_LVT i_1_0_319( + .A1(registers_14__ap[15]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[15]), + .ZN(n_1_0_303) + ); + AOI22_X1_LVT i_1_0_318( + .A1(registers_16__ap[15]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[15]), + .ZN(n_1_0_302) + ); + NAND3_X1_LVT i_1_0_317( + .A1(n_1_0_305), .A2(n_1_0_303), .A3(n_1_0_302), .ZN(n_1_0_301) + ); + AOI221_X1_LVT i_1_0_316( + .A(n_1_0_301), .B1(n_1_0_616), .B2(registers_6__ap[15]), .C1(registers_10__ap[15]), + .C2(n_1_0_624), .ZN(n_1_0_300) + ); + AOI222_X1_LVT i_1_0_315( + .A1(registers_1__ap[15]), .A2(n_1_0_644), .B1(n_1_0_640), .B2(registers_26__ap[15]), + .C1(n_1_0_622), .C2(registers_30__ap[15]), .ZN(n_1_0_299) + ); + NAND2_X1_LVT i_1_0_314( + .A1(n_1_0_300), .A2(n_1_0_299), .ZN(n_1_0_298) + ); + AOI221_X1_LVT i_1_0_313( + .A(n_1_0_298), .B1(n_1_0_649), .B2(registers_29__ap[15]), .C1(registers_2__ap[15]), + .C2(n_1_0_618), .ZN(n_1_0_297) + ); + AOI22_X1_LVT i_1_0_312( + .A1(registers_12__ap[15]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[15]), + .ZN(n_1_0_296) + ); + AOI22_X1_LVT i_1_0_311( + .A1(registers_22__ap[15]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[15]), + .ZN(n_1_0_295) + ); + AOI22_X1_LVT i_1_0_310( + .A1(registers_4__ap[15]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[15]), + .ZN(n_1_0_294) + ); + NAND3_X1_LVT i_1_0_309( + .A1(n_1_0_296), .A2(n_1_0_295), .A3(n_1_0_294), .ZN(n_1_0_293) + ); + AOI221_X1_LVT i_1_0_308( + .A(n_1_0_293), .B1(n_1_0_633), .B2(registers_19__ap[15]), .C1(registers_18__ap[15]), + .C2(n_1_0_646), .ZN(n_1_0_292) + ); + AOI22_X1_LVT i_1_0_307( + .A1(registers_15__ap[15]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[15]), + .ZN(n_1_0_291) + ); + AOI22_X1_LVT i_1_0_306( + .A1(registers_23__ap[15]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[15]), + .ZN(n_1_0_290) + ); + AOI22_X1_LVT i_1_0_305( + .A1(registers_13__ap[15]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[15]), + .ZN(n_1_0_289) + ); + NAND3_X1_LVT i_1_0_304( + .A1(n_1_0_291), .A2(n_1_0_290), .A3(n_1_0_289), .ZN(n_1_0_288) + ); + AOI221_X1_LVT i_1_0_303( + .A(n_1_0_288), .B1(n_1_0_636), .B2(registers_27__ap[15]), .C1(registers_31__ap[15]), + .C2(n_1_0_637), .ZN(n_1_0_287) + ); + NAND4_X1_LVT i_1_0_302( + .A1(n_1_0_304), .A2(n_1_0_297), .A3(n_1_0_292), .A4(n_1_0_287), .ZN(RRs2[15]) + ); + AOI22_X1_LVT i_1_0_301( + .A1(registers_28__ap[14]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[14]), + .ZN(n_1_0_286) + ); + AOI222_X1_LVT i_1_0_300( + .A1(registers_18__ap[14]), .A2(n_1_0_646), .B1(n_1_0_620), .B2(registers_25__ap[14]), + .C1(n_1_0_618), .C2(registers_2__ap[14]), .ZN(n_1_0_285) + ); + AOI22_X1_LVT i_1_0_299( + .A1(registers_24__ap[14]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[14]), + .ZN(n_1_0_284) + ); + AOI22_X1_LVT i_1_0_298( + .A1(registers_15__ap[14]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[14]), + .ZN(n_1_0_283) + ); + AOI22_X1_LVT i_1_0_297( + .A1(registers_4__ap[14]), .A2(n_1_0_638), .B1(n_1_0_637), .B2(registers_31__ap[14]), + .ZN(n_1_0_282) + ); + AOI22_X1_LVT i_1_0_296( + .A1(registers_29__ap[14]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[14]), + .ZN(n_1_0_281) + ); + NAND4_X1_LVT i_1_0_295( + .A1(n_1_0_284), .A2(n_1_0_283), .A3(n_1_0_282), .A4(n_1_0_281), .ZN(n_1_0_280) + ); + AOI221_X1_LVT i_1_0_294( + .A(n_1_0_280), .B1(n_1_0_644), .B2(registers_1__ap[14]), .C1(registers_13__ap[14]), + .C2(n_1_0_631), .ZN(n_1_0_279) + ); + AOI22_X1_LVT i_1_0_293( + .A1(registers_17__ap[14]), .A2(n_1_0_629), .B1(n_1_0_623), .B2(registers_7__ap[14]), + .ZN(n_1_0_278) + ); + AOI22_X1_LVT i_1_0_292( + .A1(registers_5__ap[14]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[14]), + .ZN(n_1_0_277) + ); + AOI22_X1_LVT i_1_0_291( + .A1(registers_10__ap[14]), .A2(n_1_0_624), .B1(n_1_0_622), .B2(registers_30__ap[14]), + .ZN(n_1_0_276) + ); + AOI22_X1_LVT i_1_0_290( + .A1(registers_26__ap[14]), .A2(n_1_0_640), .B1(n_1_0_614), .B2(registers_16__ap[14]), + .ZN(n_1_0_275) + ); + NAND4_X1_LVT i_1_0_289( + .A1(n_1_0_278), .A2(n_1_0_277), .A3(n_1_0_276), .A4(n_1_0_275), .ZN(n_1_0_274) + ); + AOI22_X1_LVT i_1_0_288( + .A1(registers_9__ap[14]), .A2(n_1_0_617), .B1(n_1_0_612), .B2(registers_21__ap[14]), + .ZN(n_1_0_273) + ); + AOI22_X1_LVT i_1_0_287( + .A1(registers_14__ap[14]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[14]), + .ZN(n_1_0_272) + ); + AOI22_X1_LVT i_1_0_286( + .A1(registers_22__ap[14]), .A2(n_1_0_642), .B1(n_1_0_633), .B2(registers_19__ap[14]), + .ZN(n_1_0_271) + ); + AOI22_X1_LVT i_1_0_285( + .A1(registers_27__ap[14]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[14]), + .ZN(n_1_0_270) + ); + NAND4_X1_LVT i_1_0_284( + .A1(n_1_0_273), .A2(n_1_0_272), .A3(n_1_0_271), .A4(n_1_0_270), .ZN(n_1_0_269) + ); + NOR2_X1_LVT i_1_0_283( + .A1(n_1_0_274), .A2(n_1_0_269), .ZN(n_1_0_268) + ); + NAND4_X1_LVT i_1_0_282( + .A1(n_1_0_286), .A2(n_1_0_285), .A3(n_1_0_279), .A4(n_1_0_268), .ZN(RRs2[14]) + ); + AOI22_X1_LVT i_1_0_281( + .A1(registers_18__ap[13]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[13]), + .ZN(n_1_0_267) + ); + AOI22_X1_LVT i_1_0_280( + .A1(registers_12__ap[13]), .A2(n_1_0_632), .B1(n_1_0_629), .B2(registers_17__ap[13]), + .ZN(n_1_0_266) + ); + AOI22_X1_LVT i_1_0_279( + .A1(registers_7__ap[13]), .A2(n_1_0_623), .B1(n_1_0_614), .B2(registers_16__ap[13]), + .ZN(n_1_0_265) + ); + NAND3_X1_LVT i_1_0_277( + .A1(n_1_0_267), .A2(n_1_0_266), .A3(n_1_0_265), .ZN(n_1_0_263) + ); + AOI221_X1_LVT i_1_0_276( + .A(n_1_0_263), .B1(n_1_0_642), .B2(registers_22__ap[13]), .C1(registers_5__ap[13]), + .C2(n_1_0_635), .ZN(n_1_0_262) + ); + AOI22_X1_LVT i_1_0_278( + .A1(registers_13__ap[13]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[13]), + .ZN(n_1_0_264) + ); + AOI222_X1_LVT i_1_0_275( + .A1(registers_26__ap[13]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[13]), + .C1(n_1_0_620), .C2(registers_25__ap[13]), .ZN(n_1_0_261) + ); + AOI22_X1_LVT i_1_0_274( + .A1(registers_28__ap[13]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[13]), + .ZN(n_1_0_260) + ); + NAND3_X1_LVT i_1_0_273( + .A1(n_1_0_264), .A2(n_1_0_261), .A3(n_1_0_260), .ZN(n_1_0_259) + ); + AOI22_X1_LVT i_1_0_272( + .A1(registers_1__ap[13]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[13]), + .ZN(n_1_0_258) + ); + AOI22_X1_LVT i_1_0_271( + .A1(registers_19__ap[13]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[13]), + .ZN(n_1_0_257) + ); + AOI22_X1_LVT i_1_0_270( + .A1(registers_14__ap[13]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[13]), + .ZN(n_1_0_256) + ); + AOI22_X1_LVT i_1_0_269( + .A1(registers_27__ap[13]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[13]), + .ZN(n_1_0_255) + ); + NAND4_X1_LVT i_1_0_268( + .A1(n_1_0_258), .A2(n_1_0_257), .A3(n_1_0_256), .A4(n_1_0_255), .ZN(n_1_0_254) + ); + AOI22_X1_LVT i_1_0_267( + .A1(registers_24__ap[13]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[13]), + .ZN(n_1_0_253) + ); + AOI22_X1_LVT i_1_0_266( + .A1(registers_4__ap[13]), .A2(n_1_0_638), .B1(n_1_0_637), .B2(registers_31__ap[13]), + .ZN(n_1_0_252) + ); + AOI22_X1_LVT i_1_0_265( + .A1(registers_29__ap[13]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[13]), + .ZN(n_1_0_251) + ); + AOI22_X1_LVT i_1_0_264( + .A1(registers_15__ap[13]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[13]), + .ZN(n_1_0_250) + ); + NAND4_X1_LVT i_1_0_263( + .A1(n_1_0_253), .A2(n_1_0_252), .A3(n_1_0_251), .A4(n_1_0_250), .ZN(n_1_0_249) + ); + NOR3_X1_LVT i_1_0_262( + .A1(n_1_0_259), .A2(n_1_0_254), .A3(n_1_0_249), .ZN(n_1_0_248) + ); + NAND2_X1_LVT i_1_0_261( + .A1(n_1_0_262), .A2(n_1_0_248), .ZN(RRs2[13]) + ); + AOI22_X1_LVT i_1_0_260( + .A1(registers_18__ap[12]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[12]), + .ZN(n_1_0_247) + ); + AOI22_X1_LVT i_1_0_259( + .A1(registers_12__ap[12]), .A2(n_1_0_632), .B1(n_1_0_629), .B2(registers_17__ap[12]), + .ZN(n_1_0_246) + ); + AOI22_X1_LVT i_1_0_258( + .A1(registers_5__ap[12]), .A2(n_1_0_635), .B1(n_1_0_623), .B2(registers_7__ap[12]), + .ZN(n_1_0_245) + ); + NAND3_X1_LVT i_1_0_256( + .A1(n_1_0_247), .A2(n_1_0_246), .A3(n_1_0_245), .ZN(n_1_0_243) + ); + AOI221_X1_LVT i_1_0_255( + .A(n_1_0_243), .B1(n_1_0_642), .B2(registers_22__ap[12]), .C1(registers_16__ap[12]), + .C2(n_1_0_614), .ZN(n_1_0_242) + ); + AOI22_X1_LVT i_1_0_257( + .A1(registers_13__ap[12]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[12]), + .ZN(n_1_0_244) + ); + AOI222_X1_LVT i_1_0_254( + .A1(registers_26__ap[12]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[12]), + .C1(n_1_0_620), .C2(registers_25__ap[12]), .ZN(n_1_0_241) + ); + AOI22_X1_LVT i_1_0_253( + .A1(registers_28__ap[12]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[12]), + .ZN(n_1_0_240) + ); + NAND3_X1_LVT i_1_0_252( + .A1(n_1_0_244), .A2(n_1_0_241), .A3(n_1_0_240), .ZN(n_1_0_239) + ); + AOI22_X1_LVT i_1_0_251( + .A1(registers_1__ap[12]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[12]), + .ZN(n_1_0_238) + ); + AOI22_X1_LVT i_1_0_250( + .A1(registers_19__ap[12]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[12]), + .ZN(n_1_0_237) + ); + AOI22_X1_LVT i_1_0_249( + .A1(registers_14__ap[12]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[12]), + .ZN(n_1_0_236) + ); + AOI22_X1_LVT i_1_0_248( + .A1(registers_27__ap[12]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[12]), + .ZN(n_1_0_235) + ); + NAND4_X1_LVT i_1_0_247( + .A1(n_1_0_238), .A2(n_1_0_237), .A3(n_1_0_236), .A4(n_1_0_235), .ZN(n_1_0_234) + ); + AOI22_X1_LVT i_1_0_246( + .A1(registers_24__ap[12]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[12]), + .ZN(n_1_0_233) + ); + AOI22_X1_LVT i_1_0_245( + .A1(registers_4__ap[12]), .A2(n_1_0_638), .B1(n_1_0_637), .B2(registers_31__ap[12]), + .ZN(n_1_0_232) + ); + AOI22_X1_LVT i_1_0_244( + .A1(registers_29__ap[12]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[12]), + .ZN(n_1_0_231) + ); + AOI22_X1_LVT i_1_0_243( + .A1(registers_15__ap[12]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[12]), + .ZN(n_1_0_230) + ); + NAND4_X1_LVT i_1_0_242( + .A1(n_1_0_233), .A2(n_1_0_232), .A3(n_1_0_231), .A4(n_1_0_230), .ZN(n_1_0_229) + ); + NOR3_X1_LVT i_1_0_241( + .A1(n_1_0_239), .A2(n_1_0_234), .A3(n_1_0_229), .ZN(n_1_0_228) + ); + NAND2_X1_LVT i_1_0_240( + .A1(n_1_0_242), .A2(n_1_0_228), .ZN(RRs2[12]) + ); + AOI22_X1_LVT i_1_0_238( + .A1(registers_29__ap[11]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[11]), + .ZN(n_1_0_226) + ); + AOI22_X1_LVT i_1_0_239( + .A1(registers_27__ap[11]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[11]), + .ZN(n_1_0_227) + ); + AOI22_X1_LVT i_1_0_237( + .A1(registers_1__ap[11]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[11]), + .ZN(n_1_0_225) + ); + AOI22_X1_LVT i_1_0_236( + .A1(registers_5__ap[11]), .A2(n_1_0_635), .B1(n_1_0_615), .B2(registers_23__ap[11]), + .ZN(n_1_0_224) + ); + NAND3_X1_LVT i_1_0_235( + .A1(n_1_0_227), .A2(n_1_0_225), .A3(n_1_0_224), .ZN(n_1_0_223) + ); + AOI221_X1_LVT i_1_0_234( + .A(n_1_0_223), .B1(n_1_0_637), .B2(registers_31__ap[11]), .C1(registers_16__ap[11]), + .C2(n_1_0_614), .ZN(n_1_0_222) + ); + AOI222_X1_LVT i_1_0_233( + .A1(registers_8__ap[11]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[11]), + .C1(n_1_0_622), .C2(registers_30__ap[11]), .ZN(n_1_0_221) + ); + NAND3_X1_LVT i_1_0_232( + .A1(n_1_0_226), .A2(n_1_0_222), .A3(n_1_0_221), .ZN(n_1_0_220) + ); + AOI221_X1_LVT i_1_0_231( + .A(n_1_0_220), .B1(n_1_0_638), .B2(registers_4__ap[11]), .C1(registers_28__ap[11]), + .C2(n_1_0_634), .ZN(n_1_0_219) + ); + AOI22_X1_LVT i_1_0_230( + .A1(registers_18__ap[11]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[11]), + .ZN(n_1_0_218) + ); + AOI22_X1_LVT i_1_0_229( + .A1(registers_12__ap[11]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[11]), + .ZN(n_1_0_217) + ); + AOI22_X1_LVT i_1_0_228( + .A1(registers_22__ap[11]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[11]), + .ZN(n_1_0_216) + ); + NAND3_X1_LVT i_1_0_227( + .A1(n_1_0_218), .A2(n_1_0_217), .A3(n_1_0_216), .ZN(n_1_0_215) + ); + AOI221_X1_LVT i_1_0_226( + .A(n_1_0_215), .B1(n_1_0_613), .B2(registers_20__ap[11]), .C1(registers_17__ap[11]), + .C2(n_1_0_629), .ZN(n_1_0_214) + ); + AOI22_X1_LVT i_1_0_225( + .A1(registers_13__ap[11]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[11]), + .ZN(n_1_0_213) + ); + AOI22_X1_LVT i_1_0_224( + .A1(registers_7__ap[11]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[11]), + .ZN(n_1_0_212) + ); + AOI22_X1_LVT i_1_0_223( + .A1(registers_19__ap[11]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[11]), + .ZN(n_1_0_211) + ); + NAND3_X1_LVT i_1_0_222( + .A1(n_1_0_213), .A2(n_1_0_212), .A3(n_1_0_211), .ZN(n_1_0_210) + ); + AOI221_X1_LVT i_1_0_221( + .A(n_1_0_210), .B1(n_1_0_611), .B2(registers_11__ap[11]), .C1(registers_2__ap[11]), + .C2(n_1_0_618), .ZN(n_1_0_209) + ); + NAND3_X1_LVT i_1_0_220( + .A1(n_1_0_219), .A2(n_1_0_214), .A3(n_1_0_209), .ZN(RRs2[11]) + ); + AOI22_X1_LVT i_1_0_219( + .A1(registers_28__ap[10]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[10]), + .ZN(n_1_0_208) + ); + AOI222_X1_LVT i_1_0_218( + .A1(registers_26__ap[10]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[10]), + .C1(registers_25__ap[10]), .C2(n_1_0_620), .ZN(n_1_0_207) + ); + AOI22_X1_LVT i_1_0_217( + .A1(registers_13__ap[10]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[10]), + .ZN(n_1_0_206) + ); + AOI22_X1_LVT i_1_0_216( + .A1(registers_24__ap[10]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[10]), + .ZN(n_1_0_205) + ); + AOI22_X1_LVT i_1_0_215( + .A1(registers_15__ap[10]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[10]), + .ZN(n_1_0_204) + ); + AOI22_X1_LVT i_1_0_214( + .A1(registers_31__ap[10]), .A2(n_1_0_637), .B1(n_1_0_629), .B2(registers_17__ap[10]), + .ZN(n_1_0_203) + ); + AOI22_X1_LVT i_1_0_213( + .A1(registers_29__ap[10]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[10]), + .ZN(n_1_0_202) + ); + NAND4_X1_LVT i_1_0_212( + .A1(n_1_0_205), .A2(n_1_0_204), .A3(n_1_0_203), .A4(n_1_0_202), .ZN(n_1_0_201) + ); + AOI22_X1_LVT i_1_0_211( + .A1(registers_18__ap[10]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[10]), + .ZN(n_1_0_200) + ); + AOI22_X1_LVT i_1_0_210( + .A1(registers_4__ap[10]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[10]), + .ZN(n_1_0_199) + ); + AOI22_X1_LVT i_1_0_209( + .A1(registers_7__ap[10]), .A2(n_1_0_623), .B1(n_1_0_614), .B2(registers_16__ap[10]), + .ZN(n_1_0_198) + ); + AOI22_X1_LVT i_1_0_208( + .A1(registers_22__ap[10]), .A2(n_1_0_642), .B1(n_1_0_635), .B2(registers_5__ap[10]), + .ZN(n_1_0_197) + ); + NAND4_X1_LVT i_1_0_207( + .A1(n_1_0_200), .A2(n_1_0_199), .A3(n_1_0_198), .A4(n_1_0_197), .ZN(n_1_0_196) + ); + AOI22_X1_LVT i_1_0_206( + .A1(registers_1__ap[10]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[10]), + .ZN(n_1_0_195) + ); + AOI22_X1_LVT i_1_0_205( + .A1(registers_14__ap[10]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[10]), + .ZN(n_1_0_194) + ); + AOI22_X1_LVT i_1_0_204( + .A1(registers_19__ap[10]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[10]), + .ZN(n_1_0_193) + ); + AOI22_X1_LVT i_1_0_203( + .A1(registers_27__ap[10]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[10]), + .ZN(n_1_0_192) + ); + NAND4_X1_LVT i_1_0_202( + .A1(n_1_0_195), .A2(n_1_0_194), .A3(n_1_0_193), .A4(n_1_0_192), .ZN(n_1_0_191) + ); + NOR3_X1_LVT i_1_0_201( + .A1(n_1_0_201), .A2(n_1_0_196), .A3(n_1_0_191), .ZN(n_1_0_190) + ); + NAND4_X1_LVT i_1_0_200( + .A1(n_1_0_208), .A2(n_1_0_207), .A3(n_1_0_206), .A4(n_1_0_190), .ZN(RRs2[10]) + ); + AOI22_X1_LVT i_1_0_196( + .A1(registers_13__ap[9]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[9]), + .ZN(n_1_0_186) + ); + AOI22_X1_LVT i_1_0_199( + .A1(registers_29__ap[9]), .A2(n_1_0_649), .B1(n_1_0_636), .B2(registers_27__ap[9]), + .ZN(n_1_0_189) + ); + AOI22_X1_LVT i_1_0_195( + .A1(registers_24__ap[9]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[9]), + .ZN(n_1_0_185) + ); + AOI22_X1_LVT i_1_0_198( + .A1(registers_31__ap[9]), .A2(n_1_0_637), .B1(n_1_0_627), .B2(registers_15__ap[9]), + .ZN(n_1_0_188) + ); + INV_X1_LVT i_1_0_197( + .A(n_1_0_188), .ZN(n_1_0_187) + ); + AOI221_X1_LVT i_1_0_194( + .A(n_1_0_187), .B1(n_1_0_615), .B2(registers_23__ap[9]), .C1(registers_4__ap[9]), + .C2(n_1_0_638), .ZN(n_1_0_184) + ); + AOI222_X1_LVT i_1_0_193( + .A1(registers_18__ap[9]), .A2(n_1_0_646), .B1(n_1_0_624), .B2(registers_10__ap[9]), + .C1(registers_25__ap[9]), .C2(n_1_0_620), .ZN(n_1_0_183) + ); + NAND4_X1_LVT i_1_0_192( + .A1(n_1_0_189), .A2(n_1_0_185), .A3(n_1_0_184), .A4(n_1_0_183), .ZN(n_1_0_182) + ); + AOI221_X1_LVT i_1_0_191( + .A(n_1_0_182), .B1(n_1_0_626), .B2(registers_8__ap[9]), .C1(registers_28__ap[9]), + .C2(n_1_0_634), .ZN(n_1_0_181) + ); + AOI22_X1_LVT i_1_0_190( + .A1(registers_26__ap[9]), .A2(n_1_0_640), .B1(n_1_0_622), .B2(registers_30__ap[9]), + .ZN(n_1_0_180) + ); + AOI22_X1_LVT i_1_0_189( + .A1(registers_12__ap[9]), .A2(n_1_0_632), .B1(n_1_0_629), .B2(registers_17__ap[9]), + .ZN(n_1_0_179) + ); + AOI22_X1_LVT i_1_0_188( + .A1(registers_5__ap[9]), .A2(n_1_0_635), .B1(n_1_0_623), .B2(registers_7__ap[9]), + .ZN(n_1_0_178) + ); + NAND3_X1_LVT i_1_0_187( + .A1(n_1_0_180), .A2(n_1_0_179), .A3(n_1_0_178), .ZN(n_1_0_177) + ); + AOI221_X1_LVT i_1_0_186( + .A(n_1_0_177), .B1(n_1_0_642), .B2(registers_22__ap[9]), .C1(registers_16__ap[9]), + .C2(n_1_0_614), .ZN(n_1_0_176) + ); + AOI22_X1_LVT i_1_0_185( + .A1(registers_1__ap[9]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[9]), + .ZN(n_1_0_175) + ); + AOI22_X1_LVT i_1_0_184( + .A1(registers_14__ap[9]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[9]), + .ZN(n_1_0_174) + ); + AOI22_X1_LVT i_1_0_183( + .A1(registers_19__ap[9]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[9]), + .ZN(n_1_0_173) + ); + NAND3_X1_LVT i_1_0_182( + .A1(n_1_0_175), .A2(n_1_0_174), .A3(n_1_0_173), .ZN(n_1_0_172) + ); + AOI221_X1_LVT i_1_0_181( + .A(n_1_0_172), .B1(n_1_0_611), .B2(registers_11__ap[9]), .C1(registers_2__ap[9]), + .C2(n_1_0_618), .ZN(n_1_0_171) + ); + NAND4_X1_LVT i_1_0_180( + .A1(n_1_0_186), .A2(n_1_0_181), .A3(n_1_0_176), .A4(n_1_0_171), .ZN(RRs2[9]) + ); + AOI22_X1_LVT i_1_0_179( + .A1(registers_28__ap[8]), .A2(n_1_0_634), .B1(n_1_0_629), .B2(registers_17__ap[8]), + .ZN(n_1_0_170) + ); + AOI222_X1_LVT i_1_0_178( + .A1(registers_26__ap[8]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[8]), + .C1(n_1_0_626), .C2(registers_8__ap[8]), .ZN(n_1_0_169) + ); + AOI22_X1_LVT i_1_0_177( + .A1(registers_29__ap[8]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[8]), + .ZN(n_1_0_168) + ); + AOI22_X1_LVT i_1_0_176( + .A1(registers_1__ap[8]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[8]), + .ZN(n_1_0_167) + ); + AOI22_X1_LVT i_1_0_175( + .A1(registers_5__ap[8]), .A2(n_1_0_635), .B1(n_1_0_610), .B2(registers_3__ap[8]), + .ZN(n_1_0_166) + ); + AOI22_X1_LVT i_1_0_174( + .A1(registers_31__ap[8]), .A2(n_1_0_637), .B1(n_1_0_614), .B2(registers_16__ap[8]), + .ZN(n_1_0_165) + ); + AOI22_X1_LVT i_1_0_173( + .A1(registers_15__ap[8]), .A2(n_1_0_627), .B1(n_1_0_615), .B2(registers_23__ap[8]), + .ZN(n_1_0_164) + ); + NAND4_X1_LVT i_1_0_172( + .A1(n_1_0_167), .A2(n_1_0_166), .A3(n_1_0_165), .A4(n_1_0_164), .ZN(n_1_0_163) + ); + AOI22_X1_LVT i_1_0_171( + .A1(registers_18__ap[8]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[8]), + .ZN(n_1_0_162) + ); + AOI22_X1_LVT i_1_0_170( + .A1(registers_4__ap[8]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[8]), + .ZN(n_1_0_161) + ); + AOI22_X1_LVT i_1_0_169( + .A1(registers_22__ap[8]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[8]), + .ZN(n_1_0_160) + ); + AOI22_X1_LVT i_1_0_168( + .A1(registers_12__ap[8]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[8]), + .ZN(n_1_0_159) + ); + NAND4_X1_LVT i_1_0_167( + .A1(n_1_0_162), .A2(n_1_0_161), .A3(n_1_0_160), .A4(n_1_0_159), .ZN(n_1_0_158) + ); + AOI22_X1_LVT i_1_0_166( + .A1(registers_13__ap[8]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[8]), + .ZN(n_1_0_157) + ); + AOI22_X1_LVT i_1_0_165( + .A1(registers_7__ap[8]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[8]), + .ZN(n_1_0_156) + ); + AOI22_X1_LVT i_1_0_164( + .A1(registers_19__ap[8]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[8]), + .ZN(n_1_0_155) + ); + AOI22_X1_LVT i_1_0_163( + .A1(registers_27__ap[8]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[8]), + .ZN(n_1_0_154) + ); + NAND4_X1_LVT i_1_0_162( + .A1(n_1_0_157), .A2(n_1_0_156), .A3(n_1_0_155), .A4(n_1_0_154), .ZN(n_1_0_153) + ); + NOR3_X1_LVT i_1_0_161( + .A1(n_1_0_163), .A2(n_1_0_158), .A3(n_1_0_153), .ZN(n_1_0_152) + ); + NAND4_X1_LVT i_1_0_160( + .A1(n_1_0_170), .A2(n_1_0_169), .A3(n_1_0_168), .A4(n_1_0_152), .ZN(RRs2[8]) + ); + AOI22_X1_LVT i_1_0_159( + .A1(registers_28__ap[7]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[7]), + .ZN(n_1_0_151) + ); + AOI222_X1_LVT i_1_0_158( + .A1(registers_26__ap[7]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[7]), + .C1(registers_25__ap[7]), .C2(n_1_0_620), .ZN(n_1_0_150) + ); + AOI22_X1_LVT i_1_0_157( + .A1(registers_24__ap[7]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[7]), + .ZN(n_1_0_149) + ); + AOI22_X1_LVT i_1_0_156( + .A1(registers_15__ap[7]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[7]), + .ZN(n_1_0_148) + ); + AOI22_X1_LVT i_1_0_155( + .A1(registers_31__ap[7]), .A2(n_1_0_637), .B1(n_1_0_629), .B2(registers_17__ap[7]), + .ZN(n_1_0_147) + ); + AOI22_X1_LVT i_1_0_154( + .A1(registers_29__ap[7]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[7]), + .ZN(n_1_0_146) + ); + NAND4_X1_LVT i_1_0_153( + .A1(n_1_0_149), .A2(n_1_0_148), .A3(n_1_0_147), .A4(n_1_0_146), .ZN(n_1_0_145) + ); + AOI221_X1_LVT i_1_0_152( + .A(n_1_0_145), .B1(n_1_0_612), .B2(registers_21__ap[7]), .C1(registers_13__ap[7]), + .C2(n_1_0_631), .ZN(n_1_0_144) + ); + AOI22_X1_LVT i_1_0_151( + .A1(registers_18__ap[7]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[7]), + .ZN(n_1_0_143) + ); + AOI22_X1_LVT i_1_0_150( + .A1(registers_4__ap[7]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[7]), + .ZN(n_1_0_142) + ); + AOI22_X1_LVT i_1_0_149( + .A1(registers_5__ap[7]), .A2(n_1_0_635), .B1(n_1_0_623), .B2(registers_7__ap[7]), + .ZN(n_1_0_141) + ); + AOI22_X1_LVT i_1_0_148( + .A1(registers_22__ap[7]), .A2(n_1_0_642), .B1(n_1_0_614), .B2(registers_16__ap[7]), + .ZN(n_1_0_140) + ); + NAND4_X1_LVT i_1_0_147( + .A1(n_1_0_143), .A2(n_1_0_142), .A3(n_1_0_141), .A4(n_1_0_140), .ZN(n_1_0_139) + ); + AOI22_X1_LVT i_1_0_146( + .A1(registers_1__ap[7]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[7]), + .ZN(n_1_0_138) + ); + AOI22_X1_LVT i_1_0_145( + .A1(registers_14__ap[7]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[7]), + .ZN(n_1_0_137) + ); + AOI22_X1_LVT i_1_0_144( + .A1(registers_19__ap[7]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[7]), + .ZN(n_1_0_136) + ); + AOI22_X1_LVT i_1_0_143( + .A1(registers_27__ap[7]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[7]), + .ZN(n_1_0_135) + ); + NAND4_X1_LVT i_1_0_142( + .A1(n_1_0_138), .A2(n_1_0_137), .A3(n_1_0_136), .A4(n_1_0_135), .ZN(n_1_0_134) + ); + NOR2_X1_LVT i_1_0_141( + .A1(n_1_0_139), .A2(n_1_0_134), .ZN(n_1_0_133) + ); + NAND4_X1_LVT i_1_0_140( + .A1(n_1_0_151), .A2(n_1_0_150), .A3(n_1_0_144), .A4(n_1_0_133), .ZN(RRs2[7]) + ); + AOI22_X1_LVT i_1_0_136( + .A1(registers_13__ap[6]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[6]), + .ZN(n_1_0_129) + ); + AOI22_X1_LVT i_1_0_139( + .A1(registers_29__ap[6]), .A2(n_1_0_649), .B1(n_1_0_636), .B2(registers_27__ap[6]), + .ZN(n_1_0_132) + ); + AOI22_X1_LVT i_1_0_135( + .A1(registers_24__ap[6]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[6]), + .ZN(n_1_0_128) + ); + AOI22_X1_LVT i_1_0_138( + .A1(registers_31__ap[6]), .A2(n_1_0_637), .B1(n_1_0_627), .B2(registers_15__ap[6]), + .ZN(n_1_0_131) + ); + INV_X1_LVT i_1_0_137( + .A(n_1_0_131), .ZN(n_1_0_130) + ); + AOI221_X1_LVT i_1_0_134( + .A(n_1_0_130), .B1(n_1_0_638), .B2(registers_4__ap[6]), .C1(registers_23__ap[6]), + .C2(n_1_0_615), .ZN(n_1_0_127) + ); + AOI222_X1_LVT i_1_0_133( + .A1(registers_18__ap[6]), .A2(n_1_0_646), .B1(n_1_0_620), .B2(registers_25__ap[6]), + .C1(n_1_0_624), .C2(registers_10__ap[6]), .ZN(n_1_0_126) + ); + NAND4_X1_LVT i_1_0_132( + .A1(n_1_0_132), .A2(n_1_0_128), .A3(n_1_0_127), .A4(n_1_0_126), .ZN(n_1_0_125) + ); + AOI221_X1_LVT i_1_0_131( + .A(n_1_0_125), .B1(n_1_0_626), .B2(registers_8__ap[6]), .C1(registers_28__ap[6]), + .C2(n_1_0_634), .ZN(n_1_0_124) + ); + AOI22_X1_LVT i_1_0_130( + .A1(registers_26__ap[6]), .A2(n_1_0_640), .B1(n_1_0_622), .B2(registers_30__ap[6]), + .ZN(n_1_0_123) + ); + AOI22_X1_LVT i_1_0_129( + .A1(registers_12__ap[6]), .A2(n_1_0_632), .B1(n_1_0_629), .B2(registers_17__ap[6]), + .ZN(n_1_0_122) + ); + AOI22_X1_LVT i_1_0_128( + .A1(registers_7__ap[6]), .A2(n_1_0_623), .B1(n_1_0_614), .B2(registers_16__ap[6]), + .ZN(n_1_0_121) + ); + NAND3_X1_LVT i_1_0_127( + .A1(n_1_0_123), .A2(n_1_0_122), .A3(n_1_0_121), .ZN(n_1_0_120) + ); + AOI221_X1_LVT i_1_0_126( + .A(n_1_0_120), .B1(n_1_0_642), .B2(registers_22__ap[6]), .C1(registers_5__ap[6]), + .C2(n_1_0_635), .ZN(n_1_0_119) + ); + AOI22_X1_LVT i_1_0_125( + .A1(registers_1__ap[6]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[6]), + .ZN(n_1_0_118) + ); + AOI22_X1_LVT i_1_0_124( + .A1(registers_14__ap[6]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[6]), + .ZN(n_1_0_117) + ); + AOI22_X1_LVT i_1_0_123( + .A1(registers_19__ap[6]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[6]), + .ZN(n_1_0_116) + ); + NAND3_X1_LVT i_1_0_122( + .A1(n_1_0_118), .A2(n_1_0_117), .A3(n_1_0_116), .ZN(n_1_0_115) + ); + AOI221_X1_LVT i_1_0_121( + .A(n_1_0_115), .B1(n_1_0_618), .B2(registers_2__ap[6]), .C1(registers_11__ap[6]), + .C2(n_1_0_611), .ZN(n_1_0_114) + ); + NAND4_X1_LVT i_1_0_120( + .A1(n_1_0_129), .A2(n_1_0_124), .A3(n_1_0_119), .A4(n_1_0_114), .ZN(RRs2[6]) + ); + AOI22_X1_LVT i_1_0_118( + .A1(registers_28__ap[5]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[5]), + .ZN(n_1_0_112) + ); + AOI22_X1_LVT i_1_0_119( + .A1(registers_31__ap[5]), .A2(n_1_0_637), .B1(n_1_0_627), .B2(registers_15__ap[5]), + .ZN(n_1_0_113) + ); + AOI22_X1_LVT i_1_0_117( + .A1(registers_24__ap[5]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[5]), + .ZN(n_1_0_111) + ); + AOI22_X1_LVT i_1_0_116( + .A1(registers_17__ap[5]), .A2(n_1_0_629), .B1(n_1_0_615), .B2(registers_23__ap[5]), + .ZN(n_1_0_110) + ); + NAND3_X1_LVT i_1_0_115( + .A1(n_1_0_113), .A2(n_1_0_111), .A3(n_1_0_110), .ZN(n_1_0_109) + ); + AOI221_X1_LVT i_1_0_114( + .A(n_1_0_109), .B1(n_1_0_636), .B2(registers_27__ap[5]), .C1(registers_29__ap[5]), + .C2(n_1_0_649), .ZN(n_1_0_108) + ); + AOI222_X1_LVT i_1_0_113( + .A1(registers_10__ap[5]), .A2(n_1_0_624), .B1(n_1_0_620), .B2(registers_25__ap[5]), + .C1(registers_18__ap[5]), .C2(n_1_0_646), .ZN(n_1_0_107) + ); + NAND3_X1_LVT i_1_0_112( + .A1(n_1_0_112), .A2(n_1_0_108), .A3(n_1_0_107), .ZN(n_1_0_106) + ); + AOI221_X1_LVT i_1_0_111( + .A(n_1_0_106), .B1(n_1_0_612), .B2(registers_21__ap[5]), .C1(registers_13__ap[5]), + .C2(n_1_0_631), .ZN(n_1_0_105) + ); + AOI22_X1_LVT i_1_0_110( + .A1(registers_26__ap[5]), .A2(n_1_0_640), .B1(n_1_0_622), .B2(registers_30__ap[5]), + .ZN(n_1_0_104) + ); + AOI22_X1_LVT i_1_0_109( + .A1(registers_4__ap[5]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[5]), + .ZN(n_1_0_103) + ); + AOI22_X1_LVT i_1_0_108( + .A1(registers_5__ap[5]), .A2(n_1_0_635), .B1(n_1_0_623), .B2(registers_7__ap[5]), + .ZN(n_1_0_102) + ); + NAND3_X1_LVT i_1_0_107( + .A1(n_1_0_104), .A2(n_1_0_103), .A3(n_1_0_102), .ZN(n_1_0_101) + ); + AOI221_X1_LVT i_1_0_106( + .A(n_1_0_101), .B1(n_1_0_642), .B2(registers_22__ap[5]), .C1(registers_16__ap[5]), + .C2(n_1_0_614), .ZN(n_1_0_100) + ); + AOI22_X1_LVT i_1_0_105( + .A1(registers_1__ap[5]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[5]), + .ZN(n_1_0_99) + ); + AOI22_X1_LVT i_1_0_104( + .A1(registers_14__ap[5]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[5]), + .ZN(n_1_0_98) + ); + AOI22_X1_LVT i_1_0_103( + .A1(registers_19__ap[5]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[5]), + .ZN(n_1_0_97) + ); + NAND3_X1_LVT i_1_0_102( + .A1(n_1_0_99), .A2(n_1_0_98), .A3(n_1_0_97), .ZN(n_1_0_96) + ); + AOI221_X1_LVT i_1_0_101( + .A(n_1_0_96), .B1(n_1_0_611), .B2(registers_11__ap[5]), .C1(registers_2__ap[5]), + .C2(n_1_0_618), .ZN(n_1_0_95) + ); + NAND3_X1_LVT i_1_0_100( + .A1(n_1_0_105), .A2(n_1_0_100), .A3(n_1_0_95), .ZN(RRs2[5]) + ); + AOI22_X1_LVT i_1_0_99( + .A1(registers_4__ap[4]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[4]), + .ZN(n_1_0_94) + ); + AOI222_X1_LVT i_1_0_98( + .A1(registers_8__ap[4]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[4]), + .C1(n_1_0_622), .C2(registers_30__ap[4]), .ZN(n_1_0_93) + ); + AOI22_X1_LVT i_1_0_97( + .A1(registers_29__ap[4]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[4]), + .ZN(n_1_0_92) + ); + AOI22_X1_LVT i_1_0_96( + .A1(registers_1__ap[4]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[4]), + .ZN(n_1_0_91) + ); + AOI22_X1_LVT i_1_0_95( + .A1(registers_27__ap[4]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[4]), + .ZN(n_1_0_90) + ); + AOI22_X1_LVT i_1_0_94( + .A1(registers_23__ap[4]), .A2(n_1_0_615), .B1(n_1_0_614), .B2(registers_16__ap[4]), + .ZN(n_1_0_89) + ); + AOI22_X1_LVT i_1_0_93( + .A1(registers_31__ap[4]), .A2(n_1_0_637), .B1(n_1_0_635), .B2(registers_5__ap[4]), + .ZN(n_1_0_88) + ); + NAND4_X1_LVT i_1_0_92( + .A1(n_1_0_91), .A2(n_1_0_90), .A3(n_1_0_89), .A4(n_1_0_88), .ZN(n_1_0_87) + ); + AOI22_X1_LVT i_1_0_91( + .A1(registers_18__ap[4]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[4]), + .ZN(n_1_0_86) + ); + AOI22_X1_LVT i_1_0_90( + .A1(registers_12__ap[4]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[4]), + .ZN(n_1_0_85) + ); + AOI22_X1_LVT i_1_0_89( + .A1(registers_22__ap[4]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[4]), + .ZN(n_1_0_84) + ); + AOI22_X1_LVT i_1_0_88( + .A1(registers_17__ap[4]), .A2(n_1_0_629), .B1(n_1_0_613), .B2(registers_20__ap[4]), + .ZN(n_1_0_83) + ); + NAND4_X1_LVT i_1_0_87( + .A1(n_1_0_86), .A2(n_1_0_85), .A3(n_1_0_84), .A4(n_1_0_83), .ZN(n_1_0_82) + ); + AOI22_X1_LVT i_1_0_86( + .A1(registers_13__ap[4]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[4]), + .ZN(n_1_0_81) + ); + AOI22_X1_LVT i_1_0_85( + .A1(registers_7__ap[4]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[4]), + .ZN(n_1_0_80) + ); + AOI22_X1_LVT i_1_0_84( + .A1(registers_19__ap[4]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[4]), + .ZN(n_1_0_79) + ); + AOI22_X1_LVT i_1_0_83( + .A1(registers_2__ap[4]), .A2(n_1_0_618), .B1(n_1_0_611), .B2(registers_11__ap[4]), + .ZN(n_1_0_78) + ); + NAND4_X1_LVT i_1_0_82( + .A1(n_1_0_81), .A2(n_1_0_80), .A3(n_1_0_79), .A4(n_1_0_78), .ZN(n_1_0_77) + ); + NOR3_X1_LVT i_1_0_81( + .A1(n_1_0_87), .A2(n_1_0_82), .A3(n_1_0_77), .ZN(n_1_0_76) + ); + NAND4_X1_LVT i_1_0_80( + .A1(n_1_0_94), .A2(n_1_0_93), .A3(n_1_0_92), .A4(n_1_0_76), .ZN(RRs2[4]) + ); + AOI22_X1_LVT i_1_0_78( + .A1(registers_29__ap[3]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[3]), + .ZN(n_1_0_74) + ); + AOI22_X1_LVT i_1_0_79( + .A1(registers_27__ap[3]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[3]), + .ZN(n_1_0_75) + ); + AOI22_X1_LVT i_1_0_77( + .A1(registers_1__ap[3]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[3]), + .ZN(n_1_0_73) + ); + AOI22_X1_LVT i_1_0_76( + .A1(registers_5__ap[3]), .A2(n_1_0_635), .B1(n_1_0_611), .B2(registers_11__ap[3]), + .ZN(n_1_0_72) + ); + NAND3_X1_LVT i_1_0_75( + .A1(n_1_0_75), .A2(n_1_0_73), .A3(n_1_0_72), .ZN(n_1_0_71) + ); + AOI221_X1_LVT i_1_0_74( + .A(n_1_0_71), .B1(n_1_0_614), .B2(registers_16__ap[3]), .C1(registers_31__ap[3]), + .C2(n_1_0_637), .ZN(n_1_0_70) + ); + AOI222_X1_LVT i_1_0_73( + .A1(registers_8__ap[3]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[3]), + .C1(n_1_0_622), .C2(registers_30__ap[3]), .ZN(n_1_0_69) + ); + NAND3_X1_LVT i_1_0_72( + .A1(n_1_0_74), .A2(n_1_0_70), .A3(n_1_0_69), .ZN(n_1_0_68) + ); + AOI221_X1_LVT i_1_0_71( + .A(n_1_0_68), .B1(n_1_0_638), .B2(registers_4__ap[3]), .C1(registers_28__ap[3]), + .C2(n_1_0_634), .ZN(n_1_0_67) + ); + AOI22_X1_LVT i_1_0_70( + .A1(registers_18__ap[3]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[3]), + .ZN(n_1_0_66) + ); + AOI22_X1_LVT i_1_0_69( + .A1(registers_12__ap[3]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[3]), + .ZN(n_1_0_65) + ); + AOI22_X1_LVT i_1_0_68( + .A1(registers_22__ap[3]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[3]), + .ZN(n_1_0_64) + ); + NAND3_X1_LVT i_1_0_67( + .A1(n_1_0_66), .A2(n_1_0_65), .A3(n_1_0_64), .ZN(n_1_0_63) + ); + AOI221_X1_LVT i_1_0_66( + .A(n_1_0_63), .B1(n_1_0_613), .B2(registers_20__ap[3]), .C1(registers_17__ap[3]), + .C2(n_1_0_629), .ZN(n_1_0_62) + ); + AOI22_X1_LVT i_1_0_65( + .A1(registers_13__ap[3]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[3]), + .ZN(n_1_0_61) + ); + AOI22_X1_LVT i_1_0_64( + .A1(registers_7__ap[3]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[3]), + .ZN(n_1_0_60) + ); + AOI22_X1_LVT i_1_0_63( + .A1(registers_19__ap[3]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[3]), + .ZN(n_1_0_59) + ); + NAND3_X1_LVT i_1_0_62( + .A1(n_1_0_61), .A2(n_1_0_60), .A3(n_1_0_59), .ZN(n_1_0_58) + ); + AOI221_X1_LVT i_1_0_61( + .A(n_1_0_58), .B1(n_1_0_618), .B2(registers_2__ap[3]), .C1(registers_23__ap[3]), + .C2(n_1_0_615), .ZN(n_1_0_57) + ); + NAND3_X1_LVT i_1_0_60( + .A1(n_1_0_67), .A2(n_1_0_62), .A3(n_1_0_57), .ZN(RRs2[3]) + ); + AOI22_X1_LVT i_1_0_58( + .A1(registers_29__ap[2]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[2]), + .ZN(n_1_0_55) + ); + AOI22_X1_LVT i_1_0_59( + .A1(registers_27__ap[2]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[2]), + .ZN(n_1_0_56) + ); + AOI22_X1_LVT i_1_0_57( + .A1(registers_1__ap[2]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[2]), + .ZN(n_1_0_54) + ); + AOI22_X1_LVT i_1_0_56( + .A1(registers_5__ap[2]), .A2(n_1_0_635), .B1(n_1_0_615), .B2(registers_23__ap[2]), + .ZN(n_1_0_53) + ); + NAND3_X1_LVT i_1_0_55( + .A1(n_1_0_56), .A2(n_1_0_54), .A3(n_1_0_53), .ZN(n_1_0_52) + ); + AOI221_X1_LVT i_1_0_54( + .A(n_1_0_52), .B1(n_1_0_637), .B2(registers_31__ap[2]), .C1(registers_16__ap[2]), + .C2(n_1_0_614), .ZN(n_1_0_51) + ); + AOI222_X1_LVT i_1_0_53( + .A1(registers_8__ap[2]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[2]), + .C1(n_1_0_622), .C2(registers_30__ap[2]), .ZN(n_1_0_50) + ); + NAND3_X1_LVT i_1_0_52( + .A1(n_1_0_55), .A2(n_1_0_51), .A3(n_1_0_50), .ZN(n_1_0_49) + ); + AOI221_X1_LVT i_1_0_51( + .A(n_1_0_49), .B1(n_1_0_638), .B2(registers_4__ap[2]), .C1(registers_28__ap[2]), + .C2(n_1_0_634), .ZN(n_1_0_48) + ); + AOI22_X1_LVT i_1_0_50( + .A1(registers_18__ap[2]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[2]), + .ZN(n_1_0_47) + ); + AOI22_X1_LVT i_1_0_49( + .A1(registers_12__ap[2]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[2]), + .ZN(n_1_0_46) + ); + AOI22_X1_LVT i_1_0_48( + .A1(registers_22__ap[2]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[2]), + .ZN(n_1_0_45) + ); + NAND3_X1_LVT i_1_0_47( + .A1(n_1_0_47), .A2(n_1_0_46), .A3(n_1_0_45), .ZN(n_1_0_44) + ); + AOI221_X1_LVT i_1_0_46( + .A(n_1_0_44), .B1(n_1_0_629), .B2(registers_17__ap[2]), .C1(registers_20__ap[2]), + .C2(n_1_0_613), .ZN(n_1_0_43) + ); + AOI22_X1_LVT i_1_0_45( + .A1(registers_13__ap[2]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[2]), + .ZN(n_1_0_42) + ); + AOI22_X1_LVT i_1_0_44( + .A1(registers_7__ap[2]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[2]), + .ZN(n_1_0_41) + ); + AOI22_X1_LVT i_1_0_43( + .A1(registers_19__ap[2]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[2]), + .ZN(n_1_0_40) + ); + NAND3_X1_LVT i_1_0_42( + .A1(n_1_0_42), .A2(n_1_0_41), .A3(n_1_0_40), .ZN(n_1_0_39) + ); + AOI221_X1_LVT i_1_0_41( + .A(n_1_0_39), .B1(n_1_0_618), .B2(registers_2__ap[2]), .C1(registers_11__ap[2]), + .C2(n_1_0_611), .ZN(n_1_0_38) + ); + NAND3_X1_LVT i_1_0_40( + .A1(n_1_0_48), .A2(n_1_0_43), .A3(n_1_0_38), .ZN(RRs2[2]) + ); + AOI22_X1_LVT i_1_0_38( + .A1(registers_29__ap[1]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[1]), + .ZN(n_1_0_36) + ); + AOI22_X1_LVT i_1_0_39( + .A1(registers_16__ap[1]), .A2(n_1_0_614), .B1(n_1_0_610), .B2(registers_3__ap[1]), + .ZN(n_1_0_37) + ); + AOI22_X1_LVT i_1_0_37( + .A1(registers_1__ap[1]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[1]), + .ZN(n_1_0_35) + ); + AOI22_X1_LVT i_1_0_36( + .A1(registers_31__ap[1]), .A2(n_1_0_637), .B1(n_1_0_635), .B2(registers_5__ap[1]), + .ZN(n_1_0_34) + ); + NAND3_X1_LVT i_1_0_35( + .A1(n_1_0_37), .A2(n_1_0_35), .A3(n_1_0_34), .ZN(n_1_0_33) + ); + AOI221_X1_LVT i_1_0_34( + .A(n_1_0_33), .B1(n_1_0_627), .B2(registers_15__ap[1]), .C1(registers_23__ap[1]), + .C2(n_1_0_615), .ZN(n_1_0_32) + ); + AOI222_X1_LVT i_1_0_33( + .A1(registers_26__ap[1]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[1]), + .C1(n_1_0_626), .C2(registers_8__ap[1]), .ZN(n_1_0_31) + ); + NAND3_X1_LVT i_1_0_32( + .A1(n_1_0_36), .A2(n_1_0_32), .A3(n_1_0_31), .ZN(n_1_0_30) + ); + AOI221_X1_LVT i_1_0_31( + .A(n_1_0_30), .B1(n_1_0_629), .B2(registers_17__ap[1]), .C1(registers_28__ap[1]), + .C2(n_1_0_634), .ZN(n_1_0_29) + ); + AOI22_X1_LVT i_1_0_30( + .A1(registers_18__ap[1]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[1]), + .ZN(n_1_0_28) + ); + AOI22_X1_LVT i_1_0_29( + .A1(registers_4__ap[1]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[1]), + .ZN(n_1_0_27) + ); + AOI22_X1_LVT i_1_0_28( + .A1(registers_22__ap[1]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[1]), + .ZN(n_1_0_26) + ); + NAND3_X1_LVT i_1_0_27( + .A1(n_1_0_28), .A2(n_1_0_27), .A3(n_1_0_26), .ZN(n_1_0_25) + ); + AOI221_X1_LVT i_1_0_26( + .A(n_1_0_25), .B1(n_1_0_632), .B2(registers_12__ap[1]), .C1(registers_24__ap[1]), + .C2(n_1_0_621), .ZN(n_1_0_24) + ); + AOI22_X1_LVT i_1_0_25( + .A1(registers_13__ap[1]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[1]), + .ZN(n_1_0_23) + ); + AOI22_X1_LVT i_1_0_24( + .A1(registers_7__ap[1]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[1]), + .ZN(n_1_0_22) + ); + AOI22_X1_LVT i_1_0_23( + .A1(registers_19__ap[1]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[1]), + .ZN(n_1_0_21) + ); + NAND3_X1_LVT i_1_0_22( + .A1(n_1_0_23), .A2(n_1_0_22), .A3(n_1_0_21), .ZN(n_1_0_20) + ); + AOI221_X1_LVT i_1_0_21( + .A(n_1_0_20), .B1(n_1_0_611), .B2(registers_11__ap[1]), .C1(registers_27__ap[1]), + .C2(n_1_0_636), .ZN(n_1_0_19) + ); + NAND3_X1_LVT i_1_0_20( + .A1(n_1_0_29), .A2(n_1_0_24), .A3(n_1_0_19), .ZN(RRs2[1]) + ); + AOI22_X1_LVT i_1_0_19( + .A1(registers_4__ap[0]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[0]), + .ZN(n_1_0_18) + ); + AOI222_X1_LVT i_1_0_18( + .A1(registers_8__ap[0]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[0]), + .C1(n_1_0_622), .C2(registers_30__ap[0]), .ZN(n_1_0_17) + ); + AOI22_X1_LVT i_1_0_17( + .A1(registers_29__ap[0]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[0]), + .ZN(n_1_0_16) + ); + AOI22_X1_LVT i_1_0_16( + .A1(registers_1__ap[0]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[0]), + .ZN(n_1_0_15) + ); + AOI22_X1_LVT i_1_0_15( + .A1(registers_27__ap[0]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[0]), + .ZN(n_1_0_14) + ); + AOI22_X1_LVT i_1_0_14( + .A1(registers_23__ap[0]), .A2(n_1_0_615), .B1(n_1_0_614), .B2(registers_16__ap[0]), + .ZN(n_1_0_13) + ); + AOI22_X1_LVT i_1_0_13( + .A1(registers_31__ap[0]), .A2(n_1_0_637), .B1(n_1_0_635), .B2(registers_5__ap[0]), + .ZN(n_1_0_12) + ); + NAND4_X1_LVT i_1_0_12( + .A1(n_1_0_15), .A2(n_1_0_14), .A3(n_1_0_13), .A4(n_1_0_12), .ZN(n_1_0_11) + ); + AOI22_X1_LVT i_1_0_11( + .A1(registers_18__ap[0]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[0]), + .ZN(n_1_0_10) + ); + AOI22_X1_LVT i_1_0_10( + .A1(registers_12__ap[0]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[0]), + .ZN(n_1_0_9) + ); + AOI22_X1_LVT i_1_0_9( + .A1(registers_22__ap[0]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[0]), + .ZN(n_1_0_8) + ); + AOI22_X1_LVT i_1_0_8( + .A1(registers_17__ap[0]), .A2(n_1_0_629), .B1(n_1_0_613), .B2(registers_20__ap[0]), + .ZN(n_1_0_7) + ); + NAND4_X1_LVT i_1_0_7( + .A1(n_1_0_10), .A2(n_1_0_9), .A3(n_1_0_8), .A4(n_1_0_7), .ZN(n_1_0_6) + ); + AOI22_X1_LVT i_1_0_6( + .A1(registers_13__ap[0]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[0]), + .ZN(n_1_0_5) + ); + AOI22_X1_LVT i_1_0_5( + .A1(registers_7__ap[0]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[0]), + .ZN(n_1_0_4) + ); + AOI22_X1_LVT i_1_0_4( + .A1(registers_19__ap[0]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[0]), + .ZN(n_1_0_3) + ); + AOI22_X1_LVT i_1_0_3( + .A1(registers_2__ap[0]), .A2(n_1_0_618), .B1(n_1_0_611), .B2(registers_11__ap[0]), + .ZN(n_1_0_2) + ); + NAND4_X1_LVT i_1_0_2( + .A1(n_1_0_5), .A2(n_1_0_4), .A3(n_1_0_3), .A4(n_1_0_2), .ZN(n_1_0_1) + ); + NOR3_X1_LVT i_1_0_1( + .A1(n_1_0_11), .A2(n_1_0_6), .A3(n_1_0_1), .ZN(n_1_0_0) + ); + NAND4_X1_LVT i_1_0_0( + .A1(n_1_0_18), .A2(n_1_0_17), .A3(n_1_0_16), .A4(n_1_0_0), .ZN(RRs2[0]) + ); + DLL_X2_LVT ts_lockup_latchn_clkc2_intno1050_i( + .D(registers_1__ap[0]), .GN(n_0_0), .Q(ts_no1050) + ); + DLL_X2_LVT ts_lockup_latchn_clkc4_intno1051_i( + .D(registers_6__ap[0]), .GN(n_0_36), .Q(ts_no1051) + ); + DLL_X2_LVT ts_lockup_latchn_clkc3_intno1053_i( + .D(registers_27__ap[0]), .GN(n_0_57), .Q(ts_no1053) + ); + DLL_X2_LVT ts_lockup_latchn_clkc1_intno1054_i( + .D(registers_11__ap[0]), .GN(n_0_41), .Q(ts_no1054) + ); + CLKBUF_X3_LVT tessent_persistent_cell_buf_extsi1227_i( + .A(ts_extsi1227), .Z(ts_pbuf_extsi1227_) + ); + CLKBUF_X3_LVT tessent_persistent_cell_buf_extsi1228_i( + .A(ts_extsi1228), .Z(ts_pbuf_extsi1228_) + ); + CLKBUF_X3_LVT tessent_persistent_cell_buf_extsi1226_i( + .A(ts_extsi1226), .Z(ts_pbuf_extsi1226_) + ); +endmodule + +module cpu(led, btn, clk_25mhz, scan_en, SI_1, SO_1, SI_2, SO_2, SI_3, SO_3, SI_4, + SO_4); + input [6:0] btn; + input clk_25mhz, scan_en, SI_1, SI_2, SI_3, SI_4; + output [7:0] led; + output SO_1, SO_2, SO_3, SO_4; + + wire [31:0] Instruction, RData, RRs2, RRs1, WRd, DAddr, JumpOrBranchPC, + CurrentPC, NextPC; + wire [1:0] DWidth; + wire WrReg, JumpOrBranch, thePC_n_1, thePC_i_0_n_0, thePC_n_2, thePC_i_0_n_1, + thePC_n_3, thePC_i_0_n_2, thePC_n_4, thePC_i_0_n_3, thePC_n_5, + thePC_i_0_n_4, thePC_n_6, thePC_i_0_n_5, thePC_n_7, thePC_i_0_n_6, + thePC_n_8, thePC_i_0_n_7, thePC_n_9, thePC_i_0_n_8, thePC_n_10, + thePC_i_0_n_9, thePC_n_11, thePC_i_0_n_10, thePC_n_12, thePC_i_0_n_11, + thePC_n_13, thePC_i_0_n_12, thePC_n_14, thePC_i_0_n_13, thePC_n_15, + thePC_i_0_n_14, thePC_n_16, thePC_i_0_n_15, thePC_n_17, thePC_i_0_n_16, + thePC_n_18, thePC_i_0_n_17, thePC_n_19, thePC_i_0_n_18, thePC_n_20, + thePC_i_0_n_19, thePC_n_21, thePC_i_0_n_20, thePC_n_22, thePC_i_0_n_21, + thePC_n_23, thePC_i_0_n_22, thePC_n_24, thePC_i_0_n_23, thePC_n_25, + thePC_i_0_n_24, thePC_n_26, thePC_i_0_n_25, thePC_n_27, thePC_i_0_n_26, + thePC_n_28, thePC_i_0_n_27, thePC_n_29, thePC_n_0, thePC_n_30, n_0_0_0, + thePC_n_31, n_0_0_1, thePC_n_32, thePC_n_33, thePC_n_34, thePC_n_35, + thePC_n_36, thePC_n_37, thePC_n_38, thePC_n_39, thePC_n_40, thePC_n_41, + thePC_n_42, thePC_n_43, n_0_0_2, thePC_n_44, n_0_0_3, thePC_n_45, + n_0_0_4, thePC_n_46, n_0_0_5, thePC_n_47, n_0_0_6, thePC_n_48, n_0_0_7, + thePC_n_49, n_0_0_8, thePC_n_50, n_0_0_9, thePC_n_51, n_0_0_10, + thePC_n_52, n_0_0_11, thePC_n_53, n_0_0_12, thePC_n_54, n_0_0_13, + thePC_n_55, n_0_0_14, thePC_n_56, n_0_0_15, thePC_n_57, n_0_0_16, + thePC_n_58, n_0_0_17, thePC_n_59, n_0_0_18, thePC_n_60, n_0_0_19, + thePC_n_61, n_0_0_20, n_0_0_21, n_0_0_22, reset, uc_0, uc_1, uc_2, uc_3, + uc_4, uc_5, uc_6, uc_7, uc_8, uc_9, uc_10, uc_11, uc_12, uc_13, uc_14, + uc_15, uc_16, uc_17, uc_18, uc_19, uc_20, uc_21, uc_22, uc_23, uc_24, + uc_25, uc_26, uc_27, uc_28, uc_29, uc_30, uc_31, uc_32, uc_33, uc_34, + uc_35, uc_36, uc_37, uc_38, uc_39, uc_40, uc_41, uc_42, uc_43, uc_44, + uc_45, uc_46, uc_47, uc_48, uc_49, uc_50, uc_51, uc_52, uc_53, uc_54, + uc_55, uc_56, uc_57, uc_58, ts_pbuf_extsi1225_, ts_no1054, ts_no1050, + ts_no1053, ts_no1051; + + assign SO_1 = ts_no1054; + assign SO_2 = ts_no1050; + assign SO_3 = ts_no1053; + assign SO_4 = ts_no1051; + AND2_X1_LVT i_0_0_54( + .A1(JumpOrBranch), .A2(btn[0]), .ZN(n_0_0_22) + ); + INV_X1_LVT i_0_0_66( + .A(btn[0]), .ZN(reset) + ); + NOR2_X1_LVT i_0_0_53( + .A1(reset), .A2(JumpOrBranch), .ZN(n_0_0_21) + ); + AOI22_X1_LVT i_0_0_50( + .A1(JumpOrBranchPC[30]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_28), .ZN(n_0_0_19) + ); + INV_X1_LVT i_0_0_49( + .A(n_0_0_19), .ZN(thePC_n_60) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[30] ( + .CK(clk_25mhz), .D(thePC_n_60), .Q(CurrentPC[30]), .QN(), .SE(scan_en), .SI(ts_pbuf_extsi1225_) + ); + AOI22_X1_LVT i_0_0_48( + .A1(JumpOrBranchPC[29]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_27), .ZN(n_0_0_18) + ); + INV_X1_LVT i_0_0_47( + .A(n_0_0_18), .ZN(thePC_n_59) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[29] ( + .CK(clk_25mhz), .D(thePC_n_59), .Q(CurrentPC[29]), .QN(), .SE(scan_en), .SI(CurrentPC[30]) + ); + AOI22_X1_LVT i_0_0_46( + .A1(JumpOrBranchPC[28]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_26), .ZN(n_0_0_17) + ); + INV_X1_LVT i_0_0_45( + .A(n_0_0_17), .ZN(thePC_n_58) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[28] ( + .CK(clk_25mhz), .D(thePC_n_58), .Q(CurrentPC[28]), .QN(), .SE(scan_en), .SI(CurrentPC[29]) + ); + AOI22_X1_LVT i_0_0_44( + .A1(JumpOrBranchPC[27]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_25), .ZN(n_0_0_16) + ); + INV_X1_LVT i_0_0_43( + .A(n_0_0_16), .ZN(thePC_n_57) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[27] ( + .CK(clk_25mhz), .D(thePC_n_57), .Q(CurrentPC[27]), .QN(), .SE(scan_en), .SI(CurrentPC[28]) + ); + AOI22_X1_LVT i_0_0_42( + .A1(JumpOrBranchPC[26]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_24), .ZN(n_0_0_15) + ); + INV_X1_LVT i_0_0_41( + .A(n_0_0_15), .ZN(thePC_n_56) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[26] ( + .CK(clk_25mhz), .D(thePC_n_56), .Q(CurrentPC[26]), .QN(), .SE(scan_en), .SI(CurrentPC[27]) + ); + AOI22_X1_LVT i_0_0_40( + .A1(JumpOrBranchPC[25]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_23), .ZN(n_0_0_14) + ); + INV_X1_LVT i_0_0_39( + .A(n_0_0_14), .ZN(thePC_n_55) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[25] ( + .CK(clk_25mhz), .D(thePC_n_55), .Q(CurrentPC[25]), .QN(), .SE(scan_en), .SI(CurrentPC[26]) + ); + AOI22_X1_LVT i_0_0_38( + .A1(JumpOrBranchPC[24]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_22), .ZN(n_0_0_13) + ); + INV_X1_LVT i_0_0_37( + .A(n_0_0_13), .ZN(thePC_n_54) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[24] ( + .CK(clk_25mhz), .D(thePC_n_54), .Q(CurrentPC[24]), .QN(), .SE(scan_en), .SI(CurrentPC[25]) + ); + AOI22_X1_LVT i_0_0_36( + .A1(JumpOrBranchPC[23]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_21), .ZN(n_0_0_12) + ); + INV_X1_LVT i_0_0_35( + .A(n_0_0_12), .ZN(thePC_n_53) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[23] ( + .CK(clk_25mhz), .D(thePC_n_53), .Q(CurrentPC[23]), .QN(), .SE(scan_en), .SI(CurrentPC[24]) + ); + AOI22_X1_LVT i_0_0_34( + .A1(JumpOrBranchPC[22]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_20), .ZN(n_0_0_11) + ); + INV_X1_LVT i_0_0_33( + .A(n_0_0_11), .ZN(thePC_n_52) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[22] ( + .CK(clk_25mhz), .D(thePC_n_52), .Q(CurrentPC[22]), .QN(), .SE(scan_en), .SI(CurrentPC[23]) + ); + AOI22_X1_LVT i_0_0_32( + .A1(JumpOrBranchPC[21]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_19), .ZN(n_0_0_10) + ); + INV_X1_LVT i_0_0_31( + .A(n_0_0_10), .ZN(thePC_n_51) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[21] ( + .CK(clk_25mhz), .D(thePC_n_51), .Q(CurrentPC[21]), .QN(), .SE(scan_en), .SI(CurrentPC[22]) + ); + AOI22_X1_LVT i_0_0_30( + .A1(JumpOrBranchPC[20]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_18), .ZN(n_0_0_9) + ); + INV_X1_LVT i_0_0_29( + .A(n_0_0_9), .ZN(thePC_n_50) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[20] ( + .CK(clk_25mhz), .D(thePC_n_50), .Q(CurrentPC[20]), .QN(), .SE(scan_en), .SI(CurrentPC[21]) + ); + AOI22_X1_LVT i_0_0_28( + .A1(JumpOrBranchPC[19]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_17), .ZN(n_0_0_8) + ); + INV_X1_LVT i_0_0_27( + .A(n_0_0_8), .ZN(thePC_n_49) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[19] ( + .CK(clk_25mhz), .D(thePC_n_49), .Q(CurrentPC[19]), .QN(), .SE(scan_en), .SI(CurrentPC[20]) + ); + AOI22_X1_LVT i_0_0_26( + .A1(JumpOrBranchPC[18]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_16), .ZN(n_0_0_7) + ); + INV_X1_LVT i_0_0_25( + .A(n_0_0_7), .ZN(thePC_n_48) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[18] ( + .CK(clk_25mhz), .D(thePC_n_48), .Q(CurrentPC[18]), .QN(), .SE(scan_en), .SI(CurrentPC[19]) + ); + AOI22_X1_LVT i_0_0_24( + .A1(JumpOrBranchPC[17]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_15), .ZN(n_0_0_6) + ); + INV_X1_LVT i_0_0_23( + .A(n_0_0_6), .ZN(thePC_n_47) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[17] ( + .CK(clk_25mhz), .D(thePC_n_47), .Q(CurrentPC[17]), .QN(), .SE(scan_en), .SI(CurrentPC[18]) + ); + AOI22_X1_LVT i_0_0_22( + .A1(JumpOrBranchPC[16]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_14), .ZN(n_0_0_5) + ); + INV_X1_LVT i_0_0_21( + .A(n_0_0_5), .ZN(thePC_n_46) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[16] ( + .CK(clk_25mhz), .D(thePC_n_46), .Q(CurrentPC[16]), .QN(), .SE(scan_en), .SI(CurrentPC[17]) + ); + AOI22_X1_LVT i_0_0_20( + .A1(JumpOrBranchPC[15]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_13), .ZN(n_0_0_4) + ); + INV_X1_LVT i_0_0_19( + .A(n_0_0_4), .ZN(thePC_n_45) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[15] ( + .CK(clk_25mhz), .D(thePC_n_45), .Q(CurrentPC[15]), .QN(), .SE(scan_en), .SI(CurrentPC[16]) + ); + AOI22_X1_LVT i_0_0_18( + .A1(JumpOrBranchPC[14]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_12), .ZN(n_0_0_3) + ); + INV_X1_LVT i_0_0_17( + .A(n_0_0_3), .ZN(thePC_n_44) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[14] ( + .CK(clk_25mhz), .D(thePC_n_44), .Q(CurrentPC[14]), .QN(), .SE(scan_en), .SI(CurrentPC[15]) + ); + AOI22_X1_LVT i_0_0_16( + .A1(JumpOrBranchPC[13]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_11), .ZN(n_0_0_2) + ); + INV_X1_LVT i_0_0_15( + .A(n_0_0_2), .ZN(thePC_n_43) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[13] ( + .CK(clk_25mhz), .D(thePC_n_43), .Q(CurrentPC[13]), .QN(), .SE(scan_en), .SI(CurrentPC[14]) + ); + MUX2_X1_LVT i_0_0_65( + .A(thePC_n_10), .B(JumpOrBranchPC[12]), .S(JumpOrBranch), .Z(NextPC[12]) + ); + AND2_X1_LVT i_0_0_14( + .A1(NextPC[12]), .A2(btn[0]), .ZN(thePC_n_42) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[12] ( + .CK(clk_25mhz), .D(thePC_n_42), .Q(CurrentPC[12]), .QN(), .SE(scan_en), .SI(CurrentPC[13]) + ); + MUX2_X1_LVT i_0_0_64( + .A(thePC_n_9), .B(JumpOrBranchPC[11]), .S(JumpOrBranch), .Z(NextPC[11]) + ); + AND2_X1_LVT i_0_0_13( + .A1(NextPC[11]), .A2(btn[0]), .ZN(thePC_n_41) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[11] ( + .CK(clk_25mhz), .D(thePC_n_41), .Q(CurrentPC[11]), .QN(), .SE(scan_en), .SI(CurrentPC[12]) + ); + MUX2_X1_LVT i_0_0_63( + .A(thePC_n_8), .B(JumpOrBranchPC[10]), .S(JumpOrBranch), .Z(NextPC[10]) + ); + AND2_X1_LVT i_0_0_12( + .A1(NextPC[10]), .A2(btn[0]), .ZN(thePC_n_40) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[10] ( + .CK(clk_25mhz), .D(thePC_n_40), .Q(CurrentPC[10]), .QN(), .SE(scan_en), .SI(CurrentPC[11]) + ); + MUX2_X1_LVT i_0_0_62( + .A(thePC_n_7), .B(JumpOrBranchPC[9]), .S(JumpOrBranch), .Z(NextPC[9]) + ); + AND2_X1_LVT i_0_0_11( + .A1(NextPC[9]), .A2(btn[0]), .ZN(thePC_n_39) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[9] ( + .CK(clk_25mhz), .D(thePC_n_39), .Q(CurrentPC[9]), .QN(), .SE(scan_en), .SI(CurrentPC[10]) + ); + MUX2_X1_LVT i_0_0_61( + .A(thePC_n_6), .B(JumpOrBranchPC[8]), .S(JumpOrBranch), .Z(NextPC[8]) + ); + AND2_X1_LVT i_0_0_10( + .A1(NextPC[8]), .A2(btn[0]), .ZN(thePC_n_38) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[8] ( + .CK(clk_25mhz), .D(thePC_n_38), .Q(CurrentPC[8]), .QN(), .SE(scan_en), .SI(CurrentPC[9]) + ); + AND2_X1_LVT i_0_0_9( + .A1(led[7]), .A2(btn[0]), .ZN(thePC_n_37) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[7] ( + .CK(clk_25mhz), .D(thePC_n_37), .Q(CurrentPC[7]), .QN(), .SE(scan_en), .SI(CurrentPC[8]) + ); + MUX2_X1_LVT i_0_0_59( + .A(thePC_n_4), .B(JumpOrBranchPC[6]), .S(JumpOrBranch), .Z(led[6]) + ); + AND2_X1_LVT i_0_0_8( + .A1(led[6]), .A2(btn[0]), .ZN(thePC_n_36) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[6] ( + .CK(clk_25mhz), .D(thePC_n_36), .Q(CurrentPC[6]), .QN(), .SE(scan_en), .SI(CurrentPC[7]) + ); + MUX2_X1_LVT i_0_0_58( + .A(thePC_n_3), .B(JumpOrBranchPC[5]), .S(JumpOrBranch), .Z(led[5]) + ); + AND2_X1_LVT i_0_0_7( + .A1(led[5]), .A2(btn[0]), .ZN(thePC_n_35) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[5] ( + .CK(clk_25mhz), .D(thePC_n_35), .Q(CurrentPC[5]), .QN(), .SE(scan_en), .SI(CurrentPC[6]) + ); + MUX2_X1_LVT i_0_0_57( + .A(thePC_n_2), .B(JumpOrBranchPC[4]), .S(JumpOrBranch), .Z(led[4]) + ); + AND2_X1_LVT i_0_0_6( + .A1(led[4]), .A2(btn[0]), .ZN(thePC_n_34) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[4] ( + .CK(clk_25mhz), .D(thePC_n_34), .Q(CurrentPC[4]), .QN(), .SE(scan_en), .SI(CurrentPC[5]) + ); + MUX2_X1_LVT i_0_0_56( + .A(thePC_n_1), .B(JumpOrBranchPC[3]), .S(JumpOrBranch), .Z(led[3]) + ); + AND2_X1_LVT i_0_0_5( + .A1(led[3]), .A2(btn[0]), .ZN(thePC_n_33) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[3] ( + .CK(clk_25mhz), .D(thePC_n_33), .Q(CurrentPC[3]), .QN(), .SE(scan_en), .SI(CurrentPC[4]) + ); + INV_X1_LVT thePC_i_0_29( + .A(CurrentPC[2]), .ZN(thePC_n_0) + ); + MUX2_X1_LVT i_0_0_55( + .A(thePC_n_0), .B(JumpOrBranchPC[2]), .S(JumpOrBranch), .Z(led[2]) + ); + AND2_X1_LVT i_0_0_4( + .A1(led[2]), .A2(btn[0]), .ZN(thePC_n_32) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[2] ( + .CK(clk_25mhz), .D(thePC_n_32), .Q(CurrentPC[2]), .QN(), .SE(scan_en), .SI(CurrentPC[3]) + ); + HA_X1_LVT thePC_i_0_0( + .A(CurrentPC[3]), .B(CurrentPC[2]), .CO(thePC_i_0_n_0), .S(thePC_n_1) + ); + HA_X1_LVT thePC_i_0_1( + .A(CurrentPC[4]), .B(thePC_i_0_n_0), .CO(thePC_i_0_n_1), .S(thePC_n_2) + ); + HA_X1_LVT thePC_i_0_2( + .A(CurrentPC[5]), .B(thePC_i_0_n_1), .CO(thePC_i_0_n_2), .S(thePC_n_3) + ); + HA_X1_LVT thePC_i_0_3( + .A(CurrentPC[6]), .B(thePC_i_0_n_2), .CO(thePC_i_0_n_3), .S(thePC_n_4) + ); + HA_X1_LVT thePC_i_0_4( + .A(CurrentPC[7]), .B(thePC_i_0_n_3), .CO(thePC_i_0_n_4), .S(thePC_n_5) + ); + HA_X1_LVT thePC_i_0_5( + .A(CurrentPC[8]), .B(thePC_i_0_n_4), .CO(thePC_i_0_n_5), .S(thePC_n_6) + ); + HA_X1_LVT thePC_i_0_6( + .A(CurrentPC[9]), .B(thePC_i_0_n_5), .CO(thePC_i_0_n_6), .S(thePC_n_7) + ); + HA_X1_LVT thePC_i_0_7( + .A(CurrentPC[10]), .B(thePC_i_0_n_6), .CO(thePC_i_0_n_7), .S(thePC_n_8) + ); + HA_X1_LVT thePC_i_0_8( + .A(CurrentPC[11]), .B(thePC_i_0_n_7), .CO(thePC_i_0_n_8), .S(thePC_n_9) + ); + HA_X1_LVT thePC_i_0_9( + .A(CurrentPC[12]), .B(thePC_i_0_n_8), .CO(thePC_i_0_n_9), .S(thePC_n_10) + ); + HA_X1_LVT thePC_i_0_11( + .A(CurrentPC[13]), .B(thePC_i_0_n_9), .CO(thePC_i_0_n_10), .S(thePC_n_11) + ); + HA_X1_LVT thePC_i_0_12( + .A(CurrentPC[14]), .B(thePC_i_0_n_10), .CO(thePC_i_0_n_11), .S(thePC_n_12) + ); + HA_X1_LVT thePC_i_0_13( + .A(CurrentPC[15]), .B(thePC_i_0_n_11), .CO(thePC_i_0_n_12), .S(thePC_n_13) + ); + HA_X1_LVT thePC_i_0_14( + .A(CurrentPC[16]), .B(thePC_i_0_n_12), .CO(thePC_i_0_n_13), .S(thePC_n_14) + ); + HA_X1_LVT thePC_i_0_15( + .A(CurrentPC[17]), .B(thePC_i_0_n_13), .CO(thePC_i_0_n_14), .S(thePC_n_15) + ); + HA_X1_LVT thePC_i_0_16( + .A(CurrentPC[18]), .B(thePC_i_0_n_14), .CO(thePC_i_0_n_15), .S(thePC_n_16) + ); + HA_X1_LVT thePC_i_0_17( + .A(CurrentPC[19]), .B(thePC_i_0_n_15), .CO(thePC_i_0_n_16), .S(thePC_n_17) + ); + HA_X1_LVT thePC_i_0_10( + .A(CurrentPC[20]), .B(thePC_i_0_n_16), .CO(thePC_i_0_n_17), .S(thePC_n_18) + ); + HA_X1_LVT thePC_i_0_18( + .A(CurrentPC[21]), .B(thePC_i_0_n_17), .CO(thePC_i_0_n_18), .S(thePC_n_19) + ); + HA_X1_LVT thePC_i_0_19( + .A(CurrentPC[22]), .B(thePC_i_0_n_18), .CO(thePC_i_0_n_19), .S(thePC_n_20) + ); + HA_X1_LVT thePC_i_0_20( + .A(CurrentPC[23]), .B(thePC_i_0_n_19), .CO(thePC_i_0_n_20), .S(thePC_n_21) + ); + HA_X1_LVT thePC_i_0_21( + .A(CurrentPC[24]), .B(thePC_i_0_n_20), .CO(thePC_i_0_n_21), .S(thePC_n_22) + ); + HA_X1_LVT thePC_i_0_22( + .A(CurrentPC[25]), .B(thePC_i_0_n_21), .CO(thePC_i_0_n_22), .S(thePC_n_23) + ); + HA_X1_LVT thePC_i_0_23( + .A(CurrentPC[26]), .B(thePC_i_0_n_22), .CO(thePC_i_0_n_23), .S(thePC_n_24) + ); + HA_X1_LVT thePC_i_0_24( + .A(CurrentPC[27]), .B(thePC_i_0_n_23), .CO(thePC_i_0_n_24), .S(thePC_n_25) + ); + HA_X1_LVT thePC_i_0_25( + .A(CurrentPC[28]), .B(thePC_i_0_n_24), .CO(thePC_i_0_n_25), .S(thePC_n_26) + ); + HA_X1_LVT thePC_i_0_26( + .A(CurrentPC[29]), .B(thePC_i_0_n_25), .CO(thePC_i_0_n_26), .S(thePC_n_27) + ); + HA_X1_LVT thePC_i_0_27( + .A(CurrentPC[30]), .B(thePC_i_0_n_26), .CO(thePC_i_0_n_27), .S(thePC_n_28) + ); + XOR2_X1_LVT thePC_i_0_28( + .A(CurrentPC[31]), .B(thePC_i_0_n_27), .Z(thePC_n_29) + ); + AOI22_X1_LVT i_0_0_52( + .A1(JumpOrBranchPC[31]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_29), .ZN(n_0_0_20) + ); + INV_X1_LVT i_0_0_51( + .A(n_0_0_20), .ZN(thePC_n_61) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[31] ( + .CK(clk_25mhz), .D(thePC_n_61), .Q(CurrentPC[31]), .QN(), .SE(scan_en), .SI(CurrentPC[2]) + ); + AOI22_X1_LVT i_0_0_3( + .A1(JumpOrBranchPC[1]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(CurrentPC[1]), + .ZN(n_0_0_1) + ); + INV_X1_LVT i_0_0_2( + .A(n_0_0_1), .ZN(thePC_n_31) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[1] ( + .CK(clk_25mhz), .D(thePC_n_31), .Q(CurrentPC[1]), .QN(), .SE(scan_en), .SI(CurrentPC[31]) + ); + AOI22_X1_LVT i_0_0_1( + .A1(JumpOrBranchPC[0]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(CurrentPC[0]), + .ZN(n_0_0_0) + ); + INV_X1_LVT i_0_0_0( + .A(n_0_0_0), .ZN(thePC_n_30) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[0] ( + .CK(clk_25mhz), .D(thePC_n_30), .Q(CurrentPC[0]), .QN(), .SE(scan_en), .SI(CurrentPC[1]) + ); + reg_file theRegisters( + .Rs1({Instruction[19], Instruction[18], Instruction[17], + Instruction[16], Instruction[15]}), .Rs2({Instruction[24], + Instruction[23], Instruction[22], Instruction[21], Instruction[20]}), .Rd({ + Instruction[11], Instruction[10], Instruction[9], Instruction[8], + Instruction[7]}), .RRs1(RRs1), .RRs2(RRs2), .WRd(WRd), .WrReg(WrReg), .reset(reset), + .clk(clk_25mhz), .dftIn(scan_en), .ts_intno31(CurrentPC[0]), .ts_no1050(ts_no1050), + .ts_no1051(ts_no1051), .ts_no1053(ts_no1053), .ts_no1054(ts_no1054), .ts_extsi1226(SI_2), + .ts_extsi1227(SI_3), .ts_extsi1228(SI_4) + ); + main_mem theMem( + .clk(clk_25mhz), .reset(reset), .DAddr({uc_0, uc_1, uc_2, uc_3, uc_4, + uc_5, uc_6, uc_7, uc_8, uc_9, uc_10, uc_11, uc_12, uc_13, uc_14, uc_15, + uc_16, uc_17, uc_18, DAddr[12], DAddr[11], DAddr[10], DAddr[9], + DAddr[8], DAddr[7], DAddr[6], DAddr[5], DAddr[4], DAddr[3], DAddr[2], + DAddr[1], DAddr[0]}), .IAddr({uc_19, uc_20, uc_21, uc_22, uc_23, uc_24, + uc_25, uc_26, uc_27, uc_28, uc_29, uc_30, uc_31, uc_32, uc_33, uc_34, + uc_35, uc_36, uc_37, NextPC[12], NextPC[11], NextPC[10], NextPC[9], + NextPC[8], led[7], led[6], led[5], led[4], led[3], led[2], uc_38, uc_39}), + .DWData(RRs2), .DRData(RData), .IRData(Instruction), .DWE(led[1]), .DWidth(DWidth) + ); + decoder theDecoder( + .CurrentPC(CurrentPC), .JumpOrBranchPC(JumpOrBranchPC), .JumpOrBranch(JumpOrBranch), + .DAddr({uc_40, uc_41, uc_42, uc_43, uc_44, uc_45, uc_46, uc_47, uc_48, + uc_49, uc_50, uc_51, uc_52, uc_53, uc_54, uc_55, uc_56, uc_57, uc_58, + DAddr[12], DAddr[11], DAddr[10], DAddr[9], DAddr[8], DAddr[7], DAddr[6], + DAddr[5], DAddr[4], DAddr[3], DAddr[2], DAddr[1], DAddr[0]}), .WData(), .RData(RData), + .Instruction(Instruction), .WrMem(led[1]), .DWidth(DWidth), .Rs1(), .Rs2(), + .Rd(), .RRs1(RRs1), .RRs2(RRs2), .WRd(WRd), .WrReg(WrReg), .Illegal(led[0]) + ); + MUX2_X1_LVT i_0_0_60( + .A(thePC_n_5), .B(JumpOrBranchPC[7]), .S(JumpOrBranch), .Z(led[7]) + ); + CLKBUF_X3_LVT tessent_persistent_cell_buf_extsi1225_i( + .A(SI_1), .Z(ts_pbuf_extsi1225_) + ); +endmodule + diff --git a/oasys.tessent.00/Scan_0/scan.do b/oasys.tessent.00/Scan_0/scan.do new file mode 100644 index 0000000..adbba2b --- /dev/null +++ b/oasys.tessent.00/Scan_0/scan.do @@ -0,0 +1,57 @@ +set_context dft -scan -no_rtl -design_id Scan_0 +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_low_temp_ccs.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_low_temp_ccs.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/PLL.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/IO.fslib +set_module_matching_options -suffix_pattern_list {{[_]+[0-9]+[_]+[0-9]+}} -regexp -append +set_module_matching_options -suffix_pattern_list {{[_]+[A-Z]+}} -regexp -append +set_module_matching_options -suffix_pattern_list {{[_]+[0-9]+[_]+[0-9]+[_]+[A-Z]+}} -regexp -append +read_verilog /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/Scan_0/oasys_netlist.v +set_tsdb_output_directory /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/tsdb_outdir +if { [info exists ::env(OASYS_TCD_SCAN_FOLDER)] } { +set_design_sources -format tcd_scan -Y $::env(OASYS_TCD_SCAN_FOLDER) -extensions tcd_scan +} +read_sdc /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/Scan_0/oasys.sdc +set_current_design cpu -show_elaboration_warnings +set_design_level physical_block +set_shift_register_identification off + +add_nonscan_instances -instances {{/theMem/\IRData_reg[31] } {/theMem/\IRData_reg[30] } {/theMem/\IRData_reg[29] } {/theMem/\IRData_reg[28] } {/theMem/\IRData_reg[27] } {/theMem/\IRData_reg[26] } {/theMem/\IRData_reg[25] } {/theMem/\IRData_reg[24] } {/theMem/\IRData_reg[23] } {/theMem/\IRData_reg[22] } {/theMem/\IRData_reg[21] } {/theMem/\IRData_reg[20] } {/theMem/\IRData_reg[19] } {/theMem/\IRData_reg[18] } {/theMem/\IRData_reg[17] } {/theMem/\IRData_reg[16] } {/theMem/\IRData_reg[15] } {/theMem/\IRData_reg[14] } {/theMem/\IRData_reg[13] } {/theMem/\IRData_reg[12] } {/theMem/\IRData_reg[11] } {/theMem/\IRData_reg[10] } {/theMem/\IRData_reg[9] } {/theMem/\IRData_reg[8] } {/theMem/\IRData_reg[7] } {/theMem/\IRData_reg[6] } {/theMem/\IRData_reg[5] } {/theMem/\IRData_reg[4] } {/theMem/\IRData_reg[3] } {/theMem/\IRData_reg[2] } {/theMem/\IRData_reg[1] } {/theMem/\IRData_reg[0] } {/theMem/\mem_addr_reg[10] } {/theMem/\mem_addr_reg[9] } {/theMem/\mem_addr_reg[8] } {/theMem/\mem_addr_reg[7] } {/theMem/\mem_addr_reg[6] } {/theMem/\mem_addr_reg[5] } {/theMem/\mem_addr_reg[4] } {/theMem/\mem_addr_reg[3] } {/theMem/\mem_addr_reg[2] } {/theMem/\mem_addr_reg[1] } {/theMem/\mem_addr_reg[0] } {/theMem/\drTmp_reg[31] } {/theMem/\drTmp_reg[30] } {/theMem/\drTmp_reg[29] } {/theMem/\drTmp_reg[28] } {/theMem/\drTmp_reg[27] } {/theMem/\drTmp_reg[26] } {/theMem/\drTmp_reg[25] } {/theMem/\drTmp_reg[24] } {/theMem/\drTmp_reg[23] } {/theMem/\drTmp_reg[22] } {/theMem/\drTmp_reg[21] } {/theMem/\drTmp_reg[20] } {/theMem/\drTmp_reg[19] } {/theMem/\drTmp_reg[18] } {/theMem/\drTmp_reg[17] } {/theMem/\drTmp_reg[16] } {/theMem/\drTmp_reg[15] } {/theMem/\drTmp_reg[14] } {/theMem/\drTmp_reg[13] } {/theMem/\drTmp_reg[12] } {/theMem/\drTmp_reg[11] } {/theMem/\drTmp_reg[10] } {/theMem/\drTmp_reg[9] } {/theMem/\drTmp_reg[8] } {/theMem/\drTmp_reg[7] } {/theMem/\drTmp_reg[6] } {/theMem/\drTmp_reg[5] } {/theMem/\drTmp_reg[4] } {/theMem/\drTmp_reg[3] } {/theMem/\drTmp_reg[2] } {/theMem/\drTmp_reg[1] } {/theMem/\drTmp_reg[0] } {/theMem/\mem_wdata_reg[31] } {/theMem/\mem_wdata_reg[30] } {/theMem/\mem_wdata_reg[29] } {/theMem/\mem_wdata_reg[28] } {/theMem/\mem_wdata_reg[27] } {/theMem/\mem_wdata_reg[26] } {/theMem/\mem_wdata_reg[25] } {/theMem/\mem_wdata_reg[24] } {/theMem/\mem_wdata_reg[23] } {/theMem/\mem_wdata_reg[22] } {/theMem/\mem_wdata_reg[21] } {/theMem/\mem_wdata_reg[20] } {/theMem/\mem_wdata_reg[19] } {/theMem/\mem_wdata_reg[18] } {/theMem/\mem_wdata_reg[17] } {/theMem/\mem_wdata_reg[16] } {/theMem/\mem_wdata_reg[15] } {/theMem/\mem_wdata_reg[14] } {/theMem/\mem_wdata_reg[13] } {/theMem/\mem_wdata_reg[12] } {/theMem/\mem_wdata_reg[11] } {/theMem/\mem_wdata_reg[10] } {/theMem/\mem_wdata_reg[9] } {/theMem/\mem_wdata_reg[8] } {/theMem/\mem_wdata_reg[7] } {/theMem/\mem_wdata_reg[6] } {/theMem/\mem_wdata_reg[5] } {/theMem/\mem_wdata_reg[4] } {/theMem/\mem_wdata_reg[3] } {/theMem/\mem_wdata_reg[2] } {/theMem/\mem_wdata_reg[1] } {/theMem/\mem_wdata_reg[0] } } +if {[catch {get_clocks clk_25mhz > /dev/null }] && +[catch {get_dft_signal clk_25mhz > /dev/null }]} { +add_clocks 0 { clk_25mhz } +} + +set_scan_enable scan_en -active high +add_input_constraints btn[0] -C1 +set_scan_enable scan_en -active high -cluster_name scanChain_1 +set_scan_enable scan_en -active high -cluster_name scanChain_2 +set_scan_enable scan_en -active high -cluster_name scanChain_3 +set_scan_enable scan_en -active high -cluster_name scanChain_4 + +add_black_boxes -modules { MemGen_16_10 } +set_scan_insertion_options -single_clock_edge_chains on -si_port_format {oas_ts_si[%d]} -so_port_format {oas_ts_so[%d]} +set_system_mode analysis +report_drc_rules + +create_scan_chain_family scanChain_1 -include_elements {{/\thePC_CurrentPC_reg[0] } {/\thePC_CurrentPC_reg[10] } {/\thePC_CurrentPC_reg[11] } {/\thePC_CurrentPC_reg[12] } {/\thePC_CurrentPC_reg[13] } {/\thePC_CurrentPC_reg[14] } {/\thePC_CurrentPC_reg[15] } {/\thePC_CurrentPC_reg[16] } {/\thePC_CurrentPC_reg[17] } {/\thePC_CurrentPC_reg[18] } {/\thePC_CurrentPC_reg[19] } {/\thePC_CurrentPC_reg[1] } {/\thePC_CurrentPC_reg[20] } {/\thePC_CurrentPC_reg[21] } {/\thePC_CurrentPC_reg[22] } {/\thePC_CurrentPC_reg[23] } {/\thePC_CurrentPC_reg[24] } {/\thePC_CurrentPC_reg[25] } {/\thePC_CurrentPC_reg[26] } {/\thePC_CurrentPC_reg[27] } {/\thePC_CurrentPC_reg[28] } {/\thePC_CurrentPC_reg[29] } {/\thePC_CurrentPC_reg[2] } {/\thePC_CurrentPC_reg[30] } {/\thePC_CurrentPC_reg[31] } {/\thePC_CurrentPC_reg[3] } {/\thePC_CurrentPC_reg[4] } {/\thePC_CurrentPC_reg[5] } {/\thePC_CurrentPC_reg[6] } {/\thePC_CurrentPC_reg[7] } {/\thePC_CurrentPC_reg[8] } {/\thePC_CurrentPC_reg[9] } {/theRegisters/\registers_reg[10][0] } {/theRegisters/\registers_reg[10][10] } {/theRegisters/\registers_reg[10][11] } {/theRegisters/\registers_reg[10][12] } {/theRegisters/\registers_reg[10][13] } {/theRegisters/\registers_reg[10][14] } {/theRegisters/\registers_reg[10][15] } {/theRegisters/\registers_reg[10][16] } {/theRegisters/\registers_reg[10][17] } {/theRegisters/\registers_reg[10][18] } {/theRegisters/\registers_reg[10][19] } {/theRegisters/\registers_reg[10][1] } {/theRegisters/\registers_reg[10][20] } {/theRegisters/\registers_reg[10][21] } {/theRegisters/\registers_reg[10][22] } {/theRegisters/\registers_reg[10][23] } {/theRegisters/\registers_reg[10][24] } {/theRegisters/\registers_reg[10][25] } {/theRegisters/\registers_reg[10][26] } {/theRegisters/\registers_reg[10][27] } {/theRegisters/\registers_reg[10][28] } {/theRegisters/\registers_reg[10][29] } {/theRegisters/\registers_reg[10][2] } {/theRegisters/\registers_reg[10][30] } {/theRegisters/\registers_reg[10][31] } {/theRegisters/\registers_reg[10][3] } {/theRegisters/\registers_reg[10][4] } {/theRegisters/\registers_reg[10][5] } {/theRegisters/\registers_reg[10][6] } {/theRegisters/\registers_reg[10][7] } {/theRegisters/\registers_reg[10][8] } {/theRegisters/\registers_reg[10][9] } {/theRegisters/\registers_reg[11][0] } {/theRegisters/\registers_reg[11][10] } {/theRegisters/\registers_reg[11][11] } {/theRegisters/\registers_reg[11][12] } {/theRegisters/\registers_reg[11][13] } {/theRegisters/\registers_reg[11][14] } {/theRegisters/\registers_reg[11][15] } {/theRegisters/\registers_reg[11][16] } {/theRegisters/\registers_reg[11][17] } {/theRegisters/\registers_reg[11][18] } {/theRegisters/\registers_reg[11][19] } {/theRegisters/\registers_reg[11][1] } {/theRegisters/\registers_reg[11][20] } {/theRegisters/\registers_reg[11][21] } {/theRegisters/\registers_reg[11][22] } {/theRegisters/\registers_reg[11][23] } {/theRegisters/\registers_reg[11][24] } {/theRegisters/\registers_reg[11][25] } {/theRegisters/\registers_reg[11][26] } {/theRegisters/\registers_reg[11][27] } {/theRegisters/\registers_reg[11][28] } {/theRegisters/\registers_reg[11][29] } {/theRegisters/\registers_reg[11][2] } {/theRegisters/\registers_reg[11][30] } {/theRegisters/\registers_reg[11][31] } {/theRegisters/\registers_reg[11][3] } {/theRegisters/\registers_reg[11][4] } {/theRegisters/\registers_reg[11][5] } {/theRegisters/\registers_reg[11][6] } {/theRegisters/\registers_reg[11][7] } {/theRegisters/\registers_reg[11][8] } {/theRegisters/\registers_reg[11][9] } {/theRegisters/\registers_reg[12][0] } {/theRegisters/\registers_reg[12][10] } {/theRegisters/\registers_reg[12][11] } {/theRegisters/\registers_reg[12][12] } {/theRegisters/\registers_reg[12][13] } {/theRegisters/\registers_reg[12][14] } {/theRegisters/\registers_reg[12][15] } {/theRegisters/\registers_reg[12][16] } {/theRegisters/\registers_reg[12][17] } {/theRegisters/\registers_reg[12][18] } {/theRegisters/\registers_reg[12][19] } {/theRegisters/\registers_reg[12][1] } {/theRegisters/\registers_reg[12][20] } {/theRegisters/\registers_reg[12][21] } {/theRegisters/\registers_reg[12][22] } {/theRegisters/\registers_reg[12][23] } {/theRegisters/\registers_reg[12][24] } {/theRegisters/\registers_reg[12][25] } {/theRegisters/\registers_reg[12][26] } {/theRegisters/\registers_reg[12][27] } {/theRegisters/\registers_reg[12][28] } {/theRegisters/\registers_reg[12][29] } {/theRegisters/\registers_reg[12][2] } {/theRegisters/\registers_reg[12][30] } {/theRegisters/\registers_reg[12][31] } {/theRegisters/\registers_reg[12][3] } {/theRegisters/\registers_reg[12][4] } {/theRegisters/\registers_reg[12][5] } {/theRegisters/\registers_reg[12][6] } {/theRegisters/\registers_reg[12][7] } {/theRegisters/\registers_reg[12][8] } {/theRegisters/\registers_reg[12][9] } {/theRegisters/\registers_reg[13][0] } {/theRegisters/\registers_reg[13][10] } {/theRegisters/\registers_reg[13][11] } {/theRegisters/\registers_reg[13][12] } {/theRegisters/\registers_reg[13][13] } {/theRegisters/\registers_reg[13][14] } {/theRegisters/\registers_reg[13][15] } {/theRegisters/\registers_reg[13][16] } {/theRegisters/\registers_reg[13][17] } {/theRegisters/\registers_reg[13][18] } {/theRegisters/\registers_reg[13][19] } {/theRegisters/\registers_reg[13][1] } {/theRegisters/\registers_reg[13][20] } {/theRegisters/\registers_reg[13][21] } {/theRegisters/\registers_reg[13][22] } {/theRegisters/\registers_reg[13][23] } {/theRegisters/\registers_reg[13][24] } {/theRegisters/\registers_reg[13][25] } {/theRegisters/\registers_reg[13][26] } {/theRegisters/\registers_reg[13][27] } {/theRegisters/\registers_reg[13][28] } {/theRegisters/\registers_reg[13][29] } {/theRegisters/\registers_reg[13][2] } {/theRegisters/\registers_reg[13][30] } {/theRegisters/\registers_reg[13][31] } {/theRegisters/\registers_reg[13][3] } {/theRegisters/\registers_reg[13][4] } {/theRegisters/\registers_reg[13][5] } {/theRegisters/\registers_reg[13][6] } {/theRegisters/\registers_reg[13][7] } {/theRegisters/\registers_reg[13][8] } {/theRegisters/\registers_reg[13][9] } {/theRegisters/\registers_reg[14][0] } {/theRegisters/\registers_reg[14][10] } {/theRegisters/\registers_reg[14][11] } {/theRegisters/\registers_reg[14][12] } {/theRegisters/\registers_reg[14][13] } {/theRegisters/\registers_reg[14][14] } {/theRegisters/\registers_reg[14][15] } {/theRegisters/\registers_reg[14][16] } {/theRegisters/\registers_reg[14][17] } {/theRegisters/\registers_reg[14][18] } {/theRegisters/\registers_reg[14][19] } {/theRegisters/\registers_reg[14][1] } {/theRegisters/\registers_reg[14][20] } {/theRegisters/\registers_reg[14][21] } {/theRegisters/\registers_reg[14][22] } {/theRegisters/\registers_reg[14][23] } {/theRegisters/\registers_reg[14][24] } {/theRegisters/\registers_reg[14][25] } {/theRegisters/\registers_reg[14][26] } {/theRegisters/\registers_reg[14][27] } {/theRegisters/\registers_reg[14][28] } {/theRegisters/\registers_reg[14][29] } {/theRegisters/\registers_reg[14][2] } {/theRegisters/\registers_reg[14][30] } {/theRegisters/\registers_reg[14][31] } {/theRegisters/\registers_reg[14][3] } {/theRegisters/\registers_reg[14][4] } {/theRegisters/\registers_reg[14][5] } {/theRegisters/\registers_reg[14][6] } {/theRegisters/\registers_reg[14][7] } {/theRegisters/\registers_reg[14][8] } {/theRegisters/\registers_reg[14][9] } {/theRegisters/\registers_reg[15][0] } {/theRegisters/\registers_reg[15][10] } {/theRegisters/\registers_reg[15][11] } {/theRegisters/\registers_reg[15][12] } {/theRegisters/\registers_reg[15][13] } {/theRegisters/\registers_reg[15][14] } {/theRegisters/\registers_reg[15][15] } {/theRegisters/\registers_reg[15][16] } {/theRegisters/\registers_reg[15][17] } {/theRegisters/\registers_reg[15][18] } {/theRegisters/\registers_reg[15][19] } {/theRegisters/\registers_reg[15][1] } {/theRegisters/\registers_reg[15][20] } {/theRegisters/\registers_reg[15][21] } {/theRegisters/\registers_reg[15][22] } {/theRegisters/\registers_reg[15][23] } {/theRegisters/\registers_reg[15][24] } {/theRegisters/\registers_reg[15][25] } {/theRegisters/\registers_reg[15][26] } {/theRegisters/\registers_reg[15][27] } {/theRegisters/\registers_reg[15][28] } {/theRegisters/\registers_reg[15][29] } {/theRegisters/\registers_reg[15][2] } {/theRegisters/\registers_reg[15][30] } {/theRegisters/\registers_reg[15][31] } {/theRegisters/\registers_reg[15][3] } {/theRegisters/\registers_reg[15][4] } {/theRegisters/\registers_reg[15][5] } {/theRegisters/\registers_reg[15][6] } {/theRegisters/\registers_reg[15][7] } {/theRegisters/\registers_reg[15][8] } {/theRegisters/\registers_reg[15][9] } {/theRegisters/\registers_reg[16][0] } {/theRegisters/\registers_reg[16][10] } {/theRegisters/\registers_reg[16][11] } {/theRegisters/\registers_reg[16][12] } {/theRegisters/\registers_reg[16][13] } {/theRegisters/\registers_reg[16][14] } {/theRegisters/\registers_reg[16][15] } {/theRegisters/\registers_reg[16][16] } {/theRegisters/\registers_reg[16][17] } {/theRegisters/\registers_reg[16][18] } {/theRegisters/\registers_reg[16][19] } {/theRegisters/\registers_reg[16][1] } {/theRegisters/\registers_reg[16][20] } {/theRegisters/\registers_reg[16][21] } {/theRegisters/\registers_reg[16][22] } {/theRegisters/\registers_reg[16][23] } {/theRegisters/\registers_reg[16][24] } {/theRegisters/\registers_reg[16][25] } {/theRegisters/\registers_reg[16][26] } {/theRegisters/\registers_reg[16][27] } {/theRegisters/\registers_reg[16][28] } {/theRegisters/\registers_reg[16][29] } {/theRegisters/\registers_reg[16][2] } {/theRegisters/\registers_reg[16][30] } {/theRegisters/\registers_reg[16][31] } {/theRegisters/\registers_reg[16][3] } {/theRegisters/\registers_reg[16][4] } {/theRegisters/\registers_reg[16][5] } {/theRegisters/\registers_reg[16][6] } {/theRegisters/\registers_reg[16][7] } {/theRegisters/\registers_reg[16][8] } {/theRegisters/\registers_reg[16][9] } } -si_connections {SI_1 } -so_connections {SO_1 } -chain_count 1 +create_scan_chain_family scanChain_2 -include_elements {{/theRegisters/\registers_reg[17][0] } {/theRegisters/\registers_reg[17][10] } {/theRegisters/\registers_reg[17][11] } {/theRegisters/\registers_reg[17][12] } {/theRegisters/\registers_reg[17][13] } {/theRegisters/\registers_reg[17][14] } {/theRegisters/\registers_reg[17][15] } {/theRegisters/\registers_reg[17][16] } {/theRegisters/\registers_reg[17][17] } {/theRegisters/\registers_reg[17][18] } {/theRegisters/\registers_reg[17][19] } {/theRegisters/\registers_reg[17][1] } {/theRegisters/\registers_reg[17][20] } {/theRegisters/\registers_reg[17][21] } {/theRegisters/\registers_reg[17][22] } {/theRegisters/\registers_reg[17][23] } {/theRegisters/\registers_reg[17][24] } {/theRegisters/\registers_reg[17][25] } {/theRegisters/\registers_reg[17][26] } {/theRegisters/\registers_reg[17][27] } {/theRegisters/\registers_reg[17][28] } {/theRegisters/\registers_reg[17][29] } {/theRegisters/\registers_reg[17][2] } {/theRegisters/\registers_reg[17][30] } {/theRegisters/\registers_reg[17][31] } {/theRegisters/\registers_reg[17][3] } {/theRegisters/\registers_reg[17][4] } {/theRegisters/\registers_reg[17][5] } {/theRegisters/\registers_reg[17][6] } {/theRegisters/\registers_reg[17][7] } {/theRegisters/\registers_reg[17][8] } {/theRegisters/\registers_reg[17][9] } {/theRegisters/\registers_reg[18][0] } {/theRegisters/\registers_reg[18][10] } {/theRegisters/\registers_reg[18][11] } {/theRegisters/\registers_reg[18][12] } {/theRegisters/\registers_reg[18][13] } {/theRegisters/\registers_reg[18][14] } {/theRegisters/\registers_reg[18][15] } {/theRegisters/\registers_reg[18][16] } {/theRegisters/\registers_reg[18][17] } {/theRegisters/\registers_reg[18][18] } {/theRegisters/\registers_reg[18][19] } {/theRegisters/\registers_reg[18][1] } {/theRegisters/\registers_reg[18][20] } {/theRegisters/\registers_reg[18][21] } {/theRegisters/\registers_reg[18][22] } {/theRegisters/\registers_reg[18][23] } {/theRegisters/\registers_reg[18][24] } {/theRegisters/\registers_reg[18][25] } {/theRegisters/\registers_reg[18][26] } {/theRegisters/\registers_reg[18][27] } {/theRegisters/\registers_reg[18][28] } {/theRegisters/\registers_reg[18][29] } {/theRegisters/\registers_reg[18][2] } {/theRegisters/\registers_reg[18][30] } {/theRegisters/\registers_reg[18][31] } {/theRegisters/\registers_reg[18][3] } {/theRegisters/\registers_reg[18][4] } {/theRegisters/\registers_reg[18][5] } {/theRegisters/\registers_reg[18][6] } {/theRegisters/\registers_reg[18][7] } {/theRegisters/\registers_reg[18][8] } {/theRegisters/\registers_reg[18][9] } {/theRegisters/\registers_reg[19][0] } {/theRegisters/\registers_reg[19][10] } {/theRegisters/\registers_reg[19][11] } {/theRegisters/\registers_reg[19][12] } {/theRegisters/\registers_reg[19][13] } {/theRegisters/\registers_reg[19][14] } {/theRegisters/\registers_reg[19][15] } {/theRegisters/\registers_reg[19][16] } {/theRegisters/\registers_reg[19][17] } {/theRegisters/\registers_reg[19][18] } {/theRegisters/\registers_reg[19][19] } {/theRegisters/\registers_reg[19][1] } {/theRegisters/\registers_reg[19][20] } {/theRegisters/\registers_reg[19][21] } {/theRegisters/\registers_reg[19][22] } {/theRegisters/\registers_reg[19][23] } {/theRegisters/\registers_reg[19][24] } {/theRegisters/\registers_reg[19][25] } {/theRegisters/\registers_reg[19][26] } {/theRegisters/\registers_reg[19][27] } {/theRegisters/\registers_reg[19][28] } {/theRegisters/\registers_reg[19][29] } {/theRegisters/\registers_reg[19][2] } {/theRegisters/\registers_reg[19][30] } {/theRegisters/\registers_reg[19][31] } {/theRegisters/\registers_reg[19][3] } {/theRegisters/\registers_reg[19][4] } {/theRegisters/\registers_reg[19][5] } {/theRegisters/\registers_reg[19][6] } {/theRegisters/\registers_reg[19][7] } {/theRegisters/\registers_reg[19][8] } {/theRegisters/\registers_reg[19][9] } {/theRegisters/\registers_reg[1][0] } {/theRegisters/\registers_reg[1][10] } {/theRegisters/\registers_reg[1][11] } {/theRegisters/\registers_reg[1][12] } {/theRegisters/\registers_reg[1][13] } {/theRegisters/\registers_reg[1][14] } {/theRegisters/\registers_reg[1][15] } {/theRegisters/\registers_reg[1][16] } {/theRegisters/\registers_reg[1][17] } {/theRegisters/\registers_reg[1][18] } {/theRegisters/\registers_reg[1][19] } {/theRegisters/\registers_reg[1][1] } {/theRegisters/\registers_reg[1][20] } {/theRegisters/\registers_reg[1][21] } {/theRegisters/\registers_reg[1][22] } {/theRegisters/\registers_reg[1][23] } {/theRegisters/\registers_reg[1][24] } {/theRegisters/\registers_reg[1][25] } {/theRegisters/\registers_reg[1][26] } {/theRegisters/\registers_reg[1][27] } {/theRegisters/\registers_reg[1][28] } {/theRegisters/\registers_reg[1][29] } {/theRegisters/\registers_reg[1][2] } {/theRegisters/\registers_reg[1][30] } {/theRegisters/\registers_reg[1][31] } {/theRegisters/\registers_reg[1][3] } {/theRegisters/\registers_reg[1][4] } {/theRegisters/\registers_reg[1][5] } {/theRegisters/\registers_reg[1][6] } {/theRegisters/\registers_reg[1][7] } {/theRegisters/\registers_reg[1][8] } {/theRegisters/\registers_reg[1][9] } {/theRegisters/\registers_reg[20][0] } {/theRegisters/\registers_reg[20][10] } {/theRegisters/\registers_reg[20][11] } {/theRegisters/\registers_reg[20][12] } {/theRegisters/\registers_reg[20][13] } {/theRegisters/\registers_reg[20][14] } {/theRegisters/\registers_reg[20][15] } {/theRegisters/\registers_reg[20][16] } {/theRegisters/\registers_reg[20][17] } {/theRegisters/\registers_reg[20][18] } {/theRegisters/\registers_reg[20][19] } {/theRegisters/\registers_reg[20][1] } {/theRegisters/\registers_reg[20][20] } {/theRegisters/\registers_reg[20][21] } {/theRegisters/\registers_reg[20][22] } {/theRegisters/\registers_reg[20][23] } {/theRegisters/\registers_reg[20][24] } {/theRegisters/\registers_reg[20][25] } {/theRegisters/\registers_reg[20][26] } {/theRegisters/\registers_reg[20][27] } {/theRegisters/\registers_reg[20][28] } {/theRegisters/\registers_reg[20][29] } {/theRegisters/\registers_reg[20][2] } {/theRegisters/\registers_reg[20][30] } {/theRegisters/\registers_reg[20][31] } {/theRegisters/\registers_reg[20][3] } {/theRegisters/\registers_reg[20][4] } {/theRegisters/\registers_reg[20][5] } {/theRegisters/\registers_reg[20][6] } {/theRegisters/\registers_reg[20][7] } {/theRegisters/\registers_reg[20][8] } {/theRegisters/\registers_reg[20][9] } {/theRegisters/\registers_reg[21][0] } {/theRegisters/\registers_reg[21][10] } {/theRegisters/\registers_reg[21][11] } {/theRegisters/\registers_reg[21][12] } {/theRegisters/\registers_reg[21][13] } {/theRegisters/\registers_reg[21][14] } {/theRegisters/\registers_reg[21][15] } {/theRegisters/\registers_reg[21][16] } {/theRegisters/\registers_reg[21][17] } {/theRegisters/\registers_reg[21][18] } {/theRegisters/\registers_reg[21][19] } {/theRegisters/\registers_reg[21][1] } {/theRegisters/\registers_reg[21][20] } {/theRegisters/\registers_reg[21][21] } {/theRegisters/\registers_reg[21][22] } {/theRegisters/\registers_reg[21][23] } {/theRegisters/\registers_reg[21][24] } {/theRegisters/\registers_reg[21][25] } {/theRegisters/\registers_reg[21][26] } {/theRegisters/\registers_reg[21][27] } {/theRegisters/\registers_reg[21][28] } {/theRegisters/\registers_reg[21][29] } {/theRegisters/\registers_reg[21][2] } {/theRegisters/\registers_reg[21][30] } {/theRegisters/\registers_reg[21][31] } {/theRegisters/\registers_reg[21][3] } {/theRegisters/\registers_reg[21][4] } {/theRegisters/\registers_reg[21][5] } {/theRegisters/\registers_reg[21][6] } {/theRegisters/\registers_reg[21][7] } {/theRegisters/\registers_reg[21][8] } {/theRegisters/\registers_reg[21][9] } {/theRegisters/\registers_reg[22][0] } {/theRegisters/\registers_reg[22][10] } {/theRegisters/\registers_reg[22][11] } {/theRegisters/\registers_reg[22][12] } {/theRegisters/\registers_reg[22][13] } {/theRegisters/\registers_reg[22][14] } {/theRegisters/\registers_reg[22][15] } {/theRegisters/\registers_reg[22][16] } {/theRegisters/\registers_reg[22][17] } {/theRegisters/\registers_reg[22][18] } {/theRegisters/\registers_reg[22][19] } {/theRegisters/\registers_reg[22][1] } {/theRegisters/\registers_reg[22][20] } {/theRegisters/\registers_reg[22][21] } {/theRegisters/\registers_reg[22][22] } {/theRegisters/\registers_reg[22][23] } {/theRegisters/\registers_reg[22][24] } {/theRegisters/\registers_reg[22][25] } {/theRegisters/\registers_reg[22][26] } {/theRegisters/\registers_reg[22][27] } {/theRegisters/\registers_reg[22][28] } {/theRegisters/\registers_reg[22][29] } {/theRegisters/\registers_reg[22][2] } {/theRegisters/\registers_reg[22][30] } {/theRegisters/\registers_reg[22][31] } {/theRegisters/\registers_reg[22][3] } {/theRegisters/\registers_reg[22][4] } {/theRegisters/\registers_reg[22][5] } {/theRegisters/\registers_reg[22][6] } {/theRegisters/\registers_reg[22][7] } {/theRegisters/\registers_reg[22][8] } {/theRegisters/\registers_reg[22][9] } {/theRegisters/\registers_reg[23][0] } {/theRegisters/\registers_reg[23][10] } {/theRegisters/\registers_reg[23][11] } {/theRegisters/\registers_reg[23][12] } {/theRegisters/\registers_reg[23][13] } {/theRegisters/\registers_reg[23][14] } {/theRegisters/\registers_reg[23][15] } {/theRegisters/\registers_reg[23][16] } {/theRegisters/\registers_reg[23][17] } {/theRegisters/\registers_reg[23][18] } {/theRegisters/\registers_reg[23][19] } {/theRegisters/\registers_reg[23][1] } {/theRegisters/\registers_reg[23][20] } {/theRegisters/\registers_reg[23][21] } {/theRegisters/\registers_reg[23][22] } {/theRegisters/\registers_reg[23][23] } {/theRegisters/\registers_reg[23][24] } {/theRegisters/\registers_reg[23][25] } {/theRegisters/\registers_reg[23][26] } {/theRegisters/\registers_reg[23][27] } {/theRegisters/\registers_reg[23][28] } {/theRegisters/\registers_reg[23][29] } {/theRegisters/\registers_reg[23][2] } {/theRegisters/\registers_reg[23][30] } {/theRegisters/\registers_reg[23][31] } {/theRegisters/\registers_reg[23][3] } {/theRegisters/\registers_reg[23][4] } {/theRegisters/\registers_reg[23][5] } {/theRegisters/\registers_reg[23][6] } {/theRegisters/\registers_reg[23][7] } {/theRegisters/\registers_reg[23][8] } {/theRegisters/\registers_reg[23][9] } } -si_connections {SI_2 } -so_connections {SO_2 } -chain_count 1 +create_scan_chain_family scanChain_3 -include_elements {{/theRegisters/\registers_reg[24][0] } {/theRegisters/\registers_reg[24][10] } {/theRegisters/\registers_reg[24][11] } {/theRegisters/\registers_reg[24][12] } {/theRegisters/\registers_reg[24][13] } {/theRegisters/\registers_reg[24][14] } {/theRegisters/\registers_reg[24][15] } {/theRegisters/\registers_reg[24][16] } {/theRegisters/\registers_reg[24][17] } {/theRegisters/\registers_reg[24][18] } {/theRegisters/\registers_reg[24][19] } {/theRegisters/\registers_reg[24][1] } {/theRegisters/\registers_reg[24][20] } {/theRegisters/\registers_reg[24][21] } {/theRegisters/\registers_reg[24][22] } {/theRegisters/\registers_reg[24][23] } {/theRegisters/\registers_reg[24][24] } {/theRegisters/\registers_reg[24][25] } {/theRegisters/\registers_reg[24][26] } {/theRegisters/\registers_reg[24][27] } {/theRegisters/\registers_reg[24][28] } {/theRegisters/\registers_reg[24][29] } {/theRegisters/\registers_reg[24][2] } {/theRegisters/\registers_reg[24][30] } {/theRegisters/\registers_reg[24][31] } {/theRegisters/\registers_reg[24][3] } {/theRegisters/\registers_reg[24][4] } {/theRegisters/\registers_reg[24][5] } {/theRegisters/\registers_reg[24][6] } {/theRegisters/\registers_reg[24][7] } {/theRegisters/\registers_reg[24][8] } {/theRegisters/\registers_reg[24][9] } {/theRegisters/\registers_reg[25][0] } {/theRegisters/\registers_reg[25][10] } {/theRegisters/\registers_reg[25][11] } {/theRegisters/\registers_reg[25][12] } {/theRegisters/\registers_reg[25][13] } {/theRegisters/\registers_reg[25][14] } {/theRegisters/\registers_reg[25][15] } {/theRegisters/\registers_reg[25][16] } {/theRegisters/\registers_reg[25][17] } {/theRegisters/\registers_reg[25][18] } {/theRegisters/\registers_reg[25][19] } {/theRegisters/\registers_reg[25][1] } {/theRegisters/\registers_reg[25][20] } {/theRegisters/\registers_reg[25][21] } {/theRegisters/\registers_reg[25][22] } {/theRegisters/\registers_reg[25][23] } {/theRegisters/\registers_reg[25][24] } {/theRegisters/\registers_reg[25][25] } {/theRegisters/\registers_reg[25][26] } {/theRegisters/\registers_reg[25][27] } {/theRegisters/\registers_reg[25][28] } {/theRegisters/\registers_reg[25][29] } {/theRegisters/\registers_reg[25][2] } {/theRegisters/\registers_reg[25][30] } {/theRegisters/\registers_reg[25][31] } {/theRegisters/\registers_reg[25][3] } {/theRegisters/\registers_reg[25][4] } {/theRegisters/\registers_reg[25][5] } {/theRegisters/\registers_reg[25][6] } {/theRegisters/\registers_reg[25][7] } {/theRegisters/\registers_reg[25][8] } {/theRegisters/\registers_reg[25][9] } {/theRegisters/\registers_reg[26][0] } {/theRegisters/\registers_reg[26][10] } {/theRegisters/\registers_reg[26][11] } {/theRegisters/\registers_reg[26][12] } {/theRegisters/\registers_reg[26][13] } {/theRegisters/\registers_reg[26][14] } {/theRegisters/\registers_reg[26][15] } {/theRegisters/\registers_reg[26][16] } {/theRegisters/\registers_reg[26][17] } {/theRegisters/\registers_reg[26][18] } {/theRegisters/\registers_reg[26][19] } {/theRegisters/\registers_reg[26][1] } {/theRegisters/\registers_reg[26][20] } {/theRegisters/\registers_reg[26][21] } {/theRegisters/\registers_reg[26][22] } {/theRegisters/\registers_reg[26][23] } {/theRegisters/\registers_reg[26][24] } {/theRegisters/\registers_reg[26][25] } {/theRegisters/\registers_reg[26][26] } {/theRegisters/\registers_reg[26][27] } {/theRegisters/\registers_reg[26][28] } {/theRegisters/\registers_reg[26][29] } {/theRegisters/\registers_reg[26][2] } {/theRegisters/\registers_reg[26][30] } {/theRegisters/\registers_reg[26][31] } {/theRegisters/\registers_reg[26][3] } {/theRegisters/\registers_reg[26][4] } {/theRegisters/\registers_reg[26][5] } {/theRegisters/\registers_reg[26][6] } {/theRegisters/\registers_reg[26][7] } {/theRegisters/\registers_reg[26][8] } {/theRegisters/\registers_reg[26][9] } {/theRegisters/\registers_reg[27][0] } {/theRegisters/\registers_reg[27][10] } {/theRegisters/\registers_reg[27][11] } {/theRegisters/\registers_reg[27][12] } {/theRegisters/\registers_reg[27][13] } {/theRegisters/\registers_reg[27][14] } {/theRegisters/\registers_reg[27][15] } {/theRegisters/\registers_reg[27][16] } {/theRegisters/\registers_reg[27][17] } {/theRegisters/\registers_reg[27][18] } {/theRegisters/\registers_reg[27][19] } {/theRegisters/\registers_reg[27][1] } {/theRegisters/\registers_reg[27][20] } {/theRegisters/\registers_reg[27][21] } {/theRegisters/\registers_reg[27][22] } {/theRegisters/\registers_reg[27][23] } {/theRegisters/\registers_reg[27][24] } {/theRegisters/\registers_reg[27][25] } {/theRegisters/\registers_reg[27][26] } {/theRegisters/\registers_reg[27][27] } {/theRegisters/\registers_reg[27][28] } {/theRegisters/\registers_reg[27][29] } {/theRegisters/\registers_reg[27][2] } {/theRegisters/\registers_reg[27][30] } {/theRegisters/\registers_reg[27][31] } {/theRegisters/\registers_reg[27][3] } {/theRegisters/\registers_reg[27][4] } {/theRegisters/\registers_reg[27][5] } {/theRegisters/\registers_reg[27][6] } {/theRegisters/\registers_reg[27][7] } {/theRegisters/\registers_reg[27][8] } {/theRegisters/\registers_reg[27][9] } {/theRegisters/\registers_reg[28][0] } {/theRegisters/\registers_reg[28][10] } {/theRegisters/\registers_reg[28][11] } {/theRegisters/\registers_reg[28][12] } {/theRegisters/\registers_reg[28][13] } {/theRegisters/\registers_reg[28][14] } {/theRegisters/\registers_reg[28][15] } {/theRegisters/\registers_reg[28][16] } {/theRegisters/\registers_reg[28][17] } {/theRegisters/\registers_reg[28][18] } {/theRegisters/\registers_reg[28][19] } {/theRegisters/\registers_reg[28][1] } {/theRegisters/\registers_reg[28][20] } {/theRegisters/\registers_reg[28][21] } {/theRegisters/\registers_reg[28][22] } {/theRegisters/\registers_reg[28][23] } {/theRegisters/\registers_reg[28][24] } {/theRegisters/\registers_reg[28][25] } {/theRegisters/\registers_reg[28][26] } {/theRegisters/\registers_reg[28][27] } {/theRegisters/\registers_reg[28][28] } {/theRegisters/\registers_reg[28][29] } {/theRegisters/\registers_reg[28][2] } {/theRegisters/\registers_reg[28][30] } {/theRegisters/\registers_reg[28][31] } {/theRegisters/\registers_reg[28][3] } {/theRegisters/\registers_reg[28][4] } {/theRegisters/\registers_reg[28][5] } {/theRegisters/\registers_reg[28][6] } {/theRegisters/\registers_reg[28][7] } {/theRegisters/\registers_reg[28][8] } {/theRegisters/\registers_reg[28][9] } {/theRegisters/\registers_reg[29][0] } {/theRegisters/\registers_reg[29][10] } {/theRegisters/\registers_reg[29][11] } {/theRegisters/\registers_reg[29][12] } {/theRegisters/\registers_reg[29][13] } {/theRegisters/\registers_reg[29][14] } {/theRegisters/\registers_reg[29][15] } {/theRegisters/\registers_reg[29][16] } {/theRegisters/\registers_reg[29][17] } {/theRegisters/\registers_reg[29][18] } {/theRegisters/\registers_reg[29][19] } {/theRegisters/\registers_reg[29][1] } {/theRegisters/\registers_reg[29][20] } {/theRegisters/\registers_reg[29][21] } {/theRegisters/\registers_reg[29][22] } {/theRegisters/\registers_reg[29][23] } {/theRegisters/\registers_reg[29][24] } {/theRegisters/\registers_reg[29][25] } {/theRegisters/\registers_reg[29][26] } {/theRegisters/\registers_reg[29][27] } {/theRegisters/\registers_reg[29][28] } {/theRegisters/\registers_reg[29][29] } {/theRegisters/\registers_reg[29][2] } {/theRegisters/\registers_reg[29][30] } {/theRegisters/\registers_reg[29][31] } {/theRegisters/\registers_reg[29][3] } {/theRegisters/\registers_reg[29][4] } {/theRegisters/\registers_reg[29][5] } {/theRegisters/\registers_reg[29][6] } {/theRegisters/\registers_reg[29][7] } {/theRegisters/\registers_reg[29][8] } {/theRegisters/\registers_reg[29][9] } {/theRegisters/\registers_reg[2][0] } {/theRegisters/\registers_reg[2][10] } {/theRegisters/\registers_reg[2][11] } {/theRegisters/\registers_reg[2][12] } {/theRegisters/\registers_reg[2][13] } {/theRegisters/\registers_reg[2][14] } {/theRegisters/\registers_reg[2][15] } {/theRegisters/\registers_reg[2][16] } {/theRegisters/\registers_reg[2][17] } {/theRegisters/\registers_reg[2][18] } {/theRegisters/\registers_reg[2][19] } {/theRegisters/\registers_reg[2][1] } {/theRegisters/\registers_reg[2][20] } {/theRegisters/\registers_reg[2][21] } {/theRegisters/\registers_reg[2][22] } {/theRegisters/\registers_reg[2][23] } {/theRegisters/\registers_reg[2][24] } {/theRegisters/\registers_reg[2][25] } {/theRegisters/\registers_reg[2][26] } {/theRegisters/\registers_reg[2][27] } {/theRegisters/\registers_reg[2][28] } {/theRegisters/\registers_reg[2][29] } {/theRegisters/\registers_reg[2][2] } {/theRegisters/\registers_reg[2][30] } {/theRegisters/\registers_reg[2][31] } {/theRegisters/\registers_reg[2][3] } {/theRegisters/\registers_reg[2][4] } {/theRegisters/\registers_reg[2][5] } {/theRegisters/\registers_reg[2][6] } {/theRegisters/\registers_reg[2][7] } {/theRegisters/\registers_reg[2][8] } {/theRegisters/\registers_reg[2][9] } {/theRegisters/\registers_reg[30][0] } {/theRegisters/\registers_reg[30][10] } {/theRegisters/\registers_reg[30][11] } {/theRegisters/\registers_reg[30][12] } {/theRegisters/\registers_reg[30][13] } {/theRegisters/\registers_reg[30][14] } {/theRegisters/\registers_reg[30][15] } {/theRegisters/\registers_reg[30][16] } {/theRegisters/\registers_reg[30][17] } {/theRegisters/\registers_reg[30][18] } {/theRegisters/\registers_reg[30][19] } {/theRegisters/\registers_reg[30][1] } {/theRegisters/\registers_reg[30][20] } {/theRegisters/\registers_reg[30][21] } {/theRegisters/\registers_reg[30][22] } {/theRegisters/\registers_reg[30][23] } {/theRegisters/\registers_reg[30][24] } {/theRegisters/\registers_reg[30][25] } {/theRegisters/\registers_reg[30][26] } {/theRegisters/\registers_reg[30][27] } {/theRegisters/\registers_reg[30][28] } {/theRegisters/\registers_reg[30][29] } {/theRegisters/\registers_reg[30][2] } {/theRegisters/\registers_reg[30][30] } {/theRegisters/\registers_reg[30][31] } {/theRegisters/\registers_reg[30][3] } {/theRegisters/\registers_reg[30][4] } {/theRegisters/\registers_reg[30][5] } {/theRegisters/\registers_reg[30][6] } {/theRegisters/\registers_reg[30][7] } {/theRegisters/\registers_reg[30][8] } {/theRegisters/\registers_reg[30][9] } } -si_connections {SI_3 } -so_connections {SO_3 } -chain_count 1 +create_scan_chain_family scanChain_4 -include_elements {{/theRegisters/\registers_reg[31][0] } {/theRegisters/\registers_reg[31][10] } {/theRegisters/\registers_reg[31][11] } {/theRegisters/\registers_reg[31][12] } {/theRegisters/\registers_reg[31][13] } {/theRegisters/\registers_reg[31][14] } {/theRegisters/\registers_reg[31][15] } {/theRegisters/\registers_reg[31][16] } {/theRegisters/\registers_reg[31][17] } {/theRegisters/\registers_reg[31][18] } {/theRegisters/\registers_reg[31][19] } {/theRegisters/\registers_reg[31][1] } {/theRegisters/\registers_reg[31][20] } {/theRegisters/\registers_reg[31][21] } {/theRegisters/\registers_reg[31][22] } {/theRegisters/\registers_reg[31][23] } {/theRegisters/\registers_reg[31][24] } {/theRegisters/\registers_reg[31][25] } {/theRegisters/\registers_reg[31][26] } {/theRegisters/\registers_reg[31][27] } {/theRegisters/\registers_reg[31][28] } {/theRegisters/\registers_reg[31][29] } {/theRegisters/\registers_reg[31][2] } {/theRegisters/\registers_reg[31][30] } {/theRegisters/\registers_reg[31][31] } {/theRegisters/\registers_reg[31][3] } {/theRegisters/\registers_reg[31][4] } {/theRegisters/\registers_reg[31][5] } {/theRegisters/\registers_reg[31][6] } {/theRegisters/\registers_reg[31][7] } {/theRegisters/\registers_reg[31][8] } {/theRegisters/\registers_reg[31][9] } {/theRegisters/\registers_reg[3][0] } {/theRegisters/\registers_reg[3][10] } {/theRegisters/\registers_reg[3][11] } {/theRegisters/\registers_reg[3][12] } {/theRegisters/\registers_reg[3][13] } {/theRegisters/\registers_reg[3][14] } {/theRegisters/\registers_reg[3][15] } {/theRegisters/\registers_reg[3][16] } {/theRegisters/\registers_reg[3][17] } {/theRegisters/\registers_reg[3][18] } {/theRegisters/\registers_reg[3][19] } {/theRegisters/\registers_reg[3][1] } {/theRegisters/\registers_reg[3][20] } {/theRegisters/\registers_reg[3][21] } {/theRegisters/\registers_reg[3][22] } {/theRegisters/\registers_reg[3][23] } {/theRegisters/\registers_reg[3][24] } {/theRegisters/\registers_reg[3][25] } {/theRegisters/\registers_reg[3][26] } {/theRegisters/\registers_reg[3][27] } {/theRegisters/\registers_reg[3][28] } {/theRegisters/\registers_reg[3][29] } {/theRegisters/\registers_reg[3][2] } {/theRegisters/\registers_reg[3][30] } {/theRegisters/\registers_reg[3][31] } {/theRegisters/\registers_reg[3][3] } {/theRegisters/\registers_reg[3][4] } {/theRegisters/\registers_reg[3][5] } {/theRegisters/\registers_reg[3][6] } {/theRegisters/\registers_reg[3][7] } {/theRegisters/\registers_reg[3][8] } {/theRegisters/\registers_reg[3][9] } {/theRegisters/\registers_reg[4][0] } {/theRegisters/\registers_reg[4][10] } {/theRegisters/\registers_reg[4][11] } {/theRegisters/\registers_reg[4][12] } {/theRegisters/\registers_reg[4][13] } {/theRegisters/\registers_reg[4][14] } {/theRegisters/\registers_reg[4][15] } {/theRegisters/\registers_reg[4][16] } {/theRegisters/\registers_reg[4][17] } {/theRegisters/\registers_reg[4][18] } {/theRegisters/\registers_reg[4][19] } {/theRegisters/\registers_reg[4][1] } {/theRegisters/\registers_reg[4][20] } {/theRegisters/\registers_reg[4][21] } {/theRegisters/\registers_reg[4][22] } {/theRegisters/\registers_reg[4][23] } {/theRegisters/\registers_reg[4][24] } {/theRegisters/\registers_reg[4][25] } {/theRegisters/\registers_reg[4][26] } {/theRegisters/\registers_reg[4][27] } {/theRegisters/\registers_reg[4][28] } {/theRegisters/\registers_reg[4][29] } {/theRegisters/\registers_reg[4][2] } {/theRegisters/\registers_reg[4][30] } {/theRegisters/\registers_reg[4][31] } {/theRegisters/\registers_reg[4][3] } {/theRegisters/\registers_reg[4][4] } {/theRegisters/\registers_reg[4][5] } {/theRegisters/\registers_reg[4][6] } {/theRegisters/\registers_reg[4][7] } {/theRegisters/\registers_reg[4][8] } {/theRegisters/\registers_reg[4][9] } {/theRegisters/\registers_reg[5][0] } {/theRegisters/\registers_reg[5][10] } {/theRegisters/\registers_reg[5][11] } {/theRegisters/\registers_reg[5][12] } {/theRegisters/\registers_reg[5][13] } {/theRegisters/\registers_reg[5][14] } {/theRegisters/\registers_reg[5][15] } {/theRegisters/\registers_reg[5][16] } {/theRegisters/\registers_reg[5][17] } {/theRegisters/\registers_reg[5][18] } {/theRegisters/\registers_reg[5][19] } {/theRegisters/\registers_reg[5][1] } {/theRegisters/\registers_reg[5][20] } {/theRegisters/\registers_reg[5][21] } {/theRegisters/\registers_reg[5][22] } {/theRegisters/\registers_reg[5][23] } {/theRegisters/\registers_reg[5][24] } {/theRegisters/\registers_reg[5][25] } {/theRegisters/\registers_reg[5][26] } {/theRegisters/\registers_reg[5][27] } {/theRegisters/\registers_reg[5][28] } {/theRegisters/\registers_reg[5][29] } {/theRegisters/\registers_reg[5][2] } {/theRegisters/\registers_reg[5][30] } {/theRegisters/\registers_reg[5][31] } {/theRegisters/\registers_reg[5][3] } {/theRegisters/\registers_reg[5][4] } {/theRegisters/\registers_reg[5][5] } {/theRegisters/\registers_reg[5][6] } {/theRegisters/\registers_reg[5][7] } {/theRegisters/\registers_reg[5][8] } {/theRegisters/\registers_reg[5][9] } {/theRegisters/\registers_reg[6][0] } {/theRegisters/\registers_reg[6][10] } {/theRegisters/\registers_reg[6][11] } {/theRegisters/\registers_reg[6][12] } {/theRegisters/\registers_reg[6][13] } {/theRegisters/\registers_reg[6][14] } {/theRegisters/\registers_reg[6][15] } {/theRegisters/\registers_reg[6][16] } {/theRegisters/\registers_reg[6][17] } {/theRegisters/\registers_reg[6][18] } {/theRegisters/\registers_reg[6][19] } {/theRegisters/\registers_reg[6][1] } {/theRegisters/\registers_reg[6][20] } {/theRegisters/\registers_reg[6][21] } {/theRegisters/\registers_reg[6][22] } {/theRegisters/\registers_reg[6][23] } {/theRegisters/\registers_reg[6][24] } {/theRegisters/\registers_reg[6][25] } {/theRegisters/\registers_reg[6][26] } {/theRegisters/\registers_reg[6][27] } {/theRegisters/\registers_reg[6][28] } {/theRegisters/\registers_reg[6][29] } {/theRegisters/\registers_reg[6][2] } {/theRegisters/\registers_reg[6][30] } {/theRegisters/\registers_reg[6][31] } {/theRegisters/\registers_reg[6][3] } {/theRegisters/\registers_reg[6][4] } {/theRegisters/\registers_reg[6][5] } {/theRegisters/\registers_reg[6][6] } {/theRegisters/\registers_reg[6][7] } {/theRegisters/\registers_reg[6][8] } {/theRegisters/\registers_reg[6][9] } {/theRegisters/\registers_reg[7][0] } {/theRegisters/\registers_reg[7][10] } {/theRegisters/\registers_reg[7][11] } {/theRegisters/\registers_reg[7][12] } {/theRegisters/\registers_reg[7][13] } {/theRegisters/\registers_reg[7][14] } {/theRegisters/\registers_reg[7][15] } {/theRegisters/\registers_reg[7][16] } {/theRegisters/\registers_reg[7][17] } {/theRegisters/\registers_reg[7][18] } {/theRegisters/\registers_reg[7][19] } {/theRegisters/\registers_reg[7][1] } {/theRegisters/\registers_reg[7][20] } {/theRegisters/\registers_reg[7][21] } {/theRegisters/\registers_reg[7][22] } {/theRegisters/\registers_reg[7][23] } {/theRegisters/\registers_reg[7][24] } {/theRegisters/\registers_reg[7][25] } {/theRegisters/\registers_reg[7][26] } {/theRegisters/\registers_reg[7][27] } {/theRegisters/\registers_reg[7][28] } {/theRegisters/\registers_reg[7][29] } {/theRegisters/\registers_reg[7][2] } {/theRegisters/\registers_reg[7][30] } {/theRegisters/\registers_reg[7][31] } {/theRegisters/\registers_reg[7][3] } {/theRegisters/\registers_reg[7][4] } {/theRegisters/\registers_reg[7][5] } {/theRegisters/\registers_reg[7][6] } {/theRegisters/\registers_reg[7][7] } {/theRegisters/\registers_reg[7][8] } {/theRegisters/\registers_reg[7][9] } {/theRegisters/\registers_reg[8][0] } {/theRegisters/\registers_reg[8][10] } {/theRegisters/\registers_reg[8][11] } {/theRegisters/\registers_reg[8][12] } {/theRegisters/\registers_reg[8][13] } {/theRegisters/\registers_reg[8][14] } {/theRegisters/\registers_reg[8][15] } {/theRegisters/\registers_reg[8][16] } {/theRegisters/\registers_reg[8][17] } {/theRegisters/\registers_reg[8][18] } {/theRegisters/\registers_reg[8][19] } {/theRegisters/\registers_reg[8][1] } {/theRegisters/\registers_reg[8][20] } {/theRegisters/\registers_reg[8][21] } {/theRegisters/\registers_reg[8][22] } {/theRegisters/\registers_reg[8][23] } {/theRegisters/\registers_reg[8][24] } {/theRegisters/\registers_reg[8][25] } {/theRegisters/\registers_reg[8][26] } {/theRegisters/\registers_reg[8][27] } {/theRegisters/\registers_reg[8][28] } {/theRegisters/\registers_reg[8][29] } {/theRegisters/\registers_reg[8][2] } {/theRegisters/\registers_reg[8][30] } {/theRegisters/\registers_reg[8][31] } {/theRegisters/\registers_reg[8][3] } {/theRegisters/\registers_reg[8][4] } {/theRegisters/\registers_reg[8][5] } {/theRegisters/\registers_reg[8][6] } {/theRegisters/\registers_reg[8][7] } {/theRegisters/\registers_reg[8][8] } {/theRegisters/\registers_reg[8][9] } {/theRegisters/\registers_reg[9][0] } {/theRegisters/\registers_reg[9][10] } {/theRegisters/\registers_reg[9][11] } {/theRegisters/\registers_reg[9][12] } {/theRegisters/\registers_reg[9][13] } {/theRegisters/\registers_reg[9][14] } {/theRegisters/\registers_reg[9][15] } {/theRegisters/\registers_reg[9][16] } {/theRegisters/\registers_reg[9][17] } {/theRegisters/\registers_reg[9][18] } {/theRegisters/\registers_reg[9][19] } {/theRegisters/\registers_reg[9][1] } {/theRegisters/\registers_reg[9][20] } {/theRegisters/\registers_reg[9][21] } {/theRegisters/\registers_reg[9][22] } {/theRegisters/\registers_reg[9][23] } {/theRegisters/\registers_reg[9][24] } {/theRegisters/\registers_reg[9][25] } {/theRegisters/\registers_reg[9][26] } {/theRegisters/\registers_reg[9][27] } {/theRegisters/\registers_reg[9][28] } {/theRegisters/\registers_reg[9][29] } {/theRegisters/\registers_reg[9][2] } {/theRegisters/\registers_reg[9][30] } {/theRegisters/\registers_reg[9][31] } {/theRegisters/\registers_reg[9][3] } {/theRegisters/\registers_reg[9][4] } {/theRegisters/\registers_reg[9][5] } {/theRegisters/\registers_reg[9][6] } {/theRegisters/\registers_reg[9][7] } {/theRegisters/\registers_reg[9][8] } {/theRegisters/\registers_reg[9][9] } } -si_connections {SI_4 } -so_connections {SO_4 } -chain_count 1 +source /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/Scan_0/scan_enable_cluster.cfg +analyze_scan_chains +insert_test_logic -write_in_tsdb on +report_scan_chains + +write_scan_order /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/Scan_0/cpu.scandef -use_escaping_rule Lefdef -replace +write_design -output_file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/Scan_0/post_scan.v -replace + diff --git a/oasys.tessent.00/Scan_0/scan.log b/oasys.tessent.00/Scan_0/scan.log new file mode 100644 index 0000000..4a8535c --- /dev/null +++ b/oasys.tessent.00/Scan_0/scan.log @@ -0,0 +1,409 @@ +/applications/SiemensEDA/siemenseda2023/tessent_2023.4-p1/bin/tessent -shell -dofile /tmp/oasys.2483642/.tmpTessentFile -log_file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/Scan_0/scan.log -replace +// Tessent Shell 2023.4-p1 Mon Feb 19 16:22:02 GMT 2024 +// Unpublished work. Copyright 2024 Siemens +// +// This material contains trade secrets or otherwise confidential +// information owned by Siemens Industry Software Inc. or its affiliates +// (collectively, "SISW"), or its licensors. Access to and use of this +// information is strictly limited as set forth in the Customer's +// applicable agreements with SISW. +// +// Siemens software executing under x86-64 Linux on Thu May 28 17:28:57 CEST 2026. +// 64 bit version +// Host: efiapps0.ads1.fh-nuernberg.de (12 x 3.5 GHz, 48014 MB RAM, 24575 MB Swap) +// +// command: if {[catch {source /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/Scan_0/scan.do} msg]} { +// puts "$msg" +// puts "TESSENT_ER_ORTL" } +// sub-command: set_context dft -scan -no_rtl -design_id Scan_0 +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_low_temp_ccs.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_low_temp_ccs.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_low_temp_ccs.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_low_temp_ccs.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_low_temp_ccs.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_low_temp_ccs.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/PLL.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/PLL.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/PLL.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/IO.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/IO.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/IO.fslib +// sub-command: set_module_matching_options -suffix_pattern_list {[_]+[0-9]+[_]+[0-9]+} -regexp -append +// sub-command: set_module_matching_options -suffix_pattern_list {[_]+[A-Z]+} -regexp -append +// sub-command: set_module_matching_options -suffix_pattern_list {[_]+[0-9]+[_]+[0-9]+[_]+[A-Z]+} -regexp -append +// sub-command: read_verilog /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/Scan_0/oasys_netlist.v +// sub-command: set_tsdb_output_directory /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/tsdb_outdir +// sub-command: read_sdc /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/Scan_0/oasys.sdc +// Command 'read_sdc' requires an elaborated design. Automatically elaborating the design ... +// Note: 640 duplicate cell library models were read. The last model read of the same name was kept. +// To see detailed messages per duplicate model, issue 'set_cell_library_options -report_duplicate_models on' +// before issuing 'read_cell_library'. +// Warning: 1 cell library model contained 2 floating model outputs. +// To see detailed messages per model, issue 'set_cell_library_options -report_floating_nets on' +// before issuing 'read_cell_library'. +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X1' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X2' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X4' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X8' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X1_HVT' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X2_HVT' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X4_HVT' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X8_HVT' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X1_SVT' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X2_SVT' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X4_SVT' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X8_SVT' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X1_LVT' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X2_LVT' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X4_LVT' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X8_LVT' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' +// Note: Top design is 'cpu'. +// Warning: Undefined modules were found. +// Before using "set_system_mode" or "create_flat_model", you must either define +// the missing modules using "read_verilog" and/or "read_cell_library", or use the +// following command to treat them as black boxes: + add_black_boxes -modules { \ + MemGen_16_10 \ + } +// You can also use "add_black_boxes -auto" to black box all undefined modules but +// it is recommended that you do not add this command to your dofile. Doing so may +// unintentionally black-box new undefined modules in future runs. +// Warning: 32 cases: Unused net in DFT library model +// Warning: 110 cases: Undriven net in netlist module +// Warning: 1 case: Floating input on instance in netlist +// Warning: 47 cases: Net in netlist not connected +// Note: Issue set_current_design with the -show_elaboration_warnings option to see more details about previous warnings +// Design elaboration successful. +// Reading SDC file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/Scan_0/oasys.sdc ... +// Finished reading SDC file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/Scan_0/oasys.sdc. +// Read SDC summary: 1 false path, 0 multi-cycle paths, 0 erroneous paths +// 0 disable timings, 0 case analysis, 0 clock groups +// sub-command: set_current_design cpu -show_elaboration_warnings +// Warning: Undefined modules were found. +// Before using "set_system_mode" or "create_flat_model", you must either define +// the missing modules using "read_verilog" and/or "read_cell_library", or use the +// following command to treat them as black boxes: + add_black_boxes -modules { \ + MemGen_16_10 \ + } +// You can also use "add_black_boxes -auto" to black box all undefined modules but +// it is recommended that you do not add this command to your dofile. Doing so may +// unintentionally black-box new undefined modules in future runs. +// Warning: Net 'SO_1' in module 'cpu' is not driven +// Warning: Net 'SO_2' in module 'cpu' is not driven +// Warning: Net 'SO_3' in module 'cpu' is not driven +// Warning: Net 'SO_4' in module 'cpu' is not driven +// Warning: Net 'DAddr[31]' in module 'cpu' has no pins +// Warning: Net 'DAddr[30]' in module 'cpu' has no pins +// Warning: Net 'DAddr[29]' in module 'cpu' has no pins +// Warning: Net 'DAddr[28]' in module 'cpu' has no pins +// Warning: Net 'DAddr[27]' in module 'cpu' has no pins +// Warning: Net 'DAddr[26]' in module 'cpu' has no pins +// Warning: Net 'DAddr[25]' in module 'cpu' has no pins +// Warning: Net 'DAddr[24]' in module 'cpu' has no pins +// Warning: Net 'DAddr[23]' in module 'cpu' has no pins +// Warning: Net 'DAddr[22]' in module 'cpu' has no pins +// Warning: Net 'DAddr[21]' in module 'cpu' has no pins +// Warning: Net 'DAddr[20]' in module 'cpu' has no pins +// Warning: Net 'DAddr[19]' in module 'cpu' has no pins +// Warning: Net 'DAddr[18]' in module 'cpu' has no pins +// Warning: Net 'DAddr[17]' in module 'cpu' has no pins +// Warning: Net 'DAddr[16]' in module 'cpu' has no pins +// Warning: Net 'DAddr[15]' in module 'cpu' has no pins +// Warning: Net 'DAddr[14]' in module 'cpu' has no pins +// Warning: Net 'DAddr[13]' in module 'cpu' has no pins +// Warning: Net 'NextPC[31]' in module 'cpu' has no pins +// Warning: Net 'NextPC[30]' in module 'cpu' has no pins +// Warning: Net 'NextPC[29]' in module 'cpu' has no pins +// Warning: Net 'NextPC[28]' in module 'cpu' has no pins +// Warning: Net 'NextPC[27]' in module 'cpu' has no pins +// Warning: Net 'NextPC[26]' in module 'cpu' has no pins +// Warning: Net 'NextPC[25]' in module 'cpu' has no pins +// Warning: Net 'NextPC[24]' in module 'cpu' has no pins +// Warning: Net 'NextPC[23]' in module 'cpu' has no pins +// Warning: Net 'NextPC[22]' in module 'cpu' has no pins +// Warning: Net 'NextPC[21]' in module 'cpu' has no pins +// Warning: Net 'NextPC[20]' in module 'cpu' has no pins +// Warning: Net 'NextPC[19]' in module 'cpu' has no pins +// Warning: Net 'NextPC[18]' in module 'cpu' has no pins +// Warning: Net 'NextPC[17]' in module 'cpu' has no pins +// Warning: Net 'NextPC[16]' in module 'cpu' has no pins +// Warning: Net 'NextPC[15]' in module 'cpu' has no pins +// Warning: Net 'NextPC[14]' in module 'cpu' has no pins +// Warning: Net 'NextPC[13]' in module 'cpu' has no pins +// Warning: Net 'NextPC[7]' in module 'cpu' has no pins +// Warning: Net 'NextPC[6]' in module 'cpu' has no pins +// Warning: Net 'NextPC[5]' in module 'cpu' has no pins +// Warning: Net 'NextPC[4]' in module 'cpu' has no pins +// Warning: Net 'NextPC[3]' in module 'cpu' has no pins +// Warning: Net 'NextPC[2]' in module 'cpu' has no pins +// Warning: Net 'NextPC[1]' in module 'cpu' has no pins +// Warning: Net 'NextPC[0]' in module 'cpu' has no pins +// Warning: Net 'uc_0' in module 'cpu' is not driven +// Warning: Net 'uc_1' in module 'cpu' is not driven +// Warning: Net 'uc_2' in module 'cpu' is not driven +// Warning: Net 'uc_3' in module 'cpu' is not driven +// Warning: Net 'uc_4' in module 'cpu' is not driven +// Warning: Net 'uc_5' in module 'cpu' is not driven +// Warning: Net 'uc_6' in module 'cpu' is not driven +// Warning: Net 'uc_7' in module 'cpu' is not driven +// Warning: Net 'uc_8' in module 'cpu' is not driven +// Warning: Net 'uc_9' in module 'cpu' is not driven +// Warning: Net 'uc_10' in module 'cpu' is not driven +// Warning: Net 'uc_11' in module 'cpu' is not driven +// Warning: Net 'uc_12' in module 'cpu' is not driven +// Warning: Net 'uc_13' in module 'cpu' is not driven +// Warning: Net 'uc_14' in module 'cpu' is not driven +// Warning: Net 'uc_15' in module 'cpu' is not driven +// Warning: Net 'uc_16' in module 'cpu' is not driven +// Warning: Net 'uc_17' in module 'cpu' is not driven +// Warning: Net 'uc_18' in module 'cpu' is not driven +// Warning: Net 'uc_19' in module 'cpu' is not driven +// Warning: Net 'uc_20' in module 'cpu' is not driven +// Warning: Net 'uc_21' in module 'cpu' is not driven +// Warning: Net 'uc_22' in module 'cpu' is not driven +// Warning: Net 'uc_23' in module 'cpu' is not driven +// Warning: Net 'uc_24' in module 'cpu' is not driven +// Warning: Net 'uc_25' in module 'cpu' is not driven +// Warning: Net 'uc_26' in module 'cpu' is not driven +// Warning: Net 'uc_27' in module 'cpu' is not driven +// Warning: Net 'uc_28' in module 'cpu' is not driven +// Warning: Net 'uc_29' in module 'cpu' is not driven +// Warning: Net 'uc_30' in module 'cpu' is not driven +// Warning: Net 'uc_31' in module 'cpu' is not driven +// Warning: Net 'uc_32' in module 'cpu' is not driven +// Warning: Net 'uc_33' in module 'cpu' is not driven +// Warning: Net 'uc_34' in module 'cpu' is not driven +// Warning: Net 'uc_35' in module 'cpu' is not driven +// Warning: Net 'uc_36' in module 'cpu' is not driven +// Warning: Net 'uc_37' in module 'cpu' is not driven +// Warning: Net 'uc_38' in module 'cpu' is not driven +// Warning: Net 'uc_39' in module 'cpu' is not driven +// Warning: Floating input 'chip_en' at instance 'RAM' in module 'main_mem' +// Warning: Net 'mem_sel[1]' in module 'MemGen_32_11' has no pins +// Warning: Net 'DAddr[31]' in module 'decoder' is not driven +// Warning: Net 'DAddr[30]' in module 'decoder' is not driven +// Warning: Net 'DAddr[29]' in module 'decoder' is not driven +// Warning: Net 'DAddr[28]' in module 'decoder' is not driven +// Warning: Net 'DAddr[27]' in module 'decoder' is not driven +// Warning: Net 'DAddr[26]' in module 'decoder' is not driven +// Warning: Net 'DAddr[25]' in module 'decoder' is not driven +// Warning: Net 'DAddr[24]' in module 'decoder' is not driven +// Warning: Net 'DAddr[23]' in module 'decoder' is not driven +// Warning: Net 'DAddr[22]' in module 'decoder' is not driven +// Warning: Net 'DAddr[21]' in module 'decoder' is not driven +// Warning: Net 'DAddr[20]' in module 'decoder' is not driven +// Warning: Net 'DAddr[19]' in module 'decoder' is not driven +// Warning: Net 'DAddr[18]' in module 'decoder' is not driven +// Warning: Net 'DAddr[17]' in module 'decoder' is not driven +// Warning: Net 'DAddr[16]' in module 'decoder' is not driven +// Warning: Net 'DAddr[15]' in module 'decoder' is not driven +// Warning: Net 'DAddr[14]' in module 'decoder' is not driven +// Warning: Net 'DAddr[13]' in module 'decoder' is not driven +// Warning: Net 'WData[31]' in module 'decoder' is not driven +// Warning: Net 'WData[30]' in module 'decoder' is not driven +// Warning: Net 'WData[29]' in module 'decoder' is not driven +// Warning: Net 'WData[28]' in module 'decoder' is not driven +// Warning: Net 'WData[27]' in module 'decoder' is not driven +// Warning: Net 'WData[26]' in module 'decoder' is not driven +// Warning: Net 'WData[25]' in module 'decoder' is not driven +// Warning: Net 'WData[24]' in module 'decoder' is not driven +// Warning: Net 'WData[23]' in module 'decoder' is not driven +// Warning: Net 'WData[22]' in module 'decoder' is not driven +// Warning: Net 'WData[21]' in module 'decoder' is not driven +// Warning: Net 'WData[20]' in module 'decoder' is not driven +// Warning: Net 'WData[19]' in module 'decoder' is not driven +// Warning: Net 'WData[18]' in module 'decoder' is not driven +// Warning: Net 'WData[17]' in module 'decoder' is not driven +// Warning: Net 'WData[16]' in module 'decoder' is not driven +// Warning: Net 'WData[15]' in module 'decoder' is not driven +// Warning: Net 'WData[14]' in module 'decoder' is not driven +// Warning: Net 'WData[13]' in module 'decoder' is not driven +// Warning: Net 'WData[12]' in module 'decoder' is not driven +// Warning: Net 'WData[11]' in module 'decoder' is not driven +// Warning: Net 'WData[10]' in module 'decoder' is not driven +// Warning: Net 'WData[9]' in module 'decoder' is not driven +// Warning: Net 'WData[8]' in module 'decoder' is not driven +// Warning: Net 'WData[7]' in module 'decoder' is not driven +// Warning: Net 'WData[6]' in module 'decoder' is not driven +// Warning: Net 'WData[5]' in module 'decoder' is not driven +// Warning: Net 'WData[4]' in module 'decoder' is not driven +// Warning: Net 'WData[3]' in module 'decoder' is not driven +// Warning: Net 'WData[2]' in module 'decoder' is not driven +// Warning: Net 'WData[1]' in module 'decoder' is not driven +// Warning: Net 'WData[0]' in module 'decoder' is not driven +// Warning: Net 'Rs1[4]' in module 'decoder' is not driven +// Warning: Net 'Rs1[3]' in module 'decoder' is not driven +// Warning: Net 'Rs1[2]' in module 'decoder' is not driven +// Warning: Net 'Rs1[1]' in module 'decoder' is not driven +// Warning: Net 'Rs1[0]' in module 'decoder' is not driven +// Warning: Net 'Rs2[4]' in module 'decoder' is not driven +// Warning: Net 'Rs2[3]' in module 'decoder' is not driven +// Warning: Net 'Rs2[2]' in module 'decoder' is not driven +// Warning: Net 'Rs2[1]' in module 'decoder' is not driven +// Warning: Net 'Rs2[0]' in module 'decoder' is not driven +// Warning: Net 'Rd[4]' in module 'decoder' is not driven +// Warning: Net 'Rd[3]' in module 'decoder' is not driven +// Warning: Net 'Rd[2]' in module 'decoder' is not driven +// Warning: Net 'Rd[1]' in module 'decoder' is not driven +// Warning: Net 'Rd[0]' in module 'decoder' is not driven +// sub-command: set_design_level physical_block +// sub-command: set_shift_register_identification off +// sub-command: add_nonscan_instances -instances "{/theMem/\IRData_reg[31] } {/theMem/\IRData_reg[30] } {/theMem/\IRData_reg[29] } {/theMem/\IRData_reg[28] } {/theMem/\IRData_reg[27] } {/theMem/\IRData_reg[26] } {/theMem/\IRData_reg[25] } {/theMem/\IRData_reg[24] } {/theMem/\IRData_reg[23] } {/theMem/\IRData_reg[22] } {/theMem/\IRData_reg[21] } {/theMem/\IRData_reg[20] } {/theMem/\IRData_reg[19] } {/theMem/\IRData_reg[18] } {/theMem/\IRData_reg[17] } {/theMem/\IRData_reg[16] } {/theMem/\IRData_reg[15] } {/theMem/\IRData_reg[14] } {/theMem/\IRData_reg[13] } {/theMem/\IRData_reg[12] } {/theMem/\IRData_reg[11] } {/theMem/\IRData_reg[10] } {/theMem/\IRData_reg[9] } {/theMem/\IRData_reg[8] } {/theMem/\IRData_reg[7] } {/theMem/\IRData_reg[6] } {/theMem/\IRData_reg[5] } {/theMem/\IRData_reg[4] } {/theMem/\IRData_reg[3] } {/theMem/\IRData_reg[2] } {/theMem/\IRData_reg[1] } {/theMem/\IRData_reg[0] } {/theMem/\mem_addr_reg[10] } {/theMem/\mem_addr_reg[9] } {/theMem/\mem_addr_reg[8] } {/theMem/\mem_addr_reg[7] } {/theMem/\mem_addr_reg[6] } {/theMem/\mem_addr_reg[5] } {/theMem/\mem_addr_reg[4] } {/theMem/\mem_addr_reg[3] } {/theMem/\mem_addr_reg[2] } {/theMem/\mem_addr_reg[1] } {/theMem/\mem_addr_reg[0] } {/theMem/\drTmp_reg[31] } {/theMem/\drTmp_reg[30] } {/theMem/\drTmp_reg[29] } {/theMem/\drTmp_reg[28] } {/theMem/\drTmp_reg[27] } {/theMem/\drTmp_reg[26] } {/theMem/\drTmp_reg[25] } {/theMem/\drTmp_reg[24] } {/theMem/\drTmp_reg[23] } {/theMem/\drTmp_reg[22] } {/theMem/\drTmp_reg[21] } {/theMem/\drTmp_reg[20] } {/theMem/\drTmp_reg[19] } {/theMem/\drTmp_reg[18] } {/theMem/\drTmp_reg[17] } {/theMem/\drTmp_reg[16] } {/theMem/\drTmp_reg[15] } {/theMem/\drTmp_reg[14] } {/theMem/\drTmp_reg[13] } {/theMem/\drTmp_reg[12] } {/theMem/\drTmp_reg[11] } {/theMem/\drTmp_reg[10] } {/theMem/\drTmp_reg[9] } {/theMem/\drTmp_reg[8] } {/theMem/\drTmp_reg[7] } {/theMem/\drTmp_reg[6] } {/theMem/\drTmp_reg[5] } {/theMem/\drTmp_reg[4] } {/theMem/\drTmp_reg[3] } {/theMem/\drTmp_reg[2] } {/theMem/\drTmp_reg[1] } {/theMem/\drTmp_reg[0] } {/theMem/\mem_wdata_reg[31] } {/theMem/\mem_wdata_reg[30] } {/theMem/\mem_wdata_reg[29] } {/theMem/\mem_wdata_reg[28] } {/theMem/\mem_wdata_reg[27] } {/theMem/\mem_wdata_reg[26] } {/theMem/\mem_wdata_reg[25] } {/theMem/\mem_wdata_reg[24] } {/theMem/\mem_wdata_reg[23] } {/theMem/\mem_wdata_reg[22] } {/theMem/\mem_wdata_reg[21] } {/theMem/\mem_wdata_reg[20] } {/theMem/\mem_wdata_reg[19] } {/theMem/\mem_wdata_reg[18] } {/theMem/\mem_wdata_reg[17] } {/theMem/\mem_wdata_reg[16] } {/theMem/\mem_wdata_reg[15] } {/theMem/\mem_wdata_reg[14] } {/theMem/\mem_wdata_reg[13] } {/theMem/\mem_wdata_reg[12] } {/theMem/\mem_wdata_reg[11] } {/theMem/\mem_wdata_reg[10] } {/theMem/\mem_wdata_reg[9] } {/theMem/\mem_wdata_reg[8] } {/theMem/\mem_wdata_reg[7] } {/theMem/\mem_wdata_reg[6] } {/theMem/\mem_wdata_reg[5] } {/theMem/\mem_wdata_reg[4] } {/theMem/\mem_wdata_reg[3] } {/theMem/\mem_wdata_reg[2] } {/theMem/\mem_wdata_reg[1] } {/theMem/\mem_wdata_reg[0] } " +// sub-command: add_clocks 0 " clk_25mhz " +// sub-command: set_scan_enable scan_en -active high +// sub-command: add_input_constraints btn[0] -C1 +// sub-command: set_scan_enable scan_en -active high -cluster_name scanChain_1 +// sub-command: set_scan_enable scan_en -active high -cluster_name scanChain_2 +// sub-command: set_scan_enable scan_en -active high -cluster_name scanChain_3 +// sub-command: set_scan_enable scan_en -active high -cluster_name scanChain_4 +// sub-command: add_black_boxes -modules " MemGen_16_10 " +// sub-command: set_scan_insertion_options -single_clock_edge_chains on -si_port_format oas_ts_si[%d] -so_port_format oas_ts_so[%d] +// sub-command: set_system_mode analysis +// Warning: Rule FN1 violation occurs 157 times +// Warning: Rule FP13 violation occurs 1 times +// Flattening process completed, cell instances=4379, gates=18234, PIs=13, POs=12, CPU time=0.09 sec. +// --------------------------------------------------------------------------- +// Begin circuit learning analyses. +// -------------------------------- +// Learning completed, CPU time=0.01 sec. +// --------------------------------------------------------------------------- +// Begin scan chain identification process, memory elements = 1194, +// sequential library cells = 1194. +// --------------------------------------------------------------------------- +// Warning: Model 'DLH_X1_LVT' has no muxscan scan equivalent and is treated as nonscan model +// ------------------------------------------------------------------------------ +// 170 sequential library cells are treated as non-scan. +// ------------------------------------------------------------------------------ +// 63 sequential library cells missing mux-scan equivalent. +// 107 sequential library cells defined non-scan. +// --------------------------------------------------------------------------- +// Begin scannability rules checking for 1024 sequential library cells. +// --------------------------------------------------------------------------- +// 1024 sequential library cells identified as scannable. +// --------------------------------------------------------------------------- +// Begin transparent latch checking for 63 latches. +// --------------------------------------------------------------------------- +// Warning: 32 latches not transparent due to uncontrollable. (D6) +// Number transparent latches = 31. +// --------------------------------------------------------------------------- +// Begin scan clock rules checking. +// --------------------------------------------------------------------------- +// 1 scan clock/set/reset lines have been identified. +// All scan clocks successfully passed off-state check. +// 1131 sequential cells passed clock stability checking. +// There were 43 clock rule C3 fails (clock may capture data affected by its captured data). +// Note: Trailing edge triggered device can capture data affected by leading edge. +// --------------------------------------------------------------------------- +// 170 non-scan memory elements are identified. +// --------------------------------------------------------------------------- +// 32 non-scan memory elements are identified as TIE-X. (D5) +// 107 non-scan memory elements are identified as INIT-X. (D5) +// 31 non-scan memory elements are identified as TLA. (D5) +// --------------------------------------------------------------------------- +// Number of targeted sequential library cells = 1024 +// Warning: The tool may require a shift-capture clock during insertion, +// but no 'shift_capture_clock' DFT signal was identified +// and no TCLK source was specified using the command 'set_scan_signals -tclk'. +// Note: The system clock 'clk_25mhz' will be used as the shift-capture clock, if needed. +// sub-command: report_drc_rules +C3: #fails=43 handling=note (clock may capture data affected by its captured data) +D5: #fails=170 handling=warning (non-scan memory element) +D6: #fails=32 handling=warning (non-transparent non-scan latches) +// sub-command: create_scan_chain_family scanChain_1 -include_elements "{/\thePC_CurrentPC_reg[0] } {/\thePC_CurrentPC_reg[10] } {/\thePC_CurrentPC_reg[11] } {/\thePC_CurrentPC_reg[12] } {/\thePC_CurrentPC_reg[13] } {/\thePC_CurrentPC_reg[14] } {/\thePC_CurrentPC_reg[15] } {/\thePC_CurrentPC_reg[16] } {/\thePC_CurrentPC_reg[17] } {/\thePC_CurrentPC_reg[18] } {/\thePC_CurrentPC_reg[19] } {/\thePC_CurrentPC_reg[1] } {/\thePC_CurrentPC_reg[20] } {/\thePC_CurrentPC_reg[21] } {/\thePC_CurrentPC_reg[22] } {/\thePC_CurrentPC_reg[23] } {/\thePC_CurrentPC_reg[24] } {/\thePC_CurrentPC_reg[25] } {/\thePC_CurrentPC_reg[26] } {/\thePC_CurrentPC_reg[27] } {/\thePC_CurrentPC_reg[28] } {/\thePC_CurrentPC_reg[29] } {/\thePC_CurrentPC_reg[2] } {/\thePC_CurrentPC_reg[30] } {/\thePC_CurrentPC_reg[31] } {/\thePC_CurrentPC_reg[3] } {/\thePC_CurrentPC_reg[4] } {/\thePC_CurrentPC_reg[5] } {/\thePC_CurrentPC_reg[6] } {/\thePC_CurrentPC_reg[7] } {/\thePC_CurrentPC_reg[8] } {/\thePC_CurrentPC_reg[9] } {/theRegisters/\registers_reg[10][0] } {/theRegisters/\registers_reg[10][10] } {/theRegisters/\registers_reg[10][11] } {/theRegisters/\registers_reg[10][12] } {/theRegisters/\registers_reg[10][13] } {/theRegisters/\registers_reg[10][14] } {/theRegisters/\registers_reg[10][15] } {/theRegisters/\registers_reg[10][16] } {/theRegisters/\registers_reg[10][17] } {/theRegisters/\registers_reg[10][18] } {/theRegisters/\registers_reg[10][19] } {/theRegisters/\registers_reg[10][1] } {/theRegisters/\registers_reg[10][20] } {/theRegisters/\registers_reg[10][21] } {/theRegisters/\registers_reg[10][22] } {/theRegisters/\registers_reg[10][23] } {/theRegisters/\registers_reg[10][24] } {/theRegisters/\registers_reg[10][25] } {/theRegisters/\registers_reg[10][26] } {/theRegisters/\registers_reg[10][27] } {/theRegisters/\registers_reg[10][28] } {/theRegisters/\registers_reg[10][29] } {/theRegisters/\registers_reg[10][2] } {/theRegisters/\registers_reg[10][30] } {/theRegisters/\registers_reg[10][31] } {/theRegisters/\registers_reg[10][3] } {/theRegisters/\registers_reg[10][4] } {/theRegisters/\registers_reg[10][5] } {/theRegisters/\registers_reg[10][6] } {/theRegisters/\registers_reg[10][7] } {/theRegisters/\registers_reg[10][8] } {/theRegisters/\registers_reg[10][9] } {/theRegisters/\registers_reg[11][0] } {/theRegisters/\registers_reg[11][10] } {/theRegisters/\registers_reg[11][11] } {/theRegisters/\registers_reg[11][12] } {/theRegisters/\registers_reg[11][13] } {/theRegisters/\registers_reg[11][14] } {/theRegisters/\registers_reg[11][15] } {/theRegisters/\registers_reg[11][16] } {/theRegisters/\registers_reg[11][17] } {/theRegisters/\registers_reg[11][18] } {/theRegisters/\registers_reg[11][19] } {/theRegisters/\registers_reg[11][1] } {/theRegisters/\registers_reg[11][20] } {/theRegisters/\registers_reg[11][21] } {/theRegisters/\registers_reg[11][22] } {/theRegisters/\registers_reg[11][23] } {/theRegisters/\registers_reg[11][24] } {/theRegisters/\registers_reg[11][25] } {/theRegisters/\registers_reg[11][26] } {/theRegisters/\registers_reg[11][27] } {/theRegisters/\registers_reg[11][28] } {/theRegisters/\registers_reg[11][29] } {/theRegisters/\registers_reg[11][2] } {/theRegisters/\registers_reg[11][30] } {/theRegisters/\registers_reg[11][31] } {/theRegisters/\registers_reg[11][3] } {/theRegisters/\registers_reg[11][4] } {/theRegisters/\registers_reg[11][5] } {/theRegisters/\registers_reg[11][6] } {/theRegisters/\registers_reg[11][7] } {/theRegisters/\registers_reg[11][8] } {/theRegisters/\registers_reg[11][9] } {/theRegisters/\registers_reg[12][0] } {/theRegisters/\registers_reg[12][10] } {/theRegisters/\registers_reg[12][11] } {/theRegisters/\registers_reg[12][12] } {/theRegisters/\registers_reg[12][13] } {/theRegisters/\registers_reg[12][14] } {/theRegisters/\registers_reg[12][15] } {/theRegisters/\registers_reg[12][16] } {/theRegisters/\registers_reg[12][17] } {/theRegisters/\registers_reg[12][18] } {/theRegisters/\registers_reg[12][19] } {/theRegisters/\registers_reg[12][1] } {/theRegisters/\registers_reg[12][20] } {/theRegisters/\registers_reg[12][21] } {/theRegisters/\registers_reg[12][22] } {/theRegisters/\registers_reg[12][23] } {/theRegisters/\registers_reg[12][24] } {/theRegisters/\registers_reg[12][25] } {/theRegisters/\registers_reg[12][26] } {/theRegisters/\registers_reg[12][27] } {/theRegisters/\registers_reg[12][28] } {/theRegisters/\registers_reg[12][29] } {/theRegisters/\registers_reg[12][2] } {/theRegisters/\registers_reg[12][30] } {/theRegisters/\registers_reg[12][31] } {/theRegisters/\registers_reg[12][3] } {/theRegisters/\registers_reg[12][4] } {/theRegisters/\registers_reg[12][5] } {/theRegisters/\registers_reg[12][6] } {/theRegisters/\registers_reg[12][7] } {/theRegisters/\registers_reg[12][8] } {/theRegisters/\registers_reg[12][9] } {/theRegisters/\registers_reg[13][0] } {/theRegisters/\registers_reg[13][10] } {/theRegisters/\registers_reg[13][11] } {/theRegisters/\registers_reg[13][12] } {/theRegisters/\registers_reg[13][13] } {/theRegisters/\registers_reg[13][14] } {/theRegisters/\registers_reg[13][15] } {/theRegisters/\registers_reg[13][16] } {/theRegisters/\registers_reg[13][17] } {/theRegisters/\registers_reg[13][18] } {/theRegisters/\registers_reg[13][19] } {/theRegisters/\registers_reg[13][1] } {/theRegisters/\registers_reg[13][20] } {/theRegisters/\registers_reg[13][21] } {/theRegisters/\registers_reg[13][22] } {/theRegisters/\registers_reg[13][23] } {/theRegisters/\registers_reg[13][24] } {/theRegisters/\registers_reg[13][25] } {/theRegisters/\registers_reg[13][26] } {/theRegisters/\registers_reg[13][27] } {/theRegisters/\registers_reg[13][28] } {/theRegisters/\registers_reg[13][29] } {/theRegisters/\registers_reg[13][2] } {/theRegisters/\registers_reg[13][30] } {/theRegisters/\registers_reg[13][31] } {/theRegisters/\registers_reg[13][3] } {/theRegisters/\registers_reg[13][4] } {/theRegisters/\registers_reg[13][5] } {/theRegisters/\registers_reg[13][6] } {/theRegisters/\registers_reg[13][7] } {/theRegisters/\registers_reg[13][8] } {/theRegisters/\registers_reg[13][9] } {/theRegisters/\registers_reg[14][0] } {/theRegisters/\registers_reg[14][10] } {/theRegisters/\registers_reg[14][11] } {/theRegisters/\registers_reg[14][12] } {/theRegisters/\registers_reg[14][13] } {/theRegisters/\registers_reg[14][14] } {/theRegisters/\registers_reg[14][15] } {/theRegisters/\registers_reg[14][16] } {/theRegisters/\registers_reg[14][17] } {/theRegisters/\registers_reg[14][18] } {/theRegisters/\registers_reg[14][19] } {/theRegisters/\registers_reg[14][1] } {/theRegisters/\registers_reg[14][20] } {/theRegisters/\registers_reg[14][21] } {/theRegisters/\registers_reg[14][22] } {/theRegisters/\registers_reg[14][23] } {/theRegisters/\registers_reg[14][24] } {/theRegisters/\registers_reg[14][25] } {/theRegisters/\registers_reg[14][26] } {/theRegisters/\registers_reg[14][27] } {/theRegisters/\registers_reg[14][28] } {/theRegisters/\registers_reg[14][29] } {/theRegisters/\registers_reg[14][2] } {/theRegisters/\registers_reg[14][30] } {/theRegisters/\registers_reg[14][31] } {/theRegisters/\registers_reg[14][3] } {/theRegisters/\registers_reg[14][4] } {/theRegisters/\registers_reg[14][5] } {/theRegisters/\registers_reg[14][6] } {/theRegisters/\registers_reg[14][7] } {/theRegisters/\registers_reg[14][8] } {/theRegisters/\registers_reg[14][9] } {/theRegisters/\registers_reg[15][0] } {/theRegisters/\registers_reg[15][10] } {/theRegisters/\registers_reg[15][11] } {/theRegisters/\registers_reg[15][12] } {/theRegisters/\registers_reg[15][13] } {/theRegisters/\registers_reg[15][14] } {/theRegisters/\registers_reg[15][15] } {/theRegisters/\registers_reg[15][16] } {/theRegisters/\registers_reg[15][17] } {/theRegisters/\registers_reg[15][18] } {/theRegisters/\registers_reg[15][19] } {/theRegisters/\registers_reg[15][1] } {/theRegisters/\registers_reg[15][20] } {/theRegisters/\registers_reg[15][21] } {/theRegisters/\registers_reg[15][22] } {/theRegisters/\registers_reg[15][23] } {/theRegisters/\registers_reg[15][24] } {/theRegisters/\registers_reg[15][25] } {/theRegisters/\registers_reg[15][26] } {/theRegisters/\registers_reg[15][27] } {/theRegisters/\registers_reg[15][28] } {/theRegisters/\registers_reg[15][29] } {/theRegisters/\registers_reg[15][2] } {/theRegisters/\registers_reg[15][30] } {/theRegisters/\registers_reg[15][31] } {/theRegisters/\registers_reg[15][3] } {/theRegisters/\registers_reg[15][4] } {/theRegisters/\registers_reg[15][5] } {/theRegisters/\registers_reg[15][6] } {/theRegisters/\registers_reg[15][7] } {/theRegisters/\registers_reg[15][8] } {/theRegisters/\registers_reg[15][9] } {/theRegisters/\registers_reg[16][0] } {/theRegisters/\registers_reg[16][10] } {/theRegisters/\registers_reg[16][11] } {/theRegisters/\registers_reg[16][12] } {/theRegisters/\registers_reg[16][13] } {/theRegisters/\registers_reg[16][14] } {/theRegisters/\registers_reg[16][15] } {/theRegisters/\registers_reg[16][16] } {/theRegisters/\registers_reg[16][17] } {/theRegisters/\registers_reg[16][18] } {/theRegisters/\registers_reg[16][19] } {/theRegisters/\registers_reg[16][1] } {/theRegisters/\registers_reg[16][20] } {/theRegisters/\registers_reg[16][21] } {/theRegisters/\registers_reg[16][22] } {/theRegisters/\registers_reg[16][23] } {/theRegisters/\registers_reg[16][24] } {/theRegisters/\registers_reg[16][25] } {/theRegisters/\registers_reg[16][26] } {/theRegisters/\registers_reg[16][27] } {/theRegisters/\registers_reg[16][28] } {/theRegisters/\registers_reg[16][29] } {/theRegisters/\registers_reg[16][2] } {/theRegisters/\registers_reg[16][30] } {/theRegisters/\registers_reg[16][31] } {/theRegisters/\registers_reg[16][3] } {/theRegisters/\registers_reg[16][4] } {/theRegisters/\registers_reg[16][5] } {/theRegisters/\registers_reg[16][6] } {/theRegisters/\registers_reg[16][7] } {/theRegisters/\registers_reg[16][8] } {/theRegisters/\registers_reg[16][9] } " -si_connections "SI_1 " -so_connections "SO_1 " -chain_count 1 +// sub-command: create_scan_chain_family scanChain_2 -include_elements "{/theRegisters/\registers_reg[17][0] } {/theRegisters/\registers_reg[17][10] } {/theRegisters/\registers_reg[17][11] } {/theRegisters/\registers_reg[17][12] } {/theRegisters/\registers_reg[17][13] } {/theRegisters/\registers_reg[17][14] } {/theRegisters/\registers_reg[17][15] } {/theRegisters/\registers_reg[17][16] } {/theRegisters/\registers_reg[17][17] } {/theRegisters/\registers_reg[17][18] } {/theRegisters/\registers_reg[17][19] } {/theRegisters/\registers_reg[17][1] } {/theRegisters/\registers_reg[17][20] } {/theRegisters/\registers_reg[17][21] } {/theRegisters/\registers_reg[17][22] } {/theRegisters/\registers_reg[17][23] } {/theRegisters/\registers_reg[17][24] } {/theRegisters/\registers_reg[17][25] } {/theRegisters/\registers_reg[17][26] } {/theRegisters/\registers_reg[17][27] } {/theRegisters/\registers_reg[17][28] } {/theRegisters/\registers_reg[17][29] } {/theRegisters/\registers_reg[17][2] } {/theRegisters/\registers_reg[17][30] } {/theRegisters/\registers_reg[17][31] } {/theRegisters/\registers_reg[17][3] } {/theRegisters/\registers_reg[17][4] } {/theRegisters/\registers_reg[17][5] } {/theRegisters/\registers_reg[17][6] } {/theRegisters/\registers_reg[17][7] } {/theRegisters/\registers_reg[17][8] } {/theRegisters/\registers_reg[17][9] } {/theRegisters/\registers_reg[18][0] } {/theRegisters/\registers_reg[18][10] } {/theRegisters/\registers_reg[18][11] } {/theRegisters/\registers_reg[18][12] } {/theRegisters/\registers_reg[18][13] } {/theRegisters/\registers_reg[18][14] } {/theRegisters/\registers_reg[18][15] } {/theRegisters/\registers_reg[18][16] } {/theRegisters/\registers_reg[18][17] } {/theRegisters/\registers_reg[18][18] } {/theRegisters/\registers_reg[18][19] } {/theRegisters/\registers_reg[18][1] } {/theRegisters/\registers_reg[18][20] } {/theRegisters/\registers_reg[18][21] } {/theRegisters/\registers_reg[18][22] } {/theRegisters/\registers_reg[18][23] } {/theRegisters/\registers_reg[18][24] } {/theRegisters/\registers_reg[18][25] } {/theRegisters/\registers_reg[18][26] } {/theRegisters/\registers_reg[18][27] } {/theRegisters/\registers_reg[18][28] } {/theRegisters/\registers_reg[18][29] } {/theRegisters/\registers_reg[18][2] } {/theRegisters/\registers_reg[18][30] } {/theRegisters/\registers_reg[18][31] } {/theRegisters/\registers_reg[18][3] } {/theRegisters/\registers_reg[18][4] } {/theRegisters/\registers_reg[18][5] } {/theRegisters/\registers_reg[18][6] } {/theRegisters/\registers_reg[18][7] } {/theRegisters/\registers_reg[18][8] } {/theRegisters/\registers_reg[18][9] } {/theRegisters/\registers_reg[19][0] } {/theRegisters/\registers_reg[19][10] } {/theRegisters/\registers_reg[19][11] } {/theRegisters/\registers_reg[19][12] } {/theRegisters/\registers_reg[19][13] } {/theRegisters/\registers_reg[19][14] } {/theRegisters/\registers_reg[19][15] } {/theRegisters/\registers_reg[19][16] } {/theRegisters/\registers_reg[19][17] } {/theRegisters/\registers_reg[19][18] } {/theRegisters/\registers_reg[19][19] } {/theRegisters/\registers_reg[19][1] } {/theRegisters/\registers_reg[19][20] } {/theRegisters/\registers_reg[19][21] } {/theRegisters/\registers_reg[19][22] } {/theRegisters/\registers_reg[19][23] } {/theRegisters/\registers_reg[19][24] } {/theRegisters/\registers_reg[19][25] } {/theRegisters/\registers_reg[19][26] } {/theRegisters/\registers_reg[19][27] } {/theRegisters/\registers_reg[19][28] } {/theRegisters/\registers_reg[19][29] } {/theRegisters/\registers_reg[19][2] } {/theRegisters/\registers_reg[19][30] } {/theRegisters/\registers_reg[19][31] } {/theRegisters/\registers_reg[19][3] } {/theRegisters/\registers_reg[19][4] } {/theRegisters/\registers_reg[19][5] } {/theRegisters/\registers_reg[19][6] } {/theRegisters/\registers_reg[19][7] } {/theRegisters/\registers_reg[19][8] } {/theRegisters/\registers_reg[19][9] } {/theRegisters/\registers_reg[1][0] } {/theRegisters/\registers_reg[1][10] } {/theRegisters/\registers_reg[1][11] } {/theRegisters/\registers_reg[1][12] } {/theRegisters/\registers_reg[1][13] } {/theRegisters/\registers_reg[1][14] } {/theRegisters/\registers_reg[1][15] } {/theRegisters/\registers_reg[1][16] } {/theRegisters/\registers_reg[1][17] } {/theRegisters/\registers_reg[1][18] } {/theRegisters/\registers_reg[1][19] } {/theRegisters/\registers_reg[1][1] } {/theRegisters/\registers_reg[1][20] } {/theRegisters/\registers_reg[1][21] } {/theRegisters/\registers_reg[1][22] } {/theRegisters/\registers_reg[1][23] } {/theRegisters/\registers_reg[1][24] } {/theRegisters/\registers_reg[1][25] } {/theRegisters/\registers_reg[1][26] } {/theRegisters/\registers_reg[1][27] } {/theRegisters/\registers_reg[1][28] } {/theRegisters/\registers_reg[1][29] } {/theRegisters/\registers_reg[1][2] } {/theRegisters/\registers_reg[1][30] } {/theRegisters/\registers_reg[1][31] } {/theRegisters/\registers_reg[1][3] } {/theRegisters/\registers_reg[1][4] } {/theRegisters/\registers_reg[1][5] } {/theRegisters/\registers_reg[1][6] } {/theRegisters/\registers_reg[1][7] } {/theRegisters/\registers_reg[1][8] } {/theRegisters/\registers_reg[1][9] } {/theRegisters/\registers_reg[20][0] } {/theRegisters/\registers_reg[20][10] } {/theRegisters/\registers_reg[20][11] } {/theRegisters/\registers_reg[20][12] } {/theRegisters/\registers_reg[20][13] } {/theRegisters/\registers_reg[20][14] } {/theRegisters/\registers_reg[20][15] } {/theRegisters/\registers_reg[20][16] } {/theRegisters/\registers_reg[20][17] } {/theRegisters/\registers_reg[20][18] } {/theRegisters/\registers_reg[20][19] } {/theRegisters/\registers_reg[20][1] } {/theRegisters/\registers_reg[20][20] } {/theRegisters/\registers_reg[20][21] } {/theRegisters/\registers_reg[20][22] } {/theRegisters/\registers_reg[20][23] } {/theRegisters/\registers_reg[20][24] } {/theRegisters/\registers_reg[20][25] } {/theRegisters/\registers_reg[20][26] } {/theRegisters/\registers_reg[20][27] } {/theRegisters/\registers_reg[20][28] } {/theRegisters/\registers_reg[20][29] } {/theRegisters/\registers_reg[20][2] } {/theRegisters/\registers_reg[20][30] } {/theRegisters/\registers_reg[20][31] } {/theRegisters/\registers_reg[20][3] } {/theRegisters/\registers_reg[20][4] } {/theRegisters/\registers_reg[20][5] } {/theRegisters/\registers_reg[20][6] } {/theRegisters/\registers_reg[20][7] } {/theRegisters/\registers_reg[20][8] } {/theRegisters/\registers_reg[20][9] } {/theRegisters/\registers_reg[21][0] } {/theRegisters/\registers_reg[21][10] } {/theRegisters/\registers_reg[21][11] } {/theRegisters/\registers_reg[21][12] } {/theRegisters/\registers_reg[21][13] } {/theRegisters/\registers_reg[21][14] } {/theRegisters/\registers_reg[21][15] } {/theRegisters/\registers_reg[21][16] } {/theRegisters/\registers_reg[21][17] } {/theRegisters/\registers_reg[21][18] } {/theRegisters/\registers_reg[21][19] } {/theRegisters/\registers_reg[21][1] } {/theRegisters/\registers_reg[21][20] } {/theRegisters/\registers_reg[21][21] } {/theRegisters/\registers_reg[21][22] } {/theRegisters/\registers_reg[21][23] } {/theRegisters/\registers_reg[21][24] } {/theRegisters/\registers_reg[21][25] } {/theRegisters/\registers_reg[21][26] } {/theRegisters/\registers_reg[21][27] } {/theRegisters/\registers_reg[21][28] } {/theRegisters/\registers_reg[21][29] } {/theRegisters/\registers_reg[21][2] } {/theRegisters/\registers_reg[21][30] } {/theRegisters/\registers_reg[21][31] } {/theRegisters/\registers_reg[21][3] } {/theRegisters/\registers_reg[21][4] } {/theRegisters/\registers_reg[21][5] } {/theRegisters/\registers_reg[21][6] } {/theRegisters/\registers_reg[21][7] } {/theRegisters/\registers_reg[21][8] } {/theRegisters/\registers_reg[21][9] } {/theRegisters/\registers_reg[22][0] } {/theRegisters/\registers_reg[22][10] } {/theRegisters/\registers_reg[22][11] } {/theRegisters/\registers_reg[22][12] } {/theRegisters/\registers_reg[22][13] } {/theRegisters/\registers_reg[22][14] } {/theRegisters/\registers_reg[22][15] } {/theRegisters/\registers_reg[22][16] } {/theRegisters/\registers_reg[22][17] } {/theRegisters/\registers_reg[22][18] } {/theRegisters/\registers_reg[22][19] } {/theRegisters/\registers_reg[22][1] } {/theRegisters/\registers_reg[22][20] } {/theRegisters/\registers_reg[22][21] } {/theRegisters/\registers_reg[22][22] } {/theRegisters/\registers_reg[22][23] } {/theRegisters/\registers_reg[22][24] } {/theRegisters/\registers_reg[22][25] } {/theRegisters/\registers_reg[22][26] } {/theRegisters/\registers_reg[22][27] } {/theRegisters/\registers_reg[22][28] } {/theRegisters/\registers_reg[22][29] } {/theRegisters/\registers_reg[22][2] } {/theRegisters/\registers_reg[22][30] } {/theRegisters/\registers_reg[22][31] } {/theRegisters/\registers_reg[22][3] } {/theRegisters/\registers_reg[22][4] } {/theRegisters/\registers_reg[22][5] } {/theRegisters/\registers_reg[22][6] } {/theRegisters/\registers_reg[22][7] } {/theRegisters/\registers_reg[22][8] } {/theRegisters/\registers_reg[22][9] } {/theRegisters/\registers_reg[23][0] } {/theRegisters/\registers_reg[23][10] } {/theRegisters/\registers_reg[23][11] } {/theRegisters/\registers_reg[23][12] } {/theRegisters/\registers_reg[23][13] } {/theRegisters/\registers_reg[23][14] } {/theRegisters/\registers_reg[23][15] } {/theRegisters/\registers_reg[23][16] } {/theRegisters/\registers_reg[23][17] } {/theRegisters/\registers_reg[23][18] } {/theRegisters/\registers_reg[23][19] } {/theRegisters/\registers_reg[23][1] } {/theRegisters/\registers_reg[23][20] } {/theRegisters/\registers_reg[23][21] } {/theRegisters/\registers_reg[23][22] } {/theRegisters/\registers_reg[23][23] } {/theRegisters/\registers_reg[23][24] } {/theRegisters/\registers_reg[23][25] } {/theRegisters/\registers_reg[23][26] } {/theRegisters/\registers_reg[23][27] } {/theRegisters/\registers_reg[23][28] } {/theRegisters/\registers_reg[23][29] } {/theRegisters/\registers_reg[23][2] } {/theRegisters/\registers_reg[23][30] } {/theRegisters/\registers_reg[23][31] } {/theRegisters/\registers_reg[23][3] } {/theRegisters/\registers_reg[23][4] } {/theRegisters/\registers_reg[23][5] } {/theRegisters/\registers_reg[23][6] } {/theRegisters/\registers_reg[23][7] } {/theRegisters/\registers_reg[23][8] } {/theRegisters/\registers_reg[23][9] } " -si_connections "SI_2 " -so_connections "SO_2 " -chain_count 1 +// sub-command: create_scan_chain_family scanChain_3 -include_elements "{/theRegisters/\registers_reg[24][0] } {/theRegisters/\registers_reg[24][10] } {/theRegisters/\registers_reg[24][11] } {/theRegisters/\registers_reg[24][12] } {/theRegisters/\registers_reg[24][13] } {/theRegisters/\registers_reg[24][14] } {/theRegisters/\registers_reg[24][15] } {/theRegisters/\registers_reg[24][16] } {/theRegisters/\registers_reg[24][17] } {/theRegisters/\registers_reg[24][18] } {/theRegisters/\registers_reg[24][19] } {/theRegisters/\registers_reg[24][1] } {/theRegisters/\registers_reg[24][20] } {/theRegisters/\registers_reg[24][21] } {/theRegisters/\registers_reg[24][22] } {/theRegisters/\registers_reg[24][23] } {/theRegisters/\registers_reg[24][24] } {/theRegisters/\registers_reg[24][25] } {/theRegisters/\registers_reg[24][26] } {/theRegisters/\registers_reg[24][27] } {/theRegisters/\registers_reg[24][28] } {/theRegisters/\registers_reg[24][29] } {/theRegisters/\registers_reg[24][2] } {/theRegisters/\registers_reg[24][30] } {/theRegisters/\registers_reg[24][31] } {/theRegisters/\registers_reg[24][3] } {/theRegisters/\registers_reg[24][4] } {/theRegisters/\registers_reg[24][5] } {/theRegisters/\registers_reg[24][6] } {/theRegisters/\registers_reg[24][7] } {/theRegisters/\registers_reg[24][8] } {/theRegisters/\registers_reg[24][9] } {/theRegisters/\registers_reg[25][0] } {/theRegisters/\registers_reg[25][10] } {/theRegisters/\registers_reg[25][11] } {/theRegisters/\registers_reg[25][12] } {/theRegisters/\registers_reg[25][13] } {/theRegisters/\registers_reg[25][14] } {/theRegisters/\registers_reg[25][15] } {/theRegisters/\registers_reg[25][16] } {/theRegisters/\registers_reg[25][17] } {/theRegisters/\registers_reg[25][18] } {/theRegisters/\registers_reg[25][19] } {/theRegisters/\registers_reg[25][1] } {/theRegisters/\registers_reg[25][20] } {/theRegisters/\registers_reg[25][21] } {/theRegisters/\registers_reg[25][22] } {/theRegisters/\registers_reg[25][23] } {/theRegisters/\registers_reg[25][24] } {/theRegisters/\registers_reg[25][25] } {/theRegisters/\registers_reg[25][26] } {/theRegisters/\registers_reg[25][27] } {/theRegisters/\registers_reg[25][28] } {/theRegisters/\registers_reg[25][29] } {/theRegisters/\registers_reg[25][2] } {/theRegisters/\registers_reg[25][30] } {/theRegisters/\registers_reg[25][31] } {/theRegisters/\registers_reg[25][3] } {/theRegisters/\registers_reg[25][4] } {/theRegisters/\registers_reg[25][5] } {/theRegisters/\registers_reg[25][6] } {/theRegisters/\registers_reg[25][7] } {/theRegisters/\registers_reg[25][8] } {/theRegisters/\registers_reg[25][9] } {/theRegisters/\registers_reg[26][0] } {/theRegisters/\registers_reg[26][10] } {/theRegisters/\registers_reg[26][11] } {/theRegisters/\registers_reg[26][12] } {/theRegisters/\registers_reg[26][13] } {/theRegisters/\registers_reg[26][14] } {/theRegisters/\registers_reg[26][15] } {/theRegisters/\registers_reg[26][16] } {/theRegisters/\registers_reg[26][17] } {/theRegisters/\registers_reg[26][18] } {/theRegisters/\registers_reg[26][19] } {/theRegisters/\registers_reg[26][1] } {/theRegisters/\registers_reg[26][20] } {/theRegisters/\registers_reg[26][21] } {/theRegisters/\registers_reg[26][22] } {/theRegisters/\registers_reg[26][23] } {/theRegisters/\registers_reg[26][24] } {/theRegisters/\registers_reg[26][25] } {/theRegisters/\registers_reg[26][26] } {/theRegisters/\registers_reg[26][27] } {/theRegisters/\registers_reg[26][28] } {/theRegisters/\registers_reg[26][29] } {/theRegisters/\registers_reg[26][2] } {/theRegisters/\registers_reg[26][30] } {/theRegisters/\registers_reg[26][31] } {/theRegisters/\registers_reg[26][3] } {/theRegisters/\registers_reg[26][4] } {/theRegisters/\registers_reg[26][5] } {/theRegisters/\registers_reg[26][6] } {/theRegisters/\registers_reg[26][7] } {/theRegisters/\registers_reg[26][8] } {/theRegisters/\registers_reg[26][9] } {/theRegisters/\registers_reg[27][0] } {/theRegisters/\registers_reg[27][10] } {/theRegisters/\registers_reg[27][11] } {/theRegisters/\registers_reg[27][12] } {/theRegisters/\registers_reg[27][13] } {/theRegisters/\registers_reg[27][14] } {/theRegisters/\registers_reg[27][15] } {/theRegisters/\registers_reg[27][16] } {/theRegisters/\registers_reg[27][17] } {/theRegisters/\registers_reg[27][18] } {/theRegisters/\registers_reg[27][19] } {/theRegisters/\registers_reg[27][1] } {/theRegisters/\registers_reg[27][20] } {/theRegisters/\registers_reg[27][21] } {/theRegisters/\registers_reg[27][22] } {/theRegisters/\registers_reg[27][23] } {/theRegisters/\registers_reg[27][24] } {/theRegisters/\registers_reg[27][25] } {/theRegisters/\registers_reg[27][26] } {/theRegisters/\registers_reg[27][27] } {/theRegisters/\registers_reg[27][28] } {/theRegisters/\registers_reg[27][29] } {/theRegisters/\registers_reg[27][2] } {/theRegisters/\registers_reg[27][30] } {/theRegisters/\registers_reg[27][31] } {/theRegisters/\registers_reg[27][3] } {/theRegisters/\registers_reg[27][4] } {/theRegisters/\registers_reg[27][5] } {/theRegisters/\registers_reg[27][6] } {/theRegisters/\registers_reg[27][7] } {/theRegisters/\registers_reg[27][8] } {/theRegisters/\registers_reg[27][9] } {/theRegisters/\registers_reg[28][0] } {/theRegisters/\registers_reg[28][10] } {/theRegisters/\registers_reg[28][11] } {/theRegisters/\registers_reg[28][12] } {/theRegisters/\registers_reg[28][13] } {/theRegisters/\registers_reg[28][14] } {/theRegisters/\registers_reg[28][15] } {/theRegisters/\registers_reg[28][16] } {/theRegisters/\registers_reg[28][17] } {/theRegisters/\registers_reg[28][18] } {/theRegisters/\registers_reg[28][19] } {/theRegisters/\registers_reg[28][1] } {/theRegisters/\registers_reg[28][20] } {/theRegisters/\registers_reg[28][21] } {/theRegisters/\registers_reg[28][22] } {/theRegisters/\registers_reg[28][23] } {/theRegisters/\registers_reg[28][24] } {/theRegisters/\registers_reg[28][25] } {/theRegisters/\registers_reg[28][26] } {/theRegisters/\registers_reg[28][27] } {/theRegisters/\registers_reg[28][28] } {/theRegisters/\registers_reg[28][29] } {/theRegisters/\registers_reg[28][2] } {/theRegisters/\registers_reg[28][30] } {/theRegisters/\registers_reg[28][31] } {/theRegisters/\registers_reg[28][3] } {/theRegisters/\registers_reg[28][4] } {/theRegisters/\registers_reg[28][5] } {/theRegisters/\registers_reg[28][6] } {/theRegisters/\registers_reg[28][7] } {/theRegisters/\registers_reg[28][8] } {/theRegisters/\registers_reg[28][9] } {/theRegisters/\registers_reg[29][0] } {/theRegisters/\registers_reg[29][10] } {/theRegisters/\registers_reg[29][11] } {/theRegisters/\registers_reg[29][12] } {/theRegisters/\registers_reg[29][13] } {/theRegisters/\registers_reg[29][14] } {/theRegisters/\registers_reg[29][15] } {/theRegisters/\registers_reg[29][16] } {/theRegisters/\registers_reg[29][17] } {/theRegisters/\registers_reg[29][18] } {/theRegisters/\registers_reg[29][19] } {/theRegisters/\registers_reg[29][1] } {/theRegisters/\registers_reg[29][20] } {/theRegisters/\registers_reg[29][21] } {/theRegisters/\registers_reg[29][22] } {/theRegisters/\registers_reg[29][23] } {/theRegisters/\registers_reg[29][24] } {/theRegisters/\registers_reg[29][25] } {/theRegisters/\registers_reg[29][26] } {/theRegisters/\registers_reg[29][27] } {/theRegisters/\registers_reg[29][28] } {/theRegisters/\registers_reg[29][29] } {/theRegisters/\registers_reg[29][2] } {/theRegisters/\registers_reg[29][30] } {/theRegisters/\registers_reg[29][31] } {/theRegisters/\registers_reg[29][3] } {/theRegisters/\registers_reg[29][4] } {/theRegisters/\registers_reg[29][5] } {/theRegisters/\registers_reg[29][6] } {/theRegisters/\registers_reg[29][7] } {/theRegisters/\registers_reg[29][8] } {/theRegisters/\registers_reg[29][9] } {/theRegisters/\registers_reg[2][0] } {/theRegisters/\registers_reg[2][10] } {/theRegisters/\registers_reg[2][11] } {/theRegisters/\registers_reg[2][12] } {/theRegisters/\registers_reg[2][13] } {/theRegisters/\registers_reg[2][14] } {/theRegisters/\registers_reg[2][15] } {/theRegisters/\registers_reg[2][16] } {/theRegisters/\registers_reg[2][17] } {/theRegisters/\registers_reg[2][18] } {/theRegisters/\registers_reg[2][19] } {/theRegisters/\registers_reg[2][1] } {/theRegisters/\registers_reg[2][20] } {/theRegisters/\registers_reg[2][21] } {/theRegisters/\registers_reg[2][22] } {/theRegisters/\registers_reg[2][23] } {/theRegisters/\registers_reg[2][24] } {/theRegisters/\registers_reg[2][25] } {/theRegisters/\registers_reg[2][26] } {/theRegisters/\registers_reg[2][27] } {/theRegisters/\registers_reg[2][28] } {/theRegisters/\registers_reg[2][29] } {/theRegisters/\registers_reg[2][2] } {/theRegisters/\registers_reg[2][30] } {/theRegisters/\registers_reg[2][31] } {/theRegisters/\registers_reg[2][3] } {/theRegisters/\registers_reg[2][4] } {/theRegisters/\registers_reg[2][5] } {/theRegisters/\registers_reg[2][6] } {/theRegisters/\registers_reg[2][7] } {/theRegisters/\registers_reg[2][8] } {/theRegisters/\registers_reg[2][9] } {/theRegisters/\registers_reg[30][0] } {/theRegisters/\registers_reg[30][10] } {/theRegisters/\registers_reg[30][11] } {/theRegisters/\registers_reg[30][12] } {/theRegisters/\registers_reg[30][13] } {/theRegisters/\registers_reg[30][14] } {/theRegisters/\registers_reg[30][15] } {/theRegisters/\registers_reg[30][16] } {/theRegisters/\registers_reg[30][17] } {/theRegisters/\registers_reg[30][18] } {/theRegisters/\registers_reg[30][19] } {/theRegisters/\registers_reg[30][1] } {/theRegisters/\registers_reg[30][20] } {/theRegisters/\registers_reg[30][21] } {/theRegisters/\registers_reg[30][22] } {/theRegisters/\registers_reg[30][23] } {/theRegisters/\registers_reg[30][24] } {/theRegisters/\registers_reg[30][25] } {/theRegisters/\registers_reg[30][26] } {/theRegisters/\registers_reg[30][27] } {/theRegisters/\registers_reg[30][28] } {/theRegisters/\registers_reg[30][29] } {/theRegisters/\registers_reg[30][2] } {/theRegisters/\registers_reg[30][30] } {/theRegisters/\registers_reg[30][31] } {/theRegisters/\registers_reg[30][3] } {/theRegisters/\registers_reg[30][4] } {/theRegisters/\registers_reg[30][5] } {/theRegisters/\registers_reg[30][6] } {/theRegisters/\registers_reg[30][7] } {/theRegisters/\registers_reg[30][8] } {/theRegisters/\registers_reg[30][9] } " -si_connections "SI_3 " -so_connections "SO_3 " -chain_count 1 +// sub-command: create_scan_chain_family scanChain_4 -include_elements "{/theRegisters/\registers_reg[31][0] } {/theRegisters/\registers_reg[31][10] } {/theRegisters/\registers_reg[31][11] } {/theRegisters/\registers_reg[31][12] } {/theRegisters/\registers_reg[31][13] } {/theRegisters/\registers_reg[31][14] } {/theRegisters/\registers_reg[31][15] } {/theRegisters/\registers_reg[31][16] } {/theRegisters/\registers_reg[31][17] } {/theRegisters/\registers_reg[31][18] } {/theRegisters/\registers_reg[31][19] } {/theRegisters/\registers_reg[31][1] } {/theRegisters/\registers_reg[31][20] } {/theRegisters/\registers_reg[31][21] } {/theRegisters/\registers_reg[31][22] } {/theRegisters/\registers_reg[31][23] } {/theRegisters/\registers_reg[31][24] } {/theRegisters/\registers_reg[31][25] } {/theRegisters/\registers_reg[31][26] } {/theRegisters/\registers_reg[31][27] } {/theRegisters/\registers_reg[31][28] } {/theRegisters/\registers_reg[31][29] } {/theRegisters/\registers_reg[31][2] } {/theRegisters/\registers_reg[31][30] } {/theRegisters/\registers_reg[31][31] } {/theRegisters/\registers_reg[31][3] } {/theRegisters/\registers_reg[31][4] } {/theRegisters/\registers_reg[31][5] } {/theRegisters/\registers_reg[31][6] } {/theRegisters/\registers_reg[31][7] } {/theRegisters/\registers_reg[31][8] } {/theRegisters/\registers_reg[31][9] } {/theRegisters/\registers_reg[3][0] } {/theRegisters/\registers_reg[3][10] } {/theRegisters/\registers_reg[3][11] } {/theRegisters/\registers_reg[3][12] } {/theRegisters/\registers_reg[3][13] } {/theRegisters/\registers_reg[3][14] } {/theRegisters/\registers_reg[3][15] } {/theRegisters/\registers_reg[3][16] } {/theRegisters/\registers_reg[3][17] } {/theRegisters/\registers_reg[3][18] } {/theRegisters/\registers_reg[3][19] } {/theRegisters/\registers_reg[3][1] } {/theRegisters/\registers_reg[3][20] } {/theRegisters/\registers_reg[3][21] } {/theRegisters/\registers_reg[3][22] } {/theRegisters/\registers_reg[3][23] } {/theRegisters/\registers_reg[3][24] } {/theRegisters/\registers_reg[3][25] } {/theRegisters/\registers_reg[3][26] } {/theRegisters/\registers_reg[3][27] } {/theRegisters/\registers_reg[3][28] } {/theRegisters/\registers_reg[3][29] } {/theRegisters/\registers_reg[3][2] } {/theRegisters/\registers_reg[3][30] } {/theRegisters/\registers_reg[3][31] } {/theRegisters/\registers_reg[3][3] } {/theRegisters/\registers_reg[3][4] } {/theRegisters/\registers_reg[3][5] } {/theRegisters/\registers_reg[3][6] } {/theRegisters/\registers_reg[3][7] } {/theRegisters/\registers_reg[3][8] } {/theRegisters/\registers_reg[3][9] } {/theRegisters/\registers_reg[4][0] } {/theRegisters/\registers_reg[4][10] } {/theRegisters/\registers_reg[4][11] } {/theRegisters/\registers_reg[4][12] } {/theRegisters/\registers_reg[4][13] } {/theRegisters/\registers_reg[4][14] } {/theRegisters/\registers_reg[4][15] } {/theRegisters/\registers_reg[4][16] } {/theRegisters/\registers_reg[4][17] } {/theRegisters/\registers_reg[4][18] } {/theRegisters/\registers_reg[4][19] } {/theRegisters/\registers_reg[4][1] } {/theRegisters/\registers_reg[4][20] } {/theRegisters/\registers_reg[4][21] } {/theRegisters/\registers_reg[4][22] } {/theRegisters/\registers_reg[4][23] } {/theRegisters/\registers_reg[4][24] } {/theRegisters/\registers_reg[4][25] } {/theRegisters/\registers_reg[4][26] } {/theRegisters/\registers_reg[4][27] } {/theRegisters/\registers_reg[4][28] } {/theRegisters/\registers_reg[4][29] } {/theRegisters/\registers_reg[4][2] } {/theRegisters/\registers_reg[4][30] } {/theRegisters/\registers_reg[4][31] } {/theRegisters/\registers_reg[4][3] } {/theRegisters/\registers_reg[4][4] } {/theRegisters/\registers_reg[4][5] } {/theRegisters/\registers_reg[4][6] } {/theRegisters/\registers_reg[4][7] } {/theRegisters/\registers_reg[4][8] } {/theRegisters/\registers_reg[4][9] } {/theRegisters/\registers_reg[5][0] } {/theRegisters/\registers_reg[5][10] } {/theRegisters/\registers_reg[5][11] } {/theRegisters/\registers_reg[5][12] } {/theRegisters/\registers_reg[5][13] } {/theRegisters/\registers_reg[5][14] } {/theRegisters/\registers_reg[5][15] } {/theRegisters/\registers_reg[5][16] } {/theRegisters/\registers_reg[5][17] } {/theRegisters/\registers_reg[5][18] } {/theRegisters/\registers_reg[5][19] } {/theRegisters/\registers_reg[5][1] } {/theRegisters/\registers_reg[5][20] } {/theRegisters/\registers_reg[5][21] } {/theRegisters/\registers_reg[5][22] } {/theRegisters/\registers_reg[5][23] } {/theRegisters/\registers_reg[5][24] } {/theRegisters/\registers_reg[5][25] } {/theRegisters/\registers_reg[5][26] } {/theRegisters/\registers_reg[5][27] } {/theRegisters/\registers_reg[5][28] } {/theRegisters/\registers_reg[5][29] } {/theRegisters/\registers_reg[5][2] } {/theRegisters/\registers_reg[5][30] } {/theRegisters/\registers_reg[5][31] } {/theRegisters/\registers_reg[5][3] } {/theRegisters/\registers_reg[5][4] } {/theRegisters/\registers_reg[5][5] } {/theRegisters/\registers_reg[5][6] } {/theRegisters/\registers_reg[5][7] } {/theRegisters/\registers_reg[5][8] } {/theRegisters/\registers_reg[5][9] } {/theRegisters/\registers_reg[6][0] } {/theRegisters/\registers_reg[6][10] } {/theRegisters/\registers_reg[6][11] } {/theRegisters/\registers_reg[6][12] } {/theRegisters/\registers_reg[6][13] } {/theRegisters/\registers_reg[6][14] } {/theRegisters/\registers_reg[6][15] } {/theRegisters/\registers_reg[6][16] } {/theRegisters/\registers_reg[6][17] } {/theRegisters/\registers_reg[6][18] } {/theRegisters/\registers_reg[6][19] } {/theRegisters/\registers_reg[6][1] } {/theRegisters/\registers_reg[6][20] } {/theRegisters/\registers_reg[6][21] } {/theRegisters/\registers_reg[6][22] } {/theRegisters/\registers_reg[6][23] } {/theRegisters/\registers_reg[6][24] } {/theRegisters/\registers_reg[6][25] } {/theRegisters/\registers_reg[6][26] } {/theRegisters/\registers_reg[6][27] } {/theRegisters/\registers_reg[6][28] } {/theRegisters/\registers_reg[6][29] } {/theRegisters/\registers_reg[6][2] } {/theRegisters/\registers_reg[6][30] } {/theRegisters/\registers_reg[6][31] } {/theRegisters/\registers_reg[6][3] } {/theRegisters/\registers_reg[6][4] } {/theRegisters/\registers_reg[6][5] } {/theRegisters/\registers_reg[6][6] } {/theRegisters/\registers_reg[6][7] } {/theRegisters/\registers_reg[6][8] } {/theRegisters/\registers_reg[6][9] } {/theRegisters/\registers_reg[7][0] } {/theRegisters/\registers_reg[7][10] } {/theRegisters/\registers_reg[7][11] } {/theRegisters/\registers_reg[7][12] } {/theRegisters/\registers_reg[7][13] } {/theRegisters/\registers_reg[7][14] } {/theRegisters/\registers_reg[7][15] } {/theRegisters/\registers_reg[7][16] } {/theRegisters/\registers_reg[7][17] } {/theRegisters/\registers_reg[7][18] } {/theRegisters/\registers_reg[7][19] } {/theRegisters/\registers_reg[7][1] } {/theRegisters/\registers_reg[7][20] } {/theRegisters/\registers_reg[7][21] } {/theRegisters/\registers_reg[7][22] } {/theRegisters/\registers_reg[7][23] } {/theRegisters/\registers_reg[7][24] } {/theRegisters/\registers_reg[7][25] } {/theRegisters/\registers_reg[7][26] } {/theRegisters/\registers_reg[7][27] } {/theRegisters/\registers_reg[7][28] } {/theRegisters/\registers_reg[7][29] } {/theRegisters/\registers_reg[7][2] } {/theRegisters/\registers_reg[7][30] } {/theRegisters/\registers_reg[7][31] } {/theRegisters/\registers_reg[7][3] } {/theRegisters/\registers_reg[7][4] } {/theRegisters/\registers_reg[7][5] } {/theRegisters/\registers_reg[7][6] } {/theRegisters/\registers_reg[7][7] } {/theRegisters/\registers_reg[7][8] } {/theRegisters/\registers_reg[7][9] } {/theRegisters/\registers_reg[8][0] } {/theRegisters/\registers_reg[8][10] } {/theRegisters/\registers_reg[8][11] } {/theRegisters/\registers_reg[8][12] } {/theRegisters/\registers_reg[8][13] } {/theRegisters/\registers_reg[8][14] } {/theRegisters/\registers_reg[8][15] } {/theRegisters/\registers_reg[8][16] } {/theRegisters/\registers_reg[8][17] } {/theRegisters/\registers_reg[8][18] } {/theRegisters/\registers_reg[8][19] } {/theRegisters/\registers_reg[8][1] } {/theRegisters/\registers_reg[8][20] } {/theRegisters/\registers_reg[8][21] } {/theRegisters/\registers_reg[8][22] } {/theRegisters/\registers_reg[8][23] } {/theRegisters/\registers_reg[8][24] } {/theRegisters/\registers_reg[8][25] } {/theRegisters/\registers_reg[8][26] } {/theRegisters/\registers_reg[8][27] } {/theRegisters/\registers_reg[8][28] } {/theRegisters/\registers_reg[8][29] } {/theRegisters/\registers_reg[8][2] } {/theRegisters/\registers_reg[8][30] } {/theRegisters/\registers_reg[8][31] } {/theRegisters/\registers_reg[8][3] } {/theRegisters/\registers_reg[8][4] } {/theRegisters/\registers_reg[8][5] } {/theRegisters/\registers_reg[8][6] } {/theRegisters/\registers_reg[8][7] } {/theRegisters/\registers_reg[8][8] } {/theRegisters/\registers_reg[8][9] } {/theRegisters/\registers_reg[9][0] } {/theRegisters/\registers_reg[9][10] } {/theRegisters/\registers_reg[9][11] } {/theRegisters/\registers_reg[9][12] } {/theRegisters/\registers_reg[9][13] } {/theRegisters/\registers_reg[9][14] } {/theRegisters/\registers_reg[9][15] } {/theRegisters/\registers_reg[9][16] } {/theRegisters/\registers_reg[9][17] } {/theRegisters/\registers_reg[9][18] } {/theRegisters/\registers_reg[9][19] } {/theRegisters/\registers_reg[9][1] } {/theRegisters/\registers_reg[9][20] } {/theRegisters/\registers_reg[9][21] } {/theRegisters/\registers_reg[9][22] } {/theRegisters/\registers_reg[9][23] } {/theRegisters/\registers_reg[9][24] } {/theRegisters/\registers_reg[9][25] } {/theRegisters/\registers_reg[9][26] } {/theRegisters/\registers_reg[9][27] } {/theRegisters/\registers_reg[9][28] } {/theRegisters/\registers_reg[9][29] } {/theRegisters/\registers_reg[9][2] } {/theRegisters/\registers_reg[9][30] } {/theRegisters/\registers_reg[9][31] } {/theRegisters/\registers_reg[9][3] } {/theRegisters/\registers_reg[9][4] } {/theRegisters/\registers_reg[9][5] } {/theRegisters/\registers_reg[9][6] } {/theRegisters/\registers_reg[9][7] } {/theRegisters/\registers_reg[9][8] } {/theRegisters/\registers_reg[9][9] } " -si_connections "SI_4 " -so_connections "SO_4 " -chain_count 1 +// sub-command: analyze_scan_chains +// Chain allocation of 'unwrapped' mode completed: +// 4 distributed chains of size 256 +// sub-command: insert_test_logic -write_in_tsdb on +============================= +Test Logic Insertion Summary: +============================= + + Structural Data: + ---------------- + Added top-level port count: 0 + Added instance count: 8 + + Logical Data: + ------------- + Added retiming logic count: 4 + Added scan chain count (unwrapped): 4 + +// Warning: Flattened model deleted. +// +// Writing out netlist and related files in /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design +// sub-command: report_scan_chains + +=============================== +Scan Chains Created by the Tool +=============================== + + Scan mode 'unwrapped' scan chains: + ---------------------------------- + + Cluster 'scanChain_1' chains: + ----------------------------- + chain = scanChain_1 group = dummy input = /SI_1 output = /SO_1 length = 256 + + Cluster 'scanChain_2' chains: + ----------------------------- + chain = scanChain_2 group = dummy input = /SI_2 output = /SO_2 length = 256 + + Cluster 'scanChain_3' chains: + ----------------------------- + chain = scanChain_3 group = dummy input = /SI_3 output = /SO_3 length = 256 + + Cluster 'scanChain_4' chains: + ----------------------------- + chain = scanChain_4 group = dummy input = /SI_4 output = /SO_4 length = 256 + + +// sub-command: write_scan_order /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/Scan_0/cpu.scandef -use_escaping_rule Lefdef -replace +// sub-command: write_design -output_file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/Scan_0/post_scan.v -replace +// command: exit diff --git a/oasys.tessent.00/Scan_0/scan_enable_cluster.cfg b/oasys.tessent.00/Scan_0/scan_enable_cluster.cfg new file mode 100644 index 0000000..838af56 --- /dev/null +++ b/oasys.tessent.00/Scan_0/scan_enable_cluster.cfg @@ -0,0 +1,8 @@ +set_attribute_value [get_scan_elements -of_chain_families scanChain_1 ] -name cluster_name -value scanChain_1 + +set_attribute_value [get_scan_elements -of_chain_families scanChain_2 ] -name cluster_name -value scanChain_2 + +set_attribute_value [get_scan_elements -of_chain_families scanChain_3 ] -name cluster_name -value scanChain_3 + +set_attribute_value [get_scan_elements -of_chain_families scanChain_4 ] -name cluster_name -value scanChain_4 + diff --git a/oasys.tessent.00/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.scandef b/oasys.tessent.00/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.scandef new file mode 100644 index 0000000..6ae069e --- /dev/null +++ b/oasys.tessent.00/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.scandef @@ -0,0 +1,1071 @@ +# +# DESC: ScanDEF written by Tessent Shell on Thu May 28 17:29:02 CEST 2026 +# + +VERSION 5.7 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN cpu ; +UNITS DISTANCE MICRONS 1000 ; + +SCANCHAINS 4 ; + +- scan_segment_0 + + START tessent_persistent_cell_buf_extsi1225_i Z + + FLOATING + \thePC_CurrentPC_reg[30] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[29] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[28] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[27] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[26] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[25] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[24] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[23] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[22] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[21] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[20] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[19] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[18] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[17] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[16] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[15] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[14] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[13] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[12] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[11] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[10] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[9] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[8] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[7] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[6] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[5] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[4] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[3] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[2] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[31] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[1] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][0] ( IN SI ) ( OUT Q ) + + STOP theRegisters/ts_lockup_latchn_clkc1_intno1054_i D + # Partition constraints - clock domain: clk_25mhz(+); cluster: scanChain_1; chain type: core; scan mode(s): unwrapped + + PARTITION partition_1 MAXBITS 256 ; + + +- scan_segment_1 + + START theRegisters/tessent_persistent_cell_buf_extsi1226_i Z + + FLOATING + theRegisters/\registers_reg[1][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][0] ( IN SI ) ( OUT Q ) + + STOP theRegisters/ts_lockup_latchn_clkc2_intno1050_i D + # Partition constraints - clock domain: clk_25mhz(+); cluster: scanChain_2; chain type: core; scan mode(s): unwrapped + + PARTITION partition_2 MAXBITS 256 ; + + +- scan_segment_2 + + START theRegisters/tessent_persistent_cell_buf_extsi1227_i Z + + FLOATING + theRegisters/\registers_reg[28][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][0] ( IN SI ) ( OUT Q ) + + STOP theRegisters/ts_lockup_latchn_clkc3_intno1053_i D + # Partition constraints - clock domain: clk_25mhz(+); cluster: scanChain_3; chain type: core; scan mode(s): unwrapped + + PARTITION partition_3 MAXBITS 256 ; + + +- scan_segment_3 + + START theRegisters/tessent_persistent_cell_buf_extsi1228_i Z + + FLOATING + theRegisters/\registers_reg[4][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][0] ( IN SI ) ( OUT Q ) + + STOP theRegisters/ts_lockup_latchn_clkc4_intno1051_i D + # Partition constraints - clock domain: clk_25mhz(+); cluster: scanChain_4; chain type: core; scan mode(s): unwrapped + + PARTITION partition_4 MAXBITS 256 ; + + +END SCANCHAINS + +END DESIGN diff --git a/oasys.tessent.00/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.tcd b/oasys.tessent.00/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.tcd new file mode 100644 index 0000000..970c788 --- /dev/null +++ b/oasys.tessent.00/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.tcd @@ -0,0 +1,61 @@ +//-------------------------------------------------- +// File created by: Tessent Shell +// Version: 2023.4-p1 +// Created on: Thu May 28 17:29:02 CEST 2026 +//-------------------------------------------------- + + +Core(cpu) { + Scan { + allow_internal_pins : 1; + is_hard_module : 1; + exclude_from_concatenated_netlist : 1; + internal_scan_only : 1; + Mode(unwrapped) { + type : unwrapped; + traceable : 1; + make_active_automatically : 1; + ScanChain { + length : 256; + scan_in_clock : clk_25mhz; + scan_out_clock : ~clk_25mhz; + scan_in_port : SI_1; + scan_out_port : SO_1; + } + ScanChain { + length : 256; + scan_in_clock : clk_25mhz; + scan_out_clock : ~clk_25mhz; + scan_in_port : SI_2; + scan_out_port : SO_2; + } + ScanChain { + length : 256; + scan_in_clock : clk_25mhz; + scan_out_clock : ~clk_25mhz; + scan_in_port : SI_3; + scan_out_port : SO_3; + } + ScanChain { + length : 256; + scan_in_clock : clk_25mhz; + scan_out_clock : ~clk_25mhz; + scan_in_port : SI_4; + scan_out_port : SO_4; + } + ScanEn(scan_en) { + pipeline_count : 0; + active_polarity : all_ones; + } + Clock(clk_25mhz) { + off_state : 1'b0; + } + } + } + DesignInfo { + design_id : Scan_0; + design_level : physical_block; + ChildBlockModules { + } + } +} diff --git a/oasys.tessent.00/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.tsdb_info b/oasys.tessent.00/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.tsdb_info new file mode 100644 index 0000000..f7fd38c --- /dev/null +++ b/oasys.tessent.00/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.tsdb_info @@ -0,0 +1,23 @@ +//-------------------------------------------------- +// File created by: Tessent Shell +// Version: 2023.4-p1 +// Created on: Thu May 28 17:29:02 CEST 2026 +//-------------------------------------------------- + + +TsdbInfo(cpu,Scan_0) { + tessent_tool_version : 2023.4-p1; + tessent_meta_version : 10; + version : 3; + creation_date : Thu May 28 15:29:02 GMT 2026; + creation_user : charapallivenkatsaja; + creation_step : insert_test_logic; + level : physical_block; + icl_extraction_needed : Off; + library_name : work; + gate_extension : vg; + interface_has_external_dependencies : 0; + OpenedTsdbDirectories { + /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/tsdb_outdir; + } +} diff --git a/oasys.tessent.00/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.v_interface b/oasys.tessent.00/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.v_interface new file mode 100644 index 0000000..460314f --- /dev/null +++ b/oasys.tessent.00/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.v_interface @@ -0,0 +1,9 @@ +/* Generated by Tessent Shell 2023.4-p1 at Thu May 28 17:29:02 CEST 2026 */ +module cpu(led, btn, clk_25mhz, scan_en, SI_1, SO_1, SI_2, SO_2, SI_3, SO_3, SI_4, + SO_4); + input clk_25mhz, scan_en, SI_1, SI_2, SI_3, SI_4; + output SO_1, SO_2, SO_3, SO_4; + output [7:0] led; + input [6:0] btn; +endmodule + diff --git a/oasys.tessent.00/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.vg b/oasys.tessent.00/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.vg new file mode 100644 index 0000000..8235b48 --- /dev/null +++ b/oasys.tessent.00/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.vg @@ -0,0 +1,15792 @@ +/* Generated by Tessent Shell 2023.4-p1 at Thu May 28 17:29:02 CEST 2026 */ +module alu(aluOp, aluNegAr, aluBypass, op1, op2, result, eqFlag); + input [31:0] op1, op2; + input [2:0] aluOp; + input aluNegAr, aluBypass; + output [31:0] result; + output eqFlag; + + wire n_9_0, n_9_1, n_9_2, n_9_3, n_9_4, n_9_5, n_9_6, n_9_7, n_9_8, n_9_9, + n_9_10, n_9_11, n_9_12, n_9_13, n_9_14, n_9_15, n_9_16, n_9_17, n_9_18, + n_9_19, n_9_20, n_9_21, n_9_22, n_9_23, n_9_24, n_9_25, n_9_26, n_9_27, + n_9_28, n_9_29, n_9_30, n_9_31, n_10_0, n_10_1, n_10_2, n_10_3, n_10_4, + n_10_5, n_10_6, n_10_7, n_10_8, n_10_9, n_10_10, n_10_11, n_10_12, + n_10_13, n_10_14, n_10_15, n_10_16, n_10_17, n_10_18, n_10_19, n_10_20, + n_10_21, n_10_22, n_10_23, n_10_24, n_10_25, n_10_26, n_10_27, n_10_28, + n_10_29, n_10_30, n_10_31, n_10_32, n_10_33, n_10_34, n_10_35, n_10_36, + n_10_37, n_10_38, n_10_39, n_10_40, n_10_41, n_10_42, n_10_43, n_10_44, + n_10_45, n_10_46, n_10_47, n_10_48, n_10_49, n_10_50, n_10_51, n_10_52, + n_10_53, n_10_54, n_10_55, n_10_56, n_10_57, n_10_58, n_10_59, n_10_60, + n_10_61, n_10_62, n_10_63, n_10_64, n_10_65, n_10_66, n_10_67, n_10_68, + n_10_69, n_10_70, n_10_71, n_10_72, n_10_73, n_10_74, n_10_75, n_10_76, + n_10_77, n_10_78, n_10_79, n_10_80, n_10_81, n_10_82, n_10_83, n_10_84, + n_10_85, n_10_86, n_10_87, n_10_88, n_10_89, n_10_90, n_10_91, n_10_92, + n_10_93, n_10_94, n_10_95, n_10_96, n_10_97, n_10_98, n_10_99, n_10_100, + n_10_101, n_10_102, n_10_103, n_10_104, n_10_105, n_10_106, n_10_107, + n_10_108, n_10_109, n_10_110, n_10_111, n_10_112, n_10_113, n_10_114, + n_10_115, n_10_116, n_10_117, n_10_118, n_10_119, n_10_120, n_10_121, + n_10_122, n_10_123, n_0_0, n_0_1, n_0_2, n_0_3, n_0_4, n_0_5, n_0_6, + n_0_7, n_0_8, n_0_9, n_0_10, n_0_11, n_0_12, n_0_13, n_0_14, n_0_15, + n_0_16, n_0_17, n_0_18, n_0_19, n_0_20, n_0_21, n_0_22, n_0_23, n_0_24, + n_0_25, n_0_26, n_0_27, n_0_28, n_0_29, n_0_30, n_0_31, n_0_32, n_0_33, + n_0_34, n_0_35, n_0_36, n_0_37, n_0_38, n_0_39, n_0_40, n_0_41, n_0_42, + n_0_43, n_0_44, n_0_45, n_0_46, n_0_47, n_0_48, n_0_49, n_0_50, n_0_51, + n_0_52, n_0_53, n_0_54, n_0_55, n_0_56, n_0_57, n_0_58, n_0_59, n_0_60, + n_0_61, n_0_62, n_0_63, n_0_64, n_0_65, n_0_66, n_0_67, n_0_68, n_0_69, + n_0_70, n_0_71, n_0_72, n_0_73, n_0_74, n_0_75, n_0_76, n_0_77, n_0_78, + n_0_79, n_0_80, n_0_81, n_0_82, n_0_83, n_0_84, n_0_85, n_0_86, n_0_87, + n_0_88, n_0_89, n_0_90, n_0_91, n_0_92, n_0_93, n_0_94, n_0_95, n_0_96, + n_0_97, n_0_98, n_0_99, n_0_100, n_0_101, n_0_102, n_0_103, n_0_104, + n_0_105, n_0_106, n_0_107, n_0_108, n_0_109, n_0_110, n_0_111, n_0_112, + n_0_113, n_0_114, n_0_115, n_0_116, n_0_117, n_0_118, n_0_119, n_0_120, + n_0_121, n_0_122, n_0_123, n_0_124, n_0_125, n_0_126, n_0_127, n_0_128, + n_0_129, n_0_130, n_0_131, n_0_132, n_0_133, n_0_134, n_0_135, n_0_136, + n_0_137, n_0_138, n_0_139, n_0_140, n_0_141, n_0_142, n_0_143, n_0_144, + n_0_145, n_0_146, n_0_147, n_0_148, n_0_149, n_0_150, n_0_151, n_0_152, + n_0_153, n_0_154, n_0_155, n_0_156, n_0_157, n_0_158, n_0_159, n_0_160, + n_0_161, n_0_162, n_0_163, n_0_164, n_0_165, n_0_166, n_0_167, n_0_168, + n_0_169, n_0_170, n_0_171, n_0_172, n_0_173, n_0_174, n_0_175, n_0_176, + n_0_177, n_0_178, n_0_179, n_0_180, n_0_181, n_0_182, n_0_183, n_0_184, + n_0_185, n_0_186, n_0_187, n_0_188, n_0_189, n_0_190, n_0_191, n_0_192, + n_0_193, n_0_194, n_0_195, n_0_196, n_0_197, n_0_198, n_0_199, n_0_200, + n_0_201, n_0_202, n_0_203, n_0_204, n_0_205, n_0_206, n_0_207, n_0_208, + n_0_209, n_0_210, n_0_211, n_0_212, n_0_213, n_0_214, n_0_215, n_0_216, + n_0_217, n_0_218, n_0_219, n_0_220, n_0_221, n_0_222, n_0_223, n_0_224, + n_0_225, n_0_226, n_0_227, n_0_228, n_0_229, n_0_230, n_0_231, n_0_232, + n_0_233, n_0_234, n_0_235, n_0_236, n_0_237, n_0_238, n_0_239, n_0_240, + n_0_241, n_0_242, n_0_243, n_0_244, n_0_245, n_0_246, n_0_247, n_0_248, + n_0_249, n_0_250, n_0_251, n_0_252, n_0_253, n_0_254, n_0_255, n_0_256, + n_0_257, n_0_258, n_0_259, n_0_260, n_0_261, n_0_262, n_0_263, n_0_264, + n_0_265, n_0_266, n_0_267, n_0_268, n_0_269, n_0_270, n_0_271, n_0_272, + n_0_273, n_0_274, n_0_275, n_0_276, n_0_277, n_0_278, n_0_279, n_0_280, + n_0_281, n_0_282, n_0_283, n_0_284, n_0_285, n_0_286, n_0_287, n_0_288, + n_0_289, n_0_290, n_0_291, n_0_292, n_0_293, n_0_294, n_0_295, n_0_296, + n_0_297, n_0_298, n_0_299, n_0_300, n_0_301, n_0_302, n_0_303, n_0_304, + n_0_305, n_0_306, n_0_307, n_0_308, n_0_309, n_0_310, n_0_311, n_0_312, + n_0_313, n_0_314, n_0_315, n_0_316, n_0_317, n_0_318, n_0_319, n_0_320, + n_0_321, n_0_322, n_0_323, n_0_324, n_0_325, n_0_326, n_0_327, n_0_328, + n_0_329, n_0_330, n_0_331, n_0_332, n_0_333, n_0_334, n_0_335, n_0_336, + n_0_337, n_0_338, n_0_339, n_0_340, n_0_341, n_0_342, n_0_343, n_0_344, + n_0_345, n_0_346, n_0_347, n_0_348, n_0_349, n_0_350, n_0_351, n_0_352, + n_0_353, n_0_354, n_0_355, n_0_356, n_0_357, n_0_358, n_0_359, n_0_360, + n_0_361, n_0_362, n_0_363, n_0_364, n_0_365, n_0_366, n_0_367, n_0_368, + n_0_369, n_0_370, n_0_371, n_0_372, n_0_373, n_0_374, n_0_375, n_0_376, + n_0_377, n_0_378, n_0_379, n_0_380, n_0_381, n_0_382, n_0_383, n_0_384, + n_0_385, n_0_386, n_0_387, n_0_388, n_0_389, n_0_390, n_0_391, n_0_392, + n_0_393, n_0_394, n_0_395, n_0_396, n_0_397, n_0_398, n_0_399, n_0_400, + n_0_401, n_0_402, n_0_403, n_0_404, n_0_405, n_0_406, n_0_407, n_0_408, + n_0_409, n_0_410, n_0_411, n_0_412, n_0_413, n_0_414, n_0_415, n_0_416, + n_0_417, n_0_418, n_0_419, n_0_420, n_0_421, n_0_422, n_0_423, n_0_424, + n_0_425, n_0_426, n_0_427, n_0_428, n_0_429, n_0_430, n_0_431, n_0_432, + n_0_433, n_0_434, n_0_435, n_0_436, n_0_437, n_0_438, n_0_439, n_0_440, + n_0_441, n_0_442, n_0_443, n_0_444, n_0_445, n_0_446, n_0_447, n_0_448, + n_0_449, n_0_450, n_0_451, n_0_452, n_0_453, n_0_454, n_0_455, n_0_456, + n_0_457, n_0_458, n_0_459, n_0_460, n_0_461, n_0_462, n_0_463, n_0_464, + n_0_465, n_0_466, n_0_467, n_0_468, n_0_469, n_0_470, n_0_471, n_0_472, + n_0_473, n_0_474, n_0_475, n_0_476, n_0_477, n_0_478, n_0_479, n_0_480, + n_0_481, n_0_482, n_0_483, n_0_484, n_0_485, n_0_486, n_0_487, n_0_488, + n_0_489, n_0_490, n_0_491, n_0_492, n_0_493, n_0_494, n_0_495, n_0_496, + n_0_497, n_0_498, n_0_499, n_0_500, n_0_501, n_0_502, n_0_503, n_0_504, + n_0_505, n_0_506, n_0_507, n_0_508, n_0_509, n_0_510, n_0_511, n_0_512, + n_0_513, n_0_514, n_0_515, n_0_516, n_0_517, n_0_518, n_0_519, n_0_520, + n_0_521, n_0_522, n_0_523, n_0_524, n_0_525, n_0_526, n_0_527, n_0_528, + n_0_529, n_0_530, n_0_531, n_0_532, n_0_533, n_0_534, n_0_535, n_0_536, + n_0_537, n_0_538, n_0_539, n_0_540, n_0_541, n_0_542, n_0_543, n_0_544, + n_0_545, n_0_546, n_0_547, n_0_548, n_0_549, n_0_550, n_0_551, n_0_552, + n_0_553, n_0_554, n_0_555, n_0_556, n_0_557, n_0_558, n_0_559, n_0_560, + n_0_561, n_0_562, n_0_563, n_0_564, n_0_565, n_0_566, n_0_567, n_0_568, + n_0_569, n_0_570, n_0_571, n_0_572, n_0_573, n_0_574, n_0_575, n_0_576, + n_0_577, n_0_578, n_0_579, n_0_580, n_0_581, n_0_582, n_0_583, n_0_584, + n_0_585, n_0_586, n_0_587, n_0_588, n_0_589, n_0_590, n_0_591, n_0_592, + n_0_593, n_0_594, n_0_595, n_0_596, n_0_597, n_0_598, n_0_599, n_0_600, + n_0_601, n_0_602, n_0_603, n_0_604, n_0_605, n_0_606, n_0_607, n_0_608, + n_0_609, n_0_610, n_0_611, n_0_612, n_0_613, n_0_614, n_0_615, n_0_616, + n_0_617, n_0_618, n_0_619, n_0_620, n_0_621, n_0_622, n_0_623, n_0_624, + n_0_625, n_0_626, n_0_627, n_0_628, n_0_629, n_0_630, n_0_631, n_0_632, + n_0_633, n_0_634, n_0_635, n_0_636, n_0_637, n_0_638, n_0_639, n_0_640, + n_0_641, n_0_642, n_0_643, n_0_644, n_0_645, n_0_646, n_0_647, n_0_648, + n_0_649, n_0_650, n_0_651, n_0_652, n_0_653, n_0_654, n_0_655, n_0_656, + n_0_657, n_0_658, n_0_659, n_0_660, n_0_661, n_0_662, n_0_663, n_0_664, + n_0_665, n_0_666, n_0_667, n_0_668, n_0_669, n_0_670, n_0_671, n_0_672, + n_0_673, n_0_674, n_0_675, n_0_676, n_0_677, n_0_678, n_0_679, n_0_680, + n_0_681, n_0_682, n_0_683, n_0_684, n_0_685, n_0_686, n_0_687, n_0_688, + n_0_689, n_0_690, n_0_691, n_0_692, n_0_693, n_0_694, n_0_695, n_0_696, + n_0_697, n_0_698, n_0_699, n_0_700, n_0_701, n_0_702, n_0_703, n_0_704, + n_0_705, n_0_706, n_0_707, n_0_708, n_0_709, n_0_710, n_0_711, n_0_712, + n_0_713, n_0_714, n_0_715, n_0_716, n_0_717, n_0_718, n_0_719, n_0_720, + n_0_721, n_0_722, n_0_723, n_0_724, n_0_725, n_0_726, n_0_727, n_0_728, + n_0_729, n_0_730, n_0_731, n_0_732, n_0_733, n_0_734, n_0_735, n_0_736, + n_0_737, n_0_738, n_0_739, n_0_740, n_0, n_1, n_2, n_3, n_4, n_5, n_6, + n_7, n_8, n_9, n_10, n_11, n_12, n_13, n_14, n_15, n_16, n_17, n_18, + n_19, n_20, n_21, n_22, n_23, n_24, n_25, n_26, n_27, n_28, n_29, n_30, + n_31, n_63, n_62, n_61, n_60, n_59, n_58, n_57, n_56, n_55, n_54, n_53, + n_52, n_51, n_50, n_49, n_48, n_47, n_46, n_45, n_44, n_43, n_42, n_41, + n_40, n_39, n_38, n_37, n_36, n_35, n_34, n_33, n_32; + + INV_X1_LVT i_0_725( + .A(op2[31]), .ZN(n_0_692) + ); + INV_X1_LVT i_0_724( + .A(op1[31]), .ZN(n_0_691) + ); + INV_X1_LVT i_0_718( + .A(aluOp[1]), .ZN(n_0_685) + ); + INV_X1_LVT i_0_717( + .A(aluOp[2]), .ZN(n_0_684) + ); + NOR2_X1_LVT i_0_599( + .A1(n_0_685), .A2(n_0_684), .ZN(n_0_567) + ); + INV_X1_LVT i_0_598( + .A(n_0_567), .ZN(n_0_566) + ); + INV_X1_LVT i_0_716( + .A(aluOp[0]), .ZN(n_0_683) + ); + NAND2_X1_LVT i_0_602( + .A1(aluOp[2]), .A2(aluNegAr), .ZN(n_0_570) + ); + OAI21_X1_LVT i_0_590( + .A(n_0_566), .B1(n_0_683), .B2(n_0_570), .ZN(n_0_558) + ); + INV_X1_LVT i_0_714( + .A(aluBypass), .ZN(n_0_681) + ); + NOR2_X1_LVT i_0_601( + .A1(n_0_684), .A2(aluOp[0]), .ZN(n_0_569) + ); + NAND2_X1_LVT i_0_597( + .A1(n_0_681), .A2(n_0_569), .ZN(n_0_565) + ); + INV_X1_LVT i_0_596( + .A(n_0_565), .ZN(n_0_564) + ); + OAI22_X1_LVT i_0_589( + .A1(n_0_691), .A2(n_0_558), .B1(op1[31]), .B2(n_0_564), .ZN(n_0_557) + ); + NOR2_X1_LVT i_0_588( + .A1(n_0_692), .A2(n_0_557), .ZN(n_0_556) + ); + XNOR2_X1_LVT i_9_31( + .A(op2[31]), .B(op1[31]), .ZN(n_9_31) + ); + HA_X1_LVT i_9_0( + .A(op2[0]), .B(op1[0]), .CO(n_9_0), .S(n_0) + ); + FA_X1_LVT i_9_1( + .A(op2[1]), .B(op1[1]), .CI(n_9_0), .CO(n_9_1), .S(n_1) + ); + FA_X1_LVT i_9_2( + .A(op2[2]), .B(op1[2]), .CI(n_9_1), .CO(n_9_2), .S(n_2) + ); + FA_X1_LVT i_9_3( + .A(op2[3]), .B(op1[3]), .CI(n_9_2), .CO(n_9_3), .S(n_3) + ); + FA_X1_LVT i_9_4( + .A(op2[4]), .B(op1[4]), .CI(n_9_3), .CO(n_9_4), .S(n_4) + ); + FA_X1_LVT i_9_5( + .A(op2[5]), .B(op1[5]), .CI(n_9_4), .CO(n_9_5), .S(n_5) + ); + FA_X1_LVT i_9_6( + .A(op2[6]), .B(op1[6]), .CI(n_9_5), .CO(n_9_6), .S(n_6) + ); + FA_X1_LVT i_9_7( + .A(op2[7]), .B(op1[7]), .CI(n_9_6), .CO(n_9_7), .S(n_7) + ); + FA_X1_LVT i_9_8( + .A(op2[8]), .B(op1[8]), .CI(n_9_7), .CO(n_9_8), .S(n_8) + ); + FA_X1_LVT i_9_9( + .A(op2[9]), .B(op1[9]), .CI(n_9_8), .CO(n_9_9), .S(n_9) + ); + FA_X1_LVT i_9_10( + .A(op2[10]), .B(op1[10]), .CI(n_9_9), .CO(n_9_10), .S(n_10) + ); + FA_X1_LVT i_9_11( + .A(op2[11]), .B(op1[11]), .CI(n_9_10), .CO(n_9_11), .S(n_11) + ); + FA_X1_LVT i_9_12( + .A(op2[12]), .B(op1[12]), .CI(n_9_11), .CO(n_9_12), .S(n_12) + ); + FA_X1_LVT i_9_13( + .A(op2[13]), .B(op1[13]), .CI(n_9_12), .CO(n_9_13), .S(n_13) + ); + FA_X1_LVT i_9_14( + .A(op2[14]), .B(op1[14]), .CI(n_9_13), .CO(n_9_14), .S(n_14) + ); + FA_X1_LVT i_9_15( + .A(op2[15]), .B(op1[15]), .CI(n_9_14), .CO(n_9_15), .S(n_15) + ); + FA_X1_LVT i_9_16( + .A(op2[16]), .B(op1[16]), .CI(n_9_15), .CO(n_9_16), .S(n_16) + ); + FA_X1_LVT i_9_17( + .A(op2[17]), .B(op1[17]), .CI(n_9_16), .CO(n_9_17), .S(n_17) + ); + FA_X1_LVT i_9_18( + .A(op2[18]), .B(op1[18]), .CI(n_9_17), .CO(n_9_18), .S(n_18) + ); + FA_X1_LVT i_9_19( + .A(op2[19]), .B(op1[19]), .CI(n_9_18), .CO(n_9_19), .S(n_19) + ); + FA_X1_LVT i_9_20( + .A(op2[20]), .B(op1[20]), .CI(n_9_19), .CO(n_9_20), .S(n_20) + ); + FA_X1_LVT i_9_21( + .A(op2[21]), .B(op1[21]), .CI(n_9_20), .CO(n_9_21), .S(n_21) + ); + FA_X1_LVT i_9_22( + .A(op2[22]), .B(op1[22]), .CI(n_9_21), .CO(n_9_22), .S(n_22) + ); + FA_X1_LVT i_9_23( + .A(op2[23]), .B(op1[23]), .CI(n_9_22), .CO(n_9_23), .S(n_23) + ); + FA_X1_LVT i_9_24( + .A(op2[24]), .B(op1[24]), .CI(n_9_23), .CO(n_9_24), .S(n_24) + ); + FA_X1_LVT i_9_25( + .A(op2[25]), .B(op1[25]), .CI(n_9_24), .CO(n_9_25), .S(n_25) + ); + FA_X1_LVT i_9_26( + .A(op2[26]), .B(op1[26]), .CI(n_9_25), .CO(n_9_26), .S(n_26) + ); + FA_X1_LVT i_9_27( + .A(op2[27]), .B(op1[27]), .CI(n_9_26), .CO(n_9_27), .S(n_27) + ); + FA_X1_LVT i_9_28( + .A(op2[28]), .B(op1[28]), .CI(n_9_27), .CO(n_9_28), .S(n_28) + ); + FA_X1_LVT i_9_29( + .A(op2[29]), .B(op1[29]), .CI(n_9_28), .CO(n_9_29), .S(n_29) + ); + FA_X1_LVT i_9_30( + .A(op2[30]), .B(op1[30]), .CI(n_9_29), .CO(n_9_30), .S(n_30) + ); + XNOR2_X1_LVT i_9_32( + .A(n_9_31), .B(n_9_30), .ZN(n_31) + ); + NAND4_X1_LVT i_0_614( + .A1(n_0_685), .A2(n_0_681), .A3(n_0_684), .A4(n_0_683), .ZN(n_0_582) + ); + NOR2_X1_LVT i_0_613( + .A1(aluNegAr), .A2(n_0_582), .ZN(n_0_581) + ); + INV_X1_LVT i_10_147( + .A(op2[30]), .ZN(n_10_117) + ); + NAND2_X1_LVT i_10_149( + .A1(n_10_117), .A2(op1[30]), .ZN(n_10_119) + ); + INV_X1_LVT i_10_152( + .A(n_10_119), .ZN(n_10_121) + ); + INV_X1_LVT i_10_130( + .A(op1[26]), .ZN(n_10_104) + ); + NAND2_X1_LVT i_10_131( + .A1(n_10_104), .A2(op2[26]), .ZN(n_10_105) + ); + INV_X1_LVT i_10_123( + .A(op2[25]), .ZN(n_10_98) + ); + NAND2_X1_LVT i_10_125( + .A1(n_10_98), .A2(op1[25]), .ZN(n_10_100) + ); + INV_X1_LVT i_10_112( + .A(op2[23]), .ZN(n_10_89) + ); + NAND2_X1_LVT i_10_114( + .A1(n_10_89), .A2(op1[23]), .ZN(n_10_91) + ); + INV_X1_LVT i_10_101( + .A(op2[21]), .ZN(n_10_80) + ); + NAND2_X1_LVT i_10_103( + .A1(n_10_80), .A2(op1[21]), .ZN(n_10_82) + ); + INV_X1_LVT i_10_48( + .A(op1[8]), .ZN(n_10_40) + ); + NAND2_X1_LVT i_10_49( + .A1(n_10_40), .A2(op2[8]), .ZN(n_10_41) + ); + INV_X1_LVT i_10_41( + .A(op2[7]), .ZN(n_10_34) + ); + NAND2_X1_LVT i_10_43( + .A1(n_10_34), .A2(op1[7]), .ZN(n_10_36) + ); + INV_X1_LVT i_10_32( + .A(op2[5]), .ZN(n_10_27) + ); + NOR2_X1_LVT i_10_33( + .A1(n_10_27), .A2(op1[5]), .ZN(n_10_28) + ); + INV_X1_LVT i_10_24( + .A(op1[4]), .ZN(n_10_20) + ); + NOR2_X1_LVT i_10_27( + .A1(n_10_20), .A2(op2[4]), .ZN(n_10_23) + ); + INV_X1_LVT i_10_17( + .A(op2[3]), .ZN(n_10_14) + ); + NAND2_X1_LVT i_10_19( + .A1(n_10_14), .A2(op1[3]), .ZN(n_10_16) + ); + INV_X1_LVT i_10_22( + .A(n_10_16), .ZN(n_10_18) + ); + INV_X1_LVT i_10_10( + .A(op2[2]), .ZN(n_10_8) + ); + NAND2_X1_LVT i_10_12( + .A1(n_10_8), .A2(op1[2]), .ZN(n_10_10) + ); + INV_X1_LVT i_10_3( + .A(op1[1]), .ZN(n_10_2) + ); + NAND2_X1_LVT i_10_5( + .A1(n_10_2), .A2(op2[1]), .ZN(n_10_4) + ); + INV_X1_LVT i_10_0( + .A(op1[0]), .ZN(n_10_0) + ); + NAND2_X1_LVT i_10_1( + .A1(n_10_0), .A2(op2[0]), .ZN(n_10_1) + ); + OR2_X1_LVT i_10_4( + .A1(n_10_2), .A2(op2[1]), .ZN(n_10_3) + ); + INV_X1_LVT i_10_8( + .A(n_10_3), .ZN(n_10_6) + ); + OAI21_X1_LVT i_10_9( + .A(n_10_4), .B1(n_10_1), .B2(n_10_6), .ZN(n_10_7) + ); + NOR2_X1_LVT i_10_11( + .A1(n_10_8), .A2(op1[2]), .ZN(n_10_9) + ); + OAI21_X1_LVT i_10_16( + .A(n_10_10), .B1(n_10_7), .B2(n_10_9), .ZN(n_10_13) + ); + OR2_X1_LVT i_10_18( + .A1(n_10_14), .A2(op1[3]), .ZN(n_10_15) + ); + AOI21_X1_LVT i_10_23( + .A(n_10_18), .B1(n_10_13), .B2(n_10_15), .ZN(n_10_19) + ); + INV_X1_LVT i_10_30( + .A(n_10_19), .ZN(n_10_25) + ); + NAND2_X1_LVT i_10_25( + .A1(n_10_20), .A2(op2[4]), .ZN(n_10_21) + ); + AOI21_X1_LVT i_10_31( + .A(n_10_23), .B1(n_10_25), .B2(n_10_21), .ZN(n_10_26) + ); + AOI21_X1_LVT i_10_34( + .A(n_10_28), .B1(n_10_27), .B2(op1[5]), .ZN(n_10_29) + ); + AOI21_X1_LVT i_10_36( + .A(n_10_28), .B1(n_10_26), .B2(n_10_29), .ZN(n_10_30) + ); + XOR2_X1_LVT i_10_37( + .A(op2[6]), .B(op1[6]), .Z(n_10_31) + ); + INV_X1_LVT i_10_39( + .A(op2[6]), .ZN(n_10_32) + ); + OAI22_X1_LVT i_10_40( + .A1(n_10_30), .A2(n_10_31), .B1(n_10_32), .B2(op1[6]), .ZN(n_10_33) + ); + NOR2_X1_LVT i_10_42( + .A1(n_10_34), .A2(op1[7]), .ZN(n_10_35) + ); + OAI21_X1_LVT i_10_47( + .A(n_10_36), .B1(n_10_33), .B2(n_10_35), .ZN(n_10_39) + ); + OAI21_X1_LVT i_10_50( + .A(n_10_41), .B1(n_10_40), .B2(op2[8]), .ZN(n_10_42) + ); + OAI21_X1_LVT i_10_52( + .A(n_10_41), .B1(n_10_39), .B2(n_10_42), .ZN(n_10_43) + ); + XNOR2_X1_LVT i_10_53( + .A(op2[9]), .B(op1[9]), .ZN(n_10_44) + ); + INV_X1_LVT i_10_55( + .A(op1[9]), .ZN(n_10_45) + ); + AOI22_X1_LVT i_10_56( + .A1(n_10_43), .A2(n_10_44), .B1(n_10_45), .B2(op2[9]), .ZN(n_10_46) + ); + XOR2_X1_LVT i_10_57( + .A(op2[10]), .B(op1[10]), .Z(n_10_47) + ); + INV_X1_LVT i_10_59( + .A(op2[10]), .ZN(n_10_48) + ); + OAI22_X1_LVT i_10_60( + .A1(n_10_46), .A2(n_10_47), .B1(n_10_48), .B2(op1[10]), .ZN(n_10_49) + ); + XNOR2_X1_LVT i_10_61( + .A(op2[11]), .B(op1[11]), .ZN(n_10_50) + ); + INV_X1_LVT i_10_63( + .A(op1[11]), .ZN(n_10_51) + ); + AOI22_X1_LVT i_10_64( + .A1(n_10_49), .A2(n_10_50), .B1(n_10_51), .B2(op2[11]), .ZN(n_10_52) + ); + XOR2_X1_LVT i_10_65( + .A(op2[12]), .B(op1[12]), .Z(n_10_53) + ); + INV_X1_LVT i_10_67( + .A(op2[12]), .ZN(n_10_54) + ); + OAI22_X1_LVT i_10_68( + .A1(n_10_52), .A2(n_10_53), .B1(n_10_54), .B2(op1[12]), .ZN(n_10_55) + ); + XNOR2_X1_LVT i_10_69( + .A(op2[13]), .B(op1[13]), .ZN(n_10_56) + ); + INV_X1_LVT i_10_71( + .A(op1[13]), .ZN(n_10_57) + ); + AOI22_X1_LVT i_10_72( + .A1(n_10_55), .A2(n_10_56), .B1(n_10_57), .B2(op2[13]), .ZN(n_10_58) + ); + XOR2_X1_LVT i_10_73( + .A(op2[14]), .B(op1[14]), .Z(n_10_59) + ); + INV_X1_LVT i_10_75( + .A(op2[14]), .ZN(n_10_60) + ); + OAI22_X1_LVT i_10_76( + .A1(n_10_58), .A2(n_10_59), .B1(n_10_60), .B2(op1[14]), .ZN(n_10_61) + ); + XNOR2_X1_LVT i_10_77( + .A(op2[15]), .B(op1[15]), .ZN(n_10_62) + ); + INV_X1_LVT i_10_79( + .A(op1[15]), .ZN(n_10_63) + ); + AOI22_X1_LVT i_10_80( + .A1(n_10_61), .A2(n_10_62), .B1(n_10_63), .B2(op2[15]), .ZN(n_10_64) + ); + XOR2_X1_LVT i_10_81( + .A(op2[16]), .B(op1[16]), .Z(n_10_65) + ); + INV_X1_LVT i_10_83( + .A(op2[16]), .ZN(n_10_66) + ); + OAI22_X1_LVT i_10_84( + .A1(n_10_64), .A2(n_10_65), .B1(n_10_66), .B2(op1[16]), .ZN(n_10_67) + ); + XNOR2_X1_LVT i_10_85( + .A(op2[17]), .B(op1[17]), .ZN(n_10_68) + ); + INV_X1_LVT i_10_87( + .A(op1[17]), .ZN(n_10_69) + ); + AOI22_X1_LVT i_10_88( + .A1(n_10_67), .A2(n_10_68), .B1(n_10_69), .B2(op2[17]), .ZN(n_10_70) + ); + XOR2_X1_LVT i_10_89( + .A(op2[18]), .B(op1[18]), .Z(n_10_71) + ); + INV_X1_LVT i_10_91( + .A(op2[18]), .ZN(n_10_72) + ); + OAI22_X1_LVT i_10_92( + .A1(n_10_70), .A2(n_10_71), .B1(n_10_72), .B2(op1[18]), .ZN(n_10_73) + ); + XNOR2_X1_LVT i_10_93( + .A(op2[19]), .B(op1[19]), .ZN(n_10_74) + ); + INV_X1_LVT i_10_95( + .A(op1[19]), .ZN(n_10_75) + ); + AOI22_X1_LVT i_10_96( + .A1(n_10_73), .A2(n_10_74), .B1(n_10_75), .B2(op2[19]), .ZN(n_10_76) + ); + XOR2_X1_LVT i_10_97( + .A(op2[20]), .B(op1[20]), .Z(n_10_77) + ); + INV_X1_LVT i_10_99( + .A(op2[20]), .ZN(n_10_78) + ); + OAI22_X1_LVT i_10_100( + .A1(n_10_76), .A2(n_10_77), .B1(n_10_78), .B2(op1[20]), .ZN(n_10_79) + ); + NOR2_X1_LVT i_10_102( + .A1(n_10_80), .A2(op1[21]), .ZN(n_10_81) + ); + OAI21_X1_LVT i_10_107( + .A(n_10_82), .B1(n_10_79), .B2(n_10_81), .ZN(n_10_85) + ); + XOR2_X1_LVT i_10_108( + .A(op2[22]), .B(op1[22]), .Z(n_10_86) + ); + INV_X1_LVT i_10_110( + .A(op2[22]), .ZN(n_10_87) + ); + OAI22_X1_LVT i_10_111( + .A1(n_10_85), .A2(n_10_86), .B1(n_10_87), .B2(op1[22]), .ZN(n_10_88) + ); + NOR2_X1_LVT i_10_113( + .A1(n_10_89), .A2(op1[23]), .ZN(n_10_90) + ); + OAI21_X1_LVT i_10_118( + .A(n_10_91), .B1(n_10_88), .B2(n_10_90), .ZN(n_10_94) + ); + XOR2_X1_LVT i_10_119( + .A(op2[24]), .B(op1[24]), .Z(n_10_95) + ); + INV_X1_LVT i_10_121( + .A(op2[24]), .ZN(n_10_96) + ); + OAI22_X1_LVT i_10_122( + .A1(n_10_94), .A2(n_10_95), .B1(n_10_96), .B2(op1[24]), .ZN(n_10_97) + ); + NOR2_X1_LVT i_10_124( + .A1(n_10_98), .A2(op1[25]), .ZN(n_10_99) + ); + OAI21_X1_LVT i_10_129( + .A(n_10_100), .B1(n_10_97), .B2(n_10_99), .ZN(n_10_103) + ); + OAI21_X1_LVT i_10_132( + .A(n_10_105), .B1(n_10_104), .B2(op2[26]), .ZN(n_10_106) + ); + OAI21_X1_LVT i_10_134( + .A(n_10_105), .B1(n_10_103), .B2(n_10_106), .ZN(n_10_107) + ); + XNOR2_X1_LVT i_10_135( + .A(op2[27]), .B(op1[27]), .ZN(n_10_108) + ); + INV_X1_LVT i_10_137( + .A(op1[27]), .ZN(n_10_109) + ); + AOI22_X1_LVT i_10_138( + .A1(n_10_107), .A2(n_10_108), .B1(n_10_109), .B2(op2[27]), .ZN(n_10_110) + ); + XOR2_X1_LVT i_10_139( + .A(op2[28]), .B(op1[28]), .Z(n_10_111) + ); + INV_X1_LVT i_10_141( + .A(op2[28]), .ZN(n_10_112) + ); + OAI22_X1_LVT i_10_142( + .A1(n_10_110), .A2(n_10_111), .B1(n_10_112), .B2(op1[28]), .ZN(n_10_113) + ); + XNOR2_X1_LVT i_10_143( + .A(op2[29]), .B(op1[29]), .ZN(n_10_114) + ); + INV_X1_LVT i_10_145( + .A(op1[29]), .ZN(n_10_115) + ); + AOI22_X1_LVT i_10_146( + .A1(n_10_113), .A2(n_10_114), .B1(n_10_115), .B2(op2[29]), .ZN(n_10_116) + ); + OR2_X1_LVT i_10_148( + .A1(n_10_117), .A2(op1[30]), .ZN(n_10_118) + ); + AOI21_X1_LVT i_10_153( + .A(n_10_121), .B1(n_10_116), .B2(n_10_118), .ZN(n_10_122) + ); + XNOR2_X1_LVT i_10_154( + .A(op1[31]), .B(op2[31]), .ZN(n_10_123) + ); + XNOR2_X1_LVT i_10_155( + .A(n_10_122), .B(n_10_123), .ZN(n_63) + ); + INV_X1_LVT i_0_715( + .A(aluNegAr), .ZN(n_0_682) + ); + NOR2_X1_LVT i_0_612( + .A1(n_0_682), .A2(n_0_582), .ZN(n_0_580) + ); + AOI221_X1_LVT i_0_587( + .A(n_0_556), .B1(n_31), .B2(n_0_581), .C1(n_63), .C2(n_0_580), .ZN(n_0_555) + ); + NOR3_X1_LVT i_0_654( + .A1(aluOp[1]), .A2(aluBypass), .A3(n_0_683), .ZN(n_0_622) + ); + NAND2_X1_LVT i_0_653( + .A1(n_0_684), .A2(n_0_622), .ZN(n_0_621) + ); + INV_X1_LVT i_0_734( + .A(op2[0]), .ZN(n_0_701) + ); + INV_X1_LVT i_0_756( + .A(op2[3]), .ZN(n_0_723) + ); + NOR2_X1_LVT i_0_650( + .A1(op2[4]), .A2(n_0_723), .ZN(n_0_618) + ); + INV_X1_LVT i_0_649( + .A(n_0_618), .ZN(n_0_617) + ); + NOR2_X1_LVT i_0_648( + .A1(op2[4]), .A2(op2[3]), .ZN(n_0_616) + ); + INV_X1_LVT i_0_647( + .A(n_0_616), .ZN(n_0_615) + ); + INV_X1_LVT i_0_771( + .A(op2[4]), .ZN(n_0_738) + ); + INV_X1_LVT i_0_767( + .A(op1[15]), .ZN(n_0_734) + ); + INV_X1_LVT i_0_746( + .A(op1[7]), .ZN(n_0_713) + ); + AOI22_X1_LVT i_0_651( + .A1(n_0_734), .A2(n_0_723), .B1(op2[3]), .B2(n_0_713), .ZN(n_0_619) + ); + OAI222_X1_LVT i_0_646( + .A1(op1[23]), .A2(n_0_617), .B1(op1[31]), .B2(n_0_615), .C1(n_0_738), .C2(n_0_619), + .ZN(n_0_614) + ); + NOR2_X1_LVT i_0_645( + .A1(op2[2]), .A2(n_0_614), .ZN(n_0_613) + ); + NOR2_X1_LVT i_0_696( + .A1(op1[3]), .A2(n_0_723), .ZN(n_0_663) + ); + INV_X1_LVT i_0_739( + .A(op1[11]), .ZN(n_0_706) + ); + AOI21_X1_LVT i_0_644( + .A(n_0_663), .B1(n_0_723), .B2(n_0_706), .ZN(n_0_612) + ); + AOI22_X1_LVT i_0_643( + .A1(op2[4]), .A2(n_0_612), .B1(op1[27]), .B2(n_0_616), .ZN(n_0_611) + ); + INV_X1_LVT i_0_722( + .A(op1[19]), .ZN(n_0_689) + ); + OAI21_X1_LVT i_0_642( + .A(n_0_611), .B1(n_0_689), .B2(n_0_617), .ZN(n_0_610) + ); + AOI21_X1_LVT i_0_641( + .A(n_0_613), .B1(op2[2]), .B2(n_0_610), .ZN(n_0_609) + ); + INV_X1_LVT i_0_761( + .A(op2[1]), .ZN(n_0_728) + ); + OAI22_X1_LVT i_0_640( + .A1(op2[4]), .A2(op1[21]), .B1(n_0_738), .B2(op1[5]), .ZN(n_0_608) + ); + NAND2_X1_LVT i_0_639( + .A1(op2[3]), .A2(n_0_608), .ZN(n_0_607) + ); + INV_X1_LVT i_0_747( + .A(op1[13]), .ZN(n_0_714) + ); + NOR2_X1_LVT i_0_638( + .A1(n_0_738), .A2(op2[3]), .ZN(n_0_606) + ); + INV_X1_LVT i_0_743( + .A(op1[29]), .ZN(n_0_710) + ); + AOI221_X1_LVT i_0_636( + .A(op2[2]), .B1(n_0_714), .B2(n_0_606), .C1(n_0_710), .C2(n_0_616), .ZN(n_0_604) + ); + OAI22_X1_LVT i_0_635( + .A1(op2[4]), .A2(op1[17]), .B1(n_0_738), .B2(op1[1]), .ZN(n_0_603) + ); + INV_X1_LVT i_0_755( + .A(op1[9]), .ZN(n_0_722) + ); + INV_X1_LVT i_0_637( + .A(n_0_606), .ZN(n_0_605) + ); + INV_X1_LVT i_0_732( + .A(op1[25]), .ZN(n_0_699) + ); + OAI222_X1_LVT i_0_634( + .A1(n_0_723), .A2(n_0_603), .B1(n_0_722), .B2(n_0_605), .C1(n_0_699), .C2(n_0_615), + .ZN(n_0_602) + ); + AOI22_X1_LVT i_0_633( + .A1(n_0_607), .A2(n_0_604), .B1(op2[2]), .B2(n_0_602), .ZN(n_0_601) + ); + OAI221_X1_LVT i_0_616( + .A(n_0_701), .B1(op2[1]), .B2(n_0_609), .C1(n_0_728), .C2(n_0_601), .ZN(n_0_584) + ); + INV_X1_LVT i_0_729( + .A(op1[12]), .ZN(n_0_696) + ); + INV_X1_LVT i_0_731( + .A(op1[28]), .ZN(n_0_698) + ); + AOI22_X1_LVT i_0_622( + .A1(n_0_696), .A2(n_0_606), .B1(n_0_698), .B2(n_0_616), .ZN(n_0_590) + ); + INV_X1_LVT i_0_726( + .A(op2[2]), .ZN(n_0_693) + ); + NOR2_X1_LVT i_0_701( + .A1(n_0_738), .A2(op1[4]), .ZN(n_0_668) + ); + INV_X1_LVT i_0_760( + .A(op1[20]), .ZN(n_0_727) + ); + AOI21_X1_LVT i_0_623( + .A(n_0_668), .B1(n_0_738), .B2(n_0_727), .ZN(n_0_591) + ); + OAI211_X1_LVT i_0_621( + .A(n_0_590), .B(n_0_693), .C1(n_0_723), .C2(n_0_591), .ZN(n_0_589) + ); + OAI22_X1_LVT i_0_626( + .A1(op1[16]), .A2(op2[4]), .B1(n_0_738), .B2(op1[0]), .ZN(n_0_594) + ); + INV_X1_LVT i_0_769( + .A(op1[24]), .ZN(n_0_736) + ); + OAI22_X1_LVT i_0_625( + .A1(n_0_723), .A2(n_0_594), .B1(n_0_736), .B2(n_0_615), .ZN(n_0_593) + ); + AOI21_X1_LVT i_0_624( + .A(n_0_593), .B1(op1[8]), .B2(n_0_606), .ZN(n_0_592) + ); + OAI21_X1_LVT i_0_620( + .A(n_0_589), .B1(n_0_693), .B2(n_0_592), .ZN(n_0_588) + ); + INV_X1_LVT i_0_737( + .A(op1[6]), .ZN(n_0_704) + ); + INV_X1_LVT i_0_720( + .A(op1[22]), .ZN(n_0_687) + ); + OAI22_X1_LVT i_0_632( + .A1(n_0_738), .A2(n_0_704), .B1(op2[4]), .B2(n_0_687), .ZN(n_0_600) + ); + OAI221_X1_LVT i_0_631( + .A(n_0_693), .B1(n_0_723), .B2(n_0_600), .C1(op1[14]), .C2(n_0_605), .ZN(n_0_599) + ); + INV_X1_LVT i_0_750( + .A(op1[30]), .ZN(n_0_717) + ); + AOI21_X1_LVT i_0_630( + .A(n_0_599), .B1(n_0_717), .B2(n_0_616), .ZN(n_0_598) + ); + INV_X1_LVT i_0_738( + .A(op1[18]), .ZN(n_0_705) + ); + NOR2_X1_LVT i_0_628( + .A1(n_0_705), .A2(n_0_617), .ZN(n_0_596) + ); + INV_X1_LVT i_0_727( + .A(op1[2]), .ZN(n_0_694) + ); + INV_X1_LVT i_0_766( + .A(op1[10]), .ZN(n_0_733) + ); + OAI22_X1_LVT i_0_629( + .A1(n_0_723), .A2(n_0_694), .B1(n_0_733), .B2(op2[3]), .ZN(n_0_597) + ); + AOI221_X1_LVT i_0_627( + .A(n_0_596), .B1(op1[26]), .B2(n_0_616), .C1(op2[4]), .C2(n_0_597), .ZN(n_0_595) + ); + OAI21_X1_LVT i_0_619( + .A(n_0_728), .B1(n_0_693), .B2(n_0_595), .ZN(n_0_587) + ); + OAI22_X1_LVT i_0_618( + .A1(n_0_728), .A2(n_0_588), .B1(n_0_598), .B2(n_0_587), .ZN(n_0_586) + ); + INV_X1_LVT i_0_617( + .A(n_0_586), .ZN(n_0_585) + ); + OAI21_X1_LVT i_0_615( + .A(n_0_584), .B1(n_0_701), .B2(n_0_585), .ZN(n_0_583) + ); + NOR2_X1_LVT i_0_607( + .A1(op2[4]), .A2(op2[2]), .ZN(n_0_575) + ); + NAND2_X1_LVT i_0_606( + .A1(n_0_723), .A2(n_0_575), .ZN(n_0_574) + ); + INV_X1_LVT i_0_605( + .A(n_0_574), .ZN(n_0_573) + ); + NAND2_X1_LVT i_0_604( + .A1(n_0_728), .A2(n_0_573), .ZN(n_0_572) + ); + NAND2_X1_LVT i_0_611( + .A1(aluOp[2]), .A2(n_0_622), .ZN(n_0_579) + ); + INV_X1_LVT i_0_610( + .A(n_0_579), .ZN(n_0_578) + ); + NAND2_X1_LVT i_0_594( + .A1(n_0_701), .A2(n_0_578), .ZN(n_0_562) + ); + NOR3_X1_LVT i_0_592( + .A1(aluNegAr), .A2(n_0_572), .A3(n_0_562), .ZN(n_0_560) + ); + INV_X1_LVT i_0_600( + .A(n_0_569), .ZN(n_0_568) + ); + OAI21_X1_LVT i_0_595( + .A(n_0_568), .B1(aluOp[1]), .B2(n_0_570), .ZN(n_0_563) + ); + AOI211_X1_LVT i_0_591( + .A(aluBypass), .B(n_0_560), .C1(n_0_692), .C2(n_0_563), .ZN(n_0_559) + ); + OAI221_X1_LVT i_0_586( + .A(n_0_555), .B1(n_0_621), .B2(n_0_583), .C1(n_0_691), .C2(n_0_559), .ZN(result[31]) + ); + NAND2_X1_LVT i_10_150( + .A1(n_10_118), .A2(n_10_119), .ZN(n_10_120) + ); + XNOR2_X1_LVT i_10_151( + .A(n_10_116), .B(n_10_120), .ZN(n_62) + ); + AOI22_X1_LVT i_0_580( + .A1(n_62), .A2(n_0_580), .B1(n_30), .B2(n_0_581), .ZN(n_0_549) + ); + NAND2_X1_LVT i_0_576( + .A1(aluNegAr), .A2(n_0_578), .ZN(n_0_545) + ); + INV_X1_LVT i_0_603( + .A(n_0_572), .ZN(n_0_571) + ); + NOR3_X1_LVT i_0_574( + .A1(n_0_691), .A2(n_0_545), .A3(n_0_571), .ZN(n_0_543) + ); + AOI22_X1_LVT i_0_573( + .A1(n_0_717), .A2(n_0_565), .B1(op1[30]), .B2(n_0_566), .ZN(n_0_542) + ); + AOI21_X1_LVT i_0_572( + .A(n_0_543), .B1(op2[30]), .B2(n_0_542), .ZN(n_0_541) + ); + NAND2_X1_LVT i_0_579( + .A1(op2[0]), .A2(n_0_578), .ZN(n_0_548) + ); + NAND2_X1_LVT i_0_577( + .A1(op1[31]), .A2(n_0_571), .ZN(n_0_546) + ); + OAI211_X1_LVT i_0_571( + .A(n_0_549), .B(n_0_541), .C1(n_0_548), .C2(n_0_546), .ZN(n_0_540) + ); + OAI221_X1_LVT i_0_581( + .A(n_0_681), .B1(op2[30]), .B2(n_0_568), .C1(n_0_572), .C2(n_0_562), .ZN(n_0_550) + ); + AOI21_X1_LVT i_0_570( + .A(n_0_540), .B1(op1[30]), .B2(n_0_550), .ZN(n_0_539) + ); + INV_X1_LVT i_0_752( + .A(op1[23]), .ZN(n_0_719) + ); + OAI222_X1_LVT i_0_585( + .A1(n_0_713), .A2(n_0_605), .B1(n_0_719), .B2(n_0_615), .C1(n_0_734), .C2(n_0_617), + .ZN(n_0_554) + ); + AOI22_X1_LVT i_0_584( + .A1(op2[2]), .A2(n_0_554), .B1(n_0_693), .B2(n_0_610), .ZN(n_0_553) + ); + OAI22_X1_LVT i_0_583( + .A1(n_0_728), .A2(n_0_553), .B1(op2[1]), .B2(n_0_601), .ZN(n_0_552) + ); + AOI22_X1_LVT i_0_582( + .A1(n_0_701), .A2(n_0_585), .B1(op2[0]), .B2(n_0_552), .ZN(n_0_551) + ); + OAI21_X1_LVT i_0_569( + .A(n_0_539), .B1(n_0_621), .B2(n_0_551), .ZN(result[30]) + ); + INV_X1_LVT i_0_578( + .A(n_0_548), .ZN(n_0_547) + ); + NAND3_X1_LVT i_0_562( + .A1(op1[30]), .A2(n_0_571), .A3(n_0_547), .ZN(n_0_532) + ); + XNOR2_X1_LVT i_10_144( + .A(n_10_113), .B(n_10_114), .ZN(n_61) + ); + NAND2_X1_LVT i_0_558( + .A1(n_61), .A2(n_0_580), .ZN(n_0_528) + ); + OAI21_X1_LVT i_0_557( + .A(n_0_681), .B1(op2[29]), .B2(n_0_568), .ZN(n_0_527) + ); + NAND2_X1_LVT i_0_556( + .A1(op1[29]), .A2(n_0_566), .ZN(n_0_526) + ); + AOI22_X1_LVT i_0_555( + .A1(op1[29]), .A2(n_0_527), .B1(op2[29]), .B2(n_0_526), .ZN(n_0_525) + ); + AOI21_X1_LVT i_0_554( + .A(n_0_525), .B1(n_0_710), .B2(n_0_565), .ZN(n_0_524) + ); + AOI211_X1_LVT i_0_553( + .A(n_0_543), .B(n_0_524), .C1(n_29), .C2(n_0_581), .ZN(n_0_523) + ); + AND3_X1_LVT i_0_552( + .A1(n_0_532), .A2(n_0_528), .A3(n_0_523), .ZN(n_0_522) + ); + INV_X1_LVT i_0_652( + .A(n_0_621), .ZN(n_0_620) + ); + NAND2_X1_LVT i_0_565( + .A1(n_0_728), .A2(n_0_588), .ZN(n_0_535) + ); + AOI22_X1_LVT i_0_568( + .A1(n_0_723), .A2(n_0_600), .B1(op1[14]), .B2(n_0_618), .ZN(n_0_538) + ); + AOI22_X1_LVT i_0_567( + .A1(n_0_693), .A2(n_0_595), .B1(op2[2]), .B2(n_0_538), .ZN(n_0_537) + ); + INV_X1_LVT i_0_566( + .A(n_0_537), .ZN(n_0_536) + ); + OAI21_X1_LVT i_0_564( + .A(n_0_535), .B1(n_0_728), .B2(n_0_536), .ZN(n_0_534) + ); + OAI221_X1_LVT i_0_563( + .A(n_0_620), .B1(op2[0]), .B2(n_0_552), .C1(n_0_701), .C2(n_0_534), .ZN(n_0_533) + ); + NAND2_X1_LVT i_0_561( + .A1(op2[1]), .A2(n_0_573), .ZN(n_0_531) + ); + INV_X1_LVT i_0_560( + .A(n_0_531), .ZN(n_0_530) + ); + AOI22_X1_LVT i_0_559( + .A1(op1[31]), .A2(n_0_530), .B1(op1[29]), .B2(n_0_571), .ZN(n_0_529) + ); + OAI211_X1_LVT i_0_551( + .A(n_0_522), .B(n_0_533), .C1(n_0_562), .C2(n_0_529), .ZN(result[29]) + ); + INV_X1_LVT i_0_733( + .A(op2[28]), .ZN(n_0_700) + ); + AOI221_X1_LVT i_0_546( + .A(n_0_700), .B1(op1[28]), .B2(n_0_566), .C1(n_0_698), .C2(n_0_565), .ZN(n_0_517) + ); + OAI21_X1_LVT i_0_543( + .A(n_0_681), .B1(op2[28]), .B2(n_0_568), .ZN(n_0_514) + ); + AOI22_X1_LVT i_0_542( + .A1(n_28), .A2(n_0_581), .B1(op1[28]), .B2(n_0_514), .ZN(n_0_513) + ); + XNOR2_X1_LVT i_10_140( + .A(n_10_110), .B(n_10_111), .ZN(n_60) + ); + NAND2_X1_LVT i_0_544( + .A1(n_60), .A2(n_0_580), .ZN(n_0_515) + ); + NAND2_X1_LVT i_0_545( + .A1(op1[31]), .A2(n_0_574), .ZN(n_0_516) + ); + OAI211_X1_LVT i_0_541( + .A(n_0_513), .B(n_0_515), .C1(n_0_545), .C2(n_0_516), .ZN(n_0_512) + ); + AOI22_X1_LVT i_0_540( + .A1(op1[30]), .A2(n_0_530), .B1(op1[28]), .B2(n_0_571), .ZN(n_0_511) + ); + OAI22_X1_LVT i_0_539( + .A1(n_0_562), .A2(n_0_511), .B1(n_0_548), .B2(n_0_529), .ZN(n_0_510) + ); + NOR3_X1_LVT i_0_538( + .A1(n_0_517), .A2(n_0_512), .A3(n_0_510), .ZN(n_0_509) + ); + OAI22_X1_LVT i_0_550( + .A1(n_0_714), .A2(n_0_617), .B1(op2[3]), .B2(n_0_608), .ZN(n_0_521) + ); + OAI22_X1_LVT i_0_549( + .A1(op2[2]), .A2(n_0_602), .B1(n_0_693), .B2(n_0_521), .ZN(n_0_520) + ); + AOI22_X1_LVT i_0_548( + .A1(op2[1]), .A2(n_0_520), .B1(n_0_728), .B2(n_0_553), .ZN(n_0_519) + ); + OAI22_X1_LVT i_0_547( + .A1(op2[0]), .A2(n_0_534), .B1(n_0_701), .B2(n_0_519), .ZN(n_0_518) + ); + OAI21_X1_LVT i_0_537( + .A(n_0_509), .B1(n_0_621), .B2(n_0_518), .ZN(result[28]) + ); + XNOR2_X1_LVT i_10_136( + .A(n_10_107), .B(n_10_108), .ZN(n_59) + ); + AOI22_X1_LVT i_0_517( + .A1(n_27), .A2(n_0_581), .B1(n_59), .B2(n_0_580), .ZN(n_0_489) + ); + INV_X1_LVT i_0_721( + .A(op1[27]), .ZN(n_0_688) + ); + OAI21_X1_LVT i_0_516( + .A(n_0_681), .B1(op2[27]), .B2(n_0_568), .ZN(n_0_488) + ); + INV_X1_LVT i_0_515( + .A(n_0_488), .ZN(n_0_487) + ); + OAI221_X1_LVT i_0_514( + .A(n_0_489), .B1(n_0_545), .B2(n_0_516), .C1(n_0_688), .C2(n_0_487), .ZN(n_0_486) + ); + OAI21_X1_LVT i_0_530( + .A(op2[1]), .B1(n_0_710), .B2(n_0_574), .ZN(n_0_502) + ); + OAI21_X1_LVT i_0_529( + .A(n_0_728), .B1(n_0_688), .B2(n_0_574), .ZN(n_0_501) + ); + NAND2_X1_LVT i_0_528( + .A1(n_0_502), .A2(n_0_501), .ZN(n_0_500) + ); + AOI21_X1_LVT i_0_527( + .A(n_0_545), .B1(n_0_701), .B2(n_0_500), .ZN(n_0_499) + ); + NAND2_X1_LVT i_0_609( + .A1(n_0_682), .A2(n_0_578), .ZN(n_0_577) + ); + NOR2_X1_LVT i_0_526( + .A1(op2[4]), .A2(n_0_693), .ZN(n_0_498) + ); + NAND2_X1_LVT i_0_525( + .A1(n_0_723), .A2(n_0_498), .ZN(n_0_497) + ); + OAI22_X1_LVT i_0_523( + .A1(n_0_688), .A2(n_0_574), .B1(n_0_691), .B2(n_0_497), .ZN(n_0_495) + ); + OAI21_X1_LVT i_0_522( + .A(n_0_502), .B1(op2[1]), .B2(n_0_495), .ZN(n_0_494) + ); + AOI21_X1_LVT i_0_521( + .A(n_0_577), .B1(n_0_701), .B2(n_0_494), .ZN(n_0_493) + ); + NOR2_X1_LVT i_0_520( + .A1(n_0_499), .A2(n_0_493), .ZN(n_0_492) + ); + AOI21_X1_LVT i_0_519( + .A(n_0_492), .B1(op2[0]), .B2(n_0_511), .ZN(n_0_491) + ); + AOI22_X1_LVT i_0_518( + .A1(n_0_688), .A2(n_0_565), .B1(op1[27]), .B2(n_0_566), .ZN(n_0_490) + ); + AOI211_X1_LVT i_0_513( + .A(n_0_486), .B(n_0_491), .C1(op2[27]), .C2(n_0_490), .ZN(n_0_485) + ); + NOR3_X1_LVT i_0_536( + .A1(op2[4]), .A2(n_0_696), .A3(n_0_723), .ZN(n_0_508) + ); + AOI21_X1_LVT i_0_535( + .A(n_0_508), .B1(n_0_723), .B2(n_0_591), .ZN(n_0_507) + ); + OAI22_X1_LVT i_0_534( + .A1(op2[2]), .A2(n_0_592), .B1(n_0_693), .B2(n_0_507), .ZN(n_0_506) + ); + NOR2_X1_LVT i_0_533( + .A1(n_0_728), .A2(n_0_506), .ZN(n_0_505) + ); + AOI21_X1_LVT i_0_532( + .A(n_0_505), .B1(n_0_728), .B2(n_0_536), .ZN(n_0_504) + ); + OAI22_X1_LVT i_0_531( + .A1(n_0_701), .A2(n_0_504), .B1(op2[0]), .B2(n_0_519), .ZN(n_0_503) + ); + OAI21_X1_LVT i_0_512( + .A(n_0_485), .B1(n_0_621), .B2(n_0_503), .ZN(result[27]) + ); + OAI21_X1_LVT i_0_500( + .A(n_0_681), .B1(op2[26]), .B2(n_0_568), .ZN(n_0_473) + ); + NAND2_X1_LVT i_0_499( + .A1(op1[26]), .A2(n_0_473), .ZN(n_0_472) + ); + XNOR2_X1_LVT i_10_133( + .A(n_10_103), .B(n_10_106), .ZN(n_58) + ); + AOI22_X1_LVT i_0_498( + .A1(n_58), .A2(n_0_580), .B1(n_26), .B2(n_0_581), .ZN(n_0_471) + ); + INV_X1_LVT i_0_744( + .A(op1[26]), .ZN(n_0_711) + ); + OAI221_X1_LVT i_0_501( + .A(op2[26]), .B1(op1[26]), .B2(n_0_564), .C1(n_0_711), .C2(n_0_567), .ZN(n_0_474) + ); + NAND3_X1_LVT i_0_497( + .A1(n_0_472), .A2(n_0_471), .A3(n_0_474), .ZN(n_0_470) + ); + INV_X1_LVT i_0_524( + .A(n_0_497), .ZN(n_0_496) + ); + AOI22_X1_LVT i_0_505( + .A1(op1[30]), .A2(n_0_496), .B1(op1[26]), .B2(n_0_573), .ZN(n_0_478) + ); + NOR2_X1_LVT i_0_504( + .A1(op2[1]), .A2(n_0_478), .ZN(n_0_477) + ); + AOI21_X1_LVT i_0_503( + .A(n_0_477), .B1(op1[28]), .B2(n_0_530), .ZN(n_0_476) + ); + NAND2_X1_LVT i_0_502( + .A1(n_0_701), .A2(n_0_476), .ZN(n_0_475) + ); + AOI21_X1_LVT i_0_489( + .A(n_0_577), .B1(op2[0]), .B2(n_0_494), .ZN(n_0_462) + ); + AOI21_X1_LVT i_0_488( + .A(n_0_470), .B1(n_0_475), .B2(n_0_462), .ZN(n_0_461) + ); + AOI21_X1_LVT i_0_511( + .A(n_0_616), .B1(n_0_738), .B2(n_0_706), .ZN(n_0_484) + ); + AOI21_X1_LVT i_0_510( + .A(n_0_484), .B1(n_0_723), .B2(op1[19]), .ZN(n_0_483) + ); + INV_X1_LVT i_0_757( + .A(op1[3]), .ZN(n_0_724) + ); + NOR2_X1_LVT i_0_687( + .A1(n_0_724), .A2(op2[3]), .ZN(n_0_654) + ); + INV_X1_LVT i_0_686( + .A(n_0_654), .ZN(n_0_653) + ); + AOI21_X1_LVT i_0_509( + .A(n_0_483), .B1(op2[4]), .B2(n_0_653), .ZN(n_0_482) + ); + AOI22_X1_LVT i_0_508( + .A1(n_0_693), .A2(n_0_554), .B1(op2[2]), .B2(n_0_482), .ZN(n_0_481) + ); + OAI22_X1_LVT i_0_507( + .A1(n_0_728), .A2(n_0_481), .B1(op2[1]), .B2(n_0_520), .ZN(n_0_480) + ); + AOI22_X1_LVT i_0_506( + .A1(op2[0]), .A2(n_0_480), .B1(n_0_701), .B2(n_0_504), .ZN(n_0_479) + ); + NAND3_X1_LVT i_0_491( + .A1(op2[0]), .A2(n_0_516), .A3(n_0_500), .ZN(n_0_464) + ); + NAND2_X1_LVT i_0_494( + .A1(op1[31]), .A2(n_0_615), .ZN(n_0_467) + ); + OAI21_X1_LVT i_0_492( + .A(n_0_467), .B1(n_0_728), .B2(n_0_516), .ZN(n_0_465) + ); + OAI21_X1_LVT i_0_490( + .A(n_0_464), .B1(n_0_475), .B2(n_0_465), .ZN(n_0_463) + ); + OAI221_X1_LVT i_0_487( + .A(n_0_461), .B1(n_0_621), .B2(n_0_479), .C1(n_0_545), .C2(n_0_463), .ZN(result[26]) + ); + INV_X1_LVT i_10_126( + .A(n_10_100), .ZN(n_10_101) + ); + NOR2_X1_LVT i_10_127( + .A1(n_10_99), .A2(n_10_101), .ZN(n_10_102) + ); + XNOR2_X1_LVT i_10_128( + .A(n_10_97), .B(n_10_102), .ZN(n_57) + ); + AOI22_X1_LVT i_0_479( + .A1(n_57), .A2(n_0_580), .B1(n_25), .B2(n_0_581), .ZN(n_0_453) + ); + INV_X1_LVT i_0_730( + .A(op2[25]), .ZN(n_0_697) + ); + AOI21_X1_LVT i_0_478( + .A(aluBypass), .B1(n_0_697), .B2(n_0_569), .ZN(n_0_452) + ); + AOI22_X1_LVT i_0_480( + .A1(op1[25]), .A2(n_0_567), .B1(n_0_699), .B2(n_0_564), .ZN(n_0_454) + ); + OAI221_X1_LVT i_0_477( + .A(n_0_453), .B1(n_0_699), .B2(n_0_452), .C1(n_0_697), .C2(n_0_454), .ZN(n_0_451) + ); + INV_X1_LVT i_0_575( + .A(n_0_545), .ZN(n_0_544) + ); + AOI21_X1_LVT i_0_476( + .A(n_0_451), .B1(n_0_544), .B2(n_0_465), .ZN(n_0_450) + ); + AOI22_X1_LVT i_0_475( + .A1(op1[29]), .A2(n_0_496), .B1(op1[25]), .B2(n_0_573), .ZN(n_0_449) + ); + NAND2_X1_LVT i_0_474( + .A1(n_0_728), .A2(n_0_449), .ZN(n_0_448) + ); + OAI21_X1_LVT i_0_473( + .A(n_0_448), .B1(n_0_728), .B2(n_0_495), .ZN(n_0_447) + ); + OAI22_X1_LVT i_0_472( + .A1(n_0_548), .A2(n_0_476), .B1(n_0_562), .B2(n_0_447), .ZN(n_0_446) + ); + INV_X1_LVT i_0_471( + .A(n_0_446), .ZN(n_0_445) + ); + OAI222_X1_LVT i_0_486( + .A1(n_0_733), .A2(n_0_617), .B1(n_0_694), .B2(n_0_605), .C1(n_0_705), .C2(n_0_615), + .ZN(n_0_460) + ); + NOR2_X1_LVT i_0_485( + .A1(n_0_693), .A2(n_0_460), .ZN(n_0_459) + ); + AOI21_X1_LVT i_0_484( + .A(n_0_459), .B1(n_0_693), .B2(n_0_538), .ZN(n_0_458) + ); + OAI22_X1_LVT i_0_483( + .A1(n_0_728), .A2(n_0_458), .B1(op2[1]), .B2(n_0_506), .ZN(n_0_457) + ); + INV_X1_LVT i_0_482( + .A(n_0_457), .ZN(n_0_456) + ); + OAI221_X1_LVT i_0_481( + .A(n_0_620), .B1(n_0_701), .B2(n_0_456), .C1(op2[0]), .C2(n_0_480), .ZN(n_0_455) + ); + NAND3_X1_LVT i_0_470( + .A1(n_0_450), .A2(n_0_445), .A3(n_0_455), .ZN(result[25]) + ); + INV_X1_LVT i_0_493( + .A(n_0_467), .ZN(n_0_466) + ); + OAI211_X1_LVT i_0_455( + .A(n_0_544), .B(n_0_465), .C1(op2[0]), .C2(n_0_466), .ZN(n_0_430) + ); + OAI21_X1_LVT i_0_462( + .A(n_0_681), .B1(op2[24]), .B2(n_0_568), .ZN(n_0_437) + ); + XNOR2_X1_LVT i_10_120( + .A(n_10_94), .B(n_10_95), .ZN(n_56) + ); + AOI222_X1_LVT i_0_461( + .A1(op1[24]), .A2(n_0_437), .B1(n_56), .B2(n_0_580), .C1(n_24), .C2(n_0_581), + .ZN(n_0_436) + ); + INV_X1_LVT i_0_460( + .A(n_0_436), .ZN(n_0_435) + ); + AOI22_X1_LVT i_0_458( + .A1(op1[24]), .A2(n_0_573), .B1(op1[28]), .B2(n_0_496), .ZN(n_0_433) + ); + OAI22_X1_LVT i_0_457( + .A1(op2[1]), .A2(n_0_433), .B1(n_0_728), .B2(n_0_478), .ZN(n_0_432) + ); + INV_X1_LVT i_0_456( + .A(n_0_432), .ZN(n_0_431) + ); + OAI22_X1_LVT i_0_454( + .A1(n_0_562), .A2(n_0_431), .B1(n_0_548), .B2(n_0_447), .ZN(n_0_429) + ); + AOI22_X1_LVT i_0_459( + .A1(n_0_736), .A2(n_0_565), .B1(op1[24]), .B2(n_0_566), .ZN(n_0_434) + ); + AOI211_X1_LVT i_0_453( + .A(n_0_435), .B(n_0_429), .C1(op2[24]), .C2(n_0_434), .ZN(n_0_428) + ); + NAND2_X1_LVT i_0_467( + .A1(n_0_693), .A2(n_0_521), .ZN(n_0_442) + ); + NOR2_X1_LVT i_0_469( + .A1(op2[3]), .A2(n_0_603), .ZN(n_0_444) + ); + AOI21_X1_LVT i_0_468( + .A(n_0_444), .B1(op1[9]), .B2(n_0_618), .ZN(n_0_443) + ); + OAI21_X1_LVT i_0_466( + .A(n_0_442), .B1(n_0_693), .B2(n_0_443), .ZN(n_0_441) + ); + NAND2_X1_LVT i_0_465( + .A1(op2[1]), .A2(n_0_441), .ZN(n_0_440) + ); + OAI21_X1_LVT i_0_464( + .A(n_0_440), .B1(op2[1]), .B2(n_0_481), .ZN(n_0_439) + ); + OAI221_X1_LVT i_0_463( + .A(n_0_620), .B1(op2[0]), .B2(n_0_456), .C1(n_0_701), .C2(n_0_439), .ZN(n_0_438) + ); + NAND3_X1_LVT i_0_452( + .A1(n_0_430), .A2(n_0_428), .A3(n_0_438), .ZN(result[24]) + ); + INV_X1_LVT i_0_751( + .A(op2[23]), .ZN(n_0_718) + ); + AOI221_X1_LVT i_0_440( + .A(n_0_718), .B1(op1[23]), .B2(n_0_566), .C1(n_0_719), .C2(n_0_565), .ZN(n_0_416) + ); + INV_X1_LVT i_10_115( + .A(n_10_91), .ZN(n_10_92) + ); + NOR2_X1_LVT i_10_116( + .A1(n_10_90), .A2(n_10_92), .ZN(n_10_93) + ); + XNOR2_X1_LVT i_10_117( + .A(n_10_88), .B(n_10_93), .ZN(n_55) + ); + AOI222_X1_LVT i_0_438( + .A1(n_23), .A2(n_0_581), .B1(n_0_544), .B2(n_0_466), .C1(n_55), .C2(n_0_580), + .ZN(n_0_414) + ); + OAI21_X1_LVT i_0_437( + .A(n_0_414), .B1(n_0_548), .B2(n_0_431), .ZN(n_0_413) + ); + OAI21_X1_LVT i_0_439( + .A(n_0_681), .B1(op2[23]), .B2(n_0_568), .ZN(n_0_415) + ); + AOI211_X1_LVT i_0_436( + .A(n_0_416), .B(n_0_413), .C1(op1[23]), .C2(n_0_415), .ZN(n_0_412) + ); + AOI22_X1_LVT i_0_444( + .A1(n_0_723), .A2(n_0_719), .B1(op2[3]), .B2(n_0_691), .ZN(n_0_420) + ); + AOI22_X1_LVT i_0_443( + .A1(n_0_575), .A2(n_0_420), .B1(op1[27]), .B2(n_0_496), .ZN(n_0_419) + ); + AOI22_X1_LVT i_0_442( + .A1(op2[1]), .A2(n_0_449), .B1(n_0_728), .B2(n_0_419), .ZN(n_0_418) + ); + INV_X1_LVT i_0_441( + .A(n_0_418), .ZN(n_0_417) + ); + NAND2_X1_LVT i_0_447( + .A1(n_0_728), .A2(n_0_458), .ZN(n_0_423) + ); + NOR2_X1_LVT i_0_451( + .A1(op2[3]), .A2(n_0_594), .ZN(n_0_427) + ); + AOI21_X1_LVT i_0_450( + .A(n_0_427), .B1(op1[8]), .B2(n_0_618), .ZN(n_0_426) + ); + OAI22_X1_LVT i_0_449( + .A1(n_0_693), .A2(n_0_426), .B1(op2[2]), .B2(n_0_507), .ZN(n_0_425) + ); + INV_X1_LVT i_0_448( + .A(n_0_425), .ZN(n_0_424) + ); + OAI21_X1_LVT i_0_446( + .A(n_0_423), .B1(n_0_728), .B2(n_0_424), .ZN(n_0_422) + ); + AOI22_X1_LVT i_0_445( + .A1(op2[0]), .A2(n_0_422), .B1(n_0_701), .B2(n_0_439), .ZN(n_0_421) + ); + OAI221_X1_LVT i_0_435( + .A(n_0_412), .B1(n_0_562), .B2(n_0_417), .C1(n_0_621), .C2(n_0_421), .ZN(result[23]) + ); + XNOR2_X1_LVT i_10_109( + .A(n_10_85), .B(n_10_86), .ZN(n_54) + ); + AOI22_X1_LVT i_0_419( + .A1(n_54), .A2(n_0_580), .B1(n_22), .B2(n_0_581), .ZN(n_0_396) + ); + INV_X1_LVT i_0_719( + .A(op2[22]), .ZN(n_0_686) + ); + AOI21_X1_LVT i_0_420( + .A(aluBypass), .B1(n_0_686), .B2(n_0_569), .ZN(n_0_397) + ); + OAI21_X1_LVT i_0_418( + .A(n_0_396), .B1(n_0_687), .B2(n_0_397), .ZN(n_0_395) + ); + AOI22_X1_LVT i_0_421( + .A1(op1[22]), .A2(n_0_566), .B1(n_0_687), .B2(n_0_565), .ZN(n_0_398) + ); + AOI21_X1_LVT i_0_417( + .A(n_0_395), .B1(op2[22]), .B2(n_0_398), .ZN(n_0_394) + ); + NAND2_X1_LVT i_0_432( + .A1(n_0_728), .A2(n_0_441), .ZN(n_0_409) + ); + AND2_X1_LVT i_0_434( + .A1(n_0_738), .A2(n_0_619), .ZN(n_0_411) + ); + AOI22_X1_LVT i_0_433( + .A1(n_0_693), .A2(n_0_482), .B1(op2[2]), .B2(n_0_411), .ZN(n_0_410) + ); + OAI21_X1_LVT i_0_431( + .A(n_0_409), .B1(n_0_728), .B2(n_0_410), .ZN(n_0_408) + ); + OAI22_X1_LVT i_0_430( + .A1(n_0_701), .A2(n_0_408), .B1(op2[0]), .B2(n_0_422), .ZN(n_0_407) + ); + AOI22_X1_LVT i_0_429( + .A1(n_0_723), .A2(n_0_687), .B1(op2[3]), .B2(n_0_717), .ZN(n_0_406) + ); + AOI22_X1_LVT i_0_428( + .A1(n_0_575), .A2(n_0_406), .B1(op1[26]), .B2(n_0_496), .ZN(n_0_405) + ); + AND2_X1_LVT i_0_427( + .A1(n_0_728), .A2(n_0_405), .ZN(n_0_404) + ); + AOI21_X1_LVT i_0_426( + .A(n_0_404), .B1(op2[1]), .B2(n_0_433), .ZN(n_0_403) + ); + INV_X1_LVT i_0_425( + .A(n_0_403), .ZN(n_0_402) + ); + OAI222_X1_LVT i_0_424( + .A1(n_0_545), .A2(n_0_467), .B1(n_0_701), .B2(n_0_417), .C1(op2[0]), .C2(n_0_402), + .ZN(n_0_401) + ); + NOR2_X1_LVT i_0_496( + .A1(n_0_738), .A2(n_0_691), .ZN(n_0_469) + ); + INV_X1_LVT i_0_495( + .A(n_0_469), .ZN(n_0_468) + ); + NAND3_X1_LVT i_0_423( + .A1(n_0_693), .A2(n_0_468), .A3(n_0_404), .ZN(n_0_400) + ); + OAI21_X1_LVT i_0_422( + .A(n_0_401), .B1(op2[0]), .B2(n_0_400), .ZN(n_0_399) + ); + OAI221_X1_LVT i_0_416( + .A(n_0_394), .B1(n_0_621), .B2(n_0_407), .C1(n_0_579), .C2(n_0_399), .ZN(result[22]) + ); + INV_X1_LVT i_0_759( + .A(op1[21]), .ZN(n_0_726) + ); + AOI22_X1_LVT i_0_399( + .A1(op1[21]), .A2(n_0_566), .B1(n_0_726), .B2(n_0_565), .ZN(n_0_377) + ); + NOR2_X1_LVT i_0_692( + .A1(n_0_726), .A2(op2[21]), .ZN(n_0_659) + ); + AOI222_X1_LVT i_0_398( + .A1(op2[21]), .A2(n_0_377), .B1(n_21), .B2(n_0_581), .C1(n_0_659), .C2(n_0_569), + .ZN(n_0_376) + ); + INV_X1_LVT i_0_397( + .A(n_0_376), .ZN(n_0_375) + ); + INV_X1_LVT i_10_104( + .A(n_10_82), .ZN(n_10_83) + ); + NOR2_X1_LVT i_10_105( + .A1(n_10_81), .A2(n_10_83), .ZN(n_10_84) + ); + XNOR2_X1_LVT i_10_106( + .A(n_10_79), .B(n_10_84), .ZN(n_53) + ); + AOI221_X1_LVT i_0_396( + .A(n_0_375), .B1(n_53), .B2(n_0_580), .C1(op1[21]), .C2(aluBypass), .ZN(n_0_374) + ); + INV_X1_LVT i_0_608( + .A(n_0_577), .ZN(n_0_576) + ); + NAND2_X1_LVT i_0_403( + .A1(op2[0]), .A2(n_0_402), .ZN(n_0_381) + ); + AND2_X1_LVT i_0_410( + .A1(op2[1]), .A2(n_0_419), .ZN(n_0_388) + ); + OAI22_X1_LVT i_0_408( + .A1(n_0_723), .A2(n_0_710), .B1(n_0_726), .B2(op2[3]), .ZN(n_0_386) + ); + AOI22_X1_LVT i_0_407( + .A1(n_0_575), .A2(n_0_386), .B1(op1[25]), .B2(n_0_496), .ZN(n_0_385) + ); + AOI21_X1_LVT i_0_395( + .A(n_0_388), .B1(n_0_728), .B2(n_0_385), .ZN(n_0_373) + ); + OAI211_X1_LVT i_0_394( + .A(n_0_576), .B(n_0_381), .C1(op2[0]), .C2(n_0_373), .ZN(n_0_372) + ); + AOI21_X1_LVT i_0_402( + .A(n_0_381), .B1(n_0_466), .B2(n_0_400), .ZN(n_0_380) + ); + INV_X1_LVT i_0_401( + .A(n_0_380), .ZN(n_0_379) + ); + NOR2_X1_LVT i_0_409( + .A1(n_0_575), .A2(n_0_467), .ZN(n_0_387) + ); + INV_X1_LVT i_0_406( + .A(n_0_385), .ZN(n_0_384) + ); + NOR2_X1_LVT i_0_405( + .A1(n_0_387), .A2(n_0_384), .ZN(n_0_383) + ); + AOI22_X1_LVT i_0_404( + .A1(n_0_467), .A2(n_0_388), .B1(n_0_728), .B2(n_0_383), .ZN(n_0_382) + ); + OAI211_X1_LVT i_0_400( + .A(n_0_544), .B(n_0_379), .C1(op2[0]), .C2(n_0_382), .ZN(n_0_378) + ); + AOI22_X1_LVT i_0_415( + .A1(op1[14]), .A2(n_0_616), .B1(op1[6]), .B2(n_0_618), .ZN(n_0_393) + ); + NOR2_X1_LVT i_0_414( + .A1(n_0_693), .A2(n_0_393), .ZN(n_0_392) + ); + AOI21_X1_LVT i_0_413( + .A(n_0_392), .B1(n_0_693), .B2(n_0_460), .ZN(n_0_391) + ); + OAI22_X1_LVT i_0_412( + .A1(n_0_728), .A2(n_0_391), .B1(op2[1]), .B2(n_0_424), .ZN(n_0_390) + ); + OAI221_X1_LVT i_0_411( + .A(n_0_620), .B1(op2[0]), .B2(n_0_408), .C1(n_0_701), .C2(n_0_390), .ZN(n_0_389) + ); + NAND4_X1_LVT i_0_393( + .A1(n_0_374), .A2(n_0_372), .A3(n_0_378), .A4(n_0_389), .ZN(result[21]) + ); + OAI221_X1_LVT i_0_388( + .A(op2[20]), .B1(n_0_727), .B2(n_0_567), .C1(op1[20]), .C2(n_0_564), .ZN(n_0_367) + ); + NOR2_X1_LVT i_0_691( + .A1(n_0_727), .A2(op2[20]), .ZN(n_0_658) + ); + AOI22_X1_LVT i_0_387( + .A1(op1[20]), .A2(aluBypass), .B1(n_0_658), .B2(n_0_569), .ZN(n_0_366) + ); + XNOR2_X1_LVT i_10_98( + .A(n_10_76), .B(n_10_77), .ZN(n_52) + ); + AOI22_X1_LVT i_0_386( + .A1(n_52), .A2(n_0_580), .B1(n_20), .B2(n_0_581), .ZN(n_0_365) + ); + AOI221_X1_LVT i_0_392( + .A(op2[4]), .B1(n_0_727), .B2(n_0_723), .C1(op2[3]), .C2(n_0_698), .ZN(n_0_371) + ); + AOI22_X1_LVT i_0_391( + .A1(op1[24]), .A2(n_0_496), .B1(n_0_693), .B2(n_0_371), .ZN(n_0_370) + ); + OAI22_X1_LVT i_0_390( + .A1(op2[1]), .A2(n_0_370), .B1(n_0_728), .B2(n_0_405), .ZN(n_0_369) + ); + OAI221_X1_LVT i_0_385( + .A(n_0_576), .B1(n_0_701), .B2(n_0_373), .C1(op2[0]), .C2(n_0_369), .ZN(n_0_364) + ); + AND4_X1_LVT i_0_384( + .A1(n_0_367), .A2(n_0_366), .A3(n_0_365), .A4(n_0_364), .ZN(n_0_363) + ); + AOI22_X1_LVT i_0_383( + .A1(op1[13]), .A2(n_0_616), .B1(op1[5]), .B2(n_0_618), .ZN(n_0_362) + ); + AOI22_X1_LVT i_0_382( + .A1(op2[2]), .A2(n_0_362), .B1(n_0_693), .B2(n_0_443), .ZN(n_0_361) + ); + NAND2_X1_LVT i_0_381( + .A1(op2[1]), .A2(n_0_361), .ZN(n_0_360) + ); + OAI21_X1_LVT i_0_380( + .A(n_0_360), .B1(op2[1]), .B2(n_0_410), .ZN(n_0_359) + ); + OAI221_X1_LVT i_0_379( + .A(n_0_620), .B1(n_0_701), .B2(n_0_359), .C1(op2[0]), .C2(n_0_390), .ZN(n_0_358) + ); + OR2_X1_LVT i_0_389( + .A1(n_0_387), .A2(n_0_369), .ZN(n_0_368) + ); + AOI22_X1_LVT i_0_378( + .A1(op2[0]), .A2(n_0_382), .B1(n_0_701), .B2(n_0_368), .ZN(n_0_357) + ); + OAI211_X1_LVT i_0_377( + .A(n_0_363), .B(n_0_358), .C1(n_0_545), .C2(n_0_357), .ZN(result[20]) + ); + OAI22_X1_LVT i_0_370( + .A1(op2[3]), .A2(n_0_689), .B1(n_0_723), .B2(n_0_688), .ZN(n_0_350) + ); + AND2_X1_LVT i_0_369( + .A1(n_0_738), .A2(n_0_350), .ZN(n_0_349) + ); + AOI22_X1_LVT i_0_368( + .A1(n_0_498), .A2(n_0_420), .B1(n_0_693), .B2(n_0_349), .ZN(n_0_348) + ); + AND2_X1_LVT i_0_367( + .A1(n_0_728), .A2(n_0_348), .ZN(n_0_347) + ); + AOI21_X1_LVT i_0_359( + .A(n_0_347), .B1(op2[1]), .B2(n_0_385), .ZN(n_0_339) + ); + OAI221_X1_LVT i_0_357( + .A(n_0_576), .B1(n_0_701), .B2(n_0_369), .C1(op2[0]), .C2(n_0_339), .ZN(n_0_337) + ); + NAND2_X1_LVT i_0_363( + .A1(n_19), .A2(n_0_581), .ZN(n_0_343) + ); + INV_X1_LVT i_0_723( + .A(op2[19]), .ZN(n_0_690) + ); + AOI221_X1_LVT i_0_364( + .A(n_0_690), .B1(n_0_689), .B2(n_0_565), .C1(op1[19]), .C2(n_0_566), .ZN(n_0_344) + ); + XNOR2_X1_LVT i_10_94( + .A(n_10_73), .B(n_10_74), .ZN(n_51) + ); + AOI221_X1_LVT i_0_361( + .A(n_0_344), .B1(op1[19]), .B2(aluBypass), .C1(n_51), .C2(n_0_580), .ZN(n_0_341) + ); + NAND3_X1_LVT i_0_362( + .A1(n_0_690), .A2(op1[19]), .A3(n_0_569), .ZN(n_0_342) + ); + NAND3_X1_LVT i_0_360( + .A1(n_0_343), .A2(n_0_341), .A3(n_0_342), .ZN(n_0_340) + ); + AOI22_X1_LVT i_0_376( + .A1(op1[12]), .A2(n_0_616), .B1(op1[4]), .B2(n_0_618), .ZN(n_0_356) + ); + OAI22_X1_LVT i_0_375( + .A1(n_0_693), .A2(n_0_356), .B1(op2[2]), .B2(n_0_426), .ZN(n_0_355) + ); + INV_X1_LVT i_0_374( + .A(n_0_355), .ZN(n_0_354) + ); + OAI22_X1_LVT i_0_373( + .A1(op2[1]), .A2(n_0_391), .B1(n_0_728), .B2(n_0_354), .ZN(n_0_353) + ); + AOI22_X1_LVT i_0_372( + .A1(n_0_701), .A2(n_0_359), .B1(op2[0]), .B2(n_0_353), .ZN(n_0_352) + ); + INV_X1_LVT i_0_371( + .A(n_0_352), .ZN(n_0_351) + ); + AOI21_X1_LVT i_0_358( + .A(n_0_340), .B1(n_0_620), .B2(n_0_351), .ZN(n_0_338) + ); + AOI22_X1_LVT i_0_366( + .A1(n_0_468), .A2(n_0_347), .B1(op2[1]), .B2(n_0_383), .ZN(n_0_346) + ); + AOI22_X1_LVT i_0_365( + .A1(n_0_701), .A2(n_0_346), .B1(op2[0]), .B2(n_0_368), .ZN(n_0_345) + ); + OAI211_X1_LVT i_0_356( + .A(n_0_337), .B(n_0_338), .C1(n_0_545), .C2(n_0_345), .ZN(result[19]) + ); + XNOR2_X1_LVT i_10_90( + .A(n_10_70), .B(n_10_71), .ZN(n_50) + ); + NAND2_X1_LVT i_0_342( + .A1(n_50), .A2(n_0_580), .ZN(n_0_323) + ); + OAI21_X1_LVT i_0_343( + .A(n_0_681), .B1(op2[18]), .B2(n_0_568), .ZN(n_0_324) + ); + AOI22_X1_LVT i_0_341( + .A1(op1[18]), .A2(n_0_324), .B1(n_18), .B2(n_0_581), .ZN(n_0_322) + ); + OAI221_X1_LVT i_0_340( + .A(op2[18]), .B1(n_0_705), .B2(n_0_567), .C1(op1[18]), .C2(n_0_564), .ZN(n_0_321) + ); + NAND3_X1_LVT i_0_339( + .A1(n_0_323), .A2(n_0_322), .A3(n_0_321), .ZN(n_0_320) + ); + OAI22_X1_LVT i_0_351( + .A1(op2[3]), .A2(n_0_705), .B1(n_0_723), .B2(n_0_711), .ZN(n_0_332) + ); + AND2_X1_LVT i_0_350( + .A1(n_0_738), .A2(n_0_332), .ZN(n_0_331) + ); + AOI22_X1_LVT i_0_349( + .A1(n_0_498), .A2(n_0_406), .B1(n_0_693), .B2(n_0_331), .ZN(n_0_330) + ); + NAND2_X1_LVT i_0_348( + .A1(n_0_728), .A2(n_0_330), .ZN(n_0_329) + ); + NAND2_X1_LVT i_0_347( + .A1(op2[1]), .A2(n_0_370), .ZN(n_0_328) + ); + AND2_X1_LVT i_0_338( + .A1(n_0_329), .A2(n_0_328), .ZN(n_0_319) + ); + OAI22_X1_LVT i_0_337( + .A1(op2[0]), .A2(n_0_319), .B1(n_0_701), .B2(n_0_339), .ZN(n_0_318) + ); + INV_X1_LVT i_0_336( + .A(n_0_318), .ZN(n_0_317) + ); + AOI21_X1_LVT i_0_335( + .A(n_0_320), .B1(n_0_578), .B2(n_0_317), .ZN(n_0_316) + ); + OAI22_X1_LVT i_0_346( + .A1(n_0_469), .A2(n_0_329), .B1(n_0_387), .B2(n_0_328), .ZN(n_0_327) + ); + NAND2_X1_LVT i_0_344( + .A1(n_0_544), .A2(n_0_346), .ZN(n_0_325) + ); + NAND2_X1_LVT i_0_354( + .A1(n_0_728), .A2(n_0_361), .ZN(n_0_335) + ); + AOI22_X1_LVT i_0_355( + .A1(n_0_612), .A2(n_0_498), .B1(n_0_693), .B2(n_0_411), .ZN(n_0_336) + ); + OAI21_X1_LVT i_0_353( + .A(n_0_335), .B1(n_0_728), .B2(n_0_336), .ZN(n_0_334) + ); + AOI22_X1_LVT i_0_352( + .A1(n_0_701), .A2(n_0_353), .B1(op2[0]), .B2(n_0_334), .ZN(n_0_333) + ); + OAI221_X1_LVT i_0_334( + .A(n_0_316), .B1(n_0_327), .B2(n_0_325), .C1(n_0_621), .C2(n_0_333), .ZN(result[18]) + ); + NAND2_X1_LVT i_0_325( + .A1(n_17), .A2(n_0_581), .ZN(n_0_307) + ); + INV_X1_LVT i_0_765( + .A(op1[17]), .ZN(n_0_732) + ); + AOI22_X1_LVT i_0_324( + .A1(n_0_732), .A2(n_0_565), .B1(op1[17]), .B2(n_0_566), .ZN(n_0_306) + ); + NOR2_X1_LVT i_0_693( + .A1(n_0_732), .A2(op2[17]), .ZN(n_0_660) + ); + XNOR2_X1_LVT i_10_86( + .A(n_10_67), .B(n_10_68), .ZN(n_49) + ); + AOI222_X1_LVT i_0_323( + .A1(op2[17]), .A2(n_0_306), .B1(n_0_660), .B2(n_0_569), .C1(n_49), .C2(n_0_580), + .ZN(n_0_305) + ); + OAI211_X1_LVT i_0_322( + .A(n_0_307), .B(n_0_305), .C1(n_0_732), .C2(n_0_681), .ZN(n_0_304) + ); + AOI22_X1_LVT i_0_331( + .A1(op2[3]), .A2(op1[25]), .B1(op1[17]), .B2(n_0_723), .ZN(n_0_313) + ); + NOR2_X1_LVT i_0_330( + .A1(op2[4]), .A2(n_0_313), .ZN(n_0_312) + ); + AOI22_X1_LVT i_0_329( + .A1(n_0_498), .A2(n_0_386), .B1(n_0_693), .B2(n_0_312), .ZN(n_0_311) + ); + OAI22_X1_LVT i_0_328( + .A1(op2[1]), .A2(n_0_311), .B1(n_0_728), .B2(n_0_348), .ZN(n_0_310) + ); + OR2_X1_LVT i_0_327( + .A1(op2[0]), .A2(n_0_310), .ZN(n_0_309) + ); + OAI21_X1_LVT i_0_321( + .A(n_0_576), .B1(n_0_701), .B2(n_0_319), .ZN(n_0_303) + ); + INV_X1_LVT i_0_320( + .A(n_0_303), .ZN(n_0_302) + ); + AOI21_X1_LVT i_0_319( + .A(n_0_304), .B1(n_0_309), .B2(n_0_302), .ZN(n_0_301) + ); + INV_X1_LVT i_0_345( + .A(n_0_327), .ZN(n_0_326) + ); + OAI22_X1_LVT i_0_326( + .A1(n_0_701), .A2(n_0_326), .B1(n_0_469), .B2(n_0_309), .ZN(n_0_308) + ); + NOR2_X1_LVT i_0_318( + .A1(op2[2]), .A2(n_0_393), .ZN(n_0_300) + ); + AOI21_X1_LVT i_0_317( + .A(n_0_300), .B1(n_0_597), .B2(n_0_498), .ZN(n_0_299) + ); + OAI22_X1_LVT i_0_316( + .A1(n_0_728), .A2(n_0_299), .B1(op2[1]), .B2(n_0_354), .ZN(n_0_298) + ); + OAI22_X1_LVT i_0_315( + .A1(op2[0]), .A2(n_0_334), .B1(n_0_701), .B2(n_0_298), .ZN(n_0_297) + ); + OAI221_X1_LVT i_0_314( + .A(n_0_301), .B1(n_0_545), .B2(n_0_308), .C1(n_0_621), .C2(n_0_297), .ZN(result[17]) + ); + XNOR2_X1_LVT i_10_82( + .A(n_10_64), .B(n_10_65), .ZN(n_48) + ); + AOI22_X1_LVT i_0_301( + .A1(n_48), .A2(n_0_580), .B1(n_16), .B2(n_0_581), .ZN(n_0_284) + ); + NAND2_X1_LVT i_0_333( + .A1(n_0_544), .A2(n_0_469), .ZN(n_0_315) + ); + INV_X1_LVT i_0_332( + .A(n_0_315), .ZN(n_0_314) + ); + OAI21_X1_LVT i_0_302( + .A(n_0_681), .B1(op2[16]), .B2(n_0_568), .ZN(n_0_285) + ); + AOI21_X1_LVT i_0_300( + .A(n_0_314), .B1(op1[16]), .B2(n_0_285), .ZN(n_0_283) + ); + INV_X1_LVT i_0_772( + .A(op1[16]), .ZN(n_0_739) + ); + OAI221_X1_LVT i_0_303( + .A(op2[16]), .B1(op1[16]), .B2(n_0_564), .C1(n_0_739), .C2(n_0_567), .ZN(n_0_286) + ); + NAND3_X1_LVT i_0_299( + .A1(n_0_284), .A2(n_0_283), .A3(n_0_286), .ZN(n_0_282) + ); + INV_X1_LVT i_0_593( + .A(n_0_562), .ZN(n_0_561) + ); + OAI22_X1_LVT i_0_307( + .A1(op1[16]), .A2(op2[3]), .B1(op1[24]), .B2(n_0_723), .ZN(n_0_290) + ); + NOR2_X1_LVT i_0_306( + .A1(op2[4]), .A2(n_0_290), .ZN(n_0_289) + ); + AOI22_X1_LVT i_0_305( + .A1(n_0_693), .A2(n_0_289), .B1(op2[2]), .B2(n_0_371), .ZN(n_0_288) + ); + OAI22_X1_LVT i_0_304( + .A1(n_0_728), .A2(n_0_330), .B1(op2[1]), .B2(n_0_288), .ZN(n_0_287) + ); + AOI221_X1_LVT i_0_298( + .A(n_0_282), .B1(n_0_547), .B2(n_0_310), .C1(n_0_561), .C2(n_0_287), .ZN(n_0_281) + ); + INV_X1_LVT i_0_762( + .A(op1[1]), .ZN(n_0_729) + ); + OAI22_X1_LVT i_0_313( + .A1(n_0_722), .A2(n_0_615), .B1(n_0_729), .B2(n_0_617), .ZN(n_0_296) + ); + NAND2_X1_LVT i_0_312( + .A1(op2[2]), .A2(n_0_296), .ZN(n_0_295) + ); + OAI21_X1_LVT i_0_311( + .A(n_0_295), .B1(op2[2]), .B2(n_0_362), .ZN(n_0_294) + ); + NAND2_X1_LVT i_0_310( + .A1(op2[1]), .A2(n_0_294), .ZN(n_0_293) + ); + OAI21_X1_LVT i_0_309( + .A(n_0_293), .B1(op2[1]), .B2(n_0_336), .ZN(n_0_292) + ); + OAI22_X1_LVT i_0_308( + .A1(op2[0]), .A2(n_0_298), .B1(n_0_701), .B2(n_0_292), .ZN(n_0_291) + ); + OAI21_X1_LVT i_0_297( + .A(n_0_281), .B1(n_0_621), .B2(n_0_291), .ZN(result[16]) + ); + OAI221_X1_LVT i_0_286( + .A(op2[15]), .B1(n_0_734), .B2(n_0_567), .C1(op1[15]), .C2(n_0_564), .ZN(n_0_270) + ); + AOI21_X1_LVT i_0_288( + .A(n_0_314), .B1(n_15), .B2(n_0_581), .ZN(n_0_272) + ); + INV_X1_LVT i_0_287( + .A(n_0_272), .ZN(n_0_271) + ); + XNOR2_X1_LVT i_10_78( + .A(n_10_61), .B(n_10_62), .ZN(n_47) + ); + OAI21_X1_LVT i_0_285( + .A(n_0_681), .B1(op2[15]), .B2(n_0_568), .ZN(n_0_269) + ); + AOI221_X1_LVT i_0_284( + .A(n_0_271), .B1(n_47), .B2(n_0_580), .C1(op1[15]), .C2(n_0_269), .ZN(n_0_268) + ); + AOI22_X1_LVT i_0_296( + .A1(op1[8]), .A2(n_0_616), .B1(op1[0]), .B2(n_0_618), .ZN(n_0_280) + ); + AOI22_X1_LVT i_0_295( + .A1(op2[2]), .A2(n_0_280), .B1(n_0_693), .B2(n_0_356), .ZN(n_0_279) + ); + NAND2_X1_LVT i_0_294( + .A1(op2[1]), .A2(n_0_279), .ZN(n_0_278) + ); + OAI21_X1_LVT i_0_293( + .A(n_0_278), .B1(op2[1]), .B2(n_0_299), .ZN(n_0_277) + ); + OAI221_X1_LVT i_0_292( + .A(n_0_620), .B1(n_0_701), .B2(n_0_277), .C1(op2[0]), .C2(n_0_292), .ZN(n_0_276) + ); + OAI222_X1_LVT i_0_291( + .A1(n_0_719), .A2(n_0_617), .B1(n_0_691), .B2(n_0_605), .C1(n_0_734), .C2(n_0_615), + .ZN(n_0_275) + ); + OAI22_X1_LVT i_0_290( + .A1(n_0_693), .A2(n_0_349), .B1(op2[2]), .B2(n_0_275), .ZN(n_0_274) + ); + OAI22_X1_LVT i_0_289( + .A1(op2[1]), .A2(n_0_274), .B1(n_0_728), .B2(n_0_311), .ZN(n_0_273) + ); + AOI22_X1_LVT i_0_283( + .A1(n_0_561), .A2(n_0_273), .B1(n_0_547), .B2(n_0_287), .ZN(n_0_267) + ); + NAND4_X1_LVT i_0_282( + .A1(n_0_270), .A2(n_0_268), .A3(n_0_276), .A4(n_0_267), .ZN(result[15]) + ); + NOR2_X1_LVT i_0_278( + .A1(op2[0]), .A2(n_0_277), .ZN(n_0_263) + ); + NAND2_X1_LVT i_0_281( + .A1(n_0_612), .A2(n_0_575), .ZN(n_0_266) + ); + OAI21_X1_LVT i_0_280( + .A(n_0_266), .B1(n_0_713), .B2(n_0_497), .ZN(n_0_265) + ); + AOI22_X1_LVT i_0_279( + .A1(op2[1]), .A2(n_0_265), .B1(n_0_728), .B2(n_0_294), .ZN(n_0_264) + ); + AOI211_X1_LVT i_0_277( + .A(n_0_263), .B(n_0_621), .C1(op2[0]), .C2(n_0_264), .ZN(n_0_262) + ); + INV_X1_LVT i_0_754( + .A(op1[14]), .ZN(n_0_721) + ); + OAI21_X1_LVT i_0_273( + .A(op2[14]), .B1(n_0_721), .B2(n_0_567), .ZN(n_0_258) + ); + AOI21_X1_LVT i_0_272( + .A(n_0_258), .B1(n_0_721), .B2(n_0_565), .ZN(n_0_257) + ); + XNOR2_X1_LVT i_10_74( + .A(n_10_58), .B(n_10_59), .ZN(n_46) + ); + OAI21_X1_LVT i_0_276( + .A(n_0_681), .B1(op2[14]), .B2(n_0_568), .ZN(n_0_261) + ); + AOI222_X1_LVT i_0_275( + .A1(n_14), .A2(n_0_581), .B1(n_46), .B2(n_0_580), .C1(op1[14]), .C2(n_0_261), + .ZN(n_0_260) + ); + INV_X1_LVT i_0_274( + .A(n_0_260), .ZN(n_0_259) + ); + OAI222_X1_LVT i_0_271( + .A1(n_0_717), .A2(n_0_605), .B1(n_0_687), .B2(n_0_617), .C1(n_0_721), .C2(n_0_615), + .ZN(n_0_256) + ); + OAI22_X1_LVT i_0_270( + .A1(n_0_693), .A2(n_0_331), .B1(op2[2]), .B2(n_0_256), .ZN(n_0_255) + ); + AND2_X1_LVT i_0_269( + .A1(n_0_728), .A2(n_0_255), .ZN(n_0_254) + ); + NOR3_X1_LVT i_0_265( + .A1(op2[3]), .A2(op2[2]), .A3(op2[0]), .ZN(n_0_250) + ); + AOI21_X1_LVT i_0_268( + .A(n_0_254), .B1(op2[1]), .B2(n_0_288), .ZN(n_0_253) + ); + OAI22_X1_LVT i_0_266( + .A1(op2[0]), .A2(n_0_253), .B1(n_0_701), .B2(n_0_273), .ZN(n_0_251) + ); + AOI221_X1_LVT i_0_259( + .A(n_0_579), .B1(n_0_254), .B2(n_0_250), .C1(n_0_315), .C2(n_0_251), .ZN(n_0_244) + ); + OR4_X1_LVT i_0_258( + .A1(n_0_262), .A2(n_0_257), .A3(n_0_259), .A4(n_0_244), .ZN(result[14]) + ); + OAI221_X1_LVT i_0_245( + .A(op2[13]), .B1(op1[13]), .B2(n_0_564), .C1(n_0_714), .C2(n_0_567), .ZN(n_0_231) + ); + NAND2_X1_LVT i_0_244( + .A1(n_13), .A2(n_0_581), .ZN(n_0_230) + ); + OAI211_X1_LVT i_0_243( + .A(n_0_231), .B(n_0_230), .C1(n_0_714), .C2(n_0_681), .ZN(n_0_229) + ); + XNOR2_X1_LVT i_10_70( + .A(n_10_55), .B(n_10_56), .ZN(n_45) + ); + NOR2_X1_LVT i_0_695( + .A1(op2[13]), .A2(n_0_714), .ZN(n_0_662) + ); + AOI221_X1_LVT i_0_242( + .A(n_0_229), .B1(n_45), .B2(n_0_580), .C1(n_0_662), .C2(n_0_569), .ZN(n_0_228) + ); + INV_X1_LVT i_0_267( + .A(n_0_253), .ZN(n_0_252) + ); + OAI222_X1_LVT i_0_257( + .A1(n_0_714), .A2(n_0_615), .B1(n_0_726), .B2(n_0_617), .C1(n_0_710), .C2(n_0_605), + .ZN(n_0_243) + ); + OAI22_X1_LVT i_0_256( + .A1(n_0_693), .A2(n_0_312), .B1(op2[2]), .B2(n_0_243), .ZN(n_0_242) + ); + NAND2_X1_LVT i_0_255( + .A1(n_0_728), .A2(n_0_242), .ZN(n_0_241) + ); + NAND2_X1_LVT i_0_254( + .A1(op2[1]), .A2(n_0_274), .ZN(n_0_240) + ); + NAND2_X1_LVT i_0_241( + .A1(n_0_241), .A2(n_0_240), .ZN(n_0_227) + ); + OAI221_X1_LVT i_0_240( + .A(n_0_228), .B1(n_0_548), .B2(n_0_252), .C1(n_0_562), .C2(n_0_227), .ZN(n_0_226) + ); + NAND2_X1_LVT i_0_249( + .A1(n_0_728), .A2(n_0_279), .ZN(n_0_235) + ); + AOI22_X1_LVT i_0_250( + .A1(n_0_597), .A2(n_0_575), .B1(op1[6]), .B2(n_0_496), .ZN(n_0_236) + ); + OAI21_X1_LVT i_0_248( + .A(n_0_235), .B1(n_0_728), .B2(n_0_236), .ZN(n_0_234) + ); + INV_X1_LVT i_0_247( + .A(n_0_234), .ZN(n_0_233) + ); + AOI221_X1_LVT i_0_246( + .A(n_0_621), .B1(op2[0]), .B2(n_0_233), .C1(n_0_701), .C2(n_0_264), .ZN(n_0_232) + ); + NAND2_X1_LVT i_0_264( + .A1(op2[3]), .A2(n_0_469), .ZN(n_0_249) + ); + AOI21_X1_LVT i_0_262( + .A(n_0_468), .B1(n_0_693), .B2(n_0_249), .ZN(n_0_247) + ); + INV_X1_LVT i_0_261( + .A(n_0_247), .ZN(n_0_246) + ); + OAI211_X1_LVT i_0_260( + .A(n_0_252), .B(n_0_246), .C1(n_0_468), .C2(n_0_254), .ZN(n_0_245) + ); + OAI221_X1_LVT i_0_253( + .A(n_0_544), .B1(n_0_247), .B2(n_0_241), .C1(n_0_469), .C2(n_0_240), .ZN(n_0_239) + ); + INV_X1_LVT i_0_252( + .A(n_0_239), .ZN(n_0_238) + ); + AOI211_X1_LVT i_0_239( + .A(n_0_226), .B(n_0_232), .C1(n_0_245), .C2(n_0_238), .ZN(n_0_225) + ); + INV_X1_LVT i_0_238( + .A(n_0_225), .ZN(result[13]) + ); + OAI221_X1_LVT i_0_232( + .A(op2[12]), .B1(n_0_696), .B2(n_0_567), .C1(op1[12]), .C2(n_0_564), .ZN(n_0_219) + ); + OAI21_X1_LVT i_0_231( + .A(n_0_681), .B1(op2[12]), .B2(n_0_568), .ZN(n_0_218) + ); + XNOR2_X1_LVT i_10_66( + .A(n_10_52), .B(n_10_53), .ZN(n_44) + ); + AOI222_X1_LVT i_0_230( + .A1(n_12), .A2(n_0_581), .B1(op1[12]), .B2(n_0_218), .C1(n_44), .C2(n_0_580), + .ZN(n_0_217) + ); + OAI21_X1_LVT i_0_234( + .A(n_0_620), .B1(op2[1]), .B2(n_0_265), .ZN(n_0_221) + ); + INV_X1_LVT i_0_763( + .A(op1[5]), .ZN(n_0_730) + ); + OAI21_X1_LVT i_0_236( + .A(op2[2]), .B1(n_0_730), .B2(n_0_615), .ZN(n_0_223) + ); + OAI21_X1_LVT i_0_235( + .A(n_0_223), .B1(op2[2]), .B2(n_0_296), .ZN(n_0_222) + ); + AOI21_X1_LVT i_0_233( + .A(n_0_221), .B1(op2[1]), .B2(n_0_222), .ZN(n_0_220) + ); + NOR2_X1_LVT i_0_237( + .A1(n_0_577), .A2(n_0_227), .ZN(n_0_224) + ); + NOR4_X1_LVT i_0_223( + .A1(n_0_701), .A2(n_0_220), .A3(n_0_224), .A4(n_0_238), .ZN(n_0_210) + ); + NAND2_X1_LVT i_0_224( + .A1(n_0_544), .A2(n_0_247), .ZN(n_0_211) + ); + NAND2_X1_LVT i_0_222( + .A1(n_0_701), .A2(n_0_211), .ZN(n_0_209) + ); + OAI22_X1_LVT i_0_229( + .A1(op2[4]), .A2(n_0_696), .B1(n_0_738), .B2(n_0_698), .ZN(n_0_216) + ); + INV_X1_LVT i_0_228( + .A(n_0_216), .ZN(n_0_215) + ); + OAI22_X1_LVT i_0_227( + .A1(n_0_727), .A2(n_0_617), .B1(op2[3]), .B2(n_0_215), .ZN(n_0_214) + ); + OAI22_X1_LVT i_0_226( + .A1(n_0_693), .A2(n_0_289), .B1(op2[2]), .B2(n_0_214), .ZN(n_0_213) + ); + OAI22_X1_LVT i_0_225( + .A1(op2[1]), .A2(n_0_213), .B1(n_0_728), .B2(n_0_255), .ZN(n_0_212) + ); + AOI221_X1_LVT i_0_221( + .A(n_0_209), .B1(n_0_578), .B2(n_0_212), .C1(n_0_620), .C2(n_0_234), .ZN(n_0_208) + ); + OAI211_X1_LVT i_0_220( + .A(n_0_219), .B(n_0_217), .C1(n_0_210), .C2(n_0_208), .ZN(result[12]) + ); + OAI21_X1_LVT i_0_209( + .A(n_0_681), .B1(op2[11]), .B2(n_0_568), .ZN(n_0_197) + ); + AOI22_X1_LVT i_0_208( + .A1(n_11), .A2(n_0_581), .B1(op1[11]), .B2(n_0_197), .ZN(n_0_196) + ); + NAND2_X1_LVT i_0_207( + .A1(n_0_211), .A2(n_0_196), .ZN(n_0_195) + ); + AOI22_X1_LVT i_0_210( + .A1(op1[11]), .A2(n_0_566), .B1(n_0_706), .B2(n_0_565), .ZN(n_0_198) + ); + XNOR2_X1_LVT i_10_62( + .A(n_10_49), .B(n_10_50), .ZN(n_43) + ); + AOI221_X1_LVT i_0_206( + .A(n_0_195), .B1(op2[11]), .B2(n_0_198), .C1(n_43), .C2(n_0_580), .ZN(n_0_194) + ); + AOI221_X1_LVT i_0_215( + .A(op2[3]), .B1(n_0_738), .B2(n_0_706), .C1(op2[4]), .C2(n_0_688), .ZN(n_0_203) + ); + AOI21_X1_LVT i_0_214( + .A(n_0_203), .B1(op1[19]), .B2(n_0_618), .ZN(n_0_202) + ); + NAND2_X1_LVT i_0_213( + .A1(n_0_693), .A2(n_0_202), .ZN(n_0_201) + ); + OAI21_X1_LVT i_0_212( + .A(n_0_201), .B1(n_0_693), .B2(n_0_275), .ZN(n_0_200) + ); + OAI22_X1_LVT i_0_211( + .A1(n_0_728), .A2(n_0_242), .B1(op2[1]), .B2(n_0_200), .ZN(n_0_199) + ); + AOI22_X1_LVT i_0_205( + .A1(n_0_561), .A2(n_0_199), .B1(n_0_701), .B2(n_0_220), .ZN(n_0_193) + ); + NOR2_X1_LVT i_0_219( + .A1(op2[2]), .A2(n_0_280), .ZN(n_0_207) + ); + AOI21_X1_LVT i_0_218( + .A(n_0_207), .B1(op1[4]), .B2(n_0_496), .ZN(n_0_206) + ); + AOI22_X1_LVT i_0_217( + .A1(n_0_728), .A2(n_0_236), .B1(op2[1]), .B2(n_0_206), .ZN(n_0_205) + ); + AOI22_X1_LVT i_0_216( + .A1(n_0_578), .A2(n_0_212), .B1(n_0_620), .B2(n_0_205), .ZN(n_0_204) + ); + OAI211_X1_LVT i_0_204( + .A(n_0_194), .B(n_0_193), .C1(n_0_701), .C2(n_0_204), .ZN(result[11]) + ); + AOI22_X1_LVT i_0_194( + .A1(n_0_654), .A2(n_0_498), .B1(op1[7]), .B2(n_0_573), .ZN(n_0_183) + ); + OAI22_X1_LVT i_0_193( + .A1(n_0_728), .A2(n_0_183), .B1(op2[1]), .B2(n_0_222), .ZN(n_0_182) + ); + AOI22_X1_LVT i_0_192( + .A1(op2[0]), .A2(n_0_182), .B1(n_0_701), .B2(n_0_205), .ZN(n_0_181) + ); + NOR2_X1_LVT i_0_191( + .A1(n_0_621), .A2(n_0_181), .ZN(n_0_180) + ); + AOI22_X1_LVT i_0_190( + .A1(op1[10]), .A2(n_0_566), .B1(n_0_733), .B2(n_0_565), .ZN(n_0_179) + ); + XNOR2_X1_LVT i_10_58( + .A(n_10_46), .B(n_10_47), .ZN(n_42) + ); + AOI22_X1_LVT i_0_188( + .A1(op2[10]), .A2(n_0_179), .B1(n_42), .B2(n_0_580), .ZN(n_0_177) + ); + OAI21_X1_LVT i_0_189( + .A(n_0_681), .B1(op2[10]), .B2(n_0_568), .ZN(n_0_178) + ); + AOI22_X1_LVT i_0_187( + .A1(n_10), .A2(n_0_581), .B1(op1[10]), .B2(n_0_178), .ZN(n_0_176) + ); + NAND2_X1_LVT i_0_186( + .A1(n_0_177), .A2(n_0_176), .ZN(n_0_175) + ); + NOR2_X1_LVT i_0_203( + .A1(n_0_701), .A2(n_0_199), .ZN(n_0_192) + ); + NOR2_X1_LVT i_0_200( + .A1(n_0_693), .A2(n_0_256), .ZN(n_0_189) + ); + AOI221_X1_LVT i_0_202( + .A(n_0_596), .B1(op1[10]), .B2(n_0_616), .C1(op1[26]), .C2(n_0_606), .ZN(n_0_191) + ); + AOI21_X1_LVT i_0_199( + .A(n_0_189), .B1(n_0_693), .B2(n_0_191), .ZN(n_0_188) + ); + OR2_X1_LVT i_0_198( + .A1(op2[1]), .A2(n_0_188), .ZN(n_0_187) + ); + NAND2_X1_LVT i_0_197( + .A1(op2[1]), .A2(n_0_213), .ZN(n_0_186) + ); + NAND2_X1_LVT i_0_185( + .A1(n_0_187), .A2(n_0_186), .ZN(n_0_174) + ); + AOI211_X1_LVT i_0_184( + .A(n_0_577), .B(n_0_192), .C1(n_0_701), .C2(n_0_174), .ZN(n_0_173) + ); + INV_X1_LVT i_0_263( + .A(n_0_249), .ZN(n_0_248) + ); + OAI22_X1_LVT i_0_196( + .A1(n_0_248), .A2(n_0_187), .B1(n_0_247), .B2(n_0_186), .ZN(n_0_185) + ); + AOI221_X1_LVT i_0_195( + .A(n_0_545), .B1(n_0_246), .B2(n_0_192), .C1(n_0_701), .C2(n_0_185), .ZN(n_0_184) + ); + OR4_X1_LVT i_0_183( + .A1(n_0_180), .A2(n_0_175), .A3(n_0_173), .A4(n_0_184), .ZN(result[10]) + ); + INV_X1_LVT i_0_753( + .A(op2[9]), .ZN(n_0_720) + ); + AOI221_X1_LVT i_0_171( + .A(n_0_720), .B1(op1[9]), .B2(n_0_566), .C1(n_0_722), .C2(n_0_565), .ZN(n_0_161) + ); + XNOR2_X1_LVT i_10_54( + .A(n_10_43), .B(n_10_44), .ZN(n_41) + ); + AOI22_X1_LVT i_0_172( + .A1(n_9), .A2(n_0_581), .B1(n_41), .B2(n_0_580), .ZN(n_0_162) + ); + AOI21_X1_LVT i_0_170( + .A(aluBypass), .B1(n_0_720), .B2(n_0_569), .ZN(n_0_160) + ); + OAI21_X1_LVT i_0_169( + .A(n_0_162), .B1(n_0_722), .B2(n_0_160), .ZN(n_0_159) + ); + OAI222_X1_LVT i_0_182( + .A1(n_0_722), .A2(n_0_615), .B1(n_0_699), .B2(n_0_605), .C1(n_0_732), .C2(n_0_617), + .ZN(n_0_172) + ); + AOI22_X1_LVT i_0_181( + .A1(n_0_693), .A2(n_0_172), .B1(op2[2]), .B2(n_0_243), .ZN(n_0_171) + ); + NAND2_X1_LVT i_0_180( + .A1(n_0_728), .A2(n_0_171), .ZN(n_0_170) + ); + NAND2_X1_LVT i_0_179( + .A1(op2[1]), .A2(n_0_200), .ZN(n_0_169) + ); + OAI22_X1_LVT i_0_178( + .A1(n_0_248), .A2(n_0_170), .B1(n_0_247), .B2(n_0_169), .ZN(n_0_168) + ); + NOR3_X1_LVT i_0_177( + .A1(n_0_545), .A2(n_0_168), .A3(n_0_185), .ZN(n_0_167) + ); + NOR2_X1_LVT i_0_251( + .A1(n_0_704), .A2(n_0_615), .ZN(n_0_237) + ); + OAI22_X1_LVT i_0_176( + .A1(op1[2]), .A2(n_0_693), .B1(n_0_496), .B2(n_0_237), .ZN(n_0_166) + ); + OAI22_X1_LVT i_0_175( + .A1(op2[1]), .A2(n_0_206), .B1(n_0_728), .B2(n_0_166), .ZN(n_0_165) + ); + OAI221_X1_LVT i_0_174( + .A(n_0_620), .B1(op2[0]), .B2(n_0_182), .C1(n_0_701), .C2(n_0_165), .ZN(n_0_164) + ); + NAND2_X1_LVT i_0_173( + .A1(n_0_170), .A2(n_0_169), .ZN(n_0_163) + ); + OAI221_X1_LVT i_0_168( + .A(n_0_164), .B1(n_0_562), .B2(n_0_163), .C1(n_0_548), .C2(n_0_174), .ZN(n_0_158) + ); + OR4_X1_LVT i_0_167( + .A1(n_0_161), .A2(n_0_159), .A3(n_0_167), .A4(n_0_158), .ZN(result[9]) + ); + OAI21_X1_LVT i_0_160( + .A(n_0_693), .B1(n_0_730), .B2(n_0_615), .ZN(n_0_151) + ); + OAI21_X1_LVT i_0_159( + .A(op2[2]), .B1(n_0_729), .B2(n_0_615), .ZN(n_0_150) + ); + AND2_X1_LVT i_0_158( + .A1(n_0_151), .A2(n_0_150), .ZN(n_0_149) + ); + NAND2_X1_LVT i_0_157( + .A1(op2[1]), .A2(n_0_149), .ZN(n_0_148) + ); + OAI21_X1_LVT i_0_156( + .A(n_0_148), .B1(op2[1]), .B2(n_0_183), .ZN(n_0_147) + ); + OAI22_X1_LVT i_0_155( + .A1(op2[0]), .A2(n_0_165), .B1(n_0_701), .B2(n_0_147), .ZN(n_0_146) + ); + NOR2_X1_LVT i_0_154( + .A1(n_0_621), .A2(n_0_146), .ZN(n_0_145) + ); + INV_X1_LVT i_0_773( + .A(op1[8]), .ZN(n_0_740) + ); + NOR2_X1_LVT i_0_688( + .A1(n_0_740), .A2(op2[8]), .ZN(n_0_655) + ); + AOI22_X1_LVT i_0_153( + .A1(op1[8]), .A2(aluBypass), .B1(n_0_655), .B2(n_0_569), .ZN(n_0_144) + ); + OAI221_X1_LVT i_0_152( + .A(op2[8]), .B1(op1[8]), .B2(n_0_564), .C1(n_0_740), .C2(n_0_567), .ZN(n_0_143) + ); + XNOR2_X1_LVT i_10_51( + .A(n_10_39), .B(n_10_42), .ZN(n_40) + ); + AOI22_X1_LVT i_0_151( + .A1(n_40), .A2(n_0_580), .B1(n_8), .B2(n_0_581), .ZN(n_0_142) + ); + NAND3_X1_LVT i_0_150( + .A1(n_0_144), .A2(n_0_143), .A3(n_0_142), .ZN(n_0_141) + ); + OAI222_X1_LVT i_0_166( + .A1(n_0_740), .A2(n_0_615), .B1(n_0_739), .B2(n_0_617), .C1(n_0_736), .C2(n_0_605), + .ZN(n_0_157) + ); + OAI22_X1_LVT i_0_165( + .A1(op2[2]), .A2(n_0_157), .B1(n_0_693), .B2(n_0_214), .ZN(n_0_156) + ); + NOR2_X1_LVT i_0_164( + .A1(op2[1]), .A2(n_0_156), .ZN(n_0_155) + ); + AOI21_X1_LVT i_0_163( + .A(n_0_155), .B1(op2[1]), .B2(n_0_188), .ZN(n_0_154) + ); + AND2_X1_LVT i_0_162( + .A1(n_0_701), .A2(n_0_154), .ZN(n_0_153) + ); + AOI211_X1_LVT i_0_149( + .A(n_0_577), .B(n_0_153), .C1(op2[0]), .C2(n_0_163), .ZN(n_0_140) + ); + AOI221_X1_LVT i_0_161( + .A(n_0_545), .B1(op2[0]), .B2(n_0_168), .C1(n_0_249), .C2(n_0_153), .ZN(n_0_152) + ); + OR4_X1_LVT i_0_148( + .A1(n_0_145), .A2(n_0_141), .A3(n_0_140), .A4(n_0_152), .ZN(result[8]) + ); + AOI22_X1_LVT i_0_138( + .A1(op1[4]), .A2(n_0_573), .B1(op1[0]), .B2(n_0_496), .ZN(n_0_130) + ); + AOI22_X1_LVT i_0_137( + .A1(op2[1]), .A2(n_0_130), .B1(n_0_728), .B2(n_0_166), .ZN(n_0_129) + ); + OAI22_X1_LVT i_0_136( + .A1(n_0_701), .A2(n_0_129), .B1(op2[0]), .B2(n_0_147), .ZN(n_0_128) + ); + NOR2_X1_LVT i_0_135( + .A1(n_0_621), .A2(n_0_128), .ZN(n_0_127) + ); + OAI221_X1_LVT i_0_139( + .A(op2[7]), .B1(n_0_713), .B2(n_0_567), .C1(op1[7]), .C2(n_0_564), .ZN(n_0_131) + ); + INV_X1_LVT i_10_44( + .A(n_10_36), .ZN(n_10_37) + ); + NOR2_X1_LVT i_10_45( + .A1(n_10_35), .A2(n_10_37), .ZN(n_10_38) + ); + XNOR2_X1_LVT i_10_46( + .A(n_10_33), .B(n_10_38), .ZN(n_39) + ); + AOI22_X1_LVT i_0_141( + .A1(n_7), .A2(n_0_581), .B1(n_39), .B2(n_0_580), .ZN(n_0_133) + ); + INV_X1_LVT i_0_745( + .A(op2[7]), .ZN(n_0_712) + ); + AOI21_X1_LVT i_0_140( + .A(aluBypass), .B1(n_0_712), .B2(n_0_569), .ZN(n_0_132) + ); + OAI211_X1_LVT i_0_133( + .A(n_0_131), .B(n_0_133), .C1(n_0_713), .C2(n_0_132), .ZN(n_0_125) + ); + OAI22_X1_LVT i_0_147( + .A1(n_0_734), .A2(n_0_617), .B1(n_0_713), .B2(n_0_615), .ZN(n_0_139) + ); + AOI211_X1_LVT i_0_146( + .A(n_0_139), .B(n_0_248), .C1(op1[23]), .C2(n_0_606), .ZN(n_0_138) + ); + OAI22_X1_LVT i_0_145( + .A1(n_0_693), .A2(n_0_202), .B1(op2[2]), .B2(n_0_138), .ZN(n_0_137) + ); + NOR2_X1_LVT i_0_144( + .A1(op2[1]), .A2(n_0_137), .ZN(n_0_136) + ); + AOI21_X1_LVT i_0_143( + .A(n_0_136), .B1(op2[1]), .B2(n_0_171), .ZN(n_0_135) + ); + NAND2_X1_LVT i_0_142( + .A1(n_0_561), .A2(n_0_135), .ZN(n_0_134) + ); + OAI221_X1_LVT i_0_134( + .A(n_0_134), .B1(n_0_548), .B2(n_0_154), .C1(n_0_545), .C2(n_0_249), .ZN(n_0_126) + ); + OR3_X1_LVT i_0_132( + .A1(n_0_127), .A2(n_0_125), .A3(n_0_126), .ZN(result[7]) + ); + NAND2_X1_LVT i_0_124( + .A1(n_0_728), .A2(n_0_149), .ZN(n_0_117) + ); + OAI21_X1_LVT i_0_123( + .A(n_0_117), .B1(n_0_724), .B2(n_0_531), .ZN(n_0_116) + ); + OAI22_X1_LVT i_0_122( + .A1(n_0_701), .A2(n_0_116), .B1(op2[0]), .B2(n_0_129), .ZN(n_0_115) + ); + NOR2_X1_LVT i_0_121( + .A1(n_0_621), .A2(n_0_115), .ZN(n_0_114) + ); + XNOR2_X1_LVT i_10_38( + .A(n_10_30), .B(n_10_31), .ZN(n_38) + ); + AOI22_X1_LVT i_0_119( + .A1(n_6), .A2(n_0_581), .B1(n_38), .B2(n_0_580), .ZN(n_0_112) + ); + INV_X1_LVT i_0_735( + .A(op2[6]), .ZN(n_0_702) + ); + AOI21_X1_LVT i_0_120( + .A(aluBypass), .B1(n_0_702), .B2(n_0_569), .ZN(n_0_113) + ); + OAI21_X1_LVT i_0_118( + .A(n_0_112), .B1(n_0_704), .B2(n_0_113), .ZN(n_0_111) + ); + AOI221_X1_LVT i_0_117( + .A(n_0_702), .B1(n_0_704), .B2(n_0_565), .C1(op1[6]), .C2(n_0_566), .ZN(n_0_110) + ); + NOR3_X1_LVT i_0_116( + .A1(n_0_114), .A2(n_0_111), .A3(n_0_110), .ZN(n_0_109) + ); + AOI221_X1_LVT i_0_131( + .A(n_0_237), .B1(op1[14]), .B2(n_0_618), .C1(op2[4]), .C2(n_0_406), .ZN(n_0_124) + ); + NAND2_X1_LVT i_0_130( + .A1(n_0_693), .A2(n_0_124), .ZN(n_0_123) + ); + INV_X1_LVT i_0_201( + .A(n_0_191), .ZN(n_0_190) + ); + OAI21_X1_LVT i_0_129( + .A(n_0_123), .B1(n_0_693), .B2(n_0_190), .ZN(n_0_122) + ); + AOI22_X1_LVT i_0_128( + .A1(n_0_728), .A2(n_0_122), .B1(op2[1]), .B2(n_0_156), .ZN(n_0_121) + ); + INV_X1_LVT i_0_127( + .A(n_0_121), .ZN(n_0_120) + ); + OAI21_X1_LVT i_0_126( + .A(n_0_248), .B1(op2[1]), .B2(n_0_123), .ZN(n_0_119) + ); + AND2_X1_LVT i_0_125( + .A1(n_0_120), .A2(n_0_119), .ZN(n_0_118) + ); + NOR2_X1_LVT i_0_115( + .A1(n_0_545), .A2(n_0_118), .ZN(n_0_108) + ); + AOI21_X1_LVT i_0_114( + .A(n_0_108), .B1(n_0_576), .B2(n_0_121), .ZN(n_0_107) + ); + AOI22_X1_LVT i_0_113( + .A1(n_0_544), .A2(n_0_248), .B1(n_0_578), .B2(n_0_135), .ZN(n_0_106) + ); + OAI221_X1_LVT i_0_112( + .A(n_0_109), .B1(op2[0]), .B2(n_0_107), .C1(n_0_701), .C2(n_0_106), .ZN(result[6]) + ); + OAI221_X1_LVT i_0_100( + .A(op2[5]), .B1(op1[5]), .B2(n_0_564), .C1(n_0_730), .C2(n_0_567), .ZN(n_0_94) + ); + INV_X1_LVT i_0_764( + .A(op2[5]), .ZN(n_0_731) + ); + AOI21_X1_LVT i_0_99( + .A(aluBypass), .B1(n_0_731), .B2(n_0_569), .ZN(n_0_93) + ); + NOR2_X1_LVT i_0_98( + .A1(n_0_730), .A2(n_0_93), .ZN(n_0_92) + ); + XNOR2_X1_LVT i_10_35( + .A(n_10_26), .B(n_10_29), .ZN(n_37) + ); + AOI221_X1_LVT i_0_97( + .A(n_0_92), .B1(n_37), .B2(n_0_580), .C1(n_5), .C2(n_0_581), .ZN(n_0_91) + ); + OAI22_X1_LVT i_0_102( + .A1(n_0_694), .A2(n_0_531), .B1(op2[1]), .B2(n_0_130), .ZN(n_0_96) + ); + OAI221_X1_LVT i_0_101( + .A(n_0_620), .B1(n_0_701), .B2(n_0_96), .C1(op2[0]), .C2(n_0_116), .ZN(n_0_95) + ); + NAND3_X1_LVT i_0_111( + .A1(n_0_544), .A2(n_0_248), .A3(op2[2]), .ZN(n_0_105) + ); + NAND2_X1_LVT i_0_110( + .A1(op2[4]), .A2(n_0_386), .ZN(n_0_104) + ); + OAI21_X1_LVT i_0_109( + .A(n_0_104), .B1(n_0_714), .B2(n_0_617), .ZN(n_0_103) + ); + OAI22_X1_LVT i_0_108( + .A1(n_0_151), .A2(n_0_103), .B1(n_0_693), .B2(n_0_172), .ZN(n_0_102) + ); + NOR2_X1_LVT i_0_107( + .A1(op2[1]), .A2(n_0_102), .ZN(n_0_101) + ); + AOI21_X1_LVT i_0_106( + .A(n_0_101), .B1(op2[1]), .B2(n_0_137), .ZN(n_0_100) + ); + OAI21_X1_LVT i_0_105( + .A(n_0_105), .B1(n_0_579), .B2(n_0_100), .ZN(n_0_99) + ); + AOI21_X1_LVT i_0_104( + .A(n_0_118), .B1(n_0_682), .B2(n_0_120), .ZN(n_0_98) + ); + OAI22_X1_LVT i_0_103( + .A1(n_0_547), .A2(n_0_99), .B1(n_0_701), .B2(n_0_98), .ZN(n_0_97) + ); + NAND4_X1_LVT i_0_96( + .A1(n_0_94), .A2(n_0_91), .A3(n_0_95), .A4(n_0_97), .ZN(result[5]) + ); + INV_X1_LVT i_10_26( + .A(n_10_21), .ZN(n_10_22) + ); + NOR2_X1_LVT i_10_28( + .A1(n_10_22), .A2(n_10_23), .ZN(n_10_24) + ); + XNOR2_X1_LVT i_10_29( + .A(n_10_19), .B(n_10_24), .ZN(n_36) + ); + AOI222_X1_LVT i_0_89( + .A1(n_4), .A2(n_0_581), .B1(n_36), .B2(n_0_580), .C1(n_0_668), .C2(n_0_564), + .ZN(n_0_84) + ); + INV_X1_LVT i_0_770( + .A(op1[4]), .ZN(n_0_737) + ); + AOI221_X1_LVT i_0_90( + .A(aluBypass), .B1(op2[4]), .B2(n_0_567), .C1(n_0_738), .C2(n_0_569), .ZN(n_0_85) + ); + OAI21_X1_LVT i_0_88( + .A(n_0_84), .B1(n_0_737), .B2(n_0_85), .ZN(n_0_83) + ); + NOR2_X1_LVT i_0_689( + .A1(op2[4]), .A2(n_0_737), .ZN(n_0_656) + ); + AOI21_X1_LVT i_0_95( + .A(n_0_616), .B1(n_0_727), .B2(n_0_723), .ZN(n_0_90) + ); + OAI22_X1_LVT i_0_94( + .A1(n_0_723), .A2(n_0_216), .B1(n_0_656), .B2(n_0_90), .ZN(n_0_89) + ); + INV_X1_LVT i_0_93( + .A(n_0_89), .ZN(n_0_88) + ); + OAI22_X1_LVT i_0_92( + .A1(op2[2]), .A2(n_0_88), .B1(n_0_693), .B2(n_0_157), .ZN(n_0_87) + ); + OAI221_X1_LVT i_0_91( + .A(n_0_105), .B1(n_0_728), .B2(n_0_122), .C1(op2[1]), .C2(n_0_87), .ZN(n_0_86) + ); + AOI221_X1_LVT i_0_85( + .A(n_0_83), .B1(n_0_561), .B2(n_0_86), .C1(op2[0]), .C2(n_0_99), .ZN(n_0_80) + ); + AOI221_X1_LVT i_0_87( + .A(n_0_574), .B1(n_0_729), .B2(op2[1]), .C1(n_0_728), .C2(n_0_724), .ZN(n_0_82) + ); + OAI22_X1_LVT i_0_86( + .A1(op2[0]), .A2(n_0_96), .B1(n_0_701), .B2(n_0_82), .ZN(n_0_81) + ); + OAI21_X1_LVT i_0_84( + .A(n_0_80), .B1(n_0_621), .B2(n_0_81), .ZN(result[4]) + ); + AND2_X1_LVT i_0_81( + .A1(op2[1]), .A2(n_0_105), .ZN(n_0_77) + ); + NAND2_X1_LVT i_0_80( + .A1(n_0_102), .A2(n_0_77), .ZN(n_0_76) + ); + OAI221_X1_LVT i_0_83( + .A(n_0_693), .B1(n_0_654), .B2(n_0_484), .C1(n_0_738), .C2(n_0_350), .ZN(n_0_79) + ); + OAI21_X1_LVT i_0_82( + .A(n_0_79), .B1(n_0_693), .B2(n_0_138), .ZN(n_0_78) + ); + OAI21_X1_LVT i_0_79( + .A(n_0_76), .B1(op2[1]), .B2(n_0_78), .ZN(n_0_75) + ); + NOR2_X1_LVT i_0_78( + .A1(n_0_562), .A2(n_0_75), .ZN(n_0_74) + ); + NAND2_X1_LVT i_10_20( + .A1(n_10_15), .A2(n_10_16), .ZN(n_10_17) + ); + XNOR2_X1_LVT i_10_21( + .A(n_10_13), .B(n_10_17), .ZN(n_35) + ); + AOI22_X1_LVT i_0_75( + .A1(n_35), .A2(n_0_580), .B1(n_3), .B2(n_0_581), .ZN(n_0_71) + ); + OAI21_X1_LVT i_0_74( + .A(n_0_681), .B1(n_0_723), .B2(n_0_566), .ZN(n_0_70) + ); + AOI222_X1_LVT i_0_73( + .A1(n_0_654), .A2(n_0_569), .B1(n_0_663), .B2(n_0_564), .C1(op1[3]), .C2(n_0_70), + .ZN(n_0_69) + ); + INV_X1_LVT i_0_736( + .A(op1[0]), .ZN(n_0_703) + ); + OAI22_X1_LVT i_0_77( + .A1(n_0_703), .A2(n_0_531), .B1(n_0_694), .B2(n_0_572), .ZN(n_0_73) + ); + OAI22_X1_LVT i_0_76( + .A1(n_0_701), .A2(n_0_73), .B1(op2[0]), .B2(n_0_82), .ZN(n_0_72) + ); + OAI211_X1_LVT i_0_72( + .A(n_0_71), .B(n_0_69), .C1(n_0_621), .C2(n_0_72), .ZN(n_0_68) + ); + AOI211_X1_LVT i_0_71( + .A(n_0_74), .B(n_0_68), .C1(n_0_547), .C2(n_0_86), .ZN(n_0_67) + ); + INV_X1_LVT i_0_70( + .A(n_0_67), .ZN(result[3]) + ); + NAND2_X1_LVT i_0_65( + .A1(n_2), .A2(n_0_581), .ZN(n_0_62) + ); + OAI221_X1_LVT i_0_66( + .A(op2[2]), .B1(op1[2]), .B2(n_0_564), .C1(n_0_694), .C2(n_0_567), .ZN(n_0_63) + ); + AOI21_X1_LVT i_0_64( + .A(aluBypass), .B1(n_0_693), .B2(n_0_569), .ZN(n_0_61) + ); + OAI21_X1_LVT i_0_63( + .A(n_0_63), .B1(n_0_694), .B2(n_0_61), .ZN(n_0_60) + ); + INV_X1_LVT i_10_13( + .A(n_10_10), .ZN(n_10_11) + ); + NOR2_X1_LVT i_10_14( + .A1(n_10_9), .A2(n_10_11), .ZN(n_10_12) + ); + XNOR2_X1_LVT i_10_15( + .A(n_10_7), .B(n_10_12), .ZN(n_34) + ); + AOI21_X1_LVT i_0_62( + .A(n_0_60), .B1(n_34), .B2(n_0_580), .ZN(n_0_59) + ); + OAI211_X1_LVT i_0_57( + .A(n_0_62), .B(n_0_59), .C1(n_0_548), .C2(n_0_75), .ZN(n_0_54) + ); + NOR2_X1_LVT i_0_698( + .A1(n_0_729), .A2(op2[1]), .ZN(n_0_665) + ); + INV_X1_LVT i_0_697( + .A(n_0_665), .ZN(n_0_664) + ); + OAI21_X1_LVT i_0_69( + .A(op2[0]), .B1(n_0_664), .B2(n_0_574), .ZN(n_0_66) + ); + OAI21_X1_LVT i_0_68( + .A(n_0_620), .B1(op2[0]), .B2(n_0_73), .ZN(n_0_65) + ); + INV_X1_LVT i_0_67( + .A(n_0_65), .ZN(n_0_64) + ); + OAI222_X1_LVT i_0_61( + .A1(op1[10]), .A2(n_0_617), .B1(op1[2]), .B2(n_0_615), .C1(n_0_738), .C2(n_0_332), + .ZN(n_0_58) + ); + OAI22_X1_LVT i_0_60( + .A1(op2[2]), .A2(n_0_58), .B1(n_0_693), .B2(n_0_124), .ZN(n_0_57) + ); + INV_X1_LVT i_0_59( + .A(n_0_57), .ZN(n_0_56) + ); + AOI22_X1_LVT i_0_58( + .A1(n_0_728), .A2(n_0_56), .B1(n_0_87), .B2(n_0_77), .ZN(n_0_55) + ); + AOI221_X1_LVT i_0_56( + .A(n_0_54), .B1(n_0_66), .B2(n_0_64), .C1(n_0_561), .C2(n_0_55), .ZN(n_0_53) + ); + INV_X1_LVT i_0_55( + .A(n_0_53), .ZN(result[2]) + ); + NAND2_X1_LVT i_0_54( + .A1(n_0_547), .A2(n_0_55), .ZN(n_0_52) + ); + AOI221_X1_LVT i_0_47( + .A(n_0_728), .B1(n_0_729), .B2(n_0_565), .C1(op1[1]), .C2(n_0_566), .ZN(n_0_45) + ); + NOR2_X1_LVT i_0_700( + .A1(op1[0]), .A2(n_0_701), .ZN(n_0_667) + ); + AOI211_X1_LVT i_0_48( + .A(n_0_667), .B(n_0_621), .C1(n_0_729), .C2(n_0_701), .ZN(n_0_46) + ); + AOI221_X1_LVT i_0_44( + .A(n_0_45), .B1(op1[1]), .B2(aluBypass), .C1(n_0_571), .C2(n_0_46), .ZN(n_0_42) + ); + NAND2_X1_LVT i_10_6( + .A1(n_10_3), .A2(n_10_4), .ZN(n_10_5) + ); + XNOR2_X1_LVT i_10_7( + .A(n_10_5), .B(n_10_1), .ZN(n_33) + ); + AOI22_X1_LVT i_0_49( + .A1(n_33), .A2(n_0_580), .B1(n_1), .B2(n_0_581), .ZN(n_0_47) + ); + OAI21_X1_LVT i_0_46( + .A(n_0_47), .B1(n_0_664), .B2(n_0_568), .ZN(n_0_44) + ); + NAND2_X1_LVT i_0_51( + .A1(op2[1]), .A2(n_0_78), .ZN(n_0_49) + ); + OAI222_X1_LVT i_0_53( + .A1(n_0_722), .A2(n_0_617), .B1(n_0_729), .B2(n_0_615), .C1(n_0_738), .C2(n_0_313), + .ZN(n_0_51) + ); + OAI22_X1_LVT i_0_52( + .A1(n_0_223), .A2(n_0_103), .B1(op2[2]), .B2(n_0_51), .ZN(n_0_50) + ); + OAI21_X1_LVT i_0_50( + .A(n_0_49), .B1(op2[1]), .B2(n_0_50), .ZN(n_0_48) + ); + AOI21_X1_LVT i_0_45( + .A(n_0_44), .B1(n_0_561), .B2(n_0_48), .ZN(n_0_43) + ); + NAND3_X1_LVT i_0_43( + .A1(n_0_52), .A2(n_0_42), .A3(n_0_43), .ZN(result[1]) + ); + OAI222_X1_LVT i_0_11( + .A1(n_0_740), .A2(n_0_617), .B1(n_0_703), .B2(n_0_615), .C1(n_0_738), .C2(n_0_290), + .ZN(n_0_10) + ); + OAI22_X1_LVT i_0_10( + .A1(op2[2]), .A2(n_0_10), .B1(n_0_693), .B2(n_0_88), .ZN(n_0_9) + ); + OAI221_X1_LVT i_0_9( + .A(n_0_701), .B1(n_0_728), .B2(n_0_56), .C1(op2[1]), .C2(n_0_9), .ZN(n_0_8) + ); + OAI21_X1_LVT i_0_8( + .A(n_0_8), .B1(n_0_701), .B2(n_0_48), .ZN(n_0_7) + ); + NOR2_X1_LVT i_0_7( + .A1(n_0_579), .A2(n_0_7), .ZN(n_0_6) + ); + OAI221_X1_LVT i_0_3( + .A(op2[0]), .B1(op1[0]), .B2(n_0_564), .C1(n_0_703), .C2(n_0_567), .ZN(n_0_2) + ); + OAI21_X1_LVT i_10_2( + .A(n_10_1), .B1(n_10_0), .B2(op2[0]), .ZN(n_32) + ); + AOI22_X1_LVT i_0_2( + .A1(n_32), .A2(n_0_580), .B1(n_0), .B2(n_0_581), .ZN(n_0_1) + ); + NAND3_X1_LVT i_0_6( + .A1(n_0_701), .A2(n_0_571), .A3(n_0_620), .ZN(n_0_5) + ); + OAI211_X1_LVT i_0_5( + .A(n_0_681), .B(n_0_5), .C1(op2[0]), .C2(n_0_568), .ZN(n_0_4) + ); + NAND2_X1_LVT i_0_4( + .A1(op1[0]), .A2(n_0_4), .ZN(n_0_3) + ); + NAND3_X1_LVT i_0_1( + .A1(n_0_2), .A2(n_0_1), .A3(n_0_3), .ZN(n_0_0) + ); + OAI33_X1_LVT i_0_14( + .A1(n_0_692), .A2(op1[31]), .A3(n_0_683), .B1(op2[31]), .B2(n_0_691), .B3(aluOp[0]), + .ZN(n_0_13) + ); + INV_X1_LVT i_0_741( + .A(op2[29]), .ZN(n_0_708) + ); + NAND2_X1_LVT i_0_685( + .A1(op1[29]), .A2(n_0_708), .ZN(n_0_652) + ); + OAI22_X1_LVT i_0_713( + .A1(n_0_700), .A2(op1[28]), .B1(op1[29]), .B2(n_0_708), .ZN(n_0_680) + ); + NAND2_X1_LVT i_0_694( + .A1(n_0_688), .A2(op2[27]), .ZN(n_0_661) + ); + INV_X1_LVT i_0_742( + .A(op2[26]), .ZN(n_0_709) + ); + OAI22_X1_LVT i_0_712( + .A1(n_0_699), .A2(op2[25]), .B1(n_0_736), .B2(op2[24]), .ZN(n_0_679) + ); + NAND2_X1_LVT i_0_690( + .A1(n_0_727), .A2(op2[20]), .ZN(n_0_657) + ); + INV_X1_LVT i_0_740( + .A(op2[18]), .ZN(n_0_707) + ); + OAI22_X1_LVT i_0_711( + .A1(n_0_707), .A2(op1[18]), .B1(n_0_690), .B2(op1[19]), .ZN(n_0_678) + ); + OAI22_X1_LVT i_0_29( + .A1(n_0_739), .A2(op2[16]), .B1(n_0_734), .B2(op2[15]), .ZN(n_0_28) + ); + INV_X1_LVT i_0_728( + .A(op2[12]), .ZN(n_0_695) + ); + INV_X1_LVT i_0_748( + .A(op2[13]), .ZN(n_0_715) + ); + OAI22_X1_LVT i_0_704( + .A1(n_0_706), .A2(op2[11]), .B1(n_0_696), .B2(op2[12]), .ZN(n_0_671) + ); + AOI22_X1_LVT i_0_710( + .A1(n_0_740), .A2(op2[8]), .B1(n_0_713), .B2(op2[7]), .ZN(n_0_677) + ); + OAI22_X1_LVT i_0_707( + .A1(n_0_731), .A2(op1[5]), .B1(op1[6]), .B2(n_0_702), .ZN(n_0_674) + ); + OAI22_X1_LVT i_0_706( + .A1(op1[2]), .A2(n_0_693), .B1(op1[1]), .B2(n_0_728), .ZN(n_0_673) + ); + INV_X1_LVT i_0_705( + .A(n_0_673), .ZN(n_0_672) + ); + INV_X1_LVT i_0_699( + .A(n_0_667), .ZN(n_0_666) + ); + OAI21_X1_LVT i_0_42( + .A(n_0_672), .B1(n_0_666), .B2(n_0_665), .ZN(n_0_41) + ); + AOI21_X1_LVT i_0_41( + .A(n_0_654), .B1(op1[2]), .B2(n_0_693), .ZN(n_0_40) + ); + AOI211_X1_LVT i_0_40( + .A(n_0_668), .B(n_0_663), .C1(n_0_41), .C2(n_0_40), .ZN(n_0_39) + ); + AOI211_X1_LVT i_0_39( + .A(n_0_656), .B(n_0_39), .C1(n_0_731), .C2(op1[5]), .ZN(n_0_38) + ); + OAI222_X1_LVT i_0_38( + .A1(n_0_704), .A2(op2[6]), .B1(n_0_674), .B2(n_0_38), .C1(n_0_713), .C2(op2[7]), + .ZN(n_0_37) + ); + AOI221_X1_LVT i_0_37( + .A(n_0_655), .B1(op1[9]), .B2(n_0_720), .C1(n_0_677), .C2(n_0_37), .ZN(n_0_36) + ); + INV_X1_LVT i_0_768( + .A(op2[10]), .ZN(n_0_735) + ); + OAI22_X1_LVT i_0_36( + .A1(n_0_735), .A2(op1[10]), .B1(op1[9]), .B2(n_0_720), .ZN(n_0_35) + ); + OAI22_X1_LVT i_0_35( + .A1(op2[10]), .A2(n_0_733), .B1(n_0_36), .B2(n_0_35), .ZN(n_0_34) + ); + INV_X1_LVT i_0_34( + .A(n_0_34), .ZN(n_0_33) + ); + AOI21_X1_LVT i_0_33( + .A(n_0_33), .B1(n_0_706), .B2(op2[11]), .ZN(n_0_32) + ); + OAI222_X1_LVT i_0_32( + .A1(op1[12]), .A2(n_0_695), .B1(n_0_715), .B2(op1[13]), .C1(n_0_671), .C2(n_0_32), + .ZN(n_0_31) + ); + OAI221_X1_LVT i_0_31( + .A(n_0_31), .B1(n_0_721), .B2(op2[14]), .C1(op2[13]), .C2(n_0_714), .ZN(n_0_30) + ); + AOI22_X1_LVT i_0_30( + .A1(n_0_734), .A2(op2[15]), .B1(n_0_721), .B2(op2[14]), .ZN(n_0_29) + ); + AOI21_X1_LVT i_0_28( + .A(n_0_28), .B1(n_0_30), .B2(n_0_29), .ZN(n_0_27) + ); + AOI221_X1_LVT i_0_27( + .A(n_0_27), .B1(n_0_732), .B2(op2[17]), .C1(n_0_739), .C2(op2[16]), .ZN(n_0_26) + ); + AOI211_X1_LVT i_0_26( + .A(n_0_660), .B(n_0_26), .C1(n_0_707), .C2(op1[18]), .ZN(n_0_25) + ); + OAI22_X1_LVT i_0_25( + .A1(op2[19]), .A2(n_0_689), .B1(n_0_678), .B2(n_0_25), .ZN(n_0_24) + ); + AOI211_X1_LVT i_0_24( + .A(n_0_658), .B(n_0_659), .C1(n_0_657), .C2(n_0_24), .ZN(n_0_23) + ); + AOI221_X1_LVT i_0_23( + .A(n_0_23), .B1(n_0_726), .B2(op2[21]), .C1(n_0_687), .C2(op2[22]), .ZN(n_0_22) + ); + AOI221_X1_LVT i_0_22( + .A(n_0_22), .B1(op1[22]), .B2(n_0_686), .C1(op1[23]), .C2(n_0_718), .ZN(n_0_21) + ); + AOI221_X1_LVT i_0_21( + .A(n_0_21), .B1(n_0_736), .B2(op2[24]), .C1(n_0_719), .C2(op2[23]), .ZN(n_0_20) + ); + OAI222_X1_LVT i_0_20( + .A1(op1[26]), .A2(n_0_709), .B1(op1[25]), .B2(n_0_697), .C1(n_0_679), .C2(n_0_20), + .ZN(n_0_19) + ); + OAI221_X1_LVT i_0_19( + .A(n_0_19), .B1(n_0_711), .B2(op2[26]), .C1(n_0_688), .C2(op2[27]), .ZN(n_0_18) + ); + AOI22_X1_LVT i_0_18( + .A1(n_0_700), .A2(op1[28]), .B1(n_0_661), .B2(n_0_18), .ZN(n_0_17) + ); + OAI21_X1_LVT i_0_17( + .A(n_0_652), .B1(n_0_680), .B2(n_0_17), .ZN(n_0_16) + ); + INV_X1_LVT i_0_749( + .A(op2[30]), .ZN(n_0_716) + ); + OAI21_X1_LVT i_0_16( + .A(n_0_16), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_15) + ); + OAI22_X1_LVT i_0_708( + .A1(n_0_692), .A2(op1[31]), .B1(op2[31]), .B2(n_0_691), .ZN(n_0_675) + ); + AOI21_X1_LVT i_0_15( + .A(n_0_675), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_14) + ); + AOI21_X1_LVT i_0_13( + .A(n_0_13), .B1(n_0_15), .B2(n_0_14), .ZN(n_0_12) + ); + NOR4_X1_LVT i_0_12( + .A1(n_0_685), .A2(aluOp[2]), .A3(aluBypass), .A4(n_0_12), .ZN(n_0_11) + ); + OR3_X1_LVT i_0_0( + .A1(n_0_6), .A2(n_0_0), .A3(n_0_11), .ZN(result[0]) + ); + OR4_X1_LVT i_0_703( + .A1(n_0_680), .A2(n_0_673), .A3(n_0_675), .A4(n_0_678), .ZN(n_0_670) + ); + INV_X1_LVT i_0_709( + .A(n_0_677), .ZN(n_0_676) + ); + OR4_X1_LVT i_0_702( + .A1(n_0_679), .A2(n_0_674), .A3(n_0_676), .A4(n_0_671), .ZN(n_0_669) + ); + AOI22_X1_LVT i_0_663( + .A1(n_0_688), .A2(op2[27]), .B1(op1[22]), .B2(n_0_686), .ZN(n_0_630) + ); + OAI22_X1_LVT i_0_662( + .A1(n_0_694), .A2(op2[2]), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_629) + ); + AOI221_X1_LVT i_0_661( + .A(n_0_629), .B1(n_0_711), .B2(op2[26]), .C1(n_0_721), .C2(op2[14]), .ZN(n_0_628) + ); + AOI21_X1_LVT i_0_664( + .A(n_0_660), .B1(n_0_690), .B2(op1[19]), .ZN(n_0_631) + ); + OAI222_X1_LVT i_0_660( + .A1(op1[12]), .A2(n_0_695), .B1(n_0_688), .B2(op2[27]), .C1(op1[22]), .C2(n_0_686), + .ZN(n_0_627) + ); + AOI21_X1_LVT i_0_659( + .A(n_0_663), .B1(n_0_734), .B2(op2[15]), .ZN(n_0_626) + ); + OAI211_X1_LVT i_0_658( + .A(n_0_666), .B(n_0_626), .C1(n_0_715), .C2(op1[13]), .ZN(n_0_625) + ); + AOI211_X1_LVT i_0_657( + .A(n_0_627), .B(n_0_625), .C1(op1[23]), .C2(n_0_718), .ZN(n_0_624) + ); + NAND4_X1_LVT i_0_656( + .A1(n_0_630), .A2(n_0_628), .A3(n_0_631), .A4(n_0_624), .ZN(n_0_623) + ); + OAI22_X1_LVT i_0_684( + .A1(n_0_721), .A2(op2[14]), .B1(n_0_722), .B2(op2[9]), .ZN(n_0_651) + ); + AOI211_X1_LVT i_0_668( + .A(n_0_651), .B(n_0_654), .C1(n_0_719), .C2(op2[23]), .ZN(n_0_635) + ); + NAND2_X1_LVT i_0_667( + .A1(n_0_664), .A2(n_0_657), .ZN(n_0_634) + ); + NOR3_X1_LVT i_0_666( + .A1(n_0_659), .A2(n_0_656), .A3(n_0_634), .ZN(n_0_633) + ); + AOI21_X1_LVT i_0_671( + .A(n_0_655), .B1(n_0_739), .B2(op2[16]), .ZN(n_0_638) + ); + AOI21_X1_LVT i_0_670( + .A(n_0_668), .B1(n_0_736), .B2(op2[24]), .ZN(n_0_637) + ); + OAI22_X1_LVT i_0_673( + .A1(n_0_735), .A2(op1[10]), .B1(n_0_734), .B2(op2[15]), .ZN(n_0_640) + ); + AOI221_X1_LVT i_0_672( + .A(n_0_640), .B1(n_0_732), .B2(op2[17]), .C1(n_0_731), .C2(op1[5]), .ZN(n_0_639) + ); + AND3_X1_LVT i_0_669( + .A1(n_0_638), .A2(n_0_637), .A3(n_0_639), .ZN(n_0_636) + ); + OAI22_X1_LVT i_0_682( + .A1(n_0_703), .A2(op2[0]), .B1(n_0_704), .B2(op2[6]), .ZN(n_0_649) + ); + OAI22_X1_LVT i_0_681( + .A1(op2[28]), .A2(n_0_698), .B1(op1[25]), .B2(n_0_697), .ZN(n_0_648) + ); + AOI21_X1_LVT i_0_678( + .A(n_0_658), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_645) + ); + AOI21_X1_LVT i_0_677( + .A(n_0_662), .B1(n_0_735), .B2(op1[10]), .ZN(n_0_644) + ); + INV_X1_LVT i_0_758( + .A(op2[21]), .ZN(n_0_725) + ); + OAI22_X1_LVT i_0_683( + .A1(op1[21]), .A2(n_0_725), .B1(n_0_739), .B2(op2[16]), .ZN(n_0_650) + ); + AOI221_X1_LVT i_0_676( + .A(n_0_650), .B1(n_0_722), .B2(op2[9]), .C1(op1[7]), .C2(n_0_712), .ZN(n_0_643) + ); + OAI21_X1_LVT i_0_680( + .A(n_0_652), .B1(n_0_711), .B2(op2[26]), .ZN(n_0_647) + ); + AOI221_X1_LVT i_0_679( + .A(n_0_647), .B1(n_0_706), .B2(op2[11]), .C1(n_0_707), .C2(op1[18]), .ZN(n_0_646) + ); + NAND4_X1_LVT i_0_675( + .A1(n_0_645), .A2(n_0_644), .A3(n_0_643), .A4(n_0_646), .ZN(n_0_642) + ); + NOR3_X1_LVT i_0_674( + .A1(n_0_649), .A2(n_0_648), .A3(n_0_642), .ZN(n_0_641) + ); + NAND4_X1_LVT i_0_665( + .A1(n_0_635), .A2(n_0_633), .A3(n_0_636), .A4(n_0_641), .ZN(n_0_632) + ); + NOR4_X1_LVT i_0_655( + .A1(n_0_670), .A2(n_0_669), .A3(n_0_623), .A4(n_0_632), .ZN(eqFlag) + ); +endmodule + +module decoder(CurrentPC, JumpOrBranchPC, JumpOrBranch, DAddr, WData, RData, Instruction, + WrMem, DWidth, Rs1, Rs2, Rd, RRs1, RRs2, WRd, WrReg, Illegal); + input [31:0] CurrentPC, RData, Instruction, RRs1, RRs2; + output [31:0] JumpOrBranchPC, DAddr, WData, WRd; + output [4:0] Rs1, Rs2, Rd; + output [1:0] DWidth; + output JumpOrBranch, WrMem, WrReg, Illegal; + + wire [31:0] op1, op2; + wire [2:0] aluOp; + wire eqFlag, n_5_0, n_5_1, n_5_2, n_5_3, n_5_4, n_5_5, n_5_6, n_5_7, n_5_8, + n_5_9, n_5_10, n_5_11, n_5_12, n_5_13, n_5_14, n_5_15, n_5_16, n_5_17, + n_5_18, n_5_19, n_5_20, n_5_21, n_5_22, n_5_23, n_5_24, n_5_25, n_5_26, + n_5_27, n_5_28, n_5_29, n_5_30, n_5_31, n_5_32, n_5_33, n_17_0, n_17_1, + n_17_2, n_17_3, n_17_4, n_17_5, n_17_6, n_17_7, n_17_8, n_17_9, n_17_10, + n_17_11, n_17_12, n_17_13, n_17_14, n_17_15, n_17_16, n_17_17, n_17_18, + n_17_19, n_17_20, n_17_21, n_17_22, n_17_23, n_17_24, n_17_25, n_17_26, + n_17_27, n_17_28, n_17_29, n_17_30, n_17_31, n_17_32, n_18_0, n_18_1, + n_18_2, n_18_3, n_18_4, n_18_5, n_18_6, n_18_7, n_18_8, n_18_9, n_18_10, + n_18_11, n_18_12, n_18_13, n_18_14, n_18_15, n_18_16, n_18_17, n_18_18, + n_18_19, n_18_20, n_18_21, n_18_22, n_18_23, n_18_24, n_18_25, n_18_26, + n_18_27, n_18_28, n_18_29, n_18_30, n_18_31, n_18_32, n_0_15, n_0_2, + n_0_16, n_0_3, n_0_17, n_0_4, n_0_18, n_0_5, n_0_19, n_0_6, n_0_20, + n_0_7, n_0_21, n_0_8, n_0_22, n_0_9, n_0_23, n_0_10, n_0_24, n_0_11, + n_0_25, n_0_12, n_0_26, n_0_13, n_0_27, n_0_14, n_0_28, n_0_29, n_0_30, + n_0_31, n_0_32, n_0_33, n_0_34, n_0_35, n_0_36, n_0_37, n_0_38, n_0_39, + n_0_40, n_0_41, n_0_42, n_0_43, n_0_44, n_0_45, n_0_46, n_0_47, n_0_48, + n_0_49, n_0_50, n_0_51, n_0_52, n_0_53, n_0_54, n_0_55, n_0_56, n_0_57, + n_0_58, n_0_59, n_0_60, n_0_61, n_0_62, n_0_63, n_0_64, n_0_65, n_0_66, + n_0_67, n_0_68, n_0_69, n_0_70, n_0_71, n_0_72, n_0_73, n_0_74, n_0_75, + n_0_76, n_0_77, n_0_78, n_0_79, n_0_80, n_0_81, n_0_82, n_0_83, n_0_84, + n_0_85, n_0_86, n_0_87, n_0_88, n_0_89, n_0_90, n_0_91, n_0_92, n_0_93, + n_0_94, n_0_95, n_0_96, n_0_97, n_0_98, n_0_99, n_0_100, aluNegAr, + n_0_101, n_0_102, n_0_103, n_0_104, n_0_105, aluBypass, n_0_106, + n_0_107, n_0_108, n_0_109, n_0_110, n_0_111, n_0_112, n_0_113, n_0_114, + n_0_115, n_0_116, n_0_117, n_0_118, n_0_119, n_0_120, n_0_121, n_0_122, + n_0_123, n_0_124, n_0_125, n_0_126, n_0_127, n_0_128, n_0_129, n_0_130, + n_0_131, n_0_132, n_0_133, n_0_134, n_0_135, n_0_136, n_0_137, n_0_138, + n_0_139, n_0_140, n_0_141, n_0_142, n_0_143, n_0_144, n_0_145, n_0_146, + n_0_147, n_0_148, n_0_149, n_0_150, n_0_151, n_0_152, n_0_153, n_0_154, + n_0_155, n_0_156, n_0_157, n_0_158, n_0_159, n_0_160, n_0_161, n_0_162, + n_0_163, n_0_164, n_0_165, n_0_166, n_0_167, n_0_168, n_0_169, n_0_170, + n_0_171, n_0_172, n_0_173, n_0_174, n_0_175, n_0_176, n_0_177, n_0_178, + n_0_179, n_0_180, n_0_181, n_0_182, n_0_183, n_0_184, n_0_185, n_0_186, + n_0_187, n_0_188, n_0_189, n_0_190, n_0_191, n_0_192, n_0_193, n_0_194, + n_0_195, n_0_196, n_0_197, n_0_198, n_0_199, n_0_200, n_0_201, n_0_202, + n_0_203, n_0_204, n_0_205, n_0_206, n_0_207, n_0_208, n_0_209, n_0_210, + n_0_211, n_0_212, n_0_213, n_0_214, n_0_215, n_0_216, n_0_217, n_0_218, + n_0_219, n_0_220, n_0_221, n_0_222, n_0_223, n_0_224, n_0_225, n_0_226, + n_0_227, n_0_228, n_0_229, n_0_230, n_0_231, n_0_232, n_0_233, n_0_234, + n_0_235, n_0_236, n_0_237, n_0_238, n_0_239, n_0_240, n_0_241, n_0_242, + n_0_1, n_0_0, n_0_243, n_0_244, n_0_245, n_0_246, n_0_247, n_0_248, + n_0_249, n_63, n_64, n_65, n_66, n_67, n_68, n_69, n_70, n_71, n_72, + n_73, n_74, n_75, n_76, n_77, n_78, n_79, n_80, n_81, n_82, n_83, n_84, + n_85, n_86, n_87, n_88, n_89, n_90, n_91, n_92, n_93, n_32, n_33, n_34, + n_35, n_36, n_37, n_38, n_39, n_40, n_41, n_42, n_43, n_44, n_45, n_46, + n_47, n_48, n_49, n_50, n_51, n_52, n_53, n_54, n_55, n_56, n_57, n_58, + n_59, n_60, n_61, n_62, n_0, n_1, n_2, n_3, n_4, n_5, n_6, n_7, n_8, + n_9, n_10, n_11, n_12, n_13, n_14, n_15, n_16, n_17, n_18, n_19, n_20, + n_21, n_22, n_23, n_24, n_25, n_26, n_27, n_28, n_29, n_30, n_31; + + INV_X1_LVT i_18_1( + .A(CurrentPC[13]), .ZN(n_18_1) + ); + XNOR2_X1_LVT i_18_32( + .A(CurrentPC[31]), .B(n_18_1), .ZN(n_18_32) + ); + INV_X1_LVT i_18_0( + .A(Instruction[31]), .ZN(n_18_0) + ); + HA_X1_LVT i_18_2( + .A(Instruction[8]), .B(CurrentPC[1]), .CO(n_18_2), .S(n_63) + ); + FA_X1_LVT i_18_3( + .A(Instruction[9]), .B(CurrentPC[2]), .CI(n_18_2), .CO(n_18_3), .S(n_64) + ); + FA_X1_LVT i_18_4( + .A(Instruction[10]), .B(CurrentPC[3]), .CI(n_18_3), .CO(n_18_4), .S(n_65) + ); + FA_X1_LVT i_18_5( + .A(Instruction[11]), .B(CurrentPC[4]), .CI(n_18_4), .CO(n_18_5), .S(n_66) + ); + FA_X1_LVT i_18_6( + .A(Instruction[25]), .B(CurrentPC[5]), .CI(n_18_5), .CO(n_18_6), .S(n_67) + ); + FA_X1_LVT i_18_7( + .A(Instruction[26]), .B(CurrentPC[6]), .CI(n_18_6), .CO(n_18_7), .S(n_68) + ); + FA_X1_LVT i_18_8( + .A(Instruction[27]), .B(CurrentPC[7]), .CI(n_18_7), .CO(n_18_8), .S(n_69) + ); + FA_X1_LVT i_18_9( + .A(Instruction[28]), .B(CurrentPC[8]), .CI(n_18_8), .CO(n_18_9), .S(n_70) + ); + FA_X1_LVT i_18_10( + .A(Instruction[29]), .B(CurrentPC[9]), .CI(n_18_9), .CO(n_18_10), .S(n_71) + ); + FA_X1_LVT i_18_11( + .A(Instruction[30]), .B(CurrentPC[10]), .CI(n_18_10), .CO(n_18_11), .S(n_72) + ); + FA_X1_LVT i_18_12( + .A(Instruction[7]), .B(CurrentPC[11]), .CI(n_18_11), .CO(n_18_12), .S(n_73) + ); + FA_X1_LVT i_18_13( + .A(CurrentPC[12]), .B(Instruction[31]), .CI(n_18_12), .CO(n_18_13), .S(n_74) + ); + FA_X1_LVT i_18_14( + .A(n_18_0), .B(n_18_1), .CI(n_18_13), .CO(n_18_14), .S(n_75) + ); + FA_X1_LVT i_18_15( + .A(CurrentPC[14]), .B(n_18_1), .CI(n_18_14), .CO(n_18_15), .S(n_76) + ); + FA_X1_LVT i_18_16( + .A(CurrentPC[15]), .B(n_18_1), .CI(n_18_15), .CO(n_18_16), .S(n_77) + ); + FA_X1_LVT i_18_17( + .A(CurrentPC[16]), .B(n_18_1), .CI(n_18_16), .CO(n_18_17), .S(n_78) + ); + FA_X1_LVT i_18_18( + .A(CurrentPC[17]), .B(n_18_1), .CI(n_18_17), .CO(n_18_18), .S(n_79) + ); + FA_X1_LVT i_18_19( + .A(CurrentPC[18]), .B(n_18_1), .CI(n_18_18), .CO(n_18_19), .S(n_80) + ); + FA_X1_LVT i_18_20( + .A(CurrentPC[19]), .B(n_18_1), .CI(n_18_19), .CO(n_18_20), .S(n_81) + ); + FA_X1_LVT i_18_21( + .A(CurrentPC[20]), .B(n_18_1), .CI(n_18_20), .CO(n_18_21), .S(n_82) + ); + FA_X1_LVT i_18_22( + .A(CurrentPC[21]), .B(n_18_1), .CI(n_18_21), .CO(n_18_22), .S(n_83) + ); + FA_X1_LVT i_18_23( + .A(CurrentPC[22]), .B(n_18_1), .CI(n_18_22), .CO(n_18_23), .S(n_84) + ); + FA_X1_LVT i_18_24( + .A(CurrentPC[23]), .B(n_18_1), .CI(n_18_23), .CO(n_18_24), .S(n_85) + ); + FA_X1_LVT i_18_25( + .A(CurrentPC[24]), .B(n_18_1), .CI(n_18_24), .CO(n_18_25), .S(n_86) + ); + FA_X1_LVT i_18_26( + .A(CurrentPC[25]), .B(n_18_1), .CI(n_18_25), .CO(n_18_26), .S(n_87) + ); + FA_X1_LVT i_18_27( + .A(CurrentPC[26]), .B(n_18_1), .CI(n_18_26), .CO(n_18_27), .S(n_88) + ); + FA_X1_LVT i_18_28( + .A(CurrentPC[27]), .B(n_18_1), .CI(n_18_27), .CO(n_18_28), .S(n_89) + ); + FA_X1_LVT i_18_29( + .A(CurrentPC[28]), .B(n_18_1), .CI(n_18_28), .CO(n_18_29), .S(n_90) + ); + FA_X1_LVT i_18_30( + .A(CurrentPC[29]), .B(n_18_1), .CI(n_18_29), .CO(n_18_30), .S(n_91) + ); + FA_X1_LVT i_18_31( + .A(CurrentPC[30]), .B(n_18_1), .CI(n_18_30), .CO(n_18_31), .S(n_92) + ); + XNOR2_X1_LVT i_18_33( + .A(n_18_32), .B(n_18_31), .ZN(n_93) + ); + INV_X1_LVT i_0_350( + .A(Instruction[3]), .ZN(n_0_243) + ); + NAND3_X1_LVT i_0_343( + .A1(n_0_243), .A2(Instruction[0]), .A3(Instruction[1]), .ZN(n_0_238) + ); + OR2_X1_LVT i_0_332( + .A1(n_0_238), .A2(Instruction[2]), .ZN(n_0_228) + ); + INV_X1_LVT i_0_351( + .A(Instruction[5]), .ZN(n_0_244) + ); + NOR2_X1_LVT i_0_340( + .A1(n_0_244), .A2(Instruction[4]), .ZN(n_0_235) + ); + NAND2_X1_LVT i_0_329( + .A1(Instruction[6]), .A2(n_0_235), .ZN(n_0_225) + ); + INV_X1_LVT i_0_354( + .A(Instruction[13]), .ZN(n_0_247) + ); + NOR2_X1_LVT i_0_345( + .A1(n_0_247), .A2(Instruction[14]), .ZN(n_0_240) + ); + NOR3_X1_LVT i_0_118( + .A1(n_0_228), .A2(n_0_225), .A3(n_0_240), .ZN(n_0_99) + ); + NAND3_X1_LVT i_0_346( + .A1(Instruction[0]), .A2(Instruction[1]), .A3(Instruction[2]), .ZN(n_0_241) + ); + NOR2_X1_LVT i_0_328( + .A1(n_0_241), .A2(n_0_225), .ZN(n_0_224) + ); + INV_X1_LVT i_0_356( + .A(n_0_224), .ZN(n_0_249) + ); + NOR2_X1_LVT i_0_108( + .A1(n_0_243), .A2(n_0_249), .ZN(n_0_91) + ); + INV_X1_LVT i_17_1( + .A(CurrentPC[21]), .ZN(n_17_1) + ); + XNOR2_X1_LVT i_17_32( + .A(CurrentPC[31]), .B(n_17_1), .ZN(n_17_32) + ); + INV_X1_LVT i_17_0( + .A(Instruction[31]), .ZN(n_17_0) + ); + HA_X1_LVT i_17_2( + .A(Instruction[21]), .B(CurrentPC[1]), .CO(n_17_2), .S(n_32) + ); + FA_X1_LVT i_17_3( + .A(Instruction[22]), .B(CurrentPC[2]), .CI(n_17_2), .CO(n_17_3), .S(n_33) + ); + FA_X1_LVT i_17_4( + .A(Instruction[23]), .B(CurrentPC[3]), .CI(n_17_3), .CO(n_17_4), .S(n_34) + ); + FA_X1_LVT i_17_5( + .A(Instruction[24]), .B(CurrentPC[4]), .CI(n_17_4), .CO(n_17_5), .S(n_35) + ); + FA_X1_LVT i_17_6( + .A(Instruction[25]), .B(CurrentPC[5]), .CI(n_17_5), .CO(n_17_6), .S(n_36) + ); + FA_X1_LVT i_17_7( + .A(Instruction[26]), .B(CurrentPC[6]), .CI(n_17_6), .CO(n_17_7), .S(n_37) + ); + FA_X1_LVT i_17_8( + .A(Instruction[27]), .B(CurrentPC[7]), .CI(n_17_7), .CO(n_17_8), .S(n_38) + ); + FA_X1_LVT i_17_9( + .A(Instruction[28]), .B(CurrentPC[8]), .CI(n_17_8), .CO(n_17_9), .S(n_39) + ); + FA_X1_LVT i_17_10( + .A(Instruction[29]), .B(CurrentPC[9]), .CI(n_17_9), .CO(n_17_10), .S(n_40) + ); + FA_X1_LVT i_17_11( + .A(Instruction[30]), .B(CurrentPC[10]), .CI(n_17_10), .CO(n_17_11), .S(n_41) + ); + FA_X1_LVT i_17_12( + .A(Instruction[20]), .B(CurrentPC[11]), .CI(n_17_11), .CO(n_17_12), .S(n_42) + ); + FA_X1_LVT i_17_13( + .A(Instruction[12]), .B(CurrentPC[12]), .CI(n_17_12), .CO(n_17_13), .S(n_43) + ); + FA_X1_LVT i_17_14( + .A(Instruction[13]), .B(CurrentPC[13]), .CI(n_17_13), .CO(n_17_14), .S(n_44) + ); + FA_X1_LVT i_17_15( + .A(Instruction[14]), .B(CurrentPC[14]), .CI(n_17_14), .CO(n_17_15), .S(n_45) + ); + FA_X1_LVT i_17_16( + .A(Instruction[15]), .B(CurrentPC[15]), .CI(n_17_15), .CO(n_17_16), .S(n_46) + ); + FA_X1_LVT i_17_17( + .A(Instruction[16]), .B(CurrentPC[16]), .CI(n_17_16), .CO(n_17_17), .S(n_47) + ); + FA_X1_LVT i_17_18( + .A(Instruction[17]), .B(CurrentPC[17]), .CI(n_17_17), .CO(n_17_18), .S(n_48) + ); + FA_X1_LVT i_17_19( + .A(Instruction[18]), .B(CurrentPC[18]), .CI(n_17_18), .CO(n_17_19), .S(n_49) + ); + FA_X1_LVT i_17_20( + .A(Instruction[19]), .B(CurrentPC[19]), .CI(n_17_19), .CO(n_17_20), .S(n_50) + ); + FA_X1_LVT i_17_21( + .A(CurrentPC[20]), .B(Instruction[31]), .CI(n_17_20), .CO(n_17_21), .S(n_51) + ); + FA_X1_LVT i_17_22( + .A(n_17_0), .B(n_17_1), .CI(n_17_21), .CO(n_17_22), .S(n_52) + ); + FA_X1_LVT i_17_23( + .A(CurrentPC[22]), .B(n_17_1), .CI(n_17_22), .CO(n_17_23), .S(n_53) + ); + FA_X1_LVT i_17_24( + .A(CurrentPC[23]), .B(n_17_1), .CI(n_17_23), .CO(n_17_24), .S(n_54) + ); + FA_X1_LVT i_17_25( + .A(CurrentPC[24]), .B(n_17_1), .CI(n_17_24), .CO(n_17_25), .S(n_55) + ); + FA_X1_LVT i_17_26( + .A(CurrentPC[25]), .B(n_17_1), .CI(n_17_25), .CO(n_17_26), .S(n_56) + ); + FA_X1_LVT i_17_27( + .A(CurrentPC[26]), .B(n_17_1), .CI(n_17_26), .CO(n_17_27), .S(n_57) + ); + FA_X1_LVT i_17_28( + .A(CurrentPC[27]), .B(n_17_1), .CI(n_17_27), .CO(n_17_28), .S(n_58) + ); + FA_X1_LVT i_17_29( + .A(CurrentPC[28]), .B(n_17_1), .CI(n_17_28), .CO(n_17_29), .S(n_59) + ); + FA_X1_LVT i_17_30( + .A(CurrentPC[29]), .B(n_17_1), .CI(n_17_29), .CO(n_17_30), .S(n_60) + ); + FA_X1_LVT i_17_31( + .A(CurrentPC[30]), .B(n_17_1), .CI(n_17_30), .CO(n_17_31), .S(n_61) + ); + XNOR2_X1_LVT i_17_33( + .A(n_17_32), .B(n_17_31), .ZN(n_62) + ); + INV_X1_LVT i_5_1( + .A(RRs1[12]), .ZN(n_5_1) + ); + XNOR2_X1_LVT i_5_33( + .A(RRs1[31]), .B(n_5_1), .ZN(n_5_33) + ); + INV_X1_LVT i_5_0( + .A(Instruction[31]), .ZN(n_5_0) + ); + HA_X1_LVT i_5_2( + .A(Instruction[20]), .B(RRs1[0]), .CO(n_5_2), .S(n_0) + ); + FA_X1_LVT i_5_3( + .A(Instruction[21]), .B(RRs1[1]), .CI(n_5_2), .CO(n_5_3), .S(n_1) + ); + FA_X1_LVT i_5_4( + .A(Instruction[22]), .B(RRs1[2]), .CI(n_5_3), .CO(n_5_4), .S(n_2) + ); + FA_X1_LVT i_5_5( + .A(Instruction[23]), .B(RRs1[3]), .CI(n_5_4), .CO(n_5_5), .S(n_3) + ); + FA_X1_LVT i_5_6( + .A(Instruction[24]), .B(RRs1[4]), .CI(n_5_5), .CO(n_5_6), .S(n_4) + ); + FA_X1_LVT i_5_7( + .A(Instruction[25]), .B(RRs1[5]), .CI(n_5_6), .CO(n_5_7), .S(n_5) + ); + FA_X1_LVT i_5_8( + .A(Instruction[26]), .B(RRs1[6]), .CI(n_5_7), .CO(n_5_8), .S(n_6) + ); + FA_X1_LVT i_5_9( + .A(Instruction[27]), .B(RRs1[7]), .CI(n_5_8), .CO(n_5_9), .S(n_7) + ); + FA_X1_LVT i_5_10( + .A(Instruction[28]), .B(RRs1[8]), .CI(n_5_9), .CO(n_5_10), .S(n_8) + ); + FA_X1_LVT i_5_11( + .A(Instruction[29]), .B(RRs1[9]), .CI(n_5_10), .CO(n_5_11), .S(n_9) + ); + FA_X1_LVT i_5_12( + .A(Instruction[30]), .B(RRs1[10]), .CI(n_5_11), .CO(n_5_12), .S(n_10) + ); + FA_X1_LVT i_5_13( + .A(RRs1[11]), .B(Instruction[31]), .CI(n_5_12), .CO(n_5_13), .S(n_11) + ); + FA_X1_LVT i_5_14( + .A(n_5_0), .B(n_5_1), .CI(n_5_13), .CO(n_5_14), .S(n_12) + ); + FA_X1_LVT i_5_15( + .A(RRs1[13]), .B(n_5_1), .CI(n_5_14), .CO(n_5_15), .S(n_13) + ); + FA_X1_LVT i_5_16( + .A(RRs1[14]), .B(n_5_1), .CI(n_5_15), .CO(n_5_16), .S(n_14) + ); + FA_X1_LVT i_5_17( + .A(RRs1[15]), .B(n_5_1), .CI(n_5_16), .CO(n_5_17), .S(n_15) + ); + FA_X1_LVT i_5_18( + .A(RRs1[16]), .B(n_5_1), .CI(n_5_17), .CO(n_5_18), .S(n_16) + ); + FA_X1_LVT i_5_19( + .A(RRs1[17]), .B(n_5_1), .CI(n_5_18), .CO(n_5_19), .S(n_17) + ); + FA_X1_LVT i_5_20( + .A(RRs1[18]), .B(n_5_1), .CI(n_5_19), .CO(n_5_20), .S(n_18) + ); + FA_X1_LVT i_5_21( + .A(RRs1[19]), .B(n_5_1), .CI(n_5_20), .CO(n_5_21), .S(n_19) + ); + FA_X1_LVT i_5_22( + .A(RRs1[20]), .B(n_5_1), .CI(n_5_21), .CO(n_5_22), .S(n_20) + ); + FA_X1_LVT i_5_23( + .A(RRs1[21]), .B(n_5_1), .CI(n_5_22), .CO(n_5_23), .S(n_21) + ); + FA_X1_LVT i_5_24( + .A(RRs1[22]), .B(n_5_1), .CI(n_5_23), .CO(n_5_24), .S(n_22) + ); + FA_X1_LVT i_5_25( + .A(RRs1[23]), .B(n_5_1), .CI(n_5_24), .CO(n_5_25), .S(n_23) + ); + FA_X1_LVT i_5_26( + .A(RRs1[24]), .B(n_5_1), .CI(n_5_25), .CO(n_5_26), .S(n_24) + ); + FA_X1_LVT i_5_27( + .A(RRs1[25]), .B(n_5_1), .CI(n_5_26), .CO(n_5_27), .S(n_25) + ); + FA_X1_LVT i_5_28( + .A(RRs1[26]), .B(n_5_1), .CI(n_5_27), .CO(n_5_28), .S(n_26) + ); + FA_X1_LVT i_5_29( + .A(RRs1[27]), .B(n_5_1), .CI(n_5_28), .CO(n_5_29), .S(n_27) + ); + FA_X1_LVT i_5_30( + .A(RRs1[28]), .B(n_5_1), .CI(n_5_29), .CO(n_5_30), .S(n_28) + ); + FA_X1_LVT i_5_31( + .A(RRs1[29]), .B(n_5_1), .CI(n_5_30), .CO(n_5_31), .S(n_29) + ); + FA_X1_LVT i_5_32( + .A(RRs1[30]), .B(n_5_1), .CI(n_5_31), .CO(n_5_32), .S(n_30) + ); + XNOR2_X1_LVT i_5_34( + .A(n_5_33), .B(n_5_32), .ZN(n_31) + ); + NOR2_X1_LVT i_0_107( + .A1(n_0_249), .A2(Instruction[3]), .ZN(n_0_90) + ); + AOI222_X1_LVT i_0_106( + .A1(n_93), .A2(n_0_99), .B1(n_0_91), .B2(n_62), .C1(n_31), .C2(n_0_90), .ZN(n_0_89) + ); + INV_X1_LVT i_0_355( + .A(Instruction[6]), .ZN(n_0_248) + ); + NAND2_X1_LVT i_0_339( + .A1(n_0_248), .A2(Instruction[4]), .ZN(n_0_234) + ); + INV_X1_LVT i_0_338( + .A(n_0_234), .ZN(n_0_233) + ); + OAI21_X1_LVT i_0_341( + .A(Instruction[13]), .B1(Instruction[14]), .B2(Instruction[12]), .ZN(n_0_236) + ); + AOI211_X1_LVT i_0_337( + .A(n_0_235), .B(n_0_233), .C1(n_0_248), .C2(n_0_236), .ZN(n_0_232) + ); + INV_X1_LVT i_0_352( + .A(Instruction[4]), .ZN(n_0_245) + ); + NAND2_X1_LVT i_0_344( + .A1(n_0_245), .A2(Instruction[2]), .ZN(n_0_239) + ); + AOI21_X1_LVT i_0_335( + .A(Instruction[6]), .B1(n_0_243), .B2(n_0_239), .ZN(n_0_230) + ); + NOR2_X1_LVT i_0_334( + .A1(n_0_232), .A2(n_0_230), .ZN(n_0_229) + ); + NAND2_X1_LVT i_0_342( + .A1(n_0_241), .A2(n_0_238), .ZN(n_0_237) + ); + NAND2_X1_LVT i_0_336( + .A1(Instruction[6]), .A2(n_0_240), .ZN(n_0_231) + ); + OAI211_X1_LVT i_0_333( + .A(n_0_229), .B(n_0_237), .C1(Instruction[2]), .C2(n_0_231), .ZN(Illegal) + ); + NAND2_X1_LVT i_0_109( + .A1(Illegal), .A2(CurrentPC[31]), .ZN(n_0_92) + ); + NAND2_X1_LVT i_0_105( + .A1(n_0_89), .A2(n_0_92), .ZN(JumpOrBranchPC[31]) + ); + AOI222_X1_LVT i_0_103( + .A1(n_92), .A2(n_0_99), .B1(n_0_91), .B2(n_61), .C1(n_30), .C2(n_0_90), .ZN(n_0_87) + ); + NAND2_X1_LVT i_0_104( + .A1(Illegal), .A2(CurrentPC[30]), .ZN(n_0_88) + ); + NAND2_X1_LVT i_0_102( + .A1(n_0_87), .A2(n_0_88), .ZN(JumpOrBranchPC[30]) + ); + AOI222_X1_LVT i_0_100( + .A1(n_91), .A2(n_0_99), .B1(n_0_91), .B2(n_60), .C1(n_29), .C2(n_0_90), .ZN(n_0_85) + ); + NAND2_X1_LVT i_0_101( + .A1(Illegal), .A2(CurrentPC[29]), .ZN(n_0_86) + ); + NAND2_X1_LVT i_0_99( + .A1(n_0_85), .A2(n_0_86), .ZN(JumpOrBranchPC[29]) + ); + AOI222_X1_LVT i_0_97( + .A1(n_90), .A2(n_0_99), .B1(n_0_91), .B2(n_59), .C1(n_28), .C2(n_0_90), .ZN(n_0_83) + ); + NAND2_X1_LVT i_0_98( + .A1(Illegal), .A2(CurrentPC[28]), .ZN(n_0_84) + ); + NAND2_X1_LVT i_0_96( + .A1(n_0_83), .A2(n_0_84), .ZN(JumpOrBranchPC[28]) + ); + AOI222_X1_LVT i_0_94( + .A1(n_89), .A2(n_0_99), .B1(n_0_91), .B2(n_58), .C1(n_27), .C2(n_0_90), .ZN(n_0_81) + ); + NAND2_X1_LVT i_0_95( + .A1(Illegal), .A2(CurrentPC[27]), .ZN(n_0_82) + ); + NAND2_X1_LVT i_0_93( + .A1(n_0_81), .A2(n_0_82), .ZN(JumpOrBranchPC[27]) + ); + AOI222_X1_LVT i_0_91( + .A1(n_88), .A2(n_0_99), .B1(n_0_91), .B2(n_57), .C1(n_26), .C2(n_0_90), .ZN(n_0_79) + ); + NAND2_X1_LVT i_0_92( + .A1(Illegal), .A2(CurrentPC[26]), .ZN(n_0_80) + ); + NAND2_X1_LVT i_0_90( + .A1(n_0_79), .A2(n_0_80), .ZN(JumpOrBranchPC[26]) + ); + AOI222_X1_LVT i_0_88( + .A1(n_87), .A2(n_0_99), .B1(n_0_91), .B2(n_56), .C1(n_25), .C2(n_0_90), .ZN(n_0_77) + ); + NAND2_X1_LVT i_0_89( + .A1(Illegal), .A2(CurrentPC[25]), .ZN(n_0_78) + ); + NAND2_X1_LVT i_0_87( + .A1(n_0_77), .A2(n_0_78), .ZN(JumpOrBranchPC[25]) + ); + AOI222_X1_LVT i_0_85( + .A1(n_86), .A2(n_0_99), .B1(n_0_91), .B2(n_55), .C1(n_24), .C2(n_0_90), .ZN(n_0_75) + ); + NAND2_X1_LVT i_0_86( + .A1(Illegal), .A2(CurrentPC[24]), .ZN(n_0_76) + ); + NAND2_X1_LVT i_0_84( + .A1(n_0_75), .A2(n_0_76), .ZN(JumpOrBranchPC[24]) + ); + AOI222_X1_LVT i_0_82( + .A1(n_85), .A2(n_0_99), .B1(n_0_91), .B2(n_54), .C1(n_23), .C2(n_0_90), .ZN(n_0_73) + ); + NAND2_X1_LVT i_0_83( + .A1(Illegal), .A2(CurrentPC[23]), .ZN(n_0_74) + ); + NAND2_X1_LVT i_0_81( + .A1(n_0_73), .A2(n_0_74), .ZN(JumpOrBranchPC[23]) + ); + AOI222_X1_LVT i_0_79( + .A1(n_84), .A2(n_0_99), .B1(n_0_91), .B2(n_53), .C1(n_22), .C2(n_0_90), .ZN(n_0_71) + ); + NAND2_X1_LVT i_0_80( + .A1(Illegal), .A2(CurrentPC[22]), .ZN(n_0_72) + ); + NAND2_X1_LVT i_0_78( + .A1(n_0_71), .A2(n_0_72), .ZN(JumpOrBranchPC[22]) + ); + AOI222_X1_LVT i_0_76( + .A1(n_83), .A2(n_0_99), .B1(n_0_91), .B2(n_52), .C1(n_21), .C2(n_0_90), .ZN(n_0_69) + ); + NAND2_X1_LVT i_0_77( + .A1(Illegal), .A2(CurrentPC[21]), .ZN(n_0_70) + ); + NAND2_X1_LVT i_0_75( + .A1(n_0_69), .A2(n_0_70), .ZN(JumpOrBranchPC[21]) + ); + AOI222_X1_LVT i_0_73( + .A1(n_82), .A2(n_0_99), .B1(n_0_91), .B2(n_51), .C1(n_20), .C2(n_0_90), .ZN(n_0_67) + ); + NAND2_X1_LVT i_0_74( + .A1(Illegal), .A2(CurrentPC[20]), .ZN(n_0_68) + ); + NAND2_X1_LVT i_0_72( + .A1(n_0_67), .A2(n_0_68), .ZN(JumpOrBranchPC[20]) + ); + AOI222_X1_LVT i_0_70( + .A1(n_81), .A2(n_0_99), .B1(n_0_91), .B2(n_50), .C1(n_19), .C2(n_0_90), .ZN(n_0_65) + ); + NAND2_X1_LVT i_0_71( + .A1(Illegal), .A2(CurrentPC[19]), .ZN(n_0_66) + ); + NAND2_X1_LVT i_0_69( + .A1(n_0_65), .A2(n_0_66), .ZN(JumpOrBranchPC[19]) + ); + AOI222_X1_LVT i_0_67( + .A1(n_80), .A2(n_0_99), .B1(n_0_91), .B2(n_49), .C1(n_18), .C2(n_0_90), .ZN(n_0_63) + ); + NAND2_X1_LVT i_0_68( + .A1(Illegal), .A2(CurrentPC[18]), .ZN(n_0_64) + ); + NAND2_X1_LVT i_0_66( + .A1(n_0_63), .A2(n_0_64), .ZN(JumpOrBranchPC[18]) + ); + AOI222_X1_LVT i_0_64( + .A1(n_79), .A2(n_0_99), .B1(n_0_91), .B2(n_48), .C1(n_17), .C2(n_0_90), .ZN(n_0_61) + ); + NAND2_X1_LVT i_0_65( + .A1(Illegal), .A2(CurrentPC[17]), .ZN(n_0_62) + ); + NAND2_X1_LVT i_0_63( + .A1(n_0_61), .A2(n_0_62), .ZN(JumpOrBranchPC[17]) + ); + AOI222_X1_LVT i_0_61( + .A1(n_78), .A2(n_0_99), .B1(n_0_91), .B2(n_47), .C1(n_16), .C2(n_0_90), .ZN(n_0_59) + ); + NAND2_X1_LVT i_0_62( + .A1(Illegal), .A2(CurrentPC[16]), .ZN(n_0_60) + ); + NAND2_X1_LVT i_0_60( + .A1(n_0_59), .A2(n_0_60), .ZN(JumpOrBranchPC[16]) + ); + AOI222_X1_LVT i_0_58( + .A1(n_77), .A2(n_0_99), .B1(n_0_91), .B2(n_46), .C1(n_15), .C2(n_0_90), .ZN(n_0_57) + ); + NAND2_X1_LVT i_0_59( + .A1(Illegal), .A2(CurrentPC[15]), .ZN(n_0_58) + ); + NAND2_X1_LVT i_0_57( + .A1(n_0_57), .A2(n_0_58), .ZN(JumpOrBranchPC[15]) + ); + AOI222_X1_LVT i_0_55( + .A1(n_76), .A2(n_0_99), .B1(n_0_91), .B2(n_45), .C1(n_14), .C2(n_0_90), .ZN(n_0_55) + ); + NAND2_X1_LVT i_0_56( + .A1(Illegal), .A2(CurrentPC[14]), .ZN(n_0_56) + ); + NAND2_X1_LVT i_0_54( + .A1(n_0_55), .A2(n_0_56), .ZN(JumpOrBranchPC[14]) + ); + AOI222_X1_LVT i_0_52( + .A1(n_75), .A2(n_0_99), .B1(n_0_91), .B2(n_44), .C1(n_13), .C2(n_0_90), .ZN(n_0_53) + ); + NAND2_X1_LVT i_0_53( + .A1(Illegal), .A2(CurrentPC[13]), .ZN(n_0_54) + ); + NAND2_X1_LVT i_0_51( + .A1(n_0_53), .A2(n_0_54), .ZN(JumpOrBranchPC[13]) + ); + AOI222_X1_LVT i_0_49( + .A1(n_74), .A2(n_0_99), .B1(n_0_91), .B2(n_43), .C1(n_12), .C2(n_0_90), .ZN(n_0_51) + ); + NAND2_X1_LVT i_0_50( + .A1(Illegal), .A2(CurrentPC[12]), .ZN(n_0_52) + ); + NAND2_X1_LVT i_0_48( + .A1(n_0_51), .A2(n_0_52), .ZN(JumpOrBranchPC[12]) + ); + AOI222_X1_LVT i_0_46( + .A1(n_73), .A2(n_0_99), .B1(n_0_91), .B2(n_42), .C1(n_11), .C2(n_0_90), .ZN(n_0_49) + ); + NAND2_X1_LVT i_0_47( + .A1(Illegal), .A2(CurrentPC[11]), .ZN(n_0_50) + ); + NAND2_X1_LVT i_0_45( + .A1(n_0_49), .A2(n_0_50), .ZN(JumpOrBranchPC[11]) + ); + AOI222_X1_LVT i_0_43( + .A1(n_72), .A2(n_0_99), .B1(n_0_91), .B2(n_41), .C1(n_10), .C2(n_0_90), .ZN(n_0_47) + ); + NAND2_X1_LVT i_0_44( + .A1(Illegal), .A2(CurrentPC[10]), .ZN(n_0_48) + ); + NAND2_X1_LVT i_0_42( + .A1(n_0_47), .A2(n_0_48), .ZN(JumpOrBranchPC[10]) + ); + AOI222_X1_LVT i_0_40( + .A1(n_71), .A2(n_0_99), .B1(n_0_91), .B2(n_40), .C1(n_9), .C2(n_0_90), .ZN(n_0_45) + ); + NAND2_X1_LVT i_0_41( + .A1(Illegal), .A2(CurrentPC[9]), .ZN(n_0_46) + ); + NAND2_X1_LVT i_0_39( + .A1(n_0_45), .A2(n_0_46), .ZN(JumpOrBranchPC[9]) + ); + AOI222_X1_LVT i_0_37( + .A1(n_70), .A2(n_0_99), .B1(n_0_91), .B2(n_39), .C1(n_8), .C2(n_0_90), .ZN(n_0_43) + ); + NAND2_X1_LVT i_0_38( + .A1(Illegal), .A2(CurrentPC[8]), .ZN(n_0_44) + ); + NAND2_X1_LVT i_0_36( + .A1(n_0_43), .A2(n_0_44), .ZN(JumpOrBranchPC[8]) + ); + AOI222_X1_LVT i_0_34( + .A1(n_69), .A2(n_0_99), .B1(n_0_91), .B2(n_38), .C1(n_7), .C2(n_0_90), .ZN(n_0_41) + ); + NAND2_X1_LVT i_0_35( + .A1(Illegal), .A2(CurrentPC[7]), .ZN(n_0_42) + ); + NAND2_X1_LVT i_0_33( + .A1(n_0_41), .A2(n_0_42), .ZN(JumpOrBranchPC[7]) + ); + AOI222_X1_LVT i_0_31( + .A1(n_68), .A2(n_0_99), .B1(n_0_91), .B2(n_37), .C1(n_6), .C2(n_0_90), .ZN(n_0_39) + ); + NAND2_X1_LVT i_0_32( + .A1(Illegal), .A2(CurrentPC[6]), .ZN(n_0_40) + ); + NAND2_X1_LVT i_0_30( + .A1(n_0_39), .A2(n_0_40), .ZN(JumpOrBranchPC[6]) + ); + AOI222_X1_LVT i_0_28( + .A1(n_67), .A2(n_0_99), .B1(n_0_91), .B2(n_36), .C1(n_5), .C2(n_0_90), .ZN(n_0_37) + ); + NAND2_X1_LVT i_0_29( + .A1(Illegal), .A2(CurrentPC[5]), .ZN(n_0_38) + ); + NAND2_X1_LVT i_0_27( + .A1(n_0_37), .A2(n_0_38), .ZN(JumpOrBranchPC[5]) + ); + AOI222_X1_LVT i_0_25( + .A1(n_66), .A2(n_0_99), .B1(n_0_91), .B2(n_35), .C1(n_4), .C2(n_0_90), .ZN(n_0_35) + ); + NAND2_X1_LVT i_0_26( + .A1(Illegal), .A2(CurrentPC[4]), .ZN(n_0_36) + ); + NAND2_X1_LVT i_0_24( + .A1(n_0_35), .A2(n_0_36), .ZN(JumpOrBranchPC[4]) + ); + AOI222_X1_LVT i_0_22( + .A1(n_65), .A2(n_0_99), .B1(n_0_91), .B2(n_34), .C1(n_3), .C2(n_0_90), .ZN(n_0_33) + ); + NAND2_X1_LVT i_0_23( + .A1(Illegal), .A2(CurrentPC[3]), .ZN(n_0_34) + ); + NAND2_X1_LVT i_0_21( + .A1(n_0_33), .A2(n_0_34), .ZN(JumpOrBranchPC[3]) + ); + AOI222_X1_LVT i_0_19( + .A1(n_64), .A2(n_0_99), .B1(n_0_91), .B2(n_33), .C1(n_2), .C2(n_0_90), .ZN(n_0_31) + ); + NAND2_X1_LVT i_0_20( + .A1(Illegal), .A2(CurrentPC[2]), .ZN(n_0_32) + ); + NAND2_X1_LVT i_0_18( + .A1(n_0_31), .A2(n_0_32), .ZN(JumpOrBranchPC[2]) + ); + AOI222_X1_LVT i_0_16( + .A1(n_63), .A2(n_0_99), .B1(n_0_91), .B2(n_32), .C1(n_1), .C2(n_0_90), .ZN(n_0_29) + ); + NAND2_X1_LVT i_0_17( + .A1(Illegal), .A2(CurrentPC[1]), .ZN(n_0_30) + ); + NAND2_X1_LVT i_0_15( + .A1(n_0_29), .A2(n_0_30), .ZN(JumpOrBranchPC[1]) + ); + NOR2_X1_LVT i_0_112( + .A1(n_0_232), .A2(n_0_238), .ZN(n_0_94) + ); + OAI221_X1_LVT i_0_14( + .A(n_0_94), .B1(n_0_225), .B2(Instruction[2]), .C1(Instruction[6]), .C2(n_0_239), + .ZN(n_0_28) + ); + AND2_X1_LVT i_0_13( + .A1(n_0_28), .A2(CurrentPC[0]), .ZN(JumpOrBranchPC[0]) + ); + NOR2_X1_LVT i_0_221( + .A1(Instruction[13]), .A2(Instruction[14]), .ZN(n_0_166) + ); + NOR3_X1_LVT i_0_293( + .A1(n_0_241), .A2(n_0_234), .A3(Instruction[3]), .ZN(n_0_206) + ); + AND2_X1_LVT i_0_292( + .A1(n_0_206), .A2(n_0_244), .ZN(n_0_205) + ); + NOR3_X1_LVT i_0_330( + .A1(n_0_248), .A2(n_0_244), .A3(Instruction[4]), .ZN(n_0_226) + ); + AOI21_X1_LVT i_0_121( + .A(n_0_205), .B1(n_0_226), .B2(n_0_237), .ZN(n_0_100) + ); + AND2_X1_LVT i_0_120( + .A1(Instruction[14]), .A2(n_0_100), .ZN(aluOp[2]) + ); + OAI33_X1_LVT i_0_119( + .A1(n_0_205), .A2(n_0_247), .A3(n_0_224), .B1(Instruction[2]), .B2(n_0_238), + .B3(n_0_225), .ZN(aluOp[1]) + ); + AOI22_X1_LVT i_0_117( + .A1(Instruction[12]), .A2(n_0_100), .B1(n_0_99), .B2(Instruction[13]), .ZN(n_0_98) + ); + INV_X1_LVT i_0_116( + .A(n_0_98), .ZN(aluOp[0]) + ); + OR2_X1_LVT i_0_327( + .A1(n_0_238), .A2(n_0_234), .ZN(n_0_223) + ); + NOR4_X1_LVT i_0_125( + .A1(Instruction[28]), .A2(Instruction[27]), .A3(Instruction[26]), .A4(Instruction[25]), + .ZN(n_0_103) + ); + INV_X1_LVT i_0_347( + .A(Instruction[30]), .ZN(n_0_242) + ); + NOR4_X1_LVT i_0_124( + .A1(Instruction[13]), .A2(n_0_242), .A3(Instruction[29]), .A4(Instruction[31]), + .ZN(n_0_102) + ); + NAND2_X1_LVT i_0_123( + .A1(n_0_103), .A2(n_0_102), .ZN(n_0_101) + ); + NOR3_X1_LVT i_0_127( + .A1(n_0_244), .A2(Instruction[12]), .A3(Instruction[14]), .ZN(n_0_105) + ); + AOI21_X1_LVT i_0_126( + .A(n_0_105), .B1(Instruction[12]), .B2(Instruction[14]), .ZN(n_0_104) + ); + NOR4_X1_LVT i_0_122( + .A1(n_0_223), .A2(n_0_101), .A3(n_0_104), .A4(Instruction[2]), .ZN(aluNegAr) + ); + OR3_X1_LVT i_0_325( + .A1(n_0_228), .A2(Instruction[4]), .A3(Instruction[6]), .ZN(n_0_222) + ); + NOR2_X1_LVT i_0_321( + .A1(n_0_222), .A2(Instruction[5]), .ZN(n_0_221) + ); + NOR3_X1_LVT i_0_224( + .A1(n_0_224), .A2(n_0_221), .A3(n_0_206), .ZN(n_0_169) + ); + NOR3_X1_LVT i_0_129( + .A1(n_0_234), .A2(Instruction[3]), .A3(Instruction[5]), .ZN(n_0_106) + ); + NOR3_X1_LVT i_0_128( + .A1(n_0_226), .A2(n_0_169), .A3(n_0_106), .ZN(aluBypass) + ); + AOI22_X1_LVT i_0_223( + .A1(CurrentPC[31]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[31]), .ZN(n_0_168) + ); + NOR3_X1_LVT i_0_219( + .A1(n_0_247), .A2(n_0_222), .A3(Instruction[5]), .ZN(n_0_164) + ); + AOI22_X1_LVT i_0_218( + .A1(RRs1[31]), .A2(n_0_169), .B1(n_0_164), .B2(RData[31]), .ZN(n_0_163) + ); + MUX2_X1_LVT i_0_222( + .A(RData[7]), .B(RData[15]), .S(Instruction[12]), .Z(n_0_167) + ); + NAND3_X1_LVT i_0_220( + .A1(n_0_221), .A2(n_0_167), .A3(n_0_166), .ZN(n_0_165) + ); + NAND3_X1_LVT i_0_217( + .A1(n_0_168), .A2(n_0_163), .A3(n_0_165), .ZN(op1[31]) + ); + AOI22_X1_LVT i_0_216( + .A1(RRs1[30]), .A2(n_0_169), .B1(n_0_164), .B2(RData[30]), .ZN(n_0_162) + ); + AOI22_X1_LVT i_0_215( + .A1(CurrentPC[30]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[30]), .ZN(n_0_161) + ); + NAND3_X1_LVT i_0_214( + .A1(n_0_162), .A2(n_0_161), .A3(n_0_165), .ZN(op1[30]) + ); + AOI22_X1_LVT i_0_213( + .A1(RRs1[29]), .A2(n_0_169), .B1(n_0_164), .B2(RData[29]), .ZN(n_0_160) + ); + AOI22_X1_LVT i_0_212( + .A1(CurrentPC[29]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[29]), .ZN(n_0_159) + ); + NAND3_X1_LVT i_0_211( + .A1(n_0_160), .A2(n_0_159), .A3(n_0_165), .ZN(op1[29]) + ); + AOI22_X1_LVT i_0_210( + .A1(RRs1[28]), .A2(n_0_169), .B1(n_0_164), .B2(RData[28]), .ZN(n_0_158) + ); + AOI22_X1_LVT i_0_209( + .A1(CurrentPC[28]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[28]), .ZN(n_0_157) + ); + NAND3_X1_LVT i_0_208( + .A1(n_0_158), .A2(n_0_157), .A3(n_0_165), .ZN(op1[28]) + ); + AOI22_X1_LVT i_0_207( + .A1(RRs1[27]), .A2(n_0_169), .B1(n_0_164), .B2(RData[27]), .ZN(n_0_156) + ); + AOI22_X1_LVT i_0_206( + .A1(CurrentPC[27]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[27]), .ZN(n_0_155) + ); + NAND3_X1_LVT i_0_205( + .A1(n_0_156), .A2(n_0_155), .A3(n_0_165), .ZN(op1[27]) + ); + AOI22_X1_LVT i_0_204( + .A1(RRs1[26]), .A2(n_0_169), .B1(n_0_164), .B2(RData[26]), .ZN(n_0_154) + ); + AOI22_X1_LVT i_0_203( + .A1(CurrentPC[26]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[26]), .ZN(n_0_153) + ); + NAND3_X1_LVT i_0_202( + .A1(n_0_154), .A2(n_0_153), .A3(n_0_165), .ZN(op1[26]) + ); + AOI22_X1_LVT i_0_201( + .A1(RRs1[25]), .A2(n_0_169), .B1(n_0_164), .B2(RData[25]), .ZN(n_0_152) + ); + AOI22_X1_LVT i_0_200( + .A1(CurrentPC[25]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[25]), .ZN(n_0_151) + ); + NAND3_X1_LVT i_0_199( + .A1(n_0_152), .A2(n_0_151), .A3(n_0_165), .ZN(op1[25]) + ); + AOI22_X1_LVT i_0_198( + .A1(RRs1[24]), .A2(n_0_169), .B1(n_0_164), .B2(RData[24]), .ZN(n_0_150) + ); + AOI22_X1_LVT i_0_197( + .A1(CurrentPC[24]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[24]), .ZN(n_0_149) + ); + NAND3_X1_LVT i_0_196( + .A1(n_0_150), .A2(n_0_149), .A3(n_0_165), .ZN(op1[24]) + ); + AOI22_X1_LVT i_0_195( + .A1(RRs1[23]), .A2(n_0_169), .B1(n_0_164), .B2(RData[23]), .ZN(n_0_148) + ); + AOI22_X1_LVT i_0_194( + .A1(CurrentPC[23]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[23]), .ZN(n_0_147) + ); + NAND3_X1_LVT i_0_193( + .A1(n_0_148), .A2(n_0_147), .A3(n_0_165), .ZN(op1[23]) + ); + AOI22_X1_LVT i_0_192( + .A1(RRs1[22]), .A2(n_0_169), .B1(n_0_164), .B2(RData[22]), .ZN(n_0_146) + ); + AOI22_X1_LVT i_0_191( + .A1(CurrentPC[22]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[22]), .ZN(n_0_145) + ); + NAND3_X1_LVT i_0_190( + .A1(n_0_146), .A2(n_0_145), .A3(n_0_165), .ZN(op1[22]) + ); + AOI22_X1_LVT i_0_189( + .A1(RRs1[21]), .A2(n_0_169), .B1(n_0_164), .B2(RData[21]), .ZN(n_0_144) + ); + AOI22_X1_LVT i_0_188( + .A1(CurrentPC[21]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[21]), .ZN(n_0_143) + ); + NAND3_X1_LVT i_0_187( + .A1(n_0_144), .A2(n_0_143), .A3(n_0_165), .ZN(op1[21]) + ); + AOI22_X1_LVT i_0_186( + .A1(RRs1[20]), .A2(n_0_169), .B1(n_0_164), .B2(RData[20]), .ZN(n_0_142) + ); + AOI22_X1_LVT i_0_185( + .A1(CurrentPC[20]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[20]), .ZN(n_0_141) + ); + NAND3_X1_LVT i_0_184( + .A1(n_0_142), .A2(n_0_141), .A3(n_0_165), .ZN(op1[20]) + ); + AOI22_X1_LVT i_0_183( + .A1(RRs1[19]), .A2(n_0_169), .B1(n_0_164), .B2(RData[19]), .ZN(n_0_140) + ); + AOI22_X1_LVT i_0_182( + .A1(CurrentPC[19]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[19]), .ZN(n_0_139) + ); + NAND3_X1_LVT i_0_181( + .A1(n_0_140), .A2(n_0_139), .A3(n_0_165), .ZN(op1[19]) + ); + AOI22_X1_LVT i_0_180( + .A1(RRs1[18]), .A2(n_0_169), .B1(n_0_164), .B2(RData[18]), .ZN(n_0_138) + ); + AOI22_X1_LVT i_0_179( + .A1(CurrentPC[18]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[18]), .ZN(n_0_137) + ); + NAND3_X1_LVT i_0_178( + .A1(n_0_138), .A2(n_0_137), .A3(n_0_165), .ZN(op1[18]) + ); + AOI22_X1_LVT i_0_177( + .A1(RRs1[17]), .A2(n_0_169), .B1(n_0_164), .B2(RData[17]), .ZN(n_0_136) + ); + AOI22_X1_LVT i_0_176( + .A1(CurrentPC[17]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[17]), .ZN(n_0_135) + ); + NAND3_X1_LVT i_0_175( + .A1(n_0_136), .A2(n_0_135), .A3(n_0_165), .ZN(op1[17]) + ); + AOI22_X1_LVT i_0_174( + .A1(RRs1[16]), .A2(n_0_169), .B1(n_0_164), .B2(RData[16]), .ZN(n_0_134) + ); + AOI22_X1_LVT i_0_173( + .A1(CurrentPC[16]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[16]), .ZN(n_0_133) + ); + NAND3_X1_LVT i_0_172( + .A1(n_0_134), .A2(n_0_133), .A3(n_0_165), .ZN(op1[16]) + ); + AOI222_X1_LVT i_0_169( + .A1(CurrentPC[15]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[15]), .C1(n_0_169), + .C2(RRs1[15]), .ZN(n_0_130) + ); + INV_X1_LVT i_0_353( + .A(Instruction[12]), .ZN(n_0_246) + ); + AOI211_X1_LVT i_0_171( + .A(Instruction[5]), .B(n_0_222), .C1(n_0_247), .C2(n_0_246), .ZN(n_0_132) + ); + OAI211_X1_LVT i_0_170( + .A(RData[15]), .B(n_0_132), .C1(Instruction[13]), .C2(Instruction[14]), .ZN(n_0_131) + ); + NAND3_X1_LVT i_0_168( + .A1(n_0_130), .A2(n_0_131), .A3(n_0_165), .ZN(op1[15]) + ); + AOI22_X1_LVT i_0_167( + .A1(RRs1[14]), .A2(n_0_169), .B1(n_0_132), .B2(RData[14]), .ZN(n_0_129) + ); + AOI22_X1_LVT i_0_166( + .A1(CurrentPC[14]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[14]), .ZN(n_0_128) + ); + NAND4_X1_LVT i_0_165( + .A1(n_0_221), .A2(n_0_246), .A3(RData[7]), .A4(n_0_166), .ZN(n_0_127) + ); + NAND3_X1_LVT i_0_164( + .A1(n_0_129), .A2(n_0_128), .A3(n_0_127), .ZN(op1[14]) + ); + AOI22_X1_LVT i_0_163( + .A1(RRs1[13]), .A2(n_0_169), .B1(n_0_132), .B2(RData[13]), .ZN(n_0_126) + ); + AOI22_X1_LVT i_0_162( + .A1(CurrentPC[13]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[13]), .ZN(n_0_125) + ); + NAND3_X1_LVT i_0_161( + .A1(n_0_126), .A2(n_0_125), .A3(n_0_127), .ZN(op1[13]) + ); + AOI22_X1_LVT i_0_160( + .A1(RRs1[12]), .A2(n_0_169), .B1(n_0_132), .B2(RData[12]), .ZN(n_0_124) + ); + AOI22_X1_LVT i_0_159( + .A1(CurrentPC[12]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[12]), .ZN(n_0_123) + ); + NAND3_X1_LVT i_0_158( + .A1(n_0_124), .A2(n_0_123), .A3(n_0_127), .ZN(op1[12]) + ); + AOI22_X1_LVT i_0_156( + .A1(CurrentPC[11]), .A2(n_0_224), .B1(n_0_132), .B2(RData[11]), .ZN(n_0_121) + ); + NAND2_X1_LVT i_0_157( + .A1(RRs1[11]), .A2(n_0_169), .ZN(n_0_122) + ); + NAND3_X1_LVT i_0_155( + .A1(n_0_121), .A2(n_0_122), .A3(n_0_127), .ZN(op1[11]) + ); + AOI22_X1_LVT i_0_153( + .A1(CurrentPC[10]), .A2(n_0_224), .B1(n_0_132), .B2(RData[10]), .ZN(n_0_119) + ); + NAND2_X1_LVT i_0_154( + .A1(RRs1[10]), .A2(n_0_169), .ZN(n_0_120) + ); + NAND3_X1_LVT i_0_152( + .A1(n_0_119), .A2(n_0_120), .A3(n_0_127), .ZN(op1[10]) + ); + AOI22_X1_LVT i_0_150( + .A1(CurrentPC[9]), .A2(n_0_224), .B1(n_0_132), .B2(RData[9]), .ZN(n_0_117) + ); + NAND2_X1_LVT i_0_151( + .A1(RRs1[9]), .A2(n_0_169), .ZN(n_0_118) + ); + NAND3_X1_LVT i_0_149( + .A1(n_0_117), .A2(n_0_118), .A3(n_0_127), .ZN(op1[9]) + ); + AOI22_X1_LVT i_0_147( + .A1(CurrentPC[8]), .A2(n_0_224), .B1(n_0_132), .B2(RData[8]), .ZN(n_0_115) + ); + NAND2_X1_LVT i_0_148( + .A1(RRs1[8]), .A2(n_0_169), .ZN(n_0_116) + ); + NAND3_X1_LVT i_0_146( + .A1(n_0_115), .A2(n_0_116), .A3(n_0_127), .ZN(op1[8]) + ); + AOI222_X1_LVT i_0_145( + .A1(CurrentPC[7]), .A2(n_0_224), .B1(n_0_221), .B2(RData[7]), .C1(n_0_169), + .C2(RRs1[7]), .ZN(n_0_114) + ); + INV_X1_LVT i_0_144( + .A(n_0_114), .ZN(op1[7]) + ); + AOI222_X1_LVT i_0_143( + .A1(CurrentPC[6]), .A2(n_0_224), .B1(n_0_221), .B2(RData[6]), .C1(n_0_169), + .C2(RRs1[6]), .ZN(n_0_113) + ); + INV_X1_LVT i_0_142( + .A(n_0_113), .ZN(op1[6]) + ); + AOI222_X1_LVT i_0_141( + .A1(CurrentPC[5]), .A2(n_0_224), .B1(n_0_221), .B2(RData[5]), .C1(n_0_169), + .C2(RRs1[5]), .ZN(n_0_112) + ); + INV_X1_LVT i_0_140( + .A(n_0_112), .ZN(op1[5]) + ); + AOI222_X1_LVT i_0_139( + .A1(CurrentPC[4]), .A2(n_0_224), .B1(n_0_221), .B2(RData[4]), .C1(n_0_169), + .C2(RRs1[4]), .ZN(n_0_111) + ); + INV_X1_LVT i_0_138( + .A(n_0_111), .ZN(op1[4]) + ); + AOI222_X1_LVT i_0_137( + .A1(CurrentPC[3]), .A2(n_0_224), .B1(n_0_221), .B2(RData[3]), .C1(n_0_169), + .C2(RRs1[3]), .ZN(n_0_110) + ); + INV_X1_LVT i_0_136( + .A(n_0_110), .ZN(op1[3]) + ); + AOI222_X1_LVT i_0_135( + .A1(CurrentPC[2]), .A2(n_0_224), .B1(n_0_221), .B2(RData[2]), .C1(n_0_169), + .C2(RRs1[2]), .ZN(n_0_109) + ); + INV_X1_LVT i_0_134( + .A(n_0_109), .ZN(op1[2]) + ); + AOI222_X1_LVT i_0_133( + .A1(CurrentPC[1]), .A2(n_0_224), .B1(n_0_221), .B2(RData[1]), .C1(n_0_169), + .C2(RRs1[1]), .ZN(n_0_108) + ); + INV_X1_LVT i_0_132( + .A(n_0_108), .ZN(op1[1]) + ); + AOI222_X1_LVT i_0_131( + .A1(CurrentPC[0]), .A2(n_0_224), .B1(n_0_221), .B2(RData[0]), .C1(n_0_169), + .C2(RRs1[0]), .ZN(n_0_107) + ); + INV_X1_LVT i_0_130( + .A(n_0_107), .ZN(op1[0]) + ); + NOR3_X1_LVT i_0_294( + .A1(n_0_223), .A2(Instruction[2]), .A3(Instruction[5]), .ZN(n_0_207) + ); + NOR3_X1_LVT i_0_291( + .A1(n_0_224), .A2(n_0_207), .A3(n_0_205), .ZN(n_0_204) + ); + AOI22_X1_LVT i_0_289( + .A1(CurrentPC[31]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[31]), .ZN(n_0_202) + ); + NAND2_X1_LVT i_0_290( + .A1(Instruction[31]), .A2(n_0_207), .ZN(n_0_203) + ); + NAND2_X1_LVT i_0_288( + .A1(n_0_202), .A2(n_0_203), .ZN(op2[31]) + ); + AOI22_X1_LVT i_0_287( + .A1(CurrentPC[30]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[30]), .ZN(n_0_201) + ); + NAND2_X1_LVT i_0_286( + .A1(n_0_201), .A2(n_0_203), .ZN(op2[30]) + ); + AOI22_X1_LVT i_0_285( + .A1(CurrentPC[29]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[29]), .ZN(n_0_200) + ); + NAND2_X1_LVT i_0_284( + .A1(n_0_200), .A2(n_0_203), .ZN(op2[29]) + ); + AOI22_X1_LVT i_0_283( + .A1(CurrentPC[28]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[28]), .ZN(n_0_199) + ); + NAND2_X1_LVT i_0_282( + .A1(n_0_199), .A2(n_0_203), .ZN(op2[28]) + ); + AOI22_X1_LVT i_0_281( + .A1(CurrentPC[27]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[27]), .ZN(n_0_198) + ); + NAND2_X1_LVT i_0_280( + .A1(n_0_198), .A2(n_0_203), .ZN(op2[27]) + ); + AOI22_X1_LVT i_0_279( + .A1(CurrentPC[26]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[26]), .ZN(n_0_197) + ); + NAND2_X1_LVT i_0_278( + .A1(n_0_197), .A2(n_0_203), .ZN(op2[26]) + ); + AOI22_X1_LVT i_0_277( + .A1(CurrentPC[25]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[25]), .ZN(n_0_196) + ); + NAND2_X1_LVT i_0_276( + .A1(n_0_196), .A2(n_0_203), .ZN(op2[25]) + ); + AOI22_X1_LVT i_0_275( + .A1(CurrentPC[24]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[24]), .ZN(n_0_195) + ); + NAND2_X1_LVT i_0_274( + .A1(n_0_195), .A2(n_0_203), .ZN(op2[24]) + ); + AOI22_X1_LVT i_0_273( + .A1(CurrentPC[23]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[23]), .ZN(n_0_194) + ); + NAND2_X1_LVT i_0_272( + .A1(n_0_194), .A2(n_0_203), .ZN(op2[23]) + ); + AOI22_X1_LVT i_0_271( + .A1(CurrentPC[22]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[22]), .ZN(n_0_193) + ); + NAND2_X1_LVT i_0_270( + .A1(n_0_193), .A2(n_0_203), .ZN(op2[22]) + ); + AOI22_X1_LVT i_0_269( + .A1(CurrentPC[21]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[21]), .ZN(n_0_192) + ); + NAND2_X1_LVT i_0_268( + .A1(n_0_192), .A2(n_0_203), .ZN(op2[21]) + ); + AOI22_X1_LVT i_0_267( + .A1(CurrentPC[20]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[20]), .ZN(n_0_191) + ); + NAND2_X1_LVT i_0_266( + .A1(n_0_191), .A2(n_0_203), .ZN(op2[20]) + ); + AOI22_X1_LVT i_0_265( + .A1(CurrentPC[19]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[19]), .ZN(n_0_190) + ); + NAND2_X1_LVT i_0_264( + .A1(n_0_190), .A2(n_0_203), .ZN(op2[19]) + ); + AOI22_X1_LVT i_0_263( + .A1(CurrentPC[18]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[18]), .ZN(n_0_189) + ); + NAND2_X1_LVT i_0_262( + .A1(n_0_189), .A2(n_0_203), .ZN(op2[18]) + ); + AOI22_X1_LVT i_0_261( + .A1(CurrentPC[17]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[17]), .ZN(n_0_188) + ); + NAND2_X1_LVT i_0_260( + .A1(n_0_188), .A2(n_0_203), .ZN(op2[17]) + ); + AOI22_X1_LVT i_0_259( + .A1(CurrentPC[16]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[16]), .ZN(n_0_187) + ); + NAND2_X1_LVT i_0_258( + .A1(n_0_187), .A2(n_0_203), .ZN(op2[16]) + ); + AOI22_X1_LVT i_0_257( + .A1(CurrentPC[15]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[15]), .ZN(n_0_186) + ); + NAND2_X1_LVT i_0_256( + .A1(n_0_186), .A2(n_0_203), .ZN(op2[15]) + ); + AOI22_X1_LVT i_0_255( + .A1(CurrentPC[14]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[14]), .ZN(n_0_185) + ); + NAND2_X1_LVT i_0_254( + .A1(n_0_185), .A2(n_0_203), .ZN(op2[14]) + ); + AOI22_X1_LVT i_0_253( + .A1(CurrentPC[13]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[13]), .ZN(n_0_184) + ); + NAND2_X1_LVT i_0_252( + .A1(n_0_184), .A2(n_0_203), .ZN(op2[13]) + ); + AOI22_X1_LVT i_0_251( + .A1(CurrentPC[12]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[12]), .ZN(n_0_183) + ); + NAND2_X1_LVT i_0_250( + .A1(n_0_183), .A2(n_0_203), .ZN(op2[12]) + ); + AOI22_X1_LVT i_0_249( + .A1(CurrentPC[11]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[11]), .ZN(n_0_182) + ); + NAND2_X1_LVT i_0_248( + .A1(n_0_182), .A2(n_0_203), .ZN(op2[11]) + ); + AOI222_X1_LVT i_0_247( + .A1(Instruction[30]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[10]), .C1(n_0_204), + .C2(RRs2[10]), .ZN(n_0_181) + ); + INV_X1_LVT i_0_246( + .A(n_0_181), .ZN(op2[10]) + ); + AOI222_X1_LVT i_0_245( + .A1(Instruction[29]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[9]), .C1(n_0_204), + .C2(RRs2[9]), .ZN(n_0_180) + ); + INV_X1_LVT i_0_244( + .A(n_0_180), .ZN(op2[9]) + ); + AOI222_X1_LVT i_0_243( + .A1(Instruction[28]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[8]), .C1(n_0_204), + .C2(RRs2[8]), .ZN(n_0_179) + ); + INV_X1_LVT i_0_242( + .A(n_0_179), .ZN(op2[8]) + ); + AOI222_X1_LVT i_0_241( + .A1(Instruction[27]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[7]), .C1(n_0_204), + .C2(RRs2[7]), .ZN(n_0_178) + ); + INV_X1_LVT i_0_240( + .A(n_0_178), .ZN(op2[7]) + ); + AOI222_X1_LVT i_0_239( + .A1(Instruction[26]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[6]), .C1(n_0_204), + .C2(RRs2[6]), .ZN(n_0_177) + ); + INV_X1_LVT i_0_238( + .A(n_0_177), .ZN(op2[6]) + ); + AOI222_X1_LVT i_0_237( + .A1(Instruction[25]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[5]), .C1(n_0_204), + .C2(RRs2[5]), .ZN(n_0_176) + ); + INV_X1_LVT i_0_236( + .A(n_0_176), .ZN(op2[5]) + ); + AOI222_X1_LVT i_0_235( + .A1(Instruction[24]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[4]), .C1(n_0_204), + .C2(RRs2[4]), .ZN(n_0_175) + ); + INV_X1_LVT i_0_234( + .A(n_0_175), .ZN(op2[4]) + ); + AOI222_X1_LVT i_0_233( + .A1(Instruction[23]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[3]), .C1(n_0_204), + .C2(RRs2[3]), .ZN(n_0_174) + ); + INV_X1_LVT i_0_232( + .A(n_0_174), .ZN(op2[3]) + ); + AOI22_X1_LVT i_0_230( + .A1(Instruction[22]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[2]), .ZN(n_0_172) + ); + OAI21_X1_LVT i_0_231( + .A(RRs2[2]), .B1(n_0_223), .B2(Instruction[5]), .ZN(n_0_173) + ); + NAND3_X1_LVT i_0_229( + .A1(n_0_172), .A2(n_0_173), .A3(n_0_249), .ZN(op2[2]) + ); + AOI222_X1_LVT i_0_228( + .A1(Instruction[21]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[1]), .C1(n_0_204), + .C2(RRs2[1]), .ZN(n_0_171) + ); + INV_X1_LVT i_0_227( + .A(n_0_171), .ZN(op2[1]) + ); + AOI222_X1_LVT i_0_226( + .A1(Instruction[20]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[0]), .C1(n_0_204), + .C2(RRs2[0]), .ZN(n_0_170) + ); + INV_X1_LVT i_0_225( + .A(n_0_170), .ZN(op2[0]) + ); + alu theALU( + .aluOp(aluOp), .aluNegAr(aluNegAr), .aluBypass(aluBypass), .op1(op1), .op2(op2), + .result(WRd), .eqFlag(eqFlag) + ); + XNOR2_X1_LVT i_0_115( + .A(Instruction[12]), .B(eqFlag), .ZN(n_0_97) + ); + XNOR2_X1_LVT i_0_114( + .A(Instruction[12]), .B(WRd[0]), .ZN(n_0_96) + ); + AOI22_X1_LVT i_0_113( + .A1(n_0_166), .A2(n_0_97), .B1(n_0_96), .B2(Instruction[14]), .ZN(n_0_95) + ); + AOI22_X1_LVT i_0_111( + .A1(Instruction[6]), .A2(n_0_95), .B1(Instruction[2]), .B2(n_0_245), .ZN(n_0_93) + ); + NAND2_X1_LVT i_0_110( + .A1(n_0_94), .A2(n_0_93), .ZN(JumpOrBranch) + ); + INV_X1_LVT i_0_349( + .A(Instruction[31]), .ZN(n_0_0) + ); + INV_X1_LVT i_0_348( + .A(RRs1[12]), .ZN(n_0_1) + ); + HA_X1_LVT i_0_0( + .A(Instruction[7]), .B(RRs1[0]), .CO(n_0_2), .S(n_0_15) + ); + FA_X1_LVT i_0_1( + .A(Instruction[8]), .B(RRs1[1]), .CI(n_0_2), .CO(n_0_3), .S(n_0_16) + ); + FA_X1_LVT i_0_2( + .A(Instruction[9]), .B(RRs1[2]), .CI(n_0_3), .CO(n_0_4), .S(n_0_17) + ); + FA_X1_LVT i_0_3( + .A(Instruction[10]), .B(RRs1[3]), .CI(n_0_4), .CO(n_0_5), .S(n_0_18) + ); + FA_X1_LVT i_0_4( + .A(Instruction[11]), .B(RRs1[4]), .CI(n_0_5), .CO(n_0_6), .S(n_0_19) + ); + FA_X1_LVT i_0_5( + .A(Instruction[25]), .B(RRs1[5]), .CI(n_0_6), .CO(n_0_7), .S(n_0_20) + ); + FA_X1_LVT i_0_6( + .A(Instruction[26]), .B(RRs1[6]), .CI(n_0_7), .CO(n_0_8), .S(n_0_21) + ); + FA_X1_LVT i_0_7( + .A(Instruction[27]), .B(RRs1[7]), .CI(n_0_8), .CO(n_0_9), .S(n_0_22) + ); + FA_X1_LVT i_0_8( + .A(Instruction[28]), .B(RRs1[8]), .CI(n_0_9), .CO(n_0_10), .S(n_0_23) + ); + FA_X1_LVT i_0_9( + .A(Instruction[29]), .B(RRs1[9]), .CI(n_0_10), .CO(n_0_11), .S(n_0_24) + ); + FA_X1_LVT i_0_10( + .A(Instruction[30]), .B(RRs1[10]), .CI(n_0_11), .CO(n_0_12), .S(n_0_25) + ); + FA_X1_LVT i_0_11( + .A(RRs1[11]), .B(Instruction[31]), .CI(n_0_12), .CO(n_0_13), .S(n_0_26) + ); + FA_X1_LVT i_0_12( + .A(n_0_0), .B(n_0_1), .CI(n_0_13), .CO(n_0_14), .S(n_0_27) + ); + NOR2_X1_LVT i_0_322( + .A1(n_0_244), .A2(n_0_222), .ZN(WrMem) + ); + AOI22_X1_LVT i_0_320( + .A1(n_0_27), .A2(WrMem), .B1(n_0_221), .B2(n_12), .ZN(n_0_220) + ); + INV_X1_LVT i_0_319( + .A(n_0_220), .ZN(DAddr[12]) + ); + AOI22_X1_LVT i_0_318( + .A1(n_0_26), .A2(WrMem), .B1(n_0_221), .B2(n_11), .ZN(n_0_219) + ); + INV_X1_LVT i_0_317( + .A(n_0_219), .ZN(DAddr[11]) + ); + AOI22_X1_LVT i_0_316( + .A1(n_0_25), .A2(WrMem), .B1(n_0_221), .B2(n_10), .ZN(n_0_218) + ); + INV_X1_LVT i_0_315( + .A(n_0_218), .ZN(DAddr[10]) + ); + AOI22_X1_LVT i_0_314( + .A1(n_0_24), .A2(WrMem), .B1(n_0_221), .B2(n_9), .ZN(n_0_217) + ); + INV_X1_LVT i_0_313( + .A(n_0_217), .ZN(DAddr[9]) + ); + AOI22_X1_LVT i_0_312( + .A1(n_0_23), .A2(WrMem), .B1(n_0_221), .B2(n_8), .ZN(n_0_216) + ); + INV_X1_LVT i_0_311( + .A(n_0_216), .ZN(DAddr[8]) + ); + AOI22_X1_LVT i_0_310( + .A1(n_0_22), .A2(WrMem), .B1(n_0_221), .B2(n_7), .ZN(n_0_215) + ); + INV_X1_LVT i_0_309( + .A(n_0_215), .ZN(DAddr[7]) + ); + AOI22_X1_LVT i_0_308( + .A1(n_0_21), .A2(WrMem), .B1(n_0_221), .B2(n_6), .ZN(n_0_214) + ); + INV_X1_LVT i_0_307( + .A(n_0_214), .ZN(DAddr[6]) + ); + AOI22_X1_LVT i_0_306( + .A1(n_0_20), .A2(WrMem), .B1(n_0_221), .B2(n_5), .ZN(n_0_213) + ); + INV_X1_LVT i_0_305( + .A(n_0_213), .ZN(DAddr[5]) + ); + AOI22_X1_LVT i_0_304( + .A1(n_0_19), .A2(WrMem), .B1(n_0_221), .B2(n_4), .ZN(n_0_212) + ); + INV_X1_LVT i_0_303( + .A(n_0_212), .ZN(DAddr[4]) + ); + AOI22_X1_LVT i_0_302( + .A1(n_0_18), .A2(WrMem), .B1(n_0_221), .B2(n_3), .ZN(n_0_211) + ); + INV_X1_LVT i_0_301( + .A(n_0_211), .ZN(DAddr[3]) + ); + AOI22_X1_LVT i_0_300( + .A1(n_0_17), .A2(WrMem), .B1(n_0_221), .B2(n_2), .ZN(n_0_210) + ); + INV_X1_LVT i_0_299( + .A(n_0_210), .ZN(DAddr[2]) + ); + AOI22_X1_LVT i_0_298( + .A1(n_0_16), .A2(WrMem), .B1(n_0_221), .B2(n_1), .ZN(n_0_209) + ); + INV_X1_LVT i_0_297( + .A(n_0_209), .ZN(DAddr[1]) + ); + AOI22_X1_LVT i_0_296( + .A1(n_0_15), .A2(WrMem), .B1(n_0_221), .B2(n_0), .ZN(n_0_208) + ); + INV_X1_LVT i_0_295( + .A(n_0_208), .ZN(DAddr[0]) + ); + OR2_X1_LVT i_0_324( + .A1(n_0_222), .A2(Instruction[13]), .ZN(DWidth[1]) + ); + NOR2_X1_LVT i_0_323( + .A1(n_0_246), .A2(n_0_222), .ZN(DWidth[0]) + ); + NAND3_X1_LVT i_0_331( + .A1(n_0_248), .A2(n_0_244), .A3(n_0_236), .ZN(n_0_227) + ); + OAI211_X1_LVT i_0_326( + .A(n_0_249), .B(n_0_223), .C1(n_0_228), .C2(n_0_227), .ZN(WrReg) + ); +endmodule + +module MemGen_32_11(chip_en, clock, addr, rd_data, rd_en, wr_en, wr_data); + input [31:0] wr_data; + input [10:0] addr; + input chip_en, clock, rd_en, wr_en; + output [31:0] rd_data; + + wire [1:0] mem_sel; + wire n_63, n_62, n_61, n_60, n_59, n_58, n_57, n_56, n_55, n_54, n_53, n_52, + n_51, n_50, n_49, n_48, n_31, n_30, n_29, n_28, n_27, n_26, n_25, n_24, + n_23, n_22, n_21, n_20, n_19, n_18, n_17, n_16, n_47, n_46, n_45, n_44, + n_43, n_42, n_41, n_40, n_39, n_38, n_37, n_36, n_35, n_34, n_33, n_32, + n_15, n_14, n_13, n_12, n_11, n_10, n_9, n_8, n_7, n_6, n_5, n_4, n_3, + n_2, n_1, n_0; + + INV_X1_LVT i_1_3( + .A(addr[10]), .ZN(mem_sel[0]) + ); + MemGen_16_10 genblk1_0_U_hi( + .chip_en(mem_sel[0]), .wr_en(wr_en), .addr({addr[9], addr[8], addr[7], + addr[6], addr[5], addr[4], addr[3], addr[2], addr[1], addr[0]}), .wr_data({ + wr_data[31], wr_data[30], wr_data[29], wr_data[28], wr_data[27], + wr_data[26], wr_data[25], wr_data[24], wr_data[23], wr_data[22], + wr_data[21], wr_data[20], wr_data[19], wr_data[18], wr_data[17], + wr_data[16]}), .clock(clock), .rd_en(rd_en), .rd_data({n_63, n_62, n_61, + n_60, n_59, n_58, n_57, n_56, n_55, n_54, n_53, n_52, n_51, n_50, n_49, + n_48}) + ); + MemGen_16_10 genblk1_1_U_hi( + .chip_en(addr[10]), .wr_en(wr_en), .addr({addr[9], addr[8], addr[7], + addr[6], addr[5], addr[4], addr[3], addr[2], addr[1], addr[0]}), .wr_data({ + wr_data[31], wr_data[30], wr_data[29], wr_data[28], wr_data[27], + wr_data[26], wr_data[25], wr_data[24], wr_data[23], wr_data[22], + wr_data[21], wr_data[20], wr_data[19], wr_data[18], wr_data[17], + wr_data[16]}), .clock(clock), .rd_en(rd_en), .rd_data({n_31, n_30, n_29, + n_28, n_27, n_26, n_25, n_24, n_23, n_22, n_21, n_20, n_19, n_18, n_17, + n_16}) + ); + MUX2_X1_LVT i_1_1_31( + .A(n_63), .B(n_31), .S(addr[10]), .Z(rd_data[31]) + ); + MUX2_X1_LVT i_1_1_30( + .A(n_62), .B(n_30), .S(addr[10]), .Z(rd_data[30]) + ); + MUX2_X1_LVT i_1_1_29( + .A(n_61), .B(n_29), .S(addr[10]), .Z(rd_data[29]) + ); + MUX2_X1_LVT i_1_1_28( + .A(n_60), .B(n_28), .S(addr[10]), .Z(rd_data[28]) + ); + MUX2_X1_LVT i_1_1_27( + .A(n_59), .B(n_27), .S(addr[10]), .Z(rd_data[27]) + ); + MUX2_X1_LVT i_1_1_26( + .A(n_58), .B(n_26), .S(addr[10]), .Z(rd_data[26]) + ); + MUX2_X1_LVT i_1_1_25( + .A(n_57), .B(n_25), .S(addr[10]), .Z(rd_data[25]) + ); + MUX2_X1_LVT i_1_1_24( + .A(n_56), .B(n_24), .S(addr[10]), .Z(rd_data[24]) + ); + MUX2_X1_LVT i_1_1_23( + .A(n_55), .B(n_23), .S(addr[10]), .Z(rd_data[23]) + ); + MUX2_X1_LVT i_1_1_22( + .A(n_54), .B(n_22), .S(addr[10]), .Z(rd_data[22]) + ); + MUX2_X1_LVT i_1_1_21( + .A(n_53), .B(n_21), .S(addr[10]), .Z(rd_data[21]) + ); + MUX2_X1_LVT i_1_1_20( + .A(n_52), .B(n_20), .S(addr[10]), .Z(rd_data[20]) + ); + MUX2_X1_LVT i_1_1_19( + .A(n_51), .B(n_19), .S(addr[10]), .Z(rd_data[19]) + ); + MUX2_X1_LVT i_1_1_18( + .A(n_50), .B(n_18), .S(addr[10]), .Z(rd_data[18]) + ); + MUX2_X1_LVT i_1_1_17( + .A(n_49), .B(n_17), .S(addr[10]), .Z(rd_data[17]) + ); + MUX2_X1_LVT i_1_1_16( + .A(n_48), .B(n_16), .S(addr[10]), .Z(rd_data[16]) + ); + MemGen_16_10 genblk1_0_U_lo( + .chip_en(mem_sel[0]), .wr_en(wr_en), .addr({addr[9], addr[8], addr[7], + addr[6], addr[5], addr[4], addr[3], addr[2], addr[1], addr[0]}), .wr_data({ + wr_data[15], wr_data[14], wr_data[13], wr_data[12], wr_data[11], + wr_data[10], wr_data[9], wr_data[8], wr_data[7], wr_data[6], wr_data[5], + wr_data[4], wr_data[3], wr_data[2], wr_data[1], wr_data[0]}), .clock(clock), + .rd_en(rd_en), .rd_data({n_47, n_46, n_45, n_44, n_43, n_42, n_41, + n_40, n_39, n_38, n_37, n_36, n_35, n_34, n_33, n_32}) + ); + MemGen_16_10 genblk1_1_U_lo( + .chip_en(addr[10]), .wr_en(wr_en), .addr({addr[9], addr[8], addr[7], + addr[6], addr[5], addr[4], addr[3], addr[2], addr[1], addr[0]}), .wr_data({ + wr_data[15], wr_data[14], wr_data[13], wr_data[12], wr_data[11], + wr_data[10], wr_data[9], wr_data[8], wr_data[7], wr_data[6], wr_data[5], + wr_data[4], wr_data[3], wr_data[2], wr_data[1], wr_data[0]}), .clock(clock), + .rd_en(rd_en), .rd_data({n_15, n_14, n_13, n_12, n_11, n_10, n_9, n_8, + n_7, n_6, n_5, n_4, n_3, n_2, n_1, n_0}) + ); + MUX2_X1_LVT i_1_1_15( + .A(n_47), .B(n_15), .S(addr[10]), .Z(rd_data[15]) + ); + MUX2_X1_LVT i_1_1_14( + .A(n_46), .B(n_14), .S(addr[10]), .Z(rd_data[14]) + ); + MUX2_X1_LVT i_1_1_13( + .A(n_45), .B(n_13), .S(addr[10]), .Z(rd_data[13]) + ); + MUX2_X1_LVT i_1_1_12( + .A(n_44), .B(n_12), .S(addr[10]), .Z(rd_data[12]) + ); + MUX2_X1_LVT i_1_1_11( + .A(n_43), .B(n_11), .S(addr[10]), .Z(rd_data[11]) + ); + MUX2_X1_LVT i_1_1_10( + .A(n_42), .B(n_10), .S(addr[10]), .Z(rd_data[10]) + ); + MUX2_X1_LVT i_1_1_9( + .A(n_41), .B(n_9), .S(addr[10]), .Z(rd_data[9]) + ); + MUX2_X1_LVT i_1_1_8( + .A(n_40), .B(n_8), .S(addr[10]), .Z(rd_data[8]) + ); + MUX2_X1_LVT i_1_1_7( + .A(n_39), .B(n_7), .S(addr[10]), .Z(rd_data[7]) + ); + MUX2_X1_LVT i_1_1_6( + .A(n_38), .B(n_6), .S(addr[10]), .Z(rd_data[6]) + ); + MUX2_X1_LVT i_1_1_5( + .A(n_37), .B(n_5), .S(addr[10]), .Z(rd_data[5]) + ); + MUX2_X1_LVT i_1_1_4( + .A(n_36), .B(n_4), .S(addr[10]), .Z(rd_data[4]) + ); + MUX2_X1_LVT i_1_1_3( + .A(n_35), .B(n_3), .S(addr[10]), .Z(rd_data[3]) + ); + MUX2_X1_LVT i_1_1_2( + .A(n_34), .B(n_2), .S(addr[10]), .Z(rd_data[2]) + ); + MUX2_X1_LVT i_1_1_1( + .A(n_33), .B(n_1), .S(addr[10]), .Z(rd_data[1]) + ); + MUX2_X1_LVT i_1_1_0( + .A(n_32), .B(n_0), .S(addr[10]), .Z(rd_data[0]) + ); +endmodule + +module main_mem(clk, reset, DAddr, IAddr, DWData, DRData, IRData, DWE, DWidth); + input [31:0] DAddr, IAddr, DWData; + input [1:0] DWidth; + input clk, reset, DWE; + output [31:0] DRData, IRData; + + wire [31:0] mem_rdata, drTmp, mem_wdata; + wire [10:0] mem_addr; + wire n_0_0, n_0_0_0, n_0_1, n_0_0_1, n_0_2, n_0_0_2, n_0_3, n_0_0_3, n_0_4, + n_0_0_4, n_0_5, n_0_0_5, n_0_6, n_0_0_6, n_0_7, n_0_0_7, n_0_8, n_0_0_8, + n_0_9, n_0_0_9, n_0_10, n_0_0_10, n_0_0_11, n_0_11, n_0_0_12, n_0_0_13, + n_0_12, n_0_0_14, n_0_0_15, n_0_13, n_0_0_16, n_0_0_17, n_0_14, + n_0_0_18, n_0_0_19, n_0_15, n_0_0_20, n_0_0_21, n_0_16, n_0_0_22, + n_0_0_23, n_0_17, n_0_0_24, n_0_0_25, n_0_18, n_0_0_26, n_0_0_27, + n_0_0_28, n_0_19, n_0_0_29, n_0_20, n_0_0_30, n_0_21, n_0_0_31, n_0_22, + n_0_0_32, n_0_23, n_0_0_33, n_0_24, n_0_0_34, n_0_25, n_0_0_35, n_0_26, + n_0_0_36, n_0_0_37, n_0_27, n_0_28, n_0_29, n_0_30, n_0_31, n_0_32, + n_0_33, n_0_34, n_0_35, n_0_36, n_0_37, n_0_38, n_0_39, n_0_40, n_0_41, + n_0_42, n_0_65, n_0_64, n_0_63, n_0_62, n_0_61, n_0_60, n_0_59, n_0_58, + n_0_0_38, n_0_0_39, n_0_57, n_0_0_40, n_0_56, n_0_0_41, n_0_55, + n_0_0_42, n_0_54, n_0_0_43, n_0_53, n_0_0_44, n_0_52, n_0_0_45, n_0_51, + n_0_0_46, n_0_50, n_0_0_47, n_0_0_48, n_0_0_49, n_0_0_50, n_0_0_51, + n_0_49, n_0_0_52, n_0_48, n_0_0_53, n_0_47, n_0_0_54, n_0_46, n_0_0_55, + n_0_45, n_0_0_56, n_0_44, n_0_0_57, n_0_66, n_0_0_58, n_0_67, n_0_0_59, + n_0_0_60, n_0_0_61, n_0_68, n_0_0_62, n_0_0_63, n_0_69, n_0_0_64, + n_0_0_65, n_0_70, n_0_0_66, n_0_0_67, n_0_71, n_0_0_68, n_0_0_69, + n_0_72, n_0_0_70, n_0_0_71, n_0_73, n_0_0_72, n_0_0_73, n_0_74, + n_0_0_74, n_0_0_75, n_0_75, n_0_0_76, n_0_0_77, n_0_0_78, n_0_0_79, + n_0_0_80, n_0_0_81, n_0_0_82, n_0_0_83, n_0_0_84, n_0_0_85, n_0_0_86, + n_0_0_87, n_0_0_88, n_0_0_89, n_0_0_90, n_0_0_91, n_0_0_92, n_0_43, + n_0_0_93, n_0_0_94, n_0_76, n_0_0_95, n_0; + + INV_X1_LVT i_0_0_171( + .A(DWE), .ZN(n_0) + ); + NOR2_X1_LVT i_0_0_163( + .A1(n_0), .A2(reset), .ZN(n_0_0_88) + ); + NOR2_X1_LVT i_0_0_22( + .A1(DWE), .A2(reset), .ZN(n_0_0_11) + ); + AOI22_X1_LVT i_0_0_21( + .A1(DAddr[12]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[12]), .ZN(n_0_0_10) + ); + INV_X1_LVT i_0_0_20( + .A(n_0_0_10), .ZN(n_0_10) + ); + INV_X1_LVT i_0_0_172( + .A(clk), .ZN(n_0_76) + ); + DFF_X1_LVT \mem_addr_reg[10] ( + .CK(n_0_76), .D(n_0_10), .Q(mem_addr[10]), .QN() + ); + AOI22_X1_LVT i_0_0_19( + .A1(DAddr[11]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[11]), .ZN(n_0_0_9) + ); + INV_X1_LVT i_0_0_18( + .A(n_0_0_9), .ZN(n_0_9) + ); + DFF_X1_LVT \mem_addr_reg[9] ( + .CK(n_0_76), .D(n_0_9), .Q(mem_addr[9]), .QN() + ); + AOI22_X1_LVT i_0_0_17( + .A1(DAddr[10]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[10]), .ZN(n_0_0_8) + ); + INV_X1_LVT i_0_0_16( + .A(n_0_0_8), .ZN(n_0_8) + ); + DFF_X1_LVT \mem_addr_reg[8] ( + .CK(n_0_76), .D(n_0_8), .Q(mem_addr[8]), .QN() + ); + AOI22_X1_LVT i_0_0_15( + .A1(DAddr[9]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[9]), .ZN(n_0_0_7) + ); + INV_X1_LVT i_0_0_14( + .A(n_0_0_7), .ZN(n_0_7) + ); + DFF_X1_LVT \mem_addr_reg[7] ( + .CK(n_0_76), .D(n_0_7), .Q(mem_addr[7]), .QN() + ); + AOI22_X1_LVT i_0_0_13( + .A1(DAddr[8]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[8]), .ZN(n_0_0_6) + ); + INV_X1_LVT i_0_0_12( + .A(n_0_0_6), .ZN(n_0_6) + ); + DFF_X1_LVT \mem_addr_reg[6] ( + .CK(n_0_76), .D(n_0_6), .Q(mem_addr[6]), .QN() + ); + AOI22_X1_LVT i_0_0_11( + .A1(DAddr[7]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[7]), .ZN(n_0_0_5) + ); + INV_X1_LVT i_0_0_10( + .A(n_0_0_5), .ZN(n_0_5) + ); + DFF_X1_LVT \mem_addr_reg[5] ( + .CK(n_0_76), .D(n_0_5), .Q(mem_addr[5]), .QN() + ); + AOI22_X1_LVT i_0_0_9( + .A1(DAddr[6]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[6]), .ZN(n_0_0_4) + ); + INV_X1_LVT i_0_0_8( + .A(n_0_0_4), .ZN(n_0_4) + ); + DFF_X1_LVT \mem_addr_reg[4] ( + .CK(n_0_76), .D(n_0_4), .Q(mem_addr[4]), .QN() + ); + AOI22_X1_LVT i_0_0_7( + .A1(DAddr[5]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[5]), .ZN(n_0_0_3) + ); + INV_X1_LVT i_0_0_6( + .A(n_0_0_3), .ZN(n_0_3) + ); + DFF_X1_LVT \mem_addr_reg[3] ( + .CK(n_0_76), .D(n_0_3), .Q(mem_addr[3]), .QN() + ); + AOI22_X1_LVT i_0_0_5( + .A1(DAddr[4]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[4]), .ZN(n_0_0_2) + ); + INV_X1_LVT i_0_0_4( + .A(n_0_0_2), .ZN(n_0_2) + ); + DFF_X1_LVT \mem_addr_reg[2] ( + .CK(n_0_76), .D(n_0_2), .Q(mem_addr[2]), .QN() + ); + AOI22_X1_LVT i_0_0_3( + .A1(DAddr[3]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[3]), .ZN(n_0_0_1) + ); + INV_X1_LVT i_0_0_2( + .A(n_0_0_1), .ZN(n_0_1) + ); + DFF_X1_LVT \mem_addr_reg[1] ( + .CK(n_0_76), .D(n_0_1), .Q(mem_addr[1]), .QN() + ); + AOI22_X1_LVT i_0_0_1( + .A1(DAddr[2]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[2]), .ZN(n_0_0_0) + ); + INV_X1_LVT i_0_0_0( + .A(n_0_0_0), .ZN(n_0_0) + ); + DFF_X1_LVT \mem_addr_reg[0] ( + .CK(n_0_76), .D(n_0_0), .Q(mem_addr[0]), .QN() + ); + NOR2_X1_LVT i_0_0_162( + .A1(DWidth[1]), .A2(DAddr[1]), .ZN(n_0_0_87) + ); + NOR2_X1_LVT i_0_0_158( + .A1(DWidth[0]), .A2(DAddr[0]), .ZN(n_0_0_83) + ); + AND2_X1_LVT i_0_0_157( + .A1(n_0_0_87), .A2(n_0_0_83), .ZN(n_0_0_82) + ); + AND2_X1_LVT i_0_0_156( + .A1(n_0_0_88), .A2(n_0_0_82), .ZN(n_0_0_81) + ); + INV_X1_LVT i_0_0_173( + .A(n_0_0_88), .ZN(n_0_0_95) + ); + INV_X1_LVT i_0_0_169( + .A(DWidth[1]), .ZN(n_0_0_93) + ); + NOR3_X1_LVT i_0_0_155( + .A1(n_0_0_95), .A2(DWidth[0]), .A3(n_0_0_93), .ZN(n_0_0_80) + ); + AOI22_X1_LVT i_0_0_154( + .A1(DWData[7]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[31]), .ZN(n_0_0_79) + ); + NAND2_X1_LVT i_0_0_168( + .A1(DWidth[0]), .A2(DWidth[1]), .ZN(n_0_43) + ); + INV_X1_LVT i_0_0_167( + .A(n_0_43), .ZN(n_0_0_92) + ); + NOR2_X1_LVT i_0_0_160( + .A1(n_0_0_95), .A2(n_0_0_92), .ZN(n_0_0_85) + ); + NAND2_X1_LVT i_0_0_161( + .A1(n_0_0_93), .A2(DAddr[1]), .ZN(n_0_0_86) + ); + NOR2_X1_LVT i_0_0_166( + .A1(DWidth[0]), .A2(DWidth[1]), .ZN(n_0_0_91) + ); + NAND2_X1_LVT i_0_0_164( + .A1(DAddr[0]), .A2(n_0_0_91), .ZN(n_0_0_89) + ); + NAND3_X1_LVT i_0_0_159( + .A1(n_0_0_85), .A2(n_0_0_86), .A3(n_0_0_89), .ZN(n_0_0_84) + ); + INV_X1_LVT i_0_0_170( + .A(DWidth[0]), .ZN(n_0_0_94) + ); + NOR2_X1_LVT i_0_0_153( + .A1(n_0_0_94), .A2(DAddr[1]), .ZN(n_0_0_78) + ); + AND3_X1_LVT i_0_0_152( + .A1(n_0_0_88), .A2(n_0_0_78), .A3(n_0_0_93), .ZN(n_0_0_77) + ); + AOI22_X1_LVT i_0_0_151( + .A1(n_0_0_84), .A2(mem_wdata[31]), .B1(DWData[15]), .B2(n_0_0_77), .ZN(n_0_0_76) + ); + NAND2_X1_LVT i_0_0_150( + .A1(n_0_0_79), .A2(n_0_0_76), .ZN(n_0_75) + ); + DFF_X1_LVT \mem_wdata_reg[31] ( + .CK(n_0_76), .D(n_0_75), .Q(mem_wdata[31]), .QN() + ); + AOI22_X1_LVT i_0_0_149( + .A1(DWData[6]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[30]), .ZN(n_0_0_75) + ); + AOI22_X1_LVT i_0_0_148( + .A1(n_0_0_84), .A2(mem_wdata[30]), .B1(DWData[14]), .B2(n_0_0_77), .ZN(n_0_0_74) + ); + NAND2_X1_LVT i_0_0_147( + .A1(n_0_0_75), .A2(n_0_0_74), .ZN(n_0_74) + ); + DFF_X1_LVT \mem_wdata_reg[30] ( + .CK(n_0_76), .D(n_0_74), .Q(mem_wdata[30]), .QN() + ); + AOI22_X1_LVT i_0_0_146( + .A1(DWData[5]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[29]), .ZN(n_0_0_73) + ); + AOI22_X1_LVT i_0_0_145( + .A1(n_0_0_84), .A2(mem_wdata[29]), .B1(DWData[13]), .B2(n_0_0_77), .ZN(n_0_0_72) + ); + NAND2_X1_LVT i_0_0_144( + .A1(n_0_0_73), .A2(n_0_0_72), .ZN(n_0_73) + ); + DFF_X1_LVT \mem_wdata_reg[29] ( + .CK(n_0_76), .D(n_0_73), .Q(mem_wdata[29]), .QN() + ); + AOI22_X1_LVT i_0_0_143( + .A1(DWData[4]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[28]), .ZN(n_0_0_71) + ); + AOI22_X1_LVT i_0_0_142( + .A1(n_0_0_84), .A2(mem_wdata[28]), .B1(DWData[12]), .B2(n_0_0_77), .ZN(n_0_0_70) + ); + NAND2_X1_LVT i_0_0_141( + .A1(n_0_0_71), .A2(n_0_0_70), .ZN(n_0_72) + ); + DFF_X1_LVT \mem_wdata_reg[28] ( + .CK(n_0_76), .D(n_0_72), .Q(mem_wdata[28]), .QN() + ); + AOI22_X1_LVT i_0_0_140( + .A1(DWData[3]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[27]), .ZN(n_0_0_69) + ); + AOI22_X1_LVT i_0_0_139( + .A1(n_0_0_84), .A2(mem_wdata[27]), .B1(DWData[11]), .B2(n_0_0_77), .ZN(n_0_0_68) + ); + NAND2_X1_LVT i_0_0_138( + .A1(n_0_0_69), .A2(n_0_0_68), .ZN(n_0_71) + ); + DFF_X1_LVT \mem_wdata_reg[27] ( + .CK(n_0_76), .D(n_0_71), .Q(mem_wdata[27]), .QN() + ); + AOI22_X1_LVT i_0_0_137( + .A1(DWData[2]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[26]), .ZN(n_0_0_67) + ); + AOI22_X1_LVT i_0_0_136( + .A1(n_0_0_84), .A2(mem_wdata[26]), .B1(DWData[10]), .B2(n_0_0_77), .ZN(n_0_0_66) + ); + NAND2_X1_LVT i_0_0_135( + .A1(n_0_0_67), .A2(n_0_0_66), .ZN(n_0_70) + ); + DFF_X1_LVT \mem_wdata_reg[26] ( + .CK(n_0_76), .D(n_0_70), .Q(mem_wdata[26]), .QN() + ); + AOI22_X1_LVT i_0_0_134( + .A1(DWData[1]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[25]), .ZN(n_0_0_65) + ); + AOI22_X1_LVT i_0_0_133( + .A1(n_0_0_84), .A2(mem_wdata[25]), .B1(DWData[9]), .B2(n_0_0_77), .ZN(n_0_0_64) + ); + NAND2_X1_LVT i_0_0_132( + .A1(n_0_0_65), .A2(n_0_0_64), .ZN(n_0_69) + ); + DFF_X1_LVT \mem_wdata_reg[25] ( + .CK(n_0_76), .D(n_0_69), .Q(mem_wdata[25]), .QN() + ); + AOI22_X1_LVT i_0_0_131( + .A1(DWData[0]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[24]), .ZN(n_0_0_63) + ); + AOI22_X1_LVT i_0_0_130( + .A1(n_0_0_84), .A2(mem_wdata[24]), .B1(DWData[8]), .B2(n_0_0_77), .ZN(n_0_0_62) + ); + NAND2_X1_LVT i_0_0_129( + .A1(n_0_0_63), .A2(n_0_0_62), .ZN(n_0_68) + ); + DFF_X1_LVT \mem_wdata_reg[24] ( + .CK(n_0_76), .D(n_0_68), .Q(mem_wdata[24]), .QN() + ); + NOR4_X1_LVT i_0_0_127( + .A1(n_0_0_95), .A2(n_0_0_83), .A3(DWidth[1]), .A4(DAddr[1]), .ZN(n_0_0_60) + ); + INV_X1_LVT i_0_0_165( + .A(n_0_0_91), .ZN(n_0_0_90) + ); + OAI211_X1_LVT i_0_0_128( + .A(n_0_0_85), .B(n_0_0_86), .C1(n_0_0_90), .C2(DAddr[0]), .ZN(n_0_0_61) + ); + AOI222_X1_LVT i_0_0_126( + .A1(DWData[7]), .A2(n_0_0_60), .B1(mem_wdata[23]), .B2(n_0_0_61), .C1(DWData[23]), + .C2(n_0_0_80), .ZN(n_0_0_59) + ); + INV_X1_LVT i_0_0_125( + .A(n_0_0_59), .ZN(n_0_67) + ); + DFF_X1_LVT \mem_wdata_reg[23] ( + .CK(n_0_76), .D(n_0_67), .Q(mem_wdata[23]), .QN() + ); + AOI222_X1_LVT i_0_0_124( + .A1(DWData[6]), .A2(n_0_0_60), .B1(mem_wdata[22]), .B2(n_0_0_61), .C1(DWData[22]), + .C2(n_0_0_80), .ZN(n_0_0_58) + ); + INV_X1_LVT i_0_0_123( + .A(n_0_0_58), .ZN(n_0_66) + ); + DFF_X1_LVT \mem_wdata_reg[22] ( + .CK(n_0_76), .D(n_0_66), .Q(mem_wdata[22]), .QN() + ); + AOI222_X1_LVT i_0_0_122( + .A1(DWData[5]), .A2(n_0_0_60), .B1(mem_wdata[21]), .B2(n_0_0_61), .C1(DWData[21]), + .C2(n_0_0_80), .ZN(n_0_0_57) + ); + INV_X1_LVT i_0_0_121( + .A(n_0_0_57), .ZN(n_0_44) + ); + DFF_X1_LVT \mem_wdata_reg[21] ( + .CK(n_0_76), .D(n_0_44), .Q(mem_wdata[21]), .QN() + ); + AOI222_X1_LVT i_0_0_120( + .A1(DWData[4]), .A2(n_0_0_60), .B1(mem_wdata[20]), .B2(n_0_0_61), .C1(DWData[20]), + .C2(n_0_0_80), .ZN(n_0_0_56) + ); + INV_X1_LVT i_0_0_119( + .A(n_0_0_56), .ZN(n_0_45) + ); + DFF_X1_LVT \mem_wdata_reg[20] ( + .CK(n_0_76), .D(n_0_45), .Q(mem_wdata[20]), .QN() + ); + AOI222_X1_LVT i_0_0_118( + .A1(DWData[3]), .A2(n_0_0_60), .B1(mem_wdata[19]), .B2(n_0_0_61), .C1(DWData[19]), + .C2(n_0_0_80), .ZN(n_0_0_55) + ); + INV_X1_LVT i_0_0_117( + .A(n_0_0_55), .ZN(n_0_46) + ); + DFF_X1_LVT \mem_wdata_reg[19] ( + .CK(n_0_76), .D(n_0_46), .Q(mem_wdata[19]), .QN() + ); + AOI222_X1_LVT i_0_0_116( + .A1(DWData[2]), .A2(n_0_0_60), .B1(mem_wdata[18]), .B2(n_0_0_61), .C1(DWData[18]), + .C2(n_0_0_80), .ZN(n_0_0_54) + ); + INV_X1_LVT i_0_0_115( + .A(n_0_0_54), .ZN(n_0_47) + ); + DFF_X1_LVT \mem_wdata_reg[18] ( + .CK(n_0_76), .D(n_0_47), .Q(mem_wdata[18]), .QN() + ); + AOI222_X1_LVT i_0_0_114( + .A1(DWData[1]), .A2(n_0_0_60), .B1(mem_wdata[17]), .B2(n_0_0_61), .C1(DWData[17]), + .C2(n_0_0_80), .ZN(n_0_0_53) + ); + INV_X1_LVT i_0_0_113( + .A(n_0_0_53), .ZN(n_0_48) + ); + DFF_X1_LVT \mem_wdata_reg[17] ( + .CK(n_0_76), .D(n_0_48), .Q(mem_wdata[17]), .QN() + ); + AOI222_X1_LVT i_0_0_112( + .A1(DWData[0]), .A2(n_0_0_60), .B1(mem_wdata[16]), .B2(n_0_0_61), .C1(DWData[16]), + .C2(n_0_0_80), .ZN(n_0_0_52) + ); + INV_X1_LVT i_0_0_111( + .A(n_0_0_52), .ZN(n_0_49) + ); + DFF_X1_LVT \mem_wdata_reg[16] ( + .CK(n_0_76), .D(n_0_49), .Q(mem_wdata[16]), .QN() + ); + NOR4_X1_LVT i_0_0_110( + .A1(n_0_0_95), .A2(n_0_0_87), .A3(n_0_0_92), .A4(n_0_0_91), .ZN(n_0_0_51) + ); + NOR3_X1_LVT i_0_0_109( + .A1(n_0_0_86), .A2(DAddr[0]), .A3(DWidth[0]), .ZN(n_0_0_50) + ); + AND2_X1_LVT i_0_0_108( + .A1(n_0_0_88), .A2(n_0_0_50), .ZN(n_0_0_49) + ); + OAI211_X1_LVT i_0_0_107( + .A(n_0_0_85), .B(n_0_0_89), .C1(DAddr[1]), .C2(DWidth[1]), .ZN(n_0_0_48) + ); + AOI222_X1_LVT i_0_0_106( + .A1(DWData[15]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[7]), .C1(n_0_0_48), + .C2(mem_wdata[15]), .ZN(n_0_0_47) + ); + INV_X1_LVT i_0_0_105( + .A(n_0_0_47), .ZN(n_0_50) + ); + DFF_X1_LVT \mem_wdata_reg[15] ( + .CK(n_0_76), .D(n_0_50), .Q(mem_wdata[15]), .QN() + ); + AOI222_X1_LVT i_0_0_104( + .A1(DWData[14]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[6]), .C1(n_0_0_48), + .C2(mem_wdata[14]), .ZN(n_0_0_46) + ); + INV_X1_LVT i_0_0_103( + .A(n_0_0_46), .ZN(n_0_51) + ); + DFF_X1_LVT \mem_wdata_reg[14] ( + .CK(n_0_76), .D(n_0_51), .Q(mem_wdata[14]), .QN() + ); + AOI222_X1_LVT i_0_0_102( + .A1(DWData[13]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[5]), .C1(n_0_0_48), + .C2(mem_wdata[13]), .ZN(n_0_0_45) + ); + INV_X1_LVT i_0_0_101( + .A(n_0_0_45), .ZN(n_0_52) + ); + DFF_X1_LVT \mem_wdata_reg[13] ( + .CK(n_0_76), .D(n_0_52), .Q(mem_wdata[13]), .QN() + ); + AOI222_X1_LVT i_0_0_100( + .A1(DWData[12]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[4]), .C1(n_0_0_48), + .C2(mem_wdata[12]), .ZN(n_0_0_44) + ); + INV_X1_LVT i_0_0_99( + .A(n_0_0_44), .ZN(n_0_53) + ); + DFF_X1_LVT \mem_wdata_reg[12] ( + .CK(n_0_76), .D(n_0_53), .Q(mem_wdata[12]), .QN() + ); + AOI222_X1_LVT i_0_0_98( + .A1(DWData[11]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[3]), .C1(n_0_0_48), + .C2(mem_wdata[11]), .ZN(n_0_0_43) + ); + INV_X1_LVT i_0_0_97( + .A(n_0_0_43), .ZN(n_0_54) + ); + DFF_X1_LVT \mem_wdata_reg[11] ( + .CK(n_0_76), .D(n_0_54), .Q(mem_wdata[11]), .QN() + ); + AOI222_X1_LVT i_0_0_96( + .A1(DWData[10]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[2]), .C1(n_0_0_48), + .C2(mem_wdata[10]), .ZN(n_0_0_42) + ); + INV_X1_LVT i_0_0_95( + .A(n_0_0_42), .ZN(n_0_55) + ); + DFF_X1_LVT \mem_wdata_reg[10] ( + .CK(n_0_76), .D(n_0_55), .Q(mem_wdata[10]), .QN() + ); + AOI222_X1_LVT i_0_0_94( + .A1(DWData[9]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[1]), .C1(n_0_0_48), + .C2(mem_wdata[9]), .ZN(n_0_0_41) + ); + INV_X1_LVT i_0_0_93( + .A(n_0_0_41), .ZN(n_0_56) + ); + DFF_X1_LVT \mem_wdata_reg[9] ( + .CK(n_0_76), .D(n_0_56), .Q(mem_wdata[9]), .QN() + ); + AOI222_X1_LVT i_0_0_92( + .A1(DWData[8]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[0]), .C1(n_0_0_48), + .C2(mem_wdata[8]), .ZN(n_0_0_40) + ); + INV_X1_LVT i_0_0_91( + .A(n_0_0_40), .ZN(n_0_57) + ); + DFF_X1_LVT \mem_wdata_reg[8] ( + .CK(n_0_76), .D(n_0_57), .Q(mem_wdata[8]), .QN() + ); + AOI21_X1_LVT i_0_0_90( + .A(n_0_0_87), .B1(n_0_0_83), .B2(n_0_0_93), .ZN(n_0_0_39) + ); + NAND2_X1_LVT i_0_0_89( + .A1(n_0_0_85), .A2(n_0_0_39), .ZN(n_0_0_38) + ); + MUX2_X1_LVT i_0_0_88( + .A(DWData[7]), .B(mem_wdata[7]), .S(n_0_0_38), .Z(n_0_58) + ); + DFF_X1_LVT \mem_wdata_reg[7] ( + .CK(n_0_76), .D(n_0_58), .Q(mem_wdata[7]), .QN() + ); + MUX2_X1_LVT i_0_0_87( + .A(DWData[6]), .B(mem_wdata[6]), .S(n_0_0_38), .Z(n_0_59) + ); + DFF_X1_LVT \mem_wdata_reg[6] ( + .CK(n_0_76), .D(n_0_59), .Q(mem_wdata[6]), .QN() + ); + MUX2_X1_LVT i_0_0_86( + .A(DWData[5]), .B(mem_wdata[5]), .S(n_0_0_38), .Z(n_0_60) + ); + DFF_X1_LVT \mem_wdata_reg[5] ( + .CK(n_0_76), .D(n_0_60), .Q(mem_wdata[5]), .QN() + ); + MUX2_X1_LVT i_0_0_85( + .A(DWData[4]), .B(mem_wdata[4]), .S(n_0_0_38), .Z(n_0_61) + ); + DFF_X1_LVT \mem_wdata_reg[4] ( + .CK(n_0_76), .D(n_0_61), .Q(mem_wdata[4]), .QN() + ); + MUX2_X1_LVT i_0_0_84( + .A(DWData[3]), .B(mem_wdata[3]), .S(n_0_0_38), .Z(n_0_62) + ); + DFF_X1_LVT \mem_wdata_reg[3] ( + .CK(n_0_76), .D(n_0_62), .Q(mem_wdata[3]), .QN() + ); + MUX2_X1_LVT i_0_0_83( + .A(DWData[2]), .B(mem_wdata[2]), .S(n_0_0_38), .Z(n_0_63) + ); + DFF_X1_LVT \mem_wdata_reg[2] ( + .CK(n_0_76), .D(n_0_63), .Q(mem_wdata[2]), .QN() + ); + MUX2_X1_LVT i_0_0_82( + .A(DWData[1]), .B(mem_wdata[1]), .S(n_0_0_38), .Z(n_0_64) + ); + DFF_X1_LVT \mem_wdata_reg[1] ( + .CK(n_0_76), .D(n_0_64), .Q(mem_wdata[1]), .QN() + ); + MUX2_X1_LVT i_0_0_81( + .A(DWData[0]), .B(mem_wdata[0]), .S(n_0_0_38), .Z(n_0_65) + ); + DFF_X1_LVT \mem_wdata_reg[0] ( + .CK(n_0_76), .D(n_0_65), .Q(mem_wdata[0]), .QN() + ); + MemGen_32_11 RAM( + .chip_en(), .clock(clk), .addr(mem_addr), .rd_data(mem_rdata), .rd_en(n_0), + .wr_en(DWE), .wr_data(mem_wdata) + ); + DFF_X1_LVT \drTmp_reg[31] ( + .CK(n_0_76), .D(mem_rdata[31]), .Q(drTmp[31]), .QN() + ); + AND2_X1_LVT i_0_0_80( + .A1(DWidth[1]), .A2(drTmp[31]), .ZN(n_0_42) + ); + DLH_X1_LVT \DRData[31] ( + .D(n_0_42), .G(n_0_43), .Q(DRData[31]) + ); + DFF_X1_LVT \drTmp_reg[30] ( + .CK(n_0_76), .D(mem_rdata[30]), .Q(drTmp[30]), .QN() + ); + AND2_X1_LVT i_0_0_79( + .A1(DWidth[1]), .A2(drTmp[30]), .ZN(n_0_41) + ); + DLH_X1_LVT \DRData[30] ( + .D(n_0_41), .G(n_0_43), .Q(DRData[30]) + ); + DFF_X1_LVT \drTmp_reg[29] ( + .CK(n_0_76), .D(mem_rdata[29]), .Q(drTmp[29]), .QN() + ); + AND2_X1_LVT i_0_0_78( + .A1(DWidth[1]), .A2(drTmp[29]), .ZN(n_0_40) + ); + DLH_X1_LVT \DRData[29] ( + .D(n_0_40), .G(n_0_43), .Q(DRData[29]) + ); + DFF_X1_LVT \drTmp_reg[28] ( + .CK(n_0_76), .D(mem_rdata[28]), .Q(drTmp[28]), .QN() + ); + AND2_X1_LVT i_0_0_77( + .A1(DWidth[1]), .A2(drTmp[28]), .ZN(n_0_39) + ); + DLH_X1_LVT \DRData[28] ( + .D(n_0_39), .G(n_0_43), .Q(DRData[28]) + ); + DFF_X1_LVT \drTmp_reg[27] ( + .CK(n_0_76), .D(mem_rdata[27]), .Q(drTmp[27]), .QN() + ); + AND2_X1_LVT i_0_0_76( + .A1(DWidth[1]), .A2(drTmp[27]), .ZN(n_0_38) + ); + DLH_X1_LVT \DRData[27] ( + .D(n_0_38), .G(n_0_43), .Q(DRData[27]) + ); + DFF_X1_LVT \drTmp_reg[26] ( + .CK(n_0_76), .D(mem_rdata[26]), .Q(drTmp[26]), .QN() + ); + AND2_X1_LVT i_0_0_75( + .A1(DWidth[1]), .A2(drTmp[26]), .ZN(n_0_37) + ); + DLH_X1_LVT \DRData[26] ( + .D(n_0_37), .G(n_0_43), .Q(DRData[26]) + ); + DFF_X1_LVT \drTmp_reg[25] ( + .CK(n_0_76), .D(mem_rdata[25]), .Q(drTmp[25]), .QN() + ); + AND2_X1_LVT i_0_0_74( + .A1(DWidth[1]), .A2(drTmp[25]), .ZN(n_0_36) + ); + DLH_X1_LVT \DRData[25] ( + .D(n_0_36), .G(n_0_43), .Q(DRData[25]) + ); + DFF_X1_LVT \drTmp_reg[24] ( + .CK(n_0_76), .D(mem_rdata[24]), .Q(drTmp[24]), .QN() + ); + AND2_X1_LVT i_0_0_73( + .A1(DWidth[1]), .A2(drTmp[24]), .ZN(n_0_35) + ); + DLH_X1_LVT \DRData[24] ( + .D(n_0_35), .G(n_0_43), .Q(DRData[24]) + ); + DFF_X1_LVT \drTmp_reg[23] ( + .CK(n_0_76), .D(mem_rdata[23]), .Q(drTmp[23]), .QN() + ); + AND2_X1_LVT i_0_0_72( + .A1(DWidth[1]), .A2(drTmp[23]), .ZN(n_0_34) + ); + DLH_X1_LVT \DRData[23] ( + .D(n_0_34), .G(n_0_43), .Q(DRData[23]) + ); + DFF_X1_LVT \drTmp_reg[22] ( + .CK(n_0_76), .D(mem_rdata[22]), .Q(drTmp[22]), .QN() + ); + AND2_X1_LVT i_0_0_71( + .A1(DWidth[1]), .A2(drTmp[22]), .ZN(n_0_33) + ); + DLH_X1_LVT \DRData[22] ( + .D(n_0_33), .G(n_0_43), .Q(DRData[22]) + ); + DFF_X1_LVT \drTmp_reg[21] ( + .CK(n_0_76), .D(mem_rdata[21]), .Q(drTmp[21]), .QN() + ); + AND2_X1_LVT i_0_0_70( + .A1(DWidth[1]), .A2(drTmp[21]), .ZN(n_0_32) + ); + DLH_X1_LVT \DRData[21] ( + .D(n_0_32), .G(n_0_43), .Q(DRData[21]) + ); + DFF_X1_LVT \drTmp_reg[20] ( + .CK(n_0_76), .D(mem_rdata[20]), .Q(drTmp[20]), .QN() + ); + AND2_X1_LVT i_0_0_69( + .A1(DWidth[1]), .A2(drTmp[20]), .ZN(n_0_31) + ); + DLH_X1_LVT \DRData[20] ( + .D(n_0_31), .G(n_0_43), .Q(DRData[20]) + ); + DFF_X1_LVT \drTmp_reg[19] ( + .CK(n_0_76), .D(mem_rdata[19]), .Q(drTmp[19]), .QN() + ); + AND2_X1_LVT i_0_0_68( + .A1(DWidth[1]), .A2(drTmp[19]), .ZN(n_0_30) + ); + DLH_X1_LVT \DRData[19] ( + .D(n_0_30), .G(n_0_43), .Q(DRData[19]) + ); + DFF_X1_LVT \drTmp_reg[18] ( + .CK(n_0_76), .D(mem_rdata[18]), .Q(drTmp[18]), .QN() + ); + AND2_X1_LVT i_0_0_67( + .A1(DWidth[1]), .A2(drTmp[18]), .ZN(n_0_29) + ); + DLH_X1_LVT \DRData[18] ( + .D(n_0_29), .G(n_0_43), .Q(DRData[18]) + ); + DFF_X1_LVT \drTmp_reg[17] ( + .CK(n_0_76), .D(mem_rdata[17]), .Q(drTmp[17]), .QN() + ); + AND2_X1_LVT i_0_0_66( + .A1(DWidth[1]), .A2(drTmp[17]), .ZN(n_0_28) + ); + DLH_X1_LVT \DRData[17] ( + .D(n_0_28), .G(n_0_43), .Q(DRData[17]) + ); + DFF_X1_LVT \drTmp_reg[16] ( + .CK(n_0_76), .D(mem_rdata[16]), .Q(drTmp[16]), .QN() + ); + AND2_X1_LVT i_0_0_65( + .A1(DWidth[1]), .A2(drTmp[16]), .ZN(n_0_27) + ); + DLH_X1_LVT \DRData[16] ( + .D(n_0_27), .G(n_0_43), .Q(DRData[16]) + ); + NOR2_X1_LVT i_0_0_64( + .A1(n_0_0_91), .A2(n_0_0_87), .ZN(n_0_0_37) + ); + DFF_X1_LVT \drTmp_reg[15] ( + .CK(n_0_76), .D(mem_rdata[15]), .Q(drTmp[15]), .QN() + ); + AOI22_X1_LVT i_0_0_63( + .A1(drTmp[31]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[15]), .ZN(n_0_0_36) + ); + INV_X1_LVT i_0_0_62( + .A(n_0_0_36), .ZN(n_0_26) + ); + DLH_X1_LVT \DRData[15] ( + .D(n_0_26), .G(n_0_43), .Q(DRData[15]) + ); + DFF_X1_LVT \drTmp_reg[14] ( + .CK(n_0_76), .D(mem_rdata[14]), .Q(drTmp[14]), .QN() + ); + AOI22_X1_LVT i_0_0_61( + .A1(drTmp[30]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[14]), .ZN(n_0_0_35) + ); + INV_X1_LVT i_0_0_60( + .A(n_0_0_35), .ZN(n_0_25) + ); + DLH_X1_LVT \DRData[14] ( + .D(n_0_25), .G(n_0_43), .Q(DRData[14]) + ); + DFF_X1_LVT \drTmp_reg[13] ( + .CK(n_0_76), .D(mem_rdata[13]), .Q(drTmp[13]), .QN() + ); + AOI22_X1_LVT i_0_0_59( + .A1(drTmp[29]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[13]), .ZN(n_0_0_34) + ); + INV_X1_LVT i_0_0_58( + .A(n_0_0_34), .ZN(n_0_24) + ); + DLH_X1_LVT \DRData[13] ( + .D(n_0_24), .G(n_0_43), .Q(DRData[13]) + ); + DFF_X1_LVT \drTmp_reg[12] ( + .CK(n_0_76), .D(mem_rdata[12]), .Q(drTmp[12]), .QN() + ); + AOI22_X1_LVT i_0_0_57( + .A1(drTmp[28]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[12]), .ZN(n_0_0_33) + ); + INV_X1_LVT i_0_0_56( + .A(n_0_0_33), .ZN(n_0_23) + ); + DLH_X1_LVT \DRData[12] ( + .D(n_0_23), .G(n_0_43), .Q(DRData[12]) + ); + DFF_X1_LVT \drTmp_reg[11] ( + .CK(n_0_76), .D(mem_rdata[11]), .Q(drTmp[11]), .QN() + ); + AOI22_X1_LVT i_0_0_55( + .A1(drTmp[27]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[11]), .ZN(n_0_0_32) + ); + INV_X1_LVT i_0_0_54( + .A(n_0_0_32), .ZN(n_0_22) + ); + DLH_X1_LVT \DRData[11] ( + .D(n_0_22), .G(n_0_43), .Q(DRData[11]) + ); + DFF_X1_LVT \drTmp_reg[10] ( + .CK(n_0_76), .D(mem_rdata[10]), .Q(drTmp[10]), .QN() + ); + AOI22_X1_LVT i_0_0_53( + .A1(drTmp[26]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[10]), .ZN(n_0_0_31) + ); + INV_X1_LVT i_0_0_52( + .A(n_0_0_31), .ZN(n_0_21) + ); + DLH_X1_LVT \DRData[10] ( + .D(n_0_21), .G(n_0_43), .Q(DRData[10]) + ); + DFF_X1_LVT \drTmp_reg[9] ( + .CK(n_0_76), .D(mem_rdata[9]), .Q(drTmp[9]), .QN() + ); + AOI22_X1_LVT i_0_0_51( + .A1(drTmp[25]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[9]), .ZN(n_0_0_30) + ); + INV_X1_LVT i_0_0_50( + .A(n_0_0_30), .ZN(n_0_20) + ); + DLH_X1_LVT \DRData[9] ( + .D(n_0_20), .G(n_0_43), .Q(DRData[9]) + ); + DFF_X1_LVT \drTmp_reg[8] ( + .CK(n_0_76), .D(mem_rdata[8]), .Q(drTmp[8]), .QN() + ); + AOI22_X1_LVT i_0_0_49( + .A1(drTmp[24]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[8]), .ZN(n_0_0_29) + ); + INV_X1_LVT i_0_0_48( + .A(n_0_0_29), .ZN(n_0_19) + ); + DLH_X1_LVT \DRData[8] ( + .D(n_0_19), .G(n_0_43), .Q(DRData[8]) + ); + AOI22_X1_LVT i_0_0_46( + .A1(drTmp[31]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[15]), .ZN(n_0_0_27) + ); + AOI211_X1_LVT i_0_0_47( + .A(DAddr[1]), .B(n_0_0_83), .C1(n_0_0_94), .C2(DWidth[1]), .ZN(n_0_0_28) + ); + DFF_X1_LVT \drTmp_reg[7] ( + .CK(n_0_76), .D(mem_rdata[7]), .Q(drTmp[7]), .QN() + ); + AOI22_X1_LVT i_0_0_45( + .A1(drTmp[23]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[7]), .ZN(n_0_0_26) + ); + NAND2_X1_LVT i_0_0_44( + .A1(n_0_0_27), .A2(n_0_0_26), .ZN(n_0_18) + ); + DLH_X1_LVT \DRData[7] ( + .D(n_0_18), .G(n_0_43), .Q(DRData[7]) + ); + AOI22_X1_LVT i_0_0_43( + .A1(drTmp[30]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[14]), .ZN(n_0_0_25) + ); + DFF_X1_LVT \drTmp_reg[6] ( + .CK(n_0_76), .D(mem_rdata[6]), .Q(drTmp[6]), .QN() + ); + AOI22_X1_LVT i_0_0_42( + .A1(drTmp[22]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[6]), .ZN(n_0_0_24) + ); + NAND2_X1_LVT i_0_0_41( + .A1(n_0_0_25), .A2(n_0_0_24), .ZN(n_0_17) + ); + DLH_X1_LVT \DRData[6] ( + .D(n_0_17), .G(n_0_43), .Q(DRData[6]) + ); + AOI22_X1_LVT i_0_0_40( + .A1(drTmp[29]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[13]), .ZN(n_0_0_23) + ); + DFF_X1_LVT \drTmp_reg[5] ( + .CK(n_0_76), .D(mem_rdata[5]), .Q(drTmp[5]), .QN() + ); + AOI22_X1_LVT i_0_0_39( + .A1(drTmp[21]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[5]), .ZN(n_0_0_22) + ); + NAND2_X1_LVT i_0_0_38( + .A1(n_0_0_23), .A2(n_0_0_22), .ZN(n_0_16) + ); + DLH_X1_LVT \DRData[5] ( + .D(n_0_16), .G(n_0_43), .Q(DRData[5]) + ); + AOI22_X1_LVT i_0_0_37( + .A1(drTmp[28]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[12]), .ZN(n_0_0_21) + ); + DFF_X1_LVT \drTmp_reg[4] ( + .CK(n_0_76), .D(mem_rdata[4]), .Q(drTmp[4]), .QN() + ); + AOI22_X1_LVT i_0_0_36( + .A1(drTmp[20]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[4]), .ZN(n_0_0_20) + ); + NAND2_X1_LVT i_0_0_35( + .A1(n_0_0_21), .A2(n_0_0_20), .ZN(n_0_15) + ); + DLH_X1_LVT \DRData[4] ( + .D(n_0_15), .G(n_0_43), .Q(DRData[4]) + ); + AOI22_X1_LVT i_0_0_34( + .A1(drTmp[27]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[11]), .ZN(n_0_0_19) + ); + DFF_X1_LVT \drTmp_reg[3] ( + .CK(n_0_76), .D(mem_rdata[3]), .Q(drTmp[3]), .QN() + ); + AOI22_X1_LVT i_0_0_33( + .A1(drTmp[19]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[3]), .ZN(n_0_0_18) + ); + NAND2_X1_LVT i_0_0_32( + .A1(n_0_0_19), .A2(n_0_0_18), .ZN(n_0_14) + ); + DLH_X1_LVT \DRData[3] ( + .D(n_0_14), .G(n_0_43), .Q(DRData[3]) + ); + AOI22_X1_LVT i_0_0_31( + .A1(drTmp[26]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[10]), .ZN(n_0_0_17) + ); + DFF_X1_LVT \drTmp_reg[2] ( + .CK(n_0_76), .D(mem_rdata[2]), .Q(drTmp[2]), .QN() + ); + AOI22_X1_LVT i_0_0_30( + .A1(drTmp[18]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[2]), .ZN(n_0_0_16) + ); + NAND2_X1_LVT i_0_0_29( + .A1(n_0_0_17), .A2(n_0_0_16), .ZN(n_0_13) + ); + DLH_X1_LVT \DRData[2] ( + .D(n_0_13), .G(n_0_43), .Q(DRData[2]) + ); + AOI22_X1_LVT i_0_0_28( + .A1(drTmp[25]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[9]), .ZN(n_0_0_15) + ); + DFF_X1_LVT \drTmp_reg[1] ( + .CK(n_0_76), .D(mem_rdata[1]), .Q(drTmp[1]), .QN() + ); + AOI22_X1_LVT i_0_0_27( + .A1(drTmp[17]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[1]), .ZN(n_0_0_14) + ); + NAND2_X1_LVT i_0_0_26( + .A1(n_0_0_15), .A2(n_0_0_14), .ZN(n_0_12) + ); + DLH_X1_LVT \DRData[1] ( + .D(n_0_12), .G(n_0_43), .Q(DRData[1]) + ); + AOI22_X1_LVT i_0_0_25( + .A1(drTmp[24]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[8]), .ZN(n_0_0_13) + ); + DFF_X1_LVT \drTmp_reg[0] ( + .CK(n_0_76), .D(mem_rdata[0]), .Q(drTmp[0]), .QN() + ); + AOI22_X1_LVT i_0_0_24( + .A1(drTmp[16]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[0]), .ZN(n_0_0_12) + ); + NAND2_X1_LVT i_0_0_23( + .A1(n_0_0_13), .A2(n_0_0_12), .ZN(n_0_11) + ); + DLH_X1_LVT \DRData[0] ( + .D(n_0_11), .G(n_0_43), .Q(DRData[0]) + ); + DFF_X1_LVT \IRData_reg[31] ( + .CK(clk), .D(mem_rdata[31]), .Q(IRData[31]), .QN() + ); + DFF_X1_LVT \IRData_reg[30] ( + .CK(clk), .D(mem_rdata[30]), .Q(IRData[30]), .QN() + ); + DFF_X1_LVT \IRData_reg[29] ( + .CK(clk), .D(mem_rdata[29]), .Q(IRData[29]), .QN() + ); + DFF_X1_LVT \IRData_reg[28] ( + .CK(clk), .D(mem_rdata[28]), .Q(IRData[28]), .QN() + ); + DFF_X1_LVT \IRData_reg[27] ( + .CK(clk), .D(mem_rdata[27]), .Q(IRData[27]), .QN() + ); + DFF_X1_LVT \IRData_reg[26] ( + .CK(clk), .D(mem_rdata[26]), .Q(IRData[26]), .QN() + ); + DFF_X1_LVT \IRData_reg[25] ( + .CK(clk), .D(mem_rdata[25]), .Q(IRData[25]), .QN() + ); + DFF_X1_LVT \IRData_reg[24] ( + .CK(clk), .D(mem_rdata[24]), .Q(IRData[24]), .QN() + ); + DFF_X1_LVT \IRData_reg[23] ( + .CK(clk), .D(mem_rdata[23]), .Q(IRData[23]), .QN() + ); + DFF_X1_LVT \IRData_reg[22] ( + .CK(clk), .D(mem_rdata[22]), .Q(IRData[22]), .QN() + ); + DFF_X1_LVT \IRData_reg[21] ( + .CK(clk), .D(mem_rdata[21]), .Q(IRData[21]), .QN() + ); + DFF_X1_LVT \IRData_reg[20] ( + .CK(clk), .D(mem_rdata[20]), .Q(IRData[20]), .QN() + ); + DFF_X1_LVT \IRData_reg[19] ( + .CK(clk), .D(mem_rdata[19]), .Q(IRData[19]), .QN() + ); + DFF_X1_LVT \IRData_reg[18] ( + .CK(clk), .D(mem_rdata[18]), .Q(IRData[18]), .QN() + ); + DFF_X1_LVT \IRData_reg[17] ( + .CK(clk), .D(mem_rdata[17]), .Q(IRData[17]), .QN() + ); + DFF_X1_LVT \IRData_reg[16] ( + .CK(clk), .D(mem_rdata[16]), .Q(IRData[16]), .QN() + ); + DFF_X1_LVT \IRData_reg[15] ( + .CK(clk), .D(mem_rdata[15]), .Q(IRData[15]), .QN() + ); + DFF_X1_LVT \IRData_reg[14] ( + .CK(clk), .D(mem_rdata[14]), .Q(IRData[14]), .QN() + ); + DFF_X1_LVT \IRData_reg[13] ( + .CK(clk), .D(mem_rdata[13]), .Q(IRData[13]), .QN() + ); + DFF_X1_LVT \IRData_reg[12] ( + .CK(clk), .D(mem_rdata[12]), .Q(IRData[12]), .QN() + ); + DFF_X1_LVT \IRData_reg[11] ( + .CK(clk), .D(mem_rdata[11]), .Q(IRData[11]), .QN() + ); + DFF_X1_LVT \IRData_reg[10] ( + .CK(clk), .D(mem_rdata[10]), .Q(IRData[10]), .QN() + ); + DFF_X1_LVT \IRData_reg[9] ( + .CK(clk), .D(mem_rdata[9]), .Q(IRData[9]), .QN() + ); + DFF_X1_LVT \IRData_reg[8] ( + .CK(clk), .D(mem_rdata[8]), .Q(IRData[8]), .QN() + ); + DFF_X1_LVT \IRData_reg[7] ( + .CK(clk), .D(mem_rdata[7]), .Q(IRData[7]), .QN() + ); + DFF_X1_LVT \IRData_reg[6] ( + .CK(clk), .D(mem_rdata[6]), .Q(IRData[6]), .QN() + ); + DFF_X1_LVT \IRData_reg[5] ( + .CK(clk), .D(mem_rdata[5]), .Q(IRData[5]), .QN() + ); + DFF_X1_LVT \IRData_reg[4] ( + .CK(clk), .D(mem_rdata[4]), .Q(IRData[4]), .QN() + ); + DFF_X1_LVT \IRData_reg[3] ( + .CK(clk), .D(mem_rdata[3]), .Q(IRData[3]), .QN() + ); + DFF_X1_LVT \IRData_reg[2] ( + .CK(clk), .D(mem_rdata[2]), .Q(IRData[2]), .QN() + ); + DFF_X1_LVT \IRData_reg[1] ( + .CK(clk), .D(mem_rdata[1]), .Q(IRData[1]), .QN() + ); + DFF_X1_LVT \IRData_reg[0] ( + .CK(clk), .D(mem_rdata[0]), .Q(IRData[0]), .QN() + ); +endmodule + +module reg_file(Rs1, Rs2, Rd, RRs1, RRs2, WRd, WrReg, reset, clk, dftIn, ts_intno31, + ts_no1050, ts_no1051, ts_no1053, ts_no1054, ts_extsi1226, ts_extsi1227, + ts_extsi1228); + input [31:0] WRd; + input [4:0] Rs1, Rs2, Rd; + input WrReg, reset, clk, dftIn, ts_extsi1227, ts_extsi1228, ts_intno31, + ts_extsi1226; + output [31:0] RRs1, RRs2; + output ts_no1050, ts_no1051, ts_no1053, ts_no1054; + + wire [31:0] registers_1__ap, registers_2__ap, registers_3__ap, + registers_4__ap, registers_5__ap, registers_6__ap, + registers_7__ap, registers_8__ap, registers_9__ap, + registers_10__ap, registers_11__ap, registers_12__ap, + registers_13__ap, registers_14__ap, registers_15__ap, + registers_16__ap, registers_17__ap, registers_18__ap, + registers_19__ap, registers_20__ap, registers_21__ap, + registers_22__ap, registers_23__ap, registers_24__ap, + registers_25__ap, registers_26__ap, registers_27__ap, + registers_28__ap, registers_29__ap, registers_30__ap, + registers_31__ap, registers; + wire n_0_0, n_0_32, n_0_33, n_0_34, n_0_35, n_0_36, n_0_37, n_0_38, n_0_39, + n_0_40, n_0_41, n_0_42, n_0_43, n_0_44, n_0_45, n_0_46, n_0_47, n_0_48, + n_0_49, n_0_50, n_0_51, n_0_52, n_0_53, n_0_54, n_0_55, n_0_56, n_0_57, + n_0_58, n_0_59, n_0_60, n_0_61, n_0_31, n_0_30, n_0_29, n_0_28, n_0_27, + n_0_26, n_0_25, n_0_24, n_0_0_0, n_0_0_1, n_0_23, n_0_22, n_0_21, + n_0_20, n_0_19, n_0_18, n_0_17, n_0_16, n_0_0_2, n_0_0_3, n_0_15, + n_0_14, n_0_13, n_0_12, n_0_11, n_0_10, n_0_9, n_0_8, n_0_0_4, n_0_0_5, + n_0_7, n_0_0_6, n_0_6, n_0_0_7, n_0_5, n_0_0_8, n_0_4, n_0_0_9, + n_0_0_10, n_0_3, n_0_0_11, n_0_2, n_0_0_12, n_0_1, n_0_0_13, n_0_0_14, + n_0_0_15, n_0_0_16, n_0_0_17, n_0_0_18, n_0_0_19, n_0_0_20, n_1_0_0, + n_1_0_1, n_1_0_2, n_1_0_3, n_1_0_4, n_1_0_5, n_1_0_6, n_1_0_7, n_1_0_8, + n_1_0_9, n_1_0_10, n_1_0_11, n_1_0_12, n_1_0_13, n_1_0_14, n_1_0_15, + n_1_0_16, n_1_0_17, n_1_0_18, n_1_0_19, n_1_0_20, n_1_0_21, n_1_0_22, + n_1_0_23, n_1_0_24, n_1_0_25, n_1_0_26, n_1_0_27, n_1_0_28, n_1_0_29, + n_1_0_30, n_1_0_31, n_1_0_32, n_1_0_33, n_1_0_34, n_1_0_35, n_1_0_36, + n_1_0_37, n_1_0_38, n_1_0_39, n_1_0_40, n_1_0_41, n_1_0_42, n_1_0_43, + n_1_0_44, n_1_0_45, n_1_0_46, n_1_0_47, n_1_0_48, n_1_0_49, n_1_0_50, + n_1_0_51, n_1_0_52, n_1_0_53, n_1_0_54, n_1_0_55, n_1_0_56, n_1_0_57, + n_1_0_58, n_1_0_59, n_1_0_60, n_1_0_61, n_1_0_62, n_1_0_63, n_1_0_64, + n_1_0_65, n_1_0_66, n_1_0_67, n_1_0_68, n_1_0_69, n_1_0_70, n_1_0_71, + n_1_0_72, n_1_0_73, n_1_0_74, n_1_0_75, n_1_0_76, n_1_0_77, n_1_0_78, + n_1_0_79, n_1_0_80, n_1_0_81, n_1_0_82, n_1_0_83, n_1_0_84, n_1_0_85, + n_1_0_86, n_1_0_87, n_1_0_88, n_1_0_89, n_1_0_90, n_1_0_91, n_1_0_92, + n_1_0_93, n_1_0_94, n_1_0_95, n_1_0_96, n_1_0_97, n_1_0_98, n_1_0_99, + n_1_0_100, n_1_0_101, n_1_0_102, n_1_0_103, n_1_0_104, n_1_0_105, + n_1_0_106, n_1_0_107, n_1_0_108, n_1_0_109, n_1_0_110, n_1_0_111, + n_1_0_112, n_1_0_113, n_1_0_114, n_1_0_115, n_1_0_116, n_1_0_117, + n_1_0_118, n_1_0_119, n_1_0_120, n_1_0_121, n_1_0_122, n_1_0_123, + n_1_0_124, n_1_0_125, n_1_0_126, n_1_0_127, n_1_0_128, n_1_0_129, + n_1_0_130, n_1_0_131, n_1_0_132, n_1_0_133, n_1_0_134, n_1_0_135, + n_1_0_136, n_1_0_137, n_1_0_138, n_1_0_139, n_1_0_140, n_1_0_141, + n_1_0_142, n_1_0_143, n_1_0_144, n_1_0_145, n_1_0_146, n_1_0_147, + n_1_0_148, n_1_0_149, n_1_0_150, n_1_0_151, n_1_0_152, n_1_0_153, + n_1_0_154, n_1_0_155, n_1_0_156, n_1_0_157, n_1_0_158, n_1_0_159, + n_1_0_160, n_1_0_161, n_1_0_162, n_1_0_163, n_1_0_164, n_1_0_165, + n_1_0_166, n_1_0_167, n_1_0_168, n_1_0_169, n_1_0_170, n_1_0_171, + n_1_0_172, n_1_0_173, n_1_0_174, n_1_0_175, n_1_0_176, n_1_0_177, + n_1_0_178, n_1_0_179, n_1_0_180, n_1_0_181, n_1_0_182, n_1_0_183, + n_1_0_184, n_1_0_185, n_1_0_186, n_1_0_187, n_1_0_188, n_1_0_189, + n_1_0_190, n_1_0_191, n_1_0_192, n_1_0_193, n_1_0_194, n_1_0_195, + n_1_0_196, n_1_0_197, n_1_0_198, n_1_0_199, n_1_0_200, n_1_0_201, + n_1_0_202, n_1_0_203, n_1_0_204, n_1_0_205, n_1_0_206, n_1_0_207, + n_1_0_208, n_1_0_209, n_1_0_210, n_1_0_211, n_1_0_212, n_1_0_213, + n_1_0_214, n_1_0_215, n_1_0_216, n_1_0_217, n_1_0_218, n_1_0_219, + n_1_0_220, n_1_0_221, n_1_0_222, n_1_0_223, n_1_0_224, n_1_0_225, + n_1_0_226, n_1_0_227, n_1_0_228, n_1_0_229, n_1_0_230, n_1_0_231, + n_1_0_232, n_1_0_233, n_1_0_234, n_1_0_235, n_1_0_236, n_1_0_237, + n_1_0_238, n_1_0_239, n_1_0_240, n_1_0_241, n_1_0_242, n_1_0_243, + n_1_0_244, n_1_0_245, n_1_0_246, n_1_0_247, n_1_0_248, n_1_0_249, + n_1_0_250, n_1_0_251, n_1_0_252, n_1_0_253, n_1_0_254, n_1_0_255, + n_1_0_256, n_1_0_257, n_1_0_258, n_1_0_259, n_1_0_260, n_1_0_261, + n_1_0_262, n_1_0_263, n_1_0_264, n_1_0_265, n_1_0_266, n_1_0_267, + n_1_0_268, n_1_0_269, n_1_0_270, n_1_0_271, n_1_0_272, n_1_0_273, + n_1_0_274, n_1_0_275, n_1_0_276, n_1_0_277, n_1_0_278, n_1_0_279, + n_1_0_280, n_1_0_281, n_1_0_282, n_1_0_283, n_1_0_284, n_1_0_285, + n_1_0_286, n_1_0_287, n_1_0_288, n_1_0_289, n_1_0_290, n_1_0_291, + n_1_0_292, n_1_0_293, n_1_0_294, n_1_0_295, n_1_0_296, n_1_0_297, + n_1_0_298, n_1_0_299, n_1_0_300, n_1_0_301, n_1_0_302, n_1_0_303, + n_1_0_304, n_1_0_305, n_1_0_306, n_1_0_307, n_1_0_308, n_1_0_309, + n_1_0_310, n_1_0_311, n_1_0_312, n_1_0_313, n_1_0_314, n_1_0_315, + n_1_0_316, n_1_0_317, n_1_0_318, n_1_0_319, n_1_0_320, n_1_0_321, + n_1_0_322, n_1_0_323, n_1_0_324, n_1_0_325, n_1_0_326, n_1_0_327, + n_1_0_328, n_1_0_329, n_1_0_330, n_1_0_331, n_1_0_332, n_1_0_333, + n_1_0_334, n_1_0_335, n_1_0_336, n_1_0_337, n_1_0_338, n_1_0_339, + n_1_0_340, n_1_0_341, n_1_0_342, n_1_0_343, n_1_0_344, n_1_0_345, + n_1_0_346, n_1_0_347, n_1_0_348, n_1_0_349, n_1_0_350, n_1_0_351, + n_1_0_352, n_1_0_353, n_1_0_354, n_1_0_355, n_1_0_356, n_1_0_357, + n_1_0_358, n_1_0_359, n_1_0_360, n_1_0_361, n_1_0_362, n_1_0_363, + n_1_0_364, n_1_0_365, n_1_0_366, n_1_0_367, n_1_0_368, n_1_0_369, + n_1_0_370, n_1_0_371, n_1_0_372, n_1_0_373, n_1_0_374, n_1_0_375, + n_1_0_376, n_1_0_377, n_1_0_378, n_1_0_379, n_1_0_380, n_1_0_381, + n_1_0_382, n_1_0_383, n_1_0_384, n_1_0_385, n_1_0_386, n_1_0_387, + n_1_0_388, n_1_0_389, n_1_0_390, n_1_0_391, n_1_0_392, n_1_0_393, + n_1_0_394, n_1_0_395, n_1_0_396, n_1_0_397, n_1_0_398, n_1_0_399, + n_1_0_400, n_1_0_401, n_1_0_402, n_1_0_403, n_1_0_404, n_1_0_405, + n_1_0_406, n_1_0_407, n_1_0_408, n_1_0_409, n_1_0_410, n_1_0_411, + n_1_0_412, n_1_0_413, n_1_0_414, n_1_0_415, n_1_0_416, n_1_0_417, + n_1_0_418, n_1_0_419, n_1_0_420, n_1_0_421, n_1_0_422, n_1_0_423, + n_1_0_424, n_1_0_425, n_1_0_426, n_1_0_427, n_1_0_428, n_1_0_429, + n_1_0_430, n_1_0_431, n_1_0_432, n_1_0_433, n_1_0_434, n_1_0_435, + n_1_0_436, n_1_0_437, n_1_0_438, n_1_0_439, n_1_0_440, n_1_0_441, + n_1_0_442, n_1_0_443, n_1_0_444, n_1_0_445, n_1_0_446, n_1_0_447, + n_1_0_448, n_1_0_449, n_1_0_450, n_1_0_451, n_1_0_452, n_1_0_453, + n_1_0_454, n_1_0_455, n_1_0_456, n_1_0_457, n_1_0_458, n_1_0_459, + n_1_0_460, n_1_0_461, n_1_0_462, n_1_0_463, n_1_0_464, n_1_0_465, + n_1_0_466, n_1_0_467, n_1_0_468, n_1_0_469, n_1_0_470, n_1_0_471, + n_1_0_472, n_1_0_473, n_1_0_474, n_1_0_475, n_1_0_476, n_1_0_477, + n_1_0_478, n_1_0_479, n_1_0_480, n_1_0_481, n_1_0_482, n_1_0_483, + n_1_0_484, n_1_0_485, n_1_0_486, n_1_0_487, n_1_0_488, n_1_0_489, + n_1_0_490, n_1_0_491, n_1_0_492, n_1_0_493, n_1_0_494, n_1_0_495, + n_1_0_496, n_1_0_497, n_1_0_498, n_1_0_499, n_1_0_500, n_1_0_501, + n_1_0_502, n_1_0_503, n_1_0_504, n_1_0_505, n_1_0_506, n_1_0_507, + n_1_0_508, n_1_0_509, n_1_0_510, n_1_0_511, n_1_0_512, n_1_0_513, + n_1_0_514, n_1_0_515, n_1_0_516, n_1_0_517, n_1_0_518, n_1_0_519, + n_1_0_520, n_1_0_521, n_1_0_522, n_1_0_523, n_1_0_524, n_1_0_525, + n_1_0_526, n_1_0_527, n_1_0_528, n_1_0_529, n_1_0_530, n_1_0_531, + n_1_0_532, n_1_0_533, n_1_0_534, n_1_0_535, n_1_0_536, n_1_0_537, + n_1_0_538, n_1_0_539, n_1_0_540, n_1_0_541, n_1_0_542, n_1_0_543, + n_1_0_544, n_1_0_545, n_1_0_546, n_1_0_547, n_1_0_548, n_1_0_549, + n_1_0_550, n_1_0_551, n_1_0_552, n_1_0_553, n_1_0_554, n_1_0_555, + n_1_0_556, n_1_0_557, n_1_0_558, n_1_0_559, n_1_0_560, n_1_0_561, + n_1_0_562, n_1_0_563, n_1_0_564, n_1_0_565, n_1_0_566, n_1_0_567, + n_1_0_568, n_1_0_569, n_1_0_570, n_1_0_571, n_1_0_572, n_1_0_573, + n_1_0_574, n_1_0_575, n_1_0_576, n_1_0_577, n_1_0_578, n_1_0_579, + n_1_0_580, n_1_0_581, n_1_0_582, n_1_0_583, n_1_0_584, n_1_0_585, + n_1_0_586, n_1_0_587, n_1_0_588, n_1_0_589, n_1_0_590, n_1_0_591, + n_1_0_592, n_1_0_593, n_1_0_594, n_1_0_595, n_1_0_596, n_1_0_597, + n_1_0_598, n_1_0_599, n_1_0_600, n_1_0_601, n_1_0_602, n_1_0_603, + n_1_0_604, n_1_0_605, n_1_0_606, n_1_0_607, n_1_0_608, n_1_0_609, + n_1_0_610, n_1_0_611, n_1_0_612, n_1_0_613, n_1_0_614, n_1_0_615, + n_1_0_616, n_1_0_617, n_1_0_618, n_1_0_619, n_1_0_620, n_1_0_621, + n_1_0_622, n_1_0_623, n_1_0_624, n_1_0_625, n_1_0_626, n_1_0_627, + n_1_0_628, n_1_0_629, n_1_0_630, n_1_0_631, n_1_0_632, n_1_0_633, + n_1_0_634, n_1_0_635, n_1_0_636, n_1_0_637, n_1_0_638, n_1_0_639, + n_1_0_640, n_1_0_641, n_1_0_642, n_1_0_643, n_1_0_644, n_1_0_645, + n_1_0_646, n_1_0_647, n_1_0_648, n_1_0_649, n_1_0_650, n_1_0_651, + n_1_0_652, n_1_0_653, n_1_0_654, n_1_0_655, n_1_0_656, n_1_0_657, + n_1_0_658, n_1_0_659, n_1_0_660, n_1_0_661, n_1_0_662, n_1_0_663, + n_1_0_664, n_1_0_665, n_1_0_666, n_1_0_667, n_1_0_668, n_1_0_669, + n_1_0_670, n_1_0_671, n_1_0_672, n_1_0_673, n_1_0_674, n_1_0_675, + n_1_0_676, n_1_0_677, n_1_0_678, n_1_0_679, n_1_0_680, n_1_0_681, + n_1_0_682, n_1_0_683, n_1_0_684, n_1_0_685, n_1_0_686, n_1_0_687, + n_1_0_688, n_1_0_689, n_1_0_690, n_1_0_691, n_1_0_692, n_1_0_693, + n_1_0_694, n_1_0_695, n_1_0_696, n_1_0_697, n_1_0_698, n_1_0_699, + n_1_0_700, n_1_0_701, n_1_0_702, n_1_0_703, n_1_0_704, n_1_0_705, + n_1_0_706, n_1_0_707, n_1_0_708, n_1_0_709, n_1_0_710, n_1_0_711, + n_1_0_712, n_1_0_713, n_1_0_714, n_1_0_715, n_1_0_716, n_1_0_717, + n_1_0_718, n_1_0_719, n_1_0_720, n_1_0_721, n_1_0_722, n_1_0_723, + n_1_0_724, n_1_0_725, n_1_0_726, n_1_0_727, n_1_0_728, n_1_0_729, + n_1_0_730, n_1_0_731, n_1_0_732, n_1_0_733, n_1_0_734, n_1_0_735, + n_1_0_736, n_1_0_737, n_1_0_738, n_1_0_739, n_1_0_740, n_1_0_741, + n_1_0_742, n_1_0_743, n_1_0_744, n_1_0_745, n_1_0_746, n_1_0_747, + n_1_0_748, n_1_0_749, n_1_0_750, n_1_0_751, n_1_0_752, n_1_0_753, + n_1_0_754, n_1_0_755, n_1_0_756, n_1_0_757, n_1_0_758, n_1_0_759, + n_1_0_760, n_1_0_761, n_1_0_762, n_1_0_763, n_1_0_764, n_1_0_765, + n_1_0_766, n_1_0_767, n_1_0_768, n_1_0_769, n_1_0_770, n_1_0_771, + n_1_0_772, n_1_0_773, n_1_0_774, n_1_0_775, n_1_0_776, n_1_0_777, + n_1_0_778, n_1_0_779, n_1_0_780, n_1_0_781, n_1_0_782, n_1_0_783, + n_1_0_784, n_1_0_785, n_1_0_786, n_1_0_787, n_1_0_788, n_1_0_789, + n_1_0_790, n_1_0_791, n_1_0_792, n_1_0_793, n_1_0_794, n_1_0_795, + n_1_0_796, n_1_0_797, n_1_0_798, n_1_0_799, n_1_0_800, n_1_0_801, + n_1_0_802, n_1_0_803, n_1_0_804, n_1_0_805, n_1_0_806, n_1_0_807, + n_1_0_808, n_1_0_809, n_1_0_810, n_1_0_811, n_1_0_812, n_1_0_813, + n_1_0_814, n_1_0_815, n_1_0_816, n_1_0_817, n_1_0_818, n_1_0_819, + n_1_0_820, n_1_0_821, n_1_0_822, n_1_0_823, n_1_0_824, n_1_0_825, + n_1_0_826, n_1_0_827, n_1_0_828, n_1_0_829, n_1_0_830, n_1_0_831, + n_1_0_832, n_1_0_833, n_1_0_834, n_1_0_835, n_1_0_836, n_1_0_837, + n_1_0_838, n_1_0_839, n_1_0_840, n_1_0_841, n_1_0_842, n_1_0_843, + n_1_0_844, n_1_0_845, n_1_0_846, n_1_0_847, n_1_0_848, n_1_0_849, + n_1_0_850, n_1_0_851, n_1_0_852, n_1_0_853, n_1_0_854, n_1_0_855, + n_1_0_856, n_1_0_857, n_1_0_858, n_1_0_859, n_1_0_860, n_1_0_861, + n_1_0_862, n_1_0_863, n_1_0_864, n_1_0_865, n_1_0_866, n_1_0_867, + n_1_0_868, n_1_0_869, n_1_0_870, n_1_0_871, n_1_0_872, n_1_0_873, + n_1_0_874, n_1_0_875, n_1_0_876, n_1_0_877, n_1_0_878, n_1_0_879, + n_1_0_880, n_1_0_881, n_1_0_882, n_1_0_883, n_1_0_884, n_1_0_885, + n_1_0_886, n_1_0_887, n_1_0_888, n_1_0_889, n_1_0_890, n_1_0_891, + n_1_0_892, n_1_0_893, n_1_0_894, n_1_0_895, n_1_0_896, n_1_0_897, + n_1_0_898, n_1_0_899, n_1_0_900, n_1_0_901, n_1_0_902, n_1_0_903, + n_1_0_904, n_1_0_905, n_1_0_906, n_1_0_907, n_1_0_908, n_1_0_909, + n_1_0_910, n_1_0_911, n_1_0_912, n_1_0_913, n_1_0_914, n_1_0_915, + n_1_0_916, n_1_0_917, n_1_0_918, n_1_0_919, n_1_0_920, n_1_0_921, + n_1_0_922, n_1_0_923, n_1_0_924, n_1_0_925, n_1_0_926, n_1_0_927, + n_1_0_928, n_1_0_929, n_1_0_930, n_1_0_931, n_1_0_932, n_1_0_933, + n_1_0_934, n_1_0_935, n_1_0_936, n_1_0_937, n_1_0_938, n_1_0_939, + n_1_0_940, n_1_0_941, n_1_0_942, n_1_0_943, n_1_0_944, n_1_0_945, + n_1_0_946, n_1_0_947, n_1_0_948, n_1_0_949, n_1_0_950, n_1_0_951, + n_1_0_952, n_1_0_953, n_1_0_954, n_1_0_955, n_1_0_956, n_1_0_957, + n_1_0_958, n_1_0_959, n_1_0_960, n_1_0_961, n_1_0_962, n_1_0_963, + n_1_0_964, n_1_0_965, n_1_0_966, n_1_0_967, n_1_0_968, n_1_0_969, + n_1_0_970, n_1_0_971, n_1_0_972, n_1_0_973, n_1_0_974, n_1_0_975, + n_1_0_976, n_1_0_977, n_1_0_978, n_1_0_979, n_1_0_980, n_1_0_981, + n_1_0_982, n_1_0_983, n_1_0_984, n_1_0_985, n_1_0_986, n_1_0_987, + n_1_0_988, n_1_0_989, n_1_0_990, n_1_0_991, n_1_0_992, n_1_0_993, + n_1_0_994, n_1_0_995, n_1_0_996, n_1_0_997, n_1_0_998, n_1_0_999, + n_1_0_1000, n_1_0_1001, n_1_0_1002, n_1_0_1003, n_1_0_1004, n_1_0_1005, + n_1_0_1006, n_1_0_1007, n_1_0_1008, n_1_0_1009, n_1_0_1010, n_1_0_1011, + n_1_0_1012, n_1_0_1013, n_1_0_1014, n_1_0_1015, n_1_0_1016, n_1_0_1017, + n_1_0_1018, n_1_0_1019, n_1_0_1020, n_1_0_1021, n_1_0_1022, n_1_0_1023, + n_1_0_1024, n_1_0_1025, n_1_0_1026, n_1_0_1027, n_1_0_1028, n_1_0_1029, + n_1_0_1030, n_1_0_1031, n_1_0_1032, n_1_0_1033, n_1_0_1034, n_1_0_1035, + n_1_0_1036, n_1_0_1037, n_1_0_1038, n_1_0_1039, n_1_0_1040, n_1_0_1041, + n_1_0_1042, n_1_0_1043, n_1_0_1044, n_1_0_1045, n_1_0_1046, n_1_0_1047, + n_1_0_1048, n_1_0_1049, n_1_0_1050, n_1_0_1051, n_1_0_1052, n_1_0_1053, + n_1_0_1054, n_1_0_1055, n_1_0_1056, n_1_0_1057, n_1_0_1058, n_1_0_1059, + n_1_0_1060, n_1_0_1061, n_1_0_1062, n_1_0_1063, n_1_0_1064, n_1_0_1065, + n_1_0_1066, n_1_0_1067, n_1_0_1068, n_1_0_1069, n_1_0_1070, n_1_0_1071, + n_1_0_1072, n_1_0_1073, n_1_0_1074, n_1_0_1075, n_1_0_1076, n_1_0_1077, + n_1_0_1078, n_1_0_1079, n_1_0_1080, n_1_0_1081, n_1_0_1082, n_1_0_1083, + n_1_0_1084, n_1_0_1085, n_1_0_1086, n_1_0_1087, n_1_0_1088, n_1_0_1089, + n_1_0_1090, n_1_0_1091, n_1_0_1092, n_1_0_1093, n_1_0_1094, n_1_0_1095, + n_1_0_1096, n_1_0_1097, n_1_0_1098, n_1_0_1099, n_1_0_1100, n_1_0_1101, + n_1_0_1102, n_1_0_1103, n_1_0_1104, n_1_0_1105, n_1_0_1106, n_1_0_1107, + n_1_0_1108, n_1_0_1109, n_1_0_1110, n_1_0_1111, n_1_0_1112, n_1_0_1113, + n_1_0_1114, n_1_0_1115, n_1_0_1116, n_1_0_1117, n_1_0_1118, n_1_0_1119, + n_1_0_1120, n_1_0_1121, n_1_0_1122, n_1_0_1123, n_1_0_1124, n_1_0_1125, + n_1_0_1126, n_1_0_1127, n_1_0_1128, n_1_0_1129, n_1_0_1130, n_1_0_1131, + n_1_0_1132, n_1_0_1133, n_1_0_1134, n_1_0_1135, n_1_0_1136, n_1_0_1137, + n_1_0_1138, n_1_0_1139, n_1_0_1140, n_1_0_1141, n_1_0_1142, n_1_0_1143, + n_1_0_1144, n_1_0_1145, n_1_0_1146, n_1_0_1147, n_1_0_1148, n_1_0_1149, + n_1_0_1150, n_1_0_1151, n_1_0_1152, n_1_0_1153, n_1_0_1154, n_1_0_1155, + n_1_0_1156, n_1_0_1157, n_1_0_1158, n_1_0_1159, n_1_0_1160, n_1_0_1161, + n_1_0_1162, n_1_0_1163, n_1_0_1164, n_1_0_1165, n_1_0_1166, n_1_0_1167, + n_1_0_1168, n_1_0_1169, n_1_0_1170, n_1_0_1171, n_1_0_1172, n_1_0_1173, + n_1_0_1174, n_1_0_1175, n_1_0_1176, n_1_0_1177, n_1_0_1178, n_1_0_1179, + n_1_0_1180, n_1_0_1181, n_1_0_1182, n_1_0_1183, n_1_0_1184, n_1_0_1185, + n_1_0_1186, n_1_0_1187, n_1_0_1188, n_1_0_1189, n_1_0_1190, n_1_0_1191, + n_1_0_1192, n_1_0_1193, n_1_0_1194, n_1_0_1195, n_1_0_1196, n_1_0_1197, + n_1_0_1198, n_1_0_1199, n_1_0_1200, n_1_0_1201, n_1_0_1202, n_1_0_1203, + n_1_0_1204, n_1_0_1205, n_1_0_1206, n_1_0_1207, n_1_0_1208, n_1_0_1209, + n_1_0_1210, n_1_0_1211, n_1_0_1212, n_1_0_1213, n_1_0_1214, n_1_0_1215, + n_1_0_1216, n_1_0_1217, n_1_0_1218, n_1_0_1219, n_1_0_1220, n_1_0_1221, + n_1_0_1222, n_1_0_1223, n_1_0_1224, n_1_0_1225, n_1_0_1226, n_1_0_1227, + n_1_0_1228, n_1_0_1229, n_1_0_1230, n_1_0_1231, n_1_0_1232, n_1_0_1233, + n_1_0_1234, n_1_0_1235, n_1_0_1236, n_1_0_1237, n_1_0_1238, n_1_0_1239, + n_1_0_1240, n_1_0_1241, n_1_0_1242, n_1_0_1243, n_1_0_1244, n_1_0_1245, + n_1_0_1246, n_1_0_1247, n_1_0_1248, n_1_0_1249, n_1_0_1250, n_1_0_1251, + n_1_0_1252, n_1_0_1253, n_1_0_1254, n_1_0_1255, n_1_0_1256, n_1_0_1257, + n_1_0_1258, n_1_0_1259, n_1_0_1260, n_1_0_1261, n_1_0_1262, n_1_0_1263, + n_1_0_1264, n_1_0_1265, n_1_0_1266, n_1_0_1267, n_1_0_1268, n_1_0_1269, + n_1_0_1270, n_1_0_1271, n_1_0_1272, n_1_0_1273, n_1_0_1274, n_1_0_1275, + n_1_0_1276, n_1_0_1277, n_1_0_1278, n_1_0_1279, n_1_0_1280, n_1_0_1281, + n_1_0_1282, n_1_0_1283, n_1_0_1284, n_1_0_1285, n_1_0_1286, n_1_0_1287, + n_1_0_1288, n_1_0_1289, n_1_0_1290, n_1_0_1291, n_1_0_1292, n_1_0_1293, + n_1_0_1294, n_1_0_1295, n_1_0_1296, n_1_0_1297, n_1_0_1298, n_1_0_1299, + n_1_0_1300, n_1_0_1301, n_1_0_1302, n_1_0_1303, n_1_0_1304, n_1_0_1305, + n_1_0_1306, n_1_0_1307, n_1_0_1308, n_1_0_1309, ts_pbuf_extsi1227_, + ts_pbuf_extsi1228_, ts_pbuf_extsi1226_; + + INV_X1_LVT i_0_0_79( + .A(reset), .ZN(n_0_0_16) + ); + AND2_X1_LVT i_0_0_31( + .A1(n_0_0_16), .A2(WRd[31]), .ZN(registers[31]) + ); + INV_X1_LVT i_0_0_81( + .A(Rd[1]), .ZN(n_0_0_18) + ); + INV_X1_LVT i_0_0_80( + .A(Rd[0]), .ZN(n_0_0_17) + ); + NAND3_X1_LVT i_0_0_69( + .A1(n_0_0_18), .A2(n_0_0_17), .A3(Rd[2]), .ZN(n_0_0_9) + ); + NAND3_X1_LVT i_0_0_41( + .A1(Rd[3]), .A2(WrReg), .A3(Rd[4]), .ZN(n_0_0_1) + ); + OAI21_X1_LVT i_0_0_35( + .A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_1), .ZN(n_0_28) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[28]_reg ( + .CK(clk), .E(n_0_28), .GCK(n_0_58), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[28][31] ( + .CK(n_0_58), .D(registers[31]), .Q(registers_28__ap[31]), .QN(), .SE(dftIn), + .SI(ts_pbuf_extsi1227_) + ); + INV_X1_LVT i_1_0_1370( + .A(Rs1[0]), .ZN(n_1_0_1306) + ); + NAND3_X1_LVT i_1_0_1354( + .A1(n_1_0_1306), .A2(Rs1[3]), .A3(Rs1[4]), .ZN(n_1_0_1290) + ); + INV_X1_LVT i_1_0_1373( + .A(Rs1[2]), .ZN(n_1_0_1309) + ); + OR2_X1_LVT i_1_0_1348( + .A1(n_1_0_1309), .A2(Rs1[1]), .ZN(n_1_0_1284) + ); + NOR2_X1_LVT i_1_0_1347( + .A1(n_1_0_1290), .A2(n_1_0_1284), .ZN(n_1_0_1283) + ); + NOR4_X1_LVT i_1_0_1342( + .A1(n_1_0_1284), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), .ZN(n_1_0_1278) + ); + INV_X1_LVT i_0_0_83( + .A(WrReg), .ZN(n_0_0_20) + ); + OR3_X1_LVT i_0_0_77( + .A1(n_0_0_20), .A2(Rd[4]), .A3(Rd[3]), .ZN(n_0_0_14) + ); + OAI21_X1_LVT i_0_0_68( + .A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_9), .ZN(n_0_4) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[4]_reg ( + .CK(clk), .E(n_0_4), .GCK(n_0_34), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[4][31] ( + .CK(n_0_34), .D(registers[31]), .Q(registers_4__ap[31]), .QN(), .SE(dftIn), + .SI(ts_pbuf_extsi1228_) + ); + AOI22_X1_LVT i_1_0_1320( + .A1(registers_28__ap[31]), .A2(n_1_0_1283), .B1(n_1_0_1278), .B2(registers_4__ap[31]), + .ZN(n_1_0_1256) + ); + NAND2_X1_LVT i_0_0_70( + .A1(n_0_0_18), .A2(n_0_0_17), .ZN(n_0_0_10) + ); + INV_X1_LVT i_0_0_82( + .A(Rd[4]), .ZN(n_0_0_19) + ); + OR3_X1_LVT i_0_0_51( + .A1(n_0_0_20), .A2(n_0_0_19), .A3(Rd[3]), .ZN(n_0_0_3) + ); + OR2_X1_LVT i_0_0_50( + .A1(n_0_0_3), .A2(Rd[2]), .ZN(n_0_0_2) + ); + OAI21_X1_LVT i_0_0_49( + .A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_2), .ZN(n_0_16) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[16]_reg ( + .CK(clk), .E(n_0_16), .GCK(n_0_46), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[16][31] ( + .CK(n_0_46), .D(registers[31]), .Q(registers_16__ap[31]), .QN(), .SE(dftIn), + .SI(ts_intno31) + ); + INV_X1_LVT i_1_0_1371( + .A(Rs1[3]), .ZN(n_1_0_1307) + ); + NAND3_X1_LVT i_1_0_1363( + .A1(n_1_0_1307), .A2(n_1_0_1306), .A3(Rs1[4]), .ZN(n_1_0_1299) + ); + OR2_X1_LVT i_1_0_1357( + .A1(Rs1[1]), .A2(Rs1[2]), .ZN(n_1_0_1293) + ); + NOR2_X1_LVT i_1_0_1331( + .A1(n_1_0_1299), .A2(n_1_0_1293), .ZN(n_1_0_1267) + ); + NAND2_X1_LVT i_1_0_1365( + .A1(Rs1[1]), .A2(Rs1[2]), .ZN(n_1_0_1301) + ); + NAND3_X1_LVT i_1_0_1344( + .A1(Rs1[4]), .A2(Rs1[3]), .A3(Rs1[0]), .ZN(n_1_0_1280) + ); + NOR2_X1_LVT i_1_0_1330( + .A1(n_1_0_1301), .A2(n_1_0_1280), .ZN(n_1_0_1266) + ); + NAND3_X1_LVT i_0_0_63( + .A1(Rd[2]), .A2(Rd[1]), .A3(Rd[0]), .ZN(n_0_0_6) + ); + OAI21_X1_LVT i_0_0_32( + .A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_1), .ZN(n_0_31) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[31]_reg ( + .CK(clk), .E(n_0_31), .GCK(n_0_61), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[31][31] ( + .CK(n_0_61), .D(registers[31]), .Q(registers_31__ap[31]), .QN(), .SE(dftIn), + .SI(registers_4__ap[31]) + ); + AOI22_X1_LVT i_1_0_1329( + .A1(registers_16__ap[31]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[31]), + .ZN(n_1_0_1265) + ); + NAND3_X1_LVT i_0_0_65( + .A1(n_0_0_17), .A2(Rd[1]), .A3(Rd[2]), .ZN(n_0_0_7) + ); + OAI21_X1_LVT i_0_0_64( + .A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_7), .ZN(n_0_6) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[6]_reg ( + .CK(clk), .E(n_0_6), .GCK(n_0_36), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[6][31] ( + .CK(n_0_36), .D(registers[31]), .Q(registers_6__ap[31]), .QN(), .SE(dftIn), + .SI(registers_31__ap[31]) + ); + NOR4_X1_LVT i_1_0_1364( + .A1(n_1_0_1301), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), .ZN(n_1_0_1300) + ); + INV_X1_LVT i_1_0_1372( + .A(Rs1[4]), .ZN(n_1_0_1308) + ); + NAND3_X1_LVT i_1_0_1339( + .A1(n_1_0_1308), .A2(n_1_0_1307), .A3(Rs1[0]), .ZN(n_1_0_1275) + ); + NOR2_X1_LVT i_1_0_1338( + .A1(n_1_0_1293), .A2(n_1_0_1275), .ZN(n_1_0_1274) + ); + NAND2_X1_LVT i_0_0_78( + .A1(n_0_0_18), .A2(Rd[0]), .ZN(n_0_0_15) + ); + OR2_X1_LVT i_0_0_76( + .A1(n_0_0_14), .A2(Rd[2]), .ZN(n_0_0_13) + ); + OAI21_X1_LVT i_0_0_75( + .A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_13), .ZN(n_0_1) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[1]_reg ( + .CK(clk), .E(n_0_1), .GCK(n_0_0), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[1][31] ( + .CK(n_0_0), .D(registers[31]), .Q(registers_1__ap[31]), .QN(), .SE(dftIn), + .SI(ts_pbuf_extsi1226_) + ); + AOI22_X1_LVT i_1_0_1319( + .A1(registers_6__ap[31]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[31]), + .ZN(n_1_0_1255) + ); + OAI21_X1_LVT i_0_0_42( + .A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_3), .ZN(n_0_23) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[23]_reg ( + .CK(clk), .E(n_0_23), .GCK(n_0_53), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[23][31] ( + .CK(n_0_53), .D(registers[31]), .Q(registers_23__ap[31]), .QN(), .SE(dftIn), + .SI(registers_1__ap[31]) + ); + NAND3_X1_LVT i_1_0_1360( + .A1(n_1_0_1307), .A2(Rs1[0]), .A3(Rs1[4]), .ZN(n_1_0_1296) + ); + NOR2_X1_LVT i_1_0_1328( + .A1(n_1_0_1301), .A2(n_1_0_1296), .ZN(n_1_0_1264) + ); + NOR2_X1_LVT i_1_0_1327( + .A1(n_1_0_1301), .A2(n_1_0_1275), .ZN(n_1_0_1263) + ); + OAI21_X1_LVT i_0_0_62( + .A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_6), .ZN(n_0_7) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[7]_reg ( + .CK(clk), .E(n_0_7), .GCK(n_0_37), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[7][31] ( + .CK(n_0_37), .D(registers[31]), .Q(registers_7__ap[31]), .QN(), .SE(dftIn), + .SI(registers_6__ap[31]) + ); + AOI22_X1_LVT i_1_0_1326( + .A1(registers_23__ap[31]), .A2(n_1_0_1264), .B1(n_1_0_1263), .B2(registers_7__ap[31]), + .ZN(n_1_0_1262) + ); + INV_X1_LVT i_1_0_1325( + .A(n_1_0_1262), .ZN(n_1_0_1261) + ); + NAND2_X1_LVT i_1_0_1362( + .A1(n_1_0_1309), .A2(Rs1[1]), .ZN(n_1_0_1298) + ); + NOR2_X1_LVT i_1_0_1359( + .A1(n_1_0_1298), .A2(n_1_0_1296), .ZN(n_1_0_1295) + ); + NAND2_X1_LVT i_0_0_72( + .A1(Rd[1]), .A2(Rd[0]), .ZN(n_0_0_11) + ); + OAI21_X1_LVT i_0_0_46( + .A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_2), .ZN(n_0_19) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[19]_reg ( + .CK(clk), .E(n_0_19), .GCK(n_0_49), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[19][31] ( + .CK(n_0_49), .D(registers[31]), .Q(registers_19__ap[31]), .QN(), .SE(dftIn), + .SI(registers_23__ap[31]) + ); + NAND3_X1_LVT i_0_0_67( + .A1(n_0_0_18), .A2(Rd[0]), .A3(Rd[2]), .ZN(n_0_0_8) + ); + OAI21_X1_LVT i_0_0_66( + .A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_8), .ZN(n_0_5) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[5]_reg ( + .CK(clk), .E(n_0_5), .GCK(n_0_35), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[5][31] ( + .CK(n_0_35), .D(registers[31]), .Q(registers_5__ap[31]), .QN(), .SE(dftIn), + .SI(registers_7__ap[31]) + ); + NOR2_X1_LVT i_1_0_1337( + .A1(n_1_0_1284), .A2(n_1_0_1275), .ZN(n_1_0_1273) + ); + AOI221_X1_LVT i_1_0_1318( + .A(n_1_0_1261), .B1(n_1_0_1295), .B2(registers_19__ap[31]), .C1(registers_5__ap[31]), + .C2(n_1_0_1273), .ZN(n_1_0_1254) + ); + NAND2_X1_LVT i_0_0_74( + .A1(n_0_0_17), .A2(Rd[1]), .ZN(n_0_0_12) + ); + NAND3_X1_LVT i_0_0_61( + .A1(n_0_0_19), .A2(WrReg), .A3(Rd[3]), .ZN(n_0_0_5) + ); + OR2_X1_LVT i_0_0_60( + .A1(n_0_0_5), .A2(Rd[2]), .ZN(n_0_0_4) + ); + OAI21_X1_LVT i_0_0_57( + .A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_4), .ZN(n_0_10) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[10]_reg ( + .CK(clk), .E(n_0_10), .GCK(n_0_40), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[10][31] ( + .CK(n_0_40), .D(registers[31]), .Q(registers_10__ap[31]), .QN(), .SE(dftIn), + .SI(registers_16__ap[31]) + ); + NAND3_X1_LVT i_1_0_1352( + .A1(n_1_0_1308), .A2(n_1_0_1306), .A3(Rs1[3]), .ZN(n_1_0_1288) + ); + NOR2_X1_LVT i_1_0_1351( + .A1(n_1_0_1298), .A2(n_1_0_1288), .ZN(n_1_0_1287) + ); + NOR2_X1_LVT i_1_0_1349( + .A1(n_1_0_1298), .A2(n_1_0_1290), .ZN(n_1_0_1285) + ); + OR2_X1_LVT i_0_0_40( + .A1(n_0_0_1), .A2(Rd[2]), .ZN(n_0_0_0) + ); + OAI21_X1_LVT i_0_0_37( + .A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_0), .ZN(n_0_26) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[26]_reg ( + .CK(clk), .E(n_0_26), .GCK(n_0_56), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[26][31] ( + .CK(n_0_56), .D(registers[31]), .Q(registers_26__ap[31]), .QN(), .SE(dftIn), + .SI(registers_28__ap[31]) + ); + OAI21_X1_LVT i_0_0_59( + .A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_4), .ZN(n_0_8) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[8]_reg ( + .CK(clk), .E(n_0_8), .GCK(n_0_38), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[8][31] ( + .CK(n_0_38), .D(registers[31]), .Q(registers_8__ap[31]), .QN(), .SE(dftIn), + .SI(registers_5__ap[31]) + ); + NOR2_X1_LVT i_1_0_1346( + .A1(n_1_0_1293), .A2(n_1_0_1288), .ZN(n_1_0_1282) + ); + AOI222_X1_LVT i_1_0_1317( + .A1(registers_10__ap[31]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[31]), + .C1(registers_8__ap[31]), .C2(n_1_0_1282), .ZN(n_1_0_1253) + ); + NAND4_X1_LVT i_1_0_1316( + .A1(n_1_0_1265), .A2(n_1_0_1255), .A3(n_1_0_1254), .A4(n_1_0_1253), .ZN(n_1_0_1252) + ); + NAND3_X1_LVT i_1_0_1356( + .A1(n_1_0_1308), .A2(Rs1[3]), .A3(Rs1[0]), .ZN(n_1_0_1292) + ); + NOR2_X1_LVT i_1_0_1355( + .A1(n_1_0_1293), .A2(n_1_0_1292), .ZN(n_1_0_1291) + ); + OAI21_X1_LVT i_0_0_58( + .A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_4), .ZN(n_0_9) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[9]_reg ( + .CK(clk), .E(n_0_9), .GCK(n_0_39), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[9][31] ( + .CK(n_0_39), .D(registers[31]), .Q(registers_9__ap[31]), .QN(), .SE(dftIn), + .SI(registers_8__ap[31]) + ); + OAI21_X1_LVT i_0_0_34( + .A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_1), .ZN(n_0_29) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[29]_reg ( + .CK(clk), .E(n_0_29), .GCK(n_0_59), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[29][31] ( + .CK(n_0_59), .D(registers[31]), .Q(registers_29__ap[31]), .QN(), .SE(dftIn), + .SI(registers_26__ap[31]) + ); + NOR2_X1_LVT i_1_0_1340( + .A1(n_1_0_1284), .A2(n_1_0_1280), .ZN(n_1_0_1276) + ); + AOI221_X1_LVT i_1_0_1315( + .A(n_1_0_1252), .B1(n_1_0_1291), .B2(registers_9__ap[31]), .C1(registers_29__ap[31]), + .C2(n_1_0_1276), .ZN(n_1_0_1251) + ); + OAI21_X1_LVT i_0_0_47( + .A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_2), .ZN(n_0_18) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[18]_reg ( + .CK(clk), .E(n_0_18), .GCK(n_0_48), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[18][31] ( + .CK(n_0_48), .D(registers[31]), .Q(registers_18__ap[31]), .QN(), .SE(dftIn), + .SI(registers_19__ap[31]) + ); + NOR2_X1_LVT i_1_0_1361( + .A1(n_1_0_1299), .A2(n_1_0_1298), .ZN(n_1_0_1297) + ); + NOR2_X1_LVT i_1_0_1336( + .A1(n_1_0_1301), .A2(n_1_0_1290), .ZN(n_1_0_1272) + ); + OAI21_X1_LVT i_0_0_33( + .A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_1), .ZN(n_0_30) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[30]_reg ( + .CK(clk), .E(n_0_30), .GCK(n_0_60), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[30][31] ( + .CK(n_0_60), .D(registers[31]), .Q(registers_30__ap[31]), .QN(), .SE(dftIn), + .SI(registers_29__ap[31]) + ); + AOI22_X1_LVT i_1_0_1314( + .A1(registers_18__ap[31]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[31]), + .ZN(n_1_0_1250) + ); + OAI21_X1_LVT i_0_0_39( + .A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_0), .ZN(n_0_24) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[24]_reg ( + .CK(clk), .E(n_0_24), .GCK(n_0_54), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[24][31] ( + .CK(n_0_54), .D(registers[31]), .Q(registers_24__ap[31]), .QN(), .SE(dftIn), + .SI(registers_30__ap[31]) + ); + NOR2_X1_LVT i_1_0_1353( + .A1(n_1_0_1293), .A2(n_1_0_1290), .ZN(n_1_0_1289) + ); + NOR2_X1_LVT i_1_0_1324( + .A1(n_1_0_1288), .A2(n_1_0_1284), .ZN(n_1_0_1260) + ); + OAI21_X1_LVT i_0_0_55( + .A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_5), .ZN(n_0_12) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[12]_reg ( + .CK(clk), .E(n_0_12), .GCK(n_0_42), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[12][31] ( + .CK(n_0_42), .D(registers[31]), .Q(registers_12__ap[31]), .QN(), .SE(dftIn), + .SI(registers_10__ap[31]) + ); + AOI22_X1_LVT i_1_0_1313( + .A1(registers_24__ap[31]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[31]), + .ZN(n_1_0_1249) + ); + OAI21_X1_LVT i_0_0_43( + .A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_3), .ZN(n_0_22) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[22]_reg ( + .CK(clk), .E(n_0_22), .GCK(n_0_52), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[22][31] ( + .CK(n_0_52), .D(registers[31]), .Q(registers_22__ap[31]), .QN(), .SE(dftIn), + .SI(registers_18__ap[31]) + ); + NOR2_X1_LVT i_1_0_1358( + .A1(n_1_0_1301), .A2(n_1_0_1299), .ZN(n_1_0_1294) + ); + NOR2_X1_LVT i_1_0_1323( + .A1(n_1_0_1296), .A2(n_1_0_1284), .ZN(n_1_0_1259) + ); + OAI21_X1_LVT i_0_0_44( + .A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_3), .ZN(n_0_21) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[21]_reg ( + .CK(clk), .E(n_0_21), .GCK(n_0_51), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[21][31] ( + .CK(n_0_51), .D(registers[31]), .Q(registers_21__ap[31]), .QN(), .SE(dftIn), + .SI(registers_22__ap[31]) + ); + AOI22_X1_LVT i_1_0_1312( + .A1(registers_22__ap[31]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[31]), + .ZN(n_1_0_1248) + ); + NAND3_X1_LVT i_1_0_1311( + .A1(n_1_0_1250), .A2(n_1_0_1249), .A3(n_1_0_1248), .ZN(n_1_0_1247) + ); + NOR2_X1_LVT i_1_0_1335( + .A1(n_1_0_1296), .A2(n_1_0_1293), .ZN(n_1_0_1271) + ); + OAI21_X1_LVT i_0_0_48( + .A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_2), .ZN(n_0_17) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[17]_reg ( + .CK(clk), .E(n_0_17), .GCK(n_0_47), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[17][31] ( + .CK(n_0_47), .D(registers[31]), .Q(registers_17__ap[31]), .QN(), .SE(dftIn), + .SI(registers_21__ap[31]) + ); + OAI21_X1_LVT i_0_0_45( + .A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_3), .ZN(n_0_20) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[20]_reg ( + .CK(clk), .E(n_0_20), .GCK(n_0_50), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[20][31] ( + .CK(n_0_50), .D(registers[31]), .Q(registers_20__ap[31]), .QN(), .SE(dftIn), + .SI(registers_17__ap[31]) + ); + NOR2_X1_LVT i_1_0_1345( + .A1(n_1_0_1299), .A2(n_1_0_1284), .ZN(n_1_0_1281) + ); + AOI221_X1_LVT i_1_0_1310( + .A(n_1_0_1247), .B1(n_1_0_1271), .B2(registers_17__ap[31]), .C1(registers_20__ap[31]), + .C2(n_1_0_1281), .ZN(n_1_0_1246) + ); + OAI21_X1_LVT i_0_0_36( + .A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_0), .ZN(n_0_27) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[27]_reg ( + .CK(clk), .E(n_0_27), .GCK(n_0_57), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[27][31] ( + .CK(n_0_57), .D(registers[31]), .Q(registers_27__ap[31]), .QN(), .SE(dftIn), + .SI(registers_24__ap[31]) + ); + NOR2_X1_LVT i_1_0_1343( + .A1(n_1_0_1298), .A2(n_1_0_1280), .ZN(n_1_0_1279) + ); + NOR2_X1_LVT i_1_0_1334( + .A1(n_1_0_1298), .A2(n_1_0_1292), .ZN(n_1_0_1270) + ); + OAI21_X1_LVT i_0_0_56( + .A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_4), .ZN(n_0_11) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[11]_reg ( + .CK(clk), .E(n_0_11), .GCK(n_0_41), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[11][31] ( + .CK(n_0_41), .D(registers[31]), .Q(registers_11__ap[31]), .QN(), .SE(dftIn), + .SI(registers_12__ap[31]) + ); + AOI22_X1_LVT i_1_0_1309( + .A1(registers_27__ap[31]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[31]), + .ZN(n_1_0_1245) + ); + OAI21_X1_LVT i_0_0_54( + .A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_5), .ZN(n_0_13) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[13]_reg ( + .CK(clk), .E(n_0_13), .GCK(n_0_43), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[13][31] ( + .CK(n_0_43), .D(registers[31]), .Q(registers_13__ap[31]), .QN(), .SE(dftIn), + .SI(registers_11__ap[31]) + ); + NOR2_X1_LVT i_1_0_1341( + .A1(n_1_0_1292), .A2(n_1_0_1284), .ZN(n_1_0_1277) + ); + NOR2_X1_LVT i_1_0_1333( + .A1(n_1_0_1293), .A2(n_1_0_1280), .ZN(n_1_0_1269) + ); + OAI21_X1_LVT i_0_0_38( + .A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_0), .ZN(n_0_25) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[25]_reg ( + .CK(clk), .E(n_0_25), .GCK(n_0_55), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[25][31] ( + .CK(n_0_55), .D(registers[31]), .Q(registers_25__ap[31]), .QN(), .SE(dftIn), + .SI(registers_27__ap[31]) + ); + AOI22_X1_LVT i_1_0_1308( + .A1(registers_13__ap[31]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[31]), + .ZN(n_1_0_1244) + ); + OAI21_X1_LVT i_0_0_52( + .A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_5), .ZN(n_0_15) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[15]_reg ( + .CK(clk), .E(n_0_15), .GCK(n_0_45), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[15][31] ( + .CK(n_0_45), .D(registers[31]), .Q(registers_15__ap[31]), .QN(), .SE(dftIn), + .SI(registers_13__ap[31]) + ); + NOR2_X1_LVT i_1_0_1350( + .A1(n_1_0_1301), .A2(n_1_0_1292), .ZN(n_1_0_1286) + ); + NOR2_X1_LVT i_1_0_1322( + .A1(n_1_0_1301), .A2(n_1_0_1288), .ZN(n_1_0_1258) + ); + OAI21_X1_LVT i_0_0_53( + .A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_5), .ZN(n_0_14) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[14]_reg ( + .CK(clk), .E(n_0_14), .GCK(n_0_44), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[14][31] ( + .CK(n_0_44), .D(registers[31]), .Q(registers_14__ap[31]), .QN(), .SE(dftIn), + .SI(registers_15__ap[31]) + ); + AOI22_X1_LVT i_1_0_1307( + .A1(registers_15__ap[31]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[31]), + .ZN(n_1_0_1243) + ); + NAND3_X1_LVT i_1_0_1306( + .A1(n_1_0_1245), .A2(n_1_0_1244), .A3(n_1_0_1243), .ZN(n_1_0_1242) + ); + NOR2_X1_LVT i_1_0_1321( + .A1(n_1_0_1298), .A2(n_1_0_1275), .ZN(n_1_0_1257) + ); + OAI21_X1_LVT i_0_0_71( + .A(n_0_0_16), .B1(n_0_0_13), .B2(n_0_0_11), .ZN(n_0_3) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[3]_reg ( + .CK(clk), .E(n_0_3), .GCK(n_0_33), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[3][31] ( + .CK(n_0_33), .D(registers[31]), .Q(registers_3__ap[31]), .QN(), .SE(dftIn), + .SI(registers_9__ap[31]) + ); + OAI21_X1_LVT i_0_0_73( + .A(n_0_0_16), .B1(n_0_0_13), .B2(n_0_0_12), .ZN(n_0_2) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[2]_reg ( + .CK(clk), .E(n_0_2), .GCK(n_0_32), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[2][31] ( + .CK(n_0_32), .D(registers[31]), .Q(registers_2__ap[31]), .QN(), .SE(dftIn), + .SI(registers_25__ap[31]) + ); + NOR4_X1_LVT i_1_0_1332( + .A1(n_1_0_1298), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), .ZN(n_1_0_1268) + ); + AOI221_X1_LVT i_1_0_1305( + .A(n_1_0_1242), .B1(n_1_0_1257), .B2(registers_3__ap[31]), .C1(registers_2__ap[31]), + .C2(n_1_0_1268), .ZN(n_1_0_1241) + ); + NAND4_X1_LVT i_1_0_1304( + .A1(n_1_0_1256), .A2(n_1_0_1251), .A3(n_1_0_1246), .A4(n_1_0_1241), .ZN(RRs1[31]) + ); + AND2_X1_LVT i_0_0_30( + .A1(n_0_0_16), .A2(WRd[30]), .ZN(registers[30]) + ); + SDFF_X1_LVT \registers_reg[28][30] ( + .CK(n_0_58), .D(registers[30]), .Q(registers_28__ap[30]), .QN(), .SE(dftIn), + .SI(registers_2__ap[31]) + ); + SDFF_X1_LVT \registers_reg[17][30] ( + .CK(n_0_47), .D(registers[30]), .Q(registers_17__ap[30]), .QN(), .SE(dftIn), + .SI(registers_20__ap[31]) + ); + AOI22_X1_LVT i_1_0_1300( + .A1(registers_28__ap[30]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[30]), + .ZN(n_1_0_1237) + ); + SDFF_X1_LVT \registers_reg[16][30] ( + .CK(n_0_46), .D(registers[30]), .Q(registers_16__ap[30]), .QN(), .SE(dftIn), + .SI(registers_14__ap[31]) + ); + SDFF_X1_LVT \registers_reg[31][30] ( + .CK(n_0_61), .D(registers[30]), .Q(registers_31__ap[30]), .QN(), .SE(dftIn), + .SI(registers_3__ap[31]) + ); + AOI22_X1_LVT i_1_0_1303( + .A1(registers_16__ap[30]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[30]), + .ZN(n_1_0_1240) + ); + SDFF_X1_LVT \registers_reg[6][30] ( + .CK(n_0_36), .D(registers[30]), .Q(registers_6__ap[30]), .QN(), .SE(dftIn), + .SI(registers_31__ap[30]) + ); + SDFF_X1_LVT \registers_reg[1][30] ( + .CK(n_0_0), .D(registers[30]), .Q(registers_1__ap[30]), .QN(), .SE(dftIn), + .SI(registers_17__ap[30]) + ); + AOI22_X1_LVT i_1_0_1299( + .A1(registers_6__ap[30]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[30]), + .ZN(n_1_0_1236) + ); + SDFF_X1_LVT \registers_reg[23][30] ( + .CK(n_0_53), .D(registers[30]), .Q(registers_23__ap[30]), .QN(), .SE(dftIn), + .SI(registers_1__ap[30]) + ); + SDFF_X1_LVT \registers_reg[7][30] ( + .CK(n_0_37), .D(registers[30]), .Q(registers_7__ap[30]), .QN(), .SE(dftIn), + .SI(registers_6__ap[30]) + ); + AOI22_X1_LVT i_1_0_1302( + .A1(registers_23__ap[30]), .A2(n_1_0_1264), .B1(n_1_0_1263), .B2(registers_7__ap[30]), + .ZN(n_1_0_1239) + ); + INV_X1_LVT i_1_0_1301( + .A(n_1_0_1239), .ZN(n_1_0_1238) + ); + SDFF_X1_LVT \registers_reg[19][30] ( + .CK(n_0_49), .D(registers[30]), .Q(registers_19__ap[30]), .QN(), .SE(dftIn), + .SI(registers_23__ap[30]) + ); + SDFF_X1_LVT \registers_reg[5][30] ( + .CK(n_0_35), .D(registers[30]), .Q(registers_5__ap[30]), .QN(), .SE(dftIn), + .SI(registers_7__ap[30]) + ); + AOI221_X1_LVT i_1_0_1298( + .A(n_1_0_1238), .B1(n_1_0_1295), .B2(registers_19__ap[30]), .C1(registers_5__ap[30]), + .C2(n_1_0_1273), .ZN(n_1_0_1235) + ); + SDFF_X1_LVT \registers_reg[10][30] ( + .CK(n_0_40), .D(registers[30]), .Q(registers_10__ap[30]), .QN(), .SE(dftIn), + .SI(registers_16__ap[30]) + ); + SDFF_X1_LVT \registers_reg[26][30] ( + .CK(n_0_56), .D(registers[30]), .Q(registers_26__ap[30]), .QN(), .SE(dftIn), + .SI(registers_28__ap[30]) + ); + SDFF_X1_LVT \registers_reg[8][30] ( + .CK(n_0_38), .D(registers[30]), .Q(registers_8__ap[30]), .QN(), .SE(dftIn), + .SI(registers_5__ap[30]) + ); + AOI222_X1_LVT i_1_0_1297( + .A1(registers_10__ap[30]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[30]), + .C1(registers_8__ap[30]), .C2(n_1_0_1282), .ZN(n_1_0_1234) + ); + NAND4_X1_LVT i_1_0_1296( + .A1(n_1_0_1240), .A2(n_1_0_1236), .A3(n_1_0_1235), .A4(n_1_0_1234), .ZN(n_1_0_1233) + ); + SDFF_X1_LVT \registers_reg[9][30] ( + .CK(n_0_39), .D(registers[30]), .Q(registers_9__ap[30]), .QN(), .SE(dftIn), + .SI(registers_8__ap[30]) + ); + SDFF_X1_LVT \registers_reg[29][30] ( + .CK(n_0_59), .D(registers[30]), .Q(registers_29__ap[30]), .QN(), .SE(dftIn), + .SI(registers_26__ap[30]) + ); + AOI221_X1_LVT i_1_0_1295( + .A(n_1_0_1233), .B1(n_1_0_1291), .B2(registers_9__ap[30]), .C1(registers_29__ap[30]), + .C2(n_1_0_1276), .ZN(n_1_0_1232) + ); + SDFF_X1_LVT \registers_reg[18][30] ( + .CK(n_0_48), .D(registers[30]), .Q(registers_18__ap[30]), .QN(), .SE(dftIn), + .SI(registers_19__ap[30]) + ); + SDFF_X1_LVT \registers_reg[30][30] ( + .CK(n_0_60), .D(registers[30]), .Q(registers_30__ap[30]), .QN(), .SE(dftIn), + .SI(registers_29__ap[30]) + ); + AOI22_X1_LVT i_1_0_1294( + .A1(registers_18__ap[30]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[30]), + .ZN(n_1_0_1231) + ); + SDFF_X1_LVT \registers_reg[20][30] ( + .CK(n_0_50), .D(registers[30]), .Q(registers_20__ap[30]), .QN(), .SE(dftIn), + .SI(registers_18__ap[30]) + ); + SDFF_X1_LVT \registers_reg[4][30] ( + .CK(n_0_34), .D(registers[30]), .Q(registers_4__ap[30]), .QN(), .SE(dftIn), + .SI(registers_9__ap[30]) + ); + AOI22_X1_LVT i_1_0_1293( + .A1(registers_20__ap[30]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[30]), + .ZN(n_1_0_1230) + ); + SDFF_X1_LVT \registers_reg[22][30] ( + .CK(n_0_52), .D(registers[30]), .Q(registers_22__ap[30]), .QN(), .SE(dftIn), + .SI(registers_20__ap[30]) + ); + SDFF_X1_LVT \registers_reg[21][30] ( + .CK(n_0_51), .D(registers[30]), .Q(registers_21__ap[30]), .QN(), .SE(dftIn), + .SI(registers_22__ap[30]) + ); + AOI22_X1_LVT i_1_0_1292( + .A1(registers_22__ap[30]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[30]), + .ZN(n_1_0_1229) + ); + NAND3_X1_LVT i_1_0_1291( + .A1(n_1_0_1231), .A2(n_1_0_1230), .A3(n_1_0_1229), .ZN(n_1_0_1228) + ); + SDFF_X1_LVT \registers_reg[24][30] ( + .CK(n_0_54), .D(registers[30]), .Q(registers_24__ap[30]), .QN(), .SE(dftIn), + .SI(registers_30__ap[30]) + ); + SDFF_X1_LVT \registers_reg[12][30] ( + .CK(n_0_42), .D(registers[30]), .Q(registers_12__ap[30]), .QN(), .SE(dftIn), + .SI(registers_10__ap[30]) + ); + AOI221_X1_LVT i_1_0_1290( + .A(n_1_0_1228), .B1(n_1_0_1289), .B2(registers_24__ap[30]), .C1(registers_12__ap[30]), + .C2(n_1_0_1260), .ZN(n_1_0_1227) + ); + SDFF_X1_LVT \registers_reg[27][30] ( + .CK(n_0_57), .D(registers[30]), .Q(registers_27__ap[30]), .QN(), .SE(dftIn), + .SI(registers_24__ap[30]) + ); + SDFF_X1_LVT \registers_reg[11][30] ( + .CK(n_0_41), .D(registers[30]), .Q(registers_11__ap[30]), .QN(), .SE(dftIn), + .SI(registers_12__ap[30]) + ); + AOI22_X1_LVT i_1_0_1289( + .A1(registers_27__ap[30]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[30]), + .ZN(n_1_0_1226) + ); + SDFF_X1_LVT \registers_reg[13][30] ( + .CK(n_0_43), .D(registers[30]), .Q(registers_13__ap[30]), .QN(), .SE(dftIn), + .SI(registers_11__ap[30]) + ); + SDFF_X1_LVT \registers_reg[25][30] ( + .CK(n_0_55), .D(registers[30]), .Q(registers_25__ap[30]), .QN(), .SE(dftIn), + .SI(registers_27__ap[30]) + ); + AOI22_X1_LVT i_1_0_1288( + .A1(registers_13__ap[30]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[30]), + .ZN(n_1_0_1225) + ); + SDFF_X1_LVT \registers_reg[15][30] ( + .CK(n_0_45), .D(registers[30]), .Q(registers_15__ap[30]), .QN(), .SE(dftIn), + .SI(registers_13__ap[30]) + ); + SDFF_X1_LVT \registers_reg[14][30] ( + .CK(n_0_44), .D(registers[30]), .Q(registers_14__ap[30]), .QN(), .SE(dftIn), + .SI(registers_15__ap[30]) + ); + AOI22_X1_LVT i_1_0_1287( + .A1(registers_15__ap[30]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[30]), + .ZN(n_1_0_1224) + ); + NAND3_X1_LVT i_1_0_1286( + .A1(n_1_0_1226), .A2(n_1_0_1225), .A3(n_1_0_1224), .ZN(n_1_0_1223) + ); + SDFF_X1_LVT \registers_reg[3][30] ( + .CK(n_0_33), .D(registers[30]), .Q(registers_3__ap[30]), .QN(), .SE(dftIn), + .SI(registers_4__ap[30]) + ); + SDFF_X1_LVT \registers_reg[2][30] ( + .CK(n_0_32), .D(registers[30]), .Q(registers_2__ap[30]), .QN(), .SE(dftIn), + .SI(registers_25__ap[30]) + ); + AOI221_X1_LVT i_1_0_1285( + .A(n_1_0_1223), .B1(n_1_0_1257), .B2(registers_3__ap[30]), .C1(registers_2__ap[30]), + .C2(n_1_0_1268), .ZN(n_1_0_1222) + ); + NAND4_X1_LVT i_1_0_1284( + .A1(n_1_0_1237), .A2(n_1_0_1232), .A3(n_1_0_1227), .A4(n_1_0_1222), .ZN(RRs1[30]) + ); + AND2_X1_LVT i_0_0_29( + .A1(n_0_0_16), .A2(WRd[29]), .ZN(registers[29]) + ); + SDFF_X1_LVT \registers_reg[28][29] ( + .CK(n_0_58), .D(registers[29]), .Q(registers_28__ap[29]), .QN(), .SE(dftIn), + .SI(registers_2__ap[30]) + ); + SDFF_X1_LVT \registers_reg[8][29] ( + .CK(n_0_38), .D(registers[29]), .Q(registers_8__ap[29]), .QN(), .SE(dftIn), + .SI(registers_3__ap[30]) + ); + AOI22_X1_LVT i_1_0_1282( + .A1(registers_28__ap[29]), .A2(n_1_0_1283), .B1(n_1_0_1282), .B2(registers_8__ap[29]), + .ZN(n_1_0_1220) + ); + SDFF_X1_LVT \registers_reg[31][29] ( + .CK(n_0_61), .D(registers[29]), .Q(registers_31__ap[29]), .QN(), .SE(dftIn), + .SI(registers_8__ap[29]) + ); + SDFF_X1_LVT \registers_reg[7][29] ( + .CK(n_0_37), .D(registers[29]), .Q(registers_7__ap[29]), .QN(), .SE(dftIn), + .SI(registers_31__ap[29]) + ); + AOI22_X1_LVT i_1_0_1283( + .A1(registers_31__ap[29]), .A2(n_1_0_1266), .B1(n_1_0_1263), .B2(registers_7__ap[29]), + .ZN(n_1_0_1221) + ); + SDFF_X1_LVT \registers_reg[24][29] ( + .CK(n_0_54), .D(registers[29]), .Q(registers_24__ap[29]), .QN(), .SE(dftIn), + .SI(registers_28__ap[29]) + ); + SDFF_X1_LVT \registers_reg[20][29] ( + .CK(n_0_50), .D(registers[29]), .Q(registers_20__ap[29]), .QN(), .SE(dftIn), + .SI(registers_21__ap[30]) + ); + AOI22_X1_LVT i_1_0_1281( + .A1(registers_24__ap[29]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[29]), + .ZN(n_1_0_1219) + ); + SDFF_X1_LVT \registers_reg[19][29] ( + .CK(n_0_49), .D(registers[29]), .Q(registers_19__ap[29]), .QN(), .SE(dftIn), + .SI(registers_20__ap[29]) + ); + SDFF_X1_LVT \registers_reg[4][29] ( + .CK(n_0_34), .D(registers[29]), .Q(registers_4__ap[29]), .QN(), .SE(dftIn), + .SI(registers_7__ap[29]) + ); + AOI22_X1_LVT i_1_0_1280( + .A1(registers_19__ap[29]), .A2(n_1_0_1295), .B1(n_1_0_1278), .B2(registers_4__ap[29]), + .ZN(n_1_0_1218) + ); + NAND3_X1_LVT i_1_0_1279( + .A1(n_1_0_1221), .A2(n_1_0_1219), .A3(n_1_0_1218), .ZN(n_1_0_1217) + ); + SDFF_X1_LVT \registers_reg[23][29] ( + .CK(n_0_53), .D(registers[29]), .Q(registers_23__ap[29]), .QN(), .SE(dftIn), + .SI(registers_19__ap[29]) + ); + SDFF_X1_LVT \registers_reg[29][29] ( + .CK(n_0_59), .D(registers[29]), .Q(registers_29__ap[29]), .QN(), .SE(dftIn), + .SI(registers_24__ap[29]) + ); + AOI221_X1_LVT i_1_0_1278( + .A(n_1_0_1217), .B1(n_1_0_1264), .B2(registers_23__ap[29]), .C1(registers_29__ap[29]), + .C2(n_1_0_1276), .ZN(n_1_0_1216) + ); + SDFF_X1_LVT \registers_reg[10][29] ( + .CK(n_0_40), .D(registers[29]), .Q(registers_10__ap[29]), .QN(), .SE(dftIn), + .SI(registers_14__ap[30]) + ); + SDFF_X1_LVT \registers_reg[26][29] ( + .CK(n_0_56), .D(registers[29]), .Q(registers_26__ap[29]), .QN(), .SE(dftIn), + .SI(registers_29__ap[29]) + ); + SDFF_X1_LVT \registers_reg[25][29] ( + .CK(n_0_55), .D(registers[29]), .Q(registers_25__ap[29]), .QN(), .SE(dftIn), + .SI(registers_26__ap[29]) + ); + AOI222_X1_LVT i_1_0_1277( + .A1(registers_10__ap[29]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[29]), + .C1(registers_25__ap[29]), .C2(n_1_0_1269), .ZN(n_1_0_1215) + ); + NAND3_X1_LVT i_1_0_1276( + .A1(n_1_0_1220), .A2(n_1_0_1216), .A3(n_1_0_1215), .ZN(n_1_0_1214) + ); + SDFF_X1_LVT \registers_reg[21][29] ( + .CK(n_0_51), .D(registers[29]), .Q(registers_21__ap[29]), .QN(), .SE(dftIn), + .SI(registers_23__ap[29]) + ); + SDFF_X1_LVT \registers_reg[13][29] ( + .CK(n_0_43), .D(registers[29]), .Q(registers_13__ap[29]), .QN(), .SE(dftIn), + .SI(registers_10__ap[29]) + ); + AOI221_X1_LVT i_1_0_1275( + .A(n_1_0_1214), .B1(n_1_0_1259), .B2(registers_21__ap[29]), .C1(registers_13__ap[29]), + .C2(n_1_0_1277), .ZN(n_1_0_1213) + ); + SDFF_X1_LVT \registers_reg[18][29] ( + .CK(n_0_48), .D(registers[29]), .Q(registers_18__ap[29]), .QN(), .SE(dftIn), + .SI(registers_21__ap[29]) + ); + SDFF_X1_LVT \registers_reg[30][29] ( + .CK(n_0_60), .D(registers[29]), .Q(registers_30__ap[29]), .QN(), .SE(dftIn), + .SI(registers_25__ap[29]) + ); + AOI22_X1_LVT i_1_0_1274( + .A1(registers_18__ap[29]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[29]), + .ZN(n_1_0_1212) + ); + SDFF_X1_LVT \registers_reg[17][29] ( + .CK(n_0_47), .D(registers[29]), .Q(registers_17__ap[29]), .QN(), .SE(dftIn), + .SI(registers_18__ap[29]) + ); + SDFF_X1_LVT \registers_reg[12][29] ( + .CK(n_0_42), .D(registers[29]), .Q(registers_12__ap[29]), .QN(), .SE(dftIn), + .SI(registers_13__ap[29]) + ); + AOI22_X1_LVT i_1_0_1273( + .A1(registers_17__ap[29]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[29]), + .ZN(n_1_0_1211) + ); + SDFF_X1_LVT \registers_reg[15][29] ( + .CK(n_0_45), .D(registers[29]), .Q(registers_15__ap[29]), .QN(), .SE(dftIn), + .SI(registers_12__ap[29]) + ); + SDFF_X1_LVT \registers_reg[16][29] ( + .CK(n_0_46), .D(registers[29]), .Q(registers_16__ap[29]), .QN(), .SE(dftIn), + .SI(registers_15__ap[29]) + ); + AOI22_X1_LVT i_1_0_1272( + .A1(registers_15__ap[29]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[29]), + .ZN(n_1_0_1210) + ); + NAND3_X1_LVT i_1_0_1271( + .A1(n_1_0_1212), .A2(n_1_0_1211), .A3(n_1_0_1210), .ZN(n_1_0_1209) + ); + SDFF_X1_LVT \registers_reg[22][29] ( + .CK(n_0_52), .D(registers[29]), .Q(registers_22__ap[29]), .QN(), .SE(dftIn), + .SI(registers_17__ap[29]) + ); + SDFF_X1_LVT \registers_reg[5][29] ( + .CK(n_0_35), .D(registers[29]), .Q(registers_5__ap[29]), .QN(), .SE(dftIn), + .SI(registers_4__ap[29]) + ); + AOI221_X1_LVT i_1_0_1270( + .A(n_1_0_1209), .B1(n_1_0_1294), .B2(registers_22__ap[29]), .C1(registers_5__ap[29]), + .C2(n_1_0_1273), .ZN(n_1_0_1208) + ); + SDFF_X1_LVT \registers_reg[9][29] ( + .CK(n_0_39), .D(registers[29]), .Q(registers_9__ap[29]), .QN(), .SE(dftIn), + .SI(registers_5__ap[29]) + ); + SDFF_X1_LVT \registers_reg[1][29] ( + .CK(n_0_0), .D(registers[29]), .Q(registers_1__ap[29]), .QN(), .SE(dftIn), + .SI(registers_22__ap[29]) + ); + AOI22_X1_LVT i_1_0_1269( + .A1(registers_9__ap[29]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[29]), + .ZN(n_1_0_1207) + ); + SDFF_X1_LVT \registers_reg[6][29] ( + .CK(n_0_36), .D(registers[29]), .Q(registers_6__ap[29]), .QN(), .SE(dftIn), + .SI(registers_9__ap[29]) + ); + SDFF_X1_LVT \registers_reg[14][29] ( + .CK(n_0_44), .D(registers[29]), .Q(registers_14__ap[29]), .QN(), .SE(dftIn), + .SI(registers_16__ap[29]) + ); + AOI22_X1_LVT i_1_0_1268( + .A1(registers_6__ap[29]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[29]), + .ZN(n_1_0_1206) + ); + SDFF_X1_LVT \registers_reg[27][29] ( + .CK(n_0_57), .D(registers[29]), .Q(registers_27__ap[29]), .QN(), .SE(dftIn), + .SI(registers_30__ap[29]) + ); + SDFF_X1_LVT \registers_reg[11][29] ( + .CK(n_0_41), .D(registers[29]), .Q(registers_11__ap[29]), .QN(), .SE(dftIn), + .SI(registers_14__ap[29]) + ); + AOI22_X1_LVT i_1_0_1267( + .A1(registers_27__ap[29]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[29]), + .ZN(n_1_0_1205) + ); + NAND3_X1_LVT i_1_0_1266( + .A1(n_1_0_1207), .A2(n_1_0_1206), .A3(n_1_0_1205), .ZN(n_1_0_1204) + ); + SDFF_X1_LVT \registers_reg[3][29] ( + .CK(n_0_33), .D(registers[29]), .Q(registers_3__ap[29]), .QN(), .SE(dftIn), + .SI(registers_6__ap[29]) + ); + SDFF_X1_LVT \registers_reg[2][29] ( + .CK(n_0_32), .D(registers[29]), .Q(registers_2__ap[29]), .QN(), .SE(dftIn), + .SI(registers_27__ap[29]) + ); + AOI221_X1_LVT i_1_0_1265( + .A(n_1_0_1204), .B1(n_1_0_1257), .B2(registers_3__ap[29]), .C1(registers_2__ap[29]), + .C2(n_1_0_1268), .ZN(n_1_0_1203) + ); + NAND3_X1_LVT i_1_0_1264( + .A1(n_1_0_1213), .A2(n_1_0_1208), .A3(n_1_0_1203), .ZN(RRs1[29]) + ); + AND2_X1_LVT i_0_0_28( + .A1(n_0_0_16), .A2(WRd[28]), .ZN(registers[28]) + ); + SDFF_X1_LVT \registers_reg[15][28] ( + .CK(n_0_45), .D(registers[28]), .Q(registers_15__ap[28]), .QN(), .SE(dftIn), + .SI(registers_11__ap[29]) + ); + SDFF_X1_LVT \registers_reg[26][28] ( + .CK(n_0_56), .D(registers[28]), .Q(registers_26__ap[28]), .QN(), .SE(dftIn), + .SI(registers_2__ap[29]) + ); + SDFF_X1_LVT \registers_reg[22][28] ( + .CK(n_0_52), .D(registers[28]), .Q(registers_22__ap[28]), .QN(), .SE(dftIn), + .SI(registers_1__ap[29]) + ); + AOI222_X1_LVT i_1_0_1263( + .A1(registers_15__ap[28]), .A2(n_1_0_1286), .B1(n_1_0_1285), .B2(registers_26__ap[28]), + .C1(registers_22__ap[28]), .C2(n_1_0_1294), .ZN(n_1_0_1202) + ); + SDFF_X1_LVT \registers_reg[5][28] ( + .CK(n_0_35), .D(registers[28]), .Q(registers_5__ap[28]), .QN(), .SE(dftIn), + .SI(registers_3__ap[29]) + ); + SDFF_X1_LVT \registers_reg[12][28] ( + .CK(n_0_42), .D(registers[28]), .Q(registers_12__ap[28]), .QN(), .SE(dftIn), + .SI(registers_15__ap[28]) + ); + AOI22_X1_LVT i_1_0_1262( + .A1(registers_5__ap[28]), .A2(n_1_0_1273), .B1(n_1_0_1260), .B2(registers_12__ap[28]), + .ZN(n_1_0_1201) + ); + SDFF_X1_LVT \registers_reg[28][28] ( + .CK(n_0_58), .D(registers[28]), .Q(registers_28__ap[28]), .QN(), .SE(dftIn), + .SI(registers_26__ap[28]) + ); + SDFF_X1_LVT \registers_reg[14][28] ( + .CK(n_0_44), .D(registers[28]), .Q(registers_14__ap[28]), .QN(), .SE(dftIn), + .SI(registers_12__ap[28]) + ); + AOI22_X1_LVT i_1_0_1261( + .A1(registers_28__ap[28]), .A2(n_1_0_1283), .B1(n_1_0_1258), .B2(registers_14__ap[28]), + .ZN(n_1_0_1200) + ); + SDFF_X1_LVT \registers_reg[17][28] ( + .CK(n_0_47), .D(registers[28]), .Q(registers_17__ap[28]), .QN(), .SE(dftIn), + .SI(registers_22__ap[28]) + ); + SDFF_X1_LVT \registers_reg[2][28] ( + .CK(n_0_32), .D(registers[28]), .Q(registers_2__ap[28]), .QN(), .SE(dftIn), + .SI(registers_28__ap[28]) + ); + AOI22_X1_LVT i_1_0_1260( + .A1(registers_17__ap[28]), .A2(n_1_0_1271), .B1(n_1_0_1268), .B2(registers_2__ap[28]), + .ZN(n_1_0_1199) + ); + NAND3_X1_LVT i_1_0_1259( + .A1(n_1_0_1201), .A2(n_1_0_1200), .A3(n_1_0_1199), .ZN(n_1_0_1198) + ); + SDFF_X1_LVT \registers_reg[9][28] ( + .CK(n_0_39), .D(registers[28]), .Q(registers_9__ap[28]), .QN(), .SE(dftIn), + .SI(registers_5__ap[28]) + ); + SDFF_X1_LVT \registers_reg[29][28] ( + .CK(n_0_59), .D(registers[28]), .Q(registers_29__ap[28]), .QN(), .SE(dftIn), + .SI(registers_2__ap[28]) + ); + AOI221_X1_LVT i_1_0_1258( + .A(n_1_0_1198), .B1(n_1_0_1291), .B2(registers_9__ap[28]), .C1(registers_29__ap[28]), + .C2(n_1_0_1276), .ZN(n_1_0_1197) + ); + SDFF_X1_LVT \registers_reg[13][28] ( + .CK(n_0_43), .D(registers[28]), .Q(registers_13__ap[28]), .QN(), .SE(dftIn), + .SI(registers_14__ap[28]) + ); + SDFF_X1_LVT \registers_reg[25][28] ( + .CK(n_0_55), .D(registers[28]), .Q(registers_25__ap[28]), .QN(), .SE(dftIn), + .SI(registers_29__ap[28]) + ); + AOI22_X1_LVT i_1_0_1257( + .A1(registers_13__ap[28]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[28]), + .ZN(n_1_0_1196) + ); + NAND3_X1_LVT i_1_0_1256( + .A1(n_1_0_1202), .A2(n_1_0_1197), .A3(n_1_0_1196), .ZN(n_1_0_1195) + ); + SDFF_X1_LVT \registers_reg[4][28] ( + .CK(n_0_34), .D(registers[28]), .Q(registers_4__ap[28]), .QN(), .SE(dftIn), + .SI(registers_9__ap[28]) + ); + SDFF_X1_LVT \registers_reg[20][28] ( + .CK(n_0_50), .D(registers[28]), .Q(registers_20__ap[28]), .QN(), .SE(dftIn), + .SI(registers_17__ap[28]) + ); + AOI221_X1_LVT i_1_0_1255( + .A(n_1_0_1195), .B1(n_1_0_1278), .B2(registers_4__ap[28]), .C1(registers_20__ap[28]), + .C2(n_1_0_1281), .ZN(n_1_0_1194) + ); + SDFF_X1_LVT \registers_reg[1][28] ( + .CK(n_0_0), .D(registers[28]), .Q(registers_1__ap[28]), .QN(), .SE(dftIn), + .SI(registers_20__ap[28]) + ); + SDFF_X1_LVT \registers_reg[23][28] ( + .CK(n_0_53), .D(registers[28]), .Q(registers_23__ap[28]), .QN(), .SE(dftIn), + .SI(registers_1__ap[28]) + ); + AOI22_X1_LVT i_1_0_1254( + .A1(registers_1__ap[28]), .A2(n_1_0_1274), .B1(n_1_0_1264), .B2(registers_23__ap[28]), + .ZN(n_1_0_1193) + ); + SDFF_X1_LVT \registers_reg[10][28] ( + .CK(n_0_40), .D(registers[28]), .Q(registers_10__ap[28]), .QN(), .SE(dftIn), + .SI(registers_13__ap[28]) + ); + SDFF_X1_LVT \registers_reg[21][28] ( + .CK(n_0_51), .D(registers[28]), .Q(registers_21__ap[28]), .QN(), .SE(dftIn), + .SI(registers_23__ap[28]) + ); + AOI22_X1_LVT i_1_0_1253( + .A1(registers_10__ap[28]), .A2(n_1_0_1287), .B1(n_1_0_1259), .B2(registers_21__ap[28]), + .ZN(n_1_0_1192) + ); + SDFF_X1_LVT \registers_reg[6][28] ( + .CK(n_0_36), .D(registers[28]), .Q(registers_6__ap[28]), .QN(), .SE(dftIn), + .SI(registers_4__ap[28]) + ); + SDFF_X1_LVT \registers_reg[30][28] ( + .CK(n_0_60), .D(registers[28]), .Q(registers_30__ap[28]), .QN(), .SE(dftIn), + .SI(registers_25__ap[28]) + ); + AOI22_X1_LVT i_1_0_1252( + .A1(registers_6__ap[28]), .A2(n_1_0_1300), .B1(n_1_0_1272), .B2(registers_30__ap[28]), + .ZN(n_1_0_1191) + ); + NAND3_X1_LVT i_1_0_1251( + .A1(n_1_0_1193), .A2(n_1_0_1192), .A3(n_1_0_1191), .ZN(n_1_0_1190) + ); + SDFF_X1_LVT \registers_reg[8][28] ( + .CK(n_0_38), .D(registers[28]), .Q(registers_8__ap[28]), .QN(), .SE(dftIn), + .SI(registers_6__ap[28]) + ); + SDFF_X1_LVT \registers_reg[24][28] ( + .CK(n_0_54), .D(registers[28]), .Q(registers_24__ap[28]), .QN(), .SE(dftIn), + .SI(registers_30__ap[28]) + ); + AOI221_X1_LVT i_1_0_1250( + .A(n_1_0_1190), .B1(n_1_0_1282), .B2(registers_8__ap[28]), .C1(registers_24__ap[28]), + .C2(n_1_0_1289), .ZN(n_1_0_1189) + ); + SDFF_X1_LVT \registers_reg[16][28] ( + .CK(n_0_46), .D(registers[28]), .Q(registers_16__ap[28]), .QN(), .SE(dftIn), + .SI(registers_10__ap[28]) + ); + SDFF_X1_LVT \registers_reg[3][28] ( + .CK(n_0_33), .D(registers[28]), .Q(registers_3__ap[28]), .QN(), .SE(dftIn), + .SI(registers_8__ap[28]) + ); + AOI22_X1_LVT i_1_0_1249( + .A1(registers_16__ap[28]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[28]), + .ZN(n_1_0_1188) + ); + SDFF_X1_LVT \registers_reg[11][28] ( + .CK(n_0_41), .D(registers[28]), .Q(registers_11__ap[28]), .QN(), .SE(dftIn), + .SI(registers_16__ap[28]) + ); + SDFF_X1_LVT \registers_reg[31][28] ( + .CK(n_0_61), .D(registers[28]), .Q(registers_31__ap[28]), .QN(), .SE(dftIn), + .SI(registers_3__ap[28]) + ); + AOI22_X1_LVT i_1_0_1248( + .A1(registers_11__ap[28]), .A2(n_1_0_1270), .B1(n_1_0_1266), .B2(registers_31__ap[28]), + .ZN(n_1_0_1187) + ); + SDFF_X1_LVT \registers_reg[27][28] ( + .CK(n_0_57), .D(registers[28]), .Q(registers_27__ap[28]), .QN(), .SE(dftIn), + .SI(registers_24__ap[28]) + ); + SDFF_X1_LVT \registers_reg[7][28] ( + .CK(n_0_37), .D(registers[28]), .Q(registers_7__ap[28]), .QN(), .SE(dftIn), + .SI(registers_31__ap[28]) + ); + AOI22_X1_LVT i_1_0_1247( + .A1(registers_27__ap[28]), .A2(n_1_0_1279), .B1(n_1_0_1263), .B2(registers_7__ap[28]), + .ZN(n_1_0_1186) + ); + NAND3_X1_LVT i_1_0_1246( + .A1(n_1_0_1188), .A2(n_1_0_1187), .A3(n_1_0_1186), .ZN(n_1_0_1185) + ); + SDFF_X1_LVT \registers_reg[19][28] ( + .CK(n_0_49), .D(registers[28]), .Q(registers_19__ap[28]), .QN(), .SE(dftIn), + .SI(registers_21__ap[28]) + ); + SDFF_X1_LVT \registers_reg[18][28] ( + .CK(n_0_48), .D(registers[28]), .Q(registers_18__ap[28]), .QN(), .SE(dftIn), + .SI(registers_19__ap[28]) + ); + AOI221_X1_LVT i_1_0_1245( + .A(n_1_0_1185), .B1(n_1_0_1295), .B2(registers_19__ap[28]), .C1(registers_18__ap[28]), + .C2(n_1_0_1297), .ZN(n_1_0_1184) + ); + NAND3_X1_LVT i_1_0_1244( + .A1(n_1_0_1194), .A2(n_1_0_1189), .A3(n_1_0_1184), .ZN(RRs1[28]) + ); + AND2_X1_LVT i_0_0_27( + .A1(n_0_0_16), .A2(WRd[27]), .ZN(registers[27]) + ); + SDFF_X1_LVT \registers_reg[29][27] ( + .CK(n_0_59), .D(registers[27]), .Q(registers_29__ap[27]), .QN(), .SE(dftIn), + .SI(registers_27__ap[28]) + ); + SDFF_X1_LVT \registers_reg[2][27] ( + .CK(n_0_32), .D(registers[27]), .Q(registers_2__ap[27]), .QN(), .SE(dftIn), + .SI(registers_29__ap[27]) + ); + AOI22_X1_LVT i_1_0_1242( + .A1(registers_29__ap[27]), .A2(n_1_0_1276), .B1(n_1_0_1268), .B2(registers_2__ap[27]), + .ZN(n_1_0_1182) + ); + SDFF_X1_LVT \registers_reg[8][27] ( + .CK(n_0_38), .D(registers[27]), .Q(registers_8__ap[27]), .QN(), .SE(dftIn), + .SI(registers_7__ap[28]) + ); + SDFF_X1_LVT \registers_reg[25][27] ( + .CK(n_0_55), .D(registers[27]), .Q(registers_25__ap[27]), .QN(), .SE(dftIn), + .SI(registers_2__ap[27]) + ); + AOI22_X1_LVT i_1_0_1243( + .A1(registers_8__ap[27]), .A2(n_1_0_1282), .B1(n_1_0_1269), .B2(registers_25__ap[27]), + .ZN(n_1_0_1183) + ); + SDFF_X1_LVT \registers_reg[9][27] ( + .CK(n_0_39), .D(registers[27]), .Q(registers_9__ap[27]), .QN(), .SE(dftIn), + .SI(registers_8__ap[27]) + ); + SDFF_X1_LVT \registers_reg[7][27] ( + .CK(n_0_37), .D(registers[27]), .Q(registers_7__ap[27]), .QN(), .SE(dftIn), + .SI(registers_9__ap[27]) + ); + AOI22_X1_LVT i_1_0_1241( + .A1(registers_9__ap[27]), .A2(n_1_0_1291), .B1(n_1_0_1263), .B2(registers_7__ap[27]), + .ZN(n_1_0_1181) + ); + SDFF_X1_LVT \registers_reg[11][27] ( + .CK(n_0_41), .D(registers[27]), .Q(registers_11__ap[27]), .QN(), .SE(dftIn), + .SI(registers_11__ap[28]) + ); + SDFF_X1_LVT \registers_reg[16][27] ( + .CK(n_0_46), .D(registers[27]), .Q(registers_16__ap[27]), .QN(), .SE(dftIn), + .SI(registers_11__ap[27]) + ); + AOI22_X1_LVT i_1_0_1240( + .A1(registers_11__ap[27]), .A2(n_1_0_1270), .B1(n_1_0_1267), .B2(registers_16__ap[27]), + .ZN(n_1_0_1180) + ); + NAND3_X1_LVT i_1_0_1239( + .A1(n_1_0_1183), .A2(n_1_0_1181), .A3(n_1_0_1180), .ZN(n_1_0_1179) + ); + SDFF_X1_LVT \registers_reg[10][27] ( + .CK(n_0_40), .D(registers[27]), .Q(registers_10__ap[27]), .QN(), .SE(dftIn), + .SI(registers_16__ap[27]) + ); + SDFF_X1_LVT \registers_reg[6][27] ( + .CK(n_0_36), .D(registers[27]), .Q(registers_6__ap[27]), .QN(), .SE(dftIn), + .SI(registers_7__ap[27]) + ); + AOI221_X1_LVT i_1_0_1238( + .A(n_1_0_1179), .B1(n_1_0_1287), .B2(registers_10__ap[27]), .C1(registers_6__ap[27]), + .C2(n_1_0_1300), .ZN(n_1_0_1178) + ); + SDFF_X1_LVT \registers_reg[1][27] ( + .CK(n_0_0), .D(registers[27]), .Q(registers_1__ap[27]), .QN(), .SE(dftIn), + .SI(registers_18__ap[28]) + ); + SDFF_X1_LVT \registers_reg[30][27] ( + .CK(n_0_60), .D(registers[27]), .Q(registers_30__ap[27]), .QN(), .SE(dftIn), + .SI(registers_25__ap[27]) + ); + SDFF_X1_LVT \registers_reg[22][27] ( + .CK(n_0_52), .D(registers[27]), .Q(registers_22__ap[27]), .QN(), .SE(dftIn), + .SI(registers_1__ap[27]) + ); + AOI222_X1_LVT i_1_0_1237( + .A1(registers_1__ap[27]), .A2(n_1_0_1274), .B1(n_1_0_1272), .B2(registers_30__ap[27]), + .C1(registers_22__ap[27]), .C2(n_1_0_1294), .ZN(n_1_0_1177) + ); + NAND3_X1_LVT i_1_0_1236( + .A1(n_1_0_1182), .A2(n_1_0_1178), .A3(n_1_0_1177), .ZN(n_1_0_1176) + ); + SDFF_X1_LVT \registers_reg[5][27] ( + .CK(n_0_35), .D(registers[27]), .Q(registers_5__ap[27]), .QN(), .SE(dftIn), + .SI(registers_6__ap[27]) + ); + SDFF_X1_LVT \registers_reg[28][27] ( + .CK(n_0_58), .D(registers[27]), .Q(registers_28__ap[27]), .QN(), .SE(dftIn), + .SI(registers_30__ap[27]) + ); + AOI221_X1_LVT i_1_0_1235( + .A(n_1_0_1176), .B1(n_1_0_1273), .B2(registers_5__ap[27]), .C1(registers_28__ap[27]), + .C2(n_1_0_1283), .ZN(n_1_0_1175) + ); + SDFF_X1_LVT \registers_reg[4][27] ( + .CK(n_0_34), .D(registers[27]), .Q(registers_4__ap[27]), .QN(), .SE(dftIn), + .SI(registers_5__ap[27]) + ); + SDFF_X1_LVT \registers_reg[12][27] ( + .CK(n_0_42), .D(registers[27]), .Q(registers_12__ap[27]), .QN(), .SE(dftIn), + .SI(registers_10__ap[27]) + ); + AOI22_X1_LVT i_1_0_1234( + .A1(registers_4__ap[27]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[27]), + .ZN(n_1_0_1174) + ); + SDFF_X1_LVT \registers_reg[19][27] ( + .CK(n_0_49), .D(registers[27]), .Q(registers_19__ap[27]), .QN(), .SE(dftIn), + .SI(registers_22__ap[27]) + ); + SDFF_X1_LVT \registers_reg[21][27] ( + .CK(n_0_51), .D(registers[27]), .Q(registers_21__ap[27]), .QN(), .SE(dftIn), + .SI(registers_19__ap[27]) + ); + AOI22_X1_LVT i_1_0_1233( + .A1(registers_19__ap[27]), .A2(n_1_0_1295), .B1(n_1_0_1259), .B2(registers_21__ap[27]), + .ZN(n_1_0_1173) + ); + SDFF_X1_LVT \registers_reg[24][27] ( + .CK(n_0_54), .D(registers[27]), .Q(registers_24__ap[27]), .QN(), .SE(dftIn), + .SI(registers_28__ap[27]) + ); + SDFF_X1_LVT \registers_reg[20][27] ( + .CK(n_0_50), .D(registers[27]), .Q(registers_20__ap[27]), .QN(), .SE(dftIn), + .SI(registers_21__ap[27]) + ); + AOI22_X1_LVT i_1_0_1232( + .A1(registers_24__ap[27]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[27]), + .ZN(n_1_0_1172) + ); + NAND3_X1_LVT i_1_0_1231( + .A1(n_1_0_1174), .A2(n_1_0_1173), .A3(n_1_0_1172), .ZN(n_1_0_1171) + ); + SDFF_X1_LVT \registers_reg[18][27] ( + .CK(n_0_48), .D(registers[27]), .Q(registers_18__ap[27]), .QN(), .SE(dftIn), + .SI(registers_20__ap[27]) + ); + SDFF_X1_LVT \registers_reg[26][27] ( + .CK(n_0_56), .D(registers[27]), .Q(registers_26__ap[27]), .QN(), .SE(dftIn), + .SI(registers_24__ap[27]) + ); + AOI221_X1_LVT i_1_0_1230( + .A(n_1_0_1171), .B1(n_1_0_1297), .B2(registers_18__ap[27]), .C1(registers_26__ap[27]), + .C2(n_1_0_1285), .ZN(n_1_0_1170) + ); + SDFF_X1_LVT \registers_reg[23][27] ( + .CK(n_0_53), .D(registers[27]), .Q(registers_23__ap[27]), .QN(), .SE(dftIn), + .SI(registers_18__ap[27]) + ); + SDFF_X1_LVT \registers_reg[3][27] ( + .CK(n_0_33), .D(registers[27]), .Q(registers_3__ap[27]), .QN(), .SE(dftIn), + .SI(registers_4__ap[27]) + ); + AOI22_X1_LVT i_1_0_1229( + .A1(registers_23__ap[27]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[27]), + .ZN(n_1_0_1169) + ); + SDFF_X1_LVT \registers_reg[13][27] ( + .CK(n_0_43), .D(registers[27]), .Q(registers_13__ap[27]), .QN(), .SE(dftIn), + .SI(registers_12__ap[27]) + ); + SDFF_X1_LVT \registers_reg[17][27] ( + .CK(n_0_47), .D(registers[27]), .Q(registers_17__ap[27]), .QN(), .SE(dftIn), + .SI(registers_23__ap[27]) + ); + AOI22_X1_LVT i_1_0_1228( + .A1(registers_13__ap[27]), .A2(n_1_0_1277), .B1(n_1_0_1271), .B2(registers_17__ap[27]), + .ZN(n_1_0_1168) + ); + SDFF_X1_LVT \registers_reg[15][27] ( + .CK(n_0_45), .D(registers[27]), .Q(registers_15__ap[27]), .QN(), .SE(dftIn), + .SI(registers_13__ap[27]) + ); + SDFF_X1_LVT \registers_reg[14][27] ( + .CK(n_0_44), .D(registers[27]), .Q(registers_14__ap[27]), .QN(), .SE(dftIn), + .SI(registers_15__ap[27]) + ); + AOI22_X1_LVT i_1_0_1227( + .A1(registers_15__ap[27]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[27]), + .ZN(n_1_0_1167) + ); + NAND3_X1_LVT i_1_0_1226( + .A1(n_1_0_1169), .A2(n_1_0_1168), .A3(n_1_0_1167), .ZN(n_1_0_1166) + ); + SDFF_X1_LVT \registers_reg[27][27] ( + .CK(n_0_57), .D(registers[27]), .Q(registers_27__ap[27]), .QN(), .SE(dftIn), + .SI(registers_26__ap[27]) + ); + SDFF_X1_LVT \registers_reg[31][27] ( + .CK(n_0_61), .D(registers[27]), .Q(registers_31__ap[27]), .QN(), .SE(dftIn), + .SI(registers_3__ap[27]) + ); + AOI221_X1_LVT i_1_0_1225( + .A(n_1_0_1166), .B1(n_1_0_1279), .B2(registers_27__ap[27]), .C1(registers_31__ap[27]), + .C2(n_1_0_1266), .ZN(n_1_0_1165) + ); + NAND3_X1_LVT i_1_0_1224( + .A1(n_1_0_1175), .A2(n_1_0_1170), .A3(n_1_0_1165), .ZN(RRs1[27]) + ); + AND2_X1_LVT i_0_0_26( + .A1(n_0_0_16), .A2(WRd[26]), .ZN(registers[26]) + ); + SDFF_X1_LVT \registers_reg[18][26] ( + .CK(n_0_48), .D(registers[26]), .Q(registers_18__ap[26]), .QN(), .SE(dftIn), + .SI(registers_17__ap[27]) + ); + SDFF_X1_LVT \registers_reg[22][26] ( + .CK(n_0_52), .D(registers[26]), .Q(registers_22__ap[26]), .QN(), .SE(dftIn), + .SI(registers_18__ap[26]) + ); + SDFF_X1_LVT \registers_reg[1][26] ( + .CK(n_0_0), .D(registers[26]), .Q(registers_1__ap[26]), .QN(), .SE(dftIn), + .SI(registers_22__ap[26]) + ); + AOI222_X1_LVT i_1_0_1223( + .A1(registers_18__ap[26]), .A2(n_1_0_1297), .B1(n_1_0_1294), .B2(registers_22__ap[26]), + .C1(registers_1__ap[26]), .C2(n_1_0_1274), .ZN(n_1_0_1164) + ); + SDFF_X1_LVT \registers_reg[29][26] ( + .CK(n_0_59), .D(registers[26]), .Q(registers_29__ap[26]), .QN(), .SE(dftIn), + .SI(registers_27__ap[27]) + ); + SDFF_X1_LVT \registers_reg[2][26] ( + .CK(n_0_32), .D(registers[26]), .Q(registers_2__ap[26]), .QN(), .SE(dftIn), + .SI(registers_29__ap[26]) + ); + AOI22_X1_LVT i_1_0_1222( + .A1(registers_29__ap[26]), .A2(n_1_0_1276), .B1(n_1_0_1268), .B2(registers_2__ap[26]), + .ZN(n_1_0_1163) + ); + SDFF_X1_LVT \registers_reg[9][26] ( + .CK(n_0_39), .D(registers[26]), .Q(registers_9__ap[26]), .QN(), .SE(dftIn), + .SI(registers_31__ap[27]) + ); + SDFF_X1_LVT \registers_reg[7][26] ( + .CK(n_0_37), .D(registers[26]), .Q(registers_7__ap[26]), .QN(), .SE(dftIn), + .SI(registers_9__ap[26]) + ); + AOI22_X1_LVT i_1_0_1221( + .A1(registers_9__ap[26]), .A2(n_1_0_1291), .B1(n_1_0_1263), .B2(registers_7__ap[26]), + .ZN(n_1_0_1162) + ); + SDFF_X1_LVT \registers_reg[11][26] ( + .CK(n_0_41), .D(registers[26]), .Q(registers_11__ap[26]), .QN(), .SE(dftIn), + .SI(registers_14__ap[27]) + ); + SDFF_X1_LVT \registers_reg[25][26] ( + .CK(n_0_55), .D(registers[26]), .Q(registers_25__ap[26]), .QN(), .SE(dftIn), + .SI(registers_2__ap[26]) + ); + AOI22_X1_LVT i_1_0_1220( + .A1(registers_11__ap[26]), .A2(n_1_0_1270), .B1(n_1_0_1269), .B2(registers_25__ap[26]), + .ZN(n_1_0_1161) + ); + SDFF_X1_LVT \registers_reg[27][26] ( + .CK(n_0_57), .D(registers[26]), .Q(registers_27__ap[26]), .QN(), .SE(dftIn), + .SI(registers_25__ap[26]) + ); + SDFF_X1_LVT \registers_reg[16][26] ( + .CK(n_0_46), .D(registers[26]), .Q(registers_16__ap[26]), .QN(), .SE(dftIn), + .SI(registers_11__ap[26]) + ); + AOI22_X1_LVT i_1_0_1219( + .A1(registers_27__ap[26]), .A2(n_1_0_1279), .B1(n_1_0_1267), .B2(registers_16__ap[26]), + .ZN(n_1_0_1160) + ); + NAND3_X1_LVT i_1_0_1218( + .A1(n_1_0_1162), .A2(n_1_0_1161), .A3(n_1_0_1160), .ZN(n_1_0_1159) + ); + SDFF_X1_LVT \registers_reg[31][26] ( + .CK(n_0_61), .D(registers[26]), .Q(registers_31__ap[26]), .QN(), .SE(dftIn), + .SI(registers_7__ap[26]) + ); + SDFF_X1_LVT \registers_reg[6][26] ( + .CK(n_0_36), .D(registers[26]), .Q(registers_6__ap[26]), .QN(), .SE(dftIn), + .SI(registers_31__ap[26]) + ); + AOI221_X1_LVT i_1_0_1217( + .A(n_1_0_1159), .B1(n_1_0_1266), .B2(registers_31__ap[26]), .C1(registers_6__ap[26]), + .C2(n_1_0_1300), .ZN(n_1_0_1158) + ); + NAND3_X1_LVT i_1_0_1216( + .A1(n_1_0_1164), .A2(n_1_0_1163), .A3(n_1_0_1158), .ZN(n_1_0_1157) + ); + SDFF_X1_LVT \registers_reg[5][26] ( + .CK(n_0_35), .D(registers[26]), .Q(registers_5__ap[26]), .QN(), .SE(dftIn), + .SI(registers_6__ap[26]) + ); + SDFF_X1_LVT \registers_reg[28][26] ( + .CK(n_0_58), .D(registers[26]), .Q(registers_28__ap[26]), .QN(), .SE(dftIn), + .SI(registers_27__ap[26]) + ); + AOI221_X1_LVT i_1_0_1215( + .A(n_1_0_1157), .B1(n_1_0_1273), .B2(registers_5__ap[26]), .C1(registers_28__ap[26]), + .C2(n_1_0_1283), .ZN(n_1_0_1156) + ); + SDFF_X1_LVT \registers_reg[4][26] ( + .CK(n_0_34), .D(registers[26]), .Q(registers_4__ap[26]), .QN(), .SE(dftIn), + .SI(registers_5__ap[26]) + ); + SDFF_X1_LVT \registers_reg[12][26] ( + .CK(n_0_42), .D(registers[26]), .Q(registers_12__ap[26]), .QN(), .SE(dftIn), + .SI(registers_16__ap[26]) + ); + AOI22_X1_LVT i_1_0_1214( + .A1(registers_4__ap[26]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[26]), + .ZN(n_1_0_1155) + ); + SDFF_X1_LVT \registers_reg[19][26] ( + .CK(n_0_49), .D(registers[26]), .Q(registers_19__ap[26]), .QN(), .SE(dftIn), + .SI(registers_1__ap[26]) + ); + SDFF_X1_LVT \registers_reg[21][26] ( + .CK(n_0_51), .D(registers[26]), .Q(registers_21__ap[26]), .QN(), .SE(dftIn), + .SI(registers_19__ap[26]) + ); + AOI22_X1_LVT i_1_0_1213( + .A1(registers_19__ap[26]), .A2(n_1_0_1295), .B1(n_1_0_1259), .B2(registers_21__ap[26]), + .ZN(n_1_0_1154) + ); + SDFF_X1_LVT \registers_reg[24][26] ( + .CK(n_0_54), .D(registers[26]), .Q(registers_24__ap[26]), .QN(), .SE(dftIn), + .SI(registers_28__ap[26]) + ); + SDFF_X1_LVT \registers_reg[20][26] ( + .CK(n_0_50), .D(registers[26]), .Q(registers_20__ap[26]), .QN(), .SE(dftIn), + .SI(registers_21__ap[26]) + ); + AOI22_X1_LVT i_1_0_1212( + .A1(registers_24__ap[26]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[26]), + .ZN(n_1_0_1153) + ); + NAND3_X1_LVT i_1_0_1211( + .A1(n_1_0_1155), .A2(n_1_0_1154), .A3(n_1_0_1153), .ZN(n_1_0_1152) + ); + SDFF_X1_LVT \registers_reg[26][26] ( + .CK(n_0_56), .D(registers[26]), .Q(registers_26__ap[26]), .QN(), .SE(dftIn), + .SI(registers_24__ap[26]) + ); + SDFF_X1_LVT \registers_reg[30][26] ( + .CK(n_0_60), .D(registers[26]), .Q(registers_30__ap[26]), .QN(), .SE(dftIn), + .SI(registers_26__ap[26]) + ); + AOI221_X1_LVT i_1_0_1210( + .A(n_1_0_1152), .B1(n_1_0_1285), .B2(registers_26__ap[26]), .C1(registers_30__ap[26]), + .C2(n_1_0_1272), .ZN(n_1_0_1151) + ); + SDFF_X1_LVT \registers_reg[8][26] ( + .CK(n_0_38), .D(registers[26]), .Q(registers_8__ap[26]), .QN(), .SE(dftIn), + .SI(registers_4__ap[26]) + ); + SDFF_X1_LVT \registers_reg[23][26] ( + .CK(n_0_53), .D(registers[26]), .Q(registers_23__ap[26]), .QN(), .SE(dftIn), + .SI(registers_20__ap[26]) + ); + AOI22_X1_LVT i_1_0_1209( + .A1(registers_8__ap[26]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[26]), + .ZN(n_1_0_1150) + ); + SDFF_X1_LVT \registers_reg[13][26] ( + .CK(n_0_43), .D(registers[26]), .Q(registers_13__ap[26]), .QN(), .SE(dftIn), + .SI(registers_12__ap[26]) + ); + SDFF_X1_LVT \registers_reg[17][26] ( + .CK(n_0_47), .D(registers[26]), .Q(registers_17__ap[26]), .QN(), .SE(dftIn), + .SI(registers_23__ap[26]) + ); + AOI22_X1_LVT i_1_0_1208( + .A1(registers_13__ap[26]), .A2(n_1_0_1277), .B1(n_1_0_1271), .B2(registers_17__ap[26]), + .ZN(n_1_0_1149) + ); + SDFF_X1_LVT \registers_reg[15][26] ( + .CK(n_0_45), .D(registers[26]), .Q(registers_15__ap[26]), .QN(), .SE(dftIn), + .SI(registers_13__ap[26]) + ); + SDFF_X1_LVT \registers_reg[14][26] ( + .CK(n_0_44), .D(registers[26]), .Q(registers_14__ap[26]), .QN(), .SE(dftIn), + .SI(registers_15__ap[26]) + ); + AOI22_X1_LVT i_1_0_1207( + .A1(registers_15__ap[26]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[26]), + .ZN(n_1_0_1148) + ); + NAND3_X1_LVT i_1_0_1206( + .A1(n_1_0_1150), .A2(n_1_0_1149), .A3(n_1_0_1148), .ZN(n_1_0_1147) + ); + SDFF_X1_LVT \registers_reg[10][26] ( + .CK(n_0_40), .D(registers[26]), .Q(registers_10__ap[26]), .QN(), .SE(dftIn), + .SI(registers_14__ap[26]) + ); + SDFF_X1_LVT \registers_reg[3][26] ( + .CK(n_0_33), .D(registers[26]), .Q(registers_3__ap[26]), .QN(), .SE(dftIn), + .SI(registers_8__ap[26]) + ); + AOI221_X1_LVT i_1_0_1205( + .A(n_1_0_1147), .B1(n_1_0_1287), .B2(registers_10__ap[26]), .C1(registers_3__ap[26]), + .C2(n_1_0_1257), .ZN(n_1_0_1146) + ); + NAND3_X1_LVT i_1_0_1204( + .A1(n_1_0_1156), .A2(n_1_0_1151), .A3(n_1_0_1146), .ZN(RRs1[26]) + ); + AND2_X1_LVT i_0_0_25( + .A1(n_0_0_16), .A2(WRd[25]), .ZN(registers[25]) + ); + SDFF_X1_LVT \registers_reg[17][25] ( + .CK(n_0_47), .D(registers[25]), .Q(registers_17__ap[25]), .QN(), .SE(dftIn), + .SI(registers_17__ap[26]) + ); + SDFF_X1_LVT \registers_reg[21][25] ( + .CK(n_0_51), .D(registers[25]), .Q(registers_21__ap[25]), .QN(), .SE(dftIn), + .SI(registers_17__ap[25]) + ); + AOI22_X1_LVT i_1_0_1202( + .A1(registers_17__ap[25]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[25]), + .ZN(n_1_0_1144) + ); + SDFF_X1_LVT \registers_reg[6][25] ( + .CK(n_0_36), .D(registers[25]), .Q(registers_6__ap[25]), .QN(), .SE(dftIn), + .SI(registers_3__ap[26]) + ); + SDFF_X1_LVT \registers_reg[8][25] ( + .CK(n_0_38), .D(registers[25]), .Q(registers_8__ap[25]), .QN(), .SE(dftIn), + .SI(registers_6__ap[25]) + ); + AOI22_X1_LVT i_1_0_1203( + .A1(registers_6__ap[25]), .A2(n_1_0_1300), .B1(n_1_0_1282), .B2(registers_8__ap[25]), + .ZN(n_1_0_1145) + ); + SDFF_X1_LVT \registers_reg[20][25] ( + .CK(n_0_50), .D(registers[25]), .Q(registers_20__ap[25]), .QN(), .SE(dftIn), + .SI(registers_21__ap[25]) + ); + SDFF_X1_LVT \registers_reg[12][25] ( + .CK(n_0_42), .D(registers[25]), .Q(registers_12__ap[25]), .QN(), .SE(dftIn), + .SI(registers_10__ap[26]) + ); + AOI22_X1_LVT i_1_0_1201( + .A1(registers_20__ap[25]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[25]), + .ZN(n_1_0_1143) + ); + SDFF_X1_LVT \registers_reg[5][25] ( + .CK(n_0_35), .D(registers[25]), .Q(registers_5__ap[25]), .QN(), .SE(dftIn), + .SI(registers_8__ap[25]) + ); + SDFF_X1_LVT \registers_reg[11][25] ( + .CK(n_0_41), .D(registers[25]), .Q(registers_11__ap[25]), .QN(), .SE(dftIn), + .SI(registers_12__ap[25]) + ); + AOI22_X1_LVT i_1_0_1200( + .A1(registers_5__ap[25]), .A2(n_1_0_1273), .B1(n_1_0_1270), .B2(registers_11__ap[25]), + .ZN(n_1_0_1142) + ); + NAND3_X1_LVT i_1_0_1199( + .A1(n_1_0_1145), .A2(n_1_0_1143), .A3(n_1_0_1142), .ZN(n_1_0_1141) + ); + SDFF_X1_LVT \registers_reg[10][25] ( + .CK(n_0_40), .D(registers[25]), .Q(registers_10__ap[25]), .QN(), .SE(dftIn), + .SI(registers_11__ap[25]) + ); + SDFF_X1_LVT \registers_reg[2][25] ( + .CK(n_0_32), .D(registers[25]), .Q(registers_2__ap[25]), .QN(), .SE(dftIn), + .SI(registers_30__ap[26]) + ); + AOI221_X1_LVT i_1_0_1198( + .A(n_1_0_1141), .B1(n_1_0_1287), .B2(registers_10__ap[25]), .C1(registers_2__ap[25]), + .C2(n_1_0_1268), .ZN(n_1_0_1140) + ); + SDFF_X1_LVT \registers_reg[13][25] ( + .CK(n_0_43), .D(registers[25]), .Q(registers_13__ap[25]), .QN(), .SE(dftIn), + .SI(registers_10__ap[25]) + ); + SDFF_X1_LVT \registers_reg[30][25] ( + .CK(n_0_60), .D(registers[25]), .Q(registers_30__ap[25]), .QN(), .SE(dftIn), + .SI(registers_2__ap[25]) + ); + SDFF_X1_LVT \registers_reg[22][25] ( + .CK(n_0_52), .D(registers[25]), .Q(registers_22__ap[25]), .QN(), .SE(dftIn), + .SI(registers_20__ap[25]) + ); + AOI222_X1_LVT i_1_0_1197( + .A1(registers_13__ap[25]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[25]), + .C1(registers_22__ap[25]), .C2(n_1_0_1294), .ZN(n_1_0_1139) + ); + NAND2_X1_LVT i_1_0_1196( + .A1(n_1_0_1140), .A2(n_1_0_1139), .ZN(n_1_0_1138) + ); + SDFF_X1_LVT \registers_reg[1][25] ( + .CK(n_0_0), .D(registers[25]), .Q(registers_1__ap[25]), .QN(), .SE(dftIn), + .SI(registers_22__ap[25]) + ); + SDFF_X1_LVT \registers_reg[28][25] ( + .CK(n_0_58), .D(registers[25]), .Q(registers_28__ap[25]), .QN(), .SE(dftIn), + .SI(registers_30__ap[25]) + ); + AOI221_X1_LVT i_1_0_1195( + .A(n_1_0_1138), .B1(n_1_0_1274), .B2(registers_1__ap[25]), .C1(registers_28__ap[25]), + .C2(n_1_0_1283), .ZN(n_1_0_1137) + ); + SDFF_X1_LVT \registers_reg[18][25] ( + .CK(n_0_48), .D(registers[25]), .Q(registers_18__ap[25]), .QN(), .SE(dftIn), + .SI(registers_1__ap[25]) + ); + SDFF_X1_LVT \registers_reg[26][25] ( + .CK(n_0_56), .D(registers[25]), .Q(registers_26__ap[25]), .QN(), .SE(dftIn), + .SI(registers_28__ap[25]) + ); + AOI22_X1_LVT i_1_0_1194( + .A1(registers_18__ap[25]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[25]), + .ZN(n_1_0_1136) + ); + SDFF_X1_LVT \registers_reg[24][25] ( + .CK(n_0_54), .D(registers[25]), .Q(registers_24__ap[25]), .QN(), .SE(dftIn), + .SI(registers_26__ap[25]) + ); + SDFF_X1_LVT \registers_reg[4][25] ( + .CK(n_0_34), .D(registers[25]), .Q(registers_4__ap[25]), .QN(), .SE(dftIn), + .SI(registers_5__ap[25]) + ); + AOI22_X1_LVT i_1_0_1193( + .A1(registers_24__ap[25]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[25]), + .ZN(n_1_0_1135) + ); + SDFF_X1_LVT \registers_reg[15][25] ( + .CK(n_0_45), .D(registers[25]), .Q(registers_15__ap[25]), .QN(), .SE(dftIn), + .SI(registers_13__ap[25]) + ); + SDFF_X1_LVT \registers_reg[16][25] ( + .CK(n_0_46), .D(registers[25]), .Q(registers_16__ap[25]), .QN(), .SE(dftIn), + .SI(registers_15__ap[25]) + ); + AOI22_X1_LVT i_1_0_1192( + .A1(registers_15__ap[25]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[25]), + .ZN(n_1_0_1134) + ); + NAND3_X1_LVT i_1_0_1191( + .A1(n_1_0_1136), .A2(n_1_0_1135), .A3(n_1_0_1134), .ZN(n_1_0_1133) + ); + SDFF_X1_LVT \registers_reg[19][25] ( + .CK(n_0_49), .D(registers[25]), .Q(registers_19__ap[25]), .QN(), .SE(dftIn), + .SI(registers_18__ap[25]) + ); + SDFF_X1_LVT \registers_reg[25][25] ( + .CK(n_0_55), .D(registers[25]), .Q(registers_25__ap[25]), .QN(), .SE(dftIn), + .SI(registers_24__ap[25]) + ); + AOI221_X1_LVT i_1_0_1190( + .A(n_1_0_1133), .B1(n_1_0_1295), .B2(registers_19__ap[25]), .C1(registers_25__ap[25]), + .C2(n_1_0_1269), .ZN(n_1_0_1132) + ); + SDFF_X1_LVT \registers_reg[7][25] ( + .CK(n_0_37), .D(registers[25]), .Q(registers_7__ap[25]), .QN(), .SE(dftIn), + .SI(registers_4__ap[25]) + ); + SDFF_X1_LVT \registers_reg[14][25] ( + .CK(n_0_44), .D(registers[25]), .Q(registers_14__ap[25]), .QN(), .SE(dftIn), + .SI(registers_16__ap[25]) + ); + AOI22_X1_LVT i_1_0_1189( + .A1(registers_7__ap[25]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[25]), + .ZN(n_1_0_1131) + ); + SDFF_X1_LVT \registers_reg[9][25] ( + .CK(n_0_39), .D(registers[25]), .Q(registers_9__ap[25]), .QN(), .SE(dftIn), + .SI(registers_7__ap[25]) + ); + SDFF_X1_LVT \registers_reg[29][25] ( + .CK(n_0_59), .D(registers[25]), .Q(registers_29__ap[25]), .QN(), .SE(dftIn), + .SI(registers_25__ap[25]) + ); + AOI22_X1_LVT i_1_0_1188( + .A1(registers_9__ap[25]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[25]), + .ZN(n_1_0_1130) + ); + SDFF_X1_LVT \registers_reg[23][25] ( + .CK(n_0_53), .D(registers[25]), .Q(registers_23__ap[25]), .QN(), .SE(dftIn), + .SI(registers_19__ap[25]) + ); + SDFF_X1_LVT \registers_reg[3][25] ( + .CK(n_0_33), .D(registers[25]), .Q(registers_3__ap[25]), .QN(), .SE(dftIn), + .SI(registers_9__ap[25]) + ); + AOI22_X1_LVT i_1_0_1187( + .A1(registers_23__ap[25]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[25]), + .ZN(n_1_0_1129) + ); + NAND3_X1_LVT i_1_0_1186( + .A1(n_1_0_1131), .A2(n_1_0_1130), .A3(n_1_0_1129), .ZN(n_1_0_1128) + ); + SDFF_X1_LVT \registers_reg[27][25] ( + .CK(n_0_57), .D(registers[25]), .Q(registers_27__ap[25]), .QN(), .SE(dftIn), + .SI(registers_29__ap[25]) + ); + SDFF_X1_LVT \registers_reg[31][25] ( + .CK(n_0_61), .D(registers[25]), .Q(registers_31__ap[25]), .QN(), .SE(dftIn), + .SI(registers_3__ap[25]) + ); + AOI221_X1_LVT i_1_0_1185( + .A(n_1_0_1128), .B1(n_1_0_1279), .B2(registers_27__ap[25]), .C1(registers_31__ap[25]), + .C2(n_1_0_1266), .ZN(n_1_0_1127) + ); + NAND4_X1_LVT i_1_0_1184( + .A1(n_1_0_1144), .A2(n_1_0_1137), .A3(n_1_0_1132), .A4(n_1_0_1127), .ZN(RRs1[25]) + ); + AND2_X1_LVT i_0_0_24( + .A1(n_0_0_16), .A2(WRd[24]), .ZN(registers[24]) + ); + SDFF_X1_LVT \registers_reg[17][24] ( + .CK(n_0_47), .D(registers[24]), .Q(registers_17__ap[24]), .QN(), .SE(dftIn), + .SI(registers_23__ap[25]) + ); + SDFF_X1_LVT \registers_reg[21][24] ( + .CK(n_0_51), .D(registers[24]), .Q(registers_21__ap[24]), .QN(), .SE(dftIn), + .SI(registers_17__ap[24]) + ); + AOI22_X1_LVT i_1_0_1182( + .A1(registers_17__ap[24]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[24]), + .ZN(n_1_0_1125) + ); + SDFF_X1_LVT \registers_reg[6][24] ( + .CK(n_0_36), .D(registers[24]), .Q(registers_6__ap[24]), .QN(), .SE(dftIn), + .SI(registers_31__ap[25]) + ); + SDFF_X1_LVT \registers_reg[8][24] ( + .CK(n_0_38), .D(registers[24]), .Q(registers_8__ap[24]), .QN(), .SE(dftIn), + .SI(registers_6__ap[24]) + ); + AOI22_X1_LVT i_1_0_1183( + .A1(registers_6__ap[24]), .A2(n_1_0_1300), .B1(n_1_0_1282), .B2(registers_8__ap[24]), + .ZN(n_1_0_1126) + ); + SDFF_X1_LVT \registers_reg[20][24] ( + .CK(n_0_50), .D(registers[24]), .Q(registers_20__ap[24]), .QN(), .SE(dftIn), + .SI(registers_21__ap[24]) + ); + SDFF_X1_LVT \registers_reg[12][24] ( + .CK(n_0_42), .D(registers[24]), .Q(registers_12__ap[24]), .QN(), .SE(dftIn), + .SI(registers_14__ap[25]) + ); + AOI22_X1_LVT i_1_0_1181( + .A1(registers_20__ap[24]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[24]), + .ZN(n_1_0_1124) + ); + SDFF_X1_LVT \registers_reg[5][24] ( + .CK(n_0_35), .D(registers[24]), .Q(registers_5__ap[24]), .QN(), .SE(dftIn), + .SI(registers_8__ap[24]) + ); + SDFF_X1_LVT \registers_reg[11][24] ( + .CK(n_0_41), .D(registers[24]), .Q(registers_11__ap[24]), .QN(), .SE(dftIn), + .SI(registers_12__ap[24]) + ); + AOI22_X1_LVT i_1_0_1180( + .A1(registers_5__ap[24]), .A2(n_1_0_1273), .B1(n_1_0_1270), .B2(registers_11__ap[24]), + .ZN(n_1_0_1123) + ); + NAND3_X1_LVT i_1_0_1179( + .A1(n_1_0_1126), .A2(n_1_0_1124), .A3(n_1_0_1123), .ZN(n_1_0_1122) + ); + SDFF_X1_LVT \registers_reg[10][24] ( + .CK(n_0_40), .D(registers[24]), .Q(registers_10__ap[24]), .QN(), .SE(dftIn), + .SI(registers_11__ap[24]) + ); + SDFF_X1_LVT \registers_reg[2][24] ( + .CK(n_0_32), .D(registers[24]), .Q(registers_2__ap[24]), .QN(), .SE(dftIn), + .SI(registers_27__ap[25]) + ); + AOI221_X1_LVT i_1_0_1178( + .A(n_1_0_1122), .B1(n_1_0_1287), .B2(registers_10__ap[24]), .C1(registers_2__ap[24]), + .C2(n_1_0_1268), .ZN(n_1_0_1121) + ); + SDFF_X1_LVT \registers_reg[13][24] ( + .CK(n_0_43), .D(registers[24]), .Q(registers_13__ap[24]), .QN(), .SE(dftIn), + .SI(registers_10__ap[24]) + ); + SDFF_X1_LVT \registers_reg[30][24] ( + .CK(n_0_60), .D(registers[24]), .Q(registers_30__ap[24]), .QN(), .SE(dftIn), + .SI(registers_2__ap[24]) + ); + SDFF_X1_LVT \registers_reg[22][24] ( + .CK(n_0_52), .D(registers[24]), .Q(registers_22__ap[24]), .QN(), .SE(dftIn), + .SI(registers_20__ap[24]) + ); + AOI222_X1_LVT i_1_0_1177( + .A1(registers_13__ap[24]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[24]), + .C1(registers_22__ap[24]), .C2(n_1_0_1294), .ZN(n_1_0_1120) + ); + NAND2_X1_LVT i_1_0_1176( + .A1(n_1_0_1121), .A2(n_1_0_1120), .ZN(n_1_0_1119) + ); + SDFF_X1_LVT \registers_reg[1][24] ( + .CK(n_0_0), .D(registers[24]), .Q(registers_1__ap[24]), .QN(), .SE(dftIn), + .SI(registers_22__ap[24]) + ); + SDFF_X1_LVT \registers_reg[28][24] ( + .CK(n_0_58), .D(registers[24]), .Q(registers_28__ap[24]), .QN(), .SE(dftIn), + .SI(registers_30__ap[24]) + ); + AOI221_X1_LVT i_1_0_1175( + .A(n_1_0_1119), .B1(n_1_0_1274), .B2(registers_1__ap[24]), .C1(registers_28__ap[24]), + .C2(n_1_0_1283), .ZN(n_1_0_1118) + ); + SDFF_X1_LVT \registers_reg[18][24] ( + .CK(n_0_48), .D(registers[24]), .Q(registers_18__ap[24]), .QN(), .SE(dftIn), + .SI(registers_1__ap[24]) + ); + SDFF_X1_LVT \registers_reg[26][24] ( + .CK(n_0_56), .D(registers[24]), .Q(registers_26__ap[24]), .QN(), .SE(dftIn), + .SI(registers_28__ap[24]) + ); + AOI22_X1_LVT i_1_0_1174( + .A1(registers_18__ap[24]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[24]), + .ZN(n_1_0_1117) + ); + SDFF_X1_LVT \registers_reg[24][24] ( + .CK(n_0_54), .D(registers[24]), .Q(registers_24__ap[24]), .QN(), .SE(dftIn), + .SI(registers_26__ap[24]) + ); + SDFF_X1_LVT \registers_reg[4][24] ( + .CK(n_0_34), .D(registers[24]), .Q(registers_4__ap[24]), .QN(), .SE(dftIn), + .SI(registers_5__ap[24]) + ); + AOI22_X1_LVT i_1_0_1173( + .A1(registers_24__ap[24]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[24]), + .ZN(n_1_0_1116) + ); + SDFF_X1_LVT \registers_reg[15][24] ( + .CK(n_0_45), .D(registers[24]), .Q(registers_15__ap[24]), .QN(), .SE(dftIn), + .SI(registers_13__ap[24]) + ); + SDFF_X1_LVT \registers_reg[25][24] ( + .CK(n_0_55), .D(registers[24]), .Q(registers_25__ap[24]), .QN(), .SE(dftIn), + .SI(registers_24__ap[24]) + ); + AOI22_X1_LVT i_1_0_1172( + .A1(registers_15__ap[24]), .A2(n_1_0_1286), .B1(n_1_0_1269), .B2(registers_25__ap[24]), + .ZN(n_1_0_1115) + ); + NAND3_X1_LVT i_1_0_1171( + .A1(n_1_0_1117), .A2(n_1_0_1116), .A3(n_1_0_1115), .ZN(n_1_0_1114) + ); + SDFF_X1_LVT \registers_reg[19][24] ( + .CK(n_0_49), .D(registers[24]), .Q(registers_19__ap[24]), .QN(), .SE(dftIn), + .SI(registers_18__ap[24]) + ); + SDFF_X1_LVT \registers_reg[16][24] ( + .CK(n_0_46), .D(registers[24]), .Q(registers_16__ap[24]), .QN(), .SE(dftIn), + .SI(registers_15__ap[24]) + ); + AOI221_X1_LVT i_1_0_1170( + .A(n_1_0_1114), .B1(n_1_0_1295), .B2(registers_19__ap[24]), .C1(registers_16__ap[24]), + .C2(n_1_0_1267), .ZN(n_1_0_1113) + ); + SDFF_X1_LVT \registers_reg[7][24] ( + .CK(n_0_37), .D(registers[24]), .Q(registers_7__ap[24]), .QN(), .SE(dftIn), + .SI(registers_4__ap[24]) + ); + SDFF_X1_LVT \registers_reg[14][24] ( + .CK(n_0_44), .D(registers[24]), .Q(registers_14__ap[24]), .QN(), .SE(dftIn), + .SI(registers_16__ap[24]) + ); + AOI22_X1_LVT i_1_0_1169( + .A1(registers_7__ap[24]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[24]), + .ZN(n_1_0_1112) + ); + SDFF_X1_LVT \registers_reg[9][24] ( + .CK(n_0_39), .D(registers[24]), .Q(registers_9__ap[24]), .QN(), .SE(dftIn), + .SI(registers_7__ap[24]) + ); + SDFF_X1_LVT \registers_reg[29][24] ( + .CK(n_0_59), .D(registers[24]), .Q(registers_29__ap[24]), .QN(), .SE(dftIn), + .SI(registers_25__ap[24]) + ); + AOI22_X1_LVT i_1_0_1168( + .A1(registers_9__ap[24]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[24]), + .ZN(n_1_0_1111) + ); + SDFF_X1_LVT \registers_reg[23][24] ( + .CK(n_0_53), .D(registers[24]), .Q(registers_23__ap[24]), .QN(), .SE(dftIn), + .SI(registers_19__ap[24]) + ); + SDFF_X1_LVT \registers_reg[3][24] ( + .CK(n_0_33), .D(registers[24]), .Q(registers_3__ap[24]), .QN(), .SE(dftIn), + .SI(registers_9__ap[24]) + ); + AOI22_X1_LVT i_1_0_1167( + .A1(registers_23__ap[24]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[24]), + .ZN(n_1_0_1110) + ); + NAND3_X1_LVT i_1_0_1166( + .A1(n_1_0_1112), .A2(n_1_0_1111), .A3(n_1_0_1110), .ZN(n_1_0_1109) + ); + SDFF_X1_LVT \registers_reg[27][24] ( + .CK(n_0_57), .D(registers[24]), .Q(registers_27__ap[24]), .QN(), .SE(dftIn), + .SI(registers_29__ap[24]) + ); + SDFF_X1_LVT \registers_reg[31][24] ( + .CK(n_0_61), .D(registers[24]), .Q(registers_31__ap[24]), .QN(), .SE(dftIn), + .SI(registers_3__ap[24]) + ); + AOI221_X1_LVT i_1_0_1165( + .A(n_1_0_1109), .B1(n_1_0_1279), .B2(registers_27__ap[24]), .C1(registers_31__ap[24]), + .C2(n_1_0_1266), .ZN(n_1_0_1108) + ); + NAND4_X1_LVT i_1_0_1164( + .A1(n_1_0_1125), .A2(n_1_0_1118), .A3(n_1_0_1113), .A4(n_1_0_1108), .ZN(RRs1[24]) + ); + AND2_X1_LVT i_0_0_23( + .A1(n_0_0_16), .A2(WRd[23]), .ZN(registers[23]) + ); + SDFF_X1_LVT \registers_reg[9][23] ( + .CK(n_0_39), .D(registers[23]), .Q(registers_9__ap[23]), .QN(), .SE(dftIn), + .SI(registers_31__ap[24]) + ); + SDFF_X1_LVT \registers_reg[28][23] ( + .CK(n_0_58), .D(registers[23]), .Q(registers_28__ap[23]), .QN(), .SE(dftIn), + .SI(registers_27__ap[24]) + ); + AOI22_X1_LVT i_1_0_1163( + .A1(registers_9__ap[23]), .A2(n_1_0_1291), .B1(n_1_0_1283), .B2(registers_28__ap[23]), + .ZN(n_1_0_1107) + ); + SDFF_X1_LVT \registers_reg[18][23] ( + .CK(n_0_48), .D(registers[23]), .Q(registers_18__ap[23]), .QN(), .SE(dftIn), + .SI(registers_23__ap[24]) + ); + SDFF_X1_LVT \registers_reg[22][23] ( + .CK(n_0_52), .D(registers[23]), .Q(registers_22__ap[23]), .QN(), .SE(dftIn), + .SI(registers_18__ap[23]) + ); + AOI22_X1_LVT i_1_0_1160( + .A1(registers_18__ap[23]), .A2(n_1_0_1297), .B1(n_1_0_1294), .B2(registers_22__ap[23]), + .ZN(n_1_0_1104) + ); + SDFF_X1_LVT \registers_reg[1][23] ( + .CK(n_0_0), .D(registers[23]), .Q(registers_1__ap[23]), .QN(), .SE(dftIn), + .SI(registers_22__ap[23]) + ); + SDFF_X1_LVT \registers_reg[21][23] ( + .CK(n_0_51), .D(registers[23]), .Q(registers_21__ap[23]), .QN(), .SE(dftIn), + .SI(registers_1__ap[23]) + ); + AOI22_X1_LVT i_1_0_1159( + .A1(registers_1__ap[23]), .A2(n_1_0_1274), .B1(n_1_0_1259), .B2(registers_21__ap[23]), + .ZN(n_1_0_1103) + ); + NAND3_X1_LVT i_1_0_1157( + .A1(n_1_0_1107), .A2(n_1_0_1104), .A3(n_1_0_1103), .ZN(n_1_0_1101) + ); + SDFF_X1_LVT \registers_reg[20][23] ( + .CK(n_0_50), .D(registers[23]), .Q(registers_20__ap[23]), .QN(), .SE(dftIn), + .SI(registers_21__ap[23]) + ); + SDFF_X1_LVT \registers_reg[19][23] ( + .CK(n_0_49), .D(registers[23]), .Q(registers_19__ap[23]), .QN(), .SE(dftIn), + .SI(registers_20__ap[23]) + ); + AOI221_X1_LVT i_1_0_1156( + .A(n_1_0_1101), .B1(n_1_0_1281), .B2(registers_20__ap[23]), .C1(registers_19__ap[23]), + .C2(n_1_0_1295), .ZN(n_1_0_1100) + ); + SDFF_X1_LVT \registers_reg[26][23] ( + .CK(n_0_56), .D(registers[23]), .Q(registers_26__ap[23]), .QN(), .SE(dftIn), + .SI(registers_28__ap[23]) + ); + SDFF_X1_LVT \registers_reg[23][23] ( + .CK(n_0_53), .D(registers[23]), .Q(registers_23__ap[23]), .QN(), .SE(dftIn), + .SI(registers_19__ap[23]) + ); + AOI22_X1_LVT i_1_0_1162( + .A1(registers_26__ap[23]), .A2(n_1_0_1285), .B1(n_1_0_1264), .B2(registers_23__ap[23]), + .ZN(n_1_0_1106) + ); + SDFF_X1_LVT \registers_reg[29][23] ( + .CK(n_0_59), .D(registers[23]), .Q(registers_29__ap[23]), .QN(), .SE(dftIn), + .SI(registers_26__ap[23]) + ); + SDFF_X1_LVT \registers_reg[3][23] ( + .CK(n_0_33), .D(registers[23]), .Q(registers_3__ap[23]), .QN(), .SE(dftIn), + .SI(registers_9__ap[23]) + ); + AOI22_X1_LVT i_1_0_1161( + .A1(registers_29__ap[23]), .A2(n_1_0_1276), .B1(n_1_0_1257), .B2(registers_3__ap[23]), + .ZN(n_1_0_1105) + ); + SDFF_X1_LVT \registers_reg[30][23] ( + .CK(n_0_60), .D(registers[23]), .Q(registers_30__ap[23]), .QN(), .SE(dftIn), + .SI(registers_29__ap[23]) + ); + SDFF_X1_LVT \registers_reg[31][23] ( + .CK(n_0_61), .D(registers[23]), .Q(registers_31__ap[23]), .QN(), .SE(dftIn), + .SI(registers_3__ap[23]) + ); + AOI22_X1_LVT i_1_0_1158( + .A1(registers_30__ap[23]), .A2(n_1_0_1272), .B1(n_1_0_1266), .B2(registers_31__ap[23]), + .ZN(n_1_0_1102) + ); + NAND3_X1_LVT i_1_0_1155( + .A1(n_1_0_1106), .A2(n_1_0_1105), .A3(n_1_0_1102), .ZN(n_1_0_1099) + ); + SDFF_X1_LVT \registers_reg[8][23] ( + .CK(n_0_38), .D(registers[23]), .Q(registers_8__ap[23]), .QN(), .SE(dftIn), + .SI(registers_31__ap[23]) + ); + SDFF_X1_LVT \registers_reg[17][23] ( + .CK(n_0_47), .D(registers[23]), .Q(registers_17__ap[23]), .QN(), .SE(dftIn), + .SI(registers_23__ap[23]) + ); + AOI221_X1_LVT i_1_0_1154( + .A(n_1_0_1099), .B1(n_1_0_1282), .B2(registers_8__ap[23]), .C1(registers_17__ap[23]), + .C2(n_1_0_1271), .ZN(n_1_0_1098) + ); + SDFF_X1_LVT \registers_reg[24][23] ( + .CK(n_0_54), .D(registers[23]), .Q(registers_24__ap[23]), .QN(), .SE(dftIn), + .SI(registers_30__ap[23]) + ); + SDFF_X1_LVT \registers_reg[15][23] ( + .CK(n_0_45), .D(registers[23]), .Q(registers_15__ap[23]), .QN(), .SE(dftIn), + .SI(registers_14__ap[24]) + ); + SDFF_X1_LVT \registers_reg[14][23] ( + .CK(n_0_44), .D(registers[23]), .Q(registers_14__ap[23]), .QN(), .SE(dftIn), + .SI(registers_15__ap[23]) + ); + AOI222_X1_LVT i_1_0_1153( + .A1(registers_24__ap[23]), .A2(n_1_0_1289), .B1(n_1_0_1286), .B2(registers_15__ap[23]), + .C1(n_1_0_1258), .C2(registers_14__ap[23]), .ZN(n_1_0_1097) + ); + SDFF_X1_LVT \registers_reg[16][23] ( + .CK(n_0_46), .D(registers[23]), .Q(registers_16__ap[23]), .QN(), .SE(dftIn), + .SI(registers_14__ap[23]) + ); + SDFF_X1_LVT \registers_reg[7][23] ( + .CK(n_0_37), .D(registers[23]), .Q(registers_7__ap[23]), .QN(), .SE(dftIn), + .SI(registers_8__ap[23]) + ); + AOI22_X1_LVT i_1_0_1152( + .A1(registers_16__ap[23]), .A2(n_1_0_1267), .B1(n_1_0_1263), .B2(registers_7__ap[23]), + .ZN(n_1_0_1096) + ); + SDFF_X1_LVT \registers_reg[6][23] ( + .CK(n_0_36), .D(registers[23]), .Q(registers_6__ap[23]), .QN(), .SE(dftIn), + .SI(registers_7__ap[23]) + ); + SDFF_X1_LVT \registers_reg[25][23] ( + .CK(n_0_55), .D(registers[23]), .Q(registers_25__ap[23]), .QN(), .SE(dftIn), + .SI(registers_24__ap[23]) + ); + AOI22_X1_LVT i_1_0_1151( + .A1(registers_6__ap[23]), .A2(n_1_0_1300), .B1(n_1_0_1269), .B2(registers_25__ap[23]), + .ZN(n_1_0_1095) + ); + SDFF_X1_LVT \registers_reg[27][23] ( + .CK(n_0_57), .D(registers[23]), .Q(registers_27__ap[23]), .QN(), .SE(dftIn), + .SI(registers_25__ap[23]) + ); + SDFF_X1_LVT \registers_reg[11][23] ( + .CK(n_0_41), .D(registers[23]), .Q(registers_11__ap[23]), .QN(), .SE(dftIn), + .SI(registers_16__ap[23]) + ); + AOI22_X1_LVT i_1_0_1150( + .A1(registers_27__ap[23]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[23]), + .ZN(n_1_0_1094) + ); + SDFF_X1_LVT \registers_reg[13][23] ( + .CK(n_0_43), .D(registers[23]), .Q(registers_13__ap[23]), .QN(), .SE(dftIn), + .SI(registers_11__ap[23]) + ); + SDFF_X1_LVT \registers_reg[5][23] ( + .CK(n_0_35), .D(registers[23]), .Q(registers_5__ap[23]), .QN(), .SE(dftIn), + .SI(registers_6__ap[23]) + ); + AOI22_X1_LVT i_1_0_1149( + .A1(registers_13__ap[23]), .A2(n_1_0_1277), .B1(n_1_0_1273), .B2(registers_5__ap[23]), + .ZN(n_1_0_1093) + ); + SDFF_X1_LVT \registers_reg[4][23] ( + .CK(n_0_34), .D(registers[23]), .Q(registers_4__ap[23]), .QN(), .SE(dftIn), + .SI(registers_5__ap[23]) + ); + SDFF_X1_LVT \registers_reg[12][23] ( + .CK(n_0_42), .D(registers[23]), .Q(registers_12__ap[23]), .QN(), .SE(dftIn), + .SI(registers_13__ap[23]) + ); + AOI22_X1_LVT i_1_0_1148( + .A1(registers_4__ap[23]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[23]), + .ZN(n_1_0_1092) + ); + NAND3_X1_LVT i_1_0_1147( + .A1(n_1_0_1094), .A2(n_1_0_1093), .A3(n_1_0_1092), .ZN(n_1_0_1091) + ); + SDFF_X1_LVT \registers_reg[2][23] ( + .CK(n_0_32), .D(registers[23]), .Q(registers_2__ap[23]), .QN(), .SE(dftIn), + .SI(registers_27__ap[23]) + ); + SDFF_X1_LVT \registers_reg[10][23] ( + .CK(n_0_40), .D(registers[23]), .Q(registers_10__ap[23]), .QN(), .SE(dftIn), + .SI(registers_12__ap[23]) + ); + AOI221_X1_LVT i_1_0_1146( + .A(n_1_0_1091), .B1(n_1_0_1268), .B2(registers_2__ap[23]), .C1(registers_10__ap[23]), + .C2(n_1_0_1287), .ZN(n_1_0_1090) + ); + AND4_X1_LVT i_1_0_1145( + .A1(n_1_0_1097), .A2(n_1_0_1096), .A3(n_1_0_1095), .A4(n_1_0_1090), .ZN(n_1_0_1089) + ); + NAND3_X1_LVT i_1_0_1144( + .A1(n_1_0_1100), .A2(n_1_0_1098), .A3(n_1_0_1089), .ZN(RRs1[23]) + ); + AND2_X1_LVT i_0_0_22( + .A1(n_0_0_16), .A2(WRd[22]), .ZN(registers[22]) + ); + SDFF_X1_LVT \registers_reg[17][22] ( + .CK(n_0_47), .D(registers[22]), .Q(registers_17__ap[22]), .QN(), .SE(dftIn), + .SI(registers_17__ap[23]) + ); + SDFF_X1_LVT \registers_reg[21][22] ( + .CK(n_0_51), .D(registers[22]), .Q(registers_21__ap[22]), .QN(), .SE(dftIn), + .SI(registers_17__ap[22]) + ); + AOI22_X1_LVT i_1_0_1142( + .A1(registers_17__ap[22]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[22]), + .ZN(n_1_0_1087) + ); + SDFF_X1_LVT \registers_reg[6][22] ( + .CK(n_0_36), .D(registers[22]), .Q(registers_6__ap[22]), .QN(), .SE(dftIn), + .SI(registers_4__ap[23]) + ); + SDFF_X1_LVT \registers_reg[11][22] ( + .CK(n_0_41), .D(registers[22]), .Q(registers_11__ap[22]), .QN(), .SE(dftIn), + .SI(registers_10__ap[23]) + ); + AOI22_X1_LVT i_1_0_1143( + .A1(registers_6__ap[22]), .A2(n_1_0_1300), .B1(n_1_0_1270), .B2(registers_11__ap[22]), + .ZN(n_1_0_1088) + ); + SDFF_X1_LVT \registers_reg[20][22] ( + .CK(n_0_50), .D(registers[22]), .Q(registers_20__ap[22]), .QN(), .SE(dftIn), + .SI(registers_21__ap[22]) + ); + SDFF_X1_LVT \registers_reg[12][22] ( + .CK(n_0_42), .D(registers[22]), .Q(registers_12__ap[22]), .QN(), .SE(dftIn), + .SI(registers_11__ap[22]) + ); + AOI22_X1_LVT i_1_0_1141( + .A1(registers_20__ap[22]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[22]), + .ZN(n_1_0_1086) + ); + SDFF_X1_LVT \registers_reg[10][22] ( + .CK(n_0_40), .D(registers[22]), .Q(registers_10__ap[22]), .QN(), .SE(dftIn), + .SI(registers_12__ap[22]) + ); + SDFF_X1_LVT \registers_reg[5][22] ( + .CK(n_0_35), .D(registers[22]), .Q(registers_5__ap[22]), .QN(), .SE(dftIn), + .SI(registers_6__ap[22]) + ); + AOI22_X1_LVT i_1_0_1140( + .A1(registers_10__ap[22]), .A2(n_1_0_1287), .B1(n_1_0_1273), .B2(registers_5__ap[22]), + .ZN(n_1_0_1085) + ); + NAND3_X1_LVT i_1_0_1139( + .A1(n_1_0_1088), .A2(n_1_0_1086), .A3(n_1_0_1085), .ZN(n_1_0_1084) + ); + SDFF_X1_LVT \registers_reg[31][22] ( + .CK(n_0_61), .D(registers[22]), .Q(registers_31__ap[22]), .QN(), .SE(dftIn), + .SI(registers_5__ap[22]) + ); + SDFF_X1_LVT \registers_reg[2][22] ( + .CK(n_0_32), .D(registers[22]), .Q(registers_2__ap[22]), .QN(), .SE(dftIn), + .SI(registers_2__ap[23]) + ); + AOI221_X1_LVT i_1_0_1138( + .A(n_1_0_1084), .B1(n_1_0_1266), .B2(registers_31__ap[22]), .C1(registers_2__ap[22]), + .C2(n_1_0_1268), .ZN(n_1_0_1083) + ); + SDFF_X1_LVT \registers_reg[22][22] ( + .CK(n_0_52), .D(registers[22]), .Q(registers_22__ap[22]), .QN(), .SE(dftIn), + .SI(registers_20__ap[22]) + ); + SDFF_X1_LVT \registers_reg[26][22] ( + .CK(n_0_56), .D(registers[22]), .Q(registers_26__ap[22]), .QN(), .SE(dftIn), + .SI(registers_2__ap[22]) + ); + SDFF_X1_LVT \registers_reg[13][22] ( + .CK(n_0_43), .D(registers[22]), .Q(registers_13__ap[22]), .QN(), .SE(dftIn), + .SI(registers_10__ap[22]) + ); + AOI222_X1_LVT i_1_0_1137( + .A1(registers_22__ap[22]), .A2(n_1_0_1294), .B1(n_1_0_1285), .B2(registers_26__ap[22]), + .C1(n_1_0_1277), .C2(registers_13__ap[22]), .ZN(n_1_0_1082) + ); + NAND2_X1_LVT i_1_0_1136( + .A1(n_1_0_1083), .A2(n_1_0_1082), .ZN(n_1_0_1081) + ); + SDFF_X1_LVT \registers_reg[1][22] ( + .CK(n_0_0), .D(registers[22]), .Q(registers_1__ap[22]), .QN(), .SE(dftIn), + .SI(registers_22__ap[22]) + ); + SDFF_X1_LVT \registers_reg[28][22] ( + .CK(n_0_58), .D(registers[22]), .Q(registers_28__ap[22]), .QN(), .SE(dftIn), + .SI(registers_26__ap[22]) + ); + AOI221_X1_LVT i_1_0_1135( + .A(n_1_0_1081), .B1(n_1_0_1274), .B2(registers_1__ap[22]), .C1(registers_28__ap[22]), + .C2(n_1_0_1283), .ZN(n_1_0_1080) + ); + SDFF_X1_LVT \registers_reg[18][22] ( + .CK(n_0_48), .D(registers[22]), .Q(registers_18__ap[22]), .QN(), .SE(dftIn), + .SI(registers_1__ap[22]) + ); + SDFF_X1_LVT \registers_reg[30][22] ( + .CK(n_0_60), .D(registers[22]), .Q(registers_30__ap[22]), .QN(), .SE(dftIn), + .SI(registers_28__ap[22]) + ); + AOI22_X1_LVT i_1_0_1134( + .A1(registers_18__ap[22]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[22]), + .ZN(n_1_0_1079) + ); + SDFF_X1_LVT \registers_reg[24][22] ( + .CK(n_0_54), .D(registers[22]), .Q(registers_24__ap[22]), .QN(), .SE(dftIn), + .SI(registers_30__ap[22]) + ); + SDFF_X1_LVT \registers_reg[4][22] ( + .CK(n_0_34), .D(registers[22]), .Q(registers_4__ap[22]), .QN(), .SE(dftIn), + .SI(registers_31__ap[22]) + ); + AOI22_X1_LVT i_1_0_1133( + .A1(registers_24__ap[22]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[22]), + .ZN(n_1_0_1078) + ); + SDFF_X1_LVT \registers_reg[15][22] ( + .CK(n_0_45), .D(registers[22]), .Q(registers_15__ap[22]), .QN(), .SE(dftIn), + .SI(registers_13__ap[22]) + ); + SDFF_X1_LVT \registers_reg[16][22] ( + .CK(n_0_46), .D(registers[22]), .Q(registers_16__ap[22]), .QN(), .SE(dftIn), + .SI(registers_15__ap[22]) + ); + AOI22_X1_LVT i_1_0_1132( + .A1(registers_15__ap[22]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[22]), + .ZN(n_1_0_1077) + ); + NAND3_X1_LVT i_1_0_1131( + .A1(n_1_0_1079), .A2(n_1_0_1078), .A3(n_1_0_1077), .ZN(n_1_0_1076) + ); + SDFF_X1_LVT \registers_reg[19][22] ( + .CK(n_0_49), .D(registers[22]), .Q(registers_19__ap[22]), .QN(), .SE(dftIn), + .SI(registers_18__ap[22]) + ); + SDFF_X1_LVT \registers_reg[25][22] ( + .CK(n_0_55), .D(registers[22]), .Q(registers_25__ap[22]), .QN(), .SE(dftIn), + .SI(registers_24__ap[22]) + ); + AOI221_X1_LVT i_1_0_1130( + .A(n_1_0_1076), .B1(n_1_0_1295), .B2(registers_19__ap[22]), .C1(registers_25__ap[22]), + .C2(n_1_0_1269), .ZN(n_1_0_1075) + ); + SDFF_X1_LVT \registers_reg[7][22] ( + .CK(n_0_37), .D(registers[22]), .Q(registers_7__ap[22]), .QN(), .SE(dftIn), + .SI(registers_4__ap[22]) + ); + SDFF_X1_LVT \registers_reg[14][22] ( + .CK(n_0_44), .D(registers[22]), .Q(registers_14__ap[22]), .QN(), .SE(dftIn), + .SI(registers_16__ap[22]) + ); + AOI22_X1_LVT i_1_0_1129( + .A1(registers_7__ap[22]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[22]), + .ZN(n_1_0_1074) + ); + SDFF_X1_LVT \registers_reg[9][22] ( + .CK(n_0_39), .D(registers[22]), .Q(registers_9__ap[22]), .QN(), .SE(dftIn), + .SI(registers_7__ap[22]) + ); + SDFF_X1_LVT \registers_reg[29][22] ( + .CK(n_0_59), .D(registers[22]), .Q(registers_29__ap[22]), .QN(), .SE(dftIn), + .SI(registers_25__ap[22]) + ); + AOI22_X1_LVT i_1_0_1128( + .A1(registers_9__ap[22]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[22]), + .ZN(n_1_0_1073) + ); + SDFF_X1_LVT \registers_reg[8][22] ( + .CK(n_0_38), .D(registers[22]), .Q(registers_8__ap[22]), .QN(), .SE(dftIn), + .SI(registers_9__ap[22]) + ); + SDFF_X1_LVT \registers_reg[23][22] ( + .CK(n_0_53), .D(registers[22]), .Q(registers_23__ap[22]), .QN(), .SE(dftIn), + .SI(registers_19__ap[22]) + ); + AOI22_X1_LVT i_1_0_1127( + .A1(registers_8__ap[22]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[22]), + .ZN(n_1_0_1072) + ); + NAND3_X1_LVT i_1_0_1126( + .A1(n_1_0_1074), .A2(n_1_0_1073), .A3(n_1_0_1072), .ZN(n_1_0_1071) + ); + SDFF_X1_LVT \registers_reg[27][22] ( + .CK(n_0_57), .D(registers[22]), .Q(registers_27__ap[22]), .QN(), .SE(dftIn), + .SI(registers_29__ap[22]) + ); + SDFF_X1_LVT \registers_reg[3][22] ( + .CK(n_0_33), .D(registers[22]), .Q(registers_3__ap[22]), .QN(), .SE(dftIn), + .SI(registers_8__ap[22]) + ); + AOI221_X1_LVT i_1_0_1125( + .A(n_1_0_1071), .B1(n_1_0_1279), .B2(registers_27__ap[22]), .C1(registers_3__ap[22]), + .C2(n_1_0_1257), .ZN(n_1_0_1070) + ); + NAND4_X1_LVT i_1_0_1124( + .A1(n_1_0_1087), .A2(n_1_0_1080), .A3(n_1_0_1075), .A4(n_1_0_1070), .ZN(RRs1[22]) + ); + AND2_X1_LVT i_0_0_21( + .A1(n_0_0_16), .A2(WRd[21]), .ZN(registers[21]) + ); + SDFF_X1_LVT \registers_reg[17][21] ( + .CK(n_0_47), .D(registers[21]), .Q(registers_17__ap[21]), .QN(), .SE(dftIn), + .SI(registers_23__ap[22]) + ); + SDFF_X1_LVT \registers_reg[21][21] ( + .CK(n_0_51), .D(registers[21]), .Q(registers_21__ap[21]), .QN(), .SE(dftIn), + .SI(registers_17__ap[21]) + ); + AOI22_X1_LVT i_1_0_1122( + .A1(registers_17__ap[21]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[21]), + .ZN(n_1_0_1068) + ); + SDFF_X1_LVT \registers_reg[6][21] ( + .CK(n_0_36), .D(registers[21]), .Q(registers_6__ap[21]), .QN(), .SE(dftIn), + .SI(registers_3__ap[22]) + ); + SDFF_X1_LVT \registers_reg[8][21] ( + .CK(n_0_38), .D(registers[21]), .Q(registers_8__ap[21]), .QN(), .SE(dftIn), + .SI(registers_6__ap[21]) + ); + AOI22_X1_LVT i_1_0_1123( + .A1(registers_6__ap[21]), .A2(n_1_0_1300), .B1(n_1_0_1282), .B2(registers_8__ap[21]), + .ZN(n_1_0_1069) + ); + SDFF_X1_LVT \registers_reg[20][21] ( + .CK(n_0_50), .D(registers[21]), .Q(registers_20__ap[21]), .QN(), .SE(dftIn), + .SI(registers_21__ap[21]) + ); + SDFF_X1_LVT \registers_reg[12][21] ( + .CK(n_0_42), .D(registers[21]), .Q(registers_12__ap[21]), .QN(), .SE(dftIn), + .SI(registers_14__ap[22]) + ); + AOI22_X1_LVT i_1_0_1121( + .A1(registers_20__ap[21]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[21]), + .ZN(n_1_0_1067) + ); + SDFF_X1_LVT \registers_reg[5][21] ( + .CK(n_0_35), .D(registers[21]), .Q(registers_5__ap[21]), .QN(), .SE(dftIn), + .SI(registers_8__ap[21]) + ); + SDFF_X1_LVT \registers_reg[11][21] ( + .CK(n_0_41), .D(registers[21]), .Q(registers_11__ap[21]), .QN(), .SE(dftIn), + .SI(registers_12__ap[21]) + ); + AOI22_X1_LVT i_1_0_1120( + .A1(registers_5__ap[21]), .A2(n_1_0_1273), .B1(n_1_0_1270), .B2(registers_11__ap[21]), + .ZN(n_1_0_1066) + ); + NAND3_X1_LVT i_1_0_1119( + .A1(n_1_0_1069), .A2(n_1_0_1067), .A3(n_1_0_1066), .ZN(n_1_0_1065) + ); + SDFF_X1_LVT \registers_reg[10][21] ( + .CK(n_0_40), .D(registers[21]), .Q(registers_10__ap[21]), .QN(), .SE(dftIn), + .SI(registers_11__ap[21]) + ); + SDFF_X1_LVT \registers_reg[2][21] ( + .CK(n_0_32), .D(registers[21]), .Q(registers_2__ap[21]), .QN(), .SE(dftIn), + .SI(registers_27__ap[22]) + ); + AOI221_X1_LVT i_1_0_1118( + .A(n_1_0_1065), .B1(n_1_0_1287), .B2(registers_10__ap[21]), .C1(registers_2__ap[21]), + .C2(n_1_0_1268), .ZN(n_1_0_1064) + ); + SDFF_X1_LVT \registers_reg[13][21] ( + .CK(n_0_43), .D(registers[21]), .Q(registers_13__ap[21]), .QN(), .SE(dftIn), + .SI(registers_10__ap[21]) + ); + SDFF_X1_LVT \registers_reg[30][21] ( + .CK(n_0_60), .D(registers[21]), .Q(registers_30__ap[21]), .QN(), .SE(dftIn), + .SI(registers_2__ap[21]) + ); + SDFF_X1_LVT \registers_reg[22][21] ( + .CK(n_0_52), .D(registers[21]), .Q(registers_22__ap[21]), .QN(), .SE(dftIn), + .SI(registers_20__ap[21]) + ); + AOI222_X1_LVT i_1_0_1117( + .A1(registers_13__ap[21]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[21]), + .C1(registers_22__ap[21]), .C2(n_1_0_1294), .ZN(n_1_0_1063) + ); + NAND2_X1_LVT i_1_0_1116( + .A1(n_1_0_1064), .A2(n_1_0_1063), .ZN(n_1_0_1062) + ); + SDFF_X1_LVT \registers_reg[1][21] ( + .CK(n_0_0), .D(registers[21]), .Q(registers_1__ap[21]), .QN(), .SE(dftIn), + .SI(registers_22__ap[21]) + ); + SDFF_X1_LVT \registers_reg[28][21] ( + .CK(n_0_58), .D(registers[21]), .Q(registers_28__ap[21]), .QN(), .SE(dftIn), + .SI(registers_30__ap[21]) + ); + AOI221_X1_LVT i_1_0_1115( + .A(n_1_0_1062), .B1(n_1_0_1274), .B2(registers_1__ap[21]), .C1(registers_28__ap[21]), + .C2(n_1_0_1283), .ZN(n_1_0_1061) + ); + SDFF_X1_LVT \registers_reg[18][21] ( + .CK(n_0_48), .D(registers[21]), .Q(registers_18__ap[21]), .QN(), .SE(dftIn), + .SI(registers_1__ap[21]) + ); + SDFF_X1_LVT \registers_reg[26][21] ( + .CK(n_0_56), .D(registers[21]), .Q(registers_26__ap[21]), .QN(), .SE(dftIn), + .SI(registers_28__ap[21]) + ); + AOI22_X1_LVT i_1_0_1114( + .A1(registers_18__ap[21]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[21]), + .ZN(n_1_0_1060) + ); + SDFF_X1_LVT \registers_reg[24][21] ( + .CK(n_0_54), .D(registers[21]), .Q(registers_24__ap[21]), .QN(), .SE(dftIn), + .SI(registers_26__ap[21]) + ); + SDFF_X1_LVT \registers_reg[4][21] ( + .CK(n_0_34), .D(registers[21]), .Q(registers_4__ap[21]), .QN(), .SE(dftIn), + .SI(registers_5__ap[21]) + ); + AOI22_X1_LVT i_1_0_1113( + .A1(registers_24__ap[21]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[21]), + .ZN(n_1_0_1059) + ); + SDFF_X1_LVT \registers_reg[15][21] ( + .CK(n_0_45), .D(registers[21]), .Q(registers_15__ap[21]), .QN(), .SE(dftIn), + .SI(registers_13__ap[21]) + ); + SDFF_X1_LVT \registers_reg[16][21] ( + .CK(n_0_46), .D(registers[21]), .Q(registers_16__ap[21]), .QN(), .SE(dftIn), + .SI(registers_15__ap[21]) + ); + AOI22_X1_LVT i_1_0_1112( + .A1(registers_15__ap[21]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[21]), + .ZN(n_1_0_1058) + ); + NAND3_X1_LVT i_1_0_1111( + .A1(n_1_0_1060), .A2(n_1_0_1059), .A3(n_1_0_1058), .ZN(n_1_0_1057) + ); + SDFF_X1_LVT \registers_reg[19][21] ( + .CK(n_0_49), .D(registers[21]), .Q(registers_19__ap[21]), .QN(), .SE(dftIn), + .SI(registers_18__ap[21]) + ); + SDFF_X1_LVT \registers_reg[25][21] ( + .CK(n_0_55), .D(registers[21]), .Q(registers_25__ap[21]), .QN(), .SE(dftIn), + .SI(registers_24__ap[21]) + ); + AOI221_X1_LVT i_1_0_1110( + .A(n_1_0_1057), .B1(n_1_0_1295), .B2(registers_19__ap[21]), .C1(registers_25__ap[21]), + .C2(n_1_0_1269), .ZN(n_1_0_1056) + ); + SDFF_X1_LVT \registers_reg[7][21] ( + .CK(n_0_37), .D(registers[21]), .Q(registers_7__ap[21]), .QN(), .SE(dftIn), + .SI(registers_4__ap[21]) + ); + SDFF_X1_LVT \registers_reg[14][21] ( + .CK(n_0_44), .D(registers[21]), .Q(registers_14__ap[21]), .QN(), .SE(dftIn), + .SI(registers_16__ap[21]) + ); + AOI22_X1_LVT i_1_0_1109( + .A1(registers_7__ap[21]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[21]), + .ZN(n_1_0_1055) + ); + SDFF_X1_LVT \registers_reg[9][21] ( + .CK(n_0_39), .D(registers[21]), .Q(registers_9__ap[21]), .QN(), .SE(dftIn), + .SI(registers_7__ap[21]) + ); + SDFF_X1_LVT \registers_reg[29][21] ( + .CK(n_0_59), .D(registers[21]), .Q(registers_29__ap[21]), .QN(), .SE(dftIn), + .SI(registers_25__ap[21]) + ); + AOI22_X1_LVT i_1_0_1108( + .A1(registers_9__ap[21]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[21]), + .ZN(n_1_0_1054) + ); + SDFF_X1_LVT \registers_reg[23][21] ( + .CK(n_0_53), .D(registers[21]), .Q(registers_23__ap[21]), .QN(), .SE(dftIn), + .SI(registers_19__ap[21]) + ); + SDFF_X1_LVT \registers_reg[3][21] ( + .CK(n_0_33), .D(registers[21]), .Q(registers_3__ap[21]), .QN(), .SE(dftIn), + .SI(registers_9__ap[21]) + ); + AOI22_X1_LVT i_1_0_1107( + .A1(registers_23__ap[21]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[21]), + .ZN(n_1_0_1053) + ); + NAND3_X1_LVT i_1_0_1106( + .A1(n_1_0_1055), .A2(n_1_0_1054), .A3(n_1_0_1053), .ZN(n_1_0_1052) + ); + SDFF_X1_LVT \registers_reg[27][21] ( + .CK(n_0_57), .D(registers[21]), .Q(registers_27__ap[21]), .QN(), .SE(dftIn), + .SI(registers_29__ap[21]) + ); + SDFF_X1_LVT \registers_reg[31][21] ( + .CK(n_0_61), .D(registers[21]), .Q(registers_31__ap[21]), .QN(), .SE(dftIn), + .SI(registers_3__ap[21]) + ); + AOI221_X1_LVT i_1_0_1105( + .A(n_1_0_1052), .B1(n_1_0_1279), .B2(registers_27__ap[21]), .C1(registers_31__ap[21]), + .C2(n_1_0_1266), .ZN(n_1_0_1051) + ); + NAND4_X1_LVT i_1_0_1104( + .A1(n_1_0_1068), .A2(n_1_0_1061), .A3(n_1_0_1056), .A4(n_1_0_1051), .ZN(RRs1[21]) + ); + AND2_X1_LVT i_0_0_20( + .A1(n_0_0_16), .A2(WRd[20]), .ZN(registers[20]) + ); + SDFF_X1_LVT \registers_reg[17][20] ( + .CK(n_0_47), .D(registers[20]), .Q(registers_17__ap[20]), .QN(), .SE(dftIn), + .SI(registers_23__ap[21]) + ); + SDFF_X1_LVT \registers_reg[21][20] ( + .CK(n_0_51), .D(registers[20]), .Q(registers_21__ap[20]), .QN(), .SE(dftIn), + .SI(registers_17__ap[20]) + ); + AOI22_X1_LVT i_1_0_1100( + .A1(registers_17__ap[20]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[20]), + .ZN(n_1_0_1047) + ); + SDFF_X1_LVT \registers_reg[10][20] ( + .CK(n_0_40), .D(registers[20]), .Q(registers_10__ap[20]), .QN(), .SE(dftIn), + .SI(registers_14__ap[21]) + ); + SDFF_X1_LVT \registers_reg[2][20] ( + .CK(n_0_32), .D(registers[20]), .Q(registers_2__ap[20]), .QN(), .SE(dftIn), + .SI(registers_27__ap[21]) + ); + AOI22_X1_LVT i_1_0_1103( + .A1(registers_10__ap[20]), .A2(n_1_0_1287), .B1(n_1_0_1268), .B2(registers_2__ap[20]), + .ZN(n_1_0_1050) + ); + SDFF_X1_LVT \registers_reg[20][20] ( + .CK(n_0_50), .D(registers[20]), .Q(registers_20__ap[20]), .QN(), .SE(dftIn), + .SI(registers_21__ap[20]) + ); + SDFF_X1_LVT \registers_reg[12][20] ( + .CK(n_0_42), .D(registers[20]), .Q(registers_12__ap[20]), .QN(), .SE(dftIn), + .SI(registers_10__ap[20]) + ); + AOI22_X1_LVT i_1_0_1099( + .A1(registers_20__ap[20]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[20]), + .ZN(n_1_0_1046) + ); + SDFF_X1_LVT \registers_reg[15][20] ( + .CK(n_0_45), .D(registers[20]), .Q(registers_15__ap[20]), .QN(), .SE(dftIn), + .SI(registers_12__ap[20]) + ); + SDFF_X1_LVT \registers_reg[8][20] ( + .CK(n_0_38), .D(registers[20]), .Q(registers_8__ap[20]), .QN(), .SE(dftIn), + .SI(registers_31__ap[21]) + ); + AOI22_X1_LVT i_1_0_1102( + .A1(registers_15__ap[20]), .A2(n_1_0_1286), .B1(n_1_0_1282), .B2(registers_8__ap[20]), + .ZN(n_1_0_1049) + ); + INV_X1_LVT i_1_0_1101( + .A(n_1_0_1049), .ZN(n_1_0_1048) + ); + SDFF_X1_LVT \registers_reg[11][20] ( + .CK(n_0_41), .D(registers[20]), .Q(registers_11__ap[20]), .QN(), .SE(dftIn), + .SI(registers_15__ap[20]) + ); + SDFF_X1_LVT \registers_reg[5][20] ( + .CK(n_0_35), .D(registers[20]), .Q(registers_5__ap[20]), .QN(), .SE(dftIn), + .SI(registers_8__ap[20]) + ); + AOI221_X1_LVT i_1_0_1098( + .A(n_1_0_1048), .B1(n_1_0_1270), .B2(registers_11__ap[20]), .C1(registers_5__ap[20]), + .C2(n_1_0_1273), .ZN(n_1_0_1045) + ); + SDFF_X1_LVT \registers_reg[13][20] ( + .CK(n_0_43), .D(registers[20]), .Q(registers_13__ap[20]), .QN(), .SE(dftIn), + .SI(registers_11__ap[20]) + ); + SDFF_X1_LVT \registers_reg[30][20] ( + .CK(n_0_60), .D(registers[20]), .Q(registers_30__ap[20]), .QN(), .SE(dftIn), + .SI(registers_2__ap[20]) + ); + SDFF_X1_LVT \registers_reg[22][20] ( + .CK(n_0_52), .D(registers[20]), .Q(registers_22__ap[20]), .QN(), .SE(dftIn), + .SI(registers_20__ap[20]) + ); + AOI222_X1_LVT i_1_0_1097( + .A1(registers_13__ap[20]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[20]), + .C1(registers_22__ap[20]), .C2(n_1_0_1294), .ZN(n_1_0_1044) + ); + NAND4_X1_LVT i_1_0_1096( + .A1(n_1_0_1050), .A2(n_1_0_1046), .A3(n_1_0_1045), .A4(n_1_0_1044), .ZN(n_1_0_1043) + ); + SDFF_X1_LVT \registers_reg[1][20] ( + .CK(n_0_0), .D(registers[20]), .Q(registers_1__ap[20]), .QN(), .SE(dftIn), + .SI(registers_22__ap[20]) + ); + SDFF_X1_LVT \registers_reg[28][20] ( + .CK(n_0_58), .D(registers[20]), .Q(registers_28__ap[20]), .QN(), .SE(dftIn), + .SI(registers_30__ap[20]) + ); + AOI221_X1_LVT i_1_0_1095( + .A(n_1_0_1043), .B1(n_1_0_1274), .B2(registers_1__ap[20]), .C1(registers_28__ap[20]), + .C2(n_1_0_1283), .ZN(n_1_0_1042) + ); + SDFF_X1_LVT \registers_reg[18][20] ( + .CK(n_0_48), .D(registers[20]), .Q(registers_18__ap[20]), .QN(), .SE(dftIn), + .SI(registers_1__ap[20]) + ); + SDFF_X1_LVT \registers_reg[26][20] ( + .CK(n_0_56), .D(registers[20]), .Q(registers_26__ap[20]), .QN(), .SE(dftIn), + .SI(registers_28__ap[20]) + ); + AOI22_X1_LVT i_1_0_1094( + .A1(registers_18__ap[20]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[20]), + .ZN(n_1_0_1041) + ); + SDFF_X1_LVT \registers_reg[24][20] ( + .CK(n_0_54), .D(registers[20]), .Q(registers_24__ap[20]), .QN(), .SE(dftIn), + .SI(registers_26__ap[20]) + ); + SDFF_X1_LVT \registers_reg[4][20] ( + .CK(n_0_34), .D(registers[20]), .Q(registers_4__ap[20]), .QN(), .SE(dftIn), + .SI(registers_5__ap[20]) + ); + AOI22_X1_LVT i_1_0_1093( + .A1(registers_24__ap[20]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[20]), + .ZN(n_1_0_1040) + ); + SDFF_X1_LVT \registers_reg[6][20] ( + .CK(n_0_36), .D(registers[20]), .Q(registers_6__ap[20]), .QN(), .SE(dftIn), + .SI(registers_4__ap[20]) + ); + SDFF_X1_LVT \registers_reg[25][20] ( + .CK(n_0_55), .D(registers[20]), .Q(registers_25__ap[20]), .QN(), .SE(dftIn), + .SI(registers_24__ap[20]) + ); + AOI22_X1_LVT i_1_0_1092( + .A1(registers_6__ap[20]), .A2(n_1_0_1300), .B1(n_1_0_1269), .B2(registers_25__ap[20]), + .ZN(n_1_0_1039) + ); + NAND3_X1_LVT i_1_0_1091( + .A1(n_1_0_1041), .A2(n_1_0_1040), .A3(n_1_0_1039), .ZN(n_1_0_1038) + ); + SDFF_X1_LVT \registers_reg[19][20] ( + .CK(n_0_49), .D(registers[20]), .Q(registers_19__ap[20]), .QN(), .SE(dftIn), + .SI(registers_18__ap[20]) + ); + SDFF_X1_LVT \registers_reg[16][20] ( + .CK(n_0_46), .D(registers[20]), .Q(registers_16__ap[20]), .QN(), .SE(dftIn), + .SI(registers_13__ap[20]) + ); + AOI221_X1_LVT i_1_0_1090( + .A(n_1_0_1038), .B1(n_1_0_1295), .B2(registers_19__ap[20]), .C1(registers_16__ap[20]), + .C2(n_1_0_1267), .ZN(n_1_0_1037) + ); + SDFF_X1_LVT \registers_reg[7][20] ( + .CK(n_0_37), .D(registers[20]), .Q(registers_7__ap[20]), .QN(), .SE(dftIn), + .SI(registers_6__ap[20]) + ); + SDFF_X1_LVT \registers_reg[14][20] ( + .CK(n_0_44), .D(registers[20]), .Q(registers_14__ap[20]), .QN(), .SE(dftIn), + .SI(registers_16__ap[20]) + ); + AOI22_X1_LVT i_1_0_1089( + .A1(registers_7__ap[20]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[20]), + .ZN(n_1_0_1036) + ); + SDFF_X1_LVT \registers_reg[9][20] ( + .CK(n_0_39), .D(registers[20]), .Q(registers_9__ap[20]), .QN(), .SE(dftIn), + .SI(registers_7__ap[20]) + ); + SDFF_X1_LVT \registers_reg[29][20] ( + .CK(n_0_59), .D(registers[20]), .Q(registers_29__ap[20]), .QN(), .SE(dftIn), + .SI(registers_25__ap[20]) + ); + AOI22_X1_LVT i_1_0_1088( + .A1(registers_9__ap[20]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[20]), + .ZN(n_1_0_1035) + ); + SDFF_X1_LVT \registers_reg[23][20] ( + .CK(n_0_53), .D(registers[20]), .Q(registers_23__ap[20]), .QN(), .SE(dftIn), + .SI(registers_19__ap[20]) + ); + SDFF_X1_LVT \registers_reg[3][20] ( + .CK(n_0_33), .D(registers[20]), .Q(registers_3__ap[20]), .QN(), .SE(dftIn), + .SI(registers_9__ap[20]) + ); + AOI22_X1_LVT i_1_0_1087( + .A1(registers_23__ap[20]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[20]), + .ZN(n_1_0_1034) + ); + NAND3_X1_LVT i_1_0_1086( + .A1(n_1_0_1036), .A2(n_1_0_1035), .A3(n_1_0_1034), .ZN(n_1_0_1033) + ); + SDFF_X1_LVT \registers_reg[27][20] ( + .CK(n_0_57), .D(registers[20]), .Q(registers_27__ap[20]), .QN(), .SE(dftIn), + .SI(registers_29__ap[20]) + ); + SDFF_X1_LVT \registers_reg[31][20] ( + .CK(n_0_61), .D(registers[20]), .Q(registers_31__ap[20]), .QN(), .SE(dftIn), + .SI(registers_3__ap[20]) + ); + AOI221_X1_LVT i_1_0_1085( + .A(n_1_0_1033), .B1(n_1_0_1279), .B2(registers_27__ap[20]), .C1(registers_31__ap[20]), + .C2(n_1_0_1266), .ZN(n_1_0_1032) + ); + NAND4_X1_LVT i_1_0_1084( + .A1(n_1_0_1047), .A2(n_1_0_1042), .A3(n_1_0_1037), .A4(n_1_0_1032), .ZN(RRs1[20]) + ); + AND2_X1_LVT i_0_0_19( + .A1(n_0_0_16), .A2(WRd[19]), .ZN(registers[19]) + ); + SDFF_X1_LVT \registers_reg[17][19] ( + .CK(n_0_47), .D(registers[19]), .Q(registers_17__ap[19]), .QN(), .SE(dftIn), + .SI(registers_23__ap[20]) + ); + SDFF_X1_LVT \registers_reg[21][19] ( + .CK(n_0_51), .D(registers[19]), .Q(registers_21__ap[19]), .QN(), .SE(dftIn), + .SI(registers_17__ap[19]) + ); + AOI22_X1_LVT i_1_0_1080( + .A1(registers_17__ap[19]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[19]), + .ZN(n_1_0_1028) + ); + SDFF_X1_LVT \registers_reg[2][19] ( + .CK(n_0_32), .D(registers[19]), .Q(registers_2__ap[19]), .QN(), .SE(dftIn), + .SI(registers_27__ap[20]) + ); + SDFF_X1_LVT \registers_reg[31][19] ( + .CK(n_0_61), .D(registers[19]), .Q(registers_31__ap[19]), .QN(), .SE(dftIn), + .SI(registers_31__ap[20]) + ); + AOI22_X1_LVT i_1_0_1083( + .A1(registers_2__ap[19]), .A2(n_1_0_1268), .B1(n_1_0_1266), .B2(registers_31__ap[19]), + .ZN(n_1_0_1031) + ); + SDFF_X1_LVT \registers_reg[20][19] ( + .CK(n_0_50), .D(registers[19]), .Q(registers_20__ap[19]), .QN(), .SE(dftIn), + .SI(registers_21__ap[19]) + ); + SDFF_X1_LVT \registers_reg[12][19] ( + .CK(n_0_42), .D(registers[19]), .Q(registers_12__ap[19]), .QN(), .SE(dftIn), + .SI(registers_14__ap[20]) + ); + AOI22_X1_LVT i_1_0_1079( + .A1(registers_20__ap[19]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[19]), + .ZN(n_1_0_1027) + ); + SDFF_X1_LVT \registers_reg[15][19] ( + .CK(n_0_45), .D(registers[19]), .Q(registers_15__ap[19]), .QN(), .SE(dftIn), + .SI(registers_12__ap[19]) + ); + SDFF_X1_LVT \registers_reg[11][19] ( + .CK(n_0_41), .D(registers[19]), .Q(registers_11__ap[19]), .QN(), .SE(dftIn), + .SI(registers_15__ap[19]) + ); + AOI22_X1_LVT i_1_0_1082( + .A1(registers_15__ap[19]), .A2(n_1_0_1286), .B1(n_1_0_1270), .B2(registers_11__ap[19]), + .ZN(n_1_0_1030) + ); + INV_X1_LVT i_1_0_1081( + .A(n_1_0_1030), .ZN(n_1_0_1029) + ); + SDFF_X1_LVT \registers_reg[27][19] ( + .CK(n_0_57), .D(registers[19]), .Q(registers_27__ap[19]), .QN(), .SE(dftIn), + .SI(registers_2__ap[19]) + ); + SDFF_X1_LVT \registers_reg[24][19] ( + .CK(n_0_54), .D(registers[19]), .Q(registers_24__ap[19]), .QN(), .SE(dftIn), + .SI(registers_27__ap[19]) + ); + AOI221_X1_LVT i_1_0_1078( + .A(n_1_0_1029), .B1(n_1_0_1279), .B2(registers_27__ap[19]), .C1(registers_24__ap[19]), + .C2(n_1_0_1289), .ZN(n_1_0_1026) + ); + SDFF_X1_LVT \registers_reg[22][19] ( + .CK(n_0_52), .D(registers[19]), .Q(registers_22__ap[19]), .QN(), .SE(dftIn), + .SI(registers_20__ap[19]) + ); + SDFF_X1_LVT \registers_reg[26][19] ( + .CK(n_0_56), .D(registers[19]), .Q(registers_26__ap[19]), .QN(), .SE(dftIn), + .SI(registers_24__ap[19]) + ); + SDFF_X1_LVT \registers_reg[13][19] ( + .CK(n_0_43), .D(registers[19]), .Q(registers_13__ap[19]), .QN(), .SE(dftIn), + .SI(registers_11__ap[19]) + ); + AOI222_X1_LVT i_1_0_1077( + .A1(registers_22__ap[19]), .A2(n_1_0_1294), .B1(n_1_0_1285), .B2(registers_26__ap[19]), + .C1(n_1_0_1277), .C2(registers_13__ap[19]), .ZN(n_1_0_1025) + ); + NAND4_X1_LVT i_1_0_1076( + .A1(n_1_0_1031), .A2(n_1_0_1027), .A3(n_1_0_1026), .A4(n_1_0_1025), .ZN(n_1_0_1024) + ); + SDFF_X1_LVT \registers_reg[1][19] ( + .CK(n_0_0), .D(registers[19]), .Q(registers_1__ap[19]), .QN(), .SE(dftIn), + .SI(registers_22__ap[19]) + ); + SDFF_X1_LVT \registers_reg[28][19] ( + .CK(n_0_58), .D(registers[19]), .Q(registers_28__ap[19]), .QN(), .SE(dftIn), + .SI(registers_26__ap[19]) + ); + AOI221_X1_LVT i_1_0_1075( + .A(n_1_0_1024), .B1(n_1_0_1274), .B2(registers_1__ap[19]), .C1(registers_28__ap[19]), + .C2(n_1_0_1283), .ZN(n_1_0_1023) + ); + SDFF_X1_LVT \registers_reg[18][19] ( + .CK(n_0_48), .D(registers[19]), .Q(registers_18__ap[19]), .QN(), .SE(dftIn), + .SI(registers_1__ap[19]) + ); + SDFF_X1_LVT \registers_reg[30][19] ( + .CK(n_0_60), .D(registers[19]), .Q(registers_30__ap[19]), .QN(), .SE(dftIn), + .SI(registers_28__ap[19]) + ); + AOI22_X1_LVT i_1_0_1074( + .A1(registers_18__ap[19]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[19]), + .ZN(n_1_0_1022) + ); + SDFF_X1_LVT \registers_reg[4][19] ( + .CK(n_0_34), .D(registers[19]), .Q(registers_4__ap[19]), .QN(), .SE(dftIn), + .SI(registers_31__ap[19]) + ); + SDFF_X1_LVT \registers_reg[5][19] ( + .CK(n_0_35), .D(registers[19]), .Q(registers_5__ap[19]), .QN(), .SE(dftIn), + .SI(registers_4__ap[19]) + ); + AOI22_X1_LVT i_1_0_1073( + .A1(registers_4__ap[19]), .A2(n_1_0_1278), .B1(n_1_0_1273), .B2(registers_5__ap[19]), + .ZN(n_1_0_1021) + ); + SDFF_X1_LVT \registers_reg[6][19] ( + .CK(n_0_36), .D(registers[19]), .Q(registers_6__ap[19]), .QN(), .SE(dftIn), + .SI(registers_5__ap[19]) + ); + SDFF_X1_LVT \registers_reg[25][19] ( + .CK(n_0_55), .D(registers[19]), .Q(registers_25__ap[19]), .QN(), .SE(dftIn), + .SI(registers_30__ap[19]) + ); + AOI22_X1_LVT i_1_0_1072( + .A1(registers_6__ap[19]), .A2(n_1_0_1300), .B1(n_1_0_1269), .B2(registers_25__ap[19]), + .ZN(n_1_0_1020) + ); + NAND3_X1_LVT i_1_0_1071( + .A1(n_1_0_1022), .A2(n_1_0_1021), .A3(n_1_0_1020), .ZN(n_1_0_1019) + ); + SDFF_X1_LVT \registers_reg[19][19] ( + .CK(n_0_49), .D(registers[19]), .Q(registers_19__ap[19]), .QN(), .SE(dftIn), + .SI(registers_18__ap[19]) + ); + SDFF_X1_LVT \registers_reg[16][19] ( + .CK(n_0_46), .D(registers[19]), .Q(registers_16__ap[19]), .QN(), .SE(dftIn), + .SI(registers_13__ap[19]) + ); + AOI221_X1_LVT i_1_0_1070( + .A(n_1_0_1019), .B1(n_1_0_1295), .B2(registers_19__ap[19]), .C1(registers_16__ap[19]), + .C2(n_1_0_1267), .ZN(n_1_0_1018) + ); + SDFF_X1_LVT \registers_reg[9][19] ( + .CK(n_0_39), .D(registers[19]), .Q(registers_9__ap[19]), .QN(), .SE(dftIn), + .SI(registers_6__ap[19]) + ); + SDFF_X1_LVT \registers_reg[29][19] ( + .CK(n_0_59), .D(registers[19]), .Q(registers_29__ap[19]), .QN(), .SE(dftIn), + .SI(registers_25__ap[19]) + ); + AOI22_X1_LVT i_1_0_1069( + .A1(registers_9__ap[19]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[19]), + .ZN(n_1_0_1017) + ); + SDFF_X1_LVT \registers_reg[8][19] ( + .CK(n_0_38), .D(registers[19]), .Q(registers_8__ap[19]), .QN(), .SE(dftIn), + .SI(registers_9__ap[19]) + ); + SDFF_X1_LVT \registers_reg[23][19] ( + .CK(n_0_53), .D(registers[19]), .Q(registers_23__ap[19]), .QN(), .SE(dftIn), + .SI(registers_19__ap[19]) + ); + AOI22_X1_LVT i_1_0_1068( + .A1(registers_8__ap[19]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[19]), + .ZN(n_1_0_1016) + ); + SDFF_X1_LVT \registers_reg[7][19] ( + .CK(n_0_37), .D(registers[19]), .Q(registers_7__ap[19]), .QN(), .SE(dftIn), + .SI(registers_8__ap[19]) + ); + SDFF_X1_LVT \registers_reg[14][19] ( + .CK(n_0_44), .D(registers[19]), .Q(registers_14__ap[19]), .QN(), .SE(dftIn), + .SI(registers_16__ap[19]) + ); + AOI22_X1_LVT i_1_0_1067( + .A1(registers_7__ap[19]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[19]), + .ZN(n_1_0_1015) + ); + NAND3_X1_LVT i_1_0_1066( + .A1(n_1_0_1017), .A2(n_1_0_1016), .A3(n_1_0_1015), .ZN(n_1_0_1014) + ); + SDFF_X1_LVT \registers_reg[10][19] ( + .CK(n_0_40), .D(registers[19]), .Q(registers_10__ap[19]), .QN(), .SE(dftIn), + .SI(registers_14__ap[19]) + ); + SDFF_X1_LVT \registers_reg[3][19] ( + .CK(n_0_33), .D(registers[19]), .Q(registers_3__ap[19]), .QN(), .SE(dftIn), + .SI(registers_7__ap[19]) + ); + AOI221_X1_LVT i_1_0_1065( + .A(n_1_0_1014), .B1(n_1_0_1287), .B2(registers_10__ap[19]), .C1(registers_3__ap[19]), + .C2(n_1_0_1257), .ZN(n_1_0_1013) + ); + NAND4_X1_LVT i_1_0_1064( + .A1(n_1_0_1028), .A2(n_1_0_1023), .A3(n_1_0_1018), .A4(n_1_0_1013), .ZN(RRs1[19]) + ); + AND2_X1_LVT i_0_0_18( + .A1(n_0_0_16), .A2(WRd[18]), .ZN(registers[18]) + ); + SDFF_X1_LVT \registers_reg[24][18] ( + .CK(n_0_54), .D(registers[18]), .Q(registers_24__ap[18]), .QN(), .SE(dftIn), + .SI(registers_29__ap[19]) + ); + SDFF_X1_LVT \registers_reg[28][18] ( + .CK(n_0_58), .D(registers[18]), .Q(registers_28__ap[18]), .QN(), .SE(dftIn), + .SI(registers_24__ap[18]) + ); + AOI22_X1_LVT i_1_0_1062( + .A1(registers_24__ap[18]), .A2(n_1_0_1289), .B1(n_1_0_1283), .B2(registers_28__ap[18]), + .ZN(n_1_0_1011) + ); + SDFF_X1_LVT \registers_reg[11][18] ( + .CK(n_0_41), .D(registers[18]), .Q(registers_11__ap[18]), .QN(), .SE(dftIn), + .SI(registers_10__ap[19]) + ); + SDFF_X1_LVT \registers_reg[16][18] ( + .CK(n_0_46), .D(registers[18]), .Q(registers_16__ap[18]), .QN(), .SE(dftIn), + .SI(registers_11__ap[18]) + ); + AOI22_X1_LVT i_1_0_1063( + .A1(registers_11__ap[18]), .A2(n_1_0_1270), .B1(n_1_0_1267), .B2(registers_16__ap[18]), + .ZN(n_1_0_1012) + ); + SDFF_X1_LVT \registers_reg[9][18] ( + .CK(n_0_39), .D(registers[18]), .Q(registers_9__ap[18]), .QN(), .SE(dftIn), + .SI(registers_3__ap[19]) + ); + SDFF_X1_LVT \registers_reg[7][18] ( + .CK(n_0_37), .D(registers[18]), .Q(registers_7__ap[18]), .QN(), .SE(dftIn), + .SI(registers_9__ap[18]) + ); + AOI22_X1_LVT i_1_0_1061( + .A1(registers_9__ap[18]), .A2(n_1_0_1291), .B1(n_1_0_1263), .B2(registers_7__ap[18]), + .ZN(n_1_0_1010) + ); + SDFF_X1_LVT \registers_reg[27][18] ( + .CK(n_0_57), .D(registers[18]), .Q(registers_27__ap[18]), .QN(), .SE(dftIn), + .SI(registers_28__ap[18]) + ); + SDFF_X1_LVT \registers_reg[25][18] ( + .CK(n_0_55), .D(registers[18]), .Q(registers_25__ap[18]), .QN(), .SE(dftIn), + .SI(registers_27__ap[18]) + ); + AOI22_X1_LVT i_1_0_1060( + .A1(registers_27__ap[18]), .A2(n_1_0_1279), .B1(n_1_0_1269), .B2(registers_25__ap[18]), + .ZN(n_1_0_1009) + ); + NAND3_X1_LVT i_1_0_1059( + .A1(n_1_0_1012), .A2(n_1_0_1010), .A3(n_1_0_1009), .ZN(n_1_0_1008) + ); + SDFF_X1_LVT \registers_reg[31][18] ( + .CK(n_0_61), .D(registers[18]), .Q(registers_31__ap[18]), .QN(), .SE(dftIn), + .SI(registers_7__ap[18]) + ); + SDFF_X1_LVT \registers_reg[6][18] ( + .CK(n_0_36), .D(registers[18]), .Q(registers_6__ap[18]), .QN(), .SE(dftIn), + .SI(registers_31__ap[18]) + ); + AOI221_X1_LVT i_1_0_1058( + .A(n_1_0_1008), .B1(n_1_0_1266), .B2(registers_31__ap[18]), .C1(registers_6__ap[18]), + .C2(n_1_0_1300), .ZN(n_1_0_1007) + ); + SDFF_X1_LVT \registers_reg[22][18] ( + .CK(n_0_52), .D(registers[18]), .Q(registers_22__ap[18]), .QN(), .SE(dftIn), + .SI(registers_23__ap[19]) + ); + SDFF_X1_LVT \registers_reg[26][18] ( + .CK(n_0_56), .D(registers[18]), .Q(registers_26__ap[18]), .QN(), .SE(dftIn), + .SI(registers_25__ap[18]) + ); + SDFF_X1_LVT \registers_reg[1][18] ( + .CK(n_0_0), .D(registers[18]), .Q(registers_1__ap[18]), .QN(), .SE(dftIn), + .SI(registers_22__ap[18]) + ); + AOI222_X1_LVT i_1_0_1057( + .A1(registers_22__ap[18]), .A2(n_1_0_1294), .B1(n_1_0_1285), .B2(registers_26__ap[18]), + .C1(n_1_0_1274), .C2(registers_1__ap[18]), .ZN(n_1_0_1006) + ); + NAND2_X1_LVT i_1_0_1056( + .A1(n_1_0_1007), .A2(n_1_0_1006), .ZN(n_1_0_1005) + ); + SDFF_X1_LVT \registers_reg[29][18] ( + .CK(n_0_59), .D(registers[18]), .Q(registers_29__ap[18]), .QN(), .SE(dftIn), + .SI(registers_26__ap[18]) + ); + SDFF_X1_LVT \registers_reg[2][18] ( + .CK(n_0_32), .D(registers[18]), .Q(registers_2__ap[18]), .QN(), .SE(dftIn), + .SI(registers_29__ap[18]) + ); + AOI221_X1_LVT i_1_0_1055( + .A(n_1_0_1005), .B1(n_1_0_1276), .B2(registers_29__ap[18]), .C1(registers_2__ap[18]), + .C2(n_1_0_1268), .ZN(n_1_0_1004) + ); + SDFF_X1_LVT \registers_reg[18][18] ( + .CK(n_0_48), .D(registers[18]), .Q(registers_18__ap[18]), .QN(), .SE(dftIn), + .SI(registers_1__ap[18]) + ); + SDFF_X1_LVT \registers_reg[30][18] ( + .CK(n_0_60), .D(registers[18]), .Q(registers_30__ap[18]), .QN(), .SE(dftIn), + .SI(registers_2__ap[18]) + ); + AOI22_X1_LVT i_1_0_1054( + .A1(registers_18__ap[18]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[18]), + .ZN(n_1_0_1003) + ); + SDFF_X1_LVT \registers_reg[4][18] ( + .CK(n_0_34), .D(registers[18]), .Q(registers_4__ap[18]), .QN(), .SE(dftIn), + .SI(registers_6__ap[18]) + ); + SDFF_X1_LVT \registers_reg[12][18] ( + .CK(n_0_42), .D(registers[18]), .Q(registers_12__ap[18]), .QN(), .SE(dftIn), + .SI(registers_16__ap[18]) + ); + AOI22_X1_LVT i_1_0_1053( + .A1(registers_4__ap[18]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[18]), + .ZN(n_1_0_1002) + ); + SDFF_X1_LVT \registers_reg[19][18] ( + .CK(n_0_49), .D(registers[18]), .Q(registers_19__ap[18]), .QN(), .SE(dftIn), + .SI(registers_18__ap[18]) + ); + SDFF_X1_LVT \registers_reg[21][18] ( + .CK(n_0_51), .D(registers[18]), .Q(registers_21__ap[18]), .QN(), .SE(dftIn), + .SI(registers_19__ap[18]) + ); + AOI22_X1_LVT i_1_0_1052( + .A1(registers_19__ap[18]), .A2(n_1_0_1295), .B1(n_1_0_1259), .B2(registers_21__ap[18]), + .ZN(n_1_0_1001) + ); + NAND3_X1_LVT i_1_0_1051( + .A1(n_1_0_1003), .A2(n_1_0_1002), .A3(n_1_0_1001), .ZN(n_1_0_1000) + ); + SDFF_X1_LVT \registers_reg[5][18] ( + .CK(n_0_35), .D(registers[18]), .Q(registers_5__ap[18]), .QN(), .SE(dftIn), + .SI(registers_4__ap[18]) + ); + SDFF_X1_LVT \registers_reg[20][18] ( + .CK(n_0_50), .D(registers[18]), .Q(registers_20__ap[18]), .QN(), .SE(dftIn), + .SI(registers_21__ap[18]) + ); + AOI221_X1_LVT i_1_0_1050( + .A(n_1_0_1000), .B1(n_1_0_1273), .B2(registers_5__ap[18]), .C1(registers_20__ap[18]), + .C2(n_1_0_1281), .ZN(n_1_0_999) + ); + SDFF_X1_LVT \registers_reg[8][18] ( + .CK(n_0_38), .D(registers[18]), .Q(registers_8__ap[18]), .QN(), .SE(dftIn), + .SI(registers_5__ap[18]) + ); + SDFF_X1_LVT \registers_reg[23][18] ( + .CK(n_0_53), .D(registers[18]), .Q(registers_23__ap[18]), .QN(), .SE(dftIn), + .SI(registers_20__ap[18]) + ); + AOI22_X1_LVT i_1_0_1049( + .A1(registers_8__ap[18]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[18]), + .ZN(n_1_0_998) + ); + SDFF_X1_LVT \registers_reg[13][18] ( + .CK(n_0_43), .D(registers[18]), .Q(registers_13__ap[18]), .QN(), .SE(dftIn), + .SI(registers_12__ap[18]) + ); + SDFF_X1_LVT \registers_reg[17][18] ( + .CK(n_0_47), .D(registers[18]), .Q(registers_17__ap[18]), .QN(), .SE(dftIn), + .SI(registers_23__ap[18]) + ); + AOI22_X1_LVT i_1_0_1048( + .A1(registers_13__ap[18]), .A2(n_1_0_1277), .B1(n_1_0_1271), .B2(registers_17__ap[18]), + .ZN(n_1_0_997) + ); + SDFF_X1_LVT \registers_reg[15][18] ( + .CK(n_0_45), .D(registers[18]), .Q(registers_15__ap[18]), .QN(), .SE(dftIn), + .SI(registers_13__ap[18]) + ); + SDFF_X1_LVT \registers_reg[14][18] ( + .CK(n_0_44), .D(registers[18]), .Q(registers_14__ap[18]), .QN(), .SE(dftIn), + .SI(registers_15__ap[18]) + ); + AOI22_X1_LVT i_1_0_1047( + .A1(registers_15__ap[18]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[18]), + .ZN(n_1_0_996) + ); + NAND3_X1_LVT i_1_0_1046( + .A1(n_1_0_998), .A2(n_1_0_997), .A3(n_1_0_996), .ZN(n_1_0_995) + ); + SDFF_X1_LVT \registers_reg[10][18] ( + .CK(n_0_40), .D(registers[18]), .Q(registers_10__ap[18]), .QN(), .SE(dftIn), + .SI(registers_14__ap[18]) + ); + SDFF_X1_LVT \registers_reg[3][18] ( + .CK(n_0_33), .D(registers[18]), .Q(registers_3__ap[18]), .QN(), .SE(dftIn), + .SI(registers_8__ap[18]) + ); + AOI221_X1_LVT i_1_0_1045( + .A(n_1_0_995), .B1(n_1_0_1287), .B2(registers_10__ap[18]), .C1(registers_3__ap[18]), + .C2(n_1_0_1257), .ZN(n_1_0_994) + ); + NAND4_X1_LVT i_1_0_1044( + .A1(n_1_0_1011), .A2(n_1_0_1004), .A3(n_1_0_999), .A4(n_1_0_994), .ZN(RRs1[18]) + ); + AND2_X1_LVT i_0_0_17( + .A1(n_0_0_16), .A2(WRd[17]), .ZN(registers[17]) + ); + SDFF_X1_LVT \registers_reg[17][17] ( + .CK(n_0_47), .D(registers[17]), .Q(registers_17__ap[17]), .QN(), .SE(dftIn), + .SI(registers_17__ap[18]) + ); + SDFF_X1_LVT \registers_reg[21][17] ( + .CK(n_0_51), .D(registers[17]), .Q(registers_21__ap[17]), .QN(), .SE(dftIn), + .SI(registers_17__ap[17]) + ); + AOI22_X1_LVT i_1_0_1040( + .A1(registers_17__ap[17]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[17]), + .ZN(n_1_0_990) + ); + SDFF_X1_LVT \registers_reg[2][17] ( + .CK(n_0_32), .D(registers[17]), .Q(registers_2__ap[17]), .QN(), .SE(dftIn), + .SI(registers_30__ap[18]) + ); + SDFF_X1_LVT \registers_reg[31][17] ( + .CK(n_0_61), .D(registers[17]), .Q(registers_31__ap[17]), .QN(), .SE(dftIn), + .SI(registers_3__ap[18]) + ); + AOI22_X1_LVT i_1_0_1043( + .A1(registers_2__ap[17]), .A2(n_1_0_1268), .B1(n_1_0_1266), .B2(registers_31__ap[17]), + .ZN(n_1_0_993) + ); + SDFF_X1_LVT \registers_reg[20][17] ( + .CK(n_0_50), .D(registers[17]), .Q(registers_20__ap[17]), .QN(), .SE(dftIn), + .SI(registers_21__ap[17]) + ); + SDFF_X1_LVT \registers_reg[12][17] ( + .CK(n_0_42), .D(registers[17]), .Q(registers_12__ap[17]), .QN(), .SE(dftIn), + .SI(registers_10__ap[18]) + ); + AOI22_X1_LVT i_1_0_1039( + .A1(registers_20__ap[17]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[17]), + .ZN(n_1_0_989) + ); + SDFF_X1_LVT \registers_reg[15][17] ( + .CK(n_0_45), .D(registers[17]), .Q(registers_15__ap[17]), .QN(), .SE(dftIn), + .SI(registers_12__ap[17]) + ); + SDFF_X1_LVT \registers_reg[11][17] ( + .CK(n_0_41), .D(registers[17]), .Q(registers_11__ap[17]), .QN(), .SE(dftIn), + .SI(registers_15__ap[17]) + ); + AOI22_X1_LVT i_1_0_1042( + .A1(registers_15__ap[17]), .A2(n_1_0_1286), .B1(n_1_0_1270), .B2(registers_11__ap[17]), + .ZN(n_1_0_992) + ); + INV_X1_LVT i_1_0_1041( + .A(n_1_0_992), .ZN(n_1_0_991) + ); + SDFF_X1_LVT \registers_reg[10][17] ( + .CK(n_0_40), .D(registers[17]), .Q(registers_10__ap[17]), .QN(), .SE(dftIn), + .SI(registers_11__ap[17]) + ); + SDFF_X1_LVT \registers_reg[24][17] ( + .CK(n_0_54), .D(registers[17]), .Q(registers_24__ap[17]), .QN(), .SE(dftIn), + .SI(registers_2__ap[17]) + ); + AOI221_X1_LVT i_1_0_1038( + .A(n_1_0_991), .B1(n_1_0_1287), .B2(registers_10__ap[17]), .C1(registers_24__ap[17]), + .C2(n_1_0_1289), .ZN(n_1_0_988) + ); + SDFF_X1_LVT \registers_reg[22][17] ( + .CK(n_0_52), .D(registers[17]), .Q(registers_22__ap[17]), .QN(), .SE(dftIn), + .SI(registers_20__ap[17]) + ); + SDFF_X1_LVT \registers_reg[26][17] ( + .CK(n_0_56), .D(registers[17]), .Q(registers_26__ap[17]), .QN(), .SE(dftIn), + .SI(registers_24__ap[17]) + ); + SDFF_X1_LVT \registers_reg[13][17] ( + .CK(n_0_43), .D(registers[17]), .Q(registers_13__ap[17]), .QN(), .SE(dftIn), + .SI(registers_10__ap[17]) + ); + AOI222_X1_LVT i_1_0_1037( + .A1(registers_22__ap[17]), .A2(n_1_0_1294), .B1(n_1_0_1285), .B2(registers_26__ap[17]), + .C1(n_1_0_1277), .C2(registers_13__ap[17]), .ZN(n_1_0_987) + ); + NAND4_X1_LVT i_1_0_1036( + .A1(n_1_0_993), .A2(n_1_0_989), .A3(n_1_0_988), .A4(n_1_0_987), .ZN(n_1_0_986) + ); + SDFF_X1_LVT \registers_reg[1][17] ( + .CK(n_0_0), .D(registers[17]), .Q(registers_1__ap[17]), .QN(), .SE(dftIn), + .SI(registers_22__ap[17]) + ); + SDFF_X1_LVT \registers_reg[28][17] ( + .CK(n_0_58), .D(registers[17]), .Q(registers_28__ap[17]), .QN(), .SE(dftIn), + .SI(registers_26__ap[17]) + ); + AOI221_X1_LVT i_1_0_1035( + .A(n_1_0_986), .B1(n_1_0_1274), .B2(registers_1__ap[17]), .C1(registers_28__ap[17]), + .C2(n_1_0_1283), .ZN(n_1_0_985) + ); + SDFF_X1_LVT \registers_reg[18][17] ( + .CK(n_0_48), .D(registers[17]), .Q(registers_18__ap[17]), .QN(), .SE(dftIn), + .SI(registers_1__ap[17]) + ); + SDFF_X1_LVT \registers_reg[30][17] ( + .CK(n_0_60), .D(registers[17]), .Q(registers_30__ap[17]), .QN(), .SE(dftIn), + .SI(registers_28__ap[17]) + ); + AOI22_X1_LVT i_1_0_1034( + .A1(registers_18__ap[17]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[17]), + .ZN(n_1_0_984) + ); + SDFF_X1_LVT \registers_reg[4][17] ( + .CK(n_0_34), .D(registers[17]), .Q(registers_4__ap[17]), .QN(), .SE(dftIn), + .SI(registers_31__ap[17]) + ); + SDFF_X1_LVT \registers_reg[5][17] ( + .CK(n_0_35), .D(registers[17]), .Q(registers_5__ap[17]), .QN(), .SE(dftIn), + .SI(registers_4__ap[17]) + ); + AOI22_X1_LVT i_1_0_1033( + .A1(registers_4__ap[17]), .A2(n_1_0_1278), .B1(n_1_0_1273), .B2(registers_5__ap[17]), + .ZN(n_1_0_983) + ); + SDFF_X1_LVT \registers_reg[6][17] ( + .CK(n_0_36), .D(registers[17]), .Q(registers_6__ap[17]), .QN(), .SE(dftIn), + .SI(registers_5__ap[17]) + ); + SDFF_X1_LVT \registers_reg[25][17] ( + .CK(n_0_55), .D(registers[17]), .Q(registers_25__ap[17]), .QN(), .SE(dftIn), + .SI(registers_30__ap[17]) + ); + AOI22_X1_LVT i_1_0_1032( + .A1(registers_6__ap[17]), .A2(n_1_0_1300), .B1(n_1_0_1269), .B2(registers_25__ap[17]), + .ZN(n_1_0_982) + ); + NAND3_X1_LVT i_1_0_1031( + .A1(n_1_0_984), .A2(n_1_0_983), .A3(n_1_0_982), .ZN(n_1_0_981) + ); + SDFF_X1_LVT \registers_reg[19][17] ( + .CK(n_0_49), .D(registers[17]), .Q(registers_19__ap[17]), .QN(), .SE(dftIn), + .SI(registers_18__ap[17]) + ); + SDFF_X1_LVT \registers_reg[16][17] ( + .CK(n_0_46), .D(registers[17]), .Q(registers_16__ap[17]), .QN(), .SE(dftIn), + .SI(registers_13__ap[17]) + ); + AOI221_X1_LVT i_1_0_1030( + .A(n_1_0_981), .B1(n_1_0_1295), .B2(registers_19__ap[17]), .C1(registers_16__ap[17]), + .C2(n_1_0_1267), .ZN(n_1_0_980) + ); + SDFF_X1_LVT \registers_reg[7][17] ( + .CK(n_0_37), .D(registers[17]), .Q(registers_7__ap[17]), .QN(), .SE(dftIn), + .SI(registers_6__ap[17]) + ); + SDFF_X1_LVT \registers_reg[14][17] ( + .CK(n_0_44), .D(registers[17]), .Q(registers_14__ap[17]), .QN(), .SE(dftIn), + .SI(registers_16__ap[17]) + ); + AOI22_X1_LVT i_1_0_1029( + .A1(registers_7__ap[17]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[17]), + .ZN(n_1_0_979) + ); + SDFF_X1_LVT \registers_reg[9][17] ( + .CK(n_0_39), .D(registers[17]), .Q(registers_9__ap[17]), .QN(), .SE(dftIn), + .SI(registers_7__ap[17]) + ); + SDFF_X1_LVT \registers_reg[29][17] ( + .CK(n_0_59), .D(registers[17]), .Q(registers_29__ap[17]), .QN(), .SE(dftIn), + .SI(registers_25__ap[17]) + ); + AOI22_X1_LVT i_1_0_1028( + .A1(registers_9__ap[17]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[17]), + .ZN(n_1_0_978) + ); + SDFF_X1_LVT \registers_reg[8][17] ( + .CK(n_0_38), .D(registers[17]), .Q(registers_8__ap[17]), .QN(), .SE(dftIn), + .SI(registers_9__ap[17]) + ); + SDFF_X1_LVT \registers_reg[23][17] ( + .CK(n_0_53), .D(registers[17]), .Q(registers_23__ap[17]), .QN(), .SE(dftIn), + .SI(registers_19__ap[17]) + ); + AOI22_X1_LVT i_1_0_1027( + .A1(registers_8__ap[17]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[17]), + .ZN(n_1_0_977) + ); + NAND3_X1_LVT i_1_0_1026( + .A1(n_1_0_979), .A2(n_1_0_978), .A3(n_1_0_977), .ZN(n_1_0_976) + ); + SDFF_X1_LVT \registers_reg[27][17] ( + .CK(n_0_57), .D(registers[17]), .Q(registers_27__ap[17]), .QN(), .SE(dftIn), + .SI(registers_29__ap[17]) + ); + SDFF_X1_LVT \registers_reg[3][17] ( + .CK(n_0_33), .D(registers[17]), .Q(registers_3__ap[17]), .QN(), .SE(dftIn), + .SI(registers_8__ap[17]) + ); + AOI221_X1_LVT i_1_0_1025( + .A(n_1_0_976), .B1(n_1_0_1279), .B2(registers_27__ap[17]), .C1(registers_3__ap[17]), + .C2(n_1_0_1257), .ZN(n_1_0_975) + ); + NAND4_X1_LVT i_1_0_1024( + .A1(n_1_0_990), .A2(n_1_0_985), .A3(n_1_0_980), .A4(n_1_0_975), .ZN(RRs1[17]) + ); + AND2_X1_LVT i_0_0_16( + .A1(n_0_0_16), .A2(WRd[16]), .ZN(registers[16]) + ); + SDFF_X1_LVT \registers_reg[29][16] ( + .CK(n_0_59), .D(registers[16]), .Q(registers_29__ap[16]), .QN(), .SE(dftIn), + .SI(registers_27__ap[17]) + ); + SDFF_X1_LVT \registers_reg[2][16] ( + .CK(n_0_32), .D(registers[16]), .Q(registers_2__ap[16]), .QN(), .SE(dftIn), + .SI(registers_29__ap[16]) + ); + AOI22_X1_LVT i_1_0_1022( + .A1(registers_29__ap[16]), .A2(n_1_0_1276), .B1(n_1_0_1268), .B2(registers_2__ap[16]), + .ZN(n_1_0_973) + ); + SDFF_X1_LVT \registers_reg[11][16] ( + .CK(n_0_41), .D(registers[16]), .Q(registers_11__ap[16]), .QN(), .SE(dftIn), + .SI(registers_14__ap[17]) + ); + SDFF_X1_LVT \registers_reg[25][16] ( + .CK(n_0_55), .D(registers[16]), .Q(registers_25__ap[16]), .QN(), .SE(dftIn), + .SI(registers_2__ap[16]) + ); + AOI22_X1_LVT i_1_0_1023( + .A1(registers_11__ap[16]), .A2(n_1_0_1270), .B1(n_1_0_1269), .B2(registers_25__ap[16]), + .ZN(n_1_0_974) + ); + SDFF_X1_LVT \registers_reg[9][16] ( + .CK(n_0_39), .D(registers[16]), .Q(registers_9__ap[16]), .QN(), .SE(dftIn), + .SI(registers_3__ap[17]) + ); + SDFF_X1_LVT \registers_reg[7][16] ( + .CK(n_0_37), .D(registers[16]), .Q(registers_7__ap[16]), .QN(), .SE(dftIn), + .SI(registers_9__ap[16]) + ); + AOI22_X1_LVT i_1_0_1021( + .A1(registers_9__ap[16]), .A2(n_1_0_1291), .B1(n_1_0_1263), .B2(registers_7__ap[16]), + .ZN(n_1_0_972) + ); + SDFF_X1_LVT \registers_reg[10][16] ( + .CK(n_0_40), .D(registers[16]), .Q(registers_10__ap[16]), .QN(), .SE(dftIn), + .SI(registers_11__ap[16]) + ); + SDFF_X1_LVT \registers_reg[16][16] ( + .CK(n_0_46), .D(registers[16]), .Q(registers_16__ap[16]), .QN(), .SE(dftIn), + .SI(registers_10__ap[16]) + ); + AOI22_X1_LVT i_1_0_1020( + .A1(registers_10__ap[16]), .A2(n_1_0_1287), .B1(n_1_0_1267), .B2(registers_16__ap[16]), + .ZN(n_1_0_971) + ); + NAND3_X1_LVT i_1_0_1019( + .A1(n_1_0_974), .A2(n_1_0_972), .A3(n_1_0_971), .ZN(n_1_0_970) + ); + SDFF_X1_LVT \registers_reg[31][16] ( + .CK(n_0_61), .D(registers[16]), .Q(registers_31__ap[16]), .QN(), .SE(dftIn), + .SI(registers_7__ap[16]) + ); + SDFF_X1_LVT \registers_reg[6][16] ( + .CK(n_0_36), .D(registers[16]), .Q(registers_6__ap[16]), .QN(), .SE(dftIn), + .SI(registers_31__ap[16]) + ); + AOI221_X1_LVT i_1_0_1018( + .A(n_1_0_970), .B1(n_1_0_1266), .B2(registers_31__ap[16]), .C1(registers_6__ap[16]), + .C2(n_1_0_1300), .ZN(n_1_0_969) + ); + SDFF_X1_LVT \registers_reg[18][16] ( + .CK(n_0_48), .D(registers[16]), .Q(registers_18__ap[16]), .QN(), .SE(dftIn), + .SI(registers_23__ap[17]) + ); + SDFF_X1_LVT \registers_reg[22][16] ( + .CK(n_0_52), .D(registers[16]), .Q(registers_22__ap[16]), .QN(), .SE(dftIn), + .SI(registers_18__ap[16]) + ); + SDFF_X1_LVT \registers_reg[1][16] ( + .CK(n_0_0), .D(registers[16]), .Q(registers_1__ap[16]), .QN(), .SE(dftIn), + .SI(registers_22__ap[16]) + ); + AOI222_X1_LVT i_1_0_1017( + .A1(registers_18__ap[16]), .A2(n_1_0_1297), .B1(n_1_0_1294), .B2(registers_22__ap[16]), + .C1(registers_1__ap[16]), .C2(n_1_0_1274), .ZN(n_1_0_968) + ); + NAND3_X1_LVT i_1_0_1016( + .A1(n_1_0_973), .A2(n_1_0_969), .A3(n_1_0_968), .ZN(n_1_0_967) + ); + SDFF_X1_LVT \registers_reg[5][16] ( + .CK(n_0_35), .D(registers[16]), .Q(registers_5__ap[16]), .QN(), .SE(dftIn), + .SI(registers_6__ap[16]) + ); + SDFF_X1_LVT \registers_reg[28][16] ( + .CK(n_0_58), .D(registers[16]), .Q(registers_28__ap[16]), .QN(), .SE(dftIn), + .SI(registers_25__ap[16]) + ); + AOI221_X1_LVT i_1_0_1015( + .A(n_1_0_967), .B1(n_1_0_1273), .B2(registers_5__ap[16]), .C1(registers_28__ap[16]), + .C2(n_1_0_1283), .ZN(n_1_0_966) + ); + SDFF_X1_LVT \registers_reg[4][16] ( + .CK(n_0_34), .D(registers[16]), .Q(registers_4__ap[16]), .QN(), .SE(dftIn), + .SI(registers_5__ap[16]) + ); + SDFF_X1_LVT \registers_reg[12][16] ( + .CK(n_0_42), .D(registers[16]), .Q(registers_12__ap[16]), .QN(), .SE(dftIn), + .SI(registers_16__ap[16]) + ); + AOI22_X1_LVT i_1_0_1014( + .A1(registers_4__ap[16]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[16]), + .ZN(n_1_0_965) + ); + SDFF_X1_LVT \registers_reg[19][16] ( + .CK(n_0_49), .D(registers[16]), .Q(registers_19__ap[16]), .QN(), .SE(dftIn), + .SI(registers_1__ap[16]) + ); + SDFF_X1_LVT \registers_reg[21][16] ( + .CK(n_0_51), .D(registers[16]), .Q(registers_21__ap[16]), .QN(), .SE(dftIn), + .SI(registers_19__ap[16]) + ); + AOI22_X1_LVT i_1_0_1013( + .A1(registers_19__ap[16]), .A2(n_1_0_1295), .B1(n_1_0_1259), .B2(registers_21__ap[16]), + .ZN(n_1_0_964) + ); + SDFF_X1_LVT \registers_reg[24][16] ( + .CK(n_0_54), .D(registers[16]), .Q(registers_24__ap[16]), .QN(), .SE(dftIn), + .SI(registers_28__ap[16]) + ); + SDFF_X1_LVT \registers_reg[20][16] ( + .CK(n_0_50), .D(registers[16]), .Q(registers_20__ap[16]), .QN(), .SE(dftIn), + .SI(registers_21__ap[16]) + ); + AOI22_X1_LVT i_1_0_1012( + .A1(registers_24__ap[16]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[16]), + .ZN(n_1_0_963) + ); + NAND3_X1_LVT i_1_0_1011( + .A1(n_1_0_965), .A2(n_1_0_964), .A3(n_1_0_963), .ZN(n_1_0_962) + ); + SDFF_X1_LVT \registers_reg[26][16] ( + .CK(n_0_56), .D(registers[16]), .Q(registers_26__ap[16]), .QN(), .SE(dftIn), + .SI(registers_24__ap[16]) + ); + SDFF_X1_LVT \registers_reg[30][16] ( + .CK(n_0_60), .D(registers[16]), .Q(registers_30__ap[16]), .QN(), .SE(dftIn), + .SI(registers_26__ap[16]) + ); + AOI221_X1_LVT i_1_0_1010( + .A(n_1_0_962), .B1(n_1_0_1285), .B2(registers_26__ap[16]), .C1(registers_30__ap[16]), + .C2(n_1_0_1272), .ZN(n_1_0_961) + ); + SDFF_X1_LVT \registers_reg[8][16] ( + .CK(n_0_38), .D(registers[16]), .Q(registers_8__ap[16]), .QN(), .SE(dftIn), + .SI(registers_4__ap[16]) + ); + SDFF_X1_LVT \registers_reg[23][16] ( + .CK(n_0_53), .D(registers[16]), .Q(registers_23__ap[16]), .QN(), .SE(dftIn), + .SI(registers_20__ap[16]) + ); + AOI22_X1_LVT i_1_0_1009( + .A1(registers_8__ap[16]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[16]), + .ZN(n_1_0_960) + ); + SDFF_X1_LVT \registers_reg[13][16] ( + .CK(n_0_43), .D(registers[16]), .Q(registers_13__ap[16]), .QN(), .SE(dftIn), + .SI(registers_12__ap[16]) + ); + SDFF_X1_LVT \registers_reg[17][16] ( + .CK(n_0_47), .D(registers[16]), .Q(registers_17__ap[16]), .QN(), .SE(dftIn), + .SI(registers_23__ap[16]) + ); + AOI22_X1_LVT i_1_0_1008( + .A1(registers_13__ap[16]), .A2(n_1_0_1277), .B1(n_1_0_1271), .B2(registers_17__ap[16]), + .ZN(n_1_0_959) + ); + SDFF_X1_LVT \registers_reg[15][16] ( + .CK(n_0_45), .D(registers[16]), .Q(registers_15__ap[16]), .QN(), .SE(dftIn), + .SI(registers_13__ap[16]) + ); + SDFF_X1_LVT \registers_reg[14][16] ( + .CK(n_0_44), .D(registers[16]), .Q(registers_14__ap[16]), .QN(), .SE(dftIn), + .SI(registers_15__ap[16]) + ); + AOI22_X1_LVT i_1_0_1007( + .A1(registers_15__ap[16]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[16]), + .ZN(n_1_0_958) + ); + NAND3_X1_LVT i_1_0_1006( + .A1(n_1_0_960), .A2(n_1_0_959), .A3(n_1_0_958), .ZN(n_1_0_957) + ); + SDFF_X1_LVT \registers_reg[27][16] ( + .CK(n_0_57), .D(registers[16]), .Q(registers_27__ap[16]), .QN(), .SE(dftIn), + .SI(registers_30__ap[16]) + ); + SDFF_X1_LVT \registers_reg[3][16] ( + .CK(n_0_33), .D(registers[16]), .Q(registers_3__ap[16]), .QN(), .SE(dftIn), + .SI(registers_8__ap[16]) + ); + AOI221_X1_LVT i_1_0_1005( + .A(n_1_0_957), .B1(n_1_0_1279), .B2(registers_27__ap[16]), .C1(registers_3__ap[16]), + .C2(n_1_0_1257), .ZN(n_1_0_956) + ); + NAND3_X1_LVT i_1_0_1004( + .A1(n_1_0_966), .A2(n_1_0_961), .A3(n_1_0_956), .ZN(RRs1[16]) + ); + AND2_X1_LVT i_0_0_15( + .A1(n_0_0_16), .A2(WRd[15]), .ZN(registers[15]) + ); + SDFF_X1_LVT \registers_reg[17][15] ( + .CK(n_0_47), .D(registers[15]), .Q(registers_17__ap[15]), .QN(), .SE(dftIn), + .SI(registers_17__ap[16]) + ); + SDFF_X1_LVT \registers_reg[21][15] ( + .CK(n_0_51), .D(registers[15]), .Q(registers_21__ap[15]), .QN(), .SE(dftIn), + .SI(registers_17__ap[15]) + ); + AOI22_X1_LVT i_1_0_1000( + .A1(registers_17__ap[15]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[15]), + .ZN(n_1_0_952) + ); + SDFF_X1_LVT \registers_reg[10][15] ( + .CK(n_0_40), .D(registers[15]), .Q(registers_10__ap[15]), .QN(), .SE(dftIn), + .SI(registers_14__ap[16]) + ); + SDFF_X1_LVT \registers_reg[2][15] ( + .CK(n_0_32), .D(registers[15]), .Q(registers_2__ap[15]), .QN(), .SE(dftIn), + .SI(registers_27__ap[16]) + ); + AOI22_X1_LVT i_1_0_1003( + .A1(registers_10__ap[15]), .A2(n_1_0_1287), .B1(n_1_0_1268), .B2(registers_2__ap[15]), + .ZN(n_1_0_955) + ); + SDFF_X1_LVT \registers_reg[20][15] ( + .CK(n_0_50), .D(registers[15]), .Q(registers_20__ap[15]), .QN(), .SE(dftIn), + .SI(registers_21__ap[15]) + ); + SDFF_X1_LVT \registers_reg[12][15] ( + .CK(n_0_42), .D(registers[15]), .Q(registers_12__ap[15]), .QN(), .SE(dftIn), + .SI(registers_10__ap[15]) + ); + AOI22_X1_LVT i_1_0_999( + .A1(registers_20__ap[15]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[15]), + .ZN(n_1_0_951) + ); + SDFF_X1_LVT \registers_reg[15][15] ( + .CK(n_0_45), .D(registers[15]), .Q(registers_15__ap[15]), .QN(), .SE(dftIn), + .SI(registers_12__ap[15]) + ); + SDFF_X1_LVT \registers_reg[8][15] ( + .CK(n_0_38), .D(registers[15]), .Q(registers_8__ap[15]), .QN(), .SE(dftIn), + .SI(registers_3__ap[16]) + ); + AOI22_X1_LVT i_1_0_1002( + .A1(registers_15__ap[15]), .A2(n_1_0_1286), .B1(n_1_0_1282), .B2(registers_8__ap[15]), + .ZN(n_1_0_954) + ); + INV_X1_LVT i_1_0_1001( + .A(n_1_0_954), .ZN(n_1_0_953) + ); + SDFF_X1_LVT \registers_reg[11][15] ( + .CK(n_0_41), .D(registers[15]), .Q(registers_11__ap[15]), .QN(), .SE(dftIn), + .SI(registers_15__ap[15]) + ); + SDFF_X1_LVT \registers_reg[24][15] ( + .CK(n_0_54), .D(registers[15]), .Q(registers_24__ap[15]), .QN(), .SE(dftIn), + .SI(registers_2__ap[15]) + ); + AOI221_X1_LVT i_1_0_998( + .A(n_1_0_953), .B1(n_1_0_1270), .B2(registers_11__ap[15]), .C1(registers_24__ap[15]), + .C2(n_1_0_1289), .ZN(n_1_0_950) + ); + SDFF_X1_LVT \registers_reg[13][15] ( + .CK(n_0_43), .D(registers[15]), .Q(registers_13__ap[15]), .QN(), .SE(dftIn), + .SI(registers_11__ap[15]) + ); + SDFF_X1_LVT \registers_reg[30][15] ( + .CK(n_0_60), .D(registers[15]), .Q(registers_30__ap[15]), .QN(), .SE(dftIn), + .SI(registers_24__ap[15]) + ); + SDFF_X1_LVT \registers_reg[22][15] ( + .CK(n_0_52), .D(registers[15]), .Q(registers_22__ap[15]), .QN(), .SE(dftIn), + .SI(registers_20__ap[15]) + ); + AOI222_X1_LVT i_1_0_997( + .A1(registers_13__ap[15]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[15]), + .C1(registers_22__ap[15]), .C2(n_1_0_1294), .ZN(n_1_0_949) + ); + NAND4_X1_LVT i_1_0_996( + .A1(n_1_0_955), .A2(n_1_0_951), .A3(n_1_0_950), .A4(n_1_0_949), .ZN(n_1_0_948) + ); + SDFF_X1_LVT \registers_reg[1][15] ( + .CK(n_0_0), .D(registers[15]), .Q(registers_1__ap[15]), .QN(), .SE(dftIn), + .SI(registers_22__ap[15]) + ); + SDFF_X1_LVT \registers_reg[28][15] ( + .CK(n_0_58), .D(registers[15]), .Q(registers_28__ap[15]), .QN(), .SE(dftIn), + .SI(registers_30__ap[15]) + ); + AOI221_X1_LVT i_1_0_995( + .A(n_1_0_948), .B1(n_1_0_1274), .B2(registers_1__ap[15]), .C1(registers_28__ap[15]), + .C2(n_1_0_1283), .ZN(n_1_0_947) + ); + SDFF_X1_LVT \registers_reg[18][15] ( + .CK(n_0_48), .D(registers[15]), .Q(registers_18__ap[15]), .QN(), .SE(dftIn), + .SI(registers_1__ap[15]) + ); + SDFF_X1_LVT \registers_reg[26][15] ( + .CK(n_0_56), .D(registers[15]), .Q(registers_26__ap[15]), .QN(), .SE(dftIn), + .SI(registers_28__ap[15]) + ); + AOI22_X1_LVT i_1_0_994( + .A1(registers_18__ap[15]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[15]), + .ZN(n_1_0_946) + ); + SDFF_X1_LVT \registers_reg[4][15] ( + .CK(n_0_34), .D(registers[15]), .Q(registers_4__ap[15]), .QN(), .SE(dftIn), + .SI(registers_8__ap[15]) + ); + SDFF_X1_LVT \registers_reg[5][15] ( + .CK(n_0_35), .D(registers[15]), .Q(registers_5__ap[15]), .QN(), .SE(dftIn), + .SI(registers_4__ap[15]) + ); + AOI22_X1_LVT i_1_0_993( + .A1(registers_4__ap[15]), .A2(n_1_0_1278), .B1(n_1_0_1273), .B2(registers_5__ap[15]), + .ZN(n_1_0_945) + ); + SDFF_X1_LVT \registers_reg[6][15] ( + .CK(n_0_36), .D(registers[15]), .Q(registers_6__ap[15]), .QN(), .SE(dftIn), + .SI(registers_5__ap[15]) + ); + SDFF_X1_LVT \registers_reg[16][15] ( + .CK(n_0_46), .D(registers[15]), .Q(registers_16__ap[15]), .QN(), .SE(dftIn), + .SI(registers_13__ap[15]) + ); + AOI22_X1_LVT i_1_0_992( + .A1(registers_6__ap[15]), .A2(n_1_0_1300), .B1(n_1_0_1267), .B2(registers_16__ap[15]), + .ZN(n_1_0_944) + ); + NAND3_X1_LVT i_1_0_991( + .A1(n_1_0_946), .A2(n_1_0_945), .A3(n_1_0_944), .ZN(n_1_0_943) + ); + SDFF_X1_LVT \registers_reg[19][15] ( + .CK(n_0_49), .D(registers[15]), .Q(registers_19__ap[15]), .QN(), .SE(dftIn), + .SI(registers_18__ap[15]) + ); + SDFF_X1_LVT \registers_reg[25][15] ( + .CK(n_0_55), .D(registers[15]), .Q(registers_25__ap[15]), .QN(), .SE(dftIn), + .SI(registers_26__ap[15]) + ); + AOI221_X1_LVT i_1_0_990( + .A(n_1_0_943), .B1(n_1_0_1295), .B2(registers_19__ap[15]), .C1(registers_25__ap[15]), + .C2(n_1_0_1269), .ZN(n_1_0_942) + ); + SDFF_X1_LVT \registers_reg[7][15] ( + .CK(n_0_37), .D(registers[15]), .Q(registers_7__ap[15]), .QN(), .SE(dftIn), + .SI(registers_6__ap[15]) + ); + SDFF_X1_LVT \registers_reg[14][15] ( + .CK(n_0_44), .D(registers[15]), .Q(registers_14__ap[15]), .QN(), .SE(dftIn), + .SI(registers_16__ap[15]) + ); + AOI22_X1_LVT i_1_0_989( + .A1(registers_7__ap[15]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[15]), + .ZN(n_1_0_941) + ); + SDFF_X1_LVT \registers_reg[9][15] ( + .CK(n_0_39), .D(registers[15]), .Q(registers_9__ap[15]), .QN(), .SE(dftIn), + .SI(registers_7__ap[15]) + ); + SDFF_X1_LVT \registers_reg[29][15] ( + .CK(n_0_59), .D(registers[15]), .Q(registers_29__ap[15]), .QN(), .SE(dftIn), + .SI(registers_25__ap[15]) + ); + AOI22_X1_LVT i_1_0_988( + .A1(registers_9__ap[15]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[15]), + .ZN(n_1_0_940) + ); + SDFF_X1_LVT \registers_reg[23][15] ( + .CK(n_0_53), .D(registers[15]), .Q(registers_23__ap[15]), .QN(), .SE(dftIn), + .SI(registers_19__ap[15]) + ); + SDFF_X1_LVT \registers_reg[3][15] ( + .CK(n_0_33), .D(registers[15]), .Q(registers_3__ap[15]), .QN(), .SE(dftIn), + .SI(registers_9__ap[15]) + ); + AOI22_X1_LVT i_1_0_987( + .A1(registers_23__ap[15]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[15]), + .ZN(n_1_0_939) + ); + NAND3_X1_LVT i_1_0_986( + .A1(n_1_0_941), .A2(n_1_0_940), .A3(n_1_0_939), .ZN(n_1_0_938) + ); + SDFF_X1_LVT \registers_reg[27][15] ( + .CK(n_0_57), .D(registers[15]), .Q(registers_27__ap[15]), .QN(), .SE(dftIn), + .SI(registers_29__ap[15]) + ); + SDFF_X1_LVT \registers_reg[31][15] ( + .CK(n_0_61), .D(registers[15]), .Q(registers_31__ap[15]), .QN(), .SE(dftIn), + .SI(registers_3__ap[15]) + ); + AOI221_X1_LVT i_1_0_985( + .A(n_1_0_938), .B1(n_1_0_1279), .B2(registers_27__ap[15]), .C1(registers_31__ap[15]), + .C2(n_1_0_1266), .ZN(n_1_0_937) + ); + NAND4_X1_LVT i_1_0_984( + .A1(n_1_0_952), .A2(n_1_0_947), .A3(n_1_0_942), .A4(n_1_0_937), .ZN(RRs1[15]) + ); + AND2_X1_LVT i_0_0_14( + .A1(n_0_0_16), .A2(WRd[14]), .ZN(registers[14]) + ); + SDFF_X1_LVT \registers_reg[28][14] ( + .CK(n_0_58), .D(registers[14]), .Q(registers_28__ap[14]), .QN(), .SE(dftIn), + .SI(registers_27__ap[15]) + ); + SDFF_X1_LVT \registers_reg[5][14] ( + .CK(n_0_35), .D(registers[14]), .Q(registers_5__ap[14]), .QN(), .SE(dftIn), + .SI(registers_31__ap[15]) + ); + AOI22_X1_LVT i_1_0_983( + .A1(registers_28__ap[14]), .A2(n_1_0_1283), .B1(n_1_0_1273), .B2(registers_5__ap[14]), + .ZN(n_1_0_936) + ); + SDFF_X1_LVT \registers_reg[18][14] ( + .CK(n_0_48), .D(registers[14]), .Q(registers_18__ap[14]), .QN(), .SE(dftIn), + .SI(registers_23__ap[15]) + ); + SDFF_X1_LVT \registers_reg[10][14] ( + .CK(n_0_40), .D(registers[14]), .Q(registers_10__ap[14]), .QN(), .SE(dftIn), + .SI(registers_14__ap[15]) + ); + SDFF_X1_LVT \registers_reg[8][14] ( + .CK(n_0_38), .D(registers[14]), .Q(registers_8__ap[14]), .QN(), .SE(dftIn), + .SI(registers_5__ap[14]) + ); + AOI222_X1_LVT i_1_0_982( + .A1(registers_18__ap[14]), .A2(n_1_0_1297), .B1(n_1_0_1287), .B2(registers_10__ap[14]), + .C1(n_1_0_1282), .C2(registers_8__ap[14]), .ZN(n_1_0_935) + ); + SDFF_X1_LVT \registers_reg[9][14] ( + .CK(n_0_39), .D(registers[14]), .Q(registers_9__ap[14]), .QN(), .SE(dftIn), + .SI(registers_8__ap[14]) + ); + SDFF_X1_LVT \registers_reg[29][14] ( + .CK(n_0_59), .D(registers[14]), .Q(registers_29__ap[14]), .QN(), .SE(dftIn), + .SI(registers_28__ap[14]) + ); + AOI22_X1_LVT i_1_0_981( + .A1(registers_9__ap[14]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[14]), + .ZN(n_1_0_934) + ); + SDFF_X1_LVT \registers_reg[21][14] ( + .CK(n_0_51), .D(registers[14]), .Q(registers_21__ap[14]), .QN(), .SE(dftIn), + .SI(registers_18__ap[14]) + ); + SDFF_X1_LVT \registers_reg[14][14] ( + .CK(n_0_44), .D(registers[14]), .Q(registers_14__ap[14]), .QN(), .SE(dftIn), + .SI(registers_10__ap[14]) + ); + AOI22_X1_LVT i_1_0_980( + .A1(registers_21__ap[14]), .A2(n_1_0_1259), .B1(n_1_0_1258), .B2(registers_14__ap[14]), + .ZN(n_1_0_933) + ); + SDFF_X1_LVT \registers_reg[16][14] ( + .CK(n_0_46), .D(registers[14]), .Q(registers_16__ap[14]), .QN(), .SE(dftIn), + .SI(registers_14__ap[14]) + ); + SDFF_X1_LVT \registers_reg[3][14] ( + .CK(n_0_33), .D(registers[14]), .Q(registers_3__ap[14]), .QN(), .SE(dftIn), + .SI(registers_9__ap[14]) + ); + AOI22_X1_LVT i_1_0_979( + .A1(registers_16__ap[14]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[14]), + .ZN(n_1_0_932) + ); + SDFF_X1_LVT \registers_reg[17][14] ( + .CK(n_0_47), .D(registers[14]), .Q(registers_17__ap[14]), .QN(), .SE(dftIn), + .SI(registers_21__ap[14]) + ); + SDFF_X1_LVT \registers_reg[31][14] ( + .CK(n_0_61), .D(registers[14]), .Q(registers_31__ap[14]), .QN(), .SE(dftIn), + .SI(registers_3__ap[14]) + ); + AOI22_X1_LVT i_1_0_978( + .A1(registers_17__ap[14]), .A2(n_1_0_1271), .B1(n_1_0_1266), .B2(registers_31__ap[14]), + .ZN(n_1_0_931) + ); + SDFF_X1_LVT \registers_reg[15][14] ( + .CK(n_0_45), .D(registers[14]), .Q(registers_15__ap[14]), .QN(), .SE(dftIn), + .SI(registers_16__ap[14]) + ); + SDFF_X1_LVT \registers_reg[23][14] ( + .CK(n_0_53), .D(registers[14]), .Q(registers_23__ap[14]), .QN(), .SE(dftIn), + .SI(registers_17__ap[14]) + ); + AOI22_X1_LVT i_1_0_977( + .A1(registers_15__ap[14]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[14]), + .ZN(n_1_0_930) + ); + NAND4_X1_LVT i_1_0_976( + .A1(n_1_0_933), .A2(n_1_0_932), .A3(n_1_0_931), .A4(n_1_0_930), .ZN(n_1_0_929) + ); + SDFF_X1_LVT \registers_reg[26][14] ( + .CK(n_0_56), .D(registers[14]), .Q(registers_26__ap[14]), .QN(), .SE(dftIn), + .SI(registers_29__ap[14]) + ); + SDFF_X1_LVT \registers_reg[30][14] ( + .CK(n_0_60), .D(registers[14]), .Q(registers_30__ap[14]), .QN(), .SE(dftIn), + .SI(registers_26__ap[14]) + ); + AOI22_X1_LVT i_1_0_975( + .A1(registers_26__ap[14]), .A2(n_1_0_1285), .B1(n_1_0_1272), .B2(registers_30__ap[14]), + .ZN(n_1_0_928) + ); + SDFF_X1_LVT \registers_reg[20][14] ( + .CK(n_0_50), .D(registers[14]), .Q(registers_20__ap[14]), .QN(), .SE(dftIn), + .SI(registers_23__ap[14]) + ); + SDFF_X1_LVT \registers_reg[4][14] ( + .CK(n_0_34), .D(registers[14]), .Q(registers_4__ap[14]), .QN(), .SE(dftIn), + .SI(registers_31__ap[14]) + ); + AOI22_X1_LVT i_1_0_974( + .A1(registers_20__ap[14]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[14]), + .ZN(n_1_0_927) + ); + SDFF_X1_LVT \registers_reg[1][14] ( + .CK(n_0_0), .D(registers[14]), .Q(registers_1__ap[14]), .QN(), .SE(dftIn), + .SI(registers_20__ap[14]) + ); + SDFF_X1_LVT \registers_reg[2][14] ( + .CK(n_0_32), .D(registers[14]), .Q(registers_2__ap[14]), .QN(), .SE(dftIn), + .SI(registers_30__ap[14]) + ); + AOI22_X1_LVT i_1_0_973( + .A1(registers_1__ap[14]), .A2(n_1_0_1274), .B1(n_1_0_1268), .B2(registers_2__ap[14]), + .ZN(n_1_0_926) + ); + SDFF_X1_LVT \registers_reg[24][14] ( + .CK(n_0_54), .D(registers[14]), .Q(registers_24__ap[14]), .QN(), .SE(dftIn), + .SI(registers_2__ap[14]) + ); + SDFF_X1_LVT \registers_reg[12][14] ( + .CK(n_0_42), .D(registers[14]), .Q(registers_12__ap[14]), .QN(), .SE(dftIn), + .SI(registers_15__ap[14]) + ); + AOI22_X1_LVT i_1_0_972( + .A1(registers_24__ap[14]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[14]), + .ZN(n_1_0_925) + ); + NAND4_X1_LVT i_1_0_971( + .A1(n_1_0_928), .A2(n_1_0_927), .A3(n_1_0_926), .A4(n_1_0_925), .ZN(n_1_0_924) + ); + SDFF_X1_LVT \registers_reg[19][14] ( + .CK(n_0_49), .D(registers[14]), .Q(registers_19__ap[14]), .QN(), .SE(dftIn), + .SI(registers_1__ap[14]) + ); + SDFF_X1_LVT \registers_reg[22][14] ( + .CK(n_0_52), .D(registers[14]), .Q(registers_22__ap[14]), .QN(), .SE(dftIn), + .SI(registers_19__ap[14]) + ); + AOI22_X1_LVT i_1_0_970( + .A1(registers_19__ap[14]), .A2(n_1_0_1295), .B1(n_1_0_1294), .B2(registers_22__ap[14]), + .ZN(n_1_0_923) + ); + SDFF_X1_LVT \registers_reg[13][14] ( + .CK(n_0_43), .D(registers[14]), .Q(registers_13__ap[14]), .QN(), .SE(dftIn), + .SI(registers_12__ap[14]) + ); + SDFF_X1_LVT \registers_reg[25][14] ( + .CK(n_0_55), .D(registers[14]), .Q(registers_25__ap[14]), .QN(), .SE(dftIn), + .SI(registers_24__ap[14]) + ); + AOI22_X1_LVT i_1_0_969( + .A1(registers_13__ap[14]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[14]), + .ZN(n_1_0_922) + ); + SDFF_X1_LVT \registers_reg[6][14] ( + .CK(n_0_36), .D(registers[14]), .Q(registers_6__ap[14]), .QN(), .SE(dftIn), + .SI(registers_4__ap[14]) + ); + SDFF_X1_LVT \registers_reg[7][14] ( + .CK(n_0_37), .D(registers[14]), .Q(registers_7__ap[14]), .QN(), .SE(dftIn), + .SI(registers_6__ap[14]) + ); + AOI22_X1_LVT i_1_0_968( + .A1(registers_6__ap[14]), .A2(n_1_0_1300), .B1(n_1_0_1263), .B2(registers_7__ap[14]), + .ZN(n_1_0_921) + ); + SDFF_X1_LVT \registers_reg[27][14] ( + .CK(n_0_57), .D(registers[14]), .Q(registers_27__ap[14]), .QN(), .SE(dftIn), + .SI(registers_25__ap[14]) + ); + SDFF_X1_LVT \registers_reg[11][14] ( + .CK(n_0_41), .D(registers[14]), .Q(registers_11__ap[14]), .QN(), .SE(dftIn), + .SI(registers_13__ap[14]) + ); + AOI22_X1_LVT i_1_0_967( + .A1(registers_27__ap[14]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[14]), + .ZN(n_1_0_920) + ); + NAND4_X1_LVT i_1_0_966( + .A1(n_1_0_923), .A2(n_1_0_922), .A3(n_1_0_921), .A4(n_1_0_920), .ZN(n_1_0_919) + ); + NOR3_X1_LVT i_1_0_965( + .A1(n_1_0_929), .A2(n_1_0_924), .A3(n_1_0_919), .ZN(n_1_0_918) + ); + NAND4_X1_LVT i_1_0_964( + .A1(n_1_0_936), .A2(n_1_0_935), .A3(n_1_0_934), .A4(n_1_0_918), .ZN(RRs1[14]) + ); + AND2_X1_LVT i_0_0_13( + .A1(n_0_0_16), .A2(WRd[13]), .ZN(registers[13]) + ); + SDFF_X1_LVT \registers_reg[28][13] ( + .CK(n_0_58), .D(registers[13]), .Q(registers_28__ap[13]), .QN(), .SE(dftIn), + .SI(registers_27__ap[14]) + ); + SDFF_X1_LVT \registers_reg[4][13] ( + .CK(n_0_34), .D(registers[13]), .Q(registers_4__ap[13]), .QN(), .SE(dftIn), + .SI(registers_7__ap[14]) + ); + AOI22_X1_LVT i_1_0_963( + .A1(registers_28__ap[13]), .A2(n_1_0_1283), .B1(n_1_0_1278), .B2(registers_4__ap[13]), + .ZN(n_1_0_917) + ); + SDFF_X1_LVT \registers_reg[10][13] ( + .CK(n_0_40), .D(registers[13]), .Q(registers_10__ap[13]), .QN(), .SE(dftIn), + .SI(registers_11__ap[14]) + ); + SDFF_X1_LVT \registers_reg[26][13] ( + .CK(n_0_56), .D(registers[13]), .Q(registers_26__ap[13]), .QN(), .SE(dftIn), + .SI(registers_28__ap[13]) + ); + SDFF_X1_LVT \registers_reg[8][13] ( + .CK(n_0_38), .D(registers[13]), .Q(registers_8__ap[13]), .QN(), .SE(dftIn), + .SI(registers_4__ap[13]) + ); + AOI222_X1_LVT i_1_0_962( + .A1(registers_10__ap[13]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[13]), + .C1(registers_8__ap[13]), .C2(n_1_0_1282), .ZN(n_1_0_916) + ); + SDFF_X1_LVT \registers_reg[9][13] ( + .CK(n_0_39), .D(registers[13]), .Q(registers_9__ap[13]), .QN(), .SE(dftIn), + .SI(registers_8__ap[13]) + ); + SDFF_X1_LVT \registers_reg[29][13] ( + .CK(n_0_59), .D(registers[13]), .Q(registers_29__ap[13]), .QN(), .SE(dftIn), + .SI(registers_26__ap[13]) + ); + AOI22_X1_LVT i_1_0_961( + .A1(registers_9__ap[13]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[13]), + .ZN(n_1_0_915) + ); + SDFF_X1_LVT \registers_reg[6][13] ( + .CK(n_0_36), .D(registers[13]), .Q(registers_6__ap[13]), .QN(), .SE(dftIn), + .SI(registers_9__ap[13]) + ); + SDFF_X1_LVT \registers_reg[1][13] ( + .CK(n_0_0), .D(registers[13]), .Q(registers_1__ap[13]), .QN(), .SE(dftIn), + .SI(registers_22__ap[14]) + ); + AOI22_X1_LVT i_1_0_960( + .A1(registers_6__ap[13]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[13]), + .ZN(n_1_0_914) + ); + SDFF_X1_LVT \registers_reg[5][13] ( + .CK(n_0_35), .D(registers[13]), .Q(registers_5__ap[13]), .QN(), .SE(dftIn), + .SI(registers_6__ap[13]) + ); + SDFF_X1_LVT \registers_reg[3][13] ( + .CK(n_0_33), .D(registers[13]), .Q(registers_3__ap[13]), .QN(), .SE(dftIn), + .SI(registers_5__ap[13]) + ); + AOI22_X1_LVT i_1_0_959( + .A1(registers_5__ap[13]), .A2(n_1_0_1273), .B1(n_1_0_1257), .B2(registers_3__ap[13]), + .ZN(n_1_0_913) + ); + SDFF_X1_LVT \registers_reg[16][13] ( + .CK(n_0_46), .D(registers[13]), .Q(registers_16__ap[13]), .QN(), .SE(dftIn), + .SI(registers_10__ap[13]) + ); + SDFF_X1_LVT \registers_reg[31][13] ( + .CK(n_0_61), .D(registers[13]), .Q(registers_31__ap[13]), .QN(), .SE(dftIn), + .SI(registers_3__ap[13]) + ); + AOI22_X1_LVT i_1_0_958( + .A1(registers_16__ap[13]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[13]), + .ZN(n_1_0_912) + ); + SDFF_X1_LVT \registers_reg[15][13] ( + .CK(n_0_45), .D(registers[13]), .Q(registers_15__ap[13]), .QN(), .SE(dftIn), + .SI(registers_16__ap[13]) + ); + SDFF_X1_LVT \registers_reg[23][13] ( + .CK(n_0_53), .D(registers[13]), .Q(registers_23__ap[13]), .QN(), .SE(dftIn), + .SI(registers_1__ap[13]) + ); + AOI22_X1_LVT i_1_0_957( + .A1(registers_15__ap[13]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[13]), + .ZN(n_1_0_911) + ); + NAND4_X1_LVT i_1_0_956( + .A1(n_1_0_914), .A2(n_1_0_913), .A3(n_1_0_912), .A4(n_1_0_911), .ZN(n_1_0_910) + ); + SDFF_X1_LVT \registers_reg[18][13] ( + .CK(n_0_48), .D(registers[13]), .Q(registers_18__ap[13]), .QN(), .SE(dftIn), + .SI(registers_23__ap[13]) + ); + SDFF_X1_LVT \registers_reg[30][13] ( + .CK(n_0_60), .D(registers[13]), .Q(registers_30__ap[13]), .QN(), .SE(dftIn), + .SI(registers_29__ap[13]) + ); + AOI22_X1_LVT i_1_0_955( + .A1(registers_18__ap[13]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[13]), + .ZN(n_1_0_909) + ); + SDFF_X1_LVT \registers_reg[24][13] ( + .CK(n_0_54), .D(registers[13]), .Q(registers_24__ap[13]), .QN(), .SE(dftIn), + .SI(registers_30__ap[13]) + ); + SDFF_X1_LVT \registers_reg[12][13] ( + .CK(n_0_42), .D(registers[13]), .Q(registers_12__ap[13]), .QN(), .SE(dftIn), + .SI(registers_15__ap[13]) + ); + AOI22_X1_LVT i_1_0_954( + .A1(registers_24__ap[13]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[13]), + .ZN(n_1_0_908) + ); + SDFF_X1_LVT \registers_reg[22][13] ( + .CK(n_0_52), .D(registers[13]), .Q(registers_22__ap[13]), .QN(), .SE(dftIn), + .SI(registers_18__ap[13]) + ); + SDFF_X1_LVT \registers_reg[21][13] ( + .CK(n_0_51), .D(registers[13]), .Q(registers_21__ap[13]), .QN(), .SE(dftIn), + .SI(registers_22__ap[13]) + ); + AOI22_X1_LVT i_1_0_953( + .A1(registers_22__ap[13]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[13]), + .ZN(n_1_0_907) + ); + SDFF_X1_LVT \registers_reg[20][13] ( + .CK(n_0_50), .D(registers[13]), .Q(registers_20__ap[13]), .QN(), .SE(dftIn), + .SI(registers_21__ap[13]) + ); + SDFF_X1_LVT \registers_reg[17][13] ( + .CK(n_0_47), .D(registers[13]), .Q(registers_17__ap[13]), .QN(), .SE(dftIn), + .SI(registers_20__ap[13]) + ); + AOI22_X1_LVT i_1_0_952( + .A1(registers_20__ap[13]), .A2(n_1_0_1281), .B1(n_1_0_1271), .B2(registers_17__ap[13]), + .ZN(n_1_0_906) + ); + NAND4_X1_LVT i_1_0_951( + .A1(n_1_0_909), .A2(n_1_0_908), .A3(n_1_0_907), .A4(n_1_0_906), .ZN(n_1_0_905) + ); + SDFF_X1_LVT \registers_reg[13][13] ( + .CK(n_0_43), .D(registers[13]), .Q(registers_13__ap[13]), .QN(), .SE(dftIn), + .SI(registers_12__ap[13]) + ); + SDFF_X1_LVT \registers_reg[25][13] ( + .CK(n_0_55), .D(registers[13]), .Q(registers_25__ap[13]), .QN(), .SE(dftIn), + .SI(registers_24__ap[13]) + ); + AOI22_X1_LVT i_1_0_950( + .A1(registers_13__ap[13]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[13]), + .ZN(n_1_0_904) + ); + SDFF_X1_LVT \registers_reg[19][13] ( + .CK(n_0_49), .D(registers[13]), .Q(registers_19__ap[13]), .QN(), .SE(dftIn), + .SI(registers_17__ap[13]) + ); + SDFF_X1_LVT \registers_reg[2][13] ( + .CK(n_0_32), .D(registers[13]), .Q(registers_2__ap[13]), .QN(), .SE(dftIn), + .SI(registers_25__ap[13]) + ); + AOI22_X1_LVT i_1_0_949( + .A1(registers_19__ap[13]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[13]), + .ZN(n_1_0_903) + ); + SDFF_X1_LVT \registers_reg[7][13] ( + .CK(n_0_37), .D(registers[13]), .Q(registers_7__ap[13]), .QN(), .SE(dftIn), + .SI(registers_31__ap[13]) + ); + SDFF_X1_LVT \registers_reg[14][13] ( + .CK(n_0_44), .D(registers[13]), .Q(registers_14__ap[13]), .QN(), .SE(dftIn), + .SI(registers_13__ap[13]) + ); + AOI22_X1_LVT i_1_0_948( + .A1(registers_7__ap[13]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[13]), + .ZN(n_1_0_902) + ); + SDFF_X1_LVT \registers_reg[27][13] ( + .CK(n_0_57), .D(registers[13]), .Q(registers_27__ap[13]), .QN(), .SE(dftIn), + .SI(registers_2__ap[13]) + ); + SDFF_X1_LVT \registers_reg[11][13] ( + .CK(n_0_41), .D(registers[13]), .Q(registers_11__ap[13]), .QN(), .SE(dftIn), + .SI(registers_14__ap[13]) + ); + AOI22_X1_LVT i_1_0_947( + .A1(registers_27__ap[13]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[13]), + .ZN(n_1_0_901) + ); + NAND4_X1_LVT i_1_0_946( + .A1(n_1_0_904), .A2(n_1_0_903), .A3(n_1_0_902), .A4(n_1_0_901), .ZN(n_1_0_900) + ); + NOR3_X1_LVT i_1_0_945( + .A1(n_1_0_910), .A2(n_1_0_905), .A3(n_1_0_900), .ZN(n_1_0_899) + ); + NAND4_X1_LVT i_1_0_944( + .A1(n_1_0_917), .A2(n_1_0_916), .A3(n_1_0_915), .A4(n_1_0_899), .ZN(RRs1[13]) + ); + AND2_X1_LVT i_0_0_12( + .A1(n_0_0_16), .A2(WRd[12]), .ZN(registers[12]) + ); + SDFF_X1_LVT \registers_reg[28][12] ( + .CK(n_0_58), .D(registers[12]), .Q(registers_28__ap[12]), .QN(), .SE(dftIn), + .SI(registers_27__ap[13]) + ); + SDFF_X1_LVT \registers_reg[17][12] ( + .CK(n_0_47), .D(registers[12]), .Q(registers_17__ap[12]), .QN(), .SE(dftIn), + .SI(registers_19__ap[13]) + ); + AOI22_X1_LVT i_1_0_943( + .A1(registers_28__ap[12]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[12]), + .ZN(n_1_0_898) + ); + SDFF_X1_LVT \registers_reg[10][12] ( + .CK(n_0_40), .D(registers[12]), .Q(registers_10__ap[12]), .QN(), .SE(dftIn), + .SI(registers_11__ap[13]) + ); + SDFF_X1_LVT \registers_reg[26][12] ( + .CK(n_0_56), .D(registers[12]), .Q(registers_26__ap[12]), .QN(), .SE(dftIn), + .SI(registers_28__ap[12]) + ); + SDFF_X1_LVT \registers_reg[8][12] ( + .CK(n_0_38), .D(registers[12]), .Q(registers_8__ap[12]), .QN(), .SE(dftIn), + .SI(registers_7__ap[13]) + ); + AOI222_X1_LVT i_1_0_942( + .A1(registers_10__ap[12]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[12]), + .C1(registers_8__ap[12]), .C2(n_1_0_1282), .ZN(n_1_0_897) + ); + SDFF_X1_LVT \registers_reg[9][12] ( + .CK(n_0_39), .D(registers[12]), .Q(registers_9__ap[12]), .QN(), .SE(dftIn), + .SI(registers_8__ap[12]) + ); + SDFF_X1_LVT \registers_reg[29][12] ( + .CK(n_0_59), .D(registers[12]), .Q(registers_29__ap[12]), .QN(), .SE(dftIn), + .SI(registers_26__ap[12]) + ); + AOI22_X1_LVT i_1_0_941( + .A1(registers_9__ap[12]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[12]), + .ZN(n_1_0_896) + ); + SDFF_X1_LVT \registers_reg[6][12] ( + .CK(n_0_36), .D(registers[12]), .Q(registers_6__ap[12]), .QN(), .SE(dftIn), + .SI(registers_9__ap[12]) + ); + SDFF_X1_LVT \registers_reg[1][12] ( + .CK(n_0_0), .D(registers[12]), .Q(registers_1__ap[12]), .QN(), .SE(dftIn), + .SI(registers_17__ap[12]) + ); + AOI22_X1_LVT i_1_0_940( + .A1(registers_6__ap[12]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[12]), + .ZN(n_1_0_895) + ); + SDFF_X1_LVT \registers_reg[16][12] ( + .CK(n_0_46), .D(registers[12]), .Q(registers_16__ap[12]), .QN(), .SE(dftIn), + .SI(registers_10__ap[12]) + ); + SDFF_X1_LVT \registers_reg[3][12] ( + .CK(n_0_33), .D(registers[12]), .Q(registers_3__ap[12]), .QN(), .SE(dftIn), + .SI(registers_6__ap[12]) + ); + AOI22_X1_LVT i_1_0_939( + .A1(registers_16__ap[12]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[12]), + .ZN(n_1_0_894) + ); + SDFF_X1_LVT \registers_reg[5][12] ( + .CK(n_0_35), .D(registers[12]), .Q(registers_5__ap[12]), .QN(), .SE(dftIn), + .SI(registers_3__ap[12]) + ); + SDFF_X1_LVT \registers_reg[31][12] ( + .CK(n_0_61), .D(registers[12]), .Q(registers_31__ap[12]), .QN(), .SE(dftIn), + .SI(registers_5__ap[12]) + ); + AOI22_X1_LVT i_1_0_938( + .A1(registers_5__ap[12]), .A2(n_1_0_1273), .B1(n_1_0_1266), .B2(registers_31__ap[12]), + .ZN(n_1_0_893) + ); + SDFF_X1_LVT \registers_reg[15][12] ( + .CK(n_0_45), .D(registers[12]), .Q(registers_15__ap[12]), .QN(), .SE(dftIn), + .SI(registers_16__ap[12]) + ); + SDFF_X1_LVT \registers_reg[23][12] ( + .CK(n_0_53), .D(registers[12]), .Q(registers_23__ap[12]), .QN(), .SE(dftIn), + .SI(registers_1__ap[12]) + ); + AOI22_X1_LVT i_1_0_937( + .A1(registers_15__ap[12]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[12]), + .ZN(n_1_0_892) + ); + NAND4_X1_LVT i_1_0_936( + .A1(n_1_0_895), .A2(n_1_0_894), .A3(n_1_0_893), .A4(n_1_0_892), .ZN(n_1_0_891) + ); + SDFF_X1_LVT \registers_reg[18][12] ( + .CK(n_0_48), .D(registers[12]), .Q(registers_18__ap[12]), .QN(), .SE(dftIn), + .SI(registers_23__ap[12]) + ); + SDFF_X1_LVT \registers_reg[30][12] ( + .CK(n_0_60), .D(registers[12]), .Q(registers_30__ap[12]), .QN(), .SE(dftIn), + .SI(registers_29__ap[12]) + ); + AOI22_X1_LVT i_1_0_935( + .A1(registers_18__ap[12]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[12]), + .ZN(n_1_0_890) + ); + SDFF_X1_LVT \registers_reg[20][12] ( + .CK(n_0_50), .D(registers[12]), .Q(registers_20__ap[12]), .QN(), .SE(dftIn), + .SI(registers_18__ap[12]) + ); + SDFF_X1_LVT \registers_reg[4][12] ( + .CK(n_0_34), .D(registers[12]), .Q(registers_4__ap[12]), .QN(), .SE(dftIn), + .SI(registers_31__ap[12]) + ); + AOI22_X1_LVT i_1_0_934( + .A1(registers_20__ap[12]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[12]), + .ZN(n_1_0_889) + ); + SDFF_X1_LVT \registers_reg[22][12] ( + .CK(n_0_52), .D(registers[12]), .Q(registers_22__ap[12]), .QN(), .SE(dftIn), + .SI(registers_20__ap[12]) + ); + SDFF_X1_LVT \registers_reg[21][12] ( + .CK(n_0_51), .D(registers[12]), .Q(registers_21__ap[12]), .QN(), .SE(dftIn), + .SI(registers_22__ap[12]) + ); + AOI22_X1_LVT i_1_0_933( + .A1(registers_22__ap[12]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[12]), + .ZN(n_1_0_888) + ); + SDFF_X1_LVT \registers_reg[24][12] ( + .CK(n_0_54), .D(registers[12]), .Q(registers_24__ap[12]), .QN(), .SE(dftIn), + .SI(registers_30__ap[12]) + ); + SDFF_X1_LVT \registers_reg[12][12] ( + .CK(n_0_42), .D(registers[12]), .Q(registers_12__ap[12]), .QN(), .SE(dftIn), + .SI(registers_15__ap[12]) + ); + AOI22_X1_LVT i_1_0_932( + .A1(registers_24__ap[12]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[12]), + .ZN(n_1_0_887) + ); + NAND4_X1_LVT i_1_0_931( + .A1(n_1_0_890), .A2(n_1_0_889), .A3(n_1_0_888), .A4(n_1_0_887), .ZN(n_1_0_886) + ); + SDFF_X1_LVT \registers_reg[13][12] ( + .CK(n_0_43), .D(registers[12]), .Q(registers_13__ap[12]), .QN(), .SE(dftIn), + .SI(registers_12__ap[12]) + ); + SDFF_X1_LVT \registers_reg[25][12] ( + .CK(n_0_55), .D(registers[12]), .Q(registers_25__ap[12]), .QN(), .SE(dftIn), + .SI(registers_24__ap[12]) + ); + AOI22_X1_LVT i_1_0_930( + .A1(registers_13__ap[12]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[12]), + .ZN(n_1_0_885) + ); + SDFF_X1_LVT \registers_reg[19][12] ( + .CK(n_0_49), .D(registers[12]), .Q(registers_19__ap[12]), .QN(), .SE(dftIn), + .SI(registers_21__ap[12]) + ); + SDFF_X1_LVT \registers_reg[2][12] ( + .CK(n_0_32), .D(registers[12]), .Q(registers_2__ap[12]), .QN(), .SE(dftIn), + .SI(registers_25__ap[12]) + ); + AOI22_X1_LVT i_1_0_929( + .A1(registers_19__ap[12]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[12]), + .ZN(n_1_0_884) + ); + SDFF_X1_LVT \registers_reg[7][12] ( + .CK(n_0_37), .D(registers[12]), .Q(registers_7__ap[12]), .QN(), .SE(dftIn), + .SI(registers_4__ap[12]) + ); + SDFF_X1_LVT \registers_reg[14][12] ( + .CK(n_0_44), .D(registers[12]), .Q(registers_14__ap[12]), .QN(), .SE(dftIn), + .SI(registers_13__ap[12]) + ); + AOI22_X1_LVT i_1_0_928( + .A1(registers_7__ap[12]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[12]), + .ZN(n_1_0_883) + ); + SDFF_X1_LVT \registers_reg[27][12] ( + .CK(n_0_57), .D(registers[12]), .Q(registers_27__ap[12]), .QN(), .SE(dftIn), + .SI(registers_2__ap[12]) + ); + SDFF_X1_LVT \registers_reg[11][12] ( + .CK(n_0_41), .D(registers[12]), .Q(registers_11__ap[12]), .QN(), .SE(dftIn), + .SI(registers_14__ap[12]) + ); + AOI22_X1_LVT i_1_0_927( + .A1(registers_27__ap[12]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[12]), + .ZN(n_1_0_882) + ); + NAND4_X1_LVT i_1_0_926( + .A1(n_1_0_885), .A2(n_1_0_884), .A3(n_1_0_883), .A4(n_1_0_882), .ZN(n_1_0_881) + ); + NOR3_X1_LVT i_1_0_925( + .A1(n_1_0_891), .A2(n_1_0_886), .A3(n_1_0_881), .ZN(n_1_0_880) + ); + NAND4_X1_LVT i_1_0_924( + .A1(n_1_0_898), .A2(n_1_0_897), .A3(n_1_0_896), .A4(n_1_0_880), .ZN(RRs1[12]) + ); + AND2_X1_LVT i_0_0_11( + .A1(n_0_0_16), .A2(WRd[11]), .ZN(registers[11]) + ); + SDFF_X1_LVT \registers_reg[28][11] ( + .CK(n_0_58), .D(registers[11]), .Q(registers_28__ap[11]), .QN(), .SE(dftIn), + .SI(registers_27__ap[12]) + ); + SDFF_X1_LVT \registers_reg[17][11] ( + .CK(n_0_47), .D(registers[11]), .Q(registers_17__ap[11]), .QN(), .SE(dftIn), + .SI(registers_19__ap[12]) + ); + AOI22_X1_LVT i_1_0_923( + .A1(registers_28__ap[11]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[11]), + .ZN(n_1_0_879) + ); + SDFF_X1_LVT \registers_reg[10][11] ( + .CK(n_0_40), .D(registers[11]), .Q(registers_10__ap[11]), .QN(), .SE(dftIn), + .SI(registers_11__ap[12]) + ); + SDFF_X1_LVT \registers_reg[26][11] ( + .CK(n_0_56), .D(registers[11]), .Q(registers_26__ap[11]), .QN(), .SE(dftIn), + .SI(registers_28__ap[11]) + ); + SDFF_X1_LVT \registers_reg[8][11] ( + .CK(n_0_38), .D(registers[11]), .Q(registers_8__ap[11]), .QN(), .SE(dftIn), + .SI(registers_7__ap[12]) + ); + AOI222_X1_LVT i_1_0_922( + .A1(registers_10__ap[11]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[11]), + .C1(registers_8__ap[11]), .C2(n_1_0_1282), .ZN(n_1_0_878) + ); + SDFF_X1_LVT \registers_reg[9][11] ( + .CK(n_0_39), .D(registers[11]), .Q(registers_9__ap[11]), .QN(), .SE(dftIn), + .SI(registers_8__ap[11]) + ); + SDFF_X1_LVT \registers_reg[29][11] ( + .CK(n_0_59), .D(registers[11]), .Q(registers_29__ap[11]), .QN(), .SE(dftIn), + .SI(registers_26__ap[11]) + ); + AOI22_X1_LVT i_1_0_921( + .A1(registers_9__ap[11]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[11]), + .ZN(n_1_0_877) + ); + SDFF_X1_LVT \registers_reg[6][11] ( + .CK(n_0_36), .D(registers[11]), .Q(registers_6__ap[11]), .QN(), .SE(dftIn), + .SI(registers_9__ap[11]) + ); + SDFF_X1_LVT \registers_reg[1][11] ( + .CK(n_0_0), .D(registers[11]), .Q(registers_1__ap[11]), .QN(), .SE(dftIn), + .SI(registers_17__ap[11]) + ); + AOI22_X1_LVT i_1_0_920( + .A1(registers_6__ap[11]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[11]), + .ZN(n_1_0_876) + ); + SDFF_X1_LVT \registers_reg[5][11] ( + .CK(n_0_35), .D(registers[11]), .Q(registers_5__ap[11]), .QN(), .SE(dftIn), + .SI(registers_6__ap[11]) + ); + SDFF_X1_LVT \registers_reg[3][11] ( + .CK(n_0_33), .D(registers[11]), .Q(registers_3__ap[11]), .QN(), .SE(dftIn), + .SI(registers_5__ap[11]) + ); + AOI22_X1_LVT i_1_0_919( + .A1(registers_5__ap[11]), .A2(n_1_0_1273), .B1(n_1_0_1257), .B2(registers_3__ap[11]), + .ZN(n_1_0_875) + ); + SDFF_X1_LVT \registers_reg[16][11] ( + .CK(n_0_46), .D(registers[11]), .Q(registers_16__ap[11]), .QN(), .SE(dftIn), + .SI(registers_10__ap[11]) + ); + SDFF_X1_LVT \registers_reg[31][11] ( + .CK(n_0_61), .D(registers[11]), .Q(registers_31__ap[11]), .QN(), .SE(dftIn), + .SI(registers_3__ap[11]) + ); + AOI22_X1_LVT i_1_0_918( + .A1(registers_16__ap[11]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[11]), + .ZN(n_1_0_874) + ); + SDFF_X1_LVT \registers_reg[15][11] ( + .CK(n_0_45), .D(registers[11]), .Q(registers_15__ap[11]), .QN(), .SE(dftIn), + .SI(registers_16__ap[11]) + ); + SDFF_X1_LVT \registers_reg[23][11] ( + .CK(n_0_53), .D(registers[11]), .Q(registers_23__ap[11]), .QN(), .SE(dftIn), + .SI(registers_1__ap[11]) + ); + AOI22_X1_LVT i_1_0_917( + .A1(registers_15__ap[11]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[11]), + .ZN(n_1_0_873) + ); + NAND4_X1_LVT i_1_0_916( + .A1(n_1_0_876), .A2(n_1_0_875), .A3(n_1_0_874), .A4(n_1_0_873), .ZN(n_1_0_872) + ); + SDFF_X1_LVT \registers_reg[18][11] ( + .CK(n_0_48), .D(registers[11]), .Q(registers_18__ap[11]), .QN(), .SE(dftIn), + .SI(registers_23__ap[11]) + ); + SDFF_X1_LVT \registers_reg[30][11] ( + .CK(n_0_60), .D(registers[11]), .Q(registers_30__ap[11]), .QN(), .SE(dftIn), + .SI(registers_29__ap[11]) + ); + AOI22_X1_LVT i_1_0_915( + .A1(registers_18__ap[11]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[11]), + .ZN(n_1_0_871) + ); + SDFF_X1_LVT \registers_reg[20][11] ( + .CK(n_0_50), .D(registers[11]), .Q(registers_20__ap[11]), .QN(), .SE(dftIn), + .SI(registers_18__ap[11]) + ); + SDFF_X1_LVT \registers_reg[4][11] ( + .CK(n_0_34), .D(registers[11]), .Q(registers_4__ap[11]), .QN(), .SE(dftIn), + .SI(registers_31__ap[11]) + ); + AOI22_X1_LVT i_1_0_914( + .A1(registers_20__ap[11]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[11]), + .ZN(n_1_0_870) + ); + SDFF_X1_LVT \registers_reg[22][11] ( + .CK(n_0_52), .D(registers[11]), .Q(registers_22__ap[11]), .QN(), .SE(dftIn), + .SI(registers_20__ap[11]) + ); + SDFF_X1_LVT \registers_reg[21][11] ( + .CK(n_0_51), .D(registers[11]), .Q(registers_21__ap[11]), .QN(), .SE(dftIn), + .SI(registers_22__ap[11]) + ); + AOI22_X1_LVT i_1_0_913( + .A1(registers_22__ap[11]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[11]), + .ZN(n_1_0_869) + ); + SDFF_X1_LVT \registers_reg[24][11] ( + .CK(n_0_54), .D(registers[11]), .Q(registers_24__ap[11]), .QN(), .SE(dftIn), + .SI(registers_30__ap[11]) + ); + SDFF_X1_LVT \registers_reg[12][11] ( + .CK(n_0_42), .D(registers[11]), .Q(registers_12__ap[11]), .QN(), .SE(dftIn), + .SI(registers_15__ap[11]) + ); + AOI22_X1_LVT i_1_0_912( + .A1(registers_24__ap[11]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[11]), + .ZN(n_1_0_868) + ); + NAND4_X1_LVT i_1_0_911( + .A1(n_1_0_871), .A2(n_1_0_870), .A3(n_1_0_869), .A4(n_1_0_868), .ZN(n_1_0_867) + ); + SDFF_X1_LVT \registers_reg[13][11] ( + .CK(n_0_43), .D(registers[11]), .Q(registers_13__ap[11]), .QN(), .SE(dftIn), + .SI(registers_12__ap[11]) + ); + SDFF_X1_LVT \registers_reg[25][11] ( + .CK(n_0_55), .D(registers[11]), .Q(registers_25__ap[11]), .QN(), .SE(dftIn), + .SI(registers_24__ap[11]) + ); + AOI22_X1_LVT i_1_0_910( + .A1(registers_13__ap[11]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[11]), + .ZN(n_1_0_866) + ); + SDFF_X1_LVT \registers_reg[19][11] ( + .CK(n_0_49), .D(registers[11]), .Q(registers_19__ap[11]), .QN(), .SE(dftIn), + .SI(registers_21__ap[11]) + ); + SDFF_X1_LVT \registers_reg[2][11] ( + .CK(n_0_32), .D(registers[11]), .Q(registers_2__ap[11]), .QN(), .SE(dftIn), + .SI(registers_25__ap[11]) + ); + AOI22_X1_LVT i_1_0_909( + .A1(registers_19__ap[11]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[11]), + .ZN(n_1_0_865) + ); + SDFF_X1_LVT \registers_reg[7][11] ( + .CK(n_0_37), .D(registers[11]), .Q(registers_7__ap[11]), .QN(), .SE(dftIn), + .SI(registers_4__ap[11]) + ); + SDFF_X1_LVT \registers_reg[14][11] ( + .CK(n_0_44), .D(registers[11]), .Q(registers_14__ap[11]), .QN(), .SE(dftIn), + .SI(registers_13__ap[11]) + ); + AOI22_X1_LVT i_1_0_908( + .A1(registers_7__ap[11]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[11]), + .ZN(n_1_0_864) + ); + SDFF_X1_LVT \registers_reg[27][11] ( + .CK(n_0_57), .D(registers[11]), .Q(registers_27__ap[11]), .QN(), .SE(dftIn), + .SI(registers_2__ap[11]) + ); + SDFF_X1_LVT \registers_reg[11][11] ( + .CK(n_0_41), .D(registers[11]), .Q(registers_11__ap[11]), .QN(), .SE(dftIn), + .SI(registers_14__ap[11]) + ); + AOI22_X1_LVT i_1_0_907( + .A1(registers_27__ap[11]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[11]), + .ZN(n_1_0_863) + ); + NAND4_X1_LVT i_1_0_906( + .A1(n_1_0_866), .A2(n_1_0_865), .A3(n_1_0_864), .A4(n_1_0_863), .ZN(n_1_0_862) + ); + NOR3_X1_LVT i_1_0_905( + .A1(n_1_0_872), .A2(n_1_0_867), .A3(n_1_0_862), .ZN(n_1_0_861) + ); + NAND4_X1_LVT i_1_0_904( + .A1(n_1_0_879), .A2(n_1_0_878), .A3(n_1_0_877), .A4(n_1_0_861), .ZN(RRs1[11]) + ); + AND2_X1_LVT i_0_0_10( + .A1(n_0_0_16), .A2(WRd[10]), .ZN(registers[10]) + ); + SDFF_X1_LVT \registers_reg[28][10] ( + .CK(n_0_58), .D(registers[10]), .Q(registers_28__ap[10]), .QN(), .SE(dftIn), + .SI(registers_27__ap[11]) + ); + SDFF_X1_LVT \registers_reg[8][10] ( + .CK(n_0_38), .D(registers[10]), .Q(registers_8__ap[10]), .QN(), .SE(dftIn), + .SI(registers_7__ap[11]) + ); + AOI22_X1_LVT i_1_0_902( + .A1(registers_28__ap[10]), .A2(n_1_0_1283), .B1(n_1_0_1282), .B2(registers_8__ap[10]), + .ZN(n_1_0_859) + ); + SDFF_X1_LVT \registers_reg[31][10] ( + .CK(n_0_61), .D(registers[10]), .Q(registers_31__ap[10]), .QN(), .SE(dftIn), + .SI(registers_8__ap[10]) + ); + SDFF_X1_LVT \registers_reg[7][10] ( + .CK(n_0_37), .D(registers[10]), .Q(registers_7__ap[10]), .QN(), .SE(dftIn), + .SI(registers_31__ap[10]) + ); + AOI22_X1_LVT i_1_0_903( + .A1(registers_31__ap[10]), .A2(n_1_0_1266), .B1(n_1_0_1263), .B2(registers_7__ap[10]), + .ZN(n_1_0_860) + ); + SDFF_X1_LVT \registers_reg[24][10] ( + .CK(n_0_54), .D(registers[10]), .Q(registers_24__ap[10]), .QN(), .SE(dftIn), + .SI(registers_28__ap[10]) + ); + SDFF_X1_LVT \registers_reg[20][10] ( + .CK(n_0_50), .D(registers[10]), .Q(registers_20__ap[10]), .QN(), .SE(dftIn), + .SI(registers_19__ap[11]) + ); + AOI22_X1_LVT i_1_0_901( + .A1(registers_24__ap[10]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[10]), + .ZN(n_1_0_858) + ); + SDFF_X1_LVT \registers_reg[4][10] ( + .CK(n_0_34), .D(registers[10]), .Q(registers_4__ap[10]), .QN(), .SE(dftIn), + .SI(registers_7__ap[10]) + ); + SDFF_X1_LVT \registers_reg[23][10] ( + .CK(n_0_53), .D(registers[10]), .Q(registers_23__ap[10]), .QN(), .SE(dftIn), + .SI(registers_20__ap[10]) + ); + AOI22_X1_LVT i_1_0_900( + .A1(registers_4__ap[10]), .A2(n_1_0_1278), .B1(n_1_0_1264), .B2(registers_23__ap[10]), + .ZN(n_1_0_857) + ); + NAND3_X1_LVT i_1_0_899( + .A1(n_1_0_860), .A2(n_1_0_858), .A3(n_1_0_857), .ZN(n_1_0_856) + ); + SDFF_X1_LVT \registers_reg[27][10] ( + .CK(n_0_57), .D(registers[10]), .Q(registers_27__ap[10]), .QN(), .SE(dftIn), + .SI(registers_24__ap[10]) + ); + SDFF_X1_LVT \registers_reg[29][10] ( + .CK(n_0_59), .D(registers[10]), .Q(registers_29__ap[10]), .QN(), .SE(dftIn), + .SI(registers_27__ap[10]) + ); + AOI221_X1_LVT i_1_0_898( + .A(n_1_0_856), .B1(n_1_0_1279), .B2(registers_27__ap[10]), .C1(registers_29__ap[10]), + .C2(n_1_0_1276), .ZN(n_1_0_855) + ); + SDFF_X1_LVT \registers_reg[10][10] ( + .CK(n_0_40), .D(registers[10]), .Q(registers_10__ap[10]), .QN(), .SE(dftIn), + .SI(registers_11__ap[11]) + ); + SDFF_X1_LVT \registers_reg[30][10] ( + .CK(n_0_60), .D(registers[10]), .Q(registers_30__ap[10]), .QN(), .SE(dftIn), + .SI(registers_29__ap[10]) + ); + SDFF_X1_LVT \registers_reg[25][10] ( + .CK(n_0_55), .D(registers[10]), .Q(registers_25__ap[10]), .QN(), .SE(dftIn), + .SI(registers_30__ap[10]) + ); + AOI222_X1_LVT i_1_0_897( + .A1(registers_10__ap[10]), .A2(n_1_0_1287), .B1(n_1_0_1272), .B2(registers_30__ap[10]), + .C1(n_1_0_1269), .C2(registers_25__ap[10]), .ZN(n_1_0_854) + ); + NAND3_X1_LVT i_1_0_896( + .A1(n_1_0_859), .A2(n_1_0_855), .A3(n_1_0_854), .ZN(n_1_0_853) + ); + SDFF_X1_LVT \registers_reg[21][10] ( + .CK(n_0_51), .D(registers[10]), .Q(registers_21__ap[10]), .QN(), .SE(dftIn), + .SI(registers_23__ap[10]) + ); + SDFF_X1_LVT \registers_reg[13][10] ( + .CK(n_0_43), .D(registers[10]), .Q(registers_13__ap[10]), .QN(), .SE(dftIn), + .SI(registers_10__ap[10]) + ); + AOI221_X1_LVT i_1_0_895( + .A(n_1_0_853), .B1(n_1_0_1259), .B2(registers_21__ap[10]), .C1(registers_13__ap[10]), + .C2(n_1_0_1277), .ZN(n_1_0_852) + ); + SDFF_X1_LVT \registers_reg[18][10] ( + .CK(n_0_48), .D(registers[10]), .Q(registers_18__ap[10]), .QN(), .SE(dftIn), + .SI(registers_21__ap[10]) + ); + SDFF_X1_LVT \registers_reg[26][10] ( + .CK(n_0_56), .D(registers[10]), .Q(registers_26__ap[10]), .QN(), .SE(dftIn), + .SI(registers_25__ap[10]) + ); + AOI22_X1_LVT i_1_0_894( + .A1(registers_18__ap[10]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[10]), + .ZN(n_1_0_851) + ); + SDFF_X1_LVT \registers_reg[17][10] ( + .CK(n_0_47), .D(registers[10]), .Q(registers_17__ap[10]), .QN(), .SE(dftIn), + .SI(registers_18__ap[10]) + ); + SDFF_X1_LVT \registers_reg[12][10] ( + .CK(n_0_42), .D(registers[10]), .Q(registers_12__ap[10]), .QN(), .SE(dftIn), + .SI(registers_13__ap[10]) + ); + AOI22_X1_LVT i_1_0_893( + .A1(registers_17__ap[10]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[10]), + .ZN(n_1_0_850) + ); + SDFF_X1_LVT \registers_reg[15][10] ( + .CK(n_0_45), .D(registers[10]), .Q(registers_15__ap[10]), .QN(), .SE(dftIn), + .SI(registers_12__ap[10]) + ); + SDFF_X1_LVT \registers_reg[5][10] ( + .CK(n_0_35), .D(registers[10]), .Q(registers_5__ap[10]), .QN(), .SE(dftIn), + .SI(registers_4__ap[10]) + ); + AOI22_X1_LVT i_1_0_892( + .A1(registers_15__ap[10]), .A2(n_1_0_1286), .B1(n_1_0_1273), .B2(registers_5__ap[10]), + .ZN(n_1_0_849) + ); + NAND3_X1_LVT i_1_0_891( + .A1(n_1_0_851), .A2(n_1_0_850), .A3(n_1_0_849), .ZN(n_1_0_848) + ); + SDFF_X1_LVT \registers_reg[22][10] ( + .CK(n_0_52), .D(registers[10]), .Q(registers_22__ap[10]), .QN(), .SE(dftIn), + .SI(registers_17__ap[10]) + ); + SDFF_X1_LVT \registers_reg[16][10] ( + .CK(n_0_46), .D(registers[10]), .Q(registers_16__ap[10]), .QN(), .SE(dftIn), + .SI(registers_15__ap[10]) + ); + AOI221_X1_LVT i_1_0_890( + .A(n_1_0_848), .B1(n_1_0_1294), .B2(registers_22__ap[10]), .C1(registers_16__ap[10]), + .C2(n_1_0_1267), .ZN(n_1_0_847) + ); + SDFF_X1_LVT \registers_reg[9][10] ( + .CK(n_0_39), .D(registers[10]), .Q(registers_9__ap[10]), .QN(), .SE(dftIn), + .SI(registers_5__ap[10]) + ); + SDFF_X1_LVT \registers_reg[1][10] ( + .CK(n_0_0), .D(registers[10]), .Q(registers_1__ap[10]), .QN(), .SE(dftIn), + .SI(registers_22__ap[10]) + ); + AOI22_X1_LVT i_1_0_889( + .A1(registers_9__ap[10]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[10]), + .ZN(n_1_0_846) + ); + SDFF_X1_LVT \registers_reg[6][10] ( + .CK(n_0_36), .D(registers[10]), .Q(registers_6__ap[10]), .QN(), .SE(dftIn), + .SI(registers_9__ap[10]) + ); + SDFF_X1_LVT \registers_reg[14][10] ( + .CK(n_0_44), .D(registers[10]), .Q(registers_14__ap[10]), .QN(), .SE(dftIn), + .SI(registers_16__ap[10]) + ); + AOI22_X1_LVT i_1_0_888( + .A1(registers_6__ap[10]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[10]), + .ZN(n_1_0_845) + ); + SDFF_X1_LVT \registers_reg[19][10] ( + .CK(n_0_49), .D(registers[10]), .Q(registers_19__ap[10]), .QN(), .SE(dftIn), + .SI(registers_1__ap[10]) + ); + SDFF_X1_LVT \registers_reg[3][10] ( + .CK(n_0_33), .D(registers[10]), .Q(registers_3__ap[10]), .QN(), .SE(dftIn), + .SI(registers_6__ap[10]) + ); + AOI22_X1_LVT i_1_0_887( + .A1(registers_19__ap[10]), .A2(n_1_0_1295), .B1(n_1_0_1257), .B2(registers_3__ap[10]), + .ZN(n_1_0_844) + ); + NAND3_X1_LVT i_1_0_886( + .A1(n_1_0_846), .A2(n_1_0_845), .A3(n_1_0_844), .ZN(n_1_0_843) + ); + SDFF_X1_LVT \registers_reg[11][10] ( + .CK(n_0_41), .D(registers[10]), .Q(registers_11__ap[10]), .QN(), .SE(dftIn), + .SI(registers_14__ap[10]) + ); + SDFF_X1_LVT \registers_reg[2][10] ( + .CK(n_0_32), .D(registers[10]), .Q(registers_2__ap[10]), .QN(), .SE(dftIn), + .SI(registers_26__ap[10]) + ); + AOI221_X1_LVT i_1_0_885( + .A(n_1_0_843), .B1(n_1_0_1270), .B2(registers_11__ap[10]), .C1(registers_2__ap[10]), + .C2(n_1_0_1268), .ZN(n_1_0_842) + ); + NAND3_X1_LVT i_1_0_884( + .A1(n_1_0_852), .A2(n_1_0_847), .A3(n_1_0_842), .ZN(RRs1[10]) + ); + AND2_X1_LVT i_0_0_9( + .A1(n_0_0_16), .A2(WRd[9]), .ZN(registers[9]) + ); + SDFF_X1_LVT \registers_reg[13][9] ( + .CK(n_0_43), .D(registers[9]), .Q(registers_13__ap[9]), .QN(), .SE(dftIn), + .SI(registers_11__ap[10]) + ); + SDFF_X1_LVT \registers_reg[21][9] ( + .CK(n_0_51), .D(registers[9]), .Q(registers_21__ap[9]), .QN(), .SE(dftIn), + .SI(registers_19__ap[10]) + ); + AOI22_X1_LVT i_1_0_880( + .A1(registers_13__ap[9]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[9]), + .ZN(n_1_0_838) + ); + SDFF_X1_LVT \registers_reg[29][9] ( + .CK(n_0_59), .D(registers[9]), .Q(registers_29__ap[9]), .QN(), .SE(dftIn), + .SI(registers_2__ap[10]) + ); + SDFF_X1_LVT \registers_reg[23][9] ( + .CK(n_0_53), .D(registers[9]), .Q(registers_23__ap[9]), .QN(), .SE(dftIn), + .SI(registers_21__ap[9]) + ); + AOI22_X1_LVT i_1_0_883( + .A1(registers_29__ap[9]), .A2(n_1_0_1276), .B1(n_1_0_1264), .B2(registers_23__ap[9]), + .ZN(n_1_0_841) + ); + SDFF_X1_LVT \registers_reg[24][9] ( + .CK(n_0_54), .D(registers[9]), .Q(registers_24__ap[9]), .QN(), .SE(dftIn), + .SI(registers_29__ap[9]) + ); + SDFF_X1_LVT \registers_reg[20][9] ( + .CK(n_0_50), .D(registers[9]), .Q(registers_20__ap[9]), .QN(), .SE(dftIn), + .SI(registers_23__ap[9]) + ); + AOI22_X1_LVT i_1_0_879( + .A1(registers_24__ap[9]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[9]), + .ZN(n_1_0_837) + ); + SDFF_X1_LVT \registers_reg[7][9] ( + .CK(n_0_37), .D(registers[9]), .Q(registers_7__ap[9]), .QN(), .SE(dftIn), + .SI(registers_3__ap[10]) + ); + SDFF_X1_LVT \registers_reg[3][9] ( + .CK(n_0_33), .D(registers[9]), .Q(registers_3__ap[9]), .QN(), .SE(dftIn), + .SI(registers_7__ap[9]) + ); + AOI22_X1_LVT i_1_0_882( + .A1(registers_7__ap[9]), .A2(n_1_0_1263), .B1(n_1_0_1257), .B2(registers_3__ap[9]), + .ZN(n_1_0_840) + ); + INV_X1_LVT i_1_0_881( + .A(n_1_0_840), .ZN(n_1_0_839) + ); + SDFF_X1_LVT \registers_reg[31][9] ( + .CK(n_0_61), .D(registers[9]), .Q(registers_31__ap[9]), .QN(), .SE(dftIn), + .SI(registers_3__ap[9]) + ); + SDFF_X1_LVT \registers_reg[4][9] ( + .CK(n_0_34), .D(registers[9]), .Q(registers_4__ap[9]), .QN(), .SE(dftIn), + .SI(registers_31__ap[9]) + ); + AOI221_X1_LVT i_1_0_878( + .A(n_1_0_839), .B1(n_1_0_1266), .B2(registers_31__ap[9]), .C1(registers_4__ap[9]), + .C2(n_1_0_1278), .ZN(n_1_0_836) + ); + SDFF_X1_LVT \registers_reg[10][9] ( + .CK(n_0_40), .D(registers[9]), .Q(registers_10__ap[9]), .QN(), .SE(dftIn), + .SI(registers_13__ap[9]) + ); + SDFF_X1_LVT \registers_reg[26][9] ( + .CK(n_0_56), .D(registers[9]), .Q(registers_26__ap[9]), .QN(), .SE(dftIn), + .SI(registers_24__ap[9]) + ); + SDFF_X1_LVT \registers_reg[25][9] ( + .CK(n_0_55), .D(registers[9]), .Q(registers_25__ap[9]), .QN(), .SE(dftIn), + .SI(registers_26__ap[9]) + ); + AOI222_X1_LVT i_1_0_877( + .A1(registers_10__ap[9]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[9]), + .C1(registers_25__ap[9]), .C2(n_1_0_1269), .ZN(n_1_0_835) + ); + NAND4_X1_LVT i_1_0_876( + .A1(n_1_0_841), .A2(n_1_0_837), .A3(n_1_0_836), .A4(n_1_0_835), .ZN(n_1_0_834) + ); + SDFF_X1_LVT \registers_reg[8][9] ( + .CK(n_0_38), .D(registers[9]), .Q(registers_8__ap[9]), .QN(), .SE(dftIn), + .SI(registers_4__ap[9]) + ); + SDFF_X1_LVT \registers_reg[28][9] ( + .CK(n_0_58), .D(registers[9]), .Q(registers_28__ap[9]), .QN(), .SE(dftIn), + .SI(registers_25__ap[9]) + ); + AOI221_X1_LVT i_1_0_875( + .A(n_1_0_834), .B1(n_1_0_1282), .B2(registers_8__ap[9]), .C1(registers_28__ap[9]), + .C2(n_1_0_1283), .ZN(n_1_0_833) + ); + SDFF_X1_LVT \registers_reg[18][9] ( + .CK(n_0_48), .D(registers[9]), .Q(registers_18__ap[9]), .QN(), .SE(dftIn), + .SI(registers_20__ap[9]) + ); + SDFF_X1_LVT \registers_reg[30][9] ( + .CK(n_0_60), .D(registers[9]), .Q(registers_30__ap[9]), .QN(), .SE(dftIn), + .SI(registers_28__ap[9]) + ); + AOI22_X1_LVT i_1_0_874( + .A1(registers_18__ap[9]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[9]), + .ZN(n_1_0_832) + ); + SDFF_X1_LVT \registers_reg[17][9] ( + .CK(n_0_47), .D(registers[9]), .Q(registers_17__ap[9]), .QN(), .SE(dftIn), + .SI(registers_18__ap[9]) + ); + SDFF_X1_LVT \registers_reg[12][9] ( + .CK(n_0_42), .D(registers[9]), .Q(registers_12__ap[9]), .QN(), .SE(dftIn), + .SI(registers_10__ap[9]) + ); + AOI22_X1_LVT i_1_0_873( + .A1(registers_17__ap[9]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[9]), + .ZN(n_1_0_831) + ); + SDFF_X1_LVT \registers_reg[15][9] ( + .CK(n_0_45), .D(registers[9]), .Q(registers_15__ap[9]), .QN(), .SE(dftIn), + .SI(registers_12__ap[9]) + ); + SDFF_X1_LVT \registers_reg[5][9] ( + .CK(n_0_35), .D(registers[9]), .Q(registers_5__ap[9]), .QN(), .SE(dftIn), + .SI(registers_8__ap[9]) + ); + AOI22_X1_LVT i_1_0_872( + .A1(registers_15__ap[9]), .A2(n_1_0_1286), .B1(n_1_0_1273), .B2(registers_5__ap[9]), + .ZN(n_1_0_830) + ); + NAND3_X1_LVT i_1_0_871( + .A1(n_1_0_832), .A2(n_1_0_831), .A3(n_1_0_830), .ZN(n_1_0_829) + ); + SDFF_X1_LVT \registers_reg[22][9] ( + .CK(n_0_52), .D(registers[9]), .Q(registers_22__ap[9]), .QN(), .SE(dftIn), + .SI(registers_17__ap[9]) + ); + SDFF_X1_LVT \registers_reg[16][9] ( + .CK(n_0_46), .D(registers[9]), .Q(registers_16__ap[9]), .QN(), .SE(dftIn), + .SI(registers_15__ap[9]) + ); + AOI221_X1_LVT i_1_0_870( + .A(n_1_0_829), .B1(n_1_0_1294), .B2(registers_22__ap[9]), .C1(registers_16__ap[9]), + .C2(n_1_0_1267), .ZN(n_1_0_828) + ); + SDFF_X1_LVT \registers_reg[9][9] ( + .CK(n_0_39), .D(registers[9]), .Q(registers_9__ap[9]), .QN(), .SE(dftIn), + .SI(registers_5__ap[9]) + ); + SDFF_X1_LVT \registers_reg[1][9] ( + .CK(n_0_0), .D(registers[9]), .Q(registers_1__ap[9]), .QN(), .SE(dftIn), + .SI(registers_22__ap[9]) + ); + AOI22_X1_LVT i_1_0_869( + .A1(registers_9__ap[9]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[9]), + .ZN(n_1_0_827) + ); + SDFF_X1_LVT \registers_reg[6][9] ( + .CK(n_0_36), .D(registers[9]), .Q(registers_6__ap[9]), .QN(), .SE(dftIn), + .SI(registers_9__ap[9]) + ); + SDFF_X1_LVT \registers_reg[14][9] ( + .CK(n_0_44), .D(registers[9]), .Q(registers_14__ap[9]), .QN(), .SE(dftIn), + .SI(registers_16__ap[9]) + ); + AOI22_X1_LVT i_1_0_868( + .A1(registers_6__ap[9]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[9]), + .ZN(n_1_0_826) + ); + SDFF_X1_LVT \registers_reg[19][9] ( + .CK(n_0_49), .D(registers[9]), .Q(registers_19__ap[9]), .QN(), .SE(dftIn), + .SI(registers_1__ap[9]) + ); + SDFF_X1_LVT \registers_reg[2][9] ( + .CK(n_0_32), .D(registers[9]), .Q(registers_2__ap[9]), .QN(), .SE(dftIn), + .SI(registers_30__ap[9]) + ); + AOI22_X1_LVT i_1_0_867( + .A1(registers_19__ap[9]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[9]), + .ZN(n_1_0_825) + ); + NAND3_X1_LVT i_1_0_866( + .A1(n_1_0_827), .A2(n_1_0_826), .A3(n_1_0_825), .ZN(n_1_0_824) + ); + SDFF_X1_LVT \registers_reg[11][9] ( + .CK(n_0_41), .D(registers[9]), .Q(registers_11__ap[9]), .QN(), .SE(dftIn), + .SI(registers_14__ap[9]) + ); + SDFF_X1_LVT \registers_reg[27][9] ( + .CK(n_0_57), .D(registers[9]), .Q(registers_27__ap[9]), .QN(), .SE(dftIn), + .SI(registers_2__ap[9]) + ); + AOI221_X1_LVT i_1_0_865( + .A(n_1_0_824), .B1(n_1_0_1270), .B2(registers_11__ap[9]), .C1(registers_27__ap[9]), + .C2(n_1_0_1279), .ZN(n_1_0_823) + ); + NAND4_X1_LVT i_1_0_864( + .A1(n_1_0_838), .A2(n_1_0_833), .A3(n_1_0_828), .A4(n_1_0_823), .ZN(RRs1[9]) + ); + AND2_X1_LVT i_0_0_8( + .A1(n_0_0_16), .A2(WRd[8]), .ZN(registers[8]) + ); + SDFF_X1_LVT \registers_reg[13][8] ( + .CK(n_0_43), .D(registers[8]), .Q(registers_13__ap[8]), .QN(), .SE(dftIn), + .SI(registers_11__ap[9]) + ); + SDFF_X1_LVT \registers_reg[21][8] ( + .CK(n_0_51), .D(registers[8]), .Q(registers_21__ap[8]), .QN(), .SE(dftIn), + .SI(registers_19__ap[9]) + ); + AOI22_X1_LVT i_1_0_860( + .A1(registers_13__ap[8]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[8]), + .ZN(n_1_0_819) + ); + SDFF_X1_LVT \registers_reg[29][8] ( + .CK(n_0_59), .D(registers[8]), .Q(registers_29__ap[8]), .QN(), .SE(dftIn), + .SI(registers_27__ap[9]) + ); + SDFF_X1_LVT \registers_reg[23][8] ( + .CK(n_0_53), .D(registers[8]), .Q(registers_23__ap[8]), .QN(), .SE(dftIn), + .SI(registers_21__ap[8]) + ); + AOI22_X1_LVT i_1_0_863( + .A1(registers_29__ap[8]), .A2(n_1_0_1276), .B1(n_1_0_1264), .B2(registers_23__ap[8]), + .ZN(n_1_0_822) + ); + SDFF_X1_LVT \registers_reg[24][8] ( + .CK(n_0_54), .D(registers[8]), .Q(registers_24__ap[8]), .QN(), .SE(dftIn), + .SI(registers_29__ap[8]) + ); + SDFF_X1_LVT \registers_reg[20][8] ( + .CK(n_0_50), .D(registers[8]), .Q(registers_20__ap[8]), .QN(), .SE(dftIn), + .SI(registers_23__ap[8]) + ); + AOI22_X1_LVT i_1_0_859( + .A1(registers_24__ap[8]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[8]), + .ZN(n_1_0_818) + ); + SDFF_X1_LVT \registers_reg[7][8] ( + .CK(n_0_37), .D(registers[8]), .Q(registers_7__ap[8]), .QN(), .SE(dftIn), + .SI(registers_6__ap[9]) + ); + SDFF_X1_LVT \registers_reg[3][8] ( + .CK(n_0_33), .D(registers[8]), .Q(registers_3__ap[8]), .QN(), .SE(dftIn), + .SI(registers_7__ap[8]) + ); + AOI22_X1_LVT i_1_0_862( + .A1(registers_7__ap[8]), .A2(n_1_0_1263), .B1(n_1_0_1257), .B2(registers_3__ap[8]), + .ZN(n_1_0_821) + ); + INV_X1_LVT i_1_0_861( + .A(n_1_0_821), .ZN(n_1_0_820) + ); + SDFF_X1_LVT \registers_reg[31][8] ( + .CK(n_0_61), .D(registers[8]), .Q(registers_31__ap[8]), .QN(), .SE(dftIn), + .SI(registers_3__ap[8]) + ); + SDFF_X1_LVT \registers_reg[4][8] ( + .CK(n_0_34), .D(registers[8]), .Q(registers_4__ap[8]), .QN(), .SE(dftIn), + .SI(registers_31__ap[8]) + ); + AOI221_X1_LVT i_1_0_858( + .A(n_1_0_820), .B1(n_1_0_1266), .B2(registers_31__ap[8]), .C1(registers_4__ap[8]), + .C2(n_1_0_1278), .ZN(n_1_0_817) + ); + SDFF_X1_LVT \registers_reg[10][8] ( + .CK(n_0_40), .D(registers[8]), .Q(registers_10__ap[8]), .QN(), .SE(dftIn), + .SI(registers_13__ap[8]) + ); + SDFF_X1_LVT \registers_reg[26][8] ( + .CK(n_0_56), .D(registers[8]), .Q(registers_26__ap[8]), .QN(), .SE(dftIn), + .SI(registers_24__ap[8]) + ); + SDFF_X1_LVT \registers_reg[25][8] ( + .CK(n_0_55), .D(registers[8]), .Q(registers_25__ap[8]), .QN(), .SE(dftIn), + .SI(registers_26__ap[8]) + ); + AOI222_X1_LVT i_1_0_857( + .A1(registers_10__ap[8]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[8]), + .C1(registers_25__ap[8]), .C2(n_1_0_1269), .ZN(n_1_0_816) + ); + NAND4_X1_LVT i_1_0_856( + .A1(n_1_0_822), .A2(n_1_0_818), .A3(n_1_0_817), .A4(n_1_0_816), .ZN(n_1_0_815) + ); + SDFF_X1_LVT \registers_reg[8][8] ( + .CK(n_0_38), .D(registers[8]), .Q(registers_8__ap[8]), .QN(), .SE(dftIn), + .SI(registers_4__ap[8]) + ); + SDFF_X1_LVT \registers_reg[28][8] ( + .CK(n_0_58), .D(registers[8]), .Q(registers_28__ap[8]), .QN(), .SE(dftIn), + .SI(registers_25__ap[8]) + ); + AOI221_X1_LVT i_1_0_855( + .A(n_1_0_815), .B1(n_1_0_1282), .B2(registers_8__ap[8]), .C1(registers_28__ap[8]), + .C2(n_1_0_1283), .ZN(n_1_0_814) + ); + SDFF_X1_LVT \registers_reg[18][8] ( + .CK(n_0_48), .D(registers[8]), .Q(registers_18__ap[8]), .QN(), .SE(dftIn), + .SI(registers_20__ap[8]) + ); + SDFF_X1_LVT \registers_reg[30][8] ( + .CK(n_0_60), .D(registers[8]), .Q(registers_30__ap[8]), .QN(), .SE(dftIn), + .SI(registers_28__ap[8]) + ); + AOI22_X1_LVT i_1_0_854( + .A1(registers_18__ap[8]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[8]), + .ZN(n_1_0_813) + ); + SDFF_X1_LVT \registers_reg[17][8] ( + .CK(n_0_47), .D(registers[8]), .Q(registers_17__ap[8]), .QN(), .SE(dftIn), + .SI(registers_18__ap[8]) + ); + SDFF_X1_LVT \registers_reg[12][8] ( + .CK(n_0_42), .D(registers[8]), .Q(registers_12__ap[8]), .QN(), .SE(dftIn), + .SI(registers_10__ap[8]) + ); + AOI22_X1_LVT i_1_0_853( + .A1(registers_17__ap[8]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[8]), + .ZN(n_1_0_812) + ); + SDFF_X1_LVT \registers_reg[15][8] ( + .CK(n_0_45), .D(registers[8]), .Q(registers_15__ap[8]), .QN(), .SE(dftIn), + .SI(registers_12__ap[8]) + ); + SDFF_X1_LVT \registers_reg[5][8] ( + .CK(n_0_35), .D(registers[8]), .Q(registers_5__ap[8]), .QN(), .SE(dftIn), + .SI(registers_8__ap[8]) + ); + AOI22_X1_LVT i_1_0_852( + .A1(registers_15__ap[8]), .A2(n_1_0_1286), .B1(n_1_0_1273), .B2(registers_5__ap[8]), + .ZN(n_1_0_811) + ); + NAND3_X1_LVT i_1_0_851( + .A1(n_1_0_813), .A2(n_1_0_812), .A3(n_1_0_811), .ZN(n_1_0_810) + ); + SDFF_X1_LVT \registers_reg[22][8] ( + .CK(n_0_52), .D(registers[8]), .Q(registers_22__ap[8]), .QN(), .SE(dftIn), + .SI(registers_17__ap[8]) + ); + SDFF_X1_LVT \registers_reg[16][8] ( + .CK(n_0_46), .D(registers[8]), .Q(registers_16__ap[8]), .QN(), .SE(dftIn), + .SI(registers_15__ap[8]) + ); + AOI221_X1_LVT i_1_0_850( + .A(n_1_0_810), .B1(n_1_0_1294), .B2(registers_22__ap[8]), .C1(registers_16__ap[8]), + .C2(n_1_0_1267), .ZN(n_1_0_809) + ); + SDFF_X1_LVT \registers_reg[9][8] ( + .CK(n_0_39), .D(registers[8]), .Q(registers_9__ap[8]), .QN(), .SE(dftIn), + .SI(registers_5__ap[8]) + ); + SDFF_X1_LVT \registers_reg[1][8] ( + .CK(n_0_0), .D(registers[8]), .Q(registers_1__ap[8]), .QN(), .SE(dftIn), + .SI(registers_22__ap[8]) + ); + AOI22_X1_LVT i_1_0_849( + .A1(registers_9__ap[8]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[8]), + .ZN(n_1_0_808) + ); + SDFF_X1_LVT \registers_reg[6][8] ( + .CK(n_0_36), .D(registers[8]), .Q(registers_6__ap[8]), .QN(), .SE(dftIn), + .SI(registers_9__ap[8]) + ); + SDFF_X1_LVT \registers_reg[14][8] ( + .CK(n_0_44), .D(registers[8]), .Q(registers_14__ap[8]), .QN(), .SE(dftIn), + .SI(registers_16__ap[8]) + ); + AOI22_X1_LVT i_1_0_848( + .A1(registers_6__ap[8]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[8]), + .ZN(n_1_0_807) + ); + SDFF_X1_LVT \registers_reg[19][8] ( + .CK(n_0_49), .D(registers[8]), .Q(registers_19__ap[8]), .QN(), .SE(dftIn), + .SI(registers_1__ap[8]) + ); + SDFF_X1_LVT \registers_reg[2][8] ( + .CK(n_0_32), .D(registers[8]), .Q(registers_2__ap[8]), .QN(), .SE(dftIn), + .SI(registers_30__ap[8]) + ); + AOI22_X1_LVT i_1_0_847( + .A1(registers_19__ap[8]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[8]), + .ZN(n_1_0_806) + ); + NAND3_X1_LVT i_1_0_846( + .A1(n_1_0_808), .A2(n_1_0_807), .A3(n_1_0_806), .ZN(n_1_0_805) + ); + SDFF_X1_LVT \registers_reg[11][8] ( + .CK(n_0_41), .D(registers[8]), .Q(registers_11__ap[8]), .QN(), .SE(dftIn), + .SI(registers_14__ap[8]) + ); + SDFF_X1_LVT \registers_reg[27][8] ( + .CK(n_0_57), .D(registers[8]), .Q(registers_27__ap[8]), .QN(), .SE(dftIn), + .SI(registers_2__ap[8]) + ); + AOI221_X1_LVT i_1_0_845( + .A(n_1_0_805), .B1(n_1_0_1270), .B2(registers_11__ap[8]), .C1(registers_27__ap[8]), + .C2(n_1_0_1279), .ZN(n_1_0_804) + ); + NAND4_X1_LVT i_1_0_844( + .A1(n_1_0_819), .A2(n_1_0_814), .A3(n_1_0_809), .A4(n_1_0_804), .ZN(RRs1[8]) + ); + AND2_X1_LVT i_0_0_7( + .A1(n_0_0_16), .A2(WRd[7]), .ZN(registers[7]) + ); + SDFF_X1_LVT \registers_reg[13][7] ( + .CK(n_0_43), .D(registers[7]), .Q(registers_13__ap[7]), .QN(), .SE(dftIn), + .SI(registers_11__ap[8]) + ); + SDFF_X1_LVT \registers_reg[21][7] ( + .CK(n_0_51), .D(registers[7]), .Q(registers_21__ap[7]), .QN(), .SE(dftIn), + .SI(registers_19__ap[8]) + ); + AOI22_X1_LVT i_1_0_843( + .A1(registers_13__ap[7]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[7]), + .ZN(n_1_0_803) + ); + SDFF_X1_LVT \registers_reg[18][7] ( + .CK(n_0_48), .D(registers[7]), .Q(registers_18__ap[7]), .QN(), .SE(dftIn), + .SI(registers_21__ap[7]) + ); + SDFF_X1_LVT \registers_reg[10][7] ( + .CK(n_0_40), .D(registers[7]), .Q(registers_10__ap[7]), .QN(), .SE(dftIn), + .SI(registers_13__ap[7]) + ); + SDFF_X1_LVT \registers_reg[25][7] ( + .CK(n_0_55), .D(registers[7]), .Q(registers_25__ap[7]), .QN(), .SE(dftIn), + .SI(registers_27__ap[8]) + ); + AOI222_X1_LVT i_1_0_842( + .A1(registers_18__ap[7]), .A2(n_1_0_1297), .B1(n_1_0_1287), .B2(registers_10__ap[7]), + .C1(registers_25__ap[7]), .C2(n_1_0_1269), .ZN(n_1_0_802) + ); + SDFF_X1_LVT \registers_reg[28][7] ( + .CK(n_0_58), .D(registers[7]), .Q(registers_28__ap[7]), .QN(), .SE(dftIn), + .SI(registers_25__ap[7]) + ); + SDFF_X1_LVT \registers_reg[8][7] ( + .CK(n_0_38), .D(registers[7]), .Q(registers_8__ap[7]), .QN(), .SE(dftIn), + .SI(registers_6__ap[8]) + ); + AOI22_X1_LVT i_1_0_841( + .A1(registers_28__ap[7]), .A2(n_1_0_1283), .B1(n_1_0_1282), .B2(registers_8__ap[7]), + .ZN(n_1_0_801) + ); + SDFF_X1_LVT \registers_reg[24][7] ( + .CK(n_0_54), .D(registers[7]), .Q(registers_24__ap[7]), .QN(), .SE(dftIn), + .SI(registers_28__ap[7]) + ); + SDFF_X1_LVT \registers_reg[20][7] ( + .CK(n_0_50), .D(registers[7]), .Q(registers_20__ap[7]), .QN(), .SE(dftIn), + .SI(registers_18__ap[7]) + ); + AOI22_X1_LVT i_1_0_840( + .A1(registers_24__ap[7]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[7]), + .ZN(n_1_0_800) + ); + SDFF_X1_LVT \registers_reg[31][7] ( + .CK(n_0_61), .D(registers[7]), .Q(registers_31__ap[7]), .QN(), .SE(dftIn), + .SI(registers_8__ap[7]) + ); + SDFF_X1_LVT \registers_reg[7][7] ( + .CK(n_0_37), .D(registers[7]), .Q(registers_7__ap[7]), .QN(), .SE(dftIn), + .SI(registers_31__ap[7]) + ); + AOI22_X1_LVT i_1_0_839( + .A1(registers_31__ap[7]), .A2(n_1_0_1266), .B1(n_1_0_1263), .B2(registers_7__ap[7]), + .ZN(n_1_0_799) + ); + SDFF_X1_LVT \registers_reg[17][7] ( + .CK(n_0_47), .D(registers[7]), .Q(registers_17__ap[7]), .QN(), .SE(dftIn), + .SI(registers_20__ap[7]) + ); + SDFF_X1_LVT \registers_reg[11][7] ( + .CK(n_0_41), .D(registers[7]), .Q(registers_11__ap[7]), .QN(), .SE(dftIn), + .SI(registers_10__ap[7]) + ); + AOI22_X1_LVT i_1_0_838( + .A1(registers_17__ap[7]), .A2(n_1_0_1271), .B1(n_1_0_1270), .B2(registers_11__ap[7]), + .ZN(n_1_0_798) + ); + SDFF_X1_LVT \registers_reg[27][7] ( + .CK(n_0_57), .D(registers[7]), .Q(registers_27__ap[7]), .QN(), .SE(dftIn), + .SI(registers_24__ap[7]) + ); + SDFF_X1_LVT \registers_reg[29][7] ( + .CK(n_0_59), .D(registers[7]), .Q(registers_29__ap[7]), .QN(), .SE(dftIn), + .SI(registers_27__ap[7]) + ); + AOI22_X1_LVT i_1_0_837( + .A1(registers_27__ap[7]), .A2(n_1_0_1279), .B1(n_1_0_1276), .B2(registers_29__ap[7]), + .ZN(n_1_0_797) + ); + NAND4_X1_LVT i_1_0_836( + .A1(n_1_0_800), .A2(n_1_0_799), .A3(n_1_0_798), .A4(n_1_0_797), .ZN(n_1_0_796) + ); + SDFF_X1_LVT \registers_reg[26][7] ( + .CK(n_0_56), .D(registers[7]), .Q(registers_26__ap[7]), .QN(), .SE(dftIn), + .SI(registers_29__ap[7]) + ); + SDFF_X1_LVT \registers_reg[30][7] ( + .CK(n_0_60), .D(registers[7]), .Q(registers_30__ap[7]), .QN(), .SE(dftIn), + .SI(registers_26__ap[7]) + ); + AOI22_X1_LVT i_1_0_835( + .A1(registers_26__ap[7]), .A2(n_1_0_1285), .B1(n_1_0_1272), .B2(registers_30__ap[7]), + .ZN(n_1_0_795) + ); + SDFF_X1_LVT \registers_reg[4][7] ( + .CK(n_0_34), .D(registers[7]), .Q(registers_4__ap[7]), .QN(), .SE(dftIn), + .SI(registers_7__ap[7]) + ); + SDFF_X1_LVT \registers_reg[12][7] ( + .CK(n_0_42), .D(registers[7]), .Q(registers_12__ap[7]), .QN(), .SE(dftIn), + .SI(registers_11__ap[7]) + ); + AOI22_X1_LVT i_1_0_834( + .A1(registers_4__ap[7]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[7]), + .ZN(n_1_0_794) + ); + SDFF_X1_LVT \registers_reg[15][7] ( + .CK(n_0_45), .D(registers[7]), .Q(registers_15__ap[7]), .QN(), .SE(dftIn), + .SI(registers_12__ap[7]) + ); + SDFF_X1_LVT \registers_reg[16][7] ( + .CK(n_0_46), .D(registers[7]), .Q(registers_16__ap[7]), .QN(), .SE(dftIn), + .SI(registers_15__ap[7]) + ); + AOI22_X1_LVT i_1_0_833( + .A1(registers_15__ap[7]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[7]), + .ZN(n_1_0_793) + ); + SDFF_X1_LVT \registers_reg[22][7] ( + .CK(n_0_52), .D(registers[7]), .Q(registers_22__ap[7]), .QN(), .SE(dftIn), + .SI(registers_17__ap[7]) + ); + SDFF_X1_LVT \registers_reg[5][7] ( + .CK(n_0_35), .D(registers[7]), .Q(registers_5__ap[7]), .QN(), .SE(dftIn), + .SI(registers_4__ap[7]) + ); + AOI22_X1_LVT i_1_0_832( + .A1(registers_22__ap[7]), .A2(n_1_0_1294), .B1(n_1_0_1273), .B2(registers_5__ap[7]), + .ZN(n_1_0_792) + ); + NAND4_X1_LVT i_1_0_831( + .A1(n_1_0_795), .A2(n_1_0_794), .A3(n_1_0_793), .A4(n_1_0_792), .ZN(n_1_0_791) + ); + SDFF_X1_LVT \registers_reg[19][7] ( + .CK(n_0_49), .D(registers[7]), .Q(registers_19__ap[7]), .QN(), .SE(dftIn), + .SI(registers_22__ap[7]) + ); + SDFF_X1_LVT \registers_reg[3][7] ( + .CK(n_0_33), .D(registers[7]), .Q(registers_3__ap[7]), .QN(), .SE(dftIn), + .SI(registers_5__ap[7]) + ); + AOI22_X1_LVT i_1_0_830( + .A1(registers_19__ap[7]), .A2(n_1_0_1295), .B1(n_1_0_1257), .B2(registers_3__ap[7]), + .ZN(n_1_0_790) + ); + SDFF_X1_LVT \registers_reg[9][7] ( + .CK(n_0_39), .D(registers[7]), .Q(registers_9__ap[7]), .QN(), .SE(dftIn), + .SI(registers_3__ap[7]) + ); + SDFF_X1_LVT \registers_reg[1][7] ( + .CK(n_0_0), .D(registers[7]), .Q(registers_1__ap[7]), .QN(), .SE(dftIn), + .SI(registers_19__ap[7]) + ); + AOI22_X1_LVT i_1_0_829( + .A1(registers_9__ap[7]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[7]), + .ZN(n_1_0_789) + ); + SDFF_X1_LVT \registers_reg[6][7] ( + .CK(n_0_36), .D(registers[7]), .Q(registers_6__ap[7]), .QN(), .SE(dftIn), + .SI(registers_9__ap[7]) + ); + SDFF_X1_LVT \registers_reg[14][7] ( + .CK(n_0_44), .D(registers[7]), .Q(registers_14__ap[7]), .QN(), .SE(dftIn), + .SI(registers_16__ap[7]) + ); + AOI22_X1_LVT i_1_0_828( + .A1(registers_6__ap[7]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[7]), + .ZN(n_1_0_788) + ); + SDFF_X1_LVT \registers_reg[2][7] ( + .CK(n_0_32), .D(registers[7]), .Q(registers_2__ap[7]), .QN(), .SE(dftIn), + .SI(registers_30__ap[7]) + ); + SDFF_X1_LVT \registers_reg[23][7] ( + .CK(n_0_53), .D(registers[7]), .Q(registers_23__ap[7]), .QN(), .SE(dftIn), + .SI(registers_1__ap[7]) + ); + AOI22_X1_LVT i_1_0_827( + .A1(registers_2__ap[7]), .A2(n_1_0_1268), .B1(n_1_0_1264), .B2(registers_23__ap[7]), + .ZN(n_1_0_787) + ); + NAND4_X1_LVT i_1_0_826( + .A1(n_1_0_790), .A2(n_1_0_789), .A3(n_1_0_788), .A4(n_1_0_787), .ZN(n_1_0_786) + ); + NOR3_X1_LVT i_1_0_825( + .A1(n_1_0_796), .A2(n_1_0_791), .A3(n_1_0_786), .ZN(n_1_0_785) + ); + NAND4_X1_LVT i_1_0_824( + .A1(n_1_0_803), .A2(n_1_0_802), .A3(n_1_0_801), .A4(n_1_0_785), .ZN(RRs1[7]) + ); + AND2_X1_LVT i_0_0_6( + .A1(n_0_0_16), .A2(WRd[6]), .ZN(registers[6]) + ); + SDFF_X1_LVT \registers_reg[28][6] ( + .CK(n_0_58), .D(registers[6]), .Q(registers_28__ap[6]), .QN(), .SE(dftIn), + .SI(registers_2__ap[7]) + ); + SDFF_X1_LVT \registers_reg[17][6] ( + .CK(n_0_47), .D(registers[6]), .Q(registers_17__ap[6]), .QN(), .SE(dftIn), + .SI(registers_23__ap[7]) + ); + AOI22_X1_LVT i_1_0_823( + .A1(registers_28__ap[6]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[6]), + .ZN(n_1_0_784) + ); + SDFF_X1_LVT \registers_reg[18][6] ( + .CK(n_0_48), .D(registers[6]), .Q(registers_18__ap[6]), .QN(), .SE(dftIn), + .SI(registers_17__ap[6]) + ); + SDFF_X1_LVT \registers_reg[10][6] ( + .CK(n_0_40), .D(registers[6]), .Q(registers_10__ap[6]), .QN(), .SE(dftIn), + .SI(registers_14__ap[7]) + ); + SDFF_X1_LVT \registers_reg[8][6] ( + .CK(n_0_38), .D(registers[6]), .Q(registers_8__ap[6]), .QN(), .SE(dftIn), + .SI(registers_6__ap[7]) + ); + AOI222_X1_LVT i_1_0_822( + .A1(registers_18__ap[6]), .A2(n_1_0_1297), .B1(n_1_0_1287), .B2(registers_10__ap[6]), + .C1(registers_8__ap[6]), .C2(n_1_0_1282), .ZN(n_1_0_783) + ); + SDFF_X1_LVT \registers_reg[9][6] ( + .CK(n_0_39), .D(registers[6]), .Q(registers_9__ap[6]), .QN(), .SE(dftIn), + .SI(registers_8__ap[6]) + ); + SDFF_X1_LVT \registers_reg[29][6] ( + .CK(n_0_59), .D(registers[6]), .Q(registers_29__ap[6]), .QN(), .SE(dftIn), + .SI(registers_28__ap[6]) + ); + AOI22_X1_LVT i_1_0_821( + .A1(registers_9__ap[6]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[6]), + .ZN(n_1_0_782) + ); + SDFF_X1_LVT \registers_reg[6][6] ( + .CK(n_0_36), .D(registers[6]), .Q(registers_6__ap[6]), .QN(), .SE(dftIn), + .SI(registers_9__ap[6]) + ); + SDFF_X1_LVT \registers_reg[1][6] ( + .CK(n_0_0), .D(registers[6]), .Q(registers_1__ap[6]), .QN(), .SE(dftIn), + .SI(registers_18__ap[6]) + ); + AOI22_X1_LVT i_1_0_820( + .A1(registers_6__ap[6]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[6]), + .ZN(n_1_0_781) + ); + SDFF_X1_LVT \registers_reg[15][6] ( + .CK(n_0_45), .D(registers[6]), .Q(registers_15__ap[6]), .QN(), .SE(dftIn), + .SI(registers_10__ap[6]) + ); + SDFF_X1_LVT \registers_reg[27][6] ( + .CK(n_0_57), .D(registers[6]), .Q(registers_27__ap[6]), .QN(), .SE(dftIn), + .SI(registers_29__ap[6]) + ); + AOI22_X1_LVT i_1_0_819( + .A1(registers_15__ap[6]), .A2(n_1_0_1286), .B1(n_1_0_1279), .B2(registers_27__ap[6]), + .ZN(n_1_0_780) + ); + SDFF_X1_LVT \registers_reg[11][6] ( + .CK(n_0_41), .D(registers[6]), .Q(registers_11__ap[6]), .QN(), .SE(dftIn), + .SI(registers_15__ap[6]) + ); + SDFF_X1_LVT \registers_reg[16][6] ( + .CK(n_0_46), .D(registers[6]), .Q(registers_16__ap[6]), .QN(), .SE(dftIn), + .SI(registers_11__ap[6]) + ); + AOI22_X1_LVT i_1_0_818( + .A1(registers_11__ap[6]), .A2(n_1_0_1270), .B1(n_1_0_1267), .B2(registers_16__ap[6]), + .ZN(n_1_0_779) + ); + SDFF_X1_LVT \registers_reg[5][6] ( + .CK(n_0_35), .D(registers[6]), .Q(registers_5__ap[6]), .QN(), .SE(dftIn), + .SI(registers_6__ap[6]) + ); + SDFF_X1_LVT \registers_reg[31][6] ( + .CK(n_0_61), .D(registers[6]), .Q(registers_31__ap[6]), .QN(), .SE(dftIn), + .SI(registers_5__ap[6]) + ); + AOI22_X1_LVT i_1_0_817( + .A1(registers_5__ap[6]), .A2(n_1_0_1273), .B1(n_1_0_1266), .B2(registers_31__ap[6]), + .ZN(n_1_0_778) + ); + NAND4_X1_LVT i_1_0_816( + .A1(n_1_0_781), .A2(n_1_0_780), .A3(n_1_0_779), .A4(n_1_0_778), .ZN(n_1_0_777) + ); + SDFF_X1_LVT \registers_reg[26][6] ( + .CK(n_0_56), .D(registers[6]), .Q(registers_26__ap[6]), .QN(), .SE(dftIn), + .SI(registers_27__ap[6]) + ); + SDFF_X1_LVT \registers_reg[30][6] ( + .CK(n_0_60), .D(registers[6]), .Q(registers_30__ap[6]), .QN(), .SE(dftIn), + .SI(registers_26__ap[6]) + ); + AOI22_X1_LVT i_1_0_815( + .A1(registers_26__ap[6]), .A2(n_1_0_1285), .B1(n_1_0_1272), .B2(registers_30__ap[6]), + .ZN(n_1_0_776) + ); + SDFF_X1_LVT \registers_reg[20][6] ( + .CK(n_0_50), .D(registers[6]), .Q(registers_20__ap[6]), .QN(), .SE(dftIn), + .SI(registers_1__ap[6]) + ); + SDFF_X1_LVT \registers_reg[4][6] ( + .CK(n_0_34), .D(registers[6]), .Q(registers_4__ap[6]), .QN(), .SE(dftIn), + .SI(registers_31__ap[6]) + ); + AOI22_X1_LVT i_1_0_814( + .A1(registers_20__ap[6]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[6]), + .ZN(n_1_0_775) + ); + SDFF_X1_LVT \registers_reg[22][6] ( + .CK(n_0_52), .D(registers[6]), .Q(registers_22__ap[6]), .QN(), .SE(dftIn), + .SI(registers_20__ap[6]) + ); + SDFF_X1_LVT \registers_reg[21][6] ( + .CK(n_0_51), .D(registers[6]), .Q(registers_21__ap[6]), .QN(), .SE(dftIn), + .SI(registers_22__ap[6]) + ); + AOI22_X1_LVT i_1_0_813( + .A1(registers_22__ap[6]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[6]), + .ZN(n_1_0_774) + ); + SDFF_X1_LVT \registers_reg[24][6] ( + .CK(n_0_54), .D(registers[6]), .Q(registers_24__ap[6]), .QN(), .SE(dftIn), + .SI(registers_30__ap[6]) + ); + SDFF_X1_LVT \registers_reg[12][6] ( + .CK(n_0_42), .D(registers[6]), .Q(registers_12__ap[6]), .QN(), .SE(dftIn), + .SI(registers_16__ap[6]) + ); + AOI22_X1_LVT i_1_0_812( + .A1(registers_24__ap[6]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[6]), + .ZN(n_1_0_773) + ); + NAND4_X1_LVT i_1_0_811( + .A1(n_1_0_776), .A2(n_1_0_775), .A3(n_1_0_774), .A4(n_1_0_773), .ZN(n_1_0_772) + ); + SDFF_X1_LVT \registers_reg[13][6] ( + .CK(n_0_43), .D(registers[6]), .Q(registers_13__ap[6]), .QN(), .SE(dftIn), + .SI(registers_12__ap[6]) + ); + SDFF_X1_LVT \registers_reg[25][6] ( + .CK(n_0_55), .D(registers[6]), .Q(registers_25__ap[6]), .QN(), .SE(dftIn), + .SI(registers_24__ap[6]) + ); + AOI22_X1_LVT i_1_0_810( + .A1(registers_13__ap[6]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[6]), + .ZN(n_1_0_771) + ); + SDFF_X1_LVT \registers_reg[7][6] ( + .CK(n_0_37), .D(registers[6]), .Q(registers_7__ap[6]), .QN(), .SE(dftIn), + .SI(registers_4__ap[6]) + ); + SDFF_X1_LVT \registers_reg[14][6] ( + .CK(n_0_44), .D(registers[6]), .Q(registers_14__ap[6]), .QN(), .SE(dftIn), + .SI(registers_13__ap[6]) + ); + AOI22_X1_LVT i_1_0_809( + .A1(registers_7__ap[6]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[6]), + .ZN(n_1_0_770) + ); + SDFF_X1_LVT \registers_reg[19][6] ( + .CK(n_0_49), .D(registers[6]), .Q(registers_19__ap[6]), .QN(), .SE(dftIn), + .SI(registers_21__ap[6]) + ); + SDFF_X1_LVT \registers_reg[3][6] ( + .CK(n_0_33), .D(registers[6]), .Q(registers_3__ap[6]), .QN(), .SE(dftIn), + .SI(registers_7__ap[6]) + ); + AOI22_X1_LVT i_1_0_808( + .A1(registers_19__ap[6]), .A2(n_1_0_1295), .B1(n_1_0_1257), .B2(registers_3__ap[6]), + .ZN(n_1_0_769) + ); + SDFF_X1_LVT \registers_reg[2][6] ( + .CK(n_0_32), .D(registers[6]), .Q(registers_2__ap[6]), .QN(), .SE(dftIn), + .SI(registers_25__ap[6]) + ); + SDFF_X1_LVT \registers_reg[23][6] ( + .CK(n_0_53), .D(registers[6]), .Q(registers_23__ap[6]), .QN(), .SE(dftIn), + .SI(registers_19__ap[6]) + ); + AOI22_X1_LVT i_1_0_807( + .A1(registers_2__ap[6]), .A2(n_1_0_1268), .B1(n_1_0_1264), .B2(registers_23__ap[6]), + .ZN(n_1_0_768) + ); + NAND4_X1_LVT i_1_0_806( + .A1(n_1_0_771), .A2(n_1_0_770), .A3(n_1_0_769), .A4(n_1_0_768), .ZN(n_1_0_767) + ); + NOR3_X1_LVT i_1_0_805( + .A1(n_1_0_777), .A2(n_1_0_772), .A3(n_1_0_767), .ZN(n_1_0_766) + ); + NAND4_X1_LVT i_1_0_804( + .A1(n_1_0_784), .A2(n_1_0_783), .A3(n_1_0_782), .A4(n_1_0_766), .ZN(RRs1[6]) + ); + AND2_X1_LVT i_0_0_5( + .A1(n_0_0_16), .A2(WRd[5]), .ZN(registers[5]) + ); + SDFF_X1_LVT \registers_reg[28][5] ( + .CK(n_0_58), .D(registers[5]), .Q(registers_28__ap[5]), .QN(), .SE(dftIn), + .SI(registers_2__ap[6]) + ); + SDFF_X1_LVT \registers_reg[4][5] ( + .CK(n_0_34), .D(registers[5]), .Q(registers_4__ap[5]), .QN(), .SE(dftIn), + .SI(registers_3__ap[6]) + ); + AOI22_X1_LVT i_1_0_803( + .A1(registers_28__ap[5]), .A2(n_1_0_1283), .B1(n_1_0_1278), .B2(registers_4__ap[5]), + .ZN(n_1_0_765) + ); + SDFF_X1_LVT \registers_reg[10][5] ( + .CK(n_0_40), .D(registers[5]), .Q(registers_10__ap[5]), .QN(), .SE(dftIn), + .SI(registers_14__ap[6]) + ); + SDFF_X1_LVT \registers_reg[26][5] ( + .CK(n_0_56), .D(registers[5]), .Q(registers_26__ap[5]), .QN(), .SE(dftIn), + .SI(registers_28__ap[5]) + ); + SDFF_X1_LVT \registers_reg[8][5] ( + .CK(n_0_38), .D(registers[5]), .Q(registers_8__ap[5]), .QN(), .SE(dftIn), + .SI(registers_4__ap[5]) + ); + AOI222_X1_LVT i_1_0_802( + .A1(registers_10__ap[5]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[5]), + .C1(registers_8__ap[5]), .C2(n_1_0_1282), .ZN(n_1_0_764) + ); + SDFF_X1_LVT \registers_reg[9][5] ( + .CK(n_0_39), .D(registers[5]), .Q(registers_9__ap[5]), .QN(), .SE(dftIn), + .SI(registers_8__ap[5]) + ); + SDFF_X1_LVT \registers_reg[29][5] ( + .CK(n_0_59), .D(registers[5]), .Q(registers_29__ap[5]), .QN(), .SE(dftIn), + .SI(registers_26__ap[5]) + ); + AOI22_X1_LVT i_1_0_801( + .A1(registers_9__ap[5]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[5]), + .ZN(n_1_0_763) + ); + SDFF_X1_LVT \registers_reg[6][5] ( + .CK(n_0_36), .D(registers[5]), .Q(registers_6__ap[5]), .QN(), .SE(dftIn), + .SI(registers_9__ap[5]) + ); + SDFF_X1_LVT \registers_reg[1][5] ( + .CK(n_0_0), .D(registers[5]), .Q(registers_1__ap[5]), .QN(), .SE(dftIn), + .SI(registers_23__ap[6]) + ); + AOI22_X1_LVT i_1_0_800( + .A1(registers_6__ap[5]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[5]), + .ZN(n_1_0_762) + ); + SDFF_X1_LVT \registers_reg[16][5] ( + .CK(n_0_46), .D(registers[5]), .Q(registers_16__ap[5]), .QN(), .SE(dftIn), + .SI(registers_10__ap[5]) + ); + SDFF_X1_LVT \registers_reg[3][5] ( + .CK(n_0_33), .D(registers[5]), .Q(registers_3__ap[5]), .QN(), .SE(dftIn), + .SI(registers_6__ap[5]) + ); + AOI22_X1_LVT i_1_0_799( + .A1(registers_16__ap[5]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[5]), + .ZN(n_1_0_761) + ); + SDFF_X1_LVT \registers_reg[5][5] ( + .CK(n_0_35), .D(registers[5]), .Q(registers_5__ap[5]), .QN(), .SE(dftIn), + .SI(registers_3__ap[5]) + ); + SDFF_X1_LVT \registers_reg[31][5] ( + .CK(n_0_61), .D(registers[5]), .Q(registers_31__ap[5]), .QN(), .SE(dftIn), + .SI(registers_5__ap[5]) + ); + AOI22_X1_LVT i_1_0_798( + .A1(registers_5__ap[5]), .A2(n_1_0_1273), .B1(n_1_0_1266), .B2(registers_31__ap[5]), + .ZN(n_1_0_760) + ); + SDFF_X1_LVT \registers_reg[15][5] ( + .CK(n_0_45), .D(registers[5]), .Q(registers_15__ap[5]), .QN(), .SE(dftIn), + .SI(registers_16__ap[5]) + ); + SDFF_X1_LVT \registers_reg[23][5] ( + .CK(n_0_53), .D(registers[5]), .Q(registers_23__ap[5]), .QN(), .SE(dftIn), + .SI(registers_1__ap[5]) + ); + AOI22_X1_LVT i_1_0_797( + .A1(registers_15__ap[5]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[5]), + .ZN(n_1_0_759) + ); + NAND4_X1_LVT i_1_0_796( + .A1(n_1_0_762), .A2(n_1_0_761), .A3(n_1_0_760), .A4(n_1_0_759), .ZN(n_1_0_758) + ); + SDFF_X1_LVT \registers_reg[18][5] ( + .CK(n_0_48), .D(registers[5]), .Q(registers_18__ap[5]), .QN(), .SE(dftIn), + .SI(registers_23__ap[5]) + ); + SDFF_X1_LVT \registers_reg[30][5] ( + .CK(n_0_60), .D(registers[5]), .Q(registers_30__ap[5]), .QN(), .SE(dftIn), + .SI(registers_29__ap[5]) + ); + AOI22_X1_LVT i_1_0_795( + .A1(registers_18__ap[5]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[5]), + .ZN(n_1_0_757) + ); + SDFF_X1_LVT \registers_reg[24][5] ( + .CK(n_0_54), .D(registers[5]), .Q(registers_24__ap[5]), .QN(), .SE(dftIn), + .SI(registers_30__ap[5]) + ); + SDFF_X1_LVT \registers_reg[12][5] ( + .CK(n_0_42), .D(registers[5]), .Q(registers_12__ap[5]), .QN(), .SE(dftIn), + .SI(registers_15__ap[5]) + ); + AOI22_X1_LVT i_1_0_794( + .A1(registers_24__ap[5]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[5]), + .ZN(n_1_0_756) + ); + SDFF_X1_LVT \registers_reg[22][5] ( + .CK(n_0_52), .D(registers[5]), .Q(registers_22__ap[5]), .QN(), .SE(dftIn), + .SI(registers_18__ap[5]) + ); + SDFF_X1_LVT \registers_reg[21][5] ( + .CK(n_0_51), .D(registers[5]), .Q(registers_21__ap[5]), .QN(), .SE(dftIn), + .SI(registers_22__ap[5]) + ); + AOI22_X1_LVT i_1_0_793( + .A1(registers_22__ap[5]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[5]), + .ZN(n_1_0_755) + ); + SDFF_X1_LVT \registers_reg[20][5] ( + .CK(n_0_50), .D(registers[5]), .Q(registers_20__ap[5]), .QN(), .SE(dftIn), + .SI(registers_21__ap[5]) + ); + SDFF_X1_LVT \registers_reg[17][5] ( + .CK(n_0_47), .D(registers[5]), .Q(registers_17__ap[5]), .QN(), .SE(dftIn), + .SI(registers_20__ap[5]) + ); + AOI22_X1_LVT i_1_0_792( + .A1(registers_20__ap[5]), .A2(n_1_0_1281), .B1(n_1_0_1271), .B2(registers_17__ap[5]), + .ZN(n_1_0_754) + ); + NAND4_X1_LVT i_1_0_791( + .A1(n_1_0_757), .A2(n_1_0_756), .A3(n_1_0_755), .A4(n_1_0_754), .ZN(n_1_0_753) + ); + SDFF_X1_LVT \registers_reg[13][5] ( + .CK(n_0_43), .D(registers[5]), .Q(registers_13__ap[5]), .QN(), .SE(dftIn), + .SI(registers_12__ap[5]) + ); + SDFF_X1_LVT \registers_reg[25][5] ( + .CK(n_0_55), .D(registers[5]), .Q(registers_25__ap[5]), .QN(), .SE(dftIn), + .SI(registers_24__ap[5]) + ); + AOI22_X1_LVT i_1_0_790( + .A1(registers_13__ap[5]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[5]), + .ZN(n_1_0_752) + ); + SDFF_X1_LVT \registers_reg[19][5] ( + .CK(n_0_49), .D(registers[5]), .Q(registers_19__ap[5]), .QN(), .SE(dftIn), + .SI(registers_17__ap[5]) + ); + SDFF_X1_LVT \registers_reg[2][5] ( + .CK(n_0_32), .D(registers[5]), .Q(registers_2__ap[5]), .QN(), .SE(dftIn), + .SI(registers_25__ap[5]) + ); + AOI22_X1_LVT i_1_0_789( + .A1(registers_19__ap[5]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[5]), + .ZN(n_1_0_751) + ); + SDFF_X1_LVT \registers_reg[7][5] ( + .CK(n_0_37), .D(registers[5]), .Q(registers_7__ap[5]), .QN(), .SE(dftIn), + .SI(registers_31__ap[5]) + ); + SDFF_X1_LVT \registers_reg[14][5] ( + .CK(n_0_44), .D(registers[5]), .Q(registers_14__ap[5]), .QN(), .SE(dftIn), + .SI(registers_13__ap[5]) + ); + AOI22_X1_LVT i_1_0_788( + .A1(registers_7__ap[5]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[5]), + .ZN(n_1_0_750) + ); + SDFF_X1_LVT \registers_reg[27][5] ( + .CK(n_0_57), .D(registers[5]), .Q(registers_27__ap[5]), .QN(), .SE(dftIn), + .SI(registers_2__ap[5]) + ); + SDFF_X1_LVT \registers_reg[11][5] ( + .CK(n_0_41), .D(registers[5]), .Q(registers_11__ap[5]), .QN(), .SE(dftIn), + .SI(registers_14__ap[5]) + ); + AOI22_X1_LVT i_1_0_787( + .A1(registers_27__ap[5]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[5]), + .ZN(n_1_0_749) + ); + NAND4_X1_LVT i_1_0_786( + .A1(n_1_0_752), .A2(n_1_0_751), .A3(n_1_0_750), .A4(n_1_0_749), .ZN(n_1_0_748) + ); + NOR3_X1_LVT i_1_0_785( + .A1(n_1_0_758), .A2(n_1_0_753), .A3(n_1_0_748), .ZN(n_1_0_747) + ); + NAND4_X1_LVT i_1_0_784( + .A1(n_1_0_765), .A2(n_1_0_764), .A3(n_1_0_763), .A4(n_1_0_747), .ZN(RRs1[5]) + ); + AND2_X1_LVT i_0_0_4( + .A1(n_0_0_16), .A2(WRd[4]), .ZN(registers[4]) + ); + SDFF_X1_LVT \registers_reg[10][4] ( + .CK(n_0_40), .D(registers[4]), .Q(registers_10__ap[4]), .QN(), .SE(dftIn), + .SI(registers_11__ap[5]) + ); + SDFF_X1_LVT \registers_reg[21][4] ( + .CK(n_0_51), .D(registers[4]), .Q(registers_21__ap[4]), .QN(), .SE(dftIn), + .SI(registers_19__ap[5]) + ); + AOI22_X1_LVT i_1_0_783( + .A1(registers_10__ap[4]), .A2(n_1_0_1287), .B1(n_1_0_1259), .B2(registers_21__ap[4]), + .ZN(n_1_0_746) + ); + SDFF_X1_LVT \registers_reg[9][4] ( + .CK(n_0_39), .D(registers[4]), .Q(registers_9__ap[4]), .QN(), .SE(dftIn), + .SI(registers_7__ap[5]) + ); + SDFF_X1_LVT \registers_reg[1][4] ( + .CK(n_0_0), .D(registers[4]), .Q(registers_1__ap[4]), .QN(), .SE(dftIn), + .SI(registers_21__ap[4]) + ); + AOI22_X1_LVT i_1_0_778( + .A1(registers_9__ap[4]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[4]), + .ZN(n_1_0_741) + ); + SDFF_X1_LVT \registers_reg[18][4] ( + .CK(n_0_48), .D(registers[4]), .Q(registers_18__ap[4]), .QN(), .SE(dftIn), + .SI(registers_1__ap[4]) + ); + SDFF_X1_LVT \registers_reg[8][4] ( + .CK(n_0_38), .D(registers[4]), .Q(registers_8__ap[4]), .QN(), .SE(dftIn), + .SI(registers_9__ap[4]) + ); + AOI22_X1_LVT i_1_0_777( + .A1(registers_18__ap[4]), .A2(n_1_0_1297), .B1(n_1_0_1282), .B2(registers_8__ap[4]), + .ZN(n_1_0_740) + ); + NAND3_X1_LVT i_1_0_775( + .A1(n_1_0_746), .A2(n_1_0_741), .A3(n_1_0_740), .ZN(n_1_0_738) + ); + SDFF_X1_LVT \registers_reg[22][4] ( + .CK(n_0_52), .D(registers[4]), .Q(registers_22__ap[4]), .QN(), .SE(dftIn), + .SI(registers_18__ap[4]) + ); + SDFF_X1_LVT \registers_reg[23][4] ( + .CK(n_0_53), .D(registers[4]), .Q(registers_23__ap[4]), .QN(), .SE(dftIn), + .SI(registers_22__ap[4]) + ); + AOI221_X1_LVT i_1_0_774( + .A(n_1_0_738), .B1(n_1_0_1294), .B2(registers_22__ap[4]), .C1(registers_23__ap[4]), + .C2(n_1_0_1264), .ZN(n_1_0_737) + ); + SDFF_X1_LVT \registers_reg[28][4] ( + .CK(n_0_58), .D(registers[4]), .Q(registers_28__ap[4]), .QN(), .SE(dftIn), + .SI(registers_27__ap[5]) + ); + SDFF_X1_LVT \registers_reg[20][4] ( + .CK(n_0_50), .D(registers[4]), .Q(registers_20__ap[4]), .QN(), .SE(dftIn), + .SI(registers_23__ap[4]) + ); + AOI22_X1_LVT i_1_0_782( + .A1(registers_28__ap[4]), .A2(n_1_0_1283), .B1(n_1_0_1281), .B2(registers_20__ap[4]), + .ZN(n_1_0_745) + ); + SDFF_X1_LVT \registers_reg[19][4] ( + .CK(n_0_49), .D(registers[4]), .Q(registers_19__ap[4]), .QN(), .SE(dftIn), + .SI(registers_20__ap[4]) + ); + SDFF_X1_LVT \registers_reg[13][4] ( + .CK(n_0_43), .D(registers[4]), .Q(registers_13__ap[4]), .QN(), .SE(dftIn), + .SI(registers_10__ap[4]) + ); + AOI22_X1_LVT i_1_0_780( + .A1(registers_19__ap[4]), .A2(n_1_0_1295), .B1(n_1_0_1277), .B2(registers_13__ap[4]), + .ZN(n_1_0_743) + ); + SDFF_X1_LVT \registers_reg[26][4] ( + .CK(n_0_56), .D(registers[4]), .Q(registers_26__ap[4]), .QN(), .SE(dftIn), + .SI(registers_28__ap[4]) + ); + SDFF_X1_LVT \registers_reg[3][4] ( + .CK(n_0_33), .D(registers[4]), .Q(registers_3__ap[4]), .QN(), .SE(dftIn), + .SI(registers_8__ap[4]) + ); + AOI22_X1_LVT i_1_0_776( + .A1(registers_26__ap[4]), .A2(n_1_0_1285), .B1(n_1_0_1257), .B2(registers_3__ap[4]), + .ZN(n_1_0_739) + ); + NAND3_X1_LVT i_1_0_773( + .A1(n_1_0_745), .A2(n_1_0_743), .A3(n_1_0_739), .ZN(n_1_0_736) + ); + SDFF_X1_LVT \registers_reg[30][4] ( + .CK(n_0_60), .D(registers[4]), .Q(registers_30__ap[4]), .QN(), .SE(dftIn), + .SI(registers_26__ap[4]) + ); + SDFF_X1_LVT \registers_reg[31][4] ( + .CK(n_0_61), .D(registers[4]), .Q(registers_31__ap[4]), .QN(), .SE(dftIn), + .SI(registers_3__ap[4]) + ); + AOI221_X1_LVT i_1_0_772( + .A(n_1_0_736), .B1(n_1_0_1272), .B2(registers_30__ap[4]), .C1(registers_31__ap[4]), + .C2(n_1_0_1266), .ZN(n_1_0_735) + ); + SDFF_X1_LVT \registers_reg[24][4] ( + .CK(n_0_54), .D(registers[4]), .Q(registers_24__ap[4]), .QN(), .SE(dftIn), + .SI(registers_30__ap[4]) + ); + SDFF_X1_LVT \registers_reg[12][4] ( + .CK(n_0_42), .D(registers[4]), .Q(registers_12__ap[4]), .QN(), .SE(dftIn), + .SI(registers_13__ap[4]) + ); + AOI22_X1_LVT i_1_0_781( + .A1(registers_24__ap[4]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[4]), + .ZN(n_1_0_744) + ); + SDFF_X1_LVT \registers_reg[27][4] ( + .CK(n_0_57), .D(registers[4]), .Q(registers_27__ap[4]), .QN(), .SE(dftIn), + .SI(registers_24__ap[4]) + ); + SDFF_X1_LVT \registers_reg[11][4] ( + .CK(n_0_41), .D(registers[4]), .Q(registers_11__ap[4]), .QN(), .SE(dftIn), + .SI(registers_12__ap[4]) + ); + AOI22_X1_LVT i_1_0_779( + .A1(registers_27__ap[4]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[4]), + .ZN(n_1_0_742) + ); + SDFF_X1_LVT \registers_reg[17][4] ( + .CK(n_0_47), .D(registers[4]), .Q(registers_17__ap[4]), .QN(), .SE(dftIn), + .SI(registers_19__ap[4]) + ); + SDFF_X1_LVT \registers_reg[7][4] ( + .CK(n_0_37), .D(registers[4]), .Q(registers_7__ap[4]), .QN(), .SE(dftIn), + .SI(registers_31__ap[4]) + ); + SDFF_X1_LVT \registers_reg[14][4] ( + .CK(n_0_44), .D(registers[4]), .Q(registers_14__ap[4]), .QN(), .SE(dftIn), + .SI(registers_11__ap[4]) + ); + AOI222_X1_LVT i_1_0_771( + .A1(registers_17__ap[4]), .A2(n_1_0_1271), .B1(n_1_0_1263), .B2(registers_7__ap[4]), + .C1(n_1_0_1258), .C2(registers_14__ap[4]), .ZN(n_1_0_734) + ); + SDFF_X1_LVT \registers_reg[15][4] ( + .CK(n_0_45), .D(registers[4]), .Q(registers_15__ap[4]), .QN(), .SE(dftIn), + .SI(registers_14__ap[4]) + ); + SDFF_X1_LVT \registers_reg[16][4] ( + .CK(n_0_46), .D(registers[4]), .Q(registers_16__ap[4]), .QN(), .SE(dftIn), + .SI(registers_15__ap[4]) + ); + AOI22_X1_LVT i_1_0_770( + .A1(registers_15__ap[4]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[4]), + .ZN(n_1_0_733) + ); + SDFF_X1_LVT \registers_reg[4][4] ( + .CK(n_0_34), .D(registers[4]), .Q(registers_4__ap[4]), .QN(), .SE(dftIn), + .SI(registers_7__ap[4]) + ); + SDFF_X1_LVT \registers_reg[25][4] ( + .CK(n_0_55), .D(registers[4]), .Q(registers_25__ap[4]), .QN(), .SE(dftIn), + .SI(registers_27__ap[4]) + ); + AOI22_X1_LVT i_1_0_769( + .A1(registers_4__ap[4]), .A2(n_1_0_1278), .B1(n_1_0_1269), .B2(registers_25__ap[4]), + .ZN(n_1_0_732) + ); + SDFF_X1_LVT \registers_reg[29][4] ( + .CK(n_0_59), .D(registers[4]), .Q(registers_29__ap[4]), .QN(), .SE(dftIn), + .SI(registers_25__ap[4]) + ); + SDFF_X1_LVT \registers_reg[2][4] ( + .CK(n_0_32), .D(registers[4]), .Q(registers_2__ap[4]), .QN(), .SE(dftIn), + .SI(registers_29__ap[4]) + ); + AOI22_X1_LVT i_1_0_768( + .A1(registers_29__ap[4]), .A2(n_1_0_1276), .B1(n_1_0_1268), .B2(registers_2__ap[4]), + .ZN(n_1_0_731) + ); + NAND3_X1_LVT i_1_0_767( + .A1(n_1_0_733), .A2(n_1_0_732), .A3(n_1_0_731), .ZN(n_1_0_730) + ); + SDFF_X1_LVT \registers_reg[6][4] ( + .CK(n_0_36), .D(registers[4]), .Q(registers_6__ap[4]), .QN(), .SE(dftIn), + .SI(registers_4__ap[4]) + ); + SDFF_X1_LVT \registers_reg[5][4] ( + .CK(n_0_35), .D(registers[4]), .Q(registers_5__ap[4]), .QN(), .SE(dftIn), + .SI(registers_6__ap[4]) + ); + AOI221_X1_LVT i_1_0_766( + .A(n_1_0_730), .B1(n_1_0_1300), .B2(registers_6__ap[4]), .C1(registers_5__ap[4]), + .C2(n_1_0_1273), .ZN(n_1_0_729) + ); + AND4_X1_LVT i_1_0_765( + .A1(n_1_0_744), .A2(n_1_0_742), .A3(n_1_0_734), .A4(n_1_0_729), .ZN(n_1_0_728) + ); + NAND3_X1_LVT i_1_0_764( + .A1(n_1_0_737), .A2(n_1_0_735), .A3(n_1_0_728), .ZN(RRs1[4]) + ); + AND2_X1_LVT i_0_0_3( + .A1(n_0_0_16), .A2(WRd[3]), .ZN(registers[3]) + ); + SDFF_X1_LVT \registers_reg[28][3] ( + .CK(n_0_58), .D(registers[3]), .Q(registers_28__ap[3]), .QN(), .SE(dftIn), + .SI(registers_2__ap[4]) + ); + SDFF_X1_LVT \registers_reg[17][3] ( + .CK(n_0_47), .D(registers[3]), .Q(registers_17__ap[3]), .QN(), .SE(dftIn), + .SI(registers_17__ap[4]) + ); + AOI22_X1_LVT i_1_0_763( + .A1(registers_28__ap[3]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[3]), + .ZN(n_1_0_727) + ); + SDFF_X1_LVT \registers_reg[10][3] ( + .CK(n_0_40), .D(registers[3]), .Q(registers_10__ap[3]), .QN(), .SE(dftIn), + .SI(registers_16__ap[4]) + ); + SDFF_X1_LVT \registers_reg[26][3] ( + .CK(n_0_56), .D(registers[3]), .Q(registers_26__ap[3]), .QN(), .SE(dftIn), + .SI(registers_28__ap[3]) + ); + SDFF_X1_LVT \registers_reg[8][3] ( + .CK(n_0_38), .D(registers[3]), .Q(registers_8__ap[3]), .QN(), .SE(dftIn), + .SI(registers_5__ap[4]) + ); + AOI222_X1_LVT i_1_0_762( + .A1(registers_10__ap[3]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[3]), + .C1(registers_8__ap[3]), .C2(n_1_0_1282), .ZN(n_1_0_726) + ); + SDFF_X1_LVT \registers_reg[9][3] ( + .CK(n_0_39), .D(registers[3]), .Q(registers_9__ap[3]), .QN(), .SE(dftIn), + .SI(registers_8__ap[3]) + ); + SDFF_X1_LVT \registers_reg[29][3] ( + .CK(n_0_59), .D(registers[3]), .Q(registers_29__ap[3]), .QN(), .SE(dftIn), + .SI(registers_26__ap[3]) + ); + AOI22_X1_LVT i_1_0_761( + .A1(registers_9__ap[3]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[3]), + .ZN(n_1_0_725) + ); + SDFF_X1_LVT \registers_reg[6][3] ( + .CK(n_0_36), .D(registers[3]), .Q(registers_6__ap[3]), .QN(), .SE(dftIn), + .SI(registers_9__ap[3]) + ); + SDFF_X1_LVT \registers_reg[1][3] ( + .CK(n_0_0), .D(registers[3]), .Q(registers_1__ap[3]), .QN(), .SE(dftIn), + .SI(registers_17__ap[3]) + ); + AOI22_X1_LVT i_1_0_760( + .A1(registers_6__ap[3]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[3]), + .ZN(n_1_0_724) + ); + SDFF_X1_LVT \registers_reg[16][3] ( + .CK(n_0_46), .D(registers[3]), .Q(registers_16__ap[3]), .QN(), .SE(dftIn), + .SI(registers_10__ap[3]) + ); + SDFF_X1_LVT \registers_reg[3][3] ( + .CK(n_0_33), .D(registers[3]), .Q(registers_3__ap[3]), .QN(), .SE(dftIn), + .SI(registers_6__ap[3]) + ); + AOI22_X1_LVT i_1_0_759( + .A1(registers_16__ap[3]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[3]), + .ZN(n_1_0_723) + ); + SDFF_X1_LVT \registers_reg[5][3] ( + .CK(n_0_35), .D(registers[3]), .Q(registers_5__ap[3]), .QN(), .SE(dftIn), + .SI(registers_3__ap[3]) + ); + SDFF_X1_LVT \registers_reg[31][3] ( + .CK(n_0_61), .D(registers[3]), .Q(registers_31__ap[3]), .QN(), .SE(dftIn), + .SI(registers_5__ap[3]) + ); + AOI22_X1_LVT i_1_0_758( + .A1(registers_5__ap[3]), .A2(n_1_0_1273), .B1(n_1_0_1266), .B2(registers_31__ap[3]), + .ZN(n_1_0_722) + ); + SDFF_X1_LVT \registers_reg[15][3] ( + .CK(n_0_45), .D(registers[3]), .Q(registers_15__ap[3]), .QN(), .SE(dftIn), + .SI(registers_16__ap[3]) + ); + SDFF_X1_LVT \registers_reg[23][3] ( + .CK(n_0_53), .D(registers[3]), .Q(registers_23__ap[3]), .QN(), .SE(dftIn), + .SI(registers_1__ap[3]) + ); + AOI22_X1_LVT i_1_0_757( + .A1(registers_15__ap[3]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[3]), + .ZN(n_1_0_721) + ); + NAND4_X1_LVT i_1_0_756( + .A1(n_1_0_724), .A2(n_1_0_723), .A3(n_1_0_722), .A4(n_1_0_721), .ZN(n_1_0_720) + ); + SDFF_X1_LVT \registers_reg[18][3] ( + .CK(n_0_48), .D(registers[3]), .Q(registers_18__ap[3]), .QN(), .SE(dftIn), + .SI(registers_23__ap[3]) + ); + SDFF_X1_LVT \registers_reg[30][3] ( + .CK(n_0_60), .D(registers[3]), .Q(registers_30__ap[3]), .QN(), .SE(dftIn), + .SI(registers_29__ap[3]) + ); + AOI22_X1_LVT i_1_0_755( + .A1(registers_18__ap[3]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[3]), + .ZN(n_1_0_719) + ); + SDFF_X1_LVT \registers_reg[20][3] ( + .CK(n_0_50), .D(registers[3]), .Q(registers_20__ap[3]), .QN(), .SE(dftIn), + .SI(registers_18__ap[3]) + ); + SDFF_X1_LVT \registers_reg[4][3] ( + .CK(n_0_34), .D(registers[3]), .Q(registers_4__ap[3]), .QN(), .SE(dftIn), + .SI(registers_31__ap[3]) + ); + AOI22_X1_LVT i_1_0_754( + .A1(registers_20__ap[3]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[3]), + .ZN(n_1_0_718) + ); + SDFF_X1_LVT \registers_reg[22][3] ( + .CK(n_0_52), .D(registers[3]), .Q(registers_22__ap[3]), .QN(), .SE(dftIn), + .SI(registers_20__ap[3]) + ); + SDFF_X1_LVT \registers_reg[21][3] ( + .CK(n_0_51), .D(registers[3]), .Q(registers_21__ap[3]), .QN(), .SE(dftIn), + .SI(registers_22__ap[3]) + ); + AOI22_X1_LVT i_1_0_753( + .A1(registers_22__ap[3]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[3]), + .ZN(n_1_0_717) + ); + SDFF_X1_LVT \registers_reg[24][3] ( + .CK(n_0_54), .D(registers[3]), .Q(registers_24__ap[3]), .QN(), .SE(dftIn), + .SI(registers_30__ap[3]) + ); + SDFF_X1_LVT \registers_reg[12][3] ( + .CK(n_0_42), .D(registers[3]), .Q(registers_12__ap[3]), .QN(), .SE(dftIn), + .SI(registers_15__ap[3]) + ); + AOI22_X1_LVT i_1_0_752( + .A1(registers_24__ap[3]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[3]), + .ZN(n_1_0_716) + ); + NAND4_X1_LVT i_1_0_751( + .A1(n_1_0_719), .A2(n_1_0_718), .A3(n_1_0_717), .A4(n_1_0_716), .ZN(n_1_0_715) + ); + SDFF_X1_LVT \registers_reg[13][3] ( + .CK(n_0_43), .D(registers[3]), .Q(registers_13__ap[3]), .QN(), .SE(dftIn), + .SI(registers_12__ap[3]) + ); + SDFF_X1_LVT \registers_reg[25][3] ( + .CK(n_0_55), .D(registers[3]), .Q(registers_25__ap[3]), .QN(), .SE(dftIn), + .SI(registers_24__ap[3]) + ); + AOI22_X1_LVT i_1_0_750( + .A1(registers_13__ap[3]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[3]), + .ZN(n_1_0_714) + ); + SDFF_X1_LVT \registers_reg[19][3] ( + .CK(n_0_49), .D(registers[3]), .Q(registers_19__ap[3]), .QN(), .SE(dftIn), + .SI(registers_21__ap[3]) + ); + SDFF_X1_LVT \registers_reg[2][3] ( + .CK(n_0_32), .D(registers[3]), .Q(registers_2__ap[3]), .QN(), .SE(dftIn), + .SI(registers_25__ap[3]) + ); + AOI22_X1_LVT i_1_0_749( + .A1(registers_19__ap[3]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[3]), + .ZN(n_1_0_713) + ); + SDFF_X1_LVT \registers_reg[7][3] ( + .CK(n_0_37), .D(registers[3]), .Q(registers_7__ap[3]), .QN(), .SE(dftIn), + .SI(registers_4__ap[3]) + ); + SDFF_X1_LVT \registers_reg[14][3] ( + .CK(n_0_44), .D(registers[3]), .Q(registers_14__ap[3]), .QN(), .SE(dftIn), + .SI(registers_13__ap[3]) + ); + AOI22_X1_LVT i_1_0_748( + .A1(registers_7__ap[3]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[3]), + .ZN(n_1_0_712) + ); + SDFF_X1_LVT \registers_reg[27][3] ( + .CK(n_0_57), .D(registers[3]), .Q(registers_27__ap[3]), .QN(), .SE(dftIn), + .SI(registers_2__ap[3]) + ); + SDFF_X1_LVT \registers_reg[11][3] ( + .CK(n_0_41), .D(registers[3]), .Q(registers_11__ap[3]), .QN(), .SE(dftIn), + .SI(registers_14__ap[3]) + ); + AOI22_X1_LVT i_1_0_747( + .A1(registers_27__ap[3]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[3]), + .ZN(n_1_0_711) + ); + NAND4_X1_LVT i_1_0_746( + .A1(n_1_0_714), .A2(n_1_0_713), .A3(n_1_0_712), .A4(n_1_0_711), .ZN(n_1_0_710) + ); + NOR3_X1_LVT i_1_0_745( + .A1(n_1_0_720), .A2(n_1_0_715), .A3(n_1_0_710), .ZN(n_1_0_709) + ); + NAND4_X1_LVT i_1_0_744( + .A1(n_1_0_727), .A2(n_1_0_726), .A3(n_1_0_725), .A4(n_1_0_709), .ZN(RRs1[3]) + ); + AND2_X1_LVT i_0_0_2( + .A1(n_0_0_16), .A2(WRd[2]), .ZN(registers[2]) + ); + SDFF_X1_LVT \registers_reg[28][2] ( + .CK(n_0_58), .D(registers[2]), .Q(registers_28__ap[2]), .QN(), .SE(dftIn), + .SI(registers_27__ap[3]) + ); + SDFF_X1_LVT \registers_reg[4][2] ( + .CK(n_0_34), .D(registers[2]), .Q(registers_4__ap[2]), .QN(), .SE(dftIn), + .SI(registers_7__ap[3]) + ); + AOI22_X1_LVT i_1_0_740( + .A1(registers_28__ap[2]), .A2(n_1_0_1283), .B1(n_1_0_1278), .B2(registers_4__ap[2]), + .ZN(n_1_0_705) + ); + SDFF_X1_LVT \registers_reg[16][2] ( + .CK(n_0_46), .D(registers[2]), .Q(registers_16__ap[2]), .QN(), .SE(dftIn), + .SI(registers_11__ap[3]) + ); + SDFF_X1_LVT \registers_reg[31][2] ( + .CK(n_0_61), .D(registers[2]), .Q(registers_31__ap[2]), .QN(), .SE(dftIn), + .SI(registers_4__ap[2]) + ); + AOI22_X1_LVT i_1_0_743( + .A1(registers_16__ap[2]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[2]), + .ZN(n_1_0_708) + ); + SDFF_X1_LVT \registers_reg[6][2] ( + .CK(n_0_36), .D(registers[2]), .Q(registers_6__ap[2]), .QN(), .SE(dftIn), + .SI(registers_31__ap[2]) + ); + SDFF_X1_LVT \registers_reg[1][2] ( + .CK(n_0_0), .D(registers[2]), .Q(registers_1__ap[2]), .QN(), .SE(dftIn), + .SI(registers_19__ap[3]) + ); + AOI22_X1_LVT i_1_0_739( + .A1(registers_6__ap[2]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[2]), + .ZN(n_1_0_704) + ); + SDFF_X1_LVT \registers_reg[15][2] ( + .CK(n_0_45), .D(registers[2]), .Q(registers_15__ap[2]), .QN(), .SE(dftIn), + .SI(registers_16__ap[2]) + ); + SDFF_X1_LVT \registers_reg[27][2] ( + .CK(n_0_57), .D(registers[2]), .Q(registers_27__ap[2]), .QN(), .SE(dftIn), + .SI(registers_28__ap[2]) + ); + AOI22_X1_LVT i_1_0_742( + .A1(registers_15__ap[2]), .A2(n_1_0_1286), .B1(n_1_0_1279), .B2(registers_27__ap[2]), + .ZN(n_1_0_707) + ); + INV_X1_LVT i_1_0_741( + .A(n_1_0_707), .ZN(n_1_0_706) + ); + SDFF_X1_LVT \registers_reg[11][2] ( + .CK(n_0_41), .D(registers[2]), .Q(registers_11__ap[2]), .QN(), .SE(dftIn), + .SI(registers_15__ap[2]) + ); + SDFF_X1_LVT \registers_reg[5][2] ( + .CK(n_0_35), .D(registers[2]), .Q(registers_5__ap[2]), .QN(), .SE(dftIn), + .SI(registers_6__ap[2]) + ); + AOI221_X1_LVT i_1_0_738( + .A(n_1_0_706), .B1(n_1_0_1270), .B2(registers_11__ap[2]), .C1(registers_5__ap[2]), + .C2(n_1_0_1273), .ZN(n_1_0_703) + ); + SDFF_X1_LVT \registers_reg[10][2] ( + .CK(n_0_40), .D(registers[2]), .Q(registers_10__ap[2]), .QN(), .SE(dftIn), + .SI(registers_11__ap[2]) + ); + SDFF_X1_LVT \registers_reg[30][2] ( + .CK(n_0_60), .D(registers[2]), .Q(registers_30__ap[2]), .QN(), .SE(dftIn), + .SI(registers_27__ap[2]) + ); + SDFF_X1_LVT \registers_reg[8][2] ( + .CK(n_0_38), .D(registers[2]), .Q(registers_8__ap[2]), .QN(), .SE(dftIn), + .SI(registers_5__ap[2]) + ); + AOI222_X1_LVT i_1_0_737( + .A1(registers_10__ap[2]), .A2(n_1_0_1287), .B1(n_1_0_1272), .B2(registers_30__ap[2]), + .C1(n_1_0_1282), .C2(registers_8__ap[2]), .ZN(n_1_0_702) + ); + NAND4_X1_LVT i_1_0_736( + .A1(n_1_0_708), .A2(n_1_0_704), .A3(n_1_0_703), .A4(n_1_0_702), .ZN(n_1_0_701) + ); + SDFF_X1_LVT \registers_reg[9][2] ( + .CK(n_0_39), .D(registers[2]), .Q(registers_9__ap[2]), .QN(), .SE(dftIn), + .SI(registers_8__ap[2]) + ); + SDFF_X1_LVT \registers_reg[29][2] ( + .CK(n_0_59), .D(registers[2]), .Q(registers_29__ap[2]), .QN(), .SE(dftIn), + .SI(registers_30__ap[2]) + ); + AOI221_X1_LVT i_1_0_735( + .A(n_1_0_701), .B1(n_1_0_1291), .B2(registers_9__ap[2]), .C1(registers_29__ap[2]), + .C2(n_1_0_1276), .ZN(n_1_0_700) + ); + SDFF_X1_LVT \registers_reg[18][2] ( + .CK(n_0_48), .D(registers[2]), .Q(registers_18__ap[2]), .QN(), .SE(dftIn), + .SI(registers_1__ap[2]) + ); + SDFF_X1_LVT \registers_reg[26][2] ( + .CK(n_0_56), .D(registers[2]), .Q(registers_26__ap[2]), .QN(), .SE(dftIn), + .SI(registers_29__ap[2]) + ); + AOI22_X1_LVT i_1_0_734( + .A1(registers_18__ap[2]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[2]), + .ZN(n_1_0_699) + ); + SDFF_X1_LVT \registers_reg[24][2] ( + .CK(n_0_54), .D(registers[2]), .Q(registers_24__ap[2]), .QN(), .SE(dftIn), + .SI(registers_26__ap[2]) + ); + SDFF_X1_LVT \registers_reg[12][2] ( + .CK(n_0_42), .D(registers[2]), .Q(registers_12__ap[2]), .QN(), .SE(dftIn), + .SI(registers_10__ap[2]) + ); + AOI22_X1_LVT i_1_0_733( + .A1(registers_24__ap[2]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[2]), + .ZN(n_1_0_698) + ); + SDFF_X1_LVT \registers_reg[22][2] ( + .CK(n_0_52), .D(registers[2]), .Q(registers_22__ap[2]), .QN(), .SE(dftIn), + .SI(registers_18__ap[2]) + ); + SDFF_X1_LVT \registers_reg[21][2] ( + .CK(n_0_51), .D(registers[2]), .Q(registers_21__ap[2]), .QN(), .SE(dftIn), + .SI(registers_22__ap[2]) + ); + AOI22_X1_LVT i_1_0_732( + .A1(registers_22__ap[2]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[2]), + .ZN(n_1_0_697) + ); + NAND3_X1_LVT i_1_0_731( + .A1(n_1_0_699), .A2(n_1_0_698), .A3(n_1_0_697), .ZN(n_1_0_696) + ); + SDFF_X1_LVT \registers_reg[17][2] ( + .CK(n_0_47), .D(registers[2]), .Q(registers_17__ap[2]), .QN(), .SE(dftIn), + .SI(registers_21__ap[2]) + ); + SDFF_X1_LVT \registers_reg[20][2] ( + .CK(n_0_50), .D(registers[2]), .Q(registers_20__ap[2]), .QN(), .SE(dftIn), + .SI(registers_17__ap[2]) + ); + AOI221_X1_LVT i_1_0_730( + .A(n_1_0_696), .B1(n_1_0_1271), .B2(registers_17__ap[2]), .C1(registers_20__ap[2]), + .C2(n_1_0_1281), .ZN(n_1_0_695) + ); + SDFF_X1_LVT \registers_reg[13][2] ( + .CK(n_0_43), .D(registers[2]), .Q(registers_13__ap[2]), .QN(), .SE(dftIn), + .SI(registers_12__ap[2]) + ); + SDFF_X1_LVT \registers_reg[25][2] ( + .CK(n_0_55), .D(registers[2]), .Q(registers_25__ap[2]), .QN(), .SE(dftIn), + .SI(registers_24__ap[2]) + ); + AOI22_X1_LVT i_1_0_729( + .A1(registers_13__ap[2]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[2]), + .ZN(n_1_0_694) + ); + SDFF_X1_LVT \registers_reg[7][2] ( + .CK(n_0_37), .D(registers[2]), .Q(registers_7__ap[2]), .QN(), .SE(dftIn), + .SI(registers_9__ap[2]) + ); + SDFF_X1_LVT \registers_reg[14][2] ( + .CK(n_0_44), .D(registers[2]), .Q(registers_14__ap[2]), .QN(), .SE(dftIn), + .SI(registers_13__ap[2]) + ); + AOI22_X1_LVT i_1_0_728( + .A1(registers_7__ap[2]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[2]), + .ZN(n_1_0_693) + ); + SDFF_X1_LVT \registers_reg[19][2] ( + .CK(n_0_49), .D(registers[2]), .Q(registers_19__ap[2]), .QN(), .SE(dftIn), + .SI(registers_20__ap[2]) + ); + SDFF_X1_LVT \registers_reg[3][2] ( + .CK(n_0_33), .D(registers[2]), .Q(registers_3__ap[2]), .QN(), .SE(dftIn), + .SI(registers_7__ap[2]) + ); + AOI22_X1_LVT i_1_0_727( + .A1(registers_19__ap[2]), .A2(n_1_0_1295), .B1(n_1_0_1257), .B2(registers_3__ap[2]), + .ZN(n_1_0_692) + ); + NAND3_X1_LVT i_1_0_726( + .A1(n_1_0_694), .A2(n_1_0_693), .A3(n_1_0_692), .ZN(n_1_0_691) + ); + SDFF_X1_LVT \registers_reg[23][2] ( + .CK(n_0_53), .D(registers[2]), .Q(registers_23__ap[2]), .QN(), .SE(dftIn), + .SI(registers_19__ap[2]) + ); + SDFF_X1_LVT \registers_reg[2][2] ( + .CK(n_0_32), .D(registers[2]), .Q(registers_2__ap[2]), .QN(), .SE(dftIn), + .SI(registers_25__ap[2]) + ); + AOI221_X1_LVT i_1_0_725( + .A(n_1_0_691), .B1(n_1_0_1264), .B2(registers_23__ap[2]), .C1(registers_2__ap[2]), + .C2(n_1_0_1268), .ZN(n_1_0_690) + ); + NAND4_X1_LVT i_1_0_724( + .A1(n_1_0_705), .A2(n_1_0_700), .A3(n_1_0_695), .A4(n_1_0_690), .ZN(RRs1[2]) + ); + AND2_X1_LVT i_0_0_1( + .A1(n_0_0_16), .A2(WRd[1]), .ZN(registers[1]) + ); + SDFF_X1_LVT \registers_reg[13][1] ( + .CK(n_0_43), .D(registers[1]), .Q(registers_13__ap[1]), .QN(), .SE(dftIn), + .SI(registers_14__ap[2]) + ); + SDFF_X1_LVT \registers_reg[21][1] ( + .CK(n_0_51), .D(registers[1]), .Q(registers_21__ap[1]), .QN(), .SE(dftIn), + .SI(registers_23__ap[2]) + ); + AOI22_X1_LVT i_1_0_720( + .A1(registers_13__ap[1]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[1]), + .ZN(n_1_0_686) + ); + SDFF_X1_LVT \registers_reg[29][1] ( + .CK(n_0_59), .D(registers[1]), .Q(registers_29__ap[1]), .QN(), .SE(dftIn), + .SI(registers_2__ap[2]) + ); + SDFF_X1_LVT \registers_reg[23][1] ( + .CK(n_0_53), .D(registers[1]), .Q(registers_23__ap[1]), .QN(), .SE(dftIn), + .SI(registers_21__ap[1]) + ); + AOI22_X1_LVT i_1_0_723( + .A1(registers_29__ap[1]), .A2(n_1_0_1276), .B1(n_1_0_1264), .B2(registers_23__ap[1]), + .ZN(n_1_0_689) + ); + SDFF_X1_LVT \registers_reg[24][1] ( + .CK(n_0_54), .D(registers[1]), .Q(registers_24__ap[1]), .QN(), .SE(dftIn), + .SI(registers_29__ap[1]) + ); + SDFF_X1_LVT \registers_reg[20][1] ( + .CK(n_0_50), .D(registers[1]), .Q(registers_20__ap[1]), .QN(), .SE(dftIn), + .SI(registers_23__ap[1]) + ); + AOI22_X1_LVT i_1_0_719( + .A1(registers_24__ap[1]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[1]), + .ZN(n_1_0_685) + ); + SDFF_X1_LVT \registers_reg[7][1] ( + .CK(n_0_37), .D(registers[1]), .Q(registers_7__ap[1]), .QN(), .SE(dftIn), + .SI(registers_3__ap[2]) + ); + SDFF_X1_LVT \registers_reg[3][1] ( + .CK(n_0_33), .D(registers[1]), .Q(registers_3__ap[1]), .QN(), .SE(dftIn), + .SI(registers_7__ap[1]) + ); + AOI22_X1_LVT i_1_0_722( + .A1(registers_7__ap[1]), .A2(n_1_0_1263), .B1(n_1_0_1257), .B2(registers_3__ap[1]), + .ZN(n_1_0_688) + ); + INV_X1_LVT i_1_0_721( + .A(n_1_0_688), .ZN(n_1_0_687) + ); + SDFF_X1_LVT \registers_reg[31][1] ( + .CK(n_0_61), .D(registers[1]), .Q(registers_31__ap[1]), .QN(), .SE(dftIn), + .SI(registers_3__ap[1]) + ); + SDFF_X1_LVT \registers_reg[4][1] ( + .CK(n_0_34), .D(registers[1]), .Q(registers_4__ap[1]), .QN(), .SE(dftIn), + .SI(registers_31__ap[1]) + ); + AOI221_X1_LVT i_1_0_718( + .A(n_1_0_687), .B1(n_1_0_1266), .B2(registers_31__ap[1]), .C1(registers_4__ap[1]), + .C2(n_1_0_1278), .ZN(n_1_0_684) + ); + SDFF_X1_LVT \registers_reg[10][1] ( + .CK(n_0_40), .D(registers[1]), .Q(registers_10__ap[1]), .QN(), .SE(dftIn), + .SI(registers_13__ap[1]) + ); + SDFF_X1_LVT \registers_reg[26][1] ( + .CK(n_0_56), .D(registers[1]), .Q(registers_26__ap[1]), .QN(), .SE(dftIn), + .SI(registers_24__ap[1]) + ); + SDFF_X1_LVT \registers_reg[25][1] ( + .CK(n_0_55), .D(registers[1]), .Q(registers_25__ap[1]), .QN(), .SE(dftIn), + .SI(registers_26__ap[1]) + ); + AOI222_X1_LVT i_1_0_717( + .A1(registers_10__ap[1]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[1]), + .C1(registers_25__ap[1]), .C2(n_1_0_1269), .ZN(n_1_0_683) + ); + NAND4_X1_LVT i_1_0_716( + .A1(n_1_0_689), .A2(n_1_0_685), .A3(n_1_0_684), .A4(n_1_0_683), .ZN(n_1_0_682) + ); + SDFF_X1_LVT \registers_reg[8][1] ( + .CK(n_0_38), .D(registers[1]), .Q(registers_8__ap[1]), .QN(), .SE(dftIn), + .SI(registers_4__ap[1]) + ); + SDFF_X1_LVT \registers_reg[28][1] ( + .CK(n_0_58), .D(registers[1]), .Q(registers_28__ap[1]), .QN(), .SE(dftIn), + .SI(registers_25__ap[1]) + ); + AOI221_X1_LVT i_1_0_715( + .A(n_1_0_682), .B1(n_1_0_1282), .B2(registers_8__ap[1]), .C1(registers_28__ap[1]), + .C2(n_1_0_1283), .ZN(n_1_0_681) + ); + SDFF_X1_LVT \registers_reg[18][1] ( + .CK(n_0_48), .D(registers[1]), .Q(registers_18__ap[1]), .QN(), .SE(dftIn), + .SI(registers_20__ap[1]) + ); + SDFF_X1_LVT \registers_reg[30][1] ( + .CK(n_0_60), .D(registers[1]), .Q(registers_30__ap[1]), .QN(), .SE(dftIn), + .SI(registers_28__ap[1]) + ); + AOI22_X1_LVT i_1_0_714( + .A1(registers_18__ap[1]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[1]), + .ZN(n_1_0_680) + ); + SDFF_X1_LVT \registers_reg[17][1] ( + .CK(n_0_47), .D(registers[1]), .Q(registers_17__ap[1]), .QN(), .SE(dftIn), + .SI(registers_18__ap[1]) + ); + SDFF_X1_LVT \registers_reg[12][1] ( + .CK(n_0_42), .D(registers[1]), .Q(registers_12__ap[1]), .QN(), .SE(dftIn), + .SI(registers_10__ap[1]) + ); + AOI22_X1_LVT i_1_0_713( + .A1(registers_17__ap[1]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[1]), + .ZN(n_1_0_679) + ); + SDFF_X1_LVT \registers_reg[15][1] ( + .CK(n_0_45), .D(registers[1]), .Q(registers_15__ap[1]), .QN(), .SE(dftIn), + .SI(registers_12__ap[1]) + ); + SDFF_X1_LVT \registers_reg[5][1] ( + .CK(n_0_35), .D(registers[1]), .Q(registers_5__ap[1]), .QN(), .SE(dftIn), + .SI(registers_8__ap[1]) + ); + AOI22_X1_LVT i_1_0_712( + .A1(registers_15__ap[1]), .A2(n_1_0_1286), .B1(n_1_0_1273), .B2(registers_5__ap[1]), + .ZN(n_1_0_678) + ); + NAND3_X1_LVT i_1_0_711( + .A1(n_1_0_680), .A2(n_1_0_679), .A3(n_1_0_678), .ZN(n_1_0_677) + ); + SDFF_X1_LVT \registers_reg[22][1] ( + .CK(n_0_52), .D(registers[1]), .Q(registers_22__ap[1]), .QN(), .SE(dftIn), + .SI(registers_17__ap[1]) + ); + SDFF_X1_LVT \registers_reg[16][1] ( + .CK(n_0_46), .D(registers[1]), .Q(registers_16__ap[1]), .QN(), .SE(dftIn), + .SI(registers_15__ap[1]) + ); + AOI221_X1_LVT i_1_0_710( + .A(n_1_0_677), .B1(n_1_0_1294), .B2(registers_22__ap[1]), .C1(registers_16__ap[1]), + .C2(n_1_0_1267), .ZN(n_1_0_676) + ); + SDFF_X1_LVT \registers_reg[9][1] ( + .CK(n_0_39), .D(registers[1]), .Q(registers_9__ap[1]), .QN(), .SE(dftIn), + .SI(registers_5__ap[1]) + ); + SDFF_X1_LVT \registers_reg[1][1] ( + .CK(n_0_0), .D(registers[1]), .Q(registers_1__ap[1]), .QN(), .SE(dftIn), + .SI(registers_22__ap[1]) + ); + AOI22_X1_LVT i_1_0_709( + .A1(registers_9__ap[1]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[1]), + .ZN(n_1_0_675) + ); + SDFF_X1_LVT \registers_reg[6][1] ( + .CK(n_0_36), .D(registers[1]), .Q(registers_6__ap[1]), .QN(), .SE(dftIn), + .SI(registers_9__ap[1]) + ); + SDFF_X1_LVT \registers_reg[14][1] ( + .CK(n_0_44), .D(registers[1]), .Q(registers_14__ap[1]), .QN(), .SE(dftIn), + .SI(registers_16__ap[1]) + ); + AOI22_X1_LVT i_1_0_708( + .A1(registers_6__ap[1]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[1]), + .ZN(n_1_0_674) + ); + SDFF_X1_LVT \registers_reg[19][1] ( + .CK(n_0_49), .D(registers[1]), .Q(registers_19__ap[1]), .QN(), .SE(dftIn), + .SI(registers_1__ap[1]) + ); + SDFF_X1_LVT \registers_reg[2][1] ( + .CK(n_0_32), .D(registers[1]), .Q(registers_2__ap[1]), .QN(), .SE(dftIn), + .SI(registers_30__ap[1]) + ); + AOI22_X1_LVT i_1_0_707( + .A1(registers_19__ap[1]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[1]), + .ZN(n_1_0_673) + ); + NAND3_X1_LVT i_1_0_706( + .A1(n_1_0_675), .A2(n_1_0_674), .A3(n_1_0_673), .ZN(n_1_0_672) + ); + SDFF_X1_LVT \registers_reg[11][1] ( + .CK(n_0_41), .D(registers[1]), .Q(registers_11__ap[1]), .QN(), .SE(dftIn), + .SI(registers_14__ap[1]) + ); + SDFF_X1_LVT \registers_reg[27][1] ( + .CK(n_0_57), .D(registers[1]), .Q(registers_27__ap[1]), .QN(), .SE(dftIn), + .SI(registers_2__ap[1]) + ); + AOI221_X1_LVT i_1_0_705( + .A(n_1_0_672), .B1(n_1_0_1270), .B2(registers_11__ap[1]), .C1(registers_27__ap[1]), + .C2(n_1_0_1279), .ZN(n_1_0_671) + ); + NAND4_X1_LVT i_1_0_704( + .A1(n_1_0_686), .A2(n_1_0_681), .A3(n_1_0_676), .A4(n_1_0_671), .ZN(RRs1[1]) + ); + AND2_X1_LVT i_0_0_0( + .A1(n_0_0_16), .A2(WRd[0]), .ZN(registers[0]) + ); + SDFF_X1_LVT \registers_reg[13][0] ( + .CK(n_0_43), .D(registers[0]), .Q(registers_13__ap[0]), .QN(), .SE(dftIn), + .SI(registers_11__ap[1]) + ); + SDFF_X1_LVT \registers_reg[21][0] ( + .CK(n_0_51), .D(registers[0]), .Q(registers_21__ap[0]), .QN(), .SE(dftIn), + .SI(registers_19__ap[1]) + ); + AOI22_X1_LVT i_1_0_703( + .A1(registers_13__ap[0]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[0]), + .ZN(n_1_0_670) + ); + SDFF_X1_LVT \registers_reg[10][0] ( + .CK(n_0_40), .D(registers[0]), .Q(registers_10__ap[0]), .QN(), .SE(dftIn), + .SI(registers_13__ap[0]) + ); + SDFF_X1_LVT \registers_reg[26][0] ( + .CK(n_0_56), .D(registers[0]), .Q(registers_26__ap[0]), .QN(), .SE(dftIn), + .SI(registers_27__ap[1]) + ); + SDFF_X1_LVT \registers_reg[25][0] ( + .CK(n_0_55), .D(registers[0]), .Q(registers_25__ap[0]), .QN(), .SE(dftIn), + .SI(registers_26__ap[0]) + ); + AOI222_X1_LVT i_1_0_702( + .A1(registers_10__ap[0]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[0]), + .C1(registers_25__ap[0]), .C2(n_1_0_1269), .ZN(n_1_0_669) + ); + SDFF_X1_LVT \registers_reg[28][0] ( + .CK(n_0_58), .D(registers[0]), .Q(registers_28__ap[0]), .QN(), .SE(dftIn), + .SI(registers_25__ap[0]) + ); + SDFF_X1_LVT \registers_reg[8][0] ( + .CK(n_0_38), .D(registers[0]), .Q(registers_8__ap[0]), .QN(), .SE(dftIn), + .SI(registers_6__ap[1]) + ); + AOI22_X1_LVT i_1_0_701( + .A1(registers_28__ap[0]), .A2(n_1_0_1283), .B1(n_1_0_1282), .B2(registers_8__ap[0]), + .ZN(n_1_0_668) + ); + SDFF_X1_LVT \registers_reg[24][0] ( + .CK(n_0_54), .D(registers[0]), .Q(registers_24__ap[0]), .QN(), .SE(dftIn), + .SI(registers_28__ap[0]) + ); + SDFF_X1_LVT \registers_reg[20][0] ( + .CK(n_0_50), .D(registers[0]), .Q(registers_20__ap[0]), .QN(), .SE(dftIn), + .SI(registers_21__ap[0]) + ); + AOI22_X1_LVT i_1_0_700( + .A1(registers_24__ap[0]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[0]), + .ZN(n_1_0_667) + ); + SDFF_X1_LVT \registers_reg[7][0] ( + .CK(n_0_37), .D(registers[0]), .Q(registers_7__ap[0]), .QN(), .SE(dftIn), + .SI(registers_8__ap[0]) + ); + SDFF_X1_LVT \registers_reg[3][0] ( + .CK(n_0_33), .D(registers[0]), .Q(registers_3__ap[0]), .QN(), .SE(dftIn), + .SI(registers_7__ap[0]) + ); + AOI22_X1_LVT i_1_0_699( + .A1(registers_7__ap[0]), .A2(n_1_0_1263), .B1(n_1_0_1257), .B2(registers_3__ap[0]), + .ZN(n_1_0_666) + ); + SDFF_X1_LVT \registers_reg[17][0] ( + .CK(n_0_47), .D(registers[0]), .Q(registers_17__ap[0]), .QN(), .SE(dftIn), + .SI(registers_20__ap[0]) + ); + SDFF_X1_LVT \registers_reg[31][0] ( + .CK(n_0_61), .D(registers[0]), .Q(registers_31__ap[0]), .QN(), .SE(dftIn), + .SI(registers_3__ap[0]) + ); + AOI22_X1_LVT i_1_0_698( + .A1(registers_17__ap[0]), .A2(n_1_0_1271), .B1(n_1_0_1266), .B2(registers_31__ap[0]), + .ZN(n_1_0_665) + ); + SDFF_X1_LVT \registers_reg[29][0] ( + .CK(n_0_59), .D(registers[0]), .Q(registers_29__ap[0]), .QN(), .SE(dftIn), + .SI(registers_24__ap[0]) + ); + SDFF_X1_LVT \registers_reg[23][0] ( + .CK(n_0_53), .D(registers[0]), .Q(registers_23__ap[0]), .QN(), .SE(dftIn), + .SI(registers_17__ap[0]) + ); + AOI22_X1_LVT i_1_0_697( + .A1(registers_29__ap[0]), .A2(n_1_0_1276), .B1(n_1_0_1264), .B2(registers_23__ap[0]), + .ZN(n_1_0_664) + ); + NAND4_X1_LVT i_1_0_696( + .A1(n_1_0_667), .A2(n_1_0_666), .A3(n_1_0_665), .A4(n_1_0_664), .ZN(n_1_0_663) + ); + SDFF_X1_LVT \registers_reg[18][0] ( + .CK(n_0_48), .D(registers[0]), .Q(registers_18__ap[0]), .QN(), .SE(dftIn), + .SI(registers_23__ap[0]) + ); + SDFF_X1_LVT \registers_reg[30][0] ( + .CK(n_0_60), .D(registers[0]), .Q(registers_30__ap[0]), .QN(), .SE(dftIn), + .SI(registers_29__ap[0]) + ); + AOI22_X1_LVT i_1_0_695( + .A1(registers_18__ap[0]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[0]), + .ZN(n_1_0_662) + ); + SDFF_X1_LVT \registers_reg[4][0] ( + .CK(n_0_34), .D(registers[0]), .Q(registers_4__ap[0]), .QN(), .SE(dftIn), + .SI(registers_31__ap[0]) + ); + SDFF_X1_LVT \registers_reg[12][0] ( + .CK(n_0_42), .D(registers[0]), .Q(registers_12__ap[0]), .QN(), .SE(dftIn), + .SI(registers_10__ap[0]) + ); + AOI22_X1_LVT i_1_0_694( + .A1(registers_4__ap[0]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[0]), + .ZN(n_1_0_661) + ); + SDFF_X1_LVT \registers_reg[15][0] ( + .CK(n_0_45), .D(registers[0]), .Q(registers_15__ap[0]), .QN(), .SE(dftIn), + .SI(registers_12__ap[0]) + ); + SDFF_X1_LVT \registers_reg[16][0] ( + .CK(n_0_46), .D(registers[0]), .Q(registers_16__ap[0]), .QN(), .SE(dftIn), + .SI(registers_15__ap[0]) + ); + AOI22_X1_LVT i_1_0_693( + .A1(registers_15__ap[0]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[0]), + .ZN(n_1_0_660) + ); + SDFF_X1_LVT \registers_reg[22][0] ( + .CK(n_0_52), .D(registers[0]), .Q(registers_22__ap[0]), .QN(), .SE(dftIn), + .SI(registers_18__ap[0]) + ); + SDFF_X1_LVT \registers_reg[5][0] ( + .CK(n_0_35), .D(registers[0]), .Q(registers_5__ap[0]), .QN(), .SE(dftIn), + .SI(registers_4__ap[0]) + ); + AOI22_X1_LVT i_1_0_692( + .A1(registers_22__ap[0]), .A2(n_1_0_1294), .B1(n_1_0_1273), .B2(registers_5__ap[0]), + .ZN(n_1_0_659) + ); + NAND4_X1_LVT i_1_0_691( + .A1(n_1_0_662), .A2(n_1_0_661), .A3(n_1_0_660), .A4(n_1_0_659), .ZN(n_1_0_658) + ); + SDFF_X1_LVT \registers_reg[19][0] ( + .CK(n_0_49), .D(registers[0]), .Q(registers_19__ap[0]), .QN(), .SE(dftIn), + .SI(registers_22__ap[0]) + ); + SDFF_X1_LVT \registers_reg[2][0] ( + .CK(n_0_32), .D(registers[0]), .Q(registers_2__ap[0]), .QN(), .SE(dftIn), + .SI(registers_30__ap[0]) + ); + AOI22_X1_LVT i_1_0_690( + .A1(registers_19__ap[0]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[0]), + .ZN(n_1_0_657) + ); + SDFF_X1_LVT \registers_reg[9][0] ( + .CK(n_0_39), .D(registers[0]), .Q(registers_9__ap[0]), .QN(), .SE(dftIn), + .SI(registers_5__ap[0]) + ); + SDFF_X1_LVT \registers_reg[1][0] ( + .CK(n_0_0), .D(registers[0]), .Q(registers_1__ap[0]), .QN(), .SE(dftIn), + .SI(registers_19__ap[0]) + ); + AOI22_X1_LVT i_1_0_689( + .A1(registers_9__ap[0]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[0]), + .ZN(n_1_0_656) + ); + SDFF_X1_LVT \registers_reg[6][0] ( + .CK(n_0_36), .D(registers[0]), .Q(registers_6__ap[0]), .QN(), .SE(dftIn), + .SI(registers_9__ap[0]) + ); + SDFF_X1_LVT \registers_reg[14][0] ( + .CK(n_0_44), .D(registers[0]), .Q(registers_14__ap[0]), .QN(), .SE(dftIn), + .SI(registers_16__ap[0]) + ); + AOI22_X1_LVT i_1_0_688( + .A1(registers_6__ap[0]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[0]), + .ZN(n_1_0_655) + ); + SDFF_X1_LVT \registers_reg[27][0] ( + .CK(n_0_57), .D(registers[0]), .Q(registers_27__ap[0]), .QN(), .SE(dftIn), + .SI(registers_2__ap[0]) + ); + SDFF_X1_LVT \registers_reg[11][0] ( + .CK(n_0_41), .D(registers[0]), .Q(registers_11__ap[0]), .QN(), .SE(dftIn), + .SI(registers_14__ap[0]) + ); + AOI22_X1_LVT i_1_0_687( + .A1(registers_27__ap[0]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[0]), + .ZN(n_1_0_654) + ); + NAND4_X1_LVT i_1_0_686( + .A1(n_1_0_657), .A2(n_1_0_656), .A3(n_1_0_655), .A4(n_1_0_654), .ZN(n_1_0_653) + ); + NOR3_X1_LVT i_1_0_685( + .A1(n_1_0_663), .A2(n_1_0_658), .A3(n_1_0_653), .ZN(n_1_0_652) + ); + NAND4_X1_LVT i_1_0_684( + .A1(n_1_0_670), .A2(n_1_0_669), .A3(n_1_0_668), .A4(n_1_0_652), .ZN(RRs1[0]) + ); + INV_X1_LVT i_1_0_1366( + .A(Rs2[1]), .ZN(n_1_0_1302) + ); + NAND3_X1_LVT i_1_0_683( + .A1(n_1_0_1302), .A2(Rs2[4]), .A3(Rs2[2]), .ZN(n_1_0_651) + ); + INV_X1_LVT i_1_0_1369( + .A(Rs2[3]), .ZN(n_1_0_1305) + ); + OR2_X1_LVT i_1_0_673( + .A1(n_1_0_1305), .A2(Rs2[0]), .ZN(n_1_0_641) + ); + NOR2_X1_LVT i_1_0_666( + .A1(n_1_0_651), .A2(n_1_0_641), .ZN(n_1_0_634) + ); + NAND2_X1_LVT i_1_0_677( + .A1(n_1_0_1305), .A2(Rs2[0]), .ZN(n_1_0_645) + ); + INV_X1_LVT i_1_0_1368( + .A(Rs2[2]), .ZN(n_1_0_1304) + ); + NAND3_X1_LVT i_1_0_662( + .A1(n_1_0_1304), .A2(n_1_0_1302), .A3(Rs2[4]), .ZN(n_1_0_630) + ); + NOR2_X1_LVT i_1_0_661( + .A1(n_1_0_645), .A2(n_1_0_630), .ZN(n_1_0_629) + ); + AOI22_X1_LVT i_1_0_641( + .A1(registers_28__ap[31]), .A2(n_1_0_634), .B1(n_1_0_629), .B2(registers_17__ap[31]), + .ZN(n_1_0_609) + ); + NAND3_X1_LVT i_1_0_680( + .A1(n_1_0_1304), .A2(Rs2[4]), .A3(Rs2[1]), .ZN(n_1_0_648) + ); + NOR2_X1_LVT i_1_0_672( + .A1(n_1_0_648), .A2(n_1_0_641), .ZN(n_1_0_640) + ); + INV_X1_LVT i_1_0_1367( + .A(Rs2[4]), .ZN(n_1_0_1303) + ); + NAND3_X1_LVT i_1_0_657( + .A1(n_1_0_1304), .A2(n_1_0_1303), .A3(Rs2[1]), .ZN(n_1_0_625) + ); + NOR2_X1_LVT i_1_0_656( + .A1(n_1_0_641), .A2(n_1_0_625), .ZN(n_1_0_624) + ); + NOR4_X1_LVT i_1_0_658( + .A1(n_1_0_641), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), .ZN(n_1_0_626) + ); + AOI222_X1_LVT i_1_0_640( + .A1(registers_26__ap[31]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[31]), + .C1(n_1_0_626), .C2(registers_8__ap[31]), .ZN(n_1_0_608) + ); + NAND2_X1_LVT i_1_0_682( + .A1(Rs2[0]), .A2(Rs2[3]), .ZN(n_1_0_650) + ); + NOR2_X1_LVT i_1_0_681( + .A1(n_1_0_651), .A2(n_1_0_650), .ZN(n_1_0_649) + ); + NOR4_X1_LVT i_1_0_649( + .A1(n_1_0_650), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), .ZN(n_1_0_617) + ); + AOI22_X1_LVT i_1_0_639( + .A1(registers_29__ap[31]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[31]), + .ZN(n_1_0_607) + ); + NOR4_X1_LVT i_1_0_676( + .A1(n_1_0_645), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), .ZN(n_1_0_644) + ); + OR2_X1_LVT i_1_0_679( + .A1(Rs2[0]), .A2(Rs2[3]), .ZN(n_1_0_647) + ); + NAND3_X1_LVT i_1_0_660( + .A1(n_1_0_1303), .A2(Rs2[1]), .A3(Rs2[2]), .ZN(n_1_0_628) + ); + NOR2_X1_LVT i_1_0_648( + .A1(n_1_0_647), .A2(n_1_0_628), .ZN(n_1_0_616) + ); + AOI22_X1_LVT i_1_0_638( + .A1(registers_1__ap[31]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[31]), + .ZN(n_1_0_606) + ); + NOR2_X1_LVT i_1_0_655( + .A1(n_1_0_645), .A2(n_1_0_628), .ZN(n_1_0_623) + ); + NAND3_X1_LVT i_1_0_675( + .A1(Rs2[2]), .A2(Rs2[4]), .A3(Rs2[1]), .ZN(n_1_0_643) + ); + NOR2_X1_LVT i_1_0_647( + .A1(n_1_0_645), .A2(n_1_0_643), .ZN(n_1_0_615) + ); + AOI22_X1_LVT i_1_0_637( + .A1(registers_7__ap[31]), .A2(n_1_0_623), .B1(n_1_0_615), .B2(registers_23__ap[31]), + .ZN(n_1_0_605) + ); + NOR2_X1_LVT i_1_0_665( + .A1(n_1_0_648), .A2(n_1_0_645), .ZN(n_1_0_633) + ); + NOR2_X1_LVT i_1_0_646( + .A1(n_1_0_647), .A2(n_1_0_630), .ZN(n_1_0_614) + ); + AOI22_X1_LVT i_1_0_636( + .A1(registers_19__ap[31]), .A2(n_1_0_633), .B1(n_1_0_614), .B2(registers_16__ap[31]), + .ZN(n_1_0_604) + ); + NOR2_X1_LVT i_1_0_669( + .A1(n_1_0_650), .A2(n_1_0_643), .ZN(n_1_0_637) + ); + NAND3_X1_LVT i_1_0_671( + .A1(n_1_0_1303), .A2(n_1_0_1302), .A3(Rs2[2]), .ZN(n_1_0_639) + ); + NOR2_X1_LVT i_1_0_667( + .A1(n_1_0_645), .A2(n_1_0_639), .ZN(n_1_0_635) + ); + AOI22_X1_LVT i_1_0_635( + .A1(registers_31__ap[31]), .A2(n_1_0_637), .B1(n_1_0_635), .B2(registers_5__ap[31]), + .ZN(n_1_0_603) + ); + NAND4_X1_LVT i_1_0_634( + .A1(n_1_0_606), .A2(n_1_0_605), .A3(n_1_0_604), .A4(n_1_0_603), .ZN(n_1_0_602) + ); + NOR2_X1_LVT i_1_0_678( + .A1(n_1_0_648), .A2(n_1_0_647), .ZN(n_1_0_646) + ); + NOR2_X1_LVT i_1_0_654( + .A1(n_1_0_643), .A2(n_1_0_641), .ZN(n_1_0_622) + ); + AOI22_X1_LVT i_1_0_633( + .A1(registers_18__ap[31]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[31]), + .ZN(n_1_0_601) + ); + NOR2_X1_LVT i_1_0_670( + .A1(n_1_0_647), .A2(n_1_0_639), .ZN(n_1_0_638) + ); + NOR2_X1_LVT i_1_0_645( + .A1(n_1_0_651), .A2(n_1_0_647), .ZN(n_1_0_613) + ); + AOI22_X1_LVT i_1_0_632( + .A1(registers_4__ap[31]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[31]), + .ZN(n_1_0_600) + ); + NOR2_X1_LVT i_1_0_674( + .A1(n_1_0_647), .A2(n_1_0_643), .ZN(n_1_0_642) + ); + NOR2_X1_LVT i_1_0_644( + .A1(n_1_0_651), .A2(n_1_0_645), .ZN(n_1_0_612) + ); + AOI22_X1_LVT i_1_0_631( + .A1(registers_22__ap[31]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[31]), + .ZN(n_1_0_599) + ); + NOR2_X1_LVT i_1_0_664( + .A1(n_1_0_641), .A2(n_1_0_639), .ZN(n_1_0_632) + ); + NOR2_X1_LVT i_1_0_653( + .A1(n_1_0_641), .A2(n_1_0_630), .ZN(n_1_0_621) + ); + AOI22_X1_LVT i_1_0_630( + .A1(registers_12__ap[31]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[31]), + .ZN(n_1_0_598) + ); + NAND4_X1_LVT i_1_0_629( + .A1(n_1_0_601), .A2(n_1_0_600), .A3(n_1_0_599), .A4(n_1_0_598), .ZN(n_1_0_597) + ); + NOR2_X1_LVT i_1_0_663( + .A1(n_1_0_650), .A2(n_1_0_639), .ZN(n_1_0_631) + ); + NOR2_X1_LVT i_1_0_652( + .A1(n_1_0_650), .A2(n_1_0_630), .ZN(n_1_0_620) + ); + AOI22_X1_LVT i_1_0_628( + .A1(registers_13__ap[31]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[31]), + .ZN(n_1_0_596) + ); + NOR2_X1_LVT i_1_0_659( + .A1(n_1_0_650), .A2(n_1_0_628), .ZN(n_1_0_627) + ); + NOR2_X1_LVT i_1_0_651( + .A1(n_1_0_641), .A2(n_1_0_628), .ZN(n_1_0_619) + ); + AOI22_X1_LVT i_1_0_627( + .A1(registers_15__ap[31]), .A2(n_1_0_627), .B1(n_1_0_619), .B2(registers_14__ap[31]), + .ZN(n_1_0_595) + ); + NOR2_X1_LVT i_1_0_668( + .A1(n_1_0_650), .A2(n_1_0_648), .ZN(n_1_0_636) + ); + NOR2_X1_LVT i_1_0_643( + .A1(n_1_0_650), .A2(n_1_0_625), .ZN(n_1_0_611) + ); + AOI22_X1_LVT i_1_0_626( + .A1(registers_27__ap[31]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[31]), + .ZN(n_1_0_594) + ); + NOR2_X1_LVT i_1_0_650( + .A1(n_1_0_647), .A2(n_1_0_625), .ZN(n_1_0_618) + ); + NOR2_X1_LVT i_1_0_642( + .A1(n_1_0_645), .A2(n_1_0_625), .ZN(n_1_0_610) + ); + AOI22_X1_LVT i_1_0_625( + .A1(registers_2__ap[31]), .A2(n_1_0_618), .B1(n_1_0_610), .B2(registers_3__ap[31]), + .ZN(n_1_0_593) + ); + NAND4_X1_LVT i_1_0_624( + .A1(n_1_0_596), .A2(n_1_0_595), .A3(n_1_0_594), .A4(n_1_0_593), .ZN(n_1_0_592) + ); + NOR3_X1_LVT i_1_0_623( + .A1(n_1_0_602), .A2(n_1_0_597), .A3(n_1_0_592), .ZN(n_1_0_591) + ); + NAND4_X1_LVT i_1_0_622( + .A1(n_1_0_609), .A2(n_1_0_608), .A3(n_1_0_607), .A4(n_1_0_591), .ZN(RRs2[31]) + ); + AOI22_X1_LVT i_1_0_620( + .A1(registers_29__ap[30]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[30]), + .ZN(n_1_0_589) + ); + AOI22_X1_LVT i_1_0_621( + .A1(registers_7__ap[30]), .A2(n_1_0_623), .B1(n_1_0_615), .B2(registers_23__ap[30]), + .ZN(n_1_0_590) + ); + AOI22_X1_LVT i_1_0_619( + .A1(registers_1__ap[30]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[30]), + .ZN(n_1_0_588) + ); + AOI22_X1_LVT i_1_0_618( + .A1(registers_5__ap[30]), .A2(n_1_0_635), .B1(n_1_0_633), .B2(registers_19__ap[30]), + .ZN(n_1_0_587) + ); + NAND3_X1_LVT i_1_0_617( + .A1(n_1_0_590), .A2(n_1_0_588), .A3(n_1_0_587), .ZN(n_1_0_586) + ); + AOI221_X1_LVT i_1_0_616( + .A(n_1_0_586), .B1(n_1_0_637), .B2(registers_31__ap[30]), .C1(registers_16__ap[30]), + .C2(n_1_0_614), .ZN(n_1_0_585) + ); + AOI222_X1_LVT i_1_0_615( + .A1(registers_26__ap[30]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[30]), + .C1(n_1_0_626), .C2(registers_8__ap[30]), .ZN(n_1_0_584) + ); + NAND3_X1_LVT i_1_0_614( + .A1(n_1_0_589), .A2(n_1_0_585), .A3(n_1_0_584), .ZN(n_1_0_583) + ); + AOI221_X1_LVT i_1_0_613( + .A(n_1_0_583), .B1(n_1_0_629), .B2(registers_17__ap[30]), .C1(registers_28__ap[30]), + .C2(n_1_0_634), .ZN(n_1_0_582) + ); + AOI22_X1_LVT i_1_0_612( + .A1(registers_18__ap[30]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[30]), + .ZN(n_1_0_581) + ); + AOI22_X1_LVT i_1_0_611( + .A1(registers_4__ap[30]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[30]), + .ZN(n_1_0_580) + ); + AOI22_X1_LVT i_1_0_610( + .A1(registers_22__ap[30]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[30]), + .ZN(n_1_0_579) + ); + NAND3_X1_LVT i_1_0_609( + .A1(n_1_0_581), .A2(n_1_0_580), .A3(n_1_0_579), .ZN(n_1_0_578) + ); + AOI221_X1_LVT i_1_0_608( + .A(n_1_0_578), .B1(n_1_0_621), .B2(registers_24__ap[30]), .C1(registers_12__ap[30]), + .C2(n_1_0_632), .ZN(n_1_0_577) + ); + AOI22_X1_LVT i_1_0_607( + .A1(registers_13__ap[30]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[30]), + .ZN(n_1_0_576) + ); + AOI22_X1_LVT i_1_0_606( + .A1(registers_15__ap[30]), .A2(n_1_0_627), .B1(n_1_0_619), .B2(registers_14__ap[30]), + .ZN(n_1_0_575) + ); + AOI22_X1_LVT i_1_0_605( + .A1(registers_27__ap[30]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[30]), + .ZN(n_1_0_574) + ); + NAND3_X1_LVT i_1_0_604( + .A1(n_1_0_576), .A2(n_1_0_575), .A3(n_1_0_574), .ZN(n_1_0_573) + ); + AOI221_X1_LVT i_1_0_603( + .A(n_1_0_573), .B1(n_1_0_610), .B2(registers_3__ap[30]), .C1(registers_2__ap[30]), + .C2(n_1_0_618), .ZN(n_1_0_572) + ); + NAND3_X1_LVT i_1_0_602( + .A1(n_1_0_582), .A2(n_1_0_577), .A3(n_1_0_572), .ZN(RRs2[30]) + ); + AOI22_X1_LVT i_1_0_600( + .A1(registers_28__ap[29]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[29]), + .ZN(n_1_0_570) + ); + AOI22_X1_LVT i_1_0_601( + .A1(registers_31__ap[29]), .A2(n_1_0_637), .B1(n_1_0_627), .B2(registers_15__ap[29]), + .ZN(n_1_0_571) + ); + AOI22_X1_LVT i_1_0_599( + .A1(registers_24__ap[29]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[29]), + .ZN(n_1_0_569) + ); + AOI22_X1_LVT i_1_0_598( + .A1(registers_19__ap[29]), .A2(n_1_0_633), .B1(n_1_0_629), .B2(registers_17__ap[29]), + .ZN(n_1_0_568) + ); + NAND3_X1_LVT i_1_0_597( + .A1(n_1_0_571), .A2(n_1_0_569), .A3(n_1_0_568), .ZN(n_1_0_567) + ); + AOI221_X1_LVT i_1_0_596( + .A(n_1_0_567), .B1(n_1_0_615), .B2(registers_23__ap[29]), .C1(registers_29__ap[29]), + .C2(n_1_0_649), .ZN(n_1_0_566) + ); + AOI222_X1_LVT i_1_0_595( + .A1(registers_26__ap[29]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[29]), + .C1(n_1_0_620), .C2(registers_25__ap[29]), .ZN(n_1_0_565) + ); + NAND3_X1_LVT i_1_0_594( + .A1(n_1_0_570), .A2(n_1_0_566), .A3(n_1_0_565), .ZN(n_1_0_564) + ); + AOI221_X1_LVT i_1_0_593( + .A(n_1_0_564), .B1(n_1_0_612), .B2(registers_21__ap[29]), .C1(registers_13__ap[29]), + .C2(n_1_0_631), .ZN(n_1_0_563) + ); + AOI22_X1_LVT i_1_0_592( + .A1(registers_18__ap[29]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[29]), + .ZN(n_1_0_562) + ); + AOI22_X1_LVT i_1_0_591( + .A1(registers_4__ap[29]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[29]), + .ZN(n_1_0_561) + ); + AOI22_X1_LVT i_1_0_590( + .A1(registers_7__ap[29]), .A2(n_1_0_623), .B1(n_1_0_614), .B2(registers_16__ap[29]), + .ZN(n_1_0_560) + ); + NAND3_X1_LVT i_1_0_589( + .A1(n_1_0_562), .A2(n_1_0_561), .A3(n_1_0_560), .ZN(n_1_0_559) + ); + AOI221_X1_LVT i_1_0_588( + .A(n_1_0_559), .B1(n_1_0_642), .B2(registers_22__ap[29]), .C1(registers_5__ap[29]), + .C2(n_1_0_635), .ZN(n_1_0_558) + ); + AOI22_X1_LVT i_1_0_587( + .A1(registers_1__ap[29]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[29]), + .ZN(n_1_0_557) + ); + AOI22_X1_LVT i_1_0_586( + .A1(registers_14__ap[29]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[29]), + .ZN(n_1_0_556) + ); + AOI22_X1_LVT i_1_0_585( + .A1(registers_27__ap[29]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[29]), + .ZN(n_1_0_555) + ); + NAND3_X1_LVT i_1_0_584( + .A1(n_1_0_557), .A2(n_1_0_556), .A3(n_1_0_555), .ZN(n_1_0_554) + ); + AOI221_X1_LVT i_1_0_583( + .A(n_1_0_554), .B1(n_1_0_610), .B2(registers_3__ap[29]), .C1(registers_2__ap[29]), + .C2(n_1_0_618), .ZN(n_1_0_553) + ); + NAND3_X1_LVT i_1_0_582( + .A1(n_1_0_563), .A2(n_1_0_558), .A3(n_1_0_553), .ZN(RRs2[29]) + ); + AOI22_X1_LVT i_1_0_581( + .A1(registers_5__ap[28]), .A2(n_1_0_635), .B1(n_1_0_634), .B2(registers_28__ap[28]), + .ZN(n_1_0_552) + ); + AOI222_X1_LVT i_1_0_580( + .A1(registers_26__ap[28]), .A2(n_1_0_640), .B1(n_1_0_633), .B2(registers_19__ap[28]), + .C1(n_1_0_626), .C2(registers_8__ap[28]), .ZN(n_1_0_551) + ); + AOI22_X1_LVT i_1_0_579( + .A1(registers_2__ap[28]), .A2(n_1_0_618), .B1(n_1_0_617), .B2(registers_9__ap[28]), + .ZN(n_1_0_550) + ); + AOI22_X1_LVT i_1_0_578( + .A1(registers_7__ap[28]), .A2(n_1_0_623), .B1(n_1_0_612), .B2(registers_21__ap[28]), + .ZN(n_1_0_549) + ); + AOI22_X1_LVT i_1_0_577( + .A1(registers_16__ap[28]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[28]), + .ZN(n_1_0_548) + ); + AOI22_X1_LVT i_1_0_576( + .A1(registers_31__ap[28]), .A2(n_1_0_637), .B1(n_1_0_619), .B2(registers_14__ap[28]), + .ZN(n_1_0_547) + ); + AOI22_X1_LVT i_1_0_575( + .A1(registers_15__ap[28]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[28]), + .ZN(n_1_0_546) + ); + NAND4_X1_LVT i_1_0_574( + .A1(n_1_0_549), .A2(n_1_0_548), .A3(n_1_0_547), .A4(n_1_0_546), .ZN(n_1_0_545) + ); + AOI22_X1_LVT i_1_0_573( + .A1(registers_22__ap[28]), .A2(n_1_0_642), .B1(n_1_0_622), .B2(registers_30__ap[28]), + .ZN(n_1_0_544) + ); + AOI22_X1_LVT i_1_0_572( + .A1(registers_4__ap[28]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[28]), + .ZN(n_1_0_543) + ); + AOI22_X1_LVT i_1_0_571( + .A1(registers_29__ap[28]), .A2(n_1_0_649), .B1(n_1_0_644), .B2(registers_1__ap[28]), + .ZN(n_1_0_542) + ); + AOI22_X1_LVT i_1_0_570( + .A1(registers_12__ap[28]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[28]), + .ZN(n_1_0_541) + ); + NAND4_X1_LVT i_1_0_569( + .A1(n_1_0_544), .A2(n_1_0_543), .A3(n_1_0_542), .A4(n_1_0_541), .ZN(n_1_0_540) + ); + AOI22_X1_LVT i_1_0_568( + .A1(registers_13__ap[28]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[28]), + .ZN(n_1_0_539) + ); + AOI22_X1_LVT i_1_0_567( + .A1(registers_17__ap[28]), .A2(n_1_0_629), .B1(n_1_0_616), .B2(registers_6__ap[28]), + .ZN(n_1_0_538) + ); + AOI22_X1_LVT i_1_0_566( + .A1(registers_10__ap[28]), .A2(n_1_0_624), .B1(n_1_0_615), .B2(registers_23__ap[28]), + .ZN(n_1_0_537) + ); + AOI22_X1_LVT i_1_0_565( + .A1(registers_18__ap[28]), .A2(n_1_0_646), .B1(n_1_0_636), .B2(registers_27__ap[28]), + .ZN(n_1_0_536) + ); + NAND4_X1_LVT i_1_0_564( + .A1(n_1_0_539), .A2(n_1_0_538), .A3(n_1_0_537), .A4(n_1_0_536), .ZN(n_1_0_535) + ); + NOR3_X1_LVT i_1_0_563( + .A1(n_1_0_545), .A2(n_1_0_540), .A3(n_1_0_535), .ZN(n_1_0_534) + ); + NAND4_X1_LVT i_1_0_562( + .A1(n_1_0_552), .A2(n_1_0_551), .A3(n_1_0_550), .A4(n_1_0_534), .ZN(RRs2[28]) + ); + AOI22_X1_LVT i_1_0_561( + .A1(registers_17__ap[27]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[27]), + .ZN(n_1_0_533) + ); + AOI222_X1_LVT i_1_0_560( + .A1(registers_19__ap[27]), .A2(n_1_0_633), .B1(n_1_0_631), .B2(registers_13__ap[27]), + .C1(registers_30__ap[27]), .C2(n_1_0_622), .ZN(n_1_0_532) + ); + AOI22_X1_LVT i_1_0_559( + .A1(registers_1__ap[27]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[27]), + .ZN(n_1_0_531) + ); + AOI22_X1_LVT i_1_0_558( + .A1(registers_24__ap[27]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[27]), + .ZN(n_1_0_530) + ); + AOI22_X1_LVT i_1_0_557( + .A1(registers_15__ap[27]), .A2(n_1_0_627), .B1(n_1_0_611), .B2(registers_11__ap[27]), + .ZN(n_1_0_529) + ); + AOI22_X1_LVT i_1_0_556( + .A1(registers_4__ap[27]), .A2(n_1_0_638), .B1(n_1_0_636), .B2(registers_27__ap[27]), + .ZN(n_1_0_528) + ); + AOI22_X1_LVT i_1_0_555( + .A1(registers_31__ap[27]), .A2(n_1_0_637), .B1(n_1_0_618), .B2(registers_2__ap[27]), + .ZN(n_1_0_527) + ); + NAND4_X1_LVT i_1_0_554( + .A1(n_1_0_530), .A2(n_1_0_529), .A3(n_1_0_528), .A4(n_1_0_527), .ZN(n_1_0_526) + ); + AOI22_X1_LVT i_1_0_553( + .A1(registers_18__ap[27]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[27]), + .ZN(n_1_0_525) + ); + AOI22_X1_LVT i_1_0_552( + .A1(registers_5__ap[27]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[27]), + .ZN(n_1_0_524) + ); + AOI22_X1_LVT i_1_0_551( + .A1(registers_6__ap[27]), .A2(n_1_0_616), .B1(n_1_0_614), .B2(registers_16__ap[27]), + .ZN(n_1_0_523) + ); + AOI22_X1_LVT i_1_0_550( + .A1(registers_22__ap[27]), .A2(n_1_0_642), .B1(n_1_0_620), .B2(registers_25__ap[27]), + .ZN(n_1_0_522) + ); + NAND4_X1_LVT i_1_0_549( + .A1(n_1_0_525), .A2(n_1_0_524), .A3(n_1_0_523), .A4(n_1_0_522), .ZN(n_1_0_521) + ); + AOI22_X1_LVT i_1_0_548( + .A1(registers_29__ap[27]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[27]), + .ZN(n_1_0_520) + ); + AOI22_X1_LVT i_1_0_547( + .A1(registers_7__ap[27]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[27]), + .ZN(n_1_0_519) + ); + AOI22_X1_LVT i_1_0_546( + .A1(registers_8__ap[27]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[27]), + .ZN(n_1_0_518) + ); + AOI22_X1_LVT i_1_0_545( + .A1(registers_10__ap[27]), .A2(n_1_0_624), .B1(n_1_0_610), .B2(registers_3__ap[27]), + .ZN(n_1_0_517) + ); + NAND4_X1_LVT i_1_0_544( + .A1(n_1_0_520), .A2(n_1_0_519), .A3(n_1_0_518), .A4(n_1_0_517), .ZN(n_1_0_516) + ); + NOR3_X1_LVT i_1_0_543( + .A1(n_1_0_526), .A2(n_1_0_521), .A3(n_1_0_516), .ZN(n_1_0_515) + ); + NAND4_X1_LVT i_1_0_542( + .A1(n_1_0_533), .A2(n_1_0_532), .A3(n_1_0_531), .A4(n_1_0_515), .ZN(RRs2[27]) + ); + AOI22_X1_LVT i_1_0_541( + .A1(registers_17__ap[26]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[26]), + .ZN(n_1_0_514) + ); + AOI222_X1_LVT i_1_0_540( + .A1(registers_19__ap[26]), .A2(n_1_0_633), .B1(n_1_0_622), .B2(registers_30__ap[26]), + .C1(n_1_0_631), .C2(registers_13__ap[26]), .ZN(n_1_0_513) + ); + AOI22_X1_LVT i_1_0_539( + .A1(registers_1__ap[26]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[26]), + .ZN(n_1_0_512) + ); + AOI22_X1_LVT i_1_0_538( + .A1(registers_24__ap[26]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[26]), + .ZN(n_1_0_511) + ); + AOI22_X1_LVT i_1_0_537( + .A1(registers_15__ap[26]), .A2(n_1_0_627), .B1(n_1_0_611), .B2(registers_11__ap[26]), + .ZN(n_1_0_510) + ); + AOI22_X1_LVT i_1_0_536( + .A1(registers_4__ap[26]), .A2(n_1_0_638), .B1(n_1_0_636), .B2(registers_27__ap[26]), + .ZN(n_1_0_509) + ); + AOI22_X1_LVT i_1_0_535( + .A1(registers_31__ap[26]), .A2(n_1_0_637), .B1(n_1_0_618), .B2(registers_2__ap[26]), + .ZN(n_1_0_508) + ); + NAND4_X1_LVT i_1_0_534( + .A1(n_1_0_511), .A2(n_1_0_510), .A3(n_1_0_509), .A4(n_1_0_508), .ZN(n_1_0_507) + ); + AOI22_X1_LVT i_1_0_533( + .A1(registers_18__ap[26]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[26]), + .ZN(n_1_0_506) + ); + AOI22_X1_LVT i_1_0_532( + .A1(registers_5__ap[26]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[26]), + .ZN(n_1_0_505) + ); + AOI22_X1_LVT i_1_0_531( + .A1(registers_6__ap[26]), .A2(n_1_0_616), .B1(n_1_0_614), .B2(registers_16__ap[26]), + .ZN(n_1_0_504) + ); + AOI22_X1_LVT i_1_0_530( + .A1(registers_22__ap[26]), .A2(n_1_0_642), .B1(n_1_0_620), .B2(registers_25__ap[26]), + .ZN(n_1_0_503) + ); + NAND4_X1_LVT i_1_0_529( + .A1(n_1_0_506), .A2(n_1_0_505), .A3(n_1_0_504), .A4(n_1_0_503), .ZN(n_1_0_502) + ); + AOI22_X1_LVT i_1_0_528( + .A1(registers_29__ap[26]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[26]), + .ZN(n_1_0_501) + ); + AOI22_X1_LVT i_1_0_527( + .A1(registers_7__ap[26]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[26]), + .ZN(n_1_0_500) + ); + AOI22_X1_LVT i_1_0_526( + .A1(registers_8__ap[26]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[26]), + .ZN(n_1_0_499) + ); + AOI22_X1_LVT i_1_0_525( + .A1(registers_10__ap[26]), .A2(n_1_0_624), .B1(n_1_0_610), .B2(registers_3__ap[26]), + .ZN(n_1_0_498) + ); + NAND4_X1_LVT i_1_0_524( + .A1(n_1_0_501), .A2(n_1_0_500), .A3(n_1_0_499), .A4(n_1_0_498), .ZN(n_1_0_497) + ); + NOR3_X1_LVT i_1_0_523( + .A1(n_1_0_507), .A2(n_1_0_502), .A3(n_1_0_497), .ZN(n_1_0_496) + ); + NAND4_X1_LVT i_1_0_522( + .A1(n_1_0_514), .A2(n_1_0_513), .A3(n_1_0_512), .A4(n_1_0_496), .ZN(RRs2[26]) + ); + AOI22_X1_LVT i_1_0_520( + .A1(registers_5__ap[25]), .A2(n_1_0_635), .B1(n_1_0_634), .B2(registers_28__ap[25]), + .ZN(n_1_0_494) + ); + AOI22_X1_LVT i_1_0_521( + .A1(registers_8__ap[25]), .A2(n_1_0_626), .B1(n_1_0_620), .B2(registers_25__ap[25]), + .ZN(n_1_0_495) + ); + AOI22_X1_LVT i_1_0_519( + .A1(registers_14__ap[25]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[25]), + .ZN(n_1_0_493) + ); + AOI22_X1_LVT i_1_0_518( + .A1(registers_16__ap[25]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[25]), + .ZN(n_1_0_492) + ); + NAND3_X1_LVT i_1_0_517( + .A1(n_1_0_495), .A2(n_1_0_493), .A3(n_1_0_492), .ZN(n_1_0_491) + ); + AOI221_X1_LVT i_1_0_516( + .A(n_1_0_491), .B1(n_1_0_624), .B2(registers_10__ap[25]), .C1(registers_6__ap[25]), + .C2(n_1_0_616), .ZN(n_1_0_490) + ); + AOI222_X1_LVT i_1_0_515( + .A1(registers_1__ap[25]), .A2(n_1_0_644), .B1(n_1_0_640), .B2(registers_26__ap[25]), + .C1(n_1_0_622), .C2(registers_30__ap[25]), .ZN(n_1_0_489) + ); + NAND2_X1_LVT i_1_0_514( + .A1(n_1_0_490), .A2(n_1_0_489), .ZN(n_1_0_488) + ); + AOI221_X1_LVT i_1_0_513( + .A(n_1_0_488), .B1(n_1_0_649), .B2(registers_29__ap[25]), .C1(registers_2__ap[25]), + .C2(n_1_0_618), .ZN(n_1_0_487) + ); + AOI22_X1_LVT i_1_0_512( + .A1(registers_12__ap[25]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[25]), + .ZN(n_1_0_486) + ); + AOI22_X1_LVT i_1_0_511( + .A1(registers_22__ap[25]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[25]), + .ZN(n_1_0_485) + ); + AOI22_X1_LVT i_1_0_510( + .A1(registers_4__ap[25]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[25]), + .ZN(n_1_0_484) + ); + NAND3_X1_LVT i_1_0_509( + .A1(n_1_0_486), .A2(n_1_0_485), .A3(n_1_0_484), .ZN(n_1_0_483) + ); + AOI221_X1_LVT i_1_0_508( + .A(n_1_0_483), .B1(n_1_0_633), .B2(registers_19__ap[25]), .C1(registers_18__ap[25]), + .C2(n_1_0_646), .ZN(n_1_0_482) + ); + AOI22_X1_LVT i_1_0_507( + .A1(registers_15__ap[25]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[25]), + .ZN(n_1_0_481) + ); + AOI22_X1_LVT i_1_0_506( + .A1(registers_23__ap[25]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[25]), + .ZN(n_1_0_480) + ); + AOI22_X1_LVT i_1_0_505( + .A1(registers_13__ap[25]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[25]), + .ZN(n_1_0_479) + ); + NAND3_X1_LVT i_1_0_504( + .A1(n_1_0_481), .A2(n_1_0_480), .A3(n_1_0_479), .ZN(n_1_0_478) + ); + AOI221_X1_LVT i_1_0_503( + .A(n_1_0_478), .B1(n_1_0_636), .B2(registers_27__ap[25]), .C1(registers_31__ap[25]), + .C2(n_1_0_637), .ZN(n_1_0_477) + ); + NAND4_X1_LVT i_1_0_502( + .A1(n_1_0_494), .A2(n_1_0_487), .A3(n_1_0_482), .A4(n_1_0_477), .ZN(RRs2[25]) + ); + AOI22_X1_LVT i_1_0_501( + .A1(registers_17__ap[24]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[24]), + .ZN(n_1_0_476) + ); + AOI222_X1_LVT i_1_0_500( + .A1(registers_13__ap[24]), .A2(n_1_0_631), .B1(n_1_0_622), .B2(registers_30__ap[24]), + .C1(registers_26__ap[24]), .C2(n_1_0_640), .ZN(n_1_0_475) + ); + AOI22_X1_LVT i_1_0_499( + .A1(registers_1__ap[24]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[24]), + .ZN(n_1_0_474) + ); + AOI22_X1_LVT i_1_0_498( + .A1(registers_24__ap[24]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[24]), + .ZN(n_1_0_473) + ); + AOI22_X1_LVT i_1_0_497( + .A1(registers_8__ap[24]), .A2(n_1_0_626), .B1(n_1_0_616), .B2(registers_6__ap[24]), + .ZN(n_1_0_472) + ); + AOI22_X1_LVT i_1_0_496( + .A1(registers_4__ap[24]), .A2(n_1_0_638), .B1(n_1_0_611), .B2(registers_11__ap[24]), + .ZN(n_1_0_471) + ); + AOI22_X1_LVT i_1_0_495( + .A1(registers_10__ap[24]), .A2(n_1_0_624), .B1(n_1_0_618), .B2(registers_2__ap[24]), + .ZN(n_1_0_470) + ); + NAND4_X1_LVT i_1_0_494( + .A1(n_1_0_473), .A2(n_1_0_472), .A3(n_1_0_471), .A4(n_1_0_470), .ZN(n_1_0_469) + ); + AOI22_X1_LVT i_1_0_493( + .A1(registers_18__ap[24]), .A2(n_1_0_646), .B1(n_1_0_633), .B2(registers_19__ap[24]), + .ZN(n_1_0_468) + ); + AOI22_X1_LVT i_1_0_492( + .A1(registers_5__ap[24]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[24]), + .ZN(n_1_0_467) + ); + AOI22_X1_LVT i_1_0_491( + .A1(registers_15__ap[24]), .A2(n_1_0_627), .B1(n_1_0_614), .B2(registers_16__ap[24]), + .ZN(n_1_0_466) + ); + AOI22_X1_LVT i_1_0_490( + .A1(registers_22__ap[24]), .A2(n_1_0_642), .B1(n_1_0_620), .B2(registers_25__ap[24]), + .ZN(n_1_0_465) + ); + NAND4_X1_LVT i_1_0_489( + .A1(n_1_0_468), .A2(n_1_0_467), .A3(n_1_0_466), .A4(n_1_0_465), .ZN(n_1_0_464) + ); + AOI22_X1_LVT i_1_0_488( + .A1(registers_29__ap[24]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[24]), + .ZN(n_1_0_463) + ); + AOI22_X1_LVT i_1_0_487( + .A1(registers_7__ap[24]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[24]), + .ZN(n_1_0_462) + ); + AOI22_X1_LVT i_1_0_486( + .A1(registers_23__ap[24]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[24]), + .ZN(n_1_0_461) + ); + AOI22_X1_LVT i_1_0_485( + .A1(registers_31__ap[24]), .A2(n_1_0_637), .B1(n_1_0_636), .B2(registers_27__ap[24]), + .ZN(n_1_0_460) + ); + NAND4_X1_LVT i_1_0_484( + .A1(n_1_0_463), .A2(n_1_0_462), .A3(n_1_0_461), .A4(n_1_0_460), .ZN(n_1_0_459) + ); + NOR3_X1_LVT i_1_0_483( + .A1(n_1_0_469), .A2(n_1_0_464), .A3(n_1_0_459), .ZN(n_1_0_458) + ); + NAND4_X1_LVT i_1_0_482( + .A1(n_1_0_476), .A2(n_1_0_475), .A3(n_1_0_474), .A4(n_1_0_458), .ZN(RRs2[24]) + ); + AOI22_X1_LVT i_1_0_481( + .A1(registers_4__ap[23]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[23]), + .ZN(n_1_0_457) + ); + AOI222_X1_LVT i_1_0_480( + .A1(registers_18__ap[23]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[23]), + .C1(n_1_0_644), .C2(registers_1__ap[23]), .ZN(n_1_0_456) + ); + AOI22_X1_LVT i_1_0_479( + .A1(registers_29__ap[23]), .A2(n_1_0_649), .B1(n_1_0_618), .B2(registers_2__ap[23]), + .ZN(n_1_0_455) + ); + AOI22_X1_LVT i_1_0_478( + .A1(registers_14__ap[23]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[23]), + .ZN(n_1_0_454) + ); + AOI22_X1_LVT i_1_0_477( + .A1(registers_16__ap[23]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[23]), + .ZN(n_1_0_453) + ); + AOI22_X1_LVT i_1_0_476( + .A1(registers_27__ap[23]), .A2(n_1_0_636), .B1(n_1_0_620), .B2(registers_25__ap[23]), + .ZN(n_1_0_452) + ); + AOI22_X1_LVT i_1_0_475( + .A1(registers_31__ap[23]), .A2(n_1_0_637), .B1(n_1_0_616), .B2(registers_6__ap[23]), + .ZN(n_1_0_451) + ); + NAND4_X1_LVT i_1_0_474( + .A1(n_1_0_454), .A2(n_1_0_453), .A3(n_1_0_452), .A4(n_1_0_451), .ZN(n_1_0_450) + ); + AOI22_X1_LVT i_1_0_473( + .A1(registers_26__ap[23]), .A2(n_1_0_640), .B1(n_1_0_633), .B2(registers_19__ap[23]), + .ZN(n_1_0_449) + ); + AOI22_X1_LVT i_1_0_472( + .A1(registers_12__ap[23]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[23]), + .ZN(n_1_0_448) + ); + AOI22_X1_LVT i_1_0_471( + .A1(registers_22__ap[23]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[23]), + .ZN(n_1_0_447) + ); + AOI22_X1_LVT i_1_0_470( + .A1(registers_5__ap[23]), .A2(n_1_0_635), .B1(n_1_0_613), .B2(registers_20__ap[23]), + .ZN(n_1_0_446) + ); + NAND4_X1_LVT i_1_0_469( + .A1(n_1_0_449), .A2(n_1_0_448), .A3(n_1_0_447), .A4(n_1_0_446), .ZN(n_1_0_445) + ); + AOI22_X1_LVT i_1_0_468( + .A1(registers_15__ap[23]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[23]), + .ZN(n_1_0_444) + ); + AOI22_X1_LVT i_1_0_467( + .A1(registers_8__ap[23]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[23]), + .ZN(n_1_0_443) + ); + AOI22_X1_LVT i_1_0_466( + .A1(registers_13__ap[23]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[23]), + .ZN(n_1_0_442) + ); + AOI22_X1_LVT i_1_0_465( + .A1(registers_10__ap[23]), .A2(n_1_0_624), .B1(n_1_0_610), .B2(registers_3__ap[23]), + .ZN(n_1_0_441) + ); + NAND4_X1_LVT i_1_0_464( + .A1(n_1_0_444), .A2(n_1_0_443), .A3(n_1_0_442), .A4(n_1_0_441), .ZN(n_1_0_440) + ); + NOR3_X1_LVT i_1_0_463( + .A1(n_1_0_450), .A2(n_1_0_445), .A3(n_1_0_440), .ZN(n_1_0_439) + ); + NAND4_X1_LVT i_1_0_462( + .A1(n_1_0_457), .A2(n_1_0_456), .A3(n_1_0_455), .A4(n_1_0_439), .ZN(RRs2[23]) + ); + AOI22_X1_LVT i_1_0_460( + .A1(registers_17__ap[22]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[22]), + .ZN(n_1_0_437) + ); + AOI22_X1_LVT i_1_0_461( + .A1(registers_15__ap[22]), .A2(n_1_0_627), .B1(n_1_0_626), .B2(registers_8__ap[22]), + .ZN(n_1_0_438) + ); + AOI22_X1_LVT i_1_0_459( + .A1(registers_24__ap[22]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[22]), + .ZN(n_1_0_436) + ); + AOI22_X1_LVT i_1_0_458( + .A1(registers_5__ap[22]), .A2(n_1_0_635), .B1(n_1_0_611), .B2(registers_11__ap[22]), + .ZN(n_1_0_435) + ); + NAND3_X1_LVT i_1_0_457( + .A1(n_1_0_438), .A2(n_1_0_436), .A3(n_1_0_435), .ZN(n_1_0_434) + ); + AOI221_X1_LVT i_1_0_456( + .A(n_1_0_434), .B1(n_1_0_618), .B2(registers_2__ap[22]), .C1(registers_10__ap[22]), + .C2(n_1_0_624), .ZN(n_1_0_433) + ); + AOI222_X1_LVT i_1_0_455( + .A1(registers_26__ap[22]), .A2(n_1_0_640), .B1(n_1_0_622), .B2(registers_30__ap[22]), + .C1(n_1_0_631), .C2(registers_13__ap[22]), .ZN(n_1_0_432) + ); + NAND2_X1_LVT i_1_0_454( + .A1(n_1_0_433), .A2(n_1_0_432), .ZN(n_1_0_431) + ); + AOI221_X1_LVT i_1_0_453( + .A(n_1_0_431), .B1(n_1_0_644), .B2(registers_1__ap[22]), .C1(registers_28__ap[22]), + .C2(n_1_0_634), .ZN(n_1_0_430) + ); + AOI22_X1_LVT i_1_0_452( + .A1(registers_18__ap[22]), .A2(n_1_0_646), .B1(n_1_0_633), .B2(registers_19__ap[22]), + .ZN(n_1_0_429) + ); + AOI22_X1_LVT i_1_0_451( + .A1(registers_4__ap[22]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[22]), + .ZN(n_1_0_428) + ); + AOI22_X1_LVT i_1_0_450( + .A1(registers_6__ap[22]), .A2(n_1_0_616), .B1(n_1_0_614), .B2(registers_16__ap[22]), + .ZN(n_1_0_427) + ); + NAND3_X1_LVT i_1_0_449( + .A1(n_1_0_429), .A2(n_1_0_428), .A3(n_1_0_427), .ZN(n_1_0_426) + ); + AOI221_X1_LVT i_1_0_448( + .A(n_1_0_426), .B1(n_1_0_620), .B2(registers_25__ap[22]), .C1(registers_22__ap[22]), + .C2(n_1_0_642), .ZN(n_1_0_425) + ); + AOI22_X1_LVT i_1_0_447( + .A1(registers_29__ap[22]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[22]), + .ZN(n_1_0_424) + ); + AOI22_X1_LVT i_1_0_446( + .A1(registers_7__ap[22]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[22]), + .ZN(n_1_0_423) + ); + AOI22_X1_LVT i_1_0_445( + .A1(registers_23__ap[22]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[22]), + .ZN(n_1_0_422) + ); + NAND3_X1_LVT i_1_0_444( + .A1(n_1_0_424), .A2(n_1_0_423), .A3(n_1_0_422), .ZN(n_1_0_421) + ); + AOI221_X1_LVT i_1_0_443( + .A(n_1_0_421), .B1(n_1_0_636), .B2(registers_27__ap[22]), .C1(registers_31__ap[22]), + .C2(n_1_0_637), .ZN(n_1_0_420) + ); + NAND4_X1_LVT i_1_0_442( + .A1(n_1_0_437), .A2(n_1_0_430), .A3(n_1_0_425), .A4(n_1_0_420), .ZN(RRs2[22]) + ); + AOI22_X1_LVT i_1_0_441( + .A1(registers_5__ap[21]), .A2(n_1_0_635), .B1(n_1_0_634), .B2(registers_28__ap[21]), + .ZN(n_1_0_419) + ); + AOI222_X1_LVT i_1_0_440( + .A1(registers_1__ap[21]), .A2(n_1_0_644), .B1(n_1_0_640), .B2(registers_26__ap[21]), + .C1(n_1_0_622), .C2(registers_30__ap[21]), .ZN(n_1_0_418) + ); + AOI22_X1_LVT i_1_0_439( + .A1(registers_29__ap[21]), .A2(n_1_0_649), .B1(n_1_0_618), .B2(registers_2__ap[21]), + .ZN(n_1_0_417) + ); + AOI22_X1_LVT i_1_0_438( + .A1(registers_14__ap[21]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[21]), + .ZN(n_1_0_416) + ); + AOI22_X1_LVT i_1_0_437( + .A1(registers_8__ap[21]), .A2(n_1_0_626), .B1(n_1_0_614), .B2(registers_16__ap[21]), + .ZN(n_1_0_415) + ); + AOI22_X1_LVT i_1_0_436( + .A1(registers_25__ap[21]), .A2(n_1_0_620), .B1(n_1_0_611), .B2(registers_11__ap[21]), + .ZN(n_1_0_414) + ); + AOI22_X1_LVT i_1_0_435( + .A1(registers_10__ap[21]), .A2(n_1_0_624), .B1(n_1_0_616), .B2(registers_6__ap[21]), + .ZN(n_1_0_413) + ); + NAND4_X1_LVT i_1_0_434( + .A1(n_1_0_416), .A2(n_1_0_415), .A3(n_1_0_414), .A4(n_1_0_413), .ZN(n_1_0_412) + ); + AOI22_X1_LVT i_1_0_433( + .A1(registers_12__ap[21]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[21]), + .ZN(n_1_0_411) + ); + AOI22_X1_LVT i_1_0_432( + .A1(registers_22__ap[21]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[21]), + .ZN(n_1_0_410) + ); + AOI22_X1_LVT i_1_0_431( + .A1(registers_4__ap[21]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[21]), + .ZN(n_1_0_409) + ); + AOI22_X1_LVT i_1_0_430( + .A1(registers_18__ap[21]), .A2(n_1_0_646), .B1(n_1_0_633), .B2(registers_19__ap[21]), + .ZN(n_1_0_408) + ); + NAND4_X1_LVT i_1_0_429( + .A1(n_1_0_411), .A2(n_1_0_410), .A3(n_1_0_409), .A4(n_1_0_408), .ZN(n_1_0_407) + ); + AOI22_X1_LVT i_1_0_428( + .A1(registers_15__ap[21]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[21]), + .ZN(n_1_0_406) + ); + AOI22_X1_LVT i_1_0_427( + .A1(registers_23__ap[21]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[21]), + .ZN(n_1_0_405) + ); + AOI22_X1_LVT i_1_0_426( + .A1(registers_13__ap[21]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[21]), + .ZN(n_1_0_404) + ); + AOI22_X1_LVT i_1_0_425( + .A1(registers_31__ap[21]), .A2(n_1_0_637), .B1(n_1_0_636), .B2(registers_27__ap[21]), + .ZN(n_1_0_403) + ); + NAND4_X1_LVT i_1_0_424( + .A1(n_1_0_406), .A2(n_1_0_405), .A3(n_1_0_404), .A4(n_1_0_403), .ZN(n_1_0_402) + ); + NOR3_X1_LVT i_1_0_423( + .A1(n_1_0_412), .A2(n_1_0_407), .A3(n_1_0_402), .ZN(n_1_0_401) + ); + NAND4_X1_LVT i_1_0_422( + .A1(n_1_0_419), .A2(n_1_0_418), .A3(n_1_0_417), .A4(n_1_0_401), .ZN(RRs2[21]) + ); + AOI22_X1_LVT i_1_0_421( + .A1(registers_17__ap[20]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[20]), + .ZN(n_1_0_400) + ); + AOI222_X1_LVT i_1_0_420( + .A1(registers_13__ap[20]), .A2(n_1_0_631), .B1(n_1_0_622), .B2(registers_30__ap[20]), + .C1(registers_19__ap[20]), .C2(n_1_0_633), .ZN(n_1_0_399) + ); + AOI22_X1_LVT i_1_0_419( + .A1(registers_1__ap[20]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[20]), + .ZN(n_1_0_398) + ); + AOI22_X1_LVT i_1_0_418( + .A1(registers_24__ap[20]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[20]), + .ZN(n_1_0_397) + ); + AOI22_X1_LVT i_1_0_417( + .A1(registers_6__ap[20]), .A2(n_1_0_616), .B1(n_1_0_611), .B2(registers_11__ap[20]), + .ZN(n_1_0_396) + ); + AOI22_X1_LVT i_1_0_416( + .A1(registers_4__ap[20]), .A2(n_1_0_638), .B1(n_1_0_624), .B2(registers_10__ap[20]), + .ZN(n_1_0_395) + ); + AOI22_X1_LVT i_1_0_415( + .A1(registers_31__ap[20]), .A2(n_1_0_637), .B1(n_1_0_618), .B2(registers_2__ap[20]), + .ZN(n_1_0_394) + ); + NAND4_X1_LVT i_1_0_414( + .A1(n_1_0_397), .A2(n_1_0_396), .A3(n_1_0_395), .A4(n_1_0_394), .ZN(n_1_0_393) + ); + AOI22_X1_LVT i_1_0_413( + .A1(registers_18__ap[20]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[20]), + .ZN(n_1_0_392) + ); + AOI22_X1_LVT i_1_0_412( + .A1(registers_5__ap[20]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[20]), + .ZN(n_1_0_391) + ); + AOI22_X1_LVT i_1_0_411( + .A1(registers_15__ap[20]), .A2(n_1_0_627), .B1(n_1_0_614), .B2(registers_16__ap[20]), + .ZN(n_1_0_390) + ); + AOI22_X1_LVT i_1_0_410( + .A1(registers_22__ap[20]), .A2(n_1_0_642), .B1(n_1_0_620), .B2(registers_25__ap[20]), + .ZN(n_1_0_389) + ); + NAND4_X1_LVT i_1_0_409( + .A1(n_1_0_392), .A2(n_1_0_391), .A3(n_1_0_390), .A4(n_1_0_389), .ZN(n_1_0_388) + ); + AOI22_X1_LVT i_1_0_408( + .A1(registers_29__ap[20]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[20]), + .ZN(n_1_0_387) + ); + AOI22_X1_LVT i_1_0_407( + .A1(registers_7__ap[20]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[20]), + .ZN(n_1_0_386) + ); + AOI22_X1_LVT i_1_0_406( + .A1(registers_8__ap[20]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[20]), + .ZN(n_1_0_385) + ); + AOI22_X1_LVT i_1_0_405( + .A1(registers_27__ap[20]), .A2(n_1_0_636), .B1(n_1_0_610), .B2(registers_3__ap[20]), + .ZN(n_1_0_384) + ); + NAND4_X1_LVT i_1_0_404( + .A1(n_1_0_387), .A2(n_1_0_386), .A3(n_1_0_385), .A4(n_1_0_384), .ZN(n_1_0_383) + ); + NOR3_X1_LVT i_1_0_403( + .A1(n_1_0_393), .A2(n_1_0_388), .A3(n_1_0_383), .ZN(n_1_0_382) + ); + NAND4_X1_LVT i_1_0_402( + .A1(n_1_0_400), .A2(n_1_0_399), .A3(n_1_0_398), .A4(n_1_0_382), .ZN(RRs2[20]) + ); + AOI22_X1_LVT i_1_0_401( + .A1(registers_17__ap[19]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[19]), + .ZN(n_1_0_381) + ); + AOI222_X1_LVT i_1_0_400( + .A1(registers_13__ap[19]), .A2(n_1_0_631), .B1(n_1_0_622), .B2(registers_30__ap[19]), + .C1(registers_19__ap[19]), .C2(n_1_0_633), .ZN(n_1_0_380) + ); + AOI22_X1_LVT i_1_0_399( + .A1(registers_1__ap[19]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[19]), + .ZN(n_1_0_379) + ); + AOI22_X1_LVT i_1_0_398( + .A1(registers_24__ap[19]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[19]), + .ZN(n_1_0_378) + ); + AOI22_X1_LVT i_1_0_397( + .A1(registers_15__ap[19]), .A2(n_1_0_627), .B1(n_1_0_611), .B2(registers_11__ap[19]), + .ZN(n_1_0_377) + ); + AOI22_X1_LVT i_1_0_396( + .A1(registers_4__ap[19]), .A2(n_1_0_638), .B1(n_1_0_636), .B2(registers_27__ap[19]), + .ZN(n_1_0_376) + ); + AOI22_X1_LVT i_1_0_395( + .A1(registers_31__ap[19]), .A2(n_1_0_637), .B1(n_1_0_618), .B2(registers_2__ap[19]), + .ZN(n_1_0_375) + ); + NAND4_X1_LVT i_1_0_394( + .A1(n_1_0_378), .A2(n_1_0_377), .A3(n_1_0_376), .A4(n_1_0_375), .ZN(n_1_0_374) + ); + AOI22_X1_LVT i_1_0_393( + .A1(registers_18__ap[19]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[19]), + .ZN(n_1_0_373) + ); + AOI22_X1_LVT i_1_0_392( + .A1(registers_5__ap[19]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[19]), + .ZN(n_1_0_372) + ); + AOI22_X1_LVT i_1_0_391( + .A1(registers_25__ap[19]), .A2(n_1_0_620), .B1(n_1_0_616), .B2(registers_6__ap[19]), + .ZN(n_1_0_371) + ); + AOI22_X1_LVT i_1_0_390( + .A1(registers_22__ap[19]), .A2(n_1_0_642), .B1(n_1_0_614), .B2(registers_16__ap[19]), + .ZN(n_1_0_370) + ); + NAND4_X1_LVT i_1_0_389( + .A1(n_1_0_373), .A2(n_1_0_372), .A3(n_1_0_371), .A4(n_1_0_370), .ZN(n_1_0_369) + ); + AOI22_X1_LVT i_1_0_388( + .A1(registers_29__ap[19]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[19]), + .ZN(n_1_0_368) + ); + AOI22_X1_LVT i_1_0_387( + .A1(registers_7__ap[19]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[19]), + .ZN(n_1_0_367) + ); + AOI22_X1_LVT i_1_0_386( + .A1(registers_8__ap[19]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[19]), + .ZN(n_1_0_366) + ); + AOI22_X1_LVT i_1_0_385( + .A1(registers_10__ap[19]), .A2(n_1_0_624), .B1(n_1_0_610), .B2(registers_3__ap[19]), + .ZN(n_1_0_365) + ); + NAND4_X1_LVT i_1_0_384( + .A1(n_1_0_368), .A2(n_1_0_367), .A3(n_1_0_366), .A4(n_1_0_365), .ZN(n_1_0_364) + ); + NOR3_X1_LVT i_1_0_383( + .A1(n_1_0_374), .A2(n_1_0_369), .A3(n_1_0_364), .ZN(n_1_0_363) + ); + NAND4_X1_LVT i_1_0_382( + .A1(n_1_0_381), .A2(n_1_0_380), .A3(n_1_0_379), .A4(n_1_0_363), .ZN(RRs2[19]) + ); + AOI22_X1_LVT i_1_0_380( + .A1(registers_4__ap[18]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[18]), + .ZN(n_1_0_361) + ); + AOI22_X1_LVT i_1_0_381( + .A1(registers_8__ap[18]), .A2(n_1_0_626), .B1(n_1_0_614), .B2(registers_16__ap[18]), + .ZN(n_1_0_362) + ); + AOI22_X1_LVT i_1_0_379( + .A1(registers_14__ap[18]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[18]), + .ZN(n_1_0_360) + ); + AOI22_X1_LVT i_1_0_378( + .A1(registers_25__ap[18]), .A2(n_1_0_620), .B1(n_1_0_611), .B2(registers_11__ap[18]), + .ZN(n_1_0_359) + ); + NAND3_X1_LVT i_1_0_377( + .A1(n_1_0_362), .A2(n_1_0_360), .A3(n_1_0_359), .ZN(n_1_0_358) + ); + AOI221_X1_LVT i_1_0_376( + .A(n_1_0_358), .B1(n_1_0_624), .B2(registers_10__ap[18]), .C1(registers_6__ap[18]), + .C2(n_1_0_616), .ZN(n_1_0_357) + ); + AOI222_X1_LVT i_1_0_375( + .A1(registers_1__ap[18]), .A2(n_1_0_644), .B1(n_1_0_640), .B2(registers_26__ap[18]), + .C1(n_1_0_622), .C2(registers_30__ap[18]), .ZN(n_1_0_356) + ); + NAND2_X1_LVT i_1_0_374( + .A1(n_1_0_357), .A2(n_1_0_356), .ZN(n_1_0_355) + ); + AOI221_X1_LVT i_1_0_373( + .A(n_1_0_355), .B1(n_1_0_649), .B2(registers_29__ap[18]), .C1(registers_2__ap[18]), + .C2(n_1_0_618), .ZN(n_1_0_354) + ); + AOI22_X1_LVT i_1_0_372( + .A1(registers_18__ap[18]), .A2(n_1_0_646), .B1(n_1_0_633), .B2(registers_19__ap[18]), + .ZN(n_1_0_353) + ); + AOI22_X1_LVT i_1_0_371( + .A1(registers_12__ap[18]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[18]), + .ZN(n_1_0_352) + ); + AOI22_X1_LVT i_1_0_370( + .A1(registers_22__ap[18]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[18]), + .ZN(n_1_0_351) + ); + NAND3_X1_LVT i_1_0_369( + .A1(n_1_0_353), .A2(n_1_0_352), .A3(n_1_0_351), .ZN(n_1_0_350) + ); + AOI221_X1_LVT i_1_0_368( + .A(n_1_0_350), .B1(n_1_0_635), .B2(registers_5__ap[18]), .C1(registers_20__ap[18]), + .C2(n_1_0_613), .ZN(n_1_0_349) + ); + AOI22_X1_LVT i_1_0_367( + .A1(registers_15__ap[18]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[18]), + .ZN(n_1_0_348) + ); + AOI22_X1_LVT i_1_0_366( + .A1(registers_23__ap[18]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[18]), + .ZN(n_1_0_347) + ); + AOI22_X1_LVT i_1_0_365( + .A1(registers_13__ap[18]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[18]), + .ZN(n_1_0_346) + ); + NAND3_X1_LVT i_1_0_364( + .A1(n_1_0_348), .A2(n_1_0_347), .A3(n_1_0_346), .ZN(n_1_0_345) + ); + AOI221_X1_LVT i_1_0_363( + .A(n_1_0_345), .B1(n_1_0_637), .B2(registers_31__ap[18]), .C1(registers_27__ap[18]), + .C2(n_1_0_636), .ZN(n_1_0_344) + ); + NAND4_X1_LVT i_1_0_362( + .A1(n_1_0_361), .A2(n_1_0_354), .A3(n_1_0_349), .A4(n_1_0_344), .ZN(RRs2[18]) + ); + AOI22_X1_LVT i_1_0_358( + .A1(registers_4__ap[17]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[17]), + .ZN(n_1_0_340) + ); + AOI22_X1_LVT i_1_0_361( + .A1(registers_31__ap[17]), .A2(n_1_0_637), .B1(n_1_0_616), .B2(registers_6__ap[17]), + .ZN(n_1_0_343) + ); + AOI22_X1_LVT i_1_0_357( + .A1(registers_14__ap[17]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[17]), + .ZN(n_1_0_339) + ); + AOI22_X1_LVT i_1_0_360( + .A1(registers_25__ap[17]), .A2(n_1_0_620), .B1(n_1_0_611), .B2(registers_11__ap[17]), + .ZN(n_1_0_342) + ); + INV_X1_LVT i_1_0_359( + .A(n_1_0_342), .ZN(n_1_0_341) + ); + AOI221_X1_LVT i_1_0_356( + .A(n_1_0_341), .B1(n_1_0_614), .B2(registers_16__ap[17]), .C1(registers_10__ap[17]), + .C2(n_1_0_624), .ZN(n_1_0_338) + ); + AOI222_X1_LVT i_1_0_355( + .A1(registers_1__ap[17]), .A2(n_1_0_644), .B1(n_1_0_622), .B2(registers_30__ap[17]), + .C1(registers_18__ap[17]), .C2(n_1_0_646), .ZN(n_1_0_337) + ); + NAND4_X1_LVT i_1_0_354( + .A1(n_1_0_343), .A2(n_1_0_339), .A3(n_1_0_338), .A4(n_1_0_337), .ZN(n_1_0_336) + ); + AOI221_X1_LVT i_1_0_353( + .A(n_1_0_336), .B1(n_1_0_649), .B2(registers_29__ap[17]), .C1(registers_2__ap[17]), + .C2(n_1_0_618), .ZN(n_1_0_335) + ); + AOI22_X1_LVT i_1_0_352( + .A1(registers_26__ap[17]), .A2(n_1_0_640), .B1(n_1_0_633), .B2(registers_19__ap[17]), + .ZN(n_1_0_334) + ); + AOI22_X1_LVT i_1_0_351( + .A1(registers_12__ap[17]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[17]), + .ZN(n_1_0_333) + ); + AOI22_X1_LVT i_1_0_350( + .A1(registers_22__ap[17]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[17]), + .ZN(n_1_0_332) + ); + NAND3_X1_LVT i_1_0_349( + .A1(n_1_0_334), .A2(n_1_0_333), .A3(n_1_0_332), .ZN(n_1_0_331) + ); + AOI221_X1_LVT i_1_0_348( + .A(n_1_0_331), .B1(n_1_0_635), .B2(registers_5__ap[17]), .C1(registers_20__ap[17]), + .C2(n_1_0_613), .ZN(n_1_0_330) + ); + AOI22_X1_LVT i_1_0_347( + .A1(registers_15__ap[17]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[17]), + .ZN(n_1_0_329) + ); + AOI22_X1_LVT i_1_0_346( + .A1(registers_8__ap[17]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[17]), + .ZN(n_1_0_328) + ); + AOI22_X1_LVT i_1_0_345( + .A1(registers_13__ap[17]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[17]), + .ZN(n_1_0_327) + ); + NAND3_X1_LVT i_1_0_344( + .A1(n_1_0_329), .A2(n_1_0_328), .A3(n_1_0_327), .ZN(n_1_0_326) + ); + AOI221_X1_LVT i_1_0_343( + .A(n_1_0_326), .B1(n_1_0_636), .B2(registers_27__ap[17]), .C1(registers_3__ap[17]), + .C2(n_1_0_610), .ZN(n_1_0_325) + ); + NAND4_X1_LVT i_1_0_342( + .A1(n_1_0_340), .A2(n_1_0_335), .A3(n_1_0_330), .A4(n_1_0_325), .ZN(RRs2[17]) + ); + AOI22_X1_LVT i_1_0_341( + .A1(registers_4__ap[16]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[16]), + .ZN(n_1_0_324) + ); + AOI222_X1_LVT i_1_0_340( + .A1(registers_1__ap[16]), .A2(n_1_0_644), .B1(n_1_0_633), .B2(registers_19__ap[16]), + .C1(n_1_0_622), .C2(registers_30__ap[16]), .ZN(n_1_0_323) + ); + AOI22_X1_LVT i_1_0_339( + .A1(registers_29__ap[16]), .A2(n_1_0_649), .B1(n_1_0_618), .B2(registers_2__ap[16]), + .ZN(n_1_0_322) + ); + AOI22_X1_LVT i_1_0_338( + .A1(registers_14__ap[16]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[16]), + .ZN(n_1_0_321) + ); + AOI22_X1_LVT i_1_0_337( + .A1(registers_16__ap[16]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[16]), + .ZN(n_1_0_320) + ); + AOI22_X1_LVT i_1_0_336( + .A1(registers_10__ap[16]), .A2(n_1_0_624), .B1(n_1_0_620), .B2(registers_25__ap[16]), + .ZN(n_1_0_319) + ); + AOI22_X1_LVT i_1_0_335( + .A1(registers_31__ap[16]), .A2(n_1_0_637), .B1(n_1_0_616), .B2(registers_6__ap[16]), + .ZN(n_1_0_318) + ); + NAND4_X1_LVT i_1_0_334( + .A1(n_1_0_321), .A2(n_1_0_320), .A3(n_1_0_319), .A4(n_1_0_318), .ZN(n_1_0_317) + ); + AOI22_X1_LVT i_1_0_333( + .A1(registers_18__ap[16]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[16]), + .ZN(n_1_0_316) + ); + AOI22_X1_LVT i_1_0_332( + .A1(registers_12__ap[16]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[16]), + .ZN(n_1_0_315) + ); + AOI22_X1_LVT i_1_0_331( + .A1(registers_22__ap[16]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[16]), + .ZN(n_1_0_314) + ); + AOI22_X1_LVT i_1_0_330( + .A1(registers_5__ap[16]), .A2(n_1_0_635), .B1(n_1_0_613), .B2(registers_20__ap[16]), + .ZN(n_1_0_313) + ); + NAND4_X1_LVT i_1_0_329( + .A1(n_1_0_316), .A2(n_1_0_315), .A3(n_1_0_314), .A4(n_1_0_313), .ZN(n_1_0_312) + ); + AOI22_X1_LVT i_1_0_328( + .A1(registers_15__ap[16]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[16]), + .ZN(n_1_0_311) + ); + AOI22_X1_LVT i_1_0_327( + .A1(registers_8__ap[16]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[16]), + .ZN(n_1_0_310) + ); + AOI22_X1_LVT i_1_0_326( + .A1(registers_13__ap[16]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[16]), + .ZN(n_1_0_309) + ); + AOI22_X1_LVT i_1_0_325( + .A1(registers_27__ap[16]), .A2(n_1_0_636), .B1(n_1_0_610), .B2(registers_3__ap[16]), + .ZN(n_1_0_308) + ); + NAND4_X1_LVT i_1_0_324( + .A1(n_1_0_311), .A2(n_1_0_310), .A3(n_1_0_309), .A4(n_1_0_308), .ZN(n_1_0_307) + ); + NOR3_X1_LVT i_1_0_323( + .A1(n_1_0_317), .A2(n_1_0_312), .A3(n_1_0_307), .ZN(n_1_0_306) + ); + NAND4_X1_LVT i_1_0_322( + .A1(n_1_0_324), .A2(n_1_0_323), .A3(n_1_0_322), .A4(n_1_0_306), .ZN(RRs2[16]) + ); + AOI22_X1_LVT i_1_0_320( + .A1(registers_5__ap[15]), .A2(n_1_0_635), .B1(n_1_0_634), .B2(registers_28__ap[15]), + .ZN(n_1_0_304) + ); + AOI22_X1_LVT i_1_0_321( + .A1(registers_8__ap[15]), .A2(n_1_0_626), .B1(n_1_0_620), .B2(registers_25__ap[15]), + .ZN(n_1_0_305) + ); + AOI22_X1_LVT i_1_0_319( + .A1(registers_14__ap[15]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[15]), + .ZN(n_1_0_303) + ); + AOI22_X1_LVT i_1_0_318( + .A1(registers_16__ap[15]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[15]), + .ZN(n_1_0_302) + ); + NAND3_X1_LVT i_1_0_317( + .A1(n_1_0_305), .A2(n_1_0_303), .A3(n_1_0_302), .ZN(n_1_0_301) + ); + AOI221_X1_LVT i_1_0_316( + .A(n_1_0_301), .B1(n_1_0_616), .B2(registers_6__ap[15]), .C1(registers_10__ap[15]), + .C2(n_1_0_624), .ZN(n_1_0_300) + ); + AOI222_X1_LVT i_1_0_315( + .A1(registers_1__ap[15]), .A2(n_1_0_644), .B1(n_1_0_640), .B2(registers_26__ap[15]), + .C1(n_1_0_622), .C2(registers_30__ap[15]), .ZN(n_1_0_299) + ); + NAND2_X1_LVT i_1_0_314( + .A1(n_1_0_300), .A2(n_1_0_299), .ZN(n_1_0_298) + ); + AOI221_X1_LVT i_1_0_313( + .A(n_1_0_298), .B1(n_1_0_649), .B2(registers_29__ap[15]), .C1(registers_2__ap[15]), + .C2(n_1_0_618), .ZN(n_1_0_297) + ); + AOI22_X1_LVT i_1_0_312( + .A1(registers_12__ap[15]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[15]), + .ZN(n_1_0_296) + ); + AOI22_X1_LVT i_1_0_311( + .A1(registers_22__ap[15]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[15]), + .ZN(n_1_0_295) + ); + AOI22_X1_LVT i_1_0_310( + .A1(registers_4__ap[15]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[15]), + .ZN(n_1_0_294) + ); + NAND3_X1_LVT i_1_0_309( + .A1(n_1_0_296), .A2(n_1_0_295), .A3(n_1_0_294), .ZN(n_1_0_293) + ); + AOI221_X1_LVT i_1_0_308( + .A(n_1_0_293), .B1(n_1_0_633), .B2(registers_19__ap[15]), .C1(registers_18__ap[15]), + .C2(n_1_0_646), .ZN(n_1_0_292) + ); + AOI22_X1_LVT i_1_0_307( + .A1(registers_15__ap[15]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[15]), + .ZN(n_1_0_291) + ); + AOI22_X1_LVT i_1_0_306( + .A1(registers_23__ap[15]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[15]), + .ZN(n_1_0_290) + ); + AOI22_X1_LVT i_1_0_305( + .A1(registers_13__ap[15]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[15]), + .ZN(n_1_0_289) + ); + NAND3_X1_LVT i_1_0_304( + .A1(n_1_0_291), .A2(n_1_0_290), .A3(n_1_0_289), .ZN(n_1_0_288) + ); + AOI221_X1_LVT i_1_0_303( + .A(n_1_0_288), .B1(n_1_0_636), .B2(registers_27__ap[15]), .C1(registers_31__ap[15]), + .C2(n_1_0_637), .ZN(n_1_0_287) + ); + NAND4_X1_LVT i_1_0_302( + .A1(n_1_0_304), .A2(n_1_0_297), .A3(n_1_0_292), .A4(n_1_0_287), .ZN(RRs2[15]) + ); + AOI22_X1_LVT i_1_0_301( + .A1(registers_28__ap[14]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[14]), + .ZN(n_1_0_286) + ); + AOI222_X1_LVT i_1_0_300( + .A1(registers_18__ap[14]), .A2(n_1_0_646), .B1(n_1_0_620), .B2(registers_25__ap[14]), + .C1(n_1_0_618), .C2(registers_2__ap[14]), .ZN(n_1_0_285) + ); + AOI22_X1_LVT i_1_0_299( + .A1(registers_24__ap[14]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[14]), + .ZN(n_1_0_284) + ); + AOI22_X1_LVT i_1_0_298( + .A1(registers_15__ap[14]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[14]), + .ZN(n_1_0_283) + ); + AOI22_X1_LVT i_1_0_297( + .A1(registers_4__ap[14]), .A2(n_1_0_638), .B1(n_1_0_637), .B2(registers_31__ap[14]), + .ZN(n_1_0_282) + ); + AOI22_X1_LVT i_1_0_296( + .A1(registers_29__ap[14]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[14]), + .ZN(n_1_0_281) + ); + NAND4_X1_LVT i_1_0_295( + .A1(n_1_0_284), .A2(n_1_0_283), .A3(n_1_0_282), .A4(n_1_0_281), .ZN(n_1_0_280) + ); + AOI221_X1_LVT i_1_0_294( + .A(n_1_0_280), .B1(n_1_0_644), .B2(registers_1__ap[14]), .C1(registers_13__ap[14]), + .C2(n_1_0_631), .ZN(n_1_0_279) + ); + AOI22_X1_LVT i_1_0_293( + .A1(registers_17__ap[14]), .A2(n_1_0_629), .B1(n_1_0_623), .B2(registers_7__ap[14]), + .ZN(n_1_0_278) + ); + AOI22_X1_LVT i_1_0_292( + .A1(registers_5__ap[14]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[14]), + .ZN(n_1_0_277) + ); + AOI22_X1_LVT i_1_0_291( + .A1(registers_10__ap[14]), .A2(n_1_0_624), .B1(n_1_0_622), .B2(registers_30__ap[14]), + .ZN(n_1_0_276) + ); + AOI22_X1_LVT i_1_0_290( + .A1(registers_26__ap[14]), .A2(n_1_0_640), .B1(n_1_0_614), .B2(registers_16__ap[14]), + .ZN(n_1_0_275) + ); + NAND4_X1_LVT i_1_0_289( + .A1(n_1_0_278), .A2(n_1_0_277), .A3(n_1_0_276), .A4(n_1_0_275), .ZN(n_1_0_274) + ); + AOI22_X1_LVT i_1_0_288( + .A1(registers_9__ap[14]), .A2(n_1_0_617), .B1(n_1_0_612), .B2(registers_21__ap[14]), + .ZN(n_1_0_273) + ); + AOI22_X1_LVT i_1_0_287( + .A1(registers_14__ap[14]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[14]), + .ZN(n_1_0_272) + ); + AOI22_X1_LVT i_1_0_286( + .A1(registers_22__ap[14]), .A2(n_1_0_642), .B1(n_1_0_633), .B2(registers_19__ap[14]), + .ZN(n_1_0_271) + ); + AOI22_X1_LVT i_1_0_285( + .A1(registers_27__ap[14]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[14]), + .ZN(n_1_0_270) + ); + NAND4_X1_LVT i_1_0_284( + .A1(n_1_0_273), .A2(n_1_0_272), .A3(n_1_0_271), .A4(n_1_0_270), .ZN(n_1_0_269) + ); + NOR2_X1_LVT i_1_0_283( + .A1(n_1_0_274), .A2(n_1_0_269), .ZN(n_1_0_268) + ); + NAND4_X1_LVT i_1_0_282( + .A1(n_1_0_286), .A2(n_1_0_285), .A3(n_1_0_279), .A4(n_1_0_268), .ZN(RRs2[14]) + ); + AOI22_X1_LVT i_1_0_281( + .A1(registers_18__ap[13]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[13]), + .ZN(n_1_0_267) + ); + AOI22_X1_LVT i_1_0_280( + .A1(registers_12__ap[13]), .A2(n_1_0_632), .B1(n_1_0_629), .B2(registers_17__ap[13]), + .ZN(n_1_0_266) + ); + AOI22_X1_LVT i_1_0_279( + .A1(registers_7__ap[13]), .A2(n_1_0_623), .B1(n_1_0_614), .B2(registers_16__ap[13]), + .ZN(n_1_0_265) + ); + NAND3_X1_LVT i_1_0_277( + .A1(n_1_0_267), .A2(n_1_0_266), .A3(n_1_0_265), .ZN(n_1_0_263) + ); + AOI221_X1_LVT i_1_0_276( + .A(n_1_0_263), .B1(n_1_0_642), .B2(registers_22__ap[13]), .C1(registers_5__ap[13]), + .C2(n_1_0_635), .ZN(n_1_0_262) + ); + AOI22_X1_LVT i_1_0_278( + .A1(registers_13__ap[13]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[13]), + .ZN(n_1_0_264) + ); + AOI222_X1_LVT i_1_0_275( + .A1(registers_26__ap[13]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[13]), + .C1(n_1_0_620), .C2(registers_25__ap[13]), .ZN(n_1_0_261) + ); + AOI22_X1_LVT i_1_0_274( + .A1(registers_28__ap[13]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[13]), + .ZN(n_1_0_260) + ); + NAND3_X1_LVT i_1_0_273( + .A1(n_1_0_264), .A2(n_1_0_261), .A3(n_1_0_260), .ZN(n_1_0_259) + ); + AOI22_X1_LVT i_1_0_272( + .A1(registers_1__ap[13]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[13]), + .ZN(n_1_0_258) + ); + AOI22_X1_LVT i_1_0_271( + .A1(registers_19__ap[13]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[13]), + .ZN(n_1_0_257) + ); + AOI22_X1_LVT i_1_0_270( + .A1(registers_14__ap[13]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[13]), + .ZN(n_1_0_256) + ); + AOI22_X1_LVT i_1_0_269( + .A1(registers_27__ap[13]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[13]), + .ZN(n_1_0_255) + ); + NAND4_X1_LVT i_1_0_268( + .A1(n_1_0_258), .A2(n_1_0_257), .A3(n_1_0_256), .A4(n_1_0_255), .ZN(n_1_0_254) + ); + AOI22_X1_LVT i_1_0_267( + .A1(registers_24__ap[13]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[13]), + .ZN(n_1_0_253) + ); + AOI22_X1_LVT i_1_0_266( + .A1(registers_4__ap[13]), .A2(n_1_0_638), .B1(n_1_0_637), .B2(registers_31__ap[13]), + .ZN(n_1_0_252) + ); + AOI22_X1_LVT i_1_0_265( + .A1(registers_29__ap[13]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[13]), + .ZN(n_1_0_251) + ); + AOI22_X1_LVT i_1_0_264( + .A1(registers_15__ap[13]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[13]), + .ZN(n_1_0_250) + ); + NAND4_X1_LVT i_1_0_263( + .A1(n_1_0_253), .A2(n_1_0_252), .A3(n_1_0_251), .A4(n_1_0_250), .ZN(n_1_0_249) + ); + NOR3_X1_LVT i_1_0_262( + .A1(n_1_0_259), .A2(n_1_0_254), .A3(n_1_0_249), .ZN(n_1_0_248) + ); + NAND2_X1_LVT i_1_0_261( + .A1(n_1_0_262), .A2(n_1_0_248), .ZN(RRs2[13]) + ); + AOI22_X1_LVT i_1_0_260( + .A1(registers_18__ap[12]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[12]), + .ZN(n_1_0_247) + ); + AOI22_X1_LVT i_1_0_259( + .A1(registers_12__ap[12]), .A2(n_1_0_632), .B1(n_1_0_629), .B2(registers_17__ap[12]), + .ZN(n_1_0_246) + ); + AOI22_X1_LVT i_1_0_258( + .A1(registers_5__ap[12]), .A2(n_1_0_635), .B1(n_1_0_623), .B2(registers_7__ap[12]), + .ZN(n_1_0_245) + ); + NAND3_X1_LVT i_1_0_256( + .A1(n_1_0_247), .A2(n_1_0_246), .A3(n_1_0_245), .ZN(n_1_0_243) + ); + AOI221_X1_LVT i_1_0_255( + .A(n_1_0_243), .B1(n_1_0_642), .B2(registers_22__ap[12]), .C1(registers_16__ap[12]), + .C2(n_1_0_614), .ZN(n_1_0_242) + ); + AOI22_X1_LVT i_1_0_257( + .A1(registers_13__ap[12]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[12]), + .ZN(n_1_0_244) + ); + AOI222_X1_LVT i_1_0_254( + .A1(registers_26__ap[12]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[12]), + .C1(n_1_0_620), .C2(registers_25__ap[12]), .ZN(n_1_0_241) + ); + AOI22_X1_LVT i_1_0_253( + .A1(registers_28__ap[12]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[12]), + .ZN(n_1_0_240) + ); + NAND3_X1_LVT i_1_0_252( + .A1(n_1_0_244), .A2(n_1_0_241), .A3(n_1_0_240), .ZN(n_1_0_239) + ); + AOI22_X1_LVT i_1_0_251( + .A1(registers_1__ap[12]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[12]), + .ZN(n_1_0_238) + ); + AOI22_X1_LVT i_1_0_250( + .A1(registers_19__ap[12]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[12]), + .ZN(n_1_0_237) + ); + AOI22_X1_LVT i_1_0_249( + .A1(registers_14__ap[12]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[12]), + .ZN(n_1_0_236) + ); + AOI22_X1_LVT i_1_0_248( + .A1(registers_27__ap[12]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[12]), + .ZN(n_1_0_235) + ); + NAND4_X1_LVT i_1_0_247( + .A1(n_1_0_238), .A2(n_1_0_237), .A3(n_1_0_236), .A4(n_1_0_235), .ZN(n_1_0_234) + ); + AOI22_X1_LVT i_1_0_246( + .A1(registers_24__ap[12]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[12]), + .ZN(n_1_0_233) + ); + AOI22_X1_LVT i_1_0_245( + .A1(registers_4__ap[12]), .A2(n_1_0_638), .B1(n_1_0_637), .B2(registers_31__ap[12]), + .ZN(n_1_0_232) + ); + AOI22_X1_LVT i_1_0_244( + .A1(registers_29__ap[12]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[12]), + .ZN(n_1_0_231) + ); + AOI22_X1_LVT i_1_0_243( + .A1(registers_15__ap[12]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[12]), + .ZN(n_1_0_230) + ); + NAND4_X1_LVT i_1_0_242( + .A1(n_1_0_233), .A2(n_1_0_232), .A3(n_1_0_231), .A4(n_1_0_230), .ZN(n_1_0_229) + ); + NOR3_X1_LVT i_1_0_241( + .A1(n_1_0_239), .A2(n_1_0_234), .A3(n_1_0_229), .ZN(n_1_0_228) + ); + NAND2_X1_LVT i_1_0_240( + .A1(n_1_0_242), .A2(n_1_0_228), .ZN(RRs2[12]) + ); + AOI22_X1_LVT i_1_0_238( + .A1(registers_29__ap[11]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[11]), + .ZN(n_1_0_226) + ); + AOI22_X1_LVT i_1_0_239( + .A1(registers_27__ap[11]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[11]), + .ZN(n_1_0_227) + ); + AOI22_X1_LVT i_1_0_237( + .A1(registers_1__ap[11]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[11]), + .ZN(n_1_0_225) + ); + AOI22_X1_LVT i_1_0_236( + .A1(registers_5__ap[11]), .A2(n_1_0_635), .B1(n_1_0_615), .B2(registers_23__ap[11]), + .ZN(n_1_0_224) + ); + NAND3_X1_LVT i_1_0_235( + .A1(n_1_0_227), .A2(n_1_0_225), .A3(n_1_0_224), .ZN(n_1_0_223) + ); + AOI221_X1_LVT i_1_0_234( + .A(n_1_0_223), .B1(n_1_0_637), .B2(registers_31__ap[11]), .C1(registers_16__ap[11]), + .C2(n_1_0_614), .ZN(n_1_0_222) + ); + AOI222_X1_LVT i_1_0_233( + .A1(registers_8__ap[11]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[11]), + .C1(n_1_0_622), .C2(registers_30__ap[11]), .ZN(n_1_0_221) + ); + NAND3_X1_LVT i_1_0_232( + .A1(n_1_0_226), .A2(n_1_0_222), .A3(n_1_0_221), .ZN(n_1_0_220) + ); + AOI221_X1_LVT i_1_0_231( + .A(n_1_0_220), .B1(n_1_0_638), .B2(registers_4__ap[11]), .C1(registers_28__ap[11]), + .C2(n_1_0_634), .ZN(n_1_0_219) + ); + AOI22_X1_LVT i_1_0_230( + .A1(registers_18__ap[11]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[11]), + .ZN(n_1_0_218) + ); + AOI22_X1_LVT i_1_0_229( + .A1(registers_12__ap[11]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[11]), + .ZN(n_1_0_217) + ); + AOI22_X1_LVT i_1_0_228( + .A1(registers_22__ap[11]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[11]), + .ZN(n_1_0_216) + ); + NAND3_X1_LVT i_1_0_227( + .A1(n_1_0_218), .A2(n_1_0_217), .A3(n_1_0_216), .ZN(n_1_0_215) + ); + AOI221_X1_LVT i_1_0_226( + .A(n_1_0_215), .B1(n_1_0_613), .B2(registers_20__ap[11]), .C1(registers_17__ap[11]), + .C2(n_1_0_629), .ZN(n_1_0_214) + ); + AOI22_X1_LVT i_1_0_225( + .A1(registers_13__ap[11]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[11]), + .ZN(n_1_0_213) + ); + AOI22_X1_LVT i_1_0_224( + .A1(registers_7__ap[11]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[11]), + .ZN(n_1_0_212) + ); + AOI22_X1_LVT i_1_0_223( + .A1(registers_19__ap[11]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[11]), + .ZN(n_1_0_211) + ); + NAND3_X1_LVT i_1_0_222( + .A1(n_1_0_213), .A2(n_1_0_212), .A3(n_1_0_211), .ZN(n_1_0_210) + ); + AOI221_X1_LVT i_1_0_221( + .A(n_1_0_210), .B1(n_1_0_611), .B2(registers_11__ap[11]), .C1(registers_2__ap[11]), + .C2(n_1_0_618), .ZN(n_1_0_209) + ); + NAND3_X1_LVT i_1_0_220( + .A1(n_1_0_219), .A2(n_1_0_214), .A3(n_1_0_209), .ZN(RRs2[11]) + ); + AOI22_X1_LVT i_1_0_219( + .A1(registers_28__ap[10]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[10]), + .ZN(n_1_0_208) + ); + AOI222_X1_LVT i_1_0_218( + .A1(registers_26__ap[10]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[10]), + .C1(registers_25__ap[10]), .C2(n_1_0_620), .ZN(n_1_0_207) + ); + AOI22_X1_LVT i_1_0_217( + .A1(registers_13__ap[10]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[10]), + .ZN(n_1_0_206) + ); + AOI22_X1_LVT i_1_0_216( + .A1(registers_24__ap[10]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[10]), + .ZN(n_1_0_205) + ); + AOI22_X1_LVT i_1_0_215( + .A1(registers_15__ap[10]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[10]), + .ZN(n_1_0_204) + ); + AOI22_X1_LVT i_1_0_214( + .A1(registers_31__ap[10]), .A2(n_1_0_637), .B1(n_1_0_629), .B2(registers_17__ap[10]), + .ZN(n_1_0_203) + ); + AOI22_X1_LVT i_1_0_213( + .A1(registers_29__ap[10]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[10]), + .ZN(n_1_0_202) + ); + NAND4_X1_LVT i_1_0_212( + .A1(n_1_0_205), .A2(n_1_0_204), .A3(n_1_0_203), .A4(n_1_0_202), .ZN(n_1_0_201) + ); + AOI22_X1_LVT i_1_0_211( + .A1(registers_18__ap[10]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[10]), + .ZN(n_1_0_200) + ); + AOI22_X1_LVT i_1_0_210( + .A1(registers_4__ap[10]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[10]), + .ZN(n_1_0_199) + ); + AOI22_X1_LVT i_1_0_209( + .A1(registers_7__ap[10]), .A2(n_1_0_623), .B1(n_1_0_614), .B2(registers_16__ap[10]), + .ZN(n_1_0_198) + ); + AOI22_X1_LVT i_1_0_208( + .A1(registers_22__ap[10]), .A2(n_1_0_642), .B1(n_1_0_635), .B2(registers_5__ap[10]), + .ZN(n_1_0_197) + ); + NAND4_X1_LVT i_1_0_207( + .A1(n_1_0_200), .A2(n_1_0_199), .A3(n_1_0_198), .A4(n_1_0_197), .ZN(n_1_0_196) + ); + AOI22_X1_LVT i_1_0_206( + .A1(registers_1__ap[10]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[10]), + .ZN(n_1_0_195) + ); + AOI22_X1_LVT i_1_0_205( + .A1(registers_14__ap[10]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[10]), + .ZN(n_1_0_194) + ); + AOI22_X1_LVT i_1_0_204( + .A1(registers_19__ap[10]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[10]), + .ZN(n_1_0_193) + ); + AOI22_X1_LVT i_1_0_203( + .A1(registers_27__ap[10]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[10]), + .ZN(n_1_0_192) + ); + NAND4_X1_LVT i_1_0_202( + .A1(n_1_0_195), .A2(n_1_0_194), .A3(n_1_0_193), .A4(n_1_0_192), .ZN(n_1_0_191) + ); + NOR3_X1_LVT i_1_0_201( + .A1(n_1_0_201), .A2(n_1_0_196), .A3(n_1_0_191), .ZN(n_1_0_190) + ); + NAND4_X1_LVT i_1_0_200( + .A1(n_1_0_208), .A2(n_1_0_207), .A3(n_1_0_206), .A4(n_1_0_190), .ZN(RRs2[10]) + ); + AOI22_X1_LVT i_1_0_196( + .A1(registers_13__ap[9]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[9]), + .ZN(n_1_0_186) + ); + AOI22_X1_LVT i_1_0_199( + .A1(registers_29__ap[9]), .A2(n_1_0_649), .B1(n_1_0_636), .B2(registers_27__ap[9]), + .ZN(n_1_0_189) + ); + AOI22_X1_LVT i_1_0_195( + .A1(registers_24__ap[9]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[9]), + .ZN(n_1_0_185) + ); + AOI22_X1_LVT i_1_0_198( + .A1(registers_31__ap[9]), .A2(n_1_0_637), .B1(n_1_0_627), .B2(registers_15__ap[9]), + .ZN(n_1_0_188) + ); + INV_X1_LVT i_1_0_197( + .A(n_1_0_188), .ZN(n_1_0_187) + ); + AOI221_X1_LVT i_1_0_194( + .A(n_1_0_187), .B1(n_1_0_615), .B2(registers_23__ap[9]), .C1(registers_4__ap[9]), + .C2(n_1_0_638), .ZN(n_1_0_184) + ); + AOI222_X1_LVT i_1_0_193( + .A1(registers_18__ap[9]), .A2(n_1_0_646), .B1(n_1_0_624), .B2(registers_10__ap[9]), + .C1(registers_25__ap[9]), .C2(n_1_0_620), .ZN(n_1_0_183) + ); + NAND4_X1_LVT i_1_0_192( + .A1(n_1_0_189), .A2(n_1_0_185), .A3(n_1_0_184), .A4(n_1_0_183), .ZN(n_1_0_182) + ); + AOI221_X1_LVT i_1_0_191( + .A(n_1_0_182), .B1(n_1_0_626), .B2(registers_8__ap[9]), .C1(registers_28__ap[9]), + .C2(n_1_0_634), .ZN(n_1_0_181) + ); + AOI22_X1_LVT i_1_0_190( + .A1(registers_26__ap[9]), .A2(n_1_0_640), .B1(n_1_0_622), .B2(registers_30__ap[9]), + .ZN(n_1_0_180) + ); + AOI22_X1_LVT i_1_0_189( + .A1(registers_12__ap[9]), .A2(n_1_0_632), .B1(n_1_0_629), .B2(registers_17__ap[9]), + .ZN(n_1_0_179) + ); + AOI22_X1_LVT i_1_0_188( + .A1(registers_5__ap[9]), .A2(n_1_0_635), .B1(n_1_0_623), .B2(registers_7__ap[9]), + .ZN(n_1_0_178) + ); + NAND3_X1_LVT i_1_0_187( + .A1(n_1_0_180), .A2(n_1_0_179), .A3(n_1_0_178), .ZN(n_1_0_177) + ); + AOI221_X1_LVT i_1_0_186( + .A(n_1_0_177), .B1(n_1_0_642), .B2(registers_22__ap[9]), .C1(registers_16__ap[9]), + .C2(n_1_0_614), .ZN(n_1_0_176) + ); + AOI22_X1_LVT i_1_0_185( + .A1(registers_1__ap[9]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[9]), + .ZN(n_1_0_175) + ); + AOI22_X1_LVT i_1_0_184( + .A1(registers_14__ap[9]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[9]), + .ZN(n_1_0_174) + ); + AOI22_X1_LVT i_1_0_183( + .A1(registers_19__ap[9]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[9]), + .ZN(n_1_0_173) + ); + NAND3_X1_LVT i_1_0_182( + .A1(n_1_0_175), .A2(n_1_0_174), .A3(n_1_0_173), .ZN(n_1_0_172) + ); + AOI221_X1_LVT i_1_0_181( + .A(n_1_0_172), .B1(n_1_0_611), .B2(registers_11__ap[9]), .C1(registers_2__ap[9]), + .C2(n_1_0_618), .ZN(n_1_0_171) + ); + NAND4_X1_LVT i_1_0_180( + .A1(n_1_0_186), .A2(n_1_0_181), .A3(n_1_0_176), .A4(n_1_0_171), .ZN(RRs2[9]) + ); + AOI22_X1_LVT i_1_0_179( + .A1(registers_28__ap[8]), .A2(n_1_0_634), .B1(n_1_0_629), .B2(registers_17__ap[8]), + .ZN(n_1_0_170) + ); + AOI222_X1_LVT i_1_0_178( + .A1(registers_26__ap[8]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[8]), + .C1(n_1_0_626), .C2(registers_8__ap[8]), .ZN(n_1_0_169) + ); + AOI22_X1_LVT i_1_0_177( + .A1(registers_29__ap[8]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[8]), + .ZN(n_1_0_168) + ); + AOI22_X1_LVT i_1_0_176( + .A1(registers_1__ap[8]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[8]), + .ZN(n_1_0_167) + ); + AOI22_X1_LVT i_1_0_175( + .A1(registers_5__ap[8]), .A2(n_1_0_635), .B1(n_1_0_610), .B2(registers_3__ap[8]), + .ZN(n_1_0_166) + ); + AOI22_X1_LVT i_1_0_174( + .A1(registers_31__ap[8]), .A2(n_1_0_637), .B1(n_1_0_614), .B2(registers_16__ap[8]), + .ZN(n_1_0_165) + ); + AOI22_X1_LVT i_1_0_173( + .A1(registers_15__ap[8]), .A2(n_1_0_627), .B1(n_1_0_615), .B2(registers_23__ap[8]), + .ZN(n_1_0_164) + ); + NAND4_X1_LVT i_1_0_172( + .A1(n_1_0_167), .A2(n_1_0_166), .A3(n_1_0_165), .A4(n_1_0_164), .ZN(n_1_0_163) + ); + AOI22_X1_LVT i_1_0_171( + .A1(registers_18__ap[8]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[8]), + .ZN(n_1_0_162) + ); + AOI22_X1_LVT i_1_0_170( + .A1(registers_4__ap[8]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[8]), + .ZN(n_1_0_161) + ); + AOI22_X1_LVT i_1_0_169( + .A1(registers_22__ap[8]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[8]), + .ZN(n_1_0_160) + ); + AOI22_X1_LVT i_1_0_168( + .A1(registers_12__ap[8]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[8]), + .ZN(n_1_0_159) + ); + NAND4_X1_LVT i_1_0_167( + .A1(n_1_0_162), .A2(n_1_0_161), .A3(n_1_0_160), .A4(n_1_0_159), .ZN(n_1_0_158) + ); + AOI22_X1_LVT i_1_0_166( + .A1(registers_13__ap[8]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[8]), + .ZN(n_1_0_157) + ); + AOI22_X1_LVT i_1_0_165( + .A1(registers_7__ap[8]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[8]), + .ZN(n_1_0_156) + ); + AOI22_X1_LVT i_1_0_164( + .A1(registers_19__ap[8]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[8]), + .ZN(n_1_0_155) + ); + AOI22_X1_LVT i_1_0_163( + .A1(registers_27__ap[8]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[8]), + .ZN(n_1_0_154) + ); + NAND4_X1_LVT i_1_0_162( + .A1(n_1_0_157), .A2(n_1_0_156), .A3(n_1_0_155), .A4(n_1_0_154), .ZN(n_1_0_153) + ); + NOR3_X1_LVT i_1_0_161( + .A1(n_1_0_163), .A2(n_1_0_158), .A3(n_1_0_153), .ZN(n_1_0_152) + ); + NAND4_X1_LVT i_1_0_160( + .A1(n_1_0_170), .A2(n_1_0_169), .A3(n_1_0_168), .A4(n_1_0_152), .ZN(RRs2[8]) + ); + AOI22_X1_LVT i_1_0_159( + .A1(registers_28__ap[7]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[7]), + .ZN(n_1_0_151) + ); + AOI222_X1_LVT i_1_0_158( + .A1(registers_26__ap[7]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[7]), + .C1(registers_25__ap[7]), .C2(n_1_0_620), .ZN(n_1_0_150) + ); + AOI22_X1_LVT i_1_0_157( + .A1(registers_24__ap[7]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[7]), + .ZN(n_1_0_149) + ); + AOI22_X1_LVT i_1_0_156( + .A1(registers_15__ap[7]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[7]), + .ZN(n_1_0_148) + ); + AOI22_X1_LVT i_1_0_155( + .A1(registers_31__ap[7]), .A2(n_1_0_637), .B1(n_1_0_629), .B2(registers_17__ap[7]), + .ZN(n_1_0_147) + ); + AOI22_X1_LVT i_1_0_154( + .A1(registers_29__ap[7]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[7]), + .ZN(n_1_0_146) + ); + NAND4_X1_LVT i_1_0_153( + .A1(n_1_0_149), .A2(n_1_0_148), .A3(n_1_0_147), .A4(n_1_0_146), .ZN(n_1_0_145) + ); + AOI221_X1_LVT i_1_0_152( + .A(n_1_0_145), .B1(n_1_0_612), .B2(registers_21__ap[7]), .C1(registers_13__ap[7]), + .C2(n_1_0_631), .ZN(n_1_0_144) + ); + AOI22_X1_LVT i_1_0_151( + .A1(registers_18__ap[7]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[7]), + .ZN(n_1_0_143) + ); + AOI22_X1_LVT i_1_0_150( + .A1(registers_4__ap[7]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[7]), + .ZN(n_1_0_142) + ); + AOI22_X1_LVT i_1_0_149( + .A1(registers_5__ap[7]), .A2(n_1_0_635), .B1(n_1_0_623), .B2(registers_7__ap[7]), + .ZN(n_1_0_141) + ); + AOI22_X1_LVT i_1_0_148( + .A1(registers_22__ap[7]), .A2(n_1_0_642), .B1(n_1_0_614), .B2(registers_16__ap[7]), + .ZN(n_1_0_140) + ); + NAND4_X1_LVT i_1_0_147( + .A1(n_1_0_143), .A2(n_1_0_142), .A3(n_1_0_141), .A4(n_1_0_140), .ZN(n_1_0_139) + ); + AOI22_X1_LVT i_1_0_146( + .A1(registers_1__ap[7]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[7]), + .ZN(n_1_0_138) + ); + AOI22_X1_LVT i_1_0_145( + .A1(registers_14__ap[7]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[7]), + .ZN(n_1_0_137) + ); + AOI22_X1_LVT i_1_0_144( + .A1(registers_19__ap[7]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[7]), + .ZN(n_1_0_136) + ); + AOI22_X1_LVT i_1_0_143( + .A1(registers_27__ap[7]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[7]), + .ZN(n_1_0_135) + ); + NAND4_X1_LVT i_1_0_142( + .A1(n_1_0_138), .A2(n_1_0_137), .A3(n_1_0_136), .A4(n_1_0_135), .ZN(n_1_0_134) + ); + NOR2_X1_LVT i_1_0_141( + .A1(n_1_0_139), .A2(n_1_0_134), .ZN(n_1_0_133) + ); + NAND4_X1_LVT i_1_0_140( + .A1(n_1_0_151), .A2(n_1_0_150), .A3(n_1_0_144), .A4(n_1_0_133), .ZN(RRs2[7]) + ); + AOI22_X1_LVT i_1_0_136( + .A1(registers_13__ap[6]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[6]), + .ZN(n_1_0_129) + ); + AOI22_X1_LVT i_1_0_139( + .A1(registers_29__ap[6]), .A2(n_1_0_649), .B1(n_1_0_636), .B2(registers_27__ap[6]), + .ZN(n_1_0_132) + ); + AOI22_X1_LVT i_1_0_135( + .A1(registers_24__ap[6]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[6]), + .ZN(n_1_0_128) + ); + AOI22_X1_LVT i_1_0_138( + .A1(registers_31__ap[6]), .A2(n_1_0_637), .B1(n_1_0_627), .B2(registers_15__ap[6]), + .ZN(n_1_0_131) + ); + INV_X1_LVT i_1_0_137( + .A(n_1_0_131), .ZN(n_1_0_130) + ); + AOI221_X1_LVT i_1_0_134( + .A(n_1_0_130), .B1(n_1_0_638), .B2(registers_4__ap[6]), .C1(registers_23__ap[6]), + .C2(n_1_0_615), .ZN(n_1_0_127) + ); + AOI222_X1_LVT i_1_0_133( + .A1(registers_18__ap[6]), .A2(n_1_0_646), .B1(n_1_0_620), .B2(registers_25__ap[6]), + .C1(n_1_0_624), .C2(registers_10__ap[6]), .ZN(n_1_0_126) + ); + NAND4_X1_LVT i_1_0_132( + .A1(n_1_0_132), .A2(n_1_0_128), .A3(n_1_0_127), .A4(n_1_0_126), .ZN(n_1_0_125) + ); + AOI221_X1_LVT i_1_0_131( + .A(n_1_0_125), .B1(n_1_0_626), .B2(registers_8__ap[6]), .C1(registers_28__ap[6]), + .C2(n_1_0_634), .ZN(n_1_0_124) + ); + AOI22_X1_LVT i_1_0_130( + .A1(registers_26__ap[6]), .A2(n_1_0_640), .B1(n_1_0_622), .B2(registers_30__ap[6]), + .ZN(n_1_0_123) + ); + AOI22_X1_LVT i_1_0_129( + .A1(registers_12__ap[6]), .A2(n_1_0_632), .B1(n_1_0_629), .B2(registers_17__ap[6]), + .ZN(n_1_0_122) + ); + AOI22_X1_LVT i_1_0_128( + .A1(registers_7__ap[6]), .A2(n_1_0_623), .B1(n_1_0_614), .B2(registers_16__ap[6]), + .ZN(n_1_0_121) + ); + NAND3_X1_LVT i_1_0_127( + .A1(n_1_0_123), .A2(n_1_0_122), .A3(n_1_0_121), .ZN(n_1_0_120) + ); + AOI221_X1_LVT i_1_0_126( + .A(n_1_0_120), .B1(n_1_0_642), .B2(registers_22__ap[6]), .C1(registers_5__ap[6]), + .C2(n_1_0_635), .ZN(n_1_0_119) + ); + AOI22_X1_LVT i_1_0_125( + .A1(registers_1__ap[6]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[6]), + .ZN(n_1_0_118) + ); + AOI22_X1_LVT i_1_0_124( + .A1(registers_14__ap[6]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[6]), + .ZN(n_1_0_117) + ); + AOI22_X1_LVT i_1_0_123( + .A1(registers_19__ap[6]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[6]), + .ZN(n_1_0_116) + ); + NAND3_X1_LVT i_1_0_122( + .A1(n_1_0_118), .A2(n_1_0_117), .A3(n_1_0_116), .ZN(n_1_0_115) + ); + AOI221_X1_LVT i_1_0_121( + .A(n_1_0_115), .B1(n_1_0_618), .B2(registers_2__ap[6]), .C1(registers_11__ap[6]), + .C2(n_1_0_611), .ZN(n_1_0_114) + ); + NAND4_X1_LVT i_1_0_120( + .A1(n_1_0_129), .A2(n_1_0_124), .A3(n_1_0_119), .A4(n_1_0_114), .ZN(RRs2[6]) + ); + AOI22_X1_LVT i_1_0_118( + .A1(registers_28__ap[5]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[5]), + .ZN(n_1_0_112) + ); + AOI22_X1_LVT i_1_0_119( + .A1(registers_31__ap[5]), .A2(n_1_0_637), .B1(n_1_0_627), .B2(registers_15__ap[5]), + .ZN(n_1_0_113) + ); + AOI22_X1_LVT i_1_0_117( + .A1(registers_24__ap[5]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[5]), + .ZN(n_1_0_111) + ); + AOI22_X1_LVT i_1_0_116( + .A1(registers_17__ap[5]), .A2(n_1_0_629), .B1(n_1_0_615), .B2(registers_23__ap[5]), + .ZN(n_1_0_110) + ); + NAND3_X1_LVT i_1_0_115( + .A1(n_1_0_113), .A2(n_1_0_111), .A3(n_1_0_110), .ZN(n_1_0_109) + ); + AOI221_X1_LVT i_1_0_114( + .A(n_1_0_109), .B1(n_1_0_636), .B2(registers_27__ap[5]), .C1(registers_29__ap[5]), + .C2(n_1_0_649), .ZN(n_1_0_108) + ); + AOI222_X1_LVT i_1_0_113( + .A1(registers_10__ap[5]), .A2(n_1_0_624), .B1(n_1_0_620), .B2(registers_25__ap[5]), + .C1(registers_18__ap[5]), .C2(n_1_0_646), .ZN(n_1_0_107) + ); + NAND3_X1_LVT i_1_0_112( + .A1(n_1_0_112), .A2(n_1_0_108), .A3(n_1_0_107), .ZN(n_1_0_106) + ); + AOI221_X1_LVT i_1_0_111( + .A(n_1_0_106), .B1(n_1_0_612), .B2(registers_21__ap[5]), .C1(registers_13__ap[5]), + .C2(n_1_0_631), .ZN(n_1_0_105) + ); + AOI22_X1_LVT i_1_0_110( + .A1(registers_26__ap[5]), .A2(n_1_0_640), .B1(n_1_0_622), .B2(registers_30__ap[5]), + .ZN(n_1_0_104) + ); + AOI22_X1_LVT i_1_0_109( + .A1(registers_4__ap[5]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[5]), + .ZN(n_1_0_103) + ); + AOI22_X1_LVT i_1_0_108( + .A1(registers_5__ap[5]), .A2(n_1_0_635), .B1(n_1_0_623), .B2(registers_7__ap[5]), + .ZN(n_1_0_102) + ); + NAND3_X1_LVT i_1_0_107( + .A1(n_1_0_104), .A2(n_1_0_103), .A3(n_1_0_102), .ZN(n_1_0_101) + ); + AOI221_X1_LVT i_1_0_106( + .A(n_1_0_101), .B1(n_1_0_642), .B2(registers_22__ap[5]), .C1(registers_16__ap[5]), + .C2(n_1_0_614), .ZN(n_1_0_100) + ); + AOI22_X1_LVT i_1_0_105( + .A1(registers_1__ap[5]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[5]), + .ZN(n_1_0_99) + ); + AOI22_X1_LVT i_1_0_104( + .A1(registers_14__ap[5]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[5]), + .ZN(n_1_0_98) + ); + AOI22_X1_LVT i_1_0_103( + .A1(registers_19__ap[5]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[5]), + .ZN(n_1_0_97) + ); + NAND3_X1_LVT i_1_0_102( + .A1(n_1_0_99), .A2(n_1_0_98), .A3(n_1_0_97), .ZN(n_1_0_96) + ); + AOI221_X1_LVT i_1_0_101( + .A(n_1_0_96), .B1(n_1_0_611), .B2(registers_11__ap[5]), .C1(registers_2__ap[5]), + .C2(n_1_0_618), .ZN(n_1_0_95) + ); + NAND3_X1_LVT i_1_0_100( + .A1(n_1_0_105), .A2(n_1_0_100), .A3(n_1_0_95), .ZN(RRs2[5]) + ); + AOI22_X1_LVT i_1_0_99( + .A1(registers_4__ap[4]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[4]), + .ZN(n_1_0_94) + ); + AOI222_X1_LVT i_1_0_98( + .A1(registers_8__ap[4]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[4]), + .C1(n_1_0_622), .C2(registers_30__ap[4]), .ZN(n_1_0_93) + ); + AOI22_X1_LVT i_1_0_97( + .A1(registers_29__ap[4]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[4]), + .ZN(n_1_0_92) + ); + AOI22_X1_LVT i_1_0_96( + .A1(registers_1__ap[4]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[4]), + .ZN(n_1_0_91) + ); + AOI22_X1_LVT i_1_0_95( + .A1(registers_27__ap[4]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[4]), + .ZN(n_1_0_90) + ); + AOI22_X1_LVT i_1_0_94( + .A1(registers_23__ap[4]), .A2(n_1_0_615), .B1(n_1_0_614), .B2(registers_16__ap[4]), + .ZN(n_1_0_89) + ); + AOI22_X1_LVT i_1_0_93( + .A1(registers_31__ap[4]), .A2(n_1_0_637), .B1(n_1_0_635), .B2(registers_5__ap[4]), + .ZN(n_1_0_88) + ); + NAND4_X1_LVT i_1_0_92( + .A1(n_1_0_91), .A2(n_1_0_90), .A3(n_1_0_89), .A4(n_1_0_88), .ZN(n_1_0_87) + ); + AOI22_X1_LVT i_1_0_91( + .A1(registers_18__ap[4]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[4]), + .ZN(n_1_0_86) + ); + AOI22_X1_LVT i_1_0_90( + .A1(registers_12__ap[4]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[4]), + .ZN(n_1_0_85) + ); + AOI22_X1_LVT i_1_0_89( + .A1(registers_22__ap[4]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[4]), + .ZN(n_1_0_84) + ); + AOI22_X1_LVT i_1_0_88( + .A1(registers_17__ap[4]), .A2(n_1_0_629), .B1(n_1_0_613), .B2(registers_20__ap[4]), + .ZN(n_1_0_83) + ); + NAND4_X1_LVT i_1_0_87( + .A1(n_1_0_86), .A2(n_1_0_85), .A3(n_1_0_84), .A4(n_1_0_83), .ZN(n_1_0_82) + ); + AOI22_X1_LVT i_1_0_86( + .A1(registers_13__ap[4]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[4]), + .ZN(n_1_0_81) + ); + AOI22_X1_LVT i_1_0_85( + .A1(registers_7__ap[4]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[4]), + .ZN(n_1_0_80) + ); + AOI22_X1_LVT i_1_0_84( + .A1(registers_19__ap[4]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[4]), + .ZN(n_1_0_79) + ); + AOI22_X1_LVT i_1_0_83( + .A1(registers_2__ap[4]), .A2(n_1_0_618), .B1(n_1_0_611), .B2(registers_11__ap[4]), + .ZN(n_1_0_78) + ); + NAND4_X1_LVT i_1_0_82( + .A1(n_1_0_81), .A2(n_1_0_80), .A3(n_1_0_79), .A4(n_1_0_78), .ZN(n_1_0_77) + ); + NOR3_X1_LVT i_1_0_81( + .A1(n_1_0_87), .A2(n_1_0_82), .A3(n_1_0_77), .ZN(n_1_0_76) + ); + NAND4_X1_LVT i_1_0_80( + .A1(n_1_0_94), .A2(n_1_0_93), .A3(n_1_0_92), .A4(n_1_0_76), .ZN(RRs2[4]) + ); + AOI22_X1_LVT i_1_0_78( + .A1(registers_29__ap[3]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[3]), + .ZN(n_1_0_74) + ); + AOI22_X1_LVT i_1_0_79( + .A1(registers_27__ap[3]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[3]), + .ZN(n_1_0_75) + ); + AOI22_X1_LVT i_1_0_77( + .A1(registers_1__ap[3]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[3]), + .ZN(n_1_0_73) + ); + AOI22_X1_LVT i_1_0_76( + .A1(registers_5__ap[3]), .A2(n_1_0_635), .B1(n_1_0_611), .B2(registers_11__ap[3]), + .ZN(n_1_0_72) + ); + NAND3_X1_LVT i_1_0_75( + .A1(n_1_0_75), .A2(n_1_0_73), .A3(n_1_0_72), .ZN(n_1_0_71) + ); + AOI221_X1_LVT i_1_0_74( + .A(n_1_0_71), .B1(n_1_0_614), .B2(registers_16__ap[3]), .C1(registers_31__ap[3]), + .C2(n_1_0_637), .ZN(n_1_0_70) + ); + AOI222_X1_LVT i_1_0_73( + .A1(registers_8__ap[3]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[3]), + .C1(n_1_0_622), .C2(registers_30__ap[3]), .ZN(n_1_0_69) + ); + NAND3_X1_LVT i_1_0_72( + .A1(n_1_0_74), .A2(n_1_0_70), .A3(n_1_0_69), .ZN(n_1_0_68) + ); + AOI221_X1_LVT i_1_0_71( + .A(n_1_0_68), .B1(n_1_0_638), .B2(registers_4__ap[3]), .C1(registers_28__ap[3]), + .C2(n_1_0_634), .ZN(n_1_0_67) + ); + AOI22_X1_LVT i_1_0_70( + .A1(registers_18__ap[3]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[3]), + .ZN(n_1_0_66) + ); + AOI22_X1_LVT i_1_0_69( + .A1(registers_12__ap[3]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[3]), + .ZN(n_1_0_65) + ); + AOI22_X1_LVT i_1_0_68( + .A1(registers_22__ap[3]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[3]), + .ZN(n_1_0_64) + ); + NAND3_X1_LVT i_1_0_67( + .A1(n_1_0_66), .A2(n_1_0_65), .A3(n_1_0_64), .ZN(n_1_0_63) + ); + AOI221_X1_LVT i_1_0_66( + .A(n_1_0_63), .B1(n_1_0_613), .B2(registers_20__ap[3]), .C1(registers_17__ap[3]), + .C2(n_1_0_629), .ZN(n_1_0_62) + ); + AOI22_X1_LVT i_1_0_65( + .A1(registers_13__ap[3]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[3]), + .ZN(n_1_0_61) + ); + AOI22_X1_LVT i_1_0_64( + .A1(registers_7__ap[3]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[3]), + .ZN(n_1_0_60) + ); + AOI22_X1_LVT i_1_0_63( + .A1(registers_19__ap[3]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[3]), + .ZN(n_1_0_59) + ); + NAND3_X1_LVT i_1_0_62( + .A1(n_1_0_61), .A2(n_1_0_60), .A3(n_1_0_59), .ZN(n_1_0_58) + ); + AOI221_X1_LVT i_1_0_61( + .A(n_1_0_58), .B1(n_1_0_618), .B2(registers_2__ap[3]), .C1(registers_23__ap[3]), + .C2(n_1_0_615), .ZN(n_1_0_57) + ); + NAND3_X1_LVT i_1_0_60( + .A1(n_1_0_67), .A2(n_1_0_62), .A3(n_1_0_57), .ZN(RRs2[3]) + ); + AOI22_X1_LVT i_1_0_58( + .A1(registers_29__ap[2]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[2]), + .ZN(n_1_0_55) + ); + AOI22_X1_LVT i_1_0_59( + .A1(registers_27__ap[2]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[2]), + .ZN(n_1_0_56) + ); + AOI22_X1_LVT i_1_0_57( + .A1(registers_1__ap[2]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[2]), + .ZN(n_1_0_54) + ); + AOI22_X1_LVT i_1_0_56( + .A1(registers_5__ap[2]), .A2(n_1_0_635), .B1(n_1_0_615), .B2(registers_23__ap[2]), + .ZN(n_1_0_53) + ); + NAND3_X1_LVT i_1_0_55( + .A1(n_1_0_56), .A2(n_1_0_54), .A3(n_1_0_53), .ZN(n_1_0_52) + ); + AOI221_X1_LVT i_1_0_54( + .A(n_1_0_52), .B1(n_1_0_637), .B2(registers_31__ap[2]), .C1(registers_16__ap[2]), + .C2(n_1_0_614), .ZN(n_1_0_51) + ); + AOI222_X1_LVT i_1_0_53( + .A1(registers_8__ap[2]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[2]), + .C1(n_1_0_622), .C2(registers_30__ap[2]), .ZN(n_1_0_50) + ); + NAND3_X1_LVT i_1_0_52( + .A1(n_1_0_55), .A2(n_1_0_51), .A3(n_1_0_50), .ZN(n_1_0_49) + ); + AOI221_X1_LVT i_1_0_51( + .A(n_1_0_49), .B1(n_1_0_638), .B2(registers_4__ap[2]), .C1(registers_28__ap[2]), + .C2(n_1_0_634), .ZN(n_1_0_48) + ); + AOI22_X1_LVT i_1_0_50( + .A1(registers_18__ap[2]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[2]), + .ZN(n_1_0_47) + ); + AOI22_X1_LVT i_1_0_49( + .A1(registers_12__ap[2]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[2]), + .ZN(n_1_0_46) + ); + AOI22_X1_LVT i_1_0_48( + .A1(registers_22__ap[2]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[2]), + .ZN(n_1_0_45) + ); + NAND3_X1_LVT i_1_0_47( + .A1(n_1_0_47), .A2(n_1_0_46), .A3(n_1_0_45), .ZN(n_1_0_44) + ); + AOI221_X1_LVT i_1_0_46( + .A(n_1_0_44), .B1(n_1_0_629), .B2(registers_17__ap[2]), .C1(registers_20__ap[2]), + .C2(n_1_0_613), .ZN(n_1_0_43) + ); + AOI22_X1_LVT i_1_0_45( + .A1(registers_13__ap[2]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[2]), + .ZN(n_1_0_42) + ); + AOI22_X1_LVT i_1_0_44( + .A1(registers_7__ap[2]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[2]), + .ZN(n_1_0_41) + ); + AOI22_X1_LVT i_1_0_43( + .A1(registers_19__ap[2]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[2]), + .ZN(n_1_0_40) + ); + NAND3_X1_LVT i_1_0_42( + .A1(n_1_0_42), .A2(n_1_0_41), .A3(n_1_0_40), .ZN(n_1_0_39) + ); + AOI221_X1_LVT i_1_0_41( + .A(n_1_0_39), .B1(n_1_0_618), .B2(registers_2__ap[2]), .C1(registers_11__ap[2]), + .C2(n_1_0_611), .ZN(n_1_0_38) + ); + NAND3_X1_LVT i_1_0_40( + .A1(n_1_0_48), .A2(n_1_0_43), .A3(n_1_0_38), .ZN(RRs2[2]) + ); + AOI22_X1_LVT i_1_0_38( + .A1(registers_29__ap[1]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[1]), + .ZN(n_1_0_36) + ); + AOI22_X1_LVT i_1_0_39( + .A1(registers_16__ap[1]), .A2(n_1_0_614), .B1(n_1_0_610), .B2(registers_3__ap[1]), + .ZN(n_1_0_37) + ); + AOI22_X1_LVT i_1_0_37( + .A1(registers_1__ap[1]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[1]), + .ZN(n_1_0_35) + ); + AOI22_X1_LVT i_1_0_36( + .A1(registers_31__ap[1]), .A2(n_1_0_637), .B1(n_1_0_635), .B2(registers_5__ap[1]), + .ZN(n_1_0_34) + ); + NAND3_X1_LVT i_1_0_35( + .A1(n_1_0_37), .A2(n_1_0_35), .A3(n_1_0_34), .ZN(n_1_0_33) + ); + AOI221_X1_LVT i_1_0_34( + .A(n_1_0_33), .B1(n_1_0_627), .B2(registers_15__ap[1]), .C1(registers_23__ap[1]), + .C2(n_1_0_615), .ZN(n_1_0_32) + ); + AOI222_X1_LVT i_1_0_33( + .A1(registers_26__ap[1]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[1]), + .C1(n_1_0_626), .C2(registers_8__ap[1]), .ZN(n_1_0_31) + ); + NAND3_X1_LVT i_1_0_32( + .A1(n_1_0_36), .A2(n_1_0_32), .A3(n_1_0_31), .ZN(n_1_0_30) + ); + AOI221_X1_LVT i_1_0_31( + .A(n_1_0_30), .B1(n_1_0_629), .B2(registers_17__ap[1]), .C1(registers_28__ap[1]), + .C2(n_1_0_634), .ZN(n_1_0_29) + ); + AOI22_X1_LVT i_1_0_30( + .A1(registers_18__ap[1]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[1]), + .ZN(n_1_0_28) + ); + AOI22_X1_LVT i_1_0_29( + .A1(registers_4__ap[1]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[1]), + .ZN(n_1_0_27) + ); + AOI22_X1_LVT i_1_0_28( + .A1(registers_22__ap[1]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[1]), + .ZN(n_1_0_26) + ); + NAND3_X1_LVT i_1_0_27( + .A1(n_1_0_28), .A2(n_1_0_27), .A3(n_1_0_26), .ZN(n_1_0_25) + ); + AOI221_X1_LVT i_1_0_26( + .A(n_1_0_25), .B1(n_1_0_632), .B2(registers_12__ap[1]), .C1(registers_24__ap[1]), + .C2(n_1_0_621), .ZN(n_1_0_24) + ); + AOI22_X1_LVT i_1_0_25( + .A1(registers_13__ap[1]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[1]), + .ZN(n_1_0_23) + ); + AOI22_X1_LVT i_1_0_24( + .A1(registers_7__ap[1]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[1]), + .ZN(n_1_0_22) + ); + AOI22_X1_LVT i_1_0_23( + .A1(registers_19__ap[1]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[1]), + .ZN(n_1_0_21) + ); + NAND3_X1_LVT i_1_0_22( + .A1(n_1_0_23), .A2(n_1_0_22), .A3(n_1_0_21), .ZN(n_1_0_20) + ); + AOI221_X1_LVT i_1_0_21( + .A(n_1_0_20), .B1(n_1_0_611), .B2(registers_11__ap[1]), .C1(registers_27__ap[1]), + .C2(n_1_0_636), .ZN(n_1_0_19) + ); + NAND3_X1_LVT i_1_0_20( + .A1(n_1_0_29), .A2(n_1_0_24), .A3(n_1_0_19), .ZN(RRs2[1]) + ); + AOI22_X1_LVT i_1_0_19( + .A1(registers_4__ap[0]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[0]), + .ZN(n_1_0_18) + ); + AOI222_X1_LVT i_1_0_18( + .A1(registers_8__ap[0]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[0]), + .C1(n_1_0_622), .C2(registers_30__ap[0]), .ZN(n_1_0_17) + ); + AOI22_X1_LVT i_1_0_17( + .A1(registers_29__ap[0]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[0]), + .ZN(n_1_0_16) + ); + AOI22_X1_LVT i_1_0_16( + .A1(registers_1__ap[0]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[0]), + .ZN(n_1_0_15) + ); + AOI22_X1_LVT i_1_0_15( + .A1(registers_27__ap[0]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[0]), + .ZN(n_1_0_14) + ); + AOI22_X1_LVT i_1_0_14( + .A1(registers_23__ap[0]), .A2(n_1_0_615), .B1(n_1_0_614), .B2(registers_16__ap[0]), + .ZN(n_1_0_13) + ); + AOI22_X1_LVT i_1_0_13( + .A1(registers_31__ap[0]), .A2(n_1_0_637), .B1(n_1_0_635), .B2(registers_5__ap[0]), + .ZN(n_1_0_12) + ); + NAND4_X1_LVT i_1_0_12( + .A1(n_1_0_15), .A2(n_1_0_14), .A3(n_1_0_13), .A4(n_1_0_12), .ZN(n_1_0_11) + ); + AOI22_X1_LVT i_1_0_11( + .A1(registers_18__ap[0]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[0]), + .ZN(n_1_0_10) + ); + AOI22_X1_LVT i_1_0_10( + .A1(registers_12__ap[0]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[0]), + .ZN(n_1_0_9) + ); + AOI22_X1_LVT i_1_0_9( + .A1(registers_22__ap[0]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[0]), + .ZN(n_1_0_8) + ); + AOI22_X1_LVT i_1_0_8( + .A1(registers_17__ap[0]), .A2(n_1_0_629), .B1(n_1_0_613), .B2(registers_20__ap[0]), + .ZN(n_1_0_7) + ); + NAND4_X1_LVT i_1_0_7( + .A1(n_1_0_10), .A2(n_1_0_9), .A3(n_1_0_8), .A4(n_1_0_7), .ZN(n_1_0_6) + ); + AOI22_X1_LVT i_1_0_6( + .A1(registers_13__ap[0]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[0]), + .ZN(n_1_0_5) + ); + AOI22_X1_LVT i_1_0_5( + .A1(registers_7__ap[0]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[0]), + .ZN(n_1_0_4) + ); + AOI22_X1_LVT i_1_0_4( + .A1(registers_19__ap[0]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[0]), + .ZN(n_1_0_3) + ); + AOI22_X1_LVT i_1_0_3( + .A1(registers_2__ap[0]), .A2(n_1_0_618), .B1(n_1_0_611), .B2(registers_11__ap[0]), + .ZN(n_1_0_2) + ); + NAND4_X1_LVT i_1_0_2( + .A1(n_1_0_5), .A2(n_1_0_4), .A3(n_1_0_3), .A4(n_1_0_2), .ZN(n_1_0_1) + ); + NOR3_X1_LVT i_1_0_1( + .A1(n_1_0_11), .A2(n_1_0_6), .A3(n_1_0_1), .ZN(n_1_0_0) + ); + NAND4_X1_LVT i_1_0_0( + .A1(n_1_0_18), .A2(n_1_0_17), .A3(n_1_0_16), .A4(n_1_0_0), .ZN(RRs2[0]) + ); + DLL_X2_LVT ts_lockup_latchn_clkc2_intno1050_i( + .D(registers_1__ap[0]), .GN(n_0_0), .Q(ts_no1050) + ); + DLL_X2_LVT ts_lockup_latchn_clkc4_intno1051_i( + .D(registers_6__ap[0]), .GN(n_0_36), .Q(ts_no1051) + ); + DLL_X2_LVT ts_lockup_latchn_clkc3_intno1053_i( + .D(registers_27__ap[0]), .GN(n_0_57), .Q(ts_no1053) + ); + DLL_X2_LVT ts_lockup_latchn_clkc1_intno1054_i( + .D(registers_11__ap[0]), .GN(n_0_41), .Q(ts_no1054) + ); + CLKBUF_X3_LVT tessent_persistent_cell_buf_extsi1227_i( + .A(ts_extsi1227), .Z(ts_pbuf_extsi1227_) + ); + CLKBUF_X3_LVT tessent_persistent_cell_buf_extsi1228_i( + .A(ts_extsi1228), .Z(ts_pbuf_extsi1228_) + ); + CLKBUF_X3_LVT tessent_persistent_cell_buf_extsi1226_i( + .A(ts_extsi1226), .Z(ts_pbuf_extsi1226_) + ); +endmodule + +module cpu(led, btn, clk_25mhz, scan_en, SI_1, SO_1, SI_2, SO_2, SI_3, SO_3, SI_4, + SO_4); + input [6:0] btn; + input clk_25mhz, scan_en, SI_1, SI_2, SI_3, SI_4; + output [7:0] led; + output SO_1, SO_2, SO_3, SO_4; + + wire [31:0] Instruction, RData, RRs2, RRs1, WRd, DAddr, JumpOrBranchPC, + CurrentPC, NextPC; + wire [1:0] DWidth; + wire WrReg, JumpOrBranch, thePC_n_1, thePC_i_0_n_0, thePC_n_2, thePC_i_0_n_1, + thePC_n_3, thePC_i_0_n_2, thePC_n_4, thePC_i_0_n_3, thePC_n_5, + thePC_i_0_n_4, thePC_n_6, thePC_i_0_n_5, thePC_n_7, thePC_i_0_n_6, + thePC_n_8, thePC_i_0_n_7, thePC_n_9, thePC_i_0_n_8, thePC_n_10, + thePC_i_0_n_9, thePC_n_11, thePC_i_0_n_10, thePC_n_12, thePC_i_0_n_11, + thePC_n_13, thePC_i_0_n_12, thePC_n_14, thePC_i_0_n_13, thePC_n_15, + thePC_i_0_n_14, thePC_n_16, thePC_i_0_n_15, thePC_n_17, thePC_i_0_n_16, + thePC_n_18, thePC_i_0_n_17, thePC_n_19, thePC_i_0_n_18, thePC_n_20, + thePC_i_0_n_19, thePC_n_21, thePC_i_0_n_20, thePC_n_22, thePC_i_0_n_21, + thePC_n_23, thePC_i_0_n_22, thePC_n_24, thePC_i_0_n_23, thePC_n_25, + thePC_i_0_n_24, thePC_n_26, thePC_i_0_n_25, thePC_n_27, thePC_i_0_n_26, + thePC_n_28, thePC_i_0_n_27, thePC_n_29, thePC_n_0, thePC_n_30, n_0_0_0, + thePC_n_31, n_0_0_1, thePC_n_32, thePC_n_33, thePC_n_34, thePC_n_35, + thePC_n_36, thePC_n_37, thePC_n_38, thePC_n_39, thePC_n_40, thePC_n_41, + thePC_n_42, thePC_n_43, n_0_0_2, thePC_n_44, n_0_0_3, thePC_n_45, + n_0_0_4, thePC_n_46, n_0_0_5, thePC_n_47, n_0_0_6, thePC_n_48, n_0_0_7, + thePC_n_49, n_0_0_8, thePC_n_50, n_0_0_9, thePC_n_51, n_0_0_10, + thePC_n_52, n_0_0_11, thePC_n_53, n_0_0_12, thePC_n_54, n_0_0_13, + thePC_n_55, n_0_0_14, thePC_n_56, n_0_0_15, thePC_n_57, n_0_0_16, + thePC_n_58, n_0_0_17, thePC_n_59, n_0_0_18, thePC_n_60, n_0_0_19, + thePC_n_61, n_0_0_20, n_0_0_21, n_0_0_22, reset, uc_0, uc_1, uc_2, uc_3, + uc_4, uc_5, uc_6, uc_7, uc_8, uc_9, uc_10, uc_11, uc_12, uc_13, uc_14, + uc_15, uc_16, uc_17, uc_18, uc_19, uc_20, uc_21, uc_22, uc_23, uc_24, + uc_25, uc_26, uc_27, uc_28, uc_29, uc_30, uc_31, uc_32, uc_33, uc_34, + uc_35, uc_36, uc_37, uc_38, uc_39, uc_40, uc_41, uc_42, uc_43, uc_44, + uc_45, uc_46, uc_47, uc_48, uc_49, uc_50, uc_51, uc_52, uc_53, uc_54, + uc_55, uc_56, uc_57, uc_58, ts_pbuf_extsi1225_, ts_no1054, ts_no1050, + ts_no1053, ts_no1051; + + assign SO_1 = ts_no1054; + assign SO_2 = ts_no1050; + assign SO_3 = ts_no1053; + assign SO_4 = ts_no1051; + AND2_X1_LVT i_0_0_54( + .A1(JumpOrBranch), .A2(btn[0]), .ZN(n_0_0_22) + ); + INV_X1_LVT i_0_0_66( + .A(btn[0]), .ZN(reset) + ); + NOR2_X1_LVT i_0_0_53( + .A1(reset), .A2(JumpOrBranch), .ZN(n_0_0_21) + ); + AOI22_X1_LVT i_0_0_50( + .A1(JumpOrBranchPC[30]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_28), .ZN(n_0_0_19) + ); + INV_X1_LVT i_0_0_49( + .A(n_0_0_19), .ZN(thePC_n_60) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[30] ( + .CK(clk_25mhz), .D(thePC_n_60), .Q(CurrentPC[30]), .QN(), .SE(scan_en), .SI(ts_pbuf_extsi1225_) + ); + AOI22_X1_LVT i_0_0_48( + .A1(JumpOrBranchPC[29]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_27), .ZN(n_0_0_18) + ); + INV_X1_LVT i_0_0_47( + .A(n_0_0_18), .ZN(thePC_n_59) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[29] ( + .CK(clk_25mhz), .D(thePC_n_59), .Q(CurrentPC[29]), .QN(), .SE(scan_en), .SI(CurrentPC[30]) + ); + AOI22_X1_LVT i_0_0_46( + .A1(JumpOrBranchPC[28]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_26), .ZN(n_0_0_17) + ); + INV_X1_LVT i_0_0_45( + .A(n_0_0_17), .ZN(thePC_n_58) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[28] ( + .CK(clk_25mhz), .D(thePC_n_58), .Q(CurrentPC[28]), .QN(), .SE(scan_en), .SI(CurrentPC[29]) + ); + AOI22_X1_LVT i_0_0_44( + .A1(JumpOrBranchPC[27]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_25), .ZN(n_0_0_16) + ); + INV_X1_LVT i_0_0_43( + .A(n_0_0_16), .ZN(thePC_n_57) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[27] ( + .CK(clk_25mhz), .D(thePC_n_57), .Q(CurrentPC[27]), .QN(), .SE(scan_en), .SI(CurrentPC[28]) + ); + AOI22_X1_LVT i_0_0_42( + .A1(JumpOrBranchPC[26]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_24), .ZN(n_0_0_15) + ); + INV_X1_LVT i_0_0_41( + .A(n_0_0_15), .ZN(thePC_n_56) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[26] ( + .CK(clk_25mhz), .D(thePC_n_56), .Q(CurrentPC[26]), .QN(), .SE(scan_en), .SI(CurrentPC[27]) + ); + AOI22_X1_LVT i_0_0_40( + .A1(JumpOrBranchPC[25]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_23), .ZN(n_0_0_14) + ); + INV_X1_LVT i_0_0_39( + .A(n_0_0_14), .ZN(thePC_n_55) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[25] ( + .CK(clk_25mhz), .D(thePC_n_55), .Q(CurrentPC[25]), .QN(), .SE(scan_en), .SI(CurrentPC[26]) + ); + AOI22_X1_LVT i_0_0_38( + .A1(JumpOrBranchPC[24]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_22), .ZN(n_0_0_13) + ); + INV_X1_LVT i_0_0_37( + .A(n_0_0_13), .ZN(thePC_n_54) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[24] ( + .CK(clk_25mhz), .D(thePC_n_54), .Q(CurrentPC[24]), .QN(), .SE(scan_en), .SI(CurrentPC[25]) + ); + AOI22_X1_LVT i_0_0_36( + .A1(JumpOrBranchPC[23]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_21), .ZN(n_0_0_12) + ); + INV_X1_LVT i_0_0_35( + .A(n_0_0_12), .ZN(thePC_n_53) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[23] ( + .CK(clk_25mhz), .D(thePC_n_53), .Q(CurrentPC[23]), .QN(), .SE(scan_en), .SI(CurrentPC[24]) + ); + AOI22_X1_LVT i_0_0_34( + .A1(JumpOrBranchPC[22]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_20), .ZN(n_0_0_11) + ); + INV_X1_LVT i_0_0_33( + .A(n_0_0_11), .ZN(thePC_n_52) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[22] ( + .CK(clk_25mhz), .D(thePC_n_52), .Q(CurrentPC[22]), .QN(), .SE(scan_en), .SI(CurrentPC[23]) + ); + AOI22_X1_LVT i_0_0_32( + .A1(JumpOrBranchPC[21]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_19), .ZN(n_0_0_10) + ); + INV_X1_LVT i_0_0_31( + .A(n_0_0_10), .ZN(thePC_n_51) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[21] ( + .CK(clk_25mhz), .D(thePC_n_51), .Q(CurrentPC[21]), .QN(), .SE(scan_en), .SI(CurrentPC[22]) + ); + AOI22_X1_LVT i_0_0_30( + .A1(JumpOrBranchPC[20]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_18), .ZN(n_0_0_9) + ); + INV_X1_LVT i_0_0_29( + .A(n_0_0_9), .ZN(thePC_n_50) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[20] ( + .CK(clk_25mhz), .D(thePC_n_50), .Q(CurrentPC[20]), .QN(), .SE(scan_en), .SI(CurrentPC[21]) + ); + AOI22_X1_LVT i_0_0_28( + .A1(JumpOrBranchPC[19]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_17), .ZN(n_0_0_8) + ); + INV_X1_LVT i_0_0_27( + .A(n_0_0_8), .ZN(thePC_n_49) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[19] ( + .CK(clk_25mhz), .D(thePC_n_49), .Q(CurrentPC[19]), .QN(), .SE(scan_en), .SI(CurrentPC[20]) + ); + AOI22_X1_LVT i_0_0_26( + .A1(JumpOrBranchPC[18]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_16), .ZN(n_0_0_7) + ); + INV_X1_LVT i_0_0_25( + .A(n_0_0_7), .ZN(thePC_n_48) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[18] ( + .CK(clk_25mhz), .D(thePC_n_48), .Q(CurrentPC[18]), .QN(), .SE(scan_en), .SI(CurrentPC[19]) + ); + AOI22_X1_LVT i_0_0_24( + .A1(JumpOrBranchPC[17]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_15), .ZN(n_0_0_6) + ); + INV_X1_LVT i_0_0_23( + .A(n_0_0_6), .ZN(thePC_n_47) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[17] ( + .CK(clk_25mhz), .D(thePC_n_47), .Q(CurrentPC[17]), .QN(), .SE(scan_en), .SI(CurrentPC[18]) + ); + AOI22_X1_LVT i_0_0_22( + .A1(JumpOrBranchPC[16]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_14), .ZN(n_0_0_5) + ); + INV_X1_LVT i_0_0_21( + .A(n_0_0_5), .ZN(thePC_n_46) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[16] ( + .CK(clk_25mhz), .D(thePC_n_46), .Q(CurrentPC[16]), .QN(), .SE(scan_en), .SI(CurrentPC[17]) + ); + AOI22_X1_LVT i_0_0_20( + .A1(JumpOrBranchPC[15]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_13), .ZN(n_0_0_4) + ); + INV_X1_LVT i_0_0_19( + .A(n_0_0_4), .ZN(thePC_n_45) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[15] ( + .CK(clk_25mhz), .D(thePC_n_45), .Q(CurrentPC[15]), .QN(), .SE(scan_en), .SI(CurrentPC[16]) + ); + AOI22_X1_LVT i_0_0_18( + .A1(JumpOrBranchPC[14]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_12), .ZN(n_0_0_3) + ); + INV_X1_LVT i_0_0_17( + .A(n_0_0_3), .ZN(thePC_n_44) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[14] ( + .CK(clk_25mhz), .D(thePC_n_44), .Q(CurrentPC[14]), .QN(), .SE(scan_en), .SI(CurrentPC[15]) + ); + AOI22_X1_LVT i_0_0_16( + .A1(JumpOrBranchPC[13]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_11), .ZN(n_0_0_2) + ); + INV_X1_LVT i_0_0_15( + .A(n_0_0_2), .ZN(thePC_n_43) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[13] ( + .CK(clk_25mhz), .D(thePC_n_43), .Q(CurrentPC[13]), .QN(), .SE(scan_en), .SI(CurrentPC[14]) + ); + MUX2_X1_LVT i_0_0_65( + .A(thePC_n_10), .B(JumpOrBranchPC[12]), .S(JumpOrBranch), .Z(NextPC[12]) + ); + AND2_X1_LVT i_0_0_14( + .A1(NextPC[12]), .A2(btn[0]), .ZN(thePC_n_42) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[12] ( + .CK(clk_25mhz), .D(thePC_n_42), .Q(CurrentPC[12]), .QN(), .SE(scan_en), .SI(CurrentPC[13]) + ); + MUX2_X1_LVT i_0_0_64( + .A(thePC_n_9), .B(JumpOrBranchPC[11]), .S(JumpOrBranch), .Z(NextPC[11]) + ); + AND2_X1_LVT i_0_0_13( + .A1(NextPC[11]), .A2(btn[0]), .ZN(thePC_n_41) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[11] ( + .CK(clk_25mhz), .D(thePC_n_41), .Q(CurrentPC[11]), .QN(), .SE(scan_en), .SI(CurrentPC[12]) + ); + MUX2_X1_LVT i_0_0_63( + .A(thePC_n_8), .B(JumpOrBranchPC[10]), .S(JumpOrBranch), .Z(NextPC[10]) + ); + AND2_X1_LVT i_0_0_12( + .A1(NextPC[10]), .A2(btn[0]), .ZN(thePC_n_40) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[10] ( + .CK(clk_25mhz), .D(thePC_n_40), .Q(CurrentPC[10]), .QN(), .SE(scan_en), .SI(CurrentPC[11]) + ); + MUX2_X1_LVT i_0_0_62( + .A(thePC_n_7), .B(JumpOrBranchPC[9]), .S(JumpOrBranch), .Z(NextPC[9]) + ); + AND2_X1_LVT i_0_0_11( + .A1(NextPC[9]), .A2(btn[0]), .ZN(thePC_n_39) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[9] ( + .CK(clk_25mhz), .D(thePC_n_39), .Q(CurrentPC[9]), .QN(), .SE(scan_en), .SI(CurrentPC[10]) + ); + MUX2_X1_LVT i_0_0_61( + .A(thePC_n_6), .B(JumpOrBranchPC[8]), .S(JumpOrBranch), .Z(NextPC[8]) + ); + AND2_X1_LVT i_0_0_10( + .A1(NextPC[8]), .A2(btn[0]), .ZN(thePC_n_38) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[8] ( + .CK(clk_25mhz), .D(thePC_n_38), .Q(CurrentPC[8]), .QN(), .SE(scan_en), .SI(CurrentPC[9]) + ); + AND2_X1_LVT i_0_0_9( + .A1(led[7]), .A2(btn[0]), .ZN(thePC_n_37) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[7] ( + .CK(clk_25mhz), .D(thePC_n_37), .Q(CurrentPC[7]), .QN(), .SE(scan_en), .SI(CurrentPC[8]) + ); + MUX2_X1_LVT i_0_0_59( + .A(thePC_n_4), .B(JumpOrBranchPC[6]), .S(JumpOrBranch), .Z(led[6]) + ); + AND2_X1_LVT i_0_0_8( + .A1(led[6]), .A2(btn[0]), .ZN(thePC_n_36) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[6] ( + .CK(clk_25mhz), .D(thePC_n_36), .Q(CurrentPC[6]), .QN(), .SE(scan_en), .SI(CurrentPC[7]) + ); + MUX2_X1_LVT i_0_0_58( + .A(thePC_n_3), .B(JumpOrBranchPC[5]), .S(JumpOrBranch), .Z(led[5]) + ); + AND2_X1_LVT i_0_0_7( + .A1(led[5]), .A2(btn[0]), .ZN(thePC_n_35) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[5] ( + .CK(clk_25mhz), .D(thePC_n_35), .Q(CurrentPC[5]), .QN(), .SE(scan_en), .SI(CurrentPC[6]) + ); + MUX2_X1_LVT i_0_0_57( + .A(thePC_n_2), .B(JumpOrBranchPC[4]), .S(JumpOrBranch), .Z(led[4]) + ); + AND2_X1_LVT i_0_0_6( + .A1(led[4]), .A2(btn[0]), .ZN(thePC_n_34) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[4] ( + .CK(clk_25mhz), .D(thePC_n_34), .Q(CurrentPC[4]), .QN(), .SE(scan_en), .SI(CurrentPC[5]) + ); + MUX2_X1_LVT i_0_0_56( + .A(thePC_n_1), .B(JumpOrBranchPC[3]), .S(JumpOrBranch), .Z(led[3]) + ); + AND2_X1_LVT i_0_0_5( + .A1(led[3]), .A2(btn[0]), .ZN(thePC_n_33) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[3] ( + .CK(clk_25mhz), .D(thePC_n_33), .Q(CurrentPC[3]), .QN(), .SE(scan_en), .SI(CurrentPC[4]) + ); + INV_X1_LVT thePC_i_0_29( + .A(CurrentPC[2]), .ZN(thePC_n_0) + ); + MUX2_X1_LVT i_0_0_55( + .A(thePC_n_0), .B(JumpOrBranchPC[2]), .S(JumpOrBranch), .Z(led[2]) + ); + AND2_X1_LVT i_0_0_4( + .A1(led[2]), .A2(btn[0]), .ZN(thePC_n_32) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[2] ( + .CK(clk_25mhz), .D(thePC_n_32), .Q(CurrentPC[2]), .QN(), .SE(scan_en), .SI(CurrentPC[3]) + ); + HA_X1_LVT thePC_i_0_0( + .A(CurrentPC[3]), .B(CurrentPC[2]), .CO(thePC_i_0_n_0), .S(thePC_n_1) + ); + HA_X1_LVT thePC_i_0_1( + .A(CurrentPC[4]), .B(thePC_i_0_n_0), .CO(thePC_i_0_n_1), .S(thePC_n_2) + ); + HA_X1_LVT thePC_i_0_2( + .A(CurrentPC[5]), .B(thePC_i_0_n_1), .CO(thePC_i_0_n_2), .S(thePC_n_3) + ); + HA_X1_LVT thePC_i_0_3( + .A(CurrentPC[6]), .B(thePC_i_0_n_2), .CO(thePC_i_0_n_3), .S(thePC_n_4) + ); + HA_X1_LVT thePC_i_0_4( + .A(CurrentPC[7]), .B(thePC_i_0_n_3), .CO(thePC_i_0_n_4), .S(thePC_n_5) + ); + HA_X1_LVT thePC_i_0_5( + .A(CurrentPC[8]), .B(thePC_i_0_n_4), .CO(thePC_i_0_n_5), .S(thePC_n_6) + ); + HA_X1_LVT thePC_i_0_6( + .A(CurrentPC[9]), .B(thePC_i_0_n_5), .CO(thePC_i_0_n_6), .S(thePC_n_7) + ); + HA_X1_LVT thePC_i_0_7( + .A(CurrentPC[10]), .B(thePC_i_0_n_6), .CO(thePC_i_0_n_7), .S(thePC_n_8) + ); + HA_X1_LVT thePC_i_0_8( + .A(CurrentPC[11]), .B(thePC_i_0_n_7), .CO(thePC_i_0_n_8), .S(thePC_n_9) + ); + HA_X1_LVT thePC_i_0_9( + .A(CurrentPC[12]), .B(thePC_i_0_n_8), .CO(thePC_i_0_n_9), .S(thePC_n_10) + ); + HA_X1_LVT thePC_i_0_11( + .A(CurrentPC[13]), .B(thePC_i_0_n_9), .CO(thePC_i_0_n_10), .S(thePC_n_11) + ); + HA_X1_LVT thePC_i_0_12( + .A(CurrentPC[14]), .B(thePC_i_0_n_10), .CO(thePC_i_0_n_11), .S(thePC_n_12) + ); + HA_X1_LVT thePC_i_0_13( + .A(CurrentPC[15]), .B(thePC_i_0_n_11), .CO(thePC_i_0_n_12), .S(thePC_n_13) + ); + HA_X1_LVT thePC_i_0_14( + .A(CurrentPC[16]), .B(thePC_i_0_n_12), .CO(thePC_i_0_n_13), .S(thePC_n_14) + ); + HA_X1_LVT thePC_i_0_15( + .A(CurrentPC[17]), .B(thePC_i_0_n_13), .CO(thePC_i_0_n_14), .S(thePC_n_15) + ); + HA_X1_LVT thePC_i_0_16( + .A(CurrentPC[18]), .B(thePC_i_0_n_14), .CO(thePC_i_0_n_15), .S(thePC_n_16) + ); + HA_X1_LVT thePC_i_0_17( + .A(CurrentPC[19]), .B(thePC_i_0_n_15), .CO(thePC_i_0_n_16), .S(thePC_n_17) + ); + HA_X1_LVT thePC_i_0_10( + .A(CurrentPC[20]), .B(thePC_i_0_n_16), .CO(thePC_i_0_n_17), .S(thePC_n_18) + ); + HA_X1_LVT thePC_i_0_18( + .A(CurrentPC[21]), .B(thePC_i_0_n_17), .CO(thePC_i_0_n_18), .S(thePC_n_19) + ); + HA_X1_LVT thePC_i_0_19( + .A(CurrentPC[22]), .B(thePC_i_0_n_18), .CO(thePC_i_0_n_19), .S(thePC_n_20) + ); + HA_X1_LVT thePC_i_0_20( + .A(CurrentPC[23]), .B(thePC_i_0_n_19), .CO(thePC_i_0_n_20), .S(thePC_n_21) + ); + HA_X1_LVT thePC_i_0_21( + .A(CurrentPC[24]), .B(thePC_i_0_n_20), .CO(thePC_i_0_n_21), .S(thePC_n_22) + ); + HA_X1_LVT thePC_i_0_22( + .A(CurrentPC[25]), .B(thePC_i_0_n_21), .CO(thePC_i_0_n_22), .S(thePC_n_23) + ); + HA_X1_LVT thePC_i_0_23( + .A(CurrentPC[26]), .B(thePC_i_0_n_22), .CO(thePC_i_0_n_23), .S(thePC_n_24) + ); + HA_X1_LVT thePC_i_0_24( + .A(CurrentPC[27]), .B(thePC_i_0_n_23), .CO(thePC_i_0_n_24), .S(thePC_n_25) + ); + HA_X1_LVT thePC_i_0_25( + .A(CurrentPC[28]), .B(thePC_i_0_n_24), .CO(thePC_i_0_n_25), .S(thePC_n_26) + ); + HA_X1_LVT thePC_i_0_26( + .A(CurrentPC[29]), .B(thePC_i_0_n_25), .CO(thePC_i_0_n_26), .S(thePC_n_27) + ); + HA_X1_LVT thePC_i_0_27( + .A(CurrentPC[30]), .B(thePC_i_0_n_26), .CO(thePC_i_0_n_27), .S(thePC_n_28) + ); + XOR2_X1_LVT thePC_i_0_28( + .A(CurrentPC[31]), .B(thePC_i_0_n_27), .Z(thePC_n_29) + ); + AOI22_X1_LVT i_0_0_52( + .A1(JumpOrBranchPC[31]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_29), .ZN(n_0_0_20) + ); + INV_X1_LVT i_0_0_51( + .A(n_0_0_20), .ZN(thePC_n_61) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[31] ( + .CK(clk_25mhz), .D(thePC_n_61), .Q(CurrentPC[31]), .QN(), .SE(scan_en), .SI(CurrentPC[2]) + ); + AOI22_X1_LVT i_0_0_3( + .A1(JumpOrBranchPC[1]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(CurrentPC[1]), + .ZN(n_0_0_1) + ); + INV_X1_LVT i_0_0_2( + .A(n_0_0_1), .ZN(thePC_n_31) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[1] ( + .CK(clk_25mhz), .D(thePC_n_31), .Q(CurrentPC[1]), .QN(), .SE(scan_en), .SI(CurrentPC[31]) + ); + AOI22_X1_LVT i_0_0_1( + .A1(JumpOrBranchPC[0]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(CurrentPC[0]), + .ZN(n_0_0_0) + ); + INV_X1_LVT i_0_0_0( + .A(n_0_0_0), .ZN(thePC_n_30) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[0] ( + .CK(clk_25mhz), .D(thePC_n_30), .Q(CurrentPC[0]), .QN(), .SE(scan_en), .SI(CurrentPC[1]) + ); + reg_file theRegisters( + .Rs1({Instruction[19], Instruction[18], Instruction[17], + Instruction[16], Instruction[15]}), .Rs2({Instruction[24], + Instruction[23], Instruction[22], Instruction[21], Instruction[20]}), .Rd({ + Instruction[11], Instruction[10], Instruction[9], Instruction[8], + Instruction[7]}), .RRs1(RRs1), .RRs2(RRs2), .WRd(WRd), .WrReg(WrReg), .reset(reset), + .clk(clk_25mhz), .dftIn(scan_en), .ts_intno31(CurrentPC[0]), .ts_no1050(ts_no1050), + .ts_no1051(ts_no1051), .ts_no1053(ts_no1053), .ts_no1054(ts_no1054), .ts_extsi1226(SI_2), + .ts_extsi1227(SI_3), .ts_extsi1228(SI_4) + ); + main_mem theMem( + .clk(clk_25mhz), .reset(reset), .DAddr({uc_0, uc_1, uc_2, uc_3, uc_4, + uc_5, uc_6, uc_7, uc_8, uc_9, uc_10, uc_11, uc_12, uc_13, uc_14, uc_15, + uc_16, uc_17, uc_18, DAddr[12], DAddr[11], DAddr[10], DAddr[9], + DAddr[8], DAddr[7], DAddr[6], DAddr[5], DAddr[4], DAddr[3], DAddr[2], + DAddr[1], DAddr[0]}), .IAddr({uc_19, uc_20, uc_21, uc_22, uc_23, uc_24, + uc_25, uc_26, uc_27, uc_28, uc_29, uc_30, uc_31, uc_32, uc_33, uc_34, + uc_35, uc_36, uc_37, NextPC[12], NextPC[11], NextPC[10], NextPC[9], + NextPC[8], led[7], led[6], led[5], led[4], led[3], led[2], uc_38, uc_39}), + .DWData(RRs2), .DRData(RData), .IRData(Instruction), .DWE(led[1]), .DWidth(DWidth) + ); + decoder theDecoder( + .CurrentPC(CurrentPC), .JumpOrBranchPC(JumpOrBranchPC), .JumpOrBranch(JumpOrBranch), + .DAddr({uc_40, uc_41, uc_42, uc_43, uc_44, uc_45, uc_46, uc_47, uc_48, + uc_49, uc_50, uc_51, uc_52, uc_53, uc_54, uc_55, uc_56, uc_57, uc_58, + DAddr[12], DAddr[11], DAddr[10], DAddr[9], DAddr[8], DAddr[7], DAddr[6], + DAddr[5], DAddr[4], DAddr[3], DAddr[2], DAddr[1], DAddr[0]}), .WData(), .RData(RData), + .Instruction(Instruction), .WrMem(led[1]), .DWidth(DWidth), .Rs1(), .Rs2(), + .Rd(), .RRs1(RRs1), .RRs2(RRs2), .WRd(WRd), .WrReg(WrReg), .Illegal(led[0]) + ); + MUX2_X1_LVT i_0_0_60( + .A(thePC_n_5), .B(JumpOrBranchPC[7]), .S(JumpOrBranch), .Z(led[7]) + ); + CLKBUF_X3_LVT tessent_persistent_cell_buf_extsi1225_i( + .A(SI_1), .Z(ts_pbuf_extsi1225_) + ); +endmodule + diff --git a/oasys.tessent.00/tsdb_outdir/logic_test_cores/cpu_Scan_0.logic_test_core/cpu.atpg_mode_unwrapped/cpu_unwrapped.flat.gz b/oasys.tessent.00/tsdb_outdir/logic_test_cores/cpu_Scan_0.logic_test_core/cpu.atpg_mode_unwrapped/cpu_unwrapped.flat.gz new file mode 100644 index 0000000..81ffd4a Binary files /dev/null and b/oasys.tessent.00/tsdb_outdir/logic_test_cores/cpu_Scan_0.logic_test_core/cpu.atpg_mode_unwrapped/cpu_unwrapped.flat.gz differ diff --git a/oasys.tessent.00/tsdb_outdir/logic_test_cores/cpu_Scan_0.logic_test_core/cpu.atpg_mode_unwrapped/cpu_unwrapped.tcd.gz b/oasys.tessent.00/tsdb_outdir/logic_test_cores/cpu_Scan_0.logic_test_core/cpu.atpg_mode_unwrapped/cpu_unwrapped.tcd.gz new file mode 100644 index 0000000..81ec9c9 Binary files /dev/null and b/oasys.tessent.00/tsdb_outdir/logic_test_cores/cpu_Scan_0.logic_test_core/cpu.atpg_mode_unwrapped/cpu_unwrapped.tcd.gz differ diff --git a/oasys.tessent.00/tsdb_outdir/logic_test_cores/cpu_Scan_0.logic_test_core/cpu.atpg_mode_unwrapped/cpu_unwrapped_stuck.faults b/oasys.tessent.00/tsdb_outdir/logic_test_cores/cpu_Scan_0.logic_test_core/cpu.atpg_mode_unwrapped/cpu_unwrapped_stuck.faults new file mode 100644 index 0000000..4baeb94 --- /dev/null +++ b/oasys.tessent.00/tsdb_outdir/logic_test_cores/cpu_Scan_0.logic_test_core/cpu.atpg_mode_unwrapped/cpu_unwrapped_stuck.faults @@ -0,0 +1,39031 @@ +FaultInformation { + version : 1; + FaultType (Stuck) { + FaultList { + FaultCollapsing : FALSE; + Format : Identifier, Class, Location; + Instance ("") { + 0, UU, "/btn[6]"; + 1, UU, "/btn[6]"; + 0, UU, "/btn[5]"; + 1, UU, "/btn[5]"; + 0, UU, "/btn[4]"; + 1, UU, "/btn[4]"; + 0, UU, "/btn[3]"; + 1, UU, "/btn[3]"; + 0, UU, "/btn[2]"; + 1, UU, "/btn[2]"; + 0, UU, "/btn[1]"; + 1, UU, "/btn[1]"; + 0, AU, "/btn[0]"; + 1, AU, "/btn[0]"; + 0, DI.CLK, "/clk_25mhz"; + 1, DI.CLK, "/clk_25mhz"; + 0, DI.SEN, "/scan_en"; + 1, DS, "/scan_en"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[30] /SI"; + 0, EQ, "/tessent_persistent_cell_buf_extsi1225_i/Z"; + 0, EQ, "/tessent_persistent_cell_buf_extsi1225_i/A"; + 0, EQ, "/SI_1"; + 1, DI.SCAN, "/tessent_persistent_cell_buf_extsi1225_i/Z"; + 1, EQ, "/tessent_persistent_cell_buf_extsi1225_i/A"; + 1, EQ, "/SI_1"; + 1, EQ, "/\thePC_CurrentPC_reg[30] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[1][31] /SI"; + 0, EQ, "/theRegisters/tessent_persistent_cell_buf_extsi1226_i/Z"; + 0, EQ, "/theRegisters/tessent_persistent_cell_buf_extsi1226_i/A"; + 0, EQ, "/SI_2"; + 1, DI.SCAN, "/theRegisters/tessent_persistent_cell_buf_extsi1226_i/Z"; + 1, EQ, "/theRegisters/tessent_persistent_cell_buf_extsi1226_i/A"; + 1, EQ, "/SI_2"; + 1, EQ, "/theRegisters/\registers_reg[1][31] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[28][31] /SI"; + 0, EQ, "/theRegisters/tessent_persistent_cell_buf_extsi1227_i/Z"; + 0, EQ, "/theRegisters/tessent_persistent_cell_buf_extsi1227_i/A"; + 0, EQ, "/SI_3"; + 1, DI.SCAN, "/theRegisters/tessent_persistent_cell_buf_extsi1227_i/Z"; + 1, EQ, "/theRegisters/tessent_persistent_cell_buf_extsi1227_i/A"; + 1, EQ, "/SI_3"; + 1, EQ, "/theRegisters/\registers_reg[28][31] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[4][31] /SI"; + 0, EQ, "/theRegisters/tessent_persistent_cell_buf_extsi1228_i/Z"; + 0, EQ, "/theRegisters/tessent_persistent_cell_buf_extsi1228_i/A"; + 0, EQ, "/SI_4"; + 1, DI.SCAN, "/theRegisters/tessent_persistent_cell_buf_extsi1228_i/Z"; + 1, EQ, "/theRegisters/tessent_persistent_cell_buf_extsi1228_i/A"; + 1, EQ, "/SI_4"; + 1, EQ, "/theRegisters/\registers_reg[4][31] /SI"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[30] /Q"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[30] /Q"; + 0, UU, "/\thePC_CurrentPC_reg[30] /QN"; + 1, UU, "/\thePC_CurrentPC_reg[30] /QN"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[29] /Q"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[29] /Q"; + 0, UU, "/\thePC_CurrentPC_reg[29] /QN"; + 1, UU, "/\thePC_CurrentPC_reg[29] /QN"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[28] /Q"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[28] /Q"; + 0, UU, "/\thePC_CurrentPC_reg[28] /QN"; + 1, UU, "/\thePC_CurrentPC_reg[28] /QN"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[27] /Q"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[27] /Q"; + 0, UU, "/\thePC_CurrentPC_reg[27] /QN"; + 1, UU, "/\thePC_CurrentPC_reg[27] /QN"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[26] /Q"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[26] /Q"; + 0, UU, "/\thePC_CurrentPC_reg[26] /QN"; + 1, UU, "/\thePC_CurrentPC_reg[26] /QN"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[25] /Q"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[25] /Q"; + 0, UU, "/\thePC_CurrentPC_reg[25] /QN"; + 1, UU, "/\thePC_CurrentPC_reg[25] /QN"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[24] /Q"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[24] /Q"; + 0, UU, "/\thePC_CurrentPC_reg[24] /QN"; + 1, UU, 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/Q"; + 0, UU, "/\thePC_CurrentPC_reg[18] /QN"; + 1, UU, "/\thePC_CurrentPC_reg[18] /QN"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[17] /Q"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[17] /Q"; + 0, UU, "/\thePC_CurrentPC_reg[17] /QN"; + 1, UU, "/\thePC_CurrentPC_reg[17] /QN"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[16] /Q"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[16] /Q"; + 0, UU, "/\thePC_CurrentPC_reg[16] /QN"; + 1, UU, "/\thePC_CurrentPC_reg[16] /QN"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[15] /Q"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[15] /Q"; + 0, UU, "/\thePC_CurrentPC_reg[15] /QN"; + 1, UU, "/\thePC_CurrentPC_reg[15] /QN"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[14] /Q"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[14] /Q"; + 0, UU, "/\thePC_CurrentPC_reg[14] /QN"; + 1, UU, "/\thePC_CurrentPC_reg[14] /QN"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[13] /Q"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[13] /Q"; + 0, UU, "/\thePC_CurrentPC_reg[13] /QN"; + 1, UU, "/\thePC_CurrentPC_reg[13] /QN"; + 0, DI.SCAN, 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"/\thePC_CurrentPC_reg[31] /QN"; + 1, UU, "/\thePC_CurrentPC_reg[31] /QN"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[1] /Q"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[1] /Q"; + 0, UU, "/\thePC_CurrentPC_reg[1] /QN"; + 1, UU, "/\thePC_CurrentPC_reg[1] /QN"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[0] /Q"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[0] /Q"; + 0, UU, "/\thePC_CurrentPC_reg[0] /QN"; + 1, UU, "/\thePC_CurrentPC_reg[0] /QN"; + 0, DI.SCAN, "/theRegisters/\registers_reg[28][31] /Q"; + 1, DI.SCAN, "/theRegisters/\registers_reg[28][31] /Q"; + 0, UU, "/theRegisters/\registers_reg[28][31] /QN"; + 1, UU, "/theRegisters/\registers_reg[28][31] /QN"; + 0, DI.SCAN, "/theRegisters/\registers_reg[4][31] /Q"; + 1, DI.SCAN, "/theRegisters/\registers_reg[4][31] /Q"; + 0, UU, "/theRegisters/\registers_reg[4][31] /QN"; + 1, UU, "/theRegisters/\registers_reg[4][31] /QN"; + 0, DI.SCAN, "/theRegisters/\registers_reg[16][31] /Q"; + 1, DI.SCAN, "/theRegisters/\registers_reg[16][31] /Q"; + 0, UU, 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"/theRegisters/i_1_0_1328/ZN"; + 0, AU.BB, "/theRegisters/i_1_0_1328/A1"; + 0, AU.BB, "/theRegisters/i_1_0_1328/A2"; + 0, AU.BB, "/theRegisters/i_1_0_1335/ZN"; + 1, EQ, "/theRegisters/i_1_0_1335/A1"; + 1, EQ, "/theRegisters/i_1_0_1335/A2"; + 1, AU.BB, "/theRegisters/i_1_0_1335/ZN"; + 0, AU.BB, "/theRegisters/i_1_0_1335/A1"; + 0, AU.BB, "/theRegisters/i_1_0_1335/A2"; + 0, AU.BB, "/theRegisters/i_1_0_1346/ZN"; + 1, EQ, "/theRegisters/i_1_0_1346/A1"; + 1, EQ, "/theRegisters/i_1_0_1346/A2"; + 1, AU.BB, "/theRegisters/i_1_0_1346/ZN"; + 0, AU.BB, "/theRegisters/i_1_0_1346/A1"; + 0, AU.BB, "/theRegisters/i_1_0_1346/A2"; + 0, AU.BB, "/theRegisters/i_1_0_1338/ZN"; + 1, EQ, "/theRegisters/i_1_0_1338/A1"; + 1, EQ, "/theRegisters/i_1_0_1338/A2"; + 1, AU.BB, "/theRegisters/i_1_0_1338/ZN"; + 0, AU.BB, "/theRegisters/i_1_0_1338/A1"; + 0, AU.BB, "/theRegisters/i_1_0_1338/A2"; + 0, AU.BB, "/theRegisters/i_1_0_1331/ZN"; + 1, EQ, "/theRegisters/i_1_0_1331/A1"; + 1, EQ, "/theRegisters/i_1_0_1331/A2"; + 1, AU.BB, "/theRegisters/i_1_0_1331/ZN"; + 0, AU.BB, "/theRegisters/i_1_0_1331/A1"; + 0, AU.BB, "/theRegisters/i_1_0_1331/A2"; + 0, AU.BB, "/theRegisters/i_1_0_1321/ZN"; + 1, EQ, "/theRegisters/i_1_0_1321/A1"; + 1, EQ, "/theRegisters/i_1_0_1321/A2"; + 1, AU.BB, "/theRegisters/i_1_0_1321/ZN"; + 0, AU.BB, "/theRegisters/i_1_0_1321/A1"; + 0, AU.BB, "/theRegisters/i_1_0_1321/A2"; + 0, AU.BB, "/theRegisters/i_1_0_1361/ZN"; + 1, EQ, "/theRegisters/i_1_0_1361/A1"; + 1, EQ, "/theRegisters/i_1_0_1361/A2"; + 1, AU.BB, "/theRegisters/i_1_0_1361/ZN"; + 0, AU.BB, "/theRegisters/i_1_0_1361/A1"; + 0, AU.BB, "/theRegisters/i_1_0_1361/A2"; + 0, AU.BB, "/theRegisters/i_1_0_1351/ZN"; + 1, EQ, "/theRegisters/i_1_0_1351/A1"; + 1, EQ, "/theRegisters/i_1_0_1351/A2"; + 1, AU.BB, "/theRegisters/i_1_0_1351/ZN"; + 0, AU.BB, "/theRegisters/i_1_0_1351/A1"; + 0, AU.BB, "/theRegisters/i_1_0_1351/A2"; + 0, AU.BB, "/theRegisters/i_1_0_1359/ZN"; + 1, EQ, "/theRegisters/i_1_0_1359/A1"; + 1, EQ, "/theRegisters/i_1_0_1359/A2"; + 1, AU.BB, "/theRegisters/i_1_0_1359/ZN"; + 0, AU.BB, "/theRegisters/i_1_0_1359/A1"; + 0, AU.BB, "/theRegisters/i_1_0_1359/A2"; + 0, AU.BB, "/theRegisters/i_1_0_1345/ZN"; + 1, EQ, "/theRegisters/i_1_0_1345/A1"; + 1, EQ, "/theRegisters/i_1_0_1345/A2"; + 1, AU.BB, "/theRegisters/i_1_0_1345/ZN"; + 0, AU.BB, "/theRegisters/i_1_0_1345/A1"; + 0, AU.BB, "/theRegisters/i_1_0_1345/A2"; + 0, AU.BB, "/theRegisters/i_1_0_1323/ZN"; + 1, EQ, "/theRegisters/i_1_0_1323/A1"; + 1, EQ, "/theRegisters/i_1_0_1323/A2"; + 1, AU.BB, "/theRegisters/i_1_0_1323/ZN"; + 0, AU.BB, "/theRegisters/i_1_0_1323/A1"; + 0, AU.BB, "/theRegisters/i_1_0_1323/A2"; + 0, AU.BB, "/theRegisters/i_1_0_1324/ZN"; + 1, EQ, "/theRegisters/i_1_0_1324/A1"; + 1, EQ, "/theRegisters/i_1_0_1324/A2"; + 1, AU.BB, "/theRegisters/i_1_0_1324/ZN"; + 0, AU.BB, "/theRegisters/i_1_0_1324/A1"; + 0, AU.BB, "/theRegisters/i_1_0_1324/A2"; + 0, AU.BB, "/theRegisters/i_1_0_1337/ZN"; + 1, EQ, "/theRegisters/i_1_0_1337/A1"; + 1, EQ, "/theRegisters/i_1_0_1337/A2"; + 1, AU.BB, "/theRegisters/i_1_0_1337/ZN"; + 0, AU.BB, "/theRegisters/i_1_0_1337/A1"; + 0, AU.BB, "/theRegisters/i_1_0_1337/A2"; + 0, AU.BB, "/theRegisters/i_1_0_1354/ZN"; + 1, AU.BB, "/theRegisters/i_1_0_1354/ZN"; + 0, EQ, "/theRegisters/i_1_0_1354/A2"; + 0, EQ, "/theRegisters/i_1_0_1354/A1"; + 0, EQ, "/theRegisters/i_1_0_1354/A3"; + 1, AU.BB, "/theRegisters/i_1_0_1354/A2"; + 1, AU.BB, "/theRegisters/i_1_0_1354/A1"; + 1, AU.BB, "/theRegisters/i_1_0_1354/A3"; + 0, AU.BB, "/theDecoder/i_0_331/ZN"; + 0, EQ, "/theDecoder/i_0_326/C2"; + 1, AU.BB, "/theDecoder/i_0_326/C1"; + 1, EQ, "/theDecoder/i_0_326/C2"; + 1, EQ, "/theDecoder/i_0_331/ZN"; + 0, EQ, "/theDecoder/i_0_331/A2"; + 0, EQ, "/theDecoder/i_0_331/A1"; + 0, EQ, "/theDecoder/i_0_331/A3"; + 1, AU.BB, "/theDecoder/i_0_331/A2"; + 1, AU.BB, "/theDecoder/i_0_331/A1"; + 1, AU.BB, "/theDecoder/i_0_331/A3"; + 0, AU.BB, "/theDecoder/i_0_337/C1"; + 0, EQ, "/theDecoder/i_0_337/C2"; + 1, AU.BB, "/theDecoder/i_0_337/C1"; + 1, AU.BB, "/theDecoder/i_0_337/C2"; + 0, AU.BB, "/theDecoder/i_0_171/C1"; + 0, EQ, "/theDecoder/i_0_171/C2"; + 1, AU.BB, "/theDecoder/i_0_171/C1"; + 1, AU.BB, "/theDecoder/i_0_171/C2"; + 0, AU.BB, "/theDecoder/i_0_345/ZN"; + 1, EQ, "/theDecoder/i_0_345/A1"; + 1, EQ, "/theDecoder/i_0_345/A2"; + 1, AU.BB, "/theDecoder/i_0_345/ZN"; + 0, AU.BB, "/theDecoder/i_0_345/A1"; + 0, AU.BB, "/theDecoder/i_0_345/A2"; + 0, AU.BB, "/theDecoder/i_0_222/B"; + 1, AU.BB, "/theDecoder/i_0_222/B"; + 0, AU.BB, "/theDecoder/i_18_3/CI"; + 0, EQ, "/theDecoder/i_18_2/CO"; + 1, AU, "/theDecoder/i_18_3/CI"; + 1, EQ, "/theDecoder/i_18_2/CO"; + 0, AU.BB, "/theDecoder/i_0_16/A1"; + 0, EQ, "/theDecoder/i_0_16/A2"; + 0, EQ, "/theDecoder/i_18_2/S"; + 1, AU.BB, "/theDecoder/i_18_2/S"; + 1, EQ, "/theDecoder/i_0_16/A1"; + 0, AU.BB, "/theRegisters/i_0_0_70/ZN"; + 1, AU.BB, "/theRegisters/i_0_0_70/ZN"; + 0, EQ, "/theRegisters/i_0_0_70/A1"; + 0, EQ, "/theRegisters/i_0_0_70/A2"; + 1, AU.BB, "/theRegisters/i_0_0_70/A1"; + 1, AU.BB, "/theRegisters/i_0_0_70/A2"; + 0, AU.BB, "/theRegisters/i_0_0_69/ZN"; + 1, AU.BB, "/theRegisters/i_0_0_69/ZN"; + 0, EQ, "/theRegisters/i_0_0_69/A2"; + 0, EQ, "/theRegisters/i_0_0_69/A1"; + 0, EQ, "/theRegisters/i_0_0_69/A3"; + 1, AU.BB, "/theRegisters/i_0_0_69/A2"; + 1, AU.BB, "/theRegisters/i_0_0_69/A1"; + 1, AU.BB, "/theRegisters/i_0_0_69/A3"; + 0, AU.BB, "/theRegisters/i_0_0_74/ZN"; + 1, AU.BB, "/theRegisters/i_0_0_74/ZN"; + 0, EQ, "/theRegisters/i_0_0_74/A1"; + 0, EQ, "/theRegisters/i_0_0_74/A2"; + 1, AU.BB, "/theRegisters/i_0_0_74/A1"; + 1, AU.BB, "/theRegisters/i_0_0_74/A2"; + 0, AU.BB, "/theRegisters/i_0_0_65/ZN"; + 1, AU.BB, "/theRegisters/i_0_0_65/ZN"; + 0, EQ, "/theRegisters/i_0_0_65/A2"; + 0, EQ, "/theRegisters/i_0_0_65/A1"; + 0, EQ, "/theRegisters/i_0_0_65/A3"; + 1, AU.BB, "/theRegisters/i_0_0_65/A2"; + 1, AU.BB, "/theRegisters/i_0_0_65/A1"; + 1, AU.BB, "/theRegisters/i_0_0_65/A3"; + 0, AU.BB, "/theDecoder/i_0_127/ZN"; + 1, EQ, "/theDecoder/i_0_127/A2"; + 1, EQ, "/theDecoder/i_0_127/A1"; + 1, EQ, "/theDecoder/i_0_127/A3"; + 0, EQ, "/theDecoder/i_0_126/A"; + 0, AU.BB, "/theDecoder/i_0_126/ZN"; + 1, EQ, "/theDecoder/i_0_126/A"; + 1, EQ, "/theDecoder/i_0_127/ZN"; + 0, EQ, "/theDecoder/i_0_122/A3"; + 0, RE, "/theDecoder/i_0_127/A2"; + 0, AU.BB, "/theDecoder/i_0_127/A1"; + 0, RE, "/theDecoder/i_0_127/A3"; + 0, AU.BB, "/theDecoder/i_0_327/ZN"; + 1, AU.BB, "/theDecoder/i_0_327/ZN"; + 1, EQ, "/theDecoder/i_0_327/A1"; + 1, EQ, "/theDecoder/i_0_327/A2"; + 0, AU.BB, "/theDecoder/i_0_327/A1"; + 0, AU.BB, "/theDecoder/i_0_327/A2"; + 0, AU.BB, "/theDecoder/i_0_293/ZN"; + 1, EQ, "/theDecoder/i_0_293/A2"; + 1, EQ, "/theDecoder/i_0_293/A1"; + 1, EQ, "/theDecoder/i_0_293/A3"; + 1, AU.BB, "/theDecoder/i_0_293/ZN"; + 0, AU.BB, "/theDecoder/i_0_293/A2"; + 0, AU.BB, "/theDecoder/i_0_293/A1"; + 0, AU.BB, "/theDecoder/i_0_293/A3"; + 0, AU.BB, "/theDecoder/i_0_338/ZN"; + 1, EQ, "/theDecoder/i_0_338/A"; + 0, EQ, "/theDecoder/i_0_337/B"; + 0, AU.BB, "/theDecoder/i_0_337/ZN"; + 1, EQ, "/theDecoder/i_0_337/B"; + 1, EQ, "/theDecoder/i_0_337/A"; + 1, EQ, "/theDecoder/i_0_338/ZN"; + 0, EQ, "/theDecoder/i_0_338/A"; + 1, AU.BB, "/theDecoder/i_0_337/ZN"; + 0, AU.BB, "/theDecoder/i_0_337/A"; + 0, AU.BB, "/theDecoder/i_0_329/ZN"; + 1, AU.BB, "/theDecoder/i_0_329/ZN"; + 0, EQ, "/theDecoder/i_0_329/A1"; + 0, EQ, "/theDecoder/i_0_329/A2"; + 1, AU.BB, "/theDecoder/i_0_329/A1"; + 1, AU.BB, "/theDecoder/i_0_329/A2"; + 0, AU.BB, "/theDecoder/i_0_335/B1"; + 0, EQ, "/theDecoder/i_0_335/B2"; + 1, AU.BB, "/theDecoder/i_0_335/B1"; + 1, AU.BB, "/theDecoder/i_0_335/B2"; + 0, AU.BB, "/theDecoder/i_0_14/C1"; + 1, AU.BB, "/theDecoder/i_0_14/C1"; + 1, EQ, "/theDecoder/i_0_14/C2"; + 0, RE, "/theDecoder/i_0_14/C2"; + 0, AU.BB, "/theDecoder/i_0_342/ZN"; + 1, AU.BB, "/theDecoder/i_0_342/ZN"; + 0, EQ, "/theDecoder/i_0_342/A1"; + 0, EQ, "/theDecoder/i_0_342/A2"; + 1, AU.BB, "/theDecoder/i_0_342/A1"; + 1, AU.BB, "/theDecoder/i_0_342/A2"; + 0, AU.BB, "/theDecoder/i_0_328/ZN"; + 1, EQ, "/theDecoder/i_0_328/A1"; + 1, EQ, "/theDecoder/i_0_328/A2"; + 1, AU.BB, "/theDecoder/i_0_328/ZN"; + 0, AU.BB, "/theDecoder/i_0_328/A1"; + 0, AU.BB, "/theDecoder/i_0_328/A2"; + 0, RE, "/theDecoder/i_0_119/B2"; + 1, AU.BB, "/theDecoder/i_0_119/B2"; + 1, EQ, "/theDecoder/i_0_119/B1"; + 1, EQ, "/theDecoder/i_0_119/B3"; + 0, AU.BB, "/theDecoder/i_0_119/B1"; + 0, AU.BB, "/theDecoder/i_0_119/B3"; + 0, AU.BB, "/theDecoder/i_0_112/ZN"; + 1, EQ, "/theDecoder/i_0_112/A1"; + 1, EQ, "/theDecoder/i_0_112/A2"; + 1, AU.BB, "/theDecoder/i_0_112/ZN"; + 0, AU.BB, "/theDecoder/i_0_112/A1"; + 0, AU.BB, "/theDecoder/i_0_112/A2"; + 0, AU.BB, "/theDecoder/i_0_332/ZN"; + 1, AU.BB, "/theDecoder/i_0_332/ZN"; + 1, EQ, "/theDecoder/i_0_332/A1"; + 1, EQ, "/theDecoder/i_0_332/A2"; + 0, AU.BB, "/theDecoder/i_0_332/A1"; + 0, AU.BB, "/theDecoder/i_0_332/A2"; + 0, AU.BB, "/theRegisters/i_0_0_79/ZN"; + 1, EQ, "/theRegisters/i_0_0_79/A"; + 1, AU.BB, "/theRegisters/i_0_0_79/ZN"; + 0, EQ, "/theRegisters/i_0_0_79/A"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[2]_reg /CK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[2]_reg /CK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[3]_reg /CK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[3]_reg /CK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[14]_reg /CK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[14]_reg /CK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[15]_reg /CK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[15]_reg /CK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[25]_reg /CK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[25]_reg /CK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[13]_reg /CK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[13]_reg /CK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[11]_reg /CK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[11]_reg /CK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[27]_reg /CK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[27]_reg /CK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[20]_reg /CK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[20]_reg /CK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[17]_reg /CK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[17]_reg /CK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[21]_reg /CK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[21]_reg /CK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[22]_reg /CK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[22]_reg /CK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[12]_reg /CK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[12]_reg /CK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[24]_reg /CK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[24]_reg /CK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[30]_reg /CK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[30]_reg /CK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[18]_reg /CK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[18]_reg /CK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[29]_reg /CK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[29]_reg /CK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[9]_reg /CK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[9]_reg /CK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[8]_reg /CK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[8]_reg /CK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[26]_reg /CK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[26]_reg /CK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[10]_reg /CK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[10]_reg /CK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[5]_reg /CK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[5]_reg /CK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[19]_reg /CK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[19]_reg /CK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[7]_reg /CK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[7]_reg /CK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[23]_reg /CK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[23]_reg /CK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[1]_reg /CK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[1]_reg /CK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[6]_reg /CK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[6]_reg /CK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[31]_reg /CK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[31]_reg /CK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[16]_reg /CK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[16]_reg /CK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[4]_reg /CK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[4]_reg /CK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[28]_reg /CK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[28]_reg /CK"; + 0, DI.SEN, "/\thePC_CurrentPC_reg[16] /SE"; + 1, DS, "/\thePC_CurrentPC_reg[16] /SE"; + 0, DI.SEN, "/\thePC_CurrentPC_reg[17] /SE"; + 1, DS, "/\thePC_CurrentPC_reg[17] /SE"; + 0, DI.SEN, "/\thePC_CurrentPC_reg[18] /SE"; + 1, DS, "/\thePC_CurrentPC_reg[18] /SE"; + 0, DI.SEN, "/\thePC_CurrentPC_reg[19] /SE"; + 1, DS, "/\thePC_CurrentPC_reg[19] /SE"; + 0, DI.SEN, "/\thePC_CurrentPC_reg[20] /SE"; + 1, DS, "/\thePC_CurrentPC_reg[20] /SE"; + 0, DI.SEN, "/\thePC_CurrentPC_reg[21] /SE"; + 1, DS, "/\thePC_CurrentPC_reg[21] /SE"; + 0, DI.SEN, "/\thePC_CurrentPC_reg[22] /SE"; + 1, DS, "/\thePC_CurrentPC_reg[22] /SE"; + 0, DI.SEN, "/\thePC_CurrentPC_reg[23] /SE"; + 1, DS, "/\thePC_CurrentPC_reg[23] /SE"; + 0, DI.SEN, "/\thePC_CurrentPC_reg[24] /SE"; + 1, DS, "/\thePC_CurrentPC_reg[24] /SE"; + 0, DI.SEN, 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EQ, "/theRegisters/i_1_0_1347/A2"; + 1, AU.BB, "/theRegisters/i_1_0_1347/ZN"; + 0, AU.BB, "/theRegisters/i_1_0_1347/A1"; + 0, AU.BB, "/theRegisters/i_1_0_1347/A2"; + 0, AU.BB, "/theDecoder/i_0_326/C1"; + 0, AU.BB, "/theDecoder/i_0_336/ZN"; + 0, EQ, "/theDecoder/i_0_333/C2"; + 1, AU.BB, "/theDecoder/i_0_333/C1"; + 1, EQ, "/theDecoder/i_0_333/C2"; + 1, EQ, "/theDecoder/i_0_336/ZN"; + 0, EQ, "/theDecoder/i_0_336/A1"; + 0, EQ, "/theDecoder/i_0_336/A2"; + 1, AU.BB, "/theDecoder/i_0_336/A1"; + 1, AU.BB, "/theDecoder/i_0_336/A2"; + 0, AU.BB, "/theDecoder/i_0_118/ZN"; + 1, EQ, "/theDecoder/i_0_118/A2"; + 1, EQ, "/theDecoder/i_0_118/A1"; + 1, EQ, "/theDecoder/i_0_118/A3"; + 1, AU.BB, "/theDecoder/i_0_118/ZN"; + 0, AU.BB, "/theDecoder/i_0_118/A2"; + 0, AU.BB, "/theDecoder/i_0_118/A1"; + 0, AU.BB, "/theDecoder/i_0_118/A3"; + 0, AU.BB, "/theDecoder/i_0_222/A"; + 1, AU.BB, "/theDecoder/i_0_222/A"; + 0, AU.BB, "/theDecoder/i_0_231/B1"; + 1, AU.BB, "/theDecoder/i_0_231/B1"; + 1, EQ, "/theDecoder/i_0_231/B2"; + 0, AU.BB, "/theDecoder/i_0_231/B2"; + 0, AU.BB, "/theDecoder/i_0_294/ZN"; + 1, EQ, "/theDecoder/i_0_294/A2"; + 1, EQ, "/theDecoder/i_0_294/A1"; + 1, EQ, "/theDecoder/i_0_294/A3"; + 1, AU.BB, "/theDecoder/i_0_294/ZN"; + 0, AU.BB, "/theDecoder/i_0_294/A2"; + 0, AU.BB, "/theDecoder/i_0_294/A1"; + 0, AU.BB, "/theDecoder/i_0_294/A3"; + 1, AU.BB, "/theDecoder/i_0_122/ZN"; + 0, RE, "/theDecoder/i_0_122/A1"; + 0, AU.BB, "/theDecoder/i_0_122/A4"; + 0, AU.BB, "/theDecoder/i_0_209/B1"; + 0, EQ, "/theDecoder/i_0_209/B2"; + 1, AU.BB, "/theDecoder/i_0_209/B1"; + 1, AU.BB, "/theDecoder/i_0_209/B2"; + 0, AU.BB, "/theDecoder/i_0_212/B1"; + 0, EQ, "/theDecoder/i_0_212/B2"; + 1, AU.BB, "/theDecoder/i_0_212/B1"; + 1, AU.BB, "/theDecoder/i_0_212/B2"; + 0, AU.BB, "/theDecoder/i_0_215/B1"; + 0, EQ, "/theDecoder/i_0_215/B2"; + 1, AU.BB, "/theDecoder/i_0_215/B1"; + 1, AU.BB, "/theDecoder/i_0_215/B2"; + 0, AU.BB, "/theDecoder/i_0_223/B1"; + 0, EQ, "/theDecoder/i_0_223/B2"; + 1, AU.BB, "/theDecoder/i_0_223/B1"; + 1, AU.BB, "/theDecoder/i_0_223/B2"; + 0, AU.BB, "/theDecoder/i_0_292/ZN"; + 0, EQ, "/theDecoder/i_0_292/A1"; + 0, EQ, "/theDecoder/i_0_292/A2"; + 1, AU.BB, "/theDecoder/i_0_292/ZN"; + 1, AU.BB, "/theDecoder/i_0_292/A1"; + 1, RE, "/theDecoder/i_0_292/A2"; + 0, RE, "/theDecoder/i_0_14/B1"; + 1, AU.BB, "/theDecoder/i_0_14/B1"; + 1, EQ, "/theDecoder/i_0_14/B2"; + 0, AU.BB, "/theDecoder/i_0_14/B2"; + 0, AU.BB, "/theDecoder/i_0_335/ZN"; + 1, EQ, "/theDecoder/i_0_335/A"; + 0, EQ, "/theDecoder/i_0_334/A2"; + 1, AU.BB, "/theDecoder/i_0_333/ZN"; + 0, EQ, "/theDecoder/i_0_333/A"; + 0, EQ, "/theDecoder/i_0_333/B"; + 0, EQ, "/theDecoder/i_0_334/ZN"; + 1, EQ, "/theDecoder/i_0_334/A1"; + 1, EQ, "/theDecoder/i_0_334/A2"; + 1, EQ, "/theDecoder/i_0_335/ZN"; + 0, AU.BB, "/theDecoder/i_0_335/A"; + 0, AU.BB, "/i_0_0_1/A1"; + 0, EQ, "/i_0_0_1/A2"; + 0, EQ, "/theDecoder/i_0_13/ZN"; + 0, EQ, "/theDecoder/i_0_13/A2"; + 0, EQ, "/theDecoder/i_0_13/A1"; + 0, EQ, "/theDecoder/i_0_14/ZN"; + 1, AU.BB, "/theDecoder/i_0_14/ZN"; + 0, EQ, "/theDecoder/i_0_14/A"; + 1, EQ, "/theDecoder/i_0_13/A1"; + 1, AU.BB, "/theDecoder/i_0_14/A"; + 0, AU.BB, "/theDecoder/i_0_121/B1"; + 0, EQ, "/theDecoder/i_0_121/B2"; + 1, AU.BB, "/theDecoder/i_0_121/B1"; + 1, AU.BB, "/theDecoder/i_0_121/B2"; + 0, AU.BB, "/theDecoder/i_0_223/A1"; + 0, EQ, "/theDecoder/i_0_223/A2"; + 1, AU.BB, "/theDecoder/i_0_223/A1"; + 1, AU.BB, "/theDecoder/i_0_223/A2"; + 0, AU.BB, "/theDecoder/i_0_119/A2"; + 1, AU.BB, "/theDecoder/i_0_119/A2"; + 1, EQ, "/theDecoder/i_0_119/A1"; + 1, EQ, "/theDecoder/i_0_119/A3"; + 0, AU.BB, "/theDecoder/i_0_119/A1"; + 0, AU.BB, "/theDecoder/i_0_119/A3"; + 0, AU.BB, "/theDecoder/i_0_356/ZN"; + 1, EQ, "/theDecoder/i_0_356/A"; + 1, AU.BB, "/theDecoder/i_0_356/ZN"; + 0, EQ, "/theDecoder/i_0_356/A"; + 0, AU.BB, "/theDecoder/i_0_119/ZN"; + 1, AU.BB, "/theDecoder/i_0_119/ZN"; + 0, AU.BB, "/theDecoder/i_0_325/ZN"; + 1, AU.BB, "/theDecoder/i_0_325/ZN"; + 1, EQ, "/theDecoder/i_0_325/A2"; + 1, EQ, "/theDecoder/i_0_325/A1"; + 1, EQ, "/theDecoder/i_0_325/A3"; + 0, AU.BB, "/theDecoder/i_0_325/A2"; + 0, AU.BB, "/theDecoder/i_0_325/A1"; + 0, AU.BB, "/theDecoder/i_0_325/A3"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[2]_reg /GCK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[2]_reg /GCK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[3]_reg /GCK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[3]_reg /GCK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[14]_reg /GCK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[14]_reg /GCK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[15]_reg /GCK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[15]_reg /GCK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[25]_reg /GCK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[25]_reg /GCK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[13]_reg /GCK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[13]_reg /GCK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[11]_reg /GCK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[11]_reg /GCK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[27]_reg /GCK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[27]_reg /GCK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[20]_reg /GCK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[20]_reg /GCK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[17]_reg /GCK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[17]_reg /GCK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[21]_reg /GCK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[21]_reg /GCK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[22]_reg /GCK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[22]_reg /GCK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[12]_reg /GCK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[12]_reg /GCK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[24]_reg /GCK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[24]_reg /GCK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[30]_reg /GCK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[30]_reg /GCK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[18]_reg /GCK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[18]_reg /GCK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[29]_reg /GCK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[29]_reg /GCK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[9]_reg /GCK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[9]_reg /GCK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[8]_reg /GCK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[8]_reg /GCK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[26]_reg /GCK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[26]_reg /GCK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[10]_reg /GCK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[10]_reg /GCK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[5]_reg /GCK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[5]_reg /GCK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[19]_reg /GCK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[19]_reg /GCK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[7]_reg /GCK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[7]_reg /GCK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[23]_reg /GCK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[23]_reg /GCK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[1]_reg /GCK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[1]_reg /GCK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[6]_reg /GCK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[6]_reg /GCK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[31]_reg /GCK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[31]_reg /GCK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[16]_reg /GCK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[16]_reg /GCK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[4]_reg /GCK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[4]_reg /GCK"; + 0, DI.CLK, "/theRegisters/\clk_gate_registers_reg[28]_reg /GCK"; + 1, DI.CLK, "/theRegisters/\clk_gate_registers_reg[28]_reg /GCK"; + 0, DI.SEN, "/theRegisters/\registers_reg[11][0] /SE"; + 1, DS, "/theRegisters/\registers_reg[11][0] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[27][0] /SE"; + 1, DS, "/theRegisters/\registers_reg[27][0] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[14][0] /SE"; + 1, DS, "/theRegisters/\registers_reg[14][0] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[6][0] /SE"; + 1, DS, "/theRegisters/\registers_reg[6][0] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[1][0] /SE"; + 1, DS, "/theRegisters/\registers_reg[1][0] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[9][0] /SE"; + 1, DS, "/theRegisters/\registers_reg[9][0] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[2][0] /SE"; + 1, DS, "/theRegisters/\registers_reg[2][0] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[19][0] /SE"; + 1, DS, "/theRegisters/\registers_reg[19][0] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[5][0] /SE"; + 1, DS, "/theRegisters/\registers_reg[5][0] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[22][0] /SE"; + 1, DS, "/theRegisters/\registers_reg[22][0] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[16][0] /SE"; + 1, DS, "/theRegisters/\registers_reg[16][0] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[15][0] /SE"; + 1, DS, "/theRegisters/\registers_reg[15][0] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[12][0] /SE"; + 1, DS, "/theRegisters/\registers_reg[12][0] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[4][0] /SE"; + 1, DS, "/theRegisters/\registers_reg[4][0] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[30][0] /SE"; + 1, DS, "/theRegisters/\registers_reg[30][0] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[18][0] /SE"; + 1, DS, "/theRegisters/\registers_reg[18][0] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[23][0] /SE"; + 1, DS, "/theRegisters/\registers_reg[23][0] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[29][0] /SE"; + 1, DS, "/theRegisters/\registers_reg[29][0] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[31][0] /SE"; + 1, DS, "/theRegisters/\registers_reg[31][0] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[17][0] /SE"; + 1, DS, "/theRegisters/\registers_reg[17][0] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[3][0] /SE"; + 1, DS, "/theRegisters/\registers_reg[3][0] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[7][0] /SE"; + 1, DS, "/theRegisters/\registers_reg[7][0] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[20][0] /SE"; + 1, DS, "/theRegisters/\registers_reg[20][0] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[24][0] /SE"; + 1, DS, "/theRegisters/\registers_reg[24][0] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[8][0] /SE"; + 1, DS, "/theRegisters/\registers_reg[8][0] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[28][0] /SE"; + 1, DS, "/theRegisters/\registers_reg[28][0] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[25][0] /SE"; + 1, DS, "/theRegisters/\registers_reg[25][0] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[26][0] /SE"; + 1, DS, "/theRegisters/\registers_reg[26][0] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[10][0] /SE"; + 1, DS, "/theRegisters/\registers_reg[10][0] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[21][0] /SE"; + 1, DS, "/theRegisters/\registers_reg[21][0] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[13][0] /SE"; + 1, DS, "/theRegisters/\registers_reg[13][0] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[27][1] /SE"; + 1, DS, "/theRegisters/\registers_reg[27][1] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[11][1] /SE"; + 1, DS, "/theRegisters/\registers_reg[11][1] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[2][1] /SE"; + 1, DS, "/theRegisters/\registers_reg[2][1] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[19][1] /SE"; + 1, DS, "/theRegisters/\registers_reg[19][1] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[14][1] /SE"; + 1, DS, "/theRegisters/\registers_reg[14][1] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[6][1] /SE"; + 1, DS, "/theRegisters/\registers_reg[6][1] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[1][1] /SE"; + 1, DS, "/theRegisters/\registers_reg[1][1] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[9][1] /SE"; + 1, DS, "/theRegisters/\registers_reg[9][1] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[16][1] /SE"; + 1, DS, "/theRegisters/\registers_reg[16][1] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[22][1] /SE"; + 1, DS, "/theRegisters/\registers_reg[22][1] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[5][1] /SE"; + 1, DS, "/theRegisters/\registers_reg[5][1] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[15][1] /SE"; + 1, DS, "/theRegisters/\registers_reg[15][1] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[12][1] /SE"; + 1, DS, "/theRegisters/\registers_reg[12][1] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[17][1] /SE"; + 1, DS, "/theRegisters/\registers_reg[17][1] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[30][1] /SE"; + 1, DS, "/theRegisters/\registers_reg[30][1] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[18][1] /SE"; + 1, DS, "/theRegisters/\registers_reg[18][1] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[28][1] /SE"; + 1, DS, "/theRegisters/\registers_reg[28][1] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[8][1] /SE"; + 1, DS, "/theRegisters/\registers_reg[8][1] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[25][1] /SE"; + 1, DS, "/theRegisters/\registers_reg[25][1] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[26][1] /SE"; + 1, DS, "/theRegisters/\registers_reg[26][1] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[10][1] /SE"; + 1, DS, "/theRegisters/\registers_reg[10][1] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[4][1] /SE"; + 1, DS, "/theRegisters/\registers_reg[4][1] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[31][1] /SE"; + 1, DS, "/theRegisters/\registers_reg[31][1] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[3][1] /SE"; + 1, DS, "/theRegisters/\registers_reg[3][1] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[7][1] /SE"; + 1, DS, "/theRegisters/\registers_reg[7][1] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[20][1] /SE"; + 1, DS, "/theRegisters/\registers_reg[20][1] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[24][1] /SE"; + 1, DS, "/theRegisters/\registers_reg[24][1] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[23][1] /SE"; + 1, DS, "/theRegisters/\registers_reg[23][1] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[29][1] /SE"; + 1, DS, "/theRegisters/\registers_reg[29][1] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[21][1] /SE"; + 1, DS, "/theRegisters/\registers_reg[21][1] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[13][1] /SE"; + 1, DS, "/theRegisters/\registers_reg[13][1] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[2][2] /SE"; + 1, DS, "/theRegisters/\registers_reg[2][2] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[23][2] /SE"; + 1, DS, "/theRegisters/\registers_reg[23][2] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[3][2] /SE"; + 1, DS, "/theRegisters/\registers_reg[3][2] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[19][2] /SE"; + 1, DS, "/theRegisters/\registers_reg[19][2] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[14][2] /SE"; + 1, DS, "/theRegisters/\registers_reg[14][2] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[7][2] /SE"; + 1, DS, "/theRegisters/\registers_reg[7][2] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[25][2] /SE"; + 1, DS, "/theRegisters/\registers_reg[25][2] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[13][2] /SE"; + 1, DS, "/theRegisters/\registers_reg[13][2] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[20][2] /SE"; + 1, DS, "/theRegisters/\registers_reg[20][2] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[17][2] /SE"; + 1, DS, "/theRegisters/\registers_reg[17][2] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[21][2] /SE"; + 1, DS, "/theRegisters/\registers_reg[21][2] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[22][2] /SE"; + 1, DS, "/theRegisters/\registers_reg[22][2] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[12][2] /SE"; + 1, DS, "/theRegisters/\registers_reg[12][2] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[24][2] /SE"; + 1, DS, "/theRegisters/\registers_reg[24][2] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[26][2] /SE"; + 1, DS, "/theRegisters/\registers_reg[26][2] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[18][2] /SE"; + 1, DS, "/theRegisters/\registers_reg[18][2] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[29][2] /SE"; + 1, DS, "/theRegisters/\registers_reg[29][2] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[9][2] /SE"; + 1, DS, "/theRegisters/\registers_reg[9][2] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[8][2] /SE"; + 1, DS, "/theRegisters/\registers_reg[8][2] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[30][2] /SE"; + 1, DS, "/theRegisters/\registers_reg[30][2] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[10][2] /SE"; + 1, DS, "/theRegisters/\registers_reg[10][2] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[5][2] /SE"; + 1, DS, "/theRegisters/\registers_reg[5][2] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[11][2] /SE"; + 1, DS, "/theRegisters/\registers_reg[11][2] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[27][2] /SE"; + 1, DS, "/theRegisters/\registers_reg[27][2] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[15][2] /SE"; + 1, DS, "/theRegisters/\registers_reg[15][2] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[1][2] /SE"; + 1, DS, "/theRegisters/\registers_reg[1][2] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[6][2] /SE"; + 1, DS, "/theRegisters/\registers_reg[6][2] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[31][2] /SE"; + 1, DS, "/theRegisters/\registers_reg[31][2] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[16][2] /SE"; + 1, DS, "/theRegisters/\registers_reg[16][2] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[4][2] /SE"; + 1, DS, "/theRegisters/\registers_reg[4][2] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[28][2] /SE"; + 1, DS, "/theRegisters/\registers_reg[28][2] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[11][3] /SE"; + 1, DS, "/theRegisters/\registers_reg[11][3] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[27][3] /SE"; + 1, DS, "/theRegisters/\registers_reg[27][3] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[14][3] /SE"; + 1, DS, "/theRegisters/\registers_reg[14][3] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[7][3] /SE"; + 1, DS, "/theRegisters/\registers_reg[7][3] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[2][3] /SE"; + 1, DS, "/theRegisters/\registers_reg[2][3] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[19][3] /SE"; + 1, DS, "/theRegisters/\registers_reg[19][3] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[25][3] /SE"; + 1, DS, "/theRegisters/\registers_reg[25][3] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[13][3] /SE"; + 1, DS, "/theRegisters/\registers_reg[13][3] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[12][3] /SE"; + 1, DS, "/theRegisters/\registers_reg[12][3] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[24][3] /SE"; + 1, DS, "/theRegisters/\registers_reg[24][3] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[21][3] /SE"; + 1, DS, "/theRegisters/\registers_reg[21][3] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[22][3] /SE"; + 1, DS, "/theRegisters/\registers_reg[22][3] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[4][3] /SE"; + 1, DS, "/theRegisters/\registers_reg[4][3] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[20][3] /SE"; + 1, DS, "/theRegisters/\registers_reg[20][3] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[30][3] /SE"; + 1, DS, "/theRegisters/\registers_reg[30][3] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[18][3] /SE"; + 1, DS, "/theRegisters/\registers_reg[18][3] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[23][3] /SE"; + 1, DS, "/theRegisters/\registers_reg[23][3] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[15][3] /SE"; + 1, DS, "/theRegisters/\registers_reg[15][3] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[31][3] /SE"; + 1, DS, "/theRegisters/\registers_reg[31][3] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[5][3] /SE"; + 1, DS, "/theRegisters/\registers_reg[5][3] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[3][3] /SE"; + 1, DS, "/theRegisters/\registers_reg[3][3] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[16][3] /SE"; + 1, DS, "/theRegisters/\registers_reg[16][3] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[1][3] /SE"; + 1, DS, "/theRegisters/\registers_reg[1][3] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[6][3] /SE"; + 1, DS, "/theRegisters/\registers_reg[6][3] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[29][3] /SE"; + 1, DS, "/theRegisters/\registers_reg[29][3] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[9][3] /SE"; + 1, DS, "/theRegisters/\registers_reg[9][3] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[8][3] /SE"; + 1, DS, "/theRegisters/\registers_reg[8][3] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[26][3] /SE"; + 1, DS, "/theRegisters/\registers_reg[26][3] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[10][3] /SE"; + 1, DS, "/theRegisters/\registers_reg[10][3] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[17][3] /SE"; + 1, DS, "/theRegisters/\registers_reg[17][3] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[28][3] /SE"; + 1, DS, "/theRegisters/\registers_reg[28][3] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[5][4] /SE"; + 1, DS, "/theRegisters/\registers_reg[5][4] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[6][4] /SE"; + 1, DS, "/theRegisters/\registers_reg[6][4] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[2][4] /SE"; + 1, DS, "/theRegisters/\registers_reg[2][4] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[29][4] /SE"; + 1, DS, "/theRegisters/\registers_reg[29][4] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[25][4] /SE"; + 1, DS, "/theRegisters/\registers_reg[25][4] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[4][4] /SE"; + 1, DS, "/theRegisters/\registers_reg[4][4] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[16][4] /SE"; + 1, DS, "/theRegisters/\registers_reg[16][4] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[15][4] /SE"; + 1, DS, "/theRegisters/\registers_reg[15][4] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[14][4] /SE"; + 1, DS, "/theRegisters/\registers_reg[14][4] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[7][4] /SE"; + 1, DS, "/theRegisters/\registers_reg[7][4] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[17][4] /SE"; + 1, DS, "/theRegisters/\registers_reg[17][4] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[11][4] /SE"; + 1, DS, "/theRegisters/\registers_reg[11][4] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[27][4] /SE"; + 1, DS, "/theRegisters/\registers_reg[27][4] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[12][4] /SE"; + 1, DS, "/theRegisters/\registers_reg[12][4] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[24][4] /SE"; + 1, DS, "/theRegisters/\registers_reg[24][4] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[31][4] /SE"; + 1, DS, "/theRegisters/\registers_reg[31][4] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[30][4] /SE"; + 1, DS, "/theRegisters/\registers_reg[30][4] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[3][4] /SE"; + 1, DS, "/theRegisters/\registers_reg[3][4] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[26][4] /SE"; + 1, DS, "/theRegisters/\registers_reg[26][4] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[13][4] /SE"; + 1, DS, "/theRegisters/\registers_reg[13][4] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[19][4] /SE"; + 1, DS, "/theRegisters/\registers_reg[19][4] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[20][4] /SE"; + 1, DS, "/theRegisters/\registers_reg[20][4] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[28][4] /SE"; + 1, DS, "/theRegisters/\registers_reg[28][4] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[23][4] /SE"; + 1, DS, "/theRegisters/\registers_reg[23][4] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[22][4] /SE"; + 1, DS, "/theRegisters/\registers_reg[22][4] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[8][4] /SE"; + 1, DS, "/theRegisters/\registers_reg[8][4] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[18][4] /SE"; + 1, DS, "/theRegisters/\registers_reg[18][4] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[1][4] /SE"; + 1, DS, "/theRegisters/\registers_reg[1][4] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[9][4] /SE"; + 1, DS, "/theRegisters/\registers_reg[9][4] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[21][4] /SE"; + 1, DS, "/theRegisters/\registers_reg[21][4] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[10][4] /SE"; + 1, DS, "/theRegisters/\registers_reg[10][4] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[11][5] /SE"; + 1, DS, "/theRegisters/\registers_reg[11][5] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[27][5] /SE"; + 1, DS, "/theRegisters/\registers_reg[27][5] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[14][5] /SE"; + 1, DS, "/theRegisters/\registers_reg[14][5] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[7][5] /SE"; + 1, DS, "/theRegisters/\registers_reg[7][5] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[2][5] /SE"; + 1, DS, "/theRegisters/\registers_reg[2][5] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[19][5] /SE"; + 1, DS, "/theRegisters/\registers_reg[19][5] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[25][5] /SE"; + 1, DS, "/theRegisters/\registers_reg[25][5] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[13][5] /SE"; + 1, DS, "/theRegisters/\registers_reg[13][5] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[17][5] /SE"; + 1, DS, "/theRegisters/\registers_reg[17][5] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[20][5] /SE"; + 1, DS, "/theRegisters/\registers_reg[20][5] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[21][5] /SE"; + 1, DS, "/theRegisters/\registers_reg[21][5] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[22][5] /SE"; + 1, DS, "/theRegisters/\registers_reg[22][5] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[12][5] /SE"; + 1, DS, "/theRegisters/\registers_reg[12][5] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[24][5] /SE"; + 1, DS, "/theRegisters/\registers_reg[24][5] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[30][5] /SE"; + 1, DS, "/theRegisters/\registers_reg[30][5] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[18][5] /SE"; + 1, DS, "/theRegisters/\registers_reg[18][5] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[23][5] /SE"; + 1, DS, "/theRegisters/\registers_reg[23][5] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[15][5] /SE"; + 1, DS, "/theRegisters/\registers_reg[15][5] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[31][5] /SE"; + 1, DS, "/theRegisters/\registers_reg[31][5] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[5][5] /SE"; + 1, DS, "/theRegisters/\registers_reg[5][5] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[3][5] /SE"; + 1, DS, "/theRegisters/\registers_reg[3][5] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[16][5] /SE"; + 1, DS, "/theRegisters/\registers_reg[16][5] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[1][5] /SE"; + 1, DS, "/theRegisters/\registers_reg[1][5] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[6][5] /SE"; + 1, DS, "/theRegisters/\registers_reg[6][5] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[29][5] /SE"; + 1, DS, "/theRegisters/\registers_reg[29][5] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[9][5] /SE"; + 1, DS, "/theRegisters/\registers_reg[9][5] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[8][5] /SE"; + 1, DS, "/theRegisters/\registers_reg[8][5] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[26][5] /SE"; + 1, DS, "/theRegisters/\registers_reg[26][5] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[10][5] /SE"; + 1, DS, "/theRegisters/\registers_reg[10][5] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[4][5] /SE"; + 1, DS, "/theRegisters/\registers_reg[4][5] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[28][5] /SE"; + 1, DS, "/theRegisters/\registers_reg[28][5] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[23][6] /SE"; + 1, DS, "/theRegisters/\registers_reg[23][6] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[2][6] /SE"; + 1, DS, "/theRegisters/\registers_reg[2][6] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[3][6] /SE"; + 1, DS, "/theRegisters/\registers_reg[3][6] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[19][6] /SE"; + 1, DS, "/theRegisters/\registers_reg[19][6] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[14][6] /SE"; + 1, DS, "/theRegisters/\registers_reg[14][6] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[7][6] /SE"; + 1, DS, "/theRegisters/\registers_reg[7][6] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[25][6] /SE"; + 1, DS, "/theRegisters/\registers_reg[25][6] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[13][6] /SE"; + 1, DS, "/theRegisters/\registers_reg[13][6] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[12][6] /SE"; + 1, DS, "/theRegisters/\registers_reg[12][6] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[24][6] /SE"; + 1, DS, "/theRegisters/\registers_reg[24][6] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[21][6] /SE"; + 1, DS, "/theRegisters/\registers_reg[21][6] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[22][6] /SE"; + 1, DS, "/theRegisters/\registers_reg[22][6] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[4][6] /SE"; + 1, DS, "/theRegisters/\registers_reg[4][6] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[20][6] /SE"; + 1, DS, "/theRegisters/\registers_reg[20][6] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[30][6] /SE"; + 1, DS, "/theRegisters/\registers_reg[30][6] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[26][6] /SE"; + 1, DS, "/theRegisters/\registers_reg[26][6] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[31][6] /SE"; + 1, DS, "/theRegisters/\registers_reg[31][6] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[5][6] /SE"; + 1, DS, "/theRegisters/\registers_reg[5][6] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[16][6] /SE"; + 1, DS, "/theRegisters/\registers_reg[16][6] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[11][6] /SE"; + 1, DS, "/theRegisters/\registers_reg[11][6] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[27][6] /SE"; + 1, DS, "/theRegisters/\registers_reg[27][6] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[15][6] /SE"; + 1, DS, "/theRegisters/\registers_reg[15][6] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[1][6] /SE"; + 1, DS, "/theRegisters/\registers_reg[1][6] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[6][6] /SE"; + 1, DS, "/theRegisters/\registers_reg[6][6] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[29][6] /SE"; + 1, DS, "/theRegisters/\registers_reg[29][6] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[9][6] /SE"; + 1, DS, "/theRegisters/\registers_reg[9][6] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[8][6] /SE"; + 1, DS, "/theRegisters/\registers_reg[8][6] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[10][6] /SE"; + 1, DS, "/theRegisters/\registers_reg[10][6] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[18][6] /SE"; + 1, DS, "/theRegisters/\registers_reg[18][6] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[17][6] /SE"; + 1, DS, "/theRegisters/\registers_reg[17][6] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[28][6] /SE"; + 1, DS, "/theRegisters/\registers_reg[28][6] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[23][7] /SE"; + 1, DS, "/theRegisters/\registers_reg[23][7] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[2][7] /SE"; + 1, DS, "/theRegisters/\registers_reg[2][7] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[14][7] /SE"; + 1, DS, "/theRegisters/\registers_reg[14][7] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[6][7] /SE"; + 1, DS, "/theRegisters/\registers_reg[6][7] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[1][7] /SE"; + 1, DS, "/theRegisters/\registers_reg[1][7] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[9][7] /SE"; + 1, DS, "/theRegisters/\registers_reg[9][7] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[3][7] /SE"; + 1, DS, "/theRegisters/\registers_reg[3][7] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[19][7] /SE"; + 1, DS, "/theRegisters/\registers_reg[19][7] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[5][7] /SE"; + 1, DS, "/theRegisters/\registers_reg[5][7] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[22][7] /SE"; + 1, DS, "/theRegisters/\registers_reg[22][7] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[16][7] /SE"; + 1, DS, "/theRegisters/\registers_reg[16][7] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[15][7] /SE"; + 1, DS, "/theRegisters/\registers_reg[15][7] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[12][7] /SE"; + 1, DS, "/theRegisters/\registers_reg[12][7] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[4][7] /SE"; + 1, DS, "/theRegisters/\registers_reg[4][7] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[30][7] /SE"; + 1, DS, "/theRegisters/\registers_reg[30][7] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[26][7] /SE"; + 1, DS, "/theRegisters/\registers_reg[26][7] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[29][7] /SE"; + 1, DS, "/theRegisters/\registers_reg[29][7] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[27][7] /SE"; + 1, DS, "/theRegisters/\registers_reg[27][7] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[11][7] /SE"; + 1, DS, "/theRegisters/\registers_reg[11][7] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[17][7] /SE"; + 1, DS, "/theRegisters/\registers_reg[17][7] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[7][7] /SE"; + 1, DS, "/theRegisters/\registers_reg[7][7] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[31][7] /SE"; + 1, DS, "/theRegisters/\registers_reg[31][7] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[20][7] /SE"; + 1, DS, "/theRegisters/\registers_reg[20][7] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[24][7] /SE"; + 1, DS, "/theRegisters/\registers_reg[24][7] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[8][7] /SE"; + 1, DS, "/theRegisters/\registers_reg[8][7] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[28][7] /SE"; + 1, DS, "/theRegisters/\registers_reg[28][7] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[25][7] /SE"; + 1, DS, "/theRegisters/\registers_reg[25][7] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[10][7] /SE"; + 1, DS, "/theRegisters/\registers_reg[10][7] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[18][7] /SE"; + 1, DS, "/theRegisters/\registers_reg[18][7] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[21][7] /SE"; + 1, DS, "/theRegisters/\registers_reg[21][7] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[13][7] /SE"; + 1, DS, "/theRegisters/\registers_reg[13][7] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[27][8] /SE"; + 1, DS, "/theRegisters/\registers_reg[27][8] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[11][8] /SE"; + 1, DS, "/theRegisters/\registers_reg[11][8] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[2][8] /SE"; + 1, DS, "/theRegisters/\registers_reg[2][8] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[19][8] /SE"; + 1, DS, "/theRegisters/\registers_reg[19][8] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[14][8] /SE"; + 1, DS, "/theRegisters/\registers_reg[14][8] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[6][8] /SE"; + 1, DS, "/theRegisters/\registers_reg[6][8] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[1][8] /SE"; + 1, DS, "/theRegisters/\registers_reg[1][8] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[9][8] /SE"; + 1, DS, "/theRegisters/\registers_reg[9][8] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[16][8] /SE"; + 1, DS, "/theRegisters/\registers_reg[16][8] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[22][8] /SE"; + 1, DS, "/theRegisters/\registers_reg[22][8] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[5][8] /SE"; + 1, DS, "/theRegisters/\registers_reg[5][8] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[15][8] /SE"; + 1, DS, "/theRegisters/\registers_reg[15][8] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[12][8] /SE"; + 1, DS, "/theRegisters/\registers_reg[12][8] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[17][8] /SE"; + 1, DS, "/theRegisters/\registers_reg[17][8] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[30][8] /SE"; + 1, DS, "/theRegisters/\registers_reg[30][8] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[18][8] /SE"; + 1, DS, "/theRegisters/\registers_reg[18][8] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[28][8] /SE"; + 1, DS, "/theRegisters/\registers_reg[28][8] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[8][8] /SE"; + 1, DS, "/theRegisters/\registers_reg[8][8] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[25][8] /SE"; + 1, DS, "/theRegisters/\registers_reg[25][8] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[26][8] /SE"; + 1, DS, "/theRegisters/\registers_reg[26][8] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[10][8] /SE"; + 1, DS, "/theRegisters/\registers_reg[10][8] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[4][8] /SE"; + 1, DS, "/theRegisters/\registers_reg[4][8] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[31][8] /SE"; + 1, DS, "/theRegisters/\registers_reg[31][8] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[3][8] /SE"; + 1, DS, "/theRegisters/\registers_reg[3][8] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[7][8] /SE"; + 1, DS, "/theRegisters/\registers_reg[7][8] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[20][8] /SE"; + 1, DS, "/theRegisters/\registers_reg[20][8] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[24][8] /SE"; + 1, DS, "/theRegisters/\registers_reg[24][8] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[23][8] /SE"; + 1, DS, "/theRegisters/\registers_reg[23][8] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[29][8] /SE"; + 1, DS, "/theRegisters/\registers_reg[29][8] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[21][8] /SE"; + 1, DS, "/theRegisters/\registers_reg[21][8] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[13][8] /SE"; + 1, DS, "/theRegisters/\registers_reg[13][8] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[27][9] /SE"; + 1, DS, "/theRegisters/\registers_reg[27][9] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[11][9] /SE"; + 1, DS, "/theRegisters/\registers_reg[11][9] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[2][9] /SE"; + 1, DS, "/theRegisters/\registers_reg[2][9] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[19][9] /SE"; + 1, DS, "/theRegisters/\registers_reg[19][9] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[14][9] /SE"; + 1, DS, "/theRegisters/\registers_reg[14][9] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[6][9] /SE"; + 1, DS, "/theRegisters/\registers_reg[6][9] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[1][9] /SE"; + 1, DS, "/theRegisters/\registers_reg[1][9] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[9][9] /SE"; + 1, DS, "/theRegisters/\registers_reg[9][9] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[16][9] /SE"; + 1, DS, "/theRegisters/\registers_reg[16][9] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[22][9] /SE"; + 1, DS, "/theRegisters/\registers_reg[22][9] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[5][9] /SE"; + 1, DS, "/theRegisters/\registers_reg[5][9] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[15][9] /SE"; + 1, DS, "/theRegisters/\registers_reg[15][9] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[12][9] /SE"; + 1, DS, "/theRegisters/\registers_reg[12][9] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[17][9] /SE"; + 1, DS, "/theRegisters/\registers_reg[17][9] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[30][9] /SE"; + 1, DS, "/theRegisters/\registers_reg[30][9] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[18][9] /SE"; + 1, DS, "/theRegisters/\registers_reg[18][9] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[28][9] /SE"; + 1, DS, "/theRegisters/\registers_reg[28][9] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[8][9] /SE"; + 1, DS, "/theRegisters/\registers_reg[8][9] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[25][9] /SE"; + 1, DS, "/theRegisters/\registers_reg[25][9] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[26][9] /SE"; + 1, DS, "/theRegisters/\registers_reg[26][9] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[10][9] /SE"; + 1, DS, "/theRegisters/\registers_reg[10][9] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[4][9] /SE"; + 1, DS, "/theRegisters/\registers_reg[4][9] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[31][9] /SE"; + 1, DS, "/theRegisters/\registers_reg[31][9] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[3][9] /SE"; + 1, DS, "/theRegisters/\registers_reg[3][9] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[7][9] /SE"; + 1, DS, "/theRegisters/\registers_reg[7][9] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[20][9] /SE"; + 1, DS, "/theRegisters/\registers_reg[20][9] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[24][9] /SE"; + 1, DS, "/theRegisters/\registers_reg[24][9] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[23][9] /SE"; + 1, DS, "/theRegisters/\registers_reg[23][9] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[29][9] /SE"; + 1, DS, "/theRegisters/\registers_reg[29][9] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[21][9] /SE"; + 1, DS, "/theRegisters/\registers_reg[21][9] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[13][9] /SE"; + 1, DS, "/theRegisters/\registers_reg[13][9] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[2][10] /SE"; + 1, DS, "/theRegisters/\registers_reg[2][10] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[11][10] /SE"; + 1, DS, "/theRegisters/\registers_reg[11][10] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[3][10] /SE"; + 1, DS, "/theRegisters/\registers_reg[3][10] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[19][10] /SE"; + 1, DS, "/theRegisters/\registers_reg[19][10] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[14][10] /SE"; + 1, DS, "/theRegisters/\registers_reg[14][10] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[6][10] /SE"; + 1, DS, "/theRegisters/\registers_reg[6][10] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[1][10] /SE"; + 1, DS, "/theRegisters/\registers_reg[1][10] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[9][10] /SE"; + 1, DS, "/theRegisters/\registers_reg[9][10] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[16][10] /SE"; + 1, DS, "/theRegisters/\registers_reg[16][10] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[22][10] /SE"; + 1, DS, "/theRegisters/\registers_reg[22][10] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[5][10] /SE"; + 1, DS, "/theRegisters/\registers_reg[5][10] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[15][10] /SE"; + 1, DS, "/theRegisters/\registers_reg[15][10] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[12][10] /SE"; + 1, DS, "/theRegisters/\registers_reg[12][10] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[17][10] /SE"; + 1, DS, "/theRegisters/\registers_reg[17][10] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[26][10] /SE"; + 1, DS, "/theRegisters/\registers_reg[26][10] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[18][10] /SE"; + 1, DS, "/theRegisters/\registers_reg[18][10] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[13][10] /SE"; + 1, DS, "/theRegisters/\registers_reg[13][10] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[21][10] /SE"; + 1, DS, "/theRegisters/\registers_reg[21][10] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[25][10] /SE"; + 1, DS, "/theRegisters/\registers_reg[25][10] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[30][10] /SE"; + 1, DS, "/theRegisters/\registers_reg[30][10] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[10][10] /SE"; + 1, DS, "/theRegisters/\registers_reg[10][10] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[29][10] /SE"; + 1, DS, "/theRegisters/\registers_reg[29][10] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[27][10] /SE"; + 1, DS, "/theRegisters/\registers_reg[27][10] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[23][10] /SE"; + 1, DS, "/theRegisters/\registers_reg[23][10] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[4][10] /SE"; + 1, DS, "/theRegisters/\registers_reg[4][10] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[20][10] /SE"; + 1, DS, "/theRegisters/\registers_reg[20][10] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[24][10] /SE"; + 1, DS, "/theRegisters/\registers_reg[24][10] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[7][10] /SE"; + 1, DS, "/theRegisters/\registers_reg[7][10] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[31][10] /SE"; + 1, DS, "/theRegisters/\registers_reg[31][10] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[8][10] /SE"; + 1, DS, "/theRegisters/\registers_reg[8][10] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[28][10] /SE"; + 1, DS, "/theRegisters/\registers_reg[28][10] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[11][11] /SE"; + 1, DS, "/theRegisters/\registers_reg[11][11] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[27][11] /SE"; + 1, DS, "/theRegisters/\registers_reg[27][11] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[14][11] /SE"; + 1, DS, "/theRegisters/\registers_reg[14][11] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[7][11] /SE"; + 1, DS, "/theRegisters/\registers_reg[7][11] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[2][11] /SE"; + 1, DS, "/theRegisters/\registers_reg[2][11] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[19][11] /SE"; + 1, DS, "/theRegisters/\registers_reg[19][11] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[25][11] /SE"; + 1, DS, "/theRegisters/\registers_reg[25][11] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[13][11] /SE"; + 1, DS, "/theRegisters/\registers_reg[13][11] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[12][11] /SE"; + 1, DS, "/theRegisters/\registers_reg[12][11] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[24][11] /SE"; + 1, DS, "/theRegisters/\registers_reg[24][11] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[21][11] /SE"; + 1, DS, "/theRegisters/\registers_reg[21][11] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[22][11] /SE"; + 1, DS, "/theRegisters/\registers_reg[22][11] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[4][11] /SE"; + 1, DS, "/theRegisters/\registers_reg[4][11] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[20][11] /SE"; + 1, DS, "/theRegisters/\registers_reg[20][11] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[30][11] /SE"; + 1, DS, "/theRegisters/\registers_reg[30][11] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[18][11] /SE"; + 1, DS, "/theRegisters/\registers_reg[18][11] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[23][11] /SE"; + 1, DS, "/theRegisters/\registers_reg[23][11] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[15][11] /SE"; + 1, DS, "/theRegisters/\registers_reg[15][11] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[31][11] /SE"; + 1, DS, "/theRegisters/\registers_reg[31][11] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[16][11] /SE"; + 1, DS, "/theRegisters/\registers_reg[16][11] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[3][11] /SE"; + 1, DS, "/theRegisters/\registers_reg[3][11] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[5][11] /SE"; + 1, DS, "/theRegisters/\registers_reg[5][11] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[1][11] /SE"; + 1, DS, "/theRegisters/\registers_reg[1][11] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[6][11] /SE"; + 1, DS, "/theRegisters/\registers_reg[6][11] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[29][11] /SE"; + 1, DS, "/theRegisters/\registers_reg[29][11] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[9][11] /SE"; + 1, DS, "/theRegisters/\registers_reg[9][11] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[8][11] /SE"; + 1, DS, "/theRegisters/\registers_reg[8][11] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[26][11] /SE"; + 1, DS, "/theRegisters/\registers_reg[26][11] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[10][11] /SE"; + 1, DS, "/theRegisters/\registers_reg[10][11] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[17][11] /SE"; + 1, DS, "/theRegisters/\registers_reg[17][11] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[28][11] /SE"; + 1, DS, "/theRegisters/\registers_reg[28][11] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[11][12] /SE"; + 1, DS, "/theRegisters/\registers_reg[11][12] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[27][12] /SE"; + 1, DS, "/theRegisters/\registers_reg[27][12] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[14][12] /SE"; + 1, DS, "/theRegisters/\registers_reg[14][12] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[7][12] /SE"; + 1, DS, "/theRegisters/\registers_reg[7][12] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[2][12] /SE"; + 1, DS, "/theRegisters/\registers_reg[2][12] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[19][12] /SE"; + 1, DS, "/theRegisters/\registers_reg[19][12] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[25][12] /SE"; + 1, DS, "/theRegisters/\registers_reg[25][12] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[13][12] /SE"; + 1, DS, "/theRegisters/\registers_reg[13][12] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[12][12] /SE"; + 1, DS, "/theRegisters/\registers_reg[12][12] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[24][12] /SE"; + 1, DS, "/theRegisters/\registers_reg[24][12] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[21][12] /SE"; + 1, DS, "/theRegisters/\registers_reg[21][12] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[22][12] /SE"; + 1, DS, "/theRegisters/\registers_reg[22][12] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[4][12] /SE"; + 1, DS, "/theRegisters/\registers_reg[4][12] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[20][12] /SE"; + 1, DS, "/theRegisters/\registers_reg[20][12] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[30][12] /SE"; + 1, DS, "/theRegisters/\registers_reg[30][12] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[18][12] /SE"; + 1, DS, "/theRegisters/\registers_reg[18][12] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[23][12] /SE"; + 1, DS, "/theRegisters/\registers_reg[23][12] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[15][12] /SE"; + 1, DS, "/theRegisters/\registers_reg[15][12] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[31][12] /SE"; + 1, DS, "/theRegisters/\registers_reg[31][12] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[5][12] /SE"; + 1, DS, "/theRegisters/\registers_reg[5][12] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[3][12] /SE"; + 1, DS, "/theRegisters/\registers_reg[3][12] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[16][12] /SE"; + 1, DS, "/theRegisters/\registers_reg[16][12] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[1][12] /SE"; + 1, DS, "/theRegisters/\registers_reg[1][12] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[6][12] /SE"; + 1, DS, "/theRegisters/\registers_reg[6][12] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[29][12] /SE"; + 1, DS, "/theRegisters/\registers_reg[29][12] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[9][12] /SE"; + 1, DS, "/theRegisters/\registers_reg[9][12] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[8][12] /SE"; + 1, DS, "/theRegisters/\registers_reg[8][12] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[26][12] /SE"; + 1, DS, "/theRegisters/\registers_reg[26][12] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[10][12] /SE"; + 1, DS, "/theRegisters/\registers_reg[10][12] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[17][12] /SE"; + 1, DS, "/theRegisters/\registers_reg[17][12] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[28][12] /SE"; + 1, DS, "/theRegisters/\registers_reg[28][12] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[11][13] /SE"; + 1, DS, "/theRegisters/\registers_reg[11][13] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[27][13] /SE"; + 1, DS, "/theRegisters/\registers_reg[27][13] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[14][13] /SE"; + 1, DS, "/theRegisters/\registers_reg[14][13] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[7][13] /SE"; + 1, DS, "/theRegisters/\registers_reg[7][13] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[2][13] /SE"; + 1, DS, "/theRegisters/\registers_reg[2][13] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[19][13] /SE"; + 1, DS, "/theRegisters/\registers_reg[19][13] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[25][13] /SE"; + 1, DS, "/theRegisters/\registers_reg[25][13] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[13][13] /SE"; + 1, DS, "/theRegisters/\registers_reg[13][13] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[17][13] /SE"; + 1, DS, "/theRegisters/\registers_reg[17][13] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[20][13] /SE"; + 1, DS, "/theRegisters/\registers_reg[20][13] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[21][13] /SE"; + 1, DS, "/theRegisters/\registers_reg[21][13] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[22][13] /SE"; + 1, DS, "/theRegisters/\registers_reg[22][13] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[12][13] /SE"; + 1, DS, "/theRegisters/\registers_reg[12][13] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[24][13] /SE"; + 1, DS, "/theRegisters/\registers_reg[24][13] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[30][13] /SE"; + 1, DS, "/theRegisters/\registers_reg[30][13] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[18][13] /SE"; + 1, DS, "/theRegisters/\registers_reg[18][13] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[23][13] /SE"; + 1, DS, "/theRegisters/\registers_reg[23][13] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[15][13] /SE"; + 1, DS, "/theRegisters/\registers_reg[15][13] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[31][13] /SE"; + 1, DS, "/theRegisters/\registers_reg[31][13] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[16][13] /SE"; + 1, DS, "/theRegisters/\registers_reg[16][13] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[3][13] /SE"; + 1, DS, "/theRegisters/\registers_reg[3][13] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[5][13] /SE"; + 1, DS, "/theRegisters/\registers_reg[5][13] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[1][13] /SE"; + 1, DS, "/theRegisters/\registers_reg[1][13] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[6][13] /SE"; + 1, DS, "/theRegisters/\registers_reg[6][13] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[29][13] /SE"; + 1, DS, "/theRegisters/\registers_reg[29][13] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[9][13] /SE"; + 1, DS, "/theRegisters/\registers_reg[9][13] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[8][13] /SE"; + 1, DS, "/theRegisters/\registers_reg[8][13] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[26][13] /SE"; + 1, DS, "/theRegisters/\registers_reg[26][13] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[10][13] /SE"; + 1, DS, "/theRegisters/\registers_reg[10][13] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[4][13] /SE"; + 1, DS, "/theRegisters/\registers_reg[4][13] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[28][13] /SE"; + 1, DS, "/theRegisters/\registers_reg[28][13] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[11][14] /SE"; + 1, DS, "/theRegisters/\registers_reg[11][14] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[27][14] /SE"; + 1, DS, "/theRegisters/\registers_reg[27][14] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[7][14] /SE"; + 1, DS, "/theRegisters/\registers_reg[7][14] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[6][14] /SE"; + 1, DS, "/theRegisters/\registers_reg[6][14] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[25][14] /SE"; + 1, DS, "/theRegisters/\registers_reg[25][14] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[13][14] /SE"; + 1, DS, "/theRegisters/\registers_reg[13][14] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[22][14] /SE"; + 1, DS, "/theRegisters/\registers_reg[22][14] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[19][14] /SE"; + 1, DS, "/theRegisters/\registers_reg[19][14] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[12][14] /SE"; + 1, DS, "/theRegisters/\registers_reg[12][14] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[24][14] /SE"; + 1, DS, "/theRegisters/\registers_reg[24][14] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[2][14] /SE"; + 1, DS, "/theRegisters/\registers_reg[2][14] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[1][14] /SE"; + 1, DS, "/theRegisters/\registers_reg[1][14] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[4][14] /SE"; + 1, DS, "/theRegisters/\registers_reg[4][14] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[20][14] /SE"; + 1, DS, "/theRegisters/\registers_reg[20][14] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[30][14] /SE"; + 1, DS, "/theRegisters/\registers_reg[30][14] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[26][14] /SE"; + 1, DS, "/theRegisters/\registers_reg[26][14] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[23][14] /SE"; + 1, DS, "/theRegisters/\registers_reg[23][14] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[15][14] /SE"; + 1, DS, "/theRegisters/\registers_reg[15][14] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[31][14] /SE"; + 1, DS, "/theRegisters/\registers_reg[31][14] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[17][14] /SE"; + 1, DS, "/theRegisters/\registers_reg[17][14] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[3][14] /SE"; + 1, DS, "/theRegisters/\registers_reg[3][14] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[16][14] /SE"; + 1, DS, "/theRegisters/\registers_reg[16][14] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[14][14] /SE"; + 1, DS, "/theRegisters/\registers_reg[14][14] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[21][14] /SE"; + 1, DS, "/theRegisters/\registers_reg[21][14] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[29][14] /SE"; + 1, DS, "/theRegisters/\registers_reg[29][14] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[9][14] /SE"; + 1, DS, "/theRegisters/\registers_reg[9][14] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[8][14] /SE"; + 1, DS, "/theRegisters/\registers_reg[8][14] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[10][14] /SE"; + 1, DS, "/theRegisters/\registers_reg[10][14] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[18][14] /SE"; + 1, DS, "/theRegisters/\registers_reg[18][14] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[5][14] /SE"; + 1, DS, "/theRegisters/\registers_reg[5][14] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[28][14] /SE"; + 1, DS, "/theRegisters/\registers_reg[28][14] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[31][15] /SE"; + 1, DS, "/theRegisters/\registers_reg[31][15] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[27][15] /SE"; + 1, DS, "/theRegisters/\registers_reg[27][15] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[3][15] /SE"; + 1, DS, "/theRegisters/\registers_reg[3][15] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[23][15] /SE"; + 1, DS, "/theRegisters/\registers_reg[23][15] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[29][15] /SE"; + 1, DS, "/theRegisters/\registers_reg[29][15] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[9][15] /SE"; + 1, DS, "/theRegisters/\registers_reg[9][15] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[14][15] /SE"; + 1, DS, "/theRegisters/\registers_reg[14][15] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[7][15] /SE"; + 1, DS, "/theRegisters/\registers_reg[7][15] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[25][15] /SE"; + 1, DS, "/theRegisters/\registers_reg[25][15] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[19][15] /SE"; + 1, DS, "/theRegisters/\registers_reg[19][15] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[16][15] /SE"; + 1, DS, "/theRegisters/\registers_reg[16][15] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[6][15] /SE"; + 1, DS, "/theRegisters/\registers_reg[6][15] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[5][15] /SE"; + 1, DS, "/theRegisters/\registers_reg[5][15] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[4][15] /SE"; + 1, DS, "/theRegisters/\registers_reg[4][15] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[26][15] /SE"; + 1, DS, "/theRegisters/\registers_reg[26][15] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[18][15] /SE"; + 1, DS, "/theRegisters/\registers_reg[18][15] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[28][15] /SE"; + 1, DS, "/theRegisters/\registers_reg[28][15] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[1][15] /SE"; + 1, DS, "/theRegisters/\registers_reg[1][15] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[22][15] /SE"; + 1, DS, "/theRegisters/\registers_reg[22][15] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[30][15] /SE"; + 1, DS, "/theRegisters/\registers_reg[30][15] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[13][15] /SE"; + 1, DS, "/theRegisters/\registers_reg[13][15] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[24][15] /SE"; + 1, DS, "/theRegisters/\registers_reg[24][15] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[11][15] /SE"; + 1, DS, "/theRegisters/\registers_reg[11][15] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[8][15] /SE"; + 1, DS, "/theRegisters/\registers_reg[8][15] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[15][15] /SE"; + 1, DS, "/theRegisters/\registers_reg[15][15] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[12][15] /SE"; + 1, DS, "/theRegisters/\registers_reg[12][15] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[20][15] /SE"; + 1, DS, "/theRegisters/\registers_reg[20][15] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[2][15] /SE"; + 1, DS, "/theRegisters/\registers_reg[2][15] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[10][15] /SE"; + 1, DS, "/theRegisters/\registers_reg[10][15] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[21][15] /SE"; + 1, DS, "/theRegisters/\registers_reg[21][15] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[17][15] /SE"; + 1, DS, "/theRegisters/\registers_reg[17][15] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[3][16] /SE"; + 1, DS, "/theRegisters/\registers_reg[3][16] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[27][16] /SE"; + 1, DS, "/theRegisters/\registers_reg[27][16] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[14][16] /SE"; + 1, DS, "/theRegisters/\registers_reg[14][16] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[15][16] /SE"; + 1, DS, "/theRegisters/\registers_reg[15][16] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[17][16] /SE"; + 1, DS, "/theRegisters/\registers_reg[17][16] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[13][16] /SE"; + 1, DS, "/theRegisters/\registers_reg[13][16] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[23][16] /SE"; + 1, DS, "/theRegisters/\registers_reg[23][16] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[8][16] /SE"; + 1, DS, "/theRegisters/\registers_reg[8][16] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[30][16] /SE"; + 1, DS, "/theRegisters/\registers_reg[30][16] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[26][16] /SE"; + 1, DS, "/theRegisters/\registers_reg[26][16] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[20][16] /SE"; + 1, DS, "/theRegisters/\registers_reg[20][16] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[24][16] /SE"; + 1, DS, "/theRegisters/\registers_reg[24][16] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[21][16] /SE"; + 1, DS, "/theRegisters/\registers_reg[21][16] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[19][16] /SE"; + 1, DS, "/theRegisters/\registers_reg[19][16] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[12][16] /SE"; + 1, DS, "/theRegisters/\registers_reg[12][16] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[4][16] /SE"; + 1, DS, "/theRegisters/\registers_reg[4][16] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[28][16] /SE"; + 1, DS, "/theRegisters/\registers_reg[28][16] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[5][16] /SE"; + 1, DS, "/theRegisters/\registers_reg[5][16] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[1][16] /SE"; + 1, DS, "/theRegisters/\registers_reg[1][16] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[22][16] /SE"; + 1, DS, "/theRegisters/\registers_reg[22][16] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[18][16] /SE"; + 1, DS, "/theRegisters/\registers_reg[18][16] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[6][16] /SE"; + 1, DS, "/theRegisters/\registers_reg[6][16] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[31][16] /SE"; + 1, DS, "/theRegisters/\registers_reg[31][16] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[16][16] /SE"; + 1, DS, "/theRegisters/\registers_reg[16][16] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[10][16] /SE"; + 1, DS, "/theRegisters/\registers_reg[10][16] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[7][16] /SE"; + 1, DS, "/theRegisters/\registers_reg[7][16] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[9][16] /SE"; + 1, DS, "/theRegisters/\registers_reg[9][16] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[25][16] /SE"; + 1, DS, "/theRegisters/\registers_reg[25][16] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[11][16] /SE"; + 1, DS, "/theRegisters/\registers_reg[11][16] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[2][16] /SE"; + 1, DS, "/theRegisters/\registers_reg[2][16] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[29][16] /SE"; + 1, DS, "/theRegisters/\registers_reg[29][16] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[3][17] /SE"; + 1, DS, "/theRegisters/\registers_reg[3][17] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[27][17] /SE"; + 1, DS, "/theRegisters/\registers_reg[27][17] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[23][17] /SE"; + 1, DS, "/theRegisters/\registers_reg[23][17] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[8][17] /SE"; + 1, DS, "/theRegisters/\registers_reg[8][17] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[29][17] /SE"; + 1, DS, "/theRegisters/\registers_reg[29][17] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[9][17] /SE"; + 1, DS, "/theRegisters/\registers_reg[9][17] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[14][17] /SE"; + 1, DS, "/theRegisters/\registers_reg[14][17] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[7][17] /SE"; + 1, DS, "/theRegisters/\registers_reg[7][17] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[16][17] /SE"; + 1, DS, "/theRegisters/\registers_reg[16][17] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[19][17] /SE"; + 1, DS, "/theRegisters/\registers_reg[19][17] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[25][17] /SE"; + 1, DS, "/theRegisters/\registers_reg[25][17] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[6][17] /SE"; + 1, DS, "/theRegisters/\registers_reg[6][17] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[5][17] /SE"; + 1, DS, "/theRegisters/\registers_reg[5][17] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[4][17] /SE"; + 1, DS, "/theRegisters/\registers_reg[4][17] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[30][17] /SE"; + 1, DS, "/theRegisters/\registers_reg[30][17] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[18][17] /SE"; + 1, DS, "/theRegisters/\registers_reg[18][17] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[28][17] /SE"; + 1, DS, "/theRegisters/\registers_reg[28][17] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[1][17] /SE"; + 1, DS, "/theRegisters/\registers_reg[1][17] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[13][17] /SE"; + 1, DS, "/theRegisters/\registers_reg[13][17] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[26][17] /SE"; + 1, DS, "/theRegisters/\registers_reg[26][17] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[22][17] /SE"; + 1, DS, "/theRegisters/\registers_reg[22][17] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[24][17] /SE"; + 1, DS, "/theRegisters/\registers_reg[24][17] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[10][17] /SE"; + 1, DS, "/theRegisters/\registers_reg[10][17] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[11][17] /SE"; + 1, DS, "/theRegisters/\registers_reg[11][17] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[15][17] /SE"; + 1, DS, "/theRegisters/\registers_reg[15][17] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[12][17] /SE"; + 1, DS, "/theRegisters/\registers_reg[12][17] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[20][17] /SE"; + 1, DS, "/theRegisters/\registers_reg[20][17] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[31][17] /SE"; + 1, DS, "/theRegisters/\registers_reg[31][17] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[2][17] /SE"; + 1, DS, "/theRegisters/\registers_reg[2][17] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[21][17] /SE"; + 1, DS, "/theRegisters/\registers_reg[21][17] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[17][17] /SE"; + 1, DS, "/theRegisters/\registers_reg[17][17] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[3][18] /SE"; + 1, DS, "/theRegisters/\registers_reg[3][18] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[10][18] /SE"; + 1, DS, "/theRegisters/\registers_reg[10][18] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[14][18] /SE"; + 1, DS, "/theRegisters/\registers_reg[14][18] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[15][18] /SE"; + 1, DS, "/theRegisters/\registers_reg[15][18] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[17][18] /SE"; + 1, DS, "/theRegisters/\registers_reg[17][18] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[13][18] /SE"; + 1, DS, "/theRegisters/\registers_reg[13][18] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[23][18] /SE"; + 1, DS, "/theRegisters/\registers_reg[23][18] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[8][18] /SE"; + 1, DS, "/theRegisters/\registers_reg[8][18] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[20][18] /SE"; + 1, DS, "/theRegisters/\registers_reg[20][18] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[5][18] /SE"; + 1, DS, "/theRegisters/\registers_reg[5][18] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[21][18] /SE"; + 1, DS, "/theRegisters/\registers_reg[21][18] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[19][18] /SE"; + 1, DS, "/theRegisters/\registers_reg[19][18] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[12][18] /SE"; + 1, DS, "/theRegisters/\registers_reg[12][18] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[4][18] /SE"; + 1, DS, "/theRegisters/\registers_reg[4][18] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[30][18] /SE"; + 1, DS, "/theRegisters/\registers_reg[30][18] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[18][18] /SE"; + 1, DS, "/theRegisters/\registers_reg[18][18] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[2][18] /SE"; + 1, DS, "/theRegisters/\registers_reg[2][18] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[29][18] /SE"; + 1, DS, "/theRegisters/\registers_reg[29][18] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[1][18] /SE"; + 1, DS, "/theRegisters/\registers_reg[1][18] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[26][18] /SE"; + 1, DS, "/theRegisters/\registers_reg[26][18] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[22][18] /SE"; + 1, DS, "/theRegisters/\registers_reg[22][18] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[6][18] /SE"; + 1, DS, "/theRegisters/\registers_reg[6][18] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[31][18] /SE"; + 1, DS, "/theRegisters/\registers_reg[31][18] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[25][18] /SE"; + 1, DS, "/theRegisters/\registers_reg[25][18] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[27][18] /SE"; + 1, DS, "/theRegisters/\registers_reg[27][18] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[7][18] /SE"; + 1, DS, "/theRegisters/\registers_reg[7][18] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[9][18] /SE"; + 1, DS, "/theRegisters/\registers_reg[9][18] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[16][18] /SE"; + 1, DS, "/theRegisters/\registers_reg[16][18] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[11][18] /SE"; + 1, DS, "/theRegisters/\registers_reg[11][18] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[28][18] /SE"; + 1, DS, "/theRegisters/\registers_reg[28][18] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[24][18] /SE"; + 1, DS, "/theRegisters/\registers_reg[24][18] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[3][19] /SE"; + 1, DS, "/theRegisters/\registers_reg[3][19] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[10][19] /SE"; + 1, DS, "/theRegisters/\registers_reg[10][19] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[14][19] /SE"; + 1, DS, "/theRegisters/\registers_reg[14][19] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[7][19] /SE"; + 1, DS, "/theRegisters/\registers_reg[7][19] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[23][19] /SE"; + 1, DS, "/theRegisters/\registers_reg[23][19] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[8][19] /SE"; + 1, DS, "/theRegisters/\registers_reg[8][19] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[29][19] /SE"; + 1, DS, "/theRegisters/\registers_reg[29][19] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[9][19] /SE"; + 1, DS, "/theRegisters/\registers_reg[9][19] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[16][19] /SE"; + 1, DS, "/theRegisters/\registers_reg[16][19] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[19][19] /SE"; + 1, DS, "/theRegisters/\registers_reg[19][19] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[25][19] /SE"; + 1, DS, "/theRegisters/\registers_reg[25][19] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[6][19] /SE"; + 1, DS, "/theRegisters/\registers_reg[6][19] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[5][19] /SE"; + 1, DS, "/theRegisters/\registers_reg[5][19] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[4][19] /SE"; + 1, DS, "/theRegisters/\registers_reg[4][19] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[30][19] /SE"; + 1, DS, "/theRegisters/\registers_reg[30][19] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[18][19] /SE"; + 1, DS, "/theRegisters/\registers_reg[18][19] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[28][19] /SE"; + 1, DS, "/theRegisters/\registers_reg[28][19] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[1][19] /SE"; + 1, DS, "/theRegisters/\registers_reg[1][19] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[13][19] /SE"; + 1, DS, "/theRegisters/\registers_reg[13][19] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[26][19] /SE"; + 1, DS, "/theRegisters/\registers_reg[26][19] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[22][19] /SE"; + 1, DS, "/theRegisters/\registers_reg[22][19] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[24][19] /SE"; + 1, DS, "/theRegisters/\registers_reg[24][19] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[27][19] /SE"; + 1, DS, "/theRegisters/\registers_reg[27][19] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[11][19] /SE"; + 1, DS, "/theRegisters/\registers_reg[11][19] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[15][19] /SE"; + 1, DS, "/theRegisters/\registers_reg[15][19] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[12][19] /SE"; + 1, DS, "/theRegisters/\registers_reg[12][19] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[20][19] /SE"; + 1, DS, "/theRegisters/\registers_reg[20][19] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[31][19] /SE"; + 1, DS, "/theRegisters/\registers_reg[31][19] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[2][19] /SE"; + 1, DS, "/theRegisters/\registers_reg[2][19] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[21][19] /SE"; + 1, DS, "/theRegisters/\registers_reg[21][19] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[17][19] /SE"; + 1, DS, "/theRegisters/\registers_reg[17][19] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[31][20] /SE"; + 1, DS, "/theRegisters/\registers_reg[31][20] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[27][20] /SE"; + 1, DS, "/theRegisters/\registers_reg[27][20] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[3][20] /SE"; + 1, DS, "/theRegisters/\registers_reg[3][20] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[23][20] /SE"; + 1, DS, "/theRegisters/\registers_reg[23][20] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[29][20] /SE"; + 1, DS, "/theRegisters/\registers_reg[29][20] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[9][20] /SE"; + 1, DS, "/theRegisters/\registers_reg[9][20] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[14][20] /SE"; + 1, DS, "/theRegisters/\registers_reg[14][20] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[7][20] /SE"; + 1, DS, "/theRegisters/\registers_reg[7][20] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[16][20] /SE"; + 1, DS, "/theRegisters/\registers_reg[16][20] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[19][20] /SE"; + 1, DS, "/theRegisters/\registers_reg[19][20] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[25][20] /SE"; + 1, DS, "/theRegisters/\registers_reg[25][20] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[6][20] /SE"; + 1, DS, "/theRegisters/\registers_reg[6][20] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[4][20] /SE"; + 1, DS, "/theRegisters/\registers_reg[4][20] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[24][20] /SE"; + 1, DS, "/theRegisters/\registers_reg[24][20] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[26][20] /SE"; + 1, DS, "/theRegisters/\registers_reg[26][20] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[18][20] /SE"; + 1, DS, "/theRegisters/\registers_reg[18][20] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[28][20] /SE"; + 1, DS, "/theRegisters/\registers_reg[28][20] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[1][20] /SE"; + 1, DS, "/theRegisters/\registers_reg[1][20] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[22][20] /SE"; + 1, DS, "/theRegisters/\registers_reg[22][20] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[30][20] /SE"; + 1, DS, "/theRegisters/\registers_reg[30][20] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[13][20] /SE"; + 1, DS, "/theRegisters/\registers_reg[13][20] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[5][20] /SE"; + 1, DS, "/theRegisters/\registers_reg[5][20] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[11][20] /SE"; + 1, DS, "/theRegisters/\registers_reg[11][20] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[8][20] /SE"; + 1, DS, "/theRegisters/\registers_reg[8][20] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[15][20] /SE"; + 1, DS, "/theRegisters/\registers_reg[15][20] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[12][20] /SE"; + 1, DS, "/theRegisters/\registers_reg[12][20] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[20][20] /SE"; + 1, DS, "/theRegisters/\registers_reg[20][20] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[2][20] /SE"; + 1, DS, "/theRegisters/\registers_reg[2][20] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[10][20] /SE"; + 1, DS, "/theRegisters/\registers_reg[10][20] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[21][20] /SE"; + 1, DS, "/theRegisters/\registers_reg[21][20] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[17][20] /SE"; + 1, DS, "/theRegisters/\registers_reg[17][20] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[31][21] /SE"; + 1, DS, "/theRegisters/\registers_reg[31][21] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[27][21] /SE"; + 1, DS, "/theRegisters/\registers_reg[27][21] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[3][21] /SE"; + 1, DS, "/theRegisters/\registers_reg[3][21] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[23][21] /SE"; + 1, DS, "/theRegisters/\registers_reg[23][21] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[29][21] /SE"; + 1, DS, "/theRegisters/\registers_reg[29][21] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[9][21] /SE"; + 1, DS, "/theRegisters/\registers_reg[9][21] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[14][21] /SE"; + 1, DS, "/theRegisters/\registers_reg[14][21] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[7][21] /SE"; + 1, DS, "/theRegisters/\registers_reg[7][21] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[25][21] /SE"; + 1, DS, "/theRegisters/\registers_reg[25][21] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[19][21] /SE"; + 1, DS, "/theRegisters/\registers_reg[19][21] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[16][21] /SE"; + 1, DS, "/theRegisters/\registers_reg[16][21] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[15][21] /SE"; + 1, DS, "/theRegisters/\registers_reg[15][21] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[4][21] /SE"; + 1, DS, "/theRegisters/\registers_reg[4][21] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[24][21] /SE"; + 1, DS, "/theRegisters/\registers_reg[24][21] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[26][21] /SE"; + 1, DS, "/theRegisters/\registers_reg[26][21] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[18][21] /SE"; + 1, DS, "/theRegisters/\registers_reg[18][21] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[28][21] /SE"; + 1, DS, "/theRegisters/\registers_reg[28][21] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[1][21] /SE"; + 1, DS, "/theRegisters/\registers_reg[1][21] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[22][21] /SE"; + 1, DS, "/theRegisters/\registers_reg[22][21] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[30][21] /SE"; + 1, DS, "/theRegisters/\registers_reg[30][21] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[13][21] /SE"; + 1, DS, "/theRegisters/\registers_reg[13][21] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[2][21] /SE"; + 1, DS, "/theRegisters/\registers_reg[2][21] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[10][21] /SE"; + 1, DS, "/theRegisters/\registers_reg[10][21] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[11][21] /SE"; + 1, DS, "/theRegisters/\registers_reg[11][21] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[5][21] /SE"; + 1, DS, "/theRegisters/\registers_reg[5][21] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[12][21] /SE"; + 1, DS, "/theRegisters/\registers_reg[12][21] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[20][21] /SE"; + 1, DS, "/theRegisters/\registers_reg[20][21] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[8][21] /SE"; + 1, DS, "/theRegisters/\registers_reg[8][21] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[6][21] /SE"; + 1, DS, "/theRegisters/\registers_reg[6][21] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[21][21] /SE"; + 1, DS, "/theRegisters/\registers_reg[21][21] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[17][21] /SE"; + 1, DS, "/theRegisters/\registers_reg[17][21] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[3][22] /SE"; + 1, DS, "/theRegisters/\registers_reg[3][22] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[27][22] /SE"; + 1, DS, "/theRegisters/\registers_reg[27][22] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[23][22] /SE"; + 1, DS, "/theRegisters/\registers_reg[23][22] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[8][22] /SE"; + 1, DS, "/theRegisters/\registers_reg[8][22] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[29][22] /SE"; + 1, DS, "/theRegisters/\registers_reg[29][22] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[9][22] /SE"; + 1, DS, "/theRegisters/\registers_reg[9][22] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[14][22] /SE"; + 1, DS, "/theRegisters/\registers_reg[14][22] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[7][22] /SE"; + 1, DS, "/theRegisters/\registers_reg[7][22] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[25][22] /SE"; + 1, DS, "/theRegisters/\registers_reg[25][22] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[19][22] /SE"; + 1, DS, "/theRegisters/\registers_reg[19][22] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[16][22] /SE"; + 1, DS, "/theRegisters/\registers_reg[16][22] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[15][22] /SE"; + 1, DS, "/theRegisters/\registers_reg[15][22] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[4][22] /SE"; + 1, DS, "/theRegisters/\registers_reg[4][22] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[24][22] /SE"; + 1, DS, "/theRegisters/\registers_reg[24][22] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[30][22] /SE"; + 1, DS, "/theRegisters/\registers_reg[30][22] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[18][22] /SE"; + 1, DS, "/theRegisters/\registers_reg[18][22] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[28][22] /SE"; + 1, DS, "/theRegisters/\registers_reg[28][22] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[1][22] /SE"; + 1, DS, "/theRegisters/\registers_reg[1][22] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[13][22] /SE"; + 1, DS, "/theRegisters/\registers_reg[13][22] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[26][22] /SE"; + 1, DS, "/theRegisters/\registers_reg[26][22] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[22][22] /SE"; + 1, DS, "/theRegisters/\registers_reg[22][22] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[2][22] /SE"; + 1, DS, "/theRegisters/\registers_reg[2][22] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[31][22] /SE"; + 1, DS, "/theRegisters/\registers_reg[31][22] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[5][22] /SE"; + 1, DS, "/theRegisters/\registers_reg[5][22] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[10][22] /SE"; + 1, DS, "/theRegisters/\registers_reg[10][22] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[12][22] /SE"; + 1, DS, "/theRegisters/\registers_reg[12][22] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[20][22] /SE"; + 1, DS, "/theRegisters/\registers_reg[20][22] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[11][22] /SE"; + 1, DS, "/theRegisters/\registers_reg[11][22] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[6][22] /SE"; + 1, DS, "/theRegisters/\registers_reg[6][22] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[21][22] /SE"; + 1, DS, "/theRegisters/\registers_reg[21][22] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[17][22] /SE"; + 1, DS, "/theRegisters/\registers_reg[17][22] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[10][23] /SE"; + 1, DS, "/theRegisters/\registers_reg[10][23] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[2][23] /SE"; + 1, DS, "/theRegisters/\registers_reg[2][23] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[12][23] /SE"; + 1, DS, "/theRegisters/\registers_reg[12][23] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[4][23] /SE"; + 1, DS, "/theRegisters/\registers_reg[4][23] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[5][23] /SE"; + 1, DS, "/theRegisters/\registers_reg[5][23] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[13][23] /SE"; + 1, DS, "/theRegisters/\registers_reg[13][23] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[11][23] /SE"; + 1, DS, "/theRegisters/\registers_reg[11][23] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[27][23] /SE"; + 1, DS, "/theRegisters/\registers_reg[27][23] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[25][23] /SE"; + 1, DS, "/theRegisters/\registers_reg[25][23] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[6][23] /SE"; + 1, DS, "/theRegisters/\registers_reg[6][23] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[7][23] /SE"; + 1, DS, "/theRegisters/\registers_reg[7][23] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[16][23] /SE"; + 1, DS, "/theRegisters/\registers_reg[16][23] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[14][23] /SE"; + 1, DS, "/theRegisters/\registers_reg[14][23] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[15][23] /SE"; + 1, DS, "/theRegisters/\registers_reg[15][23] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[24][23] /SE"; + 1, DS, "/theRegisters/\registers_reg[24][23] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[17][23] /SE"; + 1, DS, "/theRegisters/\registers_reg[17][23] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[8][23] /SE"; + 1, DS, "/theRegisters/\registers_reg[8][23] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[31][23] /SE"; + 1, DS, "/theRegisters/\registers_reg[31][23] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[30][23] /SE"; + 1, DS, "/theRegisters/\registers_reg[30][23] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[3][23] /SE"; + 1, DS, "/theRegisters/\registers_reg[3][23] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[29][23] /SE"; + 1, DS, "/theRegisters/\registers_reg[29][23] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[23][23] /SE"; + 1, DS, "/theRegisters/\registers_reg[23][23] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[26][23] /SE"; + 1, DS, "/theRegisters/\registers_reg[26][23] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[19][23] /SE"; + 1, DS, "/theRegisters/\registers_reg[19][23] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[20][23] /SE"; + 1, DS, "/theRegisters/\registers_reg[20][23] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[21][23] /SE"; + 1, DS, "/theRegisters/\registers_reg[21][23] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[1][23] /SE"; + 1, DS, "/theRegisters/\registers_reg[1][23] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[22][23] /SE"; + 1, DS, "/theRegisters/\registers_reg[22][23] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[18][23] /SE"; + 1, DS, "/theRegisters/\registers_reg[18][23] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[28][23] /SE"; + 1, DS, "/theRegisters/\registers_reg[28][23] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[9][23] /SE"; + 1, DS, "/theRegisters/\registers_reg[9][23] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[31][24] /SE"; + 1, DS, "/theRegisters/\registers_reg[31][24] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[27][24] /SE"; + 1, DS, "/theRegisters/\registers_reg[27][24] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[3][24] /SE"; + 1, DS, "/theRegisters/\registers_reg[3][24] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[23][24] /SE"; + 1, DS, "/theRegisters/\registers_reg[23][24] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[29][24] /SE"; + 1, DS, "/theRegisters/\registers_reg[29][24] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[9][24] /SE"; + 1, DS, "/theRegisters/\registers_reg[9][24] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[14][24] /SE"; + 1, DS, "/theRegisters/\registers_reg[14][24] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[7][24] /SE"; + 1, DS, "/theRegisters/\registers_reg[7][24] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[16][24] /SE"; + 1, DS, "/theRegisters/\registers_reg[16][24] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[19][24] /SE"; + 1, DS, "/theRegisters/\registers_reg[19][24] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[25][24] /SE"; + 1, DS, "/theRegisters/\registers_reg[25][24] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[15][24] /SE"; + 1, DS, "/theRegisters/\registers_reg[15][24] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[4][24] /SE"; + 1, DS, "/theRegisters/\registers_reg[4][24] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[24][24] /SE"; + 1, DS, "/theRegisters/\registers_reg[24][24] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[26][24] /SE"; + 1, DS, "/theRegisters/\registers_reg[26][24] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[18][24] /SE"; + 1, DS, "/theRegisters/\registers_reg[18][24] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[28][24] /SE"; + 1, DS, "/theRegisters/\registers_reg[28][24] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[1][24] /SE"; + 1, DS, "/theRegisters/\registers_reg[1][24] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[22][24] /SE"; + 1, DS, "/theRegisters/\registers_reg[22][24] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[30][24] /SE"; + 1, DS, "/theRegisters/\registers_reg[30][24] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[13][24] /SE"; + 1, DS, "/theRegisters/\registers_reg[13][24] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[2][24] /SE"; + 1, DS, "/theRegisters/\registers_reg[2][24] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[10][24] /SE"; + 1, DS, "/theRegisters/\registers_reg[10][24] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[11][24] /SE"; + 1, DS, "/theRegisters/\registers_reg[11][24] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[5][24] /SE"; + 1, DS, "/theRegisters/\registers_reg[5][24] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[12][24] /SE"; + 1, DS, "/theRegisters/\registers_reg[12][24] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[20][24] /SE"; + 1, DS, "/theRegisters/\registers_reg[20][24] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[8][24] /SE"; + 1, DS, "/theRegisters/\registers_reg[8][24] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[6][24] /SE"; + 1, DS, "/theRegisters/\registers_reg[6][24] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[21][24] /SE"; + 1, DS, "/theRegisters/\registers_reg[21][24] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[17][24] /SE"; + 1, DS, "/theRegisters/\registers_reg[17][24] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[31][25] /SE"; + 1, DS, "/theRegisters/\registers_reg[31][25] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[27][25] /SE"; + 1, DS, "/theRegisters/\registers_reg[27][25] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[3][25] /SE"; + 1, DS, "/theRegisters/\registers_reg[3][25] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[23][25] /SE"; + 1, DS, "/theRegisters/\registers_reg[23][25] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[29][25] /SE"; + 1, DS, "/theRegisters/\registers_reg[29][25] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[9][25] /SE"; + 1, DS, "/theRegisters/\registers_reg[9][25] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[14][25] /SE"; + 1, DS, "/theRegisters/\registers_reg[14][25] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[7][25] /SE"; + 1, DS, "/theRegisters/\registers_reg[7][25] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[25][25] /SE"; + 1, DS, "/theRegisters/\registers_reg[25][25] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[19][25] /SE"; + 1, DS, "/theRegisters/\registers_reg[19][25] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[16][25] /SE"; + 1, DS, "/theRegisters/\registers_reg[16][25] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[15][25] /SE"; + 1, DS, "/theRegisters/\registers_reg[15][25] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[4][25] /SE"; + 1, DS, "/theRegisters/\registers_reg[4][25] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[24][25] /SE"; + 1, DS, "/theRegisters/\registers_reg[24][25] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[26][25] /SE"; + 1, DS, "/theRegisters/\registers_reg[26][25] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[18][25] /SE"; + 1, DS, "/theRegisters/\registers_reg[18][25] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[28][25] /SE"; + 1, DS, "/theRegisters/\registers_reg[28][25] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[1][25] /SE"; + 1, DS, "/theRegisters/\registers_reg[1][25] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[22][25] /SE"; + 1, DS, "/theRegisters/\registers_reg[22][25] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[30][25] /SE"; + 1, DS, "/theRegisters/\registers_reg[30][25] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[13][25] /SE"; + 1, DS, "/theRegisters/\registers_reg[13][25] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[2][25] /SE"; + 1, DS, "/theRegisters/\registers_reg[2][25] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[10][25] /SE"; + 1, DS, "/theRegisters/\registers_reg[10][25] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[11][25] /SE"; + 1, DS, "/theRegisters/\registers_reg[11][25] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[5][25] /SE"; + 1, DS, "/theRegisters/\registers_reg[5][25] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[12][25] /SE"; + 1, DS, "/theRegisters/\registers_reg[12][25] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[20][25] /SE"; + 1, DS, "/theRegisters/\registers_reg[20][25] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[8][25] /SE"; + 1, DS, "/theRegisters/\registers_reg[8][25] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[6][25] /SE"; + 1, DS, "/theRegisters/\registers_reg[6][25] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[21][25] /SE"; + 1, DS, "/theRegisters/\registers_reg[21][25] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[17][25] /SE"; + 1, DS, "/theRegisters/\registers_reg[17][25] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[3][26] /SE"; + 1, DS, "/theRegisters/\registers_reg[3][26] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[10][26] /SE"; + 1, DS, "/theRegisters/\registers_reg[10][26] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[14][26] /SE"; + 1, DS, "/theRegisters/\registers_reg[14][26] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[15][26] /SE"; + 1, DS, "/theRegisters/\registers_reg[15][26] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[17][26] /SE"; + 1, DS, "/theRegisters/\registers_reg[17][26] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[13][26] /SE"; + 1, DS, "/theRegisters/\registers_reg[13][26] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[23][26] /SE"; + 1, DS, "/theRegisters/\registers_reg[23][26] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[8][26] /SE"; + 1, DS, "/theRegisters/\registers_reg[8][26] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[30][26] /SE"; + 1, DS, "/theRegisters/\registers_reg[30][26] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[26][26] /SE"; + 1, DS, "/theRegisters/\registers_reg[26][26] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[20][26] /SE"; + 1, DS, "/theRegisters/\registers_reg[20][26] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[24][26] /SE"; + 1, DS, "/theRegisters/\registers_reg[24][26] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[21][26] /SE"; + 1, DS, "/theRegisters/\registers_reg[21][26] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[19][26] /SE"; + 1, DS, "/theRegisters/\registers_reg[19][26] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[12][26] /SE"; + 1, DS, "/theRegisters/\registers_reg[12][26] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[4][26] /SE"; + 1, DS, "/theRegisters/\registers_reg[4][26] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[28][26] /SE"; + 1, DS, "/theRegisters/\registers_reg[28][26] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[5][26] /SE"; + 1, DS, "/theRegisters/\registers_reg[5][26] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[6][26] /SE"; + 1, DS, "/theRegisters/\registers_reg[6][26] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[31][26] /SE"; + 1, DS, "/theRegisters/\registers_reg[31][26] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[16][26] /SE"; + 1, DS, "/theRegisters/\registers_reg[16][26] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[27][26] /SE"; + 1, DS, "/theRegisters/\registers_reg[27][26] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[25][26] /SE"; + 1, DS, "/theRegisters/\registers_reg[25][26] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[11][26] /SE"; + 1, DS, "/theRegisters/\registers_reg[11][26] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[7][26] /SE"; + 1, DS, "/theRegisters/\registers_reg[7][26] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[9][26] /SE"; + 1, DS, "/theRegisters/\registers_reg[9][26] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[2][26] /SE"; + 1, DS, "/theRegisters/\registers_reg[2][26] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[29][26] /SE"; + 1, DS, "/theRegisters/\registers_reg[29][26] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[1][26] /SE"; + 1, DS, "/theRegisters/\registers_reg[1][26] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[22][26] /SE"; + 1, DS, "/theRegisters/\registers_reg[22][26] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[18][26] /SE"; + 1, DS, "/theRegisters/\registers_reg[18][26] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[31][27] /SE"; + 1, DS, "/theRegisters/\registers_reg[31][27] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[27][27] /SE"; + 1, DS, "/theRegisters/\registers_reg[27][27] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[14][27] /SE"; + 1, DS, "/theRegisters/\registers_reg[14][27] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[15][27] /SE"; + 1, DS, "/theRegisters/\registers_reg[15][27] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[17][27] /SE"; + 1, DS, "/theRegisters/\registers_reg[17][27] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[13][27] /SE"; + 1, DS, "/theRegisters/\registers_reg[13][27] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[3][27] /SE"; + 1, DS, "/theRegisters/\registers_reg[3][27] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[23][27] /SE"; + 1, DS, "/theRegisters/\registers_reg[23][27] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[26][27] /SE"; + 1, DS, "/theRegisters/\registers_reg[26][27] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[18][27] /SE"; + 1, DS, "/theRegisters/\registers_reg[18][27] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[20][27] /SE"; + 1, DS, "/theRegisters/\registers_reg[20][27] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[24][27] /SE"; + 1, DS, "/theRegisters/\registers_reg[24][27] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[21][27] /SE"; + 1, DS, "/theRegisters/\registers_reg[21][27] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[19][27] /SE"; + 1, DS, "/theRegisters/\registers_reg[19][27] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[12][27] /SE"; + 1, DS, "/theRegisters/\registers_reg[12][27] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[4][27] /SE"; + 1, DS, "/theRegisters/\registers_reg[4][27] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[28][27] /SE"; + 1, DS, "/theRegisters/\registers_reg[28][27] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[5][27] /SE"; + 1, DS, "/theRegisters/\registers_reg[5][27] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[22][27] /SE"; + 1, DS, "/theRegisters/\registers_reg[22][27] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[30][27] /SE"; + 1, DS, "/theRegisters/\registers_reg[30][27] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[1][27] /SE"; + 1, DS, "/theRegisters/\registers_reg[1][27] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[6][27] /SE"; + 1, DS, "/theRegisters/\registers_reg[6][27] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[10][27] /SE"; + 1, DS, "/theRegisters/\registers_reg[10][27] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[16][27] /SE"; + 1, DS, "/theRegisters/\registers_reg[16][27] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[11][27] /SE"; + 1, DS, "/theRegisters/\registers_reg[11][27] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[7][27] /SE"; + 1, DS, "/theRegisters/\registers_reg[7][27] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[9][27] /SE"; + 1, DS, "/theRegisters/\registers_reg[9][27] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[25][27] /SE"; + 1, DS, "/theRegisters/\registers_reg[25][27] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[8][27] /SE"; + 1, DS, "/theRegisters/\registers_reg[8][27] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[2][27] /SE"; + 1, DS, "/theRegisters/\registers_reg[2][27] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[29][27] /SE"; + 1, DS, "/theRegisters/\registers_reg[29][27] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[18][28] /SE"; + 1, DS, "/theRegisters/\registers_reg[18][28] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[19][28] /SE"; + 1, DS, "/theRegisters/\registers_reg[19][28] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[7][28] /SE"; + 1, DS, "/theRegisters/\registers_reg[7][28] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[27][28] /SE"; + 1, DS, "/theRegisters/\registers_reg[27][28] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[31][28] /SE"; + 1, DS, "/theRegisters/\registers_reg[31][28] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[11][28] /SE"; + 1, DS, "/theRegisters/\registers_reg[11][28] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[3][28] /SE"; + 1, DS, "/theRegisters/\registers_reg[3][28] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[16][28] /SE"; + 1, DS, "/theRegisters/\registers_reg[16][28] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[24][28] /SE"; + 1, DS, "/theRegisters/\registers_reg[24][28] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[8][28] /SE"; + 1, DS, "/theRegisters/\registers_reg[8][28] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[30][28] /SE"; + 1, DS, "/theRegisters/\registers_reg[30][28] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[6][28] /SE"; + 1, DS, "/theRegisters/\registers_reg[6][28] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[21][28] /SE"; + 1, DS, "/theRegisters/\registers_reg[21][28] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[10][28] /SE"; + 1, DS, "/theRegisters/\registers_reg[10][28] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[23][28] /SE"; + 1, DS, "/theRegisters/\registers_reg[23][28] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[1][28] /SE"; + 1, DS, "/theRegisters/\registers_reg[1][28] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[20][28] /SE"; + 1, DS, "/theRegisters/\registers_reg[20][28] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[4][28] /SE"; + 1, DS, "/theRegisters/\registers_reg[4][28] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[25][28] /SE"; + 1, DS, "/theRegisters/\registers_reg[25][28] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[13][28] /SE"; + 1, DS, "/theRegisters/\registers_reg[13][28] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[29][28] /SE"; + 1, DS, "/theRegisters/\registers_reg[29][28] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[9][28] /SE"; + 1, DS, "/theRegisters/\registers_reg[9][28] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[2][28] /SE"; + 1, DS, "/theRegisters/\registers_reg[2][28] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[17][28] /SE"; + 1, DS, "/theRegisters/\registers_reg[17][28] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[14][28] /SE"; + 1, DS, "/theRegisters/\registers_reg[14][28] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[28][28] /SE"; + 1, DS, "/theRegisters/\registers_reg[28][28] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[12][28] /SE"; + 1, DS, "/theRegisters/\registers_reg[12][28] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[5][28] /SE"; + 1, DS, "/theRegisters/\registers_reg[5][28] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[22][28] /SE"; + 1, DS, "/theRegisters/\registers_reg[22][28] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[26][28] /SE"; + 1, DS, "/theRegisters/\registers_reg[26][28] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[15][28] /SE"; + 1, DS, "/theRegisters/\registers_reg[15][28] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[2][29] /SE"; + 1, DS, "/theRegisters/\registers_reg[2][29] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[3][29] /SE"; + 1, DS, "/theRegisters/\registers_reg[3][29] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[11][29] /SE"; + 1, DS, "/theRegisters/\registers_reg[11][29] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[27][29] /SE"; + 1, DS, "/theRegisters/\registers_reg[27][29] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[14][29] /SE"; + 1, DS, "/theRegisters/\registers_reg[14][29] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[6][29] /SE"; + 1, DS, "/theRegisters/\registers_reg[6][29] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[1][29] /SE"; + 1, DS, "/theRegisters/\registers_reg[1][29] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[9][29] /SE"; + 1, DS, "/theRegisters/\registers_reg[9][29] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[5][29] /SE"; + 1, DS, "/theRegisters/\registers_reg[5][29] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[22][29] /SE"; + 1, DS, "/theRegisters/\registers_reg[22][29] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[16][29] /SE"; + 1, DS, "/theRegisters/\registers_reg[16][29] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[15][29] /SE"; + 1, DS, "/theRegisters/\registers_reg[15][29] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[12][29] /SE"; + 1, DS, "/theRegisters/\registers_reg[12][29] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[17][29] /SE"; + 1, DS, "/theRegisters/\registers_reg[17][29] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[30][29] /SE"; + 1, DS, "/theRegisters/\registers_reg[30][29] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[18][29] /SE"; + 1, DS, "/theRegisters/\registers_reg[18][29] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[13][29] /SE"; + 1, DS, "/theRegisters/\registers_reg[13][29] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[21][29] /SE"; + 1, DS, "/theRegisters/\registers_reg[21][29] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[25][29] /SE"; + 1, DS, "/theRegisters/\registers_reg[25][29] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[26][29] /SE"; + 1, DS, "/theRegisters/\registers_reg[26][29] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[10][29] /SE"; + 1, DS, "/theRegisters/\registers_reg[10][29] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[29][29] /SE"; + 1, DS, "/theRegisters/\registers_reg[29][29] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[23][29] /SE"; + 1, DS, "/theRegisters/\registers_reg[23][29] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[4][29] /SE"; + 1, DS, "/theRegisters/\registers_reg[4][29] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[19][29] /SE"; + 1, DS, "/theRegisters/\registers_reg[19][29] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[20][29] /SE"; + 1, DS, "/theRegisters/\registers_reg[20][29] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[24][29] /SE"; + 1, DS, "/theRegisters/\registers_reg[24][29] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[7][29] /SE"; + 1, DS, "/theRegisters/\registers_reg[7][29] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[31][29] /SE"; + 1, DS, "/theRegisters/\registers_reg[31][29] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[8][29] /SE"; + 1, DS, "/theRegisters/\registers_reg[8][29] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[28][29] /SE"; + 1, DS, "/theRegisters/\registers_reg[28][29] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[2][30] /SE"; + 1, DS, "/theRegisters/\registers_reg[2][30] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[3][30] /SE"; + 1, DS, "/theRegisters/\registers_reg[3][30] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[14][30] /SE"; + 1, DS, "/theRegisters/\registers_reg[14][30] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[15][30] /SE"; + 1, DS, "/theRegisters/\registers_reg[15][30] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[25][30] /SE"; + 1, DS, "/theRegisters/\registers_reg[25][30] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[13][30] /SE"; + 1, DS, "/theRegisters/\registers_reg[13][30] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[11][30] /SE"; + 1, DS, "/theRegisters/\registers_reg[11][30] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[27][30] /SE"; + 1, DS, "/theRegisters/\registers_reg[27][30] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[12][30] /SE"; + 1, DS, "/theRegisters/\registers_reg[12][30] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[24][30] /SE"; + 1, DS, "/theRegisters/\registers_reg[24][30] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[21][30] /SE"; + 1, DS, "/theRegisters/\registers_reg[21][30] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[22][30] /SE"; + 1, DS, "/theRegisters/\registers_reg[22][30] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[4][30] /SE"; + 1, DS, "/theRegisters/\registers_reg[4][30] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[20][30] /SE"; + 1, DS, "/theRegisters/\registers_reg[20][30] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[30][30] /SE"; + 1, DS, "/theRegisters/\registers_reg[30][30] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[18][30] /SE"; + 1, DS, "/theRegisters/\registers_reg[18][30] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[29][30] /SE"; + 1, DS, "/theRegisters/\registers_reg[29][30] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[9][30] /SE"; + 1, DS, "/theRegisters/\registers_reg[9][30] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[8][30] /SE"; + 1, DS, "/theRegisters/\registers_reg[8][30] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[26][30] /SE"; + 1, DS, "/theRegisters/\registers_reg[26][30] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[10][30] /SE"; + 1, DS, "/theRegisters/\registers_reg[10][30] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[5][30] /SE"; + 1, DS, "/theRegisters/\registers_reg[5][30] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[19][30] /SE"; + 1, DS, "/theRegisters/\registers_reg[19][30] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[7][30] /SE"; + 1, DS, "/theRegisters/\registers_reg[7][30] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[23][30] /SE"; + 1, DS, "/theRegisters/\registers_reg[23][30] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[1][30] /SE"; + 1, DS, "/theRegisters/\registers_reg[1][30] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[6][30] /SE"; + 1, DS, "/theRegisters/\registers_reg[6][30] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[31][30] /SE"; + 1, DS, "/theRegisters/\registers_reg[31][30] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[16][30] /SE"; + 1, DS, "/theRegisters/\registers_reg[16][30] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[17][30] /SE"; + 1, DS, "/theRegisters/\registers_reg[17][30] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[28][30] /SE"; + 1, DS, "/theRegisters/\registers_reg[28][30] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[2][31] /SE"; + 1, DS, "/theRegisters/\registers_reg[2][31] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[3][31] /SE"; + 1, DS, "/theRegisters/\registers_reg[3][31] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[14][31] /SE"; + 1, DS, "/theRegisters/\registers_reg[14][31] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[15][31] /SE"; + 1, DS, "/theRegisters/\registers_reg[15][31] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[25][31] /SE"; + 1, DS, "/theRegisters/\registers_reg[25][31] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[13][31] /SE"; + 1, DS, "/theRegisters/\registers_reg[13][31] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[11][31] /SE"; + 1, DS, "/theRegisters/\registers_reg[11][31] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[27][31] /SE"; + 1, DS, "/theRegisters/\registers_reg[27][31] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[20][31] /SE"; + 1, DS, "/theRegisters/\registers_reg[20][31] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[17][31] /SE"; + 1, DS, "/theRegisters/\registers_reg[17][31] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[21][31] /SE"; + 1, DS, "/theRegisters/\registers_reg[21][31] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[22][31] /SE"; + 1, DS, "/theRegisters/\registers_reg[22][31] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[12][31] /SE"; + 1, DS, "/theRegisters/\registers_reg[12][31] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[24][31] /SE"; + 1, DS, "/theRegisters/\registers_reg[24][31] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[30][31] /SE"; + 1, DS, "/theRegisters/\registers_reg[30][31] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[18][31] /SE"; + 1, DS, "/theRegisters/\registers_reg[18][31] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[29][31] /SE"; + 1, DS, "/theRegisters/\registers_reg[29][31] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[9][31] /SE"; + 1, DS, "/theRegisters/\registers_reg[9][31] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[8][31] /SE"; + 1, DS, "/theRegisters/\registers_reg[8][31] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[26][31] /SE"; + 1, DS, "/theRegisters/\registers_reg[26][31] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[10][31] /SE"; + 1, DS, "/theRegisters/\registers_reg[10][31] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[5][31] /SE"; + 1, DS, "/theRegisters/\registers_reg[5][31] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[19][31] /SE"; + 1, DS, "/theRegisters/\registers_reg[19][31] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[7][31] /SE"; + 1, DS, "/theRegisters/\registers_reg[7][31] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[23][31] /SE"; + 1, DS, "/theRegisters/\registers_reg[23][31] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[1][31] /SE"; + 1, DS, "/theRegisters/\registers_reg[1][31] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[6][31] /SE"; + 1, DS, "/theRegisters/\registers_reg[6][31] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[31][31] /SE"; + 1, DS, "/theRegisters/\registers_reg[31][31] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[16][31] /SE"; + 1, DS, "/theRegisters/\registers_reg[16][31] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[4][31] /SE"; + 1, DS, "/theRegisters/\registers_reg[4][31] /SE"; + 0, DI.SEN, "/theRegisters/\registers_reg[28][31] /SE"; + 1, DS, "/theRegisters/\registers_reg[28][31] /SE"; + 0, DI.SEN, "/\thePC_CurrentPC_reg[0] /SE"; + 1, DS, "/\thePC_CurrentPC_reg[0] /SE"; + 0, DI.SEN, "/\thePC_CurrentPC_reg[1] /SE"; + 1, DS, "/\thePC_CurrentPC_reg[1] /SE"; + 0, DI.SEN, "/\thePC_CurrentPC_reg[31] /SE"; + 1, DS, "/\thePC_CurrentPC_reg[31] /SE"; + 0, DI.SEN, "/\thePC_CurrentPC_reg[2] /SE"; + 1, DS, "/\thePC_CurrentPC_reg[2] /SE"; + 0, DI.SEN, "/\thePC_CurrentPC_reg[3] /SE"; + 1, DS, "/\thePC_CurrentPC_reg[3] /SE"; + 0, DI.SEN, "/\thePC_CurrentPC_reg[4] /SE"; + 1, DS, "/\thePC_CurrentPC_reg[4] /SE"; + 0, DI.SEN, "/\thePC_CurrentPC_reg[5] /SE"; + 1, DS, "/\thePC_CurrentPC_reg[5] /SE"; + 0, DI.SEN, "/\thePC_CurrentPC_reg[6] /SE"; + 1, DS, "/\thePC_CurrentPC_reg[6] /SE"; + 0, DI.SEN, "/\thePC_CurrentPC_reg[7] /SE"; + 1, DS, "/\thePC_CurrentPC_reg[7] /SE"; + 0, DI.SEN, "/\thePC_CurrentPC_reg[8] /SE"; + 1, DS, "/\thePC_CurrentPC_reg[8] /SE"; + 0, DI.SEN, "/\thePC_CurrentPC_reg[9] /SE"; + 1, DS, "/\thePC_CurrentPC_reg[9] /SE"; + 0, DI.SEN, "/\thePC_CurrentPC_reg[10] /SE"; + 1, DS, "/\thePC_CurrentPC_reg[10] /SE"; + 0, DI.SEN, "/\thePC_CurrentPC_reg[11] /SE"; + 1, DS, "/\thePC_CurrentPC_reg[11] /SE"; + 0, DI.SEN, "/\thePC_CurrentPC_reg[12] /SE"; + 1, DS, "/\thePC_CurrentPC_reg[12] /SE"; + 0, DI.SEN, "/\thePC_CurrentPC_reg[13] /SE"; + 1, DS, "/\thePC_CurrentPC_reg[13] /SE"; + 0, DI.SEN, "/\thePC_CurrentPC_reg[14] /SE"; + 1, DS, "/\thePC_CurrentPC_reg[14] /SE"; + 0, DI.SEN, "/\thePC_CurrentPC_reg[15] /SE"; + 1, DS, "/\thePC_CurrentPC_reg[15] /SE"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[16] /SI"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[16] /SI"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[17] /SI"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[17] /SI"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[18] /SI"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[18] /SI"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[19] /SI"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[19] /SI"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[20] /SI"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[20] /SI"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[21] /SI"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[21] /SI"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[22] /SI"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[22] /SI"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[23] /SI"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[23] /SI"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[24] /SI"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[24] /SI"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[25] /SI"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[25] /SI"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[26] /SI"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[26] /SI"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[27] /SI"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[27] /SI"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[28] /SI"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[28] /SI"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[29] /SI"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[29] /SI"; + 0, AU.BB, "/theDecoder/i_18_31/B"; + 1, AU.BB, "/theDecoder/i_18_31/B"; + 0, AU.BB, "/theDecoder/i_18_30/B"; + 1, AU.BB, "/theDecoder/i_18_30/B"; + 0, AU.BB, "/theDecoder/i_18_29/B"; + 1, AU.BB, "/theDecoder/i_18_29/B"; + 0, AU.BB, "/theDecoder/i_18_28/B"; + 1, AU.BB, "/theDecoder/i_18_28/B"; + 0, AU.BB, "/theDecoder/i_18_27/B"; + 1, AU.BB, "/theDecoder/i_18_27/B"; + 0, AU.BB, "/theDecoder/i_18_26/B"; + 1, AU.BB, "/theDecoder/i_18_26/B"; + 0, AU.BB, "/theDecoder/i_18_25/B"; + 1, AU.BB, "/theDecoder/i_18_25/B"; + 0, AU.BB, "/theDecoder/i_18_24/B"; + 1, AU.BB, "/theDecoder/i_18_24/B"; + 0, AU.BB, "/theDecoder/i_18_23/B"; + 1, AU.BB, "/theDecoder/i_18_23/B"; + 0, AU.BB, "/theDecoder/i_18_22/B"; + 1, AU.BB, "/theDecoder/i_18_22/B"; + 0, AU.BB, "/theDecoder/i_18_21/B"; + 1, AU.BB, "/theDecoder/i_18_21/B"; + 0, AU.BB, "/theDecoder/i_18_20/B"; + 1, AU.BB, "/theDecoder/i_18_20/B"; + 0, AU.BB, "/theDecoder/i_18_19/B"; + 1, AU.BB, "/theDecoder/i_18_19/B"; + 0, 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0, EQ, "/theRegisters/i_1_0_1126/A3"; + 1, EQ, "/theRegisters/i_1_0_1136/ZN"; + 0, EQ, "/theRegisters/i_1_0_1136/A2"; + 0, EQ, "/theRegisters/i_1_0_1136/A1"; + 0, EQ, "/theRegisters/i_1_0_1133/ZN"; + 0, EQ, "/theRegisters/i_1_0_1134/ZN"; + 0, EQ, "/theRegisters/i_1_0_1132/ZN"; + 0, EQ, "/theRegisters/i_1_0_1128/ZN"; + 0, EQ, "/theRegisters/i_1_0_1129/ZN"; + 0, EQ, "/theRegisters/i_1_0_1127/ZN"; + 0, EQ, "/theRegisters/i_1_0_1137/ZN"; + 0, EQ, "/theRegisters/i_1_0_1138/ZN"; + 1, EQ, "/theRegisters/i_1_0_1138/A"; + 1, EQ, "/theRegisters/i_1_0_1139/ZN"; + 0, EQ, "/theRegisters/i_1_0_1139/A2"; + 0, EQ, "/theRegisters/i_1_0_1139/A1"; + 0, EQ, "/theRegisters/i_1_0_1139/A3"; + 0, EQ, "/theRegisters/i_1_0_1141/ZN"; + 0, EQ, "/theRegisters/i_1_0_1143/ZN"; + 0, EQ, "/theRegisters/i_1_0_1140/ZN"; + 1, AU.BB, "/theRegisters/i_1_0_1143/ZN"; + 1, EQ, "/theRegisters/i_1_0_1139/A1"; + 1, AU, "/theRegisters/i_1_0_1144/ZN"; + 0, EQ, "/theRegisters/i_1_0_1144/A2"; + 0, EQ, "/theRegisters/i_1_0_1144/A1"; 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0, EQ, "/theRegisters/i_1_0_1158/ZN"; + 0, EQ, "/theRegisters/i_1_0_1160/ZN"; + 0, EQ, "/theRegisters/i_1_0_1163/ZN"; + 0, EQ, "/theRegisters/i_1_0_1159/ZN"; + 1, EQ, "/theRegisters/i_1_0_1147/ZN"; + 0, EQ, "/theRegisters/i_1_0_1147/A2"; + 0, EQ, "/theRegisters/i_1_0_1147/A1"; + 0, EQ, "/theRegisters/i_1_0_1147/A3"; + 0, EQ, "/theRegisters/i_1_0_1149/ZN"; + 0, EQ, "/theRegisters/i_1_0_1150/ZN"; + 0, EQ, "/theRegisters/i_1_0_1148/ZN"; + 1, AU.BB, "/theRegisters/i_1_0_1151/ZN"; + 1, EQ, "/theRegisters/i_1_0_1145/A3"; + 1, AU, "/theRegisters/i_1_0_1164/ZN"; + 0, EQ, "/theRegisters/i_1_0_1164/A1"; + 0, EQ, "/theRegisters/i_1_0_1164/A3"; + 0, EQ, "/theRegisters/i_1_0_1164/A4"; + 0, EQ, "/theRegisters/i_1_0_1164/A2"; + 0, EQ, "/theRegisters/i_1_0_1182/ZN"; + 0, EQ, "/theRegisters/i_1_0_1170/ZN"; + 1, EQ, "/theRegisters/i_1_0_1170/A"; + 0, EQ, "/theRegisters/i_1_0_1165/ZN"; + 1, EQ, "/theRegisters/i_1_0_1165/A"; + 0, EQ, "/theRegisters/i_1_0_1175/ZN"; + 1, EQ, "/theRegisters/i_1_0_1175/A"; + 1, EQ, "/theRegisters/i_1_0_1171/ZN"; + 0, EQ, "/theRegisters/i_1_0_1171/A2"; + 0, EQ, "/theRegisters/i_1_0_1171/A1"; + 0, EQ, "/theRegisters/i_1_0_1171/A3"; + 1, EQ, "/theRegisters/i_1_0_1166/ZN"; + 0, EQ, "/theRegisters/i_1_0_1166/A2"; + 0, EQ, "/theRegisters/i_1_0_1166/A1"; + 0, EQ, "/theRegisters/i_1_0_1166/A3"; + 1, EQ, "/theRegisters/i_1_0_1176/ZN"; + 0, EQ, "/theRegisters/i_1_0_1176/A2"; + 0, EQ, "/theRegisters/i_1_0_1176/A1"; + 0, EQ, "/theRegisters/i_1_0_1173/ZN"; + 0, EQ, "/theRegisters/i_1_0_1174/ZN"; + 0, EQ, "/theRegisters/i_1_0_1172/ZN"; + 0, EQ, "/theRegisters/i_1_0_1168/ZN"; + 0, EQ, "/theRegisters/i_1_0_1169/ZN"; + 0, EQ, "/theRegisters/i_1_0_1167/ZN"; + 0, EQ, "/theRegisters/i_1_0_1177/ZN"; + 0, EQ, "/theRegisters/i_1_0_1178/ZN"; + 1, EQ, "/theRegisters/i_1_0_1178/A"; + 1, EQ, "/theRegisters/i_1_0_1179/ZN"; + 0, EQ, "/theRegisters/i_1_0_1179/A2"; + 0, EQ, "/theRegisters/i_1_0_1179/A1"; + 0, EQ, "/theRegisters/i_1_0_1179/A3"; + 0, EQ, "/theRegisters/i_1_0_1181/ZN"; + 0, EQ, "/theRegisters/i_1_0_1183/ZN"; + 0, EQ, "/theRegisters/i_1_0_1180/ZN"; + 1, AU.BB, "/theRegisters/i_1_0_1183/ZN"; + 1, EQ, "/theRegisters/i_1_0_1179/A1"; + 1, AU, "/theRegisters/i_1_0_1184/ZN"; + 0, EQ, "/theRegisters/i_1_0_1184/A1"; + 0, EQ, "/theRegisters/i_1_0_1184/A3"; + 0, EQ, "/theRegisters/i_1_0_1184/A4"; + 0, EQ, "/theRegisters/i_1_0_1184/A2"; + 0, EQ, "/theRegisters/i_1_0_1202/ZN"; + 0, EQ, "/theRegisters/i_1_0_1190/ZN"; + 1, EQ, "/theRegisters/i_1_0_1190/A"; + 0, EQ, "/theRegisters/i_1_0_1185/ZN"; + 1, EQ, "/theRegisters/i_1_0_1185/A"; + 0, EQ, "/theRegisters/i_1_0_1195/ZN"; + 1, EQ, "/theRegisters/i_1_0_1195/A"; + 1, EQ, "/theRegisters/i_1_0_1191/ZN"; + 0, EQ, "/theRegisters/i_1_0_1191/A2"; + 0, EQ, "/theRegisters/i_1_0_1191/A1"; + 0, EQ, "/theRegisters/i_1_0_1191/A3"; + 1, EQ, "/theRegisters/i_1_0_1186/ZN"; + 0, EQ, "/theRegisters/i_1_0_1186/A2"; + 0, EQ, "/theRegisters/i_1_0_1186/A1"; + 0, EQ, "/theRegisters/i_1_0_1186/A3"; + 1, EQ, "/theRegisters/i_1_0_1196/ZN"; + 0, EQ, "/theRegisters/i_1_0_1196/A2"; + 0, EQ, "/theRegisters/i_1_0_1196/A1"; + 0, EQ, "/theRegisters/i_1_0_1193/ZN"; + 0, EQ, "/theRegisters/i_1_0_1194/ZN"; + 0, EQ, "/theRegisters/i_1_0_1192/ZN"; + 0, EQ, "/theRegisters/i_1_0_1188/ZN"; + 0, EQ, "/theRegisters/i_1_0_1189/ZN"; + 0, EQ, "/theRegisters/i_1_0_1187/ZN"; + 0, EQ, "/theRegisters/i_1_0_1197/ZN"; + 0, EQ, "/theRegisters/i_1_0_1198/ZN"; + 1, EQ, "/theRegisters/i_1_0_1198/A"; + 1, EQ, "/theRegisters/i_1_0_1199/ZN"; + 0, EQ, "/theRegisters/i_1_0_1199/A2"; + 0, EQ, "/theRegisters/i_1_0_1199/A1"; + 0, EQ, "/theRegisters/i_1_0_1199/A3"; + 0, EQ, "/theRegisters/i_1_0_1201/ZN"; + 0, EQ, "/theRegisters/i_1_0_1203/ZN"; + 0, EQ, "/theRegisters/i_1_0_1200/ZN"; + 1, AU.BB, "/theRegisters/i_1_0_1203/ZN"; + 1, EQ, "/theRegisters/i_1_0_1199/A1"; + 1, AU, "/theRegisters/i_1_0_1264/ZN"; + 0, EQ, "/theRegisters/i_1_0_1264/A2"; + 0, EQ, "/theRegisters/i_1_0_1264/A3"; + 0, EQ, "/theRegisters/i_1_0_1264/A1"; + 0, EQ, "/theRegisters/i_1_0_1270/ZN"; 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0, EQ, "/theRegisters/i_1_0_1278/ZN"; + 1, EQ, "/theRegisters/i_1_0_1278/A"; + 1, EQ, "/theRegisters/i_1_0_1279/ZN"; + 0, EQ, "/theRegisters/i_1_0_1279/A2"; + 0, EQ, "/theRegisters/i_1_0_1279/A1"; + 0, EQ, "/theRegisters/i_1_0_1279/A3"; + 0, EQ, "/theRegisters/i_1_0_1281/ZN"; + 0, EQ, "/theRegisters/i_1_0_1283/ZN"; + 0, EQ, "/theRegisters/i_1_0_1280/ZN"; + 1, AU.BB, "/theRegisters/i_1_0_1268/ZN"; + 1, EQ, "/theRegisters/i_1_0_1266/A2"; + 1, AU, "/theRegisters/i_1_0_1284/ZN"; + 0, EQ, "/theRegisters/i_1_0_1284/A1"; + 0, EQ, "/theRegisters/i_1_0_1284/A3"; + 0, EQ, "/theRegisters/i_1_0_1284/A4"; + 0, EQ, "/theRegisters/i_1_0_1284/A2"; + 0, EQ, "/theRegisters/i_1_0_1300/ZN"; + 0, EQ, "/theRegisters/i_1_0_1290/ZN"; + 1, EQ, "/theRegisters/i_1_0_1290/A"; + 0, EQ, "/theRegisters/i_1_0_1285/ZN"; + 1, EQ, "/theRegisters/i_1_0_1285/A"; + 0, EQ, "/theRegisters/i_1_0_1295/ZN"; + 1, EQ, "/theRegisters/i_1_0_1295/A"; + 1, EQ, "/theRegisters/i_1_0_1291/ZN"; + 0, EQ, "/theRegisters/i_1_0_1291/A2"; + 0, EQ, "/theRegisters/i_1_0_1291/A1"; + 0, EQ, "/theRegisters/i_1_0_1291/A3"; + 1, EQ, "/theRegisters/i_1_0_1286/ZN"; + 0, EQ, "/theRegisters/i_1_0_1286/A2"; + 0, EQ, "/theRegisters/i_1_0_1286/A1"; + 0, EQ, "/theRegisters/i_1_0_1286/A3"; + 1, EQ, "/theRegisters/i_1_0_1296/ZN"; + 0, EQ, "/theRegisters/i_1_0_1296/A1"; + 0, EQ, "/theRegisters/i_1_0_1296/A2"; + 0, EQ, "/theRegisters/i_1_0_1296/A4"; + 0, EQ, "/theRegisters/i_1_0_1296/A3"; + 0, EQ, "/theRegisters/i_1_0_1293/ZN"; + 0, EQ, "/theRegisters/i_1_0_1294/ZN"; + 0, EQ, "/theRegisters/i_1_0_1292/ZN"; + 0, EQ, "/theRegisters/i_1_0_1288/ZN"; + 0, EQ, "/theRegisters/i_1_0_1289/ZN"; + 0, EQ, "/theRegisters/i_1_0_1287/ZN"; + 0, EQ, "/theRegisters/i_1_0_1303/ZN"; + 0, EQ, "/theRegisters/i_1_0_1299/ZN"; + 0, EQ, "/theRegisters/i_1_0_1297/ZN"; + 0, EQ, "/theRegisters/i_1_0_1298/ZN"; + 1, EQ, "/theRegisters/i_1_0_1298/A"; + 1, EQ, "/theRegisters/i_1_0_1301/ZN"; + 0, EQ, "/theRegisters/i_1_0_1301/A"; + 0, EQ, "/theRegisters/i_1_0_1302/ZN"; + 1, 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AU.BB, "/theDecoder/i_0_108/A2"; + 0, AU.BB, "/theDecoder/theALU/i_0_718/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_718/A"; + 1, AU.BB, "/theDecoder/theALU/i_0_718/ZN"; + 0, EQ, "/theDecoder/theALU/i_0_718/A"; + 0, AU.BB, "/theDecoder/i_0_323/ZN"; + 1, EQ, "/theDecoder/i_0_323/A1"; + 1, EQ, "/theDecoder/i_0_323/A2"; + 1, AU.BB, "/theDecoder/i_0_323/ZN"; + 0, AU.BB, "/theDecoder/i_0_323/A1"; + 0, AU.BB, "/theDecoder/i_0_323/A2"; + 0, AU.BB, "/theDecoder/i_0_324/ZN"; + 1, AU.BB, "/theDecoder/i_0_324/ZN"; + 1, EQ, "/theDecoder/i_0_324/A1"; + 1, EQ, "/theDecoder/i_0_324/A2"; + 0, AU.BB, "/theDecoder/i_0_324/A1"; + 0, AU.BB, "/theDecoder/i_0_324/A2"; + 0, AU.BB, "/theDecoder/i_0_322/ZN"; + 1, EQ, "/theDecoder/i_0_322/A1"; + 1, EQ, "/theDecoder/i_0_322/A2"; + 1, AU.BB, "/theDecoder/i_0_322/ZN"; + 0, AU.BB, "/theDecoder/i_0_322/A1"; + 0, AU.BB, "/theDecoder/i_0_322/A2"; + 0, AU.BB, "/theDecoder/i_0_171/ZN"; + 1, EQ, "/theDecoder/i_0_171/B"; + 1, EQ, "/theDecoder/i_0_171/A"; + 1, AU.BB, "/theDecoder/i_0_171/ZN"; + 0, AU.BB, "/theDecoder/i_0_171/B"; + 0, AU.BB, "/theDecoder/i_0_171/A"; + 0, AU.BB, "/theDecoder/i_0_219/ZN"; + 1, EQ, "/theDecoder/i_0_219/A2"; + 1, EQ, "/theDecoder/i_0_219/A1"; + 1, EQ, "/theDecoder/i_0_219/A3"; + 1, AU.BB, "/theDecoder/i_0_219/ZN"; + 0, AU.BB, "/theDecoder/i_0_219/A2"; + 0, AU.BB, "/theDecoder/i_0_219/A1"; + 0, RE, "/theDecoder/i_0_219/A3"; + 0, AU.BB, "/theDecoder/i_0_321/ZN"; + 1, EQ, "/theDecoder/i_0_321/A1"; + 1, EQ, "/theDecoder/i_0_321/A2"; + 1, AU.BB, "/theDecoder/i_0_321/ZN"; + 0, AU.BB, "/theDecoder/i_0_321/A1"; + 0, AU.BB, "/theDecoder/i_0_321/A2"; + 0, DI.SCAN, "/theRegisters/\registers_reg[11][0] /SI"; + 1, DI.SCAN, "/theRegisters/\registers_reg[11][0] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[27][0] /SI"; + 1, DI.SCAN, "/theRegisters/\registers_reg[27][0] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[14][0] /SI"; + 1, DI.SCAN, "/theRegisters/\registers_reg[14][0] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[6][0] /SI"; + 1, DI.SCAN, "/theRegisters/\registers_reg[6][0] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[1][0] /SI"; + 1, DI.SCAN, "/theRegisters/\registers_reg[1][0] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[9][0] /SI"; + 1, DI.SCAN, "/theRegisters/\registers_reg[9][0] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[2][0] /SI"; + 1, DI.SCAN, "/theRegisters/\registers_reg[2][0] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[19][0] /SI"; + 1, DI.SCAN, "/theRegisters/\registers_reg[19][0] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[5][0] /SI"; + 1, DI.SCAN, "/theRegisters/\registers_reg[5][0] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[22][0] /SI"; + 1, DI.SCAN, "/theRegisters/\registers_reg[22][0] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[16][0] /SI"; + 1, DI.SCAN, "/theRegisters/\registers_reg[16][0] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[15][0] /SI"; + 1, DI.SCAN, "/theRegisters/\registers_reg[15][0] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[12][0] /SI"; + 1, DI.SCAN, "/theRegisters/\registers_reg[12][0] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[4][0] /SI"; + 1, DI.SCAN, "/theRegisters/\registers_reg[4][0] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[30][0] /SI"; + 1, DI.SCAN, "/theRegisters/\registers_reg[30][0] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[18][0] /SI"; + 1, DI.SCAN, "/theRegisters/\registers_reg[18][0] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[23][0] /SI"; + 1, DI.SCAN, "/theRegisters/\registers_reg[23][0] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[29][0] /SI"; + 1, DI.SCAN, "/theRegisters/\registers_reg[29][0] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[31][0] /SI"; + 1, DI.SCAN, "/theRegisters/\registers_reg[31][0] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[17][0] /SI"; + 1, DI.SCAN, "/theRegisters/\registers_reg[17][0] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[3][0] /SI"; + 1, DI.SCAN, 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/SI"; + 1, DI.SCAN, "/theRegisters/\registers_reg[21][0] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[13][0] /SI"; + 1, DI.SCAN, "/theRegisters/\registers_reg[13][0] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[27][1] /SI"; + 1, DI.SCAN, "/theRegisters/\registers_reg[27][1] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[11][1] /SI"; + 1, DI.SCAN, "/theRegisters/\registers_reg[11][1] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[2][1] /SI"; + 1, DI.SCAN, "/theRegisters/\registers_reg[2][1] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[19][1] /SI"; + 1, DI.SCAN, "/theRegisters/\registers_reg[19][1] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[14][1] /SI"; + 1, DI.SCAN, "/theRegisters/\registers_reg[14][1] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[6][1] /SI"; + 1, DI.SCAN, "/theRegisters/\registers_reg[6][1] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[1][1] /SI"; + 1, DI.SCAN, "/theRegisters/\registers_reg[1][1] /SI"; + 0, DI.SCAN, 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"/theRegisters/\registers_reg[8][31] /SI"; + 1, DI.SCAN, "/theRegisters/\registers_reg[8][31] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[26][31] /SI"; + 1, DI.SCAN, "/theRegisters/\registers_reg[26][31] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[10][31] /SI"; + 1, DI.SCAN, "/theRegisters/\registers_reg[10][31] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[5][31] /SI"; + 1, DI.SCAN, "/theRegisters/\registers_reg[5][31] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[19][31] /SI"; + 1, DI.SCAN, "/theRegisters/\registers_reg[19][31] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[7][31] /SI"; + 1, DI.SCAN, "/theRegisters/\registers_reg[7][31] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[23][31] /SI"; + 1, DI.SCAN, "/theRegisters/\registers_reg[23][31] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[6][31] /SI"; + 1, DI.SCAN, "/theRegisters/\registers_reg[6][31] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[31][31] /SI"; + 1, DI.SCAN, "/theRegisters/\registers_reg[31][31] /SI"; + 0, DI.SCAN, "/theRegisters/\registers_reg[16][31] /SI"; + 1, DI.SCAN, "/theRegisters/\registers_reg[16][31] /SI"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[0] /SI"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[0] /SI"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[1] /SI"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[1] /SI"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[31] /SI"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[31] /SI"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[2] /SI"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[2] /SI"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[3] /SI"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[3] /SI"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[4] /SI"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[4] /SI"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[5] /SI"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[5] /SI"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[6] /SI"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[6] /SI"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[7] /SI"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[7] /SI"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[8] /SI"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[8] /SI"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[9] /SI"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[9] /SI"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[10] /SI"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[10] /SI"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[11] /SI"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[11] /SI"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[12] /SI"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[12] /SI"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[13] /SI"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[13] /SI"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[14] /SI"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[14] /SI"; + 0, DI.SCAN, "/\thePC_CurrentPC_reg[15] /SI"; + 1, DI.SCAN, "/\thePC_CurrentPC_reg[15] /SI"; + 0, AU.BB, "/thePC_i_0_2/B"; + 0, EQ, "/thePC_i_0_1/CO"; + 1, AU.BB, "/thePC_i_0_2/B"; + 1, EQ, "/thePC_i_0_1/CO"; + 0, AU.BB, "/i_0_0_57/A"; + 0, EQ, "/thePC_i_0_1/S"; + 1, AU.BB, "/thePC_i_0_1/S"; + 1, EQ, "/i_0_0_57/A"; + 1, AU, "/theRegisters/i_1_0_0/ZN"; + 0, EQ, "/theRegisters/i_1_0_0/A3"; + 0, EQ, "/theRegisters/i_1_0_0/A1"; + 0, EQ, "/theRegisters/i_1_0_0/A2"; + 0, EQ, "/theRegisters/i_1_0_0/A4"; + 0, EQ, "/theRegisters/i_1_0_17/ZN"; + 0, EQ, "/theRegisters/i_1_0_19/ZN"; + 0, EQ, "/theRegisters/i_1_0_18/ZN"; + 0, EQ, "/theRegisters/i_1_0_1/ZN"; + 1, EQ, "/theRegisters/i_1_0_1/A2"; + 1, EQ, "/theRegisters/i_1_0_1/A1"; + 1, EQ, "/theRegisters/i_1_0_1/A3"; + 1, EQ, "/theRegisters/i_1_0_7/ZN"; + 0, EQ, "/theRegisters/i_1_0_7/A3"; + 0, EQ, "/theRegisters/i_1_0_7/A1"; + 0, EQ, "/theRegisters/i_1_0_7/A2"; + 0, EQ, "/theRegisters/i_1_0_7/A4"; + 1, EQ, "/theRegisters/i_1_0_12/ZN"; + 0, EQ, "/theRegisters/i_1_0_12/A3"; + 0, EQ, "/theRegisters/i_1_0_12/A1"; + 0, EQ, "/theRegisters/i_1_0_12/A2"; + 0, EQ, "/theRegisters/i_1_0_12/A4"; + 1, EQ, "/theRegisters/i_1_0_2/ZN"; + 0, EQ, "/theRegisters/i_1_0_2/A3"; + 0, EQ, "/theRegisters/i_1_0_2/A1"; + 0, EQ, "/theRegisters/i_1_0_2/A2"; + 0, EQ, "/theRegisters/i_1_0_2/A4"; + 0, EQ, "/theRegisters/i_1_0_9/ZN"; + 0, EQ, "/theRegisters/i_1_0_11/ZN"; + 0, EQ, "/theRegisters/i_1_0_10/ZN"; + 0, EQ, "/theRegisters/i_1_0_8/ZN"; + 0, EQ, "/theRegisters/i_1_0_14/ZN"; + 0, EQ, "/theRegisters/i_1_0_16/ZN"; + 0, EQ, "/theRegisters/i_1_0_15/ZN"; + 0, EQ, "/theRegisters/i_1_0_13/ZN"; + 0, EQ, "/theRegisters/i_1_0_4/ZN"; + 0, EQ, "/theRegisters/i_1_0_6/ZN"; + 0, EQ, "/theRegisters/i_1_0_5/ZN"; + 0, EQ, "/theRegisters/i_1_0_3/ZN"; + 1, AU.BB, "/theRegisters/i_1_0_9/ZN"; + 1, EQ, "/theRegisters/i_1_0_7/A3"; + 1, AU, "/theRegisters/i_1_0_20/ZN"; + 0, EQ, "/theRegisters/i_1_0_20/A2"; + 0, EQ, "/theRegisters/i_1_0_20/A3"; + 0, EQ, "/theRegisters/i_1_0_20/A1"; + 0, EQ, "/theRegisters/i_1_0_26/ZN"; + 1, EQ, "/theRegisters/i_1_0_26/A"; + 0, EQ, "/theRegisters/i_1_0_21/ZN"; + 1, EQ, "/theRegisters/i_1_0_21/A"; + 0, EQ, "/theRegisters/i_1_0_31/ZN"; + 1, EQ, "/theRegisters/i_1_0_31/A"; + 1, EQ, "/theRegisters/i_1_0_27/ZN"; + 0, EQ, "/theRegisters/i_1_0_27/A2"; + 0, EQ, "/theRegisters/i_1_0_27/A1"; + 0, EQ, "/theRegisters/i_1_0_27/A3"; + 1, EQ, "/theRegisters/i_1_0_22/ZN"; + 0, EQ, "/theRegisters/i_1_0_22/A2"; + 0, EQ, "/theRegisters/i_1_0_22/A1"; + 0, EQ, "/theRegisters/i_1_0_22/A3"; + 1, EQ, "/theRegisters/i_1_0_32/ZN"; + 0, EQ, "/theRegisters/i_1_0_32/A1"; + 0, EQ, "/theRegisters/i_1_0_32/A3"; + 0, EQ, "/theRegisters/i_1_0_32/A2"; + 0, EQ, "/theRegisters/i_1_0_29/ZN"; + 0, EQ, "/theRegisters/i_1_0_30/ZN"; + 0, EQ, "/theRegisters/i_1_0_28/ZN"; + 0, EQ, "/theRegisters/i_1_0_24/ZN"; + 0, EQ, "/theRegisters/i_1_0_25/ZN"; + 0, EQ, "/theRegisters/i_1_0_23/ZN"; + 0, EQ, "/theRegisters/i_1_0_38/ZN"; + 0, EQ, "/theRegisters/i_1_0_33/ZN"; + 0, EQ, "/theRegisters/i_1_0_34/ZN"; + 1, EQ, "/theRegisters/i_1_0_34/A"; + 1, EQ, "/theRegisters/i_1_0_35/ZN"; + 0, EQ, "/theRegisters/i_1_0_35/A2"; + 0, EQ, "/theRegisters/i_1_0_35/A1"; + 0, EQ, "/theRegisters/i_1_0_35/A3"; + 0, EQ, "/theRegisters/i_1_0_37/ZN"; + 0, EQ, "/theRegisters/i_1_0_39/ZN"; + 0, EQ, "/theRegisters/i_1_0_36/ZN"; + 1, AU.BB, "/theRegisters/i_1_0_28/ZN"; + 1, EQ, "/theRegisters/i_1_0_27/A3"; + 1, AU, "/theRegisters/i_1_0_40/ZN"; + 0, EQ, "/theRegisters/i_1_0_40/A2"; + 0, EQ, "/theRegisters/i_1_0_40/A3"; + 0, EQ, "/theRegisters/i_1_0_40/A1"; + 0, EQ, "/theRegisters/i_1_0_46/ZN"; + 1, EQ, "/theRegisters/i_1_0_46/A"; + 0, EQ, "/theRegisters/i_1_0_41/ZN"; + 1, EQ, "/theRegisters/i_1_0_41/A"; + 0, EQ, "/theRegisters/i_1_0_51/ZN"; + 1, EQ, "/theRegisters/i_1_0_51/A"; + 1, EQ, "/theRegisters/i_1_0_47/ZN"; + 0, EQ, "/theRegisters/i_1_0_47/A2"; + 0, EQ, "/theRegisters/i_1_0_47/A1"; + 0, EQ, "/theRegisters/i_1_0_47/A3"; + 1, EQ, "/theRegisters/i_1_0_42/ZN"; + 0, EQ, "/theRegisters/i_1_0_42/A2"; + 0, EQ, "/theRegisters/i_1_0_42/A1"; + 0, EQ, "/theRegisters/i_1_0_42/A3"; + 1, EQ, "/theRegisters/i_1_0_52/ZN"; + 0, EQ, "/theRegisters/i_1_0_52/A1"; + 0, EQ, "/theRegisters/i_1_0_52/A3"; + 0, EQ, "/theRegisters/i_1_0_52/A2"; + 0, EQ, "/theRegisters/i_1_0_49/ZN"; + 0, EQ, "/theRegisters/i_1_0_50/ZN"; + 0, EQ, "/theRegisters/i_1_0_48/ZN"; + 0, EQ, "/theRegisters/i_1_0_44/ZN"; + 0, EQ, "/theRegisters/i_1_0_45/ZN"; + 0, EQ, "/theRegisters/i_1_0_43/ZN"; + 0, EQ, "/theRegisters/i_1_0_58/ZN"; + 0, EQ, "/theRegisters/i_1_0_53/ZN"; + 0, EQ, "/theRegisters/i_1_0_54/ZN"; + 1, EQ, "/theRegisters/i_1_0_54/A"; + 1, EQ, "/theRegisters/i_1_0_55/ZN"; + 0, EQ, "/theRegisters/i_1_0_55/A2"; + 0, EQ, "/theRegisters/i_1_0_55/A1"; + 0, EQ, "/theRegisters/i_1_0_55/A3"; + 0, EQ, "/theRegisters/i_1_0_57/ZN"; + 0, EQ, "/theRegisters/i_1_0_59/ZN"; + 0, EQ, "/theRegisters/i_1_0_56/ZN"; + 1, AU.BB, "/theRegisters/i_1_0_48/ZN"; + 1, EQ, "/theRegisters/i_1_0_47/A3"; + 1, AU, "/theRegisters/i_1_0_60/ZN"; + 0, EQ, "/theRegisters/i_1_0_60/A2"; + 0, EQ, "/theRegisters/i_1_0_60/A3"; + 0, EQ, "/theRegisters/i_1_0_60/A1"; + 0, EQ, "/theRegisters/i_1_0_66/ZN"; + 1, EQ, "/theRegisters/i_1_0_66/A"; + 0, EQ, "/theRegisters/i_1_0_61/ZN"; + 1, EQ, "/theRegisters/i_1_0_61/A"; + 0, EQ, "/theRegisters/i_1_0_71/ZN"; + 1, EQ, "/theRegisters/i_1_0_71/A"; + 1, EQ, "/theRegisters/i_1_0_67/ZN"; + 0, EQ, "/theRegisters/i_1_0_67/A2"; + 0, EQ, "/theRegisters/i_1_0_67/A1"; + 0, EQ, "/theRegisters/i_1_0_67/A3"; + 1, EQ, "/theRegisters/i_1_0_62/ZN"; + 0, EQ, "/theRegisters/i_1_0_62/A2"; + 0, EQ, "/theRegisters/i_1_0_62/A1"; + 0, EQ, "/theRegisters/i_1_0_62/A3"; + 1, EQ, "/theRegisters/i_1_0_72/ZN"; + 0, EQ, "/theRegisters/i_1_0_72/A1"; + 0, EQ, "/theRegisters/i_1_0_72/A3"; + 0, EQ, "/theRegisters/i_1_0_72/A2"; + 0, EQ, "/theRegisters/i_1_0_69/ZN"; + 0, EQ, "/theRegisters/i_1_0_70/ZN"; + 0, EQ, "/theRegisters/i_1_0_68/ZN"; + 0, EQ, "/theRegisters/i_1_0_64/ZN"; + 0, EQ, "/theRegisters/i_1_0_65/ZN"; + 0, EQ, "/theRegisters/i_1_0_63/ZN"; + 0, EQ, "/theRegisters/i_1_0_78/ZN"; + 0, EQ, "/theRegisters/i_1_0_73/ZN"; + 0, EQ, "/theRegisters/i_1_0_74/ZN"; + 1, EQ, "/theRegisters/i_1_0_74/A"; + 1, EQ, "/theRegisters/i_1_0_75/ZN"; + 0, EQ, "/theRegisters/i_1_0_75/A2"; + 0, EQ, "/theRegisters/i_1_0_75/A1"; + 0, EQ, "/theRegisters/i_1_0_75/A3"; + 0, EQ, "/theRegisters/i_1_0_77/ZN"; + 0, EQ, "/theRegisters/i_1_0_79/ZN"; + 0, EQ, "/theRegisters/i_1_0_76/ZN"; + 1, AU.BB, "/theRegisters/i_1_0_68/ZN"; + 1, EQ, "/theRegisters/i_1_0_67/A3"; + 1, AU, "/theRegisters/i_1_0_80/ZN"; + 0, EQ, "/theRegisters/i_1_0_80/A3"; + 0, EQ, "/theRegisters/i_1_0_80/A1"; + 0, EQ, "/theRegisters/i_1_0_80/A2"; + 0, EQ, "/theRegisters/i_1_0_80/A4"; + 0, EQ, "/theRegisters/i_1_0_97/ZN"; + 0, EQ, "/theRegisters/i_1_0_99/ZN"; + 0, EQ, "/theRegisters/i_1_0_98/ZN"; + 0, EQ, "/theRegisters/i_1_0_81/ZN"; + 1, EQ, "/theRegisters/i_1_0_81/A2"; + 1, EQ, "/theRegisters/i_1_0_81/A1"; + 1, EQ, "/theRegisters/i_1_0_81/A3"; + 1, EQ, "/theRegisters/i_1_0_87/ZN"; + 0, EQ, "/theRegisters/i_1_0_87/A3"; + 0, EQ, "/theRegisters/i_1_0_87/A1"; + 0, EQ, "/theRegisters/i_1_0_87/A2"; + 0, EQ, "/theRegisters/i_1_0_87/A4"; + 1, EQ, "/theRegisters/i_1_0_92/ZN"; + 0, EQ, "/theRegisters/i_1_0_92/A3"; + 0, EQ, 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"/theRegisters/\registers_reg[23][3] /D"; + 1, DS, "/theRegisters/\registers_reg[23][3] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[15][3] /D"; + 1, DS, "/theRegisters/\registers_reg[15][3] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[31][3] /D"; + 1, DS, "/theRegisters/\registers_reg[31][3] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[5][3] /D"; + 1, DS, "/theRegisters/\registers_reg[5][3] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[3][3] /D"; + 1, DS, "/theRegisters/\registers_reg[3][3] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[16][3] /D"; + 1, DS, "/theRegisters/\registers_reg[16][3] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[1][3] /D"; + 1, DS, "/theRegisters/\registers_reg[1][3] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[6][3] /D"; + 1, DS, "/theRegisters/\registers_reg[6][3] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[29][3] /D"; + 1, DS, "/theRegisters/\registers_reg[29][3] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[9][3] /D"; + 1, DS, "/theRegisters/\registers_reg[9][3] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[8][3] /D"; + 1, DS, "/theRegisters/\registers_reg[8][3] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[26][3] /D"; + 1, DS, "/theRegisters/\registers_reg[26][3] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[10][3] /D"; + 1, DS, "/theRegisters/\registers_reg[10][3] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[17][3] /D"; + 1, DS, "/theRegisters/\registers_reg[17][3] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[28][3] /D"; + 1, DS, "/theRegisters/\registers_reg[28][3] /D"; + 1, AU.BB, "/theDecoder/i_0_307/ZN"; + 0, EQ, "/theDecoder/i_0_307/A"; + 0, EQ, "/theDecoder/i_0_308/ZN"; + 0, AU.BB, "/theDecoder/i_0_307/ZN"; + 1, EQ, "/theDecoder/i_0_307/A"; + 1, EQ, "/theDecoder/i_0_308/ZN"; + 0, AU.BB, "/theDecoder/theALU/i_0_141/B1"; + 0, EQ, "/theDecoder/theALU/i_0_141/B2"; + 0, EQ, "/theDecoder/theALU/i_10_46/ZN"; + 1, AU.BB, "/theDecoder/theALU/i_10_46/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_141/B1"; + 0, AU.BB, "/theDecoder/theALU/i_10_46/A"; + 1, AU.BB, "/theDecoder/theALU/i_10_46/A"; + 0, AU.BB, "/theDecoder/theALU/i_10_47/B1"; + 1, AU.BB, "/theDecoder/theALU/i_10_47/B1"; + 1, EQ, "/theDecoder/theALU/i_10_47/B2"; + 0, AU.BB, "/theDecoder/theALU/i_10_47/B2"; + 1, AU.BB, "/theDecoder/i_0_31/ZN"; + 1, EQ, "/theDecoder/i_0_30/A1"; + 0, AU.BB, "/theRegisters/\registers_reg[27][1] /D"; + 1, DS, "/theRegisters/\registers_reg[27][1] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[11][1] /D"; + 1, DS, "/theRegisters/\registers_reg[11][1] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[2][1] /D"; + 1, DS, "/theRegisters/\registers_reg[2][1] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[19][1] /D"; + 1, DS, "/theRegisters/\registers_reg[19][1] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[14][1] /D"; + 1, DS, "/theRegisters/\registers_reg[14][1] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[6][1] /D"; + 1, DS, "/theRegisters/\registers_reg[6][1] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[1][1] /D"; + 1, DS, "/theRegisters/\registers_reg[1][1] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[9][1] /D"; + 1, DS, "/theRegisters/\registers_reg[9][1] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[16][1] /D"; + 1, DS, "/theRegisters/\registers_reg[16][1] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[22][1] /D"; + 1, DS, "/theRegisters/\registers_reg[22][1] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[5][1] /D"; + 1, DS, "/theRegisters/\registers_reg[5][1] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[15][1] /D"; + 1, DS, "/theRegisters/\registers_reg[15][1] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[12][1] /D"; + 1, DS, "/theRegisters/\registers_reg[12][1] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[17][1] /D"; + 1, DS, "/theRegisters/\registers_reg[17][1] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[30][1] /D"; + 1, DS, "/theRegisters/\registers_reg[30][1] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[18][1] /D"; + 1, DS, "/theRegisters/\registers_reg[18][1] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[29][2] /D"; + 1, DS, "/theRegisters/\registers_reg[29][2] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[9][2] /D"; + 1, DS, "/theRegisters/\registers_reg[9][2] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[8][2] /D"; + 1, DS, "/theRegisters/\registers_reg[8][2] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[30][2] /D"; + 1, DS, "/theRegisters/\registers_reg[30][2] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[10][2] /D"; + 1, DS, "/theRegisters/\registers_reg[10][2] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[5][2] /D"; + 1, DS, "/theRegisters/\registers_reg[5][2] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[11][2] /D"; + 1, DS, "/theRegisters/\registers_reg[11][2] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[27][2] /D"; + 1, DS, "/theRegisters/\registers_reg[27][2] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[15][2] /D"; + 1, DS, "/theRegisters/\registers_reg[15][2] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[1][2] /D"; + 1, DS, "/theRegisters/\registers_reg[1][2] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[6][2] /D"; + 1, DS, "/theRegisters/\registers_reg[6][2] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[31][2] /D"; + 1, DS, "/theRegisters/\registers_reg[31][2] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[16][2] /D"; + 1, DS, "/theRegisters/\registers_reg[16][2] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[4][2] /D"; + 1, DS, "/theRegisters/\registers_reg[4][2] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[28][2] /D"; + 1, DS, "/theRegisters/\registers_reg[28][2] /D"; + 1, AU.BB, "/theDecoder/theALU/i_0_103/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_96/A4"; + 0, AU.BB, "/theDecoder/theALU/i_0_112/B1"; + 0, AU.BB, "/theDecoder/i_18_12/CI"; + 0, EQ, "/theDecoder/i_18_11/CO"; + 1, AU, "/theDecoder/i_18_12/CI"; + 1, EQ, "/theDecoder/i_18_11/CO"; + 1, AU.BB, "/theDecoder/i_0_43/A2"; + 0, AU.BB, "/theDecoder/theALU/i_0_32/C1"; + 1, AU.BB, "/theDecoder/theALU/i_0_97/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_96/A2"; + 0, AU.BB, "/theRegisters/i_0_0_4/ZN"; + 0, EQ, "/theRegisters/i_0_0_4/A1"; + 0, EQ, "/theRegisters/i_0_0_4/A2"; + 0, EQ, "/theDecoder/theALU/i_0_84/ZN"; + 0, AU.BB, "/theRegisters/\registers_reg[11][3] /D"; + 1, DS, "/theRegisters/\registers_reg[11][3] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[27][3] /D"; + 1, DS, "/theRegisters/\registers_reg[27][3] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[14][3] /D"; + 1, DS, "/theRegisters/\registers_reg[14][3] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[7][3] /D"; + 1, DS, "/theRegisters/\registers_reg[7][3] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[2][3] /D"; + 1, DS, "/theRegisters/\registers_reg[2][3] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[19][3] /D"; + 1, DS, "/theRegisters/\registers_reg[19][3] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[25][3] /D"; + 1, DS, "/theRegisters/\registers_reg[25][3] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[13][3] /D"; + 1, DS, "/theRegisters/\registers_reg[13][3] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[12][3] /D"; + 1, DS, "/theRegisters/\registers_reg[12][3] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[24][3] /D"; + 1, DS, "/theRegisters/\registers_reg[24][3] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[21][3] /D"; + 1, DS, "/theRegisters/\registers_reg[21][3] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[22][3] /D"; + 1, DS, "/theRegisters/\registers_reg[22][3] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[4][3] /D"; + 1, DS, "/theRegisters/\registers_reg[4][3] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[20][3] /D"; + 1, DS, "/theRegisters/\registers_reg[20][3] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[30][3] /D"; + 1, DS, "/theRegisters/\registers_reg[30][3] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[18][3] /D"; + 1, DS, "/theRegisters/\registers_reg[18][3] /D"; + 0, AU.BB, "/theDecoder/i_0_310/A1"; + 0, EQ, "/theDecoder/i_0_310/A2"; + 0, EQ, "/theDecoder/i_0_7/S"; + 1, AU.BB, "/theDecoder/i_0_7/S"; + 1, EQ, "/theDecoder/i_0_310/A1"; + 1, AU.BB, "/theDecoder/theALU/i_0_141/B2"; + 0, AU.BB, "/theDecoder/theALU/i_10_47/ZN"; + 1, AU.BB, "/theDecoder/theALU/i_10_47/ZN"; + 0, EQ, "/theDecoder/theALU/i_10_47/A"; + 1, AU.BB, "/theDecoder/theALU/i_10_47/A"; + 0, AU.BB, "/theDecoder/i_5_9/S"; + 1, AU.BB, "/theDecoder/i_5_9/S"; + 0, AU.BB, "/i_0_0_59/B"; + 0, EQ, "/theDecoder/i_0_30/ZN"; + 0, AU.BB, "/theRegisters/\registers_reg[2][2] /D"; + 1, DS, "/theRegisters/\registers_reg[2][2] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[23][2] /D"; + 1, DS, "/theRegisters/\registers_reg[23][2] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[3][2] /D"; + 1, DS, "/theRegisters/\registers_reg[3][2] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[19][2] /D"; + 1, DS, "/theRegisters/\registers_reg[19][2] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[14][2] /D"; + 1, DS, "/theRegisters/\registers_reg[14][2] /D"; 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1, DS, "/theRegisters/\registers_reg[26][2] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[18][2] /D"; + 1, DS, "/theRegisters/\registers_reg[18][2] /D"; + 0, AU.BB, "/theRegisters/i_0_0_5/ZN"; + 0, EQ, "/theRegisters/i_0_0_5/A1"; + 0, EQ, "/theRegisters/i_0_0_5/A2"; + 0, EQ, "/theDecoder/theALU/i_0_96/ZN"; + 0, AU.BB, "/thePC_i_0_16/B"; + 0, EQ, "/thePC_i_0_15/CO"; + 1, AU.BB, "/thePC_i_0_16/B"; + 1, EQ, "/thePC_i_0_15/CO"; + 0, AU.BB, "/i_0_0_24/B1"; + 0, EQ, "/i_0_0_24/B2"; + 0, EQ, "/thePC_i_0_15/S"; + 1, AU.BB, "/thePC_i_0_15/S"; + 1, EQ, "/i_0_0_24/B2"; + 1, AU.BB, "/theDecoder/theALU/i_0_31/ZN"; + 0, EQ, "/theDecoder/theALU/i_0_31/A"; + 0, EQ, "/theDecoder/theALU/i_0_32/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_28/B1"; + 1, AU.BB, "/theDecoder/theALU/i_0_32/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_31/A"; + 0, AU.BB, "/theDecoder/i_0_46/B1"; + 0, EQ, "/theDecoder/i_0_46/B2"; + 0, EQ, "/theDecoder/i_17_12/S"; + 1, AU.BB, "/theDecoder/i_17_12/S"; + 1, EQ, "/theDecoder/i_0_46/B2"; + 0, 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/D"; + 0, AU.BB, "/theRegisters/\registers_reg[22][13] /D"; + 1, DS, "/theRegisters/\registers_reg[22][13] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[12][13] /D"; + 1, DS, "/theRegisters/\registers_reg[12][13] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[24][13] /D"; + 1, DS, "/theRegisters/\registers_reg[24][13] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[30][13] /D"; + 1, DS, "/theRegisters/\registers_reg[30][13] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[18][13] /D"; + 1, DS, "/theRegisters/\registers_reg[18][13] /D"; + 0, AU.BB, "/theDecoder/theALU/i_0_438/C1"; + 0, EQ, "/theDecoder/theALU/i_0_438/C2"; + 0, EQ, "/theDecoder/theALU/i_10_117/ZN"; + 1, AU.BB, "/theDecoder/theALU/i_10_117/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_438/C1"; + 0, AU.BB, "/theDecoder/theALU/i_10_117/A"; + 1, AU.BB, "/theDecoder/theALU/i_10_117/A"; + 0, AU.BB, "/theDecoder/theALU/i_10_118/B1"; + 1, AU.BB, "/theDecoder/theALU/i_10_118/B1"; + 1, EQ, "/theDecoder/theALU/i_10_118/B2"; + 0, AU.BB, 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/D"; + 0, AU.BB, "/theRegisters/\registers_reg[7][14] /D"; + 1, DS, "/theRegisters/\registers_reg[7][14] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[6][14] /D"; + 1, DS, "/theRegisters/\registers_reg[6][14] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[25][14] /D"; + 1, DS, "/theRegisters/\registers_reg[25][14] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[13][14] /D"; + 1, DS, "/theRegisters/\registers_reg[13][14] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[22][14] /D"; + 1, DS, "/theRegisters/\registers_reg[22][14] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[19][14] /D"; + 1, DS, "/theRegisters/\registers_reg[19][14] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[12][14] /D"; + 1, DS, "/theRegisters/\registers_reg[12][14] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[24][14] /D"; + 1, DS, "/theRegisters/\registers_reg[24][14] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[2][14] /D"; + 1, DS, "/theRegisters/\registers_reg[2][14] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[1][14] /D"; + 1, DS, "/theRegisters/\registers_reg[1][14] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[4][14] /D"; + 1, DS, "/theRegisters/\registers_reg[4][14] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[20][14] /D"; + 1, DS, "/theRegisters/\registers_reg[20][14] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[30][14] /D"; + 1, DS, "/theRegisters/\registers_reg[30][14] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[26][14] /D"; + 1, DS, "/theRegisters/\registers_reg[26][14] /D"; + 1, AU.BB, "/theDecoder/theALU/i_0_438/C2"; + 0, AU.BB, "/theDecoder/theALU/i_10_118/ZN"; + 1, AU.BB, "/theDecoder/theALU/i_10_118/ZN"; + 0, EQ, "/theDecoder/theALU/i_10_118/A"; + 1, AU.BB, "/theDecoder/theALU/i_10_118/A"; + 1, AU.BB, "/theDecoder/i_0_64/ZN"; + 1, EQ, "/theDecoder/i_0_63/A1"; + 0, AU.BB, "/theDecoder/i_18_23/CI"; + 0, EQ, "/theDecoder/i_18_22/CO"; + 1, AU.BB, "/theDecoder/i_18_23/CI"; + 1, EQ, "/theDecoder/i_18_22/CO"; + 1, AU.BB, "/theDecoder/i_0_76/A2"; + 1, DS, "/i_0_0_42/B1"; + 1, DS, "/i_0_0_44/B1"; + 1, DS, "/i_0_0_46/B1"; + 1, DS, "/i_0_0_48/B1"; + 1, DS, "/i_0_0_50/B1"; + 1, AU.BB, "/theDecoder/theALU/i_0_301/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_299/A1"; + 0, AU.BB, "/theRegisters/i_0_0_15/ZN"; + 0, EQ, "/theRegisters/i_0_0_15/A1"; + 0, EQ, "/theRegisters/i_0_0_15/A2"; + 0, EQ, "/theDecoder/theALU/i_0_282/ZN"; + 0, AU.BB, "/theDecoder/theALU/i_0_461/B1"; + 0, EQ, "/theDecoder/theALU/i_0_461/B2"; + 0, EQ, "/theDecoder/theALU/i_10_120/ZN"; + 1, AU.BB, "/theDecoder/theALU/i_10_120/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_461/B1"; + 0, AU.BB, "/theDecoder/theALU/i_10_120/A"; + 1, AU.BB, "/theDecoder/theALU/i_10_120/A"; + 0, AU.BB, "/theDecoder/theALU/i_10_120/B"; + 1, AU.BB, "/theDecoder/theALU/i_10_120/B"; + 0, AU.BB, "/theDecoder/theALU/i_10_122/A1"; + 1, AU.BB, "/theDecoder/theALU/i_10_122/A1"; + 1, EQ, "/theDecoder/theALU/i_10_122/A2"; + 0, AU.BB, "/theDecoder/theALU/i_10_122/A2"; + 0, AU.BB, "/theDecoder/i_0_67/C1"; + 0, EQ, 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"/theDecoder/theALU/i_0_297/ZN"; + 0, AU.BB, "/theRegisters/\registers_reg[31][15] /D"; + 1, DS, "/theRegisters/\registers_reg[31][15] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[27][15] /D"; + 1, DS, "/theRegisters/\registers_reg[27][15] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[3][15] /D"; + 1, DS, "/theRegisters/\registers_reg[3][15] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[23][15] /D"; + 1, DS, "/theRegisters/\registers_reg[23][15] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[29][15] /D"; + 1, DS, "/theRegisters/\registers_reg[29][15] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[9][15] /D"; + 1, DS, "/theRegisters/\registers_reg[9][15] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[14][15] /D"; + 1, DS, "/theRegisters/\registers_reg[14][15] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[7][15] /D"; + 1, DS, "/theRegisters/\registers_reg[7][15] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[25][15] /D"; + 1, DS, "/theRegisters/\registers_reg[25][15] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[19][15] /D"; + 1, DS, "/theRegisters/\registers_reg[19][15] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[16][15] /D"; + 1, DS, "/theRegisters/\registers_reg[16][15] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[6][15] /D"; + 1, DS, "/theRegisters/\registers_reg[6][15] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[5][15] /D"; + 1, DS, "/theRegisters/\registers_reg[5][15] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[4][15] /D"; + 1, DS, "/theRegisters/\registers_reg[4][15] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[26][15] /D"; + 1, DS, "/theRegisters/\registers_reg[26][15] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[18][15] /D"; + 1, DS, "/theRegisters/\registers_reg[18][15] /D"; + 1, AU.BB, "/theDecoder/theALU/i_0_479/A2"; + 0, AU.BB, "/theDecoder/theALU/i_10_129/ZN"; + 1, AU.BB, "/theDecoder/theALU/i_10_129/ZN"; + 0, EQ, "/theDecoder/theALU/i_10_129/A"; + 1, AU.BB, "/theDecoder/theALU/i_10_129/A"; + 0, AU.BB, "/theDecoder/i_0_70/C1"; + 0, EQ, "/theDecoder/i_0_70/C2"; + 0, EQ, "/theDecoder/i_5_21/S"; + 1, AU.BB, "/theDecoder/i_5_21/S"; + 1, EQ, "/theDecoder/i_0_70/C1"; + 0, AU.BB, "/i_0_0_26/A2"; + 0, EQ, "/i_0_0_26/A1"; + 0, EQ, "/theDecoder/i_0_66/ZN"; + 0, AU.BB, "/theDecoder/i_0_82/B2"; + 0, EQ, "/theDecoder/i_0_82/B1"; + 0, EQ, "/theDecoder/i_17_24/S"; + 1, AU.BB, "/theDecoder/i_17_24/S"; + 1, EQ, "/theDecoder/i_0_82/B2"; + 0, AU.BB, "/theDecoder/theALU/i_0_341/B1"; + 0, EQ, "/theDecoder/theALU/i_0_341/B2"; + 0, EQ, "/theDecoder/theALU/i_9_18/S"; + 1, AU.BB, "/theDecoder/theALU/i_9_18/S"; + 1, EQ, "/theDecoder/theALU/i_0_341/B1"; + 1, AU.BB, "/theDecoder/theALU/i_0_319/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_314/A"; + 1, DS, "/theRegisters/i_0_0_16/ZN"; + 1, AU.BB, "/theRegisters/i_0_0_16/A1"; + 0, AU.BB, "/theDecoder/theALU/i_0_498/A1"; + 0, EQ, "/theDecoder/theALU/i_0_498/A2"; + 0, EQ, "/theDecoder/theALU/i_10_133/ZN"; + 1, AU.BB, "/theDecoder/theALU/i_10_133/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_498/A1"; + 0, AU.BB, "/theDecoder/theALU/i_10_133/A"; + 1, AU.BB, "/theDecoder/theALU/i_10_133/A"; + 0, AU.BB, "/theDecoder/theALU/i_10_133/B"; + 1, AU.BB, "/theDecoder/theALU/i_10_133/B"; + 0, AU.BB, "/theDecoder/theALU/i_10_134/B1"; + 1, AU.BB, "/theDecoder/theALU/i_10_134/B1"; + 1, EQ, "/theDecoder/theALU/i_10_134/B2"; + 0, AU.BB, "/theDecoder/theALU/i_10_134/B2"; + 0, AU.BB, "/theDecoder/i_5_22/CI"; + 0, EQ, "/theDecoder/i_5_21/CO"; + 1, AU.BB, "/theDecoder/i_5_22/CI"; + 1, EQ, "/theDecoder/i_5_21/CO"; + 1, AU.BB, "/theDecoder/i_0_70/C2"; + 1, AU, "/i_0_0_26/A2"; + 0, AU.BB, "/theDecoder/i_0_82/A1"; + 0, EQ, "/theDecoder/i_0_82/A2"; + 0, EQ, "/theDecoder/i_18_24/S"; + 1, AU.BB, "/theDecoder/i_18_24/S"; + 1, EQ, "/theDecoder/i_0_82/A1"; + 0, AU.BB, "/theDecoder/i_17_25/CI"; + 0, EQ, "/theDecoder/i_17_24/CO"; + 1, AU.BB, "/theDecoder/i_17_25/CI"; + 1, EQ, "/theDecoder/i_17_24/CO"; + 1, AU.BB, "/theDecoder/i_0_82/B1"; + 0, AU.BB, "/theDecoder/theALU/i_9_19/CI"; + 0, EQ, "/theDecoder/theALU/i_9_18/CO"; + 1, AU.BB, "/theDecoder/theALU/i_9_19/CI"; + 1, EQ, "/theDecoder/theALU/i_9_18/CO"; + 1, AU.BB, "/theDecoder/theALU/i_0_341/B2"; + 0, AU.BB, "/theRegisters/i_0_0_17/ZN"; + 0, EQ, "/theRegisters/i_0_0_17/A1"; + 0, EQ, "/theRegisters/i_0_0_17/A2"; + 0, EQ, "/theDecoder/theALU/i_0_314/ZN"; + 0, AU.BB, "/theRegisters/\registers_reg[28][16] /D"; + 1, DS, "/theRegisters/\registers_reg[28][16] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[5][16] /D"; + 1, DS, "/theRegisters/\registers_reg[5][16] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[1][16] /D"; + 1, DS, "/theRegisters/\registers_reg[1][16] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[22][16] /D"; + 1, DS, "/theRegisters/\registers_reg[22][16] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[18][16] /D"; + 1, DS, "/theRegisters/\registers_reg[18][16] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[6][16] /D"; + 1, DS, "/theRegisters/\registers_reg[6][16] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[31][16] /D"; + 1, DS, "/theRegisters/\registers_reg[31][16] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[16][16] /D"; + 1, DS, "/theRegisters/\registers_reg[16][16] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[10][16] /D"; + 1, DS, "/theRegisters/\registers_reg[10][16] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[7][16] /D"; + 1, DS, "/theRegisters/\registers_reg[7][16] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[9][16] /D"; + 1, DS, "/theRegisters/\registers_reg[9][16] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[25][16] /D"; + 1, DS, "/theRegisters/\registers_reg[25][16] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[11][16] /D"; + 1, DS, "/theRegisters/\registers_reg[11][16] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[2][16] /D"; + 1, DS, "/theRegisters/\registers_reg[2][16] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[29][16] /D"; + 1, DS, "/theRegisters/\registers_reg[29][16] /D"; + 1, AU.BB, "/theDecoder/theALU/i_0_498/A2"; + 0, AU.BB, "/theDecoder/theALU/i_10_134/ZN"; + 1, AU.BB, "/theDecoder/theALU/i_10_134/ZN"; + 0, EQ, "/theDecoder/theALU/i_10_134/A"; + 1, AU.BB, "/theDecoder/theALU/i_10_134/A"; + 1, AU.BB, "/theDecoder/i_0_70/ZN"; + 1, EQ, "/theDecoder/i_0_69/A1"; + 1, DS, "/i_0_0_25/ZN"; + 0, EQ, "/i_0_0_25/A"; + 0, EQ, "/i_0_0_26/ZN"; + 1, EQ, "/\thePC_CurrentPC_reg[18] /D"; + 0, AU.BB, "/\thePC_CurrentPC_reg[18] /D"; + 0, EQ, "/i_0_0_25/ZN"; + 1, EQ, "/i_0_0_25/A"; + 1, EQ, "/i_0_0_26/ZN"; + 0, AU.BB, "/theDecoder/i_18_25/CI"; + 0, EQ, "/theDecoder/i_18_24/CO"; + 1, AU.BB, "/theDecoder/i_18_25/CI"; + 1, EQ, "/theDecoder/i_18_24/CO"; + 1, AU.BB, "/theDecoder/i_0_82/A2"; + 1, AU.BB, "/theDecoder/theALU/i_0_341/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_339/A2"; + 1, DS, "/theRegisters/i_0_0_17/ZN"; + 1, AU.BB, "/theRegisters/i_0_0_17/A1"; + 0, AU.BB, "/theRegisters/\registers_reg[3][16] /D"; + 1, DS, "/theRegisters/\registers_reg[3][16] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[27][16] /D"; + 1, DS, "/theRegisters/\registers_reg[27][16] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[14][16] /D"; + 1, DS, "/theRegisters/\registers_reg[14][16] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[15][16] /D"; + 1, DS, "/theRegisters/\registers_reg[15][16] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[17][16] /D"; + 1, DS, "/theRegisters/\registers_reg[17][16] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[13][16] /D"; + 1, DS, "/theRegisters/\registers_reg[13][16] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[23][16] /D"; + 1, DS, "/theRegisters/\registers_reg[23][16] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[8][16] /D"; + 1, DS, "/theRegisters/\registers_reg[8][16] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[30][16] /D"; + 1, DS, "/theRegisters/\registers_reg[30][16] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[26][16] /D"; + 1, DS, "/theRegisters/\registers_reg[26][16] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[20][16] /D"; + 1, DS, "/theRegisters/\registers_reg[20][16] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[24][16] /D"; + 1, DS, "/theRegisters/\registers_reg[24][16] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[21][16] /D"; + 1, DS, "/theRegisters/\registers_reg[21][16] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[19][16] /D"; + 1, DS, "/theRegisters/\registers_reg[19][16] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[12][16] /D"; + 1, DS, "/theRegisters/\registers_reg[12][16] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[4][16] /D"; + 1, DS, "/theRegisters/\registers_reg[4][16] /D"; + 0, AU.BB, "/theDecoder/theALU/i_0_517/B1"; + 0, EQ, "/theDecoder/theALU/i_0_517/B2"; + 0, EQ, "/theDecoder/theALU/i_10_136/ZN"; + 1, AU.BB, "/theDecoder/theALU/i_10_136/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_517/B1"; + 0, AU.BB, "/theDecoder/theALU/i_10_136/A"; + 1, AU.BB, "/theDecoder/theALU/i_10_136/A"; + 0, AU.BB, "/theDecoder/theALU/i_10_136/B"; + 1, AU.BB, "/theDecoder/theALU/i_10_136/B"; + 0, AU.BB, "/theDecoder/theALU/i_10_138/A1"; + 0, EQ, "/theDecoder/theALU/i_10_138/A2"; + 1, AU.BB, "/theDecoder/theALU/i_10_138/A1"; + 1, AU.BB, "/theDecoder/theALU/i_10_138/A2"; + 0, AU.BB, "/theDecoder/i_0_73/C1"; + 0, EQ, "/theDecoder/i_0_73/C2"; + 0, EQ, "/theDecoder/i_5_22/S"; + 1, AU.BB, "/theDecoder/i_5_22/S"; + 1, EQ, "/theDecoder/i_0_73/C1"; + 0, AU.BB, "/i_0_0_28/A2"; + 0, EQ, "/i_0_0_28/A1"; + 0, EQ, "/theDecoder/i_0_69/ZN"; + 0, AU.BB, "/theDecoder/i_0_85/B2"; + 0, EQ, "/theDecoder/i_0_85/B1"; + 0, EQ, "/theDecoder/i_17_25/S"; + 1, AU.BB, "/theDecoder/i_17_25/S"; + 1, EQ, "/theDecoder/i_0_85/B2"; + 1, AU.BB, "/theDecoder/theALU/i_0_363/ZN"; + 0, EQ, "/theDecoder/theALU/i_0_363/A1"; + 0, EQ, "/theDecoder/theALU/i_0_363/A2"; + 0, EQ, "/theDecoder/theALU/i_9_19/S"; + 1, EQ, "/theDecoder/theALU/i_0_360/A1"; + 1, AU.BB, "/theDecoder/theALU/i_9_19/S"; + 1, EQ, "/theDecoder/theALU/i_0_363/A1"; + 0, AU.BB, "/theDecoder/theALU/i_0_339/ZN"; + 0, EQ, "/theDecoder/theALU/i_0_335/A"; + 0, AU.BB, "/theRegisters/\registers_reg[28][17] /D"; + 1, DS, "/theRegisters/\registers_reg[28][17] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[1][17] /D"; + 1, DS, "/theRegisters/\registers_reg[1][17] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[13][17] /D"; + 1, DS, "/theRegisters/\registers_reg[13][17] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[26][17] /D"; + 1, DS, "/theRegisters/\registers_reg[26][17] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[22][17] /D"; + 1, DS, "/theRegisters/\registers_reg[22][17] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[24][17] /D"; + 1, DS, "/theRegisters/\registers_reg[24][17] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[10][17] /D"; + 1, DS, "/theRegisters/\registers_reg[10][17] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[11][17] /D"; + 1, DS, "/theRegisters/\registers_reg[11][17] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[15][17] /D"; + 1, DS, "/theRegisters/\registers_reg[15][17] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[12][17] /D"; + 1, DS, "/theRegisters/\registers_reg[12][17] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[20][17] /D"; + 1, DS, "/theRegisters/\registers_reg[20][17] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[31][17] /D"; + 1, DS, "/theRegisters/\registers_reg[31][17] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[2][17] /D"; + 1, DS, "/theRegisters/\registers_reg[2][17] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[21][17] /D"; + 1, DS, "/theRegisters/\registers_reg[21][17] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[17][17] /D"; + 1, DS, "/theRegisters/\registers_reg[17][17] /D"; + 1, AU.BB, "/theDecoder/theALU/i_0_517/B2"; + 0, AU.BB, "/theDecoder/theALU/i_10_138/ZN"; + 1, AU.BB, "/theDecoder/theALU/i_10_138/ZN"; + 0, AU.BB, "/theDecoder/i_5_23/CI"; + 0, EQ, "/theDecoder/i_5_22/CO"; + 1, AU.BB, "/theDecoder/i_5_23/CI"; + 1, EQ, "/theDecoder/i_5_22/CO"; + 1, AU.BB, "/theDecoder/i_0_73/C2"; + 1, AU, "/i_0_0_28/A2"; + 0, AU.BB, "/theDecoder/i_0_85/A1"; + 0, EQ, "/theDecoder/i_0_85/A2"; + 0, EQ, "/theDecoder/i_18_25/S"; + 1, AU.BB, "/theDecoder/i_18_25/S"; + 1, EQ, "/theDecoder/i_0_85/A1"; + 0, AU.BB, "/theDecoder/i_17_26/CI"; + 0, EQ, "/theDecoder/i_17_25/CO"; + 1, AU.BB, "/theDecoder/i_17_26/CI"; + 1, EQ, "/theDecoder/i_17_25/CO"; + 1, AU.BB, "/theDecoder/i_0_85/B1"; + 0, AU.BB, "/theDecoder/theALU/i_9_20/CI"; + 0, EQ, "/theDecoder/theALU/i_9_19/CO"; + 1, AU.BB, "/theDecoder/theALU/i_9_20/CI"; + 1, EQ, "/theDecoder/theALU/i_9_19/CO"; + 1, AU.BB, "/theDecoder/theALU/i_0_363/A2"; + 1, AU.BB, "/theDecoder/theALU/i_0_335/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_334/A"; + 0, AU.BB, "/theRegisters/\registers_reg[3][17] /D"; + 1, DS, "/theRegisters/\registers_reg[3][17] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[27][17] /D"; + 1, DS, "/theRegisters/\registers_reg[27][17] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[23][17] /D"; + 1, DS, "/theRegisters/\registers_reg[23][17] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[8][17] /D"; + 1, DS, "/theRegisters/\registers_reg[8][17] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[29][17] /D"; + 1, DS, "/theRegisters/\registers_reg[29][17] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[9][17] /D"; + 1, DS, "/theRegisters/\registers_reg[9][17] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[14][17] /D"; + 1, DS, "/theRegisters/\registers_reg[14][17] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[7][17] /D"; + 1, DS, "/theRegisters/\registers_reg[7][17] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[16][17] /D"; + 1, DS, "/theRegisters/\registers_reg[16][17] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[19][17] /D"; + 1, DS, "/theRegisters/\registers_reg[19][17] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[25][17] /D"; + 1, DS, "/theRegisters/\registers_reg[25][17] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[6][17] /D"; + 1, DS, "/theRegisters/\registers_reg[6][17] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[5][17] /D"; + 1, DS, "/theRegisters/\registers_reg[5][17] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[4][17] /D"; + 1, DS, "/theRegisters/\registers_reg[4][17] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[30][17] /D"; + 1, DS, "/theRegisters/\registers_reg[30][17] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[18][17] /D"; + 1, DS, "/theRegisters/\registers_reg[18][17] /D"; + 1, AU.BB, "/theDecoder/theALU/i_0_544/ZN"; + 0, EQ, "/theDecoder/theALU/i_0_544/A1"; + 0, EQ, "/theDecoder/theALU/i_0_544/A2"; + 0, EQ, "/theDecoder/theALU/i_10_140/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_541/B"; + 1, AU.BB, "/theDecoder/theALU/i_10_140/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_544/A1"; + 0, AU.BB, "/theDecoder/theALU/i_10_140/A"; + 1, AU.BB, "/theDecoder/theALU/i_10_140/A"; + 0, AU.BB, "/theDecoder/theALU/i_10_140/B"; + 1, AU.BB, "/theDecoder/theALU/i_10_140/B"; + 0, AU.BB, "/theDecoder/theALU/i_10_142/A1"; + 1, AU.BB, "/theDecoder/theALU/i_10_142/A1"; + 1, EQ, "/theDecoder/theALU/i_10_142/A2"; + 0, AU.BB, "/theDecoder/theALU/i_10_142/A2"; + 1, AU.BB, "/theDecoder/i_0_73/ZN"; + 1, EQ, "/theDecoder/i_0_72/A1"; + 1, DS, "/i_0_0_27/ZN"; + 0, EQ, "/i_0_0_27/A"; + 0, EQ, "/i_0_0_28/ZN"; + 1, EQ, "/\thePC_CurrentPC_reg[19] /D"; + 0, AU.BB, "/\thePC_CurrentPC_reg[19] /D"; + 0, EQ, "/i_0_0_27/ZN"; + 1, EQ, "/i_0_0_27/A"; + 1, EQ, "/i_0_0_28/ZN"; + 0, AU.BB, "/theDecoder/i_18_26/CI"; + 0, EQ, "/theDecoder/i_18_25/CO"; + 1, AU.BB, "/theDecoder/i_18_26/CI"; + 1, EQ, "/theDecoder/i_18_25/CO"; + 1, AU.BB, "/theDecoder/i_0_85/A2"; + 0, AU.BB, "/theDecoder/theALU/i_0_360/ZN"; + 0, EQ, "/theDecoder/theALU/i_0_358/A"; + 0, AU.BB, "/theRegisters/i_0_0_18/ZN"; + 0, EQ, "/theRegisters/i_0_0_18/A1"; + 0, EQ, "/theRegisters/i_0_0_18/A2"; + 0, EQ, "/theDecoder/theALU/i_0_334/ZN"; + 1, AU.BB, "/theDecoder/theALU/i_0_544/A2"; + 0, AU.BB, "/theDecoder/theALU/i_10_142/ZN"; + 1, AU.BB, "/theDecoder/theALU/i_10_142/ZN"; + 0, AU.BB, "/theDecoder/i_0_76/C1"; + 0, EQ, "/theDecoder/i_0_76/C2"; + 0, EQ, "/theDecoder/i_5_23/S"; + 1, AU.BB, "/theDecoder/i_5_23/S"; + 1, EQ, "/theDecoder/i_0_76/C1"; + 0, AU.BB, "/i_0_0_30/A2"; + 0, EQ, "/i_0_0_30/A1"; + 0, EQ, "/theDecoder/i_0_72/ZN"; + 0, AU.BB, "/theDecoder/i_0_88/B2"; + 0, EQ, "/theDecoder/i_0_88/B1"; + 0, EQ, "/theDecoder/i_17_26/S"; + 1, AU.BB, "/theDecoder/i_17_26/S"; + 1, EQ, "/theDecoder/i_0_88/B2"; + 0, AU.BB, "/theDecoder/theALU/i_0_386/B1"; + 0, EQ, "/theDecoder/theALU/i_0_386/B2"; + 0, EQ, "/theDecoder/theALU/i_9_20/S"; + 1, AU.BB, "/theDecoder/theALU/i_9_20/S"; + 1, EQ, "/theDecoder/theALU/i_0_386/B1"; + 1, AU.BB, "/theDecoder/theALU/i_0_358/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_356/B"; + 1, DS, "/theRegisters/i_0_0_18/ZN"; + 1, AU.BB, "/theRegisters/i_0_0_18/A1"; + 1, AU.BB, "/theDecoder/theALU/i_0_558/ZN"; + 0, EQ, "/theDecoder/theALU/i_0_558/A1"; + 0, EQ, "/theDecoder/theALU/i_0_558/A2"; + 0, EQ, "/theDecoder/theALU/i_10_144/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_552/A2"; + 1, AU.BB, "/theDecoder/theALU/i_10_144/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_558/A1"; + 0, AU.BB, "/theDecoder/theALU/i_10_144/A"; + 1, AU.BB, "/theDecoder/theALU/i_10_144/A"; + 0, AU.BB, "/theDecoder/theALU/i_10_144/B"; + 1, AU.BB, "/theDecoder/theALU/i_10_144/B"; + 0, AU.BB, "/theDecoder/theALU/i_10_146/A1"; + 0, EQ, "/theDecoder/theALU/i_10_146/A2"; + 1, AU.BB, "/theDecoder/theALU/i_10_146/A1"; + 1, AU.BB, "/theDecoder/theALU/i_10_146/A2"; + 0, AU.BB, "/theDecoder/i_5_24/CI"; + 0, EQ, "/theDecoder/i_5_23/CO"; + 1, AU.BB, "/theDecoder/i_5_24/CI"; + 1, EQ, "/theDecoder/i_5_23/CO"; + 1, AU.BB, "/theDecoder/i_0_76/C2"; + 1, AU, "/i_0_0_30/A2"; + 0, AU.BB, "/theDecoder/i_0_88/A1"; + 0, EQ, "/theDecoder/i_0_88/A2"; + 0, EQ, "/theDecoder/i_18_26/S"; + 1, AU.BB, "/theDecoder/i_18_26/S"; + 1, EQ, "/theDecoder/i_0_88/A1"; + 0, AU.BB, "/theDecoder/i_17_27/CI"; + 0, EQ, "/theDecoder/i_17_26/CO"; + 1, AU.BB, "/theDecoder/i_17_27/CI"; + 1, EQ, "/theDecoder/i_17_26/CO"; + 1, AU.BB, "/theDecoder/i_0_88/B1"; + 0, AU.BB, "/theDecoder/theALU/i_9_21/CI"; + 0, EQ, "/theDecoder/theALU/i_9_20/CO"; + 1, AU.BB, "/theDecoder/theALU/i_9_21/CI"; + 1, EQ, "/theDecoder/theALU/i_9_20/CO"; + 1, AU.BB, "/theDecoder/theALU/i_0_386/B2"; + 0, AU.BB, "/theRegisters/i_0_0_19/ZN"; + 0, EQ, "/theRegisters/i_0_0_19/A1"; + 0, EQ, "/theRegisters/i_0_0_19/A2"; + 0, EQ, "/theDecoder/theALU/i_0_356/ZN"; + 0, AU.BB, "/theRegisters/\registers_reg[2][18] /D"; + 1, DS, "/theRegisters/\registers_reg[2][18] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[29][18] /D"; + 1, DS, "/theRegisters/\registers_reg[29][18] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[1][18] /D"; + 1, DS, "/theRegisters/\registers_reg[1][18] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[26][18] /D"; + 1, DS, "/theRegisters/\registers_reg[26][18] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[22][18] /D"; + 1, DS, "/theRegisters/\registers_reg[22][18] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[6][18] /D"; + 1, DS, "/theRegisters/\registers_reg[6][18] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[31][18] /D"; + 1, DS, "/theRegisters/\registers_reg[31][18] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[25][18] /D"; + 1, DS, "/theRegisters/\registers_reg[25][18] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[27][18] /D"; + 1, DS, "/theRegisters/\registers_reg[27][18] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[7][18] /D"; + 1, DS, "/theRegisters/\registers_reg[7][18] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[9][18] /D"; + 1, DS, "/theRegisters/\registers_reg[9][18] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[16][18] /D"; + 1, DS, "/theRegisters/\registers_reg[16][18] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[11][18] /D"; + 1, DS, "/theRegisters/\registers_reg[11][18] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[28][18] /D"; + 1, DS, "/theRegisters/\registers_reg[28][18] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[24][18] /D"; + 1, DS, "/theRegisters/\registers_reg[24][18] /D"; + 1, AU.BB, "/theDecoder/theALU/i_0_558/A2"; + 0, AU.BB, "/theDecoder/theALU/i_10_146/ZN"; + 1, AU.BB, "/theDecoder/theALU/i_10_146/ZN"; + 1, AU.BB, "/theDecoder/i_0_76/ZN"; + 1, EQ, "/theDecoder/i_0_75/A1"; + 1, DS, "/i_0_0_29/ZN"; + 0, EQ, "/i_0_0_29/A"; + 0, EQ, "/i_0_0_30/ZN"; + 1, EQ, "/\thePC_CurrentPC_reg[20] /D"; + 0, AU.BB, "/\thePC_CurrentPC_reg[20] /D"; + 0, EQ, "/i_0_0_29/ZN"; + 1, EQ, "/i_0_0_29/A"; + 1, EQ, "/i_0_0_30/ZN"; + 0, AU.BB, "/theDecoder/i_18_27/CI"; + 0, EQ, "/theDecoder/i_18_26/CO"; + 1, AU.BB, "/theDecoder/i_18_27/CI"; + 1, EQ, "/theDecoder/i_18_26/CO"; + 1, AU.BB, "/theDecoder/i_0_88/A2"; + 1, AU.BB, "/theDecoder/theALU/i_0_386/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_384/A3"; + 1, DS, "/theRegisters/i_0_0_19/ZN"; + 1, AU.BB, "/theRegisters/i_0_0_19/A1"; + 0, AU.BB, "/theRegisters/\registers_reg[3][18] /D"; + 1, DS, "/theRegisters/\registers_reg[3][18] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[10][18] /D"; + 1, DS, "/theRegisters/\registers_reg[10][18] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[14][18] /D"; + 1, DS, "/theRegisters/\registers_reg[14][18] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[15][18] /D"; + 1, DS, "/theRegisters/\registers_reg[15][18] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[17][18] /D"; + 1, DS, "/theRegisters/\registers_reg[17][18] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[13][18] /D"; + 1, DS, "/theRegisters/\registers_reg[13][18] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[23][18] /D"; + 1, DS, "/theRegisters/\registers_reg[23][18] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[8][18] /D"; + 1, DS, "/theRegisters/\registers_reg[8][18] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[20][18] /D"; + 1, DS, "/theRegisters/\registers_reg[20][18] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[5][18] /D"; + 1, DS, "/theRegisters/\registers_reg[5][18] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[21][18] /D"; + 1, DS, "/theRegisters/\registers_reg[21][18] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[19][18] /D"; + 1, DS, "/theRegisters/\registers_reg[19][18] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[12][18] /D"; + 1, DS, "/theRegisters/\registers_reg[12][18] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[4][18] /D"; + 1, DS, "/theRegisters/\registers_reg[4][18] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[30][18] /D"; + 1, DS, "/theRegisters/\registers_reg[30][18] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[18][18] /D"; + 1, DS, "/theRegisters/\registers_reg[18][18] /D"; + 0, AU.BB, "/theDecoder/theALU/i_0_580/A1"; + 0, EQ, "/theDecoder/theALU/i_0_580/A2"; + 0, EQ, "/theDecoder/theALU/i_10_151/ZN"; + 1, AU.BB, "/theDecoder/theALU/i_10_151/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_580/A1"; + 0, AU.BB, "/theDecoder/theALU/i_10_151/A"; + 1, AU.BB, "/theDecoder/theALU/i_10_151/A"; + 0, AU.BB, "/theDecoder/theALU/i_10_153/B1"; + 0, EQ, "/theDecoder/theALU/i_10_153/B2"; + 1, AU.BB, "/theDecoder/theALU/i_10_153/B1"; + 1, AU.BB, "/theDecoder/theALU/i_10_153/B2"; + 0, AU.BB, "/theDecoder/i_0_79/C1"; + 0, EQ, "/theDecoder/i_0_79/C2"; + 0, EQ, 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"/theRegisters/\registers_reg[26][19] /D"; + 1, DS, "/theRegisters/\registers_reg[26][19] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[22][19] /D"; + 1, DS, "/theRegisters/\registers_reg[22][19] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[24][19] /D"; + 1, DS, "/theRegisters/\registers_reg[24][19] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[27][19] /D"; + 1, DS, "/theRegisters/\registers_reg[27][19] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[11][19] /D"; + 1, DS, "/theRegisters/\registers_reg[11][19] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[15][19] /D"; + 1, DS, "/theRegisters/\registers_reg[15][19] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[12][19] /D"; + 1, DS, "/theRegisters/\registers_reg[12][19] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[20][19] /D"; + 1, DS, "/theRegisters/\registers_reg[20][19] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[31][19] /D"; + 1, DS, "/theRegisters/\registers_reg[31][19] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[2][19] /D"; + 1, DS, "/theRegisters/\registers_reg[2][19] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[21][19] /D"; + 1, DS, "/theRegisters/\registers_reg[21][19] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[17][19] /D"; + 1, DS, "/theRegisters/\registers_reg[17][19] /D"; + 1, AU.BB, "/theDecoder/theALU/i_0_580/A2"; + 1, AU.BB, "/theDecoder/theALU/i_10_153/ZN"; + 1, EQ, "/theDecoder/theALU/i_10_155/A"; + 0, AU.BB, "/theDecoder/i_5_25/CI"; + 0, EQ, "/theDecoder/i_5_24/CO"; + 1, AU.BB, "/theDecoder/i_5_25/CI"; + 1, EQ, "/theDecoder/i_5_24/CO"; + 1, AU.BB, "/theDecoder/i_0_79/C2"; + 1, AU, "/i_0_0_32/A2"; + 0, AU.BB, "/theDecoder/i_0_91/A1"; + 0, EQ, "/theDecoder/i_0_91/A2"; + 0, EQ, "/theDecoder/i_18_27/S"; + 1, AU.BB, "/theDecoder/i_18_27/S"; + 1, EQ, "/theDecoder/i_0_91/A1"; + 0, AU.BB, "/theDecoder/i_17_28/CI"; + 0, EQ, "/theDecoder/i_17_27/CO"; + 1, AU.BB, "/theDecoder/i_17_28/CI"; + 1, EQ, "/theDecoder/i_17_27/CO"; + 1, AU.BB, "/theDecoder/i_0_91/B1"; + 0, AU.BB, "/theDecoder/theALU/i_9_22/CI"; + 0, EQ, "/theDecoder/theALU/i_9_21/CO"; + 1, AU.BB, "/theDecoder/theALU/i_9_22/CI"; + 1, EQ, "/theDecoder/theALU/i_9_21/CO"; + 1, AU.BB, "/theDecoder/theALU/i_0_398/B2"; + 0, AU.BB, "/theRegisters/i_0_0_20/ZN"; + 0, EQ, "/theRegisters/i_0_0_20/A1"; + 0, EQ, "/theRegisters/i_0_0_20/A2"; + 0, EQ, "/theDecoder/theALU/i_0_377/ZN"; + 0, AU.BB, "/theRegisters/\registers_reg[3][19] /D"; + 1, DS, "/theRegisters/\registers_reg[3][19] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[10][19] /D"; + 1, DS, "/theRegisters/\registers_reg[10][19] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[14][19] /D"; + 1, DS, "/theRegisters/\registers_reg[14][19] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[7][19] /D"; + 1, DS, "/theRegisters/\registers_reg[7][19] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[23][19] /D"; + 1, DS, "/theRegisters/\registers_reg[23][19] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[8][19] /D"; + 1, DS, "/theRegisters/\registers_reg[8][19] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[29][19] /D"; + 1, DS, "/theRegisters/\registers_reg[29][19] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[9][19] /D"; + 1, DS, "/theRegisters/\registers_reg[9][19] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[16][19] /D"; + 1, DS, "/theRegisters/\registers_reg[16][19] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[19][19] /D"; + 1, DS, "/theRegisters/\registers_reg[19][19] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[25][19] /D"; + 1, DS, "/theRegisters/\registers_reg[25][19] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[6][19] /D"; + 1, DS, "/theRegisters/\registers_reg[6][19] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[5][19] /D"; + 1, DS, "/theRegisters/\registers_reg[5][19] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[4][19] /D"; + 1, DS, "/theRegisters/\registers_reg[4][19] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[30][19] /D"; + 1, DS, "/theRegisters/\registers_reg[30][19] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[18][19] /D"; + 1, DS, "/theRegisters/\registers_reg[18][19] /D"; + 0, AU.BB, "/theDecoder/theALU/i_0_587/C1"; + 0, EQ, "/theDecoder/theALU/i_0_587/C2"; + 0, EQ, "/theDecoder/theALU/i_10_155/ZN"; + 1, AU.BB, "/theDecoder/theALU/i_10_155/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_587/C1"; + 1, AU.BB, "/theDecoder/i_0_79/ZN"; + 1, EQ, "/theDecoder/i_0_78/A1"; + 1, DS, "/i_0_0_31/ZN"; + 0, EQ, "/i_0_0_31/A"; + 0, EQ, "/i_0_0_32/ZN"; + 1, EQ, "/\thePC_CurrentPC_reg[21] /D"; + 0, AU.BB, "/\thePC_CurrentPC_reg[21] /D"; + 0, EQ, "/i_0_0_31/ZN"; + 1, EQ, "/i_0_0_31/A"; + 1, EQ, "/i_0_0_32/ZN"; + 0, AU.BB, "/theDecoder/i_18_28/CI"; + 0, EQ, "/theDecoder/i_18_27/CO"; + 1, AU.BB, "/theDecoder/i_18_28/CI"; + 1, EQ, "/theDecoder/i_18_27/CO"; + 1, AU.BB, "/theDecoder/i_0_91/A2"; + 0, AU.BB, "/theDecoder/theALU/i_0_397/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_397/A"; + 1, EQ, "/theDecoder/theALU/i_0_398/ZN"; + 0, EQ, "/theDecoder/theALU/i_0_396/A"; + 1, DS, "/theRegisters/i_0_0_20/ZN"; + 1, AU.BB, "/theRegisters/i_0_0_20/A1"; + 1, AU.BB, "/theDecoder/theALU/i_0_587/C2"; + 0, AU.BB, "/theDecoder/i_0_82/C1"; + 0, EQ, "/theDecoder/i_0_82/C2"; + 0, EQ, "/theDecoder/i_5_25/S"; + 1, AU.BB, "/theDecoder/i_5_25/S"; + 1, EQ, "/theDecoder/i_0_82/C1"; + 0, AU.BB, "/i_0_0_34/A2"; + 0, EQ, "/i_0_0_34/A1"; + 0, EQ, "/theDecoder/i_0_78/ZN"; + 0, AU.BB, "/theDecoder/i_0_94/B2"; + 0, EQ, "/theDecoder/i_0_94/B1"; + 0, EQ, "/theDecoder/i_17_28/S"; + 1, AU.BB, "/theDecoder/i_17_28/S"; + 1, EQ, "/theDecoder/i_0_94/B2"; + 0, AU.BB, "/theDecoder/theALU/i_0_419/B1"; + 0, EQ, "/theDecoder/theALU/i_0_419/B2"; + 0, EQ, "/theDecoder/theALU/i_9_22/S"; + 1, AU.BB, "/theDecoder/theALU/i_9_22/S"; + 1, EQ, "/theDecoder/theALU/i_0_419/B1"; + 0, AU.BB, "/theRegisters/\registers_reg[28][20] /D"; + 1, DS, "/theRegisters/\registers_reg[28][20] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[1][20] /D"; + 1, DS, "/theRegisters/\registers_reg[1][20] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[22][20] /D"; + 1, DS, "/theRegisters/\registers_reg[22][20] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[30][20] /D"; + 1, DS, "/theRegisters/\registers_reg[30][20] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[13][20] /D"; + 1, DS, "/theRegisters/\registers_reg[13][20] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[5][20] /D"; + 1, DS, "/theRegisters/\registers_reg[5][20] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[11][20] /D"; + 1, DS, "/theRegisters/\registers_reg[11][20] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[8][20] /D"; + 1, DS, "/theRegisters/\registers_reg[8][20] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[15][20] /D"; + 1, DS, "/theRegisters/\registers_reg[15][20] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[12][20] /D"; + 1, DS, "/theRegisters/\registers_reg[12][20] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[20][20] /D"; + 1, DS, "/theRegisters/\registers_reg[20][20] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[2][20] /D"; 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"/theDecoder/theALU/i_9_22/CO"; + 1, AU.BB, "/theDecoder/theALU/i_9_23/CI"; + 1, EQ, "/theDecoder/theALU/i_9_22/CO"; + 1, AU.BB, "/theDecoder/theALU/i_0_419/B2"; + 1, AU.BB, "/theDecoder/theALU/i_0_396/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_393/A1"; + 0, AU.BB, "/theRegisters/\registers_reg[31][20] /D"; + 1, DS, "/theRegisters/\registers_reg[31][20] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[27][20] /D"; + 1, DS, "/theRegisters/\registers_reg[27][20] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[3][20] /D"; + 1, DS, "/theRegisters/\registers_reg[3][20] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[23][20] /D"; + 1, DS, "/theRegisters/\registers_reg[23][20] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[29][20] /D"; + 1, DS, "/theRegisters/\registers_reg[29][20] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[9][20] /D"; + 1, DS, "/theRegisters/\registers_reg[9][20] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[14][20] /D"; + 1, DS, "/theRegisters/\registers_reg[14][20] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[7][20] /D"; + 1, DS, "/theRegisters/\registers_reg[7][20] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[16][20] /D"; + 1, DS, "/theRegisters/\registers_reg[16][20] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[19][20] /D"; + 1, DS, "/theRegisters/\registers_reg[19][20] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[25][20] /D"; + 1, DS, "/theRegisters/\registers_reg[25][20] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[6][20] /D"; + 1, DS, "/theRegisters/\registers_reg[6][20] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[4][20] /D"; + 1, DS, "/theRegisters/\registers_reg[4][20] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[24][20] /D"; + 1, DS, "/theRegisters/\registers_reg[24][20] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[26][20] /D"; + 1, DS, "/theRegisters/\registers_reg[26][20] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[18][20] /D"; + 1, DS, "/theRegisters/\registers_reg[18][20] /D"; + 1, AU.BB, "/theDecoder/i_0_82/ZN"; + 1, EQ, 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+ 0, AU.BB, "/theRegisters/\registers_reg[6][21] /D"; + 1, DS, "/theRegisters/\registers_reg[6][21] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[21][21] /D"; + 1, DS, "/theRegisters/\registers_reg[21][21] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[17][21] /D"; + 1, DS, "/theRegisters/\registers_reg[17][21] /D"; + 1, AU.BB, "/theDecoder/i_0_85/ZN"; + 1, EQ, "/theDecoder/i_0_84/A1"; + 1, DS, "/i_0_0_35/ZN"; + 0, EQ, "/i_0_0_35/A"; + 0, EQ, "/i_0_0_36/ZN"; + 1, EQ, "/\thePC_CurrentPC_reg[23] /D"; + 0, AU.BB, "/\thePC_CurrentPC_reg[23] /D"; + 0, EQ, "/i_0_0_35/ZN"; + 1, EQ, "/i_0_0_35/A"; + 1, EQ, "/i_0_0_36/ZN"; + 0, AU.BB, "/theDecoder/i_18_30/CI"; + 0, EQ, "/theDecoder/i_18_29/CO"; + 1, AU.BB, "/theDecoder/i_18_30/CI"; + 1, EQ, "/theDecoder/i_18_29/CO"; + 1, AU.BB, "/theDecoder/i_0_97/A2"; + 1, AU.BB, "/theDecoder/theALU/i_0_438/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_437/A"; + 0, AU.BB, "/theRegisters/i_0_0_22/ZN"; + 0, EQ, "/theRegisters/i_0_0_22/A1"; + 0, EQ, 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"/theRegisters/\registers_reg[25][21] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[19][21] /D"; + 1, DS, "/theRegisters/\registers_reg[19][21] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[16][21] /D"; + 1, DS, "/theRegisters/\registers_reg[16][21] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[15][21] /D"; + 1, DS, "/theRegisters/\registers_reg[15][21] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[4][21] /D"; + 1, DS, "/theRegisters/\registers_reg[4][21] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[24][21] /D"; + 1, DS, "/theRegisters/\registers_reg[24][21] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[26][21] /D"; + 1, DS, "/theRegisters/\registers_reg[26][21] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[18][21] /D"; + 1, DS, "/theRegisters/\registers_reg[18][21] /D"; + 0, AU.BB, "/theDecoder/i_0_88/C1"; + 0, EQ, "/theDecoder/i_0_88/C2"; + 0, EQ, "/theDecoder/i_5_27/S"; + 1, AU.BB, "/theDecoder/i_5_27/S"; + 1, EQ, "/theDecoder/i_0_88/C1"; + 0, AU.BB, "/i_0_0_38/A2"; + 0, EQ, "/i_0_0_38/A1"; + 0, EQ, "/theDecoder/i_0_84/ZN"; + 0, AU.BB, "/theDecoder/i_0_100/B2"; + 0, EQ, "/theDecoder/i_0_100/B1"; + 0, EQ, "/theDecoder/i_17_30/S"; + 1, AU.BB, "/theDecoder/i_17_30/S"; + 1, EQ, "/theDecoder/i_0_100/B2"; + 0, AU.BB, "/theDecoder/theALU/i_0_461/C1"; + 0, EQ, "/theDecoder/theALU/i_0_461/C2"; + 0, EQ, "/theDecoder/theALU/i_9_24/S"; + 1, AU.BB, "/theDecoder/theALU/i_9_24/S"; + 1, EQ, "/theDecoder/theALU/i_0_461/C1"; + 0, AU.BB, "/theDecoder/theALU/i_0_437/ZN"; + 0, EQ, "/theDecoder/theALU/i_0_436/B"; + 1, DS, "/theRegisters/i_0_0_22/ZN"; + 1, AU.BB, "/theRegisters/i_0_0_22/A1"; + 0, AU.BB, "/theDecoder/i_5_28/CI"; + 0, EQ, "/theDecoder/i_5_27/CO"; + 1, AU.BB, "/theDecoder/i_5_28/CI"; + 1, EQ, "/theDecoder/i_5_27/CO"; + 1, AU.BB, "/theDecoder/i_0_88/C2"; + 1, AU, "/i_0_0_38/A2"; + 0, AU.BB, "/theDecoder/i_0_100/A1"; + 0, EQ, "/theDecoder/i_0_100/A2"; + 0, EQ, "/theDecoder/i_18_30/S"; + 1, AU.BB, "/theDecoder/i_18_30/S"; + 1, EQ, "/theDecoder/i_0_100/A1"; + 0, AU.BB, "/theDecoder/i_17_31/CI"; + 0, EQ, "/theDecoder/i_17_30/CO"; + 1, AU.BB, "/theDecoder/i_17_31/CI"; + 1, EQ, "/theDecoder/i_17_30/CO"; + 1, AU.BB, "/theDecoder/i_0_100/B1"; + 0, AU.BB, "/theDecoder/theALU/i_9_25/CI"; + 0, EQ, "/theDecoder/theALU/i_9_24/CO"; + 1, AU.BB, "/theDecoder/theALU/i_9_25/CI"; + 1, EQ, "/theDecoder/theALU/i_9_24/CO"; + 1, AU.BB, "/theDecoder/theALU/i_0_461/C2"; + 1, AU.BB, "/theDecoder/theALU/i_0_436/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_435/A"; + 0, AU.BB, "/theRegisters/\registers_reg[28][22] /D"; + 1, DS, "/theRegisters/\registers_reg[28][22] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[1][22] /D"; + 1, DS, "/theRegisters/\registers_reg[1][22] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[13][22] /D"; + 1, DS, "/theRegisters/\registers_reg[13][22] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[26][22] /D"; + 1, DS, "/theRegisters/\registers_reg[26][22] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[22][22] /D"; + 1, DS, "/theRegisters/\registers_reg[22][22] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[2][22] /D"; + 1, DS, "/theRegisters/\registers_reg[2][22] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[31][22] /D"; + 1, DS, "/theRegisters/\registers_reg[31][22] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[5][22] /D"; + 1, DS, "/theRegisters/\registers_reg[5][22] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[10][22] /D"; + 1, DS, "/theRegisters/\registers_reg[10][22] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[12][22] /D"; + 1, DS, "/theRegisters/\registers_reg[12][22] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[20][22] /D"; + 1, DS, "/theRegisters/\registers_reg[20][22] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[11][22] /D"; + 1, DS, "/theRegisters/\registers_reg[11][22] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[6][22] /D"; + 1, DS, "/theRegisters/\registers_reg[6][22] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[21][22] /D"; + 1, DS, "/theRegisters/\registers_reg[21][22] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[17][22] /D"; + 1, DS, "/theRegisters/\registers_reg[17][22] /D"; + 1, AU.BB, "/theDecoder/i_0_88/ZN"; + 1, EQ, "/theDecoder/i_0_87/A1"; + 1, DS, "/i_0_0_37/ZN"; + 0, EQ, "/i_0_0_37/A"; + 0, EQ, "/i_0_0_38/ZN"; + 1, EQ, "/\thePC_CurrentPC_reg[24] /D"; + 0, AU.BB, "/\thePC_CurrentPC_reg[24] /D"; + 0, EQ, "/i_0_0_37/ZN"; + 1, EQ, "/i_0_0_37/A"; + 1, EQ, "/i_0_0_38/ZN"; + 0, AU.BB, "/theDecoder/i_18_31/CI"; + 0, EQ, "/theDecoder/i_18_30/CO"; + 1, AU.BB, "/theDecoder/i_18_31/CI"; + 1, EQ, "/theDecoder/i_18_30/CO"; + 1, AU.BB, "/theDecoder/i_0_100/A2"; + 0, AU.BB, "/theDecoder/theALU/i_0_460/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_460/A"; + 1, EQ, "/theDecoder/theALU/i_0_461/ZN"; + 0, EQ, "/theDecoder/theALU/i_0_453/A"; + 0, AU.BB, "/theRegisters/i_0_0_23/ZN"; + 0, EQ, "/theRegisters/i_0_0_23/A1"; + 0, EQ, "/theRegisters/i_0_0_23/A2"; + 0, EQ, "/theDecoder/theALU/i_0_435/ZN"; + 0, AU.BB, "/theRegisters/\registers_reg[3][22] /D"; + 1, DS, "/theRegisters/\registers_reg[3][22] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[27][22] /D"; + 1, DS, "/theRegisters/\registers_reg[27][22] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[23][22] /D"; + 1, DS, "/theRegisters/\registers_reg[23][22] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[8][22] /D"; + 1, DS, "/theRegisters/\registers_reg[8][22] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[29][22] /D"; + 1, DS, "/theRegisters/\registers_reg[29][22] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[9][22] /D"; + 1, DS, "/theRegisters/\registers_reg[9][22] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[14][22] /D"; + 1, DS, "/theRegisters/\registers_reg[14][22] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[7][22] /D"; + 1, DS, "/theRegisters/\registers_reg[7][22] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[25][22] /D"; + 1, DS, "/theRegisters/\registers_reg[25][22] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[19][22] /D"; + 1, DS, "/theRegisters/\registers_reg[19][22] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[16][22] /D"; + 1, DS, "/theRegisters/\registers_reg[16][22] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[15][22] /D"; + 1, DS, "/theRegisters/\registers_reg[15][22] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[4][22] /D"; + 1, DS, "/theRegisters/\registers_reg[4][22] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[24][22] /D"; + 1, DS, "/theRegisters/\registers_reg[24][22] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[30][22] /D"; + 1, DS, "/theRegisters/\registers_reg[30][22] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[18][22] /D"; + 1, DS, "/theRegisters/\registers_reg[18][22] /D"; + 0, AU.BB, "/theDecoder/i_0_91/C1"; + 0, EQ, "/theDecoder/i_0_91/C2"; + 0, EQ, "/theDecoder/i_5_28/S"; + 1, AU.BB, "/theDecoder/i_5_28/S"; + 1, EQ, "/theDecoder/i_0_91/C1"; + 0, AU.BB, "/i_0_0_40/A2"; + 0, EQ, "/i_0_0_40/A1"; + 0, EQ, "/theDecoder/i_0_87/ZN"; + 0, AU.BB, "/theDecoder/i_0_103/B2"; + 0, EQ, "/theDecoder/i_0_103/B1"; + 0, EQ, "/theDecoder/i_17_31/S"; + 1, AU.BB, "/theDecoder/i_17_31/S"; + 1, EQ, "/theDecoder/i_0_103/B2"; + 0, AU.BB, "/theDecoder/theALU/i_0_479/B1"; + 0, EQ, "/theDecoder/theALU/i_0_479/B2"; + 0, EQ, "/theDecoder/theALU/i_9_25/S"; + 1, AU.BB, "/theDecoder/theALU/i_9_25/S"; + 1, EQ, "/theDecoder/theALU/i_0_479/B1"; + 1, DS, "/theRegisters/i_0_0_23/ZN"; + 1, AU.BB, "/theRegisters/i_0_0_23/A1"; + 0, AU.BB, "/theDecoder/i_5_29/CI"; + 0, EQ, "/theDecoder/i_5_28/CO"; + 1, AU.BB, "/theDecoder/i_5_29/CI"; + 1, EQ, "/theDecoder/i_5_28/CO"; + 1, AU.BB, "/theDecoder/i_0_91/C2"; + 1, AU, "/i_0_0_40/A2"; + 0, AU.BB, "/theDecoder/i_0_103/A1"; + 0, EQ, "/theDecoder/i_0_103/A2"; + 0, EQ, "/theDecoder/i_18_31/S"; + 1, AU.BB, "/theDecoder/i_18_31/S"; + 1, EQ, "/theDecoder/i_0_103/A1"; + 0, AU.BB, "/theDecoder/i_17_31/CO"; + 0, EQ, "/theDecoder/i_17_33/B"; + 1, AU.BB, "/theDecoder/i_17_31/CO"; + 1, EQ, "/theDecoder/i_17_33/B"; + 1, AU.BB, "/theDecoder/i_0_103/B1"; + 0, AU.BB, "/theDecoder/theALU/i_9_26/CI"; + 0, EQ, "/theDecoder/theALU/i_9_25/CO"; + 1, AU.BB, "/theDecoder/theALU/i_9_26/CI"; + 1, EQ, "/theDecoder/theALU/i_9_25/CO"; + 1, AU.BB, "/theDecoder/theALU/i_0_479/B2"; + 1, AU.BB, "/theDecoder/theALU/i_0_453/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_452/A2"; + 0, AU.BB, "/theRegisters/\registers_reg[8][23] /D"; + 1, DS, "/theRegisters/\registers_reg[8][23] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[31][23] /D"; + 1, DS, "/theRegisters/\registers_reg[31][23] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[30][23] /D"; + 1, DS, "/theRegisters/\registers_reg[30][23] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[3][23] /D"; + 1, DS, "/theRegisters/\registers_reg[3][23] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[29][23] /D"; + 1, DS, "/theRegisters/\registers_reg[29][23] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[23][23] /D"; + 1, DS, "/theRegisters/\registers_reg[23][23] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[26][23] /D"; + 1, DS, "/theRegisters/\registers_reg[26][23] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[19][23] /D"; + 1, DS, "/theRegisters/\registers_reg[19][23] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[20][23] /D"; + 1, DS, "/theRegisters/\registers_reg[20][23] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[21][23] /D"; + 1, DS, "/theRegisters/\registers_reg[21][23] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[1][23] /D"; + 1, DS, "/theRegisters/\registers_reg[1][23] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[22][23] /D"; + 1, DS, "/theRegisters/\registers_reg[22][23] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[18][23] /D"; + 1, DS, "/theRegisters/\registers_reg[18][23] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[28][23] /D"; + 1, DS, "/theRegisters/\registers_reg[28][23] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[9][23] /D"; + 1, DS, "/theRegisters/\registers_reg[9][23] /D"; + 1, AU.BB, "/theDecoder/i_0_91/ZN"; + 1, EQ, "/theDecoder/i_0_90/A1"; + 1, DS, "/i_0_0_39/ZN"; + 0, EQ, "/i_0_0_39/A"; + 0, EQ, "/i_0_0_40/ZN"; + 1, EQ, "/\thePC_CurrentPC_reg[25] /D"; + 0, AU.BB, "/\thePC_CurrentPC_reg[25] /D"; + 0, EQ, "/i_0_0_39/ZN"; + 1, EQ, "/i_0_0_39/A"; + 1, EQ, "/i_0_0_40/ZN"; + 0, AU.BB, "/theDecoder/i_18_31/CO"; + 0, EQ, "/theDecoder/i_18_33/B"; + 1, AU.BB, "/theDecoder/i_18_31/CO"; + 1, EQ, "/theDecoder/i_18_33/B"; + 1, AU.BB, "/theDecoder/i_0_103/A2"; + 0, AU.BB, "/theDecoder/i_0_106/B2"; + 0, EQ, "/theDecoder/i_0_106/B1"; + 0, EQ, "/theDecoder/i_17_33/ZN"; + 1, AU.BB, "/theDecoder/i_17_33/ZN"; + 1, EQ, "/theDecoder/i_0_106/B2"; + 1, AU.BB, "/theDecoder/theALU/i_0_479/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_477/A"; + 0, AU.BB, "/theRegisters/i_0_0_24/ZN"; + 0, EQ, "/theRegisters/i_0_0_24/A1"; + 0, EQ, "/theRegisters/i_0_0_24/A2"; + 0, EQ, "/theDecoder/theALU/i_0_452/ZN"; + 0, AU.BB, "/theRegisters/\registers_reg[10][23] /D"; + 1, DS, "/theRegisters/\registers_reg[10][23] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[2][23] /D"; + 1, DS, "/theRegisters/\registers_reg[2][23] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[12][23] /D"; + 1, DS, "/theRegisters/\registers_reg[12][23] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[4][23] /D"; + 1, DS, "/theRegisters/\registers_reg[4][23] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[5][23] /D"; + 1, DS, "/theRegisters/\registers_reg[5][23] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[13][23] /D"; + 1, DS, "/theRegisters/\registers_reg[13][23] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[11][23] /D"; + 1, DS, "/theRegisters/\registers_reg[11][23] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[27][23] /D"; + 1, DS, "/theRegisters/\registers_reg[27][23] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[25][23] /D"; + 1, DS, "/theRegisters/\registers_reg[25][23] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[6][23] /D"; + 1, DS, "/theRegisters/\registers_reg[6][23] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[7][23] /D"; + 1, DS, "/theRegisters/\registers_reg[7][23] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[16][23] /D"; + 1, DS, "/theRegisters/\registers_reg[16][23] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[14][23] /D"; + 1, DS, "/theRegisters/\registers_reg[14][23] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[15][23] /D"; + 1, DS, "/theRegisters/\registers_reg[15][23] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[24][23] /D"; + 1, DS, "/theRegisters/\registers_reg[24][23] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[17][23] /D"; + 1, DS, "/theRegisters/\registers_reg[17][23] /D"; + 0, AU.BB, "/theDecoder/i_0_94/C1"; + 0, EQ, "/theDecoder/i_0_94/C2"; + 0, EQ, "/theDecoder/i_5_29/S"; + 1, AU.BB, "/theDecoder/i_5_29/S"; + 1, EQ, "/theDecoder/i_0_94/C1"; + 0, AU.BB, "/i_0_0_42/A2"; + 0, EQ, "/i_0_0_42/A1"; + 0, EQ, "/theDecoder/i_0_90/ZN"; + 0, AU.BB, "/theDecoder/i_0_106/A1"; + 0, EQ, "/theDecoder/i_0_106/A2"; + 0, EQ, "/theDecoder/i_18_33/ZN"; + 1, AU.BB, "/theDecoder/i_18_33/ZN"; + 1, EQ, "/theDecoder/i_0_106/A1"; + 1, AU.BB, "/theDecoder/i_0_106/B1"; + 0, AU.BB, "/theDecoder/theALU/i_0_498/B1"; + 0, EQ, "/theDecoder/theALU/i_0_498/B2"; + 0, EQ, "/theDecoder/theALU/i_9_26/S"; + 1, AU.BB, "/theDecoder/theALU/i_9_26/S"; + 1, EQ, "/theDecoder/theALU/i_0_498/B1"; + 0, AU.BB, "/theDecoder/theALU/i_0_477/ZN"; + 0, EQ, "/theDecoder/theALU/i_0_476/A"; + 1, DS, "/theRegisters/i_0_0_24/ZN"; + 1, AU.BB, "/theRegisters/i_0_0_24/A1"; + 0, AU.BB, "/theDecoder/i_5_30/CI"; + 0, EQ, "/theDecoder/i_5_29/CO"; + 1, AU.BB, "/theDecoder/i_5_30/CI"; + 1, EQ, "/theDecoder/i_5_29/CO"; + 1, AU.BB, "/theDecoder/i_0_94/C2"; + 1, AU, "/i_0_0_42/A2"; + 1, AU.BB, "/theDecoder/i_0_106/A2"; + 0, AU.BB, "/theDecoder/theALU/i_9_27/CI"; + 0, EQ, "/theDecoder/theALU/i_9_26/CO"; + 1, AU.BB, "/theDecoder/theALU/i_9_27/CI"; + 1, EQ, "/theDecoder/theALU/i_9_26/CO"; + 1, AU.BB, "/theDecoder/theALU/i_0_498/B2"; + 1, AU.BB, "/theDecoder/theALU/i_0_476/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_470/A1"; + 0, AU.BB, "/theRegisters/\registers_reg[28][24] /D"; + 1, DS, "/theRegisters/\registers_reg[28][24] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[1][24] /D"; + 1, DS, "/theRegisters/\registers_reg[1][24] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[22][24] /D"; + 1, DS, "/theRegisters/\registers_reg[22][24] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[30][24] /D"; + 1, DS, "/theRegisters/\registers_reg[30][24] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[13][24] /D"; + 1, DS, "/theRegisters/\registers_reg[13][24] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[2][24] /D"; + 1, DS, "/theRegisters/\registers_reg[2][24] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[10][24] /D"; + 1, DS, "/theRegisters/\registers_reg[10][24] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[11][24] /D"; + 1, DS, "/theRegisters/\registers_reg[11][24] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[5][24] /D"; + 1, DS, "/theRegisters/\registers_reg[5][24] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[12][24] /D"; + 1, DS, "/theRegisters/\registers_reg[12][24] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[20][24] /D"; + 1, DS, "/theRegisters/\registers_reg[20][24] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[8][24] /D"; + 1, DS, "/theRegisters/\registers_reg[8][24] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[6][24] /D"; + 1, DS, "/theRegisters/\registers_reg[6][24] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[21][24] /D"; + 1, DS, "/theRegisters/\registers_reg[21][24] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[17][24] /D"; + 1, DS, "/theRegisters/\registers_reg[17][24] /D"; + 1, AU.BB, "/theDecoder/i_0_94/ZN"; + 1, EQ, "/theDecoder/i_0_93/A1"; + 1, DS, "/i_0_0_41/ZN"; + 0, EQ, "/i_0_0_41/A"; + 0, EQ, "/i_0_0_42/ZN"; + 1, EQ, "/\thePC_CurrentPC_reg[26] /D"; + 0, AU.BB, "/\thePC_CurrentPC_reg[26] /D"; + 0, EQ, "/i_0_0_41/ZN"; + 1, EQ, "/i_0_0_41/A"; + 1, EQ, "/i_0_0_42/ZN"; + 1, AU.BB, "/theDecoder/theALU/i_0_498/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_497/A2"; + 0, AU.BB, "/theRegisters/i_0_0_25/ZN"; + 0, EQ, "/theRegisters/i_0_0_25/A1"; + 0, EQ, "/theRegisters/i_0_0_25/A2"; + 0, EQ, "/theDecoder/theALU/i_0_470/ZN"; + 0, AU.BB, "/theRegisters/\registers_reg[31][24] /D"; + 1, DS, "/theRegisters/\registers_reg[31][24] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[27][24] /D"; + 1, DS, "/theRegisters/\registers_reg[27][24] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[3][24] /D"; + 1, DS, "/theRegisters/\registers_reg[3][24] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[23][24] /D"; + 1, DS, "/theRegisters/\registers_reg[23][24] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[29][24] /D"; + 1, DS, "/theRegisters/\registers_reg[29][24] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[9][24] /D"; + 1, DS, "/theRegisters/\registers_reg[9][24] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[14][24] /D"; + 1, DS, "/theRegisters/\registers_reg[14][24] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[7][24] /D"; + 1, DS, "/theRegisters/\registers_reg[7][24] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[16][24] /D"; + 1, DS, "/theRegisters/\registers_reg[16][24] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[19][24] /D"; + 1, DS, "/theRegisters/\registers_reg[19][24] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[25][24] /D"; + 1, DS, "/theRegisters/\registers_reg[25][24] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[15][24] /D"; + 1, DS, "/theRegisters/\registers_reg[15][24] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[4][24] /D"; + 1, DS, "/theRegisters/\registers_reg[4][24] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[24][24] /D"; + 1, DS, "/theRegisters/\registers_reg[24][24] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[26][24] /D"; + 1, DS, "/theRegisters/\registers_reg[26][24] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[18][24] /D"; + 1, DS, "/theRegisters/\registers_reg[18][24] /D"; + 0, AU.BB, "/theDecoder/i_0_97/C1"; + 0, EQ, "/theDecoder/i_0_97/C2"; + 0, EQ, "/theDecoder/i_5_30/S"; + 1, AU.BB, "/theDecoder/i_5_30/S"; + 1, EQ, "/theDecoder/i_0_97/C1"; + 0, AU.BB, "/i_0_0_44/A2"; + 0, EQ, "/i_0_0_44/A1"; + 0, EQ, "/theDecoder/i_0_93/ZN"; + 0, AU.BB, "/theDecoder/theALU/i_0_517/A1"; + 0, EQ, "/theDecoder/theALU/i_0_517/A2"; + 0, EQ, "/theDecoder/theALU/i_9_27/S"; + 1, AU.BB, "/theDecoder/theALU/i_9_27/S"; + 1, EQ, "/theDecoder/theALU/i_0_517/A1"; + 0, AU.BB, "/theDecoder/theALU/i_0_497/ZN"; + 0, EQ, "/theDecoder/theALU/i_0_488/A"; + 1, DS, "/theRegisters/i_0_0_25/ZN"; + 1, AU.BB, "/theRegisters/i_0_0_25/A1"; + 0, AU.BB, "/theDecoder/i_5_31/CI"; + 0, EQ, "/theDecoder/i_5_30/CO"; + 1, AU.BB, "/theDecoder/i_5_31/CI"; + 1, EQ, "/theDecoder/i_5_30/CO"; + 1, AU.BB, "/theDecoder/i_0_97/C2"; + 1, AU, "/i_0_0_44/A2"; + 0, AU.BB, "/theDecoder/theALU/i_9_28/CI"; + 0, EQ, "/theDecoder/theALU/i_9_27/CO"; + 1, AU.BB, "/theDecoder/theALU/i_9_28/CI"; + 1, EQ, "/theDecoder/theALU/i_9_27/CO"; + 1, AU.BB, "/theDecoder/theALU/i_0_517/A2"; + 1, AU.BB, "/theDecoder/theALU/i_0_488/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_487/A"; + 0, AU.BB, "/theRegisters/\registers_reg[28][25] /D"; + 1, DS, "/theRegisters/\registers_reg[28][25] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[1][25] /D"; + 1, DS, "/theRegisters/\registers_reg[1][25] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[22][25] /D"; + 1, DS, "/theRegisters/\registers_reg[22][25] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[30][25] /D"; + 1, DS, "/theRegisters/\registers_reg[30][25] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[13][25] /D"; + 1, DS, "/theRegisters/\registers_reg[13][25] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[2][25] /D"; + 1, DS, "/theRegisters/\registers_reg[2][25] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[10][25] /D"; + 1, DS, "/theRegisters/\registers_reg[10][25] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[11][25] /D"; + 1, DS, "/theRegisters/\registers_reg[11][25] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[5][25] /D"; + 1, DS, "/theRegisters/\registers_reg[5][25] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[12][25] /D"; + 1, DS, "/theRegisters/\registers_reg[12][25] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[20][25] /D"; + 1, DS, "/theRegisters/\registers_reg[20][25] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[8][25] /D"; + 1, DS, "/theRegisters/\registers_reg[8][25] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[6][25] /D"; + 1, DS, "/theRegisters/\registers_reg[6][25] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[21][25] /D"; + 1, DS, "/theRegisters/\registers_reg[21][25] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[17][25] /D"; + 1, DS, "/theRegisters/\registers_reg[17][25] /D"; + 1, AU.BB, "/theDecoder/i_0_97/ZN"; + 1, EQ, "/theDecoder/i_0_96/A1"; + 1, DS, "/i_0_0_43/ZN"; + 0, EQ, "/i_0_0_43/A"; + 0, EQ, "/i_0_0_44/ZN"; + 1, EQ, "/\thePC_CurrentPC_reg[27] /D"; + 0, AU.BB, "/\thePC_CurrentPC_reg[27] /D"; + 0, EQ, "/i_0_0_43/ZN"; + 1, EQ, "/i_0_0_43/A"; + 1, EQ, "/i_0_0_44/ZN"; + 1, AU.BB, "/theDecoder/theALU/i_0_517/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_514/A"; + 0, AU.BB, "/theRegisters/i_0_0_26/ZN"; + 0, EQ, "/theRegisters/i_0_0_26/A1"; + 0, EQ, "/theRegisters/i_0_0_26/A2"; + 0, EQ, "/theDecoder/theALU/i_0_487/ZN"; + 0, AU.BB, "/theRegisters/\registers_reg[31][25] /D"; + 1, DS, "/theRegisters/\registers_reg[31][25] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[27][25] /D"; + 1, DS, "/theRegisters/\registers_reg[27][25] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[3][25] /D"; + 1, DS, "/theRegisters/\registers_reg[3][25] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[23][25] /D"; + 1, DS, "/theRegisters/\registers_reg[23][25] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[29][25] /D"; + 1, DS, "/theRegisters/\registers_reg[29][25] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[9][25] /D"; + 1, DS, "/theRegisters/\registers_reg[9][25] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[14][25] /D"; + 1, DS, "/theRegisters/\registers_reg[14][25] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[7][25] /D"; + 1, DS, "/theRegisters/\registers_reg[7][25] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[25][25] /D"; + 1, DS, "/theRegisters/\registers_reg[25][25] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[19][25] /D"; + 1, DS, "/theRegisters/\registers_reg[19][25] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[16][25] /D"; + 1, DS, "/theRegisters/\registers_reg[16][25] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[15][25] /D"; + 1, DS, "/theRegisters/\registers_reg[15][25] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[4][25] /D"; + 1, DS, "/theRegisters/\registers_reg[4][25] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[24][25] /D"; + 1, DS, "/theRegisters/\registers_reg[24][25] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[26][25] /D"; + 1, DS, "/theRegisters/\registers_reg[26][25] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[18][25] /D"; + 1, DS, "/theRegisters/\registers_reg[18][25] /D"; + 0, AU.BB, "/theDecoder/i_0_100/C1"; + 0, EQ, "/theDecoder/i_0_100/C2"; + 0, EQ, "/theDecoder/i_5_31/S"; + 1, AU.BB, "/theDecoder/i_5_31/S"; + 1, EQ, "/theDecoder/i_0_100/C1"; + 0, AU.BB, "/i_0_0_46/A2"; + 0, EQ, "/i_0_0_46/A1"; + 0, EQ, "/theDecoder/i_0_96/ZN"; + 0, AU.BB, "/theDecoder/theALU/i_0_542/A1"; + 0, EQ, "/theDecoder/theALU/i_0_542/A2"; + 0, EQ, "/theDecoder/theALU/i_9_28/S"; + 1, AU.BB, "/theDecoder/theALU/i_9_28/S"; + 1, EQ, "/theDecoder/theALU/i_0_542/A1"; + 0, AU.BB, "/theDecoder/theALU/i_0_514/ZN"; + 0, EQ, "/theDecoder/theALU/i_0_513/A"; + 1, DS, "/theRegisters/i_0_0_26/ZN"; + 1, AU.BB, "/theRegisters/i_0_0_26/A1"; + 0, AU.BB, "/theDecoder/i_5_32/CI"; + 0, EQ, "/theDecoder/i_5_31/CO"; + 1, AU.BB, "/theDecoder/i_5_32/CI"; + 1, EQ, "/theDecoder/i_5_31/CO"; + 1, AU.BB, "/theDecoder/i_0_100/C2"; + 1, AU, "/i_0_0_46/A2"; + 0, AU.BB, "/theDecoder/theALU/i_9_29/CI"; + 0, EQ, "/theDecoder/theALU/i_9_28/CO"; + 1, AU.BB, "/theDecoder/theALU/i_9_29/CI"; + 1, EQ, "/theDecoder/theALU/i_9_28/CO"; + 1, AU.BB, "/theDecoder/theALU/i_0_542/A2"; + 1, AU.BB, "/theDecoder/theALU/i_0_513/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_512/A"; + 0, AU.BB, "/theRegisters/\registers_reg[28][26] /D"; + 1, DS, "/theRegisters/\registers_reg[28][26] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[5][26] /D"; + 1, DS, "/theRegisters/\registers_reg[5][26] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[6][26] /D"; + 1, DS, "/theRegisters/\registers_reg[6][26] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[31][26] /D"; + 1, DS, "/theRegisters/\registers_reg[31][26] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[16][26] /D"; + 1, DS, "/theRegisters/\registers_reg[16][26] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[27][26] /D"; + 1, DS, "/theRegisters/\registers_reg[27][26] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[25][26] /D"; + 1, DS, "/theRegisters/\registers_reg[25][26] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[11][26] /D"; + 1, DS, "/theRegisters/\registers_reg[11][26] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[7][26] /D"; + 1, DS, "/theRegisters/\registers_reg[7][26] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[9][26] /D"; + 1, DS, "/theRegisters/\registers_reg[9][26] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[2][26] /D"; + 1, DS, "/theRegisters/\registers_reg[2][26] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[29][26] /D"; + 1, DS, "/theRegisters/\registers_reg[29][26] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[1][26] /D"; + 1, DS, "/theRegisters/\registers_reg[1][26] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[22][26] /D"; + 1, DS, "/theRegisters/\registers_reg[22][26] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[18][26] /D"; + 1, DS, "/theRegisters/\registers_reg[18][26] /D"; + 1, AU.BB, "/theDecoder/i_0_100/ZN"; + 1, EQ, "/theDecoder/i_0_99/A1"; + 1, DS, "/i_0_0_45/ZN"; + 0, EQ, "/i_0_0_45/A"; + 0, EQ, "/i_0_0_46/ZN"; + 1, EQ, "/\thePC_CurrentPC_reg[28] /D"; + 0, AU.BB, "/\thePC_CurrentPC_reg[28] /D"; + 0, EQ, "/i_0_0_45/ZN"; + 1, EQ, "/i_0_0_45/A"; + 1, EQ, "/i_0_0_46/ZN"; + 1, AU.BB, "/theDecoder/theALU/i_0_542/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_541/A"; + 0, AU.BB, "/theRegisters/i_0_0_27/ZN"; + 0, EQ, "/theRegisters/i_0_0_27/A1"; + 0, EQ, "/theRegisters/i_0_0_27/A2"; + 0, EQ, "/theDecoder/theALU/i_0_512/ZN"; + 0, AU.BB, "/theRegisters/\registers_reg[3][26] /D"; + 1, DS, "/theRegisters/\registers_reg[3][26] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[10][26] /D"; + 1, DS, "/theRegisters/\registers_reg[10][26] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[14][26] /D"; + 1, DS, "/theRegisters/\registers_reg[14][26] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[15][26] /D"; + 1, DS, "/theRegisters/\registers_reg[15][26] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[17][26] /D"; + 1, DS, "/theRegisters/\registers_reg[17][26] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[13][26] /D"; + 1, DS, "/theRegisters/\registers_reg[13][26] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[23][26] /D"; + 1, DS, "/theRegisters/\registers_reg[23][26] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[8][26] /D"; + 1, DS, "/theRegisters/\registers_reg[8][26] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[30][26] /D"; + 1, DS, "/theRegisters/\registers_reg[30][26] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[26][26] /D"; + 1, DS, "/theRegisters/\registers_reg[26][26] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[20][26] /D"; + 1, DS, "/theRegisters/\registers_reg[20][26] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[24][26] /D"; + 1, DS, "/theRegisters/\registers_reg[24][26] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[21][26] /D"; + 1, DS, "/theRegisters/\registers_reg[21][26] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[19][26] /D"; + 1, DS, "/theRegisters/\registers_reg[19][26] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[12][26] /D"; + 1, DS, "/theRegisters/\registers_reg[12][26] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[4][26] /D"; + 1, DS, "/theRegisters/\registers_reg[4][26] /D"; + 0, AU.BB, "/theDecoder/i_0_103/C1"; + 0, EQ, "/theDecoder/i_0_103/C2"; + 0, EQ, "/theDecoder/i_5_32/S"; + 1, AU.BB, "/theDecoder/i_5_32/S"; + 1, EQ, "/theDecoder/i_0_103/C1"; + 0, AU.BB, "/i_0_0_48/A2"; + 0, EQ, "/i_0_0_48/A1"; + 0, EQ, "/theDecoder/i_0_99/ZN"; + 0, AU.BB, "/theDecoder/theALU/i_0_553/C1"; + 0, EQ, "/theDecoder/theALU/i_0_553/C2"; + 0, EQ, "/theDecoder/theALU/i_9_29/S"; + 1, AU.BB, "/theDecoder/theALU/i_9_29/S"; + 1, EQ, "/theDecoder/theALU/i_0_553/C1"; + 0, AU.BB, "/theDecoder/theALU/i_0_541/ZN"; + 0, EQ, "/theDecoder/theALU/i_0_538/A2"; + 1, DS, "/theRegisters/i_0_0_27/ZN"; + 1, AU.BB, "/theRegisters/i_0_0_27/A1"; + 0, AU.BB, "/theDecoder/i_5_32/CO"; + 0, EQ, "/theDecoder/i_5_34/B"; + 1, AU.BB, "/theDecoder/i_5_32/CO"; + 1, EQ, "/theDecoder/i_5_34/B"; + 1, AU.BB, "/theDecoder/i_0_103/C2"; + 1, AU, "/i_0_0_48/A2"; + 0, AU.BB, "/theDecoder/theALU/i_9_30/CI"; + 0, EQ, "/theDecoder/theALU/i_9_29/CO"; + 1, AU.BB, "/theDecoder/theALU/i_9_30/CI"; + 1, EQ, "/theDecoder/theALU/i_9_29/CO"; + 1, AU.BB, "/theDecoder/theALU/i_0_553/C2"; + 1, AU.BB, "/theDecoder/theALU/i_0_538/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_537/A"; + 0, AU.BB, "/theRegisters/\registers_reg[28][27] /D"; + 1, DS, "/theRegisters/\registers_reg[28][27] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[5][27] /D"; + 1, DS, "/theRegisters/\registers_reg[5][27] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[22][27] /D"; + 1, DS, "/theRegisters/\registers_reg[22][27] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[30][27] /D"; + 1, DS, "/theRegisters/\registers_reg[30][27] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[1][27] /D"; + 1, DS, "/theRegisters/\registers_reg[1][27] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[6][27] /D"; + 1, DS, "/theRegisters/\registers_reg[6][27] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[10][27] /D"; + 1, DS, "/theRegisters/\registers_reg[10][27] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[16][27] /D"; + 1, DS, "/theRegisters/\registers_reg[16][27] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[11][27] /D"; + 1, DS, "/theRegisters/\registers_reg[11][27] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[7][27] /D"; + 1, DS, "/theRegisters/\registers_reg[7][27] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[9][27] /D"; + 1, DS, "/theRegisters/\registers_reg[9][27] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[25][27] /D"; + 1, DS, "/theRegisters/\registers_reg[25][27] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[8][27] /D"; + 1, DS, "/theRegisters/\registers_reg[8][27] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[2][27] /D"; + 1, DS, "/theRegisters/\registers_reg[2][27] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[29][27] /D"; + 1, DS, "/theRegisters/\registers_reg[29][27] /D"; + 0, AU.BB, "/theDecoder/i_0_106/C1"; + 0, EQ, "/theDecoder/i_0_106/C2"; + 0, EQ, "/theDecoder/i_5_34/ZN"; + 1, AU.BB, "/theDecoder/i_5_34/ZN"; + 1, EQ, "/theDecoder/i_0_106/C1"; + 1, AU.BB, "/theDecoder/i_0_103/ZN"; + 1, EQ, "/theDecoder/i_0_102/A1"; + 1, DS, "/i_0_0_47/ZN"; + 0, EQ, "/i_0_0_47/A"; + 0, EQ, "/i_0_0_48/ZN"; + 1, EQ, "/\thePC_CurrentPC_reg[29] /D"; + 0, AU.BB, "/\thePC_CurrentPC_reg[29] /D"; + 0, EQ, "/i_0_0_47/ZN"; + 1, EQ, "/i_0_0_47/A"; + 1, EQ, "/i_0_0_48/ZN"; + 1, AU.BB, "/theDecoder/theALU/i_0_553/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_552/A3"; + 0, AU.BB, "/theDecoder/theALU/i_0_553/A"; + 0, AU.BB, "/theRegisters/i_0_0_28/ZN"; + 0, EQ, "/theRegisters/i_0_0_28/A1"; + 0, EQ, "/theRegisters/i_0_0_28/A2"; + 0, EQ, "/theDecoder/theALU/i_0_537/ZN"; + 0, AU.BB, "/theRegisters/\registers_reg[31][27] /D"; + 1, DS, "/theRegisters/\registers_reg[31][27] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[27][27] /D"; + 1, DS, "/theRegisters/\registers_reg[27][27] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[14][27] /D"; + 1, DS, "/theRegisters/\registers_reg[14][27] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[15][27] /D"; + 1, DS, "/theRegisters/\registers_reg[15][27] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[17][27] /D"; + 1, DS, "/theRegisters/\registers_reg[17][27] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[13][27] /D"; + 1, DS, "/theRegisters/\registers_reg[13][27] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[3][27] /D"; + 1, DS, "/theRegisters/\registers_reg[3][27] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[23][27] /D"; + 1, DS, "/theRegisters/\registers_reg[23][27] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[26][27] /D"; + 1, DS, "/theRegisters/\registers_reg[26][27] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[18][27] /D"; + 1, DS, "/theRegisters/\registers_reg[18][27] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[20][27] /D"; + 1, DS, "/theRegisters/\registers_reg[20][27] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[24][27] /D"; + 1, DS, "/theRegisters/\registers_reg[24][27] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[21][27] /D"; + 1, DS, "/theRegisters/\registers_reg[21][27] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[19][27] /D"; + 1, DS, "/theRegisters/\registers_reg[19][27] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[12][27] /D"; + 1, DS, "/theRegisters/\registers_reg[12][27] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[4][27] /D"; + 1, DS, "/theRegisters/\registers_reg[4][27] /D"; + 1, AU.BB, "/theDecoder/i_0_106/C2"; + 0, AU.BB, "/i_0_0_50/A2"; + 0, EQ, "/i_0_0_50/A1"; + 0, EQ, "/theDecoder/i_0_102/ZN"; + 0, AU.BB, "/theDecoder/theALU/i_0_580/B1"; + 0, EQ, "/theDecoder/theALU/i_0_580/B2"; + 0, EQ, "/theDecoder/theALU/i_9_30/S"; + 1, AU.BB, "/theDecoder/theALU/i_9_30/S"; + 1, EQ, "/theDecoder/theALU/i_0_580/B1"; + 1, AU.BB, "/theDecoder/theALU/i_0_552/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_551/A"; + 1, DS, "/theRegisters/i_0_0_28/ZN"; + 1, AU.BB, "/theRegisters/i_0_0_28/A1"; + 1, AU.BB, "/theDecoder/i_0_106/ZN"; + 1, EQ, "/theDecoder/i_0_105/A1"; + 1, AU, "/i_0_0_50/A2"; + 0, AU.BB, "/theDecoder/theALU/i_9_30/CO"; + 0, EQ, "/theDecoder/theALU/i_9_32/B"; + 1, AU.BB, "/theDecoder/theALU/i_9_30/CO"; + 1, EQ, "/theDecoder/theALU/i_9_32/B"; + 1, AU.BB, "/theDecoder/theALU/i_0_580/B2"; + 0, AU.BB, "/theRegisters/i_0_0_29/ZN"; + 0, EQ, "/theRegisters/i_0_0_29/A1"; + 0, EQ, "/theRegisters/i_0_0_29/A2"; + 0, EQ, "/theDecoder/theALU/i_0_551/ZN"; + 0, AU.BB, "/theRegisters/\registers_reg[20][28] /D"; + 1, DS, "/theRegisters/\registers_reg[20][28] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[4][28] /D"; + 1, DS, "/theRegisters/\registers_reg[4][28] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[25][28] /D"; + 1, DS, "/theRegisters/\registers_reg[25][28] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[13][28] /D"; + 1, DS, "/theRegisters/\registers_reg[13][28] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[29][28] /D"; + 1, DS, "/theRegisters/\registers_reg[29][28] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[9][28] /D"; + 1, DS, "/theRegisters/\registers_reg[9][28] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[2][28] /D"; + 1, DS, "/theRegisters/\registers_reg[2][28] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[17][28] /D"; + 1, DS, "/theRegisters/\registers_reg[17][28] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[14][28] /D"; + 1, DS, "/theRegisters/\registers_reg[14][28] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[28][28] /D"; + 1, DS, "/theRegisters/\registers_reg[28][28] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[12][28] /D"; + 1, DS, "/theRegisters/\registers_reg[12][28] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[5][28] /D"; + 1, DS, "/theRegisters/\registers_reg[5][28] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[22][28] /D"; + 1, DS, "/theRegisters/\registers_reg[22][28] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[26][28] /D"; + 1, DS, "/theRegisters/\registers_reg[26][28] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[15][28] /D"; + 1, DS, "/theRegisters/\registers_reg[15][28] /D"; + 0, AU.BB, "/i_0_0_52/A2"; + 0, EQ, "/i_0_0_52/A1"; + 0, EQ, "/theDecoder/i_0_105/ZN"; + 1, DS, "/i_0_0_49/ZN"; + 0, EQ, "/i_0_0_49/A"; + 0, EQ, "/i_0_0_50/ZN"; + 1, EQ, "/\thePC_CurrentPC_reg[30] /D"; + 0, AU.BB, "/\thePC_CurrentPC_reg[30] /D"; + 0, EQ, "/i_0_0_49/ZN"; + 1, EQ, "/i_0_0_49/A"; + 1, EQ, "/i_0_0_50/ZN"; + 0, AU.BB, "/theDecoder/theALU/i_0_587/B1"; + 0, EQ, "/theDecoder/theALU/i_0_587/B2"; + 0, EQ, "/theDecoder/theALU/i_9_32/ZN"; + 1, AU.BB, "/theDecoder/theALU/i_9_32/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_587/B1"; + 1, AU.BB, "/theDecoder/theALU/i_0_580/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_571/A"; + 1, DS, "/theRegisters/i_0_0_29/ZN"; + 1, AU.BB, "/theRegisters/i_0_0_29/A1"; + 0, AU.BB, "/theRegisters/\registers_reg[18][28] /D"; + 1, DS, "/theRegisters/\registers_reg[18][28] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[19][28] /D"; + 1, DS, "/theRegisters/\registers_reg[19][28] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[7][28] /D"; + 1, DS, "/theRegisters/\registers_reg[7][28] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[27][28] /D"; + 1, DS, "/theRegisters/\registers_reg[27][28] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[31][28] /D"; + 1, DS, "/theRegisters/\registers_reg[31][28] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[11][28] /D"; + 1, DS, "/theRegisters/\registers_reg[11][28] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[3][28] /D"; + 1, DS, "/theRegisters/\registers_reg[3][28] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[16][28] /D"; + 1, DS, "/theRegisters/\registers_reg[16][28] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[24][28] /D"; + 1, DS, "/theRegisters/\registers_reg[24][28] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[8][28] /D"; + 1, DS, "/theRegisters/\registers_reg[8][28] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[30][28] /D"; + 1, DS, "/theRegisters/\registers_reg[30][28] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[6][28] /D"; + 1, DS, "/theRegisters/\registers_reg[6][28] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[21][28] /D"; + 1, DS, "/theRegisters/\registers_reg[21][28] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[10][28] /D"; + 1, DS, "/theRegisters/\registers_reg[10][28] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[23][28] /D"; + 1, DS, "/theRegisters/\registers_reg[23][28] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[1][28] /D"; + 1, DS, "/theRegisters/\registers_reg[1][28] /D"; + 1, AU, "/i_0_0_52/A2"; + 1, AU.BB, "/theDecoder/theALU/i_0_587/B2"; + 0, AU.BB, "/theDecoder/theALU/i_0_571/ZN"; + 0, EQ, "/theDecoder/theALU/i_0_570/A"; + 0, AU.BB, "/theRegisters/\registers_reg[13][29] /D"; + 1, DS, "/theRegisters/\registers_reg[13][29] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[21][29] /D"; + 1, DS, "/theRegisters/\registers_reg[21][29] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[25][29] /D"; + 1, DS, "/theRegisters/\registers_reg[25][29] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[26][29] /D"; + 1, DS, "/theRegisters/\registers_reg[26][29] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[10][29] /D"; + 1, DS, "/theRegisters/\registers_reg[10][29] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[29][29] /D"; + 1, DS, "/theRegisters/\registers_reg[29][29] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[23][29] /D"; + 1, DS, "/theRegisters/\registers_reg[23][29] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[4][29] /D"; + 1, DS, "/theRegisters/\registers_reg[4][29] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[19][29] /D"; + 1, DS, "/theRegisters/\registers_reg[19][29] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[20][29] /D"; + 1, DS, "/theRegisters/\registers_reg[20][29] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[24][29] /D"; + 1, DS, "/theRegisters/\registers_reg[24][29] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[7][29] /D"; + 1, DS, "/theRegisters/\registers_reg[7][29] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[31][29] /D"; + 1, DS, "/theRegisters/\registers_reg[31][29] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[8][29] /D"; + 1, DS, "/theRegisters/\registers_reg[8][29] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[28][29] /D"; + 1, DS, "/theRegisters/\registers_reg[28][29] /D"; + 1, DS, "/i_0_0_51/ZN"; + 0, EQ, "/i_0_0_51/A"; + 0, EQ, "/i_0_0_52/ZN"; + 1, EQ, "/\thePC_CurrentPC_reg[31] /D"; + 0, AU.BB, "/\thePC_CurrentPC_reg[31] /D"; + 0, EQ, "/i_0_0_51/ZN"; + 1, EQ, "/i_0_0_51/A"; + 1, EQ, "/i_0_0_52/ZN"; + 1, AU.BB, "/theDecoder/theALU/i_0_587/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_586/A"; + 1, AU.BB, "/theDecoder/theALU/i_0_570/ZN"; + 1, EQ, "/theDecoder/theALU/i_0_569/A"; + 0, AU.BB, "/theRegisters/\registers_reg[2][29] /D"; + 1, DS, "/theRegisters/\registers_reg[2][29] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[3][29] /D"; + 1, DS, "/theRegisters/\registers_reg[3][29] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[11][29] /D"; + 1, DS, "/theRegisters/\registers_reg[11][29] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[27][29] /D"; + 1, DS, "/theRegisters/\registers_reg[27][29] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[14][29] /D"; + 1, DS, "/theRegisters/\registers_reg[14][29] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[6][29] /D"; + 1, DS, "/theRegisters/\registers_reg[6][29] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[1][29] /D"; + 1, DS, "/theRegisters/\registers_reg[1][29] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[9][29] /D"; + 1, DS, "/theRegisters/\registers_reg[9][29] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[5][29] /D"; + 1, DS, "/theRegisters/\registers_reg[5][29] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[22][29] /D"; + 1, DS, "/theRegisters/\registers_reg[22][29] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[16][29] /D"; + 1, DS, "/theRegisters/\registers_reg[16][29] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[15][29] /D"; + 1, DS, "/theRegisters/\registers_reg[15][29] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[12][29] /D"; + 1, DS, "/theRegisters/\registers_reg[12][29] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[17][29] /D"; + 1, DS, "/theRegisters/\registers_reg[17][29] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[30][29] /D"; + 1, DS, "/theRegisters/\registers_reg[30][29] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[18][29] /D"; + 1, DS, "/theRegisters/\registers_reg[18][29] /D"; + 0, AU.BB, "/theRegisters/i_0_0_31/ZN"; + 0, EQ, "/theRegisters/i_0_0_31/A1"; + 0, EQ, "/theRegisters/i_0_0_31/A2"; + 0, EQ, "/theDecoder/theALU/i_0_586/ZN"; + 0, AU.BB, "/theRegisters/i_0_0_30/ZN"; + 0, EQ, "/theRegisters/i_0_0_30/A1"; + 0, EQ, "/theRegisters/i_0_0_30/A2"; + 0, EQ, "/theDecoder/theALU/i_0_569/ZN"; + 1, DS, "/theRegisters/i_0_0_31/ZN"; + 1, AU.BB, "/theRegisters/i_0_0_31/A1"; + 1, DS, "/theRegisters/i_0_0_30/ZN"; + 1, AU.BB, "/theRegisters/i_0_0_30/A1"; + 0, AU.BB, "/theRegisters/\registers_reg[29][31] /D"; + 1, DS, "/theRegisters/\registers_reg[29][31] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[9][31] /D"; + 1, DS, "/theRegisters/\registers_reg[9][31] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[8][31] /D"; + 1, DS, "/theRegisters/\registers_reg[8][31] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[26][31] /D"; + 1, DS, "/theRegisters/\registers_reg[26][31] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[10][31] /D"; + 1, DS, "/theRegisters/\registers_reg[10][31] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[5][31] /D"; + 1, DS, "/theRegisters/\registers_reg[5][31] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[19][31] /D"; + 1, DS, "/theRegisters/\registers_reg[19][31] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[7][31] /D"; + 1, DS, "/theRegisters/\registers_reg[7][31] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[23][31] /D"; + 1, DS, "/theRegisters/\registers_reg[23][31] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[1][31] /D"; + 1, DS, "/theRegisters/\registers_reg[1][31] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[6][31] /D"; + 1, DS, "/theRegisters/\registers_reg[6][31] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[31][31] /D"; + 1, DS, "/theRegisters/\registers_reg[31][31] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[16][31] /D"; + 1, DS, "/theRegisters/\registers_reg[16][31] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[4][31] /D"; + 1, DS, "/theRegisters/\registers_reg[4][31] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[28][31] /D"; + 1, DS, "/theRegisters/\registers_reg[28][31] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[29][30] /D"; + 1, DS, "/theRegisters/\registers_reg[29][30] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[9][30] /D"; + 1, DS, "/theRegisters/\registers_reg[9][30] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[8][30] /D"; + 1, DS, "/theRegisters/\registers_reg[8][30] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[26][30] /D"; + 1, DS, "/theRegisters/\registers_reg[26][30] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[10][30] /D"; + 1, DS, "/theRegisters/\registers_reg[10][30] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[5][30] /D"; + 1, DS, "/theRegisters/\registers_reg[5][30] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[19][30] /D"; + 1, DS, "/theRegisters/\registers_reg[19][30] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[7][30] /D"; + 1, DS, "/theRegisters/\registers_reg[7][30] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[23][30] /D"; + 1, DS, "/theRegisters/\registers_reg[23][30] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[1][30] /D"; + 1, DS, "/theRegisters/\registers_reg[1][30] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[6][30] /D"; + 1, DS, "/theRegisters/\registers_reg[6][30] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[31][30] /D"; + 1, DS, "/theRegisters/\registers_reg[31][30] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[16][30] /D"; + 1, DS, "/theRegisters/\registers_reg[16][30] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[17][30] /D"; + 1, DS, "/theRegisters/\registers_reg[17][30] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[28][30] /D"; + 1, DS, "/theRegisters/\registers_reg[28][30] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[2][31] /D"; + 1, DS, "/theRegisters/\registers_reg[2][31] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[3][31] /D"; + 1, DS, "/theRegisters/\registers_reg[3][31] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[14][31] /D"; + 1, DS, "/theRegisters/\registers_reg[14][31] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[15][31] /D"; + 1, DS, "/theRegisters/\registers_reg[15][31] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[25][31] /D"; + 1, DS, "/theRegisters/\registers_reg[25][31] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[13][31] /D"; + 1, DS, "/theRegisters/\registers_reg[13][31] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[11][31] /D"; + 1, DS, "/theRegisters/\registers_reg[11][31] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[27][31] /D"; + 1, DS, "/theRegisters/\registers_reg[27][31] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[20][31] /D"; + 1, DS, "/theRegisters/\registers_reg[20][31] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[17][31] /D"; + 1, DS, "/theRegisters/\registers_reg[17][31] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[21][31] /D"; + 1, DS, "/theRegisters/\registers_reg[21][31] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[22][31] /D"; + 1, DS, "/theRegisters/\registers_reg[22][31] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[12][31] /D"; + 1, DS, "/theRegisters/\registers_reg[12][31] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[24][31] /D"; + 1, DS, "/theRegisters/\registers_reg[24][31] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[30][31] /D"; + 1, DS, "/theRegisters/\registers_reg[30][31] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[18][31] /D"; + 1, DS, "/theRegisters/\registers_reg[18][31] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[2][30] /D"; + 1, DS, "/theRegisters/\registers_reg[2][30] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[3][30] /D"; + 1, DS, "/theRegisters/\registers_reg[3][30] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[14][30] /D"; + 1, DS, "/theRegisters/\registers_reg[14][30] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[15][30] /D"; + 1, DS, "/theRegisters/\registers_reg[15][30] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[25][30] /D"; + 1, DS, "/theRegisters/\registers_reg[25][30] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[13][30] /D"; + 1, DS, "/theRegisters/\registers_reg[13][30] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[11][30] /D"; + 1, DS, "/theRegisters/\registers_reg[11][30] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[27][30] /D"; + 1, DS, "/theRegisters/\registers_reg[27][30] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[12][30] /D"; + 1, DS, "/theRegisters/\registers_reg[12][30] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[24][30] /D"; + 1, DS, "/theRegisters/\registers_reg[24][30] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[21][30] /D"; + 1, DS, "/theRegisters/\registers_reg[21][30] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[22][30] /D"; + 1, DS, "/theRegisters/\registers_reg[22][30] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[4][30] /D"; + 1, DS, "/theRegisters/\registers_reg[4][30] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[20][30] /D"; + 1, DS, "/theRegisters/\registers_reg[20][30] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[30][30] /D"; + 1, DS, "/theRegisters/\registers_reg[30][30] /D"; + 0, AU.BB, "/theRegisters/\registers_reg[18][30] /D"; + 1, DS, "/theRegisters/\registers_reg[18][30] /D"; + 0, DI.CLK, "/\thePC_CurrentPC_reg[30] /CK"; + 1, DI.CLK, "/\thePC_CurrentPC_reg[30] /CK"; + 0, DI.CLK, "/\thePC_CurrentPC_reg[29] /CK"; + 1, DI.CLK, "/\thePC_CurrentPC_reg[29] /CK"; + 0, DI.CLK, "/\thePC_CurrentPC_reg[28] /CK"; + 1, DI.CLK, "/\thePC_CurrentPC_reg[28] /CK"; + 0, DI.CLK, "/\thePC_CurrentPC_reg[27] /CK"; + 1, DI.CLK, "/\thePC_CurrentPC_reg[27] /CK"; + 0, DI.CLK, "/\thePC_CurrentPC_reg[26] /CK"; + 1, DI.CLK, "/\thePC_CurrentPC_reg[26] /CK"; + 0, DI.CLK, "/\thePC_CurrentPC_reg[25] /CK"; + 1, DI.CLK, "/\thePC_CurrentPC_reg[25] /CK"; + 0, DI.CLK, "/\thePC_CurrentPC_reg[24] /CK"; + 1, DI.CLK, "/\thePC_CurrentPC_reg[24] /CK"; + 0, DI.CLK, "/\thePC_CurrentPC_reg[23] /CK"; + 1, DI.CLK, "/\thePC_CurrentPC_reg[23] /CK"; + 0, DI.CLK, "/\thePC_CurrentPC_reg[22] /CK"; + 1, DI.CLK, "/\thePC_CurrentPC_reg[22] /CK"; + 0, DI.CLK, "/\thePC_CurrentPC_reg[21] /CK"; + 1, DI.CLK, "/\thePC_CurrentPC_reg[21] /CK"; + 0, DI.CLK, "/\thePC_CurrentPC_reg[20] /CK"; + 1, DI.CLK, "/\thePC_CurrentPC_reg[20] /CK"; + 0, DI.CLK, "/\thePC_CurrentPC_reg[19] /CK"; + 1, DI.CLK, "/\thePC_CurrentPC_reg[19] /CK"; + 0, DI.CLK, "/\thePC_CurrentPC_reg[18] /CK"; + 1, DI.CLK, "/\thePC_CurrentPC_reg[18] /CK"; + 0, DI.CLK, "/\thePC_CurrentPC_reg[17] /CK"; + 1, DI.CLK, "/\thePC_CurrentPC_reg[17] /CK"; + 0, DI.CLK, "/\thePC_CurrentPC_reg[16] /CK"; + 1, DI.CLK, "/\thePC_CurrentPC_reg[16] /CK"; + 0, DI.CLK, "/\thePC_CurrentPC_reg[15] /CK"; + 1, DI.CLK, "/\thePC_CurrentPC_reg[15] /CK"; + 0, DI.CLK, "/\thePC_CurrentPC_reg[14] /CK"; + 1, DI.CLK, "/\thePC_CurrentPC_reg[14] /CK"; + 0, DI.CLK, "/\thePC_CurrentPC_reg[13] /CK"; + 1, DI.CLK, "/\thePC_CurrentPC_reg[13] /CK"; + 0, DI.CLK, "/\thePC_CurrentPC_reg[12] /CK"; + 1, DI.CLK, "/\thePC_CurrentPC_reg[12] /CK"; + 0, DI.CLK, "/\thePC_CurrentPC_reg[11] /CK"; + 1, DI.CLK, "/\thePC_CurrentPC_reg[11] /CK"; + 0, DI.CLK, "/\thePC_CurrentPC_reg[10] /CK"; + 1, DI.CLK, "/\thePC_CurrentPC_reg[10] /CK"; + 0, DI.CLK, "/\thePC_CurrentPC_reg[9] /CK"; + 1, DI.CLK, "/\thePC_CurrentPC_reg[9] /CK"; + 0, DI.CLK, "/\thePC_CurrentPC_reg[8] /CK"; + 1, DI.CLK, "/\thePC_CurrentPC_reg[8] /CK"; + 0, DI.CLK, "/\thePC_CurrentPC_reg[7] /CK"; + 1, DI.CLK, "/\thePC_CurrentPC_reg[7] /CK"; + 0, DI.CLK, "/\thePC_CurrentPC_reg[6] /CK"; + 1, DI.CLK, "/\thePC_CurrentPC_reg[6] /CK"; + 0, DI.CLK, "/\thePC_CurrentPC_reg[5] /CK"; + 1, DI.CLK, "/\thePC_CurrentPC_reg[5] /CK"; + 0, DI.CLK, "/\thePC_CurrentPC_reg[4] /CK"; + 1, DI.CLK, "/\thePC_CurrentPC_reg[4] /CK"; + 0, DI.CLK, "/\thePC_CurrentPC_reg[3] /CK"; + 1, DI.CLK, "/\thePC_CurrentPC_reg[3] /CK"; + 0, DI.CLK, "/\thePC_CurrentPC_reg[2] /CK"; + 1, DI.CLK, "/\thePC_CurrentPC_reg[2] /CK"; + 0, DI.CLK, "/\thePC_CurrentPC_reg[31] /CK"; + 1, DI.CLK, "/\thePC_CurrentPC_reg[31] /CK"; + 0, DI.CLK, "/\thePC_CurrentPC_reg[1] /CK"; + 1, DI.CLK, "/\thePC_CurrentPC_reg[1] /CK"; + 0, DI.CLK, "/\thePC_CurrentPC_reg[0] /CK"; + 1, DI.CLK, "/\thePC_CurrentPC_reg[0] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[28][31] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[28][31] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[4][31] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[4][31] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[16][31] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[16][31] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[31][31] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[31][31] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[6][31] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[6][31] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[1][31] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[1][31] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[23][31] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[23][31] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[7][31] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[7][31] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[19][31] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[19][31] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[5][31] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[5][31] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[10][31] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[10][31] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[26][31] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[26][31] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[8][31] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[8][31] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[9][31] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[9][31] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[29][31] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[29][31] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[18][31] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[18][31] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[30][31] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[30][31] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[24][31] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[24][31] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[12][31] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[12][31] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[22][31] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[22][31] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[21][31] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[21][31] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[17][31] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[17][31] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[20][31] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[20][31] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[27][31] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[27][31] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[11][31] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[11][31] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[13][31] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[13][31] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[25][31] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[25][31] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[15][31] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[15][31] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[14][31] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[14][31] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[3][31] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[3][31] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[2][31] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[2][31] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[28][30] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[28][30] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[17][30] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[17][30] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[16][30] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[16][30] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[31][30] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[31][30] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[6][30] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[6][30] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[1][30] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[1][30] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[23][30] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[23][30] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[7][30] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[7][30] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[19][30] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[19][30] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[5][30] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[5][30] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[10][30] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[10][30] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[26][30] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[26][30] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[8][30] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[8][30] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[9][30] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[9][30] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[29][30] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[29][30] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[18][30] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[18][30] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[30][30] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[30][30] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[20][30] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[20][30] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[4][30] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[4][30] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[22][30] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[22][30] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[21][30] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[21][30] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[24][30] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[24][30] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[12][30] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[12][30] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[27][30] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[27][30] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[11][30] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[11][30] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[13][30] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[13][30] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[25][30] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[25][30] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[15][30] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[15][30] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[14][30] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[14][30] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[3][30] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[3][30] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[2][30] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[2][30] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[28][29] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[28][29] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[8][29] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[8][29] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[31][29] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[31][29] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[7][29] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[7][29] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[24][29] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[24][29] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[20][29] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[20][29] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[19][29] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[19][29] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[4][29] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[4][29] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[23][29] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[23][29] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[29][29] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[29][29] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[10][29] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[10][29] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[26][29] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[26][29] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[25][29] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[25][29] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[21][29] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[21][29] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[13][29] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[13][29] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[18][29] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[18][29] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[30][29] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[30][29] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[17][29] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[17][29] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[12][29] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[12][29] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[15][29] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[15][29] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[16][29] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[16][29] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[22][29] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[22][29] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[5][29] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[5][29] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[9][29] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[9][29] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[1][29] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[1][29] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[6][29] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[6][29] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[14][29] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[14][29] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[27][29] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[27][29] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[11][29] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[11][29] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[3][29] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[3][29] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[2][29] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[2][29] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[15][28] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[15][28] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[26][28] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[26][28] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[22][28] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[22][28] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[5][28] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[5][28] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[12][28] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[12][28] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[28][28] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[28][28] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[14][28] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[14][28] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[17][28] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[17][28] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[2][28] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[2][28] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[9][28] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[9][28] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[29][28] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[29][28] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[13][28] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[13][28] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[25][28] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[25][28] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[4][28] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[4][28] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[20][28] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[20][28] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[1][28] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[1][28] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[23][28] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[23][28] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[10][28] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[10][28] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[21][28] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[21][28] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[6][28] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[6][28] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[30][28] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[30][28] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[8][28] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[8][28] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[24][28] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[24][28] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[16][28] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[16][28] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[3][28] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[3][28] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[11][28] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[11][28] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[31][28] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[31][28] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[27][28] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[27][28] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[7][28] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[7][28] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[19][28] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[19][28] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[18][28] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[18][28] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[29][27] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[29][27] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[2][27] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[2][27] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[8][27] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[8][27] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[25][27] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[25][27] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[9][27] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[9][27] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[7][27] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[7][27] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[11][27] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[11][27] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[16][27] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[16][27] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[10][27] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[10][27] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[6][27] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[6][27] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[1][27] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[1][27] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[30][27] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[30][27] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[22][27] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[22][27] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[5][27] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[5][27] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[28][27] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[28][27] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[4][27] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[4][27] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[12][27] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[12][27] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[19][27] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[19][27] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[21][27] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[21][27] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[24][27] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[24][27] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[20][27] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[20][27] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[18][27] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[18][27] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[26][27] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[26][27] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[23][27] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[23][27] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[3][27] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[3][27] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[13][27] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[13][27] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[17][27] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[17][27] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[15][27] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[15][27] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[14][27] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[14][27] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[27][27] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[27][27] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[31][27] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[31][27] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[18][26] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[18][26] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[22][26] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[22][26] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[1][26] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[1][26] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[29][26] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[29][26] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[2][26] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[2][26] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[9][26] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[9][26] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[7][26] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[7][26] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[11][26] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[11][26] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[25][26] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[25][26] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[27][26] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[27][26] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[16][26] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[16][26] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[31][26] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[31][26] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[6][26] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[6][26] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[5][26] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[5][26] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[28][26] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[28][26] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[4][26] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[4][26] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[12][26] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[12][26] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[19][26] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[19][26] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[21][26] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[21][26] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[24][26] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[24][26] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[20][26] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[20][26] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[26][26] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[26][26] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[30][26] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[30][26] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[8][26] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[8][26] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[23][26] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[23][26] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[13][26] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[13][26] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[17][26] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[17][26] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[15][26] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[15][26] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[14][26] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[14][26] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[10][26] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[10][26] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[3][26] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[3][26] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[17][25] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[17][25] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[21][25] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[21][25] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[6][25] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[6][25] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[8][25] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[8][25] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[20][25] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[20][25] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[12][25] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[12][25] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[5][25] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[5][25] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[11][25] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[11][25] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[10][25] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[10][25] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[2][25] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[2][25] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[13][25] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[13][25] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[30][25] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[30][25] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[22][25] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[22][25] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[1][25] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[1][25] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[28][25] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[28][25] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[18][25] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[18][25] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[26][25] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[26][25] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[24][25] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[24][25] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[4][25] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[4][25] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[15][25] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[15][25] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[16][25] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[16][25] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[19][25] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[19][25] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[25][25] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[25][25] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[7][25] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[7][25] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[14][25] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[14][25] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[9][25] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[9][25] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[29][25] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[29][25] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[23][25] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[23][25] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[3][25] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[3][25] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[27][25] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[27][25] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[31][25] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[31][25] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[17][24] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[17][24] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[21][24] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[21][24] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[6][24] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[6][24] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[8][24] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[8][24] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[20][24] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[20][24] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[12][24] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[12][24] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[5][24] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[5][24] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[11][24] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[11][24] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[10][24] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[10][24] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[2][24] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[2][24] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[13][24] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[13][24] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[30][24] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[30][24] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[22][24] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[22][24] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[1][24] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[1][24] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[28][24] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[28][24] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[18][24] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[18][24] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[26][24] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[26][24] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[24][24] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[24][24] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[4][24] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[4][24] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[15][24] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[15][24] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[25][24] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[25][24] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[19][24] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[19][24] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[16][24] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[16][24] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[7][24] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[7][24] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[14][24] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[14][24] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[9][24] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[9][24] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[29][24] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[29][24] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[23][24] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[23][24] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[3][24] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[3][24] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[27][24] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[27][24] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[31][24] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[31][24] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[9][23] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[9][23] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[28][23] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[28][23] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[18][23] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[18][23] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[22][23] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[22][23] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[1][23] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[1][23] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[21][23] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[21][23] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[20][23] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[20][23] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[19][23] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[19][23] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[26][23] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[26][23] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[23][23] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[23][23] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[29][23] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[29][23] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[3][23] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[3][23] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[30][23] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[30][23] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[31][23] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[31][23] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[8][23] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[8][23] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[17][23] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[17][23] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[24][23] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[24][23] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[15][23] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[15][23] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[14][23] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[14][23] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[16][23] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[16][23] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[7][23] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[7][23] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[6][23] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[6][23] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[25][23] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[25][23] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[27][23] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[27][23] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[11][23] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[11][23] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[13][23] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[13][23] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[5][23] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[5][23] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[4][23] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[4][23] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[12][23] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[12][23] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[2][23] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[2][23] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[10][23] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[10][23] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[17][22] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[17][22] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[21][22] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[21][22] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[6][22] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[6][22] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[11][22] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[11][22] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[20][22] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[20][22] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[12][22] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[12][22] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[10][22] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[10][22] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[5][22] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[5][22] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[31][22] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[31][22] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[2][22] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[2][22] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[22][22] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[22][22] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[26][22] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[26][22] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[13][22] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[13][22] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[1][22] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[1][22] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[28][22] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[28][22] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[18][22] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[18][22] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[30][22] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[30][22] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[24][22] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[24][22] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[4][22] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[4][22] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[15][22] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[15][22] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[16][22] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[16][22] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[19][22] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[19][22] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[25][22] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[25][22] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[7][22] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[7][22] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[14][22] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[14][22] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[9][22] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[9][22] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[29][22] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[29][22] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[8][22] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[8][22] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[23][22] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[23][22] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[27][22] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[27][22] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[3][22] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[3][22] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[17][21] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[17][21] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[21][21] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[21][21] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[6][21] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[6][21] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[8][21] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[8][21] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[20][21] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[20][21] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[12][21] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[12][21] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[5][21] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[5][21] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[11][21] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[11][21] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[10][21] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[10][21] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[2][21] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[2][21] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[13][21] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[13][21] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[30][21] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[30][21] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[22][21] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[22][21] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[1][21] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[1][21] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[28][21] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[28][21] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[18][21] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[18][21] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[26][21] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[26][21] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[24][21] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[24][21] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[4][21] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[4][21] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[15][21] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[15][21] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[16][21] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[16][21] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[19][21] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[19][21] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[25][21] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[25][21] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[7][21] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[7][21] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[14][21] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[14][21] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[9][21] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[9][21] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[29][21] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[29][21] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[23][21] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[23][21] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[3][21] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[3][21] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[27][21] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[27][21] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[31][21] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[31][21] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[17][20] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[17][20] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[21][20] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[21][20] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[10][20] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[10][20] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[2][20] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[2][20] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[20][20] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[20][20] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[12][20] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[12][20] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[15][20] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[15][20] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[8][20] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[8][20] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[11][20] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[11][20] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[5][20] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[5][20] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[13][20] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[13][20] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[30][20] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[30][20] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[22][20] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[22][20] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[1][20] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[1][20] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[28][20] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[28][20] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[18][20] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[18][20] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[26][20] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[26][20] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[24][20] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[24][20] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[4][20] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[4][20] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[6][20] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[6][20] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[25][20] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[25][20] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[19][20] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[19][20] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[16][20] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[16][20] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[7][20] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[7][20] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[14][20] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[14][20] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[9][20] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[9][20] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[29][20] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[29][20] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[23][20] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[23][20] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[3][20] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[3][20] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[27][20] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[27][20] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[31][20] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[31][20] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[17][19] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[17][19] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[21][19] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[21][19] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[2][19] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[2][19] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[31][19] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[31][19] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[20][19] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[20][19] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[12][19] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[12][19] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[15][19] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[15][19] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[11][19] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[11][19] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[27][19] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[27][19] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[24][19] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[24][19] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[22][19] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[22][19] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[26][19] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[26][19] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[13][19] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[13][19] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[1][19] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[1][19] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[28][19] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[28][19] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[18][19] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[18][19] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[30][19] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[30][19] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[4][19] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[4][19] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[5][19] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[5][19] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[6][19] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[6][19] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[25][19] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[25][19] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[19][19] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[19][19] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[16][19] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[16][19] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[9][19] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[9][19] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[29][19] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[29][19] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[8][19] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[8][19] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[23][19] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[23][19] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[7][19] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[7][19] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[14][19] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[14][19] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[10][19] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[10][19] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[3][19] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[3][19] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[24][18] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[24][18] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[28][18] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[28][18] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[11][18] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[11][18] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[16][18] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[16][18] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[9][18] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[9][18] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[7][18] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[7][18] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[27][18] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[27][18] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[25][18] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[25][18] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[31][18] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[31][18] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[6][18] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[6][18] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[22][18] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[22][18] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[26][18] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[26][18] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[1][18] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[1][18] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[29][18] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[29][18] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[2][18] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[2][18] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[18][18] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[18][18] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[30][18] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[30][18] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[4][18] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[4][18] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[12][18] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[12][18] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[19][18] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[19][18] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[21][18] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[21][18] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[5][18] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[5][18] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[20][18] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[20][18] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[8][18] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[8][18] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[23][18] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[23][18] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[13][18] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[13][18] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[17][18] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[17][18] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[15][18] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[15][18] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[14][18] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[14][18] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[10][18] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[10][18] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[3][18] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[3][18] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[17][17] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[17][17] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[21][17] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[21][17] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[2][17] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[2][17] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[31][17] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[31][17] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[20][17] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[20][17] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[12][17] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[12][17] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[15][17] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[15][17] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[11][17] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[11][17] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[10][17] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[10][17] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[24][17] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[24][17] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[22][17] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[22][17] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[26][17] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[26][17] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[13][17] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[13][17] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[1][17] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[1][17] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[28][17] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[28][17] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[18][17] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[18][17] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[30][17] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[30][17] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[4][17] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[4][17] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[5][17] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[5][17] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[6][17] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[6][17] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[25][17] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[25][17] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[19][17] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[19][17] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[16][17] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[16][17] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[7][17] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[7][17] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[14][17] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[14][17] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[9][17] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[9][17] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[29][17] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[29][17] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[8][17] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[8][17] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[23][17] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[23][17] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[27][17] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[27][17] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[3][17] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[3][17] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[29][16] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[29][16] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[2][16] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[2][16] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[11][16] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[11][16] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[25][16] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[25][16] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[9][16] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[9][16] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[7][16] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[7][16] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[10][16] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[10][16] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[16][16] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[16][16] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[31][16] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[31][16] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[6][16] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[6][16] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[18][16] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[18][16] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[22][16] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[22][16] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[1][16] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[1][16] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[5][16] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[5][16] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[28][16] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[28][16] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[4][16] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[4][16] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[12][16] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[12][16] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[19][16] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[19][16] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[21][16] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[21][16] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[24][16] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[24][16] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[20][16] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[20][16] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[26][16] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[26][16] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[30][16] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[30][16] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[8][16] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[8][16] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[23][16] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[23][16] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[13][16] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[13][16] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[17][16] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[17][16] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[15][16] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[15][16] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[14][16] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[14][16] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[27][16] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[27][16] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[3][16] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[3][16] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[17][15] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[17][15] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[21][15] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[21][15] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[10][15] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[10][15] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[2][15] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[2][15] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[20][15] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[20][15] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[12][15] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[12][15] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[15][15] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[15][15] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[8][15] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[8][15] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[11][15] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[11][15] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[24][15] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[24][15] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[13][15] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[13][15] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[30][15] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[30][15] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[22][15] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[22][15] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[1][15] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[1][15] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[28][15] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[28][15] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[18][15] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[18][15] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[26][15] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[26][15] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[4][15] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[4][15] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[5][15] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[5][15] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[6][15] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[6][15] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[16][15] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[16][15] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[19][15] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[19][15] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[25][15] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[25][15] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[7][15] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[7][15] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[14][15] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[14][15] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[9][15] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[9][15] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[29][15] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[29][15] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[23][15] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[23][15] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[3][15] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[3][15] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[27][15] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[27][15] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[31][15] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[31][15] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[28][14] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[28][14] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[5][14] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[5][14] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[18][14] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[18][14] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[10][14] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[10][14] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[8][14] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[8][14] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[9][14] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[9][14] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[29][14] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[29][14] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[21][14] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[21][14] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[14][14] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[14][14] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[16][14] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[16][14] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[3][14] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[3][14] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[17][14] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[17][14] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[31][14] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[31][14] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[15][14] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[15][14] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[23][14] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[23][14] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[26][14] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[26][14] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[30][14] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[30][14] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[20][14] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[20][14] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[4][14] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[4][14] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[1][14] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[1][14] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[2][14] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[2][14] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[24][14] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[24][14] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[12][14] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[12][14] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[19][14] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[19][14] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[22][14] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[22][14] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[13][14] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[13][14] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[25][14] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[25][14] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[6][14] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[6][14] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[7][14] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[7][14] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[27][14] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[27][14] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[11][14] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[11][14] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[28][13] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[28][13] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[4][13] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[4][13] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[10][13] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[10][13] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[26][13] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[26][13] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[8][13] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[8][13] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[9][13] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[9][13] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[29][13] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[29][13] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[6][13] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[6][13] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[1][13] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[1][13] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[5][13] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[5][13] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[3][13] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[3][13] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[16][13] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[16][13] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[31][13] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[31][13] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[15][13] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[15][13] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[23][13] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[23][13] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[18][13] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[18][13] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[30][13] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[30][13] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[24][13] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[24][13] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[12][13] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[12][13] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[22][13] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[22][13] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[21][13] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[21][13] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[20][13] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[20][13] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[17][13] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[17][13] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[13][13] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[13][13] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[25][13] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[25][13] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[19][13] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[19][13] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[2][13] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[2][13] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[7][13] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[7][13] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[14][13] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[14][13] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[27][13] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[27][13] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[11][13] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[11][13] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[28][12] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[28][12] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[17][12] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[17][12] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[10][12] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[10][12] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[26][12] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[26][12] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[8][12] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[8][12] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[9][12] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[9][12] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[29][12] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[29][12] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[6][12] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[6][12] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[1][12] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[1][12] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[16][12] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[16][12] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[3][12] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[3][12] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[5][12] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[5][12] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[31][12] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[31][12] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[15][12] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[15][12] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[23][12] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[23][12] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[18][12] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[18][12] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[30][12] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[30][12] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[20][12] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[20][12] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[4][12] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[4][12] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[22][12] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[22][12] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[21][12] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[21][12] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[24][12] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[24][12] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[12][12] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[12][12] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[13][12] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[13][12] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[25][12] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[25][12] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[19][12] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[19][12] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[2][12] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[2][12] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[7][12] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[7][12] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[14][12] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[14][12] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[27][12] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[27][12] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[11][12] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[11][12] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[28][11] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[28][11] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[17][11] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[17][11] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[10][11] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[10][11] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[26][11] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[26][11] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[8][11] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[8][11] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[9][11] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[9][11] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[29][11] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[29][11] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[6][11] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[6][11] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[1][11] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[1][11] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[5][11] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[5][11] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[3][11] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[3][11] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[16][11] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[16][11] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[31][11] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[31][11] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[15][11] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[15][11] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[23][11] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[23][11] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[18][11] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[18][11] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[30][11] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[30][11] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[20][11] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[20][11] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[4][11] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[4][11] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[22][11] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[22][11] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[21][11] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[21][11] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[24][11] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[24][11] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[12][11] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[12][11] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[13][11] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[13][11] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[25][11] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[25][11] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[19][11] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[19][11] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[2][11] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[2][11] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[7][11] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[7][11] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[14][11] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[14][11] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[27][11] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[27][11] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[11][11] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[11][11] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[28][10] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[28][10] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[8][10] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[8][10] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[31][10] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[31][10] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[7][10] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[7][10] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[24][10] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[24][10] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[20][10] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[20][10] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[4][10] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[4][10] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[23][10] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[23][10] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[27][10] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[27][10] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[29][10] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[29][10] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[10][10] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[10][10] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[30][10] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[30][10] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[25][10] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[25][10] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[21][10] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[21][10] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[13][10] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[13][10] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[18][10] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[18][10] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[26][10] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[26][10] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[17][10] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[17][10] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[12][10] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[12][10] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[15][10] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[15][10] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[5][10] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[5][10] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[22][10] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[22][10] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[16][10] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[16][10] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[9][10] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[9][10] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[1][10] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[1][10] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[6][10] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[6][10] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[14][10] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[14][10] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[19][10] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[19][10] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[3][10] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[3][10] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[11][10] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[11][10] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[2][10] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[2][10] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[13][9] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[13][9] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[21][9] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[21][9] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[29][9] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[29][9] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[23][9] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[23][9] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[24][9] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[24][9] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[20][9] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[20][9] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[7][9] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[7][9] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[3][9] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[3][9] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[31][9] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[31][9] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[4][9] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[4][9] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[10][9] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[10][9] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[26][9] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[26][9] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[25][9] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[25][9] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[8][9] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[8][9] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[28][9] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[28][9] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[18][9] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[18][9] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[30][9] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[30][9] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[17][9] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[17][9] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[12][9] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[12][9] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[15][9] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[15][9] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[5][9] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[5][9] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[22][9] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[22][9] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[16][9] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[16][9] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[9][9] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[9][9] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[1][9] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[1][9] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[6][9] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[6][9] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[14][9] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[14][9] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[19][9] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[19][9] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[2][9] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[2][9] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[11][9] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[11][9] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[27][9] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[27][9] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[13][8] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[13][8] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[21][8] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[21][8] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[29][8] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[29][8] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[23][8] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[23][8] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[24][8] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[24][8] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[20][8] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[20][8] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[7][8] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[7][8] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[3][8] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[3][8] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[31][8] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[31][8] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[4][8] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[4][8] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[10][8] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[10][8] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[26][8] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[26][8] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[25][8] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[25][8] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[8][8] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[8][8] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[28][8] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[28][8] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[18][8] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[18][8] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[30][8] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[30][8] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[17][8] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[17][8] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[12][8] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[12][8] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[15][8] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[15][8] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[5][8] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[5][8] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[22][8] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[22][8] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[16][8] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[16][8] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[9][8] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[9][8] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[1][8] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[1][8] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[6][8] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[6][8] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[14][8] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[14][8] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[19][8] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[19][8] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[2][8] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[2][8] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[11][8] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[11][8] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[27][8] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[27][8] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[13][7] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[13][7] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[21][7] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[21][7] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[18][7] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[18][7] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[10][7] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[10][7] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[25][7] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[25][7] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[28][7] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[28][7] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[8][7] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[8][7] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[24][7] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[24][7] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[20][7] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[20][7] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[31][7] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[31][7] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[7][7] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[7][7] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[17][7] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[17][7] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[11][7] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[11][7] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[27][7] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[27][7] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[29][7] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[29][7] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[26][7] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[26][7] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[30][7] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[30][7] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[4][7] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[4][7] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[12][7] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[12][7] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[15][7] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[15][7] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[16][7] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[16][7] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[22][7] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[22][7] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[5][7] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[5][7] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[19][7] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[19][7] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[3][7] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[3][7] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[9][7] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[9][7] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[1][7] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[1][7] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[6][7] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[6][7] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[14][7] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[14][7] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[2][7] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[2][7] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[23][7] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[23][7] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[28][6] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[28][6] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[17][6] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[17][6] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[18][6] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[18][6] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[10][6] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[10][6] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[8][6] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[8][6] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[9][6] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[9][6] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[29][6] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[29][6] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[6][6] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[6][6] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[1][6] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[1][6] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[15][6] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[15][6] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[27][6] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[27][6] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[11][6] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[11][6] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[16][6] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[16][6] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[5][6] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[5][6] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[31][6] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[31][6] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[26][6] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[26][6] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[30][6] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[30][6] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[20][6] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[20][6] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[4][6] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[4][6] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[22][6] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[22][6] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[21][6] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[21][6] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[24][6] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[24][6] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[12][6] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[12][6] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[13][6] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[13][6] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[25][6] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[25][6] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[7][6] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[7][6] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[14][6] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[14][6] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[19][6] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[19][6] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[3][6] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[3][6] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[2][6] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[2][6] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[23][6] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[23][6] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[28][5] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[28][5] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[4][5] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[4][5] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[10][5] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[10][5] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[26][5] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[26][5] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[8][5] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[8][5] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[9][5] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[9][5] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[29][5] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[29][5] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[6][5] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[6][5] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[1][5] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[1][5] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[16][5] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[16][5] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[3][5] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[3][5] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[5][5] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[5][5] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[31][5] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[31][5] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[15][5] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[15][5] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[23][5] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[23][5] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[18][5] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[18][5] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[30][5] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[30][5] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[24][5] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[24][5] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[12][5] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[12][5] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[22][5] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[22][5] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[21][5] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[21][5] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[20][5] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[20][5] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[17][5] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[17][5] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[13][5] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[13][5] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[25][5] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[25][5] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[19][5] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[19][5] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[2][5] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[2][5] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[7][5] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[7][5] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[14][5] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[14][5] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[27][5] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[27][5] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[11][5] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[11][5] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[10][4] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[10][4] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[21][4] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[21][4] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[9][4] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[9][4] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[1][4] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[1][4] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[18][4] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[18][4] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[8][4] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[8][4] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[22][4] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[22][4] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[23][4] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[23][4] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[28][4] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[28][4] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[20][4] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[20][4] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[19][4] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[19][4] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[13][4] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[13][4] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[26][4] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[26][4] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[3][4] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[3][4] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[30][4] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[30][4] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[31][4] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[31][4] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[24][4] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[24][4] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[12][4] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[12][4] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[27][4] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[27][4] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[11][4] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[11][4] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[17][4] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[17][4] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[7][4] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[7][4] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[14][4] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[14][4] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[15][4] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[15][4] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[16][4] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[16][4] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[4][4] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[4][4] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[25][4] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[25][4] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[29][4] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[29][4] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[2][4] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[2][4] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[6][4] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[6][4] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[5][4] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[5][4] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[28][3] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[28][3] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[17][3] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[17][3] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[10][3] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[10][3] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[26][3] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[26][3] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[8][3] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[8][3] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[9][3] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[9][3] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[29][3] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[29][3] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[6][3] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[6][3] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[1][3] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[1][3] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[16][3] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[16][3] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[3][3] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[3][3] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[5][3] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[5][3] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[31][3] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[31][3] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[15][3] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[15][3] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[23][3] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[23][3] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[18][3] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[18][3] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[30][3] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[30][3] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[20][3] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[20][3] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[4][3] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[4][3] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[22][3] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[22][3] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[21][3] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[21][3] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[24][3] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[24][3] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[12][3] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[12][3] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[13][3] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[13][3] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[25][3] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[25][3] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[19][3] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[19][3] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[2][3] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[2][3] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[7][3] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[7][3] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[14][3] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[14][3] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[27][3] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[27][3] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[11][3] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[11][3] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[28][2] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[28][2] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[4][2] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[4][2] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[16][2] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[16][2] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[31][2] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[31][2] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[6][2] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[6][2] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[1][2] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[1][2] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[15][2] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[15][2] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[27][2] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[27][2] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[11][2] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[11][2] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[5][2] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[5][2] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[10][2] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[10][2] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[30][2] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[30][2] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[8][2] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[8][2] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[9][2] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[9][2] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[29][2] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[29][2] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[18][2] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[18][2] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[26][2] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[26][2] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[24][2] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[24][2] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[12][2] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[12][2] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[22][2] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[22][2] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[21][2] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[21][2] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[17][2] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[17][2] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[20][2] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[20][2] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[13][2] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[13][2] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[25][2] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[25][2] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[7][2] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[7][2] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[14][2] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[14][2] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[19][2] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[19][2] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[3][2] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[3][2] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[23][2] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[23][2] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[2][2] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[2][2] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[13][1] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[13][1] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[21][1] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[21][1] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[29][1] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[29][1] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[23][1] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[23][1] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[24][1] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[24][1] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[20][1] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[20][1] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[7][1] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[7][1] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[3][1] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[3][1] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[31][1] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[31][1] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[4][1] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[4][1] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[10][1] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[10][1] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[26][1] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[26][1] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[25][1] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[25][1] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[8][1] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[8][1] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[28][1] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[28][1] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[18][1] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[18][1] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[30][1] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[30][1] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[17][1] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[17][1] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[12][1] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[12][1] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[15][1] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[15][1] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[5][1] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[5][1] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[22][1] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[22][1] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[16][1] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[16][1] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[9][1] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[9][1] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[1][1] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[1][1] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[6][1] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[6][1] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[14][1] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[14][1] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[19][1] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[19][1] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[2][1] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[2][1] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[11][1] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[11][1] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[27][1] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[27][1] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[13][0] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[13][0] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[21][0] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[21][0] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[10][0] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[10][0] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[26][0] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[26][0] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[25][0] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[25][0] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[28][0] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[28][0] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[8][0] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[8][0] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[24][0] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[24][0] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[20][0] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[20][0] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[7][0] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[7][0] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[3][0] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[3][0] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[17][0] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[17][0] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[31][0] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[31][0] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[29][0] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[29][0] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[23][0] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[23][0] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[18][0] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[18][0] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[30][0] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[30][0] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[4][0] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[4][0] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[12][0] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[12][0] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[15][0] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[15][0] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[16][0] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[16][0] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[22][0] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[22][0] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[5][0] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[5][0] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[19][0] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[19][0] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[2][0] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[2][0] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[9][0] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[9][0] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[1][0] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[1][0] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[6][0] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[6][0] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[14][0] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[14][0] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[27][0] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[27][0] /CK"; + 0, DI.CLK, "/theRegisters/\registers_reg[11][0] /CK"; + 1, DI.CLK, "/theRegisters/\registers_reg[11][0] /CK"; + 0, DI.SCAN, "/SO_2"; + 0, EQ, "/theRegisters/ts_lockup_latchn_clkc2_intno1050_i/Q"; + 1, DI.SCAN, "/SO_2"; + 1, EQ, "/theRegisters/ts_lockup_latchn_clkc2_intno1050_i/Q"; + 0, DI.SCAN, "/theRegisters/ts_lockup_latchn_clkc2_intno1050_i/D"; + 1, DI.SCAN, "/theRegisters/ts_lockup_latchn_clkc2_intno1050_i/D"; + 0, DI.SCAN, "/SO_4"; + 0, EQ, "/theRegisters/ts_lockup_latchn_clkc4_intno1051_i/Q"; + 1, DI.SCAN, "/SO_4"; + 1, EQ, "/theRegisters/ts_lockup_latchn_clkc4_intno1051_i/Q"; + 0, DI.SCAN, "/theRegisters/ts_lockup_latchn_clkc4_intno1051_i/D"; + 1, DI.SCAN, "/theRegisters/ts_lockup_latchn_clkc4_intno1051_i/D"; + 0, DI.SCAN, "/SO_3"; + 0, EQ, "/theRegisters/ts_lockup_latchn_clkc3_intno1053_i/Q"; + 1, DI.SCAN, "/SO_3"; + 1, EQ, "/theRegisters/ts_lockup_latchn_clkc3_intno1053_i/Q"; + 0, DI.SCAN, "/theRegisters/ts_lockup_latchn_clkc3_intno1053_i/D"; + 1, DI.SCAN, "/theRegisters/ts_lockup_latchn_clkc3_intno1053_i/D"; + 0, DI.SCAN, "/SO_1"; + 0, EQ, "/theRegisters/ts_lockup_latchn_clkc1_intno1054_i/Q"; + 1, DI.SCAN, "/SO_1"; + 1, EQ, "/theRegisters/ts_lockup_latchn_clkc1_intno1054_i/Q"; + 0, DI.SCAN, "/theRegisters/ts_lockup_latchn_clkc1_intno1054_i/D"; + 1, DI.SCAN, "/theRegisters/ts_lockup_latchn_clkc1_intno1054_i/D"; + 0, AU.BB, "/led[7]"; + 1, AU.BB, "/led[7]"; + 0, AU.BB, "/led[6]"; + 1, AU.BB, "/led[6]"; + 0, AU.BB, "/led[5]"; + 1, AU.BB, "/led[5]"; + 0, AU.BB, "/led[4]"; + 1, AU.BB, "/led[4]"; + 0, AU.BB, "/led[3]"; + 1, AU.BB, "/led[3]"; + 0, AU.BB, "/led[2]"; + 1, AU.BB, "/led[2]"; + 0, AU.BB, "/led[1]"; + 1, AU.BB, "/led[1]"; + 0, AU.BB, "/led[0]"; + 1, AU.BB, "/led[0]"; + } + } + } +} diff --git a/oasys.tessent.00/tsdb_outdir/logic_test_cores/cpu_Scan_0.logic_test_core/cpu.atpg_mode_unwrapped/cpu_unwrapped_stuck.faults.gz b/oasys.tessent.00/tsdb_outdir/logic_test_cores/cpu_Scan_0.logic_test_core/cpu.atpg_mode_unwrapped/cpu_unwrapped_stuck.faults.gz new file mode 100644 index 0000000..bf78bf6 Binary files /dev/null and b/oasys.tessent.00/tsdb_outdir/logic_test_cores/cpu_Scan_0.logic_test_core/cpu.atpg_mode_unwrapped/cpu_unwrapped_stuck.faults.gz differ diff --git a/oasys.tessent.00/tsdb_outdir/logic_test_cores/cpu_Scan_0.logic_test_core/cpu.atpg_mode_unwrapped/cpu_unwrapped_stuck.patdb b/oasys.tessent.00/tsdb_outdir/logic_test_cores/cpu_Scan_0.logic_test_core/cpu.atpg_mode_unwrapped/cpu_unwrapped_stuck.patdb new file mode 100644 index 0000000..27d254d Binary files /dev/null and b/oasys.tessent.00/tsdb_outdir/logic_test_cores/cpu_Scan_0.logic_test_core/cpu.atpg_mode_unwrapped/cpu_unwrapped_stuck.patdb differ diff --git a/oasys.tessent.01/Scan_0/cpu.scandef b/oasys.tessent.01/Scan_0/cpu.scandef new file mode 100644 index 0000000..aa5447b --- /dev/null +++ b/oasys.tessent.01/Scan_0/cpu.scandef @@ -0,0 +1,1071 @@ +# +# DESC: ScanDEF written by Tessent Shell on Fri May 29 09:09:59 CEST 2026 +# + +VERSION 5.7 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN cpu ; +UNITS DISTANCE MICRONS 1000 ; + +SCANCHAINS 4 ; + +- scan_segment_0 + + START tessent_persistent_cell_buf_extsi1225_i Z + + FLOATING + thePC_CurrentPC_reg\[30\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[29\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[28\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[27\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[26\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[25\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[24\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[23\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[22\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[21\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[20\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[19\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[18\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[17\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[16\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[15\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[14\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[13\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[12\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[11\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[10\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[9\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[8\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[7\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[6\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[5\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[4\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[3\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[2\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[31\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[1\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[0\] ( IN SI ) ( OUT Q ) + + STOP theRegisters/ts_lockup_latchn_clkc1_intno1054_i D + # Partition constraints - clock domain: clk_25mhz(+); cluster: scanChain_1; chain type: core; scan mode(s): unwrapped + + PARTITION partition_1 MAXBITS 256 ; + + +- scan_segment_1 + + START theRegisters/tessent_persistent_cell_buf_extsi1226_i Z + + FLOATING + theRegisters/registers_reg\[1\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[0\] ( IN SI ) ( OUT Q ) + + STOP theRegisters/ts_lockup_latchn_clkc2_intno1050_i D + # Partition constraints - clock domain: clk_25mhz(+); cluster: scanChain_2; chain type: core; scan mode(s): unwrapped + + PARTITION partition_2 MAXBITS 256 ; + + +- scan_segment_2 + + START theRegisters/tessent_persistent_cell_buf_extsi1227_i Z + + FLOATING + theRegisters/registers_reg\[28\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[0\] ( IN SI ) ( OUT Q ) + + STOP theRegisters/ts_lockup_latchn_clkc3_intno1053_i D + # Partition constraints - clock domain: clk_25mhz(+); cluster: scanChain_3; chain type: core; scan mode(s): unwrapped + + PARTITION partition_3 MAXBITS 256 ; + + +- scan_segment_3 + + START theRegisters/tessent_persistent_cell_buf_extsi1228_i Z + + FLOATING + theRegisters/registers_reg\[4\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[0\] ( IN SI ) ( OUT Q ) + + STOP theRegisters/ts_lockup_latchn_clkc4_intno1051_i D + # Partition constraints - clock domain: clk_25mhz(+); cluster: scanChain_4; chain type: core; scan mode(s): unwrapped + + PARTITION partition_4 MAXBITS 256 ; + + +END SCANCHAINS + +END DESIGN diff --git a/oasys.tessent.01/Scan_0/oasys.sdc b/oasys.tessent.01/Scan_0/oasys.sdc new file mode 100644 index 0000000..3b3613b --- /dev/null +++ b/oasys.tessent.01/Scan_0/oasys.sdc @@ -0,0 +1,62 @@ +# +# Created by +# ../bin/Linux-x86_64-O/oasysGui 22.2-p002 on Fri May 29 09:09:53 2026 +# (C) Mentor Graphics Corporation +# +set_units -time ns -capacitance pf -resistance kohm -power nW -voltage V -current uA +create_clock -period 40 -waveform {0 20} -name clk_25mhz [get_ports clk_25mhz] +set_clock_transition 0.1 [get_clocks clk_25mhz] +set_clock_uncertainty -setup 0.5 [get_clocks clk_25mhz] +set_clock_uncertainty -hold 0.2 [get_clocks clk_25mhz] +set_false_path -from [get_ports {btn[0]}] +group_path -name I2R -from [list [get_ports clk_25mhz] [get_ports {btn[0]}] [get_ports {btn[1]}] [get_ports {btn[2]}] [get_ports {btn[3]}] [get_ports {btn[4]}] [get_ports {btn[5]}] [get_ports {btn[6]}]] +group_path -name I2O -from [list [get_ports clk_25mhz] [get_ports {btn[0]}] [get_ports {btn[1]}] [get_ports {btn[2]}] [get_ports {btn[3]}] [get_ports {btn[4]}] [get_ports {btn[5]}] [get_ports {btn[6]}]] -to [list [get_ports {led[0]}] [get_ports {led[1]}] [get_ports {led[2]}] [get_ports {led[3]}] [get_ports {led[4]}] [get_ports {led[5]}] [get_ports {led[6]}] [get_ports {led[7]}]] +group_path -name R2O -to [list [get_ports {led[0]}] [get_ports {led[1]}] [get_ports {led[2]}] [get_ports {led[3]}] [get_ports {led[4]}] [get_ports {led[5]}] [get_ports {led[6]}] [get_ports {led[7]}]] +set_input_delay 2 -clock clk_25mhz -max [get_ports {btn[6]}] +set_input_delay 2 -clock clk_25mhz -max [get_ports {btn[5]}] +set_input_delay 2 -clock clk_25mhz -max [get_ports {btn[4]}] +set_input_delay 2 -clock clk_25mhz -max [get_ports {btn[3]}] +set_input_delay 2 -clock clk_25mhz -max [get_ports {btn[2]}] +set_input_delay 2 -clock clk_25mhz -max [get_ports {btn[1]}] +set_input_delay 2 -clock clk_25mhz -max [get_ports {btn[0]}] +set_input_delay 0.5 -clock clk_25mhz -min [get_ports {btn[6]}] +set_input_delay 0.5 -clock clk_25mhz -min [get_ports {btn[5]}] +set_input_delay 0.5 -clock clk_25mhz -min [get_ports {btn[4]}] +set_input_delay 0.5 -clock clk_25mhz -min [get_ports {btn[3]}] +set_input_delay 0.5 -clock clk_25mhz -min [get_ports {btn[2]}] +set_input_delay 0.5 -clock clk_25mhz -min [get_ports {btn[1]}] +set_input_delay 0.5 -clock clk_25mhz -min [get_ports {btn[0]}] +set_output_delay 2 -clock clk_25mhz -max [get_ports {led[7]}] +set_output_delay 2 -clock clk_25mhz -max [get_ports {led[6]}] +set_output_delay 2 -clock clk_25mhz -max [get_ports {led[5]}] +set_output_delay 2 -clock clk_25mhz -max [get_ports {led[4]}] +set_output_delay 2 -clock clk_25mhz -max [get_ports {led[3]}] +set_output_delay 2 -clock clk_25mhz -max [get_ports {led[2]}] +set_output_delay 2 -clock clk_25mhz -max [get_ports {led[1]}] +set_output_delay 2 -clock clk_25mhz -max [get_ports {led[0]}] +set_output_delay 0.5 -clock clk_25mhz -min [get_ports {led[7]}] +set_output_delay 0.5 -clock clk_25mhz -min [get_ports {led[6]}] +set_output_delay 0.5 -clock clk_25mhz -min [get_ports {led[5]}] +set_output_delay 0.5 -clock clk_25mhz -min [get_ports {led[4]}] +set_output_delay 0.5 -clock clk_25mhz -min [get_ports {led[3]}] +set_output_delay 0.5 -clock clk_25mhz -min [get_ports {led[2]}] +set_output_delay 0.5 -clock clk_25mhz -min [get_ports {led[1]}] +set_output_delay 0.5 -clock clk_25mhz -min [get_ports {led[0]}] +set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 [get_ports {btn[6]}] +set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 [get_ports {btn[5]}] +set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 [get_ports {btn[4]}] +set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 [get_ports {btn[3]}] +set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 [get_ports {btn[2]}] +set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 [get_ports {btn[1]}] +set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 [get_ports {btn[0]}] +set_load 0.05 [get_ports {led[7]}] +set_load 0.05 [get_ports {led[6]}] +set_load 0.05 [get_ports {led[5]}] +set_load 0.05 [get_ports {led[4]}] +set_load 0.05 [get_ports {led[3]}] +set_load 0.05 [get_ports {led[2]}] +set_load 0.05 [get_ports {led[1]}] +set_load 0.05 [get_ports {led[0]}] +set_operating_conditions -library [get_libs {NangateOpenCellLibrary_45nm_LVT_0p85}] -max slow_0p85V -min slow_0p85V +set_max_fanout 20.000000 [current_design] +set_max_transition 0.500000 [current_design] diff --git a/oasys.tessent.01/Scan_0/oasys_netlist.v b/oasys.tessent.01/Scan_0/oasys_netlist.v new file mode 100644 index 0000000..525f10f --- /dev/null +++ b/oasys.tessent.01/Scan_0/oasys_netlist.v @@ -0,0 +1,10896 @@ +/* + * Created by + ../bin/Linux-x86_64-O/oasysGui 22.2-p002 on Fri May 29 09:09:52 2026 + * (C) Mentor Graphics Corporation + */ +/* CheckSum: 514746972 */ + +module reg_file(Rs1, Rs2, Rd, RRs1, RRs2, WRd, WrReg, reset, clk, dftIn); + input [4:0]Rs1; + input [4:0]Rs2; + input [4:0]Rd; + output [31:0]RRs1; + output [31:0]RRs2; + input [31:0]WRd; + input WrReg; + input reset; + input clk; + input dftIn; + + wire [31:0]registers_1__ap; + wire n_0_0; + wire [31:0]registers_2__ap; + wire n_0_32; + wire [31:0]registers_3__ap; + wire n_0_33; + wire [31:0]registers_4__ap; + wire n_0_34; + wire [31:0]registers_5__ap; + wire n_0_35; + wire [31:0]registers_6__ap; + wire n_0_36; + wire [31:0]registers_7__ap; + wire n_0_37; + wire [31:0]registers_8__ap; + wire n_0_38; + wire [31:0]registers_9__ap; + wire n_0_39; + wire [31:0]registers_10__ap; + wire n_0_40; + wire [31:0]registers_11__ap; + wire n_0_41; + wire [31:0]registers_12__ap; + wire n_0_42; + wire [31:0]registers_13__ap; + wire n_0_43; + wire [31:0]registers_14__ap; + wire n_0_44; + wire [31:0]registers_15__ap; + wire n_0_45; + wire [31:0]registers_16__ap; + wire n_0_46; + wire [31:0]registers_17__ap; + wire n_0_47; + wire [31:0]registers_18__ap; + wire n_0_48; + wire [31:0]registers_19__ap; + wire n_0_49; + wire [31:0]registers_20__ap; + wire n_0_50; + wire [31:0]registers_21__ap; + wire n_0_51; + wire [31:0]registers_22__ap; + wire n_0_52; + wire [31:0]registers_23__ap; + wire n_0_53; + wire [31:0]registers_24__ap; + wire n_0_54; + wire [31:0]registers_25__ap; + wire n_0_55; + wire [31:0]registers_26__ap; + wire n_0_56; + wire [31:0]registers_27__ap; + wire n_0_57; + wire [31:0]registers_28__ap; + wire n_0_58; + wire [31:0]registers_29__ap; + wire n_0_59; + wire [31:0]registers_30__ap; + wire n_0_60; + wire [31:0]registers_31__ap; + wire n_0_61; + wire [31:0]registers; + wire n_0_31; + wire n_0_30; + wire n_0_29; + wire n_0_28; + wire n_0_27; + wire n_0_26; + wire n_0_25; + wire n_0_24; + wire n_0_0_0; + wire n_0_0_1; + wire n_0_23; + wire n_0_22; + wire n_0_21; + wire n_0_20; + wire n_0_19; + wire n_0_18; + wire n_0_17; + wire n_0_16; + wire n_0_0_2; + wire n_0_0_3; + wire n_0_15; + wire n_0_14; + wire n_0_13; + wire n_0_12; + wire n_0_11; + wire n_0_10; + wire n_0_9; + wire n_0_8; + wire n_0_0_4; + wire n_0_0_5; + wire n_0_7; + wire n_0_0_6; + wire n_0_6; + wire n_0_0_7; + wire n_0_5; + wire n_0_0_8; + wire n_0_4; + wire n_0_0_9; + wire n_0_0_10; + wire n_0_3; + wire n_0_0_11; + wire n_0_2; + wire n_0_0_12; + wire n_0_1; + wire n_0_0_13; + wire n_0_0_14; + wire n_0_0_15; + wire n_0_0_16; + wire n_0_0_17; + wire n_0_0_18; + wire n_0_0_19; + wire n_0_0_20; + wire n_1_0_0; + wire n_1_0_1; + wire n_1_0_2; + wire n_1_0_3; + wire n_1_0_4; + wire n_1_0_5; + wire n_1_0_6; + wire n_1_0_7; + wire n_1_0_8; + wire n_1_0_9; + wire n_1_0_10; + wire n_1_0_11; + wire n_1_0_12; + wire n_1_0_13; + wire n_1_0_14; + wire n_1_0_15; + wire n_1_0_16; + wire n_1_0_17; + wire n_1_0_18; + wire n_1_0_19; + wire n_1_0_20; + wire n_1_0_21; + wire n_1_0_22; + wire n_1_0_23; + wire n_1_0_24; + wire n_1_0_25; + wire n_1_0_26; + wire n_1_0_27; + wire n_1_0_28; + wire n_1_0_29; + wire n_1_0_30; + wire n_1_0_31; + wire n_1_0_32; + wire n_1_0_33; + wire n_1_0_34; + wire n_1_0_35; + wire n_1_0_36; + wire n_1_0_37; + wire n_1_0_38; + wire n_1_0_39; + wire n_1_0_40; + wire n_1_0_41; + wire n_1_0_42; + wire n_1_0_43; + wire n_1_0_44; + wire n_1_0_45; + wire n_1_0_46; + wire n_1_0_47; + wire n_1_0_48; + wire n_1_0_49; + wire n_1_0_50; + wire n_1_0_51; + wire n_1_0_52; + wire n_1_0_53; + wire n_1_0_54; + wire n_1_0_55; + wire n_1_0_56; + wire n_1_0_57; + wire n_1_0_58; + wire n_1_0_59; + wire n_1_0_60; + wire n_1_0_61; + wire n_1_0_62; + wire n_1_0_63; + wire n_1_0_64; + wire n_1_0_65; + wire n_1_0_66; + wire n_1_0_67; + wire n_1_0_68; + wire n_1_0_69; + wire n_1_0_70; + wire n_1_0_71; + wire n_1_0_72; + wire n_1_0_73; + wire n_1_0_74; + wire n_1_0_75; + wire n_1_0_76; + wire n_1_0_77; + wire n_1_0_78; + wire n_1_0_79; + wire n_1_0_80; + wire n_1_0_81; + wire n_1_0_82; + wire n_1_0_83; + wire n_1_0_84; + wire n_1_0_85; + wire n_1_0_86; + wire n_1_0_87; + wire n_1_0_88; + wire n_1_0_89; + wire n_1_0_90; + wire n_1_0_91; + wire n_1_0_92; + wire n_1_0_93; + wire n_1_0_94; + wire n_1_0_95; + wire n_1_0_96; + wire n_1_0_97; + wire n_1_0_98; + wire n_1_0_99; + wire n_1_0_100; + wire n_1_0_101; + wire n_1_0_102; + wire n_1_0_103; + wire n_1_0_104; + wire n_1_0_105; + wire n_1_0_106; + wire n_1_0_107; + wire n_1_0_108; + wire n_1_0_109; + wire n_1_0_110; + wire n_1_0_111; + wire n_1_0_112; + wire n_1_0_113; + wire n_1_0_114; + wire n_1_0_115; + wire n_1_0_116; + wire n_1_0_117; + wire n_1_0_118; + wire n_1_0_119; + wire n_1_0_120; + wire n_1_0_121; + wire n_1_0_122; + wire n_1_0_123; + wire n_1_0_124; + wire n_1_0_125; + wire n_1_0_126; + wire n_1_0_127; + wire n_1_0_128; + wire n_1_0_129; + wire n_1_0_130; + wire n_1_0_131; + wire n_1_0_132; + wire n_1_0_133; + wire n_1_0_134; + wire n_1_0_135; + wire n_1_0_136; + wire n_1_0_137; + wire n_1_0_138; + wire n_1_0_139; + wire n_1_0_140; + wire n_1_0_141; + wire n_1_0_142; + wire n_1_0_143; + wire n_1_0_144; + wire n_1_0_145; + wire n_1_0_146; + wire n_1_0_147; + wire n_1_0_148; + wire n_1_0_149; + wire n_1_0_150; + wire n_1_0_151; + wire n_1_0_152; + wire n_1_0_153; + wire n_1_0_154; + wire n_1_0_155; + wire n_1_0_156; + wire n_1_0_157; + wire n_1_0_158; + wire n_1_0_159; + wire n_1_0_160; + wire n_1_0_161; + wire n_1_0_162; + wire n_1_0_163; + wire n_1_0_164; + wire n_1_0_165; + wire n_1_0_166; + wire n_1_0_167; + wire n_1_0_168; + wire n_1_0_169; + wire n_1_0_170; + wire n_1_0_171; + wire n_1_0_172; + wire n_1_0_173; + wire n_1_0_174; + wire n_1_0_175; + wire n_1_0_176; + wire n_1_0_177; + wire n_1_0_178; + wire n_1_0_179; + wire n_1_0_180; + wire n_1_0_181; + wire n_1_0_182; + wire n_1_0_183; + wire n_1_0_184; + wire n_1_0_185; + wire n_1_0_186; + wire n_1_0_187; + wire n_1_0_188; + wire n_1_0_189; + wire n_1_0_190; + wire n_1_0_191; + wire n_1_0_192; + wire n_1_0_193; + wire n_1_0_194; + wire n_1_0_195; + wire n_1_0_196; + wire n_1_0_197; + wire n_1_0_198; + wire n_1_0_199; + wire n_1_0_200; + wire n_1_0_201; + wire n_1_0_202; + wire n_1_0_203; + wire n_1_0_204; + wire n_1_0_205; + wire n_1_0_206; + wire n_1_0_207; + wire n_1_0_208; + wire n_1_0_209; + wire n_1_0_210; + wire n_1_0_211; + wire n_1_0_212; + wire n_1_0_213; + wire n_1_0_214; + wire n_1_0_215; + wire n_1_0_216; + wire n_1_0_217; + wire n_1_0_218; + wire n_1_0_219; + wire n_1_0_220; + wire n_1_0_221; + wire n_1_0_222; + wire n_1_0_223; + wire n_1_0_224; + wire n_1_0_225; + wire n_1_0_226; + wire n_1_0_227; + wire n_1_0_228; + wire n_1_0_229; + wire n_1_0_230; + wire n_1_0_231; + wire n_1_0_232; + wire n_1_0_233; + wire n_1_0_234; + wire n_1_0_235; + wire n_1_0_236; + wire n_1_0_237; + wire n_1_0_238; + wire n_1_0_239; + wire n_1_0_240; + wire n_1_0_241; + wire n_1_0_242; + wire n_1_0_243; + wire n_1_0_244; + wire n_1_0_245; + wire n_1_0_246; + wire n_1_0_247; + wire n_1_0_248; + wire n_1_0_249; + wire n_1_0_250; + wire n_1_0_251; + wire n_1_0_252; + wire n_1_0_253; + wire n_1_0_254; + wire n_1_0_255; + wire n_1_0_256; + wire n_1_0_257; + wire n_1_0_258; + wire n_1_0_259; + wire n_1_0_260; + wire n_1_0_261; + wire n_1_0_262; + wire n_1_0_263; + wire n_1_0_264; + wire n_1_0_265; + wire n_1_0_266; + wire n_1_0_267; + wire n_1_0_268; + wire n_1_0_269; + wire n_1_0_270; + wire n_1_0_271; + wire n_1_0_272; + wire n_1_0_273; + wire n_1_0_274; + wire n_1_0_275; + wire n_1_0_276; + wire n_1_0_277; + wire n_1_0_278; + wire n_1_0_279; + wire n_1_0_280; + wire n_1_0_281; + wire n_1_0_282; + wire n_1_0_283; + wire n_1_0_284; + wire n_1_0_285; + wire n_1_0_286; + wire n_1_0_287; + wire n_1_0_288; + wire n_1_0_289; + wire n_1_0_290; + wire n_1_0_291; + wire n_1_0_292; + wire n_1_0_293; + wire n_1_0_294; + wire n_1_0_295; + wire n_1_0_296; + wire n_1_0_297; + wire n_1_0_298; + wire n_1_0_299; + wire n_1_0_300; + wire n_1_0_301; + wire n_1_0_302; + wire n_1_0_303; + wire n_1_0_304; + wire n_1_0_305; + wire n_1_0_306; + wire n_1_0_307; + wire n_1_0_308; + wire n_1_0_309; + wire n_1_0_310; + wire n_1_0_311; + wire n_1_0_312; + wire n_1_0_313; + wire n_1_0_314; + wire n_1_0_315; + wire n_1_0_316; + wire n_1_0_317; + wire n_1_0_318; + wire n_1_0_319; + wire n_1_0_320; + wire n_1_0_321; + wire n_1_0_322; + wire n_1_0_323; + wire n_1_0_324; + wire n_1_0_325; + wire n_1_0_326; + wire n_1_0_327; + wire n_1_0_328; + wire n_1_0_329; + wire n_1_0_330; + wire n_1_0_331; + wire n_1_0_332; + wire n_1_0_333; + wire n_1_0_334; + wire n_1_0_335; + wire n_1_0_336; + wire n_1_0_337; + wire n_1_0_338; + wire n_1_0_339; + wire n_1_0_340; + wire n_1_0_341; + wire n_1_0_342; + wire n_1_0_343; + wire n_1_0_344; + wire n_1_0_345; + wire n_1_0_346; + wire n_1_0_347; + wire n_1_0_348; + wire n_1_0_349; + wire n_1_0_350; + wire n_1_0_351; + wire n_1_0_352; + wire n_1_0_353; + wire n_1_0_354; + wire n_1_0_355; + wire n_1_0_356; + wire n_1_0_357; + wire n_1_0_358; + wire n_1_0_359; + wire n_1_0_360; + wire n_1_0_361; + wire n_1_0_362; + wire n_1_0_363; + wire n_1_0_364; + wire n_1_0_365; + wire n_1_0_366; + wire n_1_0_367; + wire n_1_0_368; + wire n_1_0_369; + wire n_1_0_370; + wire n_1_0_371; + wire n_1_0_372; + wire n_1_0_373; + wire n_1_0_374; + wire n_1_0_375; + wire n_1_0_376; + wire n_1_0_377; + wire n_1_0_378; + wire n_1_0_379; + wire n_1_0_380; + wire n_1_0_381; + wire n_1_0_382; + wire n_1_0_383; + wire n_1_0_384; + wire n_1_0_385; + wire n_1_0_386; + wire n_1_0_387; + wire n_1_0_388; + wire n_1_0_389; + wire n_1_0_390; + wire n_1_0_391; + wire n_1_0_392; + wire n_1_0_393; + wire n_1_0_394; + wire n_1_0_395; + wire n_1_0_396; + wire n_1_0_397; + wire n_1_0_398; + wire n_1_0_399; + wire n_1_0_400; + wire n_1_0_401; + wire n_1_0_402; + wire n_1_0_403; + wire n_1_0_404; + wire n_1_0_405; + wire n_1_0_406; + wire n_1_0_407; + wire n_1_0_408; + wire n_1_0_409; + wire n_1_0_410; + wire n_1_0_411; + wire n_1_0_412; + wire n_1_0_413; + wire n_1_0_414; + wire n_1_0_415; + wire n_1_0_416; + wire n_1_0_417; + wire n_1_0_418; + wire n_1_0_419; + wire n_1_0_420; + wire n_1_0_421; + wire n_1_0_422; + wire n_1_0_423; + wire n_1_0_424; + wire n_1_0_425; + wire n_1_0_426; + wire n_1_0_427; + wire n_1_0_428; + wire n_1_0_429; + wire n_1_0_430; + wire n_1_0_431; + wire n_1_0_432; + wire n_1_0_433; + wire n_1_0_434; + wire n_1_0_435; + wire n_1_0_436; + wire n_1_0_437; + wire n_1_0_438; + wire n_1_0_439; + wire n_1_0_440; + wire n_1_0_441; + wire n_1_0_442; + wire n_1_0_443; + wire n_1_0_444; + wire n_1_0_445; + wire n_1_0_446; + wire n_1_0_447; + wire n_1_0_448; + wire n_1_0_449; + wire n_1_0_450; + wire n_1_0_451; + wire n_1_0_452; + wire n_1_0_453; + wire n_1_0_454; + wire n_1_0_455; + wire n_1_0_456; + wire n_1_0_457; + wire n_1_0_458; + wire n_1_0_459; + wire n_1_0_460; + wire n_1_0_461; + wire n_1_0_462; + wire n_1_0_463; + wire n_1_0_464; + wire n_1_0_465; + wire n_1_0_466; + wire n_1_0_467; + wire n_1_0_468; + wire n_1_0_469; + wire n_1_0_470; + wire n_1_0_471; + wire n_1_0_472; + wire n_1_0_473; + wire n_1_0_474; + wire n_1_0_475; + wire n_1_0_476; + wire n_1_0_477; + wire n_1_0_478; + wire n_1_0_479; + wire n_1_0_480; + wire n_1_0_481; + wire n_1_0_482; + wire n_1_0_483; + wire n_1_0_484; + wire n_1_0_485; + wire n_1_0_486; + wire n_1_0_487; + wire n_1_0_488; + wire n_1_0_489; + wire n_1_0_490; + wire n_1_0_491; + wire n_1_0_492; + wire n_1_0_493; + wire n_1_0_494; + wire n_1_0_495; + wire n_1_0_496; + wire n_1_0_497; + wire n_1_0_498; + wire n_1_0_499; + wire n_1_0_500; + wire n_1_0_501; + wire n_1_0_502; + wire n_1_0_503; + wire n_1_0_504; + wire n_1_0_505; + wire n_1_0_506; + wire n_1_0_507; + wire n_1_0_508; + wire n_1_0_509; + wire n_1_0_510; + wire n_1_0_511; + wire n_1_0_512; + wire n_1_0_513; + wire n_1_0_514; + wire n_1_0_515; + wire n_1_0_516; + wire n_1_0_517; + wire n_1_0_518; + wire n_1_0_519; + wire n_1_0_520; + wire n_1_0_521; + wire n_1_0_522; + wire n_1_0_523; + wire n_1_0_524; + wire n_1_0_525; + wire n_1_0_526; + wire n_1_0_527; + wire n_1_0_528; + wire n_1_0_529; + wire n_1_0_530; + wire n_1_0_531; + wire n_1_0_532; + wire n_1_0_533; + wire n_1_0_534; + wire n_1_0_535; + wire n_1_0_536; + wire n_1_0_537; + wire n_1_0_538; + wire n_1_0_539; + wire n_1_0_540; + wire n_1_0_541; + wire n_1_0_542; + wire n_1_0_543; + wire n_1_0_544; + wire n_1_0_545; + wire n_1_0_546; + wire n_1_0_547; + wire n_1_0_548; + wire n_1_0_549; + wire n_1_0_550; + wire n_1_0_551; + wire n_1_0_552; + wire n_1_0_553; + wire n_1_0_554; + wire n_1_0_555; + wire n_1_0_556; + wire n_1_0_557; + wire n_1_0_558; + wire n_1_0_559; + wire n_1_0_560; + wire n_1_0_561; + wire n_1_0_562; + wire n_1_0_563; + wire n_1_0_564; + wire n_1_0_565; + wire n_1_0_566; + wire n_1_0_567; + wire n_1_0_568; + wire n_1_0_569; + wire n_1_0_570; + wire n_1_0_571; + wire n_1_0_572; + wire n_1_0_573; + wire n_1_0_574; + wire n_1_0_575; + wire n_1_0_576; + wire n_1_0_577; + wire n_1_0_578; + wire n_1_0_579; + wire n_1_0_580; + wire n_1_0_581; + wire n_1_0_582; + wire n_1_0_583; + wire n_1_0_584; + wire n_1_0_585; + wire n_1_0_586; + wire n_1_0_587; + wire n_1_0_588; + wire n_1_0_589; + wire n_1_0_590; + wire n_1_0_591; + wire n_1_0_592; + wire n_1_0_593; + wire n_1_0_594; + wire n_1_0_595; + wire n_1_0_596; + wire n_1_0_597; + wire n_1_0_598; + wire n_1_0_599; + wire n_1_0_600; + wire n_1_0_601; + wire n_1_0_602; + wire n_1_0_603; + wire n_1_0_604; + wire n_1_0_605; + wire n_1_0_606; + wire n_1_0_607; + wire n_1_0_608; + wire n_1_0_609; + wire n_1_0_610; + wire n_1_0_611; + wire n_1_0_612; + wire n_1_0_613; + wire n_1_0_614; + wire n_1_0_615; + wire n_1_0_616; + wire n_1_0_617; + wire n_1_0_618; + wire n_1_0_619; + wire n_1_0_620; + wire n_1_0_621; + wire n_1_0_622; + wire n_1_0_623; + wire n_1_0_624; + wire n_1_0_625; + wire n_1_0_626; + wire n_1_0_627; + wire n_1_0_628; + wire n_1_0_629; + wire n_1_0_630; + wire n_1_0_631; + wire n_1_0_632; + wire n_1_0_633; + wire n_1_0_634; + wire n_1_0_635; + wire n_1_0_636; + wire n_1_0_637; + wire n_1_0_638; + wire n_1_0_639; + wire n_1_0_640; + wire n_1_0_641; + wire n_1_0_642; + wire n_1_0_643; + wire n_1_0_644; + wire n_1_0_645; + wire n_1_0_646; + wire n_1_0_647; + wire n_1_0_648; + wire n_1_0_649; + wire n_1_0_650; + wire n_1_0_651; + wire n_1_0_652; + wire n_1_0_653; + wire n_1_0_654; + wire n_1_0_655; + wire n_1_0_656; + wire n_1_0_657; + wire n_1_0_658; + wire n_1_0_659; + wire n_1_0_660; + wire n_1_0_661; + wire n_1_0_662; + wire n_1_0_663; + wire n_1_0_664; + wire n_1_0_665; + wire n_1_0_666; + wire n_1_0_667; + wire n_1_0_668; + wire n_1_0_669; + wire n_1_0_670; + wire n_1_0_671; + wire n_1_0_672; + wire n_1_0_673; + wire n_1_0_674; + wire n_1_0_675; + wire n_1_0_676; + wire n_1_0_677; + wire n_1_0_678; + wire n_1_0_679; + wire n_1_0_680; + wire n_1_0_681; + wire n_1_0_682; + wire n_1_0_683; + wire n_1_0_684; + wire n_1_0_685; + wire n_1_0_686; + wire n_1_0_687; + wire n_1_0_688; + wire n_1_0_689; + wire n_1_0_690; + wire n_1_0_691; + wire n_1_0_692; + wire n_1_0_693; + wire n_1_0_694; + wire n_1_0_695; + wire n_1_0_696; + wire n_1_0_697; + wire n_1_0_698; + wire n_1_0_699; + wire n_1_0_700; + wire n_1_0_701; + wire n_1_0_702; + wire n_1_0_703; + wire n_1_0_704; + wire n_1_0_705; + wire n_1_0_706; + wire n_1_0_707; + wire n_1_0_708; + wire n_1_0_709; + wire n_1_0_710; + wire n_1_0_711; + wire n_1_0_712; + wire n_1_0_713; + wire n_1_0_714; + wire n_1_0_715; + wire n_1_0_716; + wire n_1_0_717; + wire n_1_0_718; + wire n_1_0_719; + wire n_1_0_720; + wire n_1_0_721; + wire n_1_0_722; + wire n_1_0_723; + wire n_1_0_724; + wire n_1_0_725; + wire n_1_0_726; + wire n_1_0_727; + wire n_1_0_728; + wire n_1_0_729; + wire n_1_0_730; + wire n_1_0_731; + wire n_1_0_732; + wire n_1_0_733; + wire n_1_0_734; + wire n_1_0_735; + wire n_1_0_736; + wire n_1_0_737; + wire n_1_0_738; + wire n_1_0_739; + wire n_1_0_740; + wire n_1_0_741; + wire n_1_0_742; + wire n_1_0_743; + wire n_1_0_744; + wire n_1_0_745; + wire n_1_0_746; + wire n_1_0_747; + wire n_1_0_748; + wire n_1_0_749; + wire n_1_0_750; + wire n_1_0_751; + wire n_1_0_752; + wire n_1_0_753; + wire n_1_0_754; + wire n_1_0_755; + wire n_1_0_756; + wire n_1_0_757; + wire n_1_0_758; + wire n_1_0_759; + wire n_1_0_760; + wire n_1_0_761; + wire n_1_0_762; + wire n_1_0_763; + wire n_1_0_764; + wire n_1_0_765; + wire n_1_0_766; + wire n_1_0_767; + wire n_1_0_768; + wire n_1_0_769; + wire n_1_0_770; + wire n_1_0_771; + wire n_1_0_772; + wire n_1_0_773; + wire n_1_0_774; + wire n_1_0_775; + wire n_1_0_776; + wire n_1_0_777; + wire n_1_0_778; + wire n_1_0_779; + wire n_1_0_780; + wire n_1_0_781; + wire n_1_0_782; + wire n_1_0_783; + wire n_1_0_784; + wire n_1_0_785; + wire n_1_0_786; + wire n_1_0_787; + wire n_1_0_788; + wire n_1_0_789; + wire n_1_0_790; + wire n_1_0_791; + wire n_1_0_792; + wire n_1_0_793; + wire n_1_0_794; + wire n_1_0_795; + wire n_1_0_796; + wire n_1_0_797; + wire n_1_0_798; + wire n_1_0_799; + wire n_1_0_800; + wire n_1_0_801; + wire n_1_0_802; + wire n_1_0_803; + wire n_1_0_804; + wire n_1_0_805; + wire n_1_0_806; + wire n_1_0_807; + wire n_1_0_808; + wire n_1_0_809; + wire n_1_0_810; + wire n_1_0_811; + wire n_1_0_812; + wire n_1_0_813; + wire n_1_0_814; + wire n_1_0_815; + wire n_1_0_816; + wire n_1_0_817; + wire n_1_0_818; + wire n_1_0_819; + wire n_1_0_820; + wire n_1_0_821; + wire n_1_0_822; + wire n_1_0_823; + wire n_1_0_824; + wire n_1_0_825; + wire n_1_0_826; + wire n_1_0_827; + wire n_1_0_828; + wire n_1_0_829; + wire n_1_0_830; + wire n_1_0_831; + wire n_1_0_832; + wire n_1_0_833; + wire n_1_0_834; + wire n_1_0_835; + wire n_1_0_836; + wire n_1_0_837; + wire n_1_0_838; + wire n_1_0_839; + wire n_1_0_840; + wire n_1_0_841; + wire n_1_0_842; + wire n_1_0_843; + wire n_1_0_844; + wire n_1_0_845; + wire n_1_0_846; + wire n_1_0_847; + wire n_1_0_848; + wire n_1_0_849; + wire n_1_0_850; + wire n_1_0_851; + wire n_1_0_852; + wire n_1_0_853; + wire n_1_0_854; + wire n_1_0_855; + wire n_1_0_856; + wire n_1_0_857; + wire n_1_0_858; + wire n_1_0_859; + wire n_1_0_860; + wire n_1_0_861; + wire n_1_0_862; + wire n_1_0_863; + wire n_1_0_864; + wire n_1_0_865; + wire n_1_0_866; + wire n_1_0_867; + wire n_1_0_868; + wire n_1_0_869; + wire n_1_0_870; + wire n_1_0_871; + wire n_1_0_872; + wire n_1_0_873; + wire n_1_0_874; + wire n_1_0_875; + wire n_1_0_876; + wire n_1_0_877; + wire n_1_0_878; + wire n_1_0_879; + wire n_1_0_880; + wire n_1_0_881; + wire n_1_0_882; + wire n_1_0_883; + wire n_1_0_884; + wire n_1_0_885; + wire n_1_0_886; + wire n_1_0_887; + wire n_1_0_888; + wire n_1_0_889; + wire n_1_0_890; + wire n_1_0_891; + wire n_1_0_892; + wire n_1_0_893; + wire n_1_0_894; + wire n_1_0_895; + wire n_1_0_896; + wire n_1_0_897; + wire n_1_0_898; + wire n_1_0_899; + wire n_1_0_900; + wire n_1_0_901; + wire n_1_0_902; + wire n_1_0_903; + wire n_1_0_904; + wire n_1_0_905; + wire n_1_0_906; + wire n_1_0_907; + wire n_1_0_908; + wire n_1_0_909; + wire n_1_0_910; + wire n_1_0_911; + wire n_1_0_912; + wire n_1_0_913; + wire n_1_0_914; + wire n_1_0_915; + wire n_1_0_916; + wire n_1_0_917; + wire n_1_0_918; + wire n_1_0_919; + wire n_1_0_920; + wire n_1_0_921; + wire n_1_0_922; + wire n_1_0_923; + wire n_1_0_924; + wire n_1_0_925; + wire n_1_0_926; + wire n_1_0_927; + wire n_1_0_928; + wire n_1_0_929; + wire n_1_0_930; + wire n_1_0_931; + wire n_1_0_932; + wire n_1_0_933; + wire n_1_0_934; + wire n_1_0_935; + wire n_1_0_936; + wire n_1_0_937; + wire n_1_0_938; + wire n_1_0_939; + wire n_1_0_940; + wire n_1_0_941; + wire n_1_0_942; + wire n_1_0_943; + wire n_1_0_944; + wire n_1_0_945; + wire n_1_0_946; + wire n_1_0_947; + wire n_1_0_948; + wire n_1_0_949; + wire n_1_0_950; + wire n_1_0_951; + wire n_1_0_952; + wire n_1_0_953; + wire n_1_0_954; + wire n_1_0_955; + wire n_1_0_956; + wire n_1_0_957; + wire n_1_0_958; + wire n_1_0_959; + wire n_1_0_960; + wire n_1_0_961; + wire n_1_0_962; + wire n_1_0_963; + wire n_1_0_964; + wire n_1_0_965; + wire n_1_0_966; + wire n_1_0_967; + wire n_1_0_968; + wire n_1_0_969; + wire n_1_0_970; + wire n_1_0_971; + wire n_1_0_972; + wire n_1_0_973; + wire n_1_0_974; + wire n_1_0_975; + wire n_1_0_976; + wire n_1_0_977; + wire n_1_0_978; + wire n_1_0_979; + wire n_1_0_980; + wire n_1_0_981; + wire n_1_0_982; + wire n_1_0_983; + wire n_1_0_984; + wire n_1_0_985; + wire n_1_0_986; + wire n_1_0_987; + wire n_1_0_988; + wire n_1_0_989; + wire n_1_0_990; + wire n_1_0_991; + wire n_1_0_992; + wire n_1_0_993; + wire n_1_0_994; + wire n_1_0_995; + wire n_1_0_996; + wire n_1_0_997; + wire n_1_0_998; + wire n_1_0_999; + wire n_1_0_1000; + wire n_1_0_1001; + wire n_1_0_1002; + wire n_1_0_1003; + wire n_1_0_1004; + wire n_1_0_1005; + wire n_1_0_1006; + wire n_1_0_1007; + wire n_1_0_1008; + wire n_1_0_1009; + wire n_1_0_1010; + wire n_1_0_1011; + wire n_1_0_1012; + wire n_1_0_1013; + wire n_1_0_1014; + wire n_1_0_1015; + wire n_1_0_1016; + wire n_1_0_1017; + wire n_1_0_1018; + wire n_1_0_1019; + wire n_1_0_1020; + wire n_1_0_1021; + wire n_1_0_1022; + wire n_1_0_1023; + wire n_1_0_1024; + wire n_1_0_1025; + wire n_1_0_1026; + wire n_1_0_1027; + wire n_1_0_1028; + wire n_1_0_1029; + wire n_1_0_1030; + wire n_1_0_1031; + wire n_1_0_1032; + wire n_1_0_1033; + wire n_1_0_1034; + wire n_1_0_1035; + wire n_1_0_1036; + wire n_1_0_1037; + wire n_1_0_1038; + wire n_1_0_1039; + wire n_1_0_1040; + wire n_1_0_1041; + wire n_1_0_1042; + wire n_1_0_1043; + wire n_1_0_1044; + wire n_1_0_1045; + wire n_1_0_1046; + wire n_1_0_1047; + wire n_1_0_1048; + wire n_1_0_1049; + wire n_1_0_1050; + wire n_1_0_1051; + wire n_1_0_1052; + wire n_1_0_1053; + wire n_1_0_1054; + wire n_1_0_1055; + wire n_1_0_1056; + wire n_1_0_1057; + wire n_1_0_1058; + wire n_1_0_1059; + wire n_1_0_1060; + wire n_1_0_1061; + wire n_1_0_1062; + wire n_1_0_1063; + wire n_1_0_1064; + wire n_1_0_1065; + wire n_1_0_1066; + wire n_1_0_1067; + wire n_1_0_1068; + wire n_1_0_1069; + wire n_1_0_1070; + wire n_1_0_1071; + wire n_1_0_1072; + wire n_1_0_1073; + wire n_1_0_1074; + wire n_1_0_1075; + wire n_1_0_1076; + wire n_1_0_1077; + wire n_1_0_1078; + wire n_1_0_1079; + wire n_1_0_1080; + wire n_1_0_1081; + wire n_1_0_1082; + wire n_1_0_1083; + wire n_1_0_1084; + wire n_1_0_1085; + wire n_1_0_1086; + wire n_1_0_1087; + wire n_1_0_1088; + wire n_1_0_1089; + wire n_1_0_1090; + wire n_1_0_1091; + wire n_1_0_1092; + wire n_1_0_1093; + wire n_1_0_1094; + wire n_1_0_1095; + wire n_1_0_1096; + wire n_1_0_1097; + wire n_1_0_1098; + wire n_1_0_1099; + wire n_1_0_1100; + wire n_1_0_1101; + wire n_1_0_1102; + wire n_1_0_1103; + wire n_1_0_1104; + wire n_1_0_1105; + wire n_1_0_1106; + wire n_1_0_1107; + wire n_1_0_1108; + wire n_1_0_1109; + wire n_1_0_1110; + wire n_1_0_1111; + wire n_1_0_1112; + wire n_1_0_1113; + wire n_1_0_1114; + wire n_1_0_1115; + wire n_1_0_1116; + wire n_1_0_1117; + wire n_1_0_1118; + wire n_1_0_1119; + wire n_1_0_1120; + wire n_1_0_1121; + wire n_1_0_1122; + wire n_1_0_1123; + wire n_1_0_1124; + wire n_1_0_1125; + wire n_1_0_1126; + wire n_1_0_1127; + wire n_1_0_1128; + wire n_1_0_1129; + wire n_1_0_1130; + wire n_1_0_1131; + wire n_1_0_1132; + wire n_1_0_1133; + wire n_1_0_1134; + wire n_1_0_1135; + wire n_1_0_1136; + wire n_1_0_1137; + wire n_1_0_1138; + wire n_1_0_1139; + wire n_1_0_1140; + wire n_1_0_1141; + wire n_1_0_1142; + wire n_1_0_1143; + wire n_1_0_1144; + wire n_1_0_1145; + wire n_1_0_1146; + wire n_1_0_1147; + wire n_1_0_1148; + wire n_1_0_1149; + wire n_1_0_1150; + wire n_1_0_1151; + wire n_1_0_1152; + wire n_1_0_1153; + wire n_1_0_1154; + wire n_1_0_1155; + wire n_1_0_1156; + wire n_1_0_1157; + wire n_1_0_1158; + wire n_1_0_1159; + wire n_1_0_1160; + wire n_1_0_1161; + wire n_1_0_1162; + wire n_1_0_1163; + wire n_1_0_1164; + wire n_1_0_1165; + wire n_1_0_1166; + wire n_1_0_1167; + wire n_1_0_1168; + wire n_1_0_1169; + wire n_1_0_1170; + wire n_1_0_1171; + wire n_1_0_1172; + wire n_1_0_1173; + wire n_1_0_1174; + wire n_1_0_1175; + wire n_1_0_1176; + wire n_1_0_1177; + wire n_1_0_1178; + wire n_1_0_1179; + wire n_1_0_1180; + wire n_1_0_1181; + wire n_1_0_1182; + wire n_1_0_1183; + wire n_1_0_1184; + wire n_1_0_1185; + wire n_1_0_1186; + wire n_1_0_1187; + wire n_1_0_1188; + wire n_1_0_1189; + wire n_1_0_1190; + wire n_1_0_1191; + wire n_1_0_1192; + wire n_1_0_1193; + wire n_1_0_1194; + wire n_1_0_1195; + wire n_1_0_1196; + wire n_1_0_1197; + wire n_1_0_1198; + wire n_1_0_1199; + wire n_1_0_1200; + wire n_1_0_1201; + wire n_1_0_1202; + wire n_1_0_1203; + wire n_1_0_1204; + wire n_1_0_1205; + wire n_1_0_1206; + wire n_1_0_1207; + wire n_1_0_1208; + wire n_1_0_1209; + wire n_1_0_1210; + wire n_1_0_1211; + wire n_1_0_1212; + wire n_1_0_1213; + wire n_1_0_1214; + wire n_1_0_1215; + wire n_1_0_1216; + wire n_1_0_1217; + wire n_1_0_1218; + wire n_1_0_1219; + wire n_1_0_1220; + wire n_1_0_1221; + wire n_1_0_1222; + wire n_1_0_1223; + wire n_1_0_1224; + wire n_1_0_1225; + wire n_1_0_1226; + wire n_1_0_1227; + wire n_1_0_1228; + wire n_1_0_1229; + wire n_1_0_1230; + wire n_1_0_1231; + wire n_1_0_1232; + wire n_1_0_1233; + wire n_1_0_1234; + wire n_1_0_1235; + wire n_1_0_1236; + wire n_1_0_1237; + wire n_1_0_1238; + wire n_1_0_1239; + wire n_1_0_1240; + wire n_1_0_1241; + wire n_1_0_1242; + wire n_1_0_1243; + wire n_1_0_1244; + wire n_1_0_1245; + wire n_1_0_1246; + wire n_1_0_1247; + wire n_1_0_1248; + wire n_1_0_1249; + wire n_1_0_1250; + wire n_1_0_1251; + wire n_1_0_1252; + wire n_1_0_1253; + wire n_1_0_1254; + wire n_1_0_1255; + wire n_1_0_1256; + wire n_1_0_1257; + wire n_1_0_1258; + wire n_1_0_1259; + wire n_1_0_1260; + wire n_1_0_1261; + wire n_1_0_1262; + wire n_1_0_1263; + wire n_1_0_1264; + wire n_1_0_1265; + wire n_1_0_1266; + wire n_1_0_1267; + wire n_1_0_1268; + wire n_1_0_1269; + wire n_1_0_1270; + wire n_1_0_1271; + wire n_1_0_1272; + wire n_1_0_1273; + wire n_1_0_1274; + wire n_1_0_1275; + wire n_1_0_1276; + wire n_1_0_1277; + wire n_1_0_1278; + wire n_1_0_1279; + wire n_1_0_1280; + wire n_1_0_1281; + wire n_1_0_1282; + wire n_1_0_1283; + wire n_1_0_1284; + wire n_1_0_1285; + wire n_1_0_1286; + wire n_1_0_1287; + wire n_1_0_1288; + wire n_1_0_1289; + wire n_1_0_1290; + wire n_1_0_1291; + wire n_1_0_1292; + wire n_1_0_1293; + wire n_1_0_1294; + wire n_1_0_1295; + wire n_1_0_1296; + wire n_1_0_1297; + wire n_1_0_1298; + wire n_1_0_1299; + wire n_1_0_1300; + wire n_1_0_1301; + wire n_1_0_1302; + wire n_1_0_1303; + wire n_1_0_1304; + wire n_1_0_1305; + wire n_1_0_1306; + wire n_1_0_1307; + wire n_1_0_1308; + wire n_1_0_1309; + + INV_X1_LVT i_0_0_79 (.A(reset), .ZN(n_0_0_16)); + AND2_X1_LVT i_0_0_31 (.A1(n_0_0_16), .A2(WRd[31]), .ZN(registers[31])); + INV_X1_LVT i_0_0_81 (.A(Rd[1]), .ZN(n_0_0_18)); + INV_X1_LVT i_0_0_80 (.A(Rd[0]), .ZN(n_0_0_17)); + NAND3_X1_LVT i_0_0_69 (.A1(n_0_0_18), .A2(n_0_0_17), .A3(Rd[2]), .ZN(n_0_0_9)); + NAND3_X1_LVT i_0_0_41 (.A1(Rd[3]), .A2(WrReg), .A3(Rd[4]), .ZN(n_0_0_1)); + OAI21_X1_LVT i_0_0_35 (.A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_1), .ZN(n_0_28)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[28]_reg (.CK(clk), .E(n_0_28), + .SE(dftIn), .GCK(n_0_58)); + SDFF_X1_LVT \registers_reg[28][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_28__ap[31]), .CK(n_0_58), .Q(registers_28__ap[31]), .QN()); + INV_X1_LVT i_1_0_1370 (.A(Rs1[0]), .ZN(n_1_0_1306)); + NAND3_X1_LVT i_1_0_1354 (.A1(n_1_0_1306), .A2(Rs1[3]), .A3(Rs1[4]), .ZN( + n_1_0_1290)); + INV_X1_LVT i_1_0_1373 (.A(Rs1[2]), .ZN(n_1_0_1309)); + OR2_X1_LVT i_1_0_1348 (.A1(n_1_0_1309), .A2(Rs1[1]), .ZN(n_1_0_1284)); + NOR2_X1_LVT i_1_0_1347 (.A1(n_1_0_1290), .A2(n_1_0_1284), .ZN(n_1_0_1283)); + NOR4_X1_LVT i_1_0_1342 (.A1(n_1_0_1284), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), + .ZN(n_1_0_1278)); + INV_X1_LVT i_0_0_83 (.A(WrReg), .ZN(n_0_0_20)); + OR3_X1_LVT i_0_0_77 (.A1(n_0_0_20), .A2(Rd[4]), .A3(Rd[3]), .ZN(n_0_0_14)); + OAI21_X1_LVT i_0_0_68 (.A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_9), .ZN(n_0_4)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[4]_reg (.CK(clk), .E(n_0_4), + .SE(dftIn), .GCK(n_0_34)); + SDFF_X1_LVT \registers_reg[4][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_4__ap[31]), .CK(n_0_34), .Q(registers_4__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1320 (.A1(registers_28__ap[31]), .A2(n_1_0_1283), .B1( + n_1_0_1278), .B2(registers_4__ap[31]), .ZN(n_1_0_1256)); + NAND2_X1_LVT i_0_0_70 (.A1(n_0_0_18), .A2(n_0_0_17), .ZN(n_0_0_10)); + INV_X1_LVT i_0_0_82 (.A(Rd[4]), .ZN(n_0_0_19)); + OR3_X1_LVT i_0_0_51 (.A1(n_0_0_20), .A2(n_0_0_19), .A3(Rd[3]), .ZN(n_0_0_3)); + OR2_X1_LVT i_0_0_50 (.A1(n_0_0_3), .A2(Rd[2]), .ZN(n_0_0_2)); + OAI21_X1_LVT i_0_0_49 (.A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_2), .ZN(n_0_16)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[16]_reg (.CK(clk), .E(n_0_16), + .SE(dftIn), .GCK(n_0_46)); + SDFF_X1_LVT \registers_reg[16][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_16__ap[31]), .CK(n_0_46), .Q(registers_16__ap[31]), .QN()); + INV_X1_LVT i_1_0_1371 (.A(Rs1[3]), .ZN(n_1_0_1307)); + NAND3_X1_LVT i_1_0_1363 (.A1(n_1_0_1307), .A2(n_1_0_1306), .A3(Rs1[4]), + .ZN(n_1_0_1299)); + OR2_X1_LVT i_1_0_1357 (.A1(Rs1[1]), .A2(Rs1[2]), .ZN(n_1_0_1293)); + NOR2_X1_LVT i_1_0_1331 (.A1(n_1_0_1299), .A2(n_1_0_1293), .ZN(n_1_0_1267)); + NAND2_X1_LVT i_1_0_1365 (.A1(Rs1[1]), .A2(Rs1[2]), .ZN(n_1_0_1301)); + NAND3_X1_LVT i_1_0_1344 (.A1(Rs1[4]), .A2(Rs1[3]), .A3(Rs1[0]), .ZN( + n_1_0_1280)); + NOR2_X1_LVT i_1_0_1330 (.A1(n_1_0_1301), .A2(n_1_0_1280), .ZN(n_1_0_1266)); + NAND3_X1_LVT i_0_0_63 (.A1(Rd[2]), .A2(Rd[1]), .A3(Rd[0]), .ZN(n_0_0_6)); + OAI21_X1_LVT i_0_0_32 (.A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_1), .ZN(n_0_31)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[31]_reg (.CK(clk), .E(n_0_31), + .SE(dftIn), .GCK(n_0_61)); + SDFF_X1_LVT \registers_reg[31][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_31__ap[31]), .CK(n_0_61), .Q(registers_31__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1329 (.A1(registers_16__ap[31]), .A2(n_1_0_1267), .B1( + n_1_0_1266), .B2(registers_31__ap[31]), .ZN(n_1_0_1265)); + NAND3_X1_LVT i_0_0_65 (.A1(n_0_0_17), .A2(Rd[1]), .A3(Rd[2]), .ZN(n_0_0_7)); + OAI21_X1_LVT i_0_0_64 (.A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_7), .ZN(n_0_6)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[6]_reg (.CK(clk), .E(n_0_6), + .SE(dftIn), .GCK(n_0_36)); + SDFF_X1_LVT \registers_reg[6][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_6__ap[31]), .CK(n_0_36), .Q(registers_6__ap[31]), .QN()); + NOR4_X1_LVT i_1_0_1364 (.A1(n_1_0_1301), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), + .ZN(n_1_0_1300)); + INV_X1_LVT i_1_0_1372 (.A(Rs1[4]), .ZN(n_1_0_1308)); + NAND3_X1_LVT i_1_0_1339 (.A1(n_1_0_1308), .A2(n_1_0_1307), .A3(Rs1[0]), + .ZN(n_1_0_1275)); + NOR2_X1_LVT i_1_0_1338 (.A1(n_1_0_1293), .A2(n_1_0_1275), .ZN(n_1_0_1274)); + NAND2_X1_LVT i_0_0_78 (.A1(n_0_0_18), .A2(Rd[0]), .ZN(n_0_0_15)); + OR2_X1_LVT i_0_0_76 (.A1(n_0_0_14), .A2(Rd[2]), .ZN(n_0_0_13)); + OAI21_X1_LVT i_0_0_75 (.A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_13), .ZN(n_0_1)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[1]_reg (.CK(clk), .E(n_0_1), + .SE(dftIn), .GCK(n_0_0)); + SDFF_X1_LVT \registers_reg[1][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_1__ap[31]), .CK(n_0_0), .Q(registers_1__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1319 (.A1(registers_6__ap[31]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[31]), .ZN(n_1_0_1255)); + OAI21_X1_LVT i_0_0_42 (.A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_3), .ZN(n_0_23)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[23]_reg (.CK(clk), .E(n_0_23), + .SE(dftIn), .GCK(n_0_53)); + SDFF_X1_LVT \registers_reg[23][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_23__ap[31]), .CK(n_0_53), .Q(registers_23__ap[31]), .QN()); + NAND3_X1_LVT i_1_0_1360 (.A1(n_1_0_1307), .A2(Rs1[0]), .A3(Rs1[4]), .ZN( + n_1_0_1296)); + NOR2_X1_LVT i_1_0_1328 (.A1(n_1_0_1301), .A2(n_1_0_1296), .ZN(n_1_0_1264)); + NOR2_X1_LVT i_1_0_1327 (.A1(n_1_0_1301), .A2(n_1_0_1275), .ZN(n_1_0_1263)); + OAI21_X1_LVT i_0_0_62 (.A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_6), .ZN(n_0_7)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[7]_reg (.CK(clk), .E(n_0_7), + .SE(dftIn), .GCK(n_0_37)); + SDFF_X1_LVT \registers_reg[7][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_7__ap[31]), .CK(n_0_37), .Q(registers_7__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1326 (.A1(registers_23__ap[31]), .A2(n_1_0_1264), .B1( + n_1_0_1263), .B2(registers_7__ap[31]), .ZN(n_1_0_1262)); + INV_X1_LVT i_1_0_1325 (.A(n_1_0_1262), .ZN(n_1_0_1261)); + NAND2_X1_LVT i_1_0_1362 (.A1(n_1_0_1309), .A2(Rs1[1]), .ZN(n_1_0_1298)); + NOR2_X1_LVT i_1_0_1359 (.A1(n_1_0_1298), .A2(n_1_0_1296), .ZN(n_1_0_1295)); + NAND2_X1_LVT i_0_0_72 (.A1(Rd[1]), .A2(Rd[0]), .ZN(n_0_0_11)); + OAI21_X1_LVT i_0_0_46 (.A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_2), .ZN(n_0_19)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[19]_reg (.CK(clk), .E(n_0_19), + .SE(dftIn), .GCK(n_0_49)); + SDFF_X1_LVT \registers_reg[19][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_19__ap[31]), .CK(n_0_49), .Q(registers_19__ap[31]), .QN()); + NAND3_X1_LVT i_0_0_67 (.A1(n_0_0_18), .A2(Rd[0]), .A3(Rd[2]), .ZN(n_0_0_8)); + OAI21_X1_LVT i_0_0_66 (.A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_8), .ZN(n_0_5)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[5]_reg (.CK(clk), .E(n_0_5), + .SE(dftIn), .GCK(n_0_35)); + SDFF_X1_LVT \registers_reg[5][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_5__ap[31]), .CK(n_0_35), .Q(registers_5__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1337 (.A1(n_1_0_1284), .A2(n_1_0_1275), .ZN(n_1_0_1273)); + AOI221_X1_LVT i_1_0_1318 (.A(n_1_0_1261), .B1(n_1_0_1295), .B2( + registers_19__ap[31]), .C1(registers_5__ap[31]), .C2(n_1_0_1273), .ZN( + n_1_0_1254)); + NAND2_X1_LVT i_0_0_74 (.A1(n_0_0_17), .A2(Rd[1]), .ZN(n_0_0_12)); + NAND3_X1_LVT i_0_0_61 (.A1(n_0_0_19), .A2(WrReg), .A3(Rd[3]), .ZN(n_0_0_5)); + OR2_X1_LVT i_0_0_60 (.A1(n_0_0_5), .A2(Rd[2]), .ZN(n_0_0_4)); + OAI21_X1_LVT i_0_0_57 (.A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_4), .ZN(n_0_10)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[10]_reg (.CK(clk), .E(n_0_10), + .SE(dftIn), .GCK(n_0_40)); + SDFF_X1_LVT \registers_reg[10][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_10__ap[31]), .CK(n_0_40), .Q(registers_10__ap[31]), .QN()); + NAND3_X1_LVT i_1_0_1352 (.A1(n_1_0_1308), .A2(n_1_0_1306), .A3(Rs1[3]), + .ZN(n_1_0_1288)); + NOR2_X1_LVT i_1_0_1351 (.A1(n_1_0_1298), .A2(n_1_0_1288), .ZN(n_1_0_1287)); + NOR2_X1_LVT i_1_0_1349 (.A1(n_1_0_1298), .A2(n_1_0_1290), .ZN(n_1_0_1285)); + OR2_X1_LVT i_0_0_40 (.A1(n_0_0_1), .A2(Rd[2]), .ZN(n_0_0_0)); + OAI21_X1_LVT i_0_0_37 (.A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_0), .ZN(n_0_26)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[26]_reg (.CK(clk), .E(n_0_26), + .SE(dftIn), .GCK(n_0_56)); + SDFF_X1_LVT \registers_reg[26][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_26__ap[31]), .CK(n_0_56), .Q(registers_26__ap[31]), .QN()); + OAI21_X1_LVT i_0_0_59 (.A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_4), .ZN(n_0_8)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[8]_reg (.CK(clk), .E(n_0_8), + .SE(dftIn), .GCK(n_0_38)); + SDFF_X1_LVT \registers_reg[8][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_8__ap[31]), .CK(n_0_38), .Q(registers_8__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1346 (.A1(n_1_0_1293), .A2(n_1_0_1288), .ZN(n_1_0_1282)); + AOI222_X1_LVT i_1_0_1317 (.A1(registers_10__ap[31]), .A2(n_1_0_1287), + .B1(n_1_0_1285), .B2(registers_26__ap[31]), .C1(registers_8__ap[31]), + .C2(n_1_0_1282), .ZN(n_1_0_1253)); + NAND4_X1_LVT i_1_0_1316 (.A1(n_1_0_1265), .A2(n_1_0_1255), .A3(n_1_0_1254), + .A4(n_1_0_1253), .ZN(n_1_0_1252)); + NAND3_X1_LVT i_1_0_1356 (.A1(n_1_0_1308), .A2(Rs1[3]), .A3(Rs1[0]), .ZN( + n_1_0_1292)); + NOR2_X1_LVT i_1_0_1355 (.A1(n_1_0_1293), .A2(n_1_0_1292), .ZN(n_1_0_1291)); + OAI21_X1_LVT i_0_0_58 (.A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_4), .ZN(n_0_9)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[9]_reg (.CK(clk), .E(n_0_9), + .SE(dftIn), .GCK(n_0_39)); + SDFF_X1_LVT \registers_reg[9][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_9__ap[31]), .CK(n_0_39), .Q(registers_9__ap[31]), .QN()); + OAI21_X1_LVT i_0_0_34 (.A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_1), .ZN(n_0_29)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[29]_reg (.CK(clk), .E(n_0_29), + .SE(dftIn), .GCK(n_0_59)); + SDFF_X1_LVT \registers_reg[29][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_29__ap[31]), .CK(n_0_59), .Q(registers_29__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1340 (.A1(n_1_0_1284), .A2(n_1_0_1280), .ZN(n_1_0_1276)); + AOI221_X1_LVT i_1_0_1315 (.A(n_1_0_1252), .B1(n_1_0_1291), .B2( + registers_9__ap[31]), .C1(registers_29__ap[31]), .C2(n_1_0_1276), .ZN( + n_1_0_1251)); + OAI21_X1_LVT i_0_0_47 (.A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_2), .ZN(n_0_18)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[18]_reg (.CK(clk), .E(n_0_18), + .SE(dftIn), .GCK(n_0_48)); + SDFF_X1_LVT \registers_reg[18][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_18__ap[31]), .CK(n_0_48), .Q(registers_18__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1361 (.A1(n_1_0_1299), .A2(n_1_0_1298), .ZN(n_1_0_1297)); + NOR2_X1_LVT i_1_0_1336 (.A1(n_1_0_1301), .A2(n_1_0_1290), .ZN(n_1_0_1272)); + OAI21_X1_LVT i_0_0_33 (.A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_1), .ZN(n_0_30)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[30]_reg (.CK(clk), .E(n_0_30), + .SE(dftIn), .GCK(n_0_60)); + SDFF_X1_LVT \registers_reg[30][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_30__ap[31]), .CK(n_0_60), .Q(registers_30__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1314 (.A1(registers_18__ap[31]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[31]), .ZN(n_1_0_1250)); + OAI21_X1_LVT i_0_0_39 (.A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_0), .ZN(n_0_24)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[24]_reg (.CK(clk), .E(n_0_24), + .SE(dftIn), .GCK(n_0_54)); + SDFF_X1_LVT \registers_reg[24][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_24__ap[31]), .CK(n_0_54), .Q(registers_24__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1353 (.A1(n_1_0_1293), .A2(n_1_0_1290), .ZN(n_1_0_1289)); + NOR2_X1_LVT i_1_0_1324 (.A1(n_1_0_1288), .A2(n_1_0_1284), .ZN(n_1_0_1260)); + OAI21_X1_LVT i_0_0_55 (.A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_5), .ZN(n_0_12)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[12]_reg (.CK(clk), .E(n_0_12), + .SE(dftIn), .GCK(n_0_42)); + SDFF_X1_LVT \registers_reg[12][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_12__ap[31]), .CK(n_0_42), .Q(registers_12__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1313 (.A1(registers_24__ap[31]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[31]), .ZN(n_1_0_1249)); + OAI21_X1_LVT i_0_0_43 (.A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_3), .ZN(n_0_22)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[22]_reg (.CK(clk), .E(n_0_22), + .SE(dftIn), .GCK(n_0_52)); + SDFF_X1_LVT \registers_reg[22][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_22__ap[31]), .CK(n_0_52), .Q(registers_22__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1358 (.A1(n_1_0_1301), .A2(n_1_0_1299), .ZN(n_1_0_1294)); + NOR2_X1_LVT i_1_0_1323 (.A1(n_1_0_1296), .A2(n_1_0_1284), .ZN(n_1_0_1259)); + OAI21_X1_LVT i_0_0_44 (.A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_3), .ZN(n_0_21)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[21]_reg (.CK(clk), .E(n_0_21), + .SE(dftIn), .GCK(n_0_51)); + SDFF_X1_LVT \registers_reg[21][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_21__ap[31]), .CK(n_0_51), .Q(registers_21__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1312 (.A1(registers_22__ap[31]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[31]), .ZN(n_1_0_1248)); + NAND3_X1_LVT i_1_0_1311 (.A1(n_1_0_1250), .A2(n_1_0_1249), .A3(n_1_0_1248), + .ZN(n_1_0_1247)); + NOR2_X1_LVT i_1_0_1335 (.A1(n_1_0_1296), .A2(n_1_0_1293), .ZN(n_1_0_1271)); + OAI21_X1_LVT i_0_0_48 (.A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_2), .ZN(n_0_17)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[17]_reg (.CK(clk), .E(n_0_17), + .SE(dftIn), .GCK(n_0_47)); + SDFF_X1_LVT \registers_reg[17][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_17__ap[31]), .CK(n_0_47), .Q(registers_17__ap[31]), .QN()); + OAI21_X1_LVT i_0_0_45 (.A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_3), .ZN(n_0_20)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[20]_reg (.CK(clk), .E(n_0_20), + .SE(dftIn), .GCK(n_0_50)); + SDFF_X1_LVT \registers_reg[20][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_20__ap[31]), .CK(n_0_50), .Q(registers_20__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1345 (.A1(n_1_0_1299), .A2(n_1_0_1284), .ZN(n_1_0_1281)); + AOI221_X1_LVT i_1_0_1310 (.A(n_1_0_1247), .B1(n_1_0_1271), .B2( + registers_17__ap[31]), .C1(registers_20__ap[31]), .C2(n_1_0_1281), + .ZN(n_1_0_1246)); + OAI21_X1_LVT i_0_0_36 (.A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_0), .ZN(n_0_27)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[27]_reg (.CK(clk), .E(n_0_27), + .SE(dftIn), .GCK(n_0_57)); + SDFF_X1_LVT \registers_reg[27][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_27__ap[31]), .CK(n_0_57), .Q(registers_27__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1343 (.A1(n_1_0_1298), .A2(n_1_0_1280), .ZN(n_1_0_1279)); + NOR2_X1_LVT i_1_0_1334 (.A1(n_1_0_1298), .A2(n_1_0_1292), .ZN(n_1_0_1270)); + OAI21_X1_LVT i_0_0_56 (.A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_4), .ZN(n_0_11)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[11]_reg (.CK(clk), .E(n_0_11), + .SE(dftIn), .GCK(n_0_41)); + SDFF_X1_LVT \registers_reg[11][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_11__ap[31]), .CK(n_0_41), .Q(registers_11__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1309 (.A1(registers_27__ap[31]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[31]), .ZN(n_1_0_1245)); + OAI21_X1_LVT i_0_0_54 (.A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_5), .ZN(n_0_13)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[13]_reg (.CK(clk), .E(n_0_13), + .SE(dftIn), .GCK(n_0_43)); + SDFF_X1_LVT \registers_reg[13][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_13__ap[31]), .CK(n_0_43), .Q(registers_13__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1341 (.A1(n_1_0_1292), .A2(n_1_0_1284), .ZN(n_1_0_1277)); + NOR2_X1_LVT i_1_0_1333 (.A1(n_1_0_1293), .A2(n_1_0_1280), .ZN(n_1_0_1269)); + OAI21_X1_LVT i_0_0_38 (.A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_0), .ZN(n_0_25)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[25]_reg (.CK(clk), .E(n_0_25), + .SE(dftIn), .GCK(n_0_55)); + SDFF_X1_LVT \registers_reg[25][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_25__ap[31]), .CK(n_0_55), .Q(registers_25__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1308 (.A1(registers_13__ap[31]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[31]), .ZN(n_1_0_1244)); + OAI21_X1_LVT i_0_0_52 (.A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_5), .ZN(n_0_15)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[15]_reg (.CK(clk), .E(n_0_15), + .SE(dftIn), .GCK(n_0_45)); + SDFF_X1_LVT \registers_reg[15][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_15__ap[31]), .CK(n_0_45), .Q(registers_15__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1350 (.A1(n_1_0_1301), .A2(n_1_0_1292), .ZN(n_1_0_1286)); + NOR2_X1_LVT i_1_0_1322 (.A1(n_1_0_1301), .A2(n_1_0_1288), .ZN(n_1_0_1258)); + OAI21_X1_LVT i_0_0_53 (.A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_5), .ZN(n_0_14)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[14]_reg (.CK(clk), .E(n_0_14), + .SE(dftIn), .GCK(n_0_44)); + SDFF_X1_LVT \registers_reg[14][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_14__ap[31]), .CK(n_0_44), .Q(registers_14__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1307 (.A1(registers_15__ap[31]), .A2(n_1_0_1286), .B1( + n_1_0_1258), .B2(registers_14__ap[31]), .ZN(n_1_0_1243)); + NAND3_X1_LVT i_1_0_1306 (.A1(n_1_0_1245), .A2(n_1_0_1244), .A3(n_1_0_1243), + .ZN(n_1_0_1242)); + NOR2_X1_LVT i_1_0_1321 (.A1(n_1_0_1298), .A2(n_1_0_1275), .ZN(n_1_0_1257)); + OAI21_X1_LVT i_0_0_71 (.A(n_0_0_16), .B1(n_0_0_13), .B2(n_0_0_11), .ZN(n_0_3)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[3]_reg (.CK(clk), .E(n_0_3), + .SE(dftIn), .GCK(n_0_33)); + SDFF_X1_LVT \registers_reg[3][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_3__ap[31]), .CK(n_0_33), .Q(registers_3__ap[31]), .QN()); + OAI21_X1_LVT i_0_0_73 (.A(n_0_0_16), .B1(n_0_0_13), .B2(n_0_0_12), .ZN(n_0_2)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[2]_reg (.CK(clk), .E(n_0_2), + .SE(dftIn), .GCK(n_0_32)); + SDFF_X1_LVT \registers_reg[2][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_2__ap[31]), .CK(n_0_32), .Q(registers_2__ap[31]), .QN()); + NOR4_X1_LVT i_1_0_1332 (.A1(n_1_0_1298), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), + .ZN(n_1_0_1268)); + AOI221_X1_LVT i_1_0_1305 (.A(n_1_0_1242), .B1(n_1_0_1257), .B2( + registers_3__ap[31]), .C1(registers_2__ap[31]), .C2(n_1_0_1268), .ZN( + n_1_0_1241)); + NAND4_X1_LVT i_1_0_1304 (.A1(n_1_0_1256), .A2(n_1_0_1251), .A3(n_1_0_1246), + .A4(n_1_0_1241), .ZN(RRs1[31])); + AND2_X1_LVT i_0_0_30 (.A1(n_0_0_16), .A2(WRd[30]), .ZN(registers[30])); + SDFF_X1_LVT \registers_reg[28][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_28__ap[30]), .CK(n_0_58), .Q(registers_28__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[17][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_17__ap[30]), .CK(n_0_47), .Q(registers_17__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1300 (.A1(registers_28__ap[30]), .A2(n_1_0_1283), .B1( + n_1_0_1271), .B2(registers_17__ap[30]), .ZN(n_1_0_1237)); + SDFF_X1_LVT \registers_reg[16][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_16__ap[30]), .CK(n_0_46), .Q(registers_16__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[31][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_31__ap[30]), .CK(n_0_61), .Q(registers_31__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1303 (.A1(registers_16__ap[30]), .A2(n_1_0_1267), .B1( + n_1_0_1266), .B2(registers_31__ap[30]), .ZN(n_1_0_1240)); + SDFF_X1_LVT \registers_reg[6][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_6__ap[30]), .CK(n_0_36), .Q(registers_6__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[1][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_1__ap[30]), .CK(n_0_0), .Q(registers_1__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1299 (.A1(registers_6__ap[30]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[30]), .ZN(n_1_0_1236)); + SDFF_X1_LVT \registers_reg[23][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_23__ap[30]), .CK(n_0_53), .Q(registers_23__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[7][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_7__ap[30]), .CK(n_0_37), .Q(registers_7__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1302 (.A1(registers_23__ap[30]), .A2(n_1_0_1264), .B1( + n_1_0_1263), .B2(registers_7__ap[30]), .ZN(n_1_0_1239)); + INV_X1_LVT i_1_0_1301 (.A(n_1_0_1239), .ZN(n_1_0_1238)); + SDFF_X1_LVT \registers_reg[19][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_19__ap[30]), .CK(n_0_49), .Q(registers_19__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[5][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_5__ap[30]), .CK(n_0_35), .Q(registers_5__ap[30]), .QN()); + AOI221_X1_LVT i_1_0_1298 (.A(n_1_0_1238), .B1(n_1_0_1295), .B2( + registers_19__ap[30]), .C1(registers_5__ap[30]), .C2(n_1_0_1273), .ZN( + n_1_0_1235)); + SDFF_X1_LVT \registers_reg[10][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_10__ap[30]), .CK(n_0_40), .Q(registers_10__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[26][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_26__ap[30]), .CK(n_0_56), .Q(registers_26__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[8][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_8__ap[30]), .CK(n_0_38), .Q(registers_8__ap[30]), .QN()); + AOI222_X1_LVT i_1_0_1297 (.A1(registers_10__ap[30]), .A2(n_1_0_1287), + .B1(n_1_0_1285), .B2(registers_26__ap[30]), .C1(registers_8__ap[30]), + .C2(n_1_0_1282), .ZN(n_1_0_1234)); + NAND4_X1_LVT i_1_0_1296 (.A1(n_1_0_1240), .A2(n_1_0_1236), .A3(n_1_0_1235), + .A4(n_1_0_1234), .ZN(n_1_0_1233)); + SDFF_X1_LVT \registers_reg[9][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_9__ap[30]), .CK(n_0_39), .Q(registers_9__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[29][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_29__ap[30]), .CK(n_0_59), .Q(registers_29__ap[30]), .QN()); + AOI221_X1_LVT i_1_0_1295 (.A(n_1_0_1233), .B1(n_1_0_1291), .B2( + registers_9__ap[30]), .C1(registers_29__ap[30]), .C2(n_1_0_1276), .ZN( + n_1_0_1232)); + SDFF_X1_LVT \registers_reg[18][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_18__ap[30]), .CK(n_0_48), .Q(registers_18__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[30][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_30__ap[30]), .CK(n_0_60), .Q(registers_30__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1294 (.A1(registers_18__ap[30]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[30]), .ZN(n_1_0_1231)); + SDFF_X1_LVT \registers_reg[20][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_20__ap[30]), .CK(n_0_50), .Q(registers_20__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[4][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_4__ap[30]), .CK(n_0_34), .Q(registers_4__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1293 (.A1(registers_20__ap[30]), .A2(n_1_0_1281), .B1( + n_1_0_1278), .B2(registers_4__ap[30]), .ZN(n_1_0_1230)); + SDFF_X1_LVT \registers_reg[22][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_22__ap[30]), .CK(n_0_52), .Q(registers_22__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[21][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_21__ap[30]), .CK(n_0_51), .Q(registers_21__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1292 (.A1(registers_22__ap[30]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[30]), .ZN(n_1_0_1229)); + NAND3_X1_LVT i_1_0_1291 (.A1(n_1_0_1231), .A2(n_1_0_1230), .A3(n_1_0_1229), + .ZN(n_1_0_1228)); + SDFF_X1_LVT \registers_reg[24][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_24__ap[30]), .CK(n_0_54), .Q(registers_24__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[12][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_12__ap[30]), .CK(n_0_42), .Q(registers_12__ap[30]), .QN()); + AOI221_X1_LVT i_1_0_1290 (.A(n_1_0_1228), .B1(n_1_0_1289), .B2( + registers_24__ap[30]), .C1(registers_12__ap[30]), .C2(n_1_0_1260), + .ZN(n_1_0_1227)); + SDFF_X1_LVT \registers_reg[27][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_27__ap[30]), .CK(n_0_57), .Q(registers_27__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[11][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_11__ap[30]), .CK(n_0_41), .Q(registers_11__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1289 (.A1(registers_27__ap[30]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[30]), .ZN(n_1_0_1226)); + SDFF_X1_LVT \registers_reg[13][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_13__ap[30]), .CK(n_0_43), .Q(registers_13__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[25][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_25__ap[30]), .CK(n_0_55), .Q(registers_25__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1288 (.A1(registers_13__ap[30]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[30]), .ZN(n_1_0_1225)); + SDFF_X1_LVT \registers_reg[15][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_15__ap[30]), .CK(n_0_45), .Q(registers_15__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[14][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_14__ap[30]), .CK(n_0_44), .Q(registers_14__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1287 (.A1(registers_15__ap[30]), .A2(n_1_0_1286), .B1( + n_1_0_1258), .B2(registers_14__ap[30]), .ZN(n_1_0_1224)); + NAND3_X1_LVT i_1_0_1286 (.A1(n_1_0_1226), .A2(n_1_0_1225), .A3(n_1_0_1224), + .ZN(n_1_0_1223)); + SDFF_X1_LVT \registers_reg[3][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_3__ap[30]), .CK(n_0_33), .Q(registers_3__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[2][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_2__ap[30]), .CK(n_0_32), .Q(registers_2__ap[30]), .QN()); + AOI221_X1_LVT i_1_0_1285 (.A(n_1_0_1223), .B1(n_1_0_1257), .B2( + registers_3__ap[30]), .C1(registers_2__ap[30]), .C2(n_1_0_1268), .ZN( + n_1_0_1222)); + NAND4_X1_LVT i_1_0_1284 (.A1(n_1_0_1237), .A2(n_1_0_1232), .A3(n_1_0_1227), + .A4(n_1_0_1222), .ZN(RRs1[30])); + AND2_X1_LVT i_0_0_29 (.A1(n_0_0_16), .A2(WRd[29]), .ZN(registers[29])); + SDFF_X1_LVT \registers_reg[28][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_28__ap[29]), .CK(n_0_58), .Q(registers_28__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[8][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_8__ap[29]), .CK(n_0_38), .Q(registers_8__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1282 (.A1(registers_28__ap[29]), .A2(n_1_0_1283), .B1( + n_1_0_1282), .B2(registers_8__ap[29]), .ZN(n_1_0_1220)); + SDFF_X1_LVT \registers_reg[31][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_31__ap[29]), .CK(n_0_61), .Q(registers_31__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[7][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_7__ap[29]), .CK(n_0_37), .Q(registers_7__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1283 (.A1(registers_31__ap[29]), .A2(n_1_0_1266), .B1( + n_1_0_1263), .B2(registers_7__ap[29]), .ZN(n_1_0_1221)); + SDFF_X1_LVT \registers_reg[24][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_24__ap[29]), .CK(n_0_54), .Q(registers_24__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[20][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_20__ap[29]), .CK(n_0_50), .Q(registers_20__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1281 (.A1(registers_24__ap[29]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[29]), .ZN(n_1_0_1219)); + SDFF_X1_LVT \registers_reg[19][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_19__ap[29]), .CK(n_0_49), .Q(registers_19__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[4][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_4__ap[29]), .CK(n_0_34), .Q(registers_4__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1280 (.A1(registers_19__ap[29]), .A2(n_1_0_1295), .B1( + n_1_0_1278), .B2(registers_4__ap[29]), .ZN(n_1_0_1218)); + NAND3_X1_LVT i_1_0_1279 (.A1(n_1_0_1221), .A2(n_1_0_1219), .A3(n_1_0_1218), + .ZN(n_1_0_1217)); + SDFF_X1_LVT \registers_reg[23][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_23__ap[29]), .CK(n_0_53), .Q(registers_23__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[29][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_29__ap[29]), .CK(n_0_59), .Q(registers_29__ap[29]), .QN()); + AOI221_X1_LVT i_1_0_1278 (.A(n_1_0_1217), .B1(n_1_0_1264), .B2( + registers_23__ap[29]), .C1(registers_29__ap[29]), .C2(n_1_0_1276), + .ZN(n_1_0_1216)); + SDFF_X1_LVT \registers_reg[10][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_10__ap[29]), .CK(n_0_40), .Q(registers_10__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[26][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_26__ap[29]), .CK(n_0_56), .Q(registers_26__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[25][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_25__ap[29]), .CK(n_0_55), .Q(registers_25__ap[29]), .QN()); + AOI222_X1_LVT i_1_0_1277 (.A1(registers_10__ap[29]), .A2(n_1_0_1287), + .B1(n_1_0_1285), .B2(registers_26__ap[29]), .C1(registers_25__ap[29]), + .C2(n_1_0_1269), .ZN(n_1_0_1215)); + NAND3_X1_LVT i_1_0_1276 (.A1(n_1_0_1220), .A2(n_1_0_1216), .A3(n_1_0_1215), + .ZN(n_1_0_1214)); + SDFF_X1_LVT \registers_reg[21][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_21__ap[29]), .CK(n_0_51), .Q(registers_21__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[13][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_13__ap[29]), .CK(n_0_43), .Q(registers_13__ap[29]), .QN()); + AOI221_X1_LVT i_1_0_1275 (.A(n_1_0_1214), .B1(n_1_0_1259), .B2( + registers_21__ap[29]), .C1(registers_13__ap[29]), .C2(n_1_0_1277), + .ZN(n_1_0_1213)); + SDFF_X1_LVT \registers_reg[18][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_18__ap[29]), .CK(n_0_48), .Q(registers_18__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[30][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_30__ap[29]), .CK(n_0_60), .Q(registers_30__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1274 (.A1(registers_18__ap[29]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[29]), .ZN(n_1_0_1212)); + SDFF_X1_LVT \registers_reg[17][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_17__ap[29]), .CK(n_0_47), .Q(registers_17__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[12][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_12__ap[29]), .CK(n_0_42), .Q(registers_12__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1273 (.A1(registers_17__ap[29]), .A2(n_1_0_1271), .B1( + n_1_0_1260), .B2(registers_12__ap[29]), .ZN(n_1_0_1211)); + SDFF_X1_LVT \registers_reg[15][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_15__ap[29]), .CK(n_0_45), .Q(registers_15__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[16][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_16__ap[29]), .CK(n_0_46), .Q(registers_16__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1272 (.A1(registers_15__ap[29]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[29]), .ZN(n_1_0_1210)); + NAND3_X1_LVT i_1_0_1271 (.A1(n_1_0_1212), .A2(n_1_0_1211), .A3(n_1_0_1210), + .ZN(n_1_0_1209)); + SDFF_X1_LVT \registers_reg[22][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_22__ap[29]), .CK(n_0_52), .Q(registers_22__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[5][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_5__ap[29]), .CK(n_0_35), .Q(registers_5__ap[29]), .QN()); + AOI221_X1_LVT i_1_0_1270 (.A(n_1_0_1209), .B1(n_1_0_1294), .B2( + registers_22__ap[29]), .C1(registers_5__ap[29]), .C2(n_1_0_1273), .ZN( + n_1_0_1208)); + SDFF_X1_LVT \registers_reg[9][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_9__ap[29]), .CK(n_0_39), .Q(registers_9__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[1][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_1__ap[29]), .CK(n_0_0), .Q(registers_1__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1269 (.A1(registers_9__ap[29]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[29]), .ZN(n_1_0_1207)); + SDFF_X1_LVT \registers_reg[6][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_6__ap[29]), .CK(n_0_36), .Q(registers_6__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[14][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_14__ap[29]), .CK(n_0_44), .Q(registers_14__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1268 (.A1(registers_6__ap[29]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[29]), .ZN(n_1_0_1206)); + SDFF_X1_LVT \registers_reg[27][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_27__ap[29]), .CK(n_0_57), .Q(registers_27__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[11][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_11__ap[29]), .CK(n_0_41), .Q(registers_11__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1267 (.A1(registers_27__ap[29]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[29]), .ZN(n_1_0_1205)); + NAND3_X1_LVT i_1_0_1266 (.A1(n_1_0_1207), .A2(n_1_0_1206), .A3(n_1_0_1205), + .ZN(n_1_0_1204)); + SDFF_X1_LVT \registers_reg[3][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_3__ap[29]), .CK(n_0_33), .Q(registers_3__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[2][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_2__ap[29]), .CK(n_0_32), .Q(registers_2__ap[29]), .QN()); + AOI221_X1_LVT i_1_0_1265 (.A(n_1_0_1204), .B1(n_1_0_1257), .B2( + registers_3__ap[29]), .C1(registers_2__ap[29]), .C2(n_1_0_1268), .ZN( + n_1_0_1203)); + NAND3_X1_LVT i_1_0_1264 (.A1(n_1_0_1213), .A2(n_1_0_1208), .A3(n_1_0_1203), + .ZN(RRs1[29])); + AND2_X1_LVT i_0_0_28 (.A1(n_0_0_16), .A2(WRd[28]), .ZN(registers[28])); + SDFF_X1_LVT \registers_reg[15][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_15__ap[28]), .CK(n_0_45), .Q(registers_15__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[26][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_26__ap[28]), .CK(n_0_56), .Q(registers_26__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[22][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_22__ap[28]), .CK(n_0_52), .Q(registers_22__ap[28]), .QN()); + AOI222_X1_LVT i_1_0_1263 (.A1(registers_15__ap[28]), .A2(n_1_0_1286), + .B1(n_1_0_1285), .B2(registers_26__ap[28]), .C1(registers_22__ap[28]), + .C2(n_1_0_1294), .ZN(n_1_0_1202)); + SDFF_X1_LVT \registers_reg[5][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_5__ap[28]), .CK(n_0_35), .Q(registers_5__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[12][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_12__ap[28]), .CK(n_0_42), .Q(registers_12__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1262 (.A1(registers_5__ap[28]), .A2(n_1_0_1273), .B1( + n_1_0_1260), .B2(registers_12__ap[28]), .ZN(n_1_0_1201)); + SDFF_X1_LVT \registers_reg[28][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_28__ap[28]), .CK(n_0_58), .Q(registers_28__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[14][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_14__ap[28]), .CK(n_0_44), .Q(registers_14__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1261 (.A1(registers_28__ap[28]), .A2(n_1_0_1283), .B1( + n_1_0_1258), .B2(registers_14__ap[28]), .ZN(n_1_0_1200)); + SDFF_X1_LVT \registers_reg[17][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_17__ap[28]), .CK(n_0_47), .Q(registers_17__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[2][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_2__ap[28]), .CK(n_0_32), .Q(registers_2__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1260 (.A1(registers_17__ap[28]), .A2(n_1_0_1271), .B1( + n_1_0_1268), .B2(registers_2__ap[28]), .ZN(n_1_0_1199)); + NAND3_X1_LVT i_1_0_1259 (.A1(n_1_0_1201), .A2(n_1_0_1200), .A3(n_1_0_1199), + .ZN(n_1_0_1198)); + SDFF_X1_LVT \registers_reg[9][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_9__ap[28]), .CK(n_0_39), .Q(registers_9__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[29][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_29__ap[28]), .CK(n_0_59), .Q(registers_29__ap[28]), .QN()); + AOI221_X1_LVT i_1_0_1258 (.A(n_1_0_1198), .B1(n_1_0_1291), .B2( + registers_9__ap[28]), .C1(registers_29__ap[28]), .C2(n_1_0_1276), .ZN( + n_1_0_1197)); + SDFF_X1_LVT \registers_reg[13][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_13__ap[28]), .CK(n_0_43), .Q(registers_13__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[25][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_25__ap[28]), .CK(n_0_55), .Q(registers_25__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1257 (.A1(registers_13__ap[28]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[28]), .ZN(n_1_0_1196)); + NAND3_X1_LVT i_1_0_1256 (.A1(n_1_0_1202), .A2(n_1_0_1197), .A3(n_1_0_1196), + .ZN(n_1_0_1195)); + SDFF_X1_LVT \registers_reg[4][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_4__ap[28]), .CK(n_0_34), .Q(registers_4__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[20][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_20__ap[28]), .CK(n_0_50), .Q(registers_20__ap[28]), .QN()); + AOI221_X1_LVT i_1_0_1255 (.A(n_1_0_1195), .B1(n_1_0_1278), .B2( + registers_4__ap[28]), .C1(registers_20__ap[28]), .C2(n_1_0_1281), .ZN( + n_1_0_1194)); + SDFF_X1_LVT \registers_reg[1][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_1__ap[28]), .CK(n_0_0), .Q(registers_1__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[23][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_23__ap[28]), .CK(n_0_53), .Q(registers_23__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1254 (.A1(registers_1__ap[28]), .A2(n_1_0_1274), .B1( + n_1_0_1264), .B2(registers_23__ap[28]), .ZN(n_1_0_1193)); + SDFF_X1_LVT \registers_reg[10][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_10__ap[28]), .CK(n_0_40), .Q(registers_10__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[21][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_21__ap[28]), .CK(n_0_51), .Q(registers_21__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1253 (.A1(registers_10__ap[28]), .A2(n_1_0_1287), .B1( + n_1_0_1259), .B2(registers_21__ap[28]), .ZN(n_1_0_1192)); + SDFF_X1_LVT \registers_reg[6][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_6__ap[28]), .CK(n_0_36), .Q(registers_6__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[30][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_30__ap[28]), .CK(n_0_60), .Q(registers_30__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1252 (.A1(registers_6__ap[28]), .A2(n_1_0_1300), .B1( + n_1_0_1272), .B2(registers_30__ap[28]), .ZN(n_1_0_1191)); + NAND3_X1_LVT i_1_0_1251 (.A1(n_1_0_1193), .A2(n_1_0_1192), .A3(n_1_0_1191), + .ZN(n_1_0_1190)); + SDFF_X1_LVT \registers_reg[8][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_8__ap[28]), .CK(n_0_38), .Q(registers_8__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[24][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_24__ap[28]), .CK(n_0_54), .Q(registers_24__ap[28]), .QN()); + AOI221_X1_LVT i_1_0_1250 (.A(n_1_0_1190), .B1(n_1_0_1282), .B2( + registers_8__ap[28]), .C1(registers_24__ap[28]), .C2(n_1_0_1289), .ZN( + n_1_0_1189)); + SDFF_X1_LVT \registers_reg[16][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_16__ap[28]), .CK(n_0_46), .Q(registers_16__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[3][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_3__ap[28]), .CK(n_0_33), .Q(registers_3__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1249 (.A1(registers_16__ap[28]), .A2(n_1_0_1267), .B1( + n_1_0_1257), .B2(registers_3__ap[28]), .ZN(n_1_0_1188)); + SDFF_X1_LVT \registers_reg[11][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_11__ap[28]), .CK(n_0_41), .Q(registers_11__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[31][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_31__ap[28]), .CK(n_0_61), .Q(registers_31__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1248 (.A1(registers_11__ap[28]), .A2(n_1_0_1270), .B1( + n_1_0_1266), .B2(registers_31__ap[28]), .ZN(n_1_0_1187)); + SDFF_X1_LVT \registers_reg[27][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_27__ap[28]), .CK(n_0_57), .Q(registers_27__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[7][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_7__ap[28]), .CK(n_0_37), .Q(registers_7__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1247 (.A1(registers_27__ap[28]), .A2(n_1_0_1279), .B1( + n_1_0_1263), .B2(registers_7__ap[28]), .ZN(n_1_0_1186)); + NAND3_X1_LVT i_1_0_1246 (.A1(n_1_0_1188), .A2(n_1_0_1187), .A3(n_1_0_1186), + .ZN(n_1_0_1185)); + SDFF_X1_LVT \registers_reg[19][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_19__ap[28]), .CK(n_0_49), .Q(registers_19__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[18][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_18__ap[28]), .CK(n_0_48), .Q(registers_18__ap[28]), .QN()); + AOI221_X1_LVT i_1_0_1245 (.A(n_1_0_1185), .B1(n_1_0_1295), .B2( + registers_19__ap[28]), .C1(registers_18__ap[28]), .C2(n_1_0_1297), + .ZN(n_1_0_1184)); + NAND3_X1_LVT i_1_0_1244 (.A1(n_1_0_1194), .A2(n_1_0_1189), .A3(n_1_0_1184), + .ZN(RRs1[28])); + AND2_X1_LVT i_0_0_27 (.A1(n_0_0_16), .A2(WRd[27]), .ZN(registers[27])); + SDFF_X1_LVT \registers_reg[29][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_29__ap[27]), .CK(n_0_59), .Q(registers_29__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[2][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_2__ap[27]), .CK(n_0_32), .Q(registers_2__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1242 (.A1(registers_29__ap[27]), .A2(n_1_0_1276), .B1( + n_1_0_1268), .B2(registers_2__ap[27]), .ZN(n_1_0_1182)); + SDFF_X1_LVT \registers_reg[8][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_8__ap[27]), .CK(n_0_38), .Q(registers_8__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[25][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_25__ap[27]), .CK(n_0_55), .Q(registers_25__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1243 (.A1(registers_8__ap[27]), .A2(n_1_0_1282), .B1( + n_1_0_1269), .B2(registers_25__ap[27]), .ZN(n_1_0_1183)); + SDFF_X1_LVT \registers_reg[9][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_9__ap[27]), .CK(n_0_39), .Q(registers_9__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[7][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_7__ap[27]), .CK(n_0_37), .Q(registers_7__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1241 (.A1(registers_9__ap[27]), .A2(n_1_0_1291), .B1( + n_1_0_1263), .B2(registers_7__ap[27]), .ZN(n_1_0_1181)); + SDFF_X1_LVT \registers_reg[11][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_11__ap[27]), .CK(n_0_41), .Q(registers_11__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[16][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_16__ap[27]), .CK(n_0_46), .Q(registers_16__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1240 (.A1(registers_11__ap[27]), .A2(n_1_0_1270), .B1( + n_1_0_1267), .B2(registers_16__ap[27]), .ZN(n_1_0_1180)); + NAND3_X1_LVT i_1_0_1239 (.A1(n_1_0_1183), .A2(n_1_0_1181), .A3(n_1_0_1180), + .ZN(n_1_0_1179)); + SDFF_X1_LVT \registers_reg[10][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_10__ap[27]), .CK(n_0_40), .Q(registers_10__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[6][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_6__ap[27]), .CK(n_0_36), .Q(registers_6__ap[27]), .QN()); + AOI221_X1_LVT i_1_0_1238 (.A(n_1_0_1179), .B1(n_1_0_1287), .B2( + registers_10__ap[27]), .C1(registers_6__ap[27]), .C2(n_1_0_1300), .ZN( + n_1_0_1178)); + SDFF_X1_LVT \registers_reg[1][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_1__ap[27]), .CK(n_0_0), .Q(registers_1__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[30][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_30__ap[27]), .CK(n_0_60), .Q(registers_30__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[22][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_22__ap[27]), .CK(n_0_52), .Q(registers_22__ap[27]), .QN()); + AOI222_X1_LVT i_1_0_1237 (.A1(registers_1__ap[27]), .A2(n_1_0_1274), .B1( + n_1_0_1272), .B2(registers_30__ap[27]), .C1(registers_22__ap[27]), + .C2(n_1_0_1294), .ZN(n_1_0_1177)); + NAND3_X1_LVT i_1_0_1236 (.A1(n_1_0_1182), .A2(n_1_0_1178), .A3(n_1_0_1177), + .ZN(n_1_0_1176)); + SDFF_X1_LVT \registers_reg[5][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_5__ap[27]), .CK(n_0_35), .Q(registers_5__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[28][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_28__ap[27]), .CK(n_0_58), .Q(registers_28__ap[27]), .QN()); + AOI221_X1_LVT i_1_0_1235 (.A(n_1_0_1176), .B1(n_1_0_1273), .B2( + registers_5__ap[27]), .C1(registers_28__ap[27]), .C2(n_1_0_1283), .ZN( + n_1_0_1175)); + SDFF_X1_LVT \registers_reg[4][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_4__ap[27]), .CK(n_0_34), .Q(registers_4__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[12][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_12__ap[27]), .CK(n_0_42), .Q(registers_12__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1234 (.A1(registers_4__ap[27]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[27]), .ZN(n_1_0_1174)); + SDFF_X1_LVT \registers_reg[19][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_19__ap[27]), .CK(n_0_49), .Q(registers_19__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[21][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_21__ap[27]), .CK(n_0_51), .Q(registers_21__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1233 (.A1(registers_19__ap[27]), .A2(n_1_0_1295), .B1( + n_1_0_1259), .B2(registers_21__ap[27]), .ZN(n_1_0_1173)); + SDFF_X1_LVT \registers_reg[24][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_24__ap[27]), .CK(n_0_54), .Q(registers_24__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[20][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_20__ap[27]), .CK(n_0_50), .Q(registers_20__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1232 (.A1(registers_24__ap[27]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[27]), .ZN(n_1_0_1172)); + NAND3_X1_LVT i_1_0_1231 (.A1(n_1_0_1174), .A2(n_1_0_1173), .A3(n_1_0_1172), + .ZN(n_1_0_1171)); + SDFF_X1_LVT \registers_reg[18][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_18__ap[27]), .CK(n_0_48), .Q(registers_18__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[26][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_26__ap[27]), .CK(n_0_56), .Q(registers_26__ap[27]), .QN()); + AOI221_X1_LVT i_1_0_1230 (.A(n_1_0_1171), .B1(n_1_0_1297), .B2( + registers_18__ap[27]), .C1(registers_26__ap[27]), .C2(n_1_0_1285), + .ZN(n_1_0_1170)); + SDFF_X1_LVT \registers_reg[23][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_23__ap[27]), .CK(n_0_53), .Q(registers_23__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[3][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_3__ap[27]), .CK(n_0_33), .Q(registers_3__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1229 (.A1(registers_23__ap[27]), .A2(n_1_0_1264), .B1( + n_1_0_1257), .B2(registers_3__ap[27]), .ZN(n_1_0_1169)); + SDFF_X1_LVT \registers_reg[13][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_13__ap[27]), .CK(n_0_43), .Q(registers_13__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[17][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_17__ap[27]), .CK(n_0_47), .Q(registers_17__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1228 (.A1(registers_13__ap[27]), .A2(n_1_0_1277), .B1( + n_1_0_1271), .B2(registers_17__ap[27]), .ZN(n_1_0_1168)); + SDFF_X1_LVT \registers_reg[15][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_15__ap[27]), .CK(n_0_45), .Q(registers_15__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[14][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_14__ap[27]), .CK(n_0_44), .Q(registers_14__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1227 (.A1(registers_15__ap[27]), .A2(n_1_0_1286), .B1( + n_1_0_1258), .B2(registers_14__ap[27]), .ZN(n_1_0_1167)); + NAND3_X1_LVT i_1_0_1226 (.A1(n_1_0_1169), .A2(n_1_0_1168), .A3(n_1_0_1167), + .ZN(n_1_0_1166)); + SDFF_X1_LVT \registers_reg[27][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_27__ap[27]), .CK(n_0_57), .Q(registers_27__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[31][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_31__ap[27]), .CK(n_0_61), .Q(registers_31__ap[27]), .QN()); + AOI221_X1_LVT i_1_0_1225 (.A(n_1_0_1166), .B1(n_1_0_1279), .B2( + registers_27__ap[27]), .C1(registers_31__ap[27]), .C2(n_1_0_1266), + .ZN(n_1_0_1165)); + NAND3_X1_LVT i_1_0_1224 (.A1(n_1_0_1175), .A2(n_1_0_1170), .A3(n_1_0_1165), + .ZN(RRs1[27])); + AND2_X1_LVT i_0_0_26 (.A1(n_0_0_16), .A2(WRd[26]), .ZN(registers[26])); + SDFF_X1_LVT \registers_reg[18][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_18__ap[26]), .CK(n_0_48), .Q(registers_18__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[22][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_22__ap[26]), .CK(n_0_52), .Q(registers_22__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[1][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_1__ap[26]), .CK(n_0_0), .Q(registers_1__ap[26]), .QN()); + AOI222_X1_LVT i_1_0_1223 (.A1(registers_18__ap[26]), .A2(n_1_0_1297), + .B1(n_1_0_1294), .B2(registers_22__ap[26]), .C1(registers_1__ap[26]), + .C2(n_1_0_1274), .ZN(n_1_0_1164)); + SDFF_X1_LVT \registers_reg[29][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_29__ap[26]), .CK(n_0_59), .Q(registers_29__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[2][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_2__ap[26]), .CK(n_0_32), .Q(registers_2__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1222 (.A1(registers_29__ap[26]), .A2(n_1_0_1276), .B1( + n_1_0_1268), .B2(registers_2__ap[26]), .ZN(n_1_0_1163)); + SDFF_X1_LVT \registers_reg[9][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_9__ap[26]), .CK(n_0_39), .Q(registers_9__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[7][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_7__ap[26]), .CK(n_0_37), .Q(registers_7__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1221 (.A1(registers_9__ap[26]), .A2(n_1_0_1291), .B1( + n_1_0_1263), .B2(registers_7__ap[26]), .ZN(n_1_0_1162)); + SDFF_X1_LVT \registers_reg[11][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_11__ap[26]), .CK(n_0_41), .Q(registers_11__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[25][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_25__ap[26]), .CK(n_0_55), .Q(registers_25__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1220 (.A1(registers_11__ap[26]), .A2(n_1_0_1270), .B1( + n_1_0_1269), .B2(registers_25__ap[26]), .ZN(n_1_0_1161)); + SDFF_X1_LVT \registers_reg[27][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_27__ap[26]), .CK(n_0_57), .Q(registers_27__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[16][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_16__ap[26]), .CK(n_0_46), .Q(registers_16__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1219 (.A1(registers_27__ap[26]), .A2(n_1_0_1279), .B1( + n_1_0_1267), .B2(registers_16__ap[26]), .ZN(n_1_0_1160)); + NAND3_X1_LVT i_1_0_1218 (.A1(n_1_0_1162), .A2(n_1_0_1161), .A3(n_1_0_1160), + .ZN(n_1_0_1159)); + SDFF_X1_LVT \registers_reg[31][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_31__ap[26]), .CK(n_0_61), .Q(registers_31__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[6][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_6__ap[26]), .CK(n_0_36), .Q(registers_6__ap[26]), .QN()); + AOI221_X1_LVT i_1_0_1217 (.A(n_1_0_1159), .B1(n_1_0_1266), .B2( + registers_31__ap[26]), .C1(registers_6__ap[26]), .C2(n_1_0_1300), .ZN( + n_1_0_1158)); + NAND3_X1_LVT i_1_0_1216 (.A1(n_1_0_1164), .A2(n_1_0_1163), .A3(n_1_0_1158), + .ZN(n_1_0_1157)); + SDFF_X1_LVT \registers_reg[5][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_5__ap[26]), .CK(n_0_35), .Q(registers_5__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[28][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_28__ap[26]), .CK(n_0_58), .Q(registers_28__ap[26]), .QN()); + AOI221_X1_LVT i_1_0_1215 (.A(n_1_0_1157), .B1(n_1_0_1273), .B2( + registers_5__ap[26]), .C1(registers_28__ap[26]), .C2(n_1_0_1283), .ZN( + n_1_0_1156)); + SDFF_X1_LVT \registers_reg[4][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_4__ap[26]), .CK(n_0_34), .Q(registers_4__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[12][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_12__ap[26]), .CK(n_0_42), .Q(registers_12__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1214 (.A1(registers_4__ap[26]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[26]), .ZN(n_1_0_1155)); + SDFF_X1_LVT \registers_reg[19][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_19__ap[26]), .CK(n_0_49), .Q(registers_19__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[21][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_21__ap[26]), .CK(n_0_51), .Q(registers_21__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1213 (.A1(registers_19__ap[26]), .A2(n_1_0_1295), .B1( + n_1_0_1259), .B2(registers_21__ap[26]), .ZN(n_1_0_1154)); + SDFF_X1_LVT \registers_reg[24][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_24__ap[26]), .CK(n_0_54), .Q(registers_24__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[20][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_20__ap[26]), .CK(n_0_50), .Q(registers_20__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1212 (.A1(registers_24__ap[26]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[26]), .ZN(n_1_0_1153)); + NAND3_X1_LVT i_1_0_1211 (.A1(n_1_0_1155), .A2(n_1_0_1154), .A3(n_1_0_1153), + .ZN(n_1_0_1152)); + SDFF_X1_LVT \registers_reg[26][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_26__ap[26]), .CK(n_0_56), .Q(registers_26__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[30][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_30__ap[26]), .CK(n_0_60), .Q(registers_30__ap[26]), .QN()); + AOI221_X1_LVT i_1_0_1210 (.A(n_1_0_1152), .B1(n_1_0_1285), .B2( + registers_26__ap[26]), .C1(registers_30__ap[26]), .C2(n_1_0_1272), + .ZN(n_1_0_1151)); + SDFF_X1_LVT \registers_reg[8][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_8__ap[26]), .CK(n_0_38), .Q(registers_8__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[23][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_23__ap[26]), .CK(n_0_53), .Q(registers_23__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1209 (.A1(registers_8__ap[26]), .A2(n_1_0_1282), .B1( + n_1_0_1264), .B2(registers_23__ap[26]), .ZN(n_1_0_1150)); + SDFF_X1_LVT \registers_reg[13][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_13__ap[26]), .CK(n_0_43), .Q(registers_13__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[17][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_17__ap[26]), .CK(n_0_47), .Q(registers_17__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1208 (.A1(registers_13__ap[26]), .A2(n_1_0_1277), .B1( + n_1_0_1271), .B2(registers_17__ap[26]), .ZN(n_1_0_1149)); + SDFF_X1_LVT \registers_reg[15][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_15__ap[26]), .CK(n_0_45), .Q(registers_15__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[14][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_14__ap[26]), .CK(n_0_44), .Q(registers_14__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1207 (.A1(registers_15__ap[26]), .A2(n_1_0_1286), .B1( + n_1_0_1258), .B2(registers_14__ap[26]), .ZN(n_1_0_1148)); + NAND3_X1_LVT i_1_0_1206 (.A1(n_1_0_1150), .A2(n_1_0_1149), .A3(n_1_0_1148), + .ZN(n_1_0_1147)); + SDFF_X1_LVT \registers_reg[10][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_10__ap[26]), .CK(n_0_40), .Q(registers_10__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[3][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_3__ap[26]), .CK(n_0_33), .Q(registers_3__ap[26]), .QN()); + AOI221_X1_LVT i_1_0_1205 (.A(n_1_0_1147), .B1(n_1_0_1287), .B2( + registers_10__ap[26]), .C1(registers_3__ap[26]), .C2(n_1_0_1257), .ZN( + n_1_0_1146)); + NAND3_X1_LVT i_1_0_1204 (.A1(n_1_0_1156), .A2(n_1_0_1151), .A3(n_1_0_1146), + .ZN(RRs1[26])); + AND2_X1_LVT i_0_0_25 (.A1(n_0_0_16), .A2(WRd[25]), .ZN(registers[25])); + SDFF_X1_LVT \registers_reg[17][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_17__ap[25]), .CK(n_0_47), .Q(registers_17__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[21][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_21__ap[25]), .CK(n_0_51), .Q(registers_21__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1202 (.A1(registers_17__ap[25]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[25]), .ZN(n_1_0_1144)); + SDFF_X1_LVT \registers_reg[6][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_6__ap[25]), .CK(n_0_36), .Q(registers_6__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[8][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_8__ap[25]), .CK(n_0_38), .Q(registers_8__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1203 (.A1(registers_6__ap[25]), .A2(n_1_0_1300), .B1( + n_1_0_1282), .B2(registers_8__ap[25]), .ZN(n_1_0_1145)); + SDFF_X1_LVT \registers_reg[20][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_20__ap[25]), .CK(n_0_50), .Q(registers_20__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[12][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_12__ap[25]), .CK(n_0_42), .Q(registers_12__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1201 (.A1(registers_20__ap[25]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[25]), .ZN(n_1_0_1143)); + SDFF_X1_LVT \registers_reg[5][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_5__ap[25]), .CK(n_0_35), .Q(registers_5__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[11][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_11__ap[25]), .CK(n_0_41), .Q(registers_11__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1200 (.A1(registers_5__ap[25]), .A2(n_1_0_1273), .B1( + n_1_0_1270), .B2(registers_11__ap[25]), .ZN(n_1_0_1142)); + NAND3_X1_LVT i_1_0_1199 (.A1(n_1_0_1145), .A2(n_1_0_1143), .A3(n_1_0_1142), + .ZN(n_1_0_1141)); + SDFF_X1_LVT \registers_reg[10][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_10__ap[25]), .CK(n_0_40), .Q(registers_10__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[2][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_2__ap[25]), .CK(n_0_32), .Q(registers_2__ap[25]), .QN()); + AOI221_X1_LVT i_1_0_1198 (.A(n_1_0_1141), .B1(n_1_0_1287), .B2( + registers_10__ap[25]), .C1(registers_2__ap[25]), .C2(n_1_0_1268), .ZN( + n_1_0_1140)); + SDFF_X1_LVT \registers_reg[13][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_13__ap[25]), .CK(n_0_43), .Q(registers_13__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[30][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_30__ap[25]), .CK(n_0_60), .Q(registers_30__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[22][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_22__ap[25]), .CK(n_0_52), .Q(registers_22__ap[25]), .QN()); + AOI222_X1_LVT i_1_0_1197 (.A1(registers_13__ap[25]), .A2(n_1_0_1277), + .B1(n_1_0_1272), .B2(registers_30__ap[25]), .C1(registers_22__ap[25]), + .C2(n_1_0_1294), .ZN(n_1_0_1139)); + NAND2_X1_LVT i_1_0_1196 (.A1(n_1_0_1140), .A2(n_1_0_1139), .ZN(n_1_0_1138)); + SDFF_X1_LVT \registers_reg[1][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_1__ap[25]), .CK(n_0_0), .Q(registers_1__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[28][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_28__ap[25]), .CK(n_0_58), .Q(registers_28__ap[25]), .QN()); + AOI221_X1_LVT i_1_0_1195 (.A(n_1_0_1138), .B1(n_1_0_1274), .B2( + registers_1__ap[25]), .C1(registers_28__ap[25]), .C2(n_1_0_1283), .ZN( + n_1_0_1137)); + SDFF_X1_LVT \registers_reg[18][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_18__ap[25]), .CK(n_0_48), .Q(registers_18__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[26][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_26__ap[25]), .CK(n_0_56), .Q(registers_26__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1194 (.A1(registers_18__ap[25]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[25]), .ZN(n_1_0_1136)); + SDFF_X1_LVT \registers_reg[24][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_24__ap[25]), .CK(n_0_54), .Q(registers_24__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[4][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_4__ap[25]), .CK(n_0_34), .Q(registers_4__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1193 (.A1(registers_24__ap[25]), .A2(n_1_0_1289), .B1( + n_1_0_1278), .B2(registers_4__ap[25]), .ZN(n_1_0_1135)); + SDFF_X1_LVT \registers_reg[15][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_15__ap[25]), .CK(n_0_45), .Q(registers_15__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[16][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_16__ap[25]), .CK(n_0_46), .Q(registers_16__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1192 (.A1(registers_15__ap[25]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[25]), .ZN(n_1_0_1134)); + NAND3_X1_LVT i_1_0_1191 (.A1(n_1_0_1136), .A2(n_1_0_1135), .A3(n_1_0_1134), + .ZN(n_1_0_1133)); + SDFF_X1_LVT \registers_reg[19][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_19__ap[25]), .CK(n_0_49), .Q(registers_19__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[25][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_25__ap[25]), .CK(n_0_55), .Q(registers_25__ap[25]), .QN()); + AOI221_X1_LVT i_1_0_1190 (.A(n_1_0_1133), .B1(n_1_0_1295), .B2( + registers_19__ap[25]), .C1(registers_25__ap[25]), .C2(n_1_0_1269), + .ZN(n_1_0_1132)); + SDFF_X1_LVT \registers_reg[7][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_7__ap[25]), .CK(n_0_37), .Q(registers_7__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[14][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_14__ap[25]), .CK(n_0_44), .Q(registers_14__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1189 (.A1(registers_7__ap[25]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[25]), .ZN(n_1_0_1131)); + SDFF_X1_LVT \registers_reg[9][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_9__ap[25]), .CK(n_0_39), .Q(registers_9__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[29][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_29__ap[25]), .CK(n_0_59), .Q(registers_29__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1188 (.A1(registers_9__ap[25]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[25]), .ZN(n_1_0_1130)); + SDFF_X1_LVT \registers_reg[23][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_23__ap[25]), .CK(n_0_53), .Q(registers_23__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[3][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_3__ap[25]), .CK(n_0_33), .Q(registers_3__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1187 (.A1(registers_23__ap[25]), .A2(n_1_0_1264), .B1( + n_1_0_1257), .B2(registers_3__ap[25]), .ZN(n_1_0_1129)); + NAND3_X1_LVT i_1_0_1186 (.A1(n_1_0_1131), .A2(n_1_0_1130), .A3(n_1_0_1129), + .ZN(n_1_0_1128)); + SDFF_X1_LVT \registers_reg[27][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_27__ap[25]), .CK(n_0_57), .Q(registers_27__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[31][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_31__ap[25]), .CK(n_0_61), .Q(registers_31__ap[25]), .QN()); + AOI221_X1_LVT i_1_0_1185 (.A(n_1_0_1128), .B1(n_1_0_1279), .B2( + registers_27__ap[25]), .C1(registers_31__ap[25]), .C2(n_1_0_1266), + .ZN(n_1_0_1127)); + NAND4_X1_LVT i_1_0_1184 (.A1(n_1_0_1144), .A2(n_1_0_1137), .A3(n_1_0_1132), + .A4(n_1_0_1127), .ZN(RRs1[25])); + AND2_X1_LVT i_0_0_24 (.A1(n_0_0_16), .A2(WRd[24]), .ZN(registers[24])); + SDFF_X1_LVT \registers_reg[17][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_17__ap[24]), .CK(n_0_47), .Q(registers_17__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[21][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_21__ap[24]), .CK(n_0_51), .Q(registers_21__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1182 (.A1(registers_17__ap[24]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[24]), .ZN(n_1_0_1125)); + SDFF_X1_LVT \registers_reg[6][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_6__ap[24]), .CK(n_0_36), .Q(registers_6__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[8][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_8__ap[24]), .CK(n_0_38), .Q(registers_8__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1183 (.A1(registers_6__ap[24]), .A2(n_1_0_1300), .B1( + n_1_0_1282), .B2(registers_8__ap[24]), .ZN(n_1_0_1126)); + SDFF_X1_LVT \registers_reg[20][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_20__ap[24]), .CK(n_0_50), .Q(registers_20__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[12][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_12__ap[24]), .CK(n_0_42), .Q(registers_12__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1181 (.A1(registers_20__ap[24]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[24]), .ZN(n_1_0_1124)); + SDFF_X1_LVT \registers_reg[5][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_5__ap[24]), .CK(n_0_35), .Q(registers_5__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[11][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_11__ap[24]), .CK(n_0_41), .Q(registers_11__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1180 (.A1(registers_5__ap[24]), .A2(n_1_0_1273), .B1( + n_1_0_1270), .B2(registers_11__ap[24]), .ZN(n_1_0_1123)); + NAND3_X1_LVT i_1_0_1179 (.A1(n_1_0_1126), .A2(n_1_0_1124), .A3(n_1_0_1123), + .ZN(n_1_0_1122)); + SDFF_X1_LVT \registers_reg[10][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_10__ap[24]), .CK(n_0_40), .Q(registers_10__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[2][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_2__ap[24]), .CK(n_0_32), .Q(registers_2__ap[24]), .QN()); + AOI221_X1_LVT i_1_0_1178 (.A(n_1_0_1122), .B1(n_1_0_1287), .B2( + registers_10__ap[24]), .C1(registers_2__ap[24]), .C2(n_1_0_1268), .ZN( + n_1_0_1121)); + SDFF_X1_LVT \registers_reg[13][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_13__ap[24]), .CK(n_0_43), .Q(registers_13__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[30][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_30__ap[24]), .CK(n_0_60), .Q(registers_30__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[22][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_22__ap[24]), .CK(n_0_52), .Q(registers_22__ap[24]), .QN()); + AOI222_X1_LVT i_1_0_1177 (.A1(registers_13__ap[24]), .A2(n_1_0_1277), + .B1(n_1_0_1272), .B2(registers_30__ap[24]), .C1(registers_22__ap[24]), + .C2(n_1_0_1294), .ZN(n_1_0_1120)); + NAND2_X1_LVT i_1_0_1176 (.A1(n_1_0_1121), .A2(n_1_0_1120), .ZN(n_1_0_1119)); + SDFF_X1_LVT \registers_reg[1][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_1__ap[24]), .CK(n_0_0), .Q(registers_1__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[28][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_28__ap[24]), .CK(n_0_58), .Q(registers_28__ap[24]), .QN()); + AOI221_X1_LVT i_1_0_1175 (.A(n_1_0_1119), .B1(n_1_0_1274), .B2( + registers_1__ap[24]), .C1(registers_28__ap[24]), .C2(n_1_0_1283), .ZN( + n_1_0_1118)); + SDFF_X1_LVT \registers_reg[18][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_18__ap[24]), .CK(n_0_48), .Q(registers_18__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[26][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_26__ap[24]), .CK(n_0_56), .Q(registers_26__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1174 (.A1(registers_18__ap[24]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[24]), .ZN(n_1_0_1117)); + SDFF_X1_LVT \registers_reg[24][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_24__ap[24]), .CK(n_0_54), .Q(registers_24__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[4][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_4__ap[24]), .CK(n_0_34), .Q(registers_4__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1173 (.A1(registers_24__ap[24]), .A2(n_1_0_1289), .B1( + n_1_0_1278), .B2(registers_4__ap[24]), .ZN(n_1_0_1116)); + SDFF_X1_LVT \registers_reg[15][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_15__ap[24]), .CK(n_0_45), .Q(registers_15__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[25][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_25__ap[24]), .CK(n_0_55), .Q(registers_25__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1172 (.A1(registers_15__ap[24]), .A2(n_1_0_1286), .B1( + n_1_0_1269), .B2(registers_25__ap[24]), .ZN(n_1_0_1115)); + NAND3_X1_LVT i_1_0_1171 (.A1(n_1_0_1117), .A2(n_1_0_1116), .A3(n_1_0_1115), + .ZN(n_1_0_1114)); + SDFF_X1_LVT \registers_reg[19][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_19__ap[24]), .CK(n_0_49), .Q(registers_19__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[16][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_16__ap[24]), .CK(n_0_46), .Q(registers_16__ap[24]), .QN()); + AOI221_X1_LVT i_1_0_1170 (.A(n_1_0_1114), .B1(n_1_0_1295), .B2( + registers_19__ap[24]), .C1(registers_16__ap[24]), .C2(n_1_0_1267), + .ZN(n_1_0_1113)); + SDFF_X1_LVT \registers_reg[7][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_7__ap[24]), .CK(n_0_37), .Q(registers_7__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[14][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_14__ap[24]), .CK(n_0_44), .Q(registers_14__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1169 (.A1(registers_7__ap[24]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[24]), .ZN(n_1_0_1112)); + SDFF_X1_LVT \registers_reg[9][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_9__ap[24]), .CK(n_0_39), .Q(registers_9__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[29][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_29__ap[24]), .CK(n_0_59), .Q(registers_29__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1168 (.A1(registers_9__ap[24]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[24]), .ZN(n_1_0_1111)); + SDFF_X1_LVT \registers_reg[23][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_23__ap[24]), .CK(n_0_53), .Q(registers_23__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[3][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_3__ap[24]), .CK(n_0_33), .Q(registers_3__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1167 (.A1(registers_23__ap[24]), .A2(n_1_0_1264), .B1( + n_1_0_1257), .B2(registers_3__ap[24]), .ZN(n_1_0_1110)); + NAND3_X1_LVT i_1_0_1166 (.A1(n_1_0_1112), .A2(n_1_0_1111), .A3(n_1_0_1110), + .ZN(n_1_0_1109)); + SDFF_X1_LVT \registers_reg[27][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_27__ap[24]), .CK(n_0_57), .Q(registers_27__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[31][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_31__ap[24]), .CK(n_0_61), .Q(registers_31__ap[24]), .QN()); + AOI221_X1_LVT i_1_0_1165 (.A(n_1_0_1109), .B1(n_1_0_1279), .B2( + registers_27__ap[24]), .C1(registers_31__ap[24]), .C2(n_1_0_1266), + .ZN(n_1_0_1108)); + NAND4_X1_LVT i_1_0_1164 (.A1(n_1_0_1125), .A2(n_1_0_1118), .A3(n_1_0_1113), + .A4(n_1_0_1108), .ZN(RRs1[24])); + AND2_X1_LVT i_0_0_23 (.A1(n_0_0_16), .A2(WRd[23]), .ZN(registers[23])); + SDFF_X1_LVT \registers_reg[9][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_9__ap[23]), .CK(n_0_39), .Q(registers_9__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[28][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_28__ap[23]), .CK(n_0_58), .Q(registers_28__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1163 (.A1(registers_9__ap[23]), .A2(n_1_0_1291), .B1( + n_1_0_1283), .B2(registers_28__ap[23]), .ZN(n_1_0_1107)); + SDFF_X1_LVT \registers_reg[18][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_18__ap[23]), .CK(n_0_48), .Q(registers_18__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[22][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_22__ap[23]), .CK(n_0_52), .Q(registers_22__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1160 (.A1(registers_18__ap[23]), .A2(n_1_0_1297), .B1( + n_1_0_1294), .B2(registers_22__ap[23]), .ZN(n_1_0_1104)); + SDFF_X1_LVT \registers_reg[1][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_1__ap[23]), .CK(n_0_0), .Q(registers_1__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[21][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_21__ap[23]), .CK(n_0_51), .Q(registers_21__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1159 (.A1(registers_1__ap[23]), .A2(n_1_0_1274), .B1( + n_1_0_1259), .B2(registers_21__ap[23]), .ZN(n_1_0_1103)); + NAND3_X1_LVT i_1_0_1157 (.A1(n_1_0_1107), .A2(n_1_0_1104), .A3(n_1_0_1103), + .ZN(n_1_0_1101)); + SDFF_X1_LVT \registers_reg[20][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_20__ap[23]), .CK(n_0_50), .Q(registers_20__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[19][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_19__ap[23]), .CK(n_0_49), .Q(registers_19__ap[23]), .QN()); + AOI221_X1_LVT i_1_0_1156 (.A(n_1_0_1101), .B1(n_1_0_1281), .B2( + registers_20__ap[23]), .C1(registers_19__ap[23]), .C2(n_1_0_1295), + .ZN(n_1_0_1100)); + SDFF_X1_LVT \registers_reg[26][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_26__ap[23]), .CK(n_0_56), .Q(registers_26__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[23][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_23__ap[23]), .CK(n_0_53), .Q(registers_23__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1162 (.A1(registers_26__ap[23]), .A2(n_1_0_1285), .B1( + n_1_0_1264), .B2(registers_23__ap[23]), .ZN(n_1_0_1106)); + SDFF_X1_LVT \registers_reg[29][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_29__ap[23]), .CK(n_0_59), .Q(registers_29__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[3][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_3__ap[23]), .CK(n_0_33), .Q(registers_3__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1161 (.A1(registers_29__ap[23]), .A2(n_1_0_1276), .B1( + n_1_0_1257), .B2(registers_3__ap[23]), .ZN(n_1_0_1105)); + SDFF_X1_LVT \registers_reg[30][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_30__ap[23]), .CK(n_0_60), .Q(registers_30__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[31][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_31__ap[23]), .CK(n_0_61), .Q(registers_31__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1158 (.A1(registers_30__ap[23]), .A2(n_1_0_1272), .B1( + n_1_0_1266), .B2(registers_31__ap[23]), .ZN(n_1_0_1102)); + NAND3_X1_LVT i_1_0_1155 (.A1(n_1_0_1106), .A2(n_1_0_1105), .A3(n_1_0_1102), + .ZN(n_1_0_1099)); + SDFF_X1_LVT \registers_reg[8][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_8__ap[23]), .CK(n_0_38), .Q(registers_8__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[17][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_17__ap[23]), .CK(n_0_47), .Q(registers_17__ap[23]), .QN()); + AOI221_X1_LVT i_1_0_1154 (.A(n_1_0_1099), .B1(n_1_0_1282), .B2( + registers_8__ap[23]), .C1(registers_17__ap[23]), .C2(n_1_0_1271), .ZN( + n_1_0_1098)); + SDFF_X1_LVT \registers_reg[24][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_24__ap[23]), .CK(n_0_54), .Q(registers_24__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[15][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_15__ap[23]), .CK(n_0_45), .Q(registers_15__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[14][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_14__ap[23]), .CK(n_0_44), .Q(registers_14__ap[23]), .QN()); + AOI222_X1_LVT i_1_0_1153 (.A1(registers_24__ap[23]), .A2(n_1_0_1289), + .B1(n_1_0_1286), .B2(registers_15__ap[23]), .C1(n_1_0_1258), .C2( + registers_14__ap[23]), .ZN(n_1_0_1097)); + SDFF_X1_LVT \registers_reg[16][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_16__ap[23]), .CK(n_0_46), .Q(registers_16__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[7][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_7__ap[23]), .CK(n_0_37), .Q(registers_7__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1152 (.A1(registers_16__ap[23]), .A2(n_1_0_1267), .B1( + n_1_0_1263), .B2(registers_7__ap[23]), .ZN(n_1_0_1096)); + SDFF_X1_LVT \registers_reg[6][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_6__ap[23]), .CK(n_0_36), .Q(registers_6__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[25][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_25__ap[23]), .CK(n_0_55), .Q(registers_25__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1151 (.A1(registers_6__ap[23]), .A2(n_1_0_1300), .B1( + n_1_0_1269), .B2(registers_25__ap[23]), .ZN(n_1_0_1095)); + SDFF_X1_LVT \registers_reg[27][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_27__ap[23]), .CK(n_0_57), .Q(registers_27__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[11][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_11__ap[23]), .CK(n_0_41), .Q(registers_11__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1150 (.A1(registers_27__ap[23]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[23]), .ZN(n_1_0_1094)); + SDFF_X1_LVT \registers_reg[13][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_13__ap[23]), .CK(n_0_43), .Q(registers_13__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[5][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_5__ap[23]), .CK(n_0_35), .Q(registers_5__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1149 (.A1(registers_13__ap[23]), .A2(n_1_0_1277), .B1( + n_1_0_1273), .B2(registers_5__ap[23]), .ZN(n_1_0_1093)); + SDFF_X1_LVT \registers_reg[4][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_4__ap[23]), .CK(n_0_34), .Q(registers_4__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[12][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_12__ap[23]), .CK(n_0_42), .Q(registers_12__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1148 (.A1(registers_4__ap[23]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[23]), .ZN(n_1_0_1092)); + NAND3_X1_LVT i_1_0_1147 (.A1(n_1_0_1094), .A2(n_1_0_1093), .A3(n_1_0_1092), + .ZN(n_1_0_1091)); + SDFF_X1_LVT \registers_reg[2][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_2__ap[23]), .CK(n_0_32), .Q(registers_2__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[10][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_10__ap[23]), .CK(n_0_40), .Q(registers_10__ap[23]), .QN()); + AOI221_X1_LVT i_1_0_1146 (.A(n_1_0_1091), .B1(n_1_0_1268), .B2( + registers_2__ap[23]), .C1(registers_10__ap[23]), .C2(n_1_0_1287), .ZN( + n_1_0_1090)); + AND4_X1_LVT i_1_0_1145 (.A1(n_1_0_1097), .A2(n_1_0_1096), .A3(n_1_0_1095), + .A4(n_1_0_1090), .ZN(n_1_0_1089)); + NAND3_X1_LVT i_1_0_1144 (.A1(n_1_0_1100), .A2(n_1_0_1098), .A3(n_1_0_1089), + .ZN(RRs1[23])); + AND2_X1_LVT i_0_0_22 (.A1(n_0_0_16), .A2(WRd[22]), .ZN(registers[22])); + SDFF_X1_LVT \registers_reg[17][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_17__ap[22]), .CK(n_0_47), .Q(registers_17__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[21][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_21__ap[22]), .CK(n_0_51), .Q(registers_21__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1142 (.A1(registers_17__ap[22]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[22]), .ZN(n_1_0_1087)); + SDFF_X1_LVT \registers_reg[6][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_6__ap[22]), .CK(n_0_36), .Q(registers_6__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[11][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_11__ap[22]), .CK(n_0_41), .Q(registers_11__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1143 (.A1(registers_6__ap[22]), .A2(n_1_0_1300), .B1( + n_1_0_1270), .B2(registers_11__ap[22]), .ZN(n_1_0_1088)); + SDFF_X1_LVT \registers_reg[20][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_20__ap[22]), .CK(n_0_50), .Q(registers_20__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[12][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_12__ap[22]), .CK(n_0_42), .Q(registers_12__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1141 (.A1(registers_20__ap[22]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[22]), .ZN(n_1_0_1086)); + SDFF_X1_LVT \registers_reg[10][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_10__ap[22]), .CK(n_0_40), .Q(registers_10__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[5][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_5__ap[22]), .CK(n_0_35), .Q(registers_5__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1140 (.A1(registers_10__ap[22]), .A2(n_1_0_1287), .B1( + n_1_0_1273), .B2(registers_5__ap[22]), .ZN(n_1_0_1085)); + NAND3_X1_LVT i_1_0_1139 (.A1(n_1_0_1088), .A2(n_1_0_1086), .A3(n_1_0_1085), + .ZN(n_1_0_1084)); + SDFF_X1_LVT \registers_reg[31][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_31__ap[22]), .CK(n_0_61), .Q(registers_31__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[2][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_2__ap[22]), .CK(n_0_32), .Q(registers_2__ap[22]), .QN()); + AOI221_X1_LVT i_1_0_1138 (.A(n_1_0_1084), .B1(n_1_0_1266), .B2( + registers_31__ap[22]), .C1(registers_2__ap[22]), .C2(n_1_0_1268), .ZN( + n_1_0_1083)); + SDFF_X1_LVT \registers_reg[22][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_22__ap[22]), .CK(n_0_52), .Q(registers_22__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[26][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_26__ap[22]), .CK(n_0_56), .Q(registers_26__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[13][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_13__ap[22]), .CK(n_0_43), .Q(registers_13__ap[22]), .QN()); + AOI222_X1_LVT i_1_0_1137 (.A1(registers_22__ap[22]), .A2(n_1_0_1294), + .B1(n_1_0_1285), .B2(registers_26__ap[22]), .C1(n_1_0_1277), .C2( + registers_13__ap[22]), .ZN(n_1_0_1082)); + NAND2_X1_LVT i_1_0_1136 (.A1(n_1_0_1083), .A2(n_1_0_1082), .ZN(n_1_0_1081)); + SDFF_X1_LVT \registers_reg[1][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_1__ap[22]), .CK(n_0_0), .Q(registers_1__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[28][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_28__ap[22]), .CK(n_0_58), .Q(registers_28__ap[22]), .QN()); + AOI221_X1_LVT i_1_0_1135 (.A(n_1_0_1081), .B1(n_1_0_1274), .B2( + registers_1__ap[22]), .C1(registers_28__ap[22]), .C2(n_1_0_1283), .ZN( + n_1_0_1080)); + SDFF_X1_LVT \registers_reg[18][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_18__ap[22]), .CK(n_0_48), .Q(registers_18__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[30][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_30__ap[22]), .CK(n_0_60), .Q(registers_30__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1134 (.A1(registers_18__ap[22]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[22]), .ZN(n_1_0_1079)); + SDFF_X1_LVT \registers_reg[24][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_24__ap[22]), .CK(n_0_54), .Q(registers_24__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[4][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_4__ap[22]), .CK(n_0_34), .Q(registers_4__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1133 (.A1(registers_24__ap[22]), .A2(n_1_0_1289), .B1( + n_1_0_1278), .B2(registers_4__ap[22]), .ZN(n_1_0_1078)); + SDFF_X1_LVT \registers_reg[15][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_15__ap[22]), .CK(n_0_45), .Q(registers_15__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[16][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_16__ap[22]), .CK(n_0_46), .Q(registers_16__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1132 (.A1(registers_15__ap[22]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[22]), .ZN(n_1_0_1077)); + NAND3_X1_LVT i_1_0_1131 (.A1(n_1_0_1079), .A2(n_1_0_1078), .A3(n_1_0_1077), + .ZN(n_1_0_1076)); + SDFF_X1_LVT \registers_reg[19][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_19__ap[22]), .CK(n_0_49), .Q(registers_19__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[25][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_25__ap[22]), .CK(n_0_55), .Q(registers_25__ap[22]), .QN()); + AOI221_X1_LVT i_1_0_1130 (.A(n_1_0_1076), .B1(n_1_0_1295), .B2( + registers_19__ap[22]), .C1(registers_25__ap[22]), .C2(n_1_0_1269), + .ZN(n_1_0_1075)); + SDFF_X1_LVT \registers_reg[7][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_7__ap[22]), .CK(n_0_37), .Q(registers_7__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[14][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_14__ap[22]), .CK(n_0_44), .Q(registers_14__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1129 (.A1(registers_7__ap[22]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[22]), .ZN(n_1_0_1074)); + SDFF_X1_LVT \registers_reg[9][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_9__ap[22]), .CK(n_0_39), .Q(registers_9__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[29][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_29__ap[22]), .CK(n_0_59), .Q(registers_29__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1128 (.A1(registers_9__ap[22]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[22]), .ZN(n_1_0_1073)); + SDFF_X1_LVT \registers_reg[8][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_8__ap[22]), .CK(n_0_38), .Q(registers_8__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[23][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_23__ap[22]), .CK(n_0_53), .Q(registers_23__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1127 (.A1(registers_8__ap[22]), .A2(n_1_0_1282), .B1( + n_1_0_1264), .B2(registers_23__ap[22]), .ZN(n_1_0_1072)); + NAND3_X1_LVT i_1_0_1126 (.A1(n_1_0_1074), .A2(n_1_0_1073), .A3(n_1_0_1072), + .ZN(n_1_0_1071)); + SDFF_X1_LVT \registers_reg[27][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_27__ap[22]), .CK(n_0_57), .Q(registers_27__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[3][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_3__ap[22]), .CK(n_0_33), .Q(registers_3__ap[22]), .QN()); + AOI221_X1_LVT i_1_0_1125 (.A(n_1_0_1071), .B1(n_1_0_1279), .B2( + registers_27__ap[22]), .C1(registers_3__ap[22]), .C2(n_1_0_1257), .ZN( + n_1_0_1070)); + NAND4_X1_LVT i_1_0_1124 (.A1(n_1_0_1087), .A2(n_1_0_1080), .A3(n_1_0_1075), + .A4(n_1_0_1070), .ZN(RRs1[22])); + AND2_X1_LVT i_0_0_21 (.A1(n_0_0_16), .A2(WRd[21]), .ZN(registers[21])); + SDFF_X1_LVT \registers_reg[17][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_17__ap[21]), .CK(n_0_47), .Q(registers_17__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[21][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_21__ap[21]), .CK(n_0_51), .Q(registers_21__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1122 (.A1(registers_17__ap[21]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[21]), .ZN(n_1_0_1068)); + SDFF_X1_LVT \registers_reg[6][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_6__ap[21]), .CK(n_0_36), .Q(registers_6__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[8][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_8__ap[21]), .CK(n_0_38), .Q(registers_8__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1123 (.A1(registers_6__ap[21]), .A2(n_1_0_1300), .B1( + n_1_0_1282), .B2(registers_8__ap[21]), .ZN(n_1_0_1069)); + SDFF_X1_LVT \registers_reg[20][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_20__ap[21]), .CK(n_0_50), .Q(registers_20__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[12][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_12__ap[21]), .CK(n_0_42), .Q(registers_12__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1121 (.A1(registers_20__ap[21]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[21]), .ZN(n_1_0_1067)); + SDFF_X1_LVT \registers_reg[5][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_5__ap[21]), .CK(n_0_35), .Q(registers_5__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[11][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_11__ap[21]), .CK(n_0_41), .Q(registers_11__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1120 (.A1(registers_5__ap[21]), .A2(n_1_0_1273), .B1( + n_1_0_1270), .B2(registers_11__ap[21]), .ZN(n_1_0_1066)); + NAND3_X1_LVT i_1_0_1119 (.A1(n_1_0_1069), .A2(n_1_0_1067), .A3(n_1_0_1066), + .ZN(n_1_0_1065)); + SDFF_X1_LVT \registers_reg[10][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_10__ap[21]), .CK(n_0_40), .Q(registers_10__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[2][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_2__ap[21]), .CK(n_0_32), .Q(registers_2__ap[21]), .QN()); + AOI221_X1_LVT i_1_0_1118 (.A(n_1_0_1065), .B1(n_1_0_1287), .B2( + registers_10__ap[21]), .C1(registers_2__ap[21]), .C2(n_1_0_1268), .ZN( + n_1_0_1064)); + SDFF_X1_LVT \registers_reg[13][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_13__ap[21]), .CK(n_0_43), .Q(registers_13__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[30][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_30__ap[21]), .CK(n_0_60), .Q(registers_30__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[22][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_22__ap[21]), .CK(n_0_52), .Q(registers_22__ap[21]), .QN()); + AOI222_X1_LVT i_1_0_1117 (.A1(registers_13__ap[21]), .A2(n_1_0_1277), + .B1(n_1_0_1272), .B2(registers_30__ap[21]), .C1(registers_22__ap[21]), + .C2(n_1_0_1294), .ZN(n_1_0_1063)); + NAND2_X1_LVT i_1_0_1116 (.A1(n_1_0_1064), .A2(n_1_0_1063), .ZN(n_1_0_1062)); + SDFF_X1_LVT \registers_reg[1][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_1__ap[21]), .CK(n_0_0), .Q(registers_1__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[28][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_28__ap[21]), .CK(n_0_58), .Q(registers_28__ap[21]), .QN()); + AOI221_X1_LVT i_1_0_1115 (.A(n_1_0_1062), .B1(n_1_0_1274), .B2( + registers_1__ap[21]), .C1(registers_28__ap[21]), .C2(n_1_0_1283), .ZN( + n_1_0_1061)); + SDFF_X1_LVT \registers_reg[18][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_18__ap[21]), .CK(n_0_48), .Q(registers_18__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[26][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_26__ap[21]), .CK(n_0_56), .Q(registers_26__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1114 (.A1(registers_18__ap[21]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[21]), .ZN(n_1_0_1060)); + SDFF_X1_LVT \registers_reg[24][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_24__ap[21]), .CK(n_0_54), .Q(registers_24__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[4][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_4__ap[21]), .CK(n_0_34), .Q(registers_4__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1113 (.A1(registers_24__ap[21]), .A2(n_1_0_1289), .B1( + n_1_0_1278), .B2(registers_4__ap[21]), .ZN(n_1_0_1059)); + SDFF_X1_LVT \registers_reg[15][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_15__ap[21]), .CK(n_0_45), .Q(registers_15__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[16][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_16__ap[21]), .CK(n_0_46), .Q(registers_16__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1112 (.A1(registers_15__ap[21]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[21]), .ZN(n_1_0_1058)); + NAND3_X1_LVT i_1_0_1111 (.A1(n_1_0_1060), .A2(n_1_0_1059), .A3(n_1_0_1058), + .ZN(n_1_0_1057)); + SDFF_X1_LVT \registers_reg[19][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_19__ap[21]), .CK(n_0_49), .Q(registers_19__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[25][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_25__ap[21]), .CK(n_0_55), .Q(registers_25__ap[21]), .QN()); + AOI221_X1_LVT i_1_0_1110 (.A(n_1_0_1057), .B1(n_1_0_1295), .B2( + registers_19__ap[21]), .C1(registers_25__ap[21]), .C2(n_1_0_1269), + .ZN(n_1_0_1056)); + SDFF_X1_LVT \registers_reg[7][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_7__ap[21]), .CK(n_0_37), .Q(registers_7__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[14][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_14__ap[21]), .CK(n_0_44), .Q(registers_14__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1109 (.A1(registers_7__ap[21]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[21]), .ZN(n_1_0_1055)); + SDFF_X1_LVT \registers_reg[9][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_9__ap[21]), .CK(n_0_39), .Q(registers_9__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[29][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_29__ap[21]), .CK(n_0_59), .Q(registers_29__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1108 (.A1(registers_9__ap[21]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[21]), .ZN(n_1_0_1054)); + SDFF_X1_LVT \registers_reg[23][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_23__ap[21]), .CK(n_0_53), .Q(registers_23__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[3][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_3__ap[21]), .CK(n_0_33), .Q(registers_3__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1107 (.A1(registers_23__ap[21]), .A2(n_1_0_1264), .B1( + n_1_0_1257), .B2(registers_3__ap[21]), .ZN(n_1_0_1053)); + NAND3_X1_LVT i_1_0_1106 (.A1(n_1_0_1055), .A2(n_1_0_1054), .A3(n_1_0_1053), + .ZN(n_1_0_1052)); + SDFF_X1_LVT \registers_reg[27][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_27__ap[21]), .CK(n_0_57), .Q(registers_27__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[31][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_31__ap[21]), .CK(n_0_61), .Q(registers_31__ap[21]), .QN()); + AOI221_X1_LVT i_1_0_1105 (.A(n_1_0_1052), .B1(n_1_0_1279), .B2( + registers_27__ap[21]), .C1(registers_31__ap[21]), .C2(n_1_0_1266), + .ZN(n_1_0_1051)); + NAND4_X1_LVT i_1_0_1104 (.A1(n_1_0_1068), .A2(n_1_0_1061), .A3(n_1_0_1056), + .A4(n_1_0_1051), .ZN(RRs1[21])); + AND2_X1_LVT i_0_0_20 (.A1(n_0_0_16), .A2(WRd[20]), .ZN(registers[20])); + SDFF_X1_LVT \registers_reg[17][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_17__ap[20]), .CK(n_0_47), .Q(registers_17__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[21][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_21__ap[20]), .CK(n_0_51), .Q(registers_21__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1100 (.A1(registers_17__ap[20]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[20]), .ZN(n_1_0_1047)); + SDFF_X1_LVT \registers_reg[10][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_10__ap[20]), .CK(n_0_40), .Q(registers_10__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[2][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_2__ap[20]), .CK(n_0_32), .Q(registers_2__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1103 (.A1(registers_10__ap[20]), .A2(n_1_0_1287), .B1( + n_1_0_1268), .B2(registers_2__ap[20]), .ZN(n_1_0_1050)); + SDFF_X1_LVT \registers_reg[20][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_20__ap[20]), .CK(n_0_50), .Q(registers_20__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[12][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_12__ap[20]), .CK(n_0_42), .Q(registers_12__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1099 (.A1(registers_20__ap[20]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[20]), .ZN(n_1_0_1046)); + SDFF_X1_LVT \registers_reg[15][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_15__ap[20]), .CK(n_0_45), .Q(registers_15__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[8][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_8__ap[20]), .CK(n_0_38), .Q(registers_8__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1102 (.A1(registers_15__ap[20]), .A2(n_1_0_1286), .B1( + n_1_0_1282), .B2(registers_8__ap[20]), .ZN(n_1_0_1049)); + INV_X1_LVT i_1_0_1101 (.A(n_1_0_1049), .ZN(n_1_0_1048)); + SDFF_X1_LVT \registers_reg[11][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_11__ap[20]), .CK(n_0_41), .Q(registers_11__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[5][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_5__ap[20]), .CK(n_0_35), .Q(registers_5__ap[20]), .QN()); + AOI221_X1_LVT i_1_0_1098 (.A(n_1_0_1048), .B1(n_1_0_1270), .B2( + registers_11__ap[20]), .C1(registers_5__ap[20]), .C2(n_1_0_1273), .ZN( + n_1_0_1045)); + SDFF_X1_LVT \registers_reg[13][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_13__ap[20]), .CK(n_0_43), .Q(registers_13__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[30][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_30__ap[20]), .CK(n_0_60), .Q(registers_30__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[22][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_22__ap[20]), .CK(n_0_52), .Q(registers_22__ap[20]), .QN()); + AOI222_X1_LVT i_1_0_1097 (.A1(registers_13__ap[20]), .A2(n_1_0_1277), + .B1(n_1_0_1272), .B2(registers_30__ap[20]), .C1(registers_22__ap[20]), + .C2(n_1_0_1294), .ZN(n_1_0_1044)); + NAND4_X1_LVT i_1_0_1096 (.A1(n_1_0_1050), .A2(n_1_0_1046), .A3(n_1_0_1045), + .A4(n_1_0_1044), .ZN(n_1_0_1043)); + SDFF_X1_LVT \registers_reg[1][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_1__ap[20]), .CK(n_0_0), .Q(registers_1__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[28][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_28__ap[20]), .CK(n_0_58), .Q(registers_28__ap[20]), .QN()); + AOI221_X1_LVT i_1_0_1095 (.A(n_1_0_1043), .B1(n_1_0_1274), .B2( + registers_1__ap[20]), .C1(registers_28__ap[20]), .C2(n_1_0_1283), .ZN( + n_1_0_1042)); + SDFF_X1_LVT \registers_reg[18][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_18__ap[20]), .CK(n_0_48), .Q(registers_18__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[26][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_26__ap[20]), .CK(n_0_56), .Q(registers_26__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1094 (.A1(registers_18__ap[20]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[20]), .ZN(n_1_0_1041)); + SDFF_X1_LVT \registers_reg[24][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_24__ap[20]), .CK(n_0_54), .Q(registers_24__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[4][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_4__ap[20]), .CK(n_0_34), .Q(registers_4__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1093 (.A1(registers_24__ap[20]), .A2(n_1_0_1289), .B1( + n_1_0_1278), .B2(registers_4__ap[20]), .ZN(n_1_0_1040)); + SDFF_X1_LVT \registers_reg[6][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_6__ap[20]), .CK(n_0_36), .Q(registers_6__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[25][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_25__ap[20]), .CK(n_0_55), .Q(registers_25__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1092 (.A1(registers_6__ap[20]), .A2(n_1_0_1300), .B1( + n_1_0_1269), .B2(registers_25__ap[20]), .ZN(n_1_0_1039)); + NAND3_X1_LVT i_1_0_1091 (.A1(n_1_0_1041), .A2(n_1_0_1040), .A3(n_1_0_1039), + .ZN(n_1_0_1038)); + SDFF_X1_LVT \registers_reg[19][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_19__ap[20]), .CK(n_0_49), .Q(registers_19__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[16][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_16__ap[20]), .CK(n_0_46), .Q(registers_16__ap[20]), .QN()); + AOI221_X1_LVT i_1_0_1090 (.A(n_1_0_1038), .B1(n_1_0_1295), .B2( + registers_19__ap[20]), .C1(registers_16__ap[20]), .C2(n_1_0_1267), + .ZN(n_1_0_1037)); + SDFF_X1_LVT \registers_reg[7][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_7__ap[20]), .CK(n_0_37), .Q(registers_7__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[14][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_14__ap[20]), .CK(n_0_44), .Q(registers_14__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1089 (.A1(registers_7__ap[20]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[20]), .ZN(n_1_0_1036)); + SDFF_X1_LVT \registers_reg[9][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_9__ap[20]), .CK(n_0_39), .Q(registers_9__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[29][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_29__ap[20]), .CK(n_0_59), .Q(registers_29__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1088 (.A1(registers_9__ap[20]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[20]), .ZN(n_1_0_1035)); + SDFF_X1_LVT \registers_reg[23][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_23__ap[20]), .CK(n_0_53), .Q(registers_23__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[3][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_3__ap[20]), .CK(n_0_33), .Q(registers_3__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1087 (.A1(registers_23__ap[20]), .A2(n_1_0_1264), .B1( + n_1_0_1257), .B2(registers_3__ap[20]), .ZN(n_1_0_1034)); + NAND3_X1_LVT i_1_0_1086 (.A1(n_1_0_1036), .A2(n_1_0_1035), .A3(n_1_0_1034), + .ZN(n_1_0_1033)); + SDFF_X1_LVT \registers_reg[27][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_27__ap[20]), .CK(n_0_57), .Q(registers_27__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[31][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_31__ap[20]), .CK(n_0_61), .Q(registers_31__ap[20]), .QN()); + AOI221_X1_LVT i_1_0_1085 (.A(n_1_0_1033), .B1(n_1_0_1279), .B2( + registers_27__ap[20]), .C1(registers_31__ap[20]), .C2(n_1_0_1266), + .ZN(n_1_0_1032)); + NAND4_X1_LVT i_1_0_1084 (.A1(n_1_0_1047), .A2(n_1_0_1042), .A3(n_1_0_1037), + .A4(n_1_0_1032), .ZN(RRs1[20])); + AND2_X1_LVT i_0_0_19 (.A1(n_0_0_16), .A2(WRd[19]), .ZN(registers[19])); + SDFF_X1_LVT \registers_reg[17][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_17__ap[19]), .CK(n_0_47), .Q(registers_17__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[21][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_21__ap[19]), .CK(n_0_51), .Q(registers_21__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1080 (.A1(registers_17__ap[19]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[19]), .ZN(n_1_0_1028)); + SDFF_X1_LVT \registers_reg[2][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_2__ap[19]), .CK(n_0_32), .Q(registers_2__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[31][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_31__ap[19]), .CK(n_0_61), .Q(registers_31__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1083 (.A1(registers_2__ap[19]), .A2(n_1_0_1268), .B1( + n_1_0_1266), .B2(registers_31__ap[19]), .ZN(n_1_0_1031)); + SDFF_X1_LVT \registers_reg[20][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_20__ap[19]), .CK(n_0_50), .Q(registers_20__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[12][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_12__ap[19]), .CK(n_0_42), .Q(registers_12__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1079 (.A1(registers_20__ap[19]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[19]), .ZN(n_1_0_1027)); + SDFF_X1_LVT \registers_reg[15][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_15__ap[19]), .CK(n_0_45), .Q(registers_15__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[11][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_11__ap[19]), .CK(n_0_41), .Q(registers_11__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1082 (.A1(registers_15__ap[19]), .A2(n_1_0_1286), .B1( + n_1_0_1270), .B2(registers_11__ap[19]), .ZN(n_1_0_1030)); + INV_X1_LVT i_1_0_1081 (.A(n_1_0_1030), .ZN(n_1_0_1029)); + SDFF_X1_LVT \registers_reg[27][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_27__ap[19]), .CK(n_0_57), .Q(registers_27__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[24][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_24__ap[19]), .CK(n_0_54), .Q(registers_24__ap[19]), .QN()); + AOI221_X1_LVT i_1_0_1078 (.A(n_1_0_1029), .B1(n_1_0_1279), .B2( + registers_27__ap[19]), .C1(registers_24__ap[19]), .C2(n_1_0_1289), + .ZN(n_1_0_1026)); + SDFF_X1_LVT \registers_reg[22][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_22__ap[19]), .CK(n_0_52), .Q(registers_22__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[26][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_26__ap[19]), .CK(n_0_56), .Q(registers_26__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[13][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_13__ap[19]), .CK(n_0_43), .Q(registers_13__ap[19]), .QN()); + AOI222_X1_LVT i_1_0_1077 (.A1(registers_22__ap[19]), .A2(n_1_0_1294), + .B1(n_1_0_1285), .B2(registers_26__ap[19]), .C1(n_1_0_1277), .C2( + registers_13__ap[19]), .ZN(n_1_0_1025)); + NAND4_X1_LVT i_1_0_1076 (.A1(n_1_0_1031), .A2(n_1_0_1027), .A3(n_1_0_1026), + .A4(n_1_0_1025), .ZN(n_1_0_1024)); + SDFF_X1_LVT \registers_reg[1][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_1__ap[19]), .CK(n_0_0), .Q(registers_1__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[28][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_28__ap[19]), .CK(n_0_58), .Q(registers_28__ap[19]), .QN()); + AOI221_X1_LVT i_1_0_1075 (.A(n_1_0_1024), .B1(n_1_0_1274), .B2( + registers_1__ap[19]), .C1(registers_28__ap[19]), .C2(n_1_0_1283), .ZN( + n_1_0_1023)); + SDFF_X1_LVT \registers_reg[18][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_18__ap[19]), .CK(n_0_48), .Q(registers_18__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[30][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_30__ap[19]), .CK(n_0_60), .Q(registers_30__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1074 (.A1(registers_18__ap[19]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[19]), .ZN(n_1_0_1022)); + SDFF_X1_LVT \registers_reg[4][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_4__ap[19]), .CK(n_0_34), .Q(registers_4__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[5][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_5__ap[19]), .CK(n_0_35), .Q(registers_5__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1073 (.A1(registers_4__ap[19]), .A2(n_1_0_1278), .B1( + n_1_0_1273), .B2(registers_5__ap[19]), .ZN(n_1_0_1021)); + SDFF_X1_LVT \registers_reg[6][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_6__ap[19]), .CK(n_0_36), .Q(registers_6__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[25][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_25__ap[19]), .CK(n_0_55), .Q(registers_25__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1072 (.A1(registers_6__ap[19]), .A2(n_1_0_1300), .B1( + n_1_0_1269), .B2(registers_25__ap[19]), .ZN(n_1_0_1020)); + NAND3_X1_LVT i_1_0_1071 (.A1(n_1_0_1022), .A2(n_1_0_1021), .A3(n_1_0_1020), + .ZN(n_1_0_1019)); + SDFF_X1_LVT \registers_reg[19][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_19__ap[19]), .CK(n_0_49), .Q(registers_19__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[16][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_16__ap[19]), .CK(n_0_46), .Q(registers_16__ap[19]), .QN()); + AOI221_X1_LVT i_1_0_1070 (.A(n_1_0_1019), .B1(n_1_0_1295), .B2( + registers_19__ap[19]), .C1(registers_16__ap[19]), .C2(n_1_0_1267), + .ZN(n_1_0_1018)); + SDFF_X1_LVT \registers_reg[9][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_9__ap[19]), .CK(n_0_39), .Q(registers_9__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[29][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_29__ap[19]), .CK(n_0_59), .Q(registers_29__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1069 (.A1(registers_9__ap[19]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[19]), .ZN(n_1_0_1017)); + SDFF_X1_LVT \registers_reg[8][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_8__ap[19]), .CK(n_0_38), .Q(registers_8__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[23][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_23__ap[19]), .CK(n_0_53), .Q(registers_23__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1068 (.A1(registers_8__ap[19]), .A2(n_1_0_1282), .B1( + n_1_0_1264), .B2(registers_23__ap[19]), .ZN(n_1_0_1016)); + SDFF_X1_LVT \registers_reg[7][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_7__ap[19]), .CK(n_0_37), .Q(registers_7__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[14][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_14__ap[19]), .CK(n_0_44), .Q(registers_14__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1067 (.A1(registers_7__ap[19]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[19]), .ZN(n_1_0_1015)); + NAND3_X1_LVT i_1_0_1066 (.A1(n_1_0_1017), .A2(n_1_0_1016), .A3(n_1_0_1015), + .ZN(n_1_0_1014)); + SDFF_X1_LVT \registers_reg[10][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_10__ap[19]), .CK(n_0_40), .Q(registers_10__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[3][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_3__ap[19]), .CK(n_0_33), .Q(registers_3__ap[19]), .QN()); + AOI221_X1_LVT i_1_0_1065 (.A(n_1_0_1014), .B1(n_1_0_1287), .B2( + registers_10__ap[19]), .C1(registers_3__ap[19]), .C2(n_1_0_1257), .ZN( + n_1_0_1013)); + NAND4_X1_LVT i_1_0_1064 (.A1(n_1_0_1028), .A2(n_1_0_1023), .A3(n_1_0_1018), + .A4(n_1_0_1013), .ZN(RRs1[19])); + AND2_X1_LVT i_0_0_18 (.A1(n_0_0_16), .A2(WRd[18]), .ZN(registers[18])); + SDFF_X1_LVT \registers_reg[24][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_24__ap[18]), .CK(n_0_54), .Q(registers_24__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[28][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_28__ap[18]), .CK(n_0_58), .Q(registers_28__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1062 (.A1(registers_24__ap[18]), .A2(n_1_0_1289), .B1( + n_1_0_1283), .B2(registers_28__ap[18]), .ZN(n_1_0_1011)); + SDFF_X1_LVT \registers_reg[11][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_11__ap[18]), .CK(n_0_41), .Q(registers_11__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[16][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_16__ap[18]), .CK(n_0_46), .Q(registers_16__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1063 (.A1(registers_11__ap[18]), .A2(n_1_0_1270), .B1( + n_1_0_1267), .B2(registers_16__ap[18]), .ZN(n_1_0_1012)); + SDFF_X1_LVT \registers_reg[9][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_9__ap[18]), .CK(n_0_39), .Q(registers_9__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[7][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_7__ap[18]), .CK(n_0_37), .Q(registers_7__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1061 (.A1(registers_9__ap[18]), .A2(n_1_0_1291), .B1( + n_1_0_1263), .B2(registers_7__ap[18]), .ZN(n_1_0_1010)); + SDFF_X1_LVT \registers_reg[27][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_27__ap[18]), .CK(n_0_57), .Q(registers_27__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[25][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_25__ap[18]), .CK(n_0_55), .Q(registers_25__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1060 (.A1(registers_27__ap[18]), .A2(n_1_0_1279), .B1( + n_1_0_1269), .B2(registers_25__ap[18]), .ZN(n_1_0_1009)); + NAND3_X1_LVT i_1_0_1059 (.A1(n_1_0_1012), .A2(n_1_0_1010), .A3(n_1_0_1009), + .ZN(n_1_0_1008)); + SDFF_X1_LVT \registers_reg[31][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_31__ap[18]), .CK(n_0_61), .Q(registers_31__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[6][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_6__ap[18]), .CK(n_0_36), .Q(registers_6__ap[18]), .QN()); + AOI221_X1_LVT i_1_0_1058 (.A(n_1_0_1008), .B1(n_1_0_1266), .B2( + registers_31__ap[18]), .C1(registers_6__ap[18]), .C2(n_1_0_1300), .ZN( + n_1_0_1007)); + SDFF_X1_LVT \registers_reg[22][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_22__ap[18]), .CK(n_0_52), .Q(registers_22__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[26][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_26__ap[18]), .CK(n_0_56), .Q(registers_26__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[1][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_1__ap[18]), .CK(n_0_0), .Q(registers_1__ap[18]), .QN()); + AOI222_X1_LVT i_1_0_1057 (.A1(registers_22__ap[18]), .A2(n_1_0_1294), + .B1(n_1_0_1285), .B2(registers_26__ap[18]), .C1(n_1_0_1274), .C2( + registers_1__ap[18]), .ZN(n_1_0_1006)); + NAND2_X1_LVT i_1_0_1056 (.A1(n_1_0_1007), .A2(n_1_0_1006), .ZN(n_1_0_1005)); + SDFF_X1_LVT \registers_reg[29][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_29__ap[18]), .CK(n_0_59), .Q(registers_29__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[2][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_2__ap[18]), .CK(n_0_32), .Q(registers_2__ap[18]), .QN()); + AOI221_X1_LVT i_1_0_1055 (.A(n_1_0_1005), .B1(n_1_0_1276), .B2( + registers_29__ap[18]), .C1(registers_2__ap[18]), .C2(n_1_0_1268), .ZN( + n_1_0_1004)); + SDFF_X1_LVT \registers_reg[18][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_18__ap[18]), .CK(n_0_48), .Q(registers_18__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[30][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_30__ap[18]), .CK(n_0_60), .Q(registers_30__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1054 (.A1(registers_18__ap[18]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[18]), .ZN(n_1_0_1003)); + SDFF_X1_LVT \registers_reg[4][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_4__ap[18]), .CK(n_0_34), .Q(registers_4__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[12][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_12__ap[18]), .CK(n_0_42), .Q(registers_12__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1053 (.A1(registers_4__ap[18]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[18]), .ZN(n_1_0_1002)); + SDFF_X1_LVT \registers_reg[19][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_19__ap[18]), .CK(n_0_49), .Q(registers_19__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[21][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_21__ap[18]), .CK(n_0_51), .Q(registers_21__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1052 (.A1(registers_19__ap[18]), .A2(n_1_0_1295), .B1( + n_1_0_1259), .B2(registers_21__ap[18]), .ZN(n_1_0_1001)); + NAND3_X1_LVT i_1_0_1051 (.A1(n_1_0_1003), .A2(n_1_0_1002), .A3(n_1_0_1001), + .ZN(n_1_0_1000)); + SDFF_X1_LVT \registers_reg[5][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_5__ap[18]), .CK(n_0_35), .Q(registers_5__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[20][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_20__ap[18]), .CK(n_0_50), .Q(registers_20__ap[18]), .QN()); + AOI221_X1_LVT i_1_0_1050 (.A(n_1_0_1000), .B1(n_1_0_1273), .B2( + registers_5__ap[18]), .C1(registers_20__ap[18]), .C2(n_1_0_1281), .ZN( + n_1_0_999)); + SDFF_X1_LVT \registers_reg[8][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_8__ap[18]), .CK(n_0_38), .Q(registers_8__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[23][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_23__ap[18]), .CK(n_0_53), .Q(registers_23__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1049 (.A1(registers_8__ap[18]), .A2(n_1_0_1282), .B1( + n_1_0_1264), .B2(registers_23__ap[18]), .ZN(n_1_0_998)); + SDFF_X1_LVT \registers_reg[13][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_13__ap[18]), .CK(n_0_43), .Q(registers_13__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[17][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_17__ap[18]), .CK(n_0_47), .Q(registers_17__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1048 (.A1(registers_13__ap[18]), .A2(n_1_0_1277), .B1( + n_1_0_1271), .B2(registers_17__ap[18]), .ZN(n_1_0_997)); + SDFF_X1_LVT \registers_reg[15][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_15__ap[18]), .CK(n_0_45), .Q(registers_15__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[14][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_14__ap[18]), .CK(n_0_44), .Q(registers_14__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1047 (.A1(registers_15__ap[18]), .A2(n_1_0_1286), .B1( + n_1_0_1258), .B2(registers_14__ap[18]), .ZN(n_1_0_996)); + NAND3_X1_LVT i_1_0_1046 (.A1(n_1_0_998), .A2(n_1_0_997), .A3(n_1_0_996), + .ZN(n_1_0_995)); + SDFF_X1_LVT \registers_reg[10][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_10__ap[18]), .CK(n_0_40), .Q(registers_10__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[3][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_3__ap[18]), .CK(n_0_33), .Q(registers_3__ap[18]), .QN()); + AOI221_X1_LVT i_1_0_1045 (.A(n_1_0_995), .B1(n_1_0_1287), .B2( + registers_10__ap[18]), .C1(registers_3__ap[18]), .C2(n_1_0_1257), .ZN( + n_1_0_994)); + NAND4_X1_LVT i_1_0_1044 (.A1(n_1_0_1011), .A2(n_1_0_1004), .A3(n_1_0_999), + .A4(n_1_0_994), .ZN(RRs1[18])); + AND2_X1_LVT i_0_0_17 (.A1(n_0_0_16), .A2(WRd[17]), .ZN(registers[17])); + SDFF_X1_LVT \registers_reg[17][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_17__ap[17]), .CK(n_0_47), .Q(registers_17__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[21][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_21__ap[17]), .CK(n_0_51), .Q(registers_21__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1040 (.A1(registers_17__ap[17]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[17]), .ZN(n_1_0_990)); + SDFF_X1_LVT \registers_reg[2][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_2__ap[17]), .CK(n_0_32), .Q(registers_2__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[31][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_31__ap[17]), .CK(n_0_61), .Q(registers_31__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1043 (.A1(registers_2__ap[17]), .A2(n_1_0_1268), .B1( + n_1_0_1266), .B2(registers_31__ap[17]), .ZN(n_1_0_993)); + SDFF_X1_LVT \registers_reg[20][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_20__ap[17]), .CK(n_0_50), .Q(registers_20__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[12][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_12__ap[17]), .CK(n_0_42), .Q(registers_12__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1039 (.A1(registers_20__ap[17]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[17]), .ZN(n_1_0_989)); + SDFF_X1_LVT \registers_reg[15][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_15__ap[17]), .CK(n_0_45), .Q(registers_15__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[11][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_11__ap[17]), .CK(n_0_41), .Q(registers_11__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1042 (.A1(registers_15__ap[17]), .A2(n_1_0_1286), .B1( + n_1_0_1270), .B2(registers_11__ap[17]), .ZN(n_1_0_992)); + INV_X1_LVT i_1_0_1041 (.A(n_1_0_992), .ZN(n_1_0_991)); + SDFF_X1_LVT \registers_reg[10][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_10__ap[17]), .CK(n_0_40), .Q(registers_10__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[24][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_24__ap[17]), .CK(n_0_54), .Q(registers_24__ap[17]), .QN()); + AOI221_X1_LVT i_1_0_1038 (.A(n_1_0_991), .B1(n_1_0_1287), .B2( + registers_10__ap[17]), .C1(registers_24__ap[17]), .C2(n_1_0_1289), + .ZN(n_1_0_988)); + SDFF_X1_LVT \registers_reg[22][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_22__ap[17]), .CK(n_0_52), .Q(registers_22__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[26][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_26__ap[17]), .CK(n_0_56), .Q(registers_26__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[13][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_13__ap[17]), .CK(n_0_43), .Q(registers_13__ap[17]), .QN()); + AOI222_X1_LVT i_1_0_1037 (.A1(registers_22__ap[17]), .A2(n_1_0_1294), + .B1(n_1_0_1285), .B2(registers_26__ap[17]), .C1(n_1_0_1277), .C2( + registers_13__ap[17]), .ZN(n_1_0_987)); + NAND4_X1_LVT i_1_0_1036 (.A1(n_1_0_993), .A2(n_1_0_989), .A3(n_1_0_988), + .A4(n_1_0_987), .ZN(n_1_0_986)); + SDFF_X1_LVT \registers_reg[1][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_1__ap[17]), .CK(n_0_0), .Q(registers_1__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[28][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_28__ap[17]), .CK(n_0_58), .Q(registers_28__ap[17]), .QN()); + AOI221_X1_LVT i_1_0_1035 (.A(n_1_0_986), .B1(n_1_0_1274), .B2( + registers_1__ap[17]), .C1(registers_28__ap[17]), .C2(n_1_0_1283), .ZN( + n_1_0_985)); + SDFF_X1_LVT \registers_reg[18][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_18__ap[17]), .CK(n_0_48), .Q(registers_18__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[30][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_30__ap[17]), .CK(n_0_60), .Q(registers_30__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1034 (.A1(registers_18__ap[17]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[17]), .ZN(n_1_0_984)); + SDFF_X1_LVT \registers_reg[4][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_4__ap[17]), .CK(n_0_34), .Q(registers_4__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[5][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_5__ap[17]), .CK(n_0_35), .Q(registers_5__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1033 (.A1(registers_4__ap[17]), .A2(n_1_0_1278), .B1( + n_1_0_1273), .B2(registers_5__ap[17]), .ZN(n_1_0_983)); + SDFF_X1_LVT \registers_reg[6][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_6__ap[17]), .CK(n_0_36), .Q(registers_6__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[25][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_25__ap[17]), .CK(n_0_55), .Q(registers_25__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1032 (.A1(registers_6__ap[17]), .A2(n_1_0_1300), .B1( + n_1_0_1269), .B2(registers_25__ap[17]), .ZN(n_1_0_982)); + NAND3_X1_LVT i_1_0_1031 (.A1(n_1_0_984), .A2(n_1_0_983), .A3(n_1_0_982), + .ZN(n_1_0_981)); + SDFF_X1_LVT \registers_reg[19][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_19__ap[17]), .CK(n_0_49), .Q(registers_19__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[16][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_16__ap[17]), .CK(n_0_46), .Q(registers_16__ap[17]), .QN()); + AOI221_X1_LVT i_1_0_1030 (.A(n_1_0_981), .B1(n_1_0_1295), .B2( + registers_19__ap[17]), .C1(registers_16__ap[17]), .C2(n_1_0_1267), + .ZN(n_1_0_980)); + SDFF_X1_LVT \registers_reg[7][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_7__ap[17]), .CK(n_0_37), .Q(registers_7__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[14][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_14__ap[17]), .CK(n_0_44), .Q(registers_14__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1029 (.A1(registers_7__ap[17]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[17]), .ZN(n_1_0_979)); + SDFF_X1_LVT \registers_reg[9][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_9__ap[17]), .CK(n_0_39), .Q(registers_9__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[29][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_29__ap[17]), .CK(n_0_59), .Q(registers_29__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1028 (.A1(registers_9__ap[17]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[17]), .ZN(n_1_0_978)); + SDFF_X1_LVT \registers_reg[8][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_8__ap[17]), .CK(n_0_38), .Q(registers_8__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[23][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_23__ap[17]), .CK(n_0_53), .Q(registers_23__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1027 (.A1(registers_8__ap[17]), .A2(n_1_0_1282), .B1( + n_1_0_1264), .B2(registers_23__ap[17]), .ZN(n_1_0_977)); + NAND3_X1_LVT i_1_0_1026 (.A1(n_1_0_979), .A2(n_1_0_978), .A3(n_1_0_977), + .ZN(n_1_0_976)); + SDFF_X1_LVT \registers_reg[27][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_27__ap[17]), .CK(n_0_57), .Q(registers_27__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[3][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_3__ap[17]), .CK(n_0_33), .Q(registers_3__ap[17]), .QN()); + AOI221_X1_LVT i_1_0_1025 (.A(n_1_0_976), .B1(n_1_0_1279), .B2( + registers_27__ap[17]), .C1(registers_3__ap[17]), .C2(n_1_0_1257), .ZN( + n_1_0_975)); + NAND4_X1_LVT i_1_0_1024 (.A1(n_1_0_990), .A2(n_1_0_985), .A3(n_1_0_980), + .A4(n_1_0_975), .ZN(RRs1[17])); + AND2_X1_LVT i_0_0_16 (.A1(n_0_0_16), .A2(WRd[16]), .ZN(registers[16])); + SDFF_X1_LVT \registers_reg[29][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_29__ap[16]), .CK(n_0_59), .Q(registers_29__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[2][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_2__ap[16]), .CK(n_0_32), .Q(registers_2__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1022 (.A1(registers_29__ap[16]), .A2(n_1_0_1276), .B1( + n_1_0_1268), .B2(registers_2__ap[16]), .ZN(n_1_0_973)); + SDFF_X1_LVT \registers_reg[11][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_11__ap[16]), .CK(n_0_41), .Q(registers_11__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[25][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_25__ap[16]), .CK(n_0_55), .Q(registers_25__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1023 (.A1(registers_11__ap[16]), .A2(n_1_0_1270), .B1( + n_1_0_1269), .B2(registers_25__ap[16]), .ZN(n_1_0_974)); + SDFF_X1_LVT \registers_reg[9][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_9__ap[16]), .CK(n_0_39), .Q(registers_9__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[7][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_7__ap[16]), .CK(n_0_37), .Q(registers_7__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1021 (.A1(registers_9__ap[16]), .A2(n_1_0_1291), .B1( + n_1_0_1263), .B2(registers_7__ap[16]), .ZN(n_1_0_972)); + SDFF_X1_LVT \registers_reg[10][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_10__ap[16]), .CK(n_0_40), .Q(registers_10__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[16][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_16__ap[16]), .CK(n_0_46), .Q(registers_16__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1020 (.A1(registers_10__ap[16]), .A2(n_1_0_1287), .B1( + n_1_0_1267), .B2(registers_16__ap[16]), .ZN(n_1_0_971)); + NAND3_X1_LVT i_1_0_1019 (.A1(n_1_0_974), .A2(n_1_0_972), .A3(n_1_0_971), + .ZN(n_1_0_970)); + SDFF_X1_LVT \registers_reg[31][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_31__ap[16]), .CK(n_0_61), .Q(registers_31__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[6][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_6__ap[16]), .CK(n_0_36), .Q(registers_6__ap[16]), .QN()); + AOI221_X1_LVT i_1_0_1018 (.A(n_1_0_970), .B1(n_1_0_1266), .B2( + registers_31__ap[16]), .C1(registers_6__ap[16]), .C2(n_1_0_1300), .ZN( + n_1_0_969)); + SDFF_X1_LVT \registers_reg[18][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_18__ap[16]), .CK(n_0_48), .Q(registers_18__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[22][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_22__ap[16]), .CK(n_0_52), .Q(registers_22__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[1][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_1__ap[16]), .CK(n_0_0), .Q(registers_1__ap[16]), .QN()); + AOI222_X1_LVT i_1_0_1017 (.A1(registers_18__ap[16]), .A2(n_1_0_1297), + .B1(n_1_0_1294), .B2(registers_22__ap[16]), .C1(registers_1__ap[16]), + .C2(n_1_0_1274), .ZN(n_1_0_968)); + NAND3_X1_LVT i_1_0_1016 (.A1(n_1_0_973), .A2(n_1_0_969), .A3(n_1_0_968), + .ZN(n_1_0_967)); + SDFF_X1_LVT \registers_reg[5][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_5__ap[16]), .CK(n_0_35), .Q(registers_5__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[28][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_28__ap[16]), .CK(n_0_58), .Q(registers_28__ap[16]), .QN()); + AOI221_X1_LVT i_1_0_1015 (.A(n_1_0_967), .B1(n_1_0_1273), .B2( + registers_5__ap[16]), .C1(registers_28__ap[16]), .C2(n_1_0_1283), .ZN( + n_1_0_966)); + SDFF_X1_LVT \registers_reg[4][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_4__ap[16]), .CK(n_0_34), .Q(registers_4__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[12][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_12__ap[16]), .CK(n_0_42), .Q(registers_12__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1014 (.A1(registers_4__ap[16]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[16]), .ZN(n_1_0_965)); + SDFF_X1_LVT \registers_reg[19][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_19__ap[16]), .CK(n_0_49), .Q(registers_19__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[21][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_21__ap[16]), .CK(n_0_51), .Q(registers_21__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1013 (.A1(registers_19__ap[16]), .A2(n_1_0_1295), .B1( + n_1_0_1259), .B2(registers_21__ap[16]), .ZN(n_1_0_964)); + SDFF_X1_LVT \registers_reg[24][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_24__ap[16]), .CK(n_0_54), .Q(registers_24__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[20][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_20__ap[16]), .CK(n_0_50), .Q(registers_20__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1012 (.A1(registers_24__ap[16]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[16]), .ZN(n_1_0_963)); + NAND3_X1_LVT i_1_0_1011 (.A1(n_1_0_965), .A2(n_1_0_964), .A3(n_1_0_963), + .ZN(n_1_0_962)); + SDFF_X1_LVT \registers_reg[26][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_26__ap[16]), .CK(n_0_56), .Q(registers_26__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[30][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_30__ap[16]), .CK(n_0_60), .Q(registers_30__ap[16]), .QN()); + AOI221_X1_LVT i_1_0_1010 (.A(n_1_0_962), .B1(n_1_0_1285), .B2( + registers_26__ap[16]), .C1(registers_30__ap[16]), .C2(n_1_0_1272), + .ZN(n_1_0_961)); + SDFF_X1_LVT \registers_reg[8][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_8__ap[16]), .CK(n_0_38), .Q(registers_8__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[23][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_23__ap[16]), .CK(n_0_53), .Q(registers_23__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1009 (.A1(registers_8__ap[16]), .A2(n_1_0_1282), .B1( + n_1_0_1264), .B2(registers_23__ap[16]), .ZN(n_1_0_960)); + SDFF_X1_LVT \registers_reg[13][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_13__ap[16]), .CK(n_0_43), .Q(registers_13__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[17][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_17__ap[16]), .CK(n_0_47), .Q(registers_17__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1008 (.A1(registers_13__ap[16]), .A2(n_1_0_1277), .B1( + n_1_0_1271), .B2(registers_17__ap[16]), .ZN(n_1_0_959)); + SDFF_X1_LVT \registers_reg[15][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_15__ap[16]), .CK(n_0_45), .Q(registers_15__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[14][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_14__ap[16]), .CK(n_0_44), .Q(registers_14__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1007 (.A1(registers_15__ap[16]), .A2(n_1_0_1286), .B1( + n_1_0_1258), .B2(registers_14__ap[16]), .ZN(n_1_0_958)); + NAND3_X1_LVT i_1_0_1006 (.A1(n_1_0_960), .A2(n_1_0_959), .A3(n_1_0_958), + .ZN(n_1_0_957)); + SDFF_X1_LVT \registers_reg[27][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_27__ap[16]), .CK(n_0_57), .Q(registers_27__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[3][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_3__ap[16]), .CK(n_0_33), .Q(registers_3__ap[16]), .QN()); + AOI221_X1_LVT i_1_0_1005 (.A(n_1_0_957), .B1(n_1_0_1279), .B2( + registers_27__ap[16]), .C1(registers_3__ap[16]), .C2(n_1_0_1257), .ZN( + n_1_0_956)); + NAND3_X1_LVT i_1_0_1004 (.A1(n_1_0_966), .A2(n_1_0_961), .A3(n_1_0_956), + .ZN(RRs1[16])); + AND2_X1_LVT i_0_0_15 (.A1(n_0_0_16), .A2(WRd[15]), .ZN(registers[15])); + SDFF_X1_LVT \registers_reg[17][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_17__ap[15]), .CK(n_0_47), .Q(registers_17__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[21][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_21__ap[15]), .CK(n_0_51), .Q(registers_21__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_1000 (.A1(registers_17__ap[15]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[15]), .ZN(n_1_0_952)); + SDFF_X1_LVT \registers_reg[10][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_10__ap[15]), .CK(n_0_40), .Q(registers_10__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[2][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_2__ap[15]), .CK(n_0_32), .Q(registers_2__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_1003 (.A1(registers_10__ap[15]), .A2(n_1_0_1287), .B1( + n_1_0_1268), .B2(registers_2__ap[15]), .ZN(n_1_0_955)); + SDFF_X1_LVT \registers_reg[20][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_20__ap[15]), .CK(n_0_50), .Q(registers_20__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[12][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_12__ap[15]), .CK(n_0_42), .Q(registers_12__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_999 (.A1(registers_20__ap[15]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[15]), .ZN(n_1_0_951)); + SDFF_X1_LVT \registers_reg[15][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_15__ap[15]), .CK(n_0_45), .Q(registers_15__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[8][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_8__ap[15]), .CK(n_0_38), .Q(registers_8__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_1002 (.A1(registers_15__ap[15]), .A2(n_1_0_1286), .B1( + n_1_0_1282), .B2(registers_8__ap[15]), .ZN(n_1_0_954)); + INV_X1_LVT i_1_0_1001 (.A(n_1_0_954), .ZN(n_1_0_953)); + SDFF_X1_LVT \registers_reg[11][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_11__ap[15]), .CK(n_0_41), .Q(registers_11__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[24][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_24__ap[15]), .CK(n_0_54), .Q(registers_24__ap[15]), .QN()); + AOI221_X1_LVT i_1_0_998 (.A(n_1_0_953), .B1(n_1_0_1270), .B2( + registers_11__ap[15]), .C1(registers_24__ap[15]), .C2(n_1_0_1289), + .ZN(n_1_0_950)); + SDFF_X1_LVT \registers_reg[13][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_13__ap[15]), .CK(n_0_43), .Q(registers_13__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[30][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_30__ap[15]), .CK(n_0_60), .Q(registers_30__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[22][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_22__ap[15]), .CK(n_0_52), .Q(registers_22__ap[15]), .QN()); + AOI222_X1_LVT i_1_0_997 (.A1(registers_13__ap[15]), .A2(n_1_0_1277), .B1( + n_1_0_1272), .B2(registers_30__ap[15]), .C1(registers_22__ap[15]), + .C2(n_1_0_1294), .ZN(n_1_0_949)); + NAND4_X1_LVT i_1_0_996 (.A1(n_1_0_955), .A2(n_1_0_951), .A3(n_1_0_950), + .A4(n_1_0_949), .ZN(n_1_0_948)); + SDFF_X1_LVT \registers_reg[1][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_1__ap[15]), .CK(n_0_0), .Q(registers_1__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[28][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_28__ap[15]), .CK(n_0_58), .Q(registers_28__ap[15]), .QN()); + AOI221_X1_LVT i_1_0_995 (.A(n_1_0_948), .B1(n_1_0_1274), .B2( + registers_1__ap[15]), .C1(registers_28__ap[15]), .C2(n_1_0_1283), .ZN( + n_1_0_947)); + SDFF_X1_LVT \registers_reg[18][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_18__ap[15]), .CK(n_0_48), .Q(registers_18__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[26][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_26__ap[15]), .CK(n_0_56), .Q(registers_26__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_994 (.A1(registers_18__ap[15]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[15]), .ZN(n_1_0_946)); + SDFF_X1_LVT \registers_reg[4][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_4__ap[15]), .CK(n_0_34), .Q(registers_4__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[5][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_5__ap[15]), .CK(n_0_35), .Q(registers_5__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_993 (.A1(registers_4__ap[15]), .A2(n_1_0_1278), .B1( + n_1_0_1273), .B2(registers_5__ap[15]), .ZN(n_1_0_945)); + SDFF_X1_LVT \registers_reg[6][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_6__ap[15]), .CK(n_0_36), .Q(registers_6__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[16][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_16__ap[15]), .CK(n_0_46), .Q(registers_16__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_992 (.A1(registers_6__ap[15]), .A2(n_1_0_1300), .B1( + n_1_0_1267), .B2(registers_16__ap[15]), .ZN(n_1_0_944)); + NAND3_X1_LVT i_1_0_991 (.A1(n_1_0_946), .A2(n_1_0_945), .A3(n_1_0_944), + .ZN(n_1_0_943)); + SDFF_X1_LVT \registers_reg[19][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_19__ap[15]), .CK(n_0_49), .Q(registers_19__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[25][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_25__ap[15]), .CK(n_0_55), .Q(registers_25__ap[15]), .QN()); + AOI221_X1_LVT i_1_0_990 (.A(n_1_0_943), .B1(n_1_0_1295), .B2( + registers_19__ap[15]), .C1(registers_25__ap[15]), .C2(n_1_0_1269), + .ZN(n_1_0_942)); + SDFF_X1_LVT \registers_reg[7][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_7__ap[15]), .CK(n_0_37), .Q(registers_7__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[14][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_14__ap[15]), .CK(n_0_44), .Q(registers_14__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_989 (.A1(registers_7__ap[15]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[15]), .ZN(n_1_0_941)); + SDFF_X1_LVT \registers_reg[9][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_9__ap[15]), .CK(n_0_39), .Q(registers_9__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[29][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_29__ap[15]), .CK(n_0_59), .Q(registers_29__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_988 (.A1(registers_9__ap[15]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[15]), .ZN(n_1_0_940)); + SDFF_X1_LVT \registers_reg[23][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_23__ap[15]), .CK(n_0_53), .Q(registers_23__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[3][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_3__ap[15]), .CK(n_0_33), .Q(registers_3__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_987 (.A1(registers_23__ap[15]), .A2(n_1_0_1264), .B1( + n_1_0_1257), .B2(registers_3__ap[15]), .ZN(n_1_0_939)); + NAND3_X1_LVT i_1_0_986 (.A1(n_1_0_941), .A2(n_1_0_940), .A3(n_1_0_939), + .ZN(n_1_0_938)); + SDFF_X1_LVT \registers_reg[27][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_27__ap[15]), .CK(n_0_57), .Q(registers_27__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[31][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_31__ap[15]), .CK(n_0_61), .Q(registers_31__ap[15]), .QN()); + AOI221_X1_LVT i_1_0_985 (.A(n_1_0_938), .B1(n_1_0_1279), .B2( + registers_27__ap[15]), .C1(registers_31__ap[15]), .C2(n_1_0_1266), + .ZN(n_1_0_937)); + NAND4_X1_LVT i_1_0_984 (.A1(n_1_0_952), .A2(n_1_0_947), .A3(n_1_0_942), + .A4(n_1_0_937), .ZN(RRs1[15])); + AND2_X1_LVT i_0_0_14 (.A1(n_0_0_16), .A2(WRd[14]), .ZN(registers[14])); + SDFF_X1_LVT \registers_reg[28][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_28__ap[14]), .CK(n_0_58), .Q(registers_28__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[5][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_5__ap[14]), .CK(n_0_35), .Q(registers_5__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_983 (.A1(registers_28__ap[14]), .A2(n_1_0_1283), .B1( + n_1_0_1273), .B2(registers_5__ap[14]), .ZN(n_1_0_936)); + SDFF_X1_LVT \registers_reg[18][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_18__ap[14]), .CK(n_0_48), .Q(registers_18__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[10][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_10__ap[14]), .CK(n_0_40), .Q(registers_10__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[8][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_8__ap[14]), .CK(n_0_38), .Q(registers_8__ap[14]), .QN()); + AOI222_X1_LVT i_1_0_982 (.A1(registers_18__ap[14]), .A2(n_1_0_1297), .B1( + n_1_0_1287), .B2(registers_10__ap[14]), .C1(n_1_0_1282), .C2( + registers_8__ap[14]), .ZN(n_1_0_935)); + SDFF_X1_LVT \registers_reg[9][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_9__ap[14]), .CK(n_0_39), .Q(registers_9__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[29][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_29__ap[14]), .CK(n_0_59), .Q(registers_29__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_981 (.A1(registers_9__ap[14]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[14]), .ZN(n_1_0_934)); + SDFF_X1_LVT \registers_reg[21][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_21__ap[14]), .CK(n_0_51), .Q(registers_21__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[14][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_14__ap[14]), .CK(n_0_44), .Q(registers_14__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_980 (.A1(registers_21__ap[14]), .A2(n_1_0_1259), .B1( + n_1_0_1258), .B2(registers_14__ap[14]), .ZN(n_1_0_933)); + SDFF_X1_LVT \registers_reg[16][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_16__ap[14]), .CK(n_0_46), .Q(registers_16__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[3][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_3__ap[14]), .CK(n_0_33), .Q(registers_3__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_979 (.A1(registers_16__ap[14]), .A2(n_1_0_1267), .B1( + n_1_0_1257), .B2(registers_3__ap[14]), .ZN(n_1_0_932)); + SDFF_X1_LVT \registers_reg[17][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_17__ap[14]), .CK(n_0_47), .Q(registers_17__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[31][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_31__ap[14]), .CK(n_0_61), .Q(registers_31__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_978 (.A1(registers_17__ap[14]), .A2(n_1_0_1271), .B1( + n_1_0_1266), .B2(registers_31__ap[14]), .ZN(n_1_0_931)); + SDFF_X1_LVT \registers_reg[15][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_15__ap[14]), .CK(n_0_45), .Q(registers_15__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[23][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_23__ap[14]), .CK(n_0_53), .Q(registers_23__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_977 (.A1(registers_15__ap[14]), .A2(n_1_0_1286), .B1( + n_1_0_1264), .B2(registers_23__ap[14]), .ZN(n_1_0_930)); + NAND4_X1_LVT i_1_0_976 (.A1(n_1_0_933), .A2(n_1_0_932), .A3(n_1_0_931), + .A4(n_1_0_930), .ZN(n_1_0_929)); + SDFF_X1_LVT \registers_reg[26][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_26__ap[14]), .CK(n_0_56), .Q(registers_26__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[30][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_30__ap[14]), .CK(n_0_60), .Q(registers_30__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_975 (.A1(registers_26__ap[14]), .A2(n_1_0_1285), .B1( + n_1_0_1272), .B2(registers_30__ap[14]), .ZN(n_1_0_928)); + SDFF_X1_LVT \registers_reg[20][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_20__ap[14]), .CK(n_0_50), .Q(registers_20__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[4][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_4__ap[14]), .CK(n_0_34), .Q(registers_4__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_974 (.A1(registers_20__ap[14]), .A2(n_1_0_1281), .B1( + n_1_0_1278), .B2(registers_4__ap[14]), .ZN(n_1_0_927)); + SDFF_X1_LVT \registers_reg[1][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_1__ap[14]), .CK(n_0_0), .Q(registers_1__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[2][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_2__ap[14]), .CK(n_0_32), .Q(registers_2__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_973 (.A1(registers_1__ap[14]), .A2(n_1_0_1274), .B1( + n_1_0_1268), .B2(registers_2__ap[14]), .ZN(n_1_0_926)); + SDFF_X1_LVT \registers_reg[24][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_24__ap[14]), .CK(n_0_54), .Q(registers_24__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[12][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_12__ap[14]), .CK(n_0_42), .Q(registers_12__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_972 (.A1(registers_24__ap[14]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[14]), .ZN(n_1_0_925)); + NAND4_X1_LVT i_1_0_971 (.A1(n_1_0_928), .A2(n_1_0_927), .A3(n_1_0_926), + .A4(n_1_0_925), .ZN(n_1_0_924)); + SDFF_X1_LVT \registers_reg[19][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_19__ap[14]), .CK(n_0_49), .Q(registers_19__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[22][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_22__ap[14]), .CK(n_0_52), .Q(registers_22__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_970 (.A1(registers_19__ap[14]), .A2(n_1_0_1295), .B1( + n_1_0_1294), .B2(registers_22__ap[14]), .ZN(n_1_0_923)); + SDFF_X1_LVT \registers_reg[13][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_13__ap[14]), .CK(n_0_43), .Q(registers_13__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[25][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_25__ap[14]), .CK(n_0_55), .Q(registers_25__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_969 (.A1(registers_13__ap[14]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[14]), .ZN(n_1_0_922)); + SDFF_X1_LVT \registers_reg[6][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_6__ap[14]), .CK(n_0_36), .Q(registers_6__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[7][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_7__ap[14]), .CK(n_0_37), .Q(registers_7__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_968 (.A1(registers_6__ap[14]), .A2(n_1_0_1300), .B1( + n_1_0_1263), .B2(registers_7__ap[14]), .ZN(n_1_0_921)); + SDFF_X1_LVT \registers_reg[27][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_27__ap[14]), .CK(n_0_57), .Q(registers_27__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[11][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_11__ap[14]), .CK(n_0_41), .Q(registers_11__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_967 (.A1(registers_27__ap[14]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[14]), .ZN(n_1_0_920)); + NAND4_X1_LVT i_1_0_966 (.A1(n_1_0_923), .A2(n_1_0_922), .A3(n_1_0_921), + .A4(n_1_0_920), .ZN(n_1_0_919)); + NOR3_X1_LVT i_1_0_965 (.A1(n_1_0_929), .A2(n_1_0_924), .A3(n_1_0_919), + .ZN(n_1_0_918)); + NAND4_X1_LVT i_1_0_964 (.A1(n_1_0_936), .A2(n_1_0_935), .A3(n_1_0_934), + .A4(n_1_0_918), .ZN(RRs1[14])); + AND2_X1_LVT i_0_0_13 (.A1(n_0_0_16), .A2(WRd[13]), .ZN(registers[13])); + SDFF_X1_LVT \registers_reg[28][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_28__ap[13]), .CK(n_0_58), .Q(registers_28__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[4][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_4__ap[13]), .CK(n_0_34), .Q(registers_4__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_963 (.A1(registers_28__ap[13]), .A2(n_1_0_1283), .B1( + n_1_0_1278), .B2(registers_4__ap[13]), .ZN(n_1_0_917)); + SDFF_X1_LVT \registers_reg[10][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_10__ap[13]), .CK(n_0_40), .Q(registers_10__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[26][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_26__ap[13]), .CK(n_0_56), .Q(registers_26__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[8][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_8__ap[13]), .CK(n_0_38), .Q(registers_8__ap[13]), .QN()); + AOI222_X1_LVT i_1_0_962 (.A1(registers_10__ap[13]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[13]), .C1(registers_8__ap[13]), .C2( + n_1_0_1282), .ZN(n_1_0_916)); + SDFF_X1_LVT \registers_reg[9][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_9__ap[13]), .CK(n_0_39), .Q(registers_9__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[29][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_29__ap[13]), .CK(n_0_59), .Q(registers_29__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_961 (.A1(registers_9__ap[13]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[13]), .ZN(n_1_0_915)); + SDFF_X1_LVT \registers_reg[6][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_6__ap[13]), .CK(n_0_36), .Q(registers_6__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[1][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_1__ap[13]), .CK(n_0_0), .Q(registers_1__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_960 (.A1(registers_6__ap[13]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[13]), .ZN(n_1_0_914)); + SDFF_X1_LVT \registers_reg[5][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_5__ap[13]), .CK(n_0_35), .Q(registers_5__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[3][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_3__ap[13]), .CK(n_0_33), .Q(registers_3__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_959 (.A1(registers_5__ap[13]), .A2(n_1_0_1273), .B1( + n_1_0_1257), .B2(registers_3__ap[13]), .ZN(n_1_0_913)); + SDFF_X1_LVT \registers_reg[16][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_16__ap[13]), .CK(n_0_46), .Q(registers_16__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[31][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_31__ap[13]), .CK(n_0_61), .Q(registers_31__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_958 (.A1(registers_16__ap[13]), .A2(n_1_0_1267), .B1( + n_1_0_1266), .B2(registers_31__ap[13]), .ZN(n_1_0_912)); + SDFF_X1_LVT \registers_reg[15][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_15__ap[13]), .CK(n_0_45), .Q(registers_15__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[23][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_23__ap[13]), .CK(n_0_53), .Q(registers_23__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_957 (.A1(registers_15__ap[13]), .A2(n_1_0_1286), .B1( + n_1_0_1264), .B2(registers_23__ap[13]), .ZN(n_1_0_911)); + NAND4_X1_LVT i_1_0_956 (.A1(n_1_0_914), .A2(n_1_0_913), .A3(n_1_0_912), + .A4(n_1_0_911), .ZN(n_1_0_910)); + SDFF_X1_LVT \registers_reg[18][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_18__ap[13]), .CK(n_0_48), .Q(registers_18__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[30][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_30__ap[13]), .CK(n_0_60), .Q(registers_30__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_955 (.A1(registers_18__ap[13]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[13]), .ZN(n_1_0_909)); + SDFF_X1_LVT \registers_reg[24][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_24__ap[13]), .CK(n_0_54), .Q(registers_24__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[12][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_12__ap[13]), .CK(n_0_42), .Q(registers_12__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_954 (.A1(registers_24__ap[13]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[13]), .ZN(n_1_0_908)); + SDFF_X1_LVT \registers_reg[22][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_22__ap[13]), .CK(n_0_52), .Q(registers_22__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[21][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_21__ap[13]), .CK(n_0_51), .Q(registers_21__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_953 (.A1(registers_22__ap[13]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[13]), .ZN(n_1_0_907)); + SDFF_X1_LVT \registers_reg[20][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_20__ap[13]), .CK(n_0_50), .Q(registers_20__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[17][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_17__ap[13]), .CK(n_0_47), .Q(registers_17__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_952 (.A1(registers_20__ap[13]), .A2(n_1_0_1281), .B1( + n_1_0_1271), .B2(registers_17__ap[13]), .ZN(n_1_0_906)); + NAND4_X1_LVT i_1_0_951 (.A1(n_1_0_909), .A2(n_1_0_908), .A3(n_1_0_907), + .A4(n_1_0_906), .ZN(n_1_0_905)); + SDFF_X1_LVT \registers_reg[13][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_13__ap[13]), .CK(n_0_43), .Q(registers_13__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[25][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_25__ap[13]), .CK(n_0_55), .Q(registers_25__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_950 (.A1(registers_13__ap[13]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[13]), .ZN(n_1_0_904)); + SDFF_X1_LVT \registers_reg[19][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_19__ap[13]), .CK(n_0_49), .Q(registers_19__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[2][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_2__ap[13]), .CK(n_0_32), .Q(registers_2__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_949 (.A1(registers_19__ap[13]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[13]), .ZN(n_1_0_903)); + SDFF_X1_LVT \registers_reg[7][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_7__ap[13]), .CK(n_0_37), .Q(registers_7__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[14][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_14__ap[13]), .CK(n_0_44), .Q(registers_14__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_948 (.A1(registers_7__ap[13]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[13]), .ZN(n_1_0_902)); + SDFF_X1_LVT \registers_reg[27][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_27__ap[13]), .CK(n_0_57), .Q(registers_27__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[11][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_11__ap[13]), .CK(n_0_41), .Q(registers_11__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_947 (.A1(registers_27__ap[13]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[13]), .ZN(n_1_0_901)); + NAND4_X1_LVT i_1_0_946 (.A1(n_1_0_904), .A2(n_1_0_903), .A3(n_1_0_902), + .A4(n_1_0_901), .ZN(n_1_0_900)); + NOR3_X1_LVT i_1_0_945 (.A1(n_1_0_910), .A2(n_1_0_905), .A3(n_1_0_900), + .ZN(n_1_0_899)); + NAND4_X1_LVT i_1_0_944 (.A1(n_1_0_917), .A2(n_1_0_916), .A3(n_1_0_915), + .A4(n_1_0_899), .ZN(RRs1[13])); + AND2_X1_LVT i_0_0_12 (.A1(n_0_0_16), .A2(WRd[12]), .ZN(registers[12])); + SDFF_X1_LVT \registers_reg[28][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_28__ap[12]), .CK(n_0_58), .Q(registers_28__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[17][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_17__ap[12]), .CK(n_0_47), .Q(registers_17__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_943 (.A1(registers_28__ap[12]), .A2(n_1_0_1283), .B1( + n_1_0_1271), .B2(registers_17__ap[12]), .ZN(n_1_0_898)); + SDFF_X1_LVT \registers_reg[10][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_10__ap[12]), .CK(n_0_40), .Q(registers_10__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[26][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_26__ap[12]), .CK(n_0_56), .Q(registers_26__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[8][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_8__ap[12]), .CK(n_0_38), .Q(registers_8__ap[12]), .QN()); + AOI222_X1_LVT i_1_0_942 (.A1(registers_10__ap[12]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[12]), .C1(registers_8__ap[12]), .C2( + n_1_0_1282), .ZN(n_1_0_897)); + SDFF_X1_LVT \registers_reg[9][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_9__ap[12]), .CK(n_0_39), .Q(registers_9__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[29][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_29__ap[12]), .CK(n_0_59), .Q(registers_29__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_941 (.A1(registers_9__ap[12]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[12]), .ZN(n_1_0_896)); + SDFF_X1_LVT \registers_reg[6][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_6__ap[12]), .CK(n_0_36), .Q(registers_6__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[1][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_1__ap[12]), .CK(n_0_0), .Q(registers_1__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_940 (.A1(registers_6__ap[12]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[12]), .ZN(n_1_0_895)); + SDFF_X1_LVT \registers_reg[16][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_16__ap[12]), .CK(n_0_46), .Q(registers_16__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[3][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_3__ap[12]), .CK(n_0_33), .Q(registers_3__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_939 (.A1(registers_16__ap[12]), .A2(n_1_0_1267), .B1( + n_1_0_1257), .B2(registers_3__ap[12]), .ZN(n_1_0_894)); + SDFF_X1_LVT \registers_reg[5][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_5__ap[12]), .CK(n_0_35), .Q(registers_5__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[31][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_31__ap[12]), .CK(n_0_61), .Q(registers_31__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_938 (.A1(registers_5__ap[12]), .A2(n_1_0_1273), .B1( + n_1_0_1266), .B2(registers_31__ap[12]), .ZN(n_1_0_893)); + SDFF_X1_LVT \registers_reg[15][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_15__ap[12]), .CK(n_0_45), .Q(registers_15__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[23][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_23__ap[12]), .CK(n_0_53), .Q(registers_23__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_937 (.A1(registers_15__ap[12]), .A2(n_1_0_1286), .B1( + n_1_0_1264), .B2(registers_23__ap[12]), .ZN(n_1_0_892)); + NAND4_X1_LVT i_1_0_936 (.A1(n_1_0_895), .A2(n_1_0_894), .A3(n_1_0_893), + .A4(n_1_0_892), .ZN(n_1_0_891)); + SDFF_X1_LVT \registers_reg[18][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_18__ap[12]), .CK(n_0_48), .Q(registers_18__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[30][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_30__ap[12]), .CK(n_0_60), .Q(registers_30__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_935 (.A1(registers_18__ap[12]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[12]), .ZN(n_1_0_890)); + SDFF_X1_LVT \registers_reg[20][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_20__ap[12]), .CK(n_0_50), .Q(registers_20__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[4][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_4__ap[12]), .CK(n_0_34), .Q(registers_4__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_934 (.A1(registers_20__ap[12]), .A2(n_1_0_1281), .B1( + n_1_0_1278), .B2(registers_4__ap[12]), .ZN(n_1_0_889)); + SDFF_X1_LVT \registers_reg[22][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_22__ap[12]), .CK(n_0_52), .Q(registers_22__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[21][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_21__ap[12]), .CK(n_0_51), .Q(registers_21__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_933 (.A1(registers_22__ap[12]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[12]), .ZN(n_1_0_888)); + SDFF_X1_LVT \registers_reg[24][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_24__ap[12]), .CK(n_0_54), .Q(registers_24__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[12][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_12__ap[12]), .CK(n_0_42), .Q(registers_12__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_932 (.A1(registers_24__ap[12]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[12]), .ZN(n_1_0_887)); + NAND4_X1_LVT i_1_0_931 (.A1(n_1_0_890), .A2(n_1_0_889), .A3(n_1_0_888), + .A4(n_1_0_887), .ZN(n_1_0_886)); + SDFF_X1_LVT \registers_reg[13][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_13__ap[12]), .CK(n_0_43), .Q(registers_13__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[25][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_25__ap[12]), .CK(n_0_55), .Q(registers_25__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_930 (.A1(registers_13__ap[12]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[12]), .ZN(n_1_0_885)); + SDFF_X1_LVT \registers_reg[19][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_19__ap[12]), .CK(n_0_49), .Q(registers_19__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[2][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_2__ap[12]), .CK(n_0_32), .Q(registers_2__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_929 (.A1(registers_19__ap[12]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[12]), .ZN(n_1_0_884)); + SDFF_X1_LVT \registers_reg[7][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_7__ap[12]), .CK(n_0_37), .Q(registers_7__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[14][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_14__ap[12]), .CK(n_0_44), .Q(registers_14__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_928 (.A1(registers_7__ap[12]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[12]), .ZN(n_1_0_883)); + SDFF_X1_LVT \registers_reg[27][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_27__ap[12]), .CK(n_0_57), .Q(registers_27__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[11][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_11__ap[12]), .CK(n_0_41), .Q(registers_11__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_927 (.A1(registers_27__ap[12]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[12]), .ZN(n_1_0_882)); + NAND4_X1_LVT i_1_0_926 (.A1(n_1_0_885), .A2(n_1_0_884), .A3(n_1_0_883), + .A4(n_1_0_882), .ZN(n_1_0_881)); + NOR3_X1_LVT i_1_0_925 (.A1(n_1_0_891), .A2(n_1_0_886), .A3(n_1_0_881), + .ZN(n_1_0_880)); + NAND4_X1_LVT i_1_0_924 (.A1(n_1_0_898), .A2(n_1_0_897), .A3(n_1_0_896), + .A4(n_1_0_880), .ZN(RRs1[12])); + AND2_X1_LVT i_0_0_11 (.A1(n_0_0_16), .A2(WRd[11]), .ZN(registers[11])); + SDFF_X1_LVT \registers_reg[28][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_28__ap[11]), .CK(n_0_58), .Q(registers_28__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[17][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_17__ap[11]), .CK(n_0_47), .Q(registers_17__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_923 (.A1(registers_28__ap[11]), .A2(n_1_0_1283), .B1( + n_1_0_1271), .B2(registers_17__ap[11]), .ZN(n_1_0_879)); + SDFF_X1_LVT \registers_reg[10][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_10__ap[11]), .CK(n_0_40), .Q(registers_10__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[26][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_26__ap[11]), .CK(n_0_56), .Q(registers_26__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[8][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_8__ap[11]), .CK(n_0_38), .Q(registers_8__ap[11]), .QN()); + AOI222_X1_LVT i_1_0_922 (.A1(registers_10__ap[11]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[11]), .C1(registers_8__ap[11]), .C2( + n_1_0_1282), .ZN(n_1_0_878)); + SDFF_X1_LVT \registers_reg[9][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_9__ap[11]), .CK(n_0_39), .Q(registers_9__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[29][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_29__ap[11]), .CK(n_0_59), .Q(registers_29__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_921 (.A1(registers_9__ap[11]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[11]), .ZN(n_1_0_877)); + SDFF_X1_LVT \registers_reg[6][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_6__ap[11]), .CK(n_0_36), .Q(registers_6__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[1][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_1__ap[11]), .CK(n_0_0), .Q(registers_1__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_920 (.A1(registers_6__ap[11]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[11]), .ZN(n_1_0_876)); + SDFF_X1_LVT \registers_reg[5][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_5__ap[11]), .CK(n_0_35), .Q(registers_5__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[3][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_3__ap[11]), .CK(n_0_33), .Q(registers_3__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_919 (.A1(registers_5__ap[11]), .A2(n_1_0_1273), .B1( + n_1_0_1257), .B2(registers_3__ap[11]), .ZN(n_1_0_875)); + SDFF_X1_LVT \registers_reg[16][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_16__ap[11]), .CK(n_0_46), .Q(registers_16__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[31][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_31__ap[11]), .CK(n_0_61), .Q(registers_31__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_918 (.A1(registers_16__ap[11]), .A2(n_1_0_1267), .B1( + n_1_0_1266), .B2(registers_31__ap[11]), .ZN(n_1_0_874)); + SDFF_X1_LVT \registers_reg[15][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_15__ap[11]), .CK(n_0_45), .Q(registers_15__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[23][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_23__ap[11]), .CK(n_0_53), .Q(registers_23__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_917 (.A1(registers_15__ap[11]), .A2(n_1_0_1286), .B1( + n_1_0_1264), .B2(registers_23__ap[11]), .ZN(n_1_0_873)); + NAND4_X1_LVT i_1_0_916 (.A1(n_1_0_876), .A2(n_1_0_875), .A3(n_1_0_874), + .A4(n_1_0_873), .ZN(n_1_0_872)); + SDFF_X1_LVT \registers_reg[18][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_18__ap[11]), .CK(n_0_48), .Q(registers_18__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[30][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_30__ap[11]), .CK(n_0_60), .Q(registers_30__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_915 (.A1(registers_18__ap[11]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[11]), .ZN(n_1_0_871)); + SDFF_X1_LVT \registers_reg[20][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_20__ap[11]), .CK(n_0_50), .Q(registers_20__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[4][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_4__ap[11]), .CK(n_0_34), .Q(registers_4__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_914 (.A1(registers_20__ap[11]), .A2(n_1_0_1281), .B1( + n_1_0_1278), .B2(registers_4__ap[11]), .ZN(n_1_0_870)); + SDFF_X1_LVT \registers_reg[22][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_22__ap[11]), .CK(n_0_52), .Q(registers_22__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[21][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_21__ap[11]), .CK(n_0_51), .Q(registers_21__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_913 (.A1(registers_22__ap[11]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[11]), .ZN(n_1_0_869)); + SDFF_X1_LVT \registers_reg[24][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_24__ap[11]), .CK(n_0_54), .Q(registers_24__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[12][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_12__ap[11]), .CK(n_0_42), .Q(registers_12__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_912 (.A1(registers_24__ap[11]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[11]), .ZN(n_1_0_868)); + NAND4_X1_LVT i_1_0_911 (.A1(n_1_0_871), .A2(n_1_0_870), .A3(n_1_0_869), + .A4(n_1_0_868), .ZN(n_1_0_867)); + SDFF_X1_LVT \registers_reg[13][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_13__ap[11]), .CK(n_0_43), .Q(registers_13__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[25][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_25__ap[11]), .CK(n_0_55), .Q(registers_25__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_910 (.A1(registers_13__ap[11]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[11]), .ZN(n_1_0_866)); + SDFF_X1_LVT \registers_reg[19][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_19__ap[11]), .CK(n_0_49), .Q(registers_19__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[2][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_2__ap[11]), .CK(n_0_32), .Q(registers_2__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_909 (.A1(registers_19__ap[11]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[11]), .ZN(n_1_0_865)); + SDFF_X1_LVT \registers_reg[7][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_7__ap[11]), .CK(n_0_37), .Q(registers_7__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[14][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_14__ap[11]), .CK(n_0_44), .Q(registers_14__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_908 (.A1(registers_7__ap[11]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[11]), .ZN(n_1_0_864)); + SDFF_X1_LVT \registers_reg[27][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_27__ap[11]), .CK(n_0_57), .Q(registers_27__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[11][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_11__ap[11]), .CK(n_0_41), .Q(registers_11__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_907 (.A1(registers_27__ap[11]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[11]), .ZN(n_1_0_863)); + NAND4_X1_LVT i_1_0_906 (.A1(n_1_0_866), .A2(n_1_0_865), .A3(n_1_0_864), + .A4(n_1_0_863), .ZN(n_1_0_862)); + NOR3_X1_LVT i_1_0_905 (.A1(n_1_0_872), .A2(n_1_0_867), .A3(n_1_0_862), + .ZN(n_1_0_861)); + NAND4_X1_LVT i_1_0_904 (.A1(n_1_0_879), .A2(n_1_0_878), .A3(n_1_0_877), + .A4(n_1_0_861), .ZN(RRs1[11])); + AND2_X1_LVT i_0_0_10 (.A1(n_0_0_16), .A2(WRd[10]), .ZN(registers[10])); + SDFF_X1_LVT \registers_reg[28][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_28__ap[10]), .CK(n_0_58), .Q(registers_28__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[8][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_8__ap[10]), .CK(n_0_38), .Q(registers_8__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_902 (.A1(registers_28__ap[10]), .A2(n_1_0_1283), .B1( + n_1_0_1282), .B2(registers_8__ap[10]), .ZN(n_1_0_859)); + SDFF_X1_LVT \registers_reg[31][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_31__ap[10]), .CK(n_0_61), .Q(registers_31__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[7][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_7__ap[10]), .CK(n_0_37), .Q(registers_7__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_903 (.A1(registers_31__ap[10]), .A2(n_1_0_1266), .B1( + n_1_0_1263), .B2(registers_7__ap[10]), .ZN(n_1_0_860)); + SDFF_X1_LVT \registers_reg[24][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_24__ap[10]), .CK(n_0_54), .Q(registers_24__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[20][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_20__ap[10]), .CK(n_0_50), .Q(registers_20__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_901 (.A1(registers_24__ap[10]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[10]), .ZN(n_1_0_858)); + SDFF_X1_LVT \registers_reg[4][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_4__ap[10]), .CK(n_0_34), .Q(registers_4__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[23][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_23__ap[10]), .CK(n_0_53), .Q(registers_23__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_900 (.A1(registers_4__ap[10]), .A2(n_1_0_1278), .B1( + n_1_0_1264), .B2(registers_23__ap[10]), .ZN(n_1_0_857)); + NAND3_X1_LVT i_1_0_899 (.A1(n_1_0_860), .A2(n_1_0_858), .A3(n_1_0_857), + .ZN(n_1_0_856)); + SDFF_X1_LVT \registers_reg[27][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_27__ap[10]), .CK(n_0_57), .Q(registers_27__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[29][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_29__ap[10]), .CK(n_0_59), .Q(registers_29__ap[10]), .QN()); + AOI221_X1_LVT i_1_0_898 (.A(n_1_0_856), .B1(n_1_0_1279), .B2( + registers_27__ap[10]), .C1(registers_29__ap[10]), .C2(n_1_0_1276), + .ZN(n_1_0_855)); + SDFF_X1_LVT \registers_reg[10][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_10__ap[10]), .CK(n_0_40), .Q(registers_10__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[30][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_30__ap[10]), .CK(n_0_60), .Q(registers_30__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[25][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_25__ap[10]), .CK(n_0_55), .Q(registers_25__ap[10]), .QN()); + AOI222_X1_LVT i_1_0_897 (.A1(registers_10__ap[10]), .A2(n_1_0_1287), .B1( + n_1_0_1272), .B2(registers_30__ap[10]), .C1(n_1_0_1269), .C2( + registers_25__ap[10]), .ZN(n_1_0_854)); + NAND3_X1_LVT i_1_0_896 (.A1(n_1_0_859), .A2(n_1_0_855), .A3(n_1_0_854), + .ZN(n_1_0_853)); + SDFF_X1_LVT \registers_reg[21][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_21__ap[10]), .CK(n_0_51), .Q(registers_21__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[13][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_13__ap[10]), .CK(n_0_43), .Q(registers_13__ap[10]), .QN()); + AOI221_X1_LVT i_1_0_895 (.A(n_1_0_853), .B1(n_1_0_1259), .B2( + registers_21__ap[10]), .C1(registers_13__ap[10]), .C2(n_1_0_1277), + .ZN(n_1_0_852)); + SDFF_X1_LVT \registers_reg[18][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_18__ap[10]), .CK(n_0_48), .Q(registers_18__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[26][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_26__ap[10]), .CK(n_0_56), .Q(registers_26__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_894 (.A1(registers_18__ap[10]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[10]), .ZN(n_1_0_851)); + SDFF_X1_LVT \registers_reg[17][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_17__ap[10]), .CK(n_0_47), .Q(registers_17__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[12][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_12__ap[10]), .CK(n_0_42), .Q(registers_12__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_893 (.A1(registers_17__ap[10]), .A2(n_1_0_1271), .B1( + n_1_0_1260), .B2(registers_12__ap[10]), .ZN(n_1_0_850)); + SDFF_X1_LVT \registers_reg[15][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_15__ap[10]), .CK(n_0_45), .Q(registers_15__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[5][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_5__ap[10]), .CK(n_0_35), .Q(registers_5__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_892 (.A1(registers_15__ap[10]), .A2(n_1_0_1286), .B1( + n_1_0_1273), .B2(registers_5__ap[10]), .ZN(n_1_0_849)); + NAND3_X1_LVT i_1_0_891 (.A1(n_1_0_851), .A2(n_1_0_850), .A3(n_1_0_849), + .ZN(n_1_0_848)); + SDFF_X1_LVT \registers_reg[22][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_22__ap[10]), .CK(n_0_52), .Q(registers_22__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[16][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_16__ap[10]), .CK(n_0_46), .Q(registers_16__ap[10]), .QN()); + AOI221_X1_LVT i_1_0_890 (.A(n_1_0_848), .B1(n_1_0_1294), .B2( + registers_22__ap[10]), .C1(registers_16__ap[10]), .C2(n_1_0_1267), + .ZN(n_1_0_847)); + SDFF_X1_LVT \registers_reg[9][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_9__ap[10]), .CK(n_0_39), .Q(registers_9__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[1][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_1__ap[10]), .CK(n_0_0), .Q(registers_1__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_889 (.A1(registers_9__ap[10]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[10]), .ZN(n_1_0_846)); + SDFF_X1_LVT \registers_reg[6][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_6__ap[10]), .CK(n_0_36), .Q(registers_6__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[14][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_14__ap[10]), .CK(n_0_44), .Q(registers_14__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_888 (.A1(registers_6__ap[10]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[10]), .ZN(n_1_0_845)); + SDFF_X1_LVT \registers_reg[19][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_19__ap[10]), .CK(n_0_49), .Q(registers_19__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[3][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_3__ap[10]), .CK(n_0_33), .Q(registers_3__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_887 (.A1(registers_19__ap[10]), .A2(n_1_0_1295), .B1( + n_1_0_1257), .B2(registers_3__ap[10]), .ZN(n_1_0_844)); + NAND3_X1_LVT i_1_0_886 (.A1(n_1_0_846), .A2(n_1_0_845), .A3(n_1_0_844), + .ZN(n_1_0_843)); + SDFF_X1_LVT \registers_reg[11][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_11__ap[10]), .CK(n_0_41), .Q(registers_11__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[2][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_2__ap[10]), .CK(n_0_32), .Q(registers_2__ap[10]), .QN()); + AOI221_X1_LVT i_1_0_885 (.A(n_1_0_843), .B1(n_1_0_1270), .B2( + registers_11__ap[10]), .C1(registers_2__ap[10]), .C2(n_1_0_1268), .ZN( + n_1_0_842)); + NAND3_X1_LVT i_1_0_884 (.A1(n_1_0_852), .A2(n_1_0_847), .A3(n_1_0_842), + .ZN(RRs1[10])); + AND2_X1_LVT i_0_0_9 (.A1(n_0_0_16), .A2(WRd[9]), .ZN(registers[9])); + SDFF_X1_LVT \registers_reg[13][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_13__ap[9]), .CK(n_0_43), .Q(registers_13__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[21][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_21__ap[9]), .CK(n_0_51), .Q(registers_21__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_880 (.A1(registers_13__ap[9]), .A2(n_1_0_1277), .B1( + n_1_0_1259), .B2(registers_21__ap[9]), .ZN(n_1_0_838)); + SDFF_X1_LVT \registers_reg[29][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_29__ap[9]), .CK(n_0_59), .Q(registers_29__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[23][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_23__ap[9]), .CK(n_0_53), .Q(registers_23__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_883 (.A1(registers_29__ap[9]), .A2(n_1_0_1276), .B1( + n_1_0_1264), .B2(registers_23__ap[9]), .ZN(n_1_0_841)); + SDFF_X1_LVT \registers_reg[24][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_24__ap[9]), .CK(n_0_54), .Q(registers_24__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[20][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_20__ap[9]), .CK(n_0_50), .Q(registers_20__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_879 (.A1(registers_24__ap[9]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[9]), .ZN(n_1_0_837)); + SDFF_X1_LVT \registers_reg[7][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_7__ap[9]), .CK(n_0_37), .Q(registers_7__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[3][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_3__ap[9]), .CK(n_0_33), .Q(registers_3__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_882 (.A1(registers_7__ap[9]), .A2(n_1_0_1263), .B1( + n_1_0_1257), .B2(registers_3__ap[9]), .ZN(n_1_0_840)); + INV_X1_LVT i_1_0_881 (.A(n_1_0_840), .ZN(n_1_0_839)); + SDFF_X1_LVT \registers_reg[31][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_31__ap[9]), .CK(n_0_61), .Q(registers_31__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[4][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_4__ap[9]), .CK(n_0_34), .Q(registers_4__ap[9]), .QN()); + AOI221_X1_LVT i_1_0_878 (.A(n_1_0_839), .B1(n_1_0_1266), .B2( + registers_31__ap[9]), .C1(registers_4__ap[9]), .C2(n_1_0_1278), .ZN( + n_1_0_836)); + SDFF_X1_LVT \registers_reg[10][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_10__ap[9]), .CK(n_0_40), .Q(registers_10__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[26][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_26__ap[9]), .CK(n_0_56), .Q(registers_26__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[25][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_25__ap[9]), .CK(n_0_55), .Q(registers_25__ap[9]), .QN()); + AOI222_X1_LVT i_1_0_877 (.A1(registers_10__ap[9]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[9]), .C1(registers_25__ap[9]), .C2( + n_1_0_1269), .ZN(n_1_0_835)); + NAND4_X1_LVT i_1_0_876 (.A1(n_1_0_841), .A2(n_1_0_837), .A3(n_1_0_836), + .A4(n_1_0_835), .ZN(n_1_0_834)); + SDFF_X1_LVT \registers_reg[8][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_8__ap[9]), .CK(n_0_38), .Q(registers_8__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[28][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_28__ap[9]), .CK(n_0_58), .Q(registers_28__ap[9]), .QN()); + AOI221_X1_LVT i_1_0_875 (.A(n_1_0_834), .B1(n_1_0_1282), .B2( + registers_8__ap[9]), .C1(registers_28__ap[9]), .C2(n_1_0_1283), .ZN( + n_1_0_833)); + SDFF_X1_LVT \registers_reg[18][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_18__ap[9]), .CK(n_0_48), .Q(registers_18__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[30][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_30__ap[9]), .CK(n_0_60), .Q(registers_30__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_874 (.A1(registers_18__ap[9]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[9]), .ZN(n_1_0_832)); + SDFF_X1_LVT \registers_reg[17][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_17__ap[9]), .CK(n_0_47), .Q(registers_17__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[12][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_12__ap[9]), .CK(n_0_42), .Q(registers_12__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_873 (.A1(registers_17__ap[9]), .A2(n_1_0_1271), .B1( + n_1_0_1260), .B2(registers_12__ap[9]), .ZN(n_1_0_831)); + SDFF_X1_LVT \registers_reg[15][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_15__ap[9]), .CK(n_0_45), .Q(registers_15__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[5][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_5__ap[9]), .CK(n_0_35), .Q(registers_5__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_872 (.A1(registers_15__ap[9]), .A2(n_1_0_1286), .B1( + n_1_0_1273), .B2(registers_5__ap[9]), .ZN(n_1_0_830)); + NAND3_X1_LVT i_1_0_871 (.A1(n_1_0_832), .A2(n_1_0_831), .A3(n_1_0_830), + .ZN(n_1_0_829)); + SDFF_X1_LVT \registers_reg[22][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_22__ap[9]), .CK(n_0_52), .Q(registers_22__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[16][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_16__ap[9]), .CK(n_0_46), .Q(registers_16__ap[9]), .QN()); + AOI221_X1_LVT i_1_0_870 (.A(n_1_0_829), .B1(n_1_0_1294), .B2( + registers_22__ap[9]), .C1(registers_16__ap[9]), .C2(n_1_0_1267), .ZN( + n_1_0_828)); + SDFF_X1_LVT \registers_reg[9][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_9__ap[9]), .CK(n_0_39), .Q(registers_9__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[1][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_1__ap[9]), .CK(n_0_0), .Q(registers_1__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_869 (.A1(registers_9__ap[9]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[9]), .ZN(n_1_0_827)); + SDFF_X1_LVT \registers_reg[6][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_6__ap[9]), .CK(n_0_36), .Q(registers_6__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[14][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_14__ap[9]), .CK(n_0_44), .Q(registers_14__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_868 (.A1(registers_6__ap[9]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[9]), .ZN(n_1_0_826)); + SDFF_X1_LVT \registers_reg[19][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_19__ap[9]), .CK(n_0_49), .Q(registers_19__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[2][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_2__ap[9]), .CK(n_0_32), .Q(registers_2__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_867 (.A1(registers_19__ap[9]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[9]), .ZN(n_1_0_825)); + NAND3_X1_LVT i_1_0_866 (.A1(n_1_0_827), .A2(n_1_0_826), .A3(n_1_0_825), + .ZN(n_1_0_824)); + SDFF_X1_LVT \registers_reg[11][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_11__ap[9]), .CK(n_0_41), .Q(registers_11__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[27][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_27__ap[9]), .CK(n_0_57), .Q(registers_27__ap[9]), .QN()); + AOI221_X1_LVT i_1_0_865 (.A(n_1_0_824), .B1(n_1_0_1270), .B2( + registers_11__ap[9]), .C1(registers_27__ap[9]), .C2(n_1_0_1279), .ZN( + n_1_0_823)); + NAND4_X1_LVT i_1_0_864 (.A1(n_1_0_838), .A2(n_1_0_833), .A3(n_1_0_828), + .A4(n_1_0_823), .ZN(RRs1[9])); + AND2_X1_LVT i_0_0_8 (.A1(n_0_0_16), .A2(WRd[8]), .ZN(registers[8])); + SDFF_X1_LVT \registers_reg[13][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_13__ap[8]), .CK(n_0_43), .Q(registers_13__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[21][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_21__ap[8]), .CK(n_0_51), .Q(registers_21__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_860 (.A1(registers_13__ap[8]), .A2(n_1_0_1277), .B1( + n_1_0_1259), .B2(registers_21__ap[8]), .ZN(n_1_0_819)); + SDFF_X1_LVT \registers_reg[29][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_29__ap[8]), .CK(n_0_59), .Q(registers_29__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[23][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_23__ap[8]), .CK(n_0_53), .Q(registers_23__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_863 (.A1(registers_29__ap[8]), .A2(n_1_0_1276), .B1( + n_1_0_1264), .B2(registers_23__ap[8]), .ZN(n_1_0_822)); + SDFF_X1_LVT \registers_reg[24][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_24__ap[8]), .CK(n_0_54), .Q(registers_24__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[20][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_20__ap[8]), .CK(n_0_50), .Q(registers_20__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_859 (.A1(registers_24__ap[8]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[8]), .ZN(n_1_0_818)); + SDFF_X1_LVT \registers_reg[7][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_7__ap[8]), .CK(n_0_37), .Q(registers_7__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[3][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_3__ap[8]), .CK(n_0_33), .Q(registers_3__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_862 (.A1(registers_7__ap[8]), .A2(n_1_0_1263), .B1( + n_1_0_1257), .B2(registers_3__ap[8]), .ZN(n_1_0_821)); + INV_X1_LVT i_1_0_861 (.A(n_1_0_821), .ZN(n_1_0_820)); + SDFF_X1_LVT \registers_reg[31][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_31__ap[8]), .CK(n_0_61), .Q(registers_31__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[4][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_4__ap[8]), .CK(n_0_34), .Q(registers_4__ap[8]), .QN()); + AOI221_X1_LVT i_1_0_858 (.A(n_1_0_820), .B1(n_1_0_1266), .B2( + registers_31__ap[8]), .C1(registers_4__ap[8]), .C2(n_1_0_1278), .ZN( + n_1_0_817)); + SDFF_X1_LVT \registers_reg[10][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_10__ap[8]), .CK(n_0_40), .Q(registers_10__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[26][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_26__ap[8]), .CK(n_0_56), .Q(registers_26__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[25][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_25__ap[8]), .CK(n_0_55), .Q(registers_25__ap[8]), .QN()); + AOI222_X1_LVT i_1_0_857 (.A1(registers_10__ap[8]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[8]), .C1(registers_25__ap[8]), .C2( + n_1_0_1269), .ZN(n_1_0_816)); + NAND4_X1_LVT i_1_0_856 (.A1(n_1_0_822), .A2(n_1_0_818), .A3(n_1_0_817), + .A4(n_1_0_816), .ZN(n_1_0_815)); + SDFF_X1_LVT \registers_reg[8][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_8__ap[8]), .CK(n_0_38), .Q(registers_8__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[28][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_28__ap[8]), .CK(n_0_58), .Q(registers_28__ap[8]), .QN()); + AOI221_X1_LVT i_1_0_855 (.A(n_1_0_815), .B1(n_1_0_1282), .B2( + registers_8__ap[8]), .C1(registers_28__ap[8]), .C2(n_1_0_1283), .ZN( + n_1_0_814)); + SDFF_X1_LVT \registers_reg[18][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_18__ap[8]), .CK(n_0_48), .Q(registers_18__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[30][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_30__ap[8]), .CK(n_0_60), .Q(registers_30__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_854 (.A1(registers_18__ap[8]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[8]), .ZN(n_1_0_813)); + SDFF_X1_LVT \registers_reg[17][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_17__ap[8]), .CK(n_0_47), .Q(registers_17__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[12][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_12__ap[8]), .CK(n_0_42), .Q(registers_12__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_853 (.A1(registers_17__ap[8]), .A2(n_1_0_1271), .B1( + n_1_0_1260), .B2(registers_12__ap[8]), .ZN(n_1_0_812)); + SDFF_X1_LVT \registers_reg[15][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_15__ap[8]), .CK(n_0_45), .Q(registers_15__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[5][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_5__ap[8]), .CK(n_0_35), .Q(registers_5__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_852 (.A1(registers_15__ap[8]), .A2(n_1_0_1286), .B1( + n_1_0_1273), .B2(registers_5__ap[8]), .ZN(n_1_0_811)); + NAND3_X1_LVT i_1_0_851 (.A1(n_1_0_813), .A2(n_1_0_812), .A3(n_1_0_811), + .ZN(n_1_0_810)); + SDFF_X1_LVT \registers_reg[22][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_22__ap[8]), .CK(n_0_52), .Q(registers_22__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[16][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_16__ap[8]), .CK(n_0_46), .Q(registers_16__ap[8]), .QN()); + AOI221_X1_LVT i_1_0_850 (.A(n_1_0_810), .B1(n_1_0_1294), .B2( + registers_22__ap[8]), .C1(registers_16__ap[8]), .C2(n_1_0_1267), .ZN( + n_1_0_809)); + SDFF_X1_LVT \registers_reg[9][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_9__ap[8]), .CK(n_0_39), .Q(registers_9__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[1][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_1__ap[8]), .CK(n_0_0), .Q(registers_1__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_849 (.A1(registers_9__ap[8]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[8]), .ZN(n_1_0_808)); + SDFF_X1_LVT \registers_reg[6][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_6__ap[8]), .CK(n_0_36), .Q(registers_6__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[14][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_14__ap[8]), .CK(n_0_44), .Q(registers_14__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_848 (.A1(registers_6__ap[8]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[8]), .ZN(n_1_0_807)); + SDFF_X1_LVT \registers_reg[19][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_19__ap[8]), .CK(n_0_49), .Q(registers_19__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[2][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_2__ap[8]), .CK(n_0_32), .Q(registers_2__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_847 (.A1(registers_19__ap[8]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[8]), .ZN(n_1_0_806)); + NAND3_X1_LVT i_1_0_846 (.A1(n_1_0_808), .A2(n_1_0_807), .A3(n_1_0_806), + .ZN(n_1_0_805)); + SDFF_X1_LVT \registers_reg[11][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_11__ap[8]), .CK(n_0_41), .Q(registers_11__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[27][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_27__ap[8]), .CK(n_0_57), .Q(registers_27__ap[8]), .QN()); + AOI221_X1_LVT i_1_0_845 (.A(n_1_0_805), .B1(n_1_0_1270), .B2( + registers_11__ap[8]), .C1(registers_27__ap[8]), .C2(n_1_0_1279), .ZN( + n_1_0_804)); + NAND4_X1_LVT i_1_0_844 (.A1(n_1_0_819), .A2(n_1_0_814), .A3(n_1_0_809), + .A4(n_1_0_804), .ZN(RRs1[8])); + AND2_X1_LVT i_0_0_7 (.A1(n_0_0_16), .A2(WRd[7]), .ZN(registers[7])); + SDFF_X1_LVT \registers_reg[13][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_13__ap[7]), .CK(n_0_43), .Q(registers_13__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[21][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_21__ap[7]), .CK(n_0_51), .Q(registers_21__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_843 (.A1(registers_13__ap[7]), .A2(n_1_0_1277), .B1( + n_1_0_1259), .B2(registers_21__ap[7]), .ZN(n_1_0_803)); + SDFF_X1_LVT \registers_reg[18][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_18__ap[7]), .CK(n_0_48), .Q(registers_18__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[10][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_10__ap[7]), .CK(n_0_40), .Q(registers_10__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[25][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_25__ap[7]), .CK(n_0_55), .Q(registers_25__ap[7]), .QN()); + AOI222_X1_LVT i_1_0_842 (.A1(registers_18__ap[7]), .A2(n_1_0_1297), .B1( + n_1_0_1287), .B2(registers_10__ap[7]), .C1(registers_25__ap[7]), .C2( + n_1_0_1269), .ZN(n_1_0_802)); + SDFF_X1_LVT \registers_reg[28][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_28__ap[7]), .CK(n_0_58), .Q(registers_28__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[8][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_8__ap[7]), .CK(n_0_38), .Q(registers_8__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_841 (.A1(registers_28__ap[7]), .A2(n_1_0_1283), .B1( + n_1_0_1282), .B2(registers_8__ap[7]), .ZN(n_1_0_801)); + SDFF_X1_LVT \registers_reg[24][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_24__ap[7]), .CK(n_0_54), .Q(registers_24__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[20][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_20__ap[7]), .CK(n_0_50), .Q(registers_20__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_840 (.A1(registers_24__ap[7]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[7]), .ZN(n_1_0_800)); + SDFF_X1_LVT \registers_reg[31][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_31__ap[7]), .CK(n_0_61), .Q(registers_31__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[7][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_7__ap[7]), .CK(n_0_37), .Q(registers_7__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_839 (.A1(registers_31__ap[7]), .A2(n_1_0_1266), .B1( + n_1_0_1263), .B2(registers_7__ap[7]), .ZN(n_1_0_799)); + SDFF_X1_LVT \registers_reg[17][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_17__ap[7]), .CK(n_0_47), .Q(registers_17__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[11][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_11__ap[7]), .CK(n_0_41), .Q(registers_11__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_838 (.A1(registers_17__ap[7]), .A2(n_1_0_1271), .B1( + n_1_0_1270), .B2(registers_11__ap[7]), .ZN(n_1_0_798)); + SDFF_X1_LVT \registers_reg[27][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_27__ap[7]), .CK(n_0_57), .Q(registers_27__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[29][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_29__ap[7]), .CK(n_0_59), .Q(registers_29__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_837 (.A1(registers_27__ap[7]), .A2(n_1_0_1279), .B1( + n_1_0_1276), .B2(registers_29__ap[7]), .ZN(n_1_0_797)); + NAND4_X1_LVT i_1_0_836 (.A1(n_1_0_800), .A2(n_1_0_799), .A3(n_1_0_798), + .A4(n_1_0_797), .ZN(n_1_0_796)); + SDFF_X1_LVT \registers_reg[26][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_26__ap[7]), .CK(n_0_56), .Q(registers_26__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[30][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_30__ap[7]), .CK(n_0_60), .Q(registers_30__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_835 (.A1(registers_26__ap[7]), .A2(n_1_0_1285), .B1( + n_1_0_1272), .B2(registers_30__ap[7]), .ZN(n_1_0_795)); + SDFF_X1_LVT \registers_reg[4][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_4__ap[7]), .CK(n_0_34), .Q(registers_4__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[12][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_12__ap[7]), .CK(n_0_42), .Q(registers_12__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_834 (.A1(registers_4__ap[7]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[7]), .ZN(n_1_0_794)); + SDFF_X1_LVT \registers_reg[15][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_15__ap[7]), .CK(n_0_45), .Q(registers_15__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[16][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_16__ap[7]), .CK(n_0_46), .Q(registers_16__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_833 (.A1(registers_15__ap[7]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[7]), .ZN(n_1_0_793)); + SDFF_X1_LVT \registers_reg[22][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_22__ap[7]), .CK(n_0_52), .Q(registers_22__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[5][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_5__ap[7]), .CK(n_0_35), .Q(registers_5__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_832 (.A1(registers_22__ap[7]), .A2(n_1_0_1294), .B1( + n_1_0_1273), .B2(registers_5__ap[7]), .ZN(n_1_0_792)); + NAND4_X1_LVT i_1_0_831 (.A1(n_1_0_795), .A2(n_1_0_794), .A3(n_1_0_793), + .A4(n_1_0_792), .ZN(n_1_0_791)); + SDFF_X1_LVT \registers_reg[19][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_19__ap[7]), .CK(n_0_49), .Q(registers_19__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[3][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_3__ap[7]), .CK(n_0_33), .Q(registers_3__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_830 (.A1(registers_19__ap[7]), .A2(n_1_0_1295), .B1( + n_1_0_1257), .B2(registers_3__ap[7]), .ZN(n_1_0_790)); + SDFF_X1_LVT \registers_reg[9][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_9__ap[7]), .CK(n_0_39), .Q(registers_9__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[1][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_1__ap[7]), .CK(n_0_0), .Q(registers_1__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_829 (.A1(registers_9__ap[7]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[7]), .ZN(n_1_0_789)); + SDFF_X1_LVT \registers_reg[6][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_6__ap[7]), .CK(n_0_36), .Q(registers_6__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[14][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_14__ap[7]), .CK(n_0_44), .Q(registers_14__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_828 (.A1(registers_6__ap[7]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[7]), .ZN(n_1_0_788)); + SDFF_X1_LVT \registers_reg[2][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_2__ap[7]), .CK(n_0_32), .Q(registers_2__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[23][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_23__ap[7]), .CK(n_0_53), .Q(registers_23__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_827 (.A1(registers_2__ap[7]), .A2(n_1_0_1268), .B1( + n_1_0_1264), .B2(registers_23__ap[7]), .ZN(n_1_0_787)); + NAND4_X1_LVT i_1_0_826 (.A1(n_1_0_790), .A2(n_1_0_789), .A3(n_1_0_788), + .A4(n_1_0_787), .ZN(n_1_0_786)); + NOR3_X1_LVT i_1_0_825 (.A1(n_1_0_796), .A2(n_1_0_791), .A3(n_1_0_786), + .ZN(n_1_0_785)); + NAND4_X1_LVT i_1_0_824 (.A1(n_1_0_803), .A2(n_1_0_802), .A3(n_1_0_801), + .A4(n_1_0_785), .ZN(RRs1[7])); + AND2_X1_LVT i_0_0_6 (.A1(n_0_0_16), .A2(WRd[6]), .ZN(registers[6])); + SDFF_X1_LVT \registers_reg[28][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_28__ap[6]), .CK(n_0_58), .Q(registers_28__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[17][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_17__ap[6]), .CK(n_0_47), .Q(registers_17__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_823 (.A1(registers_28__ap[6]), .A2(n_1_0_1283), .B1( + n_1_0_1271), .B2(registers_17__ap[6]), .ZN(n_1_0_784)); + SDFF_X1_LVT \registers_reg[18][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_18__ap[6]), .CK(n_0_48), .Q(registers_18__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[10][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_10__ap[6]), .CK(n_0_40), .Q(registers_10__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[8][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_8__ap[6]), .CK(n_0_38), .Q(registers_8__ap[6]), .QN()); + AOI222_X1_LVT i_1_0_822 (.A1(registers_18__ap[6]), .A2(n_1_0_1297), .B1( + n_1_0_1287), .B2(registers_10__ap[6]), .C1(registers_8__ap[6]), .C2( + n_1_0_1282), .ZN(n_1_0_783)); + SDFF_X1_LVT \registers_reg[9][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_9__ap[6]), .CK(n_0_39), .Q(registers_9__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[29][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_29__ap[6]), .CK(n_0_59), .Q(registers_29__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_821 (.A1(registers_9__ap[6]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[6]), .ZN(n_1_0_782)); + SDFF_X1_LVT \registers_reg[6][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_6__ap[6]), .CK(n_0_36), .Q(registers_6__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[1][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_1__ap[6]), .CK(n_0_0), .Q(registers_1__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_820 (.A1(registers_6__ap[6]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[6]), .ZN(n_1_0_781)); + SDFF_X1_LVT \registers_reg[15][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_15__ap[6]), .CK(n_0_45), .Q(registers_15__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[27][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_27__ap[6]), .CK(n_0_57), .Q(registers_27__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_819 (.A1(registers_15__ap[6]), .A2(n_1_0_1286), .B1( + n_1_0_1279), .B2(registers_27__ap[6]), .ZN(n_1_0_780)); + SDFF_X1_LVT \registers_reg[11][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_11__ap[6]), .CK(n_0_41), .Q(registers_11__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[16][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_16__ap[6]), .CK(n_0_46), .Q(registers_16__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_818 (.A1(registers_11__ap[6]), .A2(n_1_0_1270), .B1( + n_1_0_1267), .B2(registers_16__ap[6]), .ZN(n_1_0_779)); + SDFF_X1_LVT \registers_reg[5][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_5__ap[6]), .CK(n_0_35), .Q(registers_5__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[31][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_31__ap[6]), .CK(n_0_61), .Q(registers_31__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_817 (.A1(registers_5__ap[6]), .A2(n_1_0_1273), .B1( + n_1_0_1266), .B2(registers_31__ap[6]), .ZN(n_1_0_778)); + NAND4_X1_LVT i_1_0_816 (.A1(n_1_0_781), .A2(n_1_0_780), .A3(n_1_0_779), + .A4(n_1_0_778), .ZN(n_1_0_777)); + SDFF_X1_LVT \registers_reg[26][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_26__ap[6]), .CK(n_0_56), .Q(registers_26__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[30][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_30__ap[6]), .CK(n_0_60), .Q(registers_30__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_815 (.A1(registers_26__ap[6]), .A2(n_1_0_1285), .B1( + n_1_0_1272), .B2(registers_30__ap[6]), .ZN(n_1_0_776)); + SDFF_X1_LVT \registers_reg[20][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_20__ap[6]), .CK(n_0_50), .Q(registers_20__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[4][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_4__ap[6]), .CK(n_0_34), .Q(registers_4__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_814 (.A1(registers_20__ap[6]), .A2(n_1_0_1281), .B1( + n_1_0_1278), .B2(registers_4__ap[6]), .ZN(n_1_0_775)); + SDFF_X1_LVT \registers_reg[22][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_22__ap[6]), .CK(n_0_52), .Q(registers_22__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[21][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_21__ap[6]), .CK(n_0_51), .Q(registers_21__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_813 (.A1(registers_22__ap[6]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[6]), .ZN(n_1_0_774)); + SDFF_X1_LVT \registers_reg[24][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_24__ap[6]), .CK(n_0_54), .Q(registers_24__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[12][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_12__ap[6]), .CK(n_0_42), .Q(registers_12__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_812 (.A1(registers_24__ap[6]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[6]), .ZN(n_1_0_773)); + NAND4_X1_LVT i_1_0_811 (.A1(n_1_0_776), .A2(n_1_0_775), .A3(n_1_0_774), + .A4(n_1_0_773), .ZN(n_1_0_772)); + SDFF_X1_LVT \registers_reg[13][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_13__ap[6]), .CK(n_0_43), .Q(registers_13__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[25][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_25__ap[6]), .CK(n_0_55), .Q(registers_25__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_810 (.A1(registers_13__ap[6]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[6]), .ZN(n_1_0_771)); + SDFF_X1_LVT \registers_reg[7][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_7__ap[6]), .CK(n_0_37), .Q(registers_7__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[14][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_14__ap[6]), .CK(n_0_44), .Q(registers_14__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_809 (.A1(registers_7__ap[6]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[6]), .ZN(n_1_0_770)); + SDFF_X1_LVT \registers_reg[19][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_19__ap[6]), .CK(n_0_49), .Q(registers_19__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[3][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_3__ap[6]), .CK(n_0_33), .Q(registers_3__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_808 (.A1(registers_19__ap[6]), .A2(n_1_0_1295), .B1( + n_1_0_1257), .B2(registers_3__ap[6]), .ZN(n_1_0_769)); + SDFF_X1_LVT \registers_reg[2][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_2__ap[6]), .CK(n_0_32), .Q(registers_2__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[23][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_23__ap[6]), .CK(n_0_53), .Q(registers_23__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_807 (.A1(registers_2__ap[6]), .A2(n_1_0_1268), .B1( + n_1_0_1264), .B2(registers_23__ap[6]), .ZN(n_1_0_768)); + NAND4_X1_LVT i_1_0_806 (.A1(n_1_0_771), .A2(n_1_0_770), .A3(n_1_0_769), + .A4(n_1_0_768), .ZN(n_1_0_767)); + NOR3_X1_LVT i_1_0_805 (.A1(n_1_0_777), .A2(n_1_0_772), .A3(n_1_0_767), + .ZN(n_1_0_766)); + NAND4_X1_LVT i_1_0_804 (.A1(n_1_0_784), .A2(n_1_0_783), .A3(n_1_0_782), + .A4(n_1_0_766), .ZN(RRs1[6])); + AND2_X1_LVT i_0_0_5 (.A1(n_0_0_16), .A2(WRd[5]), .ZN(registers[5])); + SDFF_X1_LVT \registers_reg[28][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_28__ap[5]), .CK(n_0_58), .Q(registers_28__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[4][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_4__ap[5]), .CK(n_0_34), .Q(registers_4__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_803 (.A1(registers_28__ap[5]), .A2(n_1_0_1283), .B1( + n_1_0_1278), .B2(registers_4__ap[5]), .ZN(n_1_0_765)); + SDFF_X1_LVT \registers_reg[10][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_10__ap[5]), .CK(n_0_40), .Q(registers_10__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[26][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_26__ap[5]), .CK(n_0_56), .Q(registers_26__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[8][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_8__ap[5]), .CK(n_0_38), .Q(registers_8__ap[5]), .QN()); + AOI222_X1_LVT i_1_0_802 (.A1(registers_10__ap[5]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[5]), .C1(registers_8__ap[5]), .C2( + n_1_0_1282), .ZN(n_1_0_764)); + SDFF_X1_LVT \registers_reg[9][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_9__ap[5]), .CK(n_0_39), .Q(registers_9__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[29][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_29__ap[5]), .CK(n_0_59), .Q(registers_29__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_801 (.A1(registers_9__ap[5]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[5]), .ZN(n_1_0_763)); + SDFF_X1_LVT \registers_reg[6][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_6__ap[5]), .CK(n_0_36), .Q(registers_6__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[1][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_1__ap[5]), .CK(n_0_0), .Q(registers_1__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_800 (.A1(registers_6__ap[5]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[5]), .ZN(n_1_0_762)); + SDFF_X1_LVT \registers_reg[16][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_16__ap[5]), .CK(n_0_46), .Q(registers_16__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[3][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_3__ap[5]), .CK(n_0_33), .Q(registers_3__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_799 (.A1(registers_16__ap[5]), .A2(n_1_0_1267), .B1( + n_1_0_1257), .B2(registers_3__ap[5]), .ZN(n_1_0_761)); + SDFF_X1_LVT \registers_reg[5][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_5__ap[5]), .CK(n_0_35), .Q(registers_5__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[31][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_31__ap[5]), .CK(n_0_61), .Q(registers_31__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_798 (.A1(registers_5__ap[5]), .A2(n_1_0_1273), .B1( + n_1_0_1266), .B2(registers_31__ap[5]), .ZN(n_1_0_760)); + SDFF_X1_LVT \registers_reg[15][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_15__ap[5]), .CK(n_0_45), .Q(registers_15__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[23][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_23__ap[5]), .CK(n_0_53), .Q(registers_23__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_797 (.A1(registers_15__ap[5]), .A2(n_1_0_1286), .B1( + n_1_0_1264), .B2(registers_23__ap[5]), .ZN(n_1_0_759)); + NAND4_X1_LVT i_1_0_796 (.A1(n_1_0_762), .A2(n_1_0_761), .A3(n_1_0_760), + .A4(n_1_0_759), .ZN(n_1_0_758)); + SDFF_X1_LVT \registers_reg[18][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_18__ap[5]), .CK(n_0_48), .Q(registers_18__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[30][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_30__ap[5]), .CK(n_0_60), .Q(registers_30__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_795 (.A1(registers_18__ap[5]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[5]), .ZN(n_1_0_757)); + SDFF_X1_LVT \registers_reg[24][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_24__ap[5]), .CK(n_0_54), .Q(registers_24__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[12][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_12__ap[5]), .CK(n_0_42), .Q(registers_12__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_794 (.A1(registers_24__ap[5]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[5]), .ZN(n_1_0_756)); + SDFF_X1_LVT \registers_reg[22][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_22__ap[5]), .CK(n_0_52), .Q(registers_22__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[21][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_21__ap[5]), .CK(n_0_51), .Q(registers_21__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_793 (.A1(registers_22__ap[5]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[5]), .ZN(n_1_0_755)); + SDFF_X1_LVT \registers_reg[20][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_20__ap[5]), .CK(n_0_50), .Q(registers_20__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[17][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_17__ap[5]), .CK(n_0_47), .Q(registers_17__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_792 (.A1(registers_20__ap[5]), .A2(n_1_0_1281), .B1( + n_1_0_1271), .B2(registers_17__ap[5]), .ZN(n_1_0_754)); + NAND4_X1_LVT i_1_0_791 (.A1(n_1_0_757), .A2(n_1_0_756), .A3(n_1_0_755), + .A4(n_1_0_754), .ZN(n_1_0_753)); + SDFF_X1_LVT \registers_reg[13][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_13__ap[5]), .CK(n_0_43), .Q(registers_13__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[25][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_25__ap[5]), .CK(n_0_55), .Q(registers_25__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_790 (.A1(registers_13__ap[5]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[5]), .ZN(n_1_0_752)); + SDFF_X1_LVT \registers_reg[19][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_19__ap[5]), .CK(n_0_49), .Q(registers_19__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[2][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_2__ap[5]), .CK(n_0_32), .Q(registers_2__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_789 (.A1(registers_19__ap[5]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[5]), .ZN(n_1_0_751)); + SDFF_X1_LVT \registers_reg[7][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_7__ap[5]), .CK(n_0_37), .Q(registers_7__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[14][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_14__ap[5]), .CK(n_0_44), .Q(registers_14__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_788 (.A1(registers_7__ap[5]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[5]), .ZN(n_1_0_750)); + SDFF_X1_LVT \registers_reg[27][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_27__ap[5]), .CK(n_0_57), .Q(registers_27__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[11][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_11__ap[5]), .CK(n_0_41), .Q(registers_11__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_787 (.A1(registers_27__ap[5]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[5]), .ZN(n_1_0_749)); + NAND4_X1_LVT i_1_0_786 (.A1(n_1_0_752), .A2(n_1_0_751), .A3(n_1_0_750), + .A4(n_1_0_749), .ZN(n_1_0_748)); + NOR3_X1_LVT i_1_0_785 (.A1(n_1_0_758), .A2(n_1_0_753), .A3(n_1_0_748), + .ZN(n_1_0_747)); + NAND4_X1_LVT i_1_0_784 (.A1(n_1_0_765), .A2(n_1_0_764), .A3(n_1_0_763), + .A4(n_1_0_747), .ZN(RRs1[5])); + AND2_X1_LVT i_0_0_4 (.A1(n_0_0_16), .A2(WRd[4]), .ZN(registers[4])); + SDFF_X1_LVT \registers_reg[10][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_10__ap[4]), .CK(n_0_40), .Q(registers_10__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[21][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_21__ap[4]), .CK(n_0_51), .Q(registers_21__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_783 (.A1(registers_10__ap[4]), .A2(n_1_0_1287), .B1( + n_1_0_1259), .B2(registers_21__ap[4]), .ZN(n_1_0_746)); + SDFF_X1_LVT \registers_reg[9][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_9__ap[4]), .CK(n_0_39), .Q(registers_9__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[1][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_1__ap[4]), .CK(n_0_0), .Q(registers_1__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_778 (.A1(registers_9__ap[4]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[4]), .ZN(n_1_0_741)); + SDFF_X1_LVT \registers_reg[18][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_18__ap[4]), .CK(n_0_48), .Q(registers_18__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[8][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_8__ap[4]), .CK(n_0_38), .Q(registers_8__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_777 (.A1(registers_18__ap[4]), .A2(n_1_0_1297), .B1( + n_1_0_1282), .B2(registers_8__ap[4]), .ZN(n_1_0_740)); + NAND3_X1_LVT i_1_0_775 (.A1(n_1_0_746), .A2(n_1_0_741), .A3(n_1_0_740), + .ZN(n_1_0_738)); + SDFF_X1_LVT \registers_reg[22][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_22__ap[4]), .CK(n_0_52), .Q(registers_22__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[23][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_23__ap[4]), .CK(n_0_53), .Q(registers_23__ap[4]), .QN()); + AOI221_X1_LVT i_1_0_774 (.A(n_1_0_738), .B1(n_1_0_1294), .B2( + registers_22__ap[4]), .C1(registers_23__ap[4]), .C2(n_1_0_1264), .ZN( + n_1_0_737)); + SDFF_X1_LVT \registers_reg[28][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_28__ap[4]), .CK(n_0_58), .Q(registers_28__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[20][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_20__ap[4]), .CK(n_0_50), .Q(registers_20__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_782 (.A1(registers_28__ap[4]), .A2(n_1_0_1283), .B1( + n_1_0_1281), .B2(registers_20__ap[4]), .ZN(n_1_0_745)); + SDFF_X1_LVT \registers_reg[19][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_19__ap[4]), .CK(n_0_49), .Q(registers_19__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[13][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_13__ap[4]), .CK(n_0_43), .Q(registers_13__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_780 (.A1(registers_19__ap[4]), .A2(n_1_0_1295), .B1( + n_1_0_1277), .B2(registers_13__ap[4]), .ZN(n_1_0_743)); + SDFF_X1_LVT \registers_reg[26][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_26__ap[4]), .CK(n_0_56), .Q(registers_26__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[3][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_3__ap[4]), .CK(n_0_33), .Q(registers_3__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_776 (.A1(registers_26__ap[4]), .A2(n_1_0_1285), .B1( + n_1_0_1257), .B2(registers_3__ap[4]), .ZN(n_1_0_739)); + NAND3_X1_LVT i_1_0_773 (.A1(n_1_0_745), .A2(n_1_0_743), .A3(n_1_0_739), + .ZN(n_1_0_736)); + SDFF_X1_LVT \registers_reg[30][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_30__ap[4]), .CK(n_0_60), .Q(registers_30__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[31][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_31__ap[4]), .CK(n_0_61), .Q(registers_31__ap[4]), .QN()); + AOI221_X1_LVT i_1_0_772 (.A(n_1_0_736), .B1(n_1_0_1272), .B2( + registers_30__ap[4]), .C1(registers_31__ap[4]), .C2(n_1_0_1266), .ZN( + n_1_0_735)); + SDFF_X1_LVT \registers_reg[24][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_24__ap[4]), .CK(n_0_54), .Q(registers_24__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[12][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_12__ap[4]), .CK(n_0_42), .Q(registers_12__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_781 (.A1(registers_24__ap[4]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[4]), .ZN(n_1_0_744)); + SDFF_X1_LVT \registers_reg[27][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_27__ap[4]), .CK(n_0_57), .Q(registers_27__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[11][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_11__ap[4]), .CK(n_0_41), .Q(registers_11__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_779 (.A1(registers_27__ap[4]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[4]), .ZN(n_1_0_742)); + SDFF_X1_LVT \registers_reg[17][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_17__ap[4]), .CK(n_0_47), .Q(registers_17__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[7][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_7__ap[4]), .CK(n_0_37), .Q(registers_7__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[14][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_14__ap[4]), .CK(n_0_44), .Q(registers_14__ap[4]), .QN()); + AOI222_X1_LVT i_1_0_771 (.A1(registers_17__ap[4]), .A2(n_1_0_1271), .B1( + n_1_0_1263), .B2(registers_7__ap[4]), .C1(n_1_0_1258), .C2( + registers_14__ap[4]), .ZN(n_1_0_734)); + SDFF_X1_LVT \registers_reg[15][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_15__ap[4]), .CK(n_0_45), .Q(registers_15__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[16][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_16__ap[4]), .CK(n_0_46), .Q(registers_16__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_770 (.A1(registers_15__ap[4]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[4]), .ZN(n_1_0_733)); + SDFF_X1_LVT \registers_reg[4][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_4__ap[4]), .CK(n_0_34), .Q(registers_4__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[25][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_25__ap[4]), .CK(n_0_55), .Q(registers_25__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_769 (.A1(registers_4__ap[4]), .A2(n_1_0_1278), .B1( + n_1_0_1269), .B2(registers_25__ap[4]), .ZN(n_1_0_732)); + SDFF_X1_LVT \registers_reg[29][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_29__ap[4]), .CK(n_0_59), .Q(registers_29__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[2][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_2__ap[4]), .CK(n_0_32), .Q(registers_2__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_768 (.A1(registers_29__ap[4]), .A2(n_1_0_1276), .B1( + n_1_0_1268), .B2(registers_2__ap[4]), .ZN(n_1_0_731)); + NAND3_X1_LVT i_1_0_767 (.A1(n_1_0_733), .A2(n_1_0_732), .A3(n_1_0_731), + .ZN(n_1_0_730)); + SDFF_X1_LVT \registers_reg[6][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_6__ap[4]), .CK(n_0_36), .Q(registers_6__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[5][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_5__ap[4]), .CK(n_0_35), .Q(registers_5__ap[4]), .QN()); + AOI221_X1_LVT i_1_0_766 (.A(n_1_0_730), .B1(n_1_0_1300), .B2( + registers_6__ap[4]), .C1(registers_5__ap[4]), .C2(n_1_0_1273), .ZN( + n_1_0_729)); + AND4_X1_LVT i_1_0_765 (.A1(n_1_0_744), .A2(n_1_0_742), .A3(n_1_0_734), + .A4(n_1_0_729), .ZN(n_1_0_728)); + NAND3_X1_LVT i_1_0_764 (.A1(n_1_0_737), .A2(n_1_0_735), .A3(n_1_0_728), + .ZN(RRs1[4])); + AND2_X1_LVT i_0_0_3 (.A1(n_0_0_16), .A2(WRd[3]), .ZN(registers[3])); + SDFF_X1_LVT \registers_reg[28][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_28__ap[3]), .CK(n_0_58), .Q(registers_28__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[17][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_17__ap[3]), .CK(n_0_47), .Q(registers_17__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_763 (.A1(registers_28__ap[3]), .A2(n_1_0_1283), .B1( + n_1_0_1271), .B2(registers_17__ap[3]), .ZN(n_1_0_727)); + SDFF_X1_LVT \registers_reg[10][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_10__ap[3]), .CK(n_0_40), .Q(registers_10__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[26][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_26__ap[3]), .CK(n_0_56), .Q(registers_26__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[8][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_8__ap[3]), .CK(n_0_38), .Q(registers_8__ap[3]), .QN()); + AOI222_X1_LVT i_1_0_762 (.A1(registers_10__ap[3]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[3]), .C1(registers_8__ap[3]), .C2( + n_1_0_1282), .ZN(n_1_0_726)); + SDFF_X1_LVT \registers_reg[9][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_9__ap[3]), .CK(n_0_39), .Q(registers_9__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[29][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_29__ap[3]), .CK(n_0_59), .Q(registers_29__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_761 (.A1(registers_9__ap[3]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[3]), .ZN(n_1_0_725)); + SDFF_X1_LVT \registers_reg[6][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_6__ap[3]), .CK(n_0_36), .Q(registers_6__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[1][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_1__ap[3]), .CK(n_0_0), .Q(registers_1__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_760 (.A1(registers_6__ap[3]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[3]), .ZN(n_1_0_724)); + SDFF_X1_LVT \registers_reg[16][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_16__ap[3]), .CK(n_0_46), .Q(registers_16__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[3][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_3__ap[3]), .CK(n_0_33), .Q(registers_3__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_759 (.A1(registers_16__ap[3]), .A2(n_1_0_1267), .B1( + n_1_0_1257), .B2(registers_3__ap[3]), .ZN(n_1_0_723)); + SDFF_X1_LVT \registers_reg[5][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_5__ap[3]), .CK(n_0_35), .Q(registers_5__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[31][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_31__ap[3]), .CK(n_0_61), .Q(registers_31__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_758 (.A1(registers_5__ap[3]), .A2(n_1_0_1273), .B1( + n_1_0_1266), .B2(registers_31__ap[3]), .ZN(n_1_0_722)); + SDFF_X1_LVT \registers_reg[15][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_15__ap[3]), .CK(n_0_45), .Q(registers_15__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[23][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_23__ap[3]), .CK(n_0_53), .Q(registers_23__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_757 (.A1(registers_15__ap[3]), .A2(n_1_0_1286), .B1( + n_1_0_1264), .B2(registers_23__ap[3]), .ZN(n_1_0_721)); + NAND4_X1_LVT i_1_0_756 (.A1(n_1_0_724), .A2(n_1_0_723), .A3(n_1_0_722), + .A4(n_1_0_721), .ZN(n_1_0_720)); + SDFF_X1_LVT \registers_reg[18][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_18__ap[3]), .CK(n_0_48), .Q(registers_18__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[30][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_30__ap[3]), .CK(n_0_60), .Q(registers_30__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_755 (.A1(registers_18__ap[3]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[3]), .ZN(n_1_0_719)); + SDFF_X1_LVT \registers_reg[20][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_20__ap[3]), .CK(n_0_50), .Q(registers_20__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[4][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_4__ap[3]), .CK(n_0_34), .Q(registers_4__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_754 (.A1(registers_20__ap[3]), .A2(n_1_0_1281), .B1( + n_1_0_1278), .B2(registers_4__ap[3]), .ZN(n_1_0_718)); + SDFF_X1_LVT \registers_reg[22][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_22__ap[3]), .CK(n_0_52), .Q(registers_22__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[21][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_21__ap[3]), .CK(n_0_51), .Q(registers_21__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_753 (.A1(registers_22__ap[3]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[3]), .ZN(n_1_0_717)); + SDFF_X1_LVT \registers_reg[24][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_24__ap[3]), .CK(n_0_54), .Q(registers_24__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[12][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_12__ap[3]), .CK(n_0_42), .Q(registers_12__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_752 (.A1(registers_24__ap[3]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[3]), .ZN(n_1_0_716)); + NAND4_X1_LVT i_1_0_751 (.A1(n_1_0_719), .A2(n_1_0_718), .A3(n_1_0_717), + .A4(n_1_0_716), .ZN(n_1_0_715)); + SDFF_X1_LVT \registers_reg[13][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_13__ap[3]), .CK(n_0_43), .Q(registers_13__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[25][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_25__ap[3]), .CK(n_0_55), .Q(registers_25__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_750 (.A1(registers_13__ap[3]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[3]), .ZN(n_1_0_714)); + SDFF_X1_LVT \registers_reg[19][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_19__ap[3]), .CK(n_0_49), .Q(registers_19__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[2][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_2__ap[3]), .CK(n_0_32), .Q(registers_2__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_749 (.A1(registers_19__ap[3]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[3]), .ZN(n_1_0_713)); + SDFF_X1_LVT \registers_reg[7][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_7__ap[3]), .CK(n_0_37), .Q(registers_7__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[14][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_14__ap[3]), .CK(n_0_44), .Q(registers_14__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_748 (.A1(registers_7__ap[3]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[3]), .ZN(n_1_0_712)); + SDFF_X1_LVT \registers_reg[27][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_27__ap[3]), .CK(n_0_57), .Q(registers_27__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[11][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_11__ap[3]), .CK(n_0_41), .Q(registers_11__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_747 (.A1(registers_27__ap[3]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[3]), .ZN(n_1_0_711)); + NAND4_X1_LVT i_1_0_746 (.A1(n_1_0_714), .A2(n_1_0_713), .A3(n_1_0_712), + .A4(n_1_0_711), .ZN(n_1_0_710)); + NOR3_X1_LVT i_1_0_745 (.A1(n_1_0_720), .A2(n_1_0_715), .A3(n_1_0_710), + .ZN(n_1_0_709)); + NAND4_X1_LVT i_1_0_744 (.A1(n_1_0_727), .A2(n_1_0_726), .A3(n_1_0_725), + .A4(n_1_0_709), .ZN(RRs1[3])); + AND2_X1_LVT i_0_0_2 (.A1(n_0_0_16), .A2(WRd[2]), .ZN(registers[2])); + SDFF_X1_LVT \registers_reg[28][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_28__ap[2]), .CK(n_0_58), .Q(registers_28__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[4][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_4__ap[2]), .CK(n_0_34), .Q(registers_4__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_740 (.A1(registers_28__ap[2]), .A2(n_1_0_1283), .B1( + n_1_0_1278), .B2(registers_4__ap[2]), .ZN(n_1_0_705)); + SDFF_X1_LVT \registers_reg[16][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_16__ap[2]), .CK(n_0_46), .Q(registers_16__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[31][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_31__ap[2]), .CK(n_0_61), .Q(registers_31__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_743 (.A1(registers_16__ap[2]), .A2(n_1_0_1267), .B1( + n_1_0_1266), .B2(registers_31__ap[2]), .ZN(n_1_0_708)); + SDFF_X1_LVT \registers_reg[6][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_6__ap[2]), .CK(n_0_36), .Q(registers_6__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[1][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_1__ap[2]), .CK(n_0_0), .Q(registers_1__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_739 (.A1(registers_6__ap[2]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[2]), .ZN(n_1_0_704)); + SDFF_X1_LVT \registers_reg[15][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_15__ap[2]), .CK(n_0_45), .Q(registers_15__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[27][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_27__ap[2]), .CK(n_0_57), .Q(registers_27__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_742 (.A1(registers_15__ap[2]), .A2(n_1_0_1286), .B1( + n_1_0_1279), .B2(registers_27__ap[2]), .ZN(n_1_0_707)); + INV_X1_LVT i_1_0_741 (.A(n_1_0_707), .ZN(n_1_0_706)); + SDFF_X1_LVT \registers_reg[11][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_11__ap[2]), .CK(n_0_41), .Q(registers_11__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[5][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_5__ap[2]), .CK(n_0_35), .Q(registers_5__ap[2]), .QN()); + AOI221_X1_LVT i_1_0_738 (.A(n_1_0_706), .B1(n_1_0_1270), .B2( + registers_11__ap[2]), .C1(registers_5__ap[2]), .C2(n_1_0_1273), .ZN( + n_1_0_703)); + SDFF_X1_LVT \registers_reg[10][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_10__ap[2]), .CK(n_0_40), .Q(registers_10__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[30][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_30__ap[2]), .CK(n_0_60), .Q(registers_30__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[8][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_8__ap[2]), .CK(n_0_38), .Q(registers_8__ap[2]), .QN()); + AOI222_X1_LVT i_1_0_737 (.A1(registers_10__ap[2]), .A2(n_1_0_1287), .B1( + n_1_0_1272), .B2(registers_30__ap[2]), .C1(n_1_0_1282), .C2( + registers_8__ap[2]), .ZN(n_1_0_702)); + NAND4_X1_LVT i_1_0_736 (.A1(n_1_0_708), .A2(n_1_0_704), .A3(n_1_0_703), + .A4(n_1_0_702), .ZN(n_1_0_701)); + SDFF_X1_LVT \registers_reg[9][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_9__ap[2]), .CK(n_0_39), .Q(registers_9__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[29][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_29__ap[2]), .CK(n_0_59), .Q(registers_29__ap[2]), .QN()); + AOI221_X1_LVT i_1_0_735 (.A(n_1_0_701), .B1(n_1_0_1291), .B2( + registers_9__ap[2]), .C1(registers_29__ap[2]), .C2(n_1_0_1276), .ZN( + n_1_0_700)); + SDFF_X1_LVT \registers_reg[18][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_18__ap[2]), .CK(n_0_48), .Q(registers_18__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[26][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_26__ap[2]), .CK(n_0_56), .Q(registers_26__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_734 (.A1(registers_18__ap[2]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[2]), .ZN(n_1_0_699)); + SDFF_X1_LVT \registers_reg[24][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_24__ap[2]), .CK(n_0_54), .Q(registers_24__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[12][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_12__ap[2]), .CK(n_0_42), .Q(registers_12__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_733 (.A1(registers_24__ap[2]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[2]), .ZN(n_1_0_698)); + SDFF_X1_LVT \registers_reg[22][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_22__ap[2]), .CK(n_0_52), .Q(registers_22__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[21][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_21__ap[2]), .CK(n_0_51), .Q(registers_21__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_732 (.A1(registers_22__ap[2]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[2]), .ZN(n_1_0_697)); + NAND3_X1_LVT i_1_0_731 (.A1(n_1_0_699), .A2(n_1_0_698), .A3(n_1_0_697), + .ZN(n_1_0_696)); + SDFF_X1_LVT \registers_reg[17][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_17__ap[2]), .CK(n_0_47), .Q(registers_17__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[20][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_20__ap[2]), .CK(n_0_50), .Q(registers_20__ap[2]), .QN()); + AOI221_X1_LVT i_1_0_730 (.A(n_1_0_696), .B1(n_1_0_1271), .B2( + registers_17__ap[2]), .C1(registers_20__ap[2]), .C2(n_1_0_1281), .ZN( + n_1_0_695)); + SDFF_X1_LVT \registers_reg[13][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_13__ap[2]), .CK(n_0_43), .Q(registers_13__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[25][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_25__ap[2]), .CK(n_0_55), .Q(registers_25__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_729 (.A1(registers_13__ap[2]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[2]), .ZN(n_1_0_694)); + SDFF_X1_LVT \registers_reg[7][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_7__ap[2]), .CK(n_0_37), .Q(registers_7__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[14][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_14__ap[2]), .CK(n_0_44), .Q(registers_14__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_728 (.A1(registers_7__ap[2]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[2]), .ZN(n_1_0_693)); + SDFF_X1_LVT \registers_reg[19][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_19__ap[2]), .CK(n_0_49), .Q(registers_19__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[3][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_3__ap[2]), .CK(n_0_33), .Q(registers_3__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_727 (.A1(registers_19__ap[2]), .A2(n_1_0_1295), .B1( + n_1_0_1257), .B2(registers_3__ap[2]), .ZN(n_1_0_692)); + NAND3_X1_LVT i_1_0_726 (.A1(n_1_0_694), .A2(n_1_0_693), .A3(n_1_0_692), + .ZN(n_1_0_691)); + SDFF_X1_LVT \registers_reg[23][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_23__ap[2]), .CK(n_0_53), .Q(registers_23__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[2][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_2__ap[2]), .CK(n_0_32), .Q(registers_2__ap[2]), .QN()); + AOI221_X1_LVT i_1_0_725 (.A(n_1_0_691), .B1(n_1_0_1264), .B2( + registers_23__ap[2]), .C1(registers_2__ap[2]), .C2(n_1_0_1268), .ZN( + n_1_0_690)); + NAND4_X1_LVT i_1_0_724 (.A1(n_1_0_705), .A2(n_1_0_700), .A3(n_1_0_695), + .A4(n_1_0_690), .ZN(RRs1[2])); + AND2_X1_LVT i_0_0_1 (.A1(n_0_0_16), .A2(WRd[1]), .ZN(registers[1])); + SDFF_X1_LVT \registers_reg[13][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_13__ap[1]), .CK(n_0_43), .Q(registers_13__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[21][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_21__ap[1]), .CK(n_0_51), .Q(registers_21__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_720 (.A1(registers_13__ap[1]), .A2(n_1_0_1277), .B1( + n_1_0_1259), .B2(registers_21__ap[1]), .ZN(n_1_0_686)); + SDFF_X1_LVT \registers_reg[29][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_29__ap[1]), .CK(n_0_59), .Q(registers_29__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[23][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_23__ap[1]), .CK(n_0_53), .Q(registers_23__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_723 (.A1(registers_29__ap[1]), .A2(n_1_0_1276), .B1( + n_1_0_1264), .B2(registers_23__ap[1]), .ZN(n_1_0_689)); + SDFF_X1_LVT \registers_reg[24][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_24__ap[1]), .CK(n_0_54), .Q(registers_24__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[20][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_20__ap[1]), .CK(n_0_50), .Q(registers_20__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_719 (.A1(registers_24__ap[1]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[1]), .ZN(n_1_0_685)); + SDFF_X1_LVT \registers_reg[7][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_7__ap[1]), .CK(n_0_37), .Q(registers_7__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[3][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_3__ap[1]), .CK(n_0_33), .Q(registers_3__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_722 (.A1(registers_7__ap[1]), .A2(n_1_0_1263), .B1( + n_1_0_1257), .B2(registers_3__ap[1]), .ZN(n_1_0_688)); + INV_X1_LVT i_1_0_721 (.A(n_1_0_688), .ZN(n_1_0_687)); + SDFF_X1_LVT \registers_reg[31][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_31__ap[1]), .CK(n_0_61), .Q(registers_31__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[4][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_4__ap[1]), .CK(n_0_34), .Q(registers_4__ap[1]), .QN()); + AOI221_X1_LVT i_1_0_718 (.A(n_1_0_687), .B1(n_1_0_1266), .B2( + registers_31__ap[1]), .C1(registers_4__ap[1]), .C2(n_1_0_1278), .ZN( + n_1_0_684)); + SDFF_X1_LVT \registers_reg[10][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_10__ap[1]), .CK(n_0_40), .Q(registers_10__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[26][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_26__ap[1]), .CK(n_0_56), .Q(registers_26__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[25][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_25__ap[1]), .CK(n_0_55), .Q(registers_25__ap[1]), .QN()); + AOI222_X1_LVT i_1_0_717 (.A1(registers_10__ap[1]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[1]), .C1(registers_25__ap[1]), .C2( + n_1_0_1269), .ZN(n_1_0_683)); + NAND4_X1_LVT i_1_0_716 (.A1(n_1_0_689), .A2(n_1_0_685), .A3(n_1_0_684), + .A4(n_1_0_683), .ZN(n_1_0_682)); + SDFF_X1_LVT \registers_reg[8][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_8__ap[1]), .CK(n_0_38), .Q(registers_8__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[28][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_28__ap[1]), .CK(n_0_58), .Q(registers_28__ap[1]), .QN()); + AOI221_X1_LVT i_1_0_715 (.A(n_1_0_682), .B1(n_1_0_1282), .B2( + registers_8__ap[1]), .C1(registers_28__ap[1]), .C2(n_1_0_1283), .ZN( + n_1_0_681)); + SDFF_X1_LVT \registers_reg[18][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_18__ap[1]), .CK(n_0_48), .Q(registers_18__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[30][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_30__ap[1]), .CK(n_0_60), .Q(registers_30__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_714 (.A1(registers_18__ap[1]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[1]), .ZN(n_1_0_680)); + SDFF_X1_LVT \registers_reg[17][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_17__ap[1]), .CK(n_0_47), .Q(registers_17__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[12][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_12__ap[1]), .CK(n_0_42), .Q(registers_12__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_713 (.A1(registers_17__ap[1]), .A2(n_1_0_1271), .B1( + n_1_0_1260), .B2(registers_12__ap[1]), .ZN(n_1_0_679)); + SDFF_X1_LVT \registers_reg[15][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_15__ap[1]), .CK(n_0_45), .Q(registers_15__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[5][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_5__ap[1]), .CK(n_0_35), .Q(registers_5__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_712 (.A1(registers_15__ap[1]), .A2(n_1_0_1286), .B1( + n_1_0_1273), .B2(registers_5__ap[1]), .ZN(n_1_0_678)); + NAND3_X1_LVT i_1_0_711 (.A1(n_1_0_680), .A2(n_1_0_679), .A3(n_1_0_678), + .ZN(n_1_0_677)); + SDFF_X1_LVT \registers_reg[22][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_22__ap[1]), .CK(n_0_52), .Q(registers_22__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[16][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_16__ap[1]), .CK(n_0_46), .Q(registers_16__ap[1]), .QN()); + AOI221_X1_LVT i_1_0_710 (.A(n_1_0_677), .B1(n_1_0_1294), .B2( + registers_22__ap[1]), .C1(registers_16__ap[1]), .C2(n_1_0_1267), .ZN( + n_1_0_676)); + SDFF_X1_LVT \registers_reg[9][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_9__ap[1]), .CK(n_0_39), .Q(registers_9__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[1][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_1__ap[1]), .CK(n_0_0), .Q(registers_1__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_709 (.A1(registers_9__ap[1]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[1]), .ZN(n_1_0_675)); + SDFF_X1_LVT \registers_reg[6][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_6__ap[1]), .CK(n_0_36), .Q(registers_6__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[14][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_14__ap[1]), .CK(n_0_44), .Q(registers_14__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_708 (.A1(registers_6__ap[1]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[1]), .ZN(n_1_0_674)); + SDFF_X1_LVT \registers_reg[19][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_19__ap[1]), .CK(n_0_49), .Q(registers_19__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[2][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_2__ap[1]), .CK(n_0_32), .Q(registers_2__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_707 (.A1(registers_19__ap[1]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[1]), .ZN(n_1_0_673)); + NAND3_X1_LVT i_1_0_706 (.A1(n_1_0_675), .A2(n_1_0_674), .A3(n_1_0_673), + .ZN(n_1_0_672)); + SDFF_X1_LVT \registers_reg[11][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_11__ap[1]), .CK(n_0_41), .Q(registers_11__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[27][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_27__ap[1]), .CK(n_0_57), .Q(registers_27__ap[1]), .QN()); + AOI221_X1_LVT i_1_0_705 (.A(n_1_0_672), .B1(n_1_0_1270), .B2( + registers_11__ap[1]), .C1(registers_27__ap[1]), .C2(n_1_0_1279), .ZN( + n_1_0_671)); + NAND4_X1_LVT i_1_0_704 (.A1(n_1_0_686), .A2(n_1_0_681), .A3(n_1_0_676), + .A4(n_1_0_671), .ZN(RRs1[1])); + AND2_X1_LVT i_0_0_0 (.A1(n_0_0_16), .A2(WRd[0]), .ZN(registers[0])); + SDFF_X1_LVT \registers_reg[13][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_13__ap[0]), .CK(n_0_43), .Q(registers_13__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[21][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_21__ap[0]), .CK(n_0_51), .Q(registers_21__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_703 (.A1(registers_13__ap[0]), .A2(n_1_0_1277), .B1( + n_1_0_1259), .B2(registers_21__ap[0]), .ZN(n_1_0_670)); + SDFF_X1_LVT \registers_reg[10][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_10__ap[0]), .CK(n_0_40), .Q(registers_10__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[26][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_26__ap[0]), .CK(n_0_56), .Q(registers_26__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[25][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_25__ap[0]), .CK(n_0_55), .Q(registers_25__ap[0]), .QN()); + AOI222_X1_LVT i_1_0_702 (.A1(registers_10__ap[0]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[0]), .C1(registers_25__ap[0]), .C2( + n_1_0_1269), .ZN(n_1_0_669)); + SDFF_X1_LVT \registers_reg[28][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_28__ap[0]), .CK(n_0_58), .Q(registers_28__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[8][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_8__ap[0]), .CK(n_0_38), .Q(registers_8__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_701 (.A1(registers_28__ap[0]), .A2(n_1_0_1283), .B1( + n_1_0_1282), .B2(registers_8__ap[0]), .ZN(n_1_0_668)); + SDFF_X1_LVT \registers_reg[24][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_24__ap[0]), .CK(n_0_54), .Q(registers_24__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[20][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_20__ap[0]), .CK(n_0_50), .Q(registers_20__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_700 (.A1(registers_24__ap[0]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[0]), .ZN(n_1_0_667)); + SDFF_X1_LVT \registers_reg[7][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_7__ap[0]), .CK(n_0_37), .Q(registers_7__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[3][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_3__ap[0]), .CK(n_0_33), .Q(registers_3__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_699 (.A1(registers_7__ap[0]), .A2(n_1_0_1263), .B1( + n_1_0_1257), .B2(registers_3__ap[0]), .ZN(n_1_0_666)); + SDFF_X1_LVT \registers_reg[17][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_17__ap[0]), .CK(n_0_47), .Q(registers_17__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[31][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_31__ap[0]), .CK(n_0_61), .Q(registers_31__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_698 (.A1(registers_17__ap[0]), .A2(n_1_0_1271), .B1( + n_1_0_1266), .B2(registers_31__ap[0]), .ZN(n_1_0_665)); + SDFF_X1_LVT \registers_reg[29][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_29__ap[0]), .CK(n_0_59), .Q(registers_29__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[23][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_23__ap[0]), .CK(n_0_53), .Q(registers_23__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_697 (.A1(registers_29__ap[0]), .A2(n_1_0_1276), .B1( + n_1_0_1264), .B2(registers_23__ap[0]), .ZN(n_1_0_664)); + NAND4_X1_LVT i_1_0_696 (.A1(n_1_0_667), .A2(n_1_0_666), .A3(n_1_0_665), + .A4(n_1_0_664), .ZN(n_1_0_663)); + SDFF_X1_LVT \registers_reg[18][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_18__ap[0]), .CK(n_0_48), .Q(registers_18__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[30][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_30__ap[0]), .CK(n_0_60), .Q(registers_30__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_695 (.A1(registers_18__ap[0]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[0]), .ZN(n_1_0_662)); + SDFF_X1_LVT \registers_reg[4][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_4__ap[0]), .CK(n_0_34), .Q(registers_4__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[12][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_12__ap[0]), .CK(n_0_42), .Q(registers_12__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_694 (.A1(registers_4__ap[0]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[0]), .ZN(n_1_0_661)); + SDFF_X1_LVT \registers_reg[15][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_15__ap[0]), .CK(n_0_45), .Q(registers_15__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[16][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_16__ap[0]), .CK(n_0_46), .Q(registers_16__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_693 (.A1(registers_15__ap[0]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[0]), .ZN(n_1_0_660)); + SDFF_X1_LVT \registers_reg[22][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_22__ap[0]), .CK(n_0_52), .Q(registers_22__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[5][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_5__ap[0]), .CK(n_0_35), .Q(registers_5__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_692 (.A1(registers_22__ap[0]), .A2(n_1_0_1294), .B1( + n_1_0_1273), .B2(registers_5__ap[0]), .ZN(n_1_0_659)); + NAND4_X1_LVT i_1_0_691 (.A1(n_1_0_662), .A2(n_1_0_661), .A3(n_1_0_660), + .A4(n_1_0_659), .ZN(n_1_0_658)); + SDFF_X1_LVT \registers_reg[19][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_19__ap[0]), .CK(n_0_49), .Q(registers_19__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[2][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_2__ap[0]), .CK(n_0_32), .Q(registers_2__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_690 (.A1(registers_19__ap[0]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[0]), .ZN(n_1_0_657)); + SDFF_X1_LVT \registers_reg[9][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_9__ap[0]), .CK(n_0_39), .Q(registers_9__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[1][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_1__ap[0]), .CK(n_0_0), .Q(registers_1__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_689 (.A1(registers_9__ap[0]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[0]), .ZN(n_1_0_656)); + SDFF_X1_LVT \registers_reg[6][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_6__ap[0]), .CK(n_0_36), .Q(registers_6__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[14][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_14__ap[0]), .CK(n_0_44), .Q(registers_14__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_688 (.A1(registers_6__ap[0]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[0]), .ZN(n_1_0_655)); + SDFF_X1_LVT \registers_reg[27][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_27__ap[0]), .CK(n_0_57), .Q(registers_27__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[11][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_11__ap[0]), .CK(n_0_41), .Q(registers_11__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_687 (.A1(registers_27__ap[0]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[0]), .ZN(n_1_0_654)); + NAND4_X1_LVT i_1_0_686 (.A1(n_1_0_657), .A2(n_1_0_656), .A3(n_1_0_655), + .A4(n_1_0_654), .ZN(n_1_0_653)); + NOR3_X1_LVT i_1_0_685 (.A1(n_1_0_663), .A2(n_1_0_658), .A3(n_1_0_653), + .ZN(n_1_0_652)); + NAND4_X1_LVT i_1_0_684 (.A1(n_1_0_670), .A2(n_1_0_669), .A3(n_1_0_668), + .A4(n_1_0_652), .ZN(RRs1[0])); + INV_X1_LVT i_1_0_1366 (.A(Rs2[1]), .ZN(n_1_0_1302)); + NAND3_X1_LVT i_1_0_683 (.A1(n_1_0_1302), .A2(Rs2[4]), .A3(Rs2[2]), .ZN( + n_1_0_651)); + INV_X1_LVT i_1_0_1369 (.A(Rs2[3]), .ZN(n_1_0_1305)); + OR2_X1_LVT i_1_0_673 (.A1(n_1_0_1305), .A2(Rs2[0]), .ZN(n_1_0_641)); + NOR2_X1_LVT i_1_0_666 (.A1(n_1_0_651), .A2(n_1_0_641), .ZN(n_1_0_634)); + NAND2_X1_LVT i_1_0_677 (.A1(n_1_0_1305), .A2(Rs2[0]), .ZN(n_1_0_645)); + INV_X1_LVT i_1_0_1368 (.A(Rs2[2]), .ZN(n_1_0_1304)); + NAND3_X1_LVT i_1_0_662 (.A1(n_1_0_1304), .A2(n_1_0_1302), .A3(Rs2[4]), + .ZN(n_1_0_630)); + NOR2_X1_LVT i_1_0_661 (.A1(n_1_0_645), .A2(n_1_0_630), .ZN(n_1_0_629)); + AOI22_X1_LVT i_1_0_641 (.A1(registers_28__ap[31]), .A2(n_1_0_634), .B1( + n_1_0_629), .B2(registers_17__ap[31]), .ZN(n_1_0_609)); + NAND3_X1_LVT i_1_0_680 (.A1(n_1_0_1304), .A2(Rs2[4]), .A3(Rs2[1]), .ZN( + n_1_0_648)); + NOR2_X1_LVT i_1_0_672 (.A1(n_1_0_648), .A2(n_1_0_641), .ZN(n_1_0_640)); + INV_X1_LVT i_1_0_1367 (.A(Rs2[4]), .ZN(n_1_0_1303)); + NAND3_X1_LVT i_1_0_657 (.A1(n_1_0_1304), .A2(n_1_0_1303), .A3(Rs2[1]), + .ZN(n_1_0_625)); + NOR2_X1_LVT i_1_0_656 (.A1(n_1_0_641), .A2(n_1_0_625), .ZN(n_1_0_624)); + NOR4_X1_LVT i_1_0_658 (.A1(n_1_0_641), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), + .ZN(n_1_0_626)); + AOI222_X1_LVT i_1_0_640 (.A1(registers_26__ap[31]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[31]), .C1(n_1_0_626), .C2( + registers_8__ap[31]), .ZN(n_1_0_608)); + NAND2_X1_LVT i_1_0_682 (.A1(Rs2[0]), .A2(Rs2[3]), .ZN(n_1_0_650)); + NOR2_X1_LVT i_1_0_681 (.A1(n_1_0_651), .A2(n_1_0_650), .ZN(n_1_0_649)); + NOR4_X1_LVT i_1_0_649 (.A1(n_1_0_650), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), + .ZN(n_1_0_617)); + AOI22_X1_LVT i_1_0_639 (.A1(registers_29__ap[31]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[31]), .ZN(n_1_0_607)); + NOR4_X1_LVT i_1_0_676 (.A1(n_1_0_645), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), + .ZN(n_1_0_644)); + OR2_X1_LVT i_1_0_679 (.A1(Rs2[0]), .A2(Rs2[3]), .ZN(n_1_0_647)); + NAND3_X1_LVT i_1_0_660 (.A1(n_1_0_1303), .A2(Rs2[1]), .A3(Rs2[2]), .ZN( + n_1_0_628)); + NOR2_X1_LVT i_1_0_648 (.A1(n_1_0_647), .A2(n_1_0_628), .ZN(n_1_0_616)); + AOI22_X1_LVT i_1_0_638 (.A1(registers_1__ap[31]), .A2(n_1_0_644), .B1( + n_1_0_616), .B2(registers_6__ap[31]), .ZN(n_1_0_606)); + NOR2_X1_LVT i_1_0_655 (.A1(n_1_0_645), .A2(n_1_0_628), .ZN(n_1_0_623)); + NAND3_X1_LVT i_1_0_675 (.A1(Rs2[2]), .A2(Rs2[4]), .A3(Rs2[1]), .ZN(n_1_0_643)); + NOR2_X1_LVT i_1_0_647 (.A1(n_1_0_645), .A2(n_1_0_643), .ZN(n_1_0_615)); + AOI22_X1_LVT i_1_0_637 (.A1(registers_7__ap[31]), .A2(n_1_0_623), .B1( + n_1_0_615), .B2(registers_23__ap[31]), .ZN(n_1_0_605)); + NOR2_X1_LVT i_1_0_665 (.A1(n_1_0_648), .A2(n_1_0_645), .ZN(n_1_0_633)); + NOR2_X1_LVT i_1_0_646 (.A1(n_1_0_647), .A2(n_1_0_630), .ZN(n_1_0_614)); + AOI22_X1_LVT i_1_0_636 (.A1(registers_19__ap[31]), .A2(n_1_0_633), .B1( + n_1_0_614), .B2(registers_16__ap[31]), .ZN(n_1_0_604)); + NOR2_X1_LVT i_1_0_669 (.A1(n_1_0_650), .A2(n_1_0_643), .ZN(n_1_0_637)); + NAND3_X1_LVT i_1_0_671 (.A1(n_1_0_1303), .A2(n_1_0_1302), .A3(Rs2[2]), + .ZN(n_1_0_639)); + NOR2_X1_LVT i_1_0_667 (.A1(n_1_0_645), .A2(n_1_0_639), .ZN(n_1_0_635)); + AOI22_X1_LVT i_1_0_635 (.A1(registers_31__ap[31]), .A2(n_1_0_637), .B1( + n_1_0_635), .B2(registers_5__ap[31]), .ZN(n_1_0_603)); + NAND4_X1_LVT i_1_0_634 (.A1(n_1_0_606), .A2(n_1_0_605), .A3(n_1_0_604), + .A4(n_1_0_603), .ZN(n_1_0_602)); + NOR2_X1_LVT i_1_0_678 (.A1(n_1_0_648), .A2(n_1_0_647), .ZN(n_1_0_646)); + NOR2_X1_LVT i_1_0_654 (.A1(n_1_0_643), .A2(n_1_0_641), .ZN(n_1_0_622)); + AOI22_X1_LVT i_1_0_633 (.A1(registers_18__ap[31]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[31]), .ZN(n_1_0_601)); + NOR2_X1_LVT i_1_0_670 (.A1(n_1_0_647), .A2(n_1_0_639), .ZN(n_1_0_638)); + NOR2_X1_LVT i_1_0_645 (.A1(n_1_0_651), .A2(n_1_0_647), .ZN(n_1_0_613)); + AOI22_X1_LVT i_1_0_632 (.A1(registers_4__ap[31]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[31]), .ZN(n_1_0_600)); + NOR2_X1_LVT i_1_0_674 (.A1(n_1_0_647), .A2(n_1_0_643), .ZN(n_1_0_642)); + NOR2_X1_LVT i_1_0_644 (.A1(n_1_0_651), .A2(n_1_0_645), .ZN(n_1_0_612)); + AOI22_X1_LVT i_1_0_631 (.A1(registers_22__ap[31]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[31]), .ZN(n_1_0_599)); + NOR2_X1_LVT i_1_0_664 (.A1(n_1_0_641), .A2(n_1_0_639), .ZN(n_1_0_632)); + NOR2_X1_LVT i_1_0_653 (.A1(n_1_0_641), .A2(n_1_0_630), .ZN(n_1_0_621)); + AOI22_X1_LVT i_1_0_630 (.A1(registers_12__ap[31]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[31]), .ZN(n_1_0_598)); + NAND4_X1_LVT i_1_0_629 (.A1(n_1_0_601), .A2(n_1_0_600), .A3(n_1_0_599), + .A4(n_1_0_598), .ZN(n_1_0_597)); + NOR2_X1_LVT i_1_0_663 (.A1(n_1_0_650), .A2(n_1_0_639), .ZN(n_1_0_631)); + NOR2_X1_LVT i_1_0_652 (.A1(n_1_0_650), .A2(n_1_0_630), .ZN(n_1_0_620)); + AOI22_X1_LVT i_1_0_628 (.A1(registers_13__ap[31]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[31]), .ZN(n_1_0_596)); + NOR2_X1_LVT i_1_0_659 (.A1(n_1_0_650), .A2(n_1_0_628), .ZN(n_1_0_627)); + NOR2_X1_LVT i_1_0_651 (.A1(n_1_0_641), .A2(n_1_0_628), .ZN(n_1_0_619)); + AOI22_X1_LVT i_1_0_627 (.A1(registers_15__ap[31]), .A2(n_1_0_627), .B1( + n_1_0_619), .B2(registers_14__ap[31]), .ZN(n_1_0_595)); + NOR2_X1_LVT i_1_0_668 (.A1(n_1_0_650), .A2(n_1_0_648), .ZN(n_1_0_636)); + NOR2_X1_LVT i_1_0_643 (.A1(n_1_0_650), .A2(n_1_0_625), .ZN(n_1_0_611)); + AOI22_X1_LVT i_1_0_626 (.A1(registers_27__ap[31]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[31]), .ZN(n_1_0_594)); + NOR2_X1_LVT i_1_0_650 (.A1(n_1_0_647), .A2(n_1_0_625), .ZN(n_1_0_618)); + NOR2_X1_LVT i_1_0_642 (.A1(n_1_0_645), .A2(n_1_0_625), .ZN(n_1_0_610)); + AOI22_X1_LVT i_1_0_625 (.A1(registers_2__ap[31]), .A2(n_1_0_618), .B1( + n_1_0_610), .B2(registers_3__ap[31]), .ZN(n_1_0_593)); + NAND4_X1_LVT i_1_0_624 (.A1(n_1_0_596), .A2(n_1_0_595), .A3(n_1_0_594), + .A4(n_1_0_593), .ZN(n_1_0_592)); + NOR3_X1_LVT i_1_0_623 (.A1(n_1_0_602), .A2(n_1_0_597), .A3(n_1_0_592), + .ZN(n_1_0_591)); + NAND4_X1_LVT i_1_0_622 (.A1(n_1_0_609), .A2(n_1_0_608), .A3(n_1_0_607), + .A4(n_1_0_591), .ZN(RRs2[31])); + AOI22_X1_LVT i_1_0_620 (.A1(registers_29__ap[30]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[30]), .ZN(n_1_0_589)); + AOI22_X1_LVT i_1_0_621 (.A1(registers_7__ap[30]), .A2(n_1_0_623), .B1( + n_1_0_615), .B2(registers_23__ap[30]), .ZN(n_1_0_590)); + AOI22_X1_LVT i_1_0_619 (.A1(registers_1__ap[30]), .A2(n_1_0_644), .B1( + n_1_0_616), .B2(registers_6__ap[30]), .ZN(n_1_0_588)); + AOI22_X1_LVT i_1_0_618 (.A1(registers_5__ap[30]), .A2(n_1_0_635), .B1( + n_1_0_633), .B2(registers_19__ap[30]), .ZN(n_1_0_587)); + NAND3_X1_LVT i_1_0_617 (.A1(n_1_0_590), .A2(n_1_0_588), .A3(n_1_0_587), + .ZN(n_1_0_586)); + AOI221_X1_LVT i_1_0_616 (.A(n_1_0_586), .B1(n_1_0_637), .B2( + registers_31__ap[30]), .C1(registers_16__ap[30]), .C2(n_1_0_614), .ZN( + n_1_0_585)); + AOI222_X1_LVT i_1_0_615 (.A1(registers_26__ap[30]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[30]), .C1(n_1_0_626), .C2( + registers_8__ap[30]), .ZN(n_1_0_584)); + NAND3_X1_LVT i_1_0_614 (.A1(n_1_0_589), .A2(n_1_0_585), .A3(n_1_0_584), + .ZN(n_1_0_583)); + AOI221_X1_LVT i_1_0_613 (.A(n_1_0_583), .B1(n_1_0_629), .B2( + registers_17__ap[30]), .C1(registers_28__ap[30]), .C2(n_1_0_634), .ZN( + n_1_0_582)); + AOI22_X1_LVT i_1_0_612 (.A1(registers_18__ap[30]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[30]), .ZN(n_1_0_581)); + AOI22_X1_LVT i_1_0_611 (.A1(registers_4__ap[30]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[30]), .ZN(n_1_0_580)); + AOI22_X1_LVT i_1_0_610 (.A1(registers_22__ap[30]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[30]), .ZN(n_1_0_579)); + NAND3_X1_LVT i_1_0_609 (.A1(n_1_0_581), .A2(n_1_0_580), .A3(n_1_0_579), + .ZN(n_1_0_578)); + AOI221_X1_LVT i_1_0_608 (.A(n_1_0_578), .B1(n_1_0_621), .B2( + registers_24__ap[30]), .C1(registers_12__ap[30]), .C2(n_1_0_632), .ZN( + n_1_0_577)); + AOI22_X1_LVT i_1_0_607 (.A1(registers_13__ap[30]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[30]), .ZN(n_1_0_576)); + AOI22_X1_LVT i_1_0_606 (.A1(registers_15__ap[30]), .A2(n_1_0_627), .B1( + n_1_0_619), .B2(registers_14__ap[30]), .ZN(n_1_0_575)); + AOI22_X1_LVT i_1_0_605 (.A1(registers_27__ap[30]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[30]), .ZN(n_1_0_574)); + NAND3_X1_LVT i_1_0_604 (.A1(n_1_0_576), .A2(n_1_0_575), .A3(n_1_0_574), + .ZN(n_1_0_573)); + AOI221_X1_LVT i_1_0_603 (.A(n_1_0_573), .B1(n_1_0_610), .B2( + registers_3__ap[30]), .C1(registers_2__ap[30]), .C2(n_1_0_618), .ZN( + n_1_0_572)); + NAND3_X1_LVT i_1_0_602 (.A1(n_1_0_582), .A2(n_1_0_577), .A3(n_1_0_572), + .ZN(RRs2[30])); + AOI22_X1_LVT i_1_0_600 (.A1(registers_28__ap[29]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[29]), .ZN(n_1_0_570)); + AOI22_X1_LVT i_1_0_601 (.A1(registers_31__ap[29]), .A2(n_1_0_637), .B1( + n_1_0_627), .B2(registers_15__ap[29]), .ZN(n_1_0_571)); + AOI22_X1_LVT i_1_0_599 (.A1(registers_24__ap[29]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[29]), .ZN(n_1_0_569)); + AOI22_X1_LVT i_1_0_598 (.A1(registers_19__ap[29]), .A2(n_1_0_633), .B1( + n_1_0_629), .B2(registers_17__ap[29]), .ZN(n_1_0_568)); + NAND3_X1_LVT i_1_0_597 (.A1(n_1_0_571), .A2(n_1_0_569), .A3(n_1_0_568), + .ZN(n_1_0_567)); + AOI221_X1_LVT i_1_0_596 (.A(n_1_0_567), .B1(n_1_0_615), .B2( + registers_23__ap[29]), .C1(registers_29__ap[29]), .C2(n_1_0_649), .ZN( + n_1_0_566)); + AOI222_X1_LVT i_1_0_595 (.A1(registers_26__ap[29]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[29]), .C1(n_1_0_620), .C2( + registers_25__ap[29]), .ZN(n_1_0_565)); + NAND3_X1_LVT i_1_0_594 (.A1(n_1_0_570), .A2(n_1_0_566), .A3(n_1_0_565), + .ZN(n_1_0_564)); + AOI221_X1_LVT i_1_0_593 (.A(n_1_0_564), .B1(n_1_0_612), .B2( + registers_21__ap[29]), .C1(registers_13__ap[29]), .C2(n_1_0_631), .ZN( + n_1_0_563)); + AOI22_X1_LVT i_1_0_592 (.A1(registers_18__ap[29]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[29]), .ZN(n_1_0_562)); + AOI22_X1_LVT i_1_0_591 (.A1(registers_4__ap[29]), .A2(n_1_0_638), .B1( + n_1_0_632), .B2(registers_12__ap[29]), .ZN(n_1_0_561)); + AOI22_X1_LVT i_1_0_590 (.A1(registers_7__ap[29]), .A2(n_1_0_623), .B1( + n_1_0_614), .B2(registers_16__ap[29]), .ZN(n_1_0_560)); + NAND3_X1_LVT i_1_0_589 (.A1(n_1_0_562), .A2(n_1_0_561), .A3(n_1_0_560), + .ZN(n_1_0_559)); + AOI221_X1_LVT i_1_0_588 (.A(n_1_0_559), .B1(n_1_0_642), .B2( + registers_22__ap[29]), .C1(registers_5__ap[29]), .C2(n_1_0_635), .ZN( + n_1_0_558)); + AOI22_X1_LVT i_1_0_587 (.A1(registers_1__ap[29]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[29]), .ZN(n_1_0_557)); + AOI22_X1_LVT i_1_0_586 (.A1(registers_14__ap[29]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[29]), .ZN(n_1_0_556)); + AOI22_X1_LVT i_1_0_585 (.A1(registers_27__ap[29]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[29]), .ZN(n_1_0_555)); + NAND3_X1_LVT i_1_0_584 (.A1(n_1_0_557), .A2(n_1_0_556), .A3(n_1_0_555), + .ZN(n_1_0_554)); + AOI221_X1_LVT i_1_0_583 (.A(n_1_0_554), .B1(n_1_0_610), .B2( + registers_3__ap[29]), .C1(registers_2__ap[29]), .C2(n_1_0_618), .ZN( + n_1_0_553)); + NAND3_X1_LVT i_1_0_582 (.A1(n_1_0_563), .A2(n_1_0_558), .A3(n_1_0_553), + .ZN(RRs2[29])); + AOI22_X1_LVT i_1_0_581 (.A1(registers_5__ap[28]), .A2(n_1_0_635), .B1( + n_1_0_634), .B2(registers_28__ap[28]), .ZN(n_1_0_552)); + AOI222_X1_LVT i_1_0_580 (.A1(registers_26__ap[28]), .A2(n_1_0_640), .B1( + n_1_0_633), .B2(registers_19__ap[28]), .C1(n_1_0_626), .C2( + registers_8__ap[28]), .ZN(n_1_0_551)); + AOI22_X1_LVT i_1_0_579 (.A1(registers_2__ap[28]), .A2(n_1_0_618), .B1( + n_1_0_617), .B2(registers_9__ap[28]), .ZN(n_1_0_550)); + AOI22_X1_LVT i_1_0_578 (.A1(registers_7__ap[28]), .A2(n_1_0_623), .B1( + n_1_0_612), .B2(registers_21__ap[28]), .ZN(n_1_0_549)); + AOI22_X1_LVT i_1_0_577 (.A1(registers_16__ap[28]), .A2(n_1_0_614), .B1( + n_1_0_611), .B2(registers_11__ap[28]), .ZN(n_1_0_548)); + AOI22_X1_LVT i_1_0_576 (.A1(registers_31__ap[28]), .A2(n_1_0_637), .B1( + n_1_0_619), .B2(registers_14__ap[28]), .ZN(n_1_0_547)); + AOI22_X1_LVT i_1_0_575 (.A1(registers_15__ap[28]), .A2(n_1_0_627), .B1( + n_1_0_610), .B2(registers_3__ap[28]), .ZN(n_1_0_546)); + NAND4_X1_LVT i_1_0_574 (.A1(n_1_0_549), .A2(n_1_0_548), .A3(n_1_0_547), + .A4(n_1_0_546), .ZN(n_1_0_545)); + AOI22_X1_LVT i_1_0_573 (.A1(registers_22__ap[28]), .A2(n_1_0_642), .B1( + n_1_0_622), .B2(registers_30__ap[28]), .ZN(n_1_0_544)); + AOI22_X1_LVT i_1_0_572 (.A1(registers_4__ap[28]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[28]), .ZN(n_1_0_543)); + AOI22_X1_LVT i_1_0_571 (.A1(registers_29__ap[28]), .A2(n_1_0_649), .B1( + n_1_0_644), .B2(registers_1__ap[28]), .ZN(n_1_0_542)); + AOI22_X1_LVT i_1_0_570 (.A1(registers_12__ap[28]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[28]), .ZN(n_1_0_541)); + NAND4_X1_LVT i_1_0_569 (.A1(n_1_0_544), .A2(n_1_0_543), .A3(n_1_0_542), + .A4(n_1_0_541), .ZN(n_1_0_540)); + AOI22_X1_LVT i_1_0_568 (.A1(registers_13__ap[28]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[28]), .ZN(n_1_0_539)); + AOI22_X1_LVT i_1_0_567 (.A1(registers_17__ap[28]), .A2(n_1_0_629), .B1( + n_1_0_616), .B2(registers_6__ap[28]), .ZN(n_1_0_538)); + AOI22_X1_LVT i_1_0_566 (.A1(registers_10__ap[28]), .A2(n_1_0_624), .B1( + n_1_0_615), .B2(registers_23__ap[28]), .ZN(n_1_0_537)); + AOI22_X1_LVT i_1_0_565 (.A1(registers_18__ap[28]), .A2(n_1_0_646), .B1( + n_1_0_636), .B2(registers_27__ap[28]), .ZN(n_1_0_536)); + NAND4_X1_LVT i_1_0_564 (.A1(n_1_0_539), .A2(n_1_0_538), .A3(n_1_0_537), + .A4(n_1_0_536), .ZN(n_1_0_535)); + NOR3_X1_LVT i_1_0_563 (.A1(n_1_0_545), .A2(n_1_0_540), .A3(n_1_0_535), + .ZN(n_1_0_534)); + NAND4_X1_LVT i_1_0_562 (.A1(n_1_0_552), .A2(n_1_0_551), .A3(n_1_0_550), + .A4(n_1_0_534), .ZN(RRs2[28])); + AOI22_X1_LVT i_1_0_561 (.A1(registers_17__ap[27]), .A2(n_1_0_629), .B1( + n_1_0_612), .B2(registers_21__ap[27]), .ZN(n_1_0_533)); + AOI222_X1_LVT i_1_0_560 (.A1(registers_19__ap[27]), .A2(n_1_0_633), .B1( + n_1_0_631), .B2(registers_13__ap[27]), .C1(registers_30__ap[27]), .C2( + n_1_0_622), .ZN(n_1_0_532)); + AOI22_X1_LVT i_1_0_559 (.A1(registers_1__ap[27]), .A2(n_1_0_644), .B1( + n_1_0_634), .B2(registers_28__ap[27]), .ZN(n_1_0_531)); + AOI22_X1_LVT i_1_0_558 (.A1(registers_24__ap[27]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[27]), .ZN(n_1_0_530)); + AOI22_X1_LVT i_1_0_557 (.A1(registers_15__ap[27]), .A2(n_1_0_627), .B1( + n_1_0_611), .B2(registers_11__ap[27]), .ZN(n_1_0_529)); + AOI22_X1_LVT i_1_0_556 (.A1(registers_4__ap[27]), .A2(n_1_0_638), .B1( + n_1_0_636), .B2(registers_27__ap[27]), .ZN(n_1_0_528)); + AOI22_X1_LVT i_1_0_555 (.A1(registers_31__ap[27]), .A2(n_1_0_637), .B1( + n_1_0_618), .B2(registers_2__ap[27]), .ZN(n_1_0_527)); + NAND4_X1_LVT i_1_0_554 (.A1(n_1_0_530), .A2(n_1_0_529), .A3(n_1_0_528), + .A4(n_1_0_527), .ZN(n_1_0_526)); + AOI22_X1_LVT i_1_0_553 (.A1(registers_18__ap[27]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[27]), .ZN(n_1_0_525)); + AOI22_X1_LVT i_1_0_552 (.A1(registers_5__ap[27]), .A2(n_1_0_635), .B1( + n_1_0_632), .B2(registers_12__ap[27]), .ZN(n_1_0_524)); + AOI22_X1_LVT i_1_0_551 (.A1(registers_6__ap[27]), .A2(n_1_0_616), .B1( + n_1_0_614), .B2(registers_16__ap[27]), .ZN(n_1_0_523)); + AOI22_X1_LVT i_1_0_550 (.A1(registers_22__ap[27]), .A2(n_1_0_642), .B1( + n_1_0_620), .B2(registers_25__ap[27]), .ZN(n_1_0_522)); + NAND4_X1_LVT i_1_0_549 (.A1(n_1_0_525), .A2(n_1_0_524), .A3(n_1_0_523), + .A4(n_1_0_522), .ZN(n_1_0_521)); + AOI22_X1_LVT i_1_0_548 (.A1(registers_29__ap[27]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[27]), .ZN(n_1_0_520)); + AOI22_X1_LVT i_1_0_547 (.A1(registers_7__ap[27]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[27]), .ZN(n_1_0_519)); + AOI22_X1_LVT i_1_0_546 (.A1(registers_8__ap[27]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[27]), .ZN(n_1_0_518)); + AOI22_X1_LVT i_1_0_545 (.A1(registers_10__ap[27]), .A2(n_1_0_624), .B1( + n_1_0_610), .B2(registers_3__ap[27]), .ZN(n_1_0_517)); + NAND4_X1_LVT i_1_0_544 (.A1(n_1_0_520), .A2(n_1_0_519), .A3(n_1_0_518), + .A4(n_1_0_517), .ZN(n_1_0_516)); + NOR3_X1_LVT i_1_0_543 (.A1(n_1_0_526), .A2(n_1_0_521), .A3(n_1_0_516), + .ZN(n_1_0_515)); + NAND4_X1_LVT i_1_0_542 (.A1(n_1_0_533), .A2(n_1_0_532), .A3(n_1_0_531), + .A4(n_1_0_515), .ZN(RRs2[27])); + AOI22_X1_LVT i_1_0_541 (.A1(registers_17__ap[26]), .A2(n_1_0_629), .B1( + n_1_0_612), .B2(registers_21__ap[26]), .ZN(n_1_0_514)); + AOI222_X1_LVT i_1_0_540 (.A1(registers_19__ap[26]), .A2(n_1_0_633), .B1( + n_1_0_622), .B2(registers_30__ap[26]), .C1(n_1_0_631), .C2( + registers_13__ap[26]), .ZN(n_1_0_513)); + AOI22_X1_LVT i_1_0_539 (.A1(registers_1__ap[26]), .A2(n_1_0_644), .B1( + n_1_0_634), .B2(registers_28__ap[26]), .ZN(n_1_0_512)); + AOI22_X1_LVT i_1_0_538 (.A1(registers_24__ap[26]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[26]), .ZN(n_1_0_511)); + AOI22_X1_LVT i_1_0_537 (.A1(registers_15__ap[26]), .A2(n_1_0_627), .B1( + n_1_0_611), .B2(registers_11__ap[26]), .ZN(n_1_0_510)); + AOI22_X1_LVT i_1_0_536 (.A1(registers_4__ap[26]), .A2(n_1_0_638), .B1( + n_1_0_636), .B2(registers_27__ap[26]), .ZN(n_1_0_509)); + AOI22_X1_LVT i_1_0_535 (.A1(registers_31__ap[26]), .A2(n_1_0_637), .B1( + n_1_0_618), .B2(registers_2__ap[26]), .ZN(n_1_0_508)); + NAND4_X1_LVT i_1_0_534 (.A1(n_1_0_511), .A2(n_1_0_510), .A3(n_1_0_509), + .A4(n_1_0_508), .ZN(n_1_0_507)); + AOI22_X1_LVT i_1_0_533 (.A1(registers_18__ap[26]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[26]), .ZN(n_1_0_506)); + AOI22_X1_LVT i_1_0_532 (.A1(registers_5__ap[26]), .A2(n_1_0_635), .B1( + n_1_0_632), .B2(registers_12__ap[26]), .ZN(n_1_0_505)); + AOI22_X1_LVT i_1_0_531 (.A1(registers_6__ap[26]), .A2(n_1_0_616), .B1( + n_1_0_614), .B2(registers_16__ap[26]), .ZN(n_1_0_504)); + AOI22_X1_LVT i_1_0_530 (.A1(registers_22__ap[26]), .A2(n_1_0_642), .B1( + n_1_0_620), .B2(registers_25__ap[26]), .ZN(n_1_0_503)); + NAND4_X1_LVT i_1_0_529 (.A1(n_1_0_506), .A2(n_1_0_505), .A3(n_1_0_504), + .A4(n_1_0_503), .ZN(n_1_0_502)); + AOI22_X1_LVT i_1_0_528 (.A1(registers_29__ap[26]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[26]), .ZN(n_1_0_501)); + AOI22_X1_LVT i_1_0_527 (.A1(registers_7__ap[26]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[26]), .ZN(n_1_0_500)); + AOI22_X1_LVT i_1_0_526 (.A1(registers_8__ap[26]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[26]), .ZN(n_1_0_499)); + AOI22_X1_LVT i_1_0_525 (.A1(registers_10__ap[26]), .A2(n_1_0_624), .B1( + n_1_0_610), .B2(registers_3__ap[26]), .ZN(n_1_0_498)); + NAND4_X1_LVT i_1_0_524 (.A1(n_1_0_501), .A2(n_1_0_500), .A3(n_1_0_499), + .A4(n_1_0_498), .ZN(n_1_0_497)); + NOR3_X1_LVT i_1_0_523 (.A1(n_1_0_507), .A2(n_1_0_502), .A3(n_1_0_497), + .ZN(n_1_0_496)); + NAND4_X1_LVT i_1_0_522 (.A1(n_1_0_514), .A2(n_1_0_513), .A3(n_1_0_512), + .A4(n_1_0_496), .ZN(RRs2[26])); + AOI22_X1_LVT i_1_0_520 (.A1(registers_5__ap[25]), .A2(n_1_0_635), .B1( + n_1_0_634), .B2(registers_28__ap[25]), .ZN(n_1_0_494)); + AOI22_X1_LVT i_1_0_521 (.A1(registers_8__ap[25]), .A2(n_1_0_626), .B1( + n_1_0_620), .B2(registers_25__ap[25]), .ZN(n_1_0_495)); + AOI22_X1_LVT i_1_0_519 (.A1(registers_14__ap[25]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[25]), .ZN(n_1_0_493)); + AOI22_X1_LVT i_1_0_518 (.A1(registers_16__ap[25]), .A2(n_1_0_614), .B1( + n_1_0_611), .B2(registers_11__ap[25]), .ZN(n_1_0_492)); + NAND3_X1_LVT i_1_0_517 (.A1(n_1_0_495), .A2(n_1_0_493), .A3(n_1_0_492), + .ZN(n_1_0_491)); + AOI221_X1_LVT i_1_0_516 (.A(n_1_0_491), .B1(n_1_0_624), .B2( + registers_10__ap[25]), .C1(registers_6__ap[25]), .C2(n_1_0_616), .ZN( + n_1_0_490)); + AOI222_X1_LVT i_1_0_515 (.A1(registers_1__ap[25]), .A2(n_1_0_644), .B1( + n_1_0_640), .B2(registers_26__ap[25]), .C1(n_1_0_622), .C2( + registers_30__ap[25]), .ZN(n_1_0_489)); + NAND2_X1_LVT i_1_0_514 (.A1(n_1_0_490), .A2(n_1_0_489), .ZN(n_1_0_488)); + AOI221_X1_LVT i_1_0_513 (.A(n_1_0_488), .B1(n_1_0_649), .B2( + registers_29__ap[25]), .C1(registers_2__ap[25]), .C2(n_1_0_618), .ZN( + n_1_0_487)); + AOI22_X1_LVT i_1_0_512 (.A1(registers_12__ap[25]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[25]), .ZN(n_1_0_486)); + AOI22_X1_LVT i_1_0_511 (.A1(registers_22__ap[25]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[25]), .ZN(n_1_0_485)); + AOI22_X1_LVT i_1_0_510 (.A1(registers_4__ap[25]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[25]), .ZN(n_1_0_484)); + NAND3_X1_LVT i_1_0_509 (.A1(n_1_0_486), .A2(n_1_0_485), .A3(n_1_0_484), + .ZN(n_1_0_483)); + AOI221_X1_LVT i_1_0_508 (.A(n_1_0_483), .B1(n_1_0_633), .B2( + registers_19__ap[25]), .C1(registers_18__ap[25]), .C2(n_1_0_646), .ZN( + n_1_0_482)); + AOI22_X1_LVT i_1_0_507 (.A1(registers_15__ap[25]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[25]), .ZN(n_1_0_481)); + AOI22_X1_LVT i_1_0_506 (.A1(registers_23__ap[25]), .A2(n_1_0_615), .B1( + n_1_0_610), .B2(registers_3__ap[25]), .ZN(n_1_0_480)); + AOI22_X1_LVT i_1_0_505 (.A1(registers_13__ap[25]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[25]), .ZN(n_1_0_479)); + NAND3_X1_LVT i_1_0_504 (.A1(n_1_0_481), .A2(n_1_0_480), .A3(n_1_0_479), + .ZN(n_1_0_478)); + AOI221_X1_LVT i_1_0_503 (.A(n_1_0_478), .B1(n_1_0_636), .B2( + registers_27__ap[25]), .C1(registers_31__ap[25]), .C2(n_1_0_637), .ZN( + n_1_0_477)); + NAND4_X1_LVT i_1_0_502 (.A1(n_1_0_494), .A2(n_1_0_487), .A3(n_1_0_482), + .A4(n_1_0_477), .ZN(RRs2[25])); + AOI22_X1_LVT i_1_0_501 (.A1(registers_17__ap[24]), .A2(n_1_0_629), .B1( + n_1_0_612), .B2(registers_21__ap[24]), .ZN(n_1_0_476)); + AOI222_X1_LVT i_1_0_500 (.A1(registers_13__ap[24]), .A2(n_1_0_631), .B1( + n_1_0_622), .B2(registers_30__ap[24]), .C1(registers_26__ap[24]), .C2( + n_1_0_640), .ZN(n_1_0_475)); + AOI22_X1_LVT i_1_0_499 (.A1(registers_1__ap[24]), .A2(n_1_0_644), .B1( + n_1_0_634), .B2(registers_28__ap[24]), .ZN(n_1_0_474)); + AOI22_X1_LVT i_1_0_498 (.A1(registers_24__ap[24]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[24]), .ZN(n_1_0_473)); + AOI22_X1_LVT i_1_0_497 (.A1(registers_8__ap[24]), .A2(n_1_0_626), .B1( + n_1_0_616), .B2(registers_6__ap[24]), .ZN(n_1_0_472)); + AOI22_X1_LVT i_1_0_496 (.A1(registers_4__ap[24]), .A2(n_1_0_638), .B1( + n_1_0_611), .B2(registers_11__ap[24]), .ZN(n_1_0_471)); + AOI22_X1_LVT i_1_0_495 (.A1(registers_10__ap[24]), .A2(n_1_0_624), .B1( + n_1_0_618), .B2(registers_2__ap[24]), .ZN(n_1_0_470)); + NAND4_X1_LVT i_1_0_494 (.A1(n_1_0_473), .A2(n_1_0_472), .A3(n_1_0_471), + .A4(n_1_0_470), .ZN(n_1_0_469)); + AOI22_X1_LVT i_1_0_493 (.A1(registers_18__ap[24]), .A2(n_1_0_646), .B1( + n_1_0_633), .B2(registers_19__ap[24]), .ZN(n_1_0_468)); + AOI22_X1_LVT i_1_0_492 (.A1(registers_5__ap[24]), .A2(n_1_0_635), .B1( + n_1_0_632), .B2(registers_12__ap[24]), .ZN(n_1_0_467)); + AOI22_X1_LVT i_1_0_491 (.A1(registers_15__ap[24]), .A2(n_1_0_627), .B1( + n_1_0_614), .B2(registers_16__ap[24]), .ZN(n_1_0_466)); + AOI22_X1_LVT i_1_0_490 (.A1(registers_22__ap[24]), .A2(n_1_0_642), .B1( + n_1_0_620), .B2(registers_25__ap[24]), .ZN(n_1_0_465)); + NAND4_X1_LVT i_1_0_489 (.A1(n_1_0_468), .A2(n_1_0_467), .A3(n_1_0_466), + .A4(n_1_0_465), .ZN(n_1_0_464)); + AOI22_X1_LVT i_1_0_488 (.A1(registers_29__ap[24]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[24]), .ZN(n_1_0_463)); + AOI22_X1_LVT i_1_0_487 (.A1(registers_7__ap[24]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[24]), .ZN(n_1_0_462)); + AOI22_X1_LVT i_1_0_486 (.A1(registers_23__ap[24]), .A2(n_1_0_615), .B1( + n_1_0_610), .B2(registers_3__ap[24]), .ZN(n_1_0_461)); + AOI22_X1_LVT i_1_0_485 (.A1(registers_31__ap[24]), .A2(n_1_0_637), .B1( + n_1_0_636), .B2(registers_27__ap[24]), .ZN(n_1_0_460)); + NAND4_X1_LVT i_1_0_484 (.A1(n_1_0_463), .A2(n_1_0_462), .A3(n_1_0_461), + .A4(n_1_0_460), .ZN(n_1_0_459)); + NOR3_X1_LVT i_1_0_483 (.A1(n_1_0_469), .A2(n_1_0_464), .A3(n_1_0_459), + .ZN(n_1_0_458)); + NAND4_X1_LVT i_1_0_482 (.A1(n_1_0_476), .A2(n_1_0_475), .A3(n_1_0_474), + .A4(n_1_0_458), .ZN(RRs2[24])); + AOI22_X1_LVT i_1_0_481 (.A1(registers_4__ap[23]), .A2(n_1_0_638), .B1( + n_1_0_634), .B2(registers_28__ap[23]), .ZN(n_1_0_457)); + AOI222_X1_LVT i_1_0_480 (.A1(registers_18__ap[23]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[23]), .C1(n_1_0_644), .C2( + registers_1__ap[23]), .ZN(n_1_0_456)); + AOI22_X1_LVT i_1_0_479 (.A1(registers_29__ap[23]), .A2(n_1_0_649), .B1( + n_1_0_618), .B2(registers_2__ap[23]), .ZN(n_1_0_455)); + AOI22_X1_LVT i_1_0_478 (.A1(registers_14__ap[23]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[23]), .ZN(n_1_0_454)); + AOI22_X1_LVT i_1_0_477 (.A1(registers_16__ap[23]), .A2(n_1_0_614), .B1( + n_1_0_611), .B2(registers_11__ap[23]), .ZN(n_1_0_453)); + AOI22_X1_LVT i_1_0_476 (.A1(registers_27__ap[23]), .A2(n_1_0_636), .B1( + n_1_0_620), .B2(registers_25__ap[23]), .ZN(n_1_0_452)); + AOI22_X1_LVT i_1_0_475 (.A1(registers_31__ap[23]), .A2(n_1_0_637), .B1( + n_1_0_616), .B2(registers_6__ap[23]), .ZN(n_1_0_451)); + NAND4_X1_LVT i_1_0_474 (.A1(n_1_0_454), .A2(n_1_0_453), .A3(n_1_0_452), + .A4(n_1_0_451), .ZN(n_1_0_450)); + AOI22_X1_LVT i_1_0_473 (.A1(registers_26__ap[23]), .A2(n_1_0_640), .B1( + n_1_0_633), .B2(registers_19__ap[23]), .ZN(n_1_0_449)); + AOI22_X1_LVT i_1_0_472 (.A1(registers_12__ap[23]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[23]), .ZN(n_1_0_448)); + AOI22_X1_LVT i_1_0_471 (.A1(registers_22__ap[23]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[23]), .ZN(n_1_0_447)); + AOI22_X1_LVT i_1_0_470 (.A1(registers_5__ap[23]), .A2(n_1_0_635), .B1( + n_1_0_613), .B2(registers_20__ap[23]), .ZN(n_1_0_446)); + NAND4_X1_LVT i_1_0_469 (.A1(n_1_0_449), .A2(n_1_0_448), .A3(n_1_0_447), + .A4(n_1_0_446), .ZN(n_1_0_445)); + AOI22_X1_LVT i_1_0_468 (.A1(registers_15__ap[23]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[23]), .ZN(n_1_0_444)); + AOI22_X1_LVT i_1_0_467 (.A1(registers_8__ap[23]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[23]), .ZN(n_1_0_443)); + AOI22_X1_LVT i_1_0_466 (.A1(registers_13__ap[23]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[23]), .ZN(n_1_0_442)); + AOI22_X1_LVT i_1_0_465 (.A1(registers_10__ap[23]), .A2(n_1_0_624), .B1( + n_1_0_610), .B2(registers_3__ap[23]), .ZN(n_1_0_441)); + NAND4_X1_LVT i_1_0_464 (.A1(n_1_0_444), .A2(n_1_0_443), .A3(n_1_0_442), + .A4(n_1_0_441), .ZN(n_1_0_440)); + NOR3_X1_LVT i_1_0_463 (.A1(n_1_0_450), .A2(n_1_0_445), .A3(n_1_0_440), + .ZN(n_1_0_439)); + NAND4_X1_LVT i_1_0_462 (.A1(n_1_0_457), .A2(n_1_0_456), .A3(n_1_0_455), + .A4(n_1_0_439), .ZN(RRs2[23])); + AOI22_X1_LVT i_1_0_460 (.A1(registers_17__ap[22]), .A2(n_1_0_629), .B1( + n_1_0_612), .B2(registers_21__ap[22]), .ZN(n_1_0_437)); + AOI22_X1_LVT i_1_0_461 (.A1(registers_15__ap[22]), .A2(n_1_0_627), .B1( + n_1_0_626), .B2(registers_8__ap[22]), .ZN(n_1_0_438)); + AOI22_X1_LVT i_1_0_459 (.A1(registers_24__ap[22]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[22]), .ZN(n_1_0_436)); + AOI22_X1_LVT i_1_0_458 (.A1(registers_5__ap[22]), .A2(n_1_0_635), .B1( + n_1_0_611), .B2(registers_11__ap[22]), .ZN(n_1_0_435)); + NAND3_X1_LVT i_1_0_457 (.A1(n_1_0_438), .A2(n_1_0_436), .A3(n_1_0_435), + .ZN(n_1_0_434)); + AOI221_X1_LVT i_1_0_456 (.A(n_1_0_434), .B1(n_1_0_618), .B2( + registers_2__ap[22]), .C1(registers_10__ap[22]), .C2(n_1_0_624), .ZN( + n_1_0_433)); + AOI222_X1_LVT i_1_0_455 (.A1(registers_26__ap[22]), .A2(n_1_0_640), .B1( + n_1_0_622), .B2(registers_30__ap[22]), .C1(n_1_0_631), .C2( + registers_13__ap[22]), .ZN(n_1_0_432)); + NAND2_X1_LVT i_1_0_454 (.A1(n_1_0_433), .A2(n_1_0_432), .ZN(n_1_0_431)); + AOI221_X1_LVT i_1_0_453 (.A(n_1_0_431), .B1(n_1_0_644), .B2( + registers_1__ap[22]), .C1(registers_28__ap[22]), .C2(n_1_0_634), .ZN( + n_1_0_430)); + AOI22_X1_LVT i_1_0_452 (.A1(registers_18__ap[22]), .A2(n_1_0_646), .B1( + n_1_0_633), .B2(registers_19__ap[22]), .ZN(n_1_0_429)); + AOI22_X1_LVT i_1_0_451 (.A1(registers_4__ap[22]), .A2(n_1_0_638), .B1( + n_1_0_632), .B2(registers_12__ap[22]), .ZN(n_1_0_428)); + AOI22_X1_LVT i_1_0_450 (.A1(registers_6__ap[22]), .A2(n_1_0_616), .B1( + n_1_0_614), .B2(registers_16__ap[22]), .ZN(n_1_0_427)); + NAND3_X1_LVT i_1_0_449 (.A1(n_1_0_429), .A2(n_1_0_428), .A3(n_1_0_427), + .ZN(n_1_0_426)); + AOI221_X1_LVT i_1_0_448 (.A(n_1_0_426), .B1(n_1_0_620), .B2( + registers_25__ap[22]), .C1(registers_22__ap[22]), .C2(n_1_0_642), .ZN( + n_1_0_425)); + AOI22_X1_LVT i_1_0_447 (.A1(registers_29__ap[22]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[22]), .ZN(n_1_0_424)); + AOI22_X1_LVT i_1_0_446 (.A1(registers_7__ap[22]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[22]), .ZN(n_1_0_423)); + AOI22_X1_LVT i_1_0_445 (.A1(registers_23__ap[22]), .A2(n_1_0_615), .B1( + n_1_0_610), .B2(registers_3__ap[22]), .ZN(n_1_0_422)); + NAND3_X1_LVT i_1_0_444 (.A1(n_1_0_424), .A2(n_1_0_423), .A3(n_1_0_422), + .ZN(n_1_0_421)); + AOI221_X1_LVT i_1_0_443 (.A(n_1_0_421), .B1(n_1_0_636), .B2( + registers_27__ap[22]), .C1(registers_31__ap[22]), .C2(n_1_0_637), .ZN( + n_1_0_420)); + NAND4_X1_LVT i_1_0_442 (.A1(n_1_0_437), .A2(n_1_0_430), .A3(n_1_0_425), + .A4(n_1_0_420), .ZN(RRs2[22])); + AOI22_X1_LVT i_1_0_441 (.A1(registers_5__ap[21]), .A2(n_1_0_635), .B1( + n_1_0_634), .B2(registers_28__ap[21]), .ZN(n_1_0_419)); + AOI222_X1_LVT i_1_0_440 (.A1(registers_1__ap[21]), .A2(n_1_0_644), .B1( + n_1_0_640), .B2(registers_26__ap[21]), .C1(n_1_0_622), .C2( + registers_30__ap[21]), .ZN(n_1_0_418)); + AOI22_X1_LVT i_1_0_439 (.A1(registers_29__ap[21]), .A2(n_1_0_649), .B1( + n_1_0_618), .B2(registers_2__ap[21]), .ZN(n_1_0_417)); + AOI22_X1_LVT i_1_0_438 (.A1(registers_14__ap[21]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[21]), .ZN(n_1_0_416)); + AOI22_X1_LVT i_1_0_437 (.A1(registers_8__ap[21]), .A2(n_1_0_626), .B1( + n_1_0_614), .B2(registers_16__ap[21]), .ZN(n_1_0_415)); + AOI22_X1_LVT i_1_0_436 (.A1(registers_25__ap[21]), .A2(n_1_0_620), .B1( + n_1_0_611), .B2(registers_11__ap[21]), .ZN(n_1_0_414)); + AOI22_X1_LVT i_1_0_435 (.A1(registers_10__ap[21]), .A2(n_1_0_624), .B1( + n_1_0_616), .B2(registers_6__ap[21]), .ZN(n_1_0_413)); + NAND4_X1_LVT i_1_0_434 (.A1(n_1_0_416), .A2(n_1_0_415), .A3(n_1_0_414), + .A4(n_1_0_413), .ZN(n_1_0_412)); + AOI22_X1_LVT i_1_0_433 (.A1(registers_12__ap[21]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[21]), .ZN(n_1_0_411)); + AOI22_X1_LVT i_1_0_432 (.A1(registers_22__ap[21]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[21]), .ZN(n_1_0_410)); + AOI22_X1_LVT i_1_0_431 (.A1(registers_4__ap[21]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[21]), .ZN(n_1_0_409)); + AOI22_X1_LVT i_1_0_430 (.A1(registers_18__ap[21]), .A2(n_1_0_646), .B1( + n_1_0_633), .B2(registers_19__ap[21]), .ZN(n_1_0_408)); + NAND4_X1_LVT i_1_0_429 (.A1(n_1_0_411), .A2(n_1_0_410), .A3(n_1_0_409), + .A4(n_1_0_408), .ZN(n_1_0_407)); + AOI22_X1_LVT i_1_0_428 (.A1(registers_15__ap[21]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[21]), .ZN(n_1_0_406)); + AOI22_X1_LVT i_1_0_427 (.A1(registers_23__ap[21]), .A2(n_1_0_615), .B1( + n_1_0_610), .B2(registers_3__ap[21]), .ZN(n_1_0_405)); + AOI22_X1_LVT i_1_0_426 (.A1(registers_13__ap[21]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[21]), .ZN(n_1_0_404)); + AOI22_X1_LVT i_1_0_425 (.A1(registers_31__ap[21]), .A2(n_1_0_637), .B1( + n_1_0_636), .B2(registers_27__ap[21]), .ZN(n_1_0_403)); + NAND4_X1_LVT i_1_0_424 (.A1(n_1_0_406), .A2(n_1_0_405), .A3(n_1_0_404), + .A4(n_1_0_403), .ZN(n_1_0_402)); + NOR3_X1_LVT i_1_0_423 (.A1(n_1_0_412), .A2(n_1_0_407), .A3(n_1_0_402), + .ZN(n_1_0_401)); + NAND4_X1_LVT i_1_0_422 (.A1(n_1_0_419), .A2(n_1_0_418), .A3(n_1_0_417), + .A4(n_1_0_401), .ZN(RRs2[21])); + AOI22_X1_LVT i_1_0_421 (.A1(registers_17__ap[20]), .A2(n_1_0_629), .B1( + n_1_0_612), .B2(registers_21__ap[20]), .ZN(n_1_0_400)); + AOI222_X1_LVT i_1_0_420 (.A1(registers_13__ap[20]), .A2(n_1_0_631), .B1( + n_1_0_622), .B2(registers_30__ap[20]), .C1(registers_19__ap[20]), .C2( + n_1_0_633), .ZN(n_1_0_399)); + AOI22_X1_LVT i_1_0_419 (.A1(registers_1__ap[20]), .A2(n_1_0_644), .B1( + n_1_0_634), .B2(registers_28__ap[20]), .ZN(n_1_0_398)); + AOI22_X1_LVT i_1_0_418 (.A1(registers_24__ap[20]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[20]), .ZN(n_1_0_397)); + AOI22_X1_LVT i_1_0_417 (.A1(registers_6__ap[20]), .A2(n_1_0_616), .B1( + n_1_0_611), .B2(registers_11__ap[20]), .ZN(n_1_0_396)); + AOI22_X1_LVT i_1_0_416 (.A1(registers_4__ap[20]), .A2(n_1_0_638), .B1( + n_1_0_624), .B2(registers_10__ap[20]), .ZN(n_1_0_395)); + AOI22_X1_LVT i_1_0_415 (.A1(registers_31__ap[20]), .A2(n_1_0_637), .B1( + n_1_0_618), .B2(registers_2__ap[20]), .ZN(n_1_0_394)); + NAND4_X1_LVT i_1_0_414 (.A1(n_1_0_397), .A2(n_1_0_396), .A3(n_1_0_395), + .A4(n_1_0_394), .ZN(n_1_0_393)); + AOI22_X1_LVT i_1_0_413 (.A1(registers_18__ap[20]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[20]), .ZN(n_1_0_392)); + AOI22_X1_LVT i_1_0_412 (.A1(registers_5__ap[20]), .A2(n_1_0_635), .B1( + n_1_0_632), .B2(registers_12__ap[20]), .ZN(n_1_0_391)); + AOI22_X1_LVT i_1_0_411 (.A1(registers_15__ap[20]), .A2(n_1_0_627), .B1( + n_1_0_614), .B2(registers_16__ap[20]), .ZN(n_1_0_390)); + AOI22_X1_LVT i_1_0_410 (.A1(registers_22__ap[20]), .A2(n_1_0_642), .B1( + n_1_0_620), .B2(registers_25__ap[20]), .ZN(n_1_0_389)); + NAND4_X1_LVT i_1_0_409 (.A1(n_1_0_392), .A2(n_1_0_391), .A3(n_1_0_390), + .A4(n_1_0_389), .ZN(n_1_0_388)); + AOI22_X1_LVT i_1_0_408 (.A1(registers_29__ap[20]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[20]), .ZN(n_1_0_387)); + AOI22_X1_LVT i_1_0_407 (.A1(registers_7__ap[20]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[20]), .ZN(n_1_0_386)); + AOI22_X1_LVT i_1_0_406 (.A1(registers_8__ap[20]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[20]), .ZN(n_1_0_385)); + AOI22_X1_LVT i_1_0_405 (.A1(registers_27__ap[20]), .A2(n_1_0_636), .B1( + n_1_0_610), .B2(registers_3__ap[20]), .ZN(n_1_0_384)); + NAND4_X1_LVT i_1_0_404 (.A1(n_1_0_387), .A2(n_1_0_386), .A3(n_1_0_385), + .A4(n_1_0_384), .ZN(n_1_0_383)); + NOR3_X1_LVT i_1_0_403 (.A1(n_1_0_393), .A2(n_1_0_388), .A3(n_1_0_383), + .ZN(n_1_0_382)); + NAND4_X1_LVT i_1_0_402 (.A1(n_1_0_400), .A2(n_1_0_399), .A3(n_1_0_398), + .A4(n_1_0_382), .ZN(RRs2[20])); + AOI22_X1_LVT i_1_0_401 (.A1(registers_17__ap[19]), .A2(n_1_0_629), .B1( + n_1_0_612), .B2(registers_21__ap[19]), .ZN(n_1_0_381)); + AOI222_X1_LVT i_1_0_400 (.A1(registers_13__ap[19]), .A2(n_1_0_631), .B1( + n_1_0_622), .B2(registers_30__ap[19]), .C1(registers_19__ap[19]), .C2( + n_1_0_633), .ZN(n_1_0_380)); + AOI22_X1_LVT i_1_0_399 (.A1(registers_1__ap[19]), .A2(n_1_0_644), .B1( + n_1_0_634), .B2(registers_28__ap[19]), .ZN(n_1_0_379)); + AOI22_X1_LVT i_1_0_398 (.A1(registers_24__ap[19]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[19]), .ZN(n_1_0_378)); + AOI22_X1_LVT i_1_0_397 (.A1(registers_15__ap[19]), .A2(n_1_0_627), .B1( + n_1_0_611), .B2(registers_11__ap[19]), .ZN(n_1_0_377)); + AOI22_X1_LVT i_1_0_396 (.A1(registers_4__ap[19]), .A2(n_1_0_638), .B1( + n_1_0_636), .B2(registers_27__ap[19]), .ZN(n_1_0_376)); + AOI22_X1_LVT i_1_0_395 (.A1(registers_31__ap[19]), .A2(n_1_0_637), .B1( + n_1_0_618), .B2(registers_2__ap[19]), .ZN(n_1_0_375)); + NAND4_X1_LVT i_1_0_394 (.A1(n_1_0_378), .A2(n_1_0_377), .A3(n_1_0_376), + .A4(n_1_0_375), .ZN(n_1_0_374)); + AOI22_X1_LVT i_1_0_393 (.A1(registers_18__ap[19]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[19]), .ZN(n_1_0_373)); + AOI22_X1_LVT i_1_0_392 (.A1(registers_5__ap[19]), .A2(n_1_0_635), .B1( + n_1_0_632), .B2(registers_12__ap[19]), .ZN(n_1_0_372)); + AOI22_X1_LVT i_1_0_391 (.A1(registers_25__ap[19]), .A2(n_1_0_620), .B1( + n_1_0_616), .B2(registers_6__ap[19]), .ZN(n_1_0_371)); + AOI22_X1_LVT i_1_0_390 (.A1(registers_22__ap[19]), .A2(n_1_0_642), .B1( + n_1_0_614), .B2(registers_16__ap[19]), .ZN(n_1_0_370)); + NAND4_X1_LVT i_1_0_389 (.A1(n_1_0_373), .A2(n_1_0_372), .A3(n_1_0_371), + .A4(n_1_0_370), .ZN(n_1_0_369)); + AOI22_X1_LVT i_1_0_388 (.A1(registers_29__ap[19]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[19]), .ZN(n_1_0_368)); + AOI22_X1_LVT i_1_0_387 (.A1(registers_7__ap[19]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[19]), .ZN(n_1_0_367)); + AOI22_X1_LVT i_1_0_386 (.A1(registers_8__ap[19]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[19]), .ZN(n_1_0_366)); + AOI22_X1_LVT i_1_0_385 (.A1(registers_10__ap[19]), .A2(n_1_0_624), .B1( + n_1_0_610), .B2(registers_3__ap[19]), .ZN(n_1_0_365)); + NAND4_X1_LVT i_1_0_384 (.A1(n_1_0_368), .A2(n_1_0_367), .A3(n_1_0_366), + .A4(n_1_0_365), .ZN(n_1_0_364)); + NOR3_X1_LVT i_1_0_383 (.A1(n_1_0_374), .A2(n_1_0_369), .A3(n_1_0_364), + .ZN(n_1_0_363)); + NAND4_X1_LVT i_1_0_382 (.A1(n_1_0_381), .A2(n_1_0_380), .A3(n_1_0_379), + .A4(n_1_0_363), .ZN(RRs2[19])); + AOI22_X1_LVT i_1_0_380 (.A1(registers_4__ap[18]), .A2(n_1_0_638), .B1( + n_1_0_634), .B2(registers_28__ap[18]), .ZN(n_1_0_361)); + AOI22_X1_LVT i_1_0_381 (.A1(registers_8__ap[18]), .A2(n_1_0_626), .B1( + n_1_0_614), .B2(registers_16__ap[18]), .ZN(n_1_0_362)); + AOI22_X1_LVT i_1_0_379 (.A1(registers_14__ap[18]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[18]), .ZN(n_1_0_360)); + AOI22_X1_LVT i_1_0_378 (.A1(registers_25__ap[18]), .A2(n_1_0_620), .B1( + n_1_0_611), .B2(registers_11__ap[18]), .ZN(n_1_0_359)); + NAND3_X1_LVT i_1_0_377 (.A1(n_1_0_362), .A2(n_1_0_360), .A3(n_1_0_359), + .ZN(n_1_0_358)); + AOI221_X1_LVT i_1_0_376 (.A(n_1_0_358), .B1(n_1_0_624), .B2( + registers_10__ap[18]), .C1(registers_6__ap[18]), .C2(n_1_0_616), .ZN( + n_1_0_357)); + AOI222_X1_LVT i_1_0_375 (.A1(registers_1__ap[18]), .A2(n_1_0_644), .B1( + n_1_0_640), .B2(registers_26__ap[18]), .C1(n_1_0_622), .C2( + registers_30__ap[18]), .ZN(n_1_0_356)); + NAND2_X1_LVT i_1_0_374 (.A1(n_1_0_357), .A2(n_1_0_356), .ZN(n_1_0_355)); + AOI221_X1_LVT i_1_0_373 (.A(n_1_0_355), .B1(n_1_0_649), .B2( + registers_29__ap[18]), .C1(registers_2__ap[18]), .C2(n_1_0_618), .ZN( + n_1_0_354)); + AOI22_X1_LVT i_1_0_372 (.A1(registers_18__ap[18]), .A2(n_1_0_646), .B1( + n_1_0_633), .B2(registers_19__ap[18]), .ZN(n_1_0_353)); + AOI22_X1_LVT i_1_0_371 (.A1(registers_12__ap[18]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[18]), .ZN(n_1_0_352)); + AOI22_X1_LVT i_1_0_370 (.A1(registers_22__ap[18]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[18]), .ZN(n_1_0_351)); + NAND3_X1_LVT i_1_0_369 (.A1(n_1_0_353), .A2(n_1_0_352), .A3(n_1_0_351), + .ZN(n_1_0_350)); + AOI221_X1_LVT i_1_0_368 (.A(n_1_0_350), .B1(n_1_0_635), .B2( + registers_5__ap[18]), .C1(registers_20__ap[18]), .C2(n_1_0_613), .ZN( + n_1_0_349)); + AOI22_X1_LVT i_1_0_367 (.A1(registers_15__ap[18]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[18]), .ZN(n_1_0_348)); + AOI22_X1_LVT i_1_0_366 (.A1(registers_23__ap[18]), .A2(n_1_0_615), .B1( + n_1_0_610), .B2(registers_3__ap[18]), .ZN(n_1_0_347)); + AOI22_X1_LVT i_1_0_365 (.A1(registers_13__ap[18]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[18]), .ZN(n_1_0_346)); + NAND3_X1_LVT i_1_0_364 (.A1(n_1_0_348), .A2(n_1_0_347), .A3(n_1_0_346), + .ZN(n_1_0_345)); + AOI221_X1_LVT i_1_0_363 (.A(n_1_0_345), .B1(n_1_0_637), .B2( + registers_31__ap[18]), .C1(registers_27__ap[18]), .C2(n_1_0_636), .ZN( + n_1_0_344)); + NAND4_X1_LVT i_1_0_362 (.A1(n_1_0_361), .A2(n_1_0_354), .A3(n_1_0_349), + .A4(n_1_0_344), .ZN(RRs2[18])); + AOI22_X1_LVT i_1_0_358 (.A1(registers_4__ap[17]), .A2(n_1_0_638), .B1( + n_1_0_634), .B2(registers_28__ap[17]), .ZN(n_1_0_340)); + AOI22_X1_LVT i_1_0_361 (.A1(registers_31__ap[17]), .A2(n_1_0_637), .B1( + n_1_0_616), .B2(registers_6__ap[17]), .ZN(n_1_0_343)); + AOI22_X1_LVT i_1_0_357 (.A1(registers_14__ap[17]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[17]), .ZN(n_1_0_339)); + AOI22_X1_LVT i_1_0_360 (.A1(registers_25__ap[17]), .A2(n_1_0_620), .B1( + n_1_0_611), .B2(registers_11__ap[17]), .ZN(n_1_0_342)); + INV_X1_LVT i_1_0_359 (.A(n_1_0_342), .ZN(n_1_0_341)); + AOI221_X1_LVT i_1_0_356 (.A(n_1_0_341), .B1(n_1_0_614), .B2( + registers_16__ap[17]), .C1(registers_10__ap[17]), .C2(n_1_0_624), .ZN( + n_1_0_338)); + AOI222_X1_LVT i_1_0_355 (.A1(registers_1__ap[17]), .A2(n_1_0_644), .B1( + n_1_0_622), .B2(registers_30__ap[17]), .C1(registers_18__ap[17]), .C2( + n_1_0_646), .ZN(n_1_0_337)); + NAND4_X1_LVT i_1_0_354 (.A1(n_1_0_343), .A2(n_1_0_339), .A3(n_1_0_338), + .A4(n_1_0_337), .ZN(n_1_0_336)); + AOI221_X1_LVT i_1_0_353 (.A(n_1_0_336), .B1(n_1_0_649), .B2( + registers_29__ap[17]), .C1(registers_2__ap[17]), .C2(n_1_0_618), .ZN( + n_1_0_335)); + AOI22_X1_LVT i_1_0_352 (.A1(registers_26__ap[17]), .A2(n_1_0_640), .B1( + n_1_0_633), .B2(registers_19__ap[17]), .ZN(n_1_0_334)); + AOI22_X1_LVT i_1_0_351 (.A1(registers_12__ap[17]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[17]), .ZN(n_1_0_333)); + AOI22_X1_LVT i_1_0_350 (.A1(registers_22__ap[17]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[17]), .ZN(n_1_0_332)); + NAND3_X1_LVT i_1_0_349 (.A1(n_1_0_334), .A2(n_1_0_333), .A3(n_1_0_332), + .ZN(n_1_0_331)); + AOI221_X1_LVT i_1_0_348 (.A(n_1_0_331), .B1(n_1_0_635), .B2( + registers_5__ap[17]), .C1(registers_20__ap[17]), .C2(n_1_0_613), .ZN( + n_1_0_330)); + AOI22_X1_LVT i_1_0_347 (.A1(registers_15__ap[17]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[17]), .ZN(n_1_0_329)); + AOI22_X1_LVT i_1_0_346 (.A1(registers_8__ap[17]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[17]), .ZN(n_1_0_328)); + AOI22_X1_LVT i_1_0_345 (.A1(registers_13__ap[17]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[17]), .ZN(n_1_0_327)); + NAND3_X1_LVT i_1_0_344 (.A1(n_1_0_329), .A2(n_1_0_328), .A3(n_1_0_327), + .ZN(n_1_0_326)); + AOI221_X1_LVT i_1_0_343 (.A(n_1_0_326), .B1(n_1_0_636), .B2( + registers_27__ap[17]), .C1(registers_3__ap[17]), .C2(n_1_0_610), .ZN( + n_1_0_325)); + NAND4_X1_LVT i_1_0_342 (.A1(n_1_0_340), .A2(n_1_0_335), .A3(n_1_0_330), + .A4(n_1_0_325), .ZN(RRs2[17])); + AOI22_X1_LVT i_1_0_341 (.A1(registers_4__ap[16]), .A2(n_1_0_638), .B1( + n_1_0_634), .B2(registers_28__ap[16]), .ZN(n_1_0_324)); + AOI222_X1_LVT i_1_0_340 (.A1(registers_1__ap[16]), .A2(n_1_0_644), .B1( + n_1_0_633), .B2(registers_19__ap[16]), .C1(n_1_0_622), .C2( + registers_30__ap[16]), .ZN(n_1_0_323)); + AOI22_X1_LVT i_1_0_339 (.A1(registers_29__ap[16]), .A2(n_1_0_649), .B1( + n_1_0_618), .B2(registers_2__ap[16]), .ZN(n_1_0_322)); + AOI22_X1_LVT i_1_0_338 (.A1(registers_14__ap[16]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[16]), .ZN(n_1_0_321)); + AOI22_X1_LVT i_1_0_337 (.A1(registers_16__ap[16]), .A2(n_1_0_614), .B1( + n_1_0_611), .B2(registers_11__ap[16]), .ZN(n_1_0_320)); + AOI22_X1_LVT i_1_0_336 (.A1(registers_10__ap[16]), .A2(n_1_0_624), .B1( + n_1_0_620), .B2(registers_25__ap[16]), .ZN(n_1_0_319)); + AOI22_X1_LVT i_1_0_335 (.A1(registers_31__ap[16]), .A2(n_1_0_637), .B1( + n_1_0_616), .B2(registers_6__ap[16]), .ZN(n_1_0_318)); + NAND4_X1_LVT i_1_0_334 (.A1(n_1_0_321), .A2(n_1_0_320), .A3(n_1_0_319), + .A4(n_1_0_318), .ZN(n_1_0_317)); + AOI22_X1_LVT i_1_0_333 (.A1(registers_18__ap[16]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[16]), .ZN(n_1_0_316)); + AOI22_X1_LVT i_1_0_332 (.A1(registers_12__ap[16]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[16]), .ZN(n_1_0_315)); + AOI22_X1_LVT i_1_0_331 (.A1(registers_22__ap[16]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[16]), .ZN(n_1_0_314)); + AOI22_X1_LVT i_1_0_330 (.A1(registers_5__ap[16]), .A2(n_1_0_635), .B1( + n_1_0_613), .B2(registers_20__ap[16]), .ZN(n_1_0_313)); + NAND4_X1_LVT i_1_0_329 (.A1(n_1_0_316), .A2(n_1_0_315), .A3(n_1_0_314), + .A4(n_1_0_313), .ZN(n_1_0_312)); + AOI22_X1_LVT i_1_0_328 (.A1(registers_15__ap[16]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[16]), .ZN(n_1_0_311)); + AOI22_X1_LVT i_1_0_327 (.A1(registers_8__ap[16]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[16]), .ZN(n_1_0_310)); + AOI22_X1_LVT i_1_0_326 (.A1(registers_13__ap[16]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[16]), .ZN(n_1_0_309)); + AOI22_X1_LVT i_1_0_325 (.A1(registers_27__ap[16]), .A2(n_1_0_636), .B1( + n_1_0_610), .B2(registers_3__ap[16]), .ZN(n_1_0_308)); + NAND4_X1_LVT i_1_0_324 (.A1(n_1_0_311), .A2(n_1_0_310), .A3(n_1_0_309), + .A4(n_1_0_308), .ZN(n_1_0_307)); + NOR3_X1_LVT i_1_0_323 (.A1(n_1_0_317), .A2(n_1_0_312), .A3(n_1_0_307), + .ZN(n_1_0_306)); + NAND4_X1_LVT i_1_0_322 (.A1(n_1_0_324), .A2(n_1_0_323), .A3(n_1_0_322), + .A4(n_1_0_306), .ZN(RRs2[16])); + AOI22_X1_LVT i_1_0_320 (.A1(registers_5__ap[15]), .A2(n_1_0_635), .B1( + n_1_0_634), .B2(registers_28__ap[15]), .ZN(n_1_0_304)); + AOI22_X1_LVT i_1_0_321 (.A1(registers_8__ap[15]), .A2(n_1_0_626), .B1( + n_1_0_620), .B2(registers_25__ap[15]), .ZN(n_1_0_305)); + AOI22_X1_LVT i_1_0_319 (.A1(registers_14__ap[15]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[15]), .ZN(n_1_0_303)); + AOI22_X1_LVT i_1_0_318 (.A1(registers_16__ap[15]), .A2(n_1_0_614), .B1( + n_1_0_611), .B2(registers_11__ap[15]), .ZN(n_1_0_302)); + NAND3_X1_LVT i_1_0_317 (.A1(n_1_0_305), .A2(n_1_0_303), .A3(n_1_0_302), + .ZN(n_1_0_301)); + AOI221_X1_LVT i_1_0_316 (.A(n_1_0_301), .B1(n_1_0_616), .B2( + registers_6__ap[15]), .C1(registers_10__ap[15]), .C2(n_1_0_624), .ZN( + n_1_0_300)); + AOI222_X1_LVT i_1_0_315 (.A1(registers_1__ap[15]), .A2(n_1_0_644), .B1( + n_1_0_640), .B2(registers_26__ap[15]), .C1(n_1_0_622), .C2( + registers_30__ap[15]), .ZN(n_1_0_299)); + NAND2_X1_LVT i_1_0_314 (.A1(n_1_0_300), .A2(n_1_0_299), .ZN(n_1_0_298)); + AOI221_X1_LVT i_1_0_313 (.A(n_1_0_298), .B1(n_1_0_649), .B2( + registers_29__ap[15]), .C1(registers_2__ap[15]), .C2(n_1_0_618), .ZN( + n_1_0_297)); + AOI22_X1_LVT i_1_0_312 (.A1(registers_12__ap[15]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[15]), .ZN(n_1_0_296)); + AOI22_X1_LVT i_1_0_311 (.A1(registers_22__ap[15]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[15]), .ZN(n_1_0_295)); + AOI22_X1_LVT i_1_0_310 (.A1(registers_4__ap[15]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[15]), .ZN(n_1_0_294)); + NAND3_X1_LVT i_1_0_309 (.A1(n_1_0_296), .A2(n_1_0_295), .A3(n_1_0_294), + .ZN(n_1_0_293)); + AOI221_X1_LVT i_1_0_308 (.A(n_1_0_293), .B1(n_1_0_633), .B2( + registers_19__ap[15]), .C1(registers_18__ap[15]), .C2(n_1_0_646), .ZN( + n_1_0_292)); + AOI22_X1_LVT i_1_0_307 (.A1(registers_15__ap[15]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[15]), .ZN(n_1_0_291)); + AOI22_X1_LVT i_1_0_306 (.A1(registers_23__ap[15]), .A2(n_1_0_615), .B1( + n_1_0_610), .B2(registers_3__ap[15]), .ZN(n_1_0_290)); + AOI22_X1_LVT i_1_0_305 (.A1(registers_13__ap[15]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[15]), .ZN(n_1_0_289)); + NAND3_X1_LVT i_1_0_304 (.A1(n_1_0_291), .A2(n_1_0_290), .A3(n_1_0_289), + .ZN(n_1_0_288)); + AOI221_X1_LVT i_1_0_303 (.A(n_1_0_288), .B1(n_1_0_636), .B2( + registers_27__ap[15]), .C1(registers_31__ap[15]), .C2(n_1_0_637), .ZN( + n_1_0_287)); + NAND4_X1_LVT i_1_0_302 (.A1(n_1_0_304), .A2(n_1_0_297), .A3(n_1_0_292), + .A4(n_1_0_287), .ZN(RRs2[15])); + AOI22_X1_LVT i_1_0_301 (.A1(registers_28__ap[14]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[14]), .ZN(n_1_0_286)); + AOI222_X1_LVT i_1_0_300 (.A1(registers_18__ap[14]), .A2(n_1_0_646), .B1( + n_1_0_620), .B2(registers_25__ap[14]), .C1(n_1_0_618), .C2( + registers_2__ap[14]), .ZN(n_1_0_285)); + AOI22_X1_LVT i_1_0_299 (.A1(registers_24__ap[14]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[14]), .ZN(n_1_0_284)); + AOI22_X1_LVT i_1_0_298 (.A1(registers_15__ap[14]), .A2(n_1_0_627), .B1( + n_1_0_610), .B2(registers_3__ap[14]), .ZN(n_1_0_283)); + AOI22_X1_LVT i_1_0_297 (.A1(registers_4__ap[14]), .A2(n_1_0_638), .B1( + n_1_0_637), .B2(registers_31__ap[14]), .ZN(n_1_0_282)); + AOI22_X1_LVT i_1_0_296 (.A1(registers_29__ap[14]), .A2(n_1_0_649), .B1( + n_1_0_615), .B2(registers_23__ap[14]), .ZN(n_1_0_281)); + NAND4_X1_LVT i_1_0_295 (.A1(n_1_0_284), .A2(n_1_0_283), .A3(n_1_0_282), + .A4(n_1_0_281), .ZN(n_1_0_280)); + AOI221_X1_LVT i_1_0_294 (.A(n_1_0_280), .B1(n_1_0_644), .B2( + registers_1__ap[14]), .C1(registers_13__ap[14]), .C2(n_1_0_631), .ZN( + n_1_0_279)); + AOI22_X1_LVT i_1_0_293 (.A1(registers_17__ap[14]), .A2(n_1_0_629), .B1( + n_1_0_623), .B2(registers_7__ap[14]), .ZN(n_1_0_278)); + AOI22_X1_LVT i_1_0_292 (.A1(registers_5__ap[14]), .A2(n_1_0_635), .B1( + n_1_0_632), .B2(registers_12__ap[14]), .ZN(n_1_0_277)); + AOI22_X1_LVT i_1_0_291 (.A1(registers_10__ap[14]), .A2(n_1_0_624), .B1( + n_1_0_622), .B2(registers_30__ap[14]), .ZN(n_1_0_276)); + AOI22_X1_LVT i_1_0_290 (.A1(registers_26__ap[14]), .A2(n_1_0_640), .B1( + n_1_0_614), .B2(registers_16__ap[14]), .ZN(n_1_0_275)); + NAND4_X1_LVT i_1_0_289 (.A1(n_1_0_278), .A2(n_1_0_277), .A3(n_1_0_276), + .A4(n_1_0_275), .ZN(n_1_0_274)); + AOI22_X1_LVT i_1_0_288 (.A1(registers_9__ap[14]), .A2(n_1_0_617), .B1( + n_1_0_612), .B2(registers_21__ap[14]), .ZN(n_1_0_273)); + AOI22_X1_LVT i_1_0_287 (.A1(registers_14__ap[14]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[14]), .ZN(n_1_0_272)); + AOI22_X1_LVT i_1_0_286 (.A1(registers_22__ap[14]), .A2(n_1_0_642), .B1( + n_1_0_633), .B2(registers_19__ap[14]), .ZN(n_1_0_271)); + AOI22_X1_LVT i_1_0_285 (.A1(registers_27__ap[14]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[14]), .ZN(n_1_0_270)); + NAND4_X1_LVT i_1_0_284 (.A1(n_1_0_273), .A2(n_1_0_272), .A3(n_1_0_271), + .A4(n_1_0_270), .ZN(n_1_0_269)); + NOR2_X1_LVT i_1_0_283 (.A1(n_1_0_274), .A2(n_1_0_269), .ZN(n_1_0_268)); + NAND4_X1_LVT i_1_0_282 (.A1(n_1_0_286), .A2(n_1_0_285), .A3(n_1_0_279), + .A4(n_1_0_268), .ZN(RRs2[14])); + AOI22_X1_LVT i_1_0_281 (.A1(registers_18__ap[13]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[13]), .ZN(n_1_0_267)); + AOI22_X1_LVT i_1_0_280 (.A1(registers_12__ap[13]), .A2(n_1_0_632), .B1( + n_1_0_629), .B2(registers_17__ap[13]), .ZN(n_1_0_266)); + AOI22_X1_LVT i_1_0_279 (.A1(registers_7__ap[13]), .A2(n_1_0_623), .B1( + n_1_0_614), .B2(registers_16__ap[13]), .ZN(n_1_0_265)); + NAND3_X1_LVT i_1_0_277 (.A1(n_1_0_267), .A2(n_1_0_266), .A3(n_1_0_265), + .ZN(n_1_0_263)); + AOI221_X1_LVT i_1_0_276 (.A(n_1_0_263), .B1(n_1_0_642), .B2( + registers_22__ap[13]), .C1(registers_5__ap[13]), .C2(n_1_0_635), .ZN( + n_1_0_262)); + AOI22_X1_LVT i_1_0_278 (.A1(registers_13__ap[13]), .A2(n_1_0_631), .B1( + n_1_0_612), .B2(registers_21__ap[13]), .ZN(n_1_0_264)); + AOI222_X1_LVT i_1_0_275 (.A1(registers_26__ap[13]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[13]), .C1(n_1_0_620), .C2( + registers_25__ap[13]), .ZN(n_1_0_261)); + AOI22_X1_LVT i_1_0_274 (.A1(registers_28__ap[13]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[13]), .ZN(n_1_0_260)); + NAND3_X1_LVT i_1_0_273 (.A1(n_1_0_264), .A2(n_1_0_261), .A3(n_1_0_260), + .ZN(n_1_0_259)); + AOI22_X1_LVT i_1_0_272 (.A1(registers_1__ap[13]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[13]), .ZN(n_1_0_258)); + AOI22_X1_LVT i_1_0_271 (.A1(registers_19__ap[13]), .A2(n_1_0_633), .B1( + n_1_0_618), .B2(registers_2__ap[13]), .ZN(n_1_0_257)); + AOI22_X1_LVT i_1_0_270 (.A1(registers_14__ap[13]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[13]), .ZN(n_1_0_256)); + AOI22_X1_LVT i_1_0_269 (.A1(registers_27__ap[13]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[13]), .ZN(n_1_0_255)); + NAND4_X1_LVT i_1_0_268 (.A1(n_1_0_258), .A2(n_1_0_257), .A3(n_1_0_256), + .A4(n_1_0_255), .ZN(n_1_0_254)); + AOI22_X1_LVT i_1_0_267 (.A1(registers_24__ap[13]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[13]), .ZN(n_1_0_253)); + AOI22_X1_LVT i_1_0_266 (.A1(registers_4__ap[13]), .A2(n_1_0_638), .B1( + n_1_0_637), .B2(registers_31__ap[13]), .ZN(n_1_0_252)); + AOI22_X1_LVT i_1_0_265 (.A1(registers_29__ap[13]), .A2(n_1_0_649), .B1( + n_1_0_615), .B2(registers_23__ap[13]), .ZN(n_1_0_251)); + AOI22_X1_LVT i_1_0_264 (.A1(registers_15__ap[13]), .A2(n_1_0_627), .B1( + n_1_0_610), .B2(registers_3__ap[13]), .ZN(n_1_0_250)); + NAND4_X1_LVT i_1_0_263 (.A1(n_1_0_253), .A2(n_1_0_252), .A3(n_1_0_251), + .A4(n_1_0_250), .ZN(n_1_0_249)); + NOR3_X1_LVT i_1_0_262 (.A1(n_1_0_259), .A2(n_1_0_254), .A3(n_1_0_249), + .ZN(n_1_0_248)); + NAND2_X1_LVT i_1_0_261 (.A1(n_1_0_262), .A2(n_1_0_248), .ZN(RRs2[13])); + AOI22_X1_LVT i_1_0_260 (.A1(registers_18__ap[12]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[12]), .ZN(n_1_0_247)); + AOI22_X1_LVT i_1_0_259 (.A1(registers_12__ap[12]), .A2(n_1_0_632), .B1( + n_1_0_629), .B2(registers_17__ap[12]), .ZN(n_1_0_246)); + AOI22_X1_LVT i_1_0_258 (.A1(registers_5__ap[12]), .A2(n_1_0_635), .B1( + n_1_0_623), .B2(registers_7__ap[12]), .ZN(n_1_0_245)); + NAND3_X1_LVT i_1_0_256 (.A1(n_1_0_247), .A2(n_1_0_246), .A3(n_1_0_245), + .ZN(n_1_0_243)); + AOI221_X1_LVT i_1_0_255 (.A(n_1_0_243), .B1(n_1_0_642), .B2( + registers_22__ap[12]), .C1(registers_16__ap[12]), .C2(n_1_0_614), .ZN( + n_1_0_242)); + AOI22_X1_LVT i_1_0_257 (.A1(registers_13__ap[12]), .A2(n_1_0_631), .B1( + n_1_0_612), .B2(registers_21__ap[12]), .ZN(n_1_0_244)); + AOI222_X1_LVT i_1_0_254 (.A1(registers_26__ap[12]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[12]), .C1(n_1_0_620), .C2( + registers_25__ap[12]), .ZN(n_1_0_241)); + AOI22_X1_LVT i_1_0_253 (.A1(registers_28__ap[12]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[12]), .ZN(n_1_0_240)); + NAND3_X1_LVT i_1_0_252 (.A1(n_1_0_244), .A2(n_1_0_241), .A3(n_1_0_240), + .ZN(n_1_0_239)); + AOI22_X1_LVT i_1_0_251 (.A1(registers_1__ap[12]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[12]), .ZN(n_1_0_238)); + AOI22_X1_LVT i_1_0_250 (.A1(registers_19__ap[12]), .A2(n_1_0_633), .B1( + n_1_0_618), .B2(registers_2__ap[12]), .ZN(n_1_0_237)); + AOI22_X1_LVT i_1_0_249 (.A1(registers_14__ap[12]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[12]), .ZN(n_1_0_236)); + AOI22_X1_LVT i_1_0_248 (.A1(registers_27__ap[12]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[12]), .ZN(n_1_0_235)); + NAND4_X1_LVT i_1_0_247 (.A1(n_1_0_238), .A2(n_1_0_237), .A3(n_1_0_236), + .A4(n_1_0_235), .ZN(n_1_0_234)); + AOI22_X1_LVT i_1_0_246 (.A1(registers_24__ap[12]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[12]), .ZN(n_1_0_233)); + AOI22_X1_LVT i_1_0_245 (.A1(registers_4__ap[12]), .A2(n_1_0_638), .B1( + n_1_0_637), .B2(registers_31__ap[12]), .ZN(n_1_0_232)); + AOI22_X1_LVT i_1_0_244 (.A1(registers_29__ap[12]), .A2(n_1_0_649), .B1( + n_1_0_615), .B2(registers_23__ap[12]), .ZN(n_1_0_231)); + AOI22_X1_LVT i_1_0_243 (.A1(registers_15__ap[12]), .A2(n_1_0_627), .B1( + n_1_0_610), .B2(registers_3__ap[12]), .ZN(n_1_0_230)); + NAND4_X1_LVT i_1_0_242 (.A1(n_1_0_233), .A2(n_1_0_232), .A3(n_1_0_231), + .A4(n_1_0_230), .ZN(n_1_0_229)); + NOR3_X1_LVT i_1_0_241 (.A1(n_1_0_239), .A2(n_1_0_234), .A3(n_1_0_229), + .ZN(n_1_0_228)); + NAND2_X1_LVT i_1_0_240 (.A1(n_1_0_242), .A2(n_1_0_228), .ZN(RRs2[12])); + AOI22_X1_LVT i_1_0_238 (.A1(registers_29__ap[11]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[11]), .ZN(n_1_0_226)); + AOI22_X1_LVT i_1_0_239 (.A1(registers_27__ap[11]), .A2(n_1_0_636), .B1( + n_1_0_627), .B2(registers_15__ap[11]), .ZN(n_1_0_227)); + AOI22_X1_LVT i_1_0_237 (.A1(registers_1__ap[11]), .A2(n_1_0_644), .B1( + n_1_0_616), .B2(registers_6__ap[11]), .ZN(n_1_0_225)); + AOI22_X1_LVT i_1_0_236 (.A1(registers_5__ap[11]), .A2(n_1_0_635), .B1( + n_1_0_615), .B2(registers_23__ap[11]), .ZN(n_1_0_224)); + NAND3_X1_LVT i_1_0_235 (.A1(n_1_0_227), .A2(n_1_0_225), .A3(n_1_0_224), + .ZN(n_1_0_223)); + AOI221_X1_LVT i_1_0_234 (.A(n_1_0_223), .B1(n_1_0_637), .B2( + registers_31__ap[11]), .C1(registers_16__ap[11]), .C2(n_1_0_614), .ZN( + n_1_0_222)); + AOI222_X1_LVT i_1_0_233 (.A1(registers_8__ap[11]), .A2(n_1_0_626), .B1( + n_1_0_624), .B2(registers_10__ap[11]), .C1(n_1_0_622), .C2( + registers_30__ap[11]), .ZN(n_1_0_221)); + NAND3_X1_LVT i_1_0_232 (.A1(n_1_0_226), .A2(n_1_0_222), .A3(n_1_0_221), + .ZN(n_1_0_220)); + AOI221_X1_LVT i_1_0_231 (.A(n_1_0_220), .B1(n_1_0_638), .B2( + registers_4__ap[11]), .C1(registers_28__ap[11]), .C2(n_1_0_634), .ZN( + n_1_0_219)); + AOI22_X1_LVT i_1_0_230 (.A1(registers_18__ap[11]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[11]), .ZN(n_1_0_218)); + AOI22_X1_LVT i_1_0_229 (.A1(registers_12__ap[11]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[11]), .ZN(n_1_0_217)); + AOI22_X1_LVT i_1_0_228 (.A1(registers_22__ap[11]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[11]), .ZN(n_1_0_216)); + NAND3_X1_LVT i_1_0_227 (.A1(n_1_0_218), .A2(n_1_0_217), .A3(n_1_0_216), + .ZN(n_1_0_215)); + AOI221_X1_LVT i_1_0_226 (.A(n_1_0_215), .B1(n_1_0_613), .B2( + registers_20__ap[11]), .C1(registers_17__ap[11]), .C2(n_1_0_629), .ZN( + n_1_0_214)); + AOI22_X1_LVT i_1_0_225 (.A1(registers_13__ap[11]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[11]), .ZN(n_1_0_213)); + AOI22_X1_LVT i_1_0_224 (.A1(registers_7__ap[11]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[11]), .ZN(n_1_0_212)); + AOI22_X1_LVT i_1_0_223 (.A1(registers_19__ap[11]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[11]), .ZN(n_1_0_211)); + NAND3_X1_LVT i_1_0_222 (.A1(n_1_0_213), .A2(n_1_0_212), .A3(n_1_0_211), + .ZN(n_1_0_210)); + AOI221_X1_LVT i_1_0_221 (.A(n_1_0_210), .B1(n_1_0_611), .B2( + registers_11__ap[11]), .C1(registers_2__ap[11]), .C2(n_1_0_618), .ZN( + n_1_0_209)); + NAND3_X1_LVT i_1_0_220 (.A1(n_1_0_219), .A2(n_1_0_214), .A3(n_1_0_209), + .ZN(RRs2[11])); + AOI22_X1_LVT i_1_0_219 (.A1(registers_28__ap[10]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[10]), .ZN(n_1_0_208)); + AOI222_X1_LVT i_1_0_218 (.A1(registers_26__ap[10]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[10]), .C1(registers_25__ap[10]), .C2( + n_1_0_620), .ZN(n_1_0_207)); + AOI22_X1_LVT i_1_0_217 (.A1(registers_13__ap[10]), .A2(n_1_0_631), .B1( + n_1_0_612), .B2(registers_21__ap[10]), .ZN(n_1_0_206)); + AOI22_X1_LVT i_1_0_216 (.A1(registers_24__ap[10]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[10]), .ZN(n_1_0_205)); + AOI22_X1_LVT i_1_0_215 (.A1(registers_15__ap[10]), .A2(n_1_0_627), .B1( + n_1_0_610), .B2(registers_3__ap[10]), .ZN(n_1_0_204)); + AOI22_X1_LVT i_1_0_214 (.A1(registers_31__ap[10]), .A2(n_1_0_637), .B1( + n_1_0_629), .B2(registers_17__ap[10]), .ZN(n_1_0_203)); + AOI22_X1_LVT i_1_0_213 (.A1(registers_29__ap[10]), .A2(n_1_0_649), .B1( + n_1_0_615), .B2(registers_23__ap[10]), .ZN(n_1_0_202)); + NAND4_X1_LVT i_1_0_212 (.A1(n_1_0_205), .A2(n_1_0_204), .A3(n_1_0_203), + .A4(n_1_0_202), .ZN(n_1_0_201)); + AOI22_X1_LVT i_1_0_211 (.A1(registers_18__ap[10]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[10]), .ZN(n_1_0_200)); + AOI22_X1_LVT i_1_0_210 (.A1(registers_4__ap[10]), .A2(n_1_0_638), .B1( + n_1_0_632), .B2(registers_12__ap[10]), .ZN(n_1_0_199)); + AOI22_X1_LVT i_1_0_209 (.A1(registers_7__ap[10]), .A2(n_1_0_623), .B1( + n_1_0_614), .B2(registers_16__ap[10]), .ZN(n_1_0_198)); + AOI22_X1_LVT i_1_0_208 (.A1(registers_22__ap[10]), .A2(n_1_0_642), .B1( + n_1_0_635), .B2(registers_5__ap[10]), .ZN(n_1_0_197)); + NAND4_X1_LVT i_1_0_207 (.A1(n_1_0_200), .A2(n_1_0_199), .A3(n_1_0_198), + .A4(n_1_0_197), .ZN(n_1_0_196)); + AOI22_X1_LVT i_1_0_206 (.A1(registers_1__ap[10]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[10]), .ZN(n_1_0_195)); + AOI22_X1_LVT i_1_0_205 (.A1(registers_14__ap[10]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[10]), .ZN(n_1_0_194)); + AOI22_X1_LVT i_1_0_204 (.A1(registers_19__ap[10]), .A2(n_1_0_633), .B1( + n_1_0_618), .B2(registers_2__ap[10]), .ZN(n_1_0_193)); + AOI22_X1_LVT i_1_0_203 (.A1(registers_27__ap[10]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[10]), .ZN(n_1_0_192)); + NAND4_X1_LVT i_1_0_202 (.A1(n_1_0_195), .A2(n_1_0_194), .A3(n_1_0_193), + .A4(n_1_0_192), .ZN(n_1_0_191)); + NOR3_X1_LVT i_1_0_201 (.A1(n_1_0_201), .A2(n_1_0_196), .A3(n_1_0_191), + .ZN(n_1_0_190)); + NAND4_X1_LVT i_1_0_200 (.A1(n_1_0_208), .A2(n_1_0_207), .A3(n_1_0_206), + .A4(n_1_0_190), .ZN(RRs2[10])); + AOI22_X1_LVT i_1_0_196 (.A1(registers_13__ap[9]), .A2(n_1_0_631), .B1( + n_1_0_612), .B2(registers_21__ap[9]), .ZN(n_1_0_186)); + AOI22_X1_LVT i_1_0_199 (.A1(registers_29__ap[9]), .A2(n_1_0_649), .B1( + n_1_0_636), .B2(registers_27__ap[9]), .ZN(n_1_0_189)); + AOI22_X1_LVT i_1_0_195 (.A1(registers_24__ap[9]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[9]), .ZN(n_1_0_185)); + AOI22_X1_LVT i_1_0_198 (.A1(registers_31__ap[9]), .A2(n_1_0_637), .B1( + n_1_0_627), .B2(registers_15__ap[9]), .ZN(n_1_0_188)); + INV_X1_LVT i_1_0_197 (.A(n_1_0_188), .ZN(n_1_0_187)); + AOI221_X1_LVT i_1_0_194 (.A(n_1_0_187), .B1(n_1_0_615), .B2( + registers_23__ap[9]), .C1(registers_4__ap[9]), .C2(n_1_0_638), .ZN( + n_1_0_184)); + AOI222_X1_LVT i_1_0_193 (.A1(registers_18__ap[9]), .A2(n_1_0_646), .B1( + n_1_0_624), .B2(registers_10__ap[9]), .C1(registers_25__ap[9]), .C2( + n_1_0_620), .ZN(n_1_0_183)); + NAND4_X1_LVT i_1_0_192 (.A1(n_1_0_189), .A2(n_1_0_185), .A3(n_1_0_184), + .A4(n_1_0_183), .ZN(n_1_0_182)); + AOI221_X1_LVT i_1_0_191 (.A(n_1_0_182), .B1(n_1_0_626), .B2( + registers_8__ap[9]), .C1(registers_28__ap[9]), .C2(n_1_0_634), .ZN( + n_1_0_181)); + AOI22_X1_LVT i_1_0_190 (.A1(registers_26__ap[9]), .A2(n_1_0_640), .B1( + n_1_0_622), .B2(registers_30__ap[9]), .ZN(n_1_0_180)); + AOI22_X1_LVT i_1_0_189 (.A1(registers_12__ap[9]), .A2(n_1_0_632), .B1( + n_1_0_629), .B2(registers_17__ap[9]), .ZN(n_1_0_179)); + AOI22_X1_LVT i_1_0_188 (.A1(registers_5__ap[9]), .A2(n_1_0_635), .B1( + n_1_0_623), .B2(registers_7__ap[9]), .ZN(n_1_0_178)); + NAND3_X1_LVT i_1_0_187 (.A1(n_1_0_180), .A2(n_1_0_179), .A3(n_1_0_178), + .ZN(n_1_0_177)); + AOI221_X1_LVT i_1_0_186 (.A(n_1_0_177), .B1(n_1_0_642), .B2( + registers_22__ap[9]), .C1(registers_16__ap[9]), .C2(n_1_0_614), .ZN( + n_1_0_176)); + AOI22_X1_LVT i_1_0_185 (.A1(registers_1__ap[9]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[9]), .ZN(n_1_0_175)); + AOI22_X1_LVT i_1_0_184 (.A1(registers_14__ap[9]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[9]), .ZN(n_1_0_174)); + AOI22_X1_LVT i_1_0_183 (.A1(registers_19__ap[9]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[9]), .ZN(n_1_0_173)); + NAND3_X1_LVT i_1_0_182 (.A1(n_1_0_175), .A2(n_1_0_174), .A3(n_1_0_173), + .ZN(n_1_0_172)); + AOI221_X1_LVT i_1_0_181 (.A(n_1_0_172), .B1(n_1_0_611), .B2( + registers_11__ap[9]), .C1(registers_2__ap[9]), .C2(n_1_0_618), .ZN( + n_1_0_171)); + NAND4_X1_LVT i_1_0_180 (.A1(n_1_0_186), .A2(n_1_0_181), .A3(n_1_0_176), + .A4(n_1_0_171), .ZN(RRs2[9])); + AOI22_X1_LVT i_1_0_179 (.A1(registers_28__ap[8]), .A2(n_1_0_634), .B1( + n_1_0_629), .B2(registers_17__ap[8]), .ZN(n_1_0_170)); + AOI222_X1_LVT i_1_0_178 (.A1(registers_26__ap[8]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[8]), .C1(n_1_0_626), .C2( + registers_8__ap[8]), .ZN(n_1_0_169)); + AOI22_X1_LVT i_1_0_177 (.A1(registers_29__ap[8]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[8]), .ZN(n_1_0_168)); + AOI22_X1_LVT i_1_0_176 (.A1(registers_1__ap[8]), .A2(n_1_0_644), .B1( + n_1_0_616), .B2(registers_6__ap[8]), .ZN(n_1_0_167)); + AOI22_X1_LVT i_1_0_175 (.A1(registers_5__ap[8]), .A2(n_1_0_635), .B1( + n_1_0_610), .B2(registers_3__ap[8]), .ZN(n_1_0_166)); + AOI22_X1_LVT i_1_0_174 (.A1(registers_31__ap[8]), .A2(n_1_0_637), .B1( + n_1_0_614), .B2(registers_16__ap[8]), .ZN(n_1_0_165)); + AOI22_X1_LVT i_1_0_173 (.A1(registers_15__ap[8]), .A2(n_1_0_627), .B1( + n_1_0_615), .B2(registers_23__ap[8]), .ZN(n_1_0_164)); + NAND4_X1_LVT i_1_0_172 (.A1(n_1_0_167), .A2(n_1_0_166), .A3(n_1_0_165), + .A4(n_1_0_164), .ZN(n_1_0_163)); + AOI22_X1_LVT i_1_0_171 (.A1(registers_18__ap[8]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[8]), .ZN(n_1_0_162)); + AOI22_X1_LVT i_1_0_170 (.A1(registers_4__ap[8]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[8]), .ZN(n_1_0_161)); + AOI22_X1_LVT i_1_0_169 (.A1(registers_22__ap[8]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[8]), .ZN(n_1_0_160)); + AOI22_X1_LVT i_1_0_168 (.A1(registers_12__ap[8]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[8]), .ZN(n_1_0_159)); + NAND4_X1_LVT i_1_0_167 (.A1(n_1_0_162), .A2(n_1_0_161), .A3(n_1_0_160), + .A4(n_1_0_159), .ZN(n_1_0_158)); + AOI22_X1_LVT i_1_0_166 (.A1(registers_13__ap[8]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[8]), .ZN(n_1_0_157)); + AOI22_X1_LVT i_1_0_165 (.A1(registers_7__ap[8]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[8]), .ZN(n_1_0_156)); + AOI22_X1_LVT i_1_0_164 (.A1(registers_19__ap[8]), .A2(n_1_0_633), .B1( + n_1_0_618), .B2(registers_2__ap[8]), .ZN(n_1_0_155)); + AOI22_X1_LVT i_1_0_163 (.A1(registers_27__ap[8]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[8]), .ZN(n_1_0_154)); + NAND4_X1_LVT i_1_0_162 (.A1(n_1_0_157), .A2(n_1_0_156), .A3(n_1_0_155), + .A4(n_1_0_154), .ZN(n_1_0_153)); + NOR3_X1_LVT i_1_0_161 (.A1(n_1_0_163), .A2(n_1_0_158), .A3(n_1_0_153), + .ZN(n_1_0_152)); + NAND4_X1_LVT i_1_0_160 (.A1(n_1_0_170), .A2(n_1_0_169), .A3(n_1_0_168), + .A4(n_1_0_152), .ZN(RRs2[8])); + AOI22_X1_LVT i_1_0_159 (.A1(registers_28__ap[7]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[7]), .ZN(n_1_0_151)); + AOI222_X1_LVT i_1_0_158 (.A1(registers_26__ap[7]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[7]), .C1(registers_25__ap[7]), .C2( + n_1_0_620), .ZN(n_1_0_150)); + AOI22_X1_LVT i_1_0_157 (.A1(registers_24__ap[7]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[7]), .ZN(n_1_0_149)); + AOI22_X1_LVT i_1_0_156 (.A1(registers_15__ap[7]), .A2(n_1_0_627), .B1( + n_1_0_610), .B2(registers_3__ap[7]), .ZN(n_1_0_148)); + AOI22_X1_LVT i_1_0_155 (.A1(registers_31__ap[7]), .A2(n_1_0_637), .B1( + n_1_0_629), .B2(registers_17__ap[7]), .ZN(n_1_0_147)); + AOI22_X1_LVT i_1_0_154 (.A1(registers_29__ap[7]), .A2(n_1_0_649), .B1( + n_1_0_615), .B2(registers_23__ap[7]), .ZN(n_1_0_146)); + NAND4_X1_LVT i_1_0_153 (.A1(n_1_0_149), .A2(n_1_0_148), .A3(n_1_0_147), + .A4(n_1_0_146), .ZN(n_1_0_145)); + AOI221_X1_LVT i_1_0_152 (.A(n_1_0_145), .B1(n_1_0_612), .B2( + registers_21__ap[7]), .C1(registers_13__ap[7]), .C2(n_1_0_631), .ZN( + n_1_0_144)); + AOI22_X1_LVT i_1_0_151 (.A1(registers_18__ap[7]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[7]), .ZN(n_1_0_143)); + AOI22_X1_LVT i_1_0_150 (.A1(registers_4__ap[7]), .A2(n_1_0_638), .B1( + n_1_0_632), .B2(registers_12__ap[7]), .ZN(n_1_0_142)); + AOI22_X1_LVT i_1_0_149 (.A1(registers_5__ap[7]), .A2(n_1_0_635), .B1( + n_1_0_623), .B2(registers_7__ap[7]), .ZN(n_1_0_141)); + AOI22_X1_LVT i_1_0_148 (.A1(registers_22__ap[7]), .A2(n_1_0_642), .B1( + n_1_0_614), .B2(registers_16__ap[7]), .ZN(n_1_0_140)); + NAND4_X1_LVT i_1_0_147 (.A1(n_1_0_143), .A2(n_1_0_142), .A3(n_1_0_141), + .A4(n_1_0_140), .ZN(n_1_0_139)); + AOI22_X1_LVT i_1_0_146 (.A1(registers_1__ap[7]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[7]), .ZN(n_1_0_138)); + AOI22_X1_LVT i_1_0_145 (.A1(registers_14__ap[7]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[7]), .ZN(n_1_0_137)); + AOI22_X1_LVT i_1_0_144 (.A1(registers_19__ap[7]), .A2(n_1_0_633), .B1( + n_1_0_618), .B2(registers_2__ap[7]), .ZN(n_1_0_136)); + AOI22_X1_LVT i_1_0_143 (.A1(registers_27__ap[7]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[7]), .ZN(n_1_0_135)); + NAND4_X1_LVT i_1_0_142 (.A1(n_1_0_138), .A2(n_1_0_137), .A3(n_1_0_136), + .A4(n_1_0_135), .ZN(n_1_0_134)); + NOR2_X1_LVT i_1_0_141 (.A1(n_1_0_139), .A2(n_1_0_134), .ZN(n_1_0_133)); + NAND4_X1_LVT i_1_0_140 (.A1(n_1_0_151), .A2(n_1_0_150), .A3(n_1_0_144), + .A4(n_1_0_133), .ZN(RRs2[7])); + AOI22_X1_LVT i_1_0_136 (.A1(registers_13__ap[6]), .A2(n_1_0_631), .B1( + n_1_0_612), .B2(registers_21__ap[6]), .ZN(n_1_0_129)); + AOI22_X1_LVT i_1_0_139 (.A1(registers_29__ap[6]), .A2(n_1_0_649), .B1( + n_1_0_636), .B2(registers_27__ap[6]), .ZN(n_1_0_132)); + AOI22_X1_LVT i_1_0_135 (.A1(registers_24__ap[6]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[6]), .ZN(n_1_0_128)); + AOI22_X1_LVT i_1_0_138 (.A1(registers_31__ap[6]), .A2(n_1_0_637), .B1( + n_1_0_627), .B2(registers_15__ap[6]), .ZN(n_1_0_131)); + INV_X1_LVT i_1_0_137 (.A(n_1_0_131), .ZN(n_1_0_130)); + AOI221_X1_LVT i_1_0_134 (.A(n_1_0_130), .B1(n_1_0_638), .B2( + registers_4__ap[6]), .C1(registers_23__ap[6]), .C2(n_1_0_615), .ZN( + n_1_0_127)); + AOI222_X1_LVT i_1_0_133 (.A1(registers_18__ap[6]), .A2(n_1_0_646), .B1( + n_1_0_620), .B2(registers_25__ap[6]), .C1(n_1_0_624), .C2( + registers_10__ap[6]), .ZN(n_1_0_126)); + NAND4_X1_LVT i_1_0_132 (.A1(n_1_0_132), .A2(n_1_0_128), .A3(n_1_0_127), + .A4(n_1_0_126), .ZN(n_1_0_125)); + AOI221_X1_LVT i_1_0_131 (.A(n_1_0_125), .B1(n_1_0_626), .B2( + registers_8__ap[6]), .C1(registers_28__ap[6]), .C2(n_1_0_634), .ZN( + n_1_0_124)); + AOI22_X1_LVT i_1_0_130 (.A1(registers_26__ap[6]), .A2(n_1_0_640), .B1( + n_1_0_622), .B2(registers_30__ap[6]), .ZN(n_1_0_123)); + AOI22_X1_LVT i_1_0_129 (.A1(registers_12__ap[6]), .A2(n_1_0_632), .B1( + n_1_0_629), .B2(registers_17__ap[6]), .ZN(n_1_0_122)); + AOI22_X1_LVT i_1_0_128 (.A1(registers_7__ap[6]), .A2(n_1_0_623), .B1( + n_1_0_614), .B2(registers_16__ap[6]), .ZN(n_1_0_121)); + NAND3_X1_LVT i_1_0_127 (.A1(n_1_0_123), .A2(n_1_0_122), .A3(n_1_0_121), + .ZN(n_1_0_120)); + AOI221_X1_LVT i_1_0_126 (.A(n_1_0_120), .B1(n_1_0_642), .B2( + registers_22__ap[6]), .C1(registers_5__ap[6]), .C2(n_1_0_635), .ZN( + n_1_0_119)); + AOI22_X1_LVT i_1_0_125 (.A1(registers_1__ap[6]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[6]), .ZN(n_1_0_118)); + AOI22_X1_LVT i_1_0_124 (.A1(registers_14__ap[6]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[6]), .ZN(n_1_0_117)); + AOI22_X1_LVT i_1_0_123 (.A1(registers_19__ap[6]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[6]), .ZN(n_1_0_116)); + NAND3_X1_LVT i_1_0_122 (.A1(n_1_0_118), .A2(n_1_0_117), .A3(n_1_0_116), + .ZN(n_1_0_115)); + AOI221_X1_LVT i_1_0_121 (.A(n_1_0_115), .B1(n_1_0_618), .B2( + registers_2__ap[6]), .C1(registers_11__ap[6]), .C2(n_1_0_611), .ZN( + n_1_0_114)); + NAND4_X1_LVT i_1_0_120 (.A1(n_1_0_129), .A2(n_1_0_124), .A3(n_1_0_119), + .A4(n_1_0_114), .ZN(RRs2[6])); + AOI22_X1_LVT i_1_0_118 (.A1(registers_28__ap[5]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[5]), .ZN(n_1_0_112)); + AOI22_X1_LVT i_1_0_119 (.A1(registers_31__ap[5]), .A2(n_1_0_637), .B1( + n_1_0_627), .B2(registers_15__ap[5]), .ZN(n_1_0_113)); + AOI22_X1_LVT i_1_0_117 (.A1(registers_24__ap[5]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[5]), .ZN(n_1_0_111)); + AOI22_X1_LVT i_1_0_116 (.A1(registers_17__ap[5]), .A2(n_1_0_629), .B1( + n_1_0_615), .B2(registers_23__ap[5]), .ZN(n_1_0_110)); + NAND3_X1_LVT i_1_0_115 (.A1(n_1_0_113), .A2(n_1_0_111), .A3(n_1_0_110), + .ZN(n_1_0_109)); + AOI221_X1_LVT i_1_0_114 (.A(n_1_0_109), .B1(n_1_0_636), .B2( + registers_27__ap[5]), .C1(registers_29__ap[5]), .C2(n_1_0_649), .ZN( + n_1_0_108)); + AOI222_X1_LVT i_1_0_113 (.A1(registers_10__ap[5]), .A2(n_1_0_624), .B1( + n_1_0_620), .B2(registers_25__ap[5]), .C1(registers_18__ap[5]), .C2( + n_1_0_646), .ZN(n_1_0_107)); + NAND3_X1_LVT i_1_0_112 (.A1(n_1_0_112), .A2(n_1_0_108), .A3(n_1_0_107), + .ZN(n_1_0_106)); + AOI221_X1_LVT i_1_0_111 (.A(n_1_0_106), .B1(n_1_0_612), .B2( + registers_21__ap[5]), .C1(registers_13__ap[5]), .C2(n_1_0_631), .ZN( + n_1_0_105)); + AOI22_X1_LVT i_1_0_110 (.A1(registers_26__ap[5]), .A2(n_1_0_640), .B1( + n_1_0_622), .B2(registers_30__ap[5]), .ZN(n_1_0_104)); + AOI22_X1_LVT i_1_0_109 (.A1(registers_4__ap[5]), .A2(n_1_0_638), .B1( + n_1_0_632), .B2(registers_12__ap[5]), .ZN(n_1_0_103)); + AOI22_X1_LVT i_1_0_108 (.A1(registers_5__ap[5]), .A2(n_1_0_635), .B1( + n_1_0_623), .B2(registers_7__ap[5]), .ZN(n_1_0_102)); + NAND3_X1_LVT i_1_0_107 (.A1(n_1_0_104), .A2(n_1_0_103), .A3(n_1_0_102), + .ZN(n_1_0_101)); + AOI221_X1_LVT i_1_0_106 (.A(n_1_0_101), .B1(n_1_0_642), .B2( + registers_22__ap[5]), .C1(registers_16__ap[5]), .C2(n_1_0_614), .ZN( + n_1_0_100)); + AOI22_X1_LVT i_1_0_105 (.A1(registers_1__ap[5]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[5]), .ZN(n_1_0_99)); + AOI22_X1_LVT i_1_0_104 (.A1(registers_14__ap[5]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[5]), .ZN(n_1_0_98)); + AOI22_X1_LVT i_1_0_103 (.A1(registers_19__ap[5]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[5]), .ZN(n_1_0_97)); + NAND3_X1_LVT i_1_0_102 (.A1(n_1_0_99), .A2(n_1_0_98), .A3(n_1_0_97), .ZN( + n_1_0_96)); + AOI221_X1_LVT i_1_0_101 (.A(n_1_0_96), .B1(n_1_0_611), .B2( + registers_11__ap[5]), .C1(registers_2__ap[5]), .C2(n_1_0_618), .ZN( + n_1_0_95)); + NAND3_X1_LVT i_1_0_100 (.A1(n_1_0_105), .A2(n_1_0_100), .A3(n_1_0_95), + .ZN(RRs2[5])); + AOI22_X1_LVT i_1_0_99 (.A1(registers_4__ap[4]), .A2(n_1_0_638), .B1(n_1_0_634), + .B2(registers_28__ap[4]), .ZN(n_1_0_94)); + AOI222_X1_LVT i_1_0_98 (.A1(registers_8__ap[4]), .A2(n_1_0_626), .B1( + n_1_0_624), .B2(registers_10__ap[4]), .C1(n_1_0_622), .C2( + registers_30__ap[4]), .ZN(n_1_0_93)); + AOI22_X1_LVT i_1_0_97 (.A1(registers_29__ap[4]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[4]), .ZN(n_1_0_92)); + AOI22_X1_LVT i_1_0_96 (.A1(registers_1__ap[4]), .A2(n_1_0_644), .B1(n_1_0_616), + .B2(registers_6__ap[4]), .ZN(n_1_0_91)); + AOI22_X1_LVT i_1_0_95 (.A1(registers_27__ap[4]), .A2(n_1_0_636), .B1( + n_1_0_627), .B2(registers_15__ap[4]), .ZN(n_1_0_90)); + AOI22_X1_LVT i_1_0_94 (.A1(registers_23__ap[4]), .A2(n_1_0_615), .B1( + n_1_0_614), .B2(registers_16__ap[4]), .ZN(n_1_0_89)); + AOI22_X1_LVT i_1_0_93 (.A1(registers_31__ap[4]), .A2(n_1_0_637), .B1( + n_1_0_635), .B2(registers_5__ap[4]), .ZN(n_1_0_88)); + NAND4_X1_LVT i_1_0_92 (.A1(n_1_0_91), .A2(n_1_0_90), .A3(n_1_0_89), .A4( + n_1_0_88), .ZN(n_1_0_87)); + AOI22_X1_LVT i_1_0_91 (.A1(registers_18__ap[4]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[4]), .ZN(n_1_0_86)); + AOI22_X1_LVT i_1_0_90 (.A1(registers_12__ap[4]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[4]), .ZN(n_1_0_85)); + AOI22_X1_LVT i_1_0_89 (.A1(registers_22__ap[4]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[4]), .ZN(n_1_0_84)); + AOI22_X1_LVT i_1_0_88 (.A1(registers_17__ap[4]), .A2(n_1_0_629), .B1( + n_1_0_613), .B2(registers_20__ap[4]), .ZN(n_1_0_83)); + NAND4_X1_LVT i_1_0_87 (.A1(n_1_0_86), .A2(n_1_0_85), .A3(n_1_0_84), .A4( + n_1_0_83), .ZN(n_1_0_82)); + AOI22_X1_LVT i_1_0_86 (.A1(registers_13__ap[4]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[4]), .ZN(n_1_0_81)); + AOI22_X1_LVT i_1_0_85 (.A1(registers_7__ap[4]), .A2(n_1_0_623), .B1(n_1_0_619), + .B2(registers_14__ap[4]), .ZN(n_1_0_80)); + AOI22_X1_LVT i_1_0_84 (.A1(registers_19__ap[4]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[4]), .ZN(n_1_0_79)); + AOI22_X1_LVT i_1_0_83 (.A1(registers_2__ap[4]), .A2(n_1_0_618), .B1(n_1_0_611), + .B2(registers_11__ap[4]), .ZN(n_1_0_78)); + NAND4_X1_LVT i_1_0_82 (.A1(n_1_0_81), .A2(n_1_0_80), .A3(n_1_0_79), .A4( + n_1_0_78), .ZN(n_1_0_77)); + NOR3_X1_LVT i_1_0_81 (.A1(n_1_0_87), .A2(n_1_0_82), .A3(n_1_0_77), .ZN( + n_1_0_76)); + NAND4_X1_LVT i_1_0_80 (.A1(n_1_0_94), .A2(n_1_0_93), .A3(n_1_0_92), .A4( + n_1_0_76), .ZN(RRs2[4])); + AOI22_X1_LVT i_1_0_78 (.A1(registers_29__ap[3]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[3]), .ZN(n_1_0_74)); + AOI22_X1_LVT i_1_0_79 (.A1(registers_27__ap[3]), .A2(n_1_0_636), .B1( + n_1_0_627), .B2(registers_15__ap[3]), .ZN(n_1_0_75)); + AOI22_X1_LVT i_1_0_77 (.A1(registers_1__ap[3]), .A2(n_1_0_644), .B1(n_1_0_616), + .B2(registers_6__ap[3]), .ZN(n_1_0_73)); + AOI22_X1_LVT i_1_0_76 (.A1(registers_5__ap[3]), .A2(n_1_0_635), .B1(n_1_0_611), + .B2(registers_11__ap[3]), .ZN(n_1_0_72)); + NAND3_X1_LVT i_1_0_75 (.A1(n_1_0_75), .A2(n_1_0_73), .A3(n_1_0_72), .ZN( + n_1_0_71)); + AOI221_X1_LVT i_1_0_74 (.A(n_1_0_71), .B1(n_1_0_614), .B2(registers_16__ap[3]), + .C1(registers_31__ap[3]), .C2(n_1_0_637), .ZN(n_1_0_70)); + AOI222_X1_LVT i_1_0_73 (.A1(registers_8__ap[3]), .A2(n_1_0_626), .B1( + n_1_0_624), .B2(registers_10__ap[3]), .C1(n_1_0_622), .C2( + registers_30__ap[3]), .ZN(n_1_0_69)); + NAND3_X1_LVT i_1_0_72 (.A1(n_1_0_74), .A2(n_1_0_70), .A3(n_1_0_69), .ZN( + n_1_0_68)); + AOI221_X1_LVT i_1_0_71 (.A(n_1_0_68), .B1(n_1_0_638), .B2(registers_4__ap[3]), + .C1(registers_28__ap[3]), .C2(n_1_0_634), .ZN(n_1_0_67)); + AOI22_X1_LVT i_1_0_70 (.A1(registers_18__ap[3]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[3]), .ZN(n_1_0_66)); + AOI22_X1_LVT i_1_0_69 (.A1(registers_12__ap[3]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[3]), .ZN(n_1_0_65)); + AOI22_X1_LVT i_1_0_68 (.A1(registers_22__ap[3]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[3]), .ZN(n_1_0_64)); + NAND3_X1_LVT i_1_0_67 (.A1(n_1_0_66), .A2(n_1_0_65), .A3(n_1_0_64), .ZN( + n_1_0_63)); + AOI221_X1_LVT i_1_0_66 (.A(n_1_0_63), .B1(n_1_0_613), .B2(registers_20__ap[3]), + .C1(registers_17__ap[3]), .C2(n_1_0_629), .ZN(n_1_0_62)); + AOI22_X1_LVT i_1_0_65 (.A1(registers_13__ap[3]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[3]), .ZN(n_1_0_61)); + AOI22_X1_LVT i_1_0_64 (.A1(registers_7__ap[3]), .A2(n_1_0_623), .B1(n_1_0_619), + .B2(registers_14__ap[3]), .ZN(n_1_0_60)); + AOI22_X1_LVT i_1_0_63 (.A1(registers_19__ap[3]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[3]), .ZN(n_1_0_59)); + NAND3_X1_LVT i_1_0_62 (.A1(n_1_0_61), .A2(n_1_0_60), .A3(n_1_0_59), .ZN( + n_1_0_58)); + AOI221_X1_LVT i_1_0_61 (.A(n_1_0_58), .B1(n_1_0_618), .B2(registers_2__ap[3]), + .C1(registers_23__ap[3]), .C2(n_1_0_615), .ZN(n_1_0_57)); + NAND3_X1_LVT i_1_0_60 (.A1(n_1_0_67), .A2(n_1_0_62), .A3(n_1_0_57), .ZN( + RRs2[3])); + AOI22_X1_LVT i_1_0_58 (.A1(registers_29__ap[2]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[2]), .ZN(n_1_0_55)); + AOI22_X1_LVT i_1_0_59 (.A1(registers_27__ap[2]), .A2(n_1_0_636), .B1( + n_1_0_627), .B2(registers_15__ap[2]), .ZN(n_1_0_56)); + AOI22_X1_LVT i_1_0_57 (.A1(registers_1__ap[2]), .A2(n_1_0_644), .B1(n_1_0_616), + .B2(registers_6__ap[2]), .ZN(n_1_0_54)); + AOI22_X1_LVT i_1_0_56 (.A1(registers_5__ap[2]), .A2(n_1_0_635), .B1(n_1_0_615), + .B2(registers_23__ap[2]), .ZN(n_1_0_53)); + NAND3_X1_LVT i_1_0_55 (.A1(n_1_0_56), .A2(n_1_0_54), .A3(n_1_0_53), .ZN( + n_1_0_52)); + AOI221_X1_LVT i_1_0_54 (.A(n_1_0_52), .B1(n_1_0_637), .B2(registers_31__ap[2]), + .C1(registers_16__ap[2]), .C2(n_1_0_614), .ZN(n_1_0_51)); + AOI222_X1_LVT i_1_0_53 (.A1(registers_8__ap[2]), .A2(n_1_0_626), .B1( + n_1_0_624), .B2(registers_10__ap[2]), .C1(n_1_0_622), .C2( + registers_30__ap[2]), .ZN(n_1_0_50)); + NAND3_X1_LVT i_1_0_52 (.A1(n_1_0_55), .A2(n_1_0_51), .A3(n_1_0_50), .ZN( + n_1_0_49)); + AOI221_X1_LVT i_1_0_51 (.A(n_1_0_49), .B1(n_1_0_638), .B2(registers_4__ap[2]), + .C1(registers_28__ap[2]), .C2(n_1_0_634), .ZN(n_1_0_48)); + AOI22_X1_LVT i_1_0_50 (.A1(registers_18__ap[2]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[2]), .ZN(n_1_0_47)); + AOI22_X1_LVT i_1_0_49 (.A1(registers_12__ap[2]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[2]), .ZN(n_1_0_46)); + AOI22_X1_LVT i_1_0_48 (.A1(registers_22__ap[2]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[2]), .ZN(n_1_0_45)); + NAND3_X1_LVT i_1_0_47 (.A1(n_1_0_47), .A2(n_1_0_46), .A3(n_1_0_45), .ZN( + n_1_0_44)); + AOI221_X1_LVT i_1_0_46 (.A(n_1_0_44), .B1(n_1_0_629), .B2(registers_17__ap[2]), + .C1(registers_20__ap[2]), .C2(n_1_0_613), .ZN(n_1_0_43)); + AOI22_X1_LVT i_1_0_45 (.A1(registers_13__ap[2]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[2]), .ZN(n_1_0_42)); + AOI22_X1_LVT i_1_0_44 (.A1(registers_7__ap[2]), .A2(n_1_0_623), .B1(n_1_0_619), + .B2(registers_14__ap[2]), .ZN(n_1_0_41)); + AOI22_X1_LVT i_1_0_43 (.A1(registers_19__ap[2]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[2]), .ZN(n_1_0_40)); + NAND3_X1_LVT i_1_0_42 (.A1(n_1_0_42), .A2(n_1_0_41), .A3(n_1_0_40), .ZN( + n_1_0_39)); + AOI221_X1_LVT i_1_0_41 (.A(n_1_0_39), .B1(n_1_0_618), .B2(registers_2__ap[2]), + .C1(registers_11__ap[2]), .C2(n_1_0_611), .ZN(n_1_0_38)); + NAND3_X1_LVT i_1_0_40 (.A1(n_1_0_48), .A2(n_1_0_43), .A3(n_1_0_38), .ZN( + RRs2[2])); + AOI22_X1_LVT i_1_0_38 (.A1(registers_29__ap[1]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[1]), .ZN(n_1_0_36)); + AOI22_X1_LVT i_1_0_39 (.A1(registers_16__ap[1]), .A2(n_1_0_614), .B1( + n_1_0_610), .B2(registers_3__ap[1]), .ZN(n_1_0_37)); + AOI22_X1_LVT i_1_0_37 (.A1(registers_1__ap[1]), .A2(n_1_0_644), .B1(n_1_0_616), + .B2(registers_6__ap[1]), .ZN(n_1_0_35)); + AOI22_X1_LVT i_1_0_36 (.A1(registers_31__ap[1]), .A2(n_1_0_637), .B1( + n_1_0_635), .B2(registers_5__ap[1]), .ZN(n_1_0_34)); + NAND3_X1_LVT i_1_0_35 (.A1(n_1_0_37), .A2(n_1_0_35), .A3(n_1_0_34), .ZN( + n_1_0_33)); + AOI221_X1_LVT i_1_0_34 (.A(n_1_0_33), .B1(n_1_0_627), .B2(registers_15__ap[1]), + .C1(registers_23__ap[1]), .C2(n_1_0_615), .ZN(n_1_0_32)); + AOI222_X1_LVT i_1_0_33 (.A1(registers_26__ap[1]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[1]), .C1(n_1_0_626), .C2( + registers_8__ap[1]), .ZN(n_1_0_31)); + NAND3_X1_LVT i_1_0_32 (.A1(n_1_0_36), .A2(n_1_0_32), .A3(n_1_0_31), .ZN( + n_1_0_30)); + AOI221_X1_LVT i_1_0_31 (.A(n_1_0_30), .B1(n_1_0_629), .B2(registers_17__ap[1]), + .C1(registers_28__ap[1]), .C2(n_1_0_634), .ZN(n_1_0_29)); + AOI22_X1_LVT i_1_0_30 (.A1(registers_18__ap[1]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[1]), .ZN(n_1_0_28)); + AOI22_X1_LVT i_1_0_29 (.A1(registers_4__ap[1]), .A2(n_1_0_638), .B1(n_1_0_613), + .B2(registers_20__ap[1]), .ZN(n_1_0_27)); + AOI22_X1_LVT i_1_0_28 (.A1(registers_22__ap[1]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[1]), .ZN(n_1_0_26)); + NAND3_X1_LVT i_1_0_27 (.A1(n_1_0_28), .A2(n_1_0_27), .A3(n_1_0_26), .ZN( + n_1_0_25)); + AOI221_X1_LVT i_1_0_26 (.A(n_1_0_25), .B1(n_1_0_632), .B2(registers_12__ap[1]), + .C1(registers_24__ap[1]), .C2(n_1_0_621), .ZN(n_1_0_24)); + AOI22_X1_LVT i_1_0_25 (.A1(registers_13__ap[1]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[1]), .ZN(n_1_0_23)); + AOI22_X1_LVT i_1_0_24 (.A1(registers_7__ap[1]), .A2(n_1_0_623), .B1(n_1_0_619), + .B2(registers_14__ap[1]), .ZN(n_1_0_22)); + AOI22_X1_LVT i_1_0_23 (.A1(registers_19__ap[1]), .A2(n_1_0_633), .B1( + n_1_0_618), .B2(registers_2__ap[1]), .ZN(n_1_0_21)); + NAND3_X1_LVT i_1_0_22 (.A1(n_1_0_23), .A2(n_1_0_22), .A3(n_1_0_21), .ZN( + n_1_0_20)); + AOI221_X1_LVT i_1_0_21 (.A(n_1_0_20), .B1(n_1_0_611), .B2(registers_11__ap[1]), + .C1(registers_27__ap[1]), .C2(n_1_0_636), .ZN(n_1_0_19)); + NAND3_X1_LVT i_1_0_20 (.A1(n_1_0_29), .A2(n_1_0_24), .A3(n_1_0_19), .ZN( + RRs2[1])); + AOI22_X1_LVT i_1_0_19 (.A1(registers_4__ap[0]), .A2(n_1_0_638), .B1(n_1_0_634), + .B2(registers_28__ap[0]), .ZN(n_1_0_18)); + AOI222_X1_LVT i_1_0_18 (.A1(registers_8__ap[0]), .A2(n_1_0_626), .B1( + n_1_0_624), .B2(registers_10__ap[0]), .C1(n_1_0_622), .C2( + registers_30__ap[0]), .ZN(n_1_0_17)); + AOI22_X1_LVT i_1_0_17 (.A1(registers_29__ap[0]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[0]), .ZN(n_1_0_16)); + AOI22_X1_LVT i_1_0_16 (.A1(registers_1__ap[0]), .A2(n_1_0_644), .B1(n_1_0_616), + .B2(registers_6__ap[0]), .ZN(n_1_0_15)); + AOI22_X1_LVT i_1_0_15 (.A1(registers_27__ap[0]), .A2(n_1_0_636), .B1( + n_1_0_627), .B2(registers_15__ap[0]), .ZN(n_1_0_14)); + AOI22_X1_LVT i_1_0_14 (.A1(registers_23__ap[0]), .A2(n_1_0_615), .B1( + n_1_0_614), .B2(registers_16__ap[0]), .ZN(n_1_0_13)); + AOI22_X1_LVT i_1_0_13 (.A1(registers_31__ap[0]), .A2(n_1_0_637), .B1( + n_1_0_635), .B2(registers_5__ap[0]), .ZN(n_1_0_12)); + NAND4_X1_LVT i_1_0_12 (.A1(n_1_0_15), .A2(n_1_0_14), .A3(n_1_0_13), .A4( + n_1_0_12), .ZN(n_1_0_11)); + AOI22_X1_LVT i_1_0_11 (.A1(registers_18__ap[0]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[0]), .ZN(n_1_0_10)); + AOI22_X1_LVT i_1_0_10 (.A1(registers_12__ap[0]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[0]), .ZN(n_1_0_9)); + AOI22_X1_LVT i_1_0_9 (.A1(registers_22__ap[0]), .A2(n_1_0_642), .B1(n_1_0_612), + .B2(registers_21__ap[0]), .ZN(n_1_0_8)); + AOI22_X1_LVT i_1_0_8 (.A1(registers_17__ap[0]), .A2(n_1_0_629), .B1(n_1_0_613), + .B2(registers_20__ap[0]), .ZN(n_1_0_7)); + NAND4_X1_LVT i_1_0_7 (.A1(n_1_0_10), .A2(n_1_0_9), .A3(n_1_0_8), .A4(n_1_0_7), + .ZN(n_1_0_6)); + AOI22_X1_LVT i_1_0_6 (.A1(registers_13__ap[0]), .A2(n_1_0_631), .B1(n_1_0_620), + .B2(registers_25__ap[0]), .ZN(n_1_0_5)); + AOI22_X1_LVT i_1_0_5 (.A1(registers_7__ap[0]), .A2(n_1_0_623), .B1(n_1_0_619), + .B2(registers_14__ap[0]), .ZN(n_1_0_4)); + AOI22_X1_LVT i_1_0_4 (.A1(registers_19__ap[0]), .A2(n_1_0_633), .B1(n_1_0_610), + .B2(registers_3__ap[0]), .ZN(n_1_0_3)); + AOI22_X1_LVT i_1_0_3 (.A1(registers_2__ap[0]), .A2(n_1_0_618), .B1(n_1_0_611), + .B2(registers_11__ap[0]), .ZN(n_1_0_2)); + NAND4_X1_LVT i_1_0_2 (.A1(n_1_0_5), .A2(n_1_0_4), .A3(n_1_0_3), .A4(n_1_0_2), + .ZN(n_1_0_1)); + NOR3_X1_LVT i_1_0_1 (.A1(n_1_0_11), .A2(n_1_0_6), .A3(n_1_0_1), .ZN(n_1_0_0)); + NAND4_X1_LVT i_1_0_0 (.A1(n_1_0_18), .A2(n_1_0_17), .A3(n_1_0_16), .A4( + n_1_0_0), .ZN(RRs2[0])); +endmodule + +module MemGen_32_11(chip_en, clock, addr, rd_data, rd_en, wr_en, wr_data); + input chip_en; + input clock; + input [10:0]addr; + output [31:0]rd_data; + input rd_en; + input wr_en; + input [31:0]wr_data; + + wire [1:0]mem_sel; + + INV_X1_LVT i_1_3 (.A(addr[10]), .ZN(mem_sel[0])); + MemGen_16_10 genblk1_0_U_hi (.chip_en(mem_sel[0]), .wr_en(wr_en), .addr({ + addr[9], addr[8], addr[7], addr[6], addr[5], addr[4], addr[3], addr[2], + addr[1], addr[0]}), .wr_data({wr_data[31], wr_data[30], wr_data[29], + wr_data[28], wr_data[27], wr_data[26], wr_data[25], wr_data[24], + wr_data[23], wr_data[22], wr_data[21], wr_data[20], wr_data[19], + wr_data[18], wr_data[17], wr_data[16]}), .clock(clock), .rd_en(rd_en), + .rd_data({n_63, n_62, n_61, n_60, n_59, n_58, n_57, n_56, n_55, n_54, n_53, + n_52, n_51, n_50, n_49, n_48})); + MemGen_16_10 genblk1_1_U_hi (.chip_en(addr[10]), .wr_en(wr_en), .addr({ + addr[9], addr[8], addr[7], addr[6], addr[5], addr[4], addr[3], addr[2], + addr[1], addr[0]}), .wr_data({wr_data[31], wr_data[30], wr_data[29], + wr_data[28], wr_data[27], wr_data[26], wr_data[25], wr_data[24], + wr_data[23], wr_data[22], wr_data[21], wr_data[20], wr_data[19], + wr_data[18], wr_data[17], wr_data[16]}), .clock(clock), .rd_en(rd_en), + .rd_data({n_31, n_30, n_29, n_28, n_27, n_26, n_25, n_24, n_23, n_22, n_21, + n_20, n_19, n_18, n_17, n_16})); + MUX2_X1_LVT i_1_1_31 (.A(n_63), .B(n_31), .S(addr[10]), .Z(rd_data[31])); + MUX2_X1_LVT i_1_1_30 (.A(n_62), .B(n_30), .S(addr[10]), .Z(rd_data[30])); + MUX2_X1_LVT i_1_1_29 (.A(n_61), .B(n_29), .S(addr[10]), .Z(rd_data[29])); + MUX2_X1_LVT i_1_1_28 (.A(n_60), .B(n_28), .S(addr[10]), .Z(rd_data[28])); + MUX2_X1_LVT i_1_1_27 (.A(n_59), .B(n_27), .S(addr[10]), .Z(rd_data[27])); + MUX2_X1_LVT i_1_1_26 (.A(n_58), .B(n_26), .S(addr[10]), .Z(rd_data[26])); + MUX2_X1_LVT i_1_1_25 (.A(n_57), .B(n_25), .S(addr[10]), .Z(rd_data[25])); + MUX2_X1_LVT i_1_1_24 (.A(n_56), .B(n_24), .S(addr[10]), .Z(rd_data[24])); + MUX2_X1_LVT i_1_1_23 (.A(n_55), .B(n_23), .S(addr[10]), .Z(rd_data[23])); + MUX2_X1_LVT i_1_1_22 (.A(n_54), .B(n_22), .S(addr[10]), .Z(rd_data[22])); + MUX2_X1_LVT i_1_1_21 (.A(n_53), .B(n_21), .S(addr[10]), .Z(rd_data[21])); + MUX2_X1_LVT i_1_1_20 (.A(n_52), .B(n_20), .S(addr[10]), .Z(rd_data[20])); + MUX2_X1_LVT i_1_1_19 (.A(n_51), .B(n_19), .S(addr[10]), .Z(rd_data[19])); + MUX2_X1_LVT i_1_1_18 (.A(n_50), .B(n_18), .S(addr[10]), .Z(rd_data[18])); + MUX2_X1_LVT i_1_1_17 (.A(n_49), .B(n_17), .S(addr[10]), .Z(rd_data[17])); + MUX2_X1_LVT i_1_1_16 (.A(n_48), .B(n_16), .S(addr[10]), .Z(rd_data[16])); + MemGen_16_10 genblk1_0_U_lo (.chip_en(mem_sel[0]), .wr_en(wr_en), .addr({ + addr[9], addr[8], addr[7], addr[6], addr[5], addr[4], addr[3], addr[2], + addr[1], addr[0]}), .wr_data({wr_data[15], wr_data[14], wr_data[13], + wr_data[12], wr_data[11], wr_data[10], wr_data[9], wr_data[8], wr_data[7], + wr_data[6], wr_data[5], wr_data[4], wr_data[3], wr_data[2], wr_data[1], + wr_data[0]}), .clock(clock), .rd_en(rd_en), .rd_data({n_47, n_46, n_45, + n_44, n_43, n_42, n_41, n_40, n_39, n_38, n_37, n_36, n_35, n_34, n_33, + n_32})); + MemGen_16_10 genblk1_1_U_lo (.chip_en(addr[10]), .wr_en(wr_en), .addr({ + addr[9], addr[8], addr[7], addr[6], addr[5], addr[4], addr[3], addr[2], + addr[1], addr[0]}), .wr_data({wr_data[15], wr_data[14], wr_data[13], + wr_data[12], wr_data[11], wr_data[10], wr_data[9], wr_data[8], wr_data[7], + wr_data[6], wr_data[5], wr_data[4], wr_data[3], wr_data[2], wr_data[1], + wr_data[0]}), .clock(clock), .rd_en(rd_en), .rd_data({n_15, n_14, n_13, + n_12, n_11, n_10, n_9, n_8, n_7, n_6, n_5, n_4, n_3, n_2, n_1, n_0})); + MUX2_X1_LVT i_1_1_15 (.A(n_47), .B(n_15), .S(addr[10]), .Z(rd_data[15])); + MUX2_X1_LVT i_1_1_14 (.A(n_46), .B(n_14), .S(addr[10]), .Z(rd_data[14])); + MUX2_X1_LVT i_1_1_13 (.A(n_45), .B(n_13), .S(addr[10]), .Z(rd_data[13])); + MUX2_X1_LVT i_1_1_12 (.A(n_44), .B(n_12), .S(addr[10]), .Z(rd_data[12])); + MUX2_X1_LVT i_1_1_11 (.A(n_43), .B(n_11), .S(addr[10]), .Z(rd_data[11])); + MUX2_X1_LVT i_1_1_10 (.A(n_42), .B(n_10), .S(addr[10]), .Z(rd_data[10])); + MUX2_X1_LVT i_1_1_9 (.A(n_41), .B(n_9), .S(addr[10]), .Z(rd_data[9])); + MUX2_X1_LVT i_1_1_8 (.A(n_40), .B(n_8), .S(addr[10]), .Z(rd_data[8])); + MUX2_X1_LVT i_1_1_7 (.A(n_39), .B(n_7), .S(addr[10]), .Z(rd_data[7])); + MUX2_X1_LVT i_1_1_6 (.A(n_38), .B(n_6), .S(addr[10]), .Z(rd_data[6])); + MUX2_X1_LVT i_1_1_5 (.A(n_37), .B(n_5), .S(addr[10]), .Z(rd_data[5])); + MUX2_X1_LVT i_1_1_4 (.A(n_36), .B(n_4), .S(addr[10]), .Z(rd_data[4])); + MUX2_X1_LVT i_1_1_3 (.A(n_35), .B(n_3), .S(addr[10]), .Z(rd_data[3])); + MUX2_X1_LVT i_1_1_2 (.A(n_34), .B(n_2), .S(addr[10]), .Z(rd_data[2])); + MUX2_X1_LVT i_1_1_1 (.A(n_33), .B(n_1), .S(addr[10]), .Z(rd_data[1])); + MUX2_X1_LVT i_1_1_0 (.A(n_32), .B(n_0), .S(addr[10]), .Z(rd_data[0])); +endmodule + +module main_mem(clk, reset, DAddr, IAddr, DWData, DRData, IRData, DWE, DWidth); + input clk; + input reset; + input [31:0]DAddr; + input [31:0]IAddr; + input [31:0]DWData; + output [31:0]DRData; + output [31:0]IRData; + input DWE; + input [1:0]DWidth; + + wire [31:0]mem_rdata; + wire [10:0]mem_addr; + wire n_0_0; + wire n_0_0_0; + wire n_0_1; + wire n_0_0_1; + wire n_0_2; + wire n_0_0_2; + wire n_0_3; + wire n_0_0_3; + wire n_0_4; + wire n_0_0_4; + wire n_0_5; + wire n_0_0_5; + wire n_0_6; + wire n_0_0_6; + wire n_0_7; + wire n_0_0_7; + wire n_0_8; + wire n_0_0_8; + wire n_0_9; + wire n_0_0_9; + wire n_0_10; + wire n_0_0_10; + wire n_0_0_11; + wire n_0_11; + wire n_0_0_12; + wire n_0_0_13; + wire n_0_12; + wire n_0_0_14; + wire n_0_0_15; + wire n_0_13; + wire n_0_0_16; + wire n_0_0_17; + wire n_0_14; + wire n_0_0_18; + wire n_0_0_19; + wire n_0_15; + wire n_0_0_20; + wire n_0_0_21; + wire n_0_16; + wire n_0_0_22; + wire n_0_0_23; + wire n_0_17; + wire n_0_0_24; + wire n_0_0_25; + wire n_0_18; + wire n_0_0_26; + wire n_0_0_27; + wire n_0_0_28; + wire n_0_19; + wire n_0_0_29; + wire n_0_20; + wire n_0_0_30; + wire n_0_21; + wire n_0_0_31; + wire n_0_22; + wire n_0_0_32; + wire n_0_23; + wire n_0_0_33; + wire n_0_24; + wire n_0_0_34; + wire n_0_25; + wire n_0_0_35; + wire n_0_26; + wire n_0_0_36; + wire n_0_0_37; + wire n_0_27; + wire n_0_28; + wire n_0_29; + wire n_0_30; + wire n_0_31; + wire n_0_32; + wire n_0_33; + wire n_0_34; + wire n_0_35; + wire n_0_36; + wire n_0_37; + wire n_0_38; + wire n_0_39; + wire n_0_40; + wire n_0_41; + wire n_0_42; + wire n_0_65; + wire n_0_64; + wire n_0_63; + wire n_0_62; + wire n_0_61; + wire n_0_60; + wire n_0_59; + wire n_0_58; + wire n_0_0_38; + wire n_0_0_39; + wire n_0_57; + wire n_0_0_40; + wire n_0_56; + wire n_0_0_41; + wire n_0_55; + wire n_0_0_42; + wire n_0_54; + wire n_0_0_43; + wire n_0_53; + wire n_0_0_44; + wire n_0_52; + wire n_0_0_45; + wire n_0_51; + wire n_0_0_46; + wire n_0_50; + wire n_0_0_47; + wire n_0_0_48; + wire n_0_0_49; + wire n_0_0_50; + wire n_0_0_51; + wire n_0_49; + wire n_0_0_52; + wire n_0_48; + wire n_0_0_53; + wire n_0_47; + wire n_0_0_54; + wire n_0_46; + wire n_0_0_55; + wire n_0_45; + wire n_0_0_56; + wire n_0_44; + wire n_0_0_57; + wire n_0_66; + wire n_0_0_58; + wire n_0_67; + wire n_0_0_59; + wire n_0_0_60; + wire n_0_0_61; + wire n_0_68; + wire n_0_0_62; + wire n_0_0_63; + wire n_0_69; + wire n_0_0_64; + wire n_0_0_65; + wire n_0_70; + wire n_0_0_66; + wire n_0_0_67; + wire n_0_71; + wire n_0_0_68; + wire n_0_0_69; + wire n_0_72; + wire n_0_0_70; + wire n_0_0_71; + wire n_0_73; + wire n_0_0_72; + wire n_0_0_73; + wire n_0_74; + wire n_0_0_74; + wire n_0_0_75; + wire n_0_75; + wire n_0_0_76; + wire n_0_0_77; + wire n_0_0_78; + wire n_0_0_79; + wire n_0_0_80; + wire n_0_0_81; + wire n_0_0_82; + wire n_0_0_83; + wire n_0_0_84; + wire n_0_0_85; + wire n_0_0_86; + wire n_0_0_87; + wire n_0_0_88; + wire n_0_0_89; + wire n_0_0_90; + wire n_0_0_91; + wire n_0_0_92; + wire n_0_43; + wire n_0_0_93; + wire n_0_0_94; + wire n_0_76; + wire n_0_0_95; + wire [31:0]drTmp; + wire [31:0]mem_wdata; + + INV_X1_LVT i_0_0_171 (.A(DWE), .ZN(n_0)); + NOR2_X1_LVT i_0_0_163 (.A1(n_0), .A2(reset), .ZN(n_0_0_88)); + NOR2_X1_LVT i_0_0_22 (.A1(DWE), .A2(reset), .ZN(n_0_0_11)); + AOI22_X1_LVT i_0_0_21 (.A1(DAddr[12]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[12]), .ZN(n_0_0_10)); + INV_X1_LVT i_0_0_20 (.A(n_0_0_10), .ZN(n_0_10)); + INV_X1_LVT i_0_0_172 (.A(clk), .ZN(n_0_76)); + DFF_X1_LVT \mem_addr_reg[10] (.D(n_0_10), .CK(n_0_76), .Q(mem_addr[10]), + .QN()); + AOI22_X1_LVT i_0_0_19 (.A1(DAddr[11]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[11]), .ZN(n_0_0_9)); + INV_X1_LVT i_0_0_18 (.A(n_0_0_9), .ZN(n_0_9)); + DFF_X1_LVT \mem_addr_reg[9] (.D(n_0_9), .CK(n_0_76), .Q(mem_addr[9]), .QN()); + AOI22_X1_LVT i_0_0_17 (.A1(DAddr[10]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[10]), .ZN(n_0_0_8)); + INV_X1_LVT i_0_0_16 (.A(n_0_0_8), .ZN(n_0_8)); + DFF_X1_LVT \mem_addr_reg[8] (.D(n_0_8), .CK(n_0_76), .Q(mem_addr[8]), .QN()); + AOI22_X1_LVT i_0_0_15 (.A1(DAddr[9]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[9]), .ZN(n_0_0_7)); + INV_X1_LVT i_0_0_14 (.A(n_0_0_7), .ZN(n_0_7)); + DFF_X1_LVT \mem_addr_reg[7] (.D(n_0_7), .CK(n_0_76), .Q(mem_addr[7]), .QN()); + AOI22_X1_LVT i_0_0_13 (.A1(DAddr[8]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[8]), .ZN(n_0_0_6)); + INV_X1_LVT i_0_0_12 (.A(n_0_0_6), .ZN(n_0_6)); + DFF_X1_LVT \mem_addr_reg[6] (.D(n_0_6), .CK(n_0_76), .Q(mem_addr[6]), .QN()); + AOI22_X1_LVT i_0_0_11 (.A1(DAddr[7]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[7]), .ZN(n_0_0_5)); + INV_X1_LVT i_0_0_10 (.A(n_0_0_5), .ZN(n_0_5)); + DFF_X1_LVT \mem_addr_reg[5] (.D(n_0_5), .CK(n_0_76), .Q(mem_addr[5]), .QN()); + AOI22_X1_LVT i_0_0_9 (.A1(DAddr[6]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[6]), .ZN(n_0_0_4)); + INV_X1_LVT i_0_0_8 (.A(n_0_0_4), .ZN(n_0_4)); + DFF_X1_LVT \mem_addr_reg[4] (.D(n_0_4), .CK(n_0_76), .Q(mem_addr[4]), .QN()); + AOI22_X1_LVT i_0_0_7 (.A1(DAddr[5]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[5]), .ZN(n_0_0_3)); + INV_X1_LVT i_0_0_6 (.A(n_0_0_3), .ZN(n_0_3)); + DFF_X1_LVT \mem_addr_reg[3] (.D(n_0_3), .CK(n_0_76), .Q(mem_addr[3]), .QN()); + AOI22_X1_LVT i_0_0_5 (.A1(DAddr[4]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[4]), .ZN(n_0_0_2)); + INV_X1_LVT i_0_0_4 (.A(n_0_0_2), .ZN(n_0_2)); + DFF_X1_LVT \mem_addr_reg[2] (.D(n_0_2), .CK(n_0_76), .Q(mem_addr[2]), .QN()); + AOI22_X1_LVT i_0_0_3 (.A1(DAddr[3]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[3]), .ZN(n_0_0_1)); + INV_X1_LVT i_0_0_2 (.A(n_0_0_1), .ZN(n_0_1)); + DFF_X1_LVT \mem_addr_reg[1] (.D(n_0_1), .CK(n_0_76), .Q(mem_addr[1]), .QN()); + AOI22_X1_LVT i_0_0_1 (.A1(DAddr[2]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[2]), .ZN(n_0_0_0)); + INV_X1_LVT i_0_0_0 (.A(n_0_0_0), .ZN(n_0_0)); + DFF_X1_LVT \mem_addr_reg[0] (.D(n_0_0), .CK(n_0_76), .Q(mem_addr[0]), .QN()); + NOR2_X1_LVT i_0_0_162 (.A1(DWidth[1]), .A2(DAddr[1]), .ZN(n_0_0_87)); + NOR2_X1_LVT i_0_0_158 (.A1(DWidth[0]), .A2(DAddr[0]), .ZN(n_0_0_83)); + AND2_X1_LVT i_0_0_157 (.A1(n_0_0_87), .A2(n_0_0_83), .ZN(n_0_0_82)); + AND2_X1_LVT i_0_0_156 (.A1(n_0_0_88), .A2(n_0_0_82), .ZN(n_0_0_81)); + INV_X1_LVT i_0_0_173 (.A(n_0_0_88), .ZN(n_0_0_95)); + INV_X1_LVT i_0_0_169 (.A(DWidth[1]), .ZN(n_0_0_93)); + NOR3_X1_LVT i_0_0_155 (.A1(n_0_0_95), .A2(DWidth[0]), .A3(n_0_0_93), .ZN( + n_0_0_80)); + AOI22_X1_LVT i_0_0_154 (.A1(DWData[7]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[31]), .ZN(n_0_0_79)); + NAND2_X1_LVT i_0_0_168 (.A1(DWidth[0]), .A2(DWidth[1]), .ZN(n_0_43)); + INV_X1_LVT i_0_0_167 (.A(n_0_43), .ZN(n_0_0_92)); + NOR2_X1_LVT i_0_0_160 (.A1(n_0_0_95), .A2(n_0_0_92), .ZN(n_0_0_85)); + NAND2_X1_LVT i_0_0_161 (.A1(n_0_0_93), .A2(DAddr[1]), .ZN(n_0_0_86)); + NOR2_X1_LVT i_0_0_166 (.A1(DWidth[0]), .A2(DWidth[1]), .ZN(n_0_0_91)); + NAND2_X1_LVT i_0_0_164 (.A1(DAddr[0]), .A2(n_0_0_91), .ZN(n_0_0_89)); + NAND3_X1_LVT i_0_0_159 (.A1(n_0_0_85), .A2(n_0_0_86), .A3(n_0_0_89), .ZN( + n_0_0_84)); + INV_X1_LVT i_0_0_170 (.A(DWidth[0]), .ZN(n_0_0_94)); + NOR2_X1_LVT i_0_0_153 (.A1(n_0_0_94), .A2(DAddr[1]), .ZN(n_0_0_78)); + AND3_X1_LVT i_0_0_152 (.A1(n_0_0_88), .A2(n_0_0_78), .A3(n_0_0_93), .ZN( + n_0_0_77)); + AOI22_X1_LVT i_0_0_151 (.A1(n_0_0_84), .A2(mem_wdata[31]), .B1(DWData[15]), + .B2(n_0_0_77), .ZN(n_0_0_76)); + NAND2_X1_LVT i_0_0_150 (.A1(n_0_0_79), .A2(n_0_0_76), .ZN(n_0_75)); + DFF_X1_LVT \mem_wdata_reg[31] (.D(n_0_75), .CK(n_0_76), .Q(mem_wdata[31]), + .QN()); + AOI22_X1_LVT i_0_0_149 (.A1(DWData[6]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[30]), .ZN(n_0_0_75)); + AOI22_X1_LVT i_0_0_148 (.A1(n_0_0_84), .A2(mem_wdata[30]), .B1(DWData[14]), + .B2(n_0_0_77), .ZN(n_0_0_74)); + NAND2_X1_LVT i_0_0_147 (.A1(n_0_0_75), .A2(n_0_0_74), .ZN(n_0_74)); + DFF_X1_LVT \mem_wdata_reg[30] (.D(n_0_74), .CK(n_0_76), .Q(mem_wdata[30]), + .QN()); + AOI22_X1_LVT i_0_0_146 (.A1(DWData[5]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[29]), .ZN(n_0_0_73)); + AOI22_X1_LVT i_0_0_145 (.A1(n_0_0_84), .A2(mem_wdata[29]), .B1(DWData[13]), + .B2(n_0_0_77), .ZN(n_0_0_72)); + NAND2_X1_LVT i_0_0_144 (.A1(n_0_0_73), .A2(n_0_0_72), .ZN(n_0_73)); + DFF_X1_LVT \mem_wdata_reg[29] (.D(n_0_73), .CK(n_0_76), .Q(mem_wdata[29]), + .QN()); + AOI22_X1_LVT i_0_0_143 (.A1(DWData[4]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[28]), .ZN(n_0_0_71)); + AOI22_X1_LVT i_0_0_142 (.A1(n_0_0_84), .A2(mem_wdata[28]), .B1(DWData[12]), + .B2(n_0_0_77), .ZN(n_0_0_70)); + NAND2_X1_LVT i_0_0_141 (.A1(n_0_0_71), .A2(n_0_0_70), .ZN(n_0_72)); + DFF_X1_LVT \mem_wdata_reg[28] (.D(n_0_72), .CK(n_0_76), .Q(mem_wdata[28]), + .QN()); + AOI22_X1_LVT i_0_0_140 (.A1(DWData[3]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[27]), .ZN(n_0_0_69)); + AOI22_X1_LVT i_0_0_139 (.A1(n_0_0_84), .A2(mem_wdata[27]), .B1(DWData[11]), + .B2(n_0_0_77), .ZN(n_0_0_68)); + NAND2_X1_LVT i_0_0_138 (.A1(n_0_0_69), .A2(n_0_0_68), .ZN(n_0_71)); + DFF_X1_LVT \mem_wdata_reg[27] (.D(n_0_71), .CK(n_0_76), .Q(mem_wdata[27]), + .QN()); + AOI22_X1_LVT i_0_0_137 (.A1(DWData[2]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[26]), .ZN(n_0_0_67)); + AOI22_X1_LVT i_0_0_136 (.A1(n_0_0_84), .A2(mem_wdata[26]), .B1(DWData[10]), + .B2(n_0_0_77), .ZN(n_0_0_66)); + NAND2_X1_LVT i_0_0_135 (.A1(n_0_0_67), .A2(n_0_0_66), .ZN(n_0_70)); + DFF_X1_LVT \mem_wdata_reg[26] (.D(n_0_70), .CK(n_0_76), .Q(mem_wdata[26]), + .QN()); + AOI22_X1_LVT i_0_0_134 (.A1(DWData[1]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[25]), .ZN(n_0_0_65)); + AOI22_X1_LVT i_0_0_133 (.A1(n_0_0_84), .A2(mem_wdata[25]), .B1(DWData[9]), + .B2(n_0_0_77), .ZN(n_0_0_64)); + NAND2_X1_LVT i_0_0_132 (.A1(n_0_0_65), .A2(n_0_0_64), .ZN(n_0_69)); + DFF_X1_LVT \mem_wdata_reg[25] (.D(n_0_69), .CK(n_0_76), .Q(mem_wdata[25]), + .QN()); + AOI22_X1_LVT i_0_0_131 (.A1(DWData[0]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[24]), .ZN(n_0_0_63)); + AOI22_X1_LVT i_0_0_130 (.A1(n_0_0_84), .A2(mem_wdata[24]), .B1(DWData[8]), + .B2(n_0_0_77), .ZN(n_0_0_62)); + NAND2_X1_LVT i_0_0_129 (.A1(n_0_0_63), .A2(n_0_0_62), .ZN(n_0_68)); + DFF_X1_LVT \mem_wdata_reg[24] (.D(n_0_68), .CK(n_0_76), .Q(mem_wdata[24]), + .QN()); + NOR4_X1_LVT i_0_0_127 (.A1(n_0_0_95), .A2(n_0_0_83), .A3(DWidth[1]), .A4( + DAddr[1]), .ZN(n_0_0_60)); + INV_X1_LVT i_0_0_165 (.A(n_0_0_91), .ZN(n_0_0_90)); + OAI211_X1_LVT i_0_0_128 (.A(n_0_0_85), .B(n_0_0_86), .C1(n_0_0_90), .C2( + DAddr[0]), .ZN(n_0_0_61)); + AOI222_X1_LVT i_0_0_126 (.A1(DWData[7]), .A2(n_0_0_60), .B1(mem_wdata[23]), + .B2(n_0_0_61), .C1(DWData[23]), .C2(n_0_0_80), .ZN(n_0_0_59)); + INV_X1_LVT i_0_0_125 (.A(n_0_0_59), .ZN(n_0_67)); + DFF_X1_LVT \mem_wdata_reg[23] (.D(n_0_67), .CK(n_0_76), .Q(mem_wdata[23]), + .QN()); + AOI222_X1_LVT i_0_0_124 (.A1(DWData[6]), .A2(n_0_0_60), .B1(mem_wdata[22]), + .B2(n_0_0_61), .C1(DWData[22]), .C2(n_0_0_80), .ZN(n_0_0_58)); + INV_X1_LVT i_0_0_123 (.A(n_0_0_58), .ZN(n_0_66)); + DFF_X1_LVT \mem_wdata_reg[22] (.D(n_0_66), .CK(n_0_76), .Q(mem_wdata[22]), + .QN()); + AOI222_X1_LVT i_0_0_122 (.A1(DWData[5]), .A2(n_0_0_60), .B1(mem_wdata[21]), + .B2(n_0_0_61), .C1(DWData[21]), .C2(n_0_0_80), .ZN(n_0_0_57)); + INV_X1_LVT i_0_0_121 (.A(n_0_0_57), .ZN(n_0_44)); + DFF_X1_LVT \mem_wdata_reg[21] (.D(n_0_44), .CK(n_0_76), .Q(mem_wdata[21]), + .QN()); + AOI222_X1_LVT i_0_0_120 (.A1(DWData[4]), .A2(n_0_0_60), .B1(mem_wdata[20]), + .B2(n_0_0_61), .C1(DWData[20]), .C2(n_0_0_80), .ZN(n_0_0_56)); + INV_X1_LVT i_0_0_119 (.A(n_0_0_56), .ZN(n_0_45)); + DFF_X1_LVT \mem_wdata_reg[20] (.D(n_0_45), .CK(n_0_76), .Q(mem_wdata[20]), + .QN()); + AOI222_X1_LVT i_0_0_118 (.A1(DWData[3]), .A2(n_0_0_60), .B1(mem_wdata[19]), + .B2(n_0_0_61), .C1(DWData[19]), .C2(n_0_0_80), .ZN(n_0_0_55)); + INV_X1_LVT i_0_0_117 (.A(n_0_0_55), .ZN(n_0_46)); + DFF_X1_LVT \mem_wdata_reg[19] (.D(n_0_46), .CK(n_0_76), .Q(mem_wdata[19]), + .QN()); + AOI222_X1_LVT i_0_0_116 (.A1(DWData[2]), .A2(n_0_0_60), .B1(mem_wdata[18]), + .B2(n_0_0_61), .C1(DWData[18]), .C2(n_0_0_80), .ZN(n_0_0_54)); + INV_X1_LVT i_0_0_115 (.A(n_0_0_54), .ZN(n_0_47)); + DFF_X1_LVT \mem_wdata_reg[18] (.D(n_0_47), .CK(n_0_76), .Q(mem_wdata[18]), + .QN()); + AOI222_X1_LVT i_0_0_114 (.A1(DWData[1]), .A2(n_0_0_60), .B1(mem_wdata[17]), + .B2(n_0_0_61), .C1(DWData[17]), .C2(n_0_0_80), .ZN(n_0_0_53)); + INV_X1_LVT i_0_0_113 (.A(n_0_0_53), .ZN(n_0_48)); + DFF_X1_LVT \mem_wdata_reg[17] (.D(n_0_48), .CK(n_0_76), .Q(mem_wdata[17]), + .QN()); + AOI222_X1_LVT i_0_0_112 (.A1(DWData[0]), .A2(n_0_0_60), .B1(mem_wdata[16]), + .B2(n_0_0_61), .C1(DWData[16]), .C2(n_0_0_80), .ZN(n_0_0_52)); + INV_X1_LVT i_0_0_111 (.A(n_0_0_52), .ZN(n_0_49)); + DFF_X1_LVT \mem_wdata_reg[16] (.D(n_0_49), .CK(n_0_76), .Q(mem_wdata[16]), + .QN()); + NOR4_X1_LVT i_0_0_110 (.A1(n_0_0_95), .A2(n_0_0_87), .A3(n_0_0_92), .A4( + n_0_0_91), .ZN(n_0_0_51)); + NOR3_X1_LVT i_0_0_109 (.A1(n_0_0_86), .A2(DAddr[0]), .A3(DWidth[0]), .ZN( + n_0_0_50)); + AND2_X1_LVT i_0_0_108 (.A1(n_0_0_88), .A2(n_0_0_50), .ZN(n_0_0_49)); + OAI211_X1_LVT i_0_0_107 (.A(n_0_0_85), .B(n_0_0_89), .C1(DAddr[1]), .C2( + DWidth[1]), .ZN(n_0_0_48)); + AOI222_X1_LVT i_0_0_106 (.A1(DWData[15]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[7]), .C1(n_0_0_48), .C2(mem_wdata[15]), .ZN(n_0_0_47)); + INV_X1_LVT i_0_0_105 (.A(n_0_0_47), .ZN(n_0_50)); + DFF_X1_LVT \mem_wdata_reg[15] (.D(n_0_50), .CK(n_0_76), .Q(mem_wdata[15]), + .QN()); + AOI222_X1_LVT i_0_0_104 (.A1(DWData[14]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[6]), .C1(n_0_0_48), .C2(mem_wdata[14]), .ZN(n_0_0_46)); + INV_X1_LVT i_0_0_103 (.A(n_0_0_46), .ZN(n_0_51)); + DFF_X1_LVT \mem_wdata_reg[14] (.D(n_0_51), .CK(n_0_76), .Q(mem_wdata[14]), + .QN()); + AOI222_X1_LVT i_0_0_102 (.A1(DWData[13]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[5]), .C1(n_0_0_48), .C2(mem_wdata[13]), .ZN(n_0_0_45)); + INV_X1_LVT i_0_0_101 (.A(n_0_0_45), .ZN(n_0_52)); + DFF_X1_LVT \mem_wdata_reg[13] (.D(n_0_52), .CK(n_0_76), .Q(mem_wdata[13]), + .QN()); + AOI222_X1_LVT i_0_0_100 (.A1(DWData[12]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[4]), .C1(n_0_0_48), .C2(mem_wdata[12]), .ZN(n_0_0_44)); + INV_X1_LVT i_0_0_99 (.A(n_0_0_44), .ZN(n_0_53)); + DFF_X1_LVT \mem_wdata_reg[12] (.D(n_0_53), .CK(n_0_76), .Q(mem_wdata[12]), + .QN()); + AOI222_X1_LVT i_0_0_98 (.A1(DWData[11]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[3]), .C1(n_0_0_48), .C2(mem_wdata[11]), .ZN(n_0_0_43)); + INV_X1_LVT i_0_0_97 (.A(n_0_0_43), .ZN(n_0_54)); + DFF_X1_LVT \mem_wdata_reg[11] (.D(n_0_54), .CK(n_0_76), .Q(mem_wdata[11]), + .QN()); + AOI222_X1_LVT i_0_0_96 (.A1(DWData[10]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[2]), .C1(n_0_0_48), .C2(mem_wdata[10]), .ZN(n_0_0_42)); + INV_X1_LVT i_0_0_95 (.A(n_0_0_42), .ZN(n_0_55)); + DFF_X1_LVT \mem_wdata_reg[10] (.D(n_0_55), .CK(n_0_76), .Q(mem_wdata[10]), + .QN()); + AOI222_X1_LVT i_0_0_94 (.A1(DWData[9]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[1]), .C1(n_0_0_48), .C2(mem_wdata[9]), .ZN(n_0_0_41)); + INV_X1_LVT i_0_0_93 (.A(n_0_0_41), .ZN(n_0_56)); + DFF_X1_LVT \mem_wdata_reg[9] (.D(n_0_56), .CK(n_0_76), .Q(mem_wdata[9]), + .QN()); + AOI222_X1_LVT i_0_0_92 (.A1(DWData[8]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[0]), .C1(n_0_0_48), .C2(mem_wdata[8]), .ZN(n_0_0_40)); + INV_X1_LVT i_0_0_91 (.A(n_0_0_40), .ZN(n_0_57)); + DFF_X1_LVT \mem_wdata_reg[8] (.D(n_0_57), .CK(n_0_76), .Q(mem_wdata[8]), + .QN()); + AOI21_X1_LVT i_0_0_90 (.A(n_0_0_87), .B1(n_0_0_83), .B2(n_0_0_93), .ZN( + n_0_0_39)); + NAND2_X1_LVT i_0_0_89 (.A1(n_0_0_85), .A2(n_0_0_39), .ZN(n_0_0_38)); + MUX2_X1_LVT i_0_0_88 (.A(DWData[7]), .B(mem_wdata[7]), .S(n_0_0_38), .Z( + n_0_58)); + DFF_X1_LVT \mem_wdata_reg[7] (.D(n_0_58), .CK(n_0_76), .Q(mem_wdata[7]), + .QN()); + MUX2_X1_LVT i_0_0_87 (.A(DWData[6]), .B(mem_wdata[6]), .S(n_0_0_38), .Z( + n_0_59)); + DFF_X1_LVT \mem_wdata_reg[6] (.D(n_0_59), .CK(n_0_76), .Q(mem_wdata[6]), + .QN()); + MUX2_X1_LVT i_0_0_86 (.A(DWData[5]), .B(mem_wdata[5]), .S(n_0_0_38), .Z( + n_0_60)); + DFF_X1_LVT \mem_wdata_reg[5] (.D(n_0_60), .CK(n_0_76), .Q(mem_wdata[5]), + .QN()); + MUX2_X1_LVT i_0_0_85 (.A(DWData[4]), .B(mem_wdata[4]), .S(n_0_0_38), .Z( + n_0_61)); + DFF_X1_LVT \mem_wdata_reg[4] (.D(n_0_61), .CK(n_0_76), .Q(mem_wdata[4]), + .QN()); + MUX2_X1_LVT i_0_0_84 (.A(DWData[3]), .B(mem_wdata[3]), .S(n_0_0_38), .Z( + n_0_62)); + DFF_X1_LVT \mem_wdata_reg[3] (.D(n_0_62), .CK(n_0_76), .Q(mem_wdata[3]), + .QN()); + MUX2_X1_LVT i_0_0_83 (.A(DWData[2]), .B(mem_wdata[2]), .S(n_0_0_38), .Z( + n_0_63)); + DFF_X1_LVT \mem_wdata_reg[2] (.D(n_0_63), .CK(n_0_76), .Q(mem_wdata[2]), + .QN()); + MUX2_X1_LVT i_0_0_82 (.A(DWData[1]), .B(mem_wdata[1]), .S(n_0_0_38), .Z( + n_0_64)); + DFF_X1_LVT \mem_wdata_reg[1] (.D(n_0_64), .CK(n_0_76), .Q(mem_wdata[1]), + .QN()); + MUX2_X1_LVT i_0_0_81 (.A(DWData[0]), .B(mem_wdata[0]), .S(n_0_0_38), .Z( + n_0_65)); + DFF_X1_LVT \mem_wdata_reg[0] (.D(n_0_65), .CK(n_0_76), .Q(mem_wdata[0]), + .QN()); + MemGen_32_11 RAM (.chip_en(), .clock(clk), .addr(mem_addr), .rd_data( + mem_rdata), .rd_en(n_0), .wr_en(DWE), .wr_data(mem_wdata)); + DFF_X1_LVT \drTmp_reg[31] (.D(mem_rdata[31]), .CK(n_0_76), .Q(drTmp[31]), + .QN()); + AND2_X1_LVT i_0_0_80 (.A1(DWidth[1]), .A2(drTmp[31]), .ZN(n_0_42)); + DLH_X1_LVT \DRData[31] (.D(n_0_42), .G(n_0_43), .Q(DRData[31])); + DFF_X1_LVT \drTmp_reg[30] (.D(mem_rdata[30]), .CK(n_0_76), .Q(drTmp[30]), + .QN()); + AND2_X1_LVT i_0_0_79 (.A1(DWidth[1]), .A2(drTmp[30]), .ZN(n_0_41)); + DLH_X1_LVT \DRData[30] (.D(n_0_41), .G(n_0_43), .Q(DRData[30])); + DFF_X1_LVT \drTmp_reg[29] (.D(mem_rdata[29]), .CK(n_0_76), .Q(drTmp[29]), + .QN()); + AND2_X1_LVT i_0_0_78 (.A1(DWidth[1]), .A2(drTmp[29]), .ZN(n_0_40)); + DLH_X1_LVT \DRData[29] (.D(n_0_40), .G(n_0_43), .Q(DRData[29])); + DFF_X1_LVT \drTmp_reg[28] (.D(mem_rdata[28]), .CK(n_0_76), .Q(drTmp[28]), + .QN()); + AND2_X1_LVT i_0_0_77 (.A1(DWidth[1]), .A2(drTmp[28]), .ZN(n_0_39)); + DLH_X1_LVT \DRData[28] (.D(n_0_39), .G(n_0_43), .Q(DRData[28])); + DFF_X1_LVT \drTmp_reg[27] (.D(mem_rdata[27]), .CK(n_0_76), .Q(drTmp[27]), + .QN()); + AND2_X1_LVT i_0_0_76 (.A1(DWidth[1]), .A2(drTmp[27]), .ZN(n_0_38)); + DLH_X1_LVT \DRData[27] (.D(n_0_38), .G(n_0_43), .Q(DRData[27])); + DFF_X1_LVT \drTmp_reg[26] (.D(mem_rdata[26]), .CK(n_0_76), .Q(drTmp[26]), + .QN()); + AND2_X1_LVT i_0_0_75 (.A1(DWidth[1]), .A2(drTmp[26]), .ZN(n_0_37)); + DLH_X1_LVT \DRData[26] (.D(n_0_37), .G(n_0_43), .Q(DRData[26])); + DFF_X1_LVT \drTmp_reg[25] (.D(mem_rdata[25]), .CK(n_0_76), .Q(drTmp[25]), + .QN()); + AND2_X1_LVT i_0_0_74 (.A1(DWidth[1]), .A2(drTmp[25]), .ZN(n_0_36)); + DLH_X1_LVT \DRData[25] (.D(n_0_36), .G(n_0_43), .Q(DRData[25])); + DFF_X1_LVT \drTmp_reg[24] (.D(mem_rdata[24]), .CK(n_0_76), .Q(drTmp[24]), + .QN()); + AND2_X1_LVT i_0_0_73 (.A1(DWidth[1]), .A2(drTmp[24]), .ZN(n_0_35)); + DLH_X1_LVT \DRData[24] (.D(n_0_35), .G(n_0_43), .Q(DRData[24])); + DFF_X1_LVT \drTmp_reg[23] (.D(mem_rdata[23]), .CK(n_0_76), .Q(drTmp[23]), + .QN()); + AND2_X1_LVT i_0_0_72 (.A1(DWidth[1]), .A2(drTmp[23]), .ZN(n_0_34)); + DLH_X1_LVT \DRData[23] (.D(n_0_34), .G(n_0_43), .Q(DRData[23])); + DFF_X1_LVT \drTmp_reg[22] (.D(mem_rdata[22]), .CK(n_0_76), .Q(drTmp[22]), + .QN()); + AND2_X1_LVT i_0_0_71 (.A1(DWidth[1]), .A2(drTmp[22]), .ZN(n_0_33)); + DLH_X1_LVT \DRData[22] (.D(n_0_33), .G(n_0_43), .Q(DRData[22])); + DFF_X1_LVT \drTmp_reg[21] (.D(mem_rdata[21]), .CK(n_0_76), .Q(drTmp[21]), + .QN()); + AND2_X1_LVT i_0_0_70 (.A1(DWidth[1]), .A2(drTmp[21]), .ZN(n_0_32)); + DLH_X1_LVT \DRData[21] (.D(n_0_32), .G(n_0_43), .Q(DRData[21])); + DFF_X1_LVT \drTmp_reg[20] (.D(mem_rdata[20]), .CK(n_0_76), .Q(drTmp[20]), + .QN()); + AND2_X1_LVT i_0_0_69 (.A1(DWidth[1]), .A2(drTmp[20]), .ZN(n_0_31)); + DLH_X1_LVT \DRData[20] (.D(n_0_31), .G(n_0_43), .Q(DRData[20])); + DFF_X1_LVT \drTmp_reg[19] (.D(mem_rdata[19]), .CK(n_0_76), .Q(drTmp[19]), + .QN()); + AND2_X1_LVT i_0_0_68 (.A1(DWidth[1]), .A2(drTmp[19]), .ZN(n_0_30)); + DLH_X1_LVT \DRData[19] (.D(n_0_30), .G(n_0_43), .Q(DRData[19])); + DFF_X1_LVT \drTmp_reg[18] (.D(mem_rdata[18]), .CK(n_0_76), .Q(drTmp[18]), + .QN()); + AND2_X1_LVT i_0_0_67 (.A1(DWidth[1]), .A2(drTmp[18]), .ZN(n_0_29)); + DLH_X1_LVT \DRData[18] (.D(n_0_29), .G(n_0_43), .Q(DRData[18])); + DFF_X1_LVT \drTmp_reg[17] (.D(mem_rdata[17]), .CK(n_0_76), .Q(drTmp[17]), + .QN()); + AND2_X1_LVT i_0_0_66 (.A1(DWidth[1]), .A2(drTmp[17]), .ZN(n_0_28)); + DLH_X1_LVT \DRData[17] (.D(n_0_28), .G(n_0_43), .Q(DRData[17])); + DFF_X1_LVT \drTmp_reg[16] (.D(mem_rdata[16]), .CK(n_0_76), .Q(drTmp[16]), + .QN()); + AND2_X1_LVT i_0_0_65 (.A1(DWidth[1]), .A2(drTmp[16]), .ZN(n_0_27)); + DLH_X1_LVT \DRData[16] (.D(n_0_27), .G(n_0_43), .Q(DRData[16])); + NOR2_X1_LVT i_0_0_64 (.A1(n_0_0_91), .A2(n_0_0_87), .ZN(n_0_0_37)); + DFF_X1_LVT \drTmp_reg[15] (.D(mem_rdata[15]), .CK(n_0_76), .Q(drTmp[15]), + .QN()); + AOI22_X1_LVT i_0_0_63 (.A1(drTmp[31]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[15]), .ZN(n_0_0_36)); + INV_X1_LVT i_0_0_62 (.A(n_0_0_36), .ZN(n_0_26)); + DLH_X1_LVT \DRData[15] (.D(n_0_26), .G(n_0_43), .Q(DRData[15])); + DFF_X1_LVT \drTmp_reg[14] (.D(mem_rdata[14]), .CK(n_0_76), .Q(drTmp[14]), + .QN()); + AOI22_X1_LVT i_0_0_61 (.A1(drTmp[30]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[14]), .ZN(n_0_0_35)); + INV_X1_LVT i_0_0_60 (.A(n_0_0_35), .ZN(n_0_25)); + DLH_X1_LVT \DRData[14] (.D(n_0_25), .G(n_0_43), .Q(DRData[14])); + DFF_X1_LVT \drTmp_reg[13] (.D(mem_rdata[13]), .CK(n_0_76), .Q(drTmp[13]), + .QN()); + AOI22_X1_LVT i_0_0_59 (.A1(drTmp[29]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[13]), .ZN(n_0_0_34)); + INV_X1_LVT i_0_0_58 (.A(n_0_0_34), .ZN(n_0_24)); + DLH_X1_LVT \DRData[13] (.D(n_0_24), .G(n_0_43), .Q(DRData[13])); + DFF_X1_LVT \drTmp_reg[12] (.D(mem_rdata[12]), .CK(n_0_76), .Q(drTmp[12]), + .QN()); + AOI22_X1_LVT i_0_0_57 (.A1(drTmp[28]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[12]), .ZN(n_0_0_33)); + INV_X1_LVT i_0_0_56 (.A(n_0_0_33), .ZN(n_0_23)); + DLH_X1_LVT \DRData[12] (.D(n_0_23), .G(n_0_43), .Q(DRData[12])); + DFF_X1_LVT \drTmp_reg[11] (.D(mem_rdata[11]), .CK(n_0_76), .Q(drTmp[11]), + .QN()); + AOI22_X1_LVT i_0_0_55 (.A1(drTmp[27]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[11]), .ZN(n_0_0_32)); + INV_X1_LVT i_0_0_54 (.A(n_0_0_32), .ZN(n_0_22)); + DLH_X1_LVT \DRData[11] (.D(n_0_22), .G(n_0_43), .Q(DRData[11])); + DFF_X1_LVT \drTmp_reg[10] (.D(mem_rdata[10]), .CK(n_0_76), .Q(drTmp[10]), + .QN()); + AOI22_X1_LVT i_0_0_53 (.A1(drTmp[26]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[10]), .ZN(n_0_0_31)); + INV_X1_LVT i_0_0_52 (.A(n_0_0_31), .ZN(n_0_21)); + DLH_X1_LVT \DRData[10] (.D(n_0_21), .G(n_0_43), .Q(DRData[10])); + DFF_X1_LVT \drTmp_reg[9] (.D(mem_rdata[9]), .CK(n_0_76), .Q(drTmp[9]), .QN()); + AOI22_X1_LVT i_0_0_51 (.A1(drTmp[25]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[9]), .ZN(n_0_0_30)); + INV_X1_LVT i_0_0_50 (.A(n_0_0_30), .ZN(n_0_20)); + DLH_X1_LVT \DRData[9] (.D(n_0_20), .G(n_0_43), .Q(DRData[9])); + DFF_X1_LVT \drTmp_reg[8] (.D(mem_rdata[8]), .CK(n_0_76), .Q(drTmp[8]), .QN()); + AOI22_X1_LVT i_0_0_49 (.A1(drTmp[24]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[8]), .ZN(n_0_0_29)); + INV_X1_LVT i_0_0_48 (.A(n_0_0_29), .ZN(n_0_19)); + DLH_X1_LVT \DRData[8] (.D(n_0_19), .G(n_0_43), .Q(DRData[8])); + AOI22_X1_LVT i_0_0_46 (.A1(drTmp[31]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[15]), .ZN(n_0_0_27)); + AOI211_X1_LVT i_0_0_47 (.A(DAddr[1]), .B(n_0_0_83), .C1(n_0_0_94), .C2( + DWidth[1]), .ZN(n_0_0_28)); + DFF_X1_LVT \drTmp_reg[7] (.D(mem_rdata[7]), .CK(n_0_76), .Q(drTmp[7]), .QN()); + AOI22_X1_LVT i_0_0_45 (.A1(drTmp[23]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[7]), .ZN(n_0_0_26)); + NAND2_X1_LVT i_0_0_44 (.A1(n_0_0_27), .A2(n_0_0_26), .ZN(n_0_18)); + DLH_X1_LVT \DRData[7] (.D(n_0_18), .G(n_0_43), .Q(DRData[7])); + AOI22_X1_LVT i_0_0_43 (.A1(drTmp[30]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[14]), .ZN(n_0_0_25)); + DFF_X1_LVT \drTmp_reg[6] (.D(mem_rdata[6]), .CK(n_0_76), .Q(drTmp[6]), .QN()); + AOI22_X1_LVT i_0_0_42 (.A1(drTmp[22]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[6]), .ZN(n_0_0_24)); + NAND2_X1_LVT i_0_0_41 (.A1(n_0_0_25), .A2(n_0_0_24), .ZN(n_0_17)); + DLH_X1_LVT \DRData[6] (.D(n_0_17), .G(n_0_43), .Q(DRData[6])); + AOI22_X1_LVT i_0_0_40 (.A1(drTmp[29]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[13]), .ZN(n_0_0_23)); + DFF_X1_LVT \drTmp_reg[5] (.D(mem_rdata[5]), .CK(n_0_76), .Q(drTmp[5]), .QN()); + AOI22_X1_LVT i_0_0_39 (.A1(drTmp[21]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[5]), .ZN(n_0_0_22)); + NAND2_X1_LVT i_0_0_38 (.A1(n_0_0_23), .A2(n_0_0_22), .ZN(n_0_16)); + DLH_X1_LVT \DRData[5] (.D(n_0_16), .G(n_0_43), .Q(DRData[5])); + AOI22_X1_LVT i_0_0_37 (.A1(drTmp[28]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[12]), .ZN(n_0_0_21)); + DFF_X1_LVT \drTmp_reg[4] (.D(mem_rdata[4]), .CK(n_0_76), .Q(drTmp[4]), .QN()); + AOI22_X1_LVT i_0_0_36 (.A1(drTmp[20]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[4]), .ZN(n_0_0_20)); + NAND2_X1_LVT i_0_0_35 (.A1(n_0_0_21), .A2(n_0_0_20), .ZN(n_0_15)); + DLH_X1_LVT \DRData[4] (.D(n_0_15), .G(n_0_43), .Q(DRData[4])); + AOI22_X1_LVT i_0_0_34 (.A1(drTmp[27]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[11]), .ZN(n_0_0_19)); + DFF_X1_LVT \drTmp_reg[3] (.D(mem_rdata[3]), .CK(n_0_76), .Q(drTmp[3]), .QN()); + AOI22_X1_LVT i_0_0_33 (.A1(drTmp[19]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[3]), .ZN(n_0_0_18)); + NAND2_X1_LVT i_0_0_32 (.A1(n_0_0_19), .A2(n_0_0_18), .ZN(n_0_14)); + DLH_X1_LVT \DRData[3] (.D(n_0_14), .G(n_0_43), .Q(DRData[3])); + AOI22_X1_LVT i_0_0_31 (.A1(drTmp[26]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[10]), .ZN(n_0_0_17)); + DFF_X1_LVT \drTmp_reg[2] (.D(mem_rdata[2]), .CK(n_0_76), .Q(drTmp[2]), .QN()); + AOI22_X1_LVT i_0_0_30 (.A1(drTmp[18]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[2]), .ZN(n_0_0_16)); + NAND2_X1_LVT i_0_0_29 (.A1(n_0_0_17), .A2(n_0_0_16), .ZN(n_0_13)); + DLH_X1_LVT \DRData[2] (.D(n_0_13), .G(n_0_43), .Q(DRData[2])); + AOI22_X1_LVT i_0_0_28 (.A1(drTmp[25]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[9]), .ZN(n_0_0_15)); + DFF_X1_LVT \drTmp_reg[1] (.D(mem_rdata[1]), .CK(n_0_76), .Q(drTmp[1]), .QN()); + AOI22_X1_LVT i_0_0_27 (.A1(drTmp[17]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[1]), .ZN(n_0_0_14)); + NAND2_X1_LVT i_0_0_26 (.A1(n_0_0_15), .A2(n_0_0_14), .ZN(n_0_12)); + DLH_X1_LVT \DRData[1] (.D(n_0_12), .G(n_0_43), .Q(DRData[1])); + AOI22_X1_LVT i_0_0_25 (.A1(drTmp[24]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[8]), .ZN(n_0_0_13)); + DFF_X1_LVT \drTmp_reg[0] (.D(mem_rdata[0]), .CK(n_0_76), .Q(drTmp[0]), .QN()); + AOI22_X1_LVT i_0_0_24 (.A1(drTmp[16]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[0]), .ZN(n_0_0_12)); + NAND2_X1_LVT i_0_0_23 (.A1(n_0_0_13), .A2(n_0_0_12), .ZN(n_0_11)); + DLH_X1_LVT \DRData[0] (.D(n_0_11), .G(n_0_43), .Q(DRData[0])); + DFF_X1_LVT \IRData_reg[31] (.D(mem_rdata[31]), .CK(clk), .Q(IRData[31]), + .QN()); + DFF_X1_LVT \IRData_reg[30] (.D(mem_rdata[30]), .CK(clk), .Q(IRData[30]), + .QN()); + DFF_X1_LVT \IRData_reg[29] (.D(mem_rdata[29]), .CK(clk), .Q(IRData[29]), + .QN()); + DFF_X1_LVT \IRData_reg[28] (.D(mem_rdata[28]), .CK(clk), .Q(IRData[28]), + .QN()); + DFF_X1_LVT \IRData_reg[27] (.D(mem_rdata[27]), .CK(clk), .Q(IRData[27]), + .QN()); + DFF_X1_LVT \IRData_reg[26] (.D(mem_rdata[26]), .CK(clk), .Q(IRData[26]), + .QN()); + DFF_X1_LVT \IRData_reg[25] (.D(mem_rdata[25]), .CK(clk), .Q(IRData[25]), + .QN()); + DFF_X1_LVT \IRData_reg[24] (.D(mem_rdata[24]), .CK(clk), .Q(IRData[24]), + .QN()); + DFF_X1_LVT \IRData_reg[23] (.D(mem_rdata[23]), .CK(clk), .Q(IRData[23]), + .QN()); + DFF_X1_LVT \IRData_reg[22] (.D(mem_rdata[22]), .CK(clk), .Q(IRData[22]), + .QN()); + DFF_X1_LVT \IRData_reg[21] (.D(mem_rdata[21]), .CK(clk), .Q(IRData[21]), + .QN()); + DFF_X1_LVT \IRData_reg[20] (.D(mem_rdata[20]), .CK(clk), .Q(IRData[20]), + .QN()); + DFF_X1_LVT \IRData_reg[19] (.D(mem_rdata[19]), .CK(clk), .Q(IRData[19]), + .QN()); + DFF_X1_LVT \IRData_reg[18] (.D(mem_rdata[18]), .CK(clk), .Q(IRData[18]), + .QN()); + DFF_X1_LVT \IRData_reg[17] (.D(mem_rdata[17]), .CK(clk), .Q(IRData[17]), + .QN()); + DFF_X1_LVT \IRData_reg[16] (.D(mem_rdata[16]), .CK(clk), .Q(IRData[16]), + .QN()); + DFF_X1_LVT \IRData_reg[15] (.D(mem_rdata[15]), .CK(clk), .Q(IRData[15]), + .QN()); + DFF_X1_LVT \IRData_reg[14] (.D(mem_rdata[14]), .CK(clk), .Q(IRData[14]), + .QN()); + DFF_X1_LVT \IRData_reg[13] (.D(mem_rdata[13]), .CK(clk), .Q(IRData[13]), + .QN()); + DFF_X1_LVT \IRData_reg[12] (.D(mem_rdata[12]), .CK(clk), .Q(IRData[12]), + .QN()); + DFF_X1_LVT \IRData_reg[11] (.D(mem_rdata[11]), .CK(clk), .Q(IRData[11]), + .QN()); + DFF_X1_LVT \IRData_reg[10] (.D(mem_rdata[10]), .CK(clk), .Q(IRData[10]), + .QN()); + DFF_X1_LVT \IRData_reg[9] (.D(mem_rdata[9]), .CK(clk), .Q(IRData[9]), .QN()); + DFF_X1_LVT \IRData_reg[8] (.D(mem_rdata[8]), .CK(clk), .Q(IRData[8]), .QN()); + DFF_X1_LVT \IRData_reg[7] (.D(mem_rdata[7]), .CK(clk), .Q(IRData[7]), .QN()); + DFF_X1_LVT \IRData_reg[6] (.D(mem_rdata[6]), .CK(clk), .Q(IRData[6]), .QN()); + DFF_X1_LVT \IRData_reg[5] (.D(mem_rdata[5]), .CK(clk), .Q(IRData[5]), .QN()); + DFF_X1_LVT \IRData_reg[4] (.D(mem_rdata[4]), .CK(clk), .Q(IRData[4]), .QN()); + DFF_X1_LVT \IRData_reg[3] (.D(mem_rdata[3]), .CK(clk), .Q(IRData[3]), .QN()); + DFF_X1_LVT \IRData_reg[2] (.D(mem_rdata[2]), .CK(clk), .Q(IRData[2]), .QN()); + DFF_X1_LVT \IRData_reg[1] (.D(mem_rdata[1]), .CK(clk), .Q(IRData[1]), .QN()); + DFF_X1_LVT \IRData_reg[0] (.D(mem_rdata[0]), .CK(clk), .Q(IRData[0]), .QN()); +endmodule + +module alu(aluOp, aluNegAr, aluBypass, op1, op2, result, eqFlag); + input [2:0]aluOp; + input aluNegAr; + input aluBypass; + input [31:0]op1; + input [31:0]op2; + output [31:0]result; + output eqFlag; + + wire n_9_0; + wire n_9_1; + wire n_9_2; + wire n_9_3; + wire n_9_4; + wire n_9_5; + wire n_9_6; + wire n_9_7; + wire n_9_8; + wire n_9_9; + wire n_9_10; + wire n_9_11; + wire n_9_12; + wire n_9_13; + wire n_9_14; + wire n_9_15; + wire n_9_16; + wire n_9_17; + wire n_9_18; + wire n_9_19; + wire n_9_20; + wire n_9_21; + wire n_9_22; + wire n_9_23; + wire n_9_24; + wire n_9_25; + wire n_9_26; + wire n_9_27; + wire n_9_28; + wire n_9_29; + wire n_9_30; + wire n_9_31; + wire n_10_0; + wire n_10_1; + wire n_10_2; + wire n_10_3; + wire n_10_4; + wire n_10_5; + wire n_10_6; + wire n_10_7; + wire n_10_8; + wire n_10_9; + wire n_10_10; + wire n_10_11; + wire n_10_12; + wire n_10_13; + wire n_10_14; + wire n_10_15; + wire n_10_16; + wire n_10_17; + wire n_10_18; + wire n_10_19; + wire n_10_20; + wire n_10_21; + wire n_10_22; + wire n_10_23; + wire n_10_24; + wire n_10_25; + wire n_10_26; + wire n_10_27; + wire n_10_28; + wire n_10_29; + wire n_10_30; + wire n_10_31; + wire n_10_32; + wire n_10_33; + wire n_10_34; + wire n_10_35; + wire n_10_36; + wire n_10_37; + wire n_10_38; + wire n_10_39; + wire n_10_40; + wire n_10_41; + wire n_10_42; + wire n_10_43; + wire n_10_44; + wire n_10_45; + wire n_10_46; + wire n_10_47; + wire n_10_48; + wire n_10_49; + wire n_10_50; + wire n_10_51; + wire n_10_52; + wire n_10_53; + wire n_10_54; + wire n_10_55; + wire n_10_56; + wire n_10_57; + wire n_10_58; + wire n_10_59; + wire n_10_60; + wire n_10_61; + wire n_10_62; + wire n_10_63; + wire n_10_64; + wire n_10_65; + wire n_10_66; + wire n_10_67; + wire n_10_68; + wire n_10_69; + wire n_10_70; + wire n_10_71; + wire n_10_72; + wire n_10_73; + wire n_10_74; + wire n_10_75; + wire n_10_76; + wire n_10_77; + wire n_10_78; + wire n_10_79; + wire n_10_80; + wire n_10_81; + wire n_10_82; + wire n_10_83; + wire n_10_84; + wire n_10_85; + wire n_10_86; + wire n_10_87; + wire n_10_88; + wire n_10_89; + wire n_10_90; + wire n_10_91; + wire n_10_92; + wire n_10_93; + wire n_10_94; + wire n_10_95; + wire n_10_96; + wire n_10_97; + wire n_10_98; + wire n_10_99; + wire n_10_100; + wire n_10_101; + wire n_10_102; + wire n_10_103; + wire n_10_104; + wire n_10_105; + wire n_10_106; + wire n_10_107; + wire n_10_108; + wire n_10_109; + wire n_10_110; + wire n_10_111; + wire n_10_112; + wire n_10_113; + wire n_10_114; + wire n_10_115; + wire n_10_116; + wire n_10_117; + wire n_10_118; + wire n_10_119; + wire n_10_120; + wire n_10_121; + wire n_10_122; + wire n_10_123; + wire n_0_0; + wire n_0_1; + wire n_0_2; + wire n_0_3; + wire n_0_4; + wire n_0_5; + wire n_0_6; + wire n_0_7; + wire n_0_8; + wire n_0_9; + wire n_0_10; + wire n_0_11; + wire n_0_12; + wire n_0_13; + wire n_0_14; + wire n_0_15; + wire n_0_16; + wire n_0_17; + wire n_0_18; + wire n_0_19; + wire n_0_20; + wire n_0_21; + wire n_0_22; + wire n_0_23; + wire n_0_24; + wire n_0_25; + wire n_0_26; + wire n_0_27; + wire n_0_28; + wire n_0_29; + wire n_0_30; + wire n_0_31; + wire n_0_32; + wire n_0_33; + wire n_0_34; + wire n_0_35; + wire n_0_36; + wire n_0_37; + wire n_0_38; + wire n_0_39; + wire n_0_40; + wire n_0_41; + wire n_0_42; + wire n_0_43; + wire n_0_44; + wire n_0_45; + wire n_0_46; + wire n_0_47; + wire n_0_48; + wire n_0_49; + wire n_0_50; + wire n_0_51; + wire n_0_52; + wire n_0_53; + wire n_0_54; + wire n_0_55; + wire n_0_56; + wire n_0_57; + wire n_0_58; + wire n_0_59; + wire n_0_60; + wire n_0_61; + wire n_0_62; + wire n_0_63; + wire n_0_64; + wire n_0_65; + wire n_0_66; + wire n_0_67; + wire n_0_68; + wire n_0_69; + wire n_0_70; + wire n_0_71; + wire n_0_72; + wire n_0_73; + wire n_0_74; + wire n_0_75; + wire n_0_76; + wire n_0_77; + wire n_0_78; + wire n_0_79; + wire n_0_80; + wire n_0_81; + wire n_0_82; + wire n_0_83; + wire n_0_84; + wire n_0_85; + wire n_0_86; + wire n_0_87; + wire n_0_88; + wire n_0_89; + wire n_0_90; + wire n_0_91; + wire n_0_92; + wire n_0_93; + wire n_0_94; + wire n_0_95; + wire n_0_96; + wire n_0_97; + wire n_0_98; + wire n_0_99; + wire n_0_100; + wire n_0_101; + wire n_0_102; + wire n_0_103; + wire n_0_104; + wire n_0_105; + wire n_0_106; + wire n_0_107; + wire n_0_108; + wire n_0_109; + wire n_0_110; + wire n_0_111; + wire n_0_112; + wire n_0_113; + wire n_0_114; + wire n_0_115; + wire n_0_116; + wire n_0_117; + wire n_0_118; + wire n_0_119; + wire n_0_120; + wire n_0_121; + wire n_0_122; + wire n_0_123; + wire n_0_124; + wire n_0_125; + wire n_0_126; + wire n_0_127; + wire n_0_128; + wire n_0_129; + wire n_0_130; + wire n_0_131; + wire n_0_132; + wire n_0_133; + wire n_0_134; + wire n_0_135; + wire n_0_136; + wire n_0_137; + wire n_0_138; + wire n_0_139; + wire n_0_140; + wire n_0_141; + wire n_0_142; + wire n_0_143; + wire n_0_144; + wire n_0_145; + wire n_0_146; + wire n_0_147; + wire n_0_148; + wire n_0_149; + wire n_0_150; + wire n_0_151; + wire n_0_152; + wire n_0_153; + wire n_0_154; + wire n_0_155; + wire n_0_156; + wire n_0_157; + wire n_0_158; + wire n_0_159; + wire n_0_160; + wire n_0_161; + wire n_0_162; + wire n_0_163; + wire n_0_164; + wire n_0_165; + wire n_0_166; + wire n_0_167; + wire n_0_168; + wire n_0_169; + wire n_0_170; + wire n_0_171; + wire n_0_172; + wire n_0_173; + wire n_0_174; + wire n_0_175; + wire n_0_176; + wire n_0_177; + wire n_0_178; + wire n_0_179; + wire n_0_180; + wire n_0_181; + wire n_0_182; + wire n_0_183; + wire n_0_184; + wire n_0_185; + wire n_0_186; + wire n_0_187; + wire n_0_188; + wire n_0_189; + wire n_0_190; + wire n_0_191; + wire n_0_192; + wire n_0_193; + wire n_0_194; + wire n_0_195; + wire n_0_196; + wire n_0_197; + wire n_0_198; + wire n_0_199; + wire n_0_200; + wire n_0_201; + wire n_0_202; + wire n_0_203; + wire n_0_204; + wire n_0_205; + wire n_0_206; + wire n_0_207; + wire n_0_208; + wire n_0_209; + wire n_0_210; + wire n_0_211; + wire n_0_212; + wire n_0_213; + wire n_0_214; + wire n_0_215; + wire n_0_216; + wire n_0_217; + wire n_0_218; + wire n_0_219; + wire n_0_220; + wire n_0_221; + wire n_0_222; + wire n_0_223; + wire n_0_224; + wire n_0_225; + wire n_0_226; + wire n_0_227; + wire n_0_228; + wire n_0_229; + wire n_0_230; + wire n_0_231; + wire n_0_232; + wire n_0_233; + wire n_0_234; + wire n_0_235; + wire n_0_236; + wire n_0_237; + wire n_0_238; + wire n_0_239; + wire n_0_240; + wire n_0_241; + wire n_0_242; + wire n_0_243; + wire n_0_244; + wire n_0_245; + wire n_0_246; + wire n_0_247; + wire n_0_248; + wire n_0_249; + wire n_0_250; + wire n_0_251; + wire n_0_252; + wire n_0_253; + wire n_0_254; + wire n_0_255; + wire n_0_256; + wire n_0_257; + wire n_0_258; + wire n_0_259; + wire n_0_260; + wire n_0_261; + wire n_0_262; + wire n_0_263; + wire n_0_264; + wire n_0_265; + wire n_0_266; + wire n_0_267; + wire n_0_268; + wire n_0_269; + wire n_0_270; + wire n_0_271; + wire n_0_272; + wire n_0_273; + wire n_0_274; + wire n_0_275; + wire n_0_276; + wire n_0_277; + wire n_0_278; + wire n_0_279; + wire n_0_280; + wire n_0_281; + wire n_0_282; + wire n_0_283; + wire n_0_284; + wire n_0_285; + wire n_0_286; + wire n_0_287; + wire n_0_288; + wire n_0_289; + wire n_0_290; + wire n_0_291; + wire n_0_292; + wire n_0_293; + wire n_0_294; + wire n_0_295; + wire n_0_296; + wire n_0_297; + wire n_0_298; + wire n_0_299; + wire n_0_300; + wire n_0_301; + wire n_0_302; + wire n_0_303; + wire n_0_304; + wire n_0_305; + wire n_0_306; + wire n_0_307; + wire n_0_308; + wire n_0_309; + wire n_0_310; + wire n_0_311; + wire n_0_312; + wire n_0_313; + wire n_0_314; + wire n_0_315; + wire n_0_316; + wire n_0_317; + wire n_0_318; + wire n_0_319; + wire n_0_320; + wire n_0_321; + wire n_0_322; + wire n_0_323; + wire n_0_324; + wire n_0_325; + wire n_0_326; + wire n_0_327; + wire n_0_328; + wire n_0_329; + wire n_0_330; + wire n_0_331; + wire n_0_332; + wire n_0_333; + wire n_0_334; + wire n_0_335; + wire n_0_336; + wire n_0_337; + wire n_0_338; + wire n_0_339; + wire n_0_340; + wire n_0_341; + wire n_0_342; + wire n_0_343; + wire n_0_344; + wire n_0_345; + wire n_0_346; + wire n_0_347; + wire n_0_348; + wire n_0_349; + wire n_0_350; + wire n_0_351; + wire n_0_352; + wire n_0_353; + wire n_0_354; + wire n_0_355; + wire n_0_356; + wire n_0_357; + wire n_0_358; + wire n_0_359; + wire n_0_360; + wire n_0_361; + wire n_0_362; + wire n_0_363; + wire n_0_364; + wire n_0_365; + wire n_0_366; + wire n_0_367; + wire n_0_368; + wire n_0_369; + wire n_0_370; + wire n_0_371; + wire n_0_372; + wire n_0_373; + wire n_0_374; + wire n_0_375; + wire n_0_376; + wire n_0_377; + wire n_0_378; + wire n_0_379; + wire n_0_380; + wire n_0_381; + wire n_0_382; + wire n_0_383; + wire n_0_384; + wire n_0_385; + wire n_0_386; + wire n_0_387; + wire n_0_388; + wire n_0_389; + wire n_0_390; + wire n_0_391; + wire n_0_392; + wire n_0_393; + wire n_0_394; + wire n_0_395; + wire n_0_396; + wire n_0_397; + wire n_0_398; + wire n_0_399; + wire n_0_400; + wire n_0_401; + wire n_0_402; + wire n_0_403; + wire n_0_404; + wire n_0_405; + wire n_0_406; + wire n_0_407; + wire n_0_408; + wire n_0_409; + wire n_0_410; + wire n_0_411; + wire n_0_412; + wire n_0_413; + wire n_0_414; + wire n_0_415; + wire n_0_416; + wire n_0_417; + wire n_0_418; + wire n_0_419; + wire n_0_420; + wire n_0_421; + wire n_0_422; + wire n_0_423; + wire n_0_424; + wire n_0_425; + wire n_0_426; + wire n_0_427; + wire n_0_428; + wire n_0_429; + wire n_0_430; + wire n_0_431; + wire n_0_432; + wire n_0_433; + wire n_0_434; + wire n_0_435; + wire n_0_436; + wire n_0_437; + wire n_0_438; + wire n_0_439; + wire n_0_440; + wire n_0_441; + wire n_0_442; + wire n_0_443; + wire n_0_444; + wire n_0_445; + wire n_0_446; + wire n_0_447; + wire n_0_448; + wire n_0_449; + wire n_0_450; + wire n_0_451; + wire n_0_452; + wire n_0_453; + wire n_0_454; + wire n_0_455; + wire n_0_456; + wire n_0_457; + wire n_0_458; + wire n_0_459; + wire n_0_460; + wire n_0_461; + wire n_0_462; + wire n_0_463; + wire n_0_464; + wire n_0_465; + wire n_0_466; + wire n_0_467; + wire n_0_468; + wire n_0_469; + wire n_0_470; + wire n_0_471; + wire n_0_472; + wire n_0_473; + wire n_0_474; + wire n_0_475; + wire n_0_476; + wire n_0_477; + wire n_0_478; + wire n_0_479; + wire n_0_480; + wire n_0_481; + wire n_0_482; + wire n_0_483; + wire n_0_484; + wire n_0_485; + wire n_0_486; + wire n_0_487; + wire n_0_488; + wire n_0_489; + wire n_0_490; + wire n_0_491; + wire n_0_492; + wire n_0_493; + wire n_0_494; + wire n_0_495; + wire n_0_496; + wire n_0_497; + wire n_0_498; + wire n_0_499; + wire n_0_500; + wire n_0_501; + wire n_0_502; + wire n_0_503; + wire n_0_504; + wire n_0_505; + wire n_0_506; + wire n_0_507; + wire n_0_508; + wire n_0_509; + wire n_0_510; + wire n_0_511; + wire n_0_512; + wire n_0_513; + wire n_0_514; + wire n_0_515; + wire n_0_516; + wire n_0_517; + wire n_0_518; + wire n_0_519; + wire n_0_520; + wire n_0_521; + wire n_0_522; + wire n_0_523; + wire n_0_524; + wire n_0_525; + wire n_0_526; + wire n_0_527; + wire n_0_528; + wire n_0_529; + wire n_0_530; + wire n_0_531; + wire n_0_532; + wire n_0_533; + wire n_0_534; + wire n_0_535; + wire n_0_536; + wire n_0_537; + wire n_0_538; + wire n_0_539; + wire n_0_540; + wire n_0_541; + wire n_0_542; + wire n_0_543; + wire n_0_544; + wire n_0_545; + wire n_0_546; + wire n_0_547; + wire n_0_548; + wire n_0_549; + wire n_0_550; + wire n_0_551; + wire n_0_552; + wire n_0_553; + wire n_0_554; + wire n_0_555; + wire n_0_556; + wire n_0_557; + wire n_0_558; + wire n_0_559; + wire n_0_560; + wire n_0_561; + wire n_0_562; + wire n_0_563; + wire n_0_564; + wire n_0_565; + wire n_0_566; + wire n_0_567; + wire n_0_568; + wire n_0_569; + wire n_0_570; + wire n_0_571; + wire n_0_572; + wire n_0_573; + wire n_0_574; + wire n_0_575; + wire n_0_576; + wire n_0_577; + wire n_0_578; + wire n_0_579; + wire n_0_580; + wire n_0_581; + wire n_0_582; + wire n_0_583; + wire n_0_584; + wire n_0_585; + wire n_0_586; + wire n_0_587; + wire n_0_588; + wire n_0_589; + wire n_0_590; + wire n_0_591; + wire n_0_592; + wire n_0_593; + wire n_0_594; + wire n_0_595; + wire n_0_596; + wire n_0_597; + wire n_0_598; + wire n_0_599; + wire n_0_600; + wire n_0_601; + wire n_0_602; + wire n_0_603; + wire n_0_604; + wire n_0_605; + wire n_0_606; + wire n_0_607; + wire n_0_608; + wire n_0_609; + wire n_0_610; + wire n_0_611; + wire n_0_612; + wire n_0_613; + wire n_0_614; + wire n_0_615; + wire n_0_616; + wire n_0_617; + wire n_0_618; + wire n_0_619; + wire n_0_620; + wire n_0_621; + wire n_0_622; + wire n_0_623; + wire n_0_624; + wire n_0_625; + wire n_0_626; + wire n_0_627; + wire n_0_628; + wire n_0_629; + wire n_0_630; + wire n_0_631; + wire n_0_632; + wire n_0_633; + wire n_0_634; + wire n_0_635; + wire n_0_636; + wire n_0_637; + wire n_0_638; + wire n_0_639; + wire n_0_640; + wire n_0_641; + wire n_0_642; + wire n_0_643; + wire n_0_644; + wire n_0_645; + wire n_0_646; + wire n_0_647; + wire n_0_648; + wire n_0_649; + wire n_0_650; + wire n_0_651; + wire n_0_652; + wire n_0_653; + wire n_0_654; + wire n_0_655; + wire n_0_656; + wire n_0_657; + wire n_0_658; + wire n_0_659; + wire n_0_660; + wire n_0_661; + wire n_0_662; + wire n_0_663; + wire n_0_664; + wire n_0_665; + wire n_0_666; + wire n_0_667; + wire n_0_668; + wire n_0_669; + wire n_0_670; + wire n_0_671; + wire n_0_672; + wire n_0_673; + wire n_0_674; + wire n_0_675; + wire n_0_676; + wire n_0_677; + wire n_0_678; + wire n_0_679; + wire n_0_680; + wire n_0_681; + wire n_0_682; + wire n_0_683; + wire n_0_684; + wire n_0_685; + wire n_0_686; + wire n_0_687; + wire n_0_688; + wire n_0_689; + wire n_0_690; + wire n_0_691; + wire n_0_692; + wire n_0_693; + wire n_0_694; + wire n_0_695; + wire n_0_696; + wire n_0_697; + wire n_0_698; + wire n_0_699; + wire n_0_700; + wire n_0_701; + wire n_0_702; + wire n_0_703; + wire n_0_704; + wire n_0_705; + wire n_0_706; + wire n_0_707; + wire n_0_708; + wire n_0_709; + wire n_0_710; + wire n_0_711; + wire n_0_712; + wire n_0_713; + wire n_0_714; + wire n_0_715; + wire n_0_716; + wire n_0_717; + wire n_0_718; + wire n_0_719; + wire n_0_720; + wire n_0_721; + wire n_0_722; + wire n_0_723; + wire n_0_724; + wire n_0_725; + wire n_0_726; + wire n_0_727; + wire n_0_728; + wire n_0_729; + wire n_0_730; + wire n_0_731; + wire n_0_732; + wire n_0_733; + wire n_0_734; + wire n_0_735; + wire n_0_736; + wire n_0_737; + wire n_0_738; + wire n_0_739; + wire n_0_740; + + INV_X1_LVT i_0_725 (.A(op2[31]), .ZN(n_0_692)); + INV_X1_LVT i_0_724 (.A(op1[31]), .ZN(n_0_691)); + INV_X1_LVT i_0_718 (.A(aluOp[1]), .ZN(n_0_685)); + INV_X1_LVT i_0_717 (.A(aluOp[2]), .ZN(n_0_684)); + NOR2_X1_LVT i_0_599 (.A1(n_0_685), .A2(n_0_684), .ZN(n_0_567)); + INV_X1_LVT i_0_598 (.A(n_0_567), .ZN(n_0_566)); + INV_X1_LVT i_0_716 (.A(aluOp[0]), .ZN(n_0_683)); + NAND2_X1_LVT i_0_602 (.A1(aluOp[2]), .A2(aluNegAr), .ZN(n_0_570)); + OAI21_X1_LVT i_0_590 (.A(n_0_566), .B1(n_0_683), .B2(n_0_570), .ZN(n_0_558)); + INV_X1_LVT i_0_714 (.A(aluBypass), .ZN(n_0_681)); + NOR2_X1_LVT i_0_601 (.A1(n_0_684), .A2(aluOp[0]), .ZN(n_0_569)); + NAND2_X1_LVT i_0_597 (.A1(n_0_681), .A2(n_0_569), .ZN(n_0_565)); + INV_X1_LVT i_0_596 (.A(n_0_565), .ZN(n_0_564)); + OAI22_X1_LVT i_0_589 (.A1(n_0_691), .A2(n_0_558), .B1(op1[31]), .B2(n_0_564), + .ZN(n_0_557)); + NOR2_X1_LVT i_0_588 (.A1(n_0_692), .A2(n_0_557), .ZN(n_0_556)); + XNOR2_X1_LVT i_9_31 (.A(op2[31]), .B(op1[31]), .ZN(n_9_31)); + HA_X1_LVT i_9_0 (.A(op2[0]), .B(op1[0]), .CO(n_9_0), .S(n_0)); + FA_X1_LVT i_9_1 (.A(op2[1]), .B(op1[1]), .CI(n_9_0), .CO(n_9_1), .S(n_1)); + FA_X1_LVT i_9_2 (.A(op2[2]), .B(op1[2]), .CI(n_9_1), .CO(n_9_2), .S(n_2)); + FA_X1_LVT i_9_3 (.A(op2[3]), .B(op1[3]), .CI(n_9_2), .CO(n_9_3), .S(n_3)); + FA_X1_LVT i_9_4 (.A(op2[4]), .B(op1[4]), .CI(n_9_3), .CO(n_9_4), .S(n_4)); + FA_X1_LVT i_9_5 (.A(op2[5]), .B(op1[5]), .CI(n_9_4), .CO(n_9_5), .S(n_5)); + FA_X1_LVT i_9_6 (.A(op2[6]), .B(op1[6]), .CI(n_9_5), .CO(n_9_6), .S(n_6)); + FA_X1_LVT i_9_7 (.A(op2[7]), .B(op1[7]), .CI(n_9_6), .CO(n_9_7), .S(n_7)); + FA_X1_LVT i_9_8 (.A(op2[8]), .B(op1[8]), .CI(n_9_7), .CO(n_9_8), .S(n_8)); + FA_X1_LVT i_9_9 (.A(op2[9]), .B(op1[9]), .CI(n_9_8), .CO(n_9_9), .S(n_9)); + FA_X1_LVT i_9_10 (.A(op2[10]), .B(op1[10]), .CI(n_9_9), .CO(n_9_10), .S(n_10)); + FA_X1_LVT i_9_11 (.A(op2[11]), .B(op1[11]), .CI(n_9_10), .CO(n_9_11), + .S(n_11)); + FA_X1_LVT i_9_12 (.A(op2[12]), .B(op1[12]), .CI(n_9_11), .CO(n_9_12), + .S(n_12)); + FA_X1_LVT i_9_13 (.A(op2[13]), .B(op1[13]), .CI(n_9_12), .CO(n_9_13), + .S(n_13)); + FA_X1_LVT i_9_14 (.A(op2[14]), .B(op1[14]), .CI(n_9_13), .CO(n_9_14), + .S(n_14)); + FA_X1_LVT i_9_15 (.A(op2[15]), .B(op1[15]), .CI(n_9_14), .CO(n_9_15), + .S(n_15)); + FA_X1_LVT i_9_16 (.A(op2[16]), .B(op1[16]), .CI(n_9_15), .CO(n_9_16), + .S(n_16)); + FA_X1_LVT i_9_17 (.A(op2[17]), .B(op1[17]), .CI(n_9_16), .CO(n_9_17), + .S(n_17)); + FA_X1_LVT i_9_18 (.A(op2[18]), .B(op1[18]), .CI(n_9_17), .CO(n_9_18), + .S(n_18)); + FA_X1_LVT i_9_19 (.A(op2[19]), .B(op1[19]), .CI(n_9_18), .CO(n_9_19), + .S(n_19)); + FA_X1_LVT i_9_20 (.A(op2[20]), .B(op1[20]), .CI(n_9_19), .CO(n_9_20), + .S(n_20)); + FA_X1_LVT i_9_21 (.A(op2[21]), .B(op1[21]), .CI(n_9_20), .CO(n_9_21), + .S(n_21)); + FA_X1_LVT i_9_22 (.A(op2[22]), .B(op1[22]), .CI(n_9_21), .CO(n_9_22), + .S(n_22)); + FA_X1_LVT i_9_23 (.A(op2[23]), .B(op1[23]), .CI(n_9_22), .CO(n_9_23), + .S(n_23)); + FA_X1_LVT i_9_24 (.A(op2[24]), .B(op1[24]), .CI(n_9_23), .CO(n_9_24), + .S(n_24)); + FA_X1_LVT i_9_25 (.A(op2[25]), .B(op1[25]), .CI(n_9_24), .CO(n_9_25), + .S(n_25)); + FA_X1_LVT i_9_26 (.A(op2[26]), .B(op1[26]), .CI(n_9_25), .CO(n_9_26), + .S(n_26)); + FA_X1_LVT i_9_27 (.A(op2[27]), .B(op1[27]), .CI(n_9_26), .CO(n_9_27), + .S(n_27)); + FA_X1_LVT i_9_28 (.A(op2[28]), .B(op1[28]), .CI(n_9_27), .CO(n_9_28), + .S(n_28)); + FA_X1_LVT i_9_29 (.A(op2[29]), .B(op1[29]), .CI(n_9_28), .CO(n_9_29), + .S(n_29)); + FA_X1_LVT i_9_30 (.A(op2[30]), .B(op1[30]), .CI(n_9_29), .CO(n_9_30), + .S(n_30)); + XNOR2_X1_LVT i_9_32 (.A(n_9_31), .B(n_9_30), .ZN(n_31)); + NAND4_X1_LVT i_0_614 (.A1(n_0_685), .A2(n_0_681), .A3(n_0_684), .A4(n_0_683), + .ZN(n_0_582)); + NOR2_X1_LVT i_0_613 (.A1(aluNegAr), .A2(n_0_582), .ZN(n_0_581)); + INV_X1_LVT i_10_147 (.A(op2[30]), .ZN(n_10_117)); + NAND2_X1_LVT i_10_149 (.A1(n_10_117), .A2(op1[30]), .ZN(n_10_119)); + INV_X1_LVT i_10_152 (.A(n_10_119), .ZN(n_10_121)); + INV_X1_LVT i_10_130 (.A(op1[26]), .ZN(n_10_104)); + NAND2_X1_LVT i_10_131 (.A1(n_10_104), .A2(op2[26]), .ZN(n_10_105)); + INV_X1_LVT i_10_123 (.A(op2[25]), .ZN(n_10_98)); + NAND2_X1_LVT i_10_125 (.A1(n_10_98), .A2(op1[25]), .ZN(n_10_100)); + INV_X1_LVT i_10_112 (.A(op2[23]), .ZN(n_10_89)); + NAND2_X1_LVT i_10_114 (.A1(n_10_89), .A2(op1[23]), .ZN(n_10_91)); + INV_X1_LVT i_10_101 (.A(op2[21]), .ZN(n_10_80)); + NAND2_X1_LVT i_10_103 (.A1(n_10_80), .A2(op1[21]), .ZN(n_10_82)); + INV_X1_LVT i_10_48 (.A(op1[8]), .ZN(n_10_40)); + NAND2_X1_LVT i_10_49 (.A1(n_10_40), .A2(op2[8]), .ZN(n_10_41)); + INV_X1_LVT i_10_41 (.A(op2[7]), .ZN(n_10_34)); + NAND2_X1_LVT i_10_43 (.A1(n_10_34), .A2(op1[7]), .ZN(n_10_36)); + INV_X1_LVT i_10_32 (.A(op2[5]), .ZN(n_10_27)); + NOR2_X1_LVT i_10_33 (.A1(n_10_27), .A2(op1[5]), .ZN(n_10_28)); + INV_X1_LVT i_10_24 (.A(op1[4]), .ZN(n_10_20)); + NOR2_X1_LVT i_10_27 (.A1(n_10_20), .A2(op2[4]), .ZN(n_10_23)); + INV_X1_LVT i_10_17 (.A(op2[3]), .ZN(n_10_14)); + NAND2_X1_LVT i_10_19 (.A1(n_10_14), .A2(op1[3]), .ZN(n_10_16)); + INV_X1_LVT i_10_22 (.A(n_10_16), .ZN(n_10_18)); + INV_X1_LVT i_10_10 (.A(op2[2]), .ZN(n_10_8)); + NAND2_X1_LVT i_10_12 (.A1(n_10_8), .A2(op1[2]), .ZN(n_10_10)); + INV_X1_LVT i_10_3 (.A(op1[1]), .ZN(n_10_2)); + NAND2_X1_LVT i_10_5 (.A1(n_10_2), .A2(op2[1]), .ZN(n_10_4)); + INV_X1_LVT i_10_0 (.A(op1[0]), .ZN(n_10_0)); + NAND2_X1_LVT i_10_1 (.A1(n_10_0), .A2(op2[0]), .ZN(n_10_1)); + OR2_X1_LVT i_10_4 (.A1(n_10_2), .A2(op2[1]), .ZN(n_10_3)); + INV_X1_LVT i_10_8 (.A(n_10_3), .ZN(n_10_6)); + OAI21_X1_LVT i_10_9 (.A(n_10_4), .B1(n_10_1), .B2(n_10_6), .ZN(n_10_7)); + NOR2_X1_LVT i_10_11 (.A1(n_10_8), .A2(op1[2]), .ZN(n_10_9)); + OAI21_X1_LVT i_10_16 (.A(n_10_10), .B1(n_10_7), .B2(n_10_9), .ZN(n_10_13)); + OR2_X1_LVT i_10_18 (.A1(n_10_14), .A2(op1[3]), .ZN(n_10_15)); + AOI21_X1_LVT i_10_23 (.A(n_10_18), .B1(n_10_13), .B2(n_10_15), .ZN(n_10_19)); + INV_X1_LVT i_10_30 (.A(n_10_19), .ZN(n_10_25)); + NAND2_X1_LVT i_10_25 (.A1(n_10_20), .A2(op2[4]), .ZN(n_10_21)); + AOI21_X1_LVT i_10_31 (.A(n_10_23), .B1(n_10_25), .B2(n_10_21), .ZN(n_10_26)); + AOI21_X1_LVT i_10_34 (.A(n_10_28), .B1(n_10_27), .B2(op1[5]), .ZN(n_10_29)); + AOI21_X1_LVT i_10_36 (.A(n_10_28), .B1(n_10_26), .B2(n_10_29), .ZN(n_10_30)); + XOR2_X1_LVT i_10_37 (.A(op2[6]), .B(op1[6]), .Z(n_10_31)); + INV_X1_LVT i_10_39 (.A(op2[6]), .ZN(n_10_32)); + OAI22_X1_LVT i_10_40 (.A1(n_10_30), .A2(n_10_31), .B1(n_10_32), .B2(op1[6]), + .ZN(n_10_33)); + NOR2_X1_LVT i_10_42 (.A1(n_10_34), .A2(op1[7]), .ZN(n_10_35)); + OAI21_X1_LVT i_10_47 (.A(n_10_36), .B1(n_10_33), .B2(n_10_35), .ZN(n_10_39)); + OAI21_X1_LVT i_10_50 (.A(n_10_41), .B1(n_10_40), .B2(op2[8]), .ZN(n_10_42)); + OAI21_X1_LVT i_10_52 (.A(n_10_41), .B1(n_10_39), .B2(n_10_42), .ZN(n_10_43)); + XNOR2_X1_LVT i_10_53 (.A(op2[9]), .B(op1[9]), .ZN(n_10_44)); + INV_X1_LVT i_10_55 (.A(op1[9]), .ZN(n_10_45)); + AOI22_X1_LVT i_10_56 (.A1(n_10_43), .A2(n_10_44), .B1(n_10_45), .B2(op2[9]), + .ZN(n_10_46)); + XOR2_X1_LVT i_10_57 (.A(op2[10]), .B(op1[10]), .Z(n_10_47)); + INV_X1_LVT i_10_59 (.A(op2[10]), .ZN(n_10_48)); + OAI22_X1_LVT i_10_60 (.A1(n_10_46), .A2(n_10_47), .B1(n_10_48), .B2(op1[10]), + .ZN(n_10_49)); + XNOR2_X1_LVT i_10_61 (.A(op2[11]), .B(op1[11]), .ZN(n_10_50)); + INV_X1_LVT i_10_63 (.A(op1[11]), .ZN(n_10_51)); + AOI22_X1_LVT i_10_64 (.A1(n_10_49), .A2(n_10_50), .B1(n_10_51), .B2(op2[11]), + .ZN(n_10_52)); + XOR2_X1_LVT i_10_65 (.A(op2[12]), .B(op1[12]), .Z(n_10_53)); + INV_X1_LVT i_10_67 (.A(op2[12]), .ZN(n_10_54)); + OAI22_X1_LVT i_10_68 (.A1(n_10_52), .A2(n_10_53), .B1(n_10_54), .B2(op1[12]), + .ZN(n_10_55)); + XNOR2_X1_LVT i_10_69 (.A(op2[13]), .B(op1[13]), .ZN(n_10_56)); + INV_X1_LVT i_10_71 (.A(op1[13]), .ZN(n_10_57)); + AOI22_X1_LVT i_10_72 (.A1(n_10_55), .A2(n_10_56), .B1(n_10_57), .B2(op2[13]), + .ZN(n_10_58)); + XOR2_X1_LVT i_10_73 (.A(op2[14]), .B(op1[14]), .Z(n_10_59)); + INV_X1_LVT i_10_75 (.A(op2[14]), .ZN(n_10_60)); + OAI22_X1_LVT i_10_76 (.A1(n_10_58), .A2(n_10_59), .B1(n_10_60), .B2(op1[14]), + .ZN(n_10_61)); + XNOR2_X1_LVT i_10_77 (.A(op2[15]), .B(op1[15]), .ZN(n_10_62)); + INV_X1_LVT i_10_79 (.A(op1[15]), .ZN(n_10_63)); + AOI22_X1_LVT i_10_80 (.A1(n_10_61), .A2(n_10_62), .B1(n_10_63), .B2(op2[15]), + .ZN(n_10_64)); + XOR2_X1_LVT i_10_81 (.A(op2[16]), .B(op1[16]), .Z(n_10_65)); + INV_X1_LVT i_10_83 (.A(op2[16]), .ZN(n_10_66)); + OAI22_X1_LVT i_10_84 (.A1(n_10_64), .A2(n_10_65), .B1(n_10_66), .B2(op1[16]), + .ZN(n_10_67)); + XNOR2_X1_LVT i_10_85 (.A(op2[17]), .B(op1[17]), .ZN(n_10_68)); + INV_X1_LVT i_10_87 (.A(op1[17]), .ZN(n_10_69)); + AOI22_X1_LVT i_10_88 (.A1(n_10_67), .A2(n_10_68), .B1(n_10_69), .B2(op2[17]), + .ZN(n_10_70)); + XOR2_X1_LVT i_10_89 (.A(op2[18]), .B(op1[18]), .Z(n_10_71)); + INV_X1_LVT i_10_91 (.A(op2[18]), .ZN(n_10_72)); + OAI22_X1_LVT i_10_92 (.A1(n_10_70), .A2(n_10_71), .B1(n_10_72), .B2(op1[18]), + .ZN(n_10_73)); + XNOR2_X1_LVT i_10_93 (.A(op2[19]), .B(op1[19]), .ZN(n_10_74)); + INV_X1_LVT i_10_95 (.A(op1[19]), .ZN(n_10_75)); + AOI22_X1_LVT i_10_96 (.A1(n_10_73), .A2(n_10_74), .B1(n_10_75), .B2(op2[19]), + .ZN(n_10_76)); + XOR2_X1_LVT i_10_97 (.A(op2[20]), .B(op1[20]), .Z(n_10_77)); + INV_X1_LVT i_10_99 (.A(op2[20]), .ZN(n_10_78)); + OAI22_X1_LVT i_10_100 (.A1(n_10_76), .A2(n_10_77), .B1(n_10_78), .B2(op1[20]), + .ZN(n_10_79)); + NOR2_X1_LVT i_10_102 (.A1(n_10_80), .A2(op1[21]), .ZN(n_10_81)); + OAI21_X1_LVT i_10_107 (.A(n_10_82), .B1(n_10_79), .B2(n_10_81), .ZN(n_10_85)); + XOR2_X1_LVT i_10_108 (.A(op2[22]), .B(op1[22]), .Z(n_10_86)); + INV_X1_LVT i_10_110 (.A(op2[22]), .ZN(n_10_87)); + OAI22_X1_LVT i_10_111 (.A1(n_10_85), .A2(n_10_86), .B1(n_10_87), .B2(op1[22]), + .ZN(n_10_88)); + NOR2_X1_LVT i_10_113 (.A1(n_10_89), .A2(op1[23]), .ZN(n_10_90)); + OAI21_X1_LVT i_10_118 (.A(n_10_91), .B1(n_10_88), .B2(n_10_90), .ZN(n_10_94)); + XOR2_X1_LVT i_10_119 (.A(op2[24]), .B(op1[24]), .Z(n_10_95)); + INV_X1_LVT i_10_121 (.A(op2[24]), .ZN(n_10_96)); + OAI22_X1_LVT i_10_122 (.A1(n_10_94), .A2(n_10_95), .B1(n_10_96), .B2(op1[24]), + .ZN(n_10_97)); + NOR2_X1_LVT i_10_124 (.A1(n_10_98), .A2(op1[25]), .ZN(n_10_99)); + OAI21_X1_LVT i_10_129 (.A(n_10_100), .B1(n_10_97), .B2(n_10_99), .ZN(n_10_103)); + OAI21_X1_LVT i_10_132 (.A(n_10_105), .B1(n_10_104), .B2(op2[26]), .ZN( + n_10_106)); + OAI21_X1_LVT i_10_134 (.A(n_10_105), .B1(n_10_103), .B2(n_10_106), .ZN( + n_10_107)); + XNOR2_X1_LVT i_10_135 (.A(op2[27]), .B(op1[27]), .ZN(n_10_108)); + INV_X1_LVT i_10_137 (.A(op1[27]), .ZN(n_10_109)); + AOI22_X1_LVT i_10_138 (.A1(n_10_107), .A2(n_10_108), .B1(n_10_109), .B2( + op2[27]), .ZN(n_10_110)); + XOR2_X1_LVT i_10_139 (.A(op2[28]), .B(op1[28]), .Z(n_10_111)); + INV_X1_LVT i_10_141 (.A(op2[28]), .ZN(n_10_112)); + OAI22_X1_LVT i_10_142 (.A1(n_10_110), .A2(n_10_111), .B1(n_10_112), .B2( + op1[28]), .ZN(n_10_113)); + XNOR2_X1_LVT i_10_143 (.A(op2[29]), .B(op1[29]), .ZN(n_10_114)); + INV_X1_LVT i_10_145 (.A(op1[29]), .ZN(n_10_115)); + AOI22_X1_LVT i_10_146 (.A1(n_10_113), .A2(n_10_114), .B1(n_10_115), .B2( + op2[29]), .ZN(n_10_116)); + OR2_X1_LVT i_10_148 (.A1(n_10_117), .A2(op1[30]), .ZN(n_10_118)); + AOI21_X1_LVT i_10_153 (.A(n_10_121), .B1(n_10_116), .B2(n_10_118), .ZN( + n_10_122)); + XNOR2_X1_LVT i_10_154 (.A(op1[31]), .B(op2[31]), .ZN(n_10_123)); + XNOR2_X1_LVT i_10_155 (.A(n_10_122), .B(n_10_123), .ZN(n_63)); + INV_X1_LVT i_0_715 (.A(aluNegAr), .ZN(n_0_682)); + NOR2_X1_LVT i_0_612 (.A1(n_0_682), .A2(n_0_582), .ZN(n_0_580)); + AOI221_X1_LVT i_0_587 (.A(n_0_556), .B1(n_31), .B2(n_0_581), .C1(n_63), + .C2(n_0_580), .ZN(n_0_555)); + NOR3_X1_LVT i_0_654 (.A1(aluOp[1]), .A2(aluBypass), .A3(n_0_683), .ZN(n_0_622)); + NAND2_X1_LVT i_0_653 (.A1(n_0_684), .A2(n_0_622), .ZN(n_0_621)); + INV_X1_LVT i_0_734 (.A(op2[0]), .ZN(n_0_701)); + INV_X1_LVT i_0_756 (.A(op2[3]), .ZN(n_0_723)); + NOR2_X1_LVT i_0_650 (.A1(op2[4]), .A2(n_0_723), .ZN(n_0_618)); + INV_X1_LVT i_0_649 (.A(n_0_618), .ZN(n_0_617)); + NOR2_X1_LVT i_0_648 (.A1(op2[4]), .A2(op2[3]), .ZN(n_0_616)); + INV_X1_LVT i_0_647 (.A(n_0_616), .ZN(n_0_615)); + INV_X1_LVT i_0_771 (.A(op2[4]), .ZN(n_0_738)); + INV_X1_LVT i_0_767 (.A(op1[15]), .ZN(n_0_734)); + INV_X1_LVT i_0_746 (.A(op1[7]), .ZN(n_0_713)); + AOI22_X1_LVT i_0_651 (.A1(n_0_734), .A2(n_0_723), .B1(op2[3]), .B2(n_0_713), + .ZN(n_0_619)); + OAI222_X1_LVT i_0_646 (.A1(op1[23]), .A2(n_0_617), .B1(op1[31]), .B2(n_0_615), + .C1(n_0_738), .C2(n_0_619), .ZN(n_0_614)); + NOR2_X1_LVT i_0_645 (.A1(op2[2]), .A2(n_0_614), .ZN(n_0_613)); + NOR2_X1_LVT i_0_696 (.A1(op1[3]), .A2(n_0_723), .ZN(n_0_663)); + INV_X1_LVT i_0_739 (.A(op1[11]), .ZN(n_0_706)); + AOI21_X1_LVT i_0_644 (.A(n_0_663), .B1(n_0_723), .B2(n_0_706), .ZN(n_0_612)); + AOI22_X1_LVT i_0_643 (.A1(op2[4]), .A2(n_0_612), .B1(op1[27]), .B2(n_0_616), + .ZN(n_0_611)); + INV_X1_LVT i_0_722 (.A(op1[19]), .ZN(n_0_689)); + OAI21_X1_LVT i_0_642 (.A(n_0_611), .B1(n_0_689), .B2(n_0_617), .ZN(n_0_610)); + AOI21_X1_LVT i_0_641 (.A(n_0_613), .B1(op2[2]), .B2(n_0_610), .ZN(n_0_609)); + INV_X1_LVT i_0_761 (.A(op2[1]), .ZN(n_0_728)); + OAI22_X1_LVT i_0_640 (.A1(op2[4]), .A2(op1[21]), .B1(n_0_738), .B2(op1[5]), + .ZN(n_0_608)); + NAND2_X1_LVT i_0_639 (.A1(op2[3]), .A2(n_0_608), .ZN(n_0_607)); + INV_X1_LVT i_0_747 (.A(op1[13]), .ZN(n_0_714)); + NOR2_X1_LVT i_0_638 (.A1(n_0_738), .A2(op2[3]), .ZN(n_0_606)); + INV_X1_LVT i_0_743 (.A(op1[29]), .ZN(n_0_710)); + AOI221_X1_LVT i_0_636 (.A(op2[2]), .B1(n_0_714), .B2(n_0_606), .C1(n_0_710), + .C2(n_0_616), .ZN(n_0_604)); + OAI22_X1_LVT i_0_635 (.A1(op2[4]), .A2(op1[17]), .B1(n_0_738), .B2(op1[1]), + .ZN(n_0_603)); + INV_X1_LVT i_0_755 (.A(op1[9]), .ZN(n_0_722)); + INV_X1_LVT i_0_637 (.A(n_0_606), .ZN(n_0_605)); + INV_X1_LVT i_0_732 (.A(op1[25]), .ZN(n_0_699)); + OAI222_X1_LVT i_0_634 (.A1(n_0_723), .A2(n_0_603), .B1(n_0_722), .B2(n_0_605), + .C1(n_0_699), .C2(n_0_615), .ZN(n_0_602)); + AOI22_X1_LVT i_0_633 (.A1(n_0_607), .A2(n_0_604), .B1(op2[2]), .B2(n_0_602), + .ZN(n_0_601)); + OAI221_X1_LVT i_0_616 (.A(n_0_701), .B1(op2[1]), .B2(n_0_609), .C1(n_0_728), + .C2(n_0_601), .ZN(n_0_584)); + INV_X1_LVT i_0_729 (.A(op1[12]), .ZN(n_0_696)); + INV_X1_LVT i_0_731 (.A(op1[28]), .ZN(n_0_698)); + AOI22_X1_LVT i_0_622 (.A1(n_0_696), .A2(n_0_606), .B1(n_0_698), .B2(n_0_616), + .ZN(n_0_590)); + INV_X1_LVT i_0_726 (.A(op2[2]), .ZN(n_0_693)); + NOR2_X1_LVT i_0_701 (.A1(n_0_738), .A2(op1[4]), .ZN(n_0_668)); + INV_X1_LVT i_0_760 (.A(op1[20]), .ZN(n_0_727)); + AOI21_X1_LVT i_0_623 (.A(n_0_668), .B1(n_0_738), .B2(n_0_727), .ZN(n_0_591)); + OAI211_X1_LVT i_0_621 (.A(n_0_590), .B(n_0_693), .C1(n_0_723), .C2(n_0_591), + .ZN(n_0_589)); + OAI22_X1_LVT i_0_626 (.A1(op1[16]), .A2(op2[4]), .B1(n_0_738), .B2(op1[0]), + .ZN(n_0_594)); + INV_X1_LVT i_0_769 (.A(op1[24]), .ZN(n_0_736)); + OAI22_X1_LVT i_0_625 (.A1(n_0_723), .A2(n_0_594), .B1(n_0_736), .B2(n_0_615), + .ZN(n_0_593)); + AOI21_X1_LVT i_0_624 (.A(n_0_593), .B1(op1[8]), .B2(n_0_606), .ZN(n_0_592)); + OAI21_X1_LVT i_0_620 (.A(n_0_589), .B1(n_0_693), .B2(n_0_592), .ZN(n_0_588)); + INV_X1_LVT i_0_737 (.A(op1[6]), .ZN(n_0_704)); + INV_X1_LVT i_0_720 (.A(op1[22]), .ZN(n_0_687)); + OAI22_X1_LVT i_0_632 (.A1(n_0_738), .A2(n_0_704), .B1(op2[4]), .B2(n_0_687), + .ZN(n_0_600)); + OAI221_X1_LVT i_0_631 (.A(n_0_693), .B1(n_0_723), .B2(n_0_600), .C1(op1[14]), + .C2(n_0_605), .ZN(n_0_599)); + INV_X1_LVT i_0_750 (.A(op1[30]), .ZN(n_0_717)); + AOI21_X1_LVT i_0_630 (.A(n_0_599), .B1(n_0_717), .B2(n_0_616), .ZN(n_0_598)); + INV_X1_LVT i_0_738 (.A(op1[18]), .ZN(n_0_705)); + NOR2_X1_LVT i_0_628 (.A1(n_0_705), .A2(n_0_617), .ZN(n_0_596)); + INV_X1_LVT i_0_727 (.A(op1[2]), .ZN(n_0_694)); + INV_X1_LVT i_0_766 (.A(op1[10]), .ZN(n_0_733)); + OAI22_X1_LVT i_0_629 (.A1(n_0_723), .A2(n_0_694), .B1(n_0_733), .B2(op2[3]), + .ZN(n_0_597)); + AOI221_X1_LVT i_0_627 (.A(n_0_596), .B1(op1[26]), .B2(n_0_616), .C1(op2[4]), + .C2(n_0_597), .ZN(n_0_595)); + OAI21_X1_LVT i_0_619 (.A(n_0_728), .B1(n_0_693), .B2(n_0_595), .ZN(n_0_587)); + OAI22_X1_LVT i_0_618 (.A1(n_0_728), .A2(n_0_588), .B1(n_0_598), .B2(n_0_587), + .ZN(n_0_586)); + INV_X1_LVT i_0_617 (.A(n_0_586), .ZN(n_0_585)); + OAI21_X1_LVT i_0_615 (.A(n_0_584), .B1(n_0_701), .B2(n_0_585), .ZN(n_0_583)); + NOR2_X1_LVT i_0_607 (.A1(op2[4]), .A2(op2[2]), .ZN(n_0_575)); + NAND2_X1_LVT i_0_606 (.A1(n_0_723), .A2(n_0_575), .ZN(n_0_574)); + INV_X1_LVT i_0_605 (.A(n_0_574), .ZN(n_0_573)); + NAND2_X1_LVT i_0_604 (.A1(n_0_728), .A2(n_0_573), .ZN(n_0_572)); + NAND2_X1_LVT i_0_611 (.A1(aluOp[2]), .A2(n_0_622), .ZN(n_0_579)); + INV_X1_LVT i_0_610 (.A(n_0_579), .ZN(n_0_578)); + NAND2_X1_LVT i_0_594 (.A1(n_0_701), .A2(n_0_578), .ZN(n_0_562)); + NOR3_X1_LVT i_0_592 (.A1(aluNegAr), .A2(n_0_572), .A3(n_0_562), .ZN(n_0_560)); + INV_X1_LVT i_0_600 (.A(n_0_569), .ZN(n_0_568)); + OAI21_X1_LVT i_0_595 (.A(n_0_568), .B1(aluOp[1]), .B2(n_0_570), .ZN(n_0_563)); + AOI211_X1_LVT i_0_591 (.A(aluBypass), .B(n_0_560), .C1(n_0_692), .C2(n_0_563), + .ZN(n_0_559)); + OAI221_X1_LVT i_0_586 (.A(n_0_555), .B1(n_0_621), .B2(n_0_583), .C1(n_0_691), + .C2(n_0_559), .ZN(result[31])); + NAND2_X1_LVT i_10_150 (.A1(n_10_118), .A2(n_10_119), .ZN(n_10_120)); + XNOR2_X1_LVT i_10_151 (.A(n_10_116), .B(n_10_120), .ZN(n_62)); + AOI22_X1_LVT i_0_580 (.A1(n_62), .A2(n_0_580), .B1(n_30), .B2(n_0_581), + .ZN(n_0_549)); + NAND2_X1_LVT i_0_576 (.A1(aluNegAr), .A2(n_0_578), .ZN(n_0_545)); + INV_X1_LVT i_0_603 (.A(n_0_572), .ZN(n_0_571)); + NOR3_X1_LVT i_0_574 (.A1(n_0_691), .A2(n_0_545), .A3(n_0_571), .ZN(n_0_543)); + AOI22_X1_LVT i_0_573 (.A1(n_0_717), .A2(n_0_565), .B1(op1[30]), .B2(n_0_566), + .ZN(n_0_542)); + AOI21_X1_LVT i_0_572 (.A(n_0_543), .B1(op2[30]), .B2(n_0_542), .ZN(n_0_541)); + NAND2_X1_LVT i_0_579 (.A1(op2[0]), .A2(n_0_578), .ZN(n_0_548)); + NAND2_X1_LVT i_0_577 (.A1(op1[31]), .A2(n_0_571), .ZN(n_0_546)); + OAI211_X1_LVT i_0_571 (.A(n_0_549), .B(n_0_541), .C1(n_0_548), .C2(n_0_546), + .ZN(n_0_540)); + OAI221_X1_LVT i_0_581 (.A(n_0_681), .B1(op2[30]), .B2(n_0_568), .C1(n_0_572), + .C2(n_0_562), .ZN(n_0_550)); + AOI21_X1_LVT i_0_570 (.A(n_0_540), .B1(op1[30]), .B2(n_0_550), .ZN(n_0_539)); + INV_X1_LVT i_0_752 (.A(op1[23]), .ZN(n_0_719)); + OAI222_X1_LVT i_0_585 (.A1(n_0_713), .A2(n_0_605), .B1(n_0_719), .B2(n_0_615), + .C1(n_0_734), .C2(n_0_617), .ZN(n_0_554)); + AOI22_X1_LVT i_0_584 (.A1(op2[2]), .A2(n_0_554), .B1(n_0_693), .B2(n_0_610), + .ZN(n_0_553)); + OAI22_X1_LVT i_0_583 (.A1(n_0_728), .A2(n_0_553), .B1(op2[1]), .B2(n_0_601), + .ZN(n_0_552)); + AOI22_X1_LVT i_0_582 (.A1(n_0_701), .A2(n_0_585), .B1(op2[0]), .B2(n_0_552), + .ZN(n_0_551)); + OAI21_X1_LVT i_0_569 (.A(n_0_539), .B1(n_0_621), .B2(n_0_551), .ZN(result[30])); + INV_X1_LVT i_0_578 (.A(n_0_548), .ZN(n_0_547)); + NAND3_X1_LVT i_0_562 (.A1(op1[30]), .A2(n_0_571), .A3(n_0_547), .ZN(n_0_532)); + XNOR2_X1_LVT i_10_144 (.A(n_10_113), .B(n_10_114), .ZN(n_61)); + NAND2_X1_LVT i_0_558 (.A1(n_61), .A2(n_0_580), .ZN(n_0_528)); + OAI21_X1_LVT i_0_557 (.A(n_0_681), .B1(op2[29]), .B2(n_0_568), .ZN(n_0_527)); + NAND2_X1_LVT i_0_556 (.A1(op1[29]), .A2(n_0_566), .ZN(n_0_526)); + AOI22_X1_LVT i_0_555 (.A1(op1[29]), .A2(n_0_527), .B1(op2[29]), .B2(n_0_526), + .ZN(n_0_525)); + AOI21_X1_LVT i_0_554 (.A(n_0_525), .B1(n_0_710), .B2(n_0_565), .ZN(n_0_524)); + AOI211_X1_LVT i_0_553 (.A(n_0_543), .B(n_0_524), .C1(n_29), .C2(n_0_581), + .ZN(n_0_523)); + AND3_X1_LVT i_0_552 (.A1(n_0_532), .A2(n_0_528), .A3(n_0_523), .ZN(n_0_522)); + INV_X1_LVT i_0_652 (.A(n_0_621), .ZN(n_0_620)); + NAND2_X1_LVT i_0_565 (.A1(n_0_728), .A2(n_0_588), .ZN(n_0_535)); + AOI22_X1_LVT i_0_568 (.A1(n_0_723), .A2(n_0_600), .B1(op1[14]), .B2(n_0_618), + .ZN(n_0_538)); + AOI22_X1_LVT i_0_567 (.A1(n_0_693), .A2(n_0_595), .B1(op2[2]), .B2(n_0_538), + .ZN(n_0_537)); + INV_X1_LVT i_0_566 (.A(n_0_537), .ZN(n_0_536)); + OAI21_X1_LVT i_0_564 (.A(n_0_535), .B1(n_0_728), .B2(n_0_536), .ZN(n_0_534)); + OAI221_X1_LVT i_0_563 (.A(n_0_620), .B1(op2[0]), .B2(n_0_552), .C1(n_0_701), + .C2(n_0_534), .ZN(n_0_533)); + NAND2_X1_LVT i_0_561 (.A1(op2[1]), .A2(n_0_573), .ZN(n_0_531)); + INV_X1_LVT i_0_560 (.A(n_0_531), .ZN(n_0_530)); + AOI22_X1_LVT i_0_559 (.A1(op1[31]), .A2(n_0_530), .B1(op1[29]), .B2(n_0_571), + .ZN(n_0_529)); + OAI211_X1_LVT i_0_551 (.A(n_0_522), .B(n_0_533), .C1(n_0_562), .C2(n_0_529), + .ZN(result[29])); + INV_X1_LVT i_0_733 (.A(op2[28]), .ZN(n_0_700)); + AOI221_X1_LVT i_0_546 (.A(n_0_700), .B1(op1[28]), .B2(n_0_566), .C1(n_0_698), + .C2(n_0_565), .ZN(n_0_517)); + OAI21_X1_LVT i_0_543 (.A(n_0_681), .B1(op2[28]), .B2(n_0_568), .ZN(n_0_514)); + AOI22_X1_LVT i_0_542 (.A1(n_28), .A2(n_0_581), .B1(op1[28]), .B2(n_0_514), + .ZN(n_0_513)); + XNOR2_X1_LVT i_10_140 (.A(n_10_110), .B(n_10_111), .ZN(n_60)); + NAND2_X1_LVT i_0_544 (.A1(n_60), .A2(n_0_580), .ZN(n_0_515)); + NAND2_X1_LVT i_0_545 (.A1(op1[31]), .A2(n_0_574), .ZN(n_0_516)); + OAI211_X1_LVT i_0_541 (.A(n_0_513), .B(n_0_515), .C1(n_0_545), .C2(n_0_516), + .ZN(n_0_512)); + AOI22_X1_LVT i_0_540 (.A1(op1[30]), .A2(n_0_530), .B1(op1[28]), .B2(n_0_571), + .ZN(n_0_511)); + OAI22_X1_LVT i_0_539 (.A1(n_0_562), .A2(n_0_511), .B1(n_0_548), .B2(n_0_529), + .ZN(n_0_510)); + NOR3_X1_LVT i_0_538 (.A1(n_0_517), .A2(n_0_512), .A3(n_0_510), .ZN(n_0_509)); + OAI22_X1_LVT i_0_550 (.A1(n_0_714), .A2(n_0_617), .B1(op2[3]), .B2(n_0_608), + .ZN(n_0_521)); + OAI22_X1_LVT i_0_549 (.A1(op2[2]), .A2(n_0_602), .B1(n_0_693), .B2(n_0_521), + .ZN(n_0_520)); + AOI22_X1_LVT i_0_548 (.A1(op2[1]), .A2(n_0_520), .B1(n_0_728), .B2(n_0_553), + .ZN(n_0_519)); + OAI22_X1_LVT i_0_547 (.A1(op2[0]), .A2(n_0_534), .B1(n_0_701), .B2(n_0_519), + .ZN(n_0_518)); + OAI21_X1_LVT i_0_537 (.A(n_0_509), .B1(n_0_621), .B2(n_0_518), .ZN(result[28])); + XNOR2_X1_LVT i_10_136 (.A(n_10_107), .B(n_10_108), .ZN(n_59)); + AOI22_X1_LVT i_0_517 (.A1(n_27), .A2(n_0_581), .B1(n_59), .B2(n_0_580), + .ZN(n_0_489)); + INV_X1_LVT i_0_721 (.A(op1[27]), .ZN(n_0_688)); + OAI21_X1_LVT i_0_516 (.A(n_0_681), .B1(op2[27]), .B2(n_0_568), .ZN(n_0_488)); + INV_X1_LVT i_0_515 (.A(n_0_488), .ZN(n_0_487)); + OAI221_X1_LVT i_0_514 (.A(n_0_489), .B1(n_0_545), .B2(n_0_516), .C1(n_0_688), + .C2(n_0_487), .ZN(n_0_486)); + OAI21_X1_LVT i_0_530 (.A(op2[1]), .B1(n_0_710), .B2(n_0_574), .ZN(n_0_502)); + OAI21_X1_LVT i_0_529 (.A(n_0_728), .B1(n_0_688), .B2(n_0_574), .ZN(n_0_501)); + NAND2_X1_LVT i_0_528 (.A1(n_0_502), .A2(n_0_501), .ZN(n_0_500)); + AOI21_X1_LVT i_0_527 (.A(n_0_545), .B1(n_0_701), .B2(n_0_500), .ZN(n_0_499)); + NAND2_X1_LVT i_0_609 (.A1(n_0_682), .A2(n_0_578), .ZN(n_0_577)); + NOR2_X1_LVT i_0_526 (.A1(op2[4]), .A2(n_0_693), .ZN(n_0_498)); + NAND2_X1_LVT i_0_525 (.A1(n_0_723), .A2(n_0_498), .ZN(n_0_497)); + OAI22_X1_LVT i_0_523 (.A1(n_0_688), .A2(n_0_574), .B1(n_0_691), .B2(n_0_497), + .ZN(n_0_495)); + OAI21_X1_LVT i_0_522 (.A(n_0_502), .B1(op2[1]), .B2(n_0_495), .ZN(n_0_494)); + AOI21_X1_LVT i_0_521 (.A(n_0_577), .B1(n_0_701), .B2(n_0_494), .ZN(n_0_493)); + NOR2_X1_LVT i_0_520 (.A1(n_0_499), .A2(n_0_493), .ZN(n_0_492)); + AOI21_X1_LVT i_0_519 (.A(n_0_492), .B1(op2[0]), .B2(n_0_511), .ZN(n_0_491)); + AOI22_X1_LVT i_0_518 (.A1(n_0_688), .A2(n_0_565), .B1(op1[27]), .B2(n_0_566), + .ZN(n_0_490)); + AOI211_X1_LVT i_0_513 (.A(n_0_486), .B(n_0_491), .C1(op2[27]), .C2(n_0_490), + .ZN(n_0_485)); + NOR3_X1_LVT i_0_536 (.A1(op2[4]), .A2(n_0_696), .A3(n_0_723), .ZN(n_0_508)); + AOI21_X1_LVT i_0_535 (.A(n_0_508), .B1(n_0_723), .B2(n_0_591), .ZN(n_0_507)); + OAI22_X1_LVT i_0_534 (.A1(op2[2]), .A2(n_0_592), .B1(n_0_693), .B2(n_0_507), + .ZN(n_0_506)); + NOR2_X1_LVT i_0_533 (.A1(n_0_728), .A2(n_0_506), .ZN(n_0_505)); + AOI21_X1_LVT i_0_532 (.A(n_0_505), .B1(n_0_728), .B2(n_0_536), .ZN(n_0_504)); + OAI22_X1_LVT i_0_531 (.A1(n_0_701), .A2(n_0_504), .B1(op2[0]), .B2(n_0_519), + .ZN(n_0_503)); + OAI21_X1_LVT i_0_512 (.A(n_0_485), .B1(n_0_621), .B2(n_0_503), .ZN(result[27])); + OAI21_X1_LVT i_0_500 (.A(n_0_681), .B1(op2[26]), .B2(n_0_568), .ZN(n_0_473)); + NAND2_X1_LVT i_0_499 (.A1(op1[26]), .A2(n_0_473), .ZN(n_0_472)); + XNOR2_X1_LVT i_10_133 (.A(n_10_103), .B(n_10_106), .ZN(n_58)); + AOI22_X1_LVT i_0_498 (.A1(n_58), .A2(n_0_580), .B1(n_26), .B2(n_0_581), + .ZN(n_0_471)); + INV_X1_LVT i_0_744 (.A(op1[26]), .ZN(n_0_711)); + OAI221_X1_LVT i_0_501 (.A(op2[26]), .B1(op1[26]), .B2(n_0_564), .C1(n_0_711), + .C2(n_0_567), .ZN(n_0_474)); + NAND3_X1_LVT i_0_497 (.A1(n_0_472), .A2(n_0_471), .A3(n_0_474), .ZN(n_0_470)); + INV_X1_LVT i_0_524 (.A(n_0_497), .ZN(n_0_496)); + AOI22_X1_LVT i_0_505 (.A1(op1[30]), .A2(n_0_496), .B1(op1[26]), .B2(n_0_573), + .ZN(n_0_478)); + NOR2_X1_LVT i_0_504 (.A1(op2[1]), .A2(n_0_478), .ZN(n_0_477)); + AOI21_X1_LVT i_0_503 (.A(n_0_477), .B1(op1[28]), .B2(n_0_530), .ZN(n_0_476)); + NAND2_X1_LVT i_0_502 (.A1(n_0_701), .A2(n_0_476), .ZN(n_0_475)); + AOI21_X1_LVT i_0_489 (.A(n_0_577), .B1(op2[0]), .B2(n_0_494), .ZN(n_0_462)); + AOI21_X1_LVT i_0_488 (.A(n_0_470), .B1(n_0_475), .B2(n_0_462), .ZN(n_0_461)); + AOI21_X1_LVT i_0_511 (.A(n_0_616), .B1(n_0_738), .B2(n_0_706), .ZN(n_0_484)); + AOI21_X1_LVT i_0_510 (.A(n_0_484), .B1(n_0_723), .B2(op1[19]), .ZN(n_0_483)); + INV_X1_LVT i_0_757 (.A(op1[3]), .ZN(n_0_724)); + NOR2_X1_LVT i_0_687 (.A1(n_0_724), .A2(op2[3]), .ZN(n_0_654)); + INV_X1_LVT i_0_686 (.A(n_0_654), .ZN(n_0_653)); + AOI21_X1_LVT i_0_509 (.A(n_0_483), .B1(op2[4]), .B2(n_0_653), .ZN(n_0_482)); + AOI22_X1_LVT i_0_508 (.A1(n_0_693), .A2(n_0_554), .B1(op2[2]), .B2(n_0_482), + .ZN(n_0_481)); + OAI22_X1_LVT i_0_507 (.A1(n_0_728), .A2(n_0_481), .B1(op2[1]), .B2(n_0_520), + .ZN(n_0_480)); + AOI22_X1_LVT i_0_506 (.A1(op2[0]), .A2(n_0_480), .B1(n_0_701), .B2(n_0_504), + .ZN(n_0_479)); + NAND3_X1_LVT i_0_491 (.A1(op2[0]), .A2(n_0_516), .A3(n_0_500), .ZN(n_0_464)); + NAND2_X1_LVT i_0_494 (.A1(op1[31]), .A2(n_0_615), .ZN(n_0_467)); + OAI21_X1_LVT i_0_492 (.A(n_0_467), .B1(n_0_728), .B2(n_0_516), .ZN(n_0_465)); + OAI21_X1_LVT i_0_490 (.A(n_0_464), .B1(n_0_475), .B2(n_0_465), .ZN(n_0_463)); + OAI221_X1_LVT i_0_487 (.A(n_0_461), .B1(n_0_621), .B2(n_0_479), .C1(n_0_545), + .C2(n_0_463), .ZN(result[26])); + INV_X1_LVT i_10_126 (.A(n_10_100), .ZN(n_10_101)); + NOR2_X1_LVT i_10_127 (.A1(n_10_99), .A2(n_10_101), .ZN(n_10_102)); + XNOR2_X1_LVT i_10_128 (.A(n_10_97), .B(n_10_102), .ZN(n_57)); + AOI22_X1_LVT i_0_479 (.A1(n_57), .A2(n_0_580), .B1(n_25), .B2(n_0_581), + .ZN(n_0_453)); + INV_X1_LVT i_0_730 (.A(op2[25]), .ZN(n_0_697)); + AOI21_X1_LVT i_0_478 (.A(aluBypass), .B1(n_0_697), .B2(n_0_569), .ZN(n_0_452)); + AOI22_X1_LVT i_0_480 (.A1(op1[25]), .A2(n_0_567), .B1(n_0_699), .B2(n_0_564), + .ZN(n_0_454)); + OAI221_X1_LVT i_0_477 (.A(n_0_453), .B1(n_0_699), .B2(n_0_452), .C1(n_0_697), + .C2(n_0_454), .ZN(n_0_451)); + INV_X1_LVT i_0_575 (.A(n_0_545), .ZN(n_0_544)); + AOI21_X1_LVT i_0_476 (.A(n_0_451), .B1(n_0_544), .B2(n_0_465), .ZN(n_0_450)); + AOI22_X1_LVT i_0_475 (.A1(op1[29]), .A2(n_0_496), .B1(op1[25]), .B2(n_0_573), + .ZN(n_0_449)); + NAND2_X1_LVT i_0_474 (.A1(n_0_728), .A2(n_0_449), .ZN(n_0_448)); + OAI21_X1_LVT i_0_473 (.A(n_0_448), .B1(n_0_728), .B2(n_0_495), .ZN(n_0_447)); + OAI22_X1_LVT i_0_472 (.A1(n_0_548), .A2(n_0_476), .B1(n_0_562), .B2(n_0_447), + .ZN(n_0_446)); + INV_X1_LVT i_0_471 (.A(n_0_446), .ZN(n_0_445)); + OAI222_X1_LVT i_0_486 (.A1(n_0_733), .A2(n_0_617), .B1(n_0_694), .B2(n_0_605), + .C1(n_0_705), .C2(n_0_615), .ZN(n_0_460)); + NOR2_X1_LVT i_0_485 (.A1(n_0_693), .A2(n_0_460), .ZN(n_0_459)); + AOI21_X1_LVT i_0_484 (.A(n_0_459), .B1(n_0_693), .B2(n_0_538), .ZN(n_0_458)); + OAI22_X1_LVT i_0_483 (.A1(n_0_728), .A2(n_0_458), .B1(op2[1]), .B2(n_0_506), + .ZN(n_0_457)); + INV_X1_LVT i_0_482 (.A(n_0_457), .ZN(n_0_456)); + OAI221_X1_LVT i_0_481 (.A(n_0_620), .B1(n_0_701), .B2(n_0_456), .C1(op2[0]), + .C2(n_0_480), .ZN(n_0_455)); + NAND3_X1_LVT i_0_470 (.A1(n_0_450), .A2(n_0_445), .A3(n_0_455), .ZN( + result[25])); + INV_X1_LVT i_0_493 (.A(n_0_467), .ZN(n_0_466)); + OAI211_X1_LVT i_0_455 (.A(n_0_544), .B(n_0_465), .C1(op2[0]), .C2(n_0_466), + .ZN(n_0_430)); + OAI21_X1_LVT i_0_462 (.A(n_0_681), .B1(op2[24]), .B2(n_0_568), .ZN(n_0_437)); + XNOR2_X1_LVT i_10_120 (.A(n_10_94), .B(n_10_95), .ZN(n_56)); + AOI222_X1_LVT i_0_461 (.A1(op1[24]), .A2(n_0_437), .B1(n_56), .B2(n_0_580), + .C1(n_24), .C2(n_0_581), .ZN(n_0_436)); + INV_X1_LVT i_0_460 (.A(n_0_436), .ZN(n_0_435)); + AOI22_X1_LVT i_0_458 (.A1(op1[24]), .A2(n_0_573), .B1(op1[28]), .B2(n_0_496), + .ZN(n_0_433)); + OAI22_X1_LVT i_0_457 (.A1(op2[1]), .A2(n_0_433), .B1(n_0_728), .B2(n_0_478), + .ZN(n_0_432)); + INV_X1_LVT i_0_456 (.A(n_0_432), .ZN(n_0_431)); + OAI22_X1_LVT i_0_454 (.A1(n_0_562), .A2(n_0_431), .B1(n_0_548), .B2(n_0_447), + .ZN(n_0_429)); + AOI22_X1_LVT i_0_459 (.A1(n_0_736), .A2(n_0_565), .B1(op1[24]), .B2(n_0_566), + .ZN(n_0_434)); + AOI211_X1_LVT i_0_453 (.A(n_0_435), .B(n_0_429), .C1(op2[24]), .C2(n_0_434), + .ZN(n_0_428)); + NAND2_X1_LVT i_0_467 (.A1(n_0_693), .A2(n_0_521), .ZN(n_0_442)); + NOR2_X1_LVT i_0_469 (.A1(op2[3]), .A2(n_0_603), .ZN(n_0_444)); + AOI21_X1_LVT i_0_468 (.A(n_0_444), .B1(op1[9]), .B2(n_0_618), .ZN(n_0_443)); + OAI21_X1_LVT i_0_466 (.A(n_0_442), .B1(n_0_693), .B2(n_0_443), .ZN(n_0_441)); + NAND2_X1_LVT i_0_465 (.A1(op2[1]), .A2(n_0_441), .ZN(n_0_440)); + OAI21_X1_LVT i_0_464 (.A(n_0_440), .B1(op2[1]), .B2(n_0_481), .ZN(n_0_439)); + OAI221_X1_LVT i_0_463 (.A(n_0_620), .B1(op2[0]), .B2(n_0_456), .C1(n_0_701), + .C2(n_0_439), .ZN(n_0_438)); + NAND3_X1_LVT i_0_452 (.A1(n_0_430), .A2(n_0_428), .A3(n_0_438), .ZN( + result[24])); + INV_X1_LVT i_0_751 (.A(op2[23]), .ZN(n_0_718)); + AOI221_X1_LVT i_0_440 (.A(n_0_718), .B1(op1[23]), .B2(n_0_566), .C1(n_0_719), + .C2(n_0_565), .ZN(n_0_416)); + INV_X1_LVT i_10_115 (.A(n_10_91), .ZN(n_10_92)); + NOR2_X1_LVT i_10_116 (.A1(n_10_90), .A2(n_10_92), .ZN(n_10_93)); + XNOR2_X1_LVT i_10_117 (.A(n_10_88), .B(n_10_93), .ZN(n_55)); + AOI222_X1_LVT i_0_438 (.A1(n_23), .A2(n_0_581), .B1(n_0_544), .B2(n_0_466), + .C1(n_55), .C2(n_0_580), .ZN(n_0_414)); + OAI21_X1_LVT i_0_437 (.A(n_0_414), .B1(n_0_548), .B2(n_0_431), .ZN(n_0_413)); + OAI21_X1_LVT i_0_439 (.A(n_0_681), .B1(op2[23]), .B2(n_0_568), .ZN(n_0_415)); + AOI211_X1_LVT i_0_436 (.A(n_0_416), .B(n_0_413), .C1(op1[23]), .C2(n_0_415), + .ZN(n_0_412)); + AOI22_X1_LVT i_0_444 (.A1(n_0_723), .A2(n_0_719), .B1(op2[3]), .B2(n_0_691), + .ZN(n_0_420)); + AOI22_X1_LVT i_0_443 (.A1(n_0_575), .A2(n_0_420), .B1(op1[27]), .B2(n_0_496), + .ZN(n_0_419)); + AOI22_X1_LVT i_0_442 (.A1(op2[1]), .A2(n_0_449), .B1(n_0_728), .B2(n_0_419), + .ZN(n_0_418)); + INV_X1_LVT i_0_441 (.A(n_0_418), .ZN(n_0_417)); + NAND2_X1_LVT i_0_447 (.A1(n_0_728), .A2(n_0_458), .ZN(n_0_423)); + NOR2_X1_LVT i_0_451 (.A1(op2[3]), .A2(n_0_594), .ZN(n_0_427)); + AOI21_X1_LVT i_0_450 (.A(n_0_427), .B1(op1[8]), .B2(n_0_618), .ZN(n_0_426)); + OAI22_X1_LVT i_0_449 (.A1(n_0_693), .A2(n_0_426), .B1(op2[2]), .B2(n_0_507), + .ZN(n_0_425)); + INV_X1_LVT i_0_448 (.A(n_0_425), .ZN(n_0_424)); + OAI21_X1_LVT i_0_446 (.A(n_0_423), .B1(n_0_728), .B2(n_0_424), .ZN(n_0_422)); + AOI22_X1_LVT i_0_445 (.A1(op2[0]), .A2(n_0_422), .B1(n_0_701), .B2(n_0_439), + .ZN(n_0_421)); + OAI221_X1_LVT i_0_435 (.A(n_0_412), .B1(n_0_562), .B2(n_0_417), .C1(n_0_621), + .C2(n_0_421), .ZN(result[23])); + XNOR2_X1_LVT i_10_109 (.A(n_10_85), .B(n_10_86), .ZN(n_54)); + AOI22_X1_LVT i_0_419 (.A1(n_54), .A2(n_0_580), .B1(n_22), .B2(n_0_581), + .ZN(n_0_396)); + INV_X1_LVT i_0_719 (.A(op2[22]), .ZN(n_0_686)); + AOI21_X1_LVT i_0_420 (.A(aluBypass), .B1(n_0_686), .B2(n_0_569), .ZN(n_0_397)); + OAI21_X1_LVT i_0_418 (.A(n_0_396), .B1(n_0_687), .B2(n_0_397), .ZN(n_0_395)); + AOI22_X1_LVT i_0_421 (.A1(op1[22]), .A2(n_0_566), .B1(n_0_687), .B2(n_0_565), + .ZN(n_0_398)); + AOI21_X1_LVT i_0_417 (.A(n_0_395), .B1(op2[22]), .B2(n_0_398), .ZN(n_0_394)); + NAND2_X1_LVT i_0_432 (.A1(n_0_728), .A2(n_0_441), .ZN(n_0_409)); + AND2_X1_LVT i_0_434 (.A1(n_0_738), .A2(n_0_619), .ZN(n_0_411)); + AOI22_X1_LVT i_0_433 (.A1(n_0_693), .A2(n_0_482), .B1(op2[2]), .B2(n_0_411), + .ZN(n_0_410)); + OAI21_X1_LVT i_0_431 (.A(n_0_409), .B1(n_0_728), .B2(n_0_410), .ZN(n_0_408)); + OAI22_X1_LVT i_0_430 (.A1(n_0_701), .A2(n_0_408), .B1(op2[0]), .B2(n_0_422), + .ZN(n_0_407)); + AOI22_X1_LVT i_0_429 (.A1(n_0_723), .A2(n_0_687), .B1(op2[3]), .B2(n_0_717), + .ZN(n_0_406)); + AOI22_X1_LVT i_0_428 (.A1(n_0_575), .A2(n_0_406), .B1(op1[26]), .B2(n_0_496), + .ZN(n_0_405)); + AND2_X1_LVT i_0_427 (.A1(n_0_728), .A2(n_0_405), .ZN(n_0_404)); + AOI21_X1_LVT i_0_426 (.A(n_0_404), .B1(op2[1]), .B2(n_0_433), .ZN(n_0_403)); + INV_X1_LVT i_0_425 (.A(n_0_403), .ZN(n_0_402)); + OAI222_X1_LVT i_0_424 (.A1(n_0_545), .A2(n_0_467), .B1(n_0_701), .B2(n_0_417), + .C1(op2[0]), .C2(n_0_402), .ZN(n_0_401)); + NOR2_X1_LVT i_0_496 (.A1(n_0_738), .A2(n_0_691), .ZN(n_0_469)); + INV_X1_LVT i_0_495 (.A(n_0_469), .ZN(n_0_468)); + NAND3_X1_LVT i_0_423 (.A1(n_0_693), .A2(n_0_468), .A3(n_0_404), .ZN(n_0_400)); + OAI21_X1_LVT i_0_422 (.A(n_0_401), .B1(op2[0]), .B2(n_0_400), .ZN(n_0_399)); + OAI221_X1_LVT i_0_416 (.A(n_0_394), .B1(n_0_621), .B2(n_0_407), .C1(n_0_579), + .C2(n_0_399), .ZN(result[22])); + INV_X1_LVT i_0_759 (.A(op1[21]), .ZN(n_0_726)); + AOI22_X1_LVT i_0_399 (.A1(op1[21]), .A2(n_0_566), .B1(n_0_726), .B2(n_0_565), + .ZN(n_0_377)); + NOR2_X1_LVT i_0_692 (.A1(n_0_726), .A2(op2[21]), .ZN(n_0_659)); + AOI222_X1_LVT i_0_398 (.A1(op2[21]), .A2(n_0_377), .B1(n_21), .B2(n_0_581), + .C1(n_0_659), .C2(n_0_569), .ZN(n_0_376)); + INV_X1_LVT i_0_397 (.A(n_0_376), .ZN(n_0_375)); + INV_X1_LVT i_10_104 (.A(n_10_82), .ZN(n_10_83)); + NOR2_X1_LVT i_10_105 (.A1(n_10_81), .A2(n_10_83), .ZN(n_10_84)); + XNOR2_X1_LVT i_10_106 (.A(n_10_79), .B(n_10_84), .ZN(n_53)); + AOI221_X1_LVT i_0_396 (.A(n_0_375), .B1(n_53), .B2(n_0_580), .C1(op1[21]), + .C2(aluBypass), .ZN(n_0_374)); + INV_X1_LVT i_0_608 (.A(n_0_577), .ZN(n_0_576)); + NAND2_X1_LVT i_0_403 (.A1(op2[0]), .A2(n_0_402), .ZN(n_0_381)); + AND2_X1_LVT i_0_410 (.A1(op2[1]), .A2(n_0_419), .ZN(n_0_388)); + OAI22_X1_LVT i_0_408 (.A1(n_0_723), .A2(n_0_710), .B1(n_0_726), .B2(op2[3]), + .ZN(n_0_386)); + AOI22_X1_LVT i_0_407 (.A1(n_0_575), .A2(n_0_386), .B1(op1[25]), .B2(n_0_496), + .ZN(n_0_385)); + AOI21_X1_LVT i_0_395 (.A(n_0_388), .B1(n_0_728), .B2(n_0_385), .ZN(n_0_373)); + OAI211_X1_LVT i_0_394 (.A(n_0_576), .B(n_0_381), .C1(op2[0]), .C2(n_0_373), + .ZN(n_0_372)); + AOI21_X1_LVT i_0_402 (.A(n_0_381), .B1(n_0_466), .B2(n_0_400), .ZN(n_0_380)); + INV_X1_LVT i_0_401 (.A(n_0_380), .ZN(n_0_379)); + NOR2_X1_LVT i_0_409 (.A1(n_0_575), .A2(n_0_467), .ZN(n_0_387)); + INV_X1_LVT i_0_406 (.A(n_0_385), .ZN(n_0_384)); + NOR2_X1_LVT i_0_405 (.A1(n_0_387), .A2(n_0_384), .ZN(n_0_383)); + AOI22_X1_LVT i_0_404 (.A1(n_0_467), .A2(n_0_388), .B1(n_0_728), .B2(n_0_383), + .ZN(n_0_382)); + OAI211_X1_LVT i_0_400 (.A(n_0_544), .B(n_0_379), .C1(op2[0]), .C2(n_0_382), + .ZN(n_0_378)); + AOI22_X1_LVT i_0_415 (.A1(op1[14]), .A2(n_0_616), .B1(op1[6]), .B2(n_0_618), + .ZN(n_0_393)); + NOR2_X1_LVT i_0_414 (.A1(n_0_693), .A2(n_0_393), .ZN(n_0_392)); + AOI21_X1_LVT i_0_413 (.A(n_0_392), .B1(n_0_693), .B2(n_0_460), .ZN(n_0_391)); + OAI22_X1_LVT i_0_412 (.A1(n_0_728), .A2(n_0_391), .B1(op2[1]), .B2(n_0_424), + .ZN(n_0_390)); + OAI221_X1_LVT i_0_411 (.A(n_0_620), .B1(op2[0]), .B2(n_0_408), .C1(n_0_701), + .C2(n_0_390), .ZN(n_0_389)); + NAND4_X1_LVT i_0_393 (.A1(n_0_374), .A2(n_0_372), .A3(n_0_378), .A4(n_0_389), + .ZN(result[21])); + OAI221_X1_LVT i_0_388 (.A(op2[20]), .B1(n_0_727), .B2(n_0_567), .C1(op1[20]), + .C2(n_0_564), .ZN(n_0_367)); + NOR2_X1_LVT i_0_691 (.A1(n_0_727), .A2(op2[20]), .ZN(n_0_658)); + AOI22_X1_LVT i_0_387 (.A1(op1[20]), .A2(aluBypass), .B1(n_0_658), .B2(n_0_569), + .ZN(n_0_366)); + XNOR2_X1_LVT i_10_98 (.A(n_10_76), .B(n_10_77), .ZN(n_52)); + AOI22_X1_LVT i_0_386 (.A1(n_52), .A2(n_0_580), .B1(n_20), .B2(n_0_581), + .ZN(n_0_365)); + AOI221_X1_LVT i_0_392 (.A(op2[4]), .B1(n_0_727), .B2(n_0_723), .C1(op2[3]), + .C2(n_0_698), .ZN(n_0_371)); + AOI22_X1_LVT i_0_391 (.A1(op1[24]), .A2(n_0_496), .B1(n_0_693), .B2(n_0_371), + .ZN(n_0_370)); + OAI22_X1_LVT i_0_390 (.A1(op2[1]), .A2(n_0_370), .B1(n_0_728), .B2(n_0_405), + .ZN(n_0_369)); + OAI221_X1_LVT i_0_385 (.A(n_0_576), .B1(n_0_701), .B2(n_0_373), .C1(op2[0]), + .C2(n_0_369), .ZN(n_0_364)); + AND4_X1_LVT i_0_384 (.A1(n_0_367), .A2(n_0_366), .A3(n_0_365), .A4(n_0_364), + .ZN(n_0_363)); + AOI22_X1_LVT i_0_383 (.A1(op1[13]), .A2(n_0_616), .B1(op1[5]), .B2(n_0_618), + .ZN(n_0_362)); + AOI22_X1_LVT i_0_382 (.A1(op2[2]), .A2(n_0_362), .B1(n_0_693), .B2(n_0_443), + .ZN(n_0_361)); + NAND2_X1_LVT i_0_381 (.A1(op2[1]), .A2(n_0_361), .ZN(n_0_360)); + OAI21_X1_LVT i_0_380 (.A(n_0_360), .B1(op2[1]), .B2(n_0_410), .ZN(n_0_359)); + OAI221_X1_LVT i_0_379 (.A(n_0_620), .B1(n_0_701), .B2(n_0_359), .C1(op2[0]), + .C2(n_0_390), .ZN(n_0_358)); + OR2_X1_LVT i_0_389 (.A1(n_0_387), .A2(n_0_369), .ZN(n_0_368)); + AOI22_X1_LVT i_0_378 (.A1(op2[0]), .A2(n_0_382), .B1(n_0_701), .B2(n_0_368), + .ZN(n_0_357)); + OAI211_X1_LVT i_0_377 (.A(n_0_363), .B(n_0_358), .C1(n_0_545), .C2(n_0_357), + .ZN(result[20])); + OAI22_X1_LVT i_0_370 (.A1(op2[3]), .A2(n_0_689), .B1(n_0_723), .B2(n_0_688), + .ZN(n_0_350)); + AND2_X1_LVT i_0_369 (.A1(n_0_738), .A2(n_0_350), .ZN(n_0_349)); + AOI22_X1_LVT i_0_368 (.A1(n_0_498), .A2(n_0_420), .B1(n_0_693), .B2(n_0_349), + .ZN(n_0_348)); + AND2_X1_LVT i_0_367 (.A1(n_0_728), .A2(n_0_348), .ZN(n_0_347)); + AOI21_X1_LVT i_0_359 (.A(n_0_347), .B1(op2[1]), .B2(n_0_385), .ZN(n_0_339)); + OAI221_X1_LVT i_0_357 (.A(n_0_576), .B1(n_0_701), .B2(n_0_369), .C1(op2[0]), + .C2(n_0_339), .ZN(n_0_337)); + NAND2_X1_LVT i_0_363 (.A1(n_19), .A2(n_0_581), .ZN(n_0_343)); + INV_X1_LVT i_0_723 (.A(op2[19]), .ZN(n_0_690)); + AOI221_X1_LVT i_0_364 (.A(n_0_690), .B1(n_0_689), .B2(n_0_565), .C1(op1[19]), + .C2(n_0_566), .ZN(n_0_344)); + XNOR2_X1_LVT i_10_94 (.A(n_10_73), .B(n_10_74), .ZN(n_51)); + AOI221_X1_LVT i_0_361 (.A(n_0_344), .B1(op1[19]), .B2(aluBypass), .C1(n_51), + .C2(n_0_580), .ZN(n_0_341)); + NAND3_X1_LVT i_0_362 (.A1(n_0_690), .A2(op1[19]), .A3(n_0_569), .ZN(n_0_342)); + NAND3_X1_LVT i_0_360 (.A1(n_0_343), .A2(n_0_341), .A3(n_0_342), .ZN(n_0_340)); + AOI22_X1_LVT i_0_376 (.A1(op1[12]), .A2(n_0_616), .B1(op1[4]), .B2(n_0_618), + .ZN(n_0_356)); + OAI22_X1_LVT i_0_375 (.A1(n_0_693), .A2(n_0_356), .B1(op2[2]), .B2(n_0_426), + .ZN(n_0_355)); + INV_X1_LVT i_0_374 (.A(n_0_355), .ZN(n_0_354)); + OAI22_X1_LVT i_0_373 (.A1(op2[1]), .A2(n_0_391), .B1(n_0_728), .B2(n_0_354), + .ZN(n_0_353)); + AOI22_X1_LVT i_0_372 (.A1(n_0_701), .A2(n_0_359), .B1(op2[0]), .B2(n_0_353), + .ZN(n_0_352)); + INV_X1_LVT i_0_371 (.A(n_0_352), .ZN(n_0_351)); + AOI21_X1_LVT i_0_358 (.A(n_0_340), .B1(n_0_620), .B2(n_0_351), .ZN(n_0_338)); + AOI22_X1_LVT i_0_366 (.A1(n_0_468), .A2(n_0_347), .B1(op2[1]), .B2(n_0_383), + .ZN(n_0_346)); + AOI22_X1_LVT i_0_365 (.A1(n_0_701), .A2(n_0_346), .B1(op2[0]), .B2(n_0_368), + .ZN(n_0_345)); + OAI211_X1_LVT i_0_356 (.A(n_0_337), .B(n_0_338), .C1(n_0_545), .C2(n_0_345), + .ZN(result[19])); + XNOR2_X1_LVT i_10_90 (.A(n_10_70), .B(n_10_71), .ZN(n_50)); + NAND2_X1_LVT i_0_342 (.A1(n_50), .A2(n_0_580), .ZN(n_0_323)); + OAI21_X1_LVT i_0_343 (.A(n_0_681), .B1(op2[18]), .B2(n_0_568), .ZN(n_0_324)); + AOI22_X1_LVT i_0_341 (.A1(op1[18]), .A2(n_0_324), .B1(n_18), .B2(n_0_581), + .ZN(n_0_322)); + OAI221_X1_LVT i_0_340 (.A(op2[18]), .B1(n_0_705), .B2(n_0_567), .C1(op1[18]), + .C2(n_0_564), .ZN(n_0_321)); + NAND3_X1_LVT i_0_339 (.A1(n_0_323), .A2(n_0_322), .A3(n_0_321), .ZN(n_0_320)); + OAI22_X1_LVT i_0_351 (.A1(op2[3]), .A2(n_0_705), .B1(n_0_723), .B2(n_0_711), + .ZN(n_0_332)); + AND2_X1_LVT i_0_350 (.A1(n_0_738), .A2(n_0_332), .ZN(n_0_331)); + AOI22_X1_LVT i_0_349 (.A1(n_0_498), .A2(n_0_406), .B1(n_0_693), .B2(n_0_331), + .ZN(n_0_330)); + NAND2_X1_LVT i_0_348 (.A1(n_0_728), .A2(n_0_330), .ZN(n_0_329)); + NAND2_X1_LVT i_0_347 (.A1(op2[1]), .A2(n_0_370), .ZN(n_0_328)); + AND2_X1_LVT i_0_338 (.A1(n_0_329), .A2(n_0_328), .ZN(n_0_319)); + OAI22_X1_LVT i_0_337 (.A1(op2[0]), .A2(n_0_319), .B1(n_0_701), .B2(n_0_339), + .ZN(n_0_318)); + INV_X1_LVT i_0_336 (.A(n_0_318), .ZN(n_0_317)); + AOI21_X1_LVT i_0_335 (.A(n_0_320), .B1(n_0_578), .B2(n_0_317), .ZN(n_0_316)); + OAI22_X1_LVT i_0_346 (.A1(n_0_469), .A2(n_0_329), .B1(n_0_387), .B2(n_0_328), + .ZN(n_0_327)); + NAND2_X1_LVT i_0_344 (.A1(n_0_544), .A2(n_0_346), .ZN(n_0_325)); + NAND2_X1_LVT i_0_354 (.A1(n_0_728), .A2(n_0_361), .ZN(n_0_335)); + AOI22_X1_LVT i_0_355 (.A1(n_0_612), .A2(n_0_498), .B1(n_0_693), .B2(n_0_411), + .ZN(n_0_336)); + OAI21_X1_LVT i_0_353 (.A(n_0_335), .B1(n_0_728), .B2(n_0_336), .ZN(n_0_334)); + AOI22_X1_LVT i_0_352 (.A1(n_0_701), .A2(n_0_353), .B1(op2[0]), .B2(n_0_334), + .ZN(n_0_333)); + OAI221_X1_LVT i_0_334 (.A(n_0_316), .B1(n_0_327), .B2(n_0_325), .C1(n_0_621), + .C2(n_0_333), .ZN(result[18])); + NAND2_X1_LVT i_0_325 (.A1(n_17), .A2(n_0_581), .ZN(n_0_307)); + INV_X1_LVT i_0_765 (.A(op1[17]), .ZN(n_0_732)); + AOI22_X1_LVT i_0_324 (.A1(n_0_732), .A2(n_0_565), .B1(op1[17]), .B2(n_0_566), + .ZN(n_0_306)); + NOR2_X1_LVT i_0_693 (.A1(n_0_732), .A2(op2[17]), .ZN(n_0_660)); + XNOR2_X1_LVT i_10_86 (.A(n_10_67), .B(n_10_68), .ZN(n_49)); + AOI222_X1_LVT i_0_323 (.A1(op2[17]), .A2(n_0_306), .B1(n_0_660), .B2(n_0_569), + .C1(n_49), .C2(n_0_580), .ZN(n_0_305)); + OAI211_X1_LVT i_0_322 (.A(n_0_307), .B(n_0_305), .C1(n_0_732), .C2(n_0_681), + .ZN(n_0_304)); + AOI22_X1_LVT i_0_331 (.A1(op2[3]), .A2(op1[25]), .B1(op1[17]), .B2(n_0_723), + .ZN(n_0_313)); + NOR2_X1_LVT i_0_330 (.A1(op2[4]), .A2(n_0_313), .ZN(n_0_312)); + AOI22_X1_LVT i_0_329 (.A1(n_0_498), .A2(n_0_386), .B1(n_0_693), .B2(n_0_312), + .ZN(n_0_311)); + OAI22_X1_LVT i_0_328 (.A1(op2[1]), .A2(n_0_311), .B1(n_0_728), .B2(n_0_348), + .ZN(n_0_310)); + OR2_X1_LVT i_0_327 (.A1(op2[0]), .A2(n_0_310), .ZN(n_0_309)); + OAI21_X1_LVT i_0_321 (.A(n_0_576), .B1(n_0_701), .B2(n_0_319), .ZN(n_0_303)); + INV_X1_LVT i_0_320 (.A(n_0_303), .ZN(n_0_302)); + AOI21_X1_LVT i_0_319 (.A(n_0_304), .B1(n_0_309), .B2(n_0_302), .ZN(n_0_301)); + INV_X1_LVT i_0_345 (.A(n_0_327), .ZN(n_0_326)); + OAI22_X1_LVT i_0_326 (.A1(n_0_701), .A2(n_0_326), .B1(n_0_469), .B2(n_0_309), + .ZN(n_0_308)); + NOR2_X1_LVT i_0_318 (.A1(op2[2]), .A2(n_0_393), .ZN(n_0_300)); + AOI21_X1_LVT i_0_317 (.A(n_0_300), .B1(n_0_597), .B2(n_0_498), .ZN(n_0_299)); + OAI22_X1_LVT i_0_316 (.A1(n_0_728), .A2(n_0_299), .B1(op2[1]), .B2(n_0_354), + .ZN(n_0_298)); + OAI22_X1_LVT i_0_315 (.A1(op2[0]), .A2(n_0_334), .B1(n_0_701), .B2(n_0_298), + .ZN(n_0_297)); + OAI221_X1_LVT i_0_314 (.A(n_0_301), .B1(n_0_545), .B2(n_0_308), .C1(n_0_621), + .C2(n_0_297), .ZN(result[17])); + XNOR2_X1_LVT i_10_82 (.A(n_10_64), .B(n_10_65), .ZN(n_48)); + AOI22_X1_LVT i_0_301 (.A1(n_48), .A2(n_0_580), .B1(n_16), .B2(n_0_581), + .ZN(n_0_284)); + NAND2_X1_LVT i_0_333 (.A1(n_0_544), .A2(n_0_469), .ZN(n_0_315)); + INV_X1_LVT i_0_332 (.A(n_0_315), .ZN(n_0_314)); + OAI21_X1_LVT i_0_302 (.A(n_0_681), .B1(op2[16]), .B2(n_0_568), .ZN(n_0_285)); + AOI21_X1_LVT i_0_300 (.A(n_0_314), .B1(op1[16]), .B2(n_0_285), .ZN(n_0_283)); + INV_X1_LVT i_0_772 (.A(op1[16]), .ZN(n_0_739)); + OAI221_X1_LVT i_0_303 (.A(op2[16]), .B1(op1[16]), .B2(n_0_564), .C1(n_0_739), + .C2(n_0_567), .ZN(n_0_286)); + NAND3_X1_LVT i_0_299 (.A1(n_0_284), .A2(n_0_283), .A3(n_0_286), .ZN(n_0_282)); + INV_X1_LVT i_0_593 (.A(n_0_562), .ZN(n_0_561)); + OAI22_X1_LVT i_0_307 (.A1(op1[16]), .A2(op2[3]), .B1(op1[24]), .B2(n_0_723), + .ZN(n_0_290)); + NOR2_X1_LVT i_0_306 (.A1(op2[4]), .A2(n_0_290), .ZN(n_0_289)); + AOI22_X1_LVT i_0_305 (.A1(n_0_693), .A2(n_0_289), .B1(op2[2]), .B2(n_0_371), + .ZN(n_0_288)); + OAI22_X1_LVT i_0_304 (.A1(n_0_728), .A2(n_0_330), .B1(op2[1]), .B2(n_0_288), + .ZN(n_0_287)); + AOI221_X1_LVT i_0_298 (.A(n_0_282), .B1(n_0_547), .B2(n_0_310), .C1(n_0_561), + .C2(n_0_287), .ZN(n_0_281)); + INV_X1_LVT i_0_762 (.A(op1[1]), .ZN(n_0_729)); + OAI22_X1_LVT i_0_313 (.A1(n_0_722), .A2(n_0_615), .B1(n_0_729), .B2(n_0_617), + .ZN(n_0_296)); + NAND2_X1_LVT i_0_312 (.A1(op2[2]), .A2(n_0_296), .ZN(n_0_295)); + OAI21_X1_LVT i_0_311 (.A(n_0_295), .B1(op2[2]), .B2(n_0_362), .ZN(n_0_294)); + NAND2_X1_LVT i_0_310 (.A1(op2[1]), .A2(n_0_294), .ZN(n_0_293)); + OAI21_X1_LVT i_0_309 (.A(n_0_293), .B1(op2[1]), .B2(n_0_336), .ZN(n_0_292)); + OAI22_X1_LVT i_0_308 (.A1(op2[0]), .A2(n_0_298), .B1(n_0_701), .B2(n_0_292), + .ZN(n_0_291)); + OAI21_X1_LVT i_0_297 (.A(n_0_281), .B1(n_0_621), .B2(n_0_291), .ZN(result[16])); + OAI221_X1_LVT i_0_286 (.A(op2[15]), .B1(n_0_734), .B2(n_0_567), .C1(op1[15]), + .C2(n_0_564), .ZN(n_0_270)); + AOI21_X1_LVT i_0_288 (.A(n_0_314), .B1(n_15), .B2(n_0_581), .ZN(n_0_272)); + INV_X1_LVT i_0_287 (.A(n_0_272), .ZN(n_0_271)); + XNOR2_X1_LVT i_10_78 (.A(n_10_61), .B(n_10_62), .ZN(n_47)); + OAI21_X1_LVT i_0_285 (.A(n_0_681), .B1(op2[15]), .B2(n_0_568), .ZN(n_0_269)); + AOI221_X1_LVT i_0_284 (.A(n_0_271), .B1(n_47), .B2(n_0_580), .C1(op1[15]), + .C2(n_0_269), .ZN(n_0_268)); + AOI22_X1_LVT i_0_296 (.A1(op1[8]), .A2(n_0_616), .B1(op1[0]), .B2(n_0_618), + .ZN(n_0_280)); + AOI22_X1_LVT i_0_295 (.A1(op2[2]), .A2(n_0_280), .B1(n_0_693), .B2(n_0_356), + .ZN(n_0_279)); + NAND2_X1_LVT i_0_294 (.A1(op2[1]), .A2(n_0_279), .ZN(n_0_278)); + OAI21_X1_LVT i_0_293 (.A(n_0_278), .B1(op2[1]), .B2(n_0_299), .ZN(n_0_277)); + OAI221_X1_LVT i_0_292 (.A(n_0_620), .B1(n_0_701), .B2(n_0_277), .C1(op2[0]), + .C2(n_0_292), .ZN(n_0_276)); + OAI222_X1_LVT i_0_291 (.A1(n_0_719), .A2(n_0_617), .B1(n_0_691), .B2(n_0_605), + .C1(n_0_734), .C2(n_0_615), .ZN(n_0_275)); + OAI22_X1_LVT i_0_290 (.A1(n_0_693), .A2(n_0_349), .B1(op2[2]), .B2(n_0_275), + .ZN(n_0_274)); + OAI22_X1_LVT i_0_289 (.A1(op2[1]), .A2(n_0_274), .B1(n_0_728), .B2(n_0_311), + .ZN(n_0_273)); + AOI22_X1_LVT i_0_283 (.A1(n_0_561), .A2(n_0_273), .B1(n_0_547), .B2(n_0_287), + .ZN(n_0_267)); + NAND4_X1_LVT i_0_282 (.A1(n_0_270), .A2(n_0_268), .A3(n_0_276), .A4(n_0_267), + .ZN(result[15])); + NOR2_X1_LVT i_0_278 (.A1(op2[0]), .A2(n_0_277), .ZN(n_0_263)); + NAND2_X1_LVT i_0_281 (.A1(n_0_612), .A2(n_0_575), .ZN(n_0_266)); + OAI21_X1_LVT i_0_280 (.A(n_0_266), .B1(n_0_713), .B2(n_0_497), .ZN(n_0_265)); + AOI22_X1_LVT i_0_279 (.A1(op2[1]), .A2(n_0_265), .B1(n_0_728), .B2(n_0_294), + .ZN(n_0_264)); + AOI211_X1_LVT i_0_277 (.A(n_0_263), .B(n_0_621), .C1(op2[0]), .C2(n_0_264), + .ZN(n_0_262)); + INV_X1_LVT i_0_754 (.A(op1[14]), .ZN(n_0_721)); + OAI21_X1_LVT i_0_273 (.A(op2[14]), .B1(n_0_721), .B2(n_0_567), .ZN(n_0_258)); + AOI21_X1_LVT i_0_272 (.A(n_0_258), .B1(n_0_721), .B2(n_0_565), .ZN(n_0_257)); + XNOR2_X1_LVT i_10_74 (.A(n_10_58), .B(n_10_59), .ZN(n_46)); + OAI21_X1_LVT i_0_276 (.A(n_0_681), .B1(op2[14]), .B2(n_0_568), .ZN(n_0_261)); + AOI222_X1_LVT i_0_275 (.A1(n_14), .A2(n_0_581), .B1(n_46), .B2(n_0_580), + .C1(op1[14]), .C2(n_0_261), .ZN(n_0_260)); + INV_X1_LVT i_0_274 (.A(n_0_260), .ZN(n_0_259)); + OAI222_X1_LVT i_0_271 (.A1(n_0_717), .A2(n_0_605), .B1(n_0_687), .B2(n_0_617), + .C1(n_0_721), .C2(n_0_615), .ZN(n_0_256)); + OAI22_X1_LVT i_0_270 (.A1(n_0_693), .A2(n_0_331), .B1(op2[2]), .B2(n_0_256), + .ZN(n_0_255)); + AND2_X1_LVT i_0_269 (.A1(n_0_728), .A2(n_0_255), .ZN(n_0_254)); + NOR3_X1_LVT i_0_265 (.A1(op2[3]), .A2(op2[2]), .A3(op2[0]), .ZN(n_0_250)); + AOI21_X1_LVT i_0_268 (.A(n_0_254), .B1(op2[1]), .B2(n_0_288), .ZN(n_0_253)); + OAI22_X1_LVT i_0_266 (.A1(op2[0]), .A2(n_0_253), .B1(n_0_701), .B2(n_0_273), + .ZN(n_0_251)); + AOI221_X1_LVT i_0_259 (.A(n_0_579), .B1(n_0_254), .B2(n_0_250), .C1(n_0_315), + .C2(n_0_251), .ZN(n_0_244)); + OR4_X1_LVT i_0_258 (.A1(n_0_262), .A2(n_0_257), .A3(n_0_259), .A4(n_0_244), + .ZN(result[14])); + OAI221_X1_LVT i_0_245 (.A(op2[13]), .B1(op1[13]), .B2(n_0_564), .C1(n_0_714), + .C2(n_0_567), .ZN(n_0_231)); + NAND2_X1_LVT i_0_244 (.A1(n_13), .A2(n_0_581), .ZN(n_0_230)); + OAI211_X1_LVT i_0_243 (.A(n_0_231), .B(n_0_230), .C1(n_0_714), .C2(n_0_681), + .ZN(n_0_229)); + XNOR2_X1_LVT i_10_70 (.A(n_10_55), .B(n_10_56), .ZN(n_45)); + NOR2_X1_LVT i_0_695 (.A1(op2[13]), .A2(n_0_714), .ZN(n_0_662)); + AOI221_X1_LVT i_0_242 (.A(n_0_229), .B1(n_45), .B2(n_0_580), .C1(n_0_662), + .C2(n_0_569), .ZN(n_0_228)); + INV_X1_LVT i_0_267 (.A(n_0_253), .ZN(n_0_252)); + OAI222_X1_LVT i_0_257 (.A1(n_0_714), .A2(n_0_615), .B1(n_0_726), .B2(n_0_617), + .C1(n_0_710), .C2(n_0_605), .ZN(n_0_243)); + OAI22_X1_LVT i_0_256 (.A1(n_0_693), .A2(n_0_312), .B1(op2[2]), .B2(n_0_243), + .ZN(n_0_242)); + NAND2_X1_LVT i_0_255 (.A1(n_0_728), .A2(n_0_242), .ZN(n_0_241)); + NAND2_X1_LVT i_0_254 (.A1(op2[1]), .A2(n_0_274), .ZN(n_0_240)); + NAND2_X1_LVT i_0_241 (.A1(n_0_241), .A2(n_0_240), .ZN(n_0_227)); + OAI221_X1_LVT i_0_240 (.A(n_0_228), .B1(n_0_548), .B2(n_0_252), .C1(n_0_562), + .C2(n_0_227), .ZN(n_0_226)); + NAND2_X1_LVT i_0_249 (.A1(n_0_728), .A2(n_0_279), .ZN(n_0_235)); + AOI22_X1_LVT i_0_250 (.A1(n_0_597), .A2(n_0_575), .B1(op1[6]), .B2(n_0_496), + .ZN(n_0_236)); + OAI21_X1_LVT i_0_248 (.A(n_0_235), .B1(n_0_728), .B2(n_0_236), .ZN(n_0_234)); + INV_X1_LVT i_0_247 (.A(n_0_234), .ZN(n_0_233)); + AOI221_X1_LVT i_0_246 (.A(n_0_621), .B1(op2[0]), .B2(n_0_233), .C1(n_0_701), + .C2(n_0_264), .ZN(n_0_232)); + NAND2_X1_LVT i_0_264 (.A1(op2[3]), .A2(n_0_469), .ZN(n_0_249)); + AOI21_X1_LVT i_0_262 (.A(n_0_468), .B1(n_0_693), .B2(n_0_249), .ZN(n_0_247)); + INV_X1_LVT i_0_261 (.A(n_0_247), .ZN(n_0_246)); + OAI211_X1_LVT i_0_260 (.A(n_0_252), .B(n_0_246), .C1(n_0_468), .C2(n_0_254), + .ZN(n_0_245)); + OAI221_X1_LVT i_0_253 (.A(n_0_544), .B1(n_0_247), .B2(n_0_241), .C1(n_0_469), + .C2(n_0_240), .ZN(n_0_239)); + INV_X1_LVT i_0_252 (.A(n_0_239), .ZN(n_0_238)); + AOI211_X1_LVT i_0_239 (.A(n_0_226), .B(n_0_232), .C1(n_0_245), .C2(n_0_238), + .ZN(n_0_225)); + INV_X1_LVT i_0_238 (.A(n_0_225), .ZN(result[13])); + OAI221_X1_LVT i_0_232 (.A(op2[12]), .B1(n_0_696), .B2(n_0_567), .C1(op1[12]), + .C2(n_0_564), .ZN(n_0_219)); + OAI21_X1_LVT i_0_231 (.A(n_0_681), .B1(op2[12]), .B2(n_0_568), .ZN(n_0_218)); + XNOR2_X1_LVT i_10_66 (.A(n_10_52), .B(n_10_53), .ZN(n_44)); + AOI222_X1_LVT i_0_230 (.A1(n_12), .A2(n_0_581), .B1(op1[12]), .B2(n_0_218), + .C1(n_44), .C2(n_0_580), .ZN(n_0_217)); + OAI21_X1_LVT i_0_234 (.A(n_0_620), .B1(op2[1]), .B2(n_0_265), .ZN(n_0_221)); + INV_X1_LVT i_0_763 (.A(op1[5]), .ZN(n_0_730)); + OAI21_X1_LVT i_0_236 (.A(op2[2]), .B1(n_0_730), .B2(n_0_615), .ZN(n_0_223)); + OAI21_X1_LVT i_0_235 (.A(n_0_223), .B1(op2[2]), .B2(n_0_296), .ZN(n_0_222)); + AOI21_X1_LVT i_0_233 (.A(n_0_221), .B1(op2[1]), .B2(n_0_222), .ZN(n_0_220)); + NOR2_X1_LVT i_0_237 (.A1(n_0_577), .A2(n_0_227), .ZN(n_0_224)); + NOR4_X1_LVT i_0_223 (.A1(n_0_701), .A2(n_0_220), .A3(n_0_224), .A4(n_0_238), + .ZN(n_0_210)); + NAND2_X1_LVT i_0_224 (.A1(n_0_544), .A2(n_0_247), .ZN(n_0_211)); + NAND2_X1_LVT i_0_222 (.A1(n_0_701), .A2(n_0_211), .ZN(n_0_209)); + OAI22_X1_LVT i_0_229 (.A1(op2[4]), .A2(n_0_696), .B1(n_0_738), .B2(n_0_698), + .ZN(n_0_216)); + INV_X1_LVT i_0_228 (.A(n_0_216), .ZN(n_0_215)); + OAI22_X1_LVT i_0_227 (.A1(n_0_727), .A2(n_0_617), .B1(op2[3]), .B2(n_0_215), + .ZN(n_0_214)); + OAI22_X1_LVT i_0_226 (.A1(n_0_693), .A2(n_0_289), .B1(op2[2]), .B2(n_0_214), + .ZN(n_0_213)); + OAI22_X1_LVT i_0_225 (.A1(op2[1]), .A2(n_0_213), .B1(n_0_728), .B2(n_0_255), + .ZN(n_0_212)); + AOI221_X1_LVT i_0_221 (.A(n_0_209), .B1(n_0_578), .B2(n_0_212), .C1(n_0_620), + .C2(n_0_234), .ZN(n_0_208)); + OAI211_X1_LVT i_0_220 (.A(n_0_219), .B(n_0_217), .C1(n_0_210), .C2(n_0_208), + .ZN(result[12])); + OAI21_X1_LVT i_0_209 (.A(n_0_681), .B1(op2[11]), .B2(n_0_568), .ZN(n_0_197)); + AOI22_X1_LVT i_0_208 (.A1(n_11), .A2(n_0_581), .B1(op1[11]), .B2(n_0_197), + .ZN(n_0_196)); + NAND2_X1_LVT i_0_207 (.A1(n_0_211), .A2(n_0_196), .ZN(n_0_195)); + AOI22_X1_LVT i_0_210 (.A1(op1[11]), .A2(n_0_566), .B1(n_0_706), .B2(n_0_565), + .ZN(n_0_198)); + XNOR2_X1_LVT i_10_62 (.A(n_10_49), .B(n_10_50), .ZN(n_43)); + AOI221_X1_LVT i_0_206 (.A(n_0_195), .B1(op2[11]), .B2(n_0_198), .C1(n_43), + .C2(n_0_580), .ZN(n_0_194)); + AOI221_X1_LVT i_0_215 (.A(op2[3]), .B1(n_0_738), .B2(n_0_706), .C1(op2[4]), + .C2(n_0_688), .ZN(n_0_203)); + AOI21_X1_LVT i_0_214 (.A(n_0_203), .B1(op1[19]), .B2(n_0_618), .ZN(n_0_202)); + NAND2_X1_LVT i_0_213 (.A1(n_0_693), .A2(n_0_202), .ZN(n_0_201)); + OAI21_X1_LVT i_0_212 (.A(n_0_201), .B1(n_0_693), .B2(n_0_275), .ZN(n_0_200)); + OAI22_X1_LVT i_0_211 (.A1(n_0_728), .A2(n_0_242), .B1(op2[1]), .B2(n_0_200), + .ZN(n_0_199)); + AOI22_X1_LVT i_0_205 (.A1(n_0_561), .A2(n_0_199), .B1(n_0_701), .B2(n_0_220), + .ZN(n_0_193)); + NOR2_X1_LVT i_0_219 (.A1(op2[2]), .A2(n_0_280), .ZN(n_0_207)); + AOI21_X1_LVT i_0_218 (.A(n_0_207), .B1(op1[4]), .B2(n_0_496), .ZN(n_0_206)); + AOI22_X1_LVT i_0_217 (.A1(n_0_728), .A2(n_0_236), .B1(op2[1]), .B2(n_0_206), + .ZN(n_0_205)); + AOI22_X1_LVT i_0_216 (.A1(n_0_578), .A2(n_0_212), .B1(n_0_620), .B2(n_0_205), + .ZN(n_0_204)); + OAI211_X1_LVT i_0_204 (.A(n_0_194), .B(n_0_193), .C1(n_0_701), .C2(n_0_204), + .ZN(result[11])); + AOI22_X1_LVT i_0_194 (.A1(n_0_654), .A2(n_0_498), .B1(op1[7]), .B2(n_0_573), + .ZN(n_0_183)); + OAI22_X1_LVT i_0_193 (.A1(n_0_728), .A2(n_0_183), .B1(op2[1]), .B2(n_0_222), + .ZN(n_0_182)); + AOI22_X1_LVT i_0_192 (.A1(op2[0]), .A2(n_0_182), .B1(n_0_701), .B2(n_0_205), + .ZN(n_0_181)); + NOR2_X1_LVT i_0_191 (.A1(n_0_621), .A2(n_0_181), .ZN(n_0_180)); + AOI22_X1_LVT i_0_190 (.A1(op1[10]), .A2(n_0_566), .B1(n_0_733), .B2(n_0_565), + .ZN(n_0_179)); + XNOR2_X1_LVT i_10_58 (.A(n_10_46), .B(n_10_47), .ZN(n_42)); + AOI22_X1_LVT i_0_188 (.A1(op2[10]), .A2(n_0_179), .B1(n_42), .B2(n_0_580), + .ZN(n_0_177)); + OAI21_X1_LVT i_0_189 (.A(n_0_681), .B1(op2[10]), .B2(n_0_568), .ZN(n_0_178)); + AOI22_X1_LVT i_0_187 (.A1(n_10), .A2(n_0_581), .B1(op1[10]), .B2(n_0_178), + .ZN(n_0_176)); + NAND2_X1_LVT i_0_186 (.A1(n_0_177), .A2(n_0_176), .ZN(n_0_175)); + NOR2_X1_LVT i_0_203 (.A1(n_0_701), .A2(n_0_199), .ZN(n_0_192)); + NOR2_X1_LVT i_0_200 (.A1(n_0_693), .A2(n_0_256), .ZN(n_0_189)); + AOI221_X1_LVT i_0_202 (.A(n_0_596), .B1(op1[10]), .B2(n_0_616), .C1(op1[26]), + .C2(n_0_606), .ZN(n_0_191)); + AOI21_X1_LVT i_0_199 (.A(n_0_189), .B1(n_0_693), .B2(n_0_191), .ZN(n_0_188)); + OR2_X1_LVT i_0_198 (.A1(op2[1]), .A2(n_0_188), .ZN(n_0_187)); + NAND2_X1_LVT i_0_197 (.A1(op2[1]), .A2(n_0_213), .ZN(n_0_186)); + NAND2_X1_LVT i_0_185 (.A1(n_0_187), .A2(n_0_186), .ZN(n_0_174)); + AOI211_X1_LVT i_0_184 (.A(n_0_577), .B(n_0_192), .C1(n_0_701), .C2(n_0_174), + .ZN(n_0_173)); + INV_X1_LVT i_0_263 (.A(n_0_249), .ZN(n_0_248)); + OAI22_X1_LVT i_0_196 (.A1(n_0_248), .A2(n_0_187), .B1(n_0_247), .B2(n_0_186), + .ZN(n_0_185)); + AOI221_X1_LVT i_0_195 (.A(n_0_545), .B1(n_0_246), .B2(n_0_192), .C1(n_0_701), + .C2(n_0_185), .ZN(n_0_184)); + OR4_X1_LVT i_0_183 (.A1(n_0_180), .A2(n_0_175), .A3(n_0_173), .A4(n_0_184), + .ZN(result[10])); + INV_X1_LVT i_0_753 (.A(op2[9]), .ZN(n_0_720)); + AOI221_X1_LVT i_0_171 (.A(n_0_720), .B1(op1[9]), .B2(n_0_566), .C1(n_0_722), + .C2(n_0_565), .ZN(n_0_161)); + XNOR2_X1_LVT i_10_54 (.A(n_10_43), .B(n_10_44), .ZN(n_41)); + AOI22_X1_LVT i_0_172 (.A1(n_9), .A2(n_0_581), .B1(n_41), .B2(n_0_580), + .ZN(n_0_162)); + AOI21_X1_LVT i_0_170 (.A(aluBypass), .B1(n_0_720), .B2(n_0_569), .ZN(n_0_160)); + OAI21_X1_LVT i_0_169 (.A(n_0_162), .B1(n_0_722), .B2(n_0_160), .ZN(n_0_159)); + OAI222_X1_LVT i_0_182 (.A1(n_0_722), .A2(n_0_615), .B1(n_0_699), .B2(n_0_605), + .C1(n_0_732), .C2(n_0_617), .ZN(n_0_172)); + AOI22_X1_LVT i_0_181 (.A1(n_0_693), .A2(n_0_172), .B1(op2[2]), .B2(n_0_243), + .ZN(n_0_171)); + NAND2_X1_LVT i_0_180 (.A1(n_0_728), .A2(n_0_171), .ZN(n_0_170)); + NAND2_X1_LVT i_0_179 (.A1(op2[1]), .A2(n_0_200), .ZN(n_0_169)); + OAI22_X1_LVT i_0_178 (.A1(n_0_248), .A2(n_0_170), .B1(n_0_247), .B2(n_0_169), + .ZN(n_0_168)); + NOR3_X1_LVT i_0_177 (.A1(n_0_545), .A2(n_0_168), .A3(n_0_185), .ZN(n_0_167)); + NOR2_X1_LVT i_0_251 (.A1(n_0_704), .A2(n_0_615), .ZN(n_0_237)); + OAI22_X1_LVT i_0_176 (.A1(op1[2]), .A2(n_0_693), .B1(n_0_496), .B2(n_0_237), + .ZN(n_0_166)); + OAI22_X1_LVT i_0_175 (.A1(op2[1]), .A2(n_0_206), .B1(n_0_728), .B2(n_0_166), + .ZN(n_0_165)); + OAI221_X1_LVT i_0_174 (.A(n_0_620), .B1(op2[0]), .B2(n_0_182), .C1(n_0_701), + .C2(n_0_165), .ZN(n_0_164)); + NAND2_X1_LVT i_0_173 (.A1(n_0_170), .A2(n_0_169), .ZN(n_0_163)); + OAI221_X1_LVT i_0_168 (.A(n_0_164), .B1(n_0_562), .B2(n_0_163), .C1(n_0_548), + .C2(n_0_174), .ZN(n_0_158)); + OR4_X1_LVT i_0_167 (.A1(n_0_161), .A2(n_0_159), .A3(n_0_167), .A4(n_0_158), + .ZN(result[9])); + OAI21_X1_LVT i_0_160 (.A(n_0_693), .B1(n_0_730), .B2(n_0_615), .ZN(n_0_151)); + OAI21_X1_LVT i_0_159 (.A(op2[2]), .B1(n_0_729), .B2(n_0_615), .ZN(n_0_150)); + AND2_X1_LVT i_0_158 (.A1(n_0_151), .A2(n_0_150), .ZN(n_0_149)); + NAND2_X1_LVT i_0_157 (.A1(op2[1]), .A2(n_0_149), .ZN(n_0_148)); + OAI21_X1_LVT i_0_156 (.A(n_0_148), .B1(op2[1]), .B2(n_0_183), .ZN(n_0_147)); + OAI22_X1_LVT i_0_155 (.A1(op2[0]), .A2(n_0_165), .B1(n_0_701), .B2(n_0_147), + .ZN(n_0_146)); + NOR2_X1_LVT i_0_154 (.A1(n_0_621), .A2(n_0_146), .ZN(n_0_145)); + INV_X1_LVT i_0_773 (.A(op1[8]), .ZN(n_0_740)); + NOR2_X1_LVT i_0_688 (.A1(n_0_740), .A2(op2[8]), .ZN(n_0_655)); + AOI22_X1_LVT i_0_153 (.A1(op1[8]), .A2(aluBypass), .B1(n_0_655), .B2(n_0_569), + .ZN(n_0_144)); + OAI221_X1_LVT i_0_152 (.A(op2[8]), .B1(op1[8]), .B2(n_0_564), .C1(n_0_740), + .C2(n_0_567), .ZN(n_0_143)); + XNOR2_X1_LVT i_10_51 (.A(n_10_39), .B(n_10_42), .ZN(n_40)); + AOI22_X1_LVT i_0_151 (.A1(n_40), .A2(n_0_580), .B1(n_8), .B2(n_0_581), + .ZN(n_0_142)); + NAND3_X1_LVT i_0_150 (.A1(n_0_144), .A2(n_0_143), .A3(n_0_142), .ZN(n_0_141)); + OAI222_X1_LVT i_0_166 (.A1(n_0_740), .A2(n_0_615), .B1(n_0_739), .B2(n_0_617), + .C1(n_0_736), .C2(n_0_605), .ZN(n_0_157)); + OAI22_X1_LVT i_0_165 (.A1(op2[2]), .A2(n_0_157), .B1(n_0_693), .B2(n_0_214), + .ZN(n_0_156)); + NOR2_X1_LVT i_0_164 (.A1(op2[1]), .A2(n_0_156), .ZN(n_0_155)); + AOI21_X1_LVT i_0_163 (.A(n_0_155), .B1(op2[1]), .B2(n_0_188), .ZN(n_0_154)); + AND2_X1_LVT i_0_162 (.A1(n_0_701), .A2(n_0_154), .ZN(n_0_153)); + AOI211_X1_LVT i_0_149 (.A(n_0_577), .B(n_0_153), .C1(op2[0]), .C2(n_0_163), + .ZN(n_0_140)); + AOI221_X1_LVT i_0_161 (.A(n_0_545), .B1(op2[0]), .B2(n_0_168), .C1(n_0_249), + .C2(n_0_153), .ZN(n_0_152)); + OR4_X1_LVT i_0_148 (.A1(n_0_145), .A2(n_0_141), .A3(n_0_140), .A4(n_0_152), + .ZN(result[8])); + AOI22_X1_LVT i_0_138 (.A1(op1[4]), .A2(n_0_573), .B1(op1[0]), .B2(n_0_496), + .ZN(n_0_130)); + AOI22_X1_LVT i_0_137 (.A1(op2[1]), .A2(n_0_130), .B1(n_0_728), .B2(n_0_166), + .ZN(n_0_129)); + OAI22_X1_LVT i_0_136 (.A1(n_0_701), .A2(n_0_129), .B1(op2[0]), .B2(n_0_147), + .ZN(n_0_128)); + NOR2_X1_LVT i_0_135 (.A1(n_0_621), .A2(n_0_128), .ZN(n_0_127)); + OAI221_X1_LVT i_0_139 (.A(op2[7]), .B1(n_0_713), .B2(n_0_567), .C1(op1[7]), + .C2(n_0_564), .ZN(n_0_131)); + INV_X1_LVT i_10_44 (.A(n_10_36), .ZN(n_10_37)); + NOR2_X1_LVT i_10_45 (.A1(n_10_35), .A2(n_10_37), .ZN(n_10_38)); + XNOR2_X1_LVT i_10_46 (.A(n_10_33), .B(n_10_38), .ZN(n_39)); + AOI22_X1_LVT i_0_141 (.A1(n_7), .A2(n_0_581), .B1(n_39), .B2(n_0_580), + .ZN(n_0_133)); + INV_X1_LVT i_0_745 (.A(op2[7]), .ZN(n_0_712)); + AOI21_X1_LVT i_0_140 (.A(aluBypass), .B1(n_0_712), .B2(n_0_569), .ZN(n_0_132)); + OAI211_X1_LVT i_0_133 (.A(n_0_131), .B(n_0_133), .C1(n_0_713), .C2(n_0_132), + .ZN(n_0_125)); + OAI22_X1_LVT i_0_147 (.A1(n_0_734), .A2(n_0_617), .B1(n_0_713), .B2(n_0_615), + .ZN(n_0_139)); + AOI211_X1_LVT i_0_146 (.A(n_0_139), .B(n_0_248), .C1(op1[23]), .C2(n_0_606), + .ZN(n_0_138)); + OAI22_X1_LVT i_0_145 (.A1(n_0_693), .A2(n_0_202), .B1(op2[2]), .B2(n_0_138), + .ZN(n_0_137)); + NOR2_X1_LVT i_0_144 (.A1(op2[1]), .A2(n_0_137), .ZN(n_0_136)); + AOI21_X1_LVT i_0_143 (.A(n_0_136), .B1(op2[1]), .B2(n_0_171), .ZN(n_0_135)); + NAND2_X1_LVT i_0_142 (.A1(n_0_561), .A2(n_0_135), .ZN(n_0_134)); + OAI221_X1_LVT i_0_134 (.A(n_0_134), .B1(n_0_548), .B2(n_0_154), .C1(n_0_545), + .C2(n_0_249), .ZN(n_0_126)); + OR3_X1_LVT i_0_132 (.A1(n_0_127), .A2(n_0_125), .A3(n_0_126), .ZN(result[7])); + NAND2_X1_LVT i_0_124 (.A1(n_0_728), .A2(n_0_149), .ZN(n_0_117)); + OAI21_X1_LVT i_0_123 (.A(n_0_117), .B1(n_0_724), .B2(n_0_531), .ZN(n_0_116)); + OAI22_X1_LVT i_0_122 (.A1(n_0_701), .A2(n_0_116), .B1(op2[0]), .B2(n_0_129), + .ZN(n_0_115)); + NOR2_X1_LVT i_0_121 (.A1(n_0_621), .A2(n_0_115), .ZN(n_0_114)); + XNOR2_X1_LVT i_10_38 (.A(n_10_30), .B(n_10_31), .ZN(n_38)); + AOI22_X1_LVT i_0_119 (.A1(n_6), .A2(n_0_581), .B1(n_38), .B2(n_0_580), + .ZN(n_0_112)); + INV_X1_LVT i_0_735 (.A(op2[6]), .ZN(n_0_702)); + AOI21_X1_LVT i_0_120 (.A(aluBypass), .B1(n_0_702), .B2(n_0_569), .ZN(n_0_113)); + OAI21_X1_LVT i_0_118 (.A(n_0_112), .B1(n_0_704), .B2(n_0_113), .ZN(n_0_111)); + AOI221_X1_LVT i_0_117 (.A(n_0_702), .B1(n_0_704), .B2(n_0_565), .C1(op1[6]), + .C2(n_0_566), .ZN(n_0_110)); + NOR3_X1_LVT i_0_116 (.A1(n_0_114), .A2(n_0_111), .A3(n_0_110), .ZN(n_0_109)); + AOI221_X1_LVT i_0_131 (.A(n_0_237), .B1(op1[14]), .B2(n_0_618), .C1(op2[4]), + .C2(n_0_406), .ZN(n_0_124)); + NAND2_X1_LVT i_0_130 (.A1(n_0_693), .A2(n_0_124), .ZN(n_0_123)); + INV_X1_LVT i_0_201 (.A(n_0_191), .ZN(n_0_190)); + OAI21_X1_LVT i_0_129 (.A(n_0_123), .B1(n_0_693), .B2(n_0_190), .ZN(n_0_122)); + AOI22_X1_LVT i_0_128 (.A1(n_0_728), .A2(n_0_122), .B1(op2[1]), .B2(n_0_156), + .ZN(n_0_121)); + INV_X1_LVT i_0_127 (.A(n_0_121), .ZN(n_0_120)); + OAI21_X1_LVT i_0_126 (.A(n_0_248), .B1(op2[1]), .B2(n_0_123), .ZN(n_0_119)); + AND2_X1_LVT i_0_125 (.A1(n_0_120), .A2(n_0_119), .ZN(n_0_118)); + NOR2_X1_LVT i_0_115 (.A1(n_0_545), .A2(n_0_118), .ZN(n_0_108)); + AOI21_X1_LVT i_0_114 (.A(n_0_108), .B1(n_0_576), .B2(n_0_121), .ZN(n_0_107)); + AOI22_X1_LVT i_0_113 (.A1(n_0_544), .A2(n_0_248), .B1(n_0_578), .B2(n_0_135), + .ZN(n_0_106)); + OAI221_X1_LVT i_0_112 (.A(n_0_109), .B1(op2[0]), .B2(n_0_107), .C1(n_0_701), + .C2(n_0_106), .ZN(result[6])); + OAI221_X1_LVT i_0_100 (.A(op2[5]), .B1(op1[5]), .B2(n_0_564), .C1(n_0_730), + .C2(n_0_567), .ZN(n_0_94)); + INV_X1_LVT i_0_764 (.A(op2[5]), .ZN(n_0_731)); + AOI21_X1_LVT i_0_99 (.A(aluBypass), .B1(n_0_731), .B2(n_0_569), .ZN(n_0_93)); + NOR2_X1_LVT i_0_98 (.A1(n_0_730), .A2(n_0_93), .ZN(n_0_92)); + XNOR2_X1_LVT i_10_35 (.A(n_10_26), .B(n_10_29), .ZN(n_37)); + AOI221_X1_LVT i_0_97 (.A(n_0_92), .B1(n_37), .B2(n_0_580), .C1(n_5), .C2( + n_0_581), .ZN(n_0_91)); + OAI22_X1_LVT i_0_102 (.A1(n_0_694), .A2(n_0_531), .B1(op2[1]), .B2(n_0_130), + .ZN(n_0_96)); + OAI221_X1_LVT i_0_101 (.A(n_0_620), .B1(n_0_701), .B2(n_0_96), .C1(op2[0]), + .C2(n_0_116), .ZN(n_0_95)); + NAND3_X1_LVT i_0_111 (.A1(n_0_544), .A2(n_0_248), .A3(op2[2]), .ZN(n_0_105)); + NAND2_X1_LVT i_0_110 (.A1(op2[4]), .A2(n_0_386), .ZN(n_0_104)); + OAI21_X1_LVT i_0_109 (.A(n_0_104), .B1(n_0_714), .B2(n_0_617), .ZN(n_0_103)); + OAI22_X1_LVT i_0_108 (.A1(n_0_151), .A2(n_0_103), .B1(n_0_693), .B2(n_0_172), + .ZN(n_0_102)); + NOR2_X1_LVT i_0_107 (.A1(op2[1]), .A2(n_0_102), .ZN(n_0_101)); + AOI21_X1_LVT i_0_106 (.A(n_0_101), .B1(op2[1]), .B2(n_0_137), .ZN(n_0_100)); + OAI21_X1_LVT i_0_105 (.A(n_0_105), .B1(n_0_579), .B2(n_0_100), .ZN(n_0_99)); + AOI21_X1_LVT i_0_104 (.A(n_0_118), .B1(n_0_682), .B2(n_0_120), .ZN(n_0_98)); + OAI22_X1_LVT i_0_103 (.A1(n_0_547), .A2(n_0_99), .B1(n_0_701), .B2(n_0_98), + .ZN(n_0_97)); + NAND4_X1_LVT i_0_96 (.A1(n_0_94), .A2(n_0_91), .A3(n_0_95), .A4(n_0_97), + .ZN(result[5])); + INV_X1_LVT i_10_26 (.A(n_10_21), .ZN(n_10_22)); + NOR2_X1_LVT i_10_28 (.A1(n_10_22), .A2(n_10_23), .ZN(n_10_24)); + XNOR2_X1_LVT i_10_29 (.A(n_10_19), .B(n_10_24), .ZN(n_36)); + AOI222_X1_LVT i_0_89 (.A1(n_4), .A2(n_0_581), .B1(n_36), .B2(n_0_580), + .C1(n_0_668), .C2(n_0_564), .ZN(n_0_84)); + INV_X1_LVT i_0_770 (.A(op1[4]), .ZN(n_0_737)); + AOI221_X1_LVT i_0_90 (.A(aluBypass), .B1(op2[4]), .B2(n_0_567), .C1(n_0_738), + .C2(n_0_569), .ZN(n_0_85)); + OAI21_X1_LVT i_0_88 (.A(n_0_84), .B1(n_0_737), .B2(n_0_85), .ZN(n_0_83)); + NOR2_X1_LVT i_0_689 (.A1(op2[4]), .A2(n_0_737), .ZN(n_0_656)); + AOI21_X1_LVT i_0_95 (.A(n_0_616), .B1(n_0_727), .B2(n_0_723), .ZN(n_0_90)); + OAI22_X1_LVT i_0_94 (.A1(n_0_723), .A2(n_0_216), .B1(n_0_656), .B2(n_0_90), + .ZN(n_0_89)); + INV_X1_LVT i_0_93 (.A(n_0_89), .ZN(n_0_88)); + OAI22_X1_LVT i_0_92 (.A1(op2[2]), .A2(n_0_88), .B1(n_0_693), .B2(n_0_157), + .ZN(n_0_87)); + OAI221_X1_LVT i_0_91 (.A(n_0_105), .B1(n_0_728), .B2(n_0_122), .C1(op2[1]), + .C2(n_0_87), .ZN(n_0_86)); + AOI221_X1_LVT i_0_85 (.A(n_0_83), .B1(n_0_561), .B2(n_0_86), .C1(op2[0]), + .C2(n_0_99), .ZN(n_0_80)); + AOI221_X1_LVT i_0_87 (.A(n_0_574), .B1(n_0_729), .B2(op2[1]), .C1(n_0_728), + .C2(n_0_724), .ZN(n_0_82)); + OAI22_X1_LVT i_0_86 (.A1(op2[0]), .A2(n_0_96), .B1(n_0_701), .B2(n_0_82), + .ZN(n_0_81)); + OAI21_X1_LVT i_0_84 (.A(n_0_80), .B1(n_0_621), .B2(n_0_81), .ZN(result[4])); + AND2_X1_LVT i_0_81 (.A1(op2[1]), .A2(n_0_105), .ZN(n_0_77)); + NAND2_X1_LVT i_0_80 (.A1(n_0_102), .A2(n_0_77), .ZN(n_0_76)); + OAI221_X1_LVT i_0_83 (.A(n_0_693), .B1(n_0_654), .B2(n_0_484), .C1(n_0_738), + .C2(n_0_350), .ZN(n_0_79)); + OAI21_X1_LVT i_0_82 (.A(n_0_79), .B1(n_0_693), .B2(n_0_138), .ZN(n_0_78)); + OAI21_X1_LVT i_0_79 (.A(n_0_76), .B1(op2[1]), .B2(n_0_78), .ZN(n_0_75)); + NOR2_X1_LVT i_0_78 (.A1(n_0_562), .A2(n_0_75), .ZN(n_0_74)); + NAND2_X1_LVT i_10_20 (.A1(n_10_15), .A2(n_10_16), .ZN(n_10_17)); + XNOR2_X1_LVT i_10_21 (.A(n_10_13), .B(n_10_17), .ZN(n_35)); + AOI22_X1_LVT i_0_75 (.A1(n_35), .A2(n_0_580), .B1(n_3), .B2(n_0_581), + .ZN(n_0_71)); + OAI21_X1_LVT i_0_74 (.A(n_0_681), .B1(n_0_723), .B2(n_0_566), .ZN(n_0_70)); + AOI222_X1_LVT i_0_73 (.A1(n_0_654), .A2(n_0_569), .B1(n_0_663), .B2(n_0_564), + .C1(op1[3]), .C2(n_0_70), .ZN(n_0_69)); + INV_X1_LVT i_0_736 (.A(op1[0]), .ZN(n_0_703)); + OAI22_X1_LVT i_0_77 (.A1(n_0_703), .A2(n_0_531), .B1(n_0_694), .B2(n_0_572), + .ZN(n_0_73)); + OAI22_X1_LVT i_0_76 (.A1(n_0_701), .A2(n_0_73), .B1(op2[0]), .B2(n_0_82), + .ZN(n_0_72)); + OAI211_X1_LVT i_0_72 (.A(n_0_71), .B(n_0_69), .C1(n_0_621), .C2(n_0_72), + .ZN(n_0_68)); + AOI211_X1_LVT i_0_71 (.A(n_0_74), .B(n_0_68), .C1(n_0_547), .C2(n_0_86), + .ZN(n_0_67)); + INV_X1_LVT i_0_70 (.A(n_0_67), .ZN(result[3])); + NAND2_X1_LVT i_0_65 (.A1(n_2), .A2(n_0_581), .ZN(n_0_62)); + OAI221_X1_LVT i_0_66 (.A(op2[2]), .B1(op1[2]), .B2(n_0_564), .C1(n_0_694), + .C2(n_0_567), .ZN(n_0_63)); + AOI21_X1_LVT i_0_64 (.A(aluBypass), .B1(n_0_693), .B2(n_0_569), .ZN(n_0_61)); + OAI21_X1_LVT i_0_63 (.A(n_0_63), .B1(n_0_694), .B2(n_0_61), .ZN(n_0_60)); + INV_X1_LVT i_10_13 (.A(n_10_10), .ZN(n_10_11)); + NOR2_X1_LVT i_10_14 (.A1(n_10_9), .A2(n_10_11), .ZN(n_10_12)); + XNOR2_X1_LVT i_10_15 (.A(n_10_7), .B(n_10_12), .ZN(n_34)); + AOI21_X1_LVT i_0_62 (.A(n_0_60), .B1(n_34), .B2(n_0_580), .ZN(n_0_59)); + OAI211_X1_LVT i_0_57 (.A(n_0_62), .B(n_0_59), .C1(n_0_548), .C2(n_0_75), + .ZN(n_0_54)); + NOR2_X1_LVT i_0_698 (.A1(n_0_729), .A2(op2[1]), .ZN(n_0_665)); + INV_X1_LVT i_0_697 (.A(n_0_665), .ZN(n_0_664)); + OAI21_X1_LVT i_0_69 (.A(op2[0]), .B1(n_0_664), .B2(n_0_574), .ZN(n_0_66)); + OAI21_X1_LVT i_0_68 (.A(n_0_620), .B1(op2[0]), .B2(n_0_73), .ZN(n_0_65)); + INV_X1_LVT i_0_67 (.A(n_0_65), .ZN(n_0_64)); + OAI222_X1_LVT i_0_61 (.A1(op1[10]), .A2(n_0_617), .B1(op1[2]), .B2(n_0_615), + .C1(n_0_738), .C2(n_0_332), .ZN(n_0_58)); + OAI22_X1_LVT i_0_60 (.A1(op2[2]), .A2(n_0_58), .B1(n_0_693), .B2(n_0_124), + .ZN(n_0_57)); + INV_X1_LVT i_0_59 (.A(n_0_57), .ZN(n_0_56)); + AOI22_X1_LVT i_0_58 (.A1(n_0_728), .A2(n_0_56), .B1(n_0_87), .B2(n_0_77), + .ZN(n_0_55)); + AOI221_X1_LVT i_0_56 (.A(n_0_54), .B1(n_0_66), .B2(n_0_64), .C1(n_0_561), + .C2(n_0_55), .ZN(n_0_53)); + INV_X1_LVT i_0_55 (.A(n_0_53), .ZN(result[2])); + NAND2_X1_LVT i_0_54 (.A1(n_0_547), .A2(n_0_55), .ZN(n_0_52)); + AOI221_X1_LVT i_0_47 (.A(n_0_728), .B1(n_0_729), .B2(n_0_565), .C1(op1[1]), + .C2(n_0_566), .ZN(n_0_45)); + NOR2_X1_LVT i_0_700 (.A1(op1[0]), .A2(n_0_701), .ZN(n_0_667)); + AOI211_X1_LVT i_0_48 (.A(n_0_667), .B(n_0_621), .C1(n_0_729), .C2(n_0_701), + .ZN(n_0_46)); + AOI221_X1_LVT i_0_44 (.A(n_0_45), .B1(op1[1]), .B2(aluBypass), .C1(n_0_571), + .C2(n_0_46), .ZN(n_0_42)); + NAND2_X1_LVT i_10_6 (.A1(n_10_3), .A2(n_10_4), .ZN(n_10_5)); + XNOR2_X1_LVT i_10_7 (.A(n_10_5), .B(n_10_1), .ZN(n_33)); + AOI22_X1_LVT i_0_49 (.A1(n_33), .A2(n_0_580), .B1(n_1), .B2(n_0_581), + .ZN(n_0_47)); + OAI21_X1_LVT i_0_46 (.A(n_0_47), .B1(n_0_664), .B2(n_0_568), .ZN(n_0_44)); + NAND2_X1_LVT i_0_51 (.A1(op2[1]), .A2(n_0_78), .ZN(n_0_49)); + OAI222_X1_LVT i_0_53 (.A1(n_0_722), .A2(n_0_617), .B1(n_0_729), .B2(n_0_615), + .C1(n_0_738), .C2(n_0_313), .ZN(n_0_51)); + OAI22_X1_LVT i_0_52 (.A1(n_0_223), .A2(n_0_103), .B1(op2[2]), .B2(n_0_51), + .ZN(n_0_50)); + OAI21_X1_LVT i_0_50 (.A(n_0_49), .B1(op2[1]), .B2(n_0_50), .ZN(n_0_48)); + AOI21_X1_LVT i_0_45 (.A(n_0_44), .B1(n_0_561), .B2(n_0_48), .ZN(n_0_43)); + NAND3_X1_LVT i_0_43 (.A1(n_0_52), .A2(n_0_42), .A3(n_0_43), .ZN(result[1])); + OAI222_X1_LVT i_0_11 (.A1(n_0_740), .A2(n_0_617), .B1(n_0_703), .B2(n_0_615), + .C1(n_0_738), .C2(n_0_290), .ZN(n_0_10)); + OAI22_X1_LVT i_0_10 (.A1(op2[2]), .A2(n_0_10), .B1(n_0_693), .B2(n_0_88), + .ZN(n_0_9)); + OAI221_X1_LVT i_0_9 (.A(n_0_701), .B1(n_0_728), .B2(n_0_56), .C1(op2[1]), + .C2(n_0_9), .ZN(n_0_8)); + OAI21_X1_LVT i_0_8 (.A(n_0_8), .B1(n_0_701), .B2(n_0_48), .ZN(n_0_7)); + NOR2_X1_LVT i_0_7 (.A1(n_0_579), .A2(n_0_7), .ZN(n_0_6)); + OAI221_X1_LVT i_0_3 (.A(op2[0]), .B1(op1[0]), .B2(n_0_564), .C1(n_0_703), + .C2(n_0_567), .ZN(n_0_2)); + OAI21_X1_LVT i_10_2 (.A(n_10_1), .B1(n_10_0), .B2(op2[0]), .ZN(n_32)); + AOI22_X1_LVT i_0_2 (.A1(n_32), .A2(n_0_580), .B1(n_0), .B2(n_0_581), .ZN( + n_0_1)); + NAND3_X1_LVT i_0_6 (.A1(n_0_701), .A2(n_0_571), .A3(n_0_620), .ZN(n_0_5)); + OAI211_X1_LVT i_0_5 (.A(n_0_681), .B(n_0_5), .C1(op2[0]), .C2(n_0_568), + .ZN(n_0_4)); + NAND2_X1_LVT i_0_4 (.A1(op1[0]), .A2(n_0_4), .ZN(n_0_3)); + NAND3_X1_LVT i_0_1 (.A1(n_0_2), .A2(n_0_1), .A3(n_0_3), .ZN(n_0_0)); + OAI33_X1_LVT i_0_14 (.A1(n_0_692), .A2(op1[31]), .A3(n_0_683), .B1(op2[31]), + .B2(n_0_691), .B3(aluOp[0]), .ZN(n_0_13)); + INV_X1_LVT i_0_741 (.A(op2[29]), .ZN(n_0_708)); + NAND2_X1_LVT i_0_685 (.A1(op1[29]), .A2(n_0_708), .ZN(n_0_652)); + OAI22_X1_LVT i_0_713 (.A1(n_0_700), .A2(op1[28]), .B1(op1[29]), .B2(n_0_708), + .ZN(n_0_680)); + NAND2_X1_LVT i_0_694 (.A1(n_0_688), .A2(op2[27]), .ZN(n_0_661)); + INV_X1_LVT i_0_742 (.A(op2[26]), .ZN(n_0_709)); + OAI22_X1_LVT i_0_712 (.A1(n_0_699), .A2(op2[25]), .B1(n_0_736), .B2(op2[24]), + .ZN(n_0_679)); + NAND2_X1_LVT i_0_690 (.A1(n_0_727), .A2(op2[20]), .ZN(n_0_657)); + INV_X1_LVT i_0_740 (.A(op2[18]), .ZN(n_0_707)); + OAI22_X1_LVT i_0_711 (.A1(n_0_707), .A2(op1[18]), .B1(n_0_690), .B2(op1[19]), + .ZN(n_0_678)); + OAI22_X1_LVT i_0_29 (.A1(n_0_739), .A2(op2[16]), .B1(n_0_734), .B2(op2[15]), + .ZN(n_0_28)); + INV_X1_LVT i_0_728 (.A(op2[12]), .ZN(n_0_695)); + INV_X1_LVT i_0_748 (.A(op2[13]), .ZN(n_0_715)); + OAI22_X1_LVT i_0_704 (.A1(n_0_706), .A2(op2[11]), .B1(n_0_696), .B2(op2[12]), + .ZN(n_0_671)); + AOI22_X1_LVT i_0_710 (.A1(n_0_740), .A2(op2[8]), .B1(n_0_713), .B2(op2[7]), + .ZN(n_0_677)); + OAI22_X1_LVT i_0_707 (.A1(n_0_731), .A2(op1[5]), .B1(op1[6]), .B2(n_0_702), + .ZN(n_0_674)); + OAI22_X1_LVT i_0_706 (.A1(op1[2]), .A2(n_0_693), .B1(op1[1]), .B2(n_0_728), + .ZN(n_0_673)); + INV_X1_LVT i_0_705 (.A(n_0_673), .ZN(n_0_672)); + INV_X1_LVT i_0_699 (.A(n_0_667), .ZN(n_0_666)); + OAI21_X1_LVT i_0_42 (.A(n_0_672), .B1(n_0_666), .B2(n_0_665), .ZN(n_0_41)); + AOI21_X1_LVT i_0_41 (.A(n_0_654), .B1(op1[2]), .B2(n_0_693), .ZN(n_0_40)); + AOI211_X1_LVT i_0_40 (.A(n_0_668), .B(n_0_663), .C1(n_0_41), .C2(n_0_40), + .ZN(n_0_39)); + AOI211_X1_LVT i_0_39 (.A(n_0_656), .B(n_0_39), .C1(n_0_731), .C2(op1[5]), + .ZN(n_0_38)); + OAI222_X1_LVT i_0_38 (.A1(n_0_704), .A2(op2[6]), .B1(n_0_674), .B2(n_0_38), + .C1(n_0_713), .C2(op2[7]), .ZN(n_0_37)); + AOI221_X1_LVT i_0_37 (.A(n_0_655), .B1(op1[9]), .B2(n_0_720), .C1(n_0_677), + .C2(n_0_37), .ZN(n_0_36)); + INV_X1_LVT i_0_768 (.A(op2[10]), .ZN(n_0_735)); + OAI22_X1_LVT i_0_36 (.A1(n_0_735), .A2(op1[10]), .B1(op1[9]), .B2(n_0_720), + .ZN(n_0_35)); + OAI22_X1_LVT i_0_35 (.A1(op2[10]), .A2(n_0_733), .B1(n_0_36), .B2(n_0_35), + .ZN(n_0_34)); + INV_X1_LVT i_0_34 (.A(n_0_34), .ZN(n_0_33)); + AOI21_X1_LVT i_0_33 (.A(n_0_33), .B1(n_0_706), .B2(op2[11]), .ZN(n_0_32)); + OAI222_X1_LVT i_0_32 (.A1(op1[12]), .A2(n_0_695), .B1(n_0_715), .B2(op1[13]), + .C1(n_0_671), .C2(n_0_32), .ZN(n_0_31)); + OAI221_X1_LVT i_0_31 (.A(n_0_31), .B1(n_0_721), .B2(op2[14]), .C1(op2[13]), + .C2(n_0_714), .ZN(n_0_30)); + AOI22_X1_LVT i_0_30 (.A1(n_0_734), .A2(op2[15]), .B1(n_0_721), .B2(op2[14]), + .ZN(n_0_29)); + AOI21_X1_LVT i_0_28 (.A(n_0_28), .B1(n_0_30), .B2(n_0_29), .ZN(n_0_27)); + AOI221_X1_LVT i_0_27 (.A(n_0_27), .B1(n_0_732), .B2(op2[17]), .C1(n_0_739), + .C2(op2[16]), .ZN(n_0_26)); + AOI211_X1_LVT i_0_26 (.A(n_0_660), .B(n_0_26), .C1(n_0_707), .C2(op1[18]), + .ZN(n_0_25)); + OAI22_X1_LVT i_0_25 (.A1(op2[19]), .A2(n_0_689), .B1(n_0_678), .B2(n_0_25), + .ZN(n_0_24)); + AOI211_X1_LVT i_0_24 (.A(n_0_658), .B(n_0_659), .C1(n_0_657), .C2(n_0_24), + .ZN(n_0_23)); + AOI221_X1_LVT i_0_23 (.A(n_0_23), .B1(n_0_726), .B2(op2[21]), .C1(n_0_687), + .C2(op2[22]), .ZN(n_0_22)); + AOI221_X1_LVT i_0_22 (.A(n_0_22), .B1(op1[22]), .B2(n_0_686), .C1(op1[23]), + .C2(n_0_718), .ZN(n_0_21)); + AOI221_X1_LVT i_0_21 (.A(n_0_21), .B1(n_0_736), .B2(op2[24]), .C1(n_0_719), + .C2(op2[23]), .ZN(n_0_20)); + OAI222_X1_LVT i_0_20 (.A1(op1[26]), .A2(n_0_709), .B1(op1[25]), .B2(n_0_697), + .C1(n_0_679), .C2(n_0_20), .ZN(n_0_19)); + OAI221_X1_LVT i_0_19 (.A(n_0_19), .B1(n_0_711), .B2(op2[26]), .C1(n_0_688), + .C2(op2[27]), .ZN(n_0_18)); + AOI22_X1_LVT i_0_18 (.A1(n_0_700), .A2(op1[28]), .B1(n_0_661), .B2(n_0_18), + .ZN(n_0_17)); + OAI21_X1_LVT i_0_17 (.A(n_0_652), .B1(n_0_680), .B2(n_0_17), .ZN(n_0_16)); + INV_X1_LVT i_0_749 (.A(op2[30]), .ZN(n_0_716)); + OAI21_X1_LVT i_0_16 (.A(n_0_16), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_15)); + OAI22_X1_LVT i_0_708 (.A1(n_0_692), .A2(op1[31]), .B1(op2[31]), .B2(n_0_691), + .ZN(n_0_675)); + AOI21_X1_LVT i_0_15 (.A(n_0_675), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_14)); + AOI21_X1_LVT i_0_13 (.A(n_0_13), .B1(n_0_15), .B2(n_0_14), .ZN(n_0_12)); + NOR4_X1_LVT i_0_12 (.A1(n_0_685), .A2(aluOp[2]), .A3(aluBypass), .A4(n_0_12), + .ZN(n_0_11)); + OR3_X1_LVT i_0_0 (.A1(n_0_6), .A2(n_0_0), .A3(n_0_11), .ZN(result[0])); + OR4_X1_LVT i_0_703 (.A1(n_0_680), .A2(n_0_673), .A3(n_0_675), .A4(n_0_678), + .ZN(n_0_670)); + INV_X1_LVT i_0_709 (.A(n_0_677), .ZN(n_0_676)); + OR4_X1_LVT i_0_702 (.A1(n_0_679), .A2(n_0_674), .A3(n_0_676), .A4(n_0_671), + .ZN(n_0_669)); + AOI22_X1_LVT i_0_663 (.A1(n_0_688), .A2(op2[27]), .B1(op1[22]), .B2(n_0_686), + .ZN(n_0_630)); + OAI22_X1_LVT i_0_662 (.A1(n_0_694), .A2(op2[2]), .B1(op1[30]), .B2(n_0_716), + .ZN(n_0_629)); + AOI221_X1_LVT i_0_661 (.A(n_0_629), .B1(n_0_711), .B2(op2[26]), .C1(n_0_721), + .C2(op2[14]), .ZN(n_0_628)); + AOI21_X1_LVT i_0_664 (.A(n_0_660), .B1(n_0_690), .B2(op1[19]), .ZN(n_0_631)); + OAI222_X1_LVT i_0_660 (.A1(op1[12]), .A2(n_0_695), .B1(n_0_688), .B2(op2[27]), + .C1(op1[22]), .C2(n_0_686), .ZN(n_0_627)); + AOI21_X1_LVT i_0_659 (.A(n_0_663), .B1(n_0_734), .B2(op2[15]), .ZN(n_0_626)); + OAI211_X1_LVT i_0_658 (.A(n_0_666), .B(n_0_626), .C1(n_0_715), .C2(op1[13]), + .ZN(n_0_625)); + AOI211_X1_LVT i_0_657 (.A(n_0_627), .B(n_0_625), .C1(op1[23]), .C2(n_0_718), + .ZN(n_0_624)); + NAND4_X1_LVT i_0_656 (.A1(n_0_630), .A2(n_0_628), .A3(n_0_631), .A4(n_0_624), + .ZN(n_0_623)); + OAI22_X1_LVT i_0_684 (.A1(n_0_721), .A2(op2[14]), .B1(n_0_722), .B2(op2[9]), + .ZN(n_0_651)); + AOI211_X1_LVT i_0_668 (.A(n_0_651), .B(n_0_654), .C1(n_0_719), .C2(op2[23]), + .ZN(n_0_635)); + NAND2_X1_LVT i_0_667 (.A1(n_0_664), .A2(n_0_657), .ZN(n_0_634)); + NOR3_X1_LVT i_0_666 (.A1(n_0_659), .A2(n_0_656), .A3(n_0_634), .ZN(n_0_633)); + AOI21_X1_LVT i_0_671 (.A(n_0_655), .B1(n_0_739), .B2(op2[16]), .ZN(n_0_638)); + AOI21_X1_LVT i_0_670 (.A(n_0_668), .B1(n_0_736), .B2(op2[24]), .ZN(n_0_637)); + OAI22_X1_LVT i_0_673 (.A1(n_0_735), .A2(op1[10]), .B1(n_0_734), .B2(op2[15]), + .ZN(n_0_640)); + AOI221_X1_LVT i_0_672 (.A(n_0_640), .B1(n_0_732), .B2(op2[17]), .C1(n_0_731), + .C2(op1[5]), .ZN(n_0_639)); + AND3_X1_LVT i_0_669 (.A1(n_0_638), .A2(n_0_637), .A3(n_0_639), .ZN(n_0_636)); + OAI22_X1_LVT i_0_682 (.A1(n_0_703), .A2(op2[0]), .B1(n_0_704), .B2(op2[6]), + .ZN(n_0_649)); + OAI22_X1_LVT i_0_681 (.A1(op2[28]), .A2(n_0_698), .B1(op1[25]), .B2(n_0_697), + .ZN(n_0_648)); + AOI21_X1_LVT i_0_678 (.A(n_0_658), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_645)); + AOI21_X1_LVT i_0_677 (.A(n_0_662), .B1(n_0_735), .B2(op1[10]), .ZN(n_0_644)); + INV_X1_LVT i_0_758 (.A(op2[21]), .ZN(n_0_725)); + OAI22_X1_LVT i_0_683 (.A1(op1[21]), .A2(n_0_725), .B1(n_0_739), .B2(op2[16]), + .ZN(n_0_650)); + AOI221_X1_LVT i_0_676 (.A(n_0_650), .B1(n_0_722), .B2(op2[9]), .C1(op1[7]), + .C2(n_0_712), .ZN(n_0_643)); + OAI21_X1_LVT i_0_680 (.A(n_0_652), .B1(n_0_711), .B2(op2[26]), .ZN(n_0_647)); + AOI221_X1_LVT i_0_679 (.A(n_0_647), .B1(n_0_706), .B2(op2[11]), .C1(n_0_707), + .C2(op1[18]), .ZN(n_0_646)); + NAND4_X1_LVT i_0_675 (.A1(n_0_645), .A2(n_0_644), .A3(n_0_643), .A4(n_0_646), + .ZN(n_0_642)); + NOR3_X1_LVT i_0_674 (.A1(n_0_649), .A2(n_0_648), .A3(n_0_642), .ZN(n_0_641)); + NAND4_X1_LVT i_0_665 (.A1(n_0_635), .A2(n_0_633), .A3(n_0_636), .A4(n_0_641), + .ZN(n_0_632)); + NOR4_X1_LVT i_0_655 (.A1(n_0_670), .A2(n_0_669), .A3(n_0_623), .A4(n_0_632), + .ZN(eqFlag)); +endmodule + +module decoder(CurrentPC, JumpOrBranchPC, JumpOrBranch, DAddr, WData, RData, + Instruction, WrMem, DWidth, Rs1, Rs2, Rd, RRs1, RRs2, WRd, WrReg, Illegal); + input [31:0]CurrentPC; + output [31:0]JumpOrBranchPC; + output JumpOrBranch; + output [31:0]DAddr; + output [31:0]WData; + input [31:0]RData; + input [31:0]Instruction; + output WrMem; + output [1:0]DWidth; + output [4:0]Rs1; + output [4:0]Rs2; + output [4:0]Rd; + input [31:0]RRs1; + input [31:0]RRs2; + output [31:0]WRd; + output WrReg; + output Illegal; + + wire eqFlag; + wire n_5_0; + wire n_5_1; + wire n_5_2; + wire n_5_3; + wire n_5_4; + wire n_5_5; + wire n_5_6; + wire n_5_7; + wire n_5_8; + wire n_5_9; + wire n_5_10; + wire n_5_11; + wire n_5_12; + wire n_5_13; + wire n_5_14; + wire n_5_15; + wire n_5_16; + wire n_5_17; + wire n_5_18; + wire n_5_19; + wire n_5_20; + wire n_5_21; + wire n_5_22; + wire n_5_23; + wire n_5_24; + wire n_5_25; + wire n_5_26; + wire n_5_27; + wire n_5_28; + wire n_5_29; + wire n_5_30; + wire n_5_31; + wire n_5_32; + wire n_5_33; + wire n_17_0; + wire n_17_1; + wire n_17_2; + wire n_17_3; + wire n_17_4; + wire n_17_5; + wire n_17_6; + wire n_17_7; + wire n_17_8; + wire n_17_9; + wire n_17_10; + wire n_17_11; + wire n_17_12; + wire n_17_13; + wire n_17_14; + wire n_17_15; + wire n_17_16; + wire n_17_17; + wire n_17_18; + wire n_17_19; + wire n_17_20; + wire n_17_21; + wire n_17_22; + wire n_17_23; + wire n_17_24; + wire n_17_25; + wire n_17_26; + wire n_17_27; + wire n_17_28; + wire n_17_29; + wire n_17_30; + wire n_17_31; + wire n_17_32; + wire n_18_0; + wire n_18_1; + wire n_18_2; + wire n_18_3; + wire n_18_4; + wire n_18_5; + wire n_18_6; + wire n_18_7; + wire n_18_8; + wire n_18_9; + wire n_18_10; + wire n_18_11; + wire n_18_12; + wire n_18_13; + wire n_18_14; + wire n_18_15; + wire n_18_16; + wire n_18_17; + wire n_18_18; + wire n_18_19; + wire n_18_20; + wire n_18_21; + wire n_18_22; + wire n_18_23; + wire n_18_24; + wire n_18_25; + wire n_18_26; + wire n_18_27; + wire n_18_28; + wire n_18_29; + wire n_18_30; + wire n_18_31; + wire n_18_32; + wire n_0_15; + wire n_0_2; + wire n_0_16; + wire n_0_3; + wire n_0_17; + wire n_0_4; + wire n_0_18; + wire n_0_5; + wire n_0_19; + wire n_0_6; + wire n_0_20; + wire n_0_7; + wire n_0_21; + wire n_0_8; + wire n_0_22; + wire n_0_9; + wire n_0_23; + wire n_0_10; + wire n_0_24; + wire n_0_11; + wire n_0_25; + wire n_0_12; + wire n_0_26; + wire n_0_13; + wire n_0_27; + wire n_0_14; + wire n_0_28; + wire n_0_29; + wire n_0_30; + wire n_0_31; + wire n_0_32; + wire n_0_33; + wire n_0_34; + wire n_0_35; + wire n_0_36; + wire n_0_37; + wire n_0_38; + wire n_0_39; + wire n_0_40; + wire n_0_41; + wire n_0_42; + wire n_0_43; + wire n_0_44; + wire n_0_45; + wire n_0_46; + wire n_0_47; + wire n_0_48; + wire n_0_49; + wire n_0_50; + wire n_0_51; + wire n_0_52; + wire n_0_53; + wire n_0_54; + wire n_0_55; + wire n_0_56; + wire n_0_57; + wire n_0_58; + wire n_0_59; + wire n_0_60; + wire n_0_61; + wire n_0_62; + wire n_0_63; + wire n_0_64; + wire n_0_65; + wire n_0_66; + wire n_0_67; + wire n_0_68; + wire n_0_69; + wire n_0_70; + wire n_0_71; + wire n_0_72; + wire n_0_73; + wire n_0_74; + wire n_0_75; + wire n_0_76; + wire n_0_77; + wire n_0_78; + wire n_0_79; + wire n_0_80; + wire n_0_81; + wire n_0_82; + wire n_0_83; + wire n_0_84; + wire n_0_85; + wire n_0_86; + wire n_0_87; + wire n_0_88; + wire n_0_89; + wire n_0_90; + wire n_0_91; + wire n_0_92; + wire n_0_93; + wire n_0_94; + wire n_0_95; + wire n_0_96; + wire n_0_97; + wire [2:0]aluOp; + wire n_0_98; + wire n_0_99; + wire n_0_100; + wire aluNegAr; + wire n_0_101; + wire n_0_102; + wire n_0_103; + wire n_0_104; + wire n_0_105; + wire aluBypass; + wire n_0_106; + wire [31:0]op1; + wire n_0_107; + wire n_0_108; + wire n_0_109; + wire n_0_110; + wire n_0_111; + wire n_0_112; + wire n_0_113; + wire n_0_114; + wire n_0_115; + wire n_0_116; + wire n_0_117; + wire n_0_118; + wire n_0_119; + wire n_0_120; + wire n_0_121; + wire n_0_122; + wire n_0_123; + wire n_0_124; + wire n_0_125; + wire n_0_126; + wire n_0_127; + wire n_0_128; + wire n_0_129; + wire n_0_130; + wire n_0_131; + wire n_0_132; + wire n_0_133; + wire n_0_134; + wire n_0_135; + wire n_0_136; + wire n_0_137; + wire n_0_138; + wire n_0_139; + wire n_0_140; + wire n_0_141; + wire n_0_142; + wire n_0_143; + wire n_0_144; + wire n_0_145; + wire n_0_146; + wire n_0_147; + wire n_0_148; + wire n_0_149; + wire n_0_150; + wire n_0_151; + wire n_0_152; + wire n_0_153; + wire n_0_154; + wire n_0_155; + wire n_0_156; + wire n_0_157; + wire n_0_158; + wire n_0_159; + wire n_0_160; + wire n_0_161; + wire n_0_162; + wire n_0_163; + wire n_0_164; + wire n_0_165; + wire n_0_166; + wire n_0_167; + wire n_0_168; + wire n_0_169; + wire [31:0]op2; + wire n_0_170; + wire n_0_171; + wire n_0_172; + wire n_0_173; + wire n_0_174; + wire n_0_175; + wire n_0_176; + wire n_0_177; + wire n_0_178; + wire n_0_179; + wire n_0_180; + wire n_0_181; + wire n_0_182; + wire n_0_183; + wire n_0_184; + wire n_0_185; + wire n_0_186; + wire n_0_187; + wire n_0_188; + wire n_0_189; + wire n_0_190; + wire n_0_191; + wire n_0_192; + wire n_0_193; + wire n_0_194; + wire n_0_195; + wire n_0_196; + wire n_0_197; + wire n_0_198; + wire n_0_199; + wire n_0_200; + wire n_0_201; + wire n_0_202; + wire n_0_203; + wire n_0_204; + wire n_0_205; + wire n_0_206; + wire n_0_207; + wire n_0_208; + wire n_0_209; + wire n_0_210; + wire n_0_211; + wire n_0_212; + wire n_0_213; + wire n_0_214; + wire n_0_215; + wire n_0_216; + wire n_0_217; + wire n_0_218; + wire n_0_219; + wire n_0_220; + wire n_0_221; + wire n_0_222; + wire n_0_223; + wire n_0_224; + wire n_0_225; + wire n_0_226; + wire n_0_227; + wire n_0_228; + wire n_0_229; + wire n_0_230; + wire n_0_231; + wire n_0_232; + wire n_0_233; + wire n_0_234; + wire n_0_235; + wire n_0_236; + wire n_0_237; + wire n_0_238; + wire n_0_239; + wire n_0_240; + wire n_0_241; + wire n_0_242; + wire n_0_1; + wire n_0_0; + wire n_0_243; + wire n_0_244; + wire n_0_245; + wire n_0_246; + wire n_0_247; + wire n_0_248; + wire n_0_249; + + INV_X1_LVT i_18_1 (.A(CurrentPC[13]), .ZN(n_18_1)); + XNOR2_X1_LVT i_18_32 (.A(CurrentPC[31]), .B(n_18_1), .ZN(n_18_32)); + INV_X1_LVT i_18_0 (.A(Instruction[31]), .ZN(n_18_0)); + HA_X1_LVT i_18_2 (.A(Instruction[8]), .B(CurrentPC[1]), .CO(n_18_2), .S(n_63)); + FA_X1_LVT i_18_3 (.A(Instruction[9]), .B(CurrentPC[2]), .CI(n_18_2), .CO( + n_18_3), .S(n_64)); + FA_X1_LVT i_18_4 (.A(Instruction[10]), .B(CurrentPC[3]), .CI(n_18_3), + .CO(n_18_4), .S(n_65)); + FA_X1_LVT i_18_5 (.A(Instruction[11]), .B(CurrentPC[4]), .CI(n_18_4), + .CO(n_18_5), .S(n_66)); + FA_X1_LVT i_18_6 (.A(Instruction[25]), .B(CurrentPC[5]), .CI(n_18_5), + .CO(n_18_6), .S(n_67)); + FA_X1_LVT i_18_7 (.A(Instruction[26]), .B(CurrentPC[6]), .CI(n_18_6), + .CO(n_18_7), .S(n_68)); + FA_X1_LVT i_18_8 (.A(Instruction[27]), .B(CurrentPC[7]), .CI(n_18_7), + .CO(n_18_8), .S(n_69)); + FA_X1_LVT i_18_9 (.A(Instruction[28]), .B(CurrentPC[8]), .CI(n_18_8), + .CO(n_18_9), .S(n_70)); + FA_X1_LVT i_18_10 (.A(Instruction[29]), .B(CurrentPC[9]), .CI(n_18_9), + .CO(n_18_10), .S(n_71)); + FA_X1_LVT i_18_11 (.A(Instruction[30]), .B(CurrentPC[10]), .CI(n_18_10), + .CO(n_18_11), .S(n_72)); + FA_X1_LVT i_18_12 (.A(Instruction[7]), .B(CurrentPC[11]), .CI(n_18_11), + .CO(n_18_12), .S(n_73)); + FA_X1_LVT i_18_13 (.A(CurrentPC[12]), .B(Instruction[31]), .CI(n_18_12), + .CO(n_18_13), .S(n_74)); + FA_X1_LVT i_18_14 (.A(n_18_0), .B(n_18_1), .CI(n_18_13), .CO(n_18_14), + .S(n_75)); + FA_X1_LVT i_18_15 (.A(CurrentPC[14]), .B(n_18_1), .CI(n_18_14), .CO(n_18_15), + .S(n_76)); + FA_X1_LVT i_18_16 (.A(CurrentPC[15]), .B(n_18_1), .CI(n_18_15), .CO(n_18_16), + .S(n_77)); + FA_X1_LVT i_18_17 (.A(CurrentPC[16]), .B(n_18_1), .CI(n_18_16), .CO(n_18_17), + .S(n_78)); + FA_X1_LVT i_18_18 (.A(CurrentPC[17]), .B(n_18_1), .CI(n_18_17), .CO(n_18_18), + .S(n_79)); + FA_X1_LVT i_18_19 (.A(CurrentPC[18]), .B(n_18_1), .CI(n_18_18), .CO(n_18_19), + .S(n_80)); + FA_X1_LVT i_18_20 (.A(CurrentPC[19]), .B(n_18_1), .CI(n_18_19), .CO(n_18_20), + .S(n_81)); + FA_X1_LVT i_18_21 (.A(CurrentPC[20]), .B(n_18_1), .CI(n_18_20), .CO(n_18_21), + .S(n_82)); + FA_X1_LVT i_18_22 (.A(CurrentPC[21]), .B(n_18_1), .CI(n_18_21), .CO(n_18_22), + .S(n_83)); + FA_X1_LVT i_18_23 (.A(CurrentPC[22]), .B(n_18_1), .CI(n_18_22), .CO(n_18_23), + .S(n_84)); + FA_X1_LVT i_18_24 (.A(CurrentPC[23]), .B(n_18_1), .CI(n_18_23), .CO(n_18_24), + .S(n_85)); + FA_X1_LVT i_18_25 (.A(CurrentPC[24]), .B(n_18_1), .CI(n_18_24), .CO(n_18_25), + .S(n_86)); + FA_X1_LVT i_18_26 (.A(CurrentPC[25]), .B(n_18_1), .CI(n_18_25), .CO(n_18_26), + .S(n_87)); + FA_X1_LVT i_18_27 (.A(CurrentPC[26]), .B(n_18_1), .CI(n_18_26), .CO(n_18_27), + .S(n_88)); + FA_X1_LVT i_18_28 (.A(CurrentPC[27]), .B(n_18_1), .CI(n_18_27), .CO(n_18_28), + .S(n_89)); + FA_X1_LVT i_18_29 (.A(CurrentPC[28]), .B(n_18_1), .CI(n_18_28), .CO(n_18_29), + .S(n_90)); + FA_X1_LVT i_18_30 (.A(CurrentPC[29]), .B(n_18_1), .CI(n_18_29), .CO(n_18_30), + .S(n_91)); + FA_X1_LVT i_18_31 (.A(CurrentPC[30]), .B(n_18_1), .CI(n_18_30), .CO(n_18_31), + .S(n_92)); + XNOR2_X1_LVT i_18_33 (.A(n_18_32), .B(n_18_31), .ZN(n_93)); + INV_X1_LVT i_0_350 (.A(Instruction[3]), .ZN(n_0_243)); + NAND3_X1_LVT i_0_343 (.A1(n_0_243), .A2(Instruction[0]), .A3(Instruction[1]), + .ZN(n_0_238)); + OR2_X1_LVT i_0_332 (.A1(n_0_238), .A2(Instruction[2]), .ZN(n_0_228)); + INV_X1_LVT i_0_351 (.A(Instruction[5]), .ZN(n_0_244)); + NOR2_X1_LVT i_0_340 (.A1(n_0_244), .A2(Instruction[4]), .ZN(n_0_235)); + NAND2_X1_LVT i_0_329 (.A1(Instruction[6]), .A2(n_0_235), .ZN(n_0_225)); + INV_X1_LVT i_0_354 (.A(Instruction[13]), .ZN(n_0_247)); + NOR2_X1_LVT i_0_345 (.A1(n_0_247), .A2(Instruction[14]), .ZN(n_0_240)); + NOR3_X1_LVT i_0_118 (.A1(n_0_228), .A2(n_0_225), .A3(n_0_240), .ZN(n_0_99)); + NAND3_X1_LVT i_0_346 (.A1(Instruction[0]), .A2(Instruction[1]), .A3( + Instruction[2]), .ZN(n_0_241)); + NOR2_X1_LVT i_0_328 (.A1(n_0_241), .A2(n_0_225), .ZN(n_0_224)); + INV_X1_LVT i_0_356 (.A(n_0_224), .ZN(n_0_249)); + NOR2_X1_LVT i_0_108 (.A1(n_0_243), .A2(n_0_249), .ZN(n_0_91)); + INV_X1_LVT i_17_1 (.A(CurrentPC[21]), .ZN(n_17_1)); + XNOR2_X1_LVT i_17_32 (.A(CurrentPC[31]), .B(n_17_1), .ZN(n_17_32)); + INV_X1_LVT i_17_0 (.A(Instruction[31]), .ZN(n_17_0)); + HA_X1_LVT i_17_2 (.A(Instruction[21]), .B(CurrentPC[1]), .CO(n_17_2), + .S(n_32)); + FA_X1_LVT i_17_3 (.A(Instruction[22]), .B(CurrentPC[2]), .CI(n_17_2), + .CO(n_17_3), .S(n_33)); + FA_X1_LVT i_17_4 (.A(Instruction[23]), .B(CurrentPC[3]), .CI(n_17_3), + .CO(n_17_4), .S(n_34)); + FA_X1_LVT i_17_5 (.A(Instruction[24]), .B(CurrentPC[4]), .CI(n_17_4), + .CO(n_17_5), .S(n_35)); + FA_X1_LVT i_17_6 (.A(Instruction[25]), .B(CurrentPC[5]), .CI(n_17_5), + .CO(n_17_6), .S(n_36)); + FA_X1_LVT i_17_7 (.A(Instruction[26]), .B(CurrentPC[6]), .CI(n_17_6), + .CO(n_17_7), .S(n_37)); + FA_X1_LVT i_17_8 (.A(Instruction[27]), .B(CurrentPC[7]), .CI(n_17_7), + .CO(n_17_8), .S(n_38)); + FA_X1_LVT i_17_9 (.A(Instruction[28]), .B(CurrentPC[8]), .CI(n_17_8), + .CO(n_17_9), .S(n_39)); + FA_X1_LVT i_17_10 (.A(Instruction[29]), .B(CurrentPC[9]), .CI(n_17_9), + .CO(n_17_10), .S(n_40)); + FA_X1_LVT i_17_11 (.A(Instruction[30]), .B(CurrentPC[10]), .CI(n_17_10), + .CO(n_17_11), .S(n_41)); + FA_X1_LVT i_17_12 (.A(Instruction[20]), .B(CurrentPC[11]), .CI(n_17_11), + .CO(n_17_12), .S(n_42)); + FA_X1_LVT i_17_13 (.A(Instruction[12]), .B(CurrentPC[12]), .CI(n_17_12), + .CO(n_17_13), .S(n_43)); + FA_X1_LVT i_17_14 (.A(Instruction[13]), .B(CurrentPC[13]), .CI(n_17_13), + .CO(n_17_14), .S(n_44)); + FA_X1_LVT i_17_15 (.A(Instruction[14]), .B(CurrentPC[14]), .CI(n_17_14), + .CO(n_17_15), .S(n_45)); + FA_X1_LVT i_17_16 (.A(Instruction[15]), .B(CurrentPC[15]), .CI(n_17_15), + .CO(n_17_16), .S(n_46)); + FA_X1_LVT i_17_17 (.A(Instruction[16]), .B(CurrentPC[16]), .CI(n_17_16), + .CO(n_17_17), .S(n_47)); + FA_X1_LVT i_17_18 (.A(Instruction[17]), .B(CurrentPC[17]), .CI(n_17_17), + .CO(n_17_18), .S(n_48)); + FA_X1_LVT i_17_19 (.A(Instruction[18]), .B(CurrentPC[18]), .CI(n_17_18), + .CO(n_17_19), .S(n_49)); + FA_X1_LVT i_17_20 (.A(Instruction[19]), .B(CurrentPC[19]), .CI(n_17_19), + .CO(n_17_20), .S(n_50)); + FA_X1_LVT i_17_21 (.A(CurrentPC[20]), .B(Instruction[31]), .CI(n_17_20), + .CO(n_17_21), .S(n_51)); + FA_X1_LVT i_17_22 (.A(n_17_0), .B(n_17_1), .CI(n_17_21), .CO(n_17_22), + .S(n_52)); + FA_X1_LVT i_17_23 (.A(CurrentPC[22]), .B(n_17_1), .CI(n_17_22), .CO(n_17_23), + .S(n_53)); + FA_X1_LVT i_17_24 (.A(CurrentPC[23]), .B(n_17_1), .CI(n_17_23), .CO(n_17_24), + .S(n_54)); + FA_X1_LVT i_17_25 (.A(CurrentPC[24]), .B(n_17_1), .CI(n_17_24), .CO(n_17_25), + .S(n_55)); + FA_X1_LVT i_17_26 (.A(CurrentPC[25]), .B(n_17_1), .CI(n_17_25), .CO(n_17_26), + .S(n_56)); + FA_X1_LVT i_17_27 (.A(CurrentPC[26]), .B(n_17_1), .CI(n_17_26), .CO(n_17_27), + .S(n_57)); + FA_X1_LVT i_17_28 (.A(CurrentPC[27]), .B(n_17_1), .CI(n_17_27), .CO(n_17_28), + .S(n_58)); + FA_X1_LVT i_17_29 (.A(CurrentPC[28]), .B(n_17_1), .CI(n_17_28), .CO(n_17_29), + .S(n_59)); + FA_X1_LVT i_17_30 (.A(CurrentPC[29]), .B(n_17_1), .CI(n_17_29), .CO(n_17_30), + .S(n_60)); + FA_X1_LVT i_17_31 (.A(CurrentPC[30]), .B(n_17_1), .CI(n_17_30), .CO(n_17_31), + .S(n_61)); + XNOR2_X1_LVT i_17_33 (.A(n_17_32), .B(n_17_31), .ZN(n_62)); + INV_X1_LVT i_5_1 (.A(RRs1[12]), .ZN(n_5_1)); + XNOR2_X1_LVT i_5_33 (.A(RRs1[31]), .B(n_5_1), .ZN(n_5_33)); + INV_X1_LVT i_5_0 (.A(Instruction[31]), .ZN(n_5_0)); + HA_X1_LVT i_5_2 (.A(Instruction[20]), .B(RRs1[0]), .CO(n_5_2), .S(n_0)); + FA_X1_LVT i_5_3 (.A(Instruction[21]), .B(RRs1[1]), .CI(n_5_2), .CO(n_5_3), + .S(n_1)); + FA_X1_LVT i_5_4 (.A(Instruction[22]), .B(RRs1[2]), .CI(n_5_3), .CO(n_5_4), + .S(n_2)); + FA_X1_LVT i_5_5 (.A(Instruction[23]), .B(RRs1[3]), .CI(n_5_4), .CO(n_5_5), + .S(n_3)); + FA_X1_LVT i_5_6 (.A(Instruction[24]), .B(RRs1[4]), .CI(n_5_5), .CO(n_5_6), + .S(n_4)); + FA_X1_LVT i_5_7 (.A(Instruction[25]), .B(RRs1[5]), .CI(n_5_6), .CO(n_5_7), + .S(n_5)); + FA_X1_LVT i_5_8 (.A(Instruction[26]), .B(RRs1[6]), .CI(n_5_7), .CO(n_5_8), + .S(n_6)); + FA_X1_LVT i_5_9 (.A(Instruction[27]), .B(RRs1[7]), .CI(n_5_8), .CO(n_5_9), + .S(n_7)); + FA_X1_LVT i_5_10 (.A(Instruction[28]), .B(RRs1[8]), .CI(n_5_9), .CO(n_5_10), + .S(n_8)); + FA_X1_LVT i_5_11 (.A(Instruction[29]), .B(RRs1[9]), .CI(n_5_10), .CO(n_5_11), + .S(n_9)); + FA_X1_LVT i_5_12 (.A(Instruction[30]), .B(RRs1[10]), .CI(n_5_11), .CO(n_5_12), + .S(n_10)); + FA_X1_LVT i_5_13 (.A(RRs1[11]), .B(Instruction[31]), .CI(n_5_12), .CO(n_5_13), + .S(n_11)); + FA_X1_LVT i_5_14 (.A(n_5_0), .B(n_5_1), .CI(n_5_13), .CO(n_5_14), .S(n_12)); + FA_X1_LVT i_5_15 (.A(RRs1[13]), .B(n_5_1), .CI(n_5_14), .CO(n_5_15), .S(n_13)); + FA_X1_LVT i_5_16 (.A(RRs1[14]), .B(n_5_1), .CI(n_5_15), .CO(n_5_16), .S(n_14)); + FA_X1_LVT i_5_17 (.A(RRs1[15]), .B(n_5_1), .CI(n_5_16), .CO(n_5_17), .S(n_15)); + FA_X1_LVT i_5_18 (.A(RRs1[16]), .B(n_5_1), .CI(n_5_17), .CO(n_5_18), .S(n_16)); + FA_X1_LVT i_5_19 (.A(RRs1[17]), .B(n_5_1), .CI(n_5_18), .CO(n_5_19), .S(n_17)); + FA_X1_LVT i_5_20 (.A(RRs1[18]), .B(n_5_1), .CI(n_5_19), .CO(n_5_20), .S(n_18)); + FA_X1_LVT i_5_21 (.A(RRs1[19]), .B(n_5_1), .CI(n_5_20), .CO(n_5_21), .S(n_19)); + FA_X1_LVT i_5_22 (.A(RRs1[20]), .B(n_5_1), .CI(n_5_21), .CO(n_5_22), .S(n_20)); + FA_X1_LVT i_5_23 (.A(RRs1[21]), .B(n_5_1), .CI(n_5_22), .CO(n_5_23), .S(n_21)); + FA_X1_LVT i_5_24 (.A(RRs1[22]), .B(n_5_1), .CI(n_5_23), .CO(n_5_24), .S(n_22)); + FA_X1_LVT i_5_25 (.A(RRs1[23]), .B(n_5_1), .CI(n_5_24), .CO(n_5_25), .S(n_23)); + FA_X1_LVT i_5_26 (.A(RRs1[24]), .B(n_5_1), .CI(n_5_25), .CO(n_5_26), .S(n_24)); + FA_X1_LVT i_5_27 (.A(RRs1[25]), .B(n_5_1), .CI(n_5_26), .CO(n_5_27), .S(n_25)); + FA_X1_LVT i_5_28 (.A(RRs1[26]), .B(n_5_1), .CI(n_5_27), .CO(n_5_28), .S(n_26)); + FA_X1_LVT i_5_29 (.A(RRs1[27]), .B(n_5_1), .CI(n_5_28), .CO(n_5_29), .S(n_27)); + FA_X1_LVT i_5_30 (.A(RRs1[28]), .B(n_5_1), .CI(n_5_29), .CO(n_5_30), .S(n_28)); + FA_X1_LVT i_5_31 (.A(RRs1[29]), .B(n_5_1), .CI(n_5_30), .CO(n_5_31), .S(n_29)); + FA_X1_LVT i_5_32 (.A(RRs1[30]), .B(n_5_1), .CI(n_5_31), .CO(n_5_32), .S(n_30)); + XNOR2_X1_LVT i_5_34 (.A(n_5_33), .B(n_5_32), .ZN(n_31)); + NOR2_X1_LVT i_0_107 (.A1(n_0_249), .A2(Instruction[3]), .ZN(n_0_90)); + AOI222_X1_LVT i_0_106 (.A1(n_93), .A2(n_0_99), .B1(n_0_91), .B2(n_62), + .C1(n_31), .C2(n_0_90), .ZN(n_0_89)); + INV_X1_LVT i_0_355 (.A(Instruction[6]), .ZN(n_0_248)); + NAND2_X1_LVT i_0_339 (.A1(n_0_248), .A2(Instruction[4]), .ZN(n_0_234)); + INV_X1_LVT i_0_338 (.A(n_0_234), .ZN(n_0_233)); + OAI21_X1_LVT i_0_341 (.A(Instruction[13]), .B1(Instruction[14]), .B2( + Instruction[12]), .ZN(n_0_236)); + AOI211_X1_LVT i_0_337 (.A(n_0_235), .B(n_0_233), .C1(n_0_248), .C2(n_0_236), + .ZN(n_0_232)); + INV_X1_LVT i_0_352 (.A(Instruction[4]), .ZN(n_0_245)); + NAND2_X1_LVT i_0_344 (.A1(n_0_245), .A2(Instruction[2]), .ZN(n_0_239)); + AOI21_X1_LVT i_0_335 (.A(Instruction[6]), .B1(n_0_243), .B2(n_0_239), + .ZN(n_0_230)); + NOR2_X1_LVT i_0_334 (.A1(n_0_232), .A2(n_0_230), .ZN(n_0_229)); + NAND2_X1_LVT i_0_342 (.A1(n_0_241), .A2(n_0_238), .ZN(n_0_237)); + NAND2_X1_LVT i_0_336 (.A1(Instruction[6]), .A2(n_0_240), .ZN(n_0_231)); + OAI211_X1_LVT i_0_333 (.A(n_0_229), .B(n_0_237), .C1(Instruction[2]), + .C2(n_0_231), .ZN(Illegal)); + NAND2_X1_LVT i_0_109 (.A1(Illegal), .A2(CurrentPC[31]), .ZN(n_0_92)); + NAND2_X1_LVT i_0_105 (.A1(n_0_89), .A2(n_0_92), .ZN(JumpOrBranchPC[31])); + AOI222_X1_LVT i_0_103 (.A1(n_92), .A2(n_0_99), .B1(n_0_91), .B2(n_61), + .C1(n_30), .C2(n_0_90), .ZN(n_0_87)); + NAND2_X1_LVT i_0_104 (.A1(Illegal), .A2(CurrentPC[30]), .ZN(n_0_88)); + NAND2_X1_LVT i_0_102 (.A1(n_0_87), .A2(n_0_88), .ZN(JumpOrBranchPC[30])); + AOI222_X1_LVT i_0_100 (.A1(n_91), .A2(n_0_99), .B1(n_0_91), .B2(n_60), + .C1(n_29), .C2(n_0_90), .ZN(n_0_85)); + NAND2_X1_LVT i_0_101 (.A1(Illegal), .A2(CurrentPC[29]), .ZN(n_0_86)); + NAND2_X1_LVT i_0_99 (.A1(n_0_85), .A2(n_0_86), .ZN(JumpOrBranchPC[29])); + AOI222_X1_LVT i_0_97 (.A1(n_90), .A2(n_0_99), .B1(n_0_91), .B2(n_59), + .C1(n_28), .C2(n_0_90), .ZN(n_0_83)); + NAND2_X1_LVT i_0_98 (.A1(Illegal), .A2(CurrentPC[28]), .ZN(n_0_84)); + NAND2_X1_LVT i_0_96 (.A1(n_0_83), .A2(n_0_84), .ZN(JumpOrBranchPC[28])); + AOI222_X1_LVT i_0_94 (.A1(n_89), .A2(n_0_99), .B1(n_0_91), .B2(n_58), + .C1(n_27), .C2(n_0_90), .ZN(n_0_81)); + NAND2_X1_LVT i_0_95 (.A1(Illegal), .A2(CurrentPC[27]), .ZN(n_0_82)); + NAND2_X1_LVT i_0_93 (.A1(n_0_81), .A2(n_0_82), .ZN(JumpOrBranchPC[27])); + AOI222_X1_LVT i_0_91 (.A1(n_88), .A2(n_0_99), .B1(n_0_91), .B2(n_57), + .C1(n_26), .C2(n_0_90), .ZN(n_0_79)); + NAND2_X1_LVT i_0_92 (.A1(Illegal), .A2(CurrentPC[26]), .ZN(n_0_80)); + NAND2_X1_LVT i_0_90 (.A1(n_0_79), .A2(n_0_80), .ZN(JumpOrBranchPC[26])); + AOI222_X1_LVT i_0_88 (.A1(n_87), .A2(n_0_99), .B1(n_0_91), .B2(n_56), + .C1(n_25), .C2(n_0_90), .ZN(n_0_77)); + NAND2_X1_LVT i_0_89 (.A1(Illegal), .A2(CurrentPC[25]), .ZN(n_0_78)); + NAND2_X1_LVT i_0_87 (.A1(n_0_77), .A2(n_0_78), .ZN(JumpOrBranchPC[25])); + AOI222_X1_LVT i_0_85 (.A1(n_86), .A2(n_0_99), .B1(n_0_91), .B2(n_55), + .C1(n_24), .C2(n_0_90), .ZN(n_0_75)); + NAND2_X1_LVT i_0_86 (.A1(Illegal), .A2(CurrentPC[24]), .ZN(n_0_76)); + NAND2_X1_LVT i_0_84 (.A1(n_0_75), .A2(n_0_76), .ZN(JumpOrBranchPC[24])); + AOI222_X1_LVT i_0_82 (.A1(n_85), .A2(n_0_99), .B1(n_0_91), .B2(n_54), + .C1(n_23), .C2(n_0_90), .ZN(n_0_73)); + NAND2_X1_LVT i_0_83 (.A1(Illegal), .A2(CurrentPC[23]), .ZN(n_0_74)); + NAND2_X1_LVT i_0_81 (.A1(n_0_73), .A2(n_0_74), .ZN(JumpOrBranchPC[23])); + AOI222_X1_LVT i_0_79 (.A1(n_84), .A2(n_0_99), .B1(n_0_91), .B2(n_53), + .C1(n_22), .C2(n_0_90), .ZN(n_0_71)); + NAND2_X1_LVT i_0_80 (.A1(Illegal), .A2(CurrentPC[22]), .ZN(n_0_72)); + NAND2_X1_LVT i_0_78 (.A1(n_0_71), .A2(n_0_72), .ZN(JumpOrBranchPC[22])); + AOI222_X1_LVT i_0_76 (.A1(n_83), .A2(n_0_99), .B1(n_0_91), .B2(n_52), + .C1(n_21), .C2(n_0_90), .ZN(n_0_69)); + NAND2_X1_LVT i_0_77 (.A1(Illegal), .A2(CurrentPC[21]), .ZN(n_0_70)); + NAND2_X1_LVT i_0_75 (.A1(n_0_69), .A2(n_0_70), .ZN(JumpOrBranchPC[21])); + AOI222_X1_LVT i_0_73 (.A1(n_82), .A2(n_0_99), .B1(n_0_91), .B2(n_51), + .C1(n_20), .C2(n_0_90), .ZN(n_0_67)); + NAND2_X1_LVT i_0_74 (.A1(Illegal), .A2(CurrentPC[20]), .ZN(n_0_68)); + NAND2_X1_LVT i_0_72 (.A1(n_0_67), .A2(n_0_68), .ZN(JumpOrBranchPC[20])); + AOI222_X1_LVT i_0_70 (.A1(n_81), .A2(n_0_99), .B1(n_0_91), .B2(n_50), + .C1(n_19), .C2(n_0_90), .ZN(n_0_65)); + NAND2_X1_LVT i_0_71 (.A1(Illegal), .A2(CurrentPC[19]), .ZN(n_0_66)); + NAND2_X1_LVT i_0_69 (.A1(n_0_65), .A2(n_0_66), .ZN(JumpOrBranchPC[19])); + AOI222_X1_LVT i_0_67 (.A1(n_80), .A2(n_0_99), .B1(n_0_91), .B2(n_49), + .C1(n_18), .C2(n_0_90), .ZN(n_0_63)); + NAND2_X1_LVT i_0_68 (.A1(Illegal), .A2(CurrentPC[18]), .ZN(n_0_64)); + NAND2_X1_LVT i_0_66 (.A1(n_0_63), .A2(n_0_64), .ZN(JumpOrBranchPC[18])); + AOI222_X1_LVT i_0_64 (.A1(n_79), .A2(n_0_99), .B1(n_0_91), .B2(n_48), + .C1(n_17), .C2(n_0_90), .ZN(n_0_61)); + NAND2_X1_LVT i_0_65 (.A1(Illegal), .A2(CurrentPC[17]), .ZN(n_0_62)); + NAND2_X1_LVT i_0_63 (.A1(n_0_61), .A2(n_0_62), .ZN(JumpOrBranchPC[17])); + AOI222_X1_LVT i_0_61 (.A1(n_78), .A2(n_0_99), .B1(n_0_91), .B2(n_47), + .C1(n_16), .C2(n_0_90), .ZN(n_0_59)); + NAND2_X1_LVT i_0_62 (.A1(Illegal), .A2(CurrentPC[16]), .ZN(n_0_60)); + NAND2_X1_LVT i_0_60 (.A1(n_0_59), .A2(n_0_60), .ZN(JumpOrBranchPC[16])); + AOI222_X1_LVT i_0_58 (.A1(n_77), .A2(n_0_99), .B1(n_0_91), .B2(n_46), + .C1(n_15), .C2(n_0_90), .ZN(n_0_57)); + NAND2_X1_LVT i_0_59 (.A1(Illegal), .A2(CurrentPC[15]), .ZN(n_0_58)); + NAND2_X1_LVT i_0_57 (.A1(n_0_57), .A2(n_0_58), .ZN(JumpOrBranchPC[15])); + AOI222_X1_LVT i_0_55 (.A1(n_76), .A2(n_0_99), .B1(n_0_91), .B2(n_45), + .C1(n_14), .C2(n_0_90), .ZN(n_0_55)); + NAND2_X1_LVT i_0_56 (.A1(Illegal), .A2(CurrentPC[14]), .ZN(n_0_56)); + NAND2_X1_LVT i_0_54 (.A1(n_0_55), .A2(n_0_56), .ZN(JumpOrBranchPC[14])); + AOI222_X1_LVT i_0_52 (.A1(n_75), .A2(n_0_99), .B1(n_0_91), .B2(n_44), + .C1(n_13), .C2(n_0_90), .ZN(n_0_53)); + NAND2_X1_LVT i_0_53 (.A1(Illegal), .A2(CurrentPC[13]), .ZN(n_0_54)); + NAND2_X1_LVT i_0_51 (.A1(n_0_53), .A2(n_0_54), .ZN(JumpOrBranchPC[13])); + AOI222_X1_LVT i_0_49 (.A1(n_74), .A2(n_0_99), .B1(n_0_91), .B2(n_43), + .C1(n_12), .C2(n_0_90), .ZN(n_0_51)); + NAND2_X1_LVT i_0_50 (.A1(Illegal), .A2(CurrentPC[12]), .ZN(n_0_52)); + NAND2_X1_LVT i_0_48 (.A1(n_0_51), .A2(n_0_52), .ZN(JumpOrBranchPC[12])); + AOI222_X1_LVT i_0_46 (.A1(n_73), .A2(n_0_99), .B1(n_0_91), .B2(n_42), + .C1(n_11), .C2(n_0_90), .ZN(n_0_49)); + NAND2_X1_LVT i_0_47 (.A1(Illegal), .A2(CurrentPC[11]), .ZN(n_0_50)); + NAND2_X1_LVT i_0_45 (.A1(n_0_49), .A2(n_0_50), .ZN(JumpOrBranchPC[11])); + AOI222_X1_LVT i_0_43 (.A1(n_72), .A2(n_0_99), .B1(n_0_91), .B2(n_41), + .C1(n_10), .C2(n_0_90), .ZN(n_0_47)); + NAND2_X1_LVT i_0_44 (.A1(Illegal), .A2(CurrentPC[10]), .ZN(n_0_48)); + NAND2_X1_LVT i_0_42 (.A1(n_0_47), .A2(n_0_48), .ZN(JumpOrBranchPC[10])); + AOI222_X1_LVT i_0_40 (.A1(n_71), .A2(n_0_99), .B1(n_0_91), .B2(n_40), + .C1(n_9), .C2(n_0_90), .ZN(n_0_45)); + NAND2_X1_LVT i_0_41 (.A1(Illegal), .A2(CurrentPC[9]), .ZN(n_0_46)); + NAND2_X1_LVT i_0_39 (.A1(n_0_45), .A2(n_0_46), .ZN(JumpOrBranchPC[9])); + AOI222_X1_LVT i_0_37 (.A1(n_70), .A2(n_0_99), .B1(n_0_91), .B2(n_39), + .C1(n_8), .C2(n_0_90), .ZN(n_0_43)); + NAND2_X1_LVT i_0_38 (.A1(Illegal), .A2(CurrentPC[8]), .ZN(n_0_44)); + NAND2_X1_LVT i_0_36 (.A1(n_0_43), .A2(n_0_44), .ZN(JumpOrBranchPC[8])); + AOI222_X1_LVT i_0_34 (.A1(n_69), .A2(n_0_99), .B1(n_0_91), .B2(n_38), + .C1(n_7), .C2(n_0_90), .ZN(n_0_41)); + NAND2_X1_LVT i_0_35 (.A1(Illegal), .A2(CurrentPC[7]), .ZN(n_0_42)); + NAND2_X1_LVT i_0_33 (.A1(n_0_41), .A2(n_0_42), .ZN(JumpOrBranchPC[7])); + AOI222_X1_LVT i_0_31 (.A1(n_68), .A2(n_0_99), .B1(n_0_91), .B2(n_37), + .C1(n_6), .C2(n_0_90), .ZN(n_0_39)); + NAND2_X1_LVT i_0_32 (.A1(Illegal), .A2(CurrentPC[6]), .ZN(n_0_40)); + NAND2_X1_LVT i_0_30 (.A1(n_0_39), .A2(n_0_40), .ZN(JumpOrBranchPC[6])); + AOI222_X1_LVT i_0_28 (.A1(n_67), .A2(n_0_99), .B1(n_0_91), .B2(n_36), + .C1(n_5), .C2(n_0_90), .ZN(n_0_37)); + NAND2_X1_LVT i_0_29 (.A1(Illegal), .A2(CurrentPC[5]), .ZN(n_0_38)); + NAND2_X1_LVT i_0_27 (.A1(n_0_37), .A2(n_0_38), .ZN(JumpOrBranchPC[5])); + AOI222_X1_LVT i_0_25 (.A1(n_66), .A2(n_0_99), .B1(n_0_91), .B2(n_35), + .C1(n_4), .C2(n_0_90), .ZN(n_0_35)); + NAND2_X1_LVT i_0_26 (.A1(Illegal), .A2(CurrentPC[4]), .ZN(n_0_36)); + NAND2_X1_LVT i_0_24 (.A1(n_0_35), .A2(n_0_36), .ZN(JumpOrBranchPC[4])); + AOI222_X1_LVT i_0_22 (.A1(n_65), .A2(n_0_99), .B1(n_0_91), .B2(n_34), + .C1(n_3), .C2(n_0_90), .ZN(n_0_33)); + NAND2_X1_LVT i_0_23 (.A1(Illegal), .A2(CurrentPC[3]), .ZN(n_0_34)); + NAND2_X1_LVT i_0_21 (.A1(n_0_33), .A2(n_0_34), .ZN(JumpOrBranchPC[3])); + AOI222_X1_LVT i_0_19 (.A1(n_64), .A2(n_0_99), .B1(n_0_91), .B2(n_33), + .C1(n_2), .C2(n_0_90), .ZN(n_0_31)); + NAND2_X1_LVT i_0_20 (.A1(Illegal), .A2(CurrentPC[2]), .ZN(n_0_32)); + NAND2_X1_LVT i_0_18 (.A1(n_0_31), .A2(n_0_32), .ZN(JumpOrBranchPC[2])); + AOI222_X1_LVT i_0_16 (.A1(n_63), .A2(n_0_99), .B1(n_0_91), .B2(n_32), + .C1(n_1), .C2(n_0_90), .ZN(n_0_29)); + NAND2_X1_LVT i_0_17 (.A1(Illegal), .A2(CurrentPC[1]), .ZN(n_0_30)); + NAND2_X1_LVT i_0_15 (.A1(n_0_29), .A2(n_0_30), .ZN(JumpOrBranchPC[1])); + NOR2_X1_LVT i_0_112 (.A1(n_0_232), .A2(n_0_238), .ZN(n_0_94)); + OAI221_X1_LVT i_0_14 (.A(n_0_94), .B1(n_0_225), .B2(Instruction[2]), .C1( + Instruction[6]), .C2(n_0_239), .ZN(n_0_28)); + AND2_X1_LVT i_0_13 (.A1(n_0_28), .A2(CurrentPC[0]), .ZN(JumpOrBranchPC[0])); + NOR2_X1_LVT i_0_221 (.A1(Instruction[13]), .A2(Instruction[14]), .ZN(n_0_166)); + NOR3_X1_LVT i_0_293 (.A1(n_0_241), .A2(n_0_234), .A3(Instruction[3]), + .ZN(n_0_206)); + AND2_X1_LVT i_0_292 (.A1(n_0_206), .A2(n_0_244), .ZN(n_0_205)); + NOR3_X1_LVT i_0_330 (.A1(n_0_248), .A2(n_0_244), .A3(Instruction[4]), + .ZN(n_0_226)); + AOI21_X1_LVT i_0_121 (.A(n_0_205), .B1(n_0_226), .B2(n_0_237), .ZN(n_0_100)); + AND2_X1_LVT i_0_120 (.A1(Instruction[14]), .A2(n_0_100), .ZN(aluOp[2])); + OAI33_X1_LVT i_0_119 (.A1(n_0_205), .A2(n_0_247), .A3(n_0_224), .B1( + Instruction[2]), .B2(n_0_238), .B3(n_0_225), .ZN(aluOp[1])); + AOI22_X1_LVT i_0_117 (.A1(Instruction[12]), .A2(n_0_100), .B1(n_0_99), + .B2(Instruction[13]), .ZN(n_0_98)); + INV_X1_LVT i_0_116 (.A(n_0_98), .ZN(aluOp[0])); + OR2_X1_LVT i_0_327 (.A1(n_0_238), .A2(n_0_234), .ZN(n_0_223)); + NOR4_X1_LVT i_0_125 (.A1(Instruction[28]), .A2(Instruction[27]), .A3( + Instruction[26]), .A4(Instruction[25]), .ZN(n_0_103)); + INV_X1_LVT i_0_347 (.A(Instruction[30]), .ZN(n_0_242)); + NOR4_X1_LVT i_0_124 (.A1(Instruction[13]), .A2(n_0_242), .A3(Instruction[29]), + .A4(Instruction[31]), .ZN(n_0_102)); + NAND2_X1_LVT i_0_123 (.A1(n_0_103), .A2(n_0_102), .ZN(n_0_101)); + NOR3_X1_LVT i_0_127 (.A1(n_0_244), .A2(Instruction[12]), .A3(Instruction[14]), + .ZN(n_0_105)); + AOI21_X1_LVT i_0_126 (.A(n_0_105), .B1(Instruction[12]), .B2(Instruction[14]), + .ZN(n_0_104)); + NOR4_X1_LVT i_0_122 (.A1(n_0_223), .A2(n_0_101), .A3(n_0_104), .A4( + Instruction[2]), .ZN(aluNegAr)); + OR3_X1_LVT i_0_325 (.A1(n_0_228), .A2(Instruction[4]), .A3(Instruction[6]), + .ZN(n_0_222)); + NOR2_X1_LVT i_0_321 (.A1(n_0_222), .A2(Instruction[5]), .ZN(n_0_221)); + NOR3_X1_LVT i_0_224 (.A1(n_0_224), .A2(n_0_221), .A3(n_0_206), .ZN(n_0_169)); + NOR3_X1_LVT i_0_129 (.A1(n_0_234), .A2(Instruction[3]), .A3(Instruction[5]), + .ZN(n_0_106)); + NOR3_X1_LVT i_0_128 (.A1(n_0_226), .A2(n_0_169), .A3(n_0_106), .ZN(aluBypass)); + AOI22_X1_LVT i_0_223 (.A1(CurrentPC[31]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[31]), .ZN(n_0_168)); + NOR3_X1_LVT i_0_219 (.A1(n_0_247), .A2(n_0_222), .A3(Instruction[5]), + .ZN(n_0_164)); + AOI22_X1_LVT i_0_218 (.A1(RRs1[31]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[31]), .ZN(n_0_163)); + MUX2_X1_LVT i_0_222 (.A(RData[7]), .B(RData[15]), .S(Instruction[12]), + .Z(n_0_167)); + NAND3_X1_LVT i_0_220 (.A1(n_0_221), .A2(n_0_167), .A3(n_0_166), .ZN(n_0_165)); + NAND3_X1_LVT i_0_217 (.A1(n_0_168), .A2(n_0_163), .A3(n_0_165), .ZN(op1[31])); + AOI22_X1_LVT i_0_216 (.A1(RRs1[30]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[30]), .ZN(n_0_162)); + AOI22_X1_LVT i_0_215 (.A1(CurrentPC[30]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[30]), .ZN(n_0_161)); + NAND3_X1_LVT i_0_214 (.A1(n_0_162), .A2(n_0_161), .A3(n_0_165), .ZN(op1[30])); + AOI22_X1_LVT i_0_213 (.A1(RRs1[29]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[29]), .ZN(n_0_160)); + AOI22_X1_LVT i_0_212 (.A1(CurrentPC[29]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[29]), .ZN(n_0_159)); + NAND3_X1_LVT i_0_211 (.A1(n_0_160), .A2(n_0_159), .A3(n_0_165), .ZN(op1[29])); + AOI22_X1_LVT i_0_210 (.A1(RRs1[28]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[28]), .ZN(n_0_158)); + AOI22_X1_LVT i_0_209 (.A1(CurrentPC[28]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[28]), .ZN(n_0_157)); + NAND3_X1_LVT i_0_208 (.A1(n_0_158), .A2(n_0_157), .A3(n_0_165), .ZN(op1[28])); + AOI22_X1_LVT i_0_207 (.A1(RRs1[27]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[27]), .ZN(n_0_156)); + AOI22_X1_LVT i_0_206 (.A1(CurrentPC[27]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[27]), .ZN(n_0_155)); + NAND3_X1_LVT i_0_205 (.A1(n_0_156), .A2(n_0_155), .A3(n_0_165), .ZN(op1[27])); + AOI22_X1_LVT i_0_204 (.A1(RRs1[26]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[26]), .ZN(n_0_154)); + AOI22_X1_LVT i_0_203 (.A1(CurrentPC[26]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[26]), .ZN(n_0_153)); + NAND3_X1_LVT i_0_202 (.A1(n_0_154), .A2(n_0_153), .A3(n_0_165), .ZN(op1[26])); + AOI22_X1_LVT i_0_201 (.A1(RRs1[25]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[25]), .ZN(n_0_152)); + AOI22_X1_LVT i_0_200 (.A1(CurrentPC[25]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[25]), .ZN(n_0_151)); + NAND3_X1_LVT i_0_199 (.A1(n_0_152), .A2(n_0_151), .A3(n_0_165), .ZN(op1[25])); + AOI22_X1_LVT i_0_198 (.A1(RRs1[24]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[24]), .ZN(n_0_150)); + AOI22_X1_LVT i_0_197 (.A1(CurrentPC[24]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[24]), .ZN(n_0_149)); + NAND3_X1_LVT i_0_196 (.A1(n_0_150), .A2(n_0_149), .A3(n_0_165), .ZN(op1[24])); + AOI22_X1_LVT i_0_195 (.A1(RRs1[23]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[23]), .ZN(n_0_148)); + AOI22_X1_LVT i_0_194 (.A1(CurrentPC[23]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[23]), .ZN(n_0_147)); + NAND3_X1_LVT i_0_193 (.A1(n_0_148), .A2(n_0_147), .A3(n_0_165), .ZN(op1[23])); + AOI22_X1_LVT i_0_192 (.A1(RRs1[22]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[22]), .ZN(n_0_146)); + AOI22_X1_LVT i_0_191 (.A1(CurrentPC[22]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[22]), .ZN(n_0_145)); + NAND3_X1_LVT i_0_190 (.A1(n_0_146), .A2(n_0_145), .A3(n_0_165), .ZN(op1[22])); + AOI22_X1_LVT i_0_189 (.A1(RRs1[21]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[21]), .ZN(n_0_144)); + AOI22_X1_LVT i_0_188 (.A1(CurrentPC[21]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[21]), .ZN(n_0_143)); + NAND3_X1_LVT i_0_187 (.A1(n_0_144), .A2(n_0_143), .A3(n_0_165), .ZN(op1[21])); + AOI22_X1_LVT i_0_186 (.A1(RRs1[20]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[20]), .ZN(n_0_142)); + AOI22_X1_LVT i_0_185 (.A1(CurrentPC[20]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[20]), .ZN(n_0_141)); + NAND3_X1_LVT i_0_184 (.A1(n_0_142), .A2(n_0_141), .A3(n_0_165), .ZN(op1[20])); + AOI22_X1_LVT i_0_183 (.A1(RRs1[19]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[19]), .ZN(n_0_140)); + AOI22_X1_LVT i_0_182 (.A1(CurrentPC[19]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[19]), .ZN(n_0_139)); + NAND3_X1_LVT i_0_181 (.A1(n_0_140), .A2(n_0_139), .A3(n_0_165), .ZN(op1[19])); + AOI22_X1_LVT i_0_180 (.A1(RRs1[18]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[18]), .ZN(n_0_138)); + AOI22_X1_LVT i_0_179 (.A1(CurrentPC[18]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[18]), .ZN(n_0_137)); + NAND3_X1_LVT i_0_178 (.A1(n_0_138), .A2(n_0_137), .A3(n_0_165), .ZN(op1[18])); + AOI22_X1_LVT i_0_177 (.A1(RRs1[17]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[17]), .ZN(n_0_136)); + AOI22_X1_LVT i_0_176 (.A1(CurrentPC[17]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[17]), .ZN(n_0_135)); + NAND3_X1_LVT i_0_175 (.A1(n_0_136), .A2(n_0_135), .A3(n_0_165), .ZN(op1[17])); + AOI22_X1_LVT i_0_174 (.A1(RRs1[16]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[16]), .ZN(n_0_134)); + AOI22_X1_LVT i_0_173 (.A1(CurrentPC[16]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[16]), .ZN(n_0_133)); + NAND3_X1_LVT i_0_172 (.A1(n_0_134), .A2(n_0_133), .A3(n_0_165), .ZN(op1[16])); + AOI222_X1_LVT i_0_169 (.A1(CurrentPC[15]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[15]), .C1(n_0_169), .C2(RRs1[15]), .ZN(n_0_130)); + INV_X1_LVT i_0_353 (.A(Instruction[12]), .ZN(n_0_246)); + AOI211_X1_LVT i_0_171 (.A(Instruction[5]), .B(n_0_222), .C1(n_0_247), + .C2(n_0_246), .ZN(n_0_132)); + OAI211_X1_LVT i_0_170 (.A(RData[15]), .B(n_0_132), .C1(Instruction[13]), + .C2(Instruction[14]), .ZN(n_0_131)); + NAND3_X1_LVT i_0_168 (.A1(n_0_130), .A2(n_0_131), .A3(n_0_165), .ZN(op1[15])); + AOI22_X1_LVT i_0_167 (.A1(RRs1[14]), .A2(n_0_169), .B1(n_0_132), .B2( + RData[14]), .ZN(n_0_129)); + AOI22_X1_LVT i_0_166 (.A1(CurrentPC[14]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[14]), .ZN(n_0_128)); + NAND4_X1_LVT i_0_165 (.A1(n_0_221), .A2(n_0_246), .A3(RData[7]), .A4(n_0_166), + .ZN(n_0_127)); + NAND3_X1_LVT i_0_164 (.A1(n_0_129), .A2(n_0_128), .A3(n_0_127), .ZN(op1[14])); + AOI22_X1_LVT i_0_163 (.A1(RRs1[13]), .A2(n_0_169), .B1(n_0_132), .B2( + RData[13]), .ZN(n_0_126)); + AOI22_X1_LVT i_0_162 (.A1(CurrentPC[13]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[13]), .ZN(n_0_125)); + NAND3_X1_LVT i_0_161 (.A1(n_0_126), .A2(n_0_125), .A3(n_0_127), .ZN(op1[13])); + AOI22_X1_LVT i_0_160 (.A1(RRs1[12]), .A2(n_0_169), .B1(n_0_132), .B2( + RData[12]), .ZN(n_0_124)); + AOI22_X1_LVT i_0_159 (.A1(CurrentPC[12]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[12]), .ZN(n_0_123)); + NAND3_X1_LVT i_0_158 (.A1(n_0_124), .A2(n_0_123), .A3(n_0_127), .ZN(op1[12])); + AOI22_X1_LVT i_0_156 (.A1(CurrentPC[11]), .A2(n_0_224), .B1(n_0_132), + .B2(RData[11]), .ZN(n_0_121)); + NAND2_X1_LVT i_0_157 (.A1(RRs1[11]), .A2(n_0_169), .ZN(n_0_122)); + NAND3_X1_LVT i_0_155 (.A1(n_0_121), .A2(n_0_122), .A3(n_0_127), .ZN(op1[11])); + AOI22_X1_LVT i_0_153 (.A1(CurrentPC[10]), .A2(n_0_224), .B1(n_0_132), + .B2(RData[10]), .ZN(n_0_119)); + NAND2_X1_LVT i_0_154 (.A1(RRs1[10]), .A2(n_0_169), .ZN(n_0_120)); + NAND3_X1_LVT i_0_152 (.A1(n_0_119), .A2(n_0_120), .A3(n_0_127), .ZN(op1[10])); + AOI22_X1_LVT i_0_150 (.A1(CurrentPC[9]), .A2(n_0_224), .B1(n_0_132), .B2( + RData[9]), .ZN(n_0_117)); + NAND2_X1_LVT i_0_151 (.A1(RRs1[9]), .A2(n_0_169), .ZN(n_0_118)); + NAND3_X1_LVT i_0_149 (.A1(n_0_117), .A2(n_0_118), .A3(n_0_127), .ZN(op1[9])); + AOI22_X1_LVT i_0_147 (.A1(CurrentPC[8]), .A2(n_0_224), .B1(n_0_132), .B2( + RData[8]), .ZN(n_0_115)); + NAND2_X1_LVT i_0_148 (.A1(RRs1[8]), .A2(n_0_169), .ZN(n_0_116)); + NAND3_X1_LVT i_0_146 (.A1(n_0_115), .A2(n_0_116), .A3(n_0_127), .ZN(op1[8])); + AOI222_X1_LVT i_0_145 (.A1(CurrentPC[7]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[7]), .C1(n_0_169), .C2(RRs1[7]), .ZN(n_0_114)); + INV_X1_LVT i_0_144 (.A(n_0_114), .ZN(op1[7])); + AOI222_X1_LVT i_0_143 (.A1(CurrentPC[6]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[6]), .C1(n_0_169), .C2(RRs1[6]), .ZN(n_0_113)); + INV_X1_LVT i_0_142 (.A(n_0_113), .ZN(op1[6])); + AOI222_X1_LVT i_0_141 (.A1(CurrentPC[5]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[5]), .C1(n_0_169), .C2(RRs1[5]), .ZN(n_0_112)); + INV_X1_LVT i_0_140 (.A(n_0_112), .ZN(op1[5])); + AOI222_X1_LVT i_0_139 (.A1(CurrentPC[4]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[4]), .C1(n_0_169), .C2(RRs1[4]), .ZN(n_0_111)); + INV_X1_LVT i_0_138 (.A(n_0_111), .ZN(op1[4])); + AOI222_X1_LVT i_0_137 (.A1(CurrentPC[3]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[3]), .C1(n_0_169), .C2(RRs1[3]), .ZN(n_0_110)); + INV_X1_LVT i_0_136 (.A(n_0_110), .ZN(op1[3])); + AOI222_X1_LVT i_0_135 (.A1(CurrentPC[2]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[2]), .C1(n_0_169), .C2(RRs1[2]), .ZN(n_0_109)); + INV_X1_LVT i_0_134 (.A(n_0_109), .ZN(op1[2])); + AOI222_X1_LVT i_0_133 (.A1(CurrentPC[1]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[1]), .C1(n_0_169), .C2(RRs1[1]), .ZN(n_0_108)); + INV_X1_LVT i_0_132 (.A(n_0_108), .ZN(op1[1])); + AOI222_X1_LVT i_0_131 (.A1(CurrentPC[0]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[0]), .C1(n_0_169), .C2(RRs1[0]), .ZN(n_0_107)); + INV_X1_LVT i_0_130 (.A(n_0_107), .ZN(op1[0])); + NOR3_X1_LVT i_0_294 (.A1(n_0_223), .A2(Instruction[2]), .A3(Instruction[5]), + .ZN(n_0_207)); + NOR3_X1_LVT i_0_291 (.A1(n_0_224), .A2(n_0_207), .A3(n_0_205), .ZN(n_0_204)); + AOI22_X1_LVT i_0_289 (.A1(CurrentPC[31]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[31]), .ZN(n_0_202)); + NAND2_X1_LVT i_0_290 (.A1(Instruction[31]), .A2(n_0_207), .ZN(n_0_203)); + NAND2_X1_LVT i_0_288 (.A1(n_0_202), .A2(n_0_203), .ZN(op2[31])); + AOI22_X1_LVT i_0_287 (.A1(CurrentPC[30]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[30]), .ZN(n_0_201)); + NAND2_X1_LVT i_0_286 (.A1(n_0_201), .A2(n_0_203), .ZN(op2[30])); + AOI22_X1_LVT i_0_285 (.A1(CurrentPC[29]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[29]), .ZN(n_0_200)); + NAND2_X1_LVT i_0_284 (.A1(n_0_200), .A2(n_0_203), .ZN(op2[29])); + AOI22_X1_LVT i_0_283 (.A1(CurrentPC[28]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[28]), .ZN(n_0_199)); + NAND2_X1_LVT i_0_282 (.A1(n_0_199), .A2(n_0_203), .ZN(op2[28])); + AOI22_X1_LVT i_0_281 (.A1(CurrentPC[27]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[27]), .ZN(n_0_198)); + NAND2_X1_LVT i_0_280 (.A1(n_0_198), .A2(n_0_203), .ZN(op2[27])); + AOI22_X1_LVT i_0_279 (.A1(CurrentPC[26]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[26]), .ZN(n_0_197)); + NAND2_X1_LVT i_0_278 (.A1(n_0_197), .A2(n_0_203), .ZN(op2[26])); + AOI22_X1_LVT i_0_277 (.A1(CurrentPC[25]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[25]), .ZN(n_0_196)); + NAND2_X1_LVT i_0_276 (.A1(n_0_196), .A2(n_0_203), .ZN(op2[25])); + AOI22_X1_LVT i_0_275 (.A1(CurrentPC[24]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[24]), .ZN(n_0_195)); + NAND2_X1_LVT i_0_274 (.A1(n_0_195), .A2(n_0_203), .ZN(op2[24])); + AOI22_X1_LVT i_0_273 (.A1(CurrentPC[23]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[23]), .ZN(n_0_194)); + NAND2_X1_LVT i_0_272 (.A1(n_0_194), .A2(n_0_203), .ZN(op2[23])); + AOI22_X1_LVT i_0_271 (.A1(CurrentPC[22]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[22]), .ZN(n_0_193)); + NAND2_X1_LVT i_0_270 (.A1(n_0_193), .A2(n_0_203), .ZN(op2[22])); + AOI22_X1_LVT i_0_269 (.A1(CurrentPC[21]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[21]), .ZN(n_0_192)); + NAND2_X1_LVT i_0_268 (.A1(n_0_192), .A2(n_0_203), .ZN(op2[21])); + AOI22_X1_LVT i_0_267 (.A1(CurrentPC[20]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[20]), .ZN(n_0_191)); + NAND2_X1_LVT i_0_266 (.A1(n_0_191), .A2(n_0_203), .ZN(op2[20])); + AOI22_X1_LVT i_0_265 (.A1(CurrentPC[19]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[19]), .ZN(n_0_190)); + NAND2_X1_LVT i_0_264 (.A1(n_0_190), .A2(n_0_203), .ZN(op2[19])); + AOI22_X1_LVT i_0_263 (.A1(CurrentPC[18]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[18]), .ZN(n_0_189)); + NAND2_X1_LVT i_0_262 (.A1(n_0_189), .A2(n_0_203), .ZN(op2[18])); + AOI22_X1_LVT i_0_261 (.A1(CurrentPC[17]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[17]), .ZN(n_0_188)); + NAND2_X1_LVT i_0_260 (.A1(n_0_188), .A2(n_0_203), .ZN(op2[17])); + AOI22_X1_LVT i_0_259 (.A1(CurrentPC[16]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[16]), .ZN(n_0_187)); + NAND2_X1_LVT i_0_258 (.A1(n_0_187), .A2(n_0_203), .ZN(op2[16])); + AOI22_X1_LVT i_0_257 (.A1(CurrentPC[15]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[15]), .ZN(n_0_186)); + NAND2_X1_LVT i_0_256 (.A1(n_0_186), .A2(n_0_203), .ZN(op2[15])); + AOI22_X1_LVT i_0_255 (.A1(CurrentPC[14]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[14]), .ZN(n_0_185)); + NAND2_X1_LVT i_0_254 (.A1(n_0_185), .A2(n_0_203), .ZN(op2[14])); + AOI22_X1_LVT i_0_253 (.A1(CurrentPC[13]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[13]), .ZN(n_0_184)); + NAND2_X1_LVT i_0_252 (.A1(n_0_184), .A2(n_0_203), .ZN(op2[13])); + AOI22_X1_LVT i_0_251 (.A1(CurrentPC[12]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[12]), .ZN(n_0_183)); + NAND2_X1_LVT i_0_250 (.A1(n_0_183), .A2(n_0_203), .ZN(op2[12])); + AOI22_X1_LVT i_0_249 (.A1(CurrentPC[11]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[11]), .ZN(n_0_182)); + NAND2_X1_LVT i_0_248 (.A1(n_0_182), .A2(n_0_203), .ZN(op2[11])); + AOI222_X1_LVT i_0_247 (.A1(Instruction[30]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[10]), .C1(n_0_204), .C2(RRs2[10]), .ZN(n_0_181)); + INV_X1_LVT i_0_246 (.A(n_0_181), .ZN(op2[10])); + AOI222_X1_LVT i_0_245 (.A1(Instruction[29]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[9]), .C1(n_0_204), .C2(RRs2[9]), .ZN(n_0_180)); + INV_X1_LVT i_0_244 (.A(n_0_180), .ZN(op2[9])); + AOI222_X1_LVT i_0_243 (.A1(Instruction[28]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[8]), .C1(n_0_204), .C2(RRs2[8]), .ZN(n_0_179)); + INV_X1_LVT i_0_242 (.A(n_0_179), .ZN(op2[8])); + AOI222_X1_LVT i_0_241 (.A1(Instruction[27]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[7]), .C1(n_0_204), .C2(RRs2[7]), .ZN(n_0_178)); + INV_X1_LVT i_0_240 (.A(n_0_178), .ZN(op2[7])); + AOI222_X1_LVT i_0_239 (.A1(Instruction[26]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[6]), .C1(n_0_204), .C2(RRs2[6]), .ZN(n_0_177)); + INV_X1_LVT i_0_238 (.A(n_0_177), .ZN(op2[6])); + AOI222_X1_LVT i_0_237 (.A1(Instruction[25]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[5]), .C1(n_0_204), .C2(RRs2[5]), .ZN(n_0_176)); + INV_X1_LVT i_0_236 (.A(n_0_176), .ZN(op2[5])); + AOI222_X1_LVT i_0_235 (.A1(Instruction[24]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[4]), .C1(n_0_204), .C2(RRs2[4]), .ZN(n_0_175)); + INV_X1_LVT i_0_234 (.A(n_0_175), .ZN(op2[4])); + AOI222_X1_LVT i_0_233 (.A1(Instruction[23]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[3]), .C1(n_0_204), .C2(RRs2[3]), .ZN(n_0_174)); + INV_X1_LVT i_0_232 (.A(n_0_174), .ZN(op2[3])); + AOI22_X1_LVT i_0_230 (.A1(Instruction[22]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[2]), .ZN(n_0_172)); + OAI21_X1_LVT i_0_231 (.A(RRs2[2]), .B1(n_0_223), .B2(Instruction[5]), + .ZN(n_0_173)); + NAND3_X1_LVT i_0_229 (.A1(n_0_172), .A2(n_0_173), .A3(n_0_249), .ZN(op2[2])); + AOI222_X1_LVT i_0_228 (.A1(Instruction[21]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[1]), .C1(n_0_204), .C2(RRs2[1]), .ZN(n_0_171)); + INV_X1_LVT i_0_227 (.A(n_0_171), .ZN(op2[1])); + AOI222_X1_LVT i_0_226 (.A1(Instruction[20]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[0]), .C1(n_0_204), .C2(RRs2[0]), .ZN(n_0_170)); + INV_X1_LVT i_0_225 (.A(n_0_170), .ZN(op2[0])); + alu theALU (.aluOp(aluOp), .aluNegAr(aluNegAr), .aluBypass(aluBypass), + .op1(op1), .op2(op2), .result(WRd), .eqFlag(eqFlag)); + XNOR2_X1_LVT i_0_115 (.A(Instruction[12]), .B(eqFlag), .ZN(n_0_97)); + XNOR2_X1_LVT i_0_114 (.A(Instruction[12]), .B(WRd[0]), .ZN(n_0_96)); + AOI22_X1_LVT i_0_113 (.A1(n_0_166), .A2(n_0_97), .B1(n_0_96), .B2( + Instruction[14]), .ZN(n_0_95)); + AOI22_X1_LVT i_0_111 (.A1(Instruction[6]), .A2(n_0_95), .B1(Instruction[2]), + .B2(n_0_245), .ZN(n_0_93)); + NAND2_X1_LVT i_0_110 (.A1(n_0_94), .A2(n_0_93), .ZN(JumpOrBranch)); + INV_X1_LVT i_0_349 (.A(Instruction[31]), .ZN(n_0_0)); + INV_X1_LVT i_0_348 (.A(RRs1[12]), .ZN(n_0_1)); + HA_X1_LVT i_0_0 (.A(Instruction[7]), .B(RRs1[0]), .CO(n_0_2), .S(n_0_15)); + FA_X1_LVT i_0_1 (.A(Instruction[8]), .B(RRs1[1]), .CI(n_0_2), .CO(n_0_3), + .S(n_0_16)); + FA_X1_LVT i_0_2 (.A(Instruction[9]), .B(RRs1[2]), .CI(n_0_3), .CO(n_0_4), + .S(n_0_17)); + FA_X1_LVT i_0_3 (.A(Instruction[10]), .B(RRs1[3]), .CI(n_0_4), .CO(n_0_5), + .S(n_0_18)); + FA_X1_LVT i_0_4 (.A(Instruction[11]), .B(RRs1[4]), .CI(n_0_5), .CO(n_0_6), + .S(n_0_19)); + FA_X1_LVT i_0_5 (.A(Instruction[25]), .B(RRs1[5]), .CI(n_0_6), .CO(n_0_7), + .S(n_0_20)); + FA_X1_LVT i_0_6 (.A(Instruction[26]), .B(RRs1[6]), .CI(n_0_7), .CO(n_0_8), + .S(n_0_21)); + FA_X1_LVT i_0_7 (.A(Instruction[27]), .B(RRs1[7]), .CI(n_0_8), .CO(n_0_9), + .S(n_0_22)); + FA_X1_LVT i_0_8 (.A(Instruction[28]), .B(RRs1[8]), .CI(n_0_9), .CO(n_0_10), + .S(n_0_23)); + FA_X1_LVT i_0_9 (.A(Instruction[29]), .B(RRs1[9]), .CI(n_0_10), .CO(n_0_11), + .S(n_0_24)); + FA_X1_LVT i_0_10 (.A(Instruction[30]), .B(RRs1[10]), .CI(n_0_11), .CO(n_0_12), + .S(n_0_25)); + FA_X1_LVT i_0_11 (.A(RRs1[11]), .B(Instruction[31]), .CI(n_0_12), .CO(n_0_13), + .S(n_0_26)); + FA_X1_LVT i_0_12 (.A(n_0_0), .B(n_0_1), .CI(n_0_13), .CO(n_0_14), .S(n_0_27)); + NOR2_X1_LVT i_0_322 (.A1(n_0_244), .A2(n_0_222), .ZN(WrMem)); + AOI22_X1_LVT i_0_320 (.A1(n_0_27), .A2(WrMem), .B1(n_0_221), .B2(n_12), + .ZN(n_0_220)); + INV_X1_LVT i_0_319 (.A(n_0_220), .ZN(DAddr[12])); + AOI22_X1_LVT i_0_318 (.A1(n_0_26), .A2(WrMem), .B1(n_0_221), .B2(n_11), + .ZN(n_0_219)); + INV_X1_LVT i_0_317 (.A(n_0_219), .ZN(DAddr[11])); + AOI22_X1_LVT i_0_316 (.A1(n_0_25), .A2(WrMem), .B1(n_0_221), .B2(n_10), + .ZN(n_0_218)); + INV_X1_LVT i_0_315 (.A(n_0_218), .ZN(DAddr[10])); + AOI22_X1_LVT i_0_314 (.A1(n_0_24), .A2(WrMem), .B1(n_0_221), .B2(n_9), + .ZN(n_0_217)); + INV_X1_LVT i_0_313 (.A(n_0_217), .ZN(DAddr[9])); + AOI22_X1_LVT i_0_312 (.A1(n_0_23), .A2(WrMem), .B1(n_0_221), .B2(n_8), + .ZN(n_0_216)); + INV_X1_LVT i_0_311 (.A(n_0_216), .ZN(DAddr[8])); + AOI22_X1_LVT i_0_310 (.A1(n_0_22), .A2(WrMem), .B1(n_0_221), .B2(n_7), + .ZN(n_0_215)); + INV_X1_LVT i_0_309 (.A(n_0_215), .ZN(DAddr[7])); + AOI22_X1_LVT i_0_308 (.A1(n_0_21), .A2(WrMem), .B1(n_0_221), .B2(n_6), + .ZN(n_0_214)); + INV_X1_LVT i_0_307 (.A(n_0_214), .ZN(DAddr[6])); + AOI22_X1_LVT i_0_306 (.A1(n_0_20), .A2(WrMem), .B1(n_0_221), .B2(n_5), + .ZN(n_0_213)); + INV_X1_LVT i_0_305 (.A(n_0_213), .ZN(DAddr[5])); + AOI22_X1_LVT i_0_304 (.A1(n_0_19), .A2(WrMem), .B1(n_0_221), .B2(n_4), + .ZN(n_0_212)); + INV_X1_LVT i_0_303 (.A(n_0_212), .ZN(DAddr[4])); + AOI22_X1_LVT i_0_302 (.A1(n_0_18), .A2(WrMem), .B1(n_0_221), .B2(n_3), + .ZN(n_0_211)); + INV_X1_LVT i_0_301 (.A(n_0_211), .ZN(DAddr[3])); + AOI22_X1_LVT i_0_300 (.A1(n_0_17), .A2(WrMem), .B1(n_0_221), .B2(n_2), + .ZN(n_0_210)); + INV_X1_LVT i_0_299 (.A(n_0_210), .ZN(DAddr[2])); + AOI22_X1_LVT i_0_298 (.A1(n_0_16), .A2(WrMem), .B1(n_0_221), .B2(n_1), + .ZN(n_0_209)); + INV_X1_LVT i_0_297 (.A(n_0_209), .ZN(DAddr[1])); + AOI22_X1_LVT i_0_296 (.A1(n_0_15), .A2(WrMem), .B1(n_0_221), .B2(n_0), + .ZN(n_0_208)); + INV_X1_LVT i_0_295 (.A(n_0_208), .ZN(DAddr[0])); + OR2_X1_LVT i_0_324 (.A1(n_0_222), .A2(Instruction[13]), .ZN(DWidth[1])); + NOR2_X1_LVT i_0_323 (.A1(n_0_246), .A2(n_0_222), .ZN(DWidth[0])); + NAND3_X1_LVT i_0_331 (.A1(n_0_248), .A2(n_0_244), .A3(n_0_236), .ZN(n_0_227)); + OAI211_X1_LVT i_0_326 (.A(n_0_249), .B(n_0_223), .C1(n_0_228), .C2(n_0_227), + .ZN(WrReg)); +endmodule + +module cpu(led, btn, clk_25mhz, scan_en, SI_1, SO_1, SI_2, SO_2, SI_3, SO_3, + SI_4, SO_4); + output [7:0]led; + input [6:0]btn; + input clk_25mhz; + input scan_en; + input SI_1; + output SO_1; + input SI_2; + output SO_2; + input SI_3; + output SO_3; + input SI_4; + output SO_4; + + wire [31:0]Instruction; + wire [31:0]RData; + wire [31:0]RRs2; + wire [31:0]RRs1; + wire WrReg; + wire [31:0]WRd; + wire [1:0]DWidth; + wire [31:0]DAddr; + wire JumpOrBranch; + wire [31:0]JumpOrBranchPC; + wire thePC_n_1; + wire thePC_i_0_n_0; + wire thePC_n_2; + wire thePC_i_0_n_1; + wire thePC_n_3; + wire thePC_i_0_n_2; + wire thePC_n_4; + wire thePC_i_0_n_3; + wire thePC_n_5; + wire thePC_i_0_n_4; + wire thePC_n_6; + wire thePC_i_0_n_5; + wire thePC_n_7; + wire thePC_i_0_n_6; + wire thePC_n_8; + wire thePC_i_0_n_7; + wire thePC_n_9; + wire thePC_i_0_n_8; + wire thePC_n_10; + wire thePC_i_0_n_9; + wire thePC_n_11; + wire thePC_i_0_n_10; + wire thePC_n_12; + wire thePC_i_0_n_11; + wire thePC_n_13; + wire thePC_i_0_n_12; + wire thePC_n_14; + wire thePC_i_0_n_13; + wire thePC_n_15; + wire thePC_i_0_n_14; + wire thePC_n_16; + wire thePC_i_0_n_15; + wire thePC_n_17; + wire thePC_i_0_n_16; + wire thePC_n_18; + wire thePC_i_0_n_17; + wire thePC_n_19; + wire thePC_i_0_n_18; + wire thePC_n_20; + wire thePC_i_0_n_19; + wire thePC_n_21; + wire thePC_i_0_n_20; + wire thePC_n_22; + wire thePC_i_0_n_21; + wire thePC_n_23; + wire thePC_i_0_n_22; + wire thePC_n_24; + wire thePC_i_0_n_23; + wire thePC_n_25; + wire thePC_i_0_n_24; + wire thePC_n_26; + wire thePC_i_0_n_25; + wire thePC_n_27; + wire thePC_i_0_n_26; + wire thePC_n_28; + wire thePC_i_0_n_27; + wire thePC_n_29; + wire thePC_n_0; + wire [31:0]CurrentPC; + wire thePC_n_30; + wire n_0_0_0; + wire thePC_n_31; + wire n_0_0_1; + wire thePC_n_32; + wire thePC_n_33; + wire thePC_n_34; + wire thePC_n_35; + wire thePC_n_36; + wire thePC_n_37; + wire thePC_n_38; + wire thePC_n_39; + wire thePC_n_40; + wire thePC_n_41; + wire thePC_n_42; + wire thePC_n_43; + wire n_0_0_2; + wire thePC_n_44; + wire n_0_0_3; + wire thePC_n_45; + wire n_0_0_4; + wire thePC_n_46; + wire n_0_0_5; + wire thePC_n_47; + wire n_0_0_6; + wire thePC_n_48; + wire n_0_0_7; + wire thePC_n_49; + wire n_0_0_8; + wire thePC_n_50; + wire n_0_0_9; + wire thePC_n_51; + wire n_0_0_10; + wire thePC_n_52; + wire n_0_0_11; + wire thePC_n_53; + wire n_0_0_12; + wire thePC_n_54; + wire n_0_0_13; + wire thePC_n_55; + wire n_0_0_14; + wire thePC_n_56; + wire n_0_0_15; + wire thePC_n_57; + wire n_0_0_16; + wire thePC_n_58; + wire n_0_0_17; + wire thePC_n_59; + wire n_0_0_18; + wire thePC_n_60; + wire n_0_0_19; + wire thePC_n_61; + wire n_0_0_20; + wire n_0_0_21; + wire n_0_0_22; + wire [31:0]NextPC; + wire reset; + + AND2_X1_LVT i_0_0_54 (.A1(JumpOrBranch), .A2(btn[0]), .ZN(n_0_0_22)); + INV_X1_LVT i_0_0_66 (.A(btn[0]), .ZN(reset)); + NOR2_X1_LVT i_0_0_53 (.A1(reset), .A2(JumpOrBranch), .ZN(n_0_0_21)); + AOI22_X1_LVT i_0_0_50 (.A1(JumpOrBranchPC[30]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_28), .ZN(n_0_0_19)); + INV_X1_LVT i_0_0_49 (.A(n_0_0_19), .ZN(thePC_n_60)); + SDFF_X1_LVT \thePC_CurrentPC_reg[30] (.D(thePC_n_60), .SE(1'b0), .SI( + CurrentPC[30]), .CK(clk_25mhz), .Q(CurrentPC[30]), .QN()); + AOI22_X1_LVT i_0_0_48 (.A1(JumpOrBranchPC[29]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_27), .ZN(n_0_0_18)); + INV_X1_LVT i_0_0_47 (.A(n_0_0_18), .ZN(thePC_n_59)); + SDFF_X1_LVT \thePC_CurrentPC_reg[29] (.D(thePC_n_59), .SE(1'b0), .SI( + CurrentPC[29]), .CK(clk_25mhz), .Q(CurrentPC[29]), .QN()); + AOI22_X1_LVT i_0_0_46 (.A1(JumpOrBranchPC[28]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_26), .ZN(n_0_0_17)); + INV_X1_LVT i_0_0_45 (.A(n_0_0_17), .ZN(thePC_n_58)); + SDFF_X1_LVT \thePC_CurrentPC_reg[28] (.D(thePC_n_58), .SE(1'b0), .SI( + CurrentPC[28]), .CK(clk_25mhz), .Q(CurrentPC[28]), .QN()); + AOI22_X1_LVT i_0_0_44 (.A1(JumpOrBranchPC[27]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_25), .ZN(n_0_0_16)); + INV_X1_LVT i_0_0_43 (.A(n_0_0_16), .ZN(thePC_n_57)); + SDFF_X1_LVT \thePC_CurrentPC_reg[27] (.D(thePC_n_57), .SE(1'b0), .SI( + CurrentPC[27]), .CK(clk_25mhz), .Q(CurrentPC[27]), .QN()); + AOI22_X1_LVT i_0_0_42 (.A1(JumpOrBranchPC[26]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_24), .ZN(n_0_0_15)); + INV_X1_LVT i_0_0_41 (.A(n_0_0_15), .ZN(thePC_n_56)); + SDFF_X1_LVT \thePC_CurrentPC_reg[26] (.D(thePC_n_56), .SE(1'b0), .SI( + CurrentPC[26]), .CK(clk_25mhz), .Q(CurrentPC[26]), .QN()); + AOI22_X1_LVT i_0_0_40 (.A1(JumpOrBranchPC[25]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_23), .ZN(n_0_0_14)); + INV_X1_LVT i_0_0_39 (.A(n_0_0_14), .ZN(thePC_n_55)); + SDFF_X1_LVT \thePC_CurrentPC_reg[25] (.D(thePC_n_55), .SE(1'b0), .SI( + CurrentPC[25]), .CK(clk_25mhz), .Q(CurrentPC[25]), .QN()); + AOI22_X1_LVT i_0_0_38 (.A1(JumpOrBranchPC[24]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_22), .ZN(n_0_0_13)); + INV_X1_LVT i_0_0_37 (.A(n_0_0_13), .ZN(thePC_n_54)); + SDFF_X1_LVT \thePC_CurrentPC_reg[24] (.D(thePC_n_54), .SE(1'b0), .SI( + CurrentPC[24]), .CK(clk_25mhz), .Q(CurrentPC[24]), .QN()); + AOI22_X1_LVT i_0_0_36 (.A1(JumpOrBranchPC[23]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_21), .ZN(n_0_0_12)); + INV_X1_LVT i_0_0_35 (.A(n_0_0_12), .ZN(thePC_n_53)); + SDFF_X1_LVT \thePC_CurrentPC_reg[23] (.D(thePC_n_53), .SE(1'b0), .SI( + CurrentPC[23]), .CK(clk_25mhz), .Q(CurrentPC[23]), .QN()); + AOI22_X1_LVT i_0_0_34 (.A1(JumpOrBranchPC[22]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_20), .ZN(n_0_0_11)); + INV_X1_LVT i_0_0_33 (.A(n_0_0_11), .ZN(thePC_n_52)); + SDFF_X1_LVT \thePC_CurrentPC_reg[22] (.D(thePC_n_52), .SE(1'b0), .SI( + CurrentPC[22]), .CK(clk_25mhz), .Q(CurrentPC[22]), .QN()); + AOI22_X1_LVT i_0_0_32 (.A1(JumpOrBranchPC[21]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_19), .ZN(n_0_0_10)); + INV_X1_LVT i_0_0_31 (.A(n_0_0_10), .ZN(thePC_n_51)); + SDFF_X1_LVT \thePC_CurrentPC_reg[21] (.D(thePC_n_51), .SE(1'b0), .SI( + CurrentPC[21]), .CK(clk_25mhz), .Q(CurrentPC[21]), .QN()); + AOI22_X1_LVT i_0_0_30 (.A1(JumpOrBranchPC[20]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_18), .ZN(n_0_0_9)); + INV_X1_LVT i_0_0_29 (.A(n_0_0_9), .ZN(thePC_n_50)); + SDFF_X1_LVT \thePC_CurrentPC_reg[20] (.D(thePC_n_50), .SE(1'b0), .SI( + CurrentPC[20]), .CK(clk_25mhz), .Q(CurrentPC[20]), .QN()); + AOI22_X1_LVT i_0_0_28 (.A1(JumpOrBranchPC[19]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_17), .ZN(n_0_0_8)); + INV_X1_LVT i_0_0_27 (.A(n_0_0_8), .ZN(thePC_n_49)); + SDFF_X1_LVT \thePC_CurrentPC_reg[19] (.D(thePC_n_49), .SE(1'b0), .SI( + CurrentPC[19]), .CK(clk_25mhz), .Q(CurrentPC[19]), .QN()); + AOI22_X1_LVT i_0_0_26 (.A1(JumpOrBranchPC[18]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_16), .ZN(n_0_0_7)); + INV_X1_LVT i_0_0_25 (.A(n_0_0_7), .ZN(thePC_n_48)); + SDFF_X1_LVT \thePC_CurrentPC_reg[18] (.D(thePC_n_48), .SE(1'b0), .SI( + CurrentPC[18]), .CK(clk_25mhz), .Q(CurrentPC[18]), .QN()); + AOI22_X1_LVT i_0_0_24 (.A1(JumpOrBranchPC[17]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_15), .ZN(n_0_0_6)); + INV_X1_LVT i_0_0_23 (.A(n_0_0_6), .ZN(thePC_n_47)); + SDFF_X1_LVT \thePC_CurrentPC_reg[17] (.D(thePC_n_47), .SE(1'b0), .SI( + CurrentPC[17]), .CK(clk_25mhz), .Q(CurrentPC[17]), .QN()); + AOI22_X1_LVT i_0_0_22 (.A1(JumpOrBranchPC[16]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_14), .ZN(n_0_0_5)); + INV_X1_LVT i_0_0_21 (.A(n_0_0_5), .ZN(thePC_n_46)); + SDFF_X1_LVT \thePC_CurrentPC_reg[16] (.D(thePC_n_46), .SE(1'b0), .SI( + CurrentPC[16]), .CK(clk_25mhz), .Q(CurrentPC[16]), .QN()); + AOI22_X1_LVT i_0_0_20 (.A1(JumpOrBranchPC[15]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_13), .ZN(n_0_0_4)); + INV_X1_LVT i_0_0_19 (.A(n_0_0_4), .ZN(thePC_n_45)); + SDFF_X1_LVT \thePC_CurrentPC_reg[15] (.D(thePC_n_45), .SE(1'b0), .SI( + CurrentPC[15]), .CK(clk_25mhz), .Q(CurrentPC[15]), .QN()); + AOI22_X1_LVT i_0_0_18 (.A1(JumpOrBranchPC[14]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_12), .ZN(n_0_0_3)); + INV_X1_LVT i_0_0_17 (.A(n_0_0_3), .ZN(thePC_n_44)); + SDFF_X1_LVT \thePC_CurrentPC_reg[14] (.D(thePC_n_44), .SE(1'b0), .SI( + CurrentPC[14]), .CK(clk_25mhz), .Q(CurrentPC[14]), .QN()); + AOI22_X1_LVT i_0_0_16 (.A1(JumpOrBranchPC[13]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_11), .ZN(n_0_0_2)); + INV_X1_LVT i_0_0_15 (.A(n_0_0_2), .ZN(thePC_n_43)); + SDFF_X1_LVT \thePC_CurrentPC_reg[13] (.D(thePC_n_43), .SE(1'b0), .SI( + CurrentPC[13]), .CK(clk_25mhz), .Q(CurrentPC[13]), .QN()); + MUX2_X1_LVT i_0_0_65 (.A(thePC_n_10), .B(JumpOrBranchPC[12]), .S(JumpOrBranch), + .Z(NextPC[12])); + AND2_X1_LVT i_0_0_14 (.A1(NextPC[12]), .A2(btn[0]), .ZN(thePC_n_42)); + SDFF_X1_LVT \thePC_CurrentPC_reg[12] (.D(thePC_n_42), .SE(1'b0), .SI( + CurrentPC[12]), .CK(clk_25mhz), .Q(CurrentPC[12]), .QN()); + MUX2_X1_LVT i_0_0_64 (.A(thePC_n_9), .B(JumpOrBranchPC[11]), .S(JumpOrBranch), + .Z(NextPC[11])); + AND2_X1_LVT i_0_0_13 (.A1(NextPC[11]), .A2(btn[0]), .ZN(thePC_n_41)); + SDFF_X1_LVT \thePC_CurrentPC_reg[11] (.D(thePC_n_41), .SE(1'b0), .SI( + CurrentPC[11]), .CK(clk_25mhz), .Q(CurrentPC[11]), .QN()); + MUX2_X1_LVT i_0_0_63 (.A(thePC_n_8), .B(JumpOrBranchPC[10]), .S(JumpOrBranch), + .Z(NextPC[10])); + AND2_X1_LVT i_0_0_12 (.A1(NextPC[10]), .A2(btn[0]), .ZN(thePC_n_40)); + SDFF_X1_LVT \thePC_CurrentPC_reg[10] (.D(thePC_n_40), .SE(1'b0), .SI( + CurrentPC[10]), .CK(clk_25mhz), .Q(CurrentPC[10]), .QN()); + MUX2_X1_LVT i_0_0_62 (.A(thePC_n_7), .B(JumpOrBranchPC[9]), .S(JumpOrBranch), + .Z(NextPC[9])); + AND2_X1_LVT i_0_0_11 (.A1(NextPC[9]), .A2(btn[0]), .ZN(thePC_n_39)); + SDFF_X1_LVT \thePC_CurrentPC_reg[9] (.D(thePC_n_39), .SE(1'b0), .SI( + CurrentPC[9]), .CK(clk_25mhz), .Q(CurrentPC[9]), .QN()); + MUX2_X1_LVT i_0_0_61 (.A(thePC_n_6), .B(JumpOrBranchPC[8]), .S(JumpOrBranch), + .Z(NextPC[8])); + AND2_X1_LVT i_0_0_10 (.A1(NextPC[8]), .A2(btn[0]), .ZN(thePC_n_38)); + SDFF_X1_LVT \thePC_CurrentPC_reg[8] (.D(thePC_n_38), .SE(1'b0), .SI( + CurrentPC[8]), .CK(clk_25mhz), .Q(CurrentPC[8]), .QN()); + AND2_X1_LVT i_0_0_9 (.A1(led[7]), .A2(btn[0]), .ZN(thePC_n_37)); + SDFF_X1_LVT \thePC_CurrentPC_reg[7] (.D(thePC_n_37), .SE(1'b0), .SI( + CurrentPC[7]), .CK(clk_25mhz), .Q(CurrentPC[7]), .QN()); + MUX2_X1_LVT i_0_0_59 (.A(thePC_n_4), .B(JumpOrBranchPC[6]), .S(JumpOrBranch), + .Z(led[6])); + AND2_X1_LVT i_0_0_8 (.A1(led[6]), .A2(btn[0]), .ZN(thePC_n_36)); + SDFF_X1_LVT \thePC_CurrentPC_reg[6] (.D(thePC_n_36), .SE(1'b0), .SI( + CurrentPC[6]), .CK(clk_25mhz), .Q(CurrentPC[6]), .QN()); + MUX2_X1_LVT i_0_0_58 (.A(thePC_n_3), .B(JumpOrBranchPC[5]), .S(JumpOrBranch), + .Z(led[5])); + AND2_X1_LVT i_0_0_7 (.A1(led[5]), .A2(btn[0]), .ZN(thePC_n_35)); + SDFF_X1_LVT \thePC_CurrentPC_reg[5] (.D(thePC_n_35), .SE(1'b0), .SI( + CurrentPC[5]), .CK(clk_25mhz), .Q(CurrentPC[5]), .QN()); + MUX2_X1_LVT i_0_0_57 (.A(thePC_n_2), .B(JumpOrBranchPC[4]), .S(JumpOrBranch), + .Z(led[4])); + AND2_X1_LVT i_0_0_6 (.A1(led[4]), .A2(btn[0]), .ZN(thePC_n_34)); + SDFF_X1_LVT \thePC_CurrentPC_reg[4] (.D(thePC_n_34), .SE(1'b0), .SI( + CurrentPC[4]), .CK(clk_25mhz), .Q(CurrentPC[4]), .QN()); + MUX2_X1_LVT i_0_0_56 (.A(thePC_n_1), .B(JumpOrBranchPC[3]), .S(JumpOrBranch), + .Z(led[3])); + AND2_X1_LVT i_0_0_5 (.A1(led[3]), .A2(btn[0]), .ZN(thePC_n_33)); + SDFF_X1_LVT \thePC_CurrentPC_reg[3] (.D(thePC_n_33), .SE(1'b0), .SI( + CurrentPC[3]), .CK(clk_25mhz), .Q(CurrentPC[3]), .QN()); + INV_X1_LVT thePC_i_0_29 (.A(CurrentPC[2]), .ZN(thePC_n_0)); + MUX2_X1_LVT i_0_0_55 (.A(thePC_n_0), .B(JumpOrBranchPC[2]), .S(JumpOrBranch), + .Z(led[2])); + AND2_X1_LVT i_0_0_4 (.A1(led[2]), .A2(btn[0]), .ZN(thePC_n_32)); + SDFF_X1_LVT \thePC_CurrentPC_reg[2] (.D(thePC_n_32), .SE(1'b0), .SI( + CurrentPC[2]), .CK(clk_25mhz), .Q(CurrentPC[2]), .QN()); + HA_X1_LVT thePC_i_0_0 (.A(CurrentPC[3]), .B(CurrentPC[2]), .CO(thePC_i_0_n_0), + .S(thePC_n_1)); + HA_X1_LVT thePC_i_0_1 (.A(CurrentPC[4]), .B(thePC_i_0_n_0), .CO(thePC_i_0_n_1), + .S(thePC_n_2)); + HA_X1_LVT thePC_i_0_2 (.A(CurrentPC[5]), .B(thePC_i_0_n_1), .CO(thePC_i_0_n_2), + .S(thePC_n_3)); + HA_X1_LVT thePC_i_0_3 (.A(CurrentPC[6]), .B(thePC_i_0_n_2), .CO(thePC_i_0_n_3), + .S(thePC_n_4)); + HA_X1_LVT thePC_i_0_4 (.A(CurrentPC[7]), .B(thePC_i_0_n_3), .CO(thePC_i_0_n_4), + .S(thePC_n_5)); + HA_X1_LVT thePC_i_0_5 (.A(CurrentPC[8]), .B(thePC_i_0_n_4), .CO(thePC_i_0_n_5), + .S(thePC_n_6)); + HA_X1_LVT thePC_i_0_6 (.A(CurrentPC[9]), .B(thePC_i_0_n_5), .CO(thePC_i_0_n_6), + .S(thePC_n_7)); + HA_X1_LVT thePC_i_0_7 (.A(CurrentPC[10]), .B(thePC_i_0_n_6), .CO( + thePC_i_0_n_7), .S(thePC_n_8)); + HA_X1_LVT thePC_i_0_8 (.A(CurrentPC[11]), .B(thePC_i_0_n_7), .CO( + thePC_i_0_n_8), .S(thePC_n_9)); + HA_X1_LVT thePC_i_0_9 (.A(CurrentPC[12]), .B(thePC_i_0_n_8), .CO( + thePC_i_0_n_9), .S(thePC_n_10)); + HA_X1_LVT thePC_i_0_11 (.A(CurrentPC[13]), .B(thePC_i_0_n_9), .CO( + thePC_i_0_n_10), .S(thePC_n_11)); + HA_X1_LVT thePC_i_0_12 (.A(CurrentPC[14]), .B(thePC_i_0_n_10), .CO( + thePC_i_0_n_11), .S(thePC_n_12)); + HA_X1_LVT thePC_i_0_13 (.A(CurrentPC[15]), .B(thePC_i_0_n_11), .CO( + thePC_i_0_n_12), .S(thePC_n_13)); + HA_X1_LVT thePC_i_0_14 (.A(CurrentPC[16]), .B(thePC_i_0_n_12), .CO( + thePC_i_0_n_13), .S(thePC_n_14)); + HA_X1_LVT thePC_i_0_15 (.A(CurrentPC[17]), .B(thePC_i_0_n_13), .CO( + thePC_i_0_n_14), .S(thePC_n_15)); + HA_X1_LVT thePC_i_0_16 (.A(CurrentPC[18]), .B(thePC_i_0_n_14), .CO( + thePC_i_0_n_15), .S(thePC_n_16)); + HA_X1_LVT thePC_i_0_17 (.A(CurrentPC[19]), .B(thePC_i_0_n_15), .CO( + thePC_i_0_n_16), .S(thePC_n_17)); + HA_X1_LVT thePC_i_0_10 (.A(CurrentPC[20]), .B(thePC_i_0_n_16), .CO( + thePC_i_0_n_17), .S(thePC_n_18)); + HA_X1_LVT thePC_i_0_18 (.A(CurrentPC[21]), .B(thePC_i_0_n_17), .CO( + thePC_i_0_n_18), .S(thePC_n_19)); + HA_X1_LVT thePC_i_0_19 (.A(CurrentPC[22]), .B(thePC_i_0_n_18), .CO( + thePC_i_0_n_19), .S(thePC_n_20)); + HA_X1_LVT thePC_i_0_20 (.A(CurrentPC[23]), .B(thePC_i_0_n_19), .CO( + thePC_i_0_n_20), .S(thePC_n_21)); + HA_X1_LVT thePC_i_0_21 (.A(CurrentPC[24]), .B(thePC_i_0_n_20), .CO( + thePC_i_0_n_21), .S(thePC_n_22)); + HA_X1_LVT thePC_i_0_22 (.A(CurrentPC[25]), .B(thePC_i_0_n_21), .CO( + thePC_i_0_n_22), .S(thePC_n_23)); + HA_X1_LVT thePC_i_0_23 (.A(CurrentPC[26]), .B(thePC_i_0_n_22), .CO( + thePC_i_0_n_23), .S(thePC_n_24)); + HA_X1_LVT thePC_i_0_24 (.A(CurrentPC[27]), .B(thePC_i_0_n_23), .CO( + thePC_i_0_n_24), .S(thePC_n_25)); + HA_X1_LVT thePC_i_0_25 (.A(CurrentPC[28]), .B(thePC_i_0_n_24), .CO( + thePC_i_0_n_25), .S(thePC_n_26)); + HA_X1_LVT thePC_i_0_26 (.A(CurrentPC[29]), .B(thePC_i_0_n_25), .CO( + thePC_i_0_n_26), .S(thePC_n_27)); + HA_X1_LVT thePC_i_0_27 (.A(CurrentPC[30]), .B(thePC_i_0_n_26), .CO( + thePC_i_0_n_27), .S(thePC_n_28)); + XOR2_X1_LVT thePC_i_0_28 (.A(CurrentPC[31]), .B(thePC_i_0_n_27), .Z( + thePC_n_29)); + AOI22_X1_LVT i_0_0_52 (.A1(JumpOrBranchPC[31]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_29), .ZN(n_0_0_20)); + INV_X1_LVT i_0_0_51 (.A(n_0_0_20), .ZN(thePC_n_61)); + SDFF_X1_LVT \thePC_CurrentPC_reg[31] (.D(thePC_n_61), .SE(1'b0), .SI( + CurrentPC[31]), .CK(clk_25mhz), .Q(CurrentPC[31]), .QN()); + AOI22_X1_LVT i_0_0_3 (.A1(JumpOrBranchPC[1]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(CurrentPC[1]), .ZN(n_0_0_1)); + INV_X1_LVT i_0_0_2 (.A(n_0_0_1), .ZN(thePC_n_31)); + SDFF_X1_LVT \thePC_CurrentPC_reg[1] (.D(thePC_n_31), .SE(1'b0), .SI( + CurrentPC[1]), .CK(clk_25mhz), .Q(CurrentPC[1]), .QN()); + AOI22_X1_LVT i_0_0_1 (.A1(JumpOrBranchPC[0]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(CurrentPC[0]), .ZN(n_0_0_0)); + INV_X1_LVT i_0_0_0 (.A(n_0_0_0), .ZN(thePC_n_30)); + SDFF_X1_LVT \thePC_CurrentPC_reg[0] (.D(thePC_n_30), .SE(1'b0), .SI( + CurrentPC[0]), .CK(clk_25mhz), .Q(CurrentPC[0]), .QN()); + reg_file theRegisters (.Rs1({Instruction[19], Instruction[18], + Instruction[17], Instruction[16], Instruction[15]}), .Rs2({Instruction[24], + Instruction[23], Instruction[22], Instruction[21], Instruction[20]}), + .Rd({Instruction[11], Instruction[10], Instruction[9], Instruction[8], + Instruction[7]}), .RRs1(RRs1), .RRs2(RRs2), .WRd(WRd), .WrReg(WrReg), + .reset(reset), .clk(clk_25mhz), .dftIn(scan_en)); + main_mem theMem (.clk(clk_25mhz), .reset(reset), .DAddr({uc_0, uc_1, uc_2, + uc_3, uc_4, uc_5, uc_6, uc_7, uc_8, uc_9, uc_10, uc_11, uc_12, uc_13, + uc_14, uc_15, uc_16, uc_17, uc_18, DAddr[12], DAddr[11], DAddr[10], + DAddr[9], DAddr[8], DAddr[7], DAddr[6], DAddr[5], DAddr[4], DAddr[3], + DAddr[2], DAddr[1], DAddr[0]}), .IAddr({uc_19, uc_20, uc_21, uc_22, uc_23, + uc_24, uc_25, uc_26, uc_27, uc_28, uc_29, uc_30, uc_31, uc_32, uc_33, + uc_34, uc_35, uc_36, uc_37, NextPC[12], NextPC[11], NextPC[10], NextPC[9], + NextPC[8], led[7], led[6], led[5], led[4], led[3], led[2], uc_38, uc_39}), + .DWData(RRs2), .DRData(RData), .IRData(Instruction), .DWE(led[1]), + .DWidth(DWidth)); + decoder theDecoder (.CurrentPC(CurrentPC), .JumpOrBranchPC(JumpOrBranchPC), + .JumpOrBranch(JumpOrBranch), .DAddr({uc_40, uc_41, uc_42, uc_43, uc_44, + uc_45, uc_46, uc_47, uc_48, uc_49, uc_50, uc_51, uc_52, uc_53, uc_54, + uc_55, uc_56, uc_57, uc_58, DAddr[12], DAddr[11], DAddr[10], DAddr[9], + DAddr[8], DAddr[7], DAddr[6], DAddr[5], DAddr[4], DAddr[3], DAddr[2], + DAddr[1], DAddr[0]}), .WData(), .RData(RData), .Instruction(Instruction), + .WrMem(led[1]), .DWidth(DWidth), .Rs1(), .Rs2(), .Rd(), .RRs1(RRs1), + .RRs2(RRs2), .WRd(WRd), .WrReg(WrReg), .Illegal(led[0])); + MUX2_X1_LVT i_0_0_60 (.A(thePC_n_5), .B(JumpOrBranchPC[7]), .S(JumpOrBranch), + .Z(led[7])); +endmodule diff --git a/oasys.tessent.01/Scan_0/post_scan.v b/oasys.tessent.01/Scan_0/post_scan.v new file mode 100644 index 0000000..fdac9f6 --- /dev/null +++ b/oasys.tessent.01/Scan_0/post_scan.v @@ -0,0 +1,15792 @@ +/* Generated by Tessent Shell 2023.4-p1 at Fri May 29 09:09:59 CEST 2026 */ +module alu(aluOp, aluNegAr, aluBypass, op1, op2, result, eqFlag); + input [31:0] op1, op2; + input [2:0] aluOp; + input aluNegAr, aluBypass; + output [31:0] result; + output eqFlag; + + wire n_9_0, n_9_1, n_9_2, n_9_3, n_9_4, n_9_5, n_9_6, n_9_7, n_9_8, n_9_9, + n_9_10, n_9_11, n_9_12, n_9_13, n_9_14, n_9_15, n_9_16, n_9_17, n_9_18, + n_9_19, n_9_20, n_9_21, n_9_22, n_9_23, n_9_24, n_9_25, n_9_26, n_9_27, + n_9_28, n_9_29, n_9_30, n_9_31, n_10_0, n_10_1, n_10_2, n_10_3, n_10_4, + n_10_5, n_10_6, n_10_7, n_10_8, n_10_9, n_10_10, n_10_11, n_10_12, + n_10_13, n_10_14, n_10_15, n_10_16, n_10_17, n_10_18, n_10_19, n_10_20, + n_10_21, n_10_22, n_10_23, n_10_24, n_10_25, n_10_26, n_10_27, n_10_28, + n_10_29, n_10_30, n_10_31, n_10_32, n_10_33, n_10_34, n_10_35, n_10_36, + n_10_37, n_10_38, n_10_39, n_10_40, n_10_41, n_10_42, n_10_43, n_10_44, + n_10_45, n_10_46, n_10_47, n_10_48, n_10_49, n_10_50, n_10_51, n_10_52, + n_10_53, n_10_54, n_10_55, n_10_56, n_10_57, n_10_58, n_10_59, n_10_60, + n_10_61, n_10_62, n_10_63, n_10_64, n_10_65, n_10_66, n_10_67, n_10_68, + n_10_69, n_10_70, n_10_71, n_10_72, n_10_73, n_10_74, n_10_75, n_10_76, + n_10_77, n_10_78, n_10_79, n_10_80, n_10_81, n_10_82, n_10_83, n_10_84, + n_10_85, n_10_86, n_10_87, n_10_88, n_10_89, n_10_90, n_10_91, n_10_92, + n_10_93, n_10_94, n_10_95, n_10_96, n_10_97, n_10_98, n_10_99, n_10_100, + n_10_101, n_10_102, n_10_103, n_10_104, n_10_105, n_10_106, n_10_107, + n_10_108, n_10_109, n_10_110, n_10_111, n_10_112, n_10_113, n_10_114, + n_10_115, n_10_116, n_10_117, n_10_118, n_10_119, n_10_120, n_10_121, + n_10_122, n_10_123, n_0_0, n_0_1, n_0_2, n_0_3, n_0_4, n_0_5, n_0_6, + n_0_7, n_0_8, n_0_9, n_0_10, n_0_11, n_0_12, n_0_13, n_0_14, n_0_15, + n_0_16, n_0_17, n_0_18, n_0_19, n_0_20, n_0_21, n_0_22, n_0_23, n_0_24, + n_0_25, n_0_26, n_0_27, n_0_28, n_0_29, n_0_30, n_0_31, n_0_32, n_0_33, + n_0_34, n_0_35, n_0_36, n_0_37, n_0_38, n_0_39, n_0_40, n_0_41, n_0_42, + n_0_43, n_0_44, n_0_45, n_0_46, n_0_47, n_0_48, n_0_49, n_0_50, n_0_51, + n_0_52, n_0_53, n_0_54, n_0_55, n_0_56, n_0_57, n_0_58, n_0_59, n_0_60, + n_0_61, n_0_62, n_0_63, n_0_64, n_0_65, n_0_66, n_0_67, n_0_68, n_0_69, + n_0_70, n_0_71, n_0_72, n_0_73, n_0_74, n_0_75, n_0_76, n_0_77, n_0_78, + n_0_79, n_0_80, n_0_81, n_0_82, n_0_83, n_0_84, n_0_85, n_0_86, n_0_87, + n_0_88, n_0_89, n_0_90, n_0_91, n_0_92, n_0_93, n_0_94, n_0_95, n_0_96, + n_0_97, n_0_98, n_0_99, n_0_100, n_0_101, n_0_102, n_0_103, n_0_104, + n_0_105, n_0_106, n_0_107, n_0_108, n_0_109, n_0_110, n_0_111, n_0_112, + n_0_113, n_0_114, n_0_115, n_0_116, n_0_117, n_0_118, n_0_119, n_0_120, + n_0_121, n_0_122, n_0_123, n_0_124, n_0_125, n_0_126, n_0_127, n_0_128, + n_0_129, n_0_130, n_0_131, n_0_132, n_0_133, n_0_134, n_0_135, n_0_136, + n_0_137, n_0_138, n_0_139, n_0_140, n_0_141, n_0_142, n_0_143, n_0_144, + n_0_145, n_0_146, n_0_147, n_0_148, n_0_149, n_0_150, n_0_151, n_0_152, + n_0_153, n_0_154, n_0_155, n_0_156, n_0_157, n_0_158, n_0_159, n_0_160, + n_0_161, n_0_162, n_0_163, n_0_164, n_0_165, n_0_166, n_0_167, n_0_168, + n_0_169, n_0_170, n_0_171, n_0_172, n_0_173, n_0_174, n_0_175, n_0_176, + n_0_177, n_0_178, n_0_179, n_0_180, n_0_181, n_0_182, n_0_183, n_0_184, + n_0_185, n_0_186, n_0_187, n_0_188, n_0_189, n_0_190, n_0_191, n_0_192, + n_0_193, n_0_194, n_0_195, n_0_196, n_0_197, n_0_198, n_0_199, n_0_200, + n_0_201, n_0_202, n_0_203, n_0_204, n_0_205, n_0_206, n_0_207, n_0_208, + n_0_209, n_0_210, n_0_211, n_0_212, n_0_213, n_0_214, n_0_215, n_0_216, + n_0_217, n_0_218, n_0_219, n_0_220, n_0_221, n_0_222, n_0_223, n_0_224, + n_0_225, n_0_226, n_0_227, n_0_228, n_0_229, n_0_230, n_0_231, n_0_232, + n_0_233, n_0_234, n_0_235, n_0_236, n_0_237, n_0_238, n_0_239, n_0_240, + n_0_241, n_0_242, n_0_243, n_0_244, n_0_245, n_0_246, n_0_247, n_0_248, + n_0_249, n_0_250, n_0_251, n_0_252, n_0_253, n_0_254, n_0_255, n_0_256, + n_0_257, n_0_258, n_0_259, n_0_260, n_0_261, n_0_262, n_0_263, n_0_264, + n_0_265, n_0_266, n_0_267, n_0_268, n_0_269, n_0_270, n_0_271, n_0_272, + n_0_273, n_0_274, n_0_275, n_0_276, n_0_277, n_0_278, n_0_279, n_0_280, + n_0_281, n_0_282, n_0_283, n_0_284, n_0_285, n_0_286, n_0_287, n_0_288, + n_0_289, n_0_290, n_0_291, n_0_292, n_0_293, n_0_294, n_0_295, n_0_296, + n_0_297, n_0_298, n_0_299, n_0_300, n_0_301, n_0_302, n_0_303, n_0_304, + n_0_305, n_0_306, n_0_307, n_0_308, n_0_309, n_0_310, n_0_311, n_0_312, + n_0_313, n_0_314, n_0_315, n_0_316, n_0_317, n_0_318, n_0_319, n_0_320, + n_0_321, n_0_322, n_0_323, n_0_324, n_0_325, n_0_326, n_0_327, n_0_328, + n_0_329, n_0_330, n_0_331, n_0_332, n_0_333, n_0_334, n_0_335, n_0_336, + n_0_337, n_0_338, n_0_339, n_0_340, n_0_341, n_0_342, n_0_343, n_0_344, + n_0_345, n_0_346, n_0_347, n_0_348, n_0_349, n_0_350, n_0_351, n_0_352, + n_0_353, n_0_354, n_0_355, n_0_356, n_0_357, n_0_358, n_0_359, n_0_360, + n_0_361, n_0_362, n_0_363, n_0_364, n_0_365, n_0_366, n_0_367, n_0_368, + n_0_369, n_0_370, n_0_371, n_0_372, n_0_373, n_0_374, n_0_375, n_0_376, + n_0_377, n_0_378, n_0_379, n_0_380, n_0_381, n_0_382, n_0_383, n_0_384, + n_0_385, n_0_386, n_0_387, n_0_388, n_0_389, n_0_390, n_0_391, n_0_392, + n_0_393, n_0_394, n_0_395, n_0_396, n_0_397, n_0_398, n_0_399, n_0_400, + n_0_401, n_0_402, n_0_403, n_0_404, n_0_405, n_0_406, n_0_407, n_0_408, + n_0_409, n_0_410, n_0_411, n_0_412, n_0_413, n_0_414, n_0_415, n_0_416, + n_0_417, n_0_418, n_0_419, n_0_420, n_0_421, n_0_422, n_0_423, n_0_424, + n_0_425, n_0_426, n_0_427, n_0_428, n_0_429, n_0_430, n_0_431, n_0_432, + n_0_433, n_0_434, n_0_435, n_0_436, n_0_437, n_0_438, n_0_439, n_0_440, + n_0_441, n_0_442, n_0_443, n_0_444, n_0_445, n_0_446, n_0_447, n_0_448, + n_0_449, n_0_450, n_0_451, n_0_452, n_0_453, n_0_454, n_0_455, n_0_456, + n_0_457, n_0_458, n_0_459, n_0_460, n_0_461, n_0_462, n_0_463, n_0_464, + n_0_465, n_0_466, n_0_467, n_0_468, n_0_469, n_0_470, n_0_471, n_0_472, + n_0_473, n_0_474, n_0_475, n_0_476, n_0_477, n_0_478, n_0_479, n_0_480, + n_0_481, n_0_482, n_0_483, n_0_484, n_0_485, n_0_486, n_0_487, n_0_488, + n_0_489, n_0_490, n_0_491, n_0_492, n_0_493, n_0_494, n_0_495, n_0_496, + n_0_497, n_0_498, n_0_499, n_0_500, n_0_501, n_0_502, n_0_503, n_0_504, + n_0_505, n_0_506, n_0_507, n_0_508, n_0_509, n_0_510, n_0_511, n_0_512, + n_0_513, n_0_514, n_0_515, n_0_516, n_0_517, n_0_518, n_0_519, n_0_520, + n_0_521, n_0_522, n_0_523, n_0_524, n_0_525, n_0_526, n_0_527, n_0_528, + n_0_529, n_0_530, n_0_531, n_0_532, n_0_533, n_0_534, n_0_535, n_0_536, + n_0_537, n_0_538, n_0_539, n_0_540, n_0_541, n_0_542, n_0_543, n_0_544, + n_0_545, n_0_546, n_0_547, n_0_548, n_0_549, n_0_550, n_0_551, n_0_552, + n_0_553, n_0_554, n_0_555, n_0_556, n_0_557, n_0_558, n_0_559, n_0_560, + n_0_561, n_0_562, n_0_563, n_0_564, n_0_565, n_0_566, n_0_567, n_0_568, + n_0_569, n_0_570, n_0_571, n_0_572, n_0_573, n_0_574, n_0_575, n_0_576, + n_0_577, n_0_578, n_0_579, n_0_580, n_0_581, n_0_582, n_0_583, n_0_584, + n_0_585, n_0_586, n_0_587, n_0_588, n_0_589, n_0_590, n_0_591, n_0_592, + n_0_593, n_0_594, n_0_595, n_0_596, n_0_597, n_0_598, n_0_599, n_0_600, + n_0_601, n_0_602, n_0_603, n_0_604, n_0_605, n_0_606, n_0_607, n_0_608, + n_0_609, n_0_610, n_0_611, n_0_612, n_0_613, n_0_614, n_0_615, n_0_616, + n_0_617, n_0_618, n_0_619, n_0_620, n_0_621, n_0_622, n_0_623, n_0_624, + n_0_625, n_0_626, n_0_627, n_0_628, n_0_629, n_0_630, n_0_631, n_0_632, + n_0_633, n_0_634, n_0_635, n_0_636, n_0_637, n_0_638, n_0_639, n_0_640, + n_0_641, n_0_642, n_0_643, n_0_644, n_0_645, n_0_646, n_0_647, n_0_648, + n_0_649, n_0_650, n_0_651, n_0_652, n_0_653, n_0_654, n_0_655, n_0_656, + n_0_657, n_0_658, n_0_659, n_0_660, n_0_661, n_0_662, n_0_663, n_0_664, + n_0_665, n_0_666, n_0_667, n_0_668, n_0_669, n_0_670, n_0_671, n_0_672, + n_0_673, n_0_674, n_0_675, n_0_676, n_0_677, n_0_678, n_0_679, n_0_680, + n_0_681, n_0_682, n_0_683, n_0_684, n_0_685, n_0_686, n_0_687, n_0_688, + n_0_689, n_0_690, n_0_691, n_0_692, n_0_693, n_0_694, n_0_695, n_0_696, + n_0_697, n_0_698, n_0_699, n_0_700, n_0_701, n_0_702, n_0_703, n_0_704, + n_0_705, n_0_706, n_0_707, n_0_708, n_0_709, n_0_710, n_0_711, n_0_712, + n_0_713, n_0_714, n_0_715, n_0_716, n_0_717, n_0_718, n_0_719, n_0_720, + n_0_721, n_0_722, n_0_723, n_0_724, n_0_725, n_0_726, n_0_727, n_0_728, + n_0_729, n_0_730, n_0_731, n_0_732, n_0_733, n_0_734, n_0_735, n_0_736, + n_0_737, n_0_738, n_0_739, n_0_740, n_0, n_1, n_2, n_3, n_4, n_5, n_6, + n_7, n_8, n_9, n_10, n_11, n_12, n_13, n_14, n_15, n_16, n_17, n_18, + n_19, n_20, n_21, n_22, n_23, n_24, n_25, n_26, n_27, n_28, n_29, n_30, + n_31, n_63, n_62, n_61, n_60, n_59, n_58, n_57, n_56, n_55, n_54, n_53, + n_52, n_51, n_50, n_49, n_48, n_47, n_46, n_45, n_44, n_43, n_42, n_41, + n_40, n_39, n_38, n_37, n_36, n_35, n_34, n_33, n_32; + + INV_X1_LVT i_0_725( + .A(op2[31]), .ZN(n_0_692) + ); + INV_X1_LVT i_0_724( + .A(op1[31]), .ZN(n_0_691) + ); + INV_X1_LVT i_0_718( + .A(aluOp[1]), .ZN(n_0_685) + ); + INV_X1_LVT i_0_717( + .A(aluOp[2]), .ZN(n_0_684) + ); + NOR2_X1_LVT i_0_599( + .A1(n_0_685), .A2(n_0_684), .ZN(n_0_567) + ); + INV_X1_LVT i_0_598( + .A(n_0_567), .ZN(n_0_566) + ); + INV_X1_LVT i_0_716( + .A(aluOp[0]), .ZN(n_0_683) + ); + NAND2_X1_LVT i_0_602( + .A1(aluOp[2]), .A2(aluNegAr), .ZN(n_0_570) + ); + OAI21_X1_LVT i_0_590( + .A(n_0_566), .B1(n_0_683), .B2(n_0_570), .ZN(n_0_558) + ); + INV_X1_LVT i_0_714( + .A(aluBypass), .ZN(n_0_681) + ); + NOR2_X1_LVT i_0_601( + .A1(n_0_684), .A2(aluOp[0]), .ZN(n_0_569) + ); + NAND2_X1_LVT i_0_597( + .A1(n_0_681), .A2(n_0_569), .ZN(n_0_565) + ); + INV_X1_LVT i_0_596( + .A(n_0_565), .ZN(n_0_564) + ); + OAI22_X1_LVT i_0_589( + .A1(n_0_691), .A2(n_0_558), .B1(op1[31]), .B2(n_0_564), .ZN(n_0_557) + ); + NOR2_X1_LVT i_0_588( + .A1(n_0_692), .A2(n_0_557), .ZN(n_0_556) + ); + XNOR2_X1_LVT i_9_31( + .A(op2[31]), .B(op1[31]), .ZN(n_9_31) + ); + HA_X1_LVT i_9_0( + .A(op2[0]), .B(op1[0]), .CO(n_9_0), .S(n_0) + ); + FA_X1_LVT i_9_1( + .A(op2[1]), .B(op1[1]), .CI(n_9_0), .CO(n_9_1), .S(n_1) + ); + FA_X1_LVT i_9_2( + .A(op2[2]), .B(op1[2]), .CI(n_9_1), .CO(n_9_2), .S(n_2) + ); + FA_X1_LVT i_9_3( + .A(op2[3]), .B(op1[3]), .CI(n_9_2), .CO(n_9_3), .S(n_3) + ); + FA_X1_LVT i_9_4( + .A(op2[4]), .B(op1[4]), .CI(n_9_3), .CO(n_9_4), .S(n_4) + ); + FA_X1_LVT i_9_5( + .A(op2[5]), .B(op1[5]), .CI(n_9_4), .CO(n_9_5), .S(n_5) + ); + FA_X1_LVT i_9_6( + .A(op2[6]), .B(op1[6]), .CI(n_9_5), .CO(n_9_6), .S(n_6) + ); + FA_X1_LVT i_9_7( + .A(op2[7]), .B(op1[7]), .CI(n_9_6), .CO(n_9_7), .S(n_7) + ); + FA_X1_LVT i_9_8( + .A(op2[8]), .B(op1[8]), .CI(n_9_7), .CO(n_9_8), .S(n_8) + ); + FA_X1_LVT i_9_9( + .A(op2[9]), .B(op1[9]), .CI(n_9_8), .CO(n_9_9), .S(n_9) + ); + FA_X1_LVT i_9_10( + .A(op2[10]), .B(op1[10]), .CI(n_9_9), .CO(n_9_10), .S(n_10) + ); + FA_X1_LVT i_9_11( + .A(op2[11]), .B(op1[11]), .CI(n_9_10), .CO(n_9_11), .S(n_11) + ); + FA_X1_LVT i_9_12( + .A(op2[12]), .B(op1[12]), .CI(n_9_11), .CO(n_9_12), .S(n_12) + ); + FA_X1_LVT i_9_13( + .A(op2[13]), .B(op1[13]), .CI(n_9_12), .CO(n_9_13), .S(n_13) + ); + FA_X1_LVT i_9_14( + .A(op2[14]), .B(op1[14]), .CI(n_9_13), .CO(n_9_14), .S(n_14) + ); + FA_X1_LVT i_9_15( + .A(op2[15]), .B(op1[15]), .CI(n_9_14), .CO(n_9_15), .S(n_15) + ); + FA_X1_LVT i_9_16( + .A(op2[16]), .B(op1[16]), .CI(n_9_15), .CO(n_9_16), .S(n_16) + ); + FA_X1_LVT i_9_17( + .A(op2[17]), .B(op1[17]), .CI(n_9_16), .CO(n_9_17), .S(n_17) + ); + FA_X1_LVT i_9_18( + .A(op2[18]), .B(op1[18]), .CI(n_9_17), .CO(n_9_18), .S(n_18) + ); + FA_X1_LVT i_9_19( + .A(op2[19]), .B(op1[19]), .CI(n_9_18), .CO(n_9_19), .S(n_19) + ); + FA_X1_LVT i_9_20( + .A(op2[20]), .B(op1[20]), .CI(n_9_19), .CO(n_9_20), .S(n_20) + ); + FA_X1_LVT i_9_21( + .A(op2[21]), .B(op1[21]), .CI(n_9_20), .CO(n_9_21), .S(n_21) + ); + FA_X1_LVT i_9_22( + .A(op2[22]), .B(op1[22]), .CI(n_9_21), .CO(n_9_22), .S(n_22) + ); + FA_X1_LVT i_9_23( + .A(op2[23]), .B(op1[23]), .CI(n_9_22), .CO(n_9_23), .S(n_23) + ); + FA_X1_LVT i_9_24( + .A(op2[24]), .B(op1[24]), .CI(n_9_23), .CO(n_9_24), .S(n_24) + ); + FA_X1_LVT i_9_25( + .A(op2[25]), .B(op1[25]), .CI(n_9_24), .CO(n_9_25), .S(n_25) + ); + FA_X1_LVT i_9_26( + .A(op2[26]), .B(op1[26]), .CI(n_9_25), .CO(n_9_26), .S(n_26) + ); + FA_X1_LVT i_9_27( + .A(op2[27]), .B(op1[27]), .CI(n_9_26), .CO(n_9_27), .S(n_27) + ); + FA_X1_LVT i_9_28( + .A(op2[28]), .B(op1[28]), .CI(n_9_27), .CO(n_9_28), .S(n_28) + ); + FA_X1_LVT i_9_29( + .A(op2[29]), .B(op1[29]), .CI(n_9_28), .CO(n_9_29), .S(n_29) + ); + FA_X1_LVT i_9_30( + .A(op2[30]), .B(op1[30]), .CI(n_9_29), .CO(n_9_30), .S(n_30) + ); + XNOR2_X1_LVT i_9_32( + .A(n_9_31), .B(n_9_30), .ZN(n_31) + ); + NAND4_X1_LVT i_0_614( + .A1(n_0_685), .A2(n_0_681), .A3(n_0_684), .A4(n_0_683), .ZN(n_0_582) + ); + NOR2_X1_LVT i_0_613( + .A1(aluNegAr), .A2(n_0_582), .ZN(n_0_581) + ); + INV_X1_LVT i_10_147( + .A(op2[30]), .ZN(n_10_117) + ); + NAND2_X1_LVT i_10_149( + .A1(n_10_117), .A2(op1[30]), .ZN(n_10_119) + ); + INV_X1_LVT i_10_152( + .A(n_10_119), .ZN(n_10_121) + ); + INV_X1_LVT i_10_130( + .A(op1[26]), .ZN(n_10_104) + ); + NAND2_X1_LVT i_10_131( + .A1(n_10_104), .A2(op2[26]), .ZN(n_10_105) + ); + INV_X1_LVT i_10_123( + .A(op2[25]), .ZN(n_10_98) + ); + NAND2_X1_LVT i_10_125( + .A1(n_10_98), .A2(op1[25]), .ZN(n_10_100) + ); + INV_X1_LVT i_10_112( + .A(op2[23]), .ZN(n_10_89) + ); + NAND2_X1_LVT i_10_114( + .A1(n_10_89), .A2(op1[23]), .ZN(n_10_91) + ); + INV_X1_LVT i_10_101( + .A(op2[21]), .ZN(n_10_80) + ); + NAND2_X1_LVT i_10_103( + .A1(n_10_80), .A2(op1[21]), .ZN(n_10_82) + ); + INV_X1_LVT i_10_48( + .A(op1[8]), .ZN(n_10_40) + ); + NAND2_X1_LVT i_10_49( + .A1(n_10_40), .A2(op2[8]), .ZN(n_10_41) + ); + INV_X1_LVT i_10_41( + .A(op2[7]), .ZN(n_10_34) + ); + NAND2_X1_LVT i_10_43( + .A1(n_10_34), .A2(op1[7]), .ZN(n_10_36) + ); + INV_X1_LVT i_10_32( + .A(op2[5]), .ZN(n_10_27) + ); + NOR2_X1_LVT i_10_33( + .A1(n_10_27), .A2(op1[5]), .ZN(n_10_28) + ); + INV_X1_LVT i_10_24( + .A(op1[4]), .ZN(n_10_20) + ); + NOR2_X1_LVT i_10_27( + .A1(n_10_20), .A2(op2[4]), .ZN(n_10_23) + ); + INV_X1_LVT i_10_17( + .A(op2[3]), .ZN(n_10_14) + ); + NAND2_X1_LVT i_10_19( + .A1(n_10_14), .A2(op1[3]), .ZN(n_10_16) + ); + INV_X1_LVT i_10_22( + .A(n_10_16), .ZN(n_10_18) + ); + INV_X1_LVT i_10_10( + .A(op2[2]), .ZN(n_10_8) + ); + NAND2_X1_LVT i_10_12( + .A1(n_10_8), .A2(op1[2]), .ZN(n_10_10) + ); + INV_X1_LVT i_10_3( + .A(op1[1]), .ZN(n_10_2) + ); + NAND2_X1_LVT i_10_5( + .A1(n_10_2), .A2(op2[1]), .ZN(n_10_4) + ); + INV_X1_LVT i_10_0( + .A(op1[0]), .ZN(n_10_0) + ); + NAND2_X1_LVT i_10_1( + .A1(n_10_0), .A2(op2[0]), .ZN(n_10_1) + ); + OR2_X1_LVT i_10_4( + .A1(n_10_2), .A2(op2[1]), .ZN(n_10_3) + ); + INV_X1_LVT i_10_8( + .A(n_10_3), .ZN(n_10_6) + ); + OAI21_X1_LVT i_10_9( + .A(n_10_4), .B1(n_10_1), .B2(n_10_6), .ZN(n_10_7) + ); + NOR2_X1_LVT i_10_11( + .A1(n_10_8), .A2(op1[2]), .ZN(n_10_9) + ); + OAI21_X1_LVT i_10_16( + .A(n_10_10), .B1(n_10_7), .B2(n_10_9), .ZN(n_10_13) + ); + OR2_X1_LVT i_10_18( + .A1(n_10_14), .A2(op1[3]), .ZN(n_10_15) + ); + AOI21_X1_LVT i_10_23( + .A(n_10_18), .B1(n_10_13), .B2(n_10_15), .ZN(n_10_19) + ); + INV_X1_LVT i_10_30( + .A(n_10_19), .ZN(n_10_25) + ); + NAND2_X1_LVT i_10_25( + .A1(n_10_20), .A2(op2[4]), .ZN(n_10_21) + ); + AOI21_X1_LVT i_10_31( + .A(n_10_23), .B1(n_10_25), .B2(n_10_21), .ZN(n_10_26) + ); + AOI21_X1_LVT i_10_34( + .A(n_10_28), .B1(n_10_27), .B2(op1[5]), .ZN(n_10_29) + ); + AOI21_X1_LVT i_10_36( + .A(n_10_28), .B1(n_10_26), .B2(n_10_29), .ZN(n_10_30) + ); + XOR2_X1_LVT i_10_37( + .A(op2[6]), .B(op1[6]), .Z(n_10_31) + ); + INV_X1_LVT i_10_39( + .A(op2[6]), .ZN(n_10_32) + ); + OAI22_X1_LVT i_10_40( + .A1(n_10_30), .A2(n_10_31), .B1(n_10_32), .B2(op1[6]), .ZN(n_10_33) + ); + NOR2_X1_LVT i_10_42( + .A1(n_10_34), .A2(op1[7]), .ZN(n_10_35) + ); + OAI21_X1_LVT i_10_47( + .A(n_10_36), .B1(n_10_33), .B2(n_10_35), .ZN(n_10_39) + ); + OAI21_X1_LVT i_10_50( + .A(n_10_41), .B1(n_10_40), .B2(op2[8]), .ZN(n_10_42) + ); + OAI21_X1_LVT i_10_52( + .A(n_10_41), .B1(n_10_39), .B2(n_10_42), .ZN(n_10_43) + ); + XNOR2_X1_LVT i_10_53( + .A(op2[9]), .B(op1[9]), .ZN(n_10_44) + ); + INV_X1_LVT i_10_55( + .A(op1[9]), .ZN(n_10_45) + ); + AOI22_X1_LVT i_10_56( + .A1(n_10_43), .A2(n_10_44), .B1(n_10_45), .B2(op2[9]), .ZN(n_10_46) + ); + XOR2_X1_LVT i_10_57( + .A(op2[10]), .B(op1[10]), .Z(n_10_47) + ); + INV_X1_LVT i_10_59( + .A(op2[10]), .ZN(n_10_48) + ); + OAI22_X1_LVT i_10_60( + .A1(n_10_46), .A2(n_10_47), .B1(n_10_48), .B2(op1[10]), .ZN(n_10_49) + ); + XNOR2_X1_LVT i_10_61( + .A(op2[11]), .B(op1[11]), .ZN(n_10_50) + ); + INV_X1_LVT i_10_63( + .A(op1[11]), .ZN(n_10_51) + ); + AOI22_X1_LVT i_10_64( + .A1(n_10_49), .A2(n_10_50), .B1(n_10_51), .B2(op2[11]), .ZN(n_10_52) + ); + XOR2_X1_LVT i_10_65( + .A(op2[12]), .B(op1[12]), .Z(n_10_53) + ); + INV_X1_LVT i_10_67( + .A(op2[12]), .ZN(n_10_54) + ); + OAI22_X1_LVT i_10_68( + .A1(n_10_52), .A2(n_10_53), .B1(n_10_54), .B2(op1[12]), .ZN(n_10_55) + ); + XNOR2_X1_LVT i_10_69( + .A(op2[13]), .B(op1[13]), .ZN(n_10_56) + ); + INV_X1_LVT i_10_71( + .A(op1[13]), .ZN(n_10_57) + ); + AOI22_X1_LVT i_10_72( + .A1(n_10_55), .A2(n_10_56), .B1(n_10_57), .B2(op2[13]), .ZN(n_10_58) + ); + XOR2_X1_LVT i_10_73( + .A(op2[14]), .B(op1[14]), .Z(n_10_59) + ); + INV_X1_LVT i_10_75( + .A(op2[14]), .ZN(n_10_60) + ); + OAI22_X1_LVT i_10_76( + .A1(n_10_58), .A2(n_10_59), .B1(n_10_60), .B2(op1[14]), .ZN(n_10_61) + ); + XNOR2_X1_LVT i_10_77( + .A(op2[15]), .B(op1[15]), .ZN(n_10_62) + ); + INV_X1_LVT i_10_79( + .A(op1[15]), .ZN(n_10_63) + ); + AOI22_X1_LVT i_10_80( + .A1(n_10_61), .A2(n_10_62), .B1(n_10_63), .B2(op2[15]), .ZN(n_10_64) + ); + XOR2_X1_LVT i_10_81( + .A(op2[16]), .B(op1[16]), .Z(n_10_65) + ); + INV_X1_LVT i_10_83( + .A(op2[16]), .ZN(n_10_66) + ); + OAI22_X1_LVT i_10_84( + .A1(n_10_64), .A2(n_10_65), .B1(n_10_66), .B2(op1[16]), .ZN(n_10_67) + ); + XNOR2_X1_LVT i_10_85( + .A(op2[17]), .B(op1[17]), .ZN(n_10_68) + ); + INV_X1_LVT i_10_87( + .A(op1[17]), .ZN(n_10_69) + ); + AOI22_X1_LVT i_10_88( + .A1(n_10_67), .A2(n_10_68), .B1(n_10_69), .B2(op2[17]), .ZN(n_10_70) + ); + XOR2_X1_LVT i_10_89( + .A(op2[18]), .B(op1[18]), .Z(n_10_71) + ); + INV_X1_LVT i_10_91( + .A(op2[18]), .ZN(n_10_72) + ); + OAI22_X1_LVT i_10_92( + .A1(n_10_70), .A2(n_10_71), .B1(n_10_72), .B2(op1[18]), .ZN(n_10_73) + ); + XNOR2_X1_LVT i_10_93( + .A(op2[19]), .B(op1[19]), .ZN(n_10_74) + ); + INV_X1_LVT i_10_95( + .A(op1[19]), .ZN(n_10_75) + ); + AOI22_X1_LVT i_10_96( + .A1(n_10_73), .A2(n_10_74), .B1(n_10_75), .B2(op2[19]), .ZN(n_10_76) + ); + XOR2_X1_LVT i_10_97( + .A(op2[20]), .B(op1[20]), .Z(n_10_77) + ); + INV_X1_LVT i_10_99( + .A(op2[20]), .ZN(n_10_78) + ); + OAI22_X1_LVT i_10_100( + .A1(n_10_76), .A2(n_10_77), .B1(n_10_78), .B2(op1[20]), .ZN(n_10_79) + ); + NOR2_X1_LVT i_10_102( + .A1(n_10_80), .A2(op1[21]), .ZN(n_10_81) + ); + OAI21_X1_LVT i_10_107( + .A(n_10_82), .B1(n_10_79), .B2(n_10_81), .ZN(n_10_85) + ); + XOR2_X1_LVT i_10_108( + .A(op2[22]), .B(op1[22]), .Z(n_10_86) + ); + INV_X1_LVT i_10_110( + .A(op2[22]), .ZN(n_10_87) + ); + OAI22_X1_LVT i_10_111( + .A1(n_10_85), .A2(n_10_86), .B1(n_10_87), .B2(op1[22]), .ZN(n_10_88) + ); + NOR2_X1_LVT i_10_113( + .A1(n_10_89), .A2(op1[23]), .ZN(n_10_90) + ); + OAI21_X1_LVT i_10_118( + .A(n_10_91), .B1(n_10_88), .B2(n_10_90), .ZN(n_10_94) + ); + XOR2_X1_LVT i_10_119( + .A(op2[24]), .B(op1[24]), .Z(n_10_95) + ); + INV_X1_LVT i_10_121( + .A(op2[24]), .ZN(n_10_96) + ); + OAI22_X1_LVT i_10_122( + .A1(n_10_94), .A2(n_10_95), .B1(n_10_96), .B2(op1[24]), .ZN(n_10_97) + ); + NOR2_X1_LVT i_10_124( + .A1(n_10_98), .A2(op1[25]), .ZN(n_10_99) + ); + OAI21_X1_LVT i_10_129( + .A(n_10_100), .B1(n_10_97), .B2(n_10_99), .ZN(n_10_103) + ); + OAI21_X1_LVT i_10_132( + .A(n_10_105), .B1(n_10_104), .B2(op2[26]), .ZN(n_10_106) + ); + OAI21_X1_LVT i_10_134( + .A(n_10_105), .B1(n_10_103), .B2(n_10_106), .ZN(n_10_107) + ); + XNOR2_X1_LVT i_10_135( + .A(op2[27]), .B(op1[27]), .ZN(n_10_108) + ); + INV_X1_LVT i_10_137( + .A(op1[27]), .ZN(n_10_109) + ); + AOI22_X1_LVT i_10_138( + .A1(n_10_107), .A2(n_10_108), .B1(n_10_109), .B2(op2[27]), .ZN(n_10_110) + ); + XOR2_X1_LVT i_10_139( + .A(op2[28]), .B(op1[28]), .Z(n_10_111) + ); + INV_X1_LVT i_10_141( + .A(op2[28]), .ZN(n_10_112) + ); + OAI22_X1_LVT i_10_142( + .A1(n_10_110), .A2(n_10_111), .B1(n_10_112), .B2(op1[28]), .ZN(n_10_113) + ); + XNOR2_X1_LVT i_10_143( + .A(op2[29]), .B(op1[29]), .ZN(n_10_114) + ); + INV_X1_LVT i_10_145( + .A(op1[29]), .ZN(n_10_115) + ); + AOI22_X1_LVT i_10_146( + .A1(n_10_113), .A2(n_10_114), .B1(n_10_115), .B2(op2[29]), .ZN(n_10_116) + ); + OR2_X1_LVT i_10_148( + .A1(n_10_117), .A2(op1[30]), .ZN(n_10_118) + ); + AOI21_X1_LVT i_10_153( + .A(n_10_121), .B1(n_10_116), .B2(n_10_118), .ZN(n_10_122) + ); + XNOR2_X1_LVT i_10_154( + .A(op1[31]), .B(op2[31]), .ZN(n_10_123) + ); + XNOR2_X1_LVT i_10_155( + .A(n_10_122), .B(n_10_123), .ZN(n_63) + ); + INV_X1_LVT i_0_715( + .A(aluNegAr), .ZN(n_0_682) + ); + NOR2_X1_LVT i_0_612( + .A1(n_0_682), .A2(n_0_582), .ZN(n_0_580) + ); + AOI221_X1_LVT i_0_587( + .A(n_0_556), .B1(n_31), .B2(n_0_581), .C1(n_63), .C2(n_0_580), .ZN(n_0_555) + ); + NOR3_X1_LVT i_0_654( + .A1(aluOp[1]), .A2(aluBypass), .A3(n_0_683), .ZN(n_0_622) + ); + NAND2_X1_LVT i_0_653( + .A1(n_0_684), .A2(n_0_622), .ZN(n_0_621) + ); + INV_X1_LVT i_0_734( + .A(op2[0]), .ZN(n_0_701) + ); + INV_X1_LVT i_0_756( + .A(op2[3]), .ZN(n_0_723) + ); + NOR2_X1_LVT i_0_650( + .A1(op2[4]), .A2(n_0_723), .ZN(n_0_618) + ); + INV_X1_LVT i_0_649( + .A(n_0_618), .ZN(n_0_617) + ); + NOR2_X1_LVT i_0_648( + .A1(op2[4]), .A2(op2[3]), .ZN(n_0_616) + ); + INV_X1_LVT i_0_647( + .A(n_0_616), .ZN(n_0_615) + ); + INV_X1_LVT i_0_771( + .A(op2[4]), .ZN(n_0_738) + ); + INV_X1_LVT i_0_767( + .A(op1[15]), .ZN(n_0_734) + ); + INV_X1_LVT i_0_746( + .A(op1[7]), .ZN(n_0_713) + ); + AOI22_X1_LVT i_0_651( + .A1(n_0_734), .A2(n_0_723), .B1(op2[3]), .B2(n_0_713), .ZN(n_0_619) + ); + OAI222_X1_LVT i_0_646( + .A1(op1[23]), .A2(n_0_617), .B1(op1[31]), .B2(n_0_615), .C1(n_0_738), .C2(n_0_619), + .ZN(n_0_614) + ); + NOR2_X1_LVT i_0_645( + .A1(op2[2]), .A2(n_0_614), .ZN(n_0_613) + ); + NOR2_X1_LVT i_0_696( + .A1(op1[3]), .A2(n_0_723), .ZN(n_0_663) + ); + INV_X1_LVT i_0_739( + .A(op1[11]), .ZN(n_0_706) + ); + AOI21_X1_LVT i_0_644( + .A(n_0_663), .B1(n_0_723), .B2(n_0_706), .ZN(n_0_612) + ); + AOI22_X1_LVT i_0_643( + .A1(op2[4]), .A2(n_0_612), .B1(op1[27]), .B2(n_0_616), .ZN(n_0_611) + ); + INV_X1_LVT i_0_722( + .A(op1[19]), .ZN(n_0_689) + ); + OAI21_X1_LVT i_0_642( + .A(n_0_611), .B1(n_0_689), .B2(n_0_617), .ZN(n_0_610) + ); + AOI21_X1_LVT i_0_641( + .A(n_0_613), .B1(op2[2]), .B2(n_0_610), .ZN(n_0_609) + ); + INV_X1_LVT i_0_761( + .A(op2[1]), .ZN(n_0_728) + ); + OAI22_X1_LVT i_0_640( + .A1(op2[4]), .A2(op1[21]), .B1(n_0_738), .B2(op1[5]), .ZN(n_0_608) + ); + NAND2_X1_LVT i_0_639( + .A1(op2[3]), .A2(n_0_608), .ZN(n_0_607) + ); + INV_X1_LVT i_0_747( + .A(op1[13]), .ZN(n_0_714) + ); + NOR2_X1_LVT i_0_638( + .A1(n_0_738), .A2(op2[3]), .ZN(n_0_606) + ); + INV_X1_LVT i_0_743( + .A(op1[29]), .ZN(n_0_710) + ); + AOI221_X1_LVT i_0_636( + .A(op2[2]), .B1(n_0_714), .B2(n_0_606), .C1(n_0_710), .C2(n_0_616), .ZN(n_0_604) + ); + OAI22_X1_LVT i_0_635( + .A1(op2[4]), .A2(op1[17]), .B1(n_0_738), .B2(op1[1]), .ZN(n_0_603) + ); + INV_X1_LVT i_0_755( + .A(op1[9]), .ZN(n_0_722) + ); + INV_X1_LVT i_0_637( + .A(n_0_606), .ZN(n_0_605) + ); + INV_X1_LVT i_0_732( + .A(op1[25]), .ZN(n_0_699) + ); + OAI222_X1_LVT i_0_634( + .A1(n_0_723), .A2(n_0_603), .B1(n_0_722), .B2(n_0_605), .C1(n_0_699), .C2(n_0_615), + .ZN(n_0_602) + ); + AOI22_X1_LVT i_0_633( + .A1(n_0_607), .A2(n_0_604), .B1(op2[2]), .B2(n_0_602), .ZN(n_0_601) + ); + OAI221_X1_LVT i_0_616( + .A(n_0_701), .B1(op2[1]), .B2(n_0_609), .C1(n_0_728), .C2(n_0_601), .ZN(n_0_584) + ); + INV_X1_LVT i_0_729( + .A(op1[12]), .ZN(n_0_696) + ); + INV_X1_LVT i_0_731( + .A(op1[28]), .ZN(n_0_698) + ); + AOI22_X1_LVT i_0_622( + .A1(n_0_696), .A2(n_0_606), .B1(n_0_698), .B2(n_0_616), .ZN(n_0_590) + ); + INV_X1_LVT i_0_726( + .A(op2[2]), .ZN(n_0_693) + ); + NOR2_X1_LVT i_0_701( + .A1(n_0_738), .A2(op1[4]), .ZN(n_0_668) + ); + INV_X1_LVT i_0_760( + .A(op1[20]), .ZN(n_0_727) + ); + AOI21_X1_LVT i_0_623( + .A(n_0_668), .B1(n_0_738), .B2(n_0_727), .ZN(n_0_591) + ); + OAI211_X1_LVT i_0_621( + .A(n_0_590), .B(n_0_693), .C1(n_0_723), .C2(n_0_591), .ZN(n_0_589) + ); + OAI22_X1_LVT i_0_626( + .A1(op1[16]), .A2(op2[4]), .B1(n_0_738), .B2(op1[0]), .ZN(n_0_594) + ); + INV_X1_LVT i_0_769( + .A(op1[24]), .ZN(n_0_736) + ); + OAI22_X1_LVT i_0_625( + .A1(n_0_723), .A2(n_0_594), .B1(n_0_736), .B2(n_0_615), .ZN(n_0_593) + ); + AOI21_X1_LVT i_0_624( + .A(n_0_593), .B1(op1[8]), .B2(n_0_606), .ZN(n_0_592) + ); + OAI21_X1_LVT i_0_620( + .A(n_0_589), .B1(n_0_693), .B2(n_0_592), .ZN(n_0_588) + ); + INV_X1_LVT i_0_737( + .A(op1[6]), .ZN(n_0_704) + ); + INV_X1_LVT i_0_720( + .A(op1[22]), .ZN(n_0_687) + ); + OAI22_X1_LVT i_0_632( + .A1(n_0_738), .A2(n_0_704), .B1(op2[4]), .B2(n_0_687), .ZN(n_0_600) + ); + OAI221_X1_LVT i_0_631( + .A(n_0_693), .B1(n_0_723), .B2(n_0_600), .C1(op1[14]), .C2(n_0_605), .ZN(n_0_599) + ); + INV_X1_LVT i_0_750( + .A(op1[30]), .ZN(n_0_717) + ); + AOI21_X1_LVT i_0_630( + .A(n_0_599), .B1(n_0_717), .B2(n_0_616), .ZN(n_0_598) + ); + INV_X1_LVT i_0_738( + .A(op1[18]), .ZN(n_0_705) + ); + NOR2_X1_LVT i_0_628( + .A1(n_0_705), .A2(n_0_617), .ZN(n_0_596) + ); + INV_X1_LVT i_0_727( + .A(op1[2]), .ZN(n_0_694) + ); + INV_X1_LVT i_0_766( + .A(op1[10]), .ZN(n_0_733) + ); + OAI22_X1_LVT i_0_629( + .A1(n_0_723), .A2(n_0_694), .B1(n_0_733), .B2(op2[3]), .ZN(n_0_597) + ); + AOI221_X1_LVT i_0_627( + .A(n_0_596), .B1(op1[26]), .B2(n_0_616), .C1(op2[4]), .C2(n_0_597), .ZN(n_0_595) + ); + OAI21_X1_LVT i_0_619( + .A(n_0_728), .B1(n_0_693), .B2(n_0_595), .ZN(n_0_587) + ); + OAI22_X1_LVT i_0_618( + .A1(n_0_728), .A2(n_0_588), .B1(n_0_598), .B2(n_0_587), .ZN(n_0_586) + ); + INV_X1_LVT i_0_617( + .A(n_0_586), .ZN(n_0_585) + ); + OAI21_X1_LVT i_0_615( + .A(n_0_584), .B1(n_0_701), .B2(n_0_585), .ZN(n_0_583) + ); + NOR2_X1_LVT i_0_607( + .A1(op2[4]), .A2(op2[2]), .ZN(n_0_575) + ); + NAND2_X1_LVT i_0_606( + .A1(n_0_723), .A2(n_0_575), .ZN(n_0_574) + ); + INV_X1_LVT i_0_605( + .A(n_0_574), .ZN(n_0_573) + ); + NAND2_X1_LVT i_0_604( + .A1(n_0_728), .A2(n_0_573), .ZN(n_0_572) + ); + NAND2_X1_LVT i_0_611( + .A1(aluOp[2]), .A2(n_0_622), .ZN(n_0_579) + ); + INV_X1_LVT i_0_610( + .A(n_0_579), .ZN(n_0_578) + ); + NAND2_X1_LVT i_0_594( + .A1(n_0_701), .A2(n_0_578), .ZN(n_0_562) + ); + NOR3_X1_LVT i_0_592( + .A1(aluNegAr), .A2(n_0_572), .A3(n_0_562), .ZN(n_0_560) + ); + INV_X1_LVT i_0_600( + .A(n_0_569), .ZN(n_0_568) + ); + OAI21_X1_LVT i_0_595( + .A(n_0_568), .B1(aluOp[1]), .B2(n_0_570), .ZN(n_0_563) + ); + AOI211_X1_LVT i_0_591( + .A(aluBypass), .B(n_0_560), .C1(n_0_692), .C2(n_0_563), .ZN(n_0_559) + ); + OAI221_X1_LVT i_0_586( + .A(n_0_555), .B1(n_0_621), .B2(n_0_583), .C1(n_0_691), .C2(n_0_559), .ZN(result[31]) + ); + NAND2_X1_LVT i_10_150( + .A1(n_10_118), .A2(n_10_119), .ZN(n_10_120) + ); + XNOR2_X1_LVT i_10_151( + .A(n_10_116), .B(n_10_120), .ZN(n_62) + ); + AOI22_X1_LVT i_0_580( + .A1(n_62), .A2(n_0_580), .B1(n_30), .B2(n_0_581), .ZN(n_0_549) + ); + NAND2_X1_LVT i_0_576( + .A1(aluNegAr), .A2(n_0_578), .ZN(n_0_545) + ); + INV_X1_LVT i_0_603( + .A(n_0_572), .ZN(n_0_571) + ); + NOR3_X1_LVT i_0_574( + .A1(n_0_691), .A2(n_0_545), .A3(n_0_571), .ZN(n_0_543) + ); + AOI22_X1_LVT i_0_573( + .A1(n_0_717), .A2(n_0_565), .B1(op1[30]), .B2(n_0_566), .ZN(n_0_542) + ); + AOI21_X1_LVT i_0_572( + .A(n_0_543), .B1(op2[30]), .B2(n_0_542), .ZN(n_0_541) + ); + NAND2_X1_LVT i_0_579( + .A1(op2[0]), .A2(n_0_578), .ZN(n_0_548) + ); + NAND2_X1_LVT i_0_577( + .A1(op1[31]), .A2(n_0_571), .ZN(n_0_546) + ); + OAI211_X1_LVT i_0_571( + .A(n_0_549), .B(n_0_541), .C1(n_0_548), .C2(n_0_546), .ZN(n_0_540) + ); + OAI221_X1_LVT i_0_581( + .A(n_0_681), .B1(op2[30]), .B2(n_0_568), .C1(n_0_572), .C2(n_0_562), .ZN(n_0_550) + ); + AOI21_X1_LVT i_0_570( + .A(n_0_540), .B1(op1[30]), .B2(n_0_550), .ZN(n_0_539) + ); + INV_X1_LVT i_0_752( + .A(op1[23]), .ZN(n_0_719) + ); + OAI222_X1_LVT i_0_585( + .A1(n_0_713), .A2(n_0_605), .B1(n_0_719), .B2(n_0_615), .C1(n_0_734), .C2(n_0_617), + .ZN(n_0_554) + ); + AOI22_X1_LVT i_0_584( + .A1(op2[2]), .A2(n_0_554), .B1(n_0_693), .B2(n_0_610), .ZN(n_0_553) + ); + OAI22_X1_LVT i_0_583( + .A1(n_0_728), .A2(n_0_553), .B1(op2[1]), .B2(n_0_601), .ZN(n_0_552) + ); + AOI22_X1_LVT i_0_582( + .A1(n_0_701), .A2(n_0_585), .B1(op2[0]), .B2(n_0_552), .ZN(n_0_551) + ); + OAI21_X1_LVT i_0_569( + .A(n_0_539), .B1(n_0_621), .B2(n_0_551), .ZN(result[30]) + ); + INV_X1_LVT i_0_578( + .A(n_0_548), .ZN(n_0_547) + ); + NAND3_X1_LVT i_0_562( + .A1(op1[30]), .A2(n_0_571), .A3(n_0_547), .ZN(n_0_532) + ); + XNOR2_X1_LVT i_10_144( + .A(n_10_113), .B(n_10_114), .ZN(n_61) + ); + NAND2_X1_LVT i_0_558( + .A1(n_61), .A2(n_0_580), .ZN(n_0_528) + ); + OAI21_X1_LVT i_0_557( + .A(n_0_681), .B1(op2[29]), .B2(n_0_568), .ZN(n_0_527) + ); + NAND2_X1_LVT i_0_556( + .A1(op1[29]), .A2(n_0_566), .ZN(n_0_526) + ); + AOI22_X1_LVT i_0_555( + .A1(op1[29]), .A2(n_0_527), .B1(op2[29]), .B2(n_0_526), .ZN(n_0_525) + ); + AOI21_X1_LVT i_0_554( + .A(n_0_525), .B1(n_0_710), .B2(n_0_565), .ZN(n_0_524) + ); + AOI211_X1_LVT i_0_553( + .A(n_0_543), .B(n_0_524), .C1(n_29), .C2(n_0_581), .ZN(n_0_523) + ); + AND3_X1_LVT i_0_552( + .A1(n_0_532), .A2(n_0_528), .A3(n_0_523), .ZN(n_0_522) + ); + INV_X1_LVT i_0_652( + .A(n_0_621), .ZN(n_0_620) + ); + NAND2_X1_LVT i_0_565( + .A1(n_0_728), .A2(n_0_588), .ZN(n_0_535) + ); + AOI22_X1_LVT i_0_568( + .A1(n_0_723), .A2(n_0_600), .B1(op1[14]), .B2(n_0_618), .ZN(n_0_538) + ); + AOI22_X1_LVT i_0_567( + .A1(n_0_693), .A2(n_0_595), .B1(op2[2]), .B2(n_0_538), .ZN(n_0_537) + ); + INV_X1_LVT i_0_566( + .A(n_0_537), .ZN(n_0_536) + ); + OAI21_X1_LVT i_0_564( + .A(n_0_535), .B1(n_0_728), .B2(n_0_536), .ZN(n_0_534) + ); + OAI221_X1_LVT i_0_563( + .A(n_0_620), .B1(op2[0]), .B2(n_0_552), .C1(n_0_701), .C2(n_0_534), .ZN(n_0_533) + ); + NAND2_X1_LVT i_0_561( + .A1(op2[1]), .A2(n_0_573), .ZN(n_0_531) + ); + INV_X1_LVT i_0_560( + .A(n_0_531), .ZN(n_0_530) + ); + AOI22_X1_LVT i_0_559( + .A1(op1[31]), .A2(n_0_530), .B1(op1[29]), .B2(n_0_571), .ZN(n_0_529) + ); + OAI211_X1_LVT i_0_551( + .A(n_0_522), .B(n_0_533), .C1(n_0_562), .C2(n_0_529), .ZN(result[29]) + ); + INV_X1_LVT i_0_733( + .A(op2[28]), .ZN(n_0_700) + ); + AOI221_X1_LVT i_0_546( + .A(n_0_700), .B1(op1[28]), .B2(n_0_566), .C1(n_0_698), .C2(n_0_565), .ZN(n_0_517) + ); + OAI21_X1_LVT i_0_543( + .A(n_0_681), .B1(op2[28]), .B2(n_0_568), .ZN(n_0_514) + ); + AOI22_X1_LVT i_0_542( + .A1(n_28), .A2(n_0_581), .B1(op1[28]), .B2(n_0_514), .ZN(n_0_513) + ); + XNOR2_X1_LVT i_10_140( + .A(n_10_110), .B(n_10_111), .ZN(n_60) + ); + NAND2_X1_LVT i_0_544( + .A1(n_60), .A2(n_0_580), .ZN(n_0_515) + ); + NAND2_X1_LVT i_0_545( + .A1(op1[31]), .A2(n_0_574), .ZN(n_0_516) + ); + OAI211_X1_LVT i_0_541( + .A(n_0_513), .B(n_0_515), .C1(n_0_545), .C2(n_0_516), .ZN(n_0_512) + ); + AOI22_X1_LVT i_0_540( + .A1(op1[30]), .A2(n_0_530), .B1(op1[28]), .B2(n_0_571), .ZN(n_0_511) + ); + OAI22_X1_LVT i_0_539( + .A1(n_0_562), .A2(n_0_511), .B1(n_0_548), .B2(n_0_529), .ZN(n_0_510) + ); + NOR3_X1_LVT i_0_538( + .A1(n_0_517), .A2(n_0_512), .A3(n_0_510), .ZN(n_0_509) + ); + OAI22_X1_LVT i_0_550( + .A1(n_0_714), .A2(n_0_617), .B1(op2[3]), .B2(n_0_608), .ZN(n_0_521) + ); + OAI22_X1_LVT i_0_549( + .A1(op2[2]), .A2(n_0_602), .B1(n_0_693), .B2(n_0_521), .ZN(n_0_520) + ); + AOI22_X1_LVT i_0_548( + .A1(op2[1]), .A2(n_0_520), .B1(n_0_728), .B2(n_0_553), .ZN(n_0_519) + ); + OAI22_X1_LVT i_0_547( + .A1(op2[0]), .A2(n_0_534), .B1(n_0_701), .B2(n_0_519), .ZN(n_0_518) + ); + OAI21_X1_LVT i_0_537( + .A(n_0_509), .B1(n_0_621), .B2(n_0_518), .ZN(result[28]) + ); + XNOR2_X1_LVT i_10_136( + .A(n_10_107), .B(n_10_108), .ZN(n_59) + ); + AOI22_X1_LVT i_0_517( + .A1(n_27), .A2(n_0_581), .B1(n_59), .B2(n_0_580), .ZN(n_0_489) + ); + INV_X1_LVT i_0_721( + .A(op1[27]), .ZN(n_0_688) + ); + OAI21_X1_LVT i_0_516( + .A(n_0_681), .B1(op2[27]), .B2(n_0_568), .ZN(n_0_488) + ); + INV_X1_LVT i_0_515( + .A(n_0_488), .ZN(n_0_487) + ); + OAI221_X1_LVT i_0_514( + .A(n_0_489), .B1(n_0_545), .B2(n_0_516), .C1(n_0_688), .C2(n_0_487), .ZN(n_0_486) + ); + OAI21_X1_LVT i_0_530( + .A(op2[1]), .B1(n_0_710), .B2(n_0_574), .ZN(n_0_502) + ); + OAI21_X1_LVT i_0_529( + .A(n_0_728), .B1(n_0_688), .B2(n_0_574), .ZN(n_0_501) + ); + NAND2_X1_LVT i_0_528( + .A1(n_0_502), .A2(n_0_501), .ZN(n_0_500) + ); + AOI21_X1_LVT i_0_527( + .A(n_0_545), .B1(n_0_701), .B2(n_0_500), .ZN(n_0_499) + ); + NAND2_X1_LVT i_0_609( + .A1(n_0_682), .A2(n_0_578), .ZN(n_0_577) + ); + NOR2_X1_LVT i_0_526( + .A1(op2[4]), .A2(n_0_693), .ZN(n_0_498) + ); + NAND2_X1_LVT i_0_525( + .A1(n_0_723), .A2(n_0_498), .ZN(n_0_497) + ); + OAI22_X1_LVT i_0_523( + .A1(n_0_688), .A2(n_0_574), .B1(n_0_691), .B2(n_0_497), .ZN(n_0_495) + ); + OAI21_X1_LVT i_0_522( + .A(n_0_502), .B1(op2[1]), .B2(n_0_495), .ZN(n_0_494) + ); + AOI21_X1_LVT i_0_521( + .A(n_0_577), .B1(n_0_701), .B2(n_0_494), .ZN(n_0_493) + ); + NOR2_X1_LVT i_0_520( + .A1(n_0_499), .A2(n_0_493), .ZN(n_0_492) + ); + AOI21_X1_LVT i_0_519( + .A(n_0_492), .B1(op2[0]), .B2(n_0_511), .ZN(n_0_491) + ); + AOI22_X1_LVT i_0_518( + .A1(n_0_688), .A2(n_0_565), .B1(op1[27]), .B2(n_0_566), .ZN(n_0_490) + ); + AOI211_X1_LVT i_0_513( + .A(n_0_486), .B(n_0_491), .C1(op2[27]), .C2(n_0_490), .ZN(n_0_485) + ); + NOR3_X1_LVT i_0_536( + .A1(op2[4]), .A2(n_0_696), .A3(n_0_723), .ZN(n_0_508) + ); + AOI21_X1_LVT i_0_535( + .A(n_0_508), .B1(n_0_723), .B2(n_0_591), .ZN(n_0_507) + ); + OAI22_X1_LVT i_0_534( + .A1(op2[2]), .A2(n_0_592), .B1(n_0_693), .B2(n_0_507), .ZN(n_0_506) + ); + NOR2_X1_LVT i_0_533( + .A1(n_0_728), .A2(n_0_506), .ZN(n_0_505) + ); + AOI21_X1_LVT i_0_532( + .A(n_0_505), .B1(n_0_728), .B2(n_0_536), .ZN(n_0_504) + ); + OAI22_X1_LVT i_0_531( + .A1(n_0_701), .A2(n_0_504), .B1(op2[0]), .B2(n_0_519), .ZN(n_0_503) + ); + OAI21_X1_LVT i_0_512( + .A(n_0_485), .B1(n_0_621), .B2(n_0_503), .ZN(result[27]) + ); + OAI21_X1_LVT i_0_500( + .A(n_0_681), .B1(op2[26]), .B2(n_0_568), .ZN(n_0_473) + ); + NAND2_X1_LVT i_0_499( + .A1(op1[26]), .A2(n_0_473), .ZN(n_0_472) + ); + XNOR2_X1_LVT i_10_133( + .A(n_10_103), .B(n_10_106), .ZN(n_58) + ); + AOI22_X1_LVT i_0_498( + .A1(n_58), .A2(n_0_580), .B1(n_26), .B2(n_0_581), .ZN(n_0_471) + ); + INV_X1_LVT i_0_744( + .A(op1[26]), .ZN(n_0_711) + ); + OAI221_X1_LVT i_0_501( + .A(op2[26]), .B1(op1[26]), .B2(n_0_564), .C1(n_0_711), .C2(n_0_567), .ZN(n_0_474) + ); + NAND3_X1_LVT i_0_497( + .A1(n_0_472), .A2(n_0_471), .A3(n_0_474), .ZN(n_0_470) + ); + INV_X1_LVT i_0_524( + .A(n_0_497), .ZN(n_0_496) + ); + AOI22_X1_LVT i_0_505( + .A1(op1[30]), .A2(n_0_496), .B1(op1[26]), .B2(n_0_573), .ZN(n_0_478) + ); + NOR2_X1_LVT i_0_504( + .A1(op2[1]), .A2(n_0_478), .ZN(n_0_477) + ); + AOI21_X1_LVT i_0_503( + .A(n_0_477), .B1(op1[28]), .B2(n_0_530), .ZN(n_0_476) + ); + NAND2_X1_LVT i_0_502( + .A1(n_0_701), .A2(n_0_476), .ZN(n_0_475) + ); + AOI21_X1_LVT i_0_489( + .A(n_0_577), .B1(op2[0]), .B2(n_0_494), .ZN(n_0_462) + ); + AOI21_X1_LVT i_0_488( + .A(n_0_470), .B1(n_0_475), .B2(n_0_462), .ZN(n_0_461) + ); + AOI21_X1_LVT i_0_511( + .A(n_0_616), .B1(n_0_738), .B2(n_0_706), .ZN(n_0_484) + ); + AOI21_X1_LVT i_0_510( + .A(n_0_484), .B1(n_0_723), .B2(op1[19]), .ZN(n_0_483) + ); + INV_X1_LVT i_0_757( + .A(op1[3]), .ZN(n_0_724) + ); + NOR2_X1_LVT i_0_687( + .A1(n_0_724), .A2(op2[3]), .ZN(n_0_654) + ); + INV_X1_LVT i_0_686( + .A(n_0_654), .ZN(n_0_653) + ); + AOI21_X1_LVT i_0_509( + .A(n_0_483), .B1(op2[4]), .B2(n_0_653), .ZN(n_0_482) + ); + AOI22_X1_LVT i_0_508( + .A1(n_0_693), .A2(n_0_554), .B1(op2[2]), .B2(n_0_482), .ZN(n_0_481) + ); + OAI22_X1_LVT i_0_507( + .A1(n_0_728), .A2(n_0_481), .B1(op2[1]), .B2(n_0_520), .ZN(n_0_480) + ); + AOI22_X1_LVT i_0_506( + .A1(op2[0]), .A2(n_0_480), .B1(n_0_701), .B2(n_0_504), .ZN(n_0_479) + ); + NAND3_X1_LVT i_0_491( + .A1(op2[0]), .A2(n_0_516), .A3(n_0_500), .ZN(n_0_464) + ); + NAND2_X1_LVT i_0_494( + .A1(op1[31]), .A2(n_0_615), .ZN(n_0_467) + ); + OAI21_X1_LVT i_0_492( + .A(n_0_467), .B1(n_0_728), .B2(n_0_516), .ZN(n_0_465) + ); + OAI21_X1_LVT i_0_490( + .A(n_0_464), .B1(n_0_475), .B2(n_0_465), .ZN(n_0_463) + ); + OAI221_X1_LVT i_0_487( + .A(n_0_461), .B1(n_0_621), .B2(n_0_479), .C1(n_0_545), .C2(n_0_463), .ZN(result[26]) + ); + INV_X1_LVT i_10_126( + .A(n_10_100), .ZN(n_10_101) + ); + NOR2_X1_LVT i_10_127( + .A1(n_10_99), .A2(n_10_101), .ZN(n_10_102) + ); + XNOR2_X1_LVT i_10_128( + .A(n_10_97), .B(n_10_102), .ZN(n_57) + ); + AOI22_X1_LVT i_0_479( + .A1(n_57), .A2(n_0_580), .B1(n_25), .B2(n_0_581), .ZN(n_0_453) + ); + INV_X1_LVT i_0_730( + .A(op2[25]), .ZN(n_0_697) + ); + AOI21_X1_LVT i_0_478( + .A(aluBypass), .B1(n_0_697), .B2(n_0_569), .ZN(n_0_452) + ); + AOI22_X1_LVT i_0_480( + .A1(op1[25]), .A2(n_0_567), .B1(n_0_699), .B2(n_0_564), .ZN(n_0_454) + ); + OAI221_X1_LVT i_0_477( + .A(n_0_453), .B1(n_0_699), .B2(n_0_452), .C1(n_0_697), .C2(n_0_454), .ZN(n_0_451) + ); + INV_X1_LVT i_0_575( + .A(n_0_545), .ZN(n_0_544) + ); + AOI21_X1_LVT i_0_476( + .A(n_0_451), .B1(n_0_544), .B2(n_0_465), .ZN(n_0_450) + ); + AOI22_X1_LVT i_0_475( + .A1(op1[29]), .A2(n_0_496), .B1(op1[25]), .B2(n_0_573), .ZN(n_0_449) + ); + NAND2_X1_LVT i_0_474( + .A1(n_0_728), .A2(n_0_449), .ZN(n_0_448) + ); + OAI21_X1_LVT i_0_473( + .A(n_0_448), .B1(n_0_728), .B2(n_0_495), .ZN(n_0_447) + ); + OAI22_X1_LVT i_0_472( + .A1(n_0_548), .A2(n_0_476), .B1(n_0_562), .B2(n_0_447), .ZN(n_0_446) + ); + INV_X1_LVT i_0_471( + .A(n_0_446), .ZN(n_0_445) + ); + OAI222_X1_LVT i_0_486( + .A1(n_0_733), .A2(n_0_617), .B1(n_0_694), .B2(n_0_605), .C1(n_0_705), .C2(n_0_615), + .ZN(n_0_460) + ); + NOR2_X1_LVT i_0_485( + .A1(n_0_693), .A2(n_0_460), .ZN(n_0_459) + ); + AOI21_X1_LVT i_0_484( + .A(n_0_459), .B1(n_0_693), .B2(n_0_538), .ZN(n_0_458) + ); + OAI22_X1_LVT i_0_483( + .A1(n_0_728), .A2(n_0_458), .B1(op2[1]), .B2(n_0_506), .ZN(n_0_457) + ); + INV_X1_LVT i_0_482( + .A(n_0_457), .ZN(n_0_456) + ); + OAI221_X1_LVT i_0_481( + .A(n_0_620), .B1(n_0_701), .B2(n_0_456), .C1(op2[0]), .C2(n_0_480), .ZN(n_0_455) + ); + NAND3_X1_LVT i_0_470( + .A1(n_0_450), .A2(n_0_445), .A3(n_0_455), .ZN(result[25]) + ); + INV_X1_LVT i_0_493( + .A(n_0_467), .ZN(n_0_466) + ); + OAI211_X1_LVT i_0_455( + .A(n_0_544), .B(n_0_465), .C1(op2[0]), .C2(n_0_466), .ZN(n_0_430) + ); + OAI21_X1_LVT i_0_462( + .A(n_0_681), .B1(op2[24]), .B2(n_0_568), .ZN(n_0_437) + ); + XNOR2_X1_LVT i_10_120( + .A(n_10_94), .B(n_10_95), .ZN(n_56) + ); + AOI222_X1_LVT i_0_461( + .A1(op1[24]), .A2(n_0_437), .B1(n_56), .B2(n_0_580), .C1(n_24), .C2(n_0_581), + .ZN(n_0_436) + ); + INV_X1_LVT i_0_460( + .A(n_0_436), .ZN(n_0_435) + ); + AOI22_X1_LVT i_0_458( + .A1(op1[24]), .A2(n_0_573), .B1(op1[28]), .B2(n_0_496), .ZN(n_0_433) + ); + OAI22_X1_LVT i_0_457( + .A1(op2[1]), .A2(n_0_433), .B1(n_0_728), .B2(n_0_478), .ZN(n_0_432) + ); + INV_X1_LVT i_0_456( + .A(n_0_432), .ZN(n_0_431) + ); + OAI22_X1_LVT i_0_454( + .A1(n_0_562), .A2(n_0_431), .B1(n_0_548), .B2(n_0_447), .ZN(n_0_429) + ); + AOI22_X1_LVT i_0_459( + .A1(n_0_736), .A2(n_0_565), .B1(op1[24]), .B2(n_0_566), .ZN(n_0_434) + ); + AOI211_X1_LVT i_0_453( + .A(n_0_435), .B(n_0_429), .C1(op2[24]), .C2(n_0_434), .ZN(n_0_428) + ); + NAND2_X1_LVT i_0_467( + .A1(n_0_693), .A2(n_0_521), .ZN(n_0_442) + ); + NOR2_X1_LVT i_0_469( + .A1(op2[3]), .A2(n_0_603), .ZN(n_0_444) + ); + AOI21_X1_LVT i_0_468( + .A(n_0_444), .B1(op1[9]), .B2(n_0_618), .ZN(n_0_443) + ); + OAI21_X1_LVT i_0_466( + .A(n_0_442), .B1(n_0_693), .B2(n_0_443), .ZN(n_0_441) + ); + NAND2_X1_LVT i_0_465( + .A1(op2[1]), .A2(n_0_441), .ZN(n_0_440) + ); + OAI21_X1_LVT i_0_464( + .A(n_0_440), .B1(op2[1]), .B2(n_0_481), .ZN(n_0_439) + ); + OAI221_X1_LVT i_0_463( + .A(n_0_620), .B1(op2[0]), .B2(n_0_456), .C1(n_0_701), .C2(n_0_439), .ZN(n_0_438) + ); + NAND3_X1_LVT i_0_452( + .A1(n_0_430), .A2(n_0_428), .A3(n_0_438), .ZN(result[24]) + ); + INV_X1_LVT i_0_751( + .A(op2[23]), .ZN(n_0_718) + ); + AOI221_X1_LVT i_0_440( + .A(n_0_718), .B1(op1[23]), .B2(n_0_566), .C1(n_0_719), .C2(n_0_565), .ZN(n_0_416) + ); + INV_X1_LVT i_10_115( + .A(n_10_91), .ZN(n_10_92) + ); + NOR2_X1_LVT i_10_116( + .A1(n_10_90), .A2(n_10_92), .ZN(n_10_93) + ); + XNOR2_X1_LVT i_10_117( + .A(n_10_88), .B(n_10_93), .ZN(n_55) + ); + AOI222_X1_LVT i_0_438( + .A1(n_23), .A2(n_0_581), .B1(n_0_544), .B2(n_0_466), .C1(n_55), .C2(n_0_580), + .ZN(n_0_414) + ); + OAI21_X1_LVT i_0_437( + .A(n_0_414), .B1(n_0_548), .B2(n_0_431), .ZN(n_0_413) + ); + OAI21_X1_LVT i_0_439( + .A(n_0_681), .B1(op2[23]), .B2(n_0_568), .ZN(n_0_415) + ); + AOI211_X1_LVT i_0_436( + .A(n_0_416), .B(n_0_413), .C1(op1[23]), .C2(n_0_415), .ZN(n_0_412) + ); + AOI22_X1_LVT i_0_444( + .A1(n_0_723), .A2(n_0_719), .B1(op2[3]), .B2(n_0_691), .ZN(n_0_420) + ); + AOI22_X1_LVT i_0_443( + .A1(n_0_575), .A2(n_0_420), .B1(op1[27]), .B2(n_0_496), .ZN(n_0_419) + ); + AOI22_X1_LVT i_0_442( + .A1(op2[1]), .A2(n_0_449), .B1(n_0_728), .B2(n_0_419), .ZN(n_0_418) + ); + INV_X1_LVT i_0_441( + .A(n_0_418), .ZN(n_0_417) + ); + NAND2_X1_LVT i_0_447( + .A1(n_0_728), .A2(n_0_458), .ZN(n_0_423) + ); + NOR2_X1_LVT i_0_451( + .A1(op2[3]), .A2(n_0_594), .ZN(n_0_427) + ); + AOI21_X1_LVT i_0_450( + .A(n_0_427), .B1(op1[8]), .B2(n_0_618), .ZN(n_0_426) + ); + OAI22_X1_LVT i_0_449( + .A1(n_0_693), .A2(n_0_426), .B1(op2[2]), .B2(n_0_507), .ZN(n_0_425) + ); + INV_X1_LVT i_0_448( + .A(n_0_425), .ZN(n_0_424) + ); + OAI21_X1_LVT i_0_446( + .A(n_0_423), .B1(n_0_728), .B2(n_0_424), .ZN(n_0_422) + ); + AOI22_X1_LVT i_0_445( + .A1(op2[0]), .A2(n_0_422), .B1(n_0_701), .B2(n_0_439), .ZN(n_0_421) + ); + OAI221_X1_LVT i_0_435( + .A(n_0_412), .B1(n_0_562), .B2(n_0_417), .C1(n_0_621), .C2(n_0_421), .ZN(result[23]) + ); + XNOR2_X1_LVT i_10_109( + .A(n_10_85), .B(n_10_86), .ZN(n_54) + ); + AOI22_X1_LVT i_0_419( + .A1(n_54), .A2(n_0_580), .B1(n_22), .B2(n_0_581), .ZN(n_0_396) + ); + INV_X1_LVT i_0_719( + .A(op2[22]), .ZN(n_0_686) + ); + AOI21_X1_LVT i_0_420( + .A(aluBypass), .B1(n_0_686), .B2(n_0_569), .ZN(n_0_397) + ); + OAI21_X1_LVT i_0_418( + .A(n_0_396), .B1(n_0_687), .B2(n_0_397), .ZN(n_0_395) + ); + AOI22_X1_LVT i_0_421( + .A1(op1[22]), .A2(n_0_566), .B1(n_0_687), .B2(n_0_565), .ZN(n_0_398) + ); + AOI21_X1_LVT i_0_417( + .A(n_0_395), .B1(op2[22]), .B2(n_0_398), .ZN(n_0_394) + ); + NAND2_X1_LVT i_0_432( + .A1(n_0_728), .A2(n_0_441), .ZN(n_0_409) + ); + AND2_X1_LVT i_0_434( + .A1(n_0_738), .A2(n_0_619), .ZN(n_0_411) + ); + AOI22_X1_LVT i_0_433( + .A1(n_0_693), .A2(n_0_482), .B1(op2[2]), .B2(n_0_411), .ZN(n_0_410) + ); + OAI21_X1_LVT i_0_431( + .A(n_0_409), .B1(n_0_728), .B2(n_0_410), .ZN(n_0_408) + ); + OAI22_X1_LVT i_0_430( + .A1(n_0_701), .A2(n_0_408), .B1(op2[0]), .B2(n_0_422), .ZN(n_0_407) + ); + AOI22_X1_LVT i_0_429( + .A1(n_0_723), .A2(n_0_687), .B1(op2[3]), .B2(n_0_717), .ZN(n_0_406) + ); + AOI22_X1_LVT i_0_428( + .A1(n_0_575), .A2(n_0_406), .B1(op1[26]), .B2(n_0_496), .ZN(n_0_405) + ); + AND2_X1_LVT i_0_427( + .A1(n_0_728), .A2(n_0_405), .ZN(n_0_404) + ); + AOI21_X1_LVT i_0_426( + .A(n_0_404), .B1(op2[1]), .B2(n_0_433), .ZN(n_0_403) + ); + INV_X1_LVT i_0_425( + .A(n_0_403), .ZN(n_0_402) + ); + OAI222_X1_LVT i_0_424( + .A1(n_0_545), .A2(n_0_467), .B1(n_0_701), .B2(n_0_417), .C1(op2[0]), .C2(n_0_402), + .ZN(n_0_401) + ); + NOR2_X1_LVT i_0_496( + .A1(n_0_738), .A2(n_0_691), .ZN(n_0_469) + ); + INV_X1_LVT i_0_495( + .A(n_0_469), .ZN(n_0_468) + ); + NAND3_X1_LVT i_0_423( + .A1(n_0_693), .A2(n_0_468), .A3(n_0_404), .ZN(n_0_400) + ); + OAI21_X1_LVT i_0_422( + .A(n_0_401), .B1(op2[0]), .B2(n_0_400), .ZN(n_0_399) + ); + OAI221_X1_LVT i_0_416( + .A(n_0_394), .B1(n_0_621), .B2(n_0_407), .C1(n_0_579), .C2(n_0_399), .ZN(result[22]) + ); + INV_X1_LVT i_0_759( + .A(op1[21]), .ZN(n_0_726) + ); + AOI22_X1_LVT i_0_399( + .A1(op1[21]), .A2(n_0_566), .B1(n_0_726), .B2(n_0_565), .ZN(n_0_377) + ); + NOR2_X1_LVT i_0_692( + .A1(n_0_726), .A2(op2[21]), .ZN(n_0_659) + ); + AOI222_X1_LVT i_0_398( + .A1(op2[21]), .A2(n_0_377), .B1(n_21), .B2(n_0_581), .C1(n_0_659), .C2(n_0_569), + .ZN(n_0_376) + ); + INV_X1_LVT i_0_397( + .A(n_0_376), .ZN(n_0_375) + ); + INV_X1_LVT i_10_104( + .A(n_10_82), .ZN(n_10_83) + ); + NOR2_X1_LVT i_10_105( + .A1(n_10_81), .A2(n_10_83), .ZN(n_10_84) + ); + XNOR2_X1_LVT i_10_106( + .A(n_10_79), .B(n_10_84), .ZN(n_53) + ); + AOI221_X1_LVT i_0_396( + .A(n_0_375), .B1(n_53), .B2(n_0_580), .C1(op1[21]), .C2(aluBypass), .ZN(n_0_374) + ); + INV_X1_LVT i_0_608( + .A(n_0_577), .ZN(n_0_576) + ); + NAND2_X1_LVT i_0_403( + .A1(op2[0]), .A2(n_0_402), .ZN(n_0_381) + ); + AND2_X1_LVT i_0_410( + .A1(op2[1]), .A2(n_0_419), .ZN(n_0_388) + ); + OAI22_X1_LVT i_0_408( + .A1(n_0_723), .A2(n_0_710), .B1(n_0_726), .B2(op2[3]), .ZN(n_0_386) + ); + AOI22_X1_LVT i_0_407( + .A1(n_0_575), .A2(n_0_386), .B1(op1[25]), .B2(n_0_496), .ZN(n_0_385) + ); + AOI21_X1_LVT i_0_395( + .A(n_0_388), .B1(n_0_728), .B2(n_0_385), .ZN(n_0_373) + ); + OAI211_X1_LVT i_0_394( + .A(n_0_576), .B(n_0_381), .C1(op2[0]), .C2(n_0_373), .ZN(n_0_372) + ); + AOI21_X1_LVT i_0_402( + .A(n_0_381), .B1(n_0_466), .B2(n_0_400), .ZN(n_0_380) + ); + INV_X1_LVT i_0_401( + .A(n_0_380), .ZN(n_0_379) + ); + NOR2_X1_LVT i_0_409( + .A1(n_0_575), .A2(n_0_467), .ZN(n_0_387) + ); + INV_X1_LVT i_0_406( + .A(n_0_385), .ZN(n_0_384) + ); + NOR2_X1_LVT i_0_405( + .A1(n_0_387), .A2(n_0_384), .ZN(n_0_383) + ); + AOI22_X1_LVT i_0_404( + .A1(n_0_467), .A2(n_0_388), .B1(n_0_728), .B2(n_0_383), .ZN(n_0_382) + ); + OAI211_X1_LVT i_0_400( + .A(n_0_544), .B(n_0_379), .C1(op2[0]), .C2(n_0_382), .ZN(n_0_378) + ); + AOI22_X1_LVT i_0_415( + .A1(op1[14]), .A2(n_0_616), .B1(op1[6]), .B2(n_0_618), .ZN(n_0_393) + ); + NOR2_X1_LVT i_0_414( + .A1(n_0_693), .A2(n_0_393), .ZN(n_0_392) + ); + AOI21_X1_LVT i_0_413( + .A(n_0_392), .B1(n_0_693), .B2(n_0_460), .ZN(n_0_391) + ); + OAI22_X1_LVT i_0_412( + .A1(n_0_728), .A2(n_0_391), .B1(op2[1]), .B2(n_0_424), .ZN(n_0_390) + ); + OAI221_X1_LVT i_0_411( + .A(n_0_620), .B1(op2[0]), .B2(n_0_408), .C1(n_0_701), .C2(n_0_390), .ZN(n_0_389) + ); + NAND4_X1_LVT i_0_393( + .A1(n_0_374), .A2(n_0_372), .A3(n_0_378), .A4(n_0_389), .ZN(result[21]) + ); + OAI221_X1_LVT i_0_388( + .A(op2[20]), .B1(n_0_727), .B2(n_0_567), .C1(op1[20]), .C2(n_0_564), .ZN(n_0_367) + ); + NOR2_X1_LVT i_0_691( + .A1(n_0_727), .A2(op2[20]), .ZN(n_0_658) + ); + AOI22_X1_LVT i_0_387( + .A1(op1[20]), .A2(aluBypass), .B1(n_0_658), .B2(n_0_569), .ZN(n_0_366) + ); + XNOR2_X1_LVT i_10_98( + .A(n_10_76), .B(n_10_77), .ZN(n_52) + ); + AOI22_X1_LVT i_0_386( + .A1(n_52), .A2(n_0_580), .B1(n_20), .B2(n_0_581), .ZN(n_0_365) + ); + AOI221_X1_LVT i_0_392( + .A(op2[4]), .B1(n_0_727), .B2(n_0_723), .C1(op2[3]), .C2(n_0_698), .ZN(n_0_371) + ); + AOI22_X1_LVT i_0_391( + .A1(op1[24]), .A2(n_0_496), .B1(n_0_693), .B2(n_0_371), .ZN(n_0_370) + ); + OAI22_X1_LVT i_0_390( + .A1(op2[1]), .A2(n_0_370), .B1(n_0_728), .B2(n_0_405), .ZN(n_0_369) + ); + OAI221_X1_LVT i_0_385( + .A(n_0_576), .B1(n_0_701), .B2(n_0_373), .C1(op2[0]), .C2(n_0_369), .ZN(n_0_364) + ); + AND4_X1_LVT i_0_384( + .A1(n_0_367), .A2(n_0_366), .A3(n_0_365), .A4(n_0_364), .ZN(n_0_363) + ); + AOI22_X1_LVT i_0_383( + .A1(op1[13]), .A2(n_0_616), .B1(op1[5]), .B2(n_0_618), .ZN(n_0_362) + ); + AOI22_X1_LVT i_0_382( + .A1(op2[2]), .A2(n_0_362), .B1(n_0_693), .B2(n_0_443), .ZN(n_0_361) + ); + NAND2_X1_LVT i_0_381( + .A1(op2[1]), .A2(n_0_361), .ZN(n_0_360) + ); + OAI21_X1_LVT i_0_380( + .A(n_0_360), .B1(op2[1]), .B2(n_0_410), .ZN(n_0_359) + ); + OAI221_X1_LVT i_0_379( + .A(n_0_620), .B1(n_0_701), .B2(n_0_359), .C1(op2[0]), .C2(n_0_390), .ZN(n_0_358) + ); + OR2_X1_LVT i_0_389( + .A1(n_0_387), .A2(n_0_369), .ZN(n_0_368) + ); + AOI22_X1_LVT i_0_378( + .A1(op2[0]), .A2(n_0_382), .B1(n_0_701), .B2(n_0_368), .ZN(n_0_357) + ); + OAI211_X1_LVT i_0_377( + .A(n_0_363), .B(n_0_358), .C1(n_0_545), .C2(n_0_357), .ZN(result[20]) + ); + OAI22_X1_LVT i_0_370( + .A1(op2[3]), .A2(n_0_689), .B1(n_0_723), .B2(n_0_688), .ZN(n_0_350) + ); + AND2_X1_LVT i_0_369( + .A1(n_0_738), .A2(n_0_350), .ZN(n_0_349) + ); + AOI22_X1_LVT i_0_368( + .A1(n_0_498), .A2(n_0_420), .B1(n_0_693), .B2(n_0_349), .ZN(n_0_348) + ); + AND2_X1_LVT i_0_367( + .A1(n_0_728), .A2(n_0_348), .ZN(n_0_347) + ); + AOI21_X1_LVT i_0_359( + .A(n_0_347), .B1(op2[1]), .B2(n_0_385), .ZN(n_0_339) + ); + OAI221_X1_LVT i_0_357( + .A(n_0_576), .B1(n_0_701), .B2(n_0_369), .C1(op2[0]), .C2(n_0_339), .ZN(n_0_337) + ); + NAND2_X1_LVT i_0_363( + .A1(n_19), .A2(n_0_581), .ZN(n_0_343) + ); + INV_X1_LVT i_0_723( + .A(op2[19]), .ZN(n_0_690) + ); + AOI221_X1_LVT i_0_364( + .A(n_0_690), .B1(n_0_689), .B2(n_0_565), .C1(op1[19]), .C2(n_0_566), .ZN(n_0_344) + ); + XNOR2_X1_LVT i_10_94( + .A(n_10_73), .B(n_10_74), .ZN(n_51) + ); + AOI221_X1_LVT i_0_361( + .A(n_0_344), .B1(op1[19]), .B2(aluBypass), .C1(n_51), .C2(n_0_580), .ZN(n_0_341) + ); + NAND3_X1_LVT i_0_362( + .A1(n_0_690), .A2(op1[19]), .A3(n_0_569), .ZN(n_0_342) + ); + NAND3_X1_LVT i_0_360( + .A1(n_0_343), .A2(n_0_341), .A3(n_0_342), .ZN(n_0_340) + ); + AOI22_X1_LVT i_0_376( + .A1(op1[12]), .A2(n_0_616), .B1(op1[4]), .B2(n_0_618), .ZN(n_0_356) + ); + OAI22_X1_LVT i_0_375( + .A1(n_0_693), .A2(n_0_356), .B1(op2[2]), .B2(n_0_426), .ZN(n_0_355) + ); + INV_X1_LVT i_0_374( + .A(n_0_355), .ZN(n_0_354) + ); + OAI22_X1_LVT i_0_373( + .A1(op2[1]), .A2(n_0_391), .B1(n_0_728), .B2(n_0_354), .ZN(n_0_353) + ); + AOI22_X1_LVT i_0_372( + .A1(n_0_701), .A2(n_0_359), .B1(op2[0]), .B2(n_0_353), .ZN(n_0_352) + ); + INV_X1_LVT i_0_371( + .A(n_0_352), .ZN(n_0_351) + ); + AOI21_X1_LVT i_0_358( + .A(n_0_340), .B1(n_0_620), .B2(n_0_351), .ZN(n_0_338) + ); + AOI22_X1_LVT i_0_366( + .A1(n_0_468), .A2(n_0_347), .B1(op2[1]), .B2(n_0_383), .ZN(n_0_346) + ); + AOI22_X1_LVT i_0_365( + .A1(n_0_701), .A2(n_0_346), .B1(op2[0]), .B2(n_0_368), .ZN(n_0_345) + ); + OAI211_X1_LVT i_0_356( + .A(n_0_337), .B(n_0_338), .C1(n_0_545), .C2(n_0_345), .ZN(result[19]) + ); + XNOR2_X1_LVT i_10_90( + .A(n_10_70), .B(n_10_71), .ZN(n_50) + ); + NAND2_X1_LVT i_0_342( + .A1(n_50), .A2(n_0_580), .ZN(n_0_323) + ); + OAI21_X1_LVT i_0_343( + .A(n_0_681), .B1(op2[18]), .B2(n_0_568), .ZN(n_0_324) + ); + AOI22_X1_LVT i_0_341( + .A1(op1[18]), .A2(n_0_324), .B1(n_18), .B2(n_0_581), .ZN(n_0_322) + ); + OAI221_X1_LVT i_0_340( + .A(op2[18]), .B1(n_0_705), .B2(n_0_567), .C1(op1[18]), .C2(n_0_564), .ZN(n_0_321) + ); + NAND3_X1_LVT i_0_339( + .A1(n_0_323), .A2(n_0_322), .A3(n_0_321), .ZN(n_0_320) + ); + OAI22_X1_LVT i_0_351( + .A1(op2[3]), .A2(n_0_705), .B1(n_0_723), .B2(n_0_711), .ZN(n_0_332) + ); + AND2_X1_LVT i_0_350( + .A1(n_0_738), .A2(n_0_332), .ZN(n_0_331) + ); + AOI22_X1_LVT i_0_349( + .A1(n_0_498), .A2(n_0_406), .B1(n_0_693), .B2(n_0_331), .ZN(n_0_330) + ); + NAND2_X1_LVT i_0_348( + .A1(n_0_728), .A2(n_0_330), .ZN(n_0_329) + ); + NAND2_X1_LVT i_0_347( + .A1(op2[1]), .A2(n_0_370), .ZN(n_0_328) + ); + AND2_X1_LVT i_0_338( + .A1(n_0_329), .A2(n_0_328), .ZN(n_0_319) + ); + OAI22_X1_LVT i_0_337( + .A1(op2[0]), .A2(n_0_319), .B1(n_0_701), .B2(n_0_339), .ZN(n_0_318) + ); + INV_X1_LVT i_0_336( + .A(n_0_318), .ZN(n_0_317) + ); + AOI21_X1_LVT i_0_335( + .A(n_0_320), .B1(n_0_578), .B2(n_0_317), .ZN(n_0_316) + ); + OAI22_X1_LVT i_0_346( + .A1(n_0_469), .A2(n_0_329), .B1(n_0_387), .B2(n_0_328), .ZN(n_0_327) + ); + NAND2_X1_LVT i_0_344( + .A1(n_0_544), .A2(n_0_346), .ZN(n_0_325) + ); + NAND2_X1_LVT i_0_354( + .A1(n_0_728), .A2(n_0_361), .ZN(n_0_335) + ); + AOI22_X1_LVT i_0_355( + .A1(n_0_612), .A2(n_0_498), .B1(n_0_693), .B2(n_0_411), .ZN(n_0_336) + ); + OAI21_X1_LVT i_0_353( + .A(n_0_335), .B1(n_0_728), .B2(n_0_336), .ZN(n_0_334) + ); + AOI22_X1_LVT i_0_352( + .A1(n_0_701), .A2(n_0_353), .B1(op2[0]), .B2(n_0_334), .ZN(n_0_333) + ); + OAI221_X1_LVT i_0_334( + .A(n_0_316), .B1(n_0_327), .B2(n_0_325), .C1(n_0_621), .C2(n_0_333), .ZN(result[18]) + ); + NAND2_X1_LVT i_0_325( + .A1(n_17), .A2(n_0_581), .ZN(n_0_307) + ); + INV_X1_LVT i_0_765( + .A(op1[17]), .ZN(n_0_732) + ); + AOI22_X1_LVT i_0_324( + .A1(n_0_732), .A2(n_0_565), .B1(op1[17]), .B2(n_0_566), .ZN(n_0_306) + ); + NOR2_X1_LVT i_0_693( + .A1(n_0_732), .A2(op2[17]), .ZN(n_0_660) + ); + XNOR2_X1_LVT i_10_86( + .A(n_10_67), .B(n_10_68), .ZN(n_49) + ); + AOI222_X1_LVT i_0_323( + .A1(op2[17]), .A2(n_0_306), .B1(n_0_660), .B2(n_0_569), .C1(n_49), .C2(n_0_580), + .ZN(n_0_305) + ); + OAI211_X1_LVT i_0_322( + .A(n_0_307), .B(n_0_305), .C1(n_0_732), .C2(n_0_681), .ZN(n_0_304) + ); + AOI22_X1_LVT i_0_331( + .A1(op2[3]), .A2(op1[25]), .B1(op1[17]), .B2(n_0_723), .ZN(n_0_313) + ); + NOR2_X1_LVT i_0_330( + .A1(op2[4]), .A2(n_0_313), .ZN(n_0_312) + ); + AOI22_X1_LVT i_0_329( + .A1(n_0_498), .A2(n_0_386), .B1(n_0_693), .B2(n_0_312), .ZN(n_0_311) + ); + OAI22_X1_LVT i_0_328( + .A1(op2[1]), .A2(n_0_311), .B1(n_0_728), .B2(n_0_348), .ZN(n_0_310) + ); + OR2_X1_LVT i_0_327( + .A1(op2[0]), .A2(n_0_310), .ZN(n_0_309) + ); + OAI21_X1_LVT i_0_321( + .A(n_0_576), .B1(n_0_701), .B2(n_0_319), .ZN(n_0_303) + ); + INV_X1_LVT i_0_320( + .A(n_0_303), .ZN(n_0_302) + ); + AOI21_X1_LVT i_0_319( + .A(n_0_304), .B1(n_0_309), .B2(n_0_302), .ZN(n_0_301) + ); + INV_X1_LVT i_0_345( + .A(n_0_327), .ZN(n_0_326) + ); + OAI22_X1_LVT i_0_326( + .A1(n_0_701), .A2(n_0_326), .B1(n_0_469), .B2(n_0_309), .ZN(n_0_308) + ); + NOR2_X1_LVT i_0_318( + .A1(op2[2]), .A2(n_0_393), .ZN(n_0_300) + ); + AOI21_X1_LVT i_0_317( + .A(n_0_300), .B1(n_0_597), .B2(n_0_498), .ZN(n_0_299) + ); + OAI22_X1_LVT i_0_316( + .A1(n_0_728), .A2(n_0_299), .B1(op2[1]), .B2(n_0_354), .ZN(n_0_298) + ); + OAI22_X1_LVT i_0_315( + .A1(op2[0]), .A2(n_0_334), .B1(n_0_701), .B2(n_0_298), .ZN(n_0_297) + ); + OAI221_X1_LVT i_0_314( + .A(n_0_301), .B1(n_0_545), .B2(n_0_308), .C1(n_0_621), .C2(n_0_297), .ZN(result[17]) + ); + XNOR2_X1_LVT i_10_82( + .A(n_10_64), .B(n_10_65), .ZN(n_48) + ); + AOI22_X1_LVT i_0_301( + .A1(n_48), .A2(n_0_580), .B1(n_16), .B2(n_0_581), .ZN(n_0_284) + ); + NAND2_X1_LVT i_0_333( + .A1(n_0_544), .A2(n_0_469), .ZN(n_0_315) + ); + INV_X1_LVT i_0_332( + .A(n_0_315), .ZN(n_0_314) + ); + OAI21_X1_LVT i_0_302( + .A(n_0_681), .B1(op2[16]), .B2(n_0_568), .ZN(n_0_285) + ); + AOI21_X1_LVT i_0_300( + .A(n_0_314), .B1(op1[16]), .B2(n_0_285), .ZN(n_0_283) + ); + INV_X1_LVT i_0_772( + .A(op1[16]), .ZN(n_0_739) + ); + OAI221_X1_LVT i_0_303( + .A(op2[16]), .B1(op1[16]), .B2(n_0_564), .C1(n_0_739), .C2(n_0_567), .ZN(n_0_286) + ); + NAND3_X1_LVT i_0_299( + .A1(n_0_284), .A2(n_0_283), .A3(n_0_286), .ZN(n_0_282) + ); + INV_X1_LVT i_0_593( + .A(n_0_562), .ZN(n_0_561) + ); + OAI22_X1_LVT i_0_307( + .A1(op1[16]), .A2(op2[3]), .B1(op1[24]), .B2(n_0_723), .ZN(n_0_290) + ); + NOR2_X1_LVT i_0_306( + .A1(op2[4]), .A2(n_0_290), .ZN(n_0_289) + ); + AOI22_X1_LVT i_0_305( + .A1(n_0_693), .A2(n_0_289), .B1(op2[2]), .B2(n_0_371), .ZN(n_0_288) + ); + OAI22_X1_LVT i_0_304( + .A1(n_0_728), .A2(n_0_330), .B1(op2[1]), .B2(n_0_288), .ZN(n_0_287) + ); + AOI221_X1_LVT i_0_298( + .A(n_0_282), .B1(n_0_547), .B2(n_0_310), .C1(n_0_561), .C2(n_0_287), .ZN(n_0_281) + ); + INV_X1_LVT i_0_762( + .A(op1[1]), .ZN(n_0_729) + ); + OAI22_X1_LVT i_0_313( + .A1(n_0_722), .A2(n_0_615), .B1(n_0_729), .B2(n_0_617), .ZN(n_0_296) + ); + NAND2_X1_LVT i_0_312( + .A1(op2[2]), .A2(n_0_296), .ZN(n_0_295) + ); + OAI21_X1_LVT i_0_311( + .A(n_0_295), .B1(op2[2]), .B2(n_0_362), .ZN(n_0_294) + ); + NAND2_X1_LVT i_0_310( + .A1(op2[1]), .A2(n_0_294), .ZN(n_0_293) + ); + OAI21_X1_LVT i_0_309( + .A(n_0_293), .B1(op2[1]), .B2(n_0_336), .ZN(n_0_292) + ); + OAI22_X1_LVT i_0_308( + .A1(op2[0]), .A2(n_0_298), .B1(n_0_701), .B2(n_0_292), .ZN(n_0_291) + ); + OAI21_X1_LVT i_0_297( + .A(n_0_281), .B1(n_0_621), .B2(n_0_291), .ZN(result[16]) + ); + OAI221_X1_LVT i_0_286( + .A(op2[15]), .B1(n_0_734), .B2(n_0_567), .C1(op1[15]), .C2(n_0_564), .ZN(n_0_270) + ); + AOI21_X1_LVT i_0_288( + .A(n_0_314), .B1(n_15), .B2(n_0_581), .ZN(n_0_272) + ); + INV_X1_LVT i_0_287( + .A(n_0_272), .ZN(n_0_271) + ); + XNOR2_X1_LVT i_10_78( + .A(n_10_61), .B(n_10_62), .ZN(n_47) + ); + OAI21_X1_LVT i_0_285( + .A(n_0_681), .B1(op2[15]), .B2(n_0_568), .ZN(n_0_269) + ); + AOI221_X1_LVT i_0_284( + .A(n_0_271), .B1(n_47), .B2(n_0_580), .C1(op1[15]), .C2(n_0_269), .ZN(n_0_268) + ); + AOI22_X1_LVT i_0_296( + .A1(op1[8]), .A2(n_0_616), .B1(op1[0]), .B2(n_0_618), .ZN(n_0_280) + ); + AOI22_X1_LVT i_0_295( + .A1(op2[2]), .A2(n_0_280), .B1(n_0_693), .B2(n_0_356), .ZN(n_0_279) + ); + NAND2_X1_LVT i_0_294( + .A1(op2[1]), .A2(n_0_279), .ZN(n_0_278) + ); + OAI21_X1_LVT i_0_293( + .A(n_0_278), .B1(op2[1]), .B2(n_0_299), .ZN(n_0_277) + ); + OAI221_X1_LVT i_0_292( + .A(n_0_620), .B1(n_0_701), .B2(n_0_277), .C1(op2[0]), .C2(n_0_292), .ZN(n_0_276) + ); + OAI222_X1_LVT i_0_291( + .A1(n_0_719), .A2(n_0_617), .B1(n_0_691), .B2(n_0_605), .C1(n_0_734), .C2(n_0_615), + .ZN(n_0_275) + ); + OAI22_X1_LVT i_0_290( + .A1(n_0_693), .A2(n_0_349), .B1(op2[2]), .B2(n_0_275), .ZN(n_0_274) + ); + OAI22_X1_LVT i_0_289( + .A1(op2[1]), .A2(n_0_274), .B1(n_0_728), .B2(n_0_311), .ZN(n_0_273) + ); + AOI22_X1_LVT i_0_283( + .A1(n_0_561), .A2(n_0_273), .B1(n_0_547), .B2(n_0_287), .ZN(n_0_267) + ); + NAND4_X1_LVT i_0_282( + .A1(n_0_270), .A2(n_0_268), .A3(n_0_276), .A4(n_0_267), .ZN(result[15]) + ); + NOR2_X1_LVT i_0_278( + .A1(op2[0]), .A2(n_0_277), .ZN(n_0_263) + ); + NAND2_X1_LVT i_0_281( + .A1(n_0_612), .A2(n_0_575), .ZN(n_0_266) + ); + OAI21_X1_LVT i_0_280( + .A(n_0_266), .B1(n_0_713), .B2(n_0_497), .ZN(n_0_265) + ); + AOI22_X1_LVT i_0_279( + .A1(op2[1]), .A2(n_0_265), .B1(n_0_728), .B2(n_0_294), .ZN(n_0_264) + ); + AOI211_X1_LVT i_0_277( + .A(n_0_263), .B(n_0_621), .C1(op2[0]), .C2(n_0_264), .ZN(n_0_262) + ); + INV_X1_LVT i_0_754( + .A(op1[14]), .ZN(n_0_721) + ); + OAI21_X1_LVT i_0_273( + .A(op2[14]), .B1(n_0_721), .B2(n_0_567), .ZN(n_0_258) + ); + AOI21_X1_LVT i_0_272( + .A(n_0_258), .B1(n_0_721), .B2(n_0_565), .ZN(n_0_257) + ); + XNOR2_X1_LVT i_10_74( + .A(n_10_58), .B(n_10_59), .ZN(n_46) + ); + OAI21_X1_LVT i_0_276( + .A(n_0_681), .B1(op2[14]), .B2(n_0_568), .ZN(n_0_261) + ); + AOI222_X1_LVT i_0_275( + .A1(n_14), .A2(n_0_581), .B1(n_46), .B2(n_0_580), .C1(op1[14]), .C2(n_0_261), + .ZN(n_0_260) + ); + INV_X1_LVT i_0_274( + .A(n_0_260), .ZN(n_0_259) + ); + OAI222_X1_LVT i_0_271( + .A1(n_0_717), .A2(n_0_605), .B1(n_0_687), .B2(n_0_617), .C1(n_0_721), .C2(n_0_615), + .ZN(n_0_256) + ); + OAI22_X1_LVT i_0_270( + .A1(n_0_693), .A2(n_0_331), .B1(op2[2]), .B2(n_0_256), .ZN(n_0_255) + ); + AND2_X1_LVT i_0_269( + .A1(n_0_728), .A2(n_0_255), .ZN(n_0_254) + ); + NOR3_X1_LVT i_0_265( + .A1(op2[3]), .A2(op2[2]), .A3(op2[0]), .ZN(n_0_250) + ); + AOI21_X1_LVT i_0_268( + .A(n_0_254), .B1(op2[1]), .B2(n_0_288), .ZN(n_0_253) + ); + OAI22_X1_LVT i_0_266( + .A1(op2[0]), .A2(n_0_253), .B1(n_0_701), .B2(n_0_273), .ZN(n_0_251) + ); + AOI221_X1_LVT i_0_259( + .A(n_0_579), .B1(n_0_254), .B2(n_0_250), .C1(n_0_315), .C2(n_0_251), .ZN(n_0_244) + ); + OR4_X1_LVT i_0_258( + .A1(n_0_262), .A2(n_0_257), .A3(n_0_259), .A4(n_0_244), .ZN(result[14]) + ); + OAI221_X1_LVT i_0_245( + .A(op2[13]), .B1(op1[13]), .B2(n_0_564), .C1(n_0_714), .C2(n_0_567), .ZN(n_0_231) + ); + NAND2_X1_LVT i_0_244( + .A1(n_13), .A2(n_0_581), .ZN(n_0_230) + ); + OAI211_X1_LVT i_0_243( + .A(n_0_231), .B(n_0_230), .C1(n_0_714), .C2(n_0_681), .ZN(n_0_229) + ); + XNOR2_X1_LVT i_10_70( + .A(n_10_55), .B(n_10_56), .ZN(n_45) + ); + NOR2_X1_LVT i_0_695( + .A1(op2[13]), .A2(n_0_714), .ZN(n_0_662) + ); + AOI221_X1_LVT i_0_242( + .A(n_0_229), .B1(n_45), .B2(n_0_580), .C1(n_0_662), .C2(n_0_569), .ZN(n_0_228) + ); + INV_X1_LVT i_0_267( + .A(n_0_253), .ZN(n_0_252) + ); + OAI222_X1_LVT i_0_257( + .A1(n_0_714), .A2(n_0_615), .B1(n_0_726), .B2(n_0_617), .C1(n_0_710), .C2(n_0_605), + .ZN(n_0_243) + ); + OAI22_X1_LVT i_0_256( + .A1(n_0_693), .A2(n_0_312), .B1(op2[2]), .B2(n_0_243), .ZN(n_0_242) + ); + NAND2_X1_LVT i_0_255( + .A1(n_0_728), .A2(n_0_242), .ZN(n_0_241) + ); + NAND2_X1_LVT i_0_254( + .A1(op2[1]), .A2(n_0_274), .ZN(n_0_240) + ); + NAND2_X1_LVT i_0_241( + .A1(n_0_241), .A2(n_0_240), .ZN(n_0_227) + ); + OAI221_X1_LVT i_0_240( + .A(n_0_228), .B1(n_0_548), .B2(n_0_252), .C1(n_0_562), .C2(n_0_227), .ZN(n_0_226) + ); + NAND2_X1_LVT i_0_249( + .A1(n_0_728), .A2(n_0_279), .ZN(n_0_235) + ); + AOI22_X1_LVT i_0_250( + .A1(n_0_597), .A2(n_0_575), .B1(op1[6]), .B2(n_0_496), .ZN(n_0_236) + ); + OAI21_X1_LVT i_0_248( + .A(n_0_235), .B1(n_0_728), .B2(n_0_236), .ZN(n_0_234) + ); + INV_X1_LVT i_0_247( + .A(n_0_234), .ZN(n_0_233) + ); + AOI221_X1_LVT i_0_246( + .A(n_0_621), .B1(op2[0]), .B2(n_0_233), .C1(n_0_701), .C2(n_0_264), .ZN(n_0_232) + ); + NAND2_X1_LVT i_0_264( + .A1(op2[3]), .A2(n_0_469), .ZN(n_0_249) + ); + AOI21_X1_LVT i_0_262( + .A(n_0_468), .B1(n_0_693), .B2(n_0_249), .ZN(n_0_247) + ); + INV_X1_LVT i_0_261( + .A(n_0_247), .ZN(n_0_246) + ); + OAI211_X1_LVT i_0_260( + .A(n_0_252), .B(n_0_246), .C1(n_0_468), .C2(n_0_254), .ZN(n_0_245) + ); + OAI221_X1_LVT i_0_253( + .A(n_0_544), .B1(n_0_247), .B2(n_0_241), .C1(n_0_469), .C2(n_0_240), .ZN(n_0_239) + ); + INV_X1_LVT i_0_252( + .A(n_0_239), .ZN(n_0_238) + ); + AOI211_X1_LVT i_0_239( + .A(n_0_226), .B(n_0_232), .C1(n_0_245), .C2(n_0_238), .ZN(n_0_225) + ); + INV_X1_LVT i_0_238( + .A(n_0_225), .ZN(result[13]) + ); + OAI221_X1_LVT i_0_232( + .A(op2[12]), .B1(n_0_696), .B2(n_0_567), .C1(op1[12]), .C2(n_0_564), .ZN(n_0_219) + ); + OAI21_X1_LVT i_0_231( + .A(n_0_681), .B1(op2[12]), .B2(n_0_568), .ZN(n_0_218) + ); + XNOR2_X1_LVT i_10_66( + .A(n_10_52), .B(n_10_53), .ZN(n_44) + ); + AOI222_X1_LVT i_0_230( + .A1(n_12), .A2(n_0_581), .B1(op1[12]), .B2(n_0_218), .C1(n_44), .C2(n_0_580), + .ZN(n_0_217) + ); + OAI21_X1_LVT i_0_234( + .A(n_0_620), .B1(op2[1]), .B2(n_0_265), .ZN(n_0_221) + ); + INV_X1_LVT i_0_763( + .A(op1[5]), .ZN(n_0_730) + ); + OAI21_X1_LVT i_0_236( + .A(op2[2]), .B1(n_0_730), .B2(n_0_615), .ZN(n_0_223) + ); + OAI21_X1_LVT i_0_235( + .A(n_0_223), .B1(op2[2]), .B2(n_0_296), .ZN(n_0_222) + ); + AOI21_X1_LVT i_0_233( + .A(n_0_221), .B1(op2[1]), .B2(n_0_222), .ZN(n_0_220) + ); + NOR2_X1_LVT i_0_237( + .A1(n_0_577), .A2(n_0_227), .ZN(n_0_224) + ); + NOR4_X1_LVT i_0_223( + .A1(n_0_701), .A2(n_0_220), .A3(n_0_224), .A4(n_0_238), .ZN(n_0_210) + ); + NAND2_X1_LVT i_0_224( + .A1(n_0_544), .A2(n_0_247), .ZN(n_0_211) + ); + NAND2_X1_LVT i_0_222( + .A1(n_0_701), .A2(n_0_211), .ZN(n_0_209) + ); + OAI22_X1_LVT i_0_229( + .A1(op2[4]), .A2(n_0_696), .B1(n_0_738), .B2(n_0_698), .ZN(n_0_216) + ); + INV_X1_LVT i_0_228( + .A(n_0_216), .ZN(n_0_215) + ); + OAI22_X1_LVT i_0_227( + .A1(n_0_727), .A2(n_0_617), .B1(op2[3]), .B2(n_0_215), .ZN(n_0_214) + ); + OAI22_X1_LVT i_0_226( + .A1(n_0_693), .A2(n_0_289), .B1(op2[2]), .B2(n_0_214), .ZN(n_0_213) + ); + OAI22_X1_LVT i_0_225( + .A1(op2[1]), .A2(n_0_213), .B1(n_0_728), .B2(n_0_255), .ZN(n_0_212) + ); + AOI221_X1_LVT i_0_221( + .A(n_0_209), .B1(n_0_578), .B2(n_0_212), .C1(n_0_620), .C2(n_0_234), .ZN(n_0_208) + ); + OAI211_X1_LVT i_0_220( + .A(n_0_219), .B(n_0_217), .C1(n_0_210), .C2(n_0_208), .ZN(result[12]) + ); + OAI21_X1_LVT i_0_209( + .A(n_0_681), .B1(op2[11]), .B2(n_0_568), .ZN(n_0_197) + ); + AOI22_X1_LVT i_0_208( + .A1(n_11), .A2(n_0_581), .B1(op1[11]), .B2(n_0_197), .ZN(n_0_196) + ); + NAND2_X1_LVT i_0_207( + .A1(n_0_211), .A2(n_0_196), .ZN(n_0_195) + ); + AOI22_X1_LVT i_0_210( + .A1(op1[11]), .A2(n_0_566), .B1(n_0_706), .B2(n_0_565), .ZN(n_0_198) + ); + XNOR2_X1_LVT i_10_62( + .A(n_10_49), .B(n_10_50), .ZN(n_43) + ); + AOI221_X1_LVT i_0_206( + .A(n_0_195), .B1(op2[11]), .B2(n_0_198), .C1(n_43), .C2(n_0_580), .ZN(n_0_194) + ); + AOI221_X1_LVT i_0_215( + .A(op2[3]), .B1(n_0_738), .B2(n_0_706), .C1(op2[4]), .C2(n_0_688), .ZN(n_0_203) + ); + AOI21_X1_LVT i_0_214( + .A(n_0_203), .B1(op1[19]), .B2(n_0_618), .ZN(n_0_202) + ); + NAND2_X1_LVT i_0_213( + .A1(n_0_693), .A2(n_0_202), .ZN(n_0_201) + ); + OAI21_X1_LVT i_0_212( + .A(n_0_201), .B1(n_0_693), .B2(n_0_275), .ZN(n_0_200) + ); + OAI22_X1_LVT i_0_211( + .A1(n_0_728), .A2(n_0_242), .B1(op2[1]), .B2(n_0_200), .ZN(n_0_199) + ); + AOI22_X1_LVT i_0_205( + .A1(n_0_561), .A2(n_0_199), .B1(n_0_701), .B2(n_0_220), .ZN(n_0_193) + ); + NOR2_X1_LVT i_0_219( + .A1(op2[2]), .A2(n_0_280), .ZN(n_0_207) + ); + AOI21_X1_LVT i_0_218( + .A(n_0_207), .B1(op1[4]), .B2(n_0_496), .ZN(n_0_206) + ); + AOI22_X1_LVT i_0_217( + .A1(n_0_728), .A2(n_0_236), .B1(op2[1]), .B2(n_0_206), .ZN(n_0_205) + ); + AOI22_X1_LVT i_0_216( + .A1(n_0_578), .A2(n_0_212), .B1(n_0_620), .B2(n_0_205), .ZN(n_0_204) + ); + OAI211_X1_LVT i_0_204( + .A(n_0_194), .B(n_0_193), .C1(n_0_701), .C2(n_0_204), .ZN(result[11]) + ); + AOI22_X1_LVT i_0_194( + .A1(n_0_654), .A2(n_0_498), .B1(op1[7]), .B2(n_0_573), .ZN(n_0_183) + ); + OAI22_X1_LVT i_0_193( + .A1(n_0_728), .A2(n_0_183), .B1(op2[1]), .B2(n_0_222), .ZN(n_0_182) + ); + AOI22_X1_LVT i_0_192( + .A1(op2[0]), .A2(n_0_182), .B1(n_0_701), .B2(n_0_205), .ZN(n_0_181) + ); + NOR2_X1_LVT i_0_191( + .A1(n_0_621), .A2(n_0_181), .ZN(n_0_180) + ); + AOI22_X1_LVT i_0_190( + .A1(op1[10]), .A2(n_0_566), .B1(n_0_733), .B2(n_0_565), .ZN(n_0_179) + ); + XNOR2_X1_LVT i_10_58( + .A(n_10_46), .B(n_10_47), .ZN(n_42) + ); + AOI22_X1_LVT i_0_188( + .A1(op2[10]), .A2(n_0_179), .B1(n_42), .B2(n_0_580), .ZN(n_0_177) + ); + OAI21_X1_LVT i_0_189( + .A(n_0_681), .B1(op2[10]), .B2(n_0_568), .ZN(n_0_178) + ); + AOI22_X1_LVT i_0_187( + .A1(n_10), .A2(n_0_581), .B1(op1[10]), .B2(n_0_178), .ZN(n_0_176) + ); + NAND2_X1_LVT i_0_186( + .A1(n_0_177), .A2(n_0_176), .ZN(n_0_175) + ); + NOR2_X1_LVT i_0_203( + .A1(n_0_701), .A2(n_0_199), .ZN(n_0_192) + ); + NOR2_X1_LVT i_0_200( + .A1(n_0_693), .A2(n_0_256), .ZN(n_0_189) + ); + AOI221_X1_LVT i_0_202( + .A(n_0_596), .B1(op1[10]), .B2(n_0_616), .C1(op1[26]), .C2(n_0_606), .ZN(n_0_191) + ); + AOI21_X1_LVT i_0_199( + .A(n_0_189), .B1(n_0_693), .B2(n_0_191), .ZN(n_0_188) + ); + OR2_X1_LVT i_0_198( + .A1(op2[1]), .A2(n_0_188), .ZN(n_0_187) + ); + NAND2_X1_LVT i_0_197( + .A1(op2[1]), .A2(n_0_213), .ZN(n_0_186) + ); + NAND2_X1_LVT i_0_185( + .A1(n_0_187), .A2(n_0_186), .ZN(n_0_174) + ); + AOI211_X1_LVT i_0_184( + .A(n_0_577), .B(n_0_192), .C1(n_0_701), .C2(n_0_174), .ZN(n_0_173) + ); + INV_X1_LVT i_0_263( + .A(n_0_249), .ZN(n_0_248) + ); + OAI22_X1_LVT i_0_196( + .A1(n_0_248), .A2(n_0_187), .B1(n_0_247), .B2(n_0_186), .ZN(n_0_185) + ); + AOI221_X1_LVT i_0_195( + .A(n_0_545), .B1(n_0_246), .B2(n_0_192), .C1(n_0_701), .C2(n_0_185), .ZN(n_0_184) + ); + OR4_X1_LVT i_0_183( + .A1(n_0_180), .A2(n_0_175), .A3(n_0_173), .A4(n_0_184), .ZN(result[10]) + ); + INV_X1_LVT i_0_753( + .A(op2[9]), .ZN(n_0_720) + ); + AOI221_X1_LVT i_0_171( + .A(n_0_720), .B1(op1[9]), .B2(n_0_566), .C1(n_0_722), .C2(n_0_565), .ZN(n_0_161) + ); + XNOR2_X1_LVT i_10_54( + .A(n_10_43), .B(n_10_44), .ZN(n_41) + ); + AOI22_X1_LVT i_0_172( + .A1(n_9), .A2(n_0_581), .B1(n_41), .B2(n_0_580), .ZN(n_0_162) + ); + AOI21_X1_LVT i_0_170( + .A(aluBypass), .B1(n_0_720), .B2(n_0_569), .ZN(n_0_160) + ); + OAI21_X1_LVT i_0_169( + .A(n_0_162), .B1(n_0_722), .B2(n_0_160), .ZN(n_0_159) + ); + OAI222_X1_LVT i_0_182( + .A1(n_0_722), .A2(n_0_615), .B1(n_0_699), .B2(n_0_605), .C1(n_0_732), .C2(n_0_617), + .ZN(n_0_172) + ); + AOI22_X1_LVT i_0_181( + .A1(n_0_693), .A2(n_0_172), .B1(op2[2]), .B2(n_0_243), .ZN(n_0_171) + ); + NAND2_X1_LVT i_0_180( + .A1(n_0_728), .A2(n_0_171), .ZN(n_0_170) + ); + NAND2_X1_LVT i_0_179( + .A1(op2[1]), .A2(n_0_200), .ZN(n_0_169) + ); + OAI22_X1_LVT i_0_178( + .A1(n_0_248), .A2(n_0_170), .B1(n_0_247), .B2(n_0_169), .ZN(n_0_168) + ); + NOR3_X1_LVT i_0_177( + .A1(n_0_545), .A2(n_0_168), .A3(n_0_185), .ZN(n_0_167) + ); + NOR2_X1_LVT i_0_251( + .A1(n_0_704), .A2(n_0_615), .ZN(n_0_237) + ); + OAI22_X1_LVT i_0_176( + .A1(op1[2]), .A2(n_0_693), .B1(n_0_496), .B2(n_0_237), .ZN(n_0_166) + ); + OAI22_X1_LVT i_0_175( + .A1(op2[1]), .A2(n_0_206), .B1(n_0_728), .B2(n_0_166), .ZN(n_0_165) + ); + OAI221_X1_LVT i_0_174( + .A(n_0_620), .B1(op2[0]), .B2(n_0_182), .C1(n_0_701), .C2(n_0_165), .ZN(n_0_164) + ); + NAND2_X1_LVT i_0_173( + .A1(n_0_170), .A2(n_0_169), .ZN(n_0_163) + ); + OAI221_X1_LVT i_0_168( + .A(n_0_164), .B1(n_0_562), .B2(n_0_163), .C1(n_0_548), .C2(n_0_174), .ZN(n_0_158) + ); + OR4_X1_LVT i_0_167( + .A1(n_0_161), .A2(n_0_159), .A3(n_0_167), .A4(n_0_158), .ZN(result[9]) + ); + OAI21_X1_LVT i_0_160( + .A(n_0_693), .B1(n_0_730), .B2(n_0_615), .ZN(n_0_151) + ); + OAI21_X1_LVT i_0_159( + .A(op2[2]), .B1(n_0_729), .B2(n_0_615), .ZN(n_0_150) + ); + AND2_X1_LVT i_0_158( + .A1(n_0_151), .A2(n_0_150), .ZN(n_0_149) + ); + NAND2_X1_LVT i_0_157( + .A1(op2[1]), .A2(n_0_149), .ZN(n_0_148) + ); + OAI21_X1_LVT i_0_156( + .A(n_0_148), .B1(op2[1]), .B2(n_0_183), .ZN(n_0_147) + ); + OAI22_X1_LVT i_0_155( + .A1(op2[0]), .A2(n_0_165), .B1(n_0_701), .B2(n_0_147), .ZN(n_0_146) + ); + NOR2_X1_LVT i_0_154( + .A1(n_0_621), .A2(n_0_146), .ZN(n_0_145) + ); + INV_X1_LVT i_0_773( + .A(op1[8]), .ZN(n_0_740) + ); + NOR2_X1_LVT i_0_688( + .A1(n_0_740), .A2(op2[8]), .ZN(n_0_655) + ); + AOI22_X1_LVT i_0_153( + .A1(op1[8]), .A2(aluBypass), .B1(n_0_655), .B2(n_0_569), .ZN(n_0_144) + ); + OAI221_X1_LVT i_0_152( + .A(op2[8]), .B1(op1[8]), .B2(n_0_564), .C1(n_0_740), .C2(n_0_567), .ZN(n_0_143) + ); + XNOR2_X1_LVT i_10_51( + .A(n_10_39), .B(n_10_42), .ZN(n_40) + ); + AOI22_X1_LVT i_0_151( + .A1(n_40), .A2(n_0_580), .B1(n_8), .B2(n_0_581), .ZN(n_0_142) + ); + NAND3_X1_LVT i_0_150( + .A1(n_0_144), .A2(n_0_143), .A3(n_0_142), .ZN(n_0_141) + ); + OAI222_X1_LVT i_0_166( + .A1(n_0_740), .A2(n_0_615), .B1(n_0_739), .B2(n_0_617), .C1(n_0_736), .C2(n_0_605), + .ZN(n_0_157) + ); + OAI22_X1_LVT i_0_165( + .A1(op2[2]), .A2(n_0_157), .B1(n_0_693), .B2(n_0_214), .ZN(n_0_156) + ); + NOR2_X1_LVT i_0_164( + .A1(op2[1]), .A2(n_0_156), .ZN(n_0_155) + ); + AOI21_X1_LVT i_0_163( + .A(n_0_155), .B1(op2[1]), .B2(n_0_188), .ZN(n_0_154) + ); + AND2_X1_LVT i_0_162( + .A1(n_0_701), .A2(n_0_154), .ZN(n_0_153) + ); + AOI211_X1_LVT i_0_149( + .A(n_0_577), .B(n_0_153), .C1(op2[0]), .C2(n_0_163), .ZN(n_0_140) + ); + AOI221_X1_LVT i_0_161( + .A(n_0_545), .B1(op2[0]), .B2(n_0_168), .C1(n_0_249), .C2(n_0_153), .ZN(n_0_152) + ); + OR4_X1_LVT i_0_148( + .A1(n_0_145), .A2(n_0_141), .A3(n_0_140), .A4(n_0_152), .ZN(result[8]) + ); + AOI22_X1_LVT i_0_138( + .A1(op1[4]), .A2(n_0_573), .B1(op1[0]), .B2(n_0_496), .ZN(n_0_130) + ); + AOI22_X1_LVT i_0_137( + .A1(op2[1]), .A2(n_0_130), .B1(n_0_728), .B2(n_0_166), .ZN(n_0_129) + ); + OAI22_X1_LVT i_0_136( + .A1(n_0_701), .A2(n_0_129), .B1(op2[0]), .B2(n_0_147), .ZN(n_0_128) + ); + NOR2_X1_LVT i_0_135( + .A1(n_0_621), .A2(n_0_128), .ZN(n_0_127) + ); + OAI221_X1_LVT i_0_139( + .A(op2[7]), .B1(n_0_713), .B2(n_0_567), .C1(op1[7]), .C2(n_0_564), .ZN(n_0_131) + ); + INV_X1_LVT i_10_44( + .A(n_10_36), .ZN(n_10_37) + ); + NOR2_X1_LVT i_10_45( + .A1(n_10_35), .A2(n_10_37), .ZN(n_10_38) + ); + XNOR2_X1_LVT i_10_46( + .A(n_10_33), .B(n_10_38), .ZN(n_39) + ); + AOI22_X1_LVT i_0_141( + .A1(n_7), .A2(n_0_581), .B1(n_39), .B2(n_0_580), .ZN(n_0_133) + ); + INV_X1_LVT i_0_745( + .A(op2[7]), .ZN(n_0_712) + ); + AOI21_X1_LVT i_0_140( + .A(aluBypass), .B1(n_0_712), .B2(n_0_569), .ZN(n_0_132) + ); + OAI211_X1_LVT i_0_133( + .A(n_0_131), .B(n_0_133), .C1(n_0_713), .C2(n_0_132), .ZN(n_0_125) + ); + OAI22_X1_LVT i_0_147( + .A1(n_0_734), .A2(n_0_617), .B1(n_0_713), .B2(n_0_615), .ZN(n_0_139) + ); + AOI211_X1_LVT i_0_146( + .A(n_0_139), .B(n_0_248), .C1(op1[23]), .C2(n_0_606), .ZN(n_0_138) + ); + OAI22_X1_LVT i_0_145( + .A1(n_0_693), .A2(n_0_202), .B1(op2[2]), .B2(n_0_138), .ZN(n_0_137) + ); + NOR2_X1_LVT i_0_144( + .A1(op2[1]), .A2(n_0_137), .ZN(n_0_136) + ); + AOI21_X1_LVT i_0_143( + .A(n_0_136), .B1(op2[1]), .B2(n_0_171), .ZN(n_0_135) + ); + NAND2_X1_LVT i_0_142( + .A1(n_0_561), .A2(n_0_135), .ZN(n_0_134) + ); + OAI221_X1_LVT i_0_134( + .A(n_0_134), .B1(n_0_548), .B2(n_0_154), .C1(n_0_545), .C2(n_0_249), .ZN(n_0_126) + ); + OR3_X1_LVT i_0_132( + .A1(n_0_127), .A2(n_0_125), .A3(n_0_126), .ZN(result[7]) + ); + NAND2_X1_LVT i_0_124( + .A1(n_0_728), .A2(n_0_149), .ZN(n_0_117) + ); + OAI21_X1_LVT i_0_123( + .A(n_0_117), .B1(n_0_724), .B2(n_0_531), .ZN(n_0_116) + ); + OAI22_X1_LVT i_0_122( + .A1(n_0_701), .A2(n_0_116), .B1(op2[0]), .B2(n_0_129), .ZN(n_0_115) + ); + NOR2_X1_LVT i_0_121( + .A1(n_0_621), .A2(n_0_115), .ZN(n_0_114) + ); + XNOR2_X1_LVT i_10_38( + .A(n_10_30), .B(n_10_31), .ZN(n_38) + ); + AOI22_X1_LVT i_0_119( + .A1(n_6), .A2(n_0_581), .B1(n_38), .B2(n_0_580), .ZN(n_0_112) + ); + INV_X1_LVT i_0_735( + .A(op2[6]), .ZN(n_0_702) + ); + AOI21_X1_LVT i_0_120( + .A(aluBypass), .B1(n_0_702), .B2(n_0_569), .ZN(n_0_113) + ); + OAI21_X1_LVT i_0_118( + .A(n_0_112), .B1(n_0_704), .B2(n_0_113), .ZN(n_0_111) + ); + AOI221_X1_LVT i_0_117( + .A(n_0_702), .B1(n_0_704), .B2(n_0_565), .C1(op1[6]), .C2(n_0_566), .ZN(n_0_110) + ); + NOR3_X1_LVT i_0_116( + .A1(n_0_114), .A2(n_0_111), .A3(n_0_110), .ZN(n_0_109) + ); + AOI221_X1_LVT i_0_131( + .A(n_0_237), .B1(op1[14]), .B2(n_0_618), .C1(op2[4]), .C2(n_0_406), .ZN(n_0_124) + ); + NAND2_X1_LVT i_0_130( + .A1(n_0_693), .A2(n_0_124), .ZN(n_0_123) + ); + INV_X1_LVT i_0_201( + .A(n_0_191), .ZN(n_0_190) + ); + OAI21_X1_LVT i_0_129( + .A(n_0_123), .B1(n_0_693), .B2(n_0_190), .ZN(n_0_122) + ); + AOI22_X1_LVT i_0_128( + .A1(n_0_728), .A2(n_0_122), .B1(op2[1]), .B2(n_0_156), .ZN(n_0_121) + ); + INV_X1_LVT i_0_127( + .A(n_0_121), .ZN(n_0_120) + ); + OAI21_X1_LVT i_0_126( + .A(n_0_248), .B1(op2[1]), .B2(n_0_123), .ZN(n_0_119) + ); + AND2_X1_LVT i_0_125( + .A1(n_0_120), .A2(n_0_119), .ZN(n_0_118) + ); + NOR2_X1_LVT i_0_115( + .A1(n_0_545), .A2(n_0_118), .ZN(n_0_108) + ); + AOI21_X1_LVT i_0_114( + .A(n_0_108), .B1(n_0_576), .B2(n_0_121), .ZN(n_0_107) + ); + AOI22_X1_LVT i_0_113( + .A1(n_0_544), .A2(n_0_248), .B1(n_0_578), .B2(n_0_135), .ZN(n_0_106) + ); + OAI221_X1_LVT i_0_112( + .A(n_0_109), .B1(op2[0]), .B2(n_0_107), .C1(n_0_701), .C2(n_0_106), .ZN(result[6]) + ); + OAI221_X1_LVT i_0_100( + .A(op2[5]), .B1(op1[5]), .B2(n_0_564), .C1(n_0_730), .C2(n_0_567), .ZN(n_0_94) + ); + INV_X1_LVT i_0_764( + .A(op2[5]), .ZN(n_0_731) + ); + AOI21_X1_LVT i_0_99( + .A(aluBypass), .B1(n_0_731), .B2(n_0_569), .ZN(n_0_93) + ); + NOR2_X1_LVT i_0_98( + .A1(n_0_730), .A2(n_0_93), .ZN(n_0_92) + ); + XNOR2_X1_LVT i_10_35( + .A(n_10_26), .B(n_10_29), .ZN(n_37) + ); + AOI221_X1_LVT i_0_97( + .A(n_0_92), .B1(n_37), .B2(n_0_580), .C1(n_5), .C2(n_0_581), .ZN(n_0_91) + ); + OAI22_X1_LVT i_0_102( + .A1(n_0_694), .A2(n_0_531), .B1(op2[1]), .B2(n_0_130), .ZN(n_0_96) + ); + OAI221_X1_LVT i_0_101( + .A(n_0_620), .B1(n_0_701), .B2(n_0_96), .C1(op2[0]), .C2(n_0_116), .ZN(n_0_95) + ); + NAND3_X1_LVT i_0_111( + .A1(n_0_544), .A2(n_0_248), .A3(op2[2]), .ZN(n_0_105) + ); + NAND2_X1_LVT i_0_110( + .A1(op2[4]), .A2(n_0_386), .ZN(n_0_104) + ); + OAI21_X1_LVT i_0_109( + .A(n_0_104), .B1(n_0_714), .B2(n_0_617), .ZN(n_0_103) + ); + OAI22_X1_LVT i_0_108( + .A1(n_0_151), .A2(n_0_103), .B1(n_0_693), .B2(n_0_172), .ZN(n_0_102) + ); + NOR2_X1_LVT i_0_107( + .A1(op2[1]), .A2(n_0_102), .ZN(n_0_101) + ); + AOI21_X1_LVT i_0_106( + .A(n_0_101), .B1(op2[1]), .B2(n_0_137), .ZN(n_0_100) + ); + OAI21_X1_LVT i_0_105( + .A(n_0_105), .B1(n_0_579), .B2(n_0_100), .ZN(n_0_99) + ); + AOI21_X1_LVT i_0_104( + .A(n_0_118), .B1(n_0_682), .B2(n_0_120), .ZN(n_0_98) + ); + OAI22_X1_LVT i_0_103( + .A1(n_0_547), .A2(n_0_99), .B1(n_0_701), .B2(n_0_98), .ZN(n_0_97) + ); + NAND4_X1_LVT i_0_96( + .A1(n_0_94), .A2(n_0_91), .A3(n_0_95), .A4(n_0_97), .ZN(result[5]) + ); + INV_X1_LVT i_10_26( + .A(n_10_21), .ZN(n_10_22) + ); + NOR2_X1_LVT i_10_28( + .A1(n_10_22), .A2(n_10_23), .ZN(n_10_24) + ); + XNOR2_X1_LVT i_10_29( + .A(n_10_19), .B(n_10_24), .ZN(n_36) + ); + AOI222_X1_LVT i_0_89( + .A1(n_4), .A2(n_0_581), .B1(n_36), .B2(n_0_580), .C1(n_0_668), .C2(n_0_564), + .ZN(n_0_84) + ); + INV_X1_LVT i_0_770( + .A(op1[4]), .ZN(n_0_737) + ); + AOI221_X1_LVT i_0_90( + .A(aluBypass), .B1(op2[4]), .B2(n_0_567), .C1(n_0_738), .C2(n_0_569), .ZN(n_0_85) + ); + OAI21_X1_LVT i_0_88( + .A(n_0_84), .B1(n_0_737), .B2(n_0_85), .ZN(n_0_83) + ); + NOR2_X1_LVT i_0_689( + .A1(op2[4]), .A2(n_0_737), .ZN(n_0_656) + ); + AOI21_X1_LVT i_0_95( + .A(n_0_616), .B1(n_0_727), .B2(n_0_723), .ZN(n_0_90) + ); + OAI22_X1_LVT i_0_94( + .A1(n_0_723), .A2(n_0_216), .B1(n_0_656), .B2(n_0_90), .ZN(n_0_89) + ); + INV_X1_LVT i_0_93( + .A(n_0_89), .ZN(n_0_88) + ); + OAI22_X1_LVT i_0_92( + .A1(op2[2]), .A2(n_0_88), .B1(n_0_693), .B2(n_0_157), .ZN(n_0_87) + ); + OAI221_X1_LVT i_0_91( + .A(n_0_105), .B1(n_0_728), .B2(n_0_122), .C1(op2[1]), .C2(n_0_87), .ZN(n_0_86) + ); + AOI221_X1_LVT i_0_85( + .A(n_0_83), .B1(n_0_561), .B2(n_0_86), .C1(op2[0]), .C2(n_0_99), .ZN(n_0_80) + ); + AOI221_X1_LVT i_0_87( + .A(n_0_574), .B1(n_0_729), .B2(op2[1]), .C1(n_0_728), .C2(n_0_724), .ZN(n_0_82) + ); + OAI22_X1_LVT i_0_86( + .A1(op2[0]), .A2(n_0_96), .B1(n_0_701), .B2(n_0_82), .ZN(n_0_81) + ); + OAI21_X1_LVT i_0_84( + .A(n_0_80), .B1(n_0_621), .B2(n_0_81), .ZN(result[4]) + ); + AND2_X1_LVT i_0_81( + .A1(op2[1]), .A2(n_0_105), .ZN(n_0_77) + ); + NAND2_X1_LVT i_0_80( + .A1(n_0_102), .A2(n_0_77), .ZN(n_0_76) + ); + OAI221_X1_LVT i_0_83( + .A(n_0_693), .B1(n_0_654), .B2(n_0_484), .C1(n_0_738), .C2(n_0_350), .ZN(n_0_79) + ); + OAI21_X1_LVT i_0_82( + .A(n_0_79), .B1(n_0_693), .B2(n_0_138), .ZN(n_0_78) + ); + OAI21_X1_LVT i_0_79( + .A(n_0_76), .B1(op2[1]), .B2(n_0_78), .ZN(n_0_75) + ); + NOR2_X1_LVT i_0_78( + .A1(n_0_562), .A2(n_0_75), .ZN(n_0_74) + ); + NAND2_X1_LVT i_10_20( + .A1(n_10_15), .A2(n_10_16), .ZN(n_10_17) + ); + XNOR2_X1_LVT i_10_21( + .A(n_10_13), .B(n_10_17), .ZN(n_35) + ); + AOI22_X1_LVT i_0_75( + .A1(n_35), .A2(n_0_580), .B1(n_3), .B2(n_0_581), .ZN(n_0_71) + ); + OAI21_X1_LVT i_0_74( + .A(n_0_681), .B1(n_0_723), .B2(n_0_566), .ZN(n_0_70) + ); + AOI222_X1_LVT i_0_73( + .A1(n_0_654), .A2(n_0_569), .B1(n_0_663), .B2(n_0_564), .C1(op1[3]), .C2(n_0_70), + .ZN(n_0_69) + ); + INV_X1_LVT i_0_736( + .A(op1[0]), .ZN(n_0_703) + ); + OAI22_X1_LVT i_0_77( + .A1(n_0_703), .A2(n_0_531), .B1(n_0_694), .B2(n_0_572), .ZN(n_0_73) + ); + OAI22_X1_LVT i_0_76( + .A1(n_0_701), .A2(n_0_73), .B1(op2[0]), .B2(n_0_82), .ZN(n_0_72) + ); + OAI211_X1_LVT i_0_72( + .A(n_0_71), .B(n_0_69), .C1(n_0_621), .C2(n_0_72), .ZN(n_0_68) + ); + AOI211_X1_LVT i_0_71( + .A(n_0_74), .B(n_0_68), .C1(n_0_547), .C2(n_0_86), .ZN(n_0_67) + ); + INV_X1_LVT i_0_70( + .A(n_0_67), .ZN(result[3]) + ); + NAND2_X1_LVT i_0_65( + .A1(n_2), .A2(n_0_581), .ZN(n_0_62) + ); + OAI221_X1_LVT i_0_66( + .A(op2[2]), .B1(op1[2]), .B2(n_0_564), .C1(n_0_694), .C2(n_0_567), .ZN(n_0_63) + ); + AOI21_X1_LVT i_0_64( + .A(aluBypass), .B1(n_0_693), .B2(n_0_569), .ZN(n_0_61) + ); + OAI21_X1_LVT i_0_63( + .A(n_0_63), .B1(n_0_694), .B2(n_0_61), .ZN(n_0_60) + ); + INV_X1_LVT i_10_13( + .A(n_10_10), .ZN(n_10_11) + ); + NOR2_X1_LVT i_10_14( + .A1(n_10_9), .A2(n_10_11), .ZN(n_10_12) + ); + XNOR2_X1_LVT i_10_15( + .A(n_10_7), .B(n_10_12), .ZN(n_34) + ); + AOI21_X1_LVT i_0_62( + .A(n_0_60), .B1(n_34), .B2(n_0_580), .ZN(n_0_59) + ); + OAI211_X1_LVT i_0_57( + .A(n_0_62), .B(n_0_59), .C1(n_0_548), .C2(n_0_75), .ZN(n_0_54) + ); + NOR2_X1_LVT i_0_698( + .A1(n_0_729), .A2(op2[1]), .ZN(n_0_665) + ); + INV_X1_LVT i_0_697( + .A(n_0_665), .ZN(n_0_664) + ); + OAI21_X1_LVT i_0_69( + .A(op2[0]), .B1(n_0_664), .B2(n_0_574), .ZN(n_0_66) + ); + OAI21_X1_LVT i_0_68( + .A(n_0_620), .B1(op2[0]), .B2(n_0_73), .ZN(n_0_65) + ); + INV_X1_LVT i_0_67( + .A(n_0_65), .ZN(n_0_64) + ); + OAI222_X1_LVT i_0_61( + .A1(op1[10]), .A2(n_0_617), .B1(op1[2]), .B2(n_0_615), .C1(n_0_738), .C2(n_0_332), + .ZN(n_0_58) + ); + OAI22_X1_LVT i_0_60( + .A1(op2[2]), .A2(n_0_58), .B1(n_0_693), .B2(n_0_124), .ZN(n_0_57) + ); + INV_X1_LVT i_0_59( + .A(n_0_57), .ZN(n_0_56) + ); + AOI22_X1_LVT i_0_58( + .A1(n_0_728), .A2(n_0_56), .B1(n_0_87), .B2(n_0_77), .ZN(n_0_55) + ); + AOI221_X1_LVT i_0_56( + .A(n_0_54), .B1(n_0_66), .B2(n_0_64), .C1(n_0_561), .C2(n_0_55), .ZN(n_0_53) + ); + INV_X1_LVT i_0_55( + .A(n_0_53), .ZN(result[2]) + ); + NAND2_X1_LVT i_0_54( + .A1(n_0_547), .A2(n_0_55), .ZN(n_0_52) + ); + AOI221_X1_LVT i_0_47( + .A(n_0_728), .B1(n_0_729), .B2(n_0_565), .C1(op1[1]), .C2(n_0_566), .ZN(n_0_45) + ); + NOR2_X1_LVT i_0_700( + .A1(op1[0]), .A2(n_0_701), .ZN(n_0_667) + ); + AOI211_X1_LVT i_0_48( + .A(n_0_667), .B(n_0_621), .C1(n_0_729), .C2(n_0_701), .ZN(n_0_46) + ); + AOI221_X1_LVT i_0_44( + .A(n_0_45), .B1(op1[1]), .B2(aluBypass), .C1(n_0_571), .C2(n_0_46), .ZN(n_0_42) + ); + NAND2_X1_LVT i_10_6( + .A1(n_10_3), .A2(n_10_4), .ZN(n_10_5) + ); + XNOR2_X1_LVT i_10_7( + .A(n_10_5), .B(n_10_1), .ZN(n_33) + ); + AOI22_X1_LVT i_0_49( + .A1(n_33), .A2(n_0_580), .B1(n_1), .B2(n_0_581), .ZN(n_0_47) + ); + OAI21_X1_LVT i_0_46( + .A(n_0_47), .B1(n_0_664), .B2(n_0_568), .ZN(n_0_44) + ); + NAND2_X1_LVT i_0_51( + .A1(op2[1]), .A2(n_0_78), .ZN(n_0_49) + ); + OAI222_X1_LVT i_0_53( + .A1(n_0_722), .A2(n_0_617), .B1(n_0_729), .B2(n_0_615), .C1(n_0_738), .C2(n_0_313), + .ZN(n_0_51) + ); + OAI22_X1_LVT i_0_52( + .A1(n_0_223), .A2(n_0_103), .B1(op2[2]), .B2(n_0_51), .ZN(n_0_50) + ); + OAI21_X1_LVT i_0_50( + .A(n_0_49), .B1(op2[1]), .B2(n_0_50), .ZN(n_0_48) + ); + AOI21_X1_LVT i_0_45( + .A(n_0_44), .B1(n_0_561), .B2(n_0_48), .ZN(n_0_43) + ); + NAND3_X1_LVT i_0_43( + .A1(n_0_52), .A2(n_0_42), .A3(n_0_43), .ZN(result[1]) + ); + OAI222_X1_LVT i_0_11( + .A1(n_0_740), .A2(n_0_617), .B1(n_0_703), .B2(n_0_615), .C1(n_0_738), .C2(n_0_290), + .ZN(n_0_10) + ); + OAI22_X1_LVT i_0_10( + .A1(op2[2]), .A2(n_0_10), .B1(n_0_693), .B2(n_0_88), .ZN(n_0_9) + ); + OAI221_X1_LVT i_0_9( + .A(n_0_701), .B1(n_0_728), .B2(n_0_56), .C1(op2[1]), .C2(n_0_9), .ZN(n_0_8) + ); + OAI21_X1_LVT i_0_8( + .A(n_0_8), .B1(n_0_701), .B2(n_0_48), .ZN(n_0_7) + ); + NOR2_X1_LVT i_0_7( + .A1(n_0_579), .A2(n_0_7), .ZN(n_0_6) + ); + OAI221_X1_LVT i_0_3( + .A(op2[0]), .B1(op1[0]), .B2(n_0_564), .C1(n_0_703), .C2(n_0_567), .ZN(n_0_2) + ); + OAI21_X1_LVT i_10_2( + .A(n_10_1), .B1(n_10_0), .B2(op2[0]), .ZN(n_32) + ); + AOI22_X1_LVT i_0_2( + .A1(n_32), .A2(n_0_580), .B1(n_0), .B2(n_0_581), .ZN(n_0_1) + ); + NAND3_X1_LVT i_0_6( + .A1(n_0_701), .A2(n_0_571), .A3(n_0_620), .ZN(n_0_5) + ); + OAI211_X1_LVT i_0_5( + .A(n_0_681), .B(n_0_5), .C1(op2[0]), .C2(n_0_568), .ZN(n_0_4) + ); + NAND2_X1_LVT i_0_4( + .A1(op1[0]), .A2(n_0_4), .ZN(n_0_3) + ); + NAND3_X1_LVT i_0_1( + .A1(n_0_2), .A2(n_0_1), .A3(n_0_3), .ZN(n_0_0) + ); + OAI33_X1_LVT i_0_14( + .A1(n_0_692), .A2(op1[31]), .A3(n_0_683), .B1(op2[31]), .B2(n_0_691), .B3(aluOp[0]), + .ZN(n_0_13) + ); + INV_X1_LVT i_0_741( + .A(op2[29]), .ZN(n_0_708) + ); + NAND2_X1_LVT i_0_685( + .A1(op1[29]), .A2(n_0_708), .ZN(n_0_652) + ); + OAI22_X1_LVT i_0_713( + .A1(n_0_700), .A2(op1[28]), .B1(op1[29]), .B2(n_0_708), .ZN(n_0_680) + ); + NAND2_X1_LVT i_0_694( + .A1(n_0_688), .A2(op2[27]), .ZN(n_0_661) + ); + INV_X1_LVT i_0_742( + .A(op2[26]), .ZN(n_0_709) + ); + OAI22_X1_LVT i_0_712( + .A1(n_0_699), .A2(op2[25]), .B1(n_0_736), .B2(op2[24]), .ZN(n_0_679) + ); + NAND2_X1_LVT i_0_690( + .A1(n_0_727), .A2(op2[20]), .ZN(n_0_657) + ); + INV_X1_LVT i_0_740( + .A(op2[18]), .ZN(n_0_707) + ); + OAI22_X1_LVT i_0_711( + .A1(n_0_707), .A2(op1[18]), .B1(n_0_690), .B2(op1[19]), .ZN(n_0_678) + ); + OAI22_X1_LVT i_0_29( + .A1(n_0_739), .A2(op2[16]), .B1(n_0_734), .B2(op2[15]), .ZN(n_0_28) + ); + INV_X1_LVT i_0_728( + .A(op2[12]), .ZN(n_0_695) + ); + INV_X1_LVT i_0_748( + .A(op2[13]), .ZN(n_0_715) + ); + OAI22_X1_LVT i_0_704( + .A1(n_0_706), .A2(op2[11]), .B1(n_0_696), .B2(op2[12]), .ZN(n_0_671) + ); + AOI22_X1_LVT i_0_710( + .A1(n_0_740), .A2(op2[8]), .B1(n_0_713), .B2(op2[7]), .ZN(n_0_677) + ); + OAI22_X1_LVT i_0_707( + .A1(n_0_731), .A2(op1[5]), .B1(op1[6]), .B2(n_0_702), .ZN(n_0_674) + ); + OAI22_X1_LVT i_0_706( + .A1(op1[2]), .A2(n_0_693), .B1(op1[1]), .B2(n_0_728), .ZN(n_0_673) + ); + INV_X1_LVT i_0_705( + .A(n_0_673), .ZN(n_0_672) + ); + INV_X1_LVT i_0_699( + .A(n_0_667), .ZN(n_0_666) + ); + OAI21_X1_LVT i_0_42( + .A(n_0_672), .B1(n_0_666), .B2(n_0_665), .ZN(n_0_41) + ); + AOI21_X1_LVT i_0_41( + .A(n_0_654), .B1(op1[2]), .B2(n_0_693), .ZN(n_0_40) + ); + AOI211_X1_LVT i_0_40( + .A(n_0_668), .B(n_0_663), .C1(n_0_41), .C2(n_0_40), .ZN(n_0_39) + ); + AOI211_X1_LVT i_0_39( + .A(n_0_656), .B(n_0_39), .C1(n_0_731), .C2(op1[5]), .ZN(n_0_38) + ); + OAI222_X1_LVT i_0_38( + .A1(n_0_704), .A2(op2[6]), .B1(n_0_674), .B2(n_0_38), .C1(n_0_713), .C2(op2[7]), + .ZN(n_0_37) + ); + AOI221_X1_LVT i_0_37( + .A(n_0_655), .B1(op1[9]), .B2(n_0_720), .C1(n_0_677), .C2(n_0_37), .ZN(n_0_36) + ); + INV_X1_LVT i_0_768( + .A(op2[10]), .ZN(n_0_735) + ); + OAI22_X1_LVT i_0_36( + .A1(n_0_735), .A2(op1[10]), .B1(op1[9]), .B2(n_0_720), .ZN(n_0_35) + ); + OAI22_X1_LVT i_0_35( + .A1(op2[10]), .A2(n_0_733), .B1(n_0_36), .B2(n_0_35), .ZN(n_0_34) + ); + INV_X1_LVT i_0_34( + .A(n_0_34), .ZN(n_0_33) + ); + AOI21_X1_LVT i_0_33( + .A(n_0_33), .B1(n_0_706), .B2(op2[11]), .ZN(n_0_32) + ); + OAI222_X1_LVT i_0_32( + .A1(op1[12]), .A2(n_0_695), .B1(n_0_715), .B2(op1[13]), .C1(n_0_671), .C2(n_0_32), + .ZN(n_0_31) + ); + OAI221_X1_LVT i_0_31( + .A(n_0_31), .B1(n_0_721), .B2(op2[14]), .C1(op2[13]), .C2(n_0_714), .ZN(n_0_30) + ); + AOI22_X1_LVT i_0_30( + .A1(n_0_734), .A2(op2[15]), .B1(n_0_721), .B2(op2[14]), .ZN(n_0_29) + ); + AOI21_X1_LVT i_0_28( + .A(n_0_28), .B1(n_0_30), .B2(n_0_29), .ZN(n_0_27) + ); + AOI221_X1_LVT i_0_27( + .A(n_0_27), .B1(n_0_732), .B2(op2[17]), .C1(n_0_739), .C2(op2[16]), .ZN(n_0_26) + ); + AOI211_X1_LVT i_0_26( + .A(n_0_660), .B(n_0_26), .C1(n_0_707), .C2(op1[18]), .ZN(n_0_25) + ); + OAI22_X1_LVT i_0_25( + .A1(op2[19]), .A2(n_0_689), .B1(n_0_678), .B2(n_0_25), .ZN(n_0_24) + ); + AOI211_X1_LVT i_0_24( + .A(n_0_658), .B(n_0_659), .C1(n_0_657), .C2(n_0_24), .ZN(n_0_23) + ); + AOI221_X1_LVT i_0_23( + .A(n_0_23), .B1(n_0_726), .B2(op2[21]), .C1(n_0_687), .C2(op2[22]), .ZN(n_0_22) + ); + AOI221_X1_LVT i_0_22( + .A(n_0_22), .B1(op1[22]), .B2(n_0_686), .C1(op1[23]), .C2(n_0_718), .ZN(n_0_21) + ); + AOI221_X1_LVT i_0_21( + .A(n_0_21), .B1(n_0_736), .B2(op2[24]), .C1(n_0_719), .C2(op2[23]), .ZN(n_0_20) + ); + OAI222_X1_LVT i_0_20( + .A1(op1[26]), .A2(n_0_709), .B1(op1[25]), .B2(n_0_697), .C1(n_0_679), .C2(n_0_20), + .ZN(n_0_19) + ); + OAI221_X1_LVT i_0_19( + .A(n_0_19), .B1(n_0_711), .B2(op2[26]), .C1(n_0_688), .C2(op2[27]), .ZN(n_0_18) + ); + AOI22_X1_LVT i_0_18( + .A1(n_0_700), .A2(op1[28]), .B1(n_0_661), .B2(n_0_18), .ZN(n_0_17) + ); + OAI21_X1_LVT i_0_17( + .A(n_0_652), .B1(n_0_680), .B2(n_0_17), .ZN(n_0_16) + ); + INV_X1_LVT i_0_749( + .A(op2[30]), .ZN(n_0_716) + ); + OAI21_X1_LVT i_0_16( + .A(n_0_16), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_15) + ); + OAI22_X1_LVT i_0_708( + .A1(n_0_692), .A2(op1[31]), .B1(op2[31]), .B2(n_0_691), .ZN(n_0_675) + ); + AOI21_X1_LVT i_0_15( + .A(n_0_675), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_14) + ); + AOI21_X1_LVT i_0_13( + .A(n_0_13), .B1(n_0_15), .B2(n_0_14), .ZN(n_0_12) + ); + NOR4_X1_LVT i_0_12( + .A1(n_0_685), .A2(aluOp[2]), .A3(aluBypass), .A4(n_0_12), .ZN(n_0_11) + ); + OR3_X1_LVT i_0_0( + .A1(n_0_6), .A2(n_0_0), .A3(n_0_11), .ZN(result[0]) + ); + OR4_X1_LVT i_0_703( + .A1(n_0_680), .A2(n_0_673), .A3(n_0_675), .A4(n_0_678), .ZN(n_0_670) + ); + INV_X1_LVT i_0_709( + .A(n_0_677), .ZN(n_0_676) + ); + OR4_X1_LVT i_0_702( + .A1(n_0_679), .A2(n_0_674), .A3(n_0_676), .A4(n_0_671), .ZN(n_0_669) + ); + AOI22_X1_LVT i_0_663( + .A1(n_0_688), .A2(op2[27]), .B1(op1[22]), .B2(n_0_686), .ZN(n_0_630) + ); + OAI22_X1_LVT i_0_662( + .A1(n_0_694), .A2(op2[2]), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_629) + ); + AOI221_X1_LVT i_0_661( + .A(n_0_629), .B1(n_0_711), .B2(op2[26]), .C1(n_0_721), .C2(op2[14]), .ZN(n_0_628) + ); + AOI21_X1_LVT i_0_664( + .A(n_0_660), .B1(n_0_690), .B2(op1[19]), .ZN(n_0_631) + ); + OAI222_X1_LVT i_0_660( + .A1(op1[12]), .A2(n_0_695), .B1(n_0_688), .B2(op2[27]), .C1(op1[22]), .C2(n_0_686), + .ZN(n_0_627) + ); + AOI21_X1_LVT i_0_659( + .A(n_0_663), .B1(n_0_734), .B2(op2[15]), .ZN(n_0_626) + ); + OAI211_X1_LVT i_0_658( + .A(n_0_666), .B(n_0_626), .C1(n_0_715), .C2(op1[13]), .ZN(n_0_625) + ); + AOI211_X1_LVT i_0_657( + .A(n_0_627), .B(n_0_625), .C1(op1[23]), .C2(n_0_718), .ZN(n_0_624) + ); + NAND4_X1_LVT i_0_656( + .A1(n_0_630), .A2(n_0_628), .A3(n_0_631), .A4(n_0_624), .ZN(n_0_623) + ); + OAI22_X1_LVT i_0_684( + .A1(n_0_721), .A2(op2[14]), .B1(n_0_722), .B2(op2[9]), .ZN(n_0_651) + ); + AOI211_X1_LVT i_0_668( + .A(n_0_651), .B(n_0_654), .C1(n_0_719), .C2(op2[23]), .ZN(n_0_635) + ); + NAND2_X1_LVT i_0_667( + .A1(n_0_664), .A2(n_0_657), .ZN(n_0_634) + ); + NOR3_X1_LVT i_0_666( + .A1(n_0_659), .A2(n_0_656), .A3(n_0_634), .ZN(n_0_633) + ); + AOI21_X1_LVT i_0_671( + .A(n_0_655), .B1(n_0_739), .B2(op2[16]), .ZN(n_0_638) + ); + AOI21_X1_LVT i_0_670( + .A(n_0_668), .B1(n_0_736), .B2(op2[24]), .ZN(n_0_637) + ); + OAI22_X1_LVT i_0_673( + .A1(n_0_735), .A2(op1[10]), .B1(n_0_734), .B2(op2[15]), .ZN(n_0_640) + ); + AOI221_X1_LVT i_0_672( + .A(n_0_640), .B1(n_0_732), .B2(op2[17]), .C1(n_0_731), .C2(op1[5]), .ZN(n_0_639) + ); + AND3_X1_LVT i_0_669( + .A1(n_0_638), .A2(n_0_637), .A3(n_0_639), .ZN(n_0_636) + ); + OAI22_X1_LVT i_0_682( + .A1(n_0_703), .A2(op2[0]), .B1(n_0_704), .B2(op2[6]), .ZN(n_0_649) + ); + OAI22_X1_LVT i_0_681( + .A1(op2[28]), .A2(n_0_698), .B1(op1[25]), .B2(n_0_697), .ZN(n_0_648) + ); + AOI21_X1_LVT i_0_678( + .A(n_0_658), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_645) + ); + AOI21_X1_LVT i_0_677( + .A(n_0_662), .B1(n_0_735), .B2(op1[10]), .ZN(n_0_644) + ); + INV_X1_LVT i_0_758( + .A(op2[21]), .ZN(n_0_725) + ); + OAI22_X1_LVT i_0_683( + .A1(op1[21]), .A2(n_0_725), .B1(n_0_739), .B2(op2[16]), .ZN(n_0_650) + ); + AOI221_X1_LVT i_0_676( + .A(n_0_650), .B1(n_0_722), .B2(op2[9]), .C1(op1[7]), .C2(n_0_712), .ZN(n_0_643) + ); + OAI21_X1_LVT i_0_680( + .A(n_0_652), .B1(n_0_711), .B2(op2[26]), .ZN(n_0_647) + ); + AOI221_X1_LVT i_0_679( + .A(n_0_647), .B1(n_0_706), .B2(op2[11]), .C1(n_0_707), .C2(op1[18]), .ZN(n_0_646) + ); + NAND4_X1_LVT i_0_675( + .A1(n_0_645), .A2(n_0_644), .A3(n_0_643), .A4(n_0_646), .ZN(n_0_642) + ); + NOR3_X1_LVT i_0_674( + .A1(n_0_649), .A2(n_0_648), .A3(n_0_642), .ZN(n_0_641) + ); + NAND4_X1_LVT i_0_665( + .A1(n_0_635), .A2(n_0_633), .A3(n_0_636), .A4(n_0_641), .ZN(n_0_632) + ); + NOR4_X1_LVT i_0_655( + .A1(n_0_670), .A2(n_0_669), .A3(n_0_623), .A4(n_0_632), .ZN(eqFlag) + ); +endmodule + +module decoder(CurrentPC, JumpOrBranchPC, JumpOrBranch, DAddr, WData, RData, Instruction, + WrMem, DWidth, Rs1, Rs2, Rd, RRs1, RRs2, WRd, WrReg, Illegal); + input [31:0] CurrentPC, RData, Instruction, RRs1, RRs2; + output [31:0] JumpOrBranchPC, DAddr, WData, WRd; + output [4:0] Rs1, Rs2, Rd; + output [1:0] DWidth; + output JumpOrBranch, WrMem, WrReg, Illegal; + + wire [31:0] op1, op2; + wire [2:0] aluOp; + wire eqFlag, n_5_0, n_5_1, n_5_2, n_5_3, n_5_4, n_5_5, n_5_6, n_5_7, n_5_8, + n_5_9, n_5_10, n_5_11, n_5_12, n_5_13, n_5_14, n_5_15, n_5_16, n_5_17, + n_5_18, n_5_19, n_5_20, n_5_21, n_5_22, n_5_23, n_5_24, n_5_25, n_5_26, + n_5_27, n_5_28, n_5_29, n_5_30, n_5_31, n_5_32, n_5_33, n_17_0, n_17_1, + n_17_2, n_17_3, n_17_4, n_17_5, n_17_6, n_17_7, n_17_8, n_17_9, n_17_10, + n_17_11, n_17_12, n_17_13, n_17_14, n_17_15, n_17_16, n_17_17, n_17_18, + n_17_19, n_17_20, n_17_21, n_17_22, n_17_23, n_17_24, n_17_25, n_17_26, + n_17_27, n_17_28, n_17_29, n_17_30, n_17_31, n_17_32, n_18_0, n_18_1, + n_18_2, n_18_3, n_18_4, n_18_5, n_18_6, n_18_7, n_18_8, n_18_9, n_18_10, + n_18_11, n_18_12, n_18_13, n_18_14, n_18_15, n_18_16, n_18_17, n_18_18, + n_18_19, n_18_20, n_18_21, n_18_22, n_18_23, n_18_24, n_18_25, n_18_26, + n_18_27, n_18_28, n_18_29, n_18_30, n_18_31, n_18_32, n_0_15, n_0_2, + n_0_16, n_0_3, n_0_17, n_0_4, n_0_18, n_0_5, n_0_19, n_0_6, n_0_20, + n_0_7, n_0_21, n_0_8, n_0_22, n_0_9, n_0_23, n_0_10, n_0_24, n_0_11, + n_0_25, n_0_12, n_0_26, n_0_13, n_0_27, n_0_14, n_0_28, n_0_29, n_0_30, + n_0_31, n_0_32, n_0_33, n_0_34, n_0_35, n_0_36, n_0_37, n_0_38, n_0_39, + n_0_40, n_0_41, n_0_42, n_0_43, n_0_44, n_0_45, n_0_46, n_0_47, n_0_48, + n_0_49, n_0_50, n_0_51, n_0_52, n_0_53, n_0_54, n_0_55, n_0_56, n_0_57, + n_0_58, n_0_59, n_0_60, n_0_61, n_0_62, n_0_63, n_0_64, n_0_65, n_0_66, + n_0_67, n_0_68, n_0_69, n_0_70, n_0_71, n_0_72, n_0_73, n_0_74, n_0_75, + n_0_76, n_0_77, n_0_78, n_0_79, n_0_80, n_0_81, n_0_82, n_0_83, n_0_84, + n_0_85, n_0_86, n_0_87, n_0_88, n_0_89, n_0_90, n_0_91, n_0_92, n_0_93, + n_0_94, n_0_95, n_0_96, n_0_97, n_0_98, n_0_99, n_0_100, aluNegAr, + n_0_101, n_0_102, n_0_103, n_0_104, n_0_105, aluBypass, n_0_106, + n_0_107, n_0_108, n_0_109, n_0_110, n_0_111, n_0_112, n_0_113, n_0_114, + n_0_115, n_0_116, n_0_117, n_0_118, n_0_119, n_0_120, n_0_121, n_0_122, + n_0_123, n_0_124, n_0_125, n_0_126, n_0_127, n_0_128, n_0_129, n_0_130, + n_0_131, n_0_132, n_0_133, n_0_134, n_0_135, n_0_136, n_0_137, n_0_138, + n_0_139, n_0_140, n_0_141, n_0_142, n_0_143, n_0_144, n_0_145, n_0_146, + n_0_147, n_0_148, n_0_149, n_0_150, n_0_151, n_0_152, n_0_153, n_0_154, + n_0_155, n_0_156, n_0_157, n_0_158, n_0_159, n_0_160, n_0_161, n_0_162, + n_0_163, n_0_164, n_0_165, n_0_166, n_0_167, n_0_168, n_0_169, n_0_170, + n_0_171, n_0_172, n_0_173, n_0_174, n_0_175, n_0_176, n_0_177, n_0_178, + n_0_179, n_0_180, n_0_181, n_0_182, n_0_183, n_0_184, n_0_185, n_0_186, + n_0_187, n_0_188, n_0_189, n_0_190, n_0_191, n_0_192, n_0_193, n_0_194, + n_0_195, n_0_196, n_0_197, n_0_198, n_0_199, n_0_200, n_0_201, n_0_202, + n_0_203, n_0_204, n_0_205, n_0_206, n_0_207, n_0_208, n_0_209, n_0_210, + n_0_211, n_0_212, n_0_213, n_0_214, n_0_215, n_0_216, n_0_217, n_0_218, + n_0_219, n_0_220, n_0_221, n_0_222, n_0_223, n_0_224, n_0_225, n_0_226, + n_0_227, n_0_228, n_0_229, n_0_230, n_0_231, n_0_232, n_0_233, n_0_234, + n_0_235, n_0_236, n_0_237, n_0_238, n_0_239, n_0_240, n_0_241, n_0_242, + n_0_1, n_0_0, n_0_243, n_0_244, n_0_245, n_0_246, n_0_247, n_0_248, + n_0_249, n_63, n_64, n_65, n_66, n_67, n_68, n_69, n_70, n_71, n_72, + n_73, n_74, n_75, n_76, n_77, n_78, n_79, n_80, n_81, n_82, n_83, n_84, + n_85, n_86, n_87, n_88, n_89, n_90, n_91, n_92, n_93, n_32, n_33, n_34, + n_35, n_36, n_37, n_38, n_39, n_40, n_41, n_42, n_43, n_44, n_45, n_46, + n_47, n_48, n_49, n_50, n_51, n_52, n_53, n_54, n_55, n_56, n_57, n_58, + n_59, n_60, n_61, n_62, n_0, n_1, n_2, n_3, n_4, n_5, n_6, n_7, n_8, + n_9, n_10, n_11, n_12, n_13, n_14, n_15, n_16, n_17, n_18, n_19, n_20, + n_21, n_22, n_23, n_24, n_25, n_26, n_27, n_28, n_29, n_30, n_31; + + INV_X1_LVT i_18_1( + .A(CurrentPC[13]), .ZN(n_18_1) + ); + XNOR2_X1_LVT i_18_32( + .A(CurrentPC[31]), .B(n_18_1), .ZN(n_18_32) + ); + INV_X1_LVT i_18_0( + .A(Instruction[31]), .ZN(n_18_0) + ); + HA_X1_LVT i_18_2( + .A(Instruction[8]), .B(CurrentPC[1]), .CO(n_18_2), .S(n_63) + ); + FA_X1_LVT i_18_3( + .A(Instruction[9]), .B(CurrentPC[2]), .CI(n_18_2), .CO(n_18_3), .S(n_64) + ); + FA_X1_LVT i_18_4( + .A(Instruction[10]), .B(CurrentPC[3]), .CI(n_18_3), .CO(n_18_4), .S(n_65) + ); + FA_X1_LVT i_18_5( + .A(Instruction[11]), .B(CurrentPC[4]), .CI(n_18_4), .CO(n_18_5), .S(n_66) + ); + FA_X1_LVT i_18_6( + .A(Instruction[25]), .B(CurrentPC[5]), .CI(n_18_5), .CO(n_18_6), .S(n_67) + ); + FA_X1_LVT i_18_7( + .A(Instruction[26]), .B(CurrentPC[6]), .CI(n_18_6), .CO(n_18_7), .S(n_68) + ); + FA_X1_LVT i_18_8( + .A(Instruction[27]), .B(CurrentPC[7]), .CI(n_18_7), .CO(n_18_8), .S(n_69) + ); + FA_X1_LVT i_18_9( + .A(Instruction[28]), .B(CurrentPC[8]), .CI(n_18_8), .CO(n_18_9), .S(n_70) + ); + FA_X1_LVT i_18_10( + .A(Instruction[29]), .B(CurrentPC[9]), .CI(n_18_9), .CO(n_18_10), .S(n_71) + ); + FA_X1_LVT i_18_11( + .A(Instruction[30]), .B(CurrentPC[10]), .CI(n_18_10), .CO(n_18_11), .S(n_72) + ); + FA_X1_LVT i_18_12( + .A(Instruction[7]), .B(CurrentPC[11]), .CI(n_18_11), .CO(n_18_12), .S(n_73) + ); + FA_X1_LVT i_18_13( + .A(CurrentPC[12]), .B(Instruction[31]), .CI(n_18_12), .CO(n_18_13), .S(n_74) + ); + FA_X1_LVT i_18_14( + .A(n_18_0), .B(n_18_1), .CI(n_18_13), .CO(n_18_14), .S(n_75) + ); + FA_X1_LVT i_18_15( + .A(CurrentPC[14]), .B(n_18_1), .CI(n_18_14), .CO(n_18_15), .S(n_76) + ); + FA_X1_LVT i_18_16( + .A(CurrentPC[15]), .B(n_18_1), .CI(n_18_15), .CO(n_18_16), .S(n_77) + ); + FA_X1_LVT i_18_17( + .A(CurrentPC[16]), .B(n_18_1), .CI(n_18_16), .CO(n_18_17), .S(n_78) + ); + FA_X1_LVT i_18_18( + .A(CurrentPC[17]), .B(n_18_1), .CI(n_18_17), .CO(n_18_18), .S(n_79) + ); + FA_X1_LVT i_18_19( + .A(CurrentPC[18]), .B(n_18_1), .CI(n_18_18), .CO(n_18_19), .S(n_80) + ); + FA_X1_LVT i_18_20( + .A(CurrentPC[19]), .B(n_18_1), .CI(n_18_19), .CO(n_18_20), .S(n_81) + ); + FA_X1_LVT i_18_21( + .A(CurrentPC[20]), .B(n_18_1), .CI(n_18_20), .CO(n_18_21), .S(n_82) + ); + FA_X1_LVT i_18_22( + .A(CurrentPC[21]), .B(n_18_1), .CI(n_18_21), .CO(n_18_22), .S(n_83) + ); + FA_X1_LVT i_18_23( + .A(CurrentPC[22]), .B(n_18_1), .CI(n_18_22), .CO(n_18_23), .S(n_84) + ); + FA_X1_LVT i_18_24( + .A(CurrentPC[23]), .B(n_18_1), .CI(n_18_23), .CO(n_18_24), .S(n_85) + ); + FA_X1_LVT i_18_25( + .A(CurrentPC[24]), .B(n_18_1), .CI(n_18_24), .CO(n_18_25), .S(n_86) + ); + FA_X1_LVT i_18_26( + .A(CurrentPC[25]), .B(n_18_1), .CI(n_18_25), .CO(n_18_26), .S(n_87) + ); + FA_X1_LVT i_18_27( + .A(CurrentPC[26]), .B(n_18_1), .CI(n_18_26), .CO(n_18_27), .S(n_88) + ); + FA_X1_LVT i_18_28( + .A(CurrentPC[27]), .B(n_18_1), .CI(n_18_27), .CO(n_18_28), .S(n_89) + ); + FA_X1_LVT i_18_29( + .A(CurrentPC[28]), .B(n_18_1), .CI(n_18_28), .CO(n_18_29), .S(n_90) + ); + FA_X1_LVT i_18_30( + .A(CurrentPC[29]), .B(n_18_1), .CI(n_18_29), .CO(n_18_30), .S(n_91) + ); + FA_X1_LVT i_18_31( + .A(CurrentPC[30]), .B(n_18_1), .CI(n_18_30), .CO(n_18_31), .S(n_92) + ); + XNOR2_X1_LVT i_18_33( + .A(n_18_32), .B(n_18_31), .ZN(n_93) + ); + INV_X1_LVT i_0_350( + .A(Instruction[3]), .ZN(n_0_243) + ); + NAND3_X1_LVT i_0_343( + .A1(n_0_243), .A2(Instruction[0]), .A3(Instruction[1]), .ZN(n_0_238) + ); + OR2_X1_LVT i_0_332( + .A1(n_0_238), .A2(Instruction[2]), .ZN(n_0_228) + ); + INV_X1_LVT i_0_351( + .A(Instruction[5]), .ZN(n_0_244) + ); + NOR2_X1_LVT i_0_340( + .A1(n_0_244), .A2(Instruction[4]), .ZN(n_0_235) + ); + NAND2_X1_LVT i_0_329( + .A1(Instruction[6]), .A2(n_0_235), .ZN(n_0_225) + ); + INV_X1_LVT i_0_354( + .A(Instruction[13]), .ZN(n_0_247) + ); + NOR2_X1_LVT i_0_345( + .A1(n_0_247), .A2(Instruction[14]), .ZN(n_0_240) + ); + NOR3_X1_LVT i_0_118( + .A1(n_0_228), .A2(n_0_225), .A3(n_0_240), .ZN(n_0_99) + ); + NAND3_X1_LVT i_0_346( + .A1(Instruction[0]), .A2(Instruction[1]), .A3(Instruction[2]), .ZN(n_0_241) + ); + NOR2_X1_LVT i_0_328( + .A1(n_0_241), .A2(n_0_225), .ZN(n_0_224) + ); + INV_X1_LVT i_0_356( + .A(n_0_224), .ZN(n_0_249) + ); + NOR2_X1_LVT i_0_108( + .A1(n_0_243), .A2(n_0_249), .ZN(n_0_91) + ); + INV_X1_LVT i_17_1( + .A(CurrentPC[21]), .ZN(n_17_1) + ); + XNOR2_X1_LVT i_17_32( + .A(CurrentPC[31]), .B(n_17_1), .ZN(n_17_32) + ); + INV_X1_LVT i_17_0( + .A(Instruction[31]), .ZN(n_17_0) + ); + HA_X1_LVT i_17_2( + .A(Instruction[21]), .B(CurrentPC[1]), .CO(n_17_2), .S(n_32) + ); + FA_X1_LVT i_17_3( + .A(Instruction[22]), .B(CurrentPC[2]), .CI(n_17_2), .CO(n_17_3), .S(n_33) + ); + FA_X1_LVT i_17_4( + .A(Instruction[23]), .B(CurrentPC[3]), .CI(n_17_3), .CO(n_17_4), .S(n_34) + ); + FA_X1_LVT i_17_5( + .A(Instruction[24]), .B(CurrentPC[4]), .CI(n_17_4), .CO(n_17_5), .S(n_35) + ); + FA_X1_LVT i_17_6( + .A(Instruction[25]), .B(CurrentPC[5]), .CI(n_17_5), .CO(n_17_6), .S(n_36) + ); + FA_X1_LVT i_17_7( + .A(Instruction[26]), .B(CurrentPC[6]), .CI(n_17_6), .CO(n_17_7), .S(n_37) + ); + FA_X1_LVT i_17_8( + .A(Instruction[27]), .B(CurrentPC[7]), .CI(n_17_7), .CO(n_17_8), .S(n_38) + ); + FA_X1_LVT i_17_9( + .A(Instruction[28]), .B(CurrentPC[8]), .CI(n_17_8), .CO(n_17_9), .S(n_39) + ); + FA_X1_LVT i_17_10( + .A(Instruction[29]), .B(CurrentPC[9]), .CI(n_17_9), .CO(n_17_10), .S(n_40) + ); + FA_X1_LVT i_17_11( + .A(Instruction[30]), .B(CurrentPC[10]), .CI(n_17_10), .CO(n_17_11), .S(n_41) + ); + FA_X1_LVT i_17_12( + .A(Instruction[20]), .B(CurrentPC[11]), .CI(n_17_11), .CO(n_17_12), .S(n_42) + ); + FA_X1_LVT i_17_13( + .A(Instruction[12]), .B(CurrentPC[12]), .CI(n_17_12), .CO(n_17_13), .S(n_43) + ); + FA_X1_LVT i_17_14( + .A(Instruction[13]), .B(CurrentPC[13]), .CI(n_17_13), .CO(n_17_14), .S(n_44) + ); + FA_X1_LVT i_17_15( + .A(Instruction[14]), .B(CurrentPC[14]), .CI(n_17_14), .CO(n_17_15), .S(n_45) + ); + FA_X1_LVT i_17_16( + .A(Instruction[15]), .B(CurrentPC[15]), .CI(n_17_15), .CO(n_17_16), .S(n_46) + ); + FA_X1_LVT i_17_17( + .A(Instruction[16]), .B(CurrentPC[16]), .CI(n_17_16), .CO(n_17_17), .S(n_47) + ); + FA_X1_LVT i_17_18( + .A(Instruction[17]), .B(CurrentPC[17]), .CI(n_17_17), .CO(n_17_18), .S(n_48) + ); + FA_X1_LVT i_17_19( + .A(Instruction[18]), .B(CurrentPC[18]), .CI(n_17_18), .CO(n_17_19), .S(n_49) + ); + FA_X1_LVT i_17_20( + .A(Instruction[19]), .B(CurrentPC[19]), .CI(n_17_19), .CO(n_17_20), .S(n_50) + ); + FA_X1_LVT i_17_21( + .A(CurrentPC[20]), .B(Instruction[31]), .CI(n_17_20), .CO(n_17_21), .S(n_51) + ); + FA_X1_LVT i_17_22( + .A(n_17_0), .B(n_17_1), .CI(n_17_21), .CO(n_17_22), .S(n_52) + ); + FA_X1_LVT i_17_23( + .A(CurrentPC[22]), .B(n_17_1), .CI(n_17_22), .CO(n_17_23), .S(n_53) + ); + FA_X1_LVT i_17_24( + .A(CurrentPC[23]), .B(n_17_1), .CI(n_17_23), .CO(n_17_24), .S(n_54) + ); + FA_X1_LVT i_17_25( + .A(CurrentPC[24]), .B(n_17_1), .CI(n_17_24), .CO(n_17_25), .S(n_55) + ); + FA_X1_LVT i_17_26( + .A(CurrentPC[25]), .B(n_17_1), .CI(n_17_25), .CO(n_17_26), .S(n_56) + ); + FA_X1_LVT i_17_27( + .A(CurrentPC[26]), .B(n_17_1), .CI(n_17_26), .CO(n_17_27), .S(n_57) + ); + FA_X1_LVT i_17_28( + .A(CurrentPC[27]), .B(n_17_1), .CI(n_17_27), .CO(n_17_28), .S(n_58) + ); + FA_X1_LVT i_17_29( + .A(CurrentPC[28]), .B(n_17_1), .CI(n_17_28), .CO(n_17_29), .S(n_59) + ); + FA_X1_LVT i_17_30( + .A(CurrentPC[29]), .B(n_17_1), .CI(n_17_29), .CO(n_17_30), .S(n_60) + ); + FA_X1_LVT i_17_31( + .A(CurrentPC[30]), .B(n_17_1), .CI(n_17_30), .CO(n_17_31), .S(n_61) + ); + XNOR2_X1_LVT i_17_33( + .A(n_17_32), .B(n_17_31), .ZN(n_62) + ); + INV_X1_LVT i_5_1( + .A(RRs1[12]), .ZN(n_5_1) + ); + XNOR2_X1_LVT i_5_33( + .A(RRs1[31]), .B(n_5_1), .ZN(n_5_33) + ); + INV_X1_LVT i_5_0( + .A(Instruction[31]), .ZN(n_5_0) + ); + HA_X1_LVT i_5_2( + .A(Instruction[20]), .B(RRs1[0]), .CO(n_5_2), .S(n_0) + ); + FA_X1_LVT i_5_3( + .A(Instruction[21]), .B(RRs1[1]), .CI(n_5_2), .CO(n_5_3), .S(n_1) + ); + FA_X1_LVT i_5_4( + .A(Instruction[22]), .B(RRs1[2]), .CI(n_5_3), .CO(n_5_4), .S(n_2) + ); + FA_X1_LVT i_5_5( + .A(Instruction[23]), .B(RRs1[3]), .CI(n_5_4), .CO(n_5_5), .S(n_3) + ); + FA_X1_LVT i_5_6( + .A(Instruction[24]), .B(RRs1[4]), .CI(n_5_5), .CO(n_5_6), .S(n_4) + ); + FA_X1_LVT i_5_7( + .A(Instruction[25]), .B(RRs1[5]), .CI(n_5_6), .CO(n_5_7), .S(n_5) + ); + FA_X1_LVT i_5_8( + .A(Instruction[26]), .B(RRs1[6]), .CI(n_5_7), .CO(n_5_8), .S(n_6) + ); + FA_X1_LVT i_5_9( + .A(Instruction[27]), .B(RRs1[7]), .CI(n_5_8), .CO(n_5_9), .S(n_7) + ); + FA_X1_LVT i_5_10( + .A(Instruction[28]), .B(RRs1[8]), .CI(n_5_9), .CO(n_5_10), .S(n_8) + ); + FA_X1_LVT i_5_11( + .A(Instruction[29]), .B(RRs1[9]), .CI(n_5_10), .CO(n_5_11), .S(n_9) + ); + FA_X1_LVT i_5_12( + .A(Instruction[30]), .B(RRs1[10]), .CI(n_5_11), .CO(n_5_12), .S(n_10) + ); + FA_X1_LVT i_5_13( + .A(RRs1[11]), .B(Instruction[31]), .CI(n_5_12), .CO(n_5_13), .S(n_11) + ); + FA_X1_LVT i_5_14( + .A(n_5_0), .B(n_5_1), .CI(n_5_13), .CO(n_5_14), .S(n_12) + ); + FA_X1_LVT i_5_15( + .A(RRs1[13]), .B(n_5_1), .CI(n_5_14), .CO(n_5_15), .S(n_13) + ); + FA_X1_LVT i_5_16( + .A(RRs1[14]), .B(n_5_1), .CI(n_5_15), .CO(n_5_16), .S(n_14) + ); + FA_X1_LVT i_5_17( + .A(RRs1[15]), .B(n_5_1), .CI(n_5_16), .CO(n_5_17), .S(n_15) + ); + FA_X1_LVT i_5_18( + .A(RRs1[16]), .B(n_5_1), .CI(n_5_17), .CO(n_5_18), .S(n_16) + ); + FA_X1_LVT i_5_19( + .A(RRs1[17]), .B(n_5_1), .CI(n_5_18), .CO(n_5_19), .S(n_17) + ); + FA_X1_LVT i_5_20( + .A(RRs1[18]), .B(n_5_1), .CI(n_5_19), .CO(n_5_20), .S(n_18) + ); + FA_X1_LVT i_5_21( + .A(RRs1[19]), .B(n_5_1), .CI(n_5_20), .CO(n_5_21), .S(n_19) + ); + FA_X1_LVT i_5_22( + .A(RRs1[20]), .B(n_5_1), .CI(n_5_21), .CO(n_5_22), .S(n_20) + ); + FA_X1_LVT i_5_23( + .A(RRs1[21]), .B(n_5_1), .CI(n_5_22), .CO(n_5_23), .S(n_21) + ); + FA_X1_LVT i_5_24( + .A(RRs1[22]), .B(n_5_1), .CI(n_5_23), .CO(n_5_24), .S(n_22) + ); + FA_X1_LVT i_5_25( + .A(RRs1[23]), .B(n_5_1), .CI(n_5_24), .CO(n_5_25), .S(n_23) + ); + FA_X1_LVT i_5_26( + .A(RRs1[24]), .B(n_5_1), .CI(n_5_25), .CO(n_5_26), .S(n_24) + ); + FA_X1_LVT i_5_27( + .A(RRs1[25]), .B(n_5_1), .CI(n_5_26), .CO(n_5_27), .S(n_25) + ); + FA_X1_LVT i_5_28( + .A(RRs1[26]), .B(n_5_1), .CI(n_5_27), .CO(n_5_28), .S(n_26) + ); + FA_X1_LVT i_5_29( + .A(RRs1[27]), .B(n_5_1), .CI(n_5_28), .CO(n_5_29), .S(n_27) + ); + FA_X1_LVT i_5_30( + .A(RRs1[28]), .B(n_5_1), .CI(n_5_29), .CO(n_5_30), .S(n_28) + ); + FA_X1_LVT i_5_31( + .A(RRs1[29]), .B(n_5_1), .CI(n_5_30), .CO(n_5_31), .S(n_29) + ); + FA_X1_LVT i_5_32( + .A(RRs1[30]), .B(n_5_1), .CI(n_5_31), .CO(n_5_32), .S(n_30) + ); + XNOR2_X1_LVT i_5_34( + .A(n_5_33), .B(n_5_32), .ZN(n_31) + ); + NOR2_X1_LVT i_0_107( + .A1(n_0_249), .A2(Instruction[3]), .ZN(n_0_90) + ); + AOI222_X1_LVT i_0_106( + .A1(n_93), .A2(n_0_99), .B1(n_0_91), .B2(n_62), .C1(n_31), .C2(n_0_90), .ZN(n_0_89) + ); + INV_X1_LVT i_0_355( + .A(Instruction[6]), .ZN(n_0_248) + ); + NAND2_X1_LVT i_0_339( + .A1(n_0_248), .A2(Instruction[4]), .ZN(n_0_234) + ); + INV_X1_LVT i_0_338( + .A(n_0_234), .ZN(n_0_233) + ); + OAI21_X1_LVT i_0_341( + .A(Instruction[13]), .B1(Instruction[14]), .B2(Instruction[12]), .ZN(n_0_236) + ); + AOI211_X1_LVT i_0_337( + .A(n_0_235), .B(n_0_233), .C1(n_0_248), .C2(n_0_236), .ZN(n_0_232) + ); + INV_X1_LVT i_0_352( + .A(Instruction[4]), .ZN(n_0_245) + ); + NAND2_X1_LVT i_0_344( + .A1(n_0_245), .A2(Instruction[2]), .ZN(n_0_239) + ); + AOI21_X1_LVT i_0_335( + .A(Instruction[6]), .B1(n_0_243), .B2(n_0_239), .ZN(n_0_230) + ); + NOR2_X1_LVT i_0_334( + .A1(n_0_232), .A2(n_0_230), .ZN(n_0_229) + ); + NAND2_X1_LVT i_0_342( + .A1(n_0_241), .A2(n_0_238), .ZN(n_0_237) + ); + NAND2_X1_LVT i_0_336( + .A1(Instruction[6]), .A2(n_0_240), .ZN(n_0_231) + ); + OAI211_X1_LVT i_0_333( + .A(n_0_229), .B(n_0_237), .C1(Instruction[2]), .C2(n_0_231), .ZN(Illegal) + ); + NAND2_X1_LVT i_0_109( + .A1(Illegal), .A2(CurrentPC[31]), .ZN(n_0_92) + ); + NAND2_X1_LVT i_0_105( + .A1(n_0_89), .A2(n_0_92), .ZN(JumpOrBranchPC[31]) + ); + AOI222_X1_LVT i_0_103( + .A1(n_92), .A2(n_0_99), .B1(n_0_91), .B2(n_61), .C1(n_30), .C2(n_0_90), .ZN(n_0_87) + ); + NAND2_X1_LVT i_0_104( + .A1(Illegal), .A2(CurrentPC[30]), .ZN(n_0_88) + ); + NAND2_X1_LVT i_0_102( + .A1(n_0_87), .A2(n_0_88), .ZN(JumpOrBranchPC[30]) + ); + AOI222_X1_LVT i_0_100( + .A1(n_91), .A2(n_0_99), .B1(n_0_91), .B2(n_60), .C1(n_29), .C2(n_0_90), .ZN(n_0_85) + ); + NAND2_X1_LVT i_0_101( + .A1(Illegal), .A2(CurrentPC[29]), .ZN(n_0_86) + ); + NAND2_X1_LVT i_0_99( + .A1(n_0_85), .A2(n_0_86), .ZN(JumpOrBranchPC[29]) + ); + AOI222_X1_LVT i_0_97( + .A1(n_90), .A2(n_0_99), .B1(n_0_91), .B2(n_59), .C1(n_28), .C2(n_0_90), .ZN(n_0_83) + ); + NAND2_X1_LVT i_0_98( + .A1(Illegal), .A2(CurrentPC[28]), .ZN(n_0_84) + ); + NAND2_X1_LVT i_0_96( + .A1(n_0_83), .A2(n_0_84), .ZN(JumpOrBranchPC[28]) + ); + AOI222_X1_LVT i_0_94( + .A1(n_89), .A2(n_0_99), .B1(n_0_91), .B2(n_58), .C1(n_27), .C2(n_0_90), .ZN(n_0_81) + ); + NAND2_X1_LVT i_0_95( + .A1(Illegal), .A2(CurrentPC[27]), .ZN(n_0_82) + ); + NAND2_X1_LVT i_0_93( + .A1(n_0_81), .A2(n_0_82), .ZN(JumpOrBranchPC[27]) + ); + AOI222_X1_LVT i_0_91( + .A1(n_88), .A2(n_0_99), .B1(n_0_91), .B2(n_57), .C1(n_26), .C2(n_0_90), .ZN(n_0_79) + ); + NAND2_X1_LVT i_0_92( + .A1(Illegal), .A2(CurrentPC[26]), .ZN(n_0_80) + ); + NAND2_X1_LVT i_0_90( + .A1(n_0_79), .A2(n_0_80), .ZN(JumpOrBranchPC[26]) + ); + AOI222_X1_LVT i_0_88( + .A1(n_87), .A2(n_0_99), .B1(n_0_91), .B2(n_56), .C1(n_25), .C2(n_0_90), .ZN(n_0_77) + ); + NAND2_X1_LVT i_0_89( + .A1(Illegal), .A2(CurrentPC[25]), .ZN(n_0_78) + ); + NAND2_X1_LVT i_0_87( + .A1(n_0_77), .A2(n_0_78), .ZN(JumpOrBranchPC[25]) + ); + AOI222_X1_LVT i_0_85( + .A1(n_86), .A2(n_0_99), .B1(n_0_91), .B2(n_55), .C1(n_24), .C2(n_0_90), .ZN(n_0_75) + ); + NAND2_X1_LVT i_0_86( + .A1(Illegal), .A2(CurrentPC[24]), .ZN(n_0_76) + ); + NAND2_X1_LVT i_0_84( + .A1(n_0_75), .A2(n_0_76), .ZN(JumpOrBranchPC[24]) + ); + AOI222_X1_LVT i_0_82( + .A1(n_85), .A2(n_0_99), .B1(n_0_91), .B2(n_54), .C1(n_23), .C2(n_0_90), .ZN(n_0_73) + ); + NAND2_X1_LVT i_0_83( + .A1(Illegal), .A2(CurrentPC[23]), .ZN(n_0_74) + ); + NAND2_X1_LVT i_0_81( + .A1(n_0_73), .A2(n_0_74), .ZN(JumpOrBranchPC[23]) + ); + AOI222_X1_LVT i_0_79( + .A1(n_84), .A2(n_0_99), .B1(n_0_91), .B2(n_53), .C1(n_22), .C2(n_0_90), .ZN(n_0_71) + ); + NAND2_X1_LVT i_0_80( + .A1(Illegal), .A2(CurrentPC[22]), .ZN(n_0_72) + ); + NAND2_X1_LVT i_0_78( + .A1(n_0_71), .A2(n_0_72), .ZN(JumpOrBranchPC[22]) + ); + AOI222_X1_LVT i_0_76( + .A1(n_83), .A2(n_0_99), .B1(n_0_91), .B2(n_52), .C1(n_21), .C2(n_0_90), .ZN(n_0_69) + ); + NAND2_X1_LVT i_0_77( + .A1(Illegal), .A2(CurrentPC[21]), .ZN(n_0_70) + ); + NAND2_X1_LVT i_0_75( + .A1(n_0_69), .A2(n_0_70), .ZN(JumpOrBranchPC[21]) + ); + AOI222_X1_LVT i_0_73( + .A1(n_82), .A2(n_0_99), .B1(n_0_91), .B2(n_51), .C1(n_20), .C2(n_0_90), .ZN(n_0_67) + ); + NAND2_X1_LVT i_0_74( + .A1(Illegal), .A2(CurrentPC[20]), .ZN(n_0_68) + ); + NAND2_X1_LVT i_0_72( + .A1(n_0_67), .A2(n_0_68), .ZN(JumpOrBranchPC[20]) + ); + AOI222_X1_LVT i_0_70( + .A1(n_81), .A2(n_0_99), .B1(n_0_91), .B2(n_50), .C1(n_19), .C2(n_0_90), .ZN(n_0_65) + ); + NAND2_X1_LVT i_0_71( + .A1(Illegal), .A2(CurrentPC[19]), .ZN(n_0_66) + ); + NAND2_X1_LVT i_0_69( + .A1(n_0_65), .A2(n_0_66), .ZN(JumpOrBranchPC[19]) + ); + AOI222_X1_LVT i_0_67( + .A1(n_80), .A2(n_0_99), .B1(n_0_91), .B2(n_49), .C1(n_18), .C2(n_0_90), .ZN(n_0_63) + ); + NAND2_X1_LVT i_0_68( + .A1(Illegal), .A2(CurrentPC[18]), .ZN(n_0_64) + ); + NAND2_X1_LVT i_0_66( + .A1(n_0_63), .A2(n_0_64), .ZN(JumpOrBranchPC[18]) + ); + AOI222_X1_LVT i_0_64( + .A1(n_79), .A2(n_0_99), .B1(n_0_91), .B2(n_48), .C1(n_17), .C2(n_0_90), .ZN(n_0_61) + ); + NAND2_X1_LVT i_0_65( + .A1(Illegal), .A2(CurrentPC[17]), .ZN(n_0_62) + ); + NAND2_X1_LVT i_0_63( + .A1(n_0_61), .A2(n_0_62), .ZN(JumpOrBranchPC[17]) + ); + AOI222_X1_LVT i_0_61( + .A1(n_78), .A2(n_0_99), .B1(n_0_91), .B2(n_47), .C1(n_16), .C2(n_0_90), .ZN(n_0_59) + ); + NAND2_X1_LVT i_0_62( + .A1(Illegal), .A2(CurrentPC[16]), .ZN(n_0_60) + ); + NAND2_X1_LVT i_0_60( + .A1(n_0_59), .A2(n_0_60), .ZN(JumpOrBranchPC[16]) + ); + AOI222_X1_LVT i_0_58( + .A1(n_77), .A2(n_0_99), .B1(n_0_91), .B2(n_46), .C1(n_15), .C2(n_0_90), .ZN(n_0_57) + ); + NAND2_X1_LVT i_0_59( + .A1(Illegal), .A2(CurrentPC[15]), .ZN(n_0_58) + ); + NAND2_X1_LVT i_0_57( + .A1(n_0_57), .A2(n_0_58), .ZN(JumpOrBranchPC[15]) + ); + AOI222_X1_LVT i_0_55( + .A1(n_76), .A2(n_0_99), .B1(n_0_91), .B2(n_45), .C1(n_14), .C2(n_0_90), .ZN(n_0_55) + ); + NAND2_X1_LVT i_0_56( + .A1(Illegal), .A2(CurrentPC[14]), .ZN(n_0_56) + ); + NAND2_X1_LVT i_0_54( + .A1(n_0_55), .A2(n_0_56), .ZN(JumpOrBranchPC[14]) + ); + AOI222_X1_LVT i_0_52( + .A1(n_75), .A2(n_0_99), .B1(n_0_91), .B2(n_44), .C1(n_13), .C2(n_0_90), .ZN(n_0_53) + ); + NAND2_X1_LVT i_0_53( + .A1(Illegal), .A2(CurrentPC[13]), .ZN(n_0_54) + ); + NAND2_X1_LVT i_0_51( + .A1(n_0_53), .A2(n_0_54), .ZN(JumpOrBranchPC[13]) + ); + AOI222_X1_LVT i_0_49( + .A1(n_74), .A2(n_0_99), .B1(n_0_91), .B2(n_43), .C1(n_12), .C2(n_0_90), .ZN(n_0_51) + ); + NAND2_X1_LVT i_0_50( + .A1(Illegal), .A2(CurrentPC[12]), .ZN(n_0_52) + ); + NAND2_X1_LVT i_0_48( + .A1(n_0_51), .A2(n_0_52), .ZN(JumpOrBranchPC[12]) + ); + AOI222_X1_LVT i_0_46( + .A1(n_73), .A2(n_0_99), .B1(n_0_91), .B2(n_42), .C1(n_11), .C2(n_0_90), .ZN(n_0_49) + ); + NAND2_X1_LVT i_0_47( + .A1(Illegal), .A2(CurrentPC[11]), .ZN(n_0_50) + ); + NAND2_X1_LVT i_0_45( + .A1(n_0_49), .A2(n_0_50), .ZN(JumpOrBranchPC[11]) + ); + AOI222_X1_LVT i_0_43( + .A1(n_72), .A2(n_0_99), .B1(n_0_91), .B2(n_41), .C1(n_10), .C2(n_0_90), .ZN(n_0_47) + ); + NAND2_X1_LVT i_0_44( + .A1(Illegal), .A2(CurrentPC[10]), .ZN(n_0_48) + ); + NAND2_X1_LVT i_0_42( + .A1(n_0_47), .A2(n_0_48), .ZN(JumpOrBranchPC[10]) + ); + AOI222_X1_LVT i_0_40( + .A1(n_71), .A2(n_0_99), .B1(n_0_91), .B2(n_40), .C1(n_9), .C2(n_0_90), .ZN(n_0_45) + ); + NAND2_X1_LVT i_0_41( + .A1(Illegal), .A2(CurrentPC[9]), .ZN(n_0_46) + ); + NAND2_X1_LVT i_0_39( + .A1(n_0_45), .A2(n_0_46), .ZN(JumpOrBranchPC[9]) + ); + AOI222_X1_LVT i_0_37( + .A1(n_70), .A2(n_0_99), .B1(n_0_91), .B2(n_39), .C1(n_8), .C2(n_0_90), .ZN(n_0_43) + ); + NAND2_X1_LVT i_0_38( + .A1(Illegal), .A2(CurrentPC[8]), .ZN(n_0_44) + ); + NAND2_X1_LVT i_0_36( + .A1(n_0_43), .A2(n_0_44), .ZN(JumpOrBranchPC[8]) + ); + AOI222_X1_LVT i_0_34( + .A1(n_69), .A2(n_0_99), .B1(n_0_91), .B2(n_38), .C1(n_7), .C2(n_0_90), .ZN(n_0_41) + ); + NAND2_X1_LVT i_0_35( + .A1(Illegal), .A2(CurrentPC[7]), .ZN(n_0_42) + ); + NAND2_X1_LVT i_0_33( + .A1(n_0_41), .A2(n_0_42), .ZN(JumpOrBranchPC[7]) + ); + AOI222_X1_LVT i_0_31( + .A1(n_68), .A2(n_0_99), .B1(n_0_91), .B2(n_37), .C1(n_6), .C2(n_0_90), .ZN(n_0_39) + ); + NAND2_X1_LVT i_0_32( + .A1(Illegal), .A2(CurrentPC[6]), .ZN(n_0_40) + ); + NAND2_X1_LVT i_0_30( + .A1(n_0_39), .A2(n_0_40), .ZN(JumpOrBranchPC[6]) + ); + AOI222_X1_LVT i_0_28( + .A1(n_67), .A2(n_0_99), .B1(n_0_91), .B2(n_36), .C1(n_5), .C2(n_0_90), .ZN(n_0_37) + ); + NAND2_X1_LVT i_0_29( + .A1(Illegal), .A2(CurrentPC[5]), .ZN(n_0_38) + ); + NAND2_X1_LVT i_0_27( + .A1(n_0_37), .A2(n_0_38), .ZN(JumpOrBranchPC[5]) + ); + AOI222_X1_LVT i_0_25( + .A1(n_66), .A2(n_0_99), .B1(n_0_91), .B2(n_35), .C1(n_4), .C2(n_0_90), .ZN(n_0_35) + ); + NAND2_X1_LVT i_0_26( + .A1(Illegal), .A2(CurrentPC[4]), .ZN(n_0_36) + ); + NAND2_X1_LVT i_0_24( + .A1(n_0_35), .A2(n_0_36), .ZN(JumpOrBranchPC[4]) + ); + AOI222_X1_LVT i_0_22( + .A1(n_65), .A2(n_0_99), .B1(n_0_91), .B2(n_34), .C1(n_3), .C2(n_0_90), .ZN(n_0_33) + ); + NAND2_X1_LVT i_0_23( + .A1(Illegal), .A2(CurrentPC[3]), .ZN(n_0_34) + ); + NAND2_X1_LVT i_0_21( + .A1(n_0_33), .A2(n_0_34), .ZN(JumpOrBranchPC[3]) + ); + AOI222_X1_LVT i_0_19( + .A1(n_64), .A2(n_0_99), .B1(n_0_91), .B2(n_33), .C1(n_2), .C2(n_0_90), .ZN(n_0_31) + ); + NAND2_X1_LVT i_0_20( + .A1(Illegal), .A2(CurrentPC[2]), .ZN(n_0_32) + ); + NAND2_X1_LVT i_0_18( + .A1(n_0_31), .A2(n_0_32), .ZN(JumpOrBranchPC[2]) + ); + AOI222_X1_LVT i_0_16( + .A1(n_63), .A2(n_0_99), .B1(n_0_91), .B2(n_32), .C1(n_1), .C2(n_0_90), .ZN(n_0_29) + ); + NAND2_X1_LVT i_0_17( + .A1(Illegal), .A2(CurrentPC[1]), .ZN(n_0_30) + ); + NAND2_X1_LVT i_0_15( + .A1(n_0_29), .A2(n_0_30), .ZN(JumpOrBranchPC[1]) + ); + NOR2_X1_LVT i_0_112( + .A1(n_0_232), .A2(n_0_238), .ZN(n_0_94) + ); + OAI221_X1_LVT i_0_14( + .A(n_0_94), .B1(n_0_225), .B2(Instruction[2]), .C1(Instruction[6]), .C2(n_0_239), + .ZN(n_0_28) + ); + AND2_X1_LVT i_0_13( + .A1(n_0_28), .A2(CurrentPC[0]), .ZN(JumpOrBranchPC[0]) + ); + NOR2_X1_LVT i_0_221( + .A1(Instruction[13]), .A2(Instruction[14]), .ZN(n_0_166) + ); + NOR3_X1_LVT i_0_293( + .A1(n_0_241), .A2(n_0_234), .A3(Instruction[3]), .ZN(n_0_206) + ); + AND2_X1_LVT i_0_292( + .A1(n_0_206), .A2(n_0_244), .ZN(n_0_205) + ); + NOR3_X1_LVT i_0_330( + .A1(n_0_248), .A2(n_0_244), .A3(Instruction[4]), .ZN(n_0_226) + ); + AOI21_X1_LVT i_0_121( + .A(n_0_205), .B1(n_0_226), .B2(n_0_237), .ZN(n_0_100) + ); + AND2_X1_LVT i_0_120( + .A1(Instruction[14]), .A2(n_0_100), .ZN(aluOp[2]) + ); + OAI33_X1_LVT i_0_119( + .A1(n_0_205), .A2(n_0_247), .A3(n_0_224), .B1(Instruction[2]), .B2(n_0_238), + .B3(n_0_225), .ZN(aluOp[1]) + ); + AOI22_X1_LVT i_0_117( + .A1(Instruction[12]), .A2(n_0_100), .B1(n_0_99), .B2(Instruction[13]), .ZN(n_0_98) + ); + INV_X1_LVT i_0_116( + .A(n_0_98), .ZN(aluOp[0]) + ); + OR2_X1_LVT i_0_327( + .A1(n_0_238), .A2(n_0_234), .ZN(n_0_223) + ); + NOR4_X1_LVT i_0_125( + .A1(Instruction[28]), .A2(Instruction[27]), .A3(Instruction[26]), .A4(Instruction[25]), + .ZN(n_0_103) + ); + INV_X1_LVT i_0_347( + .A(Instruction[30]), .ZN(n_0_242) + ); + NOR4_X1_LVT i_0_124( + .A1(Instruction[13]), .A2(n_0_242), .A3(Instruction[29]), .A4(Instruction[31]), + .ZN(n_0_102) + ); + NAND2_X1_LVT i_0_123( + .A1(n_0_103), .A2(n_0_102), .ZN(n_0_101) + ); + NOR3_X1_LVT i_0_127( + .A1(n_0_244), .A2(Instruction[12]), .A3(Instruction[14]), .ZN(n_0_105) + ); + AOI21_X1_LVT i_0_126( + .A(n_0_105), .B1(Instruction[12]), .B2(Instruction[14]), .ZN(n_0_104) + ); + NOR4_X1_LVT i_0_122( + .A1(n_0_223), .A2(n_0_101), .A3(n_0_104), .A4(Instruction[2]), .ZN(aluNegAr) + ); + OR3_X1_LVT i_0_325( + .A1(n_0_228), .A2(Instruction[4]), .A3(Instruction[6]), .ZN(n_0_222) + ); + NOR2_X1_LVT i_0_321( + .A1(n_0_222), .A2(Instruction[5]), .ZN(n_0_221) + ); + NOR3_X1_LVT i_0_224( + .A1(n_0_224), .A2(n_0_221), .A3(n_0_206), .ZN(n_0_169) + ); + NOR3_X1_LVT i_0_129( + .A1(n_0_234), .A2(Instruction[3]), .A3(Instruction[5]), .ZN(n_0_106) + ); + NOR3_X1_LVT i_0_128( + .A1(n_0_226), .A2(n_0_169), .A3(n_0_106), .ZN(aluBypass) + ); + AOI22_X1_LVT i_0_223( + .A1(CurrentPC[31]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[31]), .ZN(n_0_168) + ); + NOR3_X1_LVT i_0_219( + .A1(n_0_247), .A2(n_0_222), .A3(Instruction[5]), .ZN(n_0_164) + ); + AOI22_X1_LVT i_0_218( + .A1(RRs1[31]), .A2(n_0_169), .B1(n_0_164), .B2(RData[31]), .ZN(n_0_163) + ); + MUX2_X1_LVT i_0_222( + .A(RData[7]), .B(RData[15]), .S(Instruction[12]), .Z(n_0_167) + ); + NAND3_X1_LVT i_0_220( + .A1(n_0_221), .A2(n_0_167), .A3(n_0_166), .ZN(n_0_165) + ); + NAND3_X1_LVT i_0_217( + .A1(n_0_168), .A2(n_0_163), .A3(n_0_165), .ZN(op1[31]) + ); + AOI22_X1_LVT i_0_216( + .A1(RRs1[30]), .A2(n_0_169), .B1(n_0_164), .B2(RData[30]), .ZN(n_0_162) + ); + AOI22_X1_LVT i_0_215( + .A1(CurrentPC[30]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[30]), .ZN(n_0_161) + ); + NAND3_X1_LVT i_0_214( + .A1(n_0_162), .A2(n_0_161), .A3(n_0_165), .ZN(op1[30]) + ); + AOI22_X1_LVT i_0_213( + .A1(RRs1[29]), .A2(n_0_169), .B1(n_0_164), .B2(RData[29]), .ZN(n_0_160) + ); + AOI22_X1_LVT i_0_212( + .A1(CurrentPC[29]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[29]), .ZN(n_0_159) + ); + NAND3_X1_LVT i_0_211( + .A1(n_0_160), .A2(n_0_159), .A3(n_0_165), .ZN(op1[29]) + ); + AOI22_X1_LVT i_0_210( + .A1(RRs1[28]), .A2(n_0_169), .B1(n_0_164), .B2(RData[28]), .ZN(n_0_158) + ); + AOI22_X1_LVT i_0_209( + .A1(CurrentPC[28]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[28]), .ZN(n_0_157) + ); + NAND3_X1_LVT i_0_208( + .A1(n_0_158), .A2(n_0_157), .A3(n_0_165), .ZN(op1[28]) + ); + AOI22_X1_LVT i_0_207( + .A1(RRs1[27]), .A2(n_0_169), .B1(n_0_164), .B2(RData[27]), .ZN(n_0_156) + ); + AOI22_X1_LVT i_0_206( + .A1(CurrentPC[27]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[27]), .ZN(n_0_155) + ); + NAND3_X1_LVT i_0_205( + .A1(n_0_156), .A2(n_0_155), .A3(n_0_165), .ZN(op1[27]) + ); + AOI22_X1_LVT i_0_204( + .A1(RRs1[26]), .A2(n_0_169), .B1(n_0_164), .B2(RData[26]), .ZN(n_0_154) + ); + AOI22_X1_LVT i_0_203( + .A1(CurrentPC[26]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[26]), .ZN(n_0_153) + ); + NAND3_X1_LVT i_0_202( + .A1(n_0_154), .A2(n_0_153), .A3(n_0_165), .ZN(op1[26]) + ); + AOI22_X1_LVT i_0_201( + .A1(RRs1[25]), .A2(n_0_169), .B1(n_0_164), .B2(RData[25]), .ZN(n_0_152) + ); + AOI22_X1_LVT i_0_200( + .A1(CurrentPC[25]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[25]), .ZN(n_0_151) + ); + NAND3_X1_LVT i_0_199( + .A1(n_0_152), .A2(n_0_151), .A3(n_0_165), .ZN(op1[25]) + ); + AOI22_X1_LVT i_0_198( + .A1(RRs1[24]), .A2(n_0_169), .B1(n_0_164), .B2(RData[24]), .ZN(n_0_150) + ); + AOI22_X1_LVT i_0_197( + .A1(CurrentPC[24]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[24]), .ZN(n_0_149) + ); + NAND3_X1_LVT i_0_196( + .A1(n_0_150), .A2(n_0_149), .A3(n_0_165), .ZN(op1[24]) + ); + AOI22_X1_LVT i_0_195( + .A1(RRs1[23]), .A2(n_0_169), .B1(n_0_164), .B2(RData[23]), .ZN(n_0_148) + ); + AOI22_X1_LVT i_0_194( + .A1(CurrentPC[23]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[23]), .ZN(n_0_147) + ); + NAND3_X1_LVT i_0_193( + .A1(n_0_148), .A2(n_0_147), .A3(n_0_165), .ZN(op1[23]) + ); + AOI22_X1_LVT i_0_192( + .A1(RRs1[22]), .A2(n_0_169), .B1(n_0_164), .B2(RData[22]), .ZN(n_0_146) + ); + AOI22_X1_LVT i_0_191( + .A1(CurrentPC[22]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[22]), .ZN(n_0_145) + ); + NAND3_X1_LVT i_0_190( + .A1(n_0_146), .A2(n_0_145), .A3(n_0_165), .ZN(op1[22]) + ); + AOI22_X1_LVT i_0_189( + .A1(RRs1[21]), .A2(n_0_169), .B1(n_0_164), .B2(RData[21]), .ZN(n_0_144) + ); + AOI22_X1_LVT i_0_188( + .A1(CurrentPC[21]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[21]), .ZN(n_0_143) + ); + NAND3_X1_LVT i_0_187( + .A1(n_0_144), .A2(n_0_143), .A3(n_0_165), .ZN(op1[21]) + ); + AOI22_X1_LVT i_0_186( + .A1(RRs1[20]), .A2(n_0_169), .B1(n_0_164), .B2(RData[20]), .ZN(n_0_142) + ); + AOI22_X1_LVT i_0_185( + .A1(CurrentPC[20]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[20]), .ZN(n_0_141) + ); + NAND3_X1_LVT i_0_184( + .A1(n_0_142), .A2(n_0_141), .A3(n_0_165), .ZN(op1[20]) + ); + AOI22_X1_LVT i_0_183( + .A1(RRs1[19]), .A2(n_0_169), .B1(n_0_164), .B2(RData[19]), .ZN(n_0_140) + ); + AOI22_X1_LVT i_0_182( + .A1(CurrentPC[19]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[19]), .ZN(n_0_139) + ); + NAND3_X1_LVT i_0_181( + .A1(n_0_140), .A2(n_0_139), .A3(n_0_165), .ZN(op1[19]) + ); + AOI22_X1_LVT i_0_180( + .A1(RRs1[18]), .A2(n_0_169), .B1(n_0_164), .B2(RData[18]), .ZN(n_0_138) + ); + AOI22_X1_LVT i_0_179( + .A1(CurrentPC[18]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[18]), .ZN(n_0_137) + ); + NAND3_X1_LVT i_0_178( + .A1(n_0_138), .A2(n_0_137), .A3(n_0_165), .ZN(op1[18]) + ); + AOI22_X1_LVT i_0_177( + .A1(RRs1[17]), .A2(n_0_169), .B1(n_0_164), .B2(RData[17]), .ZN(n_0_136) + ); + AOI22_X1_LVT i_0_176( + .A1(CurrentPC[17]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[17]), .ZN(n_0_135) + ); + NAND3_X1_LVT i_0_175( + .A1(n_0_136), .A2(n_0_135), .A3(n_0_165), .ZN(op1[17]) + ); + AOI22_X1_LVT i_0_174( + .A1(RRs1[16]), .A2(n_0_169), .B1(n_0_164), .B2(RData[16]), .ZN(n_0_134) + ); + AOI22_X1_LVT i_0_173( + .A1(CurrentPC[16]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[16]), .ZN(n_0_133) + ); + NAND3_X1_LVT i_0_172( + .A1(n_0_134), .A2(n_0_133), .A3(n_0_165), .ZN(op1[16]) + ); + AOI222_X1_LVT i_0_169( + .A1(CurrentPC[15]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[15]), .C1(n_0_169), + .C2(RRs1[15]), .ZN(n_0_130) + ); + INV_X1_LVT i_0_353( + .A(Instruction[12]), .ZN(n_0_246) + ); + AOI211_X1_LVT i_0_171( + .A(Instruction[5]), .B(n_0_222), .C1(n_0_247), .C2(n_0_246), .ZN(n_0_132) + ); + OAI211_X1_LVT i_0_170( + .A(RData[15]), .B(n_0_132), .C1(Instruction[13]), .C2(Instruction[14]), .ZN(n_0_131) + ); + NAND3_X1_LVT i_0_168( + .A1(n_0_130), .A2(n_0_131), .A3(n_0_165), .ZN(op1[15]) + ); + AOI22_X1_LVT i_0_167( + .A1(RRs1[14]), .A2(n_0_169), .B1(n_0_132), .B2(RData[14]), .ZN(n_0_129) + ); + AOI22_X1_LVT i_0_166( + .A1(CurrentPC[14]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[14]), .ZN(n_0_128) + ); + NAND4_X1_LVT i_0_165( + .A1(n_0_221), .A2(n_0_246), .A3(RData[7]), .A4(n_0_166), .ZN(n_0_127) + ); + NAND3_X1_LVT i_0_164( + .A1(n_0_129), .A2(n_0_128), .A3(n_0_127), .ZN(op1[14]) + ); + AOI22_X1_LVT i_0_163( + .A1(RRs1[13]), .A2(n_0_169), .B1(n_0_132), .B2(RData[13]), .ZN(n_0_126) + ); + AOI22_X1_LVT i_0_162( + .A1(CurrentPC[13]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[13]), .ZN(n_0_125) + ); + NAND3_X1_LVT i_0_161( + .A1(n_0_126), .A2(n_0_125), .A3(n_0_127), .ZN(op1[13]) + ); + AOI22_X1_LVT i_0_160( + .A1(RRs1[12]), .A2(n_0_169), .B1(n_0_132), .B2(RData[12]), .ZN(n_0_124) + ); + AOI22_X1_LVT i_0_159( + .A1(CurrentPC[12]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[12]), .ZN(n_0_123) + ); + NAND3_X1_LVT i_0_158( + .A1(n_0_124), .A2(n_0_123), .A3(n_0_127), .ZN(op1[12]) + ); + AOI22_X1_LVT i_0_156( + .A1(CurrentPC[11]), .A2(n_0_224), .B1(n_0_132), .B2(RData[11]), .ZN(n_0_121) + ); + NAND2_X1_LVT i_0_157( + .A1(RRs1[11]), .A2(n_0_169), .ZN(n_0_122) + ); + NAND3_X1_LVT i_0_155( + .A1(n_0_121), .A2(n_0_122), .A3(n_0_127), .ZN(op1[11]) + ); + AOI22_X1_LVT i_0_153( + .A1(CurrentPC[10]), .A2(n_0_224), .B1(n_0_132), .B2(RData[10]), .ZN(n_0_119) + ); + NAND2_X1_LVT i_0_154( + .A1(RRs1[10]), .A2(n_0_169), .ZN(n_0_120) + ); + NAND3_X1_LVT i_0_152( + .A1(n_0_119), .A2(n_0_120), .A3(n_0_127), .ZN(op1[10]) + ); + AOI22_X1_LVT i_0_150( + .A1(CurrentPC[9]), .A2(n_0_224), .B1(n_0_132), .B2(RData[9]), .ZN(n_0_117) + ); + NAND2_X1_LVT i_0_151( + .A1(RRs1[9]), .A2(n_0_169), .ZN(n_0_118) + ); + NAND3_X1_LVT i_0_149( + .A1(n_0_117), .A2(n_0_118), .A3(n_0_127), .ZN(op1[9]) + ); + AOI22_X1_LVT i_0_147( + .A1(CurrentPC[8]), .A2(n_0_224), .B1(n_0_132), .B2(RData[8]), .ZN(n_0_115) + ); + NAND2_X1_LVT i_0_148( + .A1(RRs1[8]), .A2(n_0_169), .ZN(n_0_116) + ); + NAND3_X1_LVT i_0_146( + .A1(n_0_115), .A2(n_0_116), .A3(n_0_127), .ZN(op1[8]) + ); + AOI222_X1_LVT i_0_145( + .A1(CurrentPC[7]), .A2(n_0_224), .B1(n_0_221), .B2(RData[7]), .C1(n_0_169), + .C2(RRs1[7]), .ZN(n_0_114) + ); + INV_X1_LVT i_0_144( + .A(n_0_114), .ZN(op1[7]) + ); + AOI222_X1_LVT i_0_143( + .A1(CurrentPC[6]), .A2(n_0_224), .B1(n_0_221), .B2(RData[6]), .C1(n_0_169), + .C2(RRs1[6]), .ZN(n_0_113) + ); + INV_X1_LVT i_0_142( + .A(n_0_113), .ZN(op1[6]) + ); + AOI222_X1_LVT i_0_141( + .A1(CurrentPC[5]), .A2(n_0_224), .B1(n_0_221), .B2(RData[5]), .C1(n_0_169), + .C2(RRs1[5]), .ZN(n_0_112) + ); + INV_X1_LVT i_0_140( + .A(n_0_112), .ZN(op1[5]) + ); + AOI222_X1_LVT i_0_139( + .A1(CurrentPC[4]), .A2(n_0_224), .B1(n_0_221), .B2(RData[4]), .C1(n_0_169), + .C2(RRs1[4]), .ZN(n_0_111) + ); + INV_X1_LVT i_0_138( + .A(n_0_111), .ZN(op1[4]) + ); + AOI222_X1_LVT i_0_137( + .A1(CurrentPC[3]), .A2(n_0_224), .B1(n_0_221), .B2(RData[3]), .C1(n_0_169), + .C2(RRs1[3]), .ZN(n_0_110) + ); + INV_X1_LVT i_0_136( + .A(n_0_110), .ZN(op1[3]) + ); + AOI222_X1_LVT i_0_135( + .A1(CurrentPC[2]), .A2(n_0_224), .B1(n_0_221), .B2(RData[2]), .C1(n_0_169), + .C2(RRs1[2]), .ZN(n_0_109) + ); + INV_X1_LVT i_0_134( + .A(n_0_109), .ZN(op1[2]) + ); + AOI222_X1_LVT i_0_133( + .A1(CurrentPC[1]), .A2(n_0_224), .B1(n_0_221), .B2(RData[1]), .C1(n_0_169), + .C2(RRs1[1]), .ZN(n_0_108) + ); + INV_X1_LVT i_0_132( + .A(n_0_108), .ZN(op1[1]) + ); + AOI222_X1_LVT i_0_131( + .A1(CurrentPC[0]), .A2(n_0_224), .B1(n_0_221), .B2(RData[0]), .C1(n_0_169), + .C2(RRs1[0]), .ZN(n_0_107) + ); + INV_X1_LVT i_0_130( + .A(n_0_107), .ZN(op1[0]) + ); + NOR3_X1_LVT i_0_294( + .A1(n_0_223), .A2(Instruction[2]), .A3(Instruction[5]), .ZN(n_0_207) + ); + NOR3_X1_LVT i_0_291( + .A1(n_0_224), .A2(n_0_207), .A3(n_0_205), .ZN(n_0_204) + ); + AOI22_X1_LVT i_0_289( + .A1(CurrentPC[31]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[31]), .ZN(n_0_202) + ); + NAND2_X1_LVT i_0_290( + .A1(Instruction[31]), .A2(n_0_207), .ZN(n_0_203) + ); + NAND2_X1_LVT i_0_288( + .A1(n_0_202), .A2(n_0_203), .ZN(op2[31]) + ); + AOI22_X1_LVT i_0_287( + .A1(CurrentPC[30]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[30]), .ZN(n_0_201) + ); + NAND2_X1_LVT i_0_286( + .A1(n_0_201), .A2(n_0_203), .ZN(op2[30]) + ); + AOI22_X1_LVT i_0_285( + .A1(CurrentPC[29]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[29]), .ZN(n_0_200) + ); + NAND2_X1_LVT i_0_284( + .A1(n_0_200), .A2(n_0_203), .ZN(op2[29]) + ); + AOI22_X1_LVT i_0_283( + .A1(CurrentPC[28]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[28]), .ZN(n_0_199) + ); + NAND2_X1_LVT i_0_282( + .A1(n_0_199), .A2(n_0_203), .ZN(op2[28]) + ); + AOI22_X1_LVT i_0_281( + .A1(CurrentPC[27]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[27]), .ZN(n_0_198) + ); + NAND2_X1_LVT i_0_280( + .A1(n_0_198), .A2(n_0_203), .ZN(op2[27]) + ); + AOI22_X1_LVT i_0_279( + .A1(CurrentPC[26]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[26]), .ZN(n_0_197) + ); + NAND2_X1_LVT i_0_278( + .A1(n_0_197), .A2(n_0_203), .ZN(op2[26]) + ); + AOI22_X1_LVT i_0_277( + .A1(CurrentPC[25]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[25]), .ZN(n_0_196) + ); + NAND2_X1_LVT i_0_276( + .A1(n_0_196), .A2(n_0_203), .ZN(op2[25]) + ); + AOI22_X1_LVT i_0_275( + .A1(CurrentPC[24]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[24]), .ZN(n_0_195) + ); + NAND2_X1_LVT i_0_274( + .A1(n_0_195), .A2(n_0_203), .ZN(op2[24]) + ); + AOI22_X1_LVT i_0_273( + .A1(CurrentPC[23]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[23]), .ZN(n_0_194) + ); + NAND2_X1_LVT i_0_272( + .A1(n_0_194), .A2(n_0_203), .ZN(op2[23]) + ); + AOI22_X1_LVT i_0_271( + .A1(CurrentPC[22]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[22]), .ZN(n_0_193) + ); + NAND2_X1_LVT i_0_270( + .A1(n_0_193), .A2(n_0_203), .ZN(op2[22]) + ); + AOI22_X1_LVT i_0_269( + .A1(CurrentPC[21]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[21]), .ZN(n_0_192) + ); + NAND2_X1_LVT i_0_268( + .A1(n_0_192), .A2(n_0_203), .ZN(op2[21]) + ); + AOI22_X1_LVT i_0_267( + .A1(CurrentPC[20]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[20]), .ZN(n_0_191) + ); + NAND2_X1_LVT i_0_266( + .A1(n_0_191), .A2(n_0_203), .ZN(op2[20]) + ); + AOI22_X1_LVT i_0_265( + .A1(CurrentPC[19]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[19]), .ZN(n_0_190) + ); + NAND2_X1_LVT i_0_264( + .A1(n_0_190), .A2(n_0_203), .ZN(op2[19]) + ); + AOI22_X1_LVT i_0_263( + .A1(CurrentPC[18]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[18]), .ZN(n_0_189) + ); + NAND2_X1_LVT i_0_262( + .A1(n_0_189), .A2(n_0_203), .ZN(op2[18]) + ); + AOI22_X1_LVT i_0_261( + .A1(CurrentPC[17]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[17]), .ZN(n_0_188) + ); + NAND2_X1_LVT i_0_260( + .A1(n_0_188), .A2(n_0_203), .ZN(op2[17]) + ); + AOI22_X1_LVT i_0_259( + .A1(CurrentPC[16]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[16]), .ZN(n_0_187) + ); + NAND2_X1_LVT i_0_258( + .A1(n_0_187), .A2(n_0_203), .ZN(op2[16]) + ); + AOI22_X1_LVT i_0_257( + .A1(CurrentPC[15]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[15]), .ZN(n_0_186) + ); + NAND2_X1_LVT i_0_256( + .A1(n_0_186), .A2(n_0_203), .ZN(op2[15]) + ); + AOI22_X1_LVT i_0_255( + .A1(CurrentPC[14]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[14]), .ZN(n_0_185) + ); + NAND2_X1_LVT i_0_254( + .A1(n_0_185), .A2(n_0_203), .ZN(op2[14]) + ); + AOI22_X1_LVT i_0_253( + .A1(CurrentPC[13]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[13]), .ZN(n_0_184) + ); + NAND2_X1_LVT i_0_252( + .A1(n_0_184), .A2(n_0_203), .ZN(op2[13]) + ); + AOI22_X1_LVT i_0_251( + .A1(CurrentPC[12]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[12]), .ZN(n_0_183) + ); + NAND2_X1_LVT i_0_250( + .A1(n_0_183), .A2(n_0_203), .ZN(op2[12]) + ); + AOI22_X1_LVT i_0_249( + .A1(CurrentPC[11]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[11]), .ZN(n_0_182) + ); + NAND2_X1_LVT i_0_248( + .A1(n_0_182), .A2(n_0_203), .ZN(op2[11]) + ); + AOI222_X1_LVT i_0_247( + .A1(Instruction[30]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[10]), .C1(n_0_204), + .C2(RRs2[10]), .ZN(n_0_181) + ); + INV_X1_LVT i_0_246( + .A(n_0_181), .ZN(op2[10]) + ); + AOI222_X1_LVT i_0_245( + .A1(Instruction[29]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[9]), .C1(n_0_204), + .C2(RRs2[9]), .ZN(n_0_180) + ); + INV_X1_LVT i_0_244( + .A(n_0_180), .ZN(op2[9]) + ); + AOI222_X1_LVT i_0_243( + .A1(Instruction[28]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[8]), .C1(n_0_204), + .C2(RRs2[8]), .ZN(n_0_179) + ); + INV_X1_LVT i_0_242( + .A(n_0_179), .ZN(op2[8]) + ); + AOI222_X1_LVT i_0_241( + .A1(Instruction[27]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[7]), .C1(n_0_204), + .C2(RRs2[7]), .ZN(n_0_178) + ); + INV_X1_LVT i_0_240( + .A(n_0_178), .ZN(op2[7]) + ); + AOI222_X1_LVT i_0_239( + .A1(Instruction[26]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[6]), .C1(n_0_204), + .C2(RRs2[6]), .ZN(n_0_177) + ); + INV_X1_LVT i_0_238( + .A(n_0_177), .ZN(op2[6]) + ); + AOI222_X1_LVT i_0_237( + .A1(Instruction[25]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[5]), .C1(n_0_204), + .C2(RRs2[5]), .ZN(n_0_176) + ); + INV_X1_LVT i_0_236( + .A(n_0_176), .ZN(op2[5]) + ); + AOI222_X1_LVT i_0_235( + .A1(Instruction[24]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[4]), .C1(n_0_204), + .C2(RRs2[4]), .ZN(n_0_175) + ); + INV_X1_LVT i_0_234( + .A(n_0_175), .ZN(op2[4]) + ); + AOI222_X1_LVT i_0_233( + .A1(Instruction[23]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[3]), .C1(n_0_204), + .C2(RRs2[3]), .ZN(n_0_174) + ); + INV_X1_LVT i_0_232( + .A(n_0_174), .ZN(op2[3]) + ); + AOI22_X1_LVT i_0_230( + .A1(Instruction[22]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[2]), .ZN(n_0_172) + ); + OAI21_X1_LVT i_0_231( + .A(RRs2[2]), .B1(n_0_223), .B2(Instruction[5]), .ZN(n_0_173) + ); + NAND3_X1_LVT i_0_229( + .A1(n_0_172), .A2(n_0_173), .A3(n_0_249), .ZN(op2[2]) + ); + AOI222_X1_LVT i_0_228( + .A1(Instruction[21]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[1]), .C1(n_0_204), + .C2(RRs2[1]), .ZN(n_0_171) + ); + INV_X1_LVT i_0_227( + .A(n_0_171), .ZN(op2[1]) + ); + AOI222_X1_LVT i_0_226( + .A1(Instruction[20]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[0]), .C1(n_0_204), + .C2(RRs2[0]), .ZN(n_0_170) + ); + INV_X1_LVT i_0_225( + .A(n_0_170), .ZN(op2[0]) + ); + alu theALU( + .aluOp(aluOp), .aluNegAr(aluNegAr), .aluBypass(aluBypass), .op1(op1), .op2(op2), + .result(WRd), .eqFlag(eqFlag) + ); + XNOR2_X1_LVT i_0_115( + .A(Instruction[12]), .B(eqFlag), .ZN(n_0_97) + ); + XNOR2_X1_LVT i_0_114( + .A(Instruction[12]), .B(WRd[0]), .ZN(n_0_96) + ); + AOI22_X1_LVT i_0_113( + .A1(n_0_166), .A2(n_0_97), .B1(n_0_96), .B2(Instruction[14]), .ZN(n_0_95) + ); + AOI22_X1_LVT i_0_111( + .A1(Instruction[6]), .A2(n_0_95), .B1(Instruction[2]), .B2(n_0_245), .ZN(n_0_93) + ); + NAND2_X1_LVT i_0_110( + .A1(n_0_94), .A2(n_0_93), .ZN(JumpOrBranch) + ); + INV_X1_LVT i_0_349( + .A(Instruction[31]), .ZN(n_0_0) + ); + INV_X1_LVT i_0_348( + .A(RRs1[12]), .ZN(n_0_1) + ); + HA_X1_LVT i_0_0( + .A(Instruction[7]), .B(RRs1[0]), .CO(n_0_2), .S(n_0_15) + ); + FA_X1_LVT i_0_1( + .A(Instruction[8]), .B(RRs1[1]), .CI(n_0_2), .CO(n_0_3), .S(n_0_16) + ); + FA_X1_LVT i_0_2( + .A(Instruction[9]), .B(RRs1[2]), .CI(n_0_3), .CO(n_0_4), .S(n_0_17) + ); + FA_X1_LVT i_0_3( + .A(Instruction[10]), .B(RRs1[3]), .CI(n_0_4), .CO(n_0_5), .S(n_0_18) + ); + FA_X1_LVT i_0_4( + .A(Instruction[11]), .B(RRs1[4]), .CI(n_0_5), .CO(n_0_6), .S(n_0_19) + ); + FA_X1_LVT i_0_5( + .A(Instruction[25]), .B(RRs1[5]), .CI(n_0_6), .CO(n_0_7), .S(n_0_20) + ); + FA_X1_LVT i_0_6( + .A(Instruction[26]), .B(RRs1[6]), .CI(n_0_7), .CO(n_0_8), .S(n_0_21) + ); + FA_X1_LVT i_0_7( + .A(Instruction[27]), .B(RRs1[7]), .CI(n_0_8), .CO(n_0_9), .S(n_0_22) + ); + FA_X1_LVT i_0_8( + .A(Instruction[28]), .B(RRs1[8]), .CI(n_0_9), .CO(n_0_10), .S(n_0_23) + ); + FA_X1_LVT i_0_9( + .A(Instruction[29]), .B(RRs1[9]), .CI(n_0_10), .CO(n_0_11), .S(n_0_24) + ); + FA_X1_LVT i_0_10( + .A(Instruction[30]), .B(RRs1[10]), .CI(n_0_11), .CO(n_0_12), .S(n_0_25) + ); + FA_X1_LVT i_0_11( + .A(RRs1[11]), .B(Instruction[31]), .CI(n_0_12), .CO(n_0_13), .S(n_0_26) + ); + FA_X1_LVT i_0_12( + .A(n_0_0), .B(n_0_1), .CI(n_0_13), .CO(n_0_14), .S(n_0_27) + ); + NOR2_X1_LVT i_0_322( + .A1(n_0_244), .A2(n_0_222), .ZN(WrMem) + ); + AOI22_X1_LVT i_0_320( + .A1(n_0_27), .A2(WrMem), .B1(n_0_221), .B2(n_12), .ZN(n_0_220) + ); + INV_X1_LVT i_0_319( + .A(n_0_220), .ZN(DAddr[12]) + ); + AOI22_X1_LVT i_0_318( + .A1(n_0_26), .A2(WrMem), .B1(n_0_221), .B2(n_11), .ZN(n_0_219) + ); + INV_X1_LVT i_0_317( + .A(n_0_219), .ZN(DAddr[11]) + ); + AOI22_X1_LVT i_0_316( + .A1(n_0_25), .A2(WrMem), .B1(n_0_221), .B2(n_10), .ZN(n_0_218) + ); + INV_X1_LVT i_0_315( + .A(n_0_218), .ZN(DAddr[10]) + ); + AOI22_X1_LVT i_0_314( + .A1(n_0_24), .A2(WrMem), .B1(n_0_221), .B2(n_9), .ZN(n_0_217) + ); + INV_X1_LVT i_0_313( + .A(n_0_217), .ZN(DAddr[9]) + ); + AOI22_X1_LVT i_0_312( + .A1(n_0_23), .A2(WrMem), .B1(n_0_221), .B2(n_8), .ZN(n_0_216) + ); + INV_X1_LVT i_0_311( + .A(n_0_216), .ZN(DAddr[8]) + ); + AOI22_X1_LVT i_0_310( + .A1(n_0_22), .A2(WrMem), .B1(n_0_221), .B2(n_7), .ZN(n_0_215) + ); + INV_X1_LVT i_0_309( + .A(n_0_215), .ZN(DAddr[7]) + ); + AOI22_X1_LVT i_0_308( + .A1(n_0_21), .A2(WrMem), .B1(n_0_221), .B2(n_6), .ZN(n_0_214) + ); + INV_X1_LVT i_0_307( + .A(n_0_214), .ZN(DAddr[6]) + ); + AOI22_X1_LVT i_0_306( + .A1(n_0_20), .A2(WrMem), .B1(n_0_221), .B2(n_5), .ZN(n_0_213) + ); + INV_X1_LVT i_0_305( + .A(n_0_213), .ZN(DAddr[5]) + ); + AOI22_X1_LVT i_0_304( + .A1(n_0_19), .A2(WrMem), .B1(n_0_221), .B2(n_4), .ZN(n_0_212) + ); + INV_X1_LVT i_0_303( + .A(n_0_212), .ZN(DAddr[4]) + ); + AOI22_X1_LVT i_0_302( + .A1(n_0_18), .A2(WrMem), .B1(n_0_221), .B2(n_3), .ZN(n_0_211) + ); + INV_X1_LVT i_0_301( + .A(n_0_211), .ZN(DAddr[3]) + ); + AOI22_X1_LVT i_0_300( + .A1(n_0_17), .A2(WrMem), .B1(n_0_221), .B2(n_2), .ZN(n_0_210) + ); + INV_X1_LVT i_0_299( + .A(n_0_210), .ZN(DAddr[2]) + ); + AOI22_X1_LVT i_0_298( + .A1(n_0_16), .A2(WrMem), .B1(n_0_221), .B2(n_1), .ZN(n_0_209) + ); + INV_X1_LVT i_0_297( + .A(n_0_209), .ZN(DAddr[1]) + ); + AOI22_X1_LVT i_0_296( + .A1(n_0_15), .A2(WrMem), .B1(n_0_221), .B2(n_0), .ZN(n_0_208) + ); + INV_X1_LVT i_0_295( + .A(n_0_208), .ZN(DAddr[0]) + ); + OR2_X1_LVT i_0_324( + .A1(n_0_222), .A2(Instruction[13]), .ZN(DWidth[1]) + ); + NOR2_X1_LVT i_0_323( + .A1(n_0_246), .A2(n_0_222), .ZN(DWidth[0]) + ); + NAND3_X1_LVT i_0_331( + .A1(n_0_248), .A2(n_0_244), .A3(n_0_236), .ZN(n_0_227) + ); + OAI211_X1_LVT i_0_326( + .A(n_0_249), .B(n_0_223), .C1(n_0_228), .C2(n_0_227), .ZN(WrReg) + ); +endmodule + +module MemGen_32_11(chip_en, clock, addr, rd_data, rd_en, wr_en, wr_data); + input [31:0] wr_data; + input [10:0] addr; + input chip_en, clock, rd_en, wr_en; + output [31:0] rd_data; + + wire [1:0] mem_sel; + wire n_63, n_62, n_61, n_60, n_59, n_58, n_57, n_56, n_55, n_54, n_53, n_52, + n_51, n_50, n_49, n_48, n_31, n_30, n_29, n_28, n_27, n_26, n_25, n_24, + n_23, n_22, n_21, n_20, n_19, n_18, n_17, n_16, n_47, n_46, n_45, n_44, + n_43, n_42, n_41, n_40, n_39, n_38, n_37, n_36, n_35, n_34, n_33, n_32, + n_15, n_14, n_13, n_12, n_11, n_10, n_9, n_8, n_7, n_6, n_5, n_4, n_3, + n_2, n_1, n_0; + + INV_X1_LVT i_1_3( + .A(addr[10]), .ZN(mem_sel[0]) + ); + MemGen_16_10 genblk1_0_U_hi( + .chip_en(mem_sel[0]), .wr_en(wr_en), .addr({addr[9], addr[8], addr[7], + addr[6], addr[5], addr[4], addr[3], addr[2], addr[1], addr[0]}), .wr_data({ + wr_data[31], wr_data[30], wr_data[29], wr_data[28], wr_data[27], + wr_data[26], wr_data[25], wr_data[24], wr_data[23], wr_data[22], + wr_data[21], wr_data[20], wr_data[19], wr_data[18], wr_data[17], + wr_data[16]}), .clock(clock), .rd_en(rd_en), .rd_data({n_63, n_62, n_61, + n_60, n_59, n_58, n_57, n_56, n_55, n_54, n_53, n_52, n_51, n_50, n_49, + n_48}) + ); + MemGen_16_10 genblk1_1_U_hi( + .chip_en(addr[10]), .wr_en(wr_en), .addr({addr[9], addr[8], addr[7], + addr[6], addr[5], addr[4], addr[3], addr[2], addr[1], addr[0]}), .wr_data({ + wr_data[31], wr_data[30], wr_data[29], wr_data[28], wr_data[27], + wr_data[26], wr_data[25], wr_data[24], wr_data[23], wr_data[22], + wr_data[21], wr_data[20], wr_data[19], wr_data[18], wr_data[17], + wr_data[16]}), .clock(clock), .rd_en(rd_en), .rd_data({n_31, n_30, n_29, + n_28, n_27, n_26, n_25, n_24, n_23, n_22, n_21, n_20, n_19, n_18, n_17, + n_16}) + ); + MUX2_X1_LVT i_1_1_31( + .A(n_63), .B(n_31), .S(addr[10]), .Z(rd_data[31]) + ); + MUX2_X1_LVT i_1_1_30( + .A(n_62), .B(n_30), .S(addr[10]), .Z(rd_data[30]) + ); + MUX2_X1_LVT i_1_1_29( + .A(n_61), .B(n_29), .S(addr[10]), .Z(rd_data[29]) + ); + MUX2_X1_LVT i_1_1_28( + .A(n_60), .B(n_28), .S(addr[10]), .Z(rd_data[28]) + ); + MUX2_X1_LVT i_1_1_27( + .A(n_59), .B(n_27), .S(addr[10]), .Z(rd_data[27]) + ); + MUX2_X1_LVT i_1_1_26( + .A(n_58), .B(n_26), .S(addr[10]), .Z(rd_data[26]) + ); + MUX2_X1_LVT i_1_1_25( + .A(n_57), .B(n_25), .S(addr[10]), .Z(rd_data[25]) + ); + MUX2_X1_LVT i_1_1_24( + .A(n_56), .B(n_24), .S(addr[10]), .Z(rd_data[24]) + ); + MUX2_X1_LVT i_1_1_23( + .A(n_55), .B(n_23), .S(addr[10]), .Z(rd_data[23]) + ); + MUX2_X1_LVT i_1_1_22( + .A(n_54), .B(n_22), .S(addr[10]), .Z(rd_data[22]) + ); + MUX2_X1_LVT i_1_1_21( + .A(n_53), .B(n_21), .S(addr[10]), .Z(rd_data[21]) + ); + MUX2_X1_LVT i_1_1_20( + .A(n_52), .B(n_20), .S(addr[10]), .Z(rd_data[20]) + ); + MUX2_X1_LVT i_1_1_19( + .A(n_51), .B(n_19), .S(addr[10]), .Z(rd_data[19]) + ); + MUX2_X1_LVT i_1_1_18( + .A(n_50), .B(n_18), .S(addr[10]), .Z(rd_data[18]) + ); + MUX2_X1_LVT i_1_1_17( + .A(n_49), .B(n_17), .S(addr[10]), .Z(rd_data[17]) + ); + MUX2_X1_LVT i_1_1_16( + .A(n_48), .B(n_16), .S(addr[10]), .Z(rd_data[16]) + ); + MemGen_16_10 genblk1_0_U_lo( + .chip_en(mem_sel[0]), .wr_en(wr_en), .addr({addr[9], addr[8], addr[7], + addr[6], addr[5], addr[4], addr[3], addr[2], addr[1], addr[0]}), .wr_data({ + wr_data[15], wr_data[14], wr_data[13], wr_data[12], wr_data[11], + wr_data[10], wr_data[9], wr_data[8], wr_data[7], wr_data[6], wr_data[5], + wr_data[4], wr_data[3], wr_data[2], wr_data[1], wr_data[0]}), .clock(clock), + .rd_en(rd_en), .rd_data({n_47, n_46, n_45, n_44, n_43, n_42, n_41, + n_40, n_39, n_38, n_37, n_36, n_35, n_34, n_33, n_32}) + ); + MemGen_16_10 genblk1_1_U_lo( + .chip_en(addr[10]), .wr_en(wr_en), .addr({addr[9], addr[8], addr[7], + addr[6], addr[5], addr[4], addr[3], addr[2], addr[1], addr[0]}), .wr_data({ + wr_data[15], wr_data[14], wr_data[13], wr_data[12], wr_data[11], + wr_data[10], wr_data[9], wr_data[8], wr_data[7], wr_data[6], wr_data[5], + wr_data[4], wr_data[3], wr_data[2], wr_data[1], wr_data[0]}), .clock(clock), + .rd_en(rd_en), .rd_data({n_15, n_14, n_13, n_12, n_11, n_10, n_9, n_8, + n_7, n_6, n_5, n_4, n_3, n_2, n_1, n_0}) + ); + MUX2_X1_LVT i_1_1_15( + .A(n_47), .B(n_15), .S(addr[10]), .Z(rd_data[15]) + ); + MUX2_X1_LVT i_1_1_14( + .A(n_46), .B(n_14), .S(addr[10]), .Z(rd_data[14]) + ); + MUX2_X1_LVT i_1_1_13( + .A(n_45), .B(n_13), .S(addr[10]), .Z(rd_data[13]) + ); + MUX2_X1_LVT i_1_1_12( + .A(n_44), .B(n_12), .S(addr[10]), .Z(rd_data[12]) + ); + MUX2_X1_LVT i_1_1_11( + .A(n_43), .B(n_11), .S(addr[10]), .Z(rd_data[11]) + ); + MUX2_X1_LVT i_1_1_10( + .A(n_42), .B(n_10), .S(addr[10]), .Z(rd_data[10]) + ); + MUX2_X1_LVT i_1_1_9( + .A(n_41), .B(n_9), .S(addr[10]), .Z(rd_data[9]) + ); + MUX2_X1_LVT i_1_1_8( + .A(n_40), .B(n_8), .S(addr[10]), .Z(rd_data[8]) + ); + MUX2_X1_LVT i_1_1_7( + .A(n_39), .B(n_7), .S(addr[10]), .Z(rd_data[7]) + ); + MUX2_X1_LVT i_1_1_6( + .A(n_38), .B(n_6), .S(addr[10]), .Z(rd_data[6]) + ); + MUX2_X1_LVT i_1_1_5( + .A(n_37), .B(n_5), .S(addr[10]), .Z(rd_data[5]) + ); + MUX2_X1_LVT i_1_1_4( + .A(n_36), .B(n_4), .S(addr[10]), .Z(rd_data[4]) + ); + MUX2_X1_LVT i_1_1_3( + .A(n_35), .B(n_3), .S(addr[10]), .Z(rd_data[3]) + ); + MUX2_X1_LVT i_1_1_2( + .A(n_34), .B(n_2), .S(addr[10]), .Z(rd_data[2]) + ); + MUX2_X1_LVT i_1_1_1( + .A(n_33), .B(n_1), .S(addr[10]), .Z(rd_data[1]) + ); + MUX2_X1_LVT i_1_1_0( + .A(n_32), .B(n_0), .S(addr[10]), .Z(rd_data[0]) + ); +endmodule + +module main_mem(clk, reset, DAddr, IAddr, DWData, DRData, IRData, DWE, DWidth); + input [31:0] DAddr, IAddr, DWData; + input [1:0] DWidth; + input clk, reset, DWE; + output [31:0] DRData, IRData; + + wire [31:0] mem_rdata, drTmp, mem_wdata; + wire [10:0] mem_addr; + wire n_0_0, n_0_0_0, n_0_1, n_0_0_1, n_0_2, n_0_0_2, n_0_3, n_0_0_3, n_0_4, + n_0_0_4, n_0_5, n_0_0_5, n_0_6, n_0_0_6, n_0_7, n_0_0_7, n_0_8, n_0_0_8, + n_0_9, n_0_0_9, n_0_10, n_0_0_10, n_0_0_11, n_0_11, n_0_0_12, n_0_0_13, + n_0_12, n_0_0_14, n_0_0_15, n_0_13, n_0_0_16, n_0_0_17, n_0_14, + n_0_0_18, n_0_0_19, n_0_15, n_0_0_20, n_0_0_21, n_0_16, n_0_0_22, + n_0_0_23, n_0_17, n_0_0_24, n_0_0_25, n_0_18, n_0_0_26, n_0_0_27, + n_0_0_28, n_0_19, n_0_0_29, n_0_20, n_0_0_30, n_0_21, n_0_0_31, n_0_22, + n_0_0_32, n_0_23, n_0_0_33, n_0_24, n_0_0_34, n_0_25, n_0_0_35, n_0_26, + n_0_0_36, n_0_0_37, n_0_27, n_0_28, n_0_29, n_0_30, n_0_31, n_0_32, + n_0_33, n_0_34, n_0_35, n_0_36, n_0_37, n_0_38, n_0_39, n_0_40, n_0_41, + n_0_42, n_0_65, n_0_64, n_0_63, n_0_62, n_0_61, n_0_60, n_0_59, n_0_58, + n_0_0_38, n_0_0_39, n_0_57, n_0_0_40, n_0_56, n_0_0_41, n_0_55, + n_0_0_42, n_0_54, n_0_0_43, n_0_53, n_0_0_44, n_0_52, n_0_0_45, n_0_51, + n_0_0_46, n_0_50, n_0_0_47, n_0_0_48, n_0_0_49, n_0_0_50, n_0_0_51, + n_0_49, n_0_0_52, n_0_48, n_0_0_53, n_0_47, n_0_0_54, n_0_46, n_0_0_55, + n_0_45, n_0_0_56, n_0_44, n_0_0_57, n_0_66, n_0_0_58, n_0_67, n_0_0_59, + n_0_0_60, n_0_0_61, n_0_68, n_0_0_62, n_0_0_63, n_0_69, n_0_0_64, + n_0_0_65, n_0_70, n_0_0_66, n_0_0_67, n_0_71, n_0_0_68, n_0_0_69, + n_0_72, n_0_0_70, n_0_0_71, n_0_73, n_0_0_72, n_0_0_73, n_0_74, + n_0_0_74, n_0_0_75, n_0_75, n_0_0_76, n_0_0_77, n_0_0_78, n_0_0_79, + n_0_0_80, n_0_0_81, n_0_0_82, n_0_0_83, n_0_0_84, n_0_0_85, n_0_0_86, + n_0_0_87, n_0_0_88, n_0_0_89, n_0_0_90, n_0_0_91, n_0_0_92, n_0_43, + n_0_0_93, n_0_0_94, n_0_76, n_0_0_95, n_0; + + INV_X1_LVT i_0_0_171( + .A(DWE), .ZN(n_0) + ); + NOR2_X1_LVT i_0_0_163( + .A1(n_0), .A2(reset), .ZN(n_0_0_88) + ); + NOR2_X1_LVT i_0_0_22( + .A1(DWE), .A2(reset), .ZN(n_0_0_11) + ); + AOI22_X1_LVT i_0_0_21( + .A1(DAddr[12]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[12]), .ZN(n_0_0_10) + ); + INV_X1_LVT i_0_0_20( + .A(n_0_0_10), .ZN(n_0_10) + ); + INV_X1_LVT i_0_0_172( + .A(clk), .ZN(n_0_76) + ); + DFF_X1_LVT \mem_addr_reg[10] ( + .CK(n_0_76), .D(n_0_10), .Q(mem_addr[10]), .QN() + ); + AOI22_X1_LVT i_0_0_19( + .A1(DAddr[11]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[11]), .ZN(n_0_0_9) + ); + INV_X1_LVT i_0_0_18( + .A(n_0_0_9), .ZN(n_0_9) + ); + DFF_X1_LVT \mem_addr_reg[9] ( + .CK(n_0_76), .D(n_0_9), .Q(mem_addr[9]), .QN() + ); + AOI22_X1_LVT i_0_0_17( + .A1(DAddr[10]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[10]), .ZN(n_0_0_8) + ); + INV_X1_LVT i_0_0_16( + .A(n_0_0_8), .ZN(n_0_8) + ); + DFF_X1_LVT \mem_addr_reg[8] ( + .CK(n_0_76), .D(n_0_8), .Q(mem_addr[8]), .QN() + ); + AOI22_X1_LVT i_0_0_15( + .A1(DAddr[9]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[9]), .ZN(n_0_0_7) + ); + INV_X1_LVT i_0_0_14( + .A(n_0_0_7), .ZN(n_0_7) + ); + DFF_X1_LVT \mem_addr_reg[7] ( + .CK(n_0_76), .D(n_0_7), .Q(mem_addr[7]), .QN() + ); + AOI22_X1_LVT i_0_0_13( + .A1(DAddr[8]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[8]), .ZN(n_0_0_6) + ); + INV_X1_LVT i_0_0_12( + .A(n_0_0_6), .ZN(n_0_6) + ); + DFF_X1_LVT \mem_addr_reg[6] ( + .CK(n_0_76), .D(n_0_6), .Q(mem_addr[6]), .QN() + ); + AOI22_X1_LVT i_0_0_11( + .A1(DAddr[7]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[7]), .ZN(n_0_0_5) + ); + INV_X1_LVT i_0_0_10( + .A(n_0_0_5), .ZN(n_0_5) + ); + DFF_X1_LVT \mem_addr_reg[5] ( + .CK(n_0_76), .D(n_0_5), .Q(mem_addr[5]), .QN() + ); + AOI22_X1_LVT i_0_0_9( + .A1(DAddr[6]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[6]), .ZN(n_0_0_4) + ); + INV_X1_LVT i_0_0_8( + .A(n_0_0_4), .ZN(n_0_4) + ); + DFF_X1_LVT \mem_addr_reg[4] ( + .CK(n_0_76), .D(n_0_4), .Q(mem_addr[4]), .QN() + ); + AOI22_X1_LVT i_0_0_7( + .A1(DAddr[5]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[5]), .ZN(n_0_0_3) + ); + INV_X1_LVT i_0_0_6( + .A(n_0_0_3), .ZN(n_0_3) + ); + DFF_X1_LVT \mem_addr_reg[3] ( + .CK(n_0_76), .D(n_0_3), .Q(mem_addr[3]), .QN() + ); + AOI22_X1_LVT i_0_0_5( + .A1(DAddr[4]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[4]), .ZN(n_0_0_2) + ); + INV_X1_LVT i_0_0_4( + .A(n_0_0_2), .ZN(n_0_2) + ); + DFF_X1_LVT \mem_addr_reg[2] ( + .CK(n_0_76), .D(n_0_2), .Q(mem_addr[2]), .QN() + ); + AOI22_X1_LVT i_0_0_3( + .A1(DAddr[3]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[3]), .ZN(n_0_0_1) + ); + INV_X1_LVT i_0_0_2( + .A(n_0_0_1), .ZN(n_0_1) + ); + DFF_X1_LVT \mem_addr_reg[1] ( + .CK(n_0_76), .D(n_0_1), .Q(mem_addr[1]), .QN() + ); + AOI22_X1_LVT i_0_0_1( + .A1(DAddr[2]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[2]), .ZN(n_0_0_0) + ); + INV_X1_LVT i_0_0_0( + .A(n_0_0_0), .ZN(n_0_0) + ); + DFF_X1_LVT \mem_addr_reg[0] ( + .CK(n_0_76), .D(n_0_0), .Q(mem_addr[0]), .QN() + ); + NOR2_X1_LVT i_0_0_162( + .A1(DWidth[1]), .A2(DAddr[1]), .ZN(n_0_0_87) + ); + NOR2_X1_LVT i_0_0_158( + .A1(DWidth[0]), .A2(DAddr[0]), .ZN(n_0_0_83) + ); + AND2_X1_LVT i_0_0_157( + .A1(n_0_0_87), .A2(n_0_0_83), .ZN(n_0_0_82) + ); + AND2_X1_LVT i_0_0_156( + .A1(n_0_0_88), .A2(n_0_0_82), .ZN(n_0_0_81) + ); + INV_X1_LVT i_0_0_173( + .A(n_0_0_88), .ZN(n_0_0_95) + ); + INV_X1_LVT i_0_0_169( + .A(DWidth[1]), .ZN(n_0_0_93) + ); + NOR3_X1_LVT i_0_0_155( + .A1(n_0_0_95), .A2(DWidth[0]), .A3(n_0_0_93), .ZN(n_0_0_80) + ); + AOI22_X1_LVT i_0_0_154( + .A1(DWData[7]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[31]), .ZN(n_0_0_79) + ); + NAND2_X1_LVT i_0_0_168( + .A1(DWidth[0]), .A2(DWidth[1]), .ZN(n_0_43) + ); + INV_X1_LVT i_0_0_167( + .A(n_0_43), .ZN(n_0_0_92) + ); + NOR2_X1_LVT i_0_0_160( + .A1(n_0_0_95), .A2(n_0_0_92), .ZN(n_0_0_85) + ); + NAND2_X1_LVT i_0_0_161( + .A1(n_0_0_93), .A2(DAddr[1]), .ZN(n_0_0_86) + ); + NOR2_X1_LVT i_0_0_166( + .A1(DWidth[0]), .A2(DWidth[1]), .ZN(n_0_0_91) + ); + NAND2_X1_LVT i_0_0_164( + .A1(DAddr[0]), .A2(n_0_0_91), .ZN(n_0_0_89) + ); + NAND3_X1_LVT i_0_0_159( + .A1(n_0_0_85), .A2(n_0_0_86), .A3(n_0_0_89), .ZN(n_0_0_84) + ); + INV_X1_LVT i_0_0_170( + .A(DWidth[0]), .ZN(n_0_0_94) + ); + NOR2_X1_LVT i_0_0_153( + .A1(n_0_0_94), .A2(DAddr[1]), .ZN(n_0_0_78) + ); + AND3_X1_LVT i_0_0_152( + .A1(n_0_0_88), .A2(n_0_0_78), .A3(n_0_0_93), .ZN(n_0_0_77) + ); + AOI22_X1_LVT i_0_0_151( + .A1(n_0_0_84), .A2(mem_wdata[31]), .B1(DWData[15]), .B2(n_0_0_77), .ZN(n_0_0_76) + ); + NAND2_X1_LVT i_0_0_150( + .A1(n_0_0_79), .A2(n_0_0_76), .ZN(n_0_75) + ); + DFF_X1_LVT \mem_wdata_reg[31] ( + .CK(n_0_76), .D(n_0_75), .Q(mem_wdata[31]), .QN() + ); + AOI22_X1_LVT i_0_0_149( + .A1(DWData[6]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[30]), .ZN(n_0_0_75) + ); + AOI22_X1_LVT i_0_0_148( + .A1(n_0_0_84), .A2(mem_wdata[30]), .B1(DWData[14]), .B2(n_0_0_77), .ZN(n_0_0_74) + ); + NAND2_X1_LVT i_0_0_147( + .A1(n_0_0_75), .A2(n_0_0_74), .ZN(n_0_74) + ); + DFF_X1_LVT \mem_wdata_reg[30] ( + .CK(n_0_76), .D(n_0_74), .Q(mem_wdata[30]), .QN() + ); + AOI22_X1_LVT i_0_0_146( + .A1(DWData[5]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[29]), .ZN(n_0_0_73) + ); + AOI22_X1_LVT i_0_0_145( + .A1(n_0_0_84), .A2(mem_wdata[29]), .B1(DWData[13]), .B2(n_0_0_77), .ZN(n_0_0_72) + ); + NAND2_X1_LVT i_0_0_144( + .A1(n_0_0_73), .A2(n_0_0_72), .ZN(n_0_73) + ); + DFF_X1_LVT \mem_wdata_reg[29] ( + .CK(n_0_76), .D(n_0_73), .Q(mem_wdata[29]), .QN() + ); + AOI22_X1_LVT i_0_0_143( + .A1(DWData[4]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[28]), .ZN(n_0_0_71) + ); + AOI22_X1_LVT i_0_0_142( + .A1(n_0_0_84), .A2(mem_wdata[28]), .B1(DWData[12]), .B2(n_0_0_77), .ZN(n_0_0_70) + ); + NAND2_X1_LVT i_0_0_141( + .A1(n_0_0_71), .A2(n_0_0_70), .ZN(n_0_72) + ); + DFF_X1_LVT \mem_wdata_reg[28] ( + .CK(n_0_76), .D(n_0_72), .Q(mem_wdata[28]), .QN() + ); + AOI22_X1_LVT i_0_0_140( + .A1(DWData[3]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[27]), .ZN(n_0_0_69) + ); + AOI22_X1_LVT i_0_0_139( + .A1(n_0_0_84), .A2(mem_wdata[27]), .B1(DWData[11]), .B2(n_0_0_77), .ZN(n_0_0_68) + ); + NAND2_X1_LVT i_0_0_138( + .A1(n_0_0_69), .A2(n_0_0_68), .ZN(n_0_71) + ); + DFF_X1_LVT \mem_wdata_reg[27] ( + .CK(n_0_76), .D(n_0_71), .Q(mem_wdata[27]), .QN() + ); + AOI22_X1_LVT i_0_0_137( + .A1(DWData[2]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[26]), .ZN(n_0_0_67) + ); + AOI22_X1_LVT i_0_0_136( + .A1(n_0_0_84), .A2(mem_wdata[26]), .B1(DWData[10]), .B2(n_0_0_77), .ZN(n_0_0_66) + ); + NAND2_X1_LVT i_0_0_135( + .A1(n_0_0_67), .A2(n_0_0_66), .ZN(n_0_70) + ); + DFF_X1_LVT \mem_wdata_reg[26] ( + .CK(n_0_76), .D(n_0_70), .Q(mem_wdata[26]), .QN() + ); + AOI22_X1_LVT i_0_0_134( + .A1(DWData[1]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[25]), .ZN(n_0_0_65) + ); + AOI22_X1_LVT i_0_0_133( + .A1(n_0_0_84), .A2(mem_wdata[25]), .B1(DWData[9]), .B2(n_0_0_77), .ZN(n_0_0_64) + ); + NAND2_X1_LVT i_0_0_132( + .A1(n_0_0_65), .A2(n_0_0_64), .ZN(n_0_69) + ); + DFF_X1_LVT \mem_wdata_reg[25] ( + .CK(n_0_76), .D(n_0_69), .Q(mem_wdata[25]), .QN() + ); + AOI22_X1_LVT i_0_0_131( + .A1(DWData[0]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[24]), .ZN(n_0_0_63) + ); + AOI22_X1_LVT i_0_0_130( + .A1(n_0_0_84), .A2(mem_wdata[24]), .B1(DWData[8]), .B2(n_0_0_77), .ZN(n_0_0_62) + ); + NAND2_X1_LVT i_0_0_129( + .A1(n_0_0_63), .A2(n_0_0_62), .ZN(n_0_68) + ); + DFF_X1_LVT \mem_wdata_reg[24] ( + .CK(n_0_76), .D(n_0_68), .Q(mem_wdata[24]), .QN() + ); + NOR4_X1_LVT i_0_0_127( + .A1(n_0_0_95), .A2(n_0_0_83), .A3(DWidth[1]), .A4(DAddr[1]), .ZN(n_0_0_60) + ); + INV_X1_LVT i_0_0_165( + .A(n_0_0_91), .ZN(n_0_0_90) + ); + OAI211_X1_LVT i_0_0_128( + .A(n_0_0_85), .B(n_0_0_86), .C1(n_0_0_90), .C2(DAddr[0]), .ZN(n_0_0_61) + ); + AOI222_X1_LVT i_0_0_126( + .A1(DWData[7]), .A2(n_0_0_60), .B1(mem_wdata[23]), .B2(n_0_0_61), .C1(DWData[23]), + .C2(n_0_0_80), .ZN(n_0_0_59) + ); + INV_X1_LVT i_0_0_125( + .A(n_0_0_59), .ZN(n_0_67) + ); + DFF_X1_LVT \mem_wdata_reg[23] ( + .CK(n_0_76), .D(n_0_67), .Q(mem_wdata[23]), .QN() + ); + AOI222_X1_LVT i_0_0_124( + .A1(DWData[6]), .A2(n_0_0_60), .B1(mem_wdata[22]), .B2(n_0_0_61), .C1(DWData[22]), + .C2(n_0_0_80), .ZN(n_0_0_58) + ); + INV_X1_LVT i_0_0_123( + .A(n_0_0_58), .ZN(n_0_66) + ); + DFF_X1_LVT \mem_wdata_reg[22] ( + .CK(n_0_76), .D(n_0_66), .Q(mem_wdata[22]), .QN() + ); + AOI222_X1_LVT i_0_0_122( + .A1(DWData[5]), .A2(n_0_0_60), .B1(mem_wdata[21]), .B2(n_0_0_61), .C1(DWData[21]), + .C2(n_0_0_80), .ZN(n_0_0_57) + ); + INV_X1_LVT i_0_0_121( + .A(n_0_0_57), .ZN(n_0_44) + ); + DFF_X1_LVT \mem_wdata_reg[21] ( + .CK(n_0_76), .D(n_0_44), .Q(mem_wdata[21]), .QN() + ); + AOI222_X1_LVT i_0_0_120( + .A1(DWData[4]), .A2(n_0_0_60), .B1(mem_wdata[20]), .B2(n_0_0_61), .C1(DWData[20]), + .C2(n_0_0_80), .ZN(n_0_0_56) + ); + INV_X1_LVT i_0_0_119( + .A(n_0_0_56), .ZN(n_0_45) + ); + DFF_X1_LVT \mem_wdata_reg[20] ( + .CK(n_0_76), .D(n_0_45), .Q(mem_wdata[20]), .QN() + ); + AOI222_X1_LVT i_0_0_118( + .A1(DWData[3]), .A2(n_0_0_60), .B1(mem_wdata[19]), .B2(n_0_0_61), .C1(DWData[19]), + .C2(n_0_0_80), .ZN(n_0_0_55) + ); + INV_X1_LVT i_0_0_117( + .A(n_0_0_55), .ZN(n_0_46) + ); + DFF_X1_LVT \mem_wdata_reg[19] ( + .CK(n_0_76), .D(n_0_46), .Q(mem_wdata[19]), .QN() + ); + AOI222_X1_LVT i_0_0_116( + .A1(DWData[2]), .A2(n_0_0_60), .B1(mem_wdata[18]), .B2(n_0_0_61), .C1(DWData[18]), + .C2(n_0_0_80), .ZN(n_0_0_54) + ); + INV_X1_LVT i_0_0_115( + .A(n_0_0_54), .ZN(n_0_47) + ); + DFF_X1_LVT \mem_wdata_reg[18] ( + .CK(n_0_76), .D(n_0_47), .Q(mem_wdata[18]), .QN() + ); + AOI222_X1_LVT i_0_0_114( + .A1(DWData[1]), .A2(n_0_0_60), .B1(mem_wdata[17]), .B2(n_0_0_61), .C1(DWData[17]), + .C2(n_0_0_80), .ZN(n_0_0_53) + ); + INV_X1_LVT i_0_0_113( + .A(n_0_0_53), .ZN(n_0_48) + ); + DFF_X1_LVT \mem_wdata_reg[17] ( + .CK(n_0_76), .D(n_0_48), .Q(mem_wdata[17]), .QN() + ); + AOI222_X1_LVT i_0_0_112( + .A1(DWData[0]), .A2(n_0_0_60), .B1(mem_wdata[16]), .B2(n_0_0_61), .C1(DWData[16]), + .C2(n_0_0_80), .ZN(n_0_0_52) + ); + INV_X1_LVT i_0_0_111( + .A(n_0_0_52), .ZN(n_0_49) + ); + DFF_X1_LVT \mem_wdata_reg[16] ( + .CK(n_0_76), .D(n_0_49), .Q(mem_wdata[16]), .QN() + ); + NOR4_X1_LVT i_0_0_110( + .A1(n_0_0_95), .A2(n_0_0_87), .A3(n_0_0_92), .A4(n_0_0_91), .ZN(n_0_0_51) + ); + NOR3_X1_LVT i_0_0_109( + .A1(n_0_0_86), .A2(DAddr[0]), .A3(DWidth[0]), .ZN(n_0_0_50) + ); + AND2_X1_LVT i_0_0_108( + .A1(n_0_0_88), .A2(n_0_0_50), .ZN(n_0_0_49) + ); + OAI211_X1_LVT i_0_0_107( + .A(n_0_0_85), .B(n_0_0_89), .C1(DAddr[1]), .C2(DWidth[1]), .ZN(n_0_0_48) + ); + AOI222_X1_LVT i_0_0_106( + .A1(DWData[15]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[7]), .C1(n_0_0_48), + .C2(mem_wdata[15]), .ZN(n_0_0_47) + ); + INV_X1_LVT i_0_0_105( + .A(n_0_0_47), .ZN(n_0_50) + ); + DFF_X1_LVT \mem_wdata_reg[15] ( + .CK(n_0_76), .D(n_0_50), .Q(mem_wdata[15]), .QN() + ); + AOI222_X1_LVT i_0_0_104( + .A1(DWData[14]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[6]), .C1(n_0_0_48), + .C2(mem_wdata[14]), .ZN(n_0_0_46) + ); + INV_X1_LVT i_0_0_103( + .A(n_0_0_46), .ZN(n_0_51) + ); + DFF_X1_LVT \mem_wdata_reg[14] ( + .CK(n_0_76), .D(n_0_51), .Q(mem_wdata[14]), .QN() + ); + AOI222_X1_LVT i_0_0_102( + .A1(DWData[13]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[5]), .C1(n_0_0_48), + .C2(mem_wdata[13]), .ZN(n_0_0_45) + ); + INV_X1_LVT i_0_0_101( + .A(n_0_0_45), .ZN(n_0_52) + ); + DFF_X1_LVT \mem_wdata_reg[13] ( + .CK(n_0_76), .D(n_0_52), .Q(mem_wdata[13]), .QN() + ); + AOI222_X1_LVT i_0_0_100( + .A1(DWData[12]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[4]), .C1(n_0_0_48), + .C2(mem_wdata[12]), .ZN(n_0_0_44) + ); + INV_X1_LVT i_0_0_99( + .A(n_0_0_44), .ZN(n_0_53) + ); + DFF_X1_LVT \mem_wdata_reg[12] ( + .CK(n_0_76), .D(n_0_53), .Q(mem_wdata[12]), .QN() + ); + AOI222_X1_LVT i_0_0_98( + .A1(DWData[11]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[3]), .C1(n_0_0_48), + .C2(mem_wdata[11]), .ZN(n_0_0_43) + ); + INV_X1_LVT i_0_0_97( + .A(n_0_0_43), .ZN(n_0_54) + ); + DFF_X1_LVT \mem_wdata_reg[11] ( + .CK(n_0_76), .D(n_0_54), .Q(mem_wdata[11]), .QN() + ); + AOI222_X1_LVT i_0_0_96( + .A1(DWData[10]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[2]), .C1(n_0_0_48), + .C2(mem_wdata[10]), .ZN(n_0_0_42) + ); + INV_X1_LVT i_0_0_95( + .A(n_0_0_42), .ZN(n_0_55) + ); + DFF_X1_LVT \mem_wdata_reg[10] ( + .CK(n_0_76), .D(n_0_55), .Q(mem_wdata[10]), .QN() + ); + AOI222_X1_LVT i_0_0_94( + .A1(DWData[9]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[1]), .C1(n_0_0_48), + .C2(mem_wdata[9]), .ZN(n_0_0_41) + ); + INV_X1_LVT i_0_0_93( + .A(n_0_0_41), .ZN(n_0_56) + ); + DFF_X1_LVT \mem_wdata_reg[9] ( + .CK(n_0_76), .D(n_0_56), .Q(mem_wdata[9]), .QN() + ); + AOI222_X1_LVT i_0_0_92( + .A1(DWData[8]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[0]), .C1(n_0_0_48), + .C2(mem_wdata[8]), .ZN(n_0_0_40) + ); + INV_X1_LVT i_0_0_91( + .A(n_0_0_40), .ZN(n_0_57) + ); + DFF_X1_LVT \mem_wdata_reg[8] ( + .CK(n_0_76), .D(n_0_57), .Q(mem_wdata[8]), .QN() + ); + AOI21_X1_LVT i_0_0_90( + .A(n_0_0_87), .B1(n_0_0_83), .B2(n_0_0_93), .ZN(n_0_0_39) + ); + NAND2_X1_LVT i_0_0_89( + .A1(n_0_0_85), .A2(n_0_0_39), .ZN(n_0_0_38) + ); + MUX2_X1_LVT i_0_0_88( + .A(DWData[7]), .B(mem_wdata[7]), .S(n_0_0_38), .Z(n_0_58) + ); + DFF_X1_LVT \mem_wdata_reg[7] ( + .CK(n_0_76), .D(n_0_58), .Q(mem_wdata[7]), .QN() + ); + MUX2_X1_LVT i_0_0_87( + .A(DWData[6]), .B(mem_wdata[6]), .S(n_0_0_38), .Z(n_0_59) + ); + DFF_X1_LVT \mem_wdata_reg[6] ( + .CK(n_0_76), .D(n_0_59), .Q(mem_wdata[6]), .QN() + ); + MUX2_X1_LVT i_0_0_86( + .A(DWData[5]), .B(mem_wdata[5]), .S(n_0_0_38), .Z(n_0_60) + ); + DFF_X1_LVT \mem_wdata_reg[5] ( + .CK(n_0_76), .D(n_0_60), .Q(mem_wdata[5]), .QN() + ); + MUX2_X1_LVT i_0_0_85( + .A(DWData[4]), .B(mem_wdata[4]), .S(n_0_0_38), .Z(n_0_61) + ); + DFF_X1_LVT \mem_wdata_reg[4] ( + .CK(n_0_76), .D(n_0_61), .Q(mem_wdata[4]), .QN() + ); + MUX2_X1_LVT i_0_0_84( + .A(DWData[3]), .B(mem_wdata[3]), .S(n_0_0_38), .Z(n_0_62) + ); + DFF_X1_LVT \mem_wdata_reg[3] ( + .CK(n_0_76), .D(n_0_62), .Q(mem_wdata[3]), .QN() + ); + MUX2_X1_LVT i_0_0_83( + .A(DWData[2]), .B(mem_wdata[2]), .S(n_0_0_38), .Z(n_0_63) + ); + DFF_X1_LVT \mem_wdata_reg[2] ( + .CK(n_0_76), .D(n_0_63), .Q(mem_wdata[2]), .QN() + ); + MUX2_X1_LVT i_0_0_82( + .A(DWData[1]), .B(mem_wdata[1]), .S(n_0_0_38), .Z(n_0_64) + ); + DFF_X1_LVT \mem_wdata_reg[1] ( + .CK(n_0_76), .D(n_0_64), .Q(mem_wdata[1]), .QN() + ); + MUX2_X1_LVT i_0_0_81( + .A(DWData[0]), .B(mem_wdata[0]), .S(n_0_0_38), .Z(n_0_65) + ); + DFF_X1_LVT \mem_wdata_reg[0] ( + .CK(n_0_76), .D(n_0_65), .Q(mem_wdata[0]), .QN() + ); + MemGen_32_11 RAM( + .chip_en(), .clock(clk), .addr(mem_addr), .rd_data(mem_rdata), .rd_en(n_0), + .wr_en(DWE), .wr_data(mem_wdata) + ); + DFF_X1_LVT \drTmp_reg[31] ( + .CK(n_0_76), .D(mem_rdata[31]), .Q(drTmp[31]), .QN() + ); + AND2_X1_LVT i_0_0_80( + .A1(DWidth[1]), .A2(drTmp[31]), .ZN(n_0_42) + ); + DLH_X1_LVT \DRData[31] ( + .D(n_0_42), .G(n_0_43), .Q(DRData[31]) + ); + DFF_X1_LVT \drTmp_reg[30] ( + .CK(n_0_76), .D(mem_rdata[30]), .Q(drTmp[30]), .QN() + ); + AND2_X1_LVT i_0_0_79( + .A1(DWidth[1]), .A2(drTmp[30]), .ZN(n_0_41) + ); + DLH_X1_LVT \DRData[30] ( + .D(n_0_41), .G(n_0_43), .Q(DRData[30]) + ); + DFF_X1_LVT \drTmp_reg[29] ( + .CK(n_0_76), .D(mem_rdata[29]), .Q(drTmp[29]), .QN() + ); + AND2_X1_LVT i_0_0_78( + .A1(DWidth[1]), .A2(drTmp[29]), .ZN(n_0_40) + ); + DLH_X1_LVT \DRData[29] ( + .D(n_0_40), .G(n_0_43), .Q(DRData[29]) + ); + DFF_X1_LVT \drTmp_reg[28] ( + .CK(n_0_76), .D(mem_rdata[28]), .Q(drTmp[28]), .QN() + ); + AND2_X1_LVT i_0_0_77( + .A1(DWidth[1]), .A2(drTmp[28]), .ZN(n_0_39) + ); + DLH_X1_LVT \DRData[28] ( + .D(n_0_39), .G(n_0_43), .Q(DRData[28]) + ); + DFF_X1_LVT \drTmp_reg[27] ( + .CK(n_0_76), .D(mem_rdata[27]), .Q(drTmp[27]), .QN() + ); + AND2_X1_LVT i_0_0_76( + .A1(DWidth[1]), .A2(drTmp[27]), .ZN(n_0_38) + ); + DLH_X1_LVT \DRData[27] ( + .D(n_0_38), .G(n_0_43), .Q(DRData[27]) + ); + DFF_X1_LVT \drTmp_reg[26] ( + .CK(n_0_76), .D(mem_rdata[26]), .Q(drTmp[26]), .QN() + ); + AND2_X1_LVT i_0_0_75( + .A1(DWidth[1]), .A2(drTmp[26]), .ZN(n_0_37) + ); + DLH_X1_LVT \DRData[26] ( + .D(n_0_37), .G(n_0_43), .Q(DRData[26]) + ); + DFF_X1_LVT \drTmp_reg[25] ( + .CK(n_0_76), .D(mem_rdata[25]), .Q(drTmp[25]), .QN() + ); + AND2_X1_LVT i_0_0_74( + .A1(DWidth[1]), .A2(drTmp[25]), .ZN(n_0_36) + ); + DLH_X1_LVT \DRData[25] ( + .D(n_0_36), .G(n_0_43), .Q(DRData[25]) + ); + DFF_X1_LVT \drTmp_reg[24] ( + .CK(n_0_76), .D(mem_rdata[24]), .Q(drTmp[24]), .QN() + ); + AND2_X1_LVT i_0_0_73( + .A1(DWidth[1]), .A2(drTmp[24]), .ZN(n_0_35) + ); + DLH_X1_LVT \DRData[24] ( + .D(n_0_35), .G(n_0_43), .Q(DRData[24]) + ); + DFF_X1_LVT \drTmp_reg[23] ( + .CK(n_0_76), .D(mem_rdata[23]), .Q(drTmp[23]), .QN() + ); + AND2_X1_LVT i_0_0_72( + .A1(DWidth[1]), .A2(drTmp[23]), .ZN(n_0_34) + ); + DLH_X1_LVT \DRData[23] ( + .D(n_0_34), .G(n_0_43), .Q(DRData[23]) + ); + DFF_X1_LVT \drTmp_reg[22] ( + .CK(n_0_76), .D(mem_rdata[22]), .Q(drTmp[22]), .QN() + ); + AND2_X1_LVT i_0_0_71( + .A1(DWidth[1]), .A2(drTmp[22]), .ZN(n_0_33) + ); + DLH_X1_LVT \DRData[22] ( + .D(n_0_33), .G(n_0_43), .Q(DRData[22]) + ); + DFF_X1_LVT \drTmp_reg[21] ( + .CK(n_0_76), .D(mem_rdata[21]), .Q(drTmp[21]), .QN() + ); + AND2_X1_LVT i_0_0_70( + .A1(DWidth[1]), .A2(drTmp[21]), .ZN(n_0_32) + ); + DLH_X1_LVT \DRData[21] ( + .D(n_0_32), .G(n_0_43), .Q(DRData[21]) + ); + DFF_X1_LVT \drTmp_reg[20] ( + .CK(n_0_76), .D(mem_rdata[20]), .Q(drTmp[20]), .QN() + ); + AND2_X1_LVT i_0_0_69( + .A1(DWidth[1]), .A2(drTmp[20]), .ZN(n_0_31) + ); + DLH_X1_LVT \DRData[20] ( + .D(n_0_31), .G(n_0_43), .Q(DRData[20]) + ); + DFF_X1_LVT \drTmp_reg[19] ( + .CK(n_0_76), .D(mem_rdata[19]), .Q(drTmp[19]), .QN() + ); + AND2_X1_LVT i_0_0_68( + .A1(DWidth[1]), .A2(drTmp[19]), .ZN(n_0_30) + ); + DLH_X1_LVT \DRData[19] ( + .D(n_0_30), .G(n_0_43), .Q(DRData[19]) + ); + DFF_X1_LVT \drTmp_reg[18] ( + .CK(n_0_76), .D(mem_rdata[18]), .Q(drTmp[18]), .QN() + ); + AND2_X1_LVT i_0_0_67( + .A1(DWidth[1]), .A2(drTmp[18]), .ZN(n_0_29) + ); + DLH_X1_LVT \DRData[18] ( + .D(n_0_29), .G(n_0_43), .Q(DRData[18]) + ); + DFF_X1_LVT \drTmp_reg[17] ( + .CK(n_0_76), .D(mem_rdata[17]), .Q(drTmp[17]), .QN() + ); + AND2_X1_LVT i_0_0_66( + .A1(DWidth[1]), .A2(drTmp[17]), .ZN(n_0_28) + ); + DLH_X1_LVT \DRData[17] ( + .D(n_0_28), .G(n_0_43), .Q(DRData[17]) + ); + DFF_X1_LVT \drTmp_reg[16] ( + .CK(n_0_76), .D(mem_rdata[16]), .Q(drTmp[16]), .QN() + ); + AND2_X1_LVT i_0_0_65( + .A1(DWidth[1]), .A2(drTmp[16]), .ZN(n_0_27) + ); + DLH_X1_LVT \DRData[16] ( + .D(n_0_27), .G(n_0_43), .Q(DRData[16]) + ); + NOR2_X1_LVT i_0_0_64( + .A1(n_0_0_91), .A2(n_0_0_87), .ZN(n_0_0_37) + ); + DFF_X1_LVT \drTmp_reg[15] ( + .CK(n_0_76), .D(mem_rdata[15]), .Q(drTmp[15]), .QN() + ); + AOI22_X1_LVT i_0_0_63( + .A1(drTmp[31]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[15]), .ZN(n_0_0_36) + ); + INV_X1_LVT i_0_0_62( + .A(n_0_0_36), .ZN(n_0_26) + ); + DLH_X1_LVT \DRData[15] ( + .D(n_0_26), .G(n_0_43), .Q(DRData[15]) + ); + DFF_X1_LVT \drTmp_reg[14] ( + .CK(n_0_76), .D(mem_rdata[14]), .Q(drTmp[14]), .QN() + ); + AOI22_X1_LVT i_0_0_61( + .A1(drTmp[30]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[14]), .ZN(n_0_0_35) + ); + INV_X1_LVT i_0_0_60( + .A(n_0_0_35), .ZN(n_0_25) + ); + DLH_X1_LVT \DRData[14] ( + .D(n_0_25), .G(n_0_43), .Q(DRData[14]) + ); + DFF_X1_LVT \drTmp_reg[13] ( + .CK(n_0_76), .D(mem_rdata[13]), .Q(drTmp[13]), .QN() + ); + AOI22_X1_LVT i_0_0_59( + .A1(drTmp[29]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[13]), .ZN(n_0_0_34) + ); + INV_X1_LVT i_0_0_58( + .A(n_0_0_34), .ZN(n_0_24) + ); + DLH_X1_LVT \DRData[13] ( + .D(n_0_24), .G(n_0_43), .Q(DRData[13]) + ); + DFF_X1_LVT \drTmp_reg[12] ( + .CK(n_0_76), .D(mem_rdata[12]), .Q(drTmp[12]), .QN() + ); + AOI22_X1_LVT i_0_0_57( + .A1(drTmp[28]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[12]), .ZN(n_0_0_33) + ); + INV_X1_LVT i_0_0_56( + .A(n_0_0_33), .ZN(n_0_23) + ); + DLH_X1_LVT \DRData[12] ( + .D(n_0_23), .G(n_0_43), .Q(DRData[12]) + ); + DFF_X1_LVT \drTmp_reg[11] ( + .CK(n_0_76), .D(mem_rdata[11]), .Q(drTmp[11]), .QN() + ); + AOI22_X1_LVT i_0_0_55( + .A1(drTmp[27]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[11]), .ZN(n_0_0_32) + ); + INV_X1_LVT i_0_0_54( + .A(n_0_0_32), .ZN(n_0_22) + ); + DLH_X1_LVT \DRData[11] ( + .D(n_0_22), .G(n_0_43), .Q(DRData[11]) + ); + DFF_X1_LVT \drTmp_reg[10] ( + .CK(n_0_76), .D(mem_rdata[10]), .Q(drTmp[10]), .QN() + ); + AOI22_X1_LVT i_0_0_53( + .A1(drTmp[26]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[10]), .ZN(n_0_0_31) + ); + INV_X1_LVT i_0_0_52( + .A(n_0_0_31), .ZN(n_0_21) + ); + DLH_X1_LVT \DRData[10] ( + .D(n_0_21), .G(n_0_43), .Q(DRData[10]) + ); + DFF_X1_LVT \drTmp_reg[9] ( + .CK(n_0_76), .D(mem_rdata[9]), .Q(drTmp[9]), .QN() + ); + AOI22_X1_LVT i_0_0_51( + .A1(drTmp[25]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[9]), .ZN(n_0_0_30) + ); + INV_X1_LVT i_0_0_50( + .A(n_0_0_30), .ZN(n_0_20) + ); + DLH_X1_LVT \DRData[9] ( + .D(n_0_20), .G(n_0_43), .Q(DRData[9]) + ); + DFF_X1_LVT \drTmp_reg[8] ( + .CK(n_0_76), .D(mem_rdata[8]), .Q(drTmp[8]), .QN() + ); + AOI22_X1_LVT i_0_0_49( + .A1(drTmp[24]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[8]), .ZN(n_0_0_29) + ); + INV_X1_LVT i_0_0_48( + .A(n_0_0_29), .ZN(n_0_19) + ); + DLH_X1_LVT \DRData[8] ( + .D(n_0_19), .G(n_0_43), .Q(DRData[8]) + ); + AOI22_X1_LVT i_0_0_46( + .A1(drTmp[31]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[15]), .ZN(n_0_0_27) + ); + AOI211_X1_LVT i_0_0_47( + .A(DAddr[1]), .B(n_0_0_83), .C1(n_0_0_94), .C2(DWidth[1]), .ZN(n_0_0_28) + ); + DFF_X1_LVT \drTmp_reg[7] ( + .CK(n_0_76), .D(mem_rdata[7]), .Q(drTmp[7]), .QN() + ); + AOI22_X1_LVT i_0_0_45( + .A1(drTmp[23]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[7]), .ZN(n_0_0_26) + ); + NAND2_X1_LVT i_0_0_44( + .A1(n_0_0_27), .A2(n_0_0_26), .ZN(n_0_18) + ); + DLH_X1_LVT \DRData[7] ( + .D(n_0_18), .G(n_0_43), .Q(DRData[7]) + ); + AOI22_X1_LVT i_0_0_43( + .A1(drTmp[30]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[14]), .ZN(n_0_0_25) + ); + DFF_X1_LVT \drTmp_reg[6] ( + .CK(n_0_76), .D(mem_rdata[6]), .Q(drTmp[6]), .QN() + ); + AOI22_X1_LVT i_0_0_42( + .A1(drTmp[22]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[6]), .ZN(n_0_0_24) + ); + NAND2_X1_LVT i_0_0_41( + .A1(n_0_0_25), .A2(n_0_0_24), .ZN(n_0_17) + ); + DLH_X1_LVT \DRData[6] ( + .D(n_0_17), .G(n_0_43), .Q(DRData[6]) + ); + AOI22_X1_LVT i_0_0_40( + .A1(drTmp[29]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[13]), .ZN(n_0_0_23) + ); + DFF_X1_LVT \drTmp_reg[5] ( + .CK(n_0_76), .D(mem_rdata[5]), .Q(drTmp[5]), .QN() + ); + AOI22_X1_LVT i_0_0_39( + .A1(drTmp[21]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[5]), .ZN(n_0_0_22) + ); + NAND2_X1_LVT i_0_0_38( + .A1(n_0_0_23), .A2(n_0_0_22), .ZN(n_0_16) + ); + DLH_X1_LVT \DRData[5] ( + .D(n_0_16), .G(n_0_43), .Q(DRData[5]) + ); + AOI22_X1_LVT i_0_0_37( + .A1(drTmp[28]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[12]), .ZN(n_0_0_21) + ); + DFF_X1_LVT \drTmp_reg[4] ( + .CK(n_0_76), .D(mem_rdata[4]), .Q(drTmp[4]), .QN() + ); + AOI22_X1_LVT i_0_0_36( + .A1(drTmp[20]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[4]), .ZN(n_0_0_20) + ); + NAND2_X1_LVT i_0_0_35( + .A1(n_0_0_21), .A2(n_0_0_20), .ZN(n_0_15) + ); + DLH_X1_LVT \DRData[4] ( + .D(n_0_15), .G(n_0_43), .Q(DRData[4]) + ); + AOI22_X1_LVT i_0_0_34( + .A1(drTmp[27]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[11]), .ZN(n_0_0_19) + ); + DFF_X1_LVT \drTmp_reg[3] ( + .CK(n_0_76), .D(mem_rdata[3]), .Q(drTmp[3]), .QN() + ); + AOI22_X1_LVT i_0_0_33( + .A1(drTmp[19]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[3]), .ZN(n_0_0_18) + ); + NAND2_X1_LVT i_0_0_32( + .A1(n_0_0_19), .A2(n_0_0_18), .ZN(n_0_14) + ); + DLH_X1_LVT \DRData[3] ( + .D(n_0_14), .G(n_0_43), .Q(DRData[3]) + ); + AOI22_X1_LVT i_0_0_31( + .A1(drTmp[26]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[10]), .ZN(n_0_0_17) + ); + DFF_X1_LVT \drTmp_reg[2] ( + .CK(n_0_76), .D(mem_rdata[2]), .Q(drTmp[2]), .QN() + ); + AOI22_X1_LVT i_0_0_30( + .A1(drTmp[18]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[2]), .ZN(n_0_0_16) + ); + NAND2_X1_LVT i_0_0_29( + .A1(n_0_0_17), .A2(n_0_0_16), .ZN(n_0_13) + ); + DLH_X1_LVT \DRData[2] ( + .D(n_0_13), .G(n_0_43), .Q(DRData[2]) + ); + AOI22_X1_LVT i_0_0_28( + .A1(drTmp[25]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[9]), .ZN(n_0_0_15) + ); + DFF_X1_LVT \drTmp_reg[1] ( + .CK(n_0_76), .D(mem_rdata[1]), .Q(drTmp[1]), .QN() + ); + AOI22_X1_LVT i_0_0_27( + .A1(drTmp[17]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[1]), .ZN(n_0_0_14) + ); + NAND2_X1_LVT i_0_0_26( + .A1(n_0_0_15), .A2(n_0_0_14), .ZN(n_0_12) + ); + DLH_X1_LVT \DRData[1] ( + .D(n_0_12), .G(n_0_43), .Q(DRData[1]) + ); + AOI22_X1_LVT i_0_0_25( + .A1(drTmp[24]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[8]), .ZN(n_0_0_13) + ); + DFF_X1_LVT \drTmp_reg[0] ( + .CK(n_0_76), .D(mem_rdata[0]), .Q(drTmp[0]), .QN() + ); + AOI22_X1_LVT i_0_0_24( + .A1(drTmp[16]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[0]), .ZN(n_0_0_12) + ); + NAND2_X1_LVT i_0_0_23( + .A1(n_0_0_13), .A2(n_0_0_12), .ZN(n_0_11) + ); + DLH_X1_LVT \DRData[0] ( + .D(n_0_11), .G(n_0_43), .Q(DRData[0]) + ); + DFF_X1_LVT \IRData_reg[31] ( + .CK(clk), .D(mem_rdata[31]), .Q(IRData[31]), .QN() + ); + DFF_X1_LVT \IRData_reg[30] ( + .CK(clk), .D(mem_rdata[30]), .Q(IRData[30]), .QN() + ); + DFF_X1_LVT \IRData_reg[29] ( + .CK(clk), .D(mem_rdata[29]), .Q(IRData[29]), .QN() + ); + DFF_X1_LVT \IRData_reg[28] ( + .CK(clk), .D(mem_rdata[28]), .Q(IRData[28]), .QN() + ); + DFF_X1_LVT \IRData_reg[27] ( + .CK(clk), .D(mem_rdata[27]), .Q(IRData[27]), .QN() + ); + DFF_X1_LVT \IRData_reg[26] ( + .CK(clk), .D(mem_rdata[26]), .Q(IRData[26]), .QN() + ); + DFF_X1_LVT \IRData_reg[25] ( + .CK(clk), .D(mem_rdata[25]), .Q(IRData[25]), .QN() + ); + DFF_X1_LVT \IRData_reg[24] ( + .CK(clk), .D(mem_rdata[24]), .Q(IRData[24]), .QN() + ); + DFF_X1_LVT \IRData_reg[23] ( + .CK(clk), .D(mem_rdata[23]), .Q(IRData[23]), .QN() + ); + DFF_X1_LVT \IRData_reg[22] ( + .CK(clk), .D(mem_rdata[22]), .Q(IRData[22]), .QN() + ); + DFF_X1_LVT \IRData_reg[21] ( + .CK(clk), .D(mem_rdata[21]), .Q(IRData[21]), .QN() + ); + DFF_X1_LVT \IRData_reg[20] ( + .CK(clk), .D(mem_rdata[20]), .Q(IRData[20]), .QN() + ); + DFF_X1_LVT \IRData_reg[19] ( + .CK(clk), .D(mem_rdata[19]), .Q(IRData[19]), .QN() + ); + DFF_X1_LVT \IRData_reg[18] ( + .CK(clk), .D(mem_rdata[18]), .Q(IRData[18]), .QN() + ); + DFF_X1_LVT \IRData_reg[17] ( + .CK(clk), .D(mem_rdata[17]), .Q(IRData[17]), .QN() + ); + DFF_X1_LVT \IRData_reg[16] ( + .CK(clk), .D(mem_rdata[16]), .Q(IRData[16]), .QN() + ); + DFF_X1_LVT \IRData_reg[15] ( + .CK(clk), .D(mem_rdata[15]), .Q(IRData[15]), .QN() + ); + DFF_X1_LVT \IRData_reg[14] ( + .CK(clk), .D(mem_rdata[14]), .Q(IRData[14]), .QN() + ); + DFF_X1_LVT \IRData_reg[13] ( + .CK(clk), .D(mem_rdata[13]), .Q(IRData[13]), .QN() + ); + DFF_X1_LVT \IRData_reg[12] ( + .CK(clk), .D(mem_rdata[12]), .Q(IRData[12]), .QN() + ); + DFF_X1_LVT \IRData_reg[11] ( + .CK(clk), .D(mem_rdata[11]), .Q(IRData[11]), .QN() + ); + DFF_X1_LVT \IRData_reg[10] ( + .CK(clk), .D(mem_rdata[10]), .Q(IRData[10]), .QN() + ); + DFF_X1_LVT \IRData_reg[9] ( + .CK(clk), .D(mem_rdata[9]), .Q(IRData[9]), .QN() + ); + DFF_X1_LVT \IRData_reg[8] ( + .CK(clk), .D(mem_rdata[8]), .Q(IRData[8]), .QN() + ); + DFF_X1_LVT \IRData_reg[7] ( + .CK(clk), .D(mem_rdata[7]), .Q(IRData[7]), .QN() + ); + DFF_X1_LVT \IRData_reg[6] ( + .CK(clk), .D(mem_rdata[6]), .Q(IRData[6]), .QN() + ); + DFF_X1_LVT \IRData_reg[5] ( + .CK(clk), .D(mem_rdata[5]), .Q(IRData[5]), .QN() + ); + DFF_X1_LVT \IRData_reg[4] ( + .CK(clk), .D(mem_rdata[4]), .Q(IRData[4]), .QN() + ); + DFF_X1_LVT \IRData_reg[3] ( + .CK(clk), .D(mem_rdata[3]), .Q(IRData[3]), .QN() + ); + DFF_X1_LVT \IRData_reg[2] ( + .CK(clk), .D(mem_rdata[2]), .Q(IRData[2]), .QN() + ); + DFF_X1_LVT \IRData_reg[1] ( + .CK(clk), .D(mem_rdata[1]), .Q(IRData[1]), .QN() + ); + DFF_X1_LVT \IRData_reg[0] ( + .CK(clk), .D(mem_rdata[0]), .Q(IRData[0]), .QN() + ); +endmodule + +module reg_file(Rs1, Rs2, Rd, RRs1, RRs2, WRd, WrReg, reset, clk, dftIn, ts_intno31, + ts_no1050, ts_no1051, ts_no1053, ts_no1054, ts_extsi1226, ts_extsi1227, + ts_extsi1228); + input [31:0] WRd; + input [4:0] Rs1, Rs2, Rd; + input WrReg, reset, clk, dftIn, ts_extsi1227, ts_extsi1228, ts_intno31, + ts_extsi1226; + output [31:0] RRs1, RRs2; + output ts_no1050, ts_no1051, ts_no1053, ts_no1054; + + wire [31:0] registers_1__ap, registers_2__ap, registers_3__ap, + registers_4__ap, registers_5__ap, registers_6__ap, + registers_7__ap, registers_8__ap, registers_9__ap, + registers_10__ap, registers_11__ap, registers_12__ap, + registers_13__ap, registers_14__ap, registers_15__ap, + registers_16__ap, registers_17__ap, registers_18__ap, + registers_19__ap, registers_20__ap, registers_21__ap, + registers_22__ap, registers_23__ap, registers_24__ap, + registers_25__ap, registers_26__ap, registers_27__ap, + registers_28__ap, registers_29__ap, registers_30__ap, + registers_31__ap, registers; + wire n_0_0, n_0_32, n_0_33, n_0_34, n_0_35, n_0_36, n_0_37, n_0_38, n_0_39, + n_0_40, n_0_41, n_0_42, n_0_43, n_0_44, n_0_45, n_0_46, n_0_47, n_0_48, + n_0_49, n_0_50, n_0_51, n_0_52, n_0_53, n_0_54, n_0_55, n_0_56, n_0_57, + n_0_58, n_0_59, n_0_60, n_0_61, n_0_31, n_0_30, n_0_29, n_0_28, n_0_27, + n_0_26, n_0_25, n_0_24, n_0_0_0, n_0_0_1, n_0_23, n_0_22, n_0_21, + n_0_20, n_0_19, n_0_18, n_0_17, n_0_16, n_0_0_2, n_0_0_3, n_0_15, + n_0_14, n_0_13, n_0_12, n_0_11, n_0_10, n_0_9, n_0_8, n_0_0_4, n_0_0_5, + n_0_7, n_0_0_6, n_0_6, n_0_0_7, n_0_5, n_0_0_8, n_0_4, n_0_0_9, + n_0_0_10, n_0_3, n_0_0_11, n_0_2, n_0_0_12, n_0_1, n_0_0_13, n_0_0_14, + n_0_0_15, n_0_0_16, n_0_0_17, n_0_0_18, n_0_0_19, n_0_0_20, n_1_0_0, + n_1_0_1, n_1_0_2, n_1_0_3, n_1_0_4, n_1_0_5, n_1_0_6, n_1_0_7, n_1_0_8, + n_1_0_9, n_1_0_10, n_1_0_11, n_1_0_12, n_1_0_13, n_1_0_14, n_1_0_15, + n_1_0_16, n_1_0_17, n_1_0_18, n_1_0_19, n_1_0_20, n_1_0_21, n_1_0_22, + n_1_0_23, n_1_0_24, n_1_0_25, n_1_0_26, n_1_0_27, n_1_0_28, n_1_0_29, + n_1_0_30, n_1_0_31, n_1_0_32, n_1_0_33, n_1_0_34, n_1_0_35, n_1_0_36, + n_1_0_37, n_1_0_38, n_1_0_39, n_1_0_40, n_1_0_41, n_1_0_42, n_1_0_43, + n_1_0_44, n_1_0_45, n_1_0_46, n_1_0_47, n_1_0_48, n_1_0_49, n_1_0_50, + n_1_0_51, n_1_0_52, n_1_0_53, n_1_0_54, n_1_0_55, n_1_0_56, n_1_0_57, + n_1_0_58, n_1_0_59, n_1_0_60, n_1_0_61, n_1_0_62, n_1_0_63, n_1_0_64, + n_1_0_65, n_1_0_66, n_1_0_67, n_1_0_68, n_1_0_69, n_1_0_70, n_1_0_71, + n_1_0_72, n_1_0_73, n_1_0_74, n_1_0_75, n_1_0_76, n_1_0_77, n_1_0_78, + n_1_0_79, n_1_0_80, n_1_0_81, n_1_0_82, n_1_0_83, n_1_0_84, n_1_0_85, + n_1_0_86, n_1_0_87, n_1_0_88, n_1_0_89, n_1_0_90, n_1_0_91, n_1_0_92, + n_1_0_93, n_1_0_94, n_1_0_95, n_1_0_96, n_1_0_97, n_1_0_98, n_1_0_99, + n_1_0_100, n_1_0_101, n_1_0_102, n_1_0_103, n_1_0_104, n_1_0_105, + n_1_0_106, n_1_0_107, n_1_0_108, n_1_0_109, n_1_0_110, n_1_0_111, + n_1_0_112, n_1_0_113, n_1_0_114, n_1_0_115, n_1_0_116, n_1_0_117, + n_1_0_118, n_1_0_119, n_1_0_120, n_1_0_121, n_1_0_122, n_1_0_123, + n_1_0_124, n_1_0_125, n_1_0_126, n_1_0_127, n_1_0_128, n_1_0_129, + n_1_0_130, n_1_0_131, n_1_0_132, n_1_0_133, n_1_0_134, n_1_0_135, + n_1_0_136, n_1_0_137, n_1_0_138, n_1_0_139, n_1_0_140, n_1_0_141, + n_1_0_142, n_1_0_143, n_1_0_144, n_1_0_145, n_1_0_146, n_1_0_147, + n_1_0_148, n_1_0_149, n_1_0_150, n_1_0_151, n_1_0_152, n_1_0_153, + n_1_0_154, n_1_0_155, n_1_0_156, n_1_0_157, n_1_0_158, n_1_0_159, + n_1_0_160, n_1_0_161, n_1_0_162, n_1_0_163, n_1_0_164, n_1_0_165, + n_1_0_166, n_1_0_167, n_1_0_168, n_1_0_169, n_1_0_170, n_1_0_171, + n_1_0_172, n_1_0_173, n_1_0_174, n_1_0_175, n_1_0_176, n_1_0_177, + n_1_0_178, n_1_0_179, n_1_0_180, n_1_0_181, n_1_0_182, n_1_0_183, + n_1_0_184, n_1_0_185, n_1_0_186, n_1_0_187, n_1_0_188, n_1_0_189, + n_1_0_190, n_1_0_191, n_1_0_192, n_1_0_193, n_1_0_194, n_1_0_195, + n_1_0_196, n_1_0_197, n_1_0_198, n_1_0_199, n_1_0_200, n_1_0_201, + n_1_0_202, n_1_0_203, n_1_0_204, n_1_0_205, n_1_0_206, n_1_0_207, + n_1_0_208, n_1_0_209, n_1_0_210, n_1_0_211, n_1_0_212, n_1_0_213, + n_1_0_214, n_1_0_215, n_1_0_216, n_1_0_217, n_1_0_218, n_1_0_219, + n_1_0_220, n_1_0_221, n_1_0_222, n_1_0_223, n_1_0_224, n_1_0_225, + n_1_0_226, n_1_0_227, n_1_0_228, n_1_0_229, n_1_0_230, n_1_0_231, + n_1_0_232, n_1_0_233, n_1_0_234, n_1_0_235, n_1_0_236, n_1_0_237, + n_1_0_238, n_1_0_239, n_1_0_240, n_1_0_241, n_1_0_242, n_1_0_243, + n_1_0_244, n_1_0_245, n_1_0_246, n_1_0_247, n_1_0_248, n_1_0_249, + n_1_0_250, n_1_0_251, n_1_0_252, n_1_0_253, n_1_0_254, n_1_0_255, + n_1_0_256, n_1_0_257, n_1_0_258, n_1_0_259, n_1_0_260, n_1_0_261, + n_1_0_262, n_1_0_263, n_1_0_264, n_1_0_265, n_1_0_266, n_1_0_267, + n_1_0_268, n_1_0_269, n_1_0_270, n_1_0_271, n_1_0_272, n_1_0_273, + n_1_0_274, n_1_0_275, n_1_0_276, n_1_0_277, n_1_0_278, n_1_0_279, + n_1_0_280, n_1_0_281, n_1_0_282, n_1_0_283, n_1_0_284, n_1_0_285, + n_1_0_286, n_1_0_287, n_1_0_288, n_1_0_289, n_1_0_290, n_1_0_291, + n_1_0_292, n_1_0_293, n_1_0_294, n_1_0_295, n_1_0_296, n_1_0_297, + n_1_0_298, n_1_0_299, n_1_0_300, n_1_0_301, n_1_0_302, n_1_0_303, + n_1_0_304, n_1_0_305, n_1_0_306, n_1_0_307, n_1_0_308, n_1_0_309, + n_1_0_310, n_1_0_311, n_1_0_312, n_1_0_313, n_1_0_314, n_1_0_315, + n_1_0_316, n_1_0_317, n_1_0_318, n_1_0_319, n_1_0_320, n_1_0_321, + n_1_0_322, n_1_0_323, n_1_0_324, n_1_0_325, n_1_0_326, n_1_0_327, + n_1_0_328, n_1_0_329, n_1_0_330, n_1_0_331, n_1_0_332, n_1_0_333, + n_1_0_334, n_1_0_335, n_1_0_336, n_1_0_337, n_1_0_338, n_1_0_339, + n_1_0_340, n_1_0_341, n_1_0_342, n_1_0_343, n_1_0_344, n_1_0_345, + n_1_0_346, n_1_0_347, n_1_0_348, n_1_0_349, n_1_0_350, n_1_0_351, + n_1_0_352, n_1_0_353, n_1_0_354, n_1_0_355, n_1_0_356, n_1_0_357, + n_1_0_358, n_1_0_359, n_1_0_360, n_1_0_361, n_1_0_362, n_1_0_363, + n_1_0_364, n_1_0_365, n_1_0_366, n_1_0_367, n_1_0_368, n_1_0_369, + n_1_0_370, n_1_0_371, n_1_0_372, n_1_0_373, n_1_0_374, n_1_0_375, + n_1_0_376, n_1_0_377, n_1_0_378, n_1_0_379, n_1_0_380, n_1_0_381, + n_1_0_382, n_1_0_383, n_1_0_384, n_1_0_385, n_1_0_386, n_1_0_387, + n_1_0_388, n_1_0_389, n_1_0_390, n_1_0_391, n_1_0_392, n_1_0_393, + n_1_0_394, n_1_0_395, n_1_0_396, n_1_0_397, n_1_0_398, n_1_0_399, + n_1_0_400, n_1_0_401, n_1_0_402, n_1_0_403, n_1_0_404, n_1_0_405, + n_1_0_406, n_1_0_407, n_1_0_408, n_1_0_409, n_1_0_410, n_1_0_411, + n_1_0_412, n_1_0_413, n_1_0_414, n_1_0_415, n_1_0_416, n_1_0_417, + n_1_0_418, n_1_0_419, n_1_0_420, n_1_0_421, n_1_0_422, n_1_0_423, + n_1_0_424, n_1_0_425, n_1_0_426, n_1_0_427, n_1_0_428, n_1_0_429, + n_1_0_430, n_1_0_431, n_1_0_432, n_1_0_433, n_1_0_434, n_1_0_435, + n_1_0_436, n_1_0_437, n_1_0_438, n_1_0_439, n_1_0_440, n_1_0_441, + n_1_0_442, n_1_0_443, n_1_0_444, n_1_0_445, n_1_0_446, n_1_0_447, + n_1_0_448, n_1_0_449, n_1_0_450, n_1_0_451, n_1_0_452, n_1_0_453, + n_1_0_454, n_1_0_455, n_1_0_456, n_1_0_457, n_1_0_458, n_1_0_459, + n_1_0_460, n_1_0_461, n_1_0_462, n_1_0_463, n_1_0_464, n_1_0_465, + n_1_0_466, n_1_0_467, n_1_0_468, n_1_0_469, n_1_0_470, n_1_0_471, + n_1_0_472, n_1_0_473, n_1_0_474, n_1_0_475, n_1_0_476, n_1_0_477, + n_1_0_478, n_1_0_479, n_1_0_480, n_1_0_481, n_1_0_482, n_1_0_483, + n_1_0_484, n_1_0_485, n_1_0_486, n_1_0_487, n_1_0_488, n_1_0_489, + n_1_0_490, n_1_0_491, n_1_0_492, n_1_0_493, n_1_0_494, n_1_0_495, + n_1_0_496, n_1_0_497, n_1_0_498, n_1_0_499, n_1_0_500, n_1_0_501, + n_1_0_502, n_1_0_503, n_1_0_504, n_1_0_505, n_1_0_506, n_1_0_507, + n_1_0_508, n_1_0_509, n_1_0_510, n_1_0_511, n_1_0_512, n_1_0_513, + n_1_0_514, n_1_0_515, n_1_0_516, n_1_0_517, n_1_0_518, n_1_0_519, + n_1_0_520, n_1_0_521, n_1_0_522, n_1_0_523, n_1_0_524, n_1_0_525, + n_1_0_526, n_1_0_527, n_1_0_528, n_1_0_529, n_1_0_530, n_1_0_531, + n_1_0_532, n_1_0_533, n_1_0_534, n_1_0_535, n_1_0_536, n_1_0_537, + n_1_0_538, n_1_0_539, n_1_0_540, n_1_0_541, n_1_0_542, n_1_0_543, + n_1_0_544, n_1_0_545, n_1_0_546, n_1_0_547, n_1_0_548, n_1_0_549, + n_1_0_550, n_1_0_551, n_1_0_552, n_1_0_553, n_1_0_554, n_1_0_555, + n_1_0_556, n_1_0_557, n_1_0_558, n_1_0_559, n_1_0_560, n_1_0_561, + n_1_0_562, n_1_0_563, n_1_0_564, n_1_0_565, n_1_0_566, n_1_0_567, + n_1_0_568, n_1_0_569, n_1_0_570, n_1_0_571, n_1_0_572, n_1_0_573, + n_1_0_574, n_1_0_575, n_1_0_576, n_1_0_577, n_1_0_578, n_1_0_579, + n_1_0_580, n_1_0_581, n_1_0_582, n_1_0_583, n_1_0_584, n_1_0_585, + n_1_0_586, n_1_0_587, n_1_0_588, n_1_0_589, n_1_0_590, n_1_0_591, + n_1_0_592, n_1_0_593, n_1_0_594, n_1_0_595, n_1_0_596, n_1_0_597, + n_1_0_598, n_1_0_599, n_1_0_600, n_1_0_601, n_1_0_602, n_1_0_603, + n_1_0_604, n_1_0_605, n_1_0_606, n_1_0_607, n_1_0_608, n_1_0_609, + n_1_0_610, n_1_0_611, n_1_0_612, n_1_0_613, n_1_0_614, n_1_0_615, + n_1_0_616, n_1_0_617, n_1_0_618, n_1_0_619, n_1_0_620, n_1_0_621, + n_1_0_622, n_1_0_623, n_1_0_624, n_1_0_625, n_1_0_626, n_1_0_627, + n_1_0_628, n_1_0_629, n_1_0_630, n_1_0_631, n_1_0_632, n_1_0_633, + n_1_0_634, n_1_0_635, n_1_0_636, n_1_0_637, n_1_0_638, n_1_0_639, + n_1_0_640, n_1_0_641, n_1_0_642, n_1_0_643, n_1_0_644, n_1_0_645, + n_1_0_646, n_1_0_647, n_1_0_648, n_1_0_649, n_1_0_650, n_1_0_651, + n_1_0_652, n_1_0_653, n_1_0_654, n_1_0_655, n_1_0_656, n_1_0_657, + n_1_0_658, n_1_0_659, n_1_0_660, n_1_0_661, n_1_0_662, n_1_0_663, + n_1_0_664, n_1_0_665, n_1_0_666, n_1_0_667, n_1_0_668, n_1_0_669, + n_1_0_670, n_1_0_671, n_1_0_672, n_1_0_673, n_1_0_674, n_1_0_675, + n_1_0_676, n_1_0_677, n_1_0_678, n_1_0_679, n_1_0_680, n_1_0_681, + n_1_0_682, n_1_0_683, n_1_0_684, n_1_0_685, n_1_0_686, n_1_0_687, + n_1_0_688, n_1_0_689, n_1_0_690, n_1_0_691, n_1_0_692, n_1_0_693, + n_1_0_694, n_1_0_695, n_1_0_696, n_1_0_697, n_1_0_698, n_1_0_699, + n_1_0_700, n_1_0_701, n_1_0_702, n_1_0_703, n_1_0_704, n_1_0_705, + n_1_0_706, n_1_0_707, n_1_0_708, n_1_0_709, n_1_0_710, n_1_0_711, + n_1_0_712, n_1_0_713, n_1_0_714, n_1_0_715, n_1_0_716, n_1_0_717, + n_1_0_718, n_1_0_719, n_1_0_720, n_1_0_721, n_1_0_722, n_1_0_723, + n_1_0_724, n_1_0_725, n_1_0_726, n_1_0_727, n_1_0_728, n_1_0_729, + n_1_0_730, n_1_0_731, n_1_0_732, n_1_0_733, n_1_0_734, n_1_0_735, + n_1_0_736, n_1_0_737, n_1_0_738, n_1_0_739, n_1_0_740, n_1_0_741, + n_1_0_742, n_1_0_743, n_1_0_744, n_1_0_745, n_1_0_746, n_1_0_747, + n_1_0_748, n_1_0_749, n_1_0_750, n_1_0_751, n_1_0_752, n_1_0_753, + n_1_0_754, n_1_0_755, n_1_0_756, n_1_0_757, n_1_0_758, n_1_0_759, + n_1_0_760, n_1_0_761, n_1_0_762, n_1_0_763, n_1_0_764, n_1_0_765, + n_1_0_766, n_1_0_767, n_1_0_768, n_1_0_769, n_1_0_770, n_1_0_771, + n_1_0_772, n_1_0_773, n_1_0_774, n_1_0_775, n_1_0_776, n_1_0_777, + n_1_0_778, n_1_0_779, n_1_0_780, n_1_0_781, n_1_0_782, n_1_0_783, + n_1_0_784, n_1_0_785, n_1_0_786, n_1_0_787, n_1_0_788, n_1_0_789, + n_1_0_790, n_1_0_791, n_1_0_792, n_1_0_793, n_1_0_794, n_1_0_795, + n_1_0_796, n_1_0_797, n_1_0_798, n_1_0_799, n_1_0_800, n_1_0_801, + n_1_0_802, n_1_0_803, n_1_0_804, n_1_0_805, n_1_0_806, n_1_0_807, + n_1_0_808, n_1_0_809, n_1_0_810, n_1_0_811, n_1_0_812, n_1_0_813, + n_1_0_814, n_1_0_815, n_1_0_816, n_1_0_817, n_1_0_818, n_1_0_819, + n_1_0_820, n_1_0_821, n_1_0_822, n_1_0_823, n_1_0_824, n_1_0_825, + n_1_0_826, n_1_0_827, n_1_0_828, n_1_0_829, n_1_0_830, n_1_0_831, + n_1_0_832, n_1_0_833, n_1_0_834, n_1_0_835, n_1_0_836, n_1_0_837, + n_1_0_838, n_1_0_839, n_1_0_840, n_1_0_841, n_1_0_842, n_1_0_843, + n_1_0_844, n_1_0_845, n_1_0_846, n_1_0_847, n_1_0_848, n_1_0_849, + n_1_0_850, n_1_0_851, n_1_0_852, n_1_0_853, n_1_0_854, n_1_0_855, + n_1_0_856, n_1_0_857, n_1_0_858, n_1_0_859, n_1_0_860, n_1_0_861, + n_1_0_862, n_1_0_863, n_1_0_864, n_1_0_865, n_1_0_866, n_1_0_867, + n_1_0_868, n_1_0_869, n_1_0_870, n_1_0_871, n_1_0_872, n_1_0_873, + n_1_0_874, n_1_0_875, n_1_0_876, n_1_0_877, n_1_0_878, n_1_0_879, + n_1_0_880, n_1_0_881, n_1_0_882, n_1_0_883, n_1_0_884, n_1_0_885, + n_1_0_886, n_1_0_887, n_1_0_888, n_1_0_889, n_1_0_890, n_1_0_891, + n_1_0_892, n_1_0_893, n_1_0_894, n_1_0_895, n_1_0_896, n_1_0_897, + n_1_0_898, n_1_0_899, n_1_0_900, n_1_0_901, n_1_0_902, n_1_0_903, + n_1_0_904, n_1_0_905, n_1_0_906, n_1_0_907, n_1_0_908, n_1_0_909, + n_1_0_910, n_1_0_911, n_1_0_912, n_1_0_913, n_1_0_914, n_1_0_915, + n_1_0_916, n_1_0_917, n_1_0_918, n_1_0_919, n_1_0_920, n_1_0_921, + n_1_0_922, n_1_0_923, n_1_0_924, n_1_0_925, n_1_0_926, n_1_0_927, + n_1_0_928, n_1_0_929, n_1_0_930, n_1_0_931, n_1_0_932, n_1_0_933, + n_1_0_934, n_1_0_935, n_1_0_936, n_1_0_937, n_1_0_938, n_1_0_939, + n_1_0_940, n_1_0_941, n_1_0_942, n_1_0_943, n_1_0_944, n_1_0_945, + n_1_0_946, n_1_0_947, n_1_0_948, n_1_0_949, n_1_0_950, n_1_0_951, + n_1_0_952, n_1_0_953, n_1_0_954, n_1_0_955, n_1_0_956, n_1_0_957, + n_1_0_958, n_1_0_959, n_1_0_960, n_1_0_961, n_1_0_962, n_1_0_963, + n_1_0_964, n_1_0_965, n_1_0_966, n_1_0_967, n_1_0_968, n_1_0_969, + n_1_0_970, n_1_0_971, n_1_0_972, n_1_0_973, n_1_0_974, n_1_0_975, + n_1_0_976, n_1_0_977, n_1_0_978, n_1_0_979, n_1_0_980, n_1_0_981, + n_1_0_982, n_1_0_983, n_1_0_984, n_1_0_985, n_1_0_986, n_1_0_987, + n_1_0_988, n_1_0_989, n_1_0_990, n_1_0_991, n_1_0_992, n_1_0_993, + n_1_0_994, n_1_0_995, n_1_0_996, n_1_0_997, n_1_0_998, n_1_0_999, + n_1_0_1000, n_1_0_1001, n_1_0_1002, n_1_0_1003, n_1_0_1004, n_1_0_1005, + n_1_0_1006, n_1_0_1007, n_1_0_1008, n_1_0_1009, n_1_0_1010, n_1_0_1011, + n_1_0_1012, n_1_0_1013, n_1_0_1014, n_1_0_1015, n_1_0_1016, n_1_0_1017, + n_1_0_1018, n_1_0_1019, n_1_0_1020, n_1_0_1021, n_1_0_1022, n_1_0_1023, + n_1_0_1024, n_1_0_1025, n_1_0_1026, n_1_0_1027, n_1_0_1028, n_1_0_1029, + n_1_0_1030, n_1_0_1031, n_1_0_1032, n_1_0_1033, n_1_0_1034, n_1_0_1035, + n_1_0_1036, n_1_0_1037, n_1_0_1038, n_1_0_1039, n_1_0_1040, n_1_0_1041, + n_1_0_1042, n_1_0_1043, n_1_0_1044, n_1_0_1045, n_1_0_1046, n_1_0_1047, + n_1_0_1048, n_1_0_1049, n_1_0_1050, n_1_0_1051, n_1_0_1052, n_1_0_1053, + n_1_0_1054, n_1_0_1055, n_1_0_1056, n_1_0_1057, n_1_0_1058, n_1_0_1059, + n_1_0_1060, n_1_0_1061, n_1_0_1062, n_1_0_1063, n_1_0_1064, n_1_0_1065, + n_1_0_1066, n_1_0_1067, n_1_0_1068, n_1_0_1069, n_1_0_1070, n_1_0_1071, + n_1_0_1072, n_1_0_1073, n_1_0_1074, n_1_0_1075, n_1_0_1076, n_1_0_1077, + n_1_0_1078, n_1_0_1079, n_1_0_1080, n_1_0_1081, n_1_0_1082, n_1_0_1083, + n_1_0_1084, n_1_0_1085, n_1_0_1086, n_1_0_1087, n_1_0_1088, n_1_0_1089, + n_1_0_1090, n_1_0_1091, n_1_0_1092, n_1_0_1093, n_1_0_1094, n_1_0_1095, + n_1_0_1096, n_1_0_1097, n_1_0_1098, n_1_0_1099, n_1_0_1100, n_1_0_1101, + n_1_0_1102, n_1_0_1103, n_1_0_1104, n_1_0_1105, n_1_0_1106, n_1_0_1107, + n_1_0_1108, n_1_0_1109, n_1_0_1110, n_1_0_1111, n_1_0_1112, n_1_0_1113, + n_1_0_1114, n_1_0_1115, n_1_0_1116, n_1_0_1117, n_1_0_1118, n_1_0_1119, + n_1_0_1120, n_1_0_1121, n_1_0_1122, n_1_0_1123, n_1_0_1124, n_1_0_1125, + n_1_0_1126, n_1_0_1127, n_1_0_1128, n_1_0_1129, n_1_0_1130, n_1_0_1131, + n_1_0_1132, n_1_0_1133, n_1_0_1134, n_1_0_1135, n_1_0_1136, n_1_0_1137, + n_1_0_1138, n_1_0_1139, n_1_0_1140, n_1_0_1141, n_1_0_1142, n_1_0_1143, + n_1_0_1144, n_1_0_1145, n_1_0_1146, n_1_0_1147, n_1_0_1148, n_1_0_1149, + n_1_0_1150, n_1_0_1151, n_1_0_1152, n_1_0_1153, n_1_0_1154, n_1_0_1155, + n_1_0_1156, n_1_0_1157, n_1_0_1158, n_1_0_1159, n_1_0_1160, n_1_0_1161, + n_1_0_1162, n_1_0_1163, n_1_0_1164, n_1_0_1165, n_1_0_1166, n_1_0_1167, + n_1_0_1168, n_1_0_1169, n_1_0_1170, n_1_0_1171, n_1_0_1172, n_1_0_1173, + n_1_0_1174, n_1_0_1175, n_1_0_1176, n_1_0_1177, n_1_0_1178, n_1_0_1179, + n_1_0_1180, n_1_0_1181, n_1_0_1182, n_1_0_1183, n_1_0_1184, n_1_0_1185, + n_1_0_1186, n_1_0_1187, n_1_0_1188, n_1_0_1189, n_1_0_1190, n_1_0_1191, + n_1_0_1192, n_1_0_1193, n_1_0_1194, n_1_0_1195, n_1_0_1196, n_1_0_1197, + n_1_0_1198, n_1_0_1199, n_1_0_1200, n_1_0_1201, n_1_0_1202, n_1_0_1203, + n_1_0_1204, n_1_0_1205, n_1_0_1206, n_1_0_1207, n_1_0_1208, n_1_0_1209, + n_1_0_1210, n_1_0_1211, n_1_0_1212, n_1_0_1213, n_1_0_1214, n_1_0_1215, + n_1_0_1216, n_1_0_1217, n_1_0_1218, n_1_0_1219, n_1_0_1220, n_1_0_1221, + n_1_0_1222, n_1_0_1223, n_1_0_1224, n_1_0_1225, n_1_0_1226, n_1_0_1227, + n_1_0_1228, n_1_0_1229, n_1_0_1230, n_1_0_1231, n_1_0_1232, n_1_0_1233, + n_1_0_1234, n_1_0_1235, n_1_0_1236, n_1_0_1237, n_1_0_1238, n_1_0_1239, + n_1_0_1240, n_1_0_1241, n_1_0_1242, n_1_0_1243, n_1_0_1244, n_1_0_1245, + n_1_0_1246, n_1_0_1247, n_1_0_1248, n_1_0_1249, n_1_0_1250, n_1_0_1251, + n_1_0_1252, n_1_0_1253, n_1_0_1254, n_1_0_1255, n_1_0_1256, n_1_0_1257, + n_1_0_1258, n_1_0_1259, n_1_0_1260, n_1_0_1261, n_1_0_1262, n_1_0_1263, + n_1_0_1264, n_1_0_1265, n_1_0_1266, n_1_0_1267, n_1_0_1268, n_1_0_1269, + n_1_0_1270, n_1_0_1271, n_1_0_1272, n_1_0_1273, n_1_0_1274, n_1_0_1275, + n_1_0_1276, n_1_0_1277, n_1_0_1278, n_1_0_1279, n_1_0_1280, n_1_0_1281, + n_1_0_1282, n_1_0_1283, n_1_0_1284, n_1_0_1285, n_1_0_1286, n_1_0_1287, + n_1_0_1288, n_1_0_1289, n_1_0_1290, n_1_0_1291, n_1_0_1292, n_1_0_1293, + n_1_0_1294, n_1_0_1295, n_1_0_1296, n_1_0_1297, n_1_0_1298, n_1_0_1299, + n_1_0_1300, n_1_0_1301, n_1_0_1302, n_1_0_1303, n_1_0_1304, n_1_0_1305, + n_1_0_1306, n_1_0_1307, n_1_0_1308, n_1_0_1309, ts_pbuf_extsi1227_, + ts_pbuf_extsi1228_, ts_pbuf_extsi1226_; + + INV_X1_LVT i_0_0_79( + .A(reset), .ZN(n_0_0_16) + ); + AND2_X1_LVT i_0_0_31( + .A1(n_0_0_16), .A2(WRd[31]), .ZN(registers[31]) + ); + INV_X1_LVT i_0_0_81( + .A(Rd[1]), .ZN(n_0_0_18) + ); + INV_X1_LVT i_0_0_80( + .A(Rd[0]), .ZN(n_0_0_17) + ); + NAND3_X1_LVT i_0_0_69( + .A1(n_0_0_18), .A2(n_0_0_17), .A3(Rd[2]), .ZN(n_0_0_9) + ); + NAND3_X1_LVT i_0_0_41( + .A1(Rd[3]), .A2(WrReg), .A3(Rd[4]), .ZN(n_0_0_1) + ); + OAI21_X1_LVT i_0_0_35( + .A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_1), .ZN(n_0_28) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[28]_reg ( + .CK(clk), .E(n_0_28), .GCK(n_0_58), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[28][31] ( + .CK(n_0_58), .D(registers[31]), .Q(registers_28__ap[31]), .QN(), .SE(dftIn), + .SI(ts_pbuf_extsi1227_) + ); + INV_X1_LVT i_1_0_1370( + .A(Rs1[0]), .ZN(n_1_0_1306) + ); + NAND3_X1_LVT i_1_0_1354( + .A1(n_1_0_1306), .A2(Rs1[3]), .A3(Rs1[4]), .ZN(n_1_0_1290) + ); + INV_X1_LVT i_1_0_1373( + .A(Rs1[2]), .ZN(n_1_0_1309) + ); + OR2_X1_LVT i_1_0_1348( + .A1(n_1_0_1309), .A2(Rs1[1]), .ZN(n_1_0_1284) + ); + NOR2_X1_LVT i_1_0_1347( + .A1(n_1_0_1290), .A2(n_1_0_1284), .ZN(n_1_0_1283) + ); + NOR4_X1_LVT i_1_0_1342( + .A1(n_1_0_1284), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), .ZN(n_1_0_1278) + ); + INV_X1_LVT i_0_0_83( + .A(WrReg), .ZN(n_0_0_20) + ); + OR3_X1_LVT i_0_0_77( + .A1(n_0_0_20), .A2(Rd[4]), .A3(Rd[3]), .ZN(n_0_0_14) + ); + OAI21_X1_LVT i_0_0_68( + .A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_9), .ZN(n_0_4) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[4]_reg ( + .CK(clk), .E(n_0_4), .GCK(n_0_34), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[4][31] ( + .CK(n_0_34), .D(registers[31]), .Q(registers_4__ap[31]), .QN(), .SE(dftIn), + .SI(ts_pbuf_extsi1228_) + ); + AOI22_X1_LVT i_1_0_1320( + .A1(registers_28__ap[31]), .A2(n_1_0_1283), .B1(n_1_0_1278), .B2(registers_4__ap[31]), + .ZN(n_1_0_1256) + ); + NAND2_X1_LVT i_0_0_70( + .A1(n_0_0_18), .A2(n_0_0_17), .ZN(n_0_0_10) + ); + INV_X1_LVT i_0_0_82( + .A(Rd[4]), .ZN(n_0_0_19) + ); + OR3_X1_LVT i_0_0_51( + .A1(n_0_0_20), .A2(n_0_0_19), .A3(Rd[3]), .ZN(n_0_0_3) + ); + OR2_X1_LVT i_0_0_50( + .A1(n_0_0_3), .A2(Rd[2]), .ZN(n_0_0_2) + ); + OAI21_X1_LVT i_0_0_49( + .A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_2), .ZN(n_0_16) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[16]_reg ( + .CK(clk), .E(n_0_16), .GCK(n_0_46), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[16][31] ( + .CK(n_0_46), .D(registers[31]), .Q(registers_16__ap[31]), .QN(), .SE(dftIn), + .SI(ts_intno31) + ); + INV_X1_LVT i_1_0_1371( + .A(Rs1[3]), .ZN(n_1_0_1307) + ); + NAND3_X1_LVT i_1_0_1363( + .A1(n_1_0_1307), .A2(n_1_0_1306), .A3(Rs1[4]), .ZN(n_1_0_1299) + ); + OR2_X1_LVT i_1_0_1357( + .A1(Rs1[1]), .A2(Rs1[2]), .ZN(n_1_0_1293) + ); + NOR2_X1_LVT i_1_0_1331( + .A1(n_1_0_1299), .A2(n_1_0_1293), .ZN(n_1_0_1267) + ); + NAND2_X1_LVT i_1_0_1365( + .A1(Rs1[1]), .A2(Rs1[2]), .ZN(n_1_0_1301) + ); + NAND3_X1_LVT i_1_0_1344( + .A1(Rs1[4]), .A2(Rs1[3]), .A3(Rs1[0]), .ZN(n_1_0_1280) + ); + NOR2_X1_LVT i_1_0_1330( + .A1(n_1_0_1301), .A2(n_1_0_1280), .ZN(n_1_0_1266) + ); + NAND3_X1_LVT i_0_0_63( + .A1(Rd[2]), .A2(Rd[1]), .A3(Rd[0]), .ZN(n_0_0_6) + ); + OAI21_X1_LVT i_0_0_32( + .A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_1), .ZN(n_0_31) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[31]_reg ( + .CK(clk), .E(n_0_31), .GCK(n_0_61), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[31][31] ( + .CK(n_0_61), .D(registers[31]), .Q(registers_31__ap[31]), .QN(), .SE(dftIn), + .SI(registers_4__ap[31]) + ); + AOI22_X1_LVT i_1_0_1329( + .A1(registers_16__ap[31]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[31]), + .ZN(n_1_0_1265) + ); + NAND3_X1_LVT i_0_0_65( + .A1(n_0_0_17), .A2(Rd[1]), .A3(Rd[2]), .ZN(n_0_0_7) + ); + OAI21_X1_LVT i_0_0_64( + .A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_7), .ZN(n_0_6) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[6]_reg ( + .CK(clk), .E(n_0_6), .GCK(n_0_36), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[6][31] ( + .CK(n_0_36), .D(registers[31]), .Q(registers_6__ap[31]), .QN(), .SE(dftIn), + .SI(registers_31__ap[31]) + ); + NOR4_X1_LVT i_1_0_1364( + .A1(n_1_0_1301), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), .ZN(n_1_0_1300) + ); + INV_X1_LVT i_1_0_1372( + .A(Rs1[4]), .ZN(n_1_0_1308) + ); + NAND3_X1_LVT i_1_0_1339( + .A1(n_1_0_1308), .A2(n_1_0_1307), .A3(Rs1[0]), .ZN(n_1_0_1275) + ); + NOR2_X1_LVT i_1_0_1338( + .A1(n_1_0_1293), .A2(n_1_0_1275), .ZN(n_1_0_1274) + ); + NAND2_X1_LVT i_0_0_78( + .A1(n_0_0_18), .A2(Rd[0]), .ZN(n_0_0_15) + ); + OR2_X1_LVT i_0_0_76( + .A1(n_0_0_14), .A2(Rd[2]), .ZN(n_0_0_13) + ); + OAI21_X1_LVT i_0_0_75( + .A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_13), .ZN(n_0_1) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[1]_reg ( + .CK(clk), .E(n_0_1), .GCK(n_0_0), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[1][31] ( + .CK(n_0_0), .D(registers[31]), .Q(registers_1__ap[31]), .QN(), .SE(dftIn), + .SI(ts_pbuf_extsi1226_) + ); + AOI22_X1_LVT i_1_0_1319( + .A1(registers_6__ap[31]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[31]), + .ZN(n_1_0_1255) + ); + OAI21_X1_LVT i_0_0_42( + .A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_3), .ZN(n_0_23) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[23]_reg ( + .CK(clk), .E(n_0_23), .GCK(n_0_53), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[23][31] ( + .CK(n_0_53), .D(registers[31]), .Q(registers_23__ap[31]), .QN(), .SE(dftIn), + .SI(registers_1__ap[31]) + ); + NAND3_X1_LVT i_1_0_1360( + .A1(n_1_0_1307), .A2(Rs1[0]), .A3(Rs1[4]), .ZN(n_1_0_1296) + ); + NOR2_X1_LVT i_1_0_1328( + .A1(n_1_0_1301), .A2(n_1_0_1296), .ZN(n_1_0_1264) + ); + NOR2_X1_LVT i_1_0_1327( + .A1(n_1_0_1301), .A2(n_1_0_1275), .ZN(n_1_0_1263) + ); + OAI21_X1_LVT i_0_0_62( + .A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_6), .ZN(n_0_7) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[7]_reg ( + .CK(clk), .E(n_0_7), .GCK(n_0_37), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[7][31] ( + .CK(n_0_37), .D(registers[31]), .Q(registers_7__ap[31]), .QN(), .SE(dftIn), + .SI(registers_6__ap[31]) + ); + AOI22_X1_LVT i_1_0_1326( + .A1(registers_23__ap[31]), .A2(n_1_0_1264), .B1(n_1_0_1263), .B2(registers_7__ap[31]), + .ZN(n_1_0_1262) + ); + INV_X1_LVT i_1_0_1325( + .A(n_1_0_1262), .ZN(n_1_0_1261) + ); + NAND2_X1_LVT i_1_0_1362( + .A1(n_1_0_1309), .A2(Rs1[1]), .ZN(n_1_0_1298) + ); + NOR2_X1_LVT i_1_0_1359( + .A1(n_1_0_1298), .A2(n_1_0_1296), .ZN(n_1_0_1295) + ); + NAND2_X1_LVT i_0_0_72( + .A1(Rd[1]), .A2(Rd[0]), .ZN(n_0_0_11) + ); + OAI21_X1_LVT i_0_0_46( + .A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_2), .ZN(n_0_19) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[19]_reg ( + .CK(clk), .E(n_0_19), .GCK(n_0_49), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[19][31] ( + .CK(n_0_49), .D(registers[31]), .Q(registers_19__ap[31]), .QN(), .SE(dftIn), + .SI(registers_23__ap[31]) + ); + NAND3_X1_LVT i_0_0_67( + .A1(n_0_0_18), .A2(Rd[0]), .A3(Rd[2]), .ZN(n_0_0_8) + ); + OAI21_X1_LVT i_0_0_66( + .A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_8), .ZN(n_0_5) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[5]_reg ( + .CK(clk), .E(n_0_5), .GCK(n_0_35), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[5][31] ( + .CK(n_0_35), .D(registers[31]), .Q(registers_5__ap[31]), .QN(), .SE(dftIn), + .SI(registers_7__ap[31]) + ); + NOR2_X1_LVT i_1_0_1337( + .A1(n_1_0_1284), .A2(n_1_0_1275), .ZN(n_1_0_1273) + ); + AOI221_X1_LVT i_1_0_1318( + .A(n_1_0_1261), .B1(n_1_0_1295), .B2(registers_19__ap[31]), .C1(registers_5__ap[31]), + .C2(n_1_0_1273), .ZN(n_1_0_1254) + ); + NAND2_X1_LVT i_0_0_74( + .A1(n_0_0_17), .A2(Rd[1]), .ZN(n_0_0_12) + ); + NAND3_X1_LVT i_0_0_61( + .A1(n_0_0_19), .A2(WrReg), .A3(Rd[3]), .ZN(n_0_0_5) + ); + OR2_X1_LVT i_0_0_60( + .A1(n_0_0_5), .A2(Rd[2]), .ZN(n_0_0_4) + ); + OAI21_X1_LVT i_0_0_57( + .A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_4), .ZN(n_0_10) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[10]_reg ( + .CK(clk), .E(n_0_10), .GCK(n_0_40), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[10][31] ( + .CK(n_0_40), .D(registers[31]), .Q(registers_10__ap[31]), .QN(), .SE(dftIn), + .SI(registers_16__ap[31]) + ); + NAND3_X1_LVT i_1_0_1352( + .A1(n_1_0_1308), .A2(n_1_0_1306), .A3(Rs1[3]), .ZN(n_1_0_1288) + ); + NOR2_X1_LVT i_1_0_1351( + .A1(n_1_0_1298), .A2(n_1_0_1288), .ZN(n_1_0_1287) + ); + NOR2_X1_LVT i_1_0_1349( + .A1(n_1_0_1298), .A2(n_1_0_1290), .ZN(n_1_0_1285) + ); + OR2_X1_LVT i_0_0_40( + .A1(n_0_0_1), .A2(Rd[2]), .ZN(n_0_0_0) + ); + OAI21_X1_LVT i_0_0_37( + .A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_0), .ZN(n_0_26) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[26]_reg ( + .CK(clk), .E(n_0_26), .GCK(n_0_56), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[26][31] ( + .CK(n_0_56), .D(registers[31]), .Q(registers_26__ap[31]), .QN(), .SE(dftIn), + .SI(registers_28__ap[31]) + ); + OAI21_X1_LVT i_0_0_59( + .A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_4), .ZN(n_0_8) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[8]_reg ( + .CK(clk), .E(n_0_8), .GCK(n_0_38), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[8][31] ( + .CK(n_0_38), .D(registers[31]), .Q(registers_8__ap[31]), .QN(), .SE(dftIn), + .SI(registers_5__ap[31]) + ); + NOR2_X1_LVT i_1_0_1346( + .A1(n_1_0_1293), .A2(n_1_0_1288), .ZN(n_1_0_1282) + ); + AOI222_X1_LVT i_1_0_1317( + .A1(registers_10__ap[31]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[31]), + .C1(registers_8__ap[31]), .C2(n_1_0_1282), .ZN(n_1_0_1253) + ); + NAND4_X1_LVT i_1_0_1316( + .A1(n_1_0_1265), .A2(n_1_0_1255), .A3(n_1_0_1254), .A4(n_1_0_1253), .ZN(n_1_0_1252) + ); + NAND3_X1_LVT i_1_0_1356( + .A1(n_1_0_1308), .A2(Rs1[3]), .A3(Rs1[0]), .ZN(n_1_0_1292) + ); + NOR2_X1_LVT i_1_0_1355( + .A1(n_1_0_1293), .A2(n_1_0_1292), .ZN(n_1_0_1291) + ); + OAI21_X1_LVT i_0_0_58( + .A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_4), .ZN(n_0_9) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[9]_reg ( + .CK(clk), .E(n_0_9), .GCK(n_0_39), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[9][31] ( + .CK(n_0_39), .D(registers[31]), .Q(registers_9__ap[31]), .QN(), .SE(dftIn), + .SI(registers_8__ap[31]) + ); + OAI21_X1_LVT i_0_0_34( + .A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_1), .ZN(n_0_29) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[29]_reg ( + .CK(clk), .E(n_0_29), .GCK(n_0_59), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[29][31] ( + .CK(n_0_59), .D(registers[31]), .Q(registers_29__ap[31]), .QN(), .SE(dftIn), + .SI(registers_26__ap[31]) + ); + NOR2_X1_LVT i_1_0_1340( + .A1(n_1_0_1284), .A2(n_1_0_1280), .ZN(n_1_0_1276) + ); + AOI221_X1_LVT i_1_0_1315( + .A(n_1_0_1252), .B1(n_1_0_1291), .B2(registers_9__ap[31]), .C1(registers_29__ap[31]), + .C2(n_1_0_1276), .ZN(n_1_0_1251) + ); + OAI21_X1_LVT i_0_0_47( + .A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_2), .ZN(n_0_18) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[18]_reg ( + .CK(clk), .E(n_0_18), .GCK(n_0_48), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[18][31] ( + .CK(n_0_48), .D(registers[31]), .Q(registers_18__ap[31]), .QN(), .SE(dftIn), + .SI(registers_19__ap[31]) + ); + NOR2_X1_LVT i_1_0_1361( + .A1(n_1_0_1299), .A2(n_1_0_1298), .ZN(n_1_0_1297) + ); + NOR2_X1_LVT i_1_0_1336( + .A1(n_1_0_1301), .A2(n_1_0_1290), .ZN(n_1_0_1272) + ); + OAI21_X1_LVT i_0_0_33( + .A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_1), .ZN(n_0_30) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[30]_reg ( + .CK(clk), .E(n_0_30), .GCK(n_0_60), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[30][31] ( + .CK(n_0_60), .D(registers[31]), .Q(registers_30__ap[31]), .QN(), .SE(dftIn), + .SI(registers_29__ap[31]) + ); + AOI22_X1_LVT i_1_0_1314( + .A1(registers_18__ap[31]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[31]), + .ZN(n_1_0_1250) + ); + OAI21_X1_LVT i_0_0_39( + .A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_0), .ZN(n_0_24) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[24]_reg ( + .CK(clk), .E(n_0_24), .GCK(n_0_54), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[24][31] ( + .CK(n_0_54), .D(registers[31]), .Q(registers_24__ap[31]), .QN(), .SE(dftIn), + .SI(registers_30__ap[31]) + ); + NOR2_X1_LVT i_1_0_1353( + .A1(n_1_0_1293), .A2(n_1_0_1290), .ZN(n_1_0_1289) + ); + NOR2_X1_LVT i_1_0_1324( + .A1(n_1_0_1288), .A2(n_1_0_1284), .ZN(n_1_0_1260) + ); + OAI21_X1_LVT i_0_0_55( + .A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_5), .ZN(n_0_12) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[12]_reg ( + .CK(clk), .E(n_0_12), .GCK(n_0_42), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[12][31] ( + .CK(n_0_42), .D(registers[31]), .Q(registers_12__ap[31]), .QN(), .SE(dftIn), + .SI(registers_10__ap[31]) + ); + AOI22_X1_LVT i_1_0_1313( + .A1(registers_24__ap[31]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[31]), + .ZN(n_1_0_1249) + ); + OAI21_X1_LVT i_0_0_43( + .A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_3), .ZN(n_0_22) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[22]_reg ( + .CK(clk), .E(n_0_22), .GCK(n_0_52), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[22][31] ( + .CK(n_0_52), .D(registers[31]), .Q(registers_22__ap[31]), .QN(), .SE(dftIn), + .SI(registers_18__ap[31]) + ); + NOR2_X1_LVT i_1_0_1358( + .A1(n_1_0_1301), .A2(n_1_0_1299), .ZN(n_1_0_1294) + ); + NOR2_X1_LVT i_1_0_1323( + .A1(n_1_0_1296), .A2(n_1_0_1284), .ZN(n_1_0_1259) + ); + OAI21_X1_LVT i_0_0_44( + .A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_3), .ZN(n_0_21) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[21]_reg ( + .CK(clk), .E(n_0_21), .GCK(n_0_51), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[21][31] ( + .CK(n_0_51), .D(registers[31]), .Q(registers_21__ap[31]), .QN(), .SE(dftIn), + .SI(registers_22__ap[31]) + ); + AOI22_X1_LVT i_1_0_1312( + .A1(registers_22__ap[31]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[31]), + .ZN(n_1_0_1248) + ); + NAND3_X1_LVT i_1_0_1311( + .A1(n_1_0_1250), .A2(n_1_0_1249), .A3(n_1_0_1248), .ZN(n_1_0_1247) + ); + NOR2_X1_LVT i_1_0_1335( + .A1(n_1_0_1296), .A2(n_1_0_1293), .ZN(n_1_0_1271) + ); + OAI21_X1_LVT i_0_0_48( + .A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_2), .ZN(n_0_17) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[17]_reg ( + .CK(clk), .E(n_0_17), .GCK(n_0_47), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[17][31] ( + .CK(n_0_47), .D(registers[31]), .Q(registers_17__ap[31]), .QN(), .SE(dftIn), + .SI(registers_21__ap[31]) + ); + OAI21_X1_LVT i_0_0_45( + .A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_3), .ZN(n_0_20) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[20]_reg ( + .CK(clk), .E(n_0_20), .GCK(n_0_50), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[20][31] ( + .CK(n_0_50), .D(registers[31]), .Q(registers_20__ap[31]), .QN(), .SE(dftIn), + .SI(registers_17__ap[31]) + ); + NOR2_X1_LVT i_1_0_1345( + .A1(n_1_0_1299), .A2(n_1_0_1284), .ZN(n_1_0_1281) + ); + AOI221_X1_LVT i_1_0_1310( + .A(n_1_0_1247), .B1(n_1_0_1271), .B2(registers_17__ap[31]), .C1(registers_20__ap[31]), + .C2(n_1_0_1281), .ZN(n_1_0_1246) + ); + OAI21_X1_LVT i_0_0_36( + .A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_0), .ZN(n_0_27) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[27]_reg ( + .CK(clk), .E(n_0_27), .GCK(n_0_57), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[27][31] ( + .CK(n_0_57), .D(registers[31]), .Q(registers_27__ap[31]), .QN(), .SE(dftIn), + .SI(registers_24__ap[31]) + ); + NOR2_X1_LVT i_1_0_1343( + .A1(n_1_0_1298), .A2(n_1_0_1280), .ZN(n_1_0_1279) + ); + NOR2_X1_LVT i_1_0_1334( + .A1(n_1_0_1298), .A2(n_1_0_1292), .ZN(n_1_0_1270) + ); + OAI21_X1_LVT i_0_0_56( + .A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_4), .ZN(n_0_11) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[11]_reg ( + .CK(clk), .E(n_0_11), .GCK(n_0_41), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[11][31] ( + .CK(n_0_41), .D(registers[31]), .Q(registers_11__ap[31]), .QN(), .SE(dftIn), + .SI(registers_12__ap[31]) + ); + AOI22_X1_LVT i_1_0_1309( + .A1(registers_27__ap[31]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[31]), + .ZN(n_1_0_1245) + ); + OAI21_X1_LVT i_0_0_54( + .A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_5), .ZN(n_0_13) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[13]_reg ( + .CK(clk), .E(n_0_13), .GCK(n_0_43), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[13][31] ( + .CK(n_0_43), .D(registers[31]), .Q(registers_13__ap[31]), .QN(), .SE(dftIn), + .SI(registers_11__ap[31]) + ); + NOR2_X1_LVT i_1_0_1341( + .A1(n_1_0_1292), .A2(n_1_0_1284), .ZN(n_1_0_1277) + ); + NOR2_X1_LVT i_1_0_1333( + .A1(n_1_0_1293), .A2(n_1_0_1280), .ZN(n_1_0_1269) + ); + OAI21_X1_LVT i_0_0_38( + .A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_0), .ZN(n_0_25) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[25]_reg ( + .CK(clk), .E(n_0_25), .GCK(n_0_55), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[25][31] ( + .CK(n_0_55), .D(registers[31]), .Q(registers_25__ap[31]), .QN(), .SE(dftIn), + .SI(registers_27__ap[31]) + ); + AOI22_X1_LVT i_1_0_1308( + .A1(registers_13__ap[31]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[31]), + .ZN(n_1_0_1244) + ); + OAI21_X1_LVT i_0_0_52( + .A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_5), .ZN(n_0_15) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[15]_reg ( + .CK(clk), .E(n_0_15), .GCK(n_0_45), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[15][31] ( + .CK(n_0_45), .D(registers[31]), .Q(registers_15__ap[31]), .QN(), .SE(dftIn), + .SI(registers_13__ap[31]) + ); + NOR2_X1_LVT i_1_0_1350( + .A1(n_1_0_1301), .A2(n_1_0_1292), .ZN(n_1_0_1286) + ); + NOR2_X1_LVT i_1_0_1322( + .A1(n_1_0_1301), .A2(n_1_0_1288), .ZN(n_1_0_1258) + ); + OAI21_X1_LVT i_0_0_53( + .A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_5), .ZN(n_0_14) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[14]_reg ( + .CK(clk), .E(n_0_14), .GCK(n_0_44), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[14][31] ( + .CK(n_0_44), .D(registers[31]), .Q(registers_14__ap[31]), .QN(), .SE(dftIn), + .SI(registers_15__ap[31]) + ); + AOI22_X1_LVT i_1_0_1307( + .A1(registers_15__ap[31]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[31]), + .ZN(n_1_0_1243) + ); + NAND3_X1_LVT i_1_0_1306( + .A1(n_1_0_1245), .A2(n_1_0_1244), .A3(n_1_0_1243), .ZN(n_1_0_1242) + ); + NOR2_X1_LVT i_1_0_1321( + .A1(n_1_0_1298), .A2(n_1_0_1275), .ZN(n_1_0_1257) + ); + OAI21_X1_LVT i_0_0_71( + .A(n_0_0_16), .B1(n_0_0_13), .B2(n_0_0_11), .ZN(n_0_3) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[3]_reg ( + .CK(clk), .E(n_0_3), .GCK(n_0_33), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[3][31] ( + .CK(n_0_33), .D(registers[31]), .Q(registers_3__ap[31]), .QN(), .SE(dftIn), + .SI(registers_9__ap[31]) + ); + OAI21_X1_LVT i_0_0_73( + .A(n_0_0_16), .B1(n_0_0_13), .B2(n_0_0_12), .ZN(n_0_2) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[2]_reg ( + .CK(clk), .E(n_0_2), .GCK(n_0_32), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[2][31] ( + .CK(n_0_32), .D(registers[31]), .Q(registers_2__ap[31]), .QN(), .SE(dftIn), + .SI(registers_25__ap[31]) + ); + NOR4_X1_LVT i_1_0_1332( + .A1(n_1_0_1298), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), .ZN(n_1_0_1268) + ); + AOI221_X1_LVT i_1_0_1305( + .A(n_1_0_1242), .B1(n_1_0_1257), .B2(registers_3__ap[31]), .C1(registers_2__ap[31]), + .C2(n_1_0_1268), .ZN(n_1_0_1241) + ); + NAND4_X1_LVT i_1_0_1304( + .A1(n_1_0_1256), .A2(n_1_0_1251), .A3(n_1_0_1246), .A4(n_1_0_1241), .ZN(RRs1[31]) + ); + AND2_X1_LVT i_0_0_30( + .A1(n_0_0_16), .A2(WRd[30]), .ZN(registers[30]) + ); + SDFF_X1_LVT \registers_reg[28][30] ( + .CK(n_0_58), .D(registers[30]), .Q(registers_28__ap[30]), .QN(), .SE(dftIn), + .SI(registers_2__ap[31]) + ); + SDFF_X1_LVT \registers_reg[17][30] ( + .CK(n_0_47), .D(registers[30]), .Q(registers_17__ap[30]), .QN(), .SE(dftIn), + .SI(registers_20__ap[31]) + ); + AOI22_X1_LVT i_1_0_1300( + .A1(registers_28__ap[30]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[30]), + .ZN(n_1_0_1237) + ); + SDFF_X1_LVT \registers_reg[16][30] ( + .CK(n_0_46), .D(registers[30]), .Q(registers_16__ap[30]), .QN(), .SE(dftIn), + .SI(registers_14__ap[31]) + ); + SDFF_X1_LVT \registers_reg[31][30] ( + .CK(n_0_61), .D(registers[30]), .Q(registers_31__ap[30]), .QN(), .SE(dftIn), + .SI(registers_3__ap[31]) + ); + AOI22_X1_LVT i_1_0_1303( + .A1(registers_16__ap[30]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[30]), + .ZN(n_1_0_1240) + ); + SDFF_X1_LVT \registers_reg[6][30] ( + .CK(n_0_36), .D(registers[30]), .Q(registers_6__ap[30]), .QN(), .SE(dftIn), + .SI(registers_31__ap[30]) + ); + SDFF_X1_LVT \registers_reg[1][30] ( + .CK(n_0_0), .D(registers[30]), .Q(registers_1__ap[30]), .QN(), .SE(dftIn), + .SI(registers_17__ap[30]) + ); + AOI22_X1_LVT i_1_0_1299( + .A1(registers_6__ap[30]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[30]), + .ZN(n_1_0_1236) + ); + SDFF_X1_LVT \registers_reg[23][30] ( + .CK(n_0_53), .D(registers[30]), .Q(registers_23__ap[30]), .QN(), .SE(dftIn), + .SI(registers_1__ap[30]) + ); + SDFF_X1_LVT \registers_reg[7][30] ( + .CK(n_0_37), .D(registers[30]), .Q(registers_7__ap[30]), .QN(), .SE(dftIn), + .SI(registers_6__ap[30]) + ); + AOI22_X1_LVT i_1_0_1302( + .A1(registers_23__ap[30]), .A2(n_1_0_1264), .B1(n_1_0_1263), .B2(registers_7__ap[30]), + .ZN(n_1_0_1239) + ); + INV_X1_LVT i_1_0_1301( + .A(n_1_0_1239), .ZN(n_1_0_1238) + ); + SDFF_X1_LVT \registers_reg[19][30] ( + .CK(n_0_49), .D(registers[30]), .Q(registers_19__ap[30]), .QN(), .SE(dftIn), + .SI(registers_23__ap[30]) + ); + SDFF_X1_LVT \registers_reg[5][30] ( + .CK(n_0_35), .D(registers[30]), .Q(registers_5__ap[30]), .QN(), .SE(dftIn), + .SI(registers_7__ap[30]) + ); + AOI221_X1_LVT i_1_0_1298( + .A(n_1_0_1238), .B1(n_1_0_1295), .B2(registers_19__ap[30]), .C1(registers_5__ap[30]), + .C2(n_1_0_1273), .ZN(n_1_0_1235) + ); + SDFF_X1_LVT \registers_reg[10][30] ( + .CK(n_0_40), .D(registers[30]), .Q(registers_10__ap[30]), .QN(), .SE(dftIn), + .SI(registers_16__ap[30]) + ); + SDFF_X1_LVT \registers_reg[26][30] ( + .CK(n_0_56), .D(registers[30]), .Q(registers_26__ap[30]), .QN(), .SE(dftIn), + .SI(registers_28__ap[30]) + ); + SDFF_X1_LVT \registers_reg[8][30] ( + .CK(n_0_38), .D(registers[30]), .Q(registers_8__ap[30]), .QN(), .SE(dftIn), + .SI(registers_5__ap[30]) + ); + AOI222_X1_LVT i_1_0_1297( + .A1(registers_10__ap[30]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[30]), + .C1(registers_8__ap[30]), .C2(n_1_0_1282), .ZN(n_1_0_1234) + ); + NAND4_X1_LVT i_1_0_1296( + .A1(n_1_0_1240), .A2(n_1_0_1236), .A3(n_1_0_1235), .A4(n_1_0_1234), .ZN(n_1_0_1233) + ); + SDFF_X1_LVT \registers_reg[9][30] ( + .CK(n_0_39), .D(registers[30]), .Q(registers_9__ap[30]), .QN(), .SE(dftIn), + .SI(registers_8__ap[30]) + ); + SDFF_X1_LVT \registers_reg[29][30] ( + .CK(n_0_59), .D(registers[30]), .Q(registers_29__ap[30]), .QN(), .SE(dftIn), + .SI(registers_26__ap[30]) + ); + AOI221_X1_LVT i_1_0_1295( + .A(n_1_0_1233), .B1(n_1_0_1291), .B2(registers_9__ap[30]), .C1(registers_29__ap[30]), + .C2(n_1_0_1276), .ZN(n_1_0_1232) + ); + SDFF_X1_LVT \registers_reg[18][30] ( + .CK(n_0_48), .D(registers[30]), .Q(registers_18__ap[30]), .QN(), .SE(dftIn), + .SI(registers_19__ap[30]) + ); + SDFF_X1_LVT \registers_reg[30][30] ( + .CK(n_0_60), .D(registers[30]), .Q(registers_30__ap[30]), .QN(), .SE(dftIn), + .SI(registers_29__ap[30]) + ); + AOI22_X1_LVT i_1_0_1294( + .A1(registers_18__ap[30]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[30]), + .ZN(n_1_0_1231) + ); + SDFF_X1_LVT \registers_reg[20][30] ( + .CK(n_0_50), .D(registers[30]), .Q(registers_20__ap[30]), .QN(), .SE(dftIn), + .SI(registers_18__ap[30]) + ); + SDFF_X1_LVT \registers_reg[4][30] ( + .CK(n_0_34), .D(registers[30]), .Q(registers_4__ap[30]), .QN(), .SE(dftIn), + .SI(registers_9__ap[30]) + ); + AOI22_X1_LVT i_1_0_1293( + .A1(registers_20__ap[30]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[30]), + .ZN(n_1_0_1230) + ); + SDFF_X1_LVT \registers_reg[22][30] ( + .CK(n_0_52), .D(registers[30]), .Q(registers_22__ap[30]), .QN(), .SE(dftIn), + .SI(registers_20__ap[30]) + ); + SDFF_X1_LVT \registers_reg[21][30] ( + .CK(n_0_51), .D(registers[30]), .Q(registers_21__ap[30]), .QN(), .SE(dftIn), + .SI(registers_22__ap[30]) + ); + AOI22_X1_LVT i_1_0_1292( + .A1(registers_22__ap[30]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[30]), + .ZN(n_1_0_1229) + ); + NAND3_X1_LVT i_1_0_1291( + .A1(n_1_0_1231), .A2(n_1_0_1230), .A3(n_1_0_1229), .ZN(n_1_0_1228) + ); + SDFF_X1_LVT \registers_reg[24][30] ( + .CK(n_0_54), .D(registers[30]), .Q(registers_24__ap[30]), .QN(), .SE(dftIn), + .SI(registers_30__ap[30]) + ); + SDFF_X1_LVT \registers_reg[12][30] ( + .CK(n_0_42), .D(registers[30]), .Q(registers_12__ap[30]), .QN(), .SE(dftIn), + .SI(registers_10__ap[30]) + ); + AOI221_X1_LVT i_1_0_1290( + .A(n_1_0_1228), .B1(n_1_0_1289), .B2(registers_24__ap[30]), .C1(registers_12__ap[30]), + .C2(n_1_0_1260), .ZN(n_1_0_1227) + ); + SDFF_X1_LVT \registers_reg[27][30] ( + .CK(n_0_57), .D(registers[30]), .Q(registers_27__ap[30]), .QN(), .SE(dftIn), + .SI(registers_24__ap[30]) + ); + SDFF_X1_LVT \registers_reg[11][30] ( + .CK(n_0_41), .D(registers[30]), .Q(registers_11__ap[30]), .QN(), .SE(dftIn), + .SI(registers_12__ap[30]) + ); + AOI22_X1_LVT i_1_0_1289( + .A1(registers_27__ap[30]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[30]), + .ZN(n_1_0_1226) + ); + SDFF_X1_LVT \registers_reg[13][30] ( + .CK(n_0_43), .D(registers[30]), .Q(registers_13__ap[30]), .QN(), .SE(dftIn), + .SI(registers_11__ap[30]) + ); + SDFF_X1_LVT \registers_reg[25][30] ( + .CK(n_0_55), .D(registers[30]), .Q(registers_25__ap[30]), .QN(), .SE(dftIn), + .SI(registers_27__ap[30]) + ); + AOI22_X1_LVT i_1_0_1288( + .A1(registers_13__ap[30]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[30]), + .ZN(n_1_0_1225) + ); + SDFF_X1_LVT \registers_reg[15][30] ( + .CK(n_0_45), .D(registers[30]), .Q(registers_15__ap[30]), .QN(), .SE(dftIn), + .SI(registers_13__ap[30]) + ); + SDFF_X1_LVT \registers_reg[14][30] ( + .CK(n_0_44), .D(registers[30]), .Q(registers_14__ap[30]), .QN(), .SE(dftIn), + .SI(registers_15__ap[30]) + ); + AOI22_X1_LVT i_1_0_1287( + .A1(registers_15__ap[30]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[30]), + .ZN(n_1_0_1224) + ); + NAND3_X1_LVT i_1_0_1286( + .A1(n_1_0_1226), .A2(n_1_0_1225), .A3(n_1_0_1224), .ZN(n_1_0_1223) + ); + SDFF_X1_LVT \registers_reg[3][30] ( + .CK(n_0_33), .D(registers[30]), .Q(registers_3__ap[30]), .QN(), .SE(dftIn), + .SI(registers_4__ap[30]) + ); + SDFF_X1_LVT \registers_reg[2][30] ( + .CK(n_0_32), .D(registers[30]), .Q(registers_2__ap[30]), .QN(), .SE(dftIn), + .SI(registers_25__ap[30]) + ); + AOI221_X1_LVT i_1_0_1285( + .A(n_1_0_1223), .B1(n_1_0_1257), .B2(registers_3__ap[30]), .C1(registers_2__ap[30]), + .C2(n_1_0_1268), .ZN(n_1_0_1222) + ); + NAND4_X1_LVT i_1_0_1284( + .A1(n_1_0_1237), .A2(n_1_0_1232), .A3(n_1_0_1227), .A4(n_1_0_1222), .ZN(RRs1[30]) + ); + AND2_X1_LVT i_0_0_29( + .A1(n_0_0_16), .A2(WRd[29]), .ZN(registers[29]) + ); + SDFF_X1_LVT \registers_reg[28][29] ( + .CK(n_0_58), .D(registers[29]), .Q(registers_28__ap[29]), .QN(), .SE(dftIn), + .SI(registers_2__ap[30]) + ); + SDFF_X1_LVT \registers_reg[8][29] ( + .CK(n_0_38), .D(registers[29]), .Q(registers_8__ap[29]), .QN(), .SE(dftIn), + .SI(registers_3__ap[30]) + ); + AOI22_X1_LVT i_1_0_1282( + .A1(registers_28__ap[29]), .A2(n_1_0_1283), .B1(n_1_0_1282), .B2(registers_8__ap[29]), + .ZN(n_1_0_1220) + ); + SDFF_X1_LVT \registers_reg[31][29] ( + .CK(n_0_61), .D(registers[29]), .Q(registers_31__ap[29]), .QN(), .SE(dftIn), + .SI(registers_8__ap[29]) + ); + SDFF_X1_LVT \registers_reg[7][29] ( + .CK(n_0_37), .D(registers[29]), .Q(registers_7__ap[29]), .QN(), .SE(dftIn), + .SI(registers_31__ap[29]) + ); + AOI22_X1_LVT i_1_0_1283( + .A1(registers_31__ap[29]), .A2(n_1_0_1266), .B1(n_1_0_1263), .B2(registers_7__ap[29]), + .ZN(n_1_0_1221) + ); + SDFF_X1_LVT \registers_reg[24][29] ( + .CK(n_0_54), .D(registers[29]), .Q(registers_24__ap[29]), .QN(), .SE(dftIn), + .SI(registers_28__ap[29]) + ); + SDFF_X1_LVT \registers_reg[20][29] ( + .CK(n_0_50), .D(registers[29]), .Q(registers_20__ap[29]), .QN(), .SE(dftIn), + .SI(registers_21__ap[30]) + ); + AOI22_X1_LVT i_1_0_1281( + .A1(registers_24__ap[29]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[29]), + .ZN(n_1_0_1219) + ); + SDFF_X1_LVT \registers_reg[19][29] ( + .CK(n_0_49), .D(registers[29]), .Q(registers_19__ap[29]), .QN(), .SE(dftIn), + .SI(registers_20__ap[29]) + ); + SDFF_X1_LVT \registers_reg[4][29] ( + .CK(n_0_34), .D(registers[29]), .Q(registers_4__ap[29]), .QN(), .SE(dftIn), + .SI(registers_7__ap[29]) + ); + AOI22_X1_LVT i_1_0_1280( + .A1(registers_19__ap[29]), .A2(n_1_0_1295), .B1(n_1_0_1278), .B2(registers_4__ap[29]), + .ZN(n_1_0_1218) + ); + NAND3_X1_LVT i_1_0_1279( + .A1(n_1_0_1221), .A2(n_1_0_1219), .A3(n_1_0_1218), .ZN(n_1_0_1217) + ); + SDFF_X1_LVT \registers_reg[23][29] ( + .CK(n_0_53), .D(registers[29]), .Q(registers_23__ap[29]), .QN(), .SE(dftIn), + .SI(registers_19__ap[29]) + ); + SDFF_X1_LVT \registers_reg[29][29] ( + .CK(n_0_59), .D(registers[29]), .Q(registers_29__ap[29]), .QN(), .SE(dftIn), + .SI(registers_24__ap[29]) + ); + AOI221_X1_LVT i_1_0_1278( + .A(n_1_0_1217), .B1(n_1_0_1264), .B2(registers_23__ap[29]), .C1(registers_29__ap[29]), + .C2(n_1_0_1276), .ZN(n_1_0_1216) + ); + SDFF_X1_LVT \registers_reg[10][29] ( + .CK(n_0_40), .D(registers[29]), .Q(registers_10__ap[29]), .QN(), .SE(dftIn), + .SI(registers_14__ap[30]) + ); + SDFF_X1_LVT \registers_reg[26][29] ( + .CK(n_0_56), .D(registers[29]), .Q(registers_26__ap[29]), .QN(), .SE(dftIn), + .SI(registers_29__ap[29]) + ); + SDFF_X1_LVT \registers_reg[25][29] ( + .CK(n_0_55), .D(registers[29]), .Q(registers_25__ap[29]), .QN(), .SE(dftIn), + .SI(registers_26__ap[29]) + ); + AOI222_X1_LVT i_1_0_1277( + .A1(registers_10__ap[29]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[29]), + .C1(registers_25__ap[29]), .C2(n_1_0_1269), .ZN(n_1_0_1215) + ); + NAND3_X1_LVT i_1_0_1276( + .A1(n_1_0_1220), .A2(n_1_0_1216), .A3(n_1_0_1215), .ZN(n_1_0_1214) + ); + SDFF_X1_LVT \registers_reg[21][29] ( + .CK(n_0_51), .D(registers[29]), .Q(registers_21__ap[29]), .QN(), .SE(dftIn), + .SI(registers_23__ap[29]) + ); + SDFF_X1_LVT \registers_reg[13][29] ( + .CK(n_0_43), .D(registers[29]), .Q(registers_13__ap[29]), .QN(), .SE(dftIn), + .SI(registers_10__ap[29]) + ); + AOI221_X1_LVT i_1_0_1275( + .A(n_1_0_1214), .B1(n_1_0_1259), .B2(registers_21__ap[29]), .C1(registers_13__ap[29]), + .C2(n_1_0_1277), .ZN(n_1_0_1213) + ); + SDFF_X1_LVT \registers_reg[18][29] ( + .CK(n_0_48), .D(registers[29]), .Q(registers_18__ap[29]), .QN(), .SE(dftIn), + .SI(registers_21__ap[29]) + ); + SDFF_X1_LVT \registers_reg[30][29] ( + .CK(n_0_60), .D(registers[29]), .Q(registers_30__ap[29]), .QN(), .SE(dftIn), + .SI(registers_25__ap[29]) + ); + AOI22_X1_LVT i_1_0_1274( + .A1(registers_18__ap[29]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[29]), + .ZN(n_1_0_1212) + ); + SDFF_X1_LVT \registers_reg[17][29] ( + .CK(n_0_47), .D(registers[29]), .Q(registers_17__ap[29]), .QN(), .SE(dftIn), + .SI(registers_18__ap[29]) + ); + SDFF_X1_LVT \registers_reg[12][29] ( + .CK(n_0_42), .D(registers[29]), .Q(registers_12__ap[29]), .QN(), .SE(dftIn), + .SI(registers_13__ap[29]) + ); + AOI22_X1_LVT i_1_0_1273( + .A1(registers_17__ap[29]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[29]), + .ZN(n_1_0_1211) + ); + SDFF_X1_LVT \registers_reg[15][29] ( + .CK(n_0_45), .D(registers[29]), .Q(registers_15__ap[29]), .QN(), .SE(dftIn), + .SI(registers_12__ap[29]) + ); + SDFF_X1_LVT \registers_reg[16][29] ( + .CK(n_0_46), .D(registers[29]), .Q(registers_16__ap[29]), .QN(), .SE(dftIn), + .SI(registers_15__ap[29]) + ); + AOI22_X1_LVT i_1_0_1272( + .A1(registers_15__ap[29]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[29]), + .ZN(n_1_0_1210) + ); + NAND3_X1_LVT i_1_0_1271( + .A1(n_1_0_1212), .A2(n_1_0_1211), .A3(n_1_0_1210), .ZN(n_1_0_1209) + ); + SDFF_X1_LVT \registers_reg[22][29] ( + .CK(n_0_52), .D(registers[29]), .Q(registers_22__ap[29]), .QN(), .SE(dftIn), + .SI(registers_17__ap[29]) + ); + SDFF_X1_LVT \registers_reg[5][29] ( + .CK(n_0_35), .D(registers[29]), .Q(registers_5__ap[29]), .QN(), .SE(dftIn), + .SI(registers_4__ap[29]) + ); + AOI221_X1_LVT i_1_0_1270( + .A(n_1_0_1209), .B1(n_1_0_1294), .B2(registers_22__ap[29]), .C1(registers_5__ap[29]), + .C2(n_1_0_1273), .ZN(n_1_0_1208) + ); + SDFF_X1_LVT \registers_reg[9][29] ( + .CK(n_0_39), .D(registers[29]), .Q(registers_9__ap[29]), .QN(), .SE(dftIn), + .SI(registers_5__ap[29]) + ); + SDFF_X1_LVT \registers_reg[1][29] ( + .CK(n_0_0), .D(registers[29]), .Q(registers_1__ap[29]), .QN(), .SE(dftIn), + .SI(registers_22__ap[29]) + ); + AOI22_X1_LVT i_1_0_1269( + .A1(registers_9__ap[29]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[29]), + .ZN(n_1_0_1207) + ); + SDFF_X1_LVT \registers_reg[6][29] ( + .CK(n_0_36), .D(registers[29]), .Q(registers_6__ap[29]), .QN(), .SE(dftIn), + .SI(registers_9__ap[29]) + ); + SDFF_X1_LVT \registers_reg[14][29] ( + .CK(n_0_44), .D(registers[29]), .Q(registers_14__ap[29]), .QN(), .SE(dftIn), + .SI(registers_16__ap[29]) + ); + AOI22_X1_LVT i_1_0_1268( + .A1(registers_6__ap[29]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[29]), + .ZN(n_1_0_1206) + ); + SDFF_X1_LVT \registers_reg[27][29] ( + .CK(n_0_57), .D(registers[29]), .Q(registers_27__ap[29]), .QN(), .SE(dftIn), + .SI(registers_30__ap[29]) + ); + SDFF_X1_LVT \registers_reg[11][29] ( + .CK(n_0_41), .D(registers[29]), .Q(registers_11__ap[29]), .QN(), .SE(dftIn), + .SI(registers_14__ap[29]) + ); + AOI22_X1_LVT i_1_0_1267( + .A1(registers_27__ap[29]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[29]), + .ZN(n_1_0_1205) + ); + NAND3_X1_LVT i_1_0_1266( + .A1(n_1_0_1207), .A2(n_1_0_1206), .A3(n_1_0_1205), .ZN(n_1_0_1204) + ); + SDFF_X1_LVT \registers_reg[3][29] ( + .CK(n_0_33), .D(registers[29]), .Q(registers_3__ap[29]), .QN(), .SE(dftIn), + .SI(registers_6__ap[29]) + ); + SDFF_X1_LVT \registers_reg[2][29] ( + .CK(n_0_32), .D(registers[29]), .Q(registers_2__ap[29]), .QN(), .SE(dftIn), + .SI(registers_27__ap[29]) + ); + AOI221_X1_LVT i_1_0_1265( + .A(n_1_0_1204), .B1(n_1_0_1257), .B2(registers_3__ap[29]), .C1(registers_2__ap[29]), + .C2(n_1_0_1268), .ZN(n_1_0_1203) + ); + NAND3_X1_LVT i_1_0_1264( + .A1(n_1_0_1213), .A2(n_1_0_1208), .A3(n_1_0_1203), .ZN(RRs1[29]) + ); + AND2_X1_LVT i_0_0_28( + .A1(n_0_0_16), .A2(WRd[28]), .ZN(registers[28]) + ); + SDFF_X1_LVT \registers_reg[15][28] ( + .CK(n_0_45), .D(registers[28]), .Q(registers_15__ap[28]), .QN(), .SE(dftIn), + .SI(registers_11__ap[29]) + ); + SDFF_X1_LVT \registers_reg[26][28] ( + .CK(n_0_56), .D(registers[28]), .Q(registers_26__ap[28]), .QN(), .SE(dftIn), + .SI(registers_2__ap[29]) + ); + SDFF_X1_LVT \registers_reg[22][28] ( + .CK(n_0_52), .D(registers[28]), .Q(registers_22__ap[28]), .QN(), .SE(dftIn), + .SI(registers_1__ap[29]) + ); + AOI222_X1_LVT i_1_0_1263( + .A1(registers_15__ap[28]), .A2(n_1_0_1286), .B1(n_1_0_1285), .B2(registers_26__ap[28]), + .C1(registers_22__ap[28]), .C2(n_1_0_1294), .ZN(n_1_0_1202) + ); + SDFF_X1_LVT \registers_reg[5][28] ( + .CK(n_0_35), .D(registers[28]), .Q(registers_5__ap[28]), .QN(), .SE(dftIn), + .SI(registers_3__ap[29]) + ); + SDFF_X1_LVT \registers_reg[12][28] ( + .CK(n_0_42), .D(registers[28]), .Q(registers_12__ap[28]), .QN(), .SE(dftIn), + .SI(registers_15__ap[28]) + ); + AOI22_X1_LVT i_1_0_1262( + .A1(registers_5__ap[28]), .A2(n_1_0_1273), .B1(n_1_0_1260), .B2(registers_12__ap[28]), + .ZN(n_1_0_1201) + ); + SDFF_X1_LVT \registers_reg[28][28] ( + .CK(n_0_58), .D(registers[28]), .Q(registers_28__ap[28]), .QN(), .SE(dftIn), + .SI(registers_26__ap[28]) + ); + SDFF_X1_LVT \registers_reg[14][28] ( + .CK(n_0_44), .D(registers[28]), .Q(registers_14__ap[28]), .QN(), .SE(dftIn), + .SI(registers_12__ap[28]) + ); + AOI22_X1_LVT i_1_0_1261( + .A1(registers_28__ap[28]), .A2(n_1_0_1283), .B1(n_1_0_1258), .B2(registers_14__ap[28]), + .ZN(n_1_0_1200) + ); + SDFF_X1_LVT \registers_reg[17][28] ( + .CK(n_0_47), .D(registers[28]), .Q(registers_17__ap[28]), .QN(), .SE(dftIn), + .SI(registers_22__ap[28]) + ); + SDFF_X1_LVT \registers_reg[2][28] ( + .CK(n_0_32), .D(registers[28]), .Q(registers_2__ap[28]), .QN(), .SE(dftIn), + .SI(registers_28__ap[28]) + ); + AOI22_X1_LVT i_1_0_1260( + .A1(registers_17__ap[28]), .A2(n_1_0_1271), .B1(n_1_0_1268), .B2(registers_2__ap[28]), + .ZN(n_1_0_1199) + ); + NAND3_X1_LVT i_1_0_1259( + .A1(n_1_0_1201), .A2(n_1_0_1200), .A3(n_1_0_1199), .ZN(n_1_0_1198) + ); + SDFF_X1_LVT \registers_reg[9][28] ( + .CK(n_0_39), .D(registers[28]), .Q(registers_9__ap[28]), .QN(), .SE(dftIn), + .SI(registers_5__ap[28]) + ); + SDFF_X1_LVT \registers_reg[29][28] ( + .CK(n_0_59), .D(registers[28]), .Q(registers_29__ap[28]), .QN(), .SE(dftIn), + .SI(registers_2__ap[28]) + ); + AOI221_X1_LVT i_1_0_1258( + .A(n_1_0_1198), .B1(n_1_0_1291), .B2(registers_9__ap[28]), .C1(registers_29__ap[28]), + .C2(n_1_0_1276), .ZN(n_1_0_1197) + ); + SDFF_X1_LVT \registers_reg[13][28] ( + .CK(n_0_43), .D(registers[28]), .Q(registers_13__ap[28]), .QN(), .SE(dftIn), + .SI(registers_14__ap[28]) + ); + SDFF_X1_LVT \registers_reg[25][28] ( + .CK(n_0_55), .D(registers[28]), .Q(registers_25__ap[28]), .QN(), .SE(dftIn), + .SI(registers_29__ap[28]) + ); + AOI22_X1_LVT i_1_0_1257( + .A1(registers_13__ap[28]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[28]), + .ZN(n_1_0_1196) + ); + NAND3_X1_LVT i_1_0_1256( + .A1(n_1_0_1202), .A2(n_1_0_1197), .A3(n_1_0_1196), .ZN(n_1_0_1195) + ); + SDFF_X1_LVT \registers_reg[4][28] ( + .CK(n_0_34), .D(registers[28]), .Q(registers_4__ap[28]), .QN(), .SE(dftIn), + .SI(registers_9__ap[28]) + ); + SDFF_X1_LVT \registers_reg[20][28] ( + .CK(n_0_50), .D(registers[28]), .Q(registers_20__ap[28]), .QN(), .SE(dftIn), + .SI(registers_17__ap[28]) + ); + AOI221_X1_LVT i_1_0_1255( + .A(n_1_0_1195), .B1(n_1_0_1278), .B2(registers_4__ap[28]), .C1(registers_20__ap[28]), + .C2(n_1_0_1281), .ZN(n_1_0_1194) + ); + SDFF_X1_LVT \registers_reg[1][28] ( + .CK(n_0_0), .D(registers[28]), .Q(registers_1__ap[28]), .QN(), .SE(dftIn), + .SI(registers_20__ap[28]) + ); + SDFF_X1_LVT \registers_reg[23][28] ( + .CK(n_0_53), .D(registers[28]), .Q(registers_23__ap[28]), .QN(), .SE(dftIn), + .SI(registers_1__ap[28]) + ); + AOI22_X1_LVT i_1_0_1254( + .A1(registers_1__ap[28]), .A2(n_1_0_1274), .B1(n_1_0_1264), .B2(registers_23__ap[28]), + .ZN(n_1_0_1193) + ); + SDFF_X1_LVT \registers_reg[10][28] ( + .CK(n_0_40), .D(registers[28]), .Q(registers_10__ap[28]), .QN(), .SE(dftIn), + .SI(registers_13__ap[28]) + ); + SDFF_X1_LVT \registers_reg[21][28] ( + .CK(n_0_51), .D(registers[28]), .Q(registers_21__ap[28]), .QN(), .SE(dftIn), + .SI(registers_23__ap[28]) + ); + AOI22_X1_LVT i_1_0_1253( + .A1(registers_10__ap[28]), .A2(n_1_0_1287), .B1(n_1_0_1259), .B2(registers_21__ap[28]), + .ZN(n_1_0_1192) + ); + SDFF_X1_LVT \registers_reg[6][28] ( + .CK(n_0_36), .D(registers[28]), .Q(registers_6__ap[28]), .QN(), .SE(dftIn), + .SI(registers_4__ap[28]) + ); + SDFF_X1_LVT \registers_reg[30][28] ( + .CK(n_0_60), .D(registers[28]), .Q(registers_30__ap[28]), .QN(), .SE(dftIn), + .SI(registers_25__ap[28]) + ); + AOI22_X1_LVT i_1_0_1252( + .A1(registers_6__ap[28]), .A2(n_1_0_1300), .B1(n_1_0_1272), .B2(registers_30__ap[28]), + .ZN(n_1_0_1191) + ); + NAND3_X1_LVT i_1_0_1251( + .A1(n_1_0_1193), .A2(n_1_0_1192), .A3(n_1_0_1191), .ZN(n_1_0_1190) + ); + SDFF_X1_LVT \registers_reg[8][28] ( + .CK(n_0_38), .D(registers[28]), .Q(registers_8__ap[28]), .QN(), .SE(dftIn), + .SI(registers_6__ap[28]) + ); + SDFF_X1_LVT \registers_reg[24][28] ( + .CK(n_0_54), .D(registers[28]), .Q(registers_24__ap[28]), .QN(), .SE(dftIn), + .SI(registers_30__ap[28]) + ); + AOI221_X1_LVT i_1_0_1250( + .A(n_1_0_1190), .B1(n_1_0_1282), .B2(registers_8__ap[28]), .C1(registers_24__ap[28]), + .C2(n_1_0_1289), .ZN(n_1_0_1189) + ); + SDFF_X1_LVT \registers_reg[16][28] ( + .CK(n_0_46), .D(registers[28]), .Q(registers_16__ap[28]), .QN(), .SE(dftIn), + .SI(registers_10__ap[28]) + ); + SDFF_X1_LVT \registers_reg[3][28] ( + .CK(n_0_33), .D(registers[28]), .Q(registers_3__ap[28]), .QN(), .SE(dftIn), + .SI(registers_8__ap[28]) + ); + AOI22_X1_LVT i_1_0_1249( + .A1(registers_16__ap[28]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[28]), + .ZN(n_1_0_1188) + ); + SDFF_X1_LVT \registers_reg[11][28] ( + .CK(n_0_41), .D(registers[28]), .Q(registers_11__ap[28]), .QN(), .SE(dftIn), + .SI(registers_16__ap[28]) + ); + SDFF_X1_LVT \registers_reg[31][28] ( + .CK(n_0_61), .D(registers[28]), .Q(registers_31__ap[28]), .QN(), .SE(dftIn), + .SI(registers_3__ap[28]) + ); + AOI22_X1_LVT i_1_0_1248( + .A1(registers_11__ap[28]), .A2(n_1_0_1270), .B1(n_1_0_1266), .B2(registers_31__ap[28]), + .ZN(n_1_0_1187) + ); + SDFF_X1_LVT \registers_reg[27][28] ( + .CK(n_0_57), .D(registers[28]), .Q(registers_27__ap[28]), .QN(), .SE(dftIn), + .SI(registers_24__ap[28]) + ); + SDFF_X1_LVT \registers_reg[7][28] ( + .CK(n_0_37), .D(registers[28]), .Q(registers_7__ap[28]), .QN(), .SE(dftIn), + .SI(registers_31__ap[28]) + ); + AOI22_X1_LVT i_1_0_1247( + .A1(registers_27__ap[28]), .A2(n_1_0_1279), .B1(n_1_0_1263), .B2(registers_7__ap[28]), + .ZN(n_1_0_1186) + ); + NAND3_X1_LVT i_1_0_1246( + .A1(n_1_0_1188), .A2(n_1_0_1187), .A3(n_1_0_1186), .ZN(n_1_0_1185) + ); + SDFF_X1_LVT \registers_reg[19][28] ( + .CK(n_0_49), .D(registers[28]), .Q(registers_19__ap[28]), .QN(), .SE(dftIn), + .SI(registers_21__ap[28]) + ); + SDFF_X1_LVT \registers_reg[18][28] ( + .CK(n_0_48), .D(registers[28]), .Q(registers_18__ap[28]), .QN(), .SE(dftIn), + .SI(registers_19__ap[28]) + ); + AOI221_X1_LVT i_1_0_1245( + .A(n_1_0_1185), .B1(n_1_0_1295), .B2(registers_19__ap[28]), .C1(registers_18__ap[28]), + .C2(n_1_0_1297), .ZN(n_1_0_1184) + ); + NAND3_X1_LVT i_1_0_1244( + .A1(n_1_0_1194), .A2(n_1_0_1189), .A3(n_1_0_1184), .ZN(RRs1[28]) + ); + AND2_X1_LVT i_0_0_27( + .A1(n_0_0_16), .A2(WRd[27]), .ZN(registers[27]) + ); + SDFF_X1_LVT \registers_reg[29][27] ( + .CK(n_0_59), .D(registers[27]), .Q(registers_29__ap[27]), .QN(), .SE(dftIn), + .SI(registers_27__ap[28]) + ); + SDFF_X1_LVT \registers_reg[2][27] ( + .CK(n_0_32), .D(registers[27]), .Q(registers_2__ap[27]), .QN(), .SE(dftIn), + .SI(registers_29__ap[27]) + ); + AOI22_X1_LVT i_1_0_1242( + .A1(registers_29__ap[27]), .A2(n_1_0_1276), .B1(n_1_0_1268), .B2(registers_2__ap[27]), + .ZN(n_1_0_1182) + ); + SDFF_X1_LVT \registers_reg[8][27] ( + .CK(n_0_38), .D(registers[27]), .Q(registers_8__ap[27]), .QN(), .SE(dftIn), + .SI(registers_7__ap[28]) + ); + SDFF_X1_LVT \registers_reg[25][27] ( + .CK(n_0_55), .D(registers[27]), .Q(registers_25__ap[27]), .QN(), .SE(dftIn), + .SI(registers_2__ap[27]) + ); + AOI22_X1_LVT i_1_0_1243( + .A1(registers_8__ap[27]), .A2(n_1_0_1282), .B1(n_1_0_1269), .B2(registers_25__ap[27]), + .ZN(n_1_0_1183) + ); + SDFF_X1_LVT \registers_reg[9][27] ( + .CK(n_0_39), .D(registers[27]), .Q(registers_9__ap[27]), .QN(), .SE(dftIn), + .SI(registers_8__ap[27]) + ); + SDFF_X1_LVT \registers_reg[7][27] ( + .CK(n_0_37), .D(registers[27]), .Q(registers_7__ap[27]), .QN(), .SE(dftIn), + .SI(registers_9__ap[27]) + ); + AOI22_X1_LVT i_1_0_1241( + .A1(registers_9__ap[27]), .A2(n_1_0_1291), .B1(n_1_0_1263), .B2(registers_7__ap[27]), + .ZN(n_1_0_1181) + ); + SDFF_X1_LVT \registers_reg[11][27] ( + .CK(n_0_41), .D(registers[27]), .Q(registers_11__ap[27]), .QN(), .SE(dftIn), + .SI(registers_11__ap[28]) + ); + SDFF_X1_LVT \registers_reg[16][27] ( + .CK(n_0_46), .D(registers[27]), .Q(registers_16__ap[27]), .QN(), .SE(dftIn), + .SI(registers_11__ap[27]) + ); + AOI22_X1_LVT i_1_0_1240( + .A1(registers_11__ap[27]), .A2(n_1_0_1270), .B1(n_1_0_1267), .B2(registers_16__ap[27]), + .ZN(n_1_0_1180) + ); + NAND3_X1_LVT i_1_0_1239( + .A1(n_1_0_1183), .A2(n_1_0_1181), .A3(n_1_0_1180), .ZN(n_1_0_1179) + ); + SDFF_X1_LVT \registers_reg[10][27] ( + .CK(n_0_40), .D(registers[27]), .Q(registers_10__ap[27]), .QN(), .SE(dftIn), + .SI(registers_16__ap[27]) + ); + SDFF_X1_LVT \registers_reg[6][27] ( + .CK(n_0_36), .D(registers[27]), .Q(registers_6__ap[27]), .QN(), .SE(dftIn), + .SI(registers_7__ap[27]) + ); + AOI221_X1_LVT i_1_0_1238( + .A(n_1_0_1179), .B1(n_1_0_1287), .B2(registers_10__ap[27]), .C1(registers_6__ap[27]), + .C2(n_1_0_1300), .ZN(n_1_0_1178) + ); + SDFF_X1_LVT \registers_reg[1][27] ( + .CK(n_0_0), .D(registers[27]), .Q(registers_1__ap[27]), .QN(), .SE(dftIn), + .SI(registers_18__ap[28]) + ); + SDFF_X1_LVT \registers_reg[30][27] ( + .CK(n_0_60), .D(registers[27]), .Q(registers_30__ap[27]), .QN(), .SE(dftIn), + .SI(registers_25__ap[27]) + ); + SDFF_X1_LVT \registers_reg[22][27] ( + .CK(n_0_52), .D(registers[27]), .Q(registers_22__ap[27]), .QN(), .SE(dftIn), + .SI(registers_1__ap[27]) + ); + AOI222_X1_LVT i_1_0_1237( + .A1(registers_1__ap[27]), .A2(n_1_0_1274), .B1(n_1_0_1272), .B2(registers_30__ap[27]), + .C1(registers_22__ap[27]), .C2(n_1_0_1294), .ZN(n_1_0_1177) + ); + NAND3_X1_LVT i_1_0_1236( + .A1(n_1_0_1182), .A2(n_1_0_1178), .A3(n_1_0_1177), .ZN(n_1_0_1176) + ); + SDFF_X1_LVT \registers_reg[5][27] ( + .CK(n_0_35), .D(registers[27]), .Q(registers_5__ap[27]), .QN(), .SE(dftIn), + .SI(registers_6__ap[27]) + ); + SDFF_X1_LVT \registers_reg[28][27] ( + .CK(n_0_58), .D(registers[27]), .Q(registers_28__ap[27]), .QN(), .SE(dftIn), + .SI(registers_30__ap[27]) + ); + AOI221_X1_LVT i_1_0_1235( + .A(n_1_0_1176), .B1(n_1_0_1273), .B2(registers_5__ap[27]), .C1(registers_28__ap[27]), + .C2(n_1_0_1283), .ZN(n_1_0_1175) + ); + SDFF_X1_LVT \registers_reg[4][27] ( + .CK(n_0_34), .D(registers[27]), .Q(registers_4__ap[27]), .QN(), .SE(dftIn), + .SI(registers_5__ap[27]) + ); + SDFF_X1_LVT \registers_reg[12][27] ( + .CK(n_0_42), .D(registers[27]), .Q(registers_12__ap[27]), .QN(), .SE(dftIn), + .SI(registers_10__ap[27]) + ); + AOI22_X1_LVT i_1_0_1234( + .A1(registers_4__ap[27]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[27]), + .ZN(n_1_0_1174) + ); + SDFF_X1_LVT \registers_reg[19][27] ( + .CK(n_0_49), .D(registers[27]), .Q(registers_19__ap[27]), .QN(), .SE(dftIn), + .SI(registers_22__ap[27]) + ); + SDFF_X1_LVT \registers_reg[21][27] ( + .CK(n_0_51), .D(registers[27]), .Q(registers_21__ap[27]), .QN(), .SE(dftIn), + .SI(registers_19__ap[27]) + ); + AOI22_X1_LVT i_1_0_1233( + .A1(registers_19__ap[27]), .A2(n_1_0_1295), .B1(n_1_0_1259), .B2(registers_21__ap[27]), + .ZN(n_1_0_1173) + ); + SDFF_X1_LVT \registers_reg[24][27] ( + .CK(n_0_54), .D(registers[27]), .Q(registers_24__ap[27]), .QN(), .SE(dftIn), + .SI(registers_28__ap[27]) + ); + SDFF_X1_LVT \registers_reg[20][27] ( + .CK(n_0_50), .D(registers[27]), .Q(registers_20__ap[27]), .QN(), .SE(dftIn), + .SI(registers_21__ap[27]) + ); + AOI22_X1_LVT i_1_0_1232( + .A1(registers_24__ap[27]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[27]), + .ZN(n_1_0_1172) + ); + NAND3_X1_LVT i_1_0_1231( + .A1(n_1_0_1174), .A2(n_1_0_1173), .A3(n_1_0_1172), .ZN(n_1_0_1171) + ); + SDFF_X1_LVT \registers_reg[18][27] ( + .CK(n_0_48), .D(registers[27]), .Q(registers_18__ap[27]), .QN(), .SE(dftIn), + .SI(registers_20__ap[27]) + ); + SDFF_X1_LVT \registers_reg[26][27] ( + .CK(n_0_56), .D(registers[27]), .Q(registers_26__ap[27]), .QN(), .SE(dftIn), + .SI(registers_24__ap[27]) + ); + AOI221_X1_LVT i_1_0_1230( + .A(n_1_0_1171), .B1(n_1_0_1297), .B2(registers_18__ap[27]), .C1(registers_26__ap[27]), + .C2(n_1_0_1285), .ZN(n_1_0_1170) + ); + SDFF_X1_LVT \registers_reg[23][27] ( + .CK(n_0_53), .D(registers[27]), .Q(registers_23__ap[27]), .QN(), .SE(dftIn), + .SI(registers_18__ap[27]) + ); + SDFF_X1_LVT \registers_reg[3][27] ( + .CK(n_0_33), .D(registers[27]), .Q(registers_3__ap[27]), .QN(), .SE(dftIn), + .SI(registers_4__ap[27]) + ); + AOI22_X1_LVT i_1_0_1229( + .A1(registers_23__ap[27]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[27]), + .ZN(n_1_0_1169) + ); + SDFF_X1_LVT \registers_reg[13][27] ( + .CK(n_0_43), .D(registers[27]), .Q(registers_13__ap[27]), .QN(), .SE(dftIn), + .SI(registers_12__ap[27]) + ); + SDFF_X1_LVT \registers_reg[17][27] ( + .CK(n_0_47), .D(registers[27]), .Q(registers_17__ap[27]), .QN(), .SE(dftIn), + .SI(registers_23__ap[27]) + ); + AOI22_X1_LVT i_1_0_1228( + .A1(registers_13__ap[27]), .A2(n_1_0_1277), .B1(n_1_0_1271), .B2(registers_17__ap[27]), + .ZN(n_1_0_1168) + ); + SDFF_X1_LVT \registers_reg[15][27] ( + .CK(n_0_45), .D(registers[27]), .Q(registers_15__ap[27]), .QN(), .SE(dftIn), + .SI(registers_13__ap[27]) + ); + SDFF_X1_LVT \registers_reg[14][27] ( + .CK(n_0_44), .D(registers[27]), .Q(registers_14__ap[27]), .QN(), .SE(dftIn), + .SI(registers_15__ap[27]) + ); + AOI22_X1_LVT i_1_0_1227( + .A1(registers_15__ap[27]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[27]), + .ZN(n_1_0_1167) + ); + NAND3_X1_LVT i_1_0_1226( + .A1(n_1_0_1169), .A2(n_1_0_1168), .A3(n_1_0_1167), .ZN(n_1_0_1166) + ); + SDFF_X1_LVT \registers_reg[27][27] ( + .CK(n_0_57), .D(registers[27]), .Q(registers_27__ap[27]), .QN(), .SE(dftIn), + .SI(registers_26__ap[27]) + ); + SDFF_X1_LVT \registers_reg[31][27] ( + .CK(n_0_61), .D(registers[27]), .Q(registers_31__ap[27]), .QN(), .SE(dftIn), + .SI(registers_3__ap[27]) + ); + AOI221_X1_LVT i_1_0_1225( + .A(n_1_0_1166), .B1(n_1_0_1279), .B2(registers_27__ap[27]), .C1(registers_31__ap[27]), + .C2(n_1_0_1266), .ZN(n_1_0_1165) + ); + NAND3_X1_LVT i_1_0_1224( + .A1(n_1_0_1175), .A2(n_1_0_1170), .A3(n_1_0_1165), .ZN(RRs1[27]) + ); + AND2_X1_LVT i_0_0_26( + .A1(n_0_0_16), .A2(WRd[26]), .ZN(registers[26]) + ); + SDFF_X1_LVT \registers_reg[18][26] ( + .CK(n_0_48), .D(registers[26]), .Q(registers_18__ap[26]), .QN(), .SE(dftIn), + .SI(registers_17__ap[27]) + ); + SDFF_X1_LVT \registers_reg[22][26] ( + .CK(n_0_52), .D(registers[26]), .Q(registers_22__ap[26]), .QN(), .SE(dftIn), + .SI(registers_18__ap[26]) + ); + SDFF_X1_LVT \registers_reg[1][26] ( + .CK(n_0_0), .D(registers[26]), .Q(registers_1__ap[26]), .QN(), .SE(dftIn), + .SI(registers_22__ap[26]) + ); + AOI222_X1_LVT i_1_0_1223( + .A1(registers_18__ap[26]), .A2(n_1_0_1297), .B1(n_1_0_1294), .B2(registers_22__ap[26]), + .C1(registers_1__ap[26]), .C2(n_1_0_1274), .ZN(n_1_0_1164) + ); + SDFF_X1_LVT \registers_reg[29][26] ( + .CK(n_0_59), .D(registers[26]), .Q(registers_29__ap[26]), .QN(), .SE(dftIn), + .SI(registers_27__ap[27]) + ); + SDFF_X1_LVT \registers_reg[2][26] ( + .CK(n_0_32), .D(registers[26]), .Q(registers_2__ap[26]), .QN(), .SE(dftIn), + .SI(registers_29__ap[26]) + ); + AOI22_X1_LVT i_1_0_1222( + .A1(registers_29__ap[26]), .A2(n_1_0_1276), .B1(n_1_0_1268), .B2(registers_2__ap[26]), + .ZN(n_1_0_1163) + ); + SDFF_X1_LVT \registers_reg[9][26] ( + .CK(n_0_39), .D(registers[26]), .Q(registers_9__ap[26]), .QN(), .SE(dftIn), + .SI(registers_31__ap[27]) + ); + SDFF_X1_LVT \registers_reg[7][26] ( + .CK(n_0_37), .D(registers[26]), .Q(registers_7__ap[26]), .QN(), .SE(dftIn), + .SI(registers_9__ap[26]) + ); + AOI22_X1_LVT i_1_0_1221( + .A1(registers_9__ap[26]), .A2(n_1_0_1291), .B1(n_1_0_1263), .B2(registers_7__ap[26]), + .ZN(n_1_0_1162) + ); + SDFF_X1_LVT \registers_reg[11][26] ( + .CK(n_0_41), .D(registers[26]), .Q(registers_11__ap[26]), .QN(), .SE(dftIn), + .SI(registers_14__ap[27]) + ); + SDFF_X1_LVT \registers_reg[25][26] ( + .CK(n_0_55), .D(registers[26]), .Q(registers_25__ap[26]), .QN(), .SE(dftIn), + .SI(registers_2__ap[26]) + ); + AOI22_X1_LVT i_1_0_1220( + .A1(registers_11__ap[26]), .A2(n_1_0_1270), .B1(n_1_0_1269), .B2(registers_25__ap[26]), + .ZN(n_1_0_1161) + ); + SDFF_X1_LVT \registers_reg[27][26] ( + .CK(n_0_57), .D(registers[26]), .Q(registers_27__ap[26]), .QN(), .SE(dftIn), + .SI(registers_25__ap[26]) + ); + SDFF_X1_LVT \registers_reg[16][26] ( + .CK(n_0_46), .D(registers[26]), .Q(registers_16__ap[26]), .QN(), .SE(dftIn), + .SI(registers_11__ap[26]) + ); + AOI22_X1_LVT i_1_0_1219( + .A1(registers_27__ap[26]), .A2(n_1_0_1279), .B1(n_1_0_1267), .B2(registers_16__ap[26]), + .ZN(n_1_0_1160) + ); + NAND3_X1_LVT i_1_0_1218( + .A1(n_1_0_1162), .A2(n_1_0_1161), .A3(n_1_0_1160), .ZN(n_1_0_1159) + ); + SDFF_X1_LVT \registers_reg[31][26] ( + .CK(n_0_61), .D(registers[26]), .Q(registers_31__ap[26]), .QN(), .SE(dftIn), + .SI(registers_7__ap[26]) + ); + SDFF_X1_LVT \registers_reg[6][26] ( + .CK(n_0_36), .D(registers[26]), .Q(registers_6__ap[26]), .QN(), .SE(dftIn), + .SI(registers_31__ap[26]) + ); + AOI221_X1_LVT i_1_0_1217( + .A(n_1_0_1159), .B1(n_1_0_1266), .B2(registers_31__ap[26]), .C1(registers_6__ap[26]), + .C2(n_1_0_1300), .ZN(n_1_0_1158) + ); + NAND3_X1_LVT i_1_0_1216( + .A1(n_1_0_1164), .A2(n_1_0_1163), .A3(n_1_0_1158), .ZN(n_1_0_1157) + ); + SDFF_X1_LVT \registers_reg[5][26] ( + .CK(n_0_35), .D(registers[26]), .Q(registers_5__ap[26]), .QN(), .SE(dftIn), + .SI(registers_6__ap[26]) + ); + SDFF_X1_LVT \registers_reg[28][26] ( + .CK(n_0_58), .D(registers[26]), .Q(registers_28__ap[26]), .QN(), .SE(dftIn), + .SI(registers_27__ap[26]) + ); + AOI221_X1_LVT i_1_0_1215( + .A(n_1_0_1157), .B1(n_1_0_1273), .B2(registers_5__ap[26]), .C1(registers_28__ap[26]), + .C2(n_1_0_1283), .ZN(n_1_0_1156) + ); + SDFF_X1_LVT \registers_reg[4][26] ( + .CK(n_0_34), .D(registers[26]), .Q(registers_4__ap[26]), .QN(), .SE(dftIn), + .SI(registers_5__ap[26]) + ); + SDFF_X1_LVT \registers_reg[12][26] ( + .CK(n_0_42), .D(registers[26]), .Q(registers_12__ap[26]), .QN(), .SE(dftIn), + .SI(registers_16__ap[26]) + ); + AOI22_X1_LVT i_1_0_1214( + .A1(registers_4__ap[26]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[26]), + .ZN(n_1_0_1155) + ); + SDFF_X1_LVT \registers_reg[19][26] ( + .CK(n_0_49), .D(registers[26]), .Q(registers_19__ap[26]), .QN(), .SE(dftIn), + .SI(registers_1__ap[26]) + ); + SDFF_X1_LVT \registers_reg[21][26] ( + .CK(n_0_51), .D(registers[26]), .Q(registers_21__ap[26]), .QN(), .SE(dftIn), + .SI(registers_19__ap[26]) + ); + AOI22_X1_LVT i_1_0_1213( + .A1(registers_19__ap[26]), .A2(n_1_0_1295), .B1(n_1_0_1259), .B2(registers_21__ap[26]), + .ZN(n_1_0_1154) + ); + SDFF_X1_LVT \registers_reg[24][26] ( + .CK(n_0_54), .D(registers[26]), .Q(registers_24__ap[26]), .QN(), .SE(dftIn), + .SI(registers_28__ap[26]) + ); + SDFF_X1_LVT \registers_reg[20][26] ( + .CK(n_0_50), .D(registers[26]), .Q(registers_20__ap[26]), .QN(), .SE(dftIn), + .SI(registers_21__ap[26]) + ); + AOI22_X1_LVT i_1_0_1212( + .A1(registers_24__ap[26]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[26]), + .ZN(n_1_0_1153) + ); + NAND3_X1_LVT i_1_0_1211( + .A1(n_1_0_1155), .A2(n_1_0_1154), .A3(n_1_0_1153), .ZN(n_1_0_1152) + ); + SDFF_X1_LVT \registers_reg[26][26] ( + .CK(n_0_56), .D(registers[26]), .Q(registers_26__ap[26]), .QN(), .SE(dftIn), + .SI(registers_24__ap[26]) + ); + SDFF_X1_LVT \registers_reg[30][26] ( + .CK(n_0_60), .D(registers[26]), .Q(registers_30__ap[26]), .QN(), .SE(dftIn), + .SI(registers_26__ap[26]) + ); + AOI221_X1_LVT i_1_0_1210( + .A(n_1_0_1152), .B1(n_1_0_1285), .B2(registers_26__ap[26]), .C1(registers_30__ap[26]), + .C2(n_1_0_1272), .ZN(n_1_0_1151) + ); + SDFF_X1_LVT \registers_reg[8][26] ( + .CK(n_0_38), .D(registers[26]), .Q(registers_8__ap[26]), .QN(), .SE(dftIn), + .SI(registers_4__ap[26]) + ); + SDFF_X1_LVT \registers_reg[23][26] ( + .CK(n_0_53), .D(registers[26]), .Q(registers_23__ap[26]), .QN(), .SE(dftIn), + .SI(registers_20__ap[26]) + ); + AOI22_X1_LVT i_1_0_1209( + .A1(registers_8__ap[26]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[26]), + .ZN(n_1_0_1150) + ); + SDFF_X1_LVT \registers_reg[13][26] ( + .CK(n_0_43), .D(registers[26]), .Q(registers_13__ap[26]), .QN(), .SE(dftIn), + .SI(registers_12__ap[26]) + ); + SDFF_X1_LVT \registers_reg[17][26] ( + .CK(n_0_47), .D(registers[26]), .Q(registers_17__ap[26]), .QN(), .SE(dftIn), + .SI(registers_23__ap[26]) + ); + AOI22_X1_LVT i_1_0_1208( + .A1(registers_13__ap[26]), .A2(n_1_0_1277), .B1(n_1_0_1271), .B2(registers_17__ap[26]), + .ZN(n_1_0_1149) + ); + SDFF_X1_LVT \registers_reg[15][26] ( + .CK(n_0_45), .D(registers[26]), .Q(registers_15__ap[26]), .QN(), .SE(dftIn), + .SI(registers_13__ap[26]) + ); + SDFF_X1_LVT \registers_reg[14][26] ( + .CK(n_0_44), .D(registers[26]), .Q(registers_14__ap[26]), .QN(), .SE(dftIn), + .SI(registers_15__ap[26]) + ); + AOI22_X1_LVT i_1_0_1207( + .A1(registers_15__ap[26]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[26]), + .ZN(n_1_0_1148) + ); + NAND3_X1_LVT i_1_0_1206( + .A1(n_1_0_1150), .A2(n_1_0_1149), .A3(n_1_0_1148), .ZN(n_1_0_1147) + ); + SDFF_X1_LVT \registers_reg[10][26] ( + .CK(n_0_40), .D(registers[26]), .Q(registers_10__ap[26]), .QN(), .SE(dftIn), + .SI(registers_14__ap[26]) + ); + SDFF_X1_LVT \registers_reg[3][26] ( + .CK(n_0_33), .D(registers[26]), .Q(registers_3__ap[26]), .QN(), .SE(dftIn), + .SI(registers_8__ap[26]) + ); + AOI221_X1_LVT i_1_0_1205( + .A(n_1_0_1147), .B1(n_1_0_1287), .B2(registers_10__ap[26]), .C1(registers_3__ap[26]), + .C2(n_1_0_1257), .ZN(n_1_0_1146) + ); + NAND3_X1_LVT i_1_0_1204( + .A1(n_1_0_1156), .A2(n_1_0_1151), .A3(n_1_0_1146), .ZN(RRs1[26]) + ); + AND2_X1_LVT i_0_0_25( + .A1(n_0_0_16), .A2(WRd[25]), .ZN(registers[25]) + ); + SDFF_X1_LVT \registers_reg[17][25] ( + .CK(n_0_47), .D(registers[25]), .Q(registers_17__ap[25]), .QN(), .SE(dftIn), + .SI(registers_17__ap[26]) + ); + SDFF_X1_LVT \registers_reg[21][25] ( + .CK(n_0_51), .D(registers[25]), .Q(registers_21__ap[25]), .QN(), .SE(dftIn), + .SI(registers_17__ap[25]) + ); + AOI22_X1_LVT i_1_0_1202( + .A1(registers_17__ap[25]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[25]), + .ZN(n_1_0_1144) + ); + SDFF_X1_LVT \registers_reg[6][25] ( + .CK(n_0_36), .D(registers[25]), .Q(registers_6__ap[25]), .QN(), .SE(dftIn), + .SI(registers_3__ap[26]) + ); + SDFF_X1_LVT \registers_reg[8][25] ( + .CK(n_0_38), .D(registers[25]), .Q(registers_8__ap[25]), .QN(), .SE(dftIn), + .SI(registers_6__ap[25]) + ); + AOI22_X1_LVT i_1_0_1203( + .A1(registers_6__ap[25]), .A2(n_1_0_1300), .B1(n_1_0_1282), .B2(registers_8__ap[25]), + .ZN(n_1_0_1145) + ); + SDFF_X1_LVT \registers_reg[20][25] ( + .CK(n_0_50), .D(registers[25]), .Q(registers_20__ap[25]), .QN(), .SE(dftIn), + .SI(registers_21__ap[25]) + ); + SDFF_X1_LVT \registers_reg[12][25] ( + .CK(n_0_42), .D(registers[25]), .Q(registers_12__ap[25]), .QN(), .SE(dftIn), + .SI(registers_10__ap[26]) + ); + AOI22_X1_LVT i_1_0_1201( + .A1(registers_20__ap[25]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[25]), + .ZN(n_1_0_1143) + ); + SDFF_X1_LVT \registers_reg[5][25] ( + .CK(n_0_35), .D(registers[25]), .Q(registers_5__ap[25]), .QN(), .SE(dftIn), + .SI(registers_8__ap[25]) + ); + SDFF_X1_LVT \registers_reg[11][25] ( + .CK(n_0_41), .D(registers[25]), .Q(registers_11__ap[25]), .QN(), .SE(dftIn), + .SI(registers_12__ap[25]) + ); + AOI22_X1_LVT i_1_0_1200( + .A1(registers_5__ap[25]), .A2(n_1_0_1273), .B1(n_1_0_1270), .B2(registers_11__ap[25]), + .ZN(n_1_0_1142) + ); + NAND3_X1_LVT i_1_0_1199( + .A1(n_1_0_1145), .A2(n_1_0_1143), .A3(n_1_0_1142), .ZN(n_1_0_1141) + ); + SDFF_X1_LVT \registers_reg[10][25] ( + .CK(n_0_40), .D(registers[25]), .Q(registers_10__ap[25]), .QN(), .SE(dftIn), + .SI(registers_11__ap[25]) + ); + SDFF_X1_LVT \registers_reg[2][25] ( + .CK(n_0_32), .D(registers[25]), .Q(registers_2__ap[25]), .QN(), .SE(dftIn), + .SI(registers_30__ap[26]) + ); + AOI221_X1_LVT i_1_0_1198( + .A(n_1_0_1141), .B1(n_1_0_1287), .B2(registers_10__ap[25]), .C1(registers_2__ap[25]), + .C2(n_1_0_1268), .ZN(n_1_0_1140) + ); + SDFF_X1_LVT \registers_reg[13][25] ( + .CK(n_0_43), .D(registers[25]), .Q(registers_13__ap[25]), .QN(), .SE(dftIn), + .SI(registers_10__ap[25]) + ); + SDFF_X1_LVT \registers_reg[30][25] ( + .CK(n_0_60), .D(registers[25]), .Q(registers_30__ap[25]), .QN(), .SE(dftIn), + .SI(registers_2__ap[25]) + ); + SDFF_X1_LVT \registers_reg[22][25] ( + .CK(n_0_52), .D(registers[25]), .Q(registers_22__ap[25]), .QN(), .SE(dftIn), + .SI(registers_20__ap[25]) + ); + AOI222_X1_LVT i_1_0_1197( + .A1(registers_13__ap[25]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[25]), + .C1(registers_22__ap[25]), .C2(n_1_0_1294), .ZN(n_1_0_1139) + ); + NAND2_X1_LVT i_1_0_1196( + .A1(n_1_0_1140), .A2(n_1_0_1139), .ZN(n_1_0_1138) + ); + SDFF_X1_LVT \registers_reg[1][25] ( + .CK(n_0_0), .D(registers[25]), .Q(registers_1__ap[25]), .QN(), .SE(dftIn), + .SI(registers_22__ap[25]) + ); + SDFF_X1_LVT \registers_reg[28][25] ( + .CK(n_0_58), .D(registers[25]), .Q(registers_28__ap[25]), .QN(), .SE(dftIn), + .SI(registers_30__ap[25]) + ); + AOI221_X1_LVT i_1_0_1195( + .A(n_1_0_1138), .B1(n_1_0_1274), .B2(registers_1__ap[25]), .C1(registers_28__ap[25]), + .C2(n_1_0_1283), .ZN(n_1_0_1137) + ); + SDFF_X1_LVT \registers_reg[18][25] ( + .CK(n_0_48), .D(registers[25]), .Q(registers_18__ap[25]), .QN(), .SE(dftIn), + .SI(registers_1__ap[25]) + ); + SDFF_X1_LVT \registers_reg[26][25] ( + .CK(n_0_56), .D(registers[25]), .Q(registers_26__ap[25]), .QN(), .SE(dftIn), + .SI(registers_28__ap[25]) + ); + AOI22_X1_LVT i_1_0_1194( + .A1(registers_18__ap[25]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[25]), + .ZN(n_1_0_1136) + ); + SDFF_X1_LVT \registers_reg[24][25] ( + .CK(n_0_54), .D(registers[25]), .Q(registers_24__ap[25]), .QN(), .SE(dftIn), + .SI(registers_26__ap[25]) + ); + SDFF_X1_LVT \registers_reg[4][25] ( + .CK(n_0_34), .D(registers[25]), .Q(registers_4__ap[25]), .QN(), .SE(dftIn), + .SI(registers_5__ap[25]) + ); + AOI22_X1_LVT i_1_0_1193( + .A1(registers_24__ap[25]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[25]), + .ZN(n_1_0_1135) + ); + SDFF_X1_LVT \registers_reg[15][25] ( + .CK(n_0_45), .D(registers[25]), .Q(registers_15__ap[25]), .QN(), .SE(dftIn), + .SI(registers_13__ap[25]) + ); + SDFF_X1_LVT \registers_reg[16][25] ( + .CK(n_0_46), .D(registers[25]), .Q(registers_16__ap[25]), .QN(), .SE(dftIn), + .SI(registers_15__ap[25]) + ); + AOI22_X1_LVT i_1_0_1192( + .A1(registers_15__ap[25]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[25]), + .ZN(n_1_0_1134) + ); + NAND3_X1_LVT i_1_0_1191( + .A1(n_1_0_1136), .A2(n_1_0_1135), .A3(n_1_0_1134), .ZN(n_1_0_1133) + ); + SDFF_X1_LVT \registers_reg[19][25] ( + .CK(n_0_49), .D(registers[25]), .Q(registers_19__ap[25]), .QN(), .SE(dftIn), + .SI(registers_18__ap[25]) + ); + SDFF_X1_LVT \registers_reg[25][25] ( + .CK(n_0_55), .D(registers[25]), .Q(registers_25__ap[25]), .QN(), .SE(dftIn), + .SI(registers_24__ap[25]) + ); + AOI221_X1_LVT i_1_0_1190( + .A(n_1_0_1133), .B1(n_1_0_1295), .B2(registers_19__ap[25]), .C1(registers_25__ap[25]), + .C2(n_1_0_1269), .ZN(n_1_0_1132) + ); + SDFF_X1_LVT \registers_reg[7][25] ( + .CK(n_0_37), .D(registers[25]), .Q(registers_7__ap[25]), .QN(), .SE(dftIn), + .SI(registers_4__ap[25]) + ); + SDFF_X1_LVT \registers_reg[14][25] ( + .CK(n_0_44), .D(registers[25]), .Q(registers_14__ap[25]), .QN(), .SE(dftIn), + .SI(registers_16__ap[25]) + ); + AOI22_X1_LVT i_1_0_1189( + .A1(registers_7__ap[25]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[25]), + .ZN(n_1_0_1131) + ); + SDFF_X1_LVT \registers_reg[9][25] ( + .CK(n_0_39), .D(registers[25]), .Q(registers_9__ap[25]), .QN(), .SE(dftIn), + .SI(registers_7__ap[25]) + ); + SDFF_X1_LVT \registers_reg[29][25] ( + .CK(n_0_59), .D(registers[25]), .Q(registers_29__ap[25]), .QN(), .SE(dftIn), + .SI(registers_25__ap[25]) + ); + AOI22_X1_LVT i_1_0_1188( + .A1(registers_9__ap[25]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[25]), + .ZN(n_1_0_1130) + ); + SDFF_X1_LVT \registers_reg[23][25] ( + .CK(n_0_53), .D(registers[25]), .Q(registers_23__ap[25]), .QN(), .SE(dftIn), + .SI(registers_19__ap[25]) + ); + SDFF_X1_LVT \registers_reg[3][25] ( + .CK(n_0_33), .D(registers[25]), .Q(registers_3__ap[25]), .QN(), .SE(dftIn), + .SI(registers_9__ap[25]) + ); + AOI22_X1_LVT i_1_0_1187( + .A1(registers_23__ap[25]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[25]), + .ZN(n_1_0_1129) + ); + NAND3_X1_LVT i_1_0_1186( + .A1(n_1_0_1131), .A2(n_1_0_1130), .A3(n_1_0_1129), .ZN(n_1_0_1128) + ); + SDFF_X1_LVT \registers_reg[27][25] ( + .CK(n_0_57), .D(registers[25]), .Q(registers_27__ap[25]), .QN(), .SE(dftIn), + .SI(registers_29__ap[25]) + ); + SDFF_X1_LVT \registers_reg[31][25] ( + .CK(n_0_61), .D(registers[25]), .Q(registers_31__ap[25]), .QN(), .SE(dftIn), + .SI(registers_3__ap[25]) + ); + AOI221_X1_LVT i_1_0_1185( + .A(n_1_0_1128), .B1(n_1_0_1279), .B2(registers_27__ap[25]), .C1(registers_31__ap[25]), + .C2(n_1_0_1266), .ZN(n_1_0_1127) + ); + NAND4_X1_LVT i_1_0_1184( + .A1(n_1_0_1144), .A2(n_1_0_1137), .A3(n_1_0_1132), .A4(n_1_0_1127), .ZN(RRs1[25]) + ); + AND2_X1_LVT i_0_0_24( + .A1(n_0_0_16), .A2(WRd[24]), .ZN(registers[24]) + ); + SDFF_X1_LVT \registers_reg[17][24] ( + .CK(n_0_47), .D(registers[24]), .Q(registers_17__ap[24]), .QN(), .SE(dftIn), + .SI(registers_23__ap[25]) + ); + SDFF_X1_LVT \registers_reg[21][24] ( + .CK(n_0_51), .D(registers[24]), .Q(registers_21__ap[24]), .QN(), .SE(dftIn), + .SI(registers_17__ap[24]) + ); + AOI22_X1_LVT i_1_0_1182( + .A1(registers_17__ap[24]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[24]), + .ZN(n_1_0_1125) + ); + SDFF_X1_LVT \registers_reg[6][24] ( + .CK(n_0_36), .D(registers[24]), .Q(registers_6__ap[24]), .QN(), .SE(dftIn), + .SI(registers_31__ap[25]) + ); + SDFF_X1_LVT \registers_reg[8][24] ( + .CK(n_0_38), .D(registers[24]), .Q(registers_8__ap[24]), .QN(), .SE(dftIn), + .SI(registers_6__ap[24]) + ); + AOI22_X1_LVT i_1_0_1183( + .A1(registers_6__ap[24]), .A2(n_1_0_1300), .B1(n_1_0_1282), .B2(registers_8__ap[24]), + .ZN(n_1_0_1126) + ); + SDFF_X1_LVT \registers_reg[20][24] ( + .CK(n_0_50), .D(registers[24]), .Q(registers_20__ap[24]), .QN(), .SE(dftIn), + .SI(registers_21__ap[24]) + ); + SDFF_X1_LVT \registers_reg[12][24] ( + .CK(n_0_42), .D(registers[24]), .Q(registers_12__ap[24]), .QN(), .SE(dftIn), + .SI(registers_14__ap[25]) + ); + AOI22_X1_LVT i_1_0_1181( + .A1(registers_20__ap[24]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[24]), + .ZN(n_1_0_1124) + ); + SDFF_X1_LVT \registers_reg[5][24] ( + .CK(n_0_35), .D(registers[24]), .Q(registers_5__ap[24]), .QN(), .SE(dftIn), + .SI(registers_8__ap[24]) + ); + SDFF_X1_LVT \registers_reg[11][24] ( + .CK(n_0_41), .D(registers[24]), .Q(registers_11__ap[24]), .QN(), .SE(dftIn), + .SI(registers_12__ap[24]) + ); + AOI22_X1_LVT i_1_0_1180( + .A1(registers_5__ap[24]), .A2(n_1_0_1273), .B1(n_1_0_1270), .B2(registers_11__ap[24]), + .ZN(n_1_0_1123) + ); + NAND3_X1_LVT i_1_0_1179( + .A1(n_1_0_1126), .A2(n_1_0_1124), .A3(n_1_0_1123), .ZN(n_1_0_1122) + ); + SDFF_X1_LVT \registers_reg[10][24] ( + .CK(n_0_40), .D(registers[24]), .Q(registers_10__ap[24]), .QN(), .SE(dftIn), + .SI(registers_11__ap[24]) + ); + SDFF_X1_LVT \registers_reg[2][24] ( + .CK(n_0_32), .D(registers[24]), .Q(registers_2__ap[24]), .QN(), .SE(dftIn), + .SI(registers_27__ap[25]) + ); + AOI221_X1_LVT i_1_0_1178( + .A(n_1_0_1122), .B1(n_1_0_1287), .B2(registers_10__ap[24]), .C1(registers_2__ap[24]), + .C2(n_1_0_1268), .ZN(n_1_0_1121) + ); + SDFF_X1_LVT \registers_reg[13][24] ( + .CK(n_0_43), .D(registers[24]), .Q(registers_13__ap[24]), .QN(), .SE(dftIn), + .SI(registers_10__ap[24]) + ); + SDFF_X1_LVT \registers_reg[30][24] ( + .CK(n_0_60), .D(registers[24]), .Q(registers_30__ap[24]), .QN(), .SE(dftIn), + .SI(registers_2__ap[24]) + ); + SDFF_X1_LVT \registers_reg[22][24] ( + .CK(n_0_52), .D(registers[24]), .Q(registers_22__ap[24]), .QN(), .SE(dftIn), + .SI(registers_20__ap[24]) + ); + AOI222_X1_LVT i_1_0_1177( + .A1(registers_13__ap[24]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[24]), + .C1(registers_22__ap[24]), .C2(n_1_0_1294), .ZN(n_1_0_1120) + ); + NAND2_X1_LVT i_1_0_1176( + .A1(n_1_0_1121), .A2(n_1_0_1120), .ZN(n_1_0_1119) + ); + SDFF_X1_LVT \registers_reg[1][24] ( + .CK(n_0_0), .D(registers[24]), .Q(registers_1__ap[24]), .QN(), .SE(dftIn), + .SI(registers_22__ap[24]) + ); + SDFF_X1_LVT \registers_reg[28][24] ( + .CK(n_0_58), .D(registers[24]), .Q(registers_28__ap[24]), .QN(), .SE(dftIn), + .SI(registers_30__ap[24]) + ); + AOI221_X1_LVT i_1_0_1175( + .A(n_1_0_1119), .B1(n_1_0_1274), .B2(registers_1__ap[24]), .C1(registers_28__ap[24]), + .C2(n_1_0_1283), .ZN(n_1_0_1118) + ); + SDFF_X1_LVT \registers_reg[18][24] ( + .CK(n_0_48), .D(registers[24]), .Q(registers_18__ap[24]), .QN(), .SE(dftIn), + .SI(registers_1__ap[24]) + ); + SDFF_X1_LVT \registers_reg[26][24] ( + .CK(n_0_56), .D(registers[24]), .Q(registers_26__ap[24]), .QN(), .SE(dftIn), + .SI(registers_28__ap[24]) + ); + AOI22_X1_LVT i_1_0_1174( + .A1(registers_18__ap[24]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[24]), + .ZN(n_1_0_1117) + ); + SDFF_X1_LVT \registers_reg[24][24] ( + .CK(n_0_54), .D(registers[24]), .Q(registers_24__ap[24]), .QN(), .SE(dftIn), + .SI(registers_26__ap[24]) + ); + SDFF_X1_LVT \registers_reg[4][24] ( + .CK(n_0_34), .D(registers[24]), .Q(registers_4__ap[24]), .QN(), .SE(dftIn), + .SI(registers_5__ap[24]) + ); + AOI22_X1_LVT i_1_0_1173( + .A1(registers_24__ap[24]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[24]), + .ZN(n_1_0_1116) + ); + SDFF_X1_LVT \registers_reg[15][24] ( + .CK(n_0_45), .D(registers[24]), .Q(registers_15__ap[24]), .QN(), .SE(dftIn), + .SI(registers_13__ap[24]) + ); + SDFF_X1_LVT \registers_reg[25][24] ( + .CK(n_0_55), .D(registers[24]), .Q(registers_25__ap[24]), .QN(), .SE(dftIn), + .SI(registers_24__ap[24]) + ); + AOI22_X1_LVT i_1_0_1172( + .A1(registers_15__ap[24]), .A2(n_1_0_1286), .B1(n_1_0_1269), .B2(registers_25__ap[24]), + .ZN(n_1_0_1115) + ); + NAND3_X1_LVT i_1_0_1171( + .A1(n_1_0_1117), .A2(n_1_0_1116), .A3(n_1_0_1115), .ZN(n_1_0_1114) + ); + SDFF_X1_LVT \registers_reg[19][24] ( + .CK(n_0_49), .D(registers[24]), .Q(registers_19__ap[24]), .QN(), .SE(dftIn), + .SI(registers_18__ap[24]) + ); + SDFF_X1_LVT \registers_reg[16][24] ( + .CK(n_0_46), .D(registers[24]), .Q(registers_16__ap[24]), .QN(), .SE(dftIn), + .SI(registers_15__ap[24]) + ); + AOI221_X1_LVT i_1_0_1170( + .A(n_1_0_1114), .B1(n_1_0_1295), .B2(registers_19__ap[24]), .C1(registers_16__ap[24]), + .C2(n_1_0_1267), .ZN(n_1_0_1113) + ); + SDFF_X1_LVT \registers_reg[7][24] ( + .CK(n_0_37), .D(registers[24]), .Q(registers_7__ap[24]), .QN(), .SE(dftIn), + .SI(registers_4__ap[24]) + ); + SDFF_X1_LVT \registers_reg[14][24] ( + .CK(n_0_44), .D(registers[24]), .Q(registers_14__ap[24]), .QN(), .SE(dftIn), + .SI(registers_16__ap[24]) + ); + AOI22_X1_LVT i_1_0_1169( + .A1(registers_7__ap[24]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[24]), + .ZN(n_1_0_1112) + ); + SDFF_X1_LVT \registers_reg[9][24] ( + .CK(n_0_39), .D(registers[24]), .Q(registers_9__ap[24]), .QN(), .SE(dftIn), + .SI(registers_7__ap[24]) + ); + SDFF_X1_LVT \registers_reg[29][24] ( + .CK(n_0_59), .D(registers[24]), .Q(registers_29__ap[24]), .QN(), .SE(dftIn), + .SI(registers_25__ap[24]) + ); + AOI22_X1_LVT i_1_0_1168( + .A1(registers_9__ap[24]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[24]), + .ZN(n_1_0_1111) + ); + SDFF_X1_LVT \registers_reg[23][24] ( + .CK(n_0_53), .D(registers[24]), .Q(registers_23__ap[24]), .QN(), .SE(dftIn), + .SI(registers_19__ap[24]) + ); + SDFF_X1_LVT \registers_reg[3][24] ( + .CK(n_0_33), .D(registers[24]), .Q(registers_3__ap[24]), .QN(), .SE(dftIn), + .SI(registers_9__ap[24]) + ); + AOI22_X1_LVT i_1_0_1167( + .A1(registers_23__ap[24]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[24]), + .ZN(n_1_0_1110) + ); + NAND3_X1_LVT i_1_0_1166( + .A1(n_1_0_1112), .A2(n_1_0_1111), .A3(n_1_0_1110), .ZN(n_1_0_1109) + ); + SDFF_X1_LVT \registers_reg[27][24] ( + .CK(n_0_57), .D(registers[24]), .Q(registers_27__ap[24]), .QN(), .SE(dftIn), + .SI(registers_29__ap[24]) + ); + SDFF_X1_LVT \registers_reg[31][24] ( + .CK(n_0_61), .D(registers[24]), .Q(registers_31__ap[24]), .QN(), .SE(dftIn), + .SI(registers_3__ap[24]) + ); + AOI221_X1_LVT i_1_0_1165( + .A(n_1_0_1109), .B1(n_1_0_1279), .B2(registers_27__ap[24]), .C1(registers_31__ap[24]), + .C2(n_1_0_1266), .ZN(n_1_0_1108) + ); + NAND4_X1_LVT i_1_0_1164( + .A1(n_1_0_1125), .A2(n_1_0_1118), .A3(n_1_0_1113), .A4(n_1_0_1108), .ZN(RRs1[24]) + ); + AND2_X1_LVT i_0_0_23( + .A1(n_0_0_16), .A2(WRd[23]), .ZN(registers[23]) + ); + SDFF_X1_LVT \registers_reg[9][23] ( + .CK(n_0_39), .D(registers[23]), .Q(registers_9__ap[23]), .QN(), .SE(dftIn), + .SI(registers_31__ap[24]) + ); + SDFF_X1_LVT \registers_reg[28][23] ( + .CK(n_0_58), .D(registers[23]), .Q(registers_28__ap[23]), .QN(), .SE(dftIn), + .SI(registers_27__ap[24]) + ); + AOI22_X1_LVT i_1_0_1163( + .A1(registers_9__ap[23]), .A2(n_1_0_1291), .B1(n_1_0_1283), .B2(registers_28__ap[23]), + .ZN(n_1_0_1107) + ); + SDFF_X1_LVT \registers_reg[18][23] ( + .CK(n_0_48), .D(registers[23]), .Q(registers_18__ap[23]), .QN(), .SE(dftIn), + .SI(registers_23__ap[24]) + ); + SDFF_X1_LVT \registers_reg[22][23] ( + .CK(n_0_52), .D(registers[23]), .Q(registers_22__ap[23]), .QN(), .SE(dftIn), + .SI(registers_18__ap[23]) + ); + AOI22_X1_LVT i_1_0_1160( + .A1(registers_18__ap[23]), .A2(n_1_0_1297), .B1(n_1_0_1294), .B2(registers_22__ap[23]), + .ZN(n_1_0_1104) + ); + SDFF_X1_LVT \registers_reg[1][23] ( + .CK(n_0_0), .D(registers[23]), .Q(registers_1__ap[23]), .QN(), .SE(dftIn), + .SI(registers_22__ap[23]) + ); + SDFF_X1_LVT \registers_reg[21][23] ( + .CK(n_0_51), .D(registers[23]), .Q(registers_21__ap[23]), .QN(), .SE(dftIn), + .SI(registers_1__ap[23]) + ); + AOI22_X1_LVT i_1_0_1159( + .A1(registers_1__ap[23]), .A2(n_1_0_1274), .B1(n_1_0_1259), .B2(registers_21__ap[23]), + .ZN(n_1_0_1103) + ); + NAND3_X1_LVT i_1_0_1157( + .A1(n_1_0_1107), .A2(n_1_0_1104), .A3(n_1_0_1103), .ZN(n_1_0_1101) + ); + SDFF_X1_LVT \registers_reg[20][23] ( + .CK(n_0_50), .D(registers[23]), .Q(registers_20__ap[23]), .QN(), .SE(dftIn), + .SI(registers_21__ap[23]) + ); + SDFF_X1_LVT \registers_reg[19][23] ( + .CK(n_0_49), .D(registers[23]), .Q(registers_19__ap[23]), .QN(), .SE(dftIn), + .SI(registers_20__ap[23]) + ); + AOI221_X1_LVT i_1_0_1156( + .A(n_1_0_1101), .B1(n_1_0_1281), .B2(registers_20__ap[23]), .C1(registers_19__ap[23]), + .C2(n_1_0_1295), .ZN(n_1_0_1100) + ); + SDFF_X1_LVT \registers_reg[26][23] ( + .CK(n_0_56), .D(registers[23]), .Q(registers_26__ap[23]), .QN(), .SE(dftIn), + .SI(registers_28__ap[23]) + ); + SDFF_X1_LVT \registers_reg[23][23] ( + .CK(n_0_53), .D(registers[23]), .Q(registers_23__ap[23]), .QN(), .SE(dftIn), + .SI(registers_19__ap[23]) + ); + AOI22_X1_LVT i_1_0_1162( + .A1(registers_26__ap[23]), .A2(n_1_0_1285), .B1(n_1_0_1264), .B2(registers_23__ap[23]), + .ZN(n_1_0_1106) + ); + SDFF_X1_LVT \registers_reg[29][23] ( + .CK(n_0_59), .D(registers[23]), .Q(registers_29__ap[23]), .QN(), .SE(dftIn), + .SI(registers_26__ap[23]) + ); + SDFF_X1_LVT \registers_reg[3][23] ( + .CK(n_0_33), .D(registers[23]), .Q(registers_3__ap[23]), .QN(), .SE(dftIn), + .SI(registers_9__ap[23]) + ); + AOI22_X1_LVT i_1_0_1161( + .A1(registers_29__ap[23]), .A2(n_1_0_1276), .B1(n_1_0_1257), .B2(registers_3__ap[23]), + .ZN(n_1_0_1105) + ); + SDFF_X1_LVT \registers_reg[30][23] ( + .CK(n_0_60), .D(registers[23]), .Q(registers_30__ap[23]), .QN(), .SE(dftIn), + .SI(registers_29__ap[23]) + ); + SDFF_X1_LVT \registers_reg[31][23] ( + .CK(n_0_61), .D(registers[23]), .Q(registers_31__ap[23]), .QN(), .SE(dftIn), + .SI(registers_3__ap[23]) + ); + AOI22_X1_LVT i_1_0_1158( + .A1(registers_30__ap[23]), .A2(n_1_0_1272), .B1(n_1_0_1266), .B2(registers_31__ap[23]), + .ZN(n_1_0_1102) + ); + NAND3_X1_LVT i_1_0_1155( + .A1(n_1_0_1106), .A2(n_1_0_1105), .A3(n_1_0_1102), .ZN(n_1_0_1099) + ); + SDFF_X1_LVT \registers_reg[8][23] ( + .CK(n_0_38), .D(registers[23]), .Q(registers_8__ap[23]), .QN(), .SE(dftIn), + .SI(registers_31__ap[23]) + ); + SDFF_X1_LVT \registers_reg[17][23] ( + .CK(n_0_47), .D(registers[23]), .Q(registers_17__ap[23]), .QN(), .SE(dftIn), + .SI(registers_23__ap[23]) + ); + AOI221_X1_LVT i_1_0_1154( + .A(n_1_0_1099), .B1(n_1_0_1282), .B2(registers_8__ap[23]), .C1(registers_17__ap[23]), + .C2(n_1_0_1271), .ZN(n_1_0_1098) + ); + SDFF_X1_LVT \registers_reg[24][23] ( + .CK(n_0_54), .D(registers[23]), .Q(registers_24__ap[23]), .QN(), .SE(dftIn), + .SI(registers_30__ap[23]) + ); + SDFF_X1_LVT \registers_reg[15][23] ( + .CK(n_0_45), .D(registers[23]), .Q(registers_15__ap[23]), .QN(), .SE(dftIn), + .SI(registers_14__ap[24]) + ); + SDFF_X1_LVT \registers_reg[14][23] ( + .CK(n_0_44), .D(registers[23]), .Q(registers_14__ap[23]), .QN(), .SE(dftIn), + .SI(registers_15__ap[23]) + ); + AOI222_X1_LVT i_1_0_1153( + .A1(registers_24__ap[23]), .A2(n_1_0_1289), .B1(n_1_0_1286), .B2(registers_15__ap[23]), + .C1(n_1_0_1258), .C2(registers_14__ap[23]), .ZN(n_1_0_1097) + ); + SDFF_X1_LVT \registers_reg[16][23] ( + .CK(n_0_46), .D(registers[23]), .Q(registers_16__ap[23]), .QN(), .SE(dftIn), + .SI(registers_14__ap[23]) + ); + SDFF_X1_LVT \registers_reg[7][23] ( + .CK(n_0_37), .D(registers[23]), .Q(registers_7__ap[23]), .QN(), .SE(dftIn), + .SI(registers_8__ap[23]) + ); + AOI22_X1_LVT i_1_0_1152( + .A1(registers_16__ap[23]), .A2(n_1_0_1267), .B1(n_1_0_1263), .B2(registers_7__ap[23]), + .ZN(n_1_0_1096) + ); + SDFF_X1_LVT \registers_reg[6][23] ( + .CK(n_0_36), .D(registers[23]), .Q(registers_6__ap[23]), .QN(), .SE(dftIn), + .SI(registers_7__ap[23]) + ); + SDFF_X1_LVT \registers_reg[25][23] ( + .CK(n_0_55), .D(registers[23]), .Q(registers_25__ap[23]), .QN(), .SE(dftIn), + .SI(registers_24__ap[23]) + ); + AOI22_X1_LVT i_1_0_1151( + .A1(registers_6__ap[23]), .A2(n_1_0_1300), .B1(n_1_0_1269), .B2(registers_25__ap[23]), + .ZN(n_1_0_1095) + ); + SDFF_X1_LVT \registers_reg[27][23] ( + .CK(n_0_57), .D(registers[23]), .Q(registers_27__ap[23]), .QN(), .SE(dftIn), + .SI(registers_25__ap[23]) + ); + SDFF_X1_LVT \registers_reg[11][23] ( + .CK(n_0_41), .D(registers[23]), .Q(registers_11__ap[23]), .QN(), .SE(dftIn), + .SI(registers_16__ap[23]) + ); + AOI22_X1_LVT i_1_0_1150( + .A1(registers_27__ap[23]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[23]), + .ZN(n_1_0_1094) + ); + SDFF_X1_LVT \registers_reg[13][23] ( + .CK(n_0_43), .D(registers[23]), .Q(registers_13__ap[23]), .QN(), .SE(dftIn), + .SI(registers_11__ap[23]) + ); + SDFF_X1_LVT \registers_reg[5][23] ( + .CK(n_0_35), .D(registers[23]), .Q(registers_5__ap[23]), .QN(), .SE(dftIn), + .SI(registers_6__ap[23]) + ); + AOI22_X1_LVT i_1_0_1149( + .A1(registers_13__ap[23]), .A2(n_1_0_1277), .B1(n_1_0_1273), .B2(registers_5__ap[23]), + .ZN(n_1_0_1093) + ); + SDFF_X1_LVT \registers_reg[4][23] ( + .CK(n_0_34), .D(registers[23]), .Q(registers_4__ap[23]), .QN(), .SE(dftIn), + .SI(registers_5__ap[23]) + ); + SDFF_X1_LVT \registers_reg[12][23] ( + .CK(n_0_42), .D(registers[23]), .Q(registers_12__ap[23]), .QN(), .SE(dftIn), + .SI(registers_13__ap[23]) + ); + AOI22_X1_LVT i_1_0_1148( + .A1(registers_4__ap[23]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[23]), + .ZN(n_1_0_1092) + ); + NAND3_X1_LVT i_1_0_1147( + .A1(n_1_0_1094), .A2(n_1_0_1093), .A3(n_1_0_1092), .ZN(n_1_0_1091) + ); + SDFF_X1_LVT \registers_reg[2][23] ( + .CK(n_0_32), .D(registers[23]), .Q(registers_2__ap[23]), .QN(), .SE(dftIn), + .SI(registers_27__ap[23]) + ); + SDFF_X1_LVT \registers_reg[10][23] ( + .CK(n_0_40), .D(registers[23]), .Q(registers_10__ap[23]), .QN(), .SE(dftIn), + .SI(registers_12__ap[23]) + ); + AOI221_X1_LVT i_1_0_1146( + .A(n_1_0_1091), .B1(n_1_0_1268), .B2(registers_2__ap[23]), .C1(registers_10__ap[23]), + .C2(n_1_0_1287), .ZN(n_1_0_1090) + ); + AND4_X1_LVT i_1_0_1145( + .A1(n_1_0_1097), .A2(n_1_0_1096), .A3(n_1_0_1095), .A4(n_1_0_1090), .ZN(n_1_0_1089) + ); + NAND3_X1_LVT i_1_0_1144( + .A1(n_1_0_1100), .A2(n_1_0_1098), .A3(n_1_0_1089), .ZN(RRs1[23]) + ); + AND2_X1_LVT i_0_0_22( + .A1(n_0_0_16), .A2(WRd[22]), .ZN(registers[22]) + ); + SDFF_X1_LVT \registers_reg[17][22] ( + .CK(n_0_47), .D(registers[22]), .Q(registers_17__ap[22]), .QN(), .SE(dftIn), + .SI(registers_17__ap[23]) + ); + SDFF_X1_LVT \registers_reg[21][22] ( + .CK(n_0_51), .D(registers[22]), .Q(registers_21__ap[22]), .QN(), .SE(dftIn), + .SI(registers_17__ap[22]) + ); + AOI22_X1_LVT i_1_0_1142( + .A1(registers_17__ap[22]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[22]), + .ZN(n_1_0_1087) + ); + SDFF_X1_LVT \registers_reg[6][22] ( + .CK(n_0_36), .D(registers[22]), .Q(registers_6__ap[22]), .QN(), .SE(dftIn), + .SI(registers_4__ap[23]) + ); + SDFF_X1_LVT \registers_reg[11][22] ( + .CK(n_0_41), .D(registers[22]), .Q(registers_11__ap[22]), .QN(), .SE(dftIn), + .SI(registers_10__ap[23]) + ); + AOI22_X1_LVT i_1_0_1143( + .A1(registers_6__ap[22]), .A2(n_1_0_1300), .B1(n_1_0_1270), .B2(registers_11__ap[22]), + .ZN(n_1_0_1088) + ); + SDFF_X1_LVT \registers_reg[20][22] ( + .CK(n_0_50), .D(registers[22]), .Q(registers_20__ap[22]), .QN(), .SE(dftIn), + .SI(registers_21__ap[22]) + ); + SDFF_X1_LVT \registers_reg[12][22] ( + .CK(n_0_42), .D(registers[22]), .Q(registers_12__ap[22]), .QN(), .SE(dftIn), + .SI(registers_11__ap[22]) + ); + AOI22_X1_LVT i_1_0_1141( + .A1(registers_20__ap[22]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[22]), + .ZN(n_1_0_1086) + ); + SDFF_X1_LVT \registers_reg[10][22] ( + .CK(n_0_40), .D(registers[22]), .Q(registers_10__ap[22]), .QN(), .SE(dftIn), + .SI(registers_12__ap[22]) + ); + SDFF_X1_LVT \registers_reg[5][22] ( + .CK(n_0_35), .D(registers[22]), .Q(registers_5__ap[22]), .QN(), .SE(dftIn), + .SI(registers_6__ap[22]) + ); + AOI22_X1_LVT i_1_0_1140( + .A1(registers_10__ap[22]), .A2(n_1_0_1287), .B1(n_1_0_1273), .B2(registers_5__ap[22]), + .ZN(n_1_0_1085) + ); + NAND3_X1_LVT i_1_0_1139( + .A1(n_1_0_1088), .A2(n_1_0_1086), .A3(n_1_0_1085), .ZN(n_1_0_1084) + ); + SDFF_X1_LVT \registers_reg[31][22] ( + .CK(n_0_61), .D(registers[22]), .Q(registers_31__ap[22]), .QN(), .SE(dftIn), + .SI(registers_5__ap[22]) + ); + SDFF_X1_LVT \registers_reg[2][22] ( + .CK(n_0_32), .D(registers[22]), .Q(registers_2__ap[22]), .QN(), .SE(dftIn), + .SI(registers_2__ap[23]) + ); + AOI221_X1_LVT i_1_0_1138( + .A(n_1_0_1084), .B1(n_1_0_1266), .B2(registers_31__ap[22]), .C1(registers_2__ap[22]), + .C2(n_1_0_1268), .ZN(n_1_0_1083) + ); + SDFF_X1_LVT \registers_reg[22][22] ( + .CK(n_0_52), .D(registers[22]), .Q(registers_22__ap[22]), .QN(), .SE(dftIn), + .SI(registers_20__ap[22]) + ); + SDFF_X1_LVT \registers_reg[26][22] ( + .CK(n_0_56), .D(registers[22]), .Q(registers_26__ap[22]), .QN(), .SE(dftIn), + .SI(registers_2__ap[22]) + ); + SDFF_X1_LVT \registers_reg[13][22] ( + .CK(n_0_43), .D(registers[22]), .Q(registers_13__ap[22]), .QN(), .SE(dftIn), + .SI(registers_10__ap[22]) + ); + AOI222_X1_LVT i_1_0_1137( + .A1(registers_22__ap[22]), .A2(n_1_0_1294), .B1(n_1_0_1285), .B2(registers_26__ap[22]), + .C1(n_1_0_1277), .C2(registers_13__ap[22]), .ZN(n_1_0_1082) + ); + NAND2_X1_LVT i_1_0_1136( + .A1(n_1_0_1083), .A2(n_1_0_1082), .ZN(n_1_0_1081) + ); + SDFF_X1_LVT \registers_reg[1][22] ( + .CK(n_0_0), .D(registers[22]), .Q(registers_1__ap[22]), .QN(), .SE(dftIn), + .SI(registers_22__ap[22]) + ); + SDFF_X1_LVT \registers_reg[28][22] ( + .CK(n_0_58), .D(registers[22]), .Q(registers_28__ap[22]), .QN(), .SE(dftIn), + .SI(registers_26__ap[22]) + ); + AOI221_X1_LVT i_1_0_1135( + .A(n_1_0_1081), .B1(n_1_0_1274), .B2(registers_1__ap[22]), .C1(registers_28__ap[22]), + .C2(n_1_0_1283), .ZN(n_1_0_1080) + ); + SDFF_X1_LVT \registers_reg[18][22] ( + .CK(n_0_48), .D(registers[22]), .Q(registers_18__ap[22]), .QN(), .SE(dftIn), + .SI(registers_1__ap[22]) + ); + SDFF_X1_LVT \registers_reg[30][22] ( + .CK(n_0_60), .D(registers[22]), .Q(registers_30__ap[22]), .QN(), .SE(dftIn), + .SI(registers_28__ap[22]) + ); + AOI22_X1_LVT i_1_0_1134( + .A1(registers_18__ap[22]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[22]), + .ZN(n_1_0_1079) + ); + SDFF_X1_LVT \registers_reg[24][22] ( + .CK(n_0_54), .D(registers[22]), .Q(registers_24__ap[22]), .QN(), .SE(dftIn), + .SI(registers_30__ap[22]) + ); + SDFF_X1_LVT \registers_reg[4][22] ( + .CK(n_0_34), .D(registers[22]), .Q(registers_4__ap[22]), .QN(), .SE(dftIn), + .SI(registers_31__ap[22]) + ); + AOI22_X1_LVT i_1_0_1133( + .A1(registers_24__ap[22]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[22]), + .ZN(n_1_0_1078) + ); + SDFF_X1_LVT \registers_reg[15][22] ( + .CK(n_0_45), .D(registers[22]), .Q(registers_15__ap[22]), .QN(), .SE(dftIn), + .SI(registers_13__ap[22]) + ); + SDFF_X1_LVT \registers_reg[16][22] ( + .CK(n_0_46), .D(registers[22]), .Q(registers_16__ap[22]), .QN(), .SE(dftIn), + .SI(registers_15__ap[22]) + ); + AOI22_X1_LVT i_1_0_1132( + .A1(registers_15__ap[22]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[22]), + .ZN(n_1_0_1077) + ); + NAND3_X1_LVT i_1_0_1131( + .A1(n_1_0_1079), .A2(n_1_0_1078), .A3(n_1_0_1077), .ZN(n_1_0_1076) + ); + SDFF_X1_LVT \registers_reg[19][22] ( + .CK(n_0_49), .D(registers[22]), .Q(registers_19__ap[22]), .QN(), .SE(dftIn), + .SI(registers_18__ap[22]) + ); + SDFF_X1_LVT \registers_reg[25][22] ( + .CK(n_0_55), .D(registers[22]), .Q(registers_25__ap[22]), .QN(), .SE(dftIn), + .SI(registers_24__ap[22]) + ); + AOI221_X1_LVT i_1_0_1130( + .A(n_1_0_1076), .B1(n_1_0_1295), .B2(registers_19__ap[22]), .C1(registers_25__ap[22]), + .C2(n_1_0_1269), .ZN(n_1_0_1075) + ); + SDFF_X1_LVT \registers_reg[7][22] ( + .CK(n_0_37), .D(registers[22]), .Q(registers_7__ap[22]), .QN(), .SE(dftIn), + .SI(registers_4__ap[22]) + ); + SDFF_X1_LVT \registers_reg[14][22] ( + .CK(n_0_44), .D(registers[22]), .Q(registers_14__ap[22]), .QN(), .SE(dftIn), + .SI(registers_16__ap[22]) + ); + AOI22_X1_LVT i_1_0_1129( + .A1(registers_7__ap[22]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[22]), + .ZN(n_1_0_1074) + ); + SDFF_X1_LVT \registers_reg[9][22] ( + .CK(n_0_39), .D(registers[22]), .Q(registers_9__ap[22]), .QN(), .SE(dftIn), + .SI(registers_7__ap[22]) + ); + SDFF_X1_LVT \registers_reg[29][22] ( + .CK(n_0_59), .D(registers[22]), .Q(registers_29__ap[22]), .QN(), .SE(dftIn), + .SI(registers_25__ap[22]) + ); + AOI22_X1_LVT i_1_0_1128( + .A1(registers_9__ap[22]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[22]), + .ZN(n_1_0_1073) + ); + SDFF_X1_LVT \registers_reg[8][22] ( + .CK(n_0_38), .D(registers[22]), .Q(registers_8__ap[22]), .QN(), .SE(dftIn), + .SI(registers_9__ap[22]) + ); + SDFF_X1_LVT \registers_reg[23][22] ( + .CK(n_0_53), .D(registers[22]), .Q(registers_23__ap[22]), .QN(), .SE(dftIn), + .SI(registers_19__ap[22]) + ); + AOI22_X1_LVT i_1_0_1127( + .A1(registers_8__ap[22]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[22]), + .ZN(n_1_0_1072) + ); + NAND3_X1_LVT i_1_0_1126( + .A1(n_1_0_1074), .A2(n_1_0_1073), .A3(n_1_0_1072), .ZN(n_1_0_1071) + ); + SDFF_X1_LVT \registers_reg[27][22] ( + .CK(n_0_57), .D(registers[22]), .Q(registers_27__ap[22]), .QN(), .SE(dftIn), + .SI(registers_29__ap[22]) + ); + SDFF_X1_LVT \registers_reg[3][22] ( + .CK(n_0_33), .D(registers[22]), .Q(registers_3__ap[22]), .QN(), .SE(dftIn), + .SI(registers_8__ap[22]) + ); + AOI221_X1_LVT i_1_0_1125( + .A(n_1_0_1071), .B1(n_1_0_1279), .B2(registers_27__ap[22]), .C1(registers_3__ap[22]), + .C2(n_1_0_1257), .ZN(n_1_0_1070) + ); + NAND4_X1_LVT i_1_0_1124( + .A1(n_1_0_1087), .A2(n_1_0_1080), .A3(n_1_0_1075), .A4(n_1_0_1070), .ZN(RRs1[22]) + ); + AND2_X1_LVT i_0_0_21( + .A1(n_0_0_16), .A2(WRd[21]), .ZN(registers[21]) + ); + SDFF_X1_LVT \registers_reg[17][21] ( + .CK(n_0_47), .D(registers[21]), .Q(registers_17__ap[21]), .QN(), .SE(dftIn), + .SI(registers_23__ap[22]) + ); + SDFF_X1_LVT \registers_reg[21][21] ( + .CK(n_0_51), .D(registers[21]), .Q(registers_21__ap[21]), .QN(), .SE(dftIn), + .SI(registers_17__ap[21]) + ); + AOI22_X1_LVT i_1_0_1122( + .A1(registers_17__ap[21]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[21]), + .ZN(n_1_0_1068) + ); + SDFF_X1_LVT \registers_reg[6][21] ( + .CK(n_0_36), .D(registers[21]), .Q(registers_6__ap[21]), .QN(), .SE(dftIn), + .SI(registers_3__ap[22]) + ); + SDFF_X1_LVT \registers_reg[8][21] ( + .CK(n_0_38), .D(registers[21]), .Q(registers_8__ap[21]), .QN(), .SE(dftIn), + .SI(registers_6__ap[21]) + ); + AOI22_X1_LVT i_1_0_1123( + .A1(registers_6__ap[21]), .A2(n_1_0_1300), .B1(n_1_0_1282), .B2(registers_8__ap[21]), + .ZN(n_1_0_1069) + ); + SDFF_X1_LVT \registers_reg[20][21] ( + .CK(n_0_50), .D(registers[21]), .Q(registers_20__ap[21]), .QN(), .SE(dftIn), + .SI(registers_21__ap[21]) + ); + SDFF_X1_LVT \registers_reg[12][21] ( + .CK(n_0_42), .D(registers[21]), .Q(registers_12__ap[21]), .QN(), .SE(dftIn), + .SI(registers_14__ap[22]) + ); + AOI22_X1_LVT i_1_0_1121( + .A1(registers_20__ap[21]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[21]), + .ZN(n_1_0_1067) + ); + SDFF_X1_LVT \registers_reg[5][21] ( + .CK(n_0_35), .D(registers[21]), .Q(registers_5__ap[21]), .QN(), .SE(dftIn), + .SI(registers_8__ap[21]) + ); + SDFF_X1_LVT \registers_reg[11][21] ( + .CK(n_0_41), .D(registers[21]), .Q(registers_11__ap[21]), .QN(), .SE(dftIn), + .SI(registers_12__ap[21]) + ); + AOI22_X1_LVT i_1_0_1120( + .A1(registers_5__ap[21]), .A2(n_1_0_1273), .B1(n_1_0_1270), .B2(registers_11__ap[21]), + .ZN(n_1_0_1066) + ); + NAND3_X1_LVT i_1_0_1119( + .A1(n_1_0_1069), .A2(n_1_0_1067), .A3(n_1_0_1066), .ZN(n_1_0_1065) + ); + SDFF_X1_LVT \registers_reg[10][21] ( + .CK(n_0_40), .D(registers[21]), .Q(registers_10__ap[21]), .QN(), .SE(dftIn), + .SI(registers_11__ap[21]) + ); + SDFF_X1_LVT \registers_reg[2][21] ( + .CK(n_0_32), .D(registers[21]), .Q(registers_2__ap[21]), .QN(), .SE(dftIn), + .SI(registers_27__ap[22]) + ); + AOI221_X1_LVT i_1_0_1118( + .A(n_1_0_1065), .B1(n_1_0_1287), .B2(registers_10__ap[21]), .C1(registers_2__ap[21]), + .C2(n_1_0_1268), .ZN(n_1_0_1064) + ); + SDFF_X1_LVT \registers_reg[13][21] ( + .CK(n_0_43), .D(registers[21]), .Q(registers_13__ap[21]), .QN(), .SE(dftIn), + .SI(registers_10__ap[21]) + ); + SDFF_X1_LVT \registers_reg[30][21] ( + .CK(n_0_60), .D(registers[21]), .Q(registers_30__ap[21]), .QN(), .SE(dftIn), + .SI(registers_2__ap[21]) + ); + SDFF_X1_LVT \registers_reg[22][21] ( + .CK(n_0_52), .D(registers[21]), .Q(registers_22__ap[21]), .QN(), .SE(dftIn), + .SI(registers_20__ap[21]) + ); + AOI222_X1_LVT i_1_0_1117( + .A1(registers_13__ap[21]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[21]), + .C1(registers_22__ap[21]), .C2(n_1_0_1294), .ZN(n_1_0_1063) + ); + NAND2_X1_LVT i_1_0_1116( + .A1(n_1_0_1064), .A2(n_1_0_1063), .ZN(n_1_0_1062) + ); + SDFF_X1_LVT \registers_reg[1][21] ( + .CK(n_0_0), .D(registers[21]), .Q(registers_1__ap[21]), .QN(), .SE(dftIn), + .SI(registers_22__ap[21]) + ); + SDFF_X1_LVT \registers_reg[28][21] ( + .CK(n_0_58), .D(registers[21]), .Q(registers_28__ap[21]), .QN(), .SE(dftIn), + .SI(registers_30__ap[21]) + ); + AOI221_X1_LVT i_1_0_1115( + .A(n_1_0_1062), .B1(n_1_0_1274), .B2(registers_1__ap[21]), .C1(registers_28__ap[21]), + .C2(n_1_0_1283), .ZN(n_1_0_1061) + ); + SDFF_X1_LVT \registers_reg[18][21] ( + .CK(n_0_48), .D(registers[21]), .Q(registers_18__ap[21]), .QN(), .SE(dftIn), + .SI(registers_1__ap[21]) + ); + SDFF_X1_LVT \registers_reg[26][21] ( + .CK(n_0_56), .D(registers[21]), .Q(registers_26__ap[21]), .QN(), .SE(dftIn), + .SI(registers_28__ap[21]) + ); + AOI22_X1_LVT i_1_0_1114( + .A1(registers_18__ap[21]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[21]), + .ZN(n_1_0_1060) + ); + SDFF_X1_LVT \registers_reg[24][21] ( + .CK(n_0_54), .D(registers[21]), .Q(registers_24__ap[21]), .QN(), .SE(dftIn), + .SI(registers_26__ap[21]) + ); + SDFF_X1_LVT \registers_reg[4][21] ( + .CK(n_0_34), .D(registers[21]), .Q(registers_4__ap[21]), .QN(), .SE(dftIn), + .SI(registers_5__ap[21]) + ); + AOI22_X1_LVT i_1_0_1113( + .A1(registers_24__ap[21]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[21]), + .ZN(n_1_0_1059) + ); + SDFF_X1_LVT \registers_reg[15][21] ( + .CK(n_0_45), .D(registers[21]), .Q(registers_15__ap[21]), .QN(), .SE(dftIn), + .SI(registers_13__ap[21]) + ); + SDFF_X1_LVT \registers_reg[16][21] ( + .CK(n_0_46), .D(registers[21]), .Q(registers_16__ap[21]), .QN(), .SE(dftIn), + .SI(registers_15__ap[21]) + ); + AOI22_X1_LVT i_1_0_1112( + .A1(registers_15__ap[21]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[21]), + .ZN(n_1_0_1058) + ); + NAND3_X1_LVT i_1_0_1111( + .A1(n_1_0_1060), .A2(n_1_0_1059), .A3(n_1_0_1058), .ZN(n_1_0_1057) + ); + SDFF_X1_LVT \registers_reg[19][21] ( + .CK(n_0_49), .D(registers[21]), .Q(registers_19__ap[21]), .QN(), .SE(dftIn), + .SI(registers_18__ap[21]) + ); + SDFF_X1_LVT \registers_reg[25][21] ( + .CK(n_0_55), .D(registers[21]), .Q(registers_25__ap[21]), .QN(), .SE(dftIn), + .SI(registers_24__ap[21]) + ); + AOI221_X1_LVT i_1_0_1110( + .A(n_1_0_1057), .B1(n_1_0_1295), .B2(registers_19__ap[21]), .C1(registers_25__ap[21]), + .C2(n_1_0_1269), .ZN(n_1_0_1056) + ); + SDFF_X1_LVT \registers_reg[7][21] ( + .CK(n_0_37), .D(registers[21]), .Q(registers_7__ap[21]), .QN(), .SE(dftIn), + .SI(registers_4__ap[21]) + ); + SDFF_X1_LVT \registers_reg[14][21] ( + .CK(n_0_44), .D(registers[21]), .Q(registers_14__ap[21]), .QN(), .SE(dftIn), + .SI(registers_16__ap[21]) + ); + AOI22_X1_LVT i_1_0_1109( + .A1(registers_7__ap[21]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[21]), + .ZN(n_1_0_1055) + ); + SDFF_X1_LVT \registers_reg[9][21] ( + .CK(n_0_39), .D(registers[21]), .Q(registers_9__ap[21]), .QN(), .SE(dftIn), + .SI(registers_7__ap[21]) + ); + SDFF_X1_LVT \registers_reg[29][21] ( + .CK(n_0_59), .D(registers[21]), .Q(registers_29__ap[21]), .QN(), .SE(dftIn), + .SI(registers_25__ap[21]) + ); + AOI22_X1_LVT i_1_0_1108( + .A1(registers_9__ap[21]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[21]), + .ZN(n_1_0_1054) + ); + SDFF_X1_LVT \registers_reg[23][21] ( + .CK(n_0_53), .D(registers[21]), .Q(registers_23__ap[21]), .QN(), .SE(dftIn), + .SI(registers_19__ap[21]) + ); + SDFF_X1_LVT \registers_reg[3][21] ( + .CK(n_0_33), .D(registers[21]), .Q(registers_3__ap[21]), .QN(), .SE(dftIn), + .SI(registers_9__ap[21]) + ); + AOI22_X1_LVT i_1_0_1107( + .A1(registers_23__ap[21]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[21]), + .ZN(n_1_0_1053) + ); + NAND3_X1_LVT i_1_0_1106( + .A1(n_1_0_1055), .A2(n_1_0_1054), .A3(n_1_0_1053), .ZN(n_1_0_1052) + ); + SDFF_X1_LVT \registers_reg[27][21] ( + .CK(n_0_57), .D(registers[21]), .Q(registers_27__ap[21]), .QN(), .SE(dftIn), + .SI(registers_29__ap[21]) + ); + SDFF_X1_LVT \registers_reg[31][21] ( + .CK(n_0_61), .D(registers[21]), .Q(registers_31__ap[21]), .QN(), .SE(dftIn), + .SI(registers_3__ap[21]) + ); + AOI221_X1_LVT i_1_0_1105( + .A(n_1_0_1052), .B1(n_1_0_1279), .B2(registers_27__ap[21]), .C1(registers_31__ap[21]), + .C2(n_1_0_1266), .ZN(n_1_0_1051) + ); + NAND4_X1_LVT i_1_0_1104( + .A1(n_1_0_1068), .A2(n_1_0_1061), .A3(n_1_0_1056), .A4(n_1_0_1051), .ZN(RRs1[21]) + ); + AND2_X1_LVT i_0_0_20( + .A1(n_0_0_16), .A2(WRd[20]), .ZN(registers[20]) + ); + SDFF_X1_LVT \registers_reg[17][20] ( + .CK(n_0_47), .D(registers[20]), .Q(registers_17__ap[20]), .QN(), .SE(dftIn), + .SI(registers_23__ap[21]) + ); + SDFF_X1_LVT \registers_reg[21][20] ( + .CK(n_0_51), .D(registers[20]), .Q(registers_21__ap[20]), .QN(), .SE(dftIn), + .SI(registers_17__ap[20]) + ); + AOI22_X1_LVT i_1_0_1100( + .A1(registers_17__ap[20]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[20]), + .ZN(n_1_0_1047) + ); + SDFF_X1_LVT \registers_reg[10][20] ( + .CK(n_0_40), .D(registers[20]), .Q(registers_10__ap[20]), .QN(), .SE(dftIn), + .SI(registers_14__ap[21]) + ); + SDFF_X1_LVT \registers_reg[2][20] ( + .CK(n_0_32), .D(registers[20]), .Q(registers_2__ap[20]), .QN(), .SE(dftIn), + .SI(registers_27__ap[21]) + ); + AOI22_X1_LVT i_1_0_1103( + .A1(registers_10__ap[20]), .A2(n_1_0_1287), .B1(n_1_0_1268), .B2(registers_2__ap[20]), + .ZN(n_1_0_1050) + ); + SDFF_X1_LVT \registers_reg[20][20] ( + .CK(n_0_50), .D(registers[20]), .Q(registers_20__ap[20]), .QN(), .SE(dftIn), + .SI(registers_21__ap[20]) + ); + SDFF_X1_LVT \registers_reg[12][20] ( + .CK(n_0_42), .D(registers[20]), .Q(registers_12__ap[20]), .QN(), .SE(dftIn), + .SI(registers_10__ap[20]) + ); + AOI22_X1_LVT i_1_0_1099( + .A1(registers_20__ap[20]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[20]), + .ZN(n_1_0_1046) + ); + SDFF_X1_LVT \registers_reg[15][20] ( + .CK(n_0_45), .D(registers[20]), .Q(registers_15__ap[20]), .QN(), .SE(dftIn), + .SI(registers_12__ap[20]) + ); + SDFF_X1_LVT \registers_reg[8][20] ( + .CK(n_0_38), .D(registers[20]), .Q(registers_8__ap[20]), .QN(), .SE(dftIn), + .SI(registers_31__ap[21]) + ); + AOI22_X1_LVT i_1_0_1102( + .A1(registers_15__ap[20]), .A2(n_1_0_1286), .B1(n_1_0_1282), .B2(registers_8__ap[20]), + .ZN(n_1_0_1049) + ); + INV_X1_LVT i_1_0_1101( + .A(n_1_0_1049), .ZN(n_1_0_1048) + ); + SDFF_X1_LVT \registers_reg[11][20] ( + .CK(n_0_41), .D(registers[20]), .Q(registers_11__ap[20]), .QN(), .SE(dftIn), + .SI(registers_15__ap[20]) + ); + SDFF_X1_LVT \registers_reg[5][20] ( + .CK(n_0_35), .D(registers[20]), .Q(registers_5__ap[20]), .QN(), .SE(dftIn), + .SI(registers_8__ap[20]) + ); + AOI221_X1_LVT i_1_0_1098( + .A(n_1_0_1048), .B1(n_1_0_1270), .B2(registers_11__ap[20]), .C1(registers_5__ap[20]), + .C2(n_1_0_1273), .ZN(n_1_0_1045) + ); + SDFF_X1_LVT \registers_reg[13][20] ( + .CK(n_0_43), .D(registers[20]), .Q(registers_13__ap[20]), .QN(), .SE(dftIn), + .SI(registers_11__ap[20]) + ); + SDFF_X1_LVT \registers_reg[30][20] ( + .CK(n_0_60), .D(registers[20]), .Q(registers_30__ap[20]), .QN(), .SE(dftIn), + .SI(registers_2__ap[20]) + ); + SDFF_X1_LVT \registers_reg[22][20] ( + .CK(n_0_52), .D(registers[20]), .Q(registers_22__ap[20]), .QN(), .SE(dftIn), + .SI(registers_20__ap[20]) + ); + AOI222_X1_LVT i_1_0_1097( + .A1(registers_13__ap[20]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[20]), + .C1(registers_22__ap[20]), .C2(n_1_0_1294), .ZN(n_1_0_1044) + ); + NAND4_X1_LVT i_1_0_1096( + .A1(n_1_0_1050), .A2(n_1_0_1046), .A3(n_1_0_1045), .A4(n_1_0_1044), .ZN(n_1_0_1043) + ); + SDFF_X1_LVT \registers_reg[1][20] ( + .CK(n_0_0), .D(registers[20]), .Q(registers_1__ap[20]), .QN(), .SE(dftIn), + .SI(registers_22__ap[20]) + ); + SDFF_X1_LVT \registers_reg[28][20] ( + .CK(n_0_58), .D(registers[20]), .Q(registers_28__ap[20]), .QN(), .SE(dftIn), + .SI(registers_30__ap[20]) + ); + AOI221_X1_LVT i_1_0_1095( + .A(n_1_0_1043), .B1(n_1_0_1274), .B2(registers_1__ap[20]), .C1(registers_28__ap[20]), + .C2(n_1_0_1283), .ZN(n_1_0_1042) + ); + SDFF_X1_LVT \registers_reg[18][20] ( + .CK(n_0_48), .D(registers[20]), .Q(registers_18__ap[20]), .QN(), .SE(dftIn), + .SI(registers_1__ap[20]) + ); + SDFF_X1_LVT \registers_reg[26][20] ( + .CK(n_0_56), .D(registers[20]), .Q(registers_26__ap[20]), .QN(), .SE(dftIn), + .SI(registers_28__ap[20]) + ); + AOI22_X1_LVT i_1_0_1094( + .A1(registers_18__ap[20]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[20]), + .ZN(n_1_0_1041) + ); + SDFF_X1_LVT \registers_reg[24][20] ( + .CK(n_0_54), .D(registers[20]), .Q(registers_24__ap[20]), .QN(), .SE(dftIn), + .SI(registers_26__ap[20]) + ); + SDFF_X1_LVT \registers_reg[4][20] ( + .CK(n_0_34), .D(registers[20]), .Q(registers_4__ap[20]), .QN(), .SE(dftIn), + .SI(registers_5__ap[20]) + ); + AOI22_X1_LVT i_1_0_1093( + .A1(registers_24__ap[20]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[20]), + .ZN(n_1_0_1040) + ); + SDFF_X1_LVT \registers_reg[6][20] ( + .CK(n_0_36), .D(registers[20]), .Q(registers_6__ap[20]), .QN(), .SE(dftIn), + .SI(registers_4__ap[20]) + ); + SDFF_X1_LVT \registers_reg[25][20] ( + .CK(n_0_55), .D(registers[20]), .Q(registers_25__ap[20]), .QN(), .SE(dftIn), + .SI(registers_24__ap[20]) + ); + AOI22_X1_LVT i_1_0_1092( + .A1(registers_6__ap[20]), .A2(n_1_0_1300), .B1(n_1_0_1269), .B2(registers_25__ap[20]), + .ZN(n_1_0_1039) + ); + NAND3_X1_LVT i_1_0_1091( + .A1(n_1_0_1041), .A2(n_1_0_1040), .A3(n_1_0_1039), .ZN(n_1_0_1038) + ); + SDFF_X1_LVT \registers_reg[19][20] ( + .CK(n_0_49), .D(registers[20]), .Q(registers_19__ap[20]), .QN(), .SE(dftIn), + .SI(registers_18__ap[20]) + ); + SDFF_X1_LVT \registers_reg[16][20] ( + .CK(n_0_46), .D(registers[20]), .Q(registers_16__ap[20]), .QN(), .SE(dftIn), + .SI(registers_13__ap[20]) + ); + AOI221_X1_LVT i_1_0_1090( + .A(n_1_0_1038), .B1(n_1_0_1295), .B2(registers_19__ap[20]), .C1(registers_16__ap[20]), + .C2(n_1_0_1267), .ZN(n_1_0_1037) + ); + SDFF_X1_LVT \registers_reg[7][20] ( + .CK(n_0_37), .D(registers[20]), .Q(registers_7__ap[20]), .QN(), .SE(dftIn), + .SI(registers_6__ap[20]) + ); + SDFF_X1_LVT \registers_reg[14][20] ( + .CK(n_0_44), .D(registers[20]), .Q(registers_14__ap[20]), .QN(), .SE(dftIn), + .SI(registers_16__ap[20]) + ); + AOI22_X1_LVT i_1_0_1089( + .A1(registers_7__ap[20]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[20]), + .ZN(n_1_0_1036) + ); + SDFF_X1_LVT \registers_reg[9][20] ( + .CK(n_0_39), .D(registers[20]), .Q(registers_9__ap[20]), .QN(), .SE(dftIn), + .SI(registers_7__ap[20]) + ); + SDFF_X1_LVT \registers_reg[29][20] ( + .CK(n_0_59), .D(registers[20]), .Q(registers_29__ap[20]), .QN(), .SE(dftIn), + .SI(registers_25__ap[20]) + ); + AOI22_X1_LVT i_1_0_1088( + .A1(registers_9__ap[20]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[20]), + .ZN(n_1_0_1035) + ); + SDFF_X1_LVT \registers_reg[23][20] ( + .CK(n_0_53), .D(registers[20]), .Q(registers_23__ap[20]), .QN(), .SE(dftIn), + .SI(registers_19__ap[20]) + ); + SDFF_X1_LVT \registers_reg[3][20] ( + .CK(n_0_33), .D(registers[20]), .Q(registers_3__ap[20]), .QN(), .SE(dftIn), + .SI(registers_9__ap[20]) + ); + AOI22_X1_LVT i_1_0_1087( + .A1(registers_23__ap[20]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[20]), + .ZN(n_1_0_1034) + ); + NAND3_X1_LVT i_1_0_1086( + .A1(n_1_0_1036), .A2(n_1_0_1035), .A3(n_1_0_1034), .ZN(n_1_0_1033) + ); + SDFF_X1_LVT \registers_reg[27][20] ( + .CK(n_0_57), .D(registers[20]), .Q(registers_27__ap[20]), .QN(), .SE(dftIn), + .SI(registers_29__ap[20]) + ); + SDFF_X1_LVT \registers_reg[31][20] ( + .CK(n_0_61), .D(registers[20]), .Q(registers_31__ap[20]), .QN(), .SE(dftIn), + .SI(registers_3__ap[20]) + ); + AOI221_X1_LVT i_1_0_1085( + .A(n_1_0_1033), .B1(n_1_0_1279), .B2(registers_27__ap[20]), .C1(registers_31__ap[20]), + .C2(n_1_0_1266), .ZN(n_1_0_1032) + ); + NAND4_X1_LVT i_1_0_1084( + .A1(n_1_0_1047), .A2(n_1_0_1042), .A3(n_1_0_1037), .A4(n_1_0_1032), .ZN(RRs1[20]) + ); + AND2_X1_LVT i_0_0_19( + .A1(n_0_0_16), .A2(WRd[19]), .ZN(registers[19]) + ); + SDFF_X1_LVT \registers_reg[17][19] ( + .CK(n_0_47), .D(registers[19]), .Q(registers_17__ap[19]), .QN(), .SE(dftIn), + .SI(registers_23__ap[20]) + ); + SDFF_X1_LVT \registers_reg[21][19] ( + .CK(n_0_51), .D(registers[19]), .Q(registers_21__ap[19]), .QN(), .SE(dftIn), + .SI(registers_17__ap[19]) + ); + AOI22_X1_LVT i_1_0_1080( + .A1(registers_17__ap[19]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[19]), + .ZN(n_1_0_1028) + ); + SDFF_X1_LVT \registers_reg[2][19] ( + .CK(n_0_32), .D(registers[19]), .Q(registers_2__ap[19]), .QN(), .SE(dftIn), + .SI(registers_27__ap[20]) + ); + SDFF_X1_LVT \registers_reg[31][19] ( + .CK(n_0_61), .D(registers[19]), .Q(registers_31__ap[19]), .QN(), .SE(dftIn), + .SI(registers_31__ap[20]) + ); + AOI22_X1_LVT i_1_0_1083( + .A1(registers_2__ap[19]), .A2(n_1_0_1268), .B1(n_1_0_1266), .B2(registers_31__ap[19]), + .ZN(n_1_0_1031) + ); + SDFF_X1_LVT \registers_reg[20][19] ( + .CK(n_0_50), .D(registers[19]), .Q(registers_20__ap[19]), .QN(), .SE(dftIn), + .SI(registers_21__ap[19]) + ); + SDFF_X1_LVT \registers_reg[12][19] ( + .CK(n_0_42), .D(registers[19]), .Q(registers_12__ap[19]), .QN(), .SE(dftIn), + .SI(registers_14__ap[20]) + ); + AOI22_X1_LVT i_1_0_1079( + .A1(registers_20__ap[19]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[19]), + .ZN(n_1_0_1027) + ); + SDFF_X1_LVT \registers_reg[15][19] ( + .CK(n_0_45), .D(registers[19]), .Q(registers_15__ap[19]), .QN(), .SE(dftIn), + .SI(registers_12__ap[19]) + ); + SDFF_X1_LVT \registers_reg[11][19] ( + .CK(n_0_41), .D(registers[19]), .Q(registers_11__ap[19]), .QN(), .SE(dftIn), + .SI(registers_15__ap[19]) + ); + AOI22_X1_LVT i_1_0_1082( + .A1(registers_15__ap[19]), .A2(n_1_0_1286), .B1(n_1_0_1270), .B2(registers_11__ap[19]), + .ZN(n_1_0_1030) + ); + INV_X1_LVT i_1_0_1081( + .A(n_1_0_1030), .ZN(n_1_0_1029) + ); + SDFF_X1_LVT \registers_reg[27][19] ( + .CK(n_0_57), .D(registers[19]), .Q(registers_27__ap[19]), .QN(), .SE(dftIn), + .SI(registers_2__ap[19]) + ); + SDFF_X1_LVT \registers_reg[24][19] ( + .CK(n_0_54), .D(registers[19]), .Q(registers_24__ap[19]), .QN(), .SE(dftIn), + .SI(registers_27__ap[19]) + ); + AOI221_X1_LVT i_1_0_1078( + .A(n_1_0_1029), .B1(n_1_0_1279), .B2(registers_27__ap[19]), .C1(registers_24__ap[19]), + .C2(n_1_0_1289), .ZN(n_1_0_1026) + ); + SDFF_X1_LVT \registers_reg[22][19] ( + .CK(n_0_52), .D(registers[19]), .Q(registers_22__ap[19]), .QN(), .SE(dftIn), + .SI(registers_20__ap[19]) + ); + SDFF_X1_LVT \registers_reg[26][19] ( + .CK(n_0_56), .D(registers[19]), .Q(registers_26__ap[19]), .QN(), .SE(dftIn), + .SI(registers_24__ap[19]) + ); + SDFF_X1_LVT \registers_reg[13][19] ( + .CK(n_0_43), .D(registers[19]), .Q(registers_13__ap[19]), .QN(), .SE(dftIn), + .SI(registers_11__ap[19]) + ); + AOI222_X1_LVT i_1_0_1077( + .A1(registers_22__ap[19]), .A2(n_1_0_1294), .B1(n_1_0_1285), .B2(registers_26__ap[19]), + .C1(n_1_0_1277), .C2(registers_13__ap[19]), .ZN(n_1_0_1025) + ); + NAND4_X1_LVT i_1_0_1076( + .A1(n_1_0_1031), .A2(n_1_0_1027), .A3(n_1_0_1026), .A4(n_1_0_1025), .ZN(n_1_0_1024) + ); + SDFF_X1_LVT \registers_reg[1][19] ( + .CK(n_0_0), .D(registers[19]), .Q(registers_1__ap[19]), .QN(), .SE(dftIn), + .SI(registers_22__ap[19]) + ); + SDFF_X1_LVT \registers_reg[28][19] ( + .CK(n_0_58), .D(registers[19]), .Q(registers_28__ap[19]), .QN(), .SE(dftIn), + .SI(registers_26__ap[19]) + ); + AOI221_X1_LVT i_1_0_1075( + .A(n_1_0_1024), .B1(n_1_0_1274), .B2(registers_1__ap[19]), .C1(registers_28__ap[19]), + .C2(n_1_0_1283), .ZN(n_1_0_1023) + ); + SDFF_X1_LVT \registers_reg[18][19] ( + .CK(n_0_48), .D(registers[19]), .Q(registers_18__ap[19]), .QN(), .SE(dftIn), + .SI(registers_1__ap[19]) + ); + SDFF_X1_LVT \registers_reg[30][19] ( + .CK(n_0_60), .D(registers[19]), .Q(registers_30__ap[19]), .QN(), .SE(dftIn), + .SI(registers_28__ap[19]) + ); + AOI22_X1_LVT i_1_0_1074( + .A1(registers_18__ap[19]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[19]), + .ZN(n_1_0_1022) + ); + SDFF_X1_LVT \registers_reg[4][19] ( + .CK(n_0_34), .D(registers[19]), .Q(registers_4__ap[19]), .QN(), .SE(dftIn), + .SI(registers_31__ap[19]) + ); + SDFF_X1_LVT \registers_reg[5][19] ( + .CK(n_0_35), .D(registers[19]), .Q(registers_5__ap[19]), .QN(), .SE(dftIn), + .SI(registers_4__ap[19]) + ); + AOI22_X1_LVT i_1_0_1073( + .A1(registers_4__ap[19]), .A2(n_1_0_1278), .B1(n_1_0_1273), .B2(registers_5__ap[19]), + .ZN(n_1_0_1021) + ); + SDFF_X1_LVT \registers_reg[6][19] ( + .CK(n_0_36), .D(registers[19]), .Q(registers_6__ap[19]), .QN(), .SE(dftIn), + .SI(registers_5__ap[19]) + ); + SDFF_X1_LVT \registers_reg[25][19] ( + .CK(n_0_55), .D(registers[19]), .Q(registers_25__ap[19]), .QN(), .SE(dftIn), + .SI(registers_30__ap[19]) + ); + AOI22_X1_LVT i_1_0_1072( + .A1(registers_6__ap[19]), .A2(n_1_0_1300), .B1(n_1_0_1269), .B2(registers_25__ap[19]), + .ZN(n_1_0_1020) + ); + NAND3_X1_LVT i_1_0_1071( + .A1(n_1_0_1022), .A2(n_1_0_1021), .A3(n_1_0_1020), .ZN(n_1_0_1019) + ); + SDFF_X1_LVT \registers_reg[19][19] ( + .CK(n_0_49), .D(registers[19]), .Q(registers_19__ap[19]), .QN(), .SE(dftIn), + .SI(registers_18__ap[19]) + ); + SDFF_X1_LVT \registers_reg[16][19] ( + .CK(n_0_46), .D(registers[19]), .Q(registers_16__ap[19]), .QN(), .SE(dftIn), + .SI(registers_13__ap[19]) + ); + AOI221_X1_LVT i_1_0_1070( + .A(n_1_0_1019), .B1(n_1_0_1295), .B2(registers_19__ap[19]), .C1(registers_16__ap[19]), + .C2(n_1_0_1267), .ZN(n_1_0_1018) + ); + SDFF_X1_LVT \registers_reg[9][19] ( + .CK(n_0_39), .D(registers[19]), .Q(registers_9__ap[19]), .QN(), .SE(dftIn), + .SI(registers_6__ap[19]) + ); + SDFF_X1_LVT \registers_reg[29][19] ( + .CK(n_0_59), .D(registers[19]), .Q(registers_29__ap[19]), .QN(), .SE(dftIn), + .SI(registers_25__ap[19]) + ); + AOI22_X1_LVT i_1_0_1069( + .A1(registers_9__ap[19]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[19]), + .ZN(n_1_0_1017) + ); + SDFF_X1_LVT \registers_reg[8][19] ( + .CK(n_0_38), .D(registers[19]), .Q(registers_8__ap[19]), .QN(), .SE(dftIn), + .SI(registers_9__ap[19]) + ); + SDFF_X1_LVT \registers_reg[23][19] ( + .CK(n_0_53), .D(registers[19]), .Q(registers_23__ap[19]), .QN(), .SE(dftIn), + .SI(registers_19__ap[19]) + ); + AOI22_X1_LVT i_1_0_1068( + .A1(registers_8__ap[19]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[19]), + .ZN(n_1_0_1016) + ); + SDFF_X1_LVT \registers_reg[7][19] ( + .CK(n_0_37), .D(registers[19]), .Q(registers_7__ap[19]), .QN(), .SE(dftIn), + .SI(registers_8__ap[19]) + ); + SDFF_X1_LVT \registers_reg[14][19] ( + .CK(n_0_44), .D(registers[19]), .Q(registers_14__ap[19]), .QN(), .SE(dftIn), + .SI(registers_16__ap[19]) + ); + AOI22_X1_LVT i_1_0_1067( + .A1(registers_7__ap[19]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[19]), + .ZN(n_1_0_1015) + ); + NAND3_X1_LVT i_1_0_1066( + .A1(n_1_0_1017), .A2(n_1_0_1016), .A3(n_1_0_1015), .ZN(n_1_0_1014) + ); + SDFF_X1_LVT \registers_reg[10][19] ( + .CK(n_0_40), .D(registers[19]), .Q(registers_10__ap[19]), .QN(), .SE(dftIn), + .SI(registers_14__ap[19]) + ); + SDFF_X1_LVT \registers_reg[3][19] ( + .CK(n_0_33), .D(registers[19]), .Q(registers_3__ap[19]), .QN(), .SE(dftIn), + .SI(registers_7__ap[19]) + ); + AOI221_X1_LVT i_1_0_1065( + .A(n_1_0_1014), .B1(n_1_0_1287), .B2(registers_10__ap[19]), .C1(registers_3__ap[19]), + .C2(n_1_0_1257), .ZN(n_1_0_1013) + ); + NAND4_X1_LVT i_1_0_1064( + .A1(n_1_0_1028), .A2(n_1_0_1023), .A3(n_1_0_1018), .A4(n_1_0_1013), .ZN(RRs1[19]) + ); + AND2_X1_LVT i_0_0_18( + .A1(n_0_0_16), .A2(WRd[18]), .ZN(registers[18]) + ); + SDFF_X1_LVT \registers_reg[24][18] ( + .CK(n_0_54), .D(registers[18]), .Q(registers_24__ap[18]), .QN(), .SE(dftIn), + .SI(registers_29__ap[19]) + ); + SDFF_X1_LVT \registers_reg[28][18] ( + .CK(n_0_58), .D(registers[18]), .Q(registers_28__ap[18]), .QN(), .SE(dftIn), + .SI(registers_24__ap[18]) + ); + AOI22_X1_LVT i_1_0_1062( + .A1(registers_24__ap[18]), .A2(n_1_0_1289), .B1(n_1_0_1283), .B2(registers_28__ap[18]), + .ZN(n_1_0_1011) + ); + SDFF_X1_LVT \registers_reg[11][18] ( + .CK(n_0_41), .D(registers[18]), .Q(registers_11__ap[18]), .QN(), .SE(dftIn), + .SI(registers_10__ap[19]) + ); + SDFF_X1_LVT \registers_reg[16][18] ( + .CK(n_0_46), .D(registers[18]), .Q(registers_16__ap[18]), .QN(), .SE(dftIn), + .SI(registers_11__ap[18]) + ); + AOI22_X1_LVT i_1_0_1063( + .A1(registers_11__ap[18]), .A2(n_1_0_1270), .B1(n_1_0_1267), .B2(registers_16__ap[18]), + .ZN(n_1_0_1012) + ); + SDFF_X1_LVT \registers_reg[9][18] ( + .CK(n_0_39), .D(registers[18]), .Q(registers_9__ap[18]), .QN(), .SE(dftIn), + .SI(registers_3__ap[19]) + ); + SDFF_X1_LVT \registers_reg[7][18] ( + .CK(n_0_37), .D(registers[18]), .Q(registers_7__ap[18]), .QN(), .SE(dftIn), + .SI(registers_9__ap[18]) + ); + AOI22_X1_LVT i_1_0_1061( + .A1(registers_9__ap[18]), .A2(n_1_0_1291), .B1(n_1_0_1263), .B2(registers_7__ap[18]), + .ZN(n_1_0_1010) + ); + SDFF_X1_LVT \registers_reg[27][18] ( + .CK(n_0_57), .D(registers[18]), .Q(registers_27__ap[18]), .QN(), .SE(dftIn), + .SI(registers_28__ap[18]) + ); + SDFF_X1_LVT \registers_reg[25][18] ( + .CK(n_0_55), .D(registers[18]), .Q(registers_25__ap[18]), .QN(), .SE(dftIn), + .SI(registers_27__ap[18]) + ); + AOI22_X1_LVT i_1_0_1060( + .A1(registers_27__ap[18]), .A2(n_1_0_1279), .B1(n_1_0_1269), .B2(registers_25__ap[18]), + .ZN(n_1_0_1009) + ); + NAND3_X1_LVT i_1_0_1059( + .A1(n_1_0_1012), .A2(n_1_0_1010), .A3(n_1_0_1009), .ZN(n_1_0_1008) + ); + SDFF_X1_LVT \registers_reg[31][18] ( + .CK(n_0_61), .D(registers[18]), .Q(registers_31__ap[18]), .QN(), .SE(dftIn), + .SI(registers_7__ap[18]) + ); + SDFF_X1_LVT \registers_reg[6][18] ( + .CK(n_0_36), .D(registers[18]), .Q(registers_6__ap[18]), .QN(), .SE(dftIn), + .SI(registers_31__ap[18]) + ); + AOI221_X1_LVT i_1_0_1058( + .A(n_1_0_1008), .B1(n_1_0_1266), .B2(registers_31__ap[18]), .C1(registers_6__ap[18]), + .C2(n_1_0_1300), .ZN(n_1_0_1007) + ); + SDFF_X1_LVT \registers_reg[22][18] ( + .CK(n_0_52), .D(registers[18]), .Q(registers_22__ap[18]), .QN(), .SE(dftIn), + .SI(registers_23__ap[19]) + ); + SDFF_X1_LVT \registers_reg[26][18] ( + .CK(n_0_56), .D(registers[18]), .Q(registers_26__ap[18]), .QN(), .SE(dftIn), + .SI(registers_25__ap[18]) + ); + SDFF_X1_LVT \registers_reg[1][18] ( + .CK(n_0_0), .D(registers[18]), .Q(registers_1__ap[18]), .QN(), .SE(dftIn), + .SI(registers_22__ap[18]) + ); + AOI222_X1_LVT i_1_0_1057( + .A1(registers_22__ap[18]), .A2(n_1_0_1294), .B1(n_1_0_1285), .B2(registers_26__ap[18]), + .C1(n_1_0_1274), .C2(registers_1__ap[18]), .ZN(n_1_0_1006) + ); + NAND2_X1_LVT i_1_0_1056( + .A1(n_1_0_1007), .A2(n_1_0_1006), .ZN(n_1_0_1005) + ); + SDFF_X1_LVT \registers_reg[29][18] ( + .CK(n_0_59), .D(registers[18]), .Q(registers_29__ap[18]), .QN(), .SE(dftIn), + .SI(registers_26__ap[18]) + ); + SDFF_X1_LVT \registers_reg[2][18] ( + .CK(n_0_32), .D(registers[18]), .Q(registers_2__ap[18]), .QN(), .SE(dftIn), + .SI(registers_29__ap[18]) + ); + AOI221_X1_LVT i_1_0_1055( + .A(n_1_0_1005), .B1(n_1_0_1276), .B2(registers_29__ap[18]), .C1(registers_2__ap[18]), + .C2(n_1_0_1268), .ZN(n_1_0_1004) + ); + SDFF_X1_LVT \registers_reg[18][18] ( + .CK(n_0_48), .D(registers[18]), .Q(registers_18__ap[18]), .QN(), .SE(dftIn), + .SI(registers_1__ap[18]) + ); + SDFF_X1_LVT \registers_reg[30][18] ( + .CK(n_0_60), .D(registers[18]), .Q(registers_30__ap[18]), .QN(), .SE(dftIn), + .SI(registers_2__ap[18]) + ); + AOI22_X1_LVT i_1_0_1054( + .A1(registers_18__ap[18]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[18]), + .ZN(n_1_0_1003) + ); + SDFF_X1_LVT \registers_reg[4][18] ( + .CK(n_0_34), .D(registers[18]), .Q(registers_4__ap[18]), .QN(), .SE(dftIn), + .SI(registers_6__ap[18]) + ); + SDFF_X1_LVT \registers_reg[12][18] ( + .CK(n_0_42), .D(registers[18]), .Q(registers_12__ap[18]), .QN(), .SE(dftIn), + .SI(registers_16__ap[18]) + ); + AOI22_X1_LVT i_1_0_1053( + .A1(registers_4__ap[18]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[18]), + .ZN(n_1_0_1002) + ); + SDFF_X1_LVT \registers_reg[19][18] ( + .CK(n_0_49), .D(registers[18]), .Q(registers_19__ap[18]), .QN(), .SE(dftIn), + .SI(registers_18__ap[18]) + ); + SDFF_X1_LVT \registers_reg[21][18] ( + .CK(n_0_51), .D(registers[18]), .Q(registers_21__ap[18]), .QN(), .SE(dftIn), + .SI(registers_19__ap[18]) + ); + AOI22_X1_LVT i_1_0_1052( + .A1(registers_19__ap[18]), .A2(n_1_0_1295), .B1(n_1_0_1259), .B2(registers_21__ap[18]), + .ZN(n_1_0_1001) + ); + NAND3_X1_LVT i_1_0_1051( + .A1(n_1_0_1003), .A2(n_1_0_1002), .A3(n_1_0_1001), .ZN(n_1_0_1000) + ); + SDFF_X1_LVT \registers_reg[5][18] ( + .CK(n_0_35), .D(registers[18]), .Q(registers_5__ap[18]), .QN(), .SE(dftIn), + .SI(registers_4__ap[18]) + ); + SDFF_X1_LVT \registers_reg[20][18] ( + .CK(n_0_50), .D(registers[18]), .Q(registers_20__ap[18]), .QN(), .SE(dftIn), + .SI(registers_21__ap[18]) + ); + AOI221_X1_LVT i_1_0_1050( + .A(n_1_0_1000), .B1(n_1_0_1273), .B2(registers_5__ap[18]), .C1(registers_20__ap[18]), + .C2(n_1_0_1281), .ZN(n_1_0_999) + ); + SDFF_X1_LVT \registers_reg[8][18] ( + .CK(n_0_38), .D(registers[18]), .Q(registers_8__ap[18]), .QN(), .SE(dftIn), + .SI(registers_5__ap[18]) + ); + SDFF_X1_LVT \registers_reg[23][18] ( + .CK(n_0_53), .D(registers[18]), .Q(registers_23__ap[18]), .QN(), .SE(dftIn), + .SI(registers_20__ap[18]) + ); + AOI22_X1_LVT i_1_0_1049( + .A1(registers_8__ap[18]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[18]), + .ZN(n_1_0_998) + ); + SDFF_X1_LVT \registers_reg[13][18] ( + .CK(n_0_43), .D(registers[18]), .Q(registers_13__ap[18]), .QN(), .SE(dftIn), + .SI(registers_12__ap[18]) + ); + SDFF_X1_LVT \registers_reg[17][18] ( + .CK(n_0_47), .D(registers[18]), .Q(registers_17__ap[18]), .QN(), .SE(dftIn), + .SI(registers_23__ap[18]) + ); + AOI22_X1_LVT i_1_0_1048( + .A1(registers_13__ap[18]), .A2(n_1_0_1277), .B1(n_1_0_1271), .B2(registers_17__ap[18]), + .ZN(n_1_0_997) + ); + SDFF_X1_LVT \registers_reg[15][18] ( + .CK(n_0_45), .D(registers[18]), .Q(registers_15__ap[18]), .QN(), .SE(dftIn), + .SI(registers_13__ap[18]) + ); + SDFF_X1_LVT \registers_reg[14][18] ( + .CK(n_0_44), .D(registers[18]), .Q(registers_14__ap[18]), .QN(), .SE(dftIn), + .SI(registers_15__ap[18]) + ); + AOI22_X1_LVT i_1_0_1047( + .A1(registers_15__ap[18]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[18]), + .ZN(n_1_0_996) + ); + NAND3_X1_LVT i_1_0_1046( + .A1(n_1_0_998), .A2(n_1_0_997), .A3(n_1_0_996), .ZN(n_1_0_995) + ); + SDFF_X1_LVT \registers_reg[10][18] ( + .CK(n_0_40), .D(registers[18]), .Q(registers_10__ap[18]), .QN(), .SE(dftIn), + .SI(registers_14__ap[18]) + ); + SDFF_X1_LVT \registers_reg[3][18] ( + .CK(n_0_33), .D(registers[18]), .Q(registers_3__ap[18]), .QN(), .SE(dftIn), + .SI(registers_8__ap[18]) + ); + AOI221_X1_LVT i_1_0_1045( + .A(n_1_0_995), .B1(n_1_0_1287), .B2(registers_10__ap[18]), .C1(registers_3__ap[18]), + .C2(n_1_0_1257), .ZN(n_1_0_994) + ); + NAND4_X1_LVT i_1_0_1044( + .A1(n_1_0_1011), .A2(n_1_0_1004), .A3(n_1_0_999), .A4(n_1_0_994), .ZN(RRs1[18]) + ); + AND2_X1_LVT i_0_0_17( + .A1(n_0_0_16), .A2(WRd[17]), .ZN(registers[17]) + ); + SDFF_X1_LVT \registers_reg[17][17] ( + .CK(n_0_47), .D(registers[17]), .Q(registers_17__ap[17]), .QN(), .SE(dftIn), + .SI(registers_17__ap[18]) + ); + SDFF_X1_LVT \registers_reg[21][17] ( + .CK(n_0_51), .D(registers[17]), .Q(registers_21__ap[17]), .QN(), .SE(dftIn), + .SI(registers_17__ap[17]) + ); + AOI22_X1_LVT i_1_0_1040( + .A1(registers_17__ap[17]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[17]), + .ZN(n_1_0_990) + ); + SDFF_X1_LVT \registers_reg[2][17] ( + .CK(n_0_32), .D(registers[17]), .Q(registers_2__ap[17]), .QN(), .SE(dftIn), + .SI(registers_30__ap[18]) + ); + SDFF_X1_LVT \registers_reg[31][17] ( + .CK(n_0_61), .D(registers[17]), .Q(registers_31__ap[17]), .QN(), .SE(dftIn), + .SI(registers_3__ap[18]) + ); + AOI22_X1_LVT i_1_0_1043( + .A1(registers_2__ap[17]), .A2(n_1_0_1268), .B1(n_1_0_1266), .B2(registers_31__ap[17]), + .ZN(n_1_0_993) + ); + SDFF_X1_LVT \registers_reg[20][17] ( + .CK(n_0_50), .D(registers[17]), .Q(registers_20__ap[17]), .QN(), .SE(dftIn), + .SI(registers_21__ap[17]) + ); + SDFF_X1_LVT \registers_reg[12][17] ( + .CK(n_0_42), .D(registers[17]), .Q(registers_12__ap[17]), .QN(), .SE(dftIn), + .SI(registers_10__ap[18]) + ); + AOI22_X1_LVT i_1_0_1039( + .A1(registers_20__ap[17]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[17]), + .ZN(n_1_0_989) + ); + SDFF_X1_LVT \registers_reg[15][17] ( + .CK(n_0_45), .D(registers[17]), .Q(registers_15__ap[17]), .QN(), .SE(dftIn), + .SI(registers_12__ap[17]) + ); + SDFF_X1_LVT \registers_reg[11][17] ( + .CK(n_0_41), .D(registers[17]), .Q(registers_11__ap[17]), .QN(), .SE(dftIn), + .SI(registers_15__ap[17]) + ); + AOI22_X1_LVT i_1_0_1042( + .A1(registers_15__ap[17]), .A2(n_1_0_1286), .B1(n_1_0_1270), .B2(registers_11__ap[17]), + .ZN(n_1_0_992) + ); + INV_X1_LVT i_1_0_1041( + .A(n_1_0_992), .ZN(n_1_0_991) + ); + SDFF_X1_LVT \registers_reg[10][17] ( + .CK(n_0_40), .D(registers[17]), .Q(registers_10__ap[17]), .QN(), .SE(dftIn), + .SI(registers_11__ap[17]) + ); + SDFF_X1_LVT \registers_reg[24][17] ( + .CK(n_0_54), .D(registers[17]), .Q(registers_24__ap[17]), .QN(), .SE(dftIn), + .SI(registers_2__ap[17]) + ); + AOI221_X1_LVT i_1_0_1038( + .A(n_1_0_991), .B1(n_1_0_1287), .B2(registers_10__ap[17]), .C1(registers_24__ap[17]), + .C2(n_1_0_1289), .ZN(n_1_0_988) + ); + SDFF_X1_LVT \registers_reg[22][17] ( + .CK(n_0_52), .D(registers[17]), .Q(registers_22__ap[17]), .QN(), .SE(dftIn), + .SI(registers_20__ap[17]) + ); + SDFF_X1_LVT \registers_reg[26][17] ( + .CK(n_0_56), .D(registers[17]), .Q(registers_26__ap[17]), .QN(), .SE(dftIn), + .SI(registers_24__ap[17]) + ); + SDFF_X1_LVT \registers_reg[13][17] ( + .CK(n_0_43), .D(registers[17]), .Q(registers_13__ap[17]), .QN(), .SE(dftIn), + .SI(registers_10__ap[17]) + ); + AOI222_X1_LVT i_1_0_1037( + .A1(registers_22__ap[17]), .A2(n_1_0_1294), .B1(n_1_0_1285), .B2(registers_26__ap[17]), + .C1(n_1_0_1277), .C2(registers_13__ap[17]), .ZN(n_1_0_987) + ); + NAND4_X1_LVT i_1_0_1036( + .A1(n_1_0_993), .A2(n_1_0_989), .A3(n_1_0_988), .A4(n_1_0_987), .ZN(n_1_0_986) + ); + SDFF_X1_LVT \registers_reg[1][17] ( + .CK(n_0_0), .D(registers[17]), .Q(registers_1__ap[17]), .QN(), .SE(dftIn), + .SI(registers_22__ap[17]) + ); + SDFF_X1_LVT \registers_reg[28][17] ( + .CK(n_0_58), .D(registers[17]), .Q(registers_28__ap[17]), .QN(), .SE(dftIn), + .SI(registers_26__ap[17]) + ); + AOI221_X1_LVT i_1_0_1035( + .A(n_1_0_986), .B1(n_1_0_1274), .B2(registers_1__ap[17]), .C1(registers_28__ap[17]), + .C2(n_1_0_1283), .ZN(n_1_0_985) + ); + SDFF_X1_LVT \registers_reg[18][17] ( + .CK(n_0_48), .D(registers[17]), .Q(registers_18__ap[17]), .QN(), .SE(dftIn), + .SI(registers_1__ap[17]) + ); + SDFF_X1_LVT \registers_reg[30][17] ( + .CK(n_0_60), .D(registers[17]), .Q(registers_30__ap[17]), .QN(), .SE(dftIn), + .SI(registers_28__ap[17]) + ); + AOI22_X1_LVT i_1_0_1034( + .A1(registers_18__ap[17]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[17]), + .ZN(n_1_0_984) + ); + SDFF_X1_LVT \registers_reg[4][17] ( + .CK(n_0_34), .D(registers[17]), .Q(registers_4__ap[17]), .QN(), .SE(dftIn), + .SI(registers_31__ap[17]) + ); + SDFF_X1_LVT \registers_reg[5][17] ( + .CK(n_0_35), .D(registers[17]), .Q(registers_5__ap[17]), .QN(), .SE(dftIn), + .SI(registers_4__ap[17]) + ); + AOI22_X1_LVT i_1_0_1033( + .A1(registers_4__ap[17]), .A2(n_1_0_1278), .B1(n_1_0_1273), .B2(registers_5__ap[17]), + .ZN(n_1_0_983) + ); + SDFF_X1_LVT \registers_reg[6][17] ( + .CK(n_0_36), .D(registers[17]), .Q(registers_6__ap[17]), .QN(), .SE(dftIn), + .SI(registers_5__ap[17]) + ); + SDFF_X1_LVT \registers_reg[25][17] ( + .CK(n_0_55), .D(registers[17]), .Q(registers_25__ap[17]), .QN(), .SE(dftIn), + .SI(registers_30__ap[17]) + ); + AOI22_X1_LVT i_1_0_1032( + .A1(registers_6__ap[17]), .A2(n_1_0_1300), .B1(n_1_0_1269), .B2(registers_25__ap[17]), + .ZN(n_1_0_982) + ); + NAND3_X1_LVT i_1_0_1031( + .A1(n_1_0_984), .A2(n_1_0_983), .A3(n_1_0_982), .ZN(n_1_0_981) + ); + SDFF_X1_LVT \registers_reg[19][17] ( + .CK(n_0_49), .D(registers[17]), .Q(registers_19__ap[17]), .QN(), .SE(dftIn), + .SI(registers_18__ap[17]) + ); + SDFF_X1_LVT \registers_reg[16][17] ( + .CK(n_0_46), .D(registers[17]), .Q(registers_16__ap[17]), .QN(), .SE(dftIn), + .SI(registers_13__ap[17]) + ); + AOI221_X1_LVT i_1_0_1030( + .A(n_1_0_981), .B1(n_1_0_1295), .B2(registers_19__ap[17]), .C1(registers_16__ap[17]), + .C2(n_1_0_1267), .ZN(n_1_0_980) + ); + SDFF_X1_LVT \registers_reg[7][17] ( + .CK(n_0_37), .D(registers[17]), .Q(registers_7__ap[17]), .QN(), .SE(dftIn), + .SI(registers_6__ap[17]) + ); + SDFF_X1_LVT \registers_reg[14][17] ( + .CK(n_0_44), .D(registers[17]), .Q(registers_14__ap[17]), .QN(), .SE(dftIn), + .SI(registers_16__ap[17]) + ); + AOI22_X1_LVT i_1_0_1029( + .A1(registers_7__ap[17]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[17]), + .ZN(n_1_0_979) + ); + SDFF_X1_LVT \registers_reg[9][17] ( + .CK(n_0_39), .D(registers[17]), .Q(registers_9__ap[17]), .QN(), .SE(dftIn), + .SI(registers_7__ap[17]) + ); + SDFF_X1_LVT \registers_reg[29][17] ( + .CK(n_0_59), .D(registers[17]), .Q(registers_29__ap[17]), .QN(), .SE(dftIn), + .SI(registers_25__ap[17]) + ); + AOI22_X1_LVT i_1_0_1028( + .A1(registers_9__ap[17]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[17]), + .ZN(n_1_0_978) + ); + SDFF_X1_LVT \registers_reg[8][17] ( + .CK(n_0_38), .D(registers[17]), .Q(registers_8__ap[17]), .QN(), .SE(dftIn), + .SI(registers_9__ap[17]) + ); + SDFF_X1_LVT \registers_reg[23][17] ( + .CK(n_0_53), .D(registers[17]), .Q(registers_23__ap[17]), .QN(), .SE(dftIn), + .SI(registers_19__ap[17]) + ); + AOI22_X1_LVT i_1_0_1027( + .A1(registers_8__ap[17]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[17]), + .ZN(n_1_0_977) + ); + NAND3_X1_LVT i_1_0_1026( + .A1(n_1_0_979), .A2(n_1_0_978), .A3(n_1_0_977), .ZN(n_1_0_976) + ); + SDFF_X1_LVT \registers_reg[27][17] ( + .CK(n_0_57), .D(registers[17]), .Q(registers_27__ap[17]), .QN(), .SE(dftIn), + .SI(registers_29__ap[17]) + ); + SDFF_X1_LVT \registers_reg[3][17] ( + .CK(n_0_33), .D(registers[17]), .Q(registers_3__ap[17]), .QN(), .SE(dftIn), + .SI(registers_8__ap[17]) + ); + AOI221_X1_LVT i_1_0_1025( + .A(n_1_0_976), .B1(n_1_0_1279), .B2(registers_27__ap[17]), .C1(registers_3__ap[17]), + .C2(n_1_0_1257), .ZN(n_1_0_975) + ); + NAND4_X1_LVT i_1_0_1024( + .A1(n_1_0_990), .A2(n_1_0_985), .A3(n_1_0_980), .A4(n_1_0_975), .ZN(RRs1[17]) + ); + AND2_X1_LVT i_0_0_16( + .A1(n_0_0_16), .A2(WRd[16]), .ZN(registers[16]) + ); + SDFF_X1_LVT \registers_reg[29][16] ( + .CK(n_0_59), .D(registers[16]), .Q(registers_29__ap[16]), .QN(), .SE(dftIn), + .SI(registers_27__ap[17]) + ); + SDFF_X1_LVT \registers_reg[2][16] ( + .CK(n_0_32), .D(registers[16]), .Q(registers_2__ap[16]), .QN(), .SE(dftIn), + .SI(registers_29__ap[16]) + ); + AOI22_X1_LVT i_1_0_1022( + .A1(registers_29__ap[16]), .A2(n_1_0_1276), .B1(n_1_0_1268), .B2(registers_2__ap[16]), + .ZN(n_1_0_973) + ); + SDFF_X1_LVT \registers_reg[11][16] ( + .CK(n_0_41), .D(registers[16]), .Q(registers_11__ap[16]), .QN(), .SE(dftIn), + .SI(registers_14__ap[17]) + ); + SDFF_X1_LVT \registers_reg[25][16] ( + .CK(n_0_55), .D(registers[16]), .Q(registers_25__ap[16]), .QN(), .SE(dftIn), + .SI(registers_2__ap[16]) + ); + AOI22_X1_LVT i_1_0_1023( + .A1(registers_11__ap[16]), .A2(n_1_0_1270), .B1(n_1_0_1269), .B2(registers_25__ap[16]), + .ZN(n_1_0_974) + ); + SDFF_X1_LVT \registers_reg[9][16] ( + .CK(n_0_39), .D(registers[16]), .Q(registers_9__ap[16]), .QN(), .SE(dftIn), + .SI(registers_3__ap[17]) + ); + SDFF_X1_LVT \registers_reg[7][16] ( + .CK(n_0_37), .D(registers[16]), .Q(registers_7__ap[16]), .QN(), .SE(dftIn), + .SI(registers_9__ap[16]) + ); + AOI22_X1_LVT i_1_0_1021( + .A1(registers_9__ap[16]), .A2(n_1_0_1291), .B1(n_1_0_1263), .B2(registers_7__ap[16]), + .ZN(n_1_0_972) + ); + SDFF_X1_LVT \registers_reg[10][16] ( + .CK(n_0_40), .D(registers[16]), .Q(registers_10__ap[16]), .QN(), .SE(dftIn), + .SI(registers_11__ap[16]) + ); + SDFF_X1_LVT \registers_reg[16][16] ( + .CK(n_0_46), .D(registers[16]), .Q(registers_16__ap[16]), .QN(), .SE(dftIn), + .SI(registers_10__ap[16]) + ); + AOI22_X1_LVT i_1_0_1020( + .A1(registers_10__ap[16]), .A2(n_1_0_1287), .B1(n_1_0_1267), .B2(registers_16__ap[16]), + .ZN(n_1_0_971) + ); + NAND3_X1_LVT i_1_0_1019( + .A1(n_1_0_974), .A2(n_1_0_972), .A3(n_1_0_971), .ZN(n_1_0_970) + ); + SDFF_X1_LVT \registers_reg[31][16] ( + .CK(n_0_61), .D(registers[16]), .Q(registers_31__ap[16]), .QN(), .SE(dftIn), + .SI(registers_7__ap[16]) + ); + SDFF_X1_LVT \registers_reg[6][16] ( + .CK(n_0_36), .D(registers[16]), .Q(registers_6__ap[16]), .QN(), .SE(dftIn), + .SI(registers_31__ap[16]) + ); + AOI221_X1_LVT i_1_0_1018( + .A(n_1_0_970), .B1(n_1_0_1266), .B2(registers_31__ap[16]), .C1(registers_6__ap[16]), + .C2(n_1_0_1300), .ZN(n_1_0_969) + ); + SDFF_X1_LVT \registers_reg[18][16] ( + .CK(n_0_48), .D(registers[16]), .Q(registers_18__ap[16]), .QN(), .SE(dftIn), + .SI(registers_23__ap[17]) + ); + SDFF_X1_LVT \registers_reg[22][16] ( + .CK(n_0_52), .D(registers[16]), .Q(registers_22__ap[16]), .QN(), .SE(dftIn), + .SI(registers_18__ap[16]) + ); + SDFF_X1_LVT \registers_reg[1][16] ( + .CK(n_0_0), .D(registers[16]), .Q(registers_1__ap[16]), .QN(), .SE(dftIn), + .SI(registers_22__ap[16]) + ); + AOI222_X1_LVT i_1_0_1017( + .A1(registers_18__ap[16]), .A2(n_1_0_1297), .B1(n_1_0_1294), .B2(registers_22__ap[16]), + .C1(registers_1__ap[16]), .C2(n_1_0_1274), .ZN(n_1_0_968) + ); + NAND3_X1_LVT i_1_0_1016( + .A1(n_1_0_973), .A2(n_1_0_969), .A3(n_1_0_968), .ZN(n_1_0_967) + ); + SDFF_X1_LVT \registers_reg[5][16] ( + .CK(n_0_35), .D(registers[16]), .Q(registers_5__ap[16]), .QN(), .SE(dftIn), + .SI(registers_6__ap[16]) + ); + SDFF_X1_LVT \registers_reg[28][16] ( + .CK(n_0_58), .D(registers[16]), .Q(registers_28__ap[16]), .QN(), .SE(dftIn), + .SI(registers_25__ap[16]) + ); + AOI221_X1_LVT i_1_0_1015( + .A(n_1_0_967), .B1(n_1_0_1273), .B2(registers_5__ap[16]), .C1(registers_28__ap[16]), + .C2(n_1_0_1283), .ZN(n_1_0_966) + ); + SDFF_X1_LVT \registers_reg[4][16] ( + .CK(n_0_34), .D(registers[16]), .Q(registers_4__ap[16]), .QN(), .SE(dftIn), + .SI(registers_5__ap[16]) + ); + SDFF_X1_LVT \registers_reg[12][16] ( + .CK(n_0_42), .D(registers[16]), .Q(registers_12__ap[16]), .QN(), .SE(dftIn), + .SI(registers_16__ap[16]) + ); + AOI22_X1_LVT i_1_0_1014( + .A1(registers_4__ap[16]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[16]), + .ZN(n_1_0_965) + ); + SDFF_X1_LVT \registers_reg[19][16] ( + .CK(n_0_49), .D(registers[16]), .Q(registers_19__ap[16]), .QN(), .SE(dftIn), + .SI(registers_1__ap[16]) + ); + SDFF_X1_LVT \registers_reg[21][16] ( + .CK(n_0_51), .D(registers[16]), .Q(registers_21__ap[16]), .QN(), .SE(dftIn), + .SI(registers_19__ap[16]) + ); + AOI22_X1_LVT i_1_0_1013( + .A1(registers_19__ap[16]), .A2(n_1_0_1295), .B1(n_1_0_1259), .B2(registers_21__ap[16]), + .ZN(n_1_0_964) + ); + SDFF_X1_LVT \registers_reg[24][16] ( + .CK(n_0_54), .D(registers[16]), .Q(registers_24__ap[16]), .QN(), .SE(dftIn), + .SI(registers_28__ap[16]) + ); + SDFF_X1_LVT \registers_reg[20][16] ( + .CK(n_0_50), .D(registers[16]), .Q(registers_20__ap[16]), .QN(), .SE(dftIn), + .SI(registers_21__ap[16]) + ); + AOI22_X1_LVT i_1_0_1012( + .A1(registers_24__ap[16]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[16]), + .ZN(n_1_0_963) + ); + NAND3_X1_LVT i_1_0_1011( + .A1(n_1_0_965), .A2(n_1_0_964), .A3(n_1_0_963), .ZN(n_1_0_962) + ); + SDFF_X1_LVT \registers_reg[26][16] ( + .CK(n_0_56), .D(registers[16]), .Q(registers_26__ap[16]), .QN(), .SE(dftIn), + .SI(registers_24__ap[16]) + ); + SDFF_X1_LVT \registers_reg[30][16] ( + .CK(n_0_60), .D(registers[16]), .Q(registers_30__ap[16]), .QN(), .SE(dftIn), + .SI(registers_26__ap[16]) + ); + AOI221_X1_LVT i_1_0_1010( + .A(n_1_0_962), .B1(n_1_0_1285), .B2(registers_26__ap[16]), .C1(registers_30__ap[16]), + .C2(n_1_0_1272), .ZN(n_1_0_961) + ); + SDFF_X1_LVT \registers_reg[8][16] ( + .CK(n_0_38), .D(registers[16]), .Q(registers_8__ap[16]), .QN(), .SE(dftIn), + .SI(registers_4__ap[16]) + ); + SDFF_X1_LVT \registers_reg[23][16] ( + .CK(n_0_53), .D(registers[16]), .Q(registers_23__ap[16]), .QN(), .SE(dftIn), + .SI(registers_20__ap[16]) + ); + AOI22_X1_LVT i_1_0_1009( + .A1(registers_8__ap[16]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[16]), + .ZN(n_1_0_960) + ); + SDFF_X1_LVT \registers_reg[13][16] ( + .CK(n_0_43), .D(registers[16]), .Q(registers_13__ap[16]), .QN(), .SE(dftIn), + .SI(registers_12__ap[16]) + ); + SDFF_X1_LVT \registers_reg[17][16] ( + .CK(n_0_47), .D(registers[16]), .Q(registers_17__ap[16]), .QN(), .SE(dftIn), + .SI(registers_23__ap[16]) + ); + AOI22_X1_LVT i_1_0_1008( + .A1(registers_13__ap[16]), .A2(n_1_0_1277), .B1(n_1_0_1271), .B2(registers_17__ap[16]), + .ZN(n_1_0_959) + ); + SDFF_X1_LVT \registers_reg[15][16] ( + .CK(n_0_45), .D(registers[16]), .Q(registers_15__ap[16]), .QN(), .SE(dftIn), + .SI(registers_13__ap[16]) + ); + SDFF_X1_LVT \registers_reg[14][16] ( + .CK(n_0_44), .D(registers[16]), .Q(registers_14__ap[16]), .QN(), .SE(dftIn), + .SI(registers_15__ap[16]) + ); + AOI22_X1_LVT i_1_0_1007( + .A1(registers_15__ap[16]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[16]), + .ZN(n_1_0_958) + ); + NAND3_X1_LVT i_1_0_1006( + .A1(n_1_0_960), .A2(n_1_0_959), .A3(n_1_0_958), .ZN(n_1_0_957) + ); + SDFF_X1_LVT \registers_reg[27][16] ( + .CK(n_0_57), .D(registers[16]), .Q(registers_27__ap[16]), .QN(), .SE(dftIn), + .SI(registers_30__ap[16]) + ); + SDFF_X1_LVT \registers_reg[3][16] ( + .CK(n_0_33), .D(registers[16]), .Q(registers_3__ap[16]), .QN(), .SE(dftIn), + .SI(registers_8__ap[16]) + ); + AOI221_X1_LVT i_1_0_1005( + .A(n_1_0_957), .B1(n_1_0_1279), .B2(registers_27__ap[16]), .C1(registers_3__ap[16]), + .C2(n_1_0_1257), .ZN(n_1_0_956) + ); + NAND3_X1_LVT i_1_0_1004( + .A1(n_1_0_966), .A2(n_1_0_961), .A3(n_1_0_956), .ZN(RRs1[16]) + ); + AND2_X1_LVT i_0_0_15( + .A1(n_0_0_16), .A2(WRd[15]), .ZN(registers[15]) + ); + SDFF_X1_LVT \registers_reg[17][15] ( + .CK(n_0_47), .D(registers[15]), .Q(registers_17__ap[15]), .QN(), .SE(dftIn), + .SI(registers_17__ap[16]) + ); + SDFF_X1_LVT \registers_reg[21][15] ( + .CK(n_0_51), .D(registers[15]), .Q(registers_21__ap[15]), .QN(), .SE(dftIn), + .SI(registers_17__ap[15]) + ); + AOI22_X1_LVT i_1_0_1000( + .A1(registers_17__ap[15]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[15]), + .ZN(n_1_0_952) + ); + SDFF_X1_LVT \registers_reg[10][15] ( + .CK(n_0_40), .D(registers[15]), .Q(registers_10__ap[15]), .QN(), .SE(dftIn), + .SI(registers_14__ap[16]) + ); + SDFF_X1_LVT \registers_reg[2][15] ( + .CK(n_0_32), .D(registers[15]), .Q(registers_2__ap[15]), .QN(), .SE(dftIn), + .SI(registers_27__ap[16]) + ); + AOI22_X1_LVT i_1_0_1003( + .A1(registers_10__ap[15]), .A2(n_1_0_1287), .B1(n_1_0_1268), .B2(registers_2__ap[15]), + .ZN(n_1_0_955) + ); + SDFF_X1_LVT \registers_reg[20][15] ( + .CK(n_0_50), .D(registers[15]), .Q(registers_20__ap[15]), .QN(), .SE(dftIn), + .SI(registers_21__ap[15]) + ); + SDFF_X1_LVT \registers_reg[12][15] ( + .CK(n_0_42), .D(registers[15]), .Q(registers_12__ap[15]), .QN(), .SE(dftIn), + .SI(registers_10__ap[15]) + ); + AOI22_X1_LVT i_1_0_999( + .A1(registers_20__ap[15]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[15]), + .ZN(n_1_0_951) + ); + SDFF_X1_LVT \registers_reg[15][15] ( + .CK(n_0_45), .D(registers[15]), .Q(registers_15__ap[15]), .QN(), .SE(dftIn), + .SI(registers_12__ap[15]) + ); + SDFF_X1_LVT \registers_reg[8][15] ( + .CK(n_0_38), .D(registers[15]), .Q(registers_8__ap[15]), .QN(), .SE(dftIn), + .SI(registers_3__ap[16]) + ); + AOI22_X1_LVT i_1_0_1002( + .A1(registers_15__ap[15]), .A2(n_1_0_1286), .B1(n_1_0_1282), .B2(registers_8__ap[15]), + .ZN(n_1_0_954) + ); + INV_X1_LVT i_1_0_1001( + .A(n_1_0_954), .ZN(n_1_0_953) + ); + SDFF_X1_LVT \registers_reg[11][15] ( + .CK(n_0_41), .D(registers[15]), .Q(registers_11__ap[15]), .QN(), .SE(dftIn), + .SI(registers_15__ap[15]) + ); + SDFF_X1_LVT \registers_reg[24][15] ( + .CK(n_0_54), .D(registers[15]), .Q(registers_24__ap[15]), .QN(), .SE(dftIn), + .SI(registers_2__ap[15]) + ); + AOI221_X1_LVT i_1_0_998( + .A(n_1_0_953), .B1(n_1_0_1270), .B2(registers_11__ap[15]), .C1(registers_24__ap[15]), + .C2(n_1_0_1289), .ZN(n_1_0_950) + ); + SDFF_X1_LVT \registers_reg[13][15] ( + .CK(n_0_43), .D(registers[15]), .Q(registers_13__ap[15]), .QN(), .SE(dftIn), + .SI(registers_11__ap[15]) + ); + SDFF_X1_LVT \registers_reg[30][15] ( + .CK(n_0_60), .D(registers[15]), .Q(registers_30__ap[15]), .QN(), .SE(dftIn), + .SI(registers_24__ap[15]) + ); + SDFF_X1_LVT \registers_reg[22][15] ( + .CK(n_0_52), .D(registers[15]), .Q(registers_22__ap[15]), .QN(), .SE(dftIn), + .SI(registers_20__ap[15]) + ); + AOI222_X1_LVT i_1_0_997( + .A1(registers_13__ap[15]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[15]), + .C1(registers_22__ap[15]), .C2(n_1_0_1294), .ZN(n_1_0_949) + ); + NAND4_X1_LVT i_1_0_996( + .A1(n_1_0_955), .A2(n_1_0_951), .A3(n_1_0_950), .A4(n_1_0_949), .ZN(n_1_0_948) + ); + SDFF_X1_LVT \registers_reg[1][15] ( + .CK(n_0_0), .D(registers[15]), .Q(registers_1__ap[15]), .QN(), .SE(dftIn), + .SI(registers_22__ap[15]) + ); + SDFF_X1_LVT \registers_reg[28][15] ( + .CK(n_0_58), .D(registers[15]), .Q(registers_28__ap[15]), .QN(), .SE(dftIn), + .SI(registers_30__ap[15]) + ); + AOI221_X1_LVT i_1_0_995( + .A(n_1_0_948), .B1(n_1_0_1274), .B2(registers_1__ap[15]), .C1(registers_28__ap[15]), + .C2(n_1_0_1283), .ZN(n_1_0_947) + ); + SDFF_X1_LVT \registers_reg[18][15] ( + .CK(n_0_48), .D(registers[15]), .Q(registers_18__ap[15]), .QN(), .SE(dftIn), + .SI(registers_1__ap[15]) + ); + SDFF_X1_LVT \registers_reg[26][15] ( + .CK(n_0_56), .D(registers[15]), .Q(registers_26__ap[15]), .QN(), .SE(dftIn), + .SI(registers_28__ap[15]) + ); + AOI22_X1_LVT i_1_0_994( + .A1(registers_18__ap[15]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[15]), + .ZN(n_1_0_946) + ); + SDFF_X1_LVT \registers_reg[4][15] ( + .CK(n_0_34), .D(registers[15]), .Q(registers_4__ap[15]), .QN(), .SE(dftIn), + .SI(registers_8__ap[15]) + ); + SDFF_X1_LVT \registers_reg[5][15] ( + .CK(n_0_35), .D(registers[15]), .Q(registers_5__ap[15]), .QN(), .SE(dftIn), + .SI(registers_4__ap[15]) + ); + AOI22_X1_LVT i_1_0_993( + .A1(registers_4__ap[15]), .A2(n_1_0_1278), .B1(n_1_0_1273), .B2(registers_5__ap[15]), + .ZN(n_1_0_945) + ); + SDFF_X1_LVT \registers_reg[6][15] ( + .CK(n_0_36), .D(registers[15]), .Q(registers_6__ap[15]), .QN(), .SE(dftIn), + .SI(registers_5__ap[15]) + ); + SDFF_X1_LVT \registers_reg[16][15] ( + .CK(n_0_46), .D(registers[15]), .Q(registers_16__ap[15]), .QN(), .SE(dftIn), + .SI(registers_13__ap[15]) + ); + AOI22_X1_LVT i_1_0_992( + .A1(registers_6__ap[15]), .A2(n_1_0_1300), .B1(n_1_0_1267), .B2(registers_16__ap[15]), + .ZN(n_1_0_944) + ); + NAND3_X1_LVT i_1_0_991( + .A1(n_1_0_946), .A2(n_1_0_945), .A3(n_1_0_944), .ZN(n_1_0_943) + ); + SDFF_X1_LVT \registers_reg[19][15] ( + .CK(n_0_49), .D(registers[15]), .Q(registers_19__ap[15]), .QN(), .SE(dftIn), + .SI(registers_18__ap[15]) + ); + SDFF_X1_LVT \registers_reg[25][15] ( + .CK(n_0_55), .D(registers[15]), .Q(registers_25__ap[15]), .QN(), .SE(dftIn), + .SI(registers_26__ap[15]) + ); + AOI221_X1_LVT i_1_0_990( + .A(n_1_0_943), .B1(n_1_0_1295), .B2(registers_19__ap[15]), .C1(registers_25__ap[15]), + .C2(n_1_0_1269), .ZN(n_1_0_942) + ); + SDFF_X1_LVT \registers_reg[7][15] ( + .CK(n_0_37), .D(registers[15]), .Q(registers_7__ap[15]), .QN(), .SE(dftIn), + .SI(registers_6__ap[15]) + ); + SDFF_X1_LVT \registers_reg[14][15] ( + .CK(n_0_44), .D(registers[15]), .Q(registers_14__ap[15]), .QN(), .SE(dftIn), + .SI(registers_16__ap[15]) + ); + AOI22_X1_LVT i_1_0_989( + .A1(registers_7__ap[15]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[15]), + .ZN(n_1_0_941) + ); + SDFF_X1_LVT \registers_reg[9][15] ( + .CK(n_0_39), .D(registers[15]), .Q(registers_9__ap[15]), .QN(), .SE(dftIn), + .SI(registers_7__ap[15]) + ); + SDFF_X1_LVT \registers_reg[29][15] ( + .CK(n_0_59), .D(registers[15]), .Q(registers_29__ap[15]), .QN(), .SE(dftIn), + .SI(registers_25__ap[15]) + ); + AOI22_X1_LVT i_1_0_988( + .A1(registers_9__ap[15]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[15]), + .ZN(n_1_0_940) + ); + SDFF_X1_LVT \registers_reg[23][15] ( + .CK(n_0_53), .D(registers[15]), .Q(registers_23__ap[15]), .QN(), .SE(dftIn), + .SI(registers_19__ap[15]) + ); + SDFF_X1_LVT \registers_reg[3][15] ( + .CK(n_0_33), .D(registers[15]), .Q(registers_3__ap[15]), .QN(), .SE(dftIn), + .SI(registers_9__ap[15]) + ); + AOI22_X1_LVT i_1_0_987( + .A1(registers_23__ap[15]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[15]), + .ZN(n_1_0_939) + ); + NAND3_X1_LVT i_1_0_986( + .A1(n_1_0_941), .A2(n_1_0_940), .A3(n_1_0_939), .ZN(n_1_0_938) + ); + SDFF_X1_LVT \registers_reg[27][15] ( + .CK(n_0_57), .D(registers[15]), .Q(registers_27__ap[15]), .QN(), .SE(dftIn), + .SI(registers_29__ap[15]) + ); + SDFF_X1_LVT \registers_reg[31][15] ( + .CK(n_0_61), .D(registers[15]), .Q(registers_31__ap[15]), .QN(), .SE(dftIn), + .SI(registers_3__ap[15]) + ); + AOI221_X1_LVT i_1_0_985( + .A(n_1_0_938), .B1(n_1_0_1279), .B2(registers_27__ap[15]), .C1(registers_31__ap[15]), + .C2(n_1_0_1266), .ZN(n_1_0_937) + ); + NAND4_X1_LVT i_1_0_984( + .A1(n_1_0_952), .A2(n_1_0_947), .A3(n_1_0_942), .A4(n_1_0_937), .ZN(RRs1[15]) + ); + AND2_X1_LVT i_0_0_14( + .A1(n_0_0_16), .A2(WRd[14]), .ZN(registers[14]) + ); + SDFF_X1_LVT \registers_reg[28][14] ( + .CK(n_0_58), .D(registers[14]), .Q(registers_28__ap[14]), .QN(), .SE(dftIn), + .SI(registers_27__ap[15]) + ); + SDFF_X1_LVT \registers_reg[5][14] ( + .CK(n_0_35), .D(registers[14]), .Q(registers_5__ap[14]), .QN(), .SE(dftIn), + .SI(registers_31__ap[15]) + ); + AOI22_X1_LVT i_1_0_983( + .A1(registers_28__ap[14]), .A2(n_1_0_1283), .B1(n_1_0_1273), .B2(registers_5__ap[14]), + .ZN(n_1_0_936) + ); + SDFF_X1_LVT \registers_reg[18][14] ( + .CK(n_0_48), .D(registers[14]), .Q(registers_18__ap[14]), .QN(), .SE(dftIn), + .SI(registers_23__ap[15]) + ); + SDFF_X1_LVT \registers_reg[10][14] ( + .CK(n_0_40), .D(registers[14]), .Q(registers_10__ap[14]), .QN(), .SE(dftIn), + .SI(registers_14__ap[15]) + ); + SDFF_X1_LVT \registers_reg[8][14] ( + .CK(n_0_38), .D(registers[14]), .Q(registers_8__ap[14]), .QN(), .SE(dftIn), + .SI(registers_5__ap[14]) + ); + AOI222_X1_LVT i_1_0_982( + .A1(registers_18__ap[14]), .A2(n_1_0_1297), .B1(n_1_0_1287), .B2(registers_10__ap[14]), + .C1(n_1_0_1282), .C2(registers_8__ap[14]), .ZN(n_1_0_935) + ); + SDFF_X1_LVT \registers_reg[9][14] ( + .CK(n_0_39), .D(registers[14]), .Q(registers_9__ap[14]), .QN(), .SE(dftIn), + .SI(registers_8__ap[14]) + ); + SDFF_X1_LVT \registers_reg[29][14] ( + .CK(n_0_59), .D(registers[14]), .Q(registers_29__ap[14]), .QN(), .SE(dftIn), + .SI(registers_28__ap[14]) + ); + AOI22_X1_LVT i_1_0_981( + .A1(registers_9__ap[14]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[14]), + .ZN(n_1_0_934) + ); + SDFF_X1_LVT \registers_reg[21][14] ( + .CK(n_0_51), .D(registers[14]), .Q(registers_21__ap[14]), .QN(), .SE(dftIn), + .SI(registers_18__ap[14]) + ); + SDFF_X1_LVT \registers_reg[14][14] ( + .CK(n_0_44), .D(registers[14]), .Q(registers_14__ap[14]), .QN(), .SE(dftIn), + .SI(registers_10__ap[14]) + ); + AOI22_X1_LVT i_1_0_980( + .A1(registers_21__ap[14]), .A2(n_1_0_1259), .B1(n_1_0_1258), .B2(registers_14__ap[14]), + .ZN(n_1_0_933) + ); + SDFF_X1_LVT \registers_reg[16][14] ( + .CK(n_0_46), .D(registers[14]), .Q(registers_16__ap[14]), .QN(), .SE(dftIn), + .SI(registers_14__ap[14]) + ); + SDFF_X1_LVT \registers_reg[3][14] ( + .CK(n_0_33), .D(registers[14]), .Q(registers_3__ap[14]), .QN(), .SE(dftIn), + .SI(registers_9__ap[14]) + ); + AOI22_X1_LVT i_1_0_979( + .A1(registers_16__ap[14]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[14]), + .ZN(n_1_0_932) + ); + SDFF_X1_LVT \registers_reg[17][14] ( + .CK(n_0_47), .D(registers[14]), .Q(registers_17__ap[14]), .QN(), .SE(dftIn), + .SI(registers_21__ap[14]) + ); + SDFF_X1_LVT \registers_reg[31][14] ( + .CK(n_0_61), .D(registers[14]), .Q(registers_31__ap[14]), .QN(), .SE(dftIn), + .SI(registers_3__ap[14]) + ); + AOI22_X1_LVT i_1_0_978( + .A1(registers_17__ap[14]), .A2(n_1_0_1271), .B1(n_1_0_1266), .B2(registers_31__ap[14]), + .ZN(n_1_0_931) + ); + SDFF_X1_LVT \registers_reg[15][14] ( + .CK(n_0_45), .D(registers[14]), .Q(registers_15__ap[14]), .QN(), .SE(dftIn), + .SI(registers_16__ap[14]) + ); + SDFF_X1_LVT \registers_reg[23][14] ( + .CK(n_0_53), .D(registers[14]), .Q(registers_23__ap[14]), .QN(), .SE(dftIn), + .SI(registers_17__ap[14]) + ); + AOI22_X1_LVT i_1_0_977( + .A1(registers_15__ap[14]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[14]), + .ZN(n_1_0_930) + ); + NAND4_X1_LVT i_1_0_976( + .A1(n_1_0_933), .A2(n_1_0_932), .A3(n_1_0_931), .A4(n_1_0_930), .ZN(n_1_0_929) + ); + SDFF_X1_LVT \registers_reg[26][14] ( + .CK(n_0_56), .D(registers[14]), .Q(registers_26__ap[14]), .QN(), .SE(dftIn), + .SI(registers_29__ap[14]) + ); + SDFF_X1_LVT \registers_reg[30][14] ( + .CK(n_0_60), .D(registers[14]), .Q(registers_30__ap[14]), .QN(), .SE(dftIn), + .SI(registers_26__ap[14]) + ); + AOI22_X1_LVT i_1_0_975( + .A1(registers_26__ap[14]), .A2(n_1_0_1285), .B1(n_1_0_1272), .B2(registers_30__ap[14]), + .ZN(n_1_0_928) + ); + SDFF_X1_LVT \registers_reg[20][14] ( + .CK(n_0_50), .D(registers[14]), .Q(registers_20__ap[14]), .QN(), .SE(dftIn), + .SI(registers_23__ap[14]) + ); + SDFF_X1_LVT \registers_reg[4][14] ( + .CK(n_0_34), .D(registers[14]), .Q(registers_4__ap[14]), .QN(), .SE(dftIn), + .SI(registers_31__ap[14]) + ); + AOI22_X1_LVT i_1_0_974( + .A1(registers_20__ap[14]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[14]), + .ZN(n_1_0_927) + ); + SDFF_X1_LVT \registers_reg[1][14] ( + .CK(n_0_0), .D(registers[14]), .Q(registers_1__ap[14]), .QN(), .SE(dftIn), + .SI(registers_20__ap[14]) + ); + SDFF_X1_LVT \registers_reg[2][14] ( + .CK(n_0_32), .D(registers[14]), .Q(registers_2__ap[14]), .QN(), .SE(dftIn), + .SI(registers_30__ap[14]) + ); + AOI22_X1_LVT i_1_0_973( + .A1(registers_1__ap[14]), .A2(n_1_0_1274), .B1(n_1_0_1268), .B2(registers_2__ap[14]), + .ZN(n_1_0_926) + ); + SDFF_X1_LVT \registers_reg[24][14] ( + .CK(n_0_54), .D(registers[14]), .Q(registers_24__ap[14]), .QN(), .SE(dftIn), + .SI(registers_2__ap[14]) + ); + SDFF_X1_LVT \registers_reg[12][14] ( + .CK(n_0_42), .D(registers[14]), .Q(registers_12__ap[14]), .QN(), .SE(dftIn), + .SI(registers_15__ap[14]) + ); + AOI22_X1_LVT i_1_0_972( + .A1(registers_24__ap[14]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[14]), + .ZN(n_1_0_925) + ); + NAND4_X1_LVT i_1_0_971( + .A1(n_1_0_928), .A2(n_1_0_927), .A3(n_1_0_926), .A4(n_1_0_925), .ZN(n_1_0_924) + ); + SDFF_X1_LVT \registers_reg[19][14] ( + .CK(n_0_49), .D(registers[14]), .Q(registers_19__ap[14]), .QN(), .SE(dftIn), + .SI(registers_1__ap[14]) + ); + SDFF_X1_LVT \registers_reg[22][14] ( + .CK(n_0_52), .D(registers[14]), .Q(registers_22__ap[14]), .QN(), .SE(dftIn), + .SI(registers_19__ap[14]) + ); + AOI22_X1_LVT i_1_0_970( + .A1(registers_19__ap[14]), .A2(n_1_0_1295), .B1(n_1_0_1294), .B2(registers_22__ap[14]), + .ZN(n_1_0_923) + ); + SDFF_X1_LVT \registers_reg[13][14] ( + .CK(n_0_43), .D(registers[14]), .Q(registers_13__ap[14]), .QN(), .SE(dftIn), + .SI(registers_12__ap[14]) + ); + SDFF_X1_LVT \registers_reg[25][14] ( + .CK(n_0_55), .D(registers[14]), .Q(registers_25__ap[14]), .QN(), .SE(dftIn), + .SI(registers_24__ap[14]) + ); + AOI22_X1_LVT i_1_0_969( + .A1(registers_13__ap[14]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[14]), + .ZN(n_1_0_922) + ); + SDFF_X1_LVT \registers_reg[6][14] ( + .CK(n_0_36), .D(registers[14]), .Q(registers_6__ap[14]), .QN(), .SE(dftIn), + .SI(registers_4__ap[14]) + ); + SDFF_X1_LVT \registers_reg[7][14] ( + .CK(n_0_37), .D(registers[14]), .Q(registers_7__ap[14]), .QN(), .SE(dftIn), + .SI(registers_6__ap[14]) + ); + AOI22_X1_LVT i_1_0_968( + .A1(registers_6__ap[14]), .A2(n_1_0_1300), .B1(n_1_0_1263), .B2(registers_7__ap[14]), + .ZN(n_1_0_921) + ); + SDFF_X1_LVT \registers_reg[27][14] ( + .CK(n_0_57), .D(registers[14]), .Q(registers_27__ap[14]), .QN(), .SE(dftIn), + .SI(registers_25__ap[14]) + ); + SDFF_X1_LVT \registers_reg[11][14] ( + .CK(n_0_41), .D(registers[14]), .Q(registers_11__ap[14]), .QN(), .SE(dftIn), + .SI(registers_13__ap[14]) + ); + AOI22_X1_LVT i_1_0_967( + .A1(registers_27__ap[14]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[14]), + .ZN(n_1_0_920) + ); + NAND4_X1_LVT i_1_0_966( + .A1(n_1_0_923), .A2(n_1_0_922), .A3(n_1_0_921), .A4(n_1_0_920), .ZN(n_1_0_919) + ); + NOR3_X1_LVT i_1_0_965( + .A1(n_1_0_929), .A2(n_1_0_924), .A3(n_1_0_919), .ZN(n_1_0_918) + ); + NAND4_X1_LVT i_1_0_964( + .A1(n_1_0_936), .A2(n_1_0_935), .A3(n_1_0_934), .A4(n_1_0_918), .ZN(RRs1[14]) + ); + AND2_X1_LVT i_0_0_13( + .A1(n_0_0_16), .A2(WRd[13]), .ZN(registers[13]) + ); + SDFF_X1_LVT \registers_reg[28][13] ( + .CK(n_0_58), .D(registers[13]), .Q(registers_28__ap[13]), .QN(), .SE(dftIn), + .SI(registers_27__ap[14]) + ); + SDFF_X1_LVT \registers_reg[4][13] ( + .CK(n_0_34), .D(registers[13]), .Q(registers_4__ap[13]), .QN(), .SE(dftIn), + .SI(registers_7__ap[14]) + ); + AOI22_X1_LVT i_1_0_963( + .A1(registers_28__ap[13]), .A2(n_1_0_1283), .B1(n_1_0_1278), .B2(registers_4__ap[13]), + .ZN(n_1_0_917) + ); + SDFF_X1_LVT \registers_reg[10][13] ( + .CK(n_0_40), .D(registers[13]), .Q(registers_10__ap[13]), .QN(), .SE(dftIn), + .SI(registers_11__ap[14]) + ); + SDFF_X1_LVT \registers_reg[26][13] ( + .CK(n_0_56), .D(registers[13]), .Q(registers_26__ap[13]), .QN(), .SE(dftIn), + .SI(registers_28__ap[13]) + ); + SDFF_X1_LVT \registers_reg[8][13] ( + .CK(n_0_38), .D(registers[13]), .Q(registers_8__ap[13]), .QN(), .SE(dftIn), + .SI(registers_4__ap[13]) + ); + AOI222_X1_LVT i_1_0_962( + .A1(registers_10__ap[13]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[13]), + .C1(registers_8__ap[13]), .C2(n_1_0_1282), .ZN(n_1_0_916) + ); + SDFF_X1_LVT \registers_reg[9][13] ( + .CK(n_0_39), .D(registers[13]), .Q(registers_9__ap[13]), .QN(), .SE(dftIn), + .SI(registers_8__ap[13]) + ); + SDFF_X1_LVT \registers_reg[29][13] ( + .CK(n_0_59), .D(registers[13]), .Q(registers_29__ap[13]), .QN(), .SE(dftIn), + .SI(registers_26__ap[13]) + ); + AOI22_X1_LVT i_1_0_961( + .A1(registers_9__ap[13]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[13]), + .ZN(n_1_0_915) + ); + SDFF_X1_LVT \registers_reg[6][13] ( + .CK(n_0_36), .D(registers[13]), .Q(registers_6__ap[13]), .QN(), .SE(dftIn), + .SI(registers_9__ap[13]) + ); + SDFF_X1_LVT \registers_reg[1][13] ( + .CK(n_0_0), .D(registers[13]), .Q(registers_1__ap[13]), .QN(), .SE(dftIn), + .SI(registers_22__ap[14]) + ); + AOI22_X1_LVT i_1_0_960( + .A1(registers_6__ap[13]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[13]), + .ZN(n_1_0_914) + ); + SDFF_X1_LVT \registers_reg[5][13] ( + .CK(n_0_35), .D(registers[13]), .Q(registers_5__ap[13]), .QN(), .SE(dftIn), + .SI(registers_6__ap[13]) + ); + SDFF_X1_LVT \registers_reg[3][13] ( + .CK(n_0_33), .D(registers[13]), .Q(registers_3__ap[13]), .QN(), .SE(dftIn), + .SI(registers_5__ap[13]) + ); + AOI22_X1_LVT i_1_0_959( + .A1(registers_5__ap[13]), .A2(n_1_0_1273), .B1(n_1_0_1257), .B2(registers_3__ap[13]), + .ZN(n_1_0_913) + ); + SDFF_X1_LVT \registers_reg[16][13] ( + .CK(n_0_46), .D(registers[13]), .Q(registers_16__ap[13]), .QN(), .SE(dftIn), + .SI(registers_10__ap[13]) + ); + SDFF_X1_LVT \registers_reg[31][13] ( + .CK(n_0_61), .D(registers[13]), .Q(registers_31__ap[13]), .QN(), .SE(dftIn), + .SI(registers_3__ap[13]) + ); + AOI22_X1_LVT i_1_0_958( + .A1(registers_16__ap[13]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[13]), + .ZN(n_1_0_912) + ); + SDFF_X1_LVT \registers_reg[15][13] ( + .CK(n_0_45), .D(registers[13]), .Q(registers_15__ap[13]), .QN(), .SE(dftIn), + .SI(registers_16__ap[13]) + ); + SDFF_X1_LVT \registers_reg[23][13] ( + .CK(n_0_53), .D(registers[13]), .Q(registers_23__ap[13]), .QN(), .SE(dftIn), + .SI(registers_1__ap[13]) + ); + AOI22_X1_LVT i_1_0_957( + .A1(registers_15__ap[13]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[13]), + .ZN(n_1_0_911) + ); + NAND4_X1_LVT i_1_0_956( + .A1(n_1_0_914), .A2(n_1_0_913), .A3(n_1_0_912), .A4(n_1_0_911), .ZN(n_1_0_910) + ); + SDFF_X1_LVT \registers_reg[18][13] ( + .CK(n_0_48), .D(registers[13]), .Q(registers_18__ap[13]), .QN(), .SE(dftIn), + .SI(registers_23__ap[13]) + ); + SDFF_X1_LVT \registers_reg[30][13] ( + .CK(n_0_60), .D(registers[13]), .Q(registers_30__ap[13]), .QN(), .SE(dftIn), + .SI(registers_29__ap[13]) + ); + AOI22_X1_LVT i_1_0_955( + .A1(registers_18__ap[13]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[13]), + .ZN(n_1_0_909) + ); + SDFF_X1_LVT \registers_reg[24][13] ( + .CK(n_0_54), .D(registers[13]), .Q(registers_24__ap[13]), .QN(), .SE(dftIn), + .SI(registers_30__ap[13]) + ); + SDFF_X1_LVT \registers_reg[12][13] ( + .CK(n_0_42), .D(registers[13]), .Q(registers_12__ap[13]), .QN(), .SE(dftIn), + .SI(registers_15__ap[13]) + ); + AOI22_X1_LVT i_1_0_954( + .A1(registers_24__ap[13]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[13]), + .ZN(n_1_0_908) + ); + SDFF_X1_LVT \registers_reg[22][13] ( + .CK(n_0_52), .D(registers[13]), .Q(registers_22__ap[13]), .QN(), .SE(dftIn), + .SI(registers_18__ap[13]) + ); + SDFF_X1_LVT \registers_reg[21][13] ( + .CK(n_0_51), .D(registers[13]), .Q(registers_21__ap[13]), .QN(), .SE(dftIn), + .SI(registers_22__ap[13]) + ); + AOI22_X1_LVT i_1_0_953( + .A1(registers_22__ap[13]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[13]), + .ZN(n_1_0_907) + ); + SDFF_X1_LVT \registers_reg[20][13] ( + .CK(n_0_50), .D(registers[13]), .Q(registers_20__ap[13]), .QN(), .SE(dftIn), + .SI(registers_21__ap[13]) + ); + SDFF_X1_LVT \registers_reg[17][13] ( + .CK(n_0_47), .D(registers[13]), .Q(registers_17__ap[13]), .QN(), .SE(dftIn), + .SI(registers_20__ap[13]) + ); + AOI22_X1_LVT i_1_0_952( + .A1(registers_20__ap[13]), .A2(n_1_0_1281), .B1(n_1_0_1271), .B2(registers_17__ap[13]), + .ZN(n_1_0_906) + ); + NAND4_X1_LVT i_1_0_951( + .A1(n_1_0_909), .A2(n_1_0_908), .A3(n_1_0_907), .A4(n_1_0_906), .ZN(n_1_0_905) + ); + SDFF_X1_LVT \registers_reg[13][13] ( + .CK(n_0_43), .D(registers[13]), .Q(registers_13__ap[13]), .QN(), .SE(dftIn), + .SI(registers_12__ap[13]) + ); + SDFF_X1_LVT \registers_reg[25][13] ( + .CK(n_0_55), .D(registers[13]), .Q(registers_25__ap[13]), .QN(), .SE(dftIn), + .SI(registers_24__ap[13]) + ); + AOI22_X1_LVT i_1_0_950( + .A1(registers_13__ap[13]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[13]), + .ZN(n_1_0_904) + ); + SDFF_X1_LVT \registers_reg[19][13] ( + .CK(n_0_49), .D(registers[13]), .Q(registers_19__ap[13]), .QN(), .SE(dftIn), + .SI(registers_17__ap[13]) + ); + SDFF_X1_LVT \registers_reg[2][13] ( + .CK(n_0_32), .D(registers[13]), .Q(registers_2__ap[13]), .QN(), .SE(dftIn), + .SI(registers_25__ap[13]) + ); + AOI22_X1_LVT i_1_0_949( + .A1(registers_19__ap[13]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[13]), + .ZN(n_1_0_903) + ); + SDFF_X1_LVT \registers_reg[7][13] ( + .CK(n_0_37), .D(registers[13]), .Q(registers_7__ap[13]), .QN(), .SE(dftIn), + .SI(registers_31__ap[13]) + ); + SDFF_X1_LVT \registers_reg[14][13] ( + .CK(n_0_44), .D(registers[13]), .Q(registers_14__ap[13]), .QN(), .SE(dftIn), + .SI(registers_13__ap[13]) + ); + AOI22_X1_LVT i_1_0_948( + .A1(registers_7__ap[13]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[13]), + .ZN(n_1_0_902) + ); + SDFF_X1_LVT \registers_reg[27][13] ( + .CK(n_0_57), .D(registers[13]), .Q(registers_27__ap[13]), .QN(), .SE(dftIn), + .SI(registers_2__ap[13]) + ); + SDFF_X1_LVT \registers_reg[11][13] ( + .CK(n_0_41), .D(registers[13]), .Q(registers_11__ap[13]), .QN(), .SE(dftIn), + .SI(registers_14__ap[13]) + ); + AOI22_X1_LVT i_1_0_947( + .A1(registers_27__ap[13]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[13]), + .ZN(n_1_0_901) + ); + NAND4_X1_LVT i_1_0_946( + .A1(n_1_0_904), .A2(n_1_0_903), .A3(n_1_0_902), .A4(n_1_0_901), .ZN(n_1_0_900) + ); + NOR3_X1_LVT i_1_0_945( + .A1(n_1_0_910), .A2(n_1_0_905), .A3(n_1_0_900), .ZN(n_1_0_899) + ); + NAND4_X1_LVT i_1_0_944( + .A1(n_1_0_917), .A2(n_1_0_916), .A3(n_1_0_915), .A4(n_1_0_899), .ZN(RRs1[13]) + ); + AND2_X1_LVT i_0_0_12( + .A1(n_0_0_16), .A2(WRd[12]), .ZN(registers[12]) + ); + SDFF_X1_LVT \registers_reg[28][12] ( + .CK(n_0_58), .D(registers[12]), .Q(registers_28__ap[12]), .QN(), .SE(dftIn), + .SI(registers_27__ap[13]) + ); + SDFF_X1_LVT \registers_reg[17][12] ( + .CK(n_0_47), .D(registers[12]), .Q(registers_17__ap[12]), .QN(), .SE(dftIn), + .SI(registers_19__ap[13]) + ); + AOI22_X1_LVT i_1_0_943( + .A1(registers_28__ap[12]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[12]), + .ZN(n_1_0_898) + ); + SDFF_X1_LVT \registers_reg[10][12] ( + .CK(n_0_40), .D(registers[12]), .Q(registers_10__ap[12]), .QN(), .SE(dftIn), + .SI(registers_11__ap[13]) + ); + SDFF_X1_LVT \registers_reg[26][12] ( + .CK(n_0_56), .D(registers[12]), .Q(registers_26__ap[12]), .QN(), .SE(dftIn), + .SI(registers_28__ap[12]) + ); + SDFF_X1_LVT \registers_reg[8][12] ( + .CK(n_0_38), .D(registers[12]), .Q(registers_8__ap[12]), .QN(), .SE(dftIn), + .SI(registers_7__ap[13]) + ); + AOI222_X1_LVT i_1_0_942( + .A1(registers_10__ap[12]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[12]), + .C1(registers_8__ap[12]), .C2(n_1_0_1282), .ZN(n_1_0_897) + ); + SDFF_X1_LVT \registers_reg[9][12] ( + .CK(n_0_39), .D(registers[12]), .Q(registers_9__ap[12]), .QN(), .SE(dftIn), + .SI(registers_8__ap[12]) + ); + SDFF_X1_LVT \registers_reg[29][12] ( + .CK(n_0_59), .D(registers[12]), .Q(registers_29__ap[12]), .QN(), .SE(dftIn), + .SI(registers_26__ap[12]) + ); + AOI22_X1_LVT i_1_0_941( + .A1(registers_9__ap[12]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[12]), + .ZN(n_1_0_896) + ); + SDFF_X1_LVT \registers_reg[6][12] ( + .CK(n_0_36), .D(registers[12]), .Q(registers_6__ap[12]), .QN(), .SE(dftIn), + .SI(registers_9__ap[12]) + ); + SDFF_X1_LVT \registers_reg[1][12] ( + .CK(n_0_0), .D(registers[12]), .Q(registers_1__ap[12]), .QN(), .SE(dftIn), + .SI(registers_17__ap[12]) + ); + AOI22_X1_LVT i_1_0_940( + .A1(registers_6__ap[12]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[12]), + .ZN(n_1_0_895) + ); + SDFF_X1_LVT \registers_reg[16][12] ( + .CK(n_0_46), .D(registers[12]), .Q(registers_16__ap[12]), .QN(), .SE(dftIn), + .SI(registers_10__ap[12]) + ); + SDFF_X1_LVT \registers_reg[3][12] ( + .CK(n_0_33), .D(registers[12]), .Q(registers_3__ap[12]), .QN(), .SE(dftIn), + .SI(registers_6__ap[12]) + ); + AOI22_X1_LVT i_1_0_939( + .A1(registers_16__ap[12]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[12]), + .ZN(n_1_0_894) + ); + SDFF_X1_LVT \registers_reg[5][12] ( + .CK(n_0_35), .D(registers[12]), .Q(registers_5__ap[12]), .QN(), .SE(dftIn), + .SI(registers_3__ap[12]) + ); + SDFF_X1_LVT \registers_reg[31][12] ( + .CK(n_0_61), .D(registers[12]), .Q(registers_31__ap[12]), .QN(), .SE(dftIn), + .SI(registers_5__ap[12]) + ); + AOI22_X1_LVT i_1_0_938( + .A1(registers_5__ap[12]), .A2(n_1_0_1273), .B1(n_1_0_1266), .B2(registers_31__ap[12]), + .ZN(n_1_0_893) + ); + SDFF_X1_LVT \registers_reg[15][12] ( + .CK(n_0_45), .D(registers[12]), .Q(registers_15__ap[12]), .QN(), .SE(dftIn), + .SI(registers_16__ap[12]) + ); + SDFF_X1_LVT \registers_reg[23][12] ( + .CK(n_0_53), .D(registers[12]), .Q(registers_23__ap[12]), .QN(), .SE(dftIn), + .SI(registers_1__ap[12]) + ); + AOI22_X1_LVT i_1_0_937( + .A1(registers_15__ap[12]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[12]), + .ZN(n_1_0_892) + ); + NAND4_X1_LVT i_1_0_936( + .A1(n_1_0_895), .A2(n_1_0_894), .A3(n_1_0_893), .A4(n_1_0_892), .ZN(n_1_0_891) + ); + SDFF_X1_LVT \registers_reg[18][12] ( + .CK(n_0_48), .D(registers[12]), .Q(registers_18__ap[12]), .QN(), .SE(dftIn), + .SI(registers_23__ap[12]) + ); + SDFF_X1_LVT \registers_reg[30][12] ( + .CK(n_0_60), .D(registers[12]), .Q(registers_30__ap[12]), .QN(), .SE(dftIn), + .SI(registers_29__ap[12]) + ); + AOI22_X1_LVT i_1_0_935( + .A1(registers_18__ap[12]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[12]), + .ZN(n_1_0_890) + ); + SDFF_X1_LVT \registers_reg[20][12] ( + .CK(n_0_50), .D(registers[12]), .Q(registers_20__ap[12]), .QN(), .SE(dftIn), + .SI(registers_18__ap[12]) + ); + SDFF_X1_LVT \registers_reg[4][12] ( + .CK(n_0_34), .D(registers[12]), .Q(registers_4__ap[12]), .QN(), .SE(dftIn), + .SI(registers_31__ap[12]) + ); + AOI22_X1_LVT i_1_0_934( + .A1(registers_20__ap[12]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[12]), + .ZN(n_1_0_889) + ); + SDFF_X1_LVT \registers_reg[22][12] ( + .CK(n_0_52), .D(registers[12]), .Q(registers_22__ap[12]), .QN(), .SE(dftIn), + .SI(registers_20__ap[12]) + ); + SDFF_X1_LVT \registers_reg[21][12] ( + .CK(n_0_51), .D(registers[12]), .Q(registers_21__ap[12]), .QN(), .SE(dftIn), + .SI(registers_22__ap[12]) + ); + AOI22_X1_LVT i_1_0_933( + .A1(registers_22__ap[12]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[12]), + .ZN(n_1_0_888) + ); + SDFF_X1_LVT \registers_reg[24][12] ( + .CK(n_0_54), .D(registers[12]), .Q(registers_24__ap[12]), .QN(), .SE(dftIn), + .SI(registers_30__ap[12]) + ); + SDFF_X1_LVT \registers_reg[12][12] ( + .CK(n_0_42), .D(registers[12]), .Q(registers_12__ap[12]), .QN(), .SE(dftIn), + .SI(registers_15__ap[12]) + ); + AOI22_X1_LVT i_1_0_932( + .A1(registers_24__ap[12]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[12]), + .ZN(n_1_0_887) + ); + NAND4_X1_LVT i_1_0_931( + .A1(n_1_0_890), .A2(n_1_0_889), .A3(n_1_0_888), .A4(n_1_0_887), .ZN(n_1_0_886) + ); + SDFF_X1_LVT \registers_reg[13][12] ( + .CK(n_0_43), .D(registers[12]), .Q(registers_13__ap[12]), .QN(), .SE(dftIn), + .SI(registers_12__ap[12]) + ); + SDFF_X1_LVT \registers_reg[25][12] ( + .CK(n_0_55), .D(registers[12]), .Q(registers_25__ap[12]), .QN(), .SE(dftIn), + .SI(registers_24__ap[12]) + ); + AOI22_X1_LVT i_1_0_930( + .A1(registers_13__ap[12]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[12]), + .ZN(n_1_0_885) + ); + SDFF_X1_LVT \registers_reg[19][12] ( + .CK(n_0_49), .D(registers[12]), .Q(registers_19__ap[12]), .QN(), .SE(dftIn), + .SI(registers_21__ap[12]) + ); + SDFF_X1_LVT \registers_reg[2][12] ( + .CK(n_0_32), .D(registers[12]), .Q(registers_2__ap[12]), .QN(), .SE(dftIn), + .SI(registers_25__ap[12]) + ); + AOI22_X1_LVT i_1_0_929( + .A1(registers_19__ap[12]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[12]), + .ZN(n_1_0_884) + ); + SDFF_X1_LVT \registers_reg[7][12] ( + .CK(n_0_37), .D(registers[12]), .Q(registers_7__ap[12]), .QN(), .SE(dftIn), + .SI(registers_4__ap[12]) + ); + SDFF_X1_LVT \registers_reg[14][12] ( + .CK(n_0_44), .D(registers[12]), .Q(registers_14__ap[12]), .QN(), .SE(dftIn), + .SI(registers_13__ap[12]) + ); + AOI22_X1_LVT i_1_0_928( + .A1(registers_7__ap[12]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[12]), + .ZN(n_1_0_883) + ); + SDFF_X1_LVT \registers_reg[27][12] ( + .CK(n_0_57), .D(registers[12]), .Q(registers_27__ap[12]), .QN(), .SE(dftIn), + .SI(registers_2__ap[12]) + ); + SDFF_X1_LVT \registers_reg[11][12] ( + .CK(n_0_41), .D(registers[12]), .Q(registers_11__ap[12]), .QN(), .SE(dftIn), + .SI(registers_14__ap[12]) + ); + AOI22_X1_LVT i_1_0_927( + .A1(registers_27__ap[12]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[12]), + .ZN(n_1_0_882) + ); + NAND4_X1_LVT i_1_0_926( + .A1(n_1_0_885), .A2(n_1_0_884), .A3(n_1_0_883), .A4(n_1_0_882), .ZN(n_1_0_881) + ); + NOR3_X1_LVT i_1_0_925( + .A1(n_1_0_891), .A2(n_1_0_886), .A3(n_1_0_881), .ZN(n_1_0_880) + ); + NAND4_X1_LVT i_1_0_924( + .A1(n_1_0_898), .A2(n_1_0_897), .A3(n_1_0_896), .A4(n_1_0_880), .ZN(RRs1[12]) + ); + AND2_X1_LVT i_0_0_11( + .A1(n_0_0_16), .A2(WRd[11]), .ZN(registers[11]) + ); + SDFF_X1_LVT \registers_reg[28][11] ( + .CK(n_0_58), .D(registers[11]), .Q(registers_28__ap[11]), .QN(), .SE(dftIn), + .SI(registers_27__ap[12]) + ); + SDFF_X1_LVT \registers_reg[17][11] ( + .CK(n_0_47), .D(registers[11]), .Q(registers_17__ap[11]), .QN(), .SE(dftIn), + .SI(registers_19__ap[12]) + ); + AOI22_X1_LVT i_1_0_923( + .A1(registers_28__ap[11]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[11]), + .ZN(n_1_0_879) + ); + SDFF_X1_LVT \registers_reg[10][11] ( + .CK(n_0_40), .D(registers[11]), .Q(registers_10__ap[11]), .QN(), .SE(dftIn), + .SI(registers_11__ap[12]) + ); + SDFF_X1_LVT \registers_reg[26][11] ( + .CK(n_0_56), .D(registers[11]), .Q(registers_26__ap[11]), .QN(), .SE(dftIn), + .SI(registers_28__ap[11]) + ); + SDFF_X1_LVT \registers_reg[8][11] ( + .CK(n_0_38), .D(registers[11]), .Q(registers_8__ap[11]), .QN(), .SE(dftIn), + .SI(registers_7__ap[12]) + ); + AOI222_X1_LVT i_1_0_922( + .A1(registers_10__ap[11]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[11]), + .C1(registers_8__ap[11]), .C2(n_1_0_1282), .ZN(n_1_0_878) + ); + SDFF_X1_LVT \registers_reg[9][11] ( + .CK(n_0_39), .D(registers[11]), .Q(registers_9__ap[11]), .QN(), .SE(dftIn), + .SI(registers_8__ap[11]) + ); + SDFF_X1_LVT \registers_reg[29][11] ( + .CK(n_0_59), .D(registers[11]), .Q(registers_29__ap[11]), .QN(), .SE(dftIn), + .SI(registers_26__ap[11]) + ); + AOI22_X1_LVT i_1_0_921( + .A1(registers_9__ap[11]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[11]), + .ZN(n_1_0_877) + ); + SDFF_X1_LVT \registers_reg[6][11] ( + .CK(n_0_36), .D(registers[11]), .Q(registers_6__ap[11]), .QN(), .SE(dftIn), + .SI(registers_9__ap[11]) + ); + SDFF_X1_LVT \registers_reg[1][11] ( + .CK(n_0_0), .D(registers[11]), .Q(registers_1__ap[11]), .QN(), .SE(dftIn), + .SI(registers_17__ap[11]) + ); + AOI22_X1_LVT i_1_0_920( + .A1(registers_6__ap[11]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[11]), + .ZN(n_1_0_876) + ); + SDFF_X1_LVT \registers_reg[5][11] ( + .CK(n_0_35), .D(registers[11]), .Q(registers_5__ap[11]), .QN(), .SE(dftIn), + .SI(registers_6__ap[11]) + ); + SDFF_X1_LVT \registers_reg[3][11] ( + .CK(n_0_33), .D(registers[11]), .Q(registers_3__ap[11]), .QN(), .SE(dftIn), + .SI(registers_5__ap[11]) + ); + AOI22_X1_LVT i_1_0_919( + .A1(registers_5__ap[11]), .A2(n_1_0_1273), .B1(n_1_0_1257), .B2(registers_3__ap[11]), + .ZN(n_1_0_875) + ); + SDFF_X1_LVT \registers_reg[16][11] ( + .CK(n_0_46), .D(registers[11]), .Q(registers_16__ap[11]), .QN(), .SE(dftIn), + .SI(registers_10__ap[11]) + ); + SDFF_X1_LVT \registers_reg[31][11] ( + .CK(n_0_61), .D(registers[11]), .Q(registers_31__ap[11]), .QN(), .SE(dftIn), + .SI(registers_3__ap[11]) + ); + AOI22_X1_LVT i_1_0_918( + .A1(registers_16__ap[11]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[11]), + .ZN(n_1_0_874) + ); + SDFF_X1_LVT \registers_reg[15][11] ( + .CK(n_0_45), .D(registers[11]), .Q(registers_15__ap[11]), .QN(), .SE(dftIn), + .SI(registers_16__ap[11]) + ); + SDFF_X1_LVT \registers_reg[23][11] ( + .CK(n_0_53), .D(registers[11]), .Q(registers_23__ap[11]), .QN(), .SE(dftIn), + .SI(registers_1__ap[11]) + ); + AOI22_X1_LVT i_1_0_917( + .A1(registers_15__ap[11]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[11]), + .ZN(n_1_0_873) + ); + NAND4_X1_LVT i_1_0_916( + .A1(n_1_0_876), .A2(n_1_0_875), .A3(n_1_0_874), .A4(n_1_0_873), .ZN(n_1_0_872) + ); + SDFF_X1_LVT \registers_reg[18][11] ( + .CK(n_0_48), .D(registers[11]), .Q(registers_18__ap[11]), .QN(), .SE(dftIn), + .SI(registers_23__ap[11]) + ); + SDFF_X1_LVT \registers_reg[30][11] ( + .CK(n_0_60), .D(registers[11]), .Q(registers_30__ap[11]), .QN(), .SE(dftIn), + .SI(registers_29__ap[11]) + ); + AOI22_X1_LVT i_1_0_915( + .A1(registers_18__ap[11]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[11]), + .ZN(n_1_0_871) + ); + SDFF_X1_LVT \registers_reg[20][11] ( + .CK(n_0_50), .D(registers[11]), .Q(registers_20__ap[11]), .QN(), .SE(dftIn), + .SI(registers_18__ap[11]) + ); + SDFF_X1_LVT \registers_reg[4][11] ( + .CK(n_0_34), .D(registers[11]), .Q(registers_4__ap[11]), .QN(), .SE(dftIn), + .SI(registers_31__ap[11]) + ); + AOI22_X1_LVT i_1_0_914( + .A1(registers_20__ap[11]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[11]), + .ZN(n_1_0_870) + ); + SDFF_X1_LVT \registers_reg[22][11] ( + .CK(n_0_52), .D(registers[11]), .Q(registers_22__ap[11]), .QN(), .SE(dftIn), + .SI(registers_20__ap[11]) + ); + SDFF_X1_LVT \registers_reg[21][11] ( + .CK(n_0_51), .D(registers[11]), .Q(registers_21__ap[11]), .QN(), .SE(dftIn), + .SI(registers_22__ap[11]) + ); + AOI22_X1_LVT i_1_0_913( + .A1(registers_22__ap[11]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[11]), + .ZN(n_1_0_869) + ); + SDFF_X1_LVT \registers_reg[24][11] ( + .CK(n_0_54), .D(registers[11]), .Q(registers_24__ap[11]), .QN(), .SE(dftIn), + .SI(registers_30__ap[11]) + ); + SDFF_X1_LVT \registers_reg[12][11] ( + .CK(n_0_42), .D(registers[11]), .Q(registers_12__ap[11]), .QN(), .SE(dftIn), + .SI(registers_15__ap[11]) + ); + AOI22_X1_LVT i_1_0_912( + .A1(registers_24__ap[11]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[11]), + .ZN(n_1_0_868) + ); + NAND4_X1_LVT i_1_0_911( + .A1(n_1_0_871), .A2(n_1_0_870), .A3(n_1_0_869), .A4(n_1_0_868), .ZN(n_1_0_867) + ); + SDFF_X1_LVT \registers_reg[13][11] ( + .CK(n_0_43), .D(registers[11]), .Q(registers_13__ap[11]), .QN(), .SE(dftIn), + .SI(registers_12__ap[11]) + ); + SDFF_X1_LVT \registers_reg[25][11] ( + .CK(n_0_55), .D(registers[11]), .Q(registers_25__ap[11]), .QN(), .SE(dftIn), + .SI(registers_24__ap[11]) + ); + AOI22_X1_LVT i_1_0_910( + .A1(registers_13__ap[11]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[11]), + .ZN(n_1_0_866) + ); + SDFF_X1_LVT \registers_reg[19][11] ( + .CK(n_0_49), .D(registers[11]), .Q(registers_19__ap[11]), .QN(), .SE(dftIn), + .SI(registers_21__ap[11]) + ); + SDFF_X1_LVT \registers_reg[2][11] ( + .CK(n_0_32), .D(registers[11]), .Q(registers_2__ap[11]), .QN(), .SE(dftIn), + .SI(registers_25__ap[11]) + ); + AOI22_X1_LVT i_1_0_909( + .A1(registers_19__ap[11]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[11]), + .ZN(n_1_0_865) + ); + SDFF_X1_LVT \registers_reg[7][11] ( + .CK(n_0_37), .D(registers[11]), .Q(registers_7__ap[11]), .QN(), .SE(dftIn), + .SI(registers_4__ap[11]) + ); + SDFF_X1_LVT \registers_reg[14][11] ( + .CK(n_0_44), .D(registers[11]), .Q(registers_14__ap[11]), .QN(), .SE(dftIn), + .SI(registers_13__ap[11]) + ); + AOI22_X1_LVT i_1_0_908( + .A1(registers_7__ap[11]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[11]), + .ZN(n_1_0_864) + ); + SDFF_X1_LVT \registers_reg[27][11] ( + .CK(n_0_57), .D(registers[11]), .Q(registers_27__ap[11]), .QN(), .SE(dftIn), + .SI(registers_2__ap[11]) + ); + SDFF_X1_LVT \registers_reg[11][11] ( + .CK(n_0_41), .D(registers[11]), .Q(registers_11__ap[11]), .QN(), .SE(dftIn), + .SI(registers_14__ap[11]) + ); + AOI22_X1_LVT i_1_0_907( + .A1(registers_27__ap[11]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[11]), + .ZN(n_1_0_863) + ); + NAND4_X1_LVT i_1_0_906( + .A1(n_1_0_866), .A2(n_1_0_865), .A3(n_1_0_864), .A4(n_1_0_863), .ZN(n_1_0_862) + ); + NOR3_X1_LVT i_1_0_905( + .A1(n_1_0_872), .A2(n_1_0_867), .A3(n_1_0_862), .ZN(n_1_0_861) + ); + NAND4_X1_LVT i_1_0_904( + .A1(n_1_0_879), .A2(n_1_0_878), .A3(n_1_0_877), .A4(n_1_0_861), .ZN(RRs1[11]) + ); + AND2_X1_LVT i_0_0_10( + .A1(n_0_0_16), .A2(WRd[10]), .ZN(registers[10]) + ); + SDFF_X1_LVT \registers_reg[28][10] ( + .CK(n_0_58), .D(registers[10]), .Q(registers_28__ap[10]), .QN(), .SE(dftIn), + .SI(registers_27__ap[11]) + ); + SDFF_X1_LVT \registers_reg[8][10] ( + .CK(n_0_38), .D(registers[10]), .Q(registers_8__ap[10]), .QN(), .SE(dftIn), + .SI(registers_7__ap[11]) + ); + AOI22_X1_LVT i_1_0_902( + .A1(registers_28__ap[10]), .A2(n_1_0_1283), .B1(n_1_0_1282), .B2(registers_8__ap[10]), + .ZN(n_1_0_859) + ); + SDFF_X1_LVT \registers_reg[31][10] ( + .CK(n_0_61), .D(registers[10]), .Q(registers_31__ap[10]), .QN(), .SE(dftIn), + .SI(registers_8__ap[10]) + ); + SDFF_X1_LVT \registers_reg[7][10] ( + .CK(n_0_37), .D(registers[10]), .Q(registers_7__ap[10]), .QN(), .SE(dftIn), + .SI(registers_31__ap[10]) + ); + AOI22_X1_LVT i_1_0_903( + .A1(registers_31__ap[10]), .A2(n_1_0_1266), .B1(n_1_0_1263), .B2(registers_7__ap[10]), + .ZN(n_1_0_860) + ); + SDFF_X1_LVT \registers_reg[24][10] ( + .CK(n_0_54), .D(registers[10]), .Q(registers_24__ap[10]), .QN(), .SE(dftIn), + .SI(registers_28__ap[10]) + ); + SDFF_X1_LVT \registers_reg[20][10] ( + .CK(n_0_50), .D(registers[10]), .Q(registers_20__ap[10]), .QN(), .SE(dftIn), + .SI(registers_19__ap[11]) + ); + AOI22_X1_LVT i_1_0_901( + .A1(registers_24__ap[10]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[10]), + .ZN(n_1_0_858) + ); + SDFF_X1_LVT \registers_reg[4][10] ( + .CK(n_0_34), .D(registers[10]), .Q(registers_4__ap[10]), .QN(), .SE(dftIn), + .SI(registers_7__ap[10]) + ); + SDFF_X1_LVT \registers_reg[23][10] ( + .CK(n_0_53), .D(registers[10]), .Q(registers_23__ap[10]), .QN(), .SE(dftIn), + .SI(registers_20__ap[10]) + ); + AOI22_X1_LVT i_1_0_900( + .A1(registers_4__ap[10]), .A2(n_1_0_1278), .B1(n_1_0_1264), .B2(registers_23__ap[10]), + .ZN(n_1_0_857) + ); + NAND3_X1_LVT i_1_0_899( + .A1(n_1_0_860), .A2(n_1_0_858), .A3(n_1_0_857), .ZN(n_1_0_856) + ); + SDFF_X1_LVT \registers_reg[27][10] ( + .CK(n_0_57), .D(registers[10]), .Q(registers_27__ap[10]), .QN(), .SE(dftIn), + .SI(registers_24__ap[10]) + ); + SDFF_X1_LVT \registers_reg[29][10] ( + .CK(n_0_59), .D(registers[10]), .Q(registers_29__ap[10]), .QN(), .SE(dftIn), + .SI(registers_27__ap[10]) + ); + AOI221_X1_LVT i_1_0_898( + .A(n_1_0_856), .B1(n_1_0_1279), .B2(registers_27__ap[10]), .C1(registers_29__ap[10]), + .C2(n_1_0_1276), .ZN(n_1_0_855) + ); + SDFF_X1_LVT \registers_reg[10][10] ( + .CK(n_0_40), .D(registers[10]), .Q(registers_10__ap[10]), .QN(), .SE(dftIn), + .SI(registers_11__ap[11]) + ); + SDFF_X1_LVT \registers_reg[30][10] ( + .CK(n_0_60), .D(registers[10]), .Q(registers_30__ap[10]), .QN(), .SE(dftIn), + .SI(registers_29__ap[10]) + ); + SDFF_X1_LVT \registers_reg[25][10] ( + .CK(n_0_55), .D(registers[10]), .Q(registers_25__ap[10]), .QN(), .SE(dftIn), + .SI(registers_30__ap[10]) + ); + AOI222_X1_LVT i_1_0_897( + .A1(registers_10__ap[10]), .A2(n_1_0_1287), .B1(n_1_0_1272), .B2(registers_30__ap[10]), + .C1(n_1_0_1269), .C2(registers_25__ap[10]), .ZN(n_1_0_854) + ); + NAND3_X1_LVT i_1_0_896( + .A1(n_1_0_859), .A2(n_1_0_855), .A3(n_1_0_854), .ZN(n_1_0_853) + ); + SDFF_X1_LVT \registers_reg[21][10] ( + .CK(n_0_51), .D(registers[10]), .Q(registers_21__ap[10]), .QN(), .SE(dftIn), + .SI(registers_23__ap[10]) + ); + SDFF_X1_LVT \registers_reg[13][10] ( + .CK(n_0_43), .D(registers[10]), .Q(registers_13__ap[10]), .QN(), .SE(dftIn), + .SI(registers_10__ap[10]) + ); + AOI221_X1_LVT i_1_0_895( + .A(n_1_0_853), .B1(n_1_0_1259), .B2(registers_21__ap[10]), .C1(registers_13__ap[10]), + .C2(n_1_0_1277), .ZN(n_1_0_852) + ); + SDFF_X1_LVT \registers_reg[18][10] ( + .CK(n_0_48), .D(registers[10]), .Q(registers_18__ap[10]), .QN(), .SE(dftIn), + .SI(registers_21__ap[10]) + ); + SDFF_X1_LVT \registers_reg[26][10] ( + .CK(n_0_56), .D(registers[10]), .Q(registers_26__ap[10]), .QN(), .SE(dftIn), + .SI(registers_25__ap[10]) + ); + AOI22_X1_LVT i_1_0_894( + .A1(registers_18__ap[10]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[10]), + .ZN(n_1_0_851) + ); + SDFF_X1_LVT \registers_reg[17][10] ( + .CK(n_0_47), .D(registers[10]), .Q(registers_17__ap[10]), .QN(), .SE(dftIn), + .SI(registers_18__ap[10]) + ); + SDFF_X1_LVT \registers_reg[12][10] ( + .CK(n_0_42), .D(registers[10]), .Q(registers_12__ap[10]), .QN(), .SE(dftIn), + .SI(registers_13__ap[10]) + ); + AOI22_X1_LVT i_1_0_893( + .A1(registers_17__ap[10]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[10]), + .ZN(n_1_0_850) + ); + SDFF_X1_LVT \registers_reg[15][10] ( + .CK(n_0_45), .D(registers[10]), .Q(registers_15__ap[10]), .QN(), .SE(dftIn), + .SI(registers_12__ap[10]) + ); + SDFF_X1_LVT \registers_reg[5][10] ( + .CK(n_0_35), .D(registers[10]), .Q(registers_5__ap[10]), .QN(), .SE(dftIn), + .SI(registers_4__ap[10]) + ); + AOI22_X1_LVT i_1_0_892( + .A1(registers_15__ap[10]), .A2(n_1_0_1286), .B1(n_1_0_1273), .B2(registers_5__ap[10]), + .ZN(n_1_0_849) + ); + NAND3_X1_LVT i_1_0_891( + .A1(n_1_0_851), .A2(n_1_0_850), .A3(n_1_0_849), .ZN(n_1_0_848) + ); + SDFF_X1_LVT \registers_reg[22][10] ( + .CK(n_0_52), .D(registers[10]), .Q(registers_22__ap[10]), .QN(), .SE(dftIn), + .SI(registers_17__ap[10]) + ); + SDFF_X1_LVT \registers_reg[16][10] ( + .CK(n_0_46), .D(registers[10]), .Q(registers_16__ap[10]), .QN(), .SE(dftIn), + .SI(registers_15__ap[10]) + ); + AOI221_X1_LVT i_1_0_890( + .A(n_1_0_848), .B1(n_1_0_1294), .B2(registers_22__ap[10]), .C1(registers_16__ap[10]), + .C2(n_1_0_1267), .ZN(n_1_0_847) + ); + SDFF_X1_LVT \registers_reg[9][10] ( + .CK(n_0_39), .D(registers[10]), .Q(registers_9__ap[10]), .QN(), .SE(dftIn), + .SI(registers_5__ap[10]) + ); + SDFF_X1_LVT \registers_reg[1][10] ( + .CK(n_0_0), .D(registers[10]), .Q(registers_1__ap[10]), .QN(), .SE(dftIn), + .SI(registers_22__ap[10]) + ); + AOI22_X1_LVT i_1_0_889( + .A1(registers_9__ap[10]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[10]), + .ZN(n_1_0_846) + ); + SDFF_X1_LVT \registers_reg[6][10] ( + .CK(n_0_36), .D(registers[10]), .Q(registers_6__ap[10]), .QN(), .SE(dftIn), + .SI(registers_9__ap[10]) + ); + SDFF_X1_LVT \registers_reg[14][10] ( + .CK(n_0_44), .D(registers[10]), .Q(registers_14__ap[10]), .QN(), .SE(dftIn), + .SI(registers_16__ap[10]) + ); + AOI22_X1_LVT i_1_0_888( + .A1(registers_6__ap[10]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[10]), + .ZN(n_1_0_845) + ); + SDFF_X1_LVT \registers_reg[19][10] ( + .CK(n_0_49), .D(registers[10]), .Q(registers_19__ap[10]), .QN(), .SE(dftIn), + .SI(registers_1__ap[10]) + ); + SDFF_X1_LVT \registers_reg[3][10] ( + .CK(n_0_33), .D(registers[10]), .Q(registers_3__ap[10]), .QN(), .SE(dftIn), + .SI(registers_6__ap[10]) + ); + AOI22_X1_LVT i_1_0_887( + .A1(registers_19__ap[10]), .A2(n_1_0_1295), .B1(n_1_0_1257), .B2(registers_3__ap[10]), + .ZN(n_1_0_844) + ); + NAND3_X1_LVT i_1_0_886( + .A1(n_1_0_846), .A2(n_1_0_845), .A3(n_1_0_844), .ZN(n_1_0_843) + ); + SDFF_X1_LVT \registers_reg[11][10] ( + .CK(n_0_41), .D(registers[10]), .Q(registers_11__ap[10]), .QN(), .SE(dftIn), + .SI(registers_14__ap[10]) + ); + SDFF_X1_LVT \registers_reg[2][10] ( + .CK(n_0_32), .D(registers[10]), .Q(registers_2__ap[10]), .QN(), .SE(dftIn), + .SI(registers_26__ap[10]) + ); + AOI221_X1_LVT i_1_0_885( + .A(n_1_0_843), .B1(n_1_0_1270), .B2(registers_11__ap[10]), .C1(registers_2__ap[10]), + .C2(n_1_0_1268), .ZN(n_1_0_842) + ); + NAND3_X1_LVT i_1_0_884( + .A1(n_1_0_852), .A2(n_1_0_847), .A3(n_1_0_842), .ZN(RRs1[10]) + ); + AND2_X1_LVT i_0_0_9( + .A1(n_0_0_16), .A2(WRd[9]), .ZN(registers[9]) + ); + SDFF_X1_LVT \registers_reg[13][9] ( + .CK(n_0_43), .D(registers[9]), .Q(registers_13__ap[9]), .QN(), .SE(dftIn), + .SI(registers_11__ap[10]) + ); + SDFF_X1_LVT \registers_reg[21][9] ( + .CK(n_0_51), .D(registers[9]), .Q(registers_21__ap[9]), .QN(), .SE(dftIn), + .SI(registers_19__ap[10]) + ); + AOI22_X1_LVT i_1_0_880( + .A1(registers_13__ap[9]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[9]), + .ZN(n_1_0_838) + ); + SDFF_X1_LVT \registers_reg[29][9] ( + .CK(n_0_59), .D(registers[9]), .Q(registers_29__ap[9]), .QN(), .SE(dftIn), + .SI(registers_2__ap[10]) + ); + SDFF_X1_LVT \registers_reg[23][9] ( + .CK(n_0_53), .D(registers[9]), .Q(registers_23__ap[9]), .QN(), .SE(dftIn), + .SI(registers_21__ap[9]) + ); + AOI22_X1_LVT i_1_0_883( + .A1(registers_29__ap[9]), .A2(n_1_0_1276), .B1(n_1_0_1264), .B2(registers_23__ap[9]), + .ZN(n_1_0_841) + ); + SDFF_X1_LVT \registers_reg[24][9] ( + .CK(n_0_54), .D(registers[9]), .Q(registers_24__ap[9]), .QN(), .SE(dftIn), + .SI(registers_29__ap[9]) + ); + SDFF_X1_LVT \registers_reg[20][9] ( + .CK(n_0_50), .D(registers[9]), .Q(registers_20__ap[9]), .QN(), .SE(dftIn), + .SI(registers_23__ap[9]) + ); + AOI22_X1_LVT i_1_0_879( + .A1(registers_24__ap[9]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[9]), + .ZN(n_1_0_837) + ); + SDFF_X1_LVT \registers_reg[7][9] ( + .CK(n_0_37), .D(registers[9]), .Q(registers_7__ap[9]), .QN(), .SE(dftIn), + .SI(registers_3__ap[10]) + ); + SDFF_X1_LVT \registers_reg[3][9] ( + .CK(n_0_33), .D(registers[9]), .Q(registers_3__ap[9]), .QN(), .SE(dftIn), + .SI(registers_7__ap[9]) + ); + AOI22_X1_LVT i_1_0_882( + .A1(registers_7__ap[9]), .A2(n_1_0_1263), .B1(n_1_0_1257), .B2(registers_3__ap[9]), + .ZN(n_1_0_840) + ); + INV_X1_LVT i_1_0_881( + .A(n_1_0_840), .ZN(n_1_0_839) + ); + SDFF_X1_LVT \registers_reg[31][9] ( + .CK(n_0_61), .D(registers[9]), .Q(registers_31__ap[9]), .QN(), .SE(dftIn), + .SI(registers_3__ap[9]) + ); + SDFF_X1_LVT \registers_reg[4][9] ( + .CK(n_0_34), .D(registers[9]), .Q(registers_4__ap[9]), .QN(), .SE(dftIn), + .SI(registers_31__ap[9]) + ); + AOI221_X1_LVT i_1_0_878( + .A(n_1_0_839), .B1(n_1_0_1266), .B2(registers_31__ap[9]), .C1(registers_4__ap[9]), + .C2(n_1_0_1278), .ZN(n_1_0_836) + ); + SDFF_X1_LVT \registers_reg[10][9] ( + .CK(n_0_40), .D(registers[9]), .Q(registers_10__ap[9]), .QN(), .SE(dftIn), + .SI(registers_13__ap[9]) + ); + SDFF_X1_LVT \registers_reg[26][9] ( + .CK(n_0_56), .D(registers[9]), .Q(registers_26__ap[9]), .QN(), .SE(dftIn), + .SI(registers_24__ap[9]) + ); + SDFF_X1_LVT \registers_reg[25][9] ( + .CK(n_0_55), .D(registers[9]), .Q(registers_25__ap[9]), .QN(), .SE(dftIn), + .SI(registers_26__ap[9]) + ); + AOI222_X1_LVT i_1_0_877( + .A1(registers_10__ap[9]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[9]), + .C1(registers_25__ap[9]), .C2(n_1_0_1269), .ZN(n_1_0_835) + ); + NAND4_X1_LVT i_1_0_876( + .A1(n_1_0_841), .A2(n_1_0_837), .A3(n_1_0_836), .A4(n_1_0_835), .ZN(n_1_0_834) + ); + SDFF_X1_LVT \registers_reg[8][9] ( + .CK(n_0_38), .D(registers[9]), .Q(registers_8__ap[9]), .QN(), .SE(dftIn), + .SI(registers_4__ap[9]) + ); + SDFF_X1_LVT \registers_reg[28][9] ( + .CK(n_0_58), .D(registers[9]), .Q(registers_28__ap[9]), .QN(), .SE(dftIn), + .SI(registers_25__ap[9]) + ); + AOI221_X1_LVT i_1_0_875( + .A(n_1_0_834), .B1(n_1_0_1282), .B2(registers_8__ap[9]), .C1(registers_28__ap[9]), + .C2(n_1_0_1283), .ZN(n_1_0_833) + ); + SDFF_X1_LVT \registers_reg[18][9] ( + .CK(n_0_48), .D(registers[9]), .Q(registers_18__ap[9]), .QN(), .SE(dftIn), + .SI(registers_20__ap[9]) + ); + SDFF_X1_LVT \registers_reg[30][9] ( + .CK(n_0_60), .D(registers[9]), .Q(registers_30__ap[9]), .QN(), .SE(dftIn), + .SI(registers_28__ap[9]) + ); + AOI22_X1_LVT i_1_0_874( + .A1(registers_18__ap[9]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[9]), + .ZN(n_1_0_832) + ); + SDFF_X1_LVT \registers_reg[17][9] ( + .CK(n_0_47), .D(registers[9]), .Q(registers_17__ap[9]), .QN(), .SE(dftIn), + .SI(registers_18__ap[9]) + ); + SDFF_X1_LVT \registers_reg[12][9] ( + .CK(n_0_42), .D(registers[9]), .Q(registers_12__ap[9]), .QN(), .SE(dftIn), + .SI(registers_10__ap[9]) + ); + AOI22_X1_LVT i_1_0_873( + .A1(registers_17__ap[9]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[9]), + .ZN(n_1_0_831) + ); + SDFF_X1_LVT \registers_reg[15][9] ( + .CK(n_0_45), .D(registers[9]), .Q(registers_15__ap[9]), .QN(), .SE(dftIn), + .SI(registers_12__ap[9]) + ); + SDFF_X1_LVT \registers_reg[5][9] ( + .CK(n_0_35), .D(registers[9]), .Q(registers_5__ap[9]), .QN(), .SE(dftIn), + .SI(registers_8__ap[9]) + ); + AOI22_X1_LVT i_1_0_872( + .A1(registers_15__ap[9]), .A2(n_1_0_1286), .B1(n_1_0_1273), .B2(registers_5__ap[9]), + .ZN(n_1_0_830) + ); + NAND3_X1_LVT i_1_0_871( + .A1(n_1_0_832), .A2(n_1_0_831), .A3(n_1_0_830), .ZN(n_1_0_829) + ); + SDFF_X1_LVT \registers_reg[22][9] ( + .CK(n_0_52), .D(registers[9]), .Q(registers_22__ap[9]), .QN(), .SE(dftIn), + .SI(registers_17__ap[9]) + ); + SDFF_X1_LVT \registers_reg[16][9] ( + .CK(n_0_46), .D(registers[9]), .Q(registers_16__ap[9]), .QN(), .SE(dftIn), + .SI(registers_15__ap[9]) + ); + AOI221_X1_LVT i_1_0_870( + .A(n_1_0_829), .B1(n_1_0_1294), .B2(registers_22__ap[9]), .C1(registers_16__ap[9]), + .C2(n_1_0_1267), .ZN(n_1_0_828) + ); + SDFF_X1_LVT \registers_reg[9][9] ( + .CK(n_0_39), .D(registers[9]), .Q(registers_9__ap[9]), .QN(), .SE(dftIn), + .SI(registers_5__ap[9]) + ); + SDFF_X1_LVT \registers_reg[1][9] ( + .CK(n_0_0), .D(registers[9]), .Q(registers_1__ap[9]), .QN(), .SE(dftIn), + .SI(registers_22__ap[9]) + ); + AOI22_X1_LVT i_1_0_869( + .A1(registers_9__ap[9]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[9]), + .ZN(n_1_0_827) + ); + SDFF_X1_LVT \registers_reg[6][9] ( + .CK(n_0_36), .D(registers[9]), .Q(registers_6__ap[9]), .QN(), .SE(dftIn), + .SI(registers_9__ap[9]) + ); + SDFF_X1_LVT \registers_reg[14][9] ( + .CK(n_0_44), .D(registers[9]), .Q(registers_14__ap[9]), .QN(), .SE(dftIn), + .SI(registers_16__ap[9]) + ); + AOI22_X1_LVT i_1_0_868( + .A1(registers_6__ap[9]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[9]), + .ZN(n_1_0_826) + ); + SDFF_X1_LVT \registers_reg[19][9] ( + .CK(n_0_49), .D(registers[9]), .Q(registers_19__ap[9]), .QN(), .SE(dftIn), + .SI(registers_1__ap[9]) + ); + SDFF_X1_LVT \registers_reg[2][9] ( + .CK(n_0_32), .D(registers[9]), .Q(registers_2__ap[9]), .QN(), .SE(dftIn), + .SI(registers_30__ap[9]) + ); + AOI22_X1_LVT i_1_0_867( + .A1(registers_19__ap[9]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[9]), + .ZN(n_1_0_825) + ); + NAND3_X1_LVT i_1_0_866( + .A1(n_1_0_827), .A2(n_1_0_826), .A3(n_1_0_825), .ZN(n_1_0_824) + ); + SDFF_X1_LVT \registers_reg[11][9] ( + .CK(n_0_41), .D(registers[9]), .Q(registers_11__ap[9]), .QN(), .SE(dftIn), + .SI(registers_14__ap[9]) + ); + SDFF_X1_LVT \registers_reg[27][9] ( + .CK(n_0_57), .D(registers[9]), .Q(registers_27__ap[9]), .QN(), .SE(dftIn), + .SI(registers_2__ap[9]) + ); + AOI221_X1_LVT i_1_0_865( + .A(n_1_0_824), .B1(n_1_0_1270), .B2(registers_11__ap[9]), .C1(registers_27__ap[9]), + .C2(n_1_0_1279), .ZN(n_1_0_823) + ); + NAND4_X1_LVT i_1_0_864( + .A1(n_1_0_838), .A2(n_1_0_833), .A3(n_1_0_828), .A4(n_1_0_823), .ZN(RRs1[9]) + ); + AND2_X1_LVT i_0_0_8( + .A1(n_0_0_16), .A2(WRd[8]), .ZN(registers[8]) + ); + SDFF_X1_LVT \registers_reg[13][8] ( + .CK(n_0_43), .D(registers[8]), .Q(registers_13__ap[8]), .QN(), .SE(dftIn), + .SI(registers_11__ap[9]) + ); + SDFF_X1_LVT \registers_reg[21][8] ( + .CK(n_0_51), .D(registers[8]), .Q(registers_21__ap[8]), .QN(), .SE(dftIn), + .SI(registers_19__ap[9]) + ); + AOI22_X1_LVT i_1_0_860( + .A1(registers_13__ap[8]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[8]), + .ZN(n_1_0_819) + ); + SDFF_X1_LVT \registers_reg[29][8] ( + .CK(n_0_59), .D(registers[8]), .Q(registers_29__ap[8]), .QN(), .SE(dftIn), + .SI(registers_27__ap[9]) + ); + SDFF_X1_LVT \registers_reg[23][8] ( + .CK(n_0_53), .D(registers[8]), .Q(registers_23__ap[8]), .QN(), .SE(dftIn), + .SI(registers_21__ap[8]) + ); + AOI22_X1_LVT i_1_0_863( + .A1(registers_29__ap[8]), .A2(n_1_0_1276), .B1(n_1_0_1264), .B2(registers_23__ap[8]), + .ZN(n_1_0_822) + ); + SDFF_X1_LVT \registers_reg[24][8] ( + .CK(n_0_54), .D(registers[8]), .Q(registers_24__ap[8]), .QN(), .SE(dftIn), + .SI(registers_29__ap[8]) + ); + SDFF_X1_LVT \registers_reg[20][8] ( + .CK(n_0_50), .D(registers[8]), .Q(registers_20__ap[8]), .QN(), .SE(dftIn), + .SI(registers_23__ap[8]) + ); + AOI22_X1_LVT i_1_0_859( + .A1(registers_24__ap[8]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[8]), + .ZN(n_1_0_818) + ); + SDFF_X1_LVT \registers_reg[7][8] ( + .CK(n_0_37), .D(registers[8]), .Q(registers_7__ap[8]), .QN(), .SE(dftIn), + .SI(registers_6__ap[9]) + ); + SDFF_X1_LVT \registers_reg[3][8] ( + .CK(n_0_33), .D(registers[8]), .Q(registers_3__ap[8]), .QN(), .SE(dftIn), + .SI(registers_7__ap[8]) + ); + AOI22_X1_LVT i_1_0_862( + .A1(registers_7__ap[8]), .A2(n_1_0_1263), .B1(n_1_0_1257), .B2(registers_3__ap[8]), + .ZN(n_1_0_821) + ); + INV_X1_LVT i_1_0_861( + .A(n_1_0_821), .ZN(n_1_0_820) + ); + SDFF_X1_LVT \registers_reg[31][8] ( + .CK(n_0_61), .D(registers[8]), .Q(registers_31__ap[8]), .QN(), .SE(dftIn), + .SI(registers_3__ap[8]) + ); + SDFF_X1_LVT \registers_reg[4][8] ( + .CK(n_0_34), .D(registers[8]), .Q(registers_4__ap[8]), .QN(), .SE(dftIn), + .SI(registers_31__ap[8]) + ); + AOI221_X1_LVT i_1_0_858( + .A(n_1_0_820), .B1(n_1_0_1266), .B2(registers_31__ap[8]), .C1(registers_4__ap[8]), + .C2(n_1_0_1278), .ZN(n_1_0_817) + ); + SDFF_X1_LVT \registers_reg[10][8] ( + .CK(n_0_40), .D(registers[8]), .Q(registers_10__ap[8]), .QN(), .SE(dftIn), + .SI(registers_13__ap[8]) + ); + SDFF_X1_LVT \registers_reg[26][8] ( + .CK(n_0_56), .D(registers[8]), .Q(registers_26__ap[8]), .QN(), .SE(dftIn), + .SI(registers_24__ap[8]) + ); + SDFF_X1_LVT \registers_reg[25][8] ( + .CK(n_0_55), .D(registers[8]), .Q(registers_25__ap[8]), .QN(), .SE(dftIn), + .SI(registers_26__ap[8]) + ); + AOI222_X1_LVT i_1_0_857( + .A1(registers_10__ap[8]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[8]), + .C1(registers_25__ap[8]), .C2(n_1_0_1269), .ZN(n_1_0_816) + ); + NAND4_X1_LVT i_1_0_856( + .A1(n_1_0_822), .A2(n_1_0_818), .A3(n_1_0_817), .A4(n_1_0_816), .ZN(n_1_0_815) + ); + SDFF_X1_LVT \registers_reg[8][8] ( + .CK(n_0_38), .D(registers[8]), .Q(registers_8__ap[8]), .QN(), .SE(dftIn), + .SI(registers_4__ap[8]) + ); + SDFF_X1_LVT \registers_reg[28][8] ( + .CK(n_0_58), .D(registers[8]), .Q(registers_28__ap[8]), .QN(), .SE(dftIn), + .SI(registers_25__ap[8]) + ); + AOI221_X1_LVT i_1_0_855( + .A(n_1_0_815), .B1(n_1_0_1282), .B2(registers_8__ap[8]), .C1(registers_28__ap[8]), + .C2(n_1_0_1283), .ZN(n_1_0_814) + ); + SDFF_X1_LVT \registers_reg[18][8] ( + .CK(n_0_48), .D(registers[8]), .Q(registers_18__ap[8]), .QN(), .SE(dftIn), + .SI(registers_20__ap[8]) + ); + SDFF_X1_LVT \registers_reg[30][8] ( + .CK(n_0_60), .D(registers[8]), .Q(registers_30__ap[8]), .QN(), .SE(dftIn), + .SI(registers_28__ap[8]) + ); + AOI22_X1_LVT i_1_0_854( + .A1(registers_18__ap[8]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[8]), + .ZN(n_1_0_813) + ); + SDFF_X1_LVT \registers_reg[17][8] ( + .CK(n_0_47), .D(registers[8]), .Q(registers_17__ap[8]), .QN(), .SE(dftIn), + .SI(registers_18__ap[8]) + ); + SDFF_X1_LVT \registers_reg[12][8] ( + .CK(n_0_42), .D(registers[8]), .Q(registers_12__ap[8]), .QN(), .SE(dftIn), + .SI(registers_10__ap[8]) + ); + AOI22_X1_LVT i_1_0_853( + .A1(registers_17__ap[8]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[8]), + .ZN(n_1_0_812) + ); + SDFF_X1_LVT \registers_reg[15][8] ( + .CK(n_0_45), .D(registers[8]), .Q(registers_15__ap[8]), .QN(), .SE(dftIn), + .SI(registers_12__ap[8]) + ); + SDFF_X1_LVT \registers_reg[5][8] ( + .CK(n_0_35), .D(registers[8]), .Q(registers_5__ap[8]), .QN(), .SE(dftIn), + .SI(registers_8__ap[8]) + ); + AOI22_X1_LVT i_1_0_852( + .A1(registers_15__ap[8]), .A2(n_1_0_1286), .B1(n_1_0_1273), .B2(registers_5__ap[8]), + .ZN(n_1_0_811) + ); + NAND3_X1_LVT i_1_0_851( + .A1(n_1_0_813), .A2(n_1_0_812), .A3(n_1_0_811), .ZN(n_1_0_810) + ); + SDFF_X1_LVT \registers_reg[22][8] ( + .CK(n_0_52), .D(registers[8]), .Q(registers_22__ap[8]), .QN(), .SE(dftIn), + .SI(registers_17__ap[8]) + ); + SDFF_X1_LVT \registers_reg[16][8] ( + .CK(n_0_46), .D(registers[8]), .Q(registers_16__ap[8]), .QN(), .SE(dftIn), + .SI(registers_15__ap[8]) + ); + AOI221_X1_LVT i_1_0_850( + .A(n_1_0_810), .B1(n_1_0_1294), .B2(registers_22__ap[8]), .C1(registers_16__ap[8]), + .C2(n_1_0_1267), .ZN(n_1_0_809) + ); + SDFF_X1_LVT \registers_reg[9][8] ( + .CK(n_0_39), .D(registers[8]), .Q(registers_9__ap[8]), .QN(), .SE(dftIn), + .SI(registers_5__ap[8]) + ); + SDFF_X1_LVT \registers_reg[1][8] ( + .CK(n_0_0), .D(registers[8]), .Q(registers_1__ap[8]), .QN(), .SE(dftIn), + .SI(registers_22__ap[8]) + ); + AOI22_X1_LVT i_1_0_849( + .A1(registers_9__ap[8]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[8]), + .ZN(n_1_0_808) + ); + SDFF_X1_LVT \registers_reg[6][8] ( + .CK(n_0_36), .D(registers[8]), .Q(registers_6__ap[8]), .QN(), .SE(dftIn), + .SI(registers_9__ap[8]) + ); + SDFF_X1_LVT \registers_reg[14][8] ( + .CK(n_0_44), .D(registers[8]), .Q(registers_14__ap[8]), .QN(), .SE(dftIn), + .SI(registers_16__ap[8]) + ); + AOI22_X1_LVT i_1_0_848( + .A1(registers_6__ap[8]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[8]), + .ZN(n_1_0_807) + ); + SDFF_X1_LVT \registers_reg[19][8] ( + .CK(n_0_49), .D(registers[8]), .Q(registers_19__ap[8]), .QN(), .SE(dftIn), + .SI(registers_1__ap[8]) + ); + SDFF_X1_LVT \registers_reg[2][8] ( + .CK(n_0_32), .D(registers[8]), .Q(registers_2__ap[8]), .QN(), .SE(dftIn), + .SI(registers_30__ap[8]) + ); + AOI22_X1_LVT i_1_0_847( + .A1(registers_19__ap[8]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[8]), + .ZN(n_1_0_806) + ); + NAND3_X1_LVT i_1_0_846( + .A1(n_1_0_808), .A2(n_1_0_807), .A3(n_1_0_806), .ZN(n_1_0_805) + ); + SDFF_X1_LVT \registers_reg[11][8] ( + .CK(n_0_41), .D(registers[8]), .Q(registers_11__ap[8]), .QN(), .SE(dftIn), + .SI(registers_14__ap[8]) + ); + SDFF_X1_LVT \registers_reg[27][8] ( + .CK(n_0_57), .D(registers[8]), .Q(registers_27__ap[8]), .QN(), .SE(dftIn), + .SI(registers_2__ap[8]) + ); + AOI221_X1_LVT i_1_0_845( + .A(n_1_0_805), .B1(n_1_0_1270), .B2(registers_11__ap[8]), .C1(registers_27__ap[8]), + .C2(n_1_0_1279), .ZN(n_1_0_804) + ); + NAND4_X1_LVT i_1_0_844( + .A1(n_1_0_819), .A2(n_1_0_814), .A3(n_1_0_809), .A4(n_1_0_804), .ZN(RRs1[8]) + ); + AND2_X1_LVT i_0_0_7( + .A1(n_0_0_16), .A2(WRd[7]), .ZN(registers[7]) + ); + SDFF_X1_LVT \registers_reg[13][7] ( + .CK(n_0_43), .D(registers[7]), .Q(registers_13__ap[7]), .QN(), .SE(dftIn), + .SI(registers_11__ap[8]) + ); + SDFF_X1_LVT \registers_reg[21][7] ( + .CK(n_0_51), .D(registers[7]), .Q(registers_21__ap[7]), .QN(), .SE(dftIn), + .SI(registers_19__ap[8]) + ); + AOI22_X1_LVT i_1_0_843( + .A1(registers_13__ap[7]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[7]), + .ZN(n_1_0_803) + ); + SDFF_X1_LVT \registers_reg[18][7] ( + .CK(n_0_48), .D(registers[7]), .Q(registers_18__ap[7]), .QN(), .SE(dftIn), + .SI(registers_21__ap[7]) + ); + SDFF_X1_LVT \registers_reg[10][7] ( + .CK(n_0_40), .D(registers[7]), .Q(registers_10__ap[7]), .QN(), .SE(dftIn), + .SI(registers_13__ap[7]) + ); + SDFF_X1_LVT \registers_reg[25][7] ( + .CK(n_0_55), .D(registers[7]), .Q(registers_25__ap[7]), .QN(), .SE(dftIn), + .SI(registers_27__ap[8]) + ); + AOI222_X1_LVT i_1_0_842( + .A1(registers_18__ap[7]), .A2(n_1_0_1297), .B1(n_1_0_1287), .B2(registers_10__ap[7]), + .C1(registers_25__ap[7]), .C2(n_1_0_1269), .ZN(n_1_0_802) + ); + SDFF_X1_LVT \registers_reg[28][7] ( + .CK(n_0_58), .D(registers[7]), .Q(registers_28__ap[7]), .QN(), .SE(dftIn), + .SI(registers_25__ap[7]) + ); + SDFF_X1_LVT \registers_reg[8][7] ( + .CK(n_0_38), .D(registers[7]), .Q(registers_8__ap[7]), .QN(), .SE(dftIn), + .SI(registers_6__ap[8]) + ); + AOI22_X1_LVT i_1_0_841( + .A1(registers_28__ap[7]), .A2(n_1_0_1283), .B1(n_1_0_1282), .B2(registers_8__ap[7]), + .ZN(n_1_0_801) + ); + SDFF_X1_LVT \registers_reg[24][7] ( + .CK(n_0_54), .D(registers[7]), .Q(registers_24__ap[7]), .QN(), .SE(dftIn), + .SI(registers_28__ap[7]) + ); + SDFF_X1_LVT \registers_reg[20][7] ( + .CK(n_0_50), .D(registers[7]), .Q(registers_20__ap[7]), .QN(), .SE(dftIn), + .SI(registers_18__ap[7]) + ); + AOI22_X1_LVT i_1_0_840( + .A1(registers_24__ap[7]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[7]), + .ZN(n_1_0_800) + ); + SDFF_X1_LVT \registers_reg[31][7] ( + .CK(n_0_61), .D(registers[7]), .Q(registers_31__ap[7]), .QN(), .SE(dftIn), + .SI(registers_8__ap[7]) + ); + SDFF_X1_LVT \registers_reg[7][7] ( + .CK(n_0_37), .D(registers[7]), .Q(registers_7__ap[7]), .QN(), .SE(dftIn), + .SI(registers_31__ap[7]) + ); + AOI22_X1_LVT i_1_0_839( + .A1(registers_31__ap[7]), .A2(n_1_0_1266), .B1(n_1_0_1263), .B2(registers_7__ap[7]), + .ZN(n_1_0_799) + ); + SDFF_X1_LVT \registers_reg[17][7] ( + .CK(n_0_47), .D(registers[7]), .Q(registers_17__ap[7]), .QN(), .SE(dftIn), + .SI(registers_20__ap[7]) + ); + SDFF_X1_LVT \registers_reg[11][7] ( + .CK(n_0_41), .D(registers[7]), .Q(registers_11__ap[7]), .QN(), .SE(dftIn), + .SI(registers_10__ap[7]) + ); + AOI22_X1_LVT i_1_0_838( + .A1(registers_17__ap[7]), .A2(n_1_0_1271), .B1(n_1_0_1270), .B2(registers_11__ap[7]), + .ZN(n_1_0_798) + ); + SDFF_X1_LVT \registers_reg[27][7] ( + .CK(n_0_57), .D(registers[7]), .Q(registers_27__ap[7]), .QN(), .SE(dftIn), + .SI(registers_24__ap[7]) + ); + SDFF_X1_LVT \registers_reg[29][7] ( + .CK(n_0_59), .D(registers[7]), .Q(registers_29__ap[7]), .QN(), .SE(dftIn), + .SI(registers_27__ap[7]) + ); + AOI22_X1_LVT i_1_0_837( + .A1(registers_27__ap[7]), .A2(n_1_0_1279), .B1(n_1_0_1276), .B2(registers_29__ap[7]), + .ZN(n_1_0_797) + ); + NAND4_X1_LVT i_1_0_836( + .A1(n_1_0_800), .A2(n_1_0_799), .A3(n_1_0_798), .A4(n_1_0_797), .ZN(n_1_0_796) + ); + SDFF_X1_LVT \registers_reg[26][7] ( + .CK(n_0_56), .D(registers[7]), .Q(registers_26__ap[7]), .QN(), .SE(dftIn), + .SI(registers_29__ap[7]) + ); + SDFF_X1_LVT \registers_reg[30][7] ( + .CK(n_0_60), .D(registers[7]), .Q(registers_30__ap[7]), .QN(), .SE(dftIn), + .SI(registers_26__ap[7]) + ); + AOI22_X1_LVT i_1_0_835( + .A1(registers_26__ap[7]), .A2(n_1_0_1285), .B1(n_1_0_1272), .B2(registers_30__ap[7]), + .ZN(n_1_0_795) + ); + SDFF_X1_LVT \registers_reg[4][7] ( + .CK(n_0_34), .D(registers[7]), .Q(registers_4__ap[7]), .QN(), .SE(dftIn), + .SI(registers_7__ap[7]) + ); + SDFF_X1_LVT \registers_reg[12][7] ( + .CK(n_0_42), .D(registers[7]), .Q(registers_12__ap[7]), .QN(), .SE(dftIn), + .SI(registers_11__ap[7]) + ); + AOI22_X1_LVT i_1_0_834( + .A1(registers_4__ap[7]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[7]), + .ZN(n_1_0_794) + ); + SDFF_X1_LVT \registers_reg[15][7] ( + .CK(n_0_45), .D(registers[7]), .Q(registers_15__ap[7]), .QN(), .SE(dftIn), + .SI(registers_12__ap[7]) + ); + SDFF_X1_LVT \registers_reg[16][7] ( + .CK(n_0_46), .D(registers[7]), .Q(registers_16__ap[7]), .QN(), .SE(dftIn), + .SI(registers_15__ap[7]) + ); + AOI22_X1_LVT i_1_0_833( + .A1(registers_15__ap[7]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[7]), + .ZN(n_1_0_793) + ); + SDFF_X1_LVT \registers_reg[22][7] ( + .CK(n_0_52), .D(registers[7]), .Q(registers_22__ap[7]), .QN(), .SE(dftIn), + .SI(registers_17__ap[7]) + ); + SDFF_X1_LVT \registers_reg[5][7] ( + .CK(n_0_35), .D(registers[7]), .Q(registers_5__ap[7]), .QN(), .SE(dftIn), + .SI(registers_4__ap[7]) + ); + AOI22_X1_LVT i_1_0_832( + .A1(registers_22__ap[7]), .A2(n_1_0_1294), .B1(n_1_0_1273), .B2(registers_5__ap[7]), + .ZN(n_1_0_792) + ); + NAND4_X1_LVT i_1_0_831( + .A1(n_1_0_795), .A2(n_1_0_794), .A3(n_1_0_793), .A4(n_1_0_792), .ZN(n_1_0_791) + ); + SDFF_X1_LVT \registers_reg[19][7] ( + .CK(n_0_49), .D(registers[7]), .Q(registers_19__ap[7]), .QN(), .SE(dftIn), + .SI(registers_22__ap[7]) + ); + SDFF_X1_LVT \registers_reg[3][7] ( + .CK(n_0_33), .D(registers[7]), .Q(registers_3__ap[7]), .QN(), .SE(dftIn), + .SI(registers_5__ap[7]) + ); + AOI22_X1_LVT i_1_0_830( + .A1(registers_19__ap[7]), .A2(n_1_0_1295), .B1(n_1_0_1257), .B2(registers_3__ap[7]), + .ZN(n_1_0_790) + ); + SDFF_X1_LVT \registers_reg[9][7] ( + .CK(n_0_39), .D(registers[7]), .Q(registers_9__ap[7]), .QN(), .SE(dftIn), + .SI(registers_3__ap[7]) + ); + SDFF_X1_LVT \registers_reg[1][7] ( + .CK(n_0_0), .D(registers[7]), .Q(registers_1__ap[7]), .QN(), .SE(dftIn), + .SI(registers_19__ap[7]) + ); + AOI22_X1_LVT i_1_0_829( + .A1(registers_9__ap[7]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[7]), + .ZN(n_1_0_789) + ); + SDFF_X1_LVT \registers_reg[6][7] ( + .CK(n_0_36), .D(registers[7]), .Q(registers_6__ap[7]), .QN(), .SE(dftIn), + .SI(registers_9__ap[7]) + ); + SDFF_X1_LVT \registers_reg[14][7] ( + .CK(n_0_44), .D(registers[7]), .Q(registers_14__ap[7]), .QN(), .SE(dftIn), + .SI(registers_16__ap[7]) + ); + AOI22_X1_LVT i_1_0_828( + .A1(registers_6__ap[7]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[7]), + .ZN(n_1_0_788) + ); + SDFF_X1_LVT \registers_reg[2][7] ( + .CK(n_0_32), .D(registers[7]), .Q(registers_2__ap[7]), .QN(), .SE(dftIn), + .SI(registers_30__ap[7]) + ); + SDFF_X1_LVT \registers_reg[23][7] ( + .CK(n_0_53), .D(registers[7]), .Q(registers_23__ap[7]), .QN(), .SE(dftIn), + .SI(registers_1__ap[7]) + ); + AOI22_X1_LVT i_1_0_827( + .A1(registers_2__ap[7]), .A2(n_1_0_1268), .B1(n_1_0_1264), .B2(registers_23__ap[7]), + .ZN(n_1_0_787) + ); + NAND4_X1_LVT i_1_0_826( + .A1(n_1_0_790), .A2(n_1_0_789), .A3(n_1_0_788), .A4(n_1_0_787), .ZN(n_1_0_786) + ); + NOR3_X1_LVT i_1_0_825( + .A1(n_1_0_796), .A2(n_1_0_791), .A3(n_1_0_786), .ZN(n_1_0_785) + ); + NAND4_X1_LVT i_1_0_824( + .A1(n_1_0_803), .A2(n_1_0_802), .A3(n_1_0_801), .A4(n_1_0_785), .ZN(RRs1[7]) + ); + AND2_X1_LVT i_0_0_6( + .A1(n_0_0_16), .A2(WRd[6]), .ZN(registers[6]) + ); + SDFF_X1_LVT \registers_reg[28][6] ( + .CK(n_0_58), .D(registers[6]), .Q(registers_28__ap[6]), .QN(), .SE(dftIn), + .SI(registers_2__ap[7]) + ); + SDFF_X1_LVT \registers_reg[17][6] ( + .CK(n_0_47), .D(registers[6]), .Q(registers_17__ap[6]), .QN(), .SE(dftIn), + .SI(registers_23__ap[7]) + ); + AOI22_X1_LVT i_1_0_823( + .A1(registers_28__ap[6]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[6]), + .ZN(n_1_0_784) + ); + SDFF_X1_LVT \registers_reg[18][6] ( + .CK(n_0_48), .D(registers[6]), .Q(registers_18__ap[6]), .QN(), .SE(dftIn), + .SI(registers_17__ap[6]) + ); + SDFF_X1_LVT \registers_reg[10][6] ( + .CK(n_0_40), .D(registers[6]), .Q(registers_10__ap[6]), .QN(), .SE(dftIn), + .SI(registers_14__ap[7]) + ); + SDFF_X1_LVT \registers_reg[8][6] ( + .CK(n_0_38), .D(registers[6]), .Q(registers_8__ap[6]), .QN(), .SE(dftIn), + .SI(registers_6__ap[7]) + ); + AOI222_X1_LVT i_1_0_822( + .A1(registers_18__ap[6]), .A2(n_1_0_1297), .B1(n_1_0_1287), .B2(registers_10__ap[6]), + .C1(registers_8__ap[6]), .C2(n_1_0_1282), .ZN(n_1_0_783) + ); + SDFF_X1_LVT \registers_reg[9][6] ( + .CK(n_0_39), .D(registers[6]), .Q(registers_9__ap[6]), .QN(), .SE(dftIn), + .SI(registers_8__ap[6]) + ); + SDFF_X1_LVT \registers_reg[29][6] ( + .CK(n_0_59), .D(registers[6]), .Q(registers_29__ap[6]), .QN(), .SE(dftIn), + .SI(registers_28__ap[6]) + ); + AOI22_X1_LVT i_1_0_821( + .A1(registers_9__ap[6]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[6]), + .ZN(n_1_0_782) + ); + SDFF_X1_LVT \registers_reg[6][6] ( + .CK(n_0_36), .D(registers[6]), .Q(registers_6__ap[6]), .QN(), .SE(dftIn), + .SI(registers_9__ap[6]) + ); + SDFF_X1_LVT \registers_reg[1][6] ( + .CK(n_0_0), .D(registers[6]), .Q(registers_1__ap[6]), .QN(), .SE(dftIn), + .SI(registers_18__ap[6]) + ); + AOI22_X1_LVT i_1_0_820( + .A1(registers_6__ap[6]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[6]), + .ZN(n_1_0_781) + ); + SDFF_X1_LVT \registers_reg[15][6] ( + .CK(n_0_45), .D(registers[6]), .Q(registers_15__ap[6]), .QN(), .SE(dftIn), + .SI(registers_10__ap[6]) + ); + SDFF_X1_LVT \registers_reg[27][6] ( + .CK(n_0_57), .D(registers[6]), .Q(registers_27__ap[6]), .QN(), .SE(dftIn), + .SI(registers_29__ap[6]) + ); + AOI22_X1_LVT i_1_0_819( + .A1(registers_15__ap[6]), .A2(n_1_0_1286), .B1(n_1_0_1279), .B2(registers_27__ap[6]), + .ZN(n_1_0_780) + ); + SDFF_X1_LVT \registers_reg[11][6] ( + .CK(n_0_41), .D(registers[6]), .Q(registers_11__ap[6]), .QN(), .SE(dftIn), + .SI(registers_15__ap[6]) + ); + SDFF_X1_LVT \registers_reg[16][6] ( + .CK(n_0_46), .D(registers[6]), .Q(registers_16__ap[6]), .QN(), .SE(dftIn), + .SI(registers_11__ap[6]) + ); + AOI22_X1_LVT i_1_0_818( + .A1(registers_11__ap[6]), .A2(n_1_0_1270), .B1(n_1_0_1267), .B2(registers_16__ap[6]), + .ZN(n_1_0_779) + ); + SDFF_X1_LVT \registers_reg[5][6] ( + .CK(n_0_35), .D(registers[6]), .Q(registers_5__ap[6]), .QN(), .SE(dftIn), + .SI(registers_6__ap[6]) + ); + SDFF_X1_LVT \registers_reg[31][6] ( + .CK(n_0_61), .D(registers[6]), .Q(registers_31__ap[6]), .QN(), .SE(dftIn), + .SI(registers_5__ap[6]) + ); + AOI22_X1_LVT i_1_0_817( + .A1(registers_5__ap[6]), .A2(n_1_0_1273), .B1(n_1_0_1266), .B2(registers_31__ap[6]), + .ZN(n_1_0_778) + ); + NAND4_X1_LVT i_1_0_816( + .A1(n_1_0_781), .A2(n_1_0_780), .A3(n_1_0_779), .A4(n_1_0_778), .ZN(n_1_0_777) + ); + SDFF_X1_LVT \registers_reg[26][6] ( + .CK(n_0_56), .D(registers[6]), .Q(registers_26__ap[6]), .QN(), .SE(dftIn), + .SI(registers_27__ap[6]) + ); + SDFF_X1_LVT \registers_reg[30][6] ( + .CK(n_0_60), .D(registers[6]), .Q(registers_30__ap[6]), .QN(), .SE(dftIn), + .SI(registers_26__ap[6]) + ); + AOI22_X1_LVT i_1_0_815( + .A1(registers_26__ap[6]), .A2(n_1_0_1285), .B1(n_1_0_1272), .B2(registers_30__ap[6]), + .ZN(n_1_0_776) + ); + SDFF_X1_LVT \registers_reg[20][6] ( + .CK(n_0_50), .D(registers[6]), .Q(registers_20__ap[6]), .QN(), .SE(dftIn), + .SI(registers_1__ap[6]) + ); + SDFF_X1_LVT \registers_reg[4][6] ( + .CK(n_0_34), .D(registers[6]), .Q(registers_4__ap[6]), .QN(), .SE(dftIn), + .SI(registers_31__ap[6]) + ); + AOI22_X1_LVT i_1_0_814( + .A1(registers_20__ap[6]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[6]), + .ZN(n_1_0_775) + ); + SDFF_X1_LVT \registers_reg[22][6] ( + .CK(n_0_52), .D(registers[6]), .Q(registers_22__ap[6]), .QN(), .SE(dftIn), + .SI(registers_20__ap[6]) + ); + SDFF_X1_LVT \registers_reg[21][6] ( + .CK(n_0_51), .D(registers[6]), .Q(registers_21__ap[6]), .QN(), .SE(dftIn), + .SI(registers_22__ap[6]) + ); + AOI22_X1_LVT i_1_0_813( + .A1(registers_22__ap[6]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[6]), + .ZN(n_1_0_774) + ); + SDFF_X1_LVT \registers_reg[24][6] ( + .CK(n_0_54), .D(registers[6]), .Q(registers_24__ap[6]), .QN(), .SE(dftIn), + .SI(registers_30__ap[6]) + ); + SDFF_X1_LVT \registers_reg[12][6] ( + .CK(n_0_42), .D(registers[6]), .Q(registers_12__ap[6]), .QN(), .SE(dftIn), + .SI(registers_16__ap[6]) + ); + AOI22_X1_LVT i_1_0_812( + .A1(registers_24__ap[6]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[6]), + .ZN(n_1_0_773) + ); + NAND4_X1_LVT i_1_0_811( + .A1(n_1_0_776), .A2(n_1_0_775), .A3(n_1_0_774), .A4(n_1_0_773), .ZN(n_1_0_772) + ); + SDFF_X1_LVT \registers_reg[13][6] ( + .CK(n_0_43), .D(registers[6]), .Q(registers_13__ap[6]), .QN(), .SE(dftIn), + .SI(registers_12__ap[6]) + ); + SDFF_X1_LVT \registers_reg[25][6] ( + .CK(n_0_55), .D(registers[6]), .Q(registers_25__ap[6]), .QN(), .SE(dftIn), + .SI(registers_24__ap[6]) + ); + AOI22_X1_LVT i_1_0_810( + .A1(registers_13__ap[6]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[6]), + .ZN(n_1_0_771) + ); + SDFF_X1_LVT \registers_reg[7][6] ( + .CK(n_0_37), .D(registers[6]), .Q(registers_7__ap[6]), .QN(), .SE(dftIn), + .SI(registers_4__ap[6]) + ); + SDFF_X1_LVT \registers_reg[14][6] ( + .CK(n_0_44), .D(registers[6]), .Q(registers_14__ap[6]), .QN(), .SE(dftIn), + .SI(registers_13__ap[6]) + ); + AOI22_X1_LVT i_1_0_809( + .A1(registers_7__ap[6]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[6]), + .ZN(n_1_0_770) + ); + SDFF_X1_LVT \registers_reg[19][6] ( + .CK(n_0_49), .D(registers[6]), .Q(registers_19__ap[6]), .QN(), .SE(dftIn), + .SI(registers_21__ap[6]) + ); + SDFF_X1_LVT \registers_reg[3][6] ( + .CK(n_0_33), .D(registers[6]), .Q(registers_3__ap[6]), .QN(), .SE(dftIn), + .SI(registers_7__ap[6]) + ); + AOI22_X1_LVT i_1_0_808( + .A1(registers_19__ap[6]), .A2(n_1_0_1295), .B1(n_1_0_1257), .B2(registers_3__ap[6]), + .ZN(n_1_0_769) + ); + SDFF_X1_LVT \registers_reg[2][6] ( + .CK(n_0_32), .D(registers[6]), .Q(registers_2__ap[6]), .QN(), .SE(dftIn), + .SI(registers_25__ap[6]) + ); + SDFF_X1_LVT \registers_reg[23][6] ( + .CK(n_0_53), .D(registers[6]), .Q(registers_23__ap[6]), .QN(), .SE(dftIn), + .SI(registers_19__ap[6]) + ); + AOI22_X1_LVT i_1_0_807( + .A1(registers_2__ap[6]), .A2(n_1_0_1268), .B1(n_1_0_1264), .B2(registers_23__ap[6]), + .ZN(n_1_0_768) + ); + NAND4_X1_LVT i_1_0_806( + .A1(n_1_0_771), .A2(n_1_0_770), .A3(n_1_0_769), .A4(n_1_0_768), .ZN(n_1_0_767) + ); + NOR3_X1_LVT i_1_0_805( + .A1(n_1_0_777), .A2(n_1_0_772), .A3(n_1_0_767), .ZN(n_1_0_766) + ); + NAND4_X1_LVT i_1_0_804( + .A1(n_1_0_784), .A2(n_1_0_783), .A3(n_1_0_782), .A4(n_1_0_766), .ZN(RRs1[6]) + ); + AND2_X1_LVT i_0_0_5( + .A1(n_0_0_16), .A2(WRd[5]), .ZN(registers[5]) + ); + SDFF_X1_LVT \registers_reg[28][5] ( + .CK(n_0_58), .D(registers[5]), .Q(registers_28__ap[5]), .QN(), .SE(dftIn), + .SI(registers_2__ap[6]) + ); + SDFF_X1_LVT \registers_reg[4][5] ( + .CK(n_0_34), .D(registers[5]), .Q(registers_4__ap[5]), .QN(), .SE(dftIn), + .SI(registers_3__ap[6]) + ); + AOI22_X1_LVT i_1_0_803( + .A1(registers_28__ap[5]), .A2(n_1_0_1283), .B1(n_1_0_1278), .B2(registers_4__ap[5]), + .ZN(n_1_0_765) + ); + SDFF_X1_LVT \registers_reg[10][5] ( + .CK(n_0_40), .D(registers[5]), .Q(registers_10__ap[5]), .QN(), .SE(dftIn), + .SI(registers_14__ap[6]) + ); + SDFF_X1_LVT \registers_reg[26][5] ( + .CK(n_0_56), .D(registers[5]), .Q(registers_26__ap[5]), .QN(), .SE(dftIn), + .SI(registers_28__ap[5]) + ); + SDFF_X1_LVT \registers_reg[8][5] ( + .CK(n_0_38), .D(registers[5]), .Q(registers_8__ap[5]), .QN(), .SE(dftIn), + .SI(registers_4__ap[5]) + ); + AOI222_X1_LVT i_1_0_802( + .A1(registers_10__ap[5]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[5]), + .C1(registers_8__ap[5]), .C2(n_1_0_1282), .ZN(n_1_0_764) + ); + SDFF_X1_LVT \registers_reg[9][5] ( + .CK(n_0_39), .D(registers[5]), .Q(registers_9__ap[5]), .QN(), .SE(dftIn), + .SI(registers_8__ap[5]) + ); + SDFF_X1_LVT \registers_reg[29][5] ( + .CK(n_0_59), .D(registers[5]), .Q(registers_29__ap[5]), .QN(), .SE(dftIn), + .SI(registers_26__ap[5]) + ); + AOI22_X1_LVT i_1_0_801( + .A1(registers_9__ap[5]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[5]), + .ZN(n_1_0_763) + ); + SDFF_X1_LVT \registers_reg[6][5] ( + .CK(n_0_36), .D(registers[5]), .Q(registers_6__ap[5]), .QN(), .SE(dftIn), + .SI(registers_9__ap[5]) + ); + SDFF_X1_LVT \registers_reg[1][5] ( + .CK(n_0_0), .D(registers[5]), .Q(registers_1__ap[5]), .QN(), .SE(dftIn), + .SI(registers_23__ap[6]) + ); + AOI22_X1_LVT i_1_0_800( + .A1(registers_6__ap[5]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[5]), + .ZN(n_1_0_762) + ); + SDFF_X1_LVT \registers_reg[16][5] ( + .CK(n_0_46), .D(registers[5]), .Q(registers_16__ap[5]), .QN(), .SE(dftIn), + .SI(registers_10__ap[5]) + ); + SDFF_X1_LVT \registers_reg[3][5] ( + .CK(n_0_33), .D(registers[5]), .Q(registers_3__ap[5]), .QN(), .SE(dftIn), + .SI(registers_6__ap[5]) + ); + AOI22_X1_LVT i_1_0_799( + .A1(registers_16__ap[5]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[5]), + .ZN(n_1_0_761) + ); + SDFF_X1_LVT \registers_reg[5][5] ( + .CK(n_0_35), .D(registers[5]), .Q(registers_5__ap[5]), .QN(), .SE(dftIn), + .SI(registers_3__ap[5]) + ); + SDFF_X1_LVT \registers_reg[31][5] ( + .CK(n_0_61), .D(registers[5]), .Q(registers_31__ap[5]), .QN(), .SE(dftIn), + .SI(registers_5__ap[5]) + ); + AOI22_X1_LVT i_1_0_798( + .A1(registers_5__ap[5]), .A2(n_1_0_1273), .B1(n_1_0_1266), .B2(registers_31__ap[5]), + .ZN(n_1_0_760) + ); + SDFF_X1_LVT \registers_reg[15][5] ( + .CK(n_0_45), .D(registers[5]), .Q(registers_15__ap[5]), .QN(), .SE(dftIn), + .SI(registers_16__ap[5]) + ); + SDFF_X1_LVT \registers_reg[23][5] ( + .CK(n_0_53), .D(registers[5]), .Q(registers_23__ap[5]), .QN(), .SE(dftIn), + .SI(registers_1__ap[5]) + ); + AOI22_X1_LVT i_1_0_797( + .A1(registers_15__ap[5]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[5]), + .ZN(n_1_0_759) + ); + NAND4_X1_LVT i_1_0_796( + .A1(n_1_0_762), .A2(n_1_0_761), .A3(n_1_0_760), .A4(n_1_0_759), .ZN(n_1_0_758) + ); + SDFF_X1_LVT \registers_reg[18][5] ( + .CK(n_0_48), .D(registers[5]), .Q(registers_18__ap[5]), .QN(), .SE(dftIn), + .SI(registers_23__ap[5]) + ); + SDFF_X1_LVT \registers_reg[30][5] ( + .CK(n_0_60), .D(registers[5]), .Q(registers_30__ap[5]), .QN(), .SE(dftIn), + .SI(registers_29__ap[5]) + ); + AOI22_X1_LVT i_1_0_795( + .A1(registers_18__ap[5]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[5]), + .ZN(n_1_0_757) + ); + SDFF_X1_LVT \registers_reg[24][5] ( + .CK(n_0_54), .D(registers[5]), .Q(registers_24__ap[5]), .QN(), .SE(dftIn), + .SI(registers_30__ap[5]) + ); + SDFF_X1_LVT \registers_reg[12][5] ( + .CK(n_0_42), .D(registers[5]), .Q(registers_12__ap[5]), .QN(), .SE(dftIn), + .SI(registers_15__ap[5]) + ); + AOI22_X1_LVT i_1_0_794( + .A1(registers_24__ap[5]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[5]), + .ZN(n_1_0_756) + ); + SDFF_X1_LVT \registers_reg[22][5] ( + .CK(n_0_52), .D(registers[5]), .Q(registers_22__ap[5]), .QN(), .SE(dftIn), + .SI(registers_18__ap[5]) + ); + SDFF_X1_LVT \registers_reg[21][5] ( + .CK(n_0_51), .D(registers[5]), .Q(registers_21__ap[5]), .QN(), .SE(dftIn), + .SI(registers_22__ap[5]) + ); + AOI22_X1_LVT i_1_0_793( + .A1(registers_22__ap[5]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[5]), + .ZN(n_1_0_755) + ); + SDFF_X1_LVT \registers_reg[20][5] ( + .CK(n_0_50), .D(registers[5]), .Q(registers_20__ap[5]), .QN(), .SE(dftIn), + .SI(registers_21__ap[5]) + ); + SDFF_X1_LVT \registers_reg[17][5] ( + .CK(n_0_47), .D(registers[5]), .Q(registers_17__ap[5]), .QN(), .SE(dftIn), + .SI(registers_20__ap[5]) + ); + AOI22_X1_LVT i_1_0_792( + .A1(registers_20__ap[5]), .A2(n_1_0_1281), .B1(n_1_0_1271), .B2(registers_17__ap[5]), + .ZN(n_1_0_754) + ); + NAND4_X1_LVT i_1_0_791( + .A1(n_1_0_757), .A2(n_1_0_756), .A3(n_1_0_755), .A4(n_1_0_754), .ZN(n_1_0_753) + ); + SDFF_X1_LVT \registers_reg[13][5] ( + .CK(n_0_43), .D(registers[5]), .Q(registers_13__ap[5]), .QN(), .SE(dftIn), + .SI(registers_12__ap[5]) + ); + SDFF_X1_LVT \registers_reg[25][5] ( + .CK(n_0_55), .D(registers[5]), .Q(registers_25__ap[5]), .QN(), .SE(dftIn), + .SI(registers_24__ap[5]) + ); + AOI22_X1_LVT i_1_0_790( + .A1(registers_13__ap[5]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[5]), + .ZN(n_1_0_752) + ); + SDFF_X1_LVT \registers_reg[19][5] ( + .CK(n_0_49), .D(registers[5]), .Q(registers_19__ap[5]), .QN(), .SE(dftIn), + .SI(registers_17__ap[5]) + ); + SDFF_X1_LVT \registers_reg[2][5] ( + .CK(n_0_32), .D(registers[5]), .Q(registers_2__ap[5]), .QN(), .SE(dftIn), + .SI(registers_25__ap[5]) + ); + AOI22_X1_LVT i_1_0_789( + .A1(registers_19__ap[5]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[5]), + .ZN(n_1_0_751) + ); + SDFF_X1_LVT \registers_reg[7][5] ( + .CK(n_0_37), .D(registers[5]), .Q(registers_7__ap[5]), .QN(), .SE(dftIn), + .SI(registers_31__ap[5]) + ); + SDFF_X1_LVT \registers_reg[14][5] ( + .CK(n_0_44), .D(registers[5]), .Q(registers_14__ap[5]), .QN(), .SE(dftIn), + .SI(registers_13__ap[5]) + ); + AOI22_X1_LVT i_1_0_788( + .A1(registers_7__ap[5]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[5]), + .ZN(n_1_0_750) + ); + SDFF_X1_LVT \registers_reg[27][5] ( + .CK(n_0_57), .D(registers[5]), .Q(registers_27__ap[5]), .QN(), .SE(dftIn), + .SI(registers_2__ap[5]) + ); + SDFF_X1_LVT \registers_reg[11][5] ( + .CK(n_0_41), .D(registers[5]), .Q(registers_11__ap[5]), .QN(), .SE(dftIn), + .SI(registers_14__ap[5]) + ); + AOI22_X1_LVT i_1_0_787( + .A1(registers_27__ap[5]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[5]), + .ZN(n_1_0_749) + ); + NAND4_X1_LVT i_1_0_786( + .A1(n_1_0_752), .A2(n_1_0_751), .A3(n_1_0_750), .A4(n_1_0_749), .ZN(n_1_0_748) + ); + NOR3_X1_LVT i_1_0_785( + .A1(n_1_0_758), .A2(n_1_0_753), .A3(n_1_0_748), .ZN(n_1_0_747) + ); + NAND4_X1_LVT i_1_0_784( + .A1(n_1_0_765), .A2(n_1_0_764), .A3(n_1_0_763), .A4(n_1_0_747), .ZN(RRs1[5]) + ); + AND2_X1_LVT i_0_0_4( + .A1(n_0_0_16), .A2(WRd[4]), .ZN(registers[4]) + ); + SDFF_X1_LVT \registers_reg[10][4] ( + .CK(n_0_40), .D(registers[4]), .Q(registers_10__ap[4]), .QN(), .SE(dftIn), + .SI(registers_11__ap[5]) + ); + SDFF_X1_LVT \registers_reg[21][4] ( + .CK(n_0_51), .D(registers[4]), .Q(registers_21__ap[4]), .QN(), .SE(dftIn), + .SI(registers_19__ap[5]) + ); + AOI22_X1_LVT i_1_0_783( + .A1(registers_10__ap[4]), .A2(n_1_0_1287), .B1(n_1_0_1259), .B2(registers_21__ap[4]), + .ZN(n_1_0_746) + ); + SDFF_X1_LVT \registers_reg[9][4] ( + .CK(n_0_39), .D(registers[4]), .Q(registers_9__ap[4]), .QN(), .SE(dftIn), + .SI(registers_7__ap[5]) + ); + SDFF_X1_LVT \registers_reg[1][4] ( + .CK(n_0_0), .D(registers[4]), .Q(registers_1__ap[4]), .QN(), .SE(dftIn), + .SI(registers_21__ap[4]) + ); + AOI22_X1_LVT i_1_0_778( + .A1(registers_9__ap[4]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[4]), + .ZN(n_1_0_741) + ); + SDFF_X1_LVT \registers_reg[18][4] ( + .CK(n_0_48), .D(registers[4]), .Q(registers_18__ap[4]), .QN(), .SE(dftIn), + .SI(registers_1__ap[4]) + ); + SDFF_X1_LVT \registers_reg[8][4] ( + .CK(n_0_38), .D(registers[4]), .Q(registers_8__ap[4]), .QN(), .SE(dftIn), + .SI(registers_9__ap[4]) + ); + AOI22_X1_LVT i_1_0_777( + .A1(registers_18__ap[4]), .A2(n_1_0_1297), .B1(n_1_0_1282), .B2(registers_8__ap[4]), + .ZN(n_1_0_740) + ); + NAND3_X1_LVT i_1_0_775( + .A1(n_1_0_746), .A2(n_1_0_741), .A3(n_1_0_740), .ZN(n_1_0_738) + ); + SDFF_X1_LVT \registers_reg[22][4] ( + .CK(n_0_52), .D(registers[4]), .Q(registers_22__ap[4]), .QN(), .SE(dftIn), + .SI(registers_18__ap[4]) + ); + SDFF_X1_LVT \registers_reg[23][4] ( + .CK(n_0_53), .D(registers[4]), .Q(registers_23__ap[4]), .QN(), .SE(dftIn), + .SI(registers_22__ap[4]) + ); + AOI221_X1_LVT i_1_0_774( + .A(n_1_0_738), .B1(n_1_0_1294), .B2(registers_22__ap[4]), .C1(registers_23__ap[4]), + .C2(n_1_0_1264), .ZN(n_1_0_737) + ); + SDFF_X1_LVT \registers_reg[28][4] ( + .CK(n_0_58), .D(registers[4]), .Q(registers_28__ap[4]), .QN(), .SE(dftIn), + .SI(registers_27__ap[5]) + ); + SDFF_X1_LVT \registers_reg[20][4] ( + .CK(n_0_50), .D(registers[4]), .Q(registers_20__ap[4]), .QN(), .SE(dftIn), + .SI(registers_23__ap[4]) + ); + AOI22_X1_LVT i_1_0_782( + .A1(registers_28__ap[4]), .A2(n_1_0_1283), .B1(n_1_0_1281), .B2(registers_20__ap[4]), + .ZN(n_1_0_745) + ); + SDFF_X1_LVT \registers_reg[19][4] ( + .CK(n_0_49), .D(registers[4]), .Q(registers_19__ap[4]), .QN(), .SE(dftIn), + .SI(registers_20__ap[4]) + ); + SDFF_X1_LVT \registers_reg[13][4] ( + .CK(n_0_43), .D(registers[4]), .Q(registers_13__ap[4]), .QN(), .SE(dftIn), + .SI(registers_10__ap[4]) + ); + AOI22_X1_LVT i_1_0_780( + .A1(registers_19__ap[4]), .A2(n_1_0_1295), .B1(n_1_0_1277), .B2(registers_13__ap[4]), + .ZN(n_1_0_743) + ); + SDFF_X1_LVT \registers_reg[26][4] ( + .CK(n_0_56), .D(registers[4]), .Q(registers_26__ap[4]), .QN(), .SE(dftIn), + .SI(registers_28__ap[4]) + ); + SDFF_X1_LVT \registers_reg[3][4] ( + .CK(n_0_33), .D(registers[4]), .Q(registers_3__ap[4]), .QN(), .SE(dftIn), + .SI(registers_8__ap[4]) + ); + AOI22_X1_LVT i_1_0_776( + .A1(registers_26__ap[4]), .A2(n_1_0_1285), .B1(n_1_0_1257), .B2(registers_3__ap[4]), + .ZN(n_1_0_739) + ); + NAND3_X1_LVT i_1_0_773( + .A1(n_1_0_745), .A2(n_1_0_743), .A3(n_1_0_739), .ZN(n_1_0_736) + ); + SDFF_X1_LVT \registers_reg[30][4] ( + .CK(n_0_60), .D(registers[4]), .Q(registers_30__ap[4]), .QN(), .SE(dftIn), + .SI(registers_26__ap[4]) + ); + SDFF_X1_LVT \registers_reg[31][4] ( + .CK(n_0_61), .D(registers[4]), .Q(registers_31__ap[4]), .QN(), .SE(dftIn), + .SI(registers_3__ap[4]) + ); + AOI221_X1_LVT i_1_0_772( + .A(n_1_0_736), .B1(n_1_0_1272), .B2(registers_30__ap[4]), .C1(registers_31__ap[4]), + .C2(n_1_0_1266), .ZN(n_1_0_735) + ); + SDFF_X1_LVT \registers_reg[24][4] ( + .CK(n_0_54), .D(registers[4]), .Q(registers_24__ap[4]), .QN(), .SE(dftIn), + .SI(registers_30__ap[4]) + ); + SDFF_X1_LVT \registers_reg[12][4] ( + .CK(n_0_42), .D(registers[4]), .Q(registers_12__ap[4]), .QN(), .SE(dftIn), + .SI(registers_13__ap[4]) + ); + AOI22_X1_LVT i_1_0_781( + .A1(registers_24__ap[4]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[4]), + .ZN(n_1_0_744) + ); + SDFF_X1_LVT \registers_reg[27][4] ( + .CK(n_0_57), .D(registers[4]), .Q(registers_27__ap[4]), .QN(), .SE(dftIn), + .SI(registers_24__ap[4]) + ); + SDFF_X1_LVT \registers_reg[11][4] ( + .CK(n_0_41), .D(registers[4]), .Q(registers_11__ap[4]), .QN(), .SE(dftIn), + .SI(registers_12__ap[4]) + ); + AOI22_X1_LVT i_1_0_779( + .A1(registers_27__ap[4]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[4]), + .ZN(n_1_0_742) + ); + SDFF_X1_LVT \registers_reg[17][4] ( + .CK(n_0_47), .D(registers[4]), .Q(registers_17__ap[4]), .QN(), .SE(dftIn), + .SI(registers_19__ap[4]) + ); + SDFF_X1_LVT \registers_reg[7][4] ( + .CK(n_0_37), .D(registers[4]), .Q(registers_7__ap[4]), .QN(), .SE(dftIn), + .SI(registers_31__ap[4]) + ); + SDFF_X1_LVT \registers_reg[14][4] ( + .CK(n_0_44), .D(registers[4]), .Q(registers_14__ap[4]), .QN(), .SE(dftIn), + .SI(registers_11__ap[4]) + ); + AOI222_X1_LVT i_1_0_771( + .A1(registers_17__ap[4]), .A2(n_1_0_1271), .B1(n_1_0_1263), .B2(registers_7__ap[4]), + .C1(n_1_0_1258), .C2(registers_14__ap[4]), .ZN(n_1_0_734) + ); + SDFF_X1_LVT \registers_reg[15][4] ( + .CK(n_0_45), .D(registers[4]), .Q(registers_15__ap[4]), .QN(), .SE(dftIn), + .SI(registers_14__ap[4]) + ); + SDFF_X1_LVT \registers_reg[16][4] ( + .CK(n_0_46), .D(registers[4]), .Q(registers_16__ap[4]), .QN(), .SE(dftIn), + .SI(registers_15__ap[4]) + ); + AOI22_X1_LVT i_1_0_770( + .A1(registers_15__ap[4]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[4]), + .ZN(n_1_0_733) + ); + SDFF_X1_LVT \registers_reg[4][4] ( + .CK(n_0_34), .D(registers[4]), .Q(registers_4__ap[4]), .QN(), .SE(dftIn), + .SI(registers_7__ap[4]) + ); + SDFF_X1_LVT \registers_reg[25][4] ( + .CK(n_0_55), .D(registers[4]), .Q(registers_25__ap[4]), .QN(), .SE(dftIn), + .SI(registers_27__ap[4]) + ); + AOI22_X1_LVT i_1_0_769( + .A1(registers_4__ap[4]), .A2(n_1_0_1278), .B1(n_1_0_1269), .B2(registers_25__ap[4]), + .ZN(n_1_0_732) + ); + SDFF_X1_LVT \registers_reg[29][4] ( + .CK(n_0_59), .D(registers[4]), .Q(registers_29__ap[4]), .QN(), .SE(dftIn), + .SI(registers_25__ap[4]) + ); + SDFF_X1_LVT \registers_reg[2][4] ( + .CK(n_0_32), .D(registers[4]), .Q(registers_2__ap[4]), .QN(), .SE(dftIn), + .SI(registers_29__ap[4]) + ); + AOI22_X1_LVT i_1_0_768( + .A1(registers_29__ap[4]), .A2(n_1_0_1276), .B1(n_1_0_1268), .B2(registers_2__ap[4]), + .ZN(n_1_0_731) + ); + NAND3_X1_LVT i_1_0_767( + .A1(n_1_0_733), .A2(n_1_0_732), .A3(n_1_0_731), .ZN(n_1_0_730) + ); + SDFF_X1_LVT \registers_reg[6][4] ( + .CK(n_0_36), .D(registers[4]), .Q(registers_6__ap[4]), .QN(), .SE(dftIn), + .SI(registers_4__ap[4]) + ); + SDFF_X1_LVT \registers_reg[5][4] ( + .CK(n_0_35), .D(registers[4]), .Q(registers_5__ap[4]), .QN(), .SE(dftIn), + .SI(registers_6__ap[4]) + ); + AOI221_X1_LVT i_1_0_766( + .A(n_1_0_730), .B1(n_1_0_1300), .B2(registers_6__ap[4]), .C1(registers_5__ap[4]), + .C2(n_1_0_1273), .ZN(n_1_0_729) + ); + AND4_X1_LVT i_1_0_765( + .A1(n_1_0_744), .A2(n_1_0_742), .A3(n_1_0_734), .A4(n_1_0_729), .ZN(n_1_0_728) + ); + NAND3_X1_LVT i_1_0_764( + .A1(n_1_0_737), .A2(n_1_0_735), .A3(n_1_0_728), .ZN(RRs1[4]) + ); + AND2_X1_LVT i_0_0_3( + .A1(n_0_0_16), .A2(WRd[3]), .ZN(registers[3]) + ); + SDFF_X1_LVT \registers_reg[28][3] ( + .CK(n_0_58), .D(registers[3]), .Q(registers_28__ap[3]), .QN(), .SE(dftIn), + .SI(registers_2__ap[4]) + ); + SDFF_X1_LVT \registers_reg[17][3] ( + .CK(n_0_47), .D(registers[3]), .Q(registers_17__ap[3]), .QN(), .SE(dftIn), + .SI(registers_17__ap[4]) + ); + AOI22_X1_LVT i_1_0_763( + .A1(registers_28__ap[3]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[3]), + .ZN(n_1_0_727) + ); + SDFF_X1_LVT \registers_reg[10][3] ( + .CK(n_0_40), .D(registers[3]), .Q(registers_10__ap[3]), .QN(), .SE(dftIn), + .SI(registers_16__ap[4]) + ); + SDFF_X1_LVT \registers_reg[26][3] ( + .CK(n_0_56), .D(registers[3]), .Q(registers_26__ap[3]), .QN(), .SE(dftIn), + .SI(registers_28__ap[3]) + ); + SDFF_X1_LVT \registers_reg[8][3] ( + .CK(n_0_38), .D(registers[3]), .Q(registers_8__ap[3]), .QN(), .SE(dftIn), + .SI(registers_5__ap[4]) + ); + AOI222_X1_LVT i_1_0_762( + .A1(registers_10__ap[3]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[3]), + .C1(registers_8__ap[3]), .C2(n_1_0_1282), .ZN(n_1_0_726) + ); + SDFF_X1_LVT \registers_reg[9][3] ( + .CK(n_0_39), .D(registers[3]), .Q(registers_9__ap[3]), .QN(), .SE(dftIn), + .SI(registers_8__ap[3]) + ); + SDFF_X1_LVT \registers_reg[29][3] ( + .CK(n_0_59), .D(registers[3]), .Q(registers_29__ap[3]), .QN(), .SE(dftIn), + .SI(registers_26__ap[3]) + ); + AOI22_X1_LVT i_1_0_761( + .A1(registers_9__ap[3]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[3]), + .ZN(n_1_0_725) + ); + SDFF_X1_LVT \registers_reg[6][3] ( + .CK(n_0_36), .D(registers[3]), .Q(registers_6__ap[3]), .QN(), .SE(dftIn), + .SI(registers_9__ap[3]) + ); + SDFF_X1_LVT \registers_reg[1][3] ( + .CK(n_0_0), .D(registers[3]), .Q(registers_1__ap[3]), .QN(), .SE(dftIn), + .SI(registers_17__ap[3]) + ); + AOI22_X1_LVT i_1_0_760( + .A1(registers_6__ap[3]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[3]), + .ZN(n_1_0_724) + ); + SDFF_X1_LVT \registers_reg[16][3] ( + .CK(n_0_46), .D(registers[3]), .Q(registers_16__ap[3]), .QN(), .SE(dftIn), + .SI(registers_10__ap[3]) + ); + SDFF_X1_LVT \registers_reg[3][3] ( + .CK(n_0_33), .D(registers[3]), .Q(registers_3__ap[3]), .QN(), .SE(dftIn), + .SI(registers_6__ap[3]) + ); + AOI22_X1_LVT i_1_0_759( + .A1(registers_16__ap[3]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[3]), + .ZN(n_1_0_723) + ); + SDFF_X1_LVT \registers_reg[5][3] ( + .CK(n_0_35), .D(registers[3]), .Q(registers_5__ap[3]), .QN(), .SE(dftIn), + .SI(registers_3__ap[3]) + ); + SDFF_X1_LVT \registers_reg[31][3] ( + .CK(n_0_61), .D(registers[3]), .Q(registers_31__ap[3]), .QN(), .SE(dftIn), + .SI(registers_5__ap[3]) + ); + AOI22_X1_LVT i_1_0_758( + .A1(registers_5__ap[3]), .A2(n_1_0_1273), .B1(n_1_0_1266), .B2(registers_31__ap[3]), + .ZN(n_1_0_722) + ); + SDFF_X1_LVT \registers_reg[15][3] ( + .CK(n_0_45), .D(registers[3]), .Q(registers_15__ap[3]), .QN(), .SE(dftIn), + .SI(registers_16__ap[3]) + ); + SDFF_X1_LVT \registers_reg[23][3] ( + .CK(n_0_53), .D(registers[3]), .Q(registers_23__ap[3]), .QN(), .SE(dftIn), + .SI(registers_1__ap[3]) + ); + AOI22_X1_LVT i_1_0_757( + .A1(registers_15__ap[3]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[3]), + .ZN(n_1_0_721) + ); + NAND4_X1_LVT i_1_0_756( + .A1(n_1_0_724), .A2(n_1_0_723), .A3(n_1_0_722), .A4(n_1_0_721), .ZN(n_1_0_720) + ); + SDFF_X1_LVT \registers_reg[18][3] ( + .CK(n_0_48), .D(registers[3]), .Q(registers_18__ap[3]), .QN(), .SE(dftIn), + .SI(registers_23__ap[3]) + ); + SDFF_X1_LVT \registers_reg[30][3] ( + .CK(n_0_60), .D(registers[3]), .Q(registers_30__ap[3]), .QN(), .SE(dftIn), + .SI(registers_29__ap[3]) + ); + AOI22_X1_LVT i_1_0_755( + .A1(registers_18__ap[3]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[3]), + .ZN(n_1_0_719) + ); + SDFF_X1_LVT \registers_reg[20][3] ( + .CK(n_0_50), .D(registers[3]), .Q(registers_20__ap[3]), .QN(), .SE(dftIn), + .SI(registers_18__ap[3]) + ); + SDFF_X1_LVT \registers_reg[4][3] ( + .CK(n_0_34), .D(registers[3]), .Q(registers_4__ap[3]), .QN(), .SE(dftIn), + .SI(registers_31__ap[3]) + ); + AOI22_X1_LVT i_1_0_754( + .A1(registers_20__ap[3]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[3]), + .ZN(n_1_0_718) + ); + SDFF_X1_LVT \registers_reg[22][3] ( + .CK(n_0_52), .D(registers[3]), .Q(registers_22__ap[3]), .QN(), .SE(dftIn), + .SI(registers_20__ap[3]) + ); + SDFF_X1_LVT \registers_reg[21][3] ( + .CK(n_0_51), .D(registers[3]), .Q(registers_21__ap[3]), .QN(), .SE(dftIn), + .SI(registers_22__ap[3]) + ); + AOI22_X1_LVT i_1_0_753( + .A1(registers_22__ap[3]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[3]), + .ZN(n_1_0_717) + ); + SDFF_X1_LVT \registers_reg[24][3] ( + .CK(n_0_54), .D(registers[3]), .Q(registers_24__ap[3]), .QN(), .SE(dftIn), + .SI(registers_30__ap[3]) + ); + SDFF_X1_LVT \registers_reg[12][3] ( + .CK(n_0_42), .D(registers[3]), .Q(registers_12__ap[3]), .QN(), .SE(dftIn), + .SI(registers_15__ap[3]) + ); + AOI22_X1_LVT i_1_0_752( + .A1(registers_24__ap[3]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[3]), + .ZN(n_1_0_716) + ); + NAND4_X1_LVT i_1_0_751( + .A1(n_1_0_719), .A2(n_1_0_718), .A3(n_1_0_717), .A4(n_1_0_716), .ZN(n_1_0_715) + ); + SDFF_X1_LVT \registers_reg[13][3] ( + .CK(n_0_43), .D(registers[3]), .Q(registers_13__ap[3]), .QN(), .SE(dftIn), + .SI(registers_12__ap[3]) + ); + SDFF_X1_LVT \registers_reg[25][3] ( + .CK(n_0_55), .D(registers[3]), .Q(registers_25__ap[3]), .QN(), .SE(dftIn), + .SI(registers_24__ap[3]) + ); + AOI22_X1_LVT i_1_0_750( + .A1(registers_13__ap[3]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[3]), + .ZN(n_1_0_714) + ); + SDFF_X1_LVT \registers_reg[19][3] ( + .CK(n_0_49), .D(registers[3]), .Q(registers_19__ap[3]), .QN(), .SE(dftIn), + .SI(registers_21__ap[3]) + ); + SDFF_X1_LVT \registers_reg[2][3] ( + .CK(n_0_32), .D(registers[3]), .Q(registers_2__ap[3]), .QN(), .SE(dftIn), + .SI(registers_25__ap[3]) + ); + AOI22_X1_LVT i_1_0_749( + .A1(registers_19__ap[3]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[3]), + .ZN(n_1_0_713) + ); + SDFF_X1_LVT \registers_reg[7][3] ( + .CK(n_0_37), .D(registers[3]), .Q(registers_7__ap[3]), .QN(), .SE(dftIn), + .SI(registers_4__ap[3]) + ); + SDFF_X1_LVT \registers_reg[14][3] ( + .CK(n_0_44), .D(registers[3]), .Q(registers_14__ap[3]), .QN(), .SE(dftIn), + .SI(registers_13__ap[3]) + ); + AOI22_X1_LVT i_1_0_748( + .A1(registers_7__ap[3]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[3]), + .ZN(n_1_0_712) + ); + SDFF_X1_LVT \registers_reg[27][3] ( + .CK(n_0_57), .D(registers[3]), .Q(registers_27__ap[3]), .QN(), .SE(dftIn), + .SI(registers_2__ap[3]) + ); + SDFF_X1_LVT \registers_reg[11][3] ( + .CK(n_0_41), .D(registers[3]), .Q(registers_11__ap[3]), .QN(), .SE(dftIn), + .SI(registers_14__ap[3]) + ); + AOI22_X1_LVT i_1_0_747( + .A1(registers_27__ap[3]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[3]), + .ZN(n_1_0_711) + ); + NAND4_X1_LVT i_1_0_746( + .A1(n_1_0_714), .A2(n_1_0_713), .A3(n_1_0_712), .A4(n_1_0_711), .ZN(n_1_0_710) + ); + NOR3_X1_LVT i_1_0_745( + .A1(n_1_0_720), .A2(n_1_0_715), .A3(n_1_0_710), .ZN(n_1_0_709) + ); + NAND4_X1_LVT i_1_0_744( + .A1(n_1_0_727), .A2(n_1_0_726), .A3(n_1_0_725), .A4(n_1_0_709), .ZN(RRs1[3]) + ); + AND2_X1_LVT i_0_0_2( + .A1(n_0_0_16), .A2(WRd[2]), .ZN(registers[2]) + ); + SDFF_X1_LVT \registers_reg[28][2] ( + .CK(n_0_58), .D(registers[2]), .Q(registers_28__ap[2]), .QN(), .SE(dftIn), + .SI(registers_27__ap[3]) + ); + SDFF_X1_LVT \registers_reg[4][2] ( + .CK(n_0_34), .D(registers[2]), .Q(registers_4__ap[2]), .QN(), .SE(dftIn), + .SI(registers_7__ap[3]) + ); + AOI22_X1_LVT i_1_0_740( + .A1(registers_28__ap[2]), .A2(n_1_0_1283), .B1(n_1_0_1278), .B2(registers_4__ap[2]), + .ZN(n_1_0_705) + ); + SDFF_X1_LVT \registers_reg[16][2] ( + .CK(n_0_46), .D(registers[2]), .Q(registers_16__ap[2]), .QN(), .SE(dftIn), + .SI(registers_11__ap[3]) + ); + SDFF_X1_LVT \registers_reg[31][2] ( + .CK(n_0_61), .D(registers[2]), .Q(registers_31__ap[2]), .QN(), .SE(dftIn), + .SI(registers_4__ap[2]) + ); + AOI22_X1_LVT i_1_0_743( + .A1(registers_16__ap[2]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[2]), + .ZN(n_1_0_708) + ); + SDFF_X1_LVT \registers_reg[6][2] ( + .CK(n_0_36), .D(registers[2]), .Q(registers_6__ap[2]), .QN(), .SE(dftIn), + .SI(registers_31__ap[2]) + ); + SDFF_X1_LVT \registers_reg[1][2] ( + .CK(n_0_0), .D(registers[2]), .Q(registers_1__ap[2]), .QN(), .SE(dftIn), + .SI(registers_19__ap[3]) + ); + AOI22_X1_LVT i_1_0_739( + .A1(registers_6__ap[2]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[2]), + .ZN(n_1_0_704) + ); + SDFF_X1_LVT \registers_reg[15][2] ( + .CK(n_0_45), .D(registers[2]), .Q(registers_15__ap[2]), .QN(), .SE(dftIn), + .SI(registers_16__ap[2]) + ); + SDFF_X1_LVT \registers_reg[27][2] ( + .CK(n_0_57), .D(registers[2]), .Q(registers_27__ap[2]), .QN(), .SE(dftIn), + .SI(registers_28__ap[2]) + ); + AOI22_X1_LVT i_1_0_742( + .A1(registers_15__ap[2]), .A2(n_1_0_1286), .B1(n_1_0_1279), .B2(registers_27__ap[2]), + .ZN(n_1_0_707) + ); + INV_X1_LVT i_1_0_741( + .A(n_1_0_707), .ZN(n_1_0_706) + ); + SDFF_X1_LVT \registers_reg[11][2] ( + .CK(n_0_41), .D(registers[2]), .Q(registers_11__ap[2]), .QN(), .SE(dftIn), + .SI(registers_15__ap[2]) + ); + SDFF_X1_LVT \registers_reg[5][2] ( + .CK(n_0_35), .D(registers[2]), .Q(registers_5__ap[2]), .QN(), .SE(dftIn), + .SI(registers_6__ap[2]) + ); + AOI221_X1_LVT i_1_0_738( + .A(n_1_0_706), .B1(n_1_0_1270), .B2(registers_11__ap[2]), .C1(registers_5__ap[2]), + .C2(n_1_0_1273), .ZN(n_1_0_703) + ); + SDFF_X1_LVT \registers_reg[10][2] ( + .CK(n_0_40), .D(registers[2]), .Q(registers_10__ap[2]), .QN(), .SE(dftIn), + .SI(registers_11__ap[2]) + ); + SDFF_X1_LVT \registers_reg[30][2] ( + .CK(n_0_60), .D(registers[2]), .Q(registers_30__ap[2]), .QN(), .SE(dftIn), + .SI(registers_27__ap[2]) + ); + SDFF_X1_LVT \registers_reg[8][2] ( + .CK(n_0_38), .D(registers[2]), .Q(registers_8__ap[2]), .QN(), .SE(dftIn), + .SI(registers_5__ap[2]) + ); + AOI222_X1_LVT i_1_0_737( + .A1(registers_10__ap[2]), .A2(n_1_0_1287), .B1(n_1_0_1272), .B2(registers_30__ap[2]), + .C1(n_1_0_1282), .C2(registers_8__ap[2]), .ZN(n_1_0_702) + ); + NAND4_X1_LVT i_1_0_736( + .A1(n_1_0_708), .A2(n_1_0_704), .A3(n_1_0_703), .A4(n_1_0_702), .ZN(n_1_0_701) + ); + SDFF_X1_LVT \registers_reg[9][2] ( + .CK(n_0_39), .D(registers[2]), .Q(registers_9__ap[2]), .QN(), .SE(dftIn), + .SI(registers_8__ap[2]) + ); + SDFF_X1_LVT \registers_reg[29][2] ( + .CK(n_0_59), .D(registers[2]), .Q(registers_29__ap[2]), .QN(), .SE(dftIn), + .SI(registers_30__ap[2]) + ); + AOI221_X1_LVT i_1_0_735( + .A(n_1_0_701), .B1(n_1_0_1291), .B2(registers_9__ap[2]), .C1(registers_29__ap[2]), + .C2(n_1_0_1276), .ZN(n_1_0_700) + ); + SDFF_X1_LVT \registers_reg[18][2] ( + .CK(n_0_48), .D(registers[2]), .Q(registers_18__ap[2]), .QN(), .SE(dftIn), + .SI(registers_1__ap[2]) + ); + SDFF_X1_LVT \registers_reg[26][2] ( + .CK(n_0_56), .D(registers[2]), .Q(registers_26__ap[2]), .QN(), .SE(dftIn), + .SI(registers_29__ap[2]) + ); + AOI22_X1_LVT i_1_0_734( + .A1(registers_18__ap[2]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[2]), + .ZN(n_1_0_699) + ); + SDFF_X1_LVT \registers_reg[24][2] ( + .CK(n_0_54), .D(registers[2]), .Q(registers_24__ap[2]), .QN(), .SE(dftIn), + .SI(registers_26__ap[2]) + ); + SDFF_X1_LVT \registers_reg[12][2] ( + .CK(n_0_42), .D(registers[2]), .Q(registers_12__ap[2]), .QN(), .SE(dftIn), + .SI(registers_10__ap[2]) + ); + AOI22_X1_LVT i_1_0_733( + .A1(registers_24__ap[2]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[2]), + .ZN(n_1_0_698) + ); + SDFF_X1_LVT \registers_reg[22][2] ( + .CK(n_0_52), .D(registers[2]), .Q(registers_22__ap[2]), .QN(), .SE(dftIn), + .SI(registers_18__ap[2]) + ); + SDFF_X1_LVT \registers_reg[21][2] ( + .CK(n_0_51), .D(registers[2]), .Q(registers_21__ap[2]), .QN(), .SE(dftIn), + .SI(registers_22__ap[2]) + ); + AOI22_X1_LVT i_1_0_732( + .A1(registers_22__ap[2]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[2]), + .ZN(n_1_0_697) + ); + NAND3_X1_LVT i_1_0_731( + .A1(n_1_0_699), .A2(n_1_0_698), .A3(n_1_0_697), .ZN(n_1_0_696) + ); + SDFF_X1_LVT \registers_reg[17][2] ( + .CK(n_0_47), .D(registers[2]), .Q(registers_17__ap[2]), .QN(), .SE(dftIn), + .SI(registers_21__ap[2]) + ); + SDFF_X1_LVT \registers_reg[20][2] ( + .CK(n_0_50), .D(registers[2]), .Q(registers_20__ap[2]), .QN(), .SE(dftIn), + .SI(registers_17__ap[2]) + ); + AOI221_X1_LVT i_1_0_730( + .A(n_1_0_696), .B1(n_1_0_1271), .B2(registers_17__ap[2]), .C1(registers_20__ap[2]), + .C2(n_1_0_1281), .ZN(n_1_0_695) + ); + SDFF_X1_LVT \registers_reg[13][2] ( + .CK(n_0_43), .D(registers[2]), .Q(registers_13__ap[2]), .QN(), .SE(dftIn), + .SI(registers_12__ap[2]) + ); + SDFF_X1_LVT \registers_reg[25][2] ( + .CK(n_0_55), .D(registers[2]), .Q(registers_25__ap[2]), .QN(), .SE(dftIn), + .SI(registers_24__ap[2]) + ); + AOI22_X1_LVT i_1_0_729( + .A1(registers_13__ap[2]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[2]), + .ZN(n_1_0_694) + ); + SDFF_X1_LVT \registers_reg[7][2] ( + .CK(n_0_37), .D(registers[2]), .Q(registers_7__ap[2]), .QN(), .SE(dftIn), + .SI(registers_9__ap[2]) + ); + SDFF_X1_LVT \registers_reg[14][2] ( + .CK(n_0_44), .D(registers[2]), .Q(registers_14__ap[2]), .QN(), .SE(dftIn), + .SI(registers_13__ap[2]) + ); + AOI22_X1_LVT i_1_0_728( + .A1(registers_7__ap[2]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[2]), + .ZN(n_1_0_693) + ); + SDFF_X1_LVT \registers_reg[19][2] ( + .CK(n_0_49), .D(registers[2]), .Q(registers_19__ap[2]), .QN(), .SE(dftIn), + .SI(registers_20__ap[2]) + ); + SDFF_X1_LVT \registers_reg[3][2] ( + .CK(n_0_33), .D(registers[2]), .Q(registers_3__ap[2]), .QN(), .SE(dftIn), + .SI(registers_7__ap[2]) + ); + AOI22_X1_LVT i_1_0_727( + .A1(registers_19__ap[2]), .A2(n_1_0_1295), .B1(n_1_0_1257), .B2(registers_3__ap[2]), + .ZN(n_1_0_692) + ); + NAND3_X1_LVT i_1_0_726( + .A1(n_1_0_694), .A2(n_1_0_693), .A3(n_1_0_692), .ZN(n_1_0_691) + ); + SDFF_X1_LVT \registers_reg[23][2] ( + .CK(n_0_53), .D(registers[2]), .Q(registers_23__ap[2]), .QN(), .SE(dftIn), + .SI(registers_19__ap[2]) + ); + SDFF_X1_LVT \registers_reg[2][2] ( + .CK(n_0_32), .D(registers[2]), .Q(registers_2__ap[2]), .QN(), .SE(dftIn), + .SI(registers_25__ap[2]) + ); + AOI221_X1_LVT i_1_0_725( + .A(n_1_0_691), .B1(n_1_0_1264), .B2(registers_23__ap[2]), .C1(registers_2__ap[2]), + .C2(n_1_0_1268), .ZN(n_1_0_690) + ); + NAND4_X1_LVT i_1_0_724( + .A1(n_1_0_705), .A2(n_1_0_700), .A3(n_1_0_695), .A4(n_1_0_690), .ZN(RRs1[2]) + ); + AND2_X1_LVT i_0_0_1( + .A1(n_0_0_16), .A2(WRd[1]), .ZN(registers[1]) + ); + SDFF_X1_LVT \registers_reg[13][1] ( + .CK(n_0_43), .D(registers[1]), .Q(registers_13__ap[1]), .QN(), .SE(dftIn), + .SI(registers_14__ap[2]) + ); + SDFF_X1_LVT \registers_reg[21][1] ( + .CK(n_0_51), .D(registers[1]), .Q(registers_21__ap[1]), .QN(), .SE(dftIn), + .SI(registers_23__ap[2]) + ); + AOI22_X1_LVT i_1_0_720( + .A1(registers_13__ap[1]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[1]), + .ZN(n_1_0_686) + ); + SDFF_X1_LVT \registers_reg[29][1] ( + .CK(n_0_59), .D(registers[1]), .Q(registers_29__ap[1]), .QN(), .SE(dftIn), + .SI(registers_2__ap[2]) + ); + SDFF_X1_LVT \registers_reg[23][1] ( + .CK(n_0_53), .D(registers[1]), .Q(registers_23__ap[1]), .QN(), .SE(dftIn), + .SI(registers_21__ap[1]) + ); + AOI22_X1_LVT i_1_0_723( + .A1(registers_29__ap[1]), .A2(n_1_0_1276), .B1(n_1_0_1264), .B2(registers_23__ap[1]), + .ZN(n_1_0_689) + ); + SDFF_X1_LVT \registers_reg[24][1] ( + .CK(n_0_54), .D(registers[1]), .Q(registers_24__ap[1]), .QN(), .SE(dftIn), + .SI(registers_29__ap[1]) + ); + SDFF_X1_LVT \registers_reg[20][1] ( + .CK(n_0_50), .D(registers[1]), .Q(registers_20__ap[1]), .QN(), .SE(dftIn), + .SI(registers_23__ap[1]) + ); + AOI22_X1_LVT i_1_0_719( + .A1(registers_24__ap[1]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[1]), + .ZN(n_1_0_685) + ); + SDFF_X1_LVT \registers_reg[7][1] ( + .CK(n_0_37), .D(registers[1]), .Q(registers_7__ap[1]), .QN(), .SE(dftIn), + .SI(registers_3__ap[2]) + ); + SDFF_X1_LVT \registers_reg[3][1] ( + .CK(n_0_33), .D(registers[1]), .Q(registers_3__ap[1]), .QN(), .SE(dftIn), + .SI(registers_7__ap[1]) + ); + AOI22_X1_LVT i_1_0_722( + .A1(registers_7__ap[1]), .A2(n_1_0_1263), .B1(n_1_0_1257), .B2(registers_3__ap[1]), + .ZN(n_1_0_688) + ); + INV_X1_LVT i_1_0_721( + .A(n_1_0_688), .ZN(n_1_0_687) + ); + SDFF_X1_LVT \registers_reg[31][1] ( + .CK(n_0_61), .D(registers[1]), .Q(registers_31__ap[1]), .QN(), .SE(dftIn), + .SI(registers_3__ap[1]) + ); + SDFF_X1_LVT \registers_reg[4][1] ( + .CK(n_0_34), .D(registers[1]), .Q(registers_4__ap[1]), .QN(), .SE(dftIn), + .SI(registers_31__ap[1]) + ); + AOI221_X1_LVT i_1_0_718( + .A(n_1_0_687), .B1(n_1_0_1266), .B2(registers_31__ap[1]), .C1(registers_4__ap[1]), + .C2(n_1_0_1278), .ZN(n_1_0_684) + ); + SDFF_X1_LVT \registers_reg[10][1] ( + .CK(n_0_40), .D(registers[1]), .Q(registers_10__ap[1]), .QN(), .SE(dftIn), + .SI(registers_13__ap[1]) + ); + SDFF_X1_LVT \registers_reg[26][1] ( + .CK(n_0_56), .D(registers[1]), .Q(registers_26__ap[1]), .QN(), .SE(dftIn), + .SI(registers_24__ap[1]) + ); + SDFF_X1_LVT \registers_reg[25][1] ( + .CK(n_0_55), .D(registers[1]), .Q(registers_25__ap[1]), .QN(), .SE(dftIn), + .SI(registers_26__ap[1]) + ); + AOI222_X1_LVT i_1_0_717( + .A1(registers_10__ap[1]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[1]), + .C1(registers_25__ap[1]), .C2(n_1_0_1269), .ZN(n_1_0_683) + ); + NAND4_X1_LVT i_1_0_716( + .A1(n_1_0_689), .A2(n_1_0_685), .A3(n_1_0_684), .A4(n_1_0_683), .ZN(n_1_0_682) + ); + SDFF_X1_LVT \registers_reg[8][1] ( + .CK(n_0_38), .D(registers[1]), .Q(registers_8__ap[1]), .QN(), .SE(dftIn), + .SI(registers_4__ap[1]) + ); + SDFF_X1_LVT \registers_reg[28][1] ( + .CK(n_0_58), .D(registers[1]), .Q(registers_28__ap[1]), .QN(), .SE(dftIn), + .SI(registers_25__ap[1]) + ); + AOI221_X1_LVT i_1_0_715( + .A(n_1_0_682), .B1(n_1_0_1282), .B2(registers_8__ap[1]), .C1(registers_28__ap[1]), + .C2(n_1_0_1283), .ZN(n_1_0_681) + ); + SDFF_X1_LVT \registers_reg[18][1] ( + .CK(n_0_48), .D(registers[1]), .Q(registers_18__ap[1]), .QN(), .SE(dftIn), + .SI(registers_20__ap[1]) + ); + SDFF_X1_LVT \registers_reg[30][1] ( + .CK(n_0_60), .D(registers[1]), .Q(registers_30__ap[1]), .QN(), .SE(dftIn), + .SI(registers_28__ap[1]) + ); + AOI22_X1_LVT i_1_0_714( + .A1(registers_18__ap[1]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[1]), + .ZN(n_1_0_680) + ); + SDFF_X1_LVT \registers_reg[17][1] ( + .CK(n_0_47), .D(registers[1]), .Q(registers_17__ap[1]), .QN(), .SE(dftIn), + .SI(registers_18__ap[1]) + ); + SDFF_X1_LVT \registers_reg[12][1] ( + .CK(n_0_42), .D(registers[1]), .Q(registers_12__ap[1]), .QN(), .SE(dftIn), + .SI(registers_10__ap[1]) + ); + AOI22_X1_LVT i_1_0_713( + .A1(registers_17__ap[1]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[1]), + .ZN(n_1_0_679) + ); + SDFF_X1_LVT \registers_reg[15][1] ( + .CK(n_0_45), .D(registers[1]), .Q(registers_15__ap[1]), .QN(), .SE(dftIn), + .SI(registers_12__ap[1]) + ); + SDFF_X1_LVT \registers_reg[5][1] ( + .CK(n_0_35), .D(registers[1]), .Q(registers_5__ap[1]), .QN(), .SE(dftIn), + .SI(registers_8__ap[1]) + ); + AOI22_X1_LVT i_1_0_712( + .A1(registers_15__ap[1]), .A2(n_1_0_1286), .B1(n_1_0_1273), .B2(registers_5__ap[1]), + .ZN(n_1_0_678) + ); + NAND3_X1_LVT i_1_0_711( + .A1(n_1_0_680), .A2(n_1_0_679), .A3(n_1_0_678), .ZN(n_1_0_677) + ); + SDFF_X1_LVT \registers_reg[22][1] ( + .CK(n_0_52), .D(registers[1]), .Q(registers_22__ap[1]), .QN(), .SE(dftIn), + .SI(registers_17__ap[1]) + ); + SDFF_X1_LVT \registers_reg[16][1] ( + .CK(n_0_46), .D(registers[1]), .Q(registers_16__ap[1]), .QN(), .SE(dftIn), + .SI(registers_15__ap[1]) + ); + AOI221_X1_LVT i_1_0_710( + .A(n_1_0_677), .B1(n_1_0_1294), .B2(registers_22__ap[1]), .C1(registers_16__ap[1]), + .C2(n_1_0_1267), .ZN(n_1_0_676) + ); + SDFF_X1_LVT \registers_reg[9][1] ( + .CK(n_0_39), .D(registers[1]), .Q(registers_9__ap[1]), .QN(), .SE(dftIn), + .SI(registers_5__ap[1]) + ); + SDFF_X1_LVT \registers_reg[1][1] ( + .CK(n_0_0), .D(registers[1]), .Q(registers_1__ap[1]), .QN(), .SE(dftIn), + .SI(registers_22__ap[1]) + ); + AOI22_X1_LVT i_1_0_709( + .A1(registers_9__ap[1]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[1]), + .ZN(n_1_0_675) + ); + SDFF_X1_LVT \registers_reg[6][1] ( + .CK(n_0_36), .D(registers[1]), .Q(registers_6__ap[1]), .QN(), .SE(dftIn), + .SI(registers_9__ap[1]) + ); + SDFF_X1_LVT \registers_reg[14][1] ( + .CK(n_0_44), .D(registers[1]), .Q(registers_14__ap[1]), .QN(), .SE(dftIn), + .SI(registers_16__ap[1]) + ); + AOI22_X1_LVT i_1_0_708( + .A1(registers_6__ap[1]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[1]), + .ZN(n_1_0_674) + ); + SDFF_X1_LVT \registers_reg[19][1] ( + .CK(n_0_49), .D(registers[1]), .Q(registers_19__ap[1]), .QN(), .SE(dftIn), + .SI(registers_1__ap[1]) + ); + SDFF_X1_LVT \registers_reg[2][1] ( + .CK(n_0_32), .D(registers[1]), .Q(registers_2__ap[1]), .QN(), .SE(dftIn), + .SI(registers_30__ap[1]) + ); + AOI22_X1_LVT i_1_0_707( + .A1(registers_19__ap[1]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[1]), + .ZN(n_1_0_673) + ); + NAND3_X1_LVT i_1_0_706( + .A1(n_1_0_675), .A2(n_1_0_674), .A3(n_1_0_673), .ZN(n_1_0_672) + ); + SDFF_X1_LVT \registers_reg[11][1] ( + .CK(n_0_41), .D(registers[1]), .Q(registers_11__ap[1]), .QN(), .SE(dftIn), + .SI(registers_14__ap[1]) + ); + SDFF_X1_LVT \registers_reg[27][1] ( + .CK(n_0_57), .D(registers[1]), .Q(registers_27__ap[1]), .QN(), .SE(dftIn), + .SI(registers_2__ap[1]) + ); + AOI221_X1_LVT i_1_0_705( + .A(n_1_0_672), .B1(n_1_0_1270), .B2(registers_11__ap[1]), .C1(registers_27__ap[1]), + .C2(n_1_0_1279), .ZN(n_1_0_671) + ); + NAND4_X1_LVT i_1_0_704( + .A1(n_1_0_686), .A2(n_1_0_681), .A3(n_1_0_676), .A4(n_1_0_671), .ZN(RRs1[1]) + ); + AND2_X1_LVT i_0_0_0( + .A1(n_0_0_16), .A2(WRd[0]), .ZN(registers[0]) + ); + SDFF_X1_LVT \registers_reg[13][0] ( + .CK(n_0_43), .D(registers[0]), .Q(registers_13__ap[0]), .QN(), .SE(dftIn), + .SI(registers_11__ap[1]) + ); + SDFF_X1_LVT \registers_reg[21][0] ( + .CK(n_0_51), .D(registers[0]), .Q(registers_21__ap[0]), .QN(), .SE(dftIn), + .SI(registers_19__ap[1]) + ); + AOI22_X1_LVT i_1_0_703( + .A1(registers_13__ap[0]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[0]), + .ZN(n_1_0_670) + ); + SDFF_X1_LVT \registers_reg[10][0] ( + .CK(n_0_40), .D(registers[0]), .Q(registers_10__ap[0]), .QN(), .SE(dftIn), + .SI(registers_13__ap[0]) + ); + SDFF_X1_LVT \registers_reg[26][0] ( + .CK(n_0_56), .D(registers[0]), .Q(registers_26__ap[0]), .QN(), .SE(dftIn), + .SI(registers_27__ap[1]) + ); + SDFF_X1_LVT \registers_reg[25][0] ( + .CK(n_0_55), .D(registers[0]), .Q(registers_25__ap[0]), .QN(), .SE(dftIn), + .SI(registers_26__ap[0]) + ); + AOI222_X1_LVT i_1_0_702( + .A1(registers_10__ap[0]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[0]), + .C1(registers_25__ap[0]), .C2(n_1_0_1269), .ZN(n_1_0_669) + ); + SDFF_X1_LVT \registers_reg[28][0] ( + .CK(n_0_58), .D(registers[0]), .Q(registers_28__ap[0]), .QN(), .SE(dftIn), + .SI(registers_25__ap[0]) + ); + SDFF_X1_LVT \registers_reg[8][0] ( + .CK(n_0_38), .D(registers[0]), .Q(registers_8__ap[0]), .QN(), .SE(dftIn), + .SI(registers_6__ap[1]) + ); + AOI22_X1_LVT i_1_0_701( + .A1(registers_28__ap[0]), .A2(n_1_0_1283), .B1(n_1_0_1282), .B2(registers_8__ap[0]), + .ZN(n_1_0_668) + ); + SDFF_X1_LVT \registers_reg[24][0] ( + .CK(n_0_54), .D(registers[0]), .Q(registers_24__ap[0]), .QN(), .SE(dftIn), + .SI(registers_28__ap[0]) + ); + SDFF_X1_LVT \registers_reg[20][0] ( + .CK(n_0_50), .D(registers[0]), .Q(registers_20__ap[0]), .QN(), .SE(dftIn), + .SI(registers_21__ap[0]) + ); + AOI22_X1_LVT i_1_0_700( + .A1(registers_24__ap[0]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[0]), + .ZN(n_1_0_667) + ); + SDFF_X1_LVT \registers_reg[7][0] ( + .CK(n_0_37), .D(registers[0]), .Q(registers_7__ap[0]), .QN(), .SE(dftIn), + .SI(registers_8__ap[0]) + ); + SDFF_X1_LVT \registers_reg[3][0] ( + .CK(n_0_33), .D(registers[0]), .Q(registers_3__ap[0]), .QN(), .SE(dftIn), + .SI(registers_7__ap[0]) + ); + AOI22_X1_LVT i_1_0_699( + .A1(registers_7__ap[0]), .A2(n_1_0_1263), .B1(n_1_0_1257), .B2(registers_3__ap[0]), + .ZN(n_1_0_666) + ); + SDFF_X1_LVT \registers_reg[17][0] ( + .CK(n_0_47), .D(registers[0]), .Q(registers_17__ap[0]), .QN(), .SE(dftIn), + .SI(registers_20__ap[0]) + ); + SDFF_X1_LVT \registers_reg[31][0] ( + .CK(n_0_61), .D(registers[0]), .Q(registers_31__ap[0]), .QN(), .SE(dftIn), + .SI(registers_3__ap[0]) + ); + AOI22_X1_LVT i_1_0_698( + .A1(registers_17__ap[0]), .A2(n_1_0_1271), .B1(n_1_0_1266), .B2(registers_31__ap[0]), + .ZN(n_1_0_665) + ); + SDFF_X1_LVT \registers_reg[29][0] ( + .CK(n_0_59), .D(registers[0]), .Q(registers_29__ap[0]), .QN(), .SE(dftIn), + .SI(registers_24__ap[0]) + ); + SDFF_X1_LVT \registers_reg[23][0] ( + .CK(n_0_53), .D(registers[0]), .Q(registers_23__ap[0]), .QN(), .SE(dftIn), + .SI(registers_17__ap[0]) + ); + AOI22_X1_LVT i_1_0_697( + .A1(registers_29__ap[0]), .A2(n_1_0_1276), .B1(n_1_0_1264), .B2(registers_23__ap[0]), + .ZN(n_1_0_664) + ); + NAND4_X1_LVT i_1_0_696( + .A1(n_1_0_667), .A2(n_1_0_666), .A3(n_1_0_665), .A4(n_1_0_664), .ZN(n_1_0_663) + ); + SDFF_X1_LVT \registers_reg[18][0] ( + .CK(n_0_48), .D(registers[0]), .Q(registers_18__ap[0]), .QN(), .SE(dftIn), + .SI(registers_23__ap[0]) + ); + SDFF_X1_LVT \registers_reg[30][0] ( + .CK(n_0_60), .D(registers[0]), .Q(registers_30__ap[0]), .QN(), .SE(dftIn), + .SI(registers_29__ap[0]) + ); + AOI22_X1_LVT i_1_0_695( + .A1(registers_18__ap[0]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[0]), + .ZN(n_1_0_662) + ); + SDFF_X1_LVT \registers_reg[4][0] ( + .CK(n_0_34), .D(registers[0]), .Q(registers_4__ap[0]), .QN(), .SE(dftIn), + .SI(registers_31__ap[0]) + ); + SDFF_X1_LVT \registers_reg[12][0] ( + .CK(n_0_42), .D(registers[0]), .Q(registers_12__ap[0]), .QN(), .SE(dftIn), + .SI(registers_10__ap[0]) + ); + AOI22_X1_LVT i_1_0_694( + .A1(registers_4__ap[0]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[0]), + .ZN(n_1_0_661) + ); + SDFF_X1_LVT \registers_reg[15][0] ( + .CK(n_0_45), .D(registers[0]), .Q(registers_15__ap[0]), .QN(), .SE(dftIn), + .SI(registers_12__ap[0]) + ); + SDFF_X1_LVT \registers_reg[16][0] ( + .CK(n_0_46), .D(registers[0]), .Q(registers_16__ap[0]), .QN(), .SE(dftIn), + .SI(registers_15__ap[0]) + ); + AOI22_X1_LVT i_1_0_693( + .A1(registers_15__ap[0]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[0]), + .ZN(n_1_0_660) + ); + SDFF_X1_LVT \registers_reg[22][0] ( + .CK(n_0_52), .D(registers[0]), .Q(registers_22__ap[0]), .QN(), .SE(dftIn), + .SI(registers_18__ap[0]) + ); + SDFF_X1_LVT \registers_reg[5][0] ( + .CK(n_0_35), .D(registers[0]), .Q(registers_5__ap[0]), .QN(), .SE(dftIn), + .SI(registers_4__ap[0]) + ); + AOI22_X1_LVT i_1_0_692( + .A1(registers_22__ap[0]), .A2(n_1_0_1294), .B1(n_1_0_1273), .B2(registers_5__ap[0]), + .ZN(n_1_0_659) + ); + NAND4_X1_LVT i_1_0_691( + .A1(n_1_0_662), .A2(n_1_0_661), .A3(n_1_0_660), .A4(n_1_0_659), .ZN(n_1_0_658) + ); + SDFF_X1_LVT \registers_reg[19][0] ( + .CK(n_0_49), .D(registers[0]), .Q(registers_19__ap[0]), .QN(), .SE(dftIn), + .SI(registers_22__ap[0]) + ); + SDFF_X1_LVT \registers_reg[2][0] ( + .CK(n_0_32), .D(registers[0]), .Q(registers_2__ap[0]), .QN(), .SE(dftIn), + .SI(registers_30__ap[0]) + ); + AOI22_X1_LVT i_1_0_690( + .A1(registers_19__ap[0]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[0]), + .ZN(n_1_0_657) + ); + SDFF_X1_LVT \registers_reg[9][0] ( + .CK(n_0_39), .D(registers[0]), .Q(registers_9__ap[0]), .QN(), .SE(dftIn), + .SI(registers_5__ap[0]) + ); + SDFF_X1_LVT \registers_reg[1][0] ( + .CK(n_0_0), .D(registers[0]), .Q(registers_1__ap[0]), .QN(), .SE(dftIn), + .SI(registers_19__ap[0]) + ); + AOI22_X1_LVT i_1_0_689( + .A1(registers_9__ap[0]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[0]), + .ZN(n_1_0_656) + ); + SDFF_X1_LVT \registers_reg[6][0] ( + .CK(n_0_36), .D(registers[0]), .Q(registers_6__ap[0]), .QN(), .SE(dftIn), + .SI(registers_9__ap[0]) + ); + SDFF_X1_LVT \registers_reg[14][0] ( + .CK(n_0_44), .D(registers[0]), .Q(registers_14__ap[0]), .QN(), .SE(dftIn), + .SI(registers_16__ap[0]) + ); + AOI22_X1_LVT i_1_0_688( + .A1(registers_6__ap[0]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[0]), + .ZN(n_1_0_655) + ); + SDFF_X1_LVT \registers_reg[27][0] ( + .CK(n_0_57), .D(registers[0]), .Q(registers_27__ap[0]), .QN(), .SE(dftIn), + .SI(registers_2__ap[0]) + ); + SDFF_X1_LVT \registers_reg[11][0] ( + .CK(n_0_41), .D(registers[0]), .Q(registers_11__ap[0]), .QN(), .SE(dftIn), + .SI(registers_14__ap[0]) + ); + AOI22_X1_LVT i_1_0_687( + .A1(registers_27__ap[0]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[0]), + .ZN(n_1_0_654) + ); + NAND4_X1_LVT i_1_0_686( + .A1(n_1_0_657), .A2(n_1_0_656), .A3(n_1_0_655), .A4(n_1_0_654), .ZN(n_1_0_653) + ); + NOR3_X1_LVT i_1_0_685( + .A1(n_1_0_663), .A2(n_1_0_658), .A3(n_1_0_653), .ZN(n_1_0_652) + ); + NAND4_X1_LVT i_1_0_684( + .A1(n_1_0_670), .A2(n_1_0_669), .A3(n_1_0_668), .A4(n_1_0_652), .ZN(RRs1[0]) + ); + INV_X1_LVT i_1_0_1366( + .A(Rs2[1]), .ZN(n_1_0_1302) + ); + NAND3_X1_LVT i_1_0_683( + .A1(n_1_0_1302), .A2(Rs2[4]), .A3(Rs2[2]), .ZN(n_1_0_651) + ); + INV_X1_LVT i_1_0_1369( + .A(Rs2[3]), .ZN(n_1_0_1305) + ); + OR2_X1_LVT i_1_0_673( + .A1(n_1_0_1305), .A2(Rs2[0]), .ZN(n_1_0_641) + ); + NOR2_X1_LVT i_1_0_666( + .A1(n_1_0_651), .A2(n_1_0_641), .ZN(n_1_0_634) + ); + NAND2_X1_LVT i_1_0_677( + .A1(n_1_0_1305), .A2(Rs2[0]), .ZN(n_1_0_645) + ); + INV_X1_LVT i_1_0_1368( + .A(Rs2[2]), .ZN(n_1_0_1304) + ); + NAND3_X1_LVT i_1_0_662( + .A1(n_1_0_1304), .A2(n_1_0_1302), .A3(Rs2[4]), .ZN(n_1_0_630) + ); + NOR2_X1_LVT i_1_0_661( + .A1(n_1_0_645), .A2(n_1_0_630), .ZN(n_1_0_629) + ); + AOI22_X1_LVT i_1_0_641( + .A1(registers_28__ap[31]), .A2(n_1_0_634), .B1(n_1_0_629), .B2(registers_17__ap[31]), + .ZN(n_1_0_609) + ); + NAND3_X1_LVT i_1_0_680( + .A1(n_1_0_1304), .A2(Rs2[4]), .A3(Rs2[1]), .ZN(n_1_0_648) + ); + NOR2_X1_LVT i_1_0_672( + .A1(n_1_0_648), .A2(n_1_0_641), .ZN(n_1_0_640) + ); + INV_X1_LVT i_1_0_1367( + .A(Rs2[4]), .ZN(n_1_0_1303) + ); + NAND3_X1_LVT i_1_0_657( + .A1(n_1_0_1304), .A2(n_1_0_1303), .A3(Rs2[1]), .ZN(n_1_0_625) + ); + NOR2_X1_LVT i_1_0_656( + .A1(n_1_0_641), .A2(n_1_0_625), .ZN(n_1_0_624) + ); + NOR4_X1_LVT i_1_0_658( + .A1(n_1_0_641), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), .ZN(n_1_0_626) + ); + AOI222_X1_LVT i_1_0_640( + .A1(registers_26__ap[31]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[31]), + .C1(n_1_0_626), .C2(registers_8__ap[31]), .ZN(n_1_0_608) + ); + NAND2_X1_LVT i_1_0_682( + .A1(Rs2[0]), .A2(Rs2[3]), .ZN(n_1_0_650) + ); + NOR2_X1_LVT i_1_0_681( + .A1(n_1_0_651), .A2(n_1_0_650), .ZN(n_1_0_649) + ); + NOR4_X1_LVT i_1_0_649( + .A1(n_1_0_650), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), .ZN(n_1_0_617) + ); + AOI22_X1_LVT i_1_0_639( + .A1(registers_29__ap[31]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[31]), + .ZN(n_1_0_607) + ); + NOR4_X1_LVT i_1_0_676( + .A1(n_1_0_645), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), .ZN(n_1_0_644) + ); + OR2_X1_LVT i_1_0_679( + .A1(Rs2[0]), .A2(Rs2[3]), .ZN(n_1_0_647) + ); + NAND3_X1_LVT i_1_0_660( + .A1(n_1_0_1303), .A2(Rs2[1]), .A3(Rs2[2]), .ZN(n_1_0_628) + ); + NOR2_X1_LVT i_1_0_648( + .A1(n_1_0_647), .A2(n_1_0_628), .ZN(n_1_0_616) + ); + AOI22_X1_LVT i_1_0_638( + .A1(registers_1__ap[31]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[31]), + .ZN(n_1_0_606) + ); + NOR2_X1_LVT i_1_0_655( + .A1(n_1_0_645), .A2(n_1_0_628), .ZN(n_1_0_623) + ); + NAND3_X1_LVT i_1_0_675( + .A1(Rs2[2]), .A2(Rs2[4]), .A3(Rs2[1]), .ZN(n_1_0_643) + ); + NOR2_X1_LVT i_1_0_647( + .A1(n_1_0_645), .A2(n_1_0_643), .ZN(n_1_0_615) + ); + AOI22_X1_LVT i_1_0_637( + .A1(registers_7__ap[31]), .A2(n_1_0_623), .B1(n_1_0_615), .B2(registers_23__ap[31]), + .ZN(n_1_0_605) + ); + NOR2_X1_LVT i_1_0_665( + .A1(n_1_0_648), .A2(n_1_0_645), .ZN(n_1_0_633) + ); + NOR2_X1_LVT i_1_0_646( + .A1(n_1_0_647), .A2(n_1_0_630), .ZN(n_1_0_614) + ); + AOI22_X1_LVT i_1_0_636( + .A1(registers_19__ap[31]), .A2(n_1_0_633), .B1(n_1_0_614), .B2(registers_16__ap[31]), + .ZN(n_1_0_604) + ); + NOR2_X1_LVT i_1_0_669( + .A1(n_1_0_650), .A2(n_1_0_643), .ZN(n_1_0_637) + ); + NAND3_X1_LVT i_1_0_671( + .A1(n_1_0_1303), .A2(n_1_0_1302), .A3(Rs2[2]), .ZN(n_1_0_639) + ); + NOR2_X1_LVT i_1_0_667( + .A1(n_1_0_645), .A2(n_1_0_639), .ZN(n_1_0_635) + ); + AOI22_X1_LVT i_1_0_635( + .A1(registers_31__ap[31]), .A2(n_1_0_637), .B1(n_1_0_635), .B2(registers_5__ap[31]), + .ZN(n_1_0_603) + ); + NAND4_X1_LVT i_1_0_634( + .A1(n_1_0_606), .A2(n_1_0_605), .A3(n_1_0_604), .A4(n_1_0_603), .ZN(n_1_0_602) + ); + NOR2_X1_LVT i_1_0_678( + .A1(n_1_0_648), .A2(n_1_0_647), .ZN(n_1_0_646) + ); + NOR2_X1_LVT i_1_0_654( + .A1(n_1_0_643), .A2(n_1_0_641), .ZN(n_1_0_622) + ); + AOI22_X1_LVT i_1_0_633( + .A1(registers_18__ap[31]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[31]), + .ZN(n_1_0_601) + ); + NOR2_X1_LVT i_1_0_670( + .A1(n_1_0_647), .A2(n_1_0_639), .ZN(n_1_0_638) + ); + NOR2_X1_LVT i_1_0_645( + .A1(n_1_0_651), .A2(n_1_0_647), .ZN(n_1_0_613) + ); + AOI22_X1_LVT i_1_0_632( + .A1(registers_4__ap[31]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[31]), + .ZN(n_1_0_600) + ); + NOR2_X1_LVT i_1_0_674( + .A1(n_1_0_647), .A2(n_1_0_643), .ZN(n_1_0_642) + ); + NOR2_X1_LVT i_1_0_644( + .A1(n_1_0_651), .A2(n_1_0_645), .ZN(n_1_0_612) + ); + AOI22_X1_LVT i_1_0_631( + .A1(registers_22__ap[31]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[31]), + .ZN(n_1_0_599) + ); + NOR2_X1_LVT i_1_0_664( + .A1(n_1_0_641), .A2(n_1_0_639), .ZN(n_1_0_632) + ); + NOR2_X1_LVT i_1_0_653( + .A1(n_1_0_641), .A2(n_1_0_630), .ZN(n_1_0_621) + ); + AOI22_X1_LVT i_1_0_630( + .A1(registers_12__ap[31]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[31]), + .ZN(n_1_0_598) + ); + NAND4_X1_LVT i_1_0_629( + .A1(n_1_0_601), .A2(n_1_0_600), .A3(n_1_0_599), .A4(n_1_0_598), .ZN(n_1_0_597) + ); + NOR2_X1_LVT i_1_0_663( + .A1(n_1_0_650), .A2(n_1_0_639), .ZN(n_1_0_631) + ); + NOR2_X1_LVT i_1_0_652( + .A1(n_1_0_650), .A2(n_1_0_630), .ZN(n_1_0_620) + ); + AOI22_X1_LVT i_1_0_628( + .A1(registers_13__ap[31]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[31]), + .ZN(n_1_0_596) + ); + NOR2_X1_LVT i_1_0_659( + .A1(n_1_0_650), .A2(n_1_0_628), .ZN(n_1_0_627) + ); + NOR2_X1_LVT i_1_0_651( + .A1(n_1_0_641), .A2(n_1_0_628), .ZN(n_1_0_619) + ); + AOI22_X1_LVT i_1_0_627( + .A1(registers_15__ap[31]), .A2(n_1_0_627), .B1(n_1_0_619), .B2(registers_14__ap[31]), + .ZN(n_1_0_595) + ); + NOR2_X1_LVT i_1_0_668( + .A1(n_1_0_650), .A2(n_1_0_648), .ZN(n_1_0_636) + ); + NOR2_X1_LVT i_1_0_643( + .A1(n_1_0_650), .A2(n_1_0_625), .ZN(n_1_0_611) + ); + AOI22_X1_LVT i_1_0_626( + .A1(registers_27__ap[31]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[31]), + .ZN(n_1_0_594) + ); + NOR2_X1_LVT i_1_0_650( + .A1(n_1_0_647), .A2(n_1_0_625), .ZN(n_1_0_618) + ); + NOR2_X1_LVT i_1_0_642( + .A1(n_1_0_645), .A2(n_1_0_625), .ZN(n_1_0_610) + ); + AOI22_X1_LVT i_1_0_625( + .A1(registers_2__ap[31]), .A2(n_1_0_618), .B1(n_1_0_610), .B2(registers_3__ap[31]), + .ZN(n_1_0_593) + ); + NAND4_X1_LVT i_1_0_624( + .A1(n_1_0_596), .A2(n_1_0_595), .A3(n_1_0_594), .A4(n_1_0_593), .ZN(n_1_0_592) + ); + NOR3_X1_LVT i_1_0_623( + .A1(n_1_0_602), .A2(n_1_0_597), .A3(n_1_0_592), .ZN(n_1_0_591) + ); + NAND4_X1_LVT i_1_0_622( + .A1(n_1_0_609), .A2(n_1_0_608), .A3(n_1_0_607), .A4(n_1_0_591), .ZN(RRs2[31]) + ); + AOI22_X1_LVT i_1_0_620( + .A1(registers_29__ap[30]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[30]), + .ZN(n_1_0_589) + ); + AOI22_X1_LVT i_1_0_621( + .A1(registers_7__ap[30]), .A2(n_1_0_623), .B1(n_1_0_615), .B2(registers_23__ap[30]), + .ZN(n_1_0_590) + ); + AOI22_X1_LVT i_1_0_619( + .A1(registers_1__ap[30]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[30]), + .ZN(n_1_0_588) + ); + AOI22_X1_LVT i_1_0_618( + .A1(registers_5__ap[30]), .A2(n_1_0_635), .B1(n_1_0_633), .B2(registers_19__ap[30]), + .ZN(n_1_0_587) + ); + NAND3_X1_LVT i_1_0_617( + .A1(n_1_0_590), .A2(n_1_0_588), .A3(n_1_0_587), .ZN(n_1_0_586) + ); + AOI221_X1_LVT i_1_0_616( + .A(n_1_0_586), .B1(n_1_0_637), .B2(registers_31__ap[30]), .C1(registers_16__ap[30]), + .C2(n_1_0_614), .ZN(n_1_0_585) + ); + AOI222_X1_LVT i_1_0_615( + .A1(registers_26__ap[30]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[30]), + .C1(n_1_0_626), .C2(registers_8__ap[30]), .ZN(n_1_0_584) + ); + NAND3_X1_LVT i_1_0_614( + .A1(n_1_0_589), .A2(n_1_0_585), .A3(n_1_0_584), .ZN(n_1_0_583) + ); + AOI221_X1_LVT i_1_0_613( + .A(n_1_0_583), .B1(n_1_0_629), .B2(registers_17__ap[30]), .C1(registers_28__ap[30]), + .C2(n_1_0_634), .ZN(n_1_0_582) + ); + AOI22_X1_LVT i_1_0_612( + .A1(registers_18__ap[30]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[30]), + .ZN(n_1_0_581) + ); + AOI22_X1_LVT i_1_0_611( + .A1(registers_4__ap[30]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[30]), + .ZN(n_1_0_580) + ); + AOI22_X1_LVT i_1_0_610( + .A1(registers_22__ap[30]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[30]), + .ZN(n_1_0_579) + ); + NAND3_X1_LVT i_1_0_609( + .A1(n_1_0_581), .A2(n_1_0_580), .A3(n_1_0_579), .ZN(n_1_0_578) + ); + AOI221_X1_LVT i_1_0_608( + .A(n_1_0_578), .B1(n_1_0_621), .B2(registers_24__ap[30]), .C1(registers_12__ap[30]), + .C2(n_1_0_632), .ZN(n_1_0_577) + ); + AOI22_X1_LVT i_1_0_607( + .A1(registers_13__ap[30]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[30]), + .ZN(n_1_0_576) + ); + AOI22_X1_LVT i_1_0_606( + .A1(registers_15__ap[30]), .A2(n_1_0_627), .B1(n_1_0_619), .B2(registers_14__ap[30]), + .ZN(n_1_0_575) + ); + AOI22_X1_LVT i_1_0_605( + .A1(registers_27__ap[30]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[30]), + .ZN(n_1_0_574) + ); + NAND3_X1_LVT i_1_0_604( + .A1(n_1_0_576), .A2(n_1_0_575), .A3(n_1_0_574), .ZN(n_1_0_573) + ); + AOI221_X1_LVT i_1_0_603( + .A(n_1_0_573), .B1(n_1_0_610), .B2(registers_3__ap[30]), .C1(registers_2__ap[30]), + .C2(n_1_0_618), .ZN(n_1_0_572) + ); + NAND3_X1_LVT i_1_0_602( + .A1(n_1_0_582), .A2(n_1_0_577), .A3(n_1_0_572), .ZN(RRs2[30]) + ); + AOI22_X1_LVT i_1_0_600( + .A1(registers_28__ap[29]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[29]), + .ZN(n_1_0_570) + ); + AOI22_X1_LVT i_1_0_601( + .A1(registers_31__ap[29]), .A2(n_1_0_637), .B1(n_1_0_627), .B2(registers_15__ap[29]), + .ZN(n_1_0_571) + ); + AOI22_X1_LVT i_1_0_599( + .A1(registers_24__ap[29]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[29]), + .ZN(n_1_0_569) + ); + AOI22_X1_LVT i_1_0_598( + .A1(registers_19__ap[29]), .A2(n_1_0_633), .B1(n_1_0_629), .B2(registers_17__ap[29]), + .ZN(n_1_0_568) + ); + NAND3_X1_LVT i_1_0_597( + .A1(n_1_0_571), .A2(n_1_0_569), .A3(n_1_0_568), .ZN(n_1_0_567) + ); + AOI221_X1_LVT i_1_0_596( + .A(n_1_0_567), .B1(n_1_0_615), .B2(registers_23__ap[29]), .C1(registers_29__ap[29]), + .C2(n_1_0_649), .ZN(n_1_0_566) + ); + AOI222_X1_LVT i_1_0_595( + .A1(registers_26__ap[29]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[29]), + .C1(n_1_0_620), .C2(registers_25__ap[29]), .ZN(n_1_0_565) + ); + NAND3_X1_LVT i_1_0_594( + .A1(n_1_0_570), .A2(n_1_0_566), .A3(n_1_0_565), .ZN(n_1_0_564) + ); + AOI221_X1_LVT i_1_0_593( + .A(n_1_0_564), .B1(n_1_0_612), .B2(registers_21__ap[29]), .C1(registers_13__ap[29]), + .C2(n_1_0_631), .ZN(n_1_0_563) + ); + AOI22_X1_LVT i_1_0_592( + .A1(registers_18__ap[29]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[29]), + .ZN(n_1_0_562) + ); + AOI22_X1_LVT i_1_0_591( + .A1(registers_4__ap[29]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[29]), + .ZN(n_1_0_561) + ); + AOI22_X1_LVT i_1_0_590( + .A1(registers_7__ap[29]), .A2(n_1_0_623), .B1(n_1_0_614), .B2(registers_16__ap[29]), + .ZN(n_1_0_560) + ); + NAND3_X1_LVT i_1_0_589( + .A1(n_1_0_562), .A2(n_1_0_561), .A3(n_1_0_560), .ZN(n_1_0_559) + ); + AOI221_X1_LVT i_1_0_588( + .A(n_1_0_559), .B1(n_1_0_642), .B2(registers_22__ap[29]), .C1(registers_5__ap[29]), + .C2(n_1_0_635), .ZN(n_1_0_558) + ); + AOI22_X1_LVT i_1_0_587( + .A1(registers_1__ap[29]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[29]), + .ZN(n_1_0_557) + ); + AOI22_X1_LVT i_1_0_586( + .A1(registers_14__ap[29]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[29]), + .ZN(n_1_0_556) + ); + AOI22_X1_LVT i_1_0_585( + .A1(registers_27__ap[29]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[29]), + .ZN(n_1_0_555) + ); + NAND3_X1_LVT i_1_0_584( + .A1(n_1_0_557), .A2(n_1_0_556), .A3(n_1_0_555), .ZN(n_1_0_554) + ); + AOI221_X1_LVT i_1_0_583( + .A(n_1_0_554), .B1(n_1_0_610), .B2(registers_3__ap[29]), .C1(registers_2__ap[29]), + .C2(n_1_0_618), .ZN(n_1_0_553) + ); + NAND3_X1_LVT i_1_0_582( + .A1(n_1_0_563), .A2(n_1_0_558), .A3(n_1_0_553), .ZN(RRs2[29]) + ); + AOI22_X1_LVT i_1_0_581( + .A1(registers_5__ap[28]), .A2(n_1_0_635), .B1(n_1_0_634), .B2(registers_28__ap[28]), + .ZN(n_1_0_552) + ); + AOI222_X1_LVT i_1_0_580( + .A1(registers_26__ap[28]), .A2(n_1_0_640), .B1(n_1_0_633), .B2(registers_19__ap[28]), + .C1(n_1_0_626), .C2(registers_8__ap[28]), .ZN(n_1_0_551) + ); + AOI22_X1_LVT i_1_0_579( + .A1(registers_2__ap[28]), .A2(n_1_0_618), .B1(n_1_0_617), .B2(registers_9__ap[28]), + .ZN(n_1_0_550) + ); + AOI22_X1_LVT i_1_0_578( + .A1(registers_7__ap[28]), .A2(n_1_0_623), .B1(n_1_0_612), .B2(registers_21__ap[28]), + .ZN(n_1_0_549) + ); + AOI22_X1_LVT i_1_0_577( + .A1(registers_16__ap[28]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[28]), + .ZN(n_1_0_548) + ); + AOI22_X1_LVT i_1_0_576( + .A1(registers_31__ap[28]), .A2(n_1_0_637), .B1(n_1_0_619), .B2(registers_14__ap[28]), + .ZN(n_1_0_547) + ); + AOI22_X1_LVT i_1_0_575( + .A1(registers_15__ap[28]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[28]), + .ZN(n_1_0_546) + ); + NAND4_X1_LVT i_1_0_574( + .A1(n_1_0_549), .A2(n_1_0_548), .A3(n_1_0_547), .A4(n_1_0_546), .ZN(n_1_0_545) + ); + AOI22_X1_LVT i_1_0_573( + .A1(registers_22__ap[28]), .A2(n_1_0_642), .B1(n_1_0_622), .B2(registers_30__ap[28]), + .ZN(n_1_0_544) + ); + AOI22_X1_LVT i_1_0_572( + .A1(registers_4__ap[28]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[28]), + .ZN(n_1_0_543) + ); + AOI22_X1_LVT i_1_0_571( + .A1(registers_29__ap[28]), .A2(n_1_0_649), .B1(n_1_0_644), .B2(registers_1__ap[28]), + .ZN(n_1_0_542) + ); + AOI22_X1_LVT i_1_0_570( + .A1(registers_12__ap[28]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[28]), + .ZN(n_1_0_541) + ); + NAND4_X1_LVT i_1_0_569( + .A1(n_1_0_544), .A2(n_1_0_543), .A3(n_1_0_542), .A4(n_1_0_541), .ZN(n_1_0_540) + ); + AOI22_X1_LVT i_1_0_568( + .A1(registers_13__ap[28]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[28]), + .ZN(n_1_0_539) + ); + AOI22_X1_LVT i_1_0_567( + .A1(registers_17__ap[28]), .A2(n_1_0_629), .B1(n_1_0_616), .B2(registers_6__ap[28]), + .ZN(n_1_0_538) + ); + AOI22_X1_LVT i_1_0_566( + .A1(registers_10__ap[28]), .A2(n_1_0_624), .B1(n_1_0_615), .B2(registers_23__ap[28]), + .ZN(n_1_0_537) + ); + AOI22_X1_LVT i_1_0_565( + .A1(registers_18__ap[28]), .A2(n_1_0_646), .B1(n_1_0_636), .B2(registers_27__ap[28]), + .ZN(n_1_0_536) + ); + NAND4_X1_LVT i_1_0_564( + .A1(n_1_0_539), .A2(n_1_0_538), .A3(n_1_0_537), .A4(n_1_0_536), .ZN(n_1_0_535) + ); + NOR3_X1_LVT i_1_0_563( + .A1(n_1_0_545), .A2(n_1_0_540), .A3(n_1_0_535), .ZN(n_1_0_534) + ); + NAND4_X1_LVT i_1_0_562( + .A1(n_1_0_552), .A2(n_1_0_551), .A3(n_1_0_550), .A4(n_1_0_534), .ZN(RRs2[28]) + ); + AOI22_X1_LVT i_1_0_561( + .A1(registers_17__ap[27]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[27]), + .ZN(n_1_0_533) + ); + AOI222_X1_LVT i_1_0_560( + .A1(registers_19__ap[27]), .A2(n_1_0_633), .B1(n_1_0_631), .B2(registers_13__ap[27]), + .C1(registers_30__ap[27]), .C2(n_1_0_622), .ZN(n_1_0_532) + ); + AOI22_X1_LVT i_1_0_559( + .A1(registers_1__ap[27]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[27]), + .ZN(n_1_0_531) + ); + AOI22_X1_LVT i_1_0_558( + .A1(registers_24__ap[27]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[27]), + .ZN(n_1_0_530) + ); + AOI22_X1_LVT i_1_0_557( + .A1(registers_15__ap[27]), .A2(n_1_0_627), .B1(n_1_0_611), .B2(registers_11__ap[27]), + .ZN(n_1_0_529) + ); + AOI22_X1_LVT i_1_0_556( + .A1(registers_4__ap[27]), .A2(n_1_0_638), .B1(n_1_0_636), .B2(registers_27__ap[27]), + .ZN(n_1_0_528) + ); + AOI22_X1_LVT i_1_0_555( + .A1(registers_31__ap[27]), .A2(n_1_0_637), .B1(n_1_0_618), .B2(registers_2__ap[27]), + .ZN(n_1_0_527) + ); + NAND4_X1_LVT i_1_0_554( + .A1(n_1_0_530), .A2(n_1_0_529), .A3(n_1_0_528), .A4(n_1_0_527), .ZN(n_1_0_526) + ); + AOI22_X1_LVT i_1_0_553( + .A1(registers_18__ap[27]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[27]), + .ZN(n_1_0_525) + ); + AOI22_X1_LVT i_1_0_552( + .A1(registers_5__ap[27]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[27]), + .ZN(n_1_0_524) + ); + AOI22_X1_LVT i_1_0_551( + .A1(registers_6__ap[27]), .A2(n_1_0_616), .B1(n_1_0_614), .B2(registers_16__ap[27]), + .ZN(n_1_0_523) + ); + AOI22_X1_LVT i_1_0_550( + .A1(registers_22__ap[27]), .A2(n_1_0_642), .B1(n_1_0_620), .B2(registers_25__ap[27]), + .ZN(n_1_0_522) + ); + NAND4_X1_LVT i_1_0_549( + .A1(n_1_0_525), .A2(n_1_0_524), .A3(n_1_0_523), .A4(n_1_0_522), .ZN(n_1_0_521) + ); + AOI22_X1_LVT i_1_0_548( + .A1(registers_29__ap[27]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[27]), + .ZN(n_1_0_520) + ); + AOI22_X1_LVT i_1_0_547( + .A1(registers_7__ap[27]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[27]), + .ZN(n_1_0_519) + ); + AOI22_X1_LVT i_1_0_546( + .A1(registers_8__ap[27]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[27]), + .ZN(n_1_0_518) + ); + AOI22_X1_LVT i_1_0_545( + .A1(registers_10__ap[27]), .A2(n_1_0_624), .B1(n_1_0_610), .B2(registers_3__ap[27]), + .ZN(n_1_0_517) + ); + NAND4_X1_LVT i_1_0_544( + .A1(n_1_0_520), .A2(n_1_0_519), .A3(n_1_0_518), .A4(n_1_0_517), .ZN(n_1_0_516) + ); + NOR3_X1_LVT i_1_0_543( + .A1(n_1_0_526), .A2(n_1_0_521), .A3(n_1_0_516), .ZN(n_1_0_515) + ); + NAND4_X1_LVT i_1_0_542( + .A1(n_1_0_533), .A2(n_1_0_532), .A3(n_1_0_531), .A4(n_1_0_515), .ZN(RRs2[27]) + ); + AOI22_X1_LVT i_1_0_541( + .A1(registers_17__ap[26]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[26]), + .ZN(n_1_0_514) + ); + AOI222_X1_LVT i_1_0_540( + .A1(registers_19__ap[26]), .A2(n_1_0_633), .B1(n_1_0_622), .B2(registers_30__ap[26]), + .C1(n_1_0_631), .C2(registers_13__ap[26]), .ZN(n_1_0_513) + ); + AOI22_X1_LVT i_1_0_539( + .A1(registers_1__ap[26]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[26]), + .ZN(n_1_0_512) + ); + AOI22_X1_LVT i_1_0_538( + .A1(registers_24__ap[26]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[26]), + .ZN(n_1_0_511) + ); + AOI22_X1_LVT i_1_0_537( + .A1(registers_15__ap[26]), .A2(n_1_0_627), .B1(n_1_0_611), .B2(registers_11__ap[26]), + .ZN(n_1_0_510) + ); + AOI22_X1_LVT i_1_0_536( + .A1(registers_4__ap[26]), .A2(n_1_0_638), .B1(n_1_0_636), .B2(registers_27__ap[26]), + .ZN(n_1_0_509) + ); + AOI22_X1_LVT i_1_0_535( + .A1(registers_31__ap[26]), .A2(n_1_0_637), .B1(n_1_0_618), .B2(registers_2__ap[26]), + .ZN(n_1_0_508) + ); + NAND4_X1_LVT i_1_0_534( + .A1(n_1_0_511), .A2(n_1_0_510), .A3(n_1_0_509), .A4(n_1_0_508), .ZN(n_1_0_507) + ); + AOI22_X1_LVT i_1_0_533( + .A1(registers_18__ap[26]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[26]), + .ZN(n_1_0_506) + ); + AOI22_X1_LVT i_1_0_532( + .A1(registers_5__ap[26]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[26]), + .ZN(n_1_0_505) + ); + AOI22_X1_LVT i_1_0_531( + .A1(registers_6__ap[26]), .A2(n_1_0_616), .B1(n_1_0_614), .B2(registers_16__ap[26]), + .ZN(n_1_0_504) + ); + AOI22_X1_LVT i_1_0_530( + .A1(registers_22__ap[26]), .A2(n_1_0_642), .B1(n_1_0_620), .B2(registers_25__ap[26]), + .ZN(n_1_0_503) + ); + NAND4_X1_LVT i_1_0_529( + .A1(n_1_0_506), .A2(n_1_0_505), .A3(n_1_0_504), .A4(n_1_0_503), .ZN(n_1_0_502) + ); + AOI22_X1_LVT i_1_0_528( + .A1(registers_29__ap[26]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[26]), + .ZN(n_1_0_501) + ); + AOI22_X1_LVT i_1_0_527( + .A1(registers_7__ap[26]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[26]), + .ZN(n_1_0_500) + ); + AOI22_X1_LVT i_1_0_526( + .A1(registers_8__ap[26]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[26]), + .ZN(n_1_0_499) + ); + AOI22_X1_LVT i_1_0_525( + .A1(registers_10__ap[26]), .A2(n_1_0_624), .B1(n_1_0_610), .B2(registers_3__ap[26]), + .ZN(n_1_0_498) + ); + NAND4_X1_LVT i_1_0_524( + .A1(n_1_0_501), .A2(n_1_0_500), .A3(n_1_0_499), .A4(n_1_0_498), .ZN(n_1_0_497) + ); + NOR3_X1_LVT i_1_0_523( + .A1(n_1_0_507), .A2(n_1_0_502), .A3(n_1_0_497), .ZN(n_1_0_496) + ); + NAND4_X1_LVT i_1_0_522( + .A1(n_1_0_514), .A2(n_1_0_513), .A3(n_1_0_512), .A4(n_1_0_496), .ZN(RRs2[26]) + ); + AOI22_X1_LVT i_1_0_520( + .A1(registers_5__ap[25]), .A2(n_1_0_635), .B1(n_1_0_634), .B2(registers_28__ap[25]), + .ZN(n_1_0_494) + ); + AOI22_X1_LVT i_1_0_521( + .A1(registers_8__ap[25]), .A2(n_1_0_626), .B1(n_1_0_620), .B2(registers_25__ap[25]), + .ZN(n_1_0_495) + ); + AOI22_X1_LVT i_1_0_519( + .A1(registers_14__ap[25]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[25]), + .ZN(n_1_0_493) + ); + AOI22_X1_LVT i_1_0_518( + .A1(registers_16__ap[25]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[25]), + .ZN(n_1_0_492) + ); + NAND3_X1_LVT i_1_0_517( + .A1(n_1_0_495), .A2(n_1_0_493), .A3(n_1_0_492), .ZN(n_1_0_491) + ); + AOI221_X1_LVT i_1_0_516( + .A(n_1_0_491), .B1(n_1_0_624), .B2(registers_10__ap[25]), .C1(registers_6__ap[25]), + .C2(n_1_0_616), .ZN(n_1_0_490) + ); + AOI222_X1_LVT i_1_0_515( + .A1(registers_1__ap[25]), .A2(n_1_0_644), .B1(n_1_0_640), .B2(registers_26__ap[25]), + .C1(n_1_0_622), .C2(registers_30__ap[25]), .ZN(n_1_0_489) + ); + NAND2_X1_LVT i_1_0_514( + .A1(n_1_0_490), .A2(n_1_0_489), .ZN(n_1_0_488) + ); + AOI221_X1_LVT i_1_0_513( + .A(n_1_0_488), .B1(n_1_0_649), .B2(registers_29__ap[25]), .C1(registers_2__ap[25]), + .C2(n_1_0_618), .ZN(n_1_0_487) + ); + AOI22_X1_LVT i_1_0_512( + .A1(registers_12__ap[25]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[25]), + .ZN(n_1_0_486) + ); + AOI22_X1_LVT i_1_0_511( + .A1(registers_22__ap[25]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[25]), + .ZN(n_1_0_485) + ); + AOI22_X1_LVT i_1_0_510( + .A1(registers_4__ap[25]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[25]), + .ZN(n_1_0_484) + ); + NAND3_X1_LVT i_1_0_509( + .A1(n_1_0_486), .A2(n_1_0_485), .A3(n_1_0_484), .ZN(n_1_0_483) + ); + AOI221_X1_LVT i_1_0_508( + .A(n_1_0_483), .B1(n_1_0_633), .B2(registers_19__ap[25]), .C1(registers_18__ap[25]), + .C2(n_1_0_646), .ZN(n_1_0_482) + ); + AOI22_X1_LVT i_1_0_507( + .A1(registers_15__ap[25]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[25]), + .ZN(n_1_0_481) + ); + AOI22_X1_LVT i_1_0_506( + .A1(registers_23__ap[25]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[25]), + .ZN(n_1_0_480) + ); + AOI22_X1_LVT i_1_0_505( + .A1(registers_13__ap[25]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[25]), + .ZN(n_1_0_479) + ); + NAND3_X1_LVT i_1_0_504( + .A1(n_1_0_481), .A2(n_1_0_480), .A3(n_1_0_479), .ZN(n_1_0_478) + ); + AOI221_X1_LVT i_1_0_503( + .A(n_1_0_478), .B1(n_1_0_636), .B2(registers_27__ap[25]), .C1(registers_31__ap[25]), + .C2(n_1_0_637), .ZN(n_1_0_477) + ); + NAND4_X1_LVT i_1_0_502( + .A1(n_1_0_494), .A2(n_1_0_487), .A3(n_1_0_482), .A4(n_1_0_477), .ZN(RRs2[25]) + ); + AOI22_X1_LVT i_1_0_501( + .A1(registers_17__ap[24]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[24]), + .ZN(n_1_0_476) + ); + AOI222_X1_LVT i_1_0_500( + .A1(registers_13__ap[24]), .A2(n_1_0_631), .B1(n_1_0_622), .B2(registers_30__ap[24]), + .C1(registers_26__ap[24]), .C2(n_1_0_640), .ZN(n_1_0_475) + ); + AOI22_X1_LVT i_1_0_499( + .A1(registers_1__ap[24]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[24]), + .ZN(n_1_0_474) + ); + AOI22_X1_LVT i_1_0_498( + .A1(registers_24__ap[24]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[24]), + .ZN(n_1_0_473) + ); + AOI22_X1_LVT i_1_0_497( + .A1(registers_8__ap[24]), .A2(n_1_0_626), .B1(n_1_0_616), .B2(registers_6__ap[24]), + .ZN(n_1_0_472) + ); + AOI22_X1_LVT i_1_0_496( + .A1(registers_4__ap[24]), .A2(n_1_0_638), .B1(n_1_0_611), .B2(registers_11__ap[24]), + .ZN(n_1_0_471) + ); + AOI22_X1_LVT i_1_0_495( + .A1(registers_10__ap[24]), .A2(n_1_0_624), .B1(n_1_0_618), .B2(registers_2__ap[24]), + .ZN(n_1_0_470) + ); + NAND4_X1_LVT i_1_0_494( + .A1(n_1_0_473), .A2(n_1_0_472), .A3(n_1_0_471), .A4(n_1_0_470), .ZN(n_1_0_469) + ); + AOI22_X1_LVT i_1_0_493( + .A1(registers_18__ap[24]), .A2(n_1_0_646), .B1(n_1_0_633), .B2(registers_19__ap[24]), + .ZN(n_1_0_468) + ); + AOI22_X1_LVT i_1_0_492( + .A1(registers_5__ap[24]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[24]), + .ZN(n_1_0_467) + ); + AOI22_X1_LVT i_1_0_491( + .A1(registers_15__ap[24]), .A2(n_1_0_627), .B1(n_1_0_614), .B2(registers_16__ap[24]), + .ZN(n_1_0_466) + ); + AOI22_X1_LVT i_1_0_490( + .A1(registers_22__ap[24]), .A2(n_1_0_642), .B1(n_1_0_620), .B2(registers_25__ap[24]), + .ZN(n_1_0_465) + ); + NAND4_X1_LVT i_1_0_489( + .A1(n_1_0_468), .A2(n_1_0_467), .A3(n_1_0_466), .A4(n_1_0_465), .ZN(n_1_0_464) + ); + AOI22_X1_LVT i_1_0_488( + .A1(registers_29__ap[24]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[24]), + .ZN(n_1_0_463) + ); + AOI22_X1_LVT i_1_0_487( + .A1(registers_7__ap[24]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[24]), + .ZN(n_1_0_462) + ); + AOI22_X1_LVT i_1_0_486( + .A1(registers_23__ap[24]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[24]), + .ZN(n_1_0_461) + ); + AOI22_X1_LVT i_1_0_485( + .A1(registers_31__ap[24]), .A2(n_1_0_637), .B1(n_1_0_636), .B2(registers_27__ap[24]), + .ZN(n_1_0_460) + ); + NAND4_X1_LVT i_1_0_484( + .A1(n_1_0_463), .A2(n_1_0_462), .A3(n_1_0_461), .A4(n_1_0_460), .ZN(n_1_0_459) + ); + NOR3_X1_LVT i_1_0_483( + .A1(n_1_0_469), .A2(n_1_0_464), .A3(n_1_0_459), .ZN(n_1_0_458) + ); + NAND4_X1_LVT i_1_0_482( + .A1(n_1_0_476), .A2(n_1_0_475), .A3(n_1_0_474), .A4(n_1_0_458), .ZN(RRs2[24]) + ); + AOI22_X1_LVT i_1_0_481( + .A1(registers_4__ap[23]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[23]), + .ZN(n_1_0_457) + ); + AOI222_X1_LVT i_1_0_480( + .A1(registers_18__ap[23]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[23]), + .C1(n_1_0_644), .C2(registers_1__ap[23]), .ZN(n_1_0_456) + ); + AOI22_X1_LVT i_1_0_479( + .A1(registers_29__ap[23]), .A2(n_1_0_649), .B1(n_1_0_618), .B2(registers_2__ap[23]), + .ZN(n_1_0_455) + ); + AOI22_X1_LVT i_1_0_478( + .A1(registers_14__ap[23]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[23]), + .ZN(n_1_0_454) + ); + AOI22_X1_LVT i_1_0_477( + .A1(registers_16__ap[23]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[23]), + .ZN(n_1_0_453) + ); + AOI22_X1_LVT i_1_0_476( + .A1(registers_27__ap[23]), .A2(n_1_0_636), .B1(n_1_0_620), .B2(registers_25__ap[23]), + .ZN(n_1_0_452) + ); + AOI22_X1_LVT i_1_0_475( + .A1(registers_31__ap[23]), .A2(n_1_0_637), .B1(n_1_0_616), .B2(registers_6__ap[23]), + .ZN(n_1_0_451) + ); + NAND4_X1_LVT i_1_0_474( + .A1(n_1_0_454), .A2(n_1_0_453), .A3(n_1_0_452), .A4(n_1_0_451), .ZN(n_1_0_450) + ); + AOI22_X1_LVT i_1_0_473( + .A1(registers_26__ap[23]), .A2(n_1_0_640), .B1(n_1_0_633), .B2(registers_19__ap[23]), + .ZN(n_1_0_449) + ); + AOI22_X1_LVT i_1_0_472( + .A1(registers_12__ap[23]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[23]), + .ZN(n_1_0_448) + ); + AOI22_X1_LVT i_1_0_471( + .A1(registers_22__ap[23]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[23]), + .ZN(n_1_0_447) + ); + AOI22_X1_LVT i_1_0_470( + .A1(registers_5__ap[23]), .A2(n_1_0_635), .B1(n_1_0_613), .B2(registers_20__ap[23]), + .ZN(n_1_0_446) + ); + NAND4_X1_LVT i_1_0_469( + .A1(n_1_0_449), .A2(n_1_0_448), .A3(n_1_0_447), .A4(n_1_0_446), .ZN(n_1_0_445) + ); + AOI22_X1_LVT i_1_0_468( + .A1(registers_15__ap[23]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[23]), + .ZN(n_1_0_444) + ); + AOI22_X1_LVT i_1_0_467( + .A1(registers_8__ap[23]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[23]), + .ZN(n_1_0_443) + ); + AOI22_X1_LVT i_1_0_466( + .A1(registers_13__ap[23]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[23]), + .ZN(n_1_0_442) + ); + AOI22_X1_LVT i_1_0_465( + .A1(registers_10__ap[23]), .A2(n_1_0_624), .B1(n_1_0_610), .B2(registers_3__ap[23]), + .ZN(n_1_0_441) + ); + NAND4_X1_LVT i_1_0_464( + .A1(n_1_0_444), .A2(n_1_0_443), .A3(n_1_0_442), .A4(n_1_0_441), .ZN(n_1_0_440) + ); + NOR3_X1_LVT i_1_0_463( + .A1(n_1_0_450), .A2(n_1_0_445), .A3(n_1_0_440), .ZN(n_1_0_439) + ); + NAND4_X1_LVT i_1_0_462( + .A1(n_1_0_457), .A2(n_1_0_456), .A3(n_1_0_455), .A4(n_1_0_439), .ZN(RRs2[23]) + ); + AOI22_X1_LVT i_1_0_460( + .A1(registers_17__ap[22]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[22]), + .ZN(n_1_0_437) + ); + AOI22_X1_LVT i_1_0_461( + .A1(registers_15__ap[22]), .A2(n_1_0_627), .B1(n_1_0_626), .B2(registers_8__ap[22]), + .ZN(n_1_0_438) + ); + AOI22_X1_LVT i_1_0_459( + .A1(registers_24__ap[22]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[22]), + .ZN(n_1_0_436) + ); + AOI22_X1_LVT i_1_0_458( + .A1(registers_5__ap[22]), .A2(n_1_0_635), .B1(n_1_0_611), .B2(registers_11__ap[22]), + .ZN(n_1_0_435) + ); + NAND3_X1_LVT i_1_0_457( + .A1(n_1_0_438), .A2(n_1_0_436), .A3(n_1_0_435), .ZN(n_1_0_434) + ); + AOI221_X1_LVT i_1_0_456( + .A(n_1_0_434), .B1(n_1_0_618), .B2(registers_2__ap[22]), .C1(registers_10__ap[22]), + .C2(n_1_0_624), .ZN(n_1_0_433) + ); + AOI222_X1_LVT i_1_0_455( + .A1(registers_26__ap[22]), .A2(n_1_0_640), .B1(n_1_0_622), .B2(registers_30__ap[22]), + .C1(n_1_0_631), .C2(registers_13__ap[22]), .ZN(n_1_0_432) + ); + NAND2_X1_LVT i_1_0_454( + .A1(n_1_0_433), .A2(n_1_0_432), .ZN(n_1_0_431) + ); + AOI221_X1_LVT i_1_0_453( + .A(n_1_0_431), .B1(n_1_0_644), .B2(registers_1__ap[22]), .C1(registers_28__ap[22]), + .C2(n_1_0_634), .ZN(n_1_0_430) + ); + AOI22_X1_LVT i_1_0_452( + .A1(registers_18__ap[22]), .A2(n_1_0_646), .B1(n_1_0_633), .B2(registers_19__ap[22]), + .ZN(n_1_0_429) + ); + AOI22_X1_LVT i_1_0_451( + .A1(registers_4__ap[22]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[22]), + .ZN(n_1_0_428) + ); + AOI22_X1_LVT i_1_0_450( + .A1(registers_6__ap[22]), .A2(n_1_0_616), .B1(n_1_0_614), .B2(registers_16__ap[22]), + .ZN(n_1_0_427) + ); + NAND3_X1_LVT i_1_0_449( + .A1(n_1_0_429), .A2(n_1_0_428), .A3(n_1_0_427), .ZN(n_1_0_426) + ); + AOI221_X1_LVT i_1_0_448( + .A(n_1_0_426), .B1(n_1_0_620), .B2(registers_25__ap[22]), .C1(registers_22__ap[22]), + .C2(n_1_0_642), .ZN(n_1_0_425) + ); + AOI22_X1_LVT i_1_0_447( + .A1(registers_29__ap[22]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[22]), + .ZN(n_1_0_424) + ); + AOI22_X1_LVT i_1_0_446( + .A1(registers_7__ap[22]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[22]), + .ZN(n_1_0_423) + ); + AOI22_X1_LVT i_1_0_445( + .A1(registers_23__ap[22]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[22]), + .ZN(n_1_0_422) + ); + NAND3_X1_LVT i_1_0_444( + .A1(n_1_0_424), .A2(n_1_0_423), .A3(n_1_0_422), .ZN(n_1_0_421) + ); + AOI221_X1_LVT i_1_0_443( + .A(n_1_0_421), .B1(n_1_0_636), .B2(registers_27__ap[22]), .C1(registers_31__ap[22]), + .C2(n_1_0_637), .ZN(n_1_0_420) + ); + NAND4_X1_LVT i_1_0_442( + .A1(n_1_0_437), .A2(n_1_0_430), .A3(n_1_0_425), .A4(n_1_0_420), .ZN(RRs2[22]) + ); + AOI22_X1_LVT i_1_0_441( + .A1(registers_5__ap[21]), .A2(n_1_0_635), .B1(n_1_0_634), .B2(registers_28__ap[21]), + .ZN(n_1_0_419) + ); + AOI222_X1_LVT i_1_0_440( + .A1(registers_1__ap[21]), .A2(n_1_0_644), .B1(n_1_0_640), .B2(registers_26__ap[21]), + .C1(n_1_0_622), .C2(registers_30__ap[21]), .ZN(n_1_0_418) + ); + AOI22_X1_LVT i_1_0_439( + .A1(registers_29__ap[21]), .A2(n_1_0_649), .B1(n_1_0_618), .B2(registers_2__ap[21]), + .ZN(n_1_0_417) + ); + AOI22_X1_LVT i_1_0_438( + .A1(registers_14__ap[21]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[21]), + .ZN(n_1_0_416) + ); + AOI22_X1_LVT i_1_0_437( + .A1(registers_8__ap[21]), .A2(n_1_0_626), .B1(n_1_0_614), .B2(registers_16__ap[21]), + .ZN(n_1_0_415) + ); + AOI22_X1_LVT i_1_0_436( + .A1(registers_25__ap[21]), .A2(n_1_0_620), .B1(n_1_0_611), .B2(registers_11__ap[21]), + .ZN(n_1_0_414) + ); + AOI22_X1_LVT i_1_0_435( + .A1(registers_10__ap[21]), .A2(n_1_0_624), .B1(n_1_0_616), .B2(registers_6__ap[21]), + .ZN(n_1_0_413) + ); + NAND4_X1_LVT i_1_0_434( + .A1(n_1_0_416), .A2(n_1_0_415), .A3(n_1_0_414), .A4(n_1_0_413), .ZN(n_1_0_412) + ); + AOI22_X1_LVT i_1_0_433( + .A1(registers_12__ap[21]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[21]), + .ZN(n_1_0_411) + ); + AOI22_X1_LVT i_1_0_432( + .A1(registers_22__ap[21]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[21]), + .ZN(n_1_0_410) + ); + AOI22_X1_LVT i_1_0_431( + .A1(registers_4__ap[21]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[21]), + .ZN(n_1_0_409) + ); + AOI22_X1_LVT i_1_0_430( + .A1(registers_18__ap[21]), .A2(n_1_0_646), .B1(n_1_0_633), .B2(registers_19__ap[21]), + .ZN(n_1_0_408) + ); + NAND4_X1_LVT i_1_0_429( + .A1(n_1_0_411), .A2(n_1_0_410), .A3(n_1_0_409), .A4(n_1_0_408), .ZN(n_1_0_407) + ); + AOI22_X1_LVT i_1_0_428( + .A1(registers_15__ap[21]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[21]), + .ZN(n_1_0_406) + ); + AOI22_X1_LVT i_1_0_427( + .A1(registers_23__ap[21]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[21]), + .ZN(n_1_0_405) + ); + AOI22_X1_LVT i_1_0_426( + .A1(registers_13__ap[21]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[21]), + .ZN(n_1_0_404) + ); + AOI22_X1_LVT i_1_0_425( + .A1(registers_31__ap[21]), .A2(n_1_0_637), .B1(n_1_0_636), .B2(registers_27__ap[21]), + .ZN(n_1_0_403) + ); + NAND4_X1_LVT i_1_0_424( + .A1(n_1_0_406), .A2(n_1_0_405), .A3(n_1_0_404), .A4(n_1_0_403), .ZN(n_1_0_402) + ); + NOR3_X1_LVT i_1_0_423( + .A1(n_1_0_412), .A2(n_1_0_407), .A3(n_1_0_402), .ZN(n_1_0_401) + ); + NAND4_X1_LVT i_1_0_422( + .A1(n_1_0_419), .A2(n_1_0_418), .A3(n_1_0_417), .A4(n_1_0_401), .ZN(RRs2[21]) + ); + AOI22_X1_LVT i_1_0_421( + .A1(registers_17__ap[20]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[20]), + .ZN(n_1_0_400) + ); + AOI222_X1_LVT i_1_0_420( + .A1(registers_13__ap[20]), .A2(n_1_0_631), .B1(n_1_0_622), .B2(registers_30__ap[20]), + .C1(registers_19__ap[20]), .C2(n_1_0_633), .ZN(n_1_0_399) + ); + AOI22_X1_LVT i_1_0_419( + .A1(registers_1__ap[20]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[20]), + .ZN(n_1_0_398) + ); + AOI22_X1_LVT i_1_0_418( + .A1(registers_24__ap[20]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[20]), + .ZN(n_1_0_397) + ); + AOI22_X1_LVT i_1_0_417( + .A1(registers_6__ap[20]), .A2(n_1_0_616), .B1(n_1_0_611), .B2(registers_11__ap[20]), + .ZN(n_1_0_396) + ); + AOI22_X1_LVT i_1_0_416( + .A1(registers_4__ap[20]), .A2(n_1_0_638), .B1(n_1_0_624), .B2(registers_10__ap[20]), + .ZN(n_1_0_395) + ); + AOI22_X1_LVT i_1_0_415( + .A1(registers_31__ap[20]), .A2(n_1_0_637), .B1(n_1_0_618), .B2(registers_2__ap[20]), + .ZN(n_1_0_394) + ); + NAND4_X1_LVT i_1_0_414( + .A1(n_1_0_397), .A2(n_1_0_396), .A3(n_1_0_395), .A4(n_1_0_394), .ZN(n_1_0_393) + ); + AOI22_X1_LVT i_1_0_413( + .A1(registers_18__ap[20]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[20]), + .ZN(n_1_0_392) + ); + AOI22_X1_LVT i_1_0_412( + .A1(registers_5__ap[20]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[20]), + .ZN(n_1_0_391) + ); + AOI22_X1_LVT i_1_0_411( + .A1(registers_15__ap[20]), .A2(n_1_0_627), .B1(n_1_0_614), .B2(registers_16__ap[20]), + .ZN(n_1_0_390) + ); + AOI22_X1_LVT i_1_0_410( + .A1(registers_22__ap[20]), .A2(n_1_0_642), .B1(n_1_0_620), .B2(registers_25__ap[20]), + .ZN(n_1_0_389) + ); + NAND4_X1_LVT i_1_0_409( + .A1(n_1_0_392), .A2(n_1_0_391), .A3(n_1_0_390), .A4(n_1_0_389), .ZN(n_1_0_388) + ); + AOI22_X1_LVT i_1_0_408( + .A1(registers_29__ap[20]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[20]), + .ZN(n_1_0_387) + ); + AOI22_X1_LVT i_1_0_407( + .A1(registers_7__ap[20]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[20]), + .ZN(n_1_0_386) + ); + AOI22_X1_LVT i_1_0_406( + .A1(registers_8__ap[20]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[20]), + .ZN(n_1_0_385) + ); + AOI22_X1_LVT i_1_0_405( + .A1(registers_27__ap[20]), .A2(n_1_0_636), .B1(n_1_0_610), .B2(registers_3__ap[20]), + .ZN(n_1_0_384) + ); + NAND4_X1_LVT i_1_0_404( + .A1(n_1_0_387), .A2(n_1_0_386), .A3(n_1_0_385), .A4(n_1_0_384), .ZN(n_1_0_383) + ); + NOR3_X1_LVT i_1_0_403( + .A1(n_1_0_393), .A2(n_1_0_388), .A3(n_1_0_383), .ZN(n_1_0_382) + ); + NAND4_X1_LVT i_1_0_402( + .A1(n_1_0_400), .A2(n_1_0_399), .A3(n_1_0_398), .A4(n_1_0_382), .ZN(RRs2[20]) + ); + AOI22_X1_LVT i_1_0_401( + .A1(registers_17__ap[19]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[19]), + .ZN(n_1_0_381) + ); + AOI222_X1_LVT i_1_0_400( + .A1(registers_13__ap[19]), .A2(n_1_0_631), .B1(n_1_0_622), .B2(registers_30__ap[19]), + .C1(registers_19__ap[19]), .C2(n_1_0_633), .ZN(n_1_0_380) + ); + AOI22_X1_LVT i_1_0_399( + .A1(registers_1__ap[19]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[19]), + .ZN(n_1_0_379) + ); + AOI22_X1_LVT i_1_0_398( + .A1(registers_24__ap[19]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[19]), + .ZN(n_1_0_378) + ); + AOI22_X1_LVT i_1_0_397( + .A1(registers_15__ap[19]), .A2(n_1_0_627), .B1(n_1_0_611), .B2(registers_11__ap[19]), + .ZN(n_1_0_377) + ); + AOI22_X1_LVT i_1_0_396( + .A1(registers_4__ap[19]), .A2(n_1_0_638), .B1(n_1_0_636), .B2(registers_27__ap[19]), + .ZN(n_1_0_376) + ); + AOI22_X1_LVT i_1_0_395( + .A1(registers_31__ap[19]), .A2(n_1_0_637), .B1(n_1_0_618), .B2(registers_2__ap[19]), + .ZN(n_1_0_375) + ); + NAND4_X1_LVT i_1_0_394( + .A1(n_1_0_378), .A2(n_1_0_377), .A3(n_1_0_376), .A4(n_1_0_375), .ZN(n_1_0_374) + ); + AOI22_X1_LVT i_1_0_393( + .A1(registers_18__ap[19]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[19]), + .ZN(n_1_0_373) + ); + AOI22_X1_LVT i_1_0_392( + .A1(registers_5__ap[19]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[19]), + .ZN(n_1_0_372) + ); + AOI22_X1_LVT i_1_0_391( + .A1(registers_25__ap[19]), .A2(n_1_0_620), .B1(n_1_0_616), .B2(registers_6__ap[19]), + .ZN(n_1_0_371) + ); + AOI22_X1_LVT i_1_0_390( + .A1(registers_22__ap[19]), .A2(n_1_0_642), .B1(n_1_0_614), .B2(registers_16__ap[19]), + .ZN(n_1_0_370) + ); + NAND4_X1_LVT i_1_0_389( + .A1(n_1_0_373), .A2(n_1_0_372), .A3(n_1_0_371), .A4(n_1_0_370), .ZN(n_1_0_369) + ); + AOI22_X1_LVT i_1_0_388( + .A1(registers_29__ap[19]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[19]), + .ZN(n_1_0_368) + ); + AOI22_X1_LVT i_1_0_387( + .A1(registers_7__ap[19]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[19]), + .ZN(n_1_0_367) + ); + AOI22_X1_LVT i_1_0_386( + .A1(registers_8__ap[19]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[19]), + .ZN(n_1_0_366) + ); + AOI22_X1_LVT i_1_0_385( + .A1(registers_10__ap[19]), .A2(n_1_0_624), .B1(n_1_0_610), .B2(registers_3__ap[19]), + .ZN(n_1_0_365) + ); + NAND4_X1_LVT i_1_0_384( + .A1(n_1_0_368), .A2(n_1_0_367), .A3(n_1_0_366), .A4(n_1_0_365), .ZN(n_1_0_364) + ); + NOR3_X1_LVT i_1_0_383( + .A1(n_1_0_374), .A2(n_1_0_369), .A3(n_1_0_364), .ZN(n_1_0_363) + ); + NAND4_X1_LVT i_1_0_382( + .A1(n_1_0_381), .A2(n_1_0_380), .A3(n_1_0_379), .A4(n_1_0_363), .ZN(RRs2[19]) + ); + AOI22_X1_LVT i_1_0_380( + .A1(registers_4__ap[18]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[18]), + .ZN(n_1_0_361) + ); + AOI22_X1_LVT i_1_0_381( + .A1(registers_8__ap[18]), .A2(n_1_0_626), .B1(n_1_0_614), .B2(registers_16__ap[18]), + .ZN(n_1_0_362) + ); + AOI22_X1_LVT i_1_0_379( + .A1(registers_14__ap[18]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[18]), + .ZN(n_1_0_360) + ); + AOI22_X1_LVT i_1_0_378( + .A1(registers_25__ap[18]), .A2(n_1_0_620), .B1(n_1_0_611), .B2(registers_11__ap[18]), + .ZN(n_1_0_359) + ); + NAND3_X1_LVT i_1_0_377( + .A1(n_1_0_362), .A2(n_1_0_360), .A3(n_1_0_359), .ZN(n_1_0_358) + ); + AOI221_X1_LVT i_1_0_376( + .A(n_1_0_358), .B1(n_1_0_624), .B2(registers_10__ap[18]), .C1(registers_6__ap[18]), + .C2(n_1_0_616), .ZN(n_1_0_357) + ); + AOI222_X1_LVT i_1_0_375( + .A1(registers_1__ap[18]), .A2(n_1_0_644), .B1(n_1_0_640), .B2(registers_26__ap[18]), + .C1(n_1_0_622), .C2(registers_30__ap[18]), .ZN(n_1_0_356) + ); + NAND2_X1_LVT i_1_0_374( + .A1(n_1_0_357), .A2(n_1_0_356), .ZN(n_1_0_355) + ); + AOI221_X1_LVT i_1_0_373( + .A(n_1_0_355), .B1(n_1_0_649), .B2(registers_29__ap[18]), .C1(registers_2__ap[18]), + .C2(n_1_0_618), .ZN(n_1_0_354) + ); + AOI22_X1_LVT i_1_0_372( + .A1(registers_18__ap[18]), .A2(n_1_0_646), .B1(n_1_0_633), .B2(registers_19__ap[18]), + .ZN(n_1_0_353) + ); + AOI22_X1_LVT i_1_0_371( + .A1(registers_12__ap[18]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[18]), + .ZN(n_1_0_352) + ); + AOI22_X1_LVT i_1_0_370( + .A1(registers_22__ap[18]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[18]), + .ZN(n_1_0_351) + ); + NAND3_X1_LVT i_1_0_369( + .A1(n_1_0_353), .A2(n_1_0_352), .A3(n_1_0_351), .ZN(n_1_0_350) + ); + AOI221_X1_LVT i_1_0_368( + .A(n_1_0_350), .B1(n_1_0_635), .B2(registers_5__ap[18]), .C1(registers_20__ap[18]), + .C2(n_1_0_613), .ZN(n_1_0_349) + ); + AOI22_X1_LVT i_1_0_367( + .A1(registers_15__ap[18]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[18]), + .ZN(n_1_0_348) + ); + AOI22_X1_LVT i_1_0_366( + .A1(registers_23__ap[18]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[18]), + .ZN(n_1_0_347) + ); + AOI22_X1_LVT i_1_0_365( + .A1(registers_13__ap[18]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[18]), + .ZN(n_1_0_346) + ); + NAND3_X1_LVT i_1_0_364( + .A1(n_1_0_348), .A2(n_1_0_347), .A3(n_1_0_346), .ZN(n_1_0_345) + ); + AOI221_X1_LVT i_1_0_363( + .A(n_1_0_345), .B1(n_1_0_637), .B2(registers_31__ap[18]), .C1(registers_27__ap[18]), + .C2(n_1_0_636), .ZN(n_1_0_344) + ); + NAND4_X1_LVT i_1_0_362( + .A1(n_1_0_361), .A2(n_1_0_354), .A3(n_1_0_349), .A4(n_1_0_344), .ZN(RRs2[18]) + ); + AOI22_X1_LVT i_1_0_358( + .A1(registers_4__ap[17]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[17]), + .ZN(n_1_0_340) + ); + AOI22_X1_LVT i_1_0_361( + .A1(registers_31__ap[17]), .A2(n_1_0_637), .B1(n_1_0_616), .B2(registers_6__ap[17]), + .ZN(n_1_0_343) + ); + AOI22_X1_LVT i_1_0_357( + .A1(registers_14__ap[17]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[17]), + .ZN(n_1_0_339) + ); + AOI22_X1_LVT i_1_0_360( + .A1(registers_25__ap[17]), .A2(n_1_0_620), .B1(n_1_0_611), .B2(registers_11__ap[17]), + .ZN(n_1_0_342) + ); + INV_X1_LVT i_1_0_359( + .A(n_1_0_342), .ZN(n_1_0_341) + ); + AOI221_X1_LVT i_1_0_356( + .A(n_1_0_341), .B1(n_1_0_614), .B2(registers_16__ap[17]), .C1(registers_10__ap[17]), + .C2(n_1_0_624), .ZN(n_1_0_338) + ); + AOI222_X1_LVT i_1_0_355( + .A1(registers_1__ap[17]), .A2(n_1_0_644), .B1(n_1_0_622), .B2(registers_30__ap[17]), + .C1(registers_18__ap[17]), .C2(n_1_0_646), .ZN(n_1_0_337) + ); + NAND4_X1_LVT i_1_0_354( + .A1(n_1_0_343), .A2(n_1_0_339), .A3(n_1_0_338), .A4(n_1_0_337), .ZN(n_1_0_336) + ); + AOI221_X1_LVT i_1_0_353( + .A(n_1_0_336), .B1(n_1_0_649), .B2(registers_29__ap[17]), .C1(registers_2__ap[17]), + .C2(n_1_0_618), .ZN(n_1_0_335) + ); + AOI22_X1_LVT i_1_0_352( + .A1(registers_26__ap[17]), .A2(n_1_0_640), .B1(n_1_0_633), .B2(registers_19__ap[17]), + .ZN(n_1_0_334) + ); + AOI22_X1_LVT i_1_0_351( + .A1(registers_12__ap[17]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[17]), + .ZN(n_1_0_333) + ); + AOI22_X1_LVT i_1_0_350( + .A1(registers_22__ap[17]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[17]), + .ZN(n_1_0_332) + ); + NAND3_X1_LVT i_1_0_349( + .A1(n_1_0_334), .A2(n_1_0_333), .A3(n_1_0_332), .ZN(n_1_0_331) + ); + AOI221_X1_LVT i_1_0_348( + .A(n_1_0_331), .B1(n_1_0_635), .B2(registers_5__ap[17]), .C1(registers_20__ap[17]), + .C2(n_1_0_613), .ZN(n_1_0_330) + ); + AOI22_X1_LVT i_1_0_347( + .A1(registers_15__ap[17]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[17]), + .ZN(n_1_0_329) + ); + AOI22_X1_LVT i_1_0_346( + .A1(registers_8__ap[17]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[17]), + .ZN(n_1_0_328) + ); + AOI22_X1_LVT i_1_0_345( + .A1(registers_13__ap[17]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[17]), + .ZN(n_1_0_327) + ); + NAND3_X1_LVT i_1_0_344( + .A1(n_1_0_329), .A2(n_1_0_328), .A3(n_1_0_327), .ZN(n_1_0_326) + ); + AOI221_X1_LVT i_1_0_343( + .A(n_1_0_326), .B1(n_1_0_636), .B2(registers_27__ap[17]), .C1(registers_3__ap[17]), + .C2(n_1_0_610), .ZN(n_1_0_325) + ); + NAND4_X1_LVT i_1_0_342( + .A1(n_1_0_340), .A2(n_1_0_335), .A3(n_1_0_330), .A4(n_1_0_325), .ZN(RRs2[17]) + ); + AOI22_X1_LVT i_1_0_341( + .A1(registers_4__ap[16]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[16]), + .ZN(n_1_0_324) + ); + AOI222_X1_LVT i_1_0_340( + .A1(registers_1__ap[16]), .A2(n_1_0_644), .B1(n_1_0_633), .B2(registers_19__ap[16]), + .C1(n_1_0_622), .C2(registers_30__ap[16]), .ZN(n_1_0_323) + ); + AOI22_X1_LVT i_1_0_339( + .A1(registers_29__ap[16]), .A2(n_1_0_649), .B1(n_1_0_618), .B2(registers_2__ap[16]), + .ZN(n_1_0_322) + ); + AOI22_X1_LVT i_1_0_338( + .A1(registers_14__ap[16]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[16]), + .ZN(n_1_0_321) + ); + AOI22_X1_LVT i_1_0_337( + .A1(registers_16__ap[16]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[16]), + .ZN(n_1_0_320) + ); + AOI22_X1_LVT i_1_0_336( + .A1(registers_10__ap[16]), .A2(n_1_0_624), .B1(n_1_0_620), .B2(registers_25__ap[16]), + .ZN(n_1_0_319) + ); + AOI22_X1_LVT i_1_0_335( + .A1(registers_31__ap[16]), .A2(n_1_0_637), .B1(n_1_0_616), .B2(registers_6__ap[16]), + .ZN(n_1_0_318) + ); + NAND4_X1_LVT i_1_0_334( + .A1(n_1_0_321), .A2(n_1_0_320), .A3(n_1_0_319), .A4(n_1_0_318), .ZN(n_1_0_317) + ); + AOI22_X1_LVT i_1_0_333( + .A1(registers_18__ap[16]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[16]), + .ZN(n_1_0_316) + ); + AOI22_X1_LVT i_1_0_332( + .A1(registers_12__ap[16]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[16]), + .ZN(n_1_0_315) + ); + AOI22_X1_LVT i_1_0_331( + .A1(registers_22__ap[16]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[16]), + .ZN(n_1_0_314) + ); + AOI22_X1_LVT i_1_0_330( + .A1(registers_5__ap[16]), .A2(n_1_0_635), .B1(n_1_0_613), .B2(registers_20__ap[16]), + .ZN(n_1_0_313) + ); + NAND4_X1_LVT i_1_0_329( + .A1(n_1_0_316), .A2(n_1_0_315), .A3(n_1_0_314), .A4(n_1_0_313), .ZN(n_1_0_312) + ); + AOI22_X1_LVT i_1_0_328( + .A1(registers_15__ap[16]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[16]), + .ZN(n_1_0_311) + ); + AOI22_X1_LVT i_1_0_327( + .A1(registers_8__ap[16]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[16]), + .ZN(n_1_0_310) + ); + AOI22_X1_LVT i_1_0_326( + .A1(registers_13__ap[16]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[16]), + .ZN(n_1_0_309) + ); + AOI22_X1_LVT i_1_0_325( + .A1(registers_27__ap[16]), .A2(n_1_0_636), .B1(n_1_0_610), .B2(registers_3__ap[16]), + .ZN(n_1_0_308) + ); + NAND4_X1_LVT i_1_0_324( + .A1(n_1_0_311), .A2(n_1_0_310), .A3(n_1_0_309), .A4(n_1_0_308), .ZN(n_1_0_307) + ); + NOR3_X1_LVT i_1_0_323( + .A1(n_1_0_317), .A2(n_1_0_312), .A3(n_1_0_307), .ZN(n_1_0_306) + ); + NAND4_X1_LVT i_1_0_322( + .A1(n_1_0_324), .A2(n_1_0_323), .A3(n_1_0_322), .A4(n_1_0_306), .ZN(RRs2[16]) + ); + AOI22_X1_LVT i_1_0_320( + .A1(registers_5__ap[15]), .A2(n_1_0_635), .B1(n_1_0_634), .B2(registers_28__ap[15]), + .ZN(n_1_0_304) + ); + AOI22_X1_LVT i_1_0_321( + .A1(registers_8__ap[15]), .A2(n_1_0_626), .B1(n_1_0_620), .B2(registers_25__ap[15]), + .ZN(n_1_0_305) + ); + AOI22_X1_LVT i_1_0_319( + .A1(registers_14__ap[15]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[15]), + .ZN(n_1_0_303) + ); + AOI22_X1_LVT i_1_0_318( + .A1(registers_16__ap[15]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[15]), + .ZN(n_1_0_302) + ); + NAND3_X1_LVT i_1_0_317( + .A1(n_1_0_305), .A2(n_1_0_303), .A3(n_1_0_302), .ZN(n_1_0_301) + ); + AOI221_X1_LVT i_1_0_316( + .A(n_1_0_301), .B1(n_1_0_616), .B2(registers_6__ap[15]), .C1(registers_10__ap[15]), + .C2(n_1_0_624), .ZN(n_1_0_300) + ); + AOI222_X1_LVT i_1_0_315( + .A1(registers_1__ap[15]), .A2(n_1_0_644), .B1(n_1_0_640), .B2(registers_26__ap[15]), + .C1(n_1_0_622), .C2(registers_30__ap[15]), .ZN(n_1_0_299) + ); + NAND2_X1_LVT i_1_0_314( + .A1(n_1_0_300), .A2(n_1_0_299), .ZN(n_1_0_298) + ); + AOI221_X1_LVT i_1_0_313( + .A(n_1_0_298), .B1(n_1_0_649), .B2(registers_29__ap[15]), .C1(registers_2__ap[15]), + .C2(n_1_0_618), .ZN(n_1_0_297) + ); + AOI22_X1_LVT i_1_0_312( + .A1(registers_12__ap[15]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[15]), + .ZN(n_1_0_296) + ); + AOI22_X1_LVT i_1_0_311( + .A1(registers_22__ap[15]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[15]), + .ZN(n_1_0_295) + ); + AOI22_X1_LVT i_1_0_310( + .A1(registers_4__ap[15]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[15]), + .ZN(n_1_0_294) + ); + NAND3_X1_LVT i_1_0_309( + .A1(n_1_0_296), .A2(n_1_0_295), .A3(n_1_0_294), .ZN(n_1_0_293) + ); + AOI221_X1_LVT i_1_0_308( + .A(n_1_0_293), .B1(n_1_0_633), .B2(registers_19__ap[15]), .C1(registers_18__ap[15]), + .C2(n_1_0_646), .ZN(n_1_0_292) + ); + AOI22_X1_LVT i_1_0_307( + .A1(registers_15__ap[15]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[15]), + .ZN(n_1_0_291) + ); + AOI22_X1_LVT i_1_0_306( + .A1(registers_23__ap[15]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[15]), + .ZN(n_1_0_290) + ); + AOI22_X1_LVT i_1_0_305( + .A1(registers_13__ap[15]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[15]), + .ZN(n_1_0_289) + ); + NAND3_X1_LVT i_1_0_304( + .A1(n_1_0_291), .A2(n_1_0_290), .A3(n_1_0_289), .ZN(n_1_0_288) + ); + AOI221_X1_LVT i_1_0_303( + .A(n_1_0_288), .B1(n_1_0_636), .B2(registers_27__ap[15]), .C1(registers_31__ap[15]), + .C2(n_1_0_637), .ZN(n_1_0_287) + ); + NAND4_X1_LVT i_1_0_302( + .A1(n_1_0_304), .A2(n_1_0_297), .A3(n_1_0_292), .A4(n_1_0_287), .ZN(RRs2[15]) + ); + AOI22_X1_LVT i_1_0_301( + .A1(registers_28__ap[14]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[14]), + .ZN(n_1_0_286) + ); + AOI222_X1_LVT i_1_0_300( + .A1(registers_18__ap[14]), .A2(n_1_0_646), .B1(n_1_0_620), .B2(registers_25__ap[14]), + .C1(n_1_0_618), .C2(registers_2__ap[14]), .ZN(n_1_0_285) + ); + AOI22_X1_LVT i_1_0_299( + .A1(registers_24__ap[14]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[14]), + .ZN(n_1_0_284) + ); + AOI22_X1_LVT i_1_0_298( + .A1(registers_15__ap[14]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[14]), + .ZN(n_1_0_283) + ); + AOI22_X1_LVT i_1_0_297( + .A1(registers_4__ap[14]), .A2(n_1_0_638), .B1(n_1_0_637), .B2(registers_31__ap[14]), + .ZN(n_1_0_282) + ); + AOI22_X1_LVT i_1_0_296( + .A1(registers_29__ap[14]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[14]), + .ZN(n_1_0_281) + ); + NAND4_X1_LVT i_1_0_295( + .A1(n_1_0_284), .A2(n_1_0_283), .A3(n_1_0_282), .A4(n_1_0_281), .ZN(n_1_0_280) + ); + AOI221_X1_LVT i_1_0_294( + .A(n_1_0_280), .B1(n_1_0_644), .B2(registers_1__ap[14]), .C1(registers_13__ap[14]), + .C2(n_1_0_631), .ZN(n_1_0_279) + ); + AOI22_X1_LVT i_1_0_293( + .A1(registers_17__ap[14]), .A2(n_1_0_629), .B1(n_1_0_623), .B2(registers_7__ap[14]), + .ZN(n_1_0_278) + ); + AOI22_X1_LVT i_1_0_292( + .A1(registers_5__ap[14]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[14]), + .ZN(n_1_0_277) + ); + AOI22_X1_LVT i_1_0_291( + .A1(registers_10__ap[14]), .A2(n_1_0_624), .B1(n_1_0_622), .B2(registers_30__ap[14]), + .ZN(n_1_0_276) + ); + AOI22_X1_LVT i_1_0_290( + .A1(registers_26__ap[14]), .A2(n_1_0_640), .B1(n_1_0_614), .B2(registers_16__ap[14]), + .ZN(n_1_0_275) + ); + NAND4_X1_LVT i_1_0_289( + .A1(n_1_0_278), .A2(n_1_0_277), .A3(n_1_0_276), .A4(n_1_0_275), .ZN(n_1_0_274) + ); + AOI22_X1_LVT i_1_0_288( + .A1(registers_9__ap[14]), .A2(n_1_0_617), .B1(n_1_0_612), .B2(registers_21__ap[14]), + .ZN(n_1_0_273) + ); + AOI22_X1_LVT i_1_0_287( + .A1(registers_14__ap[14]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[14]), + .ZN(n_1_0_272) + ); + AOI22_X1_LVT i_1_0_286( + .A1(registers_22__ap[14]), .A2(n_1_0_642), .B1(n_1_0_633), .B2(registers_19__ap[14]), + .ZN(n_1_0_271) + ); + AOI22_X1_LVT i_1_0_285( + .A1(registers_27__ap[14]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[14]), + .ZN(n_1_0_270) + ); + NAND4_X1_LVT i_1_0_284( + .A1(n_1_0_273), .A2(n_1_0_272), .A3(n_1_0_271), .A4(n_1_0_270), .ZN(n_1_0_269) + ); + NOR2_X1_LVT i_1_0_283( + .A1(n_1_0_274), .A2(n_1_0_269), .ZN(n_1_0_268) + ); + NAND4_X1_LVT i_1_0_282( + .A1(n_1_0_286), .A2(n_1_0_285), .A3(n_1_0_279), .A4(n_1_0_268), .ZN(RRs2[14]) + ); + AOI22_X1_LVT i_1_0_281( + .A1(registers_18__ap[13]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[13]), + .ZN(n_1_0_267) + ); + AOI22_X1_LVT i_1_0_280( + .A1(registers_12__ap[13]), .A2(n_1_0_632), .B1(n_1_0_629), .B2(registers_17__ap[13]), + .ZN(n_1_0_266) + ); + AOI22_X1_LVT i_1_0_279( + .A1(registers_7__ap[13]), .A2(n_1_0_623), .B1(n_1_0_614), .B2(registers_16__ap[13]), + .ZN(n_1_0_265) + ); + NAND3_X1_LVT i_1_0_277( + .A1(n_1_0_267), .A2(n_1_0_266), .A3(n_1_0_265), .ZN(n_1_0_263) + ); + AOI221_X1_LVT i_1_0_276( + .A(n_1_0_263), .B1(n_1_0_642), .B2(registers_22__ap[13]), .C1(registers_5__ap[13]), + .C2(n_1_0_635), .ZN(n_1_0_262) + ); + AOI22_X1_LVT i_1_0_278( + .A1(registers_13__ap[13]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[13]), + .ZN(n_1_0_264) + ); + AOI222_X1_LVT i_1_0_275( + .A1(registers_26__ap[13]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[13]), + .C1(n_1_0_620), .C2(registers_25__ap[13]), .ZN(n_1_0_261) + ); + AOI22_X1_LVT i_1_0_274( + .A1(registers_28__ap[13]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[13]), + .ZN(n_1_0_260) + ); + NAND3_X1_LVT i_1_0_273( + .A1(n_1_0_264), .A2(n_1_0_261), .A3(n_1_0_260), .ZN(n_1_0_259) + ); + AOI22_X1_LVT i_1_0_272( + .A1(registers_1__ap[13]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[13]), + .ZN(n_1_0_258) + ); + AOI22_X1_LVT i_1_0_271( + .A1(registers_19__ap[13]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[13]), + .ZN(n_1_0_257) + ); + AOI22_X1_LVT i_1_0_270( + .A1(registers_14__ap[13]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[13]), + .ZN(n_1_0_256) + ); + AOI22_X1_LVT i_1_0_269( + .A1(registers_27__ap[13]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[13]), + .ZN(n_1_0_255) + ); + NAND4_X1_LVT i_1_0_268( + .A1(n_1_0_258), .A2(n_1_0_257), .A3(n_1_0_256), .A4(n_1_0_255), .ZN(n_1_0_254) + ); + AOI22_X1_LVT i_1_0_267( + .A1(registers_24__ap[13]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[13]), + .ZN(n_1_0_253) + ); + AOI22_X1_LVT i_1_0_266( + .A1(registers_4__ap[13]), .A2(n_1_0_638), .B1(n_1_0_637), .B2(registers_31__ap[13]), + .ZN(n_1_0_252) + ); + AOI22_X1_LVT i_1_0_265( + .A1(registers_29__ap[13]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[13]), + .ZN(n_1_0_251) + ); + AOI22_X1_LVT i_1_0_264( + .A1(registers_15__ap[13]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[13]), + .ZN(n_1_0_250) + ); + NAND4_X1_LVT i_1_0_263( + .A1(n_1_0_253), .A2(n_1_0_252), .A3(n_1_0_251), .A4(n_1_0_250), .ZN(n_1_0_249) + ); + NOR3_X1_LVT i_1_0_262( + .A1(n_1_0_259), .A2(n_1_0_254), .A3(n_1_0_249), .ZN(n_1_0_248) + ); + NAND2_X1_LVT i_1_0_261( + .A1(n_1_0_262), .A2(n_1_0_248), .ZN(RRs2[13]) + ); + AOI22_X1_LVT i_1_0_260( + .A1(registers_18__ap[12]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[12]), + .ZN(n_1_0_247) + ); + AOI22_X1_LVT i_1_0_259( + .A1(registers_12__ap[12]), .A2(n_1_0_632), .B1(n_1_0_629), .B2(registers_17__ap[12]), + .ZN(n_1_0_246) + ); + AOI22_X1_LVT i_1_0_258( + .A1(registers_5__ap[12]), .A2(n_1_0_635), .B1(n_1_0_623), .B2(registers_7__ap[12]), + .ZN(n_1_0_245) + ); + NAND3_X1_LVT i_1_0_256( + .A1(n_1_0_247), .A2(n_1_0_246), .A3(n_1_0_245), .ZN(n_1_0_243) + ); + AOI221_X1_LVT i_1_0_255( + .A(n_1_0_243), .B1(n_1_0_642), .B2(registers_22__ap[12]), .C1(registers_16__ap[12]), + .C2(n_1_0_614), .ZN(n_1_0_242) + ); + AOI22_X1_LVT i_1_0_257( + .A1(registers_13__ap[12]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[12]), + .ZN(n_1_0_244) + ); + AOI222_X1_LVT i_1_0_254( + .A1(registers_26__ap[12]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[12]), + .C1(n_1_0_620), .C2(registers_25__ap[12]), .ZN(n_1_0_241) + ); + AOI22_X1_LVT i_1_0_253( + .A1(registers_28__ap[12]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[12]), + .ZN(n_1_0_240) + ); + NAND3_X1_LVT i_1_0_252( + .A1(n_1_0_244), .A2(n_1_0_241), .A3(n_1_0_240), .ZN(n_1_0_239) + ); + AOI22_X1_LVT i_1_0_251( + .A1(registers_1__ap[12]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[12]), + .ZN(n_1_0_238) + ); + AOI22_X1_LVT i_1_0_250( + .A1(registers_19__ap[12]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[12]), + .ZN(n_1_0_237) + ); + AOI22_X1_LVT i_1_0_249( + .A1(registers_14__ap[12]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[12]), + .ZN(n_1_0_236) + ); + AOI22_X1_LVT i_1_0_248( + .A1(registers_27__ap[12]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[12]), + .ZN(n_1_0_235) + ); + NAND4_X1_LVT i_1_0_247( + .A1(n_1_0_238), .A2(n_1_0_237), .A3(n_1_0_236), .A4(n_1_0_235), .ZN(n_1_0_234) + ); + AOI22_X1_LVT i_1_0_246( + .A1(registers_24__ap[12]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[12]), + .ZN(n_1_0_233) + ); + AOI22_X1_LVT i_1_0_245( + .A1(registers_4__ap[12]), .A2(n_1_0_638), .B1(n_1_0_637), .B2(registers_31__ap[12]), + .ZN(n_1_0_232) + ); + AOI22_X1_LVT i_1_0_244( + .A1(registers_29__ap[12]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[12]), + .ZN(n_1_0_231) + ); + AOI22_X1_LVT i_1_0_243( + .A1(registers_15__ap[12]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[12]), + .ZN(n_1_0_230) + ); + NAND4_X1_LVT i_1_0_242( + .A1(n_1_0_233), .A2(n_1_0_232), .A3(n_1_0_231), .A4(n_1_0_230), .ZN(n_1_0_229) + ); + NOR3_X1_LVT i_1_0_241( + .A1(n_1_0_239), .A2(n_1_0_234), .A3(n_1_0_229), .ZN(n_1_0_228) + ); + NAND2_X1_LVT i_1_0_240( + .A1(n_1_0_242), .A2(n_1_0_228), .ZN(RRs2[12]) + ); + AOI22_X1_LVT i_1_0_238( + .A1(registers_29__ap[11]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[11]), + .ZN(n_1_0_226) + ); + AOI22_X1_LVT i_1_0_239( + .A1(registers_27__ap[11]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[11]), + .ZN(n_1_0_227) + ); + AOI22_X1_LVT i_1_0_237( + .A1(registers_1__ap[11]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[11]), + .ZN(n_1_0_225) + ); + AOI22_X1_LVT i_1_0_236( + .A1(registers_5__ap[11]), .A2(n_1_0_635), .B1(n_1_0_615), .B2(registers_23__ap[11]), + .ZN(n_1_0_224) + ); + NAND3_X1_LVT i_1_0_235( + .A1(n_1_0_227), .A2(n_1_0_225), .A3(n_1_0_224), .ZN(n_1_0_223) + ); + AOI221_X1_LVT i_1_0_234( + .A(n_1_0_223), .B1(n_1_0_637), .B2(registers_31__ap[11]), .C1(registers_16__ap[11]), + .C2(n_1_0_614), .ZN(n_1_0_222) + ); + AOI222_X1_LVT i_1_0_233( + .A1(registers_8__ap[11]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[11]), + .C1(n_1_0_622), .C2(registers_30__ap[11]), .ZN(n_1_0_221) + ); + NAND3_X1_LVT i_1_0_232( + .A1(n_1_0_226), .A2(n_1_0_222), .A3(n_1_0_221), .ZN(n_1_0_220) + ); + AOI221_X1_LVT i_1_0_231( + .A(n_1_0_220), .B1(n_1_0_638), .B2(registers_4__ap[11]), .C1(registers_28__ap[11]), + .C2(n_1_0_634), .ZN(n_1_0_219) + ); + AOI22_X1_LVT i_1_0_230( + .A1(registers_18__ap[11]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[11]), + .ZN(n_1_0_218) + ); + AOI22_X1_LVT i_1_0_229( + .A1(registers_12__ap[11]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[11]), + .ZN(n_1_0_217) + ); + AOI22_X1_LVT i_1_0_228( + .A1(registers_22__ap[11]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[11]), + .ZN(n_1_0_216) + ); + NAND3_X1_LVT i_1_0_227( + .A1(n_1_0_218), .A2(n_1_0_217), .A3(n_1_0_216), .ZN(n_1_0_215) + ); + AOI221_X1_LVT i_1_0_226( + .A(n_1_0_215), .B1(n_1_0_613), .B2(registers_20__ap[11]), .C1(registers_17__ap[11]), + .C2(n_1_0_629), .ZN(n_1_0_214) + ); + AOI22_X1_LVT i_1_0_225( + .A1(registers_13__ap[11]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[11]), + .ZN(n_1_0_213) + ); + AOI22_X1_LVT i_1_0_224( + .A1(registers_7__ap[11]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[11]), + .ZN(n_1_0_212) + ); + AOI22_X1_LVT i_1_0_223( + .A1(registers_19__ap[11]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[11]), + .ZN(n_1_0_211) + ); + NAND3_X1_LVT i_1_0_222( + .A1(n_1_0_213), .A2(n_1_0_212), .A3(n_1_0_211), .ZN(n_1_0_210) + ); + AOI221_X1_LVT i_1_0_221( + .A(n_1_0_210), .B1(n_1_0_611), .B2(registers_11__ap[11]), .C1(registers_2__ap[11]), + .C2(n_1_0_618), .ZN(n_1_0_209) + ); + NAND3_X1_LVT i_1_0_220( + .A1(n_1_0_219), .A2(n_1_0_214), .A3(n_1_0_209), .ZN(RRs2[11]) + ); + AOI22_X1_LVT i_1_0_219( + .A1(registers_28__ap[10]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[10]), + .ZN(n_1_0_208) + ); + AOI222_X1_LVT i_1_0_218( + .A1(registers_26__ap[10]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[10]), + .C1(registers_25__ap[10]), .C2(n_1_0_620), .ZN(n_1_0_207) + ); + AOI22_X1_LVT i_1_0_217( + .A1(registers_13__ap[10]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[10]), + .ZN(n_1_0_206) + ); + AOI22_X1_LVT i_1_0_216( + .A1(registers_24__ap[10]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[10]), + .ZN(n_1_0_205) + ); + AOI22_X1_LVT i_1_0_215( + .A1(registers_15__ap[10]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[10]), + .ZN(n_1_0_204) + ); + AOI22_X1_LVT i_1_0_214( + .A1(registers_31__ap[10]), .A2(n_1_0_637), .B1(n_1_0_629), .B2(registers_17__ap[10]), + .ZN(n_1_0_203) + ); + AOI22_X1_LVT i_1_0_213( + .A1(registers_29__ap[10]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[10]), + .ZN(n_1_0_202) + ); + NAND4_X1_LVT i_1_0_212( + .A1(n_1_0_205), .A2(n_1_0_204), .A3(n_1_0_203), .A4(n_1_0_202), .ZN(n_1_0_201) + ); + AOI22_X1_LVT i_1_0_211( + .A1(registers_18__ap[10]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[10]), + .ZN(n_1_0_200) + ); + AOI22_X1_LVT i_1_0_210( + .A1(registers_4__ap[10]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[10]), + .ZN(n_1_0_199) + ); + AOI22_X1_LVT i_1_0_209( + .A1(registers_7__ap[10]), .A2(n_1_0_623), .B1(n_1_0_614), .B2(registers_16__ap[10]), + .ZN(n_1_0_198) + ); + AOI22_X1_LVT i_1_0_208( + .A1(registers_22__ap[10]), .A2(n_1_0_642), .B1(n_1_0_635), .B2(registers_5__ap[10]), + .ZN(n_1_0_197) + ); + NAND4_X1_LVT i_1_0_207( + .A1(n_1_0_200), .A2(n_1_0_199), .A3(n_1_0_198), .A4(n_1_0_197), .ZN(n_1_0_196) + ); + AOI22_X1_LVT i_1_0_206( + .A1(registers_1__ap[10]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[10]), + .ZN(n_1_0_195) + ); + AOI22_X1_LVT i_1_0_205( + .A1(registers_14__ap[10]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[10]), + .ZN(n_1_0_194) + ); + AOI22_X1_LVT i_1_0_204( + .A1(registers_19__ap[10]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[10]), + .ZN(n_1_0_193) + ); + AOI22_X1_LVT i_1_0_203( + .A1(registers_27__ap[10]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[10]), + .ZN(n_1_0_192) + ); + NAND4_X1_LVT i_1_0_202( + .A1(n_1_0_195), .A2(n_1_0_194), .A3(n_1_0_193), .A4(n_1_0_192), .ZN(n_1_0_191) + ); + NOR3_X1_LVT i_1_0_201( + .A1(n_1_0_201), .A2(n_1_0_196), .A3(n_1_0_191), .ZN(n_1_0_190) + ); + NAND4_X1_LVT i_1_0_200( + .A1(n_1_0_208), .A2(n_1_0_207), .A3(n_1_0_206), .A4(n_1_0_190), .ZN(RRs2[10]) + ); + AOI22_X1_LVT i_1_0_196( + .A1(registers_13__ap[9]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[9]), + .ZN(n_1_0_186) + ); + AOI22_X1_LVT i_1_0_199( + .A1(registers_29__ap[9]), .A2(n_1_0_649), .B1(n_1_0_636), .B2(registers_27__ap[9]), + .ZN(n_1_0_189) + ); + AOI22_X1_LVT i_1_0_195( + .A1(registers_24__ap[9]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[9]), + .ZN(n_1_0_185) + ); + AOI22_X1_LVT i_1_0_198( + .A1(registers_31__ap[9]), .A2(n_1_0_637), .B1(n_1_0_627), .B2(registers_15__ap[9]), + .ZN(n_1_0_188) + ); + INV_X1_LVT i_1_0_197( + .A(n_1_0_188), .ZN(n_1_0_187) + ); + AOI221_X1_LVT i_1_0_194( + .A(n_1_0_187), .B1(n_1_0_615), .B2(registers_23__ap[9]), .C1(registers_4__ap[9]), + .C2(n_1_0_638), .ZN(n_1_0_184) + ); + AOI222_X1_LVT i_1_0_193( + .A1(registers_18__ap[9]), .A2(n_1_0_646), .B1(n_1_0_624), .B2(registers_10__ap[9]), + .C1(registers_25__ap[9]), .C2(n_1_0_620), .ZN(n_1_0_183) + ); + NAND4_X1_LVT i_1_0_192( + .A1(n_1_0_189), .A2(n_1_0_185), .A3(n_1_0_184), .A4(n_1_0_183), .ZN(n_1_0_182) + ); + AOI221_X1_LVT i_1_0_191( + .A(n_1_0_182), .B1(n_1_0_626), .B2(registers_8__ap[9]), .C1(registers_28__ap[9]), + .C2(n_1_0_634), .ZN(n_1_0_181) + ); + AOI22_X1_LVT i_1_0_190( + .A1(registers_26__ap[9]), .A2(n_1_0_640), .B1(n_1_0_622), .B2(registers_30__ap[9]), + .ZN(n_1_0_180) + ); + AOI22_X1_LVT i_1_0_189( + .A1(registers_12__ap[9]), .A2(n_1_0_632), .B1(n_1_0_629), .B2(registers_17__ap[9]), + .ZN(n_1_0_179) + ); + AOI22_X1_LVT i_1_0_188( + .A1(registers_5__ap[9]), .A2(n_1_0_635), .B1(n_1_0_623), .B2(registers_7__ap[9]), + .ZN(n_1_0_178) + ); + NAND3_X1_LVT i_1_0_187( + .A1(n_1_0_180), .A2(n_1_0_179), .A3(n_1_0_178), .ZN(n_1_0_177) + ); + AOI221_X1_LVT i_1_0_186( + .A(n_1_0_177), .B1(n_1_0_642), .B2(registers_22__ap[9]), .C1(registers_16__ap[9]), + .C2(n_1_0_614), .ZN(n_1_0_176) + ); + AOI22_X1_LVT i_1_0_185( + .A1(registers_1__ap[9]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[9]), + .ZN(n_1_0_175) + ); + AOI22_X1_LVT i_1_0_184( + .A1(registers_14__ap[9]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[9]), + .ZN(n_1_0_174) + ); + AOI22_X1_LVT i_1_0_183( + .A1(registers_19__ap[9]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[9]), + .ZN(n_1_0_173) + ); + NAND3_X1_LVT i_1_0_182( + .A1(n_1_0_175), .A2(n_1_0_174), .A3(n_1_0_173), .ZN(n_1_0_172) + ); + AOI221_X1_LVT i_1_0_181( + .A(n_1_0_172), .B1(n_1_0_611), .B2(registers_11__ap[9]), .C1(registers_2__ap[9]), + .C2(n_1_0_618), .ZN(n_1_0_171) + ); + NAND4_X1_LVT i_1_0_180( + .A1(n_1_0_186), .A2(n_1_0_181), .A3(n_1_0_176), .A4(n_1_0_171), .ZN(RRs2[9]) + ); + AOI22_X1_LVT i_1_0_179( + .A1(registers_28__ap[8]), .A2(n_1_0_634), .B1(n_1_0_629), .B2(registers_17__ap[8]), + .ZN(n_1_0_170) + ); + AOI222_X1_LVT i_1_0_178( + .A1(registers_26__ap[8]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[8]), + .C1(n_1_0_626), .C2(registers_8__ap[8]), .ZN(n_1_0_169) + ); + AOI22_X1_LVT i_1_0_177( + .A1(registers_29__ap[8]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[8]), + .ZN(n_1_0_168) + ); + AOI22_X1_LVT i_1_0_176( + .A1(registers_1__ap[8]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[8]), + .ZN(n_1_0_167) + ); + AOI22_X1_LVT i_1_0_175( + .A1(registers_5__ap[8]), .A2(n_1_0_635), .B1(n_1_0_610), .B2(registers_3__ap[8]), + .ZN(n_1_0_166) + ); + AOI22_X1_LVT i_1_0_174( + .A1(registers_31__ap[8]), .A2(n_1_0_637), .B1(n_1_0_614), .B2(registers_16__ap[8]), + .ZN(n_1_0_165) + ); + AOI22_X1_LVT i_1_0_173( + .A1(registers_15__ap[8]), .A2(n_1_0_627), .B1(n_1_0_615), .B2(registers_23__ap[8]), + .ZN(n_1_0_164) + ); + NAND4_X1_LVT i_1_0_172( + .A1(n_1_0_167), .A2(n_1_0_166), .A3(n_1_0_165), .A4(n_1_0_164), .ZN(n_1_0_163) + ); + AOI22_X1_LVT i_1_0_171( + .A1(registers_18__ap[8]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[8]), + .ZN(n_1_0_162) + ); + AOI22_X1_LVT i_1_0_170( + .A1(registers_4__ap[8]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[8]), + .ZN(n_1_0_161) + ); + AOI22_X1_LVT i_1_0_169( + .A1(registers_22__ap[8]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[8]), + .ZN(n_1_0_160) + ); + AOI22_X1_LVT i_1_0_168( + .A1(registers_12__ap[8]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[8]), + .ZN(n_1_0_159) + ); + NAND4_X1_LVT i_1_0_167( + .A1(n_1_0_162), .A2(n_1_0_161), .A3(n_1_0_160), .A4(n_1_0_159), .ZN(n_1_0_158) + ); + AOI22_X1_LVT i_1_0_166( + .A1(registers_13__ap[8]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[8]), + .ZN(n_1_0_157) + ); + AOI22_X1_LVT i_1_0_165( + .A1(registers_7__ap[8]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[8]), + .ZN(n_1_0_156) + ); + AOI22_X1_LVT i_1_0_164( + .A1(registers_19__ap[8]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[8]), + .ZN(n_1_0_155) + ); + AOI22_X1_LVT i_1_0_163( + .A1(registers_27__ap[8]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[8]), + .ZN(n_1_0_154) + ); + NAND4_X1_LVT i_1_0_162( + .A1(n_1_0_157), .A2(n_1_0_156), .A3(n_1_0_155), .A4(n_1_0_154), .ZN(n_1_0_153) + ); + NOR3_X1_LVT i_1_0_161( + .A1(n_1_0_163), .A2(n_1_0_158), .A3(n_1_0_153), .ZN(n_1_0_152) + ); + NAND4_X1_LVT i_1_0_160( + .A1(n_1_0_170), .A2(n_1_0_169), .A3(n_1_0_168), .A4(n_1_0_152), .ZN(RRs2[8]) + ); + AOI22_X1_LVT i_1_0_159( + .A1(registers_28__ap[7]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[7]), + .ZN(n_1_0_151) + ); + AOI222_X1_LVT i_1_0_158( + .A1(registers_26__ap[7]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[7]), + .C1(registers_25__ap[7]), .C2(n_1_0_620), .ZN(n_1_0_150) + ); + AOI22_X1_LVT i_1_0_157( + .A1(registers_24__ap[7]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[7]), + .ZN(n_1_0_149) + ); + AOI22_X1_LVT i_1_0_156( + .A1(registers_15__ap[7]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[7]), + .ZN(n_1_0_148) + ); + AOI22_X1_LVT i_1_0_155( + .A1(registers_31__ap[7]), .A2(n_1_0_637), .B1(n_1_0_629), .B2(registers_17__ap[7]), + .ZN(n_1_0_147) + ); + AOI22_X1_LVT i_1_0_154( + .A1(registers_29__ap[7]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[7]), + .ZN(n_1_0_146) + ); + NAND4_X1_LVT i_1_0_153( + .A1(n_1_0_149), .A2(n_1_0_148), .A3(n_1_0_147), .A4(n_1_0_146), .ZN(n_1_0_145) + ); + AOI221_X1_LVT i_1_0_152( + .A(n_1_0_145), .B1(n_1_0_612), .B2(registers_21__ap[7]), .C1(registers_13__ap[7]), + .C2(n_1_0_631), .ZN(n_1_0_144) + ); + AOI22_X1_LVT i_1_0_151( + .A1(registers_18__ap[7]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[7]), + .ZN(n_1_0_143) + ); + AOI22_X1_LVT i_1_0_150( + .A1(registers_4__ap[7]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[7]), + .ZN(n_1_0_142) + ); + AOI22_X1_LVT i_1_0_149( + .A1(registers_5__ap[7]), .A2(n_1_0_635), .B1(n_1_0_623), .B2(registers_7__ap[7]), + .ZN(n_1_0_141) + ); + AOI22_X1_LVT i_1_0_148( + .A1(registers_22__ap[7]), .A2(n_1_0_642), .B1(n_1_0_614), .B2(registers_16__ap[7]), + .ZN(n_1_0_140) + ); + NAND4_X1_LVT i_1_0_147( + .A1(n_1_0_143), .A2(n_1_0_142), .A3(n_1_0_141), .A4(n_1_0_140), .ZN(n_1_0_139) + ); + AOI22_X1_LVT i_1_0_146( + .A1(registers_1__ap[7]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[7]), + .ZN(n_1_0_138) + ); + AOI22_X1_LVT i_1_0_145( + .A1(registers_14__ap[7]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[7]), + .ZN(n_1_0_137) + ); + AOI22_X1_LVT i_1_0_144( + .A1(registers_19__ap[7]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[7]), + .ZN(n_1_0_136) + ); + AOI22_X1_LVT i_1_0_143( + .A1(registers_27__ap[7]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[7]), + .ZN(n_1_0_135) + ); + NAND4_X1_LVT i_1_0_142( + .A1(n_1_0_138), .A2(n_1_0_137), .A3(n_1_0_136), .A4(n_1_0_135), .ZN(n_1_0_134) + ); + NOR2_X1_LVT i_1_0_141( + .A1(n_1_0_139), .A2(n_1_0_134), .ZN(n_1_0_133) + ); + NAND4_X1_LVT i_1_0_140( + .A1(n_1_0_151), .A2(n_1_0_150), .A3(n_1_0_144), .A4(n_1_0_133), .ZN(RRs2[7]) + ); + AOI22_X1_LVT i_1_0_136( + .A1(registers_13__ap[6]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[6]), + .ZN(n_1_0_129) + ); + AOI22_X1_LVT i_1_0_139( + .A1(registers_29__ap[6]), .A2(n_1_0_649), .B1(n_1_0_636), .B2(registers_27__ap[6]), + .ZN(n_1_0_132) + ); + AOI22_X1_LVT i_1_0_135( + .A1(registers_24__ap[6]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[6]), + .ZN(n_1_0_128) + ); + AOI22_X1_LVT i_1_0_138( + .A1(registers_31__ap[6]), .A2(n_1_0_637), .B1(n_1_0_627), .B2(registers_15__ap[6]), + .ZN(n_1_0_131) + ); + INV_X1_LVT i_1_0_137( + .A(n_1_0_131), .ZN(n_1_0_130) + ); + AOI221_X1_LVT i_1_0_134( + .A(n_1_0_130), .B1(n_1_0_638), .B2(registers_4__ap[6]), .C1(registers_23__ap[6]), + .C2(n_1_0_615), .ZN(n_1_0_127) + ); + AOI222_X1_LVT i_1_0_133( + .A1(registers_18__ap[6]), .A2(n_1_0_646), .B1(n_1_0_620), .B2(registers_25__ap[6]), + .C1(n_1_0_624), .C2(registers_10__ap[6]), .ZN(n_1_0_126) + ); + NAND4_X1_LVT i_1_0_132( + .A1(n_1_0_132), .A2(n_1_0_128), .A3(n_1_0_127), .A4(n_1_0_126), .ZN(n_1_0_125) + ); + AOI221_X1_LVT i_1_0_131( + .A(n_1_0_125), .B1(n_1_0_626), .B2(registers_8__ap[6]), .C1(registers_28__ap[6]), + .C2(n_1_0_634), .ZN(n_1_0_124) + ); + AOI22_X1_LVT i_1_0_130( + .A1(registers_26__ap[6]), .A2(n_1_0_640), .B1(n_1_0_622), .B2(registers_30__ap[6]), + .ZN(n_1_0_123) + ); + AOI22_X1_LVT i_1_0_129( + .A1(registers_12__ap[6]), .A2(n_1_0_632), .B1(n_1_0_629), .B2(registers_17__ap[6]), + .ZN(n_1_0_122) + ); + AOI22_X1_LVT i_1_0_128( + .A1(registers_7__ap[6]), .A2(n_1_0_623), .B1(n_1_0_614), .B2(registers_16__ap[6]), + .ZN(n_1_0_121) + ); + NAND3_X1_LVT i_1_0_127( + .A1(n_1_0_123), .A2(n_1_0_122), .A3(n_1_0_121), .ZN(n_1_0_120) + ); + AOI221_X1_LVT i_1_0_126( + .A(n_1_0_120), .B1(n_1_0_642), .B2(registers_22__ap[6]), .C1(registers_5__ap[6]), + .C2(n_1_0_635), .ZN(n_1_0_119) + ); + AOI22_X1_LVT i_1_0_125( + .A1(registers_1__ap[6]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[6]), + .ZN(n_1_0_118) + ); + AOI22_X1_LVT i_1_0_124( + .A1(registers_14__ap[6]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[6]), + .ZN(n_1_0_117) + ); + AOI22_X1_LVT i_1_0_123( + .A1(registers_19__ap[6]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[6]), + .ZN(n_1_0_116) + ); + NAND3_X1_LVT i_1_0_122( + .A1(n_1_0_118), .A2(n_1_0_117), .A3(n_1_0_116), .ZN(n_1_0_115) + ); + AOI221_X1_LVT i_1_0_121( + .A(n_1_0_115), .B1(n_1_0_618), .B2(registers_2__ap[6]), .C1(registers_11__ap[6]), + .C2(n_1_0_611), .ZN(n_1_0_114) + ); + NAND4_X1_LVT i_1_0_120( + .A1(n_1_0_129), .A2(n_1_0_124), .A3(n_1_0_119), .A4(n_1_0_114), .ZN(RRs2[6]) + ); + AOI22_X1_LVT i_1_0_118( + .A1(registers_28__ap[5]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[5]), + .ZN(n_1_0_112) + ); + AOI22_X1_LVT i_1_0_119( + .A1(registers_31__ap[5]), .A2(n_1_0_637), .B1(n_1_0_627), .B2(registers_15__ap[5]), + .ZN(n_1_0_113) + ); + AOI22_X1_LVT i_1_0_117( + .A1(registers_24__ap[5]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[5]), + .ZN(n_1_0_111) + ); + AOI22_X1_LVT i_1_0_116( + .A1(registers_17__ap[5]), .A2(n_1_0_629), .B1(n_1_0_615), .B2(registers_23__ap[5]), + .ZN(n_1_0_110) + ); + NAND3_X1_LVT i_1_0_115( + .A1(n_1_0_113), .A2(n_1_0_111), .A3(n_1_0_110), .ZN(n_1_0_109) + ); + AOI221_X1_LVT i_1_0_114( + .A(n_1_0_109), .B1(n_1_0_636), .B2(registers_27__ap[5]), .C1(registers_29__ap[5]), + .C2(n_1_0_649), .ZN(n_1_0_108) + ); + AOI222_X1_LVT i_1_0_113( + .A1(registers_10__ap[5]), .A2(n_1_0_624), .B1(n_1_0_620), .B2(registers_25__ap[5]), + .C1(registers_18__ap[5]), .C2(n_1_0_646), .ZN(n_1_0_107) + ); + NAND3_X1_LVT i_1_0_112( + .A1(n_1_0_112), .A2(n_1_0_108), .A3(n_1_0_107), .ZN(n_1_0_106) + ); + AOI221_X1_LVT i_1_0_111( + .A(n_1_0_106), .B1(n_1_0_612), .B2(registers_21__ap[5]), .C1(registers_13__ap[5]), + .C2(n_1_0_631), .ZN(n_1_0_105) + ); + AOI22_X1_LVT i_1_0_110( + .A1(registers_26__ap[5]), .A2(n_1_0_640), .B1(n_1_0_622), .B2(registers_30__ap[5]), + .ZN(n_1_0_104) + ); + AOI22_X1_LVT i_1_0_109( + .A1(registers_4__ap[5]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[5]), + .ZN(n_1_0_103) + ); + AOI22_X1_LVT i_1_0_108( + .A1(registers_5__ap[5]), .A2(n_1_0_635), .B1(n_1_0_623), .B2(registers_7__ap[5]), + .ZN(n_1_0_102) + ); + NAND3_X1_LVT i_1_0_107( + .A1(n_1_0_104), .A2(n_1_0_103), .A3(n_1_0_102), .ZN(n_1_0_101) + ); + AOI221_X1_LVT i_1_0_106( + .A(n_1_0_101), .B1(n_1_0_642), .B2(registers_22__ap[5]), .C1(registers_16__ap[5]), + .C2(n_1_0_614), .ZN(n_1_0_100) + ); + AOI22_X1_LVT i_1_0_105( + .A1(registers_1__ap[5]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[5]), + .ZN(n_1_0_99) + ); + AOI22_X1_LVT i_1_0_104( + .A1(registers_14__ap[5]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[5]), + .ZN(n_1_0_98) + ); + AOI22_X1_LVT i_1_0_103( + .A1(registers_19__ap[5]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[5]), + .ZN(n_1_0_97) + ); + NAND3_X1_LVT i_1_0_102( + .A1(n_1_0_99), .A2(n_1_0_98), .A3(n_1_0_97), .ZN(n_1_0_96) + ); + AOI221_X1_LVT i_1_0_101( + .A(n_1_0_96), .B1(n_1_0_611), .B2(registers_11__ap[5]), .C1(registers_2__ap[5]), + .C2(n_1_0_618), .ZN(n_1_0_95) + ); + NAND3_X1_LVT i_1_0_100( + .A1(n_1_0_105), .A2(n_1_0_100), .A3(n_1_0_95), .ZN(RRs2[5]) + ); + AOI22_X1_LVT i_1_0_99( + .A1(registers_4__ap[4]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[4]), + .ZN(n_1_0_94) + ); + AOI222_X1_LVT i_1_0_98( + .A1(registers_8__ap[4]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[4]), + .C1(n_1_0_622), .C2(registers_30__ap[4]), .ZN(n_1_0_93) + ); + AOI22_X1_LVT i_1_0_97( + .A1(registers_29__ap[4]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[4]), + .ZN(n_1_0_92) + ); + AOI22_X1_LVT i_1_0_96( + .A1(registers_1__ap[4]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[4]), + .ZN(n_1_0_91) + ); + AOI22_X1_LVT i_1_0_95( + .A1(registers_27__ap[4]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[4]), + .ZN(n_1_0_90) + ); + AOI22_X1_LVT i_1_0_94( + .A1(registers_23__ap[4]), .A2(n_1_0_615), .B1(n_1_0_614), .B2(registers_16__ap[4]), + .ZN(n_1_0_89) + ); + AOI22_X1_LVT i_1_0_93( + .A1(registers_31__ap[4]), .A2(n_1_0_637), .B1(n_1_0_635), .B2(registers_5__ap[4]), + .ZN(n_1_0_88) + ); + NAND4_X1_LVT i_1_0_92( + .A1(n_1_0_91), .A2(n_1_0_90), .A3(n_1_0_89), .A4(n_1_0_88), .ZN(n_1_0_87) + ); + AOI22_X1_LVT i_1_0_91( + .A1(registers_18__ap[4]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[4]), + .ZN(n_1_0_86) + ); + AOI22_X1_LVT i_1_0_90( + .A1(registers_12__ap[4]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[4]), + .ZN(n_1_0_85) + ); + AOI22_X1_LVT i_1_0_89( + .A1(registers_22__ap[4]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[4]), + .ZN(n_1_0_84) + ); + AOI22_X1_LVT i_1_0_88( + .A1(registers_17__ap[4]), .A2(n_1_0_629), .B1(n_1_0_613), .B2(registers_20__ap[4]), + .ZN(n_1_0_83) + ); + NAND4_X1_LVT i_1_0_87( + .A1(n_1_0_86), .A2(n_1_0_85), .A3(n_1_0_84), .A4(n_1_0_83), .ZN(n_1_0_82) + ); + AOI22_X1_LVT i_1_0_86( + .A1(registers_13__ap[4]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[4]), + .ZN(n_1_0_81) + ); + AOI22_X1_LVT i_1_0_85( + .A1(registers_7__ap[4]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[4]), + .ZN(n_1_0_80) + ); + AOI22_X1_LVT i_1_0_84( + .A1(registers_19__ap[4]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[4]), + .ZN(n_1_0_79) + ); + AOI22_X1_LVT i_1_0_83( + .A1(registers_2__ap[4]), .A2(n_1_0_618), .B1(n_1_0_611), .B2(registers_11__ap[4]), + .ZN(n_1_0_78) + ); + NAND4_X1_LVT i_1_0_82( + .A1(n_1_0_81), .A2(n_1_0_80), .A3(n_1_0_79), .A4(n_1_0_78), .ZN(n_1_0_77) + ); + NOR3_X1_LVT i_1_0_81( + .A1(n_1_0_87), .A2(n_1_0_82), .A3(n_1_0_77), .ZN(n_1_0_76) + ); + NAND4_X1_LVT i_1_0_80( + .A1(n_1_0_94), .A2(n_1_0_93), .A3(n_1_0_92), .A4(n_1_0_76), .ZN(RRs2[4]) + ); + AOI22_X1_LVT i_1_0_78( + .A1(registers_29__ap[3]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[3]), + .ZN(n_1_0_74) + ); + AOI22_X1_LVT i_1_0_79( + .A1(registers_27__ap[3]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[3]), + .ZN(n_1_0_75) + ); + AOI22_X1_LVT i_1_0_77( + .A1(registers_1__ap[3]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[3]), + .ZN(n_1_0_73) + ); + AOI22_X1_LVT i_1_0_76( + .A1(registers_5__ap[3]), .A2(n_1_0_635), .B1(n_1_0_611), .B2(registers_11__ap[3]), + .ZN(n_1_0_72) + ); + NAND3_X1_LVT i_1_0_75( + .A1(n_1_0_75), .A2(n_1_0_73), .A3(n_1_0_72), .ZN(n_1_0_71) + ); + AOI221_X1_LVT i_1_0_74( + .A(n_1_0_71), .B1(n_1_0_614), .B2(registers_16__ap[3]), .C1(registers_31__ap[3]), + .C2(n_1_0_637), .ZN(n_1_0_70) + ); + AOI222_X1_LVT i_1_0_73( + .A1(registers_8__ap[3]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[3]), + .C1(n_1_0_622), .C2(registers_30__ap[3]), .ZN(n_1_0_69) + ); + NAND3_X1_LVT i_1_0_72( + .A1(n_1_0_74), .A2(n_1_0_70), .A3(n_1_0_69), .ZN(n_1_0_68) + ); + AOI221_X1_LVT i_1_0_71( + .A(n_1_0_68), .B1(n_1_0_638), .B2(registers_4__ap[3]), .C1(registers_28__ap[3]), + .C2(n_1_0_634), .ZN(n_1_0_67) + ); + AOI22_X1_LVT i_1_0_70( + .A1(registers_18__ap[3]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[3]), + .ZN(n_1_0_66) + ); + AOI22_X1_LVT i_1_0_69( + .A1(registers_12__ap[3]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[3]), + .ZN(n_1_0_65) + ); + AOI22_X1_LVT i_1_0_68( + .A1(registers_22__ap[3]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[3]), + .ZN(n_1_0_64) + ); + NAND3_X1_LVT i_1_0_67( + .A1(n_1_0_66), .A2(n_1_0_65), .A3(n_1_0_64), .ZN(n_1_0_63) + ); + AOI221_X1_LVT i_1_0_66( + .A(n_1_0_63), .B1(n_1_0_613), .B2(registers_20__ap[3]), .C1(registers_17__ap[3]), + .C2(n_1_0_629), .ZN(n_1_0_62) + ); + AOI22_X1_LVT i_1_0_65( + .A1(registers_13__ap[3]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[3]), + .ZN(n_1_0_61) + ); + AOI22_X1_LVT i_1_0_64( + .A1(registers_7__ap[3]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[3]), + .ZN(n_1_0_60) + ); + AOI22_X1_LVT i_1_0_63( + .A1(registers_19__ap[3]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[3]), + .ZN(n_1_0_59) + ); + NAND3_X1_LVT i_1_0_62( + .A1(n_1_0_61), .A2(n_1_0_60), .A3(n_1_0_59), .ZN(n_1_0_58) + ); + AOI221_X1_LVT i_1_0_61( + .A(n_1_0_58), .B1(n_1_0_618), .B2(registers_2__ap[3]), .C1(registers_23__ap[3]), + .C2(n_1_0_615), .ZN(n_1_0_57) + ); + NAND3_X1_LVT i_1_0_60( + .A1(n_1_0_67), .A2(n_1_0_62), .A3(n_1_0_57), .ZN(RRs2[3]) + ); + AOI22_X1_LVT i_1_0_58( + .A1(registers_29__ap[2]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[2]), + .ZN(n_1_0_55) + ); + AOI22_X1_LVT i_1_0_59( + .A1(registers_27__ap[2]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[2]), + .ZN(n_1_0_56) + ); + AOI22_X1_LVT i_1_0_57( + .A1(registers_1__ap[2]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[2]), + .ZN(n_1_0_54) + ); + AOI22_X1_LVT i_1_0_56( + .A1(registers_5__ap[2]), .A2(n_1_0_635), .B1(n_1_0_615), .B2(registers_23__ap[2]), + .ZN(n_1_0_53) + ); + NAND3_X1_LVT i_1_0_55( + .A1(n_1_0_56), .A2(n_1_0_54), .A3(n_1_0_53), .ZN(n_1_0_52) + ); + AOI221_X1_LVT i_1_0_54( + .A(n_1_0_52), .B1(n_1_0_637), .B2(registers_31__ap[2]), .C1(registers_16__ap[2]), + .C2(n_1_0_614), .ZN(n_1_0_51) + ); + AOI222_X1_LVT i_1_0_53( + .A1(registers_8__ap[2]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[2]), + .C1(n_1_0_622), .C2(registers_30__ap[2]), .ZN(n_1_0_50) + ); + NAND3_X1_LVT i_1_0_52( + .A1(n_1_0_55), .A2(n_1_0_51), .A3(n_1_0_50), .ZN(n_1_0_49) + ); + AOI221_X1_LVT i_1_0_51( + .A(n_1_0_49), .B1(n_1_0_638), .B2(registers_4__ap[2]), .C1(registers_28__ap[2]), + .C2(n_1_0_634), .ZN(n_1_0_48) + ); + AOI22_X1_LVT i_1_0_50( + .A1(registers_18__ap[2]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[2]), + .ZN(n_1_0_47) + ); + AOI22_X1_LVT i_1_0_49( + .A1(registers_12__ap[2]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[2]), + .ZN(n_1_0_46) + ); + AOI22_X1_LVT i_1_0_48( + .A1(registers_22__ap[2]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[2]), + .ZN(n_1_0_45) + ); + NAND3_X1_LVT i_1_0_47( + .A1(n_1_0_47), .A2(n_1_0_46), .A3(n_1_0_45), .ZN(n_1_0_44) + ); + AOI221_X1_LVT i_1_0_46( + .A(n_1_0_44), .B1(n_1_0_629), .B2(registers_17__ap[2]), .C1(registers_20__ap[2]), + .C2(n_1_0_613), .ZN(n_1_0_43) + ); + AOI22_X1_LVT i_1_0_45( + .A1(registers_13__ap[2]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[2]), + .ZN(n_1_0_42) + ); + AOI22_X1_LVT i_1_0_44( + .A1(registers_7__ap[2]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[2]), + .ZN(n_1_0_41) + ); + AOI22_X1_LVT i_1_0_43( + .A1(registers_19__ap[2]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[2]), + .ZN(n_1_0_40) + ); + NAND3_X1_LVT i_1_0_42( + .A1(n_1_0_42), .A2(n_1_0_41), .A3(n_1_0_40), .ZN(n_1_0_39) + ); + AOI221_X1_LVT i_1_0_41( + .A(n_1_0_39), .B1(n_1_0_618), .B2(registers_2__ap[2]), .C1(registers_11__ap[2]), + .C2(n_1_0_611), .ZN(n_1_0_38) + ); + NAND3_X1_LVT i_1_0_40( + .A1(n_1_0_48), .A2(n_1_0_43), .A3(n_1_0_38), .ZN(RRs2[2]) + ); + AOI22_X1_LVT i_1_0_38( + .A1(registers_29__ap[1]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[1]), + .ZN(n_1_0_36) + ); + AOI22_X1_LVT i_1_0_39( + .A1(registers_16__ap[1]), .A2(n_1_0_614), .B1(n_1_0_610), .B2(registers_3__ap[1]), + .ZN(n_1_0_37) + ); + AOI22_X1_LVT i_1_0_37( + .A1(registers_1__ap[1]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[1]), + .ZN(n_1_0_35) + ); + AOI22_X1_LVT i_1_0_36( + .A1(registers_31__ap[1]), .A2(n_1_0_637), .B1(n_1_0_635), .B2(registers_5__ap[1]), + .ZN(n_1_0_34) + ); + NAND3_X1_LVT i_1_0_35( + .A1(n_1_0_37), .A2(n_1_0_35), .A3(n_1_0_34), .ZN(n_1_0_33) + ); + AOI221_X1_LVT i_1_0_34( + .A(n_1_0_33), .B1(n_1_0_627), .B2(registers_15__ap[1]), .C1(registers_23__ap[1]), + .C2(n_1_0_615), .ZN(n_1_0_32) + ); + AOI222_X1_LVT i_1_0_33( + .A1(registers_26__ap[1]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[1]), + .C1(n_1_0_626), .C2(registers_8__ap[1]), .ZN(n_1_0_31) + ); + NAND3_X1_LVT i_1_0_32( + .A1(n_1_0_36), .A2(n_1_0_32), .A3(n_1_0_31), .ZN(n_1_0_30) + ); + AOI221_X1_LVT i_1_0_31( + .A(n_1_0_30), .B1(n_1_0_629), .B2(registers_17__ap[1]), .C1(registers_28__ap[1]), + .C2(n_1_0_634), .ZN(n_1_0_29) + ); + AOI22_X1_LVT i_1_0_30( + .A1(registers_18__ap[1]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[1]), + .ZN(n_1_0_28) + ); + AOI22_X1_LVT i_1_0_29( + .A1(registers_4__ap[1]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[1]), + .ZN(n_1_0_27) + ); + AOI22_X1_LVT i_1_0_28( + .A1(registers_22__ap[1]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[1]), + .ZN(n_1_0_26) + ); + NAND3_X1_LVT i_1_0_27( + .A1(n_1_0_28), .A2(n_1_0_27), .A3(n_1_0_26), .ZN(n_1_0_25) + ); + AOI221_X1_LVT i_1_0_26( + .A(n_1_0_25), .B1(n_1_0_632), .B2(registers_12__ap[1]), .C1(registers_24__ap[1]), + .C2(n_1_0_621), .ZN(n_1_0_24) + ); + AOI22_X1_LVT i_1_0_25( + .A1(registers_13__ap[1]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[1]), + .ZN(n_1_0_23) + ); + AOI22_X1_LVT i_1_0_24( + .A1(registers_7__ap[1]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[1]), + .ZN(n_1_0_22) + ); + AOI22_X1_LVT i_1_0_23( + .A1(registers_19__ap[1]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[1]), + .ZN(n_1_0_21) + ); + NAND3_X1_LVT i_1_0_22( + .A1(n_1_0_23), .A2(n_1_0_22), .A3(n_1_0_21), .ZN(n_1_0_20) + ); + AOI221_X1_LVT i_1_0_21( + .A(n_1_0_20), .B1(n_1_0_611), .B2(registers_11__ap[1]), .C1(registers_27__ap[1]), + .C2(n_1_0_636), .ZN(n_1_0_19) + ); + NAND3_X1_LVT i_1_0_20( + .A1(n_1_0_29), .A2(n_1_0_24), .A3(n_1_0_19), .ZN(RRs2[1]) + ); + AOI22_X1_LVT i_1_0_19( + .A1(registers_4__ap[0]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[0]), + .ZN(n_1_0_18) + ); + AOI222_X1_LVT i_1_0_18( + .A1(registers_8__ap[0]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[0]), + .C1(n_1_0_622), .C2(registers_30__ap[0]), .ZN(n_1_0_17) + ); + AOI22_X1_LVT i_1_0_17( + .A1(registers_29__ap[0]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[0]), + .ZN(n_1_0_16) + ); + AOI22_X1_LVT i_1_0_16( + .A1(registers_1__ap[0]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[0]), + .ZN(n_1_0_15) + ); + AOI22_X1_LVT i_1_0_15( + .A1(registers_27__ap[0]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[0]), + .ZN(n_1_0_14) + ); + AOI22_X1_LVT i_1_0_14( + .A1(registers_23__ap[0]), .A2(n_1_0_615), .B1(n_1_0_614), .B2(registers_16__ap[0]), + .ZN(n_1_0_13) + ); + AOI22_X1_LVT i_1_0_13( + .A1(registers_31__ap[0]), .A2(n_1_0_637), .B1(n_1_0_635), .B2(registers_5__ap[0]), + .ZN(n_1_0_12) + ); + NAND4_X1_LVT i_1_0_12( + .A1(n_1_0_15), .A2(n_1_0_14), .A3(n_1_0_13), .A4(n_1_0_12), .ZN(n_1_0_11) + ); + AOI22_X1_LVT i_1_0_11( + .A1(registers_18__ap[0]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[0]), + .ZN(n_1_0_10) + ); + AOI22_X1_LVT i_1_0_10( + .A1(registers_12__ap[0]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[0]), + .ZN(n_1_0_9) + ); + AOI22_X1_LVT i_1_0_9( + .A1(registers_22__ap[0]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[0]), + .ZN(n_1_0_8) + ); + AOI22_X1_LVT i_1_0_8( + .A1(registers_17__ap[0]), .A2(n_1_0_629), .B1(n_1_0_613), .B2(registers_20__ap[0]), + .ZN(n_1_0_7) + ); + NAND4_X1_LVT i_1_0_7( + .A1(n_1_0_10), .A2(n_1_0_9), .A3(n_1_0_8), .A4(n_1_0_7), .ZN(n_1_0_6) + ); + AOI22_X1_LVT i_1_0_6( + .A1(registers_13__ap[0]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[0]), + .ZN(n_1_0_5) + ); + AOI22_X1_LVT i_1_0_5( + .A1(registers_7__ap[0]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[0]), + .ZN(n_1_0_4) + ); + AOI22_X1_LVT i_1_0_4( + .A1(registers_19__ap[0]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[0]), + .ZN(n_1_0_3) + ); + AOI22_X1_LVT i_1_0_3( + .A1(registers_2__ap[0]), .A2(n_1_0_618), .B1(n_1_0_611), .B2(registers_11__ap[0]), + .ZN(n_1_0_2) + ); + NAND4_X1_LVT i_1_0_2( + .A1(n_1_0_5), .A2(n_1_0_4), .A3(n_1_0_3), .A4(n_1_0_2), .ZN(n_1_0_1) + ); + NOR3_X1_LVT i_1_0_1( + .A1(n_1_0_11), .A2(n_1_0_6), .A3(n_1_0_1), .ZN(n_1_0_0) + ); + NAND4_X1_LVT i_1_0_0( + .A1(n_1_0_18), .A2(n_1_0_17), .A3(n_1_0_16), .A4(n_1_0_0), .ZN(RRs2[0]) + ); + DLL_X2_LVT ts_lockup_latchn_clkc2_intno1050_i( + .D(registers_1__ap[0]), .GN(n_0_0), .Q(ts_no1050) + ); + DLL_X2_LVT ts_lockup_latchn_clkc4_intno1051_i( + .D(registers_6__ap[0]), .GN(n_0_36), .Q(ts_no1051) + ); + DLL_X2_LVT ts_lockup_latchn_clkc3_intno1053_i( + .D(registers_27__ap[0]), .GN(n_0_57), .Q(ts_no1053) + ); + DLL_X2_LVT ts_lockup_latchn_clkc1_intno1054_i( + .D(registers_11__ap[0]), .GN(n_0_41), .Q(ts_no1054) + ); + CLKBUF_X3_LVT tessent_persistent_cell_buf_extsi1227_i( + .A(ts_extsi1227), .Z(ts_pbuf_extsi1227_) + ); + CLKBUF_X3_LVT tessent_persistent_cell_buf_extsi1228_i( + .A(ts_extsi1228), .Z(ts_pbuf_extsi1228_) + ); + CLKBUF_X3_LVT tessent_persistent_cell_buf_extsi1226_i( + .A(ts_extsi1226), .Z(ts_pbuf_extsi1226_) + ); +endmodule + +module cpu(led, btn, clk_25mhz, scan_en, SI_1, SO_1, SI_2, SO_2, SI_3, SO_3, SI_4, + SO_4); + input [6:0] btn; + input clk_25mhz, scan_en, SI_1, SI_2, SI_3, SI_4; + output [7:0] led; + output SO_1, SO_2, SO_3, SO_4; + + wire [31:0] Instruction, RData, RRs2, RRs1, WRd, DAddr, JumpOrBranchPC, + CurrentPC, NextPC; + wire [1:0] DWidth; + wire WrReg, JumpOrBranch, thePC_n_1, thePC_i_0_n_0, thePC_n_2, thePC_i_0_n_1, + thePC_n_3, thePC_i_0_n_2, thePC_n_4, thePC_i_0_n_3, thePC_n_5, + thePC_i_0_n_4, thePC_n_6, thePC_i_0_n_5, thePC_n_7, thePC_i_0_n_6, + thePC_n_8, thePC_i_0_n_7, thePC_n_9, thePC_i_0_n_8, thePC_n_10, + thePC_i_0_n_9, thePC_n_11, thePC_i_0_n_10, thePC_n_12, thePC_i_0_n_11, + thePC_n_13, thePC_i_0_n_12, thePC_n_14, thePC_i_0_n_13, thePC_n_15, + thePC_i_0_n_14, thePC_n_16, thePC_i_0_n_15, thePC_n_17, thePC_i_0_n_16, + thePC_n_18, thePC_i_0_n_17, thePC_n_19, thePC_i_0_n_18, thePC_n_20, + thePC_i_0_n_19, thePC_n_21, thePC_i_0_n_20, thePC_n_22, thePC_i_0_n_21, + thePC_n_23, thePC_i_0_n_22, thePC_n_24, thePC_i_0_n_23, thePC_n_25, + thePC_i_0_n_24, thePC_n_26, thePC_i_0_n_25, thePC_n_27, thePC_i_0_n_26, + thePC_n_28, thePC_i_0_n_27, thePC_n_29, thePC_n_0, thePC_n_30, n_0_0_0, + thePC_n_31, n_0_0_1, thePC_n_32, thePC_n_33, thePC_n_34, thePC_n_35, + thePC_n_36, thePC_n_37, thePC_n_38, thePC_n_39, thePC_n_40, thePC_n_41, + thePC_n_42, thePC_n_43, n_0_0_2, thePC_n_44, n_0_0_3, thePC_n_45, + n_0_0_4, thePC_n_46, n_0_0_5, thePC_n_47, n_0_0_6, thePC_n_48, n_0_0_7, + thePC_n_49, n_0_0_8, thePC_n_50, n_0_0_9, thePC_n_51, n_0_0_10, + thePC_n_52, n_0_0_11, thePC_n_53, n_0_0_12, thePC_n_54, n_0_0_13, + thePC_n_55, n_0_0_14, thePC_n_56, n_0_0_15, thePC_n_57, n_0_0_16, + thePC_n_58, n_0_0_17, thePC_n_59, n_0_0_18, thePC_n_60, n_0_0_19, + thePC_n_61, n_0_0_20, n_0_0_21, n_0_0_22, reset, uc_0, uc_1, uc_2, uc_3, + uc_4, uc_5, uc_6, uc_7, uc_8, uc_9, uc_10, uc_11, uc_12, uc_13, uc_14, + uc_15, uc_16, uc_17, uc_18, uc_19, uc_20, uc_21, uc_22, uc_23, uc_24, + uc_25, uc_26, uc_27, uc_28, uc_29, uc_30, uc_31, uc_32, uc_33, uc_34, + uc_35, uc_36, uc_37, uc_38, uc_39, uc_40, uc_41, uc_42, uc_43, uc_44, + uc_45, uc_46, uc_47, uc_48, uc_49, uc_50, uc_51, uc_52, uc_53, uc_54, + uc_55, uc_56, uc_57, uc_58, ts_pbuf_extsi1225_, ts_no1054, ts_no1050, + ts_no1053, ts_no1051; + + assign SO_1 = ts_no1054; + assign SO_2 = ts_no1050; + assign SO_3 = ts_no1053; + assign SO_4 = ts_no1051; + AND2_X1_LVT i_0_0_54( + .A1(JumpOrBranch), .A2(btn[0]), .ZN(n_0_0_22) + ); + INV_X1_LVT i_0_0_66( + .A(btn[0]), .ZN(reset) + ); + NOR2_X1_LVT i_0_0_53( + .A1(reset), .A2(JumpOrBranch), .ZN(n_0_0_21) + ); + AOI22_X1_LVT i_0_0_50( + .A1(JumpOrBranchPC[30]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_28), .ZN(n_0_0_19) + ); + INV_X1_LVT i_0_0_49( + .A(n_0_0_19), .ZN(thePC_n_60) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[30] ( + .CK(clk_25mhz), .D(thePC_n_60), .Q(CurrentPC[30]), .QN(), .SE(scan_en), .SI(ts_pbuf_extsi1225_) + ); + AOI22_X1_LVT i_0_0_48( + .A1(JumpOrBranchPC[29]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_27), .ZN(n_0_0_18) + ); + INV_X1_LVT i_0_0_47( + .A(n_0_0_18), .ZN(thePC_n_59) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[29] ( + .CK(clk_25mhz), .D(thePC_n_59), .Q(CurrentPC[29]), .QN(), .SE(scan_en), .SI(CurrentPC[30]) + ); + AOI22_X1_LVT i_0_0_46( + .A1(JumpOrBranchPC[28]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_26), .ZN(n_0_0_17) + ); + INV_X1_LVT i_0_0_45( + .A(n_0_0_17), .ZN(thePC_n_58) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[28] ( + .CK(clk_25mhz), .D(thePC_n_58), .Q(CurrentPC[28]), .QN(), .SE(scan_en), .SI(CurrentPC[29]) + ); + AOI22_X1_LVT i_0_0_44( + .A1(JumpOrBranchPC[27]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_25), .ZN(n_0_0_16) + ); + INV_X1_LVT i_0_0_43( + .A(n_0_0_16), .ZN(thePC_n_57) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[27] ( + .CK(clk_25mhz), .D(thePC_n_57), .Q(CurrentPC[27]), .QN(), .SE(scan_en), .SI(CurrentPC[28]) + ); + AOI22_X1_LVT i_0_0_42( + .A1(JumpOrBranchPC[26]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_24), .ZN(n_0_0_15) + ); + INV_X1_LVT i_0_0_41( + .A(n_0_0_15), .ZN(thePC_n_56) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[26] ( + .CK(clk_25mhz), .D(thePC_n_56), .Q(CurrentPC[26]), .QN(), .SE(scan_en), .SI(CurrentPC[27]) + ); + AOI22_X1_LVT i_0_0_40( + .A1(JumpOrBranchPC[25]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_23), .ZN(n_0_0_14) + ); + INV_X1_LVT i_0_0_39( + .A(n_0_0_14), .ZN(thePC_n_55) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[25] ( + .CK(clk_25mhz), .D(thePC_n_55), .Q(CurrentPC[25]), .QN(), .SE(scan_en), .SI(CurrentPC[26]) + ); + AOI22_X1_LVT i_0_0_38( + .A1(JumpOrBranchPC[24]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_22), .ZN(n_0_0_13) + ); + INV_X1_LVT i_0_0_37( + .A(n_0_0_13), .ZN(thePC_n_54) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[24] ( + .CK(clk_25mhz), .D(thePC_n_54), .Q(CurrentPC[24]), .QN(), .SE(scan_en), .SI(CurrentPC[25]) + ); + AOI22_X1_LVT i_0_0_36( + .A1(JumpOrBranchPC[23]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_21), .ZN(n_0_0_12) + ); + INV_X1_LVT i_0_0_35( + .A(n_0_0_12), .ZN(thePC_n_53) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[23] ( + .CK(clk_25mhz), .D(thePC_n_53), .Q(CurrentPC[23]), .QN(), .SE(scan_en), .SI(CurrentPC[24]) + ); + AOI22_X1_LVT i_0_0_34( + .A1(JumpOrBranchPC[22]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_20), .ZN(n_0_0_11) + ); + INV_X1_LVT i_0_0_33( + .A(n_0_0_11), .ZN(thePC_n_52) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[22] ( + .CK(clk_25mhz), .D(thePC_n_52), .Q(CurrentPC[22]), .QN(), .SE(scan_en), .SI(CurrentPC[23]) + ); + AOI22_X1_LVT i_0_0_32( + .A1(JumpOrBranchPC[21]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_19), .ZN(n_0_0_10) + ); + INV_X1_LVT i_0_0_31( + .A(n_0_0_10), .ZN(thePC_n_51) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[21] ( + .CK(clk_25mhz), .D(thePC_n_51), .Q(CurrentPC[21]), .QN(), .SE(scan_en), .SI(CurrentPC[22]) + ); + AOI22_X1_LVT i_0_0_30( + .A1(JumpOrBranchPC[20]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_18), .ZN(n_0_0_9) + ); + INV_X1_LVT i_0_0_29( + .A(n_0_0_9), .ZN(thePC_n_50) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[20] ( + .CK(clk_25mhz), .D(thePC_n_50), .Q(CurrentPC[20]), .QN(), .SE(scan_en), .SI(CurrentPC[21]) + ); + AOI22_X1_LVT i_0_0_28( + .A1(JumpOrBranchPC[19]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_17), .ZN(n_0_0_8) + ); + INV_X1_LVT i_0_0_27( + .A(n_0_0_8), .ZN(thePC_n_49) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[19] ( + .CK(clk_25mhz), .D(thePC_n_49), .Q(CurrentPC[19]), .QN(), .SE(scan_en), .SI(CurrentPC[20]) + ); + AOI22_X1_LVT i_0_0_26( + .A1(JumpOrBranchPC[18]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_16), .ZN(n_0_0_7) + ); + INV_X1_LVT i_0_0_25( + .A(n_0_0_7), .ZN(thePC_n_48) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[18] ( + .CK(clk_25mhz), .D(thePC_n_48), .Q(CurrentPC[18]), .QN(), .SE(scan_en), .SI(CurrentPC[19]) + ); + AOI22_X1_LVT i_0_0_24( + .A1(JumpOrBranchPC[17]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_15), .ZN(n_0_0_6) + ); + INV_X1_LVT i_0_0_23( + .A(n_0_0_6), .ZN(thePC_n_47) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[17] ( + .CK(clk_25mhz), .D(thePC_n_47), .Q(CurrentPC[17]), .QN(), .SE(scan_en), .SI(CurrentPC[18]) + ); + AOI22_X1_LVT i_0_0_22( + .A1(JumpOrBranchPC[16]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_14), .ZN(n_0_0_5) + ); + INV_X1_LVT i_0_0_21( + .A(n_0_0_5), .ZN(thePC_n_46) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[16] ( + .CK(clk_25mhz), .D(thePC_n_46), .Q(CurrentPC[16]), .QN(), .SE(scan_en), .SI(CurrentPC[17]) + ); + AOI22_X1_LVT i_0_0_20( + .A1(JumpOrBranchPC[15]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_13), .ZN(n_0_0_4) + ); + INV_X1_LVT i_0_0_19( + .A(n_0_0_4), .ZN(thePC_n_45) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[15] ( + .CK(clk_25mhz), .D(thePC_n_45), .Q(CurrentPC[15]), .QN(), .SE(scan_en), .SI(CurrentPC[16]) + ); + AOI22_X1_LVT i_0_0_18( + .A1(JumpOrBranchPC[14]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_12), .ZN(n_0_0_3) + ); + INV_X1_LVT i_0_0_17( + .A(n_0_0_3), .ZN(thePC_n_44) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[14] ( + .CK(clk_25mhz), .D(thePC_n_44), .Q(CurrentPC[14]), .QN(), .SE(scan_en), .SI(CurrentPC[15]) + ); + AOI22_X1_LVT i_0_0_16( + .A1(JumpOrBranchPC[13]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_11), .ZN(n_0_0_2) + ); + INV_X1_LVT i_0_0_15( + .A(n_0_0_2), .ZN(thePC_n_43) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[13] ( + .CK(clk_25mhz), .D(thePC_n_43), .Q(CurrentPC[13]), .QN(), .SE(scan_en), .SI(CurrentPC[14]) + ); + MUX2_X1_LVT i_0_0_65( + .A(thePC_n_10), .B(JumpOrBranchPC[12]), .S(JumpOrBranch), .Z(NextPC[12]) + ); + AND2_X1_LVT i_0_0_14( + .A1(NextPC[12]), .A2(btn[0]), .ZN(thePC_n_42) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[12] ( + .CK(clk_25mhz), .D(thePC_n_42), .Q(CurrentPC[12]), .QN(), .SE(scan_en), .SI(CurrentPC[13]) + ); + MUX2_X1_LVT i_0_0_64( + .A(thePC_n_9), .B(JumpOrBranchPC[11]), .S(JumpOrBranch), .Z(NextPC[11]) + ); + AND2_X1_LVT i_0_0_13( + .A1(NextPC[11]), .A2(btn[0]), .ZN(thePC_n_41) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[11] ( + .CK(clk_25mhz), .D(thePC_n_41), .Q(CurrentPC[11]), .QN(), .SE(scan_en), .SI(CurrentPC[12]) + ); + MUX2_X1_LVT i_0_0_63( + .A(thePC_n_8), .B(JumpOrBranchPC[10]), .S(JumpOrBranch), .Z(NextPC[10]) + ); + AND2_X1_LVT i_0_0_12( + .A1(NextPC[10]), .A2(btn[0]), .ZN(thePC_n_40) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[10] ( + .CK(clk_25mhz), .D(thePC_n_40), .Q(CurrentPC[10]), .QN(), .SE(scan_en), .SI(CurrentPC[11]) + ); + MUX2_X1_LVT i_0_0_62( + .A(thePC_n_7), .B(JumpOrBranchPC[9]), .S(JumpOrBranch), .Z(NextPC[9]) + ); + AND2_X1_LVT i_0_0_11( + .A1(NextPC[9]), .A2(btn[0]), .ZN(thePC_n_39) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[9] ( + .CK(clk_25mhz), .D(thePC_n_39), .Q(CurrentPC[9]), .QN(), .SE(scan_en), .SI(CurrentPC[10]) + ); + MUX2_X1_LVT i_0_0_61( + .A(thePC_n_6), .B(JumpOrBranchPC[8]), .S(JumpOrBranch), .Z(NextPC[8]) + ); + AND2_X1_LVT i_0_0_10( + .A1(NextPC[8]), .A2(btn[0]), .ZN(thePC_n_38) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[8] ( + .CK(clk_25mhz), .D(thePC_n_38), .Q(CurrentPC[8]), .QN(), .SE(scan_en), .SI(CurrentPC[9]) + ); + AND2_X1_LVT i_0_0_9( + .A1(led[7]), .A2(btn[0]), .ZN(thePC_n_37) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[7] ( + .CK(clk_25mhz), .D(thePC_n_37), .Q(CurrentPC[7]), .QN(), .SE(scan_en), .SI(CurrentPC[8]) + ); + MUX2_X1_LVT i_0_0_59( + .A(thePC_n_4), .B(JumpOrBranchPC[6]), .S(JumpOrBranch), .Z(led[6]) + ); + AND2_X1_LVT i_0_0_8( + .A1(led[6]), .A2(btn[0]), .ZN(thePC_n_36) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[6] ( + .CK(clk_25mhz), .D(thePC_n_36), .Q(CurrentPC[6]), .QN(), .SE(scan_en), .SI(CurrentPC[7]) + ); + MUX2_X1_LVT i_0_0_58( + .A(thePC_n_3), .B(JumpOrBranchPC[5]), .S(JumpOrBranch), .Z(led[5]) + ); + AND2_X1_LVT i_0_0_7( + .A1(led[5]), .A2(btn[0]), .ZN(thePC_n_35) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[5] ( + .CK(clk_25mhz), .D(thePC_n_35), .Q(CurrentPC[5]), .QN(), .SE(scan_en), .SI(CurrentPC[6]) + ); + MUX2_X1_LVT i_0_0_57( + .A(thePC_n_2), .B(JumpOrBranchPC[4]), .S(JumpOrBranch), .Z(led[4]) + ); + AND2_X1_LVT i_0_0_6( + .A1(led[4]), .A2(btn[0]), .ZN(thePC_n_34) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[4] ( + .CK(clk_25mhz), .D(thePC_n_34), .Q(CurrentPC[4]), .QN(), .SE(scan_en), .SI(CurrentPC[5]) + ); + MUX2_X1_LVT i_0_0_56( + .A(thePC_n_1), .B(JumpOrBranchPC[3]), .S(JumpOrBranch), .Z(led[3]) + ); + AND2_X1_LVT i_0_0_5( + .A1(led[3]), .A2(btn[0]), .ZN(thePC_n_33) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[3] ( + .CK(clk_25mhz), .D(thePC_n_33), .Q(CurrentPC[3]), .QN(), .SE(scan_en), .SI(CurrentPC[4]) + ); + INV_X1_LVT thePC_i_0_29( + .A(CurrentPC[2]), .ZN(thePC_n_0) + ); + MUX2_X1_LVT i_0_0_55( + .A(thePC_n_0), .B(JumpOrBranchPC[2]), .S(JumpOrBranch), .Z(led[2]) + ); + AND2_X1_LVT i_0_0_4( + .A1(led[2]), .A2(btn[0]), .ZN(thePC_n_32) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[2] ( + .CK(clk_25mhz), .D(thePC_n_32), .Q(CurrentPC[2]), .QN(), .SE(scan_en), .SI(CurrentPC[3]) + ); + HA_X1_LVT thePC_i_0_0( + .A(CurrentPC[3]), .B(CurrentPC[2]), .CO(thePC_i_0_n_0), .S(thePC_n_1) + ); + HA_X1_LVT thePC_i_0_1( + .A(CurrentPC[4]), .B(thePC_i_0_n_0), .CO(thePC_i_0_n_1), .S(thePC_n_2) + ); + HA_X1_LVT thePC_i_0_2( + .A(CurrentPC[5]), .B(thePC_i_0_n_1), .CO(thePC_i_0_n_2), .S(thePC_n_3) + ); + HA_X1_LVT thePC_i_0_3( + .A(CurrentPC[6]), .B(thePC_i_0_n_2), .CO(thePC_i_0_n_3), .S(thePC_n_4) + ); + HA_X1_LVT thePC_i_0_4( + .A(CurrentPC[7]), .B(thePC_i_0_n_3), .CO(thePC_i_0_n_4), .S(thePC_n_5) + ); + HA_X1_LVT thePC_i_0_5( + .A(CurrentPC[8]), .B(thePC_i_0_n_4), .CO(thePC_i_0_n_5), .S(thePC_n_6) + ); + HA_X1_LVT thePC_i_0_6( + .A(CurrentPC[9]), .B(thePC_i_0_n_5), .CO(thePC_i_0_n_6), .S(thePC_n_7) + ); + HA_X1_LVT thePC_i_0_7( + .A(CurrentPC[10]), .B(thePC_i_0_n_6), .CO(thePC_i_0_n_7), .S(thePC_n_8) + ); + HA_X1_LVT thePC_i_0_8( + .A(CurrentPC[11]), .B(thePC_i_0_n_7), .CO(thePC_i_0_n_8), .S(thePC_n_9) + ); + HA_X1_LVT thePC_i_0_9( + .A(CurrentPC[12]), .B(thePC_i_0_n_8), .CO(thePC_i_0_n_9), .S(thePC_n_10) + ); + HA_X1_LVT thePC_i_0_11( + .A(CurrentPC[13]), .B(thePC_i_0_n_9), .CO(thePC_i_0_n_10), .S(thePC_n_11) + ); + HA_X1_LVT thePC_i_0_12( + .A(CurrentPC[14]), .B(thePC_i_0_n_10), .CO(thePC_i_0_n_11), .S(thePC_n_12) + ); + HA_X1_LVT thePC_i_0_13( + .A(CurrentPC[15]), .B(thePC_i_0_n_11), .CO(thePC_i_0_n_12), .S(thePC_n_13) + ); + HA_X1_LVT thePC_i_0_14( + .A(CurrentPC[16]), .B(thePC_i_0_n_12), .CO(thePC_i_0_n_13), .S(thePC_n_14) + ); + HA_X1_LVT thePC_i_0_15( + .A(CurrentPC[17]), .B(thePC_i_0_n_13), .CO(thePC_i_0_n_14), .S(thePC_n_15) + ); + HA_X1_LVT thePC_i_0_16( + .A(CurrentPC[18]), .B(thePC_i_0_n_14), .CO(thePC_i_0_n_15), .S(thePC_n_16) + ); + HA_X1_LVT thePC_i_0_17( + .A(CurrentPC[19]), .B(thePC_i_0_n_15), .CO(thePC_i_0_n_16), .S(thePC_n_17) + ); + HA_X1_LVT thePC_i_0_10( + .A(CurrentPC[20]), .B(thePC_i_0_n_16), .CO(thePC_i_0_n_17), .S(thePC_n_18) + ); + HA_X1_LVT thePC_i_0_18( + .A(CurrentPC[21]), .B(thePC_i_0_n_17), .CO(thePC_i_0_n_18), .S(thePC_n_19) + ); + HA_X1_LVT thePC_i_0_19( + .A(CurrentPC[22]), .B(thePC_i_0_n_18), .CO(thePC_i_0_n_19), .S(thePC_n_20) + ); + HA_X1_LVT thePC_i_0_20( + .A(CurrentPC[23]), .B(thePC_i_0_n_19), .CO(thePC_i_0_n_20), .S(thePC_n_21) + ); + HA_X1_LVT thePC_i_0_21( + .A(CurrentPC[24]), .B(thePC_i_0_n_20), .CO(thePC_i_0_n_21), .S(thePC_n_22) + ); + HA_X1_LVT thePC_i_0_22( + .A(CurrentPC[25]), .B(thePC_i_0_n_21), .CO(thePC_i_0_n_22), .S(thePC_n_23) + ); + HA_X1_LVT thePC_i_0_23( + .A(CurrentPC[26]), .B(thePC_i_0_n_22), .CO(thePC_i_0_n_23), .S(thePC_n_24) + ); + HA_X1_LVT thePC_i_0_24( + .A(CurrentPC[27]), .B(thePC_i_0_n_23), .CO(thePC_i_0_n_24), .S(thePC_n_25) + ); + HA_X1_LVT thePC_i_0_25( + .A(CurrentPC[28]), .B(thePC_i_0_n_24), .CO(thePC_i_0_n_25), .S(thePC_n_26) + ); + HA_X1_LVT thePC_i_0_26( + .A(CurrentPC[29]), .B(thePC_i_0_n_25), .CO(thePC_i_0_n_26), .S(thePC_n_27) + ); + HA_X1_LVT thePC_i_0_27( + .A(CurrentPC[30]), .B(thePC_i_0_n_26), .CO(thePC_i_0_n_27), .S(thePC_n_28) + ); + XOR2_X1_LVT thePC_i_0_28( + .A(CurrentPC[31]), .B(thePC_i_0_n_27), .Z(thePC_n_29) + ); + AOI22_X1_LVT i_0_0_52( + .A1(JumpOrBranchPC[31]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_29), .ZN(n_0_0_20) + ); + INV_X1_LVT i_0_0_51( + .A(n_0_0_20), .ZN(thePC_n_61) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[31] ( + .CK(clk_25mhz), .D(thePC_n_61), .Q(CurrentPC[31]), .QN(), .SE(scan_en), .SI(CurrentPC[2]) + ); + AOI22_X1_LVT i_0_0_3( + .A1(JumpOrBranchPC[1]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(CurrentPC[1]), + .ZN(n_0_0_1) + ); + INV_X1_LVT i_0_0_2( + .A(n_0_0_1), .ZN(thePC_n_31) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[1] ( + .CK(clk_25mhz), .D(thePC_n_31), .Q(CurrentPC[1]), .QN(), .SE(scan_en), .SI(CurrentPC[31]) + ); + AOI22_X1_LVT i_0_0_1( + .A1(JumpOrBranchPC[0]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(CurrentPC[0]), + .ZN(n_0_0_0) + ); + INV_X1_LVT i_0_0_0( + .A(n_0_0_0), .ZN(thePC_n_30) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[0] ( + .CK(clk_25mhz), .D(thePC_n_30), .Q(CurrentPC[0]), .QN(), .SE(scan_en), .SI(CurrentPC[1]) + ); + reg_file theRegisters( + .Rs1({Instruction[19], Instruction[18], Instruction[17], + Instruction[16], Instruction[15]}), .Rs2({Instruction[24], + Instruction[23], Instruction[22], Instruction[21], Instruction[20]}), .Rd({ + Instruction[11], Instruction[10], Instruction[9], Instruction[8], + Instruction[7]}), .RRs1(RRs1), .RRs2(RRs2), .WRd(WRd), .WrReg(WrReg), .reset(reset), + .clk(clk_25mhz), .dftIn(scan_en), .ts_intno31(CurrentPC[0]), .ts_no1050(ts_no1050), + .ts_no1051(ts_no1051), .ts_no1053(ts_no1053), .ts_no1054(ts_no1054), .ts_extsi1226(SI_2), + .ts_extsi1227(SI_3), .ts_extsi1228(SI_4) + ); + main_mem theMem( + .clk(clk_25mhz), .reset(reset), .DAddr({uc_0, uc_1, uc_2, uc_3, uc_4, + uc_5, uc_6, uc_7, uc_8, uc_9, uc_10, uc_11, uc_12, uc_13, uc_14, uc_15, + uc_16, uc_17, uc_18, DAddr[12], DAddr[11], DAddr[10], DAddr[9], + DAddr[8], DAddr[7], DAddr[6], DAddr[5], DAddr[4], DAddr[3], DAddr[2], + DAddr[1], DAddr[0]}), .IAddr({uc_19, uc_20, uc_21, uc_22, uc_23, uc_24, + uc_25, uc_26, uc_27, uc_28, uc_29, uc_30, uc_31, uc_32, uc_33, uc_34, + uc_35, uc_36, uc_37, NextPC[12], NextPC[11], NextPC[10], NextPC[9], + NextPC[8], led[7], led[6], led[5], led[4], led[3], led[2], uc_38, uc_39}), + .DWData(RRs2), .DRData(RData), .IRData(Instruction), .DWE(led[1]), .DWidth(DWidth) + ); + decoder theDecoder( + .CurrentPC(CurrentPC), .JumpOrBranchPC(JumpOrBranchPC), .JumpOrBranch(JumpOrBranch), + .DAddr({uc_40, uc_41, uc_42, uc_43, uc_44, uc_45, uc_46, uc_47, uc_48, + uc_49, uc_50, uc_51, uc_52, uc_53, uc_54, uc_55, uc_56, uc_57, uc_58, + DAddr[12], DAddr[11], DAddr[10], DAddr[9], DAddr[8], DAddr[7], DAddr[6], + DAddr[5], DAddr[4], DAddr[3], DAddr[2], DAddr[1], DAddr[0]}), .WData(), .RData(RData), + .Instruction(Instruction), .WrMem(led[1]), .DWidth(DWidth), .Rs1(), .Rs2(), + .Rd(), .RRs1(RRs1), .RRs2(RRs2), .WRd(WRd), .WrReg(WrReg), .Illegal(led[0]) + ); + MUX2_X1_LVT i_0_0_60( + .A(thePC_n_5), .B(JumpOrBranchPC[7]), .S(JumpOrBranch), .Z(led[7]) + ); + CLKBUF_X3_LVT tessent_persistent_cell_buf_extsi1225_i( + .A(SI_1), .Z(ts_pbuf_extsi1225_) + ); +endmodule + diff --git a/oasys.tessent.01/Scan_0/scan.do b/oasys.tessent.01/Scan_0/scan.do new file mode 100644 index 0000000..b2c7816 --- /dev/null +++ b/oasys.tessent.01/Scan_0/scan.do @@ -0,0 +1,57 @@ +set_context dft -scan -no_rtl -design_id Scan_0 +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_low_temp_ccs.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_low_temp_ccs.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/PLL.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/IO.fslib +set_module_matching_options -suffix_pattern_list {{[_]+[0-9]+[_]+[0-9]+}} -regexp -append +set_module_matching_options -suffix_pattern_list {{[_]+[A-Z]+}} -regexp -append +set_module_matching_options -suffix_pattern_list {{[_]+[0-9]+[_]+[0-9]+[_]+[A-Z]+}} -regexp -append +read_verilog /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.01/Scan_0/oasys_netlist.v +set_tsdb_output_directory /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.01/tsdb_outdir +if { [info exists ::env(OASYS_TCD_SCAN_FOLDER)] } { +set_design_sources -format tcd_scan -Y $::env(OASYS_TCD_SCAN_FOLDER) -extensions tcd_scan +} +read_sdc /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.01/Scan_0/oasys.sdc +set_current_design cpu -show_elaboration_warnings +set_design_level physical_block +set_shift_register_identification off + +add_nonscan_instances -instances {{/theMem/\IRData_reg[31] } {/theMem/\IRData_reg[30] } {/theMem/\IRData_reg[29] } {/theMem/\IRData_reg[28] } {/theMem/\IRData_reg[27] } {/theMem/\IRData_reg[26] } {/theMem/\IRData_reg[25] } {/theMem/\IRData_reg[24] } {/theMem/\IRData_reg[23] } {/theMem/\IRData_reg[22] } {/theMem/\IRData_reg[21] } {/theMem/\IRData_reg[20] } {/theMem/\IRData_reg[19] } {/theMem/\IRData_reg[18] } {/theMem/\IRData_reg[17] } {/theMem/\IRData_reg[16] } {/theMem/\IRData_reg[15] } {/theMem/\IRData_reg[14] } {/theMem/\IRData_reg[13] } {/theMem/\IRData_reg[12] } {/theMem/\IRData_reg[11] } {/theMem/\IRData_reg[10] } {/theMem/\IRData_reg[9] } {/theMem/\IRData_reg[8] } {/theMem/\IRData_reg[7] } {/theMem/\IRData_reg[6] } {/theMem/\IRData_reg[5] } {/theMem/\IRData_reg[4] } {/theMem/\IRData_reg[3] } {/theMem/\IRData_reg[2] } {/theMem/\IRData_reg[1] } {/theMem/\IRData_reg[0] } {/theMem/\mem_addr_reg[10] } {/theMem/\mem_addr_reg[9] } {/theMem/\mem_addr_reg[8] } {/theMem/\mem_addr_reg[7] } {/theMem/\mem_addr_reg[6] } {/theMem/\mem_addr_reg[5] } {/theMem/\mem_addr_reg[4] } {/theMem/\mem_addr_reg[3] } {/theMem/\mem_addr_reg[2] } {/theMem/\mem_addr_reg[1] } {/theMem/\mem_addr_reg[0] } {/theMem/\drTmp_reg[31] } {/theMem/\drTmp_reg[30] } {/theMem/\drTmp_reg[29] } {/theMem/\drTmp_reg[28] } {/theMem/\drTmp_reg[27] } {/theMem/\drTmp_reg[26] } {/theMem/\drTmp_reg[25] } {/theMem/\drTmp_reg[24] } {/theMem/\drTmp_reg[23] } {/theMem/\drTmp_reg[22] } {/theMem/\drTmp_reg[21] } {/theMem/\drTmp_reg[20] } {/theMem/\drTmp_reg[19] } {/theMem/\drTmp_reg[18] } {/theMem/\drTmp_reg[17] } {/theMem/\drTmp_reg[16] } {/theMem/\drTmp_reg[15] } {/theMem/\drTmp_reg[14] } {/theMem/\drTmp_reg[13] } {/theMem/\drTmp_reg[12] } {/theMem/\drTmp_reg[11] } {/theMem/\drTmp_reg[10] } {/theMem/\drTmp_reg[9] } {/theMem/\drTmp_reg[8] } {/theMem/\drTmp_reg[7] } {/theMem/\drTmp_reg[6] } {/theMem/\drTmp_reg[5] } {/theMem/\drTmp_reg[4] } {/theMem/\drTmp_reg[3] } {/theMem/\drTmp_reg[2] } {/theMem/\drTmp_reg[1] } {/theMem/\drTmp_reg[0] } {/theMem/\mem_wdata_reg[31] } {/theMem/\mem_wdata_reg[30] } {/theMem/\mem_wdata_reg[29] } {/theMem/\mem_wdata_reg[28] } {/theMem/\mem_wdata_reg[27] } {/theMem/\mem_wdata_reg[26] } {/theMem/\mem_wdata_reg[25] } {/theMem/\mem_wdata_reg[24] } {/theMem/\mem_wdata_reg[23] } {/theMem/\mem_wdata_reg[22] } {/theMem/\mem_wdata_reg[21] } {/theMem/\mem_wdata_reg[20] } {/theMem/\mem_wdata_reg[19] } {/theMem/\mem_wdata_reg[18] } {/theMem/\mem_wdata_reg[17] } {/theMem/\mem_wdata_reg[16] } {/theMem/\mem_wdata_reg[15] } {/theMem/\mem_wdata_reg[14] } {/theMem/\mem_wdata_reg[13] } {/theMem/\mem_wdata_reg[12] } {/theMem/\mem_wdata_reg[11] } {/theMem/\mem_wdata_reg[10] } {/theMem/\mem_wdata_reg[9] } {/theMem/\mem_wdata_reg[8] } {/theMem/\mem_wdata_reg[7] } {/theMem/\mem_wdata_reg[6] } {/theMem/\mem_wdata_reg[5] } {/theMem/\mem_wdata_reg[4] } {/theMem/\mem_wdata_reg[3] } {/theMem/\mem_wdata_reg[2] } {/theMem/\mem_wdata_reg[1] } {/theMem/\mem_wdata_reg[0] } } +if {[catch {get_clocks clk_25mhz > /dev/null }] && +[catch {get_dft_signal clk_25mhz > /dev/null }]} { +add_clocks 0 { clk_25mhz } +} + +set_scan_enable scan_en -active high +add_input_constraints btn[0] -C1 +set_scan_enable scan_en -active high -cluster_name scanChain_1 +set_scan_enable scan_en -active high -cluster_name scanChain_2 +set_scan_enable scan_en -active high -cluster_name scanChain_3 +set_scan_enable scan_en -active high -cluster_name scanChain_4 + +add_black_boxes -modules { MemGen_16_10 } +set_scan_insertion_options -single_clock_edge_chains on -si_port_format {oas_ts_si[%d]} -so_port_format {oas_ts_so[%d]} +set_system_mode analysis +report_drc_rules + +create_scan_chain_family scanChain_1 -include_elements {{/\thePC_CurrentPC_reg[0] } {/\thePC_CurrentPC_reg[10] } {/\thePC_CurrentPC_reg[11] } {/\thePC_CurrentPC_reg[12] } {/\thePC_CurrentPC_reg[13] } {/\thePC_CurrentPC_reg[14] } {/\thePC_CurrentPC_reg[15] } {/\thePC_CurrentPC_reg[16] } {/\thePC_CurrentPC_reg[17] } {/\thePC_CurrentPC_reg[18] } {/\thePC_CurrentPC_reg[19] } {/\thePC_CurrentPC_reg[1] } {/\thePC_CurrentPC_reg[20] } {/\thePC_CurrentPC_reg[21] } {/\thePC_CurrentPC_reg[22] } {/\thePC_CurrentPC_reg[23] } {/\thePC_CurrentPC_reg[24] } {/\thePC_CurrentPC_reg[25] } {/\thePC_CurrentPC_reg[26] } {/\thePC_CurrentPC_reg[27] } {/\thePC_CurrentPC_reg[28] } {/\thePC_CurrentPC_reg[29] } {/\thePC_CurrentPC_reg[2] } {/\thePC_CurrentPC_reg[30] } {/\thePC_CurrentPC_reg[31] } {/\thePC_CurrentPC_reg[3] } {/\thePC_CurrentPC_reg[4] } {/\thePC_CurrentPC_reg[5] } {/\thePC_CurrentPC_reg[6] } {/\thePC_CurrentPC_reg[7] } {/\thePC_CurrentPC_reg[8] } {/\thePC_CurrentPC_reg[9] } {/theRegisters/\registers_reg[10][0] } {/theRegisters/\registers_reg[10][10] } {/theRegisters/\registers_reg[10][11] } {/theRegisters/\registers_reg[10][12] } {/theRegisters/\registers_reg[10][13] } {/theRegisters/\registers_reg[10][14] } {/theRegisters/\registers_reg[10][15] } {/theRegisters/\registers_reg[10][16] } {/theRegisters/\registers_reg[10][17] } {/theRegisters/\registers_reg[10][18] } {/theRegisters/\registers_reg[10][19] } {/theRegisters/\registers_reg[10][1] } {/theRegisters/\registers_reg[10][20] } {/theRegisters/\registers_reg[10][21] } {/theRegisters/\registers_reg[10][22] } {/theRegisters/\registers_reg[10][23] } {/theRegisters/\registers_reg[10][24] } {/theRegisters/\registers_reg[10][25] } {/theRegisters/\registers_reg[10][26] } {/theRegisters/\registers_reg[10][27] } {/theRegisters/\registers_reg[10][28] } {/theRegisters/\registers_reg[10][29] } {/theRegisters/\registers_reg[10][2] } {/theRegisters/\registers_reg[10][30] } {/theRegisters/\registers_reg[10][31] } {/theRegisters/\registers_reg[10][3] } {/theRegisters/\registers_reg[10][4] } {/theRegisters/\registers_reg[10][5] } {/theRegisters/\registers_reg[10][6] } {/theRegisters/\registers_reg[10][7] } {/theRegisters/\registers_reg[10][8] } {/theRegisters/\registers_reg[10][9] } {/theRegisters/\registers_reg[11][0] } {/theRegisters/\registers_reg[11][10] } {/theRegisters/\registers_reg[11][11] } {/theRegisters/\registers_reg[11][12] } {/theRegisters/\registers_reg[11][13] } {/theRegisters/\registers_reg[11][14] } {/theRegisters/\registers_reg[11][15] } {/theRegisters/\registers_reg[11][16] } {/theRegisters/\registers_reg[11][17] } {/theRegisters/\registers_reg[11][18] } {/theRegisters/\registers_reg[11][19] } {/theRegisters/\registers_reg[11][1] } {/theRegisters/\registers_reg[11][20] } {/theRegisters/\registers_reg[11][21] } {/theRegisters/\registers_reg[11][22] } {/theRegisters/\registers_reg[11][23] } {/theRegisters/\registers_reg[11][24] } {/theRegisters/\registers_reg[11][25] } {/theRegisters/\registers_reg[11][26] } {/theRegisters/\registers_reg[11][27] } {/theRegisters/\registers_reg[11][28] } {/theRegisters/\registers_reg[11][29] } {/theRegisters/\registers_reg[11][2] } {/theRegisters/\registers_reg[11][30] } {/theRegisters/\registers_reg[11][31] } {/theRegisters/\registers_reg[11][3] } {/theRegisters/\registers_reg[11][4] } {/theRegisters/\registers_reg[11][5] } {/theRegisters/\registers_reg[11][6] } {/theRegisters/\registers_reg[11][7] } {/theRegisters/\registers_reg[11][8] } {/theRegisters/\registers_reg[11][9] } {/theRegisters/\registers_reg[12][0] } {/theRegisters/\registers_reg[12][10] } {/theRegisters/\registers_reg[12][11] } {/theRegisters/\registers_reg[12][12] } {/theRegisters/\registers_reg[12][13] } {/theRegisters/\registers_reg[12][14] } {/theRegisters/\registers_reg[12][15] } {/theRegisters/\registers_reg[12][16] } {/theRegisters/\registers_reg[12][17] } {/theRegisters/\registers_reg[12][18] } {/theRegisters/\registers_reg[12][19] } {/theRegisters/\registers_reg[12][1] } {/theRegisters/\registers_reg[12][20] } {/theRegisters/\registers_reg[12][21] } {/theRegisters/\registers_reg[12][22] } {/theRegisters/\registers_reg[12][23] } {/theRegisters/\registers_reg[12][24] } {/theRegisters/\registers_reg[12][25] } {/theRegisters/\registers_reg[12][26] } {/theRegisters/\registers_reg[12][27] } {/theRegisters/\registers_reg[12][28] } {/theRegisters/\registers_reg[12][29] } {/theRegisters/\registers_reg[12][2] } {/theRegisters/\registers_reg[12][30] } {/theRegisters/\registers_reg[12][31] } {/theRegisters/\registers_reg[12][3] } {/theRegisters/\registers_reg[12][4] } {/theRegisters/\registers_reg[12][5] } {/theRegisters/\registers_reg[12][6] } {/theRegisters/\registers_reg[12][7] } {/theRegisters/\registers_reg[12][8] } {/theRegisters/\registers_reg[12][9] } {/theRegisters/\registers_reg[13][0] } {/theRegisters/\registers_reg[13][10] } {/theRegisters/\registers_reg[13][11] } {/theRegisters/\registers_reg[13][12] } {/theRegisters/\registers_reg[13][13] } {/theRegisters/\registers_reg[13][14] } {/theRegisters/\registers_reg[13][15] } {/theRegisters/\registers_reg[13][16] } {/theRegisters/\registers_reg[13][17] } {/theRegisters/\registers_reg[13][18] } {/theRegisters/\registers_reg[13][19] } {/theRegisters/\registers_reg[13][1] } {/theRegisters/\registers_reg[13][20] } {/theRegisters/\registers_reg[13][21] } {/theRegisters/\registers_reg[13][22] } {/theRegisters/\registers_reg[13][23] } {/theRegisters/\registers_reg[13][24] } {/theRegisters/\registers_reg[13][25] } {/theRegisters/\registers_reg[13][26] } {/theRegisters/\registers_reg[13][27] } {/theRegisters/\registers_reg[13][28] } {/theRegisters/\registers_reg[13][29] } {/theRegisters/\registers_reg[13][2] } {/theRegisters/\registers_reg[13][30] } {/theRegisters/\registers_reg[13][31] } {/theRegisters/\registers_reg[13][3] } {/theRegisters/\registers_reg[13][4] } {/theRegisters/\registers_reg[13][5] } {/theRegisters/\registers_reg[13][6] } {/theRegisters/\registers_reg[13][7] } {/theRegisters/\registers_reg[13][8] } {/theRegisters/\registers_reg[13][9] } {/theRegisters/\registers_reg[14][0] } {/theRegisters/\registers_reg[14][10] } {/theRegisters/\registers_reg[14][11] } {/theRegisters/\registers_reg[14][12] } {/theRegisters/\registers_reg[14][13] } {/theRegisters/\registers_reg[14][14] } {/theRegisters/\registers_reg[14][15] } {/theRegisters/\registers_reg[14][16] } {/theRegisters/\registers_reg[14][17] } {/theRegisters/\registers_reg[14][18] } {/theRegisters/\registers_reg[14][19] } {/theRegisters/\registers_reg[14][1] } {/theRegisters/\registers_reg[14][20] } {/theRegisters/\registers_reg[14][21] } {/theRegisters/\registers_reg[14][22] } {/theRegisters/\registers_reg[14][23] } {/theRegisters/\registers_reg[14][24] } {/theRegisters/\registers_reg[14][25] } {/theRegisters/\registers_reg[14][26] } {/theRegisters/\registers_reg[14][27] } {/theRegisters/\registers_reg[14][28] } {/theRegisters/\registers_reg[14][29] } {/theRegisters/\registers_reg[14][2] } {/theRegisters/\registers_reg[14][30] } {/theRegisters/\registers_reg[14][31] } {/theRegisters/\registers_reg[14][3] } {/theRegisters/\registers_reg[14][4] } {/theRegisters/\registers_reg[14][5] } {/theRegisters/\registers_reg[14][6] } {/theRegisters/\registers_reg[14][7] } {/theRegisters/\registers_reg[14][8] } {/theRegisters/\registers_reg[14][9] } {/theRegisters/\registers_reg[15][0] } {/theRegisters/\registers_reg[15][10] } {/theRegisters/\registers_reg[15][11] } {/theRegisters/\registers_reg[15][12] } {/theRegisters/\registers_reg[15][13] } {/theRegisters/\registers_reg[15][14] } {/theRegisters/\registers_reg[15][15] } {/theRegisters/\registers_reg[15][16] } {/theRegisters/\registers_reg[15][17] } {/theRegisters/\registers_reg[15][18] } {/theRegisters/\registers_reg[15][19] } {/theRegisters/\registers_reg[15][1] } {/theRegisters/\registers_reg[15][20] } {/theRegisters/\registers_reg[15][21] } {/theRegisters/\registers_reg[15][22] } {/theRegisters/\registers_reg[15][23] } {/theRegisters/\registers_reg[15][24] } {/theRegisters/\registers_reg[15][25] } {/theRegisters/\registers_reg[15][26] } {/theRegisters/\registers_reg[15][27] } {/theRegisters/\registers_reg[15][28] } {/theRegisters/\registers_reg[15][29] } {/theRegisters/\registers_reg[15][2] } {/theRegisters/\registers_reg[15][30] } {/theRegisters/\registers_reg[15][31] } {/theRegisters/\registers_reg[15][3] } {/theRegisters/\registers_reg[15][4] } {/theRegisters/\registers_reg[15][5] } {/theRegisters/\registers_reg[15][6] } {/theRegisters/\registers_reg[15][7] } {/theRegisters/\registers_reg[15][8] } {/theRegisters/\registers_reg[15][9] } {/theRegisters/\registers_reg[16][0] } {/theRegisters/\registers_reg[16][10] } {/theRegisters/\registers_reg[16][11] } {/theRegisters/\registers_reg[16][12] } {/theRegisters/\registers_reg[16][13] } {/theRegisters/\registers_reg[16][14] } {/theRegisters/\registers_reg[16][15] } {/theRegisters/\registers_reg[16][16] } {/theRegisters/\registers_reg[16][17] } {/theRegisters/\registers_reg[16][18] } {/theRegisters/\registers_reg[16][19] } {/theRegisters/\registers_reg[16][1] } {/theRegisters/\registers_reg[16][20] } {/theRegisters/\registers_reg[16][21] } {/theRegisters/\registers_reg[16][22] } {/theRegisters/\registers_reg[16][23] } {/theRegisters/\registers_reg[16][24] } {/theRegisters/\registers_reg[16][25] } {/theRegisters/\registers_reg[16][26] } {/theRegisters/\registers_reg[16][27] } {/theRegisters/\registers_reg[16][28] } {/theRegisters/\registers_reg[16][29] } {/theRegisters/\registers_reg[16][2] } {/theRegisters/\registers_reg[16][30] } {/theRegisters/\registers_reg[16][31] } {/theRegisters/\registers_reg[16][3] } {/theRegisters/\registers_reg[16][4] } {/theRegisters/\registers_reg[16][5] } {/theRegisters/\registers_reg[16][6] } {/theRegisters/\registers_reg[16][7] } {/theRegisters/\registers_reg[16][8] } {/theRegisters/\registers_reg[16][9] } } -si_connections {SI_1 } -so_connections {SO_1 } -chain_count 1 +create_scan_chain_family scanChain_2 -include_elements {{/theRegisters/\registers_reg[17][0] } {/theRegisters/\registers_reg[17][10] } {/theRegisters/\registers_reg[17][11] } {/theRegisters/\registers_reg[17][12] } {/theRegisters/\registers_reg[17][13] } {/theRegisters/\registers_reg[17][14] } {/theRegisters/\registers_reg[17][15] } {/theRegisters/\registers_reg[17][16] } {/theRegisters/\registers_reg[17][17] } {/theRegisters/\registers_reg[17][18] } {/theRegisters/\registers_reg[17][19] } {/theRegisters/\registers_reg[17][1] } {/theRegisters/\registers_reg[17][20] } {/theRegisters/\registers_reg[17][21] } {/theRegisters/\registers_reg[17][22] } {/theRegisters/\registers_reg[17][23] } {/theRegisters/\registers_reg[17][24] } {/theRegisters/\registers_reg[17][25] } {/theRegisters/\registers_reg[17][26] } {/theRegisters/\registers_reg[17][27] } {/theRegisters/\registers_reg[17][28] } {/theRegisters/\registers_reg[17][29] } {/theRegisters/\registers_reg[17][2] } {/theRegisters/\registers_reg[17][30] } {/theRegisters/\registers_reg[17][31] } {/theRegisters/\registers_reg[17][3] } {/theRegisters/\registers_reg[17][4] } {/theRegisters/\registers_reg[17][5] } {/theRegisters/\registers_reg[17][6] } {/theRegisters/\registers_reg[17][7] } {/theRegisters/\registers_reg[17][8] } {/theRegisters/\registers_reg[17][9] } {/theRegisters/\registers_reg[18][0] } {/theRegisters/\registers_reg[18][10] } {/theRegisters/\registers_reg[18][11] } {/theRegisters/\registers_reg[18][12] } {/theRegisters/\registers_reg[18][13] } {/theRegisters/\registers_reg[18][14] } {/theRegisters/\registers_reg[18][15] } {/theRegisters/\registers_reg[18][16] } {/theRegisters/\registers_reg[18][17] } {/theRegisters/\registers_reg[18][18] } {/theRegisters/\registers_reg[18][19] } {/theRegisters/\registers_reg[18][1] } {/theRegisters/\registers_reg[18][20] } {/theRegisters/\registers_reg[18][21] } {/theRegisters/\registers_reg[18][22] } {/theRegisters/\registers_reg[18][23] } {/theRegisters/\registers_reg[18][24] } {/theRegisters/\registers_reg[18][25] } {/theRegisters/\registers_reg[18][26] } {/theRegisters/\registers_reg[18][27] } {/theRegisters/\registers_reg[18][28] } {/theRegisters/\registers_reg[18][29] } {/theRegisters/\registers_reg[18][2] } {/theRegisters/\registers_reg[18][30] } {/theRegisters/\registers_reg[18][31] } {/theRegisters/\registers_reg[18][3] } {/theRegisters/\registers_reg[18][4] } {/theRegisters/\registers_reg[18][5] } {/theRegisters/\registers_reg[18][6] } {/theRegisters/\registers_reg[18][7] } {/theRegisters/\registers_reg[18][8] } {/theRegisters/\registers_reg[18][9] } {/theRegisters/\registers_reg[19][0] } {/theRegisters/\registers_reg[19][10] } {/theRegisters/\registers_reg[19][11] } {/theRegisters/\registers_reg[19][12] } {/theRegisters/\registers_reg[19][13] } {/theRegisters/\registers_reg[19][14] } {/theRegisters/\registers_reg[19][15] } {/theRegisters/\registers_reg[19][16] } {/theRegisters/\registers_reg[19][17] } {/theRegisters/\registers_reg[19][18] } {/theRegisters/\registers_reg[19][19] } {/theRegisters/\registers_reg[19][1] } {/theRegisters/\registers_reg[19][20] } {/theRegisters/\registers_reg[19][21] } {/theRegisters/\registers_reg[19][22] } {/theRegisters/\registers_reg[19][23] } {/theRegisters/\registers_reg[19][24] } {/theRegisters/\registers_reg[19][25] } {/theRegisters/\registers_reg[19][26] } {/theRegisters/\registers_reg[19][27] } {/theRegisters/\registers_reg[19][28] } {/theRegisters/\registers_reg[19][29] } {/theRegisters/\registers_reg[19][2] } {/theRegisters/\registers_reg[19][30] } {/theRegisters/\registers_reg[19][31] } {/theRegisters/\registers_reg[19][3] } {/theRegisters/\registers_reg[19][4] } {/theRegisters/\registers_reg[19][5] } {/theRegisters/\registers_reg[19][6] } {/theRegisters/\registers_reg[19][7] } {/theRegisters/\registers_reg[19][8] } {/theRegisters/\registers_reg[19][9] } {/theRegisters/\registers_reg[1][0] } {/theRegisters/\registers_reg[1][10] } {/theRegisters/\registers_reg[1][11] } {/theRegisters/\registers_reg[1][12] } {/theRegisters/\registers_reg[1][13] } {/theRegisters/\registers_reg[1][14] } {/theRegisters/\registers_reg[1][15] } {/theRegisters/\registers_reg[1][16] } {/theRegisters/\registers_reg[1][17] } {/theRegisters/\registers_reg[1][18] } {/theRegisters/\registers_reg[1][19] } {/theRegisters/\registers_reg[1][1] } {/theRegisters/\registers_reg[1][20] } {/theRegisters/\registers_reg[1][21] } {/theRegisters/\registers_reg[1][22] } {/theRegisters/\registers_reg[1][23] } {/theRegisters/\registers_reg[1][24] } {/theRegisters/\registers_reg[1][25] } {/theRegisters/\registers_reg[1][26] } {/theRegisters/\registers_reg[1][27] } {/theRegisters/\registers_reg[1][28] } {/theRegisters/\registers_reg[1][29] } {/theRegisters/\registers_reg[1][2] } {/theRegisters/\registers_reg[1][30] } {/theRegisters/\registers_reg[1][31] } {/theRegisters/\registers_reg[1][3] } {/theRegisters/\registers_reg[1][4] } {/theRegisters/\registers_reg[1][5] } {/theRegisters/\registers_reg[1][6] } {/theRegisters/\registers_reg[1][7] } {/theRegisters/\registers_reg[1][8] } {/theRegisters/\registers_reg[1][9] } {/theRegisters/\registers_reg[20][0] } {/theRegisters/\registers_reg[20][10] } {/theRegisters/\registers_reg[20][11] } {/theRegisters/\registers_reg[20][12] } {/theRegisters/\registers_reg[20][13] } {/theRegisters/\registers_reg[20][14] } {/theRegisters/\registers_reg[20][15] } {/theRegisters/\registers_reg[20][16] } {/theRegisters/\registers_reg[20][17] } {/theRegisters/\registers_reg[20][18] } {/theRegisters/\registers_reg[20][19] } {/theRegisters/\registers_reg[20][1] } {/theRegisters/\registers_reg[20][20] } {/theRegisters/\registers_reg[20][21] } {/theRegisters/\registers_reg[20][22] } {/theRegisters/\registers_reg[20][23] } {/theRegisters/\registers_reg[20][24] } {/theRegisters/\registers_reg[20][25] } {/theRegisters/\registers_reg[20][26] } {/theRegisters/\registers_reg[20][27] } {/theRegisters/\registers_reg[20][28] } {/theRegisters/\registers_reg[20][29] } {/theRegisters/\registers_reg[20][2] } {/theRegisters/\registers_reg[20][30] } {/theRegisters/\registers_reg[20][31] } {/theRegisters/\registers_reg[20][3] } {/theRegisters/\registers_reg[20][4] } {/theRegisters/\registers_reg[20][5] } {/theRegisters/\registers_reg[20][6] } {/theRegisters/\registers_reg[20][7] } {/theRegisters/\registers_reg[20][8] } {/theRegisters/\registers_reg[20][9] } {/theRegisters/\registers_reg[21][0] } {/theRegisters/\registers_reg[21][10] } {/theRegisters/\registers_reg[21][11] } {/theRegisters/\registers_reg[21][12] } {/theRegisters/\registers_reg[21][13] } {/theRegisters/\registers_reg[21][14] } {/theRegisters/\registers_reg[21][15] } {/theRegisters/\registers_reg[21][16] } {/theRegisters/\registers_reg[21][17] } {/theRegisters/\registers_reg[21][18] } {/theRegisters/\registers_reg[21][19] } {/theRegisters/\registers_reg[21][1] } {/theRegisters/\registers_reg[21][20] } {/theRegisters/\registers_reg[21][21] } {/theRegisters/\registers_reg[21][22] } {/theRegisters/\registers_reg[21][23] } {/theRegisters/\registers_reg[21][24] } {/theRegisters/\registers_reg[21][25] } {/theRegisters/\registers_reg[21][26] } {/theRegisters/\registers_reg[21][27] } {/theRegisters/\registers_reg[21][28] } {/theRegisters/\registers_reg[21][29] } {/theRegisters/\registers_reg[21][2] } {/theRegisters/\registers_reg[21][30] } {/theRegisters/\registers_reg[21][31] } {/theRegisters/\registers_reg[21][3] } {/theRegisters/\registers_reg[21][4] } {/theRegisters/\registers_reg[21][5] } {/theRegisters/\registers_reg[21][6] } {/theRegisters/\registers_reg[21][7] } {/theRegisters/\registers_reg[21][8] } {/theRegisters/\registers_reg[21][9] } {/theRegisters/\registers_reg[22][0] } {/theRegisters/\registers_reg[22][10] } {/theRegisters/\registers_reg[22][11] } {/theRegisters/\registers_reg[22][12] } {/theRegisters/\registers_reg[22][13] } {/theRegisters/\registers_reg[22][14] } {/theRegisters/\registers_reg[22][15] } {/theRegisters/\registers_reg[22][16] } {/theRegisters/\registers_reg[22][17] } {/theRegisters/\registers_reg[22][18] } {/theRegisters/\registers_reg[22][19] } {/theRegisters/\registers_reg[22][1] } {/theRegisters/\registers_reg[22][20] } {/theRegisters/\registers_reg[22][21] } {/theRegisters/\registers_reg[22][22] } {/theRegisters/\registers_reg[22][23] } {/theRegisters/\registers_reg[22][24] } {/theRegisters/\registers_reg[22][25] } {/theRegisters/\registers_reg[22][26] } {/theRegisters/\registers_reg[22][27] } {/theRegisters/\registers_reg[22][28] } {/theRegisters/\registers_reg[22][29] } {/theRegisters/\registers_reg[22][2] } {/theRegisters/\registers_reg[22][30] } {/theRegisters/\registers_reg[22][31] } {/theRegisters/\registers_reg[22][3] } {/theRegisters/\registers_reg[22][4] } {/theRegisters/\registers_reg[22][5] } {/theRegisters/\registers_reg[22][6] } {/theRegisters/\registers_reg[22][7] } {/theRegisters/\registers_reg[22][8] } {/theRegisters/\registers_reg[22][9] } {/theRegisters/\registers_reg[23][0] } {/theRegisters/\registers_reg[23][10] } {/theRegisters/\registers_reg[23][11] } {/theRegisters/\registers_reg[23][12] } {/theRegisters/\registers_reg[23][13] } {/theRegisters/\registers_reg[23][14] } {/theRegisters/\registers_reg[23][15] } {/theRegisters/\registers_reg[23][16] } {/theRegisters/\registers_reg[23][17] } {/theRegisters/\registers_reg[23][18] } {/theRegisters/\registers_reg[23][19] } {/theRegisters/\registers_reg[23][1] } {/theRegisters/\registers_reg[23][20] } {/theRegisters/\registers_reg[23][21] } {/theRegisters/\registers_reg[23][22] } {/theRegisters/\registers_reg[23][23] } {/theRegisters/\registers_reg[23][24] } {/theRegisters/\registers_reg[23][25] } {/theRegisters/\registers_reg[23][26] } {/theRegisters/\registers_reg[23][27] } {/theRegisters/\registers_reg[23][28] } {/theRegisters/\registers_reg[23][29] } {/theRegisters/\registers_reg[23][2] } {/theRegisters/\registers_reg[23][30] } {/theRegisters/\registers_reg[23][31] } {/theRegisters/\registers_reg[23][3] } {/theRegisters/\registers_reg[23][4] } {/theRegisters/\registers_reg[23][5] } {/theRegisters/\registers_reg[23][6] } {/theRegisters/\registers_reg[23][7] } {/theRegisters/\registers_reg[23][8] } {/theRegisters/\registers_reg[23][9] } } -si_connections {SI_2 } -so_connections {SO_2 } -chain_count 1 +create_scan_chain_family scanChain_3 -include_elements {{/theRegisters/\registers_reg[24][0] } {/theRegisters/\registers_reg[24][10] } {/theRegisters/\registers_reg[24][11] } {/theRegisters/\registers_reg[24][12] } {/theRegisters/\registers_reg[24][13] } {/theRegisters/\registers_reg[24][14] } {/theRegisters/\registers_reg[24][15] } {/theRegisters/\registers_reg[24][16] } {/theRegisters/\registers_reg[24][17] } {/theRegisters/\registers_reg[24][18] } {/theRegisters/\registers_reg[24][19] } {/theRegisters/\registers_reg[24][1] } {/theRegisters/\registers_reg[24][20] } {/theRegisters/\registers_reg[24][21] } {/theRegisters/\registers_reg[24][22] } {/theRegisters/\registers_reg[24][23] } {/theRegisters/\registers_reg[24][24] } {/theRegisters/\registers_reg[24][25] } {/theRegisters/\registers_reg[24][26] } {/theRegisters/\registers_reg[24][27] } {/theRegisters/\registers_reg[24][28] } {/theRegisters/\registers_reg[24][29] } {/theRegisters/\registers_reg[24][2] } {/theRegisters/\registers_reg[24][30] } {/theRegisters/\registers_reg[24][31] } {/theRegisters/\registers_reg[24][3] } {/theRegisters/\registers_reg[24][4] } {/theRegisters/\registers_reg[24][5] } {/theRegisters/\registers_reg[24][6] } {/theRegisters/\registers_reg[24][7] } {/theRegisters/\registers_reg[24][8] } {/theRegisters/\registers_reg[24][9] } {/theRegisters/\registers_reg[25][0] } {/theRegisters/\registers_reg[25][10] } {/theRegisters/\registers_reg[25][11] } {/theRegisters/\registers_reg[25][12] } {/theRegisters/\registers_reg[25][13] } {/theRegisters/\registers_reg[25][14] } {/theRegisters/\registers_reg[25][15] } {/theRegisters/\registers_reg[25][16] } {/theRegisters/\registers_reg[25][17] } {/theRegisters/\registers_reg[25][18] } {/theRegisters/\registers_reg[25][19] } {/theRegisters/\registers_reg[25][1] } {/theRegisters/\registers_reg[25][20] } {/theRegisters/\registers_reg[25][21] } {/theRegisters/\registers_reg[25][22] } {/theRegisters/\registers_reg[25][23] } {/theRegisters/\registers_reg[25][24] } {/theRegisters/\registers_reg[25][25] } {/theRegisters/\registers_reg[25][26] } {/theRegisters/\registers_reg[25][27] } {/theRegisters/\registers_reg[25][28] } {/theRegisters/\registers_reg[25][29] } {/theRegisters/\registers_reg[25][2] } {/theRegisters/\registers_reg[25][30] } {/theRegisters/\registers_reg[25][31] } {/theRegisters/\registers_reg[25][3] } {/theRegisters/\registers_reg[25][4] } {/theRegisters/\registers_reg[25][5] } {/theRegisters/\registers_reg[25][6] } {/theRegisters/\registers_reg[25][7] } {/theRegisters/\registers_reg[25][8] } {/theRegisters/\registers_reg[25][9] } {/theRegisters/\registers_reg[26][0] } {/theRegisters/\registers_reg[26][10] } {/theRegisters/\registers_reg[26][11] } {/theRegisters/\registers_reg[26][12] } {/theRegisters/\registers_reg[26][13] } {/theRegisters/\registers_reg[26][14] } {/theRegisters/\registers_reg[26][15] } {/theRegisters/\registers_reg[26][16] } {/theRegisters/\registers_reg[26][17] } {/theRegisters/\registers_reg[26][18] } {/theRegisters/\registers_reg[26][19] } {/theRegisters/\registers_reg[26][1] } {/theRegisters/\registers_reg[26][20] } {/theRegisters/\registers_reg[26][21] } {/theRegisters/\registers_reg[26][22] } {/theRegisters/\registers_reg[26][23] } {/theRegisters/\registers_reg[26][24] } {/theRegisters/\registers_reg[26][25] } {/theRegisters/\registers_reg[26][26] } {/theRegisters/\registers_reg[26][27] } {/theRegisters/\registers_reg[26][28] } {/theRegisters/\registers_reg[26][29] } {/theRegisters/\registers_reg[26][2] } {/theRegisters/\registers_reg[26][30] } {/theRegisters/\registers_reg[26][31] } {/theRegisters/\registers_reg[26][3] } {/theRegisters/\registers_reg[26][4] } {/theRegisters/\registers_reg[26][5] } {/theRegisters/\registers_reg[26][6] } {/theRegisters/\registers_reg[26][7] } {/theRegisters/\registers_reg[26][8] } {/theRegisters/\registers_reg[26][9] } {/theRegisters/\registers_reg[27][0] } {/theRegisters/\registers_reg[27][10] } {/theRegisters/\registers_reg[27][11] } {/theRegisters/\registers_reg[27][12] } {/theRegisters/\registers_reg[27][13] } {/theRegisters/\registers_reg[27][14] } {/theRegisters/\registers_reg[27][15] } {/theRegisters/\registers_reg[27][16] } {/theRegisters/\registers_reg[27][17] } {/theRegisters/\registers_reg[27][18] } {/theRegisters/\registers_reg[27][19] } {/theRegisters/\registers_reg[27][1] } {/theRegisters/\registers_reg[27][20] } {/theRegisters/\registers_reg[27][21] } {/theRegisters/\registers_reg[27][22] } {/theRegisters/\registers_reg[27][23] } {/theRegisters/\registers_reg[27][24] } {/theRegisters/\registers_reg[27][25] } {/theRegisters/\registers_reg[27][26] } {/theRegisters/\registers_reg[27][27] } {/theRegisters/\registers_reg[27][28] } {/theRegisters/\registers_reg[27][29] } {/theRegisters/\registers_reg[27][2] } {/theRegisters/\registers_reg[27][30] } {/theRegisters/\registers_reg[27][31] } {/theRegisters/\registers_reg[27][3] } {/theRegisters/\registers_reg[27][4] } {/theRegisters/\registers_reg[27][5] } {/theRegisters/\registers_reg[27][6] } {/theRegisters/\registers_reg[27][7] } {/theRegisters/\registers_reg[27][8] } {/theRegisters/\registers_reg[27][9] } {/theRegisters/\registers_reg[28][0] } {/theRegisters/\registers_reg[28][10] } {/theRegisters/\registers_reg[28][11] } {/theRegisters/\registers_reg[28][12] } {/theRegisters/\registers_reg[28][13] } {/theRegisters/\registers_reg[28][14] } {/theRegisters/\registers_reg[28][15] } {/theRegisters/\registers_reg[28][16] } {/theRegisters/\registers_reg[28][17] } {/theRegisters/\registers_reg[28][18] } {/theRegisters/\registers_reg[28][19] } {/theRegisters/\registers_reg[28][1] } {/theRegisters/\registers_reg[28][20] } {/theRegisters/\registers_reg[28][21] } {/theRegisters/\registers_reg[28][22] } {/theRegisters/\registers_reg[28][23] } {/theRegisters/\registers_reg[28][24] } {/theRegisters/\registers_reg[28][25] } {/theRegisters/\registers_reg[28][26] } {/theRegisters/\registers_reg[28][27] } {/theRegisters/\registers_reg[28][28] } {/theRegisters/\registers_reg[28][29] } {/theRegisters/\registers_reg[28][2] } {/theRegisters/\registers_reg[28][30] } {/theRegisters/\registers_reg[28][31] } {/theRegisters/\registers_reg[28][3] } {/theRegisters/\registers_reg[28][4] } {/theRegisters/\registers_reg[28][5] } {/theRegisters/\registers_reg[28][6] } {/theRegisters/\registers_reg[28][7] } {/theRegisters/\registers_reg[28][8] } {/theRegisters/\registers_reg[28][9] } {/theRegisters/\registers_reg[29][0] } {/theRegisters/\registers_reg[29][10] } {/theRegisters/\registers_reg[29][11] } {/theRegisters/\registers_reg[29][12] } {/theRegisters/\registers_reg[29][13] } {/theRegisters/\registers_reg[29][14] } {/theRegisters/\registers_reg[29][15] } {/theRegisters/\registers_reg[29][16] } {/theRegisters/\registers_reg[29][17] } {/theRegisters/\registers_reg[29][18] } {/theRegisters/\registers_reg[29][19] } {/theRegisters/\registers_reg[29][1] } {/theRegisters/\registers_reg[29][20] } {/theRegisters/\registers_reg[29][21] } {/theRegisters/\registers_reg[29][22] } {/theRegisters/\registers_reg[29][23] } {/theRegisters/\registers_reg[29][24] } {/theRegisters/\registers_reg[29][25] } {/theRegisters/\registers_reg[29][26] } {/theRegisters/\registers_reg[29][27] } {/theRegisters/\registers_reg[29][28] } {/theRegisters/\registers_reg[29][29] } {/theRegisters/\registers_reg[29][2] } {/theRegisters/\registers_reg[29][30] } {/theRegisters/\registers_reg[29][31] } {/theRegisters/\registers_reg[29][3] } {/theRegisters/\registers_reg[29][4] } {/theRegisters/\registers_reg[29][5] } {/theRegisters/\registers_reg[29][6] } {/theRegisters/\registers_reg[29][7] } {/theRegisters/\registers_reg[29][8] } {/theRegisters/\registers_reg[29][9] } {/theRegisters/\registers_reg[2][0] } {/theRegisters/\registers_reg[2][10] } {/theRegisters/\registers_reg[2][11] } {/theRegisters/\registers_reg[2][12] } {/theRegisters/\registers_reg[2][13] } {/theRegisters/\registers_reg[2][14] } {/theRegisters/\registers_reg[2][15] } {/theRegisters/\registers_reg[2][16] } {/theRegisters/\registers_reg[2][17] } {/theRegisters/\registers_reg[2][18] } {/theRegisters/\registers_reg[2][19] } {/theRegisters/\registers_reg[2][1] } {/theRegisters/\registers_reg[2][20] } {/theRegisters/\registers_reg[2][21] } {/theRegisters/\registers_reg[2][22] } {/theRegisters/\registers_reg[2][23] } {/theRegisters/\registers_reg[2][24] } {/theRegisters/\registers_reg[2][25] } {/theRegisters/\registers_reg[2][26] } {/theRegisters/\registers_reg[2][27] } {/theRegisters/\registers_reg[2][28] } {/theRegisters/\registers_reg[2][29] } {/theRegisters/\registers_reg[2][2] } {/theRegisters/\registers_reg[2][30] } {/theRegisters/\registers_reg[2][31] } {/theRegisters/\registers_reg[2][3] } {/theRegisters/\registers_reg[2][4] } {/theRegisters/\registers_reg[2][5] } {/theRegisters/\registers_reg[2][6] } {/theRegisters/\registers_reg[2][7] } {/theRegisters/\registers_reg[2][8] } {/theRegisters/\registers_reg[2][9] } {/theRegisters/\registers_reg[30][0] } {/theRegisters/\registers_reg[30][10] } {/theRegisters/\registers_reg[30][11] } {/theRegisters/\registers_reg[30][12] } {/theRegisters/\registers_reg[30][13] } {/theRegisters/\registers_reg[30][14] } {/theRegisters/\registers_reg[30][15] } {/theRegisters/\registers_reg[30][16] } {/theRegisters/\registers_reg[30][17] } {/theRegisters/\registers_reg[30][18] } {/theRegisters/\registers_reg[30][19] } {/theRegisters/\registers_reg[30][1] } {/theRegisters/\registers_reg[30][20] } {/theRegisters/\registers_reg[30][21] } {/theRegisters/\registers_reg[30][22] } {/theRegisters/\registers_reg[30][23] } {/theRegisters/\registers_reg[30][24] } {/theRegisters/\registers_reg[30][25] } {/theRegisters/\registers_reg[30][26] } {/theRegisters/\registers_reg[30][27] } {/theRegisters/\registers_reg[30][28] } {/theRegisters/\registers_reg[30][29] } {/theRegisters/\registers_reg[30][2] } {/theRegisters/\registers_reg[30][30] } {/theRegisters/\registers_reg[30][31] } {/theRegisters/\registers_reg[30][3] } {/theRegisters/\registers_reg[30][4] } {/theRegisters/\registers_reg[30][5] } {/theRegisters/\registers_reg[30][6] } {/theRegisters/\registers_reg[30][7] } {/theRegisters/\registers_reg[30][8] } {/theRegisters/\registers_reg[30][9] } } -si_connections {SI_3 } -so_connections {SO_3 } -chain_count 1 +create_scan_chain_family scanChain_4 -include_elements {{/theRegisters/\registers_reg[31][0] } {/theRegisters/\registers_reg[31][10] } {/theRegisters/\registers_reg[31][11] } {/theRegisters/\registers_reg[31][12] } {/theRegisters/\registers_reg[31][13] } {/theRegisters/\registers_reg[31][14] } {/theRegisters/\registers_reg[31][15] } {/theRegisters/\registers_reg[31][16] } {/theRegisters/\registers_reg[31][17] } {/theRegisters/\registers_reg[31][18] } {/theRegisters/\registers_reg[31][19] } {/theRegisters/\registers_reg[31][1] } {/theRegisters/\registers_reg[31][20] } {/theRegisters/\registers_reg[31][21] } {/theRegisters/\registers_reg[31][22] } {/theRegisters/\registers_reg[31][23] } {/theRegisters/\registers_reg[31][24] } {/theRegisters/\registers_reg[31][25] } {/theRegisters/\registers_reg[31][26] } {/theRegisters/\registers_reg[31][27] } {/theRegisters/\registers_reg[31][28] } {/theRegisters/\registers_reg[31][29] } {/theRegisters/\registers_reg[31][2] } {/theRegisters/\registers_reg[31][30] } {/theRegisters/\registers_reg[31][31] } {/theRegisters/\registers_reg[31][3] } {/theRegisters/\registers_reg[31][4] } {/theRegisters/\registers_reg[31][5] } {/theRegisters/\registers_reg[31][6] } {/theRegisters/\registers_reg[31][7] } {/theRegisters/\registers_reg[31][8] } {/theRegisters/\registers_reg[31][9] } {/theRegisters/\registers_reg[3][0] } {/theRegisters/\registers_reg[3][10] } {/theRegisters/\registers_reg[3][11] } {/theRegisters/\registers_reg[3][12] } {/theRegisters/\registers_reg[3][13] } {/theRegisters/\registers_reg[3][14] } {/theRegisters/\registers_reg[3][15] } {/theRegisters/\registers_reg[3][16] } {/theRegisters/\registers_reg[3][17] } {/theRegisters/\registers_reg[3][18] } {/theRegisters/\registers_reg[3][19] } {/theRegisters/\registers_reg[3][1] } {/theRegisters/\registers_reg[3][20] } {/theRegisters/\registers_reg[3][21] } {/theRegisters/\registers_reg[3][22] } {/theRegisters/\registers_reg[3][23] } {/theRegisters/\registers_reg[3][24] } {/theRegisters/\registers_reg[3][25] } {/theRegisters/\registers_reg[3][26] } {/theRegisters/\registers_reg[3][27] } {/theRegisters/\registers_reg[3][28] } {/theRegisters/\registers_reg[3][29] } {/theRegisters/\registers_reg[3][2] } {/theRegisters/\registers_reg[3][30] } {/theRegisters/\registers_reg[3][31] } {/theRegisters/\registers_reg[3][3] } {/theRegisters/\registers_reg[3][4] } {/theRegisters/\registers_reg[3][5] } {/theRegisters/\registers_reg[3][6] } {/theRegisters/\registers_reg[3][7] } {/theRegisters/\registers_reg[3][8] } {/theRegisters/\registers_reg[3][9] } {/theRegisters/\registers_reg[4][0] } {/theRegisters/\registers_reg[4][10] } {/theRegisters/\registers_reg[4][11] } {/theRegisters/\registers_reg[4][12] } {/theRegisters/\registers_reg[4][13] } {/theRegisters/\registers_reg[4][14] } {/theRegisters/\registers_reg[4][15] } {/theRegisters/\registers_reg[4][16] } {/theRegisters/\registers_reg[4][17] } {/theRegisters/\registers_reg[4][18] } {/theRegisters/\registers_reg[4][19] } {/theRegisters/\registers_reg[4][1] } {/theRegisters/\registers_reg[4][20] } {/theRegisters/\registers_reg[4][21] } {/theRegisters/\registers_reg[4][22] } {/theRegisters/\registers_reg[4][23] } {/theRegisters/\registers_reg[4][24] } {/theRegisters/\registers_reg[4][25] } {/theRegisters/\registers_reg[4][26] } {/theRegisters/\registers_reg[4][27] } {/theRegisters/\registers_reg[4][28] } {/theRegisters/\registers_reg[4][29] } {/theRegisters/\registers_reg[4][2] } {/theRegisters/\registers_reg[4][30] } {/theRegisters/\registers_reg[4][31] } {/theRegisters/\registers_reg[4][3] } {/theRegisters/\registers_reg[4][4] } {/theRegisters/\registers_reg[4][5] } {/theRegisters/\registers_reg[4][6] } {/theRegisters/\registers_reg[4][7] } {/theRegisters/\registers_reg[4][8] } {/theRegisters/\registers_reg[4][9] } {/theRegisters/\registers_reg[5][0] } {/theRegisters/\registers_reg[5][10] } {/theRegisters/\registers_reg[5][11] } {/theRegisters/\registers_reg[5][12] } {/theRegisters/\registers_reg[5][13] } {/theRegisters/\registers_reg[5][14] } {/theRegisters/\registers_reg[5][15] } {/theRegisters/\registers_reg[5][16] } {/theRegisters/\registers_reg[5][17] } {/theRegisters/\registers_reg[5][18] } {/theRegisters/\registers_reg[5][19] } {/theRegisters/\registers_reg[5][1] } {/theRegisters/\registers_reg[5][20] } {/theRegisters/\registers_reg[5][21] } {/theRegisters/\registers_reg[5][22] } {/theRegisters/\registers_reg[5][23] } {/theRegisters/\registers_reg[5][24] } {/theRegisters/\registers_reg[5][25] } {/theRegisters/\registers_reg[5][26] } {/theRegisters/\registers_reg[5][27] } {/theRegisters/\registers_reg[5][28] } {/theRegisters/\registers_reg[5][29] } {/theRegisters/\registers_reg[5][2] } {/theRegisters/\registers_reg[5][30] } {/theRegisters/\registers_reg[5][31] } {/theRegisters/\registers_reg[5][3] } {/theRegisters/\registers_reg[5][4] } {/theRegisters/\registers_reg[5][5] } {/theRegisters/\registers_reg[5][6] } {/theRegisters/\registers_reg[5][7] } {/theRegisters/\registers_reg[5][8] } {/theRegisters/\registers_reg[5][9] } {/theRegisters/\registers_reg[6][0] } {/theRegisters/\registers_reg[6][10] } {/theRegisters/\registers_reg[6][11] } {/theRegisters/\registers_reg[6][12] } {/theRegisters/\registers_reg[6][13] } {/theRegisters/\registers_reg[6][14] } {/theRegisters/\registers_reg[6][15] } {/theRegisters/\registers_reg[6][16] } {/theRegisters/\registers_reg[6][17] } {/theRegisters/\registers_reg[6][18] } {/theRegisters/\registers_reg[6][19] } {/theRegisters/\registers_reg[6][1] } {/theRegisters/\registers_reg[6][20] } {/theRegisters/\registers_reg[6][21] } {/theRegisters/\registers_reg[6][22] } {/theRegisters/\registers_reg[6][23] } {/theRegisters/\registers_reg[6][24] } {/theRegisters/\registers_reg[6][25] } {/theRegisters/\registers_reg[6][26] } {/theRegisters/\registers_reg[6][27] } {/theRegisters/\registers_reg[6][28] } {/theRegisters/\registers_reg[6][29] } {/theRegisters/\registers_reg[6][2] } {/theRegisters/\registers_reg[6][30] } {/theRegisters/\registers_reg[6][31] } {/theRegisters/\registers_reg[6][3] } {/theRegisters/\registers_reg[6][4] } {/theRegisters/\registers_reg[6][5] } {/theRegisters/\registers_reg[6][6] } {/theRegisters/\registers_reg[6][7] } {/theRegisters/\registers_reg[6][8] } {/theRegisters/\registers_reg[6][9] } {/theRegisters/\registers_reg[7][0] } {/theRegisters/\registers_reg[7][10] } {/theRegisters/\registers_reg[7][11] } {/theRegisters/\registers_reg[7][12] } {/theRegisters/\registers_reg[7][13] } {/theRegisters/\registers_reg[7][14] } {/theRegisters/\registers_reg[7][15] } {/theRegisters/\registers_reg[7][16] } {/theRegisters/\registers_reg[7][17] } {/theRegisters/\registers_reg[7][18] } {/theRegisters/\registers_reg[7][19] } {/theRegisters/\registers_reg[7][1] } {/theRegisters/\registers_reg[7][20] } {/theRegisters/\registers_reg[7][21] } {/theRegisters/\registers_reg[7][22] } {/theRegisters/\registers_reg[7][23] } {/theRegisters/\registers_reg[7][24] } {/theRegisters/\registers_reg[7][25] } {/theRegisters/\registers_reg[7][26] } {/theRegisters/\registers_reg[7][27] } {/theRegisters/\registers_reg[7][28] } {/theRegisters/\registers_reg[7][29] } {/theRegisters/\registers_reg[7][2] } {/theRegisters/\registers_reg[7][30] } {/theRegisters/\registers_reg[7][31] } {/theRegisters/\registers_reg[7][3] } {/theRegisters/\registers_reg[7][4] } {/theRegisters/\registers_reg[7][5] } {/theRegisters/\registers_reg[7][6] } {/theRegisters/\registers_reg[7][7] } {/theRegisters/\registers_reg[7][8] } {/theRegisters/\registers_reg[7][9] } {/theRegisters/\registers_reg[8][0] } {/theRegisters/\registers_reg[8][10] } {/theRegisters/\registers_reg[8][11] } {/theRegisters/\registers_reg[8][12] } {/theRegisters/\registers_reg[8][13] } {/theRegisters/\registers_reg[8][14] } {/theRegisters/\registers_reg[8][15] } {/theRegisters/\registers_reg[8][16] } {/theRegisters/\registers_reg[8][17] } {/theRegisters/\registers_reg[8][18] } {/theRegisters/\registers_reg[8][19] } {/theRegisters/\registers_reg[8][1] } {/theRegisters/\registers_reg[8][20] } {/theRegisters/\registers_reg[8][21] } {/theRegisters/\registers_reg[8][22] } {/theRegisters/\registers_reg[8][23] } {/theRegisters/\registers_reg[8][24] } {/theRegisters/\registers_reg[8][25] } {/theRegisters/\registers_reg[8][26] } {/theRegisters/\registers_reg[8][27] } {/theRegisters/\registers_reg[8][28] } {/theRegisters/\registers_reg[8][29] } {/theRegisters/\registers_reg[8][2] } {/theRegisters/\registers_reg[8][30] } {/theRegisters/\registers_reg[8][31] } {/theRegisters/\registers_reg[8][3] } {/theRegisters/\registers_reg[8][4] } {/theRegisters/\registers_reg[8][5] } {/theRegisters/\registers_reg[8][6] } {/theRegisters/\registers_reg[8][7] } {/theRegisters/\registers_reg[8][8] } {/theRegisters/\registers_reg[8][9] } {/theRegisters/\registers_reg[9][0] } {/theRegisters/\registers_reg[9][10] } {/theRegisters/\registers_reg[9][11] } {/theRegisters/\registers_reg[9][12] } {/theRegisters/\registers_reg[9][13] } {/theRegisters/\registers_reg[9][14] } {/theRegisters/\registers_reg[9][15] } {/theRegisters/\registers_reg[9][16] } {/theRegisters/\registers_reg[9][17] } {/theRegisters/\registers_reg[9][18] } {/theRegisters/\registers_reg[9][19] } {/theRegisters/\registers_reg[9][1] } {/theRegisters/\registers_reg[9][20] } {/theRegisters/\registers_reg[9][21] } {/theRegisters/\registers_reg[9][22] } {/theRegisters/\registers_reg[9][23] } {/theRegisters/\registers_reg[9][24] } {/theRegisters/\registers_reg[9][25] } {/theRegisters/\registers_reg[9][26] } {/theRegisters/\registers_reg[9][27] } {/theRegisters/\registers_reg[9][28] } {/theRegisters/\registers_reg[9][29] } {/theRegisters/\registers_reg[9][2] } {/theRegisters/\registers_reg[9][30] } {/theRegisters/\registers_reg[9][31] } {/theRegisters/\registers_reg[9][3] } {/theRegisters/\registers_reg[9][4] } {/theRegisters/\registers_reg[9][5] } {/theRegisters/\registers_reg[9][6] } {/theRegisters/\registers_reg[9][7] } {/theRegisters/\registers_reg[9][8] } {/theRegisters/\registers_reg[9][9] } } -si_connections {SI_4 } -so_connections {SO_4 } -chain_count 1 +source /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.01/Scan_0/scan_enable_cluster.cfg +analyze_scan_chains +insert_test_logic -write_in_tsdb on +report_scan_chains + +write_scan_order /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.01/Scan_0/cpu.scandef -use_escaping_rule Lefdef -replace +write_design -output_file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.01/Scan_0/post_scan.v -replace + diff --git a/oasys.tessent.01/Scan_0/scan.log b/oasys.tessent.01/Scan_0/scan.log new file mode 100644 index 0000000..157ea06 --- /dev/null +++ b/oasys.tessent.01/Scan_0/scan.log @@ -0,0 +1,409 @@ +/applications/SiemensEDA/siemenseda2023/tessent_2023.4-p1/bin/tessent -shell -dofile /tmp/oasys.2567124/.tmpTessentFile -log_file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.01/Scan_0/scan.log -replace +// Tessent Shell 2023.4-p1 Mon Feb 19 16:22:02 GMT 2024 +// Unpublished work. Copyright 2024 Siemens +// +// This material contains trade secrets or otherwise confidential +// information owned by Siemens Industry Software Inc. or its affiliates +// (collectively, "SISW"), or its licensors. Access to and use of this +// information is strictly limited as set forth in the Customer's +// applicable agreements with SISW. +// +// Siemens software executing under x86-64 Linux on Fri May 29 09:09:54 CEST 2026. +// 64 bit version +// Host: efiapps0.ads1.fh-nuernberg.de (12 x 3.5 GHz, 48014 MB RAM, 24575 MB Swap) +// +// command: if {[catch {source /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.01/Scan_0/scan.do} msg]} { +// puts "$msg" +// puts "TESSENT_ER_ORTL" } +// sub-command: set_context dft -scan -no_rtl -design_id Scan_0 +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_low_temp_ccs.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_low_temp_ccs.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_low_temp_ccs.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_low_temp_ccs.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_low_temp_ccs.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_low_temp_ccs.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/PLL.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/PLL.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/PLL.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/IO.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/IO.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/IO.fslib +// sub-command: set_module_matching_options -suffix_pattern_list {[_]+[0-9]+[_]+[0-9]+} -regexp -append +// sub-command: set_module_matching_options -suffix_pattern_list {[_]+[A-Z]+} -regexp -append +// sub-command: set_module_matching_options -suffix_pattern_list {[_]+[0-9]+[_]+[0-9]+[_]+[A-Z]+} -regexp -append +// sub-command: read_verilog /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.01/Scan_0/oasys_netlist.v +// sub-command: set_tsdb_output_directory /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.01/tsdb_outdir +// sub-command: read_sdc /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.01/Scan_0/oasys.sdc +// Command 'read_sdc' requires an elaborated design. Automatically elaborating the design ... +// Note: 640 duplicate cell library models were read. The last model read of the same name was kept. +// To see detailed messages per duplicate model, issue 'set_cell_library_options -report_duplicate_models on' +// before issuing 'read_cell_library'. +// Warning: 1 cell library model contained 2 floating model outputs. +// To see detailed messages per model, issue 'set_cell_library_options -report_floating_nets on' +// before issuing 'read_cell_library'. +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X1' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X2' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X4' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X8' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X1_HVT' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X2_HVT' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X4_HVT' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X8_HVT' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X1_SVT' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X2_SVT' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X4_SVT' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X8_SVT' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X1_LVT' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X2_LVT' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X4_LVT' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X8_LVT' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' +// Note: Top design is 'cpu'. +// Warning: Undefined modules were found. +// Before using "set_system_mode" or "create_flat_model", you must either define +// the missing modules using "read_verilog" and/or "read_cell_library", or use the +// following command to treat them as black boxes: + add_black_boxes -modules { \ + MemGen_16_10 \ + } +// You can also use "add_black_boxes -auto" to black box all undefined modules but +// it is recommended that you do not add this command to your dofile. Doing so may +// unintentionally black-box new undefined modules in future runs. +// Warning: 32 cases: Unused net in DFT library model +// Warning: 110 cases: Undriven net in netlist module +// Warning: 1 case: Floating input on instance in netlist +// Warning: 47 cases: Net in netlist not connected +// Note: Issue set_current_design with the -show_elaboration_warnings option to see more details about previous warnings +// Design elaboration successful. +// Reading SDC file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.01/Scan_0/oasys.sdc ... +// Finished reading SDC file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.01/Scan_0/oasys.sdc. +// Read SDC summary: 1 false path, 0 multi-cycle paths, 0 erroneous paths +// 0 disable timings, 0 case analysis, 0 clock groups +// sub-command: set_current_design cpu -show_elaboration_warnings +// Warning: Undefined modules were found. +// Before using "set_system_mode" or "create_flat_model", you must either define +// the missing modules using "read_verilog" and/or "read_cell_library", or use the +// following command to treat them as black boxes: + add_black_boxes -modules { \ + MemGen_16_10 \ + } +// You can also use "add_black_boxes -auto" to black box all undefined modules but +// it is recommended that you do not add this command to your dofile. Doing so may +// unintentionally black-box new undefined modules in future runs. +// Warning: Net 'SO_1' in module 'cpu' is not driven +// Warning: Net 'SO_2' in module 'cpu' is not driven +// Warning: Net 'SO_3' in module 'cpu' is not driven +// Warning: Net 'SO_4' in module 'cpu' is not driven +// Warning: Net 'DAddr[31]' in module 'cpu' has no pins +// Warning: Net 'DAddr[30]' in module 'cpu' has no pins +// Warning: Net 'DAddr[29]' in module 'cpu' has no pins +// Warning: Net 'DAddr[28]' in module 'cpu' has no pins +// Warning: Net 'DAddr[27]' in module 'cpu' has no pins +// Warning: Net 'DAddr[26]' in module 'cpu' has no pins +// Warning: Net 'DAddr[25]' in module 'cpu' has no pins +// Warning: Net 'DAddr[24]' in module 'cpu' has no pins +// Warning: Net 'DAddr[23]' in module 'cpu' has no pins +// Warning: Net 'DAddr[22]' in module 'cpu' has no pins +// Warning: Net 'DAddr[21]' in module 'cpu' has no pins +// Warning: Net 'DAddr[20]' in module 'cpu' has no pins +// Warning: Net 'DAddr[19]' in module 'cpu' has no pins +// Warning: Net 'DAddr[18]' in module 'cpu' has no pins +// Warning: Net 'DAddr[17]' in module 'cpu' has no pins +// Warning: Net 'DAddr[16]' in module 'cpu' has no pins +// Warning: Net 'DAddr[15]' in module 'cpu' has no pins +// Warning: Net 'DAddr[14]' in module 'cpu' has no pins +// Warning: Net 'DAddr[13]' in module 'cpu' has no pins +// Warning: Net 'NextPC[31]' in module 'cpu' has no pins +// Warning: Net 'NextPC[30]' in module 'cpu' has no pins +// Warning: Net 'NextPC[29]' in module 'cpu' has no pins +// Warning: Net 'NextPC[28]' in module 'cpu' has no pins +// Warning: Net 'NextPC[27]' in module 'cpu' has no pins +// Warning: Net 'NextPC[26]' in module 'cpu' has no pins +// Warning: Net 'NextPC[25]' in module 'cpu' has no pins +// Warning: Net 'NextPC[24]' in module 'cpu' has no pins +// Warning: Net 'NextPC[23]' in module 'cpu' has no pins +// Warning: Net 'NextPC[22]' in module 'cpu' has no pins +// Warning: Net 'NextPC[21]' in module 'cpu' has no pins +// Warning: Net 'NextPC[20]' in module 'cpu' has no pins +// Warning: Net 'NextPC[19]' in module 'cpu' has no pins +// Warning: Net 'NextPC[18]' in module 'cpu' has no pins +// Warning: Net 'NextPC[17]' in module 'cpu' has no pins +// Warning: Net 'NextPC[16]' in module 'cpu' has no pins +// Warning: Net 'NextPC[15]' in module 'cpu' has no pins +// Warning: Net 'NextPC[14]' in module 'cpu' has no pins +// Warning: Net 'NextPC[13]' in module 'cpu' has no pins +// Warning: Net 'NextPC[7]' in module 'cpu' has no pins +// Warning: Net 'NextPC[6]' in module 'cpu' has no pins +// Warning: Net 'NextPC[5]' in module 'cpu' has no pins +// Warning: Net 'NextPC[4]' in module 'cpu' has no pins +// Warning: Net 'NextPC[3]' in module 'cpu' has no pins +// Warning: Net 'NextPC[2]' in module 'cpu' has no pins +// Warning: Net 'NextPC[1]' in module 'cpu' has no pins +// Warning: Net 'NextPC[0]' in module 'cpu' has no pins +// Warning: Net 'uc_0' in module 'cpu' is not driven +// Warning: Net 'uc_1' in module 'cpu' is not driven +// Warning: Net 'uc_2' in module 'cpu' is not driven +// Warning: Net 'uc_3' in module 'cpu' is not driven +// Warning: Net 'uc_4' in module 'cpu' is not driven +// Warning: Net 'uc_5' in module 'cpu' is not driven +// Warning: Net 'uc_6' in module 'cpu' is not driven +// Warning: Net 'uc_7' in module 'cpu' is not driven +// Warning: Net 'uc_8' in module 'cpu' is not driven +// Warning: Net 'uc_9' in module 'cpu' is not driven +// Warning: Net 'uc_10' in module 'cpu' is not driven +// Warning: Net 'uc_11' in module 'cpu' is not driven +// Warning: Net 'uc_12' in module 'cpu' is not driven +// Warning: Net 'uc_13' in module 'cpu' is not driven +// Warning: Net 'uc_14' in module 'cpu' is not driven +// Warning: Net 'uc_15' in module 'cpu' is not driven +// Warning: Net 'uc_16' in module 'cpu' is not driven +// Warning: Net 'uc_17' in module 'cpu' is not driven +// Warning: Net 'uc_18' in module 'cpu' is not driven +// Warning: Net 'uc_19' in module 'cpu' is not driven +// Warning: Net 'uc_20' in module 'cpu' is not driven +// Warning: Net 'uc_21' in module 'cpu' is not driven +// Warning: Net 'uc_22' in module 'cpu' is not driven +// Warning: Net 'uc_23' in module 'cpu' is not driven +// Warning: Net 'uc_24' in module 'cpu' is not driven +// Warning: Net 'uc_25' in module 'cpu' is not driven +// Warning: Net 'uc_26' in module 'cpu' is not driven +// Warning: Net 'uc_27' in module 'cpu' is not driven +// Warning: Net 'uc_28' in module 'cpu' is not driven +// Warning: Net 'uc_29' in module 'cpu' is not driven +// Warning: Net 'uc_30' in module 'cpu' is not driven +// Warning: Net 'uc_31' in module 'cpu' is not driven +// Warning: Net 'uc_32' in module 'cpu' is not driven +// Warning: Net 'uc_33' in module 'cpu' is not driven +// Warning: Net 'uc_34' in module 'cpu' is not driven +// Warning: Net 'uc_35' in module 'cpu' is not driven +// Warning: Net 'uc_36' in module 'cpu' is not driven +// Warning: Net 'uc_37' in module 'cpu' is not driven +// Warning: Net 'uc_38' in module 'cpu' is not driven +// Warning: Net 'uc_39' in module 'cpu' is not driven +// Warning: Floating input 'chip_en' at instance 'RAM' in module 'main_mem' +// Warning: Net 'mem_sel[1]' in module 'MemGen_32_11' has no pins +// Warning: Net 'DAddr[31]' in module 'decoder' is not driven +// Warning: Net 'DAddr[30]' in module 'decoder' is not driven +// Warning: Net 'DAddr[29]' in module 'decoder' is not driven +// Warning: Net 'DAddr[28]' in module 'decoder' is not driven +// Warning: Net 'DAddr[27]' in module 'decoder' is not driven +// Warning: Net 'DAddr[26]' in module 'decoder' is not driven +// Warning: Net 'DAddr[25]' in module 'decoder' is not driven +// Warning: Net 'DAddr[24]' in module 'decoder' is not driven +// Warning: Net 'DAddr[23]' in module 'decoder' is not driven +// Warning: Net 'DAddr[22]' in module 'decoder' is not driven +// Warning: Net 'DAddr[21]' in module 'decoder' is not driven +// Warning: Net 'DAddr[20]' in module 'decoder' is not driven +// Warning: Net 'DAddr[19]' in module 'decoder' is not driven +// Warning: Net 'DAddr[18]' in module 'decoder' is not driven +// Warning: Net 'DAddr[17]' in module 'decoder' is not driven +// Warning: Net 'DAddr[16]' in module 'decoder' is not driven +// Warning: Net 'DAddr[15]' in module 'decoder' is not driven +// Warning: Net 'DAddr[14]' in module 'decoder' is not driven +// Warning: Net 'DAddr[13]' in module 'decoder' is not driven +// Warning: Net 'WData[31]' in module 'decoder' is not driven +// Warning: Net 'WData[30]' in module 'decoder' is not driven +// Warning: Net 'WData[29]' in module 'decoder' is not driven +// Warning: Net 'WData[28]' in module 'decoder' is not driven +// Warning: Net 'WData[27]' in module 'decoder' is not driven +// Warning: Net 'WData[26]' in module 'decoder' is not driven +// Warning: Net 'WData[25]' in module 'decoder' is not driven +// Warning: Net 'WData[24]' in module 'decoder' is not driven +// Warning: Net 'WData[23]' in module 'decoder' is not driven +// Warning: Net 'WData[22]' in module 'decoder' is not driven +// Warning: Net 'WData[21]' in module 'decoder' is not driven +// Warning: Net 'WData[20]' in module 'decoder' is not driven +// Warning: Net 'WData[19]' in module 'decoder' is not driven +// Warning: Net 'WData[18]' in module 'decoder' is not driven +// Warning: Net 'WData[17]' in module 'decoder' is not driven +// Warning: Net 'WData[16]' in module 'decoder' is not driven +// Warning: Net 'WData[15]' in module 'decoder' is not driven +// Warning: Net 'WData[14]' in module 'decoder' is not driven +// Warning: Net 'WData[13]' in module 'decoder' is not driven +// Warning: Net 'WData[12]' in module 'decoder' is not driven +// Warning: Net 'WData[11]' in module 'decoder' is not driven +// Warning: Net 'WData[10]' in module 'decoder' is not driven +// Warning: Net 'WData[9]' in module 'decoder' is not driven +// Warning: Net 'WData[8]' in module 'decoder' is not driven +// Warning: Net 'WData[7]' in module 'decoder' is not driven +// Warning: Net 'WData[6]' in module 'decoder' is not driven +// Warning: Net 'WData[5]' in module 'decoder' is not driven +// Warning: Net 'WData[4]' in module 'decoder' is not driven +// Warning: Net 'WData[3]' in module 'decoder' is not driven +// Warning: Net 'WData[2]' in module 'decoder' is not driven +// Warning: Net 'WData[1]' in module 'decoder' is not driven +// Warning: Net 'WData[0]' in module 'decoder' is not driven +// Warning: Net 'Rs1[4]' in module 'decoder' is not driven +// Warning: Net 'Rs1[3]' in module 'decoder' is not driven +// Warning: Net 'Rs1[2]' in module 'decoder' is not driven +// Warning: Net 'Rs1[1]' in module 'decoder' is not driven +// Warning: Net 'Rs1[0]' in module 'decoder' is not driven +// Warning: Net 'Rs2[4]' in module 'decoder' is not driven +// Warning: Net 'Rs2[3]' in module 'decoder' is not driven +// Warning: Net 'Rs2[2]' in module 'decoder' is not driven +// Warning: Net 'Rs2[1]' in module 'decoder' is not driven +// Warning: Net 'Rs2[0]' in module 'decoder' is not driven +// Warning: Net 'Rd[4]' in module 'decoder' is not driven +// Warning: Net 'Rd[3]' in module 'decoder' is not driven +// Warning: Net 'Rd[2]' in module 'decoder' is not driven +// Warning: Net 'Rd[1]' in module 'decoder' is not driven +// Warning: Net 'Rd[0]' in module 'decoder' is not driven +// sub-command: set_design_level physical_block +// sub-command: set_shift_register_identification off +// sub-command: add_nonscan_instances -instances "{/theMem/\IRData_reg[31] } {/theMem/\IRData_reg[30] } {/theMem/\IRData_reg[29] } {/theMem/\IRData_reg[28] } {/theMem/\IRData_reg[27] } {/theMem/\IRData_reg[26] } {/theMem/\IRData_reg[25] } {/theMem/\IRData_reg[24] } {/theMem/\IRData_reg[23] } {/theMem/\IRData_reg[22] } {/theMem/\IRData_reg[21] } {/theMem/\IRData_reg[20] } {/theMem/\IRData_reg[19] } {/theMem/\IRData_reg[18] } {/theMem/\IRData_reg[17] } {/theMem/\IRData_reg[16] } {/theMem/\IRData_reg[15] } {/theMem/\IRData_reg[14] } {/theMem/\IRData_reg[13] } {/theMem/\IRData_reg[12] } {/theMem/\IRData_reg[11] } {/theMem/\IRData_reg[10] } {/theMem/\IRData_reg[9] } {/theMem/\IRData_reg[8] } {/theMem/\IRData_reg[7] } {/theMem/\IRData_reg[6] } {/theMem/\IRData_reg[5] } {/theMem/\IRData_reg[4] } {/theMem/\IRData_reg[3] } {/theMem/\IRData_reg[2] } {/theMem/\IRData_reg[1] } {/theMem/\IRData_reg[0] } {/theMem/\mem_addr_reg[10] } {/theMem/\mem_addr_reg[9] } {/theMem/\mem_addr_reg[8] } {/theMem/\mem_addr_reg[7] } {/theMem/\mem_addr_reg[6] } {/theMem/\mem_addr_reg[5] } {/theMem/\mem_addr_reg[4] } {/theMem/\mem_addr_reg[3] } {/theMem/\mem_addr_reg[2] } {/theMem/\mem_addr_reg[1] } {/theMem/\mem_addr_reg[0] } {/theMem/\drTmp_reg[31] } {/theMem/\drTmp_reg[30] } {/theMem/\drTmp_reg[29] } {/theMem/\drTmp_reg[28] } {/theMem/\drTmp_reg[27] } {/theMem/\drTmp_reg[26] } {/theMem/\drTmp_reg[25] } {/theMem/\drTmp_reg[24] } {/theMem/\drTmp_reg[23] } {/theMem/\drTmp_reg[22] } {/theMem/\drTmp_reg[21] } {/theMem/\drTmp_reg[20] } {/theMem/\drTmp_reg[19] } {/theMem/\drTmp_reg[18] } {/theMem/\drTmp_reg[17] } {/theMem/\drTmp_reg[16] } {/theMem/\drTmp_reg[15] } {/theMem/\drTmp_reg[14] } {/theMem/\drTmp_reg[13] } {/theMem/\drTmp_reg[12] } {/theMem/\drTmp_reg[11] } {/theMem/\drTmp_reg[10] } {/theMem/\drTmp_reg[9] } {/theMem/\drTmp_reg[8] } {/theMem/\drTmp_reg[7] } {/theMem/\drTmp_reg[6] } {/theMem/\drTmp_reg[5] } {/theMem/\drTmp_reg[4] } {/theMem/\drTmp_reg[3] } {/theMem/\drTmp_reg[2] } {/theMem/\drTmp_reg[1] } {/theMem/\drTmp_reg[0] } {/theMem/\mem_wdata_reg[31] } {/theMem/\mem_wdata_reg[30] } {/theMem/\mem_wdata_reg[29] } {/theMem/\mem_wdata_reg[28] } {/theMem/\mem_wdata_reg[27] } {/theMem/\mem_wdata_reg[26] } {/theMem/\mem_wdata_reg[25] } {/theMem/\mem_wdata_reg[24] } {/theMem/\mem_wdata_reg[23] } {/theMem/\mem_wdata_reg[22] } {/theMem/\mem_wdata_reg[21] } {/theMem/\mem_wdata_reg[20] } {/theMem/\mem_wdata_reg[19] } {/theMem/\mem_wdata_reg[18] } {/theMem/\mem_wdata_reg[17] } {/theMem/\mem_wdata_reg[16] } {/theMem/\mem_wdata_reg[15] } {/theMem/\mem_wdata_reg[14] } {/theMem/\mem_wdata_reg[13] } {/theMem/\mem_wdata_reg[12] } {/theMem/\mem_wdata_reg[11] } {/theMem/\mem_wdata_reg[10] } {/theMem/\mem_wdata_reg[9] } {/theMem/\mem_wdata_reg[8] } {/theMem/\mem_wdata_reg[7] } {/theMem/\mem_wdata_reg[6] } {/theMem/\mem_wdata_reg[5] } {/theMem/\mem_wdata_reg[4] } {/theMem/\mem_wdata_reg[3] } {/theMem/\mem_wdata_reg[2] } {/theMem/\mem_wdata_reg[1] } {/theMem/\mem_wdata_reg[0] } " +// sub-command: add_clocks 0 " clk_25mhz " +// sub-command: set_scan_enable scan_en -active high +// sub-command: add_input_constraints btn[0] -C1 +// sub-command: set_scan_enable scan_en -active high -cluster_name scanChain_1 +// sub-command: set_scan_enable scan_en -active high -cluster_name scanChain_2 +// sub-command: set_scan_enable scan_en -active high -cluster_name scanChain_3 +// sub-command: set_scan_enable scan_en -active high -cluster_name scanChain_4 +// sub-command: add_black_boxes -modules " MemGen_16_10 " +// sub-command: set_scan_insertion_options -single_clock_edge_chains on -si_port_format oas_ts_si[%d] -so_port_format oas_ts_so[%d] +// sub-command: set_system_mode analysis +// Warning: Rule FN1 violation occurs 157 times +// Warning: Rule FP13 violation occurs 1 times +// Flattening process completed, cell instances=4379, gates=18234, PIs=13, POs=12, CPU time=0.09 sec. +// --------------------------------------------------------------------------- +// Begin circuit learning analyses. +// -------------------------------- +// Learning completed, CPU time=0.01 sec. +// --------------------------------------------------------------------------- +// Begin scan chain identification process, memory elements = 1194, +// sequential library cells = 1194. +// --------------------------------------------------------------------------- +// Warning: Model 'DLH_X1_LVT' has no muxscan scan equivalent and is treated as nonscan model +// ------------------------------------------------------------------------------ +// 170 sequential library cells are treated as non-scan. +// ------------------------------------------------------------------------------ +// 63 sequential library cells missing mux-scan equivalent. +// 107 sequential library cells defined non-scan. +// --------------------------------------------------------------------------- +// Begin scannability rules checking for 1024 sequential library cells. +// --------------------------------------------------------------------------- +// 1024 sequential library cells identified as scannable. +// --------------------------------------------------------------------------- +// Begin transparent latch checking for 63 latches. +// --------------------------------------------------------------------------- +// Warning: 32 latches not transparent due to uncontrollable. (D6) +// Number transparent latches = 31. +// --------------------------------------------------------------------------- +// Begin scan clock rules checking. +// --------------------------------------------------------------------------- +// 1 scan clock/set/reset lines have been identified. +// All scan clocks successfully passed off-state check. +// 1131 sequential cells passed clock stability checking. +// There were 43 clock rule C3 fails (clock may capture data affected by its captured data). +// Note: Trailing edge triggered device can capture data affected by leading edge. +// --------------------------------------------------------------------------- +// 170 non-scan memory elements are identified. +// --------------------------------------------------------------------------- +// 32 non-scan memory elements are identified as TIE-X. (D5) +// 107 non-scan memory elements are identified as INIT-X. (D5) +// 31 non-scan memory elements are identified as TLA. (D5) +// --------------------------------------------------------------------------- +// Number of targeted sequential library cells = 1024 +// Warning: The tool may require a shift-capture clock during insertion, +// but no 'shift_capture_clock' DFT signal was identified +// and no TCLK source was specified using the command 'set_scan_signals -tclk'. +// Note: The system clock 'clk_25mhz' will be used as the shift-capture clock, if needed. +// sub-command: report_drc_rules +C3: #fails=43 handling=note (clock may capture data affected by its captured data) +D5: #fails=170 handling=warning (non-scan memory element) +D6: #fails=32 handling=warning (non-transparent non-scan latches) +// sub-command: create_scan_chain_family scanChain_1 -include_elements "{/\thePC_CurrentPC_reg[0] } {/\thePC_CurrentPC_reg[10] } {/\thePC_CurrentPC_reg[11] } {/\thePC_CurrentPC_reg[12] } {/\thePC_CurrentPC_reg[13] } {/\thePC_CurrentPC_reg[14] } {/\thePC_CurrentPC_reg[15] } {/\thePC_CurrentPC_reg[16] } {/\thePC_CurrentPC_reg[17] } {/\thePC_CurrentPC_reg[18] } {/\thePC_CurrentPC_reg[19] } {/\thePC_CurrentPC_reg[1] } {/\thePC_CurrentPC_reg[20] } {/\thePC_CurrentPC_reg[21] } {/\thePC_CurrentPC_reg[22] } {/\thePC_CurrentPC_reg[23] } {/\thePC_CurrentPC_reg[24] } {/\thePC_CurrentPC_reg[25] } {/\thePC_CurrentPC_reg[26] } {/\thePC_CurrentPC_reg[27] } {/\thePC_CurrentPC_reg[28] } {/\thePC_CurrentPC_reg[29] } {/\thePC_CurrentPC_reg[2] } {/\thePC_CurrentPC_reg[30] } {/\thePC_CurrentPC_reg[31] } {/\thePC_CurrentPC_reg[3] } {/\thePC_CurrentPC_reg[4] } {/\thePC_CurrentPC_reg[5] } {/\thePC_CurrentPC_reg[6] } {/\thePC_CurrentPC_reg[7] } {/\thePC_CurrentPC_reg[8] } {/\thePC_CurrentPC_reg[9] } {/theRegisters/\registers_reg[10][0] } {/theRegisters/\registers_reg[10][10] } {/theRegisters/\registers_reg[10][11] } {/theRegisters/\registers_reg[10][12] } {/theRegisters/\registers_reg[10][13] } {/theRegisters/\registers_reg[10][14] } {/theRegisters/\registers_reg[10][15] } {/theRegisters/\registers_reg[10][16] } {/theRegisters/\registers_reg[10][17] } {/theRegisters/\registers_reg[10][18] } {/theRegisters/\registers_reg[10][19] } {/theRegisters/\registers_reg[10][1] } {/theRegisters/\registers_reg[10][20] } {/theRegisters/\registers_reg[10][21] } {/theRegisters/\registers_reg[10][22] } {/theRegisters/\registers_reg[10][23] } {/theRegisters/\registers_reg[10][24] } {/theRegisters/\registers_reg[10][25] } {/theRegisters/\registers_reg[10][26] } {/theRegisters/\registers_reg[10][27] } {/theRegisters/\registers_reg[10][28] } {/theRegisters/\registers_reg[10][29] } {/theRegisters/\registers_reg[10][2] } {/theRegisters/\registers_reg[10][30] } {/theRegisters/\registers_reg[10][31] } {/theRegisters/\registers_reg[10][3] } {/theRegisters/\registers_reg[10][4] } {/theRegisters/\registers_reg[10][5] } {/theRegisters/\registers_reg[10][6] } {/theRegisters/\registers_reg[10][7] } {/theRegisters/\registers_reg[10][8] } {/theRegisters/\registers_reg[10][9] } {/theRegisters/\registers_reg[11][0] } {/theRegisters/\registers_reg[11][10] } {/theRegisters/\registers_reg[11][11] } {/theRegisters/\registers_reg[11][12] } {/theRegisters/\registers_reg[11][13] } {/theRegisters/\registers_reg[11][14] } {/theRegisters/\registers_reg[11][15] } {/theRegisters/\registers_reg[11][16] } {/theRegisters/\registers_reg[11][17] } {/theRegisters/\registers_reg[11][18] } {/theRegisters/\registers_reg[11][19] } {/theRegisters/\registers_reg[11][1] } {/theRegisters/\registers_reg[11][20] } {/theRegisters/\registers_reg[11][21] } {/theRegisters/\registers_reg[11][22] } {/theRegisters/\registers_reg[11][23] } {/theRegisters/\registers_reg[11][24] } {/theRegisters/\registers_reg[11][25] } {/theRegisters/\registers_reg[11][26] } {/theRegisters/\registers_reg[11][27] } {/theRegisters/\registers_reg[11][28] } {/theRegisters/\registers_reg[11][29] } {/theRegisters/\registers_reg[11][2] } {/theRegisters/\registers_reg[11][30] } {/theRegisters/\registers_reg[11][31] } {/theRegisters/\registers_reg[11][3] } {/theRegisters/\registers_reg[11][4] } {/theRegisters/\registers_reg[11][5] } {/theRegisters/\registers_reg[11][6] } {/theRegisters/\registers_reg[11][7] } {/theRegisters/\registers_reg[11][8] } {/theRegisters/\registers_reg[11][9] } {/theRegisters/\registers_reg[12][0] } {/theRegisters/\registers_reg[12][10] } {/theRegisters/\registers_reg[12][11] } {/theRegisters/\registers_reg[12][12] } {/theRegisters/\registers_reg[12][13] } {/theRegisters/\registers_reg[12][14] } {/theRegisters/\registers_reg[12][15] } {/theRegisters/\registers_reg[12][16] } {/theRegisters/\registers_reg[12][17] } {/theRegisters/\registers_reg[12][18] } {/theRegisters/\registers_reg[12][19] } {/theRegisters/\registers_reg[12][1] } {/theRegisters/\registers_reg[12][20] } {/theRegisters/\registers_reg[12][21] } {/theRegisters/\registers_reg[12][22] } {/theRegisters/\registers_reg[12][23] } {/theRegisters/\registers_reg[12][24] } {/theRegisters/\registers_reg[12][25] } {/theRegisters/\registers_reg[12][26] } {/theRegisters/\registers_reg[12][27] } {/theRegisters/\registers_reg[12][28] } {/theRegisters/\registers_reg[12][29] } {/theRegisters/\registers_reg[12][2] } {/theRegisters/\registers_reg[12][30] } {/theRegisters/\registers_reg[12][31] } {/theRegisters/\registers_reg[12][3] } {/theRegisters/\registers_reg[12][4] } {/theRegisters/\registers_reg[12][5] } {/theRegisters/\registers_reg[12][6] } {/theRegisters/\registers_reg[12][7] } {/theRegisters/\registers_reg[12][8] } {/theRegisters/\registers_reg[12][9] } {/theRegisters/\registers_reg[13][0] } {/theRegisters/\registers_reg[13][10] } {/theRegisters/\registers_reg[13][11] } {/theRegisters/\registers_reg[13][12] } {/theRegisters/\registers_reg[13][13] } {/theRegisters/\registers_reg[13][14] } {/theRegisters/\registers_reg[13][15] } {/theRegisters/\registers_reg[13][16] } {/theRegisters/\registers_reg[13][17] } {/theRegisters/\registers_reg[13][18] } {/theRegisters/\registers_reg[13][19] } {/theRegisters/\registers_reg[13][1] } {/theRegisters/\registers_reg[13][20] } {/theRegisters/\registers_reg[13][21] } {/theRegisters/\registers_reg[13][22] } {/theRegisters/\registers_reg[13][23] } {/theRegisters/\registers_reg[13][24] } {/theRegisters/\registers_reg[13][25] } {/theRegisters/\registers_reg[13][26] } {/theRegisters/\registers_reg[13][27] } {/theRegisters/\registers_reg[13][28] } {/theRegisters/\registers_reg[13][29] } {/theRegisters/\registers_reg[13][2] } {/theRegisters/\registers_reg[13][30] } {/theRegisters/\registers_reg[13][31] } {/theRegisters/\registers_reg[13][3] } {/theRegisters/\registers_reg[13][4] } {/theRegisters/\registers_reg[13][5] } {/theRegisters/\registers_reg[13][6] } {/theRegisters/\registers_reg[13][7] } {/theRegisters/\registers_reg[13][8] } {/theRegisters/\registers_reg[13][9] } {/theRegisters/\registers_reg[14][0] } {/theRegisters/\registers_reg[14][10] } {/theRegisters/\registers_reg[14][11] } {/theRegisters/\registers_reg[14][12] } {/theRegisters/\registers_reg[14][13] } {/theRegisters/\registers_reg[14][14] } {/theRegisters/\registers_reg[14][15] } {/theRegisters/\registers_reg[14][16] } {/theRegisters/\registers_reg[14][17] } {/theRegisters/\registers_reg[14][18] } {/theRegisters/\registers_reg[14][19] } {/theRegisters/\registers_reg[14][1] } {/theRegisters/\registers_reg[14][20] } {/theRegisters/\registers_reg[14][21] } {/theRegisters/\registers_reg[14][22] } {/theRegisters/\registers_reg[14][23] } {/theRegisters/\registers_reg[14][24] } {/theRegisters/\registers_reg[14][25] } {/theRegisters/\registers_reg[14][26] } {/theRegisters/\registers_reg[14][27] } {/theRegisters/\registers_reg[14][28] } {/theRegisters/\registers_reg[14][29] } {/theRegisters/\registers_reg[14][2] } {/theRegisters/\registers_reg[14][30] } {/theRegisters/\registers_reg[14][31] } {/theRegisters/\registers_reg[14][3] } {/theRegisters/\registers_reg[14][4] } {/theRegisters/\registers_reg[14][5] } {/theRegisters/\registers_reg[14][6] } {/theRegisters/\registers_reg[14][7] } {/theRegisters/\registers_reg[14][8] } {/theRegisters/\registers_reg[14][9] } {/theRegisters/\registers_reg[15][0] } {/theRegisters/\registers_reg[15][10] } {/theRegisters/\registers_reg[15][11] } {/theRegisters/\registers_reg[15][12] } {/theRegisters/\registers_reg[15][13] } {/theRegisters/\registers_reg[15][14] } {/theRegisters/\registers_reg[15][15] } {/theRegisters/\registers_reg[15][16] } {/theRegisters/\registers_reg[15][17] } {/theRegisters/\registers_reg[15][18] } {/theRegisters/\registers_reg[15][19] } {/theRegisters/\registers_reg[15][1] } {/theRegisters/\registers_reg[15][20] } {/theRegisters/\registers_reg[15][21] } {/theRegisters/\registers_reg[15][22] } {/theRegisters/\registers_reg[15][23] } {/theRegisters/\registers_reg[15][24] } {/theRegisters/\registers_reg[15][25] } {/theRegisters/\registers_reg[15][26] } {/theRegisters/\registers_reg[15][27] } {/theRegisters/\registers_reg[15][28] } {/theRegisters/\registers_reg[15][29] } {/theRegisters/\registers_reg[15][2] } {/theRegisters/\registers_reg[15][30] } {/theRegisters/\registers_reg[15][31] } {/theRegisters/\registers_reg[15][3] } {/theRegisters/\registers_reg[15][4] } {/theRegisters/\registers_reg[15][5] } {/theRegisters/\registers_reg[15][6] } {/theRegisters/\registers_reg[15][7] } {/theRegisters/\registers_reg[15][8] } {/theRegisters/\registers_reg[15][9] } {/theRegisters/\registers_reg[16][0] } {/theRegisters/\registers_reg[16][10] } {/theRegisters/\registers_reg[16][11] } {/theRegisters/\registers_reg[16][12] } {/theRegisters/\registers_reg[16][13] } {/theRegisters/\registers_reg[16][14] } {/theRegisters/\registers_reg[16][15] } {/theRegisters/\registers_reg[16][16] } {/theRegisters/\registers_reg[16][17] } {/theRegisters/\registers_reg[16][18] } {/theRegisters/\registers_reg[16][19] } {/theRegisters/\registers_reg[16][1] } {/theRegisters/\registers_reg[16][20] } {/theRegisters/\registers_reg[16][21] } {/theRegisters/\registers_reg[16][22] } {/theRegisters/\registers_reg[16][23] } {/theRegisters/\registers_reg[16][24] } {/theRegisters/\registers_reg[16][25] } {/theRegisters/\registers_reg[16][26] } {/theRegisters/\registers_reg[16][27] } {/theRegisters/\registers_reg[16][28] } {/theRegisters/\registers_reg[16][29] } {/theRegisters/\registers_reg[16][2] } {/theRegisters/\registers_reg[16][30] } {/theRegisters/\registers_reg[16][31] } {/theRegisters/\registers_reg[16][3] } {/theRegisters/\registers_reg[16][4] } {/theRegisters/\registers_reg[16][5] } {/theRegisters/\registers_reg[16][6] } {/theRegisters/\registers_reg[16][7] } {/theRegisters/\registers_reg[16][8] } {/theRegisters/\registers_reg[16][9] } " -si_connections "SI_1 " -so_connections "SO_1 " -chain_count 1 +// sub-command: create_scan_chain_family scanChain_2 -include_elements "{/theRegisters/\registers_reg[17][0] } {/theRegisters/\registers_reg[17][10] } {/theRegisters/\registers_reg[17][11] } {/theRegisters/\registers_reg[17][12] } {/theRegisters/\registers_reg[17][13] } {/theRegisters/\registers_reg[17][14] } {/theRegisters/\registers_reg[17][15] } {/theRegisters/\registers_reg[17][16] } {/theRegisters/\registers_reg[17][17] } {/theRegisters/\registers_reg[17][18] } {/theRegisters/\registers_reg[17][19] } {/theRegisters/\registers_reg[17][1] } {/theRegisters/\registers_reg[17][20] } {/theRegisters/\registers_reg[17][21] } {/theRegisters/\registers_reg[17][22] } {/theRegisters/\registers_reg[17][23] } {/theRegisters/\registers_reg[17][24] } {/theRegisters/\registers_reg[17][25] } {/theRegisters/\registers_reg[17][26] } {/theRegisters/\registers_reg[17][27] } {/theRegisters/\registers_reg[17][28] } {/theRegisters/\registers_reg[17][29] } {/theRegisters/\registers_reg[17][2] } {/theRegisters/\registers_reg[17][30] } {/theRegisters/\registers_reg[17][31] } {/theRegisters/\registers_reg[17][3] } {/theRegisters/\registers_reg[17][4] } {/theRegisters/\registers_reg[17][5] } {/theRegisters/\registers_reg[17][6] } {/theRegisters/\registers_reg[17][7] } {/theRegisters/\registers_reg[17][8] } {/theRegisters/\registers_reg[17][9] } {/theRegisters/\registers_reg[18][0] } {/theRegisters/\registers_reg[18][10] } {/theRegisters/\registers_reg[18][11] } {/theRegisters/\registers_reg[18][12] } {/theRegisters/\registers_reg[18][13] } {/theRegisters/\registers_reg[18][14] } {/theRegisters/\registers_reg[18][15] } {/theRegisters/\registers_reg[18][16] } {/theRegisters/\registers_reg[18][17] } {/theRegisters/\registers_reg[18][18] } {/theRegisters/\registers_reg[18][19] } {/theRegisters/\registers_reg[18][1] } {/theRegisters/\registers_reg[18][20] } {/theRegisters/\registers_reg[18][21] } {/theRegisters/\registers_reg[18][22] } {/theRegisters/\registers_reg[18][23] } {/theRegisters/\registers_reg[18][24] } {/theRegisters/\registers_reg[18][25] } {/theRegisters/\registers_reg[18][26] } {/theRegisters/\registers_reg[18][27] } {/theRegisters/\registers_reg[18][28] } {/theRegisters/\registers_reg[18][29] } {/theRegisters/\registers_reg[18][2] } {/theRegisters/\registers_reg[18][30] } {/theRegisters/\registers_reg[18][31] } {/theRegisters/\registers_reg[18][3] } {/theRegisters/\registers_reg[18][4] } {/theRegisters/\registers_reg[18][5] } {/theRegisters/\registers_reg[18][6] } {/theRegisters/\registers_reg[18][7] } {/theRegisters/\registers_reg[18][8] } {/theRegisters/\registers_reg[18][9] } {/theRegisters/\registers_reg[19][0] } {/theRegisters/\registers_reg[19][10] } {/theRegisters/\registers_reg[19][11] } {/theRegisters/\registers_reg[19][12] } {/theRegisters/\registers_reg[19][13] } {/theRegisters/\registers_reg[19][14] } {/theRegisters/\registers_reg[19][15] } {/theRegisters/\registers_reg[19][16] } {/theRegisters/\registers_reg[19][17] } {/theRegisters/\registers_reg[19][18] } {/theRegisters/\registers_reg[19][19] } {/theRegisters/\registers_reg[19][1] } {/theRegisters/\registers_reg[19][20] } {/theRegisters/\registers_reg[19][21] } {/theRegisters/\registers_reg[19][22] } {/theRegisters/\registers_reg[19][23] } {/theRegisters/\registers_reg[19][24] } {/theRegisters/\registers_reg[19][25] } {/theRegisters/\registers_reg[19][26] } {/theRegisters/\registers_reg[19][27] } {/theRegisters/\registers_reg[19][28] } {/theRegisters/\registers_reg[19][29] } {/theRegisters/\registers_reg[19][2] } {/theRegisters/\registers_reg[19][30] } {/theRegisters/\registers_reg[19][31] } {/theRegisters/\registers_reg[19][3] } {/theRegisters/\registers_reg[19][4] } {/theRegisters/\registers_reg[19][5] } {/theRegisters/\registers_reg[19][6] } {/theRegisters/\registers_reg[19][7] } {/theRegisters/\registers_reg[19][8] } {/theRegisters/\registers_reg[19][9] } {/theRegisters/\registers_reg[1][0] } {/theRegisters/\registers_reg[1][10] } {/theRegisters/\registers_reg[1][11] } {/theRegisters/\registers_reg[1][12] } {/theRegisters/\registers_reg[1][13] } {/theRegisters/\registers_reg[1][14] } {/theRegisters/\registers_reg[1][15] } {/theRegisters/\registers_reg[1][16] } {/theRegisters/\registers_reg[1][17] } {/theRegisters/\registers_reg[1][18] } {/theRegisters/\registers_reg[1][19] } {/theRegisters/\registers_reg[1][1] } {/theRegisters/\registers_reg[1][20] } {/theRegisters/\registers_reg[1][21] } {/theRegisters/\registers_reg[1][22] } {/theRegisters/\registers_reg[1][23] } {/theRegisters/\registers_reg[1][24] } {/theRegisters/\registers_reg[1][25] } {/theRegisters/\registers_reg[1][26] } {/theRegisters/\registers_reg[1][27] } {/theRegisters/\registers_reg[1][28] } {/theRegisters/\registers_reg[1][29] } {/theRegisters/\registers_reg[1][2] } {/theRegisters/\registers_reg[1][30] } {/theRegisters/\registers_reg[1][31] } {/theRegisters/\registers_reg[1][3] } {/theRegisters/\registers_reg[1][4] } {/theRegisters/\registers_reg[1][5] } {/theRegisters/\registers_reg[1][6] } {/theRegisters/\registers_reg[1][7] } {/theRegisters/\registers_reg[1][8] } {/theRegisters/\registers_reg[1][9] } {/theRegisters/\registers_reg[20][0] } {/theRegisters/\registers_reg[20][10] } {/theRegisters/\registers_reg[20][11] } {/theRegisters/\registers_reg[20][12] } {/theRegisters/\registers_reg[20][13] } {/theRegisters/\registers_reg[20][14] } {/theRegisters/\registers_reg[20][15] } {/theRegisters/\registers_reg[20][16] } {/theRegisters/\registers_reg[20][17] } {/theRegisters/\registers_reg[20][18] } {/theRegisters/\registers_reg[20][19] } {/theRegisters/\registers_reg[20][1] } {/theRegisters/\registers_reg[20][20] } {/theRegisters/\registers_reg[20][21] } {/theRegisters/\registers_reg[20][22] } {/theRegisters/\registers_reg[20][23] } {/theRegisters/\registers_reg[20][24] } {/theRegisters/\registers_reg[20][25] } {/theRegisters/\registers_reg[20][26] } {/theRegisters/\registers_reg[20][27] } {/theRegisters/\registers_reg[20][28] } {/theRegisters/\registers_reg[20][29] } {/theRegisters/\registers_reg[20][2] } {/theRegisters/\registers_reg[20][30] } {/theRegisters/\registers_reg[20][31] } {/theRegisters/\registers_reg[20][3] } {/theRegisters/\registers_reg[20][4] } {/theRegisters/\registers_reg[20][5] } {/theRegisters/\registers_reg[20][6] } {/theRegisters/\registers_reg[20][7] } {/theRegisters/\registers_reg[20][8] } {/theRegisters/\registers_reg[20][9] } {/theRegisters/\registers_reg[21][0] } {/theRegisters/\registers_reg[21][10] } {/theRegisters/\registers_reg[21][11] } {/theRegisters/\registers_reg[21][12] } {/theRegisters/\registers_reg[21][13] } {/theRegisters/\registers_reg[21][14] } {/theRegisters/\registers_reg[21][15] } {/theRegisters/\registers_reg[21][16] } {/theRegisters/\registers_reg[21][17] } {/theRegisters/\registers_reg[21][18] } {/theRegisters/\registers_reg[21][19] } {/theRegisters/\registers_reg[21][1] } {/theRegisters/\registers_reg[21][20] } {/theRegisters/\registers_reg[21][21] } {/theRegisters/\registers_reg[21][22] } {/theRegisters/\registers_reg[21][23] } {/theRegisters/\registers_reg[21][24] } {/theRegisters/\registers_reg[21][25] } {/theRegisters/\registers_reg[21][26] } {/theRegisters/\registers_reg[21][27] } {/theRegisters/\registers_reg[21][28] } {/theRegisters/\registers_reg[21][29] } {/theRegisters/\registers_reg[21][2] } {/theRegisters/\registers_reg[21][30] } {/theRegisters/\registers_reg[21][31] } {/theRegisters/\registers_reg[21][3] } {/theRegisters/\registers_reg[21][4] } {/theRegisters/\registers_reg[21][5] } {/theRegisters/\registers_reg[21][6] } {/theRegisters/\registers_reg[21][7] } {/theRegisters/\registers_reg[21][8] } {/theRegisters/\registers_reg[21][9] } {/theRegisters/\registers_reg[22][0] } {/theRegisters/\registers_reg[22][10] } {/theRegisters/\registers_reg[22][11] } {/theRegisters/\registers_reg[22][12] } {/theRegisters/\registers_reg[22][13] } {/theRegisters/\registers_reg[22][14] } {/theRegisters/\registers_reg[22][15] } {/theRegisters/\registers_reg[22][16] } {/theRegisters/\registers_reg[22][17] } {/theRegisters/\registers_reg[22][18] } {/theRegisters/\registers_reg[22][19] } {/theRegisters/\registers_reg[22][1] } {/theRegisters/\registers_reg[22][20] } {/theRegisters/\registers_reg[22][21] } {/theRegisters/\registers_reg[22][22] } {/theRegisters/\registers_reg[22][23] } {/theRegisters/\registers_reg[22][24] } {/theRegisters/\registers_reg[22][25] } {/theRegisters/\registers_reg[22][26] } {/theRegisters/\registers_reg[22][27] } {/theRegisters/\registers_reg[22][28] } {/theRegisters/\registers_reg[22][29] } {/theRegisters/\registers_reg[22][2] } {/theRegisters/\registers_reg[22][30] } {/theRegisters/\registers_reg[22][31] } {/theRegisters/\registers_reg[22][3] } {/theRegisters/\registers_reg[22][4] } {/theRegisters/\registers_reg[22][5] } {/theRegisters/\registers_reg[22][6] } {/theRegisters/\registers_reg[22][7] } {/theRegisters/\registers_reg[22][8] } {/theRegisters/\registers_reg[22][9] } {/theRegisters/\registers_reg[23][0] } {/theRegisters/\registers_reg[23][10] } {/theRegisters/\registers_reg[23][11] } {/theRegisters/\registers_reg[23][12] } {/theRegisters/\registers_reg[23][13] } {/theRegisters/\registers_reg[23][14] } {/theRegisters/\registers_reg[23][15] } {/theRegisters/\registers_reg[23][16] } {/theRegisters/\registers_reg[23][17] } {/theRegisters/\registers_reg[23][18] } {/theRegisters/\registers_reg[23][19] } {/theRegisters/\registers_reg[23][1] } {/theRegisters/\registers_reg[23][20] } {/theRegisters/\registers_reg[23][21] } {/theRegisters/\registers_reg[23][22] } {/theRegisters/\registers_reg[23][23] } {/theRegisters/\registers_reg[23][24] } {/theRegisters/\registers_reg[23][25] } {/theRegisters/\registers_reg[23][26] } {/theRegisters/\registers_reg[23][27] } {/theRegisters/\registers_reg[23][28] } {/theRegisters/\registers_reg[23][29] } {/theRegisters/\registers_reg[23][2] } {/theRegisters/\registers_reg[23][30] } {/theRegisters/\registers_reg[23][31] } {/theRegisters/\registers_reg[23][3] } {/theRegisters/\registers_reg[23][4] } {/theRegisters/\registers_reg[23][5] } {/theRegisters/\registers_reg[23][6] } {/theRegisters/\registers_reg[23][7] } {/theRegisters/\registers_reg[23][8] } {/theRegisters/\registers_reg[23][9] } " -si_connections "SI_2 " -so_connections "SO_2 " -chain_count 1 +// sub-command: create_scan_chain_family scanChain_3 -include_elements "{/theRegisters/\registers_reg[24][0] } {/theRegisters/\registers_reg[24][10] } {/theRegisters/\registers_reg[24][11] } {/theRegisters/\registers_reg[24][12] } {/theRegisters/\registers_reg[24][13] } {/theRegisters/\registers_reg[24][14] } {/theRegisters/\registers_reg[24][15] } {/theRegisters/\registers_reg[24][16] } {/theRegisters/\registers_reg[24][17] } {/theRegisters/\registers_reg[24][18] } {/theRegisters/\registers_reg[24][19] } {/theRegisters/\registers_reg[24][1] } {/theRegisters/\registers_reg[24][20] } {/theRegisters/\registers_reg[24][21] } {/theRegisters/\registers_reg[24][22] } {/theRegisters/\registers_reg[24][23] } {/theRegisters/\registers_reg[24][24] } {/theRegisters/\registers_reg[24][25] } {/theRegisters/\registers_reg[24][26] } {/theRegisters/\registers_reg[24][27] } {/theRegisters/\registers_reg[24][28] } {/theRegisters/\registers_reg[24][29] } {/theRegisters/\registers_reg[24][2] } {/theRegisters/\registers_reg[24][30] } {/theRegisters/\registers_reg[24][31] } {/theRegisters/\registers_reg[24][3] } {/theRegisters/\registers_reg[24][4] } {/theRegisters/\registers_reg[24][5] } {/theRegisters/\registers_reg[24][6] } {/theRegisters/\registers_reg[24][7] } {/theRegisters/\registers_reg[24][8] } {/theRegisters/\registers_reg[24][9] } {/theRegisters/\registers_reg[25][0] } {/theRegisters/\registers_reg[25][10] } {/theRegisters/\registers_reg[25][11] } {/theRegisters/\registers_reg[25][12] } {/theRegisters/\registers_reg[25][13] } {/theRegisters/\registers_reg[25][14] } {/theRegisters/\registers_reg[25][15] } {/theRegisters/\registers_reg[25][16] } {/theRegisters/\registers_reg[25][17] } {/theRegisters/\registers_reg[25][18] } {/theRegisters/\registers_reg[25][19] } {/theRegisters/\registers_reg[25][1] } {/theRegisters/\registers_reg[25][20] } {/theRegisters/\registers_reg[25][21] } {/theRegisters/\registers_reg[25][22] } {/theRegisters/\registers_reg[25][23] } {/theRegisters/\registers_reg[25][24] } {/theRegisters/\registers_reg[25][25] } {/theRegisters/\registers_reg[25][26] } {/theRegisters/\registers_reg[25][27] } {/theRegisters/\registers_reg[25][28] } {/theRegisters/\registers_reg[25][29] } {/theRegisters/\registers_reg[25][2] } {/theRegisters/\registers_reg[25][30] } {/theRegisters/\registers_reg[25][31] } {/theRegisters/\registers_reg[25][3] } {/theRegisters/\registers_reg[25][4] } {/theRegisters/\registers_reg[25][5] } {/theRegisters/\registers_reg[25][6] } {/theRegisters/\registers_reg[25][7] } {/theRegisters/\registers_reg[25][8] } {/theRegisters/\registers_reg[25][9] } {/theRegisters/\registers_reg[26][0] } {/theRegisters/\registers_reg[26][10] } {/theRegisters/\registers_reg[26][11] } {/theRegisters/\registers_reg[26][12] } {/theRegisters/\registers_reg[26][13] } {/theRegisters/\registers_reg[26][14] } {/theRegisters/\registers_reg[26][15] } {/theRegisters/\registers_reg[26][16] } {/theRegisters/\registers_reg[26][17] } {/theRegisters/\registers_reg[26][18] } {/theRegisters/\registers_reg[26][19] } {/theRegisters/\registers_reg[26][1] } {/theRegisters/\registers_reg[26][20] } {/theRegisters/\registers_reg[26][21] } {/theRegisters/\registers_reg[26][22] } {/theRegisters/\registers_reg[26][23] } {/theRegisters/\registers_reg[26][24] } {/theRegisters/\registers_reg[26][25] } {/theRegisters/\registers_reg[26][26] } {/theRegisters/\registers_reg[26][27] } {/theRegisters/\registers_reg[26][28] } {/theRegisters/\registers_reg[26][29] } {/theRegisters/\registers_reg[26][2] } {/theRegisters/\registers_reg[26][30] } {/theRegisters/\registers_reg[26][31] } {/theRegisters/\registers_reg[26][3] } {/theRegisters/\registers_reg[26][4] } {/theRegisters/\registers_reg[26][5] } {/theRegisters/\registers_reg[26][6] } {/theRegisters/\registers_reg[26][7] } {/theRegisters/\registers_reg[26][8] } {/theRegisters/\registers_reg[26][9] } {/theRegisters/\registers_reg[27][0] } {/theRegisters/\registers_reg[27][10] } {/theRegisters/\registers_reg[27][11] } {/theRegisters/\registers_reg[27][12] } {/theRegisters/\registers_reg[27][13] } {/theRegisters/\registers_reg[27][14] } {/theRegisters/\registers_reg[27][15] } {/theRegisters/\registers_reg[27][16] } {/theRegisters/\registers_reg[27][17] } {/theRegisters/\registers_reg[27][18] } {/theRegisters/\registers_reg[27][19] } {/theRegisters/\registers_reg[27][1] } {/theRegisters/\registers_reg[27][20] } {/theRegisters/\registers_reg[27][21] } {/theRegisters/\registers_reg[27][22] } {/theRegisters/\registers_reg[27][23] } {/theRegisters/\registers_reg[27][24] } {/theRegisters/\registers_reg[27][25] } {/theRegisters/\registers_reg[27][26] } {/theRegisters/\registers_reg[27][27] } {/theRegisters/\registers_reg[27][28] } {/theRegisters/\registers_reg[27][29] } {/theRegisters/\registers_reg[27][2] } {/theRegisters/\registers_reg[27][30] } {/theRegisters/\registers_reg[27][31] } {/theRegisters/\registers_reg[27][3] } {/theRegisters/\registers_reg[27][4] } {/theRegisters/\registers_reg[27][5] } {/theRegisters/\registers_reg[27][6] } {/theRegisters/\registers_reg[27][7] } {/theRegisters/\registers_reg[27][8] } {/theRegisters/\registers_reg[27][9] } {/theRegisters/\registers_reg[28][0] } {/theRegisters/\registers_reg[28][10] } {/theRegisters/\registers_reg[28][11] } {/theRegisters/\registers_reg[28][12] } {/theRegisters/\registers_reg[28][13] } {/theRegisters/\registers_reg[28][14] } {/theRegisters/\registers_reg[28][15] } {/theRegisters/\registers_reg[28][16] } {/theRegisters/\registers_reg[28][17] } {/theRegisters/\registers_reg[28][18] } {/theRegisters/\registers_reg[28][19] } {/theRegisters/\registers_reg[28][1] } {/theRegisters/\registers_reg[28][20] } {/theRegisters/\registers_reg[28][21] } {/theRegisters/\registers_reg[28][22] } {/theRegisters/\registers_reg[28][23] } {/theRegisters/\registers_reg[28][24] } {/theRegisters/\registers_reg[28][25] } {/theRegisters/\registers_reg[28][26] } {/theRegisters/\registers_reg[28][27] } {/theRegisters/\registers_reg[28][28] } {/theRegisters/\registers_reg[28][29] } {/theRegisters/\registers_reg[28][2] } {/theRegisters/\registers_reg[28][30] } {/theRegisters/\registers_reg[28][31] } {/theRegisters/\registers_reg[28][3] } {/theRegisters/\registers_reg[28][4] } {/theRegisters/\registers_reg[28][5] } {/theRegisters/\registers_reg[28][6] } {/theRegisters/\registers_reg[28][7] } {/theRegisters/\registers_reg[28][8] } {/theRegisters/\registers_reg[28][9] } {/theRegisters/\registers_reg[29][0] } {/theRegisters/\registers_reg[29][10] } {/theRegisters/\registers_reg[29][11] } {/theRegisters/\registers_reg[29][12] } {/theRegisters/\registers_reg[29][13] } {/theRegisters/\registers_reg[29][14] } {/theRegisters/\registers_reg[29][15] } {/theRegisters/\registers_reg[29][16] } {/theRegisters/\registers_reg[29][17] } {/theRegisters/\registers_reg[29][18] } {/theRegisters/\registers_reg[29][19] } {/theRegisters/\registers_reg[29][1] } {/theRegisters/\registers_reg[29][20] } {/theRegisters/\registers_reg[29][21] } {/theRegisters/\registers_reg[29][22] } {/theRegisters/\registers_reg[29][23] } {/theRegisters/\registers_reg[29][24] } {/theRegisters/\registers_reg[29][25] } {/theRegisters/\registers_reg[29][26] } {/theRegisters/\registers_reg[29][27] } {/theRegisters/\registers_reg[29][28] } {/theRegisters/\registers_reg[29][29] } {/theRegisters/\registers_reg[29][2] } {/theRegisters/\registers_reg[29][30] } {/theRegisters/\registers_reg[29][31] } {/theRegisters/\registers_reg[29][3] } {/theRegisters/\registers_reg[29][4] } {/theRegisters/\registers_reg[29][5] } {/theRegisters/\registers_reg[29][6] } {/theRegisters/\registers_reg[29][7] } {/theRegisters/\registers_reg[29][8] } {/theRegisters/\registers_reg[29][9] } {/theRegisters/\registers_reg[2][0] } {/theRegisters/\registers_reg[2][10] } {/theRegisters/\registers_reg[2][11] } {/theRegisters/\registers_reg[2][12] } {/theRegisters/\registers_reg[2][13] } {/theRegisters/\registers_reg[2][14] } {/theRegisters/\registers_reg[2][15] } {/theRegisters/\registers_reg[2][16] } {/theRegisters/\registers_reg[2][17] } {/theRegisters/\registers_reg[2][18] } {/theRegisters/\registers_reg[2][19] } {/theRegisters/\registers_reg[2][1] } {/theRegisters/\registers_reg[2][20] } {/theRegisters/\registers_reg[2][21] } {/theRegisters/\registers_reg[2][22] } {/theRegisters/\registers_reg[2][23] } {/theRegisters/\registers_reg[2][24] } {/theRegisters/\registers_reg[2][25] } {/theRegisters/\registers_reg[2][26] } {/theRegisters/\registers_reg[2][27] } {/theRegisters/\registers_reg[2][28] } {/theRegisters/\registers_reg[2][29] } {/theRegisters/\registers_reg[2][2] } {/theRegisters/\registers_reg[2][30] } {/theRegisters/\registers_reg[2][31] } {/theRegisters/\registers_reg[2][3] } {/theRegisters/\registers_reg[2][4] } {/theRegisters/\registers_reg[2][5] } {/theRegisters/\registers_reg[2][6] } {/theRegisters/\registers_reg[2][7] } {/theRegisters/\registers_reg[2][8] } {/theRegisters/\registers_reg[2][9] } {/theRegisters/\registers_reg[30][0] } {/theRegisters/\registers_reg[30][10] } {/theRegisters/\registers_reg[30][11] } {/theRegisters/\registers_reg[30][12] } {/theRegisters/\registers_reg[30][13] } {/theRegisters/\registers_reg[30][14] } {/theRegisters/\registers_reg[30][15] } {/theRegisters/\registers_reg[30][16] } {/theRegisters/\registers_reg[30][17] } {/theRegisters/\registers_reg[30][18] } {/theRegisters/\registers_reg[30][19] } {/theRegisters/\registers_reg[30][1] } {/theRegisters/\registers_reg[30][20] } {/theRegisters/\registers_reg[30][21] } {/theRegisters/\registers_reg[30][22] } {/theRegisters/\registers_reg[30][23] } {/theRegisters/\registers_reg[30][24] } {/theRegisters/\registers_reg[30][25] } {/theRegisters/\registers_reg[30][26] } {/theRegisters/\registers_reg[30][27] } {/theRegisters/\registers_reg[30][28] } {/theRegisters/\registers_reg[30][29] } {/theRegisters/\registers_reg[30][2] } {/theRegisters/\registers_reg[30][30] } {/theRegisters/\registers_reg[30][31] } {/theRegisters/\registers_reg[30][3] } {/theRegisters/\registers_reg[30][4] } {/theRegisters/\registers_reg[30][5] } {/theRegisters/\registers_reg[30][6] } {/theRegisters/\registers_reg[30][7] } {/theRegisters/\registers_reg[30][8] } {/theRegisters/\registers_reg[30][9] } " -si_connections "SI_3 " -so_connections "SO_3 " -chain_count 1 +// sub-command: create_scan_chain_family scanChain_4 -include_elements "{/theRegisters/\registers_reg[31][0] } {/theRegisters/\registers_reg[31][10] } {/theRegisters/\registers_reg[31][11] } {/theRegisters/\registers_reg[31][12] } {/theRegisters/\registers_reg[31][13] } {/theRegisters/\registers_reg[31][14] } {/theRegisters/\registers_reg[31][15] } {/theRegisters/\registers_reg[31][16] } {/theRegisters/\registers_reg[31][17] } {/theRegisters/\registers_reg[31][18] } {/theRegisters/\registers_reg[31][19] } {/theRegisters/\registers_reg[31][1] } {/theRegisters/\registers_reg[31][20] } {/theRegisters/\registers_reg[31][21] } {/theRegisters/\registers_reg[31][22] } {/theRegisters/\registers_reg[31][23] } {/theRegisters/\registers_reg[31][24] } {/theRegisters/\registers_reg[31][25] } {/theRegisters/\registers_reg[31][26] } {/theRegisters/\registers_reg[31][27] } {/theRegisters/\registers_reg[31][28] } {/theRegisters/\registers_reg[31][29] } {/theRegisters/\registers_reg[31][2] } {/theRegisters/\registers_reg[31][30] } {/theRegisters/\registers_reg[31][31] } {/theRegisters/\registers_reg[31][3] } {/theRegisters/\registers_reg[31][4] } {/theRegisters/\registers_reg[31][5] } {/theRegisters/\registers_reg[31][6] } {/theRegisters/\registers_reg[31][7] } {/theRegisters/\registers_reg[31][8] } {/theRegisters/\registers_reg[31][9] } {/theRegisters/\registers_reg[3][0] } {/theRegisters/\registers_reg[3][10] } {/theRegisters/\registers_reg[3][11] } {/theRegisters/\registers_reg[3][12] } {/theRegisters/\registers_reg[3][13] } {/theRegisters/\registers_reg[3][14] } {/theRegisters/\registers_reg[3][15] } {/theRegisters/\registers_reg[3][16] } {/theRegisters/\registers_reg[3][17] } {/theRegisters/\registers_reg[3][18] } {/theRegisters/\registers_reg[3][19] } {/theRegisters/\registers_reg[3][1] } {/theRegisters/\registers_reg[3][20] } {/theRegisters/\registers_reg[3][21] } {/theRegisters/\registers_reg[3][22] } {/theRegisters/\registers_reg[3][23] } {/theRegisters/\registers_reg[3][24] } {/theRegisters/\registers_reg[3][25] } {/theRegisters/\registers_reg[3][26] } {/theRegisters/\registers_reg[3][27] } {/theRegisters/\registers_reg[3][28] } {/theRegisters/\registers_reg[3][29] } {/theRegisters/\registers_reg[3][2] } {/theRegisters/\registers_reg[3][30] } {/theRegisters/\registers_reg[3][31] } {/theRegisters/\registers_reg[3][3] } {/theRegisters/\registers_reg[3][4] } {/theRegisters/\registers_reg[3][5] } {/theRegisters/\registers_reg[3][6] } {/theRegisters/\registers_reg[3][7] } {/theRegisters/\registers_reg[3][8] } {/theRegisters/\registers_reg[3][9] } {/theRegisters/\registers_reg[4][0] } {/theRegisters/\registers_reg[4][10] } {/theRegisters/\registers_reg[4][11] } {/theRegisters/\registers_reg[4][12] } {/theRegisters/\registers_reg[4][13] } {/theRegisters/\registers_reg[4][14] } {/theRegisters/\registers_reg[4][15] } {/theRegisters/\registers_reg[4][16] } {/theRegisters/\registers_reg[4][17] } {/theRegisters/\registers_reg[4][18] } {/theRegisters/\registers_reg[4][19] } {/theRegisters/\registers_reg[4][1] } {/theRegisters/\registers_reg[4][20] } {/theRegisters/\registers_reg[4][21] } {/theRegisters/\registers_reg[4][22] } {/theRegisters/\registers_reg[4][23] } {/theRegisters/\registers_reg[4][24] } {/theRegisters/\registers_reg[4][25] } {/theRegisters/\registers_reg[4][26] } {/theRegisters/\registers_reg[4][27] } {/theRegisters/\registers_reg[4][28] } {/theRegisters/\registers_reg[4][29] } {/theRegisters/\registers_reg[4][2] } {/theRegisters/\registers_reg[4][30] } {/theRegisters/\registers_reg[4][31] } {/theRegisters/\registers_reg[4][3] } {/theRegisters/\registers_reg[4][4] } {/theRegisters/\registers_reg[4][5] } {/theRegisters/\registers_reg[4][6] } {/theRegisters/\registers_reg[4][7] } {/theRegisters/\registers_reg[4][8] } {/theRegisters/\registers_reg[4][9] } {/theRegisters/\registers_reg[5][0] } {/theRegisters/\registers_reg[5][10] } {/theRegisters/\registers_reg[5][11] } {/theRegisters/\registers_reg[5][12] } {/theRegisters/\registers_reg[5][13] } {/theRegisters/\registers_reg[5][14] } {/theRegisters/\registers_reg[5][15] } {/theRegisters/\registers_reg[5][16] } {/theRegisters/\registers_reg[5][17] } {/theRegisters/\registers_reg[5][18] } {/theRegisters/\registers_reg[5][19] } {/theRegisters/\registers_reg[5][1] } {/theRegisters/\registers_reg[5][20] } {/theRegisters/\registers_reg[5][21] } {/theRegisters/\registers_reg[5][22] } {/theRegisters/\registers_reg[5][23] } {/theRegisters/\registers_reg[5][24] } {/theRegisters/\registers_reg[5][25] } {/theRegisters/\registers_reg[5][26] } {/theRegisters/\registers_reg[5][27] } {/theRegisters/\registers_reg[5][28] } {/theRegisters/\registers_reg[5][29] } {/theRegisters/\registers_reg[5][2] } {/theRegisters/\registers_reg[5][30] } {/theRegisters/\registers_reg[5][31] } {/theRegisters/\registers_reg[5][3] } {/theRegisters/\registers_reg[5][4] } {/theRegisters/\registers_reg[5][5] } {/theRegisters/\registers_reg[5][6] } {/theRegisters/\registers_reg[5][7] } {/theRegisters/\registers_reg[5][8] } {/theRegisters/\registers_reg[5][9] } {/theRegisters/\registers_reg[6][0] } {/theRegisters/\registers_reg[6][10] } {/theRegisters/\registers_reg[6][11] } {/theRegisters/\registers_reg[6][12] } {/theRegisters/\registers_reg[6][13] } {/theRegisters/\registers_reg[6][14] } {/theRegisters/\registers_reg[6][15] } {/theRegisters/\registers_reg[6][16] } {/theRegisters/\registers_reg[6][17] } {/theRegisters/\registers_reg[6][18] } {/theRegisters/\registers_reg[6][19] } {/theRegisters/\registers_reg[6][1] } {/theRegisters/\registers_reg[6][20] } {/theRegisters/\registers_reg[6][21] } {/theRegisters/\registers_reg[6][22] } {/theRegisters/\registers_reg[6][23] } {/theRegisters/\registers_reg[6][24] } {/theRegisters/\registers_reg[6][25] } {/theRegisters/\registers_reg[6][26] } {/theRegisters/\registers_reg[6][27] } {/theRegisters/\registers_reg[6][28] } {/theRegisters/\registers_reg[6][29] } {/theRegisters/\registers_reg[6][2] } {/theRegisters/\registers_reg[6][30] } {/theRegisters/\registers_reg[6][31] } {/theRegisters/\registers_reg[6][3] } {/theRegisters/\registers_reg[6][4] } {/theRegisters/\registers_reg[6][5] } {/theRegisters/\registers_reg[6][6] } {/theRegisters/\registers_reg[6][7] } {/theRegisters/\registers_reg[6][8] } {/theRegisters/\registers_reg[6][9] } {/theRegisters/\registers_reg[7][0] } {/theRegisters/\registers_reg[7][10] } {/theRegisters/\registers_reg[7][11] } {/theRegisters/\registers_reg[7][12] } {/theRegisters/\registers_reg[7][13] } {/theRegisters/\registers_reg[7][14] } {/theRegisters/\registers_reg[7][15] } {/theRegisters/\registers_reg[7][16] } {/theRegisters/\registers_reg[7][17] } {/theRegisters/\registers_reg[7][18] } {/theRegisters/\registers_reg[7][19] } {/theRegisters/\registers_reg[7][1] } {/theRegisters/\registers_reg[7][20] } {/theRegisters/\registers_reg[7][21] } {/theRegisters/\registers_reg[7][22] } {/theRegisters/\registers_reg[7][23] } {/theRegisters/\registers_reg[7][24] } {/theRegisters/\registers_reg[7][25] } {/theRegisters/\registers_reg[7][26] } {/theRegisters/\registers_reg[7][27] } {/theRegisters/\registers_reg[7][28] } {/theRegisters/\registers_reg[7][29] } {/theRegisters/\registers_reg[7][2] } {/theRegisters/\registers_reg[7][30] } {/theRegisters/\registers_reg[7][31] } {/theRegisters/\registers_reg[7][3] } {/theRegisters/\registers_reg[7][4] } {/theRegisters/\registers_reg[7][5] } {/theRegisters/\registers_reg[7][6] } {/theRegisters/\registers_reg[7][7] } {/theRegisters/\registers_reg[7][8] } {/theRegisters/\registers_reg[7][9] } {/theRegisters/\registers_reg[8][0] } {/theRegisters/\registers_reg[8][10] } {/theRegisters/\registers_reg[8][11] } {/theRegisters/\registers_reg[8][12] } {/theRegisters/\registers_reg[8][13] } {/theRegisters/\registers_reg[8][14] } {/theRegisters/\registers_reg[8][15] } {/theRegisters/\registers_reg[8][16] } {/theRegisters/\registers_reg[8][17] } {/theRegisters/\registers_reg[8][18] } {/theRegisters/\registers_reg[8][19] } {/theRegisters/\registers_reg[8][1] } {/theRegisters/\registers_reg[8][20] } {/theRegisters/\registers_reg[8][21] } {/theRegisters/\registers_reg[8][22] } {/theRegisters/\registers_reg[8][23] } {/theRegisters/\registers_reg[8][24] } {/theRegisters/\registers_reg[8][25] } {/theRegisters/\registers_reg[8][26] } {/theRegisters/\registers_reg[8][27] } {/theRegisters/\registers_reg[8][28] } {/theRegisters/\registers_reg[8][29] } {/theRegisters/\registers_reg[8][2] } {/theRegisters/\registers_reg[8][30] } {/theRegisters/\registers_reg[8][31] } {/theRegisters/\registers_reg[8][3] } {/theRegisters/\registers_reg[8][4] } {/theRegisters/\registers_reg[8][5] } {/theRegisters/\registers_reg[8][6] } {/theRegisters/\registers_reg[8][7] } {/theRegisters/\registers_reg[8][8] } {/theRegisters/\registers_reg[8][9] } {/theRegisters/\registers_reg[9][0] } {/theRegisters/\registers_reg[9][10] } {/theRegisters/\registers_reg[9][11] } {/theRegisters/\registers_reg[9][12] } {/theRegisters/\registers_reg[9][13] } {/theRegisters/\registers_reg[9][14] } {/theRegisters/\registers_reg[9][15] } {/theRegisters/\registers_reg[9][16] } {/theRegisters/\registers_reg[9][17] } {/theRegisters/\registers_reg[9][18] } {/theRegisters/\registers_reg[9][19] } {/theRegisters/\registers_reg[9][1] } {/theRegisters/\registers_reg[9][20] } {/theRegisters/\registers_reg[9][21] } {/theRegisters/\registers_reg[9][22] } {/theRegisters/\registers_reg[9][23] } {/theRegisters/\registers_reg[9][24] } {/theRegisters/\registers_reg[9][25] } {/theRegisters/\registers_reg[9][26] } {/theRegisters/\registers_reg[9][27] } {/theRegisters/\registers_reg[9][28] } {/theRegisters/\registers_reg[9][29] } {/theRegisters/\registers_reg[9][2] } {/theRegisters/\registers_reg[9][30] } {/theRegisters/\registers_reg[9][31] } {/theRegisters/\registers_reg[9][3] } {/theRegisters/\registers_reg[9][4] } {/theRegisters/\registers_reg[9][5] } {/theRegisters/\registers_reg[9][6] } {/theRegisters/\registers_reg[9][7] } {/theRegisters/\registers_reg[9][8] } {/theRegisters/\registers_reg[9][9] } " -si_connections "SI_4 " -so_connections "SO_4 " -chain_count 1 +// sub-command: analyze_scan_chains +// Chain allocation of 'unwrapped' mode completed: +// 4 distributed chains of size 256 +// sub-command: insert_test_logic -write_in_tsdb on +============================= +Test Logic Insertion Summary: +============================= + + Structural Data: + ---------------- + Added top-level port count: 0 + Added instance count: 8 + + Logical Data: + ------------- + Added retiming logic count: 4 + Added scan chain count (unwrapped): 4 + +// Warning: Flattened model deleted. +// +// Writing out netlist and related files in /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.01/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design +// sub-command: report_scan_chains + +=============================== +Scan Chains Created by the Tool +=============================== + + Scan mode 'unwrapped' scan chains: + ---------------------------------- + + Cluster 'scanChain_1' chains: + ----------------------------- + chain = scanChain_1 group = dummy input = /SI_1 output = /SO_1 length = 256 + + Cluster 'scanChain_2' chains: + ----------------------------- + chain = scanChain_2 group = dummy input = /SI_2 output = /SO_2 length = 256 + + Cluster 'scanChain_3' chains: + ----------------------------- + chain = scanChain_3 group = dummy input = /SI_3 output = /SO_3 length = 256 + + Cluster 'scanChain_4' chains: + ----------------------------- + chain = scanChain_4 group = dummy input = /SI_4 output = /SO_4 length = 256 + + +// sub-command: write_scan_order /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.01/Scan_0/cpu.scandef -use_escaping_rule Lefdef -replace +// sub-command: write_design -output_file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.01/Scan_0/post_scan.v -replace +// command: exit diff --git a/oasys.tessent.01/Scan_0/scan_enable_cluster.cfg b/oasys.tessent.01/Scan_0/scan_enable_cluster.cfg new file mode 100644 index 0000000..838af56 --- /dev/null +++ b/oasys.tessent.01/Scan_0/scan_enable_cluster.cfg @@ -0,0 +1,8 @@ +set_attribute_value [get_scan_elements -of_chain_families scanChain_1 ] -name cluster_name -value scanChain_1 + +set_attribute_value [get_scan_elements -of_chain_families scanChain_2 ] -name cluster_name -value scanChain_2 + +set_attribute_value [get_scan_elements -of_chain_families scanChain_3 ] -name cluster_name -value scanChain_3 + +set_attribute_value [get_scan_elements -of_chain_families scanChain_4 ] -name cluster_name -value scanChain_4 + diff --git a/oasys.tessent.01/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.scandef b/oasys.tessent.01/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.scandef new file mode 100644 index 0000000..e1d7df0 --- /dev/null +++ b/oasys.tessent.01/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.scandef @@ -0,0 +1,1071 @@ +# +# DESC: ScanDEF written by Tessent Shell on Fri May 29 09:09:59 CEST 2026 +# + +VERSION 5.7 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN cpu ; +UNITS DISTANCE MICRONS 1000 ; + +SCANCHAINS 4 ; + +- scan_segment_0 + + START tessent_persistent_cell_buf_extsi1225_i Z + + FLOATING + \thePC_CurrentPC_reg[30] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[29] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[28] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[27] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[26] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[25] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[24] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[23] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[22] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[21] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[20] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[19] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[18] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[17] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[16] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[15] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[14] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[13] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[12] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[11] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[10] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[9] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[8] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[7] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[6] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[5] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[4] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[3] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[2] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[31] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[1] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][0] ( IN SI ) ( OUT Q ) + + STOP theRegisters/ts_lockup_latchn_clkc1_intno1054_i D + # Partition constraints - clock domain: clk_25mhz(+); cluster: scanChain_1; chain type: core; scan mode(s): unwrapped + + PARTITION partition_1 MAXBITS 256 ; + + +- scan_segment_1 + + START theRegisters/tessent_persistent_cell_buf_extsi1226_i Z + + FLOATING + theRegisters/\registers_reg[1][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][0] ( IN SI ) ( OUT Q ) + + STOP theRegisters/ts_lockup_latchn_clkc2_intno1050_i D + # Partition constraints - clock domain: clk_25mhz(+); cluster: scanChain_2; chain type: core; scan mode(s): unwrapped + + PARTITION partition_2 MAXBITS 256 ; + + +- scan_segment_2 + + START theRegisters/tessent_persistent_cell_buf_extsi1227_i Z + + FLOATING + theRegisters/\registers_reg[28][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][0] ( IN SI ) ( OUT Q ) + + STOP theRegisters/ts_lockup_latchn_clkc3_intno1053_i D + # Partition constraints - clock domain: clk_25mhz(+); cluster: scanChain_3; chain type: core; scan mode(s): unwrapped + + PARTITION partition_3 MAXBITS 256 ; + + +- scan_segment_3 + + START theRegisters/tessent_persistent_cell_buf_extsi1228_i Z + + FLOATING + theRegisters/\registers_reg[4][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][0] ( IN SI ) ( OUT Q ) + + STOP theRegisters/ts_lockup_latchn_clkc4_intno1051_i D + # Partition constraints - clock domain: clk_25mhz(+); cluster: scanChain_4; chain type: core; scan mode(s): unwrapped + + PARTITION partition_4 MAXBITS 256 ; + + +END SCANCHAINS + +END DESIGN diff --git a/oasys.tessent.01/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.tcd b/oasys.tessent.01/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.tcd new file mode 100644 index 0000000..c56dd1f --- /dev/null +++ b/oasys.tessent.01/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.tcd @@ -0,0 +1,61 @@ +//-------------------------------------------------- +// File created by: Tessent Shell +// Version: 2023.4-p1 +// Created on: Fri May 29 09:09:59 CEST 2026 +//-------------------------------------------------- + + +Core(cpu) { + Scan { + allow_internal_pins : 1; + is_hard_module : 1; + exclude_from_concatenated_netlist : 1; + internal_scan_only : 1; + Mode(unwrapped) { + type : unwrapped; + traceable : 1; + make_active_automatically : 1; + ScanChain { + length : 256; + scan_in_clock : clk_25mhz; + scan_out_clock : ~clk_25mhz; + scan_in_port : SI_1; + scan_out_port : SO_1; + } + ScanChain { + length : 256; + scan_in_clock : clk_25mhz; + scan_out_clock : ~clk_25mhz; + scan_in_port : SI_2; + scan_out_port : SO_2; + } + ScanChain { + length : 256; + scan_in_clock : clk_25mhz; + scan_out_clock : ~clk_25mhz; + scan_in_port : SI_3; + scan_out_port : SO_3; + } + ScanChain { + length : 256; + scan_in_clock : clk_25mhz; + scan_out_clock : ~clk_25mhz; + scan_in_port : SI_4; + scan_out_port : SO_4; + } + ScanEn(scan_en) { + pipeline_count : 0; + active_polarity : all_ones; + } + Clock(clk_25mhz) { + off_state : 1'b0; + } + } + } + DesignInfo { + design_id : Scan_0; + design_level : physical_block; + ChildBlockModules { + } + } +} diff --git a/oasys.tessent.01/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.tsdb_info b/oasys.tessent.01/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.tsdb_info new file mode 100644 index 0000000..2173297 --- /dev/null +++ b/oasys.tessent.01/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.tsdb_info @@ -0,0 +1,23 @@ +//-------------------------------------------------- +// File created by: Tessent Shell +// Version: 2023.4-p1 +// Created on: Fri May 29 09:09:59 CEST 2026 +//-------------------------------------------------- + + +TsdbInfo(cpu,Scan_0) { + tessent_tool_version : 2023.4-p1; + tessent_meta_version : 10; + version : 3; + creation_date : Fri May 29 07:09:59 GMT 2026; + creation_user : charapallivenkatsaja; + creation_step : insert_test_logic; + level : physical_block; + icl_extraction_needed : Off; + library_name : work; + gate_extension : vg; + interface_has_external_dependencies : 0; + OpenedTsdbDirectories { + /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.01/tsdb_outdir; + } +} diff --git a/oasys.tessent.01/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.v_interface b/oasys.tessent.01/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.v_interface new file mode 100644 index 0000000..04248a3 --- /dev/null +++ b/oasys.tessent.01/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.v_interface @@ -0,0 +1,9 @@ +/* Generated by Tessent Shell 2023.4-p1 at Fri May 29 09:09:59 CEST 2026 */ +module cpu(led, btn, clk_25mhz, scan_en, SI_1, SO_1, SI_2, SO_2, SI_3, SO_3, SI_4, + SO_4); + input clk_25mhz, scan_en, SI_1, SI_2, SI_3, SI_4; + output SO_1, SO_2, SO_3, SO_4; + output [7:0] led; + input [6:0] btn; +endmodule + diff --git a/oasys.tessent.01/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.vg b/oasys.tessent.01/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.vg new file mode 100644 index 0000000..fdac9f6 --- /dev/null +++ b/oasys.tessent.01/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.vg @@ -0,0 +1,15792 @@ +/* Generated by Tessent Shell 2023.4-p1 at Fri May 29 09:09:59 CEST 2026 */ +module alu(aluOp, aluNegAr, aluBypass, op1, op2, result, eqFlag); + input [31:0] op1, op2; + input [2:0] aluOp; + input aluNegAr, aluBypass; + output [31:0] result; + output eqFlag; + + wire n_9_0, n_9_1, n_9_2, n_9_3, n_9_4, n_9_5, n_9_6, n_9_7, n_9_8, n_9_9, + n_9_10, n_9_11, n_9_12, n_9_13, n_9_14, n_9_15, n_9_16, n_9_17, n_9_18, + n_9_19, n_9_20, n_9_21, n_9_22, n_9_23, n_9_24, n_9_25, n_9_26, n_9_27, + n_9_28, n_9_29, n_9_30, n_9_31, n_10_0, n_10_1, n_10_2, n_10_3, n_10_4, + n_10_5, n_10_6, n_10_7, n_10_8, n_10_9, n_10_10, n_10_11, n_10_12, + n_10_13, n_10_14, n_10_15, n_10_16, n_10_17, n_10_18, n_10_19, n_10_20, + n_10_21, n_10_22, n_10_23, n_10_24, n_10_25, n_10_26, n_10_27, n_10_28, + n_10_29, n_10_30, n_10_31, n_10_32, n_10_33, n_10_34, n_10_35, n_10_36, + n_10_37, n_10_38, n_10_39, n_10_40, n_10_41, n_10_42, n_10_43, n_10_44, + n_10_45, n_10_46, n_10_47, n_10_48, n_10_49, n_10_50, n_10_51, n_10_52, + n_10_53, n_10_54, n_10_55, n_10_56, n_10_57, n_10_58, n_10_59, n_10_60, + n_10_61, n_10_62, n_10_63, n_10_64, n_10_65, n_10_66, n_10_67, n_10_68, + n_10_69, n_10_70, n_10_71, n_10_72, n_10_73, n_10_74, n_10_75, n_10_76, + n_10_77, n_10_78, n_10_79, n_10_80, n_10_81, n_10_82, n_10_83, n_10_84, + n_10_85, n_10_86, n_10_87, n_10_88, n_10_89, n_10_90, n_10_91, n_10_92, + n_10_93, n_10_94, n_10_95, n_10_96, n_10_97, n_10_98, n_10_99, n_10_100, + n_10_101, n_10_102, n_10_103, n_10_104, n_10_105, n_10_106, n_10_107, + n_10_108, n_10_109, n_10_110, n_10_111, n_10_112, n_10_113, n_10_114, + n_10_115, n_10_116, n_10_117, n_10_118, n_10_119, n_10_120, n_10_121, + n_10_122, n_10_123, n_0_0, n_0_1, n_0_2, n_0_3, n_0_4, n_0_5, n_0_6, + n_0_7, n_0_8, n_0_9, n_0_10, n_0_11, n_0_12, n_0_13, n_0_14, n_0_15, + n_0_16, n_0_17, n_0_18, n_0_19, n_0_20, n_0_21, n_0_22, n_0_23, n_0_24, + n_0_25, n_0_26, n_0_27, n_0_28, n_0_29, n_0_30, n_0_31, n_0_32, n_0_33, + n_0_34, n_0_35, n_0_36, n_0_37, n_0_38, n_0_39, n_0_40, n_0_41, n_0_42, + n_0_43, n_0_44, n_0_45, n_0_46, n_0_47, n_0_48, n_0_49, n_0_50, n_0_51, + n_0_52, n_0_53, n_0_54, n_0_55, n_0_56, n_0_57, n_0_58, n_0_59, n_0_60, + n_0_61, n_0_62, n_0_63, n_0_64, n_0_65, n_0_66, n_0_67, n_0_68, n_0_69, + n_0_70, n_0_71, n_0_72, n_0_73, n_0_74, n_0_75, n_0_76, n_0_77, n_0_78, + n_0_79, n_0_80, n_0_81, n_0_82, n_0_83, n_0_84, n_0_85, n_0_86, n_0_87, + n_0_88, n_0_89, n_0_90, n_0_91, n_0_92, n_0_93, n_0_94, n_0_95, n_0_96, + n_0_97, n_0_98, n_0_99, n_0_100, n_0_101, n_0_102, n_0_103, n_0_104, + n_0_105, n_0_106, n_0_107, n_0_108, n_0_109, n_0_110, n_0_111, n_0_112, + n_0_113, n_0_114, n_0_115, n_0_116, n_0_117, n_0_118, n_0_119, n_0_120, + n_0_121, n_0_122, n_0_123, n_0_124, n_0_125, n_0_126, n_0_127, n_0_128, + n_0_129, n_0_130, n_0_131, n_0_132, n_0_133, n_0_134, n_0_135, n_0_136, + n_0_137, n_0_138, n_0_139, n_0_140, n_0_141, n_0_142, n_0_143, n_0_144, + n_0_145, n_0_146, n_0_147, n_0_148, n_0_149, n_0_150, n_0_151, n_0_152, + n_0_153, n_0_154, n_0_155, n_0_156, n_0_157, n_0_158, n_0_159, n_0_160, + n_0_161, n_0_162, n_0_163, n_0_164, n_0_165, n_0_166, n_0_167, n_0_168, + n_0_169, n_0_170, n_0_171, n_0_172, n_0_173, n_0_174, n_0_175, n_0_176, + n_0_177, n_0_178, n_0_179, n_0_180, n_0_181, n_0_182, n_0_183, n_0_184, + n_0_185, n_0_186, n_0_187, n_0_188, n_0_189, n_0_190, n_0_191, n_0_192, + n_0_193, n_0_194, n_0_195, n_0_196, n_0_197, n_0_198, n_0_199, n_0_200, + n_0_201, n_0_202, n_0_203, n_0_204, n_0_205, n_0_206, n_0_207, n_0_208, + n_0_209, n_0_210, n_0_211, n_0_212, n_0_213, n_0_214, n_0_215, n_0_216, + n_0_217, n_0_218, n_0_219, n_0_220, n_0_221, n_0_222, n_0_223, n_0_224, + n_0_225, n_0_226, n_0_227, n_0_228, n_0_229, n_0_230, n_0_231, n_0_232, + n_0_233, n_0_234, n_0_235, n_0_236, n_0_237, n_0_238, n_0_239, n_0_240, + n_0_241, n_0_242, n_0_243, n_0_244, n_0_245, n_0_246, n_0_247, n_0_248, + n_0_249, n_0_250, n_0_251, n_0_252, n_0_253, n_0_254, n_0_255, n_0_256, + n_0_257, n_0_258, n_0_259, n_0_260, n_0_261, n_0_262, n_0_263, n_0_264, + n_0_265, n_0_266, n_0_267, n_0_268, n_0_269, n_0_270, n_0_271, n_0_272, + n_0_273, n_0_274, n_0_275, n_0_276, n_0_277, n_0_278, n_0_279, n_0_280, + n_0_281, n_0_282, n_0_283, n_0_284, n_0_285, n_0_286, n_0_287, n_0_288, + n_0_289, n_0_290, n_0_291, n_0_292, n_0_293, n_0_294, n_0_295, n_0_296, + n_0_297, n_0_298, n_0_299, n_0_300, n_0_301, n_0_302, n_0_303, n_0_304, + n_0_305, n_0_306, n_0_307, n_0_308, n_0_309, n_0_310, n_0_311, n_0_312, + n_0_313, n_0_314, n_0_315, n_0_316, n_0_317, n_0_318, n_0_319, n_0_320, + n_0_321, n_0_322, n_0_323, n_0_324, n_0_325, n_0_326, n_0_327, n_0_328, + n_0_329, n_0_330, n_0_331, n_0_332, n_0_333, n_0_334, n_0_335, n_0_336, + n_0_337, n_0_338, n_0_339, n_0_340, n_0_341, n_0_342, n_0_343, n_0_344, + n_0_345, n_0_346, n_0_347, n_0_348, n_0_349, n_0_350, n_0_351, n_0_352, + n_0_353, n_0_354, n_0_355, n_0_356, n_0_357, n_0_358, n_0_359, n_0_360, + n_0_361, n_0_362, n_0_363, n_0_364, n_0_365, n_0_366, n_0_367, n_0_368, + n_0_369, n_0_370, n_0_371, n_0_372, n_0_373, n_0_374, n_0_375, n_0_376, + n_0_377, n_0_378, n_0_379, n_0_380, n_0_381, n_0_382, n_0_383, n_0_384, + n_0_385, n_0_386, n_0_387, n_0_388, n_0_389, n_0_390, n_0_391, n_0_392, + n_0_393, n_0_394, n_0_395, n_0_396, n_0_397, n_0_398, n_0_399, n_0_400, + n_0_401, n_0_402, n_0_403, n_0_404, n_0_405, n_0_406, n_0_407, n_0_408, + n_0_409, n_0_410, n_0_411, n_0_412, n_0_413, n_0_414, n_0_415, n_0_416, + n_0_417, n_0_418, n_0_419, n_0_420, n_0_421, n_0_422, n_0_423, n_0_424, + n_0_425, n_0_426, n_0_427, n_0_428, n_0_429, n_0_430, n_0_431, n_0_432, + n_0_433, n_0_434, n_0_435, n_0_436, n_0_437, n_0_438, n_0_439, n_0_440, + n_0_441, n_0_442, n_0_443, n_0_444, n_0_445, n_0_446, n_0_447, n_0_448, + n_0_449, n_0_450, n_0_451, n_0_452, n_0_453, n_0_454, n_0_455, n_0_456, + n_0_457, n_0_458, n_0_459, n_0_460, n_0_461, n_0_462, n_0_463, n_0_464, + n_0_465, n_0_466, n_0_467, n_0_468, n_0_469, n_0_470, n_0_471, n_0_472, + n_0_473, n_0_474, n_0_475, n_0_476, n_0_477, n_0_478, n_0_479, n_0_480, + n_0_481, n_0_482, n_0_483, n_0_484, n_0_485, n_0_486, n_0_487, n_0_488, + n_0_489, n_0_490, n_0_491, n_0_492, n_0_493, n_0_494, n_0_495, n_0_496, + n_0_497, n_0_498, n_0_499, n_0_500, n_0_501, n_0_502, n_0_503, n_0_504, + n_0_505, n_0_506, n_0_507, n_0_508, n_0_509, n_0_510, n_0_511, n_0_512, + n_0_513, n_0_514, n_0_515, n_0_516, n_0_517, n_0_518, n_0_519, n_0_520, + n_0_521, n_0_522, n_0_523, n_0_524, n_0_525, n_0_526, n_0_527, n_0_528, + n_0_529, n_0_530, n_0_531, n_0_532, n_0_533, n_0_534, n_0_535, n_0_536, + n_0_537, n_0_538, n_0_539, n_0_540, n_0_541, n_0_542, n_0_543, n_0_544, + n_0_545, n_0_546, n_0_547, n_0_548, n_0_549, n_0_550, n_0_551, n_0_552, + n_0_553, n_0_554, n_0_555, n_0_556, n_0_557, n_0_558, n_0_559, n_0_560, + n_0_561, n_0_562, n_0_563, n_0_564, n_0_565, n_0_566, n_0_567, n_0_568, + n_0_569, n_0_570, n_0_571, n_0_572, n_0_573, n_0_574, n_0_575, n_0_576, + n_0_577, n_0_578, n_0_579, n_0_580, n_0_581, n_0_582, n_0_583, n_0_584, + n_0_585, n_0_586, n_0_587, n_0_588, n_0_589, n_0_590, n_0_591, n_0_592, + n_0_593, n_0_594, n_0_595, n_0_596, n_0_597, n_0_598, n_0_599, n_0_600, + n_0_601, n_0_602, n_0_603, n_0_604, n_0_605, n_0_606, n_0_607, n_0_608, + n_0_609, n_0_610, n_0_611, n_0_612, n_0_613, n_0_614, n_0_615, n_0_616, + n_0_617, n_0_618, n_0_619, n_0_620, n_0_621, n_0_622, n_0_623, n_0_624, + n_0_625, n_0_626, n_0_627, n_0_628, n_0_629, n_0_630, n_0_631, n_0_632, + n_0_633, n_0_634, n_0_635, n_0_636, n_0_637, n_0_638, n_0_639, n_0_640, + n_0_641, n_0_642, n_0_643, n_0_644, n_0_645, n_0_646, n_0_647, n_0_648, + n_0_649, n_0_650, n_0_651, n_0_652, n_0_653, n_0_654, n_0_655, n_0_656, + n_0_657, n_0_658, n_0_659, n_0_660, n_0_661, n_0_662, n_0_663, n_0_664, + n_0_665, n_0_666, n_0_667, n_0_668, n_0_669, n_0_670, n_0_671, n_0_672, + n_0_673, n_0_674, n_0_675, n_0_676, n_0_677, n_0_678, n_0_679, n_0_680, + n_0_681, n_0_682, n_0_683, n_0_684, n_0_685, n_0_686, n_0_687, n_0_688, + n_0_689, n_0_690, n_0_691, n_0_692, n_0_693, n_0_694, n_0_695, n_0_696, + n_0_697, n_0_698, n_0_699, n_0_700, n_0_701, n_0_702, n_0_703, n_0_704, + n_0_705, n_0_706, n_0_707, n_0_708, n_0_709, n_0_710, n_0_711, n_0_712, + n_0_713, n_0_714, n_0_715, n_0_716, n_0_717, n_0_718, n_0_719, n_0_720, + n_0_721, n_0_722, n_0_723, n_0_724, n_0_725, n_0_726, n_0_727, n_0_728, + n_0_729, n_0_730, n_0_731, n_0_732, n_0_733, n_0_734, n_0_735, n_0_736, + n_0_737, n_0_738, n_0_739, n_0_740, n_0, n_1, n_2, n_3, n_4, n_5, n_6, + n_7, n_8, n_9, n_10, n_11, n_12, n_13, n_14, n_15, n_16, n_17, n_18, + n_19, n_20, n_21, n_22, n_23, n_24, n_25, n_26, n_27, n_28, n_29, n_30, + n_31, n_63, n_62, n_61, n_60, n_59, n_58, n_57, n_56, n_55, n_54, n_53, + n_52, n_51, n_50, n_49, n_48, n_47, n_46, n_45, n_44, n_43, n_42, n_41, + n_40, n_39, n_38, n_37, n_36, n_35, n_34, n_33, n_32; + + INV_X1_LVT i_0_725( + .A(op2[31]), .ZN(n_0_692) + ); + INV_X1_LVT i_0_724( + .A(op1[31]), .ZN(n_0_691) + ); + INV_X1_LVT i_0_718( + .A(aluOp[1]), .ZN(n_0_685) + ); + INV_X1_LVT i_0_717( + .A(aluOp[2]), .ZN(n_0_684) + ); + NOR2_X1_LVT i_0_599( + .A1(n_0_685), .A2(n_0_684), .ZN(n_0_567) + ); + INV_X1_LVT i_0_598( + .A(n_0_567), .ZN(n_0_566) + ); + INV_X1_LVT i_0_716( + .A(aluOp[0]), .ZN(n_0_683) + ); + NAND2_X1_LVT i_0_602( + .A1(aluOp[2]), .A2(aluNegAr), .ZN(n_0_570) + ); + OAI21_X1_LVT i_0_590( + .A(n_0_566), .B1(n_0_683), .B2(n_0_570), .ZN(n_0_558) + ); + INV_X1_LVT i_0_714( + .A(aluBypass), .ZN(n_0_681) + ); + NOR2_X1_LVT i_0_601( + .A1(n_0_684), .A2(aluOp[0]), .ZN(n_0_569) + ); + NAND2_X1_LVT i_0_597( + .A1(n_0_681), .A2(n_0_569), .ZN(n_0_565) + ); + INV_X1_LVT i_0_596( + .A(n_0_565), .ZN(n_0_564) + ); + OAI22_X1_LVT i_0_589( + .A1(n_0_691), .A2(n_0_558), .B1(op1[31]), .B2(n_0_564), .ZN(n_0_557) + ); + NOR2_X1_LVT i_0_588( + .A1(n_0_692), .A2(n_0_557), .ZN(n_0_556) + ); + XNOR2_X1_LVT i_9_31( + .A(op2[31]), .B(op1[31]), .ZN(n_9_31) + ); + HA_X1_LVT i_9_0( + .A(op2[0]), .B(op1[0]), .CO(n_9_0), .S(n_0) + ); + FA_X1_LVT i_9_1( + .A(op2[1]), .B(op1[1]), .CI(n_9_0), .CO(n_9_1), .S(n_1) + ); + FA_X1_LVT i_9_2( + .A(op2[2]), .B(op1[2]), .CI(n_9_1), .CO(n_9_2), .S(n_2) + ); + FA_X1_LVT i_9_3( + .A(op2[3]), .B(op1[3]), .CI(n_9_2), .CO(n_9_3), .S(n_3) + ); + FA_X1_LVT i_9_4( + .A(op2[4]), .B(op1[4]), .CI(n_9_3), .CO(n_9_4), .S(n_4) + ); + FA_X1_LVT i_9_5( + .A(op2[5]), .B(op1[5]), .CI(n_9_4), .CO(n_9_5), .S(n_5) + ); + FA_X1_LVT i_9_6( + .A(op2[6]), .B(op1[6]), .CI(n_9_5), .CO(n_9_6), .S(n_6) + ); + FA_X1_LVT i_9_7( + .A(op2[7]), .B(op1[7]), .CI(n_9_6), .CO(n_9_7), .S(n_7) + ); + FA_X1_LVT i_9_8( + .A(op2[8]), .B(op1[8]), .CI(n_9_7), .CO(n_9_8), .S(n_8) + ); + FA_X1_LVT i_9_9( + .A(op2[9]), .B(op1[9]), .CI(n_9_8), .CO(n_9_9), .S(n_9) + ); + FA_X1_LVT i_9_10( + .A(op2[10]), .B(op1[10]), .CI(n_9_9), .CO(n_9_10), .S(n_10) + ); + FA_X1_LVT i_9_11( + .A(op2[11]), .B(op1[11]), .CI(n_9_10), .CO(n_9_11), .S(n_11) + ); + FA_X1_LVT i_9_12( + .A(op2[12]), .B(op1[12]), .CI(n_9_11), .CO(n_9_12), .S(n_12) + ); + FA_X1_LVT i_9_13( + .A(op2[13]), .B(op1[13]), .CI(n_9_12), .CO(n_9_13), .S(n_13) + ); + FA_X1_LVT i_9_14( + .A(op2[14]), .B(op1[14]), .CI(n_9_13), .CO(n_9_14), .S(n_14) + ); + FA_X1_LVT i_9_15( + .A(op2[15]), .B(op1[15]), .CI(n_9_14), .CO(n_9_15), .S(n_15) + ); + FA_X1_LVT i_9_16( + .A(op2[16]), .B(op1[16]), .CI(n_9_15), .CO(n_9_16), .S(n_16) + ); + FA_X1_LVT i_9_17( + .A(op2[17]), .B(op1[17]), .CI(n_9_16), .CO(n_9_17), .S(n_17) + ); + FA_X1_LVT i_9_18( + .A(op2[18]), .B(op1[18]), .CI(n_9_17), .CO(n_9_18), .S(n_18) + ); + FA_X1_LVT i_9_19( + .A(op2[19]), .B(op1[19]), .CI(n_9_18), .CO(n_9_19), .S(n_19) + ); + FA_X1_LVT i_9_20( + .A(op2[20]), .B(op1[20]), .CI(n_9_19), .CO(n_9_20), .S(n_20) + ); + FA_X1_LVT i_9_21( + .A(op2[21]), .B(op1[21]), .CI(n_9_20), .CO(n_9_21), .S(n_21) + ); + FA_X1_LVT i_9_22( + .A(op2[22]), .B(op1[22]), .CI(n_9_21), .CO(n_9_22), .S(n_22) + ); + FA_X1_LVT i_9_23( + .A(op2[23]), .B(op1[23]), .CI(n_9_22), .CO(n_9_23), .S(n_23) + ); + FA_X1_LVT i_9_24( + .A(op2[24]), .B(op1[24]), .CI(n_9_23), .CO(n_9_24), .S(n_24) + ); + FA_X1_LVT i_9_25( + .A(op2[25]), .B(op1[25]), .CI(n_9_24), .CO(n_9_25), .S(n_25) + ); + FA_X1_LVT i_9_26( + .A(op2[26]), .B(op1[26]), .CI(n_9_25), .CO(n_9_26), .S(n_26) + ); + FA_X1_LVT i_9_27( + .A(op2[27]), .B(op1[27]), .CI(n_9_26), .CO(n_9_27), .S(n_27) + ); + FA_X1_LVT i_9_28( + .A(op2[28]), .B(op1[28]), .CI(n_9_27), .CO(n_9_28), .S(n_28) + ); + FA_X1_LVT i_9_29( + .A(op2[29]), .B(op1[29]), .CI(n_9_28), .CO(n_9_29), .S(n_29) + ); + FA_X1_LVT i_9_30( + .A(op2[30]), .B(op1[30]), .CI(n_9_29), .CO(n_9_30), .S(n_30) + ); + XNOR2_X1_LVT i_9_32( + .A(n_9_31), .B(n_9_30), .ZN(n_31) + ); + NAND4_X1_LVT i_0_614( + .A1(n_0_685), .A2(n_0_681), .A3(n_0_684), .A4(n_0_683), .ZN(n_0_582) + ); + NOR2_X1_LVT i_0_613( + .A1(aluNegAr), .A2(n_0_582), .ZN(n_0_581) + ); + INV_X1_LVT i_10_147( + .A(op2[30]), .ZN(n_10_117) + ); + NAND2_X1_LVT i_10_149( + .A1(n_10_117), .A2(op1[30]), .ZN(n_10_119) + ); + INV_X1_LVT i_10_152( + .A(n_10_119), .ZN(n_10_121) + ); + INV_X1_LVT i_10_130( + .A(op1[26]), .ZN(n_10_104) + ); + NAND2_X1_LVT i_10_131( + .A1(n_10_104), .A2(op2[26]), .ZN(n_10_105) + ); + INV_X1_LVT i_10_123( + .A(op2[25]), .ZN(n_10_98) + ); + NAND2_X1_LVT i_10_125( + .A1(n_10_98), .A2(op1[25]), .ZN(n_10_100) + ); + INV_X1_LVT i_10_112( + .A(op2[23]), .ZN(n_10_89) + ); + NAND2_X1_LVT i_10_114( + .A1(n_10_89), .A2(op1[23]), .ZN(n_10_91) + ); + INV_X1_LVT i_10_101( + .A(op2[21]), .ZN(n_10_80) + ); + NAND2_X1_LVT i_10_103( + .A1(n_10_80), .A2(op1[21]), .ZN(n_10_82) + ); + INV_X1_LVT i_10_48( + .A(op1[8]), .ZN(n_10_40) + ); + NAND2_X1_LVT i_10_49( + .A1(n_10_40), .A2(op2[8]), .ZN(n_10_41) + ); + INV_X1_LVT i_10_41( + .A(op2[7]), .ZN(n_10_34) + ); + NAND2_X1_LVT i_10_43( + .A1(n_10_34), .A2(op1[7]), .ZN(n_10_36) + ); + INV_X1_LVT i_10_32( + .A(op2[5]), .ZN(n_10_27) + ); + NOR2_X1_LVT i_10_33( + .A1(n_10_27), .A2(op1[5]), .ZN(n_10_28) + ); + INV_X1_LVT i_10_24( + .A(op1[4]), .ZN(n_10_20) + ); + NOR2_X1_LVT i_10_27( + .A1(n_10_20), .A2(op2[4]), .ZN(n_10_23) + ); + INV_X1_LVT i_10_17( + .A(op2[3]), .ZN(n_10_14) + ); + NAND2_X1_LVT i_10_19( + .A1(n_10_14), .A2(op1[3]), .ZN(n_10_16) + ); + INV_X1_LVT i_10_22( + .A(n_10_16), .ZN(n_10_18) + ); + INV_X1_LVT i_10_10( + .A(op2[2]), .ZN(n_10_8) + ); + NAND2_X1_LVT i_10_12( + .A1(n_10_8), .A2(op1[2]), .ZN(n_10_10) + ); + INV_X1_LVT i_10_3( + .A(op1[1]), .ZN(n_10_2) + ); + NAND2_X1_LVT i_10_5( + .A1(n_10_2), .A2(op2[1]), .ZN(n_10_4) + ); + INV_X1_LVT i_10_0( + .A(op1[0]), .ZN(n_10_0) + ); + NAND2_X1_LVT i_10_1( + .A1(n_10_0), .A2(op2[0]), .ZN(n_10_1) + ); + OR2_X1_LVT i_10_4( + .A1(n_10_2), .A2(op2[1]), .ZN(n_10_3) + ); + INV_X1_LVT i_10_8( + .A(n_10_3), .ZN(n_10_6) + ); + OAI21_X1_LVT i_10_9( + .A(n_10_4), .B1(n_10_1), .B2(n_10_6), .ZN(n_10_7) + ); + NOR2_X1_LVT i_10_11( + .A1(n_10_8), .A2(op1[2]), .ZN(n_10_9) + ); + OAI21_X1_LVT i_10_16( + .A(n_10_10), .B1(n_10_7), .B2(n_10_9), .ZN(n_10_13) + ); + OR2_X1_LVT i_10_18( + .A1(n_10_14), .A2(op1[3]), .ZN(n_10_15) + ); + AOI21_X1_LVT i_10_23( + .A(n_10_18), .B1(n_10_13), .B2(n_10_15), .ZN(n_10_19) + ); + INV_X1_LVT i_10_30( + .A(n_10_19), .ZN(n_10_25) + ); + NAND2_X1_LVT i_10_25( + .A1(n_10_20), .A2(op2[4]), .ZN(n_10_21) + ); + AOI21_X1_LVT i_10_31( + .A(n_10_23), .B1(n_10_25), .B2(n_10_21), .ZN(n_10_26) + ); + AOI21_X1_LVT i_10_34( + .A(n_10_28), .B1(n_10_27), .B2(op1[5]), .ZN(n_10_29) + ); + AOI21_X1_LVT i_10_36( + .A(n_10_28), .B1(n_10_26), .B2(n_10_29), .ZN(n_10_30) + ); + XOR2_X1_LVT i_10_37( + .A(op2[6]), .B(op1[6]), .Z(n_10_31) + ); + INV_X1_LVT i_10_39( + .A(op2[6]), .ZN(n_10_32) + ); + OAI22_X1_LVT i_10_40( + .A1(n_10_30), .A2(n_10_31), .B1(n_10_32), .B2(op1[6]), .ZN(n_10_33) + ); + NOR2_X1_LVT i_10_42( + .A1(n_10_34), .A2(op1[7]), .ZN(n_10_35) + ); + OAI21_X1_LVT i_10_47( + .A(n_10_36), .B1(n_10_33), .B2(n_10_35), .ZN(n_10_39) + ); + OAI21_X1_LVT i_10_50( + .A(n_10_41), .B1(n_10_40), .B2(op2[8]), .ZN(n_10_42) + ); + OAI21_X1_LVT i_10_52( + .A(n_10_41), .B1(n_10_39), .B2(n_10_42), .ZN(n_10_43) + ); + XNOR2_X1_LVT i_10_53( + .A(op2[9]), .B(op1[9]), .ZN(n_10_44) + ); + INV_X1_LVT i_10_55( + .A(op1[9]), .ZN(n_10_45) + ); + AOI22_X1_LVT i_10_56( + .A1(n_10_43), .A2(n_10_44), .B1(n_10_45), .B2(op2[9]), .ZN(n_10_46) + ); + XOR2_X1_LVT i_10_57( + .A(op2[10]), .B(op1[10]), .Z(n_10_47) + ); + INV_X1_LVT i_10_59( + .A(op2[10]), .ZN(n_10_48) + ); + OAI22_X1_LVT i_10_60( + .A1(n_10_46), .A2(n_10_47), .B1(n_10_48), .B2(op1[10]), .ZN(n_10_49) + ); + XNOR2_X1_LVT i_10_61( + .A(op2[11]), .B(op1[11]), .ZN(n_10_50) + ); + INV_X1_LVT i_10_63( + .A(op1[11]), .ZN(n_10_51) + ); + AOI22_X1_LVT i_10_64( + .A1(n_10_49), .A2(n_10_50), .B1(n_10_51), .B2(op2[11]), .ZN(n_10_52) + ); + XOR2_X1_LVT i_10_65( + .A(op2[12]), .B(op1[12]), .Z(n_10_53) + ); + INV_X1_LVT i_10_67( + .A(op2[12]), .ZN(n_10_54) + ); + OAI22_X1_LVT i_10_68( + .A1(n_10_52), .A2(n_10_53), .B1(n_10_54), .B2(op1[12]), .ZN(n_10_55) + ); + XNOR2_X1_LVT i_10_69( + .A(op2[13]), .B(op1[13]), .ZN(n_10_56) + ); + INV_X1_LVT i_10_71( + .A(op1[13]), .ZN(n_10_57) + ); + AOI22_X1_LVT i_10_72( + .A1(n_10_55), .A2(n_10_56), .B1(n_10_57), .B2(op2[13]), .ZN(n_10_58) + ); + XOR2_X1_LVT i_10_73( + .A(op2[14]), .B(op1[14]), .Z(n_10_59) + ); + INV_X1_LVT i_10_75( + .A(op2[14]), .ZN(n_10_60) + ); + OAI22_X1_LVT i_10_76( + .A1(n_10_58), .A2(n_10_59), .B1(n_10_60), .B2(op1[14]), .ZN(n_10_61) + ); + XNOR2_X1_LVT i_10_77( + .A(op2[15]), .B(op1[15]), .ZN(n_10_62) + ); + INV_X1_LVT i_10_79( + .A(op1[15]), .ZN(n_10_63) + ); + AOI22_X1_LVT i_10_80( + .A1(n_10_61), .A2(n_10_62), .B1(n_10_63), .B2(op2[15]), .ZN(n_10_64) + ); + XOR2_X1_LVT i_10_81( + .A(op2[16]), .B(op1[16]), .Z(n_10_65) + ); + INV_X1_LVT i_10_83( + .A(op2[16]), .ZN(n_10_66) + ); + OAI22_X1_LVT i_10_84( + .A1(n_10_64), .A2(n_10_65), .B1(n_10_66), .B2(op1[16]), .ZN(n_10_67) + ); + XNOR2_X1_LVT i_10_85( + .A(op2[17]), .B(op1[17]), .ZN(n_10_68) + ); + INV_X1_LVT i_10_87( + .A(op1[17]), .ZN(n_10_69) + ); + AOI22_X1_LVT i_10_88( + .A1(n_10_67), .A2(n_10_68), .B1(n_10_69), .B2(op2[17]), .ZN(n_10_70) + ); + XOR2_X1_LVT i_10_89( + .A(op2[18]), .B(op1[18]), .Z(n_10_71) + ); + INV_X1_LVT i_10_91( + .A(op2[18]), .ZN(n_10_72) + ); + OAI22_X1_LVT i_10_92( + .A1(n_10_70), .A2(n_10_71), .B1(n_10_72), .B2(op1[18]), .ZN(n_10_73) + ); + XNOR2_X1_LVT i_10_93( + .A(op2[19]), .B(op1[19]), .ZN(n_10_74) + ); + INV_X1_LVT i_10_95( + .A(op1[19]), .ZN(n_10_75) + ); + AOI22_X1_LVT i_10_96( + .A1(n_10_73), .A2(n_10_74), .B1(n_10_75), .B2(op2[19]), .ZN(n_10_76) + ); + XOR2_X1_LVT i_10_97( + .A(op2[20]), .B(op1[20]), .Z(n_10_77) + ); + INV_X1_LVT i_10_99( + .A(op2[20]), .ZN(n_10_78) + ); + OAI22_X1_LVT i_10_100( + .A1(n_10_76), .A2(n_10_77), .B1(n_10_78), .B2(op1[20]), .ZN(n_10_79) + ); + NOR2_X1_LVT i_10_102( + .A1(n_10_80), .A2(op1[21]), .ZN(n_10_81) + ); + OAI21_X1_LVT i_10_107( + .A(n_10_82), .B1(n_10_79), .B2(n_10_81), .ZN(n_10_85) + ); + XOR2_X1_LVT i_10_108( + .A(op2[22]), .B(op1[22]), .Z(n_10_86) + ); + INV_X1_LVT i_10_110( + .A(op2[22]), .ZN(n_10_87) + ); + OAI22_X1_LVT i_10_111( + .A1(n_10_85), .A2(n_10_86), .B1(n_10_87), .B2(op1[22]), .ZN(n_10_88) + ); + NOR2_X1_LVT i_10_113( + .A1(n_10_89), .A2(op1[23]), .ZN(n_10_90) + ); + OAI21_X1_LVT i_10_118( + .A(n_10_91), .B1(n_10_88), .B2(n_10_90), .ZN(n_10_94) + ); + XOR2_X1_LVT i_10_119( + .A(op2[24]), .B(op1[24]), .Z(n_10_95) + ); + INV_X1_LVT i_10_121( + .A(op2[24]), .ZN(n_10_96) + ); + OAI22_X1_LVT i_10_122( + .A1(n_10_94), .A2(n_10_95), .B1(n_10_96), .B2(op1[24]), .ZN(n_10_97) + ); + NOR2_X1_LVT i_10_124( + .A1(n_10_98), .A2(op1[25]), .ZN(n_10_99) + ); + OAI21_X1_LVT i_10_129( + .A(n_10_100), .B1(n_10_97), .B2(n_10_99), .ZN(n_10_103) + ); + OAI21_X1_LVT i_10_132( + .A(n_10_105), .B1(n_10_104), .B2(op2[26]), .ZN(n_10_106) + ); + OAI21_X1_LVT i_10_134( + .A(n_10_105), .B1(n_10_103), .B2(n_10_106), .ZN(n_10_107) + ); + XNOR2_X1_LVT i_10_135( + .A(op2[27]), .B(op1[27]), .ZN(n_10_108) + ); + INV_X1_LVT i_10_137( + .A(op1[27]), .ZN(n_10_109) + ); + AOI22_X1_LVT i_10_138( + .A1(n_10_107), .A2(n_10_108), .B1(n_10_109), .B2(op2[27]), .ZN(n_10_110) + ); + XOR2_X1_LVT i_10_139( + .A(op2[28]), .B(op1[28]), .Z(n_10_111) + ); + INV_X1_LVT i_10_141( + .A(op2[28]), .ZN(n_10_112) + ); + OAI22_X1_LVT i_10_142( + .A1(n_10_110), .A2(n_10_111), .B1(n_10_112), .B2(op1[28]), .ZN(n_10_113) + ); + XNOR2_X1_LVT i_10_143( + .A(op2[29]), .B(op1[29]), .ZN(n_10_114) + ); + INV_X1_LVT i_10_145( + .A(op1[29]), .ZN(n_10_115) + ); + AOI22_X1_LVT i_10_146( + .A1(n_10_113), .A2(n_10_114), .B1(n_10_115), .B2(op2[29]), .ZN(n_10_116) + ); + OR2_X1_LVT i_10_148( + .A1(n_10_117), .A2(op1[30]), .ZN(n_10_118) + ); + AOI21_X1_LVT i_10_153( + .A(n_10_121), .B1(n_10_116), .B2(n_10_118), .ZN(n_10_122) + ); + XNOR2_X1_LVT i_10_154( + .A(op1[31]), .B(op2[31]), .ZN(n_10_123) + ); + XNOR2_X1_LVT i_10_155( + .A(n_10_122), .B(n_10_123), .ZN(n_63) + ); + INV_X1_LVT i_0_715( + .A(aluNegAr), .ZN(n_0_682) + ); + NOR2_X1_LVT i_0_612( + .A1(n_0_682), .A2(n_0_582), .ZN(n_0_580) + ); + AOI221_X1_LVT i_0_587( + .A(n_0_556), .B1(n_31), .B2(n_0_581), .C1(n_63), .C2(n_0_580), .ZN(n_0_555) + ); + NOR3_X1_LVT i_0_654( + .A1(aluOp[1]), .A2(aluBypass), .A3(n_0_683), .ZN(n_0_622) + ); + NAND2_X1_LVT i_0_653( + .A1(n_0_684), .A2(n_0_622), .ZN(n_0_621) + ); + INV_X1_LVT i_0_734( + .A(op2[0]), .ZN(n_0_701) + ); + INV_X1_LVT i_0_756( + .A(op2[3]), .ZN(n_0_723) + ); + NOR2_X1_LVT i_0_650( + .A1(op2[4]), .A2(n_0_723), .ZN(n_0_618) + ); + INV_X1_LVT i_0_649( + .A(n_0_618), .ZN(n_0_617) + ); + NOR2_X1_LVT i_0_648( + .A1(op2[4]), .A2(op2[3]), .ZN(n_0_616) + ); + INV_X1_LVT i_0_647( + .A(n_0_616), .ZN(n_0_615) + ); + INV_X1_LVT i_0_771( + .A(op2[4]), .ZN(n_0_738) + ); + INV_X1_LVT i_0_767( + .A(op1[15]), .ZN(n_0_734) + ); + INV_X1_LVT i_0_746( + .A(op1[7]), .ZN(n_0_713) + ); + AOI22_X1_LVT i_0_651( + .A1(n_0_734), .A2(n_0_723), .B1(op2[3]), .B2(n_0_713), .ZN(n_0_619) + ); + OAI222_X1_LVT i_0_646( + .A1(op1[23]), .A2(n_0_617), .B1(op1[31]), .B2(n_0_615), .C1(n_0_738), .C2(n_0_619), + .ZN(n_0_614) + ); + NOR2_X1_LVT i_0_645( + .A1(op2[2]), .A2(n_0_614), .ZN(n_0_613) + ); + NOR2_X1_LVT i_0_696( + .A1(op1[3]), .A2(n_0_723), .ZN(n_0_663) + ); + INV_X1_LVT i_0_739( + .A(op1[11]), .ZN(n_0_706) + ); + AOI21_X1_LVT i_0_644( + .A(n_0_663), .B1(n_0_723), .B2(n_0_706), .ZN(n_0_612) + ); + AOI22_X1_LVT i_0_643( + .A1(op2[4]), .A2(n_0_612), .B1(op1[27]), .B2(n_0_616), .ZN(n_0_611) + ); + INV_X1_LVT i_0_722( + .A(op1[19]), .ZN(n_0_689) + ); + OAI21_X1_LVT i_0_642( + .A(n_0_611), .B1(n_0_689), .B2(n_0_617), .ZN(n_0_610) + ); + AOI21_X1_LVT i_0_641( + .A(n_0_613), .B1(op2[2]), .B2(n_0_610), .ZN(n_0_609) + ); + INV_X1_LVT i_0_761( + .A(op2[1]), .ZN(n_0_728) + ); + OAI22_X1_LVT i_0_640( + .A1(op2[4]), .A2(op1[21]), .B1(n_0_738), .B2(op1[5]), .ZN(n_0_608) + ); + NAND2_X1_LVT i_0_639( + .A1(op2[3]), .A2(n_0_608), .ZN(n_0_607) + ); + INV_X1_LVT i_0_747( + .A(op1[13]), .ZN(n_0_714) + ); + NOR2_X1_LVT i_0_638( + .A1(n_0_738), .A2(op2[3]), .ZN(n_0_606) + ); + INV_X1_LVT i_0_743( + .A(op1[29]), .ZN(n_0_710) + ); + AOI221_X1_LVT i_0_636( + .A(op2[2]), .B1(n_0_714), .B2(n_0_606), .C1(n_0_710), .C2(n_0_616), .ZN(n_0_604) + ); + OAI22_X1_LVT i_0_635( + .A1(op2[4]), .A2(op1[17]), .B1(n_0_738), .B2(op1[1]), .ZN(n_0_603) + ); + INV_X1_LVT i_0_755( + .A(op1[9]), .ZN(n_0_722) + ); + INV_X1_LVT i_0_637( + .A(n_0_606), .ZN(n_0_605) + ); + INV_X1_LVT i_0_732( + .A(op1[25]), .ZN(n_0_699) + ); + OAI222_X1_LVT i_0_634( + .A1(n_0_723), .A2(n_0_603), .B1(n_0_722), .B2(n_0_605), .C1(n_0_699), .C2(n_0_615), + .ZN(n_0_602) + ); + AOI22_X1_LVT i_0_633( + .A1(n_0_607), .A2(n_0_604), .B1(op2[2]), .B2(n_0_602), .ZN(n_0_601) + ); + OAI221_X1_LVT i_0_616( + .A(n_0_701), .B1(op2[1]), .B2(n_0_609), .C1(n_0_728), .C2(n_0_601), .ZN(n_0_584) + ); + INV_X1_LVT i_0_729( + .A(op1[12]), .ZN(n_0_696) + ); + INV_X1_LVT i_0_731( + .A(op1[28]), .ZN(n_0_698) + ); + AOI22_X1_LVT i_0_622( + .A1(n_0_696), .A2(n_0_606), .B1(n_0_698), .B2(n_0_616), .ZN(n_0_590) + ); + INV_X1_LVT i_0_726( + .A(op2[2]), .ZN(n_0_693) + ); + NOR2_X1_LVT i_0_701( + .A1(n_0_738), .A2(op1[4]), .ZN(n_0_668) + ); + INV_X1_LVT i_0_760( + .A(op1[20]), .ZN(n_0_727) + ); + AOI21_X1_LVT i_0_623( + .A(n_0_668), .B1(n_0_738), .B2(n_0_727), .ZN(n_0_591) + ); + OAI211_X1_LVT i_0_621( + .A(n_0_590), .B(n_0_693), .C1(n_0_723), .C2(n_0_591), .ZN(n_0_589) + ); + OAI22_X1_LVT i_0_626( + .A1(op1[16]), .A2(op2[4]), .B1(n_0_738), .B2(op1[0]), .ZN(n_0_594) + ); + INV_X1_LVT i_0_769( + .A(op1[24]), .ZN(n_0_736) + ); + OAI22_X1_LVT i_0_625( + .A1(n_0_723), .A2(n_0_594), .B1(n_0_736), .B2(n_0_615), .ZN(n_0_593) + ); + AOI21_X1_LVT i_0_624( + .A(n_0_593), .B1(op1[8]), .B2(n_0_606), .ZN(n_0_592) + ); + OAI21_X1_LVT i_0_620( + .A(n_0_589), .B1(n_0_693), .B2(n_0_592), .ZN(n_0_588) + ); + INV_X1_LVT i_0_737( + .A(op1[6]), .ZN(n_0_704) + ); + INV_X1_LVT i_0_720( + .A(op1[22]), .ZN(n_0_687) + ); + OAI22_X1_LVT i_0_632( + .A1(n_0_738), .A2(n_0_704), .B1(op2[4]), .B2(n_0_687), .ZN(n_0_600) + ); + OAI221_X1_LVT i_0_631( + .A(n_0_693), .B1(n_0_723), .B2(n_0_600), .C1(op1[14]), .C2(n_0_605), .ZN(n_0_599) + ); + INV_X1_LVT i_0_750( + .A(op1[30]), .ZN(n_0_717) + ); + AOI21_X1_LVT i_0_630( + .A(n_0_599), .B1(n_0_717), .B2(n_0_616), .ZN(n_0_598) + ); + INV_X1_LVT i_0_738( + .A(op1[18]), .ZN(n_0_705) + ); + NOR2_X1_LVT i_0_628( + .A1(n_0_705), .A2(n_0_617), .ZN(n_0_596) + ); + INV_X1_LVT i_0_727( + .A(op1[2]), .ZN(n_0_694) + ); + INV_X1_LVT i_0_766( + .A(op1[10]), .ZN(n_0_733) + ); + OAI22_X1_LVT i_0_629( + .A1(n_0_723), .A2(n_0_694), .B1(n_0_733), .B2(op2[3]), .ZN(n_0_597) + ); + AOI221_X1_LVT i_0_627( + .A(n_0_596), .B1(op1[26]), .B2(n_0_616), .C1(op2[4]), .C2(n_0_597), .ZN(n_0_595) + ); + OAI21_X1_LVT i_0_619( + .A(n_0_728), .B1(n_0_693), .B2(n_0_595), .ZN(n_0_587) + ); + OAI22_X1_LVT i_0_618( + .A1(n_0_728), .A2(n_0_588), .B1(n_0_598), .B2(n_0_587), .ZN(n_0_586) + ); + INV_X1_LVT i_0_617( + .A(n_0_586), .ZN(n_0_585) + ); + OAI21_X1_LVT i_0_615( + .A(n_0_584), .B1(n_0_701), .B2(n_0_585), .ZN(n_0_583) + ); + NOR2_X1_LVT i_0_607( + .A1(op2[4]), .A2(op2[2]), .ZN(n_0_575) + ); + NAND2_X1_LVT i_0_606( + .A1(n_0_723), .A2(n_0_575), .ZN(n_0_574) + ); + INV_X1_LVT i_0_605( + .A(n_0_574), .ZN(n_0_573) + ); + NAND2_X1_LVT i_0_604( + .A1(n_0_728), .A2(n_0_573), .ZN(n_0_572) + ); + NAND2_X1_LVT i_0_611( + .A1(aluOp[2]), .A2(n_0_622), .ZN(n_0_579) + ); + INV_X1_LVT i_0_610( + .A(n_0_579), .ZN(n_0_578) + ); + NAND2_X1_LVT i_0_594( + .A1(n_0_701), .A2(n_0_578), .ZN(n_0_562) + ); + NOR3_X1_LVT i_0_592( + .A1(aluNegAr), .A2(n_0_572), .A3(n_0_562), .ZN(n_0_560) + ); + INV_X1_LVT i_0_600( + .A(n_0_569), .ZN(n_0_568) + ); + OAI21_X1_LVT i_0_595( + .A(n_0_568), .B1(aluOp[1]), .B2(n_0_570), .ZN(n_0_563) + ); + AOI211_X1_LVT i_0_591( + .A(aluBypass), .B(n_0_560), .C1(n_0_692), .C2(n_0_563), .ZN(n_0_559) + ); + OAI221_X1_LVT i_0_586( + .A(n_0_555), .B1(n_0_621), .B2(n_0_583), .C1(n_0_691), .C2(n_0_559), .ZN(result[31]) + ); + NAND2_X1_LVT i_10_150( + .A1(n_10_118), .A2(n_10_119), .ZN(n_10_120) + ); + XNOR2_X1_LVT i_10_151( + .A(n_10_116), .B(n_10_120), .ZN(n_62) + ); + AOI22_X1_LVT i_0_580( + .A1(n_62), .A2(n_0_580), .B1(n_30), .B2(n_0_581), .ZN(n_0_549) + ); + NAND2_X1_LVT i_0_576( + .A1(aluNegAr), .A2(n_0_578), .ZN(n_0_545) + ); + INV_X1_LVT i_0_603( + .A(n_0_572), .ZN(n_0_571) + ); + NOR3_X1_LVT i_0_574( + .A1(n_0_691), .A2(n_0_545), .A3(n_0_571), .ZN(n_0_543) + ); + AOI22_X1_LVT i_0_573( + .A1(n_0_717), .A2(n_0_565), .B1(op1[30]), .B2(n_0_566), .ZN(n_0_542) + ); + AOI21_X1_LVT i_0_572( + .A(n_0_543), .B1(op2[30]), .B2(n_0_542), .ZN(n_0_541) + ); + NAND2_X1_LVT i_0_579( + .A1(op2[0]), .A2(n_0_578), .ZN(n_0_548) + ); + NAND2_X1_LVT i_0_577( + .A1(op1[31]), .A2(n_0_571), .ZN(n_0_546) + ); + OAI211_X1_LVT i_0_571( + .A(n_0_549), .B(n_0_541), .C1(n_0_548), .C2(n_0_546), .ZN(n_0_540) + ); + OAI221_X1_LVT i_0_581( + .A(n_0_681), .B1(op2[30]), .B2(n_0_568), .C1(n_0_572), .C2(n_0_562), .ZN(n_0_550) + ); + AOI21_X1_LVT i_0_570( + .A(n_0_540), .B1(op1[30]), .B2(n_0_550), .ZN(n_0_539) + ); + INV_X1_LVT i_0_752( + .A(op1[23]), .ZN(n_0_719) + ); + OAI222_X1_LVT i_0_585( + .A1(n_0_713), .A2(n_0_605), .B1(n_0_719), .B2(n_0_615), .C1(n_0_734), .C2(n_0_617), + .ZN(n_0_554) + ); + AOI22_X1_LVT i_0_584( + .A1(op2[2]), .A2(n_0_554), .B1(n_0_693), .B2(n_0_610), .ZN(n_0_553) + ); + OAI22_X1_LVT i_0_583( + .A1(n_0_728), .A2(n_0_553), .B1(op2[1]), .B2(n_0_601), .ZN(n_0_552) + ); + AOI22_X1_LVT i_0_582( + .A1(n_0_701), .A2(n_0_585), .B1(op2[0]), .B2(n_0_552), .ZN(n_0_551) + ); + OAI21_X1_LVT i_0_569( + .A(n_0_539), .B1(n_0_621), .B2(n_0_551), .ZN(result[30]) + ); + INV_X1_LVT i_0_578( + .A(n_0_548), .ZN(n_0_547) + ); + NAND3_X1_LVT i_0_562( + .A1(op1[30]), .A2(n_0_571), .A3(n_0_547), .ZN(n_0_532) + ); + XNOR2_X1_LVT i_10_144( + .A(n_10_113), .B(n_10_114), .ZN(n_61) + ); + NAND2_X1_LVT i_0_558( + .A1(n_61), .A2(n_0_580), .ZN(n_0_528) + ); + OAI21_X1_LVT i_0_557( + .A(n_0_681), .B1(op2[29]), .B2(n_0_568), .ZN(n_0_527) + ); + NAND2_X1_LVT i_0_556( + .A1(op1[29]), .A2(n_0_566), .ZN(n_0_526) + ); + AOI22_X1_LVT i_0_555( + .A1(op1[29]), .A2(n_0_527), .B1(op2[29]), .B2(n_0_526), .ZN(n_0_525) + ); + AOI21_X1_LVT i_0_554( + .A(n_0_525), .B1(n_0_710), .B2(n_0_565), .ZN(n_0_524) + ); + AOI211_X1_LVT i_0_553( + .A(n_0_543), .B(n_0_524), .C1(n_29), .C2(n_0_581), .ZN(n_0_523) + ); + AND3_X1_LVT i_0_552( + .A1(n_0_532), .A2(n_0_528), .A3(n_0_523), .ZN(n_0_522) + ); + INV_X1_LVT i_0_652( + .A(n_0_621), .ZN(n_0_620) + ); + NAND2_X1_LVT i_0_565( + .A1(n_0_728), .A2(n_0_588), .ZN(n_0_535) + ); + AOI22_X1_LVT i_0_568( + .A1(n_0_723), .A2(n_0_600), .B1(op1[14]), .B2(n_0_618), .ZN(n_0_538) + ); + AOI22_X1_LVT i_0_567( + .A1(n_0_693), .A2(n_0_595), .B1(op2[2]), .B2(n_0_538), .ZN(n_0_537) + ); + INV_X1_LVT i_0_566( + .A(n_0_537), .ZN(n_0_536) + ); + OAI21_X1_LVT i_0_564( + .A(n_0_535), .B1(n_0_728), .B2(n_0_536), .ZN(n_0_534) + ); + OAI221_X1_LVT i_0_563( + .A(n_0_620), .B1(op2[0]), .B2(n_0_552), .C1(n_0_701), .C2(n_0_534), .ZN(n_0_533) + ); + NAND2_X1_LVT i_0_561( + .A1(op2[1]), .A2(n_0_573), .ZN(n_0_531) + ); + INV_X1_LVT i_0_560( + .A(n_0_531), .ZN(n_0_530) + ); + AOI22_X1_LVT i_0_559( + .A1(op1[31]), .A2(n_0_530), .B1(op1[29]), .B2(n_0_571), .ZN(n_0_529) + ); + OAI211_X1_LVT i_0_551( + .A(n_0_522), .B(n_0_533), .C1(n_0_562), .C2(n_0_529), .ZN(result[29]) + ); + INV_X1_LVT i_0_733( + .A(op2[28]), .ZN(n_0_700) + ); + AOI221_X1_LVT i_0_546( + .A(n_0_700), .B1(op1[28]), .B2(n_0_566), .C1(n_0_698), .C2(n_0_565), .ZN(n_0_517) + ); + OAI21_X1_LVT i_0_543( + .A(n_0_681), .B1(op2[28]), .B2(n_0_568), .ZN(n_0_514) + ); + AOI22_X1_LVT i_0_542( + .A1(n_28), .A2(n_0_581), .B1(op1[28]), .B2(n_0_514), .ZN(n_0_513) + ); + XNOR2_X1_LVT i_10_140( + .A(n_10_110), .B(n_10_111), .ZN(n_60) + ); + NAND2_X1_LVT i_0_544( + .A1(n_60), .A2(n_0_580), .ZN(n_0_515) + ); + NAND2_X1_LVT i_0_545( + .A1(op1[31]), .A2(n_0_574), .ZN(n_0_516) + ); + OAI211_X1_LVT i_0_541( + .A(n_0_513), .B(n_0_515), .C1(n_0_545), .C2(n_0_516), .ZN(n_0_512) + ); + AOI22_X1_LVT i_0_540( + .A1(op1[30]), .A2(n_0_530), .B1(op1[28]), .B2(n_0_571), .ZN(n_0_511) + ); + OAI22_X1_LVT i_0_539( + .A1(n_0_562), .A2(n_0_511), .B1(n_0_548), .B2(n_0_529), .ZN(n_0_510) + ); + NOR3_X1_LVT i_0_538( + .A1(n_0_517), .A2(n_0_512), .A3(n_0_510), .ZN(n_0_509) + ); + OAI22_X1_LVT i_0_550( + .A1(n_0_714), .A2(n_0_617), .B1(op2[3]), .B2(n_0_608), .ZN(n_0_521) + ); + OAI22_X1_LVT i_0_549( + .A1(op2[2]), .A2(n_0_602), .B1(n_0_693), .B2(n_0_521), .ZN(n_0_520) + ); + AOI22_X1_LVT i_0_548( + .A1(op2[1]), .A2(n_0_520), .B1(n_0_728), .B2(n_0_553), .ZN(n_0_519) + ); + OAI22_X1_LVT i_0_547( + .A1(op2[0]), .A2(n_0_534), .B1(n_0_701), .B2(n_0_519), .ZN(n_0_518) + ); + OAI21_X1_LVT i_0_537( + .A(n_0_509), .B1(n_0_621), .B2(n_0_518), .ZN(result[28]) + ); + XNOR2_X1_LVT i_10_136( + .A(n_10_107), .B(n_10_108), .ZN(n_59) + ); + AOI22_X1_LVT i_0_517( + .A1(n_27), .A2(n_0_581), .B1(n_59), .B2(n_0_580), .ZN(n_0_489) + ); + INV_X1_LVT i_0_721( + .A(op1[27]), .ZN(n_0_688) + ); + OAI21_X1_LVT i_0_516( + .A(n_0_681), .B1(op2[27]), .B2(n_0_568), .ZN(n_0_488) + ); + INV_X1_LVT i_0_515( + .A(n_0_488), .ZN(n_0_487) + ); + OAI221_X1_LVT i_0_514( + .A(n_0_489), .B1(n_0_545), .B2(n_0_516), .C1(n_0_688), .C2(n_0_487), .ZN(n_0_486) + ); + OAI21_X1_LVT i_0_530( + .A(op2[1]), .B1(n_0_710), .B2(n_0_574), .ZN(n_0_502) + ); + OAI21_X1_LVT i_0_529( + .A(n_0_728), .B1(n_0_688), .B2(n_0_574), .ZN(n_0_501) + ); + NAND2_X1_LVT i_0_528( + .A1(n_0_502), .A2(n_0_501), .ZN(n_0_500) + ); + AOI21_X1_LVT i_0_527( + .A(n_0_545), .B1(n_0_701), .B2(n_0_500), .ZN(n_0_499) + ); + NAND2_X1_LVT i_0_609( + .A1(n_0_682), .A2(n_0_578), .ZN(n_0_577) + ); + NOR2_X1_LVT i_0_526( + .A1(op2[4]), .A2(n_0_693), .ZN(n_0_498) + ); + NAND2_X1_LVT i_0_525( + .A1(n_0_723), .A2(n_0_498), .ZN(n_0_497) + ); + OAI22_X1_LVT i_0_523( + .A1(n_0_688), .A2(n_0_574), .B1(n_0_691), .B2(n_0_497), .ZN(n_0_495) + ); + OAI21_X1_LVT i_0_522( + .A(n_0_502), .B1(op2[1]), .B2(n_0_495), .ZN(n_0_494) + ); + AOI21_X1_LVT i_0_521( + .A(n_0_577), .B1(n_0_701), .B2(n_0_494), .ZN(n_0_493) + ); + NOR2_X1_LVT i_0_520( + .A1(n_0_499), .A2(n_0_493), .ZN(n_0_492) + ); + AOI21_X1_LVT i_0_519( + .A(n_0_492), .B1(op2[0]), .B2(n_0_511), .ZN(n_0_491) + ); + AOI22_X1_LVT i_0_518( + .A1(n_0_688), .A2(n_0_565), .B1(op1[27]), .B2(n_0_566), .ZN(n_0_490) + ); + AOI211_X1_LVT i_0_513( + .A(n_0_486), .B(n_0_491), .C1(op2[27]), .C2(n_0_490), .ZN(n_0_485) + ); + NOR3_X1_LVT i_0_536( + .A1(op2[4]), .A2(n_0_696), .A3(n_0_723), .ZN(n_0_508) + ); + AOI21_X1_LVT i_0_535( + .A(n_0_508), .B1(n_0_723), .B2(n_0_591), .ZN(n_0_507) + ); + OAI22_X1_LVT i_0_534( + .A1(op2[2]), .A2(n_0_592), .B1(n_0_693), .B2(n_0_507), .ZN(n_0_506) + ); + NOR2_X1_LVT i_0_533( + .A1(n_0_728), .A2(n_0_506), .ZN(n_0_505) + ); + AOI21_X1_LVT i_0_532( + .A(n_0_505), .B1(n_0_728), .B2(n_0_536), .ZN(n_0_504) + ); + OAI22_X1_LVT i_0_531( + .A1(n_0_701), .A2(n_0_504), .B1(op2[0]), .B2(n_0_519), .ZN(n_0_503) + ); + OAI21_X1_LVT i_0_512( + .A(n_0_485), .B1(n_0_621), .B2(n_0_503), .ZN(result[27]) + ); + OAI21_X1_LVT i_0_500( + .A(n_0_681), .B1(op2[26]), .B2(n_0_568), .ZN(n_0_473) + ); + NAND2_X1_LVT i_0_499( + .A1(op1[26]), .A2(n_0_473), .ZN(n_0_472) + ); + XNOR2_X1_LVT i_10_133( + .A(n_10_103), .B(n_10_106), .ZN(n_58) + ); + AOI22_X1_LVT i_0_498( + .A1(n_58), .A2(n_0_580), .B1(n_26), .B2(n_0_581), .ZN(n_0_471) + ); + INV_X1_LVT i_0_744( + .A(op1[26]), .ZN(n_0_711) + ); + OAI221_X1_LVT i_0_501( + .A(op2[26]), .B1(op1[26]), .B2(n_0_564), .C1(n_0_711), .C2(n_0_567), .ZN(n_0_474) + ); + NAND3_X1_LVT i_0_497( + .A1(n_0_472), .A2(n_0_471), .A3(n_0_474), .ZN(n_0_470) + ); + INV_X1_LVT i_0_524( + .A(n_0_497), .ZN(n_0_496) + ); + AOI22_X1_LVT i_0_505( + .A1(op1[30]), .A2(n_0_496), .B1(op1[26]), .B2(n_0_573), .ZN(n_0_478) + ); + NOR2_X1_LVT i_0_504( + .A1(op2[1]), .A2(n_0_478), .ZN(n_0_477) + ); + AOI21_X1_LVT i_0_503( + .A(n_0_477), .B1(op1[28]), .B2(n_0_530), .ZN(n_0_476) + ); + NAND2_X1_LVT i_0_502( + .A1(n_0_701), .A2(n_0_476), .ZN(n_0_475) + ); + AOI21_X1_LVT i_0_489( + .A(n_0_577), .B1(op2[0]), .B2(n_0_494), .ZN(n_0_462) + ); + AOI21_X1_LVT i_0_488( + .A(n_0_470), .B1(n_0_475), .B2(n_0_462), .ZN(n_0_461) + ); + AOI21_X1_LVT i_0_511( + .A(n_0_616), .B1(n_0_738), .B2(n_0_706), .ZN(n_0_484) + ); + AOI21_X1_LVT i_0_510( + .A(n_0_484), .B1(n_0_723), .B2(op1[19]), .ZN(n_0_483) + ); + INV_X1_LVT i_0_757( + .A(op1[3]), .ZN(n_0_724) + ); + NOR2_X1_LVT i_0_687( + .A1(n_0_724), .A2(op2[3]), .ZN(n_0_654) + ); + INV_X1_LVT i_0_686( + .A(n_0_654), .ZN(n_0_653) + ); + AOI21_X1_LVT i_0_509( + .A(n_0_483), .B1(op2[4]), .B2(n_0_653), .ZN(n_0_482) + ); + AOI22_X1_LVT i_0_508( + .A1(n_0_693), .A2(n_0_554), .B1(op2[2]), .B2(n_0_482), .ZN(n_0_481) + ); + OAI22_X1_LVT i_0_507( + .A1(n_0_728), .A2(n_0_481), .B1(op2[1]), .B2(n_0_520), .ZN(n_0_480) + ); + AOI22_X1_LVT i_0_506( + .A1(op2[0]), .A2(n_0_480), .B1(n_0_701), .B2(n_0_504), .ZN(n_0_479) + ); + NAND3_X1_LVT i_0_491( + .A1(op2[0]), .A2(n_0_516), .A3(n_0_500), .ZN(n_0_464) + ); + NAND2_X1_LVT i_0_494( + .A1(op1[31]), .A2(n_0_615), .ZN(n_0_467) + ); + OAI21_X1_LVT i_0_492( + .A(n_0_467), .B1(n_0_728), .B2(n_0_516), .ZN(n_0_465) + ); + OAI21_X1_LVT i_0_490( + .A(n_0_464), .B1(n_0_475), .B2(n_0_465), .ZN(n_0_463) + ); + OAI221_X1_LVT i_0_487( + .A(n_0_461), .B1(n_0_621), .B2(n_0_479), .C1(n_0_545), .C2(n_0_463), .ZN(result[26]) + ); + INV_X1_LVT i_10_126( + .A(n_10_100), .ZN(n_10_101) + ); + NOR2_X1_LVT i_10_127( + .A1(n_10_99), .A2(n_10_101), .ZN(n_10_102) + ); + XNOR2_X1_LVT i_10_128( + .A(n_10_97), .B(n_10_102), .ZN(n_57) + ); + AOI22_X1_LVT i_0_479( + .A1(n_57), .A2(n_0_580), .B1(n_25), .B2(n_0_581), .ZN(n_0_453) + ); + INV_X1_LVT i_0_730( + .A(op2[25]), .ZN(n_0_697) + ); + AOI21_X1_LVT i_0_478( + .A(aluBypass), .B1(n_0_697), .B2(n_0_569), .ZN(n_0_452) + ); + AOI22_X1_LVT i_0_480( + .A1(op1[25]), .A2(n_0_567), .B1(n_0_699), .B2(n_0_564), .ZN(n_0_454) + ); + OAI221_X1_LVT i_0_477( + .A(n_0_453), .B1(n_0_699), .B2(n_0_452), .C1(n_0_697), .C2(n_0_454), .ZN(n_0_451) + ); + INV_X1_LVT i_0_575( + .A(n_0_545), .ZN(n_0_544) + ); + AOI21_X1_LVT i_0_476( + .A(n_0_451), .B1(n_0_544), .B2(n_0_465), .ZN(n_0_450) + ); + AOI22_X1_LVT i_0_475( + .A1(op1[29]), .A2(n_0_496), .B1(op1[25]), .B2(n_0_573), .ZN(n_0_449) + ); + NAND2_X1_LVT i_0_474( + .A1(n_0_728), .A2(n_0_449), .ZN(n_0_448) + ); + OAI21_X1_LVT i_0_473( + .A(n_0_448), .B1(n_0_728), .B2(n_0_495), .ZN(n_0_447) + ); + OAI22_X1_LVT i_0_472( + .A1(n_0_548), .A2(n_0_476), .B1(n_0_562), .B2(n_0_447), .ZN(n_0_446) + ); + INV_X1_LVT i_0_471( + .A(n_0_446), .ZN(n_0_445) + ); + OAI222_X1_LVT i_0_486( + .A1(n_0_733), .A2(n_0_617), .B1(n_0_694), .B2(n_0_605), .C1(n_0_705), .C2(n_0_615), + .ZN(n_0_460) + ); + NOR2_X1_LVT i_0_485( + .A1(n_0_693), .A2(n_0_460), .ZN(n_0_459) + ); + AOI21_X1_LVT i_0_484( + .A(n_0_459), .B1(n_0_693), .B2(n_0_538), .ZN(n_0_458) + ); + OAI22_X1_LVT i_0_483( + .A1(n_0_728), .A2(n_0_458), .B1(op2[1]), .B2(n_0_506), .ZN(n_0_457) + ); + INV_X1_LVT i_0_482( + .A(n_0_457), .ZN(n_0_456) + ); + OAI221_X1_LVT i_0_481( + .A(n_0_620), .B1(n_0_701), .B2(n_0_456), .C1(op2[0]), .C2(n_0_480), .ZN(n_0_455) + ); + NAND3_X1_LVT i_0_470( + .A1(n_0_450), .A2(n_0_445), .A3(n_0_455), .ZN(result[25]) + ); + INV_X1_LVT i_0_493( + .A(n_0_467), .ZN(n_0_466) + ); + OAI211_X1_LVT i_0_455( + .A(n_0_544), .B(n_0_465), .C1(op2[0]), .C2(n_0_466), .ZN(n_0_430) + ); + OAI21_X1_LVT i_0_462( + .A(n_0_681), .B1(op2[24]), .B2(n_0_568), .ZN(n_0_437) + ); + XNOR2_X1_LVT i_10_120( + .A(n_10_94), .B(n_10_95), .ZN(n_56) + ); + AOI222_X1_LVT i_0_461( + .A1(op1[24]), .A2(n_0_437), .B1(n_56), .B2(n_0_580), .C1(n_24), .C2(n_0_581), + .ZN(n_0_436) + ); + INV_X1_LVT i_0_460( + .A(n_0_436), .ZN(n_0_435) + ); + AOI22_X1_LVT i_0_458( + .A1(op1[24]), .A2(n_0_573), .B1(op1[28]), .B2(n_0_496), .ZN(n_0_433) + ); + OAI22_X1_LVT i_0_457( + .A1(op2[1]), .A2(n_0_433), .B1(n_0_728), .B2(n_0_478), .ZN(n_0_432) + ); + INV_X1_LVT i_0_456( + .A(n_0_432), .ZN(n_0_431) + ); + OAI22_X1_LVT i_0_454( + .A1(n_0_562), .A2(n_0_431), .B1(n_0_548), .B2(n_0_447), .ZN(n_0_429) + ); + AOI22_X1_LVT i_0_459( + .A1(n_0_736), .A2(n_0_565), .B1(op1[24]), .B2(n_0_566), .ZN(n_0_434) + ); + AOI211_X1_LVT i_0_453( + .A(n_0_435), .B(n_0_429), .C1(op2[24]), .C2(n_0_434), .ZN(n_0_428) + ); + NAND2_X1_LVT i_0_467( + .A1(n_0_693), .A2(n_0_521), .ZN(n_0_442) + ); + NOR2_X1_LVT i_0_469( + .A1(op2[3]), .A2(n_0_603), .ZN(n_0_444) + ); + AOI21_X1_LVT i_0_468( + .A(n_0_444), .B1(op1[9]), .B2(n_0_618), .ZN(n_0_443) + ); + OAI21_X1_LVT i_0_466( + .A(n_0_442), .B1(n_0_693), .B2(n_0_443), .ZN(n_0_441) + ); + NAND2_X1_LVT i_0_465( + .A1(op2[1]), .A2(n_0_441), .ZN(n_0_440) + ); + OAI21_X1_LVT i_0_464( + .A(n_0_440), .B1(op2[1]), .B2(n_0_481), .ZN(n_0_439) + ); + OAI221_X1_LVT i_0_463( + .A(n_0_620), .B1(op2[0]), .B2(n_0_456), .C1(n_0_701), .C2(n_0_439), .ZN(n_0_438) + ); + NAND3_X1_LVT i_0_452( + .A1(n_0_430), .A2(n_0_428), .A3(n_0_438), .ZN(result[24]) + ); + INV_X1_LVT i_0_751( + .A(op2[23]), .ZN(n_0_718) + ); + AOI221_X1_LVT i_0_440( + .A(n_0_718), .B1(op1[23]), .B2(n_0_566), .C1(n_0_719), .C2(n_0_565), .ZN(n_0_416) + ); + INV_X1_LVT i_10_115( + .A(n_10_91), .ZN(n_10_92) + ); + NOR2_X1_LVT i_10_116( + .A1(n_10_90), .A2(n_10_92), .ZN(n_10_93) + ); + XNOR2_X1_LVT i_10_117( + .A(n_10_88), .B(n_10_93), .ZN(n_55) + ); + AOI222_X1_LVT i_0_438( + .A1(n_23), .A2(n_0_581), .B1(n_0_544), .B2(n_0_466), .C1(n_55), .C2(n_0_580), + .ZN(n_0_414) + ); + OAI21_X1_LVT i_0_437( + .A(n_0_414), .B1(n_0_548), .B2(n_0_431), .ZN(n_0_413) + ); + OAI21_X1_LVT i_0_439( + .A(n_0_681), .B1(op2[23]), .B2(n_0_568), .ZN(n_0_415) + ); + AOI211_X1_LVT i_0_436( + .A(n_0_416), .B(n_0_413), .C1(op1[23]), .C2(n_0_415), .ZN(n_0_412) + ); + AOI22_X1_LVT i_0_444( + .A1(n_0_723), .A2(n_0_719), .B1(op2[3]), .B2(n_0_691), .ZN(n_0_420) + ); + AOI22_X1_LVT i_0_443( + .A1(n_0_575), .A2(n_0_420), .B1(op1[27]), .B2(n_0_496), .ZN(n_0_419) + ); + AOI22_X1_LVT i_0_442( + .A1(op2[1]), .A2(n_0_449), .B1(n_0_728), .B2(n_0_419), .ZN(n_0_418) + ); + INV_X1_LVT i_0_441( + .A(n_0_418), .ZN(n_0_417) + ); + NAND2_X1_LVT i_0_447( + .A1(n_0_728), .A2(n_0_458), .ZN(n_0_423) + ); + NOR2_X1_LVT i_0_451( + .A1(op2[3]), .A2(n_0_594), .ZN(n_0_427) + ); + AOI21_X1_LVT i_0_450( + .A(n_0_427), .B1(op1[8]), .B2(n_0_618), .ZN(n_0_426) + ); + OAI22_X1_LVT i_0_449( + .A1(n_0_693), .A2(n_0_426), .B1(op2[2]), .B2(n_0_507), .ZN(n_0_425) + ); + INV_X1_LVT i_0_448( + .A(n_0_425), .ZN(n_0_424) + ); + OAI21_X1_LVT i_0_446( + .A(n_0_423), .B1(n_0_728), .B2(n_0_424), .ZN(n_0_422) + ); + AOI22_X1_LVT i_0_445( + .A1(op2[0]), .A2(n_0_422), .B1(n_0_701), .B2(n_0_439), .ZN(n_0_421) + ); + OAI221_X1_LVT i_0_435( + .A(n_0_412), .B1(n_0_562), .B2(n_0_417), .C1(n_0_621), .C2(n_0_421), .ZN(result[23]) + ); + XNOR2_X1_LVT i_10_109( + .A(n_10_85), .B(n_10_86), .ZN(n_54) + ); + AOI22_X1_LVT i_0_419( + .A1(n_54), .A2(n_0_580), .B1(n_22), .B2(n_0_581), .ZN(n_0_396) + ); + INV_X1_LVT i_0_719( + .A(op2[22]), .ZN(n_0_686) + ); + AOI21_X1_LVT i_0_420( + .A(aluBypass), .B1(n_0_686), .B2(n_0_569), .ZN(n_0_397) + ); + OAI21_X1_LVT i_0_418( + .A(n_0_396), .B1(n_0_687), .B2(n_0_397), .ZN(n_0_395) + ); + AOI22_X1_LVT i_0_421( + .A1(op1[22]), .A2(n_0_566), .B1(n_0_687), .B2(n_0_565), .ZN(n_0_398) + ); + AOI21_X1_LVT i_0_417( + .A(n_0_395), .B1(op2[22]), .B2(n_0_398), .ZN(n_0_394) + ); + NAND2_X1_LVT i_0_432( + .A1(n_0_728), .A2(n_0_441), .ZN(n_0_409) + ); + AND2_X1_LVT i_0_434( + .A1(n_0_738), .A2(n_0_619), .ZN(n_0_411) + ); + AOI22_X1_LVT i_0_433( + .A1(n_0_693), .A2(n_0_482), .B1(op2[2]), .B2(n_0_411), .ZN(n_0_410) + ); + OAI21_X1_LVT i_0_431( + .A(n_0_409), .B1(n_0_728), .B2(n_0_410), .ZN(n_0_408) + ); + OAI22_X1_LVT i_0_430( + .A1(n_0_701), .A2(n_0_408), .B1(op2[0]), .B2(n_0_422), .ZN(n_0_407) + ); + AOI22_X1_LVT i_0_429( + .A1(n_0_723), .A2(n_0_687), .B1(op2[3]), .B2(n_0_717), .ZN(n_0_406) + ); + AOI22_X1_LVT i_0_428( + .A1(n_0_575), .A2(n_0_406), .B1(op1[26]), .B2(n_0_496), .ZN(n_0_405) + ); + AND2_X1_LVT i_0_427( + .A1(n_0_728), .A2(n_0_405), .ZN(n_0_404) + ); + AOI21_X1_LVT i_0_426( + .A(n_0_404), .B1(op2[1]), .B2(n_0_433), .ZN(n_0_403) + ); + INV_X1_LVT i_0_425( + .A(n_0_403), .ZN(n_0_402) + ); + OAI222_X1_LVT i_0_424( + .A1(n_0_545), .A2(n_0_467), .B1(n_0_701), .B2(n_0_417), .C1(op2[0]), .C2(n_0_402), + .ZN(n_0_401) + ); + NOR2_X1_LVT i_0_496( + .A1(n_0_738), .A2(n_0_691), .ZN(n_0_469) + ); + INV_X1_LVT i_0_495( + .A(n_0_469), .ZN(n_0_468) + ); + NAND3_X1_LVT i_0_423( + .A1(n_0_693), .A2(n_0_468), .A3(n_0_404), .ZN(n_0_400) + ); + OAI21_X1_LVT i_0_422( + .A(n_0_401), .B1(op2[0]), .B2(n_0_400), .ZN(n_0_399) + ); + OAI221_X1_LVT i_0_416( + .A(n_0_394), .B1(n_0_621), .B2(n_0_407), .C1(n_0_579), .C2(n_0_399), .ZN(result[22]) + ); + INV_X1_LVT i_0_759( + .A(op1[21]), .ZN(n_0_726) + ); + AOI22_X1_LVT i_0_399( + .A1(op1[21]), .A2(n_0_566), .B1(n_0_726), .B2(n_0_565), .ZN(n_0_377) + ); + NOR2_X1_LVT i_0_692( + .A1(n_0_726), .A2(op2[21]), .ZN(n_0_659) + ); + AOI222_X1_LVT i_0_398( + .A1(op2[21]), .A2(n_0_377), .B1(n_21), .B2(n_0_581), .C1(n_0_659), .C2(n_0_569), + .ZN(n_0_376) + ); + INV_X1_LVT i_0_397( + .A(n_0_376), .ZN(n_0_375) + ); + INV_X1_LVT i_10_104( + .A(n_10_82), .ZN(n_10_83) + ); + NOR2_X1_LVT i_10_105( + .A1(n_10_81), .A2(n_10_83), .ZN(n_10_84) + ); + XNOR2_X1_LVT i_10_106( + .A(n_10_79), .B(n_10_84), .ZN(n_53) + ); + AOI221_X1_LVT i_0_396( + .A(n_0_375), .B1(n_53), .B2(n_0_580), .C1(op1[21]), .C2(aluBypass), .ZN(n_0_374) + ); + INV_X1_LVT i_0_608( + .A(n_0_577), .ZN(n_0_576) + ); + NAND2_X1_LVT i_0_403( + .A1(op2[0]), .A2(n_0_402), .ZN(n_0_381) + ); + AND2_X1_LVT i_0_410( + .A1(op2[1]), .A2(n_0_419), .ZN(n_0_388) + ); + OAI22_X1_LVT i_0_408( + .A1(n_0_723), .A2(n_0_710), .B1(n_0_726), .B2(op2[3]), .ZN(n_0_386) + ); + AOI22_X1_LVT i_0_407( + .A1(n_0_575), .A2(n_0_386), .B1(op1[25]), .B2(n_0_496), .ZN(n_0_385) + ); + AOI21_X1_LVT i_0_395( + .A(n_0_388), .B1(n_0_728), .B2(n_0_385), .ZN(n_0_373) + ); + OAI211_X1_LVT i_0_394( + .A(n_0_576), .B(n_0_381), .C1(op2[0]), .C2(n_0_373), .ZN(n_0_372) + ); + AOI21_X1_LVT i_0_402( + .A(n_0_381), .B1(n_0_466), .B2(n_0_400), .ZN(n_0_380) + ); + INV_X1_LVT i_0_401( + .A(n_0_380), .ZN(n_0_379) + ); + NOR2_X1_LVT i_0_409( + .A1(n_0_575), .A2(n_0_467), .ZN(n_0_387) + ); + INV_X1_LVT i_0_406( + .A(n_0_385), .ZN(n_0_384) + ); + NOR2_X1_LVT i_0_405( + .A1(n_0_387), .A2(n_0_384), .ZN(n_0_383) + ); + AOI22_X1_LVT i_0_404( + .A1(n_0_467), .A2(n_0_388), .B1(n_0_728), .B2(n_0_383), .ZN(n_0_382) + ); + OAI211_X1_LVT i_0_400( + .A(n_0_544), .B(n_0_379), .C1(op2[0]), .C2(n_0_382), .ZN(n_0_378) + ); + AOI22_X1_LVT i_0_415( + .A1(op1[14]), .A2(n_0_616), .B1(op1[6]), .B2(n_0_618), .ZN(n_0_393) + ); + NOR2_X1_LVT i_0_414( + .A1(n_0_693), .A2(n_0_393), .ZN(n_0_392) + ); + AOI21_X1_LVT i_0_413( + .A(n_0_392), .B1(n_0_693), .B2(n_0_460), .ZN(n_0_391) + ); + OAI22_X1_LVT i_0_412( + .A1(n_0_728), .A2(n_0_391), .B1(op2[1]), .B2(n_0_424), .ZN(n_0_390) + ); + OAI221_X1_LVT i_0_411( + .A(n_0_620), .B1(op2[0]), .B2(n_0_408), .C1(n_0_701), .C2(n_0_390), .ZN(n_0_389) + ); + NAND4_X1_LVT i_0_393( + .A1(n_0_374), .A2(n_0_372), .A3(n_0_378), .A4(n_0_389), .ZN(result[21]) + ); + OAI221_X1_LVT i_0_388( + .A(op2[20]), .B1(n_0_727), .B2(n_0_567), .C1(op1[20]), .C2(n_0_564), .ZN(n_0_367) + ); + NOR2_X1_LVT i_0_691( + .A1(n_0_727), .A2(op2[20]), .ZN(n_0_658) + ); + AOI22_X1_LVT i_0_387( + .A1(op1[20]), .A2(aluBypass), .B1(n_0_658), .B2(n_0_569), .ZN(n_0_366) + ); + XNOR2_X1_LVT i_10_98( + .A(n_10_76), .B(n_10_77), .ZN(n_52) + ); + AOI22_X1_LVT i_0_386( + .A1(n_52), .A2(n_0_580), .B1(n_20), .B2(n_0_581), .ZN(n_0_365) + ); + AOI221_X1_LVT i_0_392( + .A(op2[4]), .B1(n_0_727), .B2(n_0_723), .C1(op2[3]), .C2(n_0_698), .ZN(n_0_371) + ); + AOI22_X1_LVT i_0_391( + .A1(op1[24]), .A2(n_0_496), .B1(n_0_693), .B2(n_0_371), .ZN(n_0_370) + ); + OAI22_X1_LVT i_0_390( + .A1(op2[1]), .A2(n_0_370), .B1(n_0_728), .B2(n_0_405), .ZN(n_0_369) + ); + OAI221_X1_LVT i_0_385( + .A(n_0_576), .B1(n_0_701), .B2(n_0_373), .C1(op2[0]), .C2(n_0_369), .ZN(n_0_364) + ); + AND4_X1_LVT i_0_384( + .A1(n_0_367), .A2(n_0_366), .A3(n_0_365), .A4(n_0_364), .ZN(n_0_363) + ); + AOI22_X1_LVT i_0_383( + .A1(op1[13]), .A2(n_0_616), .B1(op1[5]), .B2(n_0_618), .ZN(n_0_362) + ); + AOI22_X1_LVT i_0_382( + .A1(op2[2]), .A2(n_0_362), .B1(n_0_693), .B2(n_0_443), .ZN(n_0_361) + ); + NAND2_X1_LVT i_0_381( + .A1(op2[1]), .A2(n_0_361), .ZN(n_0_360) + ); + OAI21_X1_LVT i_0_380( + .A(n_0_360), .B1(op2[1]), .B2(n_0_410), .ZN(n_0_359) + ); + OAI221_X1_LVT i_0_379( + .A(n_0_620), .B1(n_0_701), .B2(n_0_359), .C1(op2[0]), .C2(n_0_390), .ZN(n_0_358) + ); + OR2_X1_LVT i_0_389( + .A1(n_0_387), .A2(n_0_369), .ZN(n_0_368) + ); + AOI22_X1_LVT i_0_378( + .A1(op2[0]), .A2(n_0_382), .B1(n_0_701), .B2(n_0_368), .ZN(n_0_357) + ); + OAI211_X1_LVT i_0_377( + .A(n_0_363), .B(n_0_358), .C1(n_0_545), .C2(n_0_357), .ZN(result[20]) + ); + OAI22_X1_LVT i_0_370( + .A1(op2[3]), .A2(n_0_689), .B1(n_0_723), .B2(n_0_688), .ZN(n_0_350) + ); + AND2_X1_LVT i_0_369( + .A1(n_0_738), .A2(n_0_350), .ZN(n_0_349) + ); + AOI22_X1_LVT i_0_368( + .A1(n_0_498), .A2(n_0_420), .B1(n_0_693), .B2(n_0_349), .ZN(n_0_348) + ); + AND2_X1_LVT i_0_367( + .A1(n_0_728), .A2(n_0_348), .ZN(n_0_347) + ); + AOI21_X1_LVT i_0_359( + .A(n_0_347), .B1(op2[1]), .B2(n_0_385), .ZN(n_0_339) + ); + OAI221_X1_LVT i_0_357( + .A(n_0_576), .B1(n_0_701), .B2(n_0_369), .C1(op2[0]), .C2(n_0_339), .ZN(n_0_337) + ); + NAND2_X1_LVT i_0_363( + .A1(n_19), .A2(n_0_581), .ZN(n_0_343) + ); + INV_X1_LVT i_0_723( + .A(op2[19]), .ZN(n_0_690) + ); + AOI221_X1_LVT i_0_364( + .A(n_0_690), .B1(n_0_689), .B2(n_0_565), .C1(op1[19]), .C2(n_0_566), .ZN(n_0_344) + ); + XNOR2_X1_LVT i_10_94( + .A(n_10_73), .B(n_10_74), .ZN(n_51) + ); + AOI221_X1_LVT i_0_361( + .A(n_0_344), .B1(op1[19]), .B2(aluBypass), .C1(n_51), .C2(n_0_580), .ZN(n_0_341) + ); + NAND3_X1_LVT i_0_362( + .A1(n_0_690), .A2(op1[19]), .A3(n_0_569), .ZN(n_0_342) + ); + NAND3_X1_LVT i_0_360( + .A1(n_0_343), .A2(n_0_341), .A3(n_0_342), .ZN(n_0_340) + ); + AOI22_X1_LVT i_0_376( + .A1(op1[12]), .A2(n_0_616), .B1(op1[4]), .B2(n_0_618), .ZN(n_0_356) + ); + OAI22_X1_LVT i_0_375( + .A1(n_0_693), .A2(n_0_356), .B1(op2[2]), .B2(n_0_426), .ZN(n_0_355) + ); + INV_X1_LVT i_0_374( + .A(n_0_355), .ZN(n_0_354) + ); + OAI22_X1_LVT i_0_373( + .A1(op2[1]), .A2(n_0_391), .B1(n_0_728), .B2(n_0_354), .ZN(n_0_353) + ); + AOI22_X1_LVT i_0_372( + .A1(n_0_701), .A2(n_0_359), .B1(op2[0]), .B2(n_0_353), .ZN(n_0_352) + ); + INV_X1_LVT i_0_371( + .A(n_0_352), .ZN(n_0_351) + ); + AOI21_X1_LVT i_0_358( + .A(n_0_340), .B1(n_0_620), .B2(n_0_351), .ZN(n_0_338) + ); + AOI22_X1_LVT i_0_366( + .A1(n_0_468), .A2(n_0_347), .B1(op2[1]), .B2(n_0_383), .ZN(n_0_346) + ); + AOI22_X1_LVT i_0_365( + .A1(n_0_701), .A2(n_0_346), .B1(op2[0]), .B2(n_0_368), .ZN(n_0_345) + ); + OAI211_X1_LVT i_0_356( + .A(n_0_337), .B(n_0_338), .C1(n_0_545), .C2(n_0_345), .ZN(result[19]) + ); + XNOR2_X1_LVT i_10_90( + .A(n_10_70), .B(n_10_71), .ZN(n_50) + ); + NAND2_X1_LVT i_0_342( + .A1(n_50), .A2(n_0_580), .ZN(n_0_323) + ); + OAI21_X1_LVT i_0_343( + .A(n_0_681), .B1(op2[18]), .B2(n_0_568), .ZN(n_0_324) + ); + AOI22_X1_LVT i_0_341( + .A1(op1[18]), .A2(n_0_324), .B1(n_18), .B2(n_0_581), .ZN(n_0_322) + ); + OAI221_X1_LVT i_0_340( + .A(op2[18]), .B1(n_0_705), .B2(n_0_567), .C1(op1[18]), .C2(n_0_564), .ZN(n_0_321) + ); + NAND3_X1_LVT i_0_339( + .A1(n_0_323), .A2(n_0_322), .A3(n_0_321), .ZN(n_0_320) + ); + OAI22_X1_LVT i_0_351( + .A1(op2[3]), .A2(n_0_705), .B1(n_0_723), .B2(n_0_711), .ZN(n_0_332) + ); + AND2_X1_LVT i_0_350( + .A1(n_0_738), .A2(n_0_332), .ZN(n_0_331) + ); + AOI22_X1_LVT i_0_349( + .A1(n_0_498), .A2(n_0_406), .B1(n_0_693), .B2(n_0_331), .ZN(n_0_330) + ); + NAND2_X1_LVT i_0_348( + .A1(n_0_728), .A2(n_0_330), .ZN(n_0_329) + ); + NAND2_X1_LVT i_0_347( + .A1(op2[1]), .A2(n_0_370), .ZN(n_0_328) + ); + AND2_X1_LVT i_0_338( + .A1(n_0_329), .A2(n_0_328), .ZN(n_0_319) + ); + OAI22_X1_LVT i_0_337( + .A1(op2[0]), .A2(n_0_319), .B1(n_0_701), .B2(n_0_339), .ZN(n_0_318) + ); + INV_X1_LVT i_0_336( + .A(n_0_318), .ZN(n_0_317) + ); + AOI21_X1_LVT i_0_335( + .A(n_0_320), .B1(n_0_578), .B2(n_0_317), .ZN(n_0_316) + ); + OAI22_X1_LVT i_0_346( + .A1(n_0_469), .A2(n_0_329), .B1(n_0_387), .B2(n_0_328), .ZN(n_0_327) + ); + NAND2_X1_LVT i_0_344( + .A1(n_0_544), .A2(n_0_346), .ZN(n_0_325) + ); + NAND2_X1_LVT i_0_354( + .A1(n_0_728), .A2(n_0_361), .ZN(n_0_335) + ); + AOI22_X1_LVT i_0_355( + .A1(n_0_612), .A2(n_0_498), .B1(n_0_693), .B2(n_0_411), .ZN(n_0_336) + ); + OAI21_X1_LVT i_0_353( + .A(n_0_335), .B1(n_0_728), .B2(n_0_336), .ZN(n_0_334) + ); + AOI22_X1_LVT i_0_352( + .A1(n_0_701), .A2(n_0_353), .B1(op2[0]), .B2(n_0_334), .ZN(n_0_333) + ); + OAI221_X1_LVT i_0_334( + .A(n_0_316), .B1(n_0_327), .B2(n_0_325), .C1(n_0_621), .C2(n_0_333), .ZN(result[18]) + ); + NAND2_X1_LVT i_0_325( + .A1(n_17), .A2(n_0_581), .ZN(n_0_307) + ); + INV_X1_LVT i_0_765( + .A(op1[17]), .ZN(n_0_732) + ); + AOI22_X1_LVT i_0_324( + .A1(n_0_732), .A2(n_0_565), .B1(op1[17]), .B2(n_0_566), .ZN(n_0_306) + ); + NOR2_X1_LVT i_0_693( + .A1(n_0_732), .A2(op2[17]), .ZN(n_0_660) + ); + XNOR2_X1_LVT i_10_86( + .A(n_10_67), .B(n_10_68), .ZN(n_49) + ); + AOI222_X1_LVT i_0_323( + .A1(op2[17]), .A2(n_0_306), .B1(n_0_660), .B2(n_0_569), .C1(n_49), .C2(n_0_580), + .ZN(n_0_305) + ); + OAI211_X1_LVT i_0_322( + .A(n_0_307), .B(n_0_305), .C1(n_0_732), .C2(n_0_681), .ZN(n_0_304) + ); + AOI22_X1_LVT i_0_331( + .A1(op2[3]), .A2(op1[25]), .B1(op1[17]), .B2(n_0_723), .ZN(n_0_313) + ); + NOR2_X1_LVT i_0_330( + .A1(op2[4]), .A2(n_0_313), .ZN(n_0_312) + ); + AOI22_X1_LVT i_0_329( + .A1(n_0_498), .A2(n_0_386), .B1(n_0_693), .B2(n_0_312), .ZN(n_0_311) + ); + OAI22_X1_LVT i_0_328( + .A1(op2[1]), .A2(n_0_311), .B1(n_0_728), .B2(n_0_348), .ZN(n_0_310) + ); + OR2_X1_LVT i_0_327( + .A1(op2[0]), .A2(n_0_310), .ZN(n_0_309) + ); + OAI21_X1_LVT i_0_321( + .A(n_0_576), .B1(n_0_701), .B2(n_0_319), .ZN(n_0_303) + ); + INV_X1_LVT i_0_320( + .A(n_0_303), .ZN(n_0_302) + ); + AOI21_X1_LVT i_0_319( + .A(n_0_304), .B1(n_0_309), .B2(n_0_302), .ZN(n_0_301) + ); + INV_X1_LVT i_0_345( + .A(n_0_327), .ZN(n_0_326) + ); + OAI22_X1_LVT i_0_326( + .A1(n_0_701), .A2(n_0_326), .B1(n_0_469), .B2(n_0_309), .ZN(n_0_308) + ); + NOR2_X1_LVT i_0_318( + .A1(op2[2]), .A2(n_0_393), .ZN(n_0_300) + ); + AOI21_X1_LVT i_0_317( + .A(n_0_300), .B1(n_0_597), .B2(n_0_498), .ZN(n_0_299) + ); + OAI22_X1_LVT i_0_316( + .A1(n_0_728), .A2(n_0_299), .B1(op2[1]), .B2(n_0_354), .ZN(n_0_298) + ); + OAI22_X1_LVT i_0_315( + .A1(op2[0]), .A2(n_0_334), .B1(n_0_701), .B2(n_0_298), .ZN(n_0_297) + ); + OAI221_X1_LVT i_0_314( + .A(n_0_301), .B1(n_0_545), .B2(n_0_308), .C1(n_0_621), .C2(n_0_297), .ZN(result[17]) + ); + XNOR2_X1_LVT i_10_82( + .A(n_10_64), .B(n_10_65), .ZN(n_48) + ); + AOI22_X1_LVT i_0_301( + .A1(n_48), .A2(n_0_580), .B1(n_16), .B2(n_0_581), .ZN(n_0_284) + ); + NAND2_X1_LVT i_0_333( + .A1(n_0_544), .A2(n_0_469), .ZN(n_0_315) + ); + INV_X1_LVT i_0_332( + .A(n_0_315), .ZN(n_0_314) + ); + OAI21_X1_LVT i_0_302( + .A(n_0_681), .B1(op2[16]), .B2(n_0_568), .ZN(n_0_285) + ); + AOI21_X1_LVT i_0_300( + .A(n_0_314), .B1(op1[16]), .B2(n_0_285), .ZN(n_0_283) + ); + INV_X1_LVT i_0_772( + .A(op1[16]), .ZN(n_0_739) + ); + OAI221_X1_LVT i_0_303( + .A(op2[16]), .B1(op1[16]), .B2(n_0_564), .C1(n_0_739), .C2(n_0_567), .ZN(n_0_286) + ); + NAND3_X1_LVT i_0_299( + .A1(n_0_284), .A2(n_0_283), .A3(n_0_286), .ZN(n_0_282) + ); + INV_X1_LVT i_0_593( + .A(n_0_562), .ZN(n_0_561) + ); + OAI22_X1_LVT i_0_307( + .A1(op1[16]), .A2(op2[3]), .B1(op1[24]), .B2(n_0_723), .ZN(n_0_290) + ); + NOR2_X1_LVT i_0_306( + .A1(op2[4]), .A2(n_0_290), .ZN(n_0_289) + ); + AOI22_X1_LVT i_0_305( + .A1(n_0_693), .A2(n_0_289), .B1(op2[2]), .B2(n_0_371), .ZN(n_0_288) + ); + OAI22_X1_LVT i_0_304( + .A1(n_0_728), .A2(n_0_330), .B1(op2[1]), .B2(n_0_288), .ZN(n_0_287) + ); + AOI221_X1_LVT i_0_298( + .A(n_0_282), .B1(n_0_547), .B2(n_0_310), .C1(n_0_561), .C2(n_0_287), .ZN(n_0_281) + ); + INV_X1_LVT i_0_762( + .A(op1[1]), .ZN(n_0_729) + ); + OAI22_X1_LVT i_0_313( + .A1(n_0_722), .A2(n_0_615), .B1(n_0_729), .B2(n_0_617), .ZN(n_0_296) + ); + NAND2_X1_LVT i_0_312( + .A1(op2[2]), .A2(n_0_296), .ZN(n_0_295) + ); + OAI21_X1_LVT i_0_311( + .A(n_0_295), .B1(op2[2]), .B2(n_0_362), .ZN(n_0_294) + ); + NAND2_X1_LVT i_0_310( + .A1(op2[1]), .A2(n_0_294), .ZN(n_0_293) + ); + OAI21_X1_LVT i_0_309( + .A(n_0_293), .B1(op2[1]), .B2(n_0_336), .ZN(n_0_292) + ); + OAI22_X1_LVT i_0_308( + .A1(op2[0]), .A2(n_0_298), .B1(n_0_701), .B2(n_0_292), .ZN(n_0_291) + ); + OAI21_X1_LVT i_0_297( + .A(n_0_281), .B1(n_0_621), .B2(n_0_291), .ZN(result[16]) + ); + OAI221_X1_LVT i_0_286( + .A(op2[15]), .B1(n_0_734), .B2(n_0_567), .C1(op1[15]), .C2(n_0_564), .ZN(n_0_270) + ); + AOI21_X1_LVT i_0_288( + .A(n_0_314), .B1(n_15), .B2(n_0_581), .ZN(n_0_272) + ); + INV_X1_LVT i_0_287( + .A(n_0_272), .ZN(n_0_271) + ); + XNOR2_X1_LVT i_10_78( + .A(n_10_61), .B(n_10_62), .ZN(n_47) + ); + OAI21_X1_LVT i_0_285( + .A(n_0_681), .B1(op2[15]), .B2(n_0_568), .ZN(n_0_269) + ); + AOI221_X1_LVT i_0_284( + .A(n_0_271), .B1(n_47), .B2(n_0_580), .C1(op1[15]), .C2(n_0_269), .ZN(n_0_268) + ); + AOI22_X1_LVT i_0_296( + .A1(op1[8]), .A2(n_0_616), .B1(op1[0]), .B2(n_0_618), .ZN(n_0_280) + ); + AOI22_X1_LVT i_0_295( + .A1(op2[2]), .A2(n_0_280), .B1(n_0_693), .B2(n_0_356), .ZN(n_0_279) + ); + NAND2_X1_LVT i_0_294( + .A1(op2[1]), .A2(n_0_279), .ZN(n_0_278) + ); + OAI21_X1_LVT i_0_293( + .A(n_0_278), .B1(op2[1]), .B2(n_0_299), .ZN(n_0_277) + ); + OAI221_X1_LVT i_0_292( + .A(n_0_620), .B1(n_0_701), .B2(n_0_277), .C1(op2[0]), .C2(n_0_292), .ZN(n_0_276) + ); + OAI222_X1_LVT i_0_291( + .A1(n_0_719), .A2(n_0_617), .B1(n_0_691), .B2(n_0_605), .C1(n_0_734), .C2(n_0_615), + .ZN(n_0_275) + ); + OAI22_X1_LVT i_0_290( + .A1(n_0_693), .A2(n_0_349), .B1(op2[2]), .B2(n_0_275), .ZN(n_0_274) + ); + OAI22_X1_LVT i_0_289( + .A1(op2[1]), .A2(n_0_274), .B1(n_0_728), .B2(n_0_311), .ZN(n_0_273) + ); + AOI22_X1_LVT i_0_283( + .A1(n_0_561), .A2(n_0_273), .B1(n_0_547), .B2(n_0_287), .ZN(n_0_267) + ); + NAND4_X1_LVT i_0_282( + .A1(n_0_270), .A2(n_0_268), .A3(n_0_276), .A4(n_0_267), .ZN(result[15]) + ); + NOR2_X1_LVT i_0_278( + .A1(op2[0]), .A2(n_0_277), .ZN(n_0_263) + ); + NAND2_X1_LVT i_0_281( + .A1(n_0_612), .A2(n_0_575), .ZN(n_0_266) + ); + OAI21_X1_LVT i_0_280( + .A(n_0_266), .B1(n_0_713), .B2(n_0_497), .ZN(n_0_265) + ); + AOI22_X1_LVT i_0_279( + .A1(op2[1]), .A2(n_0_265), .B1(n_0_728), .B2(n_0_294), .ZN(n_0_264) + ); + AOI211_X1_LVT i_0_277( + .A(n_0_263), .B(n_0_621), .C1(op2[0]), .C2(n_0_264), .ZN(n_0_262) + ); + INV_X1_LVT i_0_754( + .A(op1[14]), .ZN(n_0_721) + ); + OAI21_X1_LVT i_0_273( + .A(op2[14]), .B1(n_0_721), .B2(n_0_567), .ZN(n_0_258) + ); + AOI21_X1_LVT i_0_272( + .A(n_0_258), .B1(n_0_721), .B2(n_0_565), .ZN(n_0_257) + ); + XNOR2_X1_LVT i_10_74( + .A(n_10_58), .B(n_10_59), .ZN(n_46) + ); + OAI21_X1_LVT i_0_276( + .A(n_0_681), .B1(op2[14]), .B2(n_0_568), .ZN(n_0_261) + ); + AOI222_X1_LVT i_0_275( + .A1(n_14), .A2(n_0_581), .B1(n_46), .B2(n_0_580), .C1(op1[14]), .C2(n_0_261), + .ZN(n_0_260) + ); + INV_X1_LVT i_0_274( + .A(n_0_260), .ZN(n_0_259) + ); + OAI222_X1_LVT i_0_271( + .A1(n_0_717), .A2(n_0_605), .B1(n_0_687), .B2(n_0_617), .C1(n_0_721), .C2(n_0_615), + .ZN(n_0_256) + ); + OAI22_X1_LVT i_0_270( + .A1(n_0_693), .A2(n_0_331), .B1(op2[2]), .B2(n_0_256), .ZN(n_0_255) + ); + AND2_X1_LVT i_0_269( + .A1(n_0_728), .A2(n_0_255), .ZN(n_0_254) + ); + NOR3_X1_LVT i_0_265( + .A1(op2[3]), .A2(op2[2]), .A3(op2[0]), .ZN(n_0_250) + ); + AOI21_X1_LVT i_0_268( + .A(n_0_254), .B1(op2[1]), .B2(n_0_288), .ZN(n_0_253) + ); + OAI22_X1_LVT i_0_266( + .A1(op2[0]), .A2(n_0_253), .B1(n_0_701), .B2(n_0_273), .ZN(n_0_251) + ); + AOI221_X1_LVT i_0_259( + .A(n_0_579), .B1(n_0_254), .B2(n_0_250), .C1(n_0_315), .C2(n_0_251), .ZN(n_0_244) + ); + OR4_X1_LVT i_0_258( + .A1(n_0_262), .A2(n_0_257), .A3(n_0_259), .A4(n_0_244), .ZN(result[14]) + ); + OAI221_X1_LVT i_0_245( + .A(op2[13]), .B1(op1[13]), .B2(n_0_564), .C1(n_0_714), .C2(n_0_567), .ZN(n_0_231) + ); + NAND2_X1_LVT i_0_244( + .A1(n_13), .A2(n_0_581), .ZN(n_0_230) + ); + OAI211_X1_LVT i_0_243( + .A(n_0_231), .B(n_0_230), .C1(n_0_714), .C2(n_0_681), .ZN(n_0_229) + ); + XNOR2_X1_LVT i_10_70( + .A(n_10_55), .B(n_10_56), .ZN(n_45) + ); + NOR2_X1_LVT i_0_695( + .A1(op2[13]), .A2(n_0_714), .ZN(n_0_662) + ); + AOI221_X1_LVT i_0_242( + .A(n_0_229), .B1(n_45), .B2(n_0_580), .C1(n_0_662), .C2(n_0_569), .ZN(n_0_228) + ); + INV_X1_LVT i_0_267( + .A(n_0_253), .ZN(n_0_252) + ); + OAI222_X1_LVT i_0_257( + .A1(n_0_714), .A2(n_0_615), .B1(n_0_726), .B2(n_0_617), .C1(n_0_710), .C2(n_0_605), + .ZN(n_0_243) + ); + OAI22_X1_LVT i_0_256( + .A1(n_0_693), .A2(n_0_312), .B1(op2[2]), .B2(n_0_243), .ZN(n_0_242) + ); + NAND2_X1_LVT i_0_255( + .A1(n_0_728), .A2(n_0_242), .ZN(n_0_241) + ); + NAND2_X1_LVT i_0_254( + .A1(op2[1]), .A2(n_0_274), .ZN(n_0_240) + ); + NAND2_X1_LVT i_0_241( + .A1(n_0_241), .A2(n_0_240), .ZN(n_0_227) + ); + OAI221_X1_LVT i_0_240( + .A(n_0_228), .B1(n_0_548), .B2(n_0_252), .C1(n_0_562), .C2(n_0_227), .ZN(n_0_226) + ); + NAND2_X1_LVT i_0_249( + .A1(n_0_728), .A2(n_0_279), .ZN(n_0_235) + ); + AOI22_X1_LVT i_0_250( + .A1(n_0_597), .A2(n_0_575), .B1(op1[6]), .B2(n_0_496), .ZN(n_0_236) + ); + OAI21_X1_LVT i_0_248( + .A(n_0_235), .B1(n_0_728), .B2(n_0_236), .ZN(n_0_234) + ); + INV_X1_LVT i_0_247( + .A(n_0_234), .ZN(n_0_233) + ); + AOI221_X1_LVT i_0_246( + .A(n_0_621), .B1(op2[0]), .B2(n_0_233), .C1(n_0_701), .C2(n_0_264), .ZN(n_0_232) + ); + NAND2_X1_LVT i_0_264( + .A1(op2[3]), .A2(n_0_469), .ZN(n_0_249) + ); + AOI21_X1_LVT i_0_262( + .A(n_0_468), .B1(n_0_693), .B2(n_0_249), .ZN(n_0_247) + ); + INV_X1_LVT i_0_261( + .A(n_0_247), .ZN(n_0_246) + ); + OAI211_X1_LVT i_0_260( + .A(n_0_252), .B(n_0_246), .C1(n_0_468), .C2(n_0_254), .ZN(n_0_245) + ); + OAI221_X1_LVT i_0_253( + .A(n_0_544), .B1(n_0_247), .B2(n_0_241), .C1(n_0_469), .C2(n_0_240), .ZN(n_0_239) + ); + INV_X1_LVT i_0_252( + .A(n_0_239), .ZN(n_0_238) + ); + AOI211_X1_LVT i_0_239( + .A(n_0_226), .B(n_0_232), .C1(n_0_245), .C2(n_0_238), .ZN(n_0_225) + ); + INV_X1_LVT i_0_238( + .A(n_0_225), .ZN(result[13]) + ); + OAI221_X1_LVT i_0_232( + .A(op2[12]), .B1(n_0_696), .B2(n_0_567), .C1(op1[12]), .C2(n_0_564), .ZN(n_0_219) + ); + OAI21_X1_LVT i_0_231( + .A(n_0_681), .B1(op2[12]), .B2(n_0_568), .ZN(n_0_218) + ); + XNOR2_X1_LVT i_10_66( + .A(n_10_52), .B(n_10_53), .ZN(n_44) + ); + AOI222_X1_LVT i_0_230( + .A1(n_12), .A2(n_0_581), .B1(op1[12]), .B2(n_0_218), .C1(n_44), .C2(n_0_580), + .ZN(n_0_217) + ); + OAI21_X1_LVT i_0_234( + .A(n_0_620), .B1(op2[1]), .B2(n_0_265), .ZN(n_0_221) + ); + INV_X1_LVT i_0_763( + .A(op1[5]), .ZN(n_0_730) + ); + OAI21_X1_LVT i_0_236( + .A(op2[2]), .B1(n_0_730), .B2(n_0_615), .ZN(n_0_223) + ); + OAI21_X1_LVT i_0_235( + .A(n_0_223), .B1(op2[2]), .B2(n_0_296), .ZN(n_0_222) + ); + AOI21_X1_LVT i_0_233( + .A(n_0_221), .B1(op2[1]), .B2(n_0_222), .ZN(n_0_220) + ); + NOR2_X1_LVT i_0_237( + .A1(n_0_577), .A2(n_0_227), .ZN(n_0_224) + ); + NOR4_X1_LVT i_0_223( + .A1(n_0_701), .A2(n_0_220), .A3(n_0_224), .A4(n_0_238), .ZN(n_0_210) + ); + NAND2_X1_LVT i_0_224( + .A1(n_0_544), .A2(n_0_247), .ZN(n_0_211) + ); + NAND2_X1_LVT i_0_222( + .A1(n_0_701), .A2(n_0_211), .ZN(n_0_209) + ); + OAI22_X1_LVT i_0_229( + .A1(op2[4]), .A2(n_0_696), .B1(n_0_738), .B2(n_0_698), .ZN(n_0_216) + ); + INV_X1_LVT i_0_228( + .A(n_0_216), .ZN(n_0_215) + ); + OAI22_X1_LVT i_0_227( + .A1(n_0_727), .A2(n_0_617), .B1(op2[3]), .B2(n_0_215), .ZN(n_0_214) + ); + OAI22_X1_LVT i_0_226( + .A1(n_0_693), .A2(n_0_289), .B1(op2[2]), .B2(n_0_214), .ZN(n_0_213) + ); + OAI22_X1_LVT i_0_225( + .A1(op2[1]), .A2(n_0_213), .B1(n_0_728), .B2(n_0_255), .ZN(n_0_212) + ); + AOI221_X1_LVT i_0_221( + .A(n_0_209), .B1(n_0_578), .B2(n_0_212), .C1(n_0_620), .C2(n_0_234), .ZN(n_0_208) + ); + OAI211_X1_LVT i_0_220( + .A(n_0_219), .B(n_0_217), .C1(n_0_210), .C2(n_0_208), .ZN(result[12]) + ); + OAI21_X1_LVT i_0_209( + .A(n_0_681), .B1(op2[11]), .B2(n_0_568), .ZN(n_0_197) + ); + AOI22_X1_LVT i_0_208( + .A1(n_11), .A2(n_0_581), .B1(op1[11]), .B2(n_0_197), .ZN(n_0_196) + ); + NAND2_X1_LVT i_0_207( + .A1(n_0_211), .A2(n_0_196), .ZN(n_0_195) + ); + AOI22_X1_LVT i_0_210( + .A1(op1[11]), .A2(n_0_566), .B1(n_0_706), .B2(n_0_565), .ZN(n_0_198) + ); + XNOR2_X1_LVT i_10_62( + .A(n_10_49), .B(n_10_50), .ZN(n_43) + ); + AOI221_X1_LVT i_0_206( + .A(n_0_195), .B1(op2[11]), .B2(n_0_198), .C1(n_43), .C2(n_0_580), .ZN(n_0_194) + ); + AOI221_X1_LVT i_0_215( + .A(op2[3]), .B1(n_0_738), .B2(n_0_706), .C1(op2[4]), .C2(n_0_688), .ZN(n_0_203) + ); + AOI21_X1_LVT i_0_214( + .A(n_0_203), .B1(op1[19]), .B2(n_0_618), .ZN(n_0_202) + ); + NAND2_X1_LVT i_0_213( + .A1(n_0_693), .A2(n_0_202), .ZN(n_0_201) + ); + OAI21_X1_LVT i_0_212( + .A(n_0_201), .B1(n_0_693), .B2(n_0_275), .ZN(n_0_200) + ); + OAI22_X1_LVT i_0_211( + .A1(n_0_728), .A2(n_0_242), .B1(op2[1]), .B2(n_0_200), .ZN(n_0_199) + ); + AOI22_X1_LVT i_0_205( + .A1(n_0_561), .A2(n_0_199), .B1(n_0_701), .B2(n_0_220), .ZN(n_0_193) + ); + NOR2_X1_LVT i_0_219( + .A1(op2[2]), .A2(n_0_280), .ZN(n_0_207) + ); + AOI21_X1_LVT i_0_218( + .A(n_0_207), .B1(op1[4]), .B2(n_0_496), .ZN(n_0_206) + ); + AOI22_X1_LVT i_0_217( + .A1(n_0_728), .A2(n_0_236), .B1(op2[1]), .B2(n_0_206), .ZN(n_0_205) + ); + AOI22_X1_LVT i_0_216( + .A1(n_0_578), .A2(n_0_212), .B1(n_0_620), .B2(n_0_205), .ZN(n_0_204) + ); + OAI211_X1_LVT i_0_204( + .A(n_0_194), .B(n_0_193), .C1(n_0_701), .C2(n_0_204), .ZN(result[11]) + ); + AOI22_X1_LVT i_0_194( + .A1(n_0_654), .A2(n_0_498), .B1(op1[7]), .B2(n_0_573), .ZN(n_0_183) + ); + OAI22_X1_LVT i_0_193( + .A1(n_0_728), .A2(n_0_183), .B1(op2[1]), .B2(n_0_222), .ZN(n_0_182) + ); + AOI22_X1_LVT i_0_192( + .A1(op2[0]), .A2(n_0_182), .B1(n_0_701), .B2(n_0_205), .ZN(n_0_181) + ); + NOR2_X1_LVT i_0_191( + .A1(n_0_621), .A2(n_0_181), .ZN(n_0_180) + ); + AOI22_X1_LVT i_0_190( + .A1(op1[10]), .A2(n_0_566), .B1(n_0_733), .B2(n_0_565), .ZN(n_0_179) + ); + XNOR2_X1_LVT i_10_58( + .A(n_10_46), .B(n_10_47), .ZN(n_42) + ); + AOI22_X1_LVT i_0_188( + .A1(op2[10]), .A2(n_0_179), .B1(n_42), .B2(n_0_580), .ZN(n_0_177) + ); + OAI21_X1_LVT i_0_189( + .A(n_0_681), .B1(op2[10]), .B2(n_0_568), .ZN(n_0_178) + ); + AOI22_X1_LVT i_0_187( + .A1(n_10), .A2(n_0_581), .B1(op1[10]), .B2(n_0_178), .ZN(n_0_176) + ); + NAND2_X1_LVT i_0_186( + .A1(n_0_177), .A2(n_0_176), .ZN(n_0_175) + ); + NOR2_X1_LVT i_0_203( + .A1(n_0_701), .A2(n_0_199), .ZN(n_0_192) + ); + NOR2_X1_LVT i_0_200( + .A1(n_0_693), .A2(n_0_256), .ZN(n_0_189) + ); + AOI221_X1_LVT i_0_202( + .A(n_0_596), .B1(op1[10]), .B2(n_0_616), .C1(op1[26]), .C2(n_0_606), .ZN(n_0_191) + ); + AOI21_X1_LVT i_0_199( + .A(n_0_189), .B1(n_0_693), .B2(n_0_191), .ZN(n_0_188) + ); + OR2_X1_LVT i_0_198( + .A1(op2[1]), .A2(n_0_188), .ZN(n_0_187) + ); + NAND2_X1_LVT i_0_197( + .A1(op2[1]), .A2(n_0_213), .ZN(n_0_186) + ); + NAND2_X1_LVT i_0_185( + .A1(n_0_187), .A2(n_0_186), .ZN(n_0_174) + ); + AOI211_X1_LVT i_0_184( + .A(n_0_577), .B(n_0_192), .C1(n_0_701), .C2(n_0_174), .ZN(n_0_173) + ); + INV_X1_LVT i_0_263( + .A(n_0_249), .ZN(n_0_248) + ); + OAI22_X1_LVT i_0_196( + .A1(n_0_248), .A2(n_0_187), .B1(n_0_247), .B2(n_0_186), .ZN(n_0_185) + ); + AOI221_X1_LVT i_0_195( + .A(n_0_545), .B1(n_0_246), .B2(n_0_192), .C1(n_0_701), .C2(n_0_185), .ZN(n_0_184) + ); + OR4_X1_LVT i_0_183( + .A1(n_0_180), .A2(n_0_175), .A3(n_0_173), .A4(n_0_184), .ZN(result[10]) + ); + INV_X1_LVT i_0_753( + .A(op2[9]), .ZN(n_0_720) + ); + AOI221_X1_LVT i_0_171( + .A(n_0_720), .B1(op1[9]), .B2(n_0_566), .C1(n_0_722), .C2(n_0_565), .ZN(n_0_161) + ); + XNOR2_X1_LVT i_10_54( + .A(n_10_43), .B(n_10_44), .ZN(n_41) + ); + AOI22_X1_LVT i_0_172( + .A1(n_9), .A2(n_0_581), .B1(n_41), .B2(n_0_580), .ZN(n_0_162) + ); + AOI21_X1_LVT i_0_170( + .A(aluBypass), .B1(n_0_720), .B2(n_0_569), .ZN(n_0_160) + ); + OAI21_X1_LVT i_0_169( + .A(n_0_162), .B1(n_0_722), .B2(n_0_160), .ZN(n_0_159) + ); + OAI222_X1_LVT i_0_182( + .A1(n_0_722), .A2(n_0_615), .B1(n_0_699), .B2(n_0_605), .C1(n_0_732), .C2(n_0_617), + .ZN(n_0_172) + ); + AOI22_X1_LVT i_0_181( + .A1(n_0_693), .A2(n_0_172), .B1(op2[2]), .B2(n_0_243), .ZN(n_0_171) + ); + NAND2_X1_LVT i_0_180( + .A1(n_0_728), .A2(n_0_171), .ZN(n_0_170) + ); + NAND2_X1_LVT i_0_179( + .A1(op2[1]), .A2(n_0_200), .ZN(n_0_169) + ); + OAI22_X1_LVT i_0_178( + .A1(n_0_248), .A2(n_0_170), .B1(n_0_247), .B2(n_0_169), .ZN(n_0_168) + ); + NOR3_X1_LVT i_0_177( + .A1(n_0_545), .A2(n_0_168), .A3(n_0_185), .ZN(n_0_167) + ); + NOR2_X1_LVT i_0_251( + .A1(n_0_704), .A2(n_0_615), .ZN(n_0_237) + ); + OAI22_X1_LVT i_0_176( + .A1(op1[2]), .A2(n_0_693), .B1(n_0_496), .B2(n_0_237), .ZN(n_0_166) + ); + OAI22_X1_LVT i_0_175( + .A1(op2[1]), .A2(n_0_206), .B1(n_0_728), .B2(n_0_166), .ZN(n_0_165) + ); + OAI221_X1_LVT i_0_174( + .A(n_0_620), .B1(op2[0]), .B2(n_0_182), .C1(n_0_701), .C2(n_0_165), .ZN(n_0_164) + ); + NAND2_X1_LVT i_0_173( + .A1(n_0_170), .A2(n_0_169), .ZN(n_0_163) + ); + OAI221_X1_LVT i_0_168( + .A(n_0_164), .B1(n_0_562), .B2(n_0_163), .C1(n_0_548), .C2(n_0_174), .ZN(n_0_158) + ); + OR4_X1_LVT i_0_167( + .A1(n_0_161), .A2(n_0_159), .A3(n_0_167), .A4(n_0_158), .ZN(result[9]) + ); + OAI21_X1_LVT i_0_160( + .A(n_0_693), .B1(n_0_730), .B2(n_0_615), .ZN(n_0_151) + ); + OAI21_X1_LVT i_0_159( + .A(op2[2]), .B1(n_0_729), .B2(n_0_615), .ZN(n_0_150) + ); + AND2_X1_LVT i_0_158( + .A1(n_0_151), .A2(n_0_150), .ZN(n_0_149) + ); + NAND2_X1_LVT i_0_157( + .A1(op2[1]), .A2(n_0_149), .ZN(n_0_148) + ); + OAI21_X1_LVT i_0_156( + .A(n_0_148), .B1(op2[1]), .B2(n_0_183), .ZN(n_0_147) + ); + OAI22_X1_LVT i_0_155( + .A1(op2[0]), .A2(n_0_165), .B1(n_0_701), .B2(n_0_147), .ZN(n_0_146) + ); + NOR2_X1_LVT i_0_154( + .A1(n_0_621), .A2(n_0_146), .ZN(n_0_145) + ); + INV_X1_LVT i_0_773( + .A(op1[8]), .ZN(n_0_740) + ); + NOR2_X1_LVT i_0_688( + .A1(n_0_740), .A2(op2[8]), .ZN(n_0_655) + ); + AOI22_X1_LVT i_0_153( + .A1(op1[8]), .A2(aluBypass), .B1(n_0_655), .B2(n_0_569), .ZN(n_0_144) + ); + OAI221_X1_LVT i_0_152( + .A(op2[8]), .B1(op1[8]), .B2(n_0_564), .C1(n_0_740), .C2(n_0_567), .ZN(n_0_143) + ); + XNOR2_X1_LVT i_10_51( + .A(n_10_39), .B(n_10_42), .ZN(n_40) + ); + AOI22_X1_LVT i_0_151( + .A1(n_40), .A2(n_0_580), .B1(n_8), .B2(n_0_581), .ZN(n_0_142) + ); + NAND3_X1_LVT i_0_150( + .A1(n_0_144), .A2(n_0_143), .A3(n_0_142), .ZN(n_0_141) + ); + OAI222_X1_LVT i_0_166( + .A1(n_0_740), .A2(n_0_615), .B1(n_0_739), .B2(n_0_617), .C1(n_0_736), .C2(n_0_605), + .ZN(n_0_157) + ); + OAI22_X1_LVT i_0_165( + .A1(op2[2]), .A2(n_0_157), .B1(n_0_693), .B2(n_0_214), .ZN(n_0_156) + ); + NOR2_X1_LVT i_0_164( + .A1(op2[1]), .A2(n_0_156), .ZN(n_0_155) + ); + AOI21_X1_LVT i_0_163( + .A(n_0_155), .B1(op2[1]), .B2(n_0_188), .ZN(n_0_154) + ); + AND2_X1_LVT i_0_162( + .A1(n_0_701), .A2(n_0_154), .ZN(n_0_153) + ); + AOI211_X1_LVT i_0_149( + .A(n_0_577), .B(n_0_153), .C1(op2[0]), .C2(n_0_163), .ZN(n_0_140) + ); + AOI221_X1_LVT i_0_161( + .A(n_0_545), .B1(op2[0]), .B2(n_0_168), .C1(n_0_249), .C2(n_0_153), .ZN(n_0_152) + ); + OR4_X1_LVT i_0_148( + .A1(n_0_145), .A2(n_0_141), .A3(n_0_140), .A4(n_0_152), .ZN(result[8]) + ); + AOI22_X1_LVT i_0_138( + .A1(op1[4]), .A2(n_0_573), .B1(op1[0]), .B2(n_0_496), .ZN(n_0_130) + ); + AOI22_X1_LVT i_0_137( + .A1(op2[1]), .A2(n_0_130), .B1(n_0_728), .B2(n_0_166), .ZN(n_0_129) + ); + OAI22_X1_LVT i_0_136( + .A1(n_0_701), .A2(n_0_129), .B1(op2[0]), .B2(n_0_147), .ZN(n_0_128) + ); + NOR2_X1_LVT i_0_135( + .A1(n_0_621), .A2(n_0_128), .ZN(n_0_127) + ); + OAI221_X1_LVT i_0_139( + .A(op2[7]), .B1(n_0_713), .B2(n_0_567), .C1(op1[7]), .C2(n_0_564), .ZN(n_0_131) + ); + INV_X1_LVT i_10_44( + .A(n_10_36), .ZN(n_10_37) + ); + NOR2_X1_LVT i_10_45( + .A1(n_10_35), .A2(n_10_37), .ZN(n_10_38) + ); + XNOR2_X1_LVT i_10_46( + .A(n_10_33), .B(n_10_38), .ZN(n_39) + ); + AOI22_X1_LVT i_0_141( + .A1(n_7), .A2(n_0_581), .B1(n_39), .B2(n_0_580), .ZN(n_0_133) + ); + INV_X1_LVT i_0_745( + .A(op2[7]), .ZN(n_0_712) + ); + AOI21_X1_LVT i_0_140( + .A(aluBypass), .B1(n_0_712), .B2(n_0_569), .ZN(n_0_132) + ); + OAI211_X1_LVT i_0_133( + .A(n_0_131), .B(n_0_133), .C1(n_0_713), .C2(n_0_132), .ZN(n_0_125) + ); + OAI22_X1_LVT i_0_147( + .A1(n_0_734), .A2(n_0_617), .B1(n_0_713), .B2(n_0_615), .ZN(n_0_139) + ); + AOI211_X1_LVT i_0_146( + .A(n_0_139), .B(n_0_248), .C1(op1[23]), .C2(n_0_606), .ZN(n_0_138) + ); + OAI22_X1_LVT i_0_145( + .A1(n_0_693), .A2(n_0_202), .B1(op2[2]), .B2(n_0_138), .ZN(n_0_137) + ); + NOR2_X1_LVT i_0_144( + .A1(op2[1]), .A2(n_0_137), .ZN(n_0_136) + ); + AOI21_X1_LVT i_0_143( + .A(n_0_136), .B1(op2[1]), .B2(n_0_171), .ZN(n_0_135) + ); + NAND2_X1_LVT i_0_142( + .A1(n_0_561), .A2(n_0_135), .ZN(n_0_134) + ); + OAI221_X1_LVT i_0_134( + .A(n_0_134), .B1(n_0_548), .B2(n_0_154), .C1(n_0_545), .C2(n_0_249), .ZN(n_0_126) + ); + OR3_X1_LVT i_0_132( + .A1(n_0_127), .A2(n_0_125), .A3(n_0_126), .ZN(result[7]) + ); + NAND2_X1_LVT i_0_124( + .A1(n_0_728), .A2(n_0_149), .ZN(n_0_117) + ); + OAI21_X1_LVT i_0_123( + .A(n_0_117), .B1(n_0_724), .B2(n_0_531), .ZN(n_0_116) + ); + OAI22_X1_LVT i_0_122( + .A1(n_0_701), .A2(n_0_116), .B1(op2[0]), .B2(n_0_129), .ZN(n_0_115) + ); + NOR2_X1_LVT i_0_121( + .A1(n_0_621), .A2(n_0_115), .ZN(n_0_114) + ); + XNOR2_X1_LVT i_10_38( + .A(n_10_30), .B(n_10_31), .ZN(n_38) + ); + AOI22_X1_LVT i_0_119( + .A1(n_6), .A2(n_0_581), .B1(n_38), .B2(n_0_580), .ZN(n_0_112) + ); + INV_X1_LVT i_0_735( + .A(op2[6]), .ZN(n_0_702) + ); + AOI21_X1_LVT i_0_120( + .A(aluBypass), .B1(n_0_702), .B2(n_0_569), .ZN(n_0_113) + ); + OAI21_X1_LVT i_0_118( + .A(n_0_112), .B1(n_0_704), .B2(n_0_113), .ZN(n_0_111) + ); + AOI221_X1_LVT i_0_117( + .A(n_0_702), .B1(n_0_704), .B2(n_0_565), .C1(op1[6]), .C2(n_0_566), .ZN(n_0_110) + ); + NOR3_X1_LVT i_0_116( + .A1(n_0_114), .A2(n_0_111), .A3(n_0_110), .ZN(n_0_109) + ); + AOI221_X1_LVT i_0_131( + .A(n_0_237), .B1(op1[14]), .B2(n_0_618), .C1(op2[4]), .C2(n_0_406), .ZN(n_0_124) + ); + NAND2_X1_LVT i_0_130( + .A1(n_0_693), .A2(n_0_124), .ZN(n_0_123) + ); + INV_X1_LVT i_0_201( + .A(n_0_191), .ZN(n_0_190) + ); + OAI21_X1_LVT i_0_129( + .A(n_0_123), .B1(n_0_693), .B2(n_0_190), .ZN(n_0_122) + ); + AOI22_X1_LVT i_0_128( + .A1(n_0_728), .A2(n_0_122), .B1(op2[1]), .B2(n_0_156), .ZN(n_0_121) + ); + INV_X1_LVT i_0_127( + .A(n_0_121), .ZN(n_0_120) + ); + OAI21_X1_LVT i_0_126( + .A(n_0_248), .B1(op2[1]), .B2(n_0_123), .ZN(n_0_119) + ); + AND2_X1_LVT i_0_125( + .A1(n_0_120), .A2(n_0_119), .ZN(n_0_118) + ); + NOR2_X1_LVT i_0_115( + .A1(n_0_545), .A2(n_0_118), .ZN(n_0_108) + ); + AOI21_X1_LVT i_0_114( + .A(n_0_108), .B1(n_0_576), .B2(n_0_121), .ZN(n_0_107) + ); + AOI22_X1_LVT i_0_113( + .A1(n_0_544), .A2(n_0_248), .B1(n_0_578), .B2(n_0_135), .ZN(n_0_106) + ); + OAI221_X1_LVT i_0_112( + .A(n_0_109), .B1(op2[0]), .B2(n_0_107), .C1(n_0_701), .C2(n_0_106), .ZN(result[6]) + ); + OAI221_X1_LVT i_0_100( + .A(op2[5]), .B1(op1[5]), .B2(n_0_564), .C1(n_0_730), .C2(n_0_567), .ZN(n_0_94) + ); + INV_X1_LVT i_0_764( + .A(op2[5]), .ZN(n_0_731) + ); + AOI21_X1_LVT i_0_99( + .A(aluBypass), .B1(n_0_731), .B2(n_0_569), .ZN(n_0_93) + ); + NOR2_X1_LVT i_0_98( + .A1(n_0_730), .A2(n_0_93), .ZN(n_0_92) + ); + XNOR2_X1_LVT i_10_35( + .A(n_10_26), .B(n_10_29), .ZN(n_37) + ); + AOI221_X1_LVT i_0_97( + .A(n_0_92), .B1(n_37), .B2(n_0_580), .C1(n_5), .C2(n_0_581), .ZN(n_0_91) + ); + OAI22_X1_LVT i_0_102( + .A1(n_0_694), .A2(n_0_531), .B1(op2[1]), .B2(n_0_130), .ZN(n_0_96) + ); + OAI221_X1_LVT i_0_101( + .A(n_0_620), .B1(n_0_701), .B2(n_0_96), .C1(op2[0]), .C2(n_0_116), .ZN(n_0_95) + ); + NAND3_X1_LVT i_0_111( + .A1(n_0_544), .A2(n_0_248), .A3(op2[2]), .ZN(n_0_105) + ); + NAND2_X1_LVT i_0_110( + .A1(op2[4]), .A2(n_0_386), .ZN(n_0_104) + ); + OAI21_X1_LVT i_0_109( + .A(n_0_104), .B1(n_0_714), .B2(n_0_617), .ZN(n_0_103) + ); + OAI22_X1_LVT i_0_108( + .A1(n_0_151), .A2(n_0_103), .B1(n_0_693), .B2(n_0_172), .ZN(n_0_102) + ); + NOR2_X1_LVT i_0_107( + .A1(op2[1]), .A2(n_0_102), .ZN(n_0_101) + ); + AOI21_X1_LVT i_0_106( + .A(n_0_101), .B1(op2[1]), .B2(n_0_137), .ZN(n_0_100) + ); + OAI21_X1_LVT i_0_105( + .A(n_0_105), .B1(n_0_579), .B2(n_0_100), .ZN(n_0_99) + ); + AOI21_X1_LVT i_0_104( + .A(n_0_118), .B1(n_0_682), .B2(n_0_120), .ZN(n_0_98) + ); + OAI22_X1_LVT i_0_103( + .A1(n_0_547), .A2(n_0_99), .B1(n_0_701), .B2(n_0_98), .ZN(n_0_97) + ); + NAND4_X1_LVT i_0_96( + .A1(n_0_94), .A2(n_0_91), .A3(n_0_95), .A4(n_0_97), .ZN(result[5]) + ); + INV_X1_LVT i_10_26( + .A(n_10_21), .ZN(n_10_22) + ); + NOR2_X1_LVT i_10_28( + .A1(n_10_22), .A2(n_10_23), .ZN(n_10_24) + ); + XNOR2_X1_LVT i_10_29( + .A(n_10_19), .B(n_10_24), .ZN(n_36) + ); + AOI222_X1_LVT i_0_89( + .A1(n_4), .A2(n_0_581), .B1(n_36), .B2(n_0_580), .C1(n_0_668), .C2(n_0_564), + .ZN(n_0_84) + ); + INV_X1_LVT i_0_770( + .A(op1[4]), .ZN(n_0_737) + ); + AOI221_X1_LVT i_0_90( + .A(aluBypass), .B1(op2[4]), .B2(n_0_567), .C1(n_0_738), .C2(n_0_569), .ZN(n_0_85) + ); + OAI21_X1_LVT i_0_88( + .A(n_0_84), .B1(n_0_737), .B2(n_0_85), .ZN(n_0_83) + ); + NOR2_X1_LVT i_0_689( + .A1(op2[4]), .A2(n_0_737), .ZN(n_0_656) + ); + AOI21_X1_LVT i_0_95( + .A(n_0_616), .B1(n_0_727), .B2(n_0_723), .ZN(n_0_90) + ); + OAI22_X1_LVT i_0_94( + .A1(n_0_723), .A2(n_0_216), .B1(n_0_656), .B2(n_0_90), .ZN(n_0_89) + ); + INV_X1_LVT i_0_93( + .A(n_0_89), .ZN(n_0_88) + ); + OAI22_X1_LVT i_0_92( + .A1(op2[2]), .A2(n_0_88), .B1(n_0_693), .B2(n_0_157), .ZN(n_0_87) + ); + OAI221_X1_LVT i_0_91( + .A(n_0_105), .B1(n_0_728), .B2(n_0_122), .C1(op2[1]), .C2(n_0_87), .ZN(n_0_86) + ); + AOI221_X1_LVT i_0_85( + .A(n_0_83), .B1(n_0_561), .B2(n_0_86), .C1(op2[0]), .C2(n_0_99), .ZN(n_0_80) + ); + AOI221_X1_LVT i_0_87( + .A(n_0_574), .B1(n_0_729), .B2(op2[1]), .C1(n_0_728), .C2(n_0_724), .ZN(n_0_82) + ); + OAI22_X1_LVT i_0_86( + .A1(op2[0]), .A2(n_0_96), .B1(n_0_701), .B2(n_0_82), .ZN(n_0_81) + ); + OAI21_X1_LVT i_0_84( + .A(n_0_80), .B1(n_0_621), .B2(n_0_81), .ZN(result[4]) + ); + AND2_X1_LVT i_0_81( + .A1(op2[1]), .A2(n_0_105), .ZN(n_0_77) + ); + NAND2_X1_LVT i_0_80( + .A1(n_0_102), .A2(n_0_77), .ZN(n_0_76) + ); + OAI221_X1_LVT i_0_83( + .A(n_0_693), .B1(n_0_654), .B2(n_0_484), .C1(n_0_738), .C2(n_0_350), .ZN(n_0_79) + ); + OAI21_X1_LVT i_0_82( + .A(n_0_79), .B1(n_0_693), .B2(n_0_138), .ZN(n_0_78) + ); + OAI21_X1_LVT i_0_79( + .A(n_0_76), .B1(op2[1]), .B2(n_0_78), .ZN(n_0_75) + ); + NOR2_X1_LVT i_0_78( + .A1(n_0_562), .A2(n_0_75), .ZN(n_0_74) + ); + NAND2_X1_LVT i_10_20( + .A1(n_10_15), .A2(n_10_16), .ZN(n_10_17) + ); + XNOR2_X1_LVT i_10_21( + .A(n_10_13), .B(n_10_17), .ZN(n_35) + ); + AOI22_X1_LVT i_0_75( + .A1(n_35), .A2(n_0_580), .B1(n_3), .B2(n_0_581), .ZN(n_0_71) + ); + OAI21_X1_LVT i_0_74( + .A(n_0_681), .B1(n_0_723), .B2(n_0_566), .ZN(n_0_70) + ); + AOI222_X1_LVT i_0_73( + .A1(n_0_654), .A2(n_0_569), .B1(n_0_663), .B2(n_0_564), .C1(op1[3]), .C2(n_0_70), + .ZN(n_0_69) + ); + INV_X1_LVT i_0_736( + .A(op1[0]), .ZN(n_0_703) + ); + OAI22_X1_LVT i_0_77( + .A1(n_0_703), .A2(n_0_531), .B1(n_0_694), .B2(n_0_572), .ZN(n_0_73) + ); + OAI22_X1_LVT i_0_76( + .A1(n_0_701), .A2(n_0_73), .B1(op2[0]), .B2(n_0_82), .ZN(n_0_72) + ); + OAI211_X1_LVT i_0_72( + .A(n_0_71), .B(n_0_69), .C1(n_0_621), .C2(n_0_72), .ZN(n_0_68) + ); + AOI211_X1_LVT i_0_71( + .A(n_0_74), .B(n_0_68), .C1(n_0_547), .C2(n_0_86), .ZN(n_0_67) + ); + INV_X1_LVT i_0_70( + .A(n_0_67), .ZN(result[3]) + ); + NAND2_X1_LVT i_0_65( + .A1(n_2), .A2(n_0_581), .ZN(n_0_62) + ); + OAI221_X1_LVT i_0_66( + .A(op2[2]), .B1(op1[2]), .B2(n_0_564), .C1(n_0_694), .C2(n_0_567), .ZN(n_0_63) + ); + AOI21_X1_LVT i_0_64( + .A(aluBypass), .B1(n_0_693), .B2(n_0_569), .ZN(n_0_61) + ); + OAI21_X1_LVT i_0_63( + .A(n_0_63), .B1(n_0_694), .B2(n_0_61), .ZN(n_0_60) + ); + INV_X1_LVT i_10_13( + .A(n_10_10), .ZN(n_10_11) + ); + NOR2_X1_LVT i_10_14( + .A1(n_10_9), .A2(n_10_11), .ZN(n_10_12) + ); + XNOR2_X1_LVT i_10_15( + .A(n_10_7), .B(n_10_12), .ZN(n_34) + ); + AOI21_X1_LVT i_0_62( + .A(n_0_60), .B1(n_34), .B2(n_0_580), .ZN(n_0_59) + ); + OAI211_X1_LVT i_0_57( + .A(n_0_62), .B(n_0_59), .C1(n_0_548), .C2(n_0_75), .ZN(n_0_54) + ); + NOR2_X1_LVT i_0_698( + .A1(n_0_729), .A2(op2[1]), .ZN(n_0_665) + ); + INV_X1_LVT i_0_697( + .A(n_0_665), .ZN(n_0_664) + ); + OAI21_X1_LVT i_0_69( + .A(op2[0]), .B1(n_0_664), .B2(n_0_574), .ZN(n_0_66) + ); + OAI21_X1_LVT i_0_68( + .A(n_0_620), .B1(op2[0]), .B2(n_0_73), .ZN(n_0_65) + ); + INV_X1_LVT i_0_67( + .A(n_0_65), .ZN(n_0_64) + ); + OAI222_X1_LVT i_0_61( + .A1(op1[10]), .A2(n_0_617), .B1(op1[2]), .B2(n_0_615), .C1(n_0_738), .C2(n_0_332), + .ZN(n_0_58) + ); + OAI22_X1_LVT i_0_60( + .A1(op2[2]), .A2(n_0_58), .B1(n_0_693), .B2(n_0_124), .ZN(n_0_57) + ); + INV_X1_LVT i_0_59( + .A(n_0_57), .ZN(n_0_56) + ); + AOI22_X1_LVT i_0_58( + .A1(n_0_728), .A2(n_0_56), .B1(n_0_87), .B2(n_0_77), .ZN(n_0_55) + ); + AOI221_X1_LVT i_0_56( + .A(n_0_54), .B1(n_0_66), .B2(n_0_64), .C1(n_0_561), .C2(n_0_55), .ZN(n_0_53) + ); + INV_X1_LVT i_0_55( + .A(n_0_53), .ZN(result[2]) + ); + NAND2_X1_LVT i_0_54( + .A1(n_0_547), .A2(n_0_55), .ZN(n_0_52) + ); + AOI221_X1_LVT i_0_47( + .A(n_0_728), .B1(n_0_729), .B2(n_0_565), .C1(op1[1]), .C2(n_0_566), .ZN(n_0_45) + ); + NOR2_X1_LVT i_0_700( + .A1(op1[0]), .A2(n_0_701), .ZN(n_0_667) + ); + AOI211_X1_LVT i_0_48( + .A(n_0_667), .B(n_0_621), .C1(n_0_729), .C2(n_0_701), .ZN(n_0_46) + ); + AOI221_X1_LVT i_0_44( + .A(n_0_45), .B1(op1[1]), .B2(aluBypass), .C1(n_0_571), .C2(n_0_46), .ZN(n_0_42) + ); + NAND2_X1_LVT i_10_6( + .A1(n_10_3), .A2(n_10_4), .ZN(n_10_5) + ); + XNOR2_X1_LVT i_10_7( + .A(n_10_5), .B(n_10_1), .ZN(n_33) + ); + AOI22_X1_LVT i_0_49( + .A1(n_33), .A2(n_0_580), .B1(n_1), .B2(n_0_581), .ZN(n_0_47) + ); + OAI21_X1_LVT i_0_46( + .A(n_0_47), .B1(n_0_664), .B2(n_0_568), .ZN(n_0_44) + ); + NAND2_X1_LVT i_0_51( + .A1(op2[1]), .A2(n_0_78), .ZN(n_0_49) + ); + OAI222_X1_LVT i_0_53( + .A1(n_0_722), .A2(n_0_617), .B1(n_0_729), .B2(n_0_615), .C1(n_0_738), .C2(n_0_313), + .ZN(n_0_51) + ); + OAI22_X1_LVT i_0_52( + .A1(n_0_223), .A2(n_0_103), .B1(op2[2]), .B2(n_0_51), .ZN(n_0_50) + ); + OAI21_X1_LVT i_0_50( + .A(n_0_49), .B1(op2[1]), .B2(n_0_50), .ZN(n_0_48) + ); + AOI21_X1_LVT i_0_45( + .A(n_0_44), .B1(n_0_561), .B2(n_0_48), .ZN(n_0_43) + ); + NAND3_X1_LVT i_0_43( + .A1(n_0_52), .A2(n_0_42), .A3(n_0_43), .ZN(result[1]) + ); + OAI222_X1_LVT i_0_11( + .A1(n_0_740), .A2(n_0_617), .B1(n_0_703), .B2(n_0_615), .C1(n_0_738), .C2(n_0_290), + .ZN(n_0_10) + ); + OAI22_X1_LVT i_0_10( + .A1(op2[2]), .A2(n_0_10), .B1(n_0_693), .B2(n_0_88), .ZN(n_0_9) + ); + OAI221_X1_LVT i_0_9( + .A(n_0_701), .B1(n_0_728), .B2(n_0_56), .C1(op2[1]), .C2(n_0_9), .ZN(n_0_8) + ); + OAI21_X1_LVT i_0_8( + .A(n_0_8), .B1(n_0_701), .B2(n_0_48), .ZN(n_0_7) + ); + NOR2_X1_LVT i_0_7( + .A1(n_0_579), .A2(n_0_7), .ZN(n_0_6) + ); + OAI221_X1_LVT i_0_3( + .A(op2[0]), .B1(op1[0]), .B2(n_0_564), .C1(n_0_703), .C2(n_0_567), .ZN(n_0_2) + ); + OAI21_X1_LVT i_10_2( + .A(n_10_1), .B1(n_10_0), .B2(op2[0]), .ZN(n_32) + ); + AOI22_X1_LVT i_0_2( + .A1(n_32), .A2(n_0_580), .B1(n_0), .B2(n_0_581), .ZN(n_0_1) + ); + NAND3_X1_LVT i_0_6( + .A1(n_0_701), .A2(n_0_571), .A3(n_0_620), .ZN(n_0_5) + ); + OAI211_X1_LVT i_0_5( + .A(n_0_681), .B(n_0_5), .C1(op2[0]), .C2(n_0_568), .ZN(n_0_4) + ); + NAND2_X1_LVT i_0_4( + .A1(op1[0]), .A2(n_0_4), .ZN(n_0_3) + ); + NAND3_X1_LVT i_0_1( + .A1(n_0_2), .A2(n_0_1), .A3(n_0_3), .ZN(n_0_0) + ); + OAI33_X1_LVT i_0_14( + .A1(n_0_692), .A2(op1[31]), .A3(n_0_683), .B1(op2[31]), .B2(n_0_691), .B3(aluOp[0]), + .ZN(n_0_13) + ); + INV_X1_LVT i_0_741( + .A(op2[29]), .ZN(n_0_708) + ); + NAND2_X1_LVT i_0_685( + .A1(op1[29]), .A2(n_0_708), .ZN(n_0_652) + ); + OAI22_X1_LVT i_0_713( + .A1(n_0_700), .A2(op1[28]), .B1(op1[29]), .B2(n_0_708), .ZN(n_0_680) + ); + NAND2_X1_LVT i_0_694( + .A1(n_0_688), .A2(op2[27]), .ZN(n_0_661) + ); + INV_X1_LVT i_0_742( + .A(op2[26]), .ZN(n_0_709) + ); + OAI22_X1_LVT i_0_712( + .A1(n_0_699), .A2(op2[25]), .B1(n_0_736), .B2(op2[24]), .ZN(n_0_679) + ); + NAND2_X1_LVT i_0_690( + .A1(n_0_727), .A2(op2[20]), .ZN(n_0_657) + ); + INV_X1_LVT i_0_740( + .A(op2[18]), .ZN(n_0_707) + ); + OAI22_X1_LVT i_0_711( + .A1(n_0_707), .A2(op1[18]), .B1(n_0_690), .B2(op1[19]), .ZN(n_0_678) + ); + OAI22_X1_LVT i_0_29( + .A1(n_0_739), .A2(op2[16]), .B1(n_0_734), .B2(op2[15]), .ZN(n_0_28) + ); + INV_X1_LVT i_0_728( + .A(op2[12]), .ZN(n_0_695) + ); + INV_X1_LVT i_0_748( + .A(op2[13]), .ZN(n_0_715) + ); + OAI22_X1_LVT i_0_704( + .A1(n_0_706), .A2(op2[11]), .B1(n_0_696), .B2(op2[12]), .ZN(n_0_671) + ); + AOI22_X1_LVT i_0_710( + .A1(n_0_740), .A2(op2[8]), .B1(n_0_713), .B2(op2[7]), .ZN(n_0_677) + ); + OAI22_X1_LVT i_0_707( + .A1(n_0_731), .A2(op1[5]), .B1(op1[6]), .B2(n_0_702), .ZN(n_0_674) + ); + OAI22_X1_LVT i_0_706( + .A1(op1[2]), .A2(n_0_693), .B1(op1[1]), .B2(n_0_728), .ZN(n_0_673) + ); + INV_X1_LVT i_0_705( + .A(n_0_673), .ZN(n_0_672) + ); + INV_X1_LVT i_0_699( + .A(n_0_667), .ZN(n_0_666) + ); + OAI21_X1_LVT i_0_42( + .A(n_0_672), .B1(n_0_666), .B2(n_0_665), .ZN(n_0_41) + ); + AOI21_X1_LVT i_0_41( + .A(n_0_654), .B1(op1[2]), .B2(n_0_693), .ZN(n_0_40) + ); + AOI211_X1_LVT i_0_40( + .A(n_0_668), .B(n_0_663), .C1(n_0_41), .C2(n_0_40), .ZN(n_0_39) + ); + AOI211_X1_LVT i_0_39( + .A(n_0_656), .B(n_0_39), .C1(n_0_731), .C2(op1[5]), .ZN(n_0_38) + ); + OAI222_X1_LVT i_0_38( + .A1(n_0_704), .A2(op2[6]), .B1(n_0_674), .B2(n_0_38), .C1(n_0_713), .C2(op2[7]), + .ZN(n_0_37) + ); + AOI221_X1_LVT i_0_37( + .A(n_0_655), .B1(op1[9]), .B2(n_0_720), .C1(n_0_677), .C2(n_0_37), .ZN(n_0_36) + ); + INV_X1_LVT i_0_768( + .A(op2[10]), .ZN(n_0_735) + ); + OAI22_X1_LVT i_0_36( + .A1(n_0_735), .A2(op1[10]), .B1(op1[9]), .B2(n_0_720), .ZN(n_0_35) + ); + OAI22_X1_LVT i_0_35( + .A1(op2[10]), .A2(n_0_733), .B1(n_0_36), .B2(n_0_35), .ZN(n_0_34) + ); + INV_X1_LVT i_0_34( + .A(n_0_34), .ZN(n_0_33) + ); + AOI21_X1_LVT i_0_33( + .A(n_0_33), .B1(n_0_706), .B2(op2[11]), .ZN(n_0_32) + ); + OAI222_X1_LVT i_0_32( + .A1(op1[12]), .A2(n_0_695), .B1(n_0_715), .B2(op1[13]), .C1(n_0_671), .C2(n_0_32), + .ZN(n_0_31) + ); + OAI221_X1_LVT i_0_31( + .A(n_0_31), .B1(n_0_721), .B2(op2[14]), .C1(op2[13]), .C2(n_0_714), .ZN(n_0_30) + ); + AOI22_X1_LVT i_0_30( + .A1(n_0_734), .A2(op2[15]), .B1(n_0_721), .B2(op2[14]), .ZN(n_0_29) + ); + AOI21_X1_LVT i_0_28( + .A(n_0_28), .B1(n_0_30), .B2(n_0_29), .ZN(n_0_27) + ); + AOI221_X1_LVT i_0_27( + .A(n_0_27), .B1(n_0_732), .B2(op2[17]), .C1(n_0_739), .C2(op2[16]), .ZN(n_0_26) + ); + AOI211_X1_LVT i_0_26( + .A(n_0_660), .B(n_0_26), .C1(n_0_707), .C2(op1[18]), .ZN(n_0_25) + ); + OAI22_X1_LVT i_0_25( + .A1(op2[19]), .A2(n_0_689), .B1(n_0_678), .B2(n_0_25), .ZN(n_0_24) + ); + AOI211_X1_LVT i_0_24( + .A(n_0_658), .B(n_0_659), .C1(n_0_657), .C2(n_0_24), .ZN(n_0_23) + ); + AOI221_X1_LVT i_0_23( + .A(n_0_23), .B1(n_0_726), .B2(op2[21]), .C1(n_0_687), .C2(op2[22]), .ZN(n_0_22) + ); + AOI221_X1_LVT i_0_22( + .A(n_0_22), .B1(op1[22]), .B2(n_0_686), .C1(op1[23]), .C2(n_0_718), .ZN(n_0_21) + ); + AOI221_X1_LVT i_0_21( + .A(n_0_21), .B1(n_0_736), .B2(op2[24]), .C1(n_0_719), .C2(op2[23]), .ZN(n_0_20) + ); + OAI222_X1_LVT i_0_20( + .A1(op1[26]), .A2(n_0_709), .B1(op1[25]), .B2(n_0_697), .C1(n_0_679), .C2(n_0_20), + .ZN(n_0_19) + ); + OAI221_X1_LVT i_0_19( + .A(n_0_19), .B1(n_0_711), .B2(op2[26]), .C1(n_0_688), .C2(op2[27]), .ZN(n_0_18) + ); + AOI22_X1_LVT i_0_18( + .A1(n_0_700), .A2(op1[28]), .B1(n_0_661), .B2(n_0_18), .ZN(n_0_17) + ); + OAI21_X1_LVT i_0_17( + .A(n_0_652), .B1(n_0_680), .B2(n_0_17), .ZN(n_0_16) + ); + INV_X1_LVT i_0_749( + .A(op2[30]), .ZN(n_0_716) + ); + OAI21_X1_LVT i_0_16( + .A(n_0_16), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_15) + ); + OAI22_X1_LVT i_0_708( + .A1(n_0_692), .A2(op1[31]), .B1(op2[31]), .B2(n_0_691), .ZN(n_0_675) + ); + AOI21_X1_LVT i_0_15( + .A(n_0_675), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_14) + ); + AOI21_X1_LVT i_0_13( + .A(n_0_13), .B1(n_0_15), .B2(n_0_14), .ZN(n_0_12) + ); + NOR4_X1_LVT i_0_12( + .A1(n_0_685), .A2(aluOp[2]), .A3(aluBypass), .A4(n_0_12), .ZN(n_0_11) + ); + OR3_X1_LVT i_0_0( + .A1(n_0_6), .A2(n_0_0), .A3(n_0_11), .ZN(result[0]) + ); + OR4_X1_LVT i_0_703( + .A1(n_0_680), .A2(n_0_673), .A3(n_0_675), .A4(n_0_678), .ZN(n_0_670) + ); + INV_X1_LVT i_0_709( + .A(n_0_677), .ZN(n_0_676) + ); + OR4_X1_LVT i_0_702( + .A1(n_0_679), .A2(n_0_674), .A3(n_0_676), .A4(n_0_671), .ZN(n_0_669) + ); + AOI22_X1_LVT i_0_663( + .A1(n_0_688), .A2(op2[27]), .B1(op1[22]), .B2(n_0_686), .ZN(n_0_630) + ); + OAI22_X1_LVT i_0_662( + .A1(n_0_694), .A2(op2[2]), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_629) + ); + AOI221_X1_LVT i_0_661( + .A(n_0_629), .B1(n_0_711), .B2(op2[26]), .C1(n_0_721), .C2(op2[14]), .ZN(n_0_628) + ); + AOI21_X1_LVT i_0_664( + .A(n_0_660), .B1(n_0_690), .B2(op1[19]), .ZN(n_0_631) + ); + OAI222_X1_LVT i_0_660( + .A1(op1[12]), .A2(n_0_695), .B1(n_0_688), .B2(op2[27]), .C1(op1[22]), .C2(n_0_686), + .ZN(n_0_627) + ); + AOI21_X1_LVT i_0_659( + .A(n_0_663), .B1(n_0_734), .B2(op2[15]), .ZN(n_0_626) + ); + OAI211_X1_LVT i_0_658( + .A(n_0_666), .B(n_0_626), .C1(n_0_715), .C2(op1[13]), .ZN(n_0_625) + ); + AOI211_X1_LVT i_0_657( + .A(n_0_627), .B(n_0_625), .C1(op1[23]), .C2(n_0_718), .ZN(n_0_624) + ); + NAND4_X1_LVT i_0_656( + .A1(n_0_630), .A2(n_0_628), .A3(n_0_631), .A4(n_0_624), .ZN(n_0_623) + ); + OAI22_X1_LVT i_0_684( + .A1(n_0_721), .A2(op2[14]), .B1(n_0_722), .B2(op2[9]), .ZN(n_0_651) + ); + AOI211_X1_LVT i_0_668( + .A(n_0_651), .B(n_0_654), .C1(n_0_719), .C2(op2[23]), .ZN(n_0_635) + ); + NAND2_X1_LVT i_0_667( + .A1(n_0_664), .A2(n_0_657), .ZN(n_0_634) + ); + NOR3_X1_LVT i_0_666( + .A1(n_0_659), .A2(n_0_656), .A3(n_0_634), .ZN(n_0_633) + ); + AOI21_X1_LVT i_0_671( + .A(n_0_655), .B1(n_0_739), .B2(op2[16]), .ZN(n_0_638) + ); + AOI21_X1_LVT i_0_670( + .A(n_0_668), .B1(n_0_736), .B2(op2[24]), .ZN(n_0_637) + ); + OAI22_X1_LVT i_0_673( + .A1(n_0_735), .A2(op1[10]), .B1(n_0_734), .B2(op2[15]), .ZN(n_0_640) + ); + AOI221_X1_LVT i_0_672( + .A(n_0_640), .B1(n_0_732), .B2(op2[17]), .C1(n_0_731), .C2(op1[5]), .ZN(n_0_639) + ); + AND3_X1_LVT i_0_669( + .A1(n_0_638), .A2(n_0_637), .A3(n_0_639), .ZN(n_0_636) + ); + OAI22_X1_LVT i_0_682( + .A1(n_0_703), .A2(op2[0]), .B1(n_0_704), .B2(op2[6]), .ZN(n_0_649) + ); + OAI22_X1_LVT i_0_681( + .A1(op2[28]), .A2(n_0_698), .B1(op1[25]), .B2(n_0_697), .ZN(n_0_648) + ); + AOI21_X1_LVT i_0_678( + .A(n_0_658), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_645) + ); + AOI21_X1_LVT i_0_677( + .A(n_0_662), .B1(n_0_735), .B2(op1[10]), .ZN(n_0_644) + ); + INV_X1_LVT i_0_758( + .A(op2[21]), .ZN(n_0_725) + ); + OAI22_X1_LVT i_0_683( + .A1(op1[21]), .A2(n_0_725), .B1(n_0_739), .B2(op2[16]), .ZN(n_0_650) + ); + AOI221_X1_LVT i_0_676( + .A(n_0_650), .B1(n_0_722), .B2(op2[9]), .C1(op1[7]), .C2(n_0_712), .ZN(n_0_643) + ); + OAI21_X1_LVT i_0_680( + .A(n_0_652), .B1(n_0_711), .B2(op2[26]), .ZN(n_0_647) + ); + AOI221_X1_LVT i_0_679( + .A(n_0_647), .B1(n_0_706), .B2(op2[11]), .C1(n_0_707), .C2(op1[18]), .ZN(n_0_646) + ); + NAND4_X1_LVT i_0_675( + .A1(n_0_645), .A2(n_0_644), .A3(n_0_643), .A4(n_0_646), .ZN(n_0_642) + ); + NOR3_X1_LVT i_0_674( + .A1(n_0_649), .A2(n_0_648), .A3(n_0_642), .ZN(n_0_641) + ); + NAND4_X1_LVT i_0_665( + .A1(n_0_635), .A2(n_0_633), .A3(n_0_636), .A4(n_0_641), .ZN(n_0_632) + ); + NOR4_X1_LVT i_0_655( + .A1(n_0_670), .A2(n_0_669), .A3(n_0_623), .A4(n_0_632), .ZN(eqFlag) + ); +endmodule + +module decoder(CurrentPC, JumpOrBranchPC, JumpOrBranch, DAddr, WData, RData, Instruction, + WrMem, DWidth, Rs1, Rs2, Rd, RRs1, RRs2, WRd, WrReg, Illegal); + input [31:0] CurrentPC, RData, Instruction, RRs1, RRs2; + output [31:0] JumpOrBranchPC, DAddr, WData, WRd; + output [4:0] Rs1, Rs2, Rd; + output [1:0] DWidth; + output JumpOrBranch, WrMem, WrReg, Illegal; + + wire [31:0] op1, op2; + wire [2:0] aluOp; + wire eqFlag, n_5_0, n_5_1, n_5_2, n_5_3, n_5_4, n_5_5, n_5_6, n_5_7, n_5_8, + n_5_9, n_5_10, n_5_11, n_5_12, n_5_13, n_5_14, n_5_15, n_5_16, n_5_17, + n_5_18, n_5_19, n_5_20, n_5_21, n_5_22, n_5_23, n_5_24, n_5_25, n_5_26, + n_5_27, n_5_28, n_5_29, n_5_30, n_5_31, n_5_32, n_5_33, n_17_0, n_17_1, + n_17_2, n_17_3, n_17_4, n_17_5, n_17_6, n_17_7, n_17_8, n_17_9, n_17_10, + n_17_11, n_17_12, n_17_13, n_17_14, n_17_15, n_17_16, n_17_17, n_17_18, + n_17_19, n_17_20, n_17_21, n_17_22, n_17_23, n_17_24, n_17_25, n_17_26, + n_17_27, n_17_28, n_17_29, n_17_30, n_17_31, n_17_32, n_18_0, n_18_1, + n_18_2, n_18_3, n_18_4, n_18_5, n_18_6, n_18_7, n_18_8, n_18_9, n_18_10, + n_18_11, n_18_12, n_18_13, n_18_14, n_18_15, n_18_16, n_18_17, n_18_18, + n_18_19, n_18_20, n_18_21, n_18_22, n_18_23, n_18_24, n_18_25, n_18_26, + n_18_27, n_18_28, n_18_29, n_18_30, n_18_31, n_18_32, n_0_15, n_0_2, + n_0_16, n_0_3, n_0_17, n_0_4, n_0_18, n_0_5, n_0_19, n_0_6, n_0_20, + n_0_7, n_0_21, n_0_8, n_0_22, n_0_9, n_0_23, n_0_10, n_0_24, n_0_11, + n_0_25, n_0_12, n_0_26, n_0_13, n_0_27, n_0_14, n_0_28, n_0_29, n_0_30, + n_0_31, n_0_32, n_0_33, n_0_34, n_0_35, n_0_36, n_0_37, n_0_38, n_0_39, + n_0_40, n_0_41, n_0_42, n_0_43, n_0_44, n_0_45, n_0_46, n_0_47, n_0_48, + n_0_49, n_0_50, n_0_51, n_0_52, n_0_53, n_0_54, n_0_55, n_0_56, n_0_57, + n_0_58, n_0_59, n_0_60, n_0_61, n_0_62, n_0_63, n_0_64, n_0_65, n_0_66, + n_0_67, n_0_68, n_0_69, n_0_70, n_0_71, n_0_72, n_0_73, n_0_74, n_0_75, + n_0_76, n_0_77, n_0_78, n_0_79, n_0_80, n_0_81, n_0_82, n_0_83, n_0_84, + n_0_85, n_0_86, n_0_87, n_0_88, n_0_89, n_0_90, n_0_91, n_0_92, n_0_93, + n_0_94, n_0_95, n_0_96, n_0_97, n_0_98, n_0_99, n_0_100, aluNegAr, + n_0_101, n_0_102, n_0_103, n_0_104, n_0_105, aluBypass, n_0_106, + n_0_107, n_0_108, n_0_109, n_0_110, n_0_111, n_0_112, n_0_113, n_0_114, + n_0_115, n_0_116, n_0_117, n_0_118, n_0_119, n_0_120, n_0_121, n_0_122, + n_0_123, n_0_124, n_0_125, n_0_126, n_0_127, n_0_128, n_0_129, n_0_130, + n_0_131, n_0_132, n_0_133, n_0_134, n_0_135, n_0_136, n_0_137, n_0_138, + n_0_139, n_0_140, n_0_141, n_0_142, n_0_143, n_0_144, n_0_145, n_0_146, + n_0_147, n_0_148, n_0_149, n_0_150, n_0_151, n_0_152, n_0_153, n_0_154, + n_0_155, n_0_156, n_0_157, n_0_158, n_0_159, n_0_160, n_0_161, n_0_162, + n_0_163, n_0_164, n_0_165, n_0_166, n_0_167, n_0_168, n_0_169, n_0_170, + n_0_171, n_0_172, n_0_173, n_0_174, n_0_175, n_0_176, n_0_177, n_0_178, + n_0_179, n_0_180, n_0_181, n_0_182, n_0_183, n_0_184, n_0_185, n_0_186, + n_0_187, n_0_188, n_0_189, n_0_190, n_0_191, n_0_192, n_0_193, n_0_194, + n_0_195, n_0_196, n_0_197, n_0_198, n_0_199, n_0_200, n_0_201, n_0_202, + n_0_203, n_0_204, n_0_205, n_0_206, n_0_207, n_0_208, n_0_209, n_0_210, + n_0_211, n_0_212, n_0_213, n_0_214, n_0_215, n_0_216, n_0_217, n_0_218, + n_0_219, n_0_220, n_0_221, n_0_222, n_0_223, n_0_224, n_0_225, n_0_226, + n_0_227, n_0_228, n_0_229, n_0_230, n_0_231, n_0_232, n_0_233, n_0_234, + n_0_235, n_0_236, n_0_237, n_0_238, n_0_239, n_0_240, n_0_241, n_0_242, + n_0_1, n_0_0, n_0_243, n_0_244, n_0_245, n_0_246, n_0_247, n_0_248, + n_0_249, n_63, n_64, n_65, n_66, n_67, n_68, n_69, n_70, n_71, n_72, + n_73, n_74, n_75, n_76, n_77, n_78, n_79, n_80, n_81, n_82, n_83, n_84, + n_85, n_86, n_87, n_88, n_89, n_90, n_91, n_92, n_93, n_32, n_33, n_34, + n_35, n_36, n_37, n_38, n_39, n_40, n_41, n_42, n_43, n_44, n_45, n_46, + n_47, n_48, n_49, n_50, n_51, n_52, n_53, n_54, n_55, n_56, n_57, n_58, + n_59, n_60, n_61, n_62, n_0, n_1, n_2, n_3, n_4, n_5, n_6, n_7, n_8, + n_9, n_10, n_11, n_12, n_13, n_14, n_15, n_16, n_17, n_18, n_19, n_20, + n_21, n_22, n_23, n_24, n_25, n_26, n_27, n_28, n_29, n_30, n_31; + + INV_X1_LVT i_18_1( + .A(CurrentPC[13]), .ZN(n_18_1) + ); + XNOR2_X1_LVT i_18_32( + .A(CurrentPC[31]), .B(n_18_1), .ZN(n_18_32) + ); + INV_X1_LVT i_18_0( + .A(Instruction[31]), .ZN(n_18_0) + ); + HA_X1_LVT i_18_2( + .A(Instruction[8]), .B(CurrentPC[1]), .CO(n_18_2), .S(n_63) + ); + FA_X1_LVT i_18_3( + .A(Instruction[9]), .B(CurrentPC[2]), .CI(n_18_2), .CO(n_18_3), .S(n_64) + ); + FA_X1_LVT i_18_4( + .A(Instruction[10]), .B(CurrentPC[3]), .CI(n_18_3), .CO(n_18_4), .S(n_65) + ); + FA_X1_LVT i_18_5( + .A(Instruction[11]), .B(CurrentPC[4]), .CI(n_18_4), .CO(n_18_5), .S(n_66) + ); + FA_X1_LVT i_18_6( + .A(Instruction[25]), .B(CurrentPC[5]), .CI(n_18_5), .CO(n_18_6), .S(n_67) + ); + FA_X1_LVT i_18_7( + .A(Instruction[26]), .B(CurrentPC[6]), .CI(n_18_6), .CO(n_18_7), .S(n_68) + ); + FA_X1_LVT i_18_8( + .A(Instruction[27]), .B(CurrentPC[7]), .CI(n_18_7), .CO(n_18_8), .S(n_69) + ); + FA_X1_LVT i_18_9( + .A(Instruction[28]), .B(CurrentPC[8]), .CI(n_18_8), .CO(n_18_9), .S(n_70) + ); + FA_X1_LVT i_18_10( + .A(Instruction[29]), .B(CurrentPC[9]), .CI(n_18_9), .CO(n_18_10), .S(n_71) + ); + FA_X1_LVT i_18_11( + .A(Instruction[30]), .B(CurrentPC[10]), .CI(n_18_10), .CO(n_18_11), .S(n_72) + ); + FA_X1_LVT i_18_12( + .A(Instruction[7]), .B(CurrentPC[11]), .CI(n_18_11), .CO(n_18_12), .S(n_73) + ); + FA_X1_LVT i_18_13( + .A(CurrentPC[12]), .B(Instruction[31]), .CI(n_18_12), .CO(n_18_13), .S(n_74) + ); + FA_X1_LVT i_18_14( + .A(n_18_0), .B(n_18_1), .CI(n_18_13), .CO(n_18_14), .S(n_75) + ); + FA_X1_LVT i_18_15( + .A(CurrentPC[14]), .B(n_18_1), .CI(n_18_14), .CO(n_18_15), .S(n_76) + ); + FA_X1_LVT i_18_16( + .A(CurrentPC[15]), .B(n_18_1), .CI(n_18_15), .CO(n_18_16), .S(n_77) + ); + FA_X1_LVT i_18_17( + .A(CurrentPC[16]), .B(n_18_1), .CI(n_18_16), .CO(n_18_17), .S(n_78) + ); + FA_X1_LVT i_18_18( + .A(CurrentPC[17]), .B(n_18_1), .CI(n_18_17), .CO(n_18_18), .S(n_79) + ); + FA_X1_LVT i_18_19( + .A(CurrentPC[18]), .B(n_18_1), .CI(n_18_18), .CO(n_18_19), .S(n_80) + ); + FA_X1_LVT i_18_20( + .A(CurrentPC[19]), .B(n_18_1), .CI(n_18_19), .CO(n_18_20), .S(n_81) + ); + FA_X1_LVT i_18_21( + .A(CurrentPC[20]), .B(n_18_1), .CI(n_18_20), .CO(n_18_21), .S(n_82) + ); + FA_X1_LVT i_18_22( + .A(CurrentPC[21]), .B(n_18_1), .CI(n_18_21), .CO(n_18_22), .S(n_83) + ); + FA_X1_LVT i_18_23( + .A(CurrentPC[22]), .B(n_18_1), .CI(n_18_22), .CO(n_18_23), .S(n_84) + ); + FA_X1_LVT i_18_24( + .A(CurrentPC[23]), .B(n_18_1), .CI(n_18_23), .CO(n_18_24), .S(n_85) + ); + FA_X1_LVT i_18_25( + .A(CurrentPC[24]), .B(n_18_1), .CI(n_18_24), .CO(n_18_25), .S(n_86) + ); + FA_X1_LVT i_18_26( + .A(CurrentPC[25]), .B(n_18_1), .CI(n_18_25), .CO(n_18_26), .S(n_87) + ); + FA_X1_LVT i_18_27( + .A(CurrentPC[26]), .B(n_18_1), .CI(n_18_26), .CO(n_18_27), .S(n_88) + ); + FA_X1_LVT i_18_28( + .A(CurrentPC[27]), .B(n_18_1), .CI(n_18_27), .CO(n_18_28), .S(n_89) + ); + FA_X1_LVT i_18_29( + .A(CurrentPC[28]), .B(n_18_1), .CI(n_18_28), .CO(n_18_29), .S(n_90) + ); + FA_X1_LVT i_18_30( + .A(CurrentPC[29]), .B(n_18_1), .CI(n_18_29), .CO(n_18_30), .S(n_91) + ); + FA_X1_LVT i_18_31( + .A(CurrentPC[30]), .B(n_18_1), .CI(n_18_30), .CO(n_18_31), .S(n_92) + ); + XNOR2_X1_LVT i_18_33( + .A(n_18_32), .B(n_18_31), .ZN(n_93) + ); + INV_X1_LVT i_0_350( + .A(Instruction[3]), .ZN(n_0_243) + ); + NAND3_X1_LVT i_0_343( + .A1(n_0_243), .A2(Instruction[0]), .A3(Instruction[1]), .ZN(n_0_238) + ); + OR2_X1_LVT i_0_332( + .A1(n_0_238), .A2(Instruction[2]), .ZN(n_0_228) + ); + INV_X1_LVT i_0_351( + .A(Instruction[5]), .ZN(n_0_244) + ); + NOR2_X1_LVT i_0_340( + .A1(n_0_244), .A2(Instruction[4]), .ZN(n_0_235) + ); + NAND2_X1_LVT i_0_329( + .A1(Instruction[6]), .A2(n_0_235), .ZN(n_0_225) + ); + INV_X1_LVT i_0_354( + .A(Instruction[13]), .ZN(n_0_247) + ); + NOR2_X1_LVT i_0_345( + .A1(n_0_247), .A2(Instruction[14]), .ZN(n_0_240) + ); + NOR3_X1_LVT i_0_118( + .A1(n_0_228), .A2(n_0_225), .A3(n_0_240), .ZN(n_0_99) + ); + NAND3_X1_LVT i_0_346( + .A1(Instruction[0]), .A2(Instruction[1]), .A3(Instruction[2]), .ZN(n_0_241) + ); + NOR2_X1_LVT i_0_328( + .A1(n_0_241), .A2(n_0_225), .ZN(n_0_224) + ); + INV_X1_LVT i_0_356( + .A(n_0_224), .ZN(n_0_249) + ); + NOR2_X1_LVT i_0_108( + .A1(n_0_243), .A2(n_0_249), .ZN(n_0_91) + ); + INV_X1_LVT i_17_1( + .A(CurrentPC[21]), .ZN(n_17_1) + ); + XNOR2_X1_LVT i_17_32( + .A(CurrentPC[31]), .B(n_17_1), .ZN(n_17_32) + ); + INV_X1_LVT i_17_0( + .A(Instruction[31]), .ZN(n_17_0) + ); + HA_X1_LVT i_17_2( + .A(Instruction[21]), .B(CurrentPC[1]), .CO(n_17_2), .S(n_32) + ); + FA_X1_LVT i_17_3( + .A(Instruction[22]), .B(CurrentPC[2]), .CI(n_17_2), .CO(n_17_3), .S(n_33) + ); + FA_X1_LVT i_17_4( + .A(Instruction[23]), .B(CurrentPC[3]), .CI(n_17_3), .CO(n_17_4), .S(n_34) + ); + FA_X1_LVT i_17_5( + .A(Instruction[24]), .B(CurrentPC[4]), .CI(n_17_4), .CO(n_17_5), .S(n_35) + ); + FA_X1_LVT i_17_6( + .A(Instruction[25]), .B(CurrentPC[5]), .CI(n_17_5), .CO(n_17_6), .S(n_36) + ); + FA_X1_LVT i_17_7( + .A(Instruction[26]), .B(CurrentPC[6]), .CI(n_17_6), .CO(n_17_7), .S(n_37) + ); + FA_X1_LVT i_17_8( + .A(Instruction[27]), .B(CurrentPC[7]), .CI(n_17_7), .CO(n_17_8), .S(n_38) + ); + FA_X1_LVT i_17_9( + .A(Instruction[28]), .B(CurrentPC[8]), .CI(n_17_8), .CO(n_17_9), .S(n_39) + ); + FA_X1_LVT i_17_10( + .A(Instruction[29]), .B(CurrentPC[9]), .CI(n_17_9), .CO(n_17_10), .S(n_40) + ); + FA_X1_LVT i_17_11( + .A(Instruction[30]), .B(CurrentPC[10]), .CI(n_17_10), .CO(n_17_11), .S(n_41) + ); + FA_X1_LVT i_17_12( + .A(Instruction[20]), .B(CurrentPC[11]), .CI(n_17_11), .CO(n_17_12), .S(n_42) + ); + FA_X1_LVT i_17_13( + .A(Instruction[12]), .B(CurrentPC[12]), .CI(n_17_12), .CO(n_17_13), .S(n_43) + ); + FA_X1_LVT i_17_14( + .A(Instruction[13]), .B(CurrentPC[13]), .CI(n_17_13), .CO(n_17_14), .S(n_44) + ); + FA_X1_LVT i_17_15( + .A(Instruction[14]), .B(CurrentPC[14]), .CI(n_17_14), .CO(n_17_15), .S(n_45) + ); + FA_X1_LVT i_17_16( + .A(Instruction[15]), .B(CurrentPC[15]), .CI(n_17_15), .CO(n_17_16), .S(n_46) + ); + FA_X1_LVT i_17_17( + .A(Instruction[16]), .B(CurrentPC[16]), .CI(n_17_16), .CO(n_17_17), .S(n_47) + ); + FA_X1_LVT i_17_18( + .A(Instruction[17]), .B(CurrentPC[17]), .CI(n_17_17), .CO(n_17_18), .S(n_48) + ); + FA_X1_LVT i_17_19( + .A(Instruction[18]), .B(CurrentPC[18]), .CI(n_17_18), .CO(n_17_19), .S(n_49) + ); + FA_X1_LVT i_17_20( + .A(Instruction[19]), .B(CurrentPC[19]), .CI(n_17_19), .CO(n_17_20), .S(n_50) + ); + FA_X1_LVT i_17_21( + .A(CurrentPC[20]), .B(Instruction[31]), .CI(n_17_20), .CO(n_17_21), .S(n_51) + ); + FA_X1_LVT i_17_22( + .A(n_17_0), .B(n_17_1), .CI(n_17_21), .CO(n_17_22), .S(n_52) + ); + FA_X1_LVT i_17_23( + .A(CurrentPC[22]), .B(n_17_1), .CI(n_17_22), .CO(n_17_23), .S(n_53) + ); + FA_X1_LVT i_17_24( + .A(CurrentPC[23]), .B(n_17_1), .CI(n_17_23), .CO(n_17_24), .S(n_54) + ); + FA_X1_LVT i_17_25( + .A(CurrentPC[24]), .B(n_17_1), .CI(n_17_24), .CO(n_17_25), .S(n_55) + ); + FA_X1_LVT i_17_26( + .A(CurrentPC[25]), .B(n_17_1), .CI(n_17_25), .CO(n_17_26), .S(n_56) + ); + FA_X1_LVT i_17_27( + .A(CurrentPC[26]), .B(n_17_1), .CI(n_17_26), .CO(n_17_27), .S(n_57) + ); + FA_X1_LVT i_17_28( + .A(CurrentPC[27]), .B(n_17_1), .CI(n_17_27), .CO(n_17_28), .S(n_58) + ); + FA_X1_LVT i_17_29( + .A(CurrentPC[28]), .B(n_17_1), .CI(n_17_28), .CO(n_17_29), .S(n_59) + ); + FA_X1_LVT i_17_30( + .A(CurrentPC[29]), .B(n_17_1), .CI(n_17_29), .CO(n_17_30), .S(n_60) + ); + FA_X1_LVT i_17_31( + .A(CurrentPC[30]), .B(n_17_1), .CI(n_17_30), .CO(n_17_31), .S(n_61) + ); + XNOR2_X1_LVT i_17_33( + .A(n_17_32), .B(n_17_31), .ZN(n_62) + ); + INV_X1_LVT i_5_1( + .A(RRs1[12]), .ZN(n_5_1) + ); + XNOR2_X1_LVT i_5_33( + .A(RRs1[31]), .B(n_5_1), .ZN(n_5_33) + ); + INV_X1_LVT i_5_0( + .A(Instruction[31]), .ZN(n_5_0) + ); + HA_X1_LVT i_5_2( + .A(Instruction[20]), .B(RRs1[0]), .CO(n_5_2), .S(n_0) + ); + FA_X1_LVT i_5_3( + .A(Instruction[21]), .B(RRs1[1]), .CI(n_5_2), .CO(n_5_3), .S(n_1) + ); + FA_X1_LVT i_5_4( + .A(Instruction[22]), .B(RRs1[2]), .CI(n_5_3), .CO(n_5_4), .S(n_2) + ); + FA_X1_LVT i_5_5( + .A(Instruction[23]), .B(RRs1[3]), .CI(n_5_4), .CO(n_5_5), .S(n_3) + ); + FA_X1_LVT i_5_6( + .A(Instruction[24]), .B(RRs1[4]), .CI(n_5_5), .CO(n_5_6), .S(n_4) + ); + FA_X1_LVT i_5_7( + .A(Instruction[25]), .B(RRs1[5]), .CI(n_5_6), .CO(n_5_7), .S(n_5) + ); + FA_X1_LVT i_5_8( + .A(Instruction[26]), .B(RRs1[6]), .CI(n_5_7), .CO(n_5_8), .S(n_6) + ); + FA_X1_LVT i_5_9( + .A(Instruction[27]), .B(RRs1[7]), .CI(n_5_8), .CO(n_5_9), .S(n_7) + ); + FA_X1_LVT i_5_10( + .A(Instruction[28]), .B(RRs1[8]), .CI(n_5_9), .CO(n_5_10), .S(n_8) + ); + FA_X1_LVT i_5_11( + .A(Instruction[29]), .B(RRs1[9]), .CI(n_5_10), .CO(n_5_11), .S(n_9) + ); + FA_X1_LVT i_5_12( + .A(Instruction[30]), .B(RRs1[10]), .CI(n_5_11), .CO(n_5_12), .S(n_10) + ); + FA_X1_LVT i_5_13( + .A(RRs1[11]), .B(Instruction[31]), .CI(n_5_12), .CO(n_5_13), .S(n_11) + ); + FA_X1_LVT i_5_14( + .A(n_5_0), .B(n_5_1), .CI(n_5_13), .CO(n_5_14), .S(n_12) + ); + FA_X1_LVT i_5_15( + .A(RRs1[13]), .B(n_5_1), .CI(n_5_14), .CO(n_5_15), .S(n_13) + ); + FA_X1_LVT i_5_16( + .A(RRs1[14]), .B(n_5_1), .CI(n_5_15), .CO(n_5_16), .S(n_14) + ); + FA_X1_LVT i_5_17( + .A(RRs1[15]), .B(n_5_1), .CI(n_5_16), .CO(n_5_17), .S(n_15) + ); + FA_X1_LVT i_5_18( + .A(RRs1[16]), .B(n_5_1), .CI(n_5_17), .CO(n_5_18), .S(n_16) + ); + FA_X1_LVT i_5_19( + .A(RRs1[17]), .B(n_5_1), .CI(n_5_18), .CO(n_5_19), .S(n_17) + ); + FA_X1_LVT i_5_20( + .A(RRs1[18]), .B(n_5_1), .CI(n_5_19), .CO(n_5_20), .S(n_18) + ); + FA_X1_LVT i_5_21( + .A(RRs1[19]), .B(n_5_1), .CI(n_5_20), .CO(n_5_21), .S(n_19) + ); + FA_X1_LVT i_5_22( + .A(RRs1[20]), .B(n_5_1), .CI(n_5_21), .CO(n_5_22), .S(n_20) + ); + FA_X1_LVT i_5_23( + .A(RRs1[21]), .B(n_5_1), .CI(n_5_22), .CO(n_5_23), .S(n_21) + ); + FA_X1_LVT i_5_24( + .A(RRs1[22]), .B(n_5_1), .CI(n_5_23), .CO(n_5_24), .S(n_22) + ); + FA_X1_LVT i_5_25( + .A(RRs1[23]), .B(n_5_1), .CI(n_5_24), .CO(n_5_25), .S(n_23) + ); + FA_X1_LVT i_5_26( + .A(RRs1[24]), .B(n_5_1), .CI(n_5_25), .CO(n_5_26), .S(n_24) + ); + FA_X1_LVT i_5_27( + .A(RRs1[25]), .B(n_5_1), .CI(n_5_26), .CO(n_5_27), .S(n_25) + ); + FA_X1_LVT i_5_28( + .A(RRs1[26]), .B(n_5_1), .CI(n_5_27), .CO(n_5_28), .S(n_26) + ); + FA_X1_LVT i_5_29( + .A(RRs1[27]), .B(n_5_1), .CI(n_5_28), .CO(n_5_29), .S(n_27) + ); + FA_X1_LVT i_5_30( + .A(RRs1[28]), .B(n_5_1), .CI(n_5_29), .CO(n_5_30), .S(n_28) + ); + FA_X1_LVT i_5_31( + .A(RRs1[29]), .B(n_5_1), .CI(n_5_30), .CO(n_5_31), .S(n_29) + ); + FA_X1_LVT i_5_32( + .A(RRs1[30]), .B(n_5_1), .CI(n_5_31), .CO(n_5_32), .S(n_30) + ); + XNOR2_X1_LVT i_5_34( + .A(n_5_33), .B(n_5_32), .ZN(n_31) + ); + NOR2_X1_LVT i_0_107( + .A1(n_0_249), .A2(Instruction[3]), .ZN(n_0_90) + ); + AOI222_X1_LVT i_0_106( + .A1(n_93), .A2(n_0_99), .B1(n_0_91), .B2(n_62), .C1(n_31), .C2(n_0_90), .ZN(n_0_89) + ); + INV_X1_LVT i_0_355( + .A(Instruction[6]), .ZN(n_0_248) + ); + NAND2_X1_LVT i_0_339( + .A1(n_0_248), .A2(Instruction[4]), .ZN(n_0_234) + ); + INV_X1_LVT i_0_338( + .A(n_0_234), .ZN(n_0_233) + ); + OAI21_X1_LVT i_0_341( + .A(Instruction[13]), .B1(Instruction[14]), .B2(Instruction[12]), .ZN(n_0_236) + ); + AOI211_X1_LVT i_0_337( + .A(n_0_235), .B(n_0_233), .C1(n_0_248), .C2(n_0_236), .ZN(n_0_232) + ); + INV_X1_LVT i_0_352( + .A(Instruction[4]), .ZN(n_0_245) + ); + NAND2_X1_LVT i_0_344( + .A1(n_0_245), .A2(Instruction[2]), .ZN(n_0_239) + ); + AOI21_X1_LVT i_0_335( + .A(Instruction[6]), .B1(n_0_243), .B2(n_0_239), .ZN(n_0_230) + ); + NOR2_X1_LVT i_0_334( + .A1(n_0_232), .A2(n_0_230), .ZN(n_0_229) + ); + NAND2_X1_LVT i_0_342( + .A1(n_0_241), .A2(n_0_238), .ZN(n_0_237) + ); + NAND2_X1_LVT i_0_336( + .A1(Instruction[6]), .A2(n_0_240), .ZN(n_0_231) + ); + OAI211_X1_LVT i_0_333( + .A(n_0_229), .B(n_0_237), .C1(Instruction[2]), .C2(n_0_231), .ZN(Illegal) + ); + NAND2_X1_LVT i_0_109( + .A1(Illegal), .A2(CurrentPC[31]), .ZN(n_0_92) + ); + NAND2_X1_LVT i_0_105( + .A1(n_0_89), .A2(n_0_92), .ZN(JumpOrBranchPC[31]) + ); + AOI222_X1_LVT i_0_103( + .A1(n_92), .A2(n_0_99), .B1(n_0_91), .B2(n_61), .C1(n_30), .C2(n_0_90), .ZN(n_0_87) + ); + NAND2_X1_LVT i_0_104( + .A1(Illegal), .A2(CurrentPC[30]), .ZN(n_0_88) + ); + NAND2_X1_LVT i_0_102( + .A1(n_0_87), .A2(n_0_88), .ZN(JumpOrBranchPC[30]) + ); + AOI222_X1_LVT i_0_100( + .A1(n_91), .A2(n_0_99), .B1(n_0_91), .B2(n_60), .C1(n_29), .C2(n_0_90), .ZN(n_0_85) + ); + NAND2_X1_LVT i_0_101( + .A1(Illegal), .A2(CurrentPC[29]), .ZN(n_0_86) + ); + NAND2_X1_LVT i_0_99( + .A1(n_0_85), .A2(n_0_86), .ZN(JumpOrBranchPC[29]) + ); + AOI222_X1_LVT i_0_97( + .A1(n_90), .A2(n_0_99), .B1(n_0_91), .B2(n_59), .C1(n_28), .C2(n_0_90), .ZN(n_0_83) + ); + NAND2_X1_LVT i_0_98( + .A1(Illegal), .A2(CurrentPC[28]), .ZN(n_0_84) + ); + NAND2_X1_LVT i_0_96( + .A1(n_0_83), .A2(n_0_84), .ZN(JumpOrBranchPC[28]) + ); + AOI222_X1_LVT i_0_94( + .A1(n_89), .A2(n_0_99), .B1(n_0_91), .B2(n_58), .C1(n_27), .C2(n_0_90), .ZN(n_0_81) + ); + NAND2_X1_LVT i_0_95( + .A1(Illegal), .A2(CurrentPC[27]), .ZN(n_0_82) + ); + NAND2_X1_LVT i_0_93( + .A1(n_0_81), .A2(n_0_82), .ZN(JumpOrBranchPC[27]) + ); + AOI222_X1_LVT i_0_91( + .A1(n_88), .A2(n_0_99), .B1(n_0_91), .B2(n_57), .C1(n_26), .C2(n_0_90), .ZN(n_0_79) + ); + NAND2_X1_LVT i_0_92( + .A1(Illegal), .A2(CurrentPC[26]), .ZN(n_0_80) + ); + NAND2_X1_LVT i_0_90( + .A1(n_0_79), .A2(n_0_80), .ZN(JumpOrBranchPC[26]) + ); + AOI222_X1_LVT i_0_88( + .A1(n_87), .A2(n_0_99), .B1(n_0_91), .B2(n_56), .C1(n_25), .C2(n_0_90), .ZN(n_0_77) + ); + NAND2_X1_LVT i_0_89( + .A1(Illegal), .A2(CurrentPC[25]), .ZN(n_0_78) + ); + NAND2_X1_LVT i_0_87( + .A1(n_0_77), .A2(n_0_78), .ZN(JumpOrBranchPC[25]) + ); + AOI222_X1_LVT i_0_85( + .A1(n_86), .A2(n_0_99), .B1(n_0_91), .B2(n_55), .C1(n_24), .C2(n_0_90), .ZN(n_0_75) + ); + NAND2_X1_LVT i_0_86( + .A1(Illegal), .A2(CurrentPC[24]), .ZN(n_0_76) + ); + NAND2_X1_LVT i_0_84( + .A1(n_0_75), .A2(n_0_76), .ZN(JumpOrBranchPC[24]) + ); + AOI222_X1_LVT i_0_82( + .A1(n_85), .A2(n_0_99), .B1(n_0_91), .B2(n_54), .C1(n_23), .C2(n_0_90), .ZN(n_0_73) + ); + NAND2_X1_LVT i_0_83( + .A1(Illegal), .A2(CurrentPC[23]), .ZN(n_0_74) + ); + NAND2_X1_LVT i_0_81( + .A1(n_0_73), .A2(n_0_74), .ZN(JumpOrBranchPC[23]) + ); + AOI222_X1_LVT i_0_79( + .A1(n_84), .A2(n_0_99), .B1(n_0_91), .B2(n_53), .C1(n_22), .C2(n_0_90), .ZN(n_0_71) + ); + NAND2_X1_LVT i_0_80( + .A1(Illegal), .A2(CurrentPC[22]), .ZN(n_0_72) + ); + NAND2_X1_LVT i_0_78( + .A1(n_0_71), .A2(n_0_72), .ZN(JumpOrBranchPC[22]) + ); + AOI222_X1_LVT i_0_76( + .A1(n_83), .A2(n_0_99), .B1(n_0_91), .B2(n_52), .C1(n_21), .C2(n_0_90), .ZN(n_0_69) + ); + NAND2_X1_LVT i_0_77( + .A1(Illegal), .A2(CurrentPC[21]), .ZN(n_0_70) + ); + NAND2_X1_LVT i_0_75( + .A1(n_0_69), .A2(n_0_70), .ZN(JumpOrBranchPC[21]) + ); + AOI222_X1_LVT i_0_73( + .A1(n_82), .A2(n_0_99), .B1(n_0_91), .B2(n_51), .C1(n_20), .C2(n_0_90), .ZN(n_0_67) + ); + NAND2_X1_LVT i_0_74( + .A1(Illegal), .A2(CurrentPC[20]), .ZN(n_0_68) + ); + NAND2_X1_LVT i_0_72( + .A1(n_0_67), .A2(n_0_68), .ZN(JumpOrBranchPC[20]) + ); + AOI222_X1_LVT i_0_70( + .A1(n_81), .A2(n_0_99), .B1(n_0_91), .B2(n_50), .C1(n_19), .C2(n_0_90), .ZN(n_0_65) + ); + NAND2_X1_LVT i_0_71( + .A1(Illegal), .A2(CurrentPC[19]), .ZN(n_0_66) + ); + NAND2_X1_LVT i_0_69( + .A1(n_0_65), .A2(n_0_66), .ZN(JumpOrBranchPC[19]) + ); + AOI222_X1_LVT i_0_67( + .A1(n_80), .A2(n_0_99), .B1(n_0_91), .B2(n_49), .C1(n_18), .C2(n_0_90), .ZN(n_0_63) + ); + NAND2_X1_LVT i_0_68( + .A1(Illegal), .A2(CurrentPC[18]), .ZN(n_0_64) + ); + NAND2_X1_LVT i_0_66( + .A1(n_0_63), .A2(n_0_64), .ZN(JumpOrBranchPC[18]) + ); + AOI222_X1_LVT i_0_64( + .A1(n_79), .A2(n_0_99), .B1(n_0_91), .B2(n_48), .C1(n_17), .C2(n_0_90), .ZN(n_0_61) + ); + NAND2_X1_LVT i_0_65( + .A1(Illegal), .A2(CurrentPC[17]), .ZN(n_0_62) + ); + NAND2_X1_LVT i_0_63( + .A1(n_0_61), .A2(n_0_62), .ZN(JumpOrBranchPC[17]) + ); + AOI222_X1_LVT i_0_61( + .A1(n_78), .A2(n_0_99), .B1(n_0_91), .B2(n_47), .C1(n_16), .C2(n_0_90), .ZN(n_0_59) + ); + NAND2_X1_LVT i_0_62( + .A1(Illegal), .A2(CurrentPC[16]), .ZN(n_0_60) + ); + NAND2_X1_LVT i_0_60( + .A1(n_0_59), .A2(n_0_60), .ZN(JumpOrBranchPC[16]) + ); + AOI222_X1_LVT i_0_58( + .A1(n_77), .A2(n_0_99), .B1(n_0_91), .B2(n_46), .C1(n_15), .C2(n_0_90), .ZN(n_0_57) + ); + NAND2_X1_LVT i_0_59( + .A1(Illegal), .A2(CurrentPC[15]), .ZN(n_0_58) + ); + NAND2_X1_LVT i_0_57( + .A1(n_0_57), .A2(n_0_58), .ZN(JumpOrBranchPC[15]) + ); + AOI222_X1_LVT i_0_55( + .A1(n_76), .A2(n_0_99), .B1(n_0_91), .B2(n_45), .C1(n_14), .C2(n_0_90), .ZN(n_0_55) + ); + NAND2_X1_LVT i_0_56( + .A1(Illegal), .A2(CurrentPC[14]), .ZN(n_0_56) + ); + NAND2_X1_LVT i_0_54( + .A1(n_0_55), .A2(n_0_56), .ZN(JumpOrBranchPC[14]) + ); + AOI222_X1_LVT i_0_52( + .A1(n_75), .A2(n_0_99), .B1(n_0_91), .B2(n_44), .C1(n_13), .C2(n_0_90), .ZN(n_0_53) + ); + NAND2_X1_LVT i_0_53( + .A1(Illegal), .A2(CurrentPC[13]), .ZN(n_0_54) + ); + NAND2_X1_LVT i_0_51( + .A1(n_0_53), .A2(n_0_54), .ZN(JumpOrBranchPC[13]) + ); + AOI222_X1_LVT i_0_49( + .A1(n_74), .A2(n_0_99), .B1(n_0_91), .B2(n_43), .C1(n_12), .C2(n_0_90), .ZN(n_0_51) + ); + NAND2_X1_LVT i_0_50( + .A1(Illegal), .A2(CurrentPC[12]), .ZN(n_0_52) + ); + NAND2_X1_LVT i_0_48( + .A1(n_0_51), .A2(n_0_52), .ZN(JumpOrBranchPC[12]) + ); + AOI222_X1_LVT i_0_46( + .A1(n_73), .A2(n_0_99), .B1(n_0_91), .B2(n_42), .C1(n_11), .C2(n_0_90), .ZN(n_0_49) + ); + NAND2_X1_LVT i_0_47( + .A1(Illegal), .A2(CurrentPC[11]), .ZN(n_0_50) + ); + NAND2_X1_LVT i_0_45( + .A1(n_0_49), .A2(n_0_50), .ZN(JumpOrBranchPC[11]) + ); + AOI222_X1_LVT i_0_43( + .A1(n_72), .A2(n_0_99), .B1(n_0_91), .B2(n_41), .C1(n_10), .C2(n_0_90), .ZN(n_0_47) + ); + NAND2_X1_LVT i_0_44( + .A1(Illegal), .A2(CurrentPC[10]), .ZN(n_0_48) + ); + NAND2_X1_LVT i_0_42( + .A1(n_0_47), .A2(n_0_48), .ZN(JumpOrBranchPC[10]) + ); + AOI222_X1_LVT i_0_40( + .A1(n_71), .A2(n_0_99), .B1(n_0_91), .B2(n_40), .C1(n_9), .C2(n_0_90), .ZN(n_0_45) + ); + NAND2_X1_LVT i_0_41( + .A1(Illegal), .A2(CurrentPC[9]), .ZN(n_0_46) + ); + NAND2_X1_LVT i_0_39( + .A1(n_0_45), .A2(n_0_46), .ZN(JumpOrBranchPC[9]) + ); + AOI222_X1_LVT i_0_37( + .A1(n_70), .A2(n_0_99), .B1(n_0_91), .B2(n_39), .C1(n_8), .C2(n_0_90), .ZN(n_0_43) + ); + NAND2_X1_LVT i_0_38( + .A1(Illegal), .A2(CurrentPC[8]), .ZN(n_0_44) + ); + NAND2_X1_LVT i_0_36( + .A1(n_0_43), .A2(n_0_44), .ZN(JumpOrBranchPC[8]) + ); + AOI222_X1_LVT i_0_34( + .A1(n_69), .A2(n_0_99), .B1(n_0_91), .B2(n_38), .C1(n_7), .C2(n_0_90), .ZN(n_0_41) + ); + NAND2_X1_LVT i_0_35( + .A1(Illegal), .A2(CurrentPC[7]), .ZN(n_0_42) + ); + NAND2_X1_LVT i_0_33( + .A1(n_0_41), .A2(n_0_42), .ZN(JumpOrBranchPC[7]) + ); + AOI222_X1_LVT i_0_31( + .A1(n_68), .A2(n_0_99), .B1(n_0_91), .B2(n_37), .C1(n_6), .C2(n_0_90), .ZN(n_0_39) + ); + NAND2_X1_LVT i_0_32( + .A1(Illegal), .A2(CurrentPC[6]), .ZN(n_0_40) + ); + NAND2_X1_LVT i_0_30( + .A1(n_0_39), .A2(n_0_40), .ZN(JumpOrBranchPC[6]) + ); + AOI222_X1_LVT i_0_28( + .A1(n_67), .A2(n_0_99), .B1(n_0_91), .B2(n_36), .C1(n_5), .C2(n_0_90), .ZN(n_0_37) + ); + NAND2_X1_LVT i_0_29( + .A1(Illegal), .A2(CurrentPC[5]), .ZN(n_0_38) + ); + NAND2_X1_LVT i_0_27( + .A1(n_0_37), .A2(n_0_38), .ZN(JumpOrBranchPC[5]) + ); + AOI222_X1_LVT i_0_25( + .A1(n_66), .A2(n_0_99), .B1(n_0_91), .B2(n_35), .C1(n_4), .C2(n_0_90), .ZN(n_0_35) + ); + NAND2_X1_LVT i_0_26( + .A1(Illegal), .A2(CurrentPC[4]), .ZN(n_0_36) + ); + NAND2_X1_LVT i_0_24( + .A1(n_0_35), .A2(n_0_36), .ZN(JumpOrBranchPC[4]) + ); + AOI222_X1_LVT i_0_22( + .A1(n_65), .A2(n_0_99), .B1(n_0_91), .B2(n_34), .C1(n_3), .C2(n_0_90), .ZN(n_0_33) + ); + NAND2_X1_LVT i_0_23( + .A1(Illegal), .A2(CurrentPC[3]), .ZN(n_0_34) + ); + NAND2_X1_LVT i_0_21( + .A1(n_0_33), .A2(n_0_34), .ZN(JumpOrBranchPC[3]) + ); + AOI222_X1_LVT i_0_19( + .A1(n_64), .A2(n_0_99), .B1(n_0_91), .B2(n_33), .C1(n_2), .C2(n_0_90), .ZN(n_0_31) + ); + NAND2_X1_LVT i_0_20( + .A1(Illegal), .A2(CurrentPC[2]), .ZN(n_0_32) + ); + NAND2_X1_LVT i_0_18( + .A1(n_0_31), .A2(n_0_32), .ZN(JumpOrBranchPC[2]) + ); + AOI222_X1_LVT i_0_16( + .A1(n_63), .A2(n_0_99), .B1(n_0_91), .B2(n_32), .C1(n_1), .C2(n_0_90), .ZN(n_0_29) + ); + NAND2_X1_LVT i_0_17( + .A1(Illegal), .A2(CurrentPC[1]), .ZN(n_0_30) + ); + NAND2_X1_LVT i_0_15( + .A1(n_0_29), .A2(n_0_30), .ZN(JumpOrBranchPC[1]) + ); + NOR2_X1_LVT i_0_112( + .A1(n_0_232), .A2(n_0_238), .ZN(n_0_94) + ); + OAI221_X1_LVT i_0_14( + .A(n_0_94), .B1(n_0_225), .B2(Instruction[2]), .C1(Instruction[6]), .C2(n_0_239), + .ZN(n_0_28) + ); + AND2_X1_LVT i_0_13( + .A1(n_0_28), .A2(CurrentPC[0]), .ZN(JumpOrBranchPC[0]) + ); + NOR2_X1_LVT i_0_221( + .A1(Instruction[13]), .A2(Instruction[14]), .ZN(n_0_166) + ); + NOR3_X1_LVT i_0_293( + .A1(n_0_241), .A2(n_0_234), .A3(Instruction[3]), .ZN(n_0_206) + ); + AND2_X1_LVT i_0_292( + .A1(n_0_206), .A2(n_0_244), .ZN(n_0_205) + ); + NOR3_X1_LVT i_0_330( + .A1(n_0_248), .A2(n_0_244), .A3(Instruction[4]), .ZN(n_0_226) + ); + AOI21_X1_LVT i_0_121( + .A(n_0_205), .B1(n_0_226), .B2(n_0_237), .ZN(n_0_100) + ); + AND2_X1_LVT i_0_120( + .A1(Instruction[14]), .A2(n_0_100), .ZN(aluOp[2]) + ); + OAI33_X1_LVT i_0_119( + .A1(n_0_205), .A2(n_0_247), .A3(n_0_224), .B1(Instruction[2]), .B2(n_0_238), + .B3(n_0_225), .ZN(aluOp[1]) + ); + AOI22_X1_LVT i_0_117( + .A1(Instruction[12]), .A2(n_0_100), .B1(n_0_99), .B2(Instruction[13]), .ZN(n_0_98) + ); + INV_X1_LVT i_0_116( + .A(n_0_98), .ZN(aluOp[0]) + ); + OR2_X1_LVT i_0_327( + .A1(n_0_238), .A2(n_0_234), .ZN(n_0_223) + ); + NOR4_X1_LVT i_0_125( + .A1(Instruction[28]), .A2(Instruction[27]), .A3(Instruction[26]), .A4(Instruction[25]), + .ZN(n_0_103) + ); + INV_X1_LVT i_0_347( + .A(Instruction[30]), .ZN(n_0_242) + ); + NOR4_X1_LVT i_0_124( + .A1(Instruction[13]), .A2(n_0_242), .A3(Instruction[29]), .A4(Instruction[31]), + .ZN(n_0_102) + ); + NAND2_X1_LVT i_0_123( + .A1(n_0_103), .A2(n_0_102), .ZN(n_0_101) + ); + NOR3_X1_LVT i_0_127( + .A1(n_0_244), .A2(Instruction[12]), .A3(Instruction[14]), .ZN(n_0_105) + ); + AOI21_X1_LVT i_0_126( + .A(n_0_105), .B1(Instruction[12]), .B2(Instruction[14]), .ZN(n_0_104) + ); + NOR4_X1_LVT i_0_122( + .A1(n_0_223), .A2(n_0_101), .A3(n_0_104), .A4(Instruction[2]), .ZN(aluNegAr) + ); + OR3_X1_LVT i_0_325( + .A1(n_0_228), .A2(Instruction[4]), .A3(Instruction[6]), .ZN(n_0_222) + ); + NOR2_X1_LVT i_0_321( + .A1(n_0_222), .A2(Instruction[5]), .ZN(n_0_221) + ); + NOR3_X1_LVT i_0_224( + .A1(n_0_224), .A2(n_0_221), .A3(n_0_206), .ZN(n_0_169) + ); + NOR3_X1_LVT i_0_129( + .A1(n_0_234), .A2(Instruction[3]), .A3(Instruction[5]), .ZN(n_0_106) + ); + NOR3_X1_LVT i_0_128( + .A1(n_0_226), .A2(n_0_169), .A3(n_0_106), .ZN(aluBypass) + ); + AOI22_X1_LVT i_0_223( + .A1(CurrentPC[31]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[31]), .ZN(n_0_168) + ); + NOR3_X1_LVT i_0_219( + .A1(n_0_247), .A2(n_0_222), .A3(Instruction[5]), .ZN(n_0_164) + ); + AOI22_X1_LVT i_0_218( + .A1(RRs1[31]), .A2(n_0_169), .B1(n_0_164), .B2(RData[31]), .ZN(n_0_163) + ); + MUX2_X1_LVT i_0_222( + .A(RData[7]), .B(RData[15]), .S(Instruction[12]), .Z(n_0_167) + ); + NAND3_X1_LVT i_0_220( + .A1(n_0_221), .A2(n_0_167), .A3(n_0_166), .ZN(n_0_165) + ); + NAND3_X1_LVT i_0_217( + .A1(n_0_168), .A2(n_0_163), .A3(n_0_165), .ZN(op1[31]) + ); + AOI22_X1_LVT i_0_216( + .A1(RRs1[30]), .A2(n_0_169), .B1(n_0_164), .B2(RData[30]), .ZN(n_0_162) + ); + AOI22_X1_LVT i_0_215( + .A1(CurrentPC[30]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[30]), .ZN(n_0_161) + ); + NAND3_X1_LVT i_0_214( + .A1(n_0_162), .A2(n_0_161), .A3(n_0_165), .ZN(op1[30]) + ); + AOI22_X1_LVT i_0_213( + .A1(RRs1[29]), .A2(n_0_169), .B1(n_0_164), .B2(RData[29]), .ZN(n_0_160) + ); + AOI22_X1_LVT i_0_212( + .A1(CurrentPC[29]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[29]), .ZN(n_0_159) + ); + NAND3_X1_LVT i_0_211( + .A1(n_0_160), .A2(n_0_159), .A3(n_0_165), .ZN(op1[29]) + ); + AOI22_X1_LVT i_0_210( + .A1(RRs1[28]), .A2(n_0_169), .B1(n_0_164), .B2(RData[28]), .ZN(n_0_158) + ); + AOI22_X1_LVT i_0_209( + .A1(CurrentPC[28]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[28]), .ZN(n_0_157) + ); + NAND3_X1_LVT i_0_208( + .A1(n_0_158), .A2(n_0_157), .A3(n_0_165), .ZN(op1[28]) + ); + AOI22_X1_LVT i_0_207( + .A1(RRs1[27]), .A2(n_0_169), .B1(n_0_164), .B2(RData[27]), .ZN(n_0_156) + ); + AOI22_X1_LVT i_0_206( + .A1(CurrentPC[27]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[27]), .ZN(n_0_155) + ); + NAND3_X1_LVT i_0_205( + .A1(n_0_156), .A2(n_0_155), .A3(n_0_165), .ZN(op1[27]) + ); + AOI22_X1_LVT i_0_204( + .A1(RRs1[26]), .A2(n_0_169), .B1(n_0_164), .B2(RData[26]), .ZN(n_0_154) + ); + AOI22_X1_LVT i_0_203( + .A1(CurrentPC[26]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[26]), .ZN(n_0_153) + ); + NAND3_X1_LVT i_0_202( + .A1(n_0_154), .A2(n_0_153), .A3(n_0_165), .ZN(op1[26]) + ); + AOI22_X1_LVT i_0_201( + .A1(RRs1[25]), .A2(n_0_169), .B1(n_0_164), .B2(RData[25]), .ZN(n_0_152) + ); + AOI22_X1_LVT i_0_200( + .A1(CurrentPC[25]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[25]), .ZN(n_0_151) + ); + NAND3_X1_LVT i_0_199( + .A1(n_0_152), .A2(n_0_151), .A3(n_0_165), .ZN(op1[25]) + ); + AOI22_X1_LVT i_0_198( + .A1(RRs1[24]), .A2(n_0_169), .B1(n_0_164), .B2(RData[24]), .ZN(n_0_150) + ); + AOI22_X1_LVT i_0_197( + .A1(CurrentPC[24]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[24]), .ZN(n_0_149) + ); + NAND3_X1_LVT i_0_196( + .A1(n_0_150), .A2(n_0_149), .A3(n_0_165), .ZN(op1[24]) + ); + AOI22_X1_LVT i_0_195( + .A1(RRs1[23]), .A2(n_0_169), .B1(n_0_164), .B2(RData[23]), .ZN(n_0_148) + ); + AOI22_X1_LVT i_0_194( + .A1(CurrentPC[23]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[23]), .ZN(n_0_147) + ); + NAND3_X1_LVT i_0_193( + .A1(n_0_148), .A2(n_0_147), .A3(n_0_165), .ZN(op1[23]) + ); + AOI22_X1_LVT i_0_192( + .A1(RRs1[22]), .A2(n_0_169), .B1(n_0_164), .B2(RData[22]), .ZN(n_0_146) + ); + AOI22_X1_LVT i_0_191( + .A1(CurrentPC[22]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[22]), .ZN(n_0_145) + ); + NAND3_X1_LVT i_0_190( + .A1(n_0_146), .A2(n_0_145), .A3(n_0_165), .ZN(op1[22]) + ); + AOI22_X1_LVT i_0_189( + .A1(RRs1[21]), .A2(n_0_169), .B1(n_0_164), .B2(RData[21]), .ZN(n_0_144) + ); + AOI22_X1_LVT i_0_188( + .A1(CurrentPC[21]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[21]), .ZN(n_0_143) + ); + NAND3_X1_LVT i_0_187( + .A1(n_0_144), .A2(n_0_143), .A3(n_0_165), .ZN(op1[21]) + ); + AOI22_X1_LVT i_0_186( + .A1(RRs1[20]), .A2(n_0_169), .B1(n_0_164), .B2(RData[20]), .ZN(n_0_142) + ); + AOI22_X1_LVT i_0_185( + .A1(CurrentPC[20]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[20]), .ZN(n_0_141) + ); + NAND3_X1_LVT i_0_184( + .A1(n_0_142), .A2(n_0_141), .A3(n_0_165), .ZN(op1[20]) + ); + AOI22_X1_LVT i_0_183( + .A1(RRs1[19]), .A2(n_0_169), .B1(n_0_164), .B2(RData[19]), .ZN(n_0_140) + ); + AOI22_X1_LVT i_0_182( + .A1(CurrentPC[19]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[19]), .ZN(n_0_139) + ); + NAND3_X1_LVT i_0_181( + .A1(n_0_140), .A2(n_0_139), .A3(n_0_165), .ZN(op1[19]) + ); + AOI22_X1_LVT i_0_180( + .A1(RRs1[18]), .A2(n_0_169), .B1(n_0_164), .B2(RData[18]), .ZN(n_0_138) + ); + AOI22_X1_LVT i_0_179( + .A1(CurrentPC[18]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[18]), .ZN(n_0_137) + ); + NAND3_X1_LVT i_0_178( + .A1(n_0_138), .A2(n_0_137), .A3(n_0_165), .ZN(op1[18]) + ); + AOI22_X1_LVT i_0_177( + .A1(RRs1[17]), .A2(n_0_169), .B1(n_0_164), .B2(RData[17]), .ZN(n_0_136) + ); + AOI22_X1_LVT i_0_176( + .A1(CurrentPC[17]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[17]), .ZN(n_0_135) + ); + NAND3_X1_LVT i_0_175( + .A1(n_0_136), .A2(n_0_135), .A3(n_0_165), .ZN(op1[17]) + ); + AOI22_X1_LVT i_0_174( + .A1(RRs1[16]), .A2(n_0_169), .B1(n_0_164), .B2(RData[16]), .ZN(n_0_134) + ); + AOI22_X1_LVT i_0_173( + .A1(CurrentPC[16]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[16]), .ZN(n_0_133) + ); + NAND3_X1_LVT i_0_172( + .A1(n_0_134), .A2(n_0_133), .A3(n_0_165), .ZN(op1[16]) + ); + AOI222_X1_LVT i_0_169( + .A1(CurrentPC[15]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[15]), .C1(n_0_169), + .C2(RRs1[15]), .ZN(n_0_130) + ); + INV_X1_LVT i_0_353( + .A(Instruction[12]), .ZN(n_0_246) + ); + AOI211_X1_LVT i_0_171( + .A(Instruction[5]), .B(n_0_222), .C1(n_0_247), .C2(n_0_246), .ZN(n_0_132) + ); + OAI211_X1_LVT i_0_170( + .A(RData[15]), .B(n_0_132), .C1(Instruction[13]), .C2(Instruction[14]), .ZN(n_0_131) + ); + NAND3_X1_LVT i_0_168( + .A1(n_0_130), .A2(n_0_131), .A3(n_0_165), .ZN(op1[15]) + ); + AOI22_X1_LVT i_0_167( + .A1(RRs1[14]), .A2(n_0_169), .B1(n_0_132), .B2(RData[14]), .ZN(n_0_129) + ); + AOI22_X1_LVT i_0_166( + .A1(CurrentPC[14]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[14]), .ZN(n_0_128) + ); + NAND4_X1_LVT i_0_165( + .A1(n_0_221), .A2(n_0_246), .A3(RData[7]), .A4(n_0_166), .ZN(n_0_127) + ); + NAND3_X1_LVT i_0_164( + .A1(n_0_129), .A2(n_0_128), .A3(n_0_127), .ZN(op1[14]) + ); + AOI22_X1_LVT i_0_163( + .A1(RRs1[13]), .A2(n_0_169), .B1(n_0_132), .B2(RData[13]), .ZN(n_0_126) + ); + AOI22_X1_LVT i_0_162( + .A1(CurrentPC[13]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[13]), .ZN(n_0_125) + ); + NAND3_X1_LVT i_0_161( + .A1(n_0_126), .A2(n_0_125), .A3(n_0_127), .ZN(op1[13]) + ); + AOI22_X1_LVT i_0_160( + .A1(RRs1[12]), .A2(n_0_169), .B1(n_0_132), .B2(RData[12]), .ZN(n_0_124) + ); + AOI22_X1_LVT i_0_159( + .A1(CurrentPC[12]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[12]), .ZN(n_0_123) + ); + NAND3_X1_LVT i_0_158( + .A1(n_0_124), .A2(n_0_123), .A3(n_0_127), .ZN(op1[12]) + ); + AOI22_X1_LVT i_0_156( + .A1(CurrentPC[11]), .A2(n_0_224), .B1(n_0_132), .B2(RData[11]), .ZN(n_0_121) + ); + NAND2_X1_LVT i_0_157( + .A1(RRs1[11]), .A2(n_0_169), .ZN(n_0_122) + ); + NAND3_X1_LVT i_0_155( + .A1(n_0_121), .A2(n_0_122), .A3(n_0_127), .ZN(op1[11]) + ); + AOI22_X1_LVT i_0_153( + .A1(CurrentPC[10]), .A2(n_0_224), .B1(n_0_132), .B2(RData[10]), .ZN(n_0_119) + ); + NAND2_X1_LVT i_0_154( + .A1(RRs1[10]), .A2(n_0_169), .ZN(n_0_120) + ); + NAND3_X1_LVT i_0_152( + .A1(n_0_119), .A2(n_0_120), .A3(n_0_127), .ZN(op1[10]) + ); + AOI22_X1_LVT i_0_150( + .A1(CurrentPC[9]), .A2(n_0_224), .B1(n_0_132), .B2(RData[9]), .ZN(n_0_117) + ); + NAND2_X1_LVT i_0_151( + .A1(RRs1[9]), .A2(n_0_169), .ZN(n_0_118) + ); + NAND3_X1_LVT i_0_149( + .A1(n_0_117), .A2(n_0_118), .A3(n_0_127), .ZN(op1[9]) + ); + AOI22_X1_LVT i_0_147( + .A1(CurrentPC[8]), .A2(n_0_224), .B1(n_0_132), .B2(RData[8]), .ZN(n_0_115) + ); + NAND2_X1_LVT i_0_148( + .A1(RRs1[8]), .A2(n_0_169), .ZN(n_0_116) + ); + NAND3_X1_LVT i_0_146( + .A1(n_0_115), .A2(n_0_116), .A3(n_0_127), .ZN(op1[8]) + ); + AOI222_X1_LVT i_0_145( + .A1(CurrentPC[7]), .A2(n_0_224), .B1(n_0_221), .B2(RData[7]), .C1(n_0_169), + .C2(RRs1[7]), .ZN(n_0_114) + ); + INV_X1_LVT i_0_144( + .A(n_0_114), .ZN(op1[7]) + ); + AOI222_X1_LVT i_0_143( + .A1(CurrentPC[6]), .A2(n_0_224), .B1(n_0_221), .B2(RData[6]), .C1(n_0_169), + .C2(RRs1[6]), .ZN(n_0_113) + ); + INV_X1_LVT i_0_142( + .A(n_0_113), .ZN(op1[6]) + ); + AOI222_X1_LVT i_0_141( + .A1(CurrentPC[5]), .A2(n_0_224), .B1(n_0_221), .B2(RData[5]), .C1(n_0_169), + .C2(RRs1[5]), .ZN(n_0_112) + ); + INV_X1_LVT i_0_140( + .A(n_0_112), .ZN(op1[5]) + ); + AOI222_X1_LVT i_0_139( + .A1(CurrentPC[4]), .A2(n_0_224), .B1(n_0_221), .B2(RData[4]), .C1(n_0_169), + .C2(RRs1[4]), .ZN(n_0_111) + ); + INV_X1_LVT i_0_138( + .A(n_0_111), .ZN(op1[4]) + ); + AOI222_X1_LVT i_0_137( + .A1(CurrentPC[3]), .A2(n_0_224), .B1(n_0_221), .B2(RData[3]), .C1(n_0_169), + .C2(RRs1[3]), .ZN(n_0_110) + ); + INV_X1_LVT i_0_136( + .A(n_0_110), .ZN(op1[3]) + ); + AOI222_X1_LVT i_0_135( + .A1(CurrentPC[2]), .A2(n_0_224), .B1(n_0_221), .B2(RData[2]), .C1(n_0_169), + .C2(RRs1[2]), .ZN(n_0_109) + ); + INV_X1_LVT i_0_134( + .A(n_0_109), .ZN(op1[2]) + ); + AOI222_X1_LVT i_0_133( + .A1(CurrentPC[1]), .A2(n_0_224), .B1(n_0_221), .B2(RData[1]), .C1(n_0_169), + .C2(RRs1[1]), .ZN(n_0_108) + ); + INV_X1_LVT i_0_132( + .A(n_0_108), .ZN(op1[1]) + ); + AOI222_X1_LVT i_0_131( + .A1(CurrentPC[0]), .A2(n_0_224), .B1(n_0_221), .B2(RData[0]), .C1(n_0_169), + .C2(RRs1[0]), .ZN(n_0_107) + ); + INV_X1_LVT i_0_130( + .A(n_0_107), .ZN(op1[0]) + ); + NOR3_X1_LVT i_0_294( + .A1(n_0_223), .A2(Instruction[2]), .A3(Instruction[5]), .ZN(n_0_207) + ); + NOR3_X1_LVT i_0_291( + .A1(n_0_224), .A2(n_0_207), .A3(n_0_205), .ZN(n_0_204) + ); + AOI22_X1_LVT i_0_289( + .A1(CurrentPC[31]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[31]), .ZN(n_0_202) + ); + NAND2_X1_LVT i_0_290( + .A1(Instruction[31]), .A2(n_0_207), .ZN(n_0_203) + ); + NAND2_X1_LVT i_0_288( + .A1(n_0_202), .A2(n_0_203), .ZN(op2[31]) + ); + AOI22_X1_LVT i_0_287( + .A1(CurrentPC[30]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[30]), .ZN(n_0_201) + ); + NAND2_X1_LVT i_0_286( + .A1(n_0_201), .A2(n_0_203), .ZN(op2[30]) + ); + AOI22_X1_LVT i_0_285( + .A1(CurrentPC[29]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[29]), .ZN(n_0_200) + ); + NAND2_X1_LVT i_0_284( + .A1(n_0_200), .A2(n_0_203), .ZN(op2[29]) + ); + AOI22_X1_LVT i_0_283( + .A1(CurrentPC[28]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[28]), .ZN(n_0_199) + ); + NAND2_X1_LVT i_0_282( + .A1(n_0_199), .A2(n_0_203), .ZN(op2[28]) + ); + AOI22_X1_LVT i_0_281( + .A1(CurrentPC[27]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[27]), .ZN(n_0_198) + ); + NAND2_X1_LVT i_0_280( + .A1(n_0_198), .A2(n_0_203), .ZN(op2[27]) + ); + AOI22_X1_LVT i_0_279( + .A1(CurrentPC[26]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[26]), .ZN(n_0_197) + ); + NAND2_X1_LVT i_0_278( + .A1(n_0_197), .A2(n_0_203), .ZN(op2[26]) + ); + AOI22_X1_LVT i_0_277( + .A1(CurrentPC[25]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[25]), .ZN(n_0_196) + ); + NAND2_X1_LVT i_0_276( + .A1(n_0_196), .A2(n_0_203), .ZN(op2[25]) + ); + AOI22_X1_LVT i_0_275( + .A1(CurrentPC[24]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[24]), .ZN(n_0_195) + ); + NAND2_X1_LVT i_0_274( + .A1(n_0_195), .A2(n_0_203), .ZN(op2[24]) + ); + AOI22_X1_LVT i_0_273( + .A1(CurrentPC[23]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[23]), .ZN(n_0_194) + ); + NAND2_X1_LVT i_0_272( + .A1(n_0_194), .A2(n_0_203), .ZN(op2[23]) + ); + AOI22_X1_LVT i_0_271( + .A1(CurrentPC[22]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[22]), .ZN(n_0_193) + ); + NAND2_X1_LVT i_0_270( + .A1(n_0_193), .A2(n_0_203), .ZN(op2[22]) + ); + AOI22_X1_LVT i_0_269( + .A1(CurrentPC[21]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[21]), .ZN(n_0_192) + ); + NAND2_X1_LVT i_0_268( + .A1(n_0_192), .A2(n_0_203), .ZN(op2[21]) + ); + AOI22_X1_LVT i_0_267( + .A1(CurrentPC[20]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[20]), .ZN(n_0_191) + ); + NAND2_X1_LVT i_0_266( + .A1(n_0_191), .A2(n_0_203), .ZN(op2[20]) + ); + AOI22_X1_LVT i_0_265( + .A1(CurrentPC[19]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[19]), .ZN(n_0_190) + ); + NAND2_X1_LVT i_0_264( + .A1(n_0_190), .A2(n_0_203), .ZN(op2[19]) + ); + AOI22_X1_LVT i_0_263( + .A1(CurrentPC[18]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[18]), .ZN(n_0_189) + ); + NAND2_X1_LVT i_0_262( + .A1(n_0_189), .A2(n_0_203), .ZN(op2[18]) + ); + AOI22_X1_LVT i_0_261( + .A1(CurrentPC[17]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[17]), .ZN(n_0_188) + ); + NAND2_X1_LVT i_0_260( + .A1(n_0_188), .A2(n_0_203), .ZN(op2[17]) + ); + AOI22_X1_LVT i_0_259( + .A1(CurrentPC[16]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[16]), .ZN(n_0_187) + ); + NAND2_X1_LVT i_0_258( + .A1(n_0_187), .A2(n_0_203), .ZN(op2[16]) + ); + AOI22_X1_LVT i_0_257( + .A1(CurrentPC[15]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[15]), .ZN(n_0_186) + ); + NAND2_X1_LVT i_0_256( + .A1(n_0_186), .A2(n_0_203), .ZN(op2[15]) + ); + AOI22_X1_LVT i_0_255( + .A1(CurrentPC[14]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[14]), .ZN(n_0_185) + ); + NAND2_X1_LVT i_0_254( + .A1(n_0_185), .A2(n_0_203), .ZN(op2[14]) + ); + AOI22_X1_LVT i_0_253( + .A1(CurrentPC[13]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[13]), .ZN(n_0_184) + ); + NAND2_X1_LVT i_0_252( + .A1(n_0_184), .A2(n_0_203), .ZN(op2[13]) + ); + AOI22_X1_LVT i_0_251( + .A1(CurrentPC[12]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[12]), .ZN(n_0_183) + ); + NAND2_X1_LVT i_0_250( + .A1(n_0_183), .A2(n_0_203), .ZN(op2[12]) + ); + AOI22_X1_LVT i_0_249( + .A1(CurrentPC[11]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[11]), .ZN(n_0_182) + ); + NAND2_X1_LVT i_0_248( + .A1(n_0_182), .A2(n_0_203), .ZN(op2[11]) + ); + AOI222_X1_LVT i_0_247( + .A1(Instruction[30]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[10]), .C1(n_0_204), + .C2(RRs2[10]), .ZN(n_0_181) + ); + INV_X1_LVT i_0_246( + .A(n_0_181), .ZN(op2[10]) + ); + AOI222_X1_LVT i_0_245( + .A1(Instruction[29]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[9]), .C1(n_0_204), + .C2(RRs2[9]), .ZN(n_0_180) + ); + INV_X1_LVT i_0_244( + .A(n_0_180), .ZN(op2[9]) + ); + AOI222_X1_LVT i_0_243( + .A1(Instruction[28]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[8]), .C1(n_0_204), + .C2(RRs2[8]), .ZN(n_0_179) + ); + INV_X1_LVT i_0_242( + .A(n_0_179), .ZN(op2[8]) + ); + AOI222_X1_LVT i_0_241( + .A1(Instruction[27]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[7]), .C1(n_0_204), + .C2(RRs2[7]), .ZN(n_0_178) + ); + INV_X1_LVT i_0_240( + .A(n_0_178), .ZN(op2[7]) + ); + AOI222_X1_LVT i_0_239( + .A1(Instruction[26]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[6]), .C1(n_0_204), + .C2(RRs2[6]), .ZN(n_0_177) + ); + INV_X1_LVT i_0_238( + .A(n_0_177), .ZN(op2[6]) + ); + AOI222_X1_LVT i_0_237( + .A1(Instruction[25]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[5]), .C1(n_0_204), + .C2(RRs2[5]), .ZN(n_0_176) + ); + INV_X1_LVT i_0_236( + .A(n_0_176), .ZN(op2[5]) + ); + AOI222_X1_LVT i_0_235( + .A1(Instruction[24]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[4]), .C1(n_0_204), + .C2(RRs2[4]), .ZN(n_0_175) + ); + INV_X1_LVT i_0_234( + .A(n_0_175), .ZN(op2[4]) + ); + AOI222_X1_LVT i_0_233( + .A1(Instruction[23]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[3]), .C1(n_0_204), + .C2(RRs2[3]), .ZN(n_0_174) + ); + INV_X1_LVT i_0_232( + .A(n_0_174), .ZN(op2[3]) + ); + AOI22_X1_LVT i_0_230( + .A1(Instruction[22]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[2]), .ZN(n_0_172) + ); + OAI21_X1_LVT i_0_231( + .A(RRs2[2]), .B1(n_0_223), .B2(Instruction[5]), .ZN(n_0_173) + ); + NAND3_X1_LVT i_0_229( + .A1(n_0_172), .A2(n_0_173), .A3(n_0_249), .ZN(op2[2]) + ); + AOI222_X1_LVT i_0_228( + .A1(Instruction[21]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[1]), .C1(n_0_204), + .C2(RRs2[1]), .ZN(n_0_171) + ); + INV_X1_LVT i_0_227( + .A(n_0_171), .ZN(op2[1]) + ); + AOI222_X1_LVT i_0_226( + .A1(Instruction[20]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[0]), .C1(n_0_204), + .C2(RRs2[0]), .ZN(n_0_170) + ); + INV_X1_LVT i_0_225( + .A(n_0_170), .ZN(op2[0]) + ); + alu theALU( + .aluOp(aluOp), .aluNegAr(aluNegAr), .aluBypass(aluBypass), .op1(op1), .op2(op2), + .result(WRd), .eqFlag(eqFlag) + ); + XNOR2_X1_LVT i_0_115( + .A(Instruction[12]), .B(eqFlag), .ZN(n_0_97) + ); + XNOR2_X1_LVT i_0_114( + .A(Instruction[12]), .B(WRd[0]), .ZN(n_0_96) + ); + AOI22_X1_LVT i_0_113( + .A1(n_0_166), .A2(n_0_97), .B1(n_0_96), .B2(Instruction[14]), .ZN(n_0_95) + ); + AOI22_X1_LVT i_0_111( + .A1(Instruction[6]), .A2(n_0_95), .B1(Instruction[2]), .B2(n_0_245), .ZN(n_0_93) + ); + NAND2_X1_LVT i_0_110( + .A1(n_0_94), .A2(n_0_93), .ZN(JumpOrBranch) + ); + INV_X1_LVT i_0_349( + .A(Instruction[31]), .ZN(n_0_0) + ); + INV_X1_LVT i_0_348( + .A(RRs1[12]), .ZN(n_0_1) + ); + HA_X1_LVT i_0_0( + .A(Instruction[7]), .B(RRs1[0]), .CO(n_0_2), .S(n_0_15) + ); + FA_X1_LVT i_0_1( + .A(Instruction[8]), .B(RRs1[1]), .CI(n_0_2), .CO(n_0_3), .S(n_0_16) + ); + FA_X1_LVT i_0_2( + .A(Instruction[9]), .B(RRs1[2]), .CI(n_0_3), .CO(n_0_4), .S(n_0_17) + ); + FA_X1_LVT i_0_3( + .A(Instruction[10]), .B(RRs1[3]), .CI(n_0_4), .CO(n_0_5), .S(n_0_18) + ); + FA_X1_LVT i_0_4( + .A(Instruction[11]), .B(RRs1[4]), .CI(n_0_5), .CO(n_0_6), .S(n_0_19) + ); + FA_X1_LVT i_0_5( + .A(Instruction[25]), .B(RRs1[5]), .CI(n_0_6), .CO(n_0_7), .S(n_0_20) + ); + FA_X1_LVT i_0_6( + .A(Instruction[26]), .B(RRs1[6]), .CI(n_0_7), .CO(n_0_8), .S(n_0_21) + ); + FA_X1_LVT i_0_7( + .A(Instruction[27]), .B(RRs1[7]), .CI(n_0_8), .CO(n_0_9), .S(n_0_22) + ); + FA_X1_LVT i_0_8( + .A(Instruction[28]), .B(RRs1[8]), .CI(n_0_9), .CO(n_0_10), .S(n_0_23) + ); + FA_X1_LVT i_0_9( + .A(Instruction[29]), .B(RRs1[9]), .CI(n_0_10), .CO(n_0_11), .S(n_0_24) + ); + FA_X1_LVT i_0_10( + .A(Instruction[30]), .B(RRs1[10]), .CI(n_0_11), .CO(n_0_12), .S(n_0_25) + ); + FA_X1_LVT i_0_11( + .A(RRs1[11]), .B(Instruction[31]), .CI(n_0_12), .CO(n_0_13), .S(n_0_26) + ); + FA_X1_LVT i_0_12( + .A(n_0_0), .B(n_0_1), .CI(n_0_13), .CO(n_0_14), .S(n_0_27) + ); + NOR2_X1_LVT i_0_322( + .A1(n_0_244), .A2(n_0_222), .ZN(WrMem) + ); + AOI22_X1_LVT i_0_320( + .A1(n_0_27), .A2(WrMem), .B1(n_0_221), .B2(n_12), .ZN(n_0_220) + ); + INV_X1_LVT i_0_319( + .A(n_0_220), .ZN(DAddr[12]) + ); + AOI22_X1_LVT i_0_318( + .A1(n_0_26), .A2(WrMem), .B1(n_0_221), .B2(n_11), .ZN(n_0_219) + ); + INV_X1_LVT i_0_317( + .A(n_0_219), .ZN(DAddr[11]) + ); + AOI22_X1_LVT i_0_316( + .A1(n_0_25), .A2(WrMem), .B1(n_0_221), .B2(n_10), .ZN(n_0_218) + ); + INV_X1_LVT i_0_315( + .A(n_0_218), .ZN(DAddr[10]) + ); + AOI22_X1_LVT i_0_314( + .A1(n_0_24), .A2(WrMem), .B1(n_0_221), .B2(n_9), .ZN(n_0_217) + ); + INV_X1_LVT i_0_313( + .A(n_0_217), .ZN(DAddr[9]) + ); + AOI22_X1_LVT i_0_312( + .A1(n_0_23), .A2(WrMem), .B1(n_0_221), .B2(n_8), .ZN(n_0_216) + ); + INV_X1_LVT i_0_311( + .A(n_0_216), .ZN(DAddr[8]) + ); + AOI22_X1_LVT i_0_310( + .A1(n_0_22), .A2(WrMem), .B1(n_0_221), .B2(n_7), .ZN(n_0_215) + ); + INV_X1_LVT i_0_309( + .A(n_0_215), .ZN(DAddr[7]) + ); + AOI22_X1_LVT i_0_308( + .A1(n_0_21), .A2(WrMem), .B1(n_0_221), .B2(n_6), .ZN(n_0_214) + ); + INV_X1_LVT i_0_307( + .A(n_0_214), .ZN(DAddr[6]) + ); + AOI22_X1_LVT i_0_306( + .A1(n_0_20), .A2(WrMem), .B1(n_0_221), .B2(n_5), .ZN(n_0_213) + ); + INV_X1_LVT i_0_305( + .A(n_0_213), .ZN(DAddr[5]) + ); + AOI22_X1_LVT i_0_304( + .A1(n_0_19), .A2(WrMem), .B1(n_0_221), .B2(n_4), .ZN(n_0_212) + ); + INV_X1_LVT i_0_303( + .A(n_0_212), .ZN(DAddr[4]) + ); + AOI22_X1_LVT i_0_302( + .A1(n_0_18), .A2(WrMem), .B1(n_0_221), .B2(n_3), .ZN(n_0_211) + ); + INV_X1_LVT i_0_301( + .A(n_0_211), .ZN(DAddr[3]) + ); + AOI22_X1_LVT i_0_300( + .A1(n_0_17), .A2(WrMem), .B1(n_0_221), .B2(n_2), .ZN(n_0_210) + ); + INV_X1_LVT i_0_299( + .A(n_0_210), .ZN(DAddr[2]) + ); + AOI22_X1_LVT i_0_298( + .A1(n_0_16), .A2(WrMem), .B1(n_0_221), .B2(n_1), .ZN(n_0_209) + ); + INV_X1_LVT i_0_297( + .A(n_0_209), .ZN(DAddr[1]) + ); + AOI22_X1_LVT i_0_296( + .A1(n_0_15), .A2(WrMem), .B1(n_0_221), .B2(n_0), .ZN(n_0_208) + ); + INV_X1_LVT i_0_295( + .A(n_0_208), .ZN(DAddr[0]) + ); + OR2_X1_LVT i_0_324( + .A1(n_0_222), .A2(Instruction[13]), .ZN(DWidth[1]) + ); + NOR2_X1_LVT i_0_323( + .A1(n_0_246), .A2(n_0_222), .ZN(DWidth[0]) + ); + NAND3_X1_LVT i_0_331( + .A1(n_0_248), .A2(n_0_244), .A3(n_0_236), .ZN(n_0_227) + ); + OAI211_X1_LVT i_0_326( + .A(n_0_249), .B(n_0_223), .C1(n_0_228), .C2(n_0_227), .ZN(WrReg) + ); +endmodule + +module MemGen_32_11(chip_en, clock, addr, rd_data, rd_en, wr_en, wr_data); + input [31:0] wr_data; + input [10:0] addr; + input chip_en, clock, rd_en, wr_en; + output [31:0] rd_data; + + wire [1:0] mem_sel; + wire n_63, n_62, n_61, n_60, n_59, n_58, n_57, n_56, n_55, n_54, n_53, n_52, + n_51, n_50, n_49, n_48, n_31, n_30, n_29, n_28, n_27, n_26, n_25, n_24, + n_23, n_22, n_21, n_20, n_19, n_18, n_17, n_16, n_47, n_46, n_45, n_44, + n_43, n_42, n_41, n_40, n_39, n_38, n_37, n_36, n_35, n_34, n_33, n_32, + n_15, n_14, n_13, n_12, n_11, n_10, n_9, n_8, n_7, n_6, n_5, n_4, n_3, + n_2, n_1, n_0; + + INV_X1_LVT i_1_3( + .A(addr[10]), .ZN(mem_sel[0]) + ); + MemGen_16_10 genblk1_0_U_hi( + .chip_en(mem_sel[0]), .wr_en(wr_en), .addr({addr[9], addr[8], addr[7], + addr[6], addr[5], addr[4], addr[3], addr[2], addr[1], addr[0]}), .wr_data({ + wr_data[31], wr_data[30], wr_data[29], wr_data[28], wr_data[27], + wr_data[26], wr_data[25], wr_data[24], wr_data[23], wr_data[22], + wr_data[21], wr_data[20], wr_data[19], wr_data[18], wr_data[17], + wr_data[16]}), .clock(clock), .rd_en(rd_en), .rd_data({n_63, n_62, n_61, + n_60, n_59, n_58, n_57, n_56, n_55, n_54, n_53, n_52, n_51, n_50, n_49, + n_48}) + ); + MemGen_16_10 genblk1_1_U_hi( + .chip_en(addr[10]), .wr_en(wr_en), .addr({addr[9], addr[8], addr[7], + addr[6], addr[5], addr[4], addr[3], addr[2], addr[1], addr[0]}), .wr_data({ + wr_data[31], wr_data[30], wr_data[29], wr_data[28], wr_data[27], + wr_data[26], wr_data[25], wr_data[24], wr_data[23], wr_data[22], + wr_data[21], wr_data[20], wr_data[19], wr_data[18], wr_data[17], + wr_data[16]}), .clock(clock), .rd_en(rd_en), .rd_data({n_31, n_30, n_29, + n_28, n_27, n_26, n_25, n_24, n_23, n_22, n_21, n_20, n_19, n_18, n_17, + n_16}) + ); + MUX2_X1_LVT i_1_1_31( + .A(n_63), .B(n_31), .S(addr[10]), .Z(rd_data[31]) + ); + MUX2_X1_LVT i_1_1_30( + .A(n_62), .B(n_30), .S(addr[10]), .Z(rd_data[30]) + ); + MUX2_X1_LVT i_1_1_29( + .A(n_61), .B(n_29), .S(addr[10]), .Z(rd_data[29]) + ); + MUX2_X1_LVT i_1_1_28( + .A(n_60), .B(n_28), .S(addr[10]), .Z(rd_data[28]) + ); + MUX2_X1_LVT i_1_1_27( + .A(n_59), .B(n_27), .S(addr[10]), .Z(rd_data[27]) + ); + MUX2_X1_LVT i_1_1_26( + .A(n_58), .B(n_26), .S(addr[10]), .Z(rd_data[26]) + ); + MUX2_X1_LVT i_1_1_25( + .A(n_57), .B(n_25), .S(addr[10]), .Z(rd_data[25]) + ); + MUX2_X1_LVT i_1_1_24( + .A(n_56), .B(n_24), .S(addr[10]), .Z(rd_data[24]) + ); + MUX2_X1_LVT i_1_1_23( + .A(n_55), .B(n_23), .S(addr[10]), .Z(rd_data[23]) + ); + MUX2_X1_LVT i_1_1_22( + .A(n_54), .B(n_22), .S(addr[10]), .Z(rd_data[22]) + ); + MUX2_X1_LVT i_1_1_21( + .A(n_53), .B(n_21), .S(addr[10]), .Z(rd_data[21]) + ); + MUX2_X1_LVT i_1_1_20( + .A(n_52), .B(n_20), .S(addr[10]), .Z(rd_data[20]) + ); + MUX2_X1_LVT i_1_1_19( + .A(n_51), .B(n_19), .S(addr[10]), .Z(rd_data[19]) + ); + MUX2_X1_LVT i_1_1_18( + .A(n_50), .B(n_18), .S(addr[10]), .Z(rd_data[18]) + ); + MUX2_X1_LVT i_1_1_17( + .A(n_49), .B(n_17), .S(addr[10]), .Z(rd_data[17]) + ); + MUX2_X1_LVT i_1_1_16( + .A(n_48), .B(n_16), .S(addr[10]), .Z(rd_data[16]) + ); + MemGen_16_10 genblk1_0_U_lo( + .chip_en(mem_sel[0]), .wr_en(wr_en), .addr({addr[9], addr[8], addr[7], + addr[6], addr[5], addr[4], addr[3], addr[2], addr[1], addr[0]}), .wr_data({ + wr_data[15], wr_data[14], wr_data[13], wr_data[12], wr_data[11], + wr_data[10], wr_data[9], wr_data[8], wr_data[7], wr_data[6], wr_data[5], + wr_data[4], wr_data[3], wr_data[2], wr_data[1], wr_data[0]}), .clock(clock), + .rd_en(rd_en), .rd_data({n_47, n_46, n_45, n_44, n_43, n_42, n_41, + n_40, n_39, n_38, n_37, n_36, n_35, n_34, n_33, n_32}) + ); + MemGen_16_10 genblk1_1_U_lo( + .chip_en(addr[10]), .wr_en(wr_en), .addr({addr[9], addr[8], addr[7], + addr[6], addr[5], addr[4], addr[3], addr[2], addr[1], addr[0]}), .wr_data({ + wr_data[15], wr_data[14], wr_data[13], wr_data[12], wr_data[11], + wr_data[10], wr_data[9], wr_data[8], wr_data[7], wr_data[6], wr_data[5], + wr_data[4], wr_data[3], wr_data[2], wr_data[1], wr_data[0]}), .clock(clock), + .rd_en(rd_en), .rd_data({n_15, n_14, n_13, n_12, n_11, n_10, n_9, n_8, + n_7, n_6, n_5, n_4, n_3, n_2, n_1, n_0}) + ); + MUX2_X1_LVT i_1_1_15( + .A(n_47), .B(n_15), .S(addr[10]), .Z(rd_data[15]) + ); + MUX2_X1_LVT i_1_1_14( + .A(n_46), .B(n_14), .S(addr[10]), .Z(rd_data[14]) + ); + MUX2_X1_LVT i_1_1_13( + .A(n_45), .B(n_13), .S(addr[10]), .Z(rd_data[13]) + ); + MUX2_X1_LVT i_1_1_12( + .A(n_44), .B(n_12), .S(addr[10]), .Z(rd_data[12]) + ); + MUX2_X1_LVT i_1_1_11( + .A(n_43), .B(n_11), .S(addr[10]), .Z(rd_data[11]) + ); + MUX2_X1_LVT i_1_1_10( + .A(n_42), .B(n_10), .S(addr[10]), .Z(rd_data[10]) + ); + MUX2_X1_LVT i_1_1_9( + .A(n_41), .B(n_9), .S(addr[10]), .Z(rd_data[9]) + ); + MUX2_X1_LVT i_1_1_8( + .A(n_40), .B(n_8), .S(addr[10]), .Z(rd_data[8]) + ); + MUX2_X1_LVT i_1_1_7( + .A(n_39), .B(n_7), .S(addr[10]), .Z(rd_data[7]) + ); + MUX2_X1_LVT i_1_1_6( + .A(n_38), .B(n_6), .S(addr[10]), .Z(rd_data[6]) + ); + MUX2_X1_LVT i_1_1_5( + .A(n_37), .B(n_5), .S(addr[10]), .Z(rd_data[5]) + ); + MUX2_X1_LVT i_1_1_4( + .A(n_36), .B(n_4), .S(addr[10]), .Z(rd_data[4]) + ); + MUX2_X1_LVT i_1_1_3( + .A(n_35), .B(n_3), .S(addr[10]), .Z(rd_data[3]) + ); + MUX2_X1_LVT i_1_1_2( + .A(n_34), .B(n_2), .S(addr[10]), .Z(rd_data[2]) + ); + MUX2_X1_LVT i_1_1_1( + .A(n_33), .B(n_1), .S(addr[10]), .Z(rd_data[1]) + ); + MUX2_X1_LVT i_1_1_0( + .A(n_32), .B(n_0), .S(addr[10]), .Z(rd_data[0]) + ); +endmodule + +module main_mem(clk, reset, DAddr, IAddr, DWData, DRData, IRData, DWE, DWidth); + input [31:0] DAddr, IAddr, DWData; + input [1:0] DWidth; + input clk, reset, DWE; + output [31:0] DRData, IRData; + + wire [31:0] mem_rdata, drTmp, mem_wdata; + wire [10:0] mem_addr; + wire n_0_0, n_0_0_0, n_0_1, n_0_0_1, n_0_2, n_0_0_2, n_0_3, n_0_0_3, n_0_4, + n_0_0_4, n_0_5, n_0_0_5, n_0_6, n_0_0_6, n_0_7, n_0_0_7, n_0_8, n_0_0_8, + n_0_9, n_0_0_9, n_0_10, n_0_0_10, n_0_0_11, n_0_11, n_0_0_12, n_0_0_13, + n_0_12, n_0_0_14, n_0_0_15, n_0_13, n_0_0_16, n_0_0_17, n_0_14, + n_0_0_18, n_0_0_19, n_0_15, n_0_0_20, n_0_0_21, n_0_16, n_0_0_22, + n_0_0_23, n_0_17, n_0_0_24, n_0_0_25, n_0_18, n_0_0_26, n_0_0_27, + n_0_0_28, n_0_19, n_0_0_29, n_0_20, n_0_0_30, n_0_21, n_0_0_31, n_0_22, + n_0_0_32, n_0_23, n_0_0_33, n_0_24, n_0_0_34, n_0_25, n_0_0_35, n_0_26, + n_0_0_36, n_0_0_37, n_0_27, n_0_28, n_0_29, n_0_30, n_0_31, n_0_32, + n_0_33, n_0_34, n_0_35, n_0_36, n_0_37, n_0_38, n_0_39, n_0_40, n_0_41, + n_0_42, n_0_65, n_0_64, n_0_63, n_0_62, n_0_61, n_0_60, n_0_59, n_0_58, + n_0_0_38, n_0_0_39, n_0_57, n_0_0_40, n_0_56, n_0_0_41, n_0_55, + n_0_0_42, n_0_54, n_0_0_43, n_0_53, n_0_0_44, n_0_52, n_0_0_45, n_0_51, + n_0_0_46, n_0_50, n_0_0_47, n_0_0_48, n_0_0_49, n_0_0_50, n_0_0_51, + n_0_49, n_0_0_52, n_0_48, n_0_0_53, n_0_47, n_0_0_54, n_0_46, n_0_0_55, + n_0_45, n_0_0_56, n_0_44, n_0_0_57, n_0_66, n_0_0_58, n_0_67, n_0_0_59, + n_0_0_60, n_0_0_61, n_0_68, n_0_0_62, n_0_0_63, n_0_69, n_0_0_64, + n_0_0_65, n_0_70, n_0_0_66, n_0_0_67, n_0_71, n_0_0_68, n_0_0_69, + n_0_72, n_0_0_70, n_0_0_71, n_0_73, n_0_0_72, n_0_0_73, n_0_74, + n_0_0_74, n_0_0_75, n_0_75, n_0_0_76, n_0_0_77, n_0_0_78, n_0_0_79, + n_0_0_80, n_0_0_81, n_0_0_82, n_0_0_83, n_0_0_84, n_0_0_85, n_0_0_86, + n_0_0_87, n_0_0_88, n_0_0_89, n_0_0_90, n_0_0_91, n_0_0_92, n_0_43, + n_0_0_93, n_0_0_94, n_0_76, n_0_0_95, n_0; + + INV_X1_LVT i_0_0_171( + .A(DWE), .ZN(n_0) + ); + NOR2_X1_LVT i_0_0_163( + .A1(n_0), .A2(reset), .ZN(n_0_0_88) + ); + NOR2_X1_LVT i_0_0_22( + .A1(DWE), .A2(reset), .ZN(n_0_0_11) + ); + AOI22_X1_LVT i_0_0_21( + .A1(DAddr[12]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[12]), .ZN(n_0_0_10) + ); + INV_X1_LVT i_0_0_20( + .A(n_0_0_10), .ZN(n_0_10) + ); + INV_X1_LVT i_0_0_172( + .A(clk), .ZN(n_0_76) + ); + DFF_X1_LVT \mem_addr_reg[10] ( + .CK(n_0_76), .D(n_0_10), .Q(mem_addr[10]), .QN() + ); + AOI22_X1_LVT i_0_0_19( + .A1(DAddr[11]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[11]), .ZN(n_0_0_9) + ); + INV_X1_LVT i_0_0_18( + .A(n_0_0_9), .ZN(n_0_9) + ); + DFF_X1_LVT \mem_addr_reg[9] ( + .CK(n_0_76), .D(n_0_9), .Q(mem_addr[9]), .QN() + ); + AOI22_X1_LVT i_0_0_17( + .A1(DAddr[10]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[10]), .ZN(n_0_0_8) + ); + INV_X1_LVT i_0_0_16( + .A(n_0_0_8), .ZN(n_0_8) + ); + DFF_X1_LVT \mem_addr_reg[8] ( + .CK(n_0_76), .D(n_0_8), .Q(mem_addr[8]), .QN() + ); + AOI22_X1_LVT i_0_0_15( + .A1(DAddr[9]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[9]), .ZN(n_0_0_7) + ); + INV_X1_LVT i_0_0_14( + .A(n_0_0_7), .ZN(n_0_7) + ); + DFF_X1_LVT \mem_addr_reg[7] ( + .CK(n_0_76), .D(n_0_7), .Q(mem_addr[7]), .QN() + ); + AOI22_X1_LVT i_0_0_13( + .A1(DAddr[8]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[8]), .ZN(n_0_0_6) + ); + INV_X1_LVT i_0_0_12( + .A(n_0_0_6), .ZN(n_0_6) + ); + DFF_X1_LVT \mem_addr_reg[6] ( + .CK(n_0_76), .D(n_0_6), .Q(mem_addr[6]), .QN() + ); + AOI22_X1_LVT i_0_0_11( + .A1(DAddr[7]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[7]), .ZN(n_0_0_5) + ); + INV_X1_LVT i_0_0_10( + .A(n_0_0_5), .ZN(n_0_5) + ); + DFF_X1_LVT \mem_addr_reg[5] ( + .CK(n_0_76), .D(n_0_5), .Q(mem_addr[5]), .QN() + ); + AOI22_X1_LVT i_0_0_9( + .A1(DAddr[6]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[6]), .ZN(n_0_0_4) + ); + INV_X1_LVT i_0_0_8( + .A(n_0_0_4), .ZN(n_0_4) + ); + DFF_X1_LVT \mem_addr_reg[4] ( + .CK(n_0_76), .D(n_0_4), .Q(mem_addr[4]), .QN() + ); + AOI22_X1_LVT i_0_0_7( + .A1(DAddr[5]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[5]), .ZN(n_0_0_3) + ); + INV_X1_LVT i_0_0_6( + .A(n_0_0_3), .ZN(n_0_3) + ); + DFF_X1_LVT \mem_addr_reg[3] ( + .CK(n_0_76), .D(n_0_3), .Q(mem_addr[3]), .QN() + ); + AOI22_X1_LVT i_0_0_5( + .A1(DAddr[4]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[4]), .ZN(n_0_0_2) + ); + INV_X1_LVT i_0_0_4( + .A(n_0_0_2), .ZN(n_0_2) + ); + DFF_X1_LVT \mem_addr_reg[2] ( + .CK(n_0_76), .D(n_0_2), .Q(mem_addr[2]), .QN() + ); + AOI22_X1_LVT i_0_0_3( + .A1(DAddr[3]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[3]), .ZN(n_0_0_1) + ); + INV_X1_LVT i_0_0_2( + .A(n_0_0_1), .ZN(n_0_1) + ); + DFF_X1_LVT \mem_addr_reg[1] ( + .CK(n_0_76), .D(n_0_1), .Q(mem_addr[1]), .QN() + ); + AOI22_X1_LVT i_0_0_1( + .A1(DAddr[2]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[2]), .ZN(n_0_0_0) + ); + INV_X1_LVT i_0_0_0( + .A(n_0_0_0), .ZN(n_0_0) + ); + DFF_X1_LVT \mem_addr_reg[0] ( + .CK(n_0_76), .D(n_0_0), .Q(mem_addr[0]), .QN() + ); + NOR2_X1_LVT i_0_0_162( + .A1(DWidth[1]), .A2(DAddr[1]), .ZN(n_0_0_87) + ); + NOR2_X1_LVT i_0_0_158( + .A1(DWidth[0]), .A2(DAddr[0]), .ZN(n_0_0_83) + ); + AND2_X1_LVT i_0_0_157( + .A1(n_0_0_87), .A2(n_0_0_83), .ZN(n_0_0_82) + ); + AND2_X1_LVT i_0_0_156( + .A1(n_0_0_88), .A2(n_0_0_82), .ZN(n_0_0_81) + ); + INV_X1_LVT i_0_0_173( + .A(n_0_0_88), .ZN(n_0_0_95) + ); + INV_X1_LVT i_0_0_169( + .A(DWidth[1]), .ZN(n_0_0_93) + ); + NOR3_X1_LVT i_0_0_155( + .A1(n_0_0_95), .A2(DWidth[0]), .A3(n_0_0_93), .ZN(n_0_0_80) + ); + AOI22_X1_LVT i_0_0_154( + .A1(DWData[7]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[31]), .ZN(n_0_0_79) + ); + NAND2_X1_LVT i_0_0_168( + .A1(DWidth[0]), .A2(DWidth[1]), .ZN(n_0_43) + ); + INV_X1_LVT i_0_0_167( + .A(n_0_43), .ZN(n_0_0_92) + ); + NOR2_X1_LVT i_0_0_160( + .A1(n_0_0_95), .A2(n_0_0_92), .ZN(n_0_0_85) + ); + NAND2_X1_LVT i_0_0_161( + .A1(n_0_0_93), .A2(DAddr[1]), .ZN(n_0_0_86) + ); + NOR2_X1_LVT i_0_0_166( + .A1(DWidth[0]), .A2(DWidth[1]), .ZN(n_0_0_91) + ); + NAND2_X1_LVT i_0_0_164( + .A1(DAddr[0]), .A2(n_0_0_91), .ZN(n_0_0_89) + ); + NAND3_X1_LVT i_0_0_159( + .A1(n_0_0_85), .A2(n_0_0_86), .A3(n_0_0_89), .ZN(n_0_0_84) + ); + INV_X1_LVT i_0_0_170( + .A(DWidth[0]), .ZN(n_0_0_94) + ); + NOR2_X1_LVT i_0_0_153( + .A1(n_0_0_94), .A2(DAddr[1]), .ZN(n_0_0_78) + ); + AND3_X1_LVT i_0_0_152( + .A1(n_0_0_88), .A2(n_0_0_78), .A3(n_0_0_93), .ZN(n_0_0_77) + ); + AOI22_X1_LVT i_0_0_151( + .A1(n_0_0_84), .A2(mem_wdata[31]), .B1(DWData[15]), .B2(n_0_0_77), .ZN(n_0_0_76) + ); + NAND2_X1_LVT i_0_0_150( + .A1(n_0_0_79), .A2(n_0_0_76), .ZN(n_0_75) + ); + DFF_X1_LVT \mem_wdata_reg[31] ( + .CK(n_0_76), .D(n_0_75), .Q(mem_wdata[31]), .QN() + ); + AOI22_X1_LVT i_0_0_149( + .A1(DWData[6]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[30]), .ZN(n_0_0_75) + ); + AOI22_X1_LVT i_0_0_148( + .A1(n_0_0_84), .A2(mem_wdata[30]), .B1(DWData[14]), .B2(n_0_0_77), .ZN(n_0_0_74) + ); + NAND2_X1_LVT i_0_0_147( + .A1(n_0_0_75), .A2(n_0_0_74), .ZN(n_0_74) + ); + DFF_X1_LVT \mem_wdata_reg[30] ( + .CK(n_0_76), .D(n_0_74), .Q(mem_wdata[30]), .QN() + ); + AOI22_X1_LVT i_0_0_146( + .A1(DWData[5]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[29]), .ZN(n_0_0_73) + ); + AOI22_X1_LVT i_0_0_145( + .A1(n_0_0_84), .A2(mem_wdata[29]), .B1(DWData[13]), .B2(n_0_0_77), .ZN(n_0_0_72) + ); + NAND2_X1_LVT i_0_0_144( + .A1(n_0_0_73), .A2(n_0_0_72), .ZN(n_0_73) + ); + DFF_X1_LVT \mem_wdata_reg[29] ( + .CK(n_0_76), .D(n_0_73), .Q(mem_wdata[29]), .QN() + ); + AOI22_X1_LVT i_0_0_143( + .A1(DWData[4]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[28]), .ZN(n_0_0_71) + ); + AOI22_X1_LVT i_0_0_142( + .A1(n_0_0_84), .A2(mem_wdata[28]), .B1(DWData[12]), .B2(n_0_0_77), .ZN(n_0_0_70) + ); + NAND2_X1_LVT i_0_0_141( + .A1(n_0_0_71), .A2(n_0_0_70), .ZN(n_0_72) + ); + DFF_X1_LVT \mem_wdata_reg[28] ( + .CK(n_0_76), .D(n_0_72), .Q(mem_wdata[28]), .QN() + ); + AOI22_X1_LVT i_0_0_140( + .A1(DWData[3]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[27]), .ZN(n_0_0_69) + ); + AOI22_X1_LVT i_0_0_139( + .A1(n_0_0_84), .A2(mem_wdata[27]), .B1(DWData[11]), .B2(n_0_0_77), .ZN(n_0_0_68) + ); + NAND2_X1_LVT i_0_0_138( + .A1(n_0_0_69), .A2(n_0_0_68), .ZN(n_0_71) + ); + DFF_X1_LVT \mem_wdata_reg[27] ( + .CK(n_0_76), .D(n_0_71), .Q(mem_wdata[27]), .QN() + ); + AOI22_X1_LVT i_0_0_137( + .A1(DWData[2]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[26]), .ZN(n_0_0_67) + ); + AOI22_X1_LVT i_0_0_136( + .A1(n_0_0_84), .A2(mem_wdata[26]), .B1(DWData[10]), .B2(n_0_0_77), .ZN(n_0_0_66) + ); + NAND2_X1_LVT i_0_0_135( + .A1(n_0_0_67), .A2(n_0_0_66), .ZN(n_0_70) + ); + DFF_X1_LVT \mem_wdata_reg[26] ( + .CK(n_0_76), .D(n_0_70), .Q(mem_wdata[26]), .QN() + ); + AOI22_X1_LVT i_0_0_134( + .A1(DWData[1]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[25]), .ZN(n_0_0_65) + ); + AOI22_X1_LVT i_0_0_133( + .A1(n_0_0_84), .A2(mem_wdata[25]), .B1(DWData[9]), .B2(n_0_0_77), .ZN(n_0_0_64) + ); + NAND2_X1_LVT i_0_0_132( + .A1(n_0_0_65), .A2(n_0_0_64), .ZN(n_0_69) + ); + DFF_X1_LVT \mem_wdata_reg[25] ( + .CK(n_0_76), .D(n_0_69), .Q(mem_wdata[25]), .QN() + ); + AOI22_X1_LVT i_0_0_131( + .A1(DWData[0]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[24]), .ZN(n_0_0_63) + ); + AOI22_X1_LVT i_0_0_130( + .A1(n_0_0_84), .A2(mem_wdata[24]), .B1(DWData[8]), .B2(n_0_0_77), .ZN(n_0_0_62) + ); + NAND2_X1_LVT i_0_0_129( + .A1(n_0_0_63), .A2(n_0_0_62), .ZN(n_0_68) + ); + DFF_X1_LVT \mem_wdata_reg[24] ( + .CK(n_0_76), .D(n_0_68), .Q(mem_wdata[24]), .QN() + ); + NOR4_X1_LVT i_0_0_127( + .A1(n_0_0_95), .A2(n_0_0_83), .A3(DWidth[1]), .A4(DAddr[1]), .ZN(n_0_0_60) + ); + INV_X1_LVT i_0_0_165( + .A(n_0_0_91), .ZN(n_0_0_90) + ); + OAI211_X1_LVT i_0_0_128( + .A(n_0_0_85), .B(n_0_0_86), .C1(n_0_0_90), .C2(DAddr[0]), .ZN(n_0_0_61) + ); + AOI222_X1_LVT i_0_0_126( + .A1(DWData[7]), .A2(n_0_0_60), .B1(mem_wdata[23]), .B2(n_0_0_61), .C1(DWData[23]), + .C2(n_0_0_80), .ZN(n_0_0_59) + ); + INV_X1_LVT i_0_0_125( + .A(n_0_0_59), .ZN(n_0_67) + ); + DFF_X1_LVT \mem_wdata_reg[23] ( + .CK(n_0_76), .D(n_0_67), .Q(mem_wdata[23]), .QN() + ); + AOI222_X1_LVT i_0_0_124( + .A1(DWData[6]), .A2(n_0_0_60), .B1(mem_wdata[22]), .B2(n_0_0_61), .C1(DWData[22]), + .C2(n_0_0_80), .ZN(n_0_0_58) + ); + INV_X1_LVT i_0_0_123( + .A(n_0_0_58), .ZN(n_0_66) + ); + DFF_X1_LVT \mem_wdata_reg[22] ( + .CK(n_0_76), .D(n_0_66), .Q(mem_wdata[22]), .QN() + ); + AOI222_X1_LVT i_0_0_122( + .A1(DWData[5]), .A2(n_0_0_60), .B1(mem_wdata[21]), .B2(n_0_0_61), .C1(DWData[21]), + .C2(n_0_0_80), .ZN(n_0_0_57) + ); + INV_X1_LVT i_0_0_121( + .A(n_0_0_57), .ZN(n_0_44) + ); + DFF_X1_LVT \mem_wdata_reg[21] ( + .CK(n_0_76), .D(n_0_44), .Q(mem_wdata[21]), .QN() + ); + AOI222_X1_LVT i_0_0_120( + .A1(DWData[4]), .A2(n_0_0_60), .B1(mem_wdata[20]), .B2(n_0_0_61), .C1(DWData[20]), + .C2(n_0_0_80), .ZN(n_0_0_56) + ); + INV_X1_LVT i_0_0_119( + .A(n_0_0_56), .ZN(n_0_45) + ); + DFF_X1_LVT \mem_wdata_reg[20] ( + .CK(n_0_76), .D(n_0_45), .Q(mem_wdata[20]), .QN() + ); + AOI222_X1_LVT i_0_0_118( + .A1(DWData[3]), .A2(n_0_0_60), .B1(mem_wdata[19]), .B2(n_0_0_61), .C1(DWData[19]), + .C2(n_0_0_80), .ZN(n_0_0_55) + ); + INV_X1_LVT i_0_0_117( + .A(n_0_0_55), .ZN(n_0_46) + ); + DFF_X1_LVT \mem_wdata_reg[19] ( + .CK(n_0_76), .D(n_0_46), .Q(mem_wdata[19]), .QN() + ); + AOI222_X1_LVT i_0_0_116( + .A1(DWData[2]), .A2(n_0_0_60), .B1(mem_wdata[18]), .B2(n_0_0_61), .C1(DWData[18]), + .C2(n_0_0_80), .ZN(n_0_0_54) + ); + INV_X1_LVT i_0_0_115( + .A(n_0_0_54), .ZN(n_0_47) + ); + DFF_X1_LVT \mem_wdata_reg[18] ( + .CK(n_0_76), .D(n_0_47), .Q(mem_wdata[18]), .QN() + ); + AOI222_X1_LVT i_0_0_114( + .A1(DWData[1]), .A2(n_0_0_60), .B1(mem_wdata[17]), .B2(n_0_0_61), .C1(DWData[17]), + .C2(n_0_0_80), .ZN(n_0_0_53) + ); + INV_X1_LVT i_0_0_113( + .A(n_0_0_53), .ZN(n_0_48) + ); + DFF_X1_LVT \mem_wdata_reg[17] ( + .CK(n_0_76), .D(n_0_48), .Q(mem_wdata[17]), .QN() + ); + AOI222_X1_LVT i_0_0_112( + .A1(DWData[0]), .A2(n_0_0_60), .B1(mem_wdata[16]), .B2(n_0_0_61), .C1(DWData[16]), + .C2(n_0_0_80), .ZN(n_0_0_52) + ); + INV_X1_LVT i_0_0_111( + .A(n_0_0_52), .ZN(n_0_49) + ); + DFF_X1_LVT \mem_wdata_reg[16] ( + .CK(n_0_76), .D(n_0_49), .Q(mem_wdata[16]), .QN() + ); + NOR4_X1_LVT i_0_0_110( + .A1(n_0_0_95), .A2(n_0_0_87), .A3(n_0_0_92), .A4(n_0_0_91), .ZN(n_0_0_51) + ); + NOR3_X1_LVT i_0_0_109( + .A1(n_0_0_86), .A2(DAddr[0]), .A3(DWidth[0]), .ZN(n_0_0_50) + ); + AND2_X1_LVT i_0_0_108( + .A1(n_0_0_88), .A2(n_0_0_50), .ZN(n_0_0_49) + ); + OAI211_X1_LVT i_0_0_107( + .A(n_0_0_85), .B(n_0_0_89), .C1(DAddr[1]), .C2(DWidth[1]), .ZN(n_0_0_48) + ); + AOI222_X1_LVT i_0_0_106( + .A1(DWData[15]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[7]), .C1(n_0_0_48), + .C2(mem_wdata[15]), .ZN(n_0_0_47) + ); + INV_X1_LVT i_0_0_105( + .A(n_0_0_47), .ZN(n_0_50) + ); + DFF_X1_LVT \mem_wdata_reg[15] ( + .CK(n_0_76), .D(n_0_50), .Q(mem_wdata[15]), .QN() + ); + AOI222_X1_LVT i_0_0_104( + .A1(DWData[14]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[6]), .C1(n_0_0_48), + .C2(mem_wdata[14]), .ZN(n_0_0_46) + ); + INV_X1_LVT i_0_0_103( + .A(n_0_0_46), .ZN(n_0_51) + ); + DFF_X1_LVT \mem_wdata_reg[14] ( + .CK(n_0_76), .D(n_0_51), .Q(mem_wdata[14]), .QN() + ); + AOI222_X1_LVT i_0_0_102( + .A1(DWData[13]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[5]), .C1(n_0_0_48), + .C2(mem_wdata[13]), .ZN(n_0_0_45) + ); + INV_X1_LVT i_0_0_101( + .A(n_0_0_45), .ZN(n_0_52) + ); + DFF_X1_LVT \mem_wdata_reg[13] ( + .CK(n_0_76), .D(n_0_52), .Q(mem_wdata[13]), .QN() + ); + AOI222_X1_LVT i_0_0_100( + .A1(DWData[12]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[4]), .C1(n_0_0_48), + .C2(mem_wdata[12]), .ZN(n_0_0_44) + ); + INV_X1_LVT i_0_0_99( + .A(n_0_0_44), .ZN(n_0_53) + ); + DFF_X1_LVT \mem_wdata_reg[12] ( + .CK(n_0_76), .D(n_0_53), .Q(mem_wdata[12]), .QN() + ); + AOI222_X1_LVT i_0_0_98( + .A1(DWData[11]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[3]), .C1(n_0_0_48), + .C2(mem_wdata[11]), .ZN(n_0_0_43) + ); + INV_X1_LVT i_0_0_97( + .A(n_0_0_43), .ZN(n_0_54) + ); + DFF_X1_LVT \mem_wdata_reg[11] ( + .CK(n_0_76), .D(n_0_54), .Q(mem_wdata[11]), .QN() + ); + AOI222_X1_LVT i_0_0_96( + .A1(DWData[10]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[2]), .C1(n_0_0_48), + .C2(mem_wdata[10]), .ZN(n_0_0_42) + ); + INV_X1_LVT i_0_0_95( + .A(n_0_0_42), .ZN(n_0_55) + ); + DFF_X1_LVT \mem_wdata_reg[10] ( + .CK(n_0_76), .D(n_0_55), .Q(mem_wdata[10]), .QN() + ); + AOI222_X1_LVT i_0_0_94( + .A1(DWData[9]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[1]), .C1(n_0_0_48), + .C2(mem_wdata[9]), .ZN(n_0_0_41) + ); + INV_X1_LVT i_0_0_93( + .A(n_0_0_41), .ZN(n_0_56) + ); + DFF_X1_LVT \mem_wdata_reg[9] ( + .CK(n_0_76), .D(n_0_56), .Q(mem_wdata[9]), .QN() + ); + AOI222_X1_LVT i_0_0_92( + .A1(DWData[8]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[0]), .C1(n_0_0_48), + .C2(mem_wdata[8]), .ZN(n_0_0_40) + ); + INV_X1_LVT i_0_0_91( + .A(n_0_0_40), .ZN(n_0_57) + ); + DFF_X1_LVT \mem_wdata_reg[8] ( + .CK(n_0_76), .D(n_0_57), .Q(mem_wdata[8]), .QN() + ); + AOI21_X1_LVT i_0_0_90( + .A(n_0_0_87), .B1(n_0_0_83), .B2(n_0_0_93), .ZN(n_0_0_39) + ); + NAND2_X1_LVT i_0_0_89( + .A1(n_0_0_85), .A2(n_0_0_39), .ZN(n_0_0_38) + ); + MUX2_X1_LVT i_0_0_88( + .A(DWData[7]), .B(mem_wdata[7]), .S(n_0_0_38), .Z(n_0_58) + ); + DFF_X1_LVT \mem_wdata_reg[7] ( + .CK(n_0_76), .D(n_0_58), .Q(mem_wdata[7]), .QN() + ); + MUX2_X1_LVT i_0_0_87( + .A(DWData[6]), .B(mem_wdata[6]), .S(n_0_0_38), .Z(n_0_59) + ); + DFF_X1_LVT \mem_wdata_reg[6] ( + .CK(n_0_76), .D(n_0_59), .Q(mem_wdata[6]), .QN() + ); + MUX2_X1_LVT i_0_0_86( + .A(DWData[5]), .B(mem_wdata[5]), .S(n_0_0_38), .Z(n_0_60) + ); + DFF_X1_LVT \mem_wdata_reg[5] ( + .CK(n_0_76), .D(n_0_60), .Q(mem_wdata[5]), .QN() + ); + MUX2_X1_LVT i_0_0_85( + .A(DWData[4]), .B(mem_wdata[4]), .S(n_0_0_38), .Z(n_0_61) + ); + DFF_X1_LVT \mem_wdata_reg[4] ( + .CK(n_0_76), .D(n_0_61), .Q(mem_wdata[4]), .QN() + ); + MUX2_X1_LVT i_0_0_84( + .A(DWData[3]), .B(mem_wdata[3]), .S(n_0_0_38), .Z(n_0_62) + ); + DFF_X1_LVT \mem_wdata_reg[3] ( + .CK(n_0_76), .D(n_0_62), .Q(mem_wdata[3]), .QN() + ); + MUX2_X1_LVT i_0_0_83( + .A(DWData[2]), .B(mem_wdata[2]), .S(n_0_0_38), .Z(n_0_63) + ); + DFF_X1_LVT \mem_wdata_reg[2] ( + .CK(n_0_76), .D(n_0_63), .Q(mem_wdata[2]), .QN() + ); + MUX2_X1_LVT i_0_0_82( + .A(DWData[1]), .B(mem_wdata[1]), .S(n_0_0_38), .Z(n_0_64) + ); + DFF_X1_LVT \mem_wdata_reg[1] ( + .CK(n_0_76), .D(n_0_64), .Q(mem_wdata[1]), .QN() + ); + MUX2_X1_LVT i_0_0_81( + .A(DWData[0]), .B(mem_wdata[0]), .S(n_0_0_38), .Z(n_0_65) + ); + DFF_X1_LVT \mem_wdata_reg[0] ( + .CK(n_0_76), .D(n_0_65), .Q(mem_wdata[0]), .QN() + ); + MemGen_32_11 RAM( + .chip_en(), .clock(clk), .addr(mem_addr), .rd_data(mem_rdata), .rd_en(n_0), + .wr_en(DWE), .wr_data(mem_wdata) + ); + DFF_X1_LVT \drTmp_reg[31] ( + .CK(n_0_76), .D(mem_rdata[31]), .Q(drTmp[31]), .QN() + ); + AND2_X1_LVT i_0_0_80( + .A1(DWidth[1]), .A2(drTmp[31]), .ZN(n_0_42) + ); + DLH_X1_LVT \DRData[31] ( + .D(n_0_42), .G(n_0_43), .Q(DRData[31]) + ); + DFF_X1_LVT \drTmp_reg[30] ( + .CK(n_0_76), .D(mem_rdata[30]), .Q(drTmp[30]), .QN() + ); + AND2_X1_LVT i_0_0_79( + .A1(DWidth[1]), .A2(drTmp[30]), .ZN(n_0_41) + ); + DLH_X1_LVT \DRData[30] ( + .D(n_0_41), .G(n_0_43), .Q(DRData[30]) + ); + DFF_X1_LVT \drTmp_reg[29] ( + .CK(n_0_76), .D(mem_rdata[29]), .Q(drTmp[29]), .QN() + ); + AND2_X1_LVT i_0_0_78( + .A1(DWidth[1]), .A2(drTmp[29]), .ZN(n_0_40) + ); + DLH_X1_LVT \DRData[29] ( + .D(n_0_40), .G(n_0_43), .Q(DRData[29]) + ); + DFF_X1_LVT \drTmp_reg[28] ( + .CK(n_0_76), .D(mem_rdata[28]), .Q(drTmp[28]), .QN() + ); + AND2_X1_LVT i_0_0_77( + .A1(DWidth[1]), .A2(drTmp[28]), .ZN(n_0_39) + ); + DLH_X1_LVT \DRData[28] ( + .D(n_0_39), .G(n_0_43), .Q(DRData[28]) + ); + DFF_X1_LVT \drTmp_reg[27] ( + .CK(n_0_76), .D(mem_rdata[27]), .Q(drTmp[27]), .QN() + ); + AND2_X1_LVT i_0_0_76( + .A1(DWidth[1]), .A2(drTmp[27]), .ZN(n_0_38) + ); + DLH_X1_LVT \DRData[27] ( + .D(n_0_38), .G(n_0_43), .Q(DRData[27]) + ); + DFF_X1_LVT \drTmp_reg[26] ( + .CK(n_0_76), .D(mem_rdata[26]), .Q(drTmp[26]), .QN() + ); + AND2_X1_LVT i_0_0_75( + .A1(DWidth[1]), .A2(drTmp[26]), .ZN(n_0_37) + ); + DLH_X1_LVT \DRData[26] ( + .D(n_0_37), .G(n_0_43), .Q(DRData[26]) + ); + DFF_X1_LVT \drTmp_reg[25] ( + .CK(n_0_76), .D(mem_rdata[25]), .Q(drTmp[25]), .QN() + ); + AND2_X1_LVT i_0_0_74( + .A1(DWidth[1]), .A2(drTmp[25]), .ZN(n_0_36) + ); + DLH_X1_LVT \DRData[25] ( + .D(n_0_36), .G(n_0_43), .Q(DRData[25]) + ); + DFF_X1_LVT \drTmp_reg[24] ( + .CK(n_0_76), .D(mem_rdata[24]), .Q(drTmp[24]), .QN() + ); + AND2_X1_LVT i_0_0_73( + .A1(DWidth[1]), .A2(drTmp[24]), .ZN(n_0_35) + ); + DLH_X1_LVT \DRData[24] ( + .D(n_0_35), .G(n_0_43), .Q(DRData[24]) + ); + DFF_X1_LVT \drTmp_reg[23] ( + .CK(n_0_76), .D(mem_rdata[23]), .Q(drTmp[23]), .QN() + ); + AND2_X1_LVT i_0_0_72( + .A1(DWidth[1]), .A2(drTmp[23]), .ZN(n_0_34) + ); + DLH_X1_LVT \DRData[23] ( + .D(n_0_34), .G(n_0_43), .Q(DRData[23]) + ); + DFF_X1_LVT \drTmp_reg[22] ( + .CK(n_0_76), .D(mem_rdata[22]), .Q(drTmp[22]), .QN() + ); + AND2_X1_LVT i_0_0_71( + .A1(DWidth[1]), .A2(drTmp[22]), .ZN(n_0_33) + ); + DLH_X1_LVT \DRData[22] ( + .D(n_0_33), .G(n_0_43), .Q(DRData[22]) + ); + DFF_X1_LVT \drTmp_reg[21] ( + .CK(n_0_76), .D(mem_rdata[21]), .Q(drTmp[21]), .QN() + ); + AND2_X1_LVT i_0_0_70( + .A1(DWidth[1]), .A2(drTmp[21]), .ZN(n_0_32) + ); + DLH_X1_LVT \DRData[21] ( + .D(n_0_32), .G(n_0_43), .Q(DRData[21]) + ); + DFF_X1_LVT \drTmp_reg[20] ( + .CK(n_0_76), .D(mem_rdata[20]), .Q(drTmp[20]), .QN() + ); + AND2_X1_LVT i_0_0_69( + .A1(DWidth[1]), .A2(drTmp[20]), .ZN(n_0_31) + ); + DLH_X1_LVT \DRData[20] ( + .D(n_0_31), .G(n_0_43), .Q(DRData[20]) + ); + DFF_X1_LVT \drTmp_reg[19] ( + .CK(n_0_76), .D(mem_rdata[19]), .Q(drTmp[19]), .QN() + ); + AND2_X1_LVT i_0_0_68( + .A1(DWidth[1]), .A2(drTmp[19]), .ZN(n_0_30) + ); + DLH_X1_LVT \DRData[19] ( + .D(n_0_30), .G(n_0_43), .Q(DRData[19]) + ); + DFF_X1_LVT \drTmp_reg[18] ( + .CK(n_0_76), .D(mem_rdata[18]), .Q(drTmp[18]), .QN() + ); + AND2_X1_LVT i_0_0_67( + .A1(DWidth[1]), .A2(drTmp[18]), .ZN(n_0_29) + ); + DLH_X1_LVT \DRData[18] ( + .D(n_0_29), .G(n_0_43), .Q(DRData[18]) + ); + DFF_X1_LVT \drTmp_reg[17] ( + .CK(n_0_76), .D(mem_rdata[17]), .Q(drTmp[17]), .QN() + ); + AND2_X1_LVT i_0_0_66( + .A1(DWidth[1]), .A2(drTmp[17]), .ZN(n_0_28) + ); + DLH_X1_LVT \DRData[17] ( + .D(n_0_28), .G(n_0_43), .Q(DRData[17]) + ); + DFF_X1_LVT \drTmp_reg[16] ( + .CK(n_0_76), .D(mem_rdata[16]), .Q(drTmp[16]), .QN() + ); + AND2_X1_LVT i_0_0_65( + .A1(DWidth[1]), .A2(drTmp[16]), .ZN(n_0_27) + ); + DLH_X1_LVT \DRData[16] ( + .D(n_0_27), .G(n_0_43), .Q(DRData[16]) + ); + NOR2_X1_LVT i_0_0_64( + .A1(n_0_0_91), .A2(n_0_0_87), .ZN(n_0_0_37) + ); + DFF_X1_LVT \drTmp_reg[15] ( + .CK(n_0_76), .D(mem_rdata[15]), .Q(drTmp[15]), .QN() + ); + AOI22_X1_LVT i_0_0_63( + .A1(drTmp[31]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[15]), .ZN(n_0_0_36) + ); + INV_X1_LVT i_0_0_62( + .A(n_0_0_36), .ZN(n_0_26) + ); + DLH_X1_LVT \DRData[15] ( + .D(n_0_26), .G(n_0_43), .Q(DRData[15]) + ); + DFF_X1_LVT \drTmp_reg[14] ( + .CK(n_0_76), .D(mem_rdata[14]), .Q(drTmp[14]), .QN() + ); + AOI22_X1_LVT i_0_0_61( + .A1(drTmp[30]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[14]), .ZN(n_0_0_35) + ); + INV_X1_LVT i_0_0_60( + .A(n_0_0_35), .ZN(n_0_25) + ); + DLH_X1_LVT \DRData[14] ( + .D(n_0_25), .G(n_0_43), .Q(DRData[14]) + ); + DFF_X1_LVT \drTmp_reg[13] ( + .CK(n_0_76), .D(mem_rdata[13]), .Q(drTmp[13]), .QN() + ); + AOI22_X1_LVT i_0_0_59( + .A1(drTmp[29]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[13]), .ZN(n_0_0_34) + ); + INV_X1_LVT i_0_0_58( + .A(n_0_0_34), .ZN(n_0_24) + ); + DLH_X1_LVT \DRData[13] ( + .D(n_0_24), .G(n_0_43), .Q(DRData[13]) + ); + DFF_X1_LVT \drTmp_reg[12] ( + .CK(n_0_76), .D(mem_rdata[12]), .Q(drTmp[12]), .QN() + ); + AOI22_X1_LVT i_0_0_57( + .A1(drTmp[28]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[12]), .ZN(n_0_0_33) + ); + INV_X1_LVT i_0_0_56( + .A(n_0_0_33), .ZN(n_0_23) + ); + DLH_X1_LVT \DRData[12] ( + .D(n_0_23), .G(n_0_43), .Q(DRData[12]) + ); + DFF_X1_LVT \drTmp_reg[11] ( + .CK(n_0_76), .D(mem_rdata[11]), .Q(drTmp[11]), .QN() + ); + AOI22_X1_LVT i_0_0_55( + .A1(drTmp[27]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[11]), .ZN(n_0_0_32) + ); + INV_X1_LVT i_0_0_54( + .A(n_0_0_32), .ZN(n_0_22) + ); + DLH_X1_LVT \DRData[11] ( + .D(n_0_22), .G(n_0_43), .Q(DRData[11]) + ); + DFF_X1_LVT \drTmp_reg[10] ( + .CK(n_0_76), .D(mem_rdata[10]), .Q(drTmp[10]), .QN() + ); + AOI22_X1_LVT i_0_0_53( + .A1(drTmp[26]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[10]), .ZN(n_0_0_31) + ); + INV_X1_LVT i_0_0_52( + .A(n_0_0_31), .ZN(n_0_21) + ); + DLH_X1_LVT \DRData[10] ( + .D(n_0_21), .G(n_0_43), .Q(DRData[10]) + ); + DFF_X1_LVT \drTmp_reg[9] ( + .CK(n_0_76), .D(mem_rdata[9]), .Q(drTmp[9]), .QN() + ); + AOI22_X1_LVT i_0_0_51( + .A1(drTmp[25]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[9]), .ZN(n_0_0_30) + ); + INV_X1_LVT i_0_0_50( + .A(n_0_0_30), .ZN(n_0_20) + ); + DLH_X1_LVT \DRData[9] ( + .D(n_0_20), .G(n_0_43), .Q(DRData[9]) + ); + DFF_X1_LVT \drTmp_reg[8] ( + .CK(n_0_76), .D(mem_rdata[8]), .Q(drTmp[8]), .QN() + ); + AOI22_X1_LVT i_0_0_49( + .A1(drTmp[24]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[8]), .ZN(n_0_0_29) + ); + INV_X1_LVT i_0_0_48( + .A(n_0_0_29), .ZN(n_0_19) + ); + DLH_X1_LVT \DRData[8] ( + .D(n_0_19), .G(n_0_43), .Q(DRData[8]) + ); + AOI22_X1_LVT i_0_0_46( + .A1(drTmp[31]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[15]), .ZN(n_0_0_27) + ); + AOI211_X1_LVT i_0_0_47( + .A(DAddr[1]), .B(n_0_0_83), .C1(n_0_0_94), .C2(DWidth[1]), .ZN(n_0_0_28) + ); + DFF_X1_LVT \drTmp_reg[7] ( + .CK(n_0_76), .D(mem_rdata[7]), .Q(drTmp[7]), .QN() + ); + AOI22_X1_LVT i_0_0_45( + .A1(drTmp[23]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[7]), .ZN(n_0_0_26) + ); + NAND2_X1_LVT i_0_0_44( + .A1(n_0_0_27), .A2(n_0_0_26), .ZN(n_0_18) + ); + DLH_X1_LVT \DRData[7] ( + .D(n_0_18), .G(n_0_43), .Q(DRData[7]) + ); + AOI22_X1_LVT i_0_0_43( + .A1(drTmp[30]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[14]), .ZN(n_0_0_25) + ); + DFF_X1_LVT \drTmp_reg[6] ( + .CK(n_0_76), .D(mem_rdata[6]), .Q(drTmp[6]), .QN() + ); + AOI22_X1_LVT i_0_0_42( + .A1(drTmp[22]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[6]), .ZN(n_0_0_24) + ); + NAND2_X1_LVT i_0_0_41( + .A1(n_0_0_25), .A2(n_0_0_24), .ZN(n_0_17) + ); + DLH_X1_LVT \DRData[6] ( + .D(n_0_17), .G(n_0_43), .Q(DRData[6]) + ); + AOI22_X1_LVT i_0_0_40( + .A1(drTmp[29]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[13]), .ZN(n_0_0_23) + ); + DFF_X1_LVT \drTmp_reg[5] ( + .CK(n_0_76), .D(mem_rdata[5]), .Q(drTmp[5]), .QN() + ); + AOI22_X1_LVT i_0_0_39( + .A1(drTmp[21]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[5]), .ZN(n_0_0_22) + ); + NAND2_X1_LVT i_0_0_38( + .A1(n_0_0_23), .A2(n_0_0_22), .ZN(n_0_16) + ); + DLH_X1_LVT \DRData[5] ( + .D(n_0_16), .G(n_0_43), .Q(DRData[5]) + ); + AOI22_X1_LVT i_0_0_37( + .A1(drTmp[28]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[12]), .ZN(n_0_0_21) + ); + DFF_X1_LVT \drTmp_reg[4] ( + .CK(n_0_76), .D(mem_rdata[4]), .Q(drTmp[4]), .QN() + ); + AOI22_X1_LVT i_0_0_36( + .A1(drTmp[20]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[4]), .ZN(n_0_0_20) + ); + NAND2_X1_LVT i_0_0_35( + .A1(n_0_0_21), .A2(n_0_0_20), .ZN(n_0_15) + ); + DLH_X1_LVT \DRData[4] ( + .D(n_0_15), .G(n_0_43), .Q(DRData[4]) + ); + AOI22_X1_LVT i_0_0_34( + .A1(drTmp[27]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[11]), .ZN(n_0_0_19) + ); + DFF_X1_LVT \drTmp_reg[3] ( + .CK(n_0_76), .D(mem_rdata[3]), .Q(drTmp[3]), .QN() + ); + AOI22_X1_LVT i_0_0_33( + .A1(drTmp[19]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[3]), .ZN(n_0_0_18) + ); + NAND2_X1_LVT i_0_0_32( + .A1(n_0_0_19), .A2(n_0_0_18), .ZN(n_0_14) + ); + DLH_X1_LVT \DRData[3] ( + .D(n_0_14), .G(n_0_43), .Q(DRData[3]) + ); + AOI22_X1_LVT i_0_0_31( + .A1(drTmp[26]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[10]), .ZN(n_0_0_17) + ); + DFF_X1_LVT \drTmp_reg[2] ( + .CK(n_0_76), .D(mem_rdata[2]), .Q(drTmp[2]), .QN() + ); + AOI22_X1_LVT i_0_0_30( + .A1(drTmp[18]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[2]), .ZN(n_0_0_16) + ); + NAND2_X1_LVT i_0_0_29( + .A1(n_0_0_17), .A2(n_0_0_16), .ZN(n_0_13) + ); + DLH_X1_LVT \DRData[2] ( + .D(n_0_13), .G(n_0_43), .Q(DRData[2]) + ); + AOI22_X1_LVT i_0_0_28( + .A1(drTmp[25]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[9]), .ZN(n_0_0_15) + ); + DFF_X1_LVT \drTmp_reg[1] ( + .CK(n_0_76), .D(mem_rdata[1]), .Q(drTmp[1]), .QN() + ); + AOI22_X1_LVT i_0_0_27( + .A1(drTmp[17]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[1]), .ZN(n_0_0_14) + ); + NAND2_X1_LVT i_0_0_26( + .A1(n_0_0_15), .A2(n_0_0_14), .ZN(n_0_12) + ); + DLH_X1_LVT \DRData[1] ( + .D(n_0_12), .G(n_0_43), .Q(DRData[1]) + ); + AOI22_X1_LVT i_0_0_25( + .A1(drTmp[24]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[8]), .ZN(n_0_0_13) + ); + DFF_X1_LVT \drTmp_reg[0] ( + .CK(n_0_76), .D(mem_rdata[0]), .Q(drTmp[0]), .QN() + ); + AOI22_X1_LVT i_0_0_24( + .A1(drTmp[16]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[0]), .ZN(n_0_0_12) + ); + NAND2_X1_LVT i_0_0_23( + .A1(n_0_0_13), .A2(n_0_0_12), .ZN(n_0_11) + ); + DLH_X1_LVT \DRData[0] ( + .D(n_0_11), .G(n_0_43), .Q(DRData[0]) + ); + DFF_X1_LVT \IRData_reg[31] ( + .CK(clk), .D(mem_rdata[31]), .Q(IRData[31]), .QN() + ); + DFF_X1_LVT \IRData_reg[30] ( + .CK(clk), .D(mem_rdata[30]), .Q(IRData[30]), .QN() + ); + DFF_X1_LVT \IRData_reg[29] ( + .CK(clk), .D(mem_rdata[29]), .Q(IRData[29]), .QN() + ); + DFF_X1_LVT \IRData_reg[28] ( + .CK(clk), .D(mem_rdata[28]), .Q(IRData[28]), .QN() + ); + DFF_X1_LVT \IRData_reg[27] ( + .CK(clk), .D(mem_rdata[27]), .Q(IRData[27]), .QN() + ); + DFF_X1_LVT \IRData_reg[26] ( + .CK(clk), .D(mem_rdata[26]), .Q(IRData[26]), .QN() + ); + DFF_X1_LVT \IRData_reg[25] ( + .CK(clk), .D(mem_rdata[25]), .Q(IRData[25]), .QN() + ); + DFF_X1_LVT \IRData_reg[24] ( + .CK(clk), .D(mem_rdata[24]), .Q(IRData[24]), .QN() + ); + DFF_X1_LVT \IRData_reg[23] ( + .CK(clk), .D(mem_rdata[23]), .Q(IRData[23]), .QN() + ); + DFF_X1_LVT \IRData_reg[22] ( + .CK(clk), .D(mem_rdata[22]), .Q(IRData[22]), .QN() + ); + DFF_X1_LVT \IRData_reg[21] ( + .CK(clk), .D(mem_rdata[21]), .Q(IRData[21]), .QN() + ); + DFF_X1_LVT \IRData_reg[20] ( + .CK(clk), .D(mem_rdata[20]), .Q(IRData[20]), .QN() + ); + DFF_X1_LVT \IRData_reg[19] ( + .CK(clk), .D(mem_rdata[19]), .Q(IRData[19]), .QN() + ); + DFF_X1_LVT \IRData_reg[18] ( + .CK(clk), .D(mem_rdata[18]), .Q(IRData[18]), .QN() + ); + DFF_X1_LVT \IRData_reg[17] ( + .CK(clk), .D(mem_rdata[17]), .Q(IRData[17]), .QN() + ); + DFF_X1_LVT \IRData_reg[16] ( + .CK(clk), .D(mem_rdata[16]), .Q(IRData[16]), .QN() + ); + DFF_X1_LVT \IRData_reg[15] ( + .CK(clk), .D(mem_rdata[15]), .Q(IRData[15]), .QN() + ); + DFF_X1_LVT \IRData_reg[14] ( + .CK(clk), .D(mem_rdata[14]), .Q(IRData[14]), .QN() + ); + DFF_X1_LVT \IRData_reg[13] ( + .CK(clk), .D(mem_rdata[13]), .Q(IRData[13]), .QN() + ); + DFF_X1_LVT \IRData_reg[12] ( + .CK(clk), .D(mem_rdata[12]), .Q(IRData[12]), .QN() + ); + DFF_X1_LVT \IRData_reg[11] ( + .CK(clk), .D(mem_rdata[11]), .Q(IRData[11]), .QN() + ); + DFF_X1_LVT \IRData_reg[10] ( + .CK(clk), .D(mem_rdata[10]), .Q(IRData[10]), .QN() + ); + DFF_X1_LVT \IRData_reg[9] ( + .CK(clk), .D(mem_rdata[9]), .Q(IRData[9]), .QN() + ); + DFF_X1_LVT \IRData_reg[8] ( + .CK(clk), .D(mem_rdata[8]), .Q(IRData[8]), .QN() + ); + DFF_X1_LVT \IRData_reg[7] ( + .CK(clk), .D(mem_rdata[7]), .Q(IRData[7]), .QN() + ); + DFF_X1_LVT \IRData_reg[6] ( + .CK(clk), .D(mem_rdata[6]), .Q(IRData[6]), .QN() + ); + DFF_X1_LVT \IRData_reg[5] ( + .CK(clk), .D(mem_rdata[5]), .Q(IRData[5]), .QN() + ); + DFF_X1_LVT \IRData_reg[4] ( + .CK(clk), .D(mem_rdata[4]), .Q(IRData[4]), .QN() + ); + DFF_X1_LVT \IRData_reg[3] ( + .CK(clk), .D(mem_rdata[3]), .Q(IRData[3]), .QN() + ); + DFF_X1_LVT \IRData_reg[2] ( + .CK(clk), .D(mem_rdata[2]), .Q(IRData[2]), .QN() + ); + DFF_X1_LVT \IRData_reg[1] ( + .CK(clk), .D(mem_rdata[1]), .Q(IRData[1]), .QN() + ); + DFF_X1_LVT \IRData_reg[0] ( + .CK(clk), .D(mem_rdata[0]), .Q(IRData[0]), .QN() + ); +endmodule + +module reg_file(Rs1, Rs2, Rd, RRs1, RRs2, WRd, WrReg, reset, clk, dftIn, ts_intno31, + ts_no1050, ts_no1051, ts_no1053, ts_no1054, ts_extsi1226, ts_extsi1227, + ts_extsi1228); + input [31:0] WRd; + input [4:0] Rs1, Rs2, Rd; + input WrReg, reset, clk, dftIn, ts_extsi1227, ts_extsi1228, ts_intno31, + ts_extsi1226; + output [31:0] RRs1, RRs2; + output ts_no1050, ts_no1051, ts_no1053, ts_no1054; + + wire [31:0] registers_1__ap, registers_2__ap, registers_3__ap, + registers_4__ap, registers_5__ap, registers_6__ap, + registers_7__ap, registers_8__ap, registers_9__ap, + registers_10__ap, registers_11__ap, registers_12__ap, + registers_13__ap, registers_14__ap, registers_15__ap, + registers_16__ap, registers_17__ap, registers_18__ap, + registers_19__ap, registers_20__ap, registers_21__ap, + registers_22__ap, registers_23__ap, registers_24__ap, + registers_25__ap, registers_26__ap, registers_27__ap, + registers_28__ap, registers_29__ap, registers_30__ap, + registers_31__ap, registers; + wire n_0_0, n_0_32, n_0_33, n_0_34, n_0_35, n_0_36, n_0_37, n_0_38, n_0_39, + n_0_40, n_0_41, n_0_42, n_0_43, n_0_44, n_0_45, n_0_46, n_0_47, n_0_48, + n_0_49, n_0_50, n_0_51, n_0_52, n_0_53, n_0_54, n_0_55, n_0_56, n_0_57, + n_0_58, n_0_59, n_0_60, n_0_61, n_0_31, n_0_30, n_0_29, n_0_28, n_0_27, + n_0_26, n_0_25, n_0_24, n_0_0_0, n_0_0_1, n_0_23, n_0_22, n_0_21, + n_0_20, n_0_19, n_0_18, n_0_17, n_0_16, n_0_0_2, n_0_0_3, n_0_15, + n_0_14, n_0_13, n_0_12, n_0_11, n_0_10, n_0_9, n_0_8, n_0_0_4, n_0_0_5, + n_0_7, n_0_0_6, n_0_6, n_0_0_7, n_0_5, n_0_0_8, n_0_4, n_0_0_9, + n_0_0_10, n_0_3, n_0_0_11, n_0_2, n_0_0_12, n_0_1, n_0_0_13, n_0_0_14, + n_0_0_15, n_0_0_16, n_0_0_17, n_0_0_18, n_0_0_19, n_0_0_20, n_1_0_0, + n_1_0_1, n_1_0_2, n_1_0_3, n_1_0_4, n_1_0_5, n_1_0_6, n_1_0_7, n_1_0_8, + n_1_0_9, n_1_0_10, n_1_0_11, n_1_0_12, n_1_0_13, n_1_0_14, n_1_0_15, + n_1_0_16, n_1_0_17, n_1_0_18, n_1_0_19, n_1_0_20, n_1_0_21, n_1_0_22, + n_1_0_23, n_1_0_24, n_1_0_25, n_1_0_26, n_1_0_27, n_1_0_28, n_1_0_29, + n_1_0_30, n_1_0_31, n_1_0_32, n_1_0_33, n_1_0_34, n_1_0_35, n_1_0_36, + n_1_0_37, n_1_0_38, n_1_0_39, n_1_0_40, n_1_0_41, n_1_0_42, n_1_0_43, + n_1_0_44, n_1_0_45, n_1_0_46, n_1_0_47, n_1_0_48, n_1_0_49, n_1_0_50, + n_1_0_51, n_1_0_52, n_1_0_53, n_1_0_54, n_1_0_55, n_1_0_56, n_1_0_57, + n_1_0_58, n_1_0_59, n_1_0_60, n_1_0_61, n_1_0_62, n_1_0_63, n_1_0_64, + n_1_0_65, n_1_0_66, n_1_0_67, n_1_0_68, n_1_0_69, n_1_0_70, n_1_0_71, + n_1_0_72, n_1_0_73, n_1_0_74, n_1_0_75, n_1_0_76, n_1_0_77, n_1_0_78, + n_1_0_79, n_1_0_80, n_1_0_81, n_1_0_82, n_1_0_83, n_1_0_84, n_1_0_85, + n_1_0_86, n_1_0_87, n_1_0_88, n_1_0_89, n_1_0_90, n_1_0_91, n_1_0_92, + n_1_0_93, n_1_0_94, n_1_0_95, n_1_0_96, n_1_0_97, n_1_0_98, n_1_0_99, + n_1_0_100, n_1_0_101, n_1_0_102, n_1_0_103, n_1_0_104, n_1_0_105, + n_1_0_106, n_1_0_107, n_1_0_108, n_1_0_109, n_1_0_110, n_1_0_111, + n_1_0_112, n_1_0_113, n_1_0_114, n_1_0_115, n_1_0_116, n_1_0_117, + n_1_0_118, n_1_0_119, n_1_0_120, n_1_0_121, n_1_0_122, n_1_0_123, + n_1_0_124, n_1_0_125, n_1_0_126, n_1_0_127, n_1_0_128, n_1_0_129, + n_1_0_130, n_1_0_131, n_1_0_132, n_1_0_133, n_1_0_134, n_1_0_135, + n_1_0_136, n_1_0_137, n_1_0_138, n_1_0_139, n_1_0_140, n_1_0_141, + n_1_0_142, n_1_0_143, n_1_0_144, n_1_0_145, n_1_0_146, n_1_0_147, + n_1_0_148, n_1_0_149, n_1_0_150, n_1_0_151, n_1_0_152, n_1_0_153, + n_1_0_154, n_1_0_155, n_1_0_156, n_1_0_157, n_1_0_158, n_1_0_159, + n_1_0_160, n_1_0_161, n_1_0_162, n_1_0_163, n_1_0_164, n_1_0_165, + n_1_0_166, n_1_0_167, n_1_0_168, n_1_0_169, n_1_0_170, n_1_0_171, + n_1_0_172, n_1_0_173, n_1_0_174, n_1_0_175, n_1_0_176, n_1_0_177, + n_1_0_178, n_1_0_179, n_1_0_180, n_1_0_181, n_1_0_182, n_1_0_183, + n_1_0_184, n_1_0_185, n_1_0_186, n_1_0_187, n_1_0_188, n_1_0_189, + n_1_0_190, n_1_0_191, n_1_0_192, n_1_0_193, n_1_0_194, n_1_0_195, + n_1_0_196, n_1_0_197, n_1_0_198, n_1_0_199, n_1_0_200, n_1_0_201, + n_1_0_202, n_1_0_203, n_1_0_204, n_1_0_205, n_1_0_206, n_1_0_207, + n_1_0_208, n_1_0_209, n_1_0_210, n_1_0_211, n_1_0_212, n_1_0_213, + n_1_0_214, n_1_0_215, n_1_0_216, n_1_0_217, n_1_0_218, n_1_0_219, + n_1_0_220, n_1_0_221, n_1_0_222, n_1_0_223, n_1_0_224, n_1_0_225, + n_1_0_226, n_1_0_227, n_1_0_228, n_1_0_229, n_1_0_230, n_1_0_231, + n_1_0_232, n_1_0_233, n_1_0_234, n_1_0_235, n_1_0_236, n_1_0_237, + n_1_0_238, n_1_0_239, n_1_0_240, n_1_0_241, n_1_0_242, n_1_0_243, + n_1_0_244, n_1_0_245, n_1_0_246, n_1_0_247, n_1_0_248, n_1_0_249, + n_1_0_250, n_1_0_251, n_1_0_252, n_1_0_253, n_1_0_254, n_1_0_255, + n_1_0_256, n_1_0_257, n_1_0_258, n_1_0_259, n_1_0_260, n_1_0_261, + n_1_0_262, n_1_0_263, n_1_0_264, n_1_0_265, n_1_0_266, n_1_0_267, + n_1_0_268, n_1_0_269, n_1_0_270, n_1_0_271, n_1_0_272, n_1_0_273, + n_1_0_274, n_1_0_275, n_1_0_276, n_1_0_277, n_1_0_278, n_1_0_279, + n_1_0_280, n_1_0_281, n_1_0_282, n_1_0_283, n_1_0_284, n_1_0_285, + n_1_0_286, n_1_0_287, n_1_0_288, n_1_0_289, n_1_0_290, n_1_0_291, + n_1_0_292, n_1_0_293, n_1_0_294, n_1_0_295, n_1_0_296, n_1_0_297, + n_1_0_298, n_1_0_299, n_1_0_300, n_1_0_301, n_1_0_302, n_1_0_303, + n_1_0_304, n_1_0_305, n_1_0_306, n_1_0_307, n_1_0_308, n_1_0_309, + n_1_0_310, n_1_0_311, n_1_0_312, n_1_0_313, n_1_0_314, n_1_0_315, + n_1_0_316, n_1_0_317, n_1_0_318, n_1_0_319, n_1_0_320, n_1_0_321, + n_1_0_322, n_1_0_323, n_1_0_324, n_1_0_325, n_1_0_326, n_1_0_327, + n_1_0_328, n_1_0_329, n_1_0_330, n_1_0_331, n_1_0_332, n_1_0_333, + n_1_0_334, n_1_0_335, n_1_0_336, n_1_0_337, n_1_0_338, n_1_0_339, + n_1_0_340, n_1_0_341, n_1_0_342, n_1_0_343, n_1_0_344, n_1_0_345, + n_1_0_346, n_1_0_347, n_1_0_348, n_1_0_349, n_1_0_350, n_1_0_351, + n_1_0_352, n_1_0_353, n_1_0_354, n_1_0_355, n_1_0_356, n_1_0_357, + n_1_0_358, n_1_0_359, n_1_0_360, n_1_0_361, n_1_0_362, n_1_0_363, + n_1_0_364, n_1_0_365, n_1_0_366, n_1_0_367, n_1_0_368, n_1_0_369, + n_1_0_370, n_1_0_371, n_1_0_372, n_1_0_373, n_1_0_374, n_1_0_375, + n_1_0_376, n_1_0_377, n_1_0_378, n_1_0_379, n_1_0_380, n_1_0_381, + n_1_0_382, n_1_0_383, n_1_0_384, n_1_0_385, n_1_0_386, n_1_0_387, + n_1_0_388, n_1_0_389, n_1_0_390, n_1_0_391, n_1_0_392, n_1_0_393, + n_1_0_394, n_1_0_395, n_1_0_396, n_1_0_397, n_1_0_398, n_1_0_399, + n_1_0_400, n_1_0_401, n_1_0_402, n_1_0_403, n_1_0_404, n_1_0_405, + n_1_0_406, n_1_0_407, n_1_0_408, n_1_0_409, n_1_0_410, n_1_0_411, + n_1_0_412, n_1_0_413, n_1_0_414, n_1_0_415, n_1_0_416, n_1_0_417, + n_1_0_418, n_1_0_419, n_1_0_420, n_1_0_421, n_1_0_422, n_1_0_423, + n_1_0_424, n_1_0_425, n_1_0_426, n_1_0_427, n_1_0_428, n_1_0_429, + n_1_0_430, n_1_0_431, n_1_0_432, n_1_0_433, n_1_0_434, n_1_0_435, + n_1_0_436, n_1_0_437, n_1_0_438, n_1_0_439, n_1_0_440, n_1_0_441, + n_1_0_442, n_1_0_443, n_1_0_444, n_1_0_445, n_1_0_446, n_1_0_447, + n_1_0_448, n_1_0_449, n_1_0_450, n_1_0_451, n_1_0_452, n_1_0_453, + n_1_0_454, n_1_0_455, n_1_0_456, n_1_0_457, n_1_0_458, n_1_0_459, + n_1_0_460, n_1_0_461, n_1_0_462, n_1_0_463, n_1_0_464, n_1_0_465, + n_1_0_466, n_1_0_467, n_1_0_468, n_1_0_469, n_1_0_470, n_1_0_471, + n_1_0_472, n_1_0_473, n_1_0_474, n_1_0_475, n_1_0_476, n_1_0_477, + n_1_0_478, n_1_0_479, n_1_0_480, n_1_0_481, n_1_0_482, n_1_0_483, + n_1_0_484, n_1_0_485, n_1_0_486, n_1_0_487, n_1_0_488, n_1_0_489, + n_1_0_490, n_1_0_491, n_1_0_492, n_1_0_493, n_1_0_494, n_1_0_495, + n_1_0_496, n_1_0_497, n_1_0_498, n_1_0_499, n_1_0_500, n_1_0_501, + n_1_0_502, n_1_0_503, n_1_0_504, n_1_0_505, n_1_0_506, n_1_0_507, + n_1_0_508, n_1_0_509, n_1_0_510, n_1_0_511, n_1_0_512, n_1_0_513, + n_1_0_514, n_1_0_515, n_1_0_516, n_1_0_517, n_1_0_518, n_1_0_519, + n_1_0_520, n_1_0_521, n_1_0_522, n_1_0_523, n_1_0_524, n_1_0_525, + n_1_0_526, n_1_0_527, n_1_0_528, n_1_0_529, n_1_0_530, n_1_0_531, + n_1_0_532, n_1_0_533, n_1_0_534, n_1_0_535, n_1_0_536, n_1_0_537, + n_1_0_538, n_1_0_539, n_1_0_540, n_1_0_541, n_1_0_542, n_1_0_543, + n_1_0_544, n_1_0_545, n_1_0_546, n_1_0_547, n_1_0_548, n_1_0_549, + n_1_0_550, n_1_0_551, n_1_0_552, n_1_0_553, n_1_0_554, n_1_0_555, + n_1_0_556, n_1_0_557, n_1_0_558, n_1_0_559, n_1_0_560, n_1_0_561, + n_1_0_562, n_1_0_563, n_1_0_564, n_1_0_565, n_1_0_566, n_1_0_567, + n_1_0_568, n_1_0_569, n_1_0_570, n_1_0_571, n_1_0_572, n_1_0_573, + n_1_0_574, n_1_0_575, n_1_0_576, n_1_0_577, n_1_0_578, n_1_0_579, + n_1_0_580, n_1_0_581, n_1_0_582, n_1_0_583, n_1_0_584, n_1_0_585, + n_1_0_586, n_1_0_587, n_1_0_588, n_1_0_589, n_1_0_590, n_1_0_591, + n_1_0_592, n_1_0_593, n_1_0_594, n_1_0_595, n_1_0_596, n_1_0_597, + n_1_0_598, n_1_0_599, n_1_0_600, n_1_0_601, n_1_0_602, n_1_0_603, + n_1_0_604, n_1_0_605, n_1_0_606, n_1_0_607, n_1_0_608, n_1_0_609, + n_1_0_610, n_1_0_611, n_1_0_612, n_1_0_613, n_1_0_614, n_1_0_615, + n_1_0_616, n_1_0_617, n_1_0_618, n_1_0_619, n_1_0_620, n_1_0_621, + n_1_0_622, n_1_0_623, n_1_0_624, n_1_0_625, n_1_0_626, n_1_0_627, + n_1_0_628, n_1_0_629, n_1_0_630, n_1_0_631, n_1_0_632, n_1_0_633, + n_1_0_634, n_1_0_635, n_1_0_636, n_1_0_637, n_1_0_638, n_1_0_639, + n_1_0_640, n_1_0_641, n_1_0_642, n_1_0_643, n_1_0_644, n_1_0_645, + n_1_0_646, n_1_0_647, n_1_0_648, n_1_0_649, n_1_0_650, n_1_0_651, + n_1_0_652, n_1_0_653, n_1_0_654, n_1_0_655, n_1_0_656, n_1_0_657, + n_1_0_658, n_1_0_659, n_1_0_660, n_1_0_661, n_1_0_662, n_1_0_663, + n_1_0_664, n_1_0_665, n_1_0_666, n_1_0_667, n_1_0_668, n_1_0_669, + n_1_0_670, n_1_0_671, n_1_0_672, n_1_0_673, n_1_0_674, n_1_0_675, + n_1_0_676, n_1_0_677, n_1_0_678, n_1_0_679, n_1_0_680, n_1_0_681, + n_1_0_682, n_1_0_683, n_1_0_684, n_1_0_685, n_1_0_686, n_1_0_687, + n_1_0_688, n_1_0_689, n_1_0_690, n_1_0_691, n_1_0_692, n_1_0_693, + n_1_0_694, n_1_0_695, n_1_0_696, n_1_0_697, n_1_0_698, n_1_0_699, + n_1_0_700, n_1_0_701, n_1_0_702, n_1_0_703, n_1_0_704, n_1_0_705, + n_1_0_706, n_1_0_707, n_1_0_708, n_1_0_709, n_1_0_710, n_1_0_711, + n_1_0_712, n_1_0_713, n_1_0_714, n_1_0_715, n_1_0_716, n_1_0_717, + n_1_0_718, n_1_0_719, n_1_0_720, n_1_0_721, n_1_0_722, n_1_0_723, + n_1_0_724, n_1_0_725, n_1_0_726, n_1_0_727, n_1_0_728, n_1_0_729, + n_1_0_730, n_1_0_731, n_1_0_732, n_1_0_733, n_1_0_734, n_1_0_735, + n_1_0_736, n_1_0_737, n_1_0_738, n_1_0_739, n_1_0_740, n_1_0_741, + n_1_0_742, n_1_0_743, n_1_0_744, n_1_0_745, n_1_0_746, n_1_0_747, + n_1_0_748, n_1_0_749, n_1_0_750, n_1_0_751, n_1_0_752, n_1_0_753, + n_1_0_754, n_1_0_755, n_1_0_756, n_1_0_757, n_1_0_758, n_1_0_759, + n_1_0_760, n_1_0_761, n_1_0_762, n_1_0_763, n_1_0_764, n_1_0_765, + n_1_0_766, n_1_0_767, n_1_0_768, n_1_0_769, n_1_0_770, n_1_0_771, + n_1_0_772, n_1_0_773, n_1_0_774, n_1_0_775, n_1_0_776, n_1_0_777, + n_1_0_778, n_1_0_779, n_1_0_780, n_1_0_781, n_1_0_782, n_1_0_783, + n_1_0_784, n_1_0_785, n_1_0_786, n_1_0_787, n_1_0_788, n_1_0_789, + n_1_0_790, n_1_0_791, n_1_0_792, n_1_0_793, n_1_0_794, n_1_0_795, + n_1_0_796, n_1_0_797, n_1_0_798, n_1_0_799, n_1_0_800, n_1_0_801, + n_1_0_802, n_1_0_803, n_1_0_804, n_1_0_805, n_1_0_806, n_1_0_807, + n_1_0_808, n_1_0_809, n_1_0_810, n_1_0_811, n_1_0_812, n_1_0_813, + n_1_0_814, n_1_0_815, n_1_0_816, n_1_0_817, n_1_0_818, n_1_0_819, + n_1_0_820, n_1_0_821, n_1_0_822, n_1_0_823, n_1_0_824, n_1_0_825, + n_1_0_826, n_1_0_827, n_1_0_828, n_1_0_829, n_1_0_830, n_1_0_831, + n_1_0_832, n_1_0_833, n_1_0_834, n_1_0_835, n_1_0_836, n_1_0_837, + n_1_0_838, n_1_0_839, n_1_0_840, n_1_0_841, n_1_0_842, n_1_0_843, + n_1_0_844, n_1_0_845, n_1_0_846, n_1_0_847, n_1_0_848, n_1_0_849, + n_1_0_850, n_1_0_851, n_1_0_852, n_1_0_853, n_1_0_854, n_1_0_855, + n_1_0_856, n_1_0_857, n_1_0_858, n_1_0_859, n_1_0_860, n_1_0_861, + n_1_0_862, n_1_0_863, n_1_0_864, n_1_0_865, n_1_0_866, n_1_0_867, + n_1_0_868, n_1_0_869, n_1_0_870, n_1_0_871, n_1_0_872, n_1_0_873, + n_1_0_874, n_1_0_875, n_1_0_876, n_1_0_877, n_1_0_878, n_1_0_879, + n_1_0_880, n_1_0_881, n_1_0_882, n_1_0_883, n_1_0_884, n_1_0_885, + n_1_0_886, n_1_0_887, n_1_0_888, n_1_0_889, n_1_0_890, n_1_0_891, + n_1_0_892, n_1_0_893, n_1_0_894, n_1_0_895, n_1_0_896, n_1_0_897, + n_1_0_898, n_1_0_899, n_1_0_900, n_1_0_901, n_1_0_902, n_1_0_903, + n_1_0_904, n_1_0_905, n_1_0_906, n_1_0_907, n_1_0_908, n_1_0_909, + n_1_0_910, n_1_0_911, n_1_0_912, n_1_0_913, n_1_0_914, n_1_0_915, + n_1_0_916, n_1_0_917, n_1_0_918, n_1_0_919, n_1_0_920, n_1_0_921, + n_1_0_922, n_1_0_923, n_1_0_924, n_1_0_925, n_1_0_926, n_1_0_927, + n_1_0_928, n_1_0_929, n_1_0_930, n_1_0_931, n_1_0_932, n_1_0_933, + n_1_0_934, n_1_0_935, n_1_0_936, n_1_0_937, n_1_0_938, n_1_0_939, + n_1_0_940, n_1_0_941, n_1_0_942, n_1_0_943, n_1_0_944, n_1_0_945, + n_1_0_946, n_1_0_947, n_1_0_948, n_1_0_949, n_1_0_950, n_1_0_951, + n_1_0_952, n_1_0_953, n_1_0_954, n_1_0_955, n_1_0_956, n_1_0_957, + n_1_0_958, n_1_0_959, n_1_0_960, n_1_0_961, n_1_0_962, n_1_0_963, + n_1_0_964, n_1_0_965, n_1_0_966, n_1_0_967, n_1_0_968, n_1_0_969, + n_1_0_970, n_1_0_971, n_1_0_972, n_1_0_973, n_1_0_974, n_1_0_975, + n_1_0_976, n_1_0_977, n_1_0_978, n_1_0_979, n_1_0_980, n_1_0_981, + n_1_0_982, n_1_0_983, n_1_0_984, n_1_0_985, n_1_0_986, n_1_0_987, + n_1_0_988, n_1_0_989, n_1_0_990, n_1_0_991, n_1_0_992, n_1_0_993, + n_1_0_994, n_1_0_995, n_1_0_996, n_1_0_997, n_1_0_998, n_1_0_999, + n_1_0_1000, n_1_0_1001, n_1_0_1002, n_1_0_1003, n_1_0_1004, n_1_0_1005, + n_1_0_1006, n_1_0_1007, n_1_0_1008, n_1_0_1009, n_1_0_1010, n_1_0_1011, + n_1_0_1012, n_1_0_1013, n_1_0_1014, n_1_0_1015, n_1_0_1016, n_1_0_1017, + n_1_0_1018, n_1_0_1019, n_1_0_1020, n_1_0_1021, n_1_0_1022, n_1_0_1023, + n_1_0_1024, n_1_0_1025, n_1_0_1026, n_1_0_1027, n_1_0_1028, n_1_0_1029, + n_1_0_1030, n_1_0_1031, n_1_0_1032, n_1_0_1033, n_1_0_1034, n_1_0_1035, + n_1_0_1036, n_1_0_1037, n_1_0_1038, n_1_0_1039, n_1_0_1040, n_1_0_1041, + n_1_0_1042, n_1_0_1043, n_1_0_1044, n_1_0_1045, n_1_0_1046, n_1_0_1047, + n_1_0_1048, n_1_0_1049, n_1_0_1050, n_1_0_1051, n_1_0_1052, n_1_0_1053, + n_1_0_1054, n_1_0_1055, n_1_0_1056, n_1_0_1057, n_1_0_1058, n_1_0_1059, + n_1_0_1060, n_1_0_1061, n_1_0_1062, n_1_0_1063, n_1_0_1064, n_1_0_1065, + n_1_0_1066, n_1_0_1067, n_1_0_1068, n_1_0_1069, n_1_0_1070, n_1_0_1071, + n_1_0_1072, n_1_0_1073, n_1_0_1074, n_1_0_1075, n_1_0_1076, n_1_0_1077, + n_1_0_1078, n_1_0_1079, n_1_0_1080, n_1_0_1081, n_1_0_1082, n_1_0_1083, + n_1_0_1084, n_1_0_1085, n_1_0_1086, n_1_0_1087, n_1_0_1088, n_1_0_1089, + n_1_0_1090, n_1_0_1091, n_1_0_1092, n_1_0_1093, n_1_0_1094, n_1_0_1095, + n_1_0_1096, n_1_0_1097, n_1_0_1098, n_1_0_1099, n_1_0_1100, n_1_0_1101, + n_1_0_1102, n_1_0_1103, n_1_0_1104, n_1_0_1105, n_1_0_1106, n_1_0_1107, + n_1_0_1108, n_1_0_1109, n_1_0_1110, n_1_0_1111, n_1_0_1112, n_1_0_1113, + n_1_0_1114, n_1_0_1115, n_1_0_1116, n_1_0_1117, n_1_0_1118, n_1_0_1119, + n_1_0_1120, n_1_0_1121, n_1_0_1122, n_1_0_1123, n_1_0_1124, n_1_0_1125, + n_1_0_1126, n_1_0_1127, n_1_0_1128, n_1_0_1129, n_1_0_1130, n_1_0_1131, + n_1_0_1132, n_1_0_1133, n_1_0_1134, n_1_0_1135, n_1_0_1136, n_1_0_1137, + n_1_0_1138, n_1_0_1139, n_1_0_1140, n_1_0_1141, n_1_0_1142, n_1_0_1143, + n_1_0_1144, n_1_0_1145, n_1_0_1146, n_1_0_1147, n_1_0_1148, n_1_0_1149, + n_1_0_1150, n_1_0_1151, n_1_0_1152, n_1_0_1153, n_1_0_1154, n_1_0_1155, + n_1_0_1156, n_1_0_1157, n_1_0_1158, n_1_0_1159, n_1_0_1160, n_1_0_1161, + n_1_0_1162, n_1_0_1163, n_1_0_1164, n_1_0_1165, n_1_0_1166, n_1_0_1167, + n_1_0_1168, n_1_0_1169, n_1_0_1170, n_1_0_1171, n_1_0_1172, n_1_0_1173, + n_1_0_1174, n_1_0_1175, n_1_0_1176, n_1_0_1177, n_1_0_1178, n_1_0_1179, + n_1_0_1180, n_1_0_1181, n_1_0_1182, n_1_0_1183, n_1_0_1184, n_1_0_1185, + n_1_0_1186, n_1_0_1187, n_1_0_1188, n_1_0_1189, n_1_0_1190, n_1_0_1191, + n_1_0_1192, n_1_0_1193, n_1_0_1194, n_1_0_1195, n_1_0_1196, n_1_0_1197, + n_1_0_1198, n_1_0_1199, n_1_0_1200, n_1_0_1201, n_1_0_1202, n_1_0_1203, + n_1_0_1204, n_1_0_1205, n_1_0_1206, n_1_0_1207, n_1_0_1208, n_1_0_1209, + n_1_0_1210, n_1_0_1211, n_1_0_1212, n_1_0_1213, n_1_0_1214, n_1_0_1215, + n_1_0_1216, n_1_0_1217, n_1_0_1218, n_1_0_1219, n_1_0_1220, n_1_0_1221, + n_1_0_1222, n_1_0_1223, n_1_0_1224, n_1_0_1225, n_1_0_1226, n_1_0_1227, + n_1_0_1228, n_1_0_1229, n_1_0_1230, n_1_0_1231, n_1_0_1232, n_1_0_1233, + n_1_0_1234, n_1_0_1235, n_1_0_1236, n_1_0_1237, n_1_0_1238, n_1_0_1239, + n_1_0_1240, n_1_0_1241, n_1_0_1242, n_1_0_1243, n_1_0_1244, n_1_0_1245, + n_1_0_1246, n_1_0_1247, n_1_0_1248, n_1_0_1249, n_1_0_1250, n_1_0_1251, + n_1_0_1252, n_1_0_1253, n_1_0_1254, n_1_0_1255, n_1_0_1256, n_1_0_1257, + n_1_0_1258, n_1_0_1259, n_1_0_1260, n_1_0_1261, n_1_0_1262, n_1_0_1263, + n_1_0_1264, n_1_0_1265, n_1_0_1266, n_1_0_1267, n_1_0_1268, n_1_0_1269, + n_1_0_1270, n_1_0_1271, n_1_0_1272, n_1_0_1273, n_1_0_1274, n_1_0_1275, + n_1_0_1276, n_1_0_1277, n_1_0_1278, n_1_0_1279, n_1_0_1280, n_1_0_1281, + n_1_0_1282, n_1_0_1283, n_1_0_1284, n_1_0_1285, n_1_0_1286, n_1_0_1287, + n_1_0_1288, n_1_0_1289, n_1_0_1290, n_1_0_1291, n_1_0_1292, n_1_0_1293, + n_1_0_1294, n_1_0_1295, n_1_0_1296, n_1_0_1297, n_1_0_1298, n_1_0_1299, + n_1_0_1300, n_1_0_1301, n_1_0_1302, n_1_0_1303, n_1_0_1304, n_1_0_1305, + n_1_0_1306, n_1_0_1307, n_1_0_1308, n_1_0_1309, ts_pbuf_extsi1227_, + ts_pbuf_extsi1228_, ts_pbuf_extsi1226_; + + INV_X1_LVT i_0_0_79( + .A(reset), .ZN(n_0_0_16) + ); + AND2_X1_LVT i_0_0_31( + .A1(n_0_0_16), .A2(WRd[31]), .ZN(registers[31]) + ); + INV_X1_LVT i_0_0_81( + .A(Rd[1]), .ZN(n_0_0_18) + ); + INV_X1_LVT i_0_0_80( + .A(Rd[0]), .ZN(n_0_0_17) + ); + NAND3_X1_LVT i_0_0_69( + .A1(n_0_0_18), .A2(n_0_0_17), .A3(Rd[2]), .ZN(n_0_0_9) + ); + NAND3_X1_LVT i_0_0_41( + .A1(Rd[3]), .A2(WrReg), .A3(Rd[4]), .ZN(n_0_0_1) + ); + OAI21_X1_LVT i_0_0_35( + .A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_1), .ZN(n_0_28) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[28]_reg ( + .CK(clk), .E(n_0_28), .GCK(n_0_58), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[28][31] ( + .CK(n_0_58), .D(registers[31]), .Q(registers_28__ap[31]), .QN(), .SE(dftIn), + .SI(ts_pbuf_extsi1227_) + ); + INV_X1_LVT i_1_0_1370( + .A(Rs1[0]), .ZN(n_1_0_1306) + ); + NAND3_X1_LVT i_1_0_1354( + .A1(n_1_0_1306), .A2(Rs1[3]), .A3(Rs1[4]), .ZN(n_1_0_1290) + ); + INV_X1_LVT i_1_0_1373( + .A(Rs1[2]), .ZN(n_1_0_1309) + ); + OR2_X1_LVT i_1_0_1348( + .A1(n_1_0_1309), .A2(Rs1[1]), .ZN(n_1_0_1284) + ); + NOR2_X1_LVT i_1_0_1347( + .A1(n_1_0_1290), .A2(n_1_0_1284), .ZN(n_1_0_1283) + ); + NOR4_X1_LVT i_1_0_1342( + .A1(n_1_0_1284), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), .ZN(n_1_0_1278) + ); + INV_X1_LVT i_0_0_83( + .A(WrReg), .ZN(n_0_0_20) + ); + OR3_X1_LVT i_0_0_77( + .A1(n_0_0_20), .A2(Rd[4]), .A3(Rd[3]), .ZN(n_0_0_14) + ); + OAI21_X1_LVT i_0_0_68( + .A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_9), .ZN(n_0_4) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[4]_reg ( + .CK(clk), .E(n_0_4), .GCK(n_0_34), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[4][31] ( + .CK(n_0_34), .D(registers[31]), .Q(registers_4__ap[31]), .QN(), .SE(dftIn), + .SI(ts_pbuf_extsi1228_) + ); + AOI22_X1_LVT i_1_0_1320( + .A1(registers_28__ap[31]), .A2(n_1_0_1283), .B1(n_1_0_1278), .B2(registers_4__ap[31]), + .ZN(n_1_0_1256) + ); + NAND2_X1_LVT i_0_0_70( + .A1(n_0_0_18), .A2(n_0_0_17), .ZN(n_0_0_10) + ); + INV_X1_LVT i_0_0_82( + .A(Rd[4]), .ZN(n_0_0_19) + ); + OR3_X1_LVT i_0_0_51( + .A1(n_0_0_20), .A2(n_0_0_19), .A3(Rd[3]), .ZN(n_0_0_3) + ); + OR2_X1_LVT i_0_0_50( + .A1(n_0_0_3), .A2(Rd[2]), .ZN(n_0_0_2) + ); + OAI21_X1_LVT i_0_0_49( + .A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_2), .ZN(n_0_16) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[16]_reg ( + .CK(clk), .E(n_0_16), .GCK(n_0_46), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[16][31] ( + .CK(n_0_46), .D(registers[31]), .Q(registers_16__ap[31]), .QN(), .SE(dftIn), + .SI(ts_intno31) + ); + INV_X1_LVT i_1_0_1371( + .A(Rs1[3]), .ZN(n_1_0_1307) + ); + NAND3_X1_LVT i_1_0_1363( + .A1(n_1_0_1307), .A2(n_1_0_1306), .A3(Rs1[4]), .ZN(n_1_0_1299) + ); + OR2_X1_LVT i_1_0_1357( + .A1(Rs1[1]), .A2(Rs1[2]), .ZN(n_1_0_1293) + ); + NOR2_X1_LVT i_1_0_1331( + .A1(n_1_0_1299), .A2(n_1_0_1293), .ZN(n_1_0_1267) + ); + NAND2_X1_LVT i_1_0_1365( + .A1(Rs1[1]), .A2(Rs1[2]), .ZN(n_1_0_1301) + ); + NAND3_X1_LVT i_1_0_1344( + .A1(Rs1[4]), .A2(Rs1[3]), .A3(Rs1[0]), .ZN(n_1_0_1280) + ); + NOR2_X1_LVT i_1_0_1330( + .A1(n_1_0_1301), .A2(n_1_0_1280), .ZN(n_1_0_1266) + ); + NAND3_X1_LVT i_0_0_63( + .A1(Rd[2]), .A2(Rd[1]), .A3(Rd[0]), .ZN(n_0_0_6) + ); + OAI21_X1_LVT i_0_0_32( + .A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_1), .ZN(n_0_31) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[31]_reg ( + .CK(clk), .E(n_0_31), .GCK(n_0_61), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[31][31] ( + .CK(n_0_61), .D(registers[31]), .Q(registers_31__ap[31]), .QN(), .SE(dftIn), + .SI(registers_4__ap[31]) + ); + AOI22_X1_LVT i_1_0_1329( + .A1(registers_16__ap[31]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[31]), + .ZN(n_1_0_1265) + ); + NAND3_X1_LVT i_0_0_65( + .A1(n_0_0_17), .A2(Rd[1]), .A3(Rd[2]), .ZN(n_0_0_7) + ); + OAI21_X1_LVT i_0_0_64( + .A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_7), .ZN(n_0_6) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[6]_reg ( + .CK(clk), .E(n_0_6), .GCK(n_0_36), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[6][31] ( + .CK(n_0_36), .D(registers[31]), .Q(registers_6__ap[31]), .QN(), .SE(dftIn), + .SI(registers_31__ap[31]) + ); + NOR4_X1_LVT i_1_0_1364( + .A1(n_1_0_1301), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), .ZN(n_1_0_1300) + ); + INV_X1_LVT i_1_0_1372( + .A(Rs1[4]), .ZN(n_1_0_1308) + ); + NAND3_X1_LVT i_1_0_1339( + .A1(n_1_0_1308), .A2(n_1_0_1307), .A3(Rs1[0]), .ZN(n_1_0_1275) + ); + NOR2_X1_LVT i_1_0_1338( + .A1(n_1_0_1293), .A2(n_1_0_1275), .ZN(n_1_0_1274) + ); + NAND2_X1_LVT i_0_0_78( + .A1(n_0_0_18), .A2(Rd[0]), .ZN(n_0_0_15) + ); + OR2_X1_LVT i_0_0_76( + .A1(n_0_0_14), .A2(Rd[2]), .ZN(n_0_0_13) + ); + OAI21_X1_LVT i_0_0_75( + .A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_13), .ZN(n_0_1) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[1]_reg ( + .CK(clk), .E(n_0_1), .GCK(n_0_0), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[1][31] ( + .CK(n_0_0), .D(registers[31]), .Q(registers_1__ap[31]), .QN(), .SE(dftIn), + .SI(ts_pbuf_extsi1226_) + ); + AOI22_X1_LVT i_1_0_1319( + .A1(registers_6__ap[31]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[31]), + .ZN(n_1_0_1255) + ); + OAI21_X1_LVT i_0_0_42( + .A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_3), .ZN(n_0_23) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[23]_reg ( + .CK(clk), .E(n_0_23), .GCK(n_0_53), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[23][31] ( + .CK(n_0_53), .D(registers[31]), .Q(registers_23__ap[31]), .QN(), .SE(dftIn), + .SI(registers_1__ap[31]) + ); + NAND3_X1_LVT i_1_0_1360( + .A1(n_1_0_1307), .A2(Rs1[0]), .A3(Rs1[4]), .ZN(n_1_0_1296) + ); + NOR2_X1_LVT i_1_0_1328( + .A1(n_1_0_1301), .A2(n_1_0_1296), .ZN(n_1_0_1264) + ); + NOR2_X1_LVT i_1_0_1327( + .A1(n_1_0_1301), .A2(n_1_0_1275), .ZN(n_1_0_1263) + ); + OAI21_X1_LVT i_0_0_62( + .A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_6), .ZN(n_0_7) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[7]_reg ( + .CK(clk), .E(n_0_7), .GCK(n_0_37), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[7][31] ( + .CK(n_0_37), .D(registers[31]), .Q(registers_7__ap[31]), .QN(), .SE(dftIn), + .SI(registers_6__ap[31]) + ); + AOI22_X1_LVT i_1_0_1326( + .A1(registers_23__ap[31]), .A2(n_1_0_1264), .B1(n_1_0_1263), .B2(registers_7__ap[31]), + .ZN(n_1_0_1262) + ); + INV_X1_LVT i_1_0_1325( + .A(n_1_0_1262), .ZN(n_1_0_1261) + ); + NAND2_X1_LVT i_1_0_1362( + .A1(n_1_0_1309), .A2(Rs1[1]), .ZN(n_1_0_1298) + ); + NOR2_X1_LVT i_1_0_1359( + .A1(n_1_0_1298), .A2(n_1_0_1296), .ZN(n_1_0_1295) + ); + NAND2_X1_LVT i_0_0_72( + .A1(Rd[1]), .A2(Rd[0]), .ZN(n_0_0_11) + ); + OAI21_X1_LVT i_0_0_46( + .A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_2), .ZN(n_0_19) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[19]_reg ( + .CK(clk), .E(n_0_19), .GCK(n_0_49), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[19][31] ( + .CK(n_0_49), .D(registers[31]), .Q(registers_19__ap[31]), .QN(), .SE(dftIn), + .SI(registers_23__ap[31]) + ); + NAND3_X1_LVT i_0_0_67( + .A1(n_0_0_18), .A2(Rd[0]), .A3(Rd[2]), .ZN(n_0_0_8) + ); + OAI21_X1_LVT i_0_0_66( + .A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_8), .ZN(n_0_5) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[5]_reg ( + .CK(clk), .E(n_0_5), .GCK(n_0_35), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[5][31] ( + .CK(n_0_35), .D(registers[31]), .Q(registers_5__ap[31]), .QN(), .SE(dftIn), + .SI(registers_7__ap[31]) + ); + NOR2_X1_LVT i_1_0_1337( + .A1(n_1_0_1284), .A2(n_1_0_1275), .ZN(n_1_0_1273) + ); + AOI221_X1_LVT i_1_0_1318( + .A(n_1_0_1261), .B1(n_1_0_1295), .B2(registers_19__ap[31]), .C1(registers_5__ap[31]), + .C2(n_1_0_1273), .ZN(n_1_0_1254) + ); + NAND2_X1_LVT i_0_0_74( + .A1(n_0_0_17), .A2(Rd[1]), .ZN(n_0_0_12) + ); + NAND3_X1_LVT i_0_0_61( + .A1(n_0_0_19), .A2(WrReg), .A3(Rd[3]), .ZN(n_0_0_5) + ); + OR2_X1_LVT i_0_0_60( + .A1(n_0_0_5), .A2(Rd[2]), .ZN(n_0_0_4) + ); + OAI21_X1_LVT i_0_0_57( + .A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_4), .ZN(n_0_10) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[10]_reg ( + .CK(clk), .E(n_0_10), .GCK(n_0_40), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[10][31] ( + .CK(n_0_40), .D(registers[31]), .Q(registers_10__ap[31]), .QN(), .SE(dftIn), + .SI(registers_16__ap[31]) + ); + NAND3_X1_LVT i_1_0_1352( + .A1(n_1_0_1308), .A2(n_1_0_1306), .A3(Rs1[3]), .ZN(n_1_0_1288) + ); + NOR2_X1_LVT i_1_0_1351( + .A1(n_1_0_1298), .A2(n_1_0_1288), .ZN(n_1_0_1287) + ); + NOR2_X1_LVT i_1_0_1349( + .A1(n_1_0_1298), .A2(n_1_0_1290), .ZN(n_1_0_1285) + ); + OR2_X1_LVT i_0_0_40( + .A1(n_0_0_1), .A2(Rd[2]), .ZN(n_0_0_0) + ); + OAI21_X1_LVT i_0_0_37( + .A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_0), .ZN(n_0_26) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[26]_reg ( + .CK(clk), .E(n_0_26), .GCK(n_0_56), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[26][31] ( + .CK(n_0_56), .D(registers[31]), .Q(registers_26__ap[31]), .QN(), .SE(dftIn), + .SI(registers_28__ap[31]) + ); + OAI21_X1_LVT i_0_0_59( + .A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_4), .ZN(n_0_8) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[8]_reg ( + .CK(clk), .E(n_0_8), .GCK(n_0_38), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[8][31] ( + .CK(n_0_38), .D(registers[31]), .Q(registers_8__ap[31]), .QN(), .SE(dftIn), + .SI(registers_5__ap[31]) + ); + NOR2_X1_LVT i_1_0_1346( + .A1(n_1_0_1293), .A2(n_1_0_1288), .ZN(n_1_0_1282) + ); + AOI222_X1_LVT i_1_0_1317( + .A1(registers_10__ap[31]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[31]), + .C1(registers_8__ap[31]), .C2(n_1_0_1282), .ZN(n_1_0_1253) + ); + NAND4_X1_LVT i_1_0_1316( + .A1(n_1_0_1265), .A2(n_1_0_1255), .A3(n_1_0_1254), .A4(n_1_0_1253), .ZN(n_1_0_1252) + ); + NAND3_X1_LVT i_1_0_1356( + .A1(n_1_0_1308), .A2(Rs1[3]), .A3(Rs1[0]), .ZN(n_1_0_1292) + ); + NOR2_X1_LVT i_1_0_1355( + .A1(n_1_0_1293), .A2(n_1_0_1292), .ZN(n_1_0_1291) + ); + OAI21_X1_LVT i_0_0_58( + .A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_4), .ZN(n_0_9) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[9]_reg ( + .CK(clk), .E(n_0_9), .GCK(n_0_39), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[9][31] ( + .CK(n_0_39), .D(registers[31]), .Q(registers_9__ap[31]), .QN(), .SE(dftIn), + .SI(registers_8__ap[31]) + ); + OAI21_X1_LVT i_0_0_34( + .A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_1), .ZN(n_0_29) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[29]_reg ( + .CK(clk), .E(n_0_29), .GCK(n_0_59), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[29][31] ( + .CK(n_0_59), .D(registers[31]), .Q(registers_29__ap[31]), .QN(), .SE(dftIn), + .SI(registers_26__ap[31]) + ); + NOR2_X1_LVT i_1_0_1340( + .A1(n_1_0_1284), .A2(n_1_0_1280), .ZN(n_1_0_1276) + ); + AOI221_X1_LVT i_1_0_1315( + .A(n_1_0_1252), .B1(n_1_0_1291), .B2(registers_9__ap[31]), .C1(registers_29__ap[31]), + .C2(n_1_0_1276), .ZN(n_1_0_1251) + ); + OAI21_X1_LVT i_0_0_47( + .A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_2), .ZN(n_0_18) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[18]_reg ( + .CK(clk), .E(n_0_18), .GCK(n_0_48), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[18][31] ( + .CK(n_0_48), .D(registers[31]), .Q(registers_18__ap[31]), .QN(), .SE(dftIn), + .SI(registers_19__ap[31]) + ); + NOR2_X1_LVT i_1_0_1361( + .A1(n_1_0_1299), .A2(n_1_0_1298), .ZN(n_1_0_1297) + ); + NOR2_X1_LVT i_1_0_1336( + .A1(n_1_0_1301), .A2(n_1_0_1290), .ZN(n_1_0_1272) + ); + OAI21_X1_LVT i_0_0_33( + .A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_1), .ZN(n_0_30) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[30]_reg ( + .CK(clk), .E(n_0_30), .GCK(n_0_60), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[30][31] ( + .CK(n_0_60), .D(registers[31]), .Q(registers_30__ap[31]), .QN(), .SE(dftIn), + .SI(registers_29__ap[31]) + ); + AOI22_X1_LVT i_1_0_1314( + .A1(registers_18__ap[31]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[31]), + .ZN(n_1_0_1250) + ); + OAI21_X1_LVT i_0_0_39( + .A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_0), .ZN(n_0_24) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[24]_reg ( + .CK(clk), .E(n_0_24), .GCK(n_0_54), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[24][31] ( + .CK(n_0_54), .D(registers[31]), .Q(registers_24__ap[31]), .QN(), .SE(dftIn), + .SI(registers_30__ap[31]) + ); + NOR2_X1_LVT i_1_0_1353( + .A1(n_1_0_1293), .A2(n_1_0_1290), .ZN(n_1_0_1289) + ); + NOR2_X1_LVT i_1_0_1324( + .A1(n_1_0_1288), .A2(n_1_0_1284), .ZN(n_1_0_1260) + ); + OAI21_X1_LVT i_0_0_55( + .A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_5), .ZN(n_0_12) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[12]_reg ( + .CK(clk), .E(n_0_12), .GCK(n_0_42), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[12][31] ( + .CK(n_0_42), .D(registers[31]), .Q(registers_12__ap[31]), .QN(), .SE(dftIn), + .SI(registers_10__ap[31]) + ); + AOI22_X1_LVT i_1_0_1313( + .A1(registers_24__ap[31]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[31]), + .ZN(n_1_0_1249) + ); + OAI21_X1_LVT i_0_0_43( + .A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_3), .ZN(n_0_22) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[22]_reg ( + .CK(clk), .E(n_0_22), .GCK(n_0_52), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[22][31] ( + .CK(n_0_52), .D(registers[31]), .Q(registers_22__ap[31]), .QN(), .SE(dftIn), + .SI(registers_18__ap[31]) + ); + NOR2_X1_LVT i_1_0_1358( + .A1(n_1_0_1301), .A2(n_1_0_1299), .ZN(n_1_0_1294) + ); + NOR2_X1_LVT i_1_0_1323( + .A1(n_1_0_1296), .A2(n_1_0_1284), .ZN(n_1_0_1259) + ); + OAI21_X1_LVT i_0_0_44( + .A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_3), .ZN(n_0_21) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[21]_reg ( + .CK(clk), .E(n_0_21), .GCK(n_0_51), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[21][31] ( + .CK(n_0_51), .D(registers[31]), .Q(registers_21__ap[31]), .QN(), .SE(dftIn), + .SI(registers_22__ap[31]) + ); + AOI22_X1_LVT i_1_0_1312( + .A1(registers_22__ap[31]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[31]), + .ZN(n_1_0_1248) + ); + NAND3_X1_LVT i_1_0_1311( + .A1(n_1_0_1250), .A2(n_1_0_1249), .A3(n_1_0_1248), .ZN(n_1_0_1247) + ); + NOR2_X1_LVT i_1_0_1335( + .A1(n_1_0_1296), .A2(n_1_0_1293), .ZN(n_1_0_1271) + ); + OAI21_X1_LVT i_0_0_48( + .A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_2), .ZN(n_0_17) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[17]_reg ( + .CK(clk), .E(n_0_17), .GCK(n_0_47), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[17][31] ( + .CK(n_0_47), .D(registers[31]), .Q(registers_17__ap[31]), .QN(), .SE(dftIn), + .SI(registers_21__ap[31]) + ); + OAI21_X1_LVT i_0_0_45( + .A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_3), .ZN(n_0_20) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[20]_reg ( + .CK(clk), .E(n_0_20), .GCK(n_0_50), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[20][31] ( + .CK(n_0_50), .D(registers[31]), .Q(registers_20__ap[31]), .QN(), .SE(dftIn), + .SI(registers_17__ap[31]) + ); + NOR2_X1_LVT i_1_0_1345( + .A1(n_1_0_1299), .A2(n_1_0_1284), .ZN(n_1_0_1281) + ); + AOI221_X1_LVT i_1_0_1310( + .A(n_1_0_1247), .B1(n_1_0_1271), .B2(registers_17__ap[31]), .C1(registers_20__ap[31]), + .C2(n_1_0_1281), .ZN(n_1_0_1246) + ); + OAI21_X1_LVT i_0_0_36( + .A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_0), .ZN(n_0_27) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[27]_reg ( + .CK(clk), .E(n_0_27), .GCK(n_0_57), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[27][31] ( + .CK(n_0_57), .D(registers[31]), .Q(registers_27__ap[31]), .QN(), .SE(dftIn), + .SI(registers_24__ap[31]) + ); + NOR2_X1_LVT i_1_0_1343( + .A1(n_1_0_1298), .A2(n_1_0_1280), .ZN(n_1_0_1279) + ); + NOR2_X1_LVT i_1_0_1334( + .A1(n_1_0_1298), .A2(n_1_0_1292), .ZN(n_1_0_1270) + ); + OAI21_X1_LVT i_0_0_56( + .A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_4), .ZN(n_0_11) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[11]_reg ( + .CK(clk), .E(n_0_11), .GCK(n_0_41), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[11][31] ( + .CK(n_0_41), .D(registers[31]), .Q(registers_11__ap[31]), .QN(), .SE(dftIn), + .SI(registers_12__ap[31]) + ); + AOI22_X1_LVT i_1_0_1309( + .A1(registers_27__ap[31]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[31]), + .ZN(n_1_0_1245) + ); + OAI21_X1_LVT i_0_0_54( + .A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_5), .ZN(n_0_13) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[13]_reg ( + .CK(clk), .E(n_0_13), .GCK(n_0_43), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[13][31] ( + .CK(n_0_43), .D(registers[31]), .Q(registers_13__ap[31]), .QN(), .SE(dftIn), + .SI(registers_11__ap[31]) + ); + NOR2_X1_LVT i_1_0_1341( + .A1(n_1_0_1292), .A2(n_1_0_1284), .ZN(n_1_0_1277) + ); + NOR2_X1_LVT i_1_0_1333( + .A1(n_1_0_1293), .A2(n_1_0_1280), .ZN(n_1_0_1269) + ); + OAI21_X1_LVT i_0_0_38( + .A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_0), .ZN(n_0_25) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[25]_reg ( + .CK(clk), .E(n_0_25), .GCK(n_0_55), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[25][31] ( + .CK(n_0_55), .D(registers[31]), .Q(registers_25__ap[31]), .QN(), .SE(dftIn), + .SI(registers_27__ap[31]) + ); + AOI22_X1_LVT i_1_0_1308( + .A1(registers_13__ap[31]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[31]), + .ZN(n_1_0_1244) + ); + OAI21_X1_LVT i_0_0_52( + .A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_5), .ZN(n_0_15) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[15]_reg ( + .CK(clk), .E(n_0_15), .GCK(n_0_45), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[15][31] ( + .CK(n_0_45), .D(registers[31]), .Q(registers_15__ap[31]), .QN(), .SE(dftIn), + .SI(registers_13__ap[31]) + ); + NOR2_X1_LVT i_1_0_1350( + .A1(n_1_0_1301), .A2(n_1_0_1292), .ZN(n_1_0_1286) + ); + NOR2_X1_LVT i_1_0_1322( + .A1(n_1_0_1301), .A2(n_1_0_1288), .ZN(n_1_0_1258) + ); + OAI21_X1_LVT i_0_0_53( + .A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_5), .ZN(n_0_14) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[14]_reg ( + .CK(clk), .E(n_0_14), .GCK(n_0_44), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[14][31] ( + .CK(n_0_44), .D(registers[31]), .Q(registers_14__ap[31]), .QN(), .SE(dftIn), + .SI(registers_15__ap[31]) + ); + AOI22_X1_LVT i_1_0_1307( + .A1(registers_15__ap[31]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[31]), + .ZN(n_1_0_1243) + ); + NAND3_X1_LVT i_1_0_1306( + .A1(n_1_0_1245), .A2(n_1_0_1244), .A3(n_1_0_1243), .ZN(n_1_0_1242) + ); + NOR2_X1_LVT i_1_0_1321( + .A1(n_1_0_1298), .A2(n_1_0_1275), .ZN(n_1_0_1257) + ); + OAI21_X1_LVT i_0_0_71( + .A(n_0_0_16), .B1(n_0_0_13), .B2(n_0_0_11), .ZN(n_0_3) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[3]_reg ( + .CK(clk), .E(n_0_3), .GCK(n_0_33), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[3][31] ( + .CK(n_0_33), .D(registers[31]), .Q(registers_3__ap[31]), .QN(), .SE(dftIn), + .SI(registers_9__ap[31]) + ); + OAI21_X1_LVT i_0_0_73( + .A(n_0_0_16), .B1(n_0_0_13), .B2(n_0_0_12), .ZN(n_0_2) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[2]_reg ( + .CK(clk), .E(n_0_2), .GCK(n_0_32), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[2][31] ( + .CK(n_0_32), .D(registers[31]), .Q(registers_2__ap[31]), .QN(), .SE(dftIn), + .SI(registers_25__ap[31]) + ); + NOR4_X1_LVT i_1_0_1332( + .A1(n_1_0_1298), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), .ZN(n_1_0_1268) + ); + AOI221_X1_LVT i_1_0_1305( + .A(n_1_0_1242), .B1(n_1_0_1257), .B2(registers_3__ap[31]), .C1(registers_2__ap[31]), + .C2(n_1_0_1268), .ZN(n_1_0_1241) + ); + NAND4_X1_LVT i_1_0_1304( + .A1(n_1_0_1256), .A2(n_1_0_1251), .A3(n_1_0_1246), .A4(n_1_0_1241), .ZN(RRs1[31]) + ); + AND2_X1_LVT i_0_0_30( + .A1(n_0_0_16), .A2(WRd[30]), .ZN(registers[30]) + ); + SDFF_X1_LVT \registers_reg[28][30] ( + .CK(n_0_58), .D(registers[30]), .Q(registers_28__ap[30]), .QN(), .SE(dftIn), + .SI(registers_2__ap[31]) + ); + SDFF_X1_LVT \registers_reg[17][30] ( + .CK(n_0_47), .D(registers[30]), .Q(registers_17__ap[30]), .QN(), .SE(dftIn), + .SI(registers_20__ap[31]) + ); + AOI22_X1_LVT i_1_0_1300( + .A1(registers_28__ap[30]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[30]), + .ZN(n_1_0_1237) + ); + SDFF_X1_LVT \registers_reg[16][30] ( + .CK(n_0_46), .D(registers[30]), .Q(registers_16__ap[30]), .QN(), .SE(dftIn), + .SI(registers_14__ap[31]) + ); + SDFF_X1_LVT \registers_reg[31][30] ( + .CK(n_0_61), .D(registers[30]), .Q(registers_31__ap[30]), .QN(), .SE(dftIn), + .SI(registers_3__ap[31]) + ); + AOI22_X1_LVT i_1_0_1303( + .A1(registers_16__ap[30]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[30]), + .ZN(n_1_0_1240) + ); + SDFF_X1_LVT \registers_reg[6][30] ( + .CK(n_0_36), .D(registers[30]), .Q(registers_6__ap[30]), .QN(), .SE(dftIn), + .SI(registers_31__ap[30]) + ); + SDFF_X1_LVT \registers_reg[1][30] ( + .CK(n_0_0), .D(registers[30]), .Q(registers_1__ap[30]), .QN(), .SE(dftIn), + .SI(registers_17__ap[30]) + ); + AOI22_X1_LVT i_1_0_1299( + .A1(registers_6__ap[30]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[30]), + .ZN(n_1_0_1236) + ); + SDFF_X1_LVT \registers_reg[23][30] ( + .CK(n_0_53), .D(registers[30]), .Q(registers_23__ap[30]), .QN(), .SE(dftIn), + .SI(registers_1__ap[30]) + ); + SDFF_X1_LVT \registers_reg[7][30] ( + .CK(n_0_37), .D(registers[30]), .Q(registers_7__ap[30]), .QN(), .SE(dftIn), + .SI(registers_6__ap[30]) + ); + AOI22_X1_LVT i_1_0_1302( + .A1(registers_23__ap[30]), .A2(n_1_0_1264), .B1(n_1_0_1263), .B2(registers_7__ap[30]), + .ZN(n_1_0_1239) + ); + INV_X1_LVT i_1_0_1301( + .A(n_1_0_1239), .ZN(n_1_0_1238) + ); + SDFF_X1_LVT \registers_reg[19][30] ( + .CK(n_0_49), .D(registers[30]), .Q(registers_19__ap[30]), .QN(), .SE(dftIn), + .SI(registers_23__ap[30]) + ); + SDFF_X1_LVT \registers_reg[5][30] ( + .CK(n_0_35), .D(registers[30]), .Q(registers_5__ap[30]), .QN(), .SE(dftIn), + .SI(registers_7__ap[30]) + ); + AOI221_X1_LVT i_1_0_1298( + .A(n_1_0_1238), .B1(n_1_0_1295), .B2(registers_19__ap[30]), .C1(registers_5__ap[30]), + .C2(n_1_0_1273), .ZN(n_1_0_1235) + ); + SDFF_X1_LVT \registers_reg[10][30] ( + .CK(n_0_40), .D(registers[30]), .Q(registers_10__ap[30]), .QN(), .SE(dftIn), + .SI(registers_16__ap[30]) + ); + SDFF_X1_LVT \registers_reg[26][30] ( + .CK(n_0_56), .D(registers[30]), .Q(registers_26__ap[30]), .QN(), .SE(dftIn), + .SI(registers_28__ap[30]) + ); + SDFF_X1_LVT \registers_reg[8][30] ( + .CK(n_0_38), .D(registers[30]), .Q(registers_8__ap[30]), .QN(), .SE(dftIn), + .SI(registers_5__ap[30]) + ); + AOI222_X1_LVT i_1_0_1297( + .A1(registers_10__ap[30]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[30]), + .C1(registers_8__ap[30]), .C2(n_1_0_1282), .ZN(n_1_0_1234) + ); + NAND4_X1_LVT i_1_0_1296( + .A1(n_1_0_1240), .A2(n_1_0_1236), .A3(n_1_0_1235), .A4(n_1_0_1234), .ZN(n_1_0_1233) + ); + SDFF_X1_LVT \registers_reg[9][30] ( + .CK(n_0_39), .D(registers[30]), .Q(registers_9__ap[30]), .QN(), .SE(dftIn), + .SI(registers_8__ap[30]) + ); + SDFF_X1_LVT \registers_reg[29][30] ( + .CK(n_0_59), .D(registers[30]), .Q(registers_29__ap[30]), .QN(), .SE(dftIn), + .SI(registers_26__ap[30]) + ); + AOI221_X1_LVT i_1_0_1295( + .A(n_1_0_1233), .B1(n_1_0_1291), .B2(registers_9__ap[30]), .C1(registers_29__ap[30]), + .C2(n_1_0_1276), .ZN(n_1_0_1232) + ); + SDFF_X1_LVT \registers_reg[18][30] ( + .CK(n_0_48), .D(registers[30]), .Q(registers_18__ap[30]), .QN(), .SE(dftIn), + .SI(registers_19__ap[30]) + ); + SDFF_X1_LVT \registers_reg[30][30] ( + .CK(n_0_60), .D(registers[30]), .Q(registers_30__ap[30]), .QN(), .SE(dftIn), + .SI(registers_29__ap[30]) + ); + AOI22_X1_LVT i_1_0_1294( + .A1(registers_18__ap[30]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[30]), + .ZN(n_1_0_1231) + ); + SDFF_X1_LVT \registers_reg[20][30] ( + .CK(n_0_50), .D(registers[30]), .Q(registers_20__ap[30]), .QN(), .SE(dftIn), + .SI(registers_18__ap[30]) + ); + SDFF_X1_LVT \registers_reg[4][30] ( + .CK(n_0_34), .D(registers[30]), .Q(registers_4__ap[30]), .QN(), .SE(dftIn), + .SI(registers_9__ap[30]) + ); + AOI22_X1_LVT i_1_0_1293( + .A1(registers_20__ap[30]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[30]), + .ZN(n_1_0_1230) + ); + SDFF_X1_LVT \registers_reg[22][30] ( + .CK(n_0_52), .D(registers[30]), .Q(registers_22__ap[30]), .QN(), .SE(dftIn), + .SI(registers_20__ap[30]) + ); + SDFF_X1_LVT \registers_reg[21][30] ( + .CK(n_0_51), .D(registers[30]), .Q(registers_21__ap[30]), .QN(), .SE(dftIn), + .SI(registers_22__ap[30]) + ); + AOI22_X1_LVT i_1_0_1292( + .A1(registers_22__ap[30]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[30]), + .ZN(n_1_0_1229) + ); + NAND3_X1_LVT i_1_0_1291( + .A1(n_1_0_1231), .A2(n_1_0_1230), .A3(n_1_0_1229), .ZN(n_1_0_1228) + ); + SDFF_X1_LVT \registers_reg[24][30] ( + .CK(n_0_54), .D(registers[30]), .Q(registers_24__ap[30]), .QN(), .SE(dftIn), + .SI(registers_30__ap[30]) + ); + SDFF_X1_LVT \registers_reg[12][30] ( + .CK(n_0_42), .D(registers[30]), .Q(registers_12__ap[30]), .QN(), .SE(dftIn), + .SI(registers_10__ap[30]) + ); + AOI221_X1_LVT i_1_0_1290( + .A(n_1_0_1228), .B1(n_1_0_1289), .B2(registers_24__ap[30]), .C1(registers_12__ap[30]), + .C2(n_1_0_1260), .ZN(n_1_0_1227) + ); + SDFF_X1_LVT \registers_reg[27][30] ( + .CK(n_0_57), .D(registers[30]), .Q(registers_27__ap[30]), .QN(), .SE(dftIn), + .SI(registers_24__ap[30]) + ); + SDFF_X1_LVT \registers_reg[11][30] ( + .CK(n_0_41), .D(registers[30]), .Q(registers_11__ap[30]), .QN(), .SE(dftIn), + .SI(registers_12__ap[30]) + ); + AOI22_X1_LVT i_1_0_1289( + .A1(registers_27__ap[30]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[30]), + .ZN(n_1_0_1226) + ); + SDFF_X1_LVT \registers_reg[13][30] ( + .CK(n_0_43), .D(registers[30]), .Q(registers_13__ap[30]), .QN(), .SE(dftIn), + .SI(registers_11__ap[30]) + ); + SDFF_X1_LVT \registers_reg[25][30] ( + .CK(n_0_55), .D(registers[30]), .Q(registers_25__ap[30]), .QN(), .SE(dftIn), + .SI(registers_27__ap[30]) + ); + AOI22_X1_LVT i_1_0_1288( + .A1(registers_13__ap[30]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[30]), + .ZN(n_1_0_1225) + ); + SDFF_X1_LVT \registers_reg[15][30] ( + .CK(n_0_45), .D(registers[30]), .Q(registers_15__ap[30]), .QN(), .SE(dftIn), + .SI(registers_13__ap[30]) + ); + SDFF_X1_LVT \registers_reg[14][30] ( + .CK(n_0_44), .D(registers[30]), .Q(registers_14__ap[30]), .QN(), .SE(dftIn), + .SI(registers_15__ap[30]) + ); + AOI22_X1_LVT i_1_0_1287( + .A1(registers_15__ap[30]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[30]), + .ZN(n_1_0_1224) + ); + NAND3_X1_LVT i_1_0_1286( + .A1(n_1_0_1226), .A2(n_1_0_1225), .A3(n_1_0_1224), .ZN(n_1_0_1223) + ); + SDFF_X1_LVT \registers_reg[3][30] ( + .CK(n_0_33), .D(registers[30]), .Q(registers_3__ap[30]), .QN(), .SE(dftIn), + .SI(registers_4__ap[30]) + ); + SDFF_X1_LVT \registers_reg[2][30] ( + .CK(n_0_32), .D(registers[30]), .Q(registers_2__ap[30]), .QN(), .SE(dftIn), + .SI(registers_25__ap[30]) + ); + AOI221_X1_LVT i_1_0_1285( + .A(n_1_0_1223), .B1(n_1_0_1257), .B2(registers_3__ap[30]), .C1(registers_2__ap[30]), + .C2(n_1_0_1268), .ZN(n_1_0_1222) + ); + NAND4_X1_LVT i_1_0_1284( + .A1(n_1_0_1237), .A2(n_1_0_1232), .A3(n_1_0_1227), .A4(n_1_0_1222), .ZN(RRs1[30]) + ); + AND2_X1_LVT i_0_0_29( + .A1(n_0_0_16), .A2(WRd[29]), .ZN(registers[29]) + ); + SDFF_X1_LVT \registers_reg[28][29] ( + .CK(n_0_58), .D(registers[29]), .Q(registers_28__ap[29]), .QN(), .SE(dftIn), + .SI(registers_2__ap[30]) + ); + SDFF_X1_LVT \registers_reg[8][29] ( + .CK(n_0_38), .D(registers[29]), .Q(registers_8__ap[29]), .QN(), .SE(dftIn), + .SI(registers_3__ap[30]) + ); + AOI22_X1_LVT i_1_0_1282( + .A1(registers_28__ap[29]), .A2(n_1_0_1283), .B1(n_1_0_1282), .B2(registers_8__ap[29]), + .ZN(n_1_0_1220) + ); + SDFF_X1_LVT \registers_reg[31][29] ( + .CK(n_0_61), .D(registers[29]), .Q(registers_31__ap[29]), .QN(), .SE(dftIn), + .SI(registers_8__ap[29]) + ); + SDFF_X1_LVT \registers_reg[7][29] ( + .CK(n_0_37), .D(registers[29]), .Q(registers_7__ap[29]), .QN(), .SE(dftIn), + .SI(registers_31__ap[29]) + ); + AOI22_X1_LVT i_1_0_1283( + .A1(registers_31__ap[29]), .A2(n_1_0_1266), .B1(n_1_0_1263), .B2(registers_7__ap[29]), + .ZN(n_1_0_1221) + ); + SDFF_X1_LVT \registers_reg[24][29] ( + .CK(n_0_54), .D(registers[29]), .Q(registers_24__ap[29]), .QN(), .SE(dftIn), + .SI(registers_28__ap[29]) + ); + SDFF_X1_LVT \registers_reg[20][29] ( + .CK(n_0_50), .D(registers[29]), .Q(registers_20__ap[29]), .QN(), .SE(dftIn), + .SI(registers_21__ap[30]) + ); + AOI22_X1_LVT i_1_0_1281( + .A1(registers_24__ap[29]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[29]), + .ZN(n_1_0_1219) + ); + SDFF_X1_LVT \registers_reg[19][29] ( + .CK(n_0_49), .D(registers[29]), .Q(registers_19__ap[29]), .QN(), .SE(dftIn), + .SI(registers_20__ap[29]) + ); + SDFF_X1_LVT \registers_reg[4][29] ( + .CK(n_0_34), .D(registers[29]), .Q(registers_4__ap[29]), .QN(), .SE(dftIn), + .SI(registers_7__ap[29]) + ); + AOI22_X1_LVT i_1_0_1280( + .A1(registers_19__ap[29]), .A2(n_1_0_1295), .B1(n_1_0_1278), .B2(registers_4__ap[29]), + .ZN(n_1_0_1218) + ); + NAND3_X1_LVT i_1_0_1279( + .A1(n_1_0_1221), .A2(n_1_0_1219), .A3(n_1_0_1218), .ZN(n_1_0_1217) + ); + SDFF_X1_LVT \registers_reg[23][29] ( + .CK(n_0_53), .D(registers[29]), .Q(registers_23__ap[29]), .QN(), .SE(dftIn), + .SI(registers_19__ap[29]) + ); + SDFF_X1_LVT \registers_reg[29][29] ( + .CK(n_0_59), .D(registers[29]), .Q(registers_29__ap[29]), .QN(), .SE(dftIn), + .SI(registers_24__ap[29]) + ); + AOI221_X1_LVT i_1_0_1278( + .A(n_1_0_1217), .B1(n_1_0_1264), .B2(registers_23__ap[29]), .C1(registers_29__ap[29]), + .C2(n_1_0_1276), .ZN(n_1_0_1216) + ); + SDFF_X1_LVT \registers_reg[10][29] ( + .CK(n_0_40), .D(registers[29]), .Q(registers_10__ap[29]), .QN(), .SE(dftIn), + .SI(registers_14__ap[30]) + ); + SDFF_X1_LVT \registers_reg[26][29] ( + .CK(n_0_56), .D(registers[29]), .Q(registers_26__ap[29]), .QN(), .SE(dftIn), + .SI(registers_29__ap[29]) + ); + SDFF_X1_LVT \registers_reg[25][29] ( + .CK(n_0_55), .D(registers[29]), .Q(registers_25__ap[29]), .QN(), .SE(dftIn), + .SI(registers_26__ap[29]) + ); + AOI222_X1_LVT i_1_0_1277( + .A1(registers_10__ap[29]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[29]), + .C1(registers_25__ap[29]), .C2(n_1_0_1269), .ZN(n_1_0_1215) + ); + NAND3_X1_LVT i_1_0_1276( + .A1(n_1_0_1220), .A2(n_1_0_1216), .A3(n_1_0_1215), .ZN(n_1_0_1214) + ); + SDFF_X1_LVT \registers_reg[21][29] ( + .CK(n_0_51), .D(registers[29]), .Q(registers_21__ap[29]), .QN(), .SE(dftIn), + .SI(registers_23__ap[29]) + ); + SDFF_X1_LVT \registers_reg[13][29] ( + .CK(n_0_43), .D(registers[29]), .Q(registers_13__ap[29]), .QN(), .SE(dftIn), + .SI(registers_10__ap[29]) + ); + AOI221_X1_LVT i_1_0_1275( + .A(n_1_0_1214), .B1(n_1_0_1259), .B2(registers_21__ap[29]), .C1(registers_13__ap[29]), + .C2(n_1_0_1277), .ZN(n_1_0_1213) + ); + SDFF_X1_LVT \registers_reg[18][29] ( + .CK(n_0_48), .D(registers[29]), .Q(registers_18__ap[29]), .QN(), .SE(dftIn), + .SI(registers_21__ap[29]) + ); + SDFF_X1_LVT \registers_reg[30][29] ( + .CK(n_0_60), .D(registers[29]), .Q(registers_30__ap[29]), .QN(), .SE(dftIn), + .SI(registers_25__ap[29]) + ); + AOI22_X1_LVT i_1_0_1274( + .A1(registers_18__ap[29]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[29]), + .ZN(n_1_0_1212) + ); + SDFF_X1_LVT \registers_reg[17][29] ( + .CK(n_0_47), .D(registers[29]), .Q(registers_17__ap[29]), .QN(), .SE(dftIn), + .SI(registers_18__ap[29]) + ); + SDFF_X1_LVT \registers_reg[12][29] ( + .CK(n_0_42), .D(registers[29]), .Q(registers_12__ap[29]), .QN(), .SE(dftIn), + .SI(registers_13__ap[29]) + ); + AOI22_X1_LVT i_1_0_1273( + .A1(registers_17__ap[29]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[29]), + .ZN(n_1_0_1211) + ); + SDFF_X1_LVT \registers_reg[15][29] ( + .CK(n_0_45), .D(registers[29]), .Q(registers_15__ap[29]), .QN(), .SE(dftIn), + .SI(registers_12__ap[29]) + ); + SDFF_X1_LVT \registers_reg[16][29] ( + .CK(n_0_46), .D(registers[29]), .Q(registers_16__ap[29]), .QN(), .SE(dftIn), + .SI(registers_15__ap[29]) + ); + AOI22_X1_LVT i_1_0_1272( + .A1(registers_15__ap[29]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[29]), + .ZN(n_1_0_1210) + ); + NAND3_X1_LVT i_1_0_1271( + .A1(n_1_0_1212), .A2(n_1_0_1211), .A3(n_1_0_1210), .ZN(n_1_0_1209) + ); + SDFF_X1_LVT \registers_reg[22][29] ( + .CK(n_0_52), .D(registers[29]), .Q(registers_22__ap[29]), .QN(), .SE(dftIn), + .SI(registers_17__ap[29]) + ); + SDFF_X1_LVT \registers_reg[5][29] ( + .CK(n_0_35), .D(registers[29]), .Q(registers_5__ap[29]), .QN(), .SE(dftIn), + .SI(registers_4__ap[29]) + ); + AOI221_X1_LVT i_1_0_1270( + .A(n_1_0_1209), .B1(n_1_0_1294), .B2(registers_22__ap[29]), .C1(registers_5__ap[29]), + .C2(n_1_0_1273), .ZN(n_1_0_1208) + ); + SDFF_X1_LVT \registers_reg[9][29] ( + .CK(n_0_39), .D(registers[29]), .Q(registers_9__ap[29]), .QN(), .SE(dftIn), + .SI(registers_5__ap[29]) + ); + SDFF_X1_LVT \registers_reg[1][29] ( + .CK(n_0_0), .D(registers[29]), .Q(registers_1__ap[29]), .QN(), .SE(dftIn), + .SI(registers_22__ap[29]) + ); + AOI22_X1_LVT i_1_0_1269( + .A1(registers_9__ap[29]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[29]), + .ZN(n_1_0_1207) + ); + SDFF_X1_LVT \registers_reg[6][29] ( + .CK(n_0_36), .D(registers[29]), .Q(registers_6__ap[29]), .QN(), .SE(dftIn), + .SI(registers_9__ap[29]) + ); + SDFF_X1_LVT \registers_reg[14][29] ( + .CK(n_0_44), .D(registers[29]), .Q(registers_14__ap[29]), .QN(), .SE(dftIn), + .SI(registers_16__ap[29]) + ); + AOI22_X1_LVT i_1_0_1268( + .A1(registers_6__ap[29]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[29]), + .ZN(n_1_0_1206) + ); + SDFF_X1_LVT \registers_reg[27][29] ( + .CK(n_0_57), .D(registers[29]), .Q(registers_27__ap[29]), .QN(), .SE(dftIn), + .SI(registers_30__ap[29]) + ); + SDFF_X1_LVT \registers_reg[11][29] ( + .CK(n_0_41), .D(registers[29]), .Q(registers_11__ap[29]), .QN(), .SE(dftIn), + .SI(registers_14__ap[29]) + ); + AOI22_X1_LVT i_1_0_1267( + .A1(registers_27__ap[29]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[29]), + .ZN(n_1_0_1205) + ); + NAND3_X1_LVT i_1_0_1266( + .A1(n_1_0_1207), .A2(n_1_0_1206), .A3(n_1_0_1205), .ZN(n_1_0_1204) + ); + SDFF_X1_LVT \registers_reg[3][29] ( + .CK(n_0_33), .D(registers[29]), .Q(registers_3__ap[29]), .QN(), .SE(dftIn), + .SI(registers_6__ap[29]) + ); + SDFF_X1_LVT \registers_reg[2][29] ( + .CK(n_0_32), .D(registers[29]), .Q(registers_2__ap[29]), .QN(), .SE(dftIn), + .SI(registers_27__ap[29]) + ); + AOI221_X1_LVT i_1_0_1265( + .A(n_1_0_1204), .B1(n_1_0_1257), .B2(registers_3__ap[29]), .C1(registers_2__ap[29]), + .C2(n_1_0_1268), .ZN(n_1_0_1203) + ); + NAND3_X1_LVT i_1_0_1264( + .A1(n_1_0_1213), .A2(n_1_0_1208), .A3(n_1_0_1203), .ZN(RRs1[29]) + ); + AND2_X1_LVT i_0_0_28( + .A1(n_0_0_16), .A2(WRd[28]), .ZN(registers[28]) + ); + SDFF_X1_LVT \registers_reg[15][28] ( + .CK(n_0_45), .D(registers[28]), .Q(registers_15__ap[28]), .QN(), .SE(dftIn), + .SI(registers_11__ap[29]) + ); + SDFF_X1_LVT \registers_reg[26][28] ( + .CK(n_0_56), .D(registers[28]), .Q(registers_26__ap[28]), .QN(), .SE(dftIn), + .SI(registers_2__ap[29]) + ); + SDFF_X1_LVT \registers_reg[22][28] ( + .CK(n_0_52), .D(registers[28]), .Q(registers_22__ap[28]), .QN(), .SE(dftIn), + .SI(registers_1__ap[29]) + ); + AOI222_X1_LVT i_1_0_1263( + .A1(registers_15__ap[28]), .A2(n_1_0_1286), .B1(n_1_0_1285), .B2(registers_26__ap[28]), + .C1(registers_22__ap[28]), .C2(n_1_0_1294), .ZN(n_1_0_1202) + ); + SDFF_X1_LVT \registers_reg[5][28] ( + .CK(n_0_35), .D(registers[28]), .Q(registers_5__ap[28]), .QN(), .SE(dftIn), + .SI(registers_3__ap[29]) + ); + SDFF_X1_LVT \registers_reg[12][28] ( + .CK(n_0_42), .D(registers[28]), .Q(registers_12__ap[28]), .QN(), .SE(dftIn), + .SI(registers_15__ap[28]) + ); + AOI22_X1_LVT i_1_0_1262( + .A1(registers_5__ap[28]), .A2(n_1_0_1273), .B1(n_1_0_1260), .B2(registers_12__ap[28]), + .ZN(n_1_0_1201) + ); + SDFF_X1_LVT \registers_reg[28][28] ( + .CK(n_0_58), .D(registers[28]), .Q(registers_28__ap[28]), .QN(), .SE(dftIn), + .SI(registers_26__ap[28]) + ); + SDFF_X1_LVT \registers_reg[14][28] ( + .CK(n_0_44), .D(registers[28]), .Q(registers_14__ap[28]), .QN(), .SE(dftIn), + .SI(registers_12__ap[28]) + ); + AOI22_X1_LVT i_1_0_1261( + .A1(registers_28__ap[28]), .A2(n_1_0_1283), .B1(n_1_0_1258), .B2(registers_14__ap[28]), + .ZN(n_1_0_1200) + ); + SDFF_X1_LVT \registers_reg[17][28] ( + .CK(n_0_47), .D(registers[28]), .Q(registers_17__ap[28]), .QN(), .SE(dftIn), + .SI(registers_22__ap[28]) + ); + SDFF_X1_LVT \registers_reg[2][28] ( + .CK(n_0_32), .D(registers[28]), .Q(registers_2__ap[28]), .QN(), .SE(dftIn), + .SI(registers_28__ap[28]) + ); + AOI22_X1_LVT i_1_0_1260( + .A1(registers_17__ap[28]), .A2(n_1_0_1271), .B1(n_1_0_1268), .B2(registers_2__ap[28]), + .ZN(n_1_0_1199) + ); + NAND3_X1_LVT i_1_0_1259( + .A1(n_1_0_1201), .A2(n_1_0_1200), .A3(n_1_0_1199), .ZN(n_1_0_1198) + ); + SDFF_X1_LVT \registers_reg[9][28] ( + .CK(n_0_39), .D(registers[28]), .Q(registers_9__ap[28]), .QN(), .SE(dftIn), + .SI(registers_5__ap[28]) + ); + SDFF_X1_LVT \registers_reg[29][28] ( + .CK(n_0_59), .D(registers[28]), .Q(registers_29__ap[28]), .QN(), .SE(dftIn), + .SI(registers_2__ap[28]) + ); + AOI221_X1_LVT i_1_0_1258( + .A(n_1_0_1198), .B1(n_1_0_1291), .B2(registers_9__ap[28]), .C1(registers_29__ap[28]), + .C2(n_1_0_1276), .ZN(n_1_0_1197) + ); + SDFF_X1_LVT \registers_reg[13][28] ( + .CK(n_0_43), .D(registers[28]), .Q(registers_13__ap[28]), .QN(), .SE(dftIn), + .SI(registers_14__ap[28]) + ); + SDFF_X1_LVT \registers_reg[25][28] ( + .CK(n_0_55), .D(registers[28]), .Q(registers_25__ap[28]), .QN(), .SE(dftIn), + .SI(registers_29__ap[28]) + ); + AOI22_X1_LVT i_1_0_1257( + .A1(registers_13__ap[28]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[28]), + .ZN(n_1_0_1196) + ); + NAND3_X1_LVT i_1_0_1256( + .A1(n_1_0_1202), .A2(n_1_0_1197), .A3(n_1_0_1196), .ZN(n_1_0_1195) + ); + SDFF_X1_LVT \registers_reg[4][28] ( + .CK(n_0_34), .D(registers[28]), .Q(registers_4__ap[28]), .QN(), .SE(dftIn), + .SI(registers_9__ap[28]) + ); + SDFF_X1_LVT \registers_reg[20][28] ( + .CK(n_0_50), .D(registers[28]), .Q(registers_20__ap[28]), .QN(), .SE(dftIn), + .SI(registers_17__ap[28]) + ); + AOI221_X1_LVT i_1_0_1255( + .A(n_1_0_1195), .B1(n_1_0_1278), .B2(registers_4__ap[28]), .C1(registers_20__ap[28]), + .C2(n_1_0_1281), .ZN(n_1_0_1194) + ); + SDFF_X1_LVT \registers_reg[1][28] ( + .CK(n_0_0), .D(registers[28]), .Q(registers_1__ap[28]), .QN(), .SE(dftIn), + .SI(registers_20__ap[28]) + ); + SDFF_X1_LVT \registers_reg[23][28] ( + .CK(n_0_53), .D(registers[28]), .Q(registers_23__ap[28]), .QN(), .SE(dftIn), + .SI(registers_1__ap[28]) + ); + AOI22_X1_LVT i_1_0_1254( + .A1(registers_1__ap[28]), .A2(n_1_0_1274), .B1(n_1_0_1264), .B2(registers_23__ap[28]), + .ZN(n_1_0_1193) + ); + SDFF_X1_LVT \registers_reg[10][28] ( + .CK(n_0_40), .D(registers[28]), .Q(registers_10__ap[28]), .QN(), .SE(dftIn), + .SI(registers_13__ap[28]) + ); + SDFF_X1_LVT \registers_reg[21][28] ( + .CK(n_0_51), .D(registers[28]), .Q(registers_21__ap[28]), .QN(), .SE(dftIn), + .SI(registers_23__ap[28]) + ); + AOI22_X1_LVT i_1_0_1253( + .A1(registers_10__ap[28]), .A2(n_1_0_1287), .B1(n_1_0_1259), .B2(registers_21__ap[28]), + .ZN(n_1_0_1192) + ); + SDFF_X1_LVT \registers_reg[6][28] ( + .CK(n_0_36), .D(registers[28]), .Q(registers_6__ap[28]), .QN(), .SE(dftIn), + .SI(registers_4__ap[28]) + ); + SDFF_X1_LVT \registers_reg[30][28] ( + .CK(n_0_60), .D(registers[28]), .Q(registers_30__ap[28]), .QN(), .SE(dftIn), + .SI(registers_25__ap[28]) + ); + AOI22_X1_LVT i_1_0_1252( + .A1(registers_6__ap[28]), .A2(n_1_0_1300), .B1(n_1_0_1272), .B2(registers_30__ap[28]), + .ZN(n_1_0_1191) + ); + NAND3_X1_LVT i_1_0_1251( + .A1(n_1_0_1193), .A2(n_1_0_1192), .A3(n_1_0_1191), .ZN(n_1_0_1190) + ); + SDFF_X1_LVT \registers_reg[8][28] ( + .CK(n_0_38), .D(registers[28]), .Q(registers_8__ap[28]), .QN(), .SE(dftIn), + .SI(registers_6__ap[28]) + ); + SDFF_X1_LVT \registers_reg[24][28] ( + .CK(n_0_54), .D(registers[28]), .Q(registers_24__ap[28]), .QN(), .SE(dftIn), + .SI(registers_30__ap[28]) + ); + AOI221_X1_LVT i_1_0_1250( + .A(n_1_0_1190), .B1(n_1_0_1282), .B2(registers_8__ap[28]), .C1(registers_24__ap[28]), + .C2(n_1_0_1289), .ZN(n_1_0_1189) + ); + SDFF_X1_LVT \registers_reg[16][28] ( + .CK(n_0_46), .D(registers[28]), .Q(registers_16__ap[28]), .QN(), .SE(dftIn), + .SI(registers_10__ap[28]) + ); + SDFF_X1_LVT \registers_reg[3][28] ( + .CK(n_0_33), .D(registers[28]), .Q(registers_3__ap[28]), .QN(), .SE(dftIn), + .SI(registers_8__ap[28]) + ); + AOI22_X1_LVT i_1_0_1249( + .A1(registers_16__ap[28]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[28]), + .ZN(n_1_0_1188) + ); + SDFF_X1_LVT \registers_reg[11][28] ( + .CK(n_0_41), .D(registers[28]), .Q(registers_11__ap[28]), .QN(), .SE(dftIn), + .SI(registers_16__ap[28]) + ); + SDFF_X1_LVT \registers_reg[31][28] ( + .CK(n_0_61), .D(registers[28]), .Q(registers_31__ap[28]), .QN(), .SE(dftIn), + .SI(registers_3__ap[28]) + ); + AOI22_X1_LVT i_1_0_1248( + .A1(registers_11__ap[28]), .A2(n_1_0_1270), .B1(n_1_0_1266), .B2(registers_31__ap[28]), + .ZN(n_1_0_1187) + ); + SDFF_X1_LVT \registers_reg[27][28] ( + .CK(n_0_57), .D(registers[28]), .Q(registers_27__ap[28]), .QN(), .SE(dftIn), + .SI(registers_24__ap[28]) + ); + SDFF_X1_LVT \registers_reg[7][28] ( + .CK(n_0_37), .D(registers[28]), .Q(registers_7__ap[28]), .QN(), .SE(dftIn), + .SI(registers_31__ap[28]) + ); + AOI22_X1_LVT i_1_0_1247( + .A1(registers_27__ap[28]), .A2(n_1_0_1279), .B1(n_1_0_1263), .B2(registers_7__ap[28]), + .ZN(n_1_0_1186) + ); + NAND3_X1_LVT i_1_0_1246( + .A1(n_1_0_1188), .A2(n_1_0_1187), .A3(n_1_0_1186), .ZN(n_1_0_1185) + ); + SDFF_X1_LVT \registers_reg[19][28] ( + .CK(n_0_49), .D(registers[28]), .Q(registers_19__ap[28]), .QN(), .SE(dftIn), + .SI(registers_21__ap[28]) + ); + SDFF_X1_LVT \registers_reg[18][28] ( + .CK(n_0_48), .D(registers[28]), .Q(registers_18__ap[28]), .QN(), .SE(dftIn), + .SI(registers_19__ap[28]) + ); + AOI221_X1_LVT i_1_0_1245( + .A(n_1_0_1185), .B1(n_1_0_1295), .B2(registers_19__ap[28]), .C1(registers_18__ap[28]), + .C2(n_1_0_1297), .ZN(n_1_0_1184) + ); + NAND3_X1_LVT i_1_0_1244( + .A1(n_1_0_1194), .A2(n_1_0_1189), .A3(n_1_0_1184), .ZN(RRs1[28]) + ); + AND2_X1_LVT i_0_0_27( + .A1(n_0_0_16), .A2(WRd[27]), .ZN(registers[27]) + ); + SDFF_X1_LVT \registers_reg[29][27] ( + .CK(n_0_59), .D(registers[27]), .Q(registers_29__ap[27]), .QN(), .SE(dftIn), + .SI(registers_27__ap[28]) + ); + SDFF_X1_LVT \registers_reg[2][27] ( + .CK(n_0_32), .D(registers[27]), .Q(registers_2__ap[27]), .QN(), .SE(dftIn), + .SI(registers_29__ap[27]) + ); + AOI22_X1_LVT i_1_0_1242( + .A1(registers_29__ap[27]), .A2(n_1_0_1276), .B1(n_1_0_1268), .B2(registers_2__ap[27]), + .ZN(n_1_0_1182) + ); + SDFF_X1_LVT \registers_reg[8][27] ( + .CK(n_0_38), .D(registers[27]), .Q(registers_8__ap[27]), .QN(), .SE(dftIn), + .SI(registers_7__ap[28]) + ); + SDFF_X1_LVT \registers_reg[25][27] ( + .CK(n_0_55), .D(registers[27]), .Q(registers_25__ap[27]), .QN(), .SE(dftIn), + .SI(registers_2__ap[27]) + ); + AOI22_X1_LVT i_1_0_1243( + .A1(registers_8__ap[27]), .A2(n_1_0_1282), .B1(n_1_0_1269), .B2(registers_25__ap[27]), + .ZN(n_1_0_1183) + ); + SDFF_X1_LVT \registers_reg[9][27] ( + .CK(n_0_39), .D(registers[27]), .Q(registers_9__ap[27]), .QN(), .SE(dftIn), + .SI(registers_8__ap[27]) + ); + SDFF_X1_LVT \registers_reg[7][27] ( + .CK(n_0_37), .D(registers[27]), .Q(registers_7__ap[27]), .QN(), .SE(dftIn), + .SI(registers_9__ap[27]) + ); + AOI22_X1_LVT i_1_0_1241( + .A1(registers_9__ap[27]), .A2(n_1_0_1291), .B1(n_1_0_1263), .B2(registers_7__ap[27]), + .ZN(n_1_0_1181) + ); + SDFF_X1_LVT \registers_reg[11][27] ( + .CK(n_0_41), .D(registers[27]), .Q(registers_11__ap[27]), .QN(), .SE(dftIn), + .SI(registers_11__ap[28]) + ); + SDFF_X1_LVT \registers_reg[16][27] ( + .CK(n_0_46), .D(registers[27]), .Q(registers_16__ap[27]), .QN(), .SE(dftIn), + .SI(registers_11__ap[27]) + ); + AOI22_X1_LVT i_1_0_1240( + .A1(registers_11__ap[27]), .A2(n_1_0_1270), .B1(n_1_0_1267), .B2(registers_16__ap[27]), + .ZN(n_1_0_1180) + ); + NAND3_X1_LVT i_1_0_1239( + .A1(n_1_0_1183), .A2(n_1_0_1181), .A3(n_1_0_1180), .ZN(n_1_0_1179) + ); + SDFF_X1_LVT \registers_reg[10][27] ( + .CK(n_0_40), .D(registers[27]), .Q(registers_10__ap[27]), .QN(), .SE(dftIn), + .SI(registers_16__ap[27]) + ); + SDFF_X1_LVT \registers_reg[6][27] ( + .CK(n_0_36), .D(registers[27]), .Q(registers_6__ap[27]), .QN(), .SE(dftIn), + .SI(registers_7__ap[27]) + ); + AOI221_X1_LVT i_1_0_1238( + .A(n_1_0_1179), .B1(n_1_0_1287), .B2(registers_10__ap[27]), .C1(registers_6__ap[27]), + .C2(n_1_0_1300), .ZN(n_1_0_1178) + ); + SDFF_X1_LVT \registers_reg[1][27] ( + .CK(n_0_0), .D(registers[27]), .Q(registers_1__ap[27]), .QN(), .SE(dftIn), + .SI(registers_18__ap[28]) + ); + SDFF_X1_LVT \registers_reg[30][27] ( + .CK(n_0_60), .D(registers[27]), .Q(registers_30__ap[27]), .QN(), .SE(dftIn), + .SI(registers_25__ap[27]) + ); + SDFF_X1_LVT \registers_reg[22][27] ( + .CK(n_0_52), .D(registers[27]), .Q(registers_22__ap[27]), .QN(), .SE(dftIn), + .SI(registers_1__ap[27]) + ); + AOI222_X1_LVT i_1_0_1237( + .A1(registers_1__ap[27]), .A2(n_1_0_1274), .B1(n_1_0_1272), .B2(registers_30__ap[27]), + .C1(registers_22__ap[27]), .C2(n_1_0_1294), .ZN(n_1_0_1177) + ); + NAND3_X1_LVT i_1_0_1236( + .A1(n_1_0_1182), .A2(n_1_0_1178), .A3(n_1_0_1177), .ZN(n_1_0_1176) + ); + SDFF_X1_LVT \registers_reg[5][27] ( + .CK(n_0_35), .D(registers[27]), .Q(registers_5__ap[27]), .QN(), .SE(dftIn), + .SI(registers_6__ap[27]) + ); + SDFF_X1_LVT \registers_reg[28][27] ( + .CK(n_0_58), .D(registers[27]), .Q(registers_28__ap[27]), .QN(), .SE(dftIn), + .SI(registers_30__ap[27]) + ); + AOI221_X1_LVT i_1_0_1235( + .A(n_1_0_1176), .B1(n_1_0_1273), .B2(registers_5__ap[27]), .C1(registers_28__ap[27]), + .C2(n_1_0_1283), .ZN(n_1_0_1175) + ); + SDFF_X1_LVT \registers_reg[4][27] ( + .CK(n_0_34), .D(registers[27]), .Q(registers_4__ap[27]), .QN(), .SE(dftIn), + .SI(registers_5__ap[27]) + ); + SDFF_X1_LVT \registers_reg[12][27] ( + .CK(n_0_42), .D(registers[27]), .Q(registers_12__ap[27]), .QN(), .SE(dftIn), + .SI(registers_10__ap[27]) + ); + AOI22_X1_LVT i_1_0_1234( + .A1(registers_4__ap[27]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[27]), + .ZN(n_1_0_1174) + ); + SDFF_X1_LVT \registers_reg[19][27] ( + .CK(n_0_49), .D(registers[27]), .Q(registers_19__ap[27]), .QN(), .SE(dftIn), + .SI(registers_22__ap[27]) + ); + SDFF_X1_LVT \registers_reg[21][27] ( + .CK(n_0_51), .D(registers[27]), .Q(registers_21__ap[27]), .QN(), .SE(dftIn), + .SI(registers_19__ap[27]) + ); + AOI22_X1_LVT i_1_0_1233( + .A1(registers_19__ap[27]), .A2(n_1_0_1295), .B1(n_1_0_1259), .B2(registers_21__ap[27]), + .ZN(n_1_0_1173) + ); + SDFF_X1_LVT \registers_reg[24][27] ( + .CK(n_0_54), .D(registers[27]), .Q(registers_24__ap[27]), .QN(), .SE(dftIn), + .SI(registers_28__ap[27]) + ); + SDFF_X1_LVT \registers_reg[20][27] ( + .CK(n_0_50), .D(registers[27]), .Q(registers_20__ap[27]), .QN(), .SE(dftIn), + .SI(registers_21__ap[27]) + ); + AOI22_X1_LVT i_1_0_1232( + .A1(registers_24__ap[27]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[27]), + .ZN(n_1_0_1172) + ); + NAND3_X1_LVT i_1_0_1231( + .A1(n_1_0_1174), .A2(n_1_0_1173), .A3(n_1_0_1172), .ZN(n_1_0_1171) + ); + SDFF_X1_LVT \registers_reg[18][27] ( + .CK(n_0_48), .D(registers[27]), .Q(registers_18__ap[27]), .QN(), .SE(dftIn), + .SI(registers_20__ap[27]) + ); + SDFF_X1_LVT \registers_reg[26][27] ( + .CK(n_0_56), .D(registers[27]), .Q(registers_26__ap[27]), .QN(), .SE(dftIn), + .SI(registers_24__ap[27]) + ); + AOI221_X1_LVT i_1_0_1230( + .A(n_1_0_1171), .B1(n_1_0_1297), .B2(registers_18__ap[27]), .C1(registers_26__ap[27]), + .C2(n_1_0_1285), .ZN(n_1_0_1170) + ); + SDFF_X1_LVT \registers_reg[23][27] ( + .CK(n_0_53), .D(registers[27]), .Q(registers_23__ap[27]), .QN(), .SE(dftIn), + .SI(registers_18__ap[27]) + ); + SDFF_X1_LVT \registers_reg[3][27] ( + .CK(n_0_33), .D(registers[27]), .Q(registers_3__ap[27]), .QN(), .SE(dftIn), + .SI(registers_4__ap[27]) + ); + AOI22_X1_LVT i_1_0_1229( + .A1(registers_23__ap[27]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[27]), + .ZN(n_1_0_1169) + ); + SDFF_X1_LVT \registers_reg[13][27] ( + .CK(n_0_43), .D(registers[27]), .Q(registers_13__ap[27]), .QN(), .SE(dftIn), + .SI(registers_12__ap[27]) + ); + SDFF_X1_LVT \registers_reg[17][27] ( + .CK(n_0_47), .D(registers[27]), .Q(registers_17__ap[27]), .QN(), .SE(dftIn), + .SI(registers_23__ap[27]) + ); + AOI22_X1_LVT i_1_0_1228( + .A1(registers_13__ap[27]), .A2(n_1_0_1277), .B1(n_1_0_1271), .B2(registers_17__ap[27]), + .ZN(n_1_0_1168) + ); + SDFF_X1_LVT \registers_reg[15][27] ( + .CK(n_0_45), .D(registers[27]), .Q(registers_15__ap[27]), .QN(), .SE(dftIn), + .SI(registers_13__ap[27]) + ); + SDFF_X1_LVT \registers_reg[14][27] ( + .CK(n_0_44), .D(registers[27]), .Q(registers_14__ap[27]), .QN(), .SE(dftIn), + .SI(registers_15__ap[27]) + ); + AOI22_X1_LVT i_1_0_1227( + .A1(registers_15__ap[27]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[27]), + .ZN(n_1_0_1167) + ); + NAND3_X1_LVT i_1_0_1226( + .A1(n_1_0_1169), .A2(n_1_0_1168), .A3(n_1_0_1167), .ZN(n_1_0_1166) + ); + SDFF_X1_LVT \registers_reg[27][27] ( + .CK(n_0_57), .D(registers[27]), .Q(registers_27__ap[27]), .QN(), .SE(dftIn), + .SI(registers_26__ap[27]) + ); + SDFF_X1_LVT \registers_reg[31][27] ( + .CK(n_0_61), .D(registers[27]), .Q(registers_31__ap[27]), .QN(), .SE(dftIn), + .SI(registers_3__ap[27]) + ); + AOI221_X1_LVT i_1_0_1225( + .A(n_1_0_1166), .B1(n_1_0_1279), .B2(registers_27__ap[27]), .C1(registers_31__ap[27]), + .C2(n_1_0_1266), .ZN(n_1_0_1165) + ); + NAND3_X1_LVT i_1_0_1224( + .A1(n_1_0_1175), .A2(n_1_0_1170), .A3(n_1_0_1165), .ZN(RRs1[27]) + ); + AND2_X1_LVT i_0_0_26( + .A1(n_0_0_16), .A2(WRd[26]), .ZN(registers[26]) + ); + SDFF_X1_LVT \registers_reg[18][26] ( + .CK(n_0_48), .D(registers[26]), .Q(registers_18__ap[26]), .QN(), .SE(dftIn), + .SI(registers_17__ap[27]) + ); + SDFF_X1_LVT \registers_reg[22][26] ( + .CK(n_0_52), .D(registers[26]), .Q(registers_22__ap[26]), .QN(), .SE(dftIn), + .SI(registers_18__ap[26]) + ); + SDFF_X1_LVT \registers_reg[1][26] ( + .CK(n_0_0), .D(registers[26]), .Q(registers_1__ap[26]), .QN(), .SE(dftIn), + .SI(registers_22__ap[26]) + ); + AOI222_X1_LVT i_1_0_1223( + .A1(registers_18__ap[26]), .A2(n_1_0_1297), .B1(n_1_0_1294), .B2(registers_22__ap[26]), + .C1(registers_1__ap[26]), .C2(n_1_0_1274), .ZN(n_1_0_1164) + ); + SDFF_X1_LVT \registers_reg[29][26] ( + .CK(n_0_59), .D(registers[26]), .Q(registers_29__ap[26]), .QN(), .SE(dftIn), + .SI(registers_27__ap[27]) + ); + SDFF_X1_LVT \registers_reg[2][26] ( + .CK(n_0_32), .D(registers[26]), .Q(registers_2__ap[26]), .QN(), .SE(dftIn), + .SI(registers_29__ap[26]) + ); + AOI22_X1_LVT i_1_0_1222( + .A1(registers_29__ap[26]), .A2(n_1_0_1276), .B1(n_1_0_1268), .B2(registers_2__ap[26]), + .ZN(n_1_0_1163) + ); + SDFF_X1_LVT \registers_reg[9][26] ( + .CK(n_0_39), .D(registers[26]), .Q(registers_9__ap[26]), .QN(), .SE(dftIn), + .SI(registers_31__ap[27]) + ); + SDFF_X1_LVT \registers_reg[7][26] ( + .CK(n_0_37), .D(registers[26]), .Q(registers_7__ap[26]), .QN(), .SE(dftIn), + .SI(registers_9__ap[26]) + ); + AOI22_X1_LVT i_1_0_1221( + .A1(registers_9__ap[26]), .A2(n_1_0_1291), .B1(n_1_0_1263), .B2(registers_7__ap[26]), + .ZN(n_1_0_1162) + ); + SDFF_X1_LVT \registers_reg[11][26] ( + .CK(n_0_41), .D(registers[26]), .Q(registers_11__ap[26]), .QN(), .SE(dftIn), + .SI(registers_14__ap[27]) + ); + SDFF_X1_LVT \registers_reg[25][26] ( + .CK(n_0_55), .D(registers[26]), .Q(registers_25__ap[26]), .QN(), .SE(dftIn), + .SI(registers_2__ap[26]) + ); + AOI22_X1_LVT i_1_0_1220( + .A1(registers_11__ap[26]), .A2(n_1_0_1270), .B1(n_1_0_1269), .B2(registers_25__ap[26]), + .ZN(n_1_0_1161) + ); + SDFF_X1_LVT \registers_reg[27][26] ( + .CK(n_0_57), .D(registers[26]), .Q(registers_27__ap[26]), .QN(), .SE(dftIn), + .SI(registers_25__ap[26]) + ); + SDFF_X1_LVT \registers_reg[16][26] ( + .CK(n_0_46), .D(registers[26]), .Q(registers_16__ap[26]), .QN(), .SE(dftIn), + .SI(registers_11__ap[26]) + ); + AOI22_X1_LVT i_1_0_1219( + .A1(registers_27__ap[26]), .A2(n_1_0_1279), .B1(n_1_0_1267), .B2(registers_16__ap[26]), + .ZN(n_1_0_1160) + ); + NAND3_X1_LVT i_1_0_1218( + .A1(n_1_0_1162), .A2(n_1_0_1161), .A3(n_1_0_1160), .ZN(n_1_0_1159) + ); + SDFF_X1_LVT \registers_reg[31][26] ( + .CK(n_0_61), .D(registers[26]), .Q(registers_31__ap[26]), .QN(), .SE(dftIn), + .SI(registers_7__ap[26]) + ); + SDFF_X1_LVT \registers_reg[6][26] ( + .CK(n_0_36), .D(registers[26]), .Q(registers_6__ap[26]), .QN(), .SE(dftIn), + .SI(registers_31__ap[26]) + ); + AOI221_X1_LVT i_1_0_1217( + .A(n_1_0_1159), .B1(n_1_0_1266), .B2(registers_31__ap[26]), .C1(registers_6__ap[26]), + .C2(n_1_0_1300), .ZN(n_1_0_1158) + ); + NAND3_X1_LVT i_1_0_1216( + .A1(n_1_0_1164), .A2(n_1_0_1163), .A3(n_1_0_1158), .ZN(n_1_0_1157) + ); + SDFF_X1_LVT \registers_reg[5][26] ( + .CK(n_0_35), .D(registers[26]), .Q(registers_5__ap[26]), .QN(), .SE(dftIn), + .SI(registers_6__ap[26]) + ); + SDFF_X1_LVT \registers_reg[28][26] ( + .CK(n_0_58), .D(registers[26]), .Q(registers_28__ap[26]), .QN(), .SE(dftIn), + .SI(registers_27__ap[26]) + ); + AOI221_X1_LVT i_1_0_1215( + .A(n_1_0_1157), .B1(n_1_0_1273), .B2(registers_5__ap[26]), .C1(registers_28__ap[26]), + .C2(n_1_0_1283), .ZN(n_1_0_1156) + ); + SDFF_X1_LVT \registers_reg[4][26] ( + .CK(n_0_34), .D(registers[26]), .Q(registers_4__ap[26]), .QN(), .SE(dftIn), + .SI(registers_5__ap[26]) + ); + SDFF_X1_LVT \registers_reg[12][26] ( + .CK(n_0_42), .D(registers[26]), .Q(registers_12__ap[26]), .QN(), .SE(dftIn), + .SI(registers_16__ap[26]) + ); + AOI22_X1_LVT i_1_0_1214( + .A1(registers_4__ap[26]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[26]), + .ZN(n_1_0_1155) + ); + SDFF_X1_LVT \registers_reg[19][26] ( + .CK(n_0_49), .D(registers[26]), .Q(registers_19__ap[26]), .QN(), .SE(dftIn), + .SI(registers_1__ap[26]) + ); + SDFF_X1_LVT \registers_reg[21][26] ( + .CK(n_0_51), .D(registers[26]), .Q(registers_21__ap[26]), .QN(), .SE(dftIn), + .SI(registers_19__ap[26]) + ); + AOI22_X1_LVT i_1_0_1213( + .A1(registers_19__ap[26]), .A2(n_1_0_1295), .B1(n_1_0_1259), .B2(registers_21__ap[26]), + .ZN(n_1_0_1154) + ); + SDFF_X1_LVT \registers_reg[24][26] ( + .CK(n_0_54), .D(registers[26]), .Q(registers_24__ap[26]), .QN(), .SE(dftIn), + .SI(registers_28__ap[26]) + ); + SDFF_X1_LVT \registers_reg[20][26] ( + .CK(n_0_50), .D(registers[26]), .Q(registers_20__ap[26]), .QN(), .SE(dftIn), + .SI(registers_21__ap[26]) + ); + AOI22_X1_LVT i_1_0_1212( + .A1(registers_24__ap[26]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[26]), + .ZN(n_1_0_1153) + ); + NAND3_X1_LVT i_1_0_1211( + .A1(n_1_0_1155), .A2(n_1_0_1154), .A3(n_1_0_1153), .ZN(n_1_0_1152) + ); + SDFF_X1_LVT \registers_reg[26][26] ( + .CK(n_0_56), .D(registers[26]), .Q(registers_26__ap[26]), .QN(), .SE(dftIn), + .SI(registers_24__ap[26]) + ); + SDFF_X1_LVT \registers_reg[30][26] ( + .CK(n_0_60), .D(registers[26]), .Q(registers_30__ap[26]), .QN(), .SE(dftIn), + .SI(registers_26__ap[26]) + ); + AOI221_X1_LVT i_1_0_1210( + .A(n_1_0_1152), .B1(n_1_0_1285), .B2(registers_26__ap[26]), .C1(registers_30__ap[26]), + .C2(n_1_0_1272), .ZN(n_1_0_1151) + ); + SDFF_X1_LVT \registers_reg[8][26] ( + .CK(n_0_38), .D(registers[26]), .Q(registers_8__ap[26]), .QN(), .SE(dftIn), + .SI(registers_4__ap[26]) + ); + SDFF_X1_LVT \registers_reg[23][26] ( + .CK(n_0_53), .D(registers[26]), .Q(registers_23__ap[26]), .QN(), .SE(dftIn), + .SI(registers_20__ap[26]) + ); + AOI22_X1_LVT i_1_0_1209( + .A1(registers_8__ap[26]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[26]), + .ZN(n_1_0_1150) + ); + SDFF_X1_LVT \registers_reg[13][26] ( + .CK(n_0_43), .D(registers[26]), .Q(registers_13__ap[26]), .QN(), .SE(dftIn), + .SI(registers_12__ap[26]) + ); + SDFF_X1_LVT \registers_reg[17][26] ( + .CK(n_0_47), .D(registers[26]), .Q(registers_17__ap[26]), .QN(), .SE(dftIn), + .SI(registers_23__ap[26]) + ); + AOI22_X1_LVT i_1_0_1208( + .A1(registers_13__ap[26]), .A2(n_1_0_1277), .B1(n_1_0_1271), .B2(registers_17__ap[26]), + .ZN(n_1_0_1149) + ); + SDFF_X1_LVT \registers_reg[15][26] ( + .CK(n_0_45), .D(registers[26]), .Q(registers_15__ap[26]), .QN(), .SE(dftIn), + .SI(registers_13__ap[26]) + ); + SDFF_X1_LVT \registers_reg[14][26] ( + .CK(n_0_44), .D(registers[26]), .Q(registers_14__ap[26]), .QN(), .SE(dftIn), + .SI(registers_15__ap[26]) + ); + AOI22_X1_LVT i_1_0_1207( + .A1(registers_15__ap[26]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[26]), + .ZN(n_1_0_1148) + ); + NAND3_X1_LVT i_1_0_1206( + .A1(n_1_0_1150), .A2(n_1_0_1149), .A3(n_1_0_1148), .ZN(n_1_0_1147) + ); + SDFF_X1_LVT \registers_reg[10][26] ( + .CK(n_0_40), .D(registers[26]), .Q(registers_10__ap[26]), .QN(), .SE(dftIn), + .SI(registers_14__ap[26]) + ); + SDFF_X1_LVT \registers_reg[3][26] ( + .CK(n_0_33), .D(registers[26]), .Q(registers_3__ap[26]), .QN(), .SE(dftIn), + .SI(registers_8__ap[26]) + ); + AOI221_X1_LVT i_1_0_1205( + .A(n_1_0_1147), .B1(n_1_0_1287), .B2(registers_10__ap[26]), .C1(registers_3__ap[26]), + .C2(n_1_0_1257), .ZN(n_1_0_1146) + ); + NAND3_X1_LVT i_1_0_1204( + .A1(n_1_0_1156), .A2(n_1_0_1151), .A3(n_1_0_1146), .ZN(RRs1[26]) + ); + AND2_X1_LVT i_0_0_25( + .A1(n_0_0_16), .A2(WRd[25]), .ZN(registers[25]) + ); + SDFF_X1_LVT \registers_reg[17][25] ( + .CK(n_0_47), .D(registers[25]), .Q(registers_17__ap[25]), .QN(), .SE(dftIn), + .SI(registers_17__ap[26]) + ); + SDFF_X1_LVT \registers_reg[21][25] ( + .CK(n_0_51), .D(registers[25]), .Q(registers_21__ap[25]), .QN(), .SE(dftIn), + .SI(registers_17__ap[25]) + ); + AOI22_X1_LVT i_1_0_1202( + .A1(registers_17__ap[25]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[25]), + .ZN(n_1_0_1144) + ); + SDFF_X1_LVT \registers_reg[6][25] ( + .CK(n_0_36), .D(registers[25]), .Q(registers_6__ap[25]), .QN(), .SE(dftIn), + .SI(registers_3__ap[26]) + ); + SDFF_X1_LVT \registers_reg[8][25] ( + .CK(n_0_38), .D(registers[25]), .Q(registers_8__ap[25]), .QN(), .SE(dftIn), + .SI(registers_6__ap[25]) + ); + AOI22_X1_LVT i_1_0_1203( + .A1(registers_6__ap[25]), .A2(n_1_0_1300), .B1(n_1_0_1282), .B2(registers_8__ap[25]), + .ZN(n_1_0_1145) + ); + SDFF_X1_LVT \registers_reg[20][25] ( + .CK(n_0_50), .D(registers[25]), .Q(registers_20__ap[25]), .QN(), .SE(dftIn), + .SI(registers_21__ap[25]) + ); + SDFF_X1_LVT \registers_reg[12][25] ( + .CK(n_0_42), .D(registers[25]), .Q(registers_12__ap[25]), .QN(), .SE(dftIn), + .SI(registers_10__ap[26]) + ); + AOI22_X1_LVT i_1_0_1201( + .A1(registers_20__ap[25]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[25]), + .ZN(n_1_0_1143) + ); + SDFF_X1_LVT \registers_reg[5][25] ( + .CK(n_0_35), .D(registers[25]), .Q(registers_5__ap[25]), .QN(), .SE(dftIn), + .SI(registers_8__ap[25]) + ); + SDFF_X1_LVT \registers_reg[11][25] ( + .CK(n_0_41), .D(registers[25]), .Q(registers_11__ap[25]), .QN(), .SE(dftIn), + .SI(registers_12__ap[25]) + ); + AOI22_X1_LVT i_1_0_1200( + .A1(registers_5__ap[25]), .A2(n_1_0_1273), .B1(n_1_0_1270), .B2(registers_11__ap[25]), + .ZN(n_1_0_1142) + ); + NAND3_X1_LVT i_1_0_1199( + .A1(n_1_0_1145), .A2(n_1_0_1143), .A3(n_1_0_1142), .ZN(n_1_0_1141) + ); + SDFF_X1_LVT \registers_reg[10][25] ( + .CK(n_0_40), .D(registers[25]), .Q(registers_10__ap[25]), .QN(), .SE(dftIn), + .SI(registers_11__ap[25]) + ); + SDFF_X1_LVT \registers_reg[2][25] ( + .CK(n_0_32), .D(registers[25]), .Q(registers_2__ap[25]), .QN(), .SE(dftIn), + .SI(registers_30__ap[26]) + ); + AOI221_X1_LVT i_1_0_1198( + .A(n_1_0_1141), .B1(n_1_0_1287), .B2(registers_10__ap[25]), .C1(registers_2__ap[25]), + .C2(n_1_0_1268), .ZN(n_1_0_1140) + ); + SDFF_X1_LVT \registers_reg[13][25] ( + .CK(n_0_43), .D(registers[25]), .Q(registers_13__ap[25]), .QN(), .SE(dftIn), + .SI(registers_10__ap[25]) + ); + SDFF_X1_LVT \registers_reg[30][25] ( + .CK(n_0_60), .D(registers[25]), .Q(registers_30__ap[25]), .QN(), .SE(dftIn), + .SI(registers_2__ap[25]) + ); + SDFF_X1_LVT \registers_reg[22][25] ( + .CK(n_0_52), .D(registers[25]), .Q(registers_22__ap[25]), .QN(), .SE(dftIn), + .SI(registers_20__ap[25]) + ); + AOI222_X1_LVT i_1_0_1197( + .A1(registers_13__ap[25]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[25]), + .C1(registers_22__ap[25]), .C2(n_1_0_1294), .ZN(n_1_0_1139) + ); + NAND2_X1_LVT i_1_0_1196( + .A1(n_1_0_1140), .A2(n_1_0_1139), .ZN(n_1_0_1138) + ); + SDFF_X1_LVT \registers_reg[1][25] ( + .CK(n_0_0), .D(registers[25]), .Q(registers_1__ap[25]), .QN(), .SE(dftIn), + .SI(registers_22__ap[25]) + ); + SDFF_X1_LVT \registers_reg[28][25] ( + .CK(n_0_58), .D(registers[25]), .Q(registers_28__ap[25]), .QN(), .SE(dftIn), + .SI(registers_30__ap[25]) + ); + AOI221_X1_LVT i_1_0_1195( + .A(n_1_0_1138), .B1(n_1_0_1274), .B2(registers_1__ap[25]), .C1(registers_28__ap[25]), + .C2(n_1_0_1283), .ZN(n_1_0_1137) + ); + SDFF_X1_LVT \registers_reg[18][25] ( + .CK(n_0_48), .D(registers[25]), .Q(registers_18__ap[25]), .QN(), .SE(dftIn), + .SI(registers_1__ap[25]) + ); + SDFF_X1_LVT \registers_reg[26][25] ( + .CK(n_0_56), .D(registers[25]), .Q(registers_26__ap[25]), .QN(), .SE(dftIn), + .SI(registers_28__ap[25]) + ); + AOI22_X1_LVT i_1_0_1194( + .A1(registers_18__ap[25]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[25]), + .ZN(n_1_0_1136) + ); + SDFF_X1_LVT \registers_reg[24][25] ( + .CK(n_0_54), .D(registers[25]), .Q(registers_24__ap[25]), .QN(), .SE(dftIn), + .SI(registers_26__ap[25]) + ); + SDFF_X1_LVT \registers_reg[4][25] ( + .CK(n_0_34), .D(registers[25]), .Q(registers_4__ap[25]), .QN(), .SE(dftIn), + .SI(registers_5__ap[25]) + ); + AOI22_X1_LVT i_1_0_1193( + .A1(registers_24__ap[25]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[25]), + .ZN(n_1_0_1135) + ); + SDFF_X1_LVT \registers_reg[15][25] ( + .CK(n_0_45), .D(registers[25]), .Q(registers_15__ap[25]), .QN(), .SE(dftIn), + .SI(registers_13__ap[25]) + ); + SDFF_X1_LVT \registers_reg[16][25] ( + .CK(n_0_46), .D(registers[25]), .Q(registers_16__ap[25]), .QN(), .SE(dftIn), + .SI(registers_15__ap[25]) + ); + AOI22_X1_LVT i_1_0_1192( + .A1(registers_15__ap[25]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[25]), + .ZN(n_1_0_1134) + ); + NAND3_X1_LVT i_1_0_1191( + .A1(n_1_0_1136), .A2(n_1_0_1135), .A3(n_1_0_1134), .ZN(n_1_0_1133) + ); + SDFF_X1_LVT \registers_reg[19][25] ( + .CK(n_0_49), .D(registers[25]), .Q(registers_19__ap[25]), .QN(), .SE(dftIn), + .SI(registers_18__ap[25]) + ); + SDFF_X1_LVT \registers_reg[25][25] ( + .CK(n_0_55), .D(registers[25]), .Q(registers_25__ap[25]), .QN(), .SE(dftIn), + .SI(registers_24__ap[25]) + ); + AOI221_X1_LVT i_1_0_1190( + .A(n_1_0_1133), .B1(n_1_0_1295), .B2(registers_19__ap[25]), .C1(registers_25__ap[25]), + .C2(n_1_0_1269), .ZN(n_1_0_1132) + ); + SDFF_X1_LVT \registers_reg[7][25] ( + .CK(n_0_37), .D(registers[25]), .Q(registers_7__ap[25]), .QN(), .SE(dftIn), + .SI(registers_4__ap[25]) + ); + SDFF_X1_LVT \registers_reg[14][25] ( + .CK(n_0_44), .D(registers[25]), .Q(registers_14__ap[25]), .QN(), .SE(dftIn), + .SI(registers_16__ap[25]) + ); + AOI22_X1_LVT i_1_0_1189( + .A1(registers_7__ap[25]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[25]), + .ZN(n_1_0_1131) + ); + SDFF_X1_LVT \registers_reg[9][25] ( + .CK(n_0_39), .D(registers[25]), .Q(registers_9__ap[25]), .QN(), .SE(dftIn), + .SI(registers_7__ap[25]) + ); + SDFF_X1_LVT \registers_reg[29][25] ( + .CK(n_0_59), .D(registers[25]), .Q(registers_29__ap[25]), .QN(), .SE(dftIn), + .SI(registers_25__ap[25]) + ); + AOI22_X1_LVT i_1_0_1188( + .A1(registers_9__ap[25]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[25]), + .ZN(n_1_0_1130) + ); + SDFF_X1_LVT \registers_reg[23][25] ( + .CK(n_0_53), .D(registers[25]), .Q(registers_23__ap[25]), .QN(), .SE(dftIn), + .SI(registers_19__ap[25]) + ); + SDFF_X1_LVT \registers_reg[3][25] ( + .CK(n_0_33), .D(registers[25]), .Q(registers_3__ap[25]), .QN(), .SE(dftIn), + .SI(registers_9__ap[25]) + ); + AOI22_X1_LVT i_1_0_1187( + .A1(registers_23__ap[25]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[25]), + .ZN(n_1_0_1129) + ); + NAND3_X1_LVT i_1_0_1186( + .A1(n_1_0_1131), .A2(n_1_0_1130), .A3(n_1_0_1129), .ZN(n_1_0_1128) + ); + SDFF_X1_LVT \registers_reg[27][25] ( + .CK(n_0_57), .D(registers[25]), .Q(registers_27__ap[25]), .QN(), .SE(dftIn), + .SI(registers_29__ap[25]) + ); + SDFF_X1_LVT \registers_reg[31][25] ( + .CK(n_0_61), .D(registers[25]), .Q(registers_31__ap[25]), .QN(), .SE(dftIn), + .SI(registers_3__ap[25]) + ); + AOI221_X1_LVT i_1_0_1185( + .A(n_1_0_1128), .B1(n_1_0_1279), .B2(registers_27__ap[25]), .C1(registers_31__ap[25]), + .C2(n_1_0_1266), .ZN(n_1_0_1127) + ); + NAND4_X1_LVT i_1_0_1184( + .A1(n_1_0_1144), .A2(n_1_0_1137), .A3(n_1_0_1132), .A4(n_1_0_1127), .ZN(RRs1[25]) + ); + AND2_X1_LVT i_0_0_24( + .A1(n_0_0_16), .A2(WRd[24]), .ZN(registers[24]) + ); + SDFF_X1_LVT \registers_reg[17][24] ( + .CK(n_0_47), .D(registers[24]), .Q(registers_17__ap[24]), .QN(), .SE(dftIn), + .SI(registers_23__ap[25]) + ); + SDFF_X1_LVT \registers_reg[21][24] ( + .CK(n_0_51), .D(registers[24]), .Q(registers_21__ap[24]), .QN(), .SE(dftIn), + .SI(registers_17__ap[24]) + ); + AOI22_X1_LVT i_1_0_1182( + .A1(registers_17__ap[24]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[24]), + .ZN(n_1_0_1125) + ); + SDFF_X1_LVT \registers_reg[6][24] ( + .CK(n_0_36), .D(registers[24]), .Q(registers_6__ap[24]), .QN(), .SE(dftIn), + .SI(registers_31__ap[25]) + ); + SDFF_X1_LVT \registers_reg[8][24] ( + .CK(n_0_38), .D(registers[24]), .Q(registers_8__ap[24]), .QN(), .SE(dftIn), + .SI(registers_6__ap[24]) + ); + AOI22_X1_LVT i_1_0_1183( + .A1(registers_6__ap[24]), .A2(n_1_0_1300), .B1(n_1_0_1282), .B2(registers_8__ap[24]), + .ZN(n_1_0_1126) + ); + SDFF_X1_LVT \registers_reg[20][24] ( + .CK(n_0_50), .D(registers[24]), .Q(registers_20__ap[24]), .QN(), .SE(dftIn), + .SI(registers_21__ap[24]) + ); + SDFF_X1_LVT \registers_reg[12][24] ( + .CK(n_0_42), .D(registers[24]), .Q(registers_12__ap[24]), .QN(), .SE(dftIn), + .SI(registers_14__ap[25]) + ); + AOI22_X1_LVT i_1_0_1181( + .A1(registers_20__ap[24]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[24]), + .ZN(n_1_0_1124) + ); + SDFF_X1_LVT \registers_reg[5][24] ( + .CK(n_0_35), .D(registers[24]), .Q(registers_5__ap[24]), .QN(), .SE(dftIn), + .SI(registers_8__ap[24]) + ); + SDFF_X1_LVT \registers_reg[11][24] ( + .CK(n_0_41), .D(registers[24]), .Q(registers_11__ap[24]), .QN(), .SE(dftIn), + .SI(registers_12__ap[24]) + ); + AOI22_X1_LVT i_1_0_1180( + .A1(registers_5__ap[24]), .A2(n_1_0_1273), .B1(n_1_0_1270), .B2(registers_11__ap[24]), + .ZN(n_1_0_1123) + ); + NAND3_X1_LVT i_1_0_1179( + .A1(n_1_0_1126), .A2(n_1_0_1124), .A3(n_1_0_1123), .ZN(n_1_0_1122) + ); + SDFF_X1_LVT \registers_reg[10][24] ( + .CK(n_0_40), .D(registers[24]), .Q(registers_10__ap[24]), .QN(), .SE(dftIn), + .SI(registers_11__ap[24]) + ); + SDFF_X1_LVT \registers_reg[2][24] ( + .CK(n_0_32), .D(registers[24]), .Q(registers_2__ap[24]), .QN(), .SE(dftIn), + .SI(registers_27__ap[25]) + ); + AOI221_X1_LVT i_1_0_1178( + .A(n_1_0_1122), .B1(n_1_0_1287), .B2(registers_10__ap[24]), .C1(registers_2__ap[24]), + .C2(n_1_0_1268), .ZN(n_1_0_1121) + ); + SDFF_X1_LVT \registers_reg[13][24] ( + .CK(n_0_43), .D(registers[24]), .Q(registers_13__ap[24]), .QN(), .SE(dftIn), + .SI(registers_10__ap[24]) + ); + SDFF_X1_LVT \registers_reg[30][24] ( + .CK(n_0_60), .D(registers[24]), .Q(registers_30__ap[24]), .QN(), .SE(dftIn), + .SI(registers_2__ap[24]) + ); + SDFF_X1_LVT \registers_reg[22][24] ( + .CK(n_0_52), .D(registers[24]), .Q(registers_22__ap[24]), .QN(), .SE(dftIn), + .SI(registers_20__ap[24]) + ); + AOI222_X1_LVT i_1_0_1177( + .A1(registers_13__ap[24]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[24]), + .C1(registers_22__ap[24]), .C2(n_1_0_1294), .ZN(n_1_0_1120) + ); + NAND2_X1_LVT i_1_0_1176( + .A1(n_1_0_1121), .A2(n_1_0_1120), .ZN(n_1_0_1119) + ); + SDFF_X1_LVT \registers_reg[1][24] ( + .CK(n_0_0), .D(registers[24]), .Q(registers_1__ap[24]), .QN(), .SE(dftIn), + .SI(registers_22__ap[24]) + ); + SDFF_X1_LVT \registers_reg[28][24] ( + .CK(n_0_58), .D(registers[24]), .Q(registers_28__ap[24]), .QN(), .SE(dftIn), + .SI(registers_30__ap[24]) + ); + AOI221_X1_LVT i_1_0_1175( + .A(n_1_0_1119), .B1(n_1_0_1274), .B2(registers_1__ap[24]), .C1(registers_28__ap[24]), + .C2(n_1_0_1283), .ZN(n_1_0_1118) + ); + SDFF_X1_LVT \registers_reg[18][24] ( + .CK(n_0_48), .D(registers[24]), .Q(registers_18__ap[24]), .QN(), .SE(dftIn), + .SI(registers_1__ap[24]) + ); + SDFF_X1_LVT \registers_reg[26][24] ( + .CK(n_0_56), .D(registers[24]), .Q(registers_26__ap[24]), .QN(), .SE(dftIn), + .SI(registers_28__ap[24]) + ); + AOI22_X1_LVT i_1_0_1174( + .A1(registers_18__ap[24]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[24]), + .ZN(n_1_0_1117) + ); + SDFF_X1_LVT \registers_reg[24][24] ( + .CK(n_0_54), .D(registers[24]), .Q(registers_24__ap[24]), .QN(), .SE(dftIn), + .SI(registers_26__ap[24]) + ); + SDFF_X1_LVT \registers_reg[4][24] ( + .CK(n_0_34), .D(registers[24]), .Q(registers_4__ap[24]), .QN(), .SE(dftIn), + .SI(registers_5__ap[24]) + ); + AOI22_X1_LVT i_1_0_1173( + .A1(registers_24__ap[24]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[24]), + .ZN(n_1_0_1116) + ); + SDFF_X1_LVT \registers_reg[15][24] ( + .CK(n_0_45), .D(registers[24]), .Q(registers_15__ap[24]), .QN(), .SE(dftIn), + .SI(registers_13__ap[24]) + ); + SDFF_X1_LVT \registers_reg[25][24] ( + .CK(n_0_55), .D(registers[24]), .Q(registers_25__ap[24]), .QN(), .SE(dftIn), + .SI(registers_24__ap[24]) + ); + AOI22_X1_LVT i_1_0_1172( + .A1(registers_15__ap[24]), .A2(n_1_0_1286), .B1(n_1_0_1269), .B2(registers_25__ap[24]), + .ZN(n_1_0_1115) + ); + NAND3_X1_LVT i_1_0_1171( + .A1(n_1_0_1117), .A2(n_1_0_1116), .A3(n_1_0_1115), .ZN(n_1_0_1114) + ); + SDFF_X1_LVT \registers_reg[19][24] ( + .CK(n_0_49), .D(registers[24]), .Q(registers_19__ap[24]), .QN(), .SE(dftIn), + .SI(registers_18__ap[24]) + ); + SDFF_X1_LVT \registers_reg[16][24] ( + .CK(n_0_46), .D(registers[24]), .Q(registers_16__ap[24]), .QN(), .SE(dftIn), + .SI(registers_15__ap[24]) + ); + AOI221_X1_LVT i_1_0_1170( + .A(n_1_0_1114), .B1(n_1_0_1295), .B2(registers_19__ap[24]), .C1(registers_16__ap[24]), + .C2(n_1_0_1267), .ZN(n_1_0_1113) + ); + SDFF_X1_LVT \registers_reg[7][24] ( + .CK(n_0_37), .D(registers[24]), .Q(registers_7__ap[24]), .QN(), .SE(dftIn), + .SI(registers_4__ap[24]) + ); + SDFF_X1_LVT \registers_reg[14][24] ( + .CK(n_0_44), .D(registers[24]), .Q(registers_14__ap[24]), .QN(), .SE(dftIn), + .SI(registers_16__ap[24]) + ); + AOI22_X1_LVT i_1_0_1169( + .A1(registers_7__ap[24]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[24]), + .ZN(n_1_0_1112) + ); + SDFF_X1_LVT \registers_reg[9][24] ( + .CK(n_0_39), .D(registers[24]), .Q(registers_9__ap[24]), .QN(), .SE(dftIn), + .SI(registers_7__ap[24]) + ); + SDFF_X1_LVT \registers_reg[29][24] ( + .CK(n_0_59), .D(registers[24]), .Q(registers_29__ap[24]), .QN(), .SE(dftIn), + .SI(registers_25__ap[24]) + ); + AOI22_X1_LVT i_1_0_1168( + .A1(registers_9__ap[24]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[24]), + .ZN(n_1_0_1111) + ); + SDFF_X1_LVT \registers_reg[23][24] ( + .CK(n_0_53), .D(registers[24]), .Q(registers_23__ap[24]), .QN(), .SE(dftIn), + .SI(registers_19__ap[24]) + ); + SDFF_X1_LVT \registers_reg[3][24] ( + .CK(n_0_33), .D(registers[24]), .Q(registers_3__ap[24]), .QN(), .SE(dftIn), + .SI(registers_9__ap[24]) + ); + AOI22_X1_LVT i_1_0_1167( + .A1(registers_23__ap[24]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[24]), + .ZN(n_1_0_1110) + ); + NAND3_X1_LVT i_1_0_1166( + .A1(n_1_0_1112), .A2(n_1_0_1111), .A3(n_1_0_1110), .ZN(n_1_0_1109) + ); + SDFF_X1_LVT \registers_reg[27][24] ( + .CK(n_0_57), .D(registers[24]), .Q(registers_27__ap[24]), .QN(), .SE(dftIn), + .SI(registers_29__ap[24]) + ); + SDFF_X1_LVT \registers_reg[31][24] ( + .CK(n_0_61), .D(registers[24]), .Q(registers_31__ap[24]), .QN(), .SE(dftIn), + .SI(registers_3__ap[24]) + ); + AOI221_X1_LVT i_1_0_1165( + .A(n_1_0_1109), .B1(n_1_0_1279), .B2(registers_27__ap[24]), .C1(registers_31__ap[24]), + .C2(n_1_0_1266), .ZN(n_1_0_1108) + ); + NAND4_X1_LVT i_1_0_1164( + .A1(n_1_0_1125), .A2(n_1_0_1118), .A3(n_1_0_1113), .A4(n_1_0_1108), .ZN(RRs1[24]) + ); + AND2_X1_LVT i_0_0_23( + .A1(n_0_0_16), .A2(WRd[23]), .ZN(registers[23]) + ); + SDFF_X1_LVT \registers_reg[9][23] ( + .CK(n_0_39), .D(registers[23]), .Q(registers_9__ap[23]), .QN(), .SE(dftIn), + .SI(registers_31__ap[24]) + ); + SDFF_X1_LVT \registers_reg[28][23] ( + .CK(n_0_58), .D(registers[23]), .Q(registers_28__ap[23]), .QN(), .SE(dftIn), + .SI(registers_27__ap[24]) + ); + AOI22_X1_LVT i_1_0_1163( + .A1(registers_9__ap[23]), .A2(n_1_0_1291), .B1(n_1_0_1283), .B2(registers_28__ap[23]), + .ZN(n_1_0_1107) + ); + SDFF_X1_LVT \registers_reg[18][23] ( + .CK(n_0_48), .D(registers[23]), .Q(registers_18__ap[23]), .QN(), .SE(dftIn), + .SI(registers_23__ap[24]) + ); + SDFF_X1_LVT \registers_reg[22][23] ( + .CK(n_0_52), .D(registers[23]), .Q(registers_22__ap[23]), .QN(), .SE(dftIn), + .SI(registers_18__ap[23]) + ); + AOI22_X1_LVT i_1_0_1160( + .A1(registers_18__ap[23]), .A2(n_1_0_1297), .B1(n_1_0_1294), .B2(registers_22__ap[23]), + .ZN(n_1_0_1104) + ); + SDFF_X1_LVT \registers_reg[1][23] ( + .CK(n_0_0), .D(registers[23]), .Q(registers_1__ap[23]), .QN(), .SE(dftIn), + .SI(registers_22__ap[23]) + ); + SDFF_X1_LVT \registers_reg[21][23] ( + .CK(n_0_51), .D(registers[23]), .Q(registers_21__ap[23]), .QN(), .SE(dftIn), + .SI(registers_1__ap[23]) + ); + AOI22_X1_LVT i_1_0_1159( + .A1(registers_1__ap[23]), .A2(n_1_0_1274), .B1(n_1_0_1259), .B2(registers_21__ap[23]), + .ZN(n_1_0_1103) + ); + NAND3_X1_LVT i_1_0_1157( + .A1(n_1_0_1107), .A2(n_1_0_1104), .A3(n_1_0_1103), .ZN(n_1_0_1101) + ); + SDFF_X1_LVT \registers_reg[20][23] ( + .CK(n_0_50), .D(registers[23]), .Q(registers_20__ap[23]), .QN(), .SE(dftIn), + .SI(registers_21__ap[23]) + ); + SDFF_X1_LVT \registers_reg[19][23] ( + .CK(n_0_49), .D(registers[23]), .Q(registers_19__ap[23]), .QN(), .SE(dftIn), + .SI(registers_20__ap[23]) + ); + AOI221_X1_LVT i_1_0_1156( + .A(n_1_0_1101), .B1(n_1_0_1281), .B2(registers_20__ap[23]), .C1(registers_19__ap[23]), + .C2(n_1_0_1295), .ZN(n_1_0_1100) + ); + SDFF_X1_LVT \registers_reg[26][23] ( + .CK(n_0_56), .D(registers[23]), .Q(registers_26__ap[23]), .QN(), .SE(dftIn), + .SI(registers_28__ap[23]) + ); + SDFF_X1_LVT \registers_reg[23][23] ( + .CK(n_0_53), .D(registers[23]), .Q(registers_23__ap[23]), .QN(), .SE(dftIn), + .SI(registers_19__ap[23]) + ); + AOI22_X1_LVT i_1_0_1162( + .A1(registers_26__ap[23]), .A2(n_1_0_1285), .B1(n_1_0_1264), .B2(registers_23__ap[23]), + .ZN(n_1_0_1106) + ); + SDFF_X1_LVT \registers_reg[29][23] ( + .CK(n_0_59), .D(registers[23]), .Q(registers_29__ap[23]), .QN(), .SE(dftIn), + .SI(registers_26__ap[23]) + ); + SDFF_X1_LVT \registers_reg[3][23] ( + .CK(n_0_33), .D(registers[23]), .Q(registers_3__ap[23]), .QN(), .SE(dftIn), + .SI(registers_9__ap[23]) + ); + AOI22_X1_LVT i_1_0_1161( + .A1(registers_29__ap[23]), .A2(n_1_0_1276), .B1(n_1_0_1257), .B2(registers_3__ap[23]), + .ZN(n_1_0_1105) + ); + SDFF_X1_LVT \registers_reg[30][23] ( + .CK(n_0_60), .D(registers[23]), .Q(registers_30__ap[23]), .QN(), .SE(dftIn), + .SI(registers_29__ap[23]) + ); + SDFF_X1_LVT \registers_reg[31][23] ( + .CK(n_0_61), .D(registers[23]), .Q(registers_31__ap[23]), .QN(), .SE(dftIn), + .SI(registers_3__ap[23]) + ); + AOI22_X1_LVT i_1_0_1158( + .A1(registers_30__ap[23]), .A2(n_1_0_1272), .B1(n_1_0_1266), .B2(registers_31__ap[23]), + .ZN(n_1_0_1102) + ); + NAND3_X1_LVT i_1_0_1155( + .A1(n_1_0_1106), .A2(n_1_0_1105), .A3(n_1_0_1102), .ZN(n_1_0_1099) + ); + SDFF_X1_LVT \registers_reg[8][23] ( + .CK(n_0_38), .D(registers[23]), .Q(registers_8__ap[23]), .QN(), .SE(dftIn), + .SI(registers_31__ap[23]) + ); + SDFF_X1_LVT \registers_reg[17][23] ( + .CK(n_0_47), .D(registers[23]), .Q(registers_17__ap[23]), .QN(), .SE(dftIn), + .SI(registers_23__ap[23]) + ); + AOI221_X1_LVT i_1_0_1154( + .A(n_1_0_1099), .B1(n_1_0_1282), .B2(registers_8__ap[23]), .C1(registers_17__ap[23]), + .C2(n_1_0_1271), .ZN(n_1_0_1098) + ); + SDFF_X1_LVT \registers_reg[24][23] ( + .CK(n_0_54), .D(registers[23]), .Q(registers_24__ap[23]), .QN(), .SE(dftIn), + .SI(registers_30__ap[23]) + ); + SDFF_X1_LVT \registers_reg[15][23] ( + .CK(n_0_45), .D(registers[23]), .Q(registers_15__ap[23]), .QN(), .SE(dftIn), + .SI(registers_14__ap[24]) + ); + SDFF_X1_LVT \registers_reg[14][23] ( + .CK(n_0_44), .D(registers[23]), .Q(registers_14__ap[23]), .QN(), .SE(dftIn), + .SI(registers_15__ap[23]) + ); + AOI222_X1_LVT i_1_0_1153( + .A1(registers_24__ap[23]), .A2(n_1_0_1289), .B1(n_1_0_1286), .B2(registers_15__ap[23]), + .C1(n_1_0_1258), .C2(registers_14__ap[23]), .ZN(n_1_0_1097) + ); + SDFF_X1_LVT \registers_reg[16][23] ( + .CK(n_0_46), .D(registers[23]), .Q(registers_16__ap[23]), .QN(), .SE(dftIn), + .SI(registers_14__ap[23]) + ); + SDFF_X1_LVT \registers_reg[7][23] ( + .CK(n_0_37), .D(registers[23]), .Q(registers_7__ap[23]), .QN(), .SE(dftIn), + .SI(registers_8__ap[23]) + ); + AOI22_X1_LVT i_1_0_1152( + .A1(registers_16__ap[23]), .A2(n_1_0_1267), .B1(n_1_0_1263), .B2(registers_7__ap[23]), + .ZN(n_1_0_1096) + ); + SDFF_X1_LVT \registers_reg[6][23] ( + .CK(n_0_36), .D(registers[23]), .Q(registers_6__ap[23]), .QN(), .SE(dftIn), + .SI(registers_7__ap[23]) + ); + SDFF_X1_LVT \registers_reg[25][23] ( + .CK(n_0_55), .D(registers[23]), .Q(registers_25__ap[23]), .QN(), .SE(dftIn), + .SI(registers_24__ap[23]) + ); + AOI22_X1_LVT i_1_0_1151( + .A1(registers_6__ap[23]), .A2(n_1_0_1300), .B1(n_1_0_1269), .B2(registers_25__ap[23]), + .ZN(n_1_0_1095) + ); + SDFF_X1_LVT \registers_reg[27][23] ( + .CK(n_0_57), .D(registers[23]), .Q(registers_27__ap[23]), .QN(), .SE(dftIn), + .SI(registers_25__ap[23]) + ); + SDFF_X1_LVT \registers_reg[11][23] ( + .CK(n_0_41), .D(registers[23]), .Q(registers_11__ap[23]), .QN(), .SE(dftIn), + .SI(registers_16__ap[23]) + ); + AOI22_X1_LVT i_1_0_1150( + .A1(registers_27__ap[23]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[23]), + .ZN(n_1_0_1094) + ); + SDFF_X1_LVT \registers_reg[13][23] ( + .CK(n_0_43), .D(registers[23]), .Q(registers_13__ap[23]), .QN(), .SE(dftIn), + .SI(registers_11__ap[23]) + ); + SDFF_X1_LVT \registers_reg[5][23] ( + .CK(n_0_35), .D(registers[23]), .Q(registers_5__ap[23]), .QN(), .SE(dftIn), + .SI(registers_6__ap[23]) + ); + AOI22_X1_LVT i_1_0_1149( + .A1(registers_13__ap[23]), .A2(n_1_0_1277), .B1(n_1_0_1273), .B2(registers_5__ap[23]), + .ZN(n_1_0_1093) + ); + SDFF_X1_LVT \registers_reg[4][23] ( + .CK(n_0_34), .D(registers[23]), .Q(registers_4__ap[23]), .QN(), .SE(dftIn), + .SI(registers_5__ap[23]) + ); + SDFF_X1_LVT \registers_reg[12][23] ( + .CK(n_0_42), .D(registers[23]), .Q(registers_12__ap[23]), .QN(), .SE(dftIn), + .SI(registers_13__ap[23]) + ); + AOI22_X1_LVT i_1_0_1148( + .A1(registers_4__ap[23]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[23]), + .ZN(n_1_0_1092) + ); + NAND3_X1_LVT i_1_0_1147( + .A1(n_1_0_1094), .A2(n_1_0_1093), .A3(n_1_0_1092), .ZN(n_1_0_1091) + ); + SDFF_X1_LVT \registers_reg[2][23] ( + .CK(n_0_32), .D(registers[23]), .Q(registers_2__ap[23]), .QN(), .SE(dftIn), + .SI(registers_27__ap[23]) + ); + SDFF_X1_LVT \registers_reg[10][23] ( + .CK(n_0_40), .D(registers[23]), .Q(registers_10__ap[23]), .QN(), .SE(dftIn), + .SI(registers_12__ap[23]) + ); + AOI221_X1_LVT i_1_0_1146( + .A(n_1_0_1091), .B1(n_1_0_1268), .B2(registers_2__ap[23]), .C1(registers_10__ap[23]), + .C2(n_1_0_1287), .ZN(n_1_0_1090) + ); + AND4_X1_LVT i_1_0_1145( + .A1(n_1_0_1097), .A2(n_1_0_1096), .A3(n_1_0_1095), .A4(n_1_0_1090), .ZN(n_1_0_1089) + ); + NAND3_X1_LVT i_1_0_1144( + .A1(n_1_0_1100), .A2(n_1_0_1098), .A3(n_1_0_1089), .ZN(RRs1[23]) + ); + AND2_X1_LVT i_0_0_22( + .A1(n_0_0_16), .A2(WRd[22]), .ZN(registers[22]) + ); + SDFF_X1_LVT \registers_reg[17][22] ( + .CK(n_0_47), .D(registers[22]), .Q(registers_17__ap[22]), .QN(), .SE(dftIn), + .SI(registers_17__ap[23]) + ); + SDFF_X1_LVT \registers_reg[21][22] ( + .CK(n_0_51), .D(registers[22]), .Q(registers_21__ap[22]), .QN(), .SE(dftIn), + .SI(registers_17__ap[22]) + ); + AOI22_X1_LVT i_1_0_1142( + .A1(registers_17__ap[22]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[22]), + .ZN(n_1_0_1087) + ); + SDFF_X1_LVT \registers_reg[6][22] ( + .CK(n_0_36), .D(registers[22]), .Q(registers_6__ap[22]), .QN(), .SE(dftIn), + .SI(registers_4__ap[23]) + ); + SDFF_X1_LVT \registers_reg[11][22] ( + .CK(n_0_41), .D(registers[22]), .Q(registers_11__ap[22]), .QN(), .SE(dftIn), + .SI(registers_10__ap[23]) + ); + AOI22_X1_LVT i_1_0_1143( + .A1(registers_6__ap[22]), .A2(n_1_0_1300), .B1(n_1_0_1270), .B2(registers_11__ap[22]), + .ZN(n_1_0_1088) + ); + SDFF_X1_LVT \registers_reg[20][22] ( + .CK(n_0_50), .D(registers[22]), .Q(registers_20__ap[22]), .QN(), .SE(dftIn), + .SI(registers_21__ap[22]) + ); + SDFF_X1_LVT \registers_reg[12][22] ( + .CK(n_0_42), .D(registers[22]), .Q(registers_12__ap[22]), .QN(), .SE(dftIn), + .SI(registers_11__ap[22]) + ); + AOI22_X1_LVT i_1_0_1141( + .A1(registers_20__ap[22]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[22]), + .ZN(n_1_0_1086) + ); + SDFF_X1_LVT \registers_reg[10][22] ( + .CK(n_0_40), .D(registers[22]), .Q(registers_10__ap[22]), .QN(), .SE(dftIn), + .SI(registers_12__ap[22]) + ); + SDFF_X1_LVT \registers_reg[5][22] ( + .CK(n_0_35), .D(registers[22]), .Q(registers_5__ap[22]), .QN(), .SE(dftIn), + .SI(registers_6__ap[22]) + ); + AOI22_X1_LVT i_1_0_1140( + .A1(registers_10__ap[22]), .A2(n_1_0_1287), .B1(n_1_0_1273), .B2(registers_5__ap[22]), + .ZN(n_1_0_1085) + ); + NAND3_X1_LVT i_1_0_1139( + .A1(n_1_0_1088), .A2(n_1_0_1086), .A3(n_1_0_1085), .ZN(n_1_0_1084) + ); + SDFF_X1_LVT \registers_reg[31][22] ( + .CK(n_0_61), .D(registers[22]), .Q(registers_31__ap[22]), .QN(), .SE(dftIn), + .SI(registers_5__ap[22]) + ); + SDFF_X1_LVT \registers_reg[2][22] ( + .CK(n_0_32), .D(registers[22]), .Q(registers_2__ap[22]), .QN(), .SE(dftIn), + .SI(registers_2__ap[23]) + ); + AOI221_X1_LVT i_1_0_1138( + .A(n_1_0_1084), .B1(n_1_0_1266), .B2(registers_31__ap[22]), .C1(registers_2__ap[22]), + .C2(n_1_0_1268), .ZN(n_1_0_1083) + ); + SDFF_X1_LVT \registers_reg[22][22] ( + .CK(n_0_52), .D(registers[22]), .Q(registers_22__ap[22]), .QN(), .SE(dftIn), + .SI(registers_20__ap[22]) + ); + SDFF_X1_LVT \registers_reg[26][22] ( + .CK(n_0_56), .D(registers[22]), .Q(registers_26__ap[22]), .QN(), .SE(dftIn), + .SI(registers_2__ap[22]) + ); + SDFF_X1_LVT \registers_reg[13][22] ( + .CK(n_0_43), .D(registers[22]), .Q(registers_13__ap[22]), .QN(), .SE(dftIn), + .SI(registers_10__ap[22]) + ); + AOI222_X1_LVT i_1_0_1137( + .A1(registers_22__ap[22]), .A2(n_1_0_1294), .B1(n_1_0_1285), .B2(registers_26__ap[22]), + .C1(n_1_0_1277), .C2(registers_13__ap[22]), .ZN(n_1_0_1082) + ); + NAND2_X1_LVT i_1_0_1136( + .A1(n_1_0_1083), .A2(n_1_0_1082), .ZN(n_1_0_1081) + ); + SDFF_X1_LVT \registers_reg[1][22] ( + .CK(n_0_0), .D(registers[22]), .Q(registers_1__ap[22]), .QN(), .SE(dftIn), + .SI(registers_22__ap[22]) + ); + SDFF_X1_LVT \registers_reg[28][22] ( + .CK(n_0_58), .D(registers[22]), .Q(registers_28__ap[22]), .QN(), .SE(dftIn), + .SI(registers_26__ap[22]) + ); + AOI221_X1_LVT i_1_0_1135( + .A(n_1_0_1081), .B1(n_1_0_1274), .B2(registers_1__ap[22]), .C1(registers_28__ap[22]), + .C2(n_1_0_1283), .ZN(n_1_0_1080) + ); + SDFF_X1_LVT \registers_reg[18][22] ( + .CK(n_0_48), .D(registers[22]), .Q(registers_18__ap[22]), .QN(), .SE(dftIn), + .SI(registers_1__ap[22]) + ); + SDFF_X1_LVT \registers_reg[30][22] ( + .CK(n_0_60), .D(registers[22]), .Q(registers_30__ap[22]), .QN(), .SE(dftIn), + .SI(registers_28__ap[22]) + ); + AOI22_X1_LVT i_1_0_1134( + .A1(registers_18__ap[22]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[22]), + .ZN(n_1_0_1079) + ); + SDFF_X1_LVT \registers_reg[24][22] ( + .CK(n_0_54), .D(registers[22]), .Q(registers_24__ap[22]), .QN(), .SE(dftIn), + .SI(registers_30__ap[22]) + ); + SDFF_X1_LVT \registers_reg[4][22] ( + .CK(n_0_34), .D(registers[22]), .Q(registers_4__ap[22]), .QN(), .SE(dftIn), + .SI(registers_31__ap[22]) + ); + AOI22_X1_LVT i_1_0_1133( + .A1(registers_24__ap[22]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[22]), + .ZN(n_1_0_1078) + ); + SDFF_X1_LVT \registers_reg[15][22] ( + .CK(n_0_45), .D(registers[22]), .Q(registers_15__ap[22]), .QN(), .SE(dftIn), + .SI(registers_13__ap[22]) + ); + SDFF_X1_LVT \registers_reg[16][22] ( + .CK(n_0_46), .D(registers[22]), .Q(registers_16__ap[22]), .QN(), .SE(dftIn), + .SI(registers_15__ap[22]) + ); + AOI22_X1_LVT i_1_0_1132( + .A1(registers_15__ap[22]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[22]), + .ZN(n_1_0_1077) + ); + NAND3_X1_LVT i_1_0_1131( + .A1(n_1_0_1079), .A2(n_1_0_1078), .A3(n_1_0_1077), .ZN(n_1_0_1076) + ); + SDFF_X1_LVT \registers_reg[19][22] ( + .CK(n_0_49), .D(registers[22]), .Q(registers_19__ap[22]), .QN(), .SE(dftIn), + .SI(registers_18__ap[22]) + ); + SDFF_X1_LVT \registers_reg[25][22] ( + .CK(n_0_55), .D(registers[22]), .Q(registers_25__ap[22]), .QN(), .SE(dftIn), + .SI(registers_24__ap[22]) + ); + AOI221_X1_LVT i_1_0_1130( + .A(n_1_0_1076), .B1(n_1_0_1295), .B2(registers_19__ap[22]), .C1(registers_25__ap[22]), + .C2(n_1_0_1269), .ZN(n_1_0_1075) + ); + SDFF_X1_LVT \registers_reg[7][22] ( + .CK(n_0_37), .D(registers[22]), .Q(registers_7__ap[22]), .QN(), .SE(dftIn), + .SI(registers_4__ap[22]) + ); + SDFF_X1_LVT \registers_reg[14][22] ( + .CK(n_0_44), .D(registers[22]), .Q(registers_14__ap[22]), .QN(), .SE(dftIn), + .SI(registers_16__ap[22]) + ); + AOI22_X1_LVT i_1_0_1129( + .A1(registers_7__ap[22]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[22]), + .ZN(n_1_0_1074) + ); + SDFF_X1_LVT \registers_reg[9][22] ( + .CK(n_0_39), .D(registers[22]), .Q(registers_9__ap[22]), .QN(), .SE(dftIn), + .SI(registers_7__ap[22]) + ); + SDFF_X1_LVT \registers_reg[29][22] ( + .CK(n_0_59), .D(registers[22]), .Q(registers_29__ap[22]), .QN(), .SE(dftIn), + .SI(registers_25__ap[22]) + ); + AOI22_X1_LVT i_1_0_1128( + .A1(registers_9__ap[22]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[22]), + .ZN(n_1_0_1073) + ); + SDFF_X1_LVT \registers_reg[8][22] ( + .CK(n_0_38), .D(registers[22]), .Q(registers_8__ap[22]), .QN(), .SE(dftIn), + .SI(registers_9__ap[22]) + ); + SDFF_X1_LVT \registers_reg[23][22] ( + .CK(n_0_53), .D(registers[22]), .Q(registers_23__ap[22]), .QN(), .SE(dftIn), + .SI(registers_19__ap[22]) + ); + AOI22_X1_LVT i_1_0_1127( + .A1(registers_8__ap[22]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[22]), + .ZN(n_1_0_1072) + ); + NAND3_X1_LVT i_1_0_1126( + .A1(n_1_0_1074), .A2(n_1_0_1073), .A3(n_1_0_1072), .ZN(n_1_0_1071) + ); + SDFF_X1_LVT \registers_reg[27][22] ( + .CK(n_0_57), .D(registers[22]), .Q(registers_27__ap[22]), .QN(), .SE(dftIn), + .SI(registers_29__ap[22]) + ); + SDFF_X1_LVT \registers_reg[3][22] ( + .CK(n_0_33), .D(registers[22]), .Q(registers_3__ap[22]), .QN(), .SE(dftIn), + .SI(registers_8__ap[22]) + ); + AOI221_X1_LVT i_1_0_1125( + .A(n_1_0_1071), .B1(n_1_0_1279), .B2(registers_27__ap[22]), .C1(registers_3__ap[22]), + .C2(n_1_0_1257), .ZN(n_1_0_1070) + ); + NAND4_X1_LVT i_1_0_1124( + .A1(n_1_0_1087), .A2(n_1_0_1080), .A3(n_1_0_1075), .A4(n_1_0_1070), .ZN(RRs1[22]) + ); + AND2_X1_LVT i_0_0_21( + .A1(n_0_0_16), .A2(WRd[21]), .ZN(registers[21]) + ); + SDFF_X1_LVT \registers_reg[17][21] ( + .CK(n_0_47), .D(registers[21]), .Q(registers_17__ap[21]), .QN(), .SE(dftIn), + .SI(registers_23__ap[22]) + ); + SDFF_X1_LVT \registers_reg[21][21] ( + .CK(n_0_51), .D(registers[21]), .Q(registers_21__ap[21]), .QN(), .SE(dftIn), + .SI(registers_17__ap[21]) + ); + AOI22_X1_LVT i_1_0_1122( + .A1(registers_17__ap[21]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[21]), + .ZN(n_1_0_1068) + ); + SDFF_X1_LVT \registers_reg[6][21] ( + .CK(n_0_36), .D(registers[21]), .Q(registers_6__ap[21]), .QN(), .SE(dftIn), + .SI(registers_3__ap[22]) + ); + SDFF_X1_LVT \registers_reg[8][21] ( + .CK(n_0_38), .D(registers[21]), .Q(registers_8__ap[21]), .QN(), .SE(dftIn), + .SI(registers_6__ap[21]) + ); + AOI22_X1_LVT i_1_0_1123( + .A1(registers_6__ap[21]), .A2(n_1_0_1300), .B1(n_1_0_1282), .B2(registers_8__ap[21]), + .ZN(n_1_0_1069) + ); + SDFF_X1_LVT \registers_reg[20][21] ( + .CK(n_0_50), .D(registers[21]), .Q(registers_20__ap[21]), .QN(), .SE(dftIn), + .SI(registers_21__ap[21]) + ); + SDFF_X1_LVT \registers_reg[12][21] ( + .CK(n_0_42), .D(registers[21]), .Q(registers_12__ap[21]), .QN(), .SE(dftIn), + .SI(registers_14__ap[22]) + ); + AOI22_X1_LVT i_1_0_1121( + .A1(registers_20__ap[21]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[21]), + .ZN(n_1_0_1067) + ); + SDFF_X1_LVT \registers_reg[5][21] ( + .CK(n_0_35), .D(registers[21]), .Q(registers_5__ap[21]), .QN(), .SE(dftIn), + .SI(registers_8__ap[21]) + ); + SDFF_X1_LVT \registers_reg[11][21] ( + .CK(n_0_41), .D(registers[21]), .Q(registers_11__ap[21]), .QN(), .SE(dftIn), + .SI(registers_12__ap[21]) + ); + AOI22_X1_LVT i_1_0_1120( + .A1(registers_5__ap[21]), .A2(n_1_0_1273), .B1(n_1_0_1270), .B2(registers_11__ap[21]), + .ZN(n_1_0_1066) + ); + NAND3_X1_LVT i_1_0_1119( + .A1(n_1_0_1069), .A2(n_1_0_1067), .A3(n_1_0_1066), .ZN(n_1_0_1065) + ); + SDFF_X1_LVT \registers_reg[10][21] ( + .CK(n_0_40), .D(registers[21]), .Q(registers_10__ap[21]), .QN(), .SE(dftIn), + .SI(registers_11__ap[21]) + ); + SDFF_X1_LVT \registers_reg[2][21] ( + .CK(n_0_32), .D(registers[21]), .Q(registers_2__ap[21]), .QN(), .SE(dftIn), + .SI(registers_27__ap[22]) + ); + AOI221_X1_LVT i_1_0_1118( + .A(n_1_0_1065), .B1(n_1_0_1287), .B2(registers_10__ap[21]), .C1(registers_2__ap[21]), + .C2(n_1_0_1268), .ZN(n_1_0_1064) + ); + SDFF_X1_LVT \registers_reg[13][21] ( + .CK(n_0_43), .D(registers[21]), .Q(registers_13__ap[21]), .QN(), .SE(dftIn), + .SI(registers_10__ap[21]) + ); + SDFF_X1_LVT \registers_reg[30][21] ( + .CK(n_0_60), .D(registers[21]), .Q(registers_30__ap[21]), .QN(), .SE(dftIn), + .SI(registers_2__ap[21]) + ); + SDFF_X1_LVT \registers_reg[22][21] ( + .CK(n_0_52), .D(registers[21]), .Q(registers_22__ap[21]), .QN(), .SE(dftIn), + .SI(registers_20__ap[21]) + ); + AOI222_X1_LVT i_1_0_1117( + .A1(registers_13__ap[21]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[21]), + .C1(registers_22__ap[21]), .C2(n_1_0_1294), .ZN(n_1_0_1063) + ); + NAND2_X1_LVT i_1_0_1116( + .A1(n_1_0_1064), .A2(n_1_0_1063), .ZN(n_1_0_1062) + ); + SDFF_X1_LVT \registers_reg[1][21] ( + .CK(n_0_0), .D(registers[21]), .Q(registers_1__ap[21]), .QN(), .SE(dftIn), + .SI(registers_22__ap[21]) + ); + SDFF_X1_LVT \registers_reg[28][21] ( + .CK(n_0_58), .D(registers[21]), .Q(registers_28__ap[21]), .QN(), .SE(dftIn), + .SI(registers_30__ap[21]) + ); + AOI221_X1_LVT i_1_0_1115( + .A(n_1_0_1062), .B1(n_1_0_1274), .B2(registers_1__ap[21]), .C1(registers_28__ap[21]), + .C2(n_1_0_1283), .ZN(n_1_0_1061) + ); + SDFF_X1_LVT \registers_reg[18][21] ( + .CK(n_0_48), .D(registers[21]), .Q(registers_18__ap[21]), .QN(), .SE(dftIn), + .SI(registers_1__ap[21]) + ); + SDFF_X1_LVT \registers_reg[26][21] ( + .CK(n_0_56), .D(registers[21]), .Q(registers_26__ap[21]), .QN(), .SE(dftIn), + .SI(registers_28__ap[21]) + ); + AOI22_X1_LVT i_1_0_1114( + .A1(registers_18__ap[21]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[21]), + .ZN(n_1_0_1060) + ); + SDFF_X1_LVT \registers_reg[24][21] ( + .CK(n_0_54), .D(registers[21]), .Q(registers_24__ap[21]), .QN(), .SE(dftIn), + .SI(registers_26__ap[21]) + ); + SDFF_X1_LVT \registers_reg[4][21] ( + .CK(n_0_34), .D(registers[21]), .Q(registers_4__ap[21]), .QN(), .SE(dftIn), + .SI(registers_5__ap[21]) + ); + AOI22_X1_LVT i_1_0_1113( + .A1(registers_24__ap[21]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[21]), + .ZN(n_1_0_1059) + ); + SDFF_X1_LVT \registers_reg[15][21] ( + .CK(n_0_45), .D(registers[21]), .Q(registers_15__ap[21]), .QN(), .SE(dftIn), + .SI(registers_13__ap[21]) + ); + SDFF_X1_LVT \registers_reg[16][21] ( + .CK(n_0_46), .D(registers[21]), .Q(registers_16__ap[21]), .QN(), .SE(dftIn), + .SI(registers_15__ap[21]) + ); + AOI22_X1_LVT i_1_0_1112( + .A1(registers_15__ap[21]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[21]), + .ZN(n_1_0_1058) + ); + NAND3_X1_LVT i_1_0_1111( + .A1(n_1_0_1060), .A2(n_1_0_1059), .A3(n_1_0_1058), .ZN(n_1_0_1057) + ); + SDFF_X1_LVT \registers_reg[19][21] ( + .CK(n_0_49), .D(registers[21]), .Q(registers_19__ap[21]), .QN(), .SE(dftIn), + .SI(registers_18__ap[21]) + ); + SDFF_X1_LVT \registers_reg[25][21] ( + .CK(n_0_55), .D(registers[21]), .Q(registers_25__ap[21]), .QN(), .SE(dftIn), + .SI(registers_24__ap[21]) + ); + AOI221_X1_LVT i_1_0_1110( + .A(n_1_0_1057), .B1(n_1_0_1295), .B2(registers_19__ap[21]), .C1(registers_25__ap[21]), + .C2(n_1_0_1269), .ZN(n_1_0_1056) + ); + SDFF_X1_LVT \registers_reg[7][21] ( + .CK(n_0_37), .D(registers[21]), .Q(registers_7__ap[21]), .QN(), .SE(dftIn), + .SI(registers_4__ap[21]) + ); + SDFF_X1_LVT \registers_reg[14][21] ( + .CK(n_0_44), .D(registers[21]), .Q(registers_14__ap[21]), .QN(), .SE(dftIn), + .SI(registers_16__ap[21]) + ); + AOI22_X1_LVT i_1_0_1109( + .A1(registers_7__ap[21]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[21]), + .ZN(n_1_0_1055) + ); + SDFF_X1_LVT \registers_reg[9][21] ( + .CK(n_0_39), .D(registers[21]), .Q(registers_9__ap[21]), .QN(), .SE(dftIn), + .SI(registers_7__ap[21]) + ); + SDFF_X1_LVT \registers_reg[29][21] ( + .CK(n_0_59), .D(registers[21]), .Q(registers_29__ap[21]), .QN(), .SE(dftIn), + .SI(registers_25__ap[21]) + ); + AOI22_X1_LVT i_1_0_1108( + .A1(registers_9__ap[21]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[21]), + .ZN(n_1_0_1054) + ); + SDFF_X1_LVT \registers_reg[23][21] ( + .CK(n_0_53), .D(registers[21]), .Q(registers_23__ap[21]), .QN(), .SE(dftIn), + .SI(registers_19__ap[21]) + ); + SDFF_X1_LVT \registers_reg[3][21] ( + .CK(n_0_33), .D(registers[21]), .Q(registers_3__ap[21]), .QN(), .SE(dftIn), + .SI(registers_9__ap[21]) + ); + AOI22_X1_LVT i_1_0_1107( + .A1(registers_23__ap[21]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[21]), + .ZN(n_1_0_1053) + ); + NAND3_X1_LVT i_1_0_1106( + .A1(n_1_0_1055), .A2(n_1_0_1054), .A3(n_1_0_1053), .ZN(n_1_0_1052) + ); + SDFF_X1_LVT \registers_reg[27][21] ( + .CK(n_0_57), .D(registers[21]), .Q(registers_27__ap[21]), .QN(), .SE(dftIn), + .SI(registers_29__ap[21]) + ); + SDFF_X1_LVT \registers_reg[31][21] ( + .CK(n_0_61), .D(registers[21]), .Q(registers_31__ap[21]), .QN(), .SE(dftIn), + .SI(registers_3__ap[21]) + ); + AOI221_X1_LVT i_1_0_1105( + .A(n_1_0_1052), .B1(n_1_0_1279), .B2(registers_27__ap[21]), .C1(registers_31__ap[21]), + .C2(n_1_0_1266), .ZN(n_1_0_1051) + ); + NAND4_X1_LVT i_1_0_1104( + .A1(n_1_0_1068), .A2(n_1_0_1061), .A3(n_1_0_1056), .A4(n_1_0_1051), .ZN(RRs1[21]) + ); + AND2_X1_LVT i_0_0_20( + .A1(n_0_0_16), .A2(WRd[20]), .ZN(registers[20]) + ); + SDFF_X1_LVT \registers_reg[17][20] ( + .CK(n_0_47), .D(registers[20]), .Q(registers_17__ap[20]), .QN(), .SE(dftIn), + .SI(registers_23__ap[21]) + ); + SDFF_X1_LVT \registers_reg[21][20] ( + .CK(n_0_51), .D(registers[20]), .Q(registers_21__ap[20]), .QN(), .SE(dftIn), + .SI(registers_17__ap[20]) + ); + AOI22_X1_LVT i_1_0_1100( + .A1(registers_17__ap[20]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[20]), + .ZN(n_1_0_1047) + ); + SDFF_X1_LVT \registers_reg[10][20] ( + .CK(n_0_40), .D(registers[20]), .Q(registers_10__ap[20]), .QN(), .SE(dftIn), + .SI(registers_14__ap[21]) + ); + SDFF_X1_LVT \registers_reg[2][20] ( + .CK(n_0_32), .D(registers[20]), .Q(registers_2__ap[20]), .QN(), .SE(dftIn), + .SI(registers_27__ap[21]) + ); + AOI22_X1_LVT i_1_0_1103( + .A1(registers_10__ap[20]), .A2(n_1_0_1287), .B1(n_1_0_1268), .B2(registers_2__ap[20]), + .ZN(n_1_0_1050) + ); + SDFF_X1_LVT \registers_reg[20][20] ( + .CK(n_0_50), .D(registers[20]), .Q(registers_20__ap[20]), .QN(), .SE(dftIn), + .SI(registers_21__ap[20]) + ); + SDFF_X1_LVT \registers_reg[12][20] ( + .CK(n_0_42), .D(registers[20]), .Q(registers_12__ap[20]), .QN(), .SE(dftIn), + .SI(registers_10__ap[20]) + ); + AOI22_X1_LVT i_1_0_1099( + .A1(registers_20__ap[20]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[20]), + .ZN(n_1_0_1046) + ); + SDFF_X1_LVT \registers_reg[15][20] ( + .CK(n_0_45), .D(registers[20]), .Q(registers_15__ap[20]), .QN(), .SE(dftIn), + .SI(registers_12__ap[20]) + ); + SDFF_X1_LVT \registers_reg[8][20] ( + .CK(n_0_38), .D(registers[20]), .Q(registers_8__ap[20]), .QN(), .SE(dftIn), + .SI(registers_31__ap[21]) + ); + AOI22_X1_LVT i_1_0_1102( + .A1(registers_15__ap[20]), .A2(n_1_0_1286), .B1(n_1_0_1282), .B2(registers_8__ap[20]), + .ZN(n_1_0_1049) + ); + INV_X1_LVT i_1_0_1101( + .A(n_1_0_1049), .ZN(n_1_0_1048) + ); + SDFF_X1_LVT \registers_reg[11][20] ( + .CK(n_0_41), .D(registers[20]), .Q(registers_11__ap[20]), .QN(), .SE(dftIn), + .SI(registers_15__ap[20]) + ); + SDFF_X1_LVT \registers_reg[5][20] ( + .CK(n_0_35), .D(registers[20]), .Q(registers_5__ap[20]), .QN(), .SE(dftIn), + .SI(registers_8__ap[20]) + ); + AOI221_X1_LVT i_1_0_1098( + .A(n_1_0_1048), .B1(n_1_0_1270), .B2(registers_11__ap[20]), .C1(registers_5__ap[20]), + .C2(n_1_0_1273), .ZN(n_1_0_1045) + ); + SDFF_X1_LVT \registers_reg[13][20] ( + .CK(n_0_43), .D(registers[20]), .Q(registers_13__ap[20]), .QN(), .SE(dftIn), + .SI(registers_11__ap[20]) + ); + SDFF_X1_LVT \registers_reg[30][20] ( + .CK(n_0_60), .D(registers[20]), .Q(registers_30__ap[20]), .QN(), .SE(dftIn), + .SI(registers_2__ap[20]) + ); + SDFF_X1_LVT \registers_reg[22][20] ( + .CK(n_0_52), .D(registers[20]), .Q(registers_22__ap[20]), .QN(), .SE(dftIn), + .SI(registers_20__ap[20]) + ); + AOI222_X1_LVT i_1_0_1097( + .A1(registers_13__ap[20]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[20]), + .C1(registers_22__ap[20]), .C2(n_1_0_1294), .ZN(n_1_0_1044) + ); + NAND4_X1_LVT i_1_0_1096( + .A1(n_1_0_1050), .A2(n_1_0_1046), .A3(n_1_0_1045), .A4(n_1_0_1044), .ZN(n_1_0_1043) + ); + SDFF_X1_LVT \registers_reg[1][20] ( + .CK(n_0_0), .D(registers[20]), .Q(registers_1__ap[20]), .QN(), .SE(dftIn), + .SI(registers_22__ap[20]) + ); + SDFF_X1_LVT \registers_reg[28][20] ( + .CK(n_0_58), .D(registers[20]), .Q(registers_28__ap[20]), .QN(), .SE(dftIn), + .SI(registers_30__ap[20]) + ); + AOI221_X1_LVT i_1_0_1095( + .A(n_1_0_1043), .B1(n_1_0_1274), .B2(registers_1__ap[20]), .C1(registers_28__ap[20]), + .C2(n_1_0_1283), .ZN(n_1_0_1042) + ); + SDFF_X1_LVT \registers_reg[18][20] ( + .CK(n_0_48), .D(registers[20]), .Q(registers_18__ap[20]), .QN(), .SE(dftIn), + .SI(registers_1__ap[20]) + ); + SDFF_X1_LVT \registers_reg[26][20] ( + .CK(n_0_56), .D(registers[20]), .Q(registers_26__ap[20]), .QN(), .SE(dftIn), + .SI(registers_28__ap[20]) + ); + AOI22_X1_LVT i_1_0_1094( + .A1(registers_18__ap[20]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[20]), + .ZN(n_1_0_1041) + ); + SDFF_X1_LVT \registers_reg[24][20] ( + .CK(n_0_54), .D(registers[20]), .Q(registers_24__ap[20]), .QN(), .SE(dftIn), + .SI(registers_26__ap[20]) + ); + SDFF_X1_LVT \registers_reg[4][20] ( + .CK(n_0_34), .D(registers[20]), .Q(registers_4__ap[20]), .QN(), .SE(dftIn), + .SI(registers_5__ap[20]) + ); + AOI22_X1_LVT i_1_0_1093( + .A1(registers_24__ap[20]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[20]), + .ZN(n_1_0_1040) + ); + SDFF_X1_LVT \registers_reg[6][20] ( + .CK(n_0_36), .D(registers[20]), .Q(registers_6__ap[20]), .QN(), .SE(dftIn), + .SI(registers_4__ap[20]) + ); + SDFF_X1_LVT \registers_reg[25][20] ( + .CK(n_0_55), .D(registers[20]), .Q(registers_25__ap[20]), .QN(), .SE(dftIn), + .SI(registers_24__ap[20]) + ); + AOI22_X1_LVT i_1_0_1092( + .A1(registers_6__ap[20]), .A2(n_1_0_1300), .B1(n_1_0_1269), .B2(registers_25__ap[20]), + .ZN(n_1_0_1039) + ); + NAND3_X1_LVT i_1_0_1091( + .A1(n_1_0_1041), .A2(n_1_0_1040), .A3(n_1_0_1039), .ZN(n_1_0_1038) + ); + SDFF_X1_LVT \registers_reg[19][20] ( + .CK(n_0_49), .D(registers[20]), .Q(registers_19__ap[20]), .QN(), .SE(dftIn), + .SI(registers_18__ap[20]) + ); + SDFF_X1_LVT \registers_reg[16][20] ( + .CK(n_0_46), .D(registers[20]), .Q(registers_16__ap[20]), .QN(), .SE(dftIn), + .SI(registers_13__ap[20]) + ); + AOI221_X1_LVT i_1_0_1090( + .A(n_1_0_1038), .B1(n_1_0_1295), .B2(registers_19__ap[20]), .C1(registers_16__ap[20]), + .C2(n_1_0_1267), .ZN(n_1_0_1037) + ); + SDFF_X1_LVT \registers_reg[7][20] ( + .CK(n_0_37), .D(registers[20]), .Q(registers_7__ap[20]), .QN(), .SE(dftIn), + .SI(registers_6__ap[20]) + ); + SDFF_X1_LVT \registers_reg[14][20] ( + .CK(n_0_44), .D(registers[20]), .Q(registers_14__ap[20]), .QN(), .SE(dftIn), + .SI(registers_16__ap[20]) + ); + AOI22_X1_LVT i_1_0_1089( + .A1(registers_7__ap[20]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[20]), + .ZN(n_1_0_1036) + ); + SDFF_X1_LVT \registers_reg[9][20] ( + .CK(n_0_39), .D(registers[20]), .Q(registers_9__ap[20]), .QN(), .SE(dftIn), + .SI(registers_7__ap[20]) + ); + SDFF_X1_LVT \registers_reg[29][20] ( + .CK(n_0_59), .D(registers[20]), .Q(registers_29__ap[20]), .QN(), .SE(dftIn), + .SI(registers_25__ap[20]) + ); + AOI22_X1_LVT i_1_0_1088( + .A1(registers_9__ap[20]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[20]), + .ZN(n_1_0_1035) + ); + SDFF_X1_LVT \registers_reg[23][20] ( + .CK(n_0_53), .D(registers[20]), .Q(registers_23__ap[20]), .QN(), .SE(dftIn), + .SI(registers_19__ap[20]) + ); + SDFF_X1_LVT \registers_reg[3][20] ( + .CK(n_0_33), .D(registers[20]), .Q(registers_3__ap[20]), .QN(), .SE(dftIn), + .SI(registers_9__ap[20]) + ); + AOI22_X1_LVT i_1_0_1087( + .A1(registers_23__ap[20]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[20]), + .ZN(n_1_0_1034) + ); + NAND3_X1_LVT i_1_0_1086( + .A1(n_1_0_1036), .A2(n_1_0_1035), .A3(n_1_0_1034), .ZN(n_1_0_1033) + ); + SDFF_X1_LVT \registers_reg[27][20] ( + .CK(n_0_57), .D(registers[20]), .Q(registers_27__ap[20]), .QN(), .SE(dftIn), + .SI(registers_29__ap[20]) + ); + SDFF_X1_LVT \registers_reg[31][20] ( + .CK(n_0_61), .D(registers[20]), .Q(registers_31__ap[20]), .QN(), .SE(dftIn), + .SI(registers_3__ap[20]) + ); + AOI221_X1_LVT i_1_0_1085( + .A(n_1_0_1033), .B1(n_1_0_1279), .B2(registers_27__ap[20]), .C1(registers_31__ap[20]), + .C2(n_1_0_1266), .ZN(n_1_0_1032) + ); + NAND4_X1_LVT i_1_0_1084( + .A1(n_1_0_1047), .A2(n_1_0_1042), .A3(n_1_0_1037), .A4(n_1_0_1032), .ZN(RRs1[20]) + ); + AND2_X1_LVT i_0_0_19( + .A1(n_0_0_16), .A2(WRd[19]), .ZN(registers[19]) + ); + SDFF_X1_LVT \registers_reg[17][19] ( + .CK(n_0_47), .D(registers[19]), .Q(registers_17__ap[19]), .QN(), .SE(dftIn), + .SI(registers_23__ap[20]) + ); + SDFF_X1_LVT \registers_reg[21][19] ( + .CK(n_0_51), .D(registers[19]), .Q(registers_21__ap[19]), .QN(), .SE(dftIn), + .SI(registers_17__ap[19]) + ); + AOI22_X1_LVT i_1_0_1080( + .A1(registers_17__ap[19]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[19]), + .ZN(n_1_0_1028) + ); + SDFF_X1_LVT \registers_reg[2][19] ( + .CK(n_0_32), .D(registers[19]), .Q(registers_2__ap[19]), .QN(), .SE(dftIn), + .SI(registers_27__ap[20]) + ); + SDFF_X1_LVT \registers_reg[31][19] ( + .CK(n_0_61), .D(registers[19]), .Q(registers_31__ap[19]), .QN(), .SE(dftIn), + .SI(registers_31__ap[20]) + ); + AOI22_X1_LVT i_1_0_1083( + .A1(registers_2__ap[19]), .A2(n_1_0_1268), .B1(n_1_0_1266), .B2(registers_31__ap[19]), + .ZN(n_1_0_1031) + ); + SDFF_X1_LVT \registers_reg[20][19] ( + .CK(n_0_50), .D(registers[19]), .Q(registers_20__ap[19]), .QN(), .SE(dftIn), + .SI(registers_21__ap[19]) + ); + SDFF_X1_LVT \registers_reg[12][19] ( + .CK(n_0_42), .D(registers[19]), .Q(registers_12__ap[19]), .QN(), .SE(dftIn), + .SI(registers_14__ap[20]) + ); + AOI22_X1_LVT i_1_0_1079( + .A1(registers_20__ap[19]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[19]), + .ZN(n_1_0_1027) + ); + SDFF_X1_LVT \registers_reg[15][19] ( + .CK(n_0_45), .D(registers[19]), .Q(registers_15__ap[19]), .QN(), .SE(dftIn), + .SI(registers_12__ap[19]) + ); + SDFF_X1_LVT \registers_reg[11][19] ( + .CK(n_0_41), .D(registers[19]), .Q(registers_11__ap[19]), .QN(), .SE(dftIn), + .SI(registers_15__ap[19]) + ); + AOI22_X1_LVT i_1_0_1082( + .A1(registers_15__ap[19]), .A2(n_1_0_1286), .B1(n_1_0_1270), .B2(registers_11__ap[19]), + .ZN(n_1_0_1030) + ); + INV_X1_LVT i_1_0_1081( + .A(n_1_0_1030), .ZN(n_1_0_1029) + ); + SDFF_X1_LVT \registers_reg[27][19] ( + .CK(n_0_57), .D(registers[19]), .Q(registers_27__ap[19]), .QN(), .SE(dftIn), + .SI(registers_2__ap[19]) + ); + SDFF_X1_LVT \registers_reg[24][19] ( + .CK(n_0_54), .D(registers[19]), .Q(registers_24__ap[19]), .QN(), .SE(dftIn), + .SI(registers_27__ap[19]) + ); + AOI221_X1_LVT i_1_0_1078( + .A(n_1_0_1029), .B1(n_1_0_1279), .B2(registers_27__ap[19]), .C1(registers_24__ap[19]), + .C2(n_1_0_1289), .ZN(n_1_0_1026) + ); + SDFF_X1_LVT \registers_reg[22][19] ( + .CK(n_0_52), .D(registers[19]), .Q(registers_22__ap[19]), .QN(), .SE(dftIn), + .SI(registers_20__ap[19]) + ); + SDFF_X1_LVT \registers_reg[26][19] ( + .CK(n_0_56), .D(registers[19]), .Q(registers_26__ap[19]), .QN(), .SE(dftIn), + .SI(registers_24__ap[19]) + ); + SDFF_X1_LVT \registers_reg[13][19] ( + .CK(n_0_43), .D(registers[19]), .Q(registers_13__ap[19]), .QN(), .SE(dftIn), + .SI(registers_11__ap[19]) + ); + AOI222_X1_LVT i_1_0_1077( + .A1(registers_22__ap[19]), .A2(n_1_0_1294), .B1(n_1_0_1285), .B2(registers_26__ap[19]), + .C1(n_1_0_1277), .C2(registers_13__ap[19]), .ZN(n_1_0_1025) + ); + NAND4_X1_LVT i_1_0_1076( + .A1(n_1_0_1031), .A2(n_1_0_1027), .A3(n_1_0_1026), .A4(n_1_0_1025), .ZN(n_1_0_1024) + ); + SDFF_X1_LVT \registers_reg[1][19] ( + .CK(n_0_0), .D(registers[19]), .Q(registers_1__ap[19]), .QN(), .SE(dftIn), + .SI(registers_22__ap[19]) + ); + SDFF_X1_LVT \registers_reg[28][19] ( + .CK(n_0_58), .D(registers[19]), .Q(registers_28__ap[19]), .QN(), .SE(dftIn), + .SI(registers_26__ap[19]) + ); + AOI221_X1_LVT i_1_0_1075( + .A(n_1_0_1024), .B1(n_1_0_1274), .B2(registers_1__ap[19]), .C1(registers_28__ap[19]), + .C2(n_1_0_1283), .ZN(n_1_0_1023) + ); + SDFF_X1_LVT \registers_reg[18][19] ( + .CK(n_0_48), .D(registers[19]), .Q(registers_18__ap[19]), .QN(), .SE(dftIn), + .SI(registers_1__ap[19]) + ); + SDFF_X1_LVT \registers_reg[30][19] ( + .CK(n_0_60), .D(registers[19]), .Q(registers_30__ap[19]), .QN(), .SE(dftIn), + .SI(registers_28__ap[19]) + ); + AOI22_X1_LVT i_1_0_1074( + .A1(registers_18__ap[19]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[19]), + .ZN(n_1_0_1022) + ); + SDFF_X1_LVT \registers_reg[4][19] ( + .CK(n_0_34), .D(registers[19]), .Q(registers_4__ap[19]), .QN(), .SE(dftIn), + .SI(registers_31__ap[19]) + ); + SDFF_X1_LVT \registers_reg[5][19] ( + .CK(n_0_35), .D(registers[19]), .Q(registers_5__ap[19]), .QN(), .SE(dftIn), + .SI(registers_4__ap[19]) + ); + AOI22_X1_LVT i_1_0_1073( + .A1(registers_4__ap[19]), .A2(n_1_0_1278), .B1(n_1_0_1273), .B2(registers_5__ap[19]), + .ZN(n_1_0_1021) + ); + SDFF_X1_LVT \registers_reg[6][19] ( + .CK(n_0_36), .D(registers[19]), .Q(registers_6__ap[19]), .QN(), .SE(dftIn), + .SI(registers_5__ap[19]) + ); + SDFF_X1_LVT \registers_reg[25][19] ( + .CK(n_0_55), .D(registers[19]), .Q(registers_25__ap[19]), .QN(), .SE(dftIn), + .SI(registers_30__ap[19]) + ); + AOI22_X1_LVT i_1_0_1072( + .A1(registers_6__ap[19]), .A2(n_1_0_1300), .B1(n_1_0_1269), .B2(registers_25__ap[19]), + .ZN(n_1_0_1020) + ); + NAND3_X1_LVT i_1_0_1071( + .A1(n_1_0_1022), .A2(n_1_0_1021), .A3(n_1_0_1020), .ZN(n_1_0_1019) + ); + SDFF_X1_LVT \registers_reg[19][19] ( + .CK(n_0_49), .D(registers[19]), .Q(registers_19__ap[19]), .QN(), .SE(dftIn), + .SI(registers_18__ap[19]) + ); + SDFF_X1_LVT \registers_reg[16][19] ( + .CK(n_0_46), .D(registers[19]), .Q(registers_16__ap[19]), .QN(), .SE(dftIn), + .SI(registers_13__ap[19]) + ); + AOI221_X1_LVT i_1_0_1070( + .A(n_1_0_1019), .B1(n_1_0_1295), .B2(registers_19__ap[19]), .C1(registers_16__ap[19]), + .C2(n_1_0_1267), .ZN(n_1_0_1018) + ); + SDFF_X1_LVT \registers_reg[9][19] ( + .CK(n_0_39), .D(registers[19]), .Q(registers_9__ap[19]), .QN(), .SE(dftIn), + .SI(registers_6__ap[19]) + ); + SDFF_X1_LVT \registers_reg[29][19] ( + .CK(n_0_59), .D(registers[19]), .Q(registers_29__ap[19]), .QN(), .SE(dftIn), + .SI(registers_25__ap[19]) + ); + AOI22_X1_LVT i_1_0_1069( + .A1(registers_9__ap[19]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[19]), + .ZN(n_1_0_1017) + ); + SDFF_X1_LVT \registers_reg[8][19] ( + .CK(n_0_38), .D(registers[19]), .Q(registers_8__ap[19]), .QN(), .SE(dftIn), + .SI(registers_9__ap[19]) + ); + SDFF_X1_LVT \registers_reg[23][19] ( + .CK(n_0_53), .D(registers[19]), .Q(registers_23__ap[19]), .QN(), .SE(dftIn), + .SI(registers_19__ap[19]) + ); + AOI22_X1_LVT i_1_0_1068( + .A1(registers_8__ap[19]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[19]), + .ZN(n_1_0_1016) + ); + SDFF_X1_LVT \registers_reg[7][19] ( + .CK(n_0_37), .D(registers[19]), .Q(registers_7__ap[19]), .QN(), .SE(dftIn), + .SI(registers_8__ap[19]) + ); + SDFF_X1_LVT \registers_reg[14][19] ( + .CK(n_0_44), .D(registers[19]), .Q(registers_14__ap[19]), .QN(), .SE(dftIn), + .SI(registers_16__ap[19]) + ); + AOI22_X1_LVT i_1_0_1067( + .A1(registers_7__ap[19]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[19]), + .ZN(n_1_0_1015) + ); + NAND3_X1_LVT i_1_0_1066( + .A1(n_1_0_1017), .A2(n_1_0_1016), .A3(n_1_0_1015), .ZN(n_1_0_1014) + ); + SDFF_X1_LVT \registers_reg[10][19] ( + .CK(n_0_40), .D(registers[19]), .Q(registers_10__ap[19]), .QN(), .SE(dftIn), + .SI(registers_14__ap[19]) + ); + SDFF_X1_LVT \registers_reg[3][19] ( + .CK(n_0_33), .D(registers[19]), .Q(registers_3__ap[19]), .QN(), .SE(dftIn), + .SI(registers_7__ap[19]) + ); + AOI221_X1_LVT i_1_0_1065( + .A(n_1_0_1014), .B1(n_1_0_1287), .B2(registers_10__ap[19]), .C1(registers_3__ap[19]), + .C2(n_1_0_1257), .ZN(n_1_0_1013) + ); + NAND4_X1_LVT i_1_0_1064( + .A1(n_1_0_1028), .A2(n_1_0_1023), .A3(n_1_0_1018), .A4(n_1_0_1013), .ZN(RRs1[19]) + ); + AND2_X1_LVT i_0_0_18( + .A1(n_0_0_16), .A2(WRd[18]), .ZN(registers[18]) + ); + SDFF_X1_LVT \registers_reg[24][18] ( + .CK(n_0_54), .D(registers[18]), .Q(registers_24__ap[18]), .QN(), .SE(dftIn), + .SI(registers_29__ap[19]) + ); + SDFF_X1_LVT \registers_reg[28][18] ( + .CK(n_0_58), .D(registers[18]), .Q(registers_28__ap[18]), .QN(), .SE(dftIn), + .SI(registers_24__ap[18]) + ); + AOI22_X1_LVT i_1_0_1062( + .A1(registers_24__ap[18]), .A2(n_1_0_1289), .B1(n_1_0_1283), .B2(registers_28__ap[18]), + .ZN(n_1_0_1011) + ); + SDFF_X1_LVT \registers_reg[11][18] ( + .CK(n_0_41), .D(registers[18]), .Q(registers_11__ap[18]), .QN(), .SE(dftIn), + .SI(registers_10__ap[19]) + ); + SDFF_X1_LVT \registers_reg[16][18] ( + .CK(n_0_46), .D(registers[18]), .Q(registers_16__ap[18]), .QN(), .SE(dftIn), + .SI(registers_11__ap[18]) + ); + AOI22_X1_LVT i_1_0_1063( + .A1(registers_11__ap[18]), .A2(n_1_0_1270), .B1(n_1_0_1267), .B2(registers_16__ap[18]), + .ZN(n_1_0_1012) + ); + SDFF_X1_LVT \registers_reg[9][18] ( + .CK(n_0_39), .D(registers[18]), .Q(registers_9__ap[18]), .QN(), .SE(dftIn), + .SI(registers_3__ap[19]) + ); + SDFF_X1_LVT \registers_reg[7][18] ( + .CK(n_0_37), .D(registers[18]), .Q(registers_7__ap[18]), .QN(), .SE(dftIn), + .SI(registers_9__ap[18]) + ); + AOI22_X1_LVT i_1_0_1061( + .A1(registers_9__ap[18]), .A2(n_1_0_1291), .B1(n_1_0_1263), .B2(registers_7__ap[18]), + .ZN(n_1_0_1010) + ); + SDFF_X1_LVT \registers_reg[27][18] ( + .CK(n_0_57), .D(registers[18]), .Q(registers_27__ap[18]), .QN(), .SE(dftIn), + .SI(registers_28__ap[18]) + ); + SDFF_X1_LVT \registers_reg[25][18] ( + .CK(n_0_55), .D(registers[18]), .Q(registers_25__ap[18]), .QN(), .SE(dftIn), + .SI(registers_27__ap[18]) + ); + AOI22_X1_LVT i_1_0_1060( + .A1(registers_27__ap[18]), .A2(n_1_0_1279), .B1(n_1_0_1269), .B2(registers_25__ap[18]), + .ZN(n_1_0_1009) + ); + NAND3_X1_LVT i_1_0_1059( + .A1(n_1_0_1012), .A2(n_1_0_1010), .A3(n_1_0_1009), .ZN(n_1_0_1008) + ); + SDFF_X1_LVT \registers_reg[31][18] ( + .CK(n_0_61), .D(registers[18]), .Q(registers_31__ap[18]), .QN(), .SE(dftIn), + .SI(registers_7__ap[18]) + ); + SDFF_X1_LVT \registers_reg[6][18] ( + .CK(n_0_36), .D(registers[18]), .Q(registers_6__ap[18]), .QN(), .SE(dftIn), + .SI(registers_31__ap[18]) + ); + AOI221_X1_LVT i_1_0_1058( + .A(n_1_0_1008), .B1(n_1_0_1266), .B2(registers_31__ap[18]), .C1(registers_6__ap[18]), + .C2(n_1_0_1300), .ZN(n_1_0_1007) + ); + SDFF_X1_LVT \registers_reg[22][18] ( + .CK(n_0_52), .D(registers[18]), .Q(registers_22__ap[18]), .QN(), .SE(dftIn), + .SI(registers_23__ap[19]) + ); + SDFF_X1_LVT \registers_reg[26][18] ( + .CK(n_0_56), .D(registers[18]), .Q(registers_26__ap[18]), .QN(), .SE(dftIn), + .SI(registers_25__ap[18]) + ); + SDFF_X1_LVT \registers_reg[1][18] ( + .CK(n_0_0), .D(registers[18]), .Q(registers_1__ap[18]), .QN(), .SE(dftIn), + .SI(registers_22__ap[18]) + ); + AOI222_X1_LVT i_1_0_1057( + .A1(registers_22__ap[18]), .A2(n_1_0_1294), .B1(n_1_0_1285), .B2(registers_26__ap[18]), + .C1(n_1_0_1274), .C2(registers_1__ap[18]), .ZN(n_1_0_1006) + ); + NAND2_X1_LVT i_1_0_1056( + .A1(n_1_0_1007), .A2(n_1_0_1006), .ZN(n_1_0_1005) + ); + SDFF_X1_LVT \registers_reg[29][18] ( + .CK(n_0_59), .D(registers[18]), .Q(registers_29__ap[18]), .QN(), .SE(dftIn), + .SI(registers_26__ap[18]) + ); + SDFF_X1_LVT \registers_reg[2][18] ( + .CK(n_0_32), .D(registers[18]), .Q(registers_2__ap[18]), .QN(), .SE(dftIn), + .SI(registers_29__ap[18]) + ); + AOI221_X1_LVT i_1_0_1055( + .A(n_1_0_1005), .B1(n_1_0_1276), .B2(registers_29__ap[18]), .C1(registers_2__ap[18]), + .C2(n_1_0_1268), .ZN(n_1_0_1004) + ); + SDFF_X1_LVT \registers_reg[18][18] ( + .CK(n_0_48), .D(registers[18]), .Q(registers_18__ap[18]), .QN(), .SE(dftIn), + .SI(registers_1__ap[18]) + ); + SDFF_X1_LVT \registers_reg[30][18] ( + .CK(n_0_60), .D(registers[18]), .Q(registers_30__ap[18]), .QN(), .SE(dftIn), + .SI(registers_2__ap[18]) + ); + AOI22_X1_LVT i_1_0_1054( + .A1(registers_18__ap[18]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[18]), + .ZN(n_1_0_1003) + ); + SDFF_X1_LVT \registers_reg[4][18] ( + .CK(n_0_34), .D(registers[18]), .Q(registers_4__ap[18]), .QN(), .SE(dftIn), + .SI(registers_6__ap[18]) + ); + SDFF_X1_LVT \registers_reg[12][18] ( + .CK(n_0_42), .D(registers[18]), .Q(registers_12__ap[18]), .QN(), .SE(dftIn), + .SI(registers_16__ap[18]) + ); + AOI22_X1_LVT i_1_0_1053( + .A1(registers_4__ap[18]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[18]), + .ZN(n_1_0_1002) + ); + SDFF_X1_LVT \registers_reg[19][18] ( + .CK(n_0_49), .D(registers[18]), .Q(registers_19__ap[18]), .QN(), .SE(dftIn), + .SI(registers_18__ap[18]) + ); + SDFF_X1_LVT \registers_reg[21][18] ( + .CK(n_0_51), .D(registers[18]), .Q(registers_21__ap[18]), .QN(), .SE(dftIn), + .SI(registers_19__ap[18]) + ); + AOI22_X1_LVT i_1_0_1052( + .A1(registers_19__ap[18]), .A2(n_1_0_1295), .B1(n_1_0_1259), .B2(registers_21__ap[18]), + .ZN(n_1_0_1001) + ); + NAND3_X1_LVT i_1_0_1051( + .A1(n_1_0_1003), .A2(n_1_0_1002), .A3(n_1_0_1001), .ZN(n_1_0_1000) + ); + SDFF_X1_LVT \registers_reg[5][18] ( + .CK(n_0_35), .D(registers[18]), .Q(registers_5__ap[18]), .QN(), .SE(dftIn), + .SI(registers_4__ap[18]) + ); + SDFF_X1_LVT \registers_reg[20][18] ( + .CK(n_0_50), .D(registers[18]), .Q(registers_20__ap[18]), .QN(), .SE(dftIn), + .SI(registers_21__ap[18]) + ); + AOI221_X1_LVT i_1_0_1050( + .A(n_1_0_1000), .B1(n_1_0_1273), .B2(registers_5__ap[18]), .C1(registers_20__ap[18]), + .C2(n_1_0_1281), .ZN(n_1_0_999) + ); + SDFF_X1_LVT \registers_reg[8][18] ( + .CK(n_0_38), .D(registers[18]), .Q(registers_8__ap[18]), .QN(), .SE(dftIn), + .SI(registers_5__ap[18]) + ); + SDFF_X1_LVT \registers_reg[23][18] ( + .CK(n_0_53), .D(registers[18]), .Q(registers_23__ap[18]), .QN(), .SE(dftIn), + .SI(registers_20__ap[18]) + ); + AOI22_X1_LVT i_1_0_1049( + .A1(registers_8__ap[18]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[18]), + .ZN(n_1_0_998) + ); + SDFF_X1_LVT \registers_reg[13][18] ( + .CK(n_0_43), .D(registers[18]), .Q(registers_13__ap[18]), .QN(), .SE(dftIn), + .SI(registers_12__ap[18]) + ); + SDFF_X1_LVT \registers_reg[17][18] ( + .CK(n_0_47), .D(registers[18]), .Q(registers_17__ap[18]), .QN(), .SE(dftIn), + .SI(registers_23__ap[18]) + ); + AOI22_X1_LVT i_1_0_1048( + .A1(registers_13__ap[18]), .A2(n_1_0_1277), .B1(n_1_0_1271), .B2(registers_17__ap[18]), + .ZN(n_1_0_997) + ); + SDFF_X1_LVT \registers_reg[15][18] ( + .CK(n_0_45), .D(registers[18]), .Q(registers_15__ap[18]), .QN(), .SE(dftIn), + .SI(registers_13__ap[18]) + ); + SDFF_X1_LVT \registers_reg[14][18] ( + .CK(n_0_44), .D(registers[18]), .Q(registers_14__ap[18]), .QN(), .SE(dftIn), + .SI(registers_15__ap[18]) + ); + AOI22_X1_LVT i_1_0_1047( + .A1(registers_15__ap[18]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[18]), + .ZN(n_1_0_996) + ); + NAND3_X1_LVT i_1_0_1046( + .A1(n_1_0_998), .A2(n_1_0_997), .A3(n_1_0_996), .ZN(n_1_0_995) + ); + SDFF_X1_LVT \registers_reg[10][18] ( + .CK(n_0_40), .D(registers[18]), .Q(registers_10__ap[18]), .QN(), .SE(dftIn), + .SI(registers_14__ap[18]) + ); + SDFF_X1_LVT \registers_reg[3][18] ( + .CK(n_0_33), .D(registers[18]), .Q(registers_3__ap[18]), .QN(), .SE(dftIn), + .SI(registers_8__ap[18]) + ); + AOI221_X1_LVT i_1_0_1045( + .A(n_1_0_995), .B1(n_1_0_1287), .B2(registers_10__ap[18]), .C1(registers_3__ap[18]), + .C2(n_1_0_1257), .ZN(n_1_0_994) + ); + NAND4_X1_LVT i_1_0_1044( + .A1(n_1_0_1011), .A2(n_1_0_1004), .A3(n_1_0_999), .A4(n_1_0_994), .ZN(RRs1[18]) + ); + AND2_X1_LVT i_0_0_17( + .A1(n_0_0_16), .A2(WRd[17]), .ZN(registers[17]) + ); + SDFF_X1_LVT \registers_reg[17][17] ( + .CK(n_0_47), .D(registers[17]), .Q(registers_17__ap[17]), .QN(), .SE(dftIn), + .SI(registers_17__ap[18]) + ); + SDFF_X1_LVT \registers_reg[21][17] ( + .CK(n_0_51), .D(registers[17]), .Q(registers_21__ap[17]), .QN(), .SE(dftIn), + .SI(registers_17__ap[17]) + ); + AOI22_X1_LVT i_1_0_1040( + .A1(registers_17__ap[17]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[17]), + .ZN(n_1_0_990) + ); + SDFF_X1_LVT \registers_reg[2][17] ( + .CK(n_0_32), .D(registers[17]), .Q(registers_2__ap[17]), .QN(), .SE(dftIn), + .SI(registers_30__ap[18]) + ); + SDFF_X1_LVT \registers_reg[31][17] ( + .CK(n_0_61), .D(registers[17]), .Q(registers_31__ap[17]), .QN(), .SE(dftIn), + .SI(registers_3__ap[18]) + ); + AOI22_X1_LVT i_1_0_1043( + .A1(registers_2__ap[17]), .A2(n_1_0_1268), .B1(n_1_0_1266), .B2(registers_31__ap[17]), + .ZN(n_1_0_993) + ); + SDFF_X1_LVT \registers_reg[20][17] ( + .CK(n_0_50), .D(registers[17]), .Q(registers_20__ap[17]), .QN(), .SE(dftIn), + .SI(registers_21__ap[17]) + ); + SDFF_X1_LVT \registers_reg[12][17] ( + .CK(n_0_42), .D(registers[17]), .Q(registers_12__ap[17]), .QN(), .SE(dftIn), + .SI(registers_10__ap[18]) + ); + AOI22_X1_LVT i_1_0_1039( + .A1(registers_20__ap[17]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[17]), + .ZN(n_1_0_989) + ); + SDFF_X1_LVT \registers_reg[15][17] ( + .CK(n_0_45), .D(registers[17]), .Q(registers_15__ap[17]), .QN(), .SE(dftIn), + .SI(registers_12__ap[17]) + ); + SDFF_X1_LVT \registers_reg[11][17] ( + .CK(n_0_41), .D(registers[17]), .Q(registers_11__ap[17]), .QN(), .SE(dftIn), + .SI(registers_15__ap[17]) + ); + AOI22_X1_LVT i_1_0_1042( + .A1(registers_15__ap[17]), .A2(n_1_0_1286), .B1(n_1_0_1270), .B2(registers_11__ap[17]), + .ZN(n_1_0_992) + ); + INV_X1_LVT i_1_0_1041( + .A(n_1_0_992), .ZN(n_1_0_991) + ); + SDFF_X1_LVT \registers_reg[10][17] ( + .CK(n_0_40), .D(registers[17]), .Q(registers_10__ap[17]), .QN(), .SE(dftIn), + .SI(registers_11__ap[17]) + ); + SDFF_X1_LVT \registers_reg[24][17] ( + .CK(n_0_54), .D(registers[17]), .Q(registers_24__ap[17]), .QN(), .SE(dftIn), + .SI(registers_2__ap[17]) + ); + AOI221_X1_LVT i_1_0_1038( + .A(n_1_0_991), .B1(n_1_0_1287), .B2(registers_10__ap[17]), .C1(registers_24__ap[17]), + .C2(n_1_0_1289), .ZN(n_1_0_988) + ); + SDFF_X1_LVT \registers_reg[22][17] ( + .CK(n_0_52), .D(registers[17]), .Q(registers_22__ap[17]), .QN(), .SE(dftIn), + .SI(registers_20__ap[17]) + ); + SDFF_X1_LVT \registers_reg[26][17] ( + .CK(n_0_56), .D(registers[17]), .Q(registers_26__ap[17]), .QN(), .SE(dftIn), + .SI(registers_24__ap[17]) + ); + SDFF_X1_LVT \registers_reg[13][17] ( + .CK(n_0_43), .D(registers[17]), .Q(registers_13__ap[17]), .QN(), .SE(dftIn), + .SI(registers_10__ap[17]) + ); + AOI222_X1_LVT i_1_0_1037( + .A1(registers_22__ap[17]), .A2(n_1_0_1294), .B1(n_1_0_1285), .B2(registers_26__ap[17]), + .C1(n_1_0_1277), .C2(registers_13__ap[17]), .ZN(n_1_0_987) + ); + NAND4_X1_LVT i_1_0_1036( + .A1(n_1_0_993), .A2(n_1_0_989), .A3(n_1_0_988), .A4(n_1_0_987), .ZN(n_1_0_986) + ); + SDFF_X1_LVT \registers_reg[1][17] ( + .CK(n_0_0), .D(registers[17]), .Q(registers_1__ap[17]), .QN(), .SE(dftIn), + .SI(registers_22__ap[17]) + ); + SDFF_X1_LVT \registers_reg[28][17] ( + .CK(n_0_58), .D(registers[17]), .Q(registers_28__ap[17]), .QN(), .SE(dftIn), + .SI(registers_26__ap[17]) + ); + AOI221_X1_LVT i_1_0_1035( + .A(n_1_0_986), .B1(n_1_0_1274), .B2(registers_1__ap[17]), .C1(registers_28__ap[17]), + .C2(n_1_0_1283), .ZN(n_1_0_985) + ); + SDFF_X1_LVT \registers_reg[18][17] ( + .CK(n_0_48), .D(registers[17]), .Q(registers_18__ap[17]), .QN(), .SE(dftIn), + .SI(registers_1__ap[17]) + ); + SDFF_X1_LVT \registers_reg[30][17] ( + .CK(n_0_60), .D(registers[17]), .Q(registers_30__ap[17]), .QN(), .SE(dftIn), + .SI(registers_28__ap[17]) + ); + AOI22_X1_LVT i_1_0_1034( + .A1(registers_18__ap[17]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[17]), + .ZN(n_1_0_984) + ); + SDFF_X1_LVT \registers_reg[4][17] ( + .CK(n_0_34), .D(registers[17]), .Q(registers_4__ap[17]), .QN(), .SE(dftIn), + .SI(registers_31__ap[17]) + ); + SDFF_X1_LVT \registers_reg[5][17] ( + .CK(n_0_35), .D(registers[17]), .Q(registers_5__ap[17]), .QN(), .SE(dftIn), + .SI(registers_4__ap[17]) + ); + AOI22_X1_LVT i_1_0_1033( + .A1(registers_4__ap[17]), .A2(n_1_0_1278), .B1(n_1_0_1273), .B2(registers_5__ap[17]), + .ZN(n_1_0_983) + ); + SDFF_X1_LVT \registers_reg[6][17] ( + .CK(n_0_36), .D(registers[17]), .Q(registers_6__ap[17]), .QN(), .SE(dftIn), + .SI(registers_5__ap[17]) + ); + SDFF_X1_LVT \registers_reg[25][17] ( + .CK(n_0_55), .D(registers[17]), .Q(registers_25__ap[17]), .QN(), .SE(dftIn), + .SI(registers_30__ap[17]) + ); + AOI22_X1_LVT i_1_0_1032( + .A1(registers_6__ap[17]), .A2(n_1_0_1300), .B1(n_1_0_1269), .B2(registers_25__ap[17]), + .ZN(n_1_0_982) + ); + NAND3_X1_LVT i_1_0_1031( + .A1(n_1_0_984), .A2(n_1_0_983), .A3(n_1_0_982), .ZN(n_1_0_981) + ); + SDFF_X1_LVT \registers_reg[19][17] ( + .CK(n_0_49), .D(registers[17]), .Q(registers_19__ap[17]), .QN(), .SE(dftIn), + .SI(registers_18__ap[17]) + ); + SDFF_X1_LVT \registers_reg[16][17] ( + .CK(n_0_46), .D(registers[17]), .Q(registers_16__ap[17]), .QN(), .SE(dftIn), + .SI(registers_13__ap[17]) + ); + AOI221_X1_LVT i_1_0_1030( + .A(n_1_0_981), .B1(n_1_0_1295), .B2(registers_19__ap[17]), .C1(registers_16__ap[17]), + .C2(n_1_0_1267), .ZN(n_1_0_980) + ); + SDFF_X1_LVT \registers_reg[7][17] ( + .CK(n_0_37), .D(registers[17]), .Q(registers_7__ap[17]), .QN(), .SE(dftIn), + .SI(registers_6__ap[17]) + ); + SDFF_X1_LVT \registers_reg[14][17] ( + .CK(n_0_44), .D(registers[17]), .Q(registers_14__ap[17]), .QN(), .SE(dftIn), + .SI(registers_16__ap[17]) + ); + AOI22_X1_LVT i_1_0_1029( + .A1(registers_7__ap[17]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[17]), + .ZN(n_1_0_979) + ); + SDFF_X1_LVT \registers_reg[9][17] ( + .CK(n_0_39), .D(registers[17]), .Q(registers_9__ap[17]), .QN(), .SE(dftIn), + .SI(registers_7__ap[17]) + ); + SDFF_X1_LVT \registers_reg[29][17] ( + .CK(n_0_59), .D(registers[17]), .Q(registers_29__ap[17]), .QN(), .SE(dftIn), + .SI(registers_25__ap[17]) + ); + AOI22_X1_LVT i_1_0_1028( + .A1(registers_9__ap[17]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[17]), + .ZN(n_1_0_978) + ); + SDFF_X1_LVT \registers_reg[8][17] ( + .CK(n_0_38), .D(registers[17]), .Q(registers_8__ap[17]), .QN(), .SE(dftIn), + .SI(registers_9__ap[17]) + ); + SDFF_X1_LVT \registers_reg[23][17] ( + .CK(n_0_53), .D(registers[17]), .Q(registers_23__ap[17]), .QN(), .SE(dftIn), + .SI(registers_19__ap[17]) + ); + AOI22_X1_LVT i_1_0_1027( + .A1(registers_8__ap[17]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[17]), + .ZN(n_1_0_977) + ); + NAND3_X1_LVT i_1_0_1026( + .A1(n_1_0_979), .A2(n_1_0_978), .A3(n_1_0_977), .ZN(n_1_0_976) + ); + SDFF_X1_LVT \registers_reg[27][17] ( + .CK(n_0_57), .D(registers[17]), .Q(registers_27__ap[17]), .QN(), .SE(dftIn), + .SI(registers_29__ap[17]) + ); + SDFF_X1_LVT \registers_reg[3][17] ( + .CK(n_0_33), .D(registers[17]), .Q(registers_3__ap[17]), .QN(), .SE(dftIn), + .SI(registers_8__ap[17]) + ); + AOI221_X1_LVT i_1_0_1025( + .A(n_1_0_976), .B1(n_1_0_1279), .B2(registers_27__ap[17]), .C1(registers_3__ap[17]), + .C2(n_1_0_1257), .ZN(n_1_0_975) + ); + NAND4_X1_LVT i_1_0_1024( + .A1(n_1_0_990), .A2(n_1_0_985), .A3(n_1_0_980), .A4(n_1_0_975), .ZN(RRs1[17]) + ); + AND2_X1_LVT i_0_0_16( + .A1(n_0_0_16), .A2(WRd[16]), .ZN(registers[16]) + ); + SDFF_X1_LVT \registers_reg[29][16] ( + .CK(n_0_59), .D(registers[16]), .Q(registers_29__ap[16]), .QN(), .SE(dftIn), + .SI(registers_27__ap[17]) + ); + SDFF_X1_LVT \registers_reg[2][16] ( + .CK(n_0_32), .D(registers[16]), .Q(registers_2__ap[16]), .QN(), .SE(dftIn), + .SI(registers_29__ap[16]) + ); + AOI22_X1_LVT i_1_0_1022( + .A1(registers_29__ap[16]), .A2(n_1_0_1276), .B1(n_1_0_1268), .B2(registers_2__ap[16]), + .ZN(n_1_0_973) + ); + SDFF_X1_LVT \registers_reg[11][16] ( + .CK(n_0_41), .D(registers[16]), .Q(registers_11__ap[16]), .QN(), .SE(dftIn), + .SI(registers_14__ap[17]) + ); + SDFF_X1_LVT \registers_reg[25][16] ( + .CK(n_0_55), .D(registers[16]), .Q(registers_25__ap[16]), .QN(), .SE(dftIn), + .SI(registers_2__ap[16]) + ); + AOI22_X1_LVT i_1_0_1023( + .A1(registers_11__ap[16]), .A2(n_1_0_1270), .B1(n_1_0_1269), .B2(registers_25__ap[16]), + .ZN(n_1_0_974) + ); + SDFF_X1_LVT \registers_reg[9][16] ( + .CK(n_0_39), .D(registers[16]), .Q(registers_9__ap[16]), .QN(), .SE(dftIn), + .SI(registers_3__ap[17]) + ); + SDFF_X1_LVT \registers_reg[7][16] ( + .CK(n_0_37), .D(registers[16]), .Q(registers_7__ap[16]), .QN(), .SE(dftIn), + .SI(registers_9__ap[16]) + ); + AOI22_X1_LVT i_1_0_1021( + .A1(registers_9__ap[16]), .A2(n_1_0_1291), .B1(n_1_0_1263), .B2(registers_7__ap[16]), + .ZN(n_1_0_972) + ); + SDFF_X1_LVT \registers_reg[10][16] ( + .CK(n_0_40), .D(registers[16]), .Q(registers_10__ap[16]), .QN(), .SE(dftIn), + .SI(registers_11__ap[16]) + ); + SDFF_X1_LVT \registers_reg[16][16] ( + .CK(n_0_46), .D(registers[16]), .Q(registers_16__ap[16]), .QN(), .SE(dftIn), + .SI(registers_10__ap[16]) + ); + AOI22_X1_LVT i_1_0_1020( + .A1(registers_10__ap[16]), .A2(n_1_0_1287), .B1(n_1_0_1267), .B2(registers_16__ap[16]), + .ZN(n_1_0_971) + ); + NAND3_X1_LVT i_1_0_1019( + .A1(n_1_0_974), .A2(n_1_0_972), .A3(n_1_0_971), .ZN(n_1_0_970) + ); + SDFF_X1_LVT \registers_reg[31][16] ( + .CK(n_0_61), .D(registers[16]), .Q(registers_31__ap[16]), .QN(), .SE(dftIn), + .SI(registers_7__ap[16]) + ); + SDFF_X1_LVT \registers_reg[6][16] ( + .CK(n_0_36), .D(registers[16]), .Q(registers_6__ap[16]), .QN(), .SE(dftIn), + .SI(registers_31__ap[16]) + ); + AOI221_X1_LVT i_1_0_1018( + .A(n_1_0_970), .B1(n_1_0_1266), .B2(registers_31__ap[16]), .C1(registers_6__ap[16]), + .C2(n_1_0_1300), .ZN(n_1_0_969) + ); + SDFF_X1_LVT \registers_reg[18][16] ( + .CK(n_0_48), .D(registers[16]), .Q(registers_18__ap[16]), .QN(), .SE(dftIn), + .SI(registers_23__ap[17]) + ); + SDFF_X1_LVT \registers_reg[22][16] ( + .CK(n_0_52), .D(registers[16]), .Q(registers_22__ap[16]), .QN(), .SE(dftIn), + .SI(registers_18__ap[16]) + ); + SDFF_X1_LVT \registers_reg[1][16] ( + .CK(n_0_0), .D(registers[16]), .Q(registers_1__ap[16]), .QN(), .SE(dftIn), + .SI(registers_22__ap[16]) + ); + AOI222_X1_LVT i_1_0_1017( + .A1(registers_18__ap[16]), .A2(n_1_0_1297), .B1(n_1_0_1294), .B2(registers_22__ap[16]), + .C1(registers_1__ap[16]), .C2(n_1_0_1274), .ZN(n_1_0_968) + ); + NAND3_X1_LVT i_1_0_1016( + .A1(n_1_0_973), .A2(n_1_0_969), .A3(n_1_0_968), .ZN(n_1_0_967) + ); + SDFF_X1_LVT \registers_reg[5][16] ( + .CK(n_0_35), .D(registers[16]), .Q(registers_5__ap[16]), .QN(), .SE(dftIn), + .SI(registers_6__ap[16]) + ); + SDFF_X1_LVT \registers_reg[28][16] ( + .CK(n_0_58), .D(registers[16]), .Q(registers_28__ap[16]), .QN(), .SE(dftIn), + .SI(registers_25__ap[16]) + ); + AOI221_X1_LVT i_1_0_1015( + .A(n_1_0_967), .B1(n_1_0_1273), .B2(registers_5__ap[16]), .C1(registers_28__ap[16]), + .C2(n_1_0_1283), .ZN(n_1_0_966) + ); + SDFF_X1_LVT \registers_reg[4][16] ( + .CK(n_0_34), .D(registers[16]), .Q(registers_4__ap[16]), .QN(), .SE(dftIn), + .SI(registers_5__ap[16]) + ); + SDFF_X1_LVT \registers_reg[12][16] ( + .CK(n_0_42), .D(registers[16]), .Q(registers_12__ap[16]), .QN(), .SE(dftIn), + .SI(registers_16__ap[16]) + ); + AOI22_X1_LVT i_1_0_1014( + .A1(registers_4__ap[16]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[16]), + .ZN(n_1_0_965) + ); + SDFF_X1_LVT \registers_reg[19][16] ( + .CK(n_0_49), .D(registers[16]), .Q(registers_19__ap[16]), .QN(), .SE(dftIn), + .SI(registers_1__ap[16]) + ); + SDFF_X1_LVT \registers_reg[21][16] ( + .CK(n_0_51), .D(registers[16]), .Q(registers_21__ap[16]), .QN(), .SE(dftIn), + .SI(registers_19__ap[16]) + ); + AOI22_X1_LVT i_1_0_1013( + .A1(registers_19__ap[16]), .A2(n_1_0_1295), .B1(n_1_0_1259), .B2(registers_21__ap[16]), + .ZN(n_1_0_964) + ); + SDFF_X1_LVT \registers_reg[24][16] ( + .CK(n_0_54), .D(registers[16]), .Q(registers_24__ap[16]), .QN(), .SE(dftIn), + .SI(registers_28__ap[16]) + ); + SDFF_X1_LVT \registers_reg[20][16] ( + .CK(n_0_50), .D(registers[16]), .Q(registers_20__ap[16]), .QN(), .SE(dftIn), + .SI(registers_21__ap[16]) + ); + AOI22_X1_LVT i_1_0_1012( + .A1(registers_24__ap[16]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[16]), + .ZN(n_1_0_963) + ); + NAND3_X1_LVT i_1_0_1011( + .A1(n_1_0_965), .A2(n_1_0_964), .A3(n_1_0_963), .ZN(n_1_0_962) + ); + SDFF_X1_LVT \registers_reg[26][16] ( + .CK(n_0_56), .D(registers[16]), .Q(registers_26__ap[16]), .QN(), .SE(dftIn), + .SI(registers_24__ap[16]) + ); + SDFF_X1_LVT \registers_reg[30][16] ( + .CK(n_0_60), .D(registers[16]), .Q(registers_30__ap[16]), .QN(), .SE(dftIn), + .SI(registers_26__ap[16]) + ); + AOI221_X1_LVT i_1_0_1010( + .A(n_1_0_962), .B1(n_1_0_1285), .B2(registers_26__ap[16]), .C1(registers_30__ap[16]), + .C2(n_1_0_1272), .ZN(n_1_0_961) + ); + SDFF_X1_LVT \registers_reg[8][16] ( + .CK(n_0_38), .D(registers[16]), .Q(registers_8__ap[16]), .QN(), .SE(dftIn), + .SI(registers_4__ap[16]) + ); + SDFF_X1_LVT \registers_reg[23][16] ( + .CK(n_0_53), .D(registers[16]), .Q(registers_23__ap[16]), .QN(), .SE(dftIn), + .SI(registers_20__ap[16]) + ); + AOI22_X1_LVT i_1_0_1009( + .A1(registers_8__ap[16]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[16]), + .ZN(n_1_0_960) + ); + SDFF_X1_LVT \registers_reg[13][16] ( + .CK(n_0_43), .D(registers[16]), .Q(registers_13__ap[16]), .QN(), .SE(dftIn), + .SI(registers_12__ap[16]) + ); + SDFF_X1_LVT \registers_reg[17][16] ( + .CK(n_0_47), .D(registers[16]), .Q(registers_17__ap[16]), .QN(), .SE(dftIn), + .SI(registers_23__ap[16]) + ); + AOI22_X1_LVT i_1_0_1008( + .A1(registers_13__ap[16]), .A2(n_1_0_1277), .B1(n_1_0_1271), .B2(registers_17__ap[16]), + .ZN(n_1_0_959) + ); + SDFF_X1_LVT \registers_reg[15][16] ( + .CK(n_0_45), .D(registers[16]), .Q(registers_15__ap[16]), .QN(), .SE(dftIn), + .SI(registers_13__ap[16]) + ); + SDFF_X1_LVT \registers_reg[14][16] ( + .CK(n_0_44), .D(registers[16]), .Q(registers_14__ap[16]), .QN(), .SE(dftIn), + .SI(registers_15__ap[16]) + ); + AOI22_X1_LVT i_1_0_1007( + .A1(registers_15__ap[16]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[16]), + .ZN(n_1_0_958) + ); + NAND3_X1_LVT i_1_0_1006( + .A1(n_1_0_960), .A2(n_1_0_959), .A3(n_1_0_958), .ZN(n_1_0_957) + ); + SDFF_X1_LVT \registers_reg[27][16] ( + .CK(n_0_57), .D(registers[16]), .Q(registers_27__ap[16]), .QN(), .SE(dftIn), + .SI(registers_30__ap[16]) + ); + SDFF_X1_LVT \registers_reg[3][16] ( + .CK(n_0_33), .D(registers[16]), .Q(registers_3__ap[16]), .QN(), .SE(dftIn), + .SI(registers_8__ap[16]) + ); + AOI221_X1_LVT i_1_0_1005( + .A(n_1_0_957), .B1(n_1_0_1279), .B2(registers_27__ap[16]), .C1(registers_3__ap[16]), + .C2(n_1_0_1257), .ZN(n_1_0_956) + ); + NAND3_X1_LVT i_1_0_1004( + .A1(n_1_0_966), .A2(n_1_0_961), .A3(n_1_0_956), .ZN(RRs1[16]) + ); + AND2_X1_LVT i_0_0_15( + .A1(n_0_0_16), .A2(WRd[15]), .ZN(registers[15]) + ); + SDFF_X1_LVT \registers_reg[17][15] ( + .CK(n_0_47), .D(registers[15]), .Q(registers_17__ap[15]), .QN(), .SE(dftIn), + .SI(registers_17__ap[16]) + ); + SDFF_X1_LVT \registers_reg[21][15] ( + .CK(n_0_51), .D(registers[15]), .Q(registers_21__ap[15]), .QN(), .SE(dftIn), + .SI(registers_17__ap[15]) + ); + AOI22_X1_LVT i_1_0_1000( + .A1(registers_17__ap[15]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[15]), + .ZN(n_1_0_952) + ); + SDFF_X1_LVT \registers_reg[10][15] ( + .CK(n_0_40), .D(registers[15]), .Q(registers_10__ap[15]), .QN(), .SE(dftIn), + .SI(registers_14__ap[16]) + ); + SDFF_X1_LVT \registers_reg[2][15] ( + .CK(n_0_32), .D(registers[15]), .Q(registers_2__ap[15]), .QN(), .SE(dftIn), + .SI(registers_27__ap[16]) + ); + AOI22_X1_LVT i_1_0_1003( + .A1(registers_10__ap[15]), .A2(n_1_0_1287), .B1(n_1_0_1268), .B2(registers_2__ap[15]), + .ZN(n_1_0_955) + ); + SDFF_X1_LVT \registers_reg[20][15] ( + .CK(n_0_50), .D(registers[15]), .Q(registers_20__ap[15]), .QN(), .SE(dftIn), + .SI(registers_21__ap[15]) + ); + SDFF_X1_LVT \registers_reg[12][15] ( + .CK(n_0_42), .D(registers[15]), .Q(registers_12__ap[15]), .QN(), .SE(dftIn), + .SI(registers_10__ap[15]) + ); + AOI22_X1_LVT i_1_0_999( + .A1(registers_20__ap[15]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[15]), + .ZN(n_1_0_951) + ); + SDFF_X1_LVT \registers_reg[15][15] ( + .CK(n_0_45), .D(registers[15]), .Q(registers_15__ap[15]), .QN(), .SE(dftIn), + .SI(registers_12__ap[15]) + ); + SDFF_X1_LVT \registers_reg[8][15] ( + .CK(n_0_38), .D(registers[15]), .Q(registers_8__ap[15]), .QN(), .SE(dftIn), + .SI(registers_3__ap[16]) + ); + AOI22_X1_LVT i_1_0_1002( + .A1(registers_15__ap[15]), .A2(n_1_0_1286), .B1(n_1_0_1282), .B2(registers_8__ap[15]), + .ZN(n_1_0_954) + ); + INV_X1_LVT i_1_0_1001( + .A(n_1_0_954), .ZN(n_1_0_953) + ); + SDFF_X1_LVT \registers_reg[11][15] ( + .CK(n_0_41), .D(registers[15]), .Q(registers_11__ap[15]), .QN(), .SE(dftIn), + .SI(registers_15__ap[15]) + ); + SDFF_X1_LVT \registers_reg[24][15] ( + .CK(n_0_54), .D(registers[15]), .Q(registers_24__ap[15]), .QN(), .SE(dftIn), + .SI(registers_2__ap[15]) + ); + AOI221_X1_LVT i_1_0_998( + .A(n_1_0_953), .B1(n_1_0_1270), .B2(registers_11__ap[15]), .C1(registers_24__ap[15]), + .C2(n_1_0_1289), .ZN(n_1_0_950) + ); + SDFF_X1_LVT \registers_reg[13][15] ( + .CK(n_0_43), .D(registers[15]), .Q(registers_13__ap[15]), .QN(), .SE(dftIn), + .SI(registers_11__ap[15]) + ); + SDFF_X1_LVT \registers_reg[30][15] ( + .CK(n_0_60), .D(registers[15]), .Q(registers_30__ap[15]), .QN(), .SE(dftIn), + .SI(registers_24__ap[15]) + ); + SDFF_X1_LVT \registers_reg[22][15] ( + .CK(n_0_52), .D(registers[15]), .Q(registers_22__ap[15]), .QN(), .SE(dftIn), + .SI(registers_20__ap[15]) + ); + AOI222_X1_LVT i_1_0_997( + .A1(registers_13__ap[15]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[15]), + .C1(registers_22__ap[15]), .C2(n_1_0_1294), .ZN(n_1_0_949) + ); + NAND4_X1_LVT i_1_0_996( + .A1(n_1_0_955), .A2(n_1_0_951), .A3(n_1_0_950), .A4(n_1_0_949), .ZN(n_1_0_948) + ); + SDFF_X1_LVT \registers_reg[1][15] ( + .CK(n_0_0), .D(registers[15]), .Q(registers_1__ap[15]), .QN(), .SE(dftIn), + .SI(registers_22__ap[15]) + ); + SDFF_X1_LVT \registers_reg[28][15] ( + .CK(n_0_58), .D(registers[15]), .Q(registers_28__ap[15]), .QN(), .SE(dftIn), + .SI(registers_30__ap[15]) + ); + AOI221_X1_LVT i_1_0_995( + .A(n_1_0_948), .B1(n_1_0_1274), .B2(registers_1__ap[15]), .C1(registers_28__ap[15]), + .C2(n_1_0_1283), .ZN(n_1_0_947) + ); + SDFF_X1_LVT \registers_reg[18][15] ( + .CK(n_0_48), .D(registers[15]), .Q(registers_18__ap[15]), .QN(), .SE(dftIn), + .SI(registers_1__ap[15]) + ); + SDFF_X1_LVT \registers_reg[26][15] ( + .CK(n_0_56), .D(registers[15]), .Q(registers_26__ap[15]), .QN(), .SE(dftIn), + .SI(registers_28__ap[15]) + ); + AOI22_X1_LVT i_1_0_994( + .A1(registers_18__ap[15]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[15]), + .ZN(n_1_0_946) + ); + SDFF_X1_LVT \registers_reg[4][15] ( + .CK(n_0_34), .D(registers[15]), .Q(registers_4__ap[15]), .QN(), .SE(dftIn), + .SI(registers_8__ap[15]) + ); + SDFF_X1_LVT \registers_reg[5][15] ( + .CK(n_0_35), .D(registers[15]), .Q(registers_5__ap[15]), .QN(), .SE(dftIn), + .SI(registers_4__ap[15]) + ); + AOI22_X1_LVT i_1_0_993( + .A1(registers_4__ap[15]), .A2(n_1_0_1278), .B1(n_1_0_1273), .B2(registers_5__ap[15]), + .ZN(n_1_0_945) + ); + SDFF_X1_LVT \registers_reg[6][15] ( + .CK(n_0_36), .D(registers[15]), .Q(registers_6__ap[15]), .QN(), .SE(dftIn), + .SI(registers_5__ap[15]) + ); + SDFF_X1_LVT \registers_reg[16][15] ( + .CK(n_0_46), .D(registers[15]), .Q(registers_16__ap[15]), .QN(), .SE(dftIn), + .SI(registers_13__ap[15]) + ); + AOI22_X1_LVT i_1_0_992( + .A1(registers_6__ap[15]), .A2(n_1_0_1300), .B1(n_1_0_1267), .B2(registers_16__ap[15]), + .ZN(n_1_0_944) + ); + NAND3_X1_LVT i_1_0_991( + .A1(n_1_0_946), .A2(n_1_0_945), .A3(n_1_0_944), .ZN(n_1_0_943) + ); + SDFF_X1_LVT \registers_reg[19][15] ( + .CK(n_0_49), .D(registers[15]), .Q(registers_19__ap[15]), .QN(), .SE(dftIn), + .SI(registers_18__ap[15]) + ); + SDFF_X1_LVT \registers_reg[25][15] ( + .CK(n_0_55), .D(registers[15]), .Q(registers_25__ap[15]), .QN(), .SE(dftIn), + .SI(registers_26__ap[15]) + ); + AOI221_X1_LVT i_1_0_990( + .A(n_1_0_943), .B1(n_1_0_1295), .B2(registers_19__ap[15]), .C1(registers_25__ap[15]), + .C2(n_1_0_1269), .ZN(n_1_0_942) + ); + SDFF_X1_LVT \registers_reg[7][15] ( + .CK(n_0_37), .D(registers[15]), .Q(registers_7__ap[15]), .QN(), .SE(dftIn), + .SI(registers_6__ap[15]) + ); + SDFF_X1_LVT \registers_reg[14][15] ( + .CK(n_0_44), .D(registers[15]), .Q(registers_14__ap[15]), .QN(), .SE(dftIn), + .SI(registers_16__ap[15]) + ); + AOI22_X1_LVT i_1_0_989( + .A1(registers_7__ap[15]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[15]), + .ZN(n_1_0_941) + ); + SDFF_X1_LVT \registers_reg[9][15] ( + .CK(n_0_39), .D(registers[15]), .Q(registers_9__ap[15]), .QN(), .SE(dftIn), + .SI(registers_7__ap[15]) + ); + SDFF_X1_LVT \registers_reg[29][15] ( + .CK(n_0_59), .D(registers[15]), .Q(registers_29__ap[15]), .QN(), .SE(dftIn), + .SI(registers_25__ap[15]) + ); + AOI22_X1_LVT i_1_0_988( + .A1(registers_9__ap[15]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[15]), + .ZN(n_1_0_940) + ); + SDFF_X1_LVT \registers_reg[23][15] ( + .CK(n_0_53), .D(registers[15]), .Q(registers_23__ap[15]), .QN(), .SE(dftIn), + .SI(registers_19__ap[15]) + ); + SDFF_X1_LVT \registers_reg[3][15] ( + .CK(n_0_33), .D(registers[15]), .Q(registers_3__ap[15]), .QN(), .SE(dftIn), + .SI(registers_9__ap[15]) + ); + AOI22_X1_LVT i_1_0_987( + .A1(registers_23__ap[15]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[15]), + .ZN(n_1_0_939) + ); + NAND3_X1_LVT i_1_0_986( + .A1(n_1_0_941), .A2(n_1_0_940), .A3(n_1_0_939), .ZN(n_1_0_938) + ); + SDFF_X1_LVT \registers_reg[27][15] ( + .CK(n_0_57), .D(registers[15]), .Q(registers_27__ap[15]), .QN(), .SE(dftIn), + .SI(registers_29__ap[15]) + ); + SDFF_X1_LVT \registers_reg[31][15] ( + .CK(n_0_61), .D(registers[15]), .Q(registers_31__ap[15]), .QN(), .SE(dftIn), + .SI(registers_3__ap[15]) + ); + AOI221_X1_LVT i_1_0_985( + .A(n_1_0_938), .B1(n_1_0_1279), .B2(registers_27__ap[15]), .C1(registers_31__ap[15]), + .C2(n_1_0_1266), .ZN(n_1_0_937) + ); + NAND4_X1_LVT i_1_0_984( + .A1(n_1_0_952), .A2(n_1_0_947), .A3(n_1_0_942), .A4(n_1_0_937), .ZN(RRs1[15]) + ); + AND2_X1_LVT i_0_0_14( + .A1(n_0_0_16), .A2(WRd[14]), .ZN(registers[14]) + ); + SDFF_X1_LVT \registers_reg[28][14] ( + .CK(n_0_58), .D(registers[14]), .Q(registers_28__ap[14]), .QN(), .SE(dftIn), + .SI(registers_27__ap[15]) + ); + SDFF_X1_LVT \registers_reg[5][14] ( + .CK(n_0_35), .D(registers[14]), .Q(registers_5__ap[14]), .QN(), .SE(dftIn), + .SI(registers_31__ap[15]) + ); + AOI22_X1_LVT i_1_0_983( + .A1(registers_28__ap[14]), .A2(n_1_0_1283), .B1(n_1_0_1273), .B2(registers_5__ap[14]), + .ZN(n_1_0_936) + ); + SDFF_X1_LVT \registers_reg[18][14] ( + .CK(n_0_48), .D(registers[14]), .Q(registers_18__ap[14]), .QN(), .SE(dftIn), + .SI(registers_23__ap[15]) + ); + SDFF_X1_LVT \registers_reg[10][14] ( + .CK(n_0_40), .D(registers[14]), .Q(registers_10__ap[14]), .QN(), .SE(dftIn), + .SI(registers_14__ap[15]) + ); + SDFF_X1_LVT \registers_reg[8][14] ( + .CK(n_0_38), .D(registers[14]), .Q(registers_8__ap[14]), .QN(), .SE(dftIn), + .SI(registers_5__ap[14]) + ); + AOI222_X1_LVT i_1_0_982( + .A1(registers_18__ap[14]), .A2(n_1_0_1297), .B1(n_1_0_1287), .B2(registers_10__ap[14]), + .C1(n_1_0_1282), .C2(registers_8__ap[14]), .ZN(n_1_0_935) + ); + SDFF_X1_LVT \registers_reg[9][14] ( + .CK(n_0_39), .D(registers[14]), .Q(registers_9__ap[14]), .QN(), .SE(dftIn), + .SI(registers_8__ap[14]) + ); + SDFF_X1_LVT \registers_reg[29][14] ( + .CK(n_0_59), .D(registers[14]), .Q(registers_29__ap[14]), .QN(), .SE(dftIn), + .SI(registers_28__ap[14]) + ); + AOI22_X1_LVT i_1_0_981( + .A1(registers_9__ap[14]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[14]), + .ZN(n_1_0_934) + ); + SDFF_X1_LVT \registers_reg[21][14] ( + .CK(n_0_51), .D(registers[14]), .Q(registers_21__ap[14]), .QN(), .SE(dftIn), + .SI(registers_18__ap[14]) + ); + SDFF_X1_LVT \registers_reg[14][14] ( + .CK(n_0_44), .D(registers[14]), .Q(registers_14__ap[14]), .QN(), .SE(dftIn), + .SI(registers_10__ap[14]) + ); + AOI22_X1_LVT i_1_0_980( + .A1(registers_21__ap[14]), .A2(n_1_0_1259), .B1(n_1_0_1258), .B2(registers_14__ap[14]), + .ZN(n_1_0_933) + ); + SDFF_X1_LVT \registers_reg[16][14] ( + .CK(n_0_46), .D(registers[14]), .Q(registers_16__ap[14]), .QN(), .SE(dftIn), + .SI(registers_14__ap[14]) + ); + SDFF_X1_LVT \registers_reg[3][14] ( + .CK(n_0_33), .D(registers[14]), .Q(registers_3__ap[14]), .QN(), .SE(dftIn), + .SI(registers_9__ap[14]) + ); + AOI22_X1_LVT i_1_0_979( + .A1(registers_16__ap[14]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[14]), + .ZN(n_1_0_932) + ); + SDFF_X1_LVT \registers_reg[17][14] ( + .CK(n_0_47), .D(registers[14]), .Q(registers_17__ap[14]), .QN(), .SE(dftIn), + .SI(registers_21__ap[14]) + ); + SDFF_X1_LVT \registers_reg[31][14] ( + .CK(n_0_61), .D(registers[14]), .Q(registers_31__ap[14]), .QN(), .SE(dftIn), + .SI(registers_3__ap[14]) + ); + AOI22_X1_LVT i_1_0_978( + .A1(registers_17__ap[14]), .A2(n_1_0_1271), .B1(n_1_0_1266), .B2(registers_31__ap[14]), + .ZN(n_1_0_931) + ); + SDFF_X1_LVT \registers_reg[15][14] ( + .CK(n_0_45), .D(registers[14]), .Q(registers_15__ap[14]), .QN(), .SE(dftIn), + .SI(registers_16__ap[14]) + ); + SDFF_X1_LVT \registers_reg[23][14] ( + .CK(n_0_53), .D(registers[14]), .Q(registers_23__ap[14]), .QN(), .SE(dftIn), + .SI(registers_17__ap[14]) + ); + AOI22_X1_LVT i_1_0_977( + .A1(registers_15__ap[14]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[14]), + .ZN(n_1_0_930) + ); + NAND4_X1_LVT i_1_0_976( + .A1(n_1_0_933), .A2(n_1_0_932), .A3(n_1_0_931), .A4(n_1_0_930), .ZN(n_1_0_929) + ); + SDFF_X1_LVT \registers_reg[26][14] ( + .CK(n_0_56), .D(registers[14]), .Q(registers_26__ap[14]), .QN(), .SE(dftIn), + .SI(registers_29__ap[14]) + ); + SDFF_X1_LVT \registers_reg[30][14] ( + .CK(n_0_60), .D(registers[14]), .Q(registers_30__ap[14]), .QN(), .SE(dftIn), + .SI(registers_26__ap[14]) + ); + AOI22_X1_LVT i_1_0_975( + .A1(registers_26__ap[14]), .A2(n_1_0_1285), .B1(n_1_0_1272), .B2(registers_30__ap[14]), + .ZN(n_1_0_928) + ); + SDFF_X1_LVT \registers_reg[20][14] ( + .CK(n_0_50), .D(registers[14]), .Q(registers_20__ap[14]), .QN(), .SE(dftIn), + .SI(registers_23__ap[14]) + ); + SDFF_X1_LVT \registers_reg[4][14] ( + .CK(n_0_34), .D(registers[14]), .Q(registers_4__ap[14]), .QN(), .SE(dftIn), + .SI(registers_31__ap[14]) + ); + AOI22_X1_LVT i_1_0_974( + .A1(registers_20__ap[14]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[14]), + .ZN(n_1_0_927) + ); + SDFF_X1_LVT \registers_reg[1][14] ( + .CK(n_0_0), .D(registers[14]), .Q(registers_1__ap[14]), .QN(), .SE(dftIn), + .SI(registers_20__ap[14]) + ); + SDFF_X1_LVT \registers_reg[2][14] ( + .CK(n_0_32), .D(registers[14]), .Q(registers_2__ap[14]), .QN(), .SE(dftIn), + .SI(registers_30__ap[14]) + ); + AOI22_X1_LVT i_1_0_973( + .A1(registers_1__ap[14]), .A2(n_1_0_1274), .B1(n_1_0_1268), .B2(registers_2__ap[14]), + .ZN(n_1_0_926) + ); + SDFF_X1_LVT \registers_reg[24][14] ( + .CK(n_0_54), .D(registers[14]), .Q(registers_24__ap[14]), .QN(), .SE(dftIn), + .SI(registers_2__ap[14]) + ); + SDFF_X1_LVT \registers_reg[12][14] ( + .CK(n_0_42), .D(registers[14]), .Q(registers_12__ap[14]), .QN(), .SE(dftIn), + .SI(registers_15__ap[14]) + ); + AOI22_X1_LVT i_1_0_972( + .A1(registers_24__ap[14]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[14]), + .ZN(n_1_0_925) + ); + NAND4_X1_LVT i_1_0_971( + .A1(n_1_0_928), .A2(n_1_0_927), .A3(n_1_0_926), .A4(n_1_0_925), .ZN(n_1_0_924) + ); + SDFF_X1_LVT \registers_reg[19][14] ( + .CK(n_0_49), .D(registers[14]), .Q(registers_19__ap[14]), .QN(), .SE(dftIn), + .SI(registers_1__ap[14]) + ); + SDFF_X1_LVT \registers_reg[22][14] ( + .CK(n_0_52), .D(registers[14]), .Q(registers_22__ap[14]), .QN(), .SE(dftIn), + .SI(registers_19__ap[14]) + ); + AOI22_X1_LVT i_1_0_970( + .A1(registers_19__ap[14]), .A2(n_1_0_1295), .B1(n_1_0_1294), .B2(registers_22__ap[14]), + .ZN(n_1_0_923) + ); + SDFF_X1_LVT \registers_reg[13][14] ( + .CK(n_0_43), .D(registers[14]), .Q(registers_13__ap[14]), .QN(), .SE(dftIn), + .SI(registers_12__ap[14]) + ); + SDFF_X1_LVT \registers_reg[25][14] ( + .CK(n_0_55), .D(registers[14]), .Q(registers_25__ap[14]), .QN(), .SE(dftIn), + .SI(registers_24__ap[14]) + ); + AOI22_X1_LVT i_1_0_969( + .A1(registers_13__ap[14]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[14]), + .ZN(n_1_0_922) + ); + SDFF_X1_LVT \registers_reg[6][14] ( + .CK(n_0_36), .D(registers[14]), .Q(registers_6__ap[14]), .QN(), .SE(dftIn), + .SI(registers_4__ap[14]) + ); + SDFF_X1_LVT \registers_reg[7][14] ( + .CK(n_0_37), .D(registers[14]), .Q(registers_7__ap[14]), .QN(), .SE(dftIn), + .SI(registers_6__ap[14]) + ); + AOI22_X1_LVT i_1_0_968( + .A1(registers_6__ap[14]), .A2(n_1_0_1300), .B1(n_1_0_1263), .B2(registers_7__ap[14]), + .ZN(n_1_0_921) + ); + SDFF_X1_LVT \registers_reg[27][14] ( + .CK(n_0_57), .D(registers[14]), .Q(registers_27__ap[14]), .QN(), .SE(dftIn), + .SI(registers_25__ap[14]) + ); + SDFF_X1_LVT \registers_reg[11][14] ( + .CK(n_0_41), .D(registers[14]), .Q(registers_11__ap[14]), .QN(), .SE(dftIn), + .SI(registers_13__ap[14]) + ); + AOI22_X1_LVT i_1_0_967( + .A1(registers_27__ap[14]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[14]), + .ZN(n_1_0_920) + ); + NAND4_X1_LVT i_1_0_966( + .A1(n_1_0_923), .A2(n_1_0_922), .A3(n_1_0_921), .A4(n_1_0_920), .ZN(n_1_0_919) + ); + NOR3_X1_LVT i_1_0_965( + .A1(n_1_0_929), .A2(n_1_0_924), .A3(n_1_0_919), .ZN(n_1_0_918) + ); + NAND4_X1_LVT i_1_0_964( + .A1(n_1_0_936), .A2(n_1_0_935), .A3(n_1_0_934), .A4(n_1_0_918), .ZN(RRs1[14]) + ); + AND2_X1_LVT i_0_0_13( + .A1(n_0_0_16), .A2(WRd[13]), .ZN(registers[13]) + ); + SDFF_X1_LVT \registers_reg[28][13] ( + .CK(n_0_58), .D(registers[13]), .Q(registers_28__ap[13]), .QN(), .SE(dftIn), + .SI(registers_27__ap[14]) + ); + SDFF_X1_LVT \registers_reg[4][13] ( + .CK(n_0_34), .D(registers[13]), .Q(registers_4__ap[13]), .QN(), .SE(dftIn), + .SI(registers_7__ap[14]) + ); + AOI22_X1_LVT i_1_0_963( + .A1(registers_28__ap[13]), .A2(n_1_0_1283), .B1(n_1_0_1278), .B2(registers_4__ap[13]), + .ZN(n_1_0_917) + ); + SDFF_X1_LVT \registers_reg[10][13] ( + .CK(n_0_40), .D(registers[13]), .Q(registers_10__ap[13]), .QN(), .SE(dftIn), + .SI(registers_11__ap[14]) + ); + SDFF_X1_LVT \registers_reg[26][13] ( + .CK(n_0_56), .D(registers[13]), .Q(registers_26__ap[13]), .QN(), .SE(dftIn), + .SI(registers_28__ap[13]) + ); + SDFF_X1_LVT \registers_reg[8][13] ( + .CK(n_0_38), .D(registers[13]), .Q(registers_8__ap[13]), .QN(), .SE(dftIn), + .SI(registers_4__ap[13]) + ); + AOI222_X1_LVT i_1_0_962( + .A1(registers_10__ap[13]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[13]), + .C1(registers_8__ap[13]), .C2(n_1_0_1282), .ZN(n_1_0_916) + ); + SDFF_X1_LVT \registers_reg[9][13] ( + .CK(n_0_39), .D(registers[13]), .Q(registers_9__ap[13]), .QN(), .SE(dftIn), + .SI(registers_8__ap[13]) + ); + SDFF_X1_LVT \registers_reg[29][13] ( + .CK(n_0_59), .D(registers[13]), .Q(registers_29__ap[13]), .QN(), .SE(dftIn), + .SI(registers_26__ap[13]) + ); + AOI22_X1_LVT i_1_0_961( + .A1(registers_9__ap[13]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[13]), + .ZN(n_1_0_915) + ); + SDFF_X1_LVT \registers_reg[6][13] ( + .CK(n_0_36), .D(registers[13]), .Q(registers_6__ap[13]), .QN(), .SE(dftIn), + .SI(registers_9__ap[13]) + ); + SDFF_X1_LVT \registers_reg[1][13] ( + .CK(n_0_0), .D(registers[13]), .Q(registers_1__ap[13]), .QN(), .SE(dftIn), + .SI(registers_22__ap[14]) + ); + AOI22_X1_LVT i_1_0_960( + .A1(registers_6__ap[13]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[13]), + .ZN(n_1_0_914) + ); + SDFF_X1_LVT \registers_reg[5][13] ( + .CK(n_0_35), .D(registers[13]), .Q(registers_5__ap[13]), .QN(), .SE(dftIn), + .SI(registers_6__ap[13]) + ); + SDFF_X1_LVT \registers_reg[3][13] ( + .CK(n_0_33), .D(registers[13]), .Q(registers_3__ap[13]), .QN(), .SE(dftIn), + .SI(registers_5__ap[13]) + ); + AOI22_X1_LVT i_1_0_959( + .A1(registers_5__ap[13]), .A2(n_1_0_1273), .B1(n_1_0_1257), .B2(registers_3__ap[13]), + .ZN(n_1_0_913) + ); + SDFF_X1_LVT \registers_reg[16][13] ( + .CK(n_0_46), .D(registers[13]), .Q(registers_16__ap[13]), .QN(), .SE(dftIn), + .SI(registers_10__ap[13]) + ); + SDFF_X1_LVT \registers_reg[31][13] ( + .CK(n_0_61), .D(registers[13]), .Q(registers_31__ap[13]), .QN(), .SE(dftIn), + .SI(registers_3__ap[13]) + ); + AOI22_X1_LVT i_1_0_958( + .A1(registers_16__ap[13]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[13]), + .ZN(n_1_0_912) + ); + SDFF_X1_LVT \registers_reg[15][13] ( + .CK(n_0_45), .D(registers[13]), .Q(registers_15__ap[13]), .QN(), .SE(dftIn), + .SI(registers_16__ap[13]) + ); + SDFF_X1_LVT \registers_reg[23][13] ( + .CK(n_0_53), .D(registers[13]), .Q(registers_23__ap[13]), .QN(), .SE(dftIn), + .SI(registers_1__ap[13]) + ); + AOI22_X1_LVT i_1_0_957( + .A1(registers_15__ap[13]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[13]), + .ZN(n_1_0_911) + ); + NAND4_X1_LVT i_1_0_956( + .A1(n_1_0_914), .A2(n_1_0_913), .A3(n_1_0_912), .A4(n_1_0_911), .ZN(n_1_0_910) + ); + SDFF_X1_LVT \registers_reg[18][13] ( + .CK(n_0_48), .D(registers[13]), .Q(registers_18__ap[13]), .QN(), .SE(dftIn), + .SI(registers_23__ap[13]) + ); + SDFF_X1_LVT \registers_reg[30][13] ( + .CK(n_0_60), .D(registers[13]), .Q(registers_30__ap[13]), .QN(), .SE(dftIn), + .SI(registers_29__ap[13]) + ); + AOI22_X1_LVT i_1_0_955( + .A1(registers_18__ap[13]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[13]), + .ZN(n_1_0_909) + ); + SDFF_X1_LVT \registers_reg[24][13] ( + .CK(n_0_54), .D(registers[13]), .Q(registers_24__ap[13]), .QN(), .SE(dftIn), + .SI(registers_30__ap[13]) + ); + SDFF_X1_LVT \registers_reg[12][13] ( + .CK(n_0_42), .D(registers[13]), .Q(registers_12__ap[13]), .QN(), .SE(dftIn), + .SI(registers_15__ap[13]) + ); + AOI22_X1_LVT i_1_0_954( + .A1(registers_24__ap[13]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[13]), + .ZN(n_1_0_908) + ); + SDFF_X1_LVT \registers_reg[22][13] ( + .CK(n_0_52), .D(registers[13]), .Q(registers_22__ap[13]), .QN(), .SE(dftIn), + .SI(registers_18__ap[13]) + ); + SDFF_X1_LVT \registers_reg[21][13] ( + .CK(n_0_51), .D(registers[13]), .Q(registers_21__ap[13]), .QN(), .SE(dftIn), + .SI(registers_22__ap[13]) + ); + AOI22_X1_LVT i_1_0_953( + .A1(registers_22__ap[13]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[13]), + .ZN(n_1_0_907) + ); + SDFF_X1_LVT \registers_reg[20][13] ( + .CK(n_0_50), .D(registers[13]), .Q(registers_20__ap[13]), .QN(), .SE(dftIn), + .SI(registers_21__ap[13]) + ); + SDFF_X1_LVT \registers_reg[17][13] ( + .CK(n_0_47), .D(registers[13]), .Q(registers_17__ap[13]), .QN(), .SE(dftIn), + .SI(registers_20__ap[13]) + ); + AOI22_X1_LVT i_1_0_952( + .A1(registers_20__ap[13]), .A2(n_1_0_1281), .B1(n_1_0_1271), .B2(registers_17__ap[13]), + .ZN(n_1_0_906) + ); + NAND4_X1_LVT i_1_0_951( + .A1(n_1_0_909), .A2(n_1_0_908), .A3(n_1_0_907), .A4(n_1_0_906), .ZN(n_1_0_905) + ); + SDFF_X1_LVT \registers_reg[13][13] ( + .CK(n_0_43), .D(registers[13]), .Q(registers_13__ap[13]), .QN(), .SE(dftIn), + .SI(registers_12__ap[13]) + ); + SDFF_X1_LVT \registers_reg[25][13] ( + .CK(n_0_55), .D(registers[13]), .Q(registers_25__ap[13]), .QN(), .SE(dftIn), + .SI(registers_24__ap[13]) + ); + AOI22_X1_LVT i_1_0_950( + .A1(registers_13__ap[13]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[13]), + .ZN(n_1_0_904) + ); + SDFF_X1_LVT \registers_reg[19][13] ( + .CK(n_0_49), .D(registers[13]), .Q(registers_19__ap[13]), .QN(), .SE(dftIn), + .SI(registers_17__ap[13]) + ); + SDFF_X1_LVT \registers_reg[2][13] ( + .CK(n_0_32), .D(registers[13]), .Q(registers_2__ap[13]), .QN(), .SE(dftIn), + .SI(registers_25__ap[13]) + ); + AOI22_X1_LVT i_1_0_949( + .A1(registers_19__ap[13]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[13]), + .ZN(n_1_0_903) + ); + SDFF_X1_LVT \registers_reg[7][13] ( + .CK(n_0_37), .D(registers[13]), .Q(registers_7__ap[13]), .QN(), .SE(dftIn), + .SI(registers_31__ap[13]) + ); + SDFF_X1_LVT \registers_reg[14][13] ( + .CK(n_0_44), .D(registers[13]), .Q(registers_14__ap[13]), .QN(), .SE(dftIn), + .SI(registers_13__ap[13]) + ); + AOI22_X1_LVT i_1_0_948( + .A1(registers_7__ap[13]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[13]), + .ZN(n_1_0_902) + ); + SDFF_X1_LVT \registers_reg[27][13] ( + .CK(n_0_57), .D(registers[13]), .Q(registers_27__ap[13]), .QN(), .SE(dftIn), + .SI(registers_2__ap[13]) + ); + SDFF_X1_LVT \registers_reg[11][13] ( + .CK(n_0_41), .D(registers[13]), .Q(registers_11__ap[13]), .QN(), .SE(dftIn), + .SI(registers_14__ap[13]) + ); + AOI22_X1_LVT i_1_0_947( + .A1(registers_27__ap[13]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[13]), + .ZN(n_1_0_901) + ); + NAND4_X1_LVT i_1_0_946( + .A1(n_1_0_904), .A2(n_1_0_903), .A3(n_1_0_902), .A4(n_1_0_901), .ZN(n_1_0_900) + ); + NOR3_X1_LVT i_1_0_945( + .A1(n_1_0_910), .A2(n_1_0_905), .A3(n_1_0_900), .ZN(n_1_0_899) + ); + NAND4_X1_LVT i_1_0_944( + .A1(n_1_0_917), .A2(n_1_0_916), .A3(n_1_0_915), .A4(n_1_0_899), .ZN(RRs1[13]) + ); + AND2_X1_LVT i_0_0_12( + .A1(n_0_0_16), .A2(WRd[12]), .ZN(registers[12]) + ); + SDFF_X1_LVT \registers_reg[28][12] ( + .CK(n_0_58), .D(registers[12]), .Q(registers_28__ap[12]), .QN(), .SE(dftIn), + .SI(registers_27__ap[13]) + ); + SDFF_X1_LVT \registers_reg[17][12] ( + .CK(n_0_47), .D(registers[12]), .Q(registers_17__ap[12]), .QN(), .SE(dftIn), + .SI(registers_19__ap[13]) + ); + AOI22_X1_LVT i_1_0_943( + .A1(registers_28__ap[12]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[12]), + .ZN(n_1_0_898) + ); + SDFF_X1_LVT \registers_reg[10][12] ( + .CK(n_0_40), .D(registers[12]), .Q(registers_10__ap[12]), .QN(), .SE(dftIn), + .SI(registers_11__ap[13]) + ); + SDFF_X1_LVT \registers_reg[26][12] ( + .CK(n_0_56), .D(registers[12]), .Q(registers_26__ap[12]), .QN(), .SE(dftIn), + .SI(registers_28__ap[12]) + ); + SDFF_X1_LVT \registers_reg[8][12] ( + .CK(n_0_38), .D(registers[12]), .Q(registers_8__ap[12]), .QN(), .SE(dftIn), + .SI(registers_7__ap[13]) + ); + AOI222_X1_LVT i_1_0_942( + .A1(registers_10__ap[12]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[12]), + .C1(registers_8__ap[12]), .C2(n_1_0_1282), .ZN(n_1_0_897) + ); + SDFF_X1_LVT \registers_reg[9][12] ( + .CK(n_0_39), .D(registers[12]), .Q(registers_9__ap[12]), .QN(), .SE(dftIn), + .SI(registers_8__ap[12]) + ); + SDFF_X1_LVT \registers_reg[29][12] ( + .CK(n_0_59), .D(registers[12]), .Q(registers_29__ap[12]), .QN(), .SE(dftIn), + .SI(registers_26__ap[12]) + ); + AOI22_X1_LVT i_1_0_941( + .A1(registers_9__ap[12]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[12]), + .ZN(n_1_0_896) + ); + SDFF_X1_LVT \registers_reg[6][12] ( + .CK(n_0_36), .D(registers[12]), .Q(registers_6__ap[12]), .QN(), .SE(dftIn), + .SI(registers_9__ap[12]) + ); + SDFF_X1_LVT \registers_reg[1][12] ( + .CK(n_0_0), .D(registers[12]), .Q(registers_1__ap[12]), .QN(), .SE(dftIn), + .SI(registers_17__ap[12]) + ); + AOI22_X1_LVT i_1_0_940( + .A1(registers_6__ap[12]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[12]), + .ZN(n_1_0_895) + ); + SDFF_X1_LVT \registers_reg[16][12] ( + .CK(n_0_46), .D(registers[12]), .Q(registers_16__ap[12]), .QN(), .SE(dftIn), + .SI(registers_10__ap[12]) + ); + SDFF_X1_LVT \registers_reg[3][12] ( + .CK(n_0_33), .D(registers[12]), .Q(registers_3__ap[12]), .QN(), .SE(dftIn), + .SI(registers_6__ap[12]) + ); + AOI22_X1_LVT i_1_0_939( + .A1(registers_16__ap[12]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[12]), + .ZN(n_1_0_894) + ); + SDFF_X1_LVT \registers_reg[5][12] ( + .CK(n_0_35), .D(registers[12]), .Q(registers_5__ap[12]), .QN(), .SE(dftIn), + .SI(registers_3__ap[12]) + ); + SDFF_X1_LVT \registers_reg[31][12] ( + .CK(n_0_61), .D(registers[12]), .Q(registers_31__ap[12]), .QN(), .SE(dftIn), + .SI(registers_5__ap[12]) + ); + AOI22_X1_LVT i_1_0_938( + .A1(registers_5__ap[12]), .A2(n_1_0_1273), .B1(n_1_0_1266), .B2(registers_31__ap[12]), + .ZN(n_1_0_893) + ); + SDFF_X1_LVT \registers_reg[15][12] ( + .CK(n_0_45), .D(registers[12]), .Q(registers_15__ap[12]), .QN(), .SE(dftIn), + .SI(registers_16__ap[12]) + ); + SDFF_X1_LVT \registers_reg[23][12] ( + .CK(n_0_53), .D(registers[12]), .Q(registers_23__ap[12]), .QN(), .SE(dftIn), + .SI(registers_1__ap[12]) + ); + AOI22_X1_LVT i_1_0_937( + .A1(registers_15__ap[12]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[12]), + .ZN(n_1_0_892) + ); + NAND4_X1_LVT i_1_0_936( + .A1(n_1_0_895), .A2(n_1_0_894), .A3(n_1_0_893), .A4(n_1_0_892), .ZN(n_1_0_891) + ); + SDFF_X1_LVT \registers_reg[18][12] ( + .CK(n_0_48), .D(registers[12]), .Q(registers_18__ap[12]), .QN(), .SE(dftIn), + .SI(registers_23__ap[12]) + ); + SDFF_X1_LVT \registers_reg[30][12] ( + .CK(n_0_60), .D(registers[12]), .Q(registers_30__ap[12]), .QN(), .SE(dftIn), + .SI(registers_29__ap[12]) + ); + AOI22_X1_LVT i_1_0_935( + .A1(registers_18__ap[12]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[12]), + .ZN(n_1_0_890) + ); + SDFF_X1_LVT \registers_reg[20][12] ( + .CK(n_0_50), .D(registers[12]), .Q(registers_20__ap[12]), .QN(), .SE(dftIn), + .SI(registers_18__ap[12]) + ); + SDFF_X1_LVT \registers_reg[4][12] ( + .CK(n_0_34), .D(registers[12]), .Q(registers_4__ap[12]), .QN(), .SE(dftIn), + .SI(registers_31__ap[12]) + ); + AOI22_X1_LVT i_1_0_934( + .A1(registers_20__ap[12]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[12]), + .ZN(n_1_0_889) + ); + SDFF_X1_LVT \registers_reg[22][12] ( + .CK(n_0_52), .D(registers[12]), .Q(registers_22__ap[12]), .QN(), .SE(dftIn), + .SI(registers_20__ap[12]) + ); + SDFF_X1_LVT \registers_reg[21][12] ( + .CK(n_0_51), .D(registers[12]), .Q(registers_21__ap[12]), .QN(), .SE(dftIn), + .SI(registers_22__ap[12]) + ); + AOI22_X1_LVT i_1_0_933( + .A1(registers_22__ap[12]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[12]), + .ZN(n_1_0_888) + ); + SDFF_X1_LVT \registers_reg[24][12] ( + .CK(n_0_54), .D(registers[12]), .Q(registers_24__ap[12]), .QN(), .SE(dftIn), + .SI(registers_30__ap[12]) + ); + SDFF_X1_LVT \registers_reg[12][12] ( + .CK(n_0_42), .D(registers[12]), .Q(registers_12__ap[12]), .QN(), .SE(dftIn), + .SI(registers_15__ap[12]) + ); + AOI22_X1_LVT i_1_0_932( + .A1(registers_24__ap[12]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[12]), + .ZN(n_1_0_887) + ); + NAND4_X1_LVT i_1_0_931( + .A1(n_1_0_890), .A2(n_1_0_889), .A3(n_1_0_888), .A4(n_1_0_887), .ZN(n_1_0_886) + ); + SDFF_X1_LVT \registers_reg[13][12] ( + .CK(n_0_43), .D(registers[12]), .Q(registers_13__ap[12]), .QN(), .SE(dftIn), + .SI(registers_12__ap[12]) + ); + SDFF_X1_LVT \registers_reg[25][12] ( + .CK(n_0_55), .D(registers[12]), .Q(registers_25__ap[12]), .QN(), .SE(dftIn), + .SI(registers_24__ap[12]) + ); + AOI22_X1_LVT i_1_0_930( + .A1(registers_13__ap[12]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[12]), + .ZN(n_1_0_885) + ); + SDFF_X1_LVT \registers_reg[19][12] ( + .CK(n_0_49), .D(registers[12]), .Q(registers_19__ap[12]), .QN(), .SE(dftIn), + .SI(registers_21__ap[12]) + ); + SDFF_X1_LVT \registers_reg[2][12] ( + .CK(n_0_32), .D(registers[12]), .Q(registers_2__ap[12]), .QN(), .SE(dftIn), + .SI(registers_25__ap[12]) + ); + AOI22_X1_LVT i_1_0_929( + .A1(registers_19__ap[12]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[12]), + .ZN(n_1_0_884) + ); + SDFF_X1_LVT \registers_reg[7][12] ( + .CK(n_0_37), .D(registers[12]), .Q(registers_7__ap[12]), .QN(), .SE(dftIn), + .SI(registers_4__ap[12]) + ); + SDFF_X1_LVT \registers_reg[14][12] ( + .CK(n_0_44), .D(registers[12]), .Q(registers_14__ap[12]), .QN(), .SE(dftIn), + .SI(registers_13__ap[12]) + ); + AOI22_X1_LVT i_1_0_928( + .A1(registers_7__ap[12]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[12]), + .ZN(n_1_0_883) + ); + SDFF_X1_LVT \registers_reg[27][12] ( + .CK(n_0_57), .D(registers[12]), .Q(registers_27__ap[12]), .QN(), .SE(dftIn), + .SI(registers_2__ap[12]) + ); + SDFF_X1_LVT \registers_reg[11][12] ( + .CK(n_0_41), .D(registers[12]), .Q(registers_11__ap[12]), .QN(), .SE(dftIn), + .SI(registers_14__ap[12]) + ); + AOI22_X1_LVT i_1_0_927( + .A1(registers_27__ap[12]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[12]), + .ZN(n_1_0_882) + ); + NAND4_X1_LVT i_1_0_926( + .A1(n_1_0_885), .A2(n_1_0_884), .A3(n_1_0_883), .A4(n_1_0_882), .ZN(n_1_0_881) + ); + NOR3_X1_LVT i_1_0_925( + .A1(n_1_0_891), .A2(n_1_0_886), .A3(n_1_0_881), .ZN(n_1_0_880) + ); + NAND4_X1_LVT i_1_0_924( + .A1(n_1_0_898), .A2(n_1_0_897), .A3(n_1_0_896), .A4(n_1_0_880), .ZN(RRs1[12]) + ); + AND2_X1_LVT i_0_0_11( + .A1(n_0_0_16), .A2(WRd[11]), .ZN(registers[11]) + ); + SDFF_X1_LVT \registers_reg[28][11] ( + .CK(n_0_58), .D(registers[11]), .Q(registers_28__ap[11]), .QN(), .SE(dftIn), + .SI(registers_27__ap[12]) + ); + SDFF_X1_LVT \registers_reg[17][11] ( + .CK(n_0_47), .D(registers[11]), .Q(registers_17__ap[11]), .QN(), .SE(dftIn), + .SI(registers_19__ap[12]) + ); + AOI22_X1_LVT i_1_0_923( + .A1(registers_28__ap[11]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[11]), + .ZN(n_1_0_879) + ); + SDFF_X1_LVT \registers_reg[10][11] ( + .CK(n_0_40), .D(registers[11]), .Q(registers_10__ap[11]), .QN(), .SE(dftIn), + .SI(registers_11__ap[12]) + ); + SDFF_X1_LVT \registers_reg[26][11] ( + .CK(n_0_56), .D(registers[11]), .Q(registers_26__ap[11]), .QN(), .SE(dftIn), + .SI(registers_28__ap[11]) + ); + SDFF_X1_LVT \registers_reg[8][11] ( + .CK(n_0_38), .D(registers[11]), .Q(registers_8__ap[11]), .QN(), .SE(dftIn), + .SI(registers_7__ap[12]) + ); + AOI222_X1_LVT i_1_0_922( + .A1(registers_10__ap[11]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[11]), + .C1(registers_8__ap[11]), .C2(n_1_0_1282), .ZN(n_1_0_878) + ); + SDFF_X1_LVT \registers_reg[9][11] ( + .CK(n_0_39), .D(registers[11]), .Q(registers_9__ap[11]), .QN(), .SE(dftIn), + .SI(registers_8__ap[11]) + ); + SDFF_X1_LVT \registers_reg[29][11] ( + .CK(n_0_59), .D(registers[11]), .Q(registers_29__ap[11]), .QN(), .SE(dftIn), + .SI(registers_26__ap[11]) + ); + AOI22_X1_LVT i_1_0_921( + .A1(registers_9__ap[11]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[11]), + .ZN(n_1_0_877) + ); + SDFF_X1_LVT \registers_reg[6][11] ( + .CK(n_0_36), .D(registers[11]), .Q(registers_6__ap[11]), .QN(), .SE(dftIn), + .SI(registers_9__ap[11]) + ); + SDFF_X1_LVT \registers_reg[1][11] ( + .CK(n_0_0), .D(registers[11]), .Q(registers_1__ap[11]), .QN(), .SE(dftIn), + .SI(registers_17__ap[11]) + ); + AOI22_X1_LVT i_1_0_920( + .A1(registers_6__ap[11]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[11]), + .ZN(n_1_0_876) + ); + SDFF_X1_LVT \registers_reg[5][11] ( + .CK(n_0_35), .D(registers[11]), .Q(registers_5__ap[11]), .QN(), .SE(dftIn), + .SI(registers_6__ap[11]) + ); + SDFF_X1_LVT \registers_reg[3][11] ( + .CK(n_0_33), .D(registers[11]), .Q(registers_3__ap[11]), .QN(), .SE(dftIn), + .SI(registers_5__ap[11]) + ); + AOI22_X1_LVT i_1_0_919( + .A1(registers_5__ap[11]), .A2(n_1_0_1273), .B1(n_1_0_1257), .B2(registers_3__ap[11]), + .ZN(n_1_0_875) + ); + SDFF_X1_LVT \registers_reg[16][11] ( + .CK(n_0_46), .D(registers[11]), .Q(registers_16__ap[11]), .QN(), .SE(dftIn), + .SI(registers_10__ap[11]) + ); + SDFF_X1_LVT \registers_reg[31][11] ( + .CK(n_0_61), .D(registers[11]), .Q(registers_31__ap[11]), .QN(), .SE(dftIn), + .SI(registers_3__ap[11]) + ); + AOI22_X1_LVT i_1_0_918( + .A1(registers_16__ap[11]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[11]), + .ZN(n_1_0_874) + ); + SDFF_X1_LVT \registers_reg[15][11] ( + .CK(n_0_45), .D(registers[11]), .Q(registers_15__ap[11]), .QN(), .SE(dftIn), + .SI(registers_16__ap[11]) + ); + SDFF_X1_LVT \registers_reg[23][11] ( + .CK(n_0_53), .D(registers[11]), .Q(registers_23__ap[11]), .QN(), .SE(dftIn), + .SI(registers_1__ap[11]) + ); + AOI22_X1_LVT i_1_0_917( + .A1(registers_15__ap[11]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[11]), + .ZN(n_1_0_873) + ); + NAND4_X1_LVT i_1_0_916( + .A1(n_1_0_876), .A2(n_1_0_875), .A3(n_1_0_874), .A4(n_1_0_873), .ZN(n_1_0_872) + ); + SDFF_X1_LVT \registers_reg[18][11] ( + .CK(n_0_48), .D(registers[11]), .Q(registers_18__ap[11]), .QN(), .SE(dftIn), + .SI(registers_23__ap[11]) + ); + SDFF_X1_LVT \registers_reg[30][11] ( + .CK(n_0_60), .D(registers[11]), .Q(registers_30__ap[11]), .QN(), .SE(dftIn), + .SI(registers_29__ap[11]) + ); + AOI22_X1_LVT i_1_0_915( + .A1(registers_18__ap[11]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[11]), + .ZN(n_1_0_871) + ); + SDFF_X1_LVT \registers_reg[20][11] ( + .CK(n_0_50), .D(registers[11]), .Q(registers_20__ap[11]), .QN(), .SE(dftIn), + .SI(registers_18__ap[11]) + ); + SDFF_X1_LVT \registers_reg[4][11] ( + .CK(n_0_34), .D(registers[11]), .Q(registers_4__ap[11]), .QN(), .SE(dftIn), + .SI(registers_31__ap[11]) + ); + AOI22_X1_LVT i_1_0_914( + .A1(registers_20__ap[11]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[11]), + .ZN(n_1_0_870) + ); + SDFF_X1_LVT \registers_reg[22][11] ( + .CK(n_0_52), .D(registers[11]), .Q(registers_22__ap[11]), .QN(), .SE(dftIn), + .SI(registers_20__ap[11]) + ); + SDFF_X1_LVT \registers_reg[21][11] ( + .CK(n_0_51), .D(registers[11]), .Q(registers_21__ap[11]), .QN(), .SE(dftIn), + .SI(registers_22__ap[11]) + ); + AOI22_X1_LVT i_1_0_913( + .A1(registers_22__ap[11]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[11]), + .ZN(n_1_0_869) + ); + SDFF_X1_LVT \registers_reg[24][11] ( + .CK(n_0_54), .D(registers[11]), .Q(registers_24__ap[11]), .QN(), .SE(dftIn), + .SI(registers_30__ap[11]) + ); + SDFF_X1_LVT \registers_reg[12][11] ( + .CK(n_0_42), .D(registers[11]), .Q(registers_12__ap[11]), .QN(), .SE(dftIn), + .SI(registers_15__ap[11]) + ); + AOI22_X1_LVT i_1_0_912( + .A1(registers_24__ap[11]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[11]), + .ZN(n_1_0_868) + ); + NAND4_X1_LVT i_1_0_911( + .A1(n_1_0_871), .A2(n_1_0_870), .A3(n_1_0_869), .A4(n_1_0_868), .ZN(n_1_0_867) + ); + SDFF_X1_LVT \registers_reg[13][11] ( + .CK(n_0_43), .D(registers[11]), .Q(registers_13__ap[11]), .QN(), .SE(dftIn), + .SI(registers_12__ap[11]) + ); + SDFF_X1_LVT \registers_reg[25][11] ( + .CK(n_0_55), .D(registers[11]), .Q(registers_25__ap[11]), .QN(), .SE(dftIn), + .SI(registers_24__ap[11]) + ); + AOI22_X1_LVT i_1_0_910( + .A1(registers_13__ap[11]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[11]), + .ZN(n_1_0_866) + ); + SDFF_X1_LVT \registers_reg[19][11] ( + .CK(n_0_49), .D(registers[11]), .Q(registers_19__ap[11]), .QN(), .SE(dftIn), + .SI(registers_21__ap[11]) + ); + SDFF_X1_LVT \registers_reg[2][11] ( + .CK(n_0_32), .D(registers[11]), .Q(registers_2__ap[11]), .QN(), .SE(dftIn), + .SI(registers_25__ap[11]) + ); + AOI22_X1_LVT i_1_0_909( + .A1(registers_19__ap[11]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[11]), + .ZN(n_1_0_865) + ); + SDFF_X1_LVT \registers_reg[7][11] ( + .CK(n_0_37), .D(registers[11]), .Q(registers_7__ap[11]), .QN(), .SE(dftIn), + .SI(registers_4__ap[11]) + ); + SDFF_X1_LVT \registers_reg[14][11] ( + .CK(n_0_44), .D(registers[11]), .Q(registers_14__ap[11]), .QN(), .SE(dftIn), + .SI(registers_13__ap[11]) + ); + AOI22_X1_LVT i_1_0_908( + .A1(registers_7__ap[11]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[11]), + .ZN(n_1_0_864) + ); + SDFF_X1_LVT \registers_reg[27][11] ( + .CK(n_0_57), .D(registers[11]), .Q(registers_27__ap[11]), .QN(), .SE(dftIn), + .SI(registers_2__ap[11]) + ); + SDFF_X1_LVT \registers_reg[11][11] ( + .CK(n_0_41), .D(registers[11]), .Q(registers_11__ap[11]), .QN(), .SE(dftIn), + .SI(registers_14__ap[11]) + ); + AOI22_X1_LVT i_1_0_907( + .A1(registers_27__ap[11]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[11]), + .ZN(n_1_0_863) + ); + NAND4_X1_LVT i_1_0_906( + .A1(n_1_0_866), .A2(n_1_0_865), .A3(n_1_0_864), .A4(n_1_0_863), .ZN(n_1_0_862) + ); + NOR3_X1_LVT i_1_0_905( + .A1(n_1_0_872), .A2(n_1_0_867), .A3(n_1_0_862), .ZN(n_1_0_861) + ); + NAND4_X1_LVT i_1_0_904( + .A1(n_1_0_879), .A2(n_1_0_878), .A3(n_1_0_877), .A4(n_1_0_861), .ZN(RRs1[11]) + ); + AND2_X1_LVT i_0_0_10( + .A1(n_0_0_16), .A2(WRd[10]), .ZN(registers[10]) + ); + SDFF_X1_LVT \registers_reg[28][10] ( + .CK(n_0_58), .D(registers[10]), .Q(registers_28__ap[10]), .QN(), .SE(dftIn), + .SI(registers_27__ap[11]) + ); + SDFF_X1_LVT \registers_reg[8][10] ( + .CK(n_0_38), .D(registers[10]), .Q(registers_8__ap[10]), .QN(), .SE(dftIn), + .SI(registers_7__ap[11]) + ); + AOI22_X1_LVT i_1_0_902( + .A1(registers_28__ap[10]), .A2(n_1_0_1283), .B1(n_1_0_1282), .B2(registers_8__ap[10]), + .ZN(n_1_0_859) + ); + SDFF_X1_LVT \registers_reg[31][10] ( + .CK(n_0_61), .D(registers[10]), .Q(registers_31__ap[10]), .QN(), .SE(dftIn), + .SI(registers_8__ap[10]) + ); + SDFF_X1_LVT \registers_reg[7][10] ( + .CK(n_0_37), .D(registers[10]), .Q(registers_7__ap[10]), .QN(), .SE(dftIn), + .SI(registers_31__ap[10]) + ); + AOI22_X1_LVT i_1_0_903( + .A1(registers_31__ap[10]), .A2(n_1_0_1266), .B1(n_1_0_1263), .B2(registers_7__ap[10]), + .ZN(n_1_0_860) + ); + SDFF_X1_LVT \registers_reg[24][10] ( + .CK(n_0_54), .D(registers[10]), .Q(registers_24__ap[10]), .QN(), .SE(dftIn), + .SI(registers_28__ap[10]) + ); + SDFF_X1_LVT \registers_reg[20][10] ( + .CK(n_0_50), .D(registers[10]), .Q(registers_20__ap[10]), .QN(), .SE(dftIn), + .SI(registers_19__ap[11]) + ); + AOI22_X1_LVT i_1_0_901( + .A1(registers_24__ap[10]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[10]), + .ZN(n_1_0_858) + ); + SDFF_X1_LVT \registers_reg[4][10] ( + .CK(n_0_34), .D(registers[10]), .Q(registers_4__ap[10]), .QN(), .SE(dftIn), + .SI(registers_7__ap[10]) + ); + SDFF_X1_LVT \registers_reg[23][10] ( + .CK(n_0_53), .D(registers[10]), .Q(registers_23__ap[10]), .QN(), .SE(dftIn), + .SI(registers_20__ap[10]) + ); + AOI22_X1_LVT i_1_0_900( + .A1(registers_4__ap[10]), .A2(n_1_0_1278), .B1(n_1_0_1264), .B2(registers_23__ap[10]), + .ZN(n_1_0_857) + ); + NAND3_X1_LVT i_1_0_899( + .A1(n_1_0_860), .A2(n_1_0_858), .A3(n_1_0_857), .ZN(n_1_0_856) + ); + SDFF_X1_LVT \registers_reg[27][10] ( + .CK(n_0_57), .D(registers[10]), .Q(registers_27__ap[10]), .QN(), .SE(dftIn), + .SI(registers_24__ap[10]) + ); + SDFF_X1_LVT \registers_reg[29][10] ( + .CK(n_0_59), .D(registers[10]), .Q(registers_29__ap[10]), .QN(), .SE(dftIn), + .SI(registers_27__ap[10]) + ); + AOI221_X1_LVT i_1_0_898( + .A(n_1_0_856), .B1(n_1_0_1279), .B2(registers_27__ap[10]), .C1(registers_29__ap[10]), + .C2(n_1_0_1276), .ZN(n_1_0_855) + ); + SDFF_X1_LVT \registers_reg[10][10] ( + .CK(n_0_40), .D(registers[10]), .Q(registers_10__ap[10]), .QN(), .SE(dftIn), + .SI(registers_11__ap[11]) + ); + SDFF_X1_LVT \registers_reg[30][10] ( + .CK(n_0_60), .D(registers[10]), .Q(registers_30__ap[10]), .QN(), .SE(dftIn), + .SI(registers_29__ap[10]) + ); + SDFF_X1_LVT \registers_reg[25][10] ( + .CK(n_0_55), .D(registers[10]), .Q(registers_25__ap[10]), .QN(), .SE(dftIn), + .SI(registers_30__ap[10]) + ); + AOI222_X1_LVT i_1_0_897( + .A1(registers_10__ap[10]), .A2(n_1_0_1287), .B1(n_1_0_1272), .B2(registers_30__ap[10]), + .C1(n_1_0_1269), .C2(registers_25__ap[10]), .ZN(n_1_0_854) + ); + NAND3_X1_LVT i_1_0_896( + .A1(n_1_0_859), .A2(n_1_0_855), .A3(n_1_0_854), .ZN(n_1_0_853) + ); + SDFF_X1_LVT \registers_reg[21][10] ( + .CK(n_0_51), .D(registers[10]), .Q(registers_21__ap[10]), .QN(), .SE(dftIn), + .SI(registers_23__ap[10]) + ); + SDFF_X1_LVT \registers_reg[13][10] ( + .CK(n_0_43), .D(registers[10]), .Q(registers_13__ap[10]), .QN(), .SE(dftIn), + .SI(registers_10__ap[10]) + ); + AOI221_X1_LVT i_1_0_895( + .A(n_1_0_853), .B1(n_1_0_1259), .B2(registers_21__ap[10]), .C1(registers_13__ap[10]), + .C2(n_1_0_1277), .ZN(n_1_0_852) + ); + SDFF_X1_LVT \registers_reg[18][10] ( + .CK(n_0_48), .D(registers[10]), .Q(registers_18__ap[10]), .QN(), .SE(dftIn), + .SI(registers_21__ap[10]) + ); + SDFF_X1_LVT \registers_reg[26][10] ( + .CK(n_0_56), .D(registers[10]), .Q(registers_26__ap[10]), .QN(), .SE(dftIn), + .SI(registers_25__ap[10]) + ); + AOI22_X1_LVT i_1_0_894( + .A1(registers_18__ap[10]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[10]), + .ZN(n_1_0_851) + ); + SDFF_X1_LVT \registers_reg[17][10] ( + .CK(n_0_47), .D(registers[10]), .Q(registers_17__ap[10]), .QN(), .SE(dftIn), + .SI(registers_18__ap[10]) + ); + SDFF_X1_LVT \registers_reg[12][10] ( + .CK(n_0_42), .D(registers[10]), .Q(registers_12__ap[10]), .QN(), .SE(dftIn), + .SI(registers_13__ap[10]) + ); + AOI22_X1_LVT i_1_0_893( + .A1(registers_17__ap[10]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[10]), + .ZN(n_1_0_850) + ); + SDFF_X1_LVT \registers_reg[15][10] ( + .CK(n_0_45), .D(registers[10]), .Q(registers_15__ap[10]), .QN(), .SE(dftIn), + .SI(registers_12__ap[10]) + ); + SDFF_X1_LVT \registers_reg[5][10] ( + .CK(n_0_35), .D(registers[10]), .Q(registers_5__ap[10]), .QN(), .SE(dftIn), + .SI(registers_4__ap[10]) + ); + AOI22_X1_LVT i_1_0_892( + .A1(registers_15__ap[10]), .A2(n_1_0_1286), .B1(n_1_0_1273), .B2(registers_5__ap[10]), + .ZN(n_1_0_849) + ); + NAND3_X1_LVT i_1_0_891( + .A1(n_1_0_851), .A2(n_1_0_850), .A3(n_1_0_849), .ZN(n_1_0_848) + ); + SDFF_X1_LVT \registers_reg[22][10] ( + .CK(n_0_52), .D(registers[10]), .Q(registers_22__ap[10]), .QN(), .SE(dftIn), + .SI(registers_17__ap[10]) + ); + SDFF_X1_LVT \registers_reg[16][10] ( + .CK(n_0_46), .D(registers[10]), .Q(registers_16__ap[10]), .QN(), .SE(dftIn), + .SI(registers_15__ap[10]) + ); + AOI221_X1_LVT i_1_0_890( + .A(n_1_0_848), .B1(n_1_0_1294), .B2(registers_22__ap[10]), .C1(registers_16__ap[10]), + .C2(n_1_0_1267), .ZN(n_1_0_847) + ); + SDFF_X1_LVT \registers_reg[9][10] ( + .CK(n_0_39), .D(registers[10]), .Q(registers_9__ap[10]), .QN(), .SE(dftIn), + .SI(registers_5__ap[10]) + ); + SDFF_X1_LVT \registers_reg[1][10] ( + .CK(n_0_0), .D(registers[10]), .Q(registers_1__ap[10]), .QN(), .SE(dftIn), + .SI(registers_22__ap[10]) + ); + AOI22_X1_LVT i_1_0_889( + .A1(registers_9__ap[10]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[10]), + .ZN(n_1_0_846) + ); + SDFF_X1_LVT \registers_reg[6][10] ( + .CK(n_0_36), .D(registers[10]), .Q(registers_6__ap[10]), .QN(), .SE(dftIn), + .SI(registers_9__ap[10]) + ); + SDFF_X1_LVT \registers_reg[14][10] ( + .CK(n_0_44), .D(registers[10]), .Q(registers_14__ap[10]), .QN(), .SE(dftIn), + .SI(registers_16__ap[10]) + ); + AOI22_X1_LVT i_1_0_888( + .A1(registers_6__ap[10]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[10]), + .ZN(n_1_0_845) + ); + SDFF_X1_LVT \registers_reg[19][10] ( + .CK(n_0_49), .D(registers[10]), .Q(registers_19__ap[10]), .QN(), .SE(dftIn), + .SI(registers_1__ap[10]) + ); + SDFF_X1_LVT \registers_reg[3][10] ( + .CK(n_0_33), .D(registers[10]), .Q(registers_3__ap[10]), .QN(), .SE(dftIn), + .SI(registers_6__ap[10]) + ); + AOI22_X1_LVT i_1_0_887( + .A1(registers_19__ap[10]), .A2(n_1_0_1295), .B1(n_1_0_1257), .B2(registers_3__ap[10]), + .ZN(n_1_0_844) + ); + NAND3_X1_LVT i_1_0_886( + .A1(n_1_0_846), .A2(n_1_0_845), .A3(n_1_0_844), .ZN(n_1_0_843) + ); + SDFF_X1_LVT \registers_reg[11][10] ( + .CK(n_0_41), .D(registers[10]), .Q(registers_11__ap[10]), .QN(), .SE(dftIn), + .SI(registers_14__ap[10]) + ); + SDFF_X1_LVT \registers_reg[2][10] ( + .CK(n_0_32), .D(registers[10]), .Q(registers_2__ap[10]), .QN(), .SE(dftIn), + .SI(registers_26__ap[10]) + ); + AOI221_X1_LVT i_1_0_885( + .A(n_1_0_843), .B1(n_1_0_1270), .B2(registers_11__ap[10]), .C1(registers_2__ap[10]), + .C2(n_1_0_1268), .ZN(n_1_0_842) + ); + NAND3_X1_LVT i_1_0_884( + .A1(n_1_0_852), .A2(n_1_0_847), .A3(n_1_0_842), .ZN(RRs1[10]) + ); + AND2_X1_LVT i_0_0_9( + .A1(n_0_0_16), .A2(WRd[9]), .ZN(registers[9]) + ); + SDFF_X1_LVT \registers_reg[13][9] ( + .CK(n_0_43), .D(registers[9]), .Q(registers_13__ap[9]), .QN(), .SE(dftIn), + .SI(registers_11__ap[10]) + ); + SDFF_X1_LVT \registers_reg[21][9] ( + .CK(n_0_51), .D(registers[9]), .Q(registers_21__ap[9]), .QN(), .SE(dftIn), + .SI(registers_19__ap[10]) + ); + AOI22_X1_LVT i_1_0_880( + .A1(registers_13__ap[9]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[9]), + .ZN(n_1_0_838) + ); + SDFF_X1_LVT \registers_reg[29][9] ( + .CK(n_0_59), .D(registers[9]), .Q(registers_29__ap[9]), .QN(), .SE(dftIn), + .SI(registers_2__ap[10]) + ); + SDFF_X1_LVT \registers_reg[23][9] ( + .CK(n_0_53), .D(registers[9]), .Q(registers_23__ap[9]), .QN(), .SE(dftIn), + .SI(registers_21__ap[9]) + ); + AOI22_X1_LVT i_1_0_883( + .A1(registers_29__ap[9]), .A2(n_1_0_1276), .B1(n_1_0_1264), .B2(registers_23__ap[9]), + .ZN(n_1_0_841) + ); + SDFF_X1_LVT \registers_reg[24][9] ( + .CK(n_0_54), .D(registers[9]), .Q(registers_24__ap[9]), .QN(), .SE(dftIn), + .SI(registers_29__ap[9]) + ); + SDFF_X1_LVT \registers_reg[20][9] ( + .CK(n_0_50), .D(registers[9]), .Q(registers_20__ap[9]), .QN(), .SE(dftIn), + .SI(registers_23__ap[9]) + ); + AOI22_X1_LVT i_1_0_879( + .A1(registers_24__ap[9]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[9]), + .ZN(n_1_0_837) + ); + SDFF_X1_LVT \registers_reg[7][9] ( + .CK(n_0_37), .D(registers[9]), .Q(registers_7__ap[9]), .QN(), .SE(dftIn), + .SI(registers_3__ap[10]) + ); + SDFF_X1_LVT \registers_reg[3][9] ( + .CK(n_0_33), .D(registers[9]), .Q(registers_3__ap[9]), .QN(), .SE(dftIn), + .SI(registers_7__ap[9]) + ); + AOI22_X1_LVT i_1_0_882( + .A1(registers_7__ap[9]), .A2(n_1_0_1263), .B1(n_1_0_1257), .B2(registers_3__ap[9]), + .ZN(n_1_0_840) + ); + INV_X1_LVT i_1_0_881( + .A(n_1_0_840), .ZN(n_1_0_839) + ); + SDFF_X1_LVT \registers_reg[31][9] ( + .CK(n_0_61), .D(registers[9]), .Q(registers_31__ap[9]), .QN(), .SE(dftIn), + .SI(registers_3__ap[9]) + ); + SDFF_X1_LVT \registers_reg[4][9] ( + .CK(n_0_34), .D(registers[9]), .Q(registers_4__ap[9]), .QN(), .SE(dftIn), + .SI(registers_31__ap[9]) + ); + AOI221_X1_LVT i_1_0_878( + .A(n_1_0_839), .B1(n_1_0_1266), .B2(registers_31__ap[9]), .C1(registers_4__ap[9]), + .C2(n_1_0_1278), .ZN(n_1_0_836) + ); + SDFF_X1_LVT \registers_reg[10][9] ( + .CK(n_0_40), .D(registers[9]), .Q(registers_10__ap[9]), .QN(), .SE(dftIn), + .SI(registers_13__ap[9]) + ); + SDFF_X1_LVT \registers_reg[26][9] ( + .CK(n_0_56), .D(registers[9]), .Q(registers_26__ap[9]), .QN(), .SE(dftIn), + .SI(registers_24__ap[9]) + ); + SDFF_X1_LVT \registers_reg[25][9] ( + .CK(n_0_55), .D(registers[9]), .Q(registers_25__ap[9]), .QN(), .SE(dftIn), + .SI(registers_26__ap[9]) + ); + AOI222_X1_LVT i_1_0_877( + .A1(registers_10__ap[9]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[9]), + .C1(registers_25__ap[9]), .C2(n_1_0_1269), .ZN(n_1_0_835) + ); + NAND4_X1_LVT i_1_0_876( + .A1(n_1_0_841), .A2(n_1_0_837), .A3(n_1_0_836), .A4(n_1_0_835), .ZN(n_1_0_834) + ); + SDFF_X1_LVT \registers_reg[8][9] ( + .CK(n_0_38), .D(registers[9]), .Q(registers_8__ap[9]), .QN(), .SE(dftIn), + .SI(registers_4__ap[9]) + ); + SDFF_X1_LVT \registers_reg[28][9] ( + .CK(n_0_58), .D(registers[9]), .Q(registers_28__ap[9]), .QN(), .SE(dftIn), + .SI(registers_25__ap[9]) + ); + AOI221_X1_LVT i_1_0_875( + .A(n_1_0_834), .B1(n_1_0_1282), .B2(registers_8__ap[9]), .C1(registers_28__ap[9]), + .C2(n_1_0_1283), .ZN(n_1_0_833) + ); + SDFF_X1_LVT \registers_reg[18][9] ( + .CK(n_0_48), .D(registers[9]), .Q(registers_18__ap[9]), .QN(), .SE(dftIn), + .SI(registers_20__ap[9]) + ); + SDFF_X1_LVT \registers_reg[30][9] ( + .CK(n_0_60), .D(registers[9]), .Q(registers_30__ap[9]), .QN(), .SE(dftIn), + .SI(registers_28__ap[9]) + ); + AOI22_X1_LVT i_1_0_874( + .A1(registers_18__ap[9]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[9]), + .ZN(n_1_0_832) + ); + SDFF_X1_LVT \registers_reg[17][9] ( + .CK(n_0_47), .D(registers[9]), .Q(registers_17__ap[9]), .QN(), .SE(dftIn), + .SI(registers_18__ap[9]) + ); + SDFF_X1_LVT \registers_reg[12][9] ( + .CK(n_0_42), .D(registers[9]), .Q(registers_12__ap[9]), .QN(), .SE(dftIn), + .SI(registers_10__ap[9]) + ); + AOI22_X1_LVT i_1_0_873( + .A1(registers_17__ap[9]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[9]), + .ZN(n_1_0_831) + ); + SDFF_X1_LVT \registers_reg[15][9] ( + .CK(n_0_45), .D(registers[9]), .Q(registers_15__ap[9]), .QN(), .SE(dftIn), + .SI(registers_12__ap[9]) + ); + SDFF_X1_LVT \registers_reg[5][9] ( + .CK(n_0_35), .D(registers[9]), .Q(registers_5__ap[9]), .QN(), .SE(dftIn), + .SI(registers_8__ap[9]) + ); + AOI22_X1_LVT i_1_0_872( + .A1(registers_15__ap[9]), .A2(n_1_0_1286), .B1(n_1_0_1273), .B2(registers_5__ap[9]), + .ZN(n_1_0_830) + ); + NAND3_X1_LVT i_1_0_871( + .A1(n_1_0_832), .A2(n_1_0_831), .A3(n_1_0_830), .ZN(n_1_0_829) + ); + SDFF_X1_LVT \registers_reg[22][9] ( + .CK(n_0_52), .D(registers[9]), .Q(registers_22__ap[9]), .QN(), .SE(dftIn), + .SI(registers_17__ap[9]) + ); + SDFF_X1_LVT \registers_reg[16][9] ( + .CK(n_0_46), .D(registers[9]), .Q(registers_16__ap[9]), .QN(), .SE(dftIn), + .SI(registers_15__ap[9]) + ); + AOI221_X1_LVT i_1_0_870( + .A(n_1_0_829), .B1(n_1_0_1294), .B2(registers_22__ap[9]), .C1(registers_16__ap[9]), + .C2(n_1_0_1267), .ZN(n_1_0_828) + ); + SDFF_X1_LVT \registers_reg[9][9] ( + .CK(n_0_39), .D(registers[9]), .Q(registers_9__ap[9]), .QN(), .SE(dftIn), + .SI(registers_5__ap[9]) + ); + SDFF_X1_LVT \registers_reg[1][9] ( + .CK(n_0_0), .D(registers[9]), .Q(registers_1__ap[9]), .QN(), .SE(dftIn), + .SI(registers_22__ap[9]) + ); + AOI22_X1_LVT i_1_0_869( + .A1(registers_9__ap[9]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[9]), + .ZN(n_1_0_827) + ); + SDFF_X1_LVT \registers_reg[6][9] ( + .CK(n_0_36), .D(registers[9]), .Q(registers_6__ap[9]), .QN(), .SE(dftIn), + .SI(registers_9__ap[9]) + ); + SDFF_X1_LVT \registers_reg[14][9] ( + .CK(n_0_44), .D(registers[9]), .Q(registers_14__ap[9]), .QN(), .SE(dftIn), + .SI(registers_16__ap[9]) + ); + AOI22_X1_LVT i_1_0_868( + .A1(registers_6__ap[9]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[9]), + .ZN(n_1_0_826) + ); + SDFF_X1_LVT \registers_reg[19][9] ( + .CK(n_0_49), .D(registers[9]), .Q(registers_19__ap[9]), .QN(), .SE(dftIn), + .SI(registers_1__ap[9]) + ); + SDFF_X1_LVT \registers_reg[2][9] ( + .CK(n_0_32), .D(registers[9]), .Q(registers_2__ap[9]), .QN(), .SE(dftIn), + .SI(registers_30__ap[9]) + ); + AOI22_X1_LVT i_1_0_867( + .A1(registers_19__ap[9]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[9]), + .ZN(n_1_0_825) + ); + NAND3_X1_LVT i_1_0_866( + .A1(n_1_0_827), .A2(n_1_0_826), .A3(n_1_0_825), .ZN(n_1_0_824) + ); + SDFF_X1_LVT \registers_reg[11][9] ( + .CK(n_0_41), .D(registers[9]), .Q(registers_11__ap[9]), .QN(), .SE(dftIn), + .SI(registers_14__ap[9]) + ); + SDFF_X1_LVT \registers_reg[27][9] ( + .CK(n_0_57), .D(registers[9]), .Q(registers_27__ap[9]), .QN(), .SE(dftIn), + .SI(registers_2__ap[9]) + ); + AOI221_X1_LVT i_1_0_865( + .A(n_1_0_824), .B1(n_1_0_1270), .B2(registers_11__ap[9]), .C1(registers_27__ap[9]), + .C2(n_1_0_1279), .ZN(n_1_0_823) + ); + NAND4_X1_LVT i_1_0_864( + .A1(n_1_0_838), .A2(n_1_0_833), .A3(n_1_0_828), .A4(n_1_0_823), .ZN(RRs1[9]) + ); + AND2_X1_LVT i_0_0_8( + .A1(n_0_0_16), .A2(WRd[8]), .ZN(registers[8]) + ); + SDFF_X1_LVT \registers_reg[13][8] ( + .CK(n_0_43), .D(registers[8]), .Q(registers_13__ap[8]), .QN(), .SE(dftIn), + .SI(registers_11__ap[9]) + ); + SDFF_X1_LVT \registers_reg[21][8] ( + .CK(n_0_51), .D(registers[8]), .Q(registers_21__ap[8]), .QN(), .SE(dftIn), + .SI(registers_19__ap[9]) + ); + AOI22_X1_LVT i_1_0_860( + .A1(registers_13__ap[8]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[8]), + .ZN(n_1_0_819) + ); + SDFF_X1_LVT \registers_reg[29][8] ( + .CK(n_0_59), .D(registers[8]), .Q(registers_29__ap[8]), .QN(), .SE(dftIn), + .SI(registers_27__ap[9]) + ); + SDFF_X1_LVT \registers_reg[23][8] ( + .CK(n_0_53), .D(registers[8]), .Q(registers_23__ap[8]), .QN(), .SE(dftIn), + .SI(registers_21__ap[8]) + ); + AOI22_X1_LVT i_1_0_863( + .A1(registers_29__ap[8]), .A2(n_1_0_1276), .B1(n_1_0_1264), .B2(registers_23__ap[8]), + .ZN(n_1_0_822) + ); + SDFF_X1_LVT \registers_reg[24][8] ( + .CK(n_0_54), .D(registers[8]), .Q(registers_24__ap[8]), .QN(), .SE(dftIn), + .SI(registers_29__ap[8]) + ); + SDFF_X1_LVT \registers_reg[20][8] ( + .CK(n_0_50), .D(registers[8]), .Q(registers_20__ap[8]), .QN(), .SE(dftIn), + .SI(registers_23__ap[8]) + ); + AOI22_X1_LVT i_1_0_859( + .A1(registers_24__ap[8]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[8]), + .ZN(n_1_0_818) + ); + SDFF_X1_LVT \registers_reg[7][8] ( + .CK(n_0_37), .D(registers[8]), .Q(registers_7__ap[8]), .QN(), .SE(dftIn), + .SI(registers_6__ap[9]) + ); + SDFF_X1_LVT \registers_reg[3][8] ( + .CK(n_0_33), .D(registers[8]), .Q(registers_3__ap[8]), .QN(), .SE(dftIn), + .SI(registers_7__ap[8]) + ); + AOI22_X1_LVT i_1_0_862( + .A1(registers_7__ap[8]), .A2(n_1_0_1263), .B1(n_1_0_1257), .B2(registers_3__ap[8]), + .ZN(n_1_0_821) + ); + INV_X1_LVT i_1_0_861( + .A(n_1_0_821), .ZN(n_1_0_820) + ); + SDFF_X1_LVT \registers_reg[31][8] ( + .CK(n_0_61), .D(registers[8]), .Q(registers_31__ap[8]), .QN(), .SE(dftIn), + .SI(registers_3__ap[8]) + ); + SDFF_X1_LVT \registers_reg[4][8] ( + .CK(n_0_34), .D(registers[8]), .Q(registers_4__ap[8]), .QN(), .SE(dftIn), + .SI(registers_31__ap[8]) + ); + AOI221_X1_LVT i_1_0_858( + .A(n_1_0_820), .B1(n_1_0_1266), .B2(registers_31__ap[8]), .C1(registers_4__ap[8]), + .C2(n_1_0_1278), .ZN(n_1_0_817) + ); + SDFF_X1_LVT \registers_reg[10][8] ( + .CK(n_0_40), .D(registers[8]), .Q(registers_10__ap[8]), .QN(), .SE(dftIn), + .SI(registers_13__ap[8]) + ); + SDFF_X1_LVT \registers_reg[26][8] ( + .CK(n_0_56), .D(registers[8]), .Q(registers_26__ap[8]), .QN(), .SE(dftIn), + .SI(registers_24__ap[8]) + ); + SDFF_X1_LVT \registers_reg[25][8] ( + .CK(n_0_55), .D(registers[8]), .Q(registers_25__ap[8]), .QN(), .SE(dftIn), + .SI(registers_26__ap[8]) + ); + AOI222_X1_LVT i_1_0_857( + .A1(registers_10__ap[8]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[8]), + .C1(registers_25__ap[8]), .C2(n_1_0_1269), .ZN(n_1_0_816) + ); + NAND4_X1_LVT i_1_0_856( + .A1(n_1_0_822), .A2(n_1_0_818), .A3(n_1_0_817), .A4(n_1_0_816), .ZN(n_1_0_815) + ); + SDFF_X1_LVT \registers_reg[8][8] ( + .CK(n_0_38), .D(registers[8]), .Q(registers_8__ap[8]), .QN(), .SE(dftIn), + .SI(registers_4__ap[8]) + ); + SDFF_X1_LVT \registers_reg[28][8] ( + .CK(n_0_58), .D(registers[8]), .Q(registers_28__ap[8]), .QN(), .SE(dftIn), + .SI(registers_25__ap[8]) + ); + AOI221_X1_LVT i_1_0_855( + .A(n_1_0_815), .B1(n_1_0_1282), .B2(registers_8__ap[8]), .C1(registers_28__ap[8]), + .C2(n_1_0_1283), .ZN(n_1_0_814) + ); + SDFF_X1_LVT \registers_reg[18][8] ( + .CK(n_0_48), .D(registers[8]), .Q(registers_18__ap[8]), .QN(), .SE(dftIn), + .SI(registers_20__ap[8]) + ); + SDFF_X1_LVT \registers_reg[30][8] ( + .CK(n_0_60), .D(registers[8]), .Q(registers_30__ap[8]), .QN(), .SE(dftIn), + .SI(registers_28__ap[8]) + ); + AOI22_X1_LVT i_1_0_854( + .A1(registers_18__ap[8]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[8]), + .ZN(n_1_0_813) + ); + SDFF_X1_LVT \registers_reg[17][8] ( + .CK(n_0_47), .D(registers[8]), .Q(registers_17__ap[8]), .QN(), .SE(dftIn), + .SI(registers_18__ap[8]) + ); + SDFF_X1_LVT \registers_reg[12][8] ( + .CK(n_0_42), .D(registers[8]), .Q(registers_12__ap[8]), .QN(), .SE(dftIn), + .SI(registers_10__ap[8]) + ); + AOI22_X1_LVT i_1_0_853( + .A1(registers_17__ap[8]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[8]), + .ZN(n_1_0_812) + ); + SDFF_X1_LVT \registers_reg[15][8] ( + .CK(n_0_45), .D(registers[8]), .Q(registers_15__ap[8]), .QN(), .SE(dftIn), + .SI(registers_12__ap[8]) + ); + SDFF_X1_LVT \registers_reg[5][8] ( + .CK(n_0_35), .D(registers[8]), .Q(registers_5__ap[8]), .QN(), .SE(dftIn), + .SI(registers_8__ap[8]) + ); + AOI22_X1_LVT i_1_0_852( + .A1(registers_15__ap[8]), .A2(n_1_0_1286), .B1(n_1_0_1273), .B2(registers_5__ap[8]), + .ZN(n_1_0_811) + ); + NAND3_X1_LVT i_1_0_851( + .A1(n_1_0_813), .A2(n_1_0_812), .A3(n_1_0_811), .ZN(n_1_0_810) + ); + SDFF_X1_LVT \registers_reg[22][8] ( + .CK(n_0_52), .D(registers[8]), .Q(registers_22__ap[8]), .QN(), .SE(dftIn), + .SI(registers_17__ap[8]) + ); + SDFF_X1_LVT \registers_reg[16][8] ( + .CK(n_0_46), .D(registers[8]), .Q(registers_16__ap[8]), .QN(), .SE(dftIn), + .SI(registers_15__ap[8]) + ); + AOI221_X1_LVT i_1_0_850( + .A(n_1_0_810), .B1(n_1_0_1294), .B2(registers_22__ap[8]), .C1(registers_16__ap[8]), + .C2(n_1_0_1267), .ZN(n_1_0_809) + ); + SDFF_X1_LVT \registers_reg[9][8] ( + .CK(n_0_39), .D(registers[8]), .Q(registers_9__ap[8]), .QN(), .SE(dftIn), + .SI(registers_5__ap[8]) + ); + SDFF_X1_LVT \registers_reg[1][8] ( + .CK(n_0_0), .D(registers[8]), .Q(registers_1__ap[8]), .QN(), .SE(dftIn), + .SI(registers_22__ap[8]) + ); + AOI22_X1_LVT i_1_0_849( + .A1(registers_9__ap[8]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[8]), + .ZN(n_1_0_808) + ); + SDFF_X1_LVT \registers_reg[6][8] ( + .CK(n_0_36), .D(registers[8]), .Q(registers_6__ap[8]), .QN(), .SE(dftIn), + .SI(registers_9__ap[8]) + ); + SDFF_X1_LVT \registers_reg[14][8] ( + .CK(n_0_44), .D(registers[8]), .Q(registers_14__ap[8]), .QN(), .SE(dftIn), + .SI(registers_16__ap[8]) + ); + AOI22_X1_LVT i_1_0_848( + .A1(registers_6__ap[8]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[8]), + .ZN(n_1_0_807) + ); + SDFF_X1_LVT \registers_reg[19][8] ( + .CK(n_0_49), .D(registers[8]), .Q(registers_19__ap[8]), .QN(), .SE(dftIn), + .SI(registers_1__ap[8]) + ); + SDFF_X1_LVT \registers_reg[2][8] ( + .CK(n_0_32), .D(registers[8]), .Q(registers_2__ap[8]), .QN(), .SE(dftIn), + .SI(registers_30__ap[8]) + ); + AOI22_X1_LVT i_1_0_847( + .A1(registers_19__ap[8]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[8]), + .ZN(n_1_0_806) + ); + NAND3_X1_LVT i_1_0_846( + .A1(n_1_0_808), .A2(n_1_0_807), .A3(n_1_0_806), .ZN(n_1_0_805) + ); + SDFF_X1_LVT \registers_reg[11][8] ( + .CK(n_0_41), .D(registers[8]), .Q(registers_11__ap[8]), .QN(), .SE(dftIn), + .SI(registers_14__ap[8]) + ); + SDFF_X1_LVT \registers_reg[27][8] ( + .CK(n_0_57), .D(registers[8]), .Q(registers_27__ap[8]), .QN(), .SE(dftIn), + .SI(registers_2__ap[8]) + ); + AOI221_X1_LVT i_1_0_845( + .A(n_1_0_805), .B1(n_1_0_1270), .B2(registers_11__ap[8]), .C1(registers_27__ap[8]), + .C2(n_1_0_1279), .ZN(n_1_0_804) + ); + NAND4_X1_LVT i_1_0_844( + .A1(n_1_0_819), .A2(n_1_0_814), .A3(n_1_0_809), .A4(n_1_0_804), .ZN(RRs1[8]) + ); + AND2_X1_LVT i_0_0_7( + .A1(n_0_0_16), .A2(WRd[7]), .ZN(registers[7]) + ); + SDFF_X1_LVT \registers_reg[13][7] ( + .CK(n_0_43), .D(registers[7]), .Q(registers_13__ap[7]), .QN(), .SE(dftIn), + .SI(registers_11__ap[8]) + ); + SDFF_X1_LVT \registers_reg[21][7] ( + .CK(n_0_51), .D(registers[7]), .Q(registers_21__ap[7]), .QN(), .SE(dftIn), + .SI(registers_19__ap[8]) + ); + AOI22_X1_LVT i_1_0_843( + .A1(registers_13__ap[7]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[7]), + .ZN(n_1_0_803) + ); + SDFF_X1_LVT \registers_reg[18][7] ( + .CK(n_0_48), .D(registers[7]), .Q(registers_18__ap[7]), .QN(), .SE(dftIn), + .SI(registers_21__ap[7]) + ); + SDFF_X1_LVT \registers_reg[10][7] ( + .CK(n_0_40), .D(registers[7]), .Q(registers_10__ap[7]), .QN(), .SE(dftIn), + .SI(registers_13__ap[7]) + ); + SDFF_X1_LVT \registers_reg[25][7] ( + .CK(n_0_55), .D(registers[7]), .Q(registers_25__ap[7]), .QN(), .SE(dftIn), + .SI(registers_27__ap[8]) + ); + AOI222_X1_LVT i_1_0_842( + .A1(registers_18__ap[7]), .A2(n_1_0_1297), .B1(n_1_0_1287), .B2(registers_10__ap[7]), + .C1(registers_25__ap[7]), .C2(n_1_0_1269), .ZN(n_1_0_802) + ); + SDFF_X1_LVT \registers_reg[28][7] ( + .CK(n_0_58), .D(registers[7]), .Q(registers_28__ap[7]), .QN(), .SE(dftIn), + .SI(registers_25__ap[7]) + ); + SDFF_X1_LVT \registers_reg[8][7] ( + .CK(n_0_38), .D(registers[7]), .Q(registers_8__ap[7]), .QN(), .SE(dftIn), + .SI(registers_6__ap[8]) + ); + AOI22_X1_LVT i_1_0_841( + .A1(registers_28__ap[7]), .A2(n_1_0_1283), .B1(n_1_0_1282), .B2(registers_8__ap[7]), + .ZN(n_1_0_801) + ); + SDFF_X1_LVT \registers_reg[24][7] ( + .CK(n_0_54), .D(registers[7]), .Q(registers_24__ap[7]), .QN(), .SE(dftIn), + .SI(registers_28__ap[7]) + ); + SDFF_X1_LVT \registers_reg[20][7] ( + .CK(n_0_50), .D(registers[7]), .Q(registers_20__ap[7]), .QN(), .SE(dftIn), + .SI(registers_18__ap[7]) + ); + AOI22_X1_LVT i_1_0_840( + .A1(registers_24__ap[7]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[7]), + .ZN(n_1_0_800) + ); + SDFF_X1_LVT \registers_reg[31][7] ( + .CK(n_0_61), .D(registers[7]), .Q(registers_31__ap[7]), .QN(), .SE(dftIn), + .SI(registers_8__ap[7]) + ); + SDFF_X1_LVT \registers_reg[7][7] ( + .CK(n_0_37), .D(registers[7]), .Q(registers_7__ap[7]), .QN(), .SE(dftIn), + .SI(registers_31__ap[7]) + ); + AOI22_X1_LVT i_1_0_839( + .A1(registers_31__ap[7]), .A2(n_1_0_1266), .B1(n_1_0_1263), .B2(registers_7__ap[7]), + .ZN(n_1_0_799) + ); + SDFF_X1_LVT \registers_reg[17][7] ( + .CK(n_0_47), .D(registers[7]), .Q(registers_17__ap[7]), .QN(), .SE(dftIn), + .SI(registers_20__ap[7]) + ); + SDFF_X1_LVT \registers_reg[11][7] ( + .CK(n_0_41), .D(registers[7]), .Q(registers_11__ap[7]), .QN(), .SE(dftIn), + .SI(registers_10__ap[7]) + ); + AOI22_X1_LVT i_1_0_838( + .A1(registers_17__ap[7]), .A2(n_1_0_1271), .B1(n_1_0_1270), .B2(registers_11__ap[7]), + .ZN(n_1_0_798) + ); + SDFF_X1_LVT \registers_reg[27][7] ( + .CK(n_0_57), .D(registers[7]), .Q(registers_27__ap[7]), .QN(), .SE(dftIn), + .SI(registers_24__ap[7]) + ); + SDFF_X1_LVT \registers_reg[29][7] ( + .CK(n_0_59), .D(registers[7]), .Q(registers_29__ap[7]), .QN(), .SE(dftIn), + .SI(registers_27__ap[7]) + ); + AOI22_X1_LVT i_1_0_837( + .A1(registers_27__ap[7]), .A2(n_1_0_1279), .B1(n_1_0_1276), .B2(registers_29__ap[7]), + .ZN(n_1_0_797) + ); + NAND4_X1_LVT i_1_0_836( + .A1(n_1_0_800), .A2(n_1_0_799), .A3(n_1_0_798), .A4(n_1_0_797), .ZN(n_1_0_796) + ); + SDFF_X1_LVT \registers_reg[26][7] ( + .CK(n_0_56), .D(registers[7]), .Q(registers_26__ap[7]), .QN(), .SE(dftIn), + .SI(registers_29__ap[7]) + ); + SDFF_X1_LVT \registers_reg[30][7] ( + .CK(n_0_60), .D(registers[7]), .Q(registers_30__ap[7]), .QN(), .SE(dftIn), + .SI(registers_26__ap[7]) + ); + AOI22_X1_LVT i_1_0_835( + .A1(registers_26__ap[7]), .A2(n_1_0_1285), .B1(n_1_0_1272), .B2(registers_30__ap[7]), + .ZN(n_1_0_795) + ); + SDFF_X1_LVT \registers_reg[4][7] ( + .CK(n_0_34), .D(registers[7]), .Q(registers_4__ap[7]), .QN(), .SE(dftIn), + .SI(registers_7__ap[7]) + ); + SDFF_X1_LVT \registers_reg[12][7] ( + .CK(n_0_42), .D(registers[7]), .Q(registers_12__ap[7]), .QN(), .SE(dftIn), + .SI(registers_11__ap[7]) + ); + AOI22_X1_LVT i_1_0_834( + .A1(registers_4__ap[7]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[7]), + .ZN(n_1_0_794) + ); + SDFF_X1_LVT \registers_reg[15][7] ( + .CK(n_0_45), .D(registers[7]), .Q(registers_15__ap[7]), .QN(), .SE(dftIn), + .SI(registers_12__ap[7]) + ); + SDFF_X1_LVT \registers_reg[16][7] ( + .CK(n_0_46), .D(registers[7]), .Q(registers_16__ap[7]), .QN(), .SE(dftIn), + .SI(registers_15__ap[7]) + ); + AOI22_X1_LVT i_1_0_833( + .A1(registers_15__ap[7]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[7]), + .ZN(n_1_0_793) + ); + SDFF_X1_LVT \registers_reg[22][7] ( + .CK(n_0_52), .D(registers[7]), .Q(registers_22__ap[7]), .QN(), .SE(dftIn), + .SI(registers_17__ap[7]) + ); + SDFF_X1_LVT \registers_reg[5][7] ( + .CK(n_0_35), .D(registers[7]), .Q(registers_5__ap[7]), .QN(), .SE(dftIn), + .SI(registers_4__ap[7]) + ); + AOI22_X1_LVT i_1_0_832( + .A1(registers_22__ap[7]), .A2(n_1_0_1294), .B1(n_1_0_1273), .B2(registers_5__ap[7]), + .ZN(n_1_0_792) + ); + NAND4_X1_LVT i_1_0_831( + .A1(n_1_0_795), .A2(n_1_0_794), .A3(n_1_0_793), .A4(n_1_0_792), .ZN(n_1_0_791) + ); + SDFF_X1_LVT \registers_reg[19][7] ( + .CK(n_0_49), .D(registers[7]), .Q(registers_19__ap[7]), .QN(), .SE(dftIn), + .SI(registers_22__ap[7]) + ); + SDFF_X1_LVT \registers_reg[3][7] ( + .CK(n_0_33), .D(registers[7]), .Q(registers_3__ap[7]), .QN(), .SE(dftIn), + .SI(registers_5__ap[7]) + ); + AOI22_X1_LVT i_1_0_830( + .A1(registers_19__ap[7]), .A2(n_1_0_1295), .B1(n_1_0_1257), .B2(registers_3__ap[7]), + .ZN(n_1_0_790) + ); + SDFF_X1_LVT \registers_reg[9][7] ( + .CK(n_0_39), .D(registers[7]), .Q(registers_9__ap[7]), .QN(), .SE(dftIn), + .SI(registers_3__ap[7]) + ); + SDFF_X1_LVT \registers_reg[1][7] ( + .CK(n_0_0), .D(registers[7]), .Q(registers_1__ap[7]), .QN(), .SE(dftIn), + .SI(registers_19__ap[7]) + ); + AOI22_X1_LVT i_1_0_829( + .A1(registers_9__ap[7]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[7]), + .ZN(n_1_0_789) + ); + SDFF_X1_LVT \registers_reg[6][7] ( + .CK(n_0_36), .D(registers[7]), .Q(registers_6__ap[7]), .QN(), .SE(dftIn), + .SI(registers_9__ap[7]) + ); + SDFF_X1_LVT \registers_reg[14][7] ( + .CK(n_0_44), .D(registers[7]), .Q(registers_14__ap[7]), .QN(), .SE(dftIn), + .SI(registers_16__ap[7]) + ); + AOI22_X1_LVT i_1_0_828( + .A1(registers_6__ap[7]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[7]), + .ZN(n_1_0_788) + ); + SDFF_X1_LVT \registers_reg[2][7] ( + .CK(n_0_32), .D(registers[7]), .Q(registers_2__ap[7]), .QN(), .SE(dftIn), + .SI(registers_30__ap[7]) + ); + SDFF_X1_LVT \registers_reg[23][7] ( + .CK(n_0_53), .D(registers[7]), .Q(registers_23__ap[7]), .QN(), .SE(dftIn), + .SI(registers_1__ap[7]) + ); + AOI22_X1_LVT i_1_0_827( + .A1(registers_2__ap[7]), .A2(n_1_0_1268), .B1(n_1_0_1264), .B2(registers_23__ap[7]), + .ZN(n_1_0_787) + ); + NAND4_X1_LVT i_1_0_826( + .A1(n_1_0_790), .A2(n_1_0_789), .A3(n_1_0_788), .A4(n_1_0_787), .ZN(n_1_0_786) + ); + NOR3_X1_LVT i_1_0_825( + .A1(n_1_0_796), .A2(n_1_0_791), .A3(n_1_0_786), .ZN(n_1_0_785) + ); + NAND4_X1_LVT i_1_0_824( + .A1(n_1_0_803), .A2(n_1_0_802), .A3(n_1_0_801), .A4(n_1_0_785), .ZN(RRs1[7]) + ); + AND2_X1_LVT i_0_0_6( + .A1(n_0_0_16), .A2(WRd[6]), .ZN(registers[6]) + ); + SDFF_X1_LVT \registers_reg[28][6] ( + .CK(n_0_58), .D(registers[6]), .Q(registers_28__ap[6]), .QN(), .SE(dftIn), + .SI(registers_2__ap[7]) + ); + SDFF_X1_LVT \registers_reg[17][6] ( + .CK(n_0_47), .D(registers[6]), .Q(registers_17__ap[6]), .QN(), .SE(dftIn), + .SI(registers_23__ap[7]) + ); + AOI22_X1_LVT i_1_0_823( + .A1(registers_28__ap[6]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[6]), + .ZN(n_1_0_784) + ); + SDFF_X1_LVT \registers_reg[18][6] ( + .CK(n_0_48), .D(registers[6]), .Q(registers_18__ap[6]), .QN(), .SE(dftIn), + .SI(registers_17__ap[6]) + ); + SDFF_X1_LVT \registers_reg[10][6] ( + .CK(n_0_40), .D(registers[6]), .Q(registers_10__ap[6]), .QN(), .SE(dftIn), + .SI(registers_14__ap[7]) + ); + SDFF_X1_LVT \registers_reg[8][6] ( + .CK(n_0_38), .D(registers[6]), .Q(registers_8__ap[6]), .QN(), .SE(dftIn), + .SI(registers_6__ap[7]) + ); + AOI222_X1_LVT i_1_0_822( + .A1(registers_18__ap[6]), .A2(n_1_0_1297), .B1(n_1_0_1287), .B2(registers_10__ap[6]), + .C1(registers_8__ap[6]), .C2(n_1_0_1282), .ZN(n_1_0_783) + ); + SDFF_X1_LVT \registers_reg[9][6] ( + .CK(n_0_39), .D(registers[6]), .Q(registers_9__ap[6]), .QN(), .SE(dftIn), + .SI(registers_8__ap[6]) + ); + SDFF_X1_LVT \registers_reg[29][6] ( + .CK(n_0_59), .D(registers[6]), .Q(registers_29__ap[6]), .QN(), .SE(dftIn), + .SI(registers_28__ap[6]) + ); + AOI22_X1_LVT i_1_0_821( + .A1(registers_9__ap[6]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[6]), + .ZN(n_1_0_782) + ); + SDFF_X1_LVT \registers_reg[6][6] ( + .CK(n_0_36), .D(registers[6]), .Q(registers_6__ap[6]), .QN(), .SE(dftIn), + .SI(registers_9__ap[6]) + ); + SDFF_X1_LVT \registers_reg[1][6] ( + .CK(n_0_0), .D(registers[6]), .Q(registers_1__ap[6]), .QN(), .SE(dftIn), + .SI(registers_18__ap[6]) + ); + AOI22_X1_LVT i_1_0_820( + .A1(registers_6__ap[6]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[6]), + .ZN(n_1_0_781) + ); + SDFF_X1_LVT \registers_reg[15][6] ( + .CK(n_0_45), .D(registers[6]), .Q(registers_15__ap[6]), .QN(), .SE(dftIn), + .SI(registers_10__ap[6]) + ); + SDFF_X1_LVT \registers_reg[27][6] ( + .CK(n_0_57), .D(registers[6]), .Q(registers_27__ap[6]), .QN(), .SE(dftIn), + .SI(registers_29__ap[6]) + ); + AOI22_X1_LVT i_1_0_819( + .A1(registers_15__ap[6]), .A2(n_1_0_1286), .B1(n_1_0_1279), .B2(registers_27__ap[6]), + .ZN(n_1_0_780) + ); + SDFF_X1_LVT \registers_reg[11][6] ( + .CK(n_0_41), .D(registers[6]), .Q(registers_11__ap[6]), .QN(), .SE(dftIn), + .SI(registers_15__ap[6]) + ); + SDFF_X1_LVT \registers_reg[16][6] ( + .CK(n_0_46), .D(registers[6]), .Q(registers_16__ap[6]), .QN(), .SE(dftIn), + .SI(registers_11__ap[6]) + ); + AOI22_X1_LVT i_1_0_818( + .A1(registers_11__ap[6]), .A2(n_1_0_1270), .B1(n_1_0_1267), .B2(registers_16__ap[6]), + .ZN(n_1_0_779) + ); + SDFF_X1_LVT \registers_reg[5][6] ( + .CK(n_0_35), .D(registers[6]), .Q(registers_5__ap[6]), .QN(), .SE(dftIn), + .SI(registers_6__ap[6]) + ); + SDFF_X1_LVT \registers_reg[31][6] ( + .CK(n_0_61), .D(registers[6]), .Q(registers_31__ap[6]), .QN(), .SE(dftIn), + .SI(registers_5__ap[6]) + ); + AOI22_X1_LVT i_1_0_817( + .A1(registers_5__ap[6]), .A2(n_1_0_1273), .B1(n_1_0_1266), .B2(registers_31__ap[6]), + .ZN(n_1_0_778) + ); + NAND4_X1_LVT i_1_0_816( + .A1(n_1_0_781), .A2(n_1_0_780), .A3(n_1_0_779), .A4(n_1_0_778), .ZN(n_1_0_777) + ); + SDFF_X1_LVT \registers_reg[26][6] ( + .CK(n_0_56), .D(registers[6]), .Q(registers_26__ap[6]), .QN(), .SE(dftIn), + .SI(registers_27__ap[6]) + ); + SDFF_X1_LVT \registers_reg[30][6] ( + .CK(n_0_60), .D(registers[6]), .Q(registers_30__ap[6]), .QN(), .SE(dftIn), + .SI(registers_26__ap[6]) + ); + AOI22_X1_LVT i_1_0_815( + .A1(registers_26__ap[6]), .A2(n_1_0_1285), .B1(n_1_0_1272), .B2(registers_30__ap[6]), + .ZN(n_1_0_776) + ); + SDFF_X1_LVT \registers_reg[20][6] ( + .CK(n_0_50), .D(registers[6]), .Q(registers_20__ap[6]), .QN(), .SE(dftIn), + .SI(registers_1__ap[6]) + ); + SDFF_X1_LVT \registers_reg[4][6] ( + .CK(n_0_34), .D(registers[6]), .Q(registers_4__ap[6]), .QN(), .SE(dftIn), + .SI(registers_31__ap[6]) + ); + AOI22_X1_LVT i_1_0_814( + .A1(registers_20__ap[6]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[6]), + .ZN(n_1_0_775) + ); + SDFF_X1_LVT \registers_reg[22][6] ( + .CK(n_0_52), .D(registers[6]), .Q(registers_22__ap[6]), .QN(), .SE(dftIn), + .SI(registers_20__ap[6]) + ); + SDFF_X1_LVT \registers_reg[21][6] ( + .CK(n_0_51), .D(registers[6]), .Q(registers_21__ap[6]), .QN(), .SE(dftIn), + .SI(registers_22__ap[6]) + ); + AOI22_X1_LVT i_1_0_813( + .A1(registers_22__ap[6]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[6]), + .ZN(n_1_0_774) + ); + SDFF_X1_LVT \registers_reg[24][6] ( + .CK(n_0_54), .D(registers[6]), .Q(registers_24__ap[6]), .QN(), .SE(dftIn), + .SI(registers_30__ap[6]) + ); + SDFF_X1_LVT \registers_reg[12][6] ( + .CK(n_0_42), .D(registers[6]), .Q(registers_12__ap[6]), .QN(), .SE(dftIn), + .SI(registers_16__ap[6]) + ); + AOI22_X1_LVT i_1_0_812( + .A1(registers_24__ap[6]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[6]), + .ZN(n_1_0_773) + ); + NAND4_X1_LVT i_1_0_811( + .A1(n_1_0_776), .A2(n_1_0_775), .A3(n_1_0_774), .A4(n_1_0_773), .ZN(n_1_0_772) + ); + SDFF_X1_LVT \registers_reg[13][6] ( + .CK(n_0_43), .D(registers[6]), .Q(registers_13__ap[6]), .QN(), .SE(dftIn), + .SI(registers_12__ap[6]) + ); + SDFF_X1_LVT \registers_reg[25][6] ( + .CK(n_0_55), .D(registers[6]), .Q(registers_25__ap[6]), .QN(), .SE(dftIn), + .SI(registers_24__ap[6]) + ); + AOI22_X1_LVT i_1_0_810( + .A1(registers_13__ap[6]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[6]), + .ZN(n_1_0_771) + ); + SDFF_X1_LVT \registers_reg[7][6] ( + .CK(n_0_37), .D(registers[6]), .Q(registers_7__ap[6]), .QN(), .SE(dftIn), + .SI(registers_4__ap[6]) + ); + SDFF_X1_LVT \registers_reg[14][6] ( + .CK(n_0_44), .D(registers[6]), .Q(registers_14__ap[6]), .QN(), .SE(dftIn), + .SI(registers_13__ap[6]) + ); + AOI22_X1_LVT i_1_0_809( + .A1(registers_7__ap[6]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[6]), + .ZN(n_1_0_770) + ); + SDFF_X1_LVT \registers_reg[19][6] ( + .CK(n_0_49), .D(registers[6]), .Q(registers_19__ap[6]), .QN(), .SE(dftIn), + .SI(registers_21__ap[6]) + ); + SDFF_X1_LVT \registers_reg[3][6] ( + .CK(n_0_33), .D(registers[6]), .Q(registers_3__ap[6]), .QN(), .SE(dftIn), + .SI(registers_7__ap[6]) + ); + AOI22_X1_LVT i_1_0_808( + .A1(registers_19__ap[6]), .A2(n_1_0_1295), .B1(n_1_0_1257), .B2(registers_3__ap[6]), + .ZN(n_1_0_769) + ); + SDFF_X1_LVT \registers_reg[2][6] ( + .CK(n_0_32), .D(registers[6]), .Q(registers_2__ap[6]), .QN(), .SE(dftIn), + .SI(registers_25__ap[6]) + ); + SDFF_X1_LVT \registers_reg[23][6] ( + .CK(n_0_53), .D(registers[6]), .Q(registers_23__ap[6]), .QN(), .SE(dftIn), + .SI(registers_19__ap[6]) + ); + AOI22_X1_LVT i_1_0_807( + .A1(registers_2__ap[6]), .A2(n_1_0_1268), .B1(n_1_0_1264), .B2(registers_23__ap[6]), + .ZN(n_1_0_768) + ); + NAND4_X1_LVT i_1_0_806( + .A1(n_1_0_771), .A2(n_1_0_770), .A3(n_1_0_769), .A4(n_1_0_768), .ZN(n_1_0_767) + ); + NOR3_X1_LVT i_1_0_805( + .A1(n_1_0_777), .A2(n_1_0_772), .A3(n_1_0_767), .ZN(n_1_0_766) + ); + NAND4_X1_LVT i_1_0_804( + .A1(n_1_0_784), .A2(n_1_0_783), .A3(n_1_0_782), .A4(n_1_0_766), .ZN(RRs1[6]) + ); + AND2_X1_LVT i_0_0_5( + .A1(n_0_0_16), .A2(WRd[5]), .ZN(registers[5]) + ); + SDFF_X1_LVT \registers_reg[28][5] ( + .CK(n_0_58), .D(registers[5]), .Q(registers_28__ap[5]), .QN(), .SE(dftIn), + .SI(registers_2__ap[6]) + ); + SDFF_X1_LVT \registers_reg[4][5] ( + .CK(n_0_34), .D(registers[5]), .Q(registers_4__ap[5]), .QN(), .SE(dftIn), + .SI(registers_3__ap[6]) + ); + AOI22_X1_LVT i_1_0_803( + .A1(registers_28__ap[5]), .A2(n_1_0_1283), .B1(n_1_0_1278), .B2(registers_4__ap[5]), + .ZN(n_1_0_765) + ); + SDFF_X1_LVT \registers_reg[10][5] ( + .CK(n_0_40), .D(registers[5]), .Q(registers_10__ap[5]), .QN(), .SE(dftIn), + .SI(registers_14__ap[6]) + ); + SDFF_X1_LVT \registers_reg[26][5] ( + .CK(n_0_56), .D(registers[5]), .Q(registers_26__ap[5]), .QN(), .SE(dftIn), + .SI(registers_28__ap[5]) + ); + SDFF_X1_LVT \registers_reg[8][5] ( + .CK(n_0_38), .D(registers[5]), .Q(registers_8__ap[5]), .QN(), .SE(dftIn), + .SI(registers_4__ap[5]) + ); + AOI222_X1_LVT i_1_0_802( + .A1(registers_10__ap[5]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[5]), + .C1(registers_8__ap[5]), .C2(n_1_0_1282), .ZN(n_1_0_764) + ); + SDFF_X1_LVT \registers_reg[9][5] ( + .CK(n_0_39), .D(registers[5]), .Q(registers_9__ap[5]), .QN(), .SE(dftIn), + .SI(registers_8__ap[5]) + ); + SDFF_X1_LVT \registers_reg[29][5] ( + .CK(n_0_59), .D(registers[5]), .Q(registers_29__ap[5]), .QN(), .SE(dftIn), + .SI(registers_26__ap[5]) + ); + AOI22_X1_LVT i_1_0_801( + .A1(registers_9__ap[5]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[5]), + .ZN(n_1_0_763) + ); + SDFF_X1_LVT \registers_reg[6][5] ( + .CK(n_0_36), .D(registers[5]), .Q(registers_6__ap[5]), .QN(), .SE(dftIn), + .SI(registers_9__ap[5]) + ); + SDFF_X1_LVT \registers_reg[1][5] ( + .CK(n_0_0), .D(registers[5]), .Q(registers_1__ap[5]), .QN(), .SE(dftIn), + .SI(registers_23__ap[6]) + ); + AOI22_X1_LVT i_1_0_800( + .A1(registers_6__ap[5]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[5]), + .ZN(n_1_0_762) + ); + SDFF_X1_LVT \registers_reg[16][5] ( + .CK(n_0_46), .D(registers[5]), .Q(registers_16__ap[5]), .QN(), .SE(dftIn), + .SI(registers_10__ap[5]) + ); + SDFF_X1_LVT \registers_reg[3][5] ( + .CK(n_0_33), .D(registers[5]), .Q(registers_3__ap[5]), .QN(), .SE(dftIn), + .SI(registers_6__ap[5]) + ); + AOI22_X1_LVT i_1_0_799( + .A1(registers_16__ap[5]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[5]), + .ZN(n_1_0_761) + ); + SDFF_X1_LVT \registers_reg[5][5] ( + .CK(n_0_35), .D(registers[5]), .Q(registers_5__ap[5]), .QN(), .SE(dftIn), + .SI(registers_3__ap[5]) + ); + SDFF_X1_LVT \registers_reg[31][5] ( + .CK(n_0_61), .D(registers[5]), .Q(registers_31__ap[5]), .QN(), .SE(dftIn), + .SI(registers_5__ap[5]) + ); + AOI22_X1_LVT i_1_0_798( + .A1(registers_5__ap[5]), .A2(n_1_0_1273), .B1(n_1_0_1266), .B2(registers_31__ap[5]), + .ZN(n_1_0_760) + ); + SDFF_X1_LVT \registers_reg[15][5] ( + .CK(n_0_45), .D(registers[5]), .Q(registers_15__ap[5]), .QN(), .SE(dftIn), + .SI(registers_16__ap[5]) + ); + SDFF_X1_LVT \registers_reg[23][5] ( + .CK(n_0_53), .D(registers[5]), .Q(registers_23__ap[5]), .QN(), .SE(dftIn), + .SI(registers_1__ap[5]) + ); + AOI22_X1_LVT i_1_0_797( + .A1(registers_15__ap[5]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[5]), + .ZN(n_1_0_759) + ); + NAND4_X1_LVT i_1_0_796( + .A1(n_1_0_762), .A2(n_1_0_761), .A3(n_1_0_760), .A4(n_1_0_759), .ZN(n_1_0_758) + ); + SDFF_X1_LVT \registers_reg[18][5] ( + .CK(n_0_48), .D(registers[5]), .Q(registers_18__ap[5]), .QN(), .SE(dftIn), + .SI(registers_23__ap[5]) + ); + SDFF_X1_LVT \registers_reg[30][5] ( + .CK(n_0_60), .D(registers[5]), .Q(registers_30__ap[5]), .QN(), .SE(dftIn), + .SI(registers_29__ap[5]) + ); + AOI22_X1_LVT i_1_0_795( + .A1(registers_18__ap[5]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[5]), + .ZN(n_1_0_757) + ); + SDFF_X1_LVT \registers_reg[24][5] ( + .CK(n_0_54), .D(registers[5]), .Q(registers_24__ap[5]), .QN(), .SE(dftIn), + .SI(registers_30__ap[5]) + ); + SDFF_X1_LVT \registers_reg[12][5] ( + .CK(n_0_42), .D(registers[5]), .Q(registers_12__ap[5]), .QN(), .SE(dftIn), + .SI(registers_15__ap[5]) + ); + AOI22_X1_LVT i_1_0_794( + .A1(registers_24__ap[5]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[5]), + .ZN(n_1_0_756) + ); + SDFF_X1_LVT \registers_reg[22][5] ( + .CK(n_0_52), .D(registers[5]), .Q(registers_22__ap[5]), .QN(), .SE(dftIn), + .SI(registers_18__ap[5]) + ); + SDFF_X1_LVT \registers_reg[21][5] ( + .CK(n_0_51), .D(registers[5]), .Q(registers_21__ap[5]), .QN(), .SE(dftIn), + .SI(registers_22__ap[5]) + ); + AOI22_X1_LVT i_1_0_793( + .A1(registers_22__ap[5]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[5]), + .ZN(n_1_0_755) + ); + SDFF_X1_LVT \registers_reg[20][5] ( + .CK(n_0_50), .D(registers[5]), .Q(registers_20__ap[5]), .QN(), .SE(dftIn), + .SI(registers_21__ap[5]) + ); + SDFF_X1_LVT \registers_reg[17][5] ( + .CK(n_0_47), .D(registers[5]), .Q(registers_17__ap[5]), .QN(), .SE(dftIn), + .SI(registers_20__ap[5]) + ); + AOI22_X1_LVT i_1_0_792( + .A1(registers_20__ap[5]), .A2(n_1_0_1281), .B1(n_1_0_1271), .B2(registers_17__ap[5]), + .ZN(n_1_0_754) + ); + NAND4_X1_LVT i_1_0_791( + .A1(n_1_0_757), .A2(n_1_0_756), .A3(n_1_0_755), .A4(n_1_0_754), .ZN(n_1_0_753) + ); + SDFF_X1_LVT \registers_reg[13][5] ( + .CK(n_0_43), .D(registers[5]), .Q(registers_13__ap[5]), .QN(), .SE(dftIn), + .SI(registers_12__ap[5]) + ); + SDFF_X1_LVT \registers_reg[25][5] ( + .CK(n_0_55), .D(registers[5]), .Q(registers_25__ap[5]), .QN(), .SE(dftIn), + .SI(registers_24__ap[5]) + ); + AOI22_X1_LVT i_1_0_790( + .A1(registers_13__ap[5]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[5]), + .ZN(n_1_0_752) + ); + SDFF_X1_LVT \registers_reg[19][5] ( + .CK(n_0_49), .D(registers[5]), .Q(registers_19__ap[5]), .QN(), .SE(dftIn), + .SI(registers_17__ap[5]) + ); + SDFF_X1_LVT \registers_reg[2][5] ( + .CK(n_0_32), .D(registers[5]), .Q(registers_2__ap[5]), .QN(), .SE(dftIn), + .SI(registers_25__ap[5]) + ); + AOI22_X1_LVT i_1_0_789( + .A1(registers_19__ap[5]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[5]), + .ZN(n_1_0_751) + ); + SDFF_X1_LVT \registers_reg[7][5] ( + .CK(n_0_37), .D(registers[5]), .Q(registers_7__ap[5]), .QN(), .SE(dftIn), + .SI(registers_31__ap[5]) + ); + SDFF_X1_LVT \registers_reg[14][5] ( + .CK(n_0_44), .D(registers[5]), .Q(registers_14__ap[5]), .QN(), .SE(dftIn), + .SI(registers_13__ap[5]) + ); + AOI22_X1_LVT i_1_0_788( + .A1(registers_7__ap[5]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[5]), + .ZN(n_1_0_750) + ); + SDFF_X1_LVT \registers_reg[27][5] ( + .CK(n_0_57), .D(registers[5]), .Q(registers_27__ap[5]), .QN(), .SE(dftIn), + .SI(registers_2__ap[5]) + ); + SDFF_X1_LVT \registers_reg[11][5] ( + .CK(n_0_41), .D(registers[5]), .Q(registers_11__ap[5]), .QN(), .SE(dftIn), + .SI(registers_14__ap[5]) + ); + AOI22_X1_LVT i_1_0_787( + .A1(registers_27__ap[5]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[5]), + .ZN(n_1_0_749) + ); + NAND4_X1_LVT i_1_0_786( + .A1(n_1_0_752), .A2(n_1_0_751), .A3(n_1_0_750), .A4(n_1_0_749), .ZN(n_1_0_748) + ); + NOR3_X1_LVT i_1_0_785( + .A1(n_1_0_758), .A2(n_1_0_753), .A3(n_1_0_748), .ZN(n_1_0_747) + ); + NAND4_X1_LVT i_1_0_784( + .A1(n_1_0_765), .A2(n_1_0_764), .A3(n_1_0_763), .A4(n_1_0_747), .ZN(RRs1[5]) + ); + AND2_X1_LVT i_0_0_4( + .A1(n_0_0_16), .A2(WRd[4]), .ZN(registers[4]) + ); + SDFF_X1_LVT \registers_reg[10][4] ( + .CK(n_0_40), .D(registers[4]), .Q(registers_10__ap[4]), .QN(), .SE(dftIn), + .SI(registers_11__ap[5]) + ); + SDFF_X1_LVT \registers_reg[21][4] ( + .CK(n_0_51), .D(registers[4]), .Q(registers_21__ap[4]), .QN(), .SE(dftIn), + .SI(registers_19__ap[5]) + ); + AOI22_X1_LVT i_1_0_783( + .A1(registers_10__ap[4]), .A2(n_1_0_1287), .B1(n_1_0_1259), .B2(registers_21__ap[4]), + .ZN(n_1_0_746) + ); + SDFF_X1_LVT \registers_reg[9][4] ( + .CK(n_0_39), .D(registers[4]), .Q(registers_9__ap[4]), .QN(), .SE(dftIn), + .SI(registers_7__ap[5]) + ); + SDFF_X1_LVT \registers_reg[1][4] ( + .CK(n_0_0), .D(registers[4]), .Q(registers_1__ap[4]), .QN(), .SE(dftIn), + .SI(registers_21__ap[4]) + ); + AOI22_X1_LVT i_1_0_778( + .A1(registers_9__ap[4]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[4]), + .ZN(n_1_0_741) + ); + SDFF_X1_LVT \registers_reg[18][4] ( + .CK(n_0_48), .D(registers[4]), .Q(registers_18__ap[4]), .QN(), .SE(dftIn), + .SI(registers_1__ap[4]) + ); + SDFF_X1_LVT \registers_reg[8][4] ( + .CK(n_0_38), .D(registers[4]), .Q(registers_8__ap[4]), .QN(), .SE(dftIn), + .SI(registers_9__ap[4]) + ); + AOI22_X1_LVT i_1_0_777( + .A1(registers_18__ap[4]), .A2(n_1_0_1297), .B1(n_1_0_1282), .B2(registers_8__ap[4]), + .ZN(n_1_0_740) + ); + NAND3_X1_LVT i_1_0_775( + .A1(n_1_0_746), .A2(n_1_0_741), .A3(n_1_0_740), .ZN(n_1_0_738) + ); + SDFF_X1_LVT \registers_reg[22][4] ( + .CK(n_0_52), .D(registers[4]), .Q(registers_22__ap[4]), .QN(), .SE(dftIn), + .SI(registers_18__ap[4]) + ); + SDFF_X1_LVT \registers_reg[23][4] ( + .CK(n_0_53), .D(registers[4]), .Q(registers_23__ap[4]), .QN(), .SE(dftIn), + .SI(registers_22__ap[4]) + ); + AOI221_X1_LVT i_1_0_774( + .A(n_1_0_738), .B1(n_1_0_1294), .B2(registers_22__ap[4]), .C1(registers_23__ap[4]), + .C2(n_1_0_1264), .ZN(n_1_0_737) + ); + SDFF_X1_LVT \registers_reg[28][4] ( + .CK(n_0_58), .D(registers[4]), .Q(registers_28__ap[4]), .QN(), .SE(dftIn), + .SI(registers_27__ap[5]) + ); + SDFF_X1_LVT \registers_reg[20][4] ( + .CK(n_0_50), .D(registers[4]), .Q(registers_20__ap[4]), .QN(), .SE(dftIn), + .SI(registers_23__ap[4]) + ); + AOI22_X1_LVT i_1_0_782( + .A1(registers_28__ap[4]), .A2(n_1_0_1283), .B1(n_1_0_1281), .B2(registers_20__ap[4]), + .ZN(n_1_0_745) + ); + SDFF_X1_LVT \registers_reg[19][4] ( + .CK(n_0_49), .D(registers[4]), .Q(registers_19__ap[4]), .QN(), .SE(dftIn), + .SI(registers_20__ap[4]) + ); + SDFF_X1_LVT \registers_reg[13][4] ( + .CK(n_0_43), .D(registers[4]), .Q(registers_13__ap[4]), .QN(), .SE(dftIn), + .SI(registers_10__ap[4]) + ); + AOI22_X1_LVT i_1_0_780( + .A1(registers_19__ap[4]), .A2(n_1_0_1295), .B1(n_1_0_1277), .B2(registers_13__ap[4]), + .ZN(n_1_0_743) + ); + SDFF_X1_LVT \registers_reg[26][4] ( + .CK(n_0_56), .D(registers[4]), .Q(registers_26__ap[4]), .QN(), .SE(dftIn), + .SI(registers_28__ap[4]) + ); + SDFF_X1_LVT \registers_reg[3][4] ( + .CK(n_0_33), .D(registers[4]), .Q(registers_3__ap[4]), .QN(), .SE(dftIn), + .SI(registers_8__ap[4]) + ); + AOI22_X1_LVT i_1_0_776( + .A1(registers_26__ap[4]), .A2(n_1_0_1285), .B1(n_1_0_1257), .B2(registers_3__ap[4]), + .ZN(n_1_0_739) + ); + NAND3_X1_LVT i_1_0_773( + .A1(n_1_0_745), .A2(n_1_0_743), .A3(n_1_0_739), .ZN(n_1_0_736) + ); + SDFF_X1_LVT \registers_reg[30][4] ( + .CK(n_0_60), .D(registers[4]), .Q(registers_30__ap[4]), .QN(), .SE(dftIn), + .SI(registers_26__ap[4]) + ); + SDFF_X1_LVT \registers_reg[31][4] ( + .CK(n_0_61), .D(registers[4]), .Q(registers_31__ap[4]), .QN(), .SE(dftIn), + .SI(registers_3__ap[4]) + ); + AOI221_X1_LVT i_1_0_772( + .A(n_1_0_736), .B1(n_1_0_1272), .B2(registers_30__ap[4]), .C1(registers_31__ap[4]), + .C2(n_1_0_1266), .ZN(n_1_0_735) + ); + SDFF_X1_LVT \registers_reg[24][4] ( + .CK(n_0_54), .D(registers[4]), .Q(registers_24__ap[4]), .QN(), .SE(dftIn), + .SI(registers_30__ap[4]) + ); + SDFF_X1_LVT \registers_reg[12][4] ( + .CK(n_0_42), .D(registers[4]), .Q(registers_12__ap[4]), .QN(), .SE(dftIn), + .SI(registers_13__ap[4]) + ); + AOI22_X1_LVT i_1_0_781( + .A1(registers_24__ap[4]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[4]), + .ZN(n_1_0_744) + ); + SDFF_X1_LVT \registers_reg[27][4] ( + .CK(n_0_57), .D(registers[4]), .Q(registers_27__ap[4]), .QN(), .SE(dftIn), + .SI(registers_24__ap[4]) + ); + SDFF_X1_LVT \registers_reg[11][4] ( + .CK(n_0_41), .D(registers[4]), .Q(registers_11__ap[4]), .QN(), .SE(dftIn), + .SI(registers_12__ap[4]) + ); + AOI22_X1_LVT i_1_0_779( + .A1(registers_27__ap[4]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[4]), + .ZN(n_1_0_742) + ); + SDFF_X1_LVT \registers_reg[17][4] ( + .CK(n_0_47), .D(registers[4]), .Q(registers_17__ap[4]), .QN(), .SE(dftIn), + .SI(registers_19__ap[4]) + ); + SDFF_X1_LVT \registers_reg[7][4] ( + .CK(n_0_37), .D(registers[4]), .Q(registers_7__ap[4]), .QN(), .SE(dftIn), + .SI(registers_31__ap[4]) + ); + SDFF_X1_LVT \registers_reg[14][4] ( + .CK(n_0_44), .D(registers[4]), .Q(registers_14__ap[4]), .QN(), .SE(dftIn), + .SI(registers_11__ap[4]) + ); + AOI222_X1_LVT i_1_0_771( + .A1(registers_17__ap[4]), .A2(n_1_0_1271), .B1(n_1_0_1263), .B2(registers_7__ap[4]), + .C1(n_1_0_1258), .C2(registers_14__ap[4]), .ZN(n_1_0_734) + ); + SDFF_X1_LVT \registers_reg[15][4] ( + .CK(n_0_45), .D(registers[4]), .Q(registers_15__ap[4]), .QN(), .SE(dftIn), + .SI(registers_14__ap[4]) + ); + SDFF_X1_LVT \registers_reg[16][4] ( + .CK(n_0_46), .D(registers[4]), .Q(registers_16__ap[4]), .QN(), .SE(dftIn), + .SI(registers_15__ap[4]) + ); + AOI22_X1_LVT i_1_0_770( + .A1(registers_15__ap[4]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[4]), + .ZN(n_1_0_733) + ); + SDFF_X1_LVT \registers_reg[4][4] ( + .CK(n_0_34), .D(registers[4]), .Q(registers_4__ap[4]), .QN(), .SE(dftIn), + .SI(registers_7__ap[4]) + ); + SDFF_X1_LVT \registers_reg[25][4] ( + .CK(n_0_55), .D(registers[4]), .Q(registers_25__ap[4]), .QN(), .SE(dftIn), + .SI(registers_27__ap[4]) + ); + AOI22_X1_LVT i_1_0_769( + .A1(registers_4__ap[4]), .A2(n_1_0_1278), .B1(n_1_0_1269), .B2(registers_25__ap[4]), + .ZN(n_1_0_732) + ); + SDFF_X1_LVT \registers_reg[29][4] ( + .CK(n_0_59), .D(registers[4]), .Q(registers_29__ap[4]), .QN(), .SE(dftIn), + .SI(registers_25__ap[4]) + ); + SDFF_X1_LVT \registers_reg[2][4] ( + .CK(n_0_32), .D(registers[4]), .Q(registers_2__ap[4]), .QN(), .SE(dftIn), + .SI(registers_29__ap[4]) + ); + AOI22_X1_LVT i_1_0_768( + .A1(registers_29__ap[4]), .A2(n_1_0_1276), .B1(n_1_0_1268), .B2(registers_2__ap[4]), + .ZN(n_1_0_731) + ); + NAND3_X1_LVT i_1_0_767( + .A1(n_1_0_733), .A2(n_1_0_732), .A3(n_1_0_731), .ZN(n_1_0_730) + ); + SDFF_X1_LVT \registers_reg[6][4] ( + .CK(n_0_36), .D(registers[4]), .Q(registers_6__ap[4]), .QN(), .SE(dftIn), + .SI(registers_4__ap[4]) + ); + SDFF_X1_LVT \registers_reg[5][4] ( + .CK(n_0_35), .D(registers[4]), .Q(registers_5__ap[4]), .QN(), .SE(dftIn), + .SI(registers_6__ap[4]) + ); + AOI221_X1_LVT i_1_0_766( + .A(n_1_0_730), .B1(n_1_0_1300), .B2(registers_6__ap[4]), .C1(registers_5__ap[4]), + .C2(n_1_0_1273), .ZN(n_1_0_729) + ); + AND4_X1_LVT i_1_0_765( + .A1(n_1_0_744), .A2(n_1_0_742), .A3(n_1_0_734), .A4(n_1_0_729), .ZN(n_1_0_728) + ); + NAND3_X1_LVT i_1_0_764( + .A1(n_1_0_737), .A2(n_1_0_735), .A3(n_1_0_728), .ZN(RRs1[4]) + ); + AND2_X1_LVT i_0_0_3( + .A1(n_0_0_16), .A2(WRd[3]), .ZN(registers[3]) + ); + SDFF_X1_LVT \registers_reg[28][3] ( + .CK(n_0_58), .D(registers[3]), .Q(registers_28__ap[3]), .QN(), .SE(dftIn), + .SI(registers_2__ap[4]) + ); + SDFF_X1_LVT \registers_reg[17][3] ( + .CK(n_0_47), .D(registers[3]), .Q(registers_17__ap[3]), .QN(), .SE(dftIn), + .SI(registers_17__ap[4]) + ); + AOI22_X1_LVT i_1_0_763( + .A1(registers_28__ap[3]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[3]), + .ZN(n_1_0_727) + ); + SDFF_X1_LVT \registers_reg[10][3] ( + .CK(n_0_40), .D(registers[3]), .Q(registers_10__ap[3]), .QN(), .SE(dftIn), + .SI(registers_16__ap[4]) + ); + SDFF_X1_LVT \registers_reg[26][3] ( + .CK(n_0_56), .D(registers[3]), .Q(registers_26__ap[3]), .QN(), .SE(dftIn), + .SI(registers_28__ap[3]) + ); + SDFF_X1_LVT \registers_reg[8][3] ( + .CK(n_0_38), .D(registers[3]), .Q(registers_8__ap[3]), .QN(), .SE(dftIn), + .SI(registers_5__ap[4]) + ); + AOI222_X1_LVT i_1_0_762( + .A1(registers_10__ap[3]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[3]), + .C1(registers_8__ap[3]), .C2(n_1_0_1282), .ZN(n_1_0_726) + ); + SDFF_X1_LVT \registers_reg[9][3] ( + .CK(n_0_39), .D(registers[3]), .Q(registers_9__ap[3]), .QN(), .SE(dftIn), + .SI(registers_8__ap[3]) + ); + SDFF_X1_LVT \registers_reg[29][3] ( + .CK(n_0_59), .D(registers[3]), .Q(registers_29__ap[3]), .QN(), .SE(dftIn), + .SI(registers_26__ap[3]) + ); + AOI22_X1_LVT i_1_0_761( + .A1(registers_9__ap[3]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[3]), + .ZN(n_1_0_725) + ); + SDFF_X1_LVT \registers_reg[6][3] ( + .CK(n_0_36), .D(registers[3]), .Q(registers_6__ap[3]), .QN(), .SE(dftIn), + .SI(registers_9__ap[3]) + ); + SDFF_X1_LVT \registers_reg[1][3] ( + .CK(n_0_0), .D(registers[3]), .Q(registers_1__ap[3]), .QN(), .SE(dftIn), + .SI(registers_17__ap[3]) + ); + AOI22_X1_LVT i_1_0_760( + .A1(registers_6__ap[3]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[3]), + .ZN(n_1_0_724) + ); + SDFF_X1_LVT \registers_reg[16][3] ( + .CK(n_0_46), .D(registers[3]), .Q(registers_16__ap[3]), .QN(), .SE(dftIn), + .SI(registers_10__ap[3]) + ); + SDFF_X1_LVT \registers_reg[3][3] ( + .CK(n_0_33), .D(registers[3]), .Q(registers_3__ap[3]), .QN(), .SE(dftIn), + .SI(registers_6__ap[3]) + ); + AOI22_X1_LVT i_1_0_759( + .A1(registers_16__ap[3]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[3]), + .ZN(n_1_0_723) + ); + SDFF_X1_LVT \registers_reg[5][3] ( + .CK(n_0_35), .D(registers[3]), .Q(registers_5__ap[3]), .QN(), .SE(dftIn), + .SI(registers_3__ap[3]) + ); + SDFF_X1_LVT \registers_reg[31][3] ( + .CK(n_0_61), .D(registers[3]), .Q(registers_31__ap[3]), .QN(), .SE(dftIn), + .SI(registers_5__ap[3]) + ); + AOI22_X1_LVT i_1_0_758( + .A1(registers_5__ap[3]), .A2(n_1_0_1273), .B1(n_1_0_1266), .B2(registers_31__ap[3]), + .ZN(n_1_0_722) + ); + SDFF_X1_LVT \registers_reg[15][3] ( + .CK(n_0_45), .D(registers[3]), .Q(registers_15__ap[3]), .QN(), .SE(dftIn), + .SI(registers_16__ap[3]) + ); + SDFF_X1_LVT \registers_reg[23][3] ( + .CK(n_0_53), .D(registers[3]), .Q(registers_23__ap[3]), .QN(), .SE(dftIn), + .SI(registers_1__ap[3]) + ); + AOI22_X1_LVT i_1_0_757( + .A1(registers_15__ap[3]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[3]), + .ZN(n_1_0_721) + ); + NAND4_X1_LVT i_1_0_756( + .A1(n_1_0_724), .A2(n_1_0_723), .A3(n_1_0_722), .A4(n_1_0_721), .ZN(n_1_0_720) + ); + SDFF_X1_LVT \registers_reg[18][3] ( + .CK(n_0_48), .D(registers[3]), .Q(registers_18__ap[3]), .QN(), .SE(dftIn), + .SI(registers_23__ap[3]) + ); + SDFF_X1_LVT \registers_reg[30][3] ( + .CK(n_0_60), .D(registers[3]), .Q(registers_30__ap[3]), .QN(), .SE(dftIn), + .SI(registers_29__ap[3]) + ); + AOI22_X1_LVT i_1_0_755( + .A1(registers_18__ap[3]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[3]), + .ZN(n_1_0_719) + ); + SDFF_X1_LVT \registers_reg[20][3] ( + .CK(n_0_50), .D(registers[3]), .Q(registers_20__ap[3]), .QN(), .SE(dftIn), + .SI(registers_18__ap[3]) + ); + SDFF_X1_LVT \registers_reg[4][3] ( + .CK(n_0_34), .D(registers[3]), .Q(registers_4__ap[3]), .QN(), .SE(dftIn), + .SI(registers_31__ap[3]) + ); + AOI22_X1_LVT i_1_0_754( + .A1(registers_20__ap[3]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[3]), + .ZN(n_1_0_718) + ); + SDFF_X1_LVT \registers_reg[22][3] ( + .CK(n_0_52), .D(registers[3]), .Q(registers_22__ap[3]), .QN(), .SE(dftIn), + .SI(registers_20__ap[3]) + ); + SDFF_X1_LVT \registers_reg[21][3] ( + .CK(n_0_51), .D(registers[3]), .Q(registers_21__ap[3]), .QN(), .SE(dftIn), + .SI(registers_22__ap[3]) + ); + AOI22_X1_LVT i_1_0_753( + .A1(registers_22__ap[3]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[3]), + .ZN(n_1_0_717) + ); + SDFF_X1_LVT \registers_reg[24][3] ( + .CK(n_0_54), .D(registers[3]), .Q(registers_24__ap[3]), .QN(), .SE(dftIn), + .SI(registers_30__ap[3]) + ); + SDFF_X1_LVT \registers_reg[12][3] ( + .CK(n_0_42), .D(registers[3]), .Q(registers_12__ap[3]), .QN(), .SE(dftIn), + .SI(registers_15__ap[3]) + ); + AOI22_X1_LVT i_1_0_752( + .A1(registers_24__ap[3]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[3]), + .ZN(n_1_0_716) + ); + NAND4_X1_LVT i_1_0_751( + .A1(n_1_0_719), .A2(n_1_0_718), .A3(n_1_0_717), .A4(n_1_0_716), .ZN(n_1_0_715) + ); + SDFF_X1_LVT \registers_reg[13][3] ( + .CK(n_0_43), .D(registers[3]), .Q(registers_13__ap[3]), .QN(), .SE(dftIn), + .SI(registers_12__ap[3]) + ); + SDFF_X1_LVT \registers_reg[25][3] ( + .CK(n_0_55), .D(registers[3]), .Q(registers_25__ap[3]), .QN(), .SE(dftIn), + .SI(registers_24__ap[3]) + ); + AOI22_X1_LVT i_1_0_750( + .A1(registers_13__ap[3]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[3]), + .ZN(n_1_0_714) + ); + SDFF_X1_LVT \registers_reg[19][3] ( + .CK(n_0_49), .D(registers[3]), .Q(registers_19__ap[3]), .QN(), .SE(dftIn), + .SI(registers_21__ap[3]) + ); + SDFF_X1_LVT \registers_reg[2][3] ( + .CK(n_0_32), .D(registers[3]), .Q(registers_2__ap[3]), .QN(), .SE(dftIn), + .SI(registers_25__ap[3]) + ); + AOI22_X1_LVT i_1_0_749( + .A1(registers_19__ap[3]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[3]), + .ZN(n_1_0_713) + ); + SDFF_X1_LVT \registers_reg[7][3] ( + .CK(n_0_37), .D(registers[3]), .Q(registers_7__ap[3]), .QN(), .SE(dftIn), + .SI(registers_4__ap[3]) + ); + SDFF_X1_LVT \registers_reg[14][3] ( + .CK(n_0_44), .D(registers[3]), .Q(registers_14__ap[3]), .QN(), .SE(dftIn), + .SI(registers_13__ap[3]) + ); + AOI22_X1_LVT i_1_0_748( + .A1(registers_7__ap[3]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[3]), + .ZN(n_1_0_712) + ); + SDFF_X1_LVT \registers_reg[27][3] ( + .CK(n_0_57), .D(registers[3]), .Q(registers_27__ap[3]), .QN(), .SE(dftIn), + .SI(registers_2__ap[3]) + ); + SDFF_X1_LVT \registers_reg[11][3] ( + .CK(n_0_41), .D(registers[3]), .Q(registers_11__ap[3]), .QN(), .SE(dftIn), + .SI(registers_14__ap[3]) + ); + AOI22_X1_LVT i_1_0_747( + .A1(registers_27__ap[3]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[3]), + .ZN(n_1_0_711) + ); + NAND4_X1_LVT i_1_0_746( + .A1(n_1_0_714), .A2(n_1_0_713), .A3(n_1_0_712), .A4(n_1_0_711), .ZN(n_1_0_710) + ); + NOR3_X1_LVT i_1_0_745( + .A1(n_1_0_720), .A2(n_1_0_715), .A3(n_1_0_710), .ZN(n_1_0_709) + ); + NAND4_X1_LVT i_1_0_744( + .A1(n_1_0_727), .A2(n_1_0_726), .A3(n_1_0_725), .A4(n_1_0_709), .ZN(RRs1[3]) + ); + AND2_X1_LVT i_0_0_2( + .A1(n_0_0_16), .A2(WRd[2]), .ZN(registers[2]) + ); + SDFF_X1_LVT \registers_reg[28][2] ( + .CK(n_0_58), .D(registers[2]), .Q(registers_28__ap[2]), .QN(), .SE(dftIn), + .SI(registers_27__ap[3]) + ); + SDFF_X1_LVT \registers_reg[4][2] ( + .CK(n_0_34), .D(registers[2]), .Q(registers_4__ap[2]), .QN(), .SE(dftIn), + .SI(registers_7__ap[3]) + ); + AOI22_X1_LVT i_1_0_740( + .A1(registers_28__ap[2]), .A2(n_1_0_1283), .B1(n_1_0_1278), .B2(registers_4__ap[2]), + .ZN(n_1_0_705) + ); + SDFF_X1_LVT \registers_reg[16][2] ( + .CK(n_0_46), .D(registers[2]), .Q(registers_16__ap[2]), .QN(), .SE(dftIn), + .SI(registers_11__ap[3]) + ); + SDFF_X1_LVT \registers_reg[31][2] ( + .CK(n_0_61), .D(registers[2]), .Q(registers_31__ap[2]), .QN(), .SE(dftIn), + .SI(registers_4__ap[2]) + ); + AOI22_X1_LVT i_1_0_743( + .A1(registers_16__ap[2]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[2]), + .ZN(n_1_0_708) + ); + SDFF_X1_LVT \registers_reg[6][2] ( + .CK(n_0_36), .D(registers[2]), .Q(registers_6__ap[2]), .QN(), .SE(dftIn), + .SI(registers_31__ap[2]) + ); + SDFF_X1_LVT \registers_reg[1][2] ( + .CK(n_0_0), .D(registers[2]), .Q(registers_1__ap[2]), .QN(), .SE(dftIn), + .SI(registers_19__ap[3]) + ); + AOI22_X1_LVT i_1_0_739( + .A1(registers_6__ap[2]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[2]), + .ZN(n_1_0_704) + ); + SDFF_X1_LVT \registers_reg[15][2] ( + .CK(n_0_45), .D(registers[2]), .Q(registers_15__ap[2]), .QN(), .SE(dftIn), + .SI(registers_16__ap[2]) + ); + SDFF_X1_LVT \registers_reg[27][2] ( + .CK(n_0_57), .D(registers[2]), .Q(registers_27__ap[2]), .QN(), .SE(dftIn), + .SI(registers_28__ap[2]) + ); + AOI22_X1_LVT i_1_0_742( + .A1(registers_15__ap[2]), .A2(n_1_0_1286), .B1(n_1_0_1279), .B2(registers_27__ap[2]), + .ZN(n_1_0_707) + ); + INV_X1_LVT i_1_0_741( + .A(n_1_0_707), .ZN(n_1_0_706) + ); + SDFF_X1_LVT \registers_reg[11][2] ( + .CK(n_0_41), .D(registers[2]), .Q(registers_11__ap[2]), .QN(), .SE(dftIn), + .SI(registers_15__ap[2]) + ); + SDFF_X1_LVT \registers_reg[5][2] ( + .CK(n_0_35), .D(registers[2]), .Q(registers_5__ap[2]), .QN(), .SE(dftIn), + .SI(registers_6__ap[2]) + ); + AOI221_X1_LVT i_1_0_738( + .A(n_1_0_706), .B1(n_1_0_1270), .B2(registers_11__ap[2]), .C1(registers_5__ap[2]), + .C2(n_1_0_1273), .ZN(n_1_0_703) + ); + SDFF_X1_LVT \registers_reg[10][2] ( + .CK(n_0_40), .D(registers[2]), .Q(registers_10__ap[2]), .QN(), .SE(dftIn), + .SI(registers_11__ap[2]) + ); + SDFF_X1_LVT \registers_reg[30][2] ( + .CK(n_0_60), .D(registers[2]), .Q(registers_30__ap[2]), .QN(), .SE(dftIn), + .SI(registers_27__ap[2]) + ); + SDFF_X1_LVT \registers_reg[8][2] ( + .CK(n_0_38), .D(registers[2]), .Q(registers_8__ap[2]), .QN(), .SE(dftIn), + .SI(registers_5__ap[2]) + ); + AOI222_X1_LVT i_1_0_737( + .A1(registers_10__ap[2]), .A2(n_1_0_1287), .B1(n_1_0_1272), .B2(registers_30__ap[2]), + .C1(n_1_0_1282), .C2(registers_8__ap[2]), .ZN(n_1_0_702) + ); + NAND4_X1_LVT i_1_0_736( + .A1(n_1_0_708), .A2(n_1_0_704), .A3(n_1_0_703), .A4(n_1_0_702), .ZN(n_1_0_701) + ); + SDFF_X1_LVT \registers_reg[9][2] ( + .CK(n_0_39), .D(registers[2]), .Q(registers_9__ap[2]), .QN(), .SE(dftIn), + .SI(registers_8__ap[2]) + ); + SDFF_X1_LVT \registers_reg[29][2] ( + .CK(n_0_59), .D(registers[2]), .Q(registers_29__ap[2]), .QN(), .SE(dftIn), + .SI(registers_30__ap[2]) + ); + AOI221_X1_LVT i_1_0_735( + .A(n_1_0_701), .B1(n_1_0_1291), .B2(registers_9__ap[2]), .C1(registers_29__ap[2]), + .C2(n_1_0_1276), .ZN(n_1_0_700) + ); + SDFF_X1_LVT \registers_reg[18][2] ( + .CK(n_0_48), .D(registers[2]), .Q(registers_18__ap[2]), .QN(), .SE(dftIn), + .SI(registers_1__ap[2]) + ); + SDFF_X1_LVT \registers_reg[26][2] ( + .CK(n_0_56), .D(registers[2]), .Q(registers_26__ap[2]), .QN(), .SE(dftIn), + .SI(registers_29__ap[2]) + ); + AOI22_X1_LVT i_1_0_734( + .A1(registers_18__ap[2]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[2]), + .ZN(n_1_0_699) + ); + SDFF_X1_LVT \registers_reg[24][2] ( + .CK(n_0_54), .D(registers[2]), .Q(registers_24__ap[2]), .QN(), .SE(dftIn), + .SI(registers_26__ap[2]) + ); + SDFF_X1_LVT \registers_reg[12][2] ( + .CK(n_0_42), .D(registers[2]), .Q(registers_12__ap[2]), .QN(), .SE(dftIn), + .SI(registers_10__ap[2]) + ); + AOI22_X1_LVT i_1_0_733( + .A1(registers_24__ap[2]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[2]), + .ZN(n_1_0_698) + ); + SDFF_X1_LVT \registers_reg[22][2] ( + .CK(n_0_52), .D(registers[2]), .Q(registers_22__ap[2]), .QN(), .SE(dftIn), + .SI(registers_18__ap[2]) + ); + SDFF_X1_LVT \registers_reg[21][2] ( + .CK(n_0_51), .D(registers[2]), .Q(registers_21__ap[2]), .QN(), .SE(dftIn), + .SI(registers_22__ap[2]) + ); + AOI22_X1_LVT i_1_0_732( + .A1(registers_22__ap[2]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[2]), + .ZN(n_1_0_697) + ); + NAND3_X1_LVT i_1_0_731( + .A1(n_1_0_699), .A2(n_1_0_698), .A3(n_1_0_697), .ZN(n_1_0_696) + ); + SDFF_X1_LVT \registers_reg[17][2] ( + .CK(n_0_47), .D(registers[2]), .Q(registers_17__ap[2]), .QN(), .SE(dftIn), + .SI(registers_21__ap[2]) + ); + SDFF_X1_LVT \registers_reg[20][2] ( + .CK(n_0_50), .D(registers[2]), .Q(registers_20__ap[2]), .QN(), .SE(dftIn), + .SI(registers_17__ap[2]) + ); + AOI221_X1_LVT i_1_0_730( + .A(n_1_0_696), .B1(n_1_0_1271), .B2(registers_17__ap[2]), .C1(registers_20__ap[2]), + .C2(n_1_0_1281), .ZN(n_1_0_695) + ); + SDFF_X1_LVT \registers_reg[13][2] ( + .CK(n_0_43), .D(registers[2]), .Q(registers_13__ap[2]), .QN(), .SE(dftIn), + .SI(registers_12__ap[2]) + ); + SDFF_X1_LVT \registers_reg[25][2] ( + .CK(n_0_55), .D(registers[2]), .Q(registers_25__ap[2]), .QN(), .SE(dftIn), + .SI(registers_24__ap[2]) + ); + AOI22_X1_LVT i_1_0_729( + .A1(registers_13__ap[2]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[2]), + .ZN(n_1_0_694) + ); + SDFF_X1_LVT \registers_reg[7][2] ( + .CK(n_0_37), .D(registers[2]), .Q(registers_7__ap[2]), .QN(), .SE(dftIn), + .SI(registers_9__ap[2]) + ); + SDFF_X1_LVT \registers_reg[14][2] ( + .CK(n_0_44), .D(registers[2]), .Q(registers_14__ap[2]), .QN(), .SE(dftIn), + .SI(registers_13__ap[2]) + ); + AOI22_X1_LVT i_1_0_728( + .A1(registers_7__ap[2]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[2]), + .ZN(n_1_0_693) + ); + SDFF_X1_LVT \registers_reg[19][2] ( + .CK(n_0_49), .D(registers[2]), .Q(registers_19__ap[2]), .QN(), .SE(dftIn), + .SI(registers_20__ap[2]) + ); + SDFF_X1_LVT \registers_reg[3][2] ( + .CK(n_0_33), .D(registers[2]), .Q(registers_3__ap[2]), .QN(), .SE(dftIn), + .SI(registers_7__ap[2]) + ); + AOI22_X1_LVT i_1_0_727( + .A1(registers_19__ap[2]), .A2(n_1_0_1295), .B1(n_1_0_1257), .B2(registers_3__ap[2]), + .ZN(n_1_0_692) + ); + NAND3_X1_LVT i_1_0_726( + .A1(n_1_0_694), .A2(n_1_0_693), .A3(n_1_0_692), .ZN(n_1_0_691) + ); + SDFF_X1_LVT \registers_reg[23][2] ( + .CK(n_0_53), .D(registers[2]), .Q(registers_23__ap[2]), .QN(), .SE(dftIn), + .SI(registers_19__ap[2]) + ); + SDFF_X1_LVT \registers_reg[2][2] ( + .CK(n_0_32), .D(registers[2]), .Q(registers_2__ap[2]), .QN(), .SE(dftIn), + .SI(registers_25__ap[2]) + ); + AOI221_X1_LVT i_1_0_725( + .A(n_1_0_691), .B1(n_1_0_1264), .B2(registers_23__ap[2]), .C1(registers_2__ap[2]), + .C2(n_1_0_1268), .ZN(n_1_0_690) + ); + NAND4_X1_LVT i_1_0_724( + .A1(n_1_0_705), .A2(n_1_0_700), .A3(n_1_0_695), .A4(n_1_0_690), .ZN(RRs1[2]) + ); + AND2_X1_LVT i_0_0_1( + .A1(n_0_0_16), .A2(WRd[1]), .ZN(registers[1]) + ); + SDFF_X1_LVT \registers_reg[13][1] ( + .CK(n_0_43), .D(registers[1]), .Q(registers_13__ap[1]), .QN(), .SE(dftIn), + .SI(registers_14__ap[2]) + ); + SDFF_X1_LVT \registers_reg[21][1] ( + .CK(n_0_51), .D(registers[1]), .Q(registers_21__ap[1]), .QN(), .SE(dftIn), + .SI(registers_23__ap[2]) + ); + AOI22_X1_LVT i_1_0_720( + .A1(registers_13__ap[1]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[1]), + .ZN(n_1_0_686) + ); + SDFF_X1_LVT \registers_reg[29][1] ( + .CK(n_0_59), .D(registers[1]), .Q(registers_29__ap[1]), .QN(), .SE(dftIn), + .SI(registers_2__ap[2]) + ); + SDFF_X1_LVT \registers_reg[23][1] ( + .CK(n_0_53), .D(registers[1]), .Q(registers_23__ap[1]), .QN(), .SE(dftIn), + .SI(registers_21__ap[1]) + ); + AOI22_X1_LVT i_1_0_723( + .A1(registers_29__ap[1]), .A2(n_1_0_1276), .B1(n_1_0_1264), .B2(registers_23__ap[1]), + .ZN(n_1_0_689) + ); + SDFF_X1_LVT \registers_reg[24][1] ( + .CK(n_0_54), .D(registers[1]), .Q(registers_24__ap[1]), .QN(), .SE(dftIn), + .SI(registers_29__ap[1]) + ); + SDFF_X1_LVT \registers_reg[20][1] ( + .CK(n_0_50), .D(registers[1]), .Q(registers_20__ap[1]), .QN(), .SE(dftIn), + .SI(registers_23__ap[1]) + ); + AOI22_X1_LVT i_1_0_719( + .A1(registers_24__ap[1]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[1]), + .ZN(n_1_0_685) + ); + SDFF_X1_LVT \registers_reg[7][1] ( + .CK(n_0_37), .D(registers[1]), .Q(registers_7__ap[1]), .QN(), .SE(dftIn), + .SI(registers_3__ap[2]) + ); + SDFF_X1_LVT \registers_reg[3][1] ( + .CK(n_0_33), .D(registers[1]), .Q(registers_3__ap[1]), .QN(), .SE(dftIn), + .SI(registers_7__ap[1]) + ); + AOI22_X1_LVT i_1_0_722( + .A1(registers_7__ap[1]), .A2(n_1_0_1263), .B1(n_1_0_1257), .B2(registers_3__ap[1]), + .ZN(n_1_0_688) + ); + INV_X1_LVT i_1_0_721( + .A(n_1_0_688), .ZN(n_1_0_687) + ); + SDFF_X1_LVT \registers_reg[31][1] ( + .CK(n_0_61), .D(registers[1]), .Q(registers_31__ap[1]), .QN(), .SE(dftIn), + .SI(registers_3__ap[1]) + ); + SDFF_X1_LVT \registers_reg[4][1] ( + .CK(n_0_34), .D(registers[1]), .Q(registers_4__ap[1]), .QN(), .SE(dftIn), + .SI(registers_31__ap[1]) + ); + AOI221_X1_LVT i_1_0_718( + .A(n_1_0_687), .B1(n_1_0_1266), .B2(registers_31__ap[1]), .C1(registers_4__ap[1]), + .C2(n_1_0_1278), .ZN(n_1_0_684) + ); + SDFF_X1_LVT \registers_reg[10][1] ( + .CK(n_0_40), .D(registers[1]), .Q(registers_10__ap[1]), .QN(), .SE(dftIn), + .SI(registers_13__ap[1]) + ); + SDFF_X1_LVT \registers_reg[26][1] ( + .CK(n_0_56), .D(registers[1]), .Q(registers_26__ap[1]), .QN(), .SE(dftIn), + .SI(registers_24__ap[1]) + ); + SDFF_X1_LVT \registers_reg[25][1] ( + .CK(n_0_55), .D(registers[1]), .Q(registers_25__ap[1]), .QN(), .SE(dftIn), + .SI(registers_26__ap[1]) + ); + AOI222_X1_LVT i_1_0_717( + .A1(registers_10__ap[1]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[1]), + .C1(registers_25__ap[1]), .C2(n_1_0_1269), .ZN(n_1_0_683) + ); + NAND4_X1_LVT i_1_0_716( + .A1(n_1_0_689), .A2(n_1_0_685), .A3(n_1_0_684), .A4(n_1_0_683), .ZN(n_1_0_682) + ); + SDFF_X1_LVT \registers_reg[8][1] ( + .CK(n_0_38), .D(registers[1]), .Q(registers_8__ap[1]), .QN(), .SE(dftIn), + .SI(registers_4__ap[1]) + ); + SDFF_X1_LVT \registers_reg[28][1] ( + .CK(n_0_58), .D(registers[1]), .Q(registers_28__ap[1]), .QN(), .SE(dftIn), + .SI(registers_25__ap[1]) + ); + AOI221_X1_LVT i_1_0_715( + .A(n_1_0_682), .B1(n_1_0_1282), .B2(registers_8__ap[1]), .C1(registers_28__ap[1]), + .C2(n_1_0_1283), .ZN(n_1_0_681) + ); + SDFF_X1_LVT \registers_reg[18][1] ( + .CK(n_0_48), .D(registers[1]), .Q(registers_18__ap[1]), .QN(), .SE(dftIn), + .SI(registers_20__ap[1]) + ); + SDFF_X1_LVT \registers_reg[30][1] ( + .CK(n_0_60), .D(registers[1]), .Q(registers_30__ap[1]), .QN(), .SE(dftIn), + .SI(registers_28__ap[1]) + ); + AOI22_X1_LVT i_1_0_714( + .A1(registers_18__ap[1]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[1]), + .ZN(n_1_0_680) + ); + SDFF_X1_LVT \registers_reg[17][1] ( + .CK(n_0_47), .D(registers[1]), .Q(registers_17__ap[1]), .QN(), .SE(dftIn), + .SI(registers_18__ap[1]) + ); + SDFF_X1_LVT \registers_reg[12][1] ( + .CK(n_0_42), .D(registers[1]), .Q(registers_12__ap[1]), .QN(), .SE(dftIn), + .SI(registers_10__ap[1]) + ); + AOI22_X1_LVT i_1_0_713( + .A1(registers_17__ap[1]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[1]), + .ZN(n_1_0_679) + ); + SDFF_X1_LVT \registers_reg[15][1] ( + .CK(n_0_45), .D(registers[1]), .Q(registers_15__ap[1]), .QN(), .SE(dftIn), + .SI(registers_12__ap[1]) + ); + SDFF_X1_LVT \registers_reg[5][1] ( + .CK(n_0_35), .D(registers[1]), .Q(registers_5__ap[1]), .QN(), .SE(dftIn), + .SI(registers_8__ap[1]) + ); + AOI22_X1_LVT i_1_0_712( + .A1(registers_15__ap[1]), .A2(n_1_0_1286), .B1(n_1_0_1273), .B2(registers_5__ap[1]), + .ZN(n_1_0_678) + ); + NAND3_X1_LVT i_1_0_711( + .A1(n_1_0_680), .A2(n_1_0_679), .A3(n_1_0_678), .ZN(n_1_0_677) + ); + SDFF_X1_LVT \registers_reg[22][1] ( + .CK(n_0_52), .D(registers[1]), .Q(registers_22__ap[1]), .QN(), .SE(dftIn), + .SI(registers_17__ap[1]) + ); + SDFF_X1_LVT \registers_reg[16][1] ( + .CK(n_0_46), .D(registers[1]), .Q(registers_16__ap[1]), .QN(), .SE(dftIn), + .SI(registers_15__ap[1]) + ); + AOI221_X1_LVT i_1_0_710( + .A(n_1_0_677), .B1(n_1_0_1294), .B2(registers_22__ap[1]), .C1(registers_16__ap[1]), + .C2(n_1_0_1267), .ZN(n_1_0_676) + ); + SDFF_X1_LVT \registers_reg[9][1] ( + .CK(n_0_39), .D(registers[1]), .Q(registers_9__ap[1]), .QN(), .SE(dftIn), + .SI(registers_5__ap[1]) + ); + SDFF_X1_LVT \registers_reg[1][1] ( + .CK(n_0_0), .D(registers[1]), .Q(registers_1__ap[1]), .QN(), .SE(dftIn), + .SI(registers_22__ap[1]) + ); + AOI22_X1_LVT i_1_0_709( + .A1(registers_9__ap[1]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[1]), + .ZN(n_1_0_675) + ); + SDFF_X1_LVT \registers_reg[6][1] ( + .CK(n_0_36), .D(registers[1]), .Q(registers_6__ap[1]), .QN(), .SE(dftIn), + .SI(registers_9__ap[1]) + ); + SDFF_X1_LVT \registers_reg[14][1] ( + .CK(n_0_44), .D(registers[1]), .Q(registers_14__ap[1]), .QN(), .SE(dftIn), + .SI(registers_16__ap[1]) + ); + AOI22_X1_LVT i_1_0_708( + .A1(registers_6__ap[1]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[1]), + .ZN(n_1_0_674) + ); + SDFF_X1_LVT \registers_reg[19][1] ( + .CK(n_0_49), .D(registers[1]), .Q(registers_19__ap[1]), .QN(), .SE(dftIn), + .SI(registers_1__ap[1]) + ); + SDFF_X1_LVT \registers_reg[2][1] ( + .CK(n_0_32), .D(registers[1]), .Q(registers_2__ap[1]), .QN(), .SE(dftIn), + .SI(registers_30__ap[1]) + ); + AOI22_X1_LVT i_1_0_707( + .A1(registers_19__ap[1]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[1]), + .ZN(n_1_0_673) + ); + NAND3_X1_LVT i_1_0_706( + .A1(n_1_0_675), .A2(n_1_0_674), .A3(n_1_0_673), .ZN(n_1_0_672) + ); + SDFF_X1_LVT \registers_reg[11][1] ( + .CK(n_0_41), .D(registers[1]), .Q(registers_11__ap[1]), .QN(), .SE(dftIn), + .SI(registers_14__ap[1]) + ); + SDFF_X1_LVT \registers_reg[27][1] ( + .CK(n_0_57), .D(registers[1]), .Q(registers_27__ap[1]), .QN(), .SE(dftIn), + .SI(registers_2__ap[1]) + ); + AOI221_X1_LVT i_1_0_705( + .A(n_1_0_672), .B1(n_1_0_1270), .B2(registers_11__ap[1]), .C1(registers_27__ap[1]), + .C2(n_1_0_1279), .ZN(n_1_0_671) + ); + NAND4_X1_LVT i_1_0_704( + .A1(n_1_0_686), .A2(n_1_0_681), .A3(n_1_0_676), .A4(n_1_0_671), .ZN(RRs1[1]) + ); + AND2_X1_LVT i_0_0_0( + .A1(n_0_0_16), .A2(WRd[0]), .ZN(registers[0]) + ); + SDFF_X1_LVT \registers_reg[13][0] ( + .CK(n_0_43), .D(registers[0]), .Q(registers_13__ap[0]), .QN(), .SE(dftIn), + .SI(registers_11__ap[1]) + ); + SDFF_X1_LVT \registers_reg[21][0] ( + .CK(n_0_51), .D(registers[0]), .Q(registers_21__ap[0]), .QN(), .SE(dftIn), + .SI(registers_19__ap[1]) + ); + AOI22_X1_LVT i_1_0_703( + .A1(registers_13__ap[0]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[0]), + .ZN(n_1_0_670) + ); + SDFF_X1_LVT \registers_reg[10][0] ( + .CK(n_0_40), .D(registers[0]), .Q(registers_10__ap[0]), .QN(), .SE(dftIn), + .SI(registers_13__ap[0]) + ); + SDFF_X1_LVT \registers_reg[26][0] ( + .CK(n_0_56), .D(registers[0]), .Q(registers_26__ap[0]), .QN(), .SE(dftIn), + .SI(registers_27__ap[1]) + ); + SDFF_X1_LVT \registers_reg[25][0] ( + .CK(n_0_55), .D(registers[0]), .Q(registers_25__ap[0]), .QN(), .SE(dftIn), + .SI(registers_26__ap[0]) + ); + AOI222_X1_LVT i_1_0_702( + .A1(registers_10__ap[0]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[0]), + .C1(registers_25__ap[0]), .C2(n_1_0_1269), .ZN(n_1_0_669) + ); + SDFF_X1_LVT \registers_reg[28][0] ( + .CK(n_0_58), .D(registers[0]), .Q(registers_28__ap[0]), .QN(), .SE(dftIn), + .SI(registers_25__ap[0]) + ); + SDFF_X1_LVT \registers_reg[8][0] ( + .CK(n_0_38), .D(registers[0]), .Q(registers_8__ap[0]), .QN(), .SE(dftIn), + .SI(registers_6__ap[1]) + ); + AOI22_X1_LVT i_1_0_701( + .A1(registers_28__ap[0]), .A2(n_1_0_1283), .B1(n_1_0_1282), .B2(registers_8__ap[0]), + .ZN(n_1_0_668) + ); + SDFF_X1_LVT \registers_reg[24][0] ( + .CK(n_0_54), .D(registers[0]), .Q(registers_24__ap[0]), .QN(), .SE(dftIn), + .SI(registers_28__ap[0]) + ); + SDFF_X1_LVT \registers_reg[20][0] ( + .CK(n_0_50), .D(registers[0]), .Q(registers_20__ap[0]), .QN(), .SE(dftIn), + .SI(registers_21__ap[0]) + ); + AOI22_X1_LVT i_1_0_700( + .A1(registers_24__ap[0]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[0]), + .ZN(n_1_0_667) + ); + SDFF_X1_LVT \registers_reg[7][0] ( + .CK(n_0_37), .D(registers[0]), .Q(registers_7__ap[0]), .QN(), .SE(dftIn), + .SI(registers_8__ap[0]) + ); + SDFF_X1_LVT \registers_reg[3][0] ( + .CK(n_0_33), .D(registers[0]), .Q(registers_3__ap[0]), .QN(), .SE(dftIn), + .SI(registers_7__ap[0]) + ); + AOI22_X1_LVT i_1_0_699( + .A1(registers_7__ap[0]), .A2(n_1_0_1263), .B1(n_1_0_1257), .B2(registers_3__ap[0]), + .ZN(n_1_0_666) + ); + SDFF_X1_LVT \registers_reg[17][0] ( + .CK(n_0_47), .D(registers[0]), .Q(registers_17__ap[0]), .QN(), .SE(dftIn), + .SI(registers_20__ap[0]) + ); + SDFF_X1_LVT \registers_reg[31][0] ( + .CK(n_0_61), .D(registers[0]), .Q(registers_31__ap[0]), .QN(), .SE(dftIn), + .SI(registers_3__ap[0]) + ); + AOI22_X1_LVT i_1_0_698( + .A1(registers_17__ap[0]), .A2(n_1_0_1271), .B1(n_1_0_1266), .B2(registers_31__ap[0]), + .ZN(n_1_0_665) + ); + SDFF_X1_LVT \registers_reg[29][0] ( + .CK(n_0_59), .D(registers[0]), .Q(registers_29__ap[0]), .QN(), .SE(dftIn), + .SI(registers_24__ap[0]) + ); + SDFF_X1_LVT \registers_reg[23][0] ( + .CK(n_0_53), .D(registers[0]), .Q(registers_23__ap[0]), .QN(), .SE(dftIn), + .SI(registers_17__ap[0]) + ); + AOI22_X1_LVT i_1_0_697( + .A1(registers_29__ap[0]), .A2(n_1_0_1276), .B1(n_1_0_1264), .B2(registers_23__ap[0]), + .ZN(n_1_0_664) + ); + NAND4_X1_LVT i_1_0_696( + .A1(n_1_0_667), .A2(n_1_0_666), .A3(n_1_0_665), .A4(n_1_0_664), .ZN(n_1_0_663) + ); + SDFF_X1_LVT \registers_reg[18][0] ( + .CK(n_0_48), .D(registers[0]), .Q(registers_18__ap[0]), .QN(), .SE(dftIn), + .SI(registers_23__ap[0]) + ); + SDFF_X1_LVT \registers_reg[30][0] ( + .CK(n_0_60), .D(registers[0]), .Q(registers_30__ap[0]), .QN(), .SE(dftIn), + .SI(registers_29__ap[0]) + ); + AOI22_X1_LVT i_1_0_695( + .A1(registers_18__ap[0]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[0]), + .ZN(n_1_0_662) + ); + SDFF_X1_LVT \registers_reg[4][0] ( + .CK(n_0_34), .D(registers[0]), .Q(registers_4__ap[0]), .QN(), .SE(dftIn), + .SI(registers_31__ap[0]) + ); + SDFF_X1_LVT \registers_reg[12][0] ( + .CK(n_0_42), .D(registers[0]), .Q(registers_12__ap[0]), .QN(), .SE(dftIn), + .SI(registers_10__ap[0]) + ); + AOI22_X1_LVT i_1_0_694( + .A1(registers_4__ap[0]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[0]), + .ZN(n_1_0_661) + ); + SDFF_X1_LVT \registers_reg[15][0] ( + .CK(n_0_45), .D(registers[0]), .Q(registers_15__ap[0]), .QN(), .SE(dftIn), + .SI(registers_12__ap[0]) + ); + SDFF_X1_LVT \registers_reg[16][0] ( + .CK(n_0_46), .D(registers[0]), .Q(registers_16__ap[0]), .QN(), .SE(dftIn), + .SI(registers_15__ap[0]) + ); + AOI22_X1_LVT i_1_0_693( + .A1(registers_15__ap[0]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[0]), + .ZN(n_1_0_660) + ); + SDFF_X1_LVT \registers_reg[22][0] ( + .CK(n_0_52), .D(registers[0]), .Q(registers_22__ap[0]), .QN(), .SE(dftIn), + .SI(registers_18__ap[0]) + ); + SDFF_X1_LVT \registers_reg[5][0] ( + .CK(n_0_35), .D(registers[0]), .Q(registers_5__ap[0]), .QN(), .SE(dftIn), + .SI(registers_4__ap[0]) + ); + AOI22_X1_LVT i_1_0_692( + .A1(registers_22__ap[0]), .A2(n_1_0_1294), .B1(n_1_0_1273), .B2(registers_5__ap[0]), + .ZN(n_1_0_659) + ); + NAND4_X1_LVT i_1_0_691( + .A1(n_1_0_662), .A2(n_1_0_661), .A3(n_1_0_660), .A4(n_1_0_659), .ZN(n_1_0_658) + ); + SDFF_X1_LVT \registers_reg[19][0] ( + .CK(n_0_49), .D(registers[0]), .Q(registers_19__ap[0]), .QN(), .SE(dftIn), + .SI(registers_22__ap[0]) + ); + SDFF_X1_LVT \registers_reg[2][0] ( + .CK(n_0_32), .D(registers[0]), .Q(registers_2__ap[0]), .QN(), .SE(dftIn), + .SI(registers_30__ap[0]) + ); + AOI22_X1_LVT i_1_0_690( + .A1(registers_19__ap[0]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[0]), + .ZN(n_1_0_657) + ); + SDFF_X1_LVT \registers_reg[9][0] ( + .CK(n_0_39), .D(registers[0]), .Q(registers_9__ap[0]), .QN(), .SE(dftIn), + .SI(registers_5__ap[0]) + ); + SDFF_X1_LVT \registers_reg[1][0] ( + .CK(n_0_0), .D(registers[0]), .Q(registers_1__ap[0]), .QN(), .SE(dftIn), + .SI(registers_19__ap[0]) + ); + AOI22_X1_LVT i_1_0_689( + .A1(registers_9__ap[0]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[0]), + .ZN(n_1_0_656) + ); + SDFF_X1_LVT \registers_reg[6][0] ( + .CK(n_0_36), .D(registers[0]), .Q(registers_6__ap[0]), .QN(), .SE(dftIn), + .SI(registers_9__ap[0]) + ); + SDFF_X1_LVT \registers_reg[14][0] ( + .CK(n_0_44), .D(registers[0]), .Q(registers_14__ap[0]), .QN(), .SE(dftIn), + .SI(registers_16__ap[0]) + ); + AOI22_X1_LVT i_1_0_688( + .A1(registers_6__ap[0]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[0]), + .ZN(n_1_0_655) + ); + SDFF_X1_LVT \registers_reg[27][0] ( + .CK(n_0_57), .D(registers[0]), .Q(registers_27__ap[0]), .QN(), .SE(dftIn), + .SI(registers_2__ap[0]) + ); + SDFF_X1_LVT \registers_reg[11][0] ( + .CK(n_0_41), .D(registers[0]), .Q(registers_11__ap[0]), .QN(), .SE(dftIn), + .SI(registers_14__ap[0]) + ); + AOI22_X1_LVT i_1_0_687( + .A1(registers_27__ap[0]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[0]), + .ZN(n_1_0_654) + ); + NAND4_X1_LVT i_1_0_686( + .A1(n_1_0_657), .A2(n_1_0_656), .A3(n_1_0_655), .A4(n_1_0_654), .ZN(n_1_0_653) + ); + NOR3_X1_LVT i_1_0_685( + .A1(n_1_0_663), .A2(n_1_0_658), .A3(n_1_0_653), .ZN(n_1_0_652) + ); + NAND4_X1_LVT i_1_0_684( + .A1(n_1_0_670), .A2(n_1_0_669), .A3(n_1_0_668), .A4(n_1_0_652), .ZN(RRs1[0]) + ); + INV_X1_LVT i_1_0_1366( + .A(Rs2[1]), .ZN(n_1_0_1302) + ); + NAND3_X1_LVT i_1_0_683( + .A1(n_1_0_1302), .A2(Rs2[4]), .A3(Rs2[2]), .ZN(n_1_0_651) + ); + INV_X1_LVT i_1_0_1369( + .A(Rs2[3]), .ZN(n_1_0_1305) + ); + OR2_X1_LVT i_1_0_673( + .A1(n_1_0_1305), .A2(Rs2[0]), .ZN(n_1_0_641) + ); + NOR2_X1_LVT i_1_0_666( + .A1(n_1_0_651), .A2(n_1_0_641), .ZN(n_1_0_634) + ); + NAND2_X1_LVT i_1_0_677( + .A1(n_1_0_1305), .A2(Rs2[0]), .ZN(n_1_0_645) + ); + INV_X1_LVT i_1_0_1368( + .A(Rs2[2]), .ZN(n_1_0_1304) + ); + NAND3_X1_LVT i_1_0_662( + .A1(n_1_0_1304), .A2(n_1_0_1302), .A3(Rs2[4]), .ZN(n_1_0_630) + ); + NOR2_X1_LVT i_1_0_661( + .A1(n_1_0_645), .A2(n_1_0_630), .ZN(n_1_0_629) + ); + AOI22_X1_LVT i_1_0_641( + .A1(registers_28__ap[31]), .A2(n_1_0_634), .B1(n_1_0_629), .B2(registers_17__ap[31]), + .ZN(n_1_0_609) + ); + NAND3_X1_LVT i_1_0_680( + .A1(n_1_0_1304), .A2(Rs2[4]), .A3(Rs2[1]), .ZN(n_1_0_648) + ); + NOR2_X1_LVT i_1_0_672( + .A1(n_1_0_648), .A2(n_1_0_641), .ZN(n_1_0_640) + ); + INV_X1_LVT i_1_0_1367( + .A(Rs2[4]), .ZN(n_1_0_1303) + ); + NAND3_X1_LVT i_1_0_657( + .A1(n_1_0_1304), .A2(n_1_0_1303), .A3(Rs2[1]), .ZN(n_1_0_625) + ); + NOR2_X1_LVT i_1_0_656( + .A1(n_1_0_641), .A2(n_1_0_625), .ZN(n_1_0_624) + ); + NOR4_X1_LVT i_1_0_658( + .A1(n_1_0_641), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), .ZN(n_1_0_626) + ); + AOI222_X1_LVT i_1_0_640( + .A1(registers_26__ap[31]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[31]), + .C1(n_1_0_626), .C2(registers_8__ap[31]), .ZN(n_1_0_608) + ); + NAND2_X1_LVT i_1_0_682( + .A1(Rs2[0]), .A2(Rs2[3]), .ZN(n_1_0_650) + ); + NOR2_X1_LVT i_1_0_681( + .A1(n_1_0_651), .A2(n_1_0_650), .ZN(n_1_0_649) + ); + NOR4_X1_LVT i_1_0_649( + .A1(n_1_0_650), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), .ZN(n_1_0_617) + ); + AOI22_X1_LVT i_1_0_639( + .A1(registers_29__ap[31]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[31]), + .ZN(n_1_0_607) + ); + NOR4_X1_LVT i_1_0_676( + .A1(n_1_0_645), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), .ZN(n_1_0_644) + ); + OR2_X1_LVT i_1_0_679( + .A1(Rs2[0]), .A2(Rs2[3]), .ZN(n_1_0_647) + ); + NAND3_X1_LVT i_1_0_660( + .A1(n_1_0_1303), .A2(Rs2[1]), .A3(Rs2[2]), .ZN(n_1_0_628) + ); + NOR2_X1_LVT i_1_0_648( + .A1(n_1_0_647), .A2(n_1_0_628), .ZN(n_1_0_616) + ); + AOI22_X1_LVT i_1_0_638( + .A1(registers_1__ap[31]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[31]), + .ZN(n_1_0_606) + ); + NOR2_X1_LVT i_1_0_655( + .A1(n_1_0_645), .A2(n_1_0_628), .ZN(n_1_0_623) + ); + NAND3_X1_LVT i_1_0_675( + .A1(Rs2[2]), .A2(Rs2[4]), .A3(Rs2[1]), .ZN(n_1_0_643) + ); + NOR2_X1_LVT i_1_0_647( + .A1(n_1_0_645), .A2(n_1_0_643), .ZN(n_1_0_615) + ); + AOI22_X1_LVT i_1_0_637( + .A1(registers_7__ap[31]), .A2(n_1_0_623), .B1(n_1_0_615), .B2(registers_23__ap[31]), + .ZN(n_1_0_605) + ); + NOR2_X1_LVT i_1_0_665( + .A1(n_1_0_648), .A2(n_1_0_645), .ZN(n_1_0_633) + ); + NOR2_X1_LVT i_1_0_646( + .A1(n_1_0_647), .A2(n_1_0_630), .ZN(n_1_0_614) + ); + AOI22_X1_LVT i_1_0_636( + .A1(registers_19__ap[31]), .A2(n_1_0_633), .B1(n_1_0_614), .B2(registers_16__ap[31]), + .ZN(n_1_0_604) + ); + NOR2_X1_LVT i_1_0_669( + .A1(n_1_0_650), .A2(n_1_0_643), .ZN(n_1_0_637) + ); + NAND3_X1_LVT i_1_0_671( + .A1(n_1_0_1303), .A2(n_1_0_1302), .A3(Rs2[2]), .ZN(n_1_0_639) + ); + NOR2_X1_LVT i_1_0_667( + .A1(n_1_0_645), .A2(n_1_0_639), .ZN(n_1_0_635) + ); + AOI22_X1_LVT i_1_0_635( + .A1(registers_31__ap[31]), .A2(n_1_0_637), .B1(n_1_0_635), .B2(registers_5__ap[31]), + .ZN(n_1_0_603) + ); + NAND4_X1_LVT i_1_0_634( + .A1(n_1_0_606), .A2(n_1_0_605), .A3(n_1_0_604), .A4(n_1_0_603), .ZN(n_1_0_602) + ); + NOR2_X1_LVT i_1_0_678( + .A1(n_1_0_648), .A2(n_1_0_647), .ZN(n_1_0_646) + ); + NOR2_X1_LVT i_1_0_654( + .A1(n_1_0_643), .A2(n_1_0_641), .ZN(n_1_0_622) + ); + AOI22_X1_LVT i_1_0_633( + .A1(registers_18__ap[31]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[31]), + .ZN(n_1_0_601) + ); + NOR2_X1_LVT i_1_0_670( + .A1(n_1_0_647), .A2(n_1_0_639), .ZN(n_1_0_638) + ); + NOR2_X1_LVT i_1_0_645( + .A1(n_1_0_651), .A2(n_1_0_647), .ZN(n_1_0_613) + ); + AOI22_X1_LVT i_1_0_632( + .A1(registers_4__ap[31]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[31]), + .ZN(n_1_0_600) + ); + NOR2_X1_LVT i_1_0_674( + .A1(n_1_0_647), .A2(n_1_0_643), .ZN(n_1_0_642) + ); + NOR2_X1_LVT i_1_0_644( + .A1(n_1_0_651), .A2(n_1_0_645), .ZN(n_1_0_612) + ); + AOI22_X1_LVT i_1_0_631( + .A1(registers_22__ap[31]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[31]), + .ZN(n_1_0_599) + ); + NOR2_X1_LVT i_1_0_664( + .A1(n_1_0_641), .A2(n_1_0_639), .ZN(n_1_0_632) + ); + NOR2_X1_LVT i_1_0_653( + .A1(n_1_0_641), .A2(n_1_0_630), .ZN(n_1_0_621) + ); + AOI22_X1_LVT i_1_0_630( + .A1(registers_12__ap[31]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[31]), + .ZN(n_1_0_598) + ); + NAND4_X1_LVT i_1_0_629( + .A1(n_1_0_601), .A2(n_1_0_600), .A3(n_1_0_599), .A4(n_1_0_598), .ZN(n_1_0_597) + ); + NOR2_X1_LVT i_1_0_663( + .A1(n_1_0_650), .A2(n_1_0_639), .ZN(n_1_0_631) + ); + NOR2_X1_LVT i_1_0_652( + .A1(n_1_0_650), .A2(n_1_0_630), .ZN(n_1_0_620) + ); + AOI22_X1_LVT i_1_0_628( + .A1(registers_13__ap[31]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[31]), + .ZN(n_1_0_596) + ); + NOR2_X1_LVT i_1_0_659( + .A1(n_1_0_650), .A2(n_1_0_628), .ZN(n_1_0_627) + ); + NOR2_X1_LVT i_1_0_651( + .A1(n_1_0_641), .A2(n_1_0_628), .ZN(n_1_0_619) + ); + AOI22_X1_LVT i_1_0_627( + .A1(registers_15__ap[31]), .A2(n_1_0_627), .B1(n_1_0_619), .B2(registers_14__ap[31]), + .ZN(n_1_0_595) + ); + NOR2_X1_LVT i_1_0_668( + .A1(n_1_0_650), .A2(n_1_0_648), .ZN(n_1_0_636) + ); + NOR2_X1_LVT i_1_0_643( + .A1(n_1_0_650), .A2(n_1_0_625), .ZN(n_1_0_611) + ); + AOI22_X1_LVT i_1_0_626( + .A1(registers_27__ap[31]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[31]), + .ZN(n_1_0_594) + ); + NOR2_X1_LVT i_1_0_650( + .A1(n_1_0_647), .A2(n_1_0_625), .ZN(n_1_0_618) + ); + NOR2_X1_LVT i_1_0_642( + .A1(n_1_0_645), .A2(n_1_0_625), .ZN(n_1_0_610) + ); + AOI22_X1_LVT i_1_0_625( + .A1(registers_2__ap[31]), .A2(n_1_0_618), .B1(n_1_0_610), .B2(registers_3__ap[31]), + .ZN(n_1_0_593) + ); + NAND4_X1_LVT i_1_0_624( + .A1(n_1_0_596), .A2(n_1_0_595), .A3(n_1_0_594), .A4(n_1_0_593), .ZN(n_1_0_592) + ); + NOR3_X1_LVT i_1_0_623( + .A1(n_1_0_602), .A2(n_1_0_597), .A3(n_1_0_592), .ZN(n_1_0_591) + ); + NAND4_X1_LVT i_1_0_622( + .A1(n_1_0_609), .A2(n_1_0_608), .A3(n_1_0_607), .A4(n_1_0_591), .ZN(RRs2[31]) + ); + AOI22_X1_LVT i_1_0_620( + .A1(registers_29__ap[30]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[30]), + .ZN(n_1_0_589) + ); + AOI22_X1_LVT i_1_0_621( + .A1(registers_7__ap[30]), .A2(n_1_0_623), .B1(n_1_0_615), .B2(registers_23__ap[30]), + .ZN(n_1_0_590) + ); + AOI22_X1_LVT i_1_0_619( + .A1(registers_1__ap[30]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[30]), + .ZN(n_1_0_588) + ); + AOI22_X1_LVT i_1_0_618( + .A1(registers_5__ap[30]), .A2(n_1_0_635), .B1(n_1_0_633), .B2(registers_19__ap[30]), + .ZN(n_1_0_587) + ); + NAND3_X1_LVT i_1_0_617( + .A1(n_1_0_590), .A2(n_1_0_588), .A3(n_1_0_587), .ZN(n_1_0_586) + ); + AOI221_X1_LVT i_1_0_616( + .A(n_1_0_586), .B1(n_1_0_637), .B2(registers_31__ap[30]), .C1(registers_16__ap[30]), + .C2(n_1_0_614), .ZN(n_1_0_585) + ); + AOI222_X1_LVT i_1_0_615( + .A1(registers_26__ap[30]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[30]), + .C1(n_1_0_626), .C2(registers_8__ap[30]), .ZN(n_1_0_584) + ); + NAND3_X1_LVT i_1_0_614( + .A1(n_1_0_589), .A2(n_1_0_585), .A3(n_1_0_584), .ZN(n_1_0_583) + ); + AOI221_X1_LVT i_1_0_613( + .A(n_1_0_583), .B1(n_1_0_629), .B2(registers_17__ap[30]), .C1(registers_28__ap[30]), + .C2(n_1_0_634), .ZN(n_1_0_582) + ); + AOI22_X1_LVT i_1_0_612( + .A1(registers_18__ap[30]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[30]), + .ZN(n_1_0_581) + ); + AOI22_X1_LVT i_1_0_611( + .A1(registers_4__ap[30]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[30]), + .ZN(n_1_0_580) + ); + AOI22_X1_LVT i_1_0_610( + .A1(registers_22__ap[30]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[30]), + .ZN(n_1_0_579) + ); + NAND3_X1_LVT i_1_0_609( + .A1(n_1_0_581), .A2(n_1_0_580), .A3(n_1_0_579), .ZN(n_1_0_578) + ); + AOI221_X1_LVT i_1_0_608( + .A(n_1_0_578), .B1(n_1_0_621), .B2(registers_24__ap[30]), .C1(registers_12__ap[30]), + .C2(n_1_0_632), .ZN(n_1_0_577) + ); + AOI22_X1_LVT i_1_0_607( + .A1(registers_13__ap[30]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[30]), + .ZN(n_1_0_576) + ); + AOI22_X1_LVT i_1_0_606( + .A1(registers_15__ap[30]), .A2(n_1_0_627), .B1(n_1_0_619), .B2(registers_14__ap[30]), + .ZN(n_1_0_575) + ); + AOI22_X1_LVT i_1_0_605( + .A1(registers_27__ap[30]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[30]), + .ZN(n_1_0_574) + ); + NAND3_X1_LVT i_1_0_604( + .A1(n_1_0_576), .A2(n_1_0_575), .A3(n_1_0_574), .ZN(n_1_0_573) + ); + AOI221_X1_LVT i_1_0_603( + .A(n_1_0_573), .B1(n_1_0_610), .B2(registers_3__ap[30]), .C1(registers_2__ap[30]), + .C2(n_1_0_618), .ZN(n_1_0_572) + ); + NAND3_X1_LVT i_1_0_602( + .A1(n_1_0_582), .A2(n_1_0_577), .A3(n_1_0_572), .ZN(RRs2[30]) + ); + AOI22_X1_LVT i_1_0_600( + .A1(registers_28__ap[29]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[29]), + .ZN(n_1_0_570) + ); + AOI22_X1_LVT i_1_0_601( + .A1(registers_31__ap[29]), .A2(n_1_0_637), .B1(n_1_0_627), .B2(registers_15__ap[29]), + .ZN(n_1_0_571) + ); + AOI22_X1_LVT i_1_0_599( + .A1(registers_24__ap[29]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[29]), + .ZN(n_1_0_569) + ); + AOI22_X1_LVT i_1_0_598( + .A1(registers_19__ap[29]), .A2(n_1_0_633), .B1(n_1_0_629), .B2(registers_17__ap[29]), + .ZN(n_1_0_568) + ); + NAND3_X1_LVT i_1_0_597( + .A1(n_1_0_571), .A2(n_1_0_569), .A3(n_1_0_568), .ZN(n_1_0_567) + ); + AOI221_X1_LVT i_1_0_596( + .A(n_1_0_567), .B1(n_1_0_615), .B2(registers_23__ap[29]), .C1(registers_29__ap[29]), + .C2(n_1_0_649), .ZN(n_1_0_566) + ); + AOI222_X1_LVT i_1_0_595( + .A1(registers_26__ap[29]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[29]), + .C1(n_1_0_620), .C2(registers_25__ap[29]), .ZN(n_1_0_565) + ); + NAND3_X1_LVT i_1_0_594( + .A1(n_1_0_570), .A2(n_1_0_566), .A3(n_1_0_565), .ZN(n_1_0_564) + ); + AOI221_X1_LVT i_1_0_593( + .A(n_1_0_564), .B1(n_1_0_612), .B2(registers_21__ap[29]), .C1(registers_13__ap[29]), + .C2(n_1_0_631), .ZN(n_1_0_563) + ); + AOI22_X1_LVT i_1_0_592( + .A1(registers_18__ap[29]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[29]), + .ZN(n_1_0_562) + ); + AOI22_X1_LVT i_1_0_591( + .A1(registers_4__ap[29]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[29]), + .ZN(n_1_0_561) + ); + AOI22_X1_LVT i_1_0_590( + .A1(registers_7__ap[29]), .A2(n_1_0_623), .B1(n_1_0_614), .B2(registers_16__ap[29]), + .ZN(n_1_0_560) + ); + NAND3_X1_LVT i_1_0_589( + .A1(n_1_0_562), .A2(n_1_0_561), .A3(n_1_0_560), .ZN(n_1_0_559) + ); + AOI221_X1_LVT i_1_0_588( + .A(n_1_0_559), .B1(n_1_0_642), .B2(registers_22__ap[29]), .C1(registers_5__ap[29]), + .C2(n_1_0_635), .ZN(n_1_0_558) + ); + AOI22_X1_LVT i_1_0_587( + .A1(registers_1__ap[29]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[29]), + .ZN(n_1_0_557) + ); + AOI22_X1_LVT i_1_0_586( + .A1(registers_14__ap[29]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[29]), + .ZN(n_1_0_556) + ); + AOI22_X1_LVT i_1_0_585( + .A1(registers_27__ap[29]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[29]), + .ZN(n_1_0_555) + ); + NAND3_X1_LVT i_1_0_584( + .A1(n_1_0_557), .A2(n_1_0_556), .A3(n_1_0_555), .ZN(n_1_0_554) + ); + AOI221_X1_LVT i_1_0_583( + .A(n_1_0_554), .B1(n_1_0_610), .B2(registers_3__ap[29]), .C1(registers_2__ap[29]), + .C2(n_1_0_618), .ZN(n_1_0_553) + ); + NAND3_X1_LVT i_1_0_582( + .A1(n_1_0_563), .A2(n_1_0_558), .A3(n_1_0_553), .ZN(RRs2[29]) + ); + AOI22_X1_LVT i_1_0_581( + .A1(registers_5__ap[28]), .A2(n_1_0_635), .B1(n_1_0_634), .B2(registers_28__ap[28]), + .ZN(n_1_0_552) + ); + AOI222_X1_LVT i_1_0_580( + .A1(registers_26__ap[28]), .A2(n_1_0_640), .B1(n_1_0_633), .B2(registers_19__ap[28]), + .C1(n_1_0_626), .C2(registers_8__ap[28]), .ZN(n_1_0_551) + ); + AOI22_X1_LVT i_1_0_579( + .A1(registers_2__ap[28]), .A2(n_1_0_618), .B1(n_1_0_617), .B2(registers_9__ap[28]), + .ZN(n_1_0_550) + ); + AOI22_X1_LVT i_1_0_578( + .A1(registers_7__ap[28]), .A2(n_1_0_623), .B1(n_1_0_612), .B2(registers_21__ap[28]), + .ZN(n_1_0_549) + ); + AOI22_X1_LVT i_1_0_577( + .A1(registers_16__ap[28]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[28]), + .ZN(n_1_0_548) + ); + AOI22_X1_LVT i_1_0_576( + .A1(registers_31__ap[28]), .A2(n_1_0_637), .B1(n_1_0_619), .B2(registers_14__ap[28]), + .ZN(n_1_0_547) + ); + AOI22_X1_LVT i_1_0_575( + .A1(registers_15__ap[28]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[28]), + .ZN(n_1_0_546) + ); + NAND4_X1_LVT i_1_0_574( + .A1(n_1_0_549), .A2(n_1_0_548), .A3(n_1_0_547), .A4(n_1_0_546), .ZN(n_1_0_545) + ); + AOI22_X1_LVT i_1_0_573( + .A1(registers_22__ap[28]), .A2(n_1_0_642), .B1(n_1_0_622), .B2(registers_30__ap[28]), + .ZN(n_1_0_544) + ); + AOI22_X1_LVT i_1_0_572( + .A1(registers_4__ap[28]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[28]), + .ZN(n_1_0_543) + ); + AOI22_X1_LVT i_1_0_571( + .A1(registers_29__ap[28]), .A2(n_1_0_649), .B1(n_1_0_644), .B2(registers_1__ap[28]), + .ZN(n_1_0_542) + ); + AOI22_X1_LVT i_1_0_570( + .A1(registers_12__ap[28]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[28]), + .ZN(n_1_0_541) + ); + NAND4_X1_LVT i_1_0_569( + .A1(n_1_0_544), .A2(n_1_0_543), .A3(n_1_0_542), .A4(n_1_0_541), .ZN(n_1_0_540) + ); + AOI22_X1_LVT i_1_0_568( + .A1(registers_13__ap[28]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[28]), + .ZN(n_1_0_539) + ); + AOI22_X1_LVT i_1_0_567( + .A1(registers_17__ap[28]), .A2(n_1_0_629), .B1(n_1_0_616), .B2(registers_6__ap[28]), + .ZN(n_1_0_538) + ); + AOI22_X1_LVT i_1_0_566( + .A1(registers_10__ap[28]), .A2(n_1_0_624), .B1(n_1_0_615), .B2(registers_23__ap[28]), + .ZN(n_1_0_537) + ); + AOI22_X1_LVT i_1_0_565( + .A1(registers_18__ap[28]), .A2(n_1_0_646), .B1(n_1_0_636), .B2(registers_27__ap[28]), + .ZN(n_1_0_536) + ); + NAND4_X1_LVT i_1_0_564( + .A1(n_1_0_539), .A2(n_1_0_538), .A3(n_1_0_537), .A4(n_1_0_536), .ZN(n_1_0_535) + ); + NOR3_X1_LVT i_1_0_563( + .A1(n_1_0_545), .A2(n_1_0_540), .A3(n_1_0_535), .ZN(n_1_0_534) + ); + NAND4_X1_LVT i_1_0_562( + .A1(n_1_0_552), .A2(n_1_0_551), .A3(n_1_0_550), .A4(n_1_0_534), .ZN(RRs2[28]) + ); + AOI22_X1_LVT i_1_0_561( + .A1(registers_17__ap[27]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[27]), + .ZN(n_1_0_533) + ); + AOI222_X1_LVT i_1_0_560( + .A1(registers_19__ap[27]), .A2(n_1_0_633), .B1(n_1_0_631), .B2(registers_13__ap[27]), + .C1(registers_30__ap[27]), .C2(n_1_0_622), .ZN(n_1_0_532) + ); + AOI22_X1_LVT i_1_0_559( + .A1(registers_1__ap[27]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[27]), + .ZN(n_1_0_531) + ); + AOI22_X1_LVT i_1_0_558( + .A1(registers_24__ap[27]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[27]), + .ZN(n_1_0_530) + ); + AOI22_X1_LVT i_1_0_557( + .A1(registers_15__ap[27]), .A2(n_1_0_627), .B1(n_1_0_611), .B2(registers_11__ap[27]), + .ZN(n_1_0_529) + ); + AOI22_X1_LVT i_1_0_556( + .A1(registers_4__ap[27]), .A2(n_1_0_638), .B1(n_1_0_636), .B2(registers_27__ap[27]), + .ZN(n_1_0_528) + ); + AOI22_X1_LVT i_1_0_555( + .A1(registers_31__ap[27]), .A2(n_1_0_637), .B1(n_1_0_618), .B2(registers_2__ap[27]), + .ZN(n_1_0_527) + ); + NAND4_X1_LVT i_1_0_554( + .A1(n_1_0_530), .A2(n_1_0_529), .A3(n_1_0_528), .A4(n_1_0_527), .ZN(n_1_0_526) + ); + AOI22_X1_LVT i_1_0_553( + .A1(registers_18__ap[27]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[27]), + .ZN(n_1_0_525) + ); + AOI22_X1_LVT i_1_0_552( + .A1(registers_5__ap[27]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[27]), + .ZN(n_1_0_524) + ); + AOI22_X1_LVT i_1_0_551( + .A1(registers_6__ap[27]), .A2(n_1_0_616), .B1(n_1_0_614), .B2(registers_16__ap[27]), + .ZN(n_1_0_523) + ); + AOI22_X1_LVT i_1_0_550( + .A1(registers_22__ap[27]), .A2(n_1_0_642), .B1(n_1_0_620), .B2(registers_25__ap[27]), + .ZN(n_1_0_522) + ); + NAND4_X1_LVT i_1_0_549( + .A1(n_1_0_525), .A2(n_1_0_524), .A3(n_1_0_523), .A4(n_1_0_522), .ZN(n_1_0_521) + ); + AOI22_X1_LVT i_1_0_548( + .A1(registers_29__ap[27]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[27]), + .ZN(n_1_0_520) + ); + AOI22_X1_LVT i_1_0_547( + .A1(registers_7__ap[27]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[27]), + .ZN(n_1_0_519) + ); + AOI22_X1_LVT i_1_0_546( + .A1(registers_8__ap[27]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[27]), + .ZN(n_1_0_518) + ); + AOI22_X1_LVT i_1_0_545( + .A1(registers_10__ap[27]), .A2(n_1_0_624), .B1(n_1_0_610), .B2(registers_3__ap[27]), + .ZN(n_1_0_517) + ); + NAND4_X1_LVT i_1_0_544( + .A1(n_1_0_520), .A2(n_1_0_519), .A3(n_1_0_518), .A4(n_1_0_517), .ZN(n_1_0_516) + ); + NOR3_X1_LVT i_1_0_543( + .A1(n_1_0_526), .A2(n_1_0_521), .A3(n_1_0_516), .ZN(n_1_0_515) + ); + NAND4_X1_LVT i_1_0_542( + .A1(n_1_0_533), .A2(n_1_0_532), .A3(n_1_0_531), .A4(n_1_0_515), .ZN(RRs2[27]) + ); + AOI22_X1_LVT i_1_0_541( + .A1(registers_17__ap[26]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[26]), + .ZN(n_1_0_514) + ); + AOI222_X1_LVT i_1_0_540( + .A1(registers_19__ap[26]), .A2(n_1_0_633), .B1(n_1_0_622), .B2(registers_30__ap[26]), + .C1(n_1_0_631), .C2(registers_13__ap[26]), .ZN(n_1_0_513) + ); + AOI22_X1_LVT i_1_0_539( + .A1(registers_1__ap[26]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[26]), + .ZN(n_1_0_512) + ); + AOI22_X1_LVT i_1_0_538( + .A1(registers_24__ap[26]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[26]), + .ZN(n_1_0_511) + ); + AOI22_X1_LVT i_1_0_537( + .A1(registers_15__ap[26]), .A2(n_1_0_627), .B1(n_1_0_611), .B2(registers_11__ap[26]), + .ZN(n_1_0_510) + ); + AOI22_X1_LVT i_1_0_536( + .A1(registers_4__ap[26]), .A2(n_1_0_638), .B1(n_1_0_636), .B2(registers_27__ap[26]), + .ZN(n_1_0_509) + ); + AOI22_X1_LVT i_1_0_535( + .A1(registers_31__ap[26]), .A2(n_1_0_637), .B1(n_1_0_618), .B2(registers_2__ap[26]), + .ZN(n_1_0_508) + ); + NAND4_X1_LVT i_1_0_534( + .A1(n_1_0_511), .A2(n_1_0_510), .A3(n_1_0_509), .A4(n_1_0_508), .ZN(n_1_0_507) + ); + AOI22_X1_LVT i_1_0_533( + .A1(registers_18__ap[26]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[26]), + .ZN(n_1_0_506) + ); + AOI22_X1_LVT i_1_0_532( + .A1(registers_5__ap[26]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[26]), + .ZN(n_1_0_505) + ); + AOI22_X1_LVT i_1_0_531( + .A1(registers_6__ap[26]), .A2(n_1_0_616), .B1(n_1_0_614), .B2(registers_16__ap[26]), + .ZN(n_1_0_504) + ); + AOI22_X1_LVT i_1_0_530( + .A1(registers_22__ap[26]), .A2(n_1_0_642), .B1(n_1_0_620), .B2(registers_25__ap[26]), + .ZN(n_1_0_503) + ); + NAND4_X1_LVT i_1_0_529( + .A1(n_1_0_506), .A2(n_1_0_505), .A3(n_1_0_504), .A4(n_1_0_503), .ZN(n_1_0_502) + ); + AOI22_X1_LVT i_1_0_528( + .A1(registers_29__ap[26]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[26]), + .ZN(n_1_0_501) + ); + AOI22_X1_LVT i_1_0_527( + .A1(registers_7__ap[26]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[26]), + .ZN(n_1_0_500) + ); + AOI22_X1_LVT i_1_0_526( + .A1(registers_8__ap[26]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[26]), + .ZN(n_1_0_499) + ); + AOI22_X1_LVT i_1_0_525( + .A1(registers_10__ap[26]), .A2(n_1_0_624), .B1(n_1_0_610), .B2(registers_3__ap[26]), + .ZN(n_1_0_498) + ); + NAND4_X1_LVT i_1_0_524( + .A1(n_1_0_501), .A2(n_1_0_500), .A3(n_1_0_499), .A4(n_1_0_498), .ZN(n_1_0_497) + ); + NOR3_X1_LVT i_1_0_523( + .A1(n_1_0_507), .A2(n_1_0_502), .A3(n_1_0_497), .ZN(n_1_0_496) + ); + NAND4_X1_LVT i_1_0_522( + .A1(n_1_0_514), .A2(n_1_0_513), .A3(n_1_0_512), .A4(n_1_0_496), .ZN(RRs2[26]) + ); + AOI22_X1_LVT i_1_0_520( + .A1(registers_5__ap[25]), .A2(n_1_0_635), .B1(n_1_0_634), .B2(registers_28__ap[25]), + .ZN(n_1_0_494) + ); + AOI22_X1_LVT i_1_0_521( + .A1(registers_8__ap[25]), .A2(n_1_0_626), .B1(n_1_0_620), .B2(registers_25__ap[25]), + .ZN(n_1_0_495) + ); + AOI22_X1_LVT i_1_0_519( + .A1(registers_14__ap[25]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[25]), + .ZN(n_1_0_493) + ); + AOI22_X1_LVT i_1_0_518( + .A1(registers_16__ap[25]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[25]), + .ZN(n_1_0_492) + ); + NAND3_X1_LVT i_1_0_517( + .A1(n_1_0_495), .A2(n_1_0_493), .A3(n_1_0_492), .ZN(n_1_0_491) + ); + AOI221_X1_LVT i_1_0_516( + .A(n_1_0_491), .B1(n_1_0_624), .B2(registers_10__ap[25]), .C1(registers_6__ap[25]), + .C2(n_1_0_616), .ZN(n_1_0_490) + ); + AOI222_X1_LVT i_1_0_515( + .A1(registers_1__ap[25]), .A2(n_1_0_644), .B1(n_1_0_640), .B2(registers_26__ap[25]), + .C1(n_1_0_622), .C2(registers_30__ap[25]), .ZN(n_1_0_489) + ); + NAND2_X1_LVT i_1_0_514( + .A1(n_1_0_490), .A2(n_1_0_489), .ZN(n_1_0_488) + ); + AOI221_X1_LVT i_1_0_513( + .A(n_1_0_488), .B1(n_1_0_649), .B2(registers_29__ap[25]), .C1(registers_2__ap[25]), + .C2(n_1_0_618), .ZN(n_1_0_487) + ); + AOI22_X1_LVT i_1_0_512( + .A1(registers_12__ap[25]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[25]), + .ZN(n_1_0_486) + ); + AOI22_X1_LVT i_1_0_511( + .A1(registers_22__ap[25]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[25]), + .ZN(n_1_0_485) + ); + AOI22_X1_LVT i_1_0_510( + .A1(registers_4__ap[25]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[25]), + .ZN(n_1_0_484) + ); + NAND3_X1_LVT i_1_0_509( + .A1(n_1_0_486), .A2(n_1_0_485), .A3(n_1_0_484), .ZN(n_1_0_483) + ); + AOI221_X1_LVT i_1_0_508( + .A(n_1_0_483), .B1(n_1_0_633), .B2(registers_19__ap[25]), .C1(registers_18__ap[25]), + .C2(n_1_0_646), .ZN(n_1_0_482) + ); + AOI22_X1_LVT i_1_0_507( + .A1(registers_15__ap[25]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[25]), + .ZN(n_1_0_481) + ); + AOI22_X1_LVT i_1_0_506( + .A1(registers_23__ap[25]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[25]), + .ZN(n_1_0_480) + ); + AOI22_X1_LVT i_1_0_505( + .A1(registers_13__ap[25]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[25]), + .ZN(n_1_0_479) + ); + NAND3_X1_LVT i_1_0_504( + .A1(n_1_0_481), .A2(n_1_0_480), .A3(n_1_0_479), .ZN(n_1_0_478) + ); + AOI221_X1_LVT i_1_0_503( + .A(n_1_0_478), .B1(n_1_0_636), .B2(registers_27__ap[25]), .C1(registers_31__ap[25]), + .C2(n_1_0_637), .ZN(n_1_0_477) + ); + NAND4_X1_LVT i_1_0_502( + .A1(n_1_0_494), .A2(n_1_0_487), .A3(n_1_0_482), .A4(n_1_0_477), .ZN(RRs2[25]) + ); + AOI22_X1_LVT i_1_0_501( + .A1(registers_17__ap[24]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[24]), + .ZN(n_1_0_476) + ); + AOI222_X1_LVT i_1_0_500( + .A1(registers_13__ap[24]), .A2(n_1_0_631), .B1(n_1_0_622), .B2(registers_30__ap[24]), + .C1(registers_26__ap[24]), .C2(n_1_0_640), .ZN(n_1_0_475) + ); + AOI22_X1_LVT i_1_0_499( + .A1(registers_1__ap[24]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[24]), + .ZN(n_1_0_474) + ); + AOI22_X1_LVT i_1_0_498( + .A1(registers_24__ap[24]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[24]), + .ZN(n_1_0_473) + ); + AOI22_X1_LVT i_1_0_497( + .A1(registers_8__ap[24]), .A2(n_1_0_626), .B1(n_1_0_616), .B2(registers_6__ap[24]), + .ZN(n_1_0_472) + ); + AOI22_X1_LVT i_1_0_496( + .A1(registers_4__ap[24]), .A2(n_1_0_638), .B1(n_1_0_611), .B2(registers_11__ap[24]), + .ZN(n_1_0_471) + ); + AOI22_X1_LVT i_1_0_495( + .A1(registers_10__ap[24]), .A2(n_1_0_624), .B1(n_1_0_618), .B2(registers_2__ap[24]), + .ZN(n_1_0_470) + ); + NAND4_X1_LVT i_1_0_494( + .A1(n_1_0_473), .A2(n_1_0_472), .A3(n_1_0_471), .A4(n_1_0_470), .ZN(n_1_0_469) + ); + AOI22_X1_LVT i_1_0_493( + .A1(registers_18__ap[24]), .A2(n_1_0_646), .B1(n_1_0_633), .B2(registers_19__ap[24]), + .ZN(n_1_0_468) + ); + AOI22_X1_LVT i_1_0_492( + .A1(registers_5__ap[24]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[24]), + .ZN(n_1_0_467) + ); + AOI22_X1_LVT i_1_0_491( + .A1(registers_15__ap[24]), .A2(n_1_0_627), .B1(n_1_0_614), .B2(registers_16__ap[24]), + .ZN(n_1_0_466) + ); + AOI22_X1_LVT i_1_0_490( + .A1(registers_22__ap[24]), .A2(n_1_0_642), .B1(n_1_0_620), .B2(registers_25__ap[24]), + .ZN(n_1_0_465) + ); + NAND4_X1_LVT i_1_0_489( + .A1(n_1_0_468), .A2(n_1_0_467), .A3(n_1_0_466), .A4(n_1_0_465), .ZN(n_1_0_464) + ); + AOI22_X1_LVT i_1_0_488( + .A1(registers_29__ap[24]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[24]), + .ZN(n_1_0_463) + ); + AOI22_X1_LVT i_1_0_487( + .A1(registers_7__ap[24]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[24]), + .ZN(n_1_0_462) + ); + AOI22_X1_LVT i_1_0_486( + .A1(registers_23__ap[24]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[24]), + .ZN(n_1_0_461) + ); + AOI22_X1_LVT i_1_0_485( + .A1(registers_31__ap[24]), .A2(n_1_0_637), .B1(n_1_0_636), .B2(registers_27__ap[24]), + .ZN(n_1_0_460) + ); + NAND4_X1_LVT i_1_0_484( + .A1(n_1_0_463), .A2(n_1_0_462), .A3(n_1_0_461), .A4(n_1_0_460), .ZN(n_1_0_459) + ); + NOR3_X1_LVT i_1_0_483( + .A1(n_1_0_469), .A2(n_1_0_464), .A3(n_1_0_459), .ZN(n_1_0_458) + ); + NAND4_X1_LVT i_1_0_482( + .A1(n_1_0_476), .A2(n_1_0_475), .A3(n_1_0_474), .A4(n_1_0_458), .ZN(RRs2[24]) + ); + AOI22_X1_LVT i_1_0_481( + .A1(registers_4__ap[23]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[23]), + .ZN(n_1_0_457) + ); + AOI222_X1_LVT i_1_0_480( + .A1(registers_18__ap[23]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[23]), + .C1(n_1_0_644), .C2(registers_1__ap[23]), .ZN(n_1_0_456) + ); + AOI22_X1_LVT i_1_0_479( + .A1(registers_29__ap[23]), .A2(n_1_0_649), .B1(n_1_0_618), .B2(registers_2__ap[23]), + .ZN(n_1_0_455) + ); + AOI22_X1_LVT i_1_0_478( + .A1(registers_14__ap[23]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[23]), + .ZN(n_1_0_454) + ); + AOI22_X1_LVT i_1_0_477( + .A1(registers_16__ap[23]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[23]), + .ZN(n_1_0_453) + ); + AOI22_X1_LVT i_1_0_476( + .A1(registers_27__ap[23]), .A2(n_1_0_636), .B1(n_1_0_620), .B2(registers_25__ap[23]), + .ZN(n_1_0_452) + ); + AOI22_X1_LVT i_1_0_475( + .A1(registers_31__ap[23]), .A2(n_1_0_637), .B1(n_1_0_616), .B2(registers_6__ap[23]), + .ZN(n_1_0_451) + ); + NAND4_X1_LVT i_1_0_474( + .A1(n_1_0_454), .A2(n_1_0_453), .A3(n_1_0_452), .A4(n_1_0_451), .ZN(n_1_0_450) + ); + AOI22_X1_LVT i_1_0_473( + .A1(registers_26__ap[23]), .A2(n_1_0_640), .B1(n_1_0_633), .B2(registers_19__ap[23]), + .ZN(n_1_0_449) + ); + AOI22_X1_LVT i_1_0_472( + .A1(registers_12__ap[23]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[23]), + .ZN(n_1_0_448) + ); + AOI22_X1_LVT i_1_0_471( + .A1(registers_22__ap[23]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[23]), + .ZN(n_1_0_447) + ); + AOI22_X1_LVT i_1_0_470( + .A1(registers_5__ap[23]), .A2(n_1_0_635), .B1(n_1_0_613), .B2(registers_20__ap[23]), + .ZN(n_1_0_446) + ); + NAND4_X1_LVT i_1_0_469( + .A1(n_1_0_449), .A2(n_1_0_448), .A3(n_1_0_447), .A4(n_1_0_446), .ZN(n_1_0_445) + ); + AOI22_X1_LVT i_1_0_468( + .A1(registers_15__ap[23]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[23]), + .ZN(n_1_0_444) + ); + AOI22_X1_LVT i_1_0_467( + .A1(registers_8__ap[23]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[23]), + .ZN(n_1_0_443) + ); + AOI22_X1_LVT i_1_0_466( + .A1(registers_13__ap[23]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[23]), + .ZN(n_1_0_442) + ); + AOI22_X1_LVT i_1_0_465( + .A1(registers_10__ap[23]), .A2(n_1_0_624), .B1(n_1_0_610), .B2(registers_3__ap[23]), + .ZN(n_1_0_441) + ); + NAND4_X1_LVT i_1_0_464( + .A1(n_1_0_444), .A2(n_1_0_443), .A3(n_1_0_442), .A4(n_1_0_441), .ZN(n_1_0_440) + ); + NOR3_X1_LVT i_1_0_463( + .A1(n_1_0_450), .A2(n_1_0_445), .A3(n_1_0_440), .ZN(n_1_0_439) + ); + NAND4_X1_LVT i_1_0_462( + .A1(n_1_0_457), .A2(n_1_0_456), .A3(n_1_0_455), .A4(n_1_0_439), .ZN(RRs2[23]) + ); + AOI22_X1_LVT i_1_0_460( + .A1(registers_17__ap[22]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[22]), + .ZN(n_1_0_437) + ); + AOI22_X1_LVT i_1_0_461( + .A1(registers_15__ap[22]), .A2(n_1_0_627), .B1(n_1_0_626), .B2(registers_8__ap[22]), + .ZN(n_1_0_438) + ); + AOI22_X1_LVT i_1_0_459( + .A1(registers_24__ap[22]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[22]), + .ZN(n_1_0_436) + ); + AOI22_X1_LVT i_1_0_458( + .A1(registers_5__ap[22]), .A2(n_1_0_635), .B1(n_1_0_611), .B2(registers_11__ap[22]), + .ZN(n_1_0_435) + ); + NAND3_X1_LVT i_1_0_457( + .A1(n_1_0_438), .A2(n_1_0_436), .A3(n_1_0_435), .ZN(n_1_0_434) + ); + AOI221_X1_LVT i_1_0_456( + .A(n_1_0_434), .B1(n_1_0_618), .B2(registers_2__ap[22]), .C1(registers_10__ap[22]), + .C2(n_1_0_624), .ZN(n_1_0_433) + ); + AOI222_X1_LVT i_1_0_455( + .A1(registers_26__ap[22]), .A2(n_1_0_640), .B1(n_1_0_622), .B2(registers_30__ap[22]), + .C1(n_1_0_631), .C2(registers_13__ap[22]), .ZN(n_1_0_432) + ); + NAND2_X1_LVT i_1_0_454( + .A1(n_1_0_433), .A2(n_1_0_432), .ZN(n_1_0_431) + ); + AOI221_X1_LVT i_1_0_453( + .A(n_1_0_431), .B1(n_1_0_644), .B2(registers_1__ap[22]), .C1(registers_28__ap[22]), + .C2(n_1_0_634), .ZN(n_1_0_430) + ); + AOI22_X1_LVT i_1_0_452( + .A1(registers_18__ap[22]), .A2(n_1_0_646), .B1(n_1_0_633), .B2(registers_19__ap[22]), + .ZN(n_1_0_429) + ); + AOI22_X1_LVT i_1_0_451( + .A1(registers_4__ap[22]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[22]), + .ZN(n_1_0_428) + ); + AOI22_X1_LVT i_1_0_450( + .A1(registers_6__ap[22]), .A2(n_1_0_616), .B1(n_1_0_614), .B2(registers_16__ap[22]), + .ZN(n_1_0_427) + ); + NAND3_X1_LVT i_1_0_449( + .A1(n_1_0_429), .A2(n_1_0_428), .A3(n_1_0_427), .ZN(n_1_0_426) + ); + AOI221_X1_LVT i_1_0_448( + .A(n_1_0_426), .B1(n_1_0_620), .B2(registers_25__ap[22]), .C1(registers_22__ap[22]), + .C2(n_1_0_642), .ZN(n_1_0_425) + ); + AOI22_X1_LVT i_1_0_447( + .A1(registers_29__ap[22]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[22]), + .ZN(n_1_0_424) + ); + AOI22_X1_LVT i_1_0_446( + .A1(registers_7__ap[22]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[22]), + .ZN(n_1_0_423) + ); + AOI22_X1_LVT i_1_0_445( + .A1(registers_23__ap[22]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[22]), + .ZN(n_1_0_422) + ); + NAND3_X1_LVT i_1_0_444( + .A1(n_1_0_424), .A2(n_1_0_423), .A3(n_1_0_422), .ZN(n_1_0_421) + ); + AOI221_X1_LVT i_1_0_443( + .A(n_1_0_421), .B1(n_1_0_636), .B2(registers_27__ap[22]), .C1(registers_31__ap[22]), + .C2(n_1_0_637), .ZN(n_1_0_420) + ); + NAND4_X1_LVT i_1_0_442( + .A1(n_1_0_437), .A2(n_1_0_430), .A3(n_1_0_425), .A4(n_1_0_420), .ZN(RRs2[22]) + ); + AOI22_X1_LVT i_1_0_441( + .A1(registers_5__ap[21]), .A2(n_1_0_635), .B1(n_1_0_634), .B2(registers_28__ap[21]), + .ZN(n_1_0_419) + ); + AOI222_X1_LVT i_1_0_440( + .A1(registers_1__ap[21]), .A2(n_1_0_644), .B1(n_1_0_640), .B2(registers_26__ap[21]), + .C1(n_1_0_622), .C2(registers_30__ap[21]), .ZN(n_1_0_418) + ); + AOI22_X1_LVT i_1_0_439( + .A1(registers_29__ap[21]), .A2(n_1_0_649), .B1(n_1_0_618), .B2(registers_2__ap[21]), + .ZN(n_1_0_417) + ); + AOI22_X1_LVT i_1_0_438( + .A1(registers_14__ap[21]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[21]), + .ZN(n_1_0_416) + ); + AOI22_X1_LVT i_1_0_437( + .A1(registers_8__ap[21]), .A2(n_1_0_626), .B1(n_1_0_614), .B2(registers_16__ap[21]), + .ZN(n_1_0_415) + ); + AOI22_X1_LVT i_1_0_436( + .A1(registers_25__ap[21]), .A2(n_1_0_620), .B1(n_1_0_611), .B2(registers_11__ap[21]), + .ZN(n_1_0_414) + ); + AOI22_X1_LVT i_1_0_435( + .A1(registers_10__ap[21]), .A2(n_1_0_624), .B1(n_1_0_616), .B2(registers_6__ap[21]), + .ZN(n_1_0_413) + ); + NAND4_X1_LVT i_1_0_434( + .A1(n_1_0_416), .A2(n_1_0_415), .A3(n_1_0_414), .A4(n_1_0_413), .ZN(n_1_0_412) + ); + AOI22_X1_LVT i_1_0_433( + .A1(registers_12__ap[21]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[21]), + .ZN(n_1_0_411) + ); + AOI22_X1_LVT i_1_0_432( + .A1(registers_22__ap[21]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[21]), + .ZN(n_1_0_410) + ); + AOI22_X1_LVT i_1_0_431( + .A1(registers_4__ap[21]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[21]), + .ZN(n_1_0_409) + ); + AOI22_X1_LVT i_1_0_430( + .A1(registers_18__ap[21]), .A2(n_1_0_646), .B1(n_1_0_633), .B2(registers_19__ap[21]), + .ZN(n_1_0_408) + ); + NAND4_X1_LVT i_1_0_429( + .A1(n_1_0_411), .A2(n_1_0_410), .A3(n_1_0_409), .A4(n_1_0_408), .ZN(n_1_0_407) + ); + AOI22_X1_LVT i_1_0_428( + .A1(registers_15__ap[21]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[21]), + .ZN(n_1_0_406) + ); + AOI22_X1_LVT i_1_0_427( + .A1(registers_23__ap[21]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[21]), + .ZN(n_1_0_405) + ); + AOI22_X1_LVT i_1_0_426( + .A1(registers_13__ap[21]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[21]), + .ZN(n_1_0_404) + ); + AOI22_X1_LVT i_1_0_425( + .A1(registers_31__ap[21]), .A2(n_1_0_637), .B1(n_1_0_636), .B2(registers_27__ap[21]), + .ZN(n_1_0_403) + ); + NAND4_X1_LVT i_1_0_424( + .A1(n_1_0_406), .A2(n_1_0_405), .A3(n_1_0_404), .A4(n_1_0_403), .ZN(n_1_0_402) + ); + NOR3_X1_LVT i_1_0_423( + .A1(n_1_0_412), .A2(n_1_0_407), .A3(n_1_0_402), .ZN(n_1_0_401) + ); + NAND4_X1_LVT i_1_0_422( + .A1(n_1_0_419), .A2(n_1_0_418), .A3(n_1_0_417), .A4(n_1_0_401), .ZN(RRs2[21]) + ); + AOI22_X1_LVT i_1_0_421( + .A1(registers_17__ap[20]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[20]), + .ZN(n_1_0_400) + ); + AOI222_X1_LVT i_1_0_420( + .A1(registers_13__ap[20]), .A2(n_1_0_631), .B1(n_1_0_622), .B2(registers_30__ap[20]), + .C1(registers_19__ap[20]), .C2(n_1_0_633), .ZN(n_1_0_399) + ); + AOI22_X1_LVT i_1_0_419( + .A1(registers_1__ap[20]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[20]), + .ZN(n_1_0_398) + ); + AOI22_X1_LVT i_1_0_418( + .A1(registers_24__ap[20]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[20]), + .ZN(n_1_0_397) + ); + AOI22_X1_LVT i_1_0_417( + .A1(registers_6__ap[20]), .A2(n_1_0_616), .B1(n_1_0_611), .B2(registers_11__ap[20]), + .ZN(n_1_0_396) + ); + AOI22_X1_LVT i_1_0_416( + .A1(registers_4__ap[20]), .A2(n_1_0_638), .B1(n_1_0_624), .B2(registers_10__ap[20]), + .ZN(n_1_0_395) + ); + AOI22_X1_LVT i_1_0_415( + .A1(registers_31__ap[20]), .A2(n_1_0_637), .B1(n_1_0_618), .B2(registers_2__ap[20]), + .ZN(n_1_0_394) + ); + NAND4_X1_LVT i_1_0_414( + .A1(n_1_0_397), .A2(n_1_0_396), .A3(n_1_0_395), .A4(n_1_0_394), .ZN(n_1_0_393) + ); + AOI22_X1_LVT i_1_0_413( + .A1(registers_18__ap[20]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[20]), + .ZN(n_1_0_392) + ); + AOI22_X1_LVT i_1_0_412( + .A1(registers_5__ap[20]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[20]), + .ZN(n_1_0_391) + ); + AOI22_X1_LVT i_1_0_411( + .A1(registers_15__ap[20]), .A2(n_1_0_627), .B1(n_1_0_614), .B2(registers_16__ap[20]), + .ZN(n_1_0_390) + ); + AOI22_X1_LVT i_1_0_410( + .A1(registers_22__ap[20]), .A2(n_1_0_642), .B1(n_1_0_620), .B2(registers_25__ap[20]), + .ZN(n_1_0_389) + ); + NAND4_X1_LVT i_1_0_409( + .A1(n_1_0_392), .A2(n_1_0_391), .A3(n_1_0_390), .A4(n_1_0_389), .ZN(n_1_0_388) + ); + AOI22_X1_LVT i_1_0_408( + .A1(registers_29__ap[20]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[20]), + .ZN(n_1_0_387) + ); + AOI22_X1_LVT i_1_0_407( + .A1(registers_7__ap[20]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[20]), + .ZN(n_1_0_386) + ); + AOI22_X1_LVT i_1_0_406( + .A1(registers_8__ap[20]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[20]), + .ZN(n_1_0_385) + ); + AOI22_X1_LVT i_1_0_405( + .A1(registers_27__ap[20]), .A2(n_1_0_636), .B1(n_1_0_610), .B2(registers_3__ap[20]), + .ZN(n_1_0_384) + ); + NAND4_X1_LVT i_1_0_404( + .A1(n_1_0_387), .A2(n_1_0_386), .A3(n_1_0_385), .A4(n_1_0_384), .ZN(n_1_0_383) + ); + NOR3_X1_LVT i_1_0_403( + .A1(n_1_0_393), .A2(n_1_0_388), .A3(n_1_0_383), .ZN(n_1_0_382) + ); + NAND4_X1_LVT i_1_0_402( + .A1(n_1_0_400), .A2(n_1_0_399), .A3(n_1_0_398), .A4(n_1_0_382), .ZN(RRs2[20]) + ); + AOI22_X1_LVT i_1_0_401( + .A1(registers_17__ap[19]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[19]), + .ZN(n_1_0_381) + ); + AOI222_X1_LVT i_1_0_400( + .A1(registers_13__ap[19]), .A2(n_1_0_631), .B1(n_1_0_622), .B2(registers_30__ap[19]), + .C1(registers_19__ap[19]), .C2(n_1_0_633), .ZN(n_1_0_380) + ); + AOI22_X1_LVT i_1_0_399( + .A1(registers_1__ap[19]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[19]), + .ZN(n_1_0_379) + ); + AOI22_X1_LVT i_1_0_398( + .A1(registers_24__ap[19]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[19]), + .ZN(n_1_0_378) + ); + AOI22_X1_LVT i_1_0_397( + .A1(registers_15__ap[19]), .A2(n_1_0_627), .B1(n_1_0_611), .B2(registers_11__ap[19]), + .ZN(n_1_0_377) + ); + AOI22_X1_LVT i_1_0_396( + .A1(registers_4__ap[19]), .A2(n_1_0_638), .B1(n_1_0_636), .B2(registers_27__ap[19]), + .ZN(n_1_0_376) + ); + AOI22_X1_LVT i_1_0_395( + .A1(registers_31__ap[19]), .A2(n_1_0_637), .B1(n_1_0_618), .B2(registers_2__ap[19]), + .ZN(n_1_0_375) + ); + NAND4_X1_LVT i_1_0_394( + .A1(n_1_0_378), .A2(n_1_0_377), .A3(n_1_0_376), .A4(n_1_0_375), .ZN(n_1_0_374) + ); + AOI22_X1_LVT i_1_0_393( + .A1(registers_18__ap[19]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[19]), + .ZN(n_1_0_373) + ); + AOI22_X1_LVT i_1_0_392( + .A1(registers_5__ap[19]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[19]), + .ZN(n_1_0_372) + ); + AOI22_X1_LVT i_1_0_391( + .A1(registers_25__ap[19]), .A2(n_1_0_620), .B1(n_1_0_616), .B2(registers_6__ap[19]), + .ZN(n_1_0_371) + ); + AOI22_X1_LVT i_1_0_390( + .A1(registers_22__ap[19]), .A2(n_1_0_642), .B1(n_1_0_614), .B2(registers_16__ap[19]), + .ZN(n_1_0_370) + ); + NAND4_X1_LVT i_1_0_389( + .A1(n_1_0_373), .A2(n_1_0_372), .A3(n_1_0_371), .A4(n_1_0_370), .ZN(n_1_0_369) + ); + AOI22_X1_LVT i_1_0_388( + .A1(registers_29__ap[19]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[19]), + .ZN(n_1_0_368) + ); + AOI22_X1_LVT i_1_0_387( + .A1(registers_7__ap[19]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[19]), + .ZN(n_1_0_367) + ); + AOI22_X1_LVT i_1_0_386( + .A1(registers_8__ap[19]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[19]), + .ZN(n_1_0_366) + ); + AOI22_X1_LVT i_1_0_385( + .A1(registers_10__ap[19]), .A2(n_1_0_624), .B1(n_1_0_610), .B2(registers_3__ap[19]), + .ZN(n_1_0_365) + ); + NAND4_X1_LVT i_1_0_384( + .A1(n_1_0_368), .A2(n_1_0_367), .A3(n_1_0_366), .A4(n_1_0_365), .ZN(n_1_0_364) + ); + NOR3_X1_LVT i_1_0_383( + .A1(n_1_0_374), .A2(n_1_0_369), .A3(n_1_0_364), .ZN(n_1_0_363) + ); + NAND4_X1_LVT i_1_0_382( + .A1(n_1_0_381), .A2(n_1_0_380), .A3(n_1_0_379), .A4(n_1_0_363), .ZN(RRs2[19]) + ); + AOI22_X1_LVT i_1_0_380( + .A1(registers_4__ap[18]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[18]), + .ZN(n_1_0_361) + ); + AOI22_X1_LVT i_1_0_381( + .A1(registers_8__ap[18]), .A2(n_1_0_626), .B1(n_1_0_614), .B2(registers_16__ap[18]), + .ZN(n_1_0_362) + ); + AOI22_X1_LVT i_1_0_379( + .A1(registers_14__ap[18]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[18]), + .ZN(n_1_0_360) + ); + AOI22_X1_LVT i_1_0_378( + .A1(registers_25__ap[18]), .A2(n_1_0_620), .B1(n_1_0_611), .B2(registers_11__ap[18]), + .ZN(n_1_0_359) + ); + NAND3_X1_LVT i_1_0_377( + .A1(n_1_0_362), .A2(n_1_0_360), .A3(n_1_0_359), .ZN(n_1_0_358) + ); + AOI221_X1_LVT i_1_0_376( + .A(n_1_0_358), .B1(n_1_0_624), .B2(registers_10__ap[18]), .C1(registers_6__ap[18]), + .C2(n_1_0_616), .ZN(n_1_0_357) + ); + AOI222_X1_LVT i_1_0_375( + .A1(registers_1__ap[18]), .A2(n_1_0_644), .B1(n_1_0_640), .B2(registers_26__ap[18]), + .C1(n_1_0_622), .C2(registers_30__ap[18]), .ZN(n_1_0_356) + ); + NAND2_X1_LVT i_1_0_374( + .A1(n_1_0_357), .A2(n_1_0_356), .ZN(n_1_0_355) + ); + AOI221_X1_LVT i_1_0_373( + .A(n_1_0_355), .B1(n_1_0_649), .B2(registers_29__ap[18]), .C1(registers_2__ap[18]), + .C2(n_1_0_618), .ZN(n_1_0_354) + ); + AOI22_X1_LVT i_1_0_372( + .A1(registers_18__ap[18]), .A2(n_1_0_646), .B1(n_1_0_633), .B2(registers_19__ap[18]), + .ZN(n_1_0_353) + ); + AOI22_X1_LVT i_1_0_371( + .A1(registers_12__ap[18]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[18]), + .ZN(n_1_0_352) + ); + AOI22_X1_LVT i_1_0_370( + .A1(registers_22__ap[18]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[18]), + .ZN(n_1_0_351) + ); + NAND3_X1_LVT i_1_0_369( + .A1(n_1_0_353), .A2(n_1_0_352), .A3(n_1_0_351), .ZN(n_1_0_350) + ); + AOI221_X1_LVT i_1_0_368( + .A(n_1_0_350), .B1(n_1_0_635), .B2(registers_5__ap[18]), .C1(registers_20__ap[18]), + .C2(n_1_0_613), .ZN(n_1_0_349) + ); + AOI22_X1_LVT i_1_0_367( + .A1(registers_15__ap[18]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[18]), + .ZN(n_1_0_348) + ); + AOI22_X1_LVT i_1_0_366( + .A1(registers_23__ap[18]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[18]), + .ZN(n_1_0_347) + ); + AOI22_X1_LVT i_1_0_365( + .A1(registers_13__ap[18]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[18]), + .ZN(n_1_0_346) + ); + NAND3_X1_LVT i_1_0_364( + .A1(n_1_0_348), .A2(n_1_0_347), .A3(n_1_0_346), .ZN(n_1_0_345) + ); + AOI221_X1_LVT i_1_0_363( + .A(n_1_0_345), .B1(n_1_0_637), .B2(registers_31__ap[18]), .C1(registers_27__ap[18]), + .C2(n_1_0_636), .ZN(n_1_0_344) + ); + NAND4_X1_LVT i_1_0_362( + .A1(n_1_0_361), .A2(n_1_0_354), .A3(n_1_0_349), .A4(n_1_0_344), .ZN(RRs2[18]) + ); + AOI22_X1_LVT i_1_0_358( + .A1(registers_4__ap[17]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[17]), + .ZN(n_1_0_340) + ); + AOI22_X1_LVT i_1_0_361( + .A1(registers_31__ap[17]), .A2(n_1_0_637), .B1(n_1_0_616), .B2(registers_6__ap[17]), + .ZN(n_1_0_343) + ); + AOI22_X1_LVT i_1_0_357( + .A1(registers_14__ap[17]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[17]), + .ZN(n_1_0_339) + ); + AOI22_X1_LVT i_1_0_360( + .A1(registers_25__ap[17]), .A2(n_1_0_620), .B1(n_1_0_611), .B2(registers_11__ap[17]), + .ZN(n_1_0_342) + ); + INV_X1_LVT i_1_0_359( + .A(n_1_0_342), .ZN(n_1_0_341) + ); + AOI221_X1_LVT i_1_0_356( + .A(n_1_0_341), .B1(n_1_0_614), .B2(registers_16__ap[17]), .C1(registers_10__ap[17]), + .C2(n_1_0_624), .ZN(n_1_0_338) + ); + AOI222_X1_LVT i_1_0_355( + .A1(registers_1__ap[17]), .A2(n_1_0_644), .B1(n_1_0_622), .B2(registers_30__ap[17]), + .C1(registers_18__ap[17]), .C2(n_1_0_646), .ZN(n_1_0_337) + ); + NAND4_X1_LVT i_1_0_354( + .A1(n_1_0_343), .A2(n_1_0_339), .A3(n_1_0_338), .A4(n_1_0_337), .ZN(n_1_0_336) + ); + AOI221_X1_LVT i_1_0_353( + .A(n_1_0_336), .B1(n_1_0_649), .B2(registers_29__ap[17]), .C1(registers_2__ap[17]), + .C2(n_1_0_618), .ZN(n_1_0_335) + ); + AOI22_X1_LVT i_1_0_352( + .A1(registers_26__ap[17]), .A2(n_1_0_640), .B1(n_1_0_633), .B2(registers_19__ap[17]), + .ZN(n_1_0_334) + ); + AOI22_X1_LVT i_1_0_351( + .A1(registers_12__ap[17]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[17]), + .ZN(n_1_0_333) + ); + AOI22_X1_LVT i_1_0_350( + .A1(registers_22__ap[17]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[17]), + .ZN(n_1_0_332) + ); + NAND3_X1_LVT i_1_0_349( + .A1(n_1_0_334), .A2(n_1_0_333), .A3(n_1_0_332), .ZN(n_1_0_331) + ); + AOI221_X1_LVT i_1_0_348( + .A(n_1_0_331), .B1(n_1_0_635), .B2(registers_5__ap[17]), .C1(registers_20__ap[17]), + .C2(n_1_0_613), .ZN(n_1_0_330) + ); + AOI22_X1_LVT i_1_0_347( + .A1(registers_15__ap[17]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[17]), + .ZN(n_1_0_329) + ); + AOI22_X1_LVT i_1_0_346( + .A1(registers_8__ap[17]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[17]), + .ZN(n_1_0_328) + ); + AOI22_X1_LVT i_1_0_345( + .A1(registers_13__ap[17]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[17]), + .ZN(n_1_0_327) + ); + NAND3_X1_LVT i_1_0_344( + .A1(n_1_0_329), .A2(n_1_0_328), .A3(n_1_0_327), .ZN(n_1_0_326) + ); + AOI221_X1_LVT i_1_0_343( + .A(n_1_0_326), .B1(n_1_0_636), .B2(registers_27__ap[17]), .C1(registers_3__ap[17]), + .C2(n_1_0_610), .ZN(n_1_0_325) + ); + NAND4_X1_LVT i_1_0_342( + .A1(n_1_0_340), .A2(n_1_0_335), .A3(n_1_0_330), .A4(n_1_0_325), .ZN(RRs2[17]) + ); + AOI22_X1_LVT i_1_0_341( + .A1(registers_4__ap[16]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[16]), + .ZN(n_1_0_324) + ); + AOI222_X1_LVT i_1_0_340( + .A1(registers_1__ap[16]), .A2(n_1_0_644), .B1(n_1_0_633), .B2(registers_19__ap[16]), + .C1(n_1_0_622), .C2(registers_30__ap[16]), .ZN(n_1_0_323) + ); + AOI22_X1_LVT i_1_0_339( + .A1(registers_29__ap[16]), .A2(n_1_0_649), .B1(n_1_0_618), .B2(registers_2__ap[16]), + .ZN(n_1_0_322) + ); + AOI22_X1_LVT i_1_0_338( + .A1(registers_14__ap[16]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[16]), + .ZN(n_1_0_321) + ); + AOI22_X1_LVT i_1_0_337( + .A1(registers_16__ap[16]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[16]), + .ZN(n_1_0_320) + ); + AOI22_X1_LVT i_1_0_336( + .A1(registers_10__ap[16]), .A2(n_1_0_624), .B1(n_1_0_620), .B2(registers_25__ap[16]), + .ZN(n_1_0_319) + ); + AOI22_X1_LVT i_1_0_335( + .A1(registers_31__ap[16]), .A2(n_1_0_637), .B1(n_1_0_616), .B2(registers_6__ap[16]), + .ZN(n_1_0_318) + ); + NAND4_X1_LVT i_1_0_334( + .A1(n_1_0_321), .A2(n_1_0_320), .A3(n_1_0_319), .A4(n_1_0_318), .ZN(n_1_0_317) + ); + AOI22_X1_LVT i_1_0_333( + .A1(registers_18__ap[16]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[16]), + .ZN(n_1_0_316) + ); + AOI22_X1_LVT i_1_0_332( + .A1(registers_12__ap[16]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[16]), + .ZN(n_1_0_315) + ); + AOI22_X1_LVT i_1_0_331( + .A1(registers_22__ap[16]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[16]), + .ZN(n_1_0_314) + ); + AOI22_X1_LVT i_1_0_330( + .A1(registers_5__ap[16]), .A2(n_1_0_635), .B1(n_1_0_613), .B2(registers_20__ap[16]), + .ZN(n_1_0_313) + ); + NAND4_X1_LVT i_1_0_329( + .A1(n_1_0_316), .A2(n_1_0_315), .A3(n_1_0_314), .A4(n_1_0_313), .ZN(n_1_0_312) + ); + AOI22_X1_LVT i_1_0_328( + .A1(registers_15__ap[16]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[16]), + .ZN(n_1_0_311) + ); + AOI22_X1_LVT i_1_0_327( + .A1(registers_8__ap[16]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[16]), + .ZN(n_1_0_310) + ); + AOI22_X1_LVT i_1_0_326( + .A1(registers_13__ap[16]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[16]), + .ZN(n_1_0_309) + ); + AOI22_X1_LVT i_1_0_325( + .A1(registers_27__ap[16]), .A2(n_1_0_636), .B1(n_1_0_610), .B2(registers_3__ap[16]), + .ZN(n_1_0_308) + ); + NAND4_X1_LVT i_1_0_324( + .A1(n_1_0_311), .A2(n_1_0_310), .A3(n_1_0_309), .A4(n_1_0_308), .ZN(n_1_0_307) + ); + NOR3_X1_LVT i_1_0_323( + .A1(n_1_0_317), .A2(n_1_0_312), .A3(n_1_0_307), .ZN(n_1_0_306) + ); + NAND4_X1_LVT i_1_0_322( + .A1(n_1_0_324), .A2(n_1_0_323), .A3(n_1_0_322), .A4(n_1_0_306), .ZN(RRs2[16]) + ); + AOI22_X1_LVT i_1_0_320( + .A1(registers_5__ap[15]), .A2(n_1_0_635), .B1(n_1_0_634), .B2(registers_28__ap[15]), + .ZN(n_1_0_304) + ); + AOI22_X1_LVT i_1_0_321( + .A1(registers_8__ap[15]), .A2(n_1_0_626), .B1(n_1_0_620), .B2(registers_25__ap[15]), + .ZN(n_1_0_305) + ); + AOI22_X1_LVT i_1_0_319( + .A1(registers_14__ap[15]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[15]), + .ZN(n_1_0_303) + ); + AOI22_X1_LVT i_1_0_318( + .A1(registers_16__ap[15]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[15]), + .ZN(n_1_0_302) + ); + NAND3_X1_LVT i_1_0_317( + .A1(n_1_0_305), .A2(n_1_0_303), .A3(n_1_0_302), .ZN(n_1_0_301) + ); + AOI221_X1_LVT i_1_0_316( + .A(n_1_0_301), .B1(n_1_0_616), .B2(registers_6__ap[15]), .C1(registers_10__ap[15]), + .C2(n_1_0_624), .ZN(n_1_0_300) + ); + AOI222_X1_LVT i_1_0_315( + .A1(registers_1__ap[15]), .A2(n_1_0_644), .B1(n_1_0_640), .B2(registers_26__ap[15]), + .C1(n_1_0_622), .C2(registers_30__ap[15]), .ZN(n_1_0_299) + ); + NAND2_X1_LVT i_1_0_314( + .A1(n_1_0_300), .A2(n_1_0_299), .ZN(n_1_0_298) + ); + AOI221_X1_LVT i_1_0_313( + .A(n_1_0_298), .B1(n_1_0_649), .B2(registers_29__ap[15]), .C1(registers_2__ap[15]), + .C2(n_1_0_618), .ZN(n_1_0_297) + ); + AOI22_X1_LVT i_1_0_312( + .A1(registers_12__ap[15]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[15]), + .ZN(n_1_0_296) + ); + AOI22_X1_LVT i_1_0_311( + .A1(registers_22__ap[15]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[15]), + .ZN(n_1_0_295) + ); + AOI22_X1_LVT i_1_0_310( + .A1(registers_4__ap[15]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[15]), + .ZN(n_1_0_294) + ); + NAND3_X1_LVT i_1_0_309( + .A1(n_1_0_296), .A2(n_1_0_295), .A3(n_1_0_294), .ZN(n_1_0_293) + ); + AOI221_X1_LVT i_1_0_308( + .A(n_1_0_293), .B1(n_1_0_633), .B2(registers_19__ap[15]), .C1(registers_18__ap[15]), + .C2(n_1_0_646), .ZN(n_1_0_292) + ); + AOI22_X1_LVT i_1_0_307( + .A1(registers_15__ap[15]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[15]), + .ZN(n_1_0_291) + ); + AOI22_X1_LVT i_1_0_306( + .A1(registers_23__ap[15]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[15]), + .ZN(n_1_0_290) + ); + AOI22_X1_LVT i_1_0_305( + .A1(registers_13__ap[15]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[15]), + .ZN(n_1_0_289) + ); + NAND3_X1_LVT i_1_0_304( + .A1(n_1_0_291), .A2(n_1_0_290), .A3(n_1_0_289), .ZN(n_1_0_288) + ); + AOI221_X1_LVT i_1_0_303( + .A(n_1_0_288), .B1(n_1_0_636), .B2(registers_27__ap[15]), .C1(registers_31__ap[15]), + .C2(n_1_0_637), .ZN(n_1_0_287) + ); + NAND4_X1_LVT i_1_0_302( + .A1(n_1_0_304), .A2(n_1_0_297), .A3(n_1_0_292), .A4(n_1_0_287), .ZN(RRs2[15]) + ); + AOI22_X1_LVT i_1_0_301( + .A1(registers_28__ap[14]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[14]), + .ZN(n_1_0_286) + ); + AOI222_X1_LVT i_1_0_300( + .A1(registers_18__ap[14]), .A2(n_1_0_646), .B1(n_1_0_620), .B2(registers_25__ap[14]), + .C1(n_1_0_618), .C2(registers_2__ap[14]), .ZN(n_1_0_285) + ); + AOI22_X1_LVT i_1_0_299( + .A1(registers_24__ap[14]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[14]), + .ZN(n_1_0_284) + ); + AOI22_X1_LVT i_1_0_298( + .A1(registers_15__ap[14]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[14]), + .ZN(n_1_0_283) + ); + AOI22_X1_LVT i_1_0_297( + .A1(registers_4__ap[14]), .A2(n_1_0_638), .B1(n_1_0_637), .B2(registers_31__ap[14]), + .ZN(n_1_0_282) + ); + AOI22_X1_LVT i_1_0_296( + .A1(registers_29__ap[14]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[14]), + .ZN(n_1_0_281) + ); + NAND4_X1_LVT i_1_0_295( + .A1(n_1_0_284), .A2(n_1_0_283), .A3(n_1_0_282), .A4(n_1_0_281), .ZN(n_1_0_280) + ); + AOI221_X1_LVT i_1_0_294( + .A(n_1_0_280), .B1(n_1_0_644), .B2(registers_1__ap[14]), .C1(registers_13__ap[14]), + .C2(n_1_0_631), .ZN(n_1_0_279) + ); + AOI22_X1_LVT i_1_0_293( + .A1(registers_17__ap[14]), .A2(n_1_0_629), .B1(n_1_0_623), .B2(registers_7__ap[14]), + .ZN(n_1_0_278) + ); + AOI22_X1_LVT i_1_0_292( + .A1(registers_5__ap[14]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[14]), + .ZN(n_1_0_277) + ); + AOI22_X1_LVT i_1_0_291( + .A1(registers_10__ap[14]), .A2(n_1_0_624), .B1(n_1_0_622), .B2(registers_30__ap[14]), + .ZN(n_1_0_276) + ); + AOI22_X1_LVT i_1_0_290( + .A1(registers_26__ap[14]), .A2(n_1_0_640), .B1(n_1_0_614), .B2(registers_16__ap[14]), + .ZN(n_1_0_275) + ); + NAND4_X1_LVT i_1_0_289( + .A1(n_1_0_278), .A2(n_1_0_277), .A3(n_1_0_276), .A4(n_1_0_275), .ZN(n_1_0_274) + ); + AOI22_X1_LVT i_1_0_288( + .A1(registers_9__ap[14]), .A2(n_1_0_617), .B1(n_1_0_612), .B2(registers_21__ap[14]), + .ZN(n_1_0_273) + ); + AOI22_X1_LVT i_1_0_287( + .A1(registers_14__ap[14]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[14]), + .ZN(n_1_0_272) + ); + AOI22_X1_LVT i_1_0_286( + .A1(registers_22__ap[14]), .A2(n_1_0_642), .B1(n_1_0_633), .B2(registers_19__ap[14]), + .ZN(n_1_0_271) + ); + AOI22_X1_LVT i_1_0_285( + .A1(registers_27__ap[14]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[14]), + .ZN(n_1_0_270) + ); + NAND4_X1_LVT i_1_0_284( + .A1(n_1_0_273), .A2(n_1_0_272), .A3(n_1_0_271), .A4(n_1_0_270), .ZN(n_1_0_269) + ); + NOR2_X1_LVT i_1_0_283( + .A1(n_1_0_274), .A2(n_1_0_269), .ZN(n_1_0_268) + ); + NAND4_X1_LVT i_1_0_282( + .A1(n_1_0_286), .A2(n_1_0_285), .A3(n_1_0_279), .A4(n_1_0_268), .ZN(RRs2[14]) + ); + AOI22_X1_LVT i_1_0_281( + .A1(registers_18__ap[13]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[13]), + .ZN(n_1_0_267) + ); + AOI22_X1_LVT i_1_0_280( + .A1(registers_12__ap[13]), .A2(n_1_0_632), .B1(n_1_0_629), .B2(registers_17__ap[13]), + .ZN(n_1_0_266) + ); + AOI22_X1_LVT i_1_0_279( + .A1(registers_7__ap[13]), .A2(n_1_0_623), .B1(n_1_0_614), .B2(registers_16__ap[13]), + .ZN(n_1_0_265) + ); + NAND3_X1_LVT i_1_0_277( + .A1(n_1_0_267), .A2(n_1_0_266), .A3(n_1_0_265), .ZN(n_1_0_263) + ); + AOI221_X1_LVT i_1_0_276( + .A(n_1_0_263), .B1(n_1_0_642), .B2(registers_22__ap[13]), .C1(registers_5__ap[13]), + .C2(n_1_0_635), .ZN(n_1_0_262) + ); + AOI22_X1_LVT i_1_0_278( + .A1(registers_13__ap[13]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[13]), + .ZN(n_1_0_264) + ); + AOI222_X1_LVT i_1_0_275( + .A1(registers_26__ap[13]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[13]), + .C1(n_1_0_620), .C2(registers_25__ap[13]), .ZN(n_1_0_261) + ); + AOI22_X1_LVT i_1_0_274( + .A1(registers_28__ap[13]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[13]), + .ZN(n_1_0_260) + ); + NAND3_X1_LVT i_1_0_273( + .A1(n_1_0_264), .A2(n_1_0_261), .A3(n_1_0_260), .ZN(n_1_0_259) + ); + AOI22_X1_LVT i_1_0_272( + .A1(registers_1__ap[13]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[13]), + .ZN(n_1_0_258) + ); + AOI22_X1_LVT i_1_0_271( + .A1(registers_19__ap[13]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[13]), + .ZN(n_1_0_257) + ); + AOI22_X1_LVT i_1_0_270( + .A1(registers_14__ap[13]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[13]), + .ZN(n_1_0_256) + ); + AOI22_X1_LVT i_1_0_269( + .A1(registers_27__ap[13]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[13]), + .ZN(n_1_0_255) + ); + NAND4_X1_LVT i_1_0_268( + .A1(n_1_0_258), .A2(n_1_0_257), .A3(n_1_0_256), .A4(n_1_0_255), .ZN(n_1_0_254) + ); + AOI22_X1_LVT i_1_0_267( + .A1(registers_24__ap[13]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[13]), + .ZN(n_1_0_253) + ); + AOI22_X1_LVT i_1_0_266( + .A1(registers_4__ap[13]), .A2(n_1_0_638), .B1(n_1_0_637), .B2(registers_31__ap[13]), + .ZN(n_1_0_252) + ); + AOI22_X1_LVT i_1_0_265( + .A1(registers_29__ap[13]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[13]), + .ZN(n_1_0_251) + ); + AOI22_X1_LVT i_1_0_264( + .A1(registers_15__ap[13]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[13]), + .ZN(n_1_0_250) + ); + NAND4_X1_LVT i_1_0_263( + .A1(n_1_0_253), .A2(n_1_0_252), .A3(n_1_0_251), .A4(n_1_0_250), .ZN(n_1_0_249) + ); + NOR3_X1_LVT i_1_0_262( + .A1(n_1_0_259), .A2(n_1_0_254), .A3(n_1_0_249), .ZN(n_1_0_248) + ); + NAND2_X1_LVT i_1_0_261( + .A1(n_1_0_262), .A2(n_1_0_248), .ZN(RRs2[13]) + ); + AOI22_X1_LVT i_1_0_260( + .A1(registers_18__ap[12]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[12]), + .ZN(n_1_0_247) + ); + AOI22_X1_LVT i_1_0_259( + .A1(registers_12__ap[12]), .A2(n_1_0_632), .B1(n_1_0_629), .B2(registers_17__ap[12]), + .ZN(n_1_0_246) + ); + AOI22_X1_LVT i_1_0_258( + .A1(registers_5__ap[12]), .A2(n_1_0_635), .B1(n_1_0_623), .B2(registers_7__ap[12]), + .ZN(n_1_0_245) + ); + NAND3_X1_LVT i_1_0_256( + .A1(n_1_0_247), .A2(n_1_0_246), .A3(n_1_0_245), .ZN(n_1_0_243) + ); + AOI221_X1_LVT i_1_0_255( + .A(n_1_0_243), .B1(n_1_0_642), .B2(registers_22__ap[12]), .C1(registers_16__ap[12]), + .C2(n_1_0_614), .ZN(n_1_0_242) + ); + AOI22_X1_LVT i_1_0_257( + .A1(registers_13__ap[12]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[12]), + .ZN(n_1_0_244) + ); + AOI222_X1_LVT i_1_0_254( + .A1(registers_26__ap[12]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[12]), + .C1(n_1_0_620), .C2(registers_25__ap[12]), .ZN(n_1_0_241) + ); + AOI22_X1_LVT i_1_0_253( + .A1(registers_28__ap[12]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[12]), + .ZN(n_1_0_240) + ); + NAND3_X1_LVT i_1_0_252( + .A1(n_1_0_244), .A2(n_1_0_241), .A3(n_1_0_240), .ZN(n_1_0_239) + ); + AOI22_X1_LVT i_1_0_251( + .A1(registers_1__ap[12]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[12]), + .ZN(n_1_0_238) + ); + AOI22_X1_LVT i_1_0_250( + .A1(registers_19__ap[12]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[12]), + .ZN(n_1_0_237) + ); + AOI22_X1_LVT i_1_0_249( + .A1(registers_14__ap[12]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[12]), + .ZN(n_1_0_236) + ); + AOI22_X1_LVT i_1_0_248( + .A1(registers_27__ap[12]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[12]), + .ZN(n_1_0_235) + ); + NAND4_X1_LVT i_1_0_247( + .A1(n_1_0_238), .A2(n_1_0_237), .A3(n_1_0_236), .A4(n_1_0_235), .ZN(n_1_0_234) + ); + AOI22_X1_LVT i_1_0_246( + .A1(registers_24__ap[12]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[12]), + .ZN(n_1_0_233) + ); + AOI22_X1_LVT i_1_0_245( + .A1(registers_4__ap[12]), .A2(n_1_0_638), .B1(n_1_0_637), .B2(registers_31__ap[12]), + .ZN(n_1_0_232) + ); + AOI22_X1_LVT i_1_0_244( + .A1(registers_29__ap[12]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[12]), + .ZN(n_1_0_231) + ); + AOI22_X1_LVT i_1_0_243( + .A1(registers_15__ap[12]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[12]), + .ZN(n_1_0_230) + ); + NAND4_X1_LVT i_1_0_242( + .A1(n_1_0_233), .A2(n_1_0_232), .A3(n_1_0_231), .A4(n_1_0_230), .ZN(n_1_0_229) + ); + NOR3_X1_LVT i_1_0_241( + .A1(n_1_0_239), .A2(n_1_0_234), .A3(n_1_0_229), .ZN(n_1_0_228) + ); + NAND2_X1_LVT i_1_0_240( + .A1(n_1_0_242), .A2(n_1_0_228), .ZN(RRs2[12]) + ); + AOI22_X1_LVT i_1_0_238( + .A1(registers_29__ap[11]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[11]), + .ZN(n_1_0_226) + ); + AOI22_X1_LVT i_1_0_239( + .A1(registers_27__ap[11]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[11]), + .ZN(n_1_0_227) + ); + AOI22_X1_LVT i_1_0_237( + .A1(registers_1__ap[11]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[11]), + .ZN(n_1_0_225) + ); + AOI22_X1_LVT i_1_0_236( + .A1(registers_5__ap[11]), .A2(n_1_0_635), .B1(n_1_0_615), .B2(registers_23__ap[11]), + .ZN(n_1_0_224) + ); + NAND3_X1_LVT i_1_0_235( + .A1(n_1_0_227), .A2(n_1_0_225), .A3(n_1_0_224), .ZN(n_1_0_223) + ); + AOI221_X1_LVT i_1_0_234( + .A(n_1_0_223), .B1(n_1_0_637), .B2(registers_31__ap[11]), .C1(registers_16__ap[11]), + .C2(n_1_0_614), .ZN(n_1_0_222) + ); + AOI222_X1_LVT i_1_0_233( + .A1(registers_8__ap[11]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[11]), + .C1(n_1_0_622), .C2(registers_30__ap[11]), .ZN(n_1_0_221) + ); + NAND3_X1_LVT i_1_0_232( + .A1(n_1_0_226), .A2(n_1_0_222), .A3(n_1_0_221), .ZN(n_1_0_220) + ); + AOI221_X1_LVT i_1_0_231( + .A(n_1_0_220), .B1(n_1_0_638), .B2(registers_4__ap[11]), .C1(registers_28__ap[11]), + .C2(n_1_0_634), .ZN(n_1_0_219) + ); + AOI22_X1_LVT i_1_0_230( + .A1(registers_18__ap[11]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[11]), + .ZN(n_1_0_218) + ); + AOI22_X1_LVT i_1_0_229( + .A1(registers_12__ap[11]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[11]), + .ZN(n_1_0_217) + ); + AOI22_X1_LVT i_1_0_228( + .A1(registers_22__ap[11]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[11]), + .ZN(n_1_0_216) + ); + NAND3_X1_LVT i_1_0_227( + .A1(n_1_0_218), .A2(n_1_0_217), .A3(n_1_0_216), .ZN(n_1_0_215) + ); + AOI221_X1_LVT i_1_0_226( + .A(n_1_0_215), .B1(n_1_0_613), .B2(registers_20__ap[11]), .C1(registers_17__ap[11]), + .C2(n_1_0_629), .ZN(n_1_0_214) + ); + AOI22_X1_LVT i_1_0_225( + .A1(registers_13__ap[11]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[11]), + .ZN(n_1_0_213) + ); + AOI22_X1_LVT i_1_0_224( + .A1(registers_7__ap[11]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[11]), + .ZN(n_1_0_212) + ); + AOI22_X1_LVT i_1_0_223( + .A1(registers_19__ap[11]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[11]), + .ZN(n_1_0_211) + ); + NAND3_X1_LVT i_1_0_222( + .A1(n_1_0_213), .A2(n_1_0_212), .A3(n_1_0_211), .ZN(n_1_0_210) + ); + AOI221_X1_LVT i_1_0_221( + .A(n_1_0_210), .B1(n_1_0_611), .B2(registers_11__ap[11]), .C1(registers_2__ap[11]), + .C2(n_1_0_618), .ZN(n_1_0_209) + ); + NAND3_X1_LVT i_1_0_220( + .A1(n_1_0_219), .A2(n_1_0_214), .A3(n_1_0_209), .ZN(RRs2[11]) + ); + AOI22_X1_LVT i_1_0_219( + .A1(registers_28__ap[10]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[10]), + .ZN(n_1_0_208) + ); + AOI222_X1_LVT i_1_0_218( + .A1(registers_26__ap[10]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[10]), + .C1(registers_25__ap[10]), .C2(n_1_0_620), .ZN(n_1_0_207) + ); + AOI22_X1_LVT i_1_0_217( + .A1(registers_13__ap[10]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[10]), + .ZN(n_1_0_206) + ); + AOI22_X1_LVT i_1_0_216( + .A1(registers_24__ap[10]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[10]), + .ZN(n_1_0_205) + ); + AOI22_X1_LVT i_1_0_215( + .A1(registers_15__ap[10]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[10]), + .ZN(n_1_0_204) + ); + AOI22_X1_LVT i_1_0_214( + .A1(registers_31__ap[10]), .A2(n_1_0_637), .B1(n_1_0_629), .B2(registers_17__ap[10]), + .ZN(n_1_0_203) + ); + AOI22_X1_LVT i_1_0_213( + .A1(registers_29__ap[10]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[10]), + .ZN(n_1_0_202) + ); + NAND4_X1_LVT i_1_0_212( + .A1(n_1_0_205), .A2(n_1_0_204), .A3(n_1_0_203), .A4(n_1_0_202), .ZN(n_1_0_201) + ); + AOI22_X1_LVT i_1_0_211( + .A1(registers_18__ap[10]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[10]), + .ZN(n_1_0_200) + ); + AOI22_X1_LVT i_1_0_210( + .A1(registers_4__ap[10]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[10]), + .ZN(n_1_0_199) + ); + AOI22_X1_LVT i_1_0_209( + .A1(registers_7__ap[10]), .A2(n_1_0_623), .B1(n_1_0_614), .B2(registers_16__ap[10]), + .ZN(n_1_0_198) + ); + AOI22_X1_LVT i_1_0_208( + .A1(registers_22__ap[10]), .A2(n_1_0_642), .B1(n_1_0_635), .B2(registers_5__ap[10]), + .ZN(n_1_0_197) + ); + NAND4_X1_LVT i_1_0_207( + .A1(n_1_0_200), .A2(n_1_0_199), .A3(n_1_0_198), .A4(n_1_0_197), .ZN(n_1_0_196) + ); + AOI22_X1_LVT i_1_0_206( + .A1(registers_1__ap[10]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[10]), + .ZN(n_1_0_195) + ); + AOI22_X1_LVT i_1_0_205( + .A1(registers_14__ap[10]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[10]), + .ZN(n_1_0_194) + ); + AOI22_X1_LVT i_1_0_204( + .A1(registers_19__ap[10]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[10]), + .ZN(n_1_0_193) + ); + AOI22_X1_LVT i_1_0_203( + .A1(registers_27__ap[10]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[10]), + .ZN(n_1_0_192) + ); + NAND4_X1_LVT i_1_0_202( + .A1(n_1_0_195), .A2(n_1_0_194), .A3(n_1_0_193), .A4(n_1_0_192), .ZN(n_1_0_191) + ); + NOR3_X1_LVT i_1_0_201( + .A1(n_1_0_201), .A2(n_1_0_196), .A3(n_1_0_191), .ZN(n_1_0_190) + ); + NAND4_X1_LVT i_1_0_200( + .A1(n_1_0_208), .A2(n_1_0_207), .A3(n_1_0_206), .A4(n_1_0_190), .ZN(RRs2[10]) + ); + AOI22_X1_LVT i_1_0_196( + .A1(registers_13__ap[9]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[9]), + .ZN(n_1_0_186) + ); + AOI22_X1_LVT i_1_0_199( + .A1(registers_29__ap[9]), .A2(n_1_0_649), .B1(n_1_0_636), .B2(registers_27__ap[9]), + .ZN(n_1_0_189) + ); + AOI22_X1_LVT i_1_0_195( + .A1(registers_24__ap[9]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[9]), + .ZN(n_1_0_185) + ); + AOI22_X1_LVT i_1_0_198( + .A1(registers_31__ap[9]), .A2(n_1_0_637), .B1(n_1_0_627), .B2(registers_15__ap[9]), + .ZN(n_1_0_188) + ); + INV_X1_LVT i_1_0_197( + .A(n_1_0_188), .ZN(n_1_0_187) + ); + AOI221_X1_LVT i_1_0_194( + .A(n_1_0_187), .B1(n_1_0_615), .B2(registers_23__ap[9]), .C1(registers_4__ap[9]), + .C2(n_1_0_638), .ZN(n_1_0_184) + ); + AOI222_X1_LVT i_1_0_193( + .A1(registers_18__ap[9]), .A2(n_1_0_646), .B1(n_1_0_624), .B2(registers_10__ap[9]), + .C1(registers_25__ap[9]), .C2(n_1_0_620), .ZN(n_1_0_183) + ); + NAND4_X1_LVT i_1_0_192( + .A1(n_1_0_189), .A2(n_1_0_185), .A3(n_1_0_184), .A4(n_1_0_183), .ZN(n_1_0_182) + ); + AOI221_X1_LVT i_1_0_191( + .A(n_1_0_182), .B1(n_1_0_626), .B2(registers_8__ap[9]), .C1(registers_28__ap[9]), + .C2(n_1_0_634), .ZN(n_1_0_181) + ); + AOI22_X1_LVT i_1_0_190( + .A1(registers_26__ap[9]), .A2(n_1_0_640), .B1(n_1_0_622), .B2(registers_30__ap[9]), + .ZN(n_1_0_180) + ); + AOI22_X1_LVT i_1_0_189( + .A1(registers_12__ap[9]), .A2(n_1_0_632), .B1(n_1_0_629), .B2(registers_17__ap[9]), + .ZN(n_1_0_179) + ); + AOI22_X1_LVT i_1_0_188( + .A1(registers_5__ap[9]), .A2(n_1_0_635), .B1(n_1_0_623), .B2(registers_7__ap[9]), + .ZN(n_1_0_178) + ); + NAND3_X1_LVT i_1_0_187( + .A1(n_1_0_180), .A2(n_1_0_179), .A3(n_1_0_178), .ZN(n_1_0_177) + ); + AOI221_X1_LVT i_1_0_186( + .A(n_1_0_177), .B1(n_1_0_642), .B2(registers_22__ap[9]), .C1(registers_16__ap[9]), + .C2(n_1_0_614), .ZN(n_1_0_176) + ); + AOI22_X1_LVT i_1_0_185( + .A1(registers_1__ap[9]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[9]), + .ZN(n_1_0_175) + ); + AOI22_X1_LVT i_1_0_184( + .A1(registers_14__ap[9]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[9]), + .ZN(n_1_0_174) + ); + AOI22_X1_LVT i_1_0_183( + .A1(registers_19__ap[9]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[9]), + .ZN(n_1_0_173) + ); + NAND3_X1_LVT i_1_0_182( + .A1(n_1_0_175), .A2(n_1_0_174), .A3(n_1_0_173), .ZN(n_1_0_172) + ); + AOI221_X1_LVT i_1_0_181( + .A(n_1_0_172), .B1(n_1_0_611), .B2(registers_11__ap[9]), .C1(registers_2__ap[9]), + .C2(n_1_0_618), .ZN(n_1_0_171) + ); + NAND4_X1_LVT i_1_0_180( + .A1(n_1_0_186), .A2(n_1_0_181), .A3(n_1_0_176), .A4(n_1_0_171), .ZN(RRs2[9]) + ); + AOI22_X1_LVT i_1_0_179( + .A1(registers_28__ap[8]), .A2(n_1_0_634), .B1(n_1_0_629), .B2(registers_17__ap[8]), + .ZN(n_1_0_170) + ); + AOI222_X1_LVT i_1_0_178( + .A1(registers_26__ap[8]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[8]), + .C1(n_1_0_626), .C2(registers_8__ap[8]), .ZN(n_1_0_169) + ); + AOI22_X1_LVT i_1_0_177( + .A1(registers_29__ap[8]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[8]), + .ZN(n_1_0_168) + ); + AOI22_X1_LVT i_1_0_176( + .A1(registers_1__ap[8]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[8]), + .ZN(n_1_0_167) + ); + AOI22_X1_LVT i_1_0_175( + .A1(registers_5__ap[8]), .A2(n_1_0_635), .B1(n_1_0_610), .B2(registers_3__ap[8]), + .ZN(n_1_0_166) + ); + AOI22_X1_LVT i_1_0_174( + .A1(registers_31__ap[8]), .A2(n_1_0_637), .B1(n_1_0_614), .B2(registers_16__ap[8]), + .ZN(n_1_0_165) + ); + AOI22_X1_LVT i_1_0_173( + .A1(registers_15__ap[8]), .A2(n_1_0_627), .B1(n_1_0_615), .B2(registers_23__ap[8]), + .ZN(n_1_0_164) + ); + NAND4_X1_LVT i_1_0_172( + .A1(n_1_0_167), .A2(n_1_0_166), .A3(n_1_0_165), .A4(n_1_0_164), .ZN(n_1_0_163) + ); + AOI22_X1_LVT i_1_0_171( + .A1(registers_18__ap[8]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[8]), + .ZN(n_1_0_162) + ); + AOI22_X1_LVT i_1_0_170( + .A1(registers_4__ap[8]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[8]), + .ZN(n_1_0_161) + ); + AOI22_X1_LVT i_1_0_169( + .A1(registers_22__ap[8]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[8]), + .ZN(n_1_0_160) + ); + AOI22_X1_LVT i_1_0_168( + .A1(registers_12__ap[8]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[8]), + .ZN(n_1_0_159) + ); + NAND4_X1_LVT i_1_0_167( + .A1(n_1_0_162), .A2(n_1_0_161), .A3(n_1_0_160), .A4(n_1_0_159), .ZN(n_1_0_158) + ); + AOI22_X1_LVT i_1_0_166( + .A1(registers_13__ap[8]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[8]), + .ZN(n_1_0_157) + ); + AOI22_X1_LVT i_1_0_165( + .A1(registers_7__ap[8]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[8]), + .ZN(n_1_0_156) + ); + AOI22_X1_LVT i_1_0_164( + .A1(registers_19__ap[8]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[8]), + .ZN(n_1_0_155) + ); + AOI22_X1_LVT i_1_0_163( + .A1(registers_27__ap[8]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[8]), + .ZN(n_1_0_154) + ); + NAND4_X1_LVT i_1_0_162( + .A1(n_1_0_157), .A2(n_1_0_156), .A3(n_1_0_155), .A4(n_1_0_154), .ZN(n_1_0_153) + ); + NOR3_X1_LVT i_1_0_161( + .A1(n_1_0_163), .A2(n_1_0_158), .A3(n_1_0_153), .ZN(n_1_0_152) + ); + NAND4_X1_LVT i_1_0_160( + .A1(n_1_0_170), .A2(n_1_0_169), .A3(n_1_0_168), .A4(n_1_0_152), .ZN(RRs2[8]) + ); + AOI22_X1_LVT i_1_0_159( + .A1(registers_28__ap[7]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[7]), + .ZN(n_1_0_151) + ); + AOI222_X1_LVT i_1_0_158( + .A1(registers_26__ap[7]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[7]), + .C1(registers_25__ap[7]), .C2(n_1_0_620), .ZN(n_1_0_150) + ); + AOI22_X1_LVT i_1_0_157( + .A1(registers_24__ap[7]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[7]), + .ZN(n_1_0_149) + ); + AOI22_X1_LVT i_1_0_156( + .A1(registers_15__ap[7]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[7]), + .ZN(n_1_0_148) + ); + AOI22_X1_LVT i_1_0_155( + .A1(registers_31__ap[7]), .A2(n_1_0_637), .B1(n_1_0_629), .B2(registers_17__ap[7]), + .ZN(n_1_0_147) + ); + AOI22_X1_LVT i_1_0_154( + .A1(registers_29__ap[7]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[7]), + .ZN(n_1_0_146) + ); + NAND4_X1_LVT i_1_0_153( + .A1(n_1_0_149), .A2(n_1_0_148), .A3(n_1_0_147), .A4(n_1_0_146), .ZN(n_1_0_145) + ); + AOI221_X1_LVT i_1_0_152( + .A(n_1_0_145), .B1(n_1_0_612), .B2(registers_21__ap[7]), .C1(registers_13__ap[7]), + .C2(n_1_0_631), .ZN(n_1_0_144) + ); + AOI22_X1_LVT i_1_0_151( + .A1(registers_18__ap[7]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[7]), + .ZN(n_1_0_143) + ); + AOI22_X1_LVT i_1_0_150( + .A1(registers_4__ap[7]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[7]), + .ZN(n_1_0_142) + ); + AOI22_X1_LVT i_1_0_149( + .A1(registers_5__ap[7]), .A2(n_1_0_635), .B1(n_1_0_623), .B2(registers_7__ap[7]), + .ZN(n_1_0_141) + ); + AOI22_X1_LVT i_1_0_148( + .A1(registers_22__ap[7]), .A2(n_1_0_642), .B1(n_1_0_614), .B2(registers_16__ap[7]), + .ZN(n_1_0_140) + ); + NAND4_X1_LVT i_1_0_147( + .A1(n_1_0_143), .A2(n_1_0_142), .A3(n_1_0_141), .A4(n_1_0_140), .ZN(n_1_0_139) + ); + AOI22_X1_LVT i_1_0_146( + .A1(registers_1__ap[7]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[7]), + .ZN(n_1_0_138) + ); + AOI22_X1_LVT i_1_0_145( + .A1(registers_14__ap[7]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[7]), + .ZN(n_1_0_137) + ); + AOI22_X1_LVT i_1_0_144( + .A1(registers_19__ap[7]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[7]), + .ZN(n_1_0_136) + ); + AOI22_X1_LVT i_1_0_143( + .A1(registers_27__ap[7]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[7]), + .ZN(n_1_0_135) + ); + NAND4_X1_LVT i_1_0_142( + .A1(n_1_0_138), .A2(n_1_0_137), .A3(n_1_0_136), .A4(n_1_0_135), .ZN(n_1_0_134) + ); + NOR2_X1_LVT i_1_0_141( + .A1(n_1_0_139), .A2(n_1_0_134), .ZN(n_1_0_133) + ); + NAND4_X1_LVT i_1_0_140( + .A1(n_1_0_151), .A2(n_1_0_150), .A3(n_1_0_144), .A4(n_1_0_133), .ZN(RRs2[7]) + ); + AOI22_X1_LVT i_1_0_136( + .A1(registers_13__ap[6]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[6]), + .ZN(n_1_0_129) + ); + AOI22_X1_LVT i_1_0_139( + .A1(registers_29__ap[6]), .A2(n_1_0_649), .B1(n_1_0_636), .B2(registers_27__ap[6]), + .ZN(n_1_0_132) + ); + AOI22_X1_LVT i_1_0_135( + .A1(registers_24__ap[6]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[6]), + .ZN(n_1_0_128) + ); + AOI22_X1_LVT i_1_0_138( + .A1(registers_31__ap[6]), .A2(n_1_0_637), .B1(n_1_0_627), .B2(registers_15__ap[6]), + .ZN(n_1_0_131) + ); + INV_X1_LVT i_1_0_137( + .A(n_1_0_131), .ZN(n_1_0_130) + ); + AOI221_X1_LVT i_1_0_134( + .A(n_1_0_130), .B1(n_1_0_638), .B2(registers_4__ap[6]), .C1(registers_23__ap[6]), + .C2(n_1_0_615), .ZN(n_1_0_127) + ); + AOI222_X1_LVT i_1_0_133( + .A1(registers_18__ap[6]), .A2(n_1_0_646), .B1(n_1_0_620), .B2(registers_25__ap[6]), + .C1(n_1_0_624), .C2(registers_10__ap[6]), .ZN(n_1_0_126) + ); + NAND4_X1_LVT i_1_0_132( + .A1(n_1_0_132), .A2(n_1_0_128), .A3(n_1_0_127), .A4(n_1_0_126), .ZN(n_1_0_125) + ); + AOI221_X1_LVT i_1_0_131( + .A(n_1_0_125), .B1(n_1_0_626), .B2(registers_8__ap[6]), .C1(registers_28__ap[6]), + .C2(n_1_0_634), .ZN(n_1_0_124) + ); + AOI22_X1_LVT i_1_0_130( + .A1(registers_26__ap[6]), .A2(n_1_0_640), .B1(n_1_0_622), .B2(registers_30__ap[6]), + .ZN(n_1_0_123) + ); + AOI22_X1_LVT i_1_0_129( + .A1(registers_12__ap[6]), .A2(n_1_0_632), .B1(n_1_0_629), .B2(registers_17__ap[6]), + .ZN(n_1_0_122) + ); + AOI22_X1_LVT i_1_0_128( + .A1(registers_7__ap[6]), .A2(n_1_0_623), .B1(n_1_0_614), .B2(registers_16__ap[6]), + .ZN(n_1_0_121) + ); + NAND3_X1_LVT i_1_0_127( + .A1(n_1_0_123), .A2(n_1_0_122), .A3(n_1_0_121), .ZN(n_1_0_120) + ); + AOI221_X1_LVT i_1_0_126( + .A(n_1_0_120), .B1(n_1_0_642), .B2(registers_22__ap[6]), .C1(registers_5__ap[6]), + .C2(n_1_0_635), .ZN(n_1_0_119) + ); + AOI22_X1_LVT i_1_0_125( + .A1(registers_1__ap[6]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[6]), + .ZN(n_1_0_118) + ); + AOI22_X1_LVT i_1_0_124( + .A1(registers_14__ap[6]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[6]), + .ZN(n_1_0_117) + ); + AOI22_X1_LVT i_1_0_123( + .A1(registers_19__ap[6]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[6]), + .ZN(n_1_0_116) + ); + NAND3_X1_LVT i_1_0_122( + .A1(n_1_0_118), .A2(n_1_0_117), .A3(n_1_0_116), .ZN(n_1_0_115) + ); + AOI221_X1_LVT i_1_0_121( + .A(n_1_0_115), .B1(n_1_0_618), .B2(registers_2__ap[6]), .C1(registers_11__ap[6]), + .C2(n_1_0_611), .ZN(n_1_0_114) + ); + NAND4_X1_LVT i_1_0_120( + .A1(n_1_0_129), .A2(n_1_0_124), .A3(n_1_0_119), .A4(n_1_0_114), .ZN(RRs2[6]) + ); + AOI22_X1_LVT i_1_0_118( + .A1(registers_28__ap[5]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[5]), + .ZN(n_1_0_112) + ); + AOI22_X1_LVT i_1_0_119( + .A1(registers_31__ap[5]), .A2(n_1_0_637), .B1(n_1_0_627), .B2(registers_15__ap[5]), + .ZN(n_1_0_113) + ); + AOI22_X1_LVT i_1_0_117( + .A1(registers_24__ap[5]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[5]), + .ZN(n_1_0_111) + ); + AOI22_X1_LVT i_1_0_116( + .A1(registers_17__ap[5]), .A2(n_1_0_629), .B1(n_1_0_615), .B2(registers_23__ap[5]), + .ZN(n_1_0_110) + ); + NAND3_X1_LVT i_1_0_115( + .A1(n_1_0_113), .A2(n_1_0_111), .A3(n_1_0_110), .ZN(n_1_0_109) + ); + AOI221_X1_LVT i_1_0_114( + .A(n_1_0_109), .B1(n_1_0_636), .B2(registers_27__ap[5]), .C1(registers_29__ap[5]), + .C2(n_1_0_649), .ZN(n_1_0_108) + ); + AOI222_X1_LVT i_1_0_113( + .A1(registers_10__ap[5]), .A2(n_1_0_624), .B1(n_1_0_620), .B2(registers_25__ap[5]), + .C1(registers_18__ap[5]), .C2(n_1_0_646), .ZN(n_1_0_107) + ); + NAND3_X1_LVT i_1_0_112( + .A1(n_1_0_112), .A2(n_1_0_108), .A3(n_1_0_107), .ZN(n_1_0_106) + ); + AOI221_X1_LVT i_1_0_111( + .A(n_1_0_106), .B1(n_1_0_612), .B2(registers_21__ap[5]), .C1(registers_13__ap[5]), + .C2(n_1_0_631), .ZN(n_1_0_105) + ); + AOI22_X1_LVT i_1_0_110( + .A1(registers_26__ap[5]), .A2(n_1_0_640), .B1(n_1_0_622), .B2(registers_30__ap[5]), + .ZN(n_1_0_104) + ); + AOI22_X1_LVT i_1_0_109( + .A1(registers_4__ap[5]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[5]), + .ZN(n_1_0_103) + ); + AOI22_X1_LVT i_1_0_108( + .A1(registers_5__ap[5]), .A2(n_1_0_635), .B1(n_1_0_623), .B2(registers_7__ap[5]), + .ZN(n_1_0_102) + ); + NAND3_X1_LVT i_1_0_107( + .A1(n_1_0_104), .A2(n_1_0_103), .A3(n_1_0_102), .ZN(n_1_0_101) + ); + AOI221_X1_LVT i_1_0_106( + .A(n_1_0_101), .B1(n_1_0_642), .B2(registers_22__ap[5]), .C1(registers_16__ap[5]), + .C2(n_1_0_614), .ZN(n_1_0_100) + ); + AOI22_X1_LVT i_1_0_105( + .A1(registers_1__ap[5]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[5]), + .ZN(n_1_0_99) + ); + AOI22_X1_LVT i_1_0_104( + .A1(registers_14__ap[5]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[5]), + .ZN(n_1_0_98) + ); + AOI22_X1_LVT i_1_0_103( + .A1(registers_19__ap[5]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[5]), + .ZN(n_1_0_97) + ); + NAND3_X1_LVT i_1_0_102( + .A1(n_1_0_99), .A2(n_1_0_98), .A3(n_1_0_97), .ZN(n_1_0_96) + ); + AOI221_X1_LVT i_1_0_101( + .A(n_1_0_96), .B1(n_1_0_611), .B2(registers_11__ap[5]), .C1(registers_2__ap[5]), + .C2(n_1_0_618), .ZN(n_1_0_95) + ); + NAND3_X1_LVT i_1_0_100( + .A1(n_1_0_105), .A2(n_1_0_100), .A3(n_1_0_95), .ZN(RRs2[5]) + ); + AOI22_X1_LVT i_1_0_99( + .A1(registers_4__ap[4]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[4]), + .ZN(n_1_0_94) + ); + AOI222_X1_LVT i_1_0_98( + .A1(registers_8__ap[4]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[4]), + .C1(n_1_0_622), .C2(registers_30__ap[4]), .ZN(n_1_0_93) + ); + AOI22_X1_LVT i_1_0_97( + .A1(registers_29__ap[4]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[4]), + .ZN(n_1_0_92) + ); + AOI22_X1_LVT i_1_0_96( + .A1(registers_1__ap[4]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[4]), + .ZN(n_1_0_91) + ); + AOI22_X1_LVT i_1_0_95( + .A1(registers_27__ap[4]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[4]), + .ZN(n_1_0_90) + ); + AOI22_X1_LVT i_1_0_94( + .A1(registers_23__ap[4]), .A2(n_1_0_615), .B1(n_1_0_614), .B2(registers_16__ap[4]), + .ZN(n_1_0_89) + ); + AOI22_X1_LVT i_1_0_93( + .A1(registers_31__ap[4]), .A2(n_1_0_637), .B1(n_1_0_635), .B2(registers_5__ap[4]), + .ZN(n_1_0_88) + ); + NAND4_X1_LVT i_1_0_92( + .A1(n_1_0_91), .A2(n_1_0_90), .A3(n_1_0_89), .A4(n_1_0_88), .ZN(n_1_0_87) + ); + AOI22_X1_LVT i_1_0_91( + .A1(registers_18__ap[4]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[4]), + .ZN(n_1_0_86) + ); + AOI22_X1_LVT i_1_0_90( + .A1(registers_12__ap[4]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[4]), + .ZN(n_1_0_85) + ); + AOI22_X1_LVT i_1_0_89( + .A1(registers_22__ap[4]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[4]), + .ZN(n_1_0_84) + ); + AOI22_X1_LVT i_1_0_88( + .A1(registers_17__ap[4]), .A2(n_1_0_629), .B1(n_1_0_613), .B2(registers_20__ap[4]), + .ZN(n_1_0_83) + ); + NAND4_X1_LVT i_1_0_87( + .A1(n_1_0_86), .A2(n_1_0_85), .A3(n_1_0_84), .A4(n_1_0_83), .ZN(n_1_0_82) + ); + AOI22_X1_LVT i_1_0_86( + .A1(registers_13__ap[4]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[4]), + .ZN(n_1_0_81) + ); + AOI22_X1_LVT i_1_0_85( + .A1(registers_7__ap[4]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[4]), + .ZN(n_1_0_80) + ); + AOI22_X1_LVT i_1_0_84( + .A1(registers_19__ap[4]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[4]), + .ZN(n_1_0_79) + ); + AOI22_X1_LVT i_1_0_83( + .A1(registers_2__ap[4]), .A2(n_1_0_618), .B1(n_1_0_611), .B2(registers_11__ap[4]), + .ZN(n_1_0_78) + ); + NAND4_X1_LVT i_1_0_82( + .A1(n_1_0_81), .A2(n_1_0_80), .A3(n_1_0_79), .A4(n_1_0_78), .ZN(n_1_0_77) + ); + NOR3_X1_LVT i_1_0_81( + .A1(n_1_0_87), .A2(n_1_0_82), .A3(n_1_0_77), .ZN(n_1_0_76) + ); + NAND4_X1_LVT i_1_0_80( + .A1(n_1_0_94), .A2(n_1_0_93), .A3(n_1_0_92), .A4(n_1_0_76), .ZN(RRs2[4]) + ); + AOI22_X1_LVT i_1_0_78( + .A1(registers_29__ap[3]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[3]), + .ZN(n_1_0_74) + ); + AOI22_X1_LVT i_1_0_79( + .A1(registers_27__ap[3]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[3]), + .ZN(n_1_0_75) + ); + AOI22_X1_LVT i_1_0_77( + .A1(registers_1__ap[3]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[3]), + .ZN(n_1_0_73) + ); + AOI22_X1_LVT i_1_0_76( + .A1(registers_5__ap[3]), .A2(n_1_0_635), .B1(n_1_0_611), .B2(registers_11__ap[3]), + .ZN(n_1_0_72) + ); + NAND3_X1_LVT i_1_0_75( + .A1(n_1_0_75), .A2(n_1_0_73), .A3(n_1_0_72), .ZN(n_1_0_71) + ); + AOI221_X1_LVT i_1_0_74( + .A(n_1_0_71), .B1(n_1_0_614), .B2(registers_16__ap[3]), .C1(registers_31__ap[3]), + .C2(n_1_0_637), .ZN(n_1_0_70) + ); + AOI222_X1_LVT i_1_0_73( + .A1(registers_8__ap[3]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[3]), + .C1(n_1_0_622), .C2(registers_30__ap[3]), .ZN(n_1_0_69) + ); + NAND3_X1_LVT i_1_0_72( + .A1(n_1_0_74), .A2(n_1_0_70), .A3(n_1_0_69), .ZN(n_1_0_68) + ); + AOI221_X1_LVT i_1_0_71( + .A(n_1_0_68), .B1(n_1_0_638), .B2(registers_4__ap[3]), .C1(registers_28__ap[3]), + .C2(n_1_0_634), .ZN(n_1_0_67) + ); + AOI22_X1_LVT i_1_0_70( + .A1(registers_18__ap[3]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[3]), + .ZN(n_1_0_66) + ); + AOI22_X1_LVT i_1_0_69( + .A1(registers_12__ap[3]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[3]), + .ZN(n_1_0_65) + ); + AOI22_X1_LVT i_1_0_68( + .A1(registers_22__ap[3]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[3]), + .ZN(n_1_0_64) + ); + NAND3_X1_LVT i_1_0_67( + .A1(n_1_0_66), .A2(n_1_0_65), .A3(n_1_0_64), .ZN(n_1_0_63) + ); + AOI221_X1_LVT i_1_0_66( + .A(n_1_0_63), .B1(n_1_0_613), .B2(registers_20__ap[3]), .C1(registers_17__ap[3]), + .C2(n_1_0_629), .ZN(n_1_0_62) + ); + AOI22_X1_LVT i_1_0_65( + .A1(registers_13__ap[3]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[3]), + .ZN(n_1_0_61) + ); + AOI22_X1_LVT i_1_0_64( + .A1(registers_7__ap[3]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[3]), + .ZN(n_1_0_60) + ); + AOI22_X1_LVT i_1_0_63( + .A1(registers_19__ap[3]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[3]), + .ZN(n_1_0_59) + ); + NAND3_X1_LVT i_1_0_62( + .A1(n_1_0_61), .A2(n_1_0_60), .A3(n_1_0_59), .ZN(n_1_0_58) + ); + AOI221_X1_LVT i_1_0_61( + .A(n_1_0_58), .B1(n_1_0_618), .B2(registers_2__ap[3]), .C1(registers_23__ap[3]), + .C2(n_1_0_615), .ZN(n_1_0_57) + ); + NAND3_X1_LVT i_1_0_60( + .A1(n_1_0_67), .A2(n_1_0_62), .A3(n_1_0_57), .ZN(RRs2[3]) + ); + AOI22_X1_LVT i_1_0_58( + .A1(registers_29__ap[2]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[2]), + .ZN(n_1_0_55) + ); + AOI22_X1_LVT i_1_0_59( + .A1(registers_27__ap[2]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[2]), + .ZN(n_1_0_56) + ); + AOI22_X1_LVT i_1_0_57( + .A1(registers_1__ap[2]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[2]), + .ZN(n_1_0_54) + ); + AOI22_X1_LVT i_1_0_56( + .A1(registers_5__ap[2]), .A2(n_1_0_635), .B1(n_1_0_615), .B2(registers_23__ap[2]), + .ZN(n_1_0_53) + ); + NAND3_X1_LVT i_1_0_55( + .A1(n_1_0_56), .A2(n_1_0_54), .A3(n_1_0_53), .ZN(n_1_0_52) + ); + AOI221_X1_LVT i_1_0_54( + .A(n_1_0_52), .B1(n_1_0_637), .B2(registers_31__ap[2]), .C1(registers_16__ap[2]), + .C2(n_1_0_614), .ZN(n_1_0_51) + ); + AOI222_X1_LVT i_1_0_53( + .A1(registers_8__ap[2]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[2]), + .C1(n_1_0_622), .C2(registers_30__ap[2]), .ZN(n_1_0_50) + ); + NAND3_X1_LVT i_1_0_52( + .A1(n_1_0_55), .A2(n_1_0_51), .A3(n_1_0_50), .ZN(n_1_0_49) + ); + AOI221_X1_LVT i_1_0_51( + .A(n_1_0_49), .B1(n_1_0_638), .B2(registers_4__ap[2]), .C1(registers_28__ap[2]), + .C2(n_1_0_634), .ZN(n_1_0_48) + ); + AOI22_X1_LVT i_1_0_50( + .A1(registers_18__ap[2]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[2]), + .ZN(n_1_0_47) + ); + AOI22_X1_LVT i_1_0_49( + .A1(registers_12__ap[2]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[2]), + .ZN(n_1_0_46) + ); + AOI22_X1_LVT i_1_0_48( + .A1(registers_22__ap[2]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[2]), + .ZN(n_1_0_45) + ); + NAND3_X1_LVT i_1_0_47( + .A1(n_1_0_47), .A2(n_1_0_46), .A3(n_1_0_45), .ZN(n_1_0_44) + ); + AOI221_X1_LVT i_1_0_46( + .A(n_1_0_44), .B1(n_1_0_629), .B2(registers_17__ap[2]), .C1(registers_20__ap[2]), + .C2(n_1_0_613), .ZN(n_1_0_43) + ); + AOI22_X1_LVT i_1_0_45( + .A1(registers_13__ap[2]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[2]), + .ZN(n_1_0_42) + ); + AOI22_X1_LVT i_1_0_44( + .A1(registers_7__ap[2]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[2]), + .ZN(n_1_0_41) + ); + AOI22_X1_LVT i_1_0_43( + .A1(registers_19__ap[2]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[2]), + .ZN(n_1_0_40) + ); + NAND3_X1_LVT i_1_0_42( + .A1(n_1_0_42), .A2(n_1_0_41), .A3(n_1_0_40), .ZN(n_1_0_39) + ); + AOI221_X1_LVT i_1_0_41( + .A(n_1_0_39), .B1(n_1_0_618), .B2(registers_2__ap[2]), .C1(registers_11__ap[2]), + .C2(n_1_0_611), .ZN(n_1_0_38) + ); + NAND3_X1_LVT i_1_0_40( + .A1(n_1_0_48), .A2(n_1_0_43), .A3(n_1_0_38), .ZN(RRs2[2]) + ); + AOI22_X1_LVT i_1_0_38( + .A1(registers_29__ap[1]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[1]), + .ZN(n_1_0_36) + ); + AOI22_X1_LVT i_1_0_39( + .A1(registers_16__ap[1]), .A2(n_1_0_614), .B1(n_1_0_610), .B2(registers_3__ap[1]), + .ZN(n_1_0_37) + ); + AOI22_X1_LVT i_1_0_37( + .A1(registers_1__ap[1]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[1]), + .ZN(n_1_0_35) + ); + AOI22_X1_LVT i_1_0_36( + .A1(registers_31__ap[1]), .A2(n_1_0_637), .B1(n_1_0_635), .B2(registers_5__ap[1]), + .ZN(n_1_0_34) + ); + NAND3_X1_LVT i_1_0_35( + .A1(n_1_0_37), .A2(n_1_0_35), .A3(n_1_0_34), .ZN(n_1_0_33) + ); + AOI221_X1_LVT i_1_0_34( + .A(n_1_0_33), .B1(n_1_0_627), .B2(registers_15__ap[1]), .C1(registers_23__ap[1]), + .C2(n_1_0_615), .ZN(n_1_0_32) + ); + AOI222_X1_LVT i_1_0_33( + .A1(registers_26__ap[1]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[1]), + .C1(n_1_0_626), .C2(registers_8__ap[1]), .ZN(n_1_0_31) + ); + NAND3_X1_LVT i_1_0_32( + .A1(n_1_0_36), .A2(n_1_0_32), .A3(n_1_0_31), .ZN(n_1_0_30) + ); + AOI221_X1_LVT i_1_0_31( + .A(n_1_0_30), .B1(n_1_0_629), .B2(registers_17__ap[1]), .C1(registers_28__ap[1]), + .C2(n_1_0_634), .ZN(n_1_0_29) + ); + AOI22_X1_LVT i_1_0_30( + .A1(registers_18__ap[1]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[1]), + .ZN(n_1_0_28) + ); + AOI22_X1_LVT i_1_0_29( + .A1(registers_4__ap[1]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[1]), + .ZN(n_1_0_27) + ); + AOI22_X1_LVT i_1_0_28( + .A1(registers_22__ap[1]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[1]), + .ZN(n_1_0_26) + ); + NAND3_X1_LVT i_1_0_27( + .A1(n_1_0_28), .A2(n_1_0_27), .A3(n_1_0_26), .ZN(n_1_0_25) + ); + AOI221_X1_LVT i_1_0_26( + .A(n_1_0_25), .B1(n_1_0_632), .B2(registers_12__ap[1]), .C1(registers_24__ap[1]), + .C2(n_1_0_621), .ZN(n_1_0_24) + ); + AOI22_X1_LVT i_1_0_25( + .A1(registers_13__ap[1]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[1]), + .ZN(n_1_0_23) + ); + AOI22_X1_LVT i_1_0_24( + .A1(registers_7__ap[1]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[1]), + .ZN(n_1_0_22) + ); + AOI22_X1_LVT i_1_0_23( + .A1(registers_19__ap[1]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[1]), + .ZN(n_1_0_21) + ); + NAND3_X1_LVT i_1_0_22( + .A1(n_1_0_23), .A2(n_1_0_22), .A3(n_1_0_21), .ZN(n_1_0_20) + ); + AOI221_X1_LVT i_1_0_21( + .A(n_1_0_20), .B1(n_1_0_611), .B2(registers_11__ap[1]), .C1(registers_27__ap[1]), + .C2(n_1_0_636), .ZN(n_1_0_19) + ); + NAND3_X1_LVT i_1_0_20( + .A1(n_1_0_29), .A2(n_1_0_24), .A3(n_1_0_19), .ZN(RRs2[1]) + ); + AOI22_X1_LVT i_1_0_19( + .A1(registers_4__ap[0]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[0]), + .ZN(n_1_0_18) + ); + AOI222_X1_LVT i_1_0_18( + .A1(registers_8__ap[0]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[0]), + .C1(n_1_0_622), .C2(registers_30__ap[0]), .ZN(n_1_0_17) + ); + AOI22_X1_LVT i_1_0_17( + .A1(registers_29__ap[0]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[0]), + .ZN(n_1_0_16) + ); + AOI22_X1_LVT i_1_0_16( + .A1(registers_1__ap[0]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[0]), + .ZN(n_1_0_15) + ); + AOI22_X1_LVT i_1_0_15( + .A1(registers_27__ap[0]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[0]), + .ZN(n_1_0_14) + ); + AOI22_X1_LVT i_1_0_14( + .A1(registers_23__ap[0]), .A2(n_1_0_615), .B1(n_1_0_614), .B2(registers_16__ap[0]), + .ZN(n_1_0_13) + ); + AOI22_X1_LVT i_1_0_13( + .A1(registers_31__ap[0]), .A2(n_1_0_637), .B1(n_1_0_635), .B2(registers_5__ap[0]), + .ZN(n_1_0_12) + ); + NAND4_X1_LVT i_1_0_12( + .A1(n_1_0_15), .A2(n_1_0_14), .A3(n_1_0_13), .A4(n_1_0_12), .ZN(n_1_0_11) + ); + AOI22_X1_LVT i_1_0_11( + .A1(registers_18__ap[0]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[0]), + .ZN(n_1_0_10) + ); + AOI22_X1_LVT i_1_0_10( + .A1(registers_12__ap[0]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[0]), + .ZN(n_1_0_9) + ); + AOI22_X1_LVT i_1_0_9( + .A1(registers_22__ap[0]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[0]), + .ZN(n_1_0_8) + ); + AOI22_X1_LVT i_1_0_8( + .A1(registers_17__ap[0]), .A2(n_1_0_629), .B1(n_1_0_613), .B2(registers_20__ap[0]), + .ZN(n_1_0_7) + ); + NAND4_X1_LVT i_1_0_7( + .A1(n_1_0_10), .A2(n_1_0_9), .A3(n_1_0_8), .A4(n_1_0_7), .ZN(n_1_0_6) + ); + AOI22_X1_LVT i_1_0_6( + .A1(registers_13__ap[0]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[0]), + .ZN(n_1_0_5) + ); + AOI22_X1_LVT i_1_0_5( + .A1(registers_7__ap[0]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[0]), + .ZN(n_1_0_4) + ); + AOI22_X1_LVT i_1_0_4( + .A1(registers_19__ap[0]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[0]), + .ZN(n_1_0_3) + ); + AOI22_X1_LVT i_1_0_3( + .A1(registers_2__ap[0]), .A2(n_1_0_618), .B1(n_1_0_611), .B2(registers_11__ap[0]), + .ZN(n_1_0_2) + ); + NAND4_X1_LVT i_1_0_2( + .A1(n_1_0_5), .A2(n_1_0_4), .A3(n_1_0_3), .A4(n_1_0_2), .ZN(n_1_0_1) + ); + NOR3_X1_LVT i_1_0_1( + .A1(n_1_0_11), .A2(n_1_0_6), .A3(n_1_0_1), .ZN(n_1_0_0) + ); + NAND4_X1_LVT i_1_0_0( + .A1(n_1_0_18), .A2(n_1_0_17), .A3(n_1_0_16), .A4(n_1_0_0), .ZN(RRs2[0]) + ); + DLL_X2_LVT ts_lockup_latchn_clkc2_intno1050_i( + .D(registers_1__ap[0]), .GN(n_0_0), .Q(ts_no1050) + ); + DLL_X2_LVT ts_lockup_latchn_clkc4_intno1051_i( + .D(registers_6__ap[0]), .GN(n_0_36), .Q(ts_no1051) + ); + DLL_X2_LVT ts_lockup_latchn_clkc3_intno1053_i( + .D(registers_27__ap[0]), .GN(n_0_57), .Q(ts_no1053) + ); + DLL_X2_LVT ts_lockup_latchn_clkc1_intno1054_i( + .D(registers_11__ap[0]), .GN(n_0_41), .Q(ts_no1054) + ); + CLKBUF_X3_LVT tessent_persistent_cell_buf_extsi1227_i( + .A(ts_extsi1227), .Z(ts_pbuf_extsi1227_) + ); + CLKBUF_X3_LVT tessent_persistent_cell_buf_extsi1228_i( + .A(ts_extsi1228), .Z(ts_pbuf_extsi1228_) + ); + CLKBUF_X3_LVT tessent_persistent_cell_buf_extsi1226_i( + .A(ts_extsi1226), .Z(ts_pbuf_extsi1226_) + ); +endmodule + +module cpu(led, btn, clk_25mhz, scan_en, SI_1, SO_1, SI_2, SO_2, SI_3, SO_3, SI_4, + SO_4); + input [6:0] btn; + input clk_25mhz, scan_en, SI_1, SI_2, SI_3, SI_4; + output [7:0] led; + output SO_1, SO_2, SO_3, SO_4; + + wire [31:0] Instruction, RData, RRs2, RRs1, WRd, DAddr, JumpOrBranchPC, + CurrentPC, NextPC; + wire [1:0] DWidth; + wire WrReg, JumpOrBranch, thePC_n_1, thePC_i_0_n_0, thePC_n_2, thePC_i_0_n_1, + thePC_n_3, thePC_i_0_n_2, thePC_n_4, thePC_i_0_n_3, thePC_n_5, + thePC_i_0_n_4, thePC_n_6, thePC_i_0_n_5, thePC_n_7, thePC_i_0_n_6, + thePC_n_8, thePC_i_0_n_7, thePC_n_9, thePC_i_0_n_8, thePC_n_10, + thePC_i_0_n_9, thePC_n_11, thePC_i_0_n_10, thePC_n_12, thePC_i_0_n_11, + thePC_n_13, thePC_i_0_n_12, thePC_n_14, thePC_i_0_n_13, thePC_n_15, + thePC_i_0_n_14, thePC_n_16, thePC_i_0_n_15, thePC_n_17, thePC_i_0_n_16, + thePC_n_18, thePC_i_0_n_17, thePC_n_19, thePC_i_0_n_18, thePC_n_20, + thePC_i_0_n_19, thePC_n_21, thePC_i_0_n_20, thePC_n_22, thePC_i_0_n_21, + thePC_n_23, thePC_i_0_n_22, thePC_n_24, thePC_i_0_n_23, thePC_n_25, + thePC_i_0_n_24, thePC_n_26, thePC_i_0_n_25, thePC_n_27, thePC_i_0_n_26, + thePC_n_28, thePC_i_0_n_27, thePC_n_29, thePC_n_0, thePC_n_30, n_0_0_0, + thePC_n_31, n_0_0_1, thePC_n_32, thePC_n_33, thePC_n_34, thePC_n_35, + thePC_n_36, thePC_n_37, thePC_n_38, thePC_n_39, thePC_n_40, thePC_n_41, + thePC_n_42, thePC_n_43, n_0_0_2, thePC_n_44, n_0_0_3, thePC_n_45, + n_0_0_4, thePC_n_46, n_0_0_5, thePC_n_47, n_0_0_6, thePC_n_48, n_0_0_7, + thePC_n_49, n_0_0_8, thePC_n_50, n_0_0_9, thePC_n_51, n_0_0_10, + thePC_n_52, n_0_0_11, thePC_n_53, n_0_0_12, thePC_n_54, n_0_0_13, + thePC_n_55, n_0_0_14, thePC_n_56, n_0_0_15, thePC_n_57, n_0_0_16, + thePC_n_58, n_0_0_17, thePC_n_59, n_0_0_18, thePC_n_60, n_0_0_19, + thePC_n_61, n_0_0_20, n_0_0_21, n_0_0_22, reset, uc_0, uc_1, uc_2, uc_3, + uc_4, uc_5, uc_6, uc_7, uc_8, uc_9, uc_10, uc_11, uc_12, uc_13, uc_14, + uc_15, uc_16, uc_17, uc_18, uc_19, uc_20, uc_21, uc_22, uc_23, uc_24, + uc_25, uc_26, uc_27, uc_28, uc_29, uc_30, uc_31, uc_32, uc_33, uc_34, + uc_35, uc_36, uc_37, uc_38, uc_39, uc_40, uc_41, uc_42, uc_43, uc_44, + uc_45, uc_46, uc_47, uc_48, uc_49, uc_50, uc_51, uc_52, uc_53, uc_54, + uc_55, uc_56, uc_57, uc_58, ts_pbuf_extsi1225_, ts_no1054, ts_no1050, + ts_no1053, ts_no1051; + + assign SO_1 = ts_no1054; + assign SO_2 = ts_no1050; + assign SO_3 = ts_no1053; + assign SO_4 = ts_no1051; + AND2_X1_LVT i_0_0_54( + .A1(JumpOrBranch), .A2(btn[0]), .ZN(n_0_0_22) + ); + INV_X1_LVT i_0_0_66( + .A(btn[0]), .ZN(reset) + ); + NOR2_X1_LVT i_0_0_53( + .A1(reset), .A2(JumpOrBranch), .ZN(n_0_0_21) + ); + AOI22_X1_LVT i_0_0_50( + .A1(JumpOrBranchPC[30]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_28), .ZN(n_0_0_19) + ); + INV_X1_LVT i_0_0_49( + .A(n_0_0_19), .ZN(thePC_n_60) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[30] ( + .CK(clk_25mhz), .D(thePC_n_60), .Q(CurrentPC[30]), .QN(), .SE(scan_en), .SI(ts_pbuf_extsi1225_) + ); + AOI22_X1_LVT i_0_0_48( + .A1(JumpOrBranchPC[29]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_27), .ZN(n_0_0_18) + ); + INV_X1_LVT i_0_0_47( + .A(n_0_0_18), .ZN(thePC_n_59) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[29] ( + .CK(clk_25mhz), .D(thePC_n_59), .Q(CurrentPC[29]), .QN(), .SE(scan_en), .SI(CurrentPC[30]) + ); + AOI22_X1_LVT i_0_0_46( + .A1(JumpOrBranchPC[28]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_26), .ZN(n_0_0_17) + ); + INV_X1_LVT i_0_0_45( + .A(n_0_0_17), .ZN(thePC_n_58) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[28] ( + .CK(clk_25mhz), .D(thePC_n_58), .Q(CurrentPC[28]), .QN(), .SE(scan_en), .SI(CurrentPC[29]) + ); + AOI22_X1_LVT i_0_0_44( + .A1(JumpOrBranchPC[27]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_25), .ZN(n_0_0_16) + ); + INV_X1_LVT i_0_0_43( + .A(n_0_0_16), .ZN(thePC_n_57) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[27] ( + .CK(clk_25mhz), .D(thePC_n_57), .Q(CurrentPC[27]), .QN(), .SE(scan_en), .SI(CurrentPC[28]) + ); + AOI22_X1_LVT i_0_0_42( + .A1(JumpOrBranchPC[26]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_24), .ZN(n_0_0_15) + ); + INV_X1_LVT i_0_0_41( + .A(n_0_0_15), .ZN(thePC_n_56) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[26] ( + .CK(clk_25mhz), .D(thePC_n_56), .Q(CurrentPC[26]), .QN(), .SE(scan_en), .SI(CurrentPC[27]) + ); + AOI22_X1_LVT i_0_0_40( + .A1(JumpOrBranchPC[25]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_23), .ZN(n_0_0_14) + ); + INV_X1_LVT i_0_0_39( + .A(n_0_0_14), .ZN(thePC_n_55) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[25] ( + .CK(clk_25mhz), .D(thePC_n_55), .Q(CurrentPC[25]), .QN(), .SE(scan_en), .SI(CurrentPC[26]) + ); + AOI22_X1_LVT i_0_0_38( + .A1(JumpOrBranchPC[24]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_22), .ZN(n_0_0_13) + ); + INV_X1_LVT i_0_0_37( + .A(n_0_0_13), .ZN(thePC_n_54) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[24] ( + .CK(clk_25mhz), .D(thePC_n_54), .Q(CurrentPC[24]), .QN(), .SE(scan_en), .SI(CurrentPC[25]) + ); + AOI22_X1_LVT i_0_0_36( + .A1(JumpOrBranchPC[23]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_21), .ZN(n_0_0_12) + ); + INV_X1_LVT i_0_0_35( + .A(n_0_0_12), .ZN(thePC_n_53) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[23] ( + .CK(clk_25mhz), .D(thePC_n_53), .Q(CurrentPC[23]), .QN(), .SE(scan_en), .SI(CurrentPC[24]) + ); + AOI22_X1_LVT i_0_0_34( + .A1(JumpOrBranchPC[22]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_20), .ZN(n_0_0_11) + ); + INV_X1_LVT i_0_0_33( + .A(n_0_0_11), .ZN(thePC_n_52) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[22] ( + .CK(clk_25mhz), .D(thePC_n_52), .Q(CurrentPC[22]), .QN(), .SE(scan_en), .SI(CurrentPC[23]) + ); + AOI22_X1_LVT i_0_0_32( + .A1(JumpOrBranchPC[21]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_19), .ZN(n_0_0_10) + ); + INV_X1_LVT i_0_0_31( + .A(n_0_0_10), .ZN(thePC_n_51) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[21] ( + .CK(clk_25mhz), .D(thePC_n_51), .Q(CurrentPC[21]), .QN(), .SE(scan_en), .SI(CurrentPC[22]) + ); + AOI22_X1_LVT i_0_0_30( + .A1(JumpOrBranchPC[20]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_18), .ZN(n_0_0_9) + ); + INV_X1_LVT i_0_0_29( + .A(n_0_0_9), .ZN(thePC_n_50) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[20] ( + .CK(clk_25mhz), .D(thePC_n_50), .Q(CurrentPC[20]), .QN(), .SE(scan_en), .SI(CurrentPC[21]) + ); + AOI22_X1_LVT i_0_0_28( + .A1(JumpOrBranchPC[19]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_17), .ZN(n_0_0_8) + ); + INV_X1_LVT i_0_0_27( + .A(n_0_0_8), .ZN(thePC_n_49) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[19] ( + .CK(clk_25mhz), .D(thePC_n_49), .Q(CurrentPC[19]), .QN(), .SE(scan_en), .SI(CurrentPC[20]) + ); + AOI22_X1_LVT i_0_0_26( + .A1(JumpOrBranchPC[18]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_16), .ZN(n_0_0_7) + ); + INV_X1_LVT i_0_0_25( + .A(n_0_0_7), .ZN(thePC_n_48) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[18] ( + .CK(clk_25mhz), .D(thePC_n_48), .Q(CurrentPC[18]), .QN(), .SE(scan_en), .SI(CurrentPC[19]) + ); + AOI22_X1_LVT i_0_0_24( + .A1(JumpOrBranchPC[17]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_15), .ZN(n_0_0_6) + ); + INV_X1_LVT i_0_0_23( + .A(n_0_0_6), .ZN(thePC_n_47) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[17] ( + .CK(clk_25mhz), .D(thePC_n_47), .Q(CurrentPC[17]), .QN(), .SE(scan_en), .SI(CurrentPC[18]) + ); + AOI22_X1_LVT i_0_0_22( + .A1(JumpOrBranchPC[16]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_14), .ZN(n_0_0_5) + ); + INV_X1_LVT i_0_0_21( + .A(n_0_0_5), .ZN(thePC_n_46) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[16] ( + .CK(clk_25mhz), .D(thePC_n_46), .Q(CurrentPC[16]), .QN(), .SE(scan_en), .SI(CurrentPC[17]) + ); + AOI22_X1_LVT i_0_0_20( + .A1(JumpOrBranchPC[15]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_13), .ZN(n_0_0_4) + ); + INV_X1_LVT i_0_0_19( + .A(n_0_0_4), .ZN(thePC_n_45) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[15] ( + .CK(clk_25mhz), .D(thePC_n_45), .Q(CurrentPC[15]), .QN(), .SE(scan_en), .SI(CurrentPC[16]) + ); + AOI22_X1_LVT i_0_0_18( + .A1(JumpOrBranchPC[14]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_12), .ZN(n_0_0_3) + ); + INV_X1_LVT i_0_0_17( + .A(n_0_0_3), .ZN(thePC_n_44) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[14] ( + .CK(clk_25mhz), .D(thePC_n_44), .Q(CurrentPC[14]), .QN(), .SE(scan_en), .SI(CurrentPC[15]) + ); + AOI22_X1_LVT i_0_0_16( + .A1(JumpOrBranchPC[13]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_11), .ZN(n_0_0_2) + ); + INV_X1_LVT i_0_0_15( + .A(n_0_0_2), .ZN(thePC_n_43) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[13] ( + .CK(clk_25mhz), .D(thePC_n_43), .Q(CurrentPC[13]), .QN(), .SE(scan_en), .SI(CurrentPC[14]) + ); + MUX2_X1_LVT i_0_0_65( + .A(thePC_n_10), .B(JumpOrBranchPC[12]), .S(JumpOrBranch), .Z(NextPC[12]) + ); + AND2_X1_LVT i_0_0_14( + .A1(NextPC[12]), .A2(btn[0]), .ZN(thePC_n_42) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[12] ( + .CK(clk_25mhz), .D(thePC_n_42), .Q(CurrentPC[12]), .QN(), .SE(scan_en), .SI(CurrentPC[13]) + ); + MUX2_X1_LVT i_0_0_64( + .A(thePC_n_9), .B(JumpOrBranchPC[11]), .S(JumpOrBranch), .Z(NextPC[11]) + ); + AND2_X1_LVT i_0_0_13( + .A1(NextPC[11]), .A2(btn[0]), .ZN(thePC_n_41) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[11] ( + .CK(clk_25mhz), .D(thePC_n_41), .Q(CurrentPC[11]), .QN(), .SE(scan_en), .SI(CurrentPC[12]) + ); + MUX2_X1_LVT i_0_0_63( + .A(thePC_n_8), .B(JumpOrBranchPC[10]), .S(JumpOrBranch), .Z(NextPC[10]) + ); + AND2_X1_LVT i_0_0_12( + .A1(NextPC[10]), .A2(btn[0]), .ZN(thePC_n_40) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[10] ( + .CK(clk_25mhz), .D(thePC_n_40), .Q(CurrentPC[10]), .QN(), .SE(scan_en), .SI(CurrentPC[11]) + ); + MUX2_X1_LVT i_0_0_62( + .A(thePC_n_7), .B(JumpOrBranchPC[9]), .S(JumpOrBranch), .Z(NextPC[9]) + ); + AND2_X1_LVT i_0_0_11( + .A1(NextPC[9]), .A2(btn[0]), .ZN(thePC_n_39) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[9] ( + .CK(clk_25mhz), .D(thePC_n_39), .Q(CurrentPC[9]), .QN(), .SE(scan_en), .SI(CurrentPC[10]) + ); + MUX2_X1_LVT i_0_0_61( + .A(thePC_n_6), .B(JumpOrBranchPC[8]), .S(JumpOrBranch), .Z(NextPC[8]) + ); + AND2_X1_LVT i_0_0_10( + .A1(NextPC[8]), .A2(btn[0]), .ZN(thePC_n_38) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[8] ( + .CK(clk_25mhz), .D(thePC_n_38), .Q(CurrentPC[8]), .QN(), .SE(scan_en), .SI(CurrentPC[9]) + ); + AND2_X1_LVT i_0_0_9( + .A1(led[7]), .A2(btn[0]), .ZN(thePC_n_37) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[7] ( + .CK(clk_25mhz), .D(thePC_n_37), .Q(CurrentPC[7]), .QN(), .SE(scan_en), .SI(CurrentPC[8]) + ); + MUX2_X1_LVT i_0_0_59( + .A(thePC_n_4), .B(JumpOrBranchPC[6]), .S(JumpOrBranch), .Z(led[6]) + ); + AND2_X1_LVT i_0_0_8( + .A1(led[6]), .A2(btn[0]), .ZN(thePC_n_36) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[6] ( + .CK(clk_25mhz), .D(thePC_n_36), .Q(CurrentPC[6]), .QN(), .SE(scan_en), .SI(CurrentPC[7]) + ); + MUX2_X1_LVT i_0_0_58( + .A(thePC_n_3), .B(JumpOrBranchPC[5]), .S(JumpOrBranch), .Z(led[5]) + ); + AND2_X1_LVT i_0_0_7( + .A1(led[5]), .A2(btn[0]), .ZN(thePC_n_35) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[5] ( + .CK(clk_25mhz), .D(thePC_n_35), .Q(CurrentPC[5]), .QN(), .SE(scan_en), .SI(CurrentPC[6]) + ); + MUX2_X1_LVT i_0_0_57( + .A(thePC_n_2), .B(JumpOrBranchPC[4]), .S(JumpOrBranch), .Z(led[4]) + ); + AND2_X1_LVT i_0_0_6( + .A1(led[4]), .A2(btn[0]), .ZN(thePC_n_34) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[4] ( + .CK(clk_25mhz), .D(thePC_n_34), .Q(CurrentPC[4]), .QN(), .SE(scan_en), .SI(CurrentPC[5]) + ); + MUX2_X1_LVT i_0_0_56( + .A(thePC_n_1), .B(JumpOrBranchPC[3]), .S(JumpOrBranch), .Z(led[3]) + ); + AND2_X1_LVT i_0_0_5( + .A1(led[3]), .A2(btn[0]), .ZN(thePC_n_33) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[3] ( + .CK(clk_25mhz), .D(thePC_n_33), .Q(CurrentPC[3]), .QN(), .SE(scan_en), .SI(CurrentPC[4]) + ); + INV_X1_LVT thePC_i_0_29( + .A(CurrentPC[2]), .ZN(thePC_n_0) + ); + MUX2_X1_LVT i_0_0_55( + .A(thePC_n_0), .B(JumpOrBranchPC[2]), .S(JumpOrBranch), .Z(led[2]) + ); + AND2_X1_LVT i_0_0_4( + .A1(led[2]), .A2(btn[0]), .ZN(thePC_n_32) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[2] ( + .CK(clk_25mhz), .D(thePC_n_32), .Q(CurrentPC[2]), .QN(), .SE(scan_en), .SI(CurrentPC[3]) + ); + HA_X1_LVT thePC_i_0_0( + .A(CurrentPC[3]), .B(CurrentPC[2]), .CO(thePC_i_0_n_0), .S(thePC_n_1) + ); + HA_X1_LVT thePC_i_0_1( + .A(CurrentPC[4]), .B(thePC_i_0_n_0), .CO(thePC_i_0_n_1), .S(thePC_n_2) + ); + HA_X1_LVT thePC_i_0_2( + .A(CurrentPC[5]), .B(thePC_i_0_n_1), .CO(thePC_i_0_n_2), .S(thePC_n_3) + ); + HA_X1_LVT thePC_i_0_3( + .A(CurrentPC[6]), .B(thePC_i_0_n_2), .CO(thePC_i_0_n_3), .S(thePC_n_4) + ); + HA_X1_LVT thePC_i_0_4( + .A(CurrentPC[7]), .B(thePC_i_0_n_3), .CO(thePC_i_0_n_4), .S(thePC_n_5) + ); + HA_X1_LVT thePC_i_0_5( + .A(CurrentPC[8]), .B(thePC_i_0_n_4), .CO(thePC_i_0_n_5), .S(thePC_n_6) + ); + HA_X1_LVT thePC_i_0_6( + .A(CurrentPC[9]), .B(thePC_i_0_n_5), .CO(thePC_i_0_n_6), .S(thePC_n_7) + ); + HA_X1_LVT thePC_i_0_7( + .A(CurrentPC[10]), .B(thePC_i_0_n_6), .CO(thePC_i_0_n_7), .S(thePC_n_8) + ); + HA_X1_LVT thePC_i_0_8( + .A(CurrentPC[11]), .B(thePC_i_0_n_7), .CO(thePC_i_0_n_8), .S(thePC_n_9) + ); + HA_X1_LVT thePC_i_0_9( + .A(CurrentPC[12]), .B(thePC_i_0_n_8), .CO(thePC_i_0_n_9), .S(thePC_n_10) + ); + HA_X1_LVT thePC_i_0_11( + .A(CurrentPC[13]), .B(thePC_i_0_n_9), .CO(thePC_i_0_n_10), .S(thePC_n_11) + ); + HA_X1_LVT thePC_i_0_12( + .A(CurrentPC[14]), .B(thePC_i_0_n_10), .CO(thePC_i_0_n_11), .S(thePC_n_12) + ); + HA_X1_LVT thePC_i_0_13( + .A(CurrentPC[15]), .B(thePC_i_0_n_11), .CO(thePC_i_0_n_12), .S(thePC_n_13) + ); + HA_X1_LVT thePC_i_0_14( + .A(CurrentPC[16]), .B(thePC_i_0_n_12), .CO(thePC_i_0_n_13), .S(thePC_n_14) + ); + HA_X1_LVT thePC_i_0_15( + .A(CurrentPC[17]), .B(thePC_i_0_n_13), .CO(thePC_i_0_n_14), .S(thePC_n_15) + ); + HA_X1_LVT thePC_i_0_16( + .A(CurrentPC[18]), .B(thePC_i_0_n_14), .CO(thePC_i_0_n_15), .S(thePC_n_16) + ); + HA_X1_LVT thePC_i_0_17( + .A(CurrentPC[19]), .B(thePC_i_0_n_15), .CO(thePC_i_0_n_16), .S(thePC_n_17) + ); + HA_X1_LVT thePC_i_0_10( + .A(CurrentPC[20]), .B(thePC_i_0_n_16), .CO(thePC_i_0_n_17), .S(thePC_n_18) + ); + HA_X1_LVT thePC_i_0_18( + .A(CurrentPC[21]), .B(thePC_i_0_n_17), .CO(thePC_i_0_n_18), .S(thePC_n_19) + ); + HA_X1_LVT thePC_i_0_19( + .A(CurrentPC[22]), .B(thePC_i_0_n_18), .CO(thePC_i_0_n_19), .S(thePC_n_20) + ); + HA_X1_LVT thePC_i_0_20( + .A(CurrentPC[23]), .B(thePC_i_0_n_19), .CO(thePC_i_0_n_20), .S(thePC_n_21) + ); + HA_X1_LVT thePC_i_0_21( + .A(CurrentPC[24]), .B(thePC_i_0_n_20), .CO(thePC_i_0_n_21), .S(thePC_n_22) + ); + HA_X1_LVT thePC_i_0_22( + .A(CurrentPC[25]), .B(thePC_i_0_n_21), .CO(thePC_i_0_n_22), .S(thePC_n_23) + ); + HA_X1_LVT thePC_i_0_23( + .A(CurrentPC[26]), .B(thePC_i_0_n_22), .CO(thePC_i_0_n_23), .S(thePC_n_24) + ); + HA_X1_LVT thePC_i_0_24( + .A(CurrentPC[27]), .B(thePC_i_0_n_23), .CO(thePC_i_0_n_24), .S(thePC_n_25) + ); + HA_X1_LVT thePC_i_0_25( + .A(CurrentPC[28]), .B(thePC_i_0_n_24), .CO(thePC_i_0_n_25), .S(thePC_n_26) + ); + HA_X1_LVT thePC_i_0_26( + .A(CurrentPC[29]), .B(thePC_i_0_n_25), .CO(thePC_i_0_n_26), .S(thePC_n_27) + ); + HA_X1_LVT thePC_i_0_27( + .A(CurrentPC[30]), .B(thePC_i_0_n_26), .CO(thePC_i_0_n_27), .S(thePC_n_28) + ); + XOR2_X1_LVT thePC_i_0_28( + .A(CurrentPC[31]), .B(thePC_i_0_n_27), .Z(thePC_n_29) + ); + AOI22_X1_LVT i_0_0_52( + .A1(JumpOrBranchPC[31]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_29), .ZN(n_0_0_20) + ); + INV_X1_LVT i_0_0_51( + .A(n_0_0_20), .ZN(thePC_n_61) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[31] ( + .CK(clk_25mhz), .D(thePC_n_61), .Q(CurrentPC[31]), .QN(), .SE(scan_en), .SI(CurrentPC[2]) + ); + AOI22_X1_LVT i_0_0_3( + .A1(JumpOrBranchPC[1]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(CurrentPC[1]), + .ZN(n_0_0_1) + ); + INV_X1_LVT i_0_0_2( + .A(n_0_0_1), .ZN(thePC_n_31) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[1] ( + .CK(clk_25mhz), .D(thePC_n_31), .Q(CurrentPC[1]), .QN(), .SE(scan_en), .SI(CurrentPC[31]) + ); + AOI22_X1_LVT i_0_0_1( + .A1(JumpOrBranchPC[0]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(CurrentPC[0]), + .ZN(n_0_0_0) + ); + INV_X1_LVT i_0_0_0( + .A(n_0_0_0), .ZN(thePC_n_30) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[0] ( + .CK(clk_25mhz), .D(thePC_n_30), .Q(CurrentPC[0]), .QN(), .SE(scan_en), .SI(CurrentPC[1]) + ); + reg_file theRegisters( + .Rs1({Instruction[19], Instruction[18], Instruction[17], + Instruction[16], Instruction[15]}), .Rs2({Instruction[24], + Instruction[23], Instruction[22], Instruction[21], Instruction[20]}), .Rd({ + Instruction[11], Instruction[10], Instruction[9], Instruction[8], + Instruction[7]}), .RRs1(RRs1), .RRs2(RRs2), .WRd(WRd), .WrReg(WrReg), .reset(reset), + .clk(clk_25mhz), .dftIn(scan_en), .ts_intno31(CurrentPC[0]), .ts_no1050(ts_no1050), + .ts_no1051(ts_no1051), .ts_no1053(ts_no1053), .ts_no1054(ts_no1054), .ts_extsi1226(SI_2), + .ts_extsi1227(SI_3), .ts_extsi1228(SI_4) + ); + main_mem theMem( + .clk(clk_25mhz), .reset(reset), .DAddr({uc_0, uc_1, uc_2, uc_3, uc_4, + uc_5, uc_6, uc_7, uc_8, uc_9, uc_10, uc_11, uc_12, uc_13, uc_14, uc_15, + uc_16, uc_17, uc_18, DAddr[12], DAddr[11], DAddr[10], DAddr[9], + DAddr[8], DAddr[7], DAddr[6], DAddr[5], DAddr[4], DAddr[3], DAddr[2], + DAddr[1], DAddr[0]}), .IAddr({uc_19, uc_20, uc_21, uc_22, uc_23, uc_24, + uc_25, uc_26, uc_27, uc_28, uc_29, uc_30, uc_31, uc_32, uc_33, uc_34, + uc_35, uc_36, uc_37, NextPC[12], NextPC[11], NextPC[10], NextPC[9], + NextPC[8], led[7], led[6], led[5], led[4], led[3], led[2], uc_38, uc_39}), + .DWData(RRs2), .DRData(RData), .IRData(Instruction), .DWE(led[1]), .DWidth(DWidth) + ); + decoder theDecoder( + .CurrentPC(CurrentPC), .JumpOrBranchPC(JumpOrBranchPC), .JumpOrBranch(JumpOrBranch), + .DAddr({uc_40, uc_41, uc_42, uc_43, uc_44, uc_45, uc_46, uc_47, uc_48, + uc_49, uc_50, uc_51, uc_52, uc_53, uc_54, uc_55, uc_56, uc_57, uc_58, + DAddr[12], DAddr[11], DAddr[10], DAddr[9], DAddr[8], DAddr[7], DAddr[6], + DAddr[5], DAddr[4], DAddr[3], DAddr[2], DAddr[1], DAddr[0]}), .WData(), .RData(RData), + .Instruction(Instruction), .WrMem(led[1]), .DWidth(DWidth), .Rs1(), .Rs2(), + .Rd(), .RRs1(RRs1), .RRs2(RRs2), .WRd(WRd), .WrReg(WrReg), .Illegal(led[0]) + ); + MUX2_X1_LVT i_0_0_60( + .A(thePC_n_5), .B(JumpOrBranchPC[7]), .S(JumpOrBranch), .Z(led[7]) + ); + CLKBUF_X3_LVT tessent_persistent_cell_buf_extsi1225_i( + .A(SI_1), .Z(ts_pbuf_extsi1225_) + ); +endmodule + diff --git a/oasys.tessent.02/Scan_0/cpu.scandef b/oasys.tessent.02/Scan_0/cpu.scandef new file mode 100644 index 0000000..299eb94 --- /dev/null +++ b/oasys.tessent.02/Scan_0/cpu.scandef @@ -0,0 +1,1071 @@ +# +# DESC: ScanDEF written by Tessent Shell on Fri May 29 09:12:39 CEST 2026 +# + +VERSION 5.7 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN cpu ; +UNITS DISTANCE MICRONS 1000 ; + +SCANCHAINS 4 ; + +- scan_segment_0 + + START tessent_persistent_cell_buf_extsi1225_i Z + + FLOATING + thePC_CurrentPC_reg\[30\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[29\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[28\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[27\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[26\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[25\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[24\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[23\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[22\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[21\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[20\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[19\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[18\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[17\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[16\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[15\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[14\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[13\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[12\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[11\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[10\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[9\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[8\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[7\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[6\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[5\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[4\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[3\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[2\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[31\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[1\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[0\] ( IN SI ) ( OUT Q ) + + STOP theRegisters/ts_lockup_latchn_clkc1_intno1054_i D + # Partition constraints - clock domain: clk_25mhz(+); cluster: scanChain_1; chain type: core; scan mode(s): unwrapped + + PARTITION partition_1 MAXBITS 256 ; + + +- scan_segment_1 + + START theRegisters/tessent_persistent_cell_buf_extsi1226_i Z + + FLOATING + theRegisters/registers_reg\[1\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[0\] ( IN SI ) ( OUT Q ) + + STOP theRegisters/ts_lockup_latchn_clkc2_intno1050_i D + # Partition constraints - clock domain: clk_25mhz(+); cluster: scanChain_2; chain type: core; scan mode(s): unwrapped + + PARTITION partition_2 MAXBITS 256 ; + + +- scan_segment_2 + + START theRegisters/tessent_persistent_cell_buf_extsi1227_i Z + + FLOATING + theRegisters/registers_reg\[28\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[0\] ( IN SI ) ( OUT Q ) + + STOP theRegisters/ts_lockup_latchn_clkc3_intno1053_i D + # Partition constraints - clock domain: clk_25mhz(+); cluster: scanChain_3; chain type: core; scan mode(s): unwrapped + + PARTITION partition_3 MAXBITS 256 ; + + +- scan_segment_3 + + START theRegisters/tessent_persistent_cell_buf_extsi1228_i Z + + FLOATING + theRegisters/registers_reg\[4\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[0\] ( IN SI ) ( OUT Q ) + + STOP theRegisters/ts_lockup_latchn_clkc4_intno1051_i D + # Partition constraints - clock domain: clk_25mhz(+); cluster: scanChain_4; chain type: core; scan mode(s): unwrapped + + PARTITION partition_4 MAXBITS 256 ; + + +END SCANCHAINS + +END DESIGN diff --git a/oasys.tessent.02/Scan_0/oasys.sdc b/oasys.tessent.02/Scan_0/oasys.sdc new file mode 100644 index 0000000..e864056 --- /dev/null +++ b/oasys.tessent.02/Scan_0/oasys.sdc @@ -0,0 +1,62 @@ +# +# Created by +# ../bin/Linux-x86_64-O/oasysGui 22.2-p002 on Fri May 29 09:12:33 2026 +# (C) Mentor Graphics Corporation +# +set_units -time ns -capacitance pf -resistance kohm -power nW -voltage V -current uA +create_clock -period 40 -waveform {0 20} -name clk_25mhz [get_ports clk_25mhz] +set_clock_transition 0.1 [get_clocks clk_25mhz] +set_clock_uncertainty -setup 0.5 [get_clocks clk_25mhz] +set_clock_uncertainty -hold 0.2 [get_clocks clk_25mhz] +set_false_path -from [get_ports {btn[0]}] +group_path -name I2R -from [list [get_ports clk_25mhz] [get_ports {btn[0]}] [get_ports {btn[1]}] [get_ports {btn[2]}] [get_ports {btn[3]}] [get_ports {btn[4]}] [get_ports {btn[5]}] [get_ports {btn[6]}]] +group_path -name I2O -from [list [get_ports clk_25mhz] [get_ports {btn[0]}] [get_ports {btn[1]}] [get_ports {btn[2]}] [get_ports {btn[3]}] [get_ports {btn[4]}] [get_ports {btn[5]}] [get_ports {btn[6]}]] -to [list [get_ports {led[0]}] [get_ports {led[1]}] [get_ports {led[2]}] [get_ports {led[3]}] [get_ports {led[4]}] [get_ports {led[5]}] [get_ports {led[6]}] [get_ports {led[7]}]] +group_path -name R2O -to [list [get_ports {led[0]}] [get_ports {led[1]}] [get_ports {led[2]}] [get_ports {led[3]}] [get_ports {led[4]}] [get_ports {led[5]}] [get_ports {led[6]}] [get_ports {led[7]}]] +set_input_delay 2 -clock clk_25mhz -max [get_ports {btn[6]}] +set_input_delay 2 -clock clk_25mhz -max [get_ports {btn[5]}] +set_input_delay 2 -clock clk_25mhz -max [get_ports {btn[4]}] +set_input_delay 2 -clock clk_25mhz -max [get_ports {btn[3]}] +set_input_delay 2 -clock clk_25mhz -max [get_ports {btn[2]}] +set_input_delay 2 -clock clk_25mhz -max [get_ports {btn[1]}] +set_input_delay 2 -clock clk_25mhz -max [get_ports {btn[0]}] +set_input_delay 0.5 -clock clk_25mhz -min [get_ports {btn[6]}] +set_input_delay 0.5 -clock clk_25mhz -min [get_ports {btn[5]}] +set_input_delay 0.5 -clock clk_25mhz -min [get_ports {btn[4]}] +set_input_delay 0.5 -clock clk_25mhz -min [get_ports {btn[3]}] +set_input_delay 0.5 -clock clk_25mhz -min [get_ports {btn[2]}] +set_input_delay 0.5 -clock clk_25mhz -min [get_ports {btn[1]}] +set_input_delay 0.5 -clock clk_25mhz -min [get_ports {btn[0]}] +set_output_delay 2 -clock clk_25mhz -max [get_ports {led[7]}] +set_output_delay 2 -clock clk_25mhz -max [get_ports {led[6]}] +set_output_delay 2 -clock clk_25mhz -max [get_ports {led[5]}] +set_output_delay 2 -clock clk_25mhz -max [get_ports {led[4]}] +set_output_delay 2 -clock clk_25mhz -max [get_ports {led[3]}] +set_output_delay 2 -clock clk_25mhz -max [get_ports {led[2]}] +set_output_delay 2 -clock clk_25mhz -max [get_ports {led[1]}] +set_output_delay 2 -clock clk_25mhz -max [get_ports {led[0]}] +set_output_delay 0.5 -clock clk_25mhz -min [get_ports {led[7]}] +set_output_delay 0.5 -clock clk_25mhz -min [get_ports {led[6]}] +set_output_delay 0.5 -clock clk_25mhz -min [get_ports {led[5]}] +set_output_delay 0.5 -clock clk_25mhz -min [get_ports {led[4]}] +set_output_delay 0.5 -clock clk_25mhz -min [get_ports {led[3]}] +set_output_delay 0.5 -clock clk_25mhz -min [get_ports {led[2]}] +set_output_delay 0.5 -clock clk_25mhz -min [get_ports {led[1]}] +set_output_delay 0.5 -clock clk_25mhz -min [get_ports {led[0]}] +set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 [get_ports {btn[6]}] +set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 [get_ports {btn[5]}] +set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 [get_ports {btn[4]}] +set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 [get_ports {btn[3]}] +set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 [get_ports {btn[2]}] +set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 [get_ports {btn[1]}] +set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 [get_ports {btn[0]}] +set_load 0.05 [get_ports {led[7]}] +set_load 0.05 [get_ports {led[6]}] +set_load 0.05 [get_ports {led[5]}] +set_load 0.05 [get_ports {led[4]}] +set_load 0.05 [get_ports {led[3]}] +set_load 0.05 [get_ports {led[2]}] +set_load 0.05 [get_ports {led[1]}] +set_load 0.05 [get_ports {led[0]}] +set_operating_conditions -library [get_libs {NangateOpenCellLibrary_45nm_LVT_0p85}] -max slow_0p85V -min slow_0p85V +set_max_fanout 20.000000 [current_design] +set_max_transition 0.500000 [current_design] diff --git a/oasys.tessent.02/Scan_0/oasys_netlist.v b/oasys.tessent.02/Scan_0/oasys_netlist.v new file mode 100644 index 0000000..61e06b1 --- /dev/null +++ b/oasys.tessent.02/Scan_0/oasys_netlist.v @@ -0,0 +1,10896 @@ +/* + * Created by + ../bin/Linux-x86_64-O/oasysGui 22.2-p002 on Fri May 29 09:12:32 2026 + * (C) Mentor Graphics Corporation + */ +/* CheckSum: 514746972 */ + +module reg_file(Rs1, Rs2, Rd, RRs1, RRs2, WRd, WrReg, reset, clk, dftIn); + input [4:0]Rs1; + input [4:0]Rs2; + input [4:0]Rd; + output [31:0]RRs1; + output [31:0]RRs2; + input [31:0]WRd; + input WrReg; + input reset; + input clk; + input dftIn; + + wire [31:0]registers_1__ap; + wire n_0_0; + wire [31:0]registers_2__ap; + wire n_0_32; + wire [31:0]registers_3__ap; + wire n_0_33; + wire [31:0]registers_4__ap; + wire n_0_34; + wire [31:0]registers_5__ap; + wire n_0_35; + wire [31:0]registers_6__ap; + wire n_0_36; + wire [31:0]registers_7__ap; + wire n_0_37; + wire [31:0]registers_8__ap; + wire n_0_38; + wire [31:0]registers_9__ap; + wire n_0_39; + wire [31:0]registers_10__ap; + wire n_0_40; + wire [31:0]registers_11__ap; + wire n_0_41; + wire [31:0]registers_12__ap; + wire n_0_42; + wire [31:0]registers_13__ap; + wire n_0_43; + wire [31:0]registers_14__ap; + wire n_0_44; + wire [31:0]registers_15__ap; + wire n_0_45; + wire [31:0]registers_16__ap; + wire n_0_46; + wire [31:0]registers_17__ap; + wire n_0_47; + wire [31:0]registers_18__ap; + wire n_0_48; + wire [31:0]registers_19__ap; + wire n_0_49; + wire [31:0]registers_20__ap; + wire n_0_50; + wire [31:0]registers_21__ap; + wire n_0_51; + wire [31:0]registers_22__ap; + wire n_0_52; + wire [31:0]registers_23__ap; + wire n_0_53; + wire [31:0]registers_24__ap; + wire n_0_54; + wire [31:0]registers_25__ap; + wire n_0_55; + wire [31:0]registers_26__ap; + wire n_0_56; + wire [31:0]registers_27__ap; + wire n_0_57; + wire [31:0]registers_28__ap; + wire n_0_58; + wire [31:0]registers_29__ap; + wire n_0_59; + wire [31:0]registers_30__ap; + wire n_0_60; + wire [31:0]registers_31__ap; + wire n_0_61; + wire [31:0]registers; + wire n_0_31; + wire n_0_30; + wire n_0_29; + wire n_0_28; + wire n_0_27; + wire n_0_26; + wire n_0_25; + wire n_0_24; + wire n_0_0_0; + wire n_0_0_1; + wire n_0_23; + wire n_0_22; + wire n_0_21; + wire n_0_20; + wire n_0_19; + wire n_0_18; + wire n_0_17; + wire n_0_16; + wire n_0_0_2; + wire n_0_0_3; + wire n_0_15; + wire n_0_14; + wire n_0_13; + wire n_0_12; + wire n_0_11; + wire n_0_10; + wire n_0_9; + wire n_0_8; + wire n_0_0_4; + wire n_0_0_5; + wire n_0_7; + wire n_0_0_6; + wire n_0_6; + wire n_0_0_7; + wire n_0_5; + wire n_0_0_8; + wire n_0_4; + wire n_0_0_9; + wire n_0_0_10; + wire n_0_3; + wire n_0_0_11; + wire n_0_2; + wire n_0_0_12; + wire n_0_1; + wire n_0_0_13; + wire n_0_0_14; + wire n_0_0_15; + wire n_0_0_16; + wire n_0_0_17; + wire n_0_0_18; + wire n_0_0_19; + wire n_0_0_20; + wire n_1_0_0; + wire n_1_0_1; + wire n_1_0_2; + wire n_1_0_3; + wire n_1_0_4; + wire n_1_0_5; + wire n_1_0_6; + wire n_1_0_7; + wire n_1_0_8; + wire n_1_0_9; + wire n_1_0_10; + wire n_1_0_11; + wire n_1_0_12; + wire n_1_0_13; + wire n_1_0_14; + wire n_1_0_15; + wire n_1_0_16; + wire n_1_0_17; + wire n_1_0_18; + wire n_1_0_19; + wire n_1_0_20; + wire n_1_0_21; + wire n_1_0_22; + wire n_1_0_23; + wire n_1_0_24; + wire n_1_0_25; + wire n_1_0_26; + wire n_1_0_27; + wire n_1_0_28; + wire n_1_0_29; + wire n_1_0_30; + wire n_1_0_31; + wire n_1_0_32; + wire n_1_0_33; + wire n_1_0_34; + wire n_1_0_35; + wire n_1_0_36; + wire n_1_0_37; + wire n_1_0_38; + wire n_1_0_39; + wire n_1_0_40; + wire n_1_0_41; + wire n_1_0_42; + wire n_1_0_43; + wire n_1_0_44; + wire n_1_0_45; + wire n_1_0_46; + wire n_1_0_47; + wire n_1_0_48; + wire n_1_0_49; + wire n_1_0_50; + wire n_1_0_51; + wire n_1_0_52; + wire n_1_0_53; + wire n_1_0_54; + wire n_1_0_55; + wire n_1_0_56; + wire n_1_0_57; + wire n_1_0_58; + wire n_1_0_59; + wire n_1_0_60; + wire n_1_0_61; + wire n_1_0_62; + wire n_1_0_63; + wire n_1_0_64; + wire n_1_0_65; + wire n_1_0_66; + wire n_1_0_67; + wire n_1_0_68; + wire n_1_0_69; + wire n_1_0_70; + wire n_1_0_71; + wire n_1_0_72; + wire n_1_0_73; + wire n_1_0_74; + wire n_1_0_75; + wire n_1_0_76; + wire n_1_0_77; + wire n_1_0_78; + wire n_1_0_79; + wire n_1_0_80; + wire n_1_0_81; + wire n_1_0_82; + wire n_1_0_83; + wire n_1_0_84; + wire n_1_0_85; + wire n_1_0_86; + wire n_1_0_87; + wire n_1_0_88; + wire n_1_0_89; + wire n_1_0_90; + wire n_1_0_91; + wire n_1_0_92; + wire n_1_0_93; + wire n_1_0_94; + wire n_1_0_95; + wire n_1_0_96; + wire n_1_0_97; + wire n_1_0_98; + wire n_1_0_99; + wire n_1_0_100; + wire n_1_0_101; + wire n_1_0_102; + wire n_1_0_103; + wire n_1_0_104; + wire n_1_0_105; + wire n_1_0_106; + wire n_1_0_107; + wire n_1_0_108; + wire n_1_0_109; + wire n_1_0_110; + wire n_1_0_111; + wire n_1_0_112; + wire n_1_0_113; + wire n_1_0_114; + wire n_1_0_115; + wire n_1_0_116; + wire n_1_0_117; + wire n_1_0_118; + wire n_1_0_119; + wire n_1_0_120; + wire n_1_0_121; + wire n_1_0_122; + wire n_1_0_123; + wire n_1_0_124; + wire n_1_0_125; + wire n_1_0_126; + wire n_1_0_127; + wire n_1_0_128; + wire n_1_0_129; + wire n_1_0_130; + wire n_1_0_131; + wire n_1_0_132; + wire n_1_0_133; + wire n_1_0_134; + wire n_1_0_135; + wire n_1_0_136; + wire n_1_0_137; + wire n_1_0_138; + wire n_1_0_139; + wire n_1_0_140; + wire n_1_0_141; + wire n_1_0_142; + wire n_1_0_143; + wire n_1_0_144; + wire n_1_0_145; + wire n_1_0_146; + wire n_1_0_147; + wire n_1_0_148; + wire n_1_0_149; + wire n_1_0_150; + wire n_1_0_151; + wire n_1_0_152; + wire n_1_0_153; + wire n_1_0_154; + wire n_1_0_155; + wire n_1_0_156; + wire n_1_0_157; + wire n_1_0_158; + wire n_1_0_159; + wire n_1_0_160; + wire n_1_0_161; + wire n_1_0_162; + wire n_1_0_163; + wire n_1_0_164; + wire n_1_0_165; + wire n_1_0_166; + wire n_1_0_167; + wire n_1_0_168; + wire n_1_0_169; + wire n_1_0_170; + wire n_1_0_171; + wire n_1_0_172; + wire n_1_0_173; + wire n_1_0_174; + wire n_1_0_175; + wire n_1_0_176; + wire n_1_0_177; + wire n_1_0_178; + wire n_1_0_179; + wire n_1_0_180; + wire n_1_0_181; + wire n_1_0_182; + wire n_1_0_183; + wire n_1_0_184; + wire n_1_0_185; + wire n_1_0_186; + wire n_1_0_187; + wire n_1_0_188; + wire n_1_0_189; + wire n_1_0_190; + wire n_1_0_191; + wire n_1_0_192; + wire n_1_0_193; + wire n_1_0_194; + wire n_1_0_195; + wire n_1_0_196; + wire n_1_0_197; + wire n_1_0_198; + wire n_1_0_199; + wire n_1_0_200; + wire n_1_0_201; + wire n_1_0_202; + wire n_1_0_203; + wire n_1_0_204; + wire n_1_0_205; + wire n_1_0_206; + wire n_1_0_207; + wire n_1_0_208; + wire n_1_0_209; + wire n_1_0_210; + wire n_1_0_211; + wire n_1_0_212; + wire n_1_0_213; + wire n_1_0_214; + wire n_1_0_215; + wire n_1_0_216; + wire n_1_0_217; + wire n_1_0_218; + wire n_1_0_219; + wire n_1_0_220; + wire n_1_0_221; + wire n_1_0_222; + wire n_1_0_223; + wire n_1_0_224; + wire n_1_0_225; + wire n_1_0_226; + wire n_1_0_227; + wire n_1_0_228; + wire n_1_0_229; + wire n_1_0_230; + wire n_1_0_231; + wire n_1_0_232; + wire n_1_0_233; + wire n_1_0_234; + wire n_1_0_235; + wire n_1_0_236; + wire n_1_0_237; + wire n_1_0_238; + wire n_1_0_239; + wire n_1_0_240; + wire n_1_0_241; + wire n_1_0_242; + wire n_1_0_243; + wire n_1_0_244; + wire n_1_0_245; + wire n_1_0_246; + wire n_1_0_247; + wire n_1_0_248; + wire n_1_0_249; + wire n_1_0_250; + wire n_1_0_251; + wire n_1_0_252; + wire n_1_0_253; + wire n_1_0_254; + wire n_1_0_255; + wire n_1_0_256; + wire n_1_0_257; + wire n_1_0_258; + wire n_1_0_259; + wire n_1_0_260; + wire n_1_0_261; + wire n_1_0_262; + wire n_1_0_263; + wire n_1_0_264; + wire n_1_0_265; + wire n_1_0_266; + wire n_1_0_267; + wire n_1_0_268; + wire n_1_0_269; + wire n_1_0_270; + wire n_1_0_271; + wire n_1_0_272; + wire n_1_0_273; + wire n_1_0_274; + wire n_1_0_275; + wire n_1_0_276; + wire n_1_0_277; + wire n_1_0_278; + wire n_1_0_279; + wire n_1_0_280; + wire n_1_0_281; + wire n_1_0_282; + wire n_1_0_283; + wire n_1_0_284; + wire n_1_0_285; + wire n_1_0_286; + wire n_1_0_287; + wire n_1_0_288; + wire n_1_0_289; + wire n_1_0_290; + wire n_1_0_291; + wire n_1_0_292; + wire n_1_0_293; + wire n_1_0_294; + wire n_1_0_295; + wire n_1_0_296; + wire n_1_0_297; + wire n_1_0_298; + wire n_1_0_299; + wire n_1_0_300; + wire n_1_0_301; + wire n_1_0_302; + wire n_1_0_303; + wire n_1_0_304; + wire n_1_0_305; + wire n_1_0_306; + wire n_1_0_307; + wire n_1_0_308; + wire n_1_0_309; + wire n_1_0_310; + wire n_1_0_311; + wire n_1_0_312; + wire n_1_0_313; + wire n_1_0_314; + wire n_1_0_315; + wire n_1_0_316; + wire n_1_0_317; + wire n_1_0_318; + wire n_1_0_319; + wire n_1_0_320; + wire n_1_0_321; + wire n_1_0_322; + wire n_1_0_323; + wire n_1_0_324; + wire n_1_0_325; + wire n_1_0_326; + wire n_1_0_327; + wire n_1_0_328; + wire n_1_0_329; + wire n_1_0_330; + wire n_1_0_331; + wire n_1_0_332; + wire n_1_0_333; + wire n_1_0_334; + wire n_1_0_335; + wire n_1_0_336; + wire n_1_0_337; + wire n_1_0_338; + wire n_1_0_339; + wire n_1_0_340; + wire n_1_0_341; + wire n_1_0_342; + wire n_1_0_343; + wire n_1_0_344; + wire n_1_0_345; + wire n_1_0_346; + wire n_1_0_347; + wire n_1_0_348; + wire n_1_0_349; + wire n_1_0_350; + wire n_1_0_351; + wire n_1_0_352; + wire n_1_0_353; + wire n_1_0_354; + wire n_1_0_355; + wire n_1_0_356; + wire n_1_0_357; + wire n_1_0_358; + wire n_1_0_359; + wire n_1_0_360; + wire n_1_0_361; + wire n_1_0_362; + wire n_1_0_363; + wire n_1_0_364; + wire n_1_0_365; + wire n_1_0_366; + wire n_1_0_367; + wire n_1_0_368; + wire n_1_0_369; + wire n_1_0_370; + wire n_1_0_371; + wire n_1_0_372; + wire n_1_0_373; + wire n_1_0_374; + wire n_1_0_375; + wire n_1_0_376; + wire n_1_0_377; + wire n_1_0_378; + wire n_1_0_379; + wire n_1_0_380; + wire n_1_0_381; + wire n_1_0_382; + wire n_1_0_383; + wire n_1_0_384; + wire n_1_0_385; + wire n_1_0_386; + wire n_1_0_387; + wire n_1_0_388; + wire n_1_0_389; + wire n_1_0_390; + wire n_1_0_391; + wire n_1_0_392; + wire n_1_0_393; + wire n_1_0_394; + wire n_1_0_395; + wire n_1_0_396; + wire n_1_0_397; + wire n_1_0_398; + wire n_1_0_399; + wire n_1_0_400; + wire n_1_0_401; + wire n_1_0_402; + wire n_1_0_403; + wire n_1_0_404; + wire n_1_0_405; + wire n_1_0_406; + wire n_1_0_407; + wire n_1_0_408; + wire n_1_0_409; + wire n_1_0_410; + wire n_1_0_411; + wire n_1_0_412; + wire n_1_0_413; + wire n_1_0_414; + wire n_1_0_415; + wire n_1_0_416; + wire n_1_0_417; + wire n_1_0_418; + wire n_1_0_419; + wire n_1_0_420; + wire n_1_0_421; + wire n_1_0_422; + wire n_1_0_423; + wire n_1_0_424; + wire n_1_0_425; + wire n_1_0_426; + wire n_1_0_427; + wire n_1_0_428; + wire n_1_0_429; + wire n_1_0_430; + wire n_1_0_431; + wire n_1_0_432; + wire n_1_0_433; + wire n_1_0_434; + wire n_1_0_435; + wire n_1_0_436; + wire n_1_0_437; + wire n_1_0_438; + wire n_1_0_439; + wire n_1_0_440; + wire n_1_0_441; + wire n_1_0_442; + wire n_1_0_443; + wire n_1_0_444; + wire n_1_0_445; + wire n_1_0_446; + wire n_1_0_447; + wire n_1_0_448; + wire n_1_0_449; + wire n_1_0_450; + wire n_1_0_451; + wire n_1_0_452; + wire n_1_0_453; + wire n_1_0_454; + wire n_1_0_455; + wire n_1_0_456; + wire n_1_0_457; + wire n_1_0_458; + wire n_1_0_459; + wire n_1_0_460; + wire n_1_0_461; + wire n_1_0_462; + wire n_1_0_463; + wire n_1_0_464; + wire n_1_0_465; + wire n_1_0_466; + wire n_1_0_467; + wire n_1_0_468; + wire n_1_0_469; + wire n_1_0_470; + wire n_1_0_471; + wire n_1_0_472; + wire n_1_0_473; + wire n_1_0_474; + wire n_1_0_475; + wire n_1_0_476; + wire n_1_0_477; + wire n_1_0_478; + wire n_1_0_479; + wire n_1_0_480; + wire n_1_0_481; + wire n_1_0_482; + wire n_1_0_483; + wire n_1_0_484; + wire n_1_0_485; + wire n_1_0_486; + wire n_1_0_487; + wire n_1_0_488; + wire n_1_0_489; + wire n_1_0_490; + wire n_1_0_491; + wire n_1_0_492; + wire n_1_0_493; + wire n_1_0_494; + wire n_1_0_495; + wire n_1_0_496; + wire n_1_0_497; + wire n_1_0_498; + wire n_1_0_499; + wire n_1_0_500; + wire n_1_0_501; + wire n_1_0_502; + wire n_1_0_503; + wire n_1_0_504; + wire n_1_0_505; + wire n_1_0_506; + wire n_1_0_507; + wire n_1_0_508; + wire n_1_0_509; + wire n_1_0_510; + wire n_1_0_511; + wire n_1_0_512; + wire n_1_0_513; + wire n_1_0_514; + wire n_1_0_515; + wire n_1_0_516; + wire n_1_0_517; + wire n_1_0_518; + wire n_1_0_519; + wire n_1_0_520; + wire n_1_0_521; + wire n_1_0_522; + wire n_1_0_523; + wire n_1_0_524; + wire n_1_0_525; + wire n_1_0_526; + wire n_1_0_527; + wire n_1_0_528; + wire n_1_0_529; + wire n_1_0_530; + wire n_1_0_531; + wire n_1_0_532; + wire n_1_0_533; + wire n_1_0_534; + wire n_1_0_535; + wire n_1_0_536; + wire n_1_0_537; + wire n_1_0_538; + wire n_1_0_539; + wire n_1_0_540; + wire n_1_0_541; + wire n_1_0_542; + wire n_1_0_543; + wire n_1_0_544; + wire n_1_0_545; + wire n_1_0_546; + wire n_1_0_547; + wire n_1_0_548; + wire n_1_0_549; + wire n_1_0_550; + wire n_1_0_551; + wire n_1_0_552; + wire n_1_0_553; + wire n_1_0_554; + wire n_1_0_555; + wire n_1_0_556; + wire n_1_0_557; + wire n_1_0_558; + wire n_1_0_559; + wire n_1_0_560; + wire n_1_0_561; + wire n_1_0_562; + wire n_1_0_563; + wire n_1_0_564; + wire n_1_0_565; + wire n_1_0_566; + wire n_1_0_567; + wire n_1_0_568; + wire n_1_0_569; + wire n_1_0_570; + wire n_1_0_571; + wire n_1_0_572; + wire n_1_0_573; + wire n_1_0_574; + wire n_1_0_575; + wire n_1_0_576; + wire n_1_0_577; + wire n_1_0_578; + wire n_1_0_579; + wire n_1_0_580; + wire n_1_0_581; + wire n_1_0_582; + wire n_1_0_583; + wire n_1_0_584; + wire n_1_0_585; + wire n_1_0_586; + wire n_1_0_587; + wire n_1_0_588; + wire n_1_0_589; + wire n_1_0_590; + wire n_1_0_591; + wire n_1_0_592; + wire n_1_0_593; + wire n_1_0_594; + wire n_1_0_595; + wire n_1_0_596; + wire n_1_0_597; + wire n_1_0_598; + wire n_1_0_599; + wire n_1_0_600; + wire n_1_0_601; + wire n_1_0_602; + wire n_1_0_603; + wire n_1_0_604; + wire n_1_0_605; + wire n_1_0_606; + wire n_1_0_607; + wire n_1_0_608; + wire n_1_0_609; + wire n_1_0_610; + wire n_1_0_611; + wire n_1_0_612; + wire n_1_0_613; + wire n_1_0_614; + wire n_1_0_615; + wire n_1_0_616; + wire n_1_0_617; + wire n_1_0_618; + wire n_1_0_619; + wire n_1_0_620; + wire n_1_0_621; + wire n_1_0_622; + wire n_1_0_623; + wire n_1_0_624; + wire n_1_0_625; + wire n_1_0_626; + wire n_1_0_627; + wire n_1_0_628; + wire n_1_0_629; + wire n_1_0_630; + wire n_1_0_631; + wire n_1_0_632; + wire n_1_0_633; + wire n_1_0_634; + wire n_1_0_635; + wire n_1_0_636; + wire n_1_0_637; + wire n_1_0_638; + wire n_1_0_639; + wire n_1_0_640; + wire n_1_0_641; + wire n_1_0_642; + wire n_1_0_643; + wire n_1_0_644; + wire n_1_0_645; + wire n_1_0_646; + wire n_1_0_647; + wire n_1_0_648; + wire n_1_0_649; + wire n_1_0_650; + wire n_1_0_651; + wire n_1_0_652; + wire n_1_0_653; + wire n_1_0_654; + wire n_1_0_655; + wire n_1_0_656; + wire n_1_0_657; + wire n_1_0_658; + wire n_1_0_659; + wire n_1_0_660; + wire n_1_0_661; + wire n_1_0_662; + wire n_1_0_663; + wire n_1_0_664; + wire n_1_0_665; + wire n_1_0_666; + wire n_1_0_667; + wire n_1_0_668; + wire n_1_0_669; + wire n_1_0_670; + wire n_1_0_671; + wire n_1_0_672; + wire n_1_0_673; + wire n_1_0_674; + wire n_1_0_675; + wire n_1_0_676; + wire n_1_0_677; + wire n_1_0_678; + wire n_1_0_679; + wire n_1_0_680; + wire n_1_0_681; + wire n_1_0_682; + wire n_1_0_683; + wire n_1_0_684; + wire n_1_0_685; + wire n_1_0_686; + wire n_1_0_687; + wire n_1_0_688; + wire n_1_0_689; + wire n_1_0_690; + wire n_1_0_691; + wire n_1_0_692; + wire n_1_0_693; + wire n_1_0_694; + wire n_1_0_695; + wire n_1_0_696; + wire n_1_0_697; + wire n_1_0_698; + wire n_1_0_699; + wire n_1_0_700; + wire n_1_0_701; + wire n_1_0_702; + wire n_1_0_703; + wire n_1_0_704; + wire n_1_0_705; + wire n_1_0_706; + wire n_1_0_707; + wire n_1_0_708; + wire n_1_0_709; + wire n_1_0_710; + wire n_1_0_711; + wire n_1_0_712; + wire n_1_0_713; + wire n_1_0_714; + wire n_1_0_715; + wire n_1_0_716; + wire n_1_0_717; + wire n_1_0_718; + wire n_1_0_719; + wire n_1_0_720; + wire n_1_0_721; + wire n_1_0_722; + wire n_1_0_723; + wire n_1_0_724; + wire n_1_0_725; + wire n_1_0_726; + wire n_1_0_727; + wire n_1_0_728; + wire n_1_0_729; + wire n_1_0_730; + wire n_1_0_731; + wire n_1_0_732; + wire n_1_0_733; + wire n_1_0_734; + wire n_1_0_735; + wire n_1_0_736; + wire n_1_0_737; + wire n_1_0_738; + wire n_1_0_739; + wire n_1_0_740; + wire n_1_0_741; + wire n_1_0_742; + wire n_1_0_743; + wire n_1_0_744; + wire n_1_0_745; + wire n_1_0_746; + wire n_1_0_747; + wire n_1_0_748; + wire n_1_0_749; + wire n_1_0_750; + wire n_1_0_751; + wire n_1_0_752; + wire n_1_0_753; + wire n_1_0_754; + wire n_1_0_755; + wire n_1_0_756; + wire n_1_0_757; + wire n_1_0_758; + wire n_1_0_759; + wire n_1_0_760; + wire n_1_0_761; + wire n_1_0_762; + wire n_1_0_763; + wire n_1_0_764; + wire n_1_0_765; + wire n_1_0_766; + wire n_1_0_767; + wire n_1_0_768; + wire n_1_0_769; + wire n_1_0_770; + wire n_1_0_771; + wire n_1_0_772; + wire n_1_0_773; + wire n_1_0_774; + wire n_1_0_775; + wire n_1_0_776; + wire n_1_0_777; + wire n_1_0_778; + wire n_1_0_779; + wire n_1_0_780; + wire n_1_0_781; + wire n_1_0_782; + wire n_1_0_783; + wire n_1_0_784; + wire n_1_0_785; + wire n_1_0_786; + wire n_1_0_787; + wire n_1_0_788; + wire n_1_0_789; + wire n_1_0_790; + wire n_1_0_791; + wire n_1_0_792; + wire n_1_0_793; + wire n_1_0_794; + wire n_1_0_795; + wire n_1_0_796; + wire n_1_0_797; + wire n_1_0_798; + wire n_1_0_799; + wire n_1_0_800; + wire n_1_0_801; + wire n_1_0_802; + wire n_1_0_803; + wire n_1_0_804; + wire n_1_0_805; + wire n_1_0_806; + wire n_1_0_807; + wire n_1_0_808; + wire n_1_0_809; + wire n_1_0_810; + wire n_1_0_811; + wire n_1_0_812; + wire n_1_0_813; + wire n_1_0_814; + wire n_1_0_815; + wire n_1_0_816; + wire n_1_0_817; + wire n_1_0_818; + wire n_1_0_819; + wire n_1_0_820; + wire n_1_0_821; + wire n_1_0_822; + wire n_1_0_823; + wire n_1_0_824; + wire n_1_0_825; + wire n_1_0_826; + wire n_1_0_827; + wire n_1_0_828; + wire n_1_0_829; + wire n_1_0_830; + wire n_1_0_831; + wire n_1_0_832; + wire n_1_0_833; + wire n_1_0_834; + wire n_1_0_835; + wire n_1_0_836; + wire n_1_0_837; + wire n_1_0_838; + wire n_1_0_839; + wire n_1_0_840; + wire n_1_0_841; + wire n_1_0_842; + wire n_1_0_843; + wire n_1_0_844; + wire n_1_0_845; + wire n_1_0_846; + wire n_1_0_847; + wire n_1_0_848; + wire n_1_0_849; + wire n_1_0_850; + wire n_1_0_851; + wire n_1_0_852; + wire n_1_0_853; + wire n_1_0_854; + wire n_1_0_855; + wire n_1_0_856; + wire n_1_0_857; + wire n_1_0_858; + wire n_1_0_859; + wire n_1_0_860; + wire n_1_0_861; + wire n_1_0_862; + wire n_1_0_863; + wire n_1_0_864; + wire n_1_0_865; + wire n_1_0_866; + wire n_1_0_867; + wire n_1_0_868; + wire n_1_0_869; + wire n_1_0_870; + wire n_1_0_871; + wire n_1_0_872; + wire n_1_0_873; + wire n_1_0_874; + wire n_1_0_875; + wire n_1_0_876; + wire n_1_0_877; + wire n_1_0_878; + wire n_1_0_879; + wire n_1_0_880; + wire n_1_0_881; + wire n_1_0_882; + wire n_1_0_883; + wire n_1_0_884; + wire n_1_0_885; + wire n_1_0_886; + wire n_1_0_887; + wire n_1_0_888; + wire n_1_0_889; + wire n_1_0_890; + wire n_1_0_891; + wire n_1_0_892; + wire n_1_0_893; + wire n_1_0_894; + wire n_1_0_895; + wire n_1_0_896; + wire n_1_0_897; + wire n_1_0_898; + wire n_1_0_899; + wire n_1_0_900; + wire n_1_0_901; + wire n_1_0_902; + wire n_1_0_903; + wire n_1_0_904; + wire n_1_0_905; + wire n_1_0_906; + wire n_1_0_907; + wire n_1_0_908; + wire n_1_0_909; + wire n_1_0_910; + wire n_1_0_911; + wire n_1_0_912; + wire n_1_0_913; + wire n_1_0_914; + wire n_1_0_915; + wire n_1_0_916; + wire n_1_0_917; + wire n_1_0_918; + wire n_1_0_919; + wire n_1_0_920; + wire n_1_0_921; + wire n_1_0_922; + wire n_1_0_923; + wire n_1_0_924; + wire n_1_0_925; + wire n_1_0_926; + wire n_1_0_927; + wire n_1_0_928; + wire n_1_0_929; + wire n_1_0_930; + wire n_1_0_931; + wire n_1_0_932; + wire n_1_0_933; + wire n_1_0_934; + wire n_1_0_935; + wire n_1_0_936; + wire n_1_0_937; + wire n_1_0_938; + wire n_1_0_939; + wire n_1_0_940; + wire n_1_0_941; + wire n_1_0_942; + wire n_1_0_943; + wire n_1_0_944; + wire n_1_0_945; + wire n_1_0_946; + wire n_1_0_947; + wire n_1_0_948; + wire n_1_0_949; + wire n_1_0_950; + wire n_1_0_951; + wire n_1_0_952; + wire n_1_0_953; + wire n_1_0_954; + wire n_1_0_955; + wire n_1_0_956; + wire n_1_0_957; + wire n_1_0_958; + wire n_1_0_959; + wire n_1_0_960; + wire n_1_0_961; + wire n_1_0_962; + wire n_1_0_963; + wire n_1_0_964; + wire n_1_0_965; + wire n_1_0_966; + wire n_1_0_967; + wire n_1_0_968; + wire n_1_0_969; + wire n_1_0_970; + wire n_1_0_971; + wire n_1_0_972; + wire n_1_0_973; + wire n_1_0_974; + wire n_1_0_975; + wire n_1_0_976; + wire n_1_0_977; + wire n_1_0_978; + wire n_1_0_979; + wire n_1_0_980; + wire n_1_0_981; + wire n_1_0_982; + wire n_1_0_983; + wire n_1_0_984; + wire n_1_0_985; + wire n_1_0_986; + wire n_1_0_987; + wire n_1_0_988; + wire n_1_0_989; + wire n_1_0_990; + wire n_1_0_991; + wire n_1_0_992; + wire n_1_0_993; + wire n_1_0_994; + wire n_1_0_995; + wire n_1_0_996; + wire n_1_0_997; + wire n_1_0_998; + wire n_1_0_999; + wire n_1_0_1000; + wire n_1_0_1001; + wire n_1_0_1002; + wire n_1_0_1003; + wire n_1_0_1004; + wire n_1_0_1005; + wire n_1_0_1006; + wire n_1_0_1007; + wire n_1_0_1008; + wire n_1_0_1009; + wire n_1_0_1010; + wire n_1_0_1011; + wire n_1_0_1012; + wire n_1_0_1013; + wire n_1_0_1014; + wire n_1_0_1015; + wire n_1_0_1016; + wire n_1_0_1017; + wire n_1_0_1018; + wire n_1_0_1019; + wire n_1_0_1020; + wire n_1_0_1021; + wire n_1_0_1022; + wire n_1_0_1023; + wire n_1_0_1024; + wire n_1_0_1025; + wire n_1_0_1026; + wire n_1_0_1027; + wire n_1_0_1028; + wire n_1_0_1029; + wire n_1_0_1030; + wire n_1_0_1031; + wire n_1_0_1032; + wire n_1_0_1033; + wire n_1_0_1034; + wire n_1_0_1035; + wire n_1_0_1036; + wire n_1_0_1037; + wire n_1_0_1038; + wire n_1_0_1039; + wire n_1_0_1040; + wire n_1_0_1041; + wire n_1_0_1042; + wire n_1_0_1043; + wire n_1_0_1044; + wire n_1_0_1045; + wire n_1_0_1046; + wire n_1_0_1047; + wire n_1_0_1048; + wire n_1_0_1049; + wire n_1_0_1050; + wire n_1_0_1051; + wire n_1_0_1052; + wire n_1_0_1053; + wire n_1_0_1054; + wire n_1_0_1055; + wire n_1_0_1056; + wire n_1_0_1057; + wire n_1_0_1058; + wire n_1_0_1059; + wire n_1_0_1060; + wire n_1_0_1061; + wire n_1_0_1062; + wire n_1_0_1063; + wire n_1_0_1064; + wire n_1_0_1065; + wire n_1_0_1066; + wire n_1_0_1067; + wire n_1_0_1068; + wire n_1_0_1069; + wire n_1_0_1070; + wire n_1_0_1071; + wire n_1_0_1072; + wire n_1_0_1073; + wire n_1_0_1074; + wire n_1_0_1075; + wire n_1_0_1076; + wire n_1_0_1077; + wire n_1_0_1078; + wire n_1_0_1079; + wire n_1_0_1080; + wire n_1_0_1081; + wire n_1_0_1082; + wire n_1_0_1083; + wire n_1_0_1084; + wire n_1_0_1085; + wire n_1_0_1086; + wire n_1_0_1087; + wire n_1_0_1088; + wire n_1_0_1089; + wire n_1_0_1090; + wire n_1_0_1091; + wire n_1_0_1092; + wire n_1_0_1093; + wire n_1_0_1094; + wire n_1_0_1095; + wire n_1_0_1096; + wire n_1_0_1097; + wire n_1_0_1098; + wire n_1_0_1099; + wire n_1_0_1100; + wire n_1_0_1101; + wire n_1_0_1102; + wire n_1_0_1103; + wire n_1_0_1104; + wire n_1_0_1105; + wire n_1_0_1106; + wire n_1_0_1107; + wire n_1_0_1108; + wire n_1_0_1109; + wire n_1_0_1110; + wire n_1_0_1111; + wire n_1_0_1112; + wire n_1_0_1113; + wire n_1_0_1114; + wire n_1_0_1115; + wire n_1_0_1116; + wire n_1_0_1117; + wire n_1_0_1118; + wire n_1_0_1119; + wire n_1_0_1120; + wire n_1_0_1121; + wire n_1_0_1122; + wire n_1_0_1123; + wire n_1_0_1124; + wire n_1_0_1125; + wire n_1_0_1126; + wire n_1_0_1127; + wire n_1_0_1128; + wire n_1_0_1129; + wire n_1_0_1130; + wire n_1_0_1131; + wire n_1_0_1132; + wire n_1_0_1133; + wire n_1_0_1134; + wire n_1_0_1135; + wire n_1_0_1136; + wire n_1_0_1137; + wire n_1_0_1138; + wire n_1_0_1139; + wire n_1_0_1140; + wire n_1_0_1141; + wire n_1_0_1142; + wire n_1_0_1143; + wire n_1_0_1144; + wire n_1_0_1145; + wire n_1_0_1146; + wire n_1_0_1147; + wire n_1_0_1148; + wire n_1_0_1149; + wire n_1_0_1150; + wire n_1_0_1151; + wire n_1_0_1152; + wire n_1_0_1153; + wire n_1_0_1154; + wire n_1_0_1155; + wire n_1_0_1156; + wire n_1_0_1157; + wire n_1_0_1158; + wire n_1_0_1159; + wire n_1_0_1160; + wire n_1_0_1161; + wire n_1_0_1162; + wire n_1_0_1163; + wire n_1_0_1164; + wire n_1_0_1165; + wire n_1_0_1166; + wire n_1_0_1167; + wire n_1_0_1168; + wire n_1_0_1169; + wire n_1_0_1170; + wire n_1_0_1171; + wire n_1_0_1172; + wire n_1_0_1173; + wire n_1_0_1174; + wire n_1_0_1175; + wire n_1_0_1176; + wire n_1_0_1177; + wire n_1_0_1178; + wire n_1_0_1179; + wire n_1_0_1180; + wire n_1_0_1181; + wire n_1_0_1182; + wire n_1_0_1183; + wire n_1_0_1184; + wire n_1_0_1185; + wire n_1_0_1186; + wire n_1_0_1187; + wire n_1_0_1188; + wire n_1_0_1189; + wire n_1_0_1190; + wire n_1_0_1191; + wire n_1_0_1192; + wire n_1_0_1193; + wire n_1_0_1194; + wire n_1_0_1195; + wire n_1_0_1196; + wire n_1_0_1197; + wire n_1_0_1198; + wire n_1_0_1199; + wire n_1_0_1200; + wire n_1_0_1201; + wire n_1_0_1202; + wire n_1_0_1203; + wire n_1_0_1204; + wire n_1_0_1205; + wire n_1_0_1206; + wire n_1_0_1207; + wire n_1_0_1208; + wire n_1_0_1209; + wire n_1_0_1210; + wire n_1_0_1211; + wire n_1_0_1212; + wire n_1_0_1213; + wire n_1_0_1214; + wire n_1_0_1215; + wire n_1_0_1216; + wire n_1_0_1217; + wire n_1_0_1218; + wire n_1_0_1219; + wire n_1_0_1220; + wire n_1_0_1221; + wire n_1_0_1222; + wire n_1_0_1223; + wire n_1_0_1224; + wire n_1_0_1225; + wire n_1_0_1226; + wire n_1_0_1227; + wire n_1_0_1228; + wire n_1_0_1229; + wire n_1_0_1230; + wire n_1_0_1231; + wire n_1_0_1232; + wire n_1_0_1233; + wire n_1_0_1234; + wire n_1_0_1235; + wire n_1_0_1236; + wire n_1_0_1237; + wire n_1_0_1238; + wire n_1_0_1239; + wire n_1_0_1240; + wire n_1_0_1241; + wire n_1_0_1242; + wire n_1_0_1243; + wire n_1_0_1244; + wire n_1_0_1245; + wire n_1_0_1246; + wire n_1_0_1247; + wire n_1_0_1248; + wire n_1_0_1249; + wire n_1_0_1250; + wire n_1_0_1251; + wire n_1_0_1252; + wire n_1_0_1253; + wire n_1_0_1254; + wire n_1_0_1255; + wire n_1_0_1256; + wire n_1_0_1257; + wire n_1_0_1258; + wire n_1_0_1259; + wire n_1_0_1260; + wire n_1_0_1261; + wire n_1_0_1262; + wire n_1_0_1263; + wire n_1_0_1264; + wire n_1_0_1265; + wire n_1_0_1266; + wire n_1_0_1267; + wire n_1_0_1268; + wire n_1_0_1269; + wire n_1_0_1270; + wire n_1_0_1271; + wire n_1_0_1272; + wire n_1_0_1273; + wire n_1_0_1274; + wire n_1_0_1275; + wire n_1_0_1276; + wire n_1_0_1277; + wire n_1_0_1278; + wire n_1_0_1279; + wire n_1_0_1280; + wire n_1_0_1281; + wire n_1_0_1282; + wire n_1_0_1283; + wire n_1_0_1284; + wire n_1_0_1285; + wire n_1_0_1286; + wire n_1_0_1287; + wire n_1_0_1288; + wire n_1_0_1289; + wire n_1_0_1290; + wire n_1_0_1291; + wire n_1_0_1292; + wire n_1_0_1293; + wire n_1_0_1294; + wire n_1_0_1295; + wire n_1_0_1296; + wire n_1_0_1297; + wire n_1_0_1298; + wire n_1_0_1299; + wire n_1_0_1300; + wire n_1_0_1301; + wire n_1_0_1302; + wire n_1_0_1303; + wire n_1_0_1304; + wire n_1_0_1305; + wire n_1_0_1306; + wire n_1_0_1307; + wire n_1_0_1308; + wire n_1_0_1309; + + INV_X1_LVT i_0_0_79 (.A(reset), .ZN(n_0_0_16)); + AND2_X1_LVT i_0_0_31 (.A1(n_0_0_16), .A2(WRd[31]), .ZN(registers[31])); + INV_X1_LVT i_0_0_81 (.A(Rd[1]), .ZN(n_0_0_18)); + INV_X1_LVT i_0_0_80 (.A(Rd[0]), .ZN(n_0_0_17)); + NAND3_X1_LVT i_0_0_69 (.A1(n_0_0_18), .A2(n_0_0_17), .A3(Rd[2]), .ZN(n_0_0_9)); + NAND3_X1_LVT i_0_0_41 (.A1(Rd[3]), .A2(WrReg), .A3(Rd[4]), .ZN(n_0_0_1)); + OAI21_X1_LVT i_0_0_35 (.A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_1), .ZN(n_0_28)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[28]_reg (.CK(clk), .E(n_0_28), + .SE(dftIn), .GCK(n_0_58)); + SDFF_X1_LVT \registers_reg[28][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_28__ap[31]), .CK(n_0_58), .Q(registers_28__ap[31]), .QN()); + INV_X1_LVT i_1_0_1370 (.A(Rs1[0]), .ZN(n_1_0_1306)); + NAND3_X1_LVT i_1_0_1354 (.A1(n_1_0_1306), .A2(Rs1[3]), .A3(Rs1[4]), .ZN( + n_1_0_1290)); + INV_X1_LVT i_1_0_1373 (.A(Rs1[2]), .ZN(n_1_0_1309)); + OR2_X1_LVT i_1_0_1348 (.A1(n_1_0_1309), .A2(Rs1[1]), .ZN(n_1_0_1284)); + NOR2_X1_LVT i_1_0_1347 (.A1(n_1_0_1290), .A2(n_1_0_1284), .ZN(n_1_0_1283)); + NOR4_X1_LVT i_1_0_1342 (.A1(n_1_0_1284), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), + .ZN(n_1_0_1278)); + INV_X1_LVT i_0_0_83 (.A(WrReg), .ZN(n_0_0_20)); + OR3_X1_LVT i_0_0_77 (.A1(n_0_0_20), .A2(Rd[4]), .A3(Rd[3]), .ZN(n_0_0_14)); + OAI21_X1_LVT i_0_0_68 (.A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_9), .ZN(n_0_4)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[4]_reg (.CK(clk), .E(n_0_4), + .SE(dftIn), .GCK(n_0_34)); + SDFF_X1_LVT \registers_reg[4][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_4__ap[31]), .CK(n_0_34), .Q(registers_4__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1320 (.A1(registers_28__ap[31]), .A2(n_1_0_1283), .B1( + n_1_0_1278), .B2(registers_4__ap[31]), .ZN(n_1_0_1256)); + NAND2_X1_LVT i_0_0_70 (.A1(n_0_0_18), .A2(n_0_0_17), .ZN(n_0_0_10)); + INV_X1_LVT i_0_0_82 (.A(Rd[4]), .ZN(n_0_0_19)); + OR3_X1_LVT i_0_0_51 (.A1(n_0_0_20), .A2(n_0_0_19), .A3(Rd[3]), .ZN(n_0_0_3)); + OR2_X1_LVT i_0_0_50 (.A1(n_0_0_3), .A2(Rd[2]), .ZN(n_0_0_2)); + OAI21_X1_LVT i_0_0_49 (.A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_2), .ZN(n_0_16)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[16]_reg (.CK(clk), .E(n_0_16), + .SE(dftIn), .GCK(n_0_46)); + SDFF_X1_LVT \registers_reg[16][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_16__ap[31]), .CK(n_0_46), .Q(registers_16__ap[31]), .QN()); + INV_X1_LVT i_1_0_1371 (.A(Rs1[3]), .ZN(n_1_0_1307)); + NAND3_X1_LVT i_1_0_1363 (.A1(n_1_0_1307), .A2(n_1_0_1306), .A3(Rs1[4]), + .ZN(n_1_0_1299)); + OR2_X1_LVT i_1_0_1357 (.A1(Rs1[1]), .A2(Rs1[2]), .ZN(n_1_0_1293)); + NOR2_X1_LVT i_1_0_1331 (.A1(n_1_0_1299), .A2(n_1_0_1293), .ZN(n_1_0_1267)); + NAND2_X1_LVT i_1_0_1365 (.A1(Rs1[1]), .A2(Rs1[2]), .ZN(n_1_0_1301)); + NAND3_X1_LVT i_1_0_1344 (.A1(Rs1[4]), .A2(Rs1[3]), .A3(Rs1[0]), .ZN( + n_1_0_1280)); + NOR2_X1_LVT i_1_0_1330 (.A1(n_1_0_1301), .A2(n_1_0_1280), .ZN(n_1_0_1266)); + NAND3_X1_LVT i_0_0_63 (.A1(Rd[2]), .A2(Rd[1]), .A3(Rd[0]), .ZN(n_0_0_6)); + OAI21_X1_LVT i_0_0_32 (.A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_1), .ZN(n_0_31)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[31]_reg (.CK(clk), .E(n_0_31), + .SE(dftIn), .GCK(n_0_61)); + SDFF_X1_LVT \registers_reg[31][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_31__ap[31]), .CK(n_0_61), .Q(registers_31__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1329 (.A1(registers_16__ap[31]), .A2(n_1_0_1267), .B1( + n_1_0_1266), .B2(registers_31__ap[31]), .ZN(n_1_0_1265)); + NAND3_X1_LVT i_0_0_65 (.A1(n_0_0_17), .A2(Rd[1]), .A3(Rd[2]), .ZN(n_0_0_7)); + OAI21_X1_LVT i_0_0_64 (.A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_7), .ZN(n_0_6)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[6]_reg (.CK(clk), .E(n_0_6), + .SE(dftIn), .GCK(n_0_36)); + SDFF_X1_LVT \registers_reg[6][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_6__ap[31]), .CK(n_0_36), .Q(registers_6__ap[31]), .QN()); + NOR4_X1_LVT i_1_0_1364 (.A1(n_1_0_1301), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), + .ZN(n_1_0_1300)); + INV_X1_LVT i_1_0_1372 (.A(Rs1[4]), .ZN(n_1_0_1308)); + NAND3_X1_LVT i_1_0_1339 (.A1(n_1_0_1308), .A2(n_1_0_1307), .A3(Rs1[0]), + .ZN(n_1_0_1275)); + NOR2_X1_LVT i_1_0_1338 (.A1(n_1_0_1293), .A2(n_1_0_1275), .ZN(n_1_0_1274)); + NAND2_X1_LVT i_0_0_78 (.A1(n_0_0_18), .A2(Rd[0]), .ZN(n_0_0_15)); + OR2_X1_LVT i_0_0_76 (.A1(n_0_0_14), .A2(Rd[2]), .ZN(n_0_0_13)); + OAI21_X1_LVT i_0_0_75 (.A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_13), .ZN(n_0_1)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[1]_reg (.CK(clk), .E(n_0_1), + .SE(dftIn), .GCK(n_0_0)); + SDFF_X1_LVT \registers_reg[1][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_1__ap[31]), .CK(n_0_0), .Q(registers_1__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1319 (.A1(registers_6__ap[31]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[31]), .ZN(n_1_0_1255)); + OAI21_X1_LVT i_0_0_42 (.A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_3), .ZN(n_0_23)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[23]_reg (.CK(clk), .E(n_0_23), + .SE(dftIn), .GCK(n_0_53)); + SDFF_X1_LVT \registers_reg[23][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_23__ap[31]), .CK(n_0_53), .Q(registers_23__ap[31]), .QN()); + NAND3_X1_LVT i_1_0_1360 (.A1(n_1_0_1307), .A2(Rs1[0]), .A3(Rs1[4]), .ZN( + n_1_0_1296)); + NOR2_X1_LVT i_1_0_1328 (.A1(n_1_0_1301), .A2(n_1_0_1296), .ZN(n_1_0_1264)); + NOR2_X1_LVT i_1_0_1327 (.A1(n_1_0_1301), .A2(n_1_0_1275), .ZN(n_1_0_1263)); + OAI21_X1_LVT i_0_0_62 (.A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_6), .ZN(n_0_7)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[7]_reg (.CK(clk), .E(n_0_7), + .SE(dftIn), .GCK(n_0_37)); + SDFF_X1_LVT \registers_reg[7][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_7__ap[31]), .CK(n_0_37), .Q(registers_7__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1326 (.A1(registers_23__ap[31]), .A2(n_1_0_1264), .B1( + n_1_0_1263), .B2(registers_7__ap[31]), .ZN(n_1_0_1262)); + INV_X1_LVT i_1_0_1325 (.A(n_1_0_1262), .ZN(n_1_0_1261)); + NAND2_X1_LVT i_1_0_1362 (.A1(n_1_0_1309), .A2(Rs1[1]), .ZN(n_1_0_1298)); + NOR2_X1_LVT i_1_0_1359 (.A1(n_1_0_1298), .A2(n_1_0_1296), .ZN(n_1_0_1295)); + NAND2_X1_LVT i_0_0_72 (.A1(Rd[1]), .A2(Rd[0]), .ZN(n_0_0_11)); + OAI21_X1_LVT i_0_0_46 (.A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_2), .ZN(n_0_19)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[19]_reg (.CK(clk), .E(n_0_19), + .SE(dftIn), .GCK(n_0_49)); + SDFF_X1_LVT \registers_reg[19][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_19__ap[31]), .CK(n_0_49), .Q(registers_19__ap[31]), .QN()); + NAND3_X1_LVT i_0_0_67 (.A1(n_0_0_18), .A2(Rd[0]), .A3(Rd[2]), .ZN(n_0_0_8)); + OAI21_X1_LVT i_0_0_66 (.A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_8), .ZN(n_0_5)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[5]_reg (.CK(clk), .E(n_0_5), + .SE(dftIn), .GCK(n_0_35)); + SDFF_X1_LVT \registers_reg[5][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_5__ap[31]), .CK(n_0_35), .Q(registers_5__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1337 (.A1(n_1_0_1284), .A2(n_1_0_1275), .ZN(n_1_0_1273)); + AOI221_X1_LVT i_1_0_1318 (.A(n_1_0_1261), .B1(n_1_0_1295), .B2( + registers_19__ap[31]), .C1(registers_5__ap[31]), .C2(n_1_0_1273), .ZN( + n_1_0_1254)); + NAND2_X1_LVT i_0_0_74 (.A1(n_0_0_17), .A2(Rd[1]), .ZN(n_0_0_12)); + NAND3_X1_LVT i_0_0_61 (.A1(n_0_0_19), .A2(WrReg), .A3(Rd[3]), .ZN(n_0_0_5)); + OR2_X1_LVT i_0_0_60 (.A1(n_0_0_5), .A2(Rd[2]), .ZN(n_0_0_4)); + OAI21_X1_LVT i_0_0_57 (.A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_4), .ZN(n_0_10)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[10]_reg (.CK(clk), .E(n_0_10), + .SE(dftIn), .GCK(n_0_40)); + SDFF_X1_LVT \registers_reg[10][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_10__ap[31]), .CK(n_0_40), .Q(registers_10__ap[31]), .QN()); + NAND3_X1_LVT i_1_0_1352 (.A1(n_1_0_1308), .A2(n_1_0_1306), .A3(Rs1[3]), + .ZN(n_1_0_1288)); + NOR2_X1_LVT i_1_0_1351 (.A1(n_1_0_1298), .A2(n_1_0_1288), .ZN(n_1_0_1287)); + NOR2_X1_LVT i_1_0_1349 (.A1(n_1_0_1298), .A2(n_1_0_1290), .ZN(n_1_0_1285)); + OR2_X1_LVT i_0_0_40 (.A1(n_0_0_1), .A2(Rd[2]), .ZN(n_0_0_0)); + OAI21_X1_LVT i_0_0_37 (.A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_0), .ZN(n_0_26)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[26]_reg (.CK(clk), .E(n_0_26), + .SE(dftIn), .GCK(n_0_56)); + SDFF_X1_LVT \registers_reg[26][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_26__ap[31]), .CK(n_0_56), .Q(registers_26__ap[31]), .QN()); + OAI21_X1_LVT i_0_0_59 (.A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_4), .ZN(n_0_8)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[8]_reg (.CK(clk), .E(n_0_8), + .SE(dftIn), .GCK(n_0_38)); + SDFF_X1_LVT \registers_reg[8][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_8__ap[31]), .CK(n_0_38), .Q(registers_8__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1346 (.A1(n_1_0_1293), .A2(n_1_0_1288), .ZN(n_1_0_1282)); + AOI222_X1_LVT i_1_0_1317 (.A1(registers_10__ap[31]), .A2(n_1_0_1287), + .B1(n_1_0_1285), .B2(registers_26__ap[31]), .C1(registers_8__ap[31]), + .C2(n_1_0_1282), .ZN(n_1_0_1253)); + NAND4_X1_LVT i_1_0_1316 (.A1(n_1_0_1265), .A2(n_1_0_1255), .A3(n_1_0_1254), + .A4(n_1_0_1253), .ZN(n_1_0_1252)); + NAND3_X1_LVT i_1_0_1356 (.A1(n_1_0_1308), .A2(Rs1[3]), .A3(Rs1[0]), .ZN( + n_1_0_1292)); + NOR2_X1_LVT i_1_0_1355 (.A1(n_1_0_1293), .A2(n_1_0_1292), .ZN(n_1_0_1291)); + OAI21_X1_LVT i_0_0_58 (.A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_4), .ZN(n_0_9)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[9]_reg (.CK(clk), .E(n_0_9), + .SE(dftIn), .GCK(n_0_39)); + SDFF_X1_LVT \registers_reg[9][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_9__ap[31]), .CK(n_0_39), .Q(registers_9__ap[31]), .QN()); + OAI21_X1_LVT i_0_0_34 (.A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_1), .ZN(n_0_29)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[29]_reg (.CK(clk), .E(n_0_29), + .SE(dftIn), .GCK(n_0_59)); + SDFF_X1_LVT \registers_reg[29][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_29__ap[31]), .CK(n_0_59), .Q(registers_29__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1340 (.A1(n_1_0_1284), .A2(n_1_0_1280), .ZN(n_1_0_1276)); + AOI221_X1_LVT i_1_0_1315 (.A(n_1_0_1252), .B1(n_1_0_1291), .B2( + registers_9__ap[31]), .C1(registers_29__ap[31]), .C2(n_1_0_1276), .ZN( + n_1_0_1251)); + OAI21_X1_LVT i_0_0_47 (.A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_2), .ZN(n_0_18)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[18]_reg (.CK(clk), .E(n_0_18), + .SE(dftIn), .GCK(n_0_48)); + SDFF_X1_LVT \registers_reg[18][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_18__ap[31]), .CK(n_0_48), .Q(registers_18__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1361 (.A1(n_1_0_1299), .A2(n_1_0_1298), .ZN(n_1_0_1297)); + NOR2_X1_LVT i_1_0_1336 (.A1(n_1_0_1301), .A2(n_1_0_1290), .ZN(n_1_0_1272)); + OAI21_X1_LVT i_0_0_33 (.A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_1), .ZN(n_0_30)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[30]_reg (.CK(clk), .E(n_0_30), + .SE(dftIn), .GCK(n_0_60)); + SDFF_X1_LVT \registers_reg[30][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_30__ap[31]), .CK(n_0_60), .Q(registers_30__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1314 (.A1(registers_18__ap[31]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[31]), .ZN(n_1_0_1250)); + OAI21_X1_LVT i_0_0_39 (.A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_0), .ZN(n_0_24)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[24]_reg (.CK(clk), .E(n_0_24), + .SE(dftIn), .GCK(n_0_54)); + SDFF_X1_LVT \registers_reg[24][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_24__ap[31]), .CK(n_0_54), .Q(registers_24__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1353 (.A1(n_1_0_1293), .A2(n_1_0_1290), .ZN(n_1_0_1289)); + NOR2_X1_LVT i_1_0_1324 (.A1(n_1_0_1288), .A2(n_1_0_1284), .ZN(n_1_0_1260)); + OAI21_X1_LVT i_0_0_55 (.A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_5), .ZN(n_0_12)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[12]_reg (.CK(clk), .E(n_0_12), + .SE(dftIn), .GCK(n_0_42)); + SDFF_X1_LVT \registers_reg[12][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_12__ap[31]), .CK(n_0_42), .Q(registers_12__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1313 (.A1(registers_24__ap[31]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[31]), .ZN(n_1_0_1249)); + OAI21_X1_LVT i_0_0_43 (.A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_3), .ZN(n_0_22)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[22]_reg (.CK(clk), .E(n_0_22), + .SE(dftIn), .GCK(n_0_52)); + SDFF_X1_LVT \registers_reg[22][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_22__ap[31]), .CK(n_0_52), .Q(registers_22__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1358 (.A1(n_1_0_1301), .A2(n_1_0_1299), .ZN(n_1_0_1294)); + NOR2_X1_LVT i_1_0_1323 (.A1(n_1_0_1296), .A2(n_1_0_1284), .ZN(n_1_0_1259)); + OAI21_X1_LVT i_0_0_44 (.A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_3), .ZN(n_0_21)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[21]_reg (.CK(clk), .E(n_0_21), + .SE(dftIn), .GCK(n_0_51)); + SDFF_X1_LVT \registers_reg[21][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_21__ap[31]), .CK(n_0_51), .Q(registers_21__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1312 (.A1(registers_22__ap[31]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[31]), .ZN(n_1_0_1248)); + NAND3_X1_LVT i_1_0_1311 (.A1(n_1_0_1250), .A2(n_1_0_1249), .A3(n_1_0_1248), + .ZN(n_1_0_1247)); + NOR2_X1_LVT i_1_0_1335 (.A1(n_1_0_1296), .A2(n_1_0_1293), .ZN(n_1_0_1271)); + OAI21_X1_LVT i_0_0_48 (.A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_2), .ZN(n_0_17)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[17]_reg (.CK(clk), .E(n_0_17), + .SE(dftIn), .GCK(n_0_47)); + SDFF_X1_LVT \registers_reg[17][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_17__ap[31]), .CK(n_0_47), .Q(registers_17__ap[31]), .QN()); + OAI21_X1_LVT i_0_0_45 (.A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_3), .ZN(n_0_20)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[20]_reg (.CK(clk), .E(n_0_20), + .SE(dftIn), .GCK(n_0_50)); + SDFF_X1_LVT \registers_reg[20][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_20__ap[31]), .CK(n_0_50), .Q(registers_20__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1345 (.A1(n_1_0_1299), .A2(n_1_0_1284), .ZN(n_1_0_1281)); + AOI221_X1_LVT i_1_0_1310 (.A(n_1_0_1247), .B1(n_1_0_1271), .B2( + registers_17__ap[31]), .C1(registers_20__ap[31]), .C2(n_1_0_1281), + .ZN(n_1_0_1246)); + OAI21_X1_LVT i_0_0_36 (.A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_0), .ZN(n_0_27)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[27]_reg (.CK(clk), .E(n_0_27), + .SE(dftIn), .GCK(n_0_57)); + SDFF_X1_LVT \registers_reg[27][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_27__ap[31]), .CK(n_0_57), .Q(registers_27__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1343 (.A1(n_1_0_1298), .A2(n_1_0_1280), .ZN(n_1_0_1279)); + NOR2_X1_LVT i_1_0_1334 (.A1(n_1_0_1298), .A2(n_1_0_1292), .ZN(n_1_0_1270)); + OAI21_X1_LVT i_0_0_56 (.A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_4), .ZN(n_0_11)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[11]_reg (.CK(clk), .E(n_0_11), + .SE(dftIn), .GCK(n_0_41)); + SDFF_X1_LVT \registers_reg[11][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_11__ap[31]), .CK(n_0_41), .Q(registers_11__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1309 (.A1(registers_27__ap[31]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[31]), .ZN(n_1_0_1245)); + OAI21_X1_LVT i_0_0_54 (.A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_5), .ZN(n_0_13)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[13]_reg (.CK(clk), .E(n_0_13), + .SE(dftIn), .GCK(n_0_43)); + SDFF_X1_LVT \registers_reg[13][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_13__ap[31]), .CK(n_0_43), .Q(registers_13__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1341 (.A1(n_1_0_1292), .A2(n_1_0_1284), .ZN(n_1_0_1277)); + NOR2_X1_LVT i_1_0_1333 (.A1(n_1_0_1293), .A2(n_1_0_1280), .ZN(n_1_0_1269)); + OAI21_X1_LVT i_0_0_38 (.A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_0), .ZN(n_0_25)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[25]_reg (.CK(clk), .E(n_0_25), + .SE(dftIn), .GCK(n_0_55)); + SDFF_X1_LVT \registers_reg[25][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_25__ap[31]), .CK(n_0_55), .Q(registers_25__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1308 (.A1(registers_13__ap[31]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[31]), .ZN(n_1_0_1244)); + OAI21_X1_LVT i_0_0_52 (.A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_5), .ZN(n_0_15)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[15]_reg (.CK(clk), .E(n_0_15), + .SE(dftIn), .GCK(n_0_45)); + SDFF_X1_LVT \registers_reg[15][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_15__ap[31]), .CK(n_0_45), .Q(registers_15__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1350 (.A1(n_1_0_1301), .A2(n_1_0_1292), .ZN(n_1_0_1286)); + NOR2_X1_LVT i_1_0_1322 (.A1(n_1_0_1301), .A2(n_1_0_1288), .ZN(n_1_0_1258)); + OAI21_X1_LVT i_0_0_53 (.A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_5), .ZN(n_0_14)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[14]_reg (.CK(clk), .E(n_0_14), + .SE(dftIn), .GCK(n_0_44)); + SDFF_X1_LVT \registers_reg[14][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_14__ap[31]), .CK(n_0_44), .Q(registers_14__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1307 (.A1(registers_15__ap[31]), .A2(n_1_0_1286), .B1( + n_1_0_1258), .B2(registers_14__ap[31]), .ZN(n_1_0_1243)); + NAND3_X1_LVT i_1_0_1306 (.A1(n_1_0_1245), .A2(n_1_0_1244), .A3(n_1_0_1243), + .ZN(n_1_0_1242)); + NOR2_X1_LVT i_1_0_1321 (.A1(n_1_0_1298), .A2(n_1_0_1275), .ZN(n_1_0_1257)); + OAI21_X1_LVT i_0_0_71 (.A(n_0_0_16), .B1(n_0_0_13), .B2(n_0_0_11), .ZN(n_0_3)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[3]_reg (.CK(clk), .E(n_0_3), + .SE(dftIn), .GCK(n_0_33)); + SDFF_X1_LVT \registers_reg[3][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_3__ap[31]), .CK(n_0_33), .Q(registers_3__ap[31]), .QN()); + OAI21_X1_LVT i_0_0_73 (.A(n_0_0_16), .B1(n_0_0_13), .B2(n_0_0_12), .ZN(n_0_2)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[2]_reg (.CK(clk), .E(n_0_2), + .SE(dftIn), .GCK(n_0_32)); + SDFF_X1_LVT \registers_reg[2][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_2__ap[31]), .CK(n_0_32), .Q(registers_2__ap[31]), .QN()); + NOR4_X1_LVT i_1_0_1332 (.A1(n_1_0_1298), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), + .ZN(n_1_0_1268)); + AOI221_X1_LVT i_1_0_1305 (.A(n_1_0_1242), .B1(n_1_0_1257), .B2( + registers_3__ap[31]), .C1(registers_2__ap[31]), .C2(n_1_0_1268), .ZN( + n_1_0_1241)); + NAND4_X1_LVT i_1_0_1304 (.A1(n_1_0_1256), .A2(n_1_0_1251), .A3(n_1_0_1246), + .A4(n_1_0_1241), .ZN(RRs1[31])); + AND2_X1_LVT i_0_0_30 (.A1(n_0_0_16), .A2(WRd[30]), .ZN(registers[30])); + SDFF_X1_LVT \registers_reg[28][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_28__ap[30]), .CK(n_0_58), .Q(registers_28__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[17][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_17__ap[30]), .CK(n_0_47), .Q(registers_17__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1300 (.A1(registers_28__ap[30]), .A2(n_1_0_1283), .B1( + n_1_0_1271), .B2(registers_17__ap[30]), .ZN(n_1_0_1237)); + SDFF_X1_LVT \registers_reg[16][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_16__ap[30]), .CK(n_0_46), .Q(registers_16__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[31][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_31__ap[30]), .CK(n_0_61), .Q(registers_31__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1303 (.A1(registers_16__ap[30]), .A2(n_1_0_1267), .B1( + n_1_0_1266), .B2(registers_31__ap[30]), .ZN(n_1_0_1240)); + SDFF_X1_LVT \registers_reg[6][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_6__ap[30]), .CK(n_0_36), .Q(registers_6__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[1][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_1__ap[30]), .CK(n_0_0), .Q(registers_1__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1299 (.A1(registers_6__ap[30]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[30]), .ZN(n_1_0_1236)); + SDFF_X1_LVT \registers_reg[23][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_23__ap[30]), .CK(n_0_53), .Q(registers_23__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[7][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_7__ap[30]), .CK(n_0_37), .Q(registers_7__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1302 (.A1(registers_23__ap[30]), .A2(n_1_0_1264), .B1( + n_1_0_1263), .B2(registers_7__ap[30]), .ZN(n_1_0_1239)); + INV_X1_LVT i_1_0_1301 (.A(n_1_0_1239), .ZN(n_1_0_1238)); + SDFF_X1_LVT \registers_reg[19][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_19__ap[30]), .CK(n_0_49), .Q(registers_19__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[5][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_5__ap[30]), .CK(n_0_35), .Q(registers_5__ap[30]), .QN()); + AOI221_X1_LVT i_1_0_1298 (.A(n_1_0_1238), .B1(n_1_0_1295), .B2( + registers_19__ap[30]), .C1(registers_5__ap[30]), .C2(n_1_0_1273), .ZN( + n_1_0_1235)); + SDFF_X1_LVT \registers_reg[10][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_10__ap[30]), .CK(n_0_40), .Q(registers_10__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[26][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_26__ap[30]), .CK(n_0_56), .Q(registers_26__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[8][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_8__ap[30]), .CK(n_0_38), .Q(registers_8__ap[30]), .QN()); + AOI222_X1_LVT i_1_0_1297 (.A1(registers_10__ap[30]), .A2(n_1_0_1287), + .B1(n_1_0_1285), .B2(registers_26__ap[30]), .C1(registers_8__ap[30]), + .C2(n_1_0_1282), .ZN(n_1_0_1234)); + NAND4_X1_LVT i_1_0_1296 (.A1(n_1_0_1240), .A2(n_1_0_1236), .A3(n_1_0_1235), + .A4(n_1_0_1234), .ZN(n_1_0_1233)); + SDFF_X1_LVT \registers_reg[9][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_9__ap[30]), .CK(n_0_39), .Q(registers_9__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[29][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_29__ap[30]), .CK(n_0_59), .Q(registers_29__ap[30]), .QN()); + AOI221_X1_LVT i_1_0_1295 (.A(n_1_0_1233), .B1(n_1_0_1291), .B2( + registers_9__ap[30]), .C1(registers_29__ap[30]), .C2(n_1_0_1276), .ZN( + n_1_0_1232)); + SDFF_X1_LVT \registers_reg[18][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_18__ap[30]), .CK(n_0_48), .Q(registers_18__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[30][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_30__ap[30]), .CK(n_0_60), .Q(registers_30__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1294 (.A1(registers_18__ap[30]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[30]), .ZN(n_1_0_1231)); + SDFF_X1_LVT \registers_reg[20][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_20__ap[30]), .CK(n_0_50), .Q(registers_20__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[4][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_4__ap[30]), .CK(n_0_34), .Q(registers_4__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1293 (.A1(registers_20__ap[30]), .A2(n_1_0_1281), .B1( + n_1_0_1278), .B2(registers_4__ap[30]), .ZN(n_1_0_1230)); + SDFF_X1_LVT \registers_reg[22][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_22__ap[30]), .CK(n_0_52), .Q(registers_22__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[21][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_21__ap[30]), .CK(n_0_51), .Q(registers_21__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1292 (.A1(registers_22__ap[30]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[30]), .ZN(n_1_0_1229)); + NAND3_X1_LVT i_1_0_1291 (.A1(n_1_0_1231), .A2(n_1_0_1230), .A3(n_1_0_1229), + .ZN(n_1_0_1228)); + SDFF_X1_LVT \registers_reg[24][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_24__ap[30]), .CK(n_0_54), .Q(registers_24__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[12][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_12__ap[30]), .CK(n_0_42), .Q(registers_12__ap[30]), .QN()); + AOI221_X1_LVT i_1_0_1290 (.A(n_1_0_1228), .B1(n_1_0_1289), .B2( + registers_24__ap[30]), .C1(registers_12__ap[30]), .C2(n_1_0_1260), + .ZN(n_1_0_1227)); + SDFF_X1_LVT \registers_reg[27][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_27__ap[30]), .CK(n_0_57), .Q(registers_27__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[11][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_11__ap[30]), .CK(n_0_41), .Q(registers_11__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1289 (.A1(registers_27__ap[30]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[30]), .ZN(n_1_0_1226)); + SDFF_X1_LVT \registers_reg[13][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_13__ap[30]), .CK(n_0_43), .Q(registers_13__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[25][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_25__ap[30]), .CK(n_0_55), .Q(registers_25__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1288 (.A1(registers_13__ap[30]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[30]), .ZN(n_1_0_1225)); + SDFF_X1_LVT \registers_reg[15][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_15__ap[30]), .CK(n_0_45), .Q(registers_15__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[14][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_14__ap[30]), .CK(n_0_44), .Q(registers_14__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1287 (.A1(registers_15__ap[30]), .A2(n_1_0_1286), .B1( + n_1_0_1258), .B2(registers_14__ap[30]), .ZN(n_1_0_1224)); + NAND3_X1_LVT i_1_0_1286 (.A1(n_1_0_1226), .A2(n_1_0_1225), .A3(n_1_0_1224), + .ZN(n_1_0_1223)); + SDFF_X1_LVT \registers_reg[3][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_3__ap[30]), .CK(n_0_33), .Q(registers_3__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[2][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_2__ap[30]), .CK(n_0_32), .Q(registers_2__ap[30]), .QN()); + AOI221_X1_LVT i_1_0_1285 (.A(n_1_0_1223), .B1(n_1_0_1257), .B2( + registers_3__ap[30]), .C1(registers_2__ap[30]), .C2(n_1_0_1268), .ZN( + n_1_0_1222)); + NAND4_X1_LVT i_1_0_1284 (.A1(n_1_0_1237), .A2(n_1_0_1232), .A3(n_1_0_1227), + .A4(n_1_0_1222), .ZN(RRs1[30])); + AND2_X1_LVT i_0_0_29 (.A1(n_0_0_16), .A2(WRd[29]), .ZN(registers[29])); + SDFF_X1_LVT \registers_reg[28][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_28__ap[29]), .CK(n_0_58), .Q(registers_28__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[8][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_8__ap[29]), .CK(n_0_38), .Q(registers_8__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1282 (.A1(registers_28__ap[29]), .A2(n_1_0_1283), .B1( + n_1_0_1282), .B2(registers_8__ap[29]), .ZN(n_1_0_1220)); + SDFF_X1_LVT \registers_reg[31][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_31__ap[29]), .CK(n_0_61), .Q(registers_31__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[7][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_7__ap[29]), .CK(n_0_37), .Q(registers_7__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1283 (.A1(registers_31__ap[29]), .A2(n_1_0_1266), .B1( + n_1_0_1263), .B2(registers_7__ap[29]), .ZN(n_1_0_1221)); + SDFF_X1_LVT \registers_reg[24][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_24__ap[29]), .CK(n_0_54), .Q(registers_24__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[20][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_20__ap[29]), .CK(n_0_50), .Q(registers_20__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1281 (.A1(registers_24__ap[29]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[29]), .ZN(n_1_0_1219)); + SDFF_X1_LVT \registers_reg[19][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_19__ap[29]), .CK(n_0_49), .Q(registers_19__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[4][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_4__ap[29]), .CK(n_0_34), .Q(registers_4__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1280 (.A1(registers_19__ap[29]), .A2(n_1_0_1295), .B1( + n_1_0_1278), .B2(registers_4__ap[29]), .ZN(n_1_0_1218)); + NAND3_X1_LVT i_1_0_1279 (.A1(n_1_0_1221), .A2(n_1_0_1219), .A3(n_1_0_1218), + .ZN(n_1_0_1217)); + SDFF_X1_LVT \registers_reg[23][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_23__ap[29]), .CK(n_0_53), .Q(registers_23__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[29][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_29__ap[29]), .CK(n_0_59), .Q(registers_29__ap[29]), .QN()); + AOI221_X1_LVT i_1_0_1278 (.A(n_1_0_1217), .B1(n_1_0_1264), .B2( + registers_23__ap[29]), .C1(registers_29__ap[29]), .C2(n_1_0_1276), + .ZN(n_1_0_1216)); + SDFF_X1_LVT \registers_reg[10][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_10__ap[29]), .CK(n_0_40), .Q(registers_10__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[26][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_26__ap[29]), .CK(n_0_56), .Q(registers_26__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[25][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_25__ap[29]), .CK(n_0_55), .Q(registers_25__ap[29]), .QN()); + AOI222_X1_LVT i_1_0_1277 (.A1(registers_10__ap[29]), .A2(n_1_0_1287), + .B1(n_1_0_1285), .B2(registers_26__ap[29]), .C1(registers_25__ap[29]), + .C2(n_1_0_1269), .ZN(n_1_0_1215)); + NAND3_X1_LVT i_1_0_1276 (.A1(n_1_0_1220), .A2(n_1_0_1216), .A3(n_1_0_1215), + .ZN(n_1_0_1214)); + SDFF_X1_LVT \registers_reg[21][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_21__ap[29]), .CK(n_0_51), .Q(registers_21__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[13][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_13__ap[29]), .CK(n_0_43), .Q(registers_13__ap[29]), .QN()); + AOI221_X1_LVT i_1_0_1275 (.A(n_1_0_1214), .B1(n_1_0_1259), .B2( + registers_21__ap[29]), .C1(registers_13__ap[29]), .C2(n_1_0_1277), + .ZN(n_1_0_1213)); + SDFF_X1_LVT \registers_reg[18][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_18__ap[29]), .CK(n_0_48), .Q(registers_18__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[30][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_30__ap[29]), .CK(n_0_60), .Q(registers_30__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1274 (.A1(registers_18__ap[29]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[29]), .ZN(n_1_0_1212)); + SDFF_X1_LVT \registers_reg[17][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_17__ap[29]), .CK(n_0_47), .Q(registers_17__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[12][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_12__ap[29]), .CK(n_0_42), .Q(registers_12__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1273 (.A1(registers_17__ap[29]), .A2(n_1_0_1271), .B1( + n_1_0_1260), .B2(registers_12__ap[29]), .ZN(n_1_0_1211)); + SDFF_X1_LVT \registers_reg[15][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_15__ap[29]), .CK(n_0_45), .Q(registers_15__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[16][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_16__ap[29]), .CK(n_0_46), .Q(registers_16__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1272 (.A1(registers_15__ap[29]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[29]), .ZN(n_1_0_1210)); + NAND3_X1_LVT i_1_0_1271 (.A1(n_1_0_1212), .A2(n_1_0_1211), .A3(n_1_0_1210), + .ZN(n_1_0_1209)); + SDFF_X1_LVT \registers_reg[22][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_22__ap[29]), .CK(n_0_52), .Q(registers_22__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[5][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_5__ap[29]), .CK(n_0_35), .Q(registers_5__ap[29]), .QN()); + AOI221_X1_LVT i_1_0_1270 (.A(n_1_0_1209), .B1(n_1_0_1294), .B2( + registers_22__ap[29]), .C1(registers_5__ap[29]), .C2(n_1_0_1273), .ZN( + n_1_0_1208)); + SDFF_X1_LVT \registers_reg[9][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_9__ap[29]), .CK(n_0_39), .Q(registers_9__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[1][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_1__ap[29]), .CK(n_0_0), .Q(registers_1__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1269 (.A1(registers_9__ap[29]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[29]), .ZN(n_1_0_1207)); + SDFF_X1_LVT \registers_reg[6][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_6__ap[29]), .CK(n_0_36), .Q(registers_6__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[14][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_14__ap[29]), .CK(n_0_44), .Q(registers_14__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1268 (.A1(registers_6__ap[29]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[29]), .ZN(n_1_0_1206)); + SDFF_X1_LVT \registers_reg[27][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_27__ap[29]), .CK(n_0_57), .Q(registers_27__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[11][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_11__ap[29]), .CK(n_0_41), .Q(registers_11__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1267 (.A1(registers_27__ap[29]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[29]), .ZN(n_1_0_1205)); + NAND3_X1_LVT i_1_0_1266 (.A1(n_1_0_1207), .A2(n_1_0_1206), .A3(n_1_0_1205), + .ZN(n_1_0_1204)); + SDFF_X1_LVT \registers_reg[3][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_3__ap[29]), .CK(n_0_33), .Q(registers_3__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[2][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_2__ap[29]), .CK(n_0_32), .Q(registers_2__ap[29]), .QN()); + AOI221_X1_LVT i_1_0_1265 (.A(n_1_0_1204), .B1(n_1_0_1257), .B2( + registers_3__ap[29]), .C1(registers_2__ap[29]), .C2(n_1_0_1268), .ZN( + n_1_0_1203)); + NAND3_X1_LVT i_1_0_1264 (.A1(n_1_0_1213), .A2(n_1_0_1208), .A3(n_1_0_1203), + .ZN(RRs1[29])); + AND2_X1_LVT i_0_0_28 (.A1(n_0_0_16), .A2(WRd[28]), .ZN(registers[28])); + SDFF_X1_LVT \registers_reg[15][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_15__ap[28]), .CK(n_0_45), .Q(registers_15__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[26][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_26__ap[28]), .CK(n_0_56), .Q(registers_26__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[22][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_22__ap[28]), .CK(n_0_52), .Q(registers_22__ap[28]), .QN()); + AOI222_X1_LVT i_1_0_1263 (.A1(registers_15__ap[28]), .A2(n_1_0_1286), + .B1(n_1_0_1285), .B2(registers_26__ap[28]), .C1(registers_22__ap[28]), + .C2(n_1_0_1294), .ZN(n_1_0_1202)); + SDFF_X1_LVT \registers_reg[5][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_5__ap[28]), .CK(n_0_35), .Q(registers_5__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[12][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_12__ap[28]), .CK(n_0_42), .Q(registers_12__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1262 (.A1(registers_5__ap[28]), .A2(n_1_0_1273), .B1( + n_1_0_1260), .B2(registers_12__ap[28]), .ZN(n_1_0_1201)); + SDFF_X1_LVT \registers_reg[28][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_28__ap[28]), .CK(n_0_58), .Q(registers_28__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[14][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_14__ap[28]), .CK(n_0_44), .Q(registers_14__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1261 (.A1(registers_28__ap[28]), .A2(n_1_0_1283), .B1( + n_1_0_1258), .B2(registers_14__ap[28]), .ZN(n_1_0_1200)); + SDFF_X1_LVT \registers_reg[17][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_17__ap[28]), .CK(n_0_47), .Q(registers_17__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[2][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_2__ap[28]), .CK(n_0_32), .Q(registers_2__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1260 (.A1(registers_17__ap[28]), .A2(n_1_0_1271), .B1( + n_1_0_1268), .B2(registers_2__ap[28]), .ZN(n_1_0_1199)); + NAND3_X1_LVT i_1_0_1259 (.A1(n_1_0_1201), .A2(n_1_0_1200), .A3(n_1_0_1199), + .ZN(n_1_0_1198)); + SDFF_X1_LVT \registers_reg[9][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_9__ap[28]), .CK(n_0_39), .Q(registers_9__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[29][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_29__ap[28]), .CK(n_0_59), .Q(registers_29__ap[28]), .QN()); + AOI221_X1_LVT i_1_0_1258 (.A(n_1_0_1198), .B1(n_1_0_1291), .B2( + registers_9__ap[28]), .C1(registers_29__ap[28]), .C2(n_1_0_1276), .ZN( + n_1_0_1197)); + SDFF_X1_LVT \registers_reg[13][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_13__ap[28]), .CK(n_0_43), .Q(registers_13__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[25][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_25__ap[28]), .CK(n_0_55), .Q(registers_25__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1257 (.A1(registers_13__ap[28]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[28]), .ZN(n_1_0_1196)); + NAND3_X1_LVT i_1_0_1256 (.A1(n_1_0_1202), .A2(n_1_0_1197), .A3(n_1_0_1196), + .ZN(n_1_0_1195)); + SDFF_X1_LVT \registers_reg[4][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_4__ap[28]), .CK(n_0_34), .Q(registers_4__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[20][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_20__ap[28]), .CK(n_0_50), .Q(registers_20__ap[28]), .QN()); + AOI221_X1_LVT i_1_0_1255 (.A(n_1_0_1195), .B1(n_1_0_1278), .B2( + registers_4__ap[28]), .C1(registers_20__ap[28]), .C2(n_1_0_1281), .ZN( + n_1_0_1194)); + SDFF_X1_LVT \registers_reg[1][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_1__ap[28]), .CK(n_0_0), .Q(registers_1__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[23][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_23__ap[28]), .CK(n_0_53), .Q(registers_23__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1254 (.A1(registers_1__ap[28]), .A2(n_1_0_1274), .B1( + n_1_0_1264), .B2(registers_23__ap[28]), .ZN(n_1_0_1193)); + SDFF_X1_LVT \registers_reg[10][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_10__ap[28]), .CK(n_0_40), .Q(registers_10__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[21][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_21__ap[28]), .CK(n_0_51), .Q(registers_21__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1253 (.A1(registers_10__ap[28]), .A2(n_1_0_1287), .B1( + n_1_0_1259), .B2(registers_21__ap[28]), .ZN(n_1_0_1192)); + SDFF_X1_LVT \registers_reg[6][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_6__ap[28]), .CK(n_0_36), .Q(registers_6__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[30][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_30__ap[28]), .CK(n_0_60), .Q(registers_30__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1252 (.A1(registers_6__ap[28]), .A2(n_1_0_1300), .B1( + n_1_0_1272), .B2(registers_30__ap[28]), .ZN(n_1_0_1191)); + NAND3_X1_LVT i_1_0_1251 (.A1(n_1_0_1193), .A2(n_1_0_1192), .A3(n_1_0_1191), + .ZN(n_1_0_1190)); + SDFF_X1_LVT \registers_reg[8][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_8__ap[28]), .CK(n_0_38), .Q(registers_8__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[24][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_24__ap[28]), .CK(n_0_54), .Q(registers_24__ap[28]), .QN()); + AOI221_X1_LVT i_1_0_1250 (.A(n_1_0_1190), .B1(n_1_0_1282), .B2( + registers_8__ap[28]), .C1(registers_24__ap[28]), .C2(n_1_0_1289), .ZN( + n_1_0_1189)); + SDFF_X1_LVT \registers_reg[16][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_16__ap[28]), .CK(n_0_46), .Q(registers_16__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[3][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_3__ap[28]), .CK(n_0_33), .Q(registers_3__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1249 (.A1(registers_16__ap[28]), .A2(n_1_0_1267), .B1( + n_1_0_1257), .B2(registers_3__ap[28]), .ZN(n_1_0_1188)); + SDFF_X1_LVT \registers_reg[11][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_11__ap[28]), .CK(n_0_41), .Q(registers_11__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[31][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_31__ap[28]), .CK(n_0_61), .Q(registers_31__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1248 (.A1(registers_11__ap[28]), .A2(n_1_0_1270), .B1( + n_1_0_1266), .B2(registers_31__ap[28]), .ZN(n_1_0_1187)); + SDFF_X1_LVT \registers_reg[27][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_27__ap[28]), .CK(n_0_57), .Q(registers_27__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[7][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_7__ap[28]), .CK(n_0_37), .Q(registers_7__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1247 (.A1(registers_27__ap[28]), .A2(n_1_0_1279), .B1( + n_1_0_1263), .B2(registers_7__ap[28]), .ZN(n_1_0_1186)); + NAND3_X1_LVT i_1_0_1246 (.A1(n_1_0_1188), .A2(n_1_0_1187), .A3(n_1_0_1186), + .ZN(n_1_0_1185)); + SDFF_X1_LVT \registers_reg[19][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_19__ap[28]), .CK(n_0_49), .Q(registers_19__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[18][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_18__ap[28]), .CK(n_0_48), .Q(registers_18__ap[28]), .QN()); + AOI221_X1_LVT i_1_0_1245 (.A(n_1_0_1185), .B1(n_1_0_1295), .B2( + registers_19__ap[28]), .C1(registers_18__ap[28]), .C2(n_1_0_1297), + .ZN(n_1_0_1184)); + NAND3_X1_LVT i_1_0_1244 (.A1(n_1_0_1194), .A2(n_1_0_1189), .A3(n_1_0_1184), + .ZN(RRs1[28])); + AND2_X1_LVT i_0_0_27 (.A1(n_0_0_16), .A2(WRd[27]), .ZN(registers[27])); + SDFF_X1_LVT \registers_reg[29][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_29__ap[27]), .CK(n_0_59), .Q(registers_29__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[2][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_2__ap[27]), .CK(n_0_32), .Q(registers_2__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1242 (.A1(registers_29__ap[27]), .A2(n_1_0_1276), .B1( + n_1_0_1268), .B2(registers_2__ap[27]), .ZN(n_1_0_1182)); + SDFF_X1_LVT \registers_reg[8][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_8__ap[27]), .CK(n_0_38), .Q(registers_8__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[25][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_25__ap[27]), .CK(n_0_55), .Q(registers_25__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1243 (.A1(registers_8__ap[27]), .A2(n_1_0_1282), .B1( + n_1_0_1269), .B2(registers_25__ap[27]), .ZN(n_1_0_1183)); + SDFF_X1_LVT \registers_reg[9][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_9__ap[27]), .CK(n_0_39), .Q(registers_9__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[7][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_7__ap[27]), .CK(n_0_37), .Q(registers_7__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1241 (.A1(registers_9__ap[27]), .A2(n_1_0_1291), .B1( + n_1_0_1263), .B2(registers_7__ap[27]), .ZN(n_1_0_1181)); + SDFF_X1_LVT \registers_reg[11][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_11__ap[27]), .CK(n_0_41), .Q(registers_11__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[16][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_16__ap[27]), .CK(n_0_46), .Q(registers_16__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1240 (.A1(registers_11__ap[27]), .A2(n_1_0_1270), .B1( + n_1_0_1267), .B2(registers_16__ap[27]), .ZN(n_1_0_1180)); + NAND3_X1_LVT i_1_0_1239 (.A1(n_1_0_1183), .A2(n_1_0_1181), .A3(n_1_0_1180), + .ZN(n_1_0_1179)); + SDFF_X1_LVT \registers_reg[10][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_10__ap[27]), .CK(n_0_40), .Q(registers_10__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[6][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_6__ap[27]), .CK(n_0_36), .Q(registers_6__ap[27]), .QN()); + AOI221_X1_LVT i_1_0_1238 (.A(n_1_0_1179), .B1(n_1_0_1287), .B2( + registers_10__ap[27]), .C1(registers_6__ap[27]), .C2(n_1_0_1300), .ZN( + n_1_0_1178)); + SDFF_X1_LVT \registers_reg[1][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_1__ap[27]), .CK(n_0_0), .Q(registers_1__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[30][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_30__ap[27]), .CK(n_0_60), .Q(registers_30__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[22][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_22__ap[27]), .CK(n_0_52), .Q(registers_22__ap[27]), .QN()); + AOI222_X1_LVT i_1_0_1237 (.A1(registers_1__ap[27]), .A2(n_1_0_1274), .B1( + n_1_0_1272), .B2(registers_30__ap[27]), .C1(registers_22__ap[27]), + .C2(n_1_0_1294), .ZN(n_1_0_1177)); + NAND3_X1_LVT i_1_0_1236 (.A1(n_1_0_1182), .A2(n_1_0_1178), .A3(n_1_0_1177), + .ZN(n_1_0_1176)); + SDFF_X1_LVT \registers_reg[5][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_5__ap[27]), .CK(n_0_35), .Q(registers_5__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[28][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_28__ap[27]), .CK(n_0_58), .Q(registers_28__ap[27]), .QN()); + AOI221_X1_LVT i_1_0_1235 (.A(n_1_0_1176), .B1(n_1_0_1273), .B2( + registers_5__ap[27]), .C1(registers_28__ap[27]), .C2(n_1_0_1283), .ZN( + n_1_0_1175)); + SDFF_X1_LVT \registers_reg[4][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_4__ap[27]), .CK(n_0_34), .Q(registers_4__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[12][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_12__ap[27]), .CK(n_0_42), .Q(registers_12__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1234 (.A1(registers_4__ap[27]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[27]), .ZN(n_1_0_1174)); + SDFF_X1_LVT \registers_reg[19][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_19__ap[27]), .CK(n_0_49), .Q(registers_19__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[21][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_21__ap[27]), .CK(n_0_51), .Q(registers_21__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1233 (.A1(registers_19__ap[27]), .A2(n_1_0_1295), .B1( + n_1_0_1259), .B2(registers_21__ap[27]), .ZN(n_1_0_1173)); + SDFF_X1_LVT \registers_reg[24][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_24__ap[27]), .CK(n_0_54), .Q(registers_24__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[20][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_20__ap[27]), .CK(n_0_50), .Q(registers_20__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1232 (.A1(registers_24__ap[27]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[27]), .ZN(n_1_0_1172)); + NAND3_X1_LVT i_1_0_1231 (.A1(n_1_0_1174), .A2(n_1_0_1173), .A3(n_1_0_1172), + .ZN(n_1_0_1171)); + SDFF_X1_LVT \registers_reg[18][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_18__ap[27]), .CK(n_0_48), .Q(registers_18__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[26][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_26__ap[27]), .CK(n_0_56), .Q(registers_26__ap[27]), .QN()); + AOI221_X1_LVT i_1_0_1230 (.A(n_1_0_1171), .B1(n_1_0_1297), .B2( + registers_18__ap[27]), .C1(registers_26__ap[27]), .C2(n_1_0_1285), + .ZN(n_1_0_1170)); + SDFF_X1_LVT \registers_reg[23][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_23__ap[27]), .CK(n_0_53), .Q(registers_23__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[3][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_3__ap[27]), .CK(n_0_33), .Q(registers_3__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1229 (.A1(registers_23__ap[27]), .A2(n_1_0_1264), .B1( + n_1_0_1257), .B2(registers_3__ap[27]), .ZN(n_1_0_1169)); + SDFF_X1_LVT \registers_reg[13][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_13__ap[27]), .CK(n_0_43), .Q(registers_13__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[17][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_17__ap[27]), .CK(n_0_47), .Q(registers_17__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1228 (.A1(registers_13__ap[27]), .A2(n_1_0_1277), .B1( + n_1_0_1271), .B2(registers_17__ap[27]), .ZN(n_1_0_1168)); + SDFF_X1_LVT \registers_reg[15][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_15__ap[27]), .CK(n_0_45), .Q(registers_15__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[14][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_14__ap[27]), .CK(n_0_44), .Q(registers_14__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1227 (.A1(registers_15__ap[27]), .A2(n_1_0_1286), .B1( + n_1_0_1258), .B2(registers_14__ap[27]), .ZN(n_1_0_1167)); + NAND3_X1_LVT i_1_0_1226 (.A1(n_1_0_1169), .A2(n_1_0_1168), .A3(n_1_0_1167), + .ZN(n_1_0_1166)); + SDFF_X1_LVT \registers_reg[27][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_27__ap[27]), .CK(n_0_57), .Q(registers_27__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[31][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_31__ap[27]), .CK(n_0_61), .Q(registers_31__ap[27]), .QN()); + AOI221_X1_LVT i_1_0_1225 (.A(n_1_0_1166), .B1(n_1_0_1279), .B2( + registers_27__ap[27]), .C1(registers_31__ap[27]), .C2(n_1_0_1266), + .ZN(n_1_0_1165)); + NAND3_X1_LVT i_1_0_1224 (.A1(n_1_0_1175), .A2(n_1_0_1170), .A3(n_1_0_1165), + .ZN(RRs1[27])); + AND2_X1_LVT i_0_0_26 (.A1(n_0_0_16), .A2(WRd[26]), .ZN(registers[26])); + SDFF_X1_LVT \registers_reg[18][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_18__ap[26]), .CK(n_0_48), .Q(registers_18__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[22][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_22__ap[26]), .CK(n_0_52), .Q(registers_22__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[1][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_1__ap[26]), .CK(n_0_0), .Q(registers_1__ap[26]), .QN()); + AOI222_X1_LVT i_1_0_1223 (.A1(registers_18__ap[26]), .A2(n_1_0_1297), + .B1(n_1_0_1294), .B2(registers_22__ap[26]), .C1(registers_1__ap[26]), + .C2(n_1_0_1274), .ZN(n_1_0_1164)); + SDFF_X1_LVT \registers_reg[29][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_29__ap[26]), .CK(n_0_59), .Q(registers_29__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[2][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_2__ap[26]), .CK(n_0_32), .Q(registers_2__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1222 (.A1(registers_29__ap[26]), .A2(n_1_0_1276), .B1( + n_1_0_1268), .B2(registers_2__ap[26]), .ZN(n_1_0_1163)); + SDFF_X1_LVT \registers_reg[9][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_9__ap[26]), .CK(n_0_39), .Q(registers_9__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[7][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_7__ap[26]), .CK(n_0_37), .Q(registers_7__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1221 (.A1(registers_9__ap[26]), .A2(n_1_0_1291), .B1( + n_1_0_1263), .B2(registers_7__ap[26]), .ZN(n_1_0_1162)); + SDFF_X1_LVT \registers_reg[11][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_11__ap[26]), .CK(n_0_41), .Q(registers_11__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[25][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_25__ap[26]), .CK(n_0_55), .Q(registers_25__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1220 (.A1(registers_11__ap[26]), .A2(n_1_0_1270), .B1( + n_1_0_1269), .B2(registers_25__ap[26]), .ZN(n_1_0_1161)); + SDFF_X1_LVT \registers_reg[27][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_27__ap[26]), .CK(n_0_57), .Q(registers_27__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[16][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_16__ap[26]), .CK(n_0_46), .Q(registers_16__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1219 (.A1(registers_27__ap[26]), .A2(n_1_0_1279), .B1( + n_1_0_1267), .B2(registers_16__ap[26]), .ZN(n_1_0_1160)); + NAND3_X1_LVT i_1_0_1218 (.A1(n_1_0_1162), .A2(n_1_0_1161), .A3(n_1_0_1160), + .ZN(n_1_0_1159)); + SDFF_X1_LVT \registers_reg[31][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_31__ap[26]), .CK(n_0_61), .Q(registers_31__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[6][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_6__ap[26]), .CK(n_0_36), .Q(registers_6__ap[26]), .QN()); + AOI221_X1_LVT i_1_0_1217 (.A(n_1_0_1159), .B1(n_1_0_1266), .B2( + registers_31__ap[26]), .C1(registers_6__ap[26]), .C2(n_1_0_1300), .ZN( + n_1_0_1158)); + NAND3_X1_LVT i_1_0_1216 (.A1(n_1_0_1164), .A2(n_1_0_1163), .A3(n_1_0_1158), + .ZN(n_1_0_1157)); + SDFF_X1_LVT \registers_reg[5][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_5__ap[26]), .CK(n_0_35), .Q(registers_5__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[28][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_28__ap[26]), .CK(n_0_58), .Q(registers_28__ap[26]), .QN()); + AOI221_X1_LVT i_1_0_1215 (.A(n_1_0_1157), .B1(n_1_0_1273), .B2( + registers_5__ap[26]), .C1(registers_28__ap[26]), .C2(n_1_0_1283), .ZN( + n_1_0_1156)); + SDFF_X1_LVT \registers_reg[4][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_4__ap[26]), .CK(n_0_34), .Q(registers_4__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[12][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_12__ap[26]), .CK(n_0_42), .Q(registers_12__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1214 (.A1(registers_4__ap[26]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[26]), .ZN(n_1_0_1155)); + SDFF_X1_LVT \registers_reg[19][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_19__ap[26]), .CK(n_0_49), .Q(registers_19__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[21][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_21__ap[26]), .CK(n_0_51), .Q(registers_21__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1213 (.A1(registers_19__ap[26]), .A2(n_1_0_1295), .B1( + n_1_0_1259), .B2(registers_21__ap[26]), .ZN(n_1_0_1154)); + SDFF_X1_LVT \registers_reg[24][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_24__ap[26]), .CK(n_0_54), .Q(registers_24__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[20][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_20__ap[26]), .CK(n_0_50), .Q(registers_20__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1212 (.A1(registers_24__ap[26]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[26]), .ZN(n_1_0_1153)); + NAND3_X1_LVT i_1_0_1211 (.A1(n_1_0_1155), .A2(n_1_0_1154), .A3(n_1_0_1153), + .ZN(n_1_0_1152)); + SDFF_X1_LVT \registers_reg[26][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_26__ap[26]), .CK(n_0_56), .Q(registers_26__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[30][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_30__ap[26]), .CK(n_0_60), .Q(registers_30__ap[26]), .QN()); + AOI221_X1_LVT i_1_0_1210 (.A(n_1_0_1152), .B1(n_1_0_1285), .B2( + registers_26__ap[26]), .C1(registers_30__ap[26]), .C2(n_1_0_1272), + .ZN(n_1_0_1151)); + SDFF_X1_LVT \registers_reg[8][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_8__ap[26]), .CK(n_0_38), .Q(registers_8__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[23][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_23__ap[26]), .CK(n_0_53), .Q(registers_23__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1209 (.A1(registers_8__ap[26]), .A2(n_1_0_1282), .B1( + n_1_0_1264), .B2(registers_23__ap[26]), .ZN(n_1_0_1150)); + SDFF_X1_LVT \registers_reg[13][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_13__ap[26]), .CK(n_0_43), .Q(registers_13__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[17][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_17__ap[26]), .CK(n_0_47), .Q(registers_17__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1208 (.A1(registers_13__ap[26]), .A2(n_1_0_1277), .B1( + n_1_0_1271), .B2(registers_17__ap[26]), .ZN(n_1_0_1149)); + SDFF_X1_LVT \registers_reg[15][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_15__ap[26]), .CK(n_0_45), .Q(registers_15__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[14][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_14__ap[26]), .CK(n_0_44), .Q(registers_14__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1207 (.A1(registers_15__ap[26]), .A2(n_1_0_1286), .B1( + n_1_0_1258), .B2(registers_14__ap[26]), .ZN(n_1_0_1148)); + NAND3_X1_LVT i_1_0_1206 (.A1(n_1_0_1150), .A2(n_1_0_1149), .A3(n_1_0_1148), + .ZN(n_1_0_1147)); + SDFF_X1_LVT \registers_reg[10][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_10__ap[26]), .CK(n_0_40), .Q(registers_10__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[3][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_3__ap[26]), .CK(n_0_33), .Q(registers_3__ap[26]), .QN()); + AOI221_X1_LVT i_1_0_1205 (.A(n_1_0_1147), .B1(n_1_0_1287), .B2( + registers_10__ap[26]), .C1(registers_3__ap[26]), .C2(n_1_0_1257), .ZN( + n_1_0_1146)); + NAND3_X1_LVT i_1_0_1204 (.A1(n_1_0_1156), .A2(n_1_0_1151), .A3(n_1_0_1146), + .ZN(RRs1[26])); + AND2_X1_LVT i_0_0_25 (.A1(n_0_0_16), .A2(WRd[25]), .ZN(registers[25])); + SDFF_X1_LVT \registers_reg[17][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_17__ap[25]), .CK(n_0_47), .Q(registers_17__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[21][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_21__ap[25]), .CK(n_0_51), .Q(registers_21__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1202 (.A1(registers_17__ap[25]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[25]), .ZN(n_1_0_1144)); + SDFF_X1_LVT \registers_reg[6][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_6__ap[25]), .CK(n_0_36), .Q(registers_6__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[8][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_8__ap[25]), .CK(n_0_38), .Q(registers_8__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1203 (.A1(registers_6__ap[25]), .A2(n_1_0_1300), .B1( + n_1_0_1282), .B2(registers_8__ap[25]), .ZN(n_1_0_1145)); + SDFF_X1_LVT \registers_reg[20][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_20__ap[25]), .CK(n_0_50), .Q(registers_20__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[12][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_12__ap[25]), .CK(n_0_42), .Q(registers_12__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1201 (.A1(registers_20__ap[25]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[25]), .ZN(n_1_0_1143)); + SDFF_X1_LVT \registers_reg[5][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_5__ap[25]), .CK(n_0_35), .Q(registers_5__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[11][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_11__ap[25]), .CK(n_0_41), .Q(registers_11__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1200 (.A1(registers_5__ap[25]), .A2(n_1_0_1273), .B1( + n_1_0_1270), .B2(registers_11__ap[25]), .ZN(n_1_0_1142)); + NAND3_X1_LVT i_1_0_1199 (.A1(n_1_0_1145), .A2(n_1_0_1143), .A3(n_1_0_1142), + .ZN(n_1_0_1141)); + SDFF_X1_LVT \registers_reg[10][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_10__ap[25]), .CK(n_0_40), .Q(registers_10__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[2][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_2__ap[25]), .CK(n_0_32), .Q(registers_2__ap[25]), .QN()); + AOI221_X1_LVT i_1_0_1198 (.A(n_1_0_1141), .B1(n_1_0_1287), .B2( + registers_10__ap[25]), .C1(registers_2__ap[25]), .C2(n_1_0_1268), .ZN( + n_1_0_1140)); + SDFF_X1_LVT \registers_reg[13][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_13__ap[25]), .CK(n_0_43), .Q(registers_13__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[30][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_30__ap[25]), .CK(n_0_60), .Q(registers_30__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[22][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_22__ap[25]), .CK(n_0_52), .Q(registers_22__ap[25]), .QN()); + AOI222_X1_LVT i_1_0_1197 (.A1(registers_13__ap[25]), .A2(n_1_0_1277), + .B1(n_1_0_1272), .B2(registers_30__ap[25]), .C1(registers_22__ap[25]), + .C2(n_1_0_1294), .ZN(n_1_0_1139)); + NAND2_X1_LVT i_1_0_1196 (.A1(n_1_0_1140), .A2(n_1_0_1139), .ZN(n_1_0_1138)); + SDFF_X1_LVT \registers_reg[1][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_1__ap[25]), .CK(n_0_0), .Q(registers_1__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[28][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_28__ap[25]), .CK(n_0_58), .Q(registers_28__ap[25]), .QN()); + AOI221_X1_LVT i_1_0_1195 (.A(n_1_0_1138), .B1(n_1_0_1274), .B2( + registers_1__ap[25]), .C1(registers_28__ap[25]), .C2(n_1_0_1283), .ZN( + n_1_0_1137)); + SDFF_X1_LVT \registers_reg[18][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_18__ap[25]), .CK(n_0_48), .Q(registers_18__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[26][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_26__ap[25]), .CK(n_0_56), .Q(registers_26__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1194 (.A1(registers_18__ap[25]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[25]), .ZN(n_1_0_1136)); + SDFF_X1_LVT \registers_reg[24][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_24__ap[25]), .CK(n_0_54), .Q(registers_24__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[4][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_4__ap[25]), .CK(n_0_34), .Q(registers_4__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1193 (.A1(registers_24__ap[25]), .A2(n_1_0_1289), .B1( + n_1_0_1278), .B2(registers_4__ap[25]), .ZN(n_1_0_1135)); + SDFF_X1_LVT \registers_reg[15][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_15__ap[25]), .CK(n_0_45), .Q(registers_15__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[16][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_16__ap[25]), .CK(n_0_46), .Q(registers_16__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1192 (.A1(registers_15__ap[25]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[25]), .ZN(n_1_0_1134)); + NAND3_X1_LVT i_1_0_1191 (.A1(n_1_0_1136), .A2(n_1_0_1135), .A3(n_1_0_1134), + .ZN(n_1_0_1133)); + SDFF_X1_LVT \registers_reg[19][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_19__ap[25]), .CK(n_0_49), .Q(registers_19__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[25][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_25__ap[25]), .CK(n_0_55), .Q(registers_25__ap[25]), .QN()); + AOI221_X1_LVT i_1_0_1190 (.A(n_1_0_1133), .B1(n_1_0_1295), .B2( + registers_19__ap[25]), .C1(registers_25__ap[25]), .C2(n_1_0_1269), + .ZN(n_1_0_1132)); + SDFF_X1_LVT \registers_reg[7][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_7__ap[25]), .CK(n_0_37), .Q(registers_7__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[14][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_14__ap[25]), .CK(n_0_44), .Q(registers_14__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1189 (.A1(registers_7__ap[25]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[25]), .ZN(n_1_0_1131)); + SDFF_X1_LVT \registers_reg[9][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_9__ap[25]), .CK(n_0_39), .Q(registers_9__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[29][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_29__ap[25]), .CK(n_0_59), .Q(registers_29__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1188 (.A1(registers_9__ap[25]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[25]), .ZN(n_1_0_1130)); + SDFF_X1_LVT \registers_reg[23][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_23__ap[25]), .CK(n_0_53), .Q(registers_23__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[3][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_3__ap[25]), .CK(n_0_33), .Q(registers_3__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1187 (.A1(registers_23__ap[25]), .A2(n_1_0_1264), .B1( + n_1_0_1257), .B2(registers_3__ap[25]), .ZN(n_1_0_1129)); + NAND3_X1_LVT i_1_0_1186 (.A1(n_1_0_1131), .A2(n_1_0_1130), .A3(n_1_0_1129), + .ZN(n_1_0_1128)); + SDFF_X1_LVT \registers_reg[27][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_27__ap[25]), .CK(n_0_57), .Q(registers_27__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[31][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_31__ap[25]), .CK(n_0_61), .Q(registers_31__ap[25]), .QN()); + AOI221_X1_LVT i_1_0_1185 (.A(n_1_0_1128), .B1(n_1_0_1279), .B2( + registers_27__ap[25]), .C1(registers_31__ap[25]), .C2(n_1_0_1266), + .ZN(n_1_0_1127)); + NAND4_X1_LVT i_1_0_1184 (.A1(n_1_0_1144), .A2(n_1_0_1137), .A3(n_1_0_1132), + .A4(n_1_0_1127), .ZN(RRs1[25])); + AND2_X1_LVT i_0_0_24 (.A1(n_0_0_16), .A2(WRd[24]), .ZN(registers[24])); + SDFF_X1_LVT \registers_reg[17][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_17__ap[24]), .CK(n_0_47), .Q(registers_17__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[21][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_21__ap[24]), .CK(n_0_51), .Q(registers_21__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1182 (.A1(registers_17__ap[24]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[24]), .ZN(n_1_0_1125)); + SDFF_X1_LVT \registers_reg[6][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_6__ap[24]), .CK(n_0_36), .Q(registers_6__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[8][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_8__ap[24]), .CK(n_0_38), .Q(registers_8__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1183 (.A1(registers_6__ap[24]), .A2(n_1_0_1300), .B1( + n_1_0_1282), .B2(registers_8__ap[24]), .ZN(n_1_0_1126)); + SDFF_X1_LVT \registers_reg[20][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_20__ap[24]), .CK(n_0_50), .Q(registers_20__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[12][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_12__ap[24]), .CK(n_0_42), .Q(registers_12__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1181 (.A1(registers_20__ap[24]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[24]), .ZN(n_1_0_1124)); + SDFF_X1_LVT \registers_reg[5][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_5__ap[24]), .CK(n_0_35), .Q(registers_5__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[11][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_11__ap[24]), .CK(n_0_41), .Q(registers_11__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1180 (.A1(registers_5__ap[24]), .A2(n_1_0_1273), .B1( + n_1_0_1270), .B2(registers_11__ap[24]), .ZN(n_1_0_1123)); + NAND3_X1_LVT i_1_0_1179 (.A1(n_1_0_1126), .A2(n_1_0_1124), .A3(n_1_0_1123), + .ZN(n_1_0_1122)); + SDFF_X1_LVT \registers_reg[10][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_10__ap[24]), .CK(n_0_40), .Q(registers_10__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[2][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_2__ap[24]), .CK(n_0_32), .Q(registers_2__ap[24]), .QN()); + AOI221_X1_LVT i_1_0_1178 (.A(n_1_0_1122), .B1(n_1_0_1287), .B2( + registers_10__ap[24]), .C1(registers_2__ap[24]), .C2(n_1_0_1268), .ZN( + n_1_0_1121)); + SDFF_X1_LVT \registers_reg[13][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_13__ap[24]), .CK(n_0_43), .Q(registers_13__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[30][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_30__ap[24]), .CK(n_0_60), .Q(registers_30__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[22][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_22__ap[24]), .CK(n_0_52), .Q(registers_22__ap[24]), .QN()); + AOI222_X1_LVT i_1_0_1177 (.A1(registers_13__ap[24]), .A2(n_1_0_1277), + .B1(n_1_0_1272), .B2(registers_30__ap[24]), .C1(registers_22__ap[24]), + .C2(n_1_0_1294), .ZN(n_1_0_1120)); + NAND2_X1_LVT i_1_0_1176 (.A1(n_1_0_1121), .A2(n_1_0_1120), .ZN(n_1_0_1119)); + SDFF_X1_LVT \registers_reg[1][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_1__ap[24]), .CK(n_0_0), .Q(registers_1__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[28][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_28__ap[24]), .CK(n_0_58), .Q(registers_28__ap[24]), .QN()); + AOI221_X1_LVT i_1_0_1175 (.A(n_1_0_1119), .B1(n_1_0_1274), .B2( + registers_1__ap[24]), .C1(registers_28__ap[24]), .C2(n_1_0_1283), .ZN( + n_1_0_1118)); + SDFF_X1_LVT \registers_reg[18][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_18__ap[24]), .CK(n_0_48), .Q(registers_18__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[26][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_26__ap[24]), .CK(n_0_56), .Q(registers_26__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1174 (.A1(registers_18__ap[24]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[24]), .ZN(n_1_0_1117)); + SDFF_X1_LVT \registers_reg[24][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_24__ap[24]), .CK(n_0_54), .Q(registers_24__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[4][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_4__ap[24]), .CK(n_0_34), .Q(registers_4__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1173 (.A1(registers_24__ap[24]), .A2(n_1_0_1289), .B1( + n_1_0_1278), .B2(registers_4__ap[24]), .ZN(n_1_0_1116)); + SDFF_X1_LVT \registers_reg[15][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_15__ap[24]), .CK(n_0_45), .Q(registers_15__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[25][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_25__ap[24]), .CK(n_0_55), .Q(registers_25__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1172 (.A1(registers_15__ap[24]), .A2(n_1_0_1286), .B1( + n_1_0_1269), .B2(registers_25__ap[24]), .ZN(n_1_0_1115)); + NAND3_X1_LVT i_1_0_1171 (.A1(n_1_0_1117), .A2(n_1_0_1116), .A3(n_1_0_1115), + .ZN(n_1_0_1114)); + SDFF_X1_LVT \registers_reg[19][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_19__ap[24]), .CK(n_0_49), .Q(registers_19__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[16][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_16__ap[24]), .CK(n_0_46), .Q(registers_16__ap[24]), .QN()); + AOI221_X1_LVT i_1_0_1170 (.A(n_1_0_1114), .B1(n_1_0_1295), .B2( + registers_19__ap[24]), .C1(registers_16__ap[24]), .C2(n_1_0_1267), + .ZN(n_1_0_1113)); + SDFF_X1_LVT \registers_reg[7][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_7__ap[24]), .CK(n_0_37), .Q(registers_7__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[14][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_14__ap[24]), .CK(n_0_44), .Q(registers_14__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1169 (.A1(registers_7__ap[24]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[24]), .ZN(n_1_0_1112)); + SDFF_X1_LVT \registers_reg[9][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_9__ap[24]), .CK(n_0_39), .Q(registers_9__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[29][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_29__ap[24]), .CK(n_0_59), .Q(registers_29__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1168 (.A1(registers_9__ap[24]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[24]), .ZN(n_1_0_1111)); + SDFF_X1_LVT \registers_reg[23][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_23__ap[24]), .CK(n_0_53), .Q(registers_23__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[3][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_3__ap[24]), .CK(n_0_33), .Q(registers_3__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1167 (.A1(registers_23__ap[24]), .A2(n_1_0_1264), .B1( + n_1_0_1257), .B2(registers_3__ap[24]), .ZN(n_1_0_1110)); + NAND3_X1_LVT i_1_0_1166 (.A1(n_1_0_1112), .A2(n_1_0_1111), .A3(n_1_0_1110), + .ZN(n_1_0_1109)); + SDFF_X1_LVT \registers_reg[27][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_27__ap[24]), .CK(n_0_57), .Q(registers_27__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[31][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_31__ap[24]), .CK(n_0_61), .Q(registers_31__ap[24]), .QN()); + AOI221_X1_LVT i_1_0_1165 (.A(n_1_0_1109), .B1(n_1_0_1279), .B2( + registers_27__ap[24]), .C1(registers_31__ap[24]), .C2(n_1_0_1266), + .ZN(n_1_0_1108)); + NAND4_X1_LVT i_1_0_1164 (.A1(n_1_0_1125), .A2(n_1_0_1118), .A3(n_1_0_1113), + .A4(n_1_0_1108), .ZN(RRs1[24])); + AND2_X1_LVT i_0_0_23 (.A1(n_0_0_16), .A2(WRd[23]), .ZN(registers[23])); + SDFF_X1_LVT \registers_reg[9][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_9__ap[23]), .CK(n_0_39), .Q(registers_9__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[28][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_28__ap[23]), .CK(n_0_58), .Q(registers_28__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1163 (.A1(registers_9__ap[23]), .A2(n_1_0_1291), .B1( + n_1_0_1283), .B2(registers_28__ap[23]), .ZN(n_1_0_1107)); + SDFF_X1_LVT \registers_reg[18][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_18__ap[23]), .CK(n_0_48), .Q(registers_18__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[22][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_22__ap[23]), .CK(n_0_52), .Q(registers_22__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1160 (.A1(registers_18__ap[23]), .A2(n_1_0_1297), .B1( + n_1_0_1294), .B2(registers_22__ap[23]), .ZN(n_1_0_1104)); + SDFF_X1_LVT \registers_reg[1][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_1__ap[23]), .CK(n_0_0), .Q(registers_1__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[21][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_21__ap[23]), .CK(n_0_51), .Q(registers_21__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1159 (.A1(registers_1__ap[23]), .A2(n_1_0_1274), .B1( + n_1_0_1259), .B2(registers_21__ap[23]), .ZN(n_1_0_1103)); + NAND3_X1_LVT i_1_0_1157 (.A1(n_1_0_1107), .A2(n_1_0_1104), .A3(n_1_0_1103), + .ZN(n_1_0_1101)); + SDFF_X1_LVT \registers_reg[20][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_20__ap[23]), .CK(n_0_50), .Q(registers_20__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[19][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_19__ap[23]), .CK(n_0_49), .Q(registers_19__ap[23]), .QN()); + AOI221_X1_LVT i_1_0_1156 (.A(n_1_0_1101), .B1(n_1_0_1281), .B2( + registers_20__ap[23]), .C1(registers_19__ap[23]), .C2(n_1_0_1295), + .ZN(n_1_0_1100)); + SDFF_X1_LVT \registers_reg[26][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_26__ap[23]), .CK(n_0_56), .Q(registers_26__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[23][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_23__ap[23]), .CK(n_0_53), .Q(registers_23__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1162 (.A1(registers_26__ap[23]), .A2(n_1_0_1285), .B1( + n_1_0_1264), .B2(registers_23__ap[23]), .ZN(n_1_0_1106)); + SDFF_X1_LVT \registers_reg[29][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_29__ap[23]), .CK(n_0_59), .Q(registers_29__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[3][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_3__ap[23]), .CK(n_0_33), .Q(registers_3__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1161 (.A1(registers_29__ap[23]), .A2(n_1_0_1276), .B1( + n_1_0_1257), .B2(registers_3__ap[23]), .ZN(n_1_0_1105)); + SDFF_X1_LVT \registers_reg[30][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_30__ap[23]), .CK(n_0_60), .Q(registers_30__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[31][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_31__ap[23]), .CK(n_0_61), .Q(registers_31__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1158 (.A1(registers_30__ap[23]), .A2(n_1_0_1272), .B1( + n_1_0_1266), .B2(registers_31__ap[23]), .ZN(n_1_0_1102)); + NAND3_X1_LVT i_1_0_1155 (.A1(n_1_0_1106), .A2(n_1_0_1105), .A3(n_1_0_1102), + .ZN(n_1_0_1099)); + SDFF_X1_LVT \registers_reg[8][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_8__ap[23]), .CK(n_0_38), .Q(registers_8__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[17][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_17__ap[23]), .CK(n_0_47), .Q(registers_17__ap[23]), .QN()); + AOI221_X1_LVT i_1_0_1154 (.A(n_1_0_1099), .B1(n_1_0_1282), .B2( + registers_8__ap[23]), .C1(registers_17__ap[23]), .C2(n_1_0_1271), .ZN( + n_1_0_1098)); + SDFF_X1_LVT \registers_reg[24][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_24__ap[23]), .CK(n_0_54), .Q(registers_24__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[15][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_15__ap[23]), .CK(n_0_45), .Q(registers_15__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[14][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_14__ap[23]), .CK(n_0_44), .Q(registers_14__ap[23]), .QN()); + AOI222_X1_LVT i_1_0_1153 (.A1(registers_24__ap[23]), .A2(n_1_0_1289), + .B1(n_1_0_1286), .B2(registers_15__ap[23]), .C1(n_1_0_1258), .C2( + registers_14__ap[23]), .ZN(n_1_0_1097)); + SDFF_X1_LVT \registers_reg[16][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_16__ap[23]), .CK(n_0_46), .Q(registers_16__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[7][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_7__ap[23]), .CK(n_0_37), .Q(registers_7__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1152 (.A1(registers_16__ap[23]), .A2(n_1_0_1267), .B1( + n_1_0_1263), .B2(registers_7__ap[23]), .ZN(n_1_0_1096)); + SDFF_X1_LVT \registers_reg[6][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_6__ap[23]), .CK(n_0_36), .Q(registers_6__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[25][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_25__ap[23]), .CK(n_0_55), .Q(registers_25__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1151 (.A1(registers_6__ap[23]), .A2(n_1_0_1300), .B1( + n_1_0_1269), .B2(registers_25__ap[23]), .ZN(n_1_0_1095)); + SDFF_X1_LVT \registers_reg[27][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_27__ap[23]), .CK(n_0_57), .Q(registers_27__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[11][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_11__ap[23]), .CK(n_0_41), .Q(registers_11__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1150 (.A1(registers_27__ap[23]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[23]), .ZN(n_1_0_1094)); + SDFF_X1_LVT \registers_reg[13][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_13__ap[23]), .CK(n_0_43), .Q(registers_13__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[5][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_5__ap[23]), .CK(n_0_35), .Q(registers_5__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1149 (.A1(registers_13__ap[23]), .A2(n_1_0_1277), .B1( + n_1_0_1273), .B2(registers_5__ap[23]), .ZN(n_1_0_1093)); + SDFF_X1_LVT \registers_reg[4][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_4__ap[23]), .CK(n_0_34), .Q(registers_4__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[12][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_12__ap[23]), .CK(n_0_42), .Q(registers_12__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1148 (.A1(registers_4__ap[23]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[23]), .ZN(n_1_0_1092)); + NAND3_X1_LVT i_1_0_1147 (.A1(n_1_0_1094), .A2(n_1_0_1093), .A3(n_1_0_1092), + .ZN(n_1_0_1091)); + SDFF_X1_LVT \registers_reg[2][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_2__ap[23]), .CK(n_0_32), .Q(registers_2__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[10][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_10__ap[23]), .CK(n_0_40), .Q(registers_10__ap[23]), .QN()); + AOI221_X1_LVT i_1_0_1146 (.A(n_1_0_1091), .B1(n_1_0_1268), .B2( + registers_2__ap[23]), .C1(registers_10__ap[23]), .C2(n_1_0_1287), .ZN( + n_1_0_1090)); + AND4_X1_LVT i_1_0_1145 (.A1(n_1_0_1097), .A2(n_1_0_1096), .A3(n_1_0_1095), + .A4(n_1_0_1090), .ZN(n_1_0_1089)); + NAND3_X1_LVT i_1_0_1144 (.A1(n_1_0_1100), .A2(n_1_0_1098), .A3(n_1_0_1089), + .ZN(RRs1[23])); + AND2_X1_LVT i_0_0_22 (.A1(n_0_0_16), .A2(WRd[22]), .ZN(registers[22])); + SDFF_X1_LVT \registers_reg[17][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_17__ap[22]), .CK(n_0_47), .Q(registers_17__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[21][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_21__ap[22]), .CK(n_0_51), .Q(registers_21__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1142 (.A1(registers_17__ap[22]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[22]), .ZN(n_1_0_1087)); + SDFF_X1_LVT \registers_reg[6][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_6__ap[22]), .CK(n_0_36), .Q(registers_6__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[11][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_11__ap[22]), .CK(n_0_41), .Q(registers_11__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1143 (.A1(registers_6__ap[22]), .A2(n_1_0_1300), .B1( + n_1_0_1270), .B2(registers_11__ap[22]), .ZN(n_1_0_1088)); + SDFF_X1_LVT \registers_reg[20][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_20__ap[22]), .CK(n_0_50), .Q(registers_20__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[12][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_12__ap[22]), .CK(n_0_42), .Q(registers_12__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1141 (.A1(registers_20__ap[22]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[22]), .ZN(n_1_0_1086)); + SDFF_X1_LVT \registers_reg[10][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_10__ap[22]), .CK(n_0_40), .Q(registers_10__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[5][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_5__ap[22]), .CK(n_0_35), .Q(registers_5__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1140 (.A1(registers_10__ap[22]), .A2(n_1_0_1287), .B1( + n_1_0_1273), .B2(registers_5__ap[22]), .ZN(n_1_0_1085)); + NAND3_X1_LVT i_1_0_1139 (.A1(n_1_0_1088), .A2(n_1_0_1086), .A3(n_1_0_1085), + .ZN(n_1_0_1084)); + SDFF_X1_LVT \registers_reg[31][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_31__ap[22]), .CK(n_0_61), .Q(registers_31__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[2][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_2__ap[22]), .CK(n_0_32), .Q(registers_2__ap[22]), .QN()); + AOI221_X1_LVT i_1_0_1138 (.A(n_1_0_1084), .B1(n_1_0_1266), .B2( + registers_31__ap[22]), .C1(registers_2__ap[22]), .C2(n_1_0_1268), .ZN( + n_1_0_1083)); + SDFF_X1_LVT \registers_reg[22][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_22__ap[22]), .CK(n_0_52), .Q(registers_22__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[26][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_26__ap[22]), .CK(n_0_56), .Q(registers_26__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[13][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_13__ap[22]), .CK(n_0_43), .Q(registers_13__ap[22]), .QN()); + AOI222_X1_LVT i_1_0_1137 (.A1(registers_22__ap[22]), .A2(n_1_0_1294), + .B1(n_1_0_1285), .B2(registers_26__ap[22]), .C1(n_1_0_1277), .C2( + registers_13__ap[22]), .ZN(n_1_0_1082)); + NAND2_X1_LVT i_1_0_1136 (.A1(n_1_0_1083), .A2(n_1_0_1082), .ZN(n_1_0_1081)); + SDFF_X1_LVT \registers_reg[1][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_1__ap[22]), .CK(n_0_0), .Q(registers_1__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[28][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_28__ap[22]), .CK(n_0_58), .Q(registers_28__ap[22]), .QN()); + AOI221_X1_LVT i_1_0_1135 (.A(n_1_0_1081), .B1(n_1_0_1274), .B2( + registers_1__ap[22]), .C1(registers_28__ap[22]), .C2(n_1_0_1283), .ZN( + n_1_0_1080)); + SDFF_X1_LVT \registers_reg[18][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_18__ap[22]), .CK(n_0_48), .Q(registers_18__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[30][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_30__ap[22]), .CK(n_0_60), .Q(registers_30__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1134 (.A1(registers_18__ap[22]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[22]), .ZN(n_1_0_1079)); + SDFF_X1_LVT \registers_reg[24][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_24__ap[22]), .CK(n_0_54), .Q(registers_24__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[4][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_4__ap[22]), .CK(n_0_34), .Q(registers_4__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1133 (.A1(registers_24__ap[22]), .A2(n_1_0_1289), .B1( + n_1_0_1278), .B2(registers_4__ap[22]), .ZN(n_1_0_1078)); + SDFF_X1_LVT \registers_reg[15][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_15__ap[22]), .CK(n_0_45), .Q(registers_15__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[16][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_16__ap[22]), .CK(n_0_46), .Q(registers_16__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1132 (.A1(registers_15__ap[22]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[22]), .ZN(n_1_0_1077)); + NAND3_X1_LVT i_1_0_1131 (.A1(n_1_0_1079), .A2(n_1_0_1078), .A3(n_1_0_1077), + .ZN(n_1_0_1076)); + SDFF_X1_LVT \registers_reg[19][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_19__ap[22]), .CK(n_0_49), .Q(registers_19__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[25][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_25__ap[22]), .CK(n_0_55), .Q(registers_25__ap[22]), .QN()); + AOI221_X1_LVT i_1_0_1130 (.A(n_1_0_1076), .B1(n_1_0_1295), .B2( + registers_19__ap[22]), .C1(registers_25__ap[22]), .C2(n_1_0_1269), + .ZN(n_1_0_1075)); + SDFF_X1_LVT \registers_reg[7][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_7__ap[22]), .CK(n_0_37), .Q(registers_7__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[14][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_14__ap[22]), .CK(n_0_44), .Q(registers_14__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1129 (.A1(registers_7__ap[22]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[22]), .ZN(n_1_0_1074)); + SDFF_X1_LVT \registers_reg[9][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_9__ap[22]), .CK(n_0_39), .Q(registers_9__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[29][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_29__ap[22]), .CK(n_0_59), .Q(registers_29__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1128 (.A1(registers_9__ap[22]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[22]), .ZN(n_1_0_1073)); + SDFF_X1_LVT \registers_reg[8][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_8__ap[22]), .CK(n_0_38), .Q(registers_8__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[23][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_23__ap[22]), .CK(n_0_53), .Q(registers_23__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1127 (.A1(registers_8__ap[22]), .A2(n_1_0_1282), .B1( + n_1_0_1264), .B2(registers_23__ap[22]), .ZN(n_1_0_1072)); + NAND3_X1_LVT i_1_0_1126 (.A1(n_1_0_1074), .A2(n_1_0_1073), .A3(n_1_0_1072), + .ZN(n_1_0_1071)); + SDFF_X1_LVT \registers_reg[27][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_27__ap[22]), .CK(n_0_57), .Q(registers_27__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[3][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_3__ap[22]), .CK(n_0_33), .Q(registers_3__ap[22]), .QN()); + AOI221_X1_LVT i_1_0_1125 (.A(n_1_0_1071), .B1(n_1_0_1279), .B2( + registers_27__ap[22]), .C1(registers_3__ap[22]), .C2(n_1_0_1257), .ZN( + n_1_0_1070)); + NAND4_X1_LVT i_1_0_1124 (.A1(n_1_0_1087), .A2(n_1_0_1080), .A3(n_1_0_1075), + .A4(n_1_0_1070), .ZN(RRs1[22])); + AND2_X1_LVT i_0_0_21 (.A1(n_0_0_16), .A2(WRd[21]), .ZN(registers[21])); + SDFF_X1_LVT \registers_reg[17][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_17__ap[21]), .CK(n_0_47), .Q(registers_17__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[21][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_21__ap[21]), .CK(n_0_51), .Q(registers_21__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1122 (.A1(registers_17__ap[21]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[21]), .ZN(n_1_0_1068)); + SDFF_X1_LVT \registers_reg[6][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_6__ap[21]), .CK(n_0_36), .Q(registers_6__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[8][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_8__ap[21]), .CK(n_0_38), .Q(registers_8__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1123 (.A1(registers_6__ap[21]), .A2(n_1_0_1300), .B1( + n_1_0_1282), .B2(registers_8__ap[21]), .ZN(n_1_0_1069)); + SDFF_X1_LVT \registers_reg[20][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_20__ap[21]), .CK(n_0_50), .Q(registers_20__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[12][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_12__ap[21]), .CK(n_0_42), .Q(registers_12__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1121 (.A1(registers_20__ap[21]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[21]), .ZN(n_1_0_1067)); + SDFF_X1_LVT \registers_reg[5][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_5__ap[21]), .CK(n_0_35), .Q(registers_5__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[11][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_11__ap[21]), .CK(n_0_41), .Q(registers_11__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1120 (.A1(registers_5__ap[21]), .A2(n_1_0_1273), .B1( + n_1_0_1270), .B2(registers_11__ap[21]), .ZN(n_1_0_1066)); + NAND3_X1_LVT i_1_0_1119 (.A1(n_1_0_1069), .A2(n_1_0_1067), .A3(n_1_0_1066), + .ZN(n_1_0_1065)); + SDFF_X1_LVT \registers_reg[10][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_10__ap[21]), .CK(n_0_40), .Q(registers_10__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[2][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_2__ap[21]), .CK(n_0_32), .Q(registers_2__ap[21]), .QN()); + AOI221_X1_LVT i_1_0_1118 (.A(n_1_0_1065), .B1(n_1_0_1287), .B2( + registers_10__ap[21]), .C1(registers_2__ap[21]), .C2(n_1_0_1268), .ZN( + n_1_0_1064)); + SDFF_X1_LVT \registers_reg[13][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_13__ap[21]), .CK(n_0_43), .Q(registers_13__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[30][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_30__ap[21]), .CK(n_0_60), .Q(registers_30__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[22][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_22__ap[21]), .CK(n_0_52), .Q(registers_22__ap[21]), .QN()); + AOI222_X1_LVT i_1_0_1117 (.A1(registers_13__ap[21]), .A2(n_1_0_1277), + .B1(n_1_0_1272), .B2(registers_30__ap[21]), .C1(registers_22__ap[21]), + .C2(n_1_0_1294), .ZN(n_1_0_1063)); + NAND2_X1_LVT i_1_0_1116 (.A1(n_1_0_1064), .A2(n_1_0_1063), .ZN(n_1_0_1062)); + SDFF_X1_LVT \registers_reg[1][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_1__ap[21]), .CK(n_0_0), .Q(registers_1__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[28][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_28__ap[21]), .CK(n_0_58), .Q(registers_28__ap[21]), .QN()); + AOI221_X1_LVT i_1_0_1115 (.A(n_1_0_1062), .B1(n_1_0_1274), .B2( + registers_1__ap[21]), .C1(registers_28__ap[21]), .C2(n_1_0_1283), .ZN( + n_1_0_1061)); + SDFF_X1_LVT \registers_reg[18][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_18__ap[21]), .CK(n_0_48), .Q(registers_18__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[26][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_26__ap[21]), .CK(n_0_56), .Q(registers_26__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1114 (.A1(registers_18__ap[21]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[21]), .ZN(n_1_0_1060)); + SDFF_X1_LVT \registers_reg[24][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_24__ap[21]), .CK(n_0_54), .Q(registers_24__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[4][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_4__ap[21]), .CK(n_0_34), .Q(registers_4__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1113 (.A1(registers_24__ap[21]), .A2(n_1_0_1289), .B1( + n_1_0_1278), .B2(registers_4__ap[21]), .ZN(n_1_0_1059)); + SDFF_X1_LVT \registers_reg[15][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_15__ap[21]), .CK(n_0_45), .Q(registers_15__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[16][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_16__ap[21]), .CK(n_0_46), .Q(registers_16__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1112 (.A1(registers_15__ap[21]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[21]), .ZN(n_1_0_1058)); + NAND3_X1_LVT i_1_0_1111 (.A1(n_1_0_1060), .A2(n_1_0_1059), .A3(n_1_0_1058), + .ZN(n_1_0_1057)); + SDFF_X1_LVT \registers_reg[19][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_19__ap[21]), .CK(n_0_49), .Q(registers_19__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[25][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_25__ap[21]), .CK(n_0_55), .Q(registers_25__ap[21]), .QN()); + AOI221_X1_LVT i_1_0_1110 (.A(n_1_0_1057), .B1(n_1_0_1295), .B2( + registers_19__ap[21]), .C1(registers_25__ap[21]), .C2(n_1_0_1269), + .ZN(n_1_0_1056)); + SDFF_X1_LVT \registers_reg[7][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_7__ap[21]), .CK(n_0_37), .Q(registers_7__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[14][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_14__ap[21]), .CK(n_0_44), .Q(registers_14__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1109 (.A1(registers_7__ap[21]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[21]), .ZN(n_1_0_1055)); + SDFF_X1_LVT \registers_reg[9][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_9__ap[21]), .CK(n_0_39), .Q(registers_9__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[29][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_29__ap[21]), .CK(n_0_59), .Q(registers_29__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1108 (.A1(registers_9__ap[21]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[21]), .ZN(n_1_0_1054)); + SDFF_X1_LVT \registers_reg[23][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_23__ap[21]), .CK(n_0_53), .Q(registers_23__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[3][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_3__ap[21]), .CK(n_0_33), .Q(registers_3__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1107 (.A1(registers_23__ap[21]), .A2(n_1_0_1264), .B1( + n_1_0_1257), .B2(registers_3__ap[21]), .ZN(n_1_0_1053)); + NAND3_X1_LVT i_1_0_1106 (.A1(n_1_0_1055), .A2(n_1_0_1054), .A3(n_1_0_1053), + .ZN(n_1_0_1052)); + SDFF_X1_LVT \registers_reg[27][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_27__ap[21]), .CK(n_0_57), .Q(registers_27__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[31][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_31__ap[21]), .CK(n_0_61), .Q(registers_31__ap[21]), .QN()); + AOI221_X1_LVT i_1_0_1105 (.A(n_1_0_1052), .B1(n_1_0_1279), .B2( + registers_27__ap[21]), .C1(registers_31__ap[21]), .C2(n_1_0_1266), + .ZN(n_1_0_1051)); + NAND4_X1_LVT i_1_0_1104 (.A1(n_1_0_1068), .A2(n_1_0_1061), .A3(n_1_0_1056), + .A4(n_1_0_1051), .ZN(RRs1[21])); + AND2_X1_LVT i_0_0_20 (.A1(n_0_0_16), .A2(WRd[20]), .ZN(registers[20])); + SDFF_X1_LVT \registers_reg[17][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_17__ap[20]), .CK(n_0_47), .Q(registers_17__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[21][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_21__ap[20]), .CK(n_0_51), .Q(registers_21__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1100 (.A1(registers_17__ap[20]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[20]), .ZN(n_1_0_1047)); + SDFF_X1_LVT \registers_reg[10][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_10__ap[20]), .CK(n_0_40), .Q(registers_10__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[2][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_2__ap[20]), .CK(n_0_32), .Q(registers_2__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1103 (.A1(registers_10__ap[20]), .A2(n_1_0_1287), .B1( + n_1_0_1268), .B2(registers_2__ap[20]), .ZN(n_1_0_1050)); + SDFF_X1_LVT \registers_reg[20][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_20__ap[20]), .CK(n_0_50), .Q(registers_20__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[12][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_12__ap[20]), .CK(n_0_42), .Q(registers_12__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1099 (.A1(registers_20__ap[20]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[20]), .ZN(n_1_0_1046)); + SDFF_X1_LVT \registers_reg[15][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_15__ap[20]), .CK(n_0_45), .Q(registers_15__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[8][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_8__ap[20]), .CK(n_0_38), .Q(registers_8__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1102 (.A1(registers_15__ap[20]), .A2(n_1_0_1286), .B1( + n_1_0_1282), .B2(registers_8__ap[20]), .ZN(n_1_0_1049)); + INV_X1_LVT i_1_0_1101 (.A(n_1_0_1049), .ZN(n_1_0_1048)); + SDFF_X1_LVT \registers_reg[11][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_11__ap[20]), .CK(n_0_41), .Q(registers_11__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[5][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_5__ap[20]), .CK(n_0_35), .Q(registers_5__ap[20]), .QN()); + AOI221_X1_LVT i_1_0_1098 (.A(n_1_0_1048), .B1(n_1_0_1270), .B2( + registers_11__ap[20]), .C1(registers_5__ap[20]), .C2(n_1_0_1273), .ZN( + n_1_0_1045)); + SDFF_X1_LVT \registers_reg[13][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_13__ap[20]), .CK(n_0_43), .Q(registers_13__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[30][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_30__ap[20]), .CK(n_0_60), .Q(registers_30__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[22][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_22__ap[20]), .CK(n_0_52), .Q(registers_22__ap[20]), .QN()); + AOI222_X1_LVT i_1_0_1097 (.A1(registers_13__ap[20]), .A2(n_1_0_1277), + .B1(n_1_0_1272), .B2(registers_30__ap[20]), .C1(registers_22__ap[20]), + .C2(n_1_0_1294), .ZN(n_1_0_1044)); + NAND4_X1_LVT i_1_0_1096 (.A1(n_1_0_1050), .A2(n_1_0_1046), .A3(n_1_0_1045), + .A4(n_1_0_1044), .ZN(n_1_0_1043)); + SDFF_X1_LVT \registers_reg[1][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_1__ap[20]), .CK(n_0_0), .Q(registers_1__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[28][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_28__ap[20]), .CK(n_0_58), .Q(registers_28__ap[20]), .QN()); + AOI221_X1_LVT i_1_0_1095 (.A(n_1_0_1043), .B1(n_1_0_1274), .B2( + registers_1__ap[20]), .C1(registers_28__ap[20]), .C2(n_1_0_1283), .ZN( + n_1_0_1042)); + SDFF_X1_LVT \registers_reg[18][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_18__ap[20]), .CK(n_0_48), .Q(registers_18__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[26][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_26__ap[20]), .CK(n_0_56), .Q(registers_26__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1094 (.A1(registers_18__ap[20]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[20]), .ZN(n_1_0_1041)); + SDFF_X1_LVT \registers_reg[24][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_24__ap[20]), .CK(n_0_54), .Q(registers_24__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[4][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_4__ap[20]), .CK(n_0_34), .Q(registers_4__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1093 (.A1(registers_24__ap[20]), .A2(n_1_0_1289), .B1( + n_1_0_1278), .B2(registers_4__ap[20]), .ZN(n_1_0_1040)); + SDFF_X1_LVT \registers_reg[6][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_6__ap[20]), .CK(n_0_36), .Q(registers_6__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[25][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_25__ap[20]), .CK(n_0_55), .Q(registers_25__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1092 (.A1(registers_6__ap[20]), .A2(n_1_0_1300), .B1( + n_1_0_1269), .B2(registers_25__ap[20]), .ZN(n_1_0_1039)); + NAND3_X1_LVT i_1_0_1091 (.A1(n_1_0_1041), .A2(n_1_0_1040), .A3(n_1_0_1039), + .ZN(n_1_0_1038)); + SDFF_X1_LVT \registers_reg[19][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_19__ap[20]), .CK(n_0_49), .Q(registers_19__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[16][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_16__ap[20]), .CK(n_0_46), .Q(registers_16__ap[20]), .QN()); + AOI221_X1_LVT i_1_0_1090 (.A(n_1_0_1038), .B1(n_1_0_1295), .B2( + registers_19__ap[20]), .C1(registers_16__ap[20]), .C2(n_1_0_1267), + .ZN(n_1_0_1037)); + SDFF_X1_LVT \registers_reg[7][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_7__ap[20]), .CK(n_0_37), .Q(registers_7__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[14][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_14__ap[20]), .CK(n_0_44), .Q(registers_14__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1089 (.A1(registers_7__ap[20]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[20]), .ZN(n_1_0_1036)); + SDFF_X1_LVT \registers_reg[9][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_9__ap[20]), .CK(n_0_39), .Q(registers_9__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[29][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_29__ap[20]), .CK(n_0_59), .Q(registers_29__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1088 (.A1(registers_9__ap[20]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[20]), .ZN(n_1_0_1035)); + SDFF_X1_LVT \registers_reg[23][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_23__ap[20]), .CK(n_0_53), .Q(registers_23__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[3][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_3__ap[20]), .CK(n_0_33), .Q(registers_3__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1087 (.A1(registers_23__ap[20]), .A2(n_1_0_1264), .B1( + n_1_0_1257), .B2(registers_3__ap[20]), .ZN(n_1_0_1034)); + NAND3_X1_LVT i_1_0_1086 (.A1(n_1_0_1036), .A2(n_1_0_1035), .A3(n_1_0_1034), + .ZN(n_1_0_1033)); + SDFF_X1_LVT \registers_reg[27][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_27__ap[20]), .CK(n_0_57), .Q(registers_27__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[31][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_31__ap[20]), .CK(n_0_61), .Q(registers_31__ap[20]), .QN()); + AOI221_X1_LVT i_1_0_1085 (.A(n_1_0_1033), .B1(n_1_0_1279), .B2( + registers_27__ap[20]), .C1(registers_31__ap[20]), .C2(n_1_0_1266), + .ZN(n_1_0_1032)); + NAND4_X1_LVT i_1_0_1084 (.A1(n_1_0_1047), .A2(n_1_0_1042), .A3(n_1_0_1037), + .A4(n_1_0_1032), .ZN(RRs1[20])); + AND2_X1_LVT i_0_0_19 (.A1(n_0_0_16), .A2(WRd[19]), .ZN(registers[19])); + SDFF_X1_LVT \registers_reg[17][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_17__ap[19]), .CK(n_0_47), .Q(registers_17__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[21][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_21__ap[19]), .CK(n_0_51), .Q(registers_21__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1080 (.A1(registers_17__ap[19]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[19]), .ZN(n_1_0_1028)); + SDFF_X1_LVT \registers_reg[2][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_2__ap[19]), .CK(n_0_32), .Q(registers_2__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[31][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_31__ap[19]), .CK(n_0_61), .Q(registers_31__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1083 (.A1(registers_2__ap[19]), .A2(n_1_0_1268), .B1( + n_1_0_1266), .B2(registers_31__ap[19]), .ZN(n_1_0_1031)); + SDFF_X1_LVT \registers_reg[20][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_20__ap[19]), .CK(n_0_50), .Q(registers_20__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[12][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_12__ap[19]), .CK(n_0_42), .Q(registers_12__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1079 (.A1(registers_20__ap[19]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[19]), .ZN(n_1_0_1027)); + SDFF_X1_LVT \registers_reg[15][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_15__ap[19]), .CK(n_0_45), .Q(registers_15__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[11][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_11__ap[19]), .CK(n_0_41), .Q(registers_11__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1082 (.A1(registers_15__ap[19]), .A2(n_1_0_1286), .B1( + n_1_0_1270), .B2(registers_11__ap[19]), .ZN(n_1_0_1030)); + INV_X1_LVT i_1_0_1081 (.A(n_1_0_1030), .ZN(n_1_0_1029)); + SDFF_X1_LVT \registers_reg[27][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_27__ap[19]), .CK(n_0_57), .Q(registers_27__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[24][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_24__ap[19]), .CK(n_0_54), .Q(registers_24__ap[19]), .QN()); + AOI221_X1_LVT i_1_0_1078 (.A(n_1_0_1029), .B1(n_1_0_1279), .B2( + registers_27__ap[19]), .C1(registers_24__ap[19]), .C2(n_1_0_1289), + .ZN(n_1_0_1026)); + SDFF_X1_LVT \registers_reg[22][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_22__ap[19]), .CK(n_0_52), .Q(registers_22__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[26][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_26__ap[19]), .CK(n_0_56), .Q(registers_26__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[13][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_13__ap[19]), .CK(n_0_43), .Q(registers_13__ap[19]), .QN()); + AOI222_X1_LVT i_1_0_1077 (.A1(registers_22__ap[19]), .A2(n_1_0_1294), + .B1(n_1_0_1285), .B2(registers_26__ap[19]), .C1(n_1_0_1277), .C2( + registers_13__ap[19]), .ZN(n_1_0_1025)); + NAND4_X1_LVT i_1_0_1076 (.A1(n_1_0_1031), .A2(n_1_0_1027), .A3(n_1_0_1026), + .A4(n_1_0_1025), .ZN(n_1_0_1024)); + SDFF_X1_LVT \registers_reg[1][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_1__ap[19]), .CK(n_0_0), .Q(registers_1__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[28][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_28__ap[19]), .CK(n_0_58), .Q(registers_28__ap[19]), .QN()); + AOI221_X1_LVT i_1_0_1075 (.A(n_1_0_1024), .B1(n_1_0_1274), .B2( + registers_1__ap[19]), .C1(registers_28__ap[19]), .C2(n_1_0_1283), .ZN( + n_1_0_1023)); + SDFF_X1_LVT \registers_reg[18][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_18__ap[19]), .CK(n_0_48), .Q(registers_18__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[30][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_30__ap[19]), .CK(n_0_60), .Q(registers_30__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1074 (.A1(registers_18__ap[19]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[19]), .ZN(n_1_0_1022)); + SDFF_X1_LVT \registers_reg[4][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_4__ap[19]), .CK(n_0_34), .Q(registers_4__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[5][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_5__ap[19]), .CK(n_0_35), .Q(registers_5__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1073 (.A1(registers_4__ap[19]), .A2(n_1_0_1278), .B1( + n_1_0_1273), .B2(registers_5__ap[19]), .ZN(n_1_0_1021)); + SDFF_X1_LVT \registers_reg[6][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_6__ap[19]), .CK(n_0_36), .Q(registers_6__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[25][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_25__ap[19]), .CK(n_0_55), .Q(registers_25__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1072 (.A1(registers_6__ap[19]), .A2(n_1_0_1300), .B1( + n_1_0_1269), .B2(registers_25__ap[19]), .ZN(n_1_0_1020)); + NAND3_X1_LVT i_1_0_1071 (.A1(n_1_0_1022), .A2(n_1_0_1021), .A3(n_1_0_1020), + .ZN(n_1_0_1019)); + SDFF_X1_LVT \registers_reg[19][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_19__ap[19]), .CK(n_0_49), .Q(registers_19__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[16][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_16__ap[19]), .CK(n_0_46), .Q(registers_16__ap[19]), .QN()); + AOI221_X1_LVT i_1_0_1070 (.A(n_1_0_1019), .B1(n_1_0_1295), .B2( + registers_19__ap[19]), .C1(registers_16__ap[19]), .C2(n_1_0_1267), + .ZN(n_1_0_1018)); + SDFF_X1_LVT \registers_reg[9][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_9__ap[19]), .CK(n_0_39), .Q(registers_9__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[29][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_29__ap[19]), .CK(n_0_59), .Q(registers_29__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1069 (.A1(registers_9__ap[19]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[19]), .ZN(n_1_0_1017)); + SDFF_X1_LVT \registers_reg[8][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_8__ap[19]), .CK(n_0_38), .Q(registers_8__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[23][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_23__ap[19]), .CK(n_0_53), .Q(registers_23__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1068 (.A1(registers_8__ap[19]), .A2(n_1_0_1282), .B1( + n_1_0_1264), .B2(registers_23__ap[19]), .ZN(n_1_0_1016)); + SDFF_X1_LVT \registers_reg[7][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_7__ap[19]), .CK(n_0_37), .Q(registers_7__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[14][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_14__ap[19]), .CK(n_0_44), .Q(registers_14__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1067 (.A1(registers_7__ap[19]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[19]), .ZN(n_1_0_1015)); + NAND3_X1_LVT i_1_0_1066 (.A1(n_1_0_1017), .A2(n_1_0_1016), .A3(n_1_0_1015), + .ZN(n_1_0_1014)); + SDFF_X1_LVT \registers_reg[10][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_10__ap[19]), .CK(n_0_40), .Q(registers_10__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[3][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_3__ap[19]), .CK(n_0_33), .Q(registers_3__ap[19]), .QN()); + AOI221_X1_LVT i_1_0_1065 (.A(n_1_0_1014), .B1(n_1_0_1287), .B2( + registers_10__ap[19]), .C1(registers_3__ap[19]), .C2(n_1_0_1257), .ZN( + n_1_0_1013)); + NAND4_X1_LVT i_1_0_1064 (.A1(n_1_0_1028), .A2(n_1_0_1023), .A3(n_1_0_1018), + .A4(n_1_0_1013), .ZN(RRs1[19])); + AND2_X1_LVT i_0_0_18 (.A1(n_0_0_16), .A2(WRd[18]), .ZN(registers[18])); + SDFF_X1_LVT \registers_reg[24][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_24__ap[18]), .CK(n_0_54), .Q(registers_24__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[28][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_28__ap[18]), .CK(n_0_58), .Q(registers_28__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1062 (.A1(registers_24__ap[18]), .A2(n_1_0_1289), .B1( + n_1_0_1283), .B2(registers_28__ap[18]), .ZN(n_1_0_1011)); + SDFF_X1_LVT \registers_reg[11][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_11__ap[18]), .CK(n_0_41), .Q(registers_11__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[16][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_16__ap[18]), .CK(n_0_46), .Q(registers_16__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1063 (.A1(registers_11__ap[18]), .A2(n_1_0_1270), .B1( + n_1_0_1267), .B2(registers_16__ap[18]), .ZN(n_1_0_1012)); + SDFF_X1_LVT \registers_reg[9][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_9__ap[18]), .CK(n_0_39), .Q(registers_9__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[7][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_7__ap[18]), .CK(n_0_37), .Q(registers_7__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1061 (.A1(registers_9__ap[18]), .A2(n_1_0_1291), .B1( + n_1_0_1263), .B2(registers_7__ap[18]), .ZN(n_1_0_1010)); + SDFF_X1_LVT \registers_reg[27][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_27__ap[18]), .CK(n_0_57), .Q(registers_27__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[25][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_25__ap[18]), .CK(n_0_55), .Q(registers_25__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1060 (.A1(registers_27__ap[18]), .A2(n_1_0_1279), .B1( + n_1_0_1269), .B2(registers_25__ap[18]), .ZN(n_1_0_1009)); + NAND3_X1_LVT i_1_0_1059 (.A1(n_1_0_1012), .A2(n_1_0_1010), .A3(n_1_0_1009), + .ZN(n_1_0_1008)); + SDFF_X1_LVT \registers_reg[31][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_31__ap[18]), .CK(n_0_61), .Q(registers_31__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[6][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_6__ap[18]), .CK(n_0_36), .Q(registers_6__ap[18]), .QN()); + AOI221_X1_LVT i_1_0_1058 (.A(n_1_0_1008), .B1(n_1_0_1266), .B2( + registers_31__ap[18]), .C1(registers_6__ap[18]), .C2(n_1_0_1300), .ZN( + n_1_0_1007)); + SDFF_X1_LVT \registers_reg[22][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_22__ap[18]), .CK(n_0_52), .Q(registers_22__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[26][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_26__ap[18]), .CK(n_0_56), .Q(registers_26__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[1][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_1__ap[18]), .CK(n_0_0), .Q(registers_1__ap[18]), .QN()); + AOI222_X1_LVT i_1_0_1057 (.A1(registers_22__ap[18]), .A2(n_1_0_1294), + .B1(n_1_0_1285), .B2(registers_26__ap[18]), .C1(n_1_0_1274), .C2( + registers_1__ap[18]), .ZN(n_1_0_1006)); + NAND2_X1_LVT i_1_0_1056 (.A1(n_1_0_1007), .A2(n_1_0_1006), .ZN(n_1_0_1005)); + SDFF_X1_LVT \registers_reg[29][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_29__ap[18]), .CK(n_0_59), .Q(registers_29__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[2][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_2__ap[18]), .CK(n_0_32), .Q(registers_2__ap[18]), .QN()); + AOI221_X1_LVT i_1_0_1055 (.A(n_1_0_1005), .B1(n_1_0_1276), .B2( + registers_29__ap[18]), .C1(registers_2__ap[18]), .C2(n_1_0_1268), .ZN( + n_1_0_1004)); + SDFF_X1_LVT \registers_reg[18][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_18__ap[18]), .CK(n_0_48), .Q(registers_18__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[30][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_30__ap[18]), .CK(n_0_60), .Q(registers_30__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1054 (.A1(registers_18__ap[18]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[18]), .ZN(n_1_0_1003)); + SDFF_X1_LVT \registers_reg[4][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_4__ap[18]), .CK(n_0_34), .Q(registers_4__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[12][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_12__ap[18]), .CK(n_0_42), .Q(registers_12__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1053 (.A1(registers_4__ap[18]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[18]), .ZN(n_1_0_1002)); + SDFF_X1_LVT \registers_reg[19][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_19__ap[18]), .CK(n_0_49), .Q(registers_19__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[21][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_21__ap[18]), .CK(n_0_51), .Q(registers_21__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1052 (.A1(registers_19__ap[18]), .A2(n_1_0_1295), .B1( + n_1_0_1259), .B2(registers_21__ap[18]), .ZN(n_1_0_1001)); + NAND3_X1_LVT i_1_0_1051 (.A1(n_1_0_1003), .A2(n_1_0_1002), .A3(n_1_0_1001), + .ZN(n_1_0_1000)); + SDFF_X1_LVT \registers_reg[5][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_5__ap[18]), .CK(n_0_35), .Q(registers_5__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[20][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_20__ap[18]), .CK(n_0_50), .Q(registers_20__ap[18]), .QN()); + AOI221_X1_LVT i_1_0_1050 (.A(n_1_0_1000), .B1(n_1_0_1273), .B2( + registers_5__ap[18]), .C1(registers_20__ap[18]), .C2(n_1_0_1281), .ZN( + n_1_0_999)); + SDFF_X1_LVT \registers_reg[8][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_8__ap[18]), .CK(n_0_38), .Q(registers_8__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[23][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_23__ap[18]), .CK(n_0_53), .Q(registers_23__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1049 (.A1(registers_8__ap[18]), .A2(n_1_0_1282), .B1( + n_1_0_1264), .B2(registers_23__ap[18]), .ZN(n_1_0_998)); + SDFF_X1_LVT \registers_reg[13][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_13__ap[18]), .CK(n_0_43), .Q(registers_13__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[17][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_17__ap[18]), .CK(n_0_47), .Q(registers_17__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1048 (.A1(registers_13__ap[18]), .A2(n_1_0_1277), .B1( + n_1_0_1271), .B2(registers_17__ap[18]), .ZN(n_1_0_997)); + SDFF_X1_LVT \registers_reg[15][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_15__ap[18]), .CK(n_0_45), .Q(registers_15__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[14][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_14__ap[18]), .CK(n_0_44), .Q(registers_14__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1047 (.A1(registers_15__ap[18]), .A2(n_1_0_1286), .B1( + n_1_0_1258), .B2(registers_14__ap[18]), .ZN(n_1_0_996)); + NAND3_X1_LVT i_1_0_1046 (.A1(n_1_0_998), .A2(n_1_0_997), .A3(n_1_0_996), + .ZN(n_1_0_995)); + SDFF_X1_LVT \registers_reg[10][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_10__ap[18]), .CK(n_0_40), .Q(registers_10__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[3][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_3__ap[18]), .CK(n_0_33), .Q(registers_3__ap[18]), .QN()); + AOI221_X1_LVT i_1_0_1045 (.A(n_1_0_995), .B1(n_1_0_1287), .B2( + registers_10__ap[18]), .C1(registers_3__ap[18]), .C2(n_1_0_1257), .ZN( + n_1_0_994)); + NAND4_X1_LVT i_1_0_1044 (.A1(n_1_0_1011), .A2(n_1_0_1004), .A3(n_1_0_999), + .A4(n_1_0_994), .ZN(RRs1[18])); + AND2_X1_LVT i_0_0_17 (.A1(n_0_0_16), .A2(WRd[17]), .ZN(registers[17])); + SDFF_X1_LVT \registers_reg[17][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_17__ap[17]), .CK(n_0_47), .Q(registers_17__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[21][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_21__ap[17]), .CK(n_0_51), .Q(registers_21__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1040 (.A1(registers_17__ap[17]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[17]), .ZN(n_1_0_990)); + SDFF_X1_LVT \registers_reg[2][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_2__ap[17]), .CK(n_0_32), .Q(registers_2__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[31][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_31__ap[17]), .CK(n_0_61), .Q(registers_31__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1043 (.A1(registers_2__ap[17]), .A2(n_1_0_1268), .B1( + n_1_0_1266), .B2(registers_31__ap[17]), .ZN(n_1_0_993)); + SDFF_X1_LVT \registers_reg[20][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_20__ap[17]), .CK(n_0_50), .Q(registers_20__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[12][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_12__ap[17]), .CK(n_0_42), .Q(registers_12__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1039 (.A1(registers_20__ap[17]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[17]), .ZN(n_1_0_989)); + SDFF_X1_LVT \registers_reg[15][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_15__ap[17]), .CK(n_0_45), .Q(registers_15__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[11][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_11__ap[17]), .CK(n_0_41), .Q(registers_11__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1042 (.A1(registers_15__ap[17]), .A2(n_1_0_1286), .B1( + n_1_0_1270), .B2(registers_11__ap[17]), .ZN(n_1_0_992)); + INV_X1_LVT i_1_0_1041 (.A(n_1_0_992), .ZN(n_1_0_991)); + SDFF_X1_LVT \registers_reg[10][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_10__ap[17]), .CK(n_0_40), .Q(registers_10__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[24][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_24__ap[17]), .CK(n_0_54), .Q(registers_24__ap[17]), .QN()); + AOI221_X1_LVT i_1_0_1038 (.A(n_1_0_991), .B1(n_1_0_1287), .B2( + registers_10__ap[17]), .C1(registers_24__ap[17]), .C2(n_1_0_1289), + .ZN(n_1_0_988)); + SDFF_X1_LVT \registers_reg[22][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_22__ap[17]), .CK(n_0_52), .Q(registers_22__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[26][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_26__ap[17]), .CK(n_0_56), .Q(registers_26__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[13][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_13__ap[17]), .CK(n_0_43), .Q(registers_13__ap[17]), .QN()); + AOI222_X1_LVT i_1_0_1037 (.A1(registers_22__ap[17]), .A2(n_1_0_1294), + .B1(n_1_0_1285), .B2(registers_26__ap[17]), .C1(n_1_0_1277), .C2( + registers_13__ap[17]), .ZN(n_1_0_987)); + NAND4_X1_LVT i_1_0_1036 (.A1(n_1_0_993), .A2(n_1_0_989), .A3(n_1_0_988), + .A4(n_1_0_987), .ZN(n_1_0_986)); + SDFF_X1_LVT \registers_reg[1][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_1__ap[17]), .CK(n_0_0), .Q(registers_1__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[28][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_28__ap[17]), .CK(n_0_58), .Q(registers_28__ap[17]), .QN()); + AOI221_X1_LVT i_1_0_1035 (.A(n_1_0_986), .B1(n_1_0_1274), .B2( + registers_1__ap[17]), .C1(registers_28__ap[17]), .C2(n_1_0_1283), .ZN( + n_1_0_985)); + SDFF_X1_LVT \registers_reg[18][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_18__ap[17]), .CK(n_0_48), .Q(registers_18__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[30][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_30__ap[17]), .CK(n_0_60), .Q(registers_30__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1034 (.A1(registers_18__ap[17]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[17]), .ZN(n_1_0_984)); + SDFF_X1_LVT \registers_reg[4][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_4__ap[17]), .CK(n_0_34), .Q(registers_4__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[5][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_5__ap[17]), .CK(n_0_35), .Q(registers_5__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1033 (.A1(registers_4__ap[17]), .A2(n_1_0_1278), .B1( + n_1_0_1273), .B2(registers_5__ap[17]), .ZN(n_1_0_983)); + SDFF_X1_LVT \registers_reg[6][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_6__ap[17]), .CK(n_0_36), .Q(registers_6__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[25][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_25__ap[17]), .CK(n_0_55), .Q(registers_25__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1032 (.A1(registers_6__ap[17]), .A2(n_1_0_1300), .B1( + n_1_0_1269), .B2(registers_25__ap[17]), .ZN(n_1_0_982)); + NAND3_X1_LVT i_1_0_1031 (.A1(n_1_0_984), .A2(n_1_0_983), .A3(n_1_0_982), + .ZN(n_1_0_981)); + SDFF_X1_LVT \registers_reg[19][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_19__ap[17]), .CK(n_0_49), .Q(registers_19__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[16][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_16__ap[17]), .CK(n_0_46), .Q(registers_16__ap[17]), .QN()); + AOI221_X1_LVT i_1_0_1030 (.A(n_1_0_981), .B1(n_1_0_1295), .B2( + registers_19__ap[17]), .C1(registers_16__ap[17]), .C2(n_1_0_1267), + .ZN(n_1_0_980)); + SDFF_X1_LVT \registers_reg[7][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_7__ap[17]), .CK(n_0_37), .Q(registers_7__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[14][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_14__ap[17]), .CK(n_0_44), .Q(registers_14__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1029 (.A1(registers_7__ap[17]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[17]), .ZN(n_1_0_979)); + SDFF_X1_LVT \registers_reg[9][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_9__ap[17]), .CK(n_0_39), .Q(registers_9__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[29][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_29__ap[17]), .CK(n_0_59), .Q(registers_29__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1028 (.A1(registers_9__ap[17]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[17]), .ZN(n_1_0_978)); + SDFF_X1_LVT \registers_reg[8][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_8__ap[17]), .CK(n_0_38), .Q(registers_8__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[23][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_23__ap[17]), .CK(n_0_53), .Q(registers_23__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1027 (.A1(registers_8__ap[17]), .A2(n_1_0_1282), .B1( + n_1_0_1264), .B2(registers_23__ap[17]), .ZN(n_1_0_977)); + NAND3_X1_LVT i_1_0_1026 (.A1(n_1_0_979), .A2(n_1_0_978), .A3(n_1_0_977), + .ZN(n_1_0_976)); + SDFF_X1_LVT \registers_reg[27][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_27__ap[17]), .CK(n_0_57), .Q(registers_27__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[3][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_3__ap[17]), .CK(n_0_33), .Q(registers_3__ap[17]), .QN()); + AOI221_X1_LVT i_1_0_1025 (.A(n_1_0_976), .B1(n_1_0_1279), .B2( + registers_27__ap[17]), .C1(registers_3__ap[17]), .C2(n_1_0_1257), .ZN( + n_1_0_975)); + NAND4_X1_LVT i_1_0_1024 (.A1(n_1_0_990), .A2(n_1_0_985), .A3(n_1_0_980), + .A4(n_1_0_975), .ZN(RRs1[17])); + AND2_X1_LVT i_0_0_16 (.A1(n_0_0_16), .A2(WRd[16]), .ZN(registers[16])); + SDFF_X1_LVT \registers_reg[29][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_29__ap[16]), .CK(n_0_59), .Q(registers_29__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[2][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_2__ap[16]), .CK(n_0_32), .Q(registers_2__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1022 (.A1(registers_29__ap[16]), .A2(n_1_0_1276), .B1( + n_1_0_1268), .B2(registers_2__ap[16]), .ZN(n_1_0_973)); + SDFF_X1_LVT \registers_reg[11][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_11__ap[16]), .CK(n_0_41), .Q(registers_11__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[25][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_25__ap[16]), .CK(n_0_55), .Q(registers_25__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1023 (.A1(registers_11__ap[16]), .A2(n_1_0_1270), .B1( + n_1_0_1269), .B2(registers_25__ap[16]), .ZN(n_1_0_974)); + SDFF_X1_LVT \registers_reg[9][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_9__ap[16]), .CK(n_0_39), .Q(registers_9__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[7][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_7__ap[16]), .CK(n_0_37), .Q(registers_7__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1021 (.A1(registers_9__ap[16]), .A2(n_1_0_1291), .B1( + n_1_0_1263), .B2(registers_7__ap[16]), .ZN(n_1_0_972)); + SDFF_X1_LVT \registers_reg[10][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_10__ap[16]), .CK(n_0_40), .Q(registers_10__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[16][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_16__ap[16]), .CK(n_0_46), .Q(registers_16__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1020 (.A1(registers_10__ap[16]), .A2(n_1_0_1287), .B1( + n_1_0_1267), .B2(registers_16__ap[16]), .ZN(n_1_0_971)); + NAND3_X1_LVT i_1_0_1019 (.A1(n_1_0_974), .A2(n_1_0_972), .A3(n_1_0_971), + .ZN(n_1_0_970)); + SDFF_X1_LVT \registers_reg[31][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_31__ap[16]), .CK(n_0_61), .Q(registers_31__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[6][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_6__ap[16]), .CK(n_0_36), .Q(registers_6__ap[16]), .QN()); + AOI221_X1_LVT i_1_0_1018 (.A(n_1_0_970), .B1(n_1_0_1266), .B2( + registers_31__ap[16]), .C1(registers_6__ap[16]), .C2(n_1_0_1300), .ZN( + n_1_0_969)); + SDFF_X1_LVT \registers_reg[18][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_18__ap[16]), .CK(n_0_48), .Q(registers_18__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[22][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_22__ap[16]), .CK(n_0_52), .Q(registers_22__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[1][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_1__ap[16]), .CK(n_0_0), .Q(registers_1__ap[16]), .QN()); + AOI222_X1_LVT i_1_0_1017 (.A1(registers_18__ap[16]), .A2(n_1_0_1297), + .B1(n_1_0_1294), .B2(registers_22__ap[16]), .C1(registers_1__ap[16]), + .C2(n_1_0_1274), .ZN(n_1_0_968)); + NAND3_X1_LVT i_1_0_1016 (.A1(n_1_0_973), .A2(n_1_0_969), .A3(n_1_0_968), + .ZN(n_1_0_967)); + SDFF_X1_LVT \registers_reg[5][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_5__ap[16]), .CK(n_0_35), .Q(registers_5__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[28][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_28__ap[16]), .CK(n_0_58), .Q(registers_28__ap[16]), .QN()); + AOI221_X1_LVT i_1_0_1015 (.A(n_1_0_967), .B1(n_1_0_1273), .B2( + registers_5__ap[16]), .C1(registers_28__ap[16]), .C2(n_1_0_1283), .ZN( + n_1_0_966)); + SDFF_X1_LVT \registers_reg[4][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_4__ap[16]), .CK(n_0_34), .Q(registers_4__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[12][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_12__ap[16]), .CK(n_0_42), .Q(registers_12__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1014 (.A1(registers_4__ap[16]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[16]), .ZN(n_1_0_965)); + SDFF_X1_LVT \registers_reg[19][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_19__ap[16]), .CK(n_0_49), .Q(registers_19__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[21][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_21__ap[16]), .CK(n_0_51), .Q(registers_21__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1013 (.A1(registers_19__ap[16]), .A2(n_1_0_1295), .B1( + n_1_0_1259), .B2(registers_21__ap[16]), .ZN(n_1_0_964)); + SDFF_X1_LVT \registers_reg[24][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_24__ap[16]), .CK(n_0_54), .Q(registers_24__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[20][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_20__ap[16]), .CK(n_0_50), .Q(registers_20__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1012 (.A1(registers_24__ap[16]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[16]), .ZN(n_1_0_963)); + NAND3_X1_LVT i_1_0_1011 (.A1(n_1_0_965), .A2(n_1_0_964), .A3(n_1_0_963), + .ZN(n_1_0_962)); + SDFF_X1_LVT \registers_reg[26][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_26__ap[16]), .CK(n_0_56), .Q(registers_26__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[30][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_30__ap[16]), .CK(n_0_60), .Q(registers_30__ap[16]), .QN()); + AOI221_X1_LVT i_1_0_1010 (.A(n_1_0_962), .B1(n_1_0_1285), .B2( + registers_26__ap[16]), .C1(registers_30__ap[16]), .C2(n_1_0_1272), + .ZN(n_1_0_961)); + SDFF_X1_LVT \registers_reg[8][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_8__ap[16]), .CK(n_0_38), .Q(registers_8__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[23][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_23__ap[16]), .CK(n_0_53), .Q(registers_23__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1009 (.A1(registers_8__ap[16]), .A2(n_1_0_1282), .B1( + n_1_0_1264), .B2(registers_23__ap[16]), .ZN(n_1_0_960)); + SDFF_X1_LVT \registers_reg[13][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_13__ap[16]), .CK(n_0_43), .Q(registers_13__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[17][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_17__ap[16]), .CK(n_0_47), .Q(registers_17__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1008 (.A1(registers_13__ap[16]), .A2(n_1_0_1277), .B1( + n_1_0_1271), .B2(registers_17__ap[16]), .ZN(n_1_0_959)); + SDFF_X1_LVT \registers_reg[15][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_15__ap[16]), .CK(n_0_45), .Q(registers_15__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[14][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_14__ap[16]), .CK(n_0_44), .Q(registers_14__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1007 (.A1(registers_15__ap[16]), .A2(n_1_0_1286), .B1( + n_1_0_1258), .B2(registers_14__ap[16]), .ZN(n_1_0_958)); + NAND3_X1_LVT i_1_0_1006 (.A1(n_1_0_960), .A2(n_1_0_959), .A3(n_1_0_958), + .ZN(n_1_0_957)); + SDFF_X1_LVT \registers_reg[27][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_27__ap[16]), .CK(n_0_57), .Q(registers_27__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[3][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_3__ap[16]), .CK(n_0_33), .Q(registers_3__ap[16]), .QN()); + AOI221_X1_LVT i_1_0_1005 (.A(n_1_0_957), .B1(n_1_0_1279), .B2( + registers_27__ap[16]), .C1(registers_3__ap[16]), .C2(n_1_0_1257), .ZN( + n_1_0_956)); + NAND3_X1_LVT i_1_0_1004 (.A1(n_1_0_966), .A2(n_1_0_961), .A3(n_1_0_956), + .ZN(RRs1[16])); + AND2_X1_LVT i_0_0_15 (.A1(n_0_0_16), .A2(WRd[15]), .ZN(registers[15])); + SDFF_X1_LVT \registers_reg[17][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_17__ap[15]), .CK(n_0_47), .Q(registers_17__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[21][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_21__ap[15]), .CK(n_0_51), .Q(registers_21__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_1000 (.A1(registers_17__ap[15]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[15]), .ZN(n_1_0_952)); + SDFF_X1_LVT \registers_reg[10][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_10__ap[15]), .CK(n_0_40), .Q(registers_10__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[2][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_2__ap[15]), .CK(n_0_32), .Q(registers_2__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_1003 (.A1(registers_10__ap[15]), .A2(n_1_0_1287), .B1( + n_1_0_1268), .B2(registers_2__ap[15]), .ZN(n_1_0_955)); + SDFF_X1_LVT \registers_reg[20][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_20__ap[15]), .CK(n_0_50), .Q(registers_20__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[12][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_12__ap[15]), .CK(n_0_42), .Q(registers_12__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_999 (.A1(registers_20__ap[15]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[15]), .ZN(n_1_0_951)); + SDFF_X1_LVT \registers_reg[15][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_15__ap[15]), .CK(n_0_45), .Q(registers_15__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[8][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_8__ap[15]), .CK(n_0_38), .Q(registers_8__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_1002 (.A1(registers_15__ap[15]), .A2(n_1_0_1286), .B1( + n_1_0_1282), .B2(registers_8__ap[15]), .ZN(n_1_0_954)); + INV_X1_LVT i_1_0_1001 (.A(n_1_0_954), .ZN(n_1_0_953)); + SDFF_X1_LVT \registers_reg[11][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_11__ap[15]), .CK(n_0_41), .Q(registers_11__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[24][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_24__ap[15]), .CK(n_0_54), .Q(registers_24__ap[15]), .QN()); + AOI221_X1_LVT i_1_0_998 (.A(n_1_0_953), .B1(n_1_0_1270), .B2( + registers_11__ap[15]), .C1(registers_24__ap[15]), .C2(n_1_0_1289), + .ZN(n_1_0_950)); + SDFF_X1_LVT \registers_reg[13][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_13__ap[15]), .CK(n_0_43), .Q(registers_13__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[30][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_30__ap[15]), .CK(n_0_60), .Q(registers_30__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[22][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_22__ap[15]), .CK(n_0_52), .Q(registers_22__ap[15]), .QN()); + AOI222_X1_LVT i_1_0_997 (.A1(registers_13__ap[15]), .A2(n_1_0_1277), .B1( + n_1_0_1272), .B2(registers_30__ap[15]), .C1(registers_22__ap[15]), + .C2(n_1_0_1294), .ZN(n_1_0_949)); + NAND4_X1_LVT i_1_0_996 (.A1(n_1_0_955), .A2(n_1_0_951), .A3(n_1_0_950), + .A4(n_1_0_949), .ZN(n_1_0_948)); + SDFF_X1_LVT \registers_reg[1][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_1__ap[15]), .CK(n_0_0), .Q(registers_1__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[28][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_28__ap[15]), .CK(n_0_58), .Q(registers_28__ap[15]), .QN()); + AOI221_X1_LVT i_1_0_995 (.A(n_1_0_948), .B1(n_1_0_1274), .B2( + registers_1__ap[15]), .C1(registers_28__ap[15]), .C2(n_1_0_1283), .ZN( + n_1_0_947)); + SDFF_X1_LVT \registers_reg[18][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_18__ap[15]), .CK(n_0_48), .Q(registers_18__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[26][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_26__ap[15]), .CK(n_0_56), .Q(registers_26__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_994 (.A1(registers_18__ap[15]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[15]), .ZN(n_1_0_946)); + SDFF_X1_LVT \registers_reg[4][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_4__ap[15]), .CK(n_0_34), .Q(registers_4__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[5][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_5__ap[15]), .CK(n_0_35), .Q(registers_5__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_993 (.A1(registers_4__ap[15]), .A2(n_1_0_1278), .B1( + n_1_0_1273), .B2(registers_5__ap[15]), .ZN(n_1_0_945)); + SDFF_X1_LVT \registers_reg[6][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_6__ap[15]), .CK(n_0_36), .Q(registers_6__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[16][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_16__ap[15]), .CK(n_0_46), .Q(registers_16__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_992 (.A1(registers_6__ap[15]), .A2(n_1_0_1300), .B1( + n_1_0_1267), .B2(registers_16__ap[15]), .ZN(n_1_0_944)); + NAND3_X1_LVT i_1_0_991 (.A1(n_1_0_946), .A2(n_1_0_945), .A3(n_1_0_944), + .ZN(n_1_0_943)); + SDFF_X1_LVT \registers_reg[19][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_19__ap[15]), .CK(n_0_49), .Q(registers_19__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[25][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_25__ap[15]), .CK(n_0_55), .Q(registers_25__ap[15]), .QN()); + AOI221_X1_LVT i_1_0_990 (.A(n_1_0_943), .B1(n_1_0_1295), .B2( + registers_19__ap[15]), .C1(registers_25__ap[15]), .C2(n_1_0_1269), + .ZN(n_1_0_942)); + SDFF_X1_LVT \registers_reg[7][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_7__ap[15]), .CK(n_0_37), .Q(registers_7__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[14][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_14__ap[15]), .CK(n_0_44), .Q(registers_14__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_989 (.A1(registers_7__ap[15]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[15]), .ZN(n_1_0_941)); + SDFF_X1_LVT \registers_reg[9][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_9__ap[15]), .CK(n_0_39), .Q(registers_9__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[29][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_29__ap[15]), .CK(n_0_59), .Q(registers_29__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_988 (.A1(registers_9__ap[15]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[15]), .ZN(n_1_0_940)); + SDFF_X1_LVT \registers_reg[23][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_23__ap[15]), .CK(n_0_53), .Q(registers_23__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[3][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_3__ap[15]), .CK(n_0_33), .Q(registers_3__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_987 (.A1(registers_23__ap[15]), .A2(n_1_0_1264), .B1( + n_1_0_1257), .B2(registers_3__ap[15]), .ZN(n_1_0_939)); + NAND3_X1_LVT i_1_0_986 (.A1(n_1_0_941), .A2(n_1_0_940), .A3(n_1_0_939), + .ZN(n_1_0_938)); + SDFF_X1_LVT \registers_reg[27][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_27__ap[15]), .CK(n_0_57), .Q(registers_27__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[31][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_31__ap[15]), .CK(n_0_61), .Q(registers_31__ap[15]), .QN()); + AOI221_X1_LVT i_1_0_985 (.A(n_1_0_938), .B1(n_1_0_1279), .B2( + registers_27__ap[15]), .C1(registers_31__ap[15]), .C2(n_1_0_1266), + .ZN(n_1_0_937)); + NAND4_X1_LVT i_1_0_984 (.A1(n_1_0_952), .A2(n_1_0_947), .A3(n_1_0_942), + .A4(n_1_0_937), .ZN(RRs1[15])); + AND2_X1_LVT i_0_0_14 (.A1(n_0_0_16), .A2(WRd[14]), .ZN(registers[14])); + SDFF_X1_LVT \registers_reg[28][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_28__ap[14]), .CK(n_0_58), .Q(registers_28__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[5][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_5__ap[14]), .CK(n_0_35), .Q(registers_5__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_983 (.A1(registers_28__ap[14]), .A2(n_1_0_1283), .B1( + n_1_0_1273), .B2(registers_5__ap[14]), .ZN(n_1_0_936)); + SDFF_X1_LVT \registers_reg[18][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_18__ap[14]), .CK(n_0_48), .Q(registers_18__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[10][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_10__ap[14]), .CK(n_0_40), .Q(registers_10__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[8][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_8__ap[14]), .CK(n_0_38), .Q(registers_8__ap[14]), .QN()); + AOI222_X1_LVT i_1_0_982 (.A1(registers_18__ap[14]), .A2(n_1_0_1297), .B1( + n_1_0_1287), .B2(registers_10__ap[14]), .C1(n_1_0_1282), .C2( + registers_8__ap[14]), .ZN(n_1_0_935)); + SDFF_X1_LVT \registers_reg[9][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_9__ap[14]), .CK(n_0_39), .Q(registers_9__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[29][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_29__ap[14]), .CK(n_0_59), .Q(registers_29__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_981 (.A1(registers_9__ap[14]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[14]), .ZN(n_1_0_934)); + SDFF_X1_LVT \registers_reg[21][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_21__ap[14]), .CK(n_0_51), .Q(registers_21__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[14][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_14__ap[14]), .CK(n_0_44), .Q(registers_14__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_980 (.A1(registers_21__ap[14]), .A2(n_1_0_1259), .B1( + n_1_0_1258), .B2(registers_14__ap[14]), .ZN(n_1_0_933)); + SDFF_X1_LVT \registers_reg[16][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_16__ap[14]), .CK(n_0_46), .Q(registers_16__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[3][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_3__ap[14]), .CK(n_0_33), .Q(registers_3__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_979 (.A1(registers_16__ap[14]), .A2(n_1_0_1267), .B1( + n_1_0_1257), .B2(registers_3__ap[14]), .ZN(n_1_0_932)); + SDFF_X1_LVT \registers_reg[17][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_17__ap[14]), .CK(n_0_47), .Q(registers_17__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[31][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_31__ap[14]), .CK(n_0_61), .Q(registers_31__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_978 (.A1(registers_17__ap[14]), .A2(n_1_0_1271), .B1( + n_1_0_1266), .B2(registers_31__ap[14]), .ZN(n_1_0_931)); + SDFF_X1_LVT \registers_reg[15][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_15__ap[14]), .CK(n_0_45), .Q(registers_15__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[23][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_23__ap[14]), .CK(n_0_53), .Q(registers_23__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_977 (.A1(registers_15__ap[14]), .A2(n_1_0_1286), .B1( + n_1_0_1264), .B2(registers_23__ap[14]), .ZN(n_1_0_930)); + NAND4_X1_LVT i_1_0_976 (.A1(n_1_0_933), .A2(n_1_0_932), .A3(n_1_0_931), + .A4(n_1_0_930), .ZN(n_1_0_929)); + SDFF_X1_LVT \registers_reg[26][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_26__ap[14]), .CK(n_0_56), .Q(registers_26__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[30][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_30__ap[14]), .CK(n_0_60), .Q(registers_30__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_975 (.A1(registers_26__ap[14]), .A2(n_1_0_1285), .B1( + n_1_0_1272), .B2(registers_30__ap[14]), .ZN(n_1_0_928)); + SDFF_X1_LVT \registers_reg[20][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_20__ap[14]), .CK(n_0_50), .Q(registers_20__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[4][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_4__ap[14]), .CK(n_0_34), .Q(registers_4__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_974 (.A1(registers_20__ap[14]), .A2(n_1_0_1281), .B1( + n_1_0_1278), .B2(registers_4__ap[14]), .ZN(n_1_0_927)); + SDFF_X1_LVT \registers_reg[1][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_1__ap[14]), .CK(n_0_0), .Q(registers_1__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[2][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_2__ap[14]), .CK(n_0_32), .Q(registers_2__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_973 (.A1(registers_1__ap[14]), .A2(n_1_0_1274), .B1( + n_1_0_1268), .B2(registers_2__ap[14]), .ZN(n_1_0_926)); + SDFF_X1_LVT \registers_reg[24][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_24__ap[14]), .CK(n_0_54), .Q(registers_24__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[12][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_12__ap[14]), .CK(n_0_42), .Q(registers_12__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_972 (.A1(registers_24__ap[14]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[14]), .ZN(n_1_0_925)); + NAND4_X1_LVT i_1_0_971 (.A1(n_1_0_928), .A2(n_1_0_927), .A3(n_1_0_926), + .A4(n_1_0_925), .ZN(n_1_0_924)); + SDFF_X1_LVT \registers_reg[19][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_19__ap[14]), .CK(n_0_49), .Q(registers_19__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[22][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_22__ap[14]), .CK(n_0_52), .Q(registers_22__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_970 (.A1(registers_19__ap[14]), .A2(n_1_0_1295), .B1( + n_1_0_1294), .B2(registers_22__ap[14]), .ZN(n_1_0_923)); + SDFF_X1_LVT \registers_reg[13][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_13__ap[14]), .CK(n_0_43), .Q(registers_13__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[25][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_25__ap[14]), .CK(n_0_55), .Q(registers_25__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_969 (.A1(registers_13__ap[14]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[14]), .ZN(n_1_0_922)); + SDFF_X1_LVT \registers_reg[6][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_6__ap[14]), .CK(n_0_36), .Q(registers_6__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[7][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_7__ap[14]), .CK(n_0_37), .Q(registers_7__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_968 (.A1(registers_6__ap[14]), .A2(n_1_0_1300), .B1( + n_1_0_1263), .B2(registers_7__ap[14]), .ZN(n_1_0_921)); + SDFF_X1_LVT \registers_reg[27][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_27__ap[14]), .CK(n_0_57), .Q(registers_27__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[11][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_11__ap[14]), .CK(n_0_41), .Q(registers_11__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_967 (.A1(registers_27__ap[14]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[14]), .ZN(n_1_0_920)); + NAND4_X1_LVT i_1_0_966 (.A1(n_1_0_923), .A2(n_1_0_922), .A3(n_1_0_921), + .A4(n_1_0_920), .ZN(n_1_0_919)); + NOR3_X1_LVT i_1_0_965 (.A1(n_1_0_929), .A2(n_1_0_924), .A3(n_1_0_919), + .ZN(n_1_0_918)); + NAND4_X1_LVT i_1_0_964 (.A1(n_1_0_936), .A2(n_1_0_935), .A3(n_1_0_934), + .A4(n_1_0_918), .ZN(RRs1[14])); + AND2_X1_LVT i_0_0_13 (.A1(n_0_0_16), .A2(WRd[13]), .ZN(registers[13])); + SDFF_X1_LVT \registers_reg[28][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_28__ap[13]), .CK(n_0_58), .Q(registers_28__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[4][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_4__ap[13]), .CK(n_0_34), .Q(registers_4__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_963 (.A1(registers_28__ap[13]), .A2(n_1_0_1283), .B1( + n_1_0_1278), .B2(registers_4__ap[13]), .ZN(n_1_0_917)); + SDFF_X1_LVT \registers_reg[10][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_10__ap[13]), .CK(n_0_40), .Q(registers_10__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[26][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_26__ap[13]), .CK(n_0_56), .Q(registers_26__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[8][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_8__ap[13]), .CK(n_0_38), .Q(registers_8__ap[13]), .QN()); + AOI222_X1_LVT i_1_0_962 (.A1(registers_10__ap[13]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[13]), .C1(registers_8__ap[13]), .C2( + n_1_0_1282), .ZN(n_1_0_916)); + SDFF_X1_LVT \registers_reg[9][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_9__ap[13]), .CK(n_0_39), .Q(registers_9__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[29][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_29__ap[13]), .CK(n_0_59), .Q(registers_29__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_961 (.A1(registers_9__ap[13]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[13]), .ZN(n_1_0_915)); + SDFF_X1_LVT \registers_reg[6][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_6__ap[13]), .CK(n_0_36), .Q(registers_6__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[1][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_1__ap[13]), .CK(n_0_0), .Q(registers_1__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_960 (.A1(registers_6__ap[13]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[13]), .ZN(n_1_0_914)); + SDFF_X1_LVT \registers_reg[5][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_5__ap[13]), .CK(n_0_35), .Q(registers_5__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[3][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_3__ap[13]), .CK(n_0_33), .Q(registers_3__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_959 (.A1(registers_5__ap[13]), .A2(n_1_0_1273), .B1( + n_1_0_1257), .B2(registers_3__ap[13]), .ZN(n_1_0_913)); + SDFF_X1_LVT \registers_reg[16][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_16__ap[13]), .CK(n_0_46), .Q(registers_16__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[31][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_31__ap[13]), .CK(n_0_61), .Q(registers_31__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_958 (.A1(registers_16__ap[13]), .A2(n_1_0_1267), .B1( + n_1_0_1266), .B2(registers_31__ap[13]), .ZN(n_1_0_912)); + SDFF_X1_LVT \registers_reg[15][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_15__ap[13]), .CK(n_0_45), .Q(registers_15__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[23][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_23__ap[13]), .CK(n_0_53), .Q(registers_23__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_957 (.A1(registers_15__ap[13]), .A2(n_1_0_1286), .B1( + n_1_0_1264), .B2(registers_23__ap[13]), .ZN(n_1_0_911)); + NAND4_X1_LVT i_1_0_956 (.A1(n_1_0_914), .A2(n_1_0_913), .A3(n_1_0_912), + .A4(n_1_0_911), .ZN(n_1_0_910)); + SDFF_X1_LVT \registers_reg[18][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_18__ap[13]), .CK(n_0_48), .Q(registers_18__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[30][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_30__ap[13]), .CK(n_0_60), .Q(registers_30__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_955 (.A1(registers_18__ap[13]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[13]), .ZN(n_1_0_909)); + SDFF_X1_LVT \registers_reg[24][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_24__ap[13]), .CK(n_0_54), .Q(registers_24__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[12][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_12__ap[13]), .CK(n_0_42), .Q(registers_12__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_954 (.A1(registers_24__ap[13]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[13]), .ZN(n_1_0_908)); + SDFF_X1_LVT \registers_reg[22][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_22__ap[13]), .CK(n_0_52), .Q(registers_22__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[21][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_21__ap[13]), .CK(n_0_51), .Q(registers_21__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_953 (.A1(registers_22__ap[13]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[13]), .ZN(n_1_0_907)); + SDFF_X1_LVT \registers_reg[20][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_20__ap[13]), .CK(n_0_50), .Q(registers_20__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[17][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_17__ap[13]), .CK(n_0_47), .Q(registers_17__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_952 (.A1(registers_20__ap[13]), .A2(n_1_0_1281), .B1( + n_1_0_1271), .B2(registers_17__ap[13]), .ZN(n_1_0_906)); + NAND4_X1_LVT i_1_0_951 (.A1(n_1_0_909), .A2(n_1_0_908), .A3(n_1_0_907), + .A4(n_1_0_906), .ZN(n_1_0_905)); + SDFF_X1_LVT \registers_reg[13][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_13__ap[13]), .CK(n_0_43), .Q(registers_13__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[25][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_25__ap[13]), .CK(n_0_55), .Q(registers_25__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_950 (.A1(registers_13__ap[13]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[13]), .ZN(n_1_0_904)); + SDFF_X1_LVT \registers_reg[19][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_19__ap[13]), .CK(n_0_49), .Q(registers_19__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[2][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_2__ap[13]), .CK(n_0_32), .Q(registers_2__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_949 (.A1(registers_19__ap[13]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[13]), .ZN(n_1_0_903)); + SDFF_X1_LVT \registers_reg[7][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_7__ap[13]), .CK(n_0_37), .Q(registers_7__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[14][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_14__ap[13]), .CK(n_0_44), .Q(registers_14__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_948 (.A1(registers_7__ap[13]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[13]), .ZN(n_1_0_902)); + SDFF_X1_LVT \registers_reg[27][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_27__ap[13]), .CK(n_0_57), .Q(registers_27__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[11][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_11__ap[13]), .CK(n_0_41), .Q(registers_11__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_947 (.A1(registers_27__ap[13]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[13]), .ZN(n_1_0_901)); + NAND4_X1_LVT i_1_0_946 (.A1(n_1_0_904), .A2(n_1_0_903), .A3(n_1_0_902), + .A4(n_1_0_901), .ZN(n_1_0_900)); + NOR3_X1_LVT i_1_0_945 (.A1(n_1_0_910), .A2(n_1_0_905), .A3(n_1_0_900), + .ZN(n_1_0_899)); + NAND4_X1_LVT i_1_0_944 (.A1(n_1_0_917), .A2(n_1_0_916), .A3(n_1_0_915), + .A4(n_1_0_899), .ZN(RRs1[13])); + AND2_X1_LVT i_0_0_12 (.A1(n_0_0_16), .A2(WRd[12]), .ZN(registers[12])); + SDFF_X1_LVT \registers_reg[28][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_28__ap[12]), .CK(n_0_58), .Q(registers_28__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[17][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_17__ap[12]), .CK(n_0_47), .Q(registers_17__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_943 (.A1(registers_28__ap[12]), .A2(n_1_0_1283), .B1( + n_1_0_1271), .B2(registers_17__ap[12]), .ZN(n_1_0_898)); + SDFF_X1_LVT \registers_reg[10][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_10__ap[12]), .CK(n_0_40), .Q(registers_10__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[26][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_26__ap[12]), .CK(n_0_56), .Q(registers_26__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[8][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_8__ap[12]), .CK(n_0_38), .Q(registers_8__ap[12]), .QN()); + AOI222_X1_LVT i_1_0_942 (.A1(registers_10__ap[12]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[12]), .C1(registers_8__ap[12]), .C2( + n_1_0_1282), .ZN(n_1_0_897)); + SDFF_X1_LVT \registers_reg[9][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_9__ap[12]), .CK(n_0_39), .Q(registers_9__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[29][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_29__ap[12]), .CK(n_0_59), .Q(registers_29__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_941 (.A1(registers_9__ap[12]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[12]), .ZN(n_1_0_896)); + SDFF_X1_LVT \registers_reg[6][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_6__ap[12]), .CK(n_0_36), .Q(registers_6__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[1][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_1__ap[12]), .CK(n_0_0), .Q(registers_1__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_940 (.A1(registers_6__ap[12]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[12]), .ZN(n_1_0_895)); + SDFF_X1_LVT \registers_reg[16][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_16__ap[12]), .CK(n_0_46), .Q(registers_16__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[3][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_3__ap[12]), .CK(n_0_33), .Q(registers_3__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_939 (.A1(registers_16__ap[12]), .A2(n_1_0_1267), .B1( + n_1_0_1257), .B2(registers_3__ap[12]), .ZN(n_1_0_894)); + SDFF_X1_LVT \registers_reg[5][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_5__ap[12]), .CK(n_0_35), .Q(registers_5__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[31][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_31__ap[12]), .CK(n_0_61), .Q(registers_31__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_938 (.A1(registers_5__ap[12]), .A2(n_1_0_1273), .B1( + n_1_0_1266), .B2(registers_31__ap[12]), .ZN(n_1_0_893)); + SDFF_X1_LVT \registers_reg[15][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_15__ap[12]), .CK(n_0_45), .Q(registers_15__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[23][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_23__ap[12]), .CK(n_0_53), .Q(registers_23__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_937 (.A1(registers_15__ap[12]), .A2(n_1_0_1286), .B1( + n_1_0_1264), .B2(registers_23__ap[12]), .ZN(n_1_0_892)); + NAND4_X1_LVT i_1_0_936 (.A1(n_1_0_895), .A2(n_1_0_894), .A3(n_1_0_893), + .A4(n_1_0_892), .ZN(n_1_0_891)); + SDFF_X1_LVT \registers_reg[18][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_18__ap[12]), .CK(n_0_48), .Q(registers_18__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[30][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_30__ap[12]), .CK(n_0_60), .Q(registers_30__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_935 (.A1(registers_18__ap[12]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[12]), .ZN(n_1_0_890)); + SDFF_X1_LVT \registers_reg[20][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_20__ap[12]), .CK(n_0_50), .Q(registers_20__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[4][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_4__ap[12]), .CK(n_0_34), .Q(registers_4__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_934 (.A1(registers_20__ap[12]), .A2(n_1_0_1281), .B1( + n_1_0_1278), .B2(registers_4__ap[12]), .ZN(n_1_0_889)); + SDFF_X1_LVT \registers_reg[22][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_22__ap[12]), .CK(n_0_52), .Q(registers_22__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[21][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_21__ap[12]), .CK(n_0_51), .Q(registers_21__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_933 (.A1(registers_22__ap[12]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[12]), .ZN(n_1_0_888)); + SDFF_X1_LVT \registers_reg[24][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_24__ap[12]), .CK(n_0_54), .Q(registers_24__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[12][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_12__ap[12]), .CK(n_0_42), .Q(registers_12__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_932 (.A1(registers_24__ap[12]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[12]), .ZN(n_1_0_887)); + NAND4_X1_LVT i_1_0_931 (.A1(n_1_0_890), .A2(n_1_0_889), .A3(n_1_0_888), + .A4(n_1_0_887), .ZN(n_1_0_886)); + SDFF_X1_LVT \registers_reg[13][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_13__ap[12]), .CK(n_0_43), .Q(registers_13__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[25][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_25__ap[12]), .CK(n_0_55), .Q(registers_25__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_930 (.A1(registers_13__ap[12]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[12]), .ZN(n_1_0_885)); + SDFF_X1_LVT \registers_reg[19][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_19__ap[12]), .CK(n_0_49), .Q(registers_19__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[2][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_2__ap[12]), .CK(n_0_32), .Q(registers_2__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_929 (.A1(registers_19__ap[12]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[12]), .ZN(n_1_0_884)); + SDFF_X1_LVT \registers_reg[7][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_7__ap[12]), .CK(n_0_37), .Q(registers_7__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[14][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_14__ap[12]), .CK(n_0_44), .Q(registers_14__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_928 (.A1(registers_7__ap[12]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[12]), .ZN(n_1_0_883)); + SDFF_X1_LVT \registers_reg[27][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_27__ap[12]), .CK(n_0_57), .Q(registers_27__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[11][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_11__ap[12]), .CK(n_0_41), .Q(registers_11__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_927 (.A1(registers_27__ap[12]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[12]), .ZN(n_1_0_882)); + NAND4_X1_LVT i_1_0_926 (.A1(n_1_0_885), .A2(n_1_0_884), .A3(n_1_0_883), + .A4(n_1_0_882), .ZN(n_1_0_881)); + NOR3_X1_LVT i_1_0_925 (.A1(n_1_0_891), .A2(n_1_0_886), .A3(n_1_0_881), + .ZN(n_1_0_880)); + NAND4_X1_LVT i_1_0_924 (.A1(n_1_0_898), .A2(n_1_0_897), .A3(n_1_0_896), + .A4(n_1_0_880), .ZN(RRs1[12])); + AND2_X1_LVT i_0_0_11 (.A1(n_0_0_16), .A2(WRd[11]), .ZN(registers[11])); + SDFF_X1_LVT \registers_reg[28][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_28__ap[11]), .CK(n_0_58), .Q(registers_28__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[17][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_17__ap[11]), .CK(n_0_47), .Q(registers_17__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_923 (.A1(registers_28__ap[11]), .A2(n_1_0_1283), .B1( + n_1_0_1271), .B2(registers_17__ap[11]), .ZN(n_1_0_879)); + SDFF_X1_LVT \registers_reg[10][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_10__ap[11]), .CK(n_0_40), .Q(registers_10__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[26][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_26__ap[11]), .CK(n_0_56), .Q(registers_26__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[8][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_8__ap[11]), .CK(n_0_38), .Q(registers_8__ap[11]), .QN()); + AOI222_X1_LVT i_1_0_922 (.A1(registers_10__ap[11]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[11]), .C1(registers_8__ap[11]), .C2( + n_1_0_1282), .ZN(n_1_0_878)); + SDFF_X1_LVT \registers_reg[9][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_9__ap[11]), .CK(n_0_39), .Q(registers_9__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[29][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_29__ap[11]), .CK(n_0_59), .Q(registers_29__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_921 (.A1(registers_9__ap[11]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[11]), .ZN(n_1_0_877)); + SDFF_X1_LVT \registers_reg[6][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_6__ap[11]), .CK(n_0_36), .Q(registers_6__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[1][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_1__ap[11]), .CK(n_0_0), .Q(registers_1__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_920 (.A1(registers_6__ap[11]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[11]), .ZN(n_1_0_876)); + SDFF_X1_LVT \registers_reg[5][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_5__ap[11]), .CK(n_0_35), .Q(registers_5__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[3][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_3__ap[11]), .CK(n_0_33), .Q(registers_3__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_919 (.A1(registers_5__ap[11]), .A2(n_1_0_1273), .B1( + n_1_0_1257), .B2(registers_3__ap[11]), .ZN(n_1_0_875)); + SDFF_X1_LVT \registers_reg[16][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_16__ap[11]), .CK(n_0_46), .Q(registers_16__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[31][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_31__ap[11]), .CK(n_0_61), .Q(registers_31__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_918 (.A1(registers_16__ap[11]), .A2(n_1_0_1267), .B1( + n_1_0_1266), .B2(registers_31__ap[11]), .ZN(n_1_0_874)); + SDFF_X1_LVT \registers_reg[15][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_15__ap[11]), .CK(n_0_45), .Q(registers_15__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[23][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_23__ap[11]), .CK(n_0_53), .Q(registers_23__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_917 (.A1(registers_15__ap[11]), .A2(n_1_0_1286), .B1( + n_1_0_1264), .B2(registers_23__ap[11]), .ZN(n_1_0_873)); + NAND4_X1_LVT i_1_0_916 (.A1(n_1_0_876), .A2(n_1_0_875), .A3(n_1_0_874), + .A4(n_1_0_873), .ZN(n_1_0_872)); + SDFF_X1_LVT \registers_reg[18][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_18__ap[11]), .CK(n_0_48), .Q(registers_18__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[30][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_30__ap[11]), .CK(n_0_60), .Q(registers_30__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_915 (.A1(registers_18__ap[11]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[11]), .ZN(n_1_0_871)); + SDFF_X1_LVT \registers_reg[20][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_20__ap[11]), .CK(n_0_50), .Q(registers_20__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[4][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_4__ap[11]), .CK(n_0_34), .Q(registers_4__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_914 (.A1(registers_20__ap[11]), .A2(n_1_0_1281), .B1( + n_1_0_1278), .B2(registers_4__ap[11]), .ZN(n_1_0_870)); + SDFF_X1_LVT \registers_reg[22][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_22__ap[11]), .CK(n_0_52), .Q(registers_22__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[21][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_21__ap[11]), .CK(n_0_51), .Q(registers_21__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_913 (.A1(registers_22__ap[11]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[11]), .ZN(n_1_0_869)); + SDFF_X1_LVT \registers_reg[24][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_24__ap[11]), .CK(n_0_54), .Q(registers_24__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[12][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_12__ap[11]), .CK(n_0_42), .Q(registers_12__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_912 (.A1(registers_24__ap[11]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[11]), .ZN(n_1_0_868)); + NAND4_X1_LVT i_1_0_911 (.A1(n_1_0_871), .A2(n_1_0_870), .A3(n_1_0_869), + .A4(n_1_0_868), .ZN(n_1_0_867)); + SDFF_X1_LVT \registers_reg[13][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_13__ap[11]), .CK(n_0_43), .Q(registers_13__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[25][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_25__ap[11]), .CK(n_0_55), .Q(registers_25__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_910 (.A1(registers_13__ap[11]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[11]), .ZN(n_1_0_866)); + SDFF_X1_LVT \registers_reg[19][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_19__ap[11]), .CK(n_0_49), .Q(registers_19__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[2][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_2__ap[11]), .CK(n_0_32), .Q(registers_2__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_909 (.A1(registers_19__ap[11]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[11]), .ZN(n_1_0_865)); + SDFF_X1_LVT \registers_reg[7][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_7__ap[11]), .CK(n_0_37), .Q(registers_7__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[14][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_14__ap[11]), .CK(n_0_44), .Q(registers_14__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_908 (.A1(registers_7__ap[11]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[11]), .ZN(n_1_0_864)); + SDFF_X1_LVT \registers_reg[27][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_27__ap[11]), .CK(n_0_57), .Q(registers_27__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[11][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_11__ap[11]), .CK(n_0_41), .Q(registers_11__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_907 (.A1(registers_27__ap[11]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[11]), .ZN(n_1_0_863)); + NAND4_X1_LVT i_1_0_906 (.A1(n_1_0_866), .A2(n_1_0_865), .A3(n_1_0_864), + .A4(n_1_0_863), .ZN(n_1_0_862)); + NOR3_X1_LVT i_1_0_905 (.A1(n_1_0_872), .A2(n_1_0_867), .A3(n_1_0_862), + .ZN(n_1_0_861)); + NAND4_X1_LVT i_1_0_904 (.A1(n_1_0_879), .A2(n_1_0_878), .A3(n_1_0_877), + .A4(n_1_0_861), .ZN(RRs1[11])); + AND2_X1_LVT i_0_0_10 (.A1(n_0_0_16), .A2(WRd[10]), .ZN(registers[10])); + SDFF_X1_LVT \registers_reg[28][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_28__ap[10]), .CK(n_0_58), .Q(registers_28__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[8][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_8__ap[10]), .CK(n_0_38), .Q(registers_8__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_902 (.A1(registers_28__ap[10]), .A2(n_1_0_1283), .B1( + n_1_0_1282), .B2(registers_8__ap[10]), .ZN(n_1_0_859)); + SDFF_X1_LVT \registers_reg[31][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_31__ap[10]), .CK(n_0_61), .Q(registers_31__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[7][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_7__ap[10]), .CK(n_0_37), .Q(registers_7__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_903 (.A1(registers_31__ap[10]), .A2(n_1_0_1266), .B1( + n_1_0_1263), .B2(registers_7__ap[10]), .ZN(n_1_0_860)); + SDFF_X1_LVT \registers_reg[24][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_24__ap[10]), .CK(n_0_54), .Q(registers_24__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[20][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_20__ap[10]), .CK(n_0_50), .Q(registers_20__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_901 (.A1(registers_24__ap[10]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[10]), .ZN(n_1_0_858)); + SDFF_X1_LVT \registers_reg[4][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_4__ap[10]), .CK(n_0_34), .Q(registers_4__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[23][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_23__ap[10]), .CK(n_0_53), .Q(registers_23__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_900 (.A1(registers_4__ap[10]), .A2(n_1_0_1278), .B1( + n_1_0_1264), .B2(registers_23__ap[10]), .ZN(n_1_0_857)); + NAND3_X1_LVT i_1_0_899 (.A1(n_1_0_860), .A2(n_1_0_858), .A3(n_1_0_857), + .ZN(n_1_0_856)); + SDFF_X1_LVT \registers_reg[27][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_27__ap[10]), .CK(n_0_57), .Q(registers_27__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[29][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_29__ap[10]), .CK(n_0_59), .Q(registers_29__ap[10]), .QN()); + AOI221_X1_LVT i_1_0_898 (.A(n_1_0_856), .B1(n_1_0_1279), .B2( + registers_27__ap[10]), .C1(registers_29__ap[10]), .C2(n_1_0_1276), + .ZN(n_1_0_855)); + SDFF_X1_LVT \registers_reg[10][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_10__ap[10]), .CK(n_0_40), .Q(registers_10__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[30][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_30__ap[10]), .CK(n_0_60), .Q(registers_30__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[25][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_25__ap[10]), .CK(n_0_55), .Q(registers_25__ap[10]), .QN()); + AOI222_X1_LVT i_1_0_897 (.A1(registers_10__ap[10]), .A2(n_1_0_1287), .B1( + n_1_0_1272), .B2(registers_30__ap[10]), .C1(n_1_0_1269), .C2( + registers_25__ap[10]), .ZN(n_1_0_854)); + NAND3_X1_LVT i_1_0_896 (.A1(n_1_0_859), .A2(n_1_0_855), .A3(n_1_0_854), + .ZN(n_1_0_853)); + SDFF_X1_LVT \registers_reg[21][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_21__ap[10]), .CK(n_0_51), .Q(registers_21__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[13][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_13__ap[10]), .CK(n_0_43), .Q(registers_13__ap[10]), .QN()); + AOI221_X1_LVT i_1_0_895 (.A(n_1_0_853), .B1(n_1_0_1259), .B2( + registers_21__ap[10]), .C1(registers_13__ap[10]), .C2(n_1_0_1277), + .ZN(n_1_0_852)); + SDFF_X1_LVT \registers_reg[18][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_18__ap[10]), .CK(n_0_48), .Q(registers_18__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[26][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_26__ap[10]), .CK(n_0_56), .Q(registers_26__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_894 (.A1(registers_18__ap[10]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[10]), .ZN(n_1_0_851)); + SDFF_X1_LVT \registers_reg[17][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_17__ap[10]), .CK(n_0_47), .Q(registers_17__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[12][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_12__ap[10]), .CK(n_0_42), .Q(registers_12__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_893 (.A1(registers_17__ap[10]), .A2(n_1_0_1271), .B1( + n_1_0_1260), .B2(registers_12__ap[10]), .ZN(n_1_0_850)); + SDFF_X1_LVT \registers_reg[15][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_15__ap[10]), .CK(n_0_45), .Q(registers_15__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[5][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_5__ap[10]), .CK(n_0_35), .Q(registers_5__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_892 (.A1(registers_15__ap[10]), .A2(n_1_0_1286), .B1( + n_1_0_1273), .B2(registers_5__ap[10]), .ZN(n_1_0_849)); + NAND3_X1_LVT i_1_0_891 (.A1(n_1_0_851), .A2(n_1_0_850), .A3(n_1_0_849), + .ZN(n_1_0_848)); + SDFF_X1_LVT \registers_reg[22][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_22__ap[10]), .CK(n_0_52), .Q(registers_22__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[16][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_16__ap[10]), .CK(n_0_46), .Q(registers_16__ap[10]), .QN()); + AOI221_X1_LVT i_1_0_890 (.A(n_1_0_848), .B1(n_1_0_1294), .B2( + registers_22__ap[10]), .C1(registers_16__ap[10]), .C2(n_1_0_1267), + .ZN(n_1_0_847)); + SDFF_X1_LVT \registers_reg[9][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_9__ap[10]), .CK(n_0_39), .Q(registers_9__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[1][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_1__ap[10]), .CK(n_0_0), .Q(registers_1__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_889 (.A1(registers_9__ap[10]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[10]), .ZN(n_1_0_846)); + SDFF_X1_LVT \registers_reg[6][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_6__ap[10]), .CK(n_0_36), .Q(registers_6__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[14][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_14__ap[10]), .CK(n_0_44), .Q(registers_14__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_888 (.A1(registers_6__ap[10]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[10]), .ZN(n_1_0_845)); + SDFF_X1_LVT \registers_reg[19][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_19__ap[10]), .CK(n_0_49), .Q(registers_19__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[3][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_3__ap[10]), .CK(n_0_33), .Q(registers_3__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_887 (.A1(registers_19__ap[10]), .A2(n_1_0_1295), .B1( + n_1_0_1257), .B2(registers_3__ap[10]), .ZN(n_1_0_844)); + NAND3_X1_LVT i_1_0_886 (.A1(n_1_0_846), .A2(n_1_0_845), .A3(n_1_0_844), + .ZN(n_1_0_843)); + SDFF_X1_LVT \registers_reg[11][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_11__ap[10]), .CK(n_0_41), .Q(registers_11__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[2][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_2__ap[10]), .CK(n_0_32), .Q(registers_2__ap[10]), .QN()); + AOI221_X1_LVT i_1_0_885 (.A(n_1_0_843), .B1(n_1_0_1270), .B2( + registers_11__ap[10]), .C1(registers_2__ap[10]), .C2(n_1_0_1268), .ZN( + n_1_0_842)); + NAND3_X1_LVT i_1_0_884 (.A1(n_1_0_852), .A2(n_1_0_847), .A3(n_1_0_842), + .ZN(RRs1[10])); + AND2_X1_LVT i_0_0_9 (.A1(n_0_0_16), .A2(WRd[9]), .ZN(registers[9])); + SDFF_X1_LVT \registers_reg[13][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_13__ap[9]), .CK(n_0_43), .Q(registers_13__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[21][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_21__ap[9]), .CK(n_0_51), .Q(registers_21__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_880 (.A1(registers_13__ap[9]), .A2(n_1_0_1277), .B1( + n_1_0_1259), .B2(registers_21__ap[9]), .ZN(n_1_0_838)); + SDFF_X1_LVT \registers_reg[29][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_29__ap[9]), .CK(n_0_59), .Q(registers_29__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[23][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_23__ap[9]), .CK(n_0_53), .Q(registers_23__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_883 (.A1(registers_29__ap[9]), .A2(n_1_0_1276), .B1( + n_1_0_1264), .B2(registers_23__ap[9]), .ZN(n_1_0_841)); + SDFF_X1_LVT \registers_reg[24][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_24__ap[9]), .CK(n_0_54), .Q(registers_24__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[20][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_20__ap[9]), .CK(n_0_50), .Q(registers_20__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_879 (.A1(registers_24__ap[9]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[9]), .ZN(n_1_0_837)); + SDFF_X1_LVT \registers_reg[7][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_7__ap[9]), .CK(n_0_37), .Q(registers_7__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[3][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_3__ap[9]), .CK(n_0_33), .Q(registers_3__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_882 (.A1(registers_7__ap[9]), .A2(n_1_0_1263), .B1( + n_1_0_1257), .B2(registers_3__ap[9]), .ZN(n_1_0_840)); + INV_X1_LVT i_1_0_881 (.A(n_1_0_840), .ZN(n_1_0_839)); + SDFF_X1_LVT \registers_reg[31][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_31__ap[9]), .CK(n_0_61), .Q(registers_31__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[4][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_4__ap[9]), .CK(n_0_34), .Q(registers_4__ap[9]), .QN()); + AOI221_X1_LVT i_1_0_878 (.A(n_1_0_839), .B1(n_1_0_1266), .B2( + registers_31__ap[9]), .C1(registers_4__ap[9]), .C2(n_1_0_1278), .ZN( + n_1_0_836)); + SDFF_X1_LVT \registers_reg[10][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_10__ap[9]), .CK(n_0_40), .Q(registers_10__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[26][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_26__ap[9]), .CK(n_0_56), .Q(registers_26__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[25][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_25__ap[9]), .CK(n_0_55), .Q(registers_25__ap[9]), .QN()); + AOI222_X1_LVT i_1_0_877 (.A1(registers_10__ap[9]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[9]), .C1(registers_25__ap[9]), .C2( + n_1_0_1269), .ZN(n_1_0_835)); + NAND4_X1_LVT i_1_0_876 (.A1(n_1_0_841), .A2(n_1_0_837), .A3(n_1_0_836), + .A4(n_1_0_835), .ZN(n_1_0_834)); + SDFF_X1_LVT \registers_reg[8][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_8__ap[9]), .CK(n_0_38), .Q(registers_8__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[28][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_28__ap[9]), .CK(n_0_58), .Q(registers_28__ap[9]), .QN()); + AOI221_X1_LVT i_1_0_875 (.A(n_1_0_834), .B1(n_1_0_1282), .B2( + registers_8__ap[9]), .C1(registers_28__ap[9]), .C2(n_1_0_1283), .ZN( + n_1_0_833)); + SDFF_X1_LVT \registers_reg[18][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_18__ap[9]), .CK(n_0_48), .Q(registers_18__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[30][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_30__ap[9]), .CK(n_0_60), .Q(registers_30__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_874 (.A1(registers_18__ap[9]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[9]), .ZN(n_1_0_832)); + SDFF_X1_LVT \registers_reg[17][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_17__ap[9]), .CK(n_0_47), .Q(registers_17__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[12][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_12__ap[9]), .CK(n_0_42), .Q(registers_12__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_873 (.A1(registers_17__ap[9]), .A2(n_1_0_1271), .B1( + n_1_0_1260), .B2(registers_12__ap[9]), .ZN(n_1_0_831)); + SDFF_X1_LVT \registers_reg[15][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_15__ap[9]), .CK(n_0_45), .Q(registers_15__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[5][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_5__ap[9]), .CK(n_0_35), .Q(registers_5__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_872 (.A1(registers_15__ap[9]), .A2(n_1_0_1286), .B1( + n_1_0_1273), .B2(registers_5__ap[9]), .ZN(n_1_0_830)); + NAND3_X1_LVT i_1_0_871 (.A1(n_1_0_832), .A2(n_1_0_831), .A3(n_1_0_830), + .ZN(n_1_0_829)); + SDFF_X1_LVT \registers_reg[22][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_22__ap[9]), .CK(n_0_52), .Q(registers_22__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[16][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_16__ap[9]), .CK(n_0_46), .Q(registers_16__ap[9]), .QN()); + AOI221_X1_LVT i_1_0_870 (.A(n_1_0_829), .B1(n_1_0_1294), .B2( + registers_22__ap[9]), .C1(registers_16__ap[9]), .C2(n_1_0_1267), .ZN( + n_1_0_828)); + SDFF_X1_LVT \registers_reg[9][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_9__ap[9]), .CK(n_0_39), .Q(registers_9__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[1][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_1__ap[9]), .CK(n_0_0), .Q(registers_1__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_869 (.A1(registers_9__ap[9]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[9]), .ZN(n_1_0_827)); + SDFF_X1_LVT \registers_reg[6][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_6__ap[9]), .CK(n_0_36), .Q(registers_6__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[14][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_14__ap[9]), .CK(n_0_44), .Q(registers_14__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_868 (.A1(registers_6__ap[9]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[9]), .ZN(n_1_0_826)); + SDFF_X1_LVT \registers_reg[19][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_19__ap[9]), .CK(n_0_49), .Q(registers_19__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[2][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_2__ap[9]), .CK(n_0_32), .Q(registers_2__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_867 (.A1(registers_19__ap[9]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[9]), .ZN(n_1_0_825)); + NAND3_X1_LVT i_1_0_866 (.A1(n_1_0_827), .A2(n_1_0_826), .A3(n_1_0_825), + .ZN(n_1_0_824)); + SDFF_X1_LVT \registers_reg[11][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_11__ap[9]), .CK(n_0_41), .Q(registers_11__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[27][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_27__ap[9]), .CK(n_0_57), .Q(registers_27__ap[9]), .QN()); + AOI221_X1_LVT i_1_0_865 (.A(n_1_0_824), .B1(n_1_0_1270), .B2( + registers_11__ap[9]), .C1(registers_27__ap[9]), .C2(n_1_0_1279), .ZN( + n_1_0_823)); + NAND4_X1_LVT i_1_0_864 (.A1(n_1_0_838), .A2(n_1_0_833), .A3(n_1_0_828), + .A4(n_1_0_823), .ZN(RRs1[9])); + AND2_X1_LVT i_0_0_8 (.A1(n_0_0_16), .A2(WRd[8]), .ZN(registers[8])); + SDFF_X1_LVT \registers_reg[13][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_13__ap[8]), .CK(n_0_43), .Q(registers_13__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[21][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_21__ap[8]), .CK(n_0_51), .Q(registers_21__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_860 (.A1(registers_13__ap[8]), .A2(n_1_0_1277), .B1( + n_1_0_1259), .B2(registers_21__ap[8]), .ZN(n_1_0_819)); + SDFF_X1_LVT \registers_reg[29][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_29__ap[8]), .CK(n_0_59), .Q(registers_29__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[23][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_23__ap[8]), .CK(n_0_53), .Q(registers_23__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_863 (.A1(registers_29__ap[8]), .A2(n_1_0_1276), .B1( + n_1_0_1264), .B2(registers_23__ap[8]), .ZN(n_1_0_822)); + SDFF_X1_LVT \registers_reg[24][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_24__ap[8]), .CK(n_0_54), .Q(registers_24__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[20][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_20__ap[8]), .CK(n_0_50), .Q(registers_20__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_859 (.A1(registers_24__ap[8]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[8]), .ZN(n_1_0_818)); + SDFF_X1_LVT \registers_reg[7][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_7__ap[8]), .CK(n_0_37), .Q(registers_7__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[3][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_3__ap[8]), .CK(n_0_33), .Q(registers_3__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_862 (.A1(registers_7__ap[8]), .A2(n_1_0_1263), .B1( + n_1_0_1257), .B2(registers_3__ap[8]), .ZN(n_1_0_821)); + INV_X1_LVT i_1_0_861 (.A(n_1_0_821), .ZN(n_1_0_820)); + SDFF_X1_LVT \registers_reg[31][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_31__ap[8]), .CK(n_0_61), .Q(registers_31__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[4][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_4__ap[8]), .CK(n_0_34), .Q(registers_4__ap[8]), .QN()); + AOI221_X1_LVT i_1_0_858 (.A(n_1_0_820), .B1(n_1_0_1266), .B2( + registers_31__ap[8]), .C1(registers_4__ap[8]), .C2(n_1_0_1278), .ZN( + n_1_0_817)); + SDFF_X1_LVT \registers_reg[10][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_10__ap[8]), .CK(n_0_40), .Q(registers_10__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[26][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_26__ap[8]), .CK(n_0_56), .Q(registers_26__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[25][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_25__ap[8]), .CK(n_0_55), .Q(registers_25__ap[8]), .QN()); + AOI222_X1_LVT i_1_0_857 (.A1(registers_10__ap[8]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[8]), .C1(registers_25__ap[8]), .C2( + n_1_0_1269), .ZN(n_1_0_816)); + NAND4_X1_LVT i_1_0_856 (.A1(n_1_0_822), .A2(n_1_0_818), .A3(n_1_0_817), + .A4(n_1_0_816), .ZN(n_1_0_815)); + SDFF_X1_LVT \registers_reg[8][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_8__ap[8]), .CK(n_0_38), .Q(registers_8__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[28][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_28__ap[8]), .CK(n_0_58), .Q(registers_28__ap[8]), .QN()); + AOI221_X1_LVT i_1_0_855 (.A(n_1_0_815), .B1(n_1_0_1282), .B2( + registers_8__ap[8]), .C1(registers_28__ap[8]), .C2(n_1_0_1283), .ZN( + n_1_0_814)); + SDFF_X1_LVT \registers_reg[18][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_18__ap[8]), .CK(n_0_48), .Q(registers_18__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[30][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_30__ap[8]), .CK(n_0_60), .Q(registers_30__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_854 (.A1(registers_18__ap[8]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[8]), .ZN(n_1_0_813)); + SDFF_X1_LVT \registers_reg[17][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_17__ap[8]), .CK(n_0_47), .Q(registers_17__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[12][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_12__ap[8]), .CK(n_0_42), .Q(registers_12__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_853 (.A1(registers_17__ap[8]), .A2(n_1_0_1271), .B1( + n_1_0_1260), .B2(registers_12__ap[8]), .ZN(n_1_0_812)); + SDFF_X1_LVT \registers_reg[15][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_15__ap[8]), .CK(n_0_45), .Q(registers_15__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[5][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_5__ap[8]), .CK(n_0_35), .Q(registers_5__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_852 (.A1(registers_15__ap[8]), .A2(n_1_0_1286), .B1( + n_1_0_1273), .B2(registers_5__ap[8]), .ZN(n_1_0_811)); + NAND3_X1_LVT i_1_0_851 (.A1(n_1_0_813), .A2(n_1_0_812), .A3(n_1_0_811), + .ZN(n_1_0_810)); + SDFF_X1_LVT \registers_reg[22][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_22__ap[8]), .CK(n_0_52), .Q(registers_22__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[16][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_16__ap[8]), .CK(n_0_46), .Q(registers_16__ap[8]), .QN()); + AOI221_X1_LVT i_1_0_850 (.A(n_1_0_810), .B1(n_1_0_1294), .B2( + registers_22__ap[8]), .C1(registers_16__ap[8]), .C2(n_1_0_1267), .ZN( + n_1_0_809)); + SDFF_X1_LVT \registers_reg[9][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_9__ap[8]), .CK(n_0_39), .Q(registers_9__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[1][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_1__ap[8]), .CK(n_0_0), .Q(registers_1__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_849 (.A1(registers_9__ap[8]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[8]), .ZN(n_1_0_808)); + SDFF_X1_LVT \registers_reg[6][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_6__ap[8]), .CK(n_0_36), .Q(registers_6__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[14][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_14__ap[8]), .CK(n_0_44), .Q(registers_14__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_848 (.A1(registers_6__ap[8]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[8]), .ZN(n_1_0_807)); + SDFF_X1_LVT \registers_reg[19][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_19__ap[8]), .CK(n_0_49), .Q(registers_19__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[2][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_2__ap[8]), .CK(n_0_32), .Q(registers_2__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_847 (.A1(registers_19__ap[8]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[8]), .ZN(n_1_0_806)); + NAND3_X1_LVT i_1_0_846 (.A1(n_1_0_808), .A2(n_1_0_807), .A3(n_1_0_806), + .ZN(n_1_0_805)); + SDFF_X1_LVT \registers_reg[11][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_11__ap[8]), .CK(n_0_41), .Q(registers_11__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[27][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_27__ap[8]), .CK(n_0_57), .Q(registers_27__ap[8]), .QN()); + AOI221_X1_LVT i_1_0_845 (.A(n_1_0_805), .B1(n_1_0_1270), .B2( + registers_11__ap[8]), .C1(registers_27__ap[8]), .C2(n_1_0_1279), .ZN( + n_1_0_804)); + NAND4_X1_LVT i_1_0_844 (.A1(n_1_0_819), .A2(n_1_0_814), .A3(n_1_0_809), + .A4(n_1_0_804), .ZN(RRs1[8])); + AND2_X1_LVT i_0_0_7 (.A1(n_0_0_16), .A2(WRd[7]), .ZN(registers[7])); + SDFF_X1_LVT \registers_reg[13][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_13__ap[7]), .CK(n_0_43), .Q(registers_13__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[21][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_21__ap[7]), .CK(n_0_51), .Q(registers_21__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_843 (.A1(registers_13__ap[7]), .A2(n_1_0_1277), .B1( + n_1_0_1259), .B2(registers_21__ap[7]), .ZN(n_1_0_803)); + SDFF_X1_LVT \registers_reg[18][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_18__ap[7]), .CK(n_0_48), .Q(registers_18__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[10][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_10__ap[7]), .CK(n_0_40), .Q(registers_10__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[25][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_25__ap[7]), .CK(n_0_55), .Q(registers_25__ap[7]), .QN()); + AOI222_X1_LVT i_1_0_842 (.A1(registers_18__ap[7]), .A2(n_1_0_1297), .B1( + n_1_0_1287), .B2(registers_10__ap[7]), .C1(registers_25__ap[7]), .C2( + n_1_0_1269), .ZN(n_1_0_802)); + SDFF_X1_LVT \registers_reg[28][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_28__ap[7]), .CK(n_0_58), .Q(registers_28__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[8][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_8__ap[7]), .CK(n_0_38), .Q(registers_8__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_841 (.A1(registers_28__ap[7]), .A2(n_1_0_1283), .B1( + n_1_0_1282), .B2(registers_8__ap[7]), .ZN(n_1_0_801)); + SDFF_X1_LVT \registers_reg[24][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_24__ap[7]), .CK(n_0_54), .Q(registers_24__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[20][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_20__ap[7]), .CK(n_0_50), .Q(registers_20__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_840 (.A1(registers_24__ap[7]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[7]), .ZN(n_1_0_800)); + SDFF_X1_LVT \registers_reg[31][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_31__ap[7]), .CK(n_0_61), .Q(registers_31__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[7][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_7__ap[7]), .CK(n_0_37), .Q(registers_7__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_839 (.A1(registers_31__ap[7]), .A2(n_1_0_1266), .B1( + n_1_0_1263), .B2(registers_7__ap[7]), .ZN(n_1_0_799)); + SDFF_X1_LVT \registers_reg[17][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_17__ap[7]), .CK(n_0_47), .Q(registers_17__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[11][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_11__ap[7]), .CK(n_0_41), .Q(registers_11__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_838 (.A1(registers_17__ap[7]), .A2(n_1_0_1271), .B1( + n_1_0_1270), .B2(registers_11__ap[7]), .ZN(n_1_0_798)); + SDFF_X1_LVT \registers_reg[27][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_27__ap[7]), .CK(n_0_57), .Q(registers_27__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[29][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_29__ap[7]), .CK(n_0_59), .Q(registers_29__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_837 (.A1(registers_27__ap[7]), .A2(n_1_0_1279), .B1( + n_1_0_1276), .B2(registers_29__ap[7]), .ZN(n_1_0_797)); + NAND4_X1_LVT i_1_0_836 (.A1(n_1_0_800), .A2(n_1_0_799), .A3(n_1_0_798), + .A4(n_1_0_797), .ZN(n_1_0_796)); + SDFF_X1_LVT \registers_reg[26][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_26__ap[7]), .CK(n_0_56), .Q(registers_26__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[30][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_30__ap[7]), .CK(n_0_60), .Q(registers_30__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_835 (.A1(registers_26__ap[7]), .A2(n_1_0_1285), .B1( + n_1_0_1272), .B2(registers_30__ap[7]), .ZN(n_1_0_795)); + SDFF_X1_LVT \registers_reg[4][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_4__ap[7]), .CK(n_0_34), .Q(registers_4__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[12][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_12__ap[7]), .CK(n_0_42), .Q(registers_12__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_834 (.A1(registers_4__ap[7]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[7]), .ZN(n_1_0_794)); + SDFF_X1_LVT \registers_reg[15][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_15__ap[7]), .CK(n_0_45), .Q(registers_15__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[16][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_16__ap[7]), .CK(n_0_46), .Q(registers_16__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_833 (.A1(registers_15__ap[7]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[7]), .ZN(n_1_0_793)); + SDFF_X1_LVT \registers_reg[22][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_22__ap[7]), .CK(n_0_52), .Q(registers_22__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[5][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_5__ap[7]), .CK(n_0_35), .Q(registers_5__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_832 (.A1(registers_22__ap[7]), .A2(n_1_0_1294), .B1( + n_1_0_1273), .B2(registers_5__ap[7]), .ZN(n_1_0_792)); + NAND4_X1_LVT i_1_0_831 (.A1(n_1_0_795), .A2(n_1_0_794), .A3(n_1_0_793), + .A4(n_1_0_792), .ZN(n_1_0_791)); + SDFF_X1_LVT \registers_reg[19][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_19__ap[7]), .CK(n_0_49), .Q(registers_19__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[3][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_3__ap[7]), .CK(n_0_33), .Q(registers_3__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_830 (.A1(registers_19__ap[7]), .A2(n_1_0_1295), .B1( + n_1_0_1257), .B2(registers_3__ap[7]), .ZN(n_1_0_790)); + SDFF_X1_LVT \registers_reg[9][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_9__ap[7]), .CK(n_0_39), .Q(registers_9__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[1][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_1__ap[7]), .CK(n_0_0), .Q(registers_1__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_829 (.A1(registers_9__ap[7]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[7]), .ZN(n_1_0_789)); + SDFF_X1_LVT \registers_reg[6][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_6__ap[7]), .CK(n_0_36), .Q(registers_6__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[14][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_14__ap[7]), .CK(n_0_44), .Q(registers_14__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_828 (.A1(registers_6__ap[7]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[7]), .ZN(n_1_0_788)); + SDFF_X1_LVT \registers_reg[2][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_2__ap[7]), .CK(n_0_32), .Q(registers_2__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[23][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_23__ap[7]), .CK(n_0_53), .Q(registers_23__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_827 (.A1(registers_2__ap[7]), .A2(n_1_0_1268), .B1( + n_1_0_1264), .B2(registers_23__ap[7]), .ZN(n_1_0_787)); + NAND4_X1_LVT i_1_0_826 (.A1(n_1_0_790), .A2(n_1_0_789), .A3(n_1_0_788), + .A4(n_1_0_787), .ZN(n_1_0_786)); + NOR3_X1_LVT i_1_0_825 (.A1(n_1_0_796), .A2(n_1_0_791), .A3(n_1_0_786), + .ZN(n_1_0_785)); + NAND4_X1_LVT i_1_0_824 (.A1(n_1_0_803), .A2(n_1_0_802), .A3(n_1_0_801), + .A4(n_1_0_785), .ZN(RRs1[7])); + AND2_X1_LVT i_0_0_6 (.A1(n_0_0_16), .A2(WRd[6]), .ZN(registers[6])); + SDFF_X1_LVT \registers_reg[28][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_28__ap[6]), .CK(n_0_58), .Q(registers_28__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[17][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_17__ap[6]), .CK(n_0_47), .Q(registers_17__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_823 (.A1(registers_28__ap[6]), .A2(n_1_0_1283), .B1( + n_1_0_1271), .B2(registers_17__ap[6]), .ZN(n_1_0_784)); + SDFF_X1_LVT \registers_reg[18][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_18__ap[6]), .CK(n_0_48), .Q(registers_18__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[10][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_10__ap[6]), .CK(n_0_40), .Q(registers_10__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[8][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_8__ap[6]), .CK(n_0_38), .Q(registers_8__ap[6]), .QN()); + AOI222_X1_LVT i_1_0_822 (.A1(registers_18__ap[6]), .A2(n_1_0_1297), .B1( + n_1_0_1287), .B2(registers_10__ap[6]), .C1(registers_8__ap[6]), .C2( + n_1_0_1282), .ZN(n_1_0_783)); + SDFF_X1_LVT \registers_reg[9][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_9__ap[6]), .CK(n_0_39), .Q(registers_9__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[29][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_29__ap[6]), .CK(n_0_59), .Q(registers_29__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_821 (.A1(registers_9__ap[6]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[6]), .ZN(n_1_0_782)); + SDFF_X1_LVT \registers_reg[6][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_6__ap[6]), .CK(n_0_36), .Q(registers_6__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[1][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_1__ap[6]), .CK(n_0_0), .Q(registers_1__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_820 (.A1(registers_6__ap[6]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[6]), .ZN(n_1_0_781)); + SDFF_X1_LVT \registers_reg[15][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_15__ap[6]), .CK(n_0_45), .Q(registers_15__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[27][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_27__ap[6]), .CK(n_0_57), .Q(registers_27__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_819 (.A1(registers_15__ap[6]), .A2(n_1_0_1286), .B1( + n_1_0_1279), .B2(registers_27__ap[6]), .ZN(n_1_0_780)); + SDFF_X1_LVT \registers_reg[11][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_11__ap[6]), .CK(n_0_41), .Q(registers_11__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[16][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_16__ap[6]), .CK(n_0_46), .Q(registers_16__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_818 (.A1(registers_11__ap[6]), .A2(n_1_0_1270), .B1( + n_1_0_1267), .B2(registers_16__ap[6]), .ZN(n_1_0_779)); + SDFF_X1_LVT \registers_reg[5][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_5__ap[6]), .CK(n_0_35), .Q(registers_5__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[31][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_31__ap[6]), .CK(n_0_61), .Q(registers_31__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_817 (.A1(registers_5__ap[6]), .A2(n_1_0_1273), .B1( + n_1_0_1266), .B2(registers_31__ap[6]), .ZN(n_1_0_778)); + NAND4_X1_LVT i_1_0_816 (.A1(n_1_0_781), .A2(n_1_0_780), .A3(n_1_0_779), + .A4(n_1_0_778), .ZN(n_1_0_777)); + SDFF_X1_LVT \registers_reg[26][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_26__ap[6]), .CK(n_0_56), .Q(registers_26__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[30][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_30__ap[6]), .CK(n_0_60), .Q(registers_30__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_815 (.A1(registers_26__ap[6]), .A2(n_1_0_1285), .B1( + n_1_0_1272), .B2(registers_30__ap[6]), .ZN(n_1_0_776)); + SDFF_X1_LVT \registers_reg[20][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_20__ap[6]), .CK(n_0_50), .Q(registers_20__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[4][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_4__ap[6]), .CK(n_0_34), .Q(registers_4__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_814 (.A1(registers_20__ap[6]), .A2(n_1_0_1281), .B1( + n_1_0_1278), .B2(registers_4__ap[6]), .ZN(n_1_0_775)); + SDFF_X1_LVT \registers_reg[22][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_22__ap[6]), .CK(n_0_52), .Q(registers_22__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[21][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_21__ap[6]), .CK(n_0_51), .Q(registers_21__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_813 (.A1(registers_22__ap[6]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[6]), .ZN(n_1_0_774)); + SDFF_X1_LVT \registers_reg[24][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_24__ap[6]), .CK(n_0_54), .Q(registers_24__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[12][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_12__ap[6]), .CK(n_0_42), .Q(registers_12__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_812 (.A1(registers_24__ap[6]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[6]), .ZN(n_1_0_773)); + NAND4_X1_LVT i_1_0_811 (.A1(n_1_0_776), .A2(n_1_0_775), .A3(n_1_0_774), + .A4(n_1_0_773), .ZN(n_1_0_772)); + SDFF_X1_LVT \registers_reg[13][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_13__ap[6]), .CK(n_0_43), .Q(registers_13__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[25][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_25__ap[6]), .CK(n_0_55), .Q(registers_25__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_810 (.A1(registers_13__ap[6]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[6]), .ZN(n_1_0_771)); + SDFF_X1_LVT \registers_reg[7][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_7__ap[6]), .CK(n_0_37), .Q(registers_7__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[14][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_14__ap[6]), .CK(n_0_44), .Q(registers_14__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_809 (.A1(registers_7__ap[6]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[6]), .ZN(n_1_0_770)); + SDFF_X1_LVT \registers_reg[19][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_19__ap[6]), .CK(n_0_49), .Q(registers_19__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[3][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_3__ap[6]), .CK(n_0_33), .Q(registers_3__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_808 (.A1(registers_19__ap[6]), .A2(n_1_0_1295), .B1( + n_1_0_1257), .B2(registers_3__ap[6]), .ZN(n_1_0_769)); + SDFF_X1_LVT \registers_reg[2][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_2__ap[6]), .CK(n_0_32), .Q(registers_2__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[23][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_23__ap[6]), .CK(n_0_53), .Q(registers_23__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_807 (.A1(registers_2__ap[6]), .A2(n_1_0_1268), .B1( + n_1_0_1264), .B2(registers_23__ap[6]), .ZN(n_1_0_768)); + NAND4_X1_LVT i_1_0_806 (.A1(n_1_0_771), .A2(n_1_0_770), .A3(n_1_0_769), + .A4(n_1_0_768), .ZN(n_1_0_767)); + NOR3_X1_LVT i_1_0_805 (.A1(n_1_0_777), .A2(n_1_0_772), .A3(n_1_0_767), + .ZN(n_1_0_766)); + NAND4_X1_LVT i_1_0_804 (.A1(n_1_0_784), .A2(n_1_0_783), .A3(n_1_0_782), + .A4(n_1_0_766), .ZN(RRs1[6])); + AND2_X1_LVT i_0_0_5 (.A1(n_0_0_16), .A2(WRd[5]), .ZN(registers[5])); + SDFF_X1_LVT \registers_reg[28][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_28__ap[5]), .CK(n_0_58), .Q(registers_28__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[4][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_4__ap[5]), .CK(n_0_34), .Q(registers_4__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_803 (.A1(registers_28__ap[5]), .A2(n_1_0_1283), .B1( + n_1_0_1278), .B2(registers_4__ap[5]), .ZN(n_1_0_765)); + SDFF_X1_LVT \registers_reg[10][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_10__ap[5]), .CK(n_0_40), .Q(registers_10__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[26][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_26__ap[5]), .CK(n_0_56), .Q(registers_26__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[8][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_8__ap[5]), .CK(n_0_38), .Q(registers_8__ap[5]), .QN()); + AOI222_X1_LVT i_1_0_802 (.A1(registers_10__ap[5]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[5]), .C1(registers_8__ap[5]), .C2( + n_1_0_1282), .ZN(n_1_0_764)); + SDFF_X1_LVT \registers_reg[9][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_9__ap[5]), .CK(n_0_39), .Q(registers_9__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[29][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_29__ap[5]), .CK(n_0_59), .Q(registers_29__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_801 (.A1(registers_9__ap[5]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[5]), .ZN(n_1_0_763)); + SDFF_X1_LVT \registers_reg[6][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_6__ap[5]), .CK(n_0_36), .Q(registers_6__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[1][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_1__ap[5]), .CK(n_0_0), .Q(registers_1__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_800 (.A1(registers_6__ap[5]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[5]), .ZN(n_1_0_762)); + SDFF_X1_LVT \registers_reg[16][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_16__ap[5]), .CK(n_0_46), .Q(registers_16__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[3][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_3__ap[5]), .CK(n_0_33), .Q(registers_3__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_799 (.A1(registers_16__ap[5]), .A2(n_1_0_1267), .B1( + n_1_0_1257), .B2(registers_3__ap[5]), .ZN(n_1_0_761)); + SDFF_X1_LVT \registers_reg[5][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_5__ap[5]), .CK(n_0_35), .Q(registers_5__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[31][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_31__ap[5]), .CK(n_0_61), .Q(registers_31__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_798 (.A1(registers_5__ap[5]), .A2(n_1_0_1273), .B1( + n_1_0_1266), .B2(registers_31__ap[5]), .ZN(n_1_0_760)); + SDFF_X1_LVT \registers_reg[15][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_15__ap[5]), .CK(n_0_45), .Q(registers_15__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[23][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_23__ap[5]), .CK(n_0_53), .Q(registers_23__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_797 (.A1(registers_15__ap[5]), .A2(n_1_0_1286), .B1( + n_1_0_1264), .B2(registers_23__ap[5]), .ZN(n_1_0_759)); + NAND4_X1_LVT i_1_0_796 (.A1(n_1_0_762), .A2(n_1_0_761), .A3(n_1_0_760), + .A4(n_1_0_759), .ZN(n_1_0_758)); + SDFF_X1_LVT \registers_reg[18][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_18__ap[5]), .CK(n_0_48), .Q(registers_18__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[30][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_30__ap[5]), .CK(n_0_60), .Q(registers_30__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_795 (.A1(registers_18__ap[5]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[5]), .ZN(n_1_0_757)); + SDFF_X1_LVT \registers_reg[24][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_24__ap[5]), .CK(n_0_54), .Q(registers_24__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[12][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_12__ap[5]), .CK(n_0_42), .Q(registers_12__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_794 (.A1(registers_24__ap[5]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[5]), .ZN(n_1_0_756)); + SDFF_X1_LVT \registers_reg[22][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_22__ap[5]), .CK(n_0_52), .Q(registers_22__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[21][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_21__ap[5]), .CK(n_0_51), .Q(registers_21__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_793 (.A1(registers_22__ap[5]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[5]), .ZN(n_1_0_755)); + SDFF_X1_LVT \registers_reg[20][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_20__ap[5]), .CK(n_0_50), .Q(registers_20__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[17][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_17__ap[5]), .CK(n_0_47), .Q(registers_17__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_792 (.A1(registers_20__ap[5]), .A2(n_1_0_1281), .B1( + n_1_0_1271), .B2(registers_17__ap[5]), .ZN(n_1_0_754)); + NAND4_X1_LVT i_1_0_791 (.A1(n_1_0_757), .A2(n_1_0_756), .A3(n_1_0_755), + .A4(n_1_0_754), .ZN(n_1_0_753)); + SDFF_X1_LVT \registers_reg[13][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_13__ap[5]), .CK(n_0_43), .Q(registers_13__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[25][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_25__ap[5]), .CK(n_0_55), .Q(registers_25__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_790 (.A1(registers_13__ap[5]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[5]), .ZN(n_1_0_752)); + SDFF_X1_LVT \registers_reg[19][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_19__ap[5]), .CK(n_0_49), .Q(registers_19__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[2][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_2__ap[5]), .CK(n_0_32), .Q(registers_2__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_789 (.A1(registers_19__ap[5]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[5]), .ZN(n_1_0_751)); + SDFF_X1_LVT \registers_reg[7][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_7__ap[5]), .CK(n_0_37), .Q(registers_7__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[14][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_14__ap[5]), .CK(n_0_44), .Q(registers_14__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_788 (.A1(registers_7__ap[5]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[5]), .ZN(n_1_0_750)); + SDFF_X1_LVT \registers_reg[27][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_27__ap[5]), .CK(n_0_57), .Q(registers_27__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[11][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_11__ap[5]), .CK(n_0_41), .Q(registers_11__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_787 (.A1(registers_27__ap[5]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[5]), .ZN(n_1_0_749)); + NAND4_X1_LVT i_1_0_786 (.A1(n_1_0_752), .A2(n_1_0_751), .A3(n_1_0_750), + .A4(n_1_0_749), .ZN(n_1_0_748)); + NOR3_X1_LVT i_1_0_785 (.A1(n_1_0_758), .A2(n_1_0_753), .A3(n_1_0_748), + .ZN(n_1_0_747)); + NAND4_X1_LVT i_1_0_784 (.A1(n_1_0_765), .A2(n_1_0_764), .A3(n_1_0_763), + .A4(n_1_0_747), .ZN(RRs1[5])); + AND2_X1_LVT i_0_0_4 (.A1(n_0_0_16), .A2(WRd[4]), .ZN(registers[4])); + SDFF_X1_LVT \registers_reg[10][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_10__ap[4]), .CK(n_0_40), .Q(registers_10__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[21][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_21__ap[4]), .CK(n_0_51), .Q(registers_21__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_783 (.A1(registers_10__ap[4]), .A2(n_1_0_1287), .B1( + n_1_0_1259), .B2(registers_21__ap[4]), .ZN(n_1_0_746)); + SDFF_X1_LVT \registers_reg[9][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_9__ap[4]), .CK(n_0_39), .Q(registers_9__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[1][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_1__ap[4]), .CK(n_0_0), .Q(registers_1__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_778 (.A1(registers_9__ap[4]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[4]), .ZN(n_1_0_741)); + SDFF_X1_LVT \registers_reg[18][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_18__ap[4]), .CK(n_0_48), .Q(registers_18__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[8][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_8__ap[4]), .CK(n_0_38), .Q(registers_8__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_777 (.A1(registers_18__ap[4]), .A2(n_1_0_1297), .B1( + n_1_0_1282), .B2(registers_8__ap[4]), .ZN(n_1_0_740)); + NAND3_X1_LVT i_1_0_775 (.A1(n_1_0_746), .A2(n_1_0_741), .A3(n_1_0_740), + .ZN(n_1_0_738)); + SDFF_X1_LVT \registers_reg[22][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_22__ap[4]), .CK(n_0_52), .Q(registers_22__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[23][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_23__ap[4]), .CK(n_0_53), .Q(registers_23__ap[4]), .QN()); + AOI221_X1_LVT i_1_0_774 (.A(n_1_0_738), .B1(n_1_0_1294), .B2( + registers_22__ap[4]), .C1(registers_23__ap[4]), .C2(n_1_0_1264), .ZN( + n_1_0_737)); + SDFF_X1_LVT \registers_reg[28][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_28__ap[4]), .CK(n_0_58), .Q(registers_28__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[20][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_20__ap[4]), .CK(n_0_50), .Q(registers_20__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_782 (.A1(registers_28__ap[4]), .A2(n_1_0_1283), .B1( + n_1_0_1281), .B2(registers_20__ap[4]), .ZN(n_1_0_745)); + SDFF_X1_LVT \registers_reg[19][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_19__ap[4]), .CK(n_0_49), .Q(registers_19__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[13][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_13__ap[4]), .CK(n_0_43), .Q(registers_13__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_780 (.A1(registers_19__ap[4]), .A2(n_1_0_1295), .B1( + n_1_0_1277), .B2(registers_13__ap[4]), .ZN(n_1_0_743)); + SDFF_X1_LVT \registers_reg[26][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_26__ap[4]), .CK(n_0_56), .Q(registers_26__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[3][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_3__ap[4]), .CK(n_0_33), .Q(registers_3__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_776 (.A1(registers_26__ap[4]), .A2(n_1_0_1285), .B1( + n_1_0_1257), .B2(registers_3__ap[4]), .ZN(n_1_0_739)); + NAND3_X1_LVT i_1_0_773 (.A1(n_1_0_745), .A2(n_1_0_743), .A3(n_1_0_739), + .ZN(n_1_0_736)); + SDFF_X1_LVT \registers_reg[30][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_30__ap[4]), .CK(n_0_60), .Q(registers_30__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[31][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_31__ap[4]), .CK(n_0_61), .Q(registers_31__ap[4]), .QN()); + AOI221_X1_LVT i_1_0_772 (.A(n_1_0_736), .B1(n_1_0_1272), .B2( + registers_30__ap[4]), .C1(registers_31__ap[4]), .C2(n_1_0_1266), .ZN( + n_1_0_735)); + SDFF_X1_LVT \registers_reg[24][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_24__ap[4]), .CK(n_0_54), .Q(registers_24__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[12][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_12__ap[4]), .CK(n_0_42), .Q(registers_12__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_781 (.A1(registers_24__ap[4]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[4]), .ZN(n_1_0_744)); + SDFF_X1_LVT \registers_reg[27][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_27__ap[4]), .CK(n_0_57), .Q(registers_27__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[11][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_11__ap[4]), .CK(n_0_41), .Q(registers_11__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_779 (.A1(registers_27__ap[4]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[4]), .ZN(n_1_0_742)); + SDFF_X1_LVT \registers_reg[17][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_17__ap[4]), .CK(n_0_47), .Q(registers_17__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[7][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_7__ap[4]), .CK(n_0_37), .Q(registers_7__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[14][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_14__ap[4]), .CK(n_0_44), .Q(registers_14__ap[4]), .QN()); + AOI222_X1_LVT i_1_0_771 (.A1(registers_17__ap[4]), .A2(n_1_0_1271), .B1( + n_1_0_1263), .B2(registers_7__ap[4]), .C1(n_1_0_1258), .C2( + registers_14__ap[4]), .ZN(n_1_0_734)); + SDFF_X1_LVT \registers_reg[15][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_15__ap[4]), .CK(n_0_45), .Q(registers_15__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[16][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_16__ap[4]), .CK(n_0_46), .Q(registers_16__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_770 (.A1(registers_15__ap[4]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[4]), .ZN(n_1_0_733)); + SDFF_X1_LVT \registers_reg[4][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_4__ap[4]), .CK(n_0_34), .Q(registers_4__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[25][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_25__ap[4]), .CK(n_0_55), .Q(registers_25__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_769 (.A1(registers_4__ap[4]), .A2(n_1_0_1278), .B1( + n_1_0_1269), .B2(registers_25__ap[4]), .ZN(n_1_0_732)); + SDFF_X1_LVT \registers_reg[29][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_29__ap[4]), .CK(n_0_59), .Q(registers_29__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[2][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_2__ap[4]), .CK(n_0_32), .Q(registers_2__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_768 (.A1(registers_29__ap[4]), .A2(n_1_0_1276), .B1( + n_1_0_1268), .B2(registers_2__ap[4]), .ZN(n_1_0_731)); + NAND3_X1_LVT i_1_0_767 (.A1(n_1_0_733), .A2(n_1_0_732), .A3(n_1_0_731), + .ZN(n_1_0_730)); + SDFF_X1_LVT \registers_reg[6][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_6__ap[4]), .CK(n_0_36), .Q(registers_6__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[5][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_5__ap[4]), .CK(n_0_35), .Q(registers_5__ap[4]), .QN()); + AOI221_X1_LVT i_1_0_766 (.A(n_1_0_730), .B1(n_1_0_1300), .B2( + registers_6__ap[4]), .C1(registers_5__ap[4]), .C2(n_1_0_1273), .ZN( + n_1_0_729)); + AND4_X1_LVT i_1_0_765 (.A1(n_1_0_744), .A2(n_1_0_742), .A3(n_1_0_734), + .A4(n_1_0_729), .ZN(n_1_0_728)); + NAND3_X1_LVT i_1_0_764 (.A1(n_1_0_737), .A2(n_1_0_735), .A3(n_1_0_728), + .ZN(RRs1[4])); + AND2_X1_LVT i_0_0_3 (.A1(n_0_0_16), .A2(WRd[3]), .ZN(registers[3])); + SDFF_X1_LVT \registers_reg[28][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_28__ap[3]), .CK(n_0_58), .Q(registers_28__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[17][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_17__ap[3]), .CK(n_0_47), .Q(registers_17__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_763 (.A1(registers_28__ap[3]), .A2(n_1_0_1283), .B1( + n_1_0_1271), .B2(registers_17__ap[3]), .ZN(n_1_0_727)); + SDFF_X1_LVT \registers_reg[10][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_10__ap[3]), .CK(n_0_40), .Q(registers_10__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[26][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_26__ap[3]), .CK(n_0_56), .Q(registers_26__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[8][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_8__ap[3]), .CK(n_0_38), .Q(registers_8__ap[3]), .QN()); + AOI222_X1_LVT i_1_0_762 (.A1(registers_10__ap[3]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[3]), .C1(registers_8__ap[3]), .C2( + n_1_0_1282), .ZN(n_1_0_726)); + SDFF_X1_LVT \registers_reg[9][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_9__ap[3]), .CK(n_0_39), .Q(registers_9__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[29][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_29__ap[3]), .CK(n_0_59), .Q(registers_29__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_761 (.A1(registers_9__ap[3]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[3]), .ZN(n_1_0_725)); + SDFF_X1_LVT \registers_reg[6][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_6__ap[3]), .CK(n_0_36), .Q(registers_6__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[1][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_1__ap[3]), .CK(n_0_0), .Q(registers_1__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_760 (.A1(registers_6__ap[3]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[3]), .ZN(n_1_0_724)); + SDFF_X1_LVT \registers_reg[16][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_16__ap[3]), .CK(n_0_46), .Q(registers_16__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[3][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_3__ap[3]), .CK(n_0_33), .Q(registers_3__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_759 (.A1(registers_16__ap[3]), .A2(n_1_0_1267), .B1( + n_1_0_1257), .B2(registers_3__ap[3]), .ZN(n_1_0_723)); + SDFF_X1_LVT \registers_reg[5][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_5__ap[3]), .CK(n_0_35), .Q(registers_5__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[31][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_31__ap[3]), .CK(n_0_61), .Q(registers_31__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_758 (.A1(registers_5__ap[3]), .A2(n_1_0_1273), .B1( + n_1_0_1266), .B2(registers_31__ap[3]), .ZN(n_1_0_722)); + SDFF_X1_LVT \registers_reg[15][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_15__ap[3]), .CK(n_0_45), .Q(registers_15__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[23][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_23__ap[3]), .CK(n_0_53), .Q(registers_23__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_757 (.A1(registers_15__ap[3]), .A2(n_1_0_1286), .B1( + n_1_0_1264), .B2(registers_23__ap[3]), .ZN(n_1_0_721)); + NAND4_X1_LVT i_1_0_756 (.A1(n_1_0_724), .A2(n_1_0_723), .A3(n_1_0_722), + .A4(n_1_0_721), .ZN(n_1_0_720)); + SDFF_X1_LVT \registers_reg[18][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_18__ap[3]), .CK(n_0_48), .Q(registers_18__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[30][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_30__ap[3]), .CK(n_0_60), .Q(registers_30__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_755 (.A1(registers_18__ap[3]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[3]), .ZN(n_1_0_719)); + SDFF_X1_LVT \registers_reg[20][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_20__ap[3]), .CK(n_0_50), .Q(registers_20__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[4][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_4__ap[3]), .CK(n_0_34), .Q(registers_4__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_754 (.A1(registers_20__ap[3]), .A2(n_1_0_1281), .B1( + n_1_0_1278), .B2(registers_4__ap[3]), .ZN(n_1_0_718)); + SDFF_X1_LVT \registers_reg[22][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_22__ap[3]), .CK(n_0_52), .Q(registers_22__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[21][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_21__ap[3]), .CK(n_0_51), .Q(registers_21__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_753 (.A1(registers_22__ap[3]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[3]), .ZN(n_1_0_717)); + SDFF_X1_LVT \registers_reg[24][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_24__ap[3]), .CK(n_0_54), .Q(registers_24__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[12][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_12__ap[3]), .CK(n_0_42), .Q(registers_12__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_752 (.A1(registers_24__ap[3]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[3]), .ZN(n_1_0_716)); + NAND4_X1_LVT i_1_0_751 (.A1(n_1_0_719), .A2(n_1_0_718), .A3(n_1_0_717), + .A4(n_1_0_716), .ZN(n_1_0_715)); + SDFF_X1_LVT \registers_reg[13][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_13__ap[3]), .CK(n_0_43), .Q(registers_13__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[25][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_25__ap[3]), .CK(n_0_55), .Q(registers_25__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_750 (.A1(registers_13__ap[3]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[3]), .ZN(n_1_0_714)); + SDFF_X1_LVT \registers_reg[19][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_19__ap[3]), .CK(n_0_49), .Q(registers_19__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[2][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_2__ap[3]), .CK(n_0_32), .Q(registers_2__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_749 (.A1(registers_19__ap[3]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[3]), .ZN(n_1_0_713)); + SDFF_X1_LVT \registers_reg[7][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_7__ap[3]), .CK(n_0_37), .Q(registers_7__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[14][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_14__ap[3]), .CK(n_0_44), .Q(registers_14__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_748 (.A1(registers_7__ap[3]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[3]), .ZN(n_1_0_712)); + SDFF_X1_LVT \registers_reg[27][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_27__ap[3]), .CK(n_0_57), .Q(registers_27__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[11][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_11__ap[3]), .CK(n_0_41), .Q(registers_11__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_747 (.A1(registers_27__ap[3]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[3]), .ZN(n_1_0_711)); + NAND4_X1_LVT i_1_0_746 (.A1(n_1_0_714), .A2(n_1_0_713), .A3(n_1_0_712), + .A4(n_1_0_711), .ZN(n_1_0_710)); + NOR3_X1_LVT i_1_0_745 (.A1(n_1_0_720), .A2(n_1_0_715), .A3(n_1_0_710), + .ZN(n_1_0_709)); + NAND4_X1_LVT i_1_0_744 (.A1(n_1_0_727), .A2(n_1_0_726), .A3(n_1_0_725), + .A4(n_1_0_709), .ZN(RRs1[3])); + AND2_X1_LVT i_0_0_2 (.A1(n_0_0_16), .A2(WRd[2]), .ZN(registers[2])); + SDFF_X1_LVT \registers_reg[28][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_28__ap[2]), .CK(n_0_58), .Q(registers_28__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[4][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_4__ap[2]), .CK(n_0_34), .Q(registers_4__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_740 (.A1(registers_28__ap[2]), .A2(n_1_0_1283), .B1( + n_1_0_1278), .B2(registers_4__ap[2]), .ZN(n_1_0_705)); + SDFF_X1_LVT \registers_reg[16][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_16__ap[2]), .CK(n_0_46), .Q(registers_16__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[31][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_31__ap[2]), .CK(n_0_61), .Q(registers_31__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_743 (.A1(registers_16__ap[2]), .A2(n_1_0_1267), .B1( + n_1_0_1266), .B2(registers_31__ap[2]), .ZN(n_1_0_708)); + SDFF_X1_LVT \registers_reg[6][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_6__ap[2]), .CK(n_0_36), .Q(registers_6__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[1][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_1__ap[2]), .CK(n_0_0), .Q(registers_1__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_739 (.A1(registers_6__ap[2]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[2]), .ZN(n_1_0_704)); + SDFF_X1_LVT \registers_reg[15][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_15__ap[2]), .CK(n_0_45), .Q(registers_15__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[27][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_27__ap[2]), .CK(n_0_57), .Q(registers_27__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_742 (.A1(registers_15__ap[2]), .A2(n_1_0_1286), .B1( + n_1_0_1279), .B2(registers_27__ap[2]), .ZN(n_1_0_707)); + INV_X1_LVT i_1_0_741 (.A(n_1_0_707), .ZN(n_1_0_706)); + SDFF_X1_LVT \registers_reg[11][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_11__ap[2]), .CK(n_0_41), .Q(registers_11__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[5][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_5__ap[2]), .CK(n_0_35), .Q(registers_5__ap[2]), .QN()); + AOI221_X1_LVT i_1_0_738 (.A(n_1_0_706), .B1(n_1_0_1270), .B2( + registers_11__ap[2]), .C1(registers_5__ap[2]), .C2(n_1_0_1273), .ZN( + n_1_0_703)); + SDFF_X1_LVT \registers_reg[10][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_10__ap[2]), .CK(n_0_40), .Q(registers_10__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[30][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_30__ap[2]), .CK(n_0_60), .Q(registers_30__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[8][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_8__ap[2]), .CK(n_0_38), .Q(registers_8__ap[2]), .QN()); + AOI222_X1_LVT i_1_0_737 (.A1(registers_10__ap[2]), .A2(n_1_0_1287), .B1( + n_1_0_1272), .B2(registers_30__ap[2]), .C1(n_1_0_1282), .C2( + registers_8__ap[2]), .ZN(n_1_0_702)); + NAND4_X1_LVT i_1_0_736 (.A1(n_1_0_708), .A2(n_1_0_704), .A3(n_1_0_703), + .A4(n_1_0_702), .ZN(n_1_0_701)); + SDFF_X1_LVT \registers_reg[9][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_9__ap[2]), .CK(n_0_39), .Q(registers_9__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[29][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_29__ap[2]), .CK(n_0_59), .Q(registers_29__ap[2]), .QN()); + AOI221_X1_LVT i_1_0_735 (.A(n_1_0_701), .B1(n_1_0_1291), .B2( + registers_9__ap[2]), .C1(registers_29__ap[2]), .C2(n_1_0_1276), .ZN( + n_1_0_700)); + SDFF_X1_LVT \registers_reg[18][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_18__ap[2]), .CK(n_0_48), .Q(registers_18__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[26][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_26__ap[2]), .CK(n_0_56), .Q(registers_26__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_734 (.A1(registers_18__ap[2]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[2]), .ZN(n_1_0_699)); + SDFF_X1_LVT \registers_reg[24][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_24__ap[2]), .CK(n_0_54), .Q(registers_24__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[12][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_12__ap[2]), .CK(n_0_42), .Q(registers_12__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_733 (.A1(registers_24__ap[2]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[2]), .ZN(n_1_0_698)); + SDFF_X1_LVT \registers_reg[22][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_22__ap[2]), .CK(n_0_52), .Q(registers_22__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[21][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_21__ap[2]), .CK(n_0_51), .Q(registers_21__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_732 (.A1(registers_22__ap[2]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[2]), .ZN(n_1_0_697)); + NAND3_X1_LVT i_1_0_731 (.A1(n_1_0_699), .A2(n_1_0_698), .A3(n_1_0_697), + .ZN(n_1_0_696)); + SDFF_X1_LVT \registers_reg[17][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_17__ap[2]), .CK(n_0_47), .Q(registers_17__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[20][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_20__ap[2]), .CK(n_0_50), .Q(registers_20__ap[2]), .QN()); + AOI221_X1_LVT i_1_0_730 (.A(n_1_0_696), .B1(n_1_0_1271), .B2( + registers_17__ap[2]), .C1(registers_20__ap[2]), .C2(n_1_0_1281), .ZN( + n_1_0_695)); + SDFF_X1_LVT \registers_reg[13][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_13__ap[2]), .CK(n_0_43), .Q(registers_13__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[25][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_25__ap[2]), .CK(n_0_55), .Q(registers_25__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_729 (.A1(registers_13__ap[2]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[2]), .ZN(n_1_0_694)); + SDFF_X1_LVT \registers_reg[7][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_7__ap[2]), .CK(n_0_37), .Q(registers_7__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[14][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_14__ap[2]), .CK(n_0_44), .Q(registers_14__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_728 (.A1(registers_7__ap[2]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[2]), .ZN(n_1_0_693)); + SDFF_X1_LVT \registers_reg[19][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_19__ap[2]), .CK(n_0_49), .Q(registers_19__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[3][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_3__ap[2]), .CK(n_0_33), .Q(registers_3__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_727 (.A1(registers_19__ap[2]), .A2(n_1_0_1295), .B1( + n_1_0_1257), .B2(registers_3__ap[2]), .ZN(n_1_0_692)); + NAND3_X1_LVT i_1_0_726 (.A1(n_1_0_694), .A2(n_1_0_693), .A3(n_1_0_692), + .ZN(n_1_0_691)); + SDFF_X1_LVT \registers_reg[23][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_23__ap[2]), .CK(n_0_53), .Q(registers_23__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[2][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_2__ap[2]), .CK(n_0_32), .Q(registers_2__ap[2]), .QN()); + AOI221_X1_LVT i_1_0_725 (.A(n_1_0_691), .B1(n_1_0_1264), .B2( + registers_23__ap[2]), .C1(registers_2__ap[2]), .C2(n_1_0_1268), .ZN( + n_1_0_690)); + NAND4_X1_LVT i_1_0_724 (.A1(n_1_0_705), .A2(n_1_0_700), .A3(n_1_0_695), + .A4(n_1_0_690), .ZN(RRs1[2])); + AND2_X1_LVT i_0_0_1 (.A1(n_0_0_16), .A2(WRd[1]), .ZN(registers[1])); + SDFF_X1_LVT \registers_reg[13][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_13__ap[1]), .CK(n_0_43), .Q(registers_13__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[21][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_21__ap[1]), .CK(n_0_51), .Q(registers_21__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_720 (.A1(registers_13__ap[1]), .A2(n_1_0_1277), .B1( + n_1_0_1259), .B2(registers_21__ap[1]), .ZN(n_1_0_686)); + SDFF_X1_LVT \registers_reg[29][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_29__ap[1]), .CK(n_0_59), .Q(registers_29__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[23][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_23__ap[1]), .CK(n_0_53), .Q(registers_23__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_723 (.A1(registers_29__ap[1]), .A2(n_1_0_1276), .B1( + n_1_0_1264), .B2(registers_23__ap[1]), .ZN(n_1_0_689)); + SDFF_X1_LVT \registers_reg[24][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_24__ap[1]), .CK(n_0_54), .Q(registers_24__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[20][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_20__ap[1]), .CK(n_0_50), .Q(registers_20__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_719 (.A1(registers_24__ap[1]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[1]), .ZN(n_1_0_685)); + SDFF_X1_LVT \registers_reg[7][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_7__ap[1]), .CK(n_0_37), .Q(registers_7__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[3][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_3__ap[1]), .CK(n_0_33), .Q(registers_3__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_722 (.A1(registers_7__ap[1]), .A2(n_1_0_1263), .B1( + n_1_0_1257), .B2(registers_3__ap[1]), .ZN(n_1_0_688)); + INV_X1_LVT i_1_0_721 (.A(n_1_0_688), .ZN(n_1_0_687)); + SDFF_X1_LVT \registers_reg[31][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_31__ap[1]), .CK(n_0_61), .Q(registers_31__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[4][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_4__ap[1]), .CK(n_0_34), .Q(registers_4__ap[1]), .QN()); + AOI221_X1_LVT i_1_0_718 (.A(n_1_0_687), .B1(n_1_0_1266), .B2( + registers_31__ap[1]), .C1(registers_4__ap[1]), .C2(n_1_0_1278), .ZN( + n_1_0_684)); + SDFF_X1_LVT \registers_reg[10][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_10__ap[1]), .CK(n_0_40), .Q(registers_10__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[26][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_26__ap[1]), .CK(n_0_56), .Q(registers_26__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[25][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_25__ap[1]), .CK(n_0_55), .Q(registers_25__ap[1]), .QN()); + AOI222_X1_LVT i_1_0_717 (.A1(registers_10__ap[1]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[1]), .C1(registers_25__ap[1]), .C2( + n_1_0_1269), .ZN(n_1_0_683)); + NAND4_X1_LVT i_1_0_716 (.A1(n_1_0_689), .A2(n_1_0_685), .A3(n_1_0_684), + .A4(n_1_0_683), .ZN(n_1_0_682)); + SDFF_X1_LVT \registers_reg[8][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_8__ap[1]), .CK(n_0_38), .Q(registers_8__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[28][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_28__ap[1]), .CK(n_0_58), .Q(registers_28__ap[1]), .QN()); + AOI221_X1_LVT i_1_0_715 (.A(n_1_0_682), .B1(n_1_0_1282), .B2( + registers_8__ap[1]), .C1(registers_28__ap[1]), .C2(n_1_0_1283), .ZN( + n_1_0_681)); + SDFF_X1_LVT \registers_reg[18][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_18__ap[1]), .CK(n_0_48), .Q(registers_18__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[30][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_30__ap[1]), .CK(n_0_60), .Q(registers_30__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_714 (.A1(registers_18__ap[1]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[1]), .ZN(n_1_0_680)); + SDFF_X1_LVT \registers_reg[17][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_17__ap[1]), .CK(n_0_47), .Q(registers_17__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[12][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_12__ap[1]), .CK(n_0_42), .Q(registers_12__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_713 (.A1(registers_17__ap[1]), .A2(n_1_0_1271), .B1( + n_1_0_1260), .B2(registers_12__ap[1]), .ZN(n_1_0_679)); + SDFF_X1_LVT \registers_reg[15][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_15__ap[1]), .CK(n_0_45), .Q(registers_15__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[5][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_5__ap[1]), .CK(n_0_35), .Q(registers_5__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_712 (.A1(registers_15__ap[1]), .A2(n_1_0_1286), .B1( + n_1_0_1273), .B2(registers_5__ap[1]), .ZN(n_1_0_678)); + NAND3_X1_LVT i_1_0_711 (.A1(n_1_0_680), .A2(n_1_0_679), .A3(n_1_0_678), + .ZN(n_1_0_677)); + SDFF_X1_LVT \registers_reg[22][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_22__ap[1]), .CK(n_0_52), .Q(registers_22__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[16][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_16__ap[1]), .CK(n_0_46), .Q(registers_16__ap[1]), .QN()); + AOI221_X1_LVT i_1_0_710 (.A(n_1_0_677), .B1(n_1_0_1294), .B2( + registers_22__ap[1]), .C1(registers_16__ap[1]), .C2(n_1_0_1267), .ZN( + n_1_0_676)); + SDFF_X1_LVT \registers_reg[9][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_9__ap[1]), .CK(n_0_39), .Q(registers_9__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[1][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_1__ap[1]), .CK(n_0_0), .Q(registers_1__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_709 (.A1(registers_9__ap[1]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[1]), .ZN(n_1_0_675)); + SDFF_X1_LVT \registers_reg[6][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_6__ap[1]), .CK(n_0_36), .Q(registers_6__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[14][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_14__ap[1]), .CK(n_0_44), .Q(registers_14__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_708 (.A1(registers_6__ap[1]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[1]), .ZN(n_1_0_674)); + SDFF_X1_LVT \registers_reg[19][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_19__ap[1]), .CK(n_0_49), .Q(registers_19__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[2][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_2__ap[1]), .CK(n_0_32), .Q(registers_2__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_707 (.A1(registers_19__ap[1]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[1]), .ZN(n_1_0_673)); + NAND3_X1_LVT i_1_0_706 (.A1(n_1_0_675), .A2(n_1_0_674), .A3(n_1_0_673), + .ZN(n_1_0_672)); + SDFF_X1_LVT \registers_reg[11][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_11__ap[1]), .CK(n_0_41), .Q(registers_11__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[27][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_27__ap[1]), .CK(n_0_57), .Q(registers_27__ap[1]), .QN()); + AOI221_X1_LVT i_1_0_705 (.A(n_1_0_672), .B1(n_1_0_1270), .B2( + registers_11__ap[1]), .C1(registers_27__ap[1]), .C2(n_1_0_1279), .ZN( + n_1_0_671)); + NAND4_X1_LVT i_1_0_704 (.A1(n_1_0_686), .A2(n_1_0_681), .A3(n_1_0_676), + .A4(n_1_0_671), .ZN(RRs1[1])); + AND2_X1_LVT i_0_0_0 (.A1(n_0_0_16), .A2(WRd[0]), .ZN(registers[0])); + SDFF_X1_LVT \registers_reg[13][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_13__ap[0]), .CK(n_0_43), .Q(registers_13__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[21][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_21__ap[0]), .CK(n_0_51), .Q(registers_21__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_703 (.A1(registers_13__ap[0]), .A2(n_1_0_1277), .B1( + n_1_0_1259), .B2(registers_21__ap[0]), .ZN(n_1_0_670)); + SDFF_X1_LVT \registers_reg[10][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_10__ap[0]), .CK(n_0_40), .Q(registers_10__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[26][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_26__ap[0]), .CK(n_0_56), .Q(registers_26__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[25][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_25__ap[0]), .CK(n_0_55), .Q(registers_25__ap[0]), .QN()); + AOI222_X1_LVT i_1_0_702 (.A1(registers_10__ap[0]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[0]), .C1(registers_25__ap[0]), .C2( + n_1_0_1269), .ZN(n_1_0_669)); + SDFF_X1_LVT \registers_reg[28][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_28__ap[0]), .CK(n_0_58), .Q(registers_28__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[8][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_8__ap[0]), .CK(n_0_38), .Q(registers_8__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_701 (.A1(registers_28__ap[0]), .A2(n_1_0_1283), .B1( + n_1_0_1282), .B2(registers_8__ap[0]), .ZN(n_1_0_668)); + SDFF_X1_LVT \registers_reg[24][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_24__ap[0]), .CK(n_0_54), .Q(registers_24__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[20][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_20__ap[0]), .CK(n_0_50), .Q(registers_20__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_700 (.A1(registers_24__ap[0]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[0]), .ZN(n_1_0_667)); + SDFF_X1_LVT \registers_reg[7][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_7__ap[0]), .CK(n_0_37), .Q(registers_7__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[3][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_3__ap[0]), .CK(n_0_33), .Q(registers_3__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_699 (.A1(registers_7__ap[0]), .A2(n_1_0_1263), .B1( + n_1_0_1257), .B2(registers_3__ap[0]), .ZN(n_1_0_666)); + SDFF_X1_LVT \registers_reg[17][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_17__ap[0]), .CK(n_0_47), .Q(registers_17__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[31][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_31__ap[0]), .CK(n_0_61), .Q(registers_31__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_698 (.A1(registers_17__ap[0]), .A2(n_1_0_1271), .B1( + n_1_0_1266), .B2(registers_31__ap[0]), .ZN(n_1_0_665)); + SDFF_X1_LVT \registers_reg[29][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_29__ap[0]), .CK(n_0_59), .Q(registers_29__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[23][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_23__ap[0]), .CK(n_0_53), .Q(registers_23__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_697 (.A1(registers_29__ap[0]), .A2(n_1_0_1276), .B1( + n_1_0_1264), .B2(registers_23__ap[0]), .ZN(n_1_0_664)); + NAND4_X1_LVT i_1_0_696 (.A1(n_1_0_667), .A2(n_1_0_666), .A3(n_1_0_665), + .A4(n_1_0_664), .ZN(n_1_0_663)); + SDFF_X1_LVT \registers_reg[18][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_18__ap[0]), .CK(n_0_48), .Q(registers_18__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[30][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_30__ap[0]), .CK(n_0_60), .Q(registers_30__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_695 (.A1(registers_18__ap[0]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[0]), .ZN(n_1_0_662)); + SDFF_X1_LVT \registers_reg[4][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_4__ap[0]), .CK(n_0_34), .Q(registers_4__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[12][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_12__ap[0]), .CK(n_0_42), .Q(registers_12__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_694 (.A1(registers_4__ap[0]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[0]), .ZN(n_1_0_661)); + SDFF_X1_LVT \registers_reg[15][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_15__ap[0]), .CK(n_0_45), .Q(registers_15__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[16][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_16__ap[0]), .CK(n_0_46), .Q(registers_16__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_693 (.A1(registers_15__ap[0]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[0]), .ZN(n_1_0_660)); + SDFF_X1_LVT \registers_reg[22][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_22__ap[0]), .CK(n_0_52), .Q(registers_22__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[5][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_5__ap[0]), .CK(n_0_35), .Q(registers_5__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_692 (.A1(registers_22__ap[0]), .A2(n_1_0_1294), .B1( + n_1_0_1273), .B2(registers_5__ap[0]), .ZN(n_1_0_659)); + NAND4_X1_LVT i_1_0_691 (.A1(n_1_0_662), .A2(n_1_0_661), .A3(n_1_0_660), + .A4(n_1_0_659), .ZN(n_1_0_658)); + SDFF_X1_LVT \registers_reg[19][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_19__ap[0]), .CK(n_0_49), .Q(registers_19__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[2][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_2__ap[0]), .CK(n_0_32), .Q(registers_2__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_690 (.A1(registers_19__ap[0]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[0]), .ZN(n_1_0_657)); + SDFF_X1_LVT \registers_reg[9][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_9__ap[0]), .CK(n_0_39), .Q(registers_9__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[1][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_1__ap[0]), .CK(n_0_0), .Q(registers_1__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_689 (.A1(registers_9__ap[0]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[0]), .ZN(n_1_0_656)); + SDFF_X1_LVT \registers_reg[6][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_6__ap[0]), .CK(n_0_36), .Q(registers_6__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[14][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_14__ap[0]), .CK(n_0_44), .Q(registers_14__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_688 (.A1(registers_6__ap[0]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[0]), .ZN(n_1_0_655)); + SDFF_X1_LVT \registers_reg[27][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_27__ap[0]), .CK(n_0_57), .Q(registers_27__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[11][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_11__ap[0]), .CK(n_0_41), .Q(registers_11__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_687 (.A1(registers_27__ap[0]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[0]), .ZN(n_1_0_654)); + NAND4_X1_LVT i_1_0_686 (.A1(n_1_0_657), .A2(n_1_0_656), .A3(n_1_0_655), + .A4(n_1_0_654), .ZN(n_1_0_653)); + NOR3_X1_LVT i_1_0_685 (.A1(n_1_0_663), .A2(n_1_0_658), .A3(n_1_0_653), + .ZN(n_1_0_652)); + NAND4_X1_LVT i_1_0_684 (.A1(n_1_0_670), .A2(n_1_0_669), .A3(n_1_0_668), + .A4(n_1_0_652), .ZN(RRs1[0])); + INV_X1_LVT i_1_0_1366 (.A(Rs2[1]), .ZN(n_1_0_1302)); + NAND3_X1_LVT i_1_0_683 (.A1(n_1_0_1302), .A2(Rs2[4]), .A3(Rs2[2]), .ZN( + n_1_0_651)); + INV_X1_LVT i_1_0_1369 (.A(Rs2[3]), .ZN(n_1_0_1305)); + OR2_X1_LVT i_1_0_673 (.A1(n_1_0_1305), .A2(Rs2[0]), .ZN(n_1_0_641)); + NOR2_X1_LVT i_1_0_666 (.A1(n_1_0_651), .A2(n_1_0_641), .ZN(n_1_0_634)); + NAND2_X1_LVT i_1_0_677 (.A1(n_1_0_1305), .A2(Rs2[0]), .ZN(n_1_0_645)); + INV_X1_LVT i_1_0_1368 (.A(Rs2[2]), .ZN(n_1_0_1304)); + NAND3_X1_LVT i_1_0_662 (.A1(n_1_0_1304), .A2(n_1_0_1302), .A3(Rs2[4]), + .ZN(n_1_0_630)); + NOR2_X1_LVT i_1_0_661 (.A1(n_1_0_645), .A2(n_1_0_630), .ZN(n_1_0_629)); + AOI22_X1_LVT i_1_0_641 (.A1(registers_28__ap[31]), .A2(n_1_0_634), .B1( + n_1_0_629), .B2(registers_17__ap[31]), .ZN(n_1_0_609)); + NAND3_X1_LVT i_1_0_680 (.A1(n_1_0_1304), .A2(Rs2[4]), .A3(Rs2[1]), .ZN( + n_1_0_648)); + NOR2_X1_LVT i_1_0_672 (.A1(n_1_0_648), .A2(n_1_0_641), .ZN(n_1_0_640)); + INV_X1_LVT i_1_0_1367 (.A(Rs2[4]), .ZN(n_1_0_1303)); + NAND3_X1_LVT i_1_0_657 (.A1(n_1_0_1304), .A2(n_1_0_1303), .A3(Rs2[1]), + .ZN(n_1_0_625)); + NOR2_X1_LVT i_1_0_656 (.A1(n_1_0_641), .A2(n_1_0_625), .ZN(n_1_0_624)); + NOR4_X1_LVT i_1_0_658 (.A1(n_1_0_641), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), + .ZN(n_1_0_626)); + AOI222_X1_LVT i_1_0_640 (.A1(registers_26__ap[31]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[31]), .C1(n_1_0_626), .C2( + registers_8__ap[31]), .ZN(n_1_0_608)); + NAND2_X1_LVT i_1_0_682 (.A1(Rs2[0]), .A2(Rs2[3]), .ZN(n_1_0_650)); + NOR2_X1_LVT i_1_0_681 (.A1(n_1_0_651), .A2(n_1_0_650), .ZN(n_1_0_649)); + NOR4_X1_LVT i_1_0_649 (.A1(n_1_0_650), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), + .ZN(n_1_0_617)); + AOI22_X1_LVT i_1_0_639 (.A1(registers_29__ap[31]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[31]), .ZN(n_1_0_607)); + NOR4_X1_LVT i_1_0_676 (.A1(n_1_0_645), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), + .ZN(n_1_0_644)); + OR2_X1_LVT i_1_0_679 (.A1(Rs2[0]), .A2(Rs2[3]), .ZN(n_1_0_647)); + NAND3_X1_LVT i_1_0_660 (.A1(n_1_0_1303), .A2(Rs2[1]), .A3(Rs2[2]), .ZN( + n_1_0_628)); + NOR2_X1_LVT i_1_0_648 (.A1(n_1_0_647), .A2(n_1_0_628), .ZN(n_1_0_616)); + AOI22_X1_LVT i_1_0_638 (.A1(registers_1__ap[31]), .A2(n_1_0_644), .B1( + n_1_0_616), .B2(registers_6__ap[31]), .ZN(n_1_0_606)); + NOR2_X1_LVT i_1_0_655 (.A1(n_1_0_645), .A2(n_1_0_628), .ZN(n_1_0_623)); + NAND3_X1_LVT i_1_0_675 (.A1(Rs2[2]), .A2(Rs2[4]), .A3(Rs2[1]), .ZN(n_1_0_643)); + NOR2_X1_LVT i_1_0_647 (.A1(n_1_0_645), .A2(n_1_0_643), .ZN(n_1_0_615)); + AOI22_X1_LVT i_1_0_637 (.A1(registers_7__ap[31]), .A2(n_1_0_623), .B1( + n_1_0_615), .B2(registers_23__ap[31]), .ZN(n_1_0_605)); + NOR2_X1_LVT i_1_0_665 (.A1(n_1_0_648), .A2(n_1_0_645), .ZN(n_1_0_633)); + NOR2_X1_LVT i_1_0_646 (.A1(n_1_0_647), .A2(n_1_0_630), .ZN(n_1_0_614)); + AOI22_X1_LVT i_1_0_636 (.A1(registers_19__ap[31]), .A2(n_1_0_633), .B1( + n_1_0_614), .B2(registers_16__ap[31]), .ZN(n_1_0_604)); + NOR2_X1_LVT i_1_0_669 (.A1(n_1_0_650), .A2(n_1_0_643), .ZN(n_1_0_637)); + NAND3_X1_LVT i_1_0_671 (.A1(n_1_0_1303), .A2(n_1_0_1302), .A3(Rs2[2]), + .ZN(n_1_0_639)); + NOR2_X1_LVT i_1_0_667 (.A1(n_1_0_645), .A2(n_1_0_639), .ZN(n_1_0_635)); + AOI22_X1_LVT i_1_0_635 (.A1(registers_31__ap[31]), .A2(n_1_0_637), .B1( + n_1_0_635), .B2(registers_5__ap[31]), .ZN(n_1_0_603)); + NAND4_X1_LVT i_1_0_634 (.A1(n_1_0_606), .A2(n_1_0_605), .A3(n_1_0_604), + .A4(n_1_0_603), .ZN(n_1_0_602)); + NOR2_X1_LVT i_1_0_678 (.A1(n_1_0_648), .A2(n_1_0_647), .ZN(n_1_0_646)); + NOR2_X1_LVT i_1_0_654 (.A1(n_1_0_643), .A2(n_1_0_641), .ZN(n_1_0_622)); + AOI22_X1_LVT i_1_0_633 (.A1(registers_18__ap[31]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[31]), .ZN(n_1_0_601)); + NOR2_X1_LVT i_1_0_670 (.A1(n_1_0_647), .A2(n_1_0_639), .ZN(n_1_0_638)); + NOR2_X1_LVT i_1_0_645 (.A1(n_1_0_651), .A2(n_1_0_647), .ZN(n_1_0_613)); + AOI22_X1_LVT i_1_0_632 (.A1(registers_4__ap[31]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[31]), .ZN(n_1_0_600)); + NOR2_X1_LVT i_1_0_674 (.A1(n_1_0_647), .A2(n_1_0_643), .ZN(n_1_0_642)); + NOR2_X1_LVT i_1_0_644 (.A1(n_1_0_651), .A2(n_1_0_645), .ZN(n_1_0_612)); + AOI22_X1_LVT i_1_0_631 (.A1(registers_22__ap[31]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[31]), .ZN(n_1_0_599)); + NOR2_X1_LVT i_1_0_664 (.A1(n_1_0_641), .A2(n_1_0_639), .ZN(n_1_0_632)); + NOR2_X1_LVT i_1_0_653 (.A1(n_1_0_641), .A2(n_1_0_630), .ZN(n_1_0_621)); + AOI22_X1_LVT i_1_0_630 (.A1(registers_12__ap[31]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[31]), .ZN(n_1_0_598)); + NAND4_X1_LVT i_1_0_629 (.A1(n_1_0_601), .A2(n_1_0_600), .A3(n_1_0_599), + .A4(n_1_0_598), .ZN(n_1_0_597)); + NOR2_X1_LVT i_1_0_663 (.A1(n_1_0_650), .A2(n_1_0_639), .ZN(n_1_0_631)); + NOR2_X1_LVT i_1_0_652 (.A1(n_1_0_650), .A2(n_1_0_630), .ZN(n_1_0_620)); + AOI22_X1_LVT i_1_0_628 (.A1(registers_13__ap[31]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[31]), .ZN(n_1_0_596)); + NOR2_X1_LVT i_1_0_659 (.A1(n_1_0_650), .A2(n_1_0_628), .ZN(n_1_0_627)); + NOR2_X1_LVT i_1_0_651 (.A1(n_1_0_641), .A2(n_1_0_628), .ZN(n_1_0_619)); + AOI22_X1_LVT i_1_0_627 (.A1(registers_15__ap[31]), .A2(n_1_0_627), .B1( + n_1_0_619), .B2(registers_14__ap[31]), .ZN(n_1_0_595)); + NOR2_X1_LVT i_1_0_668 (.A1(n_1_0_650), .A2(n_1_0_648), .ZN(n_1_0_636)); + NOR2_X1_LVT i_1_0_643 (.A1(n_1_0_650), .A2(n_1_0_625), .ZN(n_1_0_611)); + AOI22_X1_LVT i_1_0_626 (.A1(registers_27__ap[31]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[31]), .ZN(n_1_0_594)); + NOR2_X1_LVT i_1_0_650 (.A1(n_1_0_647), .A2(n_1_0_625), .ZN(n_1_0_618)); + NOR2_X1_LVT i_1_0_642 (.A1(n_1_0_645), .A2(n_1_0_625), .ZN(n_1_0_610)); + AOI22_X1_LVT i_1_0_625 (.A1(registers_2__ap[31]), .A2(n_1_0_618), .B1( + n_1_0_610), .B2(registers_3__ap[31]), .ZN(n_1_0_593)); + NAND4_X1_LVT i_1_0_624 (.A1(n_1_0_596), .A2(n_1_0_595), .A3(n_1_0_594), + .A4(n_1_0_593), .ZN(n_1_0_592)); + NOR3_X1_LVT i_1_0_623 (.A1(n_1_0_602), .A2(n_1_0_597), .A3(n_1_0_592), + .ZN(n_1_0_591)); + NAND4_X1_LVT i_1_0_622 (.A1(n_1_0_609), .A2(n_1_0_608), .A3(n_1_0_607), + .A4(n_1_0_591), .ZN(RRs2[31])); + AOI22_X1_LVT i_1_0_620 (.A1(registers_29__ap[30]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[30]), .ZN(n_1_0_589)); + AOI22_X1_LVT i_1_0_621 (.A1(registers_7__ap[30]), .A2(n_1_0_623), .B1( + n_1_0_615), .B2(registers_23__ap[30]), .ZN(n_1_0_590)); + AOI22_X1_LVT i_1_0_619 (.A1(registers_1__ap[30]), .A2(n_1_0_644), .B1( + n_1_0_616), .B2(registers_6__ap[30]), .ZN(n_1_0_588)); + AOI22_X1_LVT i_1_0_618 (.A1(registers_5__ap[30]), .A2(n_1_0_635), .B1( + n_1_0_633), .B2(registers_19__ap[30]), .ZN(n_1_0_587)); + NAND3_X1_LVT i_1_0_617 (.A1(n_1_0_590), .A2(n_1_0_588), .A3(n_1_0_587), + .ZN(n_1_0_586)); + AOI221_X1_LVT i_1_0_616 (.A(n_1_0_586), .B1(n_1_0_637), .B2( + registers_31__ap[30]), .C1(registers_16__ap[30]), .C2(n_1_0_614), .ZN( + n_1_0_585)); + AOI222_X1_LVT i_1_0_615 (.A1(registers_26__ap[30]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[30]), .C1(n_1_0_626), .C2( + registers_8__ap[30]), .ZN(n_1_0_584)); + NAND3_X1_LVT i_1_0_614 (.A1(n_1_0_589), .A2(n_1_0_585), .A3(n_1_0_584), + .ZN(n_1_0_583)); + AOI221_X1_LVT i_1_0_613 (.A(n_1_0_583), .B1(n_1_0_629), .B2( + registers_17__ap[30]), .C1(registers_28__ap[30]), .C2(n_1_0_634), .ZN( + n_1_0_582)); + AOI22_X1_LVT i_1_0_612 (.A1(registers_18__ap[30]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[30]), .ZN(n_1_0_581)); + AOI22_X1_LVT i_1_0_611 (.A1(registers_4__ap[30]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[30]), .ZN(n_1_0_580)); + AOI22_X1_LVT i_1_0_610 (.A1(registers_22__ap[30]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[30]), .ZN(n_1_0_579)); + NAND3_X1_LVT i_1_0_609 (.A1(n_1_0_581), .A2(n_1_0_580), .A3(n_1_0_579), + .ZN(n_1_0_578)); + AOI221_X1_LVT i_1_0_608 (.A(n_1_0_578), .B1(n_1_0_621), .B2( + registers_24__ap[30]), .C1(registers_12__ap[30]), .C2(n_1_0_632), .ZN( + n_1_0_577)); + AOI22_X1_LVT i_1_0_607 (.A1(registers_13__ap[30]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[30]), .ZN(n_1_0_576)); + AOI22_X1_LVT i_1_0_606 (.A1(registers_15__ap[30]), .A2(n_1_0_627), .B1( + n_1_0_619), .B2(registers_14__ap[30]), .ZN(n_1_0_575)); + AOI22_X1_LVT i_1_0_605 (.A1(registers_27__ap[30]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[30]), .ZN(n_1_0_574)); + NAND3_X1_LVT i_1_0_604 (.A1(n_1_0_576), .A2(n_1_0_575), .A3(n_1_0_574), + .ZN(n_1_0_573)); + AOI221_X1_LVT i_1_0_603 (.A(n_1_0_573), .B1(n_1_0_610), .B2( + registers_3__ap[30]), .C1(registers_2__ap[30]), .C2(n_1_0_618), .ZN( + n_1_0_572)); + NAND3_X1_LVT i_1_0_602 (.A1(n_1_0_582), .A2(n_1_0_577), .A3(n_1_0_572), + .ZN(RRs2[30])); + AOI22_X1_LVT i_1_0_600 (.A1(registers_28__ap[29]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[29]), .ZN(n_1_0_570)); + AOI22_X1_LVT i_1_0_601 (.A1(registers_31__ap[29]), .A2(n_1_0_637), .B1( + n_1_0_627), .B2(registers_15__ap[29]), .ZN(n_1_0_571)); + AOI22_X1_LVT i_1_0_599 (.A1(registers_24__ap[29]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[29]), .ZN(n_1_0_569)); + AOI22_X1_LVT i_1_0_598 (.A1(registers_19__ap[29]), .A2(n_1_0_633), .B1( + n_1_0_629), .B2(registers_17__ap[29]), .ZN(n_1_0_568)); + NAND3_X1_LVT i_1_0_597 (.A1(n_1_0_571), .A2(n_1_0_569), .A3(n_1_0_568), + .ZN(n_1_0_567)); + AOI221_X1_LVT i_1_0_596 (.A(n_1_0_567), .B1(n_1_0_615), .B2( + registers_23__ap[29]), .C1(registers_29__ap[29]), .C2(n_1_0_649), .ZN( + n_1_0_566)); + AOI222_X1_LVT i_1_0_595 (.A1(registers_26__ap[29]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[29]), .C1(n_1_0_620), .C2( + registers_25__ap[29]), .ZN(n_1_0_565)); + NAND3_X1_LVT i_1_0_594 (.A1(n_1_0_570), .A2(n_1_0_566), .A3(n_1_0_565), + .ZN(n_1_0_564)); + AOI221_X1_LVT i_1_0_593 (.A(n_1_0_564), .B1(n_1_0_612), .B2( + registers_21__ap[29]), .C1(registers_13__ap[29]), .C2(n_1_0_631), .ZN( + n_1_0_563)); + AOI22_X1_LVT i_1_0_592 (.A1(registers_18__ap[29]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[29]), .ZN(n_1_0_562)); + AOI22_X1_LVT i_1_0_591 (.A1(registers_4__ap[29]), .A2(n_1_0_638), .B1( + n_1_0_632), .B2(registers_12__ap[29]), .ZN(n_1_0_561)); + AOI22_X1_LVT i_1_0_590 (.A1(registers_7__ap[29]), .A2(n_1_0_623), .B1( + n_1_0_614), .B2(registers_16__ap[29]), .ZN(n_1_0_560)); + NAND3_X1_LVT i_1_0_589 (.A1(n_1_0_562), .A2(n_1_0_561), .A3(n_1_0_560), + .ZN(n_1_0_559)); + AOI221_X1_LVT i_1_0_588 (.A(n_1_0_559), .B1(n_1_0_642), .B2( + registers_22__ap[29]), .C1(registers_5__ap[29]), .C2(n_1_0_635), .ZN( + n_1_0_558)); + AOI22_X1_LVT i_1_0_587 (.A1(registers_1__ap[29]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[29]), .ZN(n_1_0_557)); + AOI22_X1_LVT i_1_0_586 (.A1(registers_14__ap[29]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[29]), .ZN(n_1_0_556)); + AOI22_X1_LVT i_1_0_585 (.A1(registers_27__ap[29]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[29]), .ZN(n_1_0_555)); + NAND3_X1_LVT i_1_0_584 (.A1(n_1_0_557), .A2(n_1_0_556), .A3(n_1_0_555), + .ZN(n_1_0_554)); + AOI221_X1_LVT i_1_0_583 (.A(n_1_0_554), .B1(n_1_0_610), .B2( + registers_3__ap[29]), .C1(registers_2__ap[29]), .C2(n_1_0_618), .ZN( + n_1_0_553)); + NAND3_X1_LVT i_1_0_582 (.A1(n_1_0_563), .A2(n_1_0_558), .A3(n_1_0_553), + .ZN(RRs2[29])); + AOI22_X1_LVT i_1_0_581 (.A1(registers_5__ap[28]), .A2(n_1_0_635), .B1( + n_1_0_634), .B2(registers_28__ap[28]), .ZN(n_1_0_552)); + AOI222_X1_LVT i_1_0_580 (.A1(registers_26__ap[28]), .A2(n_1_0_640), .B1( + n_1_0_633), .B2(registers_19__ap[28]), .C1(n_1_0_626), .C2( + registers_8__ap[28]), .ZN(n_1_0_551)); + AOI22_X1_LVT i_1_0_579 (.A1(registers_2__ap[28]), .A2(n_1_0_618), .B1( + n_1_0_617), .B2(registers_9__ap[28]), .ZN(n_1_0_550)); + AOI22_X1_LVT i_1_0_578 (.A1(registers_7__ap[28]), .A2(n_1_0_623), .B1( + n_1_0_612), .B2(registers_21__ap[28]), .ZN(n_1_0_549)); + AOI22_X1_LVT i_1_0_577 (.A1(registers_16__ap[28]), .A2(n_1_0_614), .B1( + n_1_0_611), .B2(registers_11__ap[28]), .ZN(n_1_0_548)); + AOI22_X1_LVT i_1_0_576 (.A1(registers_31__ap[28]), .A2(n_1_0_637), .B1( + n_1_0_619), .B2(registers_14__ap[28]), .ZN(n_1_0_547)); + AOI22_X1_LVT i_1_0_575 (.A1(registers_15__ap[28]), .A2(n_1_0_627), .B1( + n_1_0_610), .B2(registers_3__ap[28]), .ZN(n_1_0_546)); + NAND4_X1_LVT i_1_0_574 (.A1(n_1_0_549), .A2(n_1_0_548), .A3(n_1_0_547), + .A4(n_1_0_546), .ZN(n_1_0_545)); + AOI22_X1_LVT i_1_0_573 (.A1(registers_22__ap[28]), .A2(n_1_0_642), .B1( + n_1_0_622), .B2(registers_30__ap[28]), .ZN(n_1_0_544)); + AOI22_X1_LVT i_1_0_572 (.A1(registers_4__ap[28]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[28]), .ZN(n_1_0_543)); + AOI22_X1_LVT i_1_0_571 (.A1(registers_29__ap[28]), .A2(n_1_0_649), .B1( + n_1_0_644), .B2(registers_1__ap[28]), .ZN(n_1_0_542)); + AOI22_X1_LVT i_1_0_570 (.A1(registers_12__ap[28]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[28]), .ZN(n_1_0_541)); + NAND4_X1_LVT i_1_0_569 (.A1(n_1_0_544), .A2(n_1_0_543), .A3(n_1_0_542), + .A4(n_1_0_541), .ZN(n_1_0_540)); + AOI22_X1_LVT i_1_0_568 (.A1(registers_13__ap[28]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[28]), .ZN(n_1_0_539)); + AOI22_X1_LVT i_1_0_567 (.A1(registers_17__ap[28]), .A2(n_1_0_629), .B1( + n_1_0_616), .B2(registers_6__ap[28]), .ZN(n_1_0_538)); + AOI22_X1_LVT i_1_0_566 (.A1(registers_10__ap[28]), .A2(n_1_0_624), .B1( + n_1_0_615), .B2(registers_23__ap[28]), .ZN(n_1_0_537)); + AOI22_X1_LVT i_1_0_565 (.A1(registers_18__ap[28]), .A2(n_1_0_646), .B1( + n_1_0_636), .B2(registers_27__ap[28]), .ZN(n_1_0_536)); + NAND4_X1_LVT i_1_0_564 (.A1(n_1_0_539), .A2(n_1_0_538), .A3(n_1_0_537), + .A4(n_1_0_536), .ZN(n_1_0_535)); + NOR3_X1_LVT i_1_0_563 (.A1(n_1_0_545), .A2(n_1_0_540), .A3(n_1_0_535), + .ZN(n_1_0_534)); + NAND4_X1_LVT i_1_0_562 (.A1(n_1_0_552), .A2(n_1_0_551), .A3(n_1_0_550), + .A4(n_1_0_534), .ZN(RRs2[28])); + AOI22_X1_LVT i_1_0_561 (.A1(registers_17__ap[27]), .A2(n_1_0_629), .B1( + n_1_0_612), .B2(registers_21__ap[27]), .ZN(n_1_0_533)); + AOI222_X1_LVT i_1_0_560 (.A1(registers_19__ap[27]), .A2(n_1_0_633), .B1( + n_1_0_631), .B2(registers_13__ap[27]), .C1(registers_30__ap[27]), .C2( + n_1_0_622), .ZN(n_1_0_532)); + AOI22_X1_LVT i_1_0_559 (.A1(registers_1__ap[27]), .A2(n_1_0_644), .B1( + n_1_0_634), .B2(registers_28__ap[27]), .ZN(n_1_0_531)); + AOI22_X1_LVT i_1_0_558 (.A1(registers_24__ap[27]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[27]), .ZN(n_1_0_530)); + AOI22_X1_LVT i_1_0_557 (.A1(registers_15__ap[27]), .A2(n_1_0_627), .B1( + n_1_0_611), .B2(registers_11__ap[27]), .ZN(n_1_0_529)); + AOI22_X1_LVT i_1_0_556 (.A1(registers_4__ap[27]), .A2(n_1_0_638), .B1( + n_1_0_636), .B2(registers_27__ap[27]), .ZN(n_1_0_528)); + AOI22_X1_LVT i_1_0_555 (.A1(registers_31__ap[27]), .A2(n_1_0_637), .B1( + n_1_0_618), .B2(registers_2__ap[27]), .ZN(n_1_0_527)); + NAND4_X1_LVT i_1_0_554 (.A1(n_1_0_530), .A2(n_1_0_529), .A3(n_1_0_528), + .A4(n_1_0_527), .ZN(n_1_0_526)); + AOI22_X1_LVT i_1_0_553 (.A1(registers_18__ap[27]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[27]), .ZN(n_1_0_525)); + AOI22_X1_LVT i_1_0_552 (.A1(registers_5__ap[27]), .A2(n_1_0_635), .B1( + n_1_0_632), .B2(registers_12__ap[27]), .ZN(n_1_0_524)); + AOI22_X1_LVT i_1_0_551 (.A1(registers_6__ap[27]), .A2(n_1_0_616), .B1( + n_1_0_614), .B2(registers_16__ap[27]), .ZN(n_1_0_523)); + AOI22_X1_LVT i_1_0_550 (.A1(registers_22__ap[27]), .A2(n_1_0_642), .B1( + n_1_0_620), .B2(registers_25__ap[27]), .ZN(n_1_0_522)); + NAND4_X1_LVT i_1_0_549 (.A1(n_1_0_525), .A2(n_1_0_524), .A3(n_1_0_523), + .A4(n_1_0_522), .ZN(n_1_0_521)); + AOI22_X1_LVT i_1_0_548 (.A1(registers_29__ap[27]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[27]), .ZN(n_1_0_520)); + AOI22_X1_LVT i_1_0_547 (.A1(registers_7__ap[27]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[27]), .ZN(n_1_0_519)); + AOI22_X1_LVT i_1_0_546 (.A1(registers_8__ap[27]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[27]), .ZN(n_1_0_518)); + AOI22_X1_LVT i_1_0_545 (.A1(registers_10__ap[27]), .A2(n_1_0_624), .B1( + n_1_0_610), .B2(registers_3__ap[27]), .ZN(n_1_0_517)); + NAND4_X1_LVT i_1_0_544 (.A1(n_1_0_520), .A2(n_1_0_519), .A3(n_1_0_518), + .A4(n_1_0_517), .ZN(n_1_0_516)); + NOR3_X1_LVT i_1_0_543 (.A1(n_1_0_526), .A2(n_1_0_521), .A3(n_1_0_516), + .ZN(n_1_0_515)); + NAND4_X1_LVT i_1_0_542 (.A1(n_1_0_533), .A2(n_1_0_532), .A3(n_1_0_531), + .A4(n_1_0_515), .ZN(RRs2[27])); + AOI22_X1_LVT i_1_0_541 (.A1(registers_17__ap[26]), .A2(n_1_0_629), .B1( + n_1_0_612), .B2(registers_21__ap[26]), .ZN(n_1_0_514)); + AOI222_X1_LVT i_1_0_540 (.A1(registers_19__ap[26]), .A2(n_1_0_633), .B1( + n_1_0_622), .B2(registers_30__ap[26]), .C1(n_1_0_631), .C2( + registers_13__ap[26]), .ZN(n_1_0_513)); + AOI22_X1_LVT i_1_0_539 (.A1(registers_1__ap[26]), .A2(n_1_0_644), .B1( + n_1_0_634), .B2(registers_28__ap[26]), .ZN(n_1_0_512)); + AOI22_X1_LVT i_1_0_538 (.A1(registers_24__ap[26]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[26]), .ZN(n_1_0_511)); + AOI22_X1_LVT i_1_0_537 (.A1(registers_15__ap[26]), .A2(n_1_0_627), .B1( + n_1_0_611), .B2(registers_11__ap[26]), .ZN(n_1_0_510)); + AOI22_X1_LVT i_1_0_536 (.A1(registers_4__ap[26]), .A2(n_1_0_638), .B1( + n_1_0_636), .B2(registers_27__ap[26]), .ZN(n_1_0_509)); + AOI22_X1_LVT i_1_0_535 (.A1(registers_31__ap[26]), .A2(n_1_0_637), .B1( + n_1_0_618), .B2(registers_2__ap[26]), .ZN(n_1_0_508)); + NAND4_X1_LVT i_1_0_534 (.A1(n_1_0_511), .A2(n_1_0_510), .A3(n_1_0_509), + .A4(n_1_0_508), .ZN(n_1_0_507)); + AOI22_X1_LVT i_1_0_533 (.A1(registers_18__ap[26]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[26]), .ZN(n_1_0_506)); + AOI22_X1_LVT i_1_0_532 (.A1(registers_5__ap[26]), .A2(n_1_0_635), .B1( + n_1_0_632), .B2(registers_12__ap[26]), .ZN(n_1_0_505)); + AOI22_X1_LVT i_1_0_531 (.A1(registers_6__ap[26]), .A2(n_1_0_616), .B1( + n_1_0_614), .B2(registers_16__ap[26]), .ZN(n_1_0_504)); + AOI22_X1_LVT i_1_0_530 (.A1(registers_22__ap[26]), .A2(n_1_0_642), .B1( + n_1_0_620), .B2(registers_25__ap[26]), .ZN(n_1_0_503)); + NAND4_X1_LVT i_1_0_529 (.A1(n_1_0_506), .A2(n_1_0_505), .A3(n_1_0_504), + .A4(n_1_0_503), .ZN(n_1_0_502)); + AOI22_X1_LVT i_1_0_528 (.A1(registers_29__ap[26]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[26]), .ZN(n_1_0_501)); + AOI22_X1_LVT i_1_0_527 (.A1(registers_7__ap[26]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[26]), .ZN(n_1_0_500)); + AOI22_X1_LVT i_1_0_526 (.A1(registers_8__ap[26]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[26]), .ZN(n_1_0_499)); + AOI22_X1_LVT i_1_0_525 (.A1(registers_10__ap[26]), .A2(n_1_0_624), .B1( + n_1_0_610), .B2(registers_3__ap[26]), .ZN(n_1_0_498)); + NAND4_X1_LVT i_1_0_524 (.A1(n_1_0_501), .A2(n_1_0_500), .A3(n_1_0_499), + .A4(n_1_0_498), .ZN(n_1_0_497)); + NOR3_X1_LVT i_1_0_523 (.A1(n_1_0_507), .A2(n_1_0_502), .A3(n_1_0_497), + .ZN(n_1_0_496)); + NAND4_X1_LVT i_1_0_522 (.A1(n_1_0_514), .A2(n_1_0_513), .A3(n_1_0_512), + .A4(n_1_0_496), .ZN(RRs2[26])); + AOI22_X1_LVT i_1_0_520 (.A1(registers_5__ap[25]), .A2(n_1_0_635), .B1( + n_1_0_634), .B2(registers_28__ap[25]), .ZN(n_1_0_494)); + AOI22_X1_LVT i_1_0_521 (.A1(registers_8__ap[25]), .A2(n_1_0_626), .B1( + n_1_0_620), .B2(registers_25__ap[25]), .ZN(n_1_0_495)); + AOI22_X1_LVT i_1_0_519 (.A1(registers_14__ap[25]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[25]), .ZN(n_1_0_493)); + AOI22_X1_LVT i_1_0_518 (.A1(registers_16__ap[25]), .A2(n_1_0_614), .B1( + n_1_0_611), .B2(registers_11__ap[25]), .ZN(n_1_0_492)); + NAND3_X1_LVT i_1_0_517 (.A1(n_1_0_495), .A2(n_1_0_493), .A3(n_1_0_492), + .ZN(n_1_0_491)); + AOI221_X1_LVT i_1_0_516 (.A(n_1_0_491), .B1(n_1_0_624), .B2( + registers_10__ap[25]), .C1(registers_6__ap[25]), .C2(n_1_0_616), .ZN( + n_1_0_490)); + AOI222_X1_LVT i_1_0_515 (.A1(registers_1__ap[25]), .A2(n_1_0_644), .B1( + n_1_0_640), .B2(registers_26__ap[25]), .C1(n_1_0_622), .C2( + registers_30__ap[25]), .ZN(n_1_0_489)); + NAND2_X1_LVT i_1_0_514 (.A1(n_1_0_490), .A2(n_1_0_489), .ZN(n_1_0_488)); + AOI221_X1_LVT i_1_0_513 (.A(n_1_0_488), .B1(n_1_0_649), .B2( + registers_29__ap[25]), .C1(registers_2__ap[25]), .C2(n_1_0_618), .ZN( + n_1_0_487)); + AOI22_X1_LVT i_1_0_512 (.A1(registers_12__ap[25]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[25]), .ZN(n_1_0_486)); + AOI22_X1_LVT i_1_0_511 (.A1(registers_22__ap[25]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[25]), .ZN(n_1_0_485)); + AOI22_X1_LVT i_1_0_510 (.A1(registers_4__ap[25]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[25]), .ZN(n_1_0_484)); + NAND3_X1_LVT i_1_0_509 (.A1(n_1_0_486), .A2(n_1_0_485), .A3(n_1_0_484), + .ZN(n_1_0_483)); + AOI221_X1_LVT i_1_0_508 (.A(n_1_0_483), .B1(n_1_0_633), .B2( + registers_19__ap[25]), .C1(registers_18__ap[25]), .C2(n_1_0_646), .ZN( + n_1_0_482)); + AOI22_X1_LVT i_1_0_507 (.A1(registers_15__ap[25]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[25]), .ZN(n_1_0_481)); + AOI22_X1_LVT i_1_0_506 (.A1(registers_23__ap[25]), .A2(n_1_0_615), .B1( + n_1_0_610), .B2(registers_3__ap[25]), .ZN(n_1_0_480)); + AOI22_X1_LVT i_1_0_505 (.A1(registers_13__ap[25]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[25]), .ZN(n_1_0_479)); + NAND3_X1_LVT i_1_0_504 (.A1(n_1_0_481), .A2(n_1_0_480), .A3(n_1_0_479), + .ZN(n_1_0_478)); + AOI221_X1_LVT i_1_0_503 (.A(n_1_0_478), .B1(n_1_0_636), .B2( + registers_27__ap[25]), .C1(registers_31__ap[25]), .C2(n_1_0_637), .ZN( + n_1_0_477)); + NAND4_X1_LVT i_1_0_502 (.A1(n_1_0_494), .A2(n_1_0_487), .A3(n_1_0_482), + .A4(n_1_0_477), .ZN(RRs2[25])); + AOI22_X1_LVT i_1_0_501 (.A1(registers_17__ap[24]), .A2(n_1_0_629), .B1( + n_1_0_612), .B2(registers_21__ap[24]), .ZN(n_1_0_476)); + AOI222_X1_LVT i_1_0_500 (.A1(registers_13__ap[24]), .A2(n_1_0_631), .B1( + n_1_0_622), .B2(registers_30__ap[24]), .C1(registers_26__ap[24]), .C2( + n_1_0_640), .ZN(n_1_0_475)); + AOI22_X1_LVT i_1_0_499 (.A1(registers_1__ap[24]), .A2(n_1_0_644), .B1( + n_1_0_634), .B2(registers_28__ap[24]), .ZN(n_1_0_474)); + AOI22_X1_LVT i_1_0_498 (.A1(registers_24__ap[24]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[24]), .ZN(n_1_0_473)); + AOI22_X1_LVT i_1_0_497 (.A1(registers_8__ap[24]), .A2(n_1_0_626), .B1( + n_1_0_616), .B2(registers_6__ap[24]), .ZN(n_1_0_472)); + AOI22_X1_LVT i_1_0_496 (.A1(registers_4__ap[24]), .A2(n_1_0_638), .B1( + n_1_0_611), .B2(registers_11__ap[24]), .ZN(n_1_0_471)); + AOI22_X1_LVT i_1_0_495 (.A1(registers_10__ap[24]), .A2(n_1_0_624), .B1( + n_1_0_618), .B2(registers_2__ap[24]), .ZN(n_1_0_470)); + NAND4_X1_LVT i_1_0_494 (.A1(n_1_0_473), .A2(n_1_0_472), .A3(n_1_0_471), + .A4(n_1_0_470), .ZN(n_1_0_469)); + AOI22_X1_LVT i_1_0_493 (.A1(registers_18__ap[24]), .A2(n_1_0_646), .B1( + n_1_0_633), .B2(registers_19__ap[24]), .ZN(n_1_0_468)); + AOI22_X1_LVT i_1_0_492 (.A1(registers_5__ap[24]), .A2(n_1_0_635), .B1( + n_1_0_632), .B2(registers_12__ap[24]), .ZN(n_1_0_467)); + AOI22_X1_LVT i_1_0_491 (.A1(registers_15__ap[24]), .A2(n_1_0_627), .B1( + n_1_0_614), .B2(registers_16__ap[24]), .ZN(n_1_0_466)); + AOI22_X1_LVT i_1_0_490 (.A1(registers_22__ap[24]), .A2(n_1_0_642), .B1( + n_1_0_620), .B2(registers_25__ap[24]), .ZN(n_1_0_465)); + NAND4_X1_LVT i_1_0_489 (.A1(n_1_0_468), .A2(n_1_0_467), .A3(n_1_0_466), + .A4(n_1_0_465), .ZN(n_1_0_464)); + AOI22_X1_LVT i_1_0_488 (.A1(registers_29__ap[24]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[24]), .ZN(n_1_0_463)); + AOI22_X1_LVT i_1_0_487 (.A1(registers_7__ap[24]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[24]), .ZN(n_1_0_462)); + AOI22_X1_LVT i_1_0_486 (.A1(registers_23__ap[24]), .A2(n_1_0_615), .B1( + n_1_0_610), .B2(registers_3__ap[24]), .ZN(n_1_0_461)); + AOI22_X1_LVT i_1_0_485 (.A1(registers_31__ap[24]), .A2(n_1_0_637), .B1( + n_1_0_636), .B2(registers_27__ap[24]), .ZN(n_1_0_460)); + NAND4_X1_LVT i_1_0_484 (.A1(n_1_0_463), .A2(n_1_0_462), .A3(n_1_0_461), + .A4(n_1_0_460), .ZN(n_1_0_459)); + NOR3_X1_LVT i_1_0_483 (.A1(n_1_0_469), .A2(n_1_0_464), .A3(n_1_0_459), + .ZN(n_1_0_458)); + NAND4_X1_LVT i_1_0_482 (.A1(n_1_0_476), .A2(n_1_0_475), .A3(n_1_0_474), + .A4(n_1_0_458), .ZN(RRs2[24])); + AOI22_X1_LVT i_1_0_481 (.A1(registers_4__ap[23]), .A2(n_1_0_638), .B1( + n_1_0_634), .B2(registers_28__ap[23]), .ZN(n_1_0_457)); + AOI222_X1_LVT i_1_0_480 (.A1(registers_18__ap[23]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[23]), .C1(n_1_0_644), .C2( + registers_1__ap[23]), .ZN(n_1_0_456)); + AOI22_X1_LVT i_1_0_479 (.A1(registers_29__ap[23]), .A2(n_1_0_649), .B1( + n_1_0_618), .B2(registers_2__ap[23]), .ZN(n_1_0_455)); + AOI22_X1_LVT i_1_0_478 (.A1(registers_14__ap[23]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[23]), .ZN(n_1_0_454)); + AOI22_X1_LVT i_1_0_477 (.A1(registers_16__ap[23]), .A2(n_1_0_614), .B1( + n_1_0_611), .B2(registers_11__ap[23]), .ZN(n_1_0_453)); + AOI22_X1_LVT i_1_0_476 (.A1(registers_27__ap[23]), .A2(n_1_0_636), .B1( + n_1_0_620), .B2(registers_25__ap[23]), .ZN(n_1_0_452)); + AOI22_X1_LVT i_1_0_475 (.A1(registers_31__ap[23]), .A2(n_1_0_637), .B1( + n_1_0_616), .B2(registers_6__ap[23]), .ZN(n_1_0_451)); + NAND4_X1_LVT i_1_0_474 (.A1(n_1_0_454), .A2(n_1_0_453), .A3(n_1_0_452), + .A4(n_1_0_451), .ZN(n_1_0_450)); + AOI22_X1_LVT i_1_0_473 (.A1(registers_26__ap[23]), .A2(n_1_0_640), .B1( + n_1_0_633), .B2(registers_19__ap[23]), .ZN(n_1_0_449)); + AOI22_X1_LVT i_1_0_472 (.A1(registers_12__ap[23]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[23]), .ZN(n_1_0_448)); + AOI22_X1_LVT i_1_0_471 (.A1(registers_22__ap[23]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[23]), .ZN(n_1_0_447)); + AOI22_X1_LVT i_1_0_470 (.A1(registers_5__ap[23]), .A2(n_1_0_635), .B1( + n_1_0_613), .B2(registers_20__ap[23]), .ZN(n_1_0_446)); + NAND4_X1_LVT i_1_0_469 (.A1(n_1_0_449), .A2(n_1_0_448), .A3(n_1_0_447), + .A4(n_1_0_446), .ZN(n_1_0_445)); + AOI22_X1_LVT i_1_0_468 (.A1(registers_15__ap[23]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[23]), .ZN(n_1_0_444)); + AOI22_X1_LVT i_1_0_467 (.A1(registers_8__ap[23]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[23]), .ZN(n_1_0_443)); + AOI22_X1_LVT i_1_0_466 (.A1(registers_13__ap[23]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[23]), .ZN(n_1_0_442)); + AOI22_X1_LVT i_1_0_465 (.A1(registers_10__ap[23]), .A2(n_1_0_624), .B1( + n_1_0_610), .B2(registers_3__ap[23]), .ZN(n_1_0_441)); + NAND4_X1_LVT i_1_0_464 (.A1(n_1_0_444), .A2(n_1_0_443), .A3(n_1_0_442), + .A4(n_1_0_441), .ZN(n_1_0_440)); + NOR3_X1_LVT i_1_0_463 (.A1(n_1_0_450), .A2(n_1_0_445), .A3(n_1_0_440), + .ZN(n_1_0_439)); + NAND4_X1_LVT i_1_0_462 (.A1(n_1_0_457), .A2(n_1_0_456), .A3(n_1_0_455), + .A4(n_1_0_439), .ZN(RRs2[23])); + AOI22_X1_LVT i_1_0_460 (.A1(registers_17__ap[22]), .A2(n_1_0_629), .B1( + n_1_0_612), .B2(registers_21__ap[22]), .ZN(n_1_0_437)); + AOI22_X1_LVT i_1_0_461 (.A1(registers_15__ap[22]), .A2(n_1_0_627), .B1( + n_1_0_626), .B2(registers_8__ap[22]), .ZN(n_1_0_438)); + AOI22_X1_LVT i_1_0_459 (.A1(registers_24__ap[22]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[22]), .ZN(n_1_0_436)); + AOI22_X1_LVT i_1_0_458 (.A1(registers_5__ap[22]), .A2(n_1_0_635), .B1( + n_1_0_611), .B2(registers_11__ap[22]), .ZN(n_1_0_435)); + NAND3_X1_LVT i_1_0_457 (.A1(n_1_0_438), .A2(n_1_0_436), .A3(n_1_0_435), + .ZN(n_1_0_434)); + AOI221_X1_LVT i_1_0_456 (.A(n_1_0_434), .B1(n_1_0_618), .B2( + registers_2__ap[22]), .C1(registers_10__ap[22]), .C2(n_1_0_624), .ZN( + n_1_0_433)); + AOI222_X1_LVT i_1_0_455 (.A1(registers_26__ap[22]), .A2(n_1_0_640), .B1( + n_1_0_622), .B2(registers_30__ap[22]), .C1(n_1_0_631), .C2( + registers_13__ap[22]), .ZN(n_1_0_432)); + NAND2_X1_LVT i_1_0_454 (.A1(n_1_0_433), .A2(n_1_0_432), .ZN(n_1_0_431)); + AOI221_X1_LVT i_1_0_453 (.A(n_1_0_431), .B1(n_1_0_644), .B2( + registers_1__ap[22]), .C1(registers_28__ap[22]), .C2(n_1_0_634), .ZN( + n_1_0_430)); + AOI22_X1_LVT i_1_0_452 (.A1(registers_18__ap[22]), .A2(n_1_0_646), .B1( + n_1_0_633), .B2(registers_19__ap[22]), .ZN(n_1_0_429)); + AOI22_X1_LVT i_1_0_451 (.A1(registers_4__ap[22]), .A2(n_1_0_638), .B1( + n_1_0_632), .B2(registers_12__ap[22]), .ZN(n_1_0_428)); + AOI22_X1_LVT i_1_0_450 (.A1(registers_6__ap[22]), .A2(n_1_0_616), .B1( + n_1_0_614), .B2(registers_16__ap[22]), .ZN(n_1_0_427)); + NAND3_X1_LVT i_1_0_449 (.A1(n_1_0_429), .A2(n_1_0_428), .A3(n_1_0_427), + .ZN(n_1_0_426)); + AOI221_X1_LVT i_1_0_448 (.A(n_1_0_426), .B1(n_1_0_620), .B2( + registers_25__ap[22]), .C1(registers_22__ap[22]), .C2(n_1_0_642), .ZN( + n_1_0_425)); + AOI22_X1_LVT i_1_0_447 (.A1(registers_29__ap[22]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[22]), .ZN(n_1_0_424)); + AOI22_X1_LVT i_1_0_446 (.A1(registers_7__ap[22]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[22]), .ZN(n_1_0_423)); + AOI22_X1_LVT i_1_0_445 (.A1(registers_23__ap[22]), .A2(n_1_0_615), .B1( + n_1_0_610), .B2(registers_3__ap[22]), .ZN(n_1_0_422)); + NAND3_X1_LVT i_1_0_444 (.A1(n_1_0_424), .A2(n_1_0_423), .A3(n_1_0_422), + .ZN(n_1_0_421)); + AOI221_X1_LVT i_1_0_443 (.A(n_1_0_421), .B1(n_1_0_636), .B2( + registers_27__ap[22]), .C1(registers_31__ap[22]), .C2(n_1_0_637), .ZN( + n_1_0_420)); + NAND4_X1_LVT i_1_0_442 (.A1(n_1_0_437), .A2(n_1_0_430), .A3(n_1_0_425), + .A4(n_1_0_420), .ZN(RRs2[22])); + AOI22_X1_LVT i_1_0_441 (.A1(registers_5__ap[21]), .A2(n_1_0_635), .B1( + n_1_0_634), .B2(registers_28__ap[21]), .ZN(n_1_0_419)); + AOI222_X1_LVT i_1_0_440 (.A1(registers_1__ap[21]), .A2(n_1_0_644), .B1( + n_1_0_640), .B2(registers_26__ap[21]), .C1(n_1_0_622), .C2( + registers_30__ap[21]), .ZN(n_1_0_418)); + AOI22_X1_LVT i_1_0_439 (.A1(registers_29__ap[21]), .A2(n_1_0_649), .B1( + n_1_0_618), .B2(registers_2__ap[21]), .ZN(n_1_0_417)); + AOI22_X1_LVT i_1_0_438 (.A1(registers_14__ap[21]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[21]), .ZN(n_1_0_416)); + AOI22_X1_LVT i_1_0_437 (.A1(registers_8__ap[21]), .A2(n_1_0_626), .B1( + n_1_0_614), .B2(registers_16__ap[21]), .ZN(n_1_0_415)); + AOI22_X1_LVT i_1_0_436 (.A1(registers_25__ap[21]), .A2(n_1_0_620), .B1( + n_1_0_611), .B2(registers_11__ap[21]), .ZN(n_1_0_414)); + AOI22_X1_LVT i_1_0_435 (.A1(registers_10__ap[21]), .A2(n_1_0_624), .B1( + n_1_0_616), .B2(registers_6__ap[21]), .ZN(n_1_0_413)); + NAND4_X1_LVT i_1_0_434 (.A1(n_1_0_416), .A2(n_1_0_415), .A3(n_1_0_414), + .A4(n_1_0_413), .ZN(n_1_0_412)); + AOI22_X1_LVT i_1_0_433 (.A1(registers_12__ap[21]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[21]), .ZN(n_1_0_411)); + AOI22_X1_LVT i_1_0_432 (.A1(registers_22__ap[21]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[21]), .ZN(n_1_0_410)); + AOI22_X1_LVT i_1_0_431 (.A1(registers_4__ap[21]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[21]), .ZN(n_1_0_409)); + AOI22_X1_LVT i_1_0_430 (.A1(registers_18__ap[21]), .A2(n_1_0_646), .B1( + n_1_0_633), .B2(registers_19__ap[21]), .ZN(n_1_0_408)); + NAND4_X1_LVT i_1_0_429 (.A1(n_1_0_411), .A2(n_1_0_410), .A3(n_1_0_409), + .A4(n_1_0_408), .ZN(n_1_0_407)); + AOI22_X1_LVT i_1_0_428 (.A1(registers_15__ap[21]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[21]), .ZN(n_1_0_406)); + AOI22_X1_LVT i_1_0_427 (.A1(registers_23__ap[21]), .A2(n_1_0_615), .B1( + n_1_0_610), .B2(registers_3__ap[21]), .ZN(n_1_0_405)); + AOI22_X1_LVT i_1_0_426 (.A1(registers_13__ap[21]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[21]), .ZN(n_1_0_404)); + AOI22_X1_LVT i_1_0_425 (.A1(registers_31__ap[21]), .A2(n_1_0_637), .B1( + n_1_0_636), .B2(registers_27__ap[21]), .ZN(n_1_0_403)); + NAND4_X1_LVT i_1_0_424 (.A1(n_1_0_406), .A2(n_1_0_405), .A3(n_1_0_404), + .A4(n_1_0_403), .ZN(n_1_0_402)); + NOR3_X1_LVT i_1_0_423 (.A1(n_1_0_412), .A2(n_1_0_407), .A3(n_1_0_402), + .ZN(n_1_0_401)); + NAND4_X1_LVT i_1_0_422 (.A1(n_1_0_419), .A2(n_1_0_418), .A3(n_1_0_417), + .A4(n_1_0_401), .ZN(RRs2[21])); + AOI22_X1_LVT i_1_0_421 (.A1(registers_17__ap[20]), .A2(n_1_0_629), .B1( + n_1_0_612), .B2(registers_21__ap[20]), .ZN(n_1_0_400)); + AOI222_X1_LVT i_1_0_420 (.A1(registers_13__ap[20]), .A2(n_1_0_631), .B1( + n_1_0_622), .B2(registers_30__ap[20]), .C1(registers_19__ap[20]), .C2( + n_1_0_633), .ZN(n_1_0_399)); + AOI22_X1_LVT i_1_0_419 (.A1(registers_1__ap[20]), .A2(n_1_0_644), .B1( + n_1_0_634), .B2(registers_28__ap[20]), .ZN(n_1_0_398)); + AOI22_X1_LVT i_1_0_418 (.A1(registers_24__ap[20]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[20]), .ZN(n_1_0_397)); + AOI22_X1_LVT i_1_0_417 (.A1(registers_6__ap[20]), .A2(n_1_0_616), .B1( + n_1_0_611), .B2(registers_11__ap[20]), .ZN(n_1_0_396)); + AOI22_X1_LVT i_1_0_416 (.A1(registers_4__ap[20]), .A2(n_1_0_638), .B1( + n_1_0_624), .B2(registers_10__ap[20]), .ZN(n_1_0_395)); + AOI22_X1_LVT i_1_0_415 (.A1(registers_31__ap[20]), .A2(n_1_0_637), .B1( + n_1_0_618), .B2(registers_2__ap[20]), .ZN(n_1_0_394)); + NAND4_X1_LVT i_1_0_414 (.A1(n_1_0_397), .A2(n_1_0_396), .A3(n_1_0_395), + .A4(n_1_0_394), .ZN(n_1_0_393)); + AOI22_X1_LVT i_1_0_413 (.A1(registers_18__ap[20]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[20]), .ZN(n_1_0_392)); + AOI22_X1_LVT i_1_0_412 (.A1(registers_5__ap[20]), .A2(n_1_0_635), .B1( + n_1_0_632), .B2(registers_12__ap[20]), .ZN(n_1_0_391)); + AOI22_X1_LVT i_1_0_411 (.A1(registers_15__ap[20]), .A2(n_1_0_627), .B1( + n_1_0_614), .B2(registers_16__ap[20]), .ZN(n_1_0_390)); + AOI22_X1_LVT i_1_0_410 (.A1(registers_22__ap[20]), .A2(n_1_0_642), .B1( + n_1_0_620), .B2(registers_25__ap[20]), .ZN(n_1_0_389)); + NAND4_X1_LVT i_1_0_409 (.A1(n_1_0_392), .A2(n_1_0_391), .A3(n_1_0_390), + .A4(n_1_0_389), .ZN(n_1_0_388)); + AOI22_X1_LVT i_1_0_408 (.A1(registers_29__ap[20]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[20]), .ZN(n_1_0_387)); + AOI22_X1_LVT i_1_0_407 (.A1(registers_7__ap[20]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[20]), .ZN(n_1_0_386)); + AOI22_X1_LVT i_1_0_406 (.A1(registers_8__ap[20]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[20]), .ZN(n_1_0_385)); + AOI22_X1_LVT i_1_0_405 (.A1(registers_27__ap[20]), .A2(n_1_0_636), .B1( + n_1_0_610), .B2(registers_3__ap[20]), .ZN(n_1_0_384)); + NAND4_X1_LVT i_1_0_404 (.A1(n_1_0_387), .A2(n_1_0_386), .A3(n_1_0_385), + .A4(n_1_0_384), .ZN(n_1_0_383)); + NOR3_X1_LVT i_1_0_403 (.A1(n_1_0_393), .A2(n_1_0_388), .A3(n_1_0_383), + .ZN(n_1_0_382)); + NAND4_X1_LVT i_1_0_402 (.A1(n_1_0_400), .A2(n_1_0_399), .A3(n_1_0_398), + .A4(n_1_0_382), .ZN(RRs2[20])); + AOI22_X1_LVT i_1_0_401 (.A1(registers_17__ap[19]), .A2(n_1_0_629), .B1( + n_1_0_612), .B2(registers_21__ap[19]), .ZN(n_1_0_381)); + AOI222_X1_LVT i_1_0_400 (.A1(registers_13__ap[19]), .A2(n_1_0_631), .B1( + n_1_0_622), .B2(registers_30__ap[19]), .C1(registers_19__ap[19]), .C2( + n_1_0_633), .ZN(n_1_0_380)); + AOI22_X1_LVT i_1_0_399 (.A1(registers_1__ap[19]), .A2(n_1_0_644), .B1( + n_1_0_634), .B2(registers_28__ap[19]), .ZN(n_1_0_379)); + AOI22_X1_LVT i_1_0_398 (.A1(registers_24__ap[19]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[19]), .ZN(n_1_0_378)); + AOI22_X1_LVT i_1_0_397 (.A1(registers_15__ap[19]), .A2(n_1_0_627), .B1( + n_1_0_611), .B2(registers_11__ap[19]), .ZN(n_1_0_377)); + AOI22_X1_LVT i_1_0_396 (.A1(registers_4__ap[19]), .A2(n_1_0_638), .B1( + n_1_0_636), .B2(registers_27__ap[19]), .ZN(n_1_0_376)); + AOI22_X1_LVT i_1_0_395 (.A1(registers_31__ap[19]), .A2(n_1_0_637), .B1( + n_1_0_618), .B2(registers_2__ap[19]), .ZN(n_1_0_375)); + NAND4_X1_LVT i_1_0_394 (.A1(n_1_0_378), .A2(n_1_0_377), .A3(n_1_0_376), + .A4(n_1_0_375), .ZN(n_1_0_374)); + AOI22_X1_LVT i_1_0_393 (.A1(registers_18__ap[19]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[19]), .ZN(n_1_0_373)); + AOI22_X1_LVT i_1_0_392 (.A1(registers_5__ap[19]), .A2(n_1_0_635), .B1( + n_1_0_632), .B2(registers_12__ap[19]), .ZN(n_1_0_372)); + AOI22_X1_LVT i_1_0_391 (.A1(registers_25__ap[19]), .A2(n_1_0_620), .B1( + n_1_0_616), .B2(registers_6__ap[19]), .ZN(n_1_0_371)); + AOI22_X1_LVT i_1_0_390 (.A1(registers_22__ap[19]), .A2(n_1_0_642), .B1( + n_1_0_614), .B2(registers_16__ap[19]), .ZN(n_1_0_370)); + NAND4_X1_LVT i_1_0_389 (.A1(n_1_0_373), .A2(n_1_0_372), .A3(n_1_0_371), + .A4(n_1_0_370), .ZN(n_1_0_369)); + AOI22_X1_LVT i_1_0_388 (.A1(registers_29__ap[19]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[19]), .ZN(n_1_0_368)); + AOI22_X1_LVT i_1_0_387 (.A1(registers_7__ap[19]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[19]), .ZN(n_1_0_367)); + AOI22_X1_LVT i_1_0_386 (.A1(registers_8__ap[19]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[19]), .ZN(n_1_0_366)); + AOI22_X1_LVT i_1_0_385 (.A1(registers_10__ap[19]), .A2(n_1_0_624), .B1( + n_1_0_610), .B2(registers_3__ap[19]), .ZN(n_1_0_365)); + NAND4_X1_LVT i_1_0_384 (.A1(n_1_0_368), .A2(n_1_0_367), .A3(n_1_0_366), + .A4(n_1_0_365), .ZN(n_1_0_364)); + NOR3_X1_LVT i_1_0_383 (.A1(n_1_0_374), .A2(n_1_0_369), .A3(n_1_0_364), + .ZN(n_1_0_363)); + NAND4_X1_LVT i_1_0_382 (.A1(n_1_0_381), .A2(n_1_0_380), .A3(n_1_0_379), + .A4(n_1_0_363), .ZN(RRs2[19])); + AOI22_X1_LVT i_1_0_380 (.A1(registers_4__ap[18]), .A2(n_1_0_638), .B1( + n_1_0_634), .B2(registers_28__ap[18]), .ZN(n_1_0_361)); + AOI22_X1_LVT i_1_0_381 (.A1(registers_8__ap[18]), .A2(n_1_0_626), .B1( + n_1_0_614), .B2(registers_16__ap[18]), .ZN(n_1_0_362)); + AOI22_X1_LVT i_1_0_379 (.A1(registers_14__ap[18]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[18]), .ZN(n_1_0_360)); + AOI22_X1_LVT i_1_0_378 (.A1(registers_25__ap[18]), .A2(n_1_0_620), .B1( + n_1_0_611), .B2(registers_11__ap[18]), .ZN(n_1_0_359)); + NAND3_X1_LVT i_1_0_377 (.A1(n_1_0_362), .A2(n_1_0_360), .A3(n_1_0_359), + .ZN(n_1_0_358)); + AOI221_X1_LVT i_1_0_376 (.A(n_1_0_358), .B1(n_1_0_624), .B2( + registers_10__ap[18]), .C1(registers_6__ap[18]), .C2(n_1_0_616), .ZN( + n_1_0_357)); + AOI222_X1_LVT i_1_0_375 (.A1(registers_1__ap[18]), .A2(n_1_0_644), .B1( + n_1_0_640), .B2(registers_26__ap[18]), .C1(n_1_0_622), .C2( + registers_30__ap[18]), .ZN(n_1_0_356)); + NAND2_X1_LVT i_1_0_374 (.A1(n_1_0_357), .A2(n_1_0_356), .ZN(n_1_0_355)); + AOI221_X1_LVT i_1_0_373 (.A(n_1_0_355), .B1(n_1_0_649), .B2( + registers_29__ap[18]), .C1(registers_2__ap[18]), .C2(n_1_0_618), .ZN( + n_1_0_354)); + AOI22_X1_LVT i_1_0_372 (.A1(registers_18__ap[18]), .A2(n_1_0_646), .B1( + n_1_0_633), .B2(registers_19__ap[18]), .ZN(n_1_0_353)); + AOI22_X1_LVT i_1_0_371 (.A1(registers_12__ap[18]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[18]), .ZN(n_1_0_352)); + AOI22_X1_LVT i_1_0_370 (.A1(registers_22__ap[18]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[18]), .ZN(n_1_0_351)); + NAND3_X1_LVT i_1_0_369 (.A1(n_1_0_353), .A2(n_1_0_352), .A3(n_1_0_351), + .ZN(n_1_0_350)); + AOI221_X1_LVT i_1_0_368 (.A(n_1_0_350), .B1(n_1_0_635), .B2( + registers_5__ap[18]), .C1(registers_20__ap[18]), .C2(n_1_0_613), .ZN( + n_1_0_349)); + AOI22_X1_LVT i_1_0_367 (.A1(registers_15__ap[18]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[18]), .ZN(n_1_0_348)); + AOI22_X1_LVT i_1_0_366 (.A1(registers_23__ap[18]), .A2(n_1_0_615), .B1( + n_1_0_610), .B2(registers_3__ap[18]), .ZN(n_1_0_347)); + AOI22_X1_LVT i_1_0_365 (.A1(registers_13__ap[18]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[18]), .ZN(n_1_0_346)); + NAND3_X1_LVT i_1_0_364 (.A1(n_1_0_348), .A2(n_1_0_347), .A3(n_1_0_346), + .ZN(n_1_0_345)); + AOI221_X1_LVT i_1_0_363 (.A(n_1_0_345), .B1(n_1_0_637), .B2( + registers_31__ap[18]), .C1(registers_27__ap[18]), .C2(n_1_0_636), .ZN( + n_1_0_344)); + NAND4_X1_LVT i_1_0_362 (.A1(n_1_0_361), .A2(n_1_0_354), .A3(n_1_0_349), + .A4(n_1_0_344), .ZN(RRs2[18])); + AOI22_X1_LVT i_1_0_358 (.A1(registers_4__ap[17]), .A2(n_1_0_638), .B1( + n_1_0_634), .B2(registers_28__ap[17]), .ZN(n_1_0_340)); + AOI22_X1_LVT i_1_0_361 (.A1(registers_31__ap[17]), .A2(n_1_0_637), .B1( + n_1_0_616), .B2(registers_6__ap[17]), .ZN(n_1_0_343)); + AOI22_X1_LVT i_1_0_357 (.A1(registers_14__ap[17]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[17]), .ZN(n_1_0_339)); + AOI22_X1_LVT i_1_0_360 (.A1(registers_25__ap[17]), .A2(n_1_0_620), .B1( + n_1_0_611), .B2(registers_11__ap[17]), .ZN(n_1_0_342)); + INV_X1_LVT i_1_0_359 (.A(n_1_0_342), .ZN(n_1_0_341)); + AOI221_X1_LVT i_1_0_356 (.A(n_1_0_341), .B1(n_1_0_614), .B2( + registers_16__ap[17]), .C1(registers_10__ap[17]), .C2(n_1_0_624), .ZN( + n_1_0_338)); + AOI222_X1_LVT i_1_0_355 (.A1(registers_1__ap[17]), .A2(n_1_0_644), .B1( + n_1_0_622), .B2(registers_30__ap[17]), .C1(registers_18__ap[17]), .C2( + n_1_0_646), .ZN(n_1_0_337)); + NAND4_X1_LVT i_1_0_354 (.A1(n_1_0_343), .A2(n_1_0_339), .A3(n_1_0_338), + .A4(n_1_0_337), .ZN(n_1_0_336)); + AOI221_X1_LVT i_1_0_353 (.A(n_1_0_336), .B1(n_1_0_649), .B2( + registers_29__ap[17]), .C1(registers_2__ap[17]), .C2(n_1_0_618), .ZN( + n_1_0_335)); + AOI22_X1_LVT i_1_0_352 (.A1(registers_26__ap[17]), .A2(n_1_0_640), .B1( + n_1_0_633), .B2(registers_19__ap[17]), .ZN(n_1_0_334)); + AOI22_X1_LVT i_1_0_351 (.A1(registers_12__ap[17]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[17]), .ZN(n_1_0_333)); + AOI22_X1_LVT i_1_0_350 (.A1(registers_22__ap[17]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[17]), .ZN(n_1_0_332)); + NAND3_X1_LVT i_1_0_349 (.A1(n_1_0_334), .A2(n_1_0_333), .A3(n_1_0_332), + .ZN(n_1_0_331)); + AOI221_X1_LVT i_1_0_348 (.A(n_1_0_331), .B1(n_1_0_635), .B2( + registers_5__ap[17]), .C1(registers_20__ap[17]), .C2(n_1_0_613), .ZN( + n_1_0_330)); + AOI22_X1_LVT i_1_0_347 (.A1(registers_15__ap[17]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[17]), .ZN(n_1_0_329)); + AOI22_X1_LVT i_1_0_346 (.A1(registers_8__ap[17]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[17]), .ZN(n_1_0_328)); + AOI22_X1_LVT i_1_0_345 (.A1(registers_13__ap[17]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[17]), .ZN(n_1_0_327)); + NAND3_X1_LVT i_1_0_344 (.A1(n_1_0_329), .A2(n_1_0_328), .A3(n_1_0_327), + .ZN(n_1_0_326)); + AOI221_X1_LVT i_1_0_343 (.A(n_1_0_326), .B1(n_1_0_636), .B2( + registers_27__ap[17]), .C1(registers_3__ap[17]), .C2(n_1_0_610), .ZN( + n_1_0_325)); + NAND4_X1_LVT i_1_0_342 (.A1(n_1_0_340), .A2(n_1_0_335), .A3(n_1_0_330), + .A4(n_1_0_325), .ZN(RRs2[17])); + AOI22_X1_LVT i_1_0_341 (.A1(registers_4__ap[16]), .A2(n_1_0_638), .B1( + n_1_0_634), .B2(registers_28__ap[16]), .ZN(n_1_0_324)); + AOI222_X1_LVT i_1_0_340 (.A1(registers_1__ap[16]), .A2(n_1_0_644), .B1( + n_1_0_633), .B2(registers_19__ap[16]), .C1(n_1_0_622), .C2( + registers_30__ap[16]), .ZN(n_1_0_323)); + AOI22_X1_LVT i_1_0_339 (.A1(registers_29__ap[16]), .A2(n_1_0_649), .B1( + n_1_0_618), .B2(registers_2__ap[16]), .ZN(n_1_0_322)); + AOI22_X1_LVT i_1_0_338 (.A1(registers_14__ap[16]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[16]), .ZN(n_1_0_321)); + AOI22_X1_LVT i_1_0_337 (.A1(registers_16__ap[16]), .A2(n_1_0_614), .B1( + n_1_0_611), .B2(registers_11__ap[16]), .ZN(n_1_0_320)); + AOI22_X1_LVT i_1_0_336 (.A1(registers_10__ap[16]), .A2(n_1_0_624), .B1( + n_1_0_620), .B2(registers_25__ap[16]), .ZN(n_1_0_319)); + AOI22_X1_LVT i_1_0_335 (.A1(registers_31__ap[16]), .A2(n_1_0_637), .B1( + n_1_0_616), .B2(registers_6__ap[16]), .ZN(n_1_0_318)); + NAND4_X1_LVT i_1_0_334 (.A1(n_1_0_321), .A2(n_1_0_320), .A3(n_1_0_319), + .A4(n_1_0_318), .ZN(n_1_0_317)); + AOI22_X1_LVT i_1_0_333 (.A1(registers_18__ap[16]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[16]), .ZN(n_1_0_316)); + AOI22_X1_LVT i_1_0_332 (.A1(registers_12__ap[16]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[16]), .ZN(n_1_0_315)); + AOI22_X1_LVT i_1_0_331 (.A1(registers_22__ap[16]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[16]), .ZN(n_1_0_314)); + AOI22_X1_LVT i_1_0_330 (.A1(registers_5__ap[16]), .A2(n_1_0_635), .B1( + n_1_0_613), .B2(registers_20__ap[16]), .ZN(n_1_0_313)); + NAND4_X1_LVT i_1_0_329 (.A1(n_1_0_316), .A2(n_1_0_315), .A3(n_1_0_314), + .A4(n_1_0_313), .ZN(n_1_0_312)); + AOI22_X1_LVT i_1_0_328 (.A1(registers_15__ap[16]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[16]), .ZN(n_1_0_311)); + AOI22_X1_LVT i_1_0_327 (.A1(registers_8__ap[16]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[16]), .ZN(n_1_0_310)); + AOI22_X1_LVT i_1_0_326 (.A1(registers_13__ap[16]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[16]), .ZN(n_1_0_309)); + AOI22_X1_LVT i_1_0_325 (.A1(registers_27__ap[16]), .A2(n_1_0_636), .B1( + n_1_0_610), .B2(registers_3__ap[16]), .ZN(n_1_0_308)); + NAND4_X1_LVT i_1_0_324 (.A1(n_1_0_311), .A2(n_1_0_310), .A3(n_1_0_309), + .A4(n_1_0_308), .ZN(n_1_0_307)); + NOR3_X1_LVT i_1_0_323 (.A1(n_1_0_317), .A2(n_1_0_312), .A3(n_1_0_307), + .ZN(n_1_0_306)); + NAND4_X1_LVT i_1_0_322 (.A1(n_1_0_324), .A2(n_1_0_323), .A3(n_1_0_322), + .A4(n_1_0_306), .ZN(RRs2[16])); + AOI22_X1_LVT i_1_0_320 (.A1(registers_5__ap[15]), .A2(n_1_0_635), .B1( + n_1_0_634), .B2(registers_28__ap[15]), .ZN(n_1_0_304)); + AOI22_X1_LVT i_1_0_321 (.A1(registers_8__ap[15]), .A2(n_1_0_626), .B1( + n_1_0_620), .B2(registers_25__ap[15]), .ZN(n_1_0_305)); + AOI22_X1_LVT i_1_0_319 (.A1(registers_14__ap[15]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[15]), .ZN(n_1_0_303)); + AOI22_X1_LVT i_1_0_318 (.A1(registers_16__ap[15]), .A2(n_1_0_614), .B1( + n_1_0_611), .B2(registers_11__ap[15]), .ZN(n_1_0_302)); + NAND3_X1_LVT i_1_0_317 (.A1(n_1_0_305), .A2(n_1_0_303), .A3(n_1_0_302), + .ZN(n_1_0_301)); + AOI221_X1_LVT i_1_0_316 (.A(n_1_0_301), .B1(n_1_0_616), .B2( + registers_6__ap[15]), .C1(registers_10__ap[15]), .C2(n_1_0_624), .ZN( + n_1_0_300)); + AOI222_X1_LVT i_1_0_315 (.A1(registers_1__ap[15]), .A2(n_1_0_644), .B1( + n_1_0_640), .B2(registers_26__ap[15]), .C1(n_1_0_622), .C2( + registers_30__ap[15]), .ZN(n_1_0_299)); + NAND2_X1_LVT i_1_0_314 (.A1(n_1_0_300), .A2(n_1_0_299), .ZN(n_1_0_298)); + AOI221_X1_LVT i_1_0_313 (.A(n_1_0_298), .B1(n_1_0_649), .B2( + registers_29__ap[15]), .C1(registers_2__ap[15]), .C2(n_1_0_618), .ZN( + n_1_0_297)); + AOI22_X1_LVT i_1_0_312 (.A1(registers_12__ap[15]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[15]), .ZN(n_1_0_296)); + AOI22_X1_LVT i_1_0_311 (.A1(registers_22__ap[15]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[15]), .ZN(n_1_0_295)); + AOI22_X1_LVT i_1_0_310 (.A1(registers_4__ap[15]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[15]), .ZN(n_1_0_294)); + NAND3_X1_LVT i_1_0_309 (.A1(n_1_0_296), .A2(n_1_0_295), .A3(n_1_0_294), + .ZN(n_1_0_293)); + AOI221_X1_LVT i_1_0_308 (.A(n_1_0_293), .B1(n_1_0_633), .B2( + registers_19__ap[15]), .C1(registers_18__ap[15]), .C2(n_1_0_646), .ZN( + n_1_0_292)); + AOI22_X1_LVT i_1_0_307 (.A1(registers_15__ap[15]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[15]), .ZN(n_1_0_291)); + AOI22_X1_LVT i_1_0_306 (.A1(registers_23__ap[15]), .A2(n_1_0_615), .B1( + n_1_0_610), .B2(registers_3__ap[15]), .ZN(n_1_0_290)); + AOI22_X1_LVT i_1_0_305 (.A1(registers_13__ap[15]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[15]), .ZN(n_1_0_289)); + NAND3_X1_LVT i_1_0_304 (.A1(n_1_0_291), .A2(n_1_0_290), .A3(n_1_0_289), + .ZN(n_1_0_288)); + AOI221_X1_LVT i_1_0_303 (.A(n_1_0_288), .B1(n_1_0_636), .B2( + registers_27__ap[15]), .C1(registers_31__ap[15]), .C2(n_1_0_637), .ZN( + n_1_0_287)); + NAND4_X1_LVT i_1_0_302 (.A1(n_1_0_304), .A2(n_1_0_297), .A3(n_1_0_292), + .A4(n_1_0_287), .ZN(RRs2[15])); + AOI22_X1_LVT i_1_0_301 (.A1(registers_28__ap[14]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[14]), .ZN(n_1_0_286)); + AOI222_X1_LVT i_1_0_300 (.A1(registers_18__ap[14]), .A2(n_1_0_646), .B1( + n_1_0_620), .B2(registers_25__ap[14]), .C1(n_1_0_618), .C2( + registers_2__ap[14]), .ZN(n_1_0_285)); + AOI22_X1_LVT i_1_0_299 (.A1(registers_24__ap[14]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[14]), .ZN(n_1_0_284)); + AOI22_X1_LVT i_1_0_298 (.A1(registers_15__ap[14]), .A2(n_1_0_627), .B1( + n_1_0_610), .B2(registers_3__ap[14]), .ZN(n_1_0_283)); + AOI22_X1_LVT i_1_0_297 (.A1(registers_4__ap[14]), .A2(n_1_0_638), .B1( + n_1_0_637), .B2(registers_31__ap[14]), .ZN(n_1_0_282)); + AOI22_X1_LVT i_1_0_296 (.A1(registers_29__ap[14]), .A2(n_1_0_649), .B1( + n_1_0_615), .B2(registers_23__ap[14]), .ZN(n_1_0_281)); + NAND4_X1_LVT i_1_0_295 (.A1(n_1_0_284), .A2(n_1_0_283), .A3(n_1_0_282), + .A4(n_1_0_281), .ZN(n_1_0_280)); + AOI221_X1_LVT i_1_0_294 (.A(n_1_0_280), .B1(n_1_0_644), .B2( + registers_1__ap[14]), .C1(registers_13__ap[14]), .C2(n_1_0_631), .ZN( + n_1_0_279)); + AOI22_X1_LVT i_1_0_293 (.A1(registers_17__ap[14]), .A2(n_1_0_629), .B1( + n_1_0_623), .B2(registers_7__ap[14]), .ZN(n_1_0_278)); + AOI22_X1_LVT i_1_0_292 (.A1(registers_5__ap[14]), .A2(n_1_0_635), .B1( + n_1_0_632), .B2(registers_12__ap[14]), .ZN(n_1_0_277)); + AOI22_X1_LVT i_1_0_291 (.A1(registers_10__ap[14]), .A2(n_1_0_624), .B1( + n_1_0_622), .B2(registers_30__ap[14]), .ZN(n_1_0_276)); + AOI22_X1_LVT i_1_0_290 (.A1(registers_26__ap[14]), .A2(n_1_0_640), .B1( + n_1_0_614), .B2(registers_16__ap[14]), .ZN(n_1_0_275)); + NAND4_X1_LVT i_1_0_289 (.A1(n_1_0_278), .A2(n_1_0_277), .A3(n_1_0_276), + .A4(n_1_0_275), .ZN(n_1_0_274)); + AOI22_X1_LVT i_1_0_288 (.A1(registers_9__ap[14]), .A2(n_1_0_617), .B1( + n_1_0_612), .B2(registers_21__ap[14]), .ZN(n_1_0_273)); + AOI22_X1_LVT i_1_0_287 (.A1(registers_14__ap[14]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[14]), .ZN(n_1_0_272)); + AOI22_X1_LVT i_1_0_286 (.A1(registers_22__ap[14]), .A2(n_1_0_642), .B1( + n_1_0_633), .B2(registers_19__ap[14]), .ZN(n_1_0_271)); + AOI22_X1_LVT i_1_0_285 (.A1(registers_27__ap[14]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[14]), .ZN(n_1_0_270)); + NAND4_X1_LVT i_1_0_284 (.A1(n_1_0_273), .A2(n_1_0_272), .A3(n_1_0_271), + .A4(n_1_0_270), .ZN(n_1_0_269)); + NOR2_X1_LVT i_1_0_283 (.A1(n_1_0_274), .A2(n_1_0_269), .ZN(n_1_0_268)); + NAND4_X1_LVT i_1_0_282 (.A1(n_1_0_286), .A2(n_1_0_285), .A3(n_1_0_279), + .A4(n_1_0_268), .ZN(RRs2[14])); + AOI22_X1_LVT i_1_0_281 (.A1(registers_18__ap[13]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[13]), .ZN(n_1_0_267)); + AOI22_X1_LVT i_1_0_280 (.A1(registers_12__ap[13]), .A2(n_1_0_632), .B1( + n_1_0_629), .B2(registers_17__ap[13]), .ZN(n_1_0_266)); + AOI22_X1_LVT i_1_0_279 (.A1(registers_7__ap[13]), .A2(n_1_0_623), .B1( + n_1_0_614), .B2(registers_16__ap[13]), .ZN(n_1_0_265)); + NAND3_X1_LVT i_1_0_277 (.A1(n_1_0_267), .A2(n_1_0_266), .A3(n_1_0_265), + .ZN(n_1_0_263)); + AOI221_X1_LVT i_1_0_276 (.A(n_1_0_263), .B1(n_1_0_642), .B2( + registers_22__ap[13]), .C1(registers_5__ap[13]), .C2(n_1_0_635), .ZN( + n_1_0_262)); + AOI22_X1_LVT i_1_0_278 (.A1(registers_13__ap[13]), .A2(n_1_0_631), .B1( + n_1_0_612), .B2(registers_21__ap[13]), .ZN(n_1_0_264)); + AOI222_X1_LVT i_1_0_275 (.A1(registers_26__ap[13]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[13]), .C1(n_1_0_620), .C2( + registers_25__ap[13]), .ZN(n_1_0_261)); + AOI22_X1_LVT i_1_0_274 (.A1(registers_28__ap[13]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[13]), .ZN(n_1_0_260)); + NAND3_X1_LVT i_1_0_273 (.A1(n_1_0_264), .A2(n_1_0_261), .A3(n_1_0_260), + .ZN(n_1_0_259)); + AOI22_X1_LVT i_1_0_272 (.A1(registers_1__ap[13]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[13]), .ZN(n_1_0_258)); + AOI22_X1_LVT i_1_0_271 (.A1(registers_19__ap[13]), .A2(n_1_0_633), .B1( + n_1_0_618), .B2(registers_2__ap[13]), .ZN(n_1_0_257)); + AOI22_X1_LVT i_1_0_270 (.A1(registers_14__ap[13]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[13]), .ZN(n_1_0_256)); + AOI22_X1_LVT i_1_0_269 (.A1(registers_27__ap[13]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[13]), .ZN(n_1_0_255)); + NAND4_X1_LVT i_1_0_268 (.A1(n_1_0_258), .A2(n_1_0_257), .A3(n_1_0_256), + .A4(n_1_0_255), .ZN(n_1_0_254)); + AOI22_X1_LVT i_1_0_267 (.A1(registers_24__ap[13]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[13]), .ZN(n_1_0_253)); + AOI22_X1_LVT i_1_0_266 (.A1(registers_4__ap[13]), .A2(n_1_0_638), .B1( + n_1_0_637), .B2(registers_31__ap[13]), .ZN(n_1_0_252)); + AOI22_X1_LVT i_1_0_265 (.A1(registers_29__ap[13]), .A2(n_1_0_649), .B1( + n_1_0_615), .B2(registers_23__ap[13]), .ZN(n_1_0_251)); + AOI22_X1_LVT i_1_0_264 (.A1(registers_15__ap[13]), .A2(n_1_0_627), .B1( + n_1_0_610), .B2(registers_3__ap[13]), .ZN(n_1_0_250)); + NAND4_X1_LVT i_1_0_263 (.A1(n_1_0_253), .A2(n_1_0_252), .A3(n_1_0_251), + .A4(n_1_0_250), .ZN(n_1_0_249)); + NOR3_X1_LVT i_1_0_262 (.A1(n_1_0_259), .A2(n_1_0_254), .A3(n_1_0_249), + .ZN(n_1_0_248)); + NAND2_X1_LVT i_1_0_261 (.A1(n_1_0_262), .A2(n_1_0_248), .ZN(RRs2[13])); + AOI22_X1_LVT i_1_0_260 (.A1(registers_18__ap[12]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[12]), .ZN(n_1_0_247)); + AOI22_X1_LVT i_1_0_259 (.A1(registers_12__ap[12]), .A2(n_1_0_632), .B1( + n_1_0_629), .B2(registers_17__ap[12]), .ZN(n_1_0_246)); + AOI22_X1_LVT i_1_0_258 (.A1(registers_5__ap[12]), .A2(n_1_0_635), .B1( + n_1_0_623), .B2(registers_7__ap[12]), .ZN(n_1_0_245)); + NAND3_X1_LVT i_1_0_256 (.A1(n_1_0_247), .A2(n_1_0_246), .A3(n_1_0_245), + .ZN(n_1_0_243)); + AOI221_X1_LVT i_1_0_255 (.A(n_1_0_243), .B1(n_1_0_642), .B2( + registers_22__ap[12]), .C1(registers_16__ap[12]), .C2(n_1_0_614), .ZN( + n_1_0_242)); + AOI22_X1_LVT i_1_0_257 (.A1(registers_13__ap[12]), .A2(n_1_0_631), .B1( + n_1_0_612), .B2(registers_21__ap[12]), .ZN(n_1_0_244)); + AOI222_X1_LVT i_1_0_254 (.A1(registers_26__ap[12]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[12]), .C1(n_1_0_620), .C2( + registers_25__ap[12]), .ZN(n_1_0_241)); + AOI22_X1_LVT i_1_0_253 (.A1(registers_28__ap[12]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[12]), .ZN(n_1_0_240)); + NAND3_X1_LVT i_1_0_252 (.A1(n_1_0_244), .A2(n_1_0_241), .A3(n_1_0_240), + .ZN(n_1_0_239)); + AOI22_X1_LVT i_1_0_251 (.A1(registers_1__ap[12]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[12]), .ZN(n_1_0_238)); + AOI22_X1_LVT i_1_0_250 (.A1(registers_19__ap[12]), .A2(n_1_0_633), .B1( + n_1_0_618), .B2(registers_2__ap[12]), .ZN(n_1_0_237)); + AOI22_X1_LVT i_1_0_249 (.A1(registers_14__ap[12]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[12]), .ZN(n_1_0_236)); + AOI22_X1_LVT i_1_0_248 (.A1(registers_27__ap[12]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[12]), .ZN(n_1_0_235)); + NAND4_X1_LVT i_1_0_247 (.A1(n_1_0_238), .A2(n_1_0_237), .A3(n_1_0_236), + .A4(n_1_0_235), .ZN(n_1_0_234)); + AOI22_X1_LVT i_1_0_246 (.A1(registers_24__ap[12]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[12]), .ZN(n_1_0_233)); + AOI22_X1_LVT i_1_0_245 (.A1(registers_4__ap[12]), .A2(n_1_0_638), .B1( + n_1_0_637), .B2(registers_31__ap[12]), .ZN(n_1_0_232)); + AOI22_X1_LVT i_1_0_244 (.A1(registers_29__ap[12]), .A2(n_1_0_649), .B1( + n_1_0_615), .B2(registers_23__ap[12]), .ZN(n_1_0_231)); + AOI22_X1_LVT i_1_0_243 (.A1(registers_15__ap[12]), .A2(n_1_0_627), .B1( + n_1_0_610), .B2(registers_3__ap[12]), .ZN(n_1_0_230)); + NAND4_X1_LVT i_1_0_242 (.A1(n_1_0_233), .A2(n_1_0_232), .A3(n_1_0_231), + .A4(n_1_0_230), .ZN(n_1_0_229)); + NOR3_X1_LVT i_1_0_241 (.A1(n_1_0_239), .A2(n_1_0_234), .A3(n_1_0_229), + .ZN(n_1_0_228)); + NAND2_X1_LVT i_1_0_240 (.A1(n_1_0_242), .A2(n_1_0_228), .ZN(RRs2[12])); + AOI22_X1_LVT i_1_0_238 (.A1(registers_29__ap[11]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[11]), .ZN(n_1_0_226)); + AOI22_X1_LVT i_1_0_239 (.A1(registers_27__ap[11]), .A2(n_1_0_636), .B1( + n_1_0_627), .B2(registers_15__ap[11]), .ZN(n_1_0_227)); + AOI22_X1_LVT i_1_0_237 (.A1(registers_1__ap[11]), .A2(n_1_0_644), .B1( + n_1_0_616), .B2(registers_6__ap[11]), .ZN(n_1_0_225)); + AOI22_X1_LVT i_1_0_236 (.A1(registers_5__ap[11]), .A2(n_1_0_635), .B1( + n_1_0_615), .B2(registers_23__ap[11]), .ZN(n_1_0_224)); + NAND3_X1_LVT i_1_0_235 (.A1(n_1_0_227), .A2(n_1_0_225), .A3(n_1_0_224), + .ZN(n_1_0_223)); + AOI221_X1_LVT i_1_0_234 (.A(n_1_0_223), .B1(n_1_0_637), .B2( + registers_31__ap[11]), .C1(registers_16__ap[11]), .C2(n_1_0_614), .ZN( + n_1_0_222)); + AOI222_X1_LVT i_1_0_233 (.A1(registers_8__ap[11]), .A2(n_1_0_626), .B1( + n_1_0_624), .B2(registers_10__ap[11]), .C1(n_1_0_622), .C2( + registers_30__ap[11]), .ZN(n_1_0_221)); + NAND3_X1_LVT i_1_0_232 (.A1(n_1_0_226), .A2(n_1_0_222), .A3(n_1_0_221), + .ZN(n_1_0_220)); + AOI221_X1_LVT i_1_0_231 (.A(n_1_0_220), .B1(n_1_0_638), .B2( + registers_4__ap[11]), .C1(registers_28__ap[11]), .C2(n_1_0_634), .ZN( + n_1_0_219)); + AOI22_X1_LVT i_1_0_230 (.A1(registers_18__ap[11]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[11]), .ZN(n_1_0_218)); + AOI22_X1_LVT i_1_0_229 (.A1(registers_12__ap[11]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[11]), .ZN(n_1_0_217)); + AOI22_X1_LVT i_1_0_228 (.A1(registers_22__ap[11]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[11]), .ZN(n_1_0_216)); + NAND3_X1_LVT i_1_0_227 (.A1(n_1_0_218), .A2(n_1_0_217), .A3(n_1_0_216), + .ZN(n_1_0_215)); + AOI221_X1_LVT i_1_0_226 (.A(n_1_0_215), .B1(n_1_0_613), .B2( + registers_20__ap[11]), .C1(registers_17__ap[11]), .C2(n_1_0_629), .ZN( + n_1_0_214)); + AOI22_X1_LVT i_1_0_225 (.A1(registers_13__ap[11]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[11]), .ZN(n_1_0_213)); + AOI22_X1_LVT i_1_0_224 (.A1(registers_7__ap[11]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[11]), .ZN(n_1_0_212)); + AOI22_X1_LVT i_1_0_223 (.A1(registers_19__ap[11]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[11]), .ZN(n_1_0_211)); + NAND3_X1_LVT i_1_0_222 (.A1(n_1_0_213), .A2(n_1_0_212), .A3(n_1_0_211), + .ZN(n_1_0_210)); + AOI221_X1_LVT i_1_0_221 (.A(n_1_0_210), .B1(n_1_0_611), .B2( + registers_11__ap[11]), .C1(registers_2__ap[11]), .C2(n_1_0_618), .ZN( + n_1_0_209)); + NAND3_X1_LVT i_1_0_220 (.A1(n_1_0_219), .A2(n_1_0_214), .A3(n_1_0_209), + .ZN(RRs2[11])); + AOI22_X1_LVT i_1_0_219 (.A1(registers_28__ap[10]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[10]), .ZN(n_1_0_208)); + AOI222_X1_LVT i_1_0_218 (.A1(registers_26__ap[10]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[10]), .C1(registers_25__ap[10]), .C2( + n_1_0_620), .ZN(n_1_0_207)); + AOI22_X1_LVT i_1_0_217 (.A1(registers_13__ap[10]), .A2(n_1_0_631), .B1( + n_1_0_612), .B2(registers_21__ap[10]), .ZN(n_1_0_206)); + AOI22_X1_LVT i_1_0_216 (.A1(registers_24__ap[10]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[10]), .ZN(n_1_0_205)); + AOI22_X1_LVT i_1_0_215 (.A1(registers_15__ap[10]), .A2(n_1_0_627), .B1( + n_1_0_610), .B2(registers_3__ap[10]), .ZN(n_1_0_204)); + AOI22_X1_LVT i_1_0_214 (.A1(registers_31__ap[10]), .A2(n_1_0_637), .B1( + n_1_0_629), .B2(registers_17__ap[10]), .ZN(n_1_0_203)); + AOI22_X1_LVT i_1_0_213 (.A1(registers_29__ap[10]), .A2(n_1_0_649), .B1( + n_1_0_615), .B2(registers_23__ap[10]), .ZN(n_1_0_202)); + NAND4_X1_LVT i_1_0_212 (.A1(n_1_0_205), .A2(n_1_0_204), .A3(n_1_0_203), + .A4(n_1_0_202), .ZN(n_1_0_201)); + AOI22_X1_LVT i_1_0_211 (.A1(registers_18__ap[10]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[10]), .ZN(n_1_0_200)); + AOI22_X1_LVT i_1_0_210 (.A1(registers_4__ap[10]), .A2(n_1_0_638), .B1( + n_1_0_632), .B2(registers_12__ap[10]), .ZN(n_1_0_199)); + AOI22_X1_LVT i_1_0_209 (.A1(registers_7__ap[10]), .A2(n_1_0_623), .B1( + n_1_0_614), .B2(registers_16__ap[10]), .ZN(n_1_0_198)); + AOI22_X1_LVT i_1_0_208 (.A1(registers_22__ap[10]), .A2(n_1_0_642), .B1( + n_1_0_635), .B2(registers_5__ap[10]), .ZN(n_1_0_197)); + NAND4_X1_LVT i_1_0_207 (.A1(n_1_0_200), .A2(n_1_0_199), .A3(n_1_0_198), + .A4(n_1_0_197), .ZN(n_1_0_196)); + AOI22_X1_LVT i_1_0_206 (.A1(registers_1__ap[10]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[10]), .ZN(n_1_0_195)); + AOI22_X1_LVT i_1_0_205 (.A1(registers_14__ap[10]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[10]), .ZN(n_1_0_194)); + AOI22_X1_LVT i_1_0_204 (.A1(registers_19__ap[10]), .A2(n_1_0_633), .B1( + n_1_0_618), .B2(registers_2__ap[10]), .ZN(n_1_0_193)); + AOI22_X1_LVT i_1_0_203 (.A1(registers_27__ap[10]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[10]), .ZN(n_1_0_192)); + NAND4_X1_LVT i_1_0_202 (.A1(n_1_0_195), .A2(n_1_0_194), .A3(n_1_0_193), + .A4(n_1_0_192), .ZN(n_1_0_191)); + NOR3_X1_LVT i_1_0_201 (.A1(n_1_0_201), .A2(n_1_0_196), .A3(n_1_0_191), + .ZN(n_1_0_190)); + NAND4_X1_LVT i_1_0_200 (.A1(n_1_0_208), .A2(n_1_0_207), .A3(n_1_0_206), + .A4(n_1_0_190), .ZN(RRs2[10])); + AOI22_X1_LVT i_1_0_196 (.A1(registers_13__ap[9]), .A2(n_1_0_631), .B1( + n_1_0_612), .B2(registers_21__ap[9]), .ZN(n_1_0_186)); + AOI22_X1_LVT i_1_0_199 (.A1(registers_29__ap[9]), .A2(n_1_0_649), .B1( + n_1_0_636), .B2(registers_27__ap[9]), .ZN(n_1_0_189)); + AOI22_X1_LVT i_1_0_195 (.A1(registers_24__ap[9]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[9]), .ZN(n_1_0_185)); + AOI22_X1_LVT i_1_0_198 (.A1(registers_31__ap[9]), .A2(n_1_0_637), .B1( + n_1_0_627), .B2(registers_15__ap[9]), .ZN(n_1_0_188)); + INV_X1_LVT i_1_0_197 (.A(n_1_0_188), .ZN(n_1_0_187)); + AOI221_X1_LVT i_1_0_194 (.A(n_1_0_187), .B1(n_1_0_615), .B2( + registers_23__ap[9]), .C1(registers_4__ap[9]), .C2(n_1_0_638), .ZN( + n_1_0_184)); + AOI222_X1_LVT i_1_0_193 (.A1(registers_18__ap[9]), .A2(n_1_0_646), .B1( + n_1_0_624), .B2(registers_10__ap[9]), .C1(registers_25__ap[9]), .C2( + n_1_0_620), .ZN(n_1_0_183)); + NAND4_X1_LVT i_1_0_192 (.A1(n_1_0_189), .A2(n_1_0_185), .A3(n_1_0_184), + .A4(n_1_0_183), .ZN(n_1_0_182)); + AOI221_X1_LVT i_1_0_191 (.A(n_1_0_182), .B1(n_1_0_626), .B2( + registers_8__ap[9]), .C1(registers_28__ap[9]), .C2(n_1_0_634), .ZN( + n_1_0_181)); + AOI22_X1_LVT i_1_0_190 (.A1(registers_26__ap[9]), .A2(n_1_0_640), .B1( + n_1_0_622), .B2(registers_30__ap[9]), .ZN(n_1_0_180)); + AOI22_X1_LVT i_1_0_189 (.A1(registers_12__ap[9]), .A2(n_1_0_632), .B1( + n_1_0_629), .B2(registers_17__ap[9]), .ZN(n_1_0_179)); + AOI22_X1_LVT i_1_0_188 (.A1(registers_5__ap[9]), .A2(n_1_0_635), .B1( + n_1_0_623), .B2(registers_7__ap[9]), .ZN(n_1_0_178)); + NAND3_X1_LVT i_1_0_187 (.A1(n_1_0_180), .A2(n_1_0_179), .A3(n_1_0_178), + .ZN(n_1_0_177)); + AOI221_X1_LVT i_1_0_186 (.A(n_1_0_177), .B1(n_1_0_642), .B2( + registers_22__ap[9]), .C1(registers_16__ap[9]), .C2(n_1_0_614), .ZN( + n_1_0_176)); + AOI22_X1_LVT i_1_0_185 (.A1(registers_1__ap[9]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[9]), .ZN(n_1_0_175)); + AOI22_X1_LVT i_1_0_184 (.A1(registers_14__ap[9]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[9]), .ZN(n_1_0_174)); + AOI22_X1_LVT i_1_0_183 (.A1(registers_19__ap[9]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[9]), .ZN(n_1_0_173)); + NAND3_X1_LVT i_1_0_182 (.A1(n_1_0_175), .A2(n_1_0_174), .A3(n_1_0_173), + .ZN(n_1_0_172)); + AOI221_X1_LVT i_1_0_181 (.A(n_1_0_172), .B1(n_1_0_611), .B2( + registers_11__ap[9]), .C1(registers_2__ap[9]), .C2(n_1_0_618), .ZN( + n_1_0_171)); + NAND4_X1_LVT i_1_0_180 (.A1(n_1_0_186), .A2(n_1_0_181), .A3(n_1_0_176), + .A4(n_1_0_171), .ZN(RRs2[9])); + AOI22_X1_LVT i_1_0_179 (.A1(registers_28__ap[8]), .A2(n_1_0_634), .B1( + n_1_0_629), .B2(registers_17__ap[8]), .ZN(n_1_0_170)); + AOI222_X1_LVT i_1_0_178 (.A1(registers_26__ap[8]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[8]), .C1(n_1_0_626), .C2( + registers_8__ap[8]), .ZN(n_1_0_169)); + AOI22_X1_LVT i_1_0_177 (.A1(registers_29__ap[8]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[8]), .ZN(n_1_0_168)); + AOI22_X1_LVT i_1_0_176 (.A1(registers_1__ap[8]), .A2(n_1_0_644), .B1( + n_1_0_616), .B2(registers_6__ap[8]), .ZN(n_1_0_167)); + AOI22_X1_LVT i_1_0_175 (.A1(registers_5__ap[8]), .A2(n_1_0_635), .B1( + n_1_0_610), .B2(registers_3__ap[8]), .ZN(n_1_0_166)); + AOI22_X1_LVT i_1_0_174 (.A1(registers_31__ap[8]), .A2(n_1_0_637), .B1( + n_1_0_614), .B2(registers_16__ap[8]), .ZN(n_1_0_165)); + AOI22_X1_LVT i_1_0_173 (.A1(registers_15__ap[8]), .A2(n_1_0_627), .B1( + n_1_0_615), .B2(registers_23__ap[8]), .ZN(n_1_0_164)); + NAND4_X1_LVT i_1_0_172 (.A1(n_1_0_167), .A2(n_1_0_166), .A3(n_1_0_165), + .A4(n_1_0_164), .ZN(n_1_0_163)); + AOI22_X1_LVT i_1_0_171 (.A1(registers_18__ap[8]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[8]), .ZN(n_1_0_162)); + AOI22_X1_LVT i_1_0_170 (.A1(registers_4__ap[8]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[8]), .ZN(n_1_0_161)); + AOI22_X1_LVT i_1_0_169 (.A1(registers_22__ap[8]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[8]), .ZN(n_1_0_160)); + AOI22_X1_LVT i_1_0_168 (.A1(registers_12__ap[8]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[8]), .ZN(n_1_0_159)); + NAND4_X1_LVT i_1_0_167 (.A1(n_1_0_162), .A2(n_1_0_161), .A3(n_1_0_160), + .A4(n_1_0_159), .ZN(n_1_0_158)); + AOI22_X1_LVT i_1_0_166 (.A1(registers_13__ap[8]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[8]), .ZN(n_1_0_157)); + AOI22_X1_LVT i_1_0_165 (.A1(registers_7__ap[8]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[8]), .ZN(n_1_0_156)); + AOI22_X1_LVT i_1_0_164 (.A1(registers_19__ap[8]), .A2(n_1_0_633), .B1( + n_1_0_618), .B2(registers_2__ap[8]), .ZN(n_1_0_155)); + AOI22_X1_LVT i_1_0_163 (.A1(registers_27__ap[8]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[8]), .ZN(n_1_0_154)); + NAND4_X1_LVT i_1_0_162 (.A1(n_1_0_157), .A2(n_1_0_156), .A3(n_1_0_155), + .A4(n_1_0_154), .ZN(n_1_0_153)); + NOR3_X1_LVT i_1_0_161 (.A1(n_1_0_163), .A2(n_1_0_158), .A3(n_1_0_153), + .ZN(n_1_0_152)); + NAND4_X1_LVT i_1_0_160 (.A1(n_1_0_170), .A2(n_1_0_169), .A3(n_1_0_168), + .A4(n_1_0_152), .ZN(RRs2[8])); + AOI22_X1_LVT i_1_0_159 (.A1(registers_28__ap[7]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[7]), .ZN(n_1_0_151)); + AOI222_X1_LVT i_1_0_158 (.A1(registers_26__ap[7]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[7]), .C1(registers_25__ap[7]), .C2( + n_1_0_620), .ZN(n_1_0_150)); + AOI22_X1_LVT i_1_0_157 (.A1(registers_24__ap[7]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[7]), .ZN(n_1_0_149)); + AOI22_X1_LVT i_1_0_156 (.A1(registers_15__ap[7]), .A2(n_1_0_627), .B1( + n_1_0_610), .B2(registers_3__ap[7]), .ZN(n_1_0_148)); + AOI22_X1_LVT i_1_0_155 (.A1(registers_31__ap[7]), .A2(n_1_0_637), .B1( + n_1_0_629), .B2(registers_17__ap[7]), .ZN(n_1_0_147)); + AOI22_X1_LVT i_1_0_154 (.A1(registers_29__ap[7]), .A2(n_1_0_649), .B1( + n_1_0_615), .B2(registers_23__ap[7]), .ZN(n_1_0_146)); + NAND4_X1_LVT i_1_0_153 (.A1(n_1_0_149), .A2(n_1_0_148), .A3(n_1_0_147), + .A4(n_1_0_146), .ZN(n_1_0_145)); + AOI221_X1_LVT i_1_0_152 (.A(n_1_0_145), .B1(n_1_0_612), .B2( + registers_21__ap[7]), .C1(registers_13__ap[7]), .C2(n_1_0_631), .ZN( + n_1_0_144)); + AOI22_X1_LVT i_1_0_151 (.A1(registers_18__ap[7]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[7]), .ZN(n_1_0_143)); + AOI22_X1_LVT i_1_0_150 (.A1(registers_4__ap[7]), .A2(n_1_0_638), .B1( + n_1_0_632), .B2(registers_12__ap[7]), .ZN(n_1_0_142)); + AOI22_X1_LVT i_1_0_149 (.A1(registers_5__ap[7]), .A2(n_1_0_635), .B1( + n_1_0_623), .B2(registers_7__ap[7]), .ZN(n_1_0_141)); + AOI22_X1_LVT i_1_0_148 (.A1(registers_22__ap[7]), .A2(n_1_0_642), .B1( + n_1_0_614), .B2(registers_16__ap[7]), .ZN(n_1_0_140)); + NAND4_X1_LVT i_1_0_147 (.A1(n_1_0_143), .A2(n_1_0_142), .A3(n_1_0_141), + .A4(n_1_0_140), .ZN(n_1_0_139)); + AOI22_X1_LVT i_1_0_146 (.A1(registers_1__ap[7]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[7]), .ZN(n_1_0_138)); + AOI22_X1_LVT i_1_0_145 (.A1(registers_14__ap[7]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[7]), .ZN(n_1_0_137)); + AOI22_X1_LVT i_1_0_144 (.A1(registers_19__ap[7]), .A2(n_1_0_633), .B1( + n_1_0_618), .B2(registers_2__ap[7]), .ZN(n_1_0_136)); + AOI22_X1_LVT i_1_0_143 (.A1(registers_27__ap[7]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[7]), .ZN(n_1_0_135)); + NAND4_X1_LVT i_1_0_142 (.A1(n_1_0_138), .A2(n_1_0_137), .A3(n_1_0_136), + .A4(n_1_0_135), .ZN(n_1_0_134)); + NOR2_X1_LVT i_1_0_141 (.A1(n_1_0_139), .A2(n_1_0_134), .ZN(n_1_0_133)); + NAND4_X1_LVT i_1_0_140 (.A1(n_1_0_151), .A2(n_1_0_150), .A3(n_1_0_144), + .A4(n_1_0_133), .ZN(RRs2[7])); + AOI22_X1_LVT i_1_0_136 (.A1(registers_13__ap[6]), .A2(n_1_0_631), .B1( + n_1_0_612), .B2(registers_21__ap[6]), .ZN(n_1_0_129)); + AOI22_X1_LVT i_1_0_139 (.A1(registers_29__ap[6]), .A2(n_1_0_649), .B1( + n_1_0_636), .B2(registers_27__ap[6]), .ZN(n_1_0_132)); + AOI22_X1_LVT i_1_0_135 (.A1(registers_24__ap[6]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[6]), .ZN(n_1_0_128)); + AOI22_X1_LVT i_1_0_138 (.A1(registers_31__ap[6]), .A2(n_1_0_637), .B1( + n_1_0_627), .B2(registers_15__ap[6]), .ZN(n_1_0_131)); + INV_X1_LVT i_1_0_137 (.A(n_1_0_131), .ZN(n_1_0_130)); + AOI221_X1_LVT i_1_0_134 (.A(n_1_0_130), .B1(n_1_0_638), .B2( + registers_4__ap[6]), .C1(registers_23__ap[6]), .C2(n_1_0_615), .ZN( + n_1_0_127)); + AOI222_X1_LVT i_1_0_133 (.A1(registers_18__ap[6]), .A2(n_1_0_646), .B1( + n_1_0_620), .B2(registers_25__ap[6]), .C1(n_1_0_624), .C2( + registers_10__ap[6]), .ZN(n_1_0_126)); + NAND4_X1_LVT i_1_0_132 (.A1(n_1_0_132), .A2(n_1_0_128), .A3(n_1_0_127), + .A4(n_1_0_126), .ZN(n_1_0_125)); + AOI221_X1_LVT i_1_0_131 (.A(n_1_0_125), .B1(n_1_0_626), .B2( + registers_8__ap[6]), .C1(registers_28__ap[6]), .C2(n_1_0_634), .ZN( + n_1_0_124)); + AOI22_X1_LVT i_1_0_130 (.A1(registers_26__ap[6]), .A2(n_1_0_640), .B1( + n_1_0_622), .B2(registers_30__ap[6]), .ZN(n_1_0_123)); + AOI22_X1_LVT i_1_0_129 (.A1(registers_12__ap[6]), .A2(n_1_0_632), .B1( + n_1_0_629), .B2(registers_17__ap[6]), .ZN(n_1_0_122)); + AOI22_X1_LVT i_1_0_128 (.A1(registers_7__ap[6]), .A2(n_1_0_623), .B1( + n_1_0_614), .B2(registers_16__ap[6]), .ZN(n_1_0_121)); + NAND3_X1_LVT i_1_0_127 (.A1(n_1_0_123), .A2(n_1_0_122), .A3(n_1_0_121), + .ZN(n_1_0_120)); + AOI221_X1_LVT i_1_0_126 (.A(n_1_0_120), .B1(n_1_0_642), .B2( + registers_22__ap[6]), .C1(registers_5__ap[6]), .C2(n_1_0_635), .ZN( + n_1_0_119)); + AOI22_X1_LVT i_1_0_125 (.A1(registers_1__ap[6]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[6]), .ZN(n_1_0_118)); + AOI22_X1_LVT i_1_0_124 (.A1(registers_14__ap[6]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[6]), .ZN(n_1_0_117)); + AOI22_X1_LVT i_1_0_123 (.A1(registers_19__ap[6]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[6]), .ZN(n_1_0_116)); + NAND3_X1_LVT i_1_0_122 (.A1(n_1_0_118), .A2(n_1_0_117), .A3(n_1_0_116), + .ZN(n_1_0_115)); + AOI221_X1_LVT i_1_0_121 (.A(n_1_0_115), .B1(n_1_0_618), .B2( + registers_2__ap[6]), .C1(registers_11__ap[6]), .C2(n_1_0_611), .ZN( + n_1_0_114)); + NAND4_X1_LVT i_1_0_120 (.A1(n_1_0_129), .A2(n_1_0_124), .A3(n_1_0_119), + .A4(n_1_0_114), .ZN(RRs2[6])); + AOI22_X1_LVT i_1_0_118 (.A1(registers_28__ap[5]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[5]), .ZN(n_1_0_112)); + AOI22_X1_LVT i_1_0_119 (.A1(registers_31__ap[5]), .A2(n_1_0_637), .B1( + n_1_0_627), .B2(registers_15__ap[5]), .ZN(n_1_0_113)); + AOI22_X1_LVT i_1_0_117 (.A1(registers_24__ap[5]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[5]), .ZN(n_1_0_111)); + AOI22_X1_LVT i_1_0_116 (.A1(registers_17__ap[5]), .A2(n_1_0_629), .B1( + n_1_0_615), .B2(registers_23__ap[5]), .ZN(n_1_0_110)); + NAND3_X1_LVT i_1_0_115 (.A1(n_1_0_113), .A2(n_1_0_111), .A3(n_1_0_110), + .ZN(n_1_0_109)); + AOI221_X1_LVT i_1_0_114 (.A(n_1_0_109), .B1(n_1_0_636), .B2( + registers_27__ap[5]), .C1(registers_29__ap[5]), .C2(n_1_0_649), .ZN( + n_1_0_108)); + AOI222_X1_LVT i_1_0_113 (.A1(registers_10__ap[5]), .A2(n_1_0_624), .B1( + n_1_0_620), .B2(registers_25__ap[5]), .C1(registers_18__ap[5]), .C2( + n_1_0_646), .ZN(n_1_0_107)); + NAND3_X1_LVT i_1_0_112 (.A1(n_1_0_112), .A2(n_1_0_108), .A3(n_1_0_107), + .ZN(n_1_0_106)); + AOI221_X1_LVT i_1_0_111 (.A(n_1_0_106), .B1(n_1_0_612), .B2( + registers_21__ap[5]), .C1(registers_13__ap[5]), .C2(n_1_0_631), .ZN( + n_1_0_105)); + AOI22_X1_LVT i_1_0_110 (.A1(registers_26__ap[5]), .A2(n_1_0_640), .B1( + n_1_0_622), .B2(registers_30__ap[5]), .ZN(n_1_0_104)); + AOI22_X1_LVT i_1_0_109 (.A1(registers_4__ap[5]), .A2(n_1_0_638), .B1( + n_1_0_632), .B2(registers_12__ap[5]), .ZN(n_1_0_103)); + AOI22_X1_LVT i_1_0_108 (.A1(registers_5__ap[5]), .A2(n_1_0_635), .B1( + n_1_0_623), .B2(registers_7__ap[5]), .ZN(n_1_0_102)); + NAND3_X1_LVT i_1_0_107 (.A1(n_1_0_104), .A2(n_1_0_103), .A3(n_1_0_102), + .ZN(n_1_0_101)); + AOI221_X1_LVT i_1_0_106 (.A(n_1_0_101), .B1(n_1_0_642), .B2( + registers_22__ap[5]), .C1(registers_16__ap[5]), .C2(n_1_0_614), .ZN( + n_1_0_100)); + AOI22_X1_LVT i_1_0_105 (.A1(registers_1__ap[5]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[5]), .ZN(n_1_0_99)); + AOI22_X1_LVT i_1_0_104 (.A1(registers_14__ap[5]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[5]), .ZN(n_1_0_98)); + AOI22_X1_LVT i_1_0_103 (.A1(registers_19__ap[5]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[5]), .ZN(n_1_0_97)); + NAND3_X1_LVT i_1_0_102 (.A1(n_1_0_99), .A2(n_1_0_98), .A3(n_1_0_97), .ZN( + n_1_0_96)); + AOI221_X1_LVT i_1_0_101 (.A(n_1_0_96), .B1(n_1_0_611), .B2( + registers_11__ap[5]), .C1(registers_2__ap[5]), .C2(n_1_0_618), .ZN( + n_1_0_95)); + NAND3_X1_LVT i_1_0_100 (.A1(n_1_0_105), .A2(n_1_0_100), .A3(n_1_0_95), + .ZN(RRs2[5])); + AOI22_X1_LVT i_1_0_99 (.A1(registers_4__ap[4]), .A2(n_1_0_638), .B1(n_1_0_634), + .B2(registers_28__ap[4]), .ZN(n_1_0_94)); + AOI222_X1_LVT i_1_0_98 (.A1(registers_8__ap[4]), .A2(n_1_0_626), .B1( + n_1_0_624), .B2(registers_10__ap[4]), .C1(n_1_0_622), .C2( + registers_30__ap[4]), .ZN(n_1_0_93)); + AOI22_X1_LVT i_1_0_97 (.A1(registers_29__ap[4]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[4]), .ZN(n_1_0_92)); + AOI22_X1_LVT i_1_0_96 (.A1(registers_1__ap[4]), .A2(n_1_0_644), .B1(n_1_0_616), + .B2(registers_6__ap[4]), .ZN(n_1_0_91)); + AOI22_X1_LVT i_1_0_95 (.A1(registers_27__ap[4]), .A2(n_1_0_636), .B1( + n_1_0_627), .B2(registers_15__ap[4]), .ZN(n_1_0_90)); + AOI22_X1_LVT i_1_0_94 (.A1(registers_23__ap[4]), .A2(n_1_0_615), .B1( + n_1_0_614), .B2(registers_16__ap[4]), .ZN(n_1_0_89)); + AOI22_X1_LVT i_1_0_93 (.A1(registers_31__ap[4]), .A2(n_1_0_637), .B1( + n_1_0_635), .B2(registers_5__ap[4]), .ZN(n_1_0_88)); + NAND4_X1_LVT i_1_0_92 (.A1(n_1_0_91), .A2(n_1_0_90), .A3(n_1_0_89), .A4( + n_1_0_88), .ZN(n_1_0_87)); + AOI22_X1_LVT i_1_0_91 (.A1(registers_18__ap[4]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[4]), .ZN(n_1_0_86)); + AOI22_X1_LVT i_1_0_90 (.A1(registers_12__ap[4]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[4]), .ZN(n_1_0_85)); + AOI22_X1_LVT i_1_0_89 (.A1(registers_22__ap[4]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[4]), .ZN(n_1_0_84)); + AOI22_X1_LVT i_1_0_88 (.A1(registers_17__ap[4]), .A2(n_1_0_629), .B1( + n_1_0_613), .B2(registers_20__ap[4]), .ZN(n_1_0_83)); + NAND4_X1_LVT i_1_0_87 (.A1(n_1_0_86), .A2(n_1_0_85), .A3(n_1_0_84), .A4( + n_1_0_83), .ZN(n_1_0_82)); + AOI22_X1_LVT i_1_0_86 (.A1(registers_13__ap[4]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[4]), .ZN(n_1_0_81)); + AOI22_X1_LVT i_1_0_85 (.A1(registers_7__ap[4]), .A2(n_1_0_623), .B1(n_1_0_619), + .B2(registers_14__ap[4]), .ZN(n_1_0_80)); + AOI22_X1_LVT i_1_0_84 (.A1(registers_19__ap[4]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[4]), .ZN(n_1_0_79)); + AOI22_X1_LVT i_1_0_83 (.A1(registers_2__ap[4]), .A2(n_1_0_618), .B1(n_1_0_611), + .B2(registers_11__ap[4]), .ZN(n_1_0_78)); + NAND4_X1_LVT i_1_0_82 (.A1(n_1_0_81), .A2(n_1_0_80), .A3(n_1_0_79), .A4( + n_1_0_78), .ZN(n_1_0_77)); + NOR3_X1_LVT i_1_0_81 (.A1(n_1_0_87), .A2(n_1_0_82), .A3(n_1_0_77), .ZN( + n_1_0_76)); + NAND4_X1_LVT i_1_0_80 (.A1(n_1_0_94), .A2(n_1_0_93), .A3(n_1_0_92), .A4( + n_1_0_76), .ZN(RRs2[4])); + AOI22_X1_LVT i_1_0_78 (.A1(registers_29__ap[3]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[3]), .ZN(n_1_0_74)); + AOI22_X1_LVT i_1_0_79 (.A1(registers_27__ap[3]), .A2(n_1_0_636), .B1( + n_1_0_627), .B2(registers_15__ap[3]), .ZN(n_1_0_75)); + AOI22_X1_LVT i_1_0_77 (.A1(registers_1__ap[3]), .A2(n_1_0_644), .B1(n_1_0_616), + .B2(registers_6__ap[3]), .ZN(n_1_0_73)); + AOI22_X1_LVT i_1_0_76 (.A1(registers_5__ap[3]), .A2(n_1_0_635), .B1(n_1_0_611), + .B2(registers_11__ap[3]), .ZN(n_1_0_72)); + NAND3_X1_LVT i_1_0_75 (.A1(n_1_0_75), .A2(n_1_0_73), .A3(n_1_0_72), .ZN( + n_1_0_71)); + AOI221_X1_LVT i_1_0_74 (.A(n_1_0_71), .B1(n_1_0_614), .B2(registers_16__ap[3]), + .C1(registers_31__ap[3]), .C2(n_1_0_637), .ZN(n_1_0_70)); + AOI222_X1_LVT i_1_0_73 (.A1(registers_8__ap[3]), .A2(n_1_0_626), .B1( + n_1_0_624), .B2(registers_10__ap[3]), .C1(n_1_0_622), .C2( + registers_30__ap[3]), .ZN(n_1_0_69)); + NAND3_X1_LVT i_1_0_72 (.A1(n_1_0_74), .A2(n_1_0_70), .A3(n_1_0_69), .ZN( + n_1_0_68)); + AOI221_X1_LVT i_1_0_71 (.A(n_1_0_68), .B1(n_1_0_638), .B2(registers_4__ap[3]), + .C1(registers_28__ap[3]), .C2(n_1_0_634), .ZN(n_1_0_67)); + AOI22_X1_LVT i_1_0_70 (.A1(registers_18__ap[3]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[3]), .ZN(n_1_0_66)); + AOI22_X1_LVT i_1_0_69 (.A1(registers_12__ap[3]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[3]), .ZN(n_1_0_65)); + AOI22_X1_LVT i_1_0_68 (.A1(registers_22__ap[3]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[3]), .ZN(n_1_0_64)); + NAND3_X1_LVT i_1_0_67 (.A1(n_1_0_66), .A2(n_1_0_65), .A3(n_1_0_64), .ZN( + n_1_0_63)); + AOI221_X1_LVT i_1_0_66 (.A(n_1_0_63), .B1(n_1_0_613), .B2(registers_20__ap[3]), + .C1(registers_17__ap[3]), .C2(n_1_0_629), .ZN(n_1_0_62)); + AOI22_X1_LVT i_1_0_65 (.A1(registers_13__ap[3]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[3]), .ZN(n_1_0_61)); + AOI22_X1_LVT i_1_0_64 (.A1(registers_7__ap[3]), .A2(n_1_0_623), .B1(n_1_0_619), + .B2(registers_14__ap[3]), .ZN(n_1_0_60)); + AOI22_X1_LVT i_1_0_63 (.A1(registers_19__ap[3]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[3]), .ZN(n_1_0_59)); + NAND3_X1_LVT i_1_0_62 (.A1(n_1_0_61), .A2(n_1_0_60), .A3(n_1_0_59), .ZN( + n_1_0_58)); + AOI221_X1_LVT i_1_0_61 (.A(n_1_0_58), .B1(n_1_0_618), .B2(registers_2__ap[3]), + .C1(registers_23__ap[3]), .C2(n_1_0_615), .ZN(n_1_0_57)); + NAND3_X1_LVT i_1_0_60 (.A1(n_1_0_67), .A2(n_1_0_62), .A3(n_1_0_57), .ZN( + RRs2[3])); + AOI22_X1_LVT i_1_0_58 (.A1(registers_29__ap[2]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[2]), .ZN(n_1_0_55)); + AOI22_X1_LVT i_1_0_59 (.A1(registers_27__ap[2]), .A2(n_1_0_636), .B1( + n_1_0_627), .B2(registers_15__ap[2]), .ZN(n_1_0_56)); + AOI22_X1_LVT i_1_0_57 (.A1(registers_1__ap[2]), .A2(n_1_0_644), .B1(n_1_0_616), + .B2(registers_6__ap[2]), .ZN(n_1_0_54)); + AOI22_X1_LVT i_1_0_56 (.A1(registers_5__ap[2]), .A2(n_1_0_635), .B1(n_1_0_615), + .B2(registers_23__ap[2]), .ZN(n_1_0_53)); + NAND3_X1_LVT i_1_0_55 (.A1(n_1_0_56), .A2(n_1_0_54), .A3(n_1_0_53), .ZN( + n_1_0_52)); + AOI221_X1_LVT i_1_0_54 (.A(n_1_0_52), .B1(n_1_0_637), .B2(registers_31__ap[2]), + .C1(registers_16__ap[2]), .C2(n_1_0_614), .ZN(n_1_0_51)); + AOI222_X1_LVT i_1_0_53 (.A1(registers_8__ap[2]), .A2(n_1_0_626), .B1( + n_1_0_624), .B2(registers_10__ap[2]), .C1(n_1_0_622), .C2( + registers_30__ap[2]), .ZN(n_1_0_50)); + NAND3_X1_LVT i_1_0_52 (.A1(n_1_0_55), .A2(n_1_0_51), .A3(n_1_0_50), .ZN( + n_1_0_49)); + AOI221_X1_LVT i_1_0_51 (.A(n_1_0_49), .B1(n_1_0_638), .B2(registers_4__ap[2]), + .C1(registers_28__ap[2]), .C2(n_1_0_634), .ZN(n_1_0_48)); + AOI22_X1_LVT i_1_0_50 (.A1(registers_18__ap[2]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[2]), .ZN(n_1_0_47)); + AOI22_X1_LVT i_1_0_49 (.A1(registers_12__ap[2]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[2]), .ZN(n_1_0_46)); + AOI22_X1_LVT i_1_0_48 (.A1(registers_22__ap[2]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[2]), .ZN(n_1_0_45)); + NAND3_X1_LVT i_1_0_47 (.A1(n_1_0_47), .A2(n_1_0_46), .A3(n_1_0_45), .ZN( + n_1_0_44)); + AOI221_X1_LVT i_1_0_46 (.A(n_1_0_44), .B1(n_1_0_629), .B2(registers_17__ap[2]), + .C1(registers_20__ap[2]), .C2(n_1_0_613), .ZN(n_1_0_43)); + AOI22_X1_LVT i_1_0_45 (.A1(registers_13__ap[2]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[2]), .ZN(n_1_0_42)); + AOI22_X1_LVT i_1_0_44 (.A1(registers_7__ap[2]), .A2(n_1_0_623), .B1(n_1_0_619), + .B2(registers_14__ap[2]), .ZN(n_1_0_41)); + AOI22_X1_LVT i_1_0_43 (.A1(registers_19__ap[2]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[2]), .ZN(n_1_0_40)); + NAND3_X1_LVT i_1_0_42 (.A1(n_1_0_42), .A2(n_1_0_41), .A3(n_1_0_40), .ZN( + n_1_0_39)); + AOI221_X1_LVT i_1_0_41 (.A(n_1_0_39), .B1(n_1_0_618), .B2(registers_2__ap[2]), + .C1(registers_11__ap[2]), .C2(n_1_0_611), .ZN(n_1_0_38)); + NAND3_X1_LVT i_1_0_40 (.A1(n_1_0_48), .A2(n_1_0_43), .A3(n_1_0_38), .ZN( + RRs2[2])); + AOI22_X1_LVT i_1_0_38 (.A1(registers_29__ap[1]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[1]), .ZN(n_1_0_36)); + AOI22_X1_LVT i_1_0_39 (.A1(registers_16__ap[1]), .A2(n_1_0_614), .B1( + n_1_0_610), .B2(registers_3__ap[1]), .ZN(n_1_0_37)); + AOI22_X1_LVT i_1_0_37 (.A1(registers_1__ap[1]), .A2(n_1_0_644), .B1(n_1_0_616), + .B2(registers_6__ap[1]), .ZN(n_1_0_35)); + AOI22_X1_LVT i_1_0_36 (.A1(registers_31__ap[1]), .A2(n_1_0_637), .B1( + n_1_0_635), .B2(registers_5__ap[1]), .ZN(n_1_0_34)); + NAND3_X1_LVT i_1_0_35 (.A1(n_1_0_37), .A2(n_1_0_35), .A3(n_1_0_34), .ZN( + n_1_0_33)); + AOI221_X1_LVT i_1_0_34 (.A(n_1_0_33), .B1(n_1_0_627), .B2(registers_15__ap[1]), + .C1(registers_23__ap[1]), .C2(n_1_0_615), .ZN(n_1_0_32)); + AOI222_X1_LVT i_1_0_33 (.A1(registers_26__ap[1]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[1]), .C1(n_1_0_626), .C2( + registers_8__ap[1]), .ZN(n_1_0_31)); + NAND3_X1_LVT i_1_0_32 (.A1(n_1_0_36), .A2(n_1_0_32), .A3(n_1_0_31), .ZN( + n_1_0_30)); + AOI221_X1_LVT i_1_0_31 (.A(n_1_0_30), .B1(n_1_0_629), .B2(registers_17__ap[1]), + .C1(registers_28__ap[1]), .C2(n_1_0_634), .ZN(n_1_0_29)); + AOI22_X1_LVT i_1_0_30 (.A1(registers_18__ap[1]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[1]), .ZN(n_1_0_28)); + AOI22_X1_LVT i_1_0_29 (.A1(registers_4__ap[1]), .A2(n_1_0_638), .B1(n_1_0_613), + .B2(registers_20__ap[1]), .ZN(n_1_0_27)); + AOI22_X1_LVT i_1_0_28 (.A1(registers_22__ap[1]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[1]), .ZN(n_1_0_26)); + NAND3_X1_LVT i_1_0_27 (.A1(n_1_0_28), .A2(n_1_0_27), .A3(n_1_0_26), .ZN( + n_1_0_25)); + AOI221_X1_LVT i_1_0_26 (.A(n_1_0_25), .B1(n_1_0_632), .B2(registers_12__ap[1]), + .C1(registers_24__ap[1]), .C2(n_1_0_621), .ZN(n_1_0_24)); + AOI22_X1_LVT i_1_0_25 (.A1(registers_13__ap[1]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[1]), .ZN(n_1_0_23)); + AOI22_X1_LVT i_1_0_24 (.A1(registers_7__ap[1]), .A2(n_1_0_623), .B1(n_1_0_619), + .B2(registers_14__ap[1]), .ZN(n_1_0_22)); + AOI22_X1_LVT i_1_0_23 (.A1(registers_19__ap[1]), .A2(n_1_0_633), .B1( + n_1_0_618), .B2(registers_2__ap[1]), .ZN(n_1_0_21)); + NAND3_X1_LVT i_1_0_22 (.A1(n_1_0_23), .A2(n_1_0_22), .A3(n_1_0_21), .ZN( + n_1_0_20)); + AOI221_X1_LVT i_1_0_21 (.A(n_1_0_20), .B1(n_1_0_611), .B2(registers_11__ap[1]), + .C1(registers_27__ap[1]), .C2(n_1_0_636), .ZN(n_1_0_19)); + NAND3_X1_LVT i_1_0_20 (.A1(n_1_0_29), .A2(n_1_0_24), .A3(n_1_0_19), .ZN( + RRs2[1])); + AOI22_X1_LVT i_1_0_19 (.A1(registers_4__ap[0]), .A2(n_1_0_638), .B1(n_1_0_634), + .B2(registers_28__ap[0]), .ZN(n_1_0_18)); + AOI222_X1_LVT i_1_0_18 (.A1(registers_8__ap[0]), .A2(n_1_0_626), .B1( + n_1_0_624), .B2(registers_10__ap[0]), .C1(n_1_0_622), .C2( + registers_30__ap[0]), .ZN(n_1_0_17)); + AOI22_X1_LVT i_1_0_17 (.A1(registers_29__ap[0]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[0]), .ZN(n_1_0_16)); + AOI22_X1_LVT i_1_0_16 (.A1(registers_1__ap[0]), .A2(n_1_0_644), .B1(n_1_0_616), + .B2(registers_6__ap[0]), .ZN(n_1_0_15)); + AOI22_X1_LVT i_1_0_15 (.A1(registers_27__ap[0]), .A2(n_1_0_636), .B1( + n_1_0_627), .B2(registers_15__ap[0]), .ZN(n_1_0_14)); + AOI22_X1_LVT i_1_0_14 (.A1(registers_23__ap[0]), .A2(n_1_0_615), .B1( + n_1_0_614), .B2(registers_16__ap[0]), .ZN(n_1_0_13)); + AOI22_X1_LVT i_1_0_13 (.A1(registers_31__ap[0]), .A2(n_1_0_637), .B1( + n_1_0_635), .B2(registers_5__ap[0]), .ZN(n_1_0_12)); + NAND4_X1_LVT i_1_0_12 (.A1(n_1_0_15), .A2(n_1_0_14), .A3(n_1_0_13), .A4( + n_1_0_12), .ZN(n_1_0_11)); + AOI22_X1_LVT i_1_0_11 (.A1(registers_18__ap[0]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[0]), .ZN(n_1_0_10)); + AOI22_X1_LVT i_1_0_10 (.A1(registers_12__ap[0]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[0]), .ZN(n_1_0_9)); + AOI22_X1_LVT i_1_0_9 (.A1(registers_22__ap[0]), .A2(n_1_0_642), .B1(n_1_0_612), + .B2(registers_21__ap[0]), .ZN(n_1_0_8)); + AOI22_X1_LVT i_1_0_8 (.A1(registers_17__ap[0]), .A2(n_1_0_629), .B1(n_1_0_613), + .B2(registers_20__ap[0]), .ZN(n_1_0_7)); + NAND4_X1_LVT i_1_0_7 (.A1(n_1_0_10), .A2(n_1_0_9), .A3(n_1_0_8), .A4(n_1_0_7), + .ZN(n_1_0_6)); + AOI22_X1_LVT i_1_0_6 (.A1(registers_13__ap[0]), .A2(n_1_0_631), .B1(n_1_0_620), + .B2(registers_25__ap[0]), .ZN(n_1_0_5)); + AOI22_X1_LVT i_1_0_5 (.A1(registers_7__ap[0]), .A2(n_1_0_623), .B1(n_1_0_619), + .B2(registers_14__ap[0]), .ZN(n_1_0_4)); + AOI22_X1_LVT i_1_0_4 (.A1(registers_19__ap[0]), .A2(n_1_0_633), .B1(n_1_0_610), + .B2(registers_3__ap[0]), .ZN(n_1_0_3)); + AOI22_X1_LVT i_1_0_3 (.A1(registers_2__ap[0]), .A2(n_1_0_618), .B1(n_1_0_611), + .B2(registers_11__ap[0]), .ZN(n_1_0_2)); + NAND4_X1_LVT i_1_0_2 (.A1(n_1_0_5), .A2(n_1_0_4), .A3(n_1_0_3), .A4(n_1_0_2), + .ZN(n_1_0_1)); + NOR3_X1_LVT i_1_0_1 (.A1(n_1_0_11), .A2(n_1_0_6), .A3(n_1_0_1), .ZN(n_1_0_0)); + NAND4_X1_LVT i_1_0_0 (.A1(n_1_0_18), .A2(n_1_0_17), .A3(n_1_0_16), .A4( + n_1_0_0), .ZN(RRs2[0])); +endmodule + +module MemGen_32_11(chip_en, clock, addr, rd_data, rd_en, wr_en, wr_data); + input chip_en; + input clock; + input [10:0]addr; + output [31:0]rd_data; + input rd_en; + input wr_en; + input [31:0]wr_data; + + wire [1:0]mem_sel; + + INV_X1_LVT i_1_3 (.A(addr[10]), .ZN(mem_sel[0])); + MemGen_16_10 genblk1_0_U_hi (.chip_en(mem_sel[0]), .wr_en(wr_en), .addr({ + addr[9], addr[8], addr[7], addr[6], addr[5], addr[4], addr[3], addr[2], + addr[1], addr[0]}), .wr_data({wr_data[31], wr_data[30], wr_data[29], + wr_data[28], wr_data[27], wr_data[26], wr_data[25], wr_data[24], + wr_data[23], wr_data[22], wr_data[21], wr_data[20], wr_data[19], + wr_data[18], wr_data[17], wr_data[16]}), .clock(clock), .rd_en(rd_en), + .rd_data({n_63, n_62, n_61, n_60, n_59, n_58, n_57, n_56, n_55, n_54, n_53, + n_52, n_51, n_50, n_49, n_48})); + MemGen_16_10 genblk1_1_U_hi (.chip_en(addr[10]), .wr_en(wr_en), .addr({ + addr[9], addr[8], addr[7], addr[6], addr[5], addr[4], addr[3], addr[2], + addr[1], addr[0]}), .wr_data({wr_data[31], wr_data[30], wr_data[29], + wr_data[28], wr_data[27], wr_data[26], wr_data[25], wr_data[24], + wr_data[23], wr_data[22], wr_data[21], wr_data[20], wr_data[19], + wr_data[18], wr_data[17], wr_data[16]}), .clock(clock), .rd_en(rd_en), + .rd_data({n_31, n_30, n_29, n_28, n_27, n_26, n_25, n_24, n_23, n_22, n_21, + n_20, n_19, n_18, n_17, n_16})); + MUX2_X1_LVT i_1_1_31 (.A(n_63), .B(n_31), .S(addr[10]), .Z(rd_data[31])); + MUX2_X1_LVT i_1_1_30 (.A(n_62), .B(n_30), .S(addr[10]), .Z(rd_data[30])); + MUX2_X1_LVT i_1_1_29 (.A(n_61), .B(n_29), .S(addr[10]), .Z(rd_data[29])); + MUX2_X1_LVT i_1_1_28 (.A(n_60), .B(n_28), .S(addr[10]), .Z(rd_data[28])); + MUX2_X1_LVT i_1_1_27 (.A(n_59), .B(n_27), .S(addr[10]), .Z(rd_data[27])); + MUX2_X1_LVT i_1_1_26 (.A(n_58), .B(n_26), .S(addr[10]), .Z(rd_data[26])); + MUX2_X1_LVT i_1_1_25 (.A(n_57), .B(n_25), .S(addr[10]), .Z(rd_data[25])); + MUX2_X1_LVT i_1_1_24 (.A(n_56), .B(n_24), .S(addr[10]), .Z(rd_data[24])); + MUX2_X1_LVT i_1_1_23 (.A(n_55), .B(n_23), .S(addr[10]), .Z(rd_data[23])); + MUX2_X1_LVT i_1_1_22 (.A(n_54), .B(n_22), .S(addr[10]), .Z(rd_data[22])); + MUX2_X1_LVT i_1_1_21 (.A(n_53), .B(n_21), .S(addr[10]), .Z(rd_data[21])); + MUX2_X1_LVT i_1_1_20 (.A(n_52), .B(n_20), .S(addr[10]), .Z(rd_data[20])); + MUX2_X1_LVT i_1_1_19 (.A(n_51), .B(n_19), .S(addr[10]), .Z(rd_data[19])); + MUX2_X1_LVT i_1_1_18 (.A(n_50), .B(n_18), .S(addr[10]), .Z(rd_data[18])); + MUX2_X1_LVT i_1_1_17 (.A(n_49), .B(n_17), .S(addr[10]), .Z(rd_data[17])); + MUX2_X1_LVT i_1_1_16 (.A(n_48), .B(n_16), .S(addr[10]), .Z(rd_data[16])); + MemGen_16_10 genblk1_0_U_lo (.chip_en(mem_sel[0]), .wr_en(wr_en), .addr({ + addr[9], addr[8], addr[7], addr[6], addr[5], addr[4], addr[3], addr[2], + addr[1], addr[0]}), .wr_data({wr_data[15], wr_data[14], wr_data[13], + wr_data[12], wr_data[11], wr_data[10], wr_data[9], wr_data[8], wr_data[7], + wr_data[6], wr_data[5], wr_data[4], wr_data[3], wr_data[2], wr_data[1], + wr_data[0]}), .clock(clock), .rd_en(rd_en), .rd_data({n_47, n_46, n_45, + n_44, n_43, n_42, n_41, n_40, n_39, n_38, n_37, n_36, n_35, n_34, n_33, + n_32})); + MemGen_16_10 genblk1_1_U_lo (.chip_en(addr[10]), .wr_en(wr_en), .addr({ + addr[9], addr[8], addr[7], addr[6], addr[5], addr[4], addr[3], addr[2], + addr[1], addr[0]}), .wr_data({wr_data[15], wr_data[14], wr_data[13], + wr_data[12], wr_data[11], wr_data[10], wr_data[9], wr_data[8], wr_data[7], + wr_data[6], wr_data[5], wr_data[4], wr_data[3], wr_data[2], wr_data[1], + wr_data[0]}), .clock(clock), .rd_en(rd_en), .rd_data({n_15, n_14, n_13, + n_12, n_11, n_10, n_9, n_8, n_7, n_6, n_5, n_4, n_3, n_2, n_1, n_0})); + MUX2_X1_LVT i_1_1_15 (.A(n_47), .B(n_15), .S(addr[10]), .Z(rd_data[15])); + MUX2_X1_LVT i_1_1_14 (.A(n_46), .B(n_14), .S(addr[10]), .Z(rd_data[14])); + MUX2_X1_LVT i_1_1_13 (.A(n_45), .B(n_13), .S(addr[10]), .Z(rd_data[13])); + MUX2_X1_LVT i_1_1_12 (.A(n_44), .B(n_12), .S(addr[10]), .Z(rd_data[12])); + MUX2_X1_LVT i_1_1_11 (.A(n_43), .B(n_11), .S(addr[10]), .Z(rd_data[11])); + MUX2_X1_LVT i_1_1_10 (.A(n_42), .B(n_10), .S(addr[10]), .Z(rd_data[10])); + MUX2_X1_LVT i_1_1_9 (.A(n_41), .B(n_9), .S(addr[10]), .Z(rd_data[9])); + MUX2_X1_LVT i_1_1_8 (.A(n_40), .B(n_8), .S(addr[10]), .Z(rd_data[8])); + MUX2_X1_LVT i_1_1_7 (.A(n_39), .B(n_7), .S(addr[10]), .Z(rd_data[7])); + MUX2_X1_LVT i_1_1_6 (.A(n_38), .B(n_6), .S(addr[10]), .Z(rd_data[6])); + MUX2_X1_LVT i_1_1_5 (.A(n_37), .B(n_5), .S(addr[10]), .Z(rd_data[5])); + MUX2_X1_LVT i_1_1_4 (.A(n_36), .B(n_4), .S(addr[10]), .Z(rd_data[4])); + MUX2_X1_LVT i_1_1_3 (.A(n_35), .B(n_3), .S(addr[10]), .Z(rd_data[3])); + MUX2_X1_LVT i_1_1_2 (.A(n_34), .B(n_2), .S(addr[10]), .Z(rd_data[2])); + MUX2_X1_LVT i_1_1_1 (.A(n_33), .B(n_1), .S(addr[10]), .Z(rd_data[1])); + MUX2_X1_LVT i_1_1_0 (.A(n_32), .B(n_0), .S(addr[10]), .Z(rd_data[0])); +endmodule + +module main_mem(clk, reset, DAddr, IAddr, DWData, DRData, IRData, DWE, DWidth); + input clk; + input reset; + input [31:0]DAddr; + input [31:0]IAddr; + input [31:0]DWData; + output [31:0]DRData; + output [31:0]IRData; + input DWE; + input [1:0]DWidth; + + wire [31:0]mem_rdata; + wire [10:0]mem_addr; + wire n_0_0; + wire n_0_0_0; + wire n_0_1; + wire n_0_0_1; + wire n_0_2; + wire n_0_0_2; + wire n_0_3; + wire n_0_0_3; + wire n_0_4; + wire n_0_0_4; + wire n_0_5; + wire n_0_0_5; + wire n_0_6; + wire n_0_0_6; + wire n_0_7; + wire n_0_0_7; + wire n_0_8; + wire n_0_0_8; + wire n_0_9; + wire n_0_0_9; + wire n_0_10; + wire n_0_0_10; + wire n_0_0_11; + wire n_0_11; + wire n_0_0_12; + wire n_0_0_13; + wire n_0_12; + wire n_0_0_14; + wire n_0_0_15; + wire n_0_13; + wire n_0_0_16; + wire n_0_0_17; + wire n_0_14; + wire n_0_0_18; + wire n_0_0_19; + wire n_0_15; + wire n_0_0_20; + wire n_0_0_21; + wire n_0_16; + wire n_0_0_22; + wire n_0_0_23; + wire n_0_17; + wire n_0_0_24; + wire n_0_0_25; + wire n_0_18; + wire n_0_0_26; + wire n_0_0_27; + wire n_0_0_28; + wire n_0_19; + wire n_0_0_29; + wire n_0_20; + wire n_0_0_30; + wire n_0_21; + wire n_0_0_31; + wire n_0_22; + wire n_0_0_32; + wire n_0_23; + wire n_0_0_33; + wire n_0_24; + wire n_0_0_34; + wire n_0_25; + wire n_0_0_35; + wire n_0_26; + wire n_0_0_36; + wire n_0_0_37; + wire n_0_27; + wire n_0_28; + wire n_0_29; + wire n_0_30; + wire n_0_31; + wire n_0_32; + wire n_0_33; + wire n_0_34; + wire n_0_35; + wire n_0_36; + wire n_0_37; + wire n_0_38; + wire n_0_39; + wire n_0_40; + wire n_0_41; + wire n_0_42; + wire n_0_65; + wire n_0_64; + wire n_0_63; + wire n_0_62; + wire n_0_61; + wire n_0_60; + wire n_0_59; + wire n_0_58; + wire n_0_0_38; + wire n_0_0_39; + wire n_0_57; + wire n_0_0_40; + wire n_0_56; + wire n_0_0_41; + wire n_0_55; + wire n_0_0_42; + wire n_0_54; + wire n_0_0_43; + wire n_0_53; + wire n_0_0_44; + wire n_0_52; + wire n_0_0_45; + wire n_0_51; + wire n_0_0_46; + wire n_0_50; + wire n_0_0_47; + wire n_0_0_48; + wire n_0_0_49; + wire n_0_0_50; + wire n_0_0_51; + wire n_0_49; + wire n_0_0_52; + wire n_0_48; + wire n_0_0_53; + wire n_0_47; + wire n_0_0_54; + wire n_0_46; + wire n_0_0_55; + wire n_0_45; + wire n_0_0_56; + wire n_0_44; + wire n_0_0_57; + wire n_0_66; + wire n_0_0_58; + wire n_0_67; + wire n_0_0_59; + wire n_0_0_60; + wire n_0_0_61; + wire n_0_68; + wire n_0_0_62; + wire n_0_0_63; + wire n_0_69; + wire n_0_0_64; + wire n_0_0_65; + wire n_0_70; + wire n_0_0_66; + wire n_0_0_67; + wire n_0_71; + wire n_0_0_68; + wire n_0_0_69; + wire n_0_72; + wire n_0_0_70; + wire n_0_0_71; + wire n_0_73; + wire n_0_0_72; + wire n_0_0_73; + wire n_0_74; + wire n_0_0_74; + wire n_0_0_75; + wire n_0_75; + wire n_0_0_76; + wire n_0_0_77; + wire n_0_0_78; + wire n_0_0_79; + wire n_0_0_80; + wire n_0_0_81; + wire n_0_0_82; + wire n_0_0_83; + wire n_0_0_84; + wire n_0_0_85; + wire n_0_0_86; + wire n_0_0_87; + wire n_0_0_88; + wire n_0_0_89; + wire n_0_0_90; + wire n_0_0_91; + wire n_0_0_92; + wire n_0_43; + wire n_0_0_93; + wire n_0_0_94; + wire n_0_76; + wire n_0_0_95; + wire [31:0]drTmp; + wire [31:0]mem_wdata; + + INV_X1_LVT i_0_0_171 (.A(DWE), .ZN(n_0)); + NOR2_X1_LVT i_0_0_163 (.A1(n_0), .A2(reset), .ZN(n_0_0_88)); + NOR2_X1_LVT i_0_0_22 (.A1(DWE), .A2(reset), .ZN(n_0_0_11)); + AOI22_X1_LVT i_0_0_21 (.A1(DAddr[12]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[12]), .ZN(n_0_0_10)); + INV_X1_LVT i_0_0_20 (.A(n_0_0_10), .ZN(n_0_10)); + INV_X1_LVT i_0_0_172 (.A(clk), .ZN(n_0_76)); + DFF_X1_LVT \mem_addr_reg[10] (.D(n_0_10), .CK(n_0_76), .Q(mem_addr[10]), + .QN()); + AOI22_X1_LVT i_0_0_19 (.A1(DAddr[11]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[11]), .ZN(n_0_0_9)); + INV_X1_LVT i_0_0_18 (.A(n_0_0_9), .ZN(n_0_9)); + DFF_X1_LVT \mem_addr_reg[9] (.D(n_0_9), .CK(n_0_76), .Q(mem_addr[9]), .QN()); + AOI22_X1_LVT i_0_0_17 (.A1(DAddr[10]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[10]), .ZN(n_0_0_8)); + INV_X1_LVT i_0_0_16 (.A(n_0_0_8), .ZN(n_0_8)); + DFF_X1_LVT \mem_addr_reg[8] (.D(n_0_8), .CK(n_0_76), .Q(mem_addr[8]), .QN()); + AOI22_X1_LVT i_0_0_15 (.A1(DAddr[9]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[9]), .ZN(n_0_0_7)); + INV_X1_LVT i_0_0_14 (.A(n_0_0_7), .ZN(n_0_7)); + DFF_X1_LVT \mem_addr_reg[7] (.D(n_0_7), .CK(n_0_76), .Q(mem_addr[7]), .QN()); + AOI22_X1_LVT i_0_0_13 (.A1(DAddr[8]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[8]), .ZN(n_0_0_6)); + INV_X1_LVT i_0_0_12 (.A(n_0_0_6), .ZN(n_0_6)); + DFF_X1_LVT \mem_addr_reg[6] (.D(n_0_6), .CK(n_0_76), .Q(mem_addr[6]), .QN()); + AOI22_X1_LVT i_0_0_11 (.A1(DAddr[7]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[7]), .ZN(n_0_0_5)); + INV_X1_LVT i_0_0_10 (.A(n_0_0_5), .ZN(n_0_5)); + DFF_X1_LVT \mem_addr_reg[5] (.D(n_0_5), .CK(n_0_76), .Q(mem_addr[5]), .QN()); + AOI22_X1_LVT i_0_0_9 (.A1(DAddr[6]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[6]), .ZN(n_0_0_4)); + INV_X1_LVT i_0_0_8 (.A(n_0_0_4), .ZN(n_0_4)); + DFF_X1_LVT \mem_addr_reg[4] (.D(n_0_4), .CK(n_0_76), .Q(mem_addr[4]), .QN()); + AOI22_X1_LVT i_0_0_7 (.A1(DAddr[5]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[5]), .ZN(n_0_0_3)); + INV_X1_LVT i_0_0_6 (.A(n_0_0_3), .ZN(n_0_3)); + DFF_X1_LVT \mem_addr_reg[3] (.D(n_0_3), .CK(n_0_76), .Q(mem_addr[3]), .QN()); + AOI22_X1_LVT i_0_0_5 (.A1(DAddr[4]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[4]), .ZN(n_0_0_2)); + INV_X1_LVT i_0_0_4 (.A(n_0_0_2), .ZN(n_0_2)); + DFF_X1_LVT \mem_addr_reg[2] (.D(n_0_2), .CK(n_0_76), .Q(mem_addr[2]), .QN()); + AOI22_X1_LVT i_0_0_3 (.A1(DAddr[3]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[3]), .ZN(n_0_0_1)); + INV_X1_LVT i_0_0_2 (.A(n_0_0_1), .ZN(n_0_1)); + DFF_X1_LVT \mem_addr_reg[1] (.D(n_0_1), .CK(n_0_76), .Q(mem_addr[1]), .QN()); + AOI22_X1_LVT i_0_0_1 (.A1(DAddr[2]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[2]), .ZN(n_0_0_0)); + INV_X1_LVT i_0_0_0 (.A(n_0_0_0), .ZN(n_0_0)); + DFF_X1_LVT \mem_addr_reg[0] (.D(n_0_0), .CK(n_0_76), .Q(mem_addr[0]), .QN()); + NOR2_X1_LVT i_0_0_162 (.A1(DWidth[1]), .A2(DAddr[1]), .ZN(n_0_0_87)); + NOR2_X1_LVT i_0_0_158 (.A1(DWidth[0]), .A2(DAddr[0]), .ZN(n_0_0_83)); + AND2_X1_LVT i_0_0_157 (.A1(n_0_0_87), .A2(n_0_0_83), .ZN(n_0_0_82)); + AND2_X1_LVT i_0_0_156 (.A1(n_0_0_88), .A2(n_0_0_82), .ZN(n_0_0_81)); + INV_X1_LVT i_0_0_173 (.A(n_0_0_88), .ZN(n_0_0_95)); + INV_X1_LVT i_0_0_169 (.A(DWidth[1]), .ZN(n_0_0_93)); + NOR3_X1_LVT i_0_0_155 (.A1(n_0_0_95), .A2(DWidth[0]), .A3(n_0_0_93), .ZN( + n_0_0_80)); + AOI22_X1_LVT i_0_0_154 (.A1(DWData[7]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[31]), .ZN(n_0_0_79)); + NAND2_X1_LVT i_0_0_168 (.A1(DWidth[0]), .A2(DWidth[1]), .ZN(n_0_43)); + INV_X1_LVT i_0_0_167 (.A(n_0_43), .ZN(n_0_0_92)); + NOR2_X1_LVT i_0_0_160 (.A1(n_0_0_95), .A2(n_0_0_92), .ZN(n_0_0_85)); + NAND2_X1_LVT i_0_0_161 (.A1(n_0_0_93), .A2(DAddr[1]), .ZN(n_0_0_86)); + NOR2_X1_LVT i_0_0_166 (.A1(DWidth[0]), .A2(DWidth[1]), .ZN(n_0_0_91)); + NAND2_X1_LVT i_0_0_164 (.A1(DAddr[0]), .A2(n_0_0_91), .ZN(n_0_0_89)); + NAND3_X1_LVT i_0_0_159 (.A1(n_0_0_85), .A2(n_0_0_86), .A3(n_0_0_89), .ZN( + n_0_0_84)); + INV_X1_LVT i_0_0_170 (.A(DWidth[0]), .ZN(n_0_0_94)); + NOR2_X1_LVT i_0_0_153 (.A1(n_0_0_94), .A2(DAddr[1]), .ZN(n_0_0_78)); + AND3_X1_LVT i_0_0_152 (.A1(n_0_0_88), .A2(n_0_0_78), .A3(n_0_0_93), .ZN( + n_0_0_77)); + AOI22_X1_LVT i_0_0_151 (.A1(n_0_0_84), .A2(mem_wdata[31]), .B1(DWData[15]), + .B2(n_0_0_77), .ZN(n_0_0_76)); + NAND2_X1_LVT i_0_0_150 (.A1(n_0_0_79), .A2(n_0_0_76), .ZN(n_0_75)); + DFF_X1_LVT \mem_wdata_reg[31] (.D(n_0_75), .CK(n_0_76), .Q(mem_wdata[31]), + .QN()); + AOI22_X1_LVT i_0_0_149 (.A1(DWData[6]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[30]), .ZN(n_0_0_75)); + AOI22_X1_LVT i_0_0_148 (.A1(n_0_0_84), .A2(mem_wdata[30]), .B1(DWData[14]), + .B2(n_0_0_77), .ZN(n_0_0_74)); + NAND2_X1_LVT i_0_0_147 (.A1(n_0_0_75), .A2(n_0_0_74), .ZN(n_0_74)); + DFF_X1_LVT \mem_wdata_reg[30] (.D(n_0_74), .CK(n_0_76), .Q(mem_wdata[30]), + .QN()); + AOI22_X1_LVT i_0_0_146 (.A1(DWData[5]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[29]), .ZN(n_0_0_73)); + AOI22_X1_LVT i_0_0_145 (.A1(n_0_0_84), .A2(mem_wdata[29]), .B1(DWData[13]), + .B2(n_0_0_77), .ZN(n_0_0_72)); + NAND2_X1_LVT i_0_0_144 (.A1(n_0_0_73), .A2(n_0_0_72), .ZN(n_0_73)); + DFF_X1_LVT \mem_wdata_reg[29] (.D(n_0_73), .CK(n_0_76), .Q(mem_wdata[29]), + .QN()); + AOI22_X1_LVT i_0_0_143 (.A1(DWData[4]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[28]), .ZN(n_0_0_71)); + AOI22_X1_LVT i_0_0_142 (.A1(n_0_0_84), .A2(mem_wdata[28]), .B1(DWData[12]), + .B2(n_0_0_77), .ZN(n_0_0_70)); + NAND2_X1_LVT i_0_0_141 (.A1(n_0_0_71), .A2(n_0_0_70), .ZN(n_0_72)); + DFF_X1_LVT \mem_wdata_reg[28] (.D(n_0_72), .CK(n_0_76), .Q(mem_wdata[28]), + .QN()); + AOI22_X1_LVT i_0_0_140 (.A1(DWData[3]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[27]), .ZN(n_0_0_69)); + AOI22_X1_LVT i_0_0_139 (.A1(n_0_0_84), .A2(mem_wdata[27]), .B1(DWData[11]), + .B2(n_0_0_77), .ZN(n_0_0_68)); + NAND2_X1_LVT i_0_0_138 (.A1(n_0_0_69), .A2(n_0_0_68), .ZN(n_0_71)); + DFF_X1_LVT \mem_wdata_reg[27] (.D(n_0_71), .CK(n_0_76), .Q(mem_wdata[27]), + .QN()); + AOI22_X1_LVT i_0_0_137 (.A1(DWData[2]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[26]), .ZN(n_0_0_67)); + AOI22_X1_LVT i_0_0_136 (.A1(n_0_0_84), .A2(mem_wdata[26]), .B1(DWData[10]), + .B2(n_0_0_77), .ZN(n_0_0_66)); + NAND2_X1_LVT i_0_0_135 (.A1(n_0_0_67), .A2(n_0_0_66), .ZN(n_0_70)); + DFF_X1_LVT \mem_wdata_reg[26] (.D(n_0_70), .CK(n_0_76), .Q(mem_wdata[26]), + .QN()); + AOI22_X1_LVT i_0_0_134 (.A1(DWData[1]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[25]), .ZN(n_0_0_65)); + AOI22_X1_LVT i_0_0_133 (.A1(n_0_0_84), .A2(mem_wdata[25]), .B1(DWData[9]), + .B2(n_0_0_77), .ZN(n_0_0_64)); + NAND2_X1_LVT i_0_0_132 (.A1(n_0_0_65), .A2(n_0_0_64), .ZN(n_0_69)); + DFF_X1_LVT \mem_wdata_reg[25] (.D(n_0_69), .CK(n_0_76), .Q(mem_wdata[25]), + .QN()); + AOI22_X1_LVT i_0_0_131 (.A1(DWData[0]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[24]), .ZN(n_0_0_63)); + AOI22_X1_LVT i_0_0_130 (.A1(n_0_0_84), .A2(mem_wdata[24]), .B1(DWData[8]), + .B2(n_0_0_77), .ZN(n_0_0_62)); + NAND2_X1_LVT i_0_0_129 (.A1(n_0_0_63), .A2(n_0_0_62), .ZN(n_0_68)); + DFF_X1_LVT \mem_wdata_reg[24] (.D(n_0_68), .CK(n_0_76), .Q(mem_wdata[24]), + .QN()); + NOR4_X1_LVT i_0_0_127 (.A1(n_0_0_95), .A2(n_0_0_83), .A3(DWidth[1]), .A4( + DAddr[1]), .ZN(n_0_0_60)); + INV_X1_LVT i_0_0_165 (.A(n_0_0_91), .ZN(n_0_0_90)); + OAI211_X1_LVT i_0_0_128 (.A(n_0_0_85), .B(n_0_0_86), .C1(n_0_0_90), .C2( + DAddr[0]), .ZN(n_0_0_61)); + AOI222_X1_LVT i_0_0_126 (.A1(DWData[7]), .A2(n_0_0_60), .B1(mem_wdata[23]), + .B2(n_0_0_61), .C1(DWData[23]), .C2(n_0_0_80), .ZN(n_0_0_59)); + INV_X1_LVT i_0_0_125 (.A(n_0_0_59), .ZN(n_0_67)); + DFF_X1_LVT \mem_wdata_reg[23] (.D(n_0_67), .CK(n_0_76), .Q(mem_wdata[23]), + .QN()); + AOI222_X1_LVT i_0_0_124 (.A1(DWData[6]), .A2(n_0_0_60), .B1(mem_wdata[22]), + .B2(n_0_0_61), .C1(DWData[22]), .C2(n_0_0_80), .ZN(n_0_0_58)); + INV_X1_LVT i_0_0_123 (.A(n_0_0_58), .ZN(n_0_66)); + DFF_X1_LVT \mem_wdata_reg[22] (.D(n_0_66), .CK(n_0_76), .Q(mem_wdata[22]), + .QN()); + AOI222_X1_LVT i_0_0_122 (.A1(DWData[5]), .A2(n_0_0_60), .B1(mem_wdata[21]), + .B2(n_0_0_61), .C1(DWData[21]), .C2(n_0_0_80), .ZN(n_0_0_57)); + INV_X1_LVT i_0_0_121 (.A(n_0_0_57), .ZN(n_0_44)); + DFF_X1_LVT \mem_wdata_reg[21] (.D(n_0_44), .CK(n_0_76), .Q(mem_wdata[21]), + .QN()); + AOI222_X1_LVT i_0_0_120 (.A1(DWData[4]), .A2(n_0_0_60), .B1(mem_wdata[20]), + .B2(n_0_0_61), .C1(DWData[20]), .C2(n_0_0_80), .ZN(n_0_0_56)); + INV_X1_LVT i_0_0_119 (.A(n_0_0_56), .ZN(n_0_45)); + DFF_X1_LVT \mem_wdata_reg[20] (.D(n_0_45), .CK(n_0_76), .Q(mem_wdata[20]), + .QN()); + AOI222_X1_LVT i_0_0_118 (.A1(DWData[3]), .A2(n_0_0_60), .B1(mem_wdata[19]), + .B2(n_0_0_61), .C1(DWData[19]), .C2(n_0_0_80), .ZN(n_0_0_55)); + INV_X1_LVT i_0_0_117 (.A(n_0_0_55), .ZN(n_0_46)); + DFF_X1_LVT \mem_wdata_reg[19] (.D(n_0_46), .CK(n_0_76), .Q(mem_wdata[19]), + .QN()); + AOI222_X1_LVT i_0_0_116 (.A1(DWData[2]), .A2(n_0_0_60), .B1(mem_wdata[18]), + .B2(n_0_0_61), .C1(DWData[18]), .C2(n_0_0_80), .ZN(n_0_0_54)); + INV_X1_LVT i_0_0_115 (.A(n_0_0_54), .ZN(n_0_47)); + DFF_X1_LVT \mem_wdata_reg[18] (.D(n_0_47), .CK(n_0_76), .Q(mem_wdata[18]), + .QN()); + AOI222_X1_LVT i_0_0_114 (.A1(DWData[1]), .A2(n_0_0_60), .B1(mem_wdata[17]), + .B2(n_0_0_61), .C1(DWData[17]), .C2(n_0_0_80), .ZN(n_0_0_53)); + INV_X1_LVT i_0_0_113 (.A(n_0_0_53), .ZN(n_0_48)); + DFF_X1_LVT \mem_wdata_reg[17] (.D(n_0_48), .CK(n_0_76), .Q(mem_wdata[17]), + .QN()); + AOI222_X1_LVT i_0_0_112 (.A1(DWData[0]), .A2(n_0_0_60), .B1(mem_wdata[16]), + .B2(n_0_0_61), .C1(DWData[16]), .C2(n_0_0_80), .ZN(n_0_0_52)); + INV_X1_LVT i_0_0_111 (.A(n_0_0_52), .ZN(n_0_49)); + DFF_X1_LVT \mem_wdata_reg[16] (.D(n_0_49), .CK(n_0_76), .Q(mem_wdata[16]), + .QN()); + NOR4_X1_LVT i_0_0_110 (.A1(n_0_0_95), .A2(n_0_0_87), .A3(n_0_0_92), .A4( + n_0_0_91), .ZN(n_0_0_51)); + NOR3_X1_LVT i_0_0_109 (.A1(n_0_0_86), .A2(DAddr[0]), .A3(DWidth[0]), .ZN( + n_0_0_50)); + AND2_X1_LVT i_0_0_108 (.A1(n_0_0_88), .A2(n_0_0_50), .ZN(n_0_0_49)); + OAI211_X1_LVT i_0_0_107 (.A(n_0_0_85), .B(n_0_0_89), .C1(DAddr[1]), .C2( + DWidth[1]), .ZN(n_0_0_48)); + AOI222_X1_LVT i_0_0_106 (.A1(DWData[15]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[7]), .C1(n_0_0_48), .C2(mem_wdata[15]), .ZN(n_0_0_47)); + INV_X1_LVT i_0_0_105 (.A(n_0_0_47), .ZN(n_0_50)); + DFF_X1_LVT \mem_wdata_reg[15] (.D(n_0_50), .CK(n_0_76), .Q(mem_wdata[15]), + .QN()); + AOI222_X1_LVT i_0_0_104 (.A1(DWData[14]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[6]), .C1(n_0_0_48), .C2(mem_wdata[14]), .ZN(n_0_0_46)); + INV_X1_LVT i_0_0_103 (.A(n_0_0_46), .ZN(n_0_51)); + DFF_X1_LVT \mem_wdata_reg[14] (.D(n_0_51), .CK(n_0_76), .Q(mem_wdata[14]), + .QN()); + AOI222_X1_LVT i_0_0_102 (.A1(DWData[13]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[5]), .C1(n_0_0_48), .C2(mem_wdata[13]), .ZN(n_0_0_45)); + INV_X1_LVT i_0_0_101 (.A(n_0_0_45), .ZN(n_0_52)); + DFF_X1_LVT \mem_wdata_reg[13] (.D(n_0_52), .CK(n_0_76), .Q(mem_wdata[13]), + .QN()); + AOI222_X1_LVT i_0_0_100 (.A1(DWData[12]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[4]), .C1(n_0_0_48), .C2(mem_wdata[12]), .ZN(n_0_0_44)); + INV_X1_LVT i_0_0_99 (.A(n_0_0_44), .ZN(n_0_53)); + DFF_X1_LVT \mem_wdata_reg[12] (.D(n_0_53), .CK(n_0_76), .Q(mem_wdata[12]), + .QN()); + AOI222_X1_LVT i_0_0_98 (.A1(DWData[11]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[3]), .C1(n_0_0_48), .C2(mem_wdata[11]), .ZN(n_0_0_43)); + INV_X1_LVT i_0_0_97 (.A(n_0_0_43), .ZN(n_0_54)); + DFF_X1_LVT \mem_wdata_reg[11] (.D(n_0_54), .CK(n_0_76), .Q(mem_wdata[11]), + .QN()); + AOI222_X1_LVT i_0_0_96 (.A1(DWData[10]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[2]), .C1(n_0_0_48), .C2(mem_wdata[10]), .ZN(n_0_0_42)); + INV_X1_LVT i_0_0_95 (.A(n_0_0_42), .ZN(n_0_55)); + DFF_X1_LVT \mem_wdata_reg[10] (.D(n_0_55), .CK(n_0_76), .Q(mem_wdata[10]), + .QN()); + AOI222_X1_LVT i_0_0_94 (.A1(DWData[9]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[1]), .C1(n_0_0_48), .C2(mem_wdata[9]), .ZN(n_0_0_41)); + INV_X1_LVT i_0_0_93 (.A(n_0_0_41), .ZN(n_0_56)); + DFF_X1_LVT \mem_wdata_reg[9] (.D(n_0_56), .CK(n_0_76), .Q(mem_wdata[9]), + .QN()); + AOI222_X1_LVT i_0_0_92 (.A1(DWData[8]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[0]), .C1(n_0_0_48), .C2(mem_wdata[8]), .ZN(n_0_0_40)); + INV_X1_LVT i_0_0_91 (.A(n_0_0_40), .ZN(n_0_57)); + DFF_X1_LVT \mem_wdata_reg[8] (.D(n_0_57), .CK(n_0_76), .Q(mem_wdata[8]), + .QN()); + AOI21_X1_LVT i_0_0_90 (.A(n_0_0_87), .B1(n_0_0_83), .B2(n_0_0_93), .ZN( + n_0_0_39)); + NAND2_X1_LVT i_0_0_89 (.A1(n_0_0_85), .A2(n_0_0_39), .ZN(n_0_0_38)); + MUX2_X1_LVT i_0_0_88 (.A(DWData[7]), .B(mem_wdata[7]), .S(n_0_0_38), .Z( + n_0_58)); + DFF_X1_LVT \mem_wdata_reg[7] (.D(n_0_58), .CK(n_0_76), .Q(mem_wdata[7]), + .QN()); + MUX2_X1_LVT i_0_0_87 (.A(DWData[6]), .B(mem_wdata[6]), .S(n_0_0_38), .Z( + n_0_59)); + DFF_X1_LVT \mem_wdata_reg[6] (.D(n_0_59), .CK(n_0_76), .Q(mem_wdata[6]), + .QN()); + MUX2_X1_LVT i_0_0_86 (.A(DWData[5]), .B(mem_wdata[5]), .S(n_0_0_38), .Z( + n_0_60)); + DFF_X1_LVT \mem_wdata_reg[5] (.D(n_0_60), .CK(n_0_76), .Q(mem_wdata[5]), + .QN()); + MUX2_X1_LVT i_0_0_85 (.A(DWData[4]), .B(mem_wdata[4]), .S(n_0_0_38), .Z( + n_0_61)); + DFF_X1_LVT \mem_wdata_reg[4] (.D(n_0_61), .CK(n_0_76), .Q(mem_wdata[4]), + .QN()); + MUX2_X1_LVT i_0_0_84 (.A(DWData[3]), .B(mem_wdata[3]), .S(n_0_0_38), .Z( + n_0_62)); + DFF_X1_LVT \mem_wdata_reg[3] (.D(n_0_62), .CK(n_0_76), .Q(mem_wdata[3]), + .QN()); + MUX2_X1_LVT i_0_0_83 (.A(DWData[2]), .B(mem_wdata[2]), .S(n_0_0_38), .Z( + n_0_63)); + DFF_X1_LVT \mem_wdata_reg[2] (.D(n_0_63), .CK(n_0_76), .Q(mem_wdata[2]), + .QN()); + MUX2_X1_LVT i_0_0_82 (.A(DWData[1]), .B(mem_wdata[1]), .S(n_0_0_38), .Z( + n_0_64)); + DFF_X1_LVT \mem_wdata_reg[1] (.D(n_0_64), .CK(n_0_76), .Q(mem_wdata[1]), + .QN()); + MUX2_X1_LVT i_0_0_81 (.A(DWData[0]), .B(mem_wdata[0]), .S(n_0_0_38), .Z( + n_0_65)); + DFF_X1_LVT \mem_wdata_reg[0] (.D(n_0_65), .CK(n_0_76), .Q(mem_wdata[0]), + .QN()); + MemGen_32_11 RAM (.chip_en(), .clock(clk), .addr(mem_addr), .rd_data( + mem_rdata), .rd_en(n_0), .wr_en(DWE), .wr_data(mem_wdata)); + DFF_X1_LVT \drTmp_reg[31] (.D(mem_rdata[31]), .CK(n_0_76), .Q(drTmp[31]), + .QN()); + AND2_X1_LVT i_0_0_80 (.A1(DWidth[1]), .A2(drTmp[31]), .ZN(n_0_42)); + DLH_X1_LVT \DRData[31] (.D(n_0_42), .G(n_0_43), .Q(DRData[31])); + DFF_X1_LVT \drTmp_reg[30] (.D(mem_rdata[30]), .CK(n_0_76), .Q(drTmp[30]), + .QN()); + AND2_X1_LVT i_0_0_79 (.A1(DWidth[1]), .A2(drTmp[30]), .ZN(n_0_41)); + DLH_X1_LVT \DRData[30] (.D(n_0_41), .G(n_0_43), .Q(DRData[30])); + DFF_X1_LVT \drTmp_reg[29] (.D(mem_rdata[29]), .CK(n_0_76), .Q(drTmp[29]), + .QN()); + AND2_X1_LVT i_0_0_78 (.A1(DWidth[1]), .A2(drTmp[29]), .ZN(n_0_40)); + DLH_X1_LVT \DRData[29] (.D(n_0_40), .G(n_0_43), .Q(DRData[29])); + DFF_X1_LVT \drTmp_reg[28] (.D(mem_rdata[28]), .CK(n_0_76), .Q(drTmp[28]), + .QN()); + AND2_X1_LVT i_0_0_77 (.A1(DWidth[1]), .A2(drTmp[28]), .ZN(n_0_39)); + DLH_X1_LVT \DRData[28] (.D(n_0_39), .G(n_0_43), .Q(DRData[28])); + DFF_X1_LVT \drTmp_reg[27] (.D(mem_rdata[27]), .CK(n_0_76), .Q(drTmp[27]), + .QN()); + AND2_X1_LVT i_0_0_76 (.A1(DWidth[1]), .A2(drTmp[27]), .ZN(n_0_38)); + DLH_X1_LVT \DRData[27] (.D(n_0_38), .G(n_0_43), .Q(DRData[27])); + DFF_X1_LVT \drTmp_reg[26] (.D(mem_rdata[26]), .CK(n_0_76), .Q(drTmp[26]), + .QN()); + AND2_X1_LVT i_0_0_75 (.A1(DWidth[1]), .A2(drTmp[26]), .ZN(n_0_37)); + DLH_X1_LVT \DRData[26] (.D(n_0_37), .G(n_0_43), .Q(DRData[26])); + DFF_X1_LVT \drTmp_reg[25] (.D(mem_rdata[25]), .CK(n_0_76), .Q(drTmp[25]), + .QN()); + AND2_X1_LVT i_0_0_74 (.A1(DWidth[1]), .A2(drTmp[25]), .ZN(n_0_36)); + DLH_X1_LVT \DRData[25] (.D(n_0_36), .G(n_0_43), .Q(DRData[25])); + DFF_X1_LVT \drTmp_reg[24] (.D(mem_rdata[24]), .CK(n_0_76), .Q(drTmp[24]), + .QN()); + AND2_X1_LVT i_0_0_73 (.A1(DWidth[1]), .A2(drTmp[24]), .ZN(n_0_35)); + DLH_X1_LVT \DRData[24] (.D(n_0_35), .G(n_0_43), .Q(DRData[24])); + DFF_X1_LVT \drTmp_reg[23] (.D(mem_rdata[23]), .CK(n_0_76), .Q(drTmp[23]), + .QN()); + AND2_X1_LVT i_0_0_72 (.A1(DWidth[1]), .A2(drTmp[23]), .ZN(n_0_34)); + DLH_X1_LVT \DRData[23] (.D(n_0_34), .G(n_0_43), .Q(DRData[23])); + DFF_X1_LVT \drTmp_reg[22] (.D(mem_rdata[22]), .CK(n_0_76), .Q(drTmp[22]), + .QN()); + AND2_X1_LVT i_0_0_71 (.A1(DWidth[1]), .A2(drTmp[22]), .ZN(n_0_33)); + DLH_X1_LVT \DRData[22] (.D(n_0_33), .G(n_0_43), .Q(DRData[22])); + DFF_X1_LVT \drTmp_reg[21] (.D(mem_rdata[21]), .CK(n_0_76), .Q(drTmp[21]), + .QN()); + AND2_X1_LVT i_0_0_70 (.A1(DWidth[1]), .A2(drTmp[21]), .ZN(n_0_32)); + DLH_X1_LVT \DRData[21] (.D(n_0_32), .G(n_0_43), .Q(DRData[21])); + DFF_X1_LVT \drTmp_reg[20] (.D(mem_rdata[20]), .CK(n_0_76), .Q(drTmp[20]), + .QN()); + AND2_X1_LVT i_0_0_69 (.A1(DWidth[1]), .A2(drTmp[20]), .ZN(n_0_31)); + DLH_X1_LVT \DRData[20] (.D(n_0_31), .G(n_0_43), .Q(DRData[20])); + DFF_X1_LVT \drTmp_reg[19] (.D(mem_rdata[19]), .CK(n_0_76), .Q(drTmp[19]), + .QN()); + AND2_X1_LVT i_0_0_68 (.A1(DWidth[1]), .A2(drTmp[19]), .ZN(n_0_30)); + DLH_X1_LVT \DRData[19] (.D(n_0_30), .G(n_0_43), .Q(DRData[19])); + DFF_X1_LVT \drTmp_reg[18] (.D(mem_rdata[18]), .CK(n_0_76), .Q(drTmp[18]), + .QN()); + AND2_X1_LVT i_0_0_67 (.A1(DWidth[1]), .A2(drTmp[18]), .ZN(n_0_29)); + DLH_X1_LVT \DRData[18] (.D(n_0_29), .G(n_0_43), .Q(DRData[18])); + DFF_X1_LVT \drTmp_reg[17] (.D(mem_rdata[17]), .CK(n_0_76), .Q(drTmp[17]), + .QN()); + AND2_X1_LVT i_0_0_66 (.A1(DWidth[1]), .A2(drTmp[17]), .ZN(n_0_28)); + DLH_X1_LVT \DRData[17] (.D(n_0_28), .G(n_0_43), .Q(DRData[17])); + DFF_X1_LVT \drTmp_reg[16] (.D(mem_rdata[16]), .CK(n_0_76), .Q(drTmp[16]), + .QN()); + AND2_X1_LVT i_0_0_65 (.A1(DWidth[1]), .A2(drTmp[16]), .ZN(n_0_27)); + DLH_X1_LVT \DRData[16] (.D(n_0_27), .G(n_0_43), .Q(DRData[16])); + NOR2_X1_LVT i_0_0_64 (.A1(n_0_0_91), .A2(n_0_0_87), .ZN(n_0_0_37)); + DFF_X1_LVT \drTmp_reg[15] (.D(mem_rdata[15]), .CK(n_0_76), .Q(drTmp[15]), + .QN()); + AOI22_X1_LVT i_0_0_63 (.A1(drTmp[31]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[15]), .ZN(n_0_0_36)); + INV_X1_LVT i_0_0_62 (.A(n_0_0_36), .ZN(n_0_26)); + DLH_X1_LVT \DRData[15] (.D(n_0_26), .G(n_0_43), .Q(DRData[15])); + DFF_X1_LVT \drTmp_reg[14] (.D(mem_rdata[14]), .CK(n_0_76), .Q(drTmp[14]), + .QN()); + AOI22_X1_LVT i_0_0_61 (.A1(drTmp[30]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[14]), .ZN(n_0_0_35)); + INV_X1_LVT i_0_0_60 (.A(n_0_0_35), .ZN(n_0_25)); + DLH_X1_LVT \DRData[14] (.D(n_0_25), .G(n_0_43), .Q(DRData[14])); + DFF_X1_LVT \drTmp_reg[13] (.D(mem_rdata[13]), .CK(n_0_76), .Q(drTmp[13]), + .QN()); + AOI22_X1_LVT i_0_0_59 (.A1(drTmp[29]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[13]), .ZN(n_0_0_34)); + INV_X1_LVT i_0_0_58 (.A(n_0_0_34), .ZN(n_0_24)); + DLH_X1_LVT \DRData[13] (.D(n_0_24), .G(n_0_43), .Q(DRData[13])); + DFF_X1_LVT \drTmp_reg[12] (.D(mem_rdata[12]), .CK(n_0_76), .Q(drTmp[12]), + .QN()); + AOI22_X1_LVT i_0_0_57 (.A1(drTmp[28]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[12]), .ZN(n_0_0_33)); + INV_X1_LVT i_0_0_56 (.A(n_0_0_33), .ZN(n_0_23)); + DLH_X1_LVT \DRData[12] (.D(n_0_23), .G(n_0_43), .Q(DRData[12])); + DFF_X1_LVT \drTmp_reg[11] (.D(mem_rdata[11]), .CK(n_0_76), .Q(drTmp[11]), + .QN()); + AOI22_X1_LVT i_0_0_55 (.A1(drTmp[27]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[11]), .ZN(n_0_0_32)); + INV_X1_LVT i_0_0_54 (.A(n_0_0_32), .ZN(n_0_22)); + DLH_X1_LVT \DRData[11] (.D(n_0_22), .G(n_0_43), .Q(DRData[11])); + DFF_X1_LVT \drTmp_reg[10] (.D(mem_rdata[10]), .CK(n_0_76), .Q(drTmp[10]), + .QN()); + AOI22_X1_LVT i_0_0_53 (.A1(drTmp[26]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[10]), .ZN(n_0_0_31)); + INV_X1_LVT i_0_0_52 (.A(n_0_0_31), .ZN(n_0_21)); + DLH_X1_LVT \DRData[10] (.D(n_0_21), .G(n_0_43), .Q(DRData[10])); + DFF_X1_LVT \drTmp_reg[9] (.D(mem_rdata[9]), .CK(n_0_76), .Q(drTmp[9]), .QN()); + AOI22_X1_LVT i_0_0_51 (.A1(drTmp[25]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[9]), .ZN(n_0_0_30)); + INV_X1_LVT i_0_0_50 (.A(n_0_0_30), .ZN(n_0_20)); + DLH_X1_LVT \DRData[9] (.D(n_0_20), .G(n_0_43), .Q(DRData[9])); + DFF_X1_LVT \drTmp_reg[8] (.D(mem_rdata[8]), .CK(n_0_76), .Q(drTmp[8]), .QN()); + AOI22_X1_LVT i_0_0_49 (.A1(drTmp[24]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[8]), .ZN(n_0_0_29)); + INV_X1_LVT i_0_0_48 (.A(n_0_0_29), .ZN(n_0_19)); + DLH_X1_LVT \DRData[8] (.D(n_0_19), .G(n_0_43), .Q(DRData[8])); + AOI22_X1_LVT i_0_0_46 (.A1(drTmp[31]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[15]), .ZN(n_0_0_27)); + AOI211_X1_LVT i_0_0_47 (.A(DAddr[1]), .B(n_0_0_83), .C1(n_0_0_94), .C2( + DWidth[1]), .ZN(n_0_0_28)); + DFF_X1_LVT \drTmp_reg[7] (.D(mem_rdata[7]), .CK(n_0_76), .Q(drTmp[7]), .QN()); + AOI22_X1_LVT i_0_0_45 (.A1(drTmp[23]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[7]), .ZN(n_0_0_26)); + NAND2_X1_LVT i_0_0_44 (.A1(n_0_0_27), .A2(n_0_0_26), .ZN(n_0_18)); + DLH_X1_LVT \DRData[7] (.D(n_0_18), .G(n_0_43), .Q(DRData[7])); + AOI22_X1_LVT i_0_0_43 (.A1(drTmp[30]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[14]), .ZN(n_0_0_25)); + DFF_X1_LVT \drTmp_reg[6] (.D(mem_rdata[6]), .CK(n_0_76), .Q(drTmp[6]), .QN()); + AOI22_X1_LVT i_0_0_42 (.A1(drTmp[22]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[6]), .ZN(n_0_0_24)); + NAND2_X1_LVT i_0_0_41 (.A1(n_0_0_25), .A2(n_0_0_24), .ZN(n_0_17)); + DLH_X1_LVT \DRData[6] (.D(n_0_17), .G(n_0_43), .Q(DRData[6])); + AOI22_X1_LVT i_0_0_40 (.A1(drTmp[29]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[13]), .ZN(n_0_0_23)); + DFF_X1_LVT \drTmp_reg[5] (.D(mem_rdata[5]), .CK(n_0_76), .Q(drTmp[5]), .QN()); + AOI22_X1_LVT i_0_0_39 (.A1(drTmp[21]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[5]), .ZN(n_0_0_22)); + NAND2_X1_LVT i_0_0_38 (.A1(n_0_0_23), .A2(n_0_0_22), .ZN(n_0_16)); + DLH_X1_LVT \DRData[5] (.D(n_0_16), .G(n_0_43), .Q(DRData[5])); + AOI22_X1_LVT i_0_0_37 (.A1(drTmp[28]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[12]), .ZN(n_0_0_21)); + DFF_X1_LVT \drTmp_reg[4] (.D(mem_rdata[4]), .CK(n_0_76), .Q(drTmp[4]), .QN()); + AOI22_X1_LVT i_0_0_36 (.A1(drTmp[20]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[4]), .ZN(n_0_0_20)); + NAND2_X1_LVT i_0_0_35 (.A1(n_0_0_21), .A2(n_0_0_20), .ZN(n_0_15)); + DLH_X1_LVT \DRData[4] (.D(n_0_15), .G(n_0_43), .Q(DRData[4])); + AOI22_X1_LVT i_0_0_34 (.A1(drTmp[27]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[11]), .ZN(n_0_0_19)); + DFF_X1_LVT \drTmp_reg[3] (.D(mem_rdata[3]), .CK(n_0_76), .Q(drTmp[3]), .QN()); + AOI22_X1_LVT i_0_0_33 (.A1(drTmp[19]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[3]), .ZN(n_0_0_18)); + NAND2_X1_LVT i_0_0_32 (.A1(n_0_0_19), .A2(n_0_0_18), .ZN(n_0_14)); + DLH_X1_LVT \DRData[3] (.D(n_0_14), .G(n_0_43), .Q(DRData[3])); + AOI22_X1_LVT i_0_0_31 (.A1(drTmp[26]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[10]), .ZN(n_0_0_17)); + DFF_X1_LVT \drTmp_reg[2] (.D(mem_rdata[2]), .CK(n_0_76), .Q(drTmp[2]), .QN()); + AOI22_X1_LVT i_0_0_30 (.A1(drTmp[18]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[2]), .ZN(n_0_0_16)); + NAND2_X1_LVT i_0_0_29 (.A1(n_0_0_17), .A2(n_0_0_16), .ZN(n_0_13)); + DLH_X1_LVT \DRData[2] (.D(n_0_13), .G(n_0_43), .Q(DRData[2])); + AOI22_X1_LVT i_0_0_28 (.A1(drTmp[25]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[9]), .ZN(n_0_0_15)); + DFF_X1_LVT \drTmp_reg[1] (.D(mem_rdata[1]), .CK(n_0_76), .Q(drTmp[1]), .QN()); + AOI22_X1_LVT i_0_0_27 (.A1(drTmp[17]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[1]), .ZN(n_0_0_14)); + NAND2_X1_LVT i_0_0_26 (.A1(n_0_0_15), .A2(n_0_0_14), .ZN(n_0_12)); + DLH_X1_LVT \DRData[1] (.D(n_0_12), .G(n_0_43), .Q(DRData[1])); + AOI22_X1_LVT i_0_0_25 (.A1(drTmp[24]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[8]), .ZN(n_0_0_13)); + DFF_X1_LVT \drTmp_reg[0] (.D(mem_rdata[0]), .CK(n_0_76), .Q(drTmp[0]), .QN()); + AOI22_X1_LVT i_0_0_24 (.A1(drTmp[16]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[0]), .ZN(n_0_0_12)); + NAND2_X1_LVT i_0_0_23 (.A1(n_0_0_13), .A2(n_0_0_12), .ZN(n_0_11)); + DLH_X1_LVT \DRData[0] (.D(n_0_11), .G(n_0_43), .Q(DRData[0])); + DFF_X1_LVT \IRData_reg[31] (.D(mem_rdata[31]), .CK(clk), .Q(IRData[31]), + .QN()); + DFF_X1_LVT \IRData_reg[30] (.D(mem_rdata[30]), .CK(clk), .Q(IRData[30]), + .QN()); + DFF_X1_LVT \IRData_reg[29] (.D(mem_rdata[29]), .CK(clk), .Q(IRData[29]), + .QN()); + DFF_X1_LVT \IRData_reg[28] (.D(mem_rdata[28]), .CK(clk), .Q(IRData[28]), + .QN()); + DFF_X1_LVT \IRData_reg[27] (.D(mem_rdata[27]), .CK(clk), .Q(IRData[27]), + .QN()); + DFF_X1_LVT \IRData_reg[26] (.D(mem_rdata[26]), .CK(clk), .Q(IRData[26]), + .QN()); + DFF_X1_LVT \IRData_reg[25] (.D(mem_rdata[25]), .CK(clk), .Q(IRData[25]), + .QN()); + DFF_X1_LVT \IRData_reg[24] (.D(mem_rdata[24]), .CK(clk), .Q(IRData[24]), + .QN()); + DFF_X1_LVT \IRData_reg[23] (.D(mem_rdata[23]), .CK(clk), .Q(IRData[23]), + .QN()); + DFF_X1_LVT \IRData_reg[22] (.D(mem_rdata[22]), .CK(clk), .Q(IRData[22]), + .QN()); + DFF_X1_LVT \IRData_reg[21] (.D(mem_rdata[21]), .CK(clk), .Q(IRData[21]), + .QN()); + DFF_X1_LVT \IRData_reg[20] (.D(mem_rdata[20]), .CK(clk), .Q(IRData[20]), + .QN()); + DFF_X1_LVT \IRData_reg[19] (.D(mem_rdata[19]), .CK(clk), .Q(IRData[19]), + .QN()); + DFF_X1_LVT \IRData_reg[18] (.D(mem_rdata[18]), .CK(clk), .Q(IRData[18]), + .QN()); + DFF_X1_LVT \IRData_reg[17] (.D(mem_rdata[17]), .CK(clk), .Q(IRData[17]), + .QN()); + DFF_X1_LVT \IRData_reg[16] (.D(mem_rdata[16]), .CK(clk), .Q(IRData[16]), + .QN()); + DFF_X1_LVT \IRData_reg[15] (.D(mem_rdata[15]), .CK(clk), .Q(IRData[15]), + .QN()); + DFF_X1_LVT \IRData_reg[14] (.D(mem_rdata[14]), .CK(clk), .Q(IRData[14]), + .QN()); + DFF_X1_LVT \IRData_reg[13] (.D(mem_rdata[13]), .CK(clk), .Q(IRData[13]), + .QN()); + DFF_X1_LVT \IRData_reg[12] (.D(mem_rdata[12]), .CK(clk), .Q(IRData[12]), + .QN()); + DFF_X1_LVT \IRData_reg[11] (.D(mem_rdata[11]), .CK(clk), .Q(IRData[11]), + .QN()); + DFF_X1_LVT \IRData_reg[10] (.D(mem_rdata[10]), .CK(clk), .Q(IRData[10]), + .QN()); + DFF_X1_LVT \IRData_reg[9] (.D(mem_rdata[9]), .CK(clk), .Q(IRData[9]), .QN()); + DFF_X1_LVT \IRData_reg[8] (.D(mem_rdata[8]), .CK(clk), .Q(IRData[8]), .QN()); + DFF_X1_LVT \IRData_reg[7] (.D(mem_rdata[7]), .CK(clk), .Q(IRData[7]), .QN()); + DFF_X1_LVT \IRData_reg[6] (.D(mem_rdata[6]), .CK(clk), .Q(IRData[6]), .QN()); + DFF_X1_LVT \IRData_reg[5] (.D(mem_rdata[5]), .CK(clk), .Q(IRData[5]), .QN()); + DFF_X1_LVT \IRData_reg[4] (.D(mem_rdata[4]), .CK(clk), .Q(IRData[4]), .QN()); + DFF_X1_LVT \IRData_reg[3] (.D(mem_rdata[3]), .CK(clk), .Q(IRData[3]), .QN()); + DFF_X1_LVT \IRData_reg[2] (.D(mem_rdata[2]), .CK(clk), .Q(IRData[2]), .QN()); + DFF_X1_LVT \IRData_reg[1] (.D(mem_rdata[1]), .CK(clk), .Q(IRData[1]), .QN()); + DFF_X1_LVT \IRData_reg[0] (.D(mem_rdata[0]), .CK(clk), .Q(IRData[0]), .QN()); +endmodule + +module alu(aluOp, aluNegAr, aluBypass, op1, op2, result, eqFlag); + input [2:0]aluOp; + input aluNegAr; + input aluBypass; + input [31:0]op1; + input [31:0]op2; + output [31:0]result; + output eqFlag; + + wire n_9_0; + wire n_9_1; + wire n_9_2; + wire n_9_3; + wire n_9_4; + wire n_9_5; + wire n_9_6; + wire n_9_7; + wire n_9_8; + wire n_9_9; + wire n_9_10; + wire n_9_11; + wire n_9_12; + wire n_9_13; + wire n_9_14; + wire n_9_15; + wire n_9_16; + wire n_9_17; + wire n_9_18; + wire n_9_19; + wire n_9_20; + wire n_9_21; + wire n_9_22; + wire n_9_23; + wire n_9_24; + wire n_9_25; + wire n_9_26; + wire n_9_27; + wire n_9_28; + wire n_9_29; + wire n_9_30; + wire n_9_31; + wire n_10_0; + wire n_10_1; + wire n_10_2; + wire n_10_3; + wire n_10_4; + wire n_10_5; + wire n_10_6; + wire n_10_7; + wire n_10_8; + wire n_10_9; + wire n_10_10; + wire n_10_11; + wire n_10_12; + wire n_10_13; + wire n_10_14; + wire n_10_15; + wire n_10_16; + wire n_10_17; + wire n_10_18; + wire n_10_19; + wire n_10_20; + wire n_10_21; + wire n_10_22; + wire n_10_23; + wire n_10_24; + wire n_10_25; + wire n_10_26; + wire n_10_27; + wire n_10_28; + wire n_10_29; + wire n_10_30; + wire n_10_31; + wire n_10_32; + wire n_10_33; + wire n_10_34; + wire n_10_35; + wire n_10_36; + wire n_10_37; + wire n_10_38; + wire n_10_39; + wire n_10_40; + wire n_10_41; + wire n_10_42; + wire n_10_43; + wire n_10_44; + wire n_10_45; + wire n_10_46; + wire n_10_47; + wire n_10_48; + wire n_10_49; + wire n_10_50; + wire n_10_51; + wire n_10_52; + wire n_10_53; + wire n_10_54; + wire n_10_55; + wire n_10_56; + wire n_10_57; + wire n_10_58; + wire n_10_59; + wire n_10_60; + wire n_10_61; + wire n_10_62; + wire n_10_63; + wire n_10_64; + wire n_10_65; + wire n_10_66; + wire n_10_67; + wire n_10_68; + wire n_10_69; + wire n_10_70; + wire n_10_71; + wire n_10_72; + wire n_10_73; + wire n_10_74; + wire n_10_75; + wire n_10_76; + wire n_10_77; + wire n_10_78; + wire n_10_79; + wire n_10_80; + wire n_10_81; + wire n_10_82; + wire n_10_83; + wire n_10_84; + wire n_10_85; + wire n_10_86; + wire n_10_87; + wire n_10_88; + wire n_10_89; + wire n_10_90; + wire n_10_91; + wire n_10_92; + wire n_10_93; + wire n_10_94; + wire n_10_95; + wire n_10_96; + wire n_10_97; + wire n_10_98; + wire n_10_99; + wire n_10_100; + wire n_10_101; + wire n_10_102; + wire n_10_103; + wire n_10_104; + wire n_10_105; + wire n_10_106; + wire n_10_107; + wire n_10_108; + wire n_10_109; + wire n_10_110; + wire n_10_111; + wire n_10_112; + wire n_10_113; + wire n_10_114; + wire n_10_115; + wire n_10_116; + wire n_10_117; + wire n_10_118; + wire n_10_119; + wire n_10_120; + wire n_10_121; + wire n_10_122; + wire n_10_123; + wire n_0_0; + wire n_0_1; + wire n_0_2; + wire n_0_3; + wire n_0_4; + wire n_0_5; + wire n_0_6; + wire n_0_7; + wire n_0_8; + wire n_0_9; + wire n_0_10; + wire n_0_11; + wire n_0_12; + wire n_0_13; + wire n_0_14; + wire n_0_15; + wire n_0_16; + wire n_0_17; + wire n_0_18; + wire n_0_19; + wire n_0_20; + wire n_0_21; + wire n_0_22; + wire n_0_23; + wire n_0_24; + wire n_0_25; + wire n_0_26; + wire n_0_27; + wire n_0_28; + wire n_0_29; + wire n_0_30; + wire n_0_31; + wire n_0_32; + wire n_0_33; + wire n_0_34; + wire n_0_35; + wire n_0_36; + wire n_0_37; + wire n_0_38; + wire n_0_39; + wire n_0_40; + wire n_0_41; + wire n_0_42; + wire n_0_43; + wire n_0_44; + wire n_0_45; + wire n_0_46; + wire n_0_47; + wire n_0_48; + wire n_0_49; + wire n_0_50; + wire n_0_51; + wire n_0_52; + wire n_0_53; + wire n_0_54; + wire n_0_55; + wire n_0_56; + wire n_0_57; + wire n_0_58; + wire n_0_59; + wire n_0_60; + wire n_0_61; + wire n_0_62; + wire n_0_63; + wire n_0_64; + wire n_0_65; + wire n_0_66; + wire n_0_67; + wire n_0_68; + wire n_0_69; + wire n_0_70; + wire n_0_71; + wire n_0_72; + wire n_0_73; + wire n_0_74; + wire n_0_75; + wire n_0_76; + wire n_0_77; + wire n_0_78; + wire n_0_79; + wire n_0_80; + wire n_0_81; + wire n_0_82; + wire n_0_83; + wire n_0_84; + wire n_0_85; + wire n_0_86; + wire n_0_87; + wire n_0_88; + wire n_0_89; + wire n_0_90; + wire n_0_91; + wire n_0_92; + wire n_0_93; + wire n_0_94; + wire n_0_95; + wire n_0_96; + wire n_0_97; + wire n_0_98; + wire n_0_99; + wire n_0_100; + wire n_0_101; + wire n_0_102; + wire n_0_103; + wire n_0_104; + wire n_0_105; + wire n_0_106; + wire n_0_107; + wire n_0_108; + wire n_0_109; + wire n_0_110; + wire n_0_111; + wire n_0_112; + wire n_0_113; + wire n_0_114; + wire n_0_115; + wire n_0_116; + wire n_0_117; + wire n_0_118; + wire n_0_119; + wire n_0_120; + wire n_0_121; + wire n_0_122; + wire n_0_123; + wire n_0_124; + wire n_0_125; + wire n_0_126; + wire n_0_127; + wire n_0_128; + wire n_0_129; + wire n_0_130; + wire n_0_131; + wire n_0_132; + wire n_0_133; + wire n_0_134; + wire n_0_135; + wire n_0_136; + wire n_0_137; + wire n_0_138; + wire n_0_139; + wire n_0_140; + wire n_0_141; + wire n_0_142; + wire n_0_143; + wire n_0_144; + wire n_0_145; + wire n_0_146; + wire n_0_147; + wire n_0_148; + wire n_0_149; + wire n_0_150; + wire n_0_151; + wire n_0_152; + wire n_0_153; + wire n_0_154; + wire n_0_155; + wire n_0_156; + wire n_0_157; + wire n_0_158; + wire n_0_159; + wire n_0_160; + wire n_0_161; + wire n_0_162; + wire n_0_163; + wire n_0_164; + wire n_0_165; + wire n_0_166; + wire n_0_167; + wire n_0_168; + wire n_0_169; + wire n_0_170; + wire n_0_171; + wire n_0_172; + wire n_0_173; + wire n_0_174; + wire n_0_175; + wire n_0_176; + wire n_0_177; + wire n_0_178; + wire n_0_179; + wire n_0_180; + wire n_0_181; + wire n_0_182; + wire n_0_183; + wire n_0_184; + wire n_0_185; + wire n_0_186; + wire n_0_187; + wire n_0_188; + wire n_0_189; + wire n_0_190; + wire n_0_191; + wire n_0_192; + wire n_0_193; + wire n_0_194; + wire n_0_195; + wire n_0_196; + wire n_0_197; + wire n_0_198; + wire n_0_199; + wire n_0_200; + wire n_0_201; + wire n_0_202; + wire n_0_203; + wire n_0_204; + wire n_0_205; + wire n_0_206; + wire n_0_207; + wire n_0_208; + wire n_0_209; + wire n_0_210; + wire n_0_211; + wire n_0_212; + wire n_0_213; + wire n_0_214; + wire n_0_215; + wire n_0_216; + wire n_0_217; + wire n_0_218; + wire n_0_219; + wire n_0_220; + wire n_0_221; + wire n_0_222; + wire n_0_223; + wire n_0_224; + wire n_0_225; + wire n_0_226; + wire n_0_227; + wire n_0_228; + wire n_0_229; + wire n_0_230; + wire n_0_231; + wire n_0_232; + wire n_0_233; + wire n_0_234; + wire n_0_235; + wire n_0_236; + wire n_0_237; + wire n_0_238; + wire n_0_239; + wire n_0_240; + wire n_0_241; + wire n_0_242; + wire n_0_243; + wire n_0_244; + wire n_0_245; + wire n_0_246; + wire n_0_247; + wire n_0_248; + wire n_0_249; + wire n_0_250; + wire n_0_251; + wire n_0_252; + wire n_0_253; + wire n_0_254; + wire n_0_255; + wire n_0_256; + wire n_0_257; + wire n_0_258; + wire n_0_259; + wire n_0_260; + wire n_0_261; + wire n_0_262; + wire n_0_263; + wire n_0_264; + wire n_0_265; + wire n_0_266; + wire n_0_267; + wire n_0_268; + wire n_0_269; + wire n_0_270; + wire n_0_271; + wire n_0_272; + wire n_0_273; + wire n_0_274; + wire n_0_275; + wire n_0_276; + wire n_0_277; + wire n_0_278; + wire n_0_279; + wire n_0_280; + wire n_0_281; + wire n_0_282; + wire n_0_283; + wire n_0_284; + wire n_0_285; + wire n_0_286; + wire n_0_287; + wire n_0_288; + wire n_0_289; + wire n_0_290; + wire n_0_291; + wire n_0_292; + wire n_0_293; + wire n_0_294; + wire n_0_295; + wire n_0_296; + wire n_0_297; + wire n_0_298; + wire n_0_299; + wire n_0_300; + wire n_0_301; + wire n_0_302; + wire n_0_303; + wire n_0_304; + wire n_0_305; + wire n_0_306; + wire n_0_307; + wire n_0_308; + wire n_0_309; + wire n_0_310; + wire n_0_311; + wire n_0_312; + wire n_0_313; + wire n_0_314; + wire n_0_315; + wire n_0_316; + wire n_0_317; + wire n_0_318; + wire n_0_319; + wire n_0_320; + wire n_0_321; + wire n_0_322; + wire n_0_323; + wire n_0_324; + wire n_0_325; + wire n_0_326; + wire n_0_327; + wire n_0_328; + wire n_0_329; + wire n_0_330; + wire n_0_331; + wire n_0_332; + wire n_0_333; + wire n_0_334; + wire n_0_335; + wire n_0_336; + wire n_0_337; + wire n_0_338; + wire n_0_339; + wire n_0_340; + wire n_0_341; + wire n_0_342; + wire n_0_343; + wire n_0_344; + wire n_0_345; + wire n_0_346; + wire n_0_347; + wire n_0_348; + wire n_0_349; + wire n_0_350; + wire n_0_351; + wire n_0_352; + wire n_0_353; + wire n_0_354; + wire n_0_355; + wire n_0_356; + wire n_0_357; + wire n_0_358; + wire n_0_359; + wire n_0_360; + wire n_0_361; + wire n_0_362; + wire n_0_363; + wire n_0_364; + wire n_0_365; + wire n_0_366; + wire n_0_367; + wire n_0_368; + wire n_0_369; + wire n_0_370; + wire n_0_371; + wire n_0_372; + wire n_0_373; + wire n_0_374; + wire n_0_375; + wire n_0_376; + wire n_0_377; + wire n_0_378; + wire n_0_379; + wire n_0_380; + wire n_0_381; + wire n_0_382; + wire n_0_383; + wire n_0_384; + wire n_0_385; + wire n_0_386; + wire n_0_387; + wire n_0_388; + wire n_0_389; + wire n_0_390; + wire n_0_391; + wire n_0_392; + wire n_0_393; + wire n_0_394; + wire n_0_395; + wire n_0_396; + wire n_0_397; + wire n_0_398; + wire n_0_399; + wire n_0_400; + wire n_0_401; + wire n_0_402; + wire n_0_403; + wire n_0_404; + wire n_0_405; + wire n_0_406; + wire n_0_407; + wire n_0_408; + wire n_0_409; + wire n_0_410; + wire n_0_411; + wire n_0_412; + wire n_0_413; + wire n_0_414; + wire n_0_415; + wire n_0_416; + wire n_0_417; + wire n_0_418; + wire n_0_419; + wire n_0_420; + wire n_0_421; + wire n_0_422; + wire n_0_423; + wire n_0_424; + wire n_0_425; + wire n_0_426; + wire n_0_427; + wire n_0_428; + wire n_0_429; + wire n_0_430; + wire n_0_431; + wire n_0_432; + wire n_0_433; + wire n_0_434; + wire n_0_435; + wire n_0_436; + wire n_0_437; + wire n_0_438; + wire n_0_439; + wire n_0_440; + wire n_0_441; + wire n_0_442; + wire n_0_443; + wire n_0_444; + wire n_0_445; + wire n_0_446; + wire n_0_447; + wire n_0_448; + wire n_0_449; + wire n_0_450; + wire n_0_451; + wire n_0_452; + wire n_0_453; + wire n_0_454; + wire n_0_455; + wire n_0_456; + wire n_0_457; + wire n_0_458; + wire n_0_459; + wire n_0_460; + wire n_0_461; + wire n_0_462; + wire n_0_463; + wire n_0_464; + wire n_0_465; + wire n_0_466; + wire n_0_467; + wire n_0_468; + wire n_0_469; + wire n_0_470; + wire n_0_471; + wire n_0_472; + wire n_0_473; + wire n_0_474; + wire n_0_475; + wire n_0_476; + wire n_0_477; + wire n_0_478; + wire n_0_479; + wire n_0_480; + wire n_0_481; + wire n_0_482; + wire n_0_483; + wire n_0_484; + wire n_0_485; + wire n_0_486; + wire n_0_487; + wire n_0_488; + wire n_0_489; + wire n_0_490; + wire n_0_491; + wire n_0_492; + wire n_0_493; + wire n_0_494; + wire n_0_495; + wire n_0_496; + wire n_0_497; + wire n_0_498; + wire n_0_499; + wire n_0_500; + wire n_0_501; + wire n_0_502; + wire n_0_503; + wire n_0_504; + wire n_0_505; + wire n_0_506; + wire n_0_507; + wire n_0_508; + wire n_0_509; + wire n_0_510; + wire n_0_511; + wire n_0_512; + wire n_0_513; + wire n_0_514; + wire n_0_515; + wire n_0_516; + wire n_0_517; + wire n_0_518; + wire n_0_519; + wire n_0_520; + wire n_0_521; + wire n_0_522; + wire n_0_523; + wire n_0_524; + wire n_0_525; + wire n_0_526; + wire n_0_527; + wire n_0_528; + wire n_0_529; + wire n_0_530; + wire n_0_531; + wire n_0_532; + wire n_0_533; + wire n_0_534; + wire n_0_535; + wire n_0_536; + wire n_0_537; + wire n_0_538; + wire n_0_539; + wire n_0_540; + wire n_0_541; + wire n_0_542; + wire n_0_543; + wire n_0_544; + wire n_0_545; + wire n_0_546; + wire n_0_547; + wire n_0_548; + wire n_0_549; + wire n_0_550; + wire n_0_551; + wire n_0_552; + wire n_0_553; + wire n_0_554; + wire n_0_555; + wire n_0_556; + wire n_0_557; + wire n_0_558; + wire n_0_559; + wire n_0_560; + wire n_0_561; + wire n_0_562; + wire n_0_563; + wire n_0_564; + wire n_0_565; + wire n_0_566; + wire n_0_567; + wire n_0_568; + wire n_0_569; + wire n_0_570; + wire n_0_571; + wire n_0_572; + wire n_0_573; + wire n_0_574; + wire n_0_575; + wire n_0_576; + wire n_0_577; + wire n_0_578; + wire n_0_579; + wire n_0_580; + wire n_0_581; + wire n_0_582; + wire n_0_583; + wire n_0_584; + wire n_0_585; + wire n_0_586; + wire n_0_587; + wire n_0_588; + wire n_0_589; + wire n_0_590; + wire n_0_591; + wire n_0_592; + wire n_0_593; + wire n_0_594; + wire n_0_595; + wire n_0_596; + wire n_0_597; + wire n_0_598; + wire n_0_599; + wire n_0_600; + wire n_0_601; + wire n_0_602; + wire n_0_603; + wire n_0_604; + wire n_0_605; + wire n_0_606; + wire n_0_607; + wire n_0_608; + wire n_0_609; + wire n_0_610; + wire n_0_611; + wire n_0_612; + wire n_0_613; + wire n_0_614; + wire n_0_615; + wire n_0_616; + wire n_0_617; + wire n_0_618; + wire n_0_619; + wire n_0_620; + wire n_0_621; + wire n_0_622; + wire n_0_623; + wire n_0_624; + wire n_0_625; + wire n_0_626; + wire n_0_627; + wire n_0_628; + wire n_0_629; + wire n_0_630; + wire n_0_631; + wire n_0_632; + wire n_0_633; + wire n_0_634; + wire n_0_635; + wire n_0_636; + wire n_0_637; + wire n_0_638; + wire n_0_639; + wire n_0_640; + wire n_0_641; + wire n_0_642; + wire n_0_643; + wire n_0_644; + wire n_0_645; + wire n_0_646; + wire n_0_647; + wire n_0_648; + wire n_0_649; + wire n_0_650; + wire n_0_651; + wire n_0_652; + wire n_0_653; + wire n_0_654; + wire n_0_655; + wire n_0_656; + wire n_0_657; + wire n_0_658; + wire n_0_659; + wire n_0_660; + wire n_0_661; + wire n_0_662; + wire n_0_663; + wire n_0_664; + wire n_0_665; + wire n_0_666; + wire n_0_667; + wire n_0_668; + wire n_0_669; + wire n_0_670; + wire n_0_671; + wire n_0_672; + wire n_0_673; + wire n_0_674; + wire n_0_675; + wire n_0_676; + wire n_0_677; + wire n_0_678; + wire n_0_679; + wire n_0_680; + wire n_0_681; + wire n_0_682; + wire n_0_683; + wire n_0_684; + wire n_0_685; + wire n_0_686; + wire n_0_687; + wire n_0_688; + wire n_0_689; + wire n_0_690; + wire n_0_691; + wire n_0_692; + wire n_0_693; + wire n_0_694; + wire n_0_695; + wire n_0_696; + wire n_0_697; + wire n_0_698; + wire n_0_699; + wire n_0_700; + wire n_0_701; + wire n_0_702; + wire n_0_703; + wire n_0_704; + wire n_0_705; + wire n_0_706; + wire n_0_707; + wire n_0_708; + wire n_0_709; + wire n_0_710; + wire n_0_711; + wire n_0_712; + wire n_0_713; + wire n_0_714; + wire n_0_715; + wire n_0_716; + wire n_0_717; + wire n_0_718; + wire n_0_719; + wire n_0_720; + wire n_0_721; + wire n_0_722; + wire n_0_723; + wire n_0_724; + wire n_0_725; + wire n_0_726; + wire n_0_727; + wire n_0_728; + wire n_0_729; + wire n_0_730; + wire n_0_731; + wire n_0_732; + wire n_0_733; + wire n_0_734; + wire n_0_735; + wire n_0_736; + wire n_0_737; + wire n_0_738; + wire n_0_739; + wire n_0_740; + + INV_X1_LVT i_0_725 (.A(op2[31]), .ZN(n_0_692)); + INV_X1_LVT i_0_724 (.A(op1[31]), .ZN(n_0_691)); + INV_X1_LVT i_0_718 (.A(aluOp[1]), .ZN(n_0_685)); + INV_X1_LVT i_0_717 (.A(aluOp[2]), .ZN(n_0_684)); + NOR2_X1_LVT i_0_599 (.A1(n_0_685), .A2(n_0_684), .ZN(n_0_567)); + INV_X1_LVT i_0_598 (.A(n_0_567), .ZN(n_0_566)); + INV_X1_LVT i_0_716 (.A(aluOp[0]), .ZN(n_0_683)); + NAND2_X1_LVT i_0_602 (.A1(aluOp[2]), .A2(aluNegAr), .ZN(n_0_570)); + OAI21_X1_LVT i_0_590 (.A(n_0_566), .B1(n_0_683), .B2(n_0_570), .ZN(n_0_558)); + INV_X1_LVT i_0_714 (.A(aluBypass), .ZN(n_0_681)); + NOR2_X1_LVT i_0_601 (.A1(n_0_684), .A2(aluOp[0]), .ZN(n_0_569)); + NAND2_X1_LVT i_0_597 (.A1(n_0_681), .A2(n_0_569), .ZN(n_0_565)); + INV_X1_LVT i_0_596 (.A(n_0_565), .ZN(n_0_564)); + OAI22_X1_LVT i_0_589 (.A1(n_0_691), .A2(n_0_558), .B1(op1[31]), .B2(n_0_564), + .ZN(n_0_557)); + NOR2_X1_LVT i_0_588 (.A1(n_0_692), .A2(n_0_557), .ZN(n_0_556)); + XNOR2_X1_LVT i_9_31 (.A(op2[31]), .B(op1[31]), .ZN(n_9_31)); + HA_X1_LVT i_9_0 (.A(op2[0]), .B(op1[0]), .CO(n_9_0), .S(n_0)); + FA_X1_LVT i_9_1 (.A(op2[1]), .B(op1[1]), .CI(n_9_0), .CO(n_9_1), .S(n_1)); + FA_X1_LVT i_9_2 (.A(op2[2]), .B(op1[2]), .CI(n_9_1), .CO(n_9_2), .S(n_2)); + FA_X1_LVT i_9_3 (.A(op2[3]), .B(op1[3]), .CI(n_9_2), .CO(n_9_3), .S(n_3)); + FA_X1_LVT i_9_4 (.A(op2[4]), .B(op1[4]), .CI(n_9_3), .CO(n_9_4), .S(n_4)); + FA_X1_LVT i_9_5 (.A(op2[5]), .B(op1[5]), .CI(n_9_4), .CO(n_9_5), .S(n_5)); + FA_X1_LVT i_9_6 (.A(op2[6]), .B(op1[6]), .CI(n_9_5), .CO(n_9_6), .S(n_6)); + FA_X1_LVT i_9_7 (.A(op2[7]), .B(op1[7]), .CI(n_9_6), .CO(n_9_7), .S(n_7)); + FA_X1_LVT i_9_8 (.A(op2[8]), .B(op1[8]), .CI(n_9_7), .CO(n_9_8), .S(n_8)); + FA_X1_LVT i_9_9 (.A(op2[9]), .B(op1[9]), .CI(n_9_8), .CO(n_9_9), .S(n_9)); + FA_X1_LVT i_9_10 (.A(op2[10]), .B(op1[10]), .CI(n_9_9), .CO(n_9_10), .S(n_10)); + FA_X1_LVT i_9_11 (.A(op2[11]), .B(op1[11]), .CI(n_9_10), .CO(n_9_11), + .S(n_11)); + FA_X1_LVT i_9_12 (.A(op2[12]), .B(op1[12]), .CI(n_9_11), .CO(n_9_12), + .S(n_12)); + FA_X1_LVT i_9_13 (.A(op2[13]), .B(op1[13]), .CI(n_9_12), .CO(n_9_13), + .S(n_13)); + FA_X1_LVT i_9_14 (.A(op2[14]), .B(op1[14]), .CI(n_9_13), .CO(n_9_14), + .S(n_14)); + FA_X1_LVT i_9_15 (.A(op2[15]), .B(op1[15]), .CI(n_9_14), .CO(n_9_15), + .S(n_15)); + FA_X1_LVT i_9_16 (.A(op2[16]), .B(op1[16]), .CI(n_9_15), .CO(n_9_16), + .S(n_16)); + FA_X1_LVT i_9_17 (.A(op2[17]), .B(op1[17]), .CI(n_9_16), .CO(n_9_17), + .S(n_17)); + FA_X1_LVT i_9_18 (.A(op2[18]), .B(op1[18]), .CI(n_9_17), .CO(n_9_18), + .S(n_18)); + FA_X1_LVT i_9_19 (.A(op2[19]), .B(op1[19]), .CI(n_9_18), .CO(n_9_19), + .S(n_19)); + FA_X1_LVT i_9_20 (.A(op2[20]), .B(op1[20]), .CI(n_9_19), .CO(n_9_20), + .S(n_20)); + FA_X1_LVT i_9_21 (.A(op2[21]), .B(op1[21]), .CI(n_9_20), .CO(n_9_21), + .S(n_21)); + FA_X1_LVT i_9_22 (.A(op2[22]), .B(op1[22]), .CI(n_9_21), .CO(n_9_22), + .S(n_22)); + FA_X1_LVT i_9_23 (.A(op2[23]), .B(op1[23]), .CI(n_9_22), .CO(n_9_23), + .S(n_23)); + FA_X1_LVT i_9_24 (.A(op2[24]), .B(op1[24]), .CI(n_9_23), .CO(n_9_24), + .S(n_24)); + FA_X1_LVT i_9_25 (.A(op2[25]), .B(op1[25]), .CI(n_9_24), .CO(n_9_25), + .S(n_25)); + FA_X1_LVT i_9_26 (.A(op2[26]), .B(op1[26]), .CI(n_9_25), .CO(n_9_26), + .S(n_26)); + FA_X1_LVT i_9_27 (.A(op2[27]), .B(op1[27]), .CI(n_9_26), .CO(n_9_27), + .S(n_27)); + FA_X1_LVT i_9_28 (.A(op2[28]), .B(op1[28]), .CI(n_9_27), .CO(n_9_28), + .S(n_28)); + FA_X1_LVT i_9_29 (.A(op2[29]), .B(op1[29]), .CI(n_9_28), .CO(n_9_29), + .S(n_29)); + FA_X1_LVT i_9_30 (.A(op2[30]), .B(op1[30]), .CI(n_9_29), .CO(n_9_30), + .S(n_30)); + XNOR2_X1_LVT i_9_32 (.A(n_9_31), .B(n_9_30), .ZN(n_31)); + NAND4_X1_LVT i_0_614 (.A1(n_0_685), .A2(n_0_681), .A3(n_0_684), .A4(n_0_683), + .ZN(n_0_582)); + NOR2_X1_LVT i_0_613 (.A1(aluNegAr), .A2(n_0_582), .ZN(n_0_581)); + INV_X1_LVT i_10_147 (.A(op2[30]), .ZN(n_10_117)); + NAND2_X1_LVT i_10_149 (.A1(n_10_117), .A2(op1[30]), .ZN(n_10_119)); + INV_X1_LVT i_10_152 (.A(n_10_119), .ZN(n_10_121)); + INV_X1_LVT i_10_130 (.A(op1[26]), .ZN(n_10_104)); + NAND2_X1_LVT i_10_131 (.A1(n_10_104), .A2(op2[26]), .ZN(n_10_105)); + INV_X1_LVT i_10_123 (.A(op2[25]), .ZN(n_10_98)); + NAND2_X1_LVT i_10_125 (.A1(n_10_98), .A2(op1[25]), .ZN(n_10_100)); + INV_X1_LVT i_10_112 (.A(op2[23]), .ZN(n_10_89)); + NAND2_X1_LVT i_10_114 (.A1(n_10_89), .A2(op1[23]), .ZN(n_10_91)); + INV_X1_LVT i_10_101 (.A(op2[21]), .ZN(n_10_80)); + NAND2_X1_LVT i_10_103 (.A1(n_10_80), .A2(op1[21]), .ZN(n_10_82)); + INV_X1_LVT i_10_48 (.A(op1[8]), .ZN(n_10_40)); + NAND2_X1_LVT i_10_49 (.A1(n_10_40), .A2(op2[8]), .ZN(n_10_41)); + INV_X1_LVT i_10_41 (.A(op2[7]), .ZN(n_10_34)); + NAND2_X1_LVT i_10_43 (.A1(n_10_34), .A2(op1[7]), .ZN(n_10_36)); + INV_X1_LVT i_10_32 (.A(op2[5]), .ZN(n_10_27)); + NOR2_X1_LVT i_10_33 (.A1(n_10_27), .A2(op1[5]), .ZN(n_10_28)); + INV_X1_LVT i_10_24 (.A(op1[4]), .ZN(n_10_20)); + NOR2_X1_LVT i_10_27 (.A1(n_10_20), .A2(op2[4]), .ZN(n_10_23)); + INV_X1_LVT i_10_17 (.A(op2[3]), .ZN(n_10_14)); + NAND2_X1_LVT i_10_19 (.A1(n_10_14), .A2(op1[3]), .ZN(n_10_16)); + INV_X1_LVT i_10_22 (.A(n_10_16), .ZN(n_10_18)); + INV_X1_LVT i_10_10 (.A(op2[2]), .ZN(n_10_8)); + NAND2_X1_LVT i_10_12 (.A1(n_10_8), .A2(op1[2]), .ZN(n_10_10)); + INV_X1_LVT i_10_3 (.A(op1[1]), .ZN(n_10_2)); + NAND2_X1_LVT i_10_5 (.A1(n_10_2), .A2(op2[1]), .ZN(n_10_4)); + INV_X1_LVT i_10_0 (.A(op1[0]), .ZN(n_10_0)); + NAND2_X1_LVT i_10_1 (.A1(n_10_0), .A2(op2[0]), .ZN(n_10_1)); + OR2_X1_LVT i_10_4 (.A1(n_10_2), .A2(op2[1]), .ZN(n_10_3)); + INV_X1_LVT i_10_8 (.A(n_10_3), .ZN(n_10_6)); + OAI21_X1_LVT i_10_9 (.A(n_10_4), .B1(n_10_1), .B2(n_10_6), .ZN(n_10_7)); + NOR2_X1_LVT i_10_11 (.A1(n_10_8), .A2(op1[2]), .ZN(n_10_9)); + OAI21_X1_LVT i_10_16 (.A(n_10_10), .B1(n_10_7), .B2(n_10_9), .ZN(n_10_13)); + OR2_X1_LVT i_10_18 (.A1(n_10_14), .A2(op1[3]), .ZN(n_10_15)); + AOI21_X1_LVT i_10_23 (.A(n_10_18), .B1(n_10_13), .B2(n_10_15), .ZN(n_10_19)); + INV_X1_LVT i_10_30 (.A(n_10_19), .ZN(n_10_25)); + NAND2_X1_LVT i_10_25 (.A1(n_10_20), .A2(op2[4]), .ZN(n_10_21)); + AOI21_X1_LVT i_10_31 (.A(n_10_23), .B1(n_10_25), .B2(n_10_21), .ZN(n_10_26)); + AOI21_X1_LVT i_10_34 (.A(n_10_28), .B1(n_10_27), .B2(op1[5]), .ZN(n_10_29)); + AOI21_X1_LVT i_10_36 (.A(n_10_28), .B1(n_10_26), .B2(n_10_29), .ZN(n_10_30)); + XOR2_X1_LVT i_10_37 (.A(op2[6]), .B(op1[6]), .Z(n_10_31)); + INV_X1_LVT i_10_39 (.A(op2[6]), .ZN(n_10_32)); + OAI22_X1_LVT i_10_40 (.A1(n_10_30), .A2(n_10_31), .B1(n_10_32), .B2(op1[6]), + .ZN(n_10_33)); + NOR2_X1_LVT i_10_42 (.A1(n_10_34), .A2(op1[7]), .ZN(n_10_35)); + OAI21_X1_LVT i_10_47 (.A(n_10_36), .B1(n_10_33), .B2(n_10_35), .ZN(n_10_39)); + OAI21_X1_LVT i_10_50 (.A(n_10_41), .B1(n_10_40), .B2(op2[8]), .ZN(n_10_42)); + OAI21_X1_LVT i_10_52 (.A(n_10_41), .B1(n_10_39), .B2(n_10_42), .ZN(n_10_43)); + XNOR2_X1_LVT i_10_53 (.A(op2[9]), .B(op1[9]), .ZN(n_10_44)); + INV_X1_LVT i_10_55 (.A(op1[9]), .ZN(n_10_45)); + AOI22_X1_LVT i_10_56 (.A1(n_10_43), .A2(n_10_44), .B1(n_10_45), .B2(op2[9]), + .ZN(n_10_46)); + XOR2_X1_LVT i_10_57 (.A(op2[10]), .B(op1[10]), .Z(n_10_47)); + INV_X1_LVT i_10_59 (.A(op2[10]), .ZN(n_10_48)); + OAI22_X1_LVT i_10_60 (.A1(n_10_46), .A2(n_10_47), .B1(n_10_48), .B2(op1[10]), + .ZN(n_10_49)); + XNOR2_X1_LVT i_10_61 (.A(op2[11]), .B(op1[11]), .ZN(n_10_50)); + INV_X1_LVT i_10_63 (.A(op1[11]), .ZN(n_10_51)); + AOI22_X1_LVT i_10_64 (.A1(n_10_49), .A2(n_10_50), .B1(n_10_51), .B2(op2[11]), + .ZN(n_10_52)); + XOR2_X1_LVT i_10_65 (.A(op2[12]), .B(op1[12]), .Z(n_10_53)); + INV_X1_LVT i_10_67 (.A(op2[12]), .ZN(n_10_54)); + OAI22_X1_LVT i_10_68 (.A1(n_10_52), .A2(n_10_53), .B1(n_10_54), .B2(op1[12]), + .ZN(n_10_55)); + XNOR2_X1_LVT i_10_69 (.A(op2[13]), .B(op1[13]), .ZN(n_10_56)); + INV_X1_LVT i_10_71 (.A(op1[13]), .ZN(n_10_57)); + AOI22_X1_LVT i_10_72 (.A1(n_10_55), .A2(n_10_56), .B1(n_10_57), .B2(op2[13]), + .ZN(n_10_58)); + XOR2_X1_LVT i_10_73 (.A(op2[14]), .B(op1[14]), .Z(n_10_59)); + INV_X1_LVT i_10_75 (.A(op2[14]), .ZN(n_10_60)); + OAI22_X1_LVT i_10_76 (.A1(n_10_58), .A2(n_10_59), .B1(n_10_60), .B2(op1[14]), + .ZN(n_10_61)); + XNOR2_X1_LVT i_10_77 (.A(op2[15]), .B(op1[15]), .ZN(n_10_62)); + INV_X1_LVT i_10_79 (.A(op1[15]), .ZN(n_10_63)); + AOI22_X1_LVT i_10_80 (.A1(n_10_61), .A2(n_10_62), .B1(n_10_63), .B2(op2[15]), + .ZN(n_10_64)); + XOR2_X1_LVT i_10_81 (.A(op2[16]), .B(op1[16]), .Z(n_10_65)); + INV_X1_LVT i_10_83 (.A(op2[16]), .ZN(n_10_66)); + OAI22_X1_LVT i_10_84 (.A1(n_10_64), .A2(n_10_65), .B1(n_10_66), .B2(op1[16]), + .ZN(n_10_67)); + XNOR2_X1_LVT i_10_85 (.A(op2[17]), .B(op1[17]), .ZN(n_10_68)); + INV_X1_LVT i_10_87 (.A(op1[17]), .ZN(n_10_69)); + AOI22_X1_LVT i_10_88 (.A1(n_10_67), .A2(n_10_68), .B1(n_10_69), .B2(op2[17]), + .ZN(n_10_70)); + XOR2_X1_LVT i_10_89 (.A(op2[18]), .B(op1[18]), .Z(n_10_71)); + INV_X1_LVT i_10_91 (.A(op2[18]), .ZN(n_10_72)); + OAI22_X1_LVT i_10_92 (.A1(n_10_70), .A2(n_10_71), .B1(n_10_72), .B2(op1[18]), + .ZN(n_10_73)); + XNOR2_X1_LVT i_10_93 (.A(op2[19]), .B(op1[19]), .ZN(n_10_74)); + INV_X1_LVT i_10_95 (.A(op1[19]), .ZN(n_10_75)); + AOI22_X1_LVT i_10_96 (.A1(n_10_73), .A2(n_10_74), .B1(n_10_75), .B2(op2[19]), + .ZN(n_10_76)); + XOR2_X1_LVT i_10_97 (.A(op2[20]), .B(op1[20]), .Z(n_10_77)); + INV_X1_LVT i_10_99 (.A(op2[20]), .ZN(n_10_78)); + OAI22_X1_LVT i_10_100 (.A1(n_10_76), .A2(n_10_77), .B1(n_10_78), .B2(op1[20]), + .ZN(n_10_79)); + NOR2_X1_LVT i_10_102 (.A1(n_10_80), .A2(op1[21]), .ZN(n_10_81)); + OAI21_X1_LVT i_10_107 (.A(n_10_82), .B1(n_10_79), .B2(n_10_81), .ZN(n_10_85)); + XOR2_X1_LVT i_10_108 (.A(op2[22]), .B(op1[22]), .Z(n_10_86)); + INV_X1_LVT i_10_110 (.A(op2[22]), .ZN(n_10_87)); + OAI22_X1_LVT i_10_111 (.A1(n_10_85), .A2(n_10_86), .B1(n_10_87), .B2(op1[22]), + .ZN(n_10_88)); + NOR2_X1_LVT i_10_113 (.A1(n_10_89), .A2(op1[23]), .ZN(n_10_90)); + OAI21_X1_LVT i_10_118 (.A(n_10_91), .B1(n_10_88), .B2(n_10_90), .ZN(n_10_94)); + XOR2_X1_LVT i_10_119 (.A(op2[24]), .B(op1[24]), .Z(n_10_95)); + INV_X1_LVT i_10_121 (.A(op2[24]), .ZN(n_10_96)); + OAI22_X1_LVT i_10_122 (.A1(n_10_94), .A2(n_10_95), .B1(n_10_96), .B2(op1[24]), + .ZN(n_10_97)); + NOR2_X1_LVT i_10_124 (.A1(n_10_98), .A2(op1[25]), .ZN(n_10_99)); + OAI21_X1_LVT i_10_129 (.A(n_10_100), .B1(n_10_97), .B2(n_10_99), .ZN(n_10_103)); + OAI21_X1_LVT i_10_132 (.A(n_10_105), .B1(n_10_104), .B2(op2[26]), .ZN( + n_10_106)); + OAI21_X1_LVT i_10_134 (.A(n_10_105), .B1(n_10_103), .B2(n_10_106), .ZN( + n_10_107)); + XNOR2_X1_LVT i_10_135 (.A(op2[27]), .B(op1[27]), .ZN(n_10_108)); + INV_X1_LVT i_10_137 (.A(op1[27]), .ZN(n_10_109)); + AOI22_X1_LVT i_10_138 (.A1(n_10_107), .A2(n_10_108), .B1(n_10_109), .B2( + op2[27]), .ZN(n_10_110)); + XOR2_X1_LVT i_10_139 (.A(op2[28]), .B(op1[28]), .Z(n_10_111)); + INV_X1_LVT i_10_141 (.A(op2[28]), .ZN(n_10_112)); + OAI22_X1_LVT i_10_142 (.A1(n_10_110), .A2(n_10_111), .B1(n_10_112), .B2( + op1[28]), .ZN(n_10_113)); + XNOR2_X1_LVT i_10_143 (.A(op2[29]), .B(op1[29]), .ZN(n_10_114)); + INV_X1_LVT i_10_145 (.A(op1[29]), .ZN(n_10_115)); + AOI22_X1_LVT i_10_146 (.A1(n_10_113), .A2(n_10_114), .B1(n_10_115), .B2( + op2[29]), .ZN(n_10_116)); + OR2_X1_LVT i_10_148 (.A1(n_10_117), .A2(op1[30]), .ZN(n_10_118)); + AOI21_X1_LVT i_10_153 (.A(n_10_121), .B1(n_10_116), .B2(n_10_118), .ZN( + n_10_122)); + XNOR2_X1_LVT i_10_154 (.A(op1[31]), .B(op2[31]), .ZN(n_10_123)); + XNOR2_X1_LVT i_10_155 (.A(n_10_122), .B(n_10_123), .ZN(n_63)); + INV_X1_LVT i_0_715 (.A(aluNegAr), .ZN(n_0_682)); + NOR2_X1_LVT i_0_612 (.A1(n_0_682), .A2(n_0_582), .ZN(n_0_580)); + AOI221_X1_LVT i_0_587 (.A(n_0_556), .B1(n_31), .B2(n_0_581), .C1(n_63), + .C2(n_0_580), .ZN(n_0_555)); + NOR3_X1_LVT i_0_654 (.A1(aluOp[1]), .A2(aluBypass), .A3(n_0_683), .ZN(n_0_622)); + NAND2_X1_LVT i_0_653 (.A1(n_0_684), .A2(n_0_622), .ZN(n_0_621)); + INV_X1_LVT i_0_734 (.A(op2[0]), .ZN(n_0_701)); + INV_X1_LVT i_0_756 (.A(op2[3]), .ZN(n_0_723)); + NOR2_X1_LVT i_0_650 (.A1(op2[4]), .A2(n_0_723), .ZN(n_0_618)); + INV_X1_LVT i_0_649 (.A(n_0_618), .ZN(n_0_617)); + NOR2_X1_LVT i_0_648 (.A1(op2[4]), .A2(op2[3]), .ZN(n_0_616)); + INV_X1_LVT i_0_647 (.A(n_0_616), .ZN(n_0_615)); + INV_X1_LVT i_0_771 (.A(op2[4]), .ZN(n_0_738)); + INV_X1_LVT i_0_767 (.A(op1[15]), .ZN(n_0_734)); + INV_X1_LVT i_0_746 (.A(op1[7]), .ZN(n_0_713)); + AOI22_X1_LVT i_0_651 (.A1(n_0_734), .A2(n_0_723), .B1(op2[3]), .B2(n_0_713), + .ZN(n_0_619)); + OAI222_X1_LVT i_0_646 (.A1(op1[23]), .A2(n_0_617), .B1(op1[31]), .B2(n_0_615), + .C1(n_0_738), .C2(n_0_619), .ZN(n_0_614)); + NOR2_X1_LVT i_0_645 (.A1(op2[2]), .A2(n_0_614), .ZN(n_0_613)); + NOR2_X1_LVT i_0_696 (.A1(op1[3]), .A2(n_0_723), .ZN(n_0_663)); + INV_X1_LVT i_0_739 (.A(op1[11]), .ZN(n_0_706)); + AOI21_X1_LVT i_0_644 (.A(n_0_663), .B1(n_0_723), .B2(n_0_706), .ZN(n_0_612)); + AOI22_X1_LVT i_0_643 (.A1(op2[4]), .A2(n_0_612), .B1(op1[27]), .B2(n_0_616), + .ZN(n_0_611)); + INV_X1_LVT i_0_722 (.A(op1[19]), .ZN(n_0_689)); + OAI21_X1_LVT i_0_642 (.A(n_0_611), .B1(n_0_689), .B2(n_0_617), .ZN(n_0_610)); + AOI21_X1_LVT i_0_641 (.A(n_0_613), .B1(op2[2]), .B2(n_0_610), .ZN(n_0_609)); + INV_X1_LVT i_0_761 (.A(op2[1]), .ZN(n_0_728)); + OAI22_X1_LVT i_0_640 (.A1(op2[4]), .A2(op1[21]), .B1(n_0_738), .B2(op1[5]), + .ZN(n_0_608)); + NAND2_X1_LVT i_0_639 (.A1(op2[3]), .A2(n_0_608), .ZN(n_0_607)); + INV_X1_LVT i_0_747 (.A(op1[13]), .ZN(n_0_714)); + NOR2_X1_LVT i_0_638 (.A1(n_0_738), .A2(op2[3]), .ZN(n_0_606)); + INV_X1_LVT i_0_743 (.A(op1[29]), .ZN(n_0_710)); + AOI221_X1_LVT i_0_636 (.A(op2[2]), .B1(n_0_714), .B2(n_0_606), .C1(n_0_710), + .C2(n_0_616), .ZN(n_0_604)); + OAI22_X1_LVT i_0_635 (.A1(op2[4]), .A2(op1[17]), .B1(n_0_738), .B2(op1[1]), + .ZN(n_0_603)); + INV_X1_LVT i_0_755 (.A(op1[9]), .ZN(n_0_722)); + INV_X1_LVT i_0_637 (.A(n_0_606), .ZN(n_0_605)); + INV_X1_LVT i_0_732 (.A(op1[25]), .ZN(n_0_699)); + OAI222_X1_LVT i_0_634 (.A1(n_0_723), .A2(n_0_603), .B1(n_0_722), .B2(n_0_605), + .C1(n_0_699), .C2(n_0_615), .ZN(n_0_602)); + AOI22_X1_LVT i_0_633 (.A1(n_0_607), .A2(n_0_604), .B1(op2[2]), .B2(n_0_602), + .ZN(n_0_601)); + OAI221_X1_LVT i_0_616 (.A(n_0_701), .B1(op2[1]), .B2(n_0_609), .C1(n_0_728), + .C2(n_0_601), .ZN(n_0_584)); + INV_X1_LVT i_0_729 (.A(op1[12]), .ZN(n_0_696)); + INV_X1_LVT i_0_731 (.A(op1[28]), .ZN(n_0_698)); + AOI22_X1_LVT i_0_622 (.A1(n_0_696), .A2(n_0_606), .B1(n_0_698), .B2(n_0_616), + .ZN(n_0_590)); + INV_X1_LVT i_0_726 (.A(op2[2]), .ZN(n_0_693)); + NOR2_X1_LVT i_0_701 (.A1(n_0_738), .A2(op1[4]), .ZN(n_0_668)); + INV_X1_LVT i_0_760 (.A(op1[20]), .ZN(n_0_727)); + AOI21_X1_LVT i_0_623 (.A(n_0_668), .B1(n_0_738), .B2(n_0_727), .ZN(n_0_591)); + OAI211_X1_LVT i_0_621 (.A(n_0_590), .B(n_0_693), .C1(n_0_723), .C2(n_0_591), + .ZN(n_0_589)); + OAI22_X1_LVT i_0_626 (.A1(op1[16]), .A2(op2[4]), .B1(n_0_738), .B2(op1[0]), + .ZN(n_0_594)); + INV_X1_LVT i_0_769 (.A(op1[24]), .ZN(n_0_736)); + OAI22_X1_LVT i_0_625 (.A1(n_0_723), .A2(n_0_594), .B1(n_0_736), .B2(n_0_615), + .ZN(n_0_593)); + AOI21_X1_LVT i_0_624 (.A(n_0_593), .B1(op1[8]), .B2(n_0_606), .ZN(n_0_592)); + OAI21_X1_LVT i_0_620 (.A(n_0_589), .B1(n_0_693), .B2(n_0_592), .ZN(n_0_588)); + INV_X1_LVT i_0_737 (.A(op1[6]), .ZN(n_0_704)); + INV_X1_LVT i_0_720 (.A(op1[22]), .ZN(n_0_687)); + OAI22_X1_LVT i_0_632 (.A1(n_0_738), .A2(n_0_704), .B1(op2[4]), .B2(n_0_687), + .ZN(n_0_600)); + OAI221_X1_LVT i_0_631 (.A(n_0_693), .B1(n_0_723), .B2(n_0_600), .C1(op1[14]), + .C2(n_0_605), .ZN(n_0_599)); + INV_X1_LVT i_0_750 (.A(op1[30]), .ZN(n_0_717)); + AOI21_X1_LVT i_0_630 (.A(n_0_599), .B1(n_0_717), .B2(n_0_616), .ZN(n_0_598)); + INV_X1_LVT i_0_738 (.A(op1[18]), .ZN(n_0_705)); + NOR2_X1_LVT i_0_628 (.A1(n_0_705), .A2(n_0_617), .ZN(n_0_596)); + INV_X1_LVT i_0_727 (.A(op1[2]), .ZN(n_0_694)); + INV_X1_LVT i_0_766 (.A(op1[10]), .ZN(n_0_733)); + OAI22_X1_LVT i_0_629 (.A1(n_0_723), .A2(n_0_694), .B1(n_0_733), .B2(op2[3]), + .ZN(n_0_597)); + AOI221_X1_LVT i_0_627 (.A(n_0_596), .B1(op1[26]), .B2(n_0_616), .C1(op2[4]), + .C2(n_0_597), .ZN(n_0_595)); + OAI21_X1_LVT i_0_619 (.A(n_0_728), .B1(n_0_693), .B2(n_0_595), .ZN(n_0_587)); + OAI22_X1_LVT i_0_618 (.A1(n_0_728), .A2(n_0_588), .B1(n_0_598), .B2(n_0_587), + .ZN(n_0_586)); + INV_X1_LVT i_0_617 (.A(n_0_586), .ZN(n_0_585)); + OAI21_X1_LVT i_0_615 (.A(n_0_584), .B1(n_0_701), .B2(n_0_585), .ZN(n_0_583)); + NOR2_X1_LVT i_0_607 (.A1(op2[4]), .A2(op2[2]), .ZN(n_0_575)); + NAND2_X1_LVT i_0_606 (.A1(n_0_723), .A2(n_0_575), .ZN(n_0_574)); + INV_X1_LVT i_0_605 (.A(n_0_574), .ZN(n_0_573)); + NAND2_X1_LVT i_0_604 (.A1(n_0_728), .A2(n_0_573), .ZN(n_0_572)); + NAND2_X1_LVT i_0_611 (.A1(aluOp[2]), .A2(n_0_622), .ZN(n_0_579)); + INV_X1_LVT i_0_610 (.A(n_0_579), .ZN(n_0_578)); + NAND2_X1_LVT i_0_594 (.A1(n_0_701), .A2(n_0_578), .ZN(n_0_562)); + NOR3_X1_LVT i_0_592 (.A1(aluNegAr), .A2(n_0_572), .A3(n_0_562), .ZN(n_0_560)); + INV_X1_LVT i_0_600 (.A(n_0_569), .ZN(n_0_568)); + OAI21_X1_LVT i_0_595 (.A(n_0_568), .B1(aluOp[1]), .B2(n_0_570), .ZN(n_0_563)); + AOI211_X1_LVT i_0_591 (.A(aluBypass), .B(n_0_560), .C1(n_0_692), .C2(n_0_563), + .ZN(n_0_559)); + OAI221_X1_LVT i_0_586 (.A(n_0_555), .B1(n_0_621), .B2(n_0_583), .C1(n_0_691), + .C2(n_0_559), .ZN(result[31])); + NAND2_X1_LVT i_10_150 (.A1(n_10_118), .A2(n_10_119), .ZN(n_10_120)); + XNOR2_X1_LVT i_10_151 (.A(n_10_116), .B(n_10_120), .ZN(n_62)); + AOI22_X1_LVT i_0_580 (.A1(n_62), .A2(n_0_580), .B1(n_30), .B2(n_0_581), + .ZN(n_0_549)); + NAND2_X1_LVT i_0_576 (.A1(aluNegAr), .A2(n_0_578), .ZN(n_0_545)); + INV_X1_LVT i_0_603 (.A(n_0_572), .ZN(n_0_571)); + NOR3_X1_LVT i_0_574 (.A1(n_0_691), .A2(n_0_545), .A3(n_0_571), .ZN(n_0_543)); + AOI22_X1_LVT i_0_573 (.A1(n_0_717), .A2(n_0_565), .B1(op1[30]), .B2(n_0_566), + .ZN(n_0_542)); + AOI21_X1_LVT i_0_572 (.A(n_0_543), .B1(op2[30]), .B2(n_0_542), .ZN(n_0_541)); + NAND2_X1_LVT i_0_579 (.A1(op2[0]), .A2(n_0_578), .ZN(n_0_548)); + NAND2_X1_LVT i_0_577 (.A1(op1[31]), .A2(n_0_571), .ZN(n_0_546)); + OAI211_X1_LVT i_0_571 (.A(n_0_549), .B(n_0_541), .C1(n_0_548), .C2(n_0_546), + .ZN(n_0_540)); + OAI221_X1_LVT i_0_581 (.A(n_0_681), .B1(op2[30]), .B2(n_0_568), .C1(n_0_572), + .C2(n_0_562), .ZN(n_0_550)); + AOI21_X1_LVT i_0_570 (.A(n_0_540), .B1(op1[30]), .B2(n_0_550), .ZN(n_0_539)); + INV_X1_LVT i_0_752 (.A(op1[23]), .ZN(n_0_719)); + OAI222_X1_LVT i_0_585 (.A1(n_0_713), .A2(n_0_605), .B1(n_0_719), .B2(n_0_615), + .C1(n_0_734), .C2(n_0_617), .ZN(n_0_554)); + AOI22_X1_LVT i_0_584 (.A1(op2[2]), .A2(n_0_554), .B1(n_0_693), .B2(n_0_610), + .ZN(n_0_553)); + OAI22_X1_LVT i_0_583 (.A1(n_0_728), .A2(n_0_553), .B1(op2[1]), .B2(n_0_601), + .ZN(n_0_552)); + AOI22_X1_LVT i_0_582 (.A1(n_0_701), .A2(n_0_585), .B1(op2[0]), .B2(n_0_552), + .ZN(n_0_551)); + OAI21_X1_LVT i_0_569 (.A(n_0_539), .B1(n_0_621), .B2(n_0_551), .ZN(result[30])); + INV_X1_LVT i_0_578 (.A(n_0_548), .ZN(n_0_547)); + NAND3_X1_LVT i_0_562 (.A1(op1[30]), .A2(n_0_571), .A3(n_0_547), .ZN(n_0_532)); + XNOR2_X1_LVT i_10_144 (.A(n_10_113), .B(n_10_114), .ZN(n_61)); + NAND2_X1_LVT i_0_558 (.A1(n_61), .A2(n_0_580), .ZN(n_0_528)); + OAI21_X1_LVT i_0_557 (.A(n_0_681), .B1(op2[29]), .B2(n_0_568), .ZN(n_0_527)); + NAND2_X1_LVT i_0_556 (.A1(op1[29]), .A2(n_0_566), .ZN(n_0_526)); + AOI22_X1_LVT i_0_555 (.A1(op1[29]), .A2(n_0_527), .B1(op2[29]), .B2(n_0_526), + .ZN(n_0_525)); + AOI21_X1_LVT i_0_554 (.A(n_0_525), .B1(n_0_710), .B2(n_0_565), .ZN(n_0_524)); + AOI211_X1_LVT i_0_553 (.A(n_0_543), .B(n_0_524), .C1(n_29), .C2(n_0_581), + .ZN(n_0_523)); + AND3_X1_LVT i_0_552 (.A1(n_0_532), .A2(n_0_528), .A3(n_0_523), .ZN(n_0_522)); + INV_X1_LVT i_0_652 (.A(n_0_621), .ZN(n_0_620)); + NAND2_X1_LVT i_0_565 (.A1(n_0_728), .A2(n_0_588), .ZN(n_0_535)); + AOI22_X1_LVT i_0_568 (.A1(n_0_723), .A2(n_0_600), .B1(op1[14]), .B2(n_0_618), + .ZN(n_0_538)); + AOI22_X1_LVT i_0_567 (.A1(n_0_693), .A2(n_0_595), .B1(op2[2]), .B2(n_0_538), + .ZN(n_0_537)); + INV_X1_LVT i_0_566 (.A(n_0_537), .ZN(n_0_536)); + OAI21_X1_LVT i_0_564 (.A(n_0_535), .B1(n_0_728), .B2(n_0_536), .ZN(n_0_534)); + OAI221_X1_LVT i_0_563 (.A(n_0_620), .B1(op2[0]), .B2(n_0_552), .C1(n_0_701), + .C2(n_0_534), .ZN(n_0_533)); + NAND2_X1_LVT i_0_561 (.A1(op2[1]), .A2(n_0_573), .ZN(n_0_531)); + INV_X1_LVT i_0_560 (.A(n_0_531), .ZN(n_0_530)); + AOI22_X1_LVT i_0_559 (.A1(op1[31]), .A2(n_0_530), .B1(op1[29]), .B2(n_0_571), + .ZN(n_0_529)); + OAI211_X1_LVT i_0_551 (.A(n_0_522), .B(n_0_533), .C1(n_0_562), .C2(n_0_529), + .ZN(result[29])); + INV_X1_LVT i_0_733 (.A(op2[28]), .ZN(n_0_700)); + AOI221_X1_LVT i_0_546 (.A(n_0_700), .B1(op1[28]), .B2(n_0_566), .C1(n_0_698), + .C2(n_0_565), .ZN(n_0_517)); + OAI21_X1_LVT i_0_543 (.A(n_0_681), .B1(op2[28]), .B2(n_0_568), .ZN(n_0_514)); + AOI22_X1_LVT i_0_542 (.A1(n_28), .A2(n_0_581), .B1(op1[28]), .B2(n_0_514), + .ZN(n_0_513)); + XNOR2_X1_LVT i_10_140 (.A(n_10_110), .B(n_10_111), .ZN(n_60)); + NAND2_X1_LVT i_0_544 (.A1(n_60), .A2(n_0_580), .ZN(n_0_515)); + NAND2_X1_LVT i_0_545 (.A1(op1[31]), .A2(n_0_574), .ZN(n_0_516)); + OAI211_X1_LVT i_0_541 (.A(n_0_513), .B(n_0_515), .C1(n_0_545), .C2(n_0_516), + .ZN(n_0_512)); + AOI22_X1_LVT i_0_540 (.A1(op1[30]), .A2(n_0_530), .B1(op1[28]), .B2(n_0_571), + .ZN(n_0_511)); + OAI22_X1_LVT i_0_539 (.A1(n_0_562), .A2(n_0_511), .B1(n_0_548), .B2(n_0_529), + .ZN(n_0_510)); + NOR3_X1_LVT i_0_538 (.A1(n_0_517), .A2(n_0_512), .A3(n_0_510), .ZN(n_0_509)); + OAI22_X1_LVT i_0_550 (.A1(n_0_714), .A2(n_0_617), .B1(op2[3]), .B2(n_0_608), + .ZN(n_0_521)); + OAI22_X1_LVT i_0_549 (.A1(op2[2]), .A2(n_0_602), .B1(n_0_693), .B2(n_0_521), + .ZN(n_0_520)); + AOI22_X1_LVT i_0_548 (.A1(op2[1]), .A2(n_0_520), .B1(n_0_728), .B2(n_0_553), + .ZN(n_0_519)); + OAI22_X1_LVT i_0_547 (.A1(op2[0]), .A2(n_0_534), .B1(n_0_701), .B2(n_0_519), + .ZN(n_0_518)); + OAI21_X1_LVT i_0_537 (.A(n_0_509), .B1(n_0_621), .B2(n_0_518), .ZN(result[28])); + XNOR2_X1_LVT i_10_136 (.A(n_10_107), .B(n_10_108), .ZN(n_59)); + AOI22_X1_LVT i_0_517 (.A1(n_27), .A2(n_0_581), .B1(n_59), .B2(n_0_580), + .ZN(n_0_489)); + INV_X1_LVT i_0_721 (.A(op1[27]), .ZN(n_0_688)); + OAI21_X1_LVT i_0_516 (.A(n_0_681), .B1(op2[27]), .B2(n_0_568), .ZN(n_0_488)); + INV_X1_LVT i_0_515 (.A(n_0_488), .ZN(n_0_487)); + OAI221_X1_LVT i_0_514 (.A(n_0_489), .B1(n_0_545), .B2(n_0_516), .C1(n_0_688), + .C2(n_0_487), .ZN(n_0_486)); + OAI21_X1_LVT i_0_530 (.A(op2[1]), .B1(n_0_710), .B2(n_0_574), .ZN(n_0_502)); + OAI21_X1_LVT i_0_529 (.A(n_0_728), .B1(n_0_688), .B2(n_0_574), .ZN(n_0_501)); + NAND2_X1_LVT i_0_528 (.A1(n_0_502), .A2(n_0_501), .ZN(n_0_500)); + AOI21_X1_LVT i_0_527 (.A(n_0_545), .B1(n_0_701), .B2(n_0_500), .ZN(n_0_499)); + NAND2_X1_LVT i_0_609 (.A1(n_0_682), .A2(n_0_578), .ZN(n_0_577)); + NOR2_X1_LVT i_0_526 (.A1(op2[4]), .A2(n_0_693), .ZN(n_0_498)); + NAND2_X1_LVT i_0_525 (.A1(n_0_723), .A2(n_0_498), .ZN(n_0_497)); + OAI22_X1_LVT i_0_523 (.A1(n_0_688), .A2(n_0_574), .B1(n_0_691), .B2(n_0_497), + .ZN(n_0_495)); + OAI21_X1_LVT i_0_522 (.A(n_0_502), .B1(op2[1]), .B2(n_0_495), .ZN(n_0_494)); + AOI21_X1_LVT i_0_521 (.A(n_0_577), .B1(n_0_701), .B2(n_0_494), .ZN(n_0_493)); + NOR2_X1_LVT i_0_520 (.A1(n_0_499), .A2(n_0_493), .ZN(n_0_492)); + AOI21_X1_LVT i_0_519 (.A(n_0_492), .B1(op2[0]), .B2(n_0_511), .ZN(n_0_491)); + AOI22_X1_LVT i_0_518 (.A1(n_0_688), .A2(n_0_565), .B1(op1[27]), .B2(n_0_566), + .ZN(n_0_490)); + AOI211_X1_LVT i_0_513 (.A(n_0_486), .B(n_0_491), .C1(op2[27]), .C2(n_0_490), + .ZN(n_0_485)); + NOR3_X1_LVT i_0_536 (.A1(op2[4]), .A2(n_0_696), .A3(n_0_723), .ZN(n_0_508)); + AOI21_X1_LVT i_0_535 (.A(n_0_508), .B1(n_0_723), .B2(n_0_591), .ZN(n_0_507)); + OAI22_X1_LVT i_0_534 (.A1(op2[2]), .A2(n_0_592), .B1(n_0_693), .B2(n_0_507), + .ZN(n_0_506)); + NOR2_X1_LVT i_0_533 (.A1(n_0_728), .A2(n_0_506), .ZN(n_0_505)); + AOI21_X1_LVT i_0_532 (.A(n_0_505), .B1(n_0_728), .B2(n_0_536), .ZN(n_0_504)); + OAI22_X1_LVT i_0_531 (.A1(n_0_701), .A2(n_0_504), .B1(op2[0]), .B2(n_0_519), + .ZN(n_0_503)); + OAI21_X1_LVT i_0_512 (.A(n_0_485), .B1(n_0_621), .B2(n_0_503), .ZN(result[27])); + OAI21_X1_LVT i_0_500 (.A(n_0_681), .B1(op2[26]), .B2(n_0_568), .ZN(n_0_473)); + NAND2_X1_LVT i_0_499 (.A1(op1[26]), .A2(n_0_473), .ZN(n_0_472)); + XNOR2_X1_LVT i_10_133 (.A(n_10_103), .B(n_10_106), .ZN(n_58)); + AOI22_X1_LVT i_0_498 (.A1(n_58), .A2(n_0_580), .B1(n_26), .B2(n_0_581), + .ZN(n_0_471)); + INV_X1_LVT i_0_744 (.A(op1[26]), .ZN(n_0_711)); + OAI221_X1_LVT i_0_501 (.A(op2[26]), .B1(op1[26]), .B2(n_0_564), .C1(n_0_711), + .C2(n_0_567), .ZN(n_0_474)); + NAND3_X1_LVT i_0_497 (.A1(n_0_472), .A2(n_0_471), .A3(n_0_474), .ZN(n_0_470)); + INV_X1_LVT i_0_524 (.A(n_0_497), .ZN(n_0_496)); + AOI22_X1_LVT i_0_505 (.A1(op1[30]), .A2(n_0_496), .B1(op1[26]), .B2(n_0_573), + .ZN(n_0_478)); + NOR2_X1_LVT i_0_504 (.A1(op2[1]), .A2(n_0_478), .ZN(n_0_477)); + AOI21_X1_LVT i_0_503 (.A(n_0_477), .B1(op1[28]), .B2(n_0_530), .ZN(n_0_476)); + NAND2_X1_LVT i_0_502 (.A1(n_0_701), .A2(n_0_476), .ZN(n_0_475)); + AOI21_X1_LVT i_0_489 (.A(n_0_577), .B1(op2[0]), .B2(n_0_494), .ZN(n_0_462)); + AOI21_X1_LVT i_0_488 (.A(n_0_470), .B1(n_0_475), .B2(n_0_462), .ZN(n_0_461)); + AOI21_X1_LVT i_0_511 (.A(n_0_616), .B1(n_0_738), .B2(n_0_706), .ZN(n_0_484)); + AOI21_X1_LVT i_0_510 (.A(n_0_484), .B1(n_0_723), .B2(op1[19]), .ZN(n_0_483)); + INV_X1_LVT i_0_757 (.A(op1[3]), .ZN(n_0_724)); + NOR2_X1_LVT i_0_687 (.A1(n_0_724), .A2(op2[3]), .ZN(n_0_654)); + INV_X1_LVT i_0_686 (.A(n_0_654), .ZN(n_0_653)); + AOI21_X1_LVT i_0_509 (.A(n_0_483), .B1(op2[4]), .B2(n_0_653), .ZN(n_0_482)); + AOI22_X1_LVT i_0_508 (.A1(n_0_693), .A2(n_0_554), .B1(op2[2]), .B2(n_0_482), + .ZN(n_0_481)); + OAI22_X1_LVT i_0_507 (.A1(n_0_728), .A2(n_0_481), .B1(op2[1]), .B2(n_0_520), + .ZN(n_0_480)); + AOI22_X1_LVT i_0_506 (.A1(op2[0]), .A2(n_0_480), .B1(n_0_701), .B2(n_0_504), + .ZN(n_0_479)); + NAND3_X1_LVT i_0_491 (.A1(op2[0]), .A2(n_0_516), .A3(n_0_500), .ZN(n_0_464)); + NAND2_X1_LVT i_0_494 (.A1(op1[31]), .A2(n_0_615), .ZN(n_0_467)); + OAI21_X1_LVT i_0_492 (.A(n_0_467), .B1(n_0_728), .B2(n_0_516), .ZN(n_0_465)); + OAI21_X1_LVT i_0_490 (.A(n_0_464), .B1(n_0_475), .B2(n_0_465), .ZN(n_0_463)); + OAI221_X1_LVT i_0_487 (.A(n_0_461), .B1(n_0_621), .B2(n_0_479), .C1(n_0_545), + .C2(n_0_463), .ZN(result[26])); + INV_X1_LVT i_10_126 (.A(n_10_100), .ZN(n_10_101)); + NOR2_X1_LVT i_10_127 (.A1(n_10_99), .A2(n_10_101), .ZN(n_10_102)); + XNOR2_X1_LVT i_10_128 (.A(n_10_97), .B(n_10_102), .ZN(n_57)); + AOI22_X1_LVT i_0_479 (.A1(n_57), .A2(n_0_580), .B1(n_25), .B2(n_0_581), + .ZN(n_0_453)); + INV_X1_LVT i_0_730 (.A(op2[25]), .ZN(n_0_697)); + AOI21_X1_LVT i_0_478 (.A(aluBypass), .B1(n_0_697), .B2(n_0_569), .ZN(n_0_452)); + AOI22_X1_LVT i_0_480 (.A1(op1[25]), .A2(n_0_567), .B1(n_0_699), .B2(n_0_564), + .ZN(n_0_454)); + OAI221_X1_LVT i_0_477 (.A(n_0_453), .B1(n_0_699), .B2(n_0_452), .C1(n_0_697), + .C2(n_0_454), .ZN(n_0_451)); + INV_X1_LVT i_0_575 (.A(n_0_545), .ZN(n_0_544)); + AOI21_X1_LVT i_0_476 (.A(n_0_451), .B1(n_0_544), .B2(n_0_465), .ZN(n_0_450)); + AOI22_X1_LVT i_0_475 (.A1(op1[29]), .A2(n_0_496), .B1(op1[25]), .B2(n_0_573), + .ZN(n_0_449)); + NAND2_X1_LVT i_0_474 (.A1(n_0_728), .A2(n_0_449), .ZN(n_0_448)); + OAI21_X1_LVT i_0_473 (.A(n_0_448), .B1(n_0_728), .B2(n_0_495), .ZN(n_0_447)); + OAI22_X1_LVT i_0_472 (.A1(n_0_548), .A2(n_0_476), .B1(n_0_562), .B2(n_0_447), + .ZN(n_0_446)); + INV_X1_LVT i_0_471 (.A(n_0_446), .ZN(n_0_445)); + OAI222_X1_LVT i_0_486 (.A1(n_0_733), .A2(n_0_617), .B1(n_0_694), .B2(n_0_605), + .C1(n_0_705), .C2(n_0_615), .ZN(n_0_460)); + NOR2_X1_LVT i_0_485 (.A1(n_0_693), .A2(n_0_460), .ZN(n_0_459)); + AOI21_X1_LVT i_0_484 (.A(n_0_459), .B1(n_0_693), .B2(n_0_538), .ZN(n_0_458)); + OAI22_X1_LVT i_0_483 (.A1(n_0_728), .A2(n_0_458), .B1(op2[1]), .B2(n_0_506), + .ZN(n_0_457)); + INV_X1_LVT i_0_482 (.A(n_0_457), .ZN(n_0_456)); + OAI221_X1_LVT i_0_481 (.A(n_0_620), .B1(n_0_701), .B2(n_0_456), .C1(op2[0]), + .C2(n_0_480), .ZN(n_0_455)); + NAND3_X1_LVT i_0_470 (.A1(n_0_450), .A2(n_0_445), .A3(n_0_455), .ZN( + result[25])); + INV_X1_LVT i_0_493 (.A(n_0_467), .ZN(n_0_466)); + OAI211_X1_LVT i_0_455 (.A(n_0_544), .B(n_0_465), .C1(op2[0]), .C2(n_0_466), + .ZN(n_0_430)); + OAI21_X1_LVT i_0_462 (.A(n_0_681), .B1(op2[24]), .B2(n_0_568), .ZN(n_0_437)); + XNOR2_X1_LVT i_10_120 (.A(n_10_94), .B(n_10_95), .ZN(n_56)); + AOI222_X1_LVT i_0_461 (.A1(op1[24]), .A2(n_0_437), .B1(n_56), .B2(n_0_580), + .C1(n_24), .C2(n_0_581), .ZN(n_0_436)); + INV_X1_LVT i_0_460 (.A(n_0_436), .ZN(n_0_435)); + AOI22_X1_LVT i_0_458 (.A1(op1[24]), .A2(n_0_573), .B1(op1[28]), .B2(n_0_496), + .ZN(n_0_433)); + OAI22_X1_LVT i_0_457 (.A1(op2[1]), .A2(n_0_433), .B1(n_0_728), .B2(n_0_478), + .ZN(n_0_432)); + INV_X1_LVT i_0_456 (.A(n_0_432), .ZN(n_0_431)); + OAI22_X1_LVT i_0_454 (.A1(n_0_562), .A2(n_0_431), .B1(n_0_548), .B2(n_0_447), + .ZN(n_0_429)); + AOI22_X1_LVT i_0_459 (.A1(n_0_736), .A2(n_0_565), .B1(op1[24]), .B2(n_0_566), + .ZN(n_0_434)); + AOI211_X1_LVT i_0_453 (.A(n_0_435), .B(n_0_429), .C1(op2[24]), .C2(n_0_434), + .ZN(n_0_428)); + NAND2_X1_LVT i_0_467 (.A1(n_0_693), .A2(n_0_521), .ZN(n_0_442)); + NOR2_X1_LVT i_0_469 (.A1(op2[3]), .A2(n_0_603), .ZN(n_0_444)); + AOI21_X1_LVT i_0_468 (.A(n_0_444), .B1(op1[9]), .B2(n_0_618), .ZN(n_0_443)); + OAI21_X1_LVT i_0_466 (.A(n_0_442), .B1(n_0_693), .B2(n_0_443), .ZN(n_0_441)); + NAND2_X1_LVT i_0_465 (.A1(op2[1]), .A2(n_0_441), .ZN(n_0_440)); + OAI21_X1_LVT i_0_464 (.A(n_0_440), .B1(op2[1]), .B2(n_0_481), .ZN(n_0_439)); + OAI221_X1_LVT i_0_463 (.A(n_0_620), .B1(op2[0]), .B2(n_0_456), .C1(n_0_701), + .C2(n_0_439), .ZN(n_0_438)); + NAND3_X1_LVT i_0_452 (.A1(n_0_430), .A2(n_0_428), .A3(n_0_438), .ZN( + result[24])); + INV_X1_LVT i_0_751 (.A(op2[23]), .ZN(n_0_718)); + AOI221_X1_LVT i_0_440 (.A(n_0_718), .B1(op1[23]), .B2(n_0_566), .C1(n_0_719), + .C2(n_0_565), .ZN(n_0_416)); + INV_X1_LVT i_10_115 (.A(n_10_91), .ZN(n_10_92)); + NOR2_X1_LVT i_10_116 (.A1(n_10_90), .A2(n_10_92), .ZN(n_10_93)); + XNOR2_X1_LVT i_10_117 (.A(n_10_88), .B(n_10_93), .ZN(n_55)); + AOI222_X1_LVT i_0_438 (.A1(n_23), .A2(n_0_581), .B1(n_0_544), .B2(n_0_466), + .C1(n_55), .C2(n_0_580), .ZN(n_0_414)); + OAI21_X1_LVT i_0_437 (.A(n_0_414), .B1(n_0_548), .B2(n_0_431), .ZN(n_0_413)); + OAI21_X1_LVT i_0_439 (.A(n_0_681), .B1(op2[23]), .B2(n_0_568), .ZN(n_0_415)); + AOI211_X1_LVT i_0_436 (.A(n_0_416), .B(n_0_413), .C1(op1[23]), .C2(n_0_415), + .ZN(n_0_412)); + AOI22_X1_LVT i_0_444 (.A1(n_0_723), .A2(n_0_719), .B1(op2[3]), .B2(n_0_691), + .ZN(n_0_420)); + AOI22_X1_LVT i_0_443 (.A1(n_0_575), .A2(n_0_420), .B1(op1[27]), .B2(n_0_496), + .ZN(n_0_419)); + AOI22_X1_LVT i_0_442 (.A1(op2[1]), .A2(n_0_449), .B1(n_0_728), .B2(n_0_419), + .ZN(n_0_418)); + INV_X1_LVT i_0_441 (.A(n_0_418), .ZN(n_0_417)); + NAND2_X1_LVT i_0_447 (.A1(n_0_728), .A2(n_0_458), .ZN(n_0_423)); + NOR2_X1_LVT i_0_451 (.A1(op2[3]), .A2(n_0_594), .ZN(n_0_427)); + AOI21_X1_LVT i_0_450 (.A(n_0_427), .B1(op1[8]), .B2(n_0_618), .ZN(n_0_426)); + OAI22_X1_LVT i_0_449 (.A1(n_0_693), .A2(n_0_426), .B1(op2[2]), .B2(n_0_507), + .ZN(n_0_425)); + INV_X1_LVT i_0_448 (.A(n_0_425), .ZN(n_0_424)); + OAI21_X1_LVT i_0_446 (.A(n_0_423), .B1(n_0_728), .B2(n_0_424), .ZN(n_0_422)); + AOI22_X1_LVT i_0_445 (.A1(op2[0]), .A2(n_0_422), .B1(n_0_701), .B2(n_0_439), + .ZN(n_0_421)); + OAI221_X1_LVT i_0_435 (.A(n_0_412), .B1(n_0_562), .B2(n_0_417), .C1(n_0_621), + .C2(n_0_421), .ZN(result[23])); + XNOR2_X1_LVT i_10_109 (.A(n_10_85), .B(n_10_86), .ZN(n_54)); + AOI22_X1_LVT i_0_419 (.A1(n_54), .A2(n_0_580), .B1(n_22), .B2(n_0_581), + .ZN(n_0_396)); + INV_X1_LVT i_0_719 (.A(op2[22]), .ZN(n_0_686)); + AOI21_X1_LVT i_0_420 (.A(aluBypass), .B1(n_0_686), .B2(n_0_569), .ZN(n_0_397)); + OAI21_X1_LVT i_0_418 (.A(n_0_396), .B1(n_0_687), .B2(n_0_397), .ZN(n_0_395)); + AOI22_X1_LVT i_0_421 (.A1(op1[22]), .A2(n_0_566), .B1(n_0_687), .B2(n_0_565), + .ZN(n_0_398)); + AOI21_X1_LVT i_0_417 (.A(n_0_395), .B1(op2[22]), .B2(n_0_398), .ZN(n_0_394)); + NAND2_X1_LVT i_0_432 (.A1(n_0_728), .A2(n_0_441), .ZN(n_0_409)); + AND2_X1_LVT i_0_434 (.A1(n_0_738), .A2(n_0_619), .ZN(n_0_411)); + AOI22_X1_LVT i_0_433 (.A1(n_0_693), .A2(n_0_482), .B1(op2[2]), .B2(n_0_411), + .ZN(n_0_410)); + OAI21_X1_LVT i_0_431 (.A(n_0_409), .B1(n_0_728), .B2(n_0_410), .ZN(n_0_408)); + OAI22_X1_LVT i_0_430 (.A1(n_0_701), .A2(n_0_408), .B1(op2[0]), .B2(n_0_422), + .ZN(n_0_407)); + AOI22_X1_LVT i_0_429 (.A1(n_0_723), .A2(n_0_687), .B1(op2[3]), .B2(n_0_717), + .ZN(n_0_406)); + AOI22_X1_LVT i_0_428 (.A1(n_0_575), .A2(n_0_406), .B1(op1[26]), .B2(n_0_496), + .ZN(n_0_405)); + AND2_X1_LVT i_0_427 (.A1(n_0_728), .A2(n_0_405), .ZN(n_0_404)); + AOI21_X1_LVT i_0_426 (.A(n_0_404), .B1(op2[1]), .B2(n_0_433), .ZN(n_0_403)); + INV_X1_LVT i_0_425 (.A(n_0_403), .ZN(n_0_402)); + OAI222_X1_LVT i_0_424 (.A1(n_0_545), .A2(n_0_467), .B1(n_0_701), .B2(n_0_417), + .C1(op2[0]), .C2(n_0_402), .ZN(n_0_401)); + NOR2_X1_LVT i_0_496 (.A1(n_0_738), .A2(n_0_691), .ZN(n_0_469)); + INV_X1_LVT i_0_495 (.A(n_0_469), .ZN(n_0_468)); + NAND3_X1_LVT i_0_423 (.A1(n_0_693), .A2(n_0_468), .A3(n_0_404), .ZN(n_0_400)); + OAI21_X1_LVT i_0_422 (.A(n_0_401), .B1(op2[0]), .B2(n_0_400), .ZN(n_0_399)); + OAI221_X1_LVT i_0_416 (.A(n_0_394), .B1(n_0_621), .B2(n_0_407), .C1(n_0_579), + .C2(n_0_399), .ZN(result[22])); + INV_X1_LVT i_0_759 (.A(op1[21]), .ZN(n_0_726)); + AOI22_X1_LVT i_0_399 (.A1(op1[21]), .A2(n_0_566), .B1(n_0_726), .B2(n_0_565), + .ZN(n_0_377)); + NOR2_X1_LVT i_0_692 (.A1(n_0_726), .A2(op2[21]), .ZN(n_0_659)); + AOI222_X1_LVT i_0_398 (.A1(op2[21]), .A2(n_0_377), .B1(n_21), .B2(n_0_581), + .C1(n_0_659), .C2(n_0_569), .ZN(n_0_376)); + INV_X1_LVT i_0_397 (.A(n_0_376), .ZN(n_0_375)); + INV_X1_LVT i_10_104 (.A(n_10_82), .ZN(n_10_83)); + NOR2_X1_LVT i_10_105 (.A1(n_10_81), .A2(n_10_83), .ZN(n_10_84)); + XNOR2_X1_LVT i_10_106 (.A(n_10_79), .B(n_10_84), .ZN(n_53)); + AOI221_X1_LVT i_0_396 (.A(n_0_375), .B1(n_53), .B2(n_0_580), .C1(op1[21]), + .C2(aluBypass), .ZN(n_0_374)); + INV_X1_LVT i_0_608 (.A(n_0_577), .ZN(n_0_576)); + NAND2_X1_LVT i_0_403 (.A1(op2[0]), .A2(n_0_402), .ZN(n_0_381)); + AND2_X1_LVT i_0_410 (.A1(op2[1]), .A2(n_0_419), .ZN(n_0_388)); + OAI22_X1_LVT i_0_408 (.A1(n_0_723), .A2(n_0_710), .B1(n_0_726), .B2(op2[3]), + .ZN(n_0_386)); + AOI22_X1_LVT i_0_407 (.A1(n_0_575), .A2(n_0_386), .B1(op1[25]), .B2(n_0_496), + .ZN(n_0_385)); + AOI21_X1_LVT i_0_395 (.A(n_0_388), .B1(n_0_728), .B2(n_0_385), .ZN(n_0_373)); + OAI211_X1_LVT i_0_394 (.A(n_0_576), .B(n_0_381), .C1(op2[0]), .C2(n_0_373), + .ZN(n_0_372)); + AOI21_X1_LVT i_0_402 (.A(n_0_381), .B1(n_0_466), .B2(n_0_400), .ZN(n_0_380)); + INV_X1_LVT i_0_401 (.A(n_0_380), .ZN(n_0_379)); + NOR2_X1_LVT i_0_409 (.A1(n_0_575), .A2(n_0_467), .ZN(n_0_387)); + INV_X1_LVT i_0_406 (.A(n_0_385), .ZN(n_0_384)); + NOR2_X1_LVT i_0_405 (.A1(n_0_387), .A2(n_0_384), .ZN(n_0_383)); + AOI22_X1_LVT i_0_404 (.A1(n_0_467), .A2(n_0_388), .B1(n_0_728), .B2(n_0_383), + .ZN(n_0_382)); + OAI211_X1_LVT i_0_400 (.A(n_0_544), .B(n_0_379), .C1(op2[0]), .C2(n_0_382), + .ZN(n_0_378)); + AOI22_X1_LVT i_0_415 (.A1(op1[14]), .A2(n_0_616), .B1(op1[6]), .B2(n_0_618), + .ZN(n_0_393)); + NOR2_X1_LVT i_0_414 (.A1(n_0_693), .A2(n_0_393), .ZN(n_0_392)); + AOI21_X1_LVT i_0_413 (.A(n_0_392), .B1(n_0_693), .B2(n_0_460), .ZN(n_0_391)); + OAI22_X1_LVT i_0_412 (.A1(n_0_728), .A2(n_0_391), .B1(op2[1]), .B2(n_0_424), + .ZN(n_0_390)); + OAI221_X1_LVT i_0_411 (.A(n_0_620), .B1(op2[0]), .B2(n_0_408), .C1(n_0_701), + .C2(n_0_390), .ZN(n_0_389)); + NAND4_X1_LVT i_0_393 (.A1(n_0_374), .A2(n_0_372), .A3(n_0_378), .A4(n_0_389), + .ZN(result[21])); + OAI221_X1_LVT i_0_388 (.A(op2[20]), .B1(n_0_727), .B2(n_0_567), .C1(op1[20]), + .C2(n_0_564), .ZN(n_0_367)); + NOR2_X1_LVT i_0_691 (.A1(n_0_727), .A2(op2[20]), .ZN(n_0_658)); + AOI22_X1_LVT i_0_387 (.A1(op1[20]), .A2(aluBypass), .B1(n_0_658), .B2(n_0_569), + .ZN(n_0_366)); + XNOR2_X1_LVT i_10_98 (.A(n_10_76), .B(n_10_77), .ZN(n_52)); + AOI22_X1_LVT i_0_386 (.A1(n_52), .A2(n_0_580), .B1(n_20), .B2(n_0_581), + .ZN(n_0_365)); + AOI221_X1_LVT i_0_392 (.A(op2[4]), .B1(n_0_727), .B2(n_0_723), .C1(op2[3]), + .C2(n_0_698), .ZN(n_0_371)); + AOI22_X1_LVT i_0_391 (.A1(op1[24]), .A2(n_0_496), .B1(n_0_693), .B2(n_0_371), + .ZN(n_0_370)); + OAI22_X1_LVT i_0_390 (.A1(op2[1]), .A2(n_0_370), .B1(n_0_728), .B2(n_0_405), + .ZN(n_0_369)); + OAI221_X1_LVT i_0_385 (.A(n_0_576), .B1(n_0_701), .B2(n_0_373), .C1(op2[0]), + .C2(n_0_369), .ZN(n_0_364)); + AND4_X1_LVT i_0_384 (.A1(n_0_367), .A2(n_0_366), .A3(n_0_365), .A4(n_0_364), + .ZN(n_0_363)); + AOI22_X1_LVT i_0_383 (.A1(op1[13]), .A2(n_0_616), .B1(op1[5]), .B2(n_0_618), + .ZN(n_0_362)); + AOI22_X1_LVT i_0_382 (.A1(op2[2]), .A2(n_0_362), .B1(n_0_693), .B2(n_0_443), + .ZN(n_0_361)); + NAND2_X1_LVT i_0_381 (.A1(op2[1]), .A2(n_0_361), .ZN(n_0_360)); + OAI21_X1_LVT i_0_380 (.A(n_0_360), .B1(op2[1]), .B2(n_0_410), .ZN(n_0_359)); + OAI221_X1_LVT i_0_379 (.A(n_0_620), .B1(n_0_701), .B2(n_0_359), .C1(op2[0]), + .C2(n_0_390), .ZN(n_0_358)); + OR2_X1_LVT i_0_389 (.A1(n_0_387), .A2(n_0_369), .ZN(n_0_368)); + AOI22_X1_LVT i_0_378 (.A1(op2[0]), .A2(n_0_382), .B1(n_0_701), .B2(n_0_368), + .ZN(n_0_357)); + OAI211_X1_LVT i_0_377 (.A(n_0_363), .B(n_0_358), .C1(n_0_545), .C2(n_0_357), + .ZN(result[20])); + OAI22_X1_LVT i_0_370 (.A1(op2[3]), .A2(n_0_689), .B1(n_0_723), .B2(n_0_688), + .ZN(n_0_350)); + AND2_X1_LVT i_0_369 (.A1(n_0_738), .A2(n_0_350), .ZN(n_0_349)); + AOI22_X1_LVT i_0_368 (.A1(n_0_498), .A2(n_0_420), .B1(n_0_693), .B2(n_0_349), + .ZN(n_0_348)); + AND2_X1_LVT i_0_367 (.A1(n_0_728), .A2(n_0_348), .ZN(n_0_347)); + AOI21_X1_LVT i_0_359 (.A(n_0_347), .B1(op2[1]), .B2(n_0_385), .ZN(n_0_339)); + OAI221_X1_LVT i_0_357 (.A(n_0_576), .B1(n_0_701), .B2(n_0_369), .C1(op2[0]), + .C2(n_0_339), .ZN(n_0_337)); + NAND2_X1_LVT i_0_363 (.A1(n_19), .A2(n_0_581), .ZN(n_0_343)); + INV_X1_LVT i_0_723 (.A(op2[19]), .ZN(n_0_690)); + AOI221_X1_LVT i_0_364 (.A(n_0_690), .B1(n_0_689), .B2(n_0_565), .C1(op1[19]), + .C2(n_0_566), .ZN(n_0_344)); + XNOR2_X1_LVT i_10_94 (.A(n_10_73), .B(n_10_74), .ZN(n_51)); + AOI221_X1_LVT i_0_361 (.A(n_0_344), .B1(op1[19]), .B2(aluBypass), .C1(n_51), + .C2(n_0_580), .ZN(n_0_341)); + NAND3_X1_LVT i_0_362 (.A1(n_0_690), .A2(op1[19]), .A3(n_0_569), .ZN(n_0_342)); + NAND3_X1_LVT i_0_360 (.A1(n_0_343), .A2(n_0_341), .A3(n_0_342), .ZN(n_0_340)); + AOI22_X1_LVT i_0_376 (.A1(op1[12]), .A2(n_0_616), .B1(op1[4]), .B2(n_0_618), + .ZN(n_0_356)); + OAI22_X1_LVT i_0_375 (.A1(n_0_693), .A2(n_0_356), .B1(op2[2]), .B2(n_0_426), + .ZN(n_0_355)); + INV_X1_LVT i_0_374 (.A(n_0_355), .ZN(n_0_354)); + OAI22_X1_LVT i_0_373 (.A1(op2[1]), .A2(n_0_391), .B1(n_0_728), .B2(n_0_354), + .ZN(n_0_353)); + AOI22_X1_LVT i_0_372 (.A1(n_0_701), .A2(n_0_359), .B1(op2[0]), .B2(n_0_353), + .ZN(n_0_352)); + INV_X1_LVT i_0_371 (.A(n_0_352), .ZN(n_0_351)); + AOI21_X1_LVT i_0_358 (.A(n_0_340), .B1(n_0_620), .B2(n_0_351), .ZN(n_0_338)); + AOI22_X1_LVT i_0_366 (.A1(n_0_468), .A2(n_0_347), .B1(op2[1]), .B2(n_0_383), + .ZN(n_0_346)); + AOI22_X1_LVT i_0_365 (.A1(n_0_701), .A2(n_0_346), .B1(op2[0]), .B2(n_0_368), + .ZN(n_0_345)); + OAI211_X1_LVT i_0_356 (.A(n_0_337), .B(n_0_338), .C1(n_0_545), .C2(n_0_345), + .ZN(result[19])); + XNOR2_X1_LVT i_10_90 (.A(n_10_70), .B(n_10_71), .ZN(n_50)); + NAND2_X1_LVT i_0_342 (.A1(n_50), .A2(n_0_580), .ZN(n_0_323)); + OAI21_X1_LVT i_0_343 (.A(n_0_681), .B1(op2[18]), .B2(n_0_568), .ZN(n_0_324)); + AOI22_X1_LVT i_0_341 (.A1(op1[18]), .A2(n_0_324), .B1(n_18), .B2(n_0_581), + .ZN(n_0_322)); + OAI221_X1_LVT i_0_340 (.A(op2[18]), .B1(n_0_705), .B2(n_0_567), .C1(op1[18]), + .C2(n_0_564), .ZN(n_0_321)); + NAND3_X1_LVT i_0_339 (.A1(n_0_323), .A2(n_0_322), .A3(n_0_321), .ZN(n_0_320)); + OAI22_X1_LVT i_0_351 (.A1(op2[3]), .A2(n_0_705), .B1(n_0_723), .B2(n_0_711), + .ZN(n_0_332)); + AND2_X1_LVT i_0_350 (.A1(n_0_738), .A2(n_0_332), .ZN(n_0_331)); + AOI22_X1_LVT i_0_349 (.A1(n_0_498), .A2(n_0_406), .B1(n_0_693), .B2(n_0_331), + .ZN(n_0_330)); + NAND2_X1_LVT i_0_348 (.A1(n_0_728), .A2(n_0_330), .ZN(n_0_329)); + NAND2_X1_LVT i_0_347 (.A1(op2[1]), .A2(n_0_370), .ZN(n_0_328)); + AND2_X1_LVT i_0_338 (.A1(n_0_329), .A2(n_0_328), .ZN(n_0_319)); + OAI22_X1_LVT i_0_337 (.A1(op2[0]), .A2(n_0_319), .B1(n_0_701), .B2(n_0_339), + .ZN(n_0_318)); + INV_X1_LVT i_0_336 (.A(n_0_318), .ZN(n_0_317)); + AOI21_X1_LVT i_0_335 (.A(n_0_320), .B1(n_0_578), .B2(n_0_317), .ZN(n_0_316)); + OAI22_X1_LVT i_0_346 (.A1(n_0_469), .A2(n_0_329), .B1(n_0_387), .B2(n_0_328), + .ZN(n_0_327)); + NAND2_X1_LVT i_0_344 (.A1(n_0_544), .A2(n_0_346), .ZN(n_0_325)); + NAND2_X1_LVT i_0_354 (.A1(n_0_728), .A2(n_0_361), .ZN(n_0_335)); + AOI22_X1_LVT i_0_355 (.A1(n_0_612), .A2(n_0_498), .B1(n_0_693), .B2(n_0_411), + .ZN(n_0_336)); + OAI21_X1_LVT i_0_353 (.A(n_0_335), .B1(n_0_728), .B2(n_0_336), .ZN(n_0_334)); + AOI22_X1_LVT i_0_352 (.A1(n_0_701), .A2(n_0_353), .B1(op2[0]), .B2(n_0_334), + .ZN(n_0_333)); + OAI221_X1_LVT i_0_334 (.A(n_0_316), .B1(n_0_327), .B2(n_0_325), .C1(n_0_621), + .C2(n_0_333), .ZN(result[18])); + NAND2_X1_LVT i_0_325 (.A1(n_17), .A2(n_0_581), .ZN(n_0_307)); + INV_X1_LVT i_0_765 (.A(op1[17]), .ZN(n_0_732)); + AOI22_X1_LVT i_0_324 (.A1(n_0_732), .A2(n_0_565), .B1(op1[17]), .B2(n_0_566), + .ZN(n_0_306)); + NOR2_X1_LVT i_0_693 (.A1(n_0_732), .A2(op2[17]), .ZN(n_0_660)); + XNOR2_X1_LVT i_10_86 (.A(n_10_67), .B(n_10_68), .ZN(n_49)); + AOI222_X1_LVT i_0_323 (.A1(op2[17]), .A2(n_0_306), .B1(n_0_660), .B2(n_0_569), + .C1(n_49), .C2(n_0_580), .ZN(n_0_305)); + OAI211_X1_LVT i_0_322 (.A(n_0_307), .B(n_0_305), .C1(n_0_732), .C2(n_0_681), + .ZN(n_0_304)); + AOI22_X1_LVT i_0_331 (.A1(op2[3]), .A2(op1[25]), .B1(op1[17]), .B2(n_0_723), + .ZN(n_0_313)); + NOR2_X1_LVT i_0_330 (.A1(op2[4]), .A2(n_0_313), .ZN(n_0_312)); + AOI22_X1_LVT i_0_329 (.A1(n_0_498), .A2(n_0_386), .B1(n_0_693), .B2(n_0_312), + .ZN(n_0_311)); + OAI22_X1_LVT i_0_328 (.A1(op2[1]), .A2(n_0_311), .B1(n_0_728), .B2(n_0_348), + .ZN(n_0_310)); + OR2_X1_LVT i_0_327 (.A1(op2[0]), .A2(n_0_310), .ZN(n_0_309)); + OAI21_X1_LVT i_0_321 (.A(n_0_576), .B1(n_0_701), .B2(n_0_319), .ZN(n_0_303)); + INV_X1_LVT i_0_320 (.A(n_0_303), .ZN(n_0_302)); + AOI21_X1_LVT i_0_319 (.A(n_0_304), .B1(n_0_309), .B2(n_0_302), .ZN(n_0_301)); + INV_X1_LVT i_0_345 (.A(n_0_327), .ZN(n_0_326)); + OAI22_X1_LVT i_0_326 (.A1(n_0_701), .A2(n_0_326), .B1(n_0_469), .B2(n_0_309), + .ZN(n_0_308)); + NOR2_X1_LVT i_0_318 (.A1(op2[2]), .A2(n_0_393), .ZN(n_0_300)); + AOI21_X1_LVT i_0_317 (.A(n_0_300), .B1(n_0_597), .B2(n_0_498), .ZN(n_0_299)); + OAI22_X1_LVT i_0_316 (.A1(n_0_728), .A2(n_0_299), .B1(op2[1]), .B2(n_0_354), + .ZN(n_0_298)); + OAI22_X1_LVT i_0_315 (.A1(op2[0]), .A2(n_0_334), .B1(n_0_701), .B2(n_0_298), + .ZN(n_0_297)); + OAI221_X1_LVT i_0_314 (.A(n_0_301), .B1(n_0_545), .B2(n_0_308), .C1(n_0_621), + .C2(n_0_297), .ZN(result[17])); + XNOR2_X1_LVT i_10_82 (.A(n_10_64), .B(n_10_65), .ZN(n_48)); + AOI22_X1_LVT i_0_301 (.A1(n_48), .A2(n_0_580), .B1(n_16), .B2(n_0_581), + .ZN(n_0_284)); + NAND2_X1_LVT i_0_333 (.A1(n_0_544), .A2(n_0_469), .ZN(n_0_315)); + INV_X1_LVT i_0_332 (.A(n_0_315), .ZN(n_0_314)); + OAI21_X1_LVT i_0_302 (.A(n_0_681), .B1(op2[16]), .B2(n_0_568), .ZN(n_0_285)); + AOI21_X1_LVT i_0_300 (.A(n_0_314), .B1(op1[16]), .B2(n_0_285), .ZN(n_0_283)); + INV_X1_LVT i_0_772 (.A(op1[16]), .ZN(n_0_739)); + OAI221_X1_LVT i_0_303 (.A(op2[16]), .B1(op1[16]), .B2(n_0_564), .C1(n_0_739), + .C2(n_0_567), .ZN(n_0_286)); + NAND3_X1_LVT i_0_299 (.A1(n_0_284), .A2(n_0_283), .A3(n_0_286), .ZN(n_0_282)); + INV_X1_LVT i_0_593 (.A(n_0_562), .ZN(n_0_561)); + OAI22_X1_LVT i_0_307 (.A1(op1[16]), .A2(op2[3]), .B1(op1[24]), .B2(n_0_723), + .ZN(n_0_290)); + NOR2_X1_LVT i_0_306 (.A1(op2[4]), .A2(n_0_290), .ZN(n_0_289)); + AOI22_X1_LVT i_0_305 (.A1(n_0_693), .A2(n_0_289), .B1(op2[2]), .B2(n_0_371), + .ZN(n_0_288)); + OAI22_X1_LVT i_0_304 (.A1(n_0_728), .A2(n_0_330), .B1(op2[1]), .B2(n_0_288), + .ZN(n_0_287)); + AOI221_X1_LVT i_0_298 (.A(n_0_282), .B1(n_0_547), .B2(n_0_310), .C1(n_0_561), + .C2(n_0_287), .ZN(n_0_281)); + INV_X1_LVT i_0_762 (.A(op1[1]), .ZN(n_0_729)); + OAI22_X1_LVT i_0_313 (.A1(n_0_722), .A2(n_0_615), .B1(n_0_729), .B2(n_0_617), + .ZN(n_0_296)); + NAND2_X1_LVT i_0_312 (.A1(op2[2]), .A2(n_0_296), .ZN(n_0_295)); + OAI21_X1_LVT i_0_311 (.A(n_0_295), .B1(op2[2]), .B2(n_0_362), .ZN(n_0_294)); + NAND2_X1_LVT i_0_310 (.A1(op2[1]), .A2(n_0_294), .ZN(n_0_293)); + OAI21_X1_LVT i_0_309 (.A(n_0_293), .B1(op2[1]), .B2(n_0_336), .ZN(n_0_292)); + OAI22_X1_LVT i_0_308 (.A1(op2[0]), .A2(n_0_298), .B1(n_0_701), .B2(n_0_292), + .ZN(n_0_291)); + OAI21_X1_LVT i_0_297 (.A(n_0_281), .B1(n_0_621), .B2(n_0_291), .ZN(result[16])); + OAI221_X1_LVT i_0_286 (.A(op2[15]), .B1(n_0_734), .B2(n_0_567), .C1(op1[15]), + .C2(n_0_564), .ZN(n_0_270)); + AOI21_X1_LVT i_0_288 (.A(n_0_314), .B1(n_15), .B2(n_0_581), .ZN(n_0_272)); + INV_X1_LVT i_0_287 (.A(n_0_272), .ZN(n_0_271)); + XNOR2_X1_LVT i_10_78 (.A(n_10_61), .B(n_10_62), .ZN(n_47)); + OAI21_X1_LVT i_0_285 (.A(n_0_681), .B1(op2[15]), .B2(n_0_568), .ZN(n_0_269)); + AOI221_X1_LVT i_0_284 (.A(n_0_271), .B1(n_47), .B2(n_0_580), .C1(op1[15]), + .C2(n_0_269), .ZN(n_0_268)); + AOI22_X1_LVT i_0_296 (.A1(op1[8]), .A2(n_0_616), .B1(op1[0]), .B2(n_0_618), + .ZN(n_0_280)); + AOI22_X1_LVT i_0_295 (.A1(op2[2]), .A2(n_0_280), .B1(n_0_693), .B2(n_0_356), + .ZN(n_0_279)); + NAND2_X1_LVT i_0_294 (.A1(op2[1]), .A2(n_0_279), .ZN(n_0_278)); + OAI21_X1_LVT i_0_293 (.A(n_0_278), .B1(op2[1]), .B2(n_0_299), .ZN(n_0_277)); + OAI221_X1_LVT i_0_292 (.A(n_0_620), .B1(n_0_701), .B2(n_0_277), .C1(op2[0]), + .C2(n_0_292), .ZN(n_0_276)); + OAI222_X1_LVT i_0_291 (.A1(n_0_719), .A2(n_0_617), .B1(n_0_691), .B2(n_0_605), + .C1(n_0_734), .C2(n_0_615), .ZN(n_0_275)); + OAI22_X1_LVT i_0_290 (.A1(n_0_693), .A2(n_0_349), .B1(op2[2]), .B2(n_0_275), + .ZN(n_0_274)); + OAI22_X1_LVT i_0_289 (.A1(op2[1]), .A2(n_0_274), .B1(n_0_728), .B2(n_0_311), + .ZN(n_0_273)); + AOI22_X1_LVT i_0_283 (.A1(n_0_561), .A2(n_0_273), .B1(n_0_547), .B2(n_0_287), + .ZN(n_0_267)); + NAND4_X1_LVT i_0_282 (.A1(n_0_270), .A2(n_0_268), .A3(n_0_276), .A4(n_0_267), + .ZN(result[15])); + NOR2_X1_LVT i_0_278 (.A1(op2[0]), .A2(n_0_277), .ZN(n_0_263)); + NAND2_X1_LVT i_0_281 (.A1(n_0_612), .A2(n_0_575), .ZN(n_0_266)); + OAI21_X1_LVT i_0_280 (.A(n_0_266), .B1(n_0_713), .B2(n_0_497), .ZN(n_0_265)); + AOI22_X1_LVT i_0_279 (.A1(op2[1]), .A2(n_0_265), .B1(n_0_728), .B2(n_0_294), + .ZN(n_0_264)); + AOI211_X1_LVT i_0_277 (.A(n_0_263), .B(n_0_621), .C1(op2[0]), .C2(n_0_264), + .ZN(n_0_262)); + INV_X1_LVT i_0_754 (.A(op1[14]), .ZN(n_0_721)); + OAI21_X1_LVT i_0_273 (.A(op2[14]), .B1(n_0_721), .B2(n_0_567), .ZN(n_0_258)); + AOI21_X1_LVT i_0_272 (.A(n_0_258), .B1(n_0_721), .B2(n_0_565), .ZN(n_0_257)); + XNOR2_X1_LVT i_10_74 (.A(n_10_58), .B(n_10_59), .ZN(n_46)); + OAI21_X1_LVT i_0_276 (.A(n_0_681), .B1(op2[14]), .B2(n_0_568), .ZN(n_0_261)); + AOI222_X1_LVT i_0_275 (.A1(n_14), .A2(n_0_581), .B1(n_46), .B2(n_0_580), + .C1(op1[14]), .C2(n_0_261), .ZN(n_0_260)); + INV_X1_LVT i_0_274 (.A(n_0_260), .ZN(n_0_259)); + OAI222_X1_LVT i_0_271 (.A1(n_0_717), .A2(n_0_605), .B1(n_0_687), .B2(n_0_617), + .C1(n_0_721), .C2(n_0_615), .ZN(n_0_256)); + OAI22_X1_LVT i_0_270 (.A1(n_0_693), .A2(n_0_331), .B1(op2[2]), .B2(n_0_256), + .ZN(n_0_255)); + AND2_X1_LVT i_0_269 (.A1(n_0_728), .A2(n_0_255), .ZN(n_0_254)); + NOR3_X1_LVT i_0_265 (.A1(op2[3]), .A2(op2[2]), .A3(op2[0]), .ZN(n_0_250)); + AOI21_X1_LVT i_0_268 (.A(n_0_254), .B1(op2[1]), .B2(n_0_288), .ZN(n_0_253)); + OAI22_X1_LVT i_0_266 (.A1(op2[0]), .A2(n_0_253), .B1(n_0_701), .B2(n_0_273), + .ZN(n_0_251)); + AOI221_X1_LVT i_0_259 (.A(n_0_579), .B1(n_0_254), .B2(n_0_250), .C1(n_0_315), + .C2(n_0_251), .ZN(n_0_244)); + OR4_X1_LVT i_0_258 (.A1(n_0_262), .A2(n_0_257), .A3(n_0_259), .A4(n_0_244), + .ZN(result[14])); + OAI221_X1_LVT i_0_245 (.A(op2[13]), .B1(op1[13]), .B2(n_0_564), .C1(n_0_714), + .C2(n_0_567), .ZN(n_0_231)); + NAND2_X1_LVT i_0_244 (.A1(n_13), .A2(n_0_581), .ZN(n_0_230)); + OAI211_X1_LVT i_0_243 (.A(n_0_231), .B(n_0_230), .C1(n_0_714), .C2(n_0_681), + .ZN(n_0_229)); + XNOR2_X1_LVT i_10_70 (.A(n_10_55), .B(n_10_56), .ZN(n_45)); + NOR2_X1_LVT i_0_695 (.A1(op2[13]), .A2(n_0_714), .ZN(n_0_662)); + AOI221_X1_LVT i_0_242 (.A(n_0_229), .B1(n_45), .B2(n_0_580), .C1(n_0_662), + .C2(n_0_569), .ZN(n_0_228)); + INV_X1_LVT i_0_267 (.A(n_0_253), .ZN(n_0_252)); + OAI222_X1_LVT i_0_257 (.A1(n_0_714), .A2(n_0_615), .B1(n_0_726), .B2(n_0_617), + .C1(n_0_710), .C2(n_0_605), .ZN(n_0_243)); + OAI22_X1_LVT i_0_256 (.A1(n_0_693), .A2(n_0_312), .B1(op2[2]), .B2(n_0_243), + .ZN(n_0_242)); + NAND2_X1_LVT i_0_255 (.A1(n_0_728), .A2(n_0_242), .ZN(n_0_241)); + NAND2_X1_LVT i_0_254 (.A1(op2[1]), .A2(n_0_274), .ZN(n_0_240)); + NAND2_X1_LVT i_0_241 (.A1(n_0_241), .A2(n_0_240), .ZN(n_0_227)); + OAI221_X1_LVT i_0_240 (.A(n_0_228), .B1(n_0_548), .B2(n_0_252), .C1(n_0_562), + .C2(n_0_227), .ZN(n_0_226)); + NAND2_X1_LVT i_0_249 (.A1(n_0_728), .A2(n_0_279), .ZN(n_0_235)); + AOI22_X1_LVT i_0_250 (.A1(n_0_597), .A2(n_0_575), .B1(op1[6]), .B2(n_0_496), + .ZN(n_0_236)); + OAI21_X1_LVT i_0_248 (.A(n_0_235), .B1(n_0_728), .B2(n_0_236), .ZN(n_0_234)); + INV_X1_LVT i_0_247 (.A(n_0_234), .ZN(n_0_233)); + AOI221_X1_LVT i_0_246 (.A(n_0_621), .B1(op2[0]), .B2(n_0_233), .C1(n_0_701), + .C2(n_0_264), .ZN(n_0_232)); + NAND2_X1_LVT i_0_264 (.A1(op2[3]), .A2(n_0_469), .ZN(n_0_249)); + AOI21_X1_LVT i_0_262 (.A(n_0_468), .B1(n_0_693), .B2(n_0_249), .ZN(n_0_247)); + INV_X1_LVT i_0_261 (.A(n_0_247), .ZN(n_0_246)); + OAI211_X1_LVT i_0_260 (.A(n_0_252), .B(n_0_246), .C1(n_0_468), .C2(n_0_254), + .ZN(n_0_245)); + OAI221_X1_LVT i_0_253 (.A(n_0_544), .B1(n_0_247), .B2(n_0_241), .C1(n_0_469), + .C2(n_0_240), .ZN(n_0_239)); + INV_X1_LVT i_0_252 (.A(n_0_239), .ZN(n_0_238)); + AOI211_X1_LVT i_0_239 (.A(n_0_226), .B(n_0_232), .C1(n_0_245), .C2(n_0_238), + .ZN(n_0_225)); + INV_X1_LVT i_0_238 (.A(n_0_225), .ZN(result[13])); + OAI221_X1_LVT i_0_232 (.A(op2[12]), .B1(n_0_696), .B2(n_0_567), .C1(op1[12]), + .C2(n_0_564), .ZN(n_0_219)); + OAI21_X1_LVT i_0_231 (.A(n_0_681), .B1(op2[12]), .B2(n_0_568), .ZN(n_0_218)); + XNOR2_X1_LVT i_10_66 (.A(n_10_52), .B(n_10_53), .ZN(n_44)); + AOI222_X1_LVT i_0_230 (.A1(n_12), .A2(n_0_581), .B1(op1[12]), .B2(n_0_218), + .C1(n_44), .C2(n_0_580), .ZN(n_0_217)); + OAI21_X1_LVT i_0_234 (.A(n_0_620), .B1(op2[1]), .B2(n_0_265), .ZN(n_0_221)); + INV_X1_LVT i_0_763 (.A(op1[5]), .ZN(n_0_730)); + OAI21_X1_LVT i_0_236 (.A(op2[2]), .B1(n_0_730), .B2(n_0_615), .ZN(n_0_223)); + OAI21_X1_LVT i_0_235 (.A(n_0_223), .B1(op2[2]), .B2(n_0_296), .ZN(n_0_222)); + AOI21_X1_LVT i_0_233 (.A(n_0_221), .B1(op2[1]), .B2(n_0_222), .ZN(n_0_220)); + NOR2_X1_LVT i_0_237 (.A1(n_0_577), .A2(n_0_227), .ZN(n_0_224)); + NOR4_X1_LVT i_0_223 (.A1(n_0_701), .A2(n_0_220), .A3(n_0_224), .A4(n_0_238), + .ZN(n_0_210)); + NAND2_X1_LVT i_0_224 (.A1(n_0_544), .A2(n_0_247), .ZN(n_0_211)); + NAND2_X1_LVT i_0_222 (.A1(n_0_701), .A2(n_0_211), .ZN(n_0_209)); + OAI22_X1_LVT i_0_229 (.A1(op2[4]), .A2(n_0_696), .B1(n_0_738), .B2(n_0_698), + .ZN(n_0_216)); + INV_X1_LVT i_0_228 (.A(n_0_216), .ZN(n_0_215)); + OAI22_X1_LVT i_0_227 (.A1(n_0_727), .A2(n_0_617), .B1(op2[3]), .B2(n_0_215), + .ZN(n_0_214)); + OAI22_X1_LVT i_0_226 (.A1(n_0_693), .A2(n_0_289), .B1(op2[2]), .B2(n_0_214), + .ZN(n_0_213)); + OAI22_X1_LVT i_0_225 (.A1(op2[1]), .A2(n_0_213), .B1(n_0_728), .B2(n_0_255), + .ZN(n_0_212)); + AOI221_X1_LVT i_0_221 (.A(n_0_209), .B1(n_0_578), .B2(n_0_212), .C1(n_0_620), + .C2(n_0_234), .ZN(n_0_208)); + OAI211_X1_LVT i_0_220 (.A(n_0_219), .B(n_0_217), .C1(n_0_210), .C2(n_0_208), + .ZN(result[12])); + OAI21_X1_LVT i_0_209 (.A(n_0_681), .B1(op2[11]), .B2(n_0_568), .ZN(n_0_197)); + AOI22_X1_LVT i_0_208 (.A1(n_11), .A2(n_0_581), .B1(op1[11]), .B2(n_0_197), + .ZN(n_0_196)); + NAND2_X1_LVT i_0_207 (.A1(n_0_211), .A2(n_0_196), .ZN(n_0_195)); + AOI22_X1_LVT i_0_210 (.A1(op1[11]), .A2(n_0_566), .B1(n_0_706), .B2(n_0_565), + .ZN(n_0_198)); + XNOR2_X1_LVT i_10_62 (.A(n_10_49), .B(n_10_50), .ZN(n_43)); + AOI221_X1_LVT i_0_206 (.A(n_0_195), .B1(op2[11]), .B2(n_0_198), .C1(n_43), + .C2(n_0_580), .ZN(n_0_194)); + AOI221_X1_LVT i_0_215 (.A(op2[3]), .B1(n_0_738), .B2(n_0_706), .C1(op2[4]), + .C2(n_0_688), .ZN(n_0_203)); + AOI21_X1_LVT i_0_214 (.A(n_0_203), .B1(op1[19]), .B2(n_0_618), .ZN(n_0_202)); + NAND2_X1_LVT i_0_213 (.A1(n_0_693), .A2(n_0_202), .ZN(n_0_201)); + OAI21_X1_LVT i_0_212 (.A(n_0_201), .B1(n_0_693), .B2(n_0_275), .ZN(n_0_200)); + OAI22_X1_LVT i_0_211 (.A1(n_0_728), .A2(n_0_242), .B1(op2[1]), .B2(n_0_200), + .ZN(n_0_199)); + AOI22_X1_LVT i_0_205 (.A1(n_0_561), .A2(n_0_199), .B1(n_0_701), .B2(n_0_220), + .ZN(n_0_193)); + NOR2_X1_LVT i_0_219 (.A1(op2[2]), .A2(n_0_280), .ZN(n_0_207)); + AOI21_X1_LVT i_0_218 (.A(n_0_207), .B1(op1[4]), .B2(n_0_496), .ZN(n_0_206)); + AOI22_X1_LVT i_0_217 (.A1(n_0_728), .A2(n_0_236), .B1(op2[1]), .B2(n_0_206), + .ZN(n_0_205)); + AOI22_X1_LVT i_0_216 (.A1(n_0_578), .A2(n_0_212), .B1(n_0_620), .B2(n_0_205), + .ZN(n_0_204)); + OAI211_X1_LVT i_0_204 (.A(n_0_194), .B(n_0_193), .C1(n_0_701), .C2(n_0_204), + .ZN(result[11])); + AOI22_X1_LVT i_0_194 (.A1(n_0_654), .A2(n_0_498), .B1(op1[7]), .B2(n_0_573), + .ZN(n_0_183)); + OAI22_X1_LVT i_0_193 (.A1(n_0_728), .A2(n_0_183), .B1(op2[1]), .B2(n_0_222), + .ZN(n_0_182)); + AOI22_X1_LVT i_0_192 (.A1(op2[0]), .A2(n_0_182), .B1(n_0_701), .B2(n_0_205), + .ZN(n_0_181)); + NOR2_X1_LVT i_0_191 (.A1(n_0_621), .A2(n_0_181), .ZN(n_0_180)); + AOI22_X1_LVT i_0_190 (.A1(op1[10]), .A2(n_0_566), .B1(n_0_733), .B2(n_0_565), + .ZN(n_0_179)); + XNOR2_X1_LVT i_10_58 (.A(n_10_46), .B(n_10_47), .ZN(n_42)); + AOI22_X1_LVT i_0_188 (.A1(op2[10]), .A2(n_0_179), .B1(n_42), .B2(n_0_580), + .ZN(n_0_177)); + OAI21_X1_LVT i_0_189 (.A(n_0_681), .B1(op2[10]), .B2(n_0_568), .ZN(n_0_178)); + AOI22_X1_LVT i_0_187 (.A1(n_10), .A2(n_0_581), .B1(op1[10]), .B2(n_0_178), + .ZN(n_0_176)); + NAND2_X1_LVT i_0_186 (.A1(n_0_177), .A2(n_0_176), .ZN(n_0_175)); + NOR2_X1_LVT i_0_203 (.A1(n_0_701), .A2(n_0_199), .ZN(n_0_192)); + NOR2_X1_LVT i_0_200 (.A1(n_0_693), .A2(n_0_256), .ZN(n_0_189)); + AOI221_X1_LVT i_0_202 (.A(n_0_596), .B1(op1[10]), .B2(n_0_616), .C1(op1[26]), + .C2(n_0_606), .ZN(n_0_191)); + AOI21_X1_LVT i_0_199 (.A(n_0_189), .B1(n_0_693), .B2(n_0_191), .ZN(n_0_188)); + OR2_X1_LVT i_0_198 (.A1(op2[1]), .A2(n_0_188), .ZN(n_0_187)); + NAND2_X1_LVT i_0_197 (.A1(op2[1]), .A2(n_0_213), .ZN(n_0_186)); + NAND2_X1_LVT i_0_185 (.A1(n_0_187), .A2(n_0_186), .ZN(n_0_174)); + AOI211_X1_LVT i_0_184 (.A(n_0_577), .B(n_0_192), .C1(n_0_701), .C2(n_0_174), + .ZN(n_0_173)); + INV_X1_LVT i_0_263 (.A(n_0_249), .ZN(n_0_248)); + OAI22_X1_LVT i_0_196 (.A1(n_0_248), .A2(n_0_187), .B1(n_0_247), .B2(n_0_186), + .ZN(n_0_185)); + AOI221_X1_LVT i_0_195 (.A(n_0_545), .B1(n_0_246), .B2(n_0_192), .C1(n_0_701), + .C2(n_0_185), .ZN(n_0_184)); + OR4_X1_LVT i_0_183 (.A1(n_0_180), .A2(n_0_175), .A3(n_0_173), .A4(n_0_184), + .ZN(result[10])); + INV_X1_LVT i_0_753 (.A(op2[9]), .ZN(n_0_720)); + AOI221_X1_LVT i_0_171 (.A(n_0_720), .B1(op1[9]), .B2(n_0_566), .C1(n_0_722), + .C2(n_0_565), .ZN(n_0_161)); + XNOR2_X1_LVT i_10_54 (.A(n_10_43), .B(n_10_44), .ZN(n_41)); + AOI22_X1_LVT i_0_172 (.A1(n_9), .A2(n_0_581), .B1(n_41), .B2(n_0_580), + .ZN(n_0_162)); + AOI21_X1_LVT i_0_170 (.A(aluBypass), .B1(n_0_720), .B2(n_0_569), .ZN(n_0_160)); + OAI21_X1_LVT i_0_169 (.A(n_0_162), .B1(n_0_722), .B2(n_0_160), .ZN(n_0_159)); + OAI222_X1_LVT i_0_182 (.A1(n_0_722), .A2(n_0_615), .B1(n_0_699), .B2(n_0_605), + .C1(n_0_732), .C2(n_0_617), .ZN(n_0_172)); + AOI22_X1_LVT i_0_181 (.A1(n_0_693), .A2(n_0_172), .B1(op2[2]), .B2(n_0_243), + .ZN(n_0_171)); + NAND2_X1_LVT i_0_180 (.A1(n_0_728), .A2(n_0_171), .ZN(n_0_170)); + NAND2_X1_LVT i_0_179 (.A1(op2[1]), .A2(n_0_200), .ZN(n_0_169)); + OAI22_X1_LVT i_0_178 (.A1(n_0_248), .A2(n_0_170), .B1(n_0_247), .B2(n_0_169), + .ZN(n_0_168)); + NOR3_X1_LVT i_0_177 (.A1(n_0_545), .A2(n_0_168), .A3(n_0_185), .ZN(n_0_167)); + NOR2_X1_LVT i_0_251 (.A1(n_0_704), .A2(n_0_615), .ZN(n_0_237)); + OAI22_X1_LVT i_0_176 (.A1(op1[2]), .A2(n_0_693), .B1(n_0_496), .B2(n_0_237), + .ZN(n_0_166)); + OAI22_X1_LVT i_0_175 (.A1(op2[1]), .A2(n_0_206), .B1(n_0_728), .B2(n_0_166), + .ZN(n_0_165)); + OAI221_X1_LVT i_0_174 (.A(n_0_620), .B1(op2[0]), .B2(n_0_182), .C1(n_0_701), + .C2(n_0_165), .ZN(n_0_164)); + NAND2_X1_LVT i_0_173 (.A1(n_0_170), .A2(n_0_169), .ZN(n_0_163)); + OAI221_X1_LVT i_0_168 (.A(n_0_164), .B1(n_0_562), .B2(n_0_163), .C1(n_0_548), + .C2(n_0_174), .ZN(n_0_158)); + OR4_X1_LVT i_0_167 (.A1(n_0_161), .A2(n_0_159), .A3(n_0_167), .A4(n_0_158), + .ZN(result[9])); + OAI21_X1_LVT i_0_160 (.A(n_0_693), .B1(n_0_730), .B2(n_0_615), .ZN(n_0_151)); + OAI21_X1_LVT i_0_159 (.A(op2[2]), .B1(n_0_729), .B2(n_0_615), .ZN(n_0_150)); + AND2_X1_LVT i_0_158 (.A1(n_0_151), .A2(n_0_150), .ZN(n_0_149)); + NAND2_X1_LVT i_0_157 (.A1(op2[1]), .A2(n_0_149), .ZN(n_0_148)); + OAI21_X1_LVT i_0_156 (.A(n_0_148), .B1(op2[1]), .B2(n_0_183), .ZN(n_0_147)); + OAI22_X1_LVT i_0_155 (.A1(op2[0]), .A2(n_0_165), .B1(n_0_701), .B2(n_0_147), + .ZN(n_0_146)); + NOR2_X1_LVT i_0_154 (.A1(n_0_621), .A2(n_0_146), .ZN(n_0_145)); + INV_X1_LVT i_0_773 (.A(op1[8]), .ZN(n_0_740)); + NOR2_X1_LVT i_0_688 (.A1(n_0_740), .A2(op2[8]), .ZN(n_0_655)); + AOI22_X1_LVT i_0_153 (.A1(op1[8]), .A2(aluBypass), .B1(n_0_655), .B2(n_0_569), + .ZN(n_0_144)); + OAI221_X1_LVT i_0_152 (.A(op2[8]), .B1(op1[8]), .B2(n_0_564), .C1(n_0_740), + .C2(n_0_567), .ZN(n_0_143)); + XNOR2_X1_LVT i_10_51 (.A(n_10_39), .B(n_10_42), .ZN(n_40)); + AOI22_X1_LVT i_0_151 (.A1(n_40), .A2(n_0_580), .B1(n_8), .B2(n_0_581), + .ZN(n_0_142)); + NAND3_X1_LVT i_0_150 (.A1(n_0_144), .A2(n_0_143), .A3(n_0_142), .ZN(n_0_141)); + OAI222_X1_LVT i_0_166 (.A1(n_0_740), .A2(n_0_615), .B1(n_0_739), .B2(n_0_617), + .C1(n_0_736), .C2(n_0_605), .ZN(n_0_157)); + OAI22_X1_LVT i_0_165 (.A1(op2[2]), .A2(n_0_157), .B1(n_0_693), .B2(n_0_214), + .ZN(n_0_156)); + NOR2_X1_LVT i_0_164 (.A1(op2[1]), .A2(n_0_156), .ZN(n_0_155)); + AOI21_X1_LVT i_0_163 (.A(n_0_155), .B1(op2[1]), .B2(n_0_188), .ZN(n_0_154)); + AND2_X1_LVT i_0_162 (.A1(n_0_701), .A2(n_0_154), .ZN(n_0_153)); + AOI211_X1_LVT i_0_149 (.A(n_0_577), .B(n_0_153), .C1(op2[0]), .C2(n_0_163), + .ZN(n_0_140)); + AOI221_X1_LVT i_0_161 (.A(n_0_545), .B1(op2[0]), .B2(n_0_168), .C1(n_0_249), + .C2(n_0_153), .ZN(n_0_152)); + OR4_X1_LVT i_0_148 (.A1(n_0_145), .A2(n_0_141), .A3(n_0_140), .A4(n_0_152), + .ZN(result[8])); + AOI22_X1_LVT i_0_138 (.A1(op1[4]), .A2(n_0_573), .B1(op1[0]), .B2(n_0_496), + .ZN(n_0_130)); + AOI22_X1_LVT i_0_137 (.A1(op2[1]), .A2(n_0_130), .B1(n_0_728), .B2(n_0_166), + .ZN(n_0_129)); + OAI22_X1_LVT i_0_136 (.A1(n_0_701), .A2(n_0_129), .B1(op2[0]), .B2(n_0_147), + .ZN(n_0_128)); + NOR2_X1_LVT i_0_135 (.A1(n_0_621), .A2(n_0_128), .ZN(n_0_127)); + OAI221_X1_LVT i_0_139 (.A(op2[7]), .B1(n_0_713), .B2(n_0_567), .C1(op1[7]), + .C2(n_0_564), .ZN(n_0_131)); + INV_X1_LVT i_10_44 (.A(n_10_36), .ZN(n_10_37)); + NOR2_X1_LVT i_10_45 (.A1(n_10_35), .A2(n_10_37), .ZN(n_10_38)); + XNOR2_X1_LVT i_10_46 (.A(n_10_33), .B(n_10_38), .ZN(n_39)); + AOI22_X1_LVT i_0_141 (.A1(n_7), .A2(n_0_581), .B1(n_39), .B2(n_0_580), + .ZN(n_0_133)); + INV_X1_LVT i_0_745 (.A(op2[7]), .ZN(n_0_712)); + AOI21_X1_LVT i_0_140 (.A(aluBypass), .B1(n_0_712), .B2(n_0_569), .ZN(n_0_132)); + OAI211_X1_LVT i_0_133 (.A(n_0_131), .B(n_0_133), .C1(n_0_713), .C2(n_0_132), + .ZN(n_0_125)); + OAI22_X1_LVT i_0_147 (.A1(n_0_734), .A2(n_0_617), .B1(n_0_713), .B2(n_0_615), + .ZN(n_0_139)); + AOI211_X1_LVT i_0_146 (.A(n_0_139), .B(n_0_248), .C1(op1[23]), .C2(n_0_606), + .ZN(n_0_138)); + OAI22_X1_LVT i_0_145 (.A1(n_0_693), .A2(n_0_202), .B1(op2[2]), .B2(n_0_138), + .ZN(n_0_137)); + NOR2_X1_LVT i_0_144 (.A1(op2[1]), .A2(n_0_137), .ZN(n_0_136)); + AOI21_X1_LVT i_0_143 (.A(n_0_136), .B1(op2[1]), .B2(n_0_171), .ZN(n_0_135)); + NAND2_X1_LVT i_0_142 (.A1(n_0_561), .A2(n_0_135), .ZN(n_0_134)); + OAI221_X1_LVT i_0_134 (.A(n_0_134), .B1(n_0_548), .B2(n_0_154), .C1(n_0_545), + .C2(n_0_249), .ZN(n_0_126)); + OR3_X1_LVT i_0_132 (.A1(n_0_127), .A2(n_0_125), .A3(n_0_126), .ZN(result[7])); + NAND2_X1_LVT i_0_124 (.A1(n_0_728), .A2(n_0_149), .ZN(n_0_117)); + OAI21_X1_LVT i_0_123 (.A(n_0_117), .B1(n_0_724), .B2(n_0_531), .ZN(n_0_116)); + OAI22_X1_LVT i_0_122 (.A1(n_0_701), .A2(n_0_116), .B1(op2[0]), .B2(n_0_129), + .ZN(n_0_115)); + NOR2_X1_LVT i_0_121 (.A1(n_0_621), .A2(n_0_115), .ZN(n_0_114)); + XNOR2_X1_LVT i_10_38 (.A(n_10_30), .B(n_10_31), .ZN(n_38)); + AOI22_X1_LVT i_0_119 (.A1(n_6), .A2(n_0_581), .B1(n_38), .B2(n_0_580), + .ZN(n_0_112)); + INV_X1_LVT i_0_735 (.A(op2[6]), .ZN(n_0_702)); + AOI21_X1_LVT i_0_120 (.A(aluBypass), .B1(n_0_702), .B2(n_0_569), .ZN(n_0_113)); + OAI21_X1_LVT i_0_118 (.A(n_0_112), .B1(n_0_704), .B2(n_0_113), .ZN(n_0_111)); + AOI221_X1_LVT i_0_117 (.A(n_0_702), .B1(n_0_704), .B2(n_0_565), .C1(op1[6]), + .C2(n_0_566), .ZN(n_0_110)); + NOR3_X1_LVT i_0_116 (.A1(n_0_114), .A2(n_0_111), .A3(n_0_110), .ZN(n_0_109)); + AOI221_X1_LVT i_0_131 (.A(n_0_237), .B1(op1[14]), .B2(n_0_618), .C1(op2[4]), + .C2(n_0_406), .ZN(n_0_124)); + NAND2_X1_LVT i_0_130 (.A1(n_0_693), .A2(n_0_124), .ZN(n_0_123)); + INV_X1_LVT i_0_201 (.A(n_0_191), .ZN(n_0_190)); + OAI21_X1_LVT i_0_129 (.A(n_0_123), .B1(n_0_693), .B2(n_0_190), .ZN(n_0_122)); + AOI22_X1_LVT i_0_128 (.A1(n_0_728), .A2(n_0_122), .B1(op2[1]), .B2(n_0_156), + .ZN(n_0_121)); + INV_X1_LVT i_0_127 (.A(n_0_121), .ZN(n_0_120)); + OAI21_X1_LVT i_0_126 (.A(n_0_248), .B1(op2[1]), .B2(n_0_123), .ZN(n_0_119)); + AND2_X1_LVT i_0_125 (.A1(n_0_120), .A2(n_0_119), .ZN(n_0_118)); + NOR2_X1_LVT i_0_115 (.A1(n_0_545), .A2(n_0_118), .ZN(n_0_108)); + AOI21_X1_LVT i_0_114 (.A(n_0_108), .B1(n_0_576), .B2(n_0_121), .ZN(n_0_107)); + AOI22_X1_LVT i_0_113 (.A1(n_0_544), .A2(n_0_248), .B1(n_0_578), .B2(n_0_135), + .ZN(n_0_106)); + OAI221_X1_LVT i_0_112 (.A(n_0_109), .B1(op2[0]), .B2(n_0_107), .C1(n_0_701), + .C2(n_0_106), .ZN(result[6])); + OAI221_X1_LVT i_0_100 (.A(op2[5]), .B1(op1[5]), .B2(n_0_564), .C1(n_0_730), + .C2(n_0_567), .ZN(n_0_94)); + INV_X1_LVT i_0_764 (.A(op2[5]), .ZN(n_0_731)); + AOI21_X1_LVT i_0_99 (.A(aluBypass), .B1(n_0_731), .B2(n_0_569), .ZN(n_0_93)); + NOR2_X1_LVT i_0_98 (.A1(n_0_730), .A2(n_0_93), .ZN(n_0_92)); + XNOR2_X1_LVT i_10_35 (.A(n_10_26), .B(n_10_29), .ZN(n_37)); + AOI221_X1_LVT i_0_97 (.A(n_0_92), .B1(n_37), .B2(n_0_580), .C1(n_5), .C2( + n_0_581), .ZN(n_0_91)); + OAI22_X1_LVT i_0_102 (.A1(n_0_694), .A2(n_0_531), .B1(op2[1]), .B2(n_0_130), + .ZN(n_0_96)); + OAI221_X1_LVT i_0_101 (.A(n_0_620), .B1(n_0_701), .B2(n_0_96), .C1(op2[0]), + .C2(n_0_116), .ZN(n_0_95)); + NAND3_X1_LVT i_0_111 (.A1(n_0_544), .A2(n_0_248), .A3(op2[2]), .ZN(n_0_105)); + NAND2_X1_LVT i_0_110 (.A1(op2[4]), .A2(n_0_386), .ZN(n_0_104)); + OAI21_X1_LVT i_0_109 (.A(n_0_104), .B1(n_0_714), .B2(n_0_617), .ZN(n_0_103)); + OAI22_X1_LVT i_0_108 (.A1(n_0_151), .A2(n_0_103), .B1(n_0_693), .B2(n_0_172), + .ZN(n_0_102)); + NOR2_X1_LVT i_0_107 (.A1(op2[1]), .A2(n_0_102), .ZN(n_0_101)); + AOI21_X1_LVT i_0_106 (.A(n_0_101), .B1(op2[1]), .B2(n_0_137), .ZN(n_0_100)); + OAI21_X1_LVT i_0_105 (.A(n_0_105), .B1(n_0_579), .B2(n_0_100), .ZN(n_0_99)); + AOI21_X1_LVT i_0_104 (.A(n_0_118), .B1(n_0_682), .B2(n_0_120), .ZN(n_0_98)); + OAI22_X1_LVT i_0_103 (.A1(n_0_547), .A2(n_0_99), .B1(n_0_701), .B2(n_0_98), + .ZN(n_0_97)); + NAND4_X1_LVT i_0_96 (.A1(n_0_94), .A2(n_0_91), .A3(n_0_95), .A4(n_0_97), + .ZN(result[5])); + INV_X1_LVT i_10_26 (.A(n_10_21), .ZN(n_10_22)); + NOR2_X1_LVT i_10_28 (.A1(n_10_22), .A2(n_10_23), .ZN(n_10_24)); + XNOR2_X1_LVT i_10_29 (.A(n_10_19), .B(n_10_24), .ZN(n_36)); + AOI222_X1_LVT i_0_89 (.A1(n_4), .A2(n_0_581), .B1(n_36), .B2(n_0_580), + .C1(n_0_668), .C2(n_0_564), .ZN(n_0_84)); + INV_X1_LVT i_0_770 (.A(op1[4]), .ZN(n_0_737)); + AOI221_X1_LVT i_0_90 (.A(aluBypass), .B1(op2[4]), .B2(n_0_567), .C1(n_0_738), + .C2(n_0_569), .ZN(n_0_85)); + OAI21_X1_LVT i_0_88 (.A(n_0_84), .B1(n_0_737), .B2(n_0_85), .ZN(n_0_83)); + NOR2_X1_LVT i_0_689 (.A1(op2[4]), .A2(n_0_737), .ZN(n_0_656)); + AOI21_X1_LVT i_0_95 (.A(n_0_616), .B1(n_0_727), .B2(n_0_723), .ZN(n_0_90)); + OAI22_X1_LVT i_0_94 (.A1(n_0_723), .A2(n_0_216), .B1(n_0_656), .B2(n_0_90), + .ZN(n_0_89)); + INV_X1_LVT i_0_93 (.A(n_0_89), .ZN(n_0_88)); + OAI22_X1_LVT i_0_92 (.A1(op2[2]), .A2(n_0_88), .B1(n_0_693), .B2(n_0_157), + .ZN(n_0_87)); + OAI221_X1_LVT i_0_91 (.A(n_0_105), .B1(n_0_728), .B2(n_0_122), .C1(op2[1]), + .C2(n_0_87), .ZN(n_0_86)); + AOI221_X1_LVT i_0_85 (.A(n_0_83), .B1(n_0_561), .B2(n_0_86), .C1(op2[0]), + .C2(n_0_99), .ZN(n_0_80)); + AOI221_X1_LVT i_0_87 (.A(n_0_574), .B1(n_0_729), .B2(op2[1]), .C1(n_0_728), + .C2(n_0_724), .ZN(n_0_82)); + OAI22_X1_LVT i_0_86 (.A1(op2[0]), .A2(n_0_96), .B1(n_0_701), .B2(n_0_82), + .ZN(n_0_81)); + OAI21_X1_LVT i_0_84 (.A(n_0_80), .B1(n_0_621), .B2(n_0_81), .ZN(result[4])); + AND2_X1_LVT i_0_81 (.A1(op2[1]), .A2(n_0_105), .ZN(n_0_77)); + NAND2_X1_LVT i_0_80 (.A1(n_0_102), .A2(n_0_77), .ZN(n_0_76)); + OAI221_X1_LVT i_0_83 (.A(n_0_693), .B1(n_0_654), .B2(n_0_484), .C1(n_0_738), + .C2(n_0_350), .ZN(n_0_79)); + OAI21_X1_LVT i_0_82 (.A(n_0_79), .B1(n_0_693), .B2(n_0_138), .ZN(n_0_78)); + OAI21_X1_LVT i_0_79 (.A(n_0_76), .B1(op2[1]), .B2(n_0_78), .ZN(n_0_75)); + NOR2_X1_LVT i_0_78 (.A1(n_0_562), .A2(n_0_75), .ZN(n_0_74)); + NAND2_X1_LVT i_10_20 (.A1(n_10_15), .A2(n_10_16), .ZN(n_10_17)); + XNOR2_X1_LVT i_10_21 (.A(n_10_13), .B(n_10_17), .ZN(n_35)); + AOI22_X1_LVT i_0_75 (.A1(n_35), .A2(n_0_580), .B1(n_3), .B2(n_0_581), + .ZN(n_0_71)); + OAI21_X1_LVT i_0_74 (.A(n_0_681), .B1(n_0_723), .B2(n_0_566), .ZN(n_0_70)); + AOI222_X1_LVT i_0_73 (.A1(n_0_654), .A2(n_0_569), .B1(n_0_663), .B2(n_0_564), + .C1(op1[3]), .C2(n_0_70), .ZN(n_0_69)); + INV_X1_LVT i_0_736 (.A(op1[0]), .ZN(n_0_703)); + OAI22_X1_LVT i_0_77 (.A1(n_0_703), .A2(n_0_531), .B1(n_0_694), .B2(n_0_572), + .ZN(n_0_73)); + OAI22_X1_LVT i_0_76 (.A1(n_0_701), .A2(n_0_73), .B1(op2[0]), .B2(n_0_82), + .ZN(n_0_72)); + OAI211_X1_LVT i_0_72 (.A(n_0_71), .B(n_0_69), .C1(n_0_621), .C2(n_0_72), + .ZN(n_0_68)); + AOI211_X1_LVT i_0_71 (.A(n_0_74), .B(n_0_68), .C1(n_0_547), .C2(n_0_86), + .ZN(n_0_67)); + INV_X1_LVT i_0_70 (.A(n_0_67), .ZN(result[3])); + NAND2_X1_LVT i_0_65 (.A1(n_2), .A2(n_0_581), .ZN(n_0_62)); + OAI221_X1_LVT i_0_66 (.A(op2[2]), .B1(op1[2]), .B2(n_0_564), .C1(n_0_694), + .C2(n_0_567), .ZN(n_0_63)); + AOI21_X1_LVT i_0_64 (.A(aluBypass), .B1(n_0_693), .B2(n_0_569), .ZN(n_0_61)); + OAI21_X1_LVT i_0_63 (.A(n_0_63), .B1(n_0_694), .B2(n_0_61), .ZN(n_0_60)); + INV_X1_LVT i_10_13 (.A(n_10_10), .ZN(n_10_11)); + NOR2_X1_LVT i_10_14 (.A1(n_10_9), .A2(n_10_11), .ZN(n_10_12)); + XNOR2_X1_LVT i_10_15 (.A(n_10_7), .B(n_10_12), .ZN(n_34)); + AOI21_X1_LVT i_0_62 (.A(n_0_60), .B1(n_34), .B2(n_0_580), .ZN(n_0_59)); + OAI211_X1_LVT i_0_57 (.A(n_0_62), .B(n_0_59), .C1(n_0_548), .C2(n_0_75), + .ZN(n_0_54)); + NOR2_X1_LVT i_0_698 (.A1(n_0_729), .A2(op2[1]), .ZN(n_0_665)); + INV_X1_LVT i_0_697 (.A(n_0_665), .ZN(n_0_664)); + OAI21_X1_LVT i_0_69 (.A(op2[0]), .B1(n_0_664), .B2(n_0_574), .ZN(n_0_66)); + OAI21_X1_LVT i_0_68 (.A(n_0_620), .B1(op2[0]), .B2(n_0_73), .ZN(n_0_65)); + INV_X1_LVT i_0_67 (.A(n_0_65), .ZN(n_0_64)); + OAI222_X1_LVT i_0_61 (.A1(op1[10]), .A2(n_0_617), .B1(op1[2]), .B2(n_0_615), + .C1(n_0_738), .C2(n_0_332), .ZN(n_0_58)); + OAI22_X1_LVT i_0_60 (.A1(op2[2]), .A2(n_0_58), .B1(n_0_693), .B2(n_0_124), + .ZN(n_0_57)); + INV_X1_LVT i_0_59 (.A(n_0_57), .ZN(n_0_56)); + AOI22_X1_LVT i_0_58 (.A1(n_0_728), .A2(n_0_56), .B1(n_0_87), .B2(n_0_77), + .ZN(n_0_55)); + AOI221_X1_LVT i_0_56 (.A(n_0_54), .B1(n_0_66), .B2(n_0_64), .C1(n_0_561), + .C2(n_0_55), .ZN(n_0_53)); + INV_X1_LVT i_0_55 (.A(n_0_53), .ZN(result[2])); + NAND2_X1_LVT i_0_54 (.A1(n_0_547), .A2(n_0_55), .ZN(n_0_52)); + AOI221_X1_LVT i_0_47 (.A(n_0_728), .B1(n_0_729), .B2(n_0_565), .C1(op1[1]), + .C2(n_0_566), .ZN(n_0_45)); + NOR2_X1_LVT i_0_700 (.A1(op1[0]), .A2(n_0_701), .ZN(n_0_667)); + AOI211_X1_LVT i_0_48 (.A(n_0_667), .B(n_0_621), .C1(n_0_729), .C2(n_0_701), + .ZN(n_0_46)); + AOI221_X1_LVT i_0_44 (.A(n_0_45), .B1(op1[1]), .B2(aluBypass), .C1(n_0_571), + .C2(n_0_46), .ZN(n_0_42)); + NAND2_X1_LVT i_10_6 (.A1(n_10_3), .A2(n_10_4), .ZN(n_10_5)); + XNOR2_X1_LVT i_10_7 (.A(n_10_5), .B(n_10_1), .ZN(n_33)); + AOI22_X1_LVT i_0_49 (.A1(n_33), .A2(n_0_580), .B1(n_1), .B2(n_0_581), + .ZN(n_0_47)); + OAI21_X1_LVT i_0_46 (.A(n_0_47), .B1(n_0_664), .B2(n_0_568), .ZN(n_0_44)); + NAND2_X1_LVT i_0_51 (.A1(op2[1]), .A2(n_0_78), .ZN(n_0_49)); + OAI222_X1_LVT i_0_53 (.A1(n_0_722), .A2(n_0_617), .B1(n_0_729), .B2(n_0_615), + .C1(n_0_738), .C2(n_0_313), .ZN(n_0_51)); + OAI22_X1_LVT i_0_52 (.A1(n_0_223), .A2(n_0_103), .B1(op2[2]), .B2(n_0_51), + .ZN(n_0_50)); + OAI21_X1_LVT i_0_50 (.A(n_0_49), .B1(op2[1]), .B2(n_0_50), .ZN(n_0_48)); + AOI21_X1_LVT i_0_45 (.A(n_0_44), .B1(n_0_561), .B2(n_0_48), .ZN(n_0_43)); + NAND3_X1_LVT i_0_43 (.A1(n_0_52), .A2(n_0_42), .A3(n_0_43), .ZN(result[1])); + OAI222_X1_LVT i_0_11 (.A1(n_0_740), .A2(n_0_617), .B1(n_0_703), .B2(n_0_615), + .C1(n_0_738), .C2(n_0_290), .ZN(n_0_10)); + OAI22_X1_LVT i_0_10 (.A1(op2[2]), .A2(n_0_10), .B1(n_0_693), .B2(n_0_88), + .ZN(n_0_9)); + OAI221_X1_LVT i_0_9 (.A(n_0_701), .B1(n_0_728), .B2(n_0_56), .C1(op2[1]), + .C2(n_0_9), .ZN(n_0_8)); + OAI21_X1_LVT i_0_8 (.A(n_0_8), .B1(n_0_701), .B2(n_0_48), .ZN(n_0_7)); + NOR2_X1_LVT i_0_7 (.A1(n_0_579), .A2(n_0_7), .ZN(n_0_6)); + OAI221_X1_LVT i_0_3 (.A(op2[0]), .B1(op1[0]), .B2(n_0_564), .C1(n_0_703), + .C2(n_0_567), .ZN(n_0_2)); + OAI21_X1_LVT i_10_2 (.A(n_10_1), .B1(n_10_0), .B2(op2[0]), .ZN(n_32)); + AOI22_X1_LVT i_0_2 (.A1(n_32), .A2(n_0_580), .B1(n_0), .B2(n_0_581), .ZN( + n_0_1)); + NAND3_X1_LVT i_0_6 (.A1(n_0_701), .A2(n_0_571), .A3(n_0_620), .ZN(n_0_5)); + OAI211_X1_LVT i_0_5 (.A(n_0_681), .B(n_0_5), .C1(op2[0]), .C2(n_0_568), + .ZN(n_0_4)); + NAND2_X1_LVT i_0_4 (.A1(op1[0]), .A2(n_0_4), .ZN(n_0_3)); + NAND3_X1_LVT i_0_1 (.A1(n_0_2), .A2(n_0_1), .A3(n_0_3), .ZN(n_0_0)); + OAI33_X1_LVT i_0_14 (.A1(n_0_692), .A2(op1[31]), .A3(n_0_683), .B1(op2[31]), + .B2(n_0_691), .B3(aluOp[0]), .ZN(n_0_13)); + INV_X1_LVT i_0_741 (.A(op2[29]), .ZN(n_0_708)); + NAND2_X1_LVT i_0_685 (.A1(op1[29]), .A2(n_0_708), .ZN(n_0_652)); + OAI22_X1_LVT i_0_713 (.A1(n_0_700), .A2(op1[28]), .B1(op1[29]), .B2(n_0_708), + .ZN(n_0_680)); + NAND2_X1_LVT i_0_694 (.A1(n_0_688), .A2(op2[27]), .ZN(n_0_661)); + INV_X1_LVT i_0_742 (.A(op2[26]), .ZN(n_0_709)); + OAI22_X1_LVT i_0_712 (.A1(n_0_699), .A2(op2[25]), .B1(n_0_736), .B2(op2[24]), + .ZN(n_0_679)); + NAND2_X1_LVT i_0_690 (.A1(n_0_727), .A2(op2[20]), .ZN(n_0_657)); + INV_X1_LVT i_0_740 (.A(op2[18]), .ZN(n_0_707)); + OAI22_X1_LVT i_0_711 (.A1(n_0_707), .A2(op1[18]), .B1(n_0_690), .B2(op1[19]), + .ZN(n_0_678)); + OAI22_X1_LVT i_0_29 (.A1(n_0_739), .A2(op2[16]), .B1(n_0_734), .B2(op2[15]), + .ZN(n_0_28)); + INV_X1_LVT i_0_728 (.A(op2[12]), .ZN(n_0_695)); + INV_X1_LVT i_0_748 (.A(op2[13]), .ZN(n_0_715)); + OAI22_X1_LVT i_0_704 (.A1(n_0_706), .A2(op2[11]), .B1(n_0_696), .B2(op2[12]), + .ZN(n_0_671)); + AOI22_X1_LVT i_0_710 (.A1(n_0_740), .A2(op2[8]), .B1(n_0_713), .B2(op2[7]), + .ZN(n_0_677)); + OAI22_X1_LVT i_0_707 (.A1(n_0_731), .A2(op1[5]), .B1(op1[6]), .B2(n_0_702), + .ZN(n_0_674)); + OAI22_X1_LVT i_0_706 (.A1(op1[2]), .A2(n_0_693), .B1(op1[1]), .B2(n_0_728), + .ZN(n_0_673)); + INV_X1_LVT i_0_705 (.A(n_0_673), .ZN(n_0_672)); + INV_X1_LVT i_0_699 (.A(n_0_667), .ZN(n_0_666)); + OAI21_X1_LVT i_0_42 (.A(n_0_672), .B1(n_0_666), .B2(n_0_665), .ZN(n_0_41)); + AOI21_X1_LVT i_0_41 (.A(n_0_654), .B1(op1[2]), .B2(n_0_693), .ZN(n_0_40)); + AOI211_X1_LVT i_0_40 (.A(n_0_668), .B(n_0_663), .C1(n_0_41), .C2(n_0_40), + .ZN(n_0_39)); + AOI211_X1_LVT i_0_39 (.A(n_0_656), .B(n_0_39), .C1(n_0_731), .C2(op1[5]), + .ZN(n_0_38)); + OAI222_X1_LVT i_0_38 (.A1(n_0_704), .A2(op2[6]), .B1(n_0_674), .B2(n_0_38), + .C1(n_0_713), .C2(op2[7]), .ZN(n_0_37)); + AOI221_X1_LVT i_0_37 (.A(n_0_655), .B1(op1[9]), .B2(n_0_720), .C1(n_0_677), + .C2(n_0_37), .ZN(n_0_36)); + INV_X1_LVT i_0_768 (.A(op2[10]), .ZN(n_0_735)); + OAI22_X1_LVT i_0_36 (.A1(n_0_735), .A2(op1[10]), .B1(op1[9]), .B2(n_0_720), + .ZN(n_0_35)); + OAI22_X1_LVT i_0_35 (.A1(op2[10]), .A2(n_0_733), .B1(n_0_36), .B2(n_0_35), + .ZN(n_0_34)); + INV_X1_LVT i_0_34 (.A(n_0_34), .ZN(n_0_33)); + AOI21_X1_LVT i_0_33 (.A(n_0_33), .B1(n_0_706), .B2(op2[11]), .ZN(n_0_32)); + OAI222_X1_LVT i_0_32 (.A1(op1[12]), .A2(n_0_695), .B1(n_0_715), .B2(op1[13]), + .C1(n_0_671), .C2(n_0_32), .ZN(n_0_31)); + OAI221_X1_LVT i_0_31 (.A(n_0_31), .B1(n_0_721), .B2(op2[14]), .C1(op2[13]), + .C2(n_0_714), .ZN(n_0_30)); + AOI22_X1_LVT i_0_30 (.A1(n_0_734), .A2(op2[15]), .B1(n_0_721), .B2(op2[14]), + .ZN(n_0_29)); + AOI21_X1_LVT i_0_28 (.A(n_0_28), .B1(n_0_30), .B2(n_0_29), .ZN(n_0_27)); + AOI221_X1_LVT i_0_27 (.A(n_0_27), .B1(n_0_732), .B2(op2[17]), .C1(n_0_739), + .C2(op2[16]), .ZN(n_0_26)); + AOI211_X1_LVT i_0_26 (.A(n_0_660), .B(n_0_26), .C1(n_0_707), .C2(op1[18]), + .ZN(n_0_25)); + OAI22_X1_LVT i_0_25 (.A1(op2[19]), .A2(n_0_689), .B1(n_0_678), .B2(n_0_25), + .ZN(n_0_24)); + AOI211_X1_LVT i_0_24 (.A(n_0_658), .B(n_0_659), .C1(n_0_657), .C2(n_0_24), + .ZN(n_0_23)); + AOI221_X1_LVT i_0_23 (.A(n_0_23), .B1(n_0_726), .B2(op2[21]), .C1(n_0_687), + .C2(op2[22]), .ZN(n_0_22)); + AOI221_X1_LVT i_0_22 (.A(n_0_22), .B1(op1[22]), .B2(n_0_686), .C1(op1[23]), + .C2(n_0_718), .ZN(n_0_21)); + AOI221_X1_LVT i_0_21 (.A(n_0_21), .B1(n_0_736), .B2(op2[24]), .C1(n_0_719), + .C2(op2[23]), .ZN(n_0_20)); + OAI222_X1_LVT i_0_20 (.A1(op1[26]), .A2(n_0_709), .B1(op1[25]), .B2(n_0_697), + .C1(n_0_679), .C2(n_0_20), .ZN(n_0_19)); + OAI221_X1_LVT i_0_19 (.A(n_0_19), .B1(n_0_711), .B2(op2[26]), .C1(n_0_688), + .C2(op2[27]), .ZN(n_0_18)); + AOI22_X1_LVT i_0_18 (.A1(n_0_700), .A2(op1[28]), .B1(n_0_661), .B2(n_0_18), + .ZN(n_0_17)); + OAI21_X1_LVT i_0_17 (.A(n_0_652), .B1(n_0_680), .B2(n_0_17), .ZN(n_0_16)); + INV_X1_LVT i_0_749 (.A(op2[30]), .ZN(n_0_716)); + OAI21_X1_LVT i_0_16 (.A(n_0_16), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_15)); + OAI22_X1_LVT i_0_708 (.A1(n_0_692), .A2(op1[31]), .B1(op2[31]), .B2(n_0_691), + .ZN(n_0_675)); + AOI21_X1_LVT i_0_15 (.A(n_0_675), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_14)); + AOI21_X1_LVT i_0_13 (.A(n_0_13), .B1(n_0_15), .B2(n_0_14), .ZN(n_0_12)); + NOR4_X1_LVT i_0_12 (.A1(n_0_685), .A2(aluOp[2]), .A3(aluBypass), .A4(n_0_12), + .ZN(n_0_11)); + OR3_X1_LVT i_0_0 (.A1(n_0_6), .A2(n_0_0), .A3(n_0_11), .ZN(result[0])); + OR4_X1_LVT i_0_703 (.A1(n_0_680), .A2(n_0_673), .A3(n_0_675), .A4(n_0_678), + .ZN(n_0_670)); + INV_X1_LVT i_0_709 (.A(n_0_677), .ZN(n_0_676)); + OR4_X1_LVT i_0_702 (.A1(n_0_679), .A2(n_0_674), .A3(n_0_676), .A4(n_0_671), + .ZN(n_0_669)); + AOI22_X1_LVT i_0_663 (.A1(n_0_688), .A2(op2[27]), .B1(op1[22]), .B2(n_0_686), + .ZN(n_0_630)); + OAI22_X1_LVT i_0_662 (.A1(n_0_694), .A2(op2[2]), .B1(op1[30]), .B2(n_0_716), + .ZN(n_0_629)); + AOI221_X1_LVT i_0_661 (.A(n_0_629), .B1(n_0_711), .B2(op2[26]), .C1(n_0_721), + .C2(op2[14]), .ZN(n_0_628)); + AOI21_X1_LVT i_0_664 (.A(n_0_660), .B1(n_0_690), .B2(op1[19]), .ZN(n_0_631)); + OAI222_X1_LVT i_0_660 (.A1(op1[12]), .A2(n_0_695), .B1(n_0_688), .B2(op2[27]), + .C1(op1[22]), .C2(n_0_686), .ZN(n_0_627)); + AOI21_X1_LVT i_0_659 (.A(n_0_663), .B1(n_0_734), .B2(op2[15]), .ZN(n_0_626)); + OAI211_X1_LVT i_0_658 (.A(n_0_666), .B(n_0_626), .C1(n_0_715), .C2(op1[13]), + .ZN(n_0_625)); + AOI211_X1_LVT i_0_657 (.A(n_0_627), .B(n_0_625), .C1(op1[23]), .C2(n_0_718), + .ZN(n_0_624)); + NAND4_X1_LVT i_0_656 (.A1(n_0_630), .A2(n_0_628), .A3(n_0_631), .A4(n_0_624), + .ZN(n_0_623)); + OAI22_X1_LVT i_0_684 (.A1(n_0_721), .A2(op2[14]), .B1(n_0_722), .B2(op2[9]), + .ZN(n_0_651)); + AOI211_X1_LVT i_0_668 (.A(n_0_651), .B(n_0_654), .C1(n_0_719), .C2(op2[23]), + .ZN(n_0_635)); + NAND2_X1_LVT i_0_667 (.A1(n_0_664), .A2(n_0_657), .ZN(n_0_634)); + NOR3_X1_LVT i_0_666 (.A1(n_0_659), .A2(n_0_656), .A3(n_0_634), .ZN(n_0_633)); + AOI21_X1_LVT i_0_671 (.A(n_0_655), .B1(n_0_739), .B2(op2[16]), .ZN(n_0_638)); + AOI21_X1_LVT i_0_670 (.A(n_0_668), .B1(n_0_736), .B2(op2[24]), .ZN(n_0_637)); + OAI22_X1_LVT i_0_673 (.A1(n_0_735), .A2(op1[10]), .B1(n_0_734), .B2(op2[15]), + .ZN(n_0_640)); + AOI221_X1_LVT i_0_672 (.A(n_0_640), .B1(n_0_732), .B2(op2[17]), .C1(n_0_731), + .C2(op1[5]), .ZN(n_0_639)); + AND3_X1_LVT i_0_669 (.A1(n_0_638), .A2(n_0_637), .A3(n_0_639), .ZN(n_0_636)); + OAI22_X1_LVT i_0_682 (.A1(n_0_703), .A2(op2[0]), .B1(n_0_704), .B2(op2[6]), + .ZN(n_0_649)); + OAI22_X1_LVT i_0_681 (.A1(op2[28]), .A2(n_0_698), .B1(op1[25]), .B2(n_0_697), + .ZN(n_0_648)); + AOI21_X1_LVT i_0_678 (.A(n_0_658), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_645)); + AOI21_X1_LVT i_0_677 (.A(n_0_662), .B1(n_0_735), .B2(op1[10]), .ZN(n_0_644)); + INV_X1_LVT i_0_758 (.A(op2[21]), .ZN(n_0_725)); + OAI22_X1_LVT i_0_683 (.A1(op1[21]), .A2(n_0_725), .B1(n_0_739), .B2(op2[16]), + .ZN(n_0_650)); + AOI221_X1_LVT i_0_676 (.A(n_0_650), .B1(n_0_722), .B2(op2[9]), .C1(op1[7]), + .C2(n_0_712), .ZN(n_0_643)); + OAI21_X1_LVT i_0_680 (.A(n_0_652), .B1(n_0_711), .B2(op2[26]), .ZN(n_0_647)); + AOI221_X1_LVT i_0_679 (.A(n_0_647), .B1(n_0_706), .B2(op2[11]), .C1(n_0_707), + .C2(op1[18]), .ZN(n_0_646)); + NAND4_X1_LVT i_0_675 (.A1(n_0_645), .A2(n_0_644), .A3(n_0_643), .A4(n_0_646), + .ZN(n_0_642)); + NOR3_X1_LVT i_0_674 (.A1(n_0_649), .A2(n_0_648), .A3(n_0_642), .ZN(n_0_641)); + NAND4_X1_LVT i_0_665 (.A1(n_0_635), .A2(n_0_633), .A3(n_0_636), .A4(n_0_641), + .ZN(n_0_632)); + NOR4_X1_LVT i_0_655 (.A1(n_0_670), .A2(n_0_669), .A3(n_0_623), .A4(n_0_632), + .ZN(eqFlag)); +endmodule + +module decoder(CurrentPC, JumpOrBranchPC, JumpOrBranch, DAddr, WData, RData, + Instruction, WrMem, DWidth, Rs1, Rs2, Rd, RRs1, RRs2, WRd, WrReg, Illegal); + input [31:0]CurrentPC; + output [31:0]JumpOrBranchPC; + output JumpOrBranch; + output [31:0]DAddr; + output [31:0]WData; + input [31:0]RData; + input [31:0]Instruction; + output WrMem; + output [1:0]DWidth; + output [4:0]Rs1; + output [4:0]Rs2; + output [4:0]Rd; + input [31:0]RRs1; + input [31:0]RRs2; + output [31:0]WRd; + output WrReg; + output Illegal; + + wire eqFlag; + wire n_5_0; + wire n_5_1; + wire n_5_2; + wire n_5_3; + wire n_5_4; + wire n_5_5; + wire n_5_6; + wire n_5_7; + wire n_5_8; + wire n_5_9; + wire n_5_10; + wire n_5_11; + wire n_5_12; + wire n_5_13; + wire n_5_14; + wire n_5_15; + wire n_5_16; + wire n_5_17; + wire n_5_18; + wire n_5_19; + wire n_5_20; + wire n_5_21; + wire n_5_22; + wire n_5_23; + wire n_5_24; + wire n_5_25; + wire n_5_26; + wire n_5_27; + wire n_5_28; + wire n_5_29; + wire n_5_30; + wire n_5_31; + wire n_5_32; + wire n_5_33; + wire n_17_0; + wire n_17_1; + wire n_17_2; + wire n_17_3; + wire n_17_4; + wire n_17_5; + wire n_17_6; + wire n_17_7; + wire n_17_8; + wire n_17_9; + wire n_17_10; + wire n_17_11; + wire n_17_12; + wire n_17_13; + wire n_17_14; + wire n_17_15; + wire n_17_16; + wire n_17_17; + wire n_17_18; + wire n_17_19; + wire n_17_20; + wire n_17_21; + wire n_17_22; + wire n_17_23; + wire n_17_24; + wire n_17_25; + wire n_17_26; + wire n_17_27; + wire n_17_28; + wire n_17_29; + wire n_17_30; + wire n_17_31; + wire n_17_32; + wire n_18_0; + wire n_18_1; + wire n_18_2; + wire n_18_3; + wire n_18_4; + wire n_18_5; + wire n_18_6; + wire n_18_7; + wire n_18_8; + wire n_18_9; + wire n_18_10; + wire n_18_11; + wire n_18_12; + wire n_18_13; + wire n_18_14; + wire n_18_15; + wire n_18_16; + wire n_18_17; + wire n_18_18; + wire n_18_19; + wire n_18_20; + wire n_18_21; + wire n_18_22; + wire n_18_23; + wire n_18_24; + wire n_18_25; + wire n_18_26; + wire n_18_27; + wire n_18_28; + wire n_18_29; + wire n_18_30; + wire n_18_31; + wire n_18_32; + wire n_0_15; + wire n_0_2; + wire n_0_16; + wire n_0_3; + wire n_0_17; + wire n_0_4; + wire n_0_18; + wire n_0_5; + wire n_0_19; + wire n_0_6; + wire n_0_20; + wire n_0_7; + wire n_0_21; + wire n_0_8; + wire n_0_22; + wire n_0_9; + wire n_0_23; + wire n_0_10; + wire n_0_24; + wire n_0_11; + wire n_0_25; + wire n_0_12; + wire n_0_26; + wire n_0_13; + wire n_0_27; + wire n_0_14; + wire n_0_28; + wire n_0_29; + wire n_0_30; + wire n_0_31; + wire n_0_32; + wire n_0_33; + wire n_0_34; + wire n_0_35; + wire n_0_36; + wire n_0_37; + wire n_0_38; + wire n_0_39; + wire n_0_40; + wire n_0_41; + wire n_0_42; + wire n_0_43; + wire n_0_44; + wire n_0_45; + wire n_0_46; + wire n_0_47; + wire n_0_48; + wire n_0_49; + wire n_0_50; + wire n_0_51; + wire n_0_52; + wire n_0_53; + wire n_0_54; + wire n_0_55; + wire n_0_56; + wire n_0_57; + wire n_0_58; + wire n_0_59; + wire n_0_60; + wire n_0_61; + wire n_0_62; + wire n_0_63; + wire n_0_64; + wire n_0_65; + wire n_0_66; + wire n_0_67; + wire n_0_68; + wire n_0_69; + wire n_0_70; + wire n_0_71; + wire n_0_72; + wire n_0_73; + wire n_0_74; + wire n_0_75; + wire n_0_76; + wire n_0_77; + wire n_0_78; + wire n_0_79; + wire n_0_80; + wire n_0_81; + wire n_0_82; + wire n_0_83; + wire n_0_84; + wire n_0_85; + wire n_0_86; + wire n_0_87; + wire n_0_88; + wire n_0_89; + wire n_0_90; + wire n_0_91; + wire n_0_92; + wire n_0_93; + wire n_0_94; + wire n_0_95; + wire n_0_96; + wire n_0_97; + wire [2:0]aluOp; + wire n_0_98; + wire n_0_99; + wire n_0_100; + wire aluNegAr; + wire n_0_101; + wire n_0_102; + wire n_0_103; + wire n_0_104; + wire n_0_105; + wire aluBypass; + wire n_0_106; + wire [31:0]op1; + wire n_0_107; + wire n_0_108; + wire n_0_109; + wire n_0_110; + wire n_0_111; + wire n_0_112; + wire n_0_113; + wire n_0_114; + wire n_0_115; + wire n_0_116; + wire n_0_117; + wire n_0_118; + wire n_0_119; + wire n_0_120; + wire n_0_121; + wire n_0_122; + wire n_0_123; + wire n_0_124; + wire n_0_125; + wire n_0_126; + wire n_0_127; + wire n_0_128; + wire n_0_129; + wire n_0_130; + wire n_0_131; + wire n_0_132; + wire n_0_133; + wire n_0_134; + wire n_0_135; + wire n_0_136; + wire n_0_137; + wire n_0_138; + wire n_0_139; + wire n_0_140; + wire n_0_141; + wire n_0_142; + wire n_0_143; + wire n_0_144; + wire n_0_145; + wire n_0_146; + wire n_0_147; + wire n_0_148; + wire n_0_149; + wire n_0_150; + wire n_0_151; + wire n_0_152; + wire n_0_153; + wire n_0_154; + wire n_0_155; + wire n_0_156; + wire n_0_157; + wire n_0_158; + wire n_0_159; + wire n_0_160; + wire n_0_161; + wire n_0_162; + wire n_0_163; + wire n_0_164; + wire n_0_165; + wire n_0_166; + wire n_0_167; + wire n_0_168; + wire n_0_169; + wire [31:0]op2; + wire n_0_170; + wire n_0_171; + wire n_0_172; + wire n_0_173; + wire n_0_174; + wire n_0_175; + wire n_0_176; + wire n_0_177; + wire n_0_178; + wire n_0_179; + wire n_0_180; + wire n_0_181; + wire n_0_182; + wire n_0_183; + wire n_0_184; + wire n_0_185; + wire n_0_186; + wire n_0_187; + wire n_0_188; + wire n_0_189; + wire n_0_190; + wire n_0_191; + wire n_0_192; + wire n_0_193; + wire n_0_194; + wire n_0_195; + wire n_0_196; + wire n_0_197; + wire n_0_198; + wire n_0_199; + wire n_0_200; + wire n_0_201; + wire n_0_202; + wire n_0_203; + wire n_0_204; + wire n_0_205; + wire n_0_206; + wire n_0_207; + wire n_0_208; + wire n_0_209; + wire n_0_210; + wire n_0_211; + wire n_0_212; + wire n_0_213; + wire n_0_214; + wire n_0_215; + wire n_0_216; + wire n_0_217; + wire n_0_218; + wire n_0_219; + wire n_0_220; + wire n_0_221; + wire n_0_222; + wire n_0_223; + wire n_0_224; + wire n_0_225; + wire n_0_226; + wire n_0_227; + wire n_0_228; + wire n_0_229; + wire n_0_230; + wire n_0_231; + wire n_0_232; + wire n_0_233; + wire n_0_234; + wire n_0_235; + wire n_0_236; + wire n_0_237; + wire n_0_238; + wire n_0_239; + wire n_0_240; + wire n_0_241; + wire n_0_242; + wire n_0_1; + wire n_0_0; + wire n_0_243; + wire n_0_244; + wire n_0_245; + wire n_0_246; + wire n_0_247; + wire n_0_248; + wire n_0_249; + + INV_X1_LVT i_18_1 (.A(CurrentPC[13]), .ZN(n_18_1)); + XNOR2_X1_LVT i_18_32 (.A(CurrentPC[31]), .B(n_18_1), .ZN(n_18_32)); + INV_X1_LVT i_18_0 (.A(Instruction[31]), .ZN(n_18_0)); + HA_X1_LVT i_18_2 (.A(Instruction[8]), .B(CurrentPC[1]), .CO(n_18_2), .S(n_63)); + FA_X1_LVT i_18_3 (.A(Instruction[9]), .B(CurrentPC[2]), .CI(n_18_2), .CO( + n_18_3), .S(n_64)); + FA_X1_LVT i_18_4 (.A(Instruction[10]), .B(CurrentPC[3]), .CI(n_18_3), + .CO(n_18_4), .S(n_65)); + FA_X1_LVT i_18_5 (.A(Instruction[11]), .B(CurrentPC[4]), .CI(n_18_4), + .CO(n_18_5), .S(n_66)); + FA_X1_LVT i_18_6 (.A(Instruction[25]), .B(CurrentPC[5]), .CI(n_18_5), + .CO(n_18_6), .S(n_67)); + FA_X1_LVT i_18_7 (.A(Instruction[26]), .B(CurrentPC[6]), .CI(n_18_6), + .CO(n_18_7), .S(n_68)); + FA_X1_LVT i_18_8 (.A(Instruction[27]), .B(CurrentPC[7]), .CI(n_18_7), + .CO(n_18_8), .S(n_69)); + FA_X1_LVT i_18_9 (.A(Instruction[28]), .B(CurrentPC[8]), .CI(n_18_8), + .CO(n_18_9), .S(n_70)); + FA_X1_LVT i_18_10 (.A(Instruction[29]), .B(CurrentPC[9]), .CI(n_18_9), + .CO(n_18_10), .S(n_71)); + FA_X1_LVT i_18_11 (.A(Instruction[30]), .B(CurrentPC[10]), .CI(n_18_10), + .CO(n_18_11), .S(n_72)); + FA_X1_LVT i_18_12 (.A(Instruction[7]), .B(CurrentPC[11]), .CI(n_18_11), + .CO(n_18_12), .S(n_73)); + FA_X1_LVT i_18_13 (.A(CurrentPC[12]), .B(Instruction[31]), .CI(n_18_12), + .CO(n_18_13), .S(n_74)); + FA_X1_LVT i_18_14 (.A(n_18_0), .B(n_18_1), .CI(n_18_13), .CO(n_18_14), + .S(n_75)); + FA_X1_LVT i_18_15 (.A(CurrentPC[14]), .B(n_18_1), .CI(n_18_14), .CO(n_18_15), + .S(n_76)); + FA_X1_LVT i_18_16 (.A(CurrentPC[15]), .B(n_18_1), .CI(n_18_15), .CO(n_18_16), + .S(n_77)); + FA_X1_LVT i_18_17 (.A(CurrentPC[16]), .B(n_18_1), .CI(n_18_16), .CO(n_18_17), + .S(n_78)); + FA_X1_LVT i_18_18 (.A(CurrentPC[17]), .B(n_18_1), .CI(n_18_17), .CO(n_18_18), + .S(n_79)); + FA_X1_LVT i_18_19 (.A(CurrentPC[18]), .B(n_18_1), .CI(n_18_18), .CO(n_18_19), + .S(n_80)); + FA_X1_LVT i_18_20 (.A(CurrentPC[19]), .B(n_18_1), .CI(n_18_19), .CO(n_18_20), + .S(n_81)); + FA_X1_LVT i_18_21 (.A(CurrentPC[20]), .B(n_18_1), .CI(n_18_20), .CO(n_18_21), + .S(n_82)); + FA_X1_LVT i_18_22 (.A(CurrentPC[21]), .B(n_18_1), .CI(n_18_21), .CO(n_18_22), + .S(n_83)); + FA_X1_LVT i_18_23 (.A(CurrentPC[22]), .B(n_18_1), .CI(n_18_22), .CO(n_18_23), + .S(n_84)); + FA_X1_LVT i_18_24 (.A(CurrentPC[23]), .B(n_18_1), .CI(n_18_23), .CO(n_18_24), + .S(n_85)); + FA_X1_LVT i_18_25 (.A(CurrentPC[24]), .B(n_18_1), .CI(n_18_24), .CO(n_18_25), + .S(n_86)); + FA_X1_LVT i_18_26 (.A(CurrentPC[25]), .B(n_18_1), .CI(n_18_25), .CO(n_18_26), + .S(n_87)); + FA_X1_LVT i_18_27 (.A(CurrentPC[26]), .B(n_18_1), .CI(n_18_26), .CO(n_18_27), + .S(n_88)); + FA_X1_LVT i_18_28 (.A(CurrentPC[27]), .B(n_18_1), .CI(n_18_27), .CO(n_18_28), + .S(n_89)); + FA_X1_LVT i_18_29 (.A(CurrentPC[28]), .B(n_18_1), .CI(n_18_28), .CO(n_18_29), + .S(n_90)); + FA_X1_LVT i_18_30 (.A(CurrentPC[29]), .B(n_18_1), .CI(n_18_29), .CO(n_18_30), + .S(n_91)); + FA_X1_LVT i_18_31 (.A(CurrentPC[30]), .B(n_18_1), .CI(n_18_30), .CO(n_18_31), + .S(n_92)); + XNOR2_X1_LVT i_18_33 (.A(n_18_32), .B(n_18_31), .ZN(n_93)); + INV_X1_LVT i_0_350 (.A(Instruction[3]), .ZN(n_0_243)); + NAND3_X1_LVT i_0_343 (.A1(n_0_243), .A2(Instruction[0]), .A3(Instruction[1]), + .ZN(n_0_238)); + OR2_X1_LVT i_0_332 (.A1(n_0_238), .A2(Instruction[2]), .ZN(n_0_228)); + INV_X1_LVT i_0_351 (.A(Instruction[5]), .ZN(n_0_244)); + NOR2_X1_LVT i_0_340 (.A1(n_0_244), .A2(Instruction[4]), .ZN(n_0_235)); + NAND2_X1_LVT i_0_329 (.A1(Instruction[6]), .A2(n_0_235), .ZN(n_0_225)); + INV_X1_LVT i_0_354 (.A(Instruction[13]), .ZN(n_0_247)); + NOR2_X1_LVT i_0_345 (.A1(n_0_247), .A2(Instruction[14]), .ZN(n_0_240)); + NOR3_X1_LVT i_0_118 (.A1(n_0_228), .A2(n_0_225), .A3(n_0_240), .ZN(n_0_99)); + NAND3_X1_LVT i_0_346 (.A1(Instruction[0]), .A2(Instruction[1]), .A3( + Instruction[2]), .ZN(n_0_241)); + NOR2_X1_LVT i_0_328 (.A1(n_0_241), .A2(n_0_225), .ZN(n_0_224)); + INV_X1_LVT i_0_356 (.A(n_0_224), .ZN(n_0_249)); + NOR2_X1_LVT i_0_108 (.A1(n_0_243), .A2(n_0_249), .ZN(n_0_91)); + INV_X1_LVT i_17_1 (.A(CurrentPC[21]), .ZN(n_17_1)); + XNOR2_X1_LVT i_17_32 (.A(CurrentPC[31]), .B(n_17_1), .ZN(n_17_32)); + INV_X1_LVT i_17_0 (.A(Instruction[31]), .ZN(n_17_0)); + HA_X1_LVT i_17_2 (.A(Instruction[21]), .B(CurrentPC[1]), .CO(n_17_2), + .S(n_32)); + FA_X1_LVT i_17_3 (.A(Instruction[22]), .B(CurrentPC[2]), .CI(n_17_2), + .CO(n_17_3), .S(n_33)); + FA_X1_LVT i_17_4 (.A(Instruction[23]), .B(CurrentPC[3]), .CI(n_17_3), + .CO(n_17_4), .S(n_34)); + FA_X1_LVT i_17_5 (.A(Instruction[24]), .B(CurrentPC[4]), .CI(n_17_4), + .CO(n_17_5), .S(n_35)); + FA_X1_LVT i_17_6 (.A(Instruction[25]), .B(CurrentPC[5]), .CI(n_17_5), + .CO(n_17_6), .S(n_36)); + FA_X1_LVT i_17_7 (.A(Instruction[26]), .B(CurrentPC[6]), .CI(n_17_6), + .CO(n_17_7), .S(n_37)); + FA_X1_LVT i_17_8 (.A(Instruction[27]), .B(CurrentPC[7]), .CI(n_17_7), + .CO(n_17_8), .S(n_38)); + FA_X1_LVT i_17_9 (.A(Instruction[28]), .B(CurrentPC[8]), .CI(n_17_8), + .CO(n_17_9), .S(n_39)); + FA_X1_LVT i_17_10 (.A(Instruction[29]), .B(CurrentPC[9]), .CI(n_17_9), + .CO(n_17_10), .S(n_40)); + FA_X1_LVT i_17_11 (.A(Instruction[30]), .B(CurrentPC[10]), .CI(n_17_10), + .CO(n_17_11), .S(n_41)); + FA_X1_LVT i_17_12 (.A(Instruction[20]), .B(CurrentPC[11]), .CI(n_17_11), + .CO(n_17_12), .S(n_42)); + FA_X1_LVT i_17_13 (.A(Instruction[12]), .B(CurrentPC[12]), .CI(n_17_12), + .CO(n_17_13), .S(n_43)); + FA_X1_LVT i_17_14 (.A(Instruction[13]), .B(CurrentPC[13]), .CI(n_17_13), + .CO(n_17_14), .S(n_44)); + FA_X1_LVT i_17_15 (.A(Instruction[14]), .B(CurrentPC[14]), .CI(n_17_14), + .CO(n_17_15), .S(n_45)); + FA_X1_LVT i_17_16 (.A(Instruction[15]), .B(CurrentPC[15]), .CI(n_17_15), + .CO(n_17_16), .S(n_46)); + FA_X1_LVT i_17_17 (.A(Instruction[16]), .B(CurrentPC[16]), .CI(n_17_16), + .CO(n_17_17), .S(n_47)); + FA_X1_LVT i_17_18 (.A(Instruction[17]), .B(CurrentPC[17]), .CI(n_17_17), + .CO(n_17_18), .S(n_48)); + FA_X1_LVT i_17_19 (.A(Instruction[18]), .B(CurrentPC[18]), .CI(n_17_18), + .CO(n_17_19), .S(n_49)); + FA_X1_LVT i_17_20 (.A(Instruction[19]), .B(CurrentPC[19]), .CI(n_17_19), + .CO(n_17_20), .S(n_50)); + FA_X1_LVT i_17_21 (.A(CurrentPC[20]), .B(Instruction[31]), .CI(n_17_20), + .CO(n_17_21), .S(n_51)); + FA_X1_LVT i_17_22 (.A(n_17_0), .B(n_17_1), .CI(n_17_21), .CO(n_17_22), + .S(n_52)); + FA_X1_LVT i_17_23 (.A(CurrentPC[22]), .B(n_17_1), .CI(n_17_22), .CO(n_17_23), + .S(n_53)); + FA_X1_LVT i_17_24 (.A(CurrentPC[23]), .B(n_17_1), .CI(n_17_23), .CO(n_17_24), + .S(n_54)); + FA_X1_LVT i_17_25 (.A(CurrentPC[24]), .B(n_17_1), .CI(n_17_24), .CO(n_17_25), + .S(n_55)); + FA_X1_LVT i_17_26 (.A(CurrentPC[25]), .B(n_17_1), .CI(n_17_25), .CO(n_17_26), + .S(n_56)); + FA_X1_LVT i_17_27 (.A(CurrentPC[26]), .B(n_17_1), .CI(n_17_26), .CO(n_17_27), + .S(n_57)); + FA_X1_LVT i_17_28 (.A(CurrentPC[27]), .B(n_17_1), .CI(n_17_27), .CO(n_17_28), + .S(n_58)); + FA_X1_LVT i_17_29 (.A(CurrentPC[28]), .B(n_17_1), .CI(n_17_28), .CO(n_17_29), + .S(n_59)); + FA_X1_LVT i_17_30 (.A(CurrentPC[29]), .B(n_17_1), .CI(n_17_29), .CO(n_17_30), + .S(n_60)); + FA_X1_LVT i_17_31 (.A(CurrentPC[30]), .B(n_17_1), .CI(n_17_30), .CO(n_17_31), + .S(n_61)); + XNOR2_X1_LVT i_17_33 (.A(n_17_32), .B(n_17_31), .ZN(n_62)); + INV_X1_LVT i_5_1 (.A(RRs1[12]), .ZN(n_5_1)); + XNOR2_X1_LVT i_5_33 (.A(RRs1[31]), .B(n_5_1), .ZN(n_5_33)); + INV_X1_LVT i_5_0 (.A(Instruction[31]), .ZN(n_5_0)); + HA_X1_LVT i_5_2 (.A(Instruction[20]), .B(RRs1[0]), .CO(n_5_2), .S(n_0)); + FA_X1_LVT i_5_3 (.A(Instruction[21]), .B(RRs1[1]), .CI(n_5_2), .CO(n_5_3), + .S(n_1)); + FA_X1_LVT i_5_4 (.A(Instruction[22]), .B(RRs1[2]), .CI(n_5_3), .CO(n_5_4), + .S(n_2)); + FA_X1_LVT i_5_5 (.A(Instruction[23]), .B(RRs1[3]), .CI(n_5_4), .CO(n_5_5), + .S(n_3)); + FA_X1_LVT i_5_6 (.A(Instruction[24]), .B(RRs1[4]), .CI(n_5_5), .CO(n_5_6), + .S(n_4)); + FA_X1_LVT i_5_7 (.A(Instruction[25]), .B(RRs1[5]), .CI(n_5_6), .CO(n_5_7), + .S(n_5)); + FA_X1_LVT i_5_8 (.A(Instruction[26]), .B(RRs1[6]), .CI(n_5_7), .CO(n_5_8), + .S(n_6)); + FA_X1_LVT i_5_9 (.A(Instruction[27]), .B(RRs1[7]), .CI(n_5_8), .CO(n_5_9), + .S(n_7)); + FA_X1_LVT i_5_10 (.A(Instruction[28]), .B(RRs1[8]), .CI(n_5_9), .CO(n_5_10), + .S(n_8)); + FA_X1_LVT i_5_11 (.A(Instruction[29]), .B(RRs1[9]), .CI(n_5_10), .CO(n_5_11), + .S(n_9)); + FA_X1_LVT i_5_12 (.A(Instruction[30]), .B(RRs1[10]), .CI(n_5_11), .CO(n_5_12), + .S(n_10)); + FA_X1_LVT i_5_13 (.A(RRs1[11]), .B(Instruction[31]), .CI(n_5_12), .CO(n_5_13), + .S(n_11)); + FA_X1_LVT i_5_14 (.A(n_5_0), .B(n_5_1), .CI(n_5_13), .CO(n_5_14), .S(n_12)); + FA_X1_LVT i_5_15 (.A(RRs1[13]), .B(n_5_1), .CI(n_5_14), .CO(n_5_15), .S(n_13)); + FA_X1_LVT i_5_16 (.A(RRs1[14]), .B(n_5_1), .CI(n_5_15), .CO(n_5_16), .S(n_14)); + FA_X1_LVT i_5_17 (.A(RRs1[15]), .B(n_5_1), .CI(n_5_16), .CO(n_5_17), .S(n_15)); + FA_X1_LVT i_5_18 (.A(RRs1[16]), .B(n_5_1), .CI(n_5_17), .CO(n_5_18), .S(n_16)); + FA_X1_LVT i_5_19 (.A(RRs1[17]), .B(n_5_1), .CI(n_5_18), .CO(n_5_19), .S(n_17)); + FA_X1_LVT i_5_20 (.A(RRs1[18]), .B(n_5_1), .CI(n_5_19), .CO(n_5_20), .S(n_18)); + FA_X1_LVT i_5_21 (.A(RRs1[19]), .B(n_5_1), .CI(n_5_20), .CO(n_5_21), .S(n_19)); + FA_X1_LVT i_5_22 (.A(RRs1[20]), .B(n_5_1), .CI(n_5_21), .CO(n_5_22), .S(n_20)); + FA_X1_LVT i_5_23 (.A(RRs1[21]), .B(n_5_1), .CI(n_5_22), .CO(n_5_23), .S(n_21)); + FA_X1_LVT i_5_24 (.A(RRs1[22]), .B(n_5_1), .CI(n_5_23), .CO(n_5_24), .S(n_22)); + FA_X1_LVT i_5_25 (.A(RRs1[23]), .B(n_5_1), .CI(n_5_24), .CO(n_5_25), .S(n_23)); + FA_X1_LVT i_5_26 (.A(RRs1[24]), .B(n_5_1), .CI(n_5_25), .CO(n_5_26), .S(n_24)); + FA_X1_LVT i_5_27 (.A(RRs1[25]), .B(n_5_1), .CI(n_5_26), .CO(n_5_27), .S(n_25)); + FA_X1_LVT i_5_28 (.A(RRs1[26]), .B(n_5_1), .CI(n_5_27), .CO(n_5_28), .S(n_26)); + FA_X1_LVT i_5_29 (.A(RRs1[27]), .B(n_5_1), .CI(n_5_28), .CO(n_5_29), .S(n_27)); + FA_X1_LVT i_5_30 (.A(RRs1[28]), .B(n_5_1), .CI(n_5_29), .CO(n_5_30), .S(n_28)); + FA_X1_LVT i_5_31 (.A(RRs1[29]), .B(n_5_1), .CI(n_5_30), .CO(n_5_31), .S(n_29)); + FA_X1_LVT i_5_32 (.A(RRs1[30]), .B(n_5_1), .CI(n_5_31), .CO(n_5_32), .S(n_30)); + XNOR2_X1_LVT i_5_34 (.A(n_5_33), .B(n_5_32), .ZN(n_31)); + NOR2_X1_LVT i_0_107 (.A1(n_0_249), .A2(Instruction[3]), .ZN(n_0_90)); + AOI222_X1_LVT i_0_106 (.A1(n_93), .A2(n_0_99), .B1(n_0_91), .B2(n_62), + .C1(n_31), .C2(n_0_90), .ZN(n_0_89)); + INV_X1_LVT i_0_355 (.A(Instruction[6]), .ZN(n_0_248)); + NAND2_X1_LVT i_0_339 (.A1(n_0_248), .A2(Instruction[4]), .ZN(n_0_234)); + INV_X1_LVT i_0_338 (.A(n_0_234), .ZN(n_0_233)); + OAI21_X1_LVT i_0_341 (.A(Instruction[13]), .B1(Instruction[14]), .B2( + Instruction[12]), .ZN(n_0_236)); + AOI211_X1_LVT i_0_337 (.A(n_0_235), .B(n_0_233), .C1(n_0_248), .C2(n_0_236), + .ZN(n_0_232)); + INV_X1_LVT i_0_352 (.A(Instruction[4]), .ZN(n_0_245)); + NAND2_X1_LVT i_0_344 (.A1(n_0_245), .A2(Instruction[2]), .ZN(n_0_239)); + AOI21_X1_LVT i_0_335 (.A(Instruction[6]), .B1(n_0_243), .B2(n_0_239), + .ZN(n_0_230)); + NOR2_X1_LVT i_0_334 (.A1(n_0_232), .A2(n_0_230), .ZN(n_0_229)); + NAND2_X1_LVT i_0_342 (.A1(n_0_241), .A2(n_0_238), .ZN(n_0_237)); + NAND2_X1_LVT i_0_336 (.A1(Instruction[6]), .A2(n_0_240), .ZN(n_0_231)); + OAI211_X1_LVT i_0_333 (.A(n_0_229), .B(n_0_237), .C1(Instruction[2]), + .C2(n_0_231), .ZN(Illegal)); + NAND2_X1_LVT i_0_109 (.A1(Illegal), .A2(CurrentPC[31]), .ZN(n_0_92)); + NAND2_X1_LVT i_0_105 (.A1(n_0_89), .A2(n_0_92), .ZN(JumpOrBranchPC[31])); + AOI222_X1_LVT i_0_103 (.A1(n_92), .A2(n_0_99), .B1(n_0_91), .B2(n_61), + .C1(n_30), .C2(n_0_90), .ZN(n_0_87)); + NAND2_X1_LVT i_0_104 (.A1(Illegal), .A2(CurrentPC[30]), .ZN(n_0_88)); + NAND2_X1_LVT i_0_102 (.A1(n_0_87), .A2(n_0_88), .ZN(JumpOrBranchPC[30])); + AOI222_X1_LVT i_0_100 (.A1(n_91), .A2(n_0_99), .B1(n_0_91), .B2(n_60), + .C1(n_29), .C2(n_0_90), .ZN(n_0_85)); + NAND2_X1_LVT i_0_101 (.A1(Illegal), .A2(CurrentPC[29]), .ZN(n_0_86)); + NAND2_X1_LVT i_0_99 (.A1(n_0_85), .A2(n_0_86), .ZN(JumpOrBranchPC[29])); + AOI222_X1_LVT i_0_97 (.A1(n_90), .A2(n_0_99), .B1(n_0_91), .B2(n_59), + .C1(n_28), .C2(n_0_90), .ZN(n_0_83)); + NAND2_X1_LVT i_0_98 (.A1(Illegal), .A2(CurrentPC[28]), .ZN(n_0_84)); + NAND2_X1_LVT i_0_96 (.A1(n_0_83), .A2(n_0_84), .ZN(JumpOrBranchPC[28])); + AOI222_X1_LVT i_0_94 (.A1(n_89), .A2(n_0_99), .B1(n_0_91), .B2(n_58), + .C1(n_27), .C2(n_0_90), .ZN(n_0_81)); + NAND2_X1_LVT i_0_95 (.A1(Illegal), .A2(CurrentPC[27]), .ZN(n_0_82)); + NAND2_X1_LVT i_0_93 (.A1(n_0_81), .A2(n_0_82), .ZN(JumpOrBranchPC[27])); + AOI222_X1_LVT i_0_91 (.A1(n_88), .A2(n_0_99), .B1(n_0_91), .B2(n_57), + .C1(n_26), .C2(n_0_90), .ZN(n_0_79)); + NAND2_X1_LVT i_0_92 (.A1(Illegal), .A2(CurrentPC[26]), .ZN(n_0_80)); + NAND2_X1_LVT i_0_90 (.A1(n_0_79), .A2(n_0_80), .ZN(JumpOrBranchPC[26])); + AOI222_X1_LVT i_0_88 (.A1(n_87), .A2(n_0_99), .B1(n_0_91), .B2(n_56), + .C1(n_25), .C2(n_0_90), .ZN(n_0_77)); + NAND2_X1_LVT i_0_89 (.A1(Illegal), .A2(CurrentPC[25]), .ZN(n_0_78)); + NAND2_X1_LVT i_0_87 (.A1(n_0_77), .A2(n_0_78), .ZN(JumpOrBranchPC[25])); + AOI222_X1_LVT i_0_85 (.A1(n_86), .A2(n_0_99), .B1(n_0_91), .B2(n_55), + .C1(n_24), .C2(n_0_90), .ZN(n_0_75)); + NAND2_X1_LVT i_0_86 (.A1(Illegal), .A2(CurrentPC[24]), .ZN(n_0_76)); + NAND2_X1_LVT i_0_84 (.A1(n_0_75), .A2(n_0_76), .ZN(JumpOrBranchPC[24])); + AOI222_X1_LVT i_0_82 (.A1(n_85), .A2(n_0_99), .B1(n_0_91), .B2(n_54), + .C1(n_23), .C2(n_0_90), .ZN(n_0_73)); + NAND2_X1_LVT i_0_83 (.A1(Illegal), .A2(CurrentPC[23]), .ZN(n_0_74)); + NAND2_X1_LVT i_0_81 (.A1(n_0_73), .A2(n_0_74), .ZN(JumpOrBranchPC[23])); + AOI222_X1_LVT i_0_79 (.A1(n_84), .A2(n_0_99), .B1(n_0_91), .B2(n_53), + .C1(n_22), .C2(n_0_90), .ZN(n_0_71)); + NAND2_X1_LVT i_0_80 (.A1(Illegal), .A2(CurrentPC[22]), .ZN(n_0_72)); + NAND2_X1_LVT i_0_78 (.A1(n_0_71), .A2(n_0_72), .ZN(JumpOrBranchPC[22])); + AOI222_X1_LVT i_0_76 (.A1(n_83), .A2(n_0_99), .B1(n_0_91), .B2(n_52), + .C1(n_21), .C2(n_0_90), .ZN(n_0_69)); + NAND2_X1_LVT i_0_77 (.A1(Illegal), .A2(CurrentPC[21]), .ZN(n_0_70)); + NAND2_X1_LVT i_0_75 (.A1(n_0_69), .A2(n_0_70), .ZN(JumpOrBranchPC[21])); + AOI222_X1_LVT i_0_73 (.A1(n_82), .A2(n_0_99), .B1(n_0_91), .B2(n_51), + .C1(n_20), .C2(n_0_90), .ZN(n_0_67)); + NAND2_X1_LVT i_0_74 (.A1(Illegal), .A2(CurrentPC[20]), .ZN(n_0_68)); + NAND2_X1_LVT i_0_72 (.A1(n_0_67), .A2(n_0_68), .ZN(JumpOrBranchPC[20])); + AOI222_X1_LVT i_0_70 (.A1(n_81), .A2(n_0_99), .B1(n_0_91), .B2(n_50), + .C1(n_19), .C2(n_0_90), .ZN(n_0_65)); + NAND2_X1_LVT i_0_71 (.A1(Illegal), .A2(CurrentPC[19]), .ZN(n_0_66)); + NAND2_X1_LVT i_0_69 (.A1(n_0_65), .A2(n_0_66), .ZN(JumpOrBranchPC[19])); + AOI222_X1_LVT i_0_67 (.A1(n_80), .A2(n_0_99), .B1(n_0_91), .B2(n_49), + .C1(n_18), .C2(n_0_90), .ZN(n_0_63)); + NAND2_X1_LVT i_0_68 (.A1(Illegal), .A2(CurrentPC[18]), .ZN(n_0_64)); + NAND2_X1_LVT i_0_66 (.A1(n_0_63), .A2(n_0_64), .ZN(JumpOrBranchPC[18])); + AOI222_X1_LVT i_0_64 (.A1(n_79), .A2(n_0_99), .B1(n_0_91), .B2(n_48), + .C1(n_17), .C2(n_0_90), .ZN(n_0_61)); + NAND2_X1_LVT i_0_65 (.A1(Illegal), .A2(CurrentPC[17]), .ZN(n_0_62)); + NAND2_X1_LVT i_0_63 (.A1(n_0_61), .A2(n_0_62), .ZN(JumpOrBranchPC[17])); + AOI222_X1_LVT i_0_61 (.A1(n_78), .A2(n_0_99), .B1(n_0_91), .B2(n_47), + .C1(n_16), .C2(n_0_90), .ZN(n_0_59)); + NAND2_X1_LVT i_0_62 (.A1(Illegal), .A2(CurrentPC[16]), .ZN(n_0_60)); + NAND2_X1_LVT i_0_60 (.A1(n_0_59), .A2(n_0_60), .ZN(JumpOrBranchPC[16])); + AOI222_X1_LVT i_0_58 (.A1(n_77), .A2(n_0_99), .B1(n_0_91), .B2(n_46), + .C1(n_15), .C2(n_0_90), .ZN(n_0_57)); + NAND2_X1_LVT i_0_59 (.A1(Illegal), .A2(CurrentPC[15]), .ZN(n_0_58)); + NAND2_X1_LVT i_0_57 (.A1(n_0_57), .A2(n_0_58), .ZN(JumpOrBranchPC[15])); + AOI222_X1_LVT i_0_55 (.A1(n_76), .A2(n_0_99), .B1(n_0_91), .B2(n_45), + .C1(n_14), .C2(n_0_90), .ZN(n_0_55)); + NAND2_X1_LVT i_0_56 (.A1(Illegal), .A2(CurrentPC[14]), .ZN(n_0_56)); + NAND2_X1_LVT i_0_54 (.A1(n_0_55), .A2(n_0_56), .ZN(JumpOrBranchPC[14])); + AOI222_X1_LVT i_0_52 (.A1(n_75), .A2(n_0_99), .B1(n_0_91), .B2(n_44), + .C1(n_13), .C2(n_0_90), .ZN(n_0_53)); + NAND2_X1_LVT i_0_53 (.A1(Illegal), .A2(CurrentPC[13]), .ZN(n_0_54)); + NAND2_X1_LVT i_0_51 (.A1(n_0_53), .A2(n_0_54), .ZN(JumpOrBranchPC[13])); + AOI222_X1_LVT i_0_49 (.A1(n_74), .A2(n_0_99), .B1(n_0_91), .B2(n_43), + .C1(n_12), .C2(n_0_90), .ZN(n_0_51)); + NAND2_X1_LVT i_0_50 (.A1(Illegal), .A2(CurrentPC[12]), .ZN(n_0_52)); + NAND2_X1_LVT i_0_48 (.A1(n_0_51), .A2(n_0_52), .ZN(JumpOrBranchPC[12])); + AOI222_X1_LVT i_0_46 (.A1(n_73), .A2(n_0_99), .B1(n_0_91), .B2(n_42), + .C1(n_11), .C2(n_0_90), .ZN(n_0_49)); + NAND2_X1_LVT i_0_47 (.A1(Illegal), .A2(CurrentPC[11]), .ZN(n_0_50)); + NAND2_X1_LVT i_0_45 (.A1(n_0_49), .A2(n_0_50), .ZN(JumpOrBranchPC[11])); + AOI222_X1_LVT i_0_43 (.A1(n_72), .A2(n_0_99), .B1(n_0_91), .B2(n_41), + .C1(n_10), .C2(n_0_90), .ZN(n_0_47)); + NAND2_X1_LVT i_0_44 (.A1(Illegal), .A2(CurrentPC[10]), .ZN(n_0_48)); + NAND2_X1_LVT i_0_42 (.A1(n_0_47), .A2(n_0_48), .ZN(JumpOrBranchPC[10])); + AOI222_X1_LVT i_0_40 (.A1(n_71), .A2(n_0_99), .B1(n_0_91), .B2(n_40), + .C1(n_9), .C2(n_0_90), .ZN(n_0_45)); + NAND2_X1_LVT i_0_41 (.A1(Illegal), .A2(CurrentPC[9]), .ZN(n_0_46)); + NAND2_X1_LVT i_0_39 (.A1(n_0_45), .A2(n_0_46), .ZN(JumpOrBranchPC[9])); + AOI222_X1_LVT i_0_37 (.A1(n_70), .A2(n_0_99), .B1(n_0_91), .B2(n_39), + .C1(n_8), .C2(n_0_90), .ZN(n_0_43)); + NAND2_X1_LVT i_0_38 (.A1(Illegal), .A2(CurrentPC[8]), .ZN(n_0_44)); + NAND2_X1_LVT i_0_36 (.A1(n_0_43), .A2(n_0_44), .ZN(JumpOrBranchPC[8])); + AOI222_X1_LVT i_0_34 (.A1(n_69), .A2(n_0_99), .B1(n_0_91), .B2(n_38), + .C1(n_7), .C2(n_0_90), .ZN(n_0_41)); + NAND2_X1_LVT i_0_35 (.A1(Illegal), .A2(CurrentPC[7]), .ZN(n_0_42)); + NAND2_X1_LVT i_0_33 (.A1(n_0_41), .A2(n_0_42), .ZN(JumpOrBranchPC[7])); + AOI222_X1_LVT i_0_31 (.A1(n_68), .A2(n_0_99), .B1(n_0_91), .B2(n_37), + .C1(n_6), .C2(n_0_90), .ZN(n_0_39)); + NAND2_X1_LVT i_0_32 (.A1(Illegal), .A2(CurrentPC[6]), .ZN(n_0_40)); + NAND2_X1_LVT i_0_30 (.A1(n_0_39), .A2(n_0_40), .ZN(JumpOrBranchPC[6])); + AOI222_X1_LVT i_0_28 (.A1(n_67), .A2(n_0_99), .B1(n_0_91), .B2(n_36), + .C1(n_5), .C2(n_0_90), .ZN(n_0_37)); + NAND2_X1_LVT i_0_29 (.A1(Illegal), .A2(CurrentPC[5]), .ZN(n_0_38)); + NAND2_X1_LVT i_0_27 (.A1(n_0_37), .A2(n_0_38), .ZN(JumpOrBranchPC[5])); + AOI222_X1_LVT i_0_25 (.A1(n_66), .A2(n_0_99), .B1(n_0_91), .B2(n_35), + .C1(n_4), .C2(n_0_90), .ZN(n_0_35)); + NAND2_X1_LVT i_0_26 (.A1(Illegal), .A2(CurrentPC[4]), .ZN(n_0_36)); + NAND2_X1_LVT i_0_24 (.A1(n_0_35), .A2(n_0_36), .ZN(JumpOrBranchPC[4])); + AOI222_X1_LVT i_0_22 (.A1(n_65), .A2(n_0_99), .B1(n_0_91), .B2(n_34), + .C1(n_3), .C2(n_0_90), .ZN(n_0_33)); + NAND2_X1_LVT i_0_23 (.A1(Illegal), .A2(CurrentPC[3]), .ZN(n_0_34)); + NAND2_X1_LVT i_0_21 (.A1(n_0_33), .A2(n_0_34), .ZN(JumpOrBranchPC[3])); + AOI222_X1_LVT i_0_19 (.A1(n_64), .A2(n_0_99), .B1(n_0_91), .B2(n_33), + .C1(n_2), .C2(n_0_90), .ZN(n_0_31)); + NAND2_X1_LVT i_0_20 (.A1(Illegal), .A2(CurrentPC[2]), .ZN(n_0_32)); + NAND2_X1_LVT i_0_18 (.A1(n_0_31), .A2(n_0_32), .ZN(JumpOrBranchPC[2])); + AOI222_X1_LVT i_0_16 (.A1(n_63), .A2(n_0_99), .B1(n_0_91), .B2(n_32), + .C1(n_1), .C2(n_0_90), .ZN(n_0_29)); + NAND2_X1_LVT i_0_17 (.A1(Illegal), .A2(CurrentPC[1]), .ZN(n_0_30)); + NAND2_X1_LVT i_0_15 (.A1(n_0_29), .A2(n_0_30), .ZN(JumpOrBranchPC[1])); + NOR2_X1_LVT i_0_112 (.A1(n_0_232), .A2(n_0_238), .ZN(n_0_94)); + OAI221_X1_LVT i_0_14 (.A(n_0_94), .B1(n_0_225), .B2(Instruction[2]), .C1( + Instruction[6]), .C2(n_0_239), .ZN(n_0_28)); + AND2_X1_LVT i_0_13 (.A1(n_0_28), .A2(CurrentPC[0]), .ZN(JumpOrBranchPC[0])); + NOR2_X1_LVT i_0_221 (.A1(Instruction[13]), .A2(Instruction[14]), .ZN(n_0_166)); + NOR3_X1_LVT i_0_293 (.A1(n_0_241), .A2(n_0_234), .A3(Instruction[3]), + .ZN(n_0_206)); + AND2_X1_LVT i_0_292 (.A1(n_0_206), .A2(n_0_244), .ZN(n_0_205)); + NOR3_X1_LVT i_0_330 (.A1(n_0_248), .A2(n_0_244), .A3(Instruction[4]), + .ZN(n_0_226)); + AOI21_X1_LVT i_0_121 (.A(n_0_205), .B1(n_0_226), .B2(n_0_237), .ZN(n_0_100)); + AND2_X1_LVT i_0_120 (.A1(Instruction[14]), .A2(n_0_100), .ZN(aluOp[2])); + OAI33_X1_LVT i_0_119 (.A1(n_0_205), .A2(n_0_247), .A3(n_0_224), .B1( + Instruction[2]), .B2(n_0_238), .B3(n_0_225), .ZN(aluOp[1])); + AOI22_X1_LVT i_0_117 (.A1(Instruction[12]), .A2(n_0_100), .B1(n_0_99), + .B2(Instruction[13]), .ZN(n_0_98)); + INV_X1_LVT i_0_116 (.A(n_0_98), .ZN(aluOp[0])); + OR2_X1_LVT i_0_327 (.A1(n_0_238), .A2(n_0_234), .ZN(n_0_223)); + NOR4_X1_LVT i_0_125 (.A1(Instruction[28]), .A2(Instruction[27]), .A3( + Instruction[26]), .A4(Instruction[25]), .ZN(n_0_103)); + INV_X1_LVT i_0_347 (.A(Instruction[30]), .ZN(n_0_242)); + NOR4_X1_LVT i_0_124 (.A1(Instruction[13]), .A2(n_0_242), .A3(Instruction[29]), + .A4(Instruction[31]), .ZN(n_0_102)); + NAND2_X1_LVT i_0_123 (.A1(n_0_103), .A2(n_0_102), .ZN(n_0_101)); + NOR3_X1_LVT i_0_127 (.A1(n_0_244), .A2(Instruction[12]), .A3(Instruction[14]), + .ZN(n_0_105)); + AOI21_X1_LVT i_0_126 (.A(n_0_105), .B1(Instruction[12]), .B2(Instruction[14]), + .ZN(n_0_104)); + NOR4_X1_LVT i_0_122 (.A1(n_0_223), .A2(n_0_101), .A3(n_0_104), .A4( + Instruction[2]), .ZN(aluNegAr)); + OR3_X1_LVT i_0_325 (.A1(n_0_228), .A2(Instruction[4]), .A3(Instruction[6]), + .ZN(n_0_222)); + NOR2_X1_LVT i_0_321 (.A1(n_0_222), .A2(Instruction[5]), .ZN(n_0_221)); + NOR3_X1_LVT i_0_224 (.A1(n_0_224), .A2(n_0_221), .A3(n_0_206), .ZN(n_0_169)); + NOR3_X1_LVT i_0_129 (.A1(n_0_234), .A2(Instruction[3]), .A3(Instruction[5]), + .ZN(n_0_106)); + NOR3_X1_LVT i_0_128 (.A1(n_0_226), .A2(n_0_169), .A3(n_0_106), .ZN(aluBypass)); + AOI22_X1_LVT i_0_223 (.A1(CurrentPC[31]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[31]), .ZN(n_0_168)); + NOR3_X1_LVT i_0_219 (.A1(n_0_247), .A2(n_0_222), .A3(Instruction[5]), + .ZN(n_0_164)); + AOI22_X1_LVT i_0_218 (.A1(RRs1[31]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[31]), .ZN(n_0_163)); + MUX2_X1_LVT i_0_222 (.A(RData[7]), .B(RData[15]), .S(Instruction[12]), + .Z(n_0_167)); + NAND3_X1_LVT i_0_220 (.A1(n_0_221), .A2(n_0_167), .A3(n_0_166), .ZN(n_0_165)); + NAND3_X1_LVT i_0_217 (.A1(n_0_168), .A2(n_0_163), .A3(n_0_165), .ZN(op1[31])); + AOI22_X1_LVT i_0_216 (.A1(RRs1[30]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[30]), .ZN(n_0_162)); + AOI22_X1_LVT i_0_215 (.A1(CurrentPC[30]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[30]), .ZN(n_0_161)); + NAND3_X1_LVT i_0_214 (.A1(n_0_162), .A2(n_0_161), .A3(n_0_165), .ZN(op1[30])); + AOI22_X1_LVT i_0_213 (.A1(RRs1[29]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[29]), .ZN(n_0_160)); + AOI22_X1_LVT i_0_212 (.A1(CurrentPC[29]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[29]), .ZN(n_0_159)); + NAND3_X1_LVT i_0_211 (.A1(n_0_160), .A2(n_0_159), .A3(n_0_165), .ZN(op1[29])); + AOI22_X1_LVT i_0_210 (.A1(RRs1[28]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[28]), .ZN(n_0_158)); + AOI22_X1_LVT i_0_209 (.A1(CurrentPC[28]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[28]), .ZN(n_0_157)); + NAND3_X1_LVT i_0_208 (.A1(n_0_158), .A2(n_0_157), .A3(n_0_165), .ZN(op1[28])); + AOI22_X1_LVT i_0_207 (.A1(RRs1[27]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[27]), .ZN(n_0_156)); + AOI22_X1_LVT i_0_206 (.A1(CurrentPC[27]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[27]), .ZN(n_0_155)); + NAND3_X1_LVT i_0_205 (.A1(n_0_156), .A2(n_0_155), .A3(n_0_165), .ZN(op1[27])); + AOI22_X1_LVT i_0_204 (.A1(RRs1[26]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[26]), .ZN(n_0_154)); + AOI22_X1_LVT i_0_203 (.A1(CurrentPC[26]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[26]), .ZN(n_0_153)); + NAND3_X1_LVT i_0_202 (.A1(n_0_154), .A2(n_0_153), .A3(n_0_165), .ZN(op1[26])); + AOI22_X1_LVT i_0_201 (.A1(RRs1[25]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[25]), .ZN(n_0_152)); + AOI22_X1_LVT i_0_200 (.A1(CurrentPC[25]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[25]), .ZN(n_0_151)); + NAND3_X1_LVT i_0_199 (.A1(n_0_152), .A2(n_0_151), .A3(n_0_165), .ZN(op1[25])); + AOI22_X1_LVT i_0_198 (.A1(RRs1[24]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[24]), .ZN(n_0_150)); + AOI22_X1_LVT i_0_197 (.A1(CurrentPC[24]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[24]), .ZN(n_0_149)); + NAND3_X1_LVT i_0_196 (.A1(n_0_150), .A2(n_0_149), .A3(n_0_165), .ZN(op1[24])); + AOI22_X1_LVT i_0_195 (.A1(RRs1[23]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[23]), .ZN(n_0_148)); + AOI22_X1_LVT i_0_194 (.A1(CurrentPC[23]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[23]), .ZN(n_0_147)); + NAND3_X1_LVT i_0_193 (.A1(n_0_148), .A2(n_0_147), .A3(n_0_165), .ZN(op1[23])); + AOI22_X1_LVT i_0_192 (.A1(RRs1[22]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[22]), .ZN(n_0_146)); + AOI22_X1_LVT i_0_191 (.A1(CurrentPC[22]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[22]), .ZN(n_0_145)); + NAND3_X1_LVT i_0_190 (.A1(n_0_146), .A2(n_0_145), .A3(n_0_165), .ZN(op1[22])); + AOI22_X1_LVT i_0_189 (.A1(RRs1[21]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[21]), .ZN(n_0_144)); + AOI22_X1_LVT i_0_188 (.A1(CurrentPC[21]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[21]), .ZN(n_0_143)); + NAND3_X1_LVT i_0_187 (.A1(n_0_144), .A2(n_0_143), .A3(n_0_165), .ZN(op1[21])); + AOI22_X1_LVT i_0_186 (.A1(RRs1[20]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[20]), .ZN(n_0_142)); + AOI22_X1_LVT i_0_185 (.A1(CurrentPC[20]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[20]), .ZN(n_0_141)); + NAND3_X1_LVT i_0_184 (.A1(n_0_142), .A2(n_0_141), .A3(n_0_165), .ZN(op1[20])); + AOI22_X1_LVT i_0_183 (.A1(RRs1[19]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[19]), .ZN(n_0_140)); + AOI22_X1_LVT i_0_182 (.A1(CurrentPC[19]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[19]), .ZN(n_0_139)); + NAND3_X1_LVT i_0_181 (.A1(n_0_140), .A2(n_0_139), .A3(n_0_165), .ZN(op1[19])); + AOI22_X1_LVT i_0_180 (.A1(RRs1[18]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[18]), .ZN(n_0_138)); + AOI22_X1_LVT i_0_179 (.A1(CurrentPC[18]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[18]), .ZN(n_0_137)); + NAND3_X1_LVT i_0_178 (.A1(n_0_138), .A2(n_0_137), .A3(n_0_165), .ZN(op1[18])); + AOI22_X1_LVT i_0_177 (.A1(RRs1[17]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[17]), .ZN(n_0_136)); + AOI22_X1_LVT i_0_176 (.A1(CurrentPC[17]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[17]), .ZN(n_0_135)); + NAND3_X1_LVT i_0_175 (.A1(n_0_136), .A2(n_0_135), .A3(n_0_165), .ZN(op1[17])); + AOI22_X1_LVT i_0_174 (.A1(RRs1[16]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[16]), .ZN(n_0_134)); + AOI22_X1_LVT i_0_173 (.A1(CurrentPC[16]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[16]), .ZN(n_0_133)); + NAND3_X1_LVT i_0_172 (.A1(n_0_134), .A2(n_0_133), .A3(n_0_165), .ZN(op1[16])); + AOI222_X1_LVT i_0_169 (.A1(CurrentPC[15]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[15]), .C1(n_0_169), .C2(RRs1[15]), .ZN(n_0_130)); + INV_X1_LVT i_0_353 (.A(Instruction[12]), .ZN(n_0_246)); + AOI211_X1_LVT i_0_171 (.A(Instruction[5]), .B(n_0_222), .C1(n_0_247), + .C2(n_0_246), .ZN(n_0_132)); + OAI211_X1_LVT i_0_170 (.A(RData[15]), .B(n_0_132), .C1(Instruction[13]), + .C2(Instruction[14]), .ZN(n_0_131)); + NAND3_X1_LVT i_0_168 (.A1(n_0_130), .A2(n_0_131), .A3(n_0_165), .ZN(op1[15])); + AOI22_X1_LVT i_0_167 (.A1(RRs1[14]), .A2(n_0_169), .B1(n_0_132), .B2( + RData[14]), .ZN(n_0_129)); + AOI22_X1_LVT i_0_166 (.A1(CurrentPC[14]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[14]), .ZN(n_0_128)); + NAND4_X1_LVT i_0_165 (.A1(n_0_221), .A2(n_0_246), .A3(RData[7]), .A4(n_0_166), + .ZN(n_0_127)); + NAND3_X1_LVT i_0_164 (.A1(n_0_129), .A2(n_0_128), .A3(n_0_127), .ZN(op1[14])); + AOI22_X1_LVT i_0_163 (.A1(RRs1[13]), .A2(n_0_169), .B1(n_0_132), .B2( + RData[13]), .ZN(n_0_126)); + AOI22_X1_LVT i_0_162 (.A1(CurrentPC[13]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[13]), .ZN(n_0_125)); + NAND3_X1_LVT i_0_161 (.A1(n_0_126), .A2(n_0_125), .A3(n_0_127), .ZN(op1[13])); + AOI22_X1_LVT i_0_160 (.A1(RRs1[12]), .A2(n_0_169), .B1(n_0_132), .B2( + RData[12]), .ZN(n_0_124)); + AOI22_X1_LVT i_0_159 (.A1(CurrentPC[12]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[12]), .ZN(n_0_123)); + NAND3_X1_LVT i_0_158 (.A1(n_0_124), .A2(n_0_123), .A3(n_0_127), .ZN(op1[12])); + AOI22_X1_LVT i_0_156 (.A1(CurrentPC[11]), .A2(n_0_224), .B1(n_0_132), + .B2(RData[11]), .ZN(n_0_121)); + NAND2_X1_LVT i_0_157 (.A1(RRs1[11]), .A2(n_0_169), .ZN(n_0_122)); + NAND3_X1_LVT i_0_155 (.A1(n_0_121), .A2(n_0_122), .A3(n_0_127), .ZN(op1[11])); + AOI22_X1_LVT i_0_153 (.A1(CurrentPC[10]), .A2(n_0_224), .B1(n_0_132), + .B2(RData[10]), .ZN(n_0_119)); + NAND2_X1_LVT i_0_154 (.A1(RRs1[10]), .A2(n_0_169), .ZN(n_0_120)); + NAND3_X1_LVT i_0_152 (.A1(n_0_119), .A2(n_0_120), .A3(n_0_127), .ZN(op1[10])); + AOI22_X1_LVT i_0_150 (.A1(CurrentPC[9]), .A2(n_0_224), .B1(n_0_132), .B2( + RData[9]), .ZN(n_0_117)); + NAND2_X1_LVT i_0_151 (.A1(RRs1[9]), .A2(n_0_169), .ZN(n_0_118)); + NAND3_X1_LVT i_0_149 (.A1(n_0_117), .A2(n_0_118), .A3(n_0_127), .ZN(op1[9])); + AOI22_X1_LVT i_0_147 (.A1(CurrentPC[8]), .A2(n_0_224), .B1(n_0_132), .B2( + RData[8]), .ZN(n_0_115)); + NAND2_X1_LVT i_0_148 (.A1(RRs1[8]), .A2(n_0_169), .ZN(n_0_116)); + NAND3_X1_LVT i_0_146 (.A1(n_0_115), .A2(n_0_116), .A3(n_0_127), .ZN(op1[8])); + AOI222_X1_LVT i_0_145 (.A1(CurrentPC[7]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[7]), .C1(n_0_169), .C2(RRs1[7]), .ZN(n_0_114)); + INV_X1_LVT i_0_144 (.A(n_0_114), .ZN(op1[7])); + AOI222_X1_LVT i_0_143 (.A1(CurrentPC[6]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[6]), .C1(n_0_169), .C2(RRs1[6]), .ZN(n_0_113)); + INV_X1_LVT i_0_142 (.A(n_0_113), .ZN(op1[6])); + AOI222_X1_LVT i_0_141 (.A1(CurrentPC[5]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[5]), .C1(n_0_169), .C2(RRs1[5]), .ZN(n_0_112)); + INV_X1_LVT i_0_140 (.A(n_0_112), .ZN(op1[5])); + AOI222_X1_LVT i_0_139 (.A1(CurrentPC[4]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[4]), .C1(n_0_169), .C2(RRs1[4]), .ZN(n_0_111)); + INV_X1_LVT i_0_138 (.A(n_0_111), .ZN(op1[4])); + AOI222_X1_LVT i_0_137 (.A1(CurrentPC[3]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[3]), .C1(n_0_169), .C2(RRs1[3]), .ZN(n_0_110)); + INV_X1_LVT i_0_136 (.A(n_0_110), .ZN(op1[3])); + AOI222_X1_LVT i_0_135 (.A1(CurrentPC[2]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[2]), .C1(n_0_169), .C2(RRs1[2]), .ZN(n_0_109)); + INV_X1_LVT i_0_134 (.A(n_0_109), .ZN(op1[2])); + AOI222_X1_LVT i_0_133 (.A1(CurrentPC[1]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[1]), .C1(n_0_169), .C2(RRs1[1]), .ZN(n_0_108)); + INV_X1_LVT i_0_132 (.A(n_0_108), .ZN(op1[1])); + AOI222_X1_LVT i_0_131 (.A1(CurrentPC[0]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[0]), .C1(n_0_169), .C2(RRs1[0]), .ZN(n_0_107)); + INV_X1_LVT i_0_130 (.A(n_0_107), .ZN(op1[0])); + NOR3_X1_LVT i_0_294 (.A1(n_0_223), .A2(Instruction[2]), .A3(Instruction[5]), + .ZN(n_0_207)); + NOR3_X1_LVT i_0_291 (.A1(n_0_224), .A2(n_0_207), .A3(n_0_205), .ZN(n_0_204)); + AOI22_X1_LVT i_0_289 (.A1(CurrentPC[31]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[31]), .ZN(n_0_202)); + NAND2_X1_LVT i_0_290 (.A1(Instruction[31]), .A2(n_0_207), .ZN(n_0_203)); + NAND2_X1_LVT i_0_288 (.A1(n_0_202), .A2(n_0_203), .ZN(op2[31])); + AOI22_X1_LVT i_0_287 (.A1(CurrentPC[30]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[30]), .ZN(n_0_201)); + NAND2_X1_LVT i_0_286 (.A1(n_0_201), .A2(n_0_203), .ZN(op2[30])); + AOI22_X1_LVT i_0_285 (.A1(CurrentPC[29]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[29]), .ZN(n_0_200)); + NAND2_X1_LVT i_0_284 (.A1(n_0_200), .A2(n_0_203), .ZN(op2[29])); + AOI22_X1_LVT i_0_283 (.A1(CurrentPC[28]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[28]), .ZN(n_0_199)); + NAND2_X1_LVT i_0_282 (.A1(n_0_199), .A2(n_0_203), .ZN(op2[28])); + AOI22_X1_LVT i_0_281 (.A1(CurrentPC[27]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[27]), .ZN(n_0_198)); + NAND2_X1_LVT i_0_280 (.A1(n_0_198), .A2(n_0_203), .ZN(op2[27])); + AOI22_X1_LVT i_0_279 (.A1(CurrentPC[26]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[26]), .ZN(n_0_197)); + NAND2_X1_LVT i_0_278 (.A1(n_0_197), .A2(n_0_203), .ZN(op2[26])); + AOI22_X1_LVT i_0_277 (.A1(CurrentPC[25]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[25]), .ZN(n_0_196)); + NAND2_X1_LVT i_0_276 (.A1(n_0_196), .A2(n_0_203), .ZN(op2[25])); + AOI22_X1_LVT i_0_275 (.A1(CurrentPC[24]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[24]), .ZN(n_0_195)); + NAND2_X1_LVT i_0_274 (.A1(n_0_195), .A2(n_0_203), .ZN(op2[24])); + AOI22_X1_LVT i_0_273 (.A1(CurrentPC[23]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[23]), .ZN(n_0_194)); + NAND2_X1_LVT i_0_272 (.A1(n_0_194), .A2(n_0_203), .ZN(op2[23])); + AOI22_X1_LVT i_0_271 (.A1(CurrentPC[22]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[22]), .ZN(n_0_193)); + NAND2_X1_LVT i_0_270 (.A1(n_0_193), .A2(n_0_203), .ZN(op2[22])); + AOI22_X1_LVT i_0_269 (.A1(CurrentPC[21]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[21]), .ZN(n_0_192)); + NAND2_X1_LVT i_0_268 (.A1(n_0_192), .A2(n_0_203), .ZN(op2[21])); + AOI22_X1_LVT i_0_267 (.A1(CurrentPC[20]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[20]), .ZN(n_0_191)); + NAND2_X1_LVT i_0_266 (.A1(n_0_191), .A2(n_0_203), .ZN(op2[20])); + AOI22_X1_LVT i_0_265 (.A1(CurrentPC[19]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[19]), .ZN(n_0_190)); + NAND2_X1_LVT i_0_264 (.A1(n_0_190), .A2(n_0_203), .ZN(op2[19])); + AOI22_X1_LVT i_0_263 (.A1(CurrentPC[18]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[18]), .ZN(n_0_189)); + NAND2_X1_LVT i_0_262 (.A1(n_0_189), .A2(n_0_203), .ZN(op2[18])); + AOI22_X1_LVT i_0_261 (.A1(CurrentPC[17]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[17]), .ZN(n_0_188)); + NAND2_X1_LVT i_0_260 (.A1(n_0_188), .A2(n_0_203), .ZN(op2[17])); + AOI22_X1_LVT i_0_259 (.A1(CurrentPC[16]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[16]), .ZN(n_0_187)); + NAND2_X1_LVT i_0_258 (.A1(n_0_187), .A2(n_0_203), .ZN(op2[16])); + AOI22_X1_LVT i_0_257 (.A1(CurrentPC[15]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[15]), .ZN(n_0_186)); + NAND2_X1_LVT i_0_256 (.A1(n_0_186), .A2(n_0_203), .ZN(op2[15])); + AOI22_X1_LVT i_0_255 (.A1(CurrentPC[14]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[14]), .ZN(n_0_185)); + NAND2_X1_LVT i_0_254 (.A1(n_0_185), .A2(n_0_203), .ZN(op2[14])); + AOI22_X1_LVT i_0_253 (.A1(CurrentPC[13]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[13]), .ZN(n_0_184)); + NAND2_X1_LVT i_0_252 (.A1(n_0_184), .A2(n_0_203), .ZN(op2[13])); + AOI22_X1_LVT i_0_251 (.A1(CurrentPC[12]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[12]), .ZN(n_0_183)); + NAND2_X1_LVT i_0_250 (.A1(n_0_183), .A2(n_0_203), .ZN(op2[12])); + AOI22_X1_LVT i_0_249 (.A1(CurrentPC[11]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[11]), .ZN(n_0_182)); + NAND2_X1_LVT i_0_248 (.A1(n_0_182), .A2(n_0_203), .ZN(op2[11])); + AOI222_X1_LVT i_0_247 (.A1(Instruction[30]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[10]), .C1(n_0_204), .C2(RRs2[10]), .ZN(n_0_181)); + INV_X1_LVT i_0_246 (.A(n_0_181), .ZN(op2[10])); + AOI222_X1_LVT i_0_245 (.A1(Instruction[29]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[9]), .C1(n_0_204), .C2(RRs2[9]), .ZN(n_0_180)); + INV_X1_LVT i_0_244 (.A(n_0_180), .ZN(op2[9])); + AOI222_X1_LVT i_0_243 (.A1(Instruction[28]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[8]), .C1(n_0_204), .C2(RRs2[8]), .ZN(n_0_179)); + INV_X1_LVT i_0_242 (.A(n_0_179), .ZN(op2[8])); + AOI222_X1_LVT i_0_241 (.A1(Instruction[27]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[7]), .C1(n_0_204), .C2(RRs2[7]), .ZN(n_0_178)); + INV_X1_LVT i_0_240 (.A(n_0_178), .ZN(op2[7])); + AOI222_X1_LVT i_0_239 (.A1(Instruction[26]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[6]), .C1(n_0_204), .C2(RRs2[6]), .ZN(n_0_177)); + INV_X1_LVT i_0_238 (.A(n_0_177), .ZN(op2[6])); + AOI222_X1_LVT i_0_237 (.A1(Instruction[25]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[5]), .C1(n_0_204), .C2(RRs2[5]), .ZN(n_0_176)); + INV_X1_LVT i_0_236 (.A(n_0_176), .ZN(op2[5])); + AOI222_X1_LVT i_0_235 (.A1(Instruction[24]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[4]), .C1(n_0_204), .C2(RRs2[4]), .ZN(n_0_175)); + INV_X1_LVT i_0_234 (.A(n_0_175), .ZN(op2[4])); + AOI222_X1_LVT i_0_233 (.A1(Instruction[23]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[3]), .C1(n_0_204), .C2(RRs2[3]), .ZN(n_0_174)); + INV_X1_LVT i_0_232 (.A(n_0_174), .ZN(op2[3])); + AOI22_X1_LVT i_0_230 (.A1(Instruction[22]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[2]), .ZN(n_0_172)); + OAI21_X1_LVT i_0_231 (.A(RRs2[2]), .B1(n_0_223), .B2(Instruction[5]), + .ZN(n_0_173)); + NAND3_X1_LVT i_0_229 (.A1(n_0_172), .A2(n_0_173), .A3(n_0_249), .ZN(op2[2])); + AOI222_X1_LVT i_0_228 (.A1(Instruction[21]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[1]), .C1(n_0_204), .C2(RRs2[1]), .ZN(n_0_171)); + INV_X1_LVT i_0_227 (.A(n_0_171), .ZN(op2[1])); + AOI222_X1_LVT i_0_226 (.A1(Instruction[20]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[0]), .C1(n_0_204), .C2(RRs2[0]), .ZN(n_0_170)); + INV_X1_LVT i_0_225 (.A(n_0_170), .ZN(op2[0])); + alu theALU (.aluOp(aluOp), .aluNegAr(aluNegAr), .aluBypass(aluBypass), + .op1(op1), .op2(op2), .result(WRd), .eqFlag(eqFlag)); + XNOR2_X1_LVT i_0_115 (.A(Instruction[12]), .B(eqFlag), .ZN(n_0_97)); + XNOR2_X1_LVT i_0_114 (.A(Instruction[12]), .B(WRd[0]), .ZN(n_0_96)); + AOI22_X1_LVT i_0_113 (.A1(n_0_166), .A2(n_0_97), .B1(n_0_96), .B2( + Instruction[14]), .ZN(n_0_95)); + AOI22_X1_LVT i_0_111 (.A1(Instruction[6]), .A2(n_0_95), .B1(Instruction[2]), + .B2(n_0_245), .ZN(n_0_93)); + NAND2_X1_LVT i_0_110 (.A1(n_0_94), .A2(n_0_93), .ZN(JumpOrBranch)); + INV_X1_LVT i_0_349 (.A(Instruction[31]), .ZN(n_0_0)); + INV_X1_LVT i_0_348 (.A(RRs1[12]), .ZN(n_0_1)); + HA_X1_LVT i_0_0 (.A(Instruction[7]), .B(RRs1[0]), .CO(n_0_2), .S(n_0_15)); + FA_X1_LVT i_0_1 (.A(Instruction[8]), .B(RRs1[1]), .CI(n_0_2), .CO(n_0_3), + .S(n_0_16)); + FA_X1_LVT i_0_2 (.A(Instruction[9]), .B(RRs1[2]), .CI(n_0_3), .CO(n_0_4), + .S(n_0_17)); + FA_X1_LVT i_0_3 (.A(Instruction[10]), .B(RRs1[3]), .CI(n_0_4), .CO(n_0_5), + .S(n_0_18)); + FA_X1_LVT i_0_4 (.A(Instruction[11]), .B(RRs1[4]), .CI(n_0_5), .CO(n_0_6), + .S(n_0_19)); + FA_X1_LVT i_0_5 (.A(Instruction[25]), .B(RRs1[5]), .CI(n_0_6), .CO(n_0_7), + .S(n_0_20)); + FA_X1_LVT i_0_6 (.A(Instruction[26]), .B(RRs1[6]), .CI(n_0_7), .CO(n_0_8), + .S(n_0_21)); + FA_X1_LVT i_0_7 (.A(Instruction[27]), .B(RRs1[7]), .CI(n_0_8), .CO(n_0_9), + .S(n_0_22)); + FA_X1_LVT i_0_8 (.A(Instruction[28]), .B(RRs1[8]), .CI(n_0_9), .CO(n_0_10), + .S(n_0_23)); + FA_X1_LVT i_0_9 (.A(Instruction[29]), .B(RRs1[9]), .CI(n_0_10), .CO(n_0_11), + .S(n_0_24)); + FA_X1_LVT i_0_10 (.A(Instruction[30]), .B(RRs1[10]), .CI(n_0_11), .CO(n_0_12), + .S(n_0_25)); + FA_X1_LVT i_0_11 (.A(RRs1[11]), .B(Instruction[31]), .CI(n_0_12), .CO(n_0_13), + .S(n_0_26)); + FA_X1_LVT i_0_12 (.A(n_0_0), .B(n_0_1), .CI(n_0_13), .CO(n_0_14), .S(n_0_27)); + NOR2_X1_LVT i_0_322 (.A1(n_0_244), .A2(n_0_222), .ZN(WrMem)); + AOI22_X1_LVT i_0_320 (.A1(n_0_27), .A2(WrMem), .B1(n_0_221), .B2(n_12), + .ZN(n_0_220)); + INV_X1_LVT i_0_319 (.A(n_0_220), .ZN(DAddr[12])); + AOI22_X1_LVT i_0_318 (.A1(n_0_26), .A2(WrMem), .B1(n_0_221), .B2(n_11), + .ZN(n_0_219)); + INV_X1_LVT i_0_317 (.A(n_0_219), .ZN(DAddr[11])); + AOI22_X1_LVT i_0_316 (.A1(n_0_25), .A2(WrMem), .B1(n_0_221), .B2(n_10), + .ZN(n_0_218)); + INV_X1_LVT i_0_315 (.A(n_0_218), .ZN(DAddr[10])); + AOI22_X1_LVT i_0_314 (.A1(n_0_24), .A2(WrMem), .B1(n_0_221), .B2(n_9), + .ZN(n_0_217)); + INV_X1_LVT i_0_313 (.A(n_0_217), .ZN(DAddr[9])); + AOI22_X1_LVT i_0_312 (.A1(n_0_23), .A2(WrMem), .B1(n_0_221), .B2(n_8), + .ZN(n_0_216)); + INV_X1_LVT i_0_311 (.A(n_0_216), .ZN(DAddr[8])); + AOI22_X1_LVT i_0_310 (.A1(n_0_22), .A2(WrMem), .B1(n_0_221), .B2(n_7), + .ZN(n_0_215)); + INV_X1_LVT i_0_309 (.A(n_0_215), .ZN(DAddr[7])); + AOI22_X1_LVT i_0_308 (.A1(n_0_21), .A2(WrMem), .B1(n_0_221), .B2(n_6), + .ZN(n_0_214)); + INV_X1_LVT i_0_307 (.A(n_0_214), .ZN(DAddr[6])); + AOI22_X1_LVT i_0_306 (.A1(n_0_20), .A2(WrMem), .B1(n_0_221), .B2(n_5), + .ZN(n_0_213)); + INV_X1_LVT i_0_305 (.A(n_0_213), .ZN(DAddr[5])); + AOI22_X1_LVT i_0_304 (.A1(n_0_19), .A2(WrMem), .B1(n_0_221), .B2(n_4), + .ZN(n_0_212)); + INV_X1_LVT i_0_303 (.A(n_0_212), .ZN(DAddr[4])); + AOI22_X1_LVT i_0_302 (.A1(n_0_18), .A2(WrMem), .B1(n_0_221), .B2(n_3), + .ZN(n_0_211)); + INV_X1_LVT i_0_301 (.A(n_0_211), .ZN(DAddr[3])); + AOI22_X1_LVT i_0_300 (.A1(n_0_17), .A2(WrMem), .B1(n_0_221), .B2(n_2), + .ZN(n_0_210)); + INV_X1_LVT i_0_299 (.A(n_0_210), .ZN(DAddr[2])); + AOI22_X1_LVT i_0_298 (.A1(n_0_16), .A2(WrMem), .B1(n_0_221), .B2(n_1), + .ZN(n_0_209)); + INV_X1_LVT i_0_297 (.A(n_0_209), .ZN(DAddr[1])); + AOI22_X1_LVT i_0_296 (.A1(n_0_15), .A2(WrMem), .B1(n_0_221), .B2(n_0), + .ZN(n_0_208)); + INV_X1_LVT i_0_295 (.A(n_0_208), .ZN(DAddr[0])); + OR2_X1_LVT i_0_324 (.A1(n_0_222), .A2(Instruction[13]), .ZN(DWidth[1])); + NOR2_X1_LVT i_0_323 (.A1(n_0_246), .A2(n_0_222), .ZN(DWidth[0])); + NAND3_X1_LVT i_0_331 (.A1(n_0_248), .A2(n_0_244), .A3(n_0_236), .ZN(n_0_227)); + OAI211_X1_LVT i_0_326 (.A(n_0_249), .B(n_0_223), .C1(n_0_228), .C2(n_0_227), + .ZN(WrReg)); +endmodule + +module cpu(led, btn, clk_25mhz, scan_en, SI_1, SO_1, SI_2, SO_2, SI_3, SO_3, + SI_4, SO_4); + output [7:0]led; + input [6:0]btn; + input clk_25mhz; + input scan_en; + input SI_1; + output SO_1; + input SI_2; + output SO_2; + input SI_3; + output SO_3; + input SI_4; + output SO_4; + + wire [31:0]Instruction; + wire [31:0]RData; + wire [31:0]RRs2; + wire [31:0]RRs1; + wire WrReg; + wire [31:0]WRd; + wire [1:0]DWidth; + wire [31:0]DAddr; + wire JumpOrBranch; + wire [31:0]JumpOrBranchPC; + wire thePC_n_1; + wire thePC_i_0_n_0; + wire thePC_n_2; + wire thePC_i_0_n_1; + wire thePC_n_3; + wire thePC_i_0_n_2; + wire thePC_n_4; + wire thePC_i_0_n_3; + wire thePC_n_5; + wire thePC_i_0_n_4; + wire thePC_n_6; + wire thePC_i_0_n_5; + wire thePC_n_7; + wire thePC_i_0_n_6; + wire thePC_n_8; + wire thePC_i_0_n_7; + wire thePC_n_9; + wire thePC_i_0_n_8; + wire thePC_n_10; + wire thePC_i_0_n_9; + wire thePC_n_11; + wire thePC_i_0_n_10; + wire thePC_n_12; + wire thePC_i_0_n_11; + wire thePC_n_13; + wire thePC_i_0_n_12; + wire thePC_n_14; + wire thePC_i_0_n_13; + wire thePC_n_15; + wire thePC_i_0_n_14; + wire thePC_n_16; + wire thePC_i_0_n_15; + wire thePC_n_17; + wire thePC_i_0_n_16; + wire thePC_n_18; + wire thePC_i_0_n_17; + wire thePC_n_19; + wire thePC_i_0_n_18; + wire thePC_n_20; + wire thePC_i_0_n_19; + wire thePC_n_21; + wire thePC_i_0_n_20; + wire thePC_n_22; + wire thePC_i_0_n_21; + wire thePC_n_23; + wire thePC_i_0_n_22; + wire thePC_n_24; + wire thePC_i_0_n_23; + wire thePC_n_25; + wire thePC_i_0_n_24; + wire thePC_n_26; + wire thePC_i_0_n_25; + wire thePC_n_27; + wire thePC_i_0_n_26; + wire thePC_n_28; + wire thePC_i_0_n_27; + wire thePC_n_29; + wire thePC_n_0; + wire [31:0]CurrentPC; + wire thePC_n_30; + wire n_0_0_0; + wire thePC_n_31; + wire n_0_0_1; + wire thePC_n_32; + wire thePC_n_33; + wire thePC_n_34; + wire thePC_n_35; + wire thePC_n_36; + wire thePC_n_37; + wire thePC_n_38; + wire thePC_n_39; + wire thePC_n_40; + wire thePC_n_41; + wire thePC_n_42; + wire thePC_n_43; + wire n_0_0_2; + wire thePC_n_44; + wire n_0_0_3; + wire thePC_n_45; + wire n_0_0_4; + wire thePC_n_46; + wire n_0_0_5; + wire thePC_n_47; + wire n_0_0_6; + wire thePC_n_48; + wire n_0_0_7; + wire thePC_n_49; + wire n_0_0_8; + wire thePC_n_50; + wire n_0_0_9; + wire thePC_n_51; + wire n_0_0_10; + wire thePC_n_52; + wire n_0_0_11; + wire thePC_n_53; + wire n_0_0_12; + wire thePC_n_54; + wire n_0_0_13; + wire thePC_n_55; + wire n_0_0_14; + wire thePC_n_56; + wire n_0_0_15; + wire thePC_n_57; + wire n_0_0_16; + wire thePC_n_58; + wire n_0_0_17; + wire thePC_n_59; + wire n_0_0_18; + wire thePC_n_60; + wire n_0_0_19; + wire thePC_n_61; + wire n_0_0_20; + wire n_0_0_21; + wire n_0_0_22; + wire [31:0]NextPC; + wire reset; + + AND2_X1_LVT i_0_0_54 (.A1(JumpOrBranch), .A2(btn[0]), .ZN(n_0_0_22)); + INV_X1_LVT i_0_0_66 (.A(btn[0]), .ZN(reset)); + NOR2_X1_LVT i_0_0_53 (.A1(reset), .A2(JumpOrBranch), .ZN(n_0_0_21)); + AOI22_X1_LVT i_0_0_50 (.A1(JumpOrBranchPC[30]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_28), .ZN(n_0_0_19)); + INV_X1_LVT i_0_0_49 (.A(n_0_0_19), .ZN(thePC_n_60)); + SDFF_X1_LVT \thePC_CurrentPC_reg[30] (.D(thePC_n_60), .SE(1'b0), .SI( + CurrentPC[30]), .CK(clk_25mhz), .Q(CurrentPC[30]), .QN()); + AOI22_X1_LVT i_0_0_48 (.A1(JumpOrBranchPC[29]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_27), .ZN(n_0_0_18)); + INV_X1_LVT i_0_0_47 (.A(n_0_0_18), .ZN(thePC_n_59)); + SDFF_X1_LVT \thePC_CurrentPC_reg[29] (.D(thePC_n_59), .SE(1'b0), .SI( + CurrentPC[29]), .CK(clk_25mhz), .Q(CurrentPC[29]), .QN()); + AOI22_X1_LVT i_0_0_46 (.A1(JumpOrBranchPC[28]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_26), .ZN(n_0_0_17)); + INV_X1_LVT i_0_0_45 (.A(n_0_0_17), .ZN(thePC_n_58)); + SDFF_X1_LVT \thePC_CurrentPC_reg[28] (.D(thePC_n_58), .SE(1'b0), .SI( + CurrentPC[28]), .CK(clk_25mhz), .Q(CurrentPC[28]), .QN()); + AOI22_X1_LVT i_0_0_44 (.A1(JumpOrBranchPC[27]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_25), .ZN(n_0_0_16)); + INV_X1_LVT i_0_0_43 (.A(n_0_0_16), .ZN(thePC_n_57)); + SDFF_X1_LVT \thePC_CurrentPC_reg[27] (.D(thePC_n_57), .SE(1'b0), .SI( + CurrentPC[27]), .CK(clk_25mhz), .Q(CurrentPC[27]), .QN()); + AOI22_X1_LVT i_0_0_42 (.A1(JumpOrBranchPC[26]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_24), .ZN(n_0_0_15)); + INV_X1_LVT i_0_0_41 (.A(n_0_0_15), .ZN(thePC_n_56)); + SDFF_X1_LVT \thePC_CurrentPC_reg[26] (.D(thePC_n_56), .SE(1'b0), .SI( + CurrentPC[26]), .CK(clk_25mhz), .Q(CurrentPC[26]), .QN()); + AOI22_X1_LVT i_0_0_40 (.A1(JumpOrBranchPC[25]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_23), .ZN(n_0_0_14)); + INV_X1_LVT i_0_0_39 (.A(n_0_0_14), .ZN(thePC_n_55)); + SDFF_X1_LVT \thePC_CurrentPC_reg[25] (.D(thePC_n_55), .SE(1'b0), .SI( + CurrentPC[25]), .CK(clk_25mhz), .Q(CurrentPC[25]), .QN()); + AOI22_X1_LVT i_0_0_38 (.A1(JumpOrBranchPC[24]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_22), .ZN(n_0_0_13)); + INV_X1_LVT i_0_0_37 (.A(n_0_0_13), .ZN(thePC_n_54)); + SDFF_X1_LVT \thePC_CurrentPC_reg[24] (.D(thePC_n_54), .SE(1'b0), .SI( + CurrentPC[24]), .CK(clk_25mhz), .Q(CurrentPC[24]), .QN()); + AOI22_X1_LVT i_0_0_36 (.A1(JumpOrBranchPC[23]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_21), .ZN(n_0_0_12)); + INV_X1_LVT i_0_0_35 (.A(n_0_0_12), .ZN(thePC_n_53)); + SDFF_X1_LVT \thePC_CurrentPC_reg[23] (.D(thePC_n_53), .SE(1'b0), .SI( + CurrentPC[23]), .CK(clk_25mhz), .Q(CurrentPC[23]), .QN()); + AOI22_X1_LVT i_0_0_34 (.A1(JumpOrBranchPC[22]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_20), .ZN(n_0_0_11)); + INV_X1_LVT i_0_0_33 (.A(n_0_0_11), .ZN(thePC_n_52)); + SDFF_X1_LVT \thePC_CurrentPC_reg[22] (.D(thePC_n_52), .SE(1'b0), .SI( + CurrentPC[22]), .CK(clk_25mhz), .Q(CurrentPC[22]), .QN()); + AOI22_X1_LVT i_0_0_32 (.A1(JumpOrBranchPC[21]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_19), .ZN(n_0_0_10)); + INV_X1_LVT i_0_0_31 (.A(n_0_0_10), .ZN(thePC_n_51)); + SDFF_X1_LVT \thePC_CurrentPC_reg[21] (.D(thePC_n_51), .SE(1'b0), .SI( + CurrentPC[21]), .CK(clk_25mhz), .Q(CurrentPC[21]), .QN()); + AOI22_X1_LVT i_0_0_30 (.A1(JumpOrBranchPC[20]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_18), .ZN(n_0_0_9)); + INV_X1_LVT i_0_0_29 (.A(n_0_0_9), .ZN(thePC_n_50)); + SDFF_X1_LVT \thePC_CurrentPC_reg[20] (.D(thePC_n_50), .SE(1'b0), .SI( + CurrentPC[20]), .CK(clk_25mhz), .Q(CurrentPC[20]), .QN()); + AOI22_X1_LVT i_0_0_28 (.A1(JumpOrBranchPC[19]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_17), .ZN(n_0_0_8)); + INV_X1_LVT i_0_0_27 (.A(n_0_0_8), .ZN(thePC_n_49)); + SDFF_X1_LVT \thePC_CurrentPC_reg[19] (.D(thePC_n_49), .SE(1'b0), .SI( + CurrentPC[19]), .CK(clk_25mhz), .Q(CurrentPC[19]), .QN()); + AOI22_X1_LVT i_0_0_26 (.A1(JumpOrBranchPC[18]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_16), .ZN(n_0_0_7)); + INV_X1_LVT i_0_0_25 (.A(n_0_0_7), .ZN(thePC_n_48)); + SDFF_X1_LVT \thePC_CurrentPC_reg[18] (.D(thePC_n_48), .SE(1'b0), .SI( + CurrentPC[18]), .CK(clk_25mhz), .Q(CurrentPC[18]), .QN()); + AOI22_X1_LVT i_0_0_24 (.A1(JumpOrBranchPC[17]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_15), .ZN(n_0_0_6)); + INV_X1_LVT i_0_0_23 (.A(n_0_0_6), .ZN(thePC_n_47)); + SDFF_X1_LVT \thePC_CurrentPC_reg[17] (.D(thePC_n_47), .SE(1'b0), .SI( + CurrentPC[17]), .CK(clk_25mhz), .Q(CurrentPC[17]), .QN()); + AOI22_X1_LVT i_0_0_22 (.A1(JumpOrBranchPC[16]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_14), .ZN(n_0_0_5)); + INV_X1_LVT i_0_0_21 (.A(n_0_0_5), .ZN(thePC_n_46)); + SDFF_X1_LVT \thePC_CurrentPC_reg[16] (.D(thePC_n_46), .SE(1'b0), .SI( + CurrentPC[16]), .CK(clk_25mhz), .Q(CurrentPC[16]), .QN()); + AOI22_X1_LVT i_0_0_20 (.A1(JumpOrBranchPC[15]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_13), .ZN(n_0_0_4)); + INV_X1_LVT i_0_0_19 (.A(n_0_0_4), .ZN(thePC_n_45)); + SDFF_X1_LVT \thePC_CurrentPC_reg[15] (.D(thePC_n_45), .SE(1'b0), .SI( + CurrentPC[15]), .CK(clk_25mhz), .Q(CurrentPC[15]), .QN()); + AOI22_X1_LVT i_0_0_18 (.A1(JumpOrBranchPC[14]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_12), .ZN(n_0_0_3)); + INV_X1_LVT i_0_0_17 (.A(n_0_0_3), .ZN(thePC_n_44)); + SDFF_X1_LVT \thePC_CurrentPC_reg[14] (.D(thePC_n_44), .SE(1'b0), .SI( + CurrentPC[14]), .CK(clk_25mhz), .Q(CurrentPC[14]), .QN()); + AOI22_X1_LVT i_0_0_16 (.A1(JumpOrBranchPC[13]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_11), .ZN(n_0_0_2)); + INV_X1_LVT i_0_0_15 (.A(n_0_0_2), .ZN(thePC_n_43)); + SDFF_X1_LVT \thePC_CurrentPC_reg[13] (.D(thePC_n_43), .SE(1'b0), .SI( + CurrentPC[13]), .CK(clk_25mhz), .Q(CurrentPC[13]), .QN()); + MUX2_X1_LVT i_0_0_65 (.A(thePC_n_10), .B(JumpOrBranchPC[12]), .S(JumpOrBranch), + .Z(NextPC[12])); + AND2_X1_LVT i_0_0_14 (.A1(NextPC[12]), .A2(btn[0]), .ZN(thePC_n_42)); + SDFF_X1_LVT \thePC_CurrentPC_reg[12] (.D(thePC_n_42), .SE(1'b0), .SI( + CurrentPC[12]), .CK(clk_25mhz), .Q(CurrentPC[12]), .QN()); + MUX2_X1_LVT i_0_0_64 (.A(thePC_n_9), .B(JumpOrBranchPC[11]), .S(JumpOrBranch), + .Z(NextPC[11])); + AND2_X1_LVT i_0_0_13 (.A1(NextPC[11]), .A2(btn[0]), .ZN(thePC_n_41)); + SDFF_X1_LVT \thePC_CurrentPC_reg[11] (.D(thePC_n_41), .SE(1'b0), .SI( + CurrentPC[11]), .CK(clk_25mhz), .Q(CurrentPC[11]), .QN()); + MUX2_X1_LVT i_0_0_63 (.A(thePC_n_8), .B(JumpOrBranchPC[10]), .S(JumpOrBranch), + .Z(NextPC[10])); + AND2_X1_LVT i_0_0_12 (.A1(NextPC[10]), .A2(btn[0]), .ZN(thePC_n_40)); + SDFF_X1_LVT \thePC_CurrentPC_reg[10] (.D(thePC_n_40), .SE(1'b0), .SI( + CurrentPC[10]), .CK(clk_25mhz), .Q(CurrentPC[10]), .QN()); + MUX2_X1_LVT i_0_0_62 (.A(thePC_n_7), .B(JumpOrBranchPC[9]), .S(JumpOrBranch), + .Z(NextPC[9])); + AND2_X1_LVT i_0_0_11 (.A1(NextPC[9]), .A2(btn[0]), .ZN(thePC_n_39)); + SDFF_X1_LVT \thePC_CurrentPC_reg[9] (.D(thePC_n_39), .SE(1'b0), .SI( + CurrentPC[9]), .CK(clk_25mhz), .Q(CurrentPC[9]), .QN()); + MUX2_X1_LVT i_0_0_61 (.A(thePC_n_6), .B(JumpOrBranchPC[8]), .S(JumpOrBranch), + .Z(NextPC[8])); + AND2_X1_LVT i_0_0_10 (.A1(NextPC[8]), .A2(btn[0]), .ZN(thePC_n_38)); + SDFF_X1_LVT \thePC_CurrentPC_reg[8] (.D(thePC_n_38), .SE(1'b0), .SI( + CurrentPC[8]), .CK(clk_25mhz), .Q(CurrentPC[8]), .QN()); + AND2_X1_LVT i_0_0_9 (.A1(led[7]), .A2(btn[0]), .ZN(thePC_n_37)); + SDFF_X1_LVT \thePC_CurrentPC_reg[7] (.D(thePC_n_37), .SE(1'b0), .SI( + CurrentPC[7]), .CK(clk_25mhz), .Q(CurrentPC[7]), .QN()); + MUX2_X1_LVT i_0_0_59 (.A(thePC_n_4), .B(JumpOrBranchPC[6]), .S(JumpOrBranch), + .Z(led[6])); + AND2_X1_LVT i_0_0_8 (.A1(led[6]), .A2(btn[0]), .ZN(thePC_n_36)); + SDFF_X1_LVT \thePC_CurrentPC_reg[6] (.D(thePC_n_36), .SE(1'b0), .SI( + CurrentPC[6]), .CK(clk_25mhz), .Q(CurrentPC[6]), .QN()); + MUX2_X1_LVT i_0_0_58 (.A(thePC_n_3), .B(JumpOrBranchPC[5]), .S(JumpOrBranch), + .Z(led[5])); + AND2_X1_LVT i_0_0_7 (.A1(led[5]), .A2(btn[0]), .ZN(thePC_n_35)); + SDFF_X1_LVT \thePC_CurrentPC_reg[5] (.D(thePC_n_35), .SE(1'b0), .SI( + CurrentPC[5]), .CK(clk_25mhz), .Q(CurrentPC[5]), .QN()); + MUX2_X1_LVT i_0_0_57 (.A(thePC_n_2), .B(JumpOrBranchPC[4]), .S(JumpOrBranch), + .Z(led[4])); + AND2_X1_LVT i_0_0_6 (.A1(led[4]), .A2(btn[0]), .ZN(thePC_n_34)); + SDFF_X1_LVT \thePC_CurrentPC_reg[4] (.D(thePC_n_34), .SE(1'b0), .SI( + CurrentPC[4]), .CK(clk_25mhz), .Q(CurrentPC[4]), .QN()); + MUX2_X1_LVT i_0_0_56 (.A(thePC_n_1), .B(JumpOrBranchPC[3]), .S(JumpOrBranch), + .Z(led[3])); + AND2_X1_LVT i_0_0_5 (.A1(led[3]), .A2(btn[0]), .ZN(thePC_n_33)); + SDFF_X1_LVT \thePC_CurrentPC_reg[3] (.D(thePC_n_33), .SE(1'b0), .SI( + CurrentPC[3]), .CK(clk_25mhz), .Q(CurrentPC[3]), .QN()); + INV_X1_LVT thePC_i_0_29 (.A(CurrentPC[2]), .ZN(thePC_n_0)); + MUX2_X1_LVT i_0_0_55 (.A(thePC_n_0), .B(JumpOrBranchPC[2]), .S(JumpOrBranch), + .Z(led[2])); + AND2_X1_LVT i_0_0_4 (.A1(led[2]), .A2(btn[0]), .ZN(thePC_n_32)); + SDFF_X1_LVT \thePC_CurrentPC_reg[2] (.D(thePC_n_32), .SE(1'b0), .SI( + CurrentPC[2]), .CK(clk_25mhz), .Q(CurrentPC[2]), .QN()); + HA_X1_LVT thePC_i_0_0 (.A(CurrentPC[3]), .B(CurrentPC[2]), .CO(thePC_i_0_n_0), + .S(thePC_n_1)); + HA_X1_LVT thePC_i_0_1 (.A(CurrentPC[4]), .B(thePC_i_0_n_0), .CO(thePC_i_0_n_1), + .S(thePC_n_2)); + HA_X1_LVT thePC_i_0_2 (.A(CurrentPC[5]), .B(thePC_i_0_n_1), .CO(thePC_i_0_n_2), + .S(thePC_n_3)); + HA_X1_LVT thePC_i_0_3 (.A(CurrentPC[6]), .B(thePC_i_0_n_2), .CO(thePC_i_0_n_3), + .S(thePC_n_4)); + HA_X1_LVT thePC_i_0_4 (.A(CurrentPC[7]), .B(thePC_i_0_n_3), .CO(thePC_i_0_n_4), + .S(thePC_n_5)); + HA_X1_LVT thePC_i_0_5 (.A(CurrentPC[8]), .B(thePC_i_0_n_4), .CO(thePC_i_0_n_5), + .S(thePC_n_6)); + HA_X1_LVT thePC_i_0_6 (.A(CurrentPC[9]), .B(thePC_i_0_n_5), .CO(thePC_i_0_n_6), + .S(thePC_n_7)); + HA_X1_LVT thePC_i_0_7 (.A(CurrentPC[10]), .B(thePC_i_0_n_6), .CO( + thePC_i_0_n_7), .S(thePC_n_8)); + HA_X1_LVT thePC_i_0_8 (.A(CurrentPC[11]), .B(thePC_i_0_n_7), .CO( + thePC_i_0_n_8), .S(thePC_n_9)); + HA_X1_LVT thePC_i_0_9 (.A(CurrentPC[12]), .B(thePC_i_0_n_8), .CO( + thePC_i_0_n_9), .S(thePC_n_10)); + HA_X1_LVT thePC_i_0_11 (.A(CurrentPC[13]), .B(thePC_i_0_n_9), .CO( + thePC_i_0_n_10), .S(thePC_n_11)); + HA_X1_LVT thePC_i_0_12 (.A(CurrentPC[14]), .B(thePC_i_0_n_10), .CO( + thePC_i_0_n_11), .S(thePC_n_12)); + HA_X1_LVT thePC_i_0_13 (.A(CurrentPC[15]), .B(thePC_i_0_n_11), .CO( + thePC_i_0_n_12), .S(thePC_n_13)); + HA_X1_LVT thePC_i_0_14 (.A(CurrentPC[16]), .B(thePC_i_0_n_12), .CO( + thePC_i_0_n_13), .S(thePC_n_14)); + HA_X1_LVT thePC_i_0_15 (.A(CurrentPC[17]), .B(thePC_i_0_n_13), .CO( + thePC_i_0_n_14), .S(thePC_n_15)); + HA_X1_LVT thePC_i_0_16 (.A(CurrentPC[18]), .B(thePC_i_0_n_14), .CO( + thePC_i_0_n_15), .S(thePC_n_16)); + HA_X1_LVT thePC_i_0_17 (.A(CurrentPC[19]), .B(thePC_i_0_n_15), .CO( + thePC_i_0_n_16), .S(thePC_n_17)); + HA_X1_LVT thePC_i_0_10 (.A(CurrentPC[20]), .B(thePC_i_0_n_16), .CO( + thePC_i_0_n_17), .S(thePC_n_18)); + HA_X1_LVT thePC_i_0_18 (.A(CurrentPC[21]), .B(thePC_i_0_n_17), .CO( + thePC_i_0_n_18), .S(thePC_n_19)); + HA_X1_LVT thePC_i_0_19 (.A(CurrentPC[22]), .B(thePC_i_0_n_18), .CO( + thePC_i_0_n_19), .S(thePC_n_20)); + HA_X1_LVT thePC_i_0_20 (.A(CurrentPC[23]), .B(thePC_i_0_n_19), .CO( + thePC_i_0_n_20), .S(thePC_n_21)); + HA_X1_LVT thePC_i_0_21 (.A(CurrentPC[24]), .B(thePC_i_0_n_20), .CO( + thePC_i_0_n_21), .S(thePC_n_22)); + HA_X1_LVT thePC_i_0_22 (.A(CurrentPC[25]), .B(thePC_i_0_n_21), .CO( + thePC_i_0_n_22), .S(thePC_n_23)); + HA_X1_LVT thePC_i_0_23 (.A(CurrentPC[26]), .B(thePC_i_0_n_22), .CO( + thePC_i_0_n_23), .S(thePC_n_24)); + HA_X1_LVT thePC_i_0_24 (.A(CurrentPC[27]), .B(thePC_i_0_n_23), .CO( + thePC_i_0_n_24), .S(thePC_n_25)); + HA_X1_LVT thePC_i_0_25 (.A(CurrentPC[28]), .B(thePC_i_0_n_24), .CO( + thePC_i_0_n_25), .S(thePC_n_26)); + HA_X1_LVT thePC_i_0_26 (.A(CurrentPC[29]), .B(thePC_i_0_n_25), .CO( + thePC_i_0_n_26), .S(thePC_n_27)); + HA_X1_LVT thePC_i_0_27 (.A(CurrentPC[30]), .B(thePC_i_0_n_26), .CO( + thePC_i_0_n_27), .S(thePC_n_28)); + XOR2_X1_LVT thePC_i_0_28 (.A(CurrentPC[31]), .B(thePC_i_0_n_27), .Z( + thePC_n_29)); + AOI22_X1_LVT i_0_0_52 (.A1(JumpOrBranchPC[31]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_29), .ZN(n_0_0_20)); + INV_X1_LVT i_0_0_51 (.A(n_0_0_20), .ZN(thePC_n_61)); + SDFF_X1_LVT \thePC_CurrentPC_reg[31] (.D(thePC_n_61), .SE(1'b0), .SI( + CurrentPC[31]), .CK(clk_25mhz), .Q(CurrentPC[31]), .QN()); + AOI22_X1_LVT i_0_0_3 (.A1(JumpOrBranchPC[1]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(CurrentPC[1]), .ZN(n_0_0_1)); + INV_X1_LVT i_0_0_2 (.A(n_0_0_1), .ZN(thePC_n_31)); + SDFF_X1_LVT \thePC_CurrentPC_reg[1] (.D(thePC_n_31), .SE(1'b0), .SI( + CurrentPC[1]), .CK(clk_25mhz), .Q(CurrentPC[1]), .QN()); + AOI22_X1_LVT i_0_0_1 (.A1(JumpOrBranchPC[0]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(CurrentPC[0]), .ZN(n_0_0_0)); + INV_X1_LVT i_0_0_0 (.A(n_0_0_0), .ZN(thePC_n_30)); + SDFF_X1_LVT \thePC_CurrentPC_reg[0] (.D(thePC_n_30), .SE(1'b0), .SI( + CurrentPC[0]), .CK(clk_25mhz), .Q(CurrentPC[0]), .QN()); + reg_file theRegisters (.Rs1({Instruction[19], Instruction[18], + Instruction[17], Instruction[16], Instruction[15]}), .Rs2({Instruction[24], + Instruction[23], Instruction[22], Instruction[21], Instruction[20]}), + .Rd({Instruction[11], Instruction[10], Instruction[9], Instruction[8], + Instruction[7]}), .RRs1(RRs1), .RRs2(RRs2), .WRd(WRd), .WrReg(WrReg), + .reset(reset), .clk(clk_25mhz), .dftIn(scan_en)); + main_mem theMem (.clk(clk_25mhz), .reset(reset), .DAddr({uc_0, uc_1, uc_2, + uc_3, uc_4, uc_5, uc_6, uc_7, uc_8, uc_9, uc_10, uc_11, uc_12, uc_13, + uc_14, uc_15, uc_16, uc_17, uc_18, DAddr[12], DAddr[11], DAddr[10], + DAddr[9], DAddr[8], DAddr[7], DAddr[6], DAddr[5], DAddr[4], DAddr[3], + DAddr[2], DAddr[1], DAddr[0]}), .IAddr({uc_19, uc_20, uc_21, uc_22, uc_23, + uc_24, uc_25, uc_26, uc_27, uc_28, uc_29, uc_30, uc_31, uc_32, uc_33, + uc_34, uc_35, uc_36, uc_37, NextPC[12], NextPC[11], NextPC[10], NextPC[9], + NextPC[8], led[7], led[6], led[5], led[4], led[3], led[2], uc_38, uc_39}), + .DWData(RRs2), .DRData(RData), .IRData(Instruction), .DWE(led[1]), + .DWidth(DWidth)); + decoder theDecoder (.CurrentPC(CurrentPC), .JumpOrBranchPC(JumpOrBranchPC), + .JumpOrBranch(JumpOrBranch), .DAddr({uc_40, uc_41, uc_42, uc_43, uc_44, + uc_45, uc_46, uc_47, uc_48, uc_49, uc_50, uc_51, uc_52, uc_53, uc_54, + uc_55, uc_56, uc_57, uc_58, DAddr[12], DAddr[11], DAddr[10], DAddr[9], + DAddr[8], DAddr[7], DAddr[6], DAddr[5], DAddr[4], DAddr[3], DAddr[2], + DAddr[1], DAddr[0]}), .WData(), .RData(RData), .Instruction(Instruction), + .WrMem(led[1]), .DWidth(DWidth), .Rs1(), .Rs2(), .Rd(), .RRs1(RRs1), + .RRs2(RRs2), .WRd(WRd), .WrReg(WrReg), .Illegal(led[0])); + MUX2_X1_LVT i_0_0_60 (.A(thePC_n_5), .B(JumpOrBranchPC[7]), .S(JumpOrBranch), + .Z(led[7])); +endmodule diff --git a/oasys.tessent.02/Scan_0/post_scan.v b/oasys.tessent.02/Scan_0/post_scan.v new file mode 100644 index 0000000..87c8a8a --- /dev/null +++ b/oasys.tessent.02/Scan_0/post_scan.v @@ -0,0 +1,15792 @@ +/* Generated by Tessent Shell 2023.4-p1 at Fri May 29 09:12:39 CEST 2026 */ +module alu(aluOp, aluNegAr, aluBypass, op1, op2, result, eqFlag); + input [31:0] op1, op2; + input [2:0] aluOp; + input aluNegAr, aluBypass; + output [31:0] result; + output eqFlag; + + wire n_9_0, n_9_1, n_9_2, n_9_3, n_9_4, n_9_5, n_9_6, n_9_7, n_9_8, n_9_9, + n_9_10, n_9_11, n_9_12, n_9_13, n_9_14, n_9_15, n_9_16, n_9_17, n_9_18, + n_9_19, n_9_20, n_9_21, n_9_22, n_9_23, n_9_24, n_9_25, n_9_26, n_9_27, + n_9_28, n_9_29, n_9_30, n_9_31, n_10_0, n_10_1, n_10_2, n_10_3, n_10_4, + n_10_5, n_10_6, n_10_7, n_10_8, n_10_9, n_10_10, n_10_11, n_10_12, + n_10_13, n_10_14, n_10_15, n_10_16, n_10_17, n_10_18, n_10_19, n_10_20, + n_10_21, n_10_22, n_10_23, n_10_24, n_10_25, n_10_26, n_10_27, n_10_28, + n_10_29, n_10_30, n_10_31, n_10_32, n_10_33, n_10_34, n_10_35, n_10_36, + n_10_37, n_10_38, n_10_39, n_10_40, n_10_41, n_10_42, n_10_43, n_10_44, + n_10_45, n_10_46, n_10_47, n_10_48, n_10_49, n_10_50, n_10_51, n_10_52, + n_10_53, n_10_54, n_10_55, n_10_56, n_10_57, n_10_58, n_10_59, n_10_60, + n_10_61, n_10_62, n_10_63, n_10_64, n_10_65, n_10_66, n_10_67, n_10_68, + n_10_69, n_10_70, n_10_71, n_10_72, n_10_73, n_10_74, n_10_75, n_10_76, + n_10_77, n_10_78, n_10_79, n_10_80, n_10_81, n_10_82, n_10_83, n_10_84, + n_10_85, n_10_86, n_10_87, n_10_88, n_10_89, n_10_90, n_10_91, n_10_92, + n_10_93, n_10_94, n_10_95, n_10_96, n_10_97, n_10_98, n_10_99, n_10_100, + n_10_101, n_10_102, n_10_103, n_10_104, n_10_105, n_10_106, n_10_107, + n_10_108, n_10_109, n_10_110, n_10_111, n_10_112, n_10_113, n_10_114, + n_10_115, n_10_116, n_10_117, n_10_118, n_10_119, n_10_120, n_10_121, + n_10_122, n_10_123, n_0_0, n_0_1, n_0_2, n_0_3, n_0_4, n_0_5, n_0_6, + n_0_7, n_0_8, n_0_9, n_0_10, n_0_11, n_0_12, n_0_13, n_0_14, n_0_15, + n_0_16, n_0_17, n_0_18, n_0_19, n_0_20, n_0_21, n_0_22, n_0_23, n_0_24, + n_0_25, n_0_26, n_0_27, n_0_28, n_0_29, n_0_30, n_0_31, n_0_32, n_0_33, + n_0_34, n_0_35, n_0_36, n_0_37, n_0_38, n_0_39, n_0_40, n_0_41, n_0_42, + n_0_43, n_0_44, n_0_45, n_0_46, n_0_47, n_0_48, n_0_49, n_0_50, n_0_51, + n_0_52, n_0_53, n_0_54, n_0_55, n_0_56, n_0_57, n_0_58, n_0_59, n_0_60, + n_0_61, n_0_62, n_0_63, n_0_64, n_0_65, n_0_66, n_0_67, n_0_68, n_0_69, + n_0_70, n_0_71, n_0_72, n_0_73, n_0_74, n_0_75, n_0_76, n_0_77, n_0_78, + n_0_79, n_0_80, n_0_81, n_0_82, n_0_83, n_0_84, n_0_85, n_0_86, n_0_87, + n_0_88, n_0_89, n_0_90, n_0_91, n_0_92, n_0_93, n_0_94, n_0_95, n_0_96, + n_0_97, n_0_98, n_0_99, n_0_100, n_0_101, n_0_102, n_0_103, n_0_104, + n_0_105, n_0_106, n_0_107, n_0_108, n_0_109, n_0_110, n_0_111, n_0_112, + n_0_113, n_0_114, n_0_115, n_0_116, n_0_117, n_0_118, n_0_119, n_0_120, + n_0_121, n_0_122, n_0_123, n_0_124, n_0_125, n_0_126, n_0_127, n_0_128, + n_0_129, n_0_130, n_0_131, n_0_132, n_0_133, n_0_134, n_0_135, n_0_136, + n_0_137, n_0_138, n_0_139, n_0_140, n_0_141, n_0_142, n_0_143, n_0_144, + n_0_145, n_0_146, n_0_147, n_0_148, n_0_149, n_0_150, n_0_151, n_0_152, + n_0_153, n_0_154, n_0_155, n_0_156, n_0_157, n_0_158, n_0_159, n_0_160, + n_0_161, n_0_162, n_0_163, n_0_164, n_0_165, n_0_166, n_0_167, n_0_168, + n_0_169, n_0_170, n_0_171, n_0_172, n_0_173, n_0_174, n_0_175, n_0_176, + n_0_177, n_0_178, n_0_179, n_0_180, n_0_181, n_0_182, n_0_183, n_0_184, + n_0_185, n_0_186, n_0_187, n_0_188, n_0_189, n_0_190, n_0_191, n_0_192, + n_0_193, n_0_194, n_0_195, n_0_196, n_0_197, n_0_198, n_0_199, n_0_200, + n_0_201, n_0_202, n_0_203, n_0_204, n_0_205, n_0_206, n_0_207, n_0_208, + n_0_209, n_0_210, n_0_211, n_0_212, n_0_213, n_0_214, n_0_215, n_0_216, + n_0_217, n_0_218, n_0_219, n_0_220, n_0_221, n_0_222, n_0_223, n_0_224, + n_0_225, n_0_226, n_0_227, n_0_228, n_0_229, n_0_230, n_0_231, n_0_232, + n_0_233, n_0_234, n_0_235, n_0_236, n_0_237, n_0_238, n_0_239, n_0_240, + n_0_241, n_0_242, n_0_243, n_0_244, n_0_245, n_0_246, n_0_247, n_0_248, + n_0_249, n_0_250, n_0_251, n_0_252, n_0_253, n_0_254, n_0_255, n_0_256, + n_0_257, n_0_258, n_0_259, n_0_260, n_0_261, n_0_262, n_0_263, n_0_264, + n_0_265, n_0_266, n_0_267, n_0_268, n_0_269, n_0_270, n_0_271, n_0_272, + n_0_273, n_0_274, n_0_275, n_0_276, n_0_277, n_0_278, n_0_279, n_0_280, + n_0_281, n_0_282, n_0_283, n_0_284, n_0_285, n_0_286, n_0_287, n_0_288, + n_0_289, n_0_290, n_0_291, n_0_292, n_0_293, n_0_294, n_0_295, n_0_296, + n_0_297, n_0_298, n_0_299, n_0_300, n_0_301, n_0_302, n_0_303, n_0_304, + n_0_305, n_0_306, n_0_307, n_0_308, n_0_309, n_0_310, n_0_311, n_0_312, + n_0_313, n_0_314, n_0_315, n_0_316, n_0_317, n_0_318, n_0_319, n_0_320, + n_0_321, n_0_322, n_0_323, n_0_324, n_0_325, n_0_326, n_0_327, n_0_328, + n_0_329, n_0_330, n_0_331, n_0_332, n_0_333, n_0_334, n_0_335, n_0_336, + n_0_337, n_0_338, n_0_339, n_0_340, n_0_341, n_0_342, n_0_343, n_0_344, + n_0_345, n_0_346, n_0_347, n_0_348, n_0_349, n_0_350, n_0_351, n_0_352, + n_0_353, n_0_354, n_0_355, n_0_356, n_0_357, n_0_358, n_0_359, n_0_360, + n_0_361, n_0_362, n_0_363, n_0_364, n_0_365, n_0_366, n_0_367, n_0_368, + n_0_369, n_0_370, n_0_371, n_0_372, n_0_373, n_0_374, n_0_375, n_0_376, + n_0_377, n_0_378, n_0_379, n_0_380, n_0_381, n_0_382, n_0_383, n_0_384, + n_0_385, n_0_386, n_0_387, n_0_388, n_0_389, n_0_390, n_0_391, n_0_392, + n_0_393, n_0_394, n_0_395, n_0_396, n_0_397, n_0_398, n_0_399, n_0_400, + n_0_401, n_0_402, n_0_403, n_0_404, n_0_405, n_0_406, n_0_407, n_0_408, + n_0_409, n_0_410, n_0_411, n_0_412, n_0_413, n_0_414, n_0_415, n_0_416, + n_0_417, n_0_418, n_0_419, n_0_420, n_0_421, n_0_422, n_0_423, n_0_424, + n_0_425, n_0_426, n_0_427, n_0_428, n_0_429, n_0_430, n_0_431, n_0_432, + n_0_433, n_0_434, n_0_435, n_0_436, n_0_437, n_0_438, n_0_439, n_0_440, + n_0_441, n_0_442, n_0_443, n_0_444, n_0_445, n_0_446, n_0_447, n_0_448, + n_0_449, n_0_450, n_0_451, n_0_452, n_0_453, n_0_454, n_0_455, n_0_456, + n_0_457, n_0_458, n_0_459, n_0_460, n_0_461, n_0_462, n_0_463, n_0_464, + n_0_465, n_0_466, n_0_467, n_0_468, n_0_469, n_0_470, n_0_471, n_0_472, + n_0_473, n_0_474, n_0_475, n_0_476, n_0_477, n_0_478, n_0_479, n_0_480, + n_0_481, n_0_482, n_0_483, n_0_484, n_0_485, n_0_486, n_0_487, n_0_488, + n_0_489, n_0_490, n_0_491, n_0_492, n_0_493, n_0_494, n_0_495, n_0_496, + n_0_497, n_0_498, n_0_499, n_0_500, n_0_501, n_0_502, n_0_503, n_0_504, + n_0_505, n_0_506, n_0_507, n_0_508, n_0_509, n_0_510, n_0_511, n_0_512, + n_0_513, n_0_514, n_0_515, n_0_516, n_0_517, n_0_518, n_0_519, n_0_520, + n_0_521, n_0_522, n_0_523, n_0_524, n_0_525, n_0_526, n_0_527, n_0_528, + n_0_529, n_0_530, n_0_531, n_0_532, n_0_533, n_0_534, n_0_535, n_0_536, + n_0_537, n_0_538, n_0_539, n_0_540, n_0_541, n_0_542, n_0_543, n_0_544, + n_0_545, n_0_546, n_0_547, n_0_548, n_0_549, n_0_550, n_0_551, n_0_552, + n_0_553, n_0_554, n_0_555, n_0_556, n_0_557, n_0_558, n_0_559, n_0_560, + n_0_561, n_0_562, n_0_563, n_0_564, n_0_565, n_0_566, n_0_567, n_0_568, + n_0_569, n_0_570, n_0_571, n_0_572, n_0_573, n_0_574, n_0_575, n_0_576, + n_0_577, n_0_578, n_0_579, n_0_580, n_0_581, n_0_582, n_0_583, n_0_584, + n_0_585, n_0_586, n_0_587, n_0_588, n_0_589, n_0_590, n_0_591, n_0_592, + n_0_593, n_0_594, n_0_595, n_0_596, n_0_597, n_0_598, n_0_599, n_0_600, + n_0_601, n_0_602, n_0_603, n_0_604, n_0_605, n_0_606, n_0_607, n_0_608, + n_0_609, n_0_610, n_0_611, n_0_612, n_0_613, n_0_614, n_0_615, n_0_616, + n_0_617, n_0_618, n_0_619, n_0_620, n_0_621, n_0_622, n_0_623, n_0_624, + n_0_625, n_0_626, n_0_627, n_0_628, n_0_629, n_0_630, n_0_631, n_0_632, + n_0_633, n_0_634, n_0_635, n_0_636, n_0_637, n_0_638, n_0_639, n_0_640, + n_0_641, n_0_642, n_0_643, n_0_644, n_0_645, n_0_646, n_0_647, n_0_648, + n_0_649, n_0_650, n_0_651, n_0_652, n_0_653, n_0_654, n_0_655, n_0_656, + n_0_657, n_0_658, n_0_659, n_0_660, n_0_661, n_0_662, n_0_663, n_0_664, + n_0_665, n_0_666, n_0_667, n_0_668, n_0_669, n_0_670, n_0_671, n_0_672, + n_0_673, n_0_674, n_0_675, n_0_676, n_0_677, n_0_678, n_0_679, n_0_680, + n_0_681, n_0_682, n_0_683, n_0_684, n_0_685, n_0_686, n_0_687, n_0_688, + n_0_689, n_0_690, n_0_691, n_0_692, n_0_693, n_0_694, n_0_695, n_0_696, + n_0_697, n_0_698, n_0_699, n_0_700, n_0_701, n_0_702, n_0_703, n_0_704, + n_0_705, n_0_706, n_0_707, n_0_708, n_0_709, n_0_710, n_0_711, n_0_712, + n_0_713, n_0_714, n_0_715, n_0_716, n_0_717, n_0_718, n_0_719, n_0_720, + n_0_721, n_0_722, n_0_723, n_0_724, n_0_725, n_0_726, n_0_727, n_0_728, + n_0_729, n_0_730, n_0_731, n_0_732, n_0_733, n_0_734, n_0_735, n_0_736, + n_0_737, n_0_738, n_0_739, n_0_740, n_0, n_1, n_2, n_3, n_4, n_5, n_6, + n_7, n_8, n_9, n_10, n_11, n_12, n_13, n_14, n_15, n_16, n_17, n_18, + n_19, n_20, n_21, n_22, n_23, n_24, n_25, n_26, n_27, n_28, n_29, n_30, + n_31, n_63, n_62, n_61, n_60, n_59, n_58, n_57, n_56, n_55, n_54, n_53, + n_52, n_51, n_50, n_49, n_48, n_47, n_46, n_45, n_44, n_43, n_42, n_41, + n_40, n_39, n_38, n_37, n_36, n_35, n_34, n_33, n_32; + + INV_X1_LVT i_0_725( + .A(op2[31]), .ZN(n_0_692) + ); + INV_X1_LVT i_0_724( + .A(op1[31]), .ZN(n_0_691) + ); + INV_X1_LVT i_0_718( + .A(aluOp[1]), .ZN(n_0_685) + ); + INV_X1_LVT i_0_717( + .A(aluOp[2]), .ZN(n_0_684) + ); + NOR2_X1_LVT i_0_599( + .A1(n_0_685), .A2(n_0_684), .ZN(n_0_567) + ); + INV_X1_LVT i_0_598( + .A(n_0_567), .ZN(n_0_566) + ); + INV_X1_LVT i_0_716( + .A(aluOp[0]), .ZN(n_0_683) + ); + NAND2_X1_LVT i_0_602( + .A1(aluOp[2]), .A2(aluNegAr), .ZN(n_0_570) + ); + OAI21_X1_LVT i_0_590( + .A(n_0_566), .B1(n_0_683), .B2(n_0_570), .ZN(n_0_558) + ); + INV_X1_LVT i_0_714( + .A(aluBypass), .ZN(n_0_681) + ); + NOR2_X1_LVT i_0_601( + .A1(n_0_684), .A2(aluOp[0]), .ZN(n_0_569) + ); + NAND2_X1_LVT i_0_597( + .A1(n_0_681), .A2(n_0_569), .ZN(n_0_565) + ); + INV_X1_LVT i_0_596( + .A(n_0_565), .ZN(n_0_564) + ); + OAI22_X1_LVT i_0_589( + .A1(n_0_691), .A2(n_0_558), .B1(op1[31]), .B2(n_0_564), .ZN(n_0_557) + ); + NOR2_X1_LVT i_0_588( + .A1(n_0_692), .A2(n_0_557), .ZN(n_0_556) + ); + XNOR2_X1_LVT i_9_31( + .A(op2[31]), .B(op1[31]), .ZN(n_9_31) + ); + HA_X1_LVT i_9_0( + .A(op2[0]), .B(op1[0]), .CO(n_9_0), .S(n_0) + ); + FA_X1_LVT i_9_1( + .A(op2[1]), .B(op1[1]), .CI(n_9_0), .CO(n_9_1), .S(n_1) + ); + FA_X1_LVT i_9_2( + .A(op2[2]), .B(op1[2]), .CI(n_9_1), .CO(n_9_2), .S(n_2) + ); + FA_X1_LVT i_9_3( + .A(op2[3]), .B(op1[3]), .CI(n_9_2), .CO(n_9_3), .S(n_3) + ); + FA_X1_LVT i_9_4( + .A(op2[4]), .B(op1[4]), .CI(n_9_3), .CO(n_9_4), .S(n_4) + ); + FA_X1_LVT i_9_5( + .A(op2[5]), .B(op1[5]), .CI(n_9_4), .CO(n_9_5), .S(n_5) + ); + FA_X1_LVT i_9_6( + .A(op2[6]), .B(op1[6]), .CI(n_9_5), .CO(n_9_6), .S(n_6) + ); + FA_X1_LVT i_9_7( + .A(op2[7]), .B(op1[7]), .CI(n_9_6), .CO(n_9_7), .S(n_7) + ); + FA_X1_LVT i_9_8( + .A(op2[8]), .B(op1[8]), .CI(n_9_7), .CO(n_9_8), .S(n_8) + ); + FA_X1_LVT i_9_9( + .A(op2[9]), .B(op1[9]), .CI(n_9_8), .CO(n_9_9), .S(n_9) + ); + FA_X1_LVT i_9_10( + .A(op2[10]), .B(op1[10]), .CI(n_9_9), .CO(n_9_10), .S(n_10) + ); + FA_X1_LVT i_9_11( + .A(op2[11]), .B(op1[11]), .CI(n_9_10), .CO(n_9_11), .S(n_11) + ); + FA_X1_LVT i_9_12( + .A(op2[12]), .B(op1[12]), .CI(n_9_11), .CO(n_9_12), .S(n_12) + ); + FA_X1_LVT i_9_13( + .A(op2[13]), .B(op1[13]), .CI(n_9_12), .CO(n_9_13), .S(n_13) + ); + FA_X1_LVT i_9_14( + .A(op2[14]), .B(op1[14]), .CI(n_9_13), .CO(n_9_14), .S(n_14) + ); + FA_X1_LVT i_9_15( + .A(op2[15]), .B(op1[15]), .CI(n_9_14), .CO(n_9_15), .S(n_15) + ); + FA_X1_LVT i_9_16( + .A(op2[16]), .B(op1[16]), .CI(n_9_15), .CO(n_9_16), .S(n_16) + ); + FA_X1_LVT i_9_17( + .A(op2[17]), .B(op1[17]), .CI(n_9_16), .CO(n_9_17), .S(n_17) + ); + FA_X1_LVT i_9_18( + .A(op2[18]), .B(op1[18]), .CI(n_9_17), .CO(n_9_18), .S(n_18) + ); + FA_X1_LVT i_9_19( + .A(op2[19]), .B(op1[19]), .CI(n_9_18), .CO(n_9_19), .S(n_19) + ); + FA_X1_LVT i_9_20( + .A(op2[20]), .B(op1[20]), .CI(n_9_19), .CO(n_9_20), .S(n_20) + ); + FA_X1_LVT i_9_21( + .A(op2[21]), .B(op1[21]), .CI(n_9_20), .CO(n_9_21), .S(n_21) + ); + FA_X1_LVT i_9_22( + .A(op2[22]), .B(op1[22]), .CI(n_9_21), .CO(n_9_22), .S(n_22) + ); + FA_X1_LVT i_9_23( + .A(op2[23]), .B(op1[23]), .CI(n_9_22), .CO(n_9_23), .S(n_23) + ); + FA_X1_LVT i_9_24( + .A(op2[24]), .B(op1[24]), .CI(n_9_23), .CO(n_9_24), .S(n_24) + ); + FA_X1_LVT i_9_25( + .A(op2[25]), .B(op1[25]), .CI(n_9_24), .CO(n_9_25), .S(n_25) + ); + FA_X1_LVT i_9_26( + .A(op2[26]), .B(op1[26]), .CI(n_9_25), .CO(n_9_26), .S(n_26) + ); + FA_X1_LVT i_9_27( + .A(op2[27]), .B(op1[27]), .CI(n_9_26), .CO(n_9_27), .S(n_27) + ); + FA_X1_LVT i_9_28( + .A(op2[28]), .B(op1[28]), .CI(n_9_27), .CO(n_9_28), .S(n_28) + ); + FA_X1_LVT i_9_29( + .A(op2[29]), .B(op1[29]), .CI(n_9_28), .CO(n_9_29), .S(n_29) + ); + FA_X1_LVT i_9_30( + .A(op2[30]), .B(op1[30]), .CI(n_9_29), .CO(n_9_30), .S(n_30) + ); + XNOR2_X1_LVT i_9_32( + .A(n_9_31), .B(n_9_30), .ZN(n_31) + ); + NAND4_X1_LVT i_0_614( + .A1(n_0_685), .A2(n_0_681), .A3(n_0_684), .A4(n_0_683), .ZN(n_0_582) + ); + NOR2_X1_LVT i_0_613( + .A1(aluNegAr), .A2(n_0_582), .ZN(n_0_581) + ); + INV_X1_LVT i_10_147( + .A(op2[30]), .ZN(n_10_117) + ); + NAND2_X1_LVT i_10_149( + .A1(n_10_117), .A2(op1[30]), .ZN(n_10_119) + ); + INV_X1_LVT i_10_152( + .A(n_10_119), .ZN(n_10_121) + ); + INV_X1_LVT i_10_130( + .A(op1[26]), .ZN(n_10_104) + ); + NAND2_X1_LVT i_10_131( + .A1(n_10_104), .A2(op2[26]), .ZN(n_10_105) + ); + INV_X1_LVT i_10_123( + .A(op2[25]), .ZN(n_10_98) + ); + NAND2_X1_LVT i_10_125( + .A1(n_10_98), .A2(op1[25]), .ZN(n_10_100) + ); + INV_X1_LVT i_10_112( + .A(op2[23]), .ZN(n_10_89) + ); + NAND2_X1_LVT i_10_114( + .A1(n_10_89), .A2(op1[23]), .ZN(n_10_91) + ); + INV_X1_LVT i_10_101( + .A(op2[21]), .ZN(n_10_80) + ); + NAND2_X1_LVT i_10_103( + .A1(n_10_80), .A2(op1[21]), .ZN(n_10_82) + ); + INV_X1_LVT i_10_48( + .A(op1[8]), .ZN(n_10_40) + ); + NAND2_X1_LVT i_10_49( + .A1(n_10_40), .A2(op2[8]), .ZN(n_10_41) + ); + INV_X1_LVT i_10_41( + .A(op2[7]), .ZN(n_10_34) + ); + NAND2_X1_LVT i_10_43( + .A1(n_10_34), .A2(op1[7]), .ZN(n_10_36) + ); + INV_X1_LVT i_10_32( + .A(op2[5]), .ZN(n_10_27) + ); + NOR2_X1_LVT i_10_33( + .A1(n_10_27), .A2(op1[5]), .ZN(n_10_28) + ); + INV_X1_LVT i_10_24( + .A(op1[4]), .ZN(n_10_20) + ); + NOR2_X1_LVT i_10_27( + .A1(n_10_20), .A2(op2[4]), .ZN(n_10_23) + ); + INV_X1_LVT i_10_17( + .A(op2[3]), .ZN(n_10_14) + ); + NAND2_X1_LVT i_10_19( + .A1(n_10_14), .A2(op1[3]), .ZN(n_10_16) + ); + INV_X1_LVT i_10_22( + .A(n_10_16), .ZN(n_10_18) + ); + INV_X1_LVT i_10_10( + .A(op2[2]), .ZN(n_10_8) + ); + NAND2_X1_LVT i_10_12( + .A1(n_10_8), .A2(op1[2]), .ZN(n_10_10) + ); + INV_X1_LVT i_10_3( + .A(op1[1]), .ZN(n_10_2) + ); + NAND2_X1_LVT i_10_5( + .A1(n_10_2), .A2(op2[1]), .ZN(n_10_4) + ); + INV_X1_LVT i_10_0( + .A(op1[0]), .ZN(n_10_0) + ); + NAND2_X1_LVT i_10_1( + .A1(n_10_0), .A2(op2[0]), .ZN(n_10_1) + ); + OR2_X1_LVT i_10_4( + .A1(n_10_2), .A2(op2[1]), .ZN(n_10_3) + ); + INV_X1_LVT i_10_8( + .A(n_10_3), .ZN(n_10_6) + ); + OAI21_X1_LVT i_10_9( + .A(n_10_4), .B1(n_10_1), .B2(n_10_6), .ZN(n_10_7) + ); + NOR2_X1_LVT i_10_11( + .A1(n_10_8), .A2(op1[2]), .ZN(n_10_9) + ); + OAI21_X1_LVT i_10_16( + .A(n_10_10), .B1(n_10_7), .B2(n_10_9), .ZN(n_10_13) + ); + OR2_X1_LVT i_10_18( + .A1(n_10_14), .A2(op1[3]), .ZN(n_10_15) + ); + AOI21_X1_LVT i_10_23( + .A(n_10_18), .B1(n_10_13), .B2(n_10_15), .ZN(n_10_19) + ); + INV_X1_LVT i_10_30( + .A(n_10_19), .ZN(n_10_25) + ); + NAND2_X1_LVT i_10_25( + .A1(n_10_20), .A2(op2[4]), .ZN(n_10_21) + ); + AOI21_X1_LVT i_10_31( + .A(n_10_23), .B1(n_10_25), .B2(n_10_21), .ZN(n_10_26) + ); + AOI21_X1_LVT i_10_34( + .A(n_10_28), .B1(n_10_27), .B2(op1[5]), .ZN(n_10_29) + ); + AOI21_X1_LVT i_10_36( + .A(n_10_28), .B1(n_10_26), .B2(n_10_29), .ZN(n_10_30) + ); + XOR2_X1_LVT i_10_37( + .A(op2[6]), .B(op1[6]), .Z(n_10_31) + ); + INV_X1_LVT i_10_39( + .A(op2[6]), .ZN(n_10_32) + ); + OAI22_X1_LVT i_10_40( + .A1(n_10_30), .A2(n_10_31), .B1(n_10_32), .B2(op1[6]), .ZN(n_10_33) + ); + NOR2_X1_LVT i_10_42( + .A1(n_10_34), .A2(op1[7]), .ZN(n_10_35) + ); + OAI21_X1_LVT i_10_47( + .A(n_10_36), .B1(n_10_33), .B2(n_10_35), .ZN(n_10_39) + ); + OAI21_X1_LVT i_10_50( + .A(n_10_41), .B1(n_10_40), .B2(op2[8]), .ZN(n_10_42) + ); + OAI21_X1_LVT i_10_52( + .A(n_10_41), .B1(n_10_39), .B2(n_10_42), .ZN(n_10_43) + ); + XNOR2_X1_LVT i_10_53( + .A(op2[9]), .B(op1[9]), .ZN(n_10_44) + ); + INV_X1_LVT i_10_55( + .A(op1[9]), .ZN(n_10_45) + ); + AOI22_X1_LVT i_10_56( + .A1(n_10_43), .A2(n_10_44), .B1(n_10_45), .B2(op2[9]), .ZN(n_10_46) + ); + XOR2_X1_LVT i_10_57( + .A(op2[10]), .B(op1[10]), .Z(n_10_47) + ); + INV_X1_LVT i_10_59( + .A(op2[10]), .ZN(n_10_48) + ); + OAI22_X1_LVT i_10_60( + .A1(n_10_46), .A2(n_10_47), .B1(n_10_48), .B2(op1[10]), .ZN(n_10_49) + ); + XNOR2_X1_LVT i_10_61( + .A(op2[11]), .B(op1[11]), .ZN(n_10_50) + ); + INV_X1_LVT i_10_63( + .A(op1[11]), .ZN(n_10_51) + ); + AOI22_X1_LVT i_10_64( + .A1(n_10_49), .A2(n_10_50), .B1(n_10_51), .B2(op2[11]), .ZN(n_10_52) + ); + XOR2_X1_LVT i_10_65( + .A(op2[12]), .B(op1[12]), .Z(n_10_53) + ); + INV_X1_LVT i_10_67( + .A(op2[12]), .ZN(n_10_54) + ); + OAI22_X1_LVT i_10_68( + .A1(n_10_52), .A2(n_10_53), .B1(n_10_54), .B2(op1[12]), .ZN(n_10_55) + ); + XNOR2_X1_LVT i_10_69( + .A(op2[13]), .B(op1[13]), .ZN(n_10_56) + ); + INV_X1_LVT i_10_71( + .A(op1[13]), .ZN(n_10_57) + ); + AOI22_X1_LVT i_10_72( + .A1(n_10_55), .A2(n_10_56), .B1(n_10_57), .B2(op2[13]), .ZN(n_10_58) + ); + XOR2_X1_LVT i_10_73( + .A(op2[14]), .B(op1[14]), .Z(n_10_59) + ); + INV_X1_LVT i_10_75( + .A(op2[14]), .ZN(n_10_60) + ); + OAI22_X1_LVT i_10_76( + .A1(n_10_58), .A2(n_10_59), .B1(n_10_60), .B2(op1[14]), .ZN(n_10_61) + ); + XNOR2_X1_LVT i_10_77( + .A(op2[15]), .B(op1[15]), .ZN(n_10_62) + ); + INV_X1_LVT i_10_79( + .A(op1[15]), .ZN(n_10_63) + ); + AOI22_X1_LVT i_10_80( + .A1(n_10_61), .A2(n_10_62), .B1(n_10_63), .B2(op2[15]), .ZN(n_10_64) + ); + XOR2_X1_LVT i_10_81( + .A(op2[16]), .B(op1[16]), .Z(n_10_65) + ); + INV_X1_LVT i_10_83( + .A(op2[16]), .ZN(n_10_66) + ); + OAI22_X1_LVT i_10_84( + .A1(n_10_64), .A2(n_10_65), .B1(n_10_66), .B2(op1[16]), .ZN(n_10_67) + ); + XNOR2_X1_LVT i_10_85( + .A(op2[17]), .B(op1[17]), .ZN(n_10_68) + ); + INV_X1_LVT i_10_87( + .A(op1[17]), .ZN(n_10_69) + ); + AOI22_X1_LVT i_10_88( + .A1(n_10_67), .A2(n_10_68), .B1(n_10_69), .B2(op2[17]), .ZN(n_10_70) + ); + XOR2_X1_LVT i_10_89( + .A(op2[18]), .B(op1[18]), .Z(n_10_71) + ); + INV_X1_LVT i_10_91( + .A(op2[18]), .ZN(n_10_72) + ); + OAI22_X1_LVT i_10_92( + .A1(n_10_70), .A2(n_10_71), .B1(n_10_72), .B2(op1[18]), .ZN(n_10_73) + ); + XNOR2_X1_LVT i_10_93( + .A(op2[19]), .B(op1[19]), .ZN(n_10_74) + ); + INV_X1_LVT i_10_95( + .A(op1[19]), .ZN(n_10_75) + ); + AOI22_X1_LVT i_10_96( + .A1(n_10_73), .A2(n_10_74), .B1(n_10_75), .B2(op2[19]), .ZN(n_10_76) + ); + XOR2_X1_LVT i_10_97( + .A(op2[20]), .B(op1[20]), .Z(n_10_77) + ); + INV_X1_LVT i_10_99( + .A(op2[20]), .ZN(n_10_78) + ); + OAI22_X1_LVT i_10_100( + .A1(n_10_76), .A2(n_10_77), .B1(n_10_78), .B2(op1[20]), .ZN(n_10_79) + ); + NOR2_X1_LVT i_10_102( + .A1(n_10_80), .A2(op1[21]), .ZN(n_10_81) + ); + OAI21_X1_LVT i_10_107( + .A(n_10_82), .B1(n_10_79), .B2(n_10_81), .ZN(n_10_85) + ); + XOR2_X1_LVT i_10_108( + .A(op2[22]), .B(op1[22]), .Z(n_10_86) + ); + INV_X1_LVT i_10_110( + .A(op2[22]), .ZN(n_10_87) + ); + OAI22_X1_LVT i_10_111( + .A1(n_10_85), .A2(n_10_86), .B1(n_10_87), .B2(op1[22]), .ZN(n_10_88) + ); + NOR2_X1_LVT i_10_113( + .A1(n_10_89), .A2(op1[23]), .ZN(n_10_90) + ); + OAI21_X1_LVT i_10_118( + .A(n_10_91), .B1(n_10_88), .B2(n_10_90), .ZN(n_10_94) + ); + XOR2_X1_LVT i_10_119( + .A(op2[24]), .B(op1[24]), .Z(n_10_95) + ); + INV_X1_LVT i_10_121( + .A(op2[24]), .ZN(n_10_96) + ); + OAI22_X1_LVT i_10_122( + .A1(n_10_94), .A2(n_10_95), .B1(n_10_96), .B2(op1[24]), .ZN(n_10_97) + ); + NOR2_X1_LVT i_10_124( + .A1(n_10_98), .A2(op1[25]), .ZN(n_10_99) + ); + OAI21_X1_LVT i_10_129( + .A(n_10_100), .B1(n_10_97), .B2(n_10_99), .ZN(n_10_103) + ); + OAI21_X1_LVT i_10_132( + .A(n_10_105), .B1(n_10_104), .B2(op2[26]), .ZN(n_10_106) + ); + OAI21_X1_LVT i_10_134( + .A(n_10_105), .B1(n_10_103), .B2(n_10_106), .ZN(n_10_107) + ); + XNOR2_X1_LVT i_10_135( + .A(op2[27]), .B(op1[27]), .ZN(n_10_108) + ); + INV_X1_LVT i_10_137( + .A(op1[27]), .ZN(n_10_109) + ); + AOI22_X1_LVT i_10_138( + .A1(n_10_107), .A2(n_10_108), .B1(n_10_109), .B2(op2[27]), .ZN(n_10_110) + ); + XOR2_X1_LVT i_10_139( + .A(op2[28]), .B(op1[28]), .Z(n_10_111) + ); + INV_X1_LVT i_10_141( + .A(op2[28]), .ZN(n_10_112) + ); + OAI22_X1_LVT i_10_142( + .A1(n_10_110), .A2(n_10_111), .B1(n_10_112), .B2(op1[28]), .ZN(n_10_113) + ); + XNOR2_X1_LVT i_10_143( + .A(op2[29]), .B(op1[29]), .ZN(n_10_114) + ); + INV_X1_LVT i_10_145( + .A(op1[29]), .ZN(n_10_115) + ); + AOI22_X1_LVT i_10_146( + .A1(n_10_113), .A2(n_10_114), .B1(n_10_115), .B2(op2[29]), .ZN(n_10_116) + ); + OR2_X1_LVT i_10_148( + .A1(n_10_117), .A2(op1[30]), .ZN(n_10_118) + ); + AOI21_X1_LVT i_10_153( + .A(n_10_121), .B1(n_10_116), .B2(n_10_118), .ZN(n_10_122) + ); + XNOR2_X1_LVT i_10_154( + .A(op1[31]), .B(op2[31]), .ZN(n_10_123) + ); + XNOR2_X1_LVT i_10_155( + .A(n_10_122), .B(n_10_123), .ZN(n_63) + ); + INV_X1_LVT i_0_715( + .A(aluNegAr), .ZN(n_0_682) + ); + NOR2_X1_LVT i_0_612( + .A1(n_0_682), .A2(n_0_582), .ZN(n_0_580) + ); + AOI221_X1_LVT i_0_587( + .A(n_0_556), .B1(n_31), .B2(n_0_581), .C1(n_63), .C2(n_0_580), .ZN(n_0_555) + ); + NOR3_X1_LVT i_0_654( + .A1(aluOp[1]), .A2(aluBypass), .A3(n_0_683), .ZN(n_0_622) + ); + NAND2_X1_LVT i_0_653( + .A1(n_0_684), .A2(n_0_622), .ZN(n_0_621) + ); + INV_X1_LVT i_0_734( + .A(op2[0]), .ZN(n_0_701) + ); + INV_X1_LVT i_0_756( + .A(op2[3]), .ZN(n_0_723) + ); + NOR2_X1_LVT i_0_650( + .A1(op2[4]), .A2(n_0_723), .ZN(n_0_618) + ); + INV_X1_LVT i_0_649( + .A(n_0_618), .ZN(n_0_617) + ); + NOR2_X1_LVT i_0_648( + .A1(op2[4]), .A2(op2[3]), .ZN(n_0_616) + ); + INV_X1_LVT i_0_647( + .A(n_0_616), .ZN(n_0_615) + ); + INV_X1_LVT i_0_771( + .A(op2[4]), .ZN(n_0_738) + ); + INV_X1_LVT i_0_767( + .A(op1[15]), .ZN(n_0_734) + ); + INV_X1_LVT i_0_746( + .A(op1[7]), .ZN(n_0_713) + ); + AOI22_X1_LVT i_0_651( + .A1(n_0_734), .A2(n_0_723), .B1(op2[3]), .B2(n_0_713), .ZN(n_0_619) + ); + OAI222_X1_LVT i_0_646( + .A1(op1[23]), .A2(n_0_617), .B1(op1[31]), .B2(n_0_615), .C1(n_0_738), .C2(n_0_619), + .ZN(n_0_614) + ); + NOR2_X1_LVT i_0_645( + .A1(op2[2]), .A2(n_0_614), .ZN(n_0_613) + ); + NOR2_X1_LVT i_0_696( + .A1(op1[3]), .A2(n_0_723), .ZN(n_0_663) + ); + INV_X1_LVT i_0_739( + .A(op1[11]), .ZN(n_0_706) + ); + AOI21_X1_LVT i_0_644( + .A(n_0_663), .B1(n_0_723), .B2(n_0_706), .ZN(n_0_612) + ); + AOI22_X1_LVT i_0_643( + .A1(op2[4]), .A2(n_0_612), .B1(op1[27]), .B2(n_0_616), .ZN(n_0_611) + ); + INV_X1_LVT i_0_722( + .A(op1[19]), .ZN(n_0_689) + ); + OAI21_X1_LVT i_0_642( + .A(n_0_611), .B1(n_0_689), .B2(n_0_617), .ZN(n_0_610) + ); + AOI21_X1_LVT i_0_641( + .A(n_0_613), .B1(op2[2]), .B2(n_0_610), .ZN(n_0_609) + ); + INV_X1_LVT i_0_761( + .A(op2[1]), .ZN(n_0_728) + ); + OAI22_X1_LVT i_0_640( + .A1(op2[4]), .A2(op1[21]), .B1(n_0_738), .B2(op1[5]), .ZN(n_0_608) + ); + NAND2_X1_LVT i_0_639( + .A1(op2[3]), .A2(n_0_608), .ZN(n_0_607) + ); + INV_X1_LVT i_0_747( + .A(op1[13]), .ZN(n_0_714) + ); + NOR2_X1_LVT i_0_638( + .A1(n_0_738), .A2(op2[3]), .ZN(n_0_606) + ); + INV_X1_LVT i_0_743( + .A(op1[29]), .ZN(n_0_710) + ); + AOI221_X1_LVT i_0_636( + .A(op2[2]), .B1(n_0_714), .B2(n_0_606), .C1(n_0_710), .C2(n_0_616), .ZN(n_0_604) + ); + OAI22_X1_LVT i_0_635( + .A1(op2[4]), .A2(op1[17]), .B1(n_0_738), .B2(op1[1]), .ZN(n_0_603) + ); + INV_X1_LVT i_0_755( + .A(op1[9]), .ZN(n_0_722) + ); + INV_X1_LVT i_0_637( + .A(n_0_606), .ZN(n_0_605) + ); + INV_X1_LVT i_0_732( + .A(op1[25]), .ZN(n_0_699) + ); + OAI222_X1_LVT i_0_634( + .A1(n_0_723), .A2(n_0_603), .B1(n_0_722), .B2(n_0_605), .C1(n_0_699), .C2(n_0_615), + .ZN(n_0_602) + ); + AOI22_X1_LVT i_0_633( + .A1(n_0_607), .A2(n_0_604), .B1(op2[2]), .B2(n_0_602), .ZN(n_0_601) + ); + OAI221_X1_LVT i_0_616( + .A(n_0_701), .B1(op2[1]), .B2(n_0_609), .C1(n_0_728), .C2(n_0_601), .ZN(n_0_584) + ); + INV_X1_LVT i_0_729( + .A(op1[12]), .ZN(n_0_696) + ); + INV_X1_LVT i_0_731( + .A(op1[28]), .ZN(n_0_698) + ); + AOI22_X1_LVT i_0_622( + .A1(n_0_696), .A2(n_0_606), .B1(n_0_698), .B2(n_0_616), .ZN(n_0_590) + ); + INV_X1_LVT i_0_726( + .A(op2[2]), .ZN(n_0_693) + ); + NOR2_X1_LVT i_0_701( + .A1(n_0_738), .A2(op1[4]), .ZN(n_0_668) + ); + INV_X1_LVT i_0_760( + .A(op1[20]), .ZN(n_0_727) + ); + AOI21_X1_LVT i_0_623( + .A(n_0_668), .B1(n_0_738), .B2(n_0_727), .ZN(n_0_591) + ); + OAI211_X1_LVT i_0_621( + .A(n_0_590), .B(n_0_693), .C1(n_0_723), .C2(n_0_591), .ZN(n_0_589) + ); + OAI22_X1_LVT i_0_626( + .A1(op1[16]), .A2(op2[4]), .B1(n_0_738), .B2(op1[0]), .ZN(n_0_594) + ); + INV_X1_LVT i_0_769( + .A(op1[24]), .ZN(n_0_736) + ); + OAI22_X1_LVT i_0_625( + .A1(n_0_723), .A2(n_0_594), .B1(n_0_736), .B2(n_0_615), .ZN(n_0_593) + ); + AOI21_X1_LVT i_0_624( + .A(n_0_593), .B1(op1[8]), .B2(n_0_606), .ZN(n_0_592) + ); + OAI21_X1_LVT i_0_620( + .A(n_0_589), .B1(n_0_693), .B2(n_0_592), .ZN(n_0_588) + ); + INV_X1_LVT i_0_737( + .A(op1[6]), .ZN(n_0_704) + ); + INV_X1_LVT i_0_720( + .A(op1[22]), .ZN(n_0_687) + ); + OAI22_X1_LVT i_0_632( + .A1(n_0_738), .A2(n_0_704), .B1(op2[4]), .B2(n_0_687), .ZN(n_0_600) + ); + OAI221_X1_LVT i_0_631( + .A(n_0_693), .B1(n_0_723), .B2(n_0_600), .C1(op1[14]), .C2(n_0_605), .ZN(n_0_599) + ); + INV_X1_LVT i_0_750( + .A(op1[30]), .ZN(n_0_717) + ); + AOI21_X1_LVT i_0_630( + .A(n_0_599), .B1(n_0_717), .B2(n_0_616), .ZN(n_0_598) + ); + INV_X1_LVT i_0_738( + .A(op1[18]), .ZN(n_0_705) + ); + NOR2_X1_LVT i_0_628( + .A1(n_0_705), .A2(n_0_617), .ZN(n_0_596) + ); + INV_X1_LVT i_0_727( + .A(op1[2]), .ZN(n_0_694) + ); + INV_X1_LVT i_0_766( + .A(op1[10]), .ZN(n_0_733) + ); + OAI22_X1_LVT i_0_629( + .A1(n_0_723), .A2(n_0_694), .B1(n_0_733), .B2(op2[3]), .ZN(n_0_597) + ); + AOI221_X1_LVT i_0_627( + .A(n_0_596), .B1(op1[26]), .B2(n_0_616), .C1(op2[4]), .C2(n_0_597), .ZN(n_0_595) + ); + OAI21_X1_LVT i_0_619( + .A(n_0_728), .B1(n_0_693), .B2(n_0_595), .ZN(n_0_587) + ); + OAI22_X1_LVT i_0_618( + .A1(n_0_728), .A2(n_0_588), .B1(n_0_598), .B2(n_0_587), .ZN(n_0_586) + ); + INV_X1_LVT i_0_617( + .A(n_0_586), .ZN(n_0_585) + ); + OAI21_X1_LVT i_0_615( + .A(n_0_584), .B1(n_0_701), .B2(n_0_585), .ZN(n_0_583) + ); + NOR2_X1_LVT i_0_607( + .A1(op2[4]), .A2(op2[2]), .ZN(n_0_575) + ); + NAND2_X1_LVT i_0_606( + .A1(n_0_723), .A2(n_0_575), .ZN(n_0_574) + ); + INV_X1_LVT i_0_605( + .A(n_0_574), .ZN(n_0_573) + ); + NAND2_X1_LVT i_0_604( + .A1(n_0_728), .A2(n_0_573), .ZN(n_0_572) + ); + NAND2_X1_LVT i_0_611( + .A1(aluOp[2]), .A2(n_0_622), .ZN(n_0_579) + ); + INV_X1_LVT i_0_610( + .A(n_0_579), .ZN(n_0_578) + ); + NAND2_X1_LVT i_0_594( + .A1(n_0_701), .A2(n_0_578), .ZN(n_0_562) + ); + NOR3_X1_LVT i_0_592( + .A1(aluNegAr), .A2(n_0_572), .A3(n_0_562), .ZN(n_0_560) + ); + INV_X1_LVT i_0_600( + .A(n_0_569), .ZN(n_0_568) + ); + OAI21_X1_LVT i_0_595( + .A(n_0_568), .B1(aluOp[1]), .B2(n_0_570), .ZN(n_0_563) + ); + AOI211_X1_LVT i_0_591( + .A(aluBypass), .B(n_0_560), .C1(n_0_692), .C2(n_0_563), .ZN(n_0_559) + ); + OAI221_X1_LVT i_0_586( + .A(n_0_555), .B1(n_0_621), .B2(n_0_583), .C1(n_0_691), .C2(n_0_559), .ZN(result[31]) + ); + NAND2_X1_LVT i_10_150( + .A1(n_10_118), .A2(n_10_119), .ZN(n_10_120) + ); + XNOR2_X1_LVT i_10_151( + .A(n_10_116), .B(n_10_120), .ZN(n_62) + ); + AOI22_X1_LVT i_0_580( + .A1(n_62), .A2(n_0_580), .B1(n_30), .B2(n_0_581), .ZN(n_0_549) + ); + NAND2_X1_LVT i_0_576( + .A1(aluNegAr), .A2(n_0_578), .ZN(n_0_545) + ); + INV_X1_LVT i_0_603( + .A(n_0_572), .ZN(n_0_571) + ); + NOR3_X1_LVT i_0_574( + .A1(n_0_691), .A2(n_0_545), .A3(n_0_571), .ZN(n_0_543) + ); + AOI22_X1_LVT i_0_573( + .A1(n_0_717), .A2(n_0_565), .B1(op1[30]), .B2(n_0_566), .ZN(n_0_542) + ); + AOI21_X1_LVT i_0_572( + .A(n_0_543), .B1(op2[30]), .B2(n_0_542), .ZN(n_0_541) + ); + NAND2_X1_LVT i_0_579( + .A1(op2[0]), .A2(n_0_578), .ZN(n_0_548) + ); + NAND2_X1_LVT i_0_577( + .A1(op1[31]), .A2(n_0_571), .ZN(n_0_546) + ); + OAI211_X1_LVT i_0_571( + .A(n_0_549), .B(n_0_541), .C1(n_0_548), .C2(n_0_546), .ZN(n_0_540) + ); + OAI221_X1_LVT i_0_581( + .A(n_0_681), .B1(op2[30]), .B2(n_0_568), .C1(n_0_572), .C2(n_0_562), .ZN(n_0_550) + ); + AOI21_X1_LVT i_0_570( + .A(n_0_540), .B1(op1[30]), .B2(n_0_550), .ZN(n_0_539) + ); + INV_X1_LVT i_0_752( + .A(op1[23]), .ZN(n_0_719) + ); + OAI222_X1_LVT i_0_585( + .A1(n_0_713), .A2(n_0_605), .B1(n_0_719), .B2(n_0_615), .C1(n_0_734), .C2(n_0_617), + .ZN(n_0_554) + ); + AOI22_X1_LVT i_0_584( + .A1(op2[2]), .A2(n_0_554), .B1(n_0_693), .B2(n_0_610), .ZN(n_0_553) + ); + OAI22_X1_LVT i_0_583( + .A1(n_0_728), .A2(n_0_553), .B1(op2[1]), .B2(n_0_601), .ZN(n_0_552) + ); + AOI22_X1_LVT i_0_582( + .A1(n_0_701), .A2(n_0_585), .B1(op2[0]), .B2(n_0_552), .ZN(n_0_551) + ); + OAI21_X1_LVT i_0_569( + .A(n_0_539), .B1(n_0_621), .B2(n_0_551), .ZN(result[30]) + ); + INV_X1_LVT i_0_578( + .A(n_0_548), .ZN(n_0_547) + ); + NAND3_X1_LVT i_0_562( + .A1(op1[30]), .A2(n_0_571), .A3(n_0_547), .ZN(n_0_532) + ); + XNOR2_X1_LVT i_10_144( + .A(n_10_113), .B(n_10_114), .ZN(n_61) + ); + NAND2_X1_LVT i_0_558( + .A1(n_61), .A2(n_0_580), .ZN(n_0_528) + ); + OAI21_X1_LVT i_0_557( + .A(n_0_681), .B1(op2[29]), .B2(n_0_568), .ZN(n_0_527) + ); + NAND2_X1_LVT i_0_556( + .A1(op1[29]), .A2(n_0_566), .ZN(n_0_526) + ); + AOI22_X1_LVT i_0_555( + .A1(op1[29]), .A2(n_0_527), .B1(op2[29]), .B2(n_0_526), .ZN(n_0_525) + ); + AOI21_X1_LVT i_0_554( + .A(n_0_525), .B1(n_0_710), .B2(n_0_565), .ZN(n_0_524) + ); + AOI211_X1_LVT i_0_553( + .A(n_0_543), .B(n_0_524), .C1(n_29), .C2(n_0_581), .ZN(n_0_523) + ); + AND3_X1_LVT i_0_552( + .A1(n_0_532), .A2(n_0_528), .A3(n_0_523), .ZN(n_0_522) + ); + INV_X1_LVT i_0_652( + .A(n_0_621), .ZN(n_0_620) + ); + NAND2_X1_LVT i_0_565( + .A1(n_0_728), .A2(n_0_588), .ZN(n_0_535) + ); + AOI22_X1_LVT i_0_568( + .A1(n_0_723), .A2(n_0_600), .B1(op1[14]), .B2(n_0_618), .ZN(n_0_538) + ); + AOI22_X1_LVT i_0_567( + .A1(n_0_693), .A2(n_0_595), .B1(op2[2]), .B2(n_0_538), .ZN(n_0_537) + ); + INV_X1_LVT i_0_566( + .A(n_0_537), .ZN(n_0_536) + ); + OAI21_X1_LVT i_0_564( + .A(n_0_535), .B1(n_0_728), .B2(n_0_536), .ZN(n_0_534) + ); + OAI221_X1_LVT i_0_563( + .A(n_0_620), .B1(op2[0]), .B2(n_0_552), .C1(n_0_701), .C2(n_0_534), .ZN(n_0_533) + ); + NAND2_X1_LVT i_0_561( + .A1(op2[1]), .A2(n_0_573), .ZN(n_0_531) + ); + INV_X1_LVT i_0_560( + .A(n_0_531), .ZN(n_0_530) + ); + AOI22_X1_LVT i_0_559( + .A1(op1[31]), .A2(n_0_530), .B1(op1[29]), .B2(n_0_571), .ZN(n_0_529) + ); + OAI211_X1_LVT i_0_551( + .A(n_0_522), .B(n_0_533), .C1(n_0_562), .C2(n_0_529), .ZN(result[29]) + ); + INV_X1_LVT i_0_733( + .A(op2[28]), .ZN(n_0_700) + ); + AOI221_X1_LVT i_0_546( + .A(n_0_700), .B1(op1[28]), .B2(n_0_566), .C1(n_0_698), .C2(n_0_565), .ZN(n_0_517) + ); + OAI21_X1_LVT i_0_543( + .A(n_0_681), .B1(op2[28]), .B2(n_0_568), .ZN(n_0_514) + ); + AOI22_X1_LVT i_0_542( + .A1(n_28), .A2(n_0_581), .B1(op1[28]), .B2(n_0_514), .ZN(n_0_513) + ); + XNOR2_X1_LVT i_10_140( + .A(n_10_110), .B(n_10_111), .ZN(n_60) + ); + NAND2_X1_LVT i_0_544( + .A1(n_60), .A2(n_0_580), .ZN(n_0_515) + ); + NAND2_X1_LVT i_0_545( + .A1(op1[31]), .A2(n_0_574), .ZN(n_0_516) + ); + OAI211_X1_LVT i_0_541( + .A(n_0_513), .B(n_0_515), .C1(n_0_545), .C2(n_0_516), .ZN(n_0_512) + ); + AOI22_X1_LVT i_0_540( + .A1(op1[30]), .A2(n_0_530), .B1(op1[28]), .B2(n_0_571), .ZN(n_0_511) + ); + OAI22_X1_LVT i_0_539( + .A1(n_0_562), .A2(n_0_511), .B1(n_0_548), .B2(n_0_529), .ZN(n_0_510) + ); + NOR3_X1_LVT i_0_538( + .A1(n_0_517), .A2(n_0_512), .A3(n_0_510), .ZN(n_0_509) + ); + OAI22_X1_LVT i_0_550( + .A1(n_0_714), .A2(n_0_617), .B1(op2[3]), .B2(n_0_608), .ZN(n_0_521) + ); + OAI22_X1_LVT i_0_549( + .A1(op2[2]), .A2(n_0_602), .B1(n_0_693), .B2(n_0_521), .ZN(n_0_520) + ); + AOI22_X1_LVT i_0_548( + .A1(op2[1]), .A2(n_0_520), .B1(n_0_728), .B2(n_0_553), .ZN(n_0_519) + ); + OAI22_X1_LVT i_0_547( + .A1(op2[0]), .A2(n_0_534), .B1(n_0_701), .B2(n_0_519), .ZN(n_0_518) + ); + OAI21_X1_LVT i_0_537( + .A(n_0_509), .B1(n_0_621), .B2(n_0_518), .ZN(result[28]) + ); + XNOR2_X1_LVT i_10_136( + .A(n_10_107), .B(n_10_108), .ZN(n_59) + ); + AOI22_X1_LVT i_0_517( + .A1(n_27), .A2(n_0_581), .B1(n_59), .B2(n_0_580), .ZN(n_0_489) + ); + INV_X1_LVT i_0_721( + .A(op1[27]), .ZN(n_0_688) + ); + OAI21_X1_LVT i_0_516( + .A(n_0_681), .B1(op2[27]), .B2(n_0_568), .ZN(n_0_488) + ); + INV_X1_LVT i_0_515( + .A(n_0_488), .ZN(n_0_487) + ); + OAI221_X1_LVT i_0_514( + .A(n_0_489), .B1(n_0_545), .B2(n_0_516), .C1(n_0_688), .C2(n_0_487), .ZN(n_0_486) + ); + OAI21_X1_LVT i_0_530( + .A(op2[1]), .B1(n_0_710), .B2(n_0_574), .ZN(n_0_502) + ); + OAI21_X1_LVT i_0_529( + .A(n_0_728), .B1(n_0_688), .B2(n_0_574), .ZN(n_0_501) + ); + NAND2_X1_LVT i_0_528( + .A1(n_0_502), .A2(n_0_501), .ZN(n_0_500) + ); + AOI21_X1_LVT i_0_527( + .A(n_0_545), .B1(n_0_701), .B2(n_0_500), .ZN(n_0_499) + ); + NAND2_X1_LVT i_0_609( + .A1(n_0_682), .A2(n_0_578), .ZN(n_0_577) + ); + NOR2_X1_LVT i_0_526( + .A1(op2[4]), .A2(n_0_693), .ZN(n_0_498) + ); + NAND2_X1_LVT i_0_525( + .A1(n_0_723), .A2(n_0_498), .ZN(n_0_497) + ); + OAI22_X1_LVT i_0_523( + .A1(n_0_688), .A2(n_0_574), .B1(n_0_691), .B2(n_0_497), .ZN(n_0_495) + ); + OAI21_X1_LVT i_0_522( + .A(n_0_502), .B1(op2[1]), .B2(n_0_495), .ZN(n_0_494) + ); + AOI21_X1_LVT i_0_521( + .A(n_0_577), .B1(n_0_701), .B2(n_0_494), .ZN(n_0_493) + ); + NOR2_X1_LVT i_0_520( + .A1(n_0_499), .A2(n_0_493), .ZN(n_0_492) + ); + AOI21_X1_LVT i_0_519( + .A(n_0_492), .B1(op2[0]), .B2(n_0_511), .ZN(n_0_491) + ); + AOI22_X1_LVT i_0_518( + .A1(n_0_688), .A2(n_0_565), .B1(op1[27]), .B2(n_0_566), .ZN(n_0_490) + ); + AOI211_X1_LVT i_0_513( + .A(n_0_486), .B(n_0_491), .C1(op2[27]), .C2(n_0_490), .ZN(n_0_485) + ); + NOR3_X1_LVT i_0_536( + .A1(op2[4]), .A2(n_0_696), .A3(n_0_723), .ZN(n_0_508) + ); + AOI21_X1_LVT i_0_535( + .A(n_0_508), .B1(n_0_723), .B2(n_0_591), .ZN(n_0_507) + ); + OAI22_X1_LVT i_0_534( + .A1(op2[2]), .A2(n_0_592), .B1(n_0_693), .B2(n_0_507), .ZN(n_0_506) + ); + NOR2_X1_LVT i_0_533( + .A1(n_0_728), .A2(n_0_506), .ZN(n_0_505) + ); + AOI21_X1_LVT i_0_532( + .A(n_0_505), .B1(n_0_728), .B2(n_0_536), .ZN(n_0_504) + ); + OAI22_X1_LVT i_0_531( + .A1(n_0_701), .A2(n_0_504), .B1(op2[0]), .B2(n_0_519), .ZN(n_0_503) + ); + OAI21_X1_LVT i_0_512( + .A(n_0_485), .B1(n_0_621), .B2(n_0_503), .ZN(result[27]) + ); + OAI21_X1_LVT i_0_500( + .A(n_0_681), .B1(op2[26]), .B2(n_0_568), .ZN(n_0_473) + ); + NAND2_X1_LVT i_0_499( + .A1(op1[26]), .A2(n_0_473), .ZN(n_0_472) + ); + XNOR2_X1_LVT i_10_133( + .A(n_10_103), .B(n_10_106), .ZN(n_58) + ); + AOI22_X1_LVT i_0_498( + .A1(n_58), .A2(n_0_580), .B1(n_26), .B2(n_0_581), .ZN(n_0_471) + ); + INV_X1_LVT i_0_744( + .A(op1[26]), .ZN(n_0_711) + ); + OAI221_X1_LVT i_0_501( + .A(op2[26]), .B1(op1[26]), .B2(n_0_564), .C1(n_0_711), .C2(n_0_567), .ZN(n_0_474) + ); + NAND3_X1_LVT i_0_497( + .A1(n_0_472), .A2(n_0_471), .A3(n_0_474), .ZN(n_0_470) + ); + INV_X1_LVT i_0_524( + .A(n_0_497), .ZN(n_0_496) + ); + AOI22_X1_LVT i_0_505( + .A1(op1[30]), .A2(n_0_496), .B1(op1[26]), .B2(n_0_573), .ZN(n_0_478) + ); + NOR2_X1_LVT i_0_504( + .A1(op2[1]), .A2(n_0_478), .ZN(n_0_477) + ); + AOI21_X1_LVT i_0_503( + .A(n_0_477), .B1(op1[28]), .B2(n_0_530), .ZN(n_0_476) + ); + NAND2_X1_LVT i_0_502( + .A1(n_0_701), .A2(n_0_476), .ZN(n_0_475) + ); + AOI21_X1_LVT i_0_489( + .A(n_0_577), .B1(op2[0]), .B2(n_0_494), .ZN(n_0_462) + ); + AOI21_X1_LVT i_0_488( + .A(n_0_470), .B1(n_0_475), .B2(n_0_462), .ZN(n_0_461) + ); + AOI21_X1_LVT i_0_511( + .A(n_0_616), .B1(n_0_738), .B2(n_0_706), .ZN(n_0_484) + ); + AOI21_X1_LVT i_0_510( + .A(n_0_484), .B1(n_0_723), .B2(op1[19]), .ZN(n_0_483) + ); + INV_X1_LVT i_0_757( + .A(op1[3]), .ZN(n_0_724) + ); + NOR2_X1_LVT i_0_687( + .A1(n_0_724), .A2(op2[3]), .ZN(n_0_654) + ); + INV_X1_LVT i_0_686( + .A(n_0_654), .ZN(n_0_653) + ); + AOI21_X1_LVT i_0_509( + .A(n_0_483), .B1(op2[4]), .B2(n_0_653), .ZN(n_0_482) + ); + AOI22_X1_LVT i_0_508( + .A1(n_0_693), .A2(n_0_554), .B1(op2[2]), .B2(n_0_482), .ZN(n_0_481) + ); + OAI22_X1_LVT i_0_507( + .A1(n_0_728), .A2(n_0_481), .B1(op2[1]), .B2(n_0_520), .ZN(n_0_480) + ); + AOI22_X1_LVT i_0_506( + .A1(op2[0]), .A2(n_0_480), .B1(n_0_701), .B2(n_0_504), .ZN(n_0_479) + ); + NAND3_X1_LVT i_0_491( + .A1(op2[0]), .A2(n_0_516), .A3(n_0_500), .ZN(n_0_464) + ); + NAND2_X1_LVT i_0_494( + .A1(op1[31]), .A2(n_0_615), .ZN(n_0_467) + ); + OAI21_X1_LVT i_0_492( + .A(n_0_467), .B1(n_0_728), .B2(n_0_516), .ZN(n_0_465) + ); + OAI21_X1_LVT i_0_490( + .A(n_0_464), .B1(n_0_475), .B2(n_0_465), .ZN(n_0_463) + ); + OAI221_X1_LVT i_0_487( + .A(n_0_461), .B1(n_0_621), .B2(n_0_479), .C1(n_0_545), .C2(n_0_463), .ZN(result[26]) + ); + INV_X1_LVT i_10_126( + .A(n_10_100), .ZN(n_10_101) + ); + NOR2_X1_LVT i_10_127( + .A1(n_10_99), .A2(n_10_101), .ZN(n_10_102) + ); + XNOR2_X1_LVT i_10_128( + .A(n_10_97), .B(n_10_102), .ZN(n_57) + ); + AOI22_X1_LVT i_0_479( + .A1(n_57), .A2(n_0_580), .B1(n_25), .B2(n_0_581), .ZN(n_0_453) + ); + INV_X1_LVT i_0_730( + .A(op2[25]), .ZN(n_0_697) + ); + AOI21_X1_LVT i_0_478( + .A(aluBypass), .B1(n_0_697), .B2(n_0_569), .ZN(n_0_452) + ); + AOI22_X1_LVT i_0_480( + .A1(op1[25]), .A2(n_0_567), .B1(n_0_699), .B2(n_0_564), .ZN(n_0_454) + ); + OAI221_X1_LVT i_0_477( + .A(n_0_453), .B1(n_0_699), .B2(n_0_452), .C1(n_0_697), .C2(n_0_454), .ZN(n_0_451) + ); + INV_X1_LVT i_0_575( + .A(n_0_545), .ZN(n_0_544) + ); + AOI21_X1_LVT i_0_476( + .A(n_0_451), .B1(n_0_544), .B2(n_0_465), .ZN(n_0_450) + ); + AOI22_X1_LVT i_0_475( + .A1(op1[29]), .A2(n_0_496), .B1(op1[25]), .B2(n_0_573), .ZN(n_0_449) + ); + NAND2_X1_LVT i_0_474( + .A1(n_0_728), .A2(n_0_449), .ZN(n_0_448) + ); + OAI21_X1_LVT i_0_473( + .A(n_0_448), .B1(n_0_728), .B2(n_0_495), .ZN(n_0_447) + ); + OAI22_X1_LVT i_0_472( + .A1(n_0_548), .A2(n_0_476), .B1(n_0_562), .B2(n_0_447), .ZN(n_0_446) + ); + INV_X1_LVT i_0_471( + .A(n_0_446), .ZN(n_0_445) + ); + OAI222_X1_LVT i_0_486( + .A1(n_0_733), .A2(n_0_617), .B1(n_0_694), .B2(n_0_605), .C1(n_0_705), .C2(n_0_615), + .ZN(n_0_460) + ); + NOR2_X1_LVT i_0_485( + .A1(n_0_693), .A2(n_0_460), .ZN(n_0_459) + ); + AOI21_X1_LVT i_0_484( + .A(n_0_459), .B1(n_0_693), .B2(n_0_538), .ZN(n_0_458) + ); + OAI22_X1_LVT i_0_483( + .A1(n_0_728), .A2(n_0_458), .B1(op2[1]), .B2(n_0_506), .ZN(n_0_457) + ); + INV_X1_LVT i_0_482( + .A(n_0_457), .ZN(n_0_456) + ); + OAI221_X1_LVT i_0_481( + .A(n_0_620), .B1(n_0_701), .B2(n_0_456), .C1(op2[0]), .C2(n_0_480), .ZN(n_0_455) + ); + NAND3_X1_LVT i_0_470( + .A1(n_0_450), .A2(n_0_445), .A3(n_0_455), .ZN(result[25]) + ); + INV_X1_LVT i_0_493( + .A(n_0_467), .ZN(n_0_466) + ); + OAI211_X1_LVT i_0_455( + .A(n_0_544), .B(n_0_465), .C1(op2[0]), .C2(n_0_466), .ZN(n_0_430) + ); + OAI21_X1_LVT i_0_462( + .A(n_0_681), .B1(op2[24]), .B2(n_0_568), .ZN(n_0_437) + ); + XNOR2_X1_LVT i_10_120( + .A(n_10_94), .B(n_10_95), .ZN(n_56) + ); + AOI222_X1_LVT i_0_461( + .A1(op1[24]), .A2(n_0_437), .B1(n_56), .B2(n_0_580), .C1(n_24), .C2(n_0_581), + .ZN(n_0_436) + ); + INV_X1_LVT i_0_460( + .A(n_0_436), .ZN(n_0_435) + ); + AOI22_X1_LVT i_0_458( + .A1(op1[24]), .A2(n_0_573), .B1(op1[28]), .B2(n_0_496), .ZN(n_0_433) + ); + OAI22_X1_LVT i_0_457( + .A1(op2[1]), .A2(n_0_433), .B1(n_0_728), .B2(n_0_478), .ZN(n_0_432) + ); + INV_X1_LVT i_0_456( + .A(n_0_432), .ZN(n_0_431) + ); + OAI22_X1_LVT i_0_454( + .A1(n_0_562), .A2(n_0_431), .B1(n_0_548), .B2(n_0_447), .ZN(n_0_429) + ); + AOI22_X1_LVT i_0_459( + .A1(n_0_736), .A2(n_0_565), .B1(op1[24]), .B2(n_0_566), .ZN(n_0_434) + ); + AOI211_X1_LVT i_0_453( + .A(n_0_435), .B(n_0_429), .C1(op2[24]), .C2(n_0_434), .ZN(n_0_428) + ); + NAND2_X1_LVT i_0_467( + .A1(n_0_693), .A2(n_0_521), .ZN(n_0_442) + ); + NOR2_X1_LVT i_0_469( + .A1(op2[3]), .A2(n_0_603), .ZN(n_0_444) + ); + AOI21_X1_LVT i_0_468( + .A(n_0_444), .B1(op1[9]), .B2(n_0_618), .ZN(n_0_443) + ); + OAI21_X1_LVT i_0_466( + .A(n_0_442), .B1(n_0_693), .B2(n_0_443), .ZN(n_0_441) + ); + NAND2_X1_LVT i_0_465( + .A1(op2[1]), .A2(n_0_441), .ZN(n_0_440) + ); + OAI21_X1_LVT i_0_464( + .A(n_0_440), .B1(op2[1]), .B2(n_0_481), .ZN(n_0_439) + ); + OAI221_X1_LVT i_0_463( + .A(n_0_620), .B1(op2[0]), .B2(n_0_456), .C1(n_0_701), .C2(n_0_439), .ZN(n_0_438) + ); + NAND3_X1_LVT i_0_452( + .A1(n_0_430), .A2(n_0_428), .A3(n_0_438), .ZN(result[24]) + ); + INV_X1_LVT i_0_751( + .A(op2[23]), .ZN(n_0_718) + ); + AOI221_X1_LVT i_0_440( + .A(n_0_718), .B1(op1[23]), .B2(n_0_566), .C1(n_0_719), .C2(n_0_565), .ZN(n_0_416) + ); + INV_X1_LVT i_10_115( + .A(n_10_91), .ZN(n_10_92) + ); + NOR2_X1_LVT i_10_116( + .A1(n_10_90), .A2(n_10_92), .ZN(n_10_93) + ); + XNOR2_X1_LVT i_10_117( + .A(n_10_88), .B(n_10_93), .ZN(n_55) + ); + AOI222_X1_LVT i_0_438( + .A1(n_23), .A2(n_0_581), .B1(n_0_544), .B2(n_0_466), .C1(n_55), .C2(n_0_580), + .ZN(n_0_414) + ); + OAI21_X1_LVT i_0_437( + .A(n_0_414), .B1(n_0_548), .B2(n_0_431), .ZN(n_0_413) + ); + OAI21_X1_LVT i_0_439( + .A(n_0_681), .B1(op2[23]), .B2(n_0_568), .ZN(n_0_415) + ); + AOI211_X1_LVT i_0_436( + .A(n_0_416), .B(n_0_413), .C1(op1[23]), .C2(n_0_415), .ZN(n_0_412) + ); + AOI22_X1_LVT i_0_444( + .A1(n_0_723), .A2(n_0_719), .B1(op2[3]), .B2(n_0_691), .ZN(n_0_420) + ); + AOI22_X1_LVT i_0_443( + .A1(n_0_575), .A2(n_0_420), .B1(op1[27]), .B2(n_0_496), .ZN(n_0_419) + ); + AOI22_X1_LVT i_0_442( + .A1(op2[1]), .A2(n_0_449), .B1(n_0_728), .B2(n_0_419), .ZN(n_0_418) + ); + INV_X1_LVT i_0_441( + .A(n_0_418), .ZN(n_0_417) + ); + NAND2_X1_LVT i_0_447( + .A1(n_0_728), .A2(n_0_458), .ZN(n_0_423) + ); + NOR2_X1_LVT i_0_451( + .A1(op2[3]), .A2(n_0_594), .ZN(n_0_427) + ); + AOI21_X1_LVT i_0_450( + .A(n_0_427), .B1(op1[8]), .B2(n_0_618), .ZN(n_0_426) + ); + OAI22_X1_LVT i_0_449( + .A1(n_0_693), .A2(n_0_426), .B1(op2[2]), .B2(n_0_507), .ZN(n_0_425) + ); + INV_X1_LVT i_0_448( + .A(n_0_425), .ZN(n_0_424) + ); + OAI21_X1_LVT i_0_446( + .A(n_0_423), .B1(n_0_728), .B2(n_0_424), .ZN(n_0_422) + ); + AOI22_X1_LVT i_0_445( + .A1(op2[0]), .A2(n_0_422), .B1(n_0_701), .B2(n_0_439), .ZN(n_0_421) + ); + OAI221_X1_LVT i_0_435( + .A(n_0_412), .B1(n_0_562), .B2(n_0_417), .C1(n_0_621), .C2(n_0_421), .ZN(result[23]) + ); + XNOR2_X1_LVT i_10_109( + .A(n_10_85), .B(n_10_86), .ZN(n_54) + ); + AOI22_X1_LVT i_0_419( + .A1(n_54), .A2(n_0_580), .B1(n_22), .B2(n_0_581), .ZN(n_0_396) + ); + INV_X1_LVT i_0_719( + .A(op2[22]), .ZN(n_0_686) + ); + AOI21_X1_LVT i_0_420( + .A(aluBypass), .B1(n_0_686), .B2(n_0_569), .ZN(n_0_397) + ); + OAI21_X1_LVT i_0_418( + .A(n_0_396), .B1(n_0_687), .B2(n_0_397), .ZN(n_0_395) + ); + AOI22_X1_LVT i_0_421( + .A1(op1[22]), .A2(n_0_566), .B1(n_0_687), .B2(n_0_565), .ZN(n_0_398) + ); + AOI21_X1_LVT i_0_417( + .A(n_0_395), .B1(op2[22]), .B2(n_0_398), .ZN(n_0_394) + ); + NAND2_X1_LVT i_0_432( + .A1(n_0_728), .A2(n_0_441), .ZN(n_0_409) + ); + AND2_X1_LVT i_0_434( + .A1(n_0_738), .A2(n_0_619), .ZN(n_0_411) + ); + AOI22_X1_LVT i_0_433( + .A1(n_0_693), .A2(n_0_482), .B1(op2[2]), .B2(n_0_411), .ZN(n_0_410) + ); + OAI21_X1_LVT i_0_431( + .A(n_0_409), .B1(n_0_728), .B2(n_0_410), .ZN(n_0_408) + ); + OAI22_X1_LVT i_0_430( + .A1(n_0_701), .A2(n_0_408), .B1(op2[0]), .B2(n_0_422), .ZN(n_0_407) + ); + AOI22_X1_LVT i_0_429( + .A1(n_0_723), .A2(n_0_687), .B1(op2[3]), .B2(n_0_717), .ZN(n_0_406) + ); + AOI22_X1_LVT i_0_428( + .A1(n_0_575), .A2(n_0_406), .B1(op1[26]), .B2(n_0_496), .ZN(n_0_405) + ); + AND2_X1_LVT i_0_427( + .A1(n_0_728), .A2(n_0_405), .ZN(n_0_404) + ); + AOI21_X1_LVT i_0_426( + .A(n_0_404), .B1(op2[1]), .B2(n_0_433), .ZN(n_0_403) + ); + INV_X1_LVT i_0_425( + .A(n_0_403), .ZN(n_0_402) + ); + OAI222_X1_LVT i_0_424( + .A1(n_0_545), .A2(n_0_467), .B1(n_0_701), .B2(n_0_417), .C1(op2[0]), .C2(n_0_402), + .ZN(n_0_401) + ); + NOR2_X1_LVT i_0_496( + .A1(n_0_738), .A2(n_0_691), .ZN(n_0_469) + ); + INV_X1_LVT i_0_495( + .A(n_0_469), .ZN(n_0_468) + ); + NAND3_X1_LVT i_0_423( + .A1(n_0_693), .A2(n_0_468), .A3(n_0_404), .ZN(n_0_400) + ); + OAI21_X1_LVT i_0_422( + .A(n_0_401), .B1(op2[0]), .B2(n_0_400), .ZN(n_0_399) + ); + OAI221_X1_LVT i_0_416( + .A(n_0_394), .B1(n_0_621), .B2(n_0_407), .C1(n_0_579), .C2(n_0_399), .ZN(result[22]) + ); + INV_X1_LVT i_0_759( + .A(op1[21]), .ZN(n_0_726) + ); + AOI22_X1_LVT i_0_399( + .A1(op1[21]), .A2(n_0_566), .B1(n_0_726), .B2(n_0_565), .ZN(n_0_377) + ); + NOR2_X1_LVT i_0_692( + .A1(n_0_726), .A2(op2[21]), .ZN(n_0_659) + ); + AOI222_X1_LVT i_0_398( + .A1(op2[21]), .A2(n_0_377), .B1(n_21), .B2(n_0_581), .C1(n_0_659), .C2(n_0_569), + .ZN(n_0_376) + ); + INV_X1_LVT i_0_397( + .A(n_0_376), .ZN(n_0_375) + ); + INV_X1_LVT i_10_104( + .A(n_10_82), .ZN(n_10_83) + ); + NOR2_X1_LVT i_10_105( + .A1(n_10_81), .A2(n_10_83), .ZN(n_10_84) + ); + XNOR2_X1_LVT i_10_106( + .A(n_10_79), .B(n_10_84), .ZN(n_53) + ); + AOI221_X1_LVT i_0_396( + .A(n_0_375), .B1(n_53), .B2(n_0_580), .C1(op1[21]), .C2(aluBypass), .ZN(n_0_374) + ); + INV_X1_LVT i_0_608( + .A(n_0_577), .ZN(n_0_576) + ); + NAND2_X1_LVT i_0_403( + .A1(op2[0]), .A2(n_0_402), .ZN(n_0_381) + ); + AND2_X1_LVT i_0_410( + .A1(op2[1]), .A2(n_0_419), .ZN(n_0_388) + ); + OAI22_X1_LVT i_0_408( + .A1(n_0_723), .A2(n_0_710), .B1(n_0_726), .B2(op2[3]), .ZN(n_0_386) + ); + AOI22_X1_LVT i_0_407( + .A1(n_0_575), .A2(n_0_386), .B1(op1[25]), .B2(n_0_496), .ZN(n_0_385) + ); + AOI21_X1_LVT i_0_395( + .A(n_0_388), .B1(n_0_728), .B2(n_0_385), .ZN(n_0_373) + ); + OAI211_X1_LVT i_0_394( + .A(n_0_576), .B(n_0_381), .C1(op2[0]), .C2(n_0_373), .ZN(n_0_372) + ); + AOI21_X1_LVT i_0_402( + .A(n_0_381), .B1(n_0_466), .B2(n_0_400), .ZN(n_0_380) + ); + INV_X1_LVT i_0_401( + .A(n_0_380), .ZN(n_0_379) + ); + NOR2_X1_LVT i_0_409( + .A1(n_0_575), .A2(n_0_467), .ZN(n_0_387) + ); + INV_X1_LVT i_0_406( + .A(n_0_385), .ZN(n_0_384) + ); + NOR2_X1_LVT i_0_405( + .A1(n_0_387), .A2(n_0_384), .ZN(n_0_383) + ); + AOI22_X1_LVT i_0_404( + .A1(n_0_467), .A2(n_0_388), .B1(n_0_728), .B2(n_0_383), .ZN(n_0_382) + ); + OAI211_X1_LVT i_0_400( + .A(n_0_544), .B(n_0_379), .C1(op2[0]), .C2(n_0_382), .ZN(n_0_378) + ); + AOI22_X1_LVT i_0_415( + .A1(op1[14]), .A2(n_0_616), .B1(op1[6]), .B2(n_0_618), .ZN(n_0_393) + ); + NOR2_X1_LVT i_0_414( + .A1(n_0_693), .A2(n_0_393), .ZN(n_0_392) + ); + AOI21_X1_LVT i_0_413( + .A(n_0_392), .B1(n_0_693), .B2(n_0_460), .ZN(n_0_391) + ); + OAI22_X1_LVT i_0_412( + .A1(n_0_728), .A2(n_0_391), .B1(op2[1]), .B2(n_0_424), .ZN(n_0_390) + ); + OAI221_X1_LVT i_0_411( + .A(n_0_620), .B1(op2[0]), .B2(n_0_408), .C1(n_0_701), .C2(n_0_390), .ZN(n_0_389) + ); + NAND4_X1_LVT i_0_393( + .A1(n_0_374), .A2(n_0_372), .A3(n_0_378), .A4(n_0_389), .ZN(result[21]) + ); + OAI221_X1_LVT i_0_388( + .A(op2[20]), .B1(n_0_727), .B2(n_0_567), .C1(op1[20]), .C2(n_0_564), .ZN(n_0_367) + ); + NOR2_X1_LVT i_0_691( + .A1(n_0_727), .A2(op2[20]), .ZN(n_0_658) + ); + AOI22_X1_LVT i_0_387( + .A1(op1[20]), .A2(aluBypass), .B1(n_0_658), .B2(n_0_569), .ZN(n_0_366) + ); + XNOR2_X1_LVT i_10_98( + .A(n_10_76), .B(n_10_77), .ZN(n_52) + ); + AOI22_X1_LVT i_0_386( + .A1(n_52), .A2(n_0_580), .B1(n_20), .B2(n_0_581), .ZN(n_0_365) + ); + AOI221_X1_LVT i_0_392( + .A(op2[4]), .B1(n_0_727), .B2(n_0_723), .C1(op2[3]), .C2(n_0_698), .ZN(n_0_371) + ); + AOI22_X1_LVT i_0_391( + .A1(op1[24]), .A2(n_0_496), .B1(n_0_693), .B2(n_0_371), .ZN(n_0_370) + ); + OAI22_X1_LVT i_0_390( + .A1(op2[1]), .A2(n_0_370), .B1(n_0_728), .B2(n_0_405), .ZN(n_0_369) + ); + OAI221_X1_LVT i_0_385( + .A(n_0_576), .B1(n_0_701), .B2(n_0_373), .C1(op2[0]), .C2(n_0_369), .ZN(n_0_364) + ); + AND4_X1_LVT i_0_384( + .A1(n_0_367), .A2(n_0_366), .A3(n_0_365), .A4(n_0_364), .ZN(n_0_363) + ); + AOI22_X1_LVT i_0_383( + .A1(op1[13]), .A2(n_0_616), .B1(op1[5]), .B2(n_0_618), .ZN(n_0_362) + ); + AOI22_X1_LVT i_0_382( + .A1(op2[2]), .A2(n_0_362), .B1(n_0_693), .B2(n_0_443), .ZN(n_0_361) + ); + NAND2_X1_LVT i_0_381( + .A1(op2[1]), .A2(n_0_361), .ZN(n_0_360) + ); + OAI21_X1_LVT i_0_380( + .A(n_0_360), .B1(op2[1]), .B2(n_0_410), .ZN(n_0_359) + ); + OAI221_X1_LVT i_0_379( + .A(n_0_620), .B1(n_0_701), .B2(n_0_359), .C1(op2[0]), .C2(n_0_390), .ZN(n_0_358) + ); + OR2_X1_LVT i_0_389( + .A1(n_0_387), .A2(n_0_369), .ZN(n_0_368) + ); + AOI22_X1_LVT i_0_378( + .A1(op2[0]), .A2(n_0_382), .B1(n_0_701), .B2(n_0_368), .ZN(n_0_357) + ); + OAI211_X1_LVT i_0_377( + .A(n_0_363), .B(n_0_358), .C1(n_0_545), .C2(n_0_357), .ZN(result[20]) + ); + OAI22_X1_LVT i_0_370( + .A1(op2[3]), .A2(n_0_689), .B1(n_0_723), .B2(n_0_688), .ZN(n_0_350) + ); + AND2_X1_LVT i_0_369( + .A1(n_0_738), .A2(n_0_350), .ZN(n_0_349) + ); + AOI22_X1_LVT i_0_368( + .A1(n_0_498), .A2(n_0_420), .B1(n_0_693), .B2(n_0_349), .ZN(n_0_348) + ); + AND2_X1_LVT i_0_367( + .A1(n_0_728), .A2(n_0_348), .ZN(n_0_347) + ); + AOI21_X1_LVT i_0_359( + .A(n_0_347), .B1(op2[1]), .B2(n_0_385), .ZN(n_0_339) + ); + OAI221_X1_LVT i_0_357( + .A(n_0_576), .B1(n_0_701), .B2(n_0_369), .C1(op2[0]), .C2(n_0_339), .ZN(n_0_337) + ); + NAND2_X1_LVT i_0_363( + .A1(n_19), .A2(n_0_581), .ZN(n_0_343) + ); + INV_X1_LVT i_0_723( + .A(op2[19]), .ZN(n_0_690) + ); + AOI221_X1_LVT i_0_364( + .A(n_0_690), .B1(n_0_689), .B2(n_0_565), .C1(op1[19]), .C2(n_0_566), .ZN(n_0_344) + ); + XNOR2_X1_LVT i_10_94( + .A(n_10_73), .B(n_10_74), .ZN(n_51) + ); + AOI221_X1_LVT i_0_361( + .A(n_0_344), .B1(op1[19]), .B2(aluBypass), .C1(n_51), .C2(n_0_580), .ZN(n_0_341) + ); + NAND3_X1_LVT i_0_362( + .A1(n_0_690), .A2(op1[19]), .A3(n_0_569), .ZN(n_0_342) + ); + NAND3_X1_LVT i_0_360( + .A1(n_0_343), .A2(n_0_341), .A3(n_0_342), .ZN(n_0_340) + ); + AOI22_X1_LVT i_0_376( + .A1(op1[12]), .A2(n_0_616), .B1(op1[4]), .B2(n_0_618), .ZN(n_0_356) + ); + OAI22_X1_LVT i_0_375( + .A1(n_0_693), .A2(n_0_356), .B1(op2[2]), .B2(n_0_426), .ZN(n_0_355) + ); + INV_X1_LVT i_0_374( + .A(n_0_355), .ZN(n_0_354) + ); + OAI22_X1_LVT i_0_373( + .A1(op2[1]), .A2(n_0_391), .B1(n_0_728), .B2(n_0_354), .ZN(n_0_353) + ); + AOI22_X1_LVT i_0_372( + .A1(n_0_701), .A2(n_0_359), .B1(op2[0]), .B2(n_0_353), .ZN(n_0_352) + ); + INV_X1_LVT i_0_371( + .A(n_0_352), .ZN(n_0_351) + ); + AOI21_X1_LVT i_0_358( + .A(n_0_340), .B1(n_0_620), .B2(n_0_351), .ZN(n_0_338) + ); + AOI22_X1_LVT i_0_366( + .A1(n_0_468), .A2(n_0_347), .B1(op2[1]), .B2(n_0_383), .ZN(n_0_346) + ); + AOI22_X1_LVT i_0_365( + .A1(n_0_701), .A2(n_0_346), .B1(op2[0]), .B2(n_0_368), .ZN(n_0_345) + ); + OAI211_X1_LVT i_0_356( + .A(n_0_337), .B(n_0_338), .C1(n_0_545), .C2(n_0_345), .ZN(result[19]) + ); + XNOR2_X1_LVT i_10_90( + .A(n_10_70), .B(n_10_71), .ZN(n_50) + ); + NAND2_X1_LVT i_0_342( + .A1(n_50), .A2(n_0_580), .ZN(n_0_323) + ); + OAI21_X1_LVT i_0_343( + .A(n_0_681), .B1(op2[18]), .B2(n_0_568), .ZN(n_0_324) + ); + AOI22_X1_LVT i_0_341( + .A1(op1[18]), .A2(n_0_324), .B1(n_18), .B2(n_0_581), .ZN(n_0_322) + ); + OAI221_X1_LVT i_0_340( + .A(op2[18]), .B1(n_0_705), .B2(n_0_567), .C1(op1[18]), .C2(n_0_564), .ZN(n_0_321) + ); + NAND3_X1_LVT i_0_339( + .A1(n_0_323), .A2(n_0_322), .A3(n_0_321), .ZN(n_0_320) + ); + OAI22_X1_LVT i_0_351( + .A1(op2[3]), .A2(n_0_705), .B1(n_0_723), .B2(n_0_711), .ZN(n_0_332) + ); + AND2_X1_LVT i_0_350( + .A1(n_0_738), .A2(n_0_332), .ZN(n_0_331) + ); + AOI22_X1_LVT i_0_349( + .A1(n_0_498), .A2(n_0_406), .B1(n_0_693), .B2(n_0_331), .ZN(n_0_330) + ); + NAND2_X1_LVT i_0_348( + .A1(n_0_728), .A2(n_0_330), .ZN(n_0_329) + ); + NAND2_X1_LVT i_0_347( + .A1(op2[1]), .A2(n_0_370), .ZN(n_0_328) + ); + AND2_X1_LVT i_0_338( + .A1(n_0_329), .A2(n_0_328), .ZN(n_0_319) + ); + OAI22_X1_LVT i_0_337( + .A1(op2[0]), .A2(n_0_319), .B1(n_0_701), .B2(n_0_339), .ZN(n_0_318) + ); + INV_X1_LVT i_0_336( + .A(n_0_318), .ZN(n_0_317) + ); + AOI21_X1_LVT i_0_335( + .A(n_0_320), .B1(n_0_578), .B2(n_0_317), .ZN(n_0_316) + ); + OAI22_X1_LVT i_0_346( + .A1(n_0_469), .A2(n_0_329), .B1(n_0_387), .B2(n_0_328), .ZN(n_0_327) + ); + NAND2_X1_LVT i_0_344( + .A1(n_0_544), .A2(n_0_346), .ZN(n_0_325) + ); + NAND2_X1_LVT i_0_354( + .A1(n_0_728), .A2(n_0_361), .ZN(n_0_335) + ); + AOI22_X1_LVT i_0_355( + .A1(n_0_612), .A2(n_0_498), .B1(n_0_693), .B2(n_0_411), .ZN(n_0_336) + ); + OAI21_X1_LVT i_0_353( + .A(n_0_335), .B1(n_0_728), .B2(n_0_336), .ZN(n_0_334) + ); + AOI22_X1_LVT i_0_352( + .A1(n_0_701), .A2(n_0_353), .B1(op2[0]), .B2(n_0_334), .ZN(n_0_333) + ); + OAI221_X1_LVT i_0_334( + .A(n_0_316), .B1(n_0_327), .B2(n_0_325), .C1(n_0_621), .C2(n_0_333), .ZN(result[18]) + ); + NAND2_X1_LVT i_0_325( + .A1(n_17), .A2(n_0_581), .ZN(n_0_307) + ); + INV_X1_LVT i_0_765( + .A(op1[17]), .ZN(n_0_732) + ); + AOI22_X1_LVT i_0_324( + .A1(n_0_732), .A2(n_0_565), .B1(op1[17]), .B2(n_0_566), .ZN(n_0_306) + ); + NOR2_X1_LVT i_0_693( + .A1(n_0_732), .A2(op2[17]), .ZN(n_0_660) + ); + XNOR2_X1_LVT i_10_86( + .A(n_10_67), .B(n_10_68), .ZN(n_49) + ); + AOI222_X1_LVT i_0_323( + .A1(op2[17]), .A2(n_0_306), .B1(n_0_660), .B2(n_0_569), .C1(n_49), .C2(n_0_580), + .ZN(n_0_305) + ); + OAI211_X1_LVT i_0_322( + .A(n_0_307), .B(n_0_305), .C1(n_0_732), .C2(n_0_681), .ZN(n_0_304) + ); + AOI22_X1_LVT i_0_331( + .A1(op2[3]), .A2(op1[25]), .B1(op1[17]), .B2(n_0_723), .ZN(n_0_313) + ); + NOR2_X1_LVT i_0_330( + .A1(op2[4]), .A2(n_0_313), .ZN(n_0_312) + ); + AOI22_X1_LVT i_0_329( + .A1(n_0_498), .A2(n_0_386), .B1(n_0_693), .B2(n_0_312), .ZN(n_0_311) + ); + OAI22_X1_LVT i_0_328( + .A1(op2[1]), .A2(n_0_311), .B1(n_0_728), .B2(n_0_348), .ZN(n_0_310) + ); + OR2_X1_LVT i_0_327( + .A1(op2[0]), .A2(n_0_310), .ZN(n_0_309) + ); + OAI21_X1_LVT i_0_321( + .A(n_0_576), .B1(n_0_701), .B2(n_0_319), .ZN(n_0_303) + ); + INV_X1_LVT i_0_320( + .A(n_0_303), .ZN(n_0_302) + ); + AOI21_X1_LVT i_0_319( + .A(n_0_304), .B1(n_0_309), .B2(n_0_302), .ZN(n_0_301) + ); + INV_X1_LVT i_0_345( + .A(n_0_327), .ZN(n_0_326) + ); + OAI22_X1_LVT i_0_326( + .A1(n_0_701), .A2(n_0_326), .B1(n_0_469), .B2(n_0_309), .ZN(n_0_308) + ); + NOR2_X1_LVT i_0_318( + .A1(op2[2]), .A2(n_0_393), .ZN(n_0_300) + ); + AOI21_X1_LVT i_0_317( + .A(n_0_300), .B1(n_0_597), .B2(n_0_498), .ZN(n_0_299) + ); + OAI22_X1_LVT i_0_316( + .A1(n_0_728), .A2(n_0_299), .B1(op2[1]), .B2(n_0_354), .ZN(n_0_298) + ); + OAI22_X1_LVT i_0_315( + .A1(op2[0]), .A2(n_0_334), .B1(n_0_701), .B2(n_0_298), .ZN(n_0_297) + ); + OAI221_X1_LVT i_0_314( + .A(n_0_301), .B1(n_0_545), .B2(n_0_308), .C1(n_0_621), .C2(n_0_297), .ZN(result[17]) + ); + XNOR2_X1_LVT i_10_82( + .A(n_10_64), .B(n_10_65), .ZN(n_48) + ); + AOI22_X1_LVT i_0_301( + .A1(n_48), .A2(n_0_580), .B1(n_16), .B2(n_0_581), .ZN(n_0_284) + ); + NAND2_X1_LVT i_0_333( + .A1(n_0_544), .A2(n_0_469), .ZN(n_0_315) + ); + INV_X1_LVT i_0_332( + .A(n_0_315), .ZN(n_0_314) + ); + OAI21_X1_LVT i_0_302( + .A(n_0_681), .B1(op2[16]), .B2(n_0_568), .ZN(n_0_285) + ); + AOI21_X1_LVT i_0_300( + .A(n_0_314), .B1(op1[16]), .B2(n_0_285), .ZN(n_0_283) + ); + INV_X1_LVT i_0_772( + .A(op1[16]), .ZN(n_0_739) + ); + OAI221_X1_LVT i_0_303( + .A(op2[16]), .B1(op1[16]), .B2(n_0_564), .C1(n_0_739), .C2(n_0_567), .ZN(n_0_286) + ); + NAND3_X1_LVT i_0_299( + .A1(n_0_284), .A2(n_0_283), .A3(n_0_286), .ZN(n_0_282) + ); + INV_X1_LVT i_0_593( + .A(n_0_562), .ZN(n_0_561) + ); + OAI22_X1_LVT i_0_307( + .A1(op1[16]), .A2(op2[3]), .B1(op1[24]), .B2(n_0_723), .ZN(n_0_290) + ); + NOR2_X1_LVT i_0_306( + .A1(op2[4]), .A2(n_0_290), .ZN(n_0_289) + ); + AOI22_X1_LVT i_0_305( + .A1(n_0_693), .A2(n_0_289), .B1(op2[2]), .B2(n_0_371), .ZN(n_0_288) + ); + OAI22_X1_LVT i_0_304( + .A1(n_0_728), .A2(n_0_330), .B1(op2[1]), .B2(n_0_288), .ZN(n_0_287) + ); + AOI221_X1_LVT i_0_298( + .A(n_0_282), .B1(n_0_547), .B2(n_0_310), .C1(n_0_561), .C2(n_0_287), .ZN(n_0_281) + ); + INV_X1_LVT i_0_762( + .A(op1[1]), .ZN(n_0_729) + ); + OAI22_X1_LVT i_0_313( + .A1(n_0_722), .A2(n_0_615), .B1(n_0_729), .B2(n_0_617), .ZN(n_0_296) + ); + NAND2_X1_LVT i_0_312( + .A1(op2[2]), .A2(n_0_296), .ZN(n_0_295) + ); + OAI21_X1_LVT i_0_311( + .A(n_0_295), .B1(op2[2]), .B2(n_0_362), .ZN(n_0_294) + ); + NAND2_X1_LVT i_0_310( + .A1(op2[1]), .A2(n_0_294), .ZN(n_0_293) + ); + OAI21_X1_LVT i_0_309( + .A(n_0_293), .B1(op2[1]), .B2(n_0_336), .ZN(n_0_292) + ); + OAI22_X1_LVT i_0_308( + .A1(op2[0]), .A2(n_0_298), .B1(n_0_701), .B2(n_0_292), .ZN(n_0_291) + ); + OAI21_X1_LVT i_0_297( + .A(n_0_281), .B1(n_0_621), .B2(n_0_291), .ZN(result[16]) + ); + OAI221_X1_LVT i_0_286( + .A(op2[15]), .B1(n_0_734), .B2(n_0_567), .C1(op1[15]), .C2(n_0_564), .ZN(n_0_270) + ); + AOI21_X1_LVT i_0_288( + .A(n_0_314), .B1(n_15), .B2(n_0_581), .ZN(n_0_272) + ); + INV_X1_LVT i_0_287( + .A(n_0_272), .ZN(n_0_271) + ); + XNOR2_X1_LVT i_10_78( + .A(n_10_61), .B(n_10_62), .ZN(n_47) + ); + OAI21_X1_LVT i_0_285( + .A(n_0_681), .B1(op2[15]), .B2(n_0_568), .ZN(n_0_269) + ); + AOI221_X1_LVT i_0_284( + .A(n_0_271), .B1(n_47), .B2(n_0_580), .C1(op1[15]), .C2(n_0_269), .ZN(n_0_268) + ); + AOI22_X1_LVT i_0_296( + .A1(op1[8]), .A2(n_0_616), .B1(op1[0]), .B2(n_0_618), .ZN(n_0_280) + ); + AOI22_X1_LVT i_0_295( + .A1(op2[2]), .A2(n_0_280), .B1(n_0_693), .B2(n_0_356), .ZN(n_0_279) + ); + NAND2_X1_LVT i_0_294( + .A1(op2[1]), .A2(n_0_279), .ZN(n_0_278) + ); + OAI21_X1_LVT i_0_293( + .A(n_0_278), .B1(op2[1]), .B2(n_0_299), .ZN(n_0_277) + ); + OAI221_X1_LVT i_0_292( + .A(n_0_620), .B1(n_0_701), .B2(n_0_277), .C1(op2[0]), .C2(n_0_292), .ZN(n_0_276) + ); + OAI222_X1_LVT i_0_291( + .A1(n_0_719), .A2(n_0_617), .B1(n_0_691), .B2(n_0_605), .C1(n_0_734), .C2(n_0_615), + .ZN(n_0_275) + ); + OAI22_X1_LVT i_0_290( + .A1(n_0_693), .A2(n_0_349), .B1(op2[2]), .B2(n_0_275), .ZN(n_0_274) + ); + OAI22_X1_LVT i_0_289( + .A1(op2[1]), .A2(n_0_274), .B1(n_0_728), .B2(n_0_311), .ZN(n_0_273) + ); + AOI22_X1_LVT i_0_283( + .A1(n_0_561), .A2(n_0_273), .B1(n_0_547), .B2(n_0_287), .ZN(n_0_267) + ); + NAND4_X1_LVT i_0_282( + .A1(n_0_270), .A2(n_0_268), .A3(n_0_276), .A4(n_0_267), .ZN(result[15]) + ); + NOR2_X1_LVT i_0_278( + .A1(op2[0]), .A2(n_0_277), .ZN(n_0_263) + ); + NAND2_X1_LVT i_0_281( + .A1(n_0_612), .A2(n_0_575), .ZN(n_0_266) + ); + OAI21_X1_LVT i_0_280( + .A(n_0_266), .B1(n_0_713), .B2(n_0_497), .ZN(n_0_265) + ); + AOI22_X1_LVT i_0_279( + .A1(op2[1]), .A2(n_0_265), .B1(n_0_728), .B2(n_0_294), .ZN(n_0_264) + ); + AOI211_X1_LVT i_0_277( + .A(n_0_263), .B(n_0_621), .C1(op2[0]), .C2(n_0_264), .ZN(n_0_262) + ); + INV_X1_LVT i_0_754( + .A(op1[14]), .ZN(n_0_721) + ); + OAI21_X1_LVT i_0_273( + .A(op2[14]), .B1(n_0_721), .B2(n_0_567), .ZN(n_0_258) + ); + AOI21_X1_LVT i_0_272( + .A(n_0_258), .B1(n_0_721), .B2(n_0_565), .ZN(n_0_257) + ); + XNOR2_X1_LVT i_10_74( + .A(n_10_58), .B(n_10_59), .ZN(n_46) + ); + OAI21_X1_LVT i_0_276( + .A(n_0_681), .B1(op2[14]), .B2(n_0_568), .ZN(n_0_261) + ); + AOI222_X1_LVT i_0_275( + .A1(n_14), .A2(n_0_581), .B1(n_46), .B2(n_0_580), .C1(op1[14]), .C2(n_0_261), + .ZN(n_0_260) + ); + INV_X1_LVT i_0_274( + .A(n_0_260), .ZN(n_0_259) + ); + OAI222_X1_LVT i_0_271( + .A1(n_0_717), .A2(n_0_605), .B1(n_0_687), .B2(n_0_617), .C1(n_0_721), .C2(n_0_615), + .ZN(n_0_256) + ); + OAI22_X1_LVT i_0_270( + .A1(n_0_693), .A2(n_0_331), .B1(op2[2]), .B2(n_0_256), .ZN(n_0_255) + ); + AND2_X1_LVT i_0_269( + .A1(n_0_728), .A2(n_0_255), .ZN(n_0_254) + ); + NOR3_X1_LVT i_0_265( + .A1(op2[3]), .A2(op2[2]), .A3(op2[0]), .ZN(n_0_250) + ); + AOI21_X1_LVT i_0_268( + .A(n_0_254), .B1(op2[1]), .B2(n_0_288), .ZN(n_0_253) + ); + OAI22_X1_LVT i_0_266( + .A1(op2[0]), .A2(n_0_253), .B1(n_0_701), .B2(n_0_273), .ZN(n_0_251) + ); + AOI221_X1_LVT i_0_259( + .A(n_0_579), .B1(n_0_254), .B2(n_0_250), .C1(n_0_315), .C2(n_0_251), .ZN(n_0_244) + ); + OR4_X1_LVT i_0_258( + .A1(n_0_262), .A2(n_0_257), .A3(n_0_259), .A4(n_0_244), .ZN(result[14]) + ); + OAI221_X1_LVT i_0_245( + .A(op2[13]), .B1(op1[13]), .B2(n_0_564), .C1(n_0_714), .C2(n_0_567), .ZN(n_0_231) + ); + NAND2_X1_LVT i_0_244( + .A1(n_13), .A2(n_0_581), .ZN(n_0_230) + ); + OAI211_X1_LVT i_0_243( + .A(n_0_231), .B(n_0_230), .C1(n_0_714), .C2(n_0_681), .ZN(n_0_229) + ); + XNOR2_X1_LVT i_10_70( + .A(n_10_55), .B(n_10_56), .ZN(n_45) + ); + NOR2_X1_LVT i_0_695( + .A1(op2[13]), .A2(n_0_714), .ZN(n_0_662) + ); + AOI221_X1_LVT i_0_242( + .A(n_0_229), .B1(n_45), .B2(n_0_580), .C1(n_0_662), .C2(n_0_569), .ZN(n_0_228) + ); + INV_X1_LVT i_0_267( + .A(n_0_253), .ZN(n_0_252) + ); + OAI222_X1_LVT i_0_257( + .A1(n_0_714), .A2(n_0_615), .B1(n_0_726), .B2(n_0_617), .C1(n_0_710), .C2(n_0_605), + .ZN(n_0_243) + ); + OAI22_X1_LVT i_0_256( + .A1(n_0_693), .A2(n_0_312), .B1(op2[2]), .B2(n_0_243), .ZN(n_0_242) + ); + NAND2_X1_LVT i_0_255( + .A1(n_0_728), .A2(n_0_242), .ZN(n_0_241) + ); + NAND2_X1_LVT i_0_254( + .A1(op2[1]), .A2(n_0_274), .ZN(n_0_240) + ); + NAND2_X1_LVT i_0_241( + .A1(n_0_241), .A2(n_0_240), .ZN(n_0_227) + ); + OAI221_X1_LVT i_0_240( + .A(n_0_228), .B1(n_0_548), .B2(n_0_252), .C1(n_0_562), .C2(n_0_227), .ZN(n_0_226) + ); + NAND2_X1_LVT i_0_249( + .A1(n_0_728), .A2(n_0_279), .ZN(n_0_235) + ); + AOI22_X1_LVT i_0_250( + .A1(n_0_597), .A2(n_0_575), .B1(op1[6]), .B2(n_0_496), .ZN(n_0_236) + ); + OAI21_X1_LVT i_0_248( + .A(n_0_235), .B1(n_0_728), .B2(n_0_236), .ZN(n_0_234) + ); + INV_X1_LVT i_0_247( + .A(n_0_234), .ZN(n_0_233) + ); + AOI221_X1_LVT i_0_246( + .A(n_0_621), .B1(op2[0]), .B2(n_0_233), .C1(n_0_701), .C2(n_0_264), .ZN(n_0_232) + ); + NAND2_X1_LVT i_0_264( + .A1(op2[3]), .A2(n_0_469), .ZN(n_0_249) + ); + AOI21_X1_LVT i_0_262( + .A(n_0_468), .B1(n_0_693), .B2(n_0_249), .ZN(n_0_247) + ); + INV_X1_LVT i_0_261( + .A(n_0_247), .ZN(n_0_246) + ); + OAI211_X1_LVT i_0_260( + .A(n_0_252), .B(n_0_246), .C1(n_0_468), .C2(n_0_254), .ZN(n_0_245) + ); + OAI221_X1_LVT i_0_253( + .A(n_0_544), .B1(n_0_247), .B2(n_0_241), .C1(n_0_469), .C2(n_0_240), .ZN(n_0_239) + ); + INV_X1_LVT i_0_252( + .A(n_0_239), .ZN(n_0_238) + ); + AOI211_X1_LVT i_0_239( + .A(n_0_226), .B(n_0_232), .C1(n_0_245), .C2(n_0_238), .ZN(n_0_225) + ); + INV_X1_LVT i_0_238( + .A(n_0_225), .ZN(result[13]) + ); + OAI221_X1_LVT i_0_232( + .A(op2[12]), .B1(n_0_696), .B2(n_0_567), .C1(op1[12]), .C2(n_0_564), .ZN(n_0_219) + ); + OAI21_X1_LVT i_0_231( + .A(n_0_681), .B1(op2[12]), .B2(n_0_568), .ZN(n_0_218) + ); + XNOR2_X1_LVT i_10_66( + .A(n_10_52), .B(n_10_53), .ZN(n_44) + ); + AOI222_X1_LVT i_0_230( + .A1(n_12), .A2(n_0_581), .B1(op1[12]), .B2(n_0_218), .C1(n_44), .C2(n_0_580), + .ZN(n_0_217) + ); + OAI21_X1_LVT i_0_234( + .A(n_0_620), .B1(op2[1]), .B2(n_0_265), .ZN(n_0_221) + ); + INV_X1_LVT i_0_763( + .A(op1[5]), .ZN(n_0_730) + ); + OAI21_X1_LVT i_0_236( + .A(op2[2]), .B1(n_0_730), .B2(n_0_615), .ZN(n_0_223) + ); + OAI21_X1_LVT i_0_235( + .A(n_0_223), .B1(op2[2]), .B2(n_0_296), .ZN(n_0_222) + ); + AOI21_X1_LVT i_0_233( + .A(n_0_221), .B1(op2[1]), .B2(n_0_222), .ZN(n_0_220) + ); + NOR2_X1_LVT i_0_237( + .A1(n_0_577), .A2(n_0_227), .ZN(n_0_224) + ); + NOR4_X1_LVT i_0_223( + .A1(n_0_701), .A2(n_0_220), .A3(n_0_224), .A4(n_0_238), .ZN(n_0_210) + ); + NAND2_X1_LVT i_0_224( + .A1(n_0_544), .A2(n_0_247), .ZN(n_0_211) + ); + NAND2_X1_LVT i_0_222( + .A1(n_0_701), .A2(n_0_211), .ZN(n_0_209) + ); + OAI22_X1_LVT i_0_229( + .A1(op2[4]), .A2(n_0_696), .B1(n_0_738), .B2(n_0_698), .ZN(n_0_216) + ); + INV_X1_LVT i_0_228( + .A(n_0_216), .ZN(n_0_215) + ); + OAI22_X1_LVT i_0_227( + .A1(n_0_727), .A2(n_0_617), .B1(op2[3]), .B2(n_0_215), .ZN(n_0_214) + ); + OAI22_X1_LVT i_0_226( + .A1(n_0_693), .A2(n_0_289), .B1(op2[2]), .B2(n_0_214), .ZN(n_0_213) + ); + OAI22_X1_LVT i_0_225( + .A1(op2[1]), .A2(n_0_213), .B1(n_0_728), .B2(n_0_255), .ZN(n_0_212) + ); + AOI221_X1_LVT i_0_221( + .A(n_0_209), .B1(n_0_578), .B2(n_0_212), .C1(n_0_620), .C2(n_0_234), .ZN(n_0_208) + ); + OAI211_X1_LVT i_0_220( + .A(n_0_219), .B(n_0_217), .C1(n_0_210), .C2(n_0_208), .ZN(result[12]) + ); + OAI21_X1_LVT i_0_209( + .A(n_0_681), .B1(op2[11]), .B2(n_0_568), .ZN(n_0_197) + ); + AOI22_X1_LVT i_0_208( + .A1(n_11), .A2(n_0_581), .B1(op1[11]), .B2(n_0_197), .ZN(n_0_196) + ); + NAND2_X1_LVT i_0_207( + .A1(n_0_211), .A2(n_0_196), .ZN(n_0_195) + ); + AOI22_X1_LVT i_0_210( + .A1(op1[11]), .A2(n_0_566), .B1(n_0_706), .B2(n_0_565), .ZN(n_0_198) + ); + XNOR2_X1_LVT i_10_62( + .A(n_10_49), .B(n_10_50), .ZN(n_43) + ); + AOI221_X1_LVT i_0_206( + .A(n_0_195), .B1(op2[11]), .B2(n_0_198), .C1(n_43), .C2(n_0_580), .ZN(n_0_194) + ); + AOI221_X1_LVT i_0_215( + .A(op2[3]), .B1(n_0_738), .B2(n_0_706), .C1(op2[4]), .C2(n_0_688), .ZN(n_0_203) + ); + AOI21_X1_LVT i_0_214( + .A(n_0_203), .B1(op1[19]), .B2(n_0_618), .ZN(n_0_202) + ); + NAND2_X1_LVT i_0_213( + .A1(n_0_693), .A2(n_0_202), .ZN(n_0_201) + ); + OAI21_X1_LVT i_0_212( + .A(n_0_201), .B1(n_0_693), .B2(n_0_275), .ZN(n_0_200) + ); + OAI22_X1_LVT i_0_211( + .A1(n_0_728), .A2(n_0_242), .B1(op2[1]), .B2(n_0_200), .ZN(n_0_199) + ); + AOI22_X1_LVT i_0_205( + .A1(n_0_561), .A2(n_0_199), .B1(n_0_701), .B2(n_0_220), .ZN(n_0_193) + ); + NOR2_X1_LVT i_0_219( + .A1(op2[2]), .A2(n_0_280), .ZN(n_0_207) + ); + AOI21_X1_LVT i_0_218( + .A(n_0_207), .B1(op1[4]), .B2(n_0_496), .ZN(n_0_206) + ); + AOI22_X1_LVT i_0_217( + .A1(n_0_728), .A2(n_0_236), .B1(op2[1]), .B2(n_0_206), .ZN(n_0_205) + ); + AOI22_X1_LVT i_0_216( + .A1(n_0_578), .A2(n_0_212), .B1(n_0_620), .B2(n_0_205), .ZN(n_0_204) + ); + OAI211_X1_LVT i_0_204( + .A(n_0_194), .B(n_0_193), .C1(n_0_701), .C2(n_0_204), .ZN(result[11]) + ); + AOI22_X1_LVT i_0_194( + .A1(n_0_654), .A2(n_0_498), .B1(op1[7]), .B2(n_0_573), .ZN(n_0_183) + ); + OAI22_X1_LVT i_0_193( + .A1(n_0_728), .A2(n_0_183), .B1(op2[1]), .B2(n_0_222), .ZN(n_0_182) + ); + AOI22_X1_LVT i_0_192( + .A1(op2[0]), .A2(n_0_182), .B1(n_0_701), .B2(n_0_205), .ZN(n_0_181) + ); + NOR2_X1_LVT i_0_191( + .A1(n_0_621), .A2(n_0_181), .ZN(n_0_180) + ); + AOI22_X1_LVT i_0_190( + .A1(op1[10]), .A2(n_0_566), .B1(n_0_733), .B2(n_0_565), .ZN(n_0_179) + ); + XNOR2_X1_LVT i_10_58( + .A(n_10_46), .B(n_10_47), .ZN(n_42) + ); + AOI22_X1_LVT i_0_188( + .A1(op2[10]), .A2(n_0_179), .B1(n_42), .B2(n_0_580), .ZN(n_0_177) + ); + OAI21_X1_LVT i_0_189( + .A(n_0_681), .B1(op2[10]), .B2(n_0_568), .ZN(n_0_178) + ); + AOI22_X1_LVT i_0_187( + .A1(n_10), .A2(n_0_581), .B1(op1[10]), .B2(n_0_178), .ZN(n_0_176) + ); + NAND2_X1_LVT i_0_186( + .A1(n_0_177), .A2(n_0_176), .ZN(n_0_175) + ); + NOR2_X1_LVT i_0_203( + .A1(n_0_701), .A2(n_0_199), .ZN(n_0_192) + ); + NOR2_X1_LVT i_0_200( + .A1(n_0_693), .A2(n_0_256), .ZN(n_0_189) + ); + AOI221_X1_LVT i_0_202( + .A(n_0_596), .B1(op1[10]), .B2(n_0_616), .C1(op1[26]), .C2(n_0_606), .ZN(n_0_191) + ); + AOI21_X1_LVT i_0_199( + .A(n_0_189), .B1(n_0_693), .B2(n_0_191), .ZN(n_0_188) + ); + OR2_X1_LVT i_0_198( + .A1(op2[1]), .A2(n_0_188), .ZN(n_0_187) + ); + NAND2_X1_LVT i_0_197( + .A1(op2[1]), .A2(n_0_213), .ZN(n_0_186) + ); + NAND2_X1_LVT i_0_185( + .A1(n_0_187), .A2(n_0_186), .ZN(n_0_174) + ); + AOI211_X1_LVT i_0_184( + .A(n_0_577), .B(n_0_192), .C1(n_0_701), .C2(n_0_174), .ZN(n_0_173) + ); + INV_X1_LVT i_0_263( + .A(n_0_249), .ZN(n_0_248) + ); + OAI22_X1_LVT i_0_196( + .A1(n_0_248), .A2(n_0_187), .B1(n_0_247), .B2(n_0_186), .ZN(n_0_185) + ); + AOI221_X1_LVT i_0_195( + .A(n_0_545), .B1(n_0_246), .B2(n_0_192), .C1(n_0_701), .C2(n_0_185), .ZN(n_0_184) + ); + OR4_X1_LVT i_0_183( + .A1(n_0_180), .A2(n_0_175), .A3(n_0_173), .A4(n_0_184), .ZN(result[10]) + ); + INV_X1_LVT i_0_753( + .A(op2[9]), .ZN(n_0_720) + ); + AOI221_X1_LVT i_0_171( + .A(n_0_720), .B1(op1[9]), .B2(n_0_566), .C1(n_0_722), .C2(n_0_565), .ZN(n_0_161) + ); + XNOR2_X1_LVT i_10_54( + .A(n_10_43), .B(n_10_44), .ZN(n_41) + ); + AOI22_X1_LVT i_0_172( + .A1(n_9), .A2(n_0_581), .B1(n_41), .B2(n_0_580), .ZN(n_0_162) + ); + AOI21_X1_LVT i_0_170( + .A(aluBypass), .B1(n_0_720), .B2(n_0_569), .ZN(n_0_160) + ); + OAI21_X1_LVT i_0_169( + .A(n_0_162), .B1(n_0_722), .B2(n_0_160), .ZN(n_0_159) + ); + OAI222_X1_LVT i_0_182( + .A1(n_0_722), .A2(n_0_615), .B1(n_0_699), .B2(n_0_605), .C1(n_0_732), .C2(n_0_617), + .ZN(n_0_172) + ); + AOI22_X1_LVT i_0_181( + .A1(n_0_693), .A2(n_0_172), .B1(op2[2]), .B2(n_0_243), .ZN(n_0_171) + ); + NAND2_X1_LVT i_0_180( + .A1(n_0_728), .A2(n_0_171), .ZN(n_0_170) + ); + NAND2_X1_LVT i_0_179( + .A1(op2[1]), .A2(n_0_200), .ZN(n_0_169) + ); + OAI22_X1_LVT i_0_178( + .A1(n_0_248), .A2(n_0_170), .B1(n_0_247), .B2(n_0_169), .ZN(n_0_168) + ); + NOR3_X1_LVT i_0_177( + .A1(n_0_545), .A2(n_0_168), .A3(n_0_185), .ZN(n_0_167) + ); + NOR2_X1_LVT i_0_251( + .A1(n_0_704), .A2(n_0_615), .ZN(n_0_237) + ); + OAI22_X1_LVT i_0_176( + .A1(op1[2]), .A2(n_0_693), .B1(n_0_496), .B2(n_0_237), .ZN(n_0_166) + ); + OAI22_X1_LVT i_0_175( + .A1(op2[1]), .A2(n_0_206), .B1(n_0_728), .B2(n_0_166), .ZN(n_0_165) + ); + OAI221_X1_LVT i_0_174( + .A(n_0_620), .B1(op2[0]), .B2(n_0_182), .C1(n_0_701), .C2(n_0_165), .ZN(n_0_164) + ); + NAND2_X1_LVT i_0_173( + .A1(n_0_170), .A2(n_0_169), .ZN(n_0_163) + ); + OAI221_X1_LVT i_0_168( + .A(n_0_164), .B1(n_0_562), .B2(n_0_163), .C1(n_0_548), .C2(n_0_174), .ZN(n_0_158) + ); + OR4_X1_LVT i_0_167( + .A1(n_0_161), .A2(n_0_159), .A3(n_0_167), .A4(n_0_158), .ZN(result[9]) + ); + OAI21_X1_LVT i_0_160( + .A(n_0_693), .B1(n_0_730), .B2(n_0_615), .ZN(n_0_151) + ); + OAI21_X1_LVT i_0_159( + .A(op2[2]), .B1(n_0_729), .B2(n_0_615), .ZN(n_0_150) + ); + AND2_X1_LVT i_0_158( + .A1(n_0_151), .A2(n_0_150), .ZN(n_0_149) + ); + NAND2_X1_LVT i_0_157( + .A1(op2[1]), .A2(n_0_149), .ZN(n_0_148) + ); + OAI21_X1_LVT i_0_156( + .A(n_0_148), .B1(op2[1]), .B2(n_0_183), .ZN(n_0_147) + ); + OAI22_X1_LVT i_0_155( + .A1(op2[0]), .A2(n_0_165), .B1(n_0_701), .B2(n_0_147), .ZN(n_0_146) + ); + NOR2_X1_LVT i_0_154( + .A1(n_0_621), .A2(n_0_146), .ZN(n_0_145) + ); + INV_X1_LVT i_0_773( + .A(op1[8]), .ZN(n_0_740) + ); + NOR2_X1_LVT i_0_688( + .A1(n_0_740), .A2(op2[8]), .ZN(n_0_655) + ); + AOI22_X1_LVT i_0_153( + .A1(op1[8]), .A2(aluBypass), .B1(n_0_655), .B2(n_0_569), .ZN(n_0_144) + ); + OAI221_X1_LVT i_0_152( + .A(op2[8]), .B1(op1[8]), .B2(n_0_564), .C1(n_0_740), .C2(n_0_567), .ZN(n_0_143) + ); + XNOR2_X1_LVT i_10_51( + .A(n_10_39), .B(n_10_42), .ZN(n_40) + ); + AOI22_X1_LVT i_0_151( + .A1(n_40), .A2(n_0_580), .B1(n_8), .B2(n_0_581), .ZN(n_0_142) + ); + NAND3_X1_LVT i_0_150( + .A1(n_0_144), .A2(n_0_143), .A3(n_0_142), .ZN(n_0_141) + ); + OAI222_X1_LVT i_0_166( + .A1(n_0_740), .A2(n_0_615), .B1(n_0_739), .B2(n_0_617), .C1(n_0_736), .C2(n_0_605), + .ZN(n_0_157) + ); + OAI22_X1_LVT i_0_165( + .A1(op2[2]), .A2(n_0_157), .B1(n_0_693), .B2(n_0_214), .ZN(n_0_156) + ); + NOR2_X1_LVT i_0_164( + .A1(op2[1]), .A2(n_0_156), .ZN(n_0_155) + ); + AOI21_X1_LVT i_0_163( + .A(n_0_155), .B1(op2[1]), .B2(n_0_188), .ZN(n_0_154) + ); + AND2_X1_LVT i_0_162( + .A1(n_0_701), .A2(n_0_154), .ZN(n_0_153) + ); + AOI211_X1_LVT i_0_149( + .A(n_0_577), .B(n_0_153), .C1(op2[0]), .C2(n_0_163), .ZN(n_0_140) + ); + AOI221_X1_LVT i_0_161( + .A(n_0_545), .B1(op2[0]), .B2(n_0_168), .C1(n_0_249), .C2(n_0_153), .ZN(n_0_152) + ); + OR4_X1_LVT i_0_148( + .A1(n_0_145), .A2(n_0_141), .A3(n_0_140), .A4(n_0_152), .ZN(result[8]) + ); + AOI22_X1_LVT i_0_138( + .A1(op1[4]), .A2(n_0_573), .B1(op1[0]), .B2(n_0_496), .ZN(n_0_130) + ); + AOI22_X1_LVT i_0_137( + .A1(op2[1]), .A2(n_0_130), .B1(n_0_728), .B2(n_0_166), .ZN(n_0_129) + ); + OAI22_X1_LVT i_0_136( + .A1(n_0_701), .A2(n_0_129), .B1(op2[0]), .B2(n_0_147), .ZN(n_0_128) + ); + NOR2_X1_LVT i_0_135( + .A1(n_0_621), .A2(n_0_128), .ZN(n_0_127) + ); + OAI221_X1_LVT i_0_139( + .A(op2[7]), .B1(n_0_713), .B2(n_0_567), .C1(op1[7]), .C2(n_0_564), .ZN(n_0_131) + ); + INV_X1_LVT i_10_44( + .A(n_10_36), .ZN(n_10_37) + ); + NOR2_X1_LVT i_10_45( + .A1(n_10_35), .A2(n_10_37), .ZN(n_10_38) + ); + XNOR2_X1_LVT i_10_46( + .A(n_10_33), .B(n_10_38), .ZN(n_39) + ); + AOI22_X1_LVT i_0_141( + .A1(n_7), .A2(n_0_581), .B1(n_39), .B2(n_0_580), .ZN(n_0_133) + ); + INV_X1_LVT i_0_745( + .A(op2[7]), .ZN(n_0_712) + ); + AOI21_X1_LVT i_0_140( + .A(aluBypass), .B1(n_0_712), .B2(n_0_569), .ZN(n_0_132) + ); + OAI211_X1_LVT i_0_133( + .A(n_0_131), .B(n_0_133), .C1(n_0_713), .C2(n_0_132), .ZN(n_0_125) + ); + OAI22_X1_LVT i_0_147( + .A1(n_0_734), .A2(n_0_617), .B1(n_0_713), .B2(n_0_615), .ZN(n_0_139) + ); + AOI211_X1_LVT i_0_146( + .A(n_0_139), .B(n_0_248), .C1(op1[23]), .C2(n_0_606), .ZN(n_0_138) + ); + OAI22_X1_LVT i_0_145( + .A1(n_0_693), .A2(n_0_202), .B1(op2[2]), .B2(n_0_138), .ZN(n_0_137) + ); + NOR2_X1_LVT i_0_144( + .A1(op2[1]), .A2(n_0_137), .ZN(n_0_136) + ); + AOI21_X1_LVT i_0_143( + .A(n_0_136), .B1(op2[1]), .B2(n_0_171), .ZN(n_0_135) + ); + NAND2_X1_LVT i_0_142( + .A1(n_0_561), .A2(n_0_135), .ZN(n_0_134) + ); + OAI221_X1_LVT i_0_134( + .A(n_0_134), .B1(n_0_548), .B2(n_0_154), .C1(n_0_545), .C2(n_0_249), .ZN(n_0_126) + ); + OR3_X1_LVT i_0_132( + .A1(n_0_127), .A2(n_0_125), .A3(n_0_126), .ZN(result[7]) + ); + NAND2_X1_LVT i_0_124( + .A1(n_0_728), .A2(n_0_149), .ZN(n_0_117) + ); + OAI21_X1_LVT i_0_123( + .A(n_0_117), .B1(n_0_724), .B2(n_0_531), .ZN(n_0_116) + ); + OAI22_X1_LVT i_0_122( + .A1(n_0_701), .A2(n_0_116), .B1(op2[0]), .B2(n_0_129), .ZN(n_0_115) + ); + NOR2_X1_LVT i_0_121( + .A1(n_0_621), .A2(n_0_115), .ZN(n_0_114) + ); + XNOR2_X1_LVT i_10_38( + .A(n_10_30), .B(n_10_31), .ZN(n_38) + ); + AOI22_X1_LVT i_0_119( + .A1(n_6), .A2(n_0_581), .B1(n_38), .B2(n_0_580), .ZN(n_0_112) + ); + INV_X1_LVT i_0_735( + .A(op2[6]), .ZN(n_0_702) + ); + AOI21_X1_LVT i_0_120( + .A(aluBypass), .B1(n_0_702), .B2(n_0_569), .ZN(n_0_113) + ); + OAI21_X1_LVT i_0_118( + .A(n_0_112), .B1(n_0_704), .B2(n_0_113), .ZN(n_0_111) + ); + AOI221_X1_LVT i_0_117( + .A(n_0_702), .B1(n_0_704), .B2(n_0_565), .C1(op1[6]), .C2(n_0_566), .ZN(n_0_110) + ); + NOR3_X1_LVT i_0_116( + .A1(n_0_114), .A2(n_0_111), .A3(n_0_110), .ZN(n_0_109) + ); + AOI221_X1_LVT i_0_131( + .A(n_0_237), .B1(op1[14]), .B2(n_0_618), .C1(op2[4]), .C2(n_0_406), .ZN(n_0_124) + ); + NAND2_X1_LVT i_0_130( + .A1(n_0_693), .A2(n_0_124), .ZN(n_0_123) + ); + INV_X1_LVT i_0_201( + .A(n_0_191), .ZN(n_0_190) + ); + OAI21_X1_LVT i_0_129( + .A(n_0_123), .B1(n_0_693), .B2(n_0_190), .ZN(n_0_122) + ); + AOI22_X1_LVT i_0_128( + .A1(n_0_728), .A2(n_0_122), .B1(op2[1]), .B2(n_0_156), .ZN(n_0_121) + ); + INV_X1_LVT i_0_127( + .A(n_0_121), .ZN(n_0_120) + ); + OAI21_X1_LVT i_0_126( + .A(n_0_248), .B1(op2[1]), .B2(n_0_123), .ZN(n_0_119) + ); + AND2_X1_LVT i_0_125( + .A1(n_0_120), .A2(n_0_119), .ZN(n_0_118) + ); + NOR2_X1_LVT i_0_115( + .A1(n_0_545), .A2(n_0_118), .ZN(n_0_108) + ); + AOI21_X1_LVT i_0_114( + .A(n_0_108), .B1(n_0_576), .B2(n_0_121), .ZN(n_0_107) + ); + AOI22_X1_LVT i_0_113( + .A1(n_0_544), .A2(n_0_248), .B1(n_0_578), .B2(n_0_135), .ZN(n_0_106) + ); + OAI221_X1_LVT i_0_112( + .A(n_0_109), .B1(op2[0]), .B2(n_0_107), .C1(n_0_701), .C2(n_0_106), .ZN(result[6]) + ); + OAI221_X1_LVT i_0_100( + .A(op2[5]), .B1(op1[5]), .B2(n_0_564), .C1(n_0_730), .C2(n_0_567), .ZN(n_0_94) + ); + INV_X1_LVT i_0_764( + .A(op2[5]), .ZN(n_0_731) + ); + AOI21_X1_LVT i_0_99( + .A(aluBypass), .B1(n_0_731), .B2(n_0_569), .ZN(n_0_93) + ); + NOR2_X1_LVT i_0_98( + .A1(n_0_730), .A2(n_0_93), .ZN(n_0_92) + ); + XNOR2_X1_LVT i_10_35( + .A(n_10_26), .B(n_10_29), .ZN(n_37) + ); + AOI221_X1_LVT i_0_97( + .A(n_0_92), .B1(n_37), .B2(n_0_580), .C1(n_5), .C2(n_0_581), .ZN(n_0_91) + ); + OAI22_X1_LVT i_0_102( + .A1(n_0_694), .A2(n_0_531), .B1(op2[1]), .B2(n_0_130), .ZN(n_0_96) + ); + OAI221_X1_LVT i_0_101( + .A(n_0_620), .B1(n_0_701), .B2(n_0_96), .C1(op2[0]), .C2(n_0_116), .ZN(n_0_95) + ); + NAND3_X1_LVT i_0_111( + .A1(n_0_544), .A2(n_0_248), .A3(op2[2]), .ZN(n_0_105) + ); + NAND2_X1_LVT i_0_110( + .A1(op2[4]), .A2(n_0_386), .ZN(n_0_104) + ); + OAI21_X1_LVT i_0_109( + .A(n_0_104), .B1(n_0_714), .B2(n_0_617), .ZN(n_0_103) + ); + OAI22_X1_LVT i_0_108( + .A1(n_0_151), .A2(n_0_103), .B1(n_0_693), .B2(n_0_172), .ZN(n_0_102) + ); + NOR2_X1_LVT i_0_107( + .A1(op2[1]), .A2(n_0_102), .ZN(n_0_101) + ); + AOI21_X1_LVT i_0_106( + .A(n_0_101), .B1(op2[1]), .B2(n_0_137), .ZN(n_0_100) + ); + OAI21_X1_LVT i_0_105( + .A(n_0_105), .B1(n_0_579), .B2(n_0_100), .ZN(n_0_99) + ); + AOI21_X1_LVT i_0_104( + .A(n_0_118), .B1(n_0_682), .B2(n_0_120), .ZN(n_0_98) + ); + OAI22_X1_LVT i_0_103( + .A1(n_0_547), .A2(n_0_99), .B1(n_0_701), .B2(n_0_98), .ZN(n_0_97) + ); + NAND4_X1_LVT i_0_96( + .A1(n_0_94), .A2(n_0_91), .A3(n_0_95), .A4(n_0_97), .ZN(result[5]) + ); + INV_X1_LVT i_10_26( + .A(n_10_21), .ZN(n_10_22) + ); + NOR2_X1_LVT i_10_28( + .A1(n_10_22), .A2(n_10_23), .ZN(n_10_24) + ); + XNOR2_X1_LVT i_10_29( + .A(n_10_19), .B(n_10_24), .ZN(n_36) + ); + AOI222_X1_LVT i_0_89( + .A1(n_4), .A2(n_0_581), .B1(n_36), .B2(n_0_580), .C1(n_0_668), .C2(n_0_564), + .ZN(n_0_84) + ); + INV_X1_LVT i_0_770( + .A(op1[4]), .ZN(n_0_737) + ); + AOI221_X1_LVT i_0_90( + .A(aluBypass), .B1(op2[4]), .B2(n_0_567), .C1(n_0_738), .C2(n_0_569), .ZN(n_0_85) + ); + OAI21_X1_LVT i_0_88( + .A(n_0_84), .B1(n_0_737), .B2(n_0_85), .ZN(n_0_83) + ); + NOR2_X1_LVT i_0_689( + .A1(op2[4]), .A2(n_0_737), .ZN(n_0_656) + ); + AOI21_X1_LVT i_0_95( + .A(n_0_616), .B1(n_0_727), .B2(n_0_723), .ZN(n_0_90) + ); + OAI22_X1_LVT i_0_94( + .A1(n_0_723), .A2(n_0_216), .B1(n_0_656), .B2(n_0_90), .ZN(n_0_89) + ); + INV_X1_LVT i_0_93( + .A(n_0_89), .ZN(n_0_88) + ); + OAI22_X1_LVT i_0_92( + .A1(op2[2]), .A2(n_0_88), .B1(n_0_693), .B2(n_0_157), .ZN(n_0_87) + ); + OAI221_X1_LVT i_0_91( + .A(n_0_105), .B1(n_0_728), .B2(n_0_122), .C1(op2[1]), .C2(n_0_87), .ZN(n_0_86) + ); + AOI221_X1_LVT i_0_85( + .A(n_0_83), .B1(n_0_561), .B2(n_0_86), .C1(op2[0]), .C2(n_0_99), .ZN(n_0_80) + ); + AOI221_X1_LVT i_0_87( + .A(n_0_574), .B1(n_0_729), .B2(op2[1]), .C1(n_0_728), .C2(n_0_724), .ZN(n_0_82) + ); + OAI22_X1_LVT i_0_86( + .A1(op2[0]), .A2(n_0_96), .B1(n_0_701), .B2(n_0_82), .ZN(n_0_81) + ); + OAI21_X1_LVT i_0_84( + .A(n_0_80), .B1(n_0_621), .B2(n_0_81), .ZN(result[4]) + ); + AND2_X1_LVT i_0_81( + .A1(op2[1]), .A2(n_0_105), .ZN(n_0_77) + ); + NAND2_X1_LVT i_0_80( + .A1(n_0_102), .A2(n_0_77), .ZN(n_0_76) + ); + OAI221_X1_LVT i_0_83( + .A(n_0_693), .B1(n_0_654), .B2(n_0_484), .C1(n_0_738), .C2(n_0_350), .ZN(n_0_79) + ); + OAI21_X1_LVT i_0_82( + .A(n_0_79), .B1(n_0_693), .B2(n_0_138), .ZN(n_0_78) + ); + OAI21_X1_LVT i_0_79( + .A(n_0_76), .B1(op2[1]), .B2(n_0_78), .ZN(n_0_75) + ); + NOR2_X1_LVT i_0_78( + .A1(n_0_562), .A2(n_0_75), .ZN(n_0_74) + ); + NAND2_X1_LVT i_10_20( + .A1(n_10_15), .A2(n_10_16), .ZN(n_10_17) + ); + XNOR2_X1_LVT i_10_21( + .A(n_10_13), .B(n_10_17), .ZN(n_35) + ); + AOI22_X1_LVT i_0_75( + .A1(n_35), .A2(n_0_580), .B1(n_3), .B2(n_0_581), .ZN(n_0_71) + ); + OAI21_X1_LVT i_0_74( + .A(n_0_681), .B1(n_0_723), .B2(n_0_566), .ZN(n_0_70) + ); + AOI222_X1_LVT i_0_73( + .A1(n_0_654), .A2(n_0_569), .B1(n_0_663), .B2(n_0_564), .C1(op1[3]), .C2(n_0_70), + .ZN(n_0_69) + ); + INV_X1_LVT i_0_736( + .A(op1[0]), .ZN(n_0_703) + ); + OAI22_X1_LVT i_0_77( + .A1(n_0_703), .A2(n_0_531), .B1(n_0_694), .B2(n_0_572), .ZN(n_0_73) + ); + OAI22_X1_LVT i_0_76( + .A1(n_0_701), .A2(n_0_73), .B1(op2[0]), .B2(n_0_82), .ZN(n_0_72) + ); + OAI211_X1_LVT i_0_72( + .A(n_0_71), .B(n_0_69), .C1(n_0_621), .C2(n_0_72), .ZN(n_0_68) + ); + AOI211_X1_LVT i_0_71( + .A(n_0_74), .B(n_0_68), .C1(n_0_547), .C2(n_0_86), .ZN(n_0_67) + ); + INV_X1_LVT i_0_70( + .A(n_0_67), .ZN(result[3]) + ); + NAND2_X1_LVT i_0_65( + .A1(n_2), .A2(n_0_581), .ZN(n_0_62) + ); + OAI221_X1_LVT i_0_66( + .A(op2[2]), .B1(op1[2]), .B2(n_0_564), .C1(n_0_694), .C2(n_0_567), .ZN(n_0_63) + ); + AOI21_X1_LVT i_0_64( + .A(aluBypass), .B1(n_0_693), .B2(n_0_569), .ZN(n_0_61) + ); + OAI21_X1_LVT i_0_63( + .A(n_0_63), .B1(n_0_694), .B2(n_0_61), .ZN(n_0_60) + ); + INV_X1_LVT i_10_13( + .A(n_10_10), .ZN(n_10_11) + ); + NOR2_X1_LVT i_10_14( + .A1(n_10_9), .A2(n_10_11), .ZN(n_10_12) + ); + XNOR2_X1_LVT i_10_15( + .A(n_10_7), .B(n_10_12), .ZN(n_34) + ); + AOI21_X1_LVT i_0_62( + .A(n_0_60), .B1(n_34), .B2(n_0_580), .ZN(n_0_59) + ); + OAI211_X1_LVT i_0_57( + .A(n_0_62), .B(n_0_59), .C1(n_0_548), .C2(n_0_75), .ZN(n_0_54) + ); + NOR2_X1_LVT i_0_698( + .A1(n_0_729), .A2(op2[1]), .ZN(n_0_665) + ); + INV_X1_LVT i_0_697( + .A(n_0_665), .ZN(n_0_664) + ); + OAI21_X1_LVT i_0_69( + .A(op2[0]), .B1(n_0_664), .B2(n_0_574), .ZN(n_0_66) + ); + OAI21_X1_LVT i_0_68( + .A(n_0_620), .B1(op2[0]), .B2(n_0_73), .ZN(n_0_65) + ); + INV_X1_LVT i_0_67( + .A(n_0_65), .ZN(n_0_64) + ); + OAI222_X1_LVT i_0_61( + .A1(op1[10]), .A2(n_0_617), .B1(op1[2]), .B2(n_0_615), .C1(n_0_738), .C2(n_0_332), + .ZN(n_0_58) + ); + OAI22_X1_LVT i_0_60( + .A1(op2[2]), .A2(n_0_58), .B1(n_0_693), .B2(n_0_124), .ZN(n_0_57) + ); + INV_X1_LVT i_0_59( + .A(n_0_57), .ZN(n_0_56) + ); + AOI22_X1_LVT i_0_58( + .A1(n_0_728), .A2(n_0_56), .B1(n_0_87), .B2(n_0_77), .ZN(n_0_55) + ); + AOI221_X1_LVT i_0_56( + .A(n_0_54), .B1(n_0_66), .B2(n_0_64), .C1(n_0_561), .C2(n_0_55), .ZN(n_0_53) + ); + INV_X1_LVT i_0_55( + .A(n_0_53), .ZN(result[2]) + ); + NAND2_X1_LVT i_0_54( + .A1(n_0_547), .A2(n_0_55), .ZN(n_0_52) + ); + AOI221_X1_LVT i_0_47( + .A(n_0_728), .B1(n_0_729), .B2(n_0_565), .C1(op1[1]), .C2(n_0_566), .ZN(n_0_45) + ); + NOR2_X1_LVT i_0_700( + .A1(op1[0]), .A2(n_0_701), .ZN(n_0_667) + ); + AOI211_X1_LVT i_0_48( + .A(n_0_667), .B(n_0_621), .C1(n_0_729), .C2(n_0_701), .ZN(n_0_46) + ); + AOI221_X1_LVT i_0_44( + .A(n_0_45), .B1(op1[1]), .B2(aluBypass), .C1(n_0_571), .C2(n_0_46), .ZN(n_0_42) + ); + NAND2_X1_LVT i_10_6( + .A1(n_10_3), .A2(n_10_4), .ZN(n_10_5) + ); + XNOR2_X1_LVT i_10_7( + .A(n_10_5), .B(n_10_1), .ZN(n_33) + ); + AOI22_X1_LVT i_0_49( + .A1(n_33), .A2(n_0_580), .B1(n_1), .B2(n_0_581), .ZN(n_0_47) + ); + OAI21_X1_LVT i_0_46( + .A(n_0_47), .B1(n_0_664), .B2(n_0_568), .ZN(n_0_44) + ); + NAND2_X1_LVT i_0_51( + .A1(op2[1]), .A2(n_0_78), .ZN(n_0_49) + ); + OAI222_X1_LVT i_0_53( + .A1(n_0_722), .A2(n_0_617), .B1(n_0_729), .B2(n_0_615), .C1(n_0_738), .C2(n_0_313), + .ZN(n_0_51) + ); + OAI22_X1_LVT i_0_52( + .A1(n_0_223), .A2(n_0_103), .B1(op2[2]), .B2(n_0_51), .ZN(n_0_50) + ); + OAI21_X1_LVT i_0_50( + .A(n_0_49), .B1(op2[1]), .B2(n_0_50), .ZN(n_0_48) + ); + AOI21_X1_LVT i_0_45( + .A(n_0_44), .B1(n_0_561), .B2(n_0_48), .ZN(n_0_43) + ); + NAND3_X1_LVT i_0_43( + .A1(n_0_52), .A2(n_0_42), .A3(n_0_43), .ZN(result[1]) + ); + OAI222_X1_LVT i_0_11( + .A1(n_0_740), .A2(n_0_617), .B1(n_0_703), .B2(n_0_615), .C1(n_0_738), .C2(n_0_290), + .ZN(n_0_10) + ); + OAI22_X1_LVT i_0_10( + .A1(op2[2]), .A2(n_0_10), .B1(n_0_693), .B2(n_0_88), .ZN(n_0_9) + ); + OAI221_X1_LVT i_0_9( + .A(n_0_701), .B1(n_0_728), .B2(n_0_56), .C1(op2[1]), .C2(n_0_9), .ZN(n_0_8) + ); + OAI21_X1_LVT i_0_8( + .A(n_0_8), .B1(n_0_701), .B2(n_0_48), .ZN(n_0_7) + ); + NOR2_X1_LVT i_0_7( + .A1(n_0_579), .A2(n_0_7), .ZN(n_0_6) + ); + OAI221_X1_LVT i_0_3( + .A(op2[0]), .B1(op1[0]), .B2(n_0_564), .C1(n_0_703), .C2(n_0_567), .ZN(n_0_2) + ); + OAI21_X1_LVT i_10_2( + .A(n_10_1), .B1(n_10_0), .B2(op2[0]), .ZN(n_32) + ); + AOI22_X1_LVT i_0_2( + .A1(n_32), .A2(n_0_580), .B1(n_0), .B2(n_0_581), .ZN(n_0_1) + ); + NAND3_X1_LVT i_0_6( + .A1(n_0_701), .A2(n_0_571), .A3(n_0_620), .ZN(n_0_5) + ); + OAI211_X1_LVT i_0_5( + .A(n_0_681), .B(n_0_5), .C1(op2[0]), .C2(n_0_568), .ZN(n_0_4) + ); + NAND2_X1_LVT i_0_4( + .A1(op1[0]), .A2(n_0_4), .ZN(n_0_3) + ); + NAND3_X1_LVT i_0_1( + .A1(n_0_2), .A2(n_0_1), .A3(n_0_3), .ZN(n_0_0) + ); + OAI33_X1_LVT i_0_14( + .A1(n_0_692), .A2(op1[31]), .A3(n_0_683), .B1(op2[31]), .B2(n_0_691), .B3(aluOp[0]), + .ZN(n_0_13) + ); + INV_X1_LVT i_0_741( + .A(op2[29]), .ZN(n_0_708) + ); + NAND2_X1_LVT i_0_685( + .A1(op1[29]), .A2(n_0_708), .ZN(n_0_652) + ); + OAI22_X1_LVT i_0_713( + .A1(n_0_700), .A2(op1[28]), .B1(op1[29]), .B2(n_0_708), .ZN(n_0_680) + ); + NAND2_X1_LVT i_0_694( + .A1(n_0_688), .A2(op2[27]), .ZN(n_0_661) + ); + INV_X1_LVT i_0_742( + .A(op2[26]), .ZN(n_0_709) + ); + OAI22_X1_LVT i_0_712( + .A1(n_0_699), .A2(op2[25]), .B1(n_0_736), .B2(op2[24]), .ZN(n_0_679) + ); + NAND2_X1_LVT i_0_690( + .A1(n_0_727), .A2(op2[20]), .ZN(n_0_657) + ); + INV_X1_LVT i_0_740( + .A(op2[18]), .ZN(n_0_707) + ); + OAI22_X1_LVT i_0_711( + .A1(n_0_707), .A2(op1[18]), .B1(n_0_690), .B2(op1[19]), .ZN(n_0_678) + ); + OAI22_X1_LVT i_0_29( + .A1(n_0_739), .A2(op2[16]), .B1(n_0_734), .B2(op2[15]), .ZN(n_0_28) + ); + INV_X1_LVT i_0_728( + .A(op2[12]), .ZN(n_0_695) + ); + INV_X1_LVT i_0_748( + .A(op2[13]), .ZN(n_0_715) + ); + OAI22_X1_LVT i_0_704( + .A1(n_0_706), .A2(op2[11]), .B1(n_0_696), .B2(op2[12]), .ZN(n_0_671) + ); + AOI22_X1_LVT i_0_710( + .A1(n_0_740), .A2(op2[8]), .B1(n_0_713), .B2(op2[7]), .ZN(n_0_677) + ); + OAI22_X1_LVT i_0_707( + .A1(n_0_731), .A2(op1[5]), .B1(op1[6]), .B2(n_0_702), .ZN(n_0_674) + ); + OAI22_X1_LVT i_0_706( + .A1(op1[2]), .A2(n_0_693), .B1(op1[1]), .B2(n_0_728), .ZN(n_0_673) + ); + INV_X1_LVT i_0_705( + .A(n_0_673), .ZN(n_0_672) + ); + INV_X1_LVT i_0_699( + .A(n_0_667), .ZN(n_0_666) + ); + OAI21_X1_LVT i_0_42( + .A(n_0_672), .B1(n_0_666), .B2(n_0_665), .ZN(n_0_41) + ); + AOI21_X1_LVT i_0_41( + .A(n_0_654), .B1(op1[2]), .B2(n_0_693), .ZN(n_0_40) + ); + AOI211_X1_LVT i_0_40( + .A(n_0_668), .B(n_0_663), .C1(n_0_41), .C2(n_0_40), .ZN(n_0_39) + ); + AOI211_X1_LVT i_0_39( + .A(n_0_656), .B(n_0_39), .C1(n_0_731), .C2(op1[5]), .ZN(n_0_38) + ); + OAI222_X1_LVT i_0_38( + .A1(n_0_704), .A2(op2[6]), .B1(n_0_674), .B2(n_0_38), .C1(n_0_713), .C2(op2[7]), + .ZN(n_0_37) + ); + AOI221_X1_LVT i_0_37( + .A(n_0_655), .B1(op1[9]), .B2(n_0_720), .C1(n_0_677), .C2(n_0_37), .ZN(n_0_36) + ); + INV_X1_LVT i_0_768( + .A(op2[10]), .ZN(n_0_735) + ); + OAI22_X1_LVT i_0_36( + .A1(n_0_735), .A2(op1[10]), .B1(op1[9]), .B2(n_0_720), .ZN(n_0_35) + ); + OAI22_X1_LVT i_0_35( + .A1(op2[10]), .A2(n_0_733), .B1(n_0_36), .B2(n_0_35), .ZN(n_0_34) + ); + INV_X1_LVT i_0_34( + .A(n_0_34), .ZN(n_0_33) + ); + AOI21_X1_LVT i_0_33( + .A(n_0_33), .B1(n_0_706), .B2(op2[11]), .ZN(n_0_32) + ); + OAI222_X1_LVT i_0_32( + .A1(op1[12]), .A2(n_0_695), .B1(n_0_715), .B2(op1[13]), .C1(n_0_671), .C2(n_0_32), + .ZN(n_0_31) + ); + OAI221_X1_LVT i_0_31( + .A(n_0_31), .B1(n_0_721), .B2(op2[14]), .C1(op2[13]), .C2(n_0_714), .ZN(n_0_30) + ); + AOI22_X1_LVT i_0_30( + .A1(n_0_734), .A2(op2[15]), .B1(n_0_721), .B2(op2[14]), .ZN(n_0_29) + ); + AOI21_X1_LVT i_0_28( + .A(n_0_28), .B1(n_0_30), .B2(n_0_29), .ZN(n_0_27) + ); + AOI221_X1_LVT i_0_27( + .A(n_0_27), .B1(n_0_732), .B2(op2[17]), .C1(n_0_739), .C2(op2[16]), .ZN(n_0_26) + ); + AOI211_X1_LVT i_0_26( + .A(n_0_660), .B(n_0_26), .C1(n_0_707), .C2(op1[18]), .ZN(n_0_25) + ); + OAI22_X1_LVT i_0_25( + .A1(op2[19]), .A2(n_0_689), .B1(n_0_678), .B2(n_0_25), .ZN(n_0_24) + ); + AOI211_X1_LVT i_0_24( + .A(n_0_658), .B(n_0_659), .C1(n_0_657), .C2(n_0_24), .ZN(n_0_23) + ); + AOI221_X1_LVT i_0_23( + .A(n_0_23), .B1(n_0_726), .B2(op2[21]), .C1(n_0_687), .C2(op2[22]), .ZN(n_0_22) + ); + AOI221_X1_LVT i_0_22( + .A(n_0_22), .B1(op1[22]), .B2(n_0_686), .C1(op1[23]), .C2(n_0_718), .ZN(n_0_21) + ); + AOI221_X1_LVT i_0_21( + .A(n_0_21), .B1(n_0_736), .B2(op2[24]), .C1(n_0_719), .C2(op2[23]), .ZN(n_0_20) + ); + OAI222_X1_LVT i_0_20( + .A1(op1[26]), .A2(n_0_709), .B1(op1[25]), .B2(n_0_697), .C1(n_0_679), .C2(n_0_20), + .ZN(n_0_19) + ); + OAI221_X1_LVT i_0_19( + .A(n_0_19), .B1(n_0_711), .B2(op2[26]), .C1(n_0_688), .C2(op2[27]), .ZN(n_0_18) + ); + AOI22_X1_LVT i_0_18( + .A1(n_0_700), .A2(op1[28]), .B1(n_0_661), .B2(n_0_18), .ZN(n_0_17) + ); + OAI21_X1_LVT i_0_17( + .A(n_0_652), .B1(n_0_680), .B2(n_0_17), .ZN(n_0_16) + ); + INV_X1_LVT i_0_749( + .A(op2[30]), .ZN(n_0_716) + ); + OAI21_X1_LVT i_0_16( + .A(n_0_16), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_15) + ); + OAI22_X1_LVT i_0_708( + .A1(n_0_692), .A2(op1[31]), .B1(op2[31]), .B2(n_0_691), .ZN(n_0_675) + ); + AOI21_X1_LVT i_0_15( + .A(n_0_675), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_14) + ); + AOI21_X1_LVT i_0_13( + .A(n_0_13), .B1(n_0_15), .B2(n_0_14), .ZN(n_0_12) + ); + NOR4_X1_LVT i_0_12( + .A1(n_0_685), .A2(aluOp[2]), .A3(aluBypass), .A4(n_0_12), .ZN(n_0_11) + ); + OR3_X1_LVT i_0_0( + .A1(n_0_6), .A2(n_0_0), .A3(n_0_11), .ZN(result[0]) + ); + OR4_X1_LVT i_0_703( + .A1(n_0_680), .A2(n_0_673), .A3(n_0_675), .A4(n_0_678), .ZN(n_0_670) + ); + INV_X1_LVT i_0_709( + .A(n_0_677), .ZN(n_0_676) + ); + OR4_X1_LVT i_0_702( + .A1(n_0_679), .A2(n_0_674), .A3(n_0_676), .A4(n_0_671), .ZN(n_0_669) + ); + AOI22_X1_LVT i_0_663( + .A1(n_0_688), .A2(op2[27]), .B1(op1[22]), .B2(n_0_686), .ZN(n_0_630) + ); + OAI22_X1_LVT i_0_662( + .A1(n_0_694), .A2(op2[2]), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_629) + ); + AOI221_X1_LVT i_0_661( + .A(n_0_629), .B1(n_0_711), .B2(op2[26]), .C1(n_0_721), .C2(op2[14]), .ZN(n_0_628) + ); + AOI21_X1_LVT i_0_664( + .A(n_0_660), .B1(n_0_690), .B2(op1[19]), .ZN(n_0_631) + ); + OAI222_X1_LVT i_0_660( + .A1(op1[12]), .A2(n_0_695), .B1(n_0_688), .B2(op2[27]), .C1(op1[22]), .C2(n_0_686), + .ZN(n_0_627) + ); + AOI21_X1_LVT i_0_659( + .A(n_0_663), .B1(n_0_734), .B2(op2[15]), .ZN(n_0_626) + ); + OAI211_X1_LVT i_0_658( + .A(n_0_666), .B(n_0_626), .C1(n_0_715), .C2(op1[13]), .ZN(n_0_625) + ); + AOI211_X1_LVT i_0_657( + .A(n_0_627), .B(n_0_625), .C1(op1[23]), .C2(n_0_718), .ZN(n_0_624) + ); + NAND4_X1_LVT i_0_656( + .A1(n_0_630), .A2(n_0_628), .A3(n_0_631), .A4(n_0_624), .ZN(n_0_623) + ); + OAI22_X1_LVT i_0_684( + .A1(n_0_721), .A2(op2[14]), .B1(n_0_722), .B2(op2[9]), .ZN(n_0_651) + ); + AOI211_X1_LVT i_0_668( + .A(n_0_651), .B(n_0_654), .C1(n_0_719), .C2(op2[23]), .ZN(n_0_635) + ); + NAND2_X1_LVT i_0_667( + .A1(n_0_664), .A2(n_0_657), .ZN(n_0_634) + ); + NOR3_X1_LVT i_0_666( + .A1(n_0_659), .A2(n_0_656), .A3(n_0_634), .ZN(n_0_633) + ); + AOI21_X1_LVT i_0_671( + .A(n_0_655), .B1(n_0_739), .B2(op2[16]), .ZN(n_0_638) + ); + AOI21_X1_LVT i_0_670( + .A(n_0_668), .B1(n_0_736), .B2(op2[24]), .ZN(n_0_637) + ); + OAI22_X1_LVT i_0_673( + .A1(n_0_735), .A2(op1[10]), .B1(n_0_734), .B2(op2[15]), .ZN(n_0_640) + ); + AOI221_X1_LVT i_0_672( + .A(n_0_640), .B1(n_0_732), .B2(op2[17]), .C1(n_0_731), .C2(op1[5]), .ZN(n_0_639) + ); + AND3_X1_LVT i_0_669( + .A1(n_0_638), .A2(n_0_637), .A3(n_0_639), .ZN(n_0_636) + ); + OAI22_X1_LVT i_0_682( + .A1(n_0_703), .A2(op2[0]), .B1(n_0_704), .B2(op2[6]), .ZN(n_0_649) + ); + OAI22_X1_LVT i_0_681( + .A1(op2[28]), .A2(n_0_698), .B1(op1[25]), .B2(n_0_697), .ZN(n_0_648) + ); + AOI21_X1_LVT i_0_678( + .A(n_0_658), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_645) + ); + AOI21_X1_LVT i_0_677( + .A(n_0_662), .B1(n_0_735), .B2(op1[10]), .ZN(n_0_644) + ); + INV_X1_LVT i_0_758( + .A(op2[21]), .ZN(n_0_725) + ); + OAI22_X1_LVT i_0_683( + .A1(op1[21]), .A2(n_0_725), .B1(n_0_739), .B2(op2[16]), .ZN(n_0_650) + ); + AOI221_X1_LVT i_0_676( + .A(n_0_650), .B1(n_0_722), .B2(op2[9]), .C1(op1[7]), .C2(n_0_712), .ZN(n_0_643) + ); + OAI21_X1_LVT i_0_680( + .A(n_0_652), .B1(n_0_711), .B2(op2[26]), .ZN(n_0_647) + ); + AOI221_X1_LVT i_0_679( + .A(n_0_647), .B1(n_0_706), .B2(op2[11]), .C1(n_0_707), .C2(op1[18]), .ZN(n_0_646) + ); + NAND4_X1_LVT i_0_675( + .A1(n_0_645), .A2(n_0_644), .A3(n_0_643), .A4(n_0_646), .ZN(n_0_642) + ); + NOR3_X1_LVT i_0_674( + .A1(n_0_649), .A2(n_0_648), .A3(n_0_642), .ZN(n_0_641) + ); + NAND4_X1_LVT i_0_665( + .A1(n_0_635), .A2(n_0_633), .A3(n_0_636), .A4(n_0_641), .ZN(n_0_632) + ); + NOR4_X1_LVT i_0_655( + .A1(n_0_670), .A2(n_0_669), .A3(n_0_623), .A4(n_0_632), .ZN(eqFlag) + ); +endmodule + +module decoder(CurrentPC, JumpOrBranchPC, JumpOrBranch, DAddr, WData, RData, Instruction, + WrMem, DWidth, Rs1, Rs2, Rd, RRs1, RRs2, WRd, WrReg, Illegal); + input [31:0] CurrentPC, RData, Instruction, RRs1, RRs2; + output [31:0] JumpOrBranchPC, DAddr, WData, WRd; + output [4:0] Rs1, Rs2, Rd; + output [1:0] DWidth; + output JumpOrBranch, WrMem, WrReg, Illegal; + + wire [31:0] op1, op2; + wire [2:0] aluOp; + wire eqFlag, n_5_0, n_5_1, n_5_2, n_5_3, n_5_4, n_5_5, n_5_6, n_5_7, n_5_8, + n_5_9, n_5_10, n_5_11, n_5_12, n_5_13, n_5_14, n_5_15, n_5_16, n_5_17, + n_5_18, n_5_19, n_5_20, n_5_21, n_5_22, n_5_23, n_5_24, n_5_25, n_5_26, + n_5_27, n_5_28, n_5_29, n_5_30, n_5_31, n_5_32, n_5_33, n_17_0, n_17_1, + n_17_2, n_17_3, n_17_4, n_17_5, n_17_6, n_17_7, n_17_8, n_17_9, n_17_10, + n_17_11, n_17_12, n_17_13, n_17_14, n_17_15, n_17_16, n_17_17, n_17_18, + n_17_19, n_17_20, n_17_21, n_17_22, n_17_23, n_17_24, n_17_25, n_17_26, + n_17_27, n_17_28, n_17_29, n_17_30, n_17_31, n_17_32, n_18_0, n_18_1, + n_18_2, n_18_3, n_18_4, n_18_5, n_18_6, n_18_7, n_18_8, n_18_9, n_18_10, + n_18_11, n_18_12, n_18_13, n_18_14, n_18_15, n_18_16, n_18_17, n_18_18, + n_18_19, n_18_20, n_18_21, n_18_22, n_18_23, n_18_24, n_18_25, n_18_26, + n_18_27, n_18_28, n_18_29, n_18_30, n_18_31, n_18_32, n_0_15, n_0_2, + n_0_16, n_0_3, n_0_17, n_0_4, n_0_18, n_0_5, n_0_19, n_0_6, n_0_20, + n_0_7, n_0_21, n_0_8, n_0_22, n_0_9, n_0_23, n_0_10, n_0_24, n_0_11, + n_0_25, n_0_12, n_0_26, n_0_13, n_0_27, n_0_14, n_0_28, n_0_29, n_0_30, + n_0_31, n_0_32, n_0_33, n_0_34, n_0_35, n_0_36, n_0_37, n_0_38, n_0_39, + n_0_40, n_0_41, n_0_42, n_0_43, n_0_44, n_0_45, n_0_46, n_0_47, n_0_48, + n_0_49, n_0_50, n_0_51, n_0_52, n_0_53, n_0_54, n_0_55, n_0_56, n_0_57, + n_0_58, n_0_59, n_0_60, n_0_61, n_0_62, n_0_63, n_0_64, n_0_65, n_0_66, + n_0_67, n_0_68, n_0_69, n_0_70, n_0_71, n_0_72, n_0_73, n_0_74, n_0_75, + n_0_76, n_0_77, n_0_78, n_0_79, n_0_80, n_0_81, n_0_82, n_0_83, n_0_84, + n_0_85, n_0_86, n_0_87, n_0_88, n_0_89, n_0_90, n_0_91, n_0_92, n_0_93, + n_0_94, n_0_95, n_0_96, n_0_97, n_0_98, n_0_99, n_0_100, aluNegAr, + n_0_101, n_0_102, n_0_103, n_0_104, n_0_105, aluBypass, n_0_106, + n_0_107, n_0_108, n_0_109, n_0_110, n_0_111, n_0_112, n_0_113, n_0_114, + n_0_115, n_0_116, n_0_117, n_0_118, n_0_119, n_0_120, n_0_121, n_0_122, + n_0_123, n_0_124, n_0_125, n_0_126, n_0_127, n_0_128, n_0_129, n_0_130, + n_0_131, n_0_132, n_0_133, n_0_134, n_0_135, n_0_136, n_0_137, n_0_138, + n_0_139, n_0_140, n_0_141, n_0_142, n_0_143, n_0_144, n_0_145, n_0_146, + n_0_147, n_0_148, n_0_149, n_0_150, n_0_151, n_0_152, n_0_153, n_0_154, + n_0_155, n_0_156, n_0_157, n_0_158, n_0_159, n_0_160, n_0_161, n_0_162, + n_0_163, n_0_164, n_0_165, n_0_166, n_0_167, n_0_168, n_0_169, n_0_170, + n_0_171, n_0_172, n_0_173, n_0_174, n_0_175, n_0_176, n_0_177, n_0_178, + n_0_179, n_0_180, n_0_181, n_0_182, n_0_183, n_0_184, n_0_185, n_0_186, + n_0_187, n_0_188, n_0_189, n_0_190, n_0_191, n_0_192, n_0_193, n_0_194, + n_0_195, n_0_196, n_0_197, n_0_198, n_0_199, n_0_200, n_0_201, n_0_202, + n_0_203, n_0_204, n_0_205, n_0_206, n_0_207, n_0_208, n_0_209, n_0_210, + n_0_211, n_0_212, n_0_213, n_0_214, n_0_215, n_0_216, n_0_217, n_0_218, + n_0_219, n_0_220, n_0_221, n_0_222, n_0_223, n_0_224, n_0_225, n_0_226, + n_0_227, n_0_228, n_0_229, n_0_230, n_0_231, n_0_232, n_0_233, n_0_234, + n_0_235, n_0_236, n_0_237, n_0_238, n_0_239, n_0_240, n_0_241, n_0_242, + n_0_1, n_0_0, n_0_243, n_0_244, n_0_245, n_0_246, n_0_247, n_0_248, + n_0_249, n_63, n_64, n_65, n_66, n_67, n_68, n_69, n_70, n_71, n_72, + n_73, n_74, n_75, n_76, n_77, n_78, n_79, n_80, n_81, n_82, n_83, n_84, + n_85, n_86, n_87, n_88, n_89, n_90, n_91, n_92, n_93, n_32, n_33, n_34, + n_35, n_36, n_37, n_38, n_39, n_40, n_41, n_42, n_43, n_44, n_45, n_46, + n_47, n_48, n_49, n_50, n_51, n_52, n_53, n_54, n_55, n_56, n_57, n_58, + n_59, n_60, n_61, n_62, n_0, n_1, n_2, n_3, n_4, n_5, n_6, n_7, n_8, + n_9, n_10, n_11, n_12, n_13, n_14, n_15, n_16, n_17, n_18, n_19, n_20, + n_21, n_22, n_23, n_24, n_25, n_26, n_27, n_28, n_29, n_30, n_31; + + INV_X1_LVT i_18_1( + .A(CurrentPC[13]), .ZN(n_18_1) + ); + XNOR2_X1_LVT i_18_32( + .A(CurrentPC[31]), .B(n_18_1), .ZN(n_18_32) + ); + INV_X1_LVT i_18_0( + .A(Instruction[31]), .ZN(n_18_0) + ); + HA_X1_LVT i_18_2( + .A(Instruction[8]), .B(CurrentPC[1]), .CO(n_18_2), .S(n_63) + ); + FA_X1_LVT i_18_3( + .A(Instruction[9]), .B(CurrentPC[2]), .CI(n_18_2), .CO(n_18_3), .S(n_64) + ); + FA_X1_LVT i_18_4( + .A(Instruction[10]), .B(CurrentPC[3]), .CI(n_18_3), .CO(n_18_4), .S(n_65) + ); + FA_X1_LVT i_18_5( + .A(Instruction[11]), .B(CurrentPC[4]), .CI(n_18_4), .CO(n_18_5), .S(n_66) + ); + FA_X1_LVT i_18_6( + .A(Instruction[25]), .B(CurrentPC[5]), .CI(n_18_5), .CO(n_18_6), .S(n_67) + ); + FA_X1_LVT i_18_7( + .A(Instruction[26]), .B(CurrentPC[6]), .CI(n_18_6), .CO(n_18_7), .S(n_68) + ); + FA_X1_LVT i_18_8( + .A(Instruction[27]), .B(CurrentPC[7]), .CI(n_18_7), .CO(n_18_8), .S(n_69) + ); + FA_X1_LVT i_18_9( + .A(Instruction[28]), .B(CurrentPC[8]), .CI(n_18_8), .CO(n_18_9), .S(n_70) + ); + FA_X1_LVT i_18_10( + .A(Instruction[29]), .B(CurrentPC[9]), .CI(n_18_9), .CO(n_18_10), .S(n_71) + ); + FA_X1_LVT i_18_11( + .A(Instruction[30]), .B(CurrentPC[10]), .CI(n_18_10), .CO(n_18_11), .S(n_72) + ); + FA_X1_LVT i_18_12( + .A(Instruction[7]), .B(CurrentPC[11]), .CI(n_18_11), .CO(n_18_12), .S(n_73) + ); + FA_X1_LVT i_18_13( + .A(CurrentPC[12]), .B(Instruction[31]), .CI(n_18_12), .CO(n_18_13), .S(n_74) + ); + FA_X1_LVT i_18_14( + .A(n_18_0), .B(n_18_1), .CI(n_18_13), .CO(n_18_14), .S(n_75) + ); + FA_X1_LVT i_18_15( + .A(CurrentPC[14]), .B(n_18_1), .CI(n_18_14), .CO(n_18_15), .S(n_76) + ); + FA_X1_LVT i_18_16( + .A(CurrentPC[15]), .B(n_18_1), .CI(n_18_15), .CO(n_18_16), .S(n_77) + ); + FA_X1_LVT i_18_17( + .A(CurrentPC[16]), .B(n_18_1), .CI(n_18_16), .CO(n_18_17), .S(n_78) + ); + FA_X1_LVT i_18_18( + .A(CurrentPC[17]), .B(n_18_1), .CI(n_18_17), .CO(n_18_18), .S(n_79) + ); + FA_X1_LVT i_18_19( + .A(CurrentPC[18]), .B(n_18_1), .CI(n_18_18), .CO(n_18_19), .S(n_80) + ); + FA_X1_LVT i_18_20( + .A(CurrentPC[19]), .B(n_18_1), .CI(n_18_19), .CO(n_18_20), .S(n_81) + ); + FA_X1_LVT i_18_21( + .A(CurrentPC[20]), .B(n_18_1), .CI(n_18_20), .CO(n_18_21), .S(n_82) + ); + FA_X1_LVT i_18_22( + .A(CurrentPC[21]), .B(n_18_1), .CI(n_18_21), .CO(n_18_22), .S(n_83) + ); + FA_X1_LVT i_18_23( + .A(CurrentPC[22]), .B(n_18_1), .CI(n_18_22), .CO(n_18_23), .S(n_84) + ); + FA_X1_LVT i_18_24( + .A(CurrentPC[23]), .B(n_18_1), .CI(n_18_23), .CO(n_18_24), .S(n_85) + ); + FA_X1_LVT i_18_25( + .A(CurrentPC[24]), .B(n_18_1), .CI(n_18_24), .CO(n_18_25), .S(n_86) + ); + FA_X1_LVT i_18_26( + .A(CurrentPC[25]), .B(n_18_1), .CI(n_18_25), .CO(n_18_26), .S(n_87) + ); + FA_X1_LVT i_18_27( + .A(CurrentPC[26]), .B(n_18_1), .CI(n_18_26), .CO(n_18_27), .S(n_88) + ); + FA_X1_LVT i_18_28( + .A(CurrentPC[27]), .B(n_18_1), .CI(n_18_27), .CO(n_18_28), .S(n_89) + ); + FA_X1_LVT i_18_29( + .A(CurrentPC[28]), .B(n_18_1), .CI(n_18_28), .CO(n_18_29), .S(n_90) + ); + FA_X1_LVT i_18_30( + .A(CurrentPC[29]), .B(n_18_1), .CI(n_18_29), .CO(n_18_30), .S(n_91) + ); + FA_X1_LVT i_18_31( + .A(CurrentPC[30]), .B(n_18_1), .CI(n_18_30), .CO(n_18_31), .S(n_92) + ); + XNOR2_X1_LVT i_18_33( + .A(n_18_32), .B(n_18_31), .ZN(n_93) + ); + INV_X1_LVT i_0_350( + .A(Instruction[3]), .ZN(n_0_243) + ); + NAND3_X1_LVT i_0_343( + .A1(n_0_243), .A2(Instruction[0]), .A3(Instruction[1]), .ZN(n_0_238) + ); + OR2_X1_LVT i_0_332( + .A1(n_0_238), .A2(Instruction[2]), .ZN(n_0_228) + ); + INV_X1_LVT i_0_351( + .A(Instruction[5]), .ZN(n_0_244) + ); + NOR2_X1_LVT i_0_340( + .A1(n_0_244), .A2(Instruction[4]), .ZN(n_0_235) + ); + NAND2_X1_LVT i_0_329( + .A1(Instruction[6]), .A2(n_0_235), .ZN(n_0_225) + ); + INV_X1_LVT i_0_354( + .A(Instruction[13]), .ZN(n_0_247) + ); + NOR2_X1_LVT i_0_345( + .A1(n_0_247), .A2(Instruction[14]), .ZN(n_0_240) + ); + NOR3_X1_LVT i_0_118( + .A1(n_0_228), .A2(n_0_225), .A3(n_0_240), .ZN(n_0_99) + ); + NAND3_X1_LVT i_0_346( + .A1(Instruction[0]), .A2(Instruction[1]), .A3(Instruction[2]), .ZN(n_0_241) + ); + NOR2_X1_LVT i_0_328( + .A1(n_0_241), .A2(n_0_225), .ZN(n_0_224) + ); + INV_X1_LVT i_0_356( + .A(n_0_224), .ZN(n_0_249) + ); + NOR2_X1_LVT i_0_108( + .A1(n_0_243), .A2(n_0_249), .ZN(n_0_91) + ); + INV_X1_LVT i_17_1( + .A(CurrentPC[21]), .ZN(n_17_1) + ); + XNOR2_X1_LVT i_17_32( + .A(CurrentPC[31]), .B(n_17_1), .ZN(n_17_32) + ); + INV_X1_LVT i_17_0( + .A(Instruction[31]), .ZN(n_17_0) + ); + HA_X1_LVT i_17_2( + .A(Instruction[21]), .B(CurrentPC[1]), .CO(n_17_2), .S(n_32) + ); + FA_X1_LVT i_17_3( + .A(Instruction[22]), .B(CurrentPC[2]), .CI(n_17_2), .CO(n_17_3), .S(n_33) + ); + FA_X1_LVT i_17_4( + .A(Instruction[23]), .B(CurrentPC[3]), .CI(n_17_3), .CO(n_17_4), .S(n_34) + ); + FA_X1_LVT i_17_5( + .A(Instruction[24]), .B(CurrentPC[4]), .CI(n_17_4), .CO(n_17_5), .S(n_35) + ); + FA_X1_LVT i_17_6( + .A(Instruction[25]), .B(CurrentPC[5]), .CI(n_17_5), .CO(n_17_6), .S(n_36) + ); + FA_X1_LVT i_17_7( + .A(Instruction[26]), .B(CurrentPC[6]), .CI(n_17_6), .CO(n_17_7), .S(n_37) + ); + FA_X1_LVT i_17_8( + .A(Instruction[27]), .B(CurrentPC[7]), .CI(n_17_7), .CO(n_17_8), .S(n_38) + ); + FA_X1_LVT i_17_9( + .A(Instruction[28]), .B(CurrentPC[8]), .CI(n_17_8), .CO(n_17_9), .S(n_39) + ); + FA_X1_LVT i_17_10( + .A(Instruction[29]), .B(CurrentPC[9]), .CI(n_17_9), .CO(n_17_10), .S(n_40) + ); + FA_X1_LVT i_17_11( + .A(Instruction[30]), .B(CurrentPC[10]), .CI(n_17_10), .CO(n_17_11), .S(n_41) + ); + FA_X1_LVT i_17_12( + .A(Instruction[20]), .B(CurrentPC[11]), .CI(n_17_11), .CO(n_17_12), .S(n_42) + ); + FA_X1_LVT i_17_13( + .A(Instruction[12]), .B(CurrentPC[12]), .CI(n_17_12), .CO(n_17_13), .S(n_43) + ); + FA_X1_LVT i_17_14( + .A(Instruction[13]), .B(CurrentPC[13]), .CI(n_17_13), .CO(n_17_14), .S(n_44) + ); + FA_X1_LVT i_17_15( + .A(Instruction[14]), .B(CurrentPC[14]), .CI(n_17_14), .CO(n_17_15), .S(n_45) + ); + FA_X1_LVT i_17_16( + .A(Instruction[15]), .B(CurrentPC[15]), .CI(n_17_15), .CO(n_17_16), .S(n_46) + ); + FA_X1_LVT i_17_17( + .A(Instruction[16]), .B(CurrentPC[16]), .CI(n_17_16), .CO(n_17_17), .S(n_47) + ); + FA_X1_LVT i_17_18( + .A(Instruction[17]), .B(CurrentPC[17]), .CI(n_17_17), .CO(n_17_18), .S(n_48) + ); + FA_X1_LVT i_17_19( + .A(Instruction[18]), .B(CurrentPC[18]), .CI(n_17_18), .CO(n_17_19), .S(n_49) + ); + FA_X1_LVT i_17_20( + .A(Instruction[19]), .B(CurrentPC[19]), .CI(n_17_19), .CO(n_17_20), .S(n_50) + ); + FA_X1_LVT i_17_21( + .A(CurrentPC[20]), .B(Instruction[31]), .CI(n_17_20), .CO(n_17_21), .S(n_51) + ); + FA_X1_LVT i_17_22( + .A(n_17_0), .B(n_17_1), .CI(n_17_21), .CO(n_17_22), .S(n_52) + ); + FA_X1_LVT i_17_23( + .A(CurrentPC[22]), .B(n_17_1), .CI(n_17_22), .CO(n_17_23), .S(n_53) + ); + FA_X1_LVT i_17_24( + .A(CurrentPC[23]), .B(n_17_1), .CI(n_17_23), .CO(n_17_24), .S(n_54) + ); + FA_X1_LVT i_17_25( + .A(CurrentPC[24]), .B(n_17_1), .CI(n_17_24), .CO(n_17_25), .S(n_55) + ); + FA_X1_LVT i_17_26( + .A(CurrentPC[25]), .B(n_17_1), .CI(n_17_25), .CO(n_17_26), .S(n_56) + ); + FA_X1_LVT i_17_27( + .A(CurrentPC[26]), .B(n_17_1), .CI(n_17_26), .CO(n_17_27), .S(n_57) + ); + FA_X1_LVT i_17_28( + .A(CurrentPC[27]), .B(n_17_1), .CI(n_17_27), .CO(n_17_28), .S(n_58) + ); + FA_X1_LVT i_17_29( + .A(CurrentPC[28]), .B(n_17_1), .CI(n_17_28), .CO(n_17_29), .S(n_59) + ); + FA_X1_LVT i_17_30( + .A(CurrentPC[29]), .B(n_17_1), .CI(n_17_29), .CO(n_17_30), .S(n_60) + ); + FA_X1_LVT i_17_31( + .A(CurrentPC[30]), .B(n_17_1), .CI(n_17_30), .CO(n_17_31), .S(n_61) + ); + XNOR2_X1_LVT i_17_33( + .A(n_17_32), .B(n_17_31), .ZN(n_62) + ); + INV_X1_LVT i_5_1( + .A(RRs1[12]), .ZN(n_5_1) + ); + XNOR2_X1_LVT i_5_33( + .A(RRs1[31]), .B(n_5_1), .ZN(n_5_33) + ); + INV_X1_LVT i_5_0( + .A(Instruction[31]), .ZN(n_5_0) + ); + HA_X1_LVT i_5_2( + .A(Instruction[20]), .B(RRs1[0]), .CO(n_5_2), .S(n_0) + ); + FA_X1_LVT i_5_3( + .A(Instruction[21]), .B(RRs1[1]), .CI(n_5_2), .CO(n_5_3), .S(n_1) + ); + FA_X1_LVT i_5_4( + .A(Instruction[22]), .B(RRs1[2]), .CI(n_5_3), .CO(n_5_4), .S(n_2) + ); + FA_X1_LVT i_5_5( + .A(Instruction[23]), .B(RRs1[3]), .CI(n_5_4), .CO(n_5_5), .S(n_3) + ); + FA_X1_LVT i_5_6( + .A(Instruction[24]), .B(RRs1[4]), .CI(n_5_5), .CO(n_5_6), .S(n_4) + ); + FA_X1_LVT i_5_7( + .A(Instruction[25]), .B(RRs1[5]), .CI(n_5_6), .CO(n_5_7), .S(n_5) + ); + FA_X1_LVT i_5_8( + .A(Instruction[26]), .B(RRs1[6]), .CI(n_5_7), .CO(n_5_8), .S(n_6) + ); + FA_X1_LVT i_5_9( + .A(Instruction[27]), .B(RRs1[7]), .CI(n_5_8), .CO(n_5_9), .S(n_7) + ); + FA_X1_LVT i_5_10( + .A(Instruction[28]), .B(RRs1[8]), .CI(n_5_9), .CO(n_5_10), .S(n_8) + ); + FA_X1_LVT i_5_11( + .A(Instruction[29]), .B(RRs1[9]), .CI(n_5_10), .CO(n_5_11), .S(n_9) + ); + FA_X1_LVT i_5_12( + .A(Instruction[30]), .B(RRs1[10]), .CI(n_5_11), .CO(n_5_12), .S(n_10) + ); + FA_X1_LVT i_5_13( + .A(RRs1[11]), .B(Instruction[31]), .CI(n_5_12), .CO(n_5_13), .S(n_11) + ); + FA_X1_LVT i_5_14( + .A(n_5_0), .B(n_5_1), .CI(n_5_13), .CO(n_5_14), .S(n_12) + ); + FA_X1_LVT i_5_15( + .A(RRs1[13]), .B(n_5_1), .CI(n_5_14), .CO(n_5_15), .S(n_13) + ); + FA_X1_LVT i_5_16( + .A(RRs1[14]), .B(n_5_1), .CI(n_5_15), .CO(n_5_16), .S(n_14) + ); + FA_X1_LVT i_5_17( + .A(RRs1[15]), .B(n_5_1), .CI(n_5_16), .CO(n_5_17), .S(n_15) + ); + FA_X1_LVT i_5_18( + .A(RRs1[16]), .B(n_5_1), .CI(n_5_17), .CO(n_5_18), .S(n_16) + ); + FA_X1_LVT i_5_19( + .A(RRs1[17]), .B(n_5_1), .CI(n_5_18), .CO(n_5_19), .S(n_17) + ); + FA_X1_LVT i_5_20( + .A(RRs1[18]), .B(n_5_1), .CI(n_5_19), .CO(n_5_20), .S(n_18) + ); + FA_X1_LVT i_5_21( + .A(RRs1[19]), .B(n_5_1), .CI(n_5_20), .CO(n_5_21), .S(n_19) + ); + FA_X1_LVT i_5_22( + .A(RRs1[20]), .B(n_5_1), .CI(n_5_21), .CO(n_5_22), .S(n_20) + ); + FA_X1_LVT i_5_23( + .A(RRs1[21]), .B(n_5_1), .CI(n_5_22), .CO(n_5_23), .S(n_21) + ); + FA_X1_LVT i_5_24( + .A(RRs1[22]), .B(n_5_1), .CI(n_5_23), .CO(n_5_24), .S(n_22) + ); + FA_X1_LVT i_5_25( + .A(RRs1[23]), .B(n_5_1), .CI(n_5_24), .CO(n_5_25), .S(n_23) + ); + FA_X1_LVT i_5_26( + .A(RRs1[24]), .B(n_5_1), .CI(n_5_25), .CO(n_5_26), .S(n_24) + ); + FA_X1_LVT i_5_27( + .A(RRs1[25]), .B(n_5_1), .CI(n_5_26), .CO(n_5_27), .S(n_25) + ); + FA_X1_LVT i_5_28( + .A(RRs1[26]), .B(n_5_1), .CI(n_5_27), .CO(n_5_28), .S(n_26) + ); + FA_X1_LVT i_5_29( + .A(RRs1[27]), .B(n_5_1), .CI(n_5_28), .CO(n_5_29), .S(n_27) + ); + FA_X1_LVT i_5_30( + .A(RRs1[28]), .B(n_5_1), .CI(n_5_29), .CO(n_5_30), .S(n_28) + ); + FA_X1_LVT i_5_31( + .A(RRs1[29]), .B(n_5_1), .CI(n_5_30), .CO(n_5_31), .S(n_29) + ); + FA_X1_LVT i_5_32( + .A(RRs1[30]), .B(n_5_1), .CI(n_5_31), .CO(n_5_32), .S(n_30) + ); + XNOR2_X1_LVT i_5_34( + .A(n_5_33), .B(n_5_32), .ZN(n_31) + ); + NOR2_X1_LVT i_0_107( + .A1(n_0_249), .A2(Instruction[3]), .ZN(n_0_90) + ); + AOI222_X1_LVT i_0_106( + .A1(n_93), .A2(n_0_99), .B1(n_0_91), .B2(n_62), .C1(n_31), .C2(n_0_90), .ZN(n_0_89) + ); + INV_X1_LVT i_0_355( + .A(Instruction[6]), .ZN(n_0_248) + ); + NAND2_X1_LVT i_0_339( + .A1(n_0_248), .A2(Instruction[4]), .ZN(n_0_234) + ); + INV_X1_LVT i_0_338( + .A(n_0_234), .ZN(n_0_233) + ); + OAI21_X1_LVT i_0_341( + .A(Instruction[13]), .B1(Instruction[14]), .B2(Instruction[12]), .ZN(n_0_236) + ); + AOI211_X1_LVT i_0_337( + .A(n_0_235), .B(n_0_233), .C1(n_0_248), .C2(n_0_236), .ZN(n_0_232) + ); + INV_X1_LVT i_0_352( + .A(Instruction[4]), .ZN(n_0_245) + ); + NAND2_X1_LVT i_0_344( + .A1(n_0_245), .A2(Instruction[2]), .ZN(n_0_239) + ); + AOI21_X1_LVT i_0_335( + .A(Instruction[6]), .B1(n_0_243), .B2(n_0_239), .ZN(n_0_230) + ); + NOR2_X1_LVT i_0_334( + .A1(n_0_232), .A2(n_0_230), .ZN(n_0_229) + ); + NAND2_X1_LVT i_0_342( + .A1(n_0_241), .A2(n_0_238), .ZN(n_0_237) + ); + NAND2_X1_LVT i_0_336( + .A1(Instruction[6]), .A2(n_0_240), .ZN(n_0_231) + ); + OAI211_X1_LVT i_0_333( + .A(n_0_229), .B(n_0_237), .C1(Instruction[2]), .C2(n_0_231), .ZN(Illegal) + ); + NAND2_X1_LVT i_0_109( + .A1(Illegal), .A2(CurrentPC[31]), .ZN(n_0_92) + ); + NAND2_X1_LVT i_0_105( + .A1(n_0_89), .A2(n_0_92), .ZN(JumpOrBranchPC[31]) + ); + AOI222_X1_LVT i_0_103( + .A1(n_92), .A2(n_0_99), .B1(n_0_91), .B2(n_61), .C1(n_30), .C2(n_0_90), .ZN(n_0_87) + ); + NAND2_X1_LVT i_0_104( + .A1(Illegal), .A2(CurrentPC[30]), .ZN(n_0_88) + ); + NAND2_X1_LVT i_0_102( + .A1(n_0_87), .A2(n_0_88), .ZN(JumpOrBranchPC[30]) + ); + AOI222_X1_LVT i_0_100( + .A1(n_91), .A2(n_0_99), .B1(n_0_91), .B2(n_60), .C1(n_29), .C2(n_0_90), .ZN(n_0_85) + ); + NAND2_X1_LVT i_0_101( + .A1(Illegal), .A2(CurrentPC[29]), .ZN(n_0_86) + ); + NAND2_X1_LVT i_0_99( + .A1(n_0_85), .A2(n_0_86), .ZN(JumpOrBranchPC[29]) + ); + AOI222_X1_LVT i_0_97( + .A1(n_90), .A2(n_0_99), .B1(n_0_91), .B2(n_59), .C1(n_28), .C2(n_0_90), .ZN(n_0_83) + ); + NAND2_X1_LVT i_0_98( + .A1(Illegal), .A2(CurrentPC[28]), .ZN(n_0_84) + ); + NAND2_X1_LVT i_0_96( + .A1(n_0_83), .A2(n_0_84), .ZN(JumpOrBranchPC[28]) + ); + AOI222_X1_LVT i_0_94( + .A1(n_89), .A2(n_0_99), .B1(n_0_91), .B2(n_58), .C1(n_27), .C2(n_0_90), .ZN(n_0_81) + ); + NAND2_X1_LVT i_0_95( + .A1(Illegal), .A2(CurrentPC[27]), .ZN(n_0_82) + ); + NAND2_X1_LVT i_0_93( + .A1(n_0_81), .A2(n_0_82), .ZN(JumpOrBranchPC[27]) + ); + AOI222_X1_LVT i_0_91( + .A1(n_88), .A2(n_0_99), .B1(n_0_91), .B2(n_57), .C1(n_26), .C2(n_0_90), .ZN(n_0_79) + ); + NAND2_X1_LVT i_0_92( + .A1(Illegal), .A2(CurrentPC[26]), .ZN(n_0_80) + ); + NAND2_X1_LVT i_0_90( + .A1(n_0_79), .A2(n_0_80), .ZN(JumpOrBranchPC[26]) + ); + AOI222_X1_LVT i_0_88( + .A1(n_87), .A2(n_0_99), .B1(n_0_91), .B2(n_56), .C1(n_25), .C2(n_0_90), .ZN(n_0_77) + ); + NAND2_X1_LVT i_0_89( + .A1(Illegal), .A2(CurrentPC[25]), .ZN(n_0_78) + ); + NAND2_X1_LVT i_0_87( + .A1(n_0_77), .A2(n_0_78), .ZN(JumpOrBranchPC[25]) + ); + AOI222_X1_LVT i_0_85( + .A1(n_86), .A2(n_0_99), .B1(n_0_91), .B2(n_55), .C1(n_24), .C2(n_0_90), .ZN(n_0_75) + ); + NAND2_X1_LVT i_0_86( + .A1(Illegal), .A2(CurrentPC[24]), .ZN(n_0_76) + ); + NAND2_X1_LVT i_0_84( + .A1(n_0_75), .A2(n_0_76), .ZN(JumpOrBranchPC[24]) + ); + AOI222_X1_LVT i_0_82( + .A1(n_85), .A2(n_0_99), .B1(n_0_91), .B2(n_54), .C1(n_23), .C2(n_0_90), .ZN(n_0_73) + ); + NAND2_X1_LVT i_0_83( + .A1(Illegal), .A2(CurrentPC[23]), .ZN(n_0_74) + ); + NAND2_X1_LVT i_0_81( + .A1(n_0_73), .A2(n_0_74), .ZN(JumpOrBranchPC[23]) + ); + AOI222_X1_LVT i_0_79( + .A1(n_84), .A2(n_0_99), .B1(n_0_91), .B2(n_53), .C1(n_22), .C2(n_0_90), .ZN(n_0_71) + ); + NAND2_X1_LVT i_0_80( + .A1(Illegal), .A2(CurrentPC[22]), .ZN(n_0_72) + ); + NAND2_X1_LVT i_0_78( + .A1(n_0_71), .A2(n_0_72), .ZN(JumpOrBranchPC[22]) + ); + AOI222_X1_LVT i_0_76( + .A1(n_83), .A2(n_0_99), .B1(n_0_91), .B2(n_52), .C1(n_21), .C2(n_0_90), .ZN(n_0_69) + ); + NAND2_X1_LVT i_0_77( + .A1(Illegal), .A2(CurrentPC[21]), .ZN(n_0_70) + ); + NAND2_X1_LVT i_0_75( + .A1(n_0_69), .A2(n_0_70), .ZN(JumpOrBranchPC[21]) + ); + AOI222_X1_LVT i_0_73( + .A1(n_82), .A2(n_0_99), .B1(n_0_91), .B2(n_51), .C1(n_20), .C2(n_0_90), .ZN(n_0_67) + ); + NAND2_X1_LVT i_0_74( + .A1(Illegal), .A2(CurrentPC[20]), .ZN(n_0_68) + ); + NAND2_X1_LVT i_0_72( + .A1(n_0_67), .A2(n_0_68), .ZN(JumpOrBranchPC[20]) + ); + AOI222_X1_LVT i_0_70( + .A1(n_81), .A2(n_0_99), .B1(n_0_91), .B2(n_50), .C1(n_19), .C2(n_0_90), .ZN(n_0_65) + ); + NAND2_X1_LVT i_0_71( + .A1(Illegal), .A2(CurrentPC[19]), .ZN(n_0_66) + ); + NAND2_X1_LVT i_0_69( + .A1(n_0_65), .A2(n_0_66), .ZN(JumpOrBranchPC[19]) + ); + AOI222_X1_LVT i_0_67( + .A1(n_80), .A2(n_0_99), .B1(n_0_91), .B2(n_49), .C1(n_18), .C2(n_0_90), .ZN(n_0_63) + ); + NAND2_X1_LVT i_0_68( + .A1(Illegal), .A2(CurrentPC[18]), .ZN(n_0_64) + ); + NAND2_X1_LVT i_0_66( + .A1(n_0_63), .A2(n_0_64), .ZN(JumpOrBranchPC[18]) + ); + AOI222_X1_LVT i_0_64( + .A1(n_79), .A2(n_0_99), .B1(n_0_91), .B2(n_48), .C1(n_17), .C2(n_0_90), .ZN(n_0_61) + ); + NAND2_X1_LVT i_0_65( + .A1(Illegal), .A2(CurrentPC[17]), .ZN(n_0_62) + ); + NAND2_X1_LVT i_0_63( + .A1(n_0_61), .A2(n_0_62), .ZN(JumpOrBranchPC[17]) + ); + AOI222_X1_LVT i_0_61( + .A1(n_78), .A2(n_0_99), .B1(n_0_91), .B2(n_47), .C1(n_16), .C2(n_0_90), .ZN(n_0_59) + ); + NAND2_X1_LVT i_0_62( + .A1(Illegal), .A2(CurrentPC[16]), .ZN(n_0_60) + ); + NAND2_X1_LVT i_0_60( + .A1(n_0_59), .A2(n_0_60), .ZN(JumpOrBranchPC[16]) + ); + AOI222_X1_LVT i_0_58( + .A1(n_77), .A2(n_0_99), .B1(n_0_91), .B2(n_46), .C1(n_15), .C2(n_0_90), .ZN(n_0_57) + ); + NAND2_X1_LVT i_0_59( + .A1(Illegal), .A2(CurrentPC[15]), .ZN(n_0_58) + ); + NAND2_X1_LVT i_0_57( + .A1(n_0_57), .A2(n_0_58), .ZN(JumpOrBranchPC[15]) + ); + AOI222_X1_LVT i_0_55( + .A1(n_76), .A2(n_0_99), .B1(n_0_91), .B2(n_45), .C1(n_14), .C2(n_0_90), .ZN(n_0_55) + ); + NAND2_X1_LVT i_0_56( + .A1(Illegal), .A2(CurrentPC[14]), .ZN(n_0_56) + ); + NAND2_X1_LVT i_0_54( + .A1(n_0_55), .A2(n_0_56), .ZN(JumpOrBranchPC[14]) + ); + AOI222_X1_LVT i_0_52( + .A1(n_75), .A2(n_0_99), .B1(n_0_91), .B2(n_44), .C1(n_13), .C2(n_0_90), .ZN(n_0_53) + ); + NAND2_X1_LVT i_0_53( + .A1(Illegal), .A2(CurrentPC[13]), .ZN(n_0_54) + ); + NAND2_X1_LVT i_0_51( + .A1(n_0_53), .A2(n_0_54), .ZN(JumpOrBranchPC[13]) + ); + AOI222_X1_LVT i_0_49( + .A1(n_74), .A2(n_0_99), .B1(n_0_91), .B2(n_43), .C1(n_12), .C2(n_0_90), .ZN(n_0_51) + ); + NAND2_X1_LVT i_0_50( + .A1(Illegal), .A2(CurrentPC[12]), .ZN(n_0_52) + ); + NAND2_X1_LVT i_0_48( + .A1(n_0_51), .A2(n_0_52), .ZN(JumpOrBranchPC[12]) + ); + AOI222_X1_LVT i_0_46( + .A1(n_73), .A2(n_0_99), .B1(n_0_91), .B2(n_42), .C1(n_11), .C2(n_0_90), .ZN(n_0_49) + ); + NAND2_X1_LVT i_0_47( + .A1(Illegal), .A2(CurrentPC[11]), .ZN(n_0_50) + ); + NAND2_X1_LVT i_0_45( + .A1(n_0_49), .A2(n_0_50), .ZN(JumpOrBranchPC[11]) + ); + AOI222_X1_LVT i_0_43( + .A1(n_72), .A2(n_0_99), .B1(n_0_91), .B2(n_41), .C1(n_10), .C2(n_0_90), .ZN(n_0_47) + ); + NAND2_X1_LVT i_0_44( + .A1(Illegal), .A2(CurrentPC[10]), .ZN(n_0_48) + ); + NAND2_X1_LVT i_0_42( + .A1(n_0_47), .A2(n_0_48), .ZN(JumpOrBranchPC[10]) + ); + AOI222_X1_LVT i_0_40( + .A1(n_71), .A2(n_0_99), .B1(n_0_91), .B2(n_40), .C1(n_9), .C2(n_0_90), .ZN(n_0_45) + ); + NAND2_X1_LVT i_0_41( + .A1(Illegal), .A2(CurrentPC[9]), .ZN(n_0_46) + ); + NAND2_X1_LVT i_0_39( + .A1(n_0_45), .A2(n_0_46), .ZN(JumpOrBranchPC[9]) + ); + AOI222_X1_LVT i_0_37( + .A1(n_70), .A2(n_0_99), .B1(n_0_91), .B2(n_39), .C1(n_8), .C2(n_0_90), .ZN(n_0_43) + ); + NAND2_X1_LVT i_0_38( + .A1(Illegal), .A2(CurrentPC[8]), .ZN(n_0_44) + ); + NAND2_X1_LVT i_0_36( + .A1(n_0_43), .A2(n_0_44), .ZN(JumpOrBranchPC[8]) + ); + AOI222_X1_LVT i_0_34( + .A1(n_69), .A2(n_0_99), .B1(n_0_91), .B2(n_38), .C1(n_7), .C2(n_0_90), .ZN(n_0_41) + ); + NAND2_X1_LVT i_0_35( + .A1(Illegal), .A2(CurrentPC[7]), .ZN(n_0_42) + ); + NAND2_X1_LVT i_0_33( + .A1(n_0_41), .A2(n_0_42), .ZN(JumpOrBranchPC[7]) + ); + AOI222_X1_LVT i_0_31( + .A1(n_68), .A2(n_0_99), .B1(n_0_91), .B2(n_37), .C1(n_6), .C2(n_0_90), .ZN(n_0_39) + ); + NAND2_X1_LVT i_0_32( + .A1(Illegal), .A2(CurrentPC[6]), .ZN(n_0_40) + ); + NAND2_X1_LVT i_0_30( + .A1(n_0_39), .A2(n_0_40), .ZN(JumpOrBranchPC[6]) + ); + AOI222_X1_LVT i_0_28( + .A1(n_67), .A2(n_0_99), .B1(n_0_91), .B2(n_36), .C1(n_5), .C2(n_0_90), .ZN(n_0_37) + ); + NAND2_X1_LVT i_0_29( + .A1(Illegal), .A2(CurrentPC[5]), .ZN(n_0_38) + ); + NAND2_X1_LVT i_0_27( + .A1(n_0_37), .A2(n_0_38), .ZN(JumpOrBranchPC[5]) + ); + AOI222_X1_LVT i_0_25( + .A1(n_66), .A2(n_0_99), .B1(n_0_91), .B2(n_35), .C1(n_4), .C2(n_0_90), .ZN(n_0_35) + ); + NAND2_X1_LVT i_0_26( + .A1(Illegal), .A2(CurrentPC[4]), .ZN(n_0_36) + ); + NAND2_X1_LVT i_0_24( + .A1(n_0_35), .A2(n_0_36), .ZN(JumpOrBranchPC[4]) + ); + AOI222_X1_LVT i_0_22( + .A1(n_65), .A2(n_0_99), .B1(n_0_91), .B2(n_34), .C1(n_3), .C2(n_0_90), .ZN(n_0_33) + ); + NAND2_X1_LVT i_0_23( + .A1(Illegal), .A2(CurrentPC[3]), .ZN(n_0_34) + ); + NAND2_X1_LVT i_0_21( + .A1(n_0_33), .A2(n_0_34), .ZN(JumpOrBranchPC[3]) + ); + AOI222_X1_LVT i_0_19( + .A1(n_64), .A2(n_0_99), .B1(n_0_91), .B2(n_33), .C1(n_2), .C2(n_0_90), .ZN(n_0_31) + ); + NAND2_X1_LVT i_0_20( + .A1(Illegal), .A2(CurrentPC[2]), .ZN(n_0_32) + ); + NAND2_X1_LVT i_0_18( + .A1(n_0_31), .A2(n_0_32), .ZN(JumpOrBranchPC[2]) + ); + AOI222_X1_LVT i_0_16( + .A1(n_63), .A2(n_0_99), .B1(n_0_91), .B2(n_32), .C1(n_1), .C2(n_0_90), .ZN(n_0_29) + ); + NAND2_X1_LVT i_0_17( + .A1(Illegal), .A2(CurrentPC[1]), .ZN(n_0_30) + ); + NAND2_X1_LVT i_0_15( + .A1(n_0_29), .A2(n_0_30), .ZN(JumpOrBranchPC[1]) + ); + NOR2_X1_LVT i_0_112( + .A1(n_0_232), .A2(n_0_238), .ZN(n_0_94) + ); + OAI221_X1_LVT i_0_14( + .A(n_0_94), .B1(n_0_225), .B2(Instruction[2]), .C1(Instruction[6]), .C2(n_0_239), + .ZN(n_0_28) + ); + AND2_X1_LVT i_0_13( + .A1(n_0_28), .A2(CurrentPC[0]), .ZN(JumpOrBranchPC[0]) + ); + NOR2_X1_LVT i_0_221( + .A1(Instruction[13]), .A2(Instruction[14]), .ZN(n_0_166) + ); + NOR3_X1_LVT i_0_293( + .A1(n_0_241), .A2(n_0_234), .A3(Instruction[3]), .ZN(n_0_206) + ); + AND2_X1_LVT i_0_292( + .A1(n_0_206), .A2(n_0_244), .ZN(n_0_205) + ); + NOR3_X1_LVT i_0_330( + .A1(n_0_248), .A2(n_0_244), .A3(Instruction[4]), .ZN(n_0_226) + ); + AOI21_X1_LVT i_0_121( + .A(n_0_205), .B1(n_0_226), .B2(n_0_237), .ZN(n_0_100) + ); + AND2_X1_LVT i_0_120( + .A1(Instruction[14]), .A2(n_0_100), .ZN(aluOp[2]) + ); + OAI33_X1_LVT i_0_119( + .A1(n_0_205), .A2(n_0_247), .A3(n_0_224), .B1(Instruction[2]), .B2(n_0_238), + .B3(n_0_225), .ZN(aluOp[1]) + ); + AOI22_X1_LVT i_0_117( + .A1(Instruction[12]), .A2(n_0_100), .B1(n_0_99), .B2(Instruction[13]), .ZN(n_0_98) + ); + INV_X1_LVT i_0_116( + .A(n_0_98), .ZN(aluOp[0]) + ); + OR2_X1_LVT i_0_327( + .A1(n_0_238), .A2(n_0_234), .ZN(n_0_223) + ); + NOR4_X1_LVT i_0_125( + .A1(Instruction[28]), .A2(Instruction[27]), .A3(Instruction[26]), .A4(Instruction[25]), + .ZN(n_0_103) + ); + INV_X1_LVT i_0_347( + .A(Instruction[30]), .ZN(n_0_242) + ); + NOR4_X1_LVT i_0_124( + .A1(Instruction[13]), .A2(n_0_242), .A3(Instruction[29]), .A4(Instruction[31]), + .ZN(n_0_102) + ); + NAND2_X1_LVT i_0_123( + .A1(n_0_103), .A2(n_0_102), .ZN(n_0_101) + ); + NOR3_X1_LVT i_0_127( + .A1(n_0_244), .A2(Instruction[12]), .A3(Instruction[14]), .ZN(n_0_105) + ); + AOI21_X1_LVT i_0_126( + .A(n_0_105), .B1(Instruction[12]), .B2(Instruction[14]), .ZN(n_0_104) + ); + NOR4_X1_LVT i_0_122( + .A1(n_0_223), .A2(n_0_101), .A3(n_0_104), .A4(Instruction[2]), .ZN(aluNegAr) + ); + OR3_X1_LVT i_0_325( + .A1(n_0_228), .A2(Instruction[4]), .A3(Instruction[6]), .ZN(n_0_222) + ); + NOR2_X1_LVT i_0_321( + .A1(n_0_222), .A2(Instruction[5]), .ZN(n_0_221) + ); + NOR3_X1_LVT i_0_224( + .A1(n_0_224), .A2(n_0_221), .A3(n_0_206), .ZN(n_0_169) + ); + NOR3_X1_LVT i_0_129( + .A1(n_0_234), .A2(Instruction[3]), .A3(Instruction[5]), .ZN(n_0_106) + ); + NOR3_X1_LVT i_0_128( + .A1(n_0_226), .A2(n_0_169), .A3(n_0_106), .ZN(aluBypass) + ); + AOI22_X1_LVT i_0_223( + .A1(CurrentPC[31]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[31]), .ZN(n_0_168) + ); + NOR3_X1_LVT i_0_219( + .A1(n_0_247), .A2(n_0_222), .A3(Instruction[5]), .ZN(n_0_164) + ); + AOI22_X1_LVT i_0_218( + .A1(RRs1[31]), .A2(n_0_169), .B1(n_0_164), .B2(RData[31]), .ZN(n_0_163) + ); + MUX2_X1_LVT i_0_222( + .A(RData[7]), .B(RData[15]), .S(Instruction[12]), .Z(n_0_167) + ); + NAND3_X1_LVT i_0_220( + .A1(n_0_221), .A2(n_0_167), .A3(n_0_166), .ZN(n_0_165) + ); + NAND3_X1_LVT i_0_217( + .A1(n_0_168), .A2(n_0_163), .A3(n_0_165), .ZN(op1[31]) + ); + AOI22_X1_LVT i_0_216( + .A1(RRs1[30]), .A2(n_0_169), .B1(n_0_164), .B2(RData[30]), .ZN(n_0_162) + ); + AOI22_X1_LVT i_0_215( + .A1(CurrentPC[30]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[30]), .ZN(n_0_161) + ); + NAND3_X1_LVT i_0_214( + .A1(n_0_162), .A2(n_0_161), .A3(n_0_165), .ZN(op1[30]) + ); + AOI22_X1_LVT i_0_213( + .A1(RRs1[29]), .A2(n_0_169), .B1(n_0_164), .B2(RData[29]), .ZN(n_0_160) + ); + AOI22_X1_LVT i_0_212( + .A1(CurrentPC[29]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[29]), .ZN(n_0_159) + ); + NAND3_X1_LVT i_0_211( + .A1(n_0_160), .A2(n_0_159), .A3(n_0_165), .ZN(op1[29]) + ); + AOI22_X1_LVT i_0_210( + .A1(RRs1[28]), .A2(n_0_169), .B1(n_0_164), .B2(RData[28]), .ZN(n_0_158) + ); + AOI22_X1_LVT i_0_209( + .A1(CurrentPC[28]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[28]), .ZN(n_0_157) + ); + NAND3_X1_LVT i_0_208( + .A1(n_0_158), .A2(n_0_157), .A3(n_0_165), .ZN(op1[28]) + ); + AOI22_X1_LVT i_0_207( + .A1(RRs1[27]), .A2(n_0_169), .B1(n_0_164), .B2(RData[27]), .ZN(n_0_156) + ); + AOI22_X1_LVT i_0_206( + .A1(CurrentPC[27]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[27]), .ZN(n_0_155) + ); + NAND3_X1_LVT i_0_205( + .A1(n_0_156), .A2(n_0_155), .A3(n_0_165), .ZN(op1[27]) + ); + AOI22_X1_LVT i_0_204( + .A1(RRs1[26]), .A2(n_0_169), .B1(n_0_164), .B2(RData[26]), .ZN(n_0_154) + ); + AOI22_X1_LVT i_0_203( + .A1(CurrentPC[26]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[26]), .ZN(n_0_153) + ); + NAND3_X1_LVT i_0_202( + .A1(n_0_154), .A2(n_0_153), .A3(n_0_165), .ZN(op1[26]) + ); + AOI22_X1_LVT i_0_201( + .A1(RRs1[25]), .A2(n_0_169), .B1(n_0_164), .B2(RData[25]), .ZN(n_0_152) + ); + AOI22_X1_LVT i_0_200( + .A1(CurrentPC[25]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[25]), .ZN(n_0_151) + ); + NAND3_X1_LVT i_0_199( + .A1(n_0_152), .A2(n_0_151), .A3(n_0_165), .ZN(op1[25]) + ); + AOI22_X1_LVT i_0_198( + .A1(RRs1[24]), .A2(n_0_169), .B1(n_0_164), .B2(RData[24]), .ZN(n_0_150) + ); + AOI22_X1_LVT i_0_197( + .A1(CurrentPC[24]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[24]), .ZN(n_0_149) + ); + NAND3_X1_LVT i_0_196( + .A1(n_0_150), .A2(n_0_149), .A3(n_0_165), .ZN(op1[24]) + ); + AOI22_X1_LVT i_0_195( + .A1(RRs1[23]), .A2(n_0_169), .B1(n_0_164), .B2(RData[23]), .ZN(n_0_148) + ); + AOI22_X1_LVT i_0_194( + .A1(CurrentPC[23]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[23]), .ZN(n_0_147) + ); + NAND3_X1_LVT i_0_193( + .A1(n_0_148), .A2(n_0_147), .A3(n_0_165), .ZN(op1[23]) + ); + AOI22_X1_LVT i_0_192( + .A1(RRs1[22]), .A2(n_0_169), .B1(n_0_164), .B2(RData[22]), .ZN(n_0_146) + ); + AOI22_X1_LVT i_0_191( + .A1(CurrentPC[22]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[22]), .ZN(n_0_145) + ); + NAND3_X1_LVT i_0_190( + .A1(n_0_146), .A2(n_0_145), .A3(n_0_165), .ZN(op1[22]) + ); + AOI22_X1_LVT i_0_189( + .A1(RRs1[21]), .A2(n_0_169), .B1(n_0_164), .B2(RData[21]), .ZN(n_0_144) + ); + AOI22_X1_LVT i_0_188( + .A1(CurrentPC[21]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[21]), .ZN(n_0_143) + ); + NAND3_X1_LVT i_0_187( + .A1(n_0_144), .A2(n_0_143), .A3(n_0_165), .ZN(op1[21]) + ); + AOI22_X1_LVT i_0_186( + .A1(RRs1[20]), .A2(n_0_169), .B1(n_0_164), .B2(RData[20]), .ZN(n_0_142) + ); + AOI22_X1_LVT i_0_185( + .A1(CurrentPC[20]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[20]), .ZN(n_0_141) + ); + NAND3_X1_LVT i_0_184( + .A1(n_0_142), .A2(n_0_141), .A3(n_0_165), .ZN(op1[20]) + ); + AOI22_X1_LVT i_0_183( + .A1(RRs1[19]), .A2(n_0_169), .B1(n_0_164), .B2(RData[19]), .ZN(n_0_140) + ); + AOI22_X1_LVT i_0_182( + .A1(CurrentPC[19]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[19]), .ZN(n_0_139) + ); + NAND3_X1_LVT i_0_181( + .A1(n_0_140), .A2(n_0_139), .A3(n_0_165), .ZN(op1[19]) + ); + AOI22_X1_LVT i_0_180( + .A1(RRs1[18]), .A2(n_0_169), .B1(n_0_164), .B2(RData[18]), .ZN(n_0_138) + ); + AOI22_X1_LVT i_0_179( + .A1(CurrentPC[18]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[18]), .ZN(n_0_137) + ); + NAND3_X1_LVT i_0_178( + .A1(n_0_138), .A2(n_0_137), .A3(n_0_165), .ZN(op1[18]) + ); + AOI22_X1_LVT i_0_177( + .A1(RRs1[17]), .A2(n_0_169), .B1(n_0_164), .B2(RData[17]), .ZN(n_0_136) + ); + AOI22_X1_LVT i_0_176( + .A1(CurrentPC[17]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[17]), .ZN(n_0_135) + ); + NAND3_X1_LVT i_0_175( + .A1(n_0_136), .A2(n_0_135), .A3(n_0_165), .ZN(op1[17]) + ); + AOI22_X1_LVT i_0_174( + .A1(RRs1[16]), .A2(n_0_169), .B1(n_0_164), .B2(RData[16]), .ZN(n_0_134) + ); + AOI22_X1_LVT i_0_173( + .A1(CurrentPC[16]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[16]), .ZN(n_0_133) + ); + NAND3_X1_LVT i_0_172( + .A1(n_0_134), .A2(n_0_133), .A3(n_0_165), .ZN(op1[16]) + ); + AOI222_X1_LVT i_0_169( + .A1(CurrentPC[15]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[15]), .C1(n_0_169), + .C2(RRs1[15]), .ZN(n_0_130) + ); + INV_X1_LVT i_0_353( + .A(Instruction[12]), .ZN(n_0_246) + ); + AOI211_X1_LVT i_0_171( + .A(Instruction[5]), .B(n_0_222), .C1(n_0_247), .C2(n_0_246), .ZN(n_0_132) + ); + OAI211_X1_LVT i_0_170( + .A(RData[15]), .B(n_0_132), .C1(Instruction[13]), .C2(Instruction[14]), .ZN(n_0_131) + ); + NAND3_X1_LVT i_0_168( + .A1(n_0_130), .A2(n_0_131), .A3(n_0_165), .ZN(op1[15]) + ); + AOI22_X1_LVT i_0_167( + .A1(RRs1[14]), .A2(n_0_169), .B1(n_0_132), .B2(RData[14]), .ZN(n_0_129) + ); + AOI22_X1_LVT i_0_166( + .A1(CurrentPC[14]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[14]), .ZN(n_0_128) + ); + NAND4_X1_LVT i_0_165( + .A1(n_0_221), .A2(n_0_246), .A3(RData[7]), .A4(n_0_166), .ZN(n_0_127) + ); + NAND3_X1_LVT i_0_164( + .A1(n_0_129), .A2(n_0_128), .A3(n_0_127), .ZN(op1[14]) + ); + AOI22_X1_LVT i_0_163( + .A1(RRs1[13]), .A2(n_0_169), .B1(n_0_132), .B2(RData[13]), .ZN(n_0_126) + ); + AOI22_X1_LVT i_0_162( + .A1(CurrentPC[13]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[13]), .ZN(n_0_125) + ); + NAND3_X1_LVT i_0_161( + .A1(n_0_126), .A2(n_0_125), .A3(n_0_127), .ZN(op1[13]) + ); + AOI22_X1_LVT i_0_160( + .A1(RRs1[12]), .A2(n_0_169), .B1(n_0_132), .B2(RData[12]), .ZN(n_0_124) + ); + AOI22_X1_LVT i_0_159( + .A1(CurrentPC[12]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[12]), .ZN(n_0_123) + ); + NAND3_X1_LVT i_0_158( + .A1(n_0_124), .A2(n_0_123), .A3(n_0_127), .ZN(op1[12]) + ); + AOI22_X1_LVT i_0_156( + .A1(CurrentPC[11]), .A2(n_0_224), .B1(n_0_132), .B2(RData[11]), .ZN(n_0_121) + ); + NAND2_X1_LVT i_0_157( + .A1(RRs1[11]), .A2(n_0_169), .ZN(n_0_122) + ); + NAND3_X1_LVT i_0_155( + .A1(n_0_121), .A2(n_0_122), .A3(n_0_127), .ZN(op1[11]) + ); + AOI22_X1_LVT i_0_153( + .A1(CurrentPC[10]), .A2(n_0_224), .B1(n_0_132), .B2(RData[10]), .ZN(n_0_119) + ); + NAND2_X1_LVT i_0_154( + .A1(RRs1[10]), .A2(n_0_169), .ZN(n_0_120) + ); + NAND3_X1_LVT i_0_152( + .A1(n_0_119), .A2(n_0_120), .A3(n_0_127), .ZN(op1[10]) + ); + AOI22_X1_LVT i_0_150( + .A1(CurrentPC[9]), .A2(n_0_224), .B1(n_0_132), .B2(RData[9]), .ZN(n_0_117) + ); + NAND2_X1_LVT i_0_151( + .A1(RRs1[9]), .A2(n_0_169), .ZN(n_0_118) + ); + NAND3_X1_LVT i_0_149( + .A1(n_0_117), .A2(n_0_118), .A3(n_0_127), .ZN(op1[9]) + ); + AOI22_X1_LVT i_0_147( + .A1(CurrentPC[8]), .A2(n_0_224), .B1(n_0_132), .B2(RData[8]), .ZN(n_0_115) + ); + NAND2_X1_LVT i_0_148( + .A1(RRs1[8]), .A2(n_0_169), .ZN(n_0_116) + ); + NAND3_X1_LVT i_0_146( + .A1(n_0_115), .A2(n_0_116), .A3(n_0_127), .ZN(op1[8]) + ); + AOI222_X1_LVT i_0_145( + .A1(CurrentPC[7]), .A2(n_0_224), .B1(n_0_221), .B2(RData[7]), .C1(n_0_169), + .C2(RRs1[7]), .ZN(n_0_114) + ); + INV_X1_LVT i_0_144( + .A(n_0_114), .ZN(op1[7]) + ); + AOI222_X1_LVT i_0_143( + .A1(CurrentPC[6]), .A2(n_0_224), .B1(n_0_221), .B2(RData[6]), .C1(n_0_169), + .C2(RRs1[6]), .ZN(n_0_113) + ); + INV_X1_LVT i_0_142( + .A(n_0_113), .ZN(op1[6]) + ); + AOI222_X1_LVT i_0_141( + .A1(CurrentPC[5]), .A2(n_0_224), .B1(n_0_221), .B2(RData[5]), .C1(n_0_169), + .C2(RRs1[5]), .ZN(n_0_112) + ); + INV_X1_LVT i_0_140( + .A(n_0_112), .ZN(op1[5]) + ); + AOI222_X1_LVT i_0_139( + .A1(CurrentPC[4]), .A2(n_0_224), .B1(n_0_221), .B2(RData[4]), .C1(n_0_169), + .C2(RRs1[4]), .ZN(n_0_111) + ); + INV_X1_LVT i_0_138( + .A(n_0_111), .ZN(op1[4]) + ); + AOI222_X1_LVT i_0_137( + .A1(CurrentPC[3]), .A2(n_0_224), .B1(n_0_221), .B2(RData[3]), .C1(n_0_169), + .C2(RRs1[3]), .ZN(n_0_110) + ); + INV_X1_LVT i_0_136( + .A(n_0_110), .ZN(op1[3]) + ); + AOI222_X1_LVT i_0_135( + .A1(CurrentPC[2]), .A2(n_0_224), .B1(n_0_221), .B2(RData[2]), .C1(n_0_169), + .C2(RRs1[2]), .ZN(n_0_109) + ); + INV_X1_LVT i_0_134( + .A(n_0_109), .ZN(op1[2]) + ); + AOI222_X1_LVT i_0_133( + .A1(CurrentPC[1]), .A2(n_0_224), .B1(n_0_221), .B2(RData[1]), .C1(n_0_169), + .C2(RRs1[1]), .ZN(n_0_108) + ); + INV_X1_LVT i_0_132( + .A(n_0_108), .ZN(op1[1]) + ); + AOI222_X1_LVT i_0_131( + .A1(CurrentPC[0]), .A2(n_0_224), .B1(n_0_221), .B2(RData[0]), .C1(n_0_169), + .C2(RRs1[0]), .ZN(n_0_107) + ); + INV_X1_LVT i_0_130( + .A(n_0_107), .ZN(op1[0]) + ); + NOR3_X1_LVT i_0_294( + .A1(n_0_223), .A2(Instruction[2]), .A3(Instruction[5]), .ZN(n_0_207) + ); + NOR3_X1_LVT i_0_291( + .A1(n_0_224), .A2(n_0_207), .A3(n_0_205), .ZN(n_0_204) + ); + AOI22_X1_LVT i_0_289( + .A1(CurrentPC[31]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[31]), .ZN(n_0_202) + ); + NAND2_X1_LVT i_0_290( + .A1(Instruction[31]), .A2(n_0_207), .ZN(n_0_203) + ); + NAND2_X1_LVT i_0_288( + .A1(n_0_202), .A2(n_0_203), .ZN(op2[31]) + ); + AOI22_X1_LVT i_0_287( + .A1(CurrentPC[30]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[30]), .ZN(n_0_201) + ); + NAND2_X1_LVT i_0_286( + .A1(n_0_201), .A2(n_0_203), .ZN(op2[30]) + ); + AOI22_X1_LVT i_0_285( + .A1(CurrentPC[29]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[29]), .ZN(n_0_200) + ); + NAND2_X1_LVT i_0_284( + .A1(n_0_200), .A2(n_0_203), .ZN(op2[29]) + ); + AOI22_X1_LVT i_0_283( + .A1(CurrentPC[28]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[28]), .ZN(n_0_199) + ); + NAND2_X1_LVT i_0_282( + .A1(n_0_199), .A2(n_0_203), .ZN(op2[28]) + ); + AOI22_X1_LVT i_0_281( + .A1(CurrentPC[27]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[27]), .ZN(n_0_198) + ); + NAND2_X1_LVT i_0_280( + .A1(n_0_198), .A2(n_0_203), .ZN(op2[27]) + ); + AOI22_X1_LVT i_0_279( + .A1(CurrentPC[26]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[26]), .ZN(n_0_197) + ); + NAND2_X1_LVT i_0_278( + .A1(n_0_197), .A2(n_0_203), .ZN(op2[26]) + ); + AOI22_X1_LVT i_0_277( + .A1(CurrentPC[25]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[25]), .ZN(n_0_196) + ); + NAND2_X1_LVT i_0_276( + .A1(n_0_196), .A2(n_0_203), .ZN(op2[25]) + ); + AOI22_X1_LVT i_0_275( + .A1(CurrentPC[24]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[24]), .ZN(n_0_195) + ); + NAND2_X1_LVT i_0_274( + .A1(n_0_195), .A2(n_0_203), .ZN(op2[24]) + ); + AOI22_X1_LVT i_0_273( + .A1(CurrentPC[23]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[23]), .ZN(n_0_194) + ); + NAND2_X1_LVT i_0_272( + .A1(n_0_194), .A2(n_0_203), .ZN(op2[23]) + ); + AOI22_X1_LVT i_0_271( + .A1(CurrentPC[22]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[22]), .ZN(n_0_193) + ); + NAND2_X1_LVT i_0_270( + .A1(n_0_193), .A2(n_0_203), .ZN(op2[22]) + ); + AOI22_X1_LVT i_0_269( + .A1(CurrentPC[21]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[21]), .ZN(n_0_192) + ); + NAND2_X1_LVT i_0_268( + .A1(n_0_192), .A2(n_0_203), .ZN(op2[21]) + ); + AOI22_X1_LVT i_0_267( + .A1(CurrentPC[20]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[20]), .ZN(n_0_191) + ); + NAND2_X1_LVT i_0_266( + .A1(n_0_191), .A2(n_0_203), .ZN(op2[20]) + ); + AOI22_X1_LVT i_0_265( + .A1(CurrentPC[19]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[19]), .ZN(n_0_190) + ); + NAND2_X1_LVT i_0_264( + .A1(n_0_190), .A2(n_0_203), .ZN(op2[19]) + ); + AOI22_X1_LVT i_0_263( + .A1(CurrentPC[18]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[18]), .ZN(n_0_189) + ); + NAND2_X1_LVT i_0_262( + .A1(n_0_189), .A2(n_0_203), .ZN(op2[18]) + ); + AOI22_X1_LVT i_0_261( + .A1(CurrentPC[17]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[17]), .ZN(n_0_188) + ); + NAND2_X1_LVT i_0_260( + .A1(n_0_188), .A2(n_0_203), .ZN(op2[17]) + ); + AOI22_X1_LVT i_0_259( + .A1(CurrentPC[16]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[16]), .ZN(n_0_187) + ); + NAND2_X1_LVT i_0_258( + .A1(n_0_187), .A2(n_0_203), .ZN(op2[16]) + ); + AOI22_X1_LVT i_0_257( + .A1(CurrentPC[15]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[15]), .ZN(n_0_186) + ); + NAND2_X1_LVT i_0_256( + .A1(n_0_186), .A2(n_0_203), .ZN(op2[15]) + ); + AOI22_X1_LVT i_0_255( + .A1(CurrentPC[14]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[14]), .ZN(n_0_185) + ); + NAND2_X1_LVT i_0_254( + .A1(n_0_185), .A2(n_0_203), .ZN(op2[14]) + ); + AOI22_X1_LVT i_0_253( + .A1(CurrentPC[13]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[13]), .ZN(n_0_184) + ); + NAND2_X1_LVT i_0_252( + .A1(n_0_184), .A2(n_0_203), .ZN(op2[13]) + ); + AOI22_X1_LVT i_0_251( + .A1(CurrentPC[12]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[12]), .ZN(n_0_183) + ); + NAND2_X1_LVT i_0_250( + .A1(n_0_183), .A2(n_0_203), .ZN(op2[12]) + ); + AOI22_X1_LVT i_0_249( + .A1(CurrentPC[11]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[11]), .ZN(n_0_182) + ); + NAND2_X1_LVT i_0_248( + .A1(n_0_182), .A2(n_0_203), .ZN(op2[11]) + ); + AOI222_X1_LVT i_0_247( + .A1(Instruction[30]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[10]), .C1(n_0_204), + .C2(RRs2[10]), .ZN(n_0_181) + ); + INV_X1_LVT i_0_246( + .A(n_0_181), .ZN(op2[10]) + ); + AOI222_X1_LVT i_0_245( + .A1(Instruction[29]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[9]), .C1(n_0_204), + .C2(RRs2[9]), .ZN(n_0_180) + ); + INV_X1_LVT i_0_244( + .A(n_0_180), .ZN(op2[9]) + ); + AOI222_X1_LVT i_0_243( + .A1(Instruction[28]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[8]), .C1(n_0_204), + .C2(RRs2[8]), .ZN(n_0_179) + ); + INV_X1_LVT i_0_242( + .A(n_0_179), .ZN(op2[8]) + ); + AOI222_X1_LVT i_0_241( + .A1(Instruction[27]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[7]), .C1(n_0_204), + .C2(RRs2[7]), .ZN(n_0_178) + ); + INV_X1_LVT i_0_240( + .A(n_0_178), .ZN(op2[7]) + ); + AOI222_X1_LVT i_0_239( + .A1(Instruction[26]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[6]), .C1(n_0_204), + .C2(RRs2[6]), .ZN(n_0_177) + ); + INV_X1_LVT i_0_238( + .A(n_0_177), .ZN(op2[6]) + ); + AOI222_X1_LVT i_0_237( + .A1(Instruction[25]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[5]), .C1(n_0_204), + .C2(RRs2[5]), .ZN(n_0_176) + ); + INV_X1_LVT i_0_236( + .A(n_0_176), .ZN(op2[5]) + ); + AOI222_X1_LVT i_0_235( + .A1(Instruction[24]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[4]), .C1(n_0_204), + .C2(RRs2[4]), .ZN(n_0_175) + ); + INV_X1_LVT i_0_234( + .A(n_0_175), .ZN(op2[4]) + ); + AOI222_X1_LVT i_0_233( + .A1(Instruction[23]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[3]), .C1(n_0_204), + .C2(RRs2[3]), .ZN(n_0_174) + ); + INV_X1_LVT i_0_232( + .A(n_0_174), .ZN(op2[3]) + ); + AOI22_X1_LVT i_0_230( + .A1(Instruction[22]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[2]), .ZN(n_0_172) + ); + OAI21_X1_LVT i_0_231( + .A(RRs2[2]), .B1(n_0_223), .B2(Instruction[5]), .ZN(n_0_173) + ); + NAND3_X1_LVT i_0_229( + .A1(n_0_172), .A2(n_0_173), .A3(n_0_249), .ZN(op2[2]) + ); + AOI222_X1_LVT i_0_228( + .A1(Instruction[21]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[1]), .C1(n_0_204), + .C2(RRs2[1]), .ZN(n_0_171) + ); + INV_X1_LVT i_0_227( + .A(n_0_171), .ZN(op2[1]) + ); + AOI222_X1_LVT i_0_226( + .A1(Instruction[20]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[0]), .C1(n_0_204), + .C2(RRs2[0]), .ZN(n_0_170) + ); + INV_X1_LVT i_0_225( + .A(n_0_170), .ZN(op2[0]) + ); + alu theALU( + .aluOp(aluOp), .aluNegAr(aluNegAr), .aluBypass(aluBypass), .op1(op1), .op2(op2), + .result(WRd), .eqFlag(eqFlag) + ); + XNOR2_X1_LVT i_0_115( + .A(Instruction[12]), .B(eqFlag), .ZN(n_0_97) + ); + XNOR2_X1_LVT i_0_114( + .A(Instruction[12]), .B(WRd[0]), .ZN(n_0_96) + ); + AOI22_X1_LVT i_0_113( + .A1(n_0_166), .A2(n_0_97), .B1(n_0_96), .B2(Instruction[14]), .ZN(n_0_95) + ); + AOI22_X1_LVT i_0_111( + .A1(Instruction[6]), .A2(n_0_95), .B1(Instruction[2]), .B2(n_0_245), .ZN(n_0_93) + ); + NAND2_X1_LVT i_0_110( + .A1(n_0_94), .A2(n_0_93), .ZN(JumpOrBranch) + ); + INV_X1_LVT i_0_349( + .A(Instruction[31]), .ZN(n_0_0) + ); + INV_X1_LVT i_0_348( + .A(RRs1[12]), .ZN(n_0_1) + ); + HA_X1_LVT i_0_0( + .A(Instruction[7]), .B(RRs1[0]), .CO(n_0_2), .S(n_0_15) + ); + FA_X1_LVT i_0_1( + .A(Instruction[8]), .B(RRs1[1]), .CI(n_0_2), .CO(n_0_3), .S(n_0_16) + ); + FA_X1_LVT i_0_2( + .A(Instruction[9]), .B(RRs1[2]), .CI(n_0_3), .CO(n_0_4), .S(n_0_17) + ); + FA_X1_LVT i_0_3( + .A(Instruction[10]), .B(RRs1[3]), .CI(n_0_4), .CO(n_0_5), .S(n_0_18) + ); + FA_X1_LVT i_0_4( + .A(Instruction[11]), .B(RRs1[4]), .CI(n_0_5), .CO(n_0_6), .S(n_0_19) + ); + FA_X1_LVT i_0_5( + .A(Instruction[25]), .B(RRs1[5]), .CI(n_0_6), .CO(n_0_7), .S(n_0_20) + ); + FA_X1_LVT i_0_6( + .A(Instruction[26]), .B(RRs1[6]), .CI(n_0_7), .CO(n_0_8), .S(n_0_21) + ); + FA_X1_LVT i_0_7( + .A(Instruction[27]), .B(RRs1[7]), .CI(n_0_8), .CO(n_0_9), .S(n_0_22) + ); + FA_X1_LVT i_0_8( + .A(Instruction[28]), .B(RRs1[8]), .CI(n_0_9), .CO(n_0_10), .S(n_0_23) + ); + FA_X1_LVT i_0_9( + .A(Instruction[29]), .B(RRs1[9]), .CI(n_0_10), .CO(n_0_11), .S(n_0_24) + ); + FA_X1_LVT i_0_10( + .A(Instruction[30]), .B(RRs1[10]), .CI(n_0_11), .CO(n_0_12), .S(n_0_25) + ); + FA_X1_LVT i_0_11( + .A(RRs1[11]), .B(Instruction[31]), .CI(n_0_12), .CO(n_0_13), .S(n_0_26) + ); + FA_X1_LVT i_0_12( + .A(n_0_0), .B(n_0_1), .CI(n_0_13), .CO(n_0_14), .S(n_0_27) + ); + NOR2_X1_LVT i_0_322( + .A1(n_0_244), .A2(n_0_222), .ZN(WrMem) + ); + AOI22_X1_LVT i_0_320( + .A1(n_0_27), .A2(WrMem), .B1(n_0_221), .B2(n_12), .ZN(n_0_220) + ); + INV_X1_LVT i_0_319( + .A(n_0_220), .ZN(DAddr[12]) + ); + AOI22_X1_LVT i_0_318( + .A1(n_0_26), .A2(WrMem), .B1(n_0_221), .B2(n_11), .ZN(n_0_219) + ); + INV_X1_LVT i_0_317( + .A(n_0_219), .ZN(DAddr[11]) + ); + AOI22_X1_LVT i_0_316( + .A1(n_0_25), .A2(WrMem), .B1(n_0_221), .B2(n_10), .ZN(n_0_218) + ); + INV_X1_LVT i_0_315( + .A(n_0_218), .ZN(DAddr[10]) + ); + AOI22_X1_LVT i_0_314( + .A1(n_0_24), .A2(WrMem), .B1(n_0_221), .B2(n_9), .ZN(n_0_217) + ); + INV_X1_LVT i_0_313( + .A(n_0_217), .ZN(DAddr[9]) + ); + AOI22_X1_LVT i_0_312( + .A1(n_0_23), .A2(WrMem), .B1(n_0_221), .B2(n_8), .ZN(n_0_216) + ); + INV_X1_LVT i_0_311( + .A(n_0_216), .ZN(DAddr[8]) + ); + AOI22_X1_LVT i_0_310( + .A1(n_0_22), .A2(WrMem), .B1(n_0_221), .B2(n_7), .ZN(n_0_215) + ); + INV_X1_LVT i_0_309( + .A(n_0_215), .ZN(DAddr[7]) + ); + AOI22_X1_LVT i_0_308( + .A1(n_0_21), .A2(WrMem), .B1(n_0_221), .B2(n_6), .ZN(n_0_214) + ); + INV_X1_LVT i_0_307( + .A(n_0_214), .ZN(DAddr[6]) + ); + AOI22_X1_LVT i_0_306( + .A1(n_0_20), .A2(WrMem), .B1(n_0_221), .B2(n_5), .ZN(n_0_213) + ); + INV_X1_LVT i_0_305( + .A(n_0_213), .ZN(DAddr[5]) + ); + AOI22_X1_LVT i_0_304( + .A1(n_0_19), .A2(WrMem), .B1(n_0_221), .B2(n_4), .ZN(n_0_212) + ); + INV_X1_LVT i_0_303( + .A(n_0_212), .ZN(DAddr[4]) + ); + AOI22_X1_LVT i_0_302( + .A1(n_0_18), .A2(WrMem), .B1(n_0_221), .B2(n_3), .ZN(n_0_211) + ); + INV_X1_LVT i_0_301( + .A(n_0_211), .ZN(DAddr[3]) + ); + AOI22_X1_LVT i_0_300( + .A1(n_0_17), .A2(WrMem), .B1(n_0_221), .B2(n_2), .ZN(n_0_210) + ); + INV_X1_LVT i_0_299( + .A(n_0_210), .ZN(DAddr[2]) + ); + AOI22_X1_LVT i_0_298( + .A1(n_0_16), .A2(WrMem), .B1(n_0_221), .B2(n_1), .ZN(n_0_209) + ); + INV_X1_LVT i_0_297( + .A(n_0_209), .ZN(DAddr[1]) + ); + AOI22_X1_LVT i_0_296( + .A1(n_0_15), .A2(WrMem), .B1(n_0_221), .B2(n_0), .ZN(n_0_208) + ); + INV_X1_LVT i_0_295( + .A(n_0_208), .ZN(DAddr[0]) + ); + OR2_X1_LVT i_0_324( + .A1(n_0_222), .A2(Instruction[13]), .ZN(DWidth[1]) + ); + NOR2_X1_LVT i_0_323( + .A1(n_0_246), .A2(n_0_222), .ZN(DWidth[0]) + ); + NAND3_X1_LVT i_0_331( + .A1(n_0_248), .A2(n_0_244), .A3(n_0_236), .ZN(n_0_227) + ); + OAI211_X1_LVT i_0_326( + .A(n_0_249), .B(n_0_223), .C1(n_0_228), .C2(n_0_227), .ZN(WrReg) + ); +endmodule + +module MemGen_32_11(chip_en, clock, addr, rd_data, rd_en, wr_en, wr_data); + input [31:0] wr_data; + input [10:0] addr; + input chip_en, clock, rd_en, wr_en; + output [31:0] rd_data; + + wire [1:0] mem_sel; + wire n_63, n_62, n_61, n_60, n_59, n_58, n_57, n_56, n_55, n_54, n_53, n_52, + n_51, n_50, n_49, n_48, n_31, n_30, n_29, n_28, n_27, n_26, n_25, n_24, + n_23, n_22, n_21, n_20, n_19, n_18, n_17, n_16, n_47, n_46, n_45, n_44, + n_43, n_42, n_41, n_40, n_39, n_38, n_37, n_36, n_35, n_34, n_33, n_32, + n_15, n_14, n_13, n_12, n_11, n_10, n_9, n_8, n_7, n_6, n_5, n_4, n_3, + n_2, n_1, n_0; + + INV_X1_LVT i_1_3( + .A(addr[10]), .ZN(mem_sel[0]) + ); + MemGen_16_10 genblk1_0_U_hi( + .chip_en(mem_sel[0]), .wr_en(wr_en), .addr({addr[9], addr[8], addr[7], + addr[6], addr[5], addr[4], addr[3], addr[2], addr[1], addr[0]}), .wr_data({ + wr_data[31], wr_data[30], wr_data[29], wr_data[28], wr_data[27], + wr_data[26], wr_data[25], wr_data[24], wr_data[23], wr_data[22], + wr_data[21], wr_data[20], wr_data[19], wr_data[18], wr_data[17], + wr_data[16]}), .clock(clock), .rd_en(rd_en), .rd_data({n_63, n_62, n_61, + n_60, n_59, n_58, n_57, n_56, n_55, n_54, n_53, n_52, n_51, n_50, n_49, + n_48}) + ); + MemGen_16_10 genblk1_1_U_hi( + .chip_en(addr[10]), .wr_en(wr_en), .addr({addr[9], addr[8], addr[7], + addr[6], addr[5], addr[4], addr[3], addr[2], addr[1], addr[0]}), .wr_data({ + wr_data[31], wr_data[30], wr_data[29], wr_data[28], wr_data[27], + wr_data[26], wr_data[25], wr_data[24], wr_data[23], wr_data[22], + wr_data[21], wr_data[20], wr_data[19], wr_data[18], wr_data[17], + wr_data[16]}), .clock(clock), .rd_en(rd_en), .rd_data({n_31, n_30, n_29, + n_28, n_27, n_26, n_25, n_24, n_23, n_22, n_21, n_20, n_19, n_18, n_17, + n_16}) + ); + MUX2_X1_LVT i_1_1_31( + .A(n_63), .B(n_31), .S(addr[10]), .Z(rd_data[31]) + ); + MUX2_X1_LVT i_1_1_30( + .A(n_62), .B(n_30), .S(addr[10]), .Z(rd_data[30]) + ); + MUX2_X1_LVT i_1_1_29( + .A(n_61), .B(n_29), .S(addr[10]), .Z(rd_data[29]) + ); + MUX2_X1_LVT i_1_1_28( + .A(n_60), .B(n_28), .S(addr[10]), .Z(rd_data[28]) + ); + MUX2_X1_LVT i_1_1_27( + .A(n_59), .B(n_27), .S(addr[10]), .Z(rd_data[27]) + ); + MUX2_X1_LVT i_1_1_26( + .A(n_58), .B(n_26), .S(addr[10]), .Z(rd_data[26]) + ); + MUX2_X1_LVT i_1_1_25( + .A(n_57), .B(n_25), .S(addr[10]), .Z(rd_data[25]) + ); + MUX2_X1_LVT i_1_1_24( + .A(n_56), .B(n_24), .S(addr[10]), .Z(rd_data[24]) + ); + MUX2_X1_LVT i_1_1_23( + .A(n_55), .B(n_23), .S(addr[10]), .Z(rd_data[23]) + ); + MUX2_X1_LVT i_1_1_22( + .A(n_54), .B(n_22), .S(addr[10]), .Z(rd_data[22]) + ); + MUX2_X1_LVT i_1_1_21( + .A(n_53), .B(n_21), .S(addr[10]), .Z(rd_data[21]) + ); + MUX2_X1_LVT i_1_1_20( + .A(n_52), .B(n_20), .S(addr[10]), .Z(rd_data[20]) + ); + MUX2_X1_LVT i_1_1_19( + .A(n_51), .B(n_19), .S(addr[10]), .Z(rd_data[19]) + ); + MUX2_X1_LVT i_1_1_18( + .A(n_50), .B(n_18), .S(addr[10]), .Z(rd_data[18]) + ); + MUX2_X1_LVT i_1_1_17( + .A(n_49), .B(n_17), .S(addr[10]), .Z(rd_data[17]) + ); + MUX2_X1_LVT i_1_1_16( + .A(n_48), .B(n_16), .S(addr[10]), .Z(rd_data[16]) + ); + MemGen_16_10 genblk1_0_U_lo( + .chip_en(mem_sel[0]), .wr_en(wr_en), .addr({addr[9], addr[8], addr[7], + addr[6], addr[5], addr[4], addr[3], addr[2], addr[1], addr[0]}), .wr_data({ + wr_data[15], wr_data[14], wr_data[13], wr_data[12], wr_data[11], + wr_data[10], wr_data[9], wr_data[8], wr_data[7], wr_data[6], wr_data[5], + wr_data[4], wr_data[3], wr_data[2], wr_data[1], wr_data[0]}), .clock(clock), + .rd_en(rd_en), .rd_data({n_47, n_46, n_45, n_44, n_43, n_42, n_41, + n_40, n_39, n_38, n_37, n_36, n_35, n_34, n_33, n_32}) + ); + MemGen_16_10 genblk1_1_U_lo( + .chip_en(addr[10]), .wr_en(wr_en), .addr({addr[9], addr[8], addr[7], + addr[6], addr[5], addr[4], addr[3], addr[2], addr[1], addr[0]}), .wr_data({ + wr_data[15], wr_data[14], wr_data[13], wr_data[12], wr_data[11], + wr_data[10], wr_data[9], wr_data[8], wr_data[7], wr_data[6], wr_data[5], + wr_data[4], wr_data[3], wr_data[2], wr_data[1], wr_data[0]}), .clock(clock), + .rd_en(rd_en), .rd_data({n_15, n_14, n_13, n_12, n_11, n_10, n_9, n_8, + n_7, n_6, n_5, n_4, n_3, n_2, n_1, n_0}) + ); + MUX2_X1_LVT i_1_1_15( + .A(n_47), .B(n_15), .S(addr[10]), .Z(rd_data[15]) + ); + MUX2_X1_LVT i_1_1_14( + .A(n_46), .B(n_14), .S(addr[10]), .Z(rd_data[14]) + ); + MUX2_X1_LVT i_1_1_13( + .A(n_45), .B(n_13), .S(addr[10]), .Z(rd_data[13]) + ); + MUX2_X1_LVT i_1_1_12( + .A(n_44), .B(n_12), .S(addr[10]), .Z(rd_data[12]) + ); + MUX2_X1_LVT i_1_1_11( + .A(n_43), .B(n_11), .S(addr[10]), .Z(rd_data[11]) + ); + MUX2_X1_LVT i_1_1_10( + .A(n_42), .B(n_10), .S(addr[10]), .Z(rd_data[10]) + ); + MUX2_X1_LVT i_1_1_9( + .A(n_41), .B(n_9), .S(addr[10]), .Z(rd_data[9]) + ); + MUX2_X1_LVT i_1_1_8( + .A(n_40), .B(n_8), .S(addr[10]), .Z(rd_data[8]) + ); + MUX2_X1_LVT i_1_1_7( + .A(n_39), .B(n_7), .S(addr[10]), .Z(rd_data[7]) + ); + MUX2_X1_LVT i_1_1_6( + .A(n_38), .B(n_6), .S(addr[10]), .Z(rd_data[6]) + ); + MUX2_X1_LVT i_1_1_5( + .A(n_37), .B(n_5), .S(addr[10]), .Z(rd_data[5]) + ); + MUX2_X1_LVT i_1_1_4( + .A(n_36), .B(n_4), .S(addr[10]), .Z(rd_data[4]) + ); + MUX2_X1_LVT i_1_1_3( + .A(n_35), .B(n_3), .S(addr[10]), .Z(rd_data[3]) + ); + MUX2_X1_LVT i_1_1_2( + .A(n_34), .B(n_2), .S(addr[10]), .Z(rd_data[2]) + ); + MUX2_X1_LVT i_1_1_1( + .A(n_33), .B(n_1), .S(addr[10]), .Z(rd_data[1]) + ); + MUX2_X1_LVT i_1_1_0( + .A(n_32), .B(n_0), .S(addr[10]), .Z(rd_data[0]) + ); +endmodule + +module main_mem(clk, reset, DAddr, IAddr, DWData, DRData, IRData, DWE, DWidth); + input [31:0] DAddr, IAddr, DWData; + input [1:0] DWidth; + input clk, reset, DWE; + output [31:0] DRData, IRData; + + wire [31:0] mem_rdata, drTmp, mem_wdata; + wire [10:0] mem_addr; + wire n_0_0, n_0_0_0, n_0_1, n_0_0_1, n_0_2, n_0_0_2, n_0_3, n_0_0_3, n_0_4, + n_0_0_4, n_0_5, n_0_0_5, n_0_6, n_0_0_6, n_0_7, n_0_0_7, n_0_8, n_0_0_8, + n_0_9, n_0_0_9, n_0_10, n_0_0_10, n_0_0_11, n_0_11, n_0_0_12, n_0_0_13, + n_0_12, n_0_0_14, n_0_0_15, n_0_13, n_0_0_16, n_0_0_17, n_0_14, + n_0_0_18, n_0_0_19, n_0_15, n_0_0_20, n_0_0_21, n_0_16, n_0_0_22, + n_0_0_23, n_0_17, n_0_0_24, n_0_0_25, n_0_18, n_0_0_26, n_0_0_27, + n_0_0_28, n_0_19, n_0_0_29, n_0_20, n_0_0_30, n_0_21, n_0_0_31, n_0_22, + n_0_0_32, n_0_23, n_0_0_33, n_0_24, n_0_0_34, n_0_25, n_0_0_35, n_0_26, + n_0_0_36, n_0_0_37, n_0_27, n_0_28, n_0_29, n_0_30, n_0_31, n_0_32, + n_0_33, n_0_34, n_0_35, n_0_36, n_0_37, n_0_38, n_0_39, n_0_40, n_0_41, + n_0_42, n_0_65, n_0_64, n_0_63, n_0_62, n_0_61, n_0_60, n_0_59, n_0_58, + n_0_0_38, n_0_0_39, n_0_57, n_0_0_40, n_0_56, n_0_0_41, n_0_55, + n_0_0_42, n_0_54, n_0_0_43, n_0_53, n_0_0_44, n_0_52, n_0_0_45, n_0_51, + n_0_0_46, n_0_50, n_0_0_47, n_0_0_48, n_0_0_49, n_0_0_50, n_0_0_51, + n_0_49, n_0_0_52, n_0_48, n_0_0_53, n_0_47, n_0_0_54, n_0_46, n_0_0_55, + n_0_45, n_0_0_56, n_0_44, n_0_0_57, n_0_66, n_0_0_58, n_0_67, n_0_0_59, + n_0_0_60, n_0_0_61, n_0_68, n_0_0_62, n_0_0_63, n_0_69, n_0_0_64, + n_0_0_65, n_0_70, n_0_0_66, n_0_0_67, n_0_71, n_0_0_68, n_0_0_69, + n_0_72, n_0_0_70, n_0_0_71, n_0_73, n_0_0_72, n_0_0_73, n_0_74, + n_0_0_74, n_0_0_75, n_0_75, n_0_0_76, n_0_0_77, n_0_0_78, n_0_0_79, + n_0_0_80, n_0_0_81, n_0_0_82, n_0_0_83, n_0_0_84, n_0_0_85, n_0_0_86, + n_0_0_87, n_0_0_88, n_0_0_89, n_0_0_90, n_0_0_91, n_0_0_92, n_0_43, + n_0_0_93, n_0_0_94, n_0_76, n_0_0_95, n_0; + + INV_X1_LVT i_0_0_171( + .A(DWE), .ZN(n_0) + ); + NOR2_X1_LVT i_0_0_163( + .A1(n_0), .A2(reset), .ZN(n_0_0_88) + ); + NOR2_X1_LVT i_0_0_22( + .A1(DWE), .A2(reset), .ZN(n_0_0_11) + ); + AOI22_X1_LVT i_0_0_21( + .A1(DAddr[12]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[12]), .ZN(n_0_0_10) + ); + INV_X1_LVT i_0_0_20( + .A(n_0_0_10), .ZN(n_0_10) + ); + INV_X1_LVT i_0_0_172( + .A(clk), .ZN(n_0_76) + ); + DFF_X1_LVT \mem_addr_reg[10] ( + .CK(n_0_76), .D(n_0_10), .Q(mem_addr[10]), .QN() + ); + AOI22_X1_LVT i_0_0_19( + .A1(DAddr[11]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[11]), .ZN(n_0_0_9) + ); + INV_X1_LVT i_0_0_18( + .A(n_0_0_9), .ZN(n_0_9) + ); + DFF_X1_LVT \mem_addr_reg[9] ( + .CK(n_0_76), .D(n_0_9), .Q(mem_addr[9]), .QN() + ); + AOI22_X1_LVT i_0_0_17( + .A1(DAddr[10]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[10]), .ZN(n_0_0_8) + ); + INV_X1_LVT i_0_0_16( + .A(n_0_0_8), .ZN(n_0_8) + ); + DFF_X1_LVT \mem_addr_reg[8] ( + .CK(n_0_76), .D(n_0_8), .Q(mem_addr[8]), .QN() + ); + AOI22_X1_LVT i_0_0_15( + .A1(DAddr[9]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[9]), .ZN(n_0_0_7) + ); + INV_X1_LVT i_0_0_14( + .A(n_0_0_7), .ZN(n_0_7) + ); + DFF_X1_LVT \mem_addr_reg[7] ( + .CK(n_0_76), .D(n_0_7), .Q(mem_addr[7]), .QN() + ); + AOI22_X1_LVT i_0_0_13( + .A1(DAddr[8]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[8]), .ZN(n_0_0_6) + ); + INV_X1_LVT i_0_0_12( + .A(n_0_0_6), .ZN(n_0_6) + ); + DFF_X1_LVT \mem_addr_reg[6] ( + .CK(n_0_76), .D(n_0_6), .Q(mem_addr[6]), .QN() + ); + AOI22_X1_LVT i_0_0_11( + .A1(DAddr[7]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[7]), .ZN(n_0_0_5) + ); + INV_X1_LVT i_0_0_10( + .A(n_0_0_5), .ZN(n_0_5) + ); + DFF_X1_LVT \mem_addr_reg[5] ( + .CK(n_0_76), .D(n_0_5), .Q(mem_addr[5]), .QN() + ); + AOI22_X1_LVT i_0_0_9( + .A1(DAddr[6]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[6]), .ZN(n_0_0_4) + ); + INV_X1_LVT i_0_0_8( + .A(n_0_0_4), .ZN(n_0_4) + ); + DFF_X1_LVT \mem_addr_reg[4] ( + .CK(n_0_76), .D(n_0_4), .Q(mem_addr[4]), .QN() + ); + AOI22_X1_LVT i_0_0_7( + .A1(DAddr[5]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[5]), .ZN(n_0_0_3) + ); + INV_X1_LVT i_0_0_6( + .A(n_0_0_3), .ZN(n_0_3) + ); + DFF_X1_LVT \mem_addr_reg[3] ( + .CK(n_0_76), .D(n_0_3), .Q(mem_addr[3]), .QN() + ); + AOI22_X1_LVT i_0_0_5( + .A1(DAddr[4]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[4]), .ZN(n_0_0_2) + ); + INV_X1_LVT i_0_0_4( + .A(n_0_0_2), .ZN(n_0_2) + ); + DFF_X1_LVT \mem_addr_reg[2] ( + .CK(n_0_76), .D(n_0_2), .Q(mem_addr[2]), .QN() + ); + AOI22_X1_LVT i_0_0_3( + .A1(DAddr[3]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[3]), .ZN(n_0_0_1) + ); + INV_X1_LVT i_0_0_2( + .A(n_0_0_1), .ZN(n_0_1) + ); + DFF_X1_LVT \mem_addr_reg[1] ( + .CK(n_0_76), .D(n_0_1), .Q(mem_addr[1]), .QN() + ); + AOI22_X1_LVT i_0_0_1( + .A1(DAddr[2]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[2]), .ZN(n_0_0_0) + ); + INV_X1_LVT i_0_0_0( + .A(n_0_0_0), .ZN(n_0_0) + ); + DFF_X1_LVT \mem_addr_reg[0] ( + .CK(n_0_76), .D(n_0_0), .Q(mem_addr[0]), .QN() + ); + NOR2_X1_LVT i_0_0_162( + .A1(DWidth[1]), .A2(DAddr[1]), .ZN(n_0_0_87) + ); + NOR2_X1_LVT i_0_0_158( + .A1(DWidth[0]), .A2(DAddr[0]), .ZN(n_0_0_83) + ); + AND2_X1_LVT i_0_0_157( + .A1(n_0_0_87), .A2(n_0_0_83), .ZN(n_0_0_82) + ); + AND2_X1_LVT i_0_0_156( + .A1(n_0_0_88), .A2(n_0_0_82), .ZN(n_0_0_81) + ); + INV_X1_LVT i_0_0_173( + .A(n_0_0_88), .ZN(n_0_0_95) + ); + INV_X1_LVT i_0_0_169( + .A(DWidth[1]), .ZN(n_0_0_93) + ); + NOR3_X1_LVT i_0_0_155( + .A1(n_0_0_95), .A2(DWidth[0]), .A3(n_0_0_93), .ZN(n_0_0_80) + ); + AOI22_X1_LVT i_0_0_154( + .A1(DWData[7]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[31]), .ZN(n_0_0_79) + ); + NAND2_X1_LVT i_0_0_168( + .A1(DWidth[0]), .A2(DWidth[1]), .ZN(n_0_43) + ); + INV_X1_LVT i_0_0_167( + .A(n_0_43), .ZN(n_0_0_92) + ); + NOR2_X1_LVT i_0_0_160( + .A1(n_0_0_95), .A2(n_0_0_92), .ZN(n_0_0_85) + ); + NAND2_X1_LVT i_0_0_161( + .A1(n_0_0_93), .A2(DAddr[1]), .ZN(n_0_0_86) + ); + NOR2_X1_LVT i_0_0_166( + .A1(DWidth[0]), .A2(DWidth[1]), .ZN(n_0_0_91) + ); + NAND2_X1_LVT i_0_0_164( + .A1(DAddr[0]), .A2(n_0_0_91), .ZN(n_0_0_89) + ); + NAND3_X1_LVT i_0_0_159( + .A1(n_0_0_85), .A2(n_0_0_86), .A3(n_0_0_89), .ZN(n_0_0_84) + ); + INV_X1_LVT i_0_0_170( + .A(DWidth[0]), .ZN(n_0_0_94) + ); + NOR2_X1_LVT i_0_0_153( + .A1(n_0_0_94), .A2(DAddr[1]), .ZN(n_0_0_78) + ); + AND3_X1_LVT i_0_0_152( + .A1(n_0_0_88), .A2(n_0_0_78), .A3(n_0_0_93), .ZN(n_0_0_77) + ); + AOI22_X1_LVT i_0_0_151( + .A1(n_0_0_84), .A2(mem_wdata[31]), .B1(DWData[15]), .B2(n_0_0_77), .ZN(n_0_0_76) + ); + NAND2_X1_LVT i_0_0_150( + .A1(n_0_0_79), .A2(n_0_0_76), .ZN(n_0_75) + ); + DFF_X1_LVT \mem_wdata_reg[31] ( + .CK(n_0_76), .D(n_0_75), .Q(mem_wdata[31]), .QN() + ); + AOI22_X1_LVT i_0_0_149( + .A1(DWData[6]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[30]), .ZN(n_0_0_75) + ); + AOI22_X1_LVT i_0_0_148( + .A1(n_0_0_84), .A2(mem_wdata[30]), .B1(DWData[14]), .B2(n_0_0_77), .ZN(n_0_0_74) + ); + NAND2_X1_LVT i_0_0_147( + .A1(n_0_0_75), .A2(n_0_0_74), .ZN(n_0_74) + ); + DFF_X1_LVT \mem_wdata_reg[30] ( + .CK(n_0_76), .D(n_0_74), .Q(mem_wdata[30]), .QN() + ); + AOI22_X1_LVT i_0_0_146( + .A1(DWData[5]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[29]), .ZN(n_0_0_73) + ); + AOI22_X1_LVT i_0_0_145( + .A1(n_0_0_84), .A2(mem_wdata[29]), .B1(DWData[13]), .B2(n_0_0_77), .ZN(n_0_0_72) + ); + NAND2_X1_LVT i_0_0_144( + .A1(n_0_0_73), .A2(n_0_0_72), .ZN(n_0_73) + ); + DFF_X1_LVT \mem_wdata_reg[29] ( + .CK(n_0_76), .D(n_0_73), .Q(mem_wdata[29]), .QN() + ); + AOI22_X1_LVT i_0_0_143( + .A1(DWData[4]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[28]), .ZN(n_0_0_71) + ); + AOI22_X1_LVT i_0_0_142( + .A1(n_0_0_84), .A2(mem_wdata[28]), .B1(DWData[12]), .B2(n_0_0_77), .ZN(n_0_0_70) + ); + NAND2_X1_LVT i_0_0_141( + .A1(n_0_0_71), .A2(n_0_0_70), .ZN(n_0_72) + ); + DFF_X1_LVT \mem_wdata_reg[28] ( + .CK(n_0_76), .D(n_0_72), .Q(mem_wdata[28]), .QN() + ); + AOI22_X1_LVT i_0_0_140( + .A1(DWData[3]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[27]), .ZN(n_0_0_69) + ); + AOI22_X1_LVT i_0_0_139( + .A1(n_0_0_84), .A2(mem_wdata[27]), .B1(DWData[11]), .B2(n_0_0_77), .ZN(n_0_0_68) + ); + NAND2_X1_LVT i_0_0_138( + .A1(n_0_0_69), .A2(n_0_0_68), .ZN(n_0_71) + ); + DFF_X1_LVT \mem_wdata_reg[27] ( + .CK(n_0_76), .D(n_0_71), .Q(mem_wdata[27]), .QN() + ); + AOI22_X1_LVT i_0_0_137( + .A1(DWData[2]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[26]), .ZN(n_0_0_67) + ); + AOI22_X1_LVT i_0_0_136( + .A1(n_0_0_84), .A2(mem_wdata[26]), .B1(DWData[10]), .B2(n_0_0_77), .ZN(n_0_0_66) + ); + NAND2_X1_LVT i_0_0_135( + .A1(n_0_0_67), .A2(n_0_0_66), .ZN(n_0_70) + ); + DFF_X1_LVT \mem_wdata_reg[26] ( + .CK(n_0_76), .D(n_0_70), .Q(mem_wdata[26]), .QN() + ); + AOI22_X1_LVT i_0_0_134( + .A1(DWData[1]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[25]), .ZN(n_0_0_65) + ); + AOI22_X1_LVT i_0_0_133( + .A1(n_0_0_84), .A2(mem_wdata[25]), .B1(DWData[9]), .B2(n_0_0_77), .ZN(n_0_0_64) + ); + NAND2_X1_LVT i_0_0_132( + .A1(n_0_0_65), .A2(n_0_0_64), .ZN(n_0_69) + ); + DFF_X1_LVT \mem_wdata_reg[25] ( + .CK(n_0_76), .D(n_0_69), .Q(mem_wdata[25]), .QN() + ); + AOI22_X1_LVT i_0_0_131( + .A1(DWData[0]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[24]), .ZN(n_0_0_63) + ); + AOI22_X1_LVT i_0_0_130( + .A1(n_0_0_84), .A2(mem_wdata[24]), .B1(DWData[8]), .B2(n_0_0_77), .ZN(n_0_0_62) + ); + NAND2_X1_LVT i_0_0_129( + .A1(n_0_0_63), .A2(n_0_0_62), .ZN(n_0_68) + ); + DFF_X1_LVT \mem_wdata_reg[24] ( + .CK(n_0_76), .D(n_0_68), .Q(mem_wdata[24]), .QN() + ); + NOR4_X1_LVT i_0_0_127( + .A1(n_0_0_95), .A2(n_0_0_83), .A3(DWidth[1]), .A4(DAddr[1]), .ZN(n_0_0_60) + ); + INV_X1_LVT i_0_0_165( + .A(n_0_0_91), .ZN(n_0_0_90) + ); + OAI211_X1_LVT i_0_0_128( + .A(n_0_0_85), .B(n_0_0_86), .C1(n_0_0_90), .C2(DAddr[0]), .ZN(n_0_0_61) + ); + AOI222_X1_LVT i_0_0_126( + .A1(DWData[7]), .A2(n_0_0_60), .B1(mem_wdata[23]), .B2(n_0_0_61), .C1(DWData[23]), + .C2(n_0_0_80), .ZN(n_0_0_59) + ); + INV_X1_LVT i_0_0_125( + .A(n_0_0_59), .ZN(n_0_67) + ); + DFF_X1_LVT \mem_wdata_reg[23] ( + .CK(n_0_76), .D(n_0_67), .Q(mem_wdata[23]), .QN() + ); + AOI222_X1_LVT i_0_0_124( + .A1(DWData[6]), .A2(n_0_0_60), .B1(mem_wdata[22]), .B2(n_0_0_61), .C1(DWData[22]), + .C2(n_0_0_80), .ZN(n_0_0_58) + ); + INV_X1_LVT i_0_0_123( + .A(n_0_0_58), .ZN(n_0_66) + ); + DFF_X1_LVT \mem_wdata_reg[22] ( + .CK(n_0_76), .D(n_0_66), .Q(mem_wdata[22]), .QN() + ); + AOI222_X1_LVT i_0_0_122( + .A1(DWData[5]), .A2(n_0_0_60), .B1(mem_wdata[21]), .B2(n_0_0_61), .C1(DWData[21]), + .C2(n_0_0_80), .ZN(n_0_0_57) + ); + INV_X1_LVT i_0_0_121( + .A(n_0_0_57), .ZN(n_0_44) + ); + DFF_X1_LVT \mem_wdata_reg[21] ( + .CK(n_0_76), .D(n_0_44), .Q(mem_wdata[21]), .QN() + ); + AOI222_X1_LVT i_0_0_120( + .A1(DWData[4]), .A2(n_0_0_60), .B1(mem_wdata[20]), .B2(n_0_0_61), .C1(DWData[20]), + .C2(n_0_0_80), .ZN(n_0_0_56) + ); + INV_X1_LVT i_0_0_119( + .A(n_0_0_56), .ZN(n_0_45) + ); + DFF_X1_LVT \mem_wdata_reg[20] ( + .CK(n_0_76), .D(n_0_45), .Q(mem_wdata[20]), .QN() + ); + AOI222_X1_LVT i_0_0_118( + .A1(DWData[3]), .A2(n_0_0_60), .B1(mem_wdata[19]), .B2(n_0_0_61), .C1(DWData[19]), + .C2(n_0_0_80), .ZN(n_0_0_55) + ); + INV_X1_LVT i_0_0_117( + .A(n_0_0_55), .ZN(n_0_46) + ); + DFF_X1_LVT \mem_wdata_reg[19] ( + .CK(n_0_76), .D(n_0_46), .Q(mem_wdata[19]), .QN() + ); + AOI222_X1_LVT i_0_0_116( + .A1(DWData[2]), .A2(n_0_0_60), .B1(mem_wdata[18]), .B2(n_0_0_61), .C1(DWData[18]), + .C2(n_0_0_80), .ZN(n_0_0_54) + ); + INV_X1_LVT i_0_0_115( + .A(n_0_0_54), .ZN(n_0_47) + ); + DFF_X1_LVT \mem_wdata_reg[18] ( + .CK(n_0_76), .D(n_0_47), .Q(mem_wdata[18]), .QN() + ); + AOI222_X1_LVT i_0_0_114( + .A1(DWData[1]), .A2(n_0_0_60), .B1(mem_wdata[17]), .B2(n_0_0_61), .C1(DWData[17]), + .C2(n_0_0_80), .ZN(n_0_0_53) + ); + INV_X1_LVT i_0_0_113( + .A(n_0_0_53), .ZN(n_0_48) + ); + DFF_X1_LVT \mem_wdata_reg[17] ( + .CK(n_0_76), .D(n_0_48), .Q(mem_wdata[17]), .QN() + ); + AOI222_X1_LVT i_0_0_112( + .A1(DWData[0]), .A2(n_0_0_60), .B1(mem_wdata[16]), .B2(n_0_0_61), .C1(DWData[16]), + .C2(n_0_0_80), .ZN(n_0_0_52) + ); + INV_X1_LVT i_0_0_111( + .A(n_0_0_52), .ZN(n_0_49) + ); + DFF_X1_LVT \mem_wdata_reg[16] ( + .CK(n_0_76), .D(n_0_49), .Q(mem_wdata[16]), .QN() + ); + NOR4_X1_LVT i_0_0_110( + .A1(n_0_0_95), .A2(n_0_0_87), .A3(n_0_0_92), .A4(n_0_0_91), .ZN(n_0_0_51) + ); + NOR3_X1_LVT i_0_0_109( + .A1(n_0_0_86), .A2(DAddr[0]), .A3(DWidth[0]), .ZN(n_0_0_50) + ); + AND2_X1_LVT i_0_0_108( + .A1(n_0_0_88), .A2(n_0_0_50), .ZN(n_0_0_49) + ); + OAI211_X1_LVT i_0_0_107( + .A(n_0_0_85), .B(n_0_0_89), .C1(DAddr[1]), .C2(DWidth[1]), .ZN(n_0_0_48) + ); + AOI222_X1_LVT i_0_0_106( + .A1(DWData[15]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[7]), .C1(n_0_0_48), + .C2(mem_wdata[15]), .ZN(n_0_0_47) + ); + INV_X1_LVT i_0_0_105( + .A(n_0_0_47), .ZN(n_0_50) + ); + DFF_X1_LVT \mem_wdata_reg[15] ( + .CK(n_0_76), .D(n_0_50), .Q(mem_wdata[15]), .QN() + ); + AOI222_X1_LVT i_0_0_104( + .A1(DWData[14]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[6]), .C1(n_0_0_48), + .C2(mem_wdata[14]), .ZN(n_0_0_46) + ); + INV_X1_LVT i_0_0_103( + .A(n_0_0_46), .ZN(n_0_51) + ); + DFF_X1_LVT \mem_wdata_reg[14] ( + .CK(n_0_76), .D(n_0_51), .Q(mem_wdata[14]), .QN() + ); + AOI222_X1_LVT i_0_0_102( + .A1(DWData[13]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[5]), .C1(n_0_0_48), + .C2(mem_wdata[13]), .ZN(n_0_0_45) + ); + INV_X1_LVT i_0_0_101( + .A(n_0_0_45), .ZN(n_0_52) + ); + DFF_X1_LVT \mem_wdata_reg[13] ( + .CK(n_0_76), .D(n_0_52), .Q(mem_wdata[13]), .QN() + ); + AOI222_X1_LVT i_0_0_100( + .A1(DWData[12]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[4]), .C1(n_0_0_48), + .C2(mem_wdata[12]), .ZN(n_0_0_44) + ); + INV_X1_LVT i_0_0_99( + .A(n_0_0_44), .ZN(n_0_53) + ); + DFF_X1_LVT \mem_wdata_reg[12] ( + .CK(n_0_76), .D(n_0_53), .Q(mem_wdata[12]), .QN() + ); + AOI222_X1_LVT i_0_0_98( + .A1(DWData[11]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[3]), .C1(n_0_0_48), + .C2(mem_wdata[11]), .ZN(n_0_0_43) + ); + INV_X1_LVT i_0_0_97( + .A(n_0_0_43), .ZN(n_0_54) + ); + DFF_X1_LVT \mem_wdata_reg[11] ( + .CK(n_0_76), .D(n_0_54), .Q(mem_wdata[11]), .QN() + ); + AOI222_X1_LVT i_0_0_96( + .A1(DWData[10]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[2]), .C1(n_0_0_48), + .C2(mem_wdata[10]), .ZN(n_0_0_42) + ); + INV_X1_LVT i_0_0_95( + .A(n_0_0_42), .ZN(n_0_55) + ); + DFF_X1_LVT \mem_wdata_reg[10] ( + .CK(n_0_76), .D(n_0_55), .Q(mem_wdata[10]), .QN() + ); + AOI222_X1_LVT i_0_0_94( + .A1(DWData[9]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[1]), .C1(n_0_0_48), + .C2(mem_wdata[9]), .ZN(n_0_0_41) + ); + INV_X1_LVT i_0_0_93( + .A(n_0_0_41), .ZN(n_0_56) + ); + DFF_X1_LVT \mem_wdata_reg[9] ( + .CK(n_0_76), .D(n_0_56), .Q(mem_wdata[9]), .QN() + ); + AOI222_X1_LVT i_0_0_92( + .A1(DWData[8]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[0]), .C1(n_0_0_48), + .C2(mem_wdata[8]), .ZN(n_0_0_40) + ); + INV_X1_LVT i_0_0_91( + .A(n_0_0_40), .ZN(n_0_57) + ); + DFF_X1_LVT \mem_wdata_reg[8] ( + .CK(n_0_76), .D(n_0_57), .Q(mem_wdata[8]), .QN() + ); + AOI21_X1_LVT i_0_0_90( + .A(n_0_0_87), .B1(n_0_0_83), .B2(n_0_0_93), .ZN(n_0_0_39) + ); + NAND2_X1_LVT i_0_0_89( + .A1(n_0_0_85), .A2(n_0_0_39), .ZN(n_0_0_38) + ); + MUX2_X1_LVT i_0_0_88( + .A(DWData[7]), .B(mem_wdata[7]), .S(n_0_0_38), .Z(n_0_58) + ); + DFF_X1_LVT \mem_wdata_reg[7] ( + .CK(n_0_76), .D(n_0_58), .Q(mem_wdata[7]), .QN() + ); + MUX2_X1_LVT i_0_0_87( + .A(DWData[6]), .B(mem_wdata[6]), .S(n_0_0_38), .Z(n_0_59) + ); + DFF_X1_LVT \mem_wdata_reg[6] ( + .CK(n_0_76), .D(n_0_59), .Q(mem_wdata[6]), .QN() + ); + MUX2_X1_LVT i_0_0_86( + .A(DWData[5]), .B(mem_wdata[5]), .S(n_0_0_38), .Z(n_0_60) + ); + DFF_X1_LVT \mem_wdata_reg[5] ( + .CK(n_0_76), .D(n_0_60), .Q(mem_wdata[5]), .QN() + ); + MUX2_X1_LVT i_0_0_85( + .A(DWData[4]), .B(mem_wdata[4]), .S(n_0_0_38), .Z(n_0_61) + ); + DFF_X1_LVT \mem_wdata_reg[4] ( + .CK(n_0_76), .D(n_0_61), .Q(mem_wdata[4]), .QN() + ); + MUX2_X1_LVT i_0_0_84( + .A(DWData[3]), .B(mem_wdata[3]), .S(n_0_0_38), .Z(n_0_62) + ); + DFF_X1_LVT \mem_wdata_reg[3] ( + .CK(n_0_76), .D(n_0_62), .Q(mem_wdata[3]), .QN() + ); + MUX2_X1_LVT i_0_0_83( + .A(DWData[2]), .B(mem_wdata[2]), .S(n_0_0_38), .Z(n_0_63) + ); + DFF_X1_LVT \mem_wdata_reg[2] ( + .CK(n_0_76), .D(n_0_63), .Q(mem_wdata[2]), .QN() + ); + MUX2_X1_LVT i_0_0_82( + .A(DWData[1]), .B(mem_wdata[1]), .S(n_0_0_38), .Z(n_0_64) + ); + DFF_X1_LVT \mem_wdata_reg[1] ( + .CK(n_0_76), .D(n_0_64), .Q(mem_wdata[1]), .QN() + ); + MUX2_X1_LVT i_0_0_81( + .A(DWData[0]), .B(mem_wdata[0]), .S(n_0_0_38), .Z(n_0_65) + ); + DFF_X1_LVT \mem_wdata_reg[0] ( + .CK(n_0_76), .D(n_0_65), .Q(mem_wdata[0]), .QN() + ); + MemGen_32_11 RAM( + .chip_en(), .clock(clk), .addr(mem_addr), .rd_data(mem_rdata), .rd_en(n_0), + .wr_en(DWE), .wr_data(mem_wdata) + ); + DFF_X1_LVT \drTmp_reg[31] ( + .CK(n_0_76), .D(mem_rdata[31]), .Q(drTmp[31]), .QN() + ); + AND2_X1_LVT i_0_0_80( + .A1(DWidth[1]), .A2(drTmp[31]), .ZN(n_0_42) + ); + DLH_X1_LVT \DRData[31] ( + .D(n_0_42), .G(n_0_43), .Q(DRData[31]) + ); + DFF_X1_LVT \drTmp_reg[30] ( + .CK(n_0_76), .D(mem_rdata[30]), .Q(drTmp[30]), .QN() + ); + AND2_X1_LVT i_0_0_79( + .A1(DWidth[1]), .A2(drTmp[30]), .ZN(n_0_41) + ); + DLH_X1_LVT \DRData[30] ( + .D(n_0_41), .G(n_0_43), .Q(DRData[30]) + ); + DFF_X1_LVT \drTmp_reg[29] ( + .CK(n_0_76), .D(mem_rdata[29]), .Q(drTmp[29]), .QN() + ); + AND2_X1_LVT i_0_0_78( + .A1(DWidth[1]), .A2(drTmp[29]), .ZN(n_0_40) + ); + DLH_X1_LVT \DRData[29] ( + .D(n_0_40), .G(n_0_43), .Q(DRData[29]) + ); + DFF_X1_LVT \drTmp_reg[28] ( + .CK(n_0_76), .D(mem_rdata[28]), .Q(drTmp[28]), .QN() + ); + AND2_X1_LVT i_0_0_77( + .A1(DWidth[1]), .A2(drTmp[28]), .ZN(n_0_39) + ); + DLH_X1_LVT \DRData[28] ( + .D(n_0_39), .G(n_0_43), .Q(DRData[28]) + ); + DFF_X1_LVT \drTmp_reg[27] ( + .CK(n_0_76), .D(mem_rdata[27]), .Q(drTmp[27]), .QN() + ); + AND2_X1_LVT i_0_0_76( + .A1(DWidth[1]), .A2(drTmp[27]), .ZN(n_0_38) + ); + DLH_X1_LVT \DRData[27] ( + .D(n_0_38), .G(n_0_43), .Q(DRData[27]) + ); + DFF_X1_LVT \drTmp_reg[26] ( + .CK(n_0_76), .D(mem_rdata[26]), .Q(drTmp[26]), .QN() + ); + AND2_X1_LVT i_0_0_75( + .A1(DWidth[1]), .A2(drTmp[26]), .ZN(n_0_37) + ); + DLH_X1_LVT \DRData[26] ( + .D(n_0_37), .G(n_0_43), .Q(DRData[26]) + ); + DFF_X1_LVT \drTmp_reg[25] ( + .CK(n_0_76), .D(mem_rdata[25]), .Q(drTmp[25]), .QN() + ); + AND2_X1_LVT i_0_0_74( + .A1(DWidth[1]), .A2(drTmp[25]), .ZN(n_0_36) + ); + DLH_X1_LVT \DRData[25] ( + .D(n_0_36), .G(n_0_43), .Q(DRData[25]) + ); + DFF_X1_LVT \drTmp_reg[24] ( + .CK(n_0_76), .D(mem_rdata[24]), .Q(drTmp[24]), .QN() + ); + AND2_X1_LVT i_0_0_73( + .A1(DWidth[1]), .A2(drTmp[24]), .ZN(n_0_35) + ); + DLH_X1_LVT \DRData[24] ( + .D(n_0_35), .G(n_0_43), .Q(DRData[24]) + ); + DFF_X1_LVT \drTmp_reg[23] ( + .CK(n_0_76), .D(mem_rdata[23]), .Q(drTmp[23]), .QN() + ); + AND2_X1_LVT i_0_0_72( + .A1(DWidth[1]), .A2(drTmp[23]), .ZN(n_0_34) + ); + DLH_X1_LVT \DRData[23] ( + .D(n_0_34), .G(n_0_43), .Q(DRData[23]) + ); + DFF_X1_LVT \drTmp_reg[22] ( + .CK(n_0_76), .D(mem_rdata[22]), .Q(drTmp[22]), .QN() + ); + AND2_X1_LVT i_0_0_71( + .A1(DWidth[1]), .A2(drTmp[22]), .ZN(n_0_33) + ); + DLH_X1_LVT \DRData[22] ( + .D(n_0_33), .G(n_0_43), .Q(DRData[22]) + ); + DFF_X1_LVT \drTmp_reg[21] ( + .CK(n_0_76), .D(mem_rdata[21]), .Q(drTmp[21]), .QN() + ); + AND2_X1_LVT i_0_0_70( + .A1(DWidth[1]), .A2(drTmp[21]), .ZN(n_0_32) + ); + DLH_X1_LVT \DRData[21] ( + .D(n_0_32), .G(n_0_43), .Q(DRData[21]) + ); + DFF_X1_LVT \drTmp_reg[20] ( + .CK(n_0_76), .D(mem_rdata[20]), .Q(drTmp[20]), .QN() + ); + AND2_X1_LVT i_0_0_69( + .A1(DWidth[1]), .A2(drTmp[20]), .ZN(n_0_31) + ); + DLH_X1_LVT \DRData[20] ( + .D(n_0_31), .G(n_0_43), .Q(DRData[20]) + ); + DFF_X1_LVT \drTmp_reg[19] ( + .CK(n_0_76), .D(mem_rdata[19]), .Q(drTmp[19]), .QN() + ); + AND2_X1_LVT i_0_0_68( + .A1(DWidth[1]), .A2(drTmp[19]), .ZN(n_0_30) + ); + DLH_X1_LVT \DRData[19] ( + .D(n_0_30), .G(n_0_43), .Q(DRData[19]) + ); + DFF_X1_LVT \drTmp_reg[18] ( + .CK(n_0_76), .D(mem_rdata[18]), .Q(drTmp[18]), .QN() + ); + AND2_X1_LVT i_0_0_67( + .A1(DWidth[1]), .A2(drTmp[18]), .ZN(n_0_29) + ); + DLH_X1_LVT \DRData[18] ( + .D(n_0_29), .G(n_0_43), .Q(DRData[18]) + ); + DFF_X1_LVT \drTmp_reg[17] ( + .CK(n_0_76), .D(mem_rdata[17]), .Q(drTmp[17]), .QN() + ); + AND2_X1_LVT i_0_0_66( + .A1(DWidth[1]), .A2(drTmp[17]), .ZN(n_0_28) + ); + DLH_X1_LVT \DRData[17] ( + .D(n_0_28), .G(n_0_43), .Q(DRData[17]) + ); + DFF_X1_LVT \drTmp_reg[16] ( + .CK(n_0_76), .D(mem_rdata[16]), .Q(drTmp[16]), .QN() + ); + AND2_X1_LVT i_0_0_65( + .A1(DWidth[1]), .A2(drTmp[16]), .ZN(n_0_27) + ); + DLH_X1_LVT \DRData[16] ( + .D(n_0_27), .G(n_0_43), .Q(DRData[16]) + ); + NOR2_X1_LVT i_0_0_64( + .A1(n_0_0_91), .A2(n_0_0_87), .ZN(n_0_0_37) + ); + DFF_X1_LVT \drTmp_reg[15] ( + .CK(n_0_76), .D(mem_rdata[15]), .Q(drTmp[15]), .QN() + ); + AOI22_X1_LVT i_0_0_63( + .A1(drTmp[31]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[15]), .ZN(n_0_0_36) + ); + INV_X1_LVT i_0_0_62( + .A(n_0_0_36), .ZN(n_0_26) + ); + DLH_X1_LVT \DRData[15] ( + .D(n_0_26), .G(n_0_43), .Q(DRData[15]) + ); + DFF_X1_LVT \drTmp_reg[14] ( + .CK(n_0_76), .D(mem_rdata[14]), .Q(drTmp[14]), .QN() + ); + AOI22_X1_LVT i_0_0_61( + .A1(drTmp[30]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[14]), .ZN(n_0_0_35) + ); + INV_X1_LVT i_0_0_60( + .A(n_0_0_35), .ZN(n_0_25) + ); + DLH_X1_LVT \DRData[14] ( + .D(n_0_25), .G(n_0_43), .Q(DRData[14]) + ); + DFF_X1_LVT \drTmp_reg[13] ( + .CK(n_0_76), .D(mem_rdata[13]), .Q(drTmp[13]), .QN() + ); + AOI22_X1_LVT i_0_0_59( + .A1(drTmp[29]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[13]), .ZN(n_0_0_34) + ); + INV_X1_LVT i_0_0_58( + .A(n_0_0_34), .ZN(n_0_24) + ); + DLH_X1_LVT \DRData[13] ( + .D(n_0_24), .G(n_0_43), .Q(DRData[13]) + ); + DFF_X1_LVT \drTmp_reg[12] ( + .CK(n_0_76), .D(mem_rdata[12]), .Q(drTmp[12]), .QN() + ); + AOI22_X1_LVT i_0_0_57( + .A1(drTmp[28]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[12]), .ZN(n_0_0_33) + ); + INV_X1_LVT i_0_0_56( + .A(n_0_0_33), .ZN(n_0_23) + ); + DLH_X1_LVT \DRData[12] ( + .D(n_0_23), .G(n_0_43), .Q(DRData[12]) + ); + DFF_X1_LVT \drTmp_reg[11] ( + .CK(n_0_76), .D(mem_rdata[11]), .Q(drTmp[11]), .QN() + ); + AOI22_X1_LVT i_0_0_55( + .A1(drTmp[27]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[11]), .ZN(n_0_0_32) + ); + INV_X1_LVT i_0_0_54( + .A(n_0_0_32), .ZN(n_0_22) + ); + DLH_X1_LVT \DRData[11] ( + .D(n_0_22), .G(n_0_43), .Q(DRData[11]) + ); + DFF_X1_LVT \drTmp_reg[10] ( + .CK(n_0_76), .D(mem_rdata[10]), .Q(drTmp[10]), .QN() + ); + AOI22_X1_LVT i_0_0_53( + .A1(drTmp[26]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[10]), .ZN(n_0_0_31) + ); + INV_X1_LVT i_0_0_52( + .A(n_0_0_31), .ZN(n_0_21) + ); + DLH_X1_LVT \DRData[10] ( + .D(n_0_21), .G(n_0_43), .Q(DRData[10]) + ); + DFF_X1_LVT \drTmp_reg[9] ( + .CK(n_0_76), .D(mem_rdata[9]), .Q(drTmp[9]), .QN() + ); + AOI22_X1_LVT i_0_0_51( + .A1(drTmp[25]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[9]), .ZN(n_0_0_30) + ); + INV_X1_LVT i_0_0_50( + .A(n_0_0_30), .ZN(n_0_20) + ); + DLH_X1_LVT \DRData[9] ( + .D(n_0_20), .G(n_0_43), .Q(DRData[9]) + ); + DFF_X1_LVT \drTmp_reg[8] ( + .CK(n_0_76), .D(mem_rdata[8]), .Q(drTmp[8]), .QN() + ); + AOI22_X1_LVT i_0_0_49( + .A1(drTmp[24]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[8]), .ZN(n_0_0_29) + ); + INV_X1_LVT i_0_0_48( + .A(n_0_0_29), .ZN(n_0_19) + ); + DLH_X1_LVT \DRData[8] ( + .D(n_0_19), .G(n_0_43), .Q(DRData[8]) + ); + AOI22_X1_LVT i_0_0_46( + .A1(drTmp[31]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[15]), .ZN(n_0_0_27) + ); + AOI211_X1_LVT i_0_0_47( + .A(DAddr[1]), .B(n_0_0_83), .C1(n_0_0_94), .C2(DWidth[1]), .ZN(n_0_0_28) + ); + DFF_X1_LVT \drTmp_reg[7] ( + .CK(n_0_76), .D(mem_rdata[7]), .Q(drTmp[7]), .QN() + ); + AOI22_X1_LVT i_0_0_45( + .A1(drTmp[23]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[7]), .ZN(n_0_0_26) + ); + NAND2_X1_LVT i_0_0_44( + .A1(n_0_0_27), .A2(n_0_0_26), .ZN(n_0_18) + ); + DLH_X1_LVT \DRData[7] ( + .D(n_0_18), .G(n_0_43), .Q(DRData[7]) + ); + AOI22_X1_LVT i_0_0_43( + .A1(drTmp[30]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[14]), .ZN(n_0_0_25) + ); + DFF_X1_LVT \drTmp_reg[6] ( + .CK(n_0_76), .D(mem_rdata[6]), .Q(drTmp[6]), .QN() + ); + AOI22_X1_LVT i_0_0_42( + .A1(drTmp[22]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[6]), .ZN(n_0_0_24) + ); + NAND2_X1_LVT i_0_0_41( + .A1(n_0_0_25), .A2(n_0_0_24), .ZN(n_0_17) + ); + DLH_X1_LVT \DRData[6] ( + .D(n_0_17), .G(n_0_43), .Q(DRData[6]) + ); + AOI22_X1_LVT i_0_0_40( + .A1(drTmp[29]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[13]), .ZN(n_0_0_23) + ); + DFF_X1_LVT \drTmp_reg[5] ( + .CK(n_0_76), .D(mem_rdata[5]), .Q(drTmp[5]), .QN() + ); + AOI22_X1_LVT i_0_0_39( + .A1(drTmp[21]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[5]), .ZN(n_0_0_22) + ); + NAND2_X1_LVT i_0_0_38( + .A1(n_0_0_23), .A2(n_0_0_22), .ZN(n_0_16) + ); + DLH_X1_LVT \DRData[5] ( + .D(n_0_16), .G(n_0_43), .Q(DRData[5]) + ); + AOI22_X1_LVT i_0_0_37( + .A1(drTmp[28]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[12]), .ZN(n_0_0_21) + ); + DFF_X1_LVT \drTmp_reg[4] ( + .CK(n_0_76), .D(mem_rdata[4]), .Q(drTmp[4]), .QN() + ); + AOI22_X1_LVT i_0_0_36( + .A1(drTmp[20]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[4]), .ZN(n_0_0_20) + ); + NAND2_X1_LVT i_0_0_35( + .A1(n_0_0_21), .A2(n_0_0_20), .ZN(n_0_15) + ); + DLH_X1_LVT \DRData[4] ( + .D(n_0_15), .G(n_0_43), .Q(DRData[4]) + ); + AOI22_X1_LVT i_0_0_34( + .A1(drTmp[27]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[11]), .ZN(n_0_0_19) + ); + DFF_X1_LVT \drTmp_reg[3] ( + .CK(n_0_76), .D(mem_rdata[3]), .Q(drTmp[3]), .QN() + ); + AOI22_X1_LVT i_0_0_33( + .A1(drTmp[19]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[3]), .ZN(n_0_0_18) + ); + NAND2_X1_LVT i_0_0_32( + .A1(n_0_0_19), .A2(n_0_0_18), .ZN(n_0_14) + ); + DLH_X1_LVT \DRData[3] ( + .D(n_0_14), .G(n_0_43), .Q(DRData[3]) + ); + AOI22_X1_LVT i_0_0_31( + .A1(drTmp[26]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[10]), .ZN(n_0_0_17) + ); + DFF_X1_LVT \drTmp_reg[2] ( + .CK(n_0_76), .D(mem_rdata[2]), .Q(drTmp[2]), .QN() + ); + AOI22_X1_LVT i_0_0_30( + .A1(drTmp[18]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[2]), .ZN(n_0_0_16) + ); + NAND2_X1_LVT i_0_0_29( + .A1(n_0_0_17), .A2(n_0_0_16), .ZN(n_0_13) + ); + DLH_X1_LVT \DRData[2] ( + .D(n_0_13), .G(n_0_43), .Q(DRData[2]) + ); + AOI22_X1_LVT i_0_0_28( + .A1(drTmp[25]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[9]), .ZN(n_0_0_15) + ); + DFF_X1_LVT \drTmp_reg[1] ( + .CK(n_0_76), .D(mem_rdata[1]), .Q(drTmp[1]), .QN() + ); + AOI22_X1_LVT i_0_0_27( + .A1(drTmp[17]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[1]), .ZN(n_0_0_14) + ); + NAND2_X1_LVT i_0_0_26( + .A1(n_0_0_15), .A2(n_0_0_14), .ZN(n_0_12) + ); + DLH_X1_LVT \DRData[1] ( + .D(n_0_12), .G(n_0_43), .Q(DRData[1]) + ); + AOI22_X1_LVT i_0_0_25( + .A1(drTmp[24]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[8]), .ZN(n_0_0_13) + ); + DFF_X1_LVT \drTmp_reg[0] ( + .CK(n_0_76), .D(mem_rdata[0]), .Q(drTmp[0]), .QN() + ); + AOI22_X1_LVT i_0_0_24( + .A1(drTmp[16]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[0]), .ZN(n_0_0_12) + ); + NAND2_X1_LVT i_0_0_23( + .A1(n_0_0_13), .A2(n_0_0_12), .ZN(n_0_11) + ); + DLH_X1_LVT \DRData[0] ( + .D(n_0_11), .G(n_0_43), .Q(DRData[0]) + ); + DFF_X1_LVT \IRData_reg[31] ( + .CK(clk), .D(mem_rdata[31]), .Q(IRData[31]), .QN() + ); + DFF_X1_LVT \IRData_reg[30] ( + .CK(clk), .D(mem_rdata[30]), .Q(IRData[30]), .QN() + ); + DFF_X1_LVT \IRData_reg[29] ( + .CK(clk), .D(mem_rdata[29]), .Q(IRData[29]), .QN() + ); + DFF_X1_LVT \IRData_reg[28] ( + .CK(clk), .D(mem_rdata[28]), .Q(IRData[28]), .QN() + ); + DFF_X1_LVT \IRData_reg[27] ( + .CK(clk), .D(mem_rdata[27]), .Q(IRData[27]), .QN() + ); + DFF_X1_LVT \IRData_reg[26] ( + .CK(clk), .D(mem_rdata[26]), .Q(IRData[26]), .QN() + ); + DFF_X1_LVT \IRData_reg[25] ( + .CK(clk), .D(mem_rdata[25]), .Q(IRData[25]), .QN() + ); + DFF_X1_LVT \IRData_reg[24] ( + .CK(clk), .D(mem_rdata[24]), .Q(IRData[24]), .QN() + ); + DFF_X1_LVT \IRData_reg[23] ( + .CK(clk), .D(mem_rdata[23]), .Q(IRData[23]), .QN() + ); + DFF_X1_LVT \IRData_reg[22] ( + .CK(clk), .D(mem_rdata[22]), .Q(IRData[22]), .QN() + ); + DFF_X1_LVT \IRData_reg[21] ( + .CK(clk), .D(mem_rdata[21]), .Q(IRData[21]), .QN() + ); + DFF_X1_LVT \IRData_reg[20] ( + .CK(clk), .D(mem_rdata[20]), .Q(IRData[20]), .QN() + ); + DFF_X1_LVT \IRData_reg[19] ( + .CK(clk), .D(mem_rdata[19]), .Q(IRData[19]), .QN() + ); + DFF_X1_LVT \IRData_reg[18] ( + .CK(clk), .D(mem_rdata[18]), .Q(IRData[18]), .QN() + ); + DFF_X1_LVT \IRData_reg[17] ( + .CK(clk), .D(mem_rdata[17]), .Q(IRData[17]), .QN() + ); + DFF_X1_LVT \IRData_reg[16] ( + .CK(clk), .D(mem_rdata[16]), .Q(IRData[16]), .QN() + ); + DFF_X1_LVT \IRData_reg[15] ( + .CK(clk), .D(mem_rdata[15]), .Q(IRData[15]), .QN() + ); + DFF_X1_LVT \IRData_reg[14] ( + .CK(clk), .D(mem_rdata[14]), .Q(IRData[14]), .QN() + ); + DFF_X1_LVT \IRData_reg[13] ( + .CK(clk), .D(mem_rdata[13]), .Q(IRData[13]), .QN() + ); + DFF_X1_LVT \IRData_reg[12] ( + .CK(clk), .D(mem_rdata[12]), .Q(IRData[12]), .QN() + ); + DFF_X1_LVT \IRData_reg[11] ( + .CK(clk), .D(mem_rdata[11]), .Q(IRData[11]), .QN() + ); + DFF_X1_LVT \IRData_reg[10] ( + .CK(clk), .D(mem_rdata[10]), .Q(IRData[10]), .QN() + ); + DFF_X1_LVT \IRData_reg[9] ( + .CK(clk), .D(mem_rdata[9]), .Q(IRData[9]), .QN() + ); + DFF_X1_LVT \IRData_reg[8] ( + .CK(clk), .D(mem_rdata[8]), .Q(IRData[8]), .QN() + ); + DFF_X1_LVT \IRData_reg[7] ( + .CK(clk), .D(mem_rdata[7]), .Q(IRData[7]), .QN() + ); + DFF_X1_LVT \IRData_reg[6] ( + .CK(clk), .D(mem_rdata[6]), .Q(IRData[6]), .QN() + ); + DFF_X1_LVT \IRData_reg[5] ( + .CK(clk), .D(mem_rdata[5]), .Q(IRData[5]), .QN() + ); + DFF_X1_LVT \IRData_reg[4] ( + .CK(clk), .D(mem_rdata[4]), .Q(IRData[4]), .QN() + ); + DFF_X1_LVT \IRData_reg[3] ( + .CK(clk), .D(mem_rdata[3]), .Q(IRData[3]), .QN() + ); + DFF_X1_LVT \IRData_reg[2] ( + .CK(clk), .D(mem_rdata[2]), .Q(IRData[2]), .QN() + ); + DFF_X1_LVT \IRData_reg[1] ( + .CK(clk), .D(mem_rdata[1]), .Q(IRData[1]), .QN() + ); + DFF_X1_LVT \IRData_reg[0] ( + .CK(clk), .D(mem_rdata[0]), .Q(IRData[0]), .QN() + ); +endmodule + +module reg_file(Rs1, Rs2, Rd, RRs1, RRs2, WRd, WrReg, reset, clk, dftIn, ts_intno31, + ts_no1050, ts_no1051, ts_no1053, ts_no1054, ts_extsi1226, ts_extsi1227, + ts_extsi1228); + input [31:0] WRd; + input [4:0] Rs1, Rs2, Rd; + input WrReg, reset, clk, dftIn, ts_extsi1227, ts_extsi1228, ts_intno31, + ts_extsi1226; + output [31:0] RRs1, RRs2; + output ts_no1050, ts_no1051, ts_no1053, ts_no1054; + + wire [31:0] registers_1__ap, registers_2__ap, registers_3__ap, + registers_4__ap, registers_5__ap, registers_6__ap, + registers_7__ap, registers_8__ap, registers_9__ap, + registers_10__ap, registers_11__ap, registers_12__ap, + registers_13__ap, registers_14__ap, registers_15__ap, + registers_16__ap, registers_17__ap, registers_18__ap, + registers_19__ap, registers_20__ap, registers_21__ap, + registers_22__ap, registers_23__ap, registers_24__ap, + registers_25__ap, registers_26__ap, registers_27__ap, + registers_28__ap, registers_29__ap, registers_30__ap, + registers_31__ap, registers; + wire n_0_0, n_0_32, n_0_33, n_0_34, n_0_35, n_0_36, n_0_37, n_0_38, n_0_39, + n_0_40, n_0_41, n_0_42, n_0_43, n_0_44, n_0_45, n_0_46, n_0_47, n_0_48, + n_0_49, n_0_50, n_0_51, n_0_52, n_0_53, n_0_54, n_0_55, n_0_56, n_0_57, + n_0_58, n_0_59, n_0_60, n_0_61, n_0_31, n_0_30, n_0_29, n_0_28, n_0_27, + n_0_26, n_0_25, n_0_24, n_0_0_0, n_0_0_1, n_0_23, n_0_22, n_0_21, + n_0_20, n_0_19, n_0_18, n_0_17, n_0_16, n_0_0_2, n_0_0_3, n_0_15, + n_0_14, n_0_13, n_0_12, n_0_11, n_0_10, n_0_9, n_0_8, n_0_0_4, n_0_0_5, + n_0_7, n_0_0_6, n_0_6, n_0_0_7, n_0_5, n_0_0_8, n_0_4, n_0_0_9, + n_0_0_10, n_0_3, n_0_0_11, n_0_2, n_0_0_12, n_0_1, n_0_0_13, n_0_0_14, + n_0_0_15, n_0_0_16, n_0_0_17, n_0_0_18, n_0_0_19, n_0_0_20, n_1_0_0, + n_1_0_1, n_1_0_2, n_1_0_3, n_1_0_4, n_1_0_5, n_1_0_6, n_1_0_7, n_1_0_8, + n_1_0_9, n_1_0_10, n_1_0_11, n_1_0_12, n_1_0_13, n_1_0_14, n_1_0_15, + n_1_0_16, n_1_0_17, n_1_0_18, n_1_0_19, n_1_0_20, n_1_0_21, n_1_0_22, + n_1_0_23, n_1_0_24, n_1_0_25, n_1_0_26, n_1_0_27, n_1_0_28, n_1_0_29, + n_1_0_30, n_1_0_31, n_1_0_32, n_1_0_33, n_1_0_34, n_1_0_35, n_1_0_36, + n_1_0_37, n_1_0_38, n_1_0_39, n_1_0_40, n_1_0_41, n_1_0_42, n_1_0_43, + n_1_0_44, n_1_0_45, n_1_0_46, n_1_0_47, n_1_0_48, n_1_0_49, n_1_0_50, + n_1_0_51, n_1_0_52, n_1_0_53, n_1_0_54, n_1_0_55, n_1_0_56, n_1_0_57, + n_1_0_58, n_1_0_59, n_1_0_60, n_1_0_61, n_1_0_62, n_1_0_63, n_1_0_64, + n_1_0_65, n_1_0_66, n_1_0_67, n_1_0_68, n_1_0_69, n_1_0_70, n_1_0_71, + n_1_0_72, n_1_0_73, n_1_0_74, n_1_0_75, n_1_0_76, n_1_0_77, n_1_0_78, + n_1_0_79, n_1_0_80, n_1_0_81, n_1_0_82, n_1_0_83, n_1_0_84, n_1_0_85, + n_1_0_86, n_1_0_87, n_1_0_88, n_1_0_89, n_1_0_90, n_1_0_91, n_1_0_92, + n_1_0_93, n_1_0_94, n_1_0_95, n_1_0_96, n_1_0_97, n_1_0_98, n_1_0_99, + n_1_0_100, n_1_0_101, n_1_0_102, n_1_0_103, n_1_0_104, n_1_0_105, + n_1_0_106, n_1_0_107, n_1_0_108, n_1_0_109, n_1_0_110, n_1_0_111, + n_1_0_112, n_1_0_113, n_1_0_114, n_1_0_115, n_1_0_116, n_1_0_117, + n_1_0_118, n_1_0_119, n_1_0_120, n_1_0_121, n_1_0_122, n_1_0_123, + n_1_0_124, n_1_0_125, n_1_0_126, n_1_0_127, n_1_0_128, n_1_0_129, + n_1_0_130, n_1_0_131, n_1_0_132, n_1_0_133, n_1_0_134, n_1_0_135, + n_1_0_136, n_1_0_137, n_1_0_138, n_1_0_139, n_1_0_140, n_1_0_141, + n_1_0_142, n_1_0_143, n_1_0_144, n_1_0_145, n_1_0_146, n_1_0_147, + n_1_0_148, n_1_0_149, n_1_0_150, n_1_0_151, n_1_0_152, n_1_0_153, + n_1_0_154, n_1_0_155, n_1_0_156, n_1_0_157, n_1_0_158, n_1_0_159, + n_1_0_160, n_1_0_161, n_1_0_162, n_1_0_163, n_1_0_164, n_1_0_165, + n_1_0_166, n_1_0_167, n_1_0_168, n_1_0_169, n_1_0_170, n_1_0_171, + n_1_0_172, n_1_0_173, n_1_0_174, n_1_0_175, n_1_0_176, n_1_0_177, + n_1_0_178, n_1_0_179, n_1_0_180, n_1_0_181, n_1_0_182, n_1_0_183, + n_1_0_184, n_1_0_185, n_1_0_186, n_1_0_187, n_1_0_188, n_1_0_189, + n_1_0_190, n_1_0_191, n_1_0_192, n_1_0_193, n_1_0_194, n_1_0_195, + n_1_0_196, n_1_0_197, n_1_0_198, n_1_0_199, n_1_0_200, n_1_0_201, + n_1_0_202, n_1_0_203, n_1_0_204, n_1_0_205, n_1_0_206, n_1_0_207, + n_1_0_208, n_1_0_209, n_1_0_210, n_1_0_211, n_1_0_212, n_1_0_213, + n_1_0_214, n_1_0_215, n_1_0_216, n_1_0_217, n_1_0_218, n_1_0_219, + n_1_0_220, n_1_0_221, n_1_0_222, n_1_0_223, n_1_0_224, n_1_0_225, + n_1_0_226, n_1_0_227, n_1_0_228, n_1_0_229, n_1_0_230, n_1_0_231, + n_1_0_232, n_1_0_233, n_1_0_234, n_1_0_235, n_1_0_236, n_1_0_237, + n_1_0_238, n_1_0_239, n_1_0_240, n_1_0_241, n_1_0_242, n_1_0_243, + n_1_0_244, n_1_0_245, n_1_0_246, n_1_0_247, n_1_0_248, n_1_0_249, + n_1_0_250, n_1_0_251, n_1_0_252, n_1_0_253, n_1_0_254, n_1_0_255, + n_1_0_256, n_1_0_257, n_1_0_258, n_1_0_259, n_1_0_260, n_1_0_261, + n_1_0_262, n_1_0_263, n_1_0_264, n_1_0_265, n_1_0_266, n_1_0_267, + n_1_0_268, n_1_0_269, n_1_0_270, n_1_0_271, n_1_0_272, n_1_0_273, + n_1_0_274, n_1_0_275, n_1_0_276, n_1_0_277, n_1_0_278, n_1_0_279, + n_1_0_280, n_1_0_281, n_1_0_282, n_1_0_283, n_1_0_284, n_1_0_285, + n_1_0_286, n_1_0_287, n_1_0_288, n_1_0_289, n_1_0_290, n_1_0_291, + n_1_0_292, n_1_0_293, n_1_0_294, n_1_0_295, n_1_0_296, n_1_0_297, + n_1_0_298, n_1_0_299, n_1_0_300, n_1_0_301, n_1_0_302, n_1_0_303, + n_1_0_304, n_1_0_305, n_1_0_306, n_1_0_307, n_1_0_308, n_1_0_309, + n_1_0_310, n_1_0_311, n_1_0_312, n_1_0_313, n_1_0_314, n_1_0_315, + n_1_0_316, n_1_0_317, n_1_0_318, n_1_0_319, n_1_0_320, n_1_0_321, + n_1_0_322, n_1_0_323, n_1_0_324, n_1_0_325, n_1_0_326, n_1_0_327, + n_1_0_328, n_1_0_329, n_1_0_330, n_1_0_331, n_1_0_332, n_1_0_333, + n_1_0_334, n_1_0_335, n_1_0_336, n_1_0_337, n_1_0_338, n_1_0_339, + n_1_0_340, n_1_0_341, n_1_0_342, n_1_0_343, n_1_0_344, n_1_0_345, + n_1_0_346, n_1_0_347, n_1_0_348, n_1_0_349, n_1_0_350, n_1_0_351, + n_1_0_352, n_1_0_353, n_1_0_354, n_1_0_355, n_1_0_356, n_1_0_357, + n_1_0_358, n_1_0_359, n_1_0_360, n_1_0_361, n_1_0_362, n_1_0_363, + n_1_0_364, n_1_0_365, n_1_0_366, n_1_0_367, n_1_0_368, n_1_0_369, + n_1_0_370, n_1_0_371, n_1_0_372, n_1_0_373, n_1_0_374, n_1_0_375, + n_1_0_376, n_1_0_377, n_1_0_378, n_1_0_379, n_1_0_380, n_1_0_381, + n_1_0_382, n_1_0_383, n_1_0_384, n_1_0_385, n_1_0_386, n_1_0_387, + n_1_0_388, n_1_0_389, n_1_0_390, n_1_0_391, n_1_0_392, n_1_0_393, + n_1_0_394, n_1_0_395, n_1_0_396, n_1_0_397, n_1_0_398, n_1_0_399, + n_1_0_400, n_1_0_401, n_1_0_402, n_1_0_403, n_1_0_404, n_1_0_405, + n_1_0_406, n_1_0_407, n_1_0_408, n_1_0_409, n_1_0_410, n_1_0_411, + n_1_0_412, n_1_0_413, n_1_0_414, n_1_0_415, n_1_0_416, n_1_0_417, + n_1_0_418, n_1_0_419, n_1_0_420, n_1_0_421, n_1_0_422, n_1_0_423, + n_1_0_424, n_1_0_425, n_1_0_426, n_1_0_427, n_1_0_428, n_1_0_429, + n_1_0_430, n_1_0_431, n_1_0_432, n_1_0_433, n_1_0_434, n_1_0_435, + n_1_0_436, n_1_0_437, n_1_0_438, n_1_0_439, n_1_0_440, n_1_0_441, + n_1_0_442, n_1_0_443, n_1_0_444, n_1_0_445, n_1_0_446, n_1_0_447, + n_1_0_448, n_1_0_449, n_1_0_450, n_1_0_451, n_1_0_452, n_1_0_453, + n_1_0_454, n_1_0_455, n_1_0_456, n_1_0_457, n_1_0_458, n_1_0_459, + n_1_0_460, n_1_0_461, n_1_0_462, n_1_0_463, n_1_0_464, n_1_0_465, + n_1_0_466, n_1_0_467, n_1_0_468, n_1_0_469, n_1_0_470, n_1_0_471, + n_1_0_472, n_1_0_473, n_1_0_474, n_1_0_475, n_1_0_476, n_1_0_477, + n_1_0_478, n_1_0_479, n_1_0_480, n_1_0_481, n_1_0_482, n_1_0_483, + n_1_0_484, n_1_0_485, n_1_0_486, n_1_0_487, n_1_0_488, n_1_0_489, + n_1_0_490, n_1_0_491, n_1_0_492, n_1_0_493, n_1_0_494, n_1_0_495, + n_1_0_496, n_1_0_497, n_1_0_498, n_1_0_499, n_1_0_500, n_1_0_501, + n_1_0_502, n_1_0_503, n_1_0_504, n_1_0_505, n_1_0_506, n_1_0_507, + n_1_0_508, n_1_0_509, n_1_0_510, n_1_0_511, n_1_0_512, n_1_0_513, + n_1_0_514, n_1_0_515, n_1_0_516, n_1_0_517, n_1_0_518, n_1_0_519, + n_1_0_520, n_1_0_521, n_1_0_522, n_1_0_523, n_1_0_524, n_1_0_525, + n_1_0_526, n_1_0_527, n_1_0_528, n_1_0_529, n_1_0_530, n_1_0_531, + n_1_0_532, n_1_0_533, n_1_0_534, n_1_0_535, n_1_0_536, n_1_0_537, + n_1_0_538, n_1_0_539, n_1_0_540, n_1_0_541, n_1_0_542, n_1_0_543, + n_1_0_544, n_1_0_545, n_1_0_546, n_1_0_547, n_1_0_548, n_1_0_549, + n_1_0_550, n_1_0_551, n_1_0_552, n_1_0_553, n_1_0_554, n_1_0_555, + n_1_0_556, n_1_0_557, n_1_0_558, n_1_0_559, n_1_0_560, n_1_0_561, + n_1_0_562, n_1_0_563, n_1_0_564, n_1_0_565, n_1_0_566, n_1_0_567, + n_1_0_568, n_1_0_569, n_1_0_570, n_1_0_571, n_1_0_572, n_1_0_573, + n_1_0_574, n_1_0_575, n_1_0_576, n_1_0_577, n_1_0_578, n_1_0_579, + n_1_0_580, n_1_0_581, n_1_0_582, n_1_0_583, n_1_0_584, n_1_0_585, + n_1_0_586, n_1_0_587, n_1_0_588, n_1_0_589, n_1_0_590, n_1_0_591, + n_1_0_592, n_1_0_593, n_1_0_594, n_1_0_595, n_1_0_596, n_1_0_597, + n_1_0_598, n_1_0_599, n_1_0_600, n_1_0_601, n_1_0_602, n_1_0_603, + n_1_0_604, n_1_0_605, n_1_0_606, n_1_0_607, n_1_0_608, n_1_0_609, + n_1_0_610, n_1_0_611, n_1_0_612, n_1_0_613, n_1_0_614, n_1_0_615, + n_1_0_616, n_1_0_617, n_1_0_618, n_1_0_619, n_1_0_620, n_1_0_621, + n_1_0_622, n_1_0_623, n_1_0_624, n_1_0_625, n_1_0_626, n_1_0_627, + n_1_0_628, n_1_0_629, n_1_0_630, n_1_0_631, n_1_0_632, n_1_0_633, + n_1_0_634, n_1_0_635, n_1_0_636, n_1_0_637, n_1_0_638, n_1_0_639, + n_1_0_640, n_1_0_641, n_1_0_642, n_1_0_643, n_1_0_644, n_1_0_645, + n_1_0_646, n_1_0_647, n_1_0_648, n_1_0_649, n_1_0_650, n_1_0_651, + n_1_0_652, n_1_0_653, n_1_0_654, n_1_0_655, n_1_0_656, n_1_0_657, + n_1_0_658, n_1_0_659, n_1_0_660, n_1_0_661, n_1_0_662, n_1_0_663, + n_1_0_664, n_1_0_665, n_1_0_666, n_1_0_667, n_1_0_668, n_1_0_669, + n_1_0_670, n_1_0_671, n_1_0_672, n_1_0_673, n_1_0_674, n_1_0_675, + n_1_0_676, n_1_0_677, n_1_0_678, n_1_0_679, n_1_0_680, n_1_0_681, + n_1_0_682, n_1_0_683, n_1_0_684, n_1_0_685, n_1_0_686, n_1_0_687, + n_1_0_688, n_1_0_689, n_1_0_690, n_1_0_691, n_1_0_692, n_1_0_693, + n_1_0_694, n_1_0_695, n_1_0_696, n_1_0_697, n_1_0_698, n_1_0_699, + n_1_0_700, n_1_0_701, n_1_0_702, n_1_0_703, n_1_0_704, n_1_0_705, + n_1_0_706, n_1_0_707, n_1_0_708, n_1_0_709, n_1_0_710, n_1_0_711, + n_1_0_712, n_1_0_713, n_1_0_714, n_1_0_715, n_1_0_716, n_1_0_717, + n_1_0_718, n_1_0_719, n_1_0_720, n_1_0_721, n_1_0_722, n_1_0_723, + n_1_0_724, n_1_0_725, n_1_0_726, n_1_0_727, n_1_0_728, n_1_0_729, + n_1_0_730, n_1_0_731, n_1_0_732, n_1_0_733, n_1_0_734, n_1_0_735, + n_1_0_736, n_1_0_737, n_1_0_738, n_1_0_739, n_1_0_740, n_1_0_741, + n_1_0_742, n_1_0_743, n_1_0_744, n_1_0_745, n_1_0_746, n_1_0_747, + n_1_0_748, n_1_0_749, n_1_0_750, n_1_0_751, n_1_0_752, n_1_0_753, + n_1_0_754, n_1_0_755, n_1_0_756, n_1_0_757, n_1_0_758, n_1_0_759, + n_1_0_760, n_1_0_761, n_1_0_762, n_1_0_763, n_1_0_764, n_1_0_765, + n_1_0_766, n_1_0_767, n_1_0_768, n_1_0_769, n_1_0_770, n_1_0_771, + n_1_0_772, n_1_0_773, n_1_0_774, n_1_0_775, n_1_0_776, n_1_0_777, + n_1_0_778, n_1_0_779, n_1_0_780, n_1_0_781, n_1_0_782, n_1_0_783, + n_1_0_784, n_1_0_785, n_1_0_786, n_1_0_787, n_1_0_788, n_1_0_789, + n_1_0_790, n_1_0_791, n_1_0_792, n_1_0_793, n_1_0_794, n_1_0_795, + n_1_0_796, n_1_0_797, n_1_0_798, n_1_0_799, n_1_0_800, n_1_0_801, + n_1_0_802, n_1_0_803, n_1_0_804, n_1_0_805, n_1_0_806, n_1_0_807, + n_1_0_808, n_1_0_809, n_1_0_810, n_1_0_811, n_1_0_812, n_1_0_813, + n_1_0_814, n_1_0_815, n_1_0_816, n_1_0_817, n_1_0_818, n_1_0_819, + n_1_0_820, n_1_0_821, n_1_0_822, n_1_0_823, n_1_0_824, n_1_0_825, + n_1_0_826, n_1_0_827, n_1_0_828, n_1_0_829, n_1_0_830, n_1_0_831, + n_1_0_832, n_1_0_833, n_1_0_834, n_1_0_835, n_1_0_836, n_1_0_837, + n_1_0_838, n_1_0_839, n_1_0_840, n_1_0_841, n_1_0_842, n_1_0_843, + n_1_0_844, n_1_0_845, n_1_0_846, n_1_0_847, n_1_0_848, n_1_0_849, + n_1_0_850, n_1_0_851, n_1_0_852, n_1_0_853, n_1_0_854, n_1_0_855, + n_1_0_856, n_1_0_857, n_1_0_858, n_1_0_859, n_1_0_860, n_1_0_861, + n_1_0_862, n_1_0_863, n_1_0_864, n_1_0_865, n_1_0_866, n_1_0_867, + n_1_0_868, n_1_0_869, n_1_0_870, n_1_0_871, n_1_0_872, n_1_0_873, + n_1_0_874, n_1_0_875, n_1_0_876, n_1_0_877, n_1_0_878, n_1_0_879, + n_1_0_880, n_1_0_881, n_1_0_882, n_1_0_883, n_1_0_884, n_1_0_885, + n_1_0_886, n_1_0_887, n_1_0_888, n_1_0_889, n_1_0_890, n_1_0_891, + n_1_0_892, n_1_0_893, n_1_0_894, n_1_0_895, n_1_0_896, n_1_0_897, + n_1_0_898, n_1_0_899, n_1_0_900, n_1_0_901, n_1_0_902, n_1_0_903, + n_1_0_904, n_1_0_905, n_1_0_906, n_1_0_907, n_1_0_908, n_1_0_909, + n_1_0_910, n_1_0_911, n_1_0_912, n_1_0_913, n_1_0_914, n_1_0_915, + n_1_0_916, n_1_0_917, n_1_0_918, n_1_0_919, n_1_0_920, n_1_0_921, + n_1_0_922, n_1_0_923, n_1_0_924, n_1_0_925, n_1_0_926, n_1_0_927, + n_1_0_928, n_1_0_929, n_1_0_930, n_1_0_931, n_1_0_932, n_1_0_933, + n_1_0_934, n_1_0_935, n_1_0_936, n_1_0_937, n_1_0_938, n_1_0_939, + n_1_0_940, n_1_0_941, n_1_0_942, n_1_0_943, n_1_0_944, n_1_0_945, + n_1_0_946, n_1_0_947, n_1_0_948, n_1_0_949, n_1_0_950, n_1_0_951, + n_1_0_952, n_1_0_953, n_1_0_954, n_1_0_955, n_1_0_956, n_1_0_957, + n_1_0_958, n_1_0_959, n_1_0_960, n_1_0_961, n_1_0_962, n_1_0_963, + n_1_0_964, n_1_0_965, n_1_0_966, n_1_0_967, n_1_0_968, n_1_0_969, + n_1_0_970, n_1_0_971, n_1_0_972, n_1_0_973, n_1_0_974, n_1_0_975, + n_1_0_976, n_1_0_977, n_1_0_978, n_1_0_979, n_1_0_980, n_1_0_981, + n_1_0_982, n_1_0_983, n_1_0_984, n_1_0_985, n_1_0_986, n_1_0_987, + n_1_0_988, n_1_0_989, n_1_0_990, n_1_0_991, n_1_0_992, n_1_0_993, + n_1_0_994, n_1_0_995, n_1_0_996, n_1_0_997, n_1_0_998, n_1_0_999, + n_1_0_1000, n_1_0_1001, n_1_0_1002, n_1_0_1003, n_1_0_1004, n_1_0_1005, + n_1_0_1006, n_1_0_1007, n_1_0_1008, n_1_0_1009, n_1_0_1010, n_1_0_1011, + n_1_0_1012, n_1_0_1013, n_1_0_1014, n_1_0_1015, n_1_0_1016, n_1_0_1017, + n_1_0_1018, n_1_0_1019, n_1_0_1020, n_1_0_1021, n_1_0_1022, n_1_0_1023, + n_1_0_1024, n_1_0_1025, n_1_0_1026, n_1_0_1027, n_1_0_1028, n_1_0_1029, + n_1_0_1030, n_1_0_1031, n_1_0_1032, n_1_0_1033, n_1_0_1034, n_1_0_1035, + n_1_0_1036, n_1_0_1037, n_1_0_1038, n_1_0_1039, n_1_0_1040, n_1_0_1041, + n_1_0_1042, n_1_0_1043, n_1_0_1044, n_1_0_1045, n_1_0_1046, n_1_0_1047, + n_1_0_1048, n_1_0_1049, n_1_0_1050, n_1_0_1051, n_1_0_1052, n_1_0_1053, + n_1_0_1054, n_1_0_1055, n_1_0_1056, n_1_0_1057, n_1_0_1058, n_1_0_1059, + n_1_0_1060, n_1_0_1061, n_1_0_1062, n_1_0_1063, n_1_0_1064, n_1_0_1065, + n_1_0_1066, n_1_0_1067, n_1_0_1068, n_1_0_1069, n_1_0_1070, n_1_0_1071, + n_1_0_1072, n_1_0_1073, n_1_0_1074, n_1_0_1075, n_1_0_1076, n_1_0_1077, + n_1_0_1078, n_1_0_1079, n_1_0_1080, n_1_0_1081, n_1_0_1082, n_1_0_1083, + n_1_0_1084, n_1_0_1085, n_1_0_1086, n_1_0_1087, n_1_0_1088, n_1_0_1089, + n_1_0_1090, n_1_0_1091, n_1_0_1092, n_1_0_1093, n_1_0_1094, n_1_0_1095, + n_1_0_1096, n_1_0_1097, n_1_0_1098, n_1_0_1099, n_1_0_1100, n_1_0_1101, + n_1_0_1102, n_1_0_1103, n_1_0_1104, n_1_0_1105, n_1_0_1106, n_1_0_1107, + n_1_0_1108, n_1_0_1109, n_1_0_1110, n_1_0_1111, n_1_0_1112, n_1_0_1113, + n_1_0_1114, n_1_0_1115, n_1_0_1116, n_1_0_1117, n_1_0_1118, n_1_0_1119, + n_1_0_1120, n_1_0_1121, n_1_0_1122, n_1_0_1123, n_1_0_1124, n_1_0_1125, + n_1_0_1126, n_1_0_1127, n_1_0_1128, n_1_0_1129, n_1_0_1130, n_1_0_1131, + n_1_0_1132, n_1_0_1133, n_1_0_1134, n_1_0_1135, n_1_0_1136, n_1_0_1137, + n_1_0_1138, n_1_0_1139, n_1_0_1140, n_1_0_1141, n_1_0_1142, n_1_0_1143, + n_1_0_1144, n_1_0_1145, n_1_0_1146, n_1_0_1147, n_1_0_1148, n_1_0_1149, + n_1_0_1150, n_1_0_1151, n_1_0_1152, n_1_0_1153, n_1_0_1154, n_1_0_1155, + n_1_0_1156, n_1_0_1157, n_1_0_1158, n_1_0_1159, n_1_0_1160, n_1_0_1161, + n_1_0_1162, n_1_0_1163, n_1_0_1164, n_1_0_1165, n_1_0_1166, n_1_0_1167, + n_1_0_1168, n_1_0_1169, n_1_0_1170, n_1_0_1171, n_1_0_1172, n_1_0_1173, + n_1_0_1174, n_1_0_1175, n_1_0_1176, n_1_0_1177, n_1_0_1178, n_1_0_1179, + n_1_0_1180, n_1_0_1181, n_1_0_1182, n_1_0_1183, n_1_0_1184, n_1_0_1185, + n_1_0_1186, n_1_0_1187, n_1_0_1188, n_1_0_1189, n_1_0_1190, n_1_0_1191, + n_1_0_1192, n_1_0_1193, n_1_0_1194, n_1_0_1195, n_1_0_1196, n_1_0_1197, + n_1_0_1198, n_1_0_1199, n_1_0_1200, n_1_0_1201, n_1_0_1202, n_1_0_1203, + n_1_0_1204, n_1_0_1205, n_1_0_1206, n_1_0_1207, n_1_0_1208, n_1_0_1209, + n_1_0_1210, n_1_0_1211, n_1_0_1212, n_1_0_1213, n_1_0_1214, n_1_0_1215, + n_1_0_1216, n_1_0_1217, n_1_0_1218, n_1_0_1219, n_1_0_1220, n_1_0_1221, + n_1_0_1222, n_1_0_1223, n_1_0_1224, n_1_0_1225, n_1_0_1226, n_1_0_1227, + n_1_0_1228, n_1_0_1229, n_1_0_1230, n_1_0_1231, n_1_0_1232, n_1_0_1233, + n_1_0_1234, n_1_0_1235, n_1_0_1236, n_1_0_1237, n_1_0_1238, n_1_0_1239, + n_1_0_1240, n_1_0_1241, n_1_0_1242, n_1_0_1243, n_1_0_1244, n_1_0_1245, + n_1_0_1246, n_1_0_1247, n_1_0_1248, n_1_0_1249, n_1_0_1250, n_1_0_1251, + n_1_0_1252, n_1_0_1253, n_1_0_1254, n_1_0_1255, n_1_0_1256, n_1_0_1257, + n_1_0_1258, n_1_0_1259, n_1_0_1260, n_1_0_1261, n_1_0_1262, n_1_0_1263, + n_1_0_1264, n_1_0_1265, n_1_0_1266, n_1_0_1267, n_1_0_1268, n_1_0_1269, + n_1_0_1270, n_1_0_1271, n_1_0_1272, n_1_0_1273, n_1_0_1274, n_1_0_1275, + n_1_0_1276, n_1_0_1277, n_1_0_1278, n_1_0_1279, n_1_0_1280, n_1_0_1281, + n_1_0_1282, n_1_0_1283, n_1_0_1284, n_1_0_1285, n_1_0_1286, n_1_0_1287, + n_1_0_1288, n_1_0_1289, n_1_0_1290, n_1_0_1291, n_1_0_1292, n_1_0_1293, + n_1_0_1294, n_1_0_1295, n_1_0_1296, n_1_0_1297, n_1_0_1298, n_1_0_1299, + n_1_0_1300, n_1_0_1301, n_1_0_1302, n_1_0_1303, n_1_0_1304, n_1_0_1305, + n_1_0_1306, n_1_0_1307, n_1_0_1308, n_1_0_1309, ts_pbuf_extsi1227_, + ts_pbuf_extsi1228_, ts_pbuf_extsi1226_; + + INV_X1_LVT i_0_0_79( + .A(reset), .ZN(n_0_0_16) + ); + AND2_X1_LVT i_0_0_31( + .A1(n_0_0_16), .A2(WRd[31]), .ZN(registers[31]) + ); + INV_X1_LVT i_0_0_81( + .A(Rd[1]), .ZN(n_0_0_18) + ); + INV_X1_LVT i_0_0_80( + .A(Rd[0]), .ZN(n_0_0_17) + ); + NAND3_X1_LVT i_0_0_69( + .A1(n_0_0_18), .A2(n_0_0_17), .A3(Rd[2]), .ZN(n_0_0_9) + ); + NAND3_X1_LVT i_0_0_41( + .A1(Rd[3]), .A2(WrReg), .A3(Rd[4]), .ZN(n_0_0_1) + ); + OAI21_X1_LVT i_0_0_35( + .A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_1), .ZN(n_0_28) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[28]_reg ( + .CK(clk), .E(n_0_28), .GCK(n_0_58), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[28][31] ( + .CK(n_0_58), .D(registers[31]), .Q(registers_28__ap[31]), .QN(), .SE(dftIn), + .SI(ts_pbuf_extsi1227_) + ); + INV_X1_LVT i_1_0_1370( + .A(Rs1[0]), .ZN(n_1_0_1306) + ); + NAND3_X1_LVT i_1_0_1354( + .A1(n_1_0_1306), .A2(Rs1[3]), .A3(Rs1[4]), .ZN(n_1_0_1290) + ); + INV_X1_LVT i_1_0_1373( + .A(Rs1[2]), .ZN(n_1_0_1309) + ); + OR2_X1_LVT i_1_0_1348( + .A1(n_1_0_1309), .A2(Rs1[1]), .ZN(n_1_0_1284) + ); + NOR2_X1_LVT i_1_0_1347( + .A1(n_1_0_1290), .A2(n_1_0_1284), .ZN(n_1_0_1283) + ); + NOR4_X1_LVT i_1_0_1342( + .A1(n_1_0_1284), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), .ZN(n_1_0_1278) + ); + INV_X1_LVT i_0_0_83( + .A(WrReg), .ZN(n_0_0_20) + ); + OR3_X1_LVT i_0_0_77( + .A1(n_0_0_20), .A2(Rd[4]), .A3(Rd[3]), .ZN(n_0_0_14) + ); + OAI21_X1_LVT i_0_0_68( + .A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_9), .ZN(n_0_4) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[4]_reg ( + .CK(clk), .E(n_0_4), .GCK(n_0_34), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[4][31] ( + .CK(n_0_34), .D(registers[31]), .Q(registers_4__ap[31]), .QN(), .SE(dftIn), + .SI(ts_pbuf_extsi1228_) + ); + AOI22_X1_LVT i_1_0_1320( + .A1(registers_28__ap[31]), .A2(n_1_0_1283), .B1(n_1_0_1278), .B2(registers_4__ap[31]), + .ZN(n_1_0_1256) + ); + NAND2_X1_LVT i_0_0_70( + .A1(n_0_0_18), .A2(n_0_0_17), .ZN(n_0_0_10) + ); + INV_X1_LVT i_0_0_82( + .A(Rd[4]), .ZN(n_0_0_19) + ); + OR3_X1_LVT i_0_0_51( + .A1(n_0_0_20), .A2(n_0_0_19), .A3(Rd[3]), .ZN(n_0_0_3) + ); + OR2_X1_LVT i_0_0_50( + .A1(n_0_0_3), .A2(Rd[2]), .ZN(n_0_0_2) + ); + OAI21_X1_LVT i_0_0_49( + .A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_2), .ZN(n_0_16) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[16]_reg ( + .CK(clk), .E(n_0_16), .GCK(n_0_46), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[16][31] ( + .CK(n_0_46), .D(registers[31]), .Q(registers_16__ap[31]), .QN(), .SE(dftIn), + .SI(ts_intno31) + ); + INV_X1_LVT i_1_0_1371( + .A(Rs1[3]), .ZN(n_1_0_1307) + ); + NAND3_X1_LVT i_1_0_1363( + .A1(n_1_0_1307), .A2(n_1_0_1306), .A3(Rs1[4]), .ZN(n_1_0_1299) + ); + OR2_X1_LVT i_1_0_1357( + .A1(Rs1[1]), .A2(Rs1[2]), .ZN(n_1_0_1293) + ); + NOR2_X1_LVT i_1_0_1331( + .A1(n_1_0_1299), .A2(n_1_0_1293), .ZN(n_1_0_1267) + ); + NAND2_X1_LVT i_1_0_1365( + .A1(Rs1[1]), .A2(Rs1[2]), .ZN(n_1_0_1301) + ); + NAND3_X1_LVT i_1_0_1344( + .A1(Rs1[4]), .A2(Rs1[3]), .A3(Rs1[0]), .ZN(n_1_0_1280) + ); + NOR2_X1_LVT i_1_0_1330( + .A1(n_1_0_1301), .A2(n_1_0_1280), .ZN(n_1_0_1266) + ); + NAND3_X1_LVT i_0_0_63( + .A1(Rd[2]), .A2(Rd[1]), .A3(Rd[0]), .ZN(n_0_0_6) + ); + OAI21_X1_LVT i_0_0_32( + .A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_1), .ZN(n_0_31) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[31]_reg ( + .CK(clk), .E(n_0_31), .GCK(n_0_61), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[31][31] ( + .CK(n_0_61), .D(registers[31]), .Q(registers_31__ap[31]), .QN(), .SE(dftIn), + .SI(registers_4__ap[31]) + ); + AOI22_X1_LVT i_1_0_1329( + .A1(registers_16__ap[31]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[31]), + .ZN(n_1_0_1265) + ); + NAND3_X1_LVT i_0_0_65( + .A1(n_0_0_17), .A2(Rd[1]), .A3(Rd[2]), .ZN(n_0_0_7) + ); + OAI21_X1_LVT i_0_0_64( + .A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_7), .ZN(n_0_6) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[6]_reg ( + .CK(clk), .E(n_0_6), .GCK(n_0_36), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[6][31] ( + .CK(n_0_36), .D(registers[31]), .Q(registers_6__ap[31]), .QN(), .SE(dftIn), + .SI(registers_31__ap[31]) + ); + NOR4_X1_LVT i_1_0_1364( + .A1(n_1_0_1301), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), .ZN(n_1_0_1300) + ); + INV_X1_LVT i_1_0_1372( + .A(Rs1[4]), .ZN(n_1_0_1308) + ); + NAND3_X1_LVT i_1_0_1339( + .A1(n_1_0_1308), .A2(n_1_0_1307), .A3(Rs1[0]), .ZN(n_1_0_1275) + ); + NOR2_X1_LVT i_1_0_1338( + .A1(n_1_0_1293), .A2(n_1_0_1275), .ZN(n_1_0_1274) + ); + NAND2_X1_LVT i_0_0_78( + .A1(n_0_0_18), .A2(Rd[0]), .ZN(n_0_0_15) + ); + OR2_X1_LVT i_0_0_76( + .A1(n_0_0_14), .A2(Rd[2]), .ZN(n_0_0_13) + ); + OAI21_X1_LVT i_0_0_75( + .A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_13), .ZN(n_0_1) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[1]_reg ( + .CK(clk), .E(n_0_1), .GCK(n_0_0), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[1][31] ( + .CK(n_0_0), .D(registers[31]), .Q(registers_1__ap[31]), .QN(), .SE(dftIn), + .SI(ts_pbuf_extsi1226_) + ); + AOI22_X1_LVT i_1_0_1319( + .A1(registers_6__ap[31]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[31]), + .ZN(n_1_0_1255) + ); + OAI21_X1_LVT i_0_0_42( + .A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_3), .ZN(n_0_23) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[23]_reg ( + .CK(clk), .E(n_0_23), .GCK(n_0_53), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[23][31] ( + .CK(n_0_53), .D(registers[31]), .Q(registers_23__ap[31]), .QN(), .SE(dftIn), + .SI(registers_1__ap[31]) + ); + NAND3_X1_LVT i_1_0_1360( + .A1(n_1_0_1307), .A2(Rs1[0]), .A3(Rs1[4]), .ZN(n_1_0_1296) + ); + NOR2_X1_LVT i_1_0_1328( + .A1(n_1_0_1301), .A2(n_1_0_1296), .ZN(n_1_0_1264) + ); + NOR2_X1_LVT i_1_0_1327( + .A1(n_1_0_1301), .A2(n_1_0_1275), .ZN(n_1_0_1263) + ); + OAI21_X1_LVT i_0_0_62( + .A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_6), .ZN(n_0_7) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[7]_reg ( + .CK(clk), .E(n_0_7), .GCK(n_0_37), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[7][31] ( + .CK(n_0_37), .D(registers[31]), .Q(registers_7__ap[31]), .QN(), .SE(dftIn), + .SI(registers_6__ap[31]) + ); + AOI22_X1_LVT i_1_0_1326( + .A1(registers_23__ap[31]), .A2(n_1_0_1264), .B1(n_1_0_1263), .B2(registers_7__ap[31]), + .ZN(n_1_0_1262) + ); + INV_X1_LVT i_1_0_1325( + .A(n_1_0_1262), .ZN(n_1_0_1261) + ); + NAND2_X1_LVT i_1_0_1362( + .A1(n_1_0_1309), .A2(Rs1[1]), .ZN(n_1_0_1298) + ); + NOR2_X1_LVT i_1_0_1359( + .A1(n_1_0_1298), .A2(n_1_0_1296), .ZN(n_1_0_1295) + ); + NAND2_X1_LVT i_0_0_72( + .A1(Rd[1]), .A2(Rd[0]), .ZN(n_0_0_11) + ); + OAI21_X1_LVT i_0_0_46( + .A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_2), .ZN(n_0_19) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[19]_reg ( + .CK(clk), .E(n_0_19), .GCK(n_0_49), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[19][31] ( + .CK(n_0_49), .D(registers[31]), .Q(registers_19__ap[31]), .QN(), .SE(dftIn), + .SI(registers_23__ap[31]) + ); + NAND3_X1_LVT i_0_0_67( + .A1(n_0_0_18), .A2(Rd[0]), .A3(Rd[2]), .ZN(n_0_0_8) + ); + OAI21_X1_LVT i_0_0_66( + .A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_8), .ZN(n_0_5) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[5]_reg ( + .CK(clk), .E(n_0_5), .GCK(n_0_35), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[5][31] ( + .CK(n_0_35), .D(registers[31]), .Q(registers_5__ap[31]), .QN(), .SE(dftIn), + .SI(registers_7__ap[31]) + ); + NOR2_X1_LVT i_1_0_1337( + .A1(n_1_0_1284), .A2(n_1_0_1275), .ZN(n_1_0_1273) + ); + AOI221_X1_LVT i_1_0_1318( + .A(n_1_0_1261), .B1(n_1_0_1295), .B2(registers_19__ap[31]), .C1(registers_5__ap[31]), + .C2(n_1_0_1273), .ZN(n_1_0_1254) + ); + NAND2_X1_LVT i_0_0_74( + .A1(n_0_0_17), .A2(Rd[1]), .ZN(n_0_0_12) + ); + NAND3_X1_LVT i_0_0_61( + .A1(n_0_0_19), .A2(WrReg), .A3(Rd[3]), .ZN(n_0_0_5) + ); + OR2_X1_LVT i_0_0_60( + .A1(n_0_0_5), .A2(Rd[2]), .ZN(n_0_0_4) + ); + OAI21_X1_LVT i_0_0_57( + .A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_4), .ZN(n_0_10) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[10]_reg ( + .CK(clk), .E(n_0_10), .GCK(n_0_40), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[10][31] ( + .CK(n_0_40), .D(registers[31]), .Q(registers_10__ap[31]), .QN(), .SE(dftIn), + .SI(registers_16__ap[31]) + ); + NAND3_X1_LVT i_1_0_1352( + .A1(n_1_0_1308), .A2(n_1_0_1306), .A3(Rs1[3]), .ZN(n_1_0_1288) + ); + NOR2_X1_LVT i_1_0_1351( + .A1(n_1_0_1298), .A2(n_1_0_1288), .ZN(n_1_0_1287) + ); + NOR2_X1_LVT i_1_0_1349( + .A1(n_1_0_1298), .A2(n_1_0_1290), .ZN(n_1_0_1285) + ); + OR2_X1_LVT i_0_0_40( + .A1(n_0_0_1), .A2(Rd[2]), .ZN(n_0_0_0) + ); + OAI21_X1_LVT i_0_0_37( + .A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_0), .ZN(n_0_26) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[26]_reg ( + .CK(clk), .E(n_0_26), .GCK(n_0_56), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[26][31] ( + .CK(n_0_56), .D(registers[31]), .Q(registers_26__ap[31]), .QN(), .SE(dftIn), + .SI(registers_28__ap[31]) + ); + OAI21_X1_LVT i_0_0_59( + .A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_4), .ZN(n_0_8) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[8]_reg ( + .CK(clk), .E(n_0_8), .GCK(n_0_38), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[8][31] ( + .CK(n_0_38), .D(registers[31]), .Q(registers_8__ap[31]), .QN(), .SE(dftIn), + .SI(registers_5__ap[31]) + ); + NOR2_X1_LVT i_1_0_1346( + .A1(n_1_0_1293), .A2(n_1_0_1288), .ZN(n_1_0_1282) + ); + AOI222_X1_LVT i_1_0_1317( + .A1(registers_10__ap[31]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[31]), + .C1(registers_8__ap[31]), .C2(n_1_0_1282), .ZN(n_1_0_1253) + ); + NAND4_X1_LVT i_1_0_1316( + .A1(n_1_0_1265), .A2(n_1_0_1255), .A3(n_1_0_1254), .A4(n_1_0_1253), .ZN(n_1_0_1252) + ); + NAND3_X1_LVT i_1_0_1356( + .A1(n_1_0_1308), .A2(Rs1[3]), .A3(Rs1[0]), .ZN(n_1_0_1292) + ); + NOR2_X1_LVT i_1_0_1355( + .A1(n_1_0_1293), .A2(n_1_0_1292), .ZN(n_1_0_1291) + ); + OAI21_X1_LVT i_0_0_58( + .A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_4), .ZN(n_0_9) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[9]_reg ( + .CK(clk), .E(n_0_9), .GCK(n_0_39), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[9][31] ( + .CK(n_0_39), .D(registers[31]), .Q(registers_9__ap[31]), .QN(), .SE(dftIn), + .SI(registers_8__ap[31]) + ); + OAI21_X1_LVT i_0_0_34( + .A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_1), .ZN(n_0_29) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[29]_reg ( + .CK(clk), .E(n_0_29), .GCK(n_0_59), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[29][31] ( + .CK(n_0_59), .D(registers[31]), .Q(registers_29__ap[31]), .QN(), .SE(dftIn), + .SI(registers_26__ap[31]) + ); + NOR2_X1_LVT i_1_0_1340( + .A1(n_1_0_1284), .A2(n_1_0_1280), .ZN(n_1_0_1276) + ); + AOI221_X1_LVT i_1_0_1315( + .A(n_1_0_1252), .B1(n_1_0_1291), .B2(registers_9__ap[31]), .C1(registers_29__ap[31]), + .C2(n_1_0_1276), .ZN(n_1_0_1251) + ); + OAI21_X1_LVT i_0_0_47( + .A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_2), .ZN(n_0_18) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[18]_reg ( + .CK(clk), .E(n_0_18), .GCK(n_0_48), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[18][31] ( + .CK(n_0_48), .D(registers[31]), .Q(registers_18__ap[31]), .QN(), .SE(dftIn), + .SI(registers_19__ap[31]) + ); + NOR2_X1_LVT i_1_0_1361( + .A1(n_1_0_1299), .A2(n_1_0_1298), .ZN(n_1_0_1297) + ); + NOR2_X1_LVT i_1_0_1336( + .A1(n_1_0_1301), .A2(n_1_0_1290), .ZN(n_1_0_1272) + ); + OAI21_X1_LVT i_0_0_33( + .A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_1), .ZN(n_0_30) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[30]_reg ( + .CK(clk), .E(n_0_30), .GCK(n_0_60), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[30][31] ( + .CK(n_0_60), .D(registers[31]), .Q(registers_30__ap[31]), .QN(), .SE(dftIn), + .SI(registers_29__ap[31]) + ); + AOI22_X1_LVT i_1_0_1314( + .A1(registers_18__ap[31]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[31]), + .ZN(n_1_0_1250) + ); + OAI21_X1_LVT i_0_0_39( + .A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_0), .ZN(n_0_24) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[24]_reg ( + .CK(clk), .E(n_0_24), .GCK(n_0_54), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[24][31] ( + .CK(n_0_54), .D(registers[31]), .Q(registers_24__ap[31]), .QN(), .SE(dftIn), + .SI(registers_30__ap[31]) + ); + NOR2_X1_LVT i_1_0_1353( + .A1(n_1_0_1293), .A2(n_1_0_1290), .ZN(n_1_0_1289) + ); + NOR2_X1_LVT i_1_0_1324( + .A1(n_1_0_1288), .A2(n_1_0_1284), .ZN(n_1_0_1260) + ); + OAI21_X1_LVT i_0_0_55( + .A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_5), .ZN(n_0_12) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[12]_reg ( + .CK(clk), .E(n_0_12), .GCK(n_0_42), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[12][31] ( + .CK(n_0_42), .D(registers[31]), .Q(registers_12__ap[31]), .QN(), .SE(dftIn), + .SI(registers_10__ap[31]) + ); + AOI22_X1_LVT i_1_0_1313( + .A1(registers_24__ap[31]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[31]), + .ZN(n_1_0_1249) + ); + OAI21_X1_LVT i_0_0_43( + .A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_3), .ZN(n_0_22) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[22]_reg ( + .CK(clk), .E(n_0_22), .GCK(n_0_52), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[22][31] ( + .CK(n_0_52), .D(registers[31]), .Q(registers_22__ap[31]), .QN(), .SE(dftIn), + .SI(registers_18__ap[31]) + ); + NOR2_X1_LVT i_1_0_1358( + .A1(n_1_0_1301), .A2(n_1_0_1299), .ZN(n_1_0_1294) + ); + NOR2_X1_LVT i_1_0_1323( + .A1(n_1_0_1296), .A2(n_1_0_1284), .ZN(n_1_0_1259) + ); + OAI21_X1_LVT i_0_0_44( + .A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_3), .ZN(n_0_21) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[21]_reg ( + .CK(clk), .E(n_0_21), .GCK(n_0_51), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[21][31] ( + .CK(n_0_51), .D(registers[31]), .Q(registers_21__ap[31]), .QN(), .SE(dftIn), + .SI(registers_22__ap[31]) + ); + AOI22_X1_LVT i_1_0_1312( + .A1(registers_22__ap[31]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[31]), + .ZN(n_1_0_1248) + ); + NAND3_X1_LVT i_1_0_1311( + .A1(n_1_0_1250), .A2(n_1_0_1249), .A3(n_1_0_1248), .ZN(n_1_0_1247) + ); + NOR2_X1_LVT i_1_0_1335( + .A1(n_1_0_1296), .A2(n_1_0_1293), .ZN(n_1_0_1271) + ); + OAI21_X1_LVT i_0_0_48( + .A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_2), .ZN(n_0_17) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[17]_reg ( + .CK(clk), .E(n_0_17), .GCK(n_0_47), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[17][31] ( + .CK(n_0_47), .D(registers[31]), .Q(registers_17__ap[31]), .QN(), .SE(dftIn), + .SI(registers_21__ap[31]) + ); + OAI21_X1_LVT i_0_0_45( + .A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_3), .ZN(n_0_20) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[20]_reg ( + .CK(clk), .E(n_0_20), .GCK(n_0_50), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[20][31] ( + .CK(n_0_50), .D(registers[31]), .Q(registers_20__ap[31]), .QN(), .SE(dftIn), + .SI(registers_17__ap[31]) + ); + NOR2_X1_LVT i_1_0_1345( + .A1(n_1_0_1299), .A2(n_1_0_1284), .ZN(n_1_0_1281) + ); + AOI221_X1_LVT i_1_0_1310( + .A(n_1_0_1247), .B1(n_1_0_1271), .B2(registers_17__ap[31]), .C1(registers_20__ap[31]), + .C2(n_1_0_1281), .ZN(n_1_0_1246) + ); + OAI21_X1_LVT i_0_0_36( + .A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_0), .ZN(n_0_27) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[27]_reg ( + .CK(clk), .E(n_0_27), .GCK(n_0_57), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[27][31] ( + .CK(n_0_57), .D(registers[31]), .Q(registers_27__ap[31]), .QN(), .SE(dftIn), + .SI(registers_24__ap[31]) + ); + NOR2_X1_LVT i_1_0_1343( + .A1(n_1_0_1298), .A2(n_1_0_1280), .ZN(n_1_0_1279) + ); + NOR2_X1_LVT i_1_0_1334( + .A1(n_1_0_1298), .A2(n_1_0_1292), .ZN(n_1_0_1270) + ); + OAI21_X1_LVT i_0_0_56( + .A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_4), .ZN(n_0_11) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[11]_reg ( + .CK(clk), .E(n_0_11), .GCK(n_0_41), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[11][31] ( + .CK(n_0_41), .D(registers[31]), .Q(registers_11__ap[31]), .QN(), .SE(dftIn), + .SI(registers_12__ap[31]) + ); + AOI22_X1_LVT i_1_0_1309( + .A1(registers_27__ap[31]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[31]), + .ZN(n_1_0_1245) + ); + OAI21_X1_LVT i_0_0_54( + .A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_5), .ZN(n_0_13) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[13]_reg ( + .CK(clk), .E(n_0_13), .GCK(n_0_43), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[13][31] ( + .CK(n_0_43), .D(registers[31]), .Q(registers_13__ap[31]), .QN(), .SE(dftIn), + .SI(registers_11__ap[31]) + ); + NOR2_X1_LVT i_1_0_1341( + .A1(n_1_0_1292), .A2(n_1_0_1284), .ZN(n_1_0_1277) + ); + NOR2_X1_LVT i_1_0_1333( + .A1(n_1_0_1293), .A2(n_1_0_1280), .ZN(n_1_0_1269) + ); + OAI21_X1_LVT i_0_0_38( + .A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_0), .ZN(n_0_25) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[25]_reg ( + .CK(clk), .E(n_0_25), .GCK(n_0_55), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[25][31] ( + .CK(n_0_55), .D(registers[31]), .Q(registers_25__ap[31]), .QN(), .SE(dftIn), + .SI(registers_27__ap[31]) + ); + AOI22_X1_LVT i_1_0_1308( + .A1(registers_13__ap[31]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[31]), + .ZN(n_1_0_1244) + ); + OAI21_X1_LVT i_0_0_52( + .A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_5), .ZN(n_0_15) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[15]_reg ( + .CK(clk), .E(n_0_15), .GCK(n_0_45), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[15][31] ( + .CK(n_0_45), .D(registers[31]), .Q(registers_15__ap[31]), .QN(), .SE(dftIn), + .SI(registers_13__ap[31]) + ); + NOR2_X1_LVT i_1_0_1350( + .A1(n_1_0_1301), .A2(n_1_0_1292), .ZN(n_1_0_1286) + ); + NOR2_X1_LVT i_1_0_1322( + .A1(n_1_0_1301), .A2(n_1_0_1288), .ZN(n_1_0_1258) + ); + OAI21_X1_LVT i_0_0_53( + .A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_5), .ZN(n_0_14) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[14]_reg ( + .CK(clk), .E(n_0_14), .GCK(n_0_44), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[14][31] ( + .CK(n_0_44), .D(registers[31]), .Q(registers_14__ap[31]), .QN(), .SE(dftIn), + .SI(registers_15__ap[31]) + ); + AOI22_X1_LVT i_1_0_1307( + .A1(registers_15__ap[31]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[31]), + .ZN(n_1_0_1243) + ); + NAND3_X1_LVT i_1_0_1306( + .A1(n_1_0_1245), .A2(n_1_0_1244), .A3(n_1_0_1243), .ZN(n_1_0_1242) + ); + NOR2_X1_LVT i_1_0_1321( + .A1(n_1_0_1298), .A2(n_1_0_1275), .ZN(n_1_0_1257) + ); + OAI21_X1_LVT i_0_0_71( + .A(n_0_0_16), .B1(n_0_0_13), .B2(n_0_0_11), .ZN(n_0_3) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[3]_reg ( + .CK(clk), .E(n_0_3), .GCK(n_0_33), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[3][31] ( + .CK(n_0_33), .D(registers[31]), .Q(registers_3__ap[31]), .QN(), .SE(dftIn), + .SI(registers_9__ap[31]) + ); + OAI21_X1_LVT i_0_0_73( + .A(n_0_0_16), .B1(n_0_0_13), .B2(n_0_0_12), .ZN(n_0_2) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[2]_reg ( + .CK(clk), .E(n_0_2), .GCK(n_0_32), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[2][31] ( + .CK(n_0_32), .D(registers[31]), .Q(registers_2__ap[31]), .QN(), .SE(dftIn), + .SI(registers_25__ap[31]) + ); + NOR4_X1_LVT i_1_0_1332( + .A1(n_1_0_1298), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), .ZN(n_1_0_1268) + ); + AOI221_X1_LVT i_1_0_1305( + .A(n_1_0_1242), .B1(n_1_0_1257), .B2(registers_3__ap[31]), .C1(registers_2__ap[31]), + .C2(n_1_0_1268), .ZN(n_1_0_1241) + ); + NAND4_X1_LVT i_1_0_1304( + .A1(n_1_0_1256), .A2(n_1_0_1251), .A3(n_1_0_1246), .A4(n_1_0_1241), .ZN(RRs1[31]) + ); + AND2_X1_LVT i_0_0_30( + .A1(n_0_0_16), .A2(WRd[30]), .ZN(registers[30]) + ); + SDFF_X1_LVT \registers_reg[28][30] ( + .CK(n_0_58), .D(registers[30]), .Q(registers_28__ap[30]), .QN(), .SE(dftIn), + .SI(registers_2__ap[31]) + ); + SDFF_X1_LVT \registers_reg[17][30] ( + .CK(n_0_47), .D(registers[30]), .Q(registers_17__ap[30]), .QN(), .SE(dftIn), + .SI(registers_20__ap[31]) + ); + AOI22_X1_LVT i_1_0_1300( + .A1(registers_28__ap[30]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[30]), + .ZN(n_1_0_1237) + ); + SDFF_X1_LVT \registers_reg[16][30] ( + .CK(n_0_46), .D(registers[30]), .Q(registers_16__ap[30]), .QN(), .SE(dftIn), + .SI(registers_14__ap[31]) + ); + SDFF_X1_LVT \registers_reg[31][30] ( + .CK(n_0_61), .D(registers[30]), .Q(registers_31__ap[30]), .QN(), .SE(dftIn), + .SI(registers_3__ap[31]) + ); + AOI22_X1_LVT i_1_0_1303( + .A1(registers_16__ap[30]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[30]), + .ZN(n_1_0_1240) + ); + SDFF_X1_LVT \registers_reg[6][30] ( + .CK(n_0_36), .D(registers[30]), .Q(registers_6__ap[30]), .QN(), .SE(dftIn), + .SI(registers_31__ap[30]) + ); + SDFF_X1_LVT \registers_reg[1][30] ( + .CK(n_0_0), .D(registers[30]), .Q(registers_1__ap[30]), .QN(), .SE(dftIn), + .SI(registers_17__ap[30]) + ); + AOI22_X1_LVT i_1_0_1299( + .A1(registers_6__ap[30]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[30]), + .ZN(n_1_0_1236) + ); + SDFF_X1_LVT \registers_reg[23][30] ( + .CK(n_0_53), .D(registers[30]), .Q(registers_23__ap[30]), .QN(), .SE(dftIn), + .SI(registers_1__ap[30]) + ); + SDFF_X1_LVT \registers_reg[7][30] ( + .CK(n_0_37), .D(registers[30]), .Q(registers_7__ap[30]), .QN(), .SE(dftIn), + .SI(registers_6__ap[30]) + ); + AOI22_X1_LVT i_1_0_1302( + .A1(registers_23__ap[30]), .A2(n_1_0_1264), .B1(n_1_0_1263), .B2(registers_7__ap[30]), + .ZN(n_1_0_1239) + ); + INV_X1_LVT i_1_0_1301( + .A(n_1_0_1239), .ZN(n_1_0_1238) + ); + SDFF_X1_LVT \registers_reg[19][30] ( + .CK(n_0_49), .D(registers[30]), .Q(registers_19__ap[30]), .QN(), .SE(dftIn), + .SI(registers_23__ap[30]) + ); + SDFF_X1_LVT \registers_reg[5][30] ( + .CK(n_0_35), .D(registers[30]), .Q(registers_5__ap[30]), .QN(), .SE(dftIn), + .SI(registers_7__ap[30]) + ); + AOI221_X1_LVT i_1_0_1298( + .A(n_1_0_1238), .B1(n_1_0_1295), .B2(registers_19__ap[30]), .C1(registers_5__ap[30]), + .C2(n_1_0_1273), .ZN(n_1_0_1235) + ); + SDFF_X1_LVT \registers_reg[10][30] ( + .CK(n_0_40), .D(registers[30]), .Q(registers_10__ap[30]), .QN(), .SE(dftIn), + .SI(registers_16__ap[30]) + ); + SDFF_X1_LVT \registers_reg[26][30] ( + .CK(n_0_56), .D(registers[30]), .Q(registers_26__ap[30]), .QN(), .SE(dftIn), + .SI(registers_28__ap[30]) + ); + SDFF_X1_LVT \registers_reg[8][30] ( + .CK(n_0_38), .D(registers[30]), .Q(registers_8__ap[30]), .QN(), .SE(dftIn), + .SI(registers_5__ap[30]) + ); + AOI222_X1_LVT i_1_0_1297( + .A1(registers_10__ap[30]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[30]), + .C1(registers_8__ap[30]), .C2(n_1_0_1282), .ZN(n_1_0_1234) + ); + NAND4_X1_LVT i_1_0_1296( + .A1(n_1_0_1240), .A2(n_1_0_1236), .A3(n_1_0_1235), .A4(n_1_0_1234), .ZN(n_1_0_1233) + ); + SDFF_X1_LVT \registers_reg[9][30] ( + .CK(n_0_39), .D(registers[30]), .Q(registers_9__ap[30]), .QN(), .SE(dftIn), + .SI(registers_8__ap[30]) + ); + SDFF_X1_LVT \registers_reg[29][30] ( + .CK(n_0_59), .D(registers[30]), .Q(registers_29__ap[30]), .QN(), .SE(dftIn), + .SI(registers_26__ap[30]) + ); + AOI221_X1_LVT i_1_0_1295( + .A(n_1_0_1233), .B1(n_1_0_1291), .B2(registers_9__ap[30]), .C1(registers_29__ap[30]), + .C2(n_1_0_1276), .ZN(n_1_0_1232) + ); + SDFF_X1_LVT \registers_reg[18][30] ( + .CK(n_0_48), .D(registers[30]), .Q(registers_18__ap[30]), .QN(), .SE(dftIn), + .SI(registers_19__ap[30]) + ); + SDFF_X1_LVT \registers_reg[30][30] ( + .CK(n_0_60), .D(registers[30]), .Q(registers_30__ap[30]), .QN(), .SE(dftIn), + .SI(registers_29__ap[30]) + ); + AOI22_X1_LVT i_1_0_1294( + .A1(registers_18__ap[30]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[30]), + .ZN(n_1_0_1231) + ); + SDFF_X1_LVT \registers_reg[20][30] ( + .CK(n_0_50), .D(registers[30]), .Q(registers_20__ap[30]), .QN(), .SE(dftIn), + .SI(registers_18__ap[30]) + ); + SDFF_X1_LVT \registers_reg[4][30] ( + .CK(n_0_34), .D(registers[30]), .Q(registers_4__ap[30]), .QN(), .SE(dftIn), + .SI(registers_9__ap[30]) + ); + AOI22_X1_LVT i_1_0_1293( + .A1(registers_20__ap[30]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[30]), + .ZN(n_1_0_1230) + ); + SDFF_X1_LVT \registers_reg[22][30] ( + .CK(n_0_52), .D(registers[30]), .Q(registers_22__ap[30]), .QN(), .SE(dftIn), + .SI(registers_20__ap[30]) + ); + SDFF_X1_LVT \registers_reg[21][30] ( + .CK(n_0_51), .D(registers[30]), .Q(registers_21__ap[30]), .QN(), .SE(dftIn), + .SI(registers_22__ap[30]) + ); + AOI22_X1_LVT i_1_0_1292( + .A1(registers_22__ap[30]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[30]), + .ZN(n_1_0_1229) + ); + NAND3_X1_LVT i_1_0_1291( + .A1(n_1_0_1231), .A2(n_1_0_1230), .A3(n_1_0_1229), .ZN(n_1_0_1228) + ); + SDFF_X1_LVT \registers_reg[24][30] ( + .CK(n_0_54), .D(registers[30]), .Q(registers_24__ap[30]), .QN(), .SE(dftIn), + .SI(registers_30__ap[30]) + ); + SDFF_X1_LVT \registers_reg[12][30] ( + .CK(n_0_42), .D(registers[30]), .Q(registers_12__ap[30]), .QN(), .SE(dftIn), + .SI(registers_10__ap[30]) + ); + AOI221_X1_LVT i_1_0_1290( + .A(n_1_0_1228), .B1(n_1_0_1289), .B2(registers_24__ap[30]), .C1(registers_12__ap[30]), + .C2(n_1_0_1260), .ZN(n_1_0_1227) + ); + SDFF_X1_LVT \registers_reg[27][30] ( + .CK(n_0_57), .D(registers[30]), .Q(registers_27__ap[30]), .QN(), .SE(dftIn), + .SI(registers_24__ap[30]) + ); + SDFF_X1_LVT \registers_reg[11][30] ( + .CK(n_0_41), .D(registers[30]), .Q(registers_11__ap[30]), .QN(), .SE(dftIn), + .SI(registers_12__ap[30]) + ); + AOI22_X1_LVT i_1_0_1289( + .A1(registers_27__ap[30]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[30]), + .ZN(n_1_0_1226) + ); + SDFF_X1_LVT \registers_reg[13][30] ( + .CK(n_0_43), .D(registers[30]), .Q(registers_13__ap[30]), .QN(), .SE(dftIn), + .SI(registers_11__ap[30]) + ); + SDFF_X1_LVT \registers_reg[25][30] ( + .CK(n_0_55), .D(registers[30]), .Q(registers_25__ap[30]), .QN(), .SE(dftIn), + .SI(registers_27__ap[30]) + ); + AOI22_X1_LVT i_1_0_1288( + .A1(registers_13__ap[30]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[30]), + .ZN(n_1_0_1225) + ); + SDFF_X1_LVT \registers_reg[15][30] ( + .CK(n_0_45), .D(registers[30]), .Q(registers_15__ap[30]), .QN(), .SE(dftIn), + .SI(registers_13__ap[30]) + ); + SDFF_X1_LVT \registers_reg[14][30] ( + .CK(n_0_44), .D(registers[30]), .Q(registers_14__ap[30]), .QN(), .SE(dftIn), + .SI(registers_15__ap[30]) + ); + AOI22_X1_LVT i_1_0_1287( + .A1(registers_15__ap[30]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[30]), + .ZN(n_1_0_1224) + ); + NAND3_X1_LVT i_1_0_1286( + .A1(n_1_0_1226), .A2(n_1_0_1225), .A3(n_1_0_1224), .ZN(n_1_0_1223) + ); + SDFF_X1_LVT \registers_reg[3][30] ( + .CK(n_0_33), .D(registers[30]), .Q(registers_3__ap[30]), .QN(), .SE(dftIn), + .SI(registers_4__ap[30]) + ); + SDFF_X1_LVT \registers_reg[2][30] ( + .CK(n_0_32), .D(registers[30]), .Q(registers_2__ap[30]), .QN(), .SE(dftIn), + .SI(registers_25__ap[30]) + ); + AOI221_X1_LVT i_1_0_1285( + .A(n_1_0_1223), .B1(n_1_0_1257), .B2(registers_3__ap[30]), .C1(registers_2__ap[30]), + .C2(n_1_0_1268), .ZN(n_1_0_1222) + ); + NAND4_X1_LVT i_1_0_1284( + .A1(n_1_0_1237), .A2(n_1_0_1232), .A3(n_1_0_1227), .A4(n_1_0_1222), .ZN(RRs1[30]) + ); + AND2_X1_LVT i_0_0_29( + .A1(n_0_0_16), .A2(WRd[29]), .ZN(registers[29]) + ); + SDFF_X1_LVT \registers_reg[28][29] ( + .CK(n_0_58), .D(registers[29]), .Q(registers_28__ap[29]), .QN(), .SE(dftIn), + .SI(registers_2__ap[30]) + ); + SDFF_X1_LVT \registers_reg[8][29] ( + .CK(n_0_38), .D(registers[29]), .Q(registers_8__ap[29]), .QN(), .SE(dftIn), + .SI(registers_3__ap[30]) + ); + AOI22_X1_LVT i_1_0_1282( + .A1(registers_28__ap[29]), .A2(n_1_0_1283), .B1(n_1_0_1282), .B2(registers_8__ap[29]), + .ZN(n_1_0_1220) + ); + SDFF_X1_LVT \registers_reg[31][29] ( + .CK(n_0_61), .D(registers[29]), .Q(registers_31__ap[29]), .QN(), .SE(dftIn), + .SI(registers_8__ap[29]) + ); + SDFF_X1_LVT \registers_reg[7][29] ( + .CK(n_0_37), .D(registers[29]), .Q(registers_7__ap[29]), .QN(), .SE(dftIn), + .SI(registers_31__ap[29]) + ); + AOI22_X1_LVT i_1_0_1283( + .A1(registers_31__ap[29]), .A2(n_1_0_1266), .B1(n_1_0_1263), .B2(registers_7__ap[29]), + .ZN(n_1_0_1221) + ); + SDFF_X1_LVT \registers_reg[24][29] ( + .CK(n_0_54), .D(registers[29]), .Q(registers_24__ap[29]), .QN(), .SE(dftIn), + .SI(registers_28__ap[29]) + ); + SDFF_X1_LVT \registers_reg[20][29] ( + .CK(n_0_50), .D(registers[29]), .Q(registers_20__ap[29]), .QN(), .SE(dftIn), + .SI(registers_21__ap[30]) + ); + AOI22_X1_LVT i_1_0_1281( + .A1(registers_24__ap[29]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[29]), + .ZN(n_1_0_1219) + ); + SDFF_X1_LVT \registers_reg[19][29] ( + .CK(n_0_49), .D(registers[29]), .Q(registers_19__ap[29]), .QN(), .SE(dftIn), + .SI(registers_20__ap[29]) + ); + SDFF_X1_LVT \registers_reg[4][29] ( + .CK(n_0_34), .D(registers[29]), .Q(registers_4__ap[29]), .QN(), .SE(dftIn), + .SI(registers_7__ap[29]) + ); + AOI22_X1_LVT i_1_0_1280( + .A1(registers_19__ap[29]), .A2(n_1_0_1295), .B1(n_1_0_1278), .B2(registers_4__ap[29]), + .ZN(n_1_0_1218) + ); + NAND3_X1_LVT i_1_0_1279( + .A1(n_1_0_1221), .A2(n_1_0_1219), .A3(n_1_0_1218), .ZN(n_1_0_1217) + ); + SDFF_X1_LVT \registers_reg[23][29] ( + .CK(n_0_53), .D(registers[29]), .Q(registers_23__ap[29]), .QN(), .SE(dftIn), + .SI(registers_19__ap[29]) + ); + SDFF_X1_LVT \registers_reg[29][29] ( + .CK(n_0_59), .D(registers[29]), .Q(registers_29__ap[29]), .QN(), .SE(dftIn), + .SI(registers_24__ap[29]) + ); + AOI221_X1_LVT i_1_0_1278( + .A(n_1_0_1217), .B1(n_1_0_1264), .B2(registers_23__ap[29]), .C1(registers_29__ap[29]), + .C2(n_1_0_1276), .ZN(n_1_0_1216) + ); + SDFF_X1_LVT \registers_reg[10][29] ( + .CK(n_0_40), .D(registers[29]), .Q(registers_10__ap[29]), .QN(), .SE(dftIn), + .SI(registers_14__ap[30]) + ); + SDFF_X1_LVT \registers_reg[26][29] ( + .CK(n_0_56), .D(registers[29]), .Q(registers_26__ap[29]), .QN(), .SE(dftIn), + .SI(registers_29__ap[29]) + ); + SDFF_X1_LVT \registers_reg[25][29] ( + .CK(n_0_55), .D(registers[29]), .Q(registers_25__ap[29]), .QN(), .SE(dftIn), + .SI(registers_26__ap[29]) + ); + AOI222_X1_LVT i_1_0_1277( + .A1(registers_10__ap[29]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[29]), + .C1(registers_25__ap[29]), .C2(n_1_0_1269), .ZN(n_1_0_1215) + ); + NAND3_X1_LVT i_1_0_1276( + .A1(n_1_0_1220), .A2(n_1_0_1216), .A3(n_1_0_1215), .ZN(n_1_0_1214) + ); + SDFF_X1_LVT \registers_reg[21][29] ( + .CK(n_0_51), .D(registers[29]), .Q(registers_21__ap[29]), .QN(), .SE(dftIn), + .SI(registers_23__ap[29]) + ); + SDFF_X1_LVT \registers_reg[13][29] ( + .CK(n_0_43), .D(registers[29]), .Q(registers_13__ap[29]), .QN(), .SE(dftIn), + .SI(registers_10__ap[29]) + ); + AOI221_X1_LVT i_1_0_1275( + .A(n_1_0_1214), .B1(n_1_0_1259), .B2(registers_21__ap[29]), .C1(registers_13__ap[29]), + .C2(n_1_0_1277), .ZN(n_1_0_1213) + ); + SDFF_X1_LVT \registers_reg[18][29] ( + .CK(n_0_48), .D(registers[29]), .Q(registers_18__ap[29]), .QN(), .SE(dftIn), + .SI(registers_21__ap[29]) + ); + SDFF_X1_LVT \registers_reg[30][29] ( + .CK(n_0_60), .D(registers[29]), .Q(registers_30__ap[29]), .QN(), .SE(dftIn), + .SI(registers_25__ap[29]) + ); + AOI22_X1_LVT i_1_0_1274( + .A1(registers_18__ap[29]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[29]), + .ZN(n_1_0_1212) + ); + SDFF_X1_LVT \registers_reg[17][29] ( + .CK(n_0_47), .D(registers[29]), .Q(registers_17__ap[29]), .QN(), .SE(dftIn), + .SI(registers_18__ap[29]) + ); + SDFF_X1_LVT \registers_reg[12][29] ( + .CK(n_0_42), .D(registers[29]), .Q(registers_12__ap[29]), .QN(), .SE(dftIn), + .SI(registers_13__ap[29]) + ); + AOI22_X1_LVT i_1_0_1273( + .A1(registers_17__ap[29]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[29]), + .ZN(n_1_0_1211) + ); + SDFF_X1_LVT \registers_reg[15][29] ( + .CK(n_0_45), .D(registers[29]), .Q(registers_15__ap[29]), .QN(), .SE(dftIn), + .SI(registers_12__ap[29]) + ); + SDFF_X1_LVT \registers_reg[16][29] ( + .CK(n_0_46), .D(registers[29]), .Q(registers_16__ap[29]), .QN(), .SE(dftIn), + .SI(registers_15__ap[29]) + ); + AOI22_X1_LVT i_1_0_1272( + .A1(registers_15__ap[29]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[29]), + .ZN(n_1_0_1210) + ); + NAND3_X1_LVT i_1_0_1271( + .A1(n_1_0_1212), .A2(n_1_0_1211), .A3(n_1_0_1210), .ZN(n_1_0_1209) + ); + SDFF_X1_LVT \registers_reg[22][29] ( + .CK(n_0_52), .D(registers[29]), .Q(registers_22__ap[29]), .QN(), .SE(dftIn), + .SI(registers_17__ap[29]) + ); + SDFF_X1_LVT \registers_reg[5][29] ( + .CK(n_0_35), .D(registers[29]), .Q(registers_5__ap[29]), .QN(), .SE(dftIn), + .SI(registers_4__ap[29]) + ); + AOI221_X1_LVT i_1_0_1270( + .A(n_1_0_1209), .B1(n_1_0_1294), .B2(registers_22__ap[29]), .C1(registers_5__ap[29]), + .C2(n_1_0_1273), .ZN(n_1_0_1208) + ); + SDFF_X1_LVT \registers_reg[9][29] ( + .CK(n_0_39), .D(registers[29]), .Q(registers_9__ap[29]), .QN(), .SE(dftIn), + .SI(registers_5__ap[29]) + ); + SDFF_X1_LVT \registers_reg[1][29] ( + .CK(n_0_0), .D(registers[29]), .Q(registers_1__ap[29]), .QN(), .SE(dftIn), + .SI(registers_22__ap[29]) + ); + AOI22_X1_LVT i_1_0_1269( + .A1(registers_9__ap[29]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[29]), + .ZN(n_1_0_1207) + ); + SDFF_X1_LVT \registers_reg[6][29] ( + .CK(n_0_36), .D(registers[29]), .Q(registers_6__ap[29]), .QN(), .SE(dftIn), + .SI(registers_9__ap[29]) + ); + SDFF_X1_LVT \registers_reg[14][29] ( + .CK(n_0_44), .D(registers[29]), .Q(registers_14__ap[29]), .QN(), .SE(dftIn), + .SI(registers_16__ap[29]) + ); + AOI22_X1_LVT i_1_0_1268( + .A1(registers_6__ap[29]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[29]), + .ZN(n_1_0_1206) + ); + SDFF_X1_LVT \registers_reg[27][29] ( + .CK(n_0_57), .D(registers[29]), .Q(registers_27__ap[29]), .QN(), .SE(dftIn), + .SI(registers_30__ap[29]) + ); + SDFF_X1_LVT \registers_reg[11][29] ( + .CK(n_0_41), .D(registers[29]), .Q(registers_11__ap[29]), .QN(), .SE(dftIn), + .SI(registers_14__ap[29]) + ); + AOI22_X1_LVT i_1_0_1267( + .A1(registers_27__ap[29]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[29]), + .ZN(n_1_0_1205) + ); + NAND3_X1_LVT i_1_0_1266( + .A1(n_1_0_1207), .A2(n_1_0_1206), .A3(n_1_0_1205), .ZN(n_1_0_1204) + ); + SDFF_X1_LVT \registers_reg[3][29] ( + .CK(n_0_33), .D(registers[29]), .Q(registers_3__ap[29]), .QN(), .SE(dftIn), + .SI(registers_6__ap[29]) + ); + SDFF_X1_LVT \registers_reg[2][29] ( + .CK(n_0_32), .D(registers[29]), .Q(registers_2__ap[29]), .QN(), .SE(dftIn), + .SI(registers_27__ap[29]) + ); + AOI221_X1_LVT i_1_0_1265( + .A(n_1_0_1204), .B1(n_1_0_1257), .B2(registers_3__ap[29]), .C1(registers_2__ap[29]), + .C2(n_1_0_1268), .ZN(n_1_0_1203) + ); + NAND3_X1_LVT i_1_0_1264( + .A1(n_1_0_1213), .A2(n_1_0_1208), .A3(n_1_0_1203), .ZN(RRs1[29]) + ); + AND2_X1_LVT i_0_0_28( + .A1(n_0_0_16), .A2(WRd[28]), .ZN(registers[28]) + ); + SDFF_X1_LVT \registers_reg[15][28] ( + .CK(n_0_45), .D(registers[28]), .Q(registers_15__ap[28]), .QN(), .SE(dftIn), + .SI(registers_11__ap[29]) + ); + SDFF_X1_LVT \registers_reg[26][28] ( + .CK(n_0_56), .D(registers[28]), .Q(registers_26__ap[28]), .QN(), .SE(dftIn), + .SI(registers_2__ap[29]) + ); + SDFF_X1_LVT \registers_reg[22][28] ( + .CK(n_0_52), .D(registers[28]), .Q(registers_22__ap[28]), .QN(), .SE(dftIn), + .SI(registers_1__ap[29]) + ); + AOI222_X1_LVT i_1_0_1263( + .A1(registers_15__ap[28]), .A2(n_1_0_1286), .B1(n_1_0_1285), .B2(registers_26__ap[28]), + .C1(registers_22__ap[28]), .C2(n_1_0_1294), .ZN(n_1_0_1202) + ); + SDFF_X1_LVT \registers_reg[5][28] ( + .CK(n_0_35), .D(registers[28]), .Q(registers_5__ap[28]), .QN(), .SE(dftIn), + .SI(registers_3__ap[29]) + ); + SDFF_X1_LVT \registers_reg[12][28] ( + .CK(n_0_42), .D(registers[28]), .Q(registers_12__ap[28]), .QN(), .SE(dftIn), + .SI(registers_15__ap[28]) + ); + AOI22_X1_LVT i_1_0_1262( + .A1(registers_5__ap[28]), .A2(n_1_0_1273), .B1(n_1_0_1260), .B2(registers_12__ap[28]), + .ZN(n_1_0_1201) + ); + SDFF_X1_LVT \registers_reg[28][28] ( + .CK(n_0_58), .D(registers[28]), .Q(registers_28__ap[28]), .QN(), .SE(dftIn), + .SI(registers_26__ap[28]) + ); + SDFF_X1_LVT \registers_reg[14][28] ( + .CK(n_0_44), .D(registers[28]), .Q(registers_14__ap[28]), .QN(), .SE(dftIn), + .SI(registers_12__ap[28]) + ); + AOI22_X1_LVT i_1_0_1261( + .A1(registers_28__ap[28]), .A2(n_1_0_1283), .B1(n_1_0_1258), .B2(registers_14__ap[28]), + .ZN(n_1_0_1200) + ); + SDFF_X1_LVT \registers_reg[17][28] ( + .CK(n_0_47), .D(registers[28]), .Q(registers_17__ap[28]), .QN(), .SE(dftIn), + .SI(registers_22__ap[28]) + ); + SDFF_X1_LVT \registers_reg[2][28] ( + .CK(n_0_32), .D(registers[28]), .Q(registers_2__ap[28]), .QN(), .SE(dftIn), + .SI(registers_28__ap[28]) + ); + AOI22_X1_LVT i_1_0_1260( + .A1(registers_17__ap[28]), .A2(n_1_0_1271), .B1(n_1_0_1268), .B2(registers_2__ap[28]), + .ZN(n_1_0_1199) + ); + NAND3_X1_LVT i_1_0_1259( + .A1(n_1_0_1201), .A2(n_1_0_1200), .A3(n_1_0_1199), .ZN(n_1_0_1198) + ); + SDFF_X1_LVT \registers_reg[9][28] ( + .CK(n_0_39), .D(registers[28]), .Q(registers_9__ap[28]), .QN(), .SE(dftIn), + .SI(registers_5__ap[28]) + ); + SDFF_X1_LVT \registers_reg[29][28] ( + .CK(n_0_59), .D(registers[28]), .Q(registers_29__ap[28]), .QN(), .SE(dftIn), + .SI(registers_2__ap[28]) + ); + AOI221_X1_LVT i_1_0_1258( + .A(n_1_0_1198), .B1(n_1_0_1291), .B2(registers_9__ap[28]), .C1(registers_29__ap[28]), + .C2(n_1_0_1276), .ZN(n_1_0_1197) + ); + SDFF_X1_LVT \registers_reg[13][28] ( + .CK(n_0_43), .D(registers[28]), .Q(registers_13__ap[28]), .QN(), .SE(dftIn), + .SI(registers_14__ap[28]) + ); + SDFF_X1_LVT \registers_reg[25][28] ( + .CK(n_0_55), .D(registers[28]), .Q(registers_25__ap[28]), .QN(), .SE(dftIn), + .SI(registers_29__ap[28]) + ); + AOI22_X1_LVT i_1_0_1257( + .A1(registers_13__ap[28]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[28]), + .ZN(n_1_0_1196) + ); + NAND3_X1_LVT i_1_0_1256( + .A1(n_1_0_1202), .A2(n_1_0_1197), .A3(n_1_0_1196), .ZN(n_1_0_1195) + ); + SDFF_X1_LVT \registers_reg[4][28] ( + .CK(n_0_34), .D(registers[28]), .Q(registers_4__ap[28]), .QN(), .SE(dftIn), + .SI(registers_9__ap[28]) + ); + SDFF_X1_LVT \registers_reg[20][28] ( + .CK(n_0_50), .D(registers[28]), .Q(registers_20__ap[28]), .QN(), .SE(dftIn), + .SI(registers_17__ap[28]) + ); + AOI221_X1_LVT i_1_0_1255( + .A(n_1_0_1195), .B1(n_1_0_1278), .B2(registers_4__ap[28]), .C1(registers_20__ap[28]), + .C2(n_1_0_1281), .ZN(n_1_0_1194) + ); + SDFF_X1_LVT \registers_reg[1][28] ( + .CK(n_0_0), .D(registers[28]), .Q(registers_1__ap[28]), .QN(), .SE(dftIn), + .SI(registers_20__ap[28]) + ); + SDFF_X1_LVT \registers_reg[23][28] ( + .CK(n_0_53), .D(registers[28]), .Q(registers_23__ap[28]), .QN(), .SE(dftIn), + .SI(registers_1__ap[28]) + ); + AOI22_X1_LVT i_1_0_1254( + .A1(registers_1__ap[28]), .A2(n_1_0_1274), .B1(n_1_0_1264), .B2(registers_23__ap[28]), + .ZN(n_1_0_1193) + ); + SDFF_X1_LVT \registers_reg[10][28] ( + .CK(n_0_40), .D(registers[28]), .Q(registers_10__ap[28]), .QN(), .SE(dftIn), + .SI(registers_13__ap[28]) + ); + SDFF_X1_LVT \registers_reg[21][28] ( + .CK(n_0_51), .D(registers[28]), .Q(registers_21__ap[28]), .QN(), .SE(dftIn), + .SI(registers_23__ap[28]) + ); + AOI22_X1_LVT i_1_0_1253( + .A1(registers_10__ap[28]), .A2(n_1_0_1287), .B1(n_1_0_1259), .B2(registers_21__ap[28]), + .ZN(n_1_0_1192) + ); + SDFF_X1_LVT \registers_reg[6][28] ( + .CK(n_0_36), .D(registers[28]), .Q(registers_6__ap[28]), .QN(), .SE(dftIn), + .SI(registers_4__ap[28]) + ); + SDFF_X1_LVT \registers_reg[30][28] ( + .CK(n_0_60), .D(registers[28]), .Q(registers_30__ap[28]), .QN(), .SE(dftIn), + .SI(registers_25__ap[28]) + ); + AOI22_X1_LVT i_1_0_1252( + .A1(registers_6__ap[28]), .A2(n_1_0_1300), .B1(n_1_0_1272), .B2(registers_30__ap[28]), + .ZN(n_1_0_1191) + ); + NAND3_X1_LVT i_1_0_1251( + .A1(n_1_0_1193), .A2(n_1_0_1192), .A3(n_1_0_1191), .ZN(n_1_0_1190) + ); + SDFF_X1_LVT \registers_reg[8][28] ( + .CK(n_0_38), .D(registers[28]), .Q(registers_8__ap[28]), .QN(), .SE(dftIn), + .SI(registers_6__ap[28]) + ); + SDFF_X1_LVT \registers_reg[24][28] ( + .CK(n_0_54), .D(registers[28]), .Q(registers_24__ap[28]), .QN(), .SE(dftIn), + .SI(registers_30__ap[28]) + ); + AOI221_X1_LVT i_1_0_1250( + .A(n_1_0_1190), .B1(n_1_0_1282), .B2(registers_8__ap[28]), .C1(registers_24__ap[28]), + .C2(n_1_0_1289), .ZN(n_1_0_1189) + ); + SDFF_X1_LVT \registers_reg[16][28] ( + .CK(n_0_46), .D(registers[28]), .Q(registers_16__ap[28]), .QN(), .SE(dftIn), + .SI(registers_10__ap[28]) + ); + SDFF_X1_LVT \registers_reg[3][28] ( + .CK(n_0_33), .D(registers[28]), .Q(registers_3__ap[28]), .QN(), .SE(dftIn), + .SI(registers_8__ap[28]) + ); + AOI22_X1_LVT i_1_0_1249( + .A1(registers_16__ap[28]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[28]), + .ZN(n_1_0_1188) + ); + SDFF_X1_LVT \registers_reg[11][28] ( + .CK(n_0_41), .D(registers[28]), .Q(registers_11__ap[28]), .QN(), .SE(dftIn), + .SI(registers_16__ap[28]) + ); + SDFF_X1_LVT \registers_reg[31][28] ( + .CK(n_0_61), .D(registers[28]), .Q(registers_31__ap[28]), .QN(), .SE(dftIn), + .SI(registers_3__ap[28]) + ); + AOI22_X1_LVT i_1_0_1248( + .A1(registers_11__ap[28]), .A2(n_1_0_1270), .B1(n_1_0_1266), .B2(registers_31__ap[28]), + .ZN(n_1_0_1187) + ); + SDFF_X1_LVT \registers_reg[27][28] ( + .CK(n_0_57), .D(registers[28]), .Q(registers_27__ap[28]), .QN(), .SE(dftIn), + .SI(registers_24__ap[28]) + ); + SDFF_X1_LVT \registers_reg[7][28] ( + .CK(n_0_37), .D(registers[28]), .Q(registers_7__ap[28]), .QN(), .SE(dftIn), + .SI(registers_31__ap[28]) + ); + AOI22_X1_LVT i_1_0_1247( + .A1(registers_27__ap[28]), .A2(n_1_0_1279), .B1(n_1_0_1263), .B2(registers_7__ap[28]), + .ZN(n_1_0_1186) + ); + NAND3_X1_LVT i_1_0_1246( + .A1(n_1_0_1188), .A2(n_1_0_1187), .A3(n_1_0_1186), .ZN(n_1_0_1185) + ); + SDFF_X1_LVT \registers_reg[19][28] ( + .CK(n_0_49), .D(registers[28]), .Q(registers_19__ap[28]), .QN(), .SE(dftIn), + .SI(registers_21__ap[28]) + ); + SDFF_X1_LVT \registers_reg[18][28] ( + .CK(n_0_48), .D(registers[28]), .Q(registers_18__ap[28]), .QN(), .SE(dftIn), + .SI(registers_19__ap[28]) + ); + AOI221_X1_LVT i_1_0_1245( + .A(n_1_0_1185), .B1(n_1_0_1295), .B2(registers_19__ap[28]), .C1(registers_18__ap[28]), + .C2(n_1_0_1297), .ZN(n_1_0_1184) + ); + NAND3_X1_LVT i_1_0_1244( + .A1(n_1_0_1194), .A2(n_1_0_1189), .A3(n_1_0_1184), .ZN(RRs1[28]) + ); + AND2_X1_LVT i_0_0_27( + .A1(n_0_0_16), .A2(WRd[27]), .ZN(registers[27]) + ); + SDFF_X1_LVT \registers_reg[29][27] ( + .CK(n_0_59), .D(registers[27]), .Q(registers_29__ap[27]), .QN(), .SE(dftIn), + .SI(registers_27__ap[28]) + ); + SDFF_X1_LVT \registers_reg[2][27] ( + .CK(n_0_32), .D(registers[27]), .Q(registers_2__ap[27]), .QN(), .SE(dftIn), + .SI(registers_29__ap[27]) + ); + AOI22_X1_LVT i_1_0_1242( + .A1(registers_29__ap[27]), .A2(n_1_0_1276), .B1(n_1_0_1268), .B2(registers_2__ap[27]), + .ZN(n_1_0_1182) + ); + SDFF_X1_LVT \registers_reg[8][27] ( + .CK(n_0_38), .D(registers[27]), .Q(registers_8__ap[27]), .QN(), .SE(dftIn), + .SI(registers_7__ap[28]) + ); + SDFF_X1_LVT \registers_reg[25][27] ( + .CK(n_0_55), .D(registers[27]), .Q(registers_25__ap[27]), .QN(), .SE(dftIn), + .SI(registers_2__ap[27]) + ); + AOI22_X1_LVT i_1_0_1243( + .A1(registers_8__ap[27]), .A2(n_1_0_1282), .B1(n_1_0_1269), .B2(registers_25__ap[27]), + .ZN(n_1_0_1183) + ); + SDFF_X1_LVT \registers_reg[9][27] ( + .CK(n_0_39), .D(registers[27]), .Q(registers_9__ap[27]), .QN(), .SE(dftIn), + .SI(registers_8__ap[27]) + ); + SDFF_X1_LVT \registers_reg[7][27] ( + .CK(n_0_37), .D(registers[27]), .Q(registers_7__ap[27]), .QN(), .SE(dftIn), + .SI(registers_9__ap[27]) + ); + AOI22_X1_LVT i_1_0_1241( + .A1(registers_9__ap[27]), .A2(n_1_0_1291), .B1(n_1_0_1263), .B2(registers_7__ap[27]), + .ZN(n_1_0_1181) + ); + SDFF_X1_LVT \registers_reg[11][27] ( + .CK(n_0_41), .D(registers[27]), .Q(registers_11__ap[27]), .QN(), .SE(dftIn), + .SI(registers_11__ap[28]) + ); + SDFF_X1_LVT \registers_reg[16][27] ( + .CK(n_0_46), .D(registers[27]), .Q(registers_16__ap[27]), .QN(), .SE(dftIn), + .SI(registers_11__ap[27]) + ); + AOI22_X1_LVT i_1_0_1240( + .A1(registers_11__ap[27]), .A2(n_1_0_1270), .B1(n_1_0_1267), .B2(registers_16__ap[27]), + .ZN(n_1_0_1180) + ); + NAND3_X1_LVT i_1_0_1239( + .A1(n_1_0_1183), .A2(n_1_0_1181), .A3(n_1_0_1180), .ZN(n_1_0_1179) + ); + SDFF_X1_LVT \registers_reg[10][27] ( + .CK(n_0_40), .D(registers[27]), .Q(registers_10__ap[27]), .QN(), .SE(dftIn), + .SI(registers_16__ap[27]) + ); + SDFF_X1_LVT \registers_reg[6][27] ( + .CK(n_0_36), .D(registers[27]), .Q(registers_6__ap[27]), .QN(), .SE(dftIn), + .SI(registers_7__ap[27]) + ); + AOI221_X1_LVT i_1_0_1238( + .A(n_1_0_1179), .B1(n_1_0_1287), .B2(registers_10__ap[27]), .C1(registers_6__ap[27]), + .C2(n_1_0_1300), .ZN(n_1_0_1178) + ); + SDFF_X1_LVT \registers_reg[1][27] ( + .CK(n_0_0), .D(registers[27]), .Q(registers_1__ap[27]), .QN(), .SE(dftIn), + .SI(registers_18__ap[28]) + ); + SDFF_X1_LVT \registers_reg[30][27] ( + .CK(n_0_60), .D(registers[27]), .Q(registers_30__ap[27]), .QN(), .SE(dftIn), + .SI(registers_25__ap[27]) + ); + SDFF_X1_LVT \registers_reg[22][27] ( + .CK(n_0_52), .D(registers[27]), .Q(registers_22__ap[27]), .QN(), .SE(dftIn), + .SI(registers_1__ap[27]) + ); + AOI222_X1_LVT i_1_0_1237( + .A1(registers_1__ap[27]), .A2(n_1_0_1274), .B1(n_1_0_1272), .B2(registers_30__ap[27]), + .C1(registers_22__ap[27]), .C2(n_1_0_1294), .ZN(n_1_0_1177) + ); + NAND3_X1_LVT i_1_0_1236( + .A1(n_1_0_1182), .A2(n_1_0_1178), .A3(n_1_0_1177), .ZN(n_1_0_1176) + ); + SDFF_X1_LVT \registers_reg[5][27] ( + .CK(n_0_35), .D(registers[27]), .Q(registers_5__ap[27]), .QN(), .SE(dftIn), + .SI(registers_6__ap[27]) + ); + SDFF_X1_LVT \registers_reg[28][27] ( + .CK(n_0_58), .D(registers[27]), .Q(registers_28__ap[27]), .QN(), .SE(dftIn), + .SI(registers_30__ap[27]) + ); + AOI221_X1_LVT i_1_0_1235( + .A(n_1_0_1176), .B1(n_1_0_1273), .B2(registers_5__ap[27]), .C1(registers_28__ap[27]), + .C2(n_1_0_1283), .ZN(n_1_0_1175) + ); + SDFF_X1_LVT \registers_reg[4][27] ( + .CK(n_0_34), .D(registers[27]), .Q(registers_4__ap[27]), .QN(), .SE(dftIn), + .SI(registers_5__ap[27]) + ); + SDFF_X1_LVT \registers_reg[12][27] ( + .CK(n_0_42), .D(registers[27]), .Q(registers_12__ap[27]), .QN(), .SE(dftIn), + .SI(registers_10__ap[27]) + ); + AOI22_X1_LVT i_1_0_1234( + .A1(registers_4__ap[27]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[27]), + .ZN(n_1_0_1174) + ); + SDFF_X1_LVT \registers_reg[19][27] ( + .CK(n_0_49), .D(registers[27]), .Q(registers_19__ap[27]), .QN(), .SE(dftIn), + .SI(registers_22__ap[27]) + ); + SDFF_X1_LVT \registers_reg[21][27] ( + .CK(n_0_51), .D(registers[27]), .Q(registers_21__ap[27]), .QN(), .SE(dftIn), + .SI(registers_19__ap[27]) + ); + AOI22_X1_LVT i_1_0_1233( + .A1(registers_19__ap[27]), .A2(n_1_0_1295), .B1(n_1_0_1259), .B2(registers_21__ap[27]), + .ZN(n_1_0_1173) + ); + SDFF_X1_LVT \registers_reg[24][27] ( + .CK(n_0_54), .D(registers[27]), .Q(registers_24__ap[27]), .QN(), .SE(dftIn), + .SI(registers_28__ap[27]) + ); + SDFF_X1_LVT \registers_reg[20][27] ( + .CK(n_0_50), .D(registers[27]), .Q(registers_20__ap[27]), .QN(), .SE(dftIn), + .SI(registers_21__ap[27]) + ); + AOI22_X1_LVT i_1_0_1232( + .A1(registers_24__ap[27]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[27]), + .ZN(n_1_0_1172) + ); + NAND3_X1_LVT i_1_0_1231( + .A1(n_1_0_1174), .A2(n_1_0_1173), .A3(n_1_0_1172), .ZN(n_1_0_1171) + ); + SDFF_X1_LVT \registers_reg[18][27] ( + .CK(n_0_48), .D(registers[27]), .Q(registers_18__ap[27]), .QN(), .SE(dftIn), + .SI(registers_20__ap[27]) + ); + SDFF_X1_LVT \registers_reg[26][27] ( + .CK(n_0_56), .D(registers[27]), .Q(registers_26__ap[27]), .QN(), .SE(dftIn), + .SI(registers_24__ap[27]) + ); + AOI221_X1_LVT i_1_0_1230( + .A(n_1_0_1171), .B1(n_1_0_1297), .B2(registers_18__ap[27]), .C1(registers_26__ap[27]), + .C2(n_1_0_1285), .ZN(n_1_0_1170) + ); + SDFF_X1_LVT \registers_reg[23][27] ( + .CK(n_0_53), .D(registers[27]), .Q(registers_23__ap[27]), .QN(), .SE(dftIn), + .SI(registers_18__ap[27]) + ); + SDFF_X1_LVT \registers_reg[3][27] ( + .CK(n_0_33), .D(registers[27]), .Q(registers_3__ap[27]), .QN(), .SE(dftIn), + .SI(registers_4__ap[27]) + ); + AOI22_X1_LVT i_1_0_1229( + .A1(registers_23__ap[27]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[27]), + .ZN(n_1_0_1169) + ); + SDFF_X1_LVT \registers_reg[13][27] ( + .CK(n_0_43), .D(registers[27]), .Q(registers_13__ap[27]), .QN(), .SE(dftIn), + .SI(registers_12__ap[27]) + ); + SDFF_X1_LVT \registers_reg[17][27] ( + .CK(n_0_47), .D(registers[27]), .Q(registers_17__ap[27]), .QN(), .SE(dftIn), + .SI(registers_23__ap[27]) + ); + AOI22_X1_LVT i_1_0_1228( + .A1(registers_13__ap[27]), .A2(n_1_0_1277), .B1(n_1_0_1271), .B2(registers_17__ap[27]), + .ZN(n_1_0_1168) + ); + SDFF_X1_LVT \registers_reg[15][27] ( + .CK(n_0_45), .D(registers[27]), .Q(registers_15__ap[27]), .QN(), .SE(dftIn), + .SI(registers_13__ap[27]) + ); + SDFF_X1_LVT \registers_reg[14][27] ( + .CK(n_0_44), .D(registers[27]), .Q(registers_14__ap[27]), .QN(), .SE(dftIn), + .SI(registers_15__ap[27]) + ); + AOI22_X1_LVT i_1_0_1227( + .A1(registers_15__ap[27]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[27]), + .ZN(n_1_0_1167) + ); + NAND3_X1_LVT i_1_0_1226( + .A1(n_1_0_1169), .A2(n_1_0_1168), .A3(n_1_0_1167), .ZN(n_1_0_1166) + ); + SDFF_X1_LVT \registers_reg[27][27] ( + .CK(n_0_57), .D(registers[27]), .Q(registers_27__ap[27]), .QN(), .SE(dftIn), + .SI(registers_26__ap[27]) + ); + SDFF_X1_LVT \registers_reg[31][27] ( + .CK(n_0_61), .D(registers[27]), .Q(registers_31__ap[27]), .QN(), .SE(dftIn), + .SI(registers_3__ap[27]) + ); + AOI221_X1_LVT i_1_0_1225( + .A(n_1_0_1166), .B1(n_1_0_1279), .B2(registers_27__ap[27]), .C1(registers_31__ap[27]), + .C2(n_1_0_1266), .ZN(n_1_0_1165) + ); + NAND3_X1_LVT i_1_0_1224( + .A1(n_1_0_1175), .A2(n_1_0_1170), .A3(n_1_0_1165), .ZN(RRs1[27]) + ); + AND2_X1_LVT i_0_0_26( + .A1(n_0_0_16), .A2(WRd[26]), .ZN(registers[26]) + ); + SDFF_X1_LVT \registers_reg[18][26] ( + .CK(n_0_48), .D(registers[26]), .Q(registers_18__ap[26]), .QN(), .SE(dftIn), + .SI(registers_17__ap[27]) + ); + SDFF_X1_LVT \registers_reg[22][26] ( + .CK(n_0_52), .D(registers[26]), .Q(registers_22__ap[26]), .QN(), .SE(dftIn), + .SI(registers_18__ap[26]) + ); + SDFF_X1_LVT \registers_reg[1][26] ( + .CK(n_0_0), .D(registers[26]), .Q(registers_1__ap[26]), .QN(), .SE(dftIn), + .SI(registers_22__ap[26]) + ); + AOI222_X1_LVT i_1_0_1223( + .A1(registers_18__ap[26]), .A2(n_1_0_1297), .B1(n_1_0_1294), .B2(registers_22__ap[26]), + .C1(registers_1__ap[26]), .C2(n_1_0_1274), .ZN(n_1_0_1164) + ); + SDFF_X1_LVT \registers_reg[29][26] ( + .CK(n_0_59), .D(registers[26]), .Q(registers_29__ap[26]), .QN(), .SE(dftIn), + .SI(registers_27__ap[27]) + ); + SDFF_X1_LVT \registers_reg[2][26] ( + .CK(n_0_32), .D(registers[26]), .Q(registers_2__ap[26]), .QN(), .SE(dftIn), + .SI(registers_29__ap[26]) + ); + AOI22_X1_LVT i_1_0_1222( + .A1(registers_29__ap[26]), .A2(n_1_0_1276), .B1(n_1_0_1268), .B2(registers_2__ap[26]), + .ZN(n_1_0_1163) + ); + SDFF_X1_LVT \registers_reg[9][26] ( + .CK(n_0_39), .D(registers[26]), .Q(registers_9__ap[26]), .QN(), .SE(dftIn), + .SI(registers_31__ap[27]) + ); + SDFF_X1_LVT \registers_reg[7][26] ( + .CK(n_0_37), .D(registers[26]), .Q(registers_7__ap[26]), .QN(), .SE(dftIn), + .SI(registers_9__ap[26]) + ); + AOI22_X1_LVT i_1_0_1221( + .A1(registers_9__ap[26]), .A2(n_1_0_1291), .B1(n_1_0_1263), .B2(registers_7__ap[26]), + .ZN(n_1_0_1162) + ); + SDFF_X1_LVT \registers_reg[11][26] ( + .CK(n_0_41), .D(registers[26]), .Q(registers_11__ap[26]), .QN(), .SE(dftIn), + .SI(registers_14__ap[27]) + ); + SDFF_X1_LVT \registers_reg[25][26] ( + .CK(n_0_55), .D(registers[26]), .Q(registers_25__ap[26]), .QN(), .SE(dftIn), + .SI(registers_2__ap[26]) + ); + AOI22_X1_LVT i_1_0_1220( + .A1(registers_11__ap[26]), .A2(n_1_0_1270), .B1(n_1_0_1269), .B2(registers_25__ap[26]), + .ZN(n_1_0_1161) + ); + SDFF_X1_LVT \registers_reg[27][26] ( + .CK(n_0_57), .D(registers[26]), .Q(registers_27__ap[26]), .QN(), .SE(dftIn), + .SI(registers_25__ap[26]) + ); + SDFF_X1_LVT \registers_reg[16][26] ( + .CK(n_0_46), .D(registers[26]), .Q(registers_16__ap[26]), .QN(), .SE(dftIn), + .SI(registers_11__ap[26]) + ); + AOI22_X1_LVT i_1_0_1219( + .A1(registers_27__ap[26]), .A2(n_1_0_1279), .B1(n_1_0_1267), .B2(registers_16__ap[26]), + .ZN(n_1_0_1160) + ); + NAND3_X1_LVT i_1_0_1218( + .A1(n_1_0_1162), .A2(n_1_0_1161), .A3(n_1_0_1160), .ZN(n_1_0_1159) + ); + SDFF_X1_LVT \registers_reg[31][26] ( + .CK(n_0_61), .D(registers[26]), .Q(registers_31__ap[26]), .QN(), .SE(dftIn), + .SI(registers_7__ap[26]) + ); + SDFF_X1_LVT \registers_reg[6][26] ( + .CK(n_0_36), .D(registers[26]), .Q(registers_6__ap[26]), .QN(), .SE(dftIn), + .SI(registers_31__ap[26]) + ); + AOI221_X1_LVT i_1_0_1217( + .A(n_1_0_1159), .B1(n_1_0_1266), .B2(registers_31__ap[26]), .C1(registers_6__ap[26]), + .C2(n_1_0_1300), .ZN(n_1_0_1158) + ); + NAND3_X1_LVT i_1_0_1216( + .A1(n_1_0_1164), .A2(n_1_0_1163), .A3(n_1_0_1158), .ZN(n_1_0_1157) + ); + SDFF_X1_LVT \registers_reg[5][26] ( + .CK(n_0_35), .D(registers[26]), .Q(registers_5__ap[26]), .QN(), .SE(dftIn), + .SI(registers_6__ap[26]) + ); + SDFF_X1_LVT \registers_reg[28][26] ( + .CK(n_0_58), .D(registers[26]), .Q(registers_28__ap[26]), .QN(), .SE(dftIn), + .SI(registers_27__ap[26]) + ); + AOI221_X1_LVT i_1_0_1215( + .A(n_1_0_1157), .B1(n_1_0_1273), .B2(registers_5__ap[26]), .C1(registers_28__ap[26]), + .C2(n_1_0_1283), .ZN(n_1_0_1156) + ); + SDFF_X1_LVT \registers_reg[4][26] ( + .CK(n_0_34), .D(registers[26]), .Q(registers_4__ap[26]), .QN(), .SE(dftIn), + .SI(registers_5__ap[26]) + ); + SDFF_X1_LVT \registers_reg[12][26] ( + .CK(n_0_42), .D(registers[26]), .Q(registers_12__ap[26]), .QN(), .SE(dftIn), + .SI(registers_16__ap[26]) + ); + AOI22_X1_LVT i_1_0_1214( + .A1(registers_4__ap[26]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[26]), + .ZN(n_1_0_1155) + ); + SDFF_X1_LVT \registers_reg[19][26] ( + .CK(n_0_49), .D(registers[26]), .Q(registers_19__ap[26]), .QN(), .SE(dftIn), + .SI(registers_1__ap[26]) + ); + SDFF_X1_LVT \registers_reg[21][26] ( + .CK(n_0_51), .D(registers[26]), .Q(registers_21__ap[26]), .QN(), .SE(dftIn), + .SI(registers_19__ap[26]) + ); + AOI22_X1_LVT i_1_0_1213( + .A1(registers_19__ap[26]), .A2(n_1_0_1295), .B1(n_1_0_1259), .B2(registers_21__ap[26]), + .ZN(n_1_0_1154) + ); + SDFF_X1_LVT \registers_reg[24][26] ( + .CK(n_0_54), .D(registers[26]), .Q(registers_24__ap[26]), .QN(), .SE(dftIn), + .SI(registers_28__ap[26]) + ); + SDFF_X1_LVT \registers_reg[20][26] ( + .CK(n_0_50), .D(registers[26]), .Q(registers_20__ap[26]), .QN(), .SE(dftIn), + .SI(registers_21__ap[26]) + ); + AOI22_X1_LVT i_1_0_1212( + .A1(registers_24__ap[26]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[26]), + .ZN(n_1_0_1153) + ); + NAND3_X1_LVT i_1_0_1211( + .A1(n_1_0_1155), .A2(n_1_0_1154), .A3(n_1_0_1153), .ZN(n_1_0_1152) + ); + SDFF_X1_LVT \registers_reg[26][26] ( + .CK(n_0_56), .D(registers[26]), .Q(registers_26__ap[26]), .QN(), .SE(dftIn), + .SI(registers_24__ap[26]) + ); + SDFF_X1_LVT \registers_reg[30][26] ( + .CK(n_0_60), .D(registers[26]), .Q(registers_30__ap[26]), .QN(), .SE(dftIn), + .SI(registers_26__ap[26]) + ); + AOI221_X1_LVT i_1_0_1210( + .A(n_1_0_1152), .B1(n_1_0_1285), .B2(registers_26__ap[26]), .C1(registers_30__ap[26]), + .C2(n_1_0_1272), .ZN(n_1_0_1151) + ); + SDFF_X1_LVT \registers_reg[8][26] ( + .CK(n_0_38), .D(registers[26]), .Q(registers_8__ap[26]), .QN(), .SE(dftIn), + .SI(registers_4__ap[26]) + ); + SDFF_X1_LVT \registers_reg[23][26] ( + .CK(n_0_53), .D(registers[26]), .Q(registers_23__ap[26]), .QN(), .SE(dftIn), + .SI(registers_20__ap[26]) + ); + AOI22_X1_LVT i_1_0_1209( + .A1(registers_8__ap[26]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[26]), + .ZN(n_1_0_1150) + ); + SDFF_X1_LVT \registers_reg[13][26] ( + .CK(n_0_43), .D(registers[26]), .Q(registers_13__ap[26]), .QN(), .SE(dftIn), + .SI(registers_12__ap[26]) + ); + SDFF_X1_LVT \registers_reg[17][26] ( + .CK(n_0_47), .D(registers[26]), .Q(registers_17__ap[26]), .QN(), .SE(dftIn), + .SI(registers_23__ap[26]) + ); + AOI22_X1_LVT i_1_0_1208( + .A1(registers_13__ap[26]), .A2(n_1_0_1277), .B1(n_1_0_1271), .B2(registers_17__ap[26]), + .ZN(n_1_0_1149) + ); + SDFF_X1_LVT \registers_reg[15][26] ( + .CK(n_0_45), .D(registers[26]), .Q(registers_15__ap[26]), .QN(), .SE(dftIn), + .SI(registers_13__ap[26]) + ); + SDFF_X1_LVT \registers_reg[14][26] ( + .CK(n_0_44), .D(registers[26]), .Q(registers_14__ap[26]), .QN(), .SE(dftIn), + .SI(registers_15__ap[26]) + ); + AOI22_X1_LVT i_1_0_1207( + .A1(registers_15__ap[26]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[26]), + .ZN(n_1_0_1148) + ); + NAND3_X1_LVT i_1_0_1206( + .A1(n_1_0_1150), .A2(n_1_0_1149), .A3(n_1_0_1148), .ZN(n_1_0_1147) + ); + SDFF_X1_LVT \registers_reg[10][26] ( + .CK(n_0_40), .D(registers[26]), .Q(registers_10__ap[26]), .QN(), .SE(dftIn), + .SI(registers_14__ap[26]) + ); + SDFF_X1_LVT \registers_reg[3][26] ( + .CK(n_0_33), .D(registers[26]), .Q(registers_3__ap[26]), .QN(), .SE(dftIn), + .SI(registers_8__ap[26]) + ); + AOI221_X1_LVT i_1_0_1205( + .A(n_1_0_1147), .B1(n_1_0_1287), .B2(registers_10__ap[26]), .C1(registers_3__ap[26]), + .C2(n_1_0_1257), .ZN(n_1_0_1146) + ); + NAND3_X1_LVT i_1_0_1204( + .A1(n_1_0_1156), .A2(n_1_0_1151), .A3(n_1_0_1146), .ZN(RRs1[26]) + ); + AND2_X1_LVT i_0_0_25( + .A1(n_0_0_16), .A2(WRd[25]), .ZN(registers[25]) + ); + SDFF_X1_LVT \registers_reg[17][25] ( + .CK(n_0_47), .D(registers[25]), .Q(registers_17__ap[25]), .QN(), .SE(dftIn), + .SI(registers_17__ap[26]) + ); + SDFF_X1_LVT \registers_reg[21][25] ( + .CK(n_0_51), .D(registers[25]), .Q(registers_21__ap[25]), .QN(), .SE(dftIn), + .SI(registers_17__ap[25]) + ); + AOI22_X1_LVT i_1_0_1202( + .A1(registers_17__ap[25]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[25]), + .ZN(n_1_0_1144) + ); + SDFF_X1_LVT \registers_reg[6][25] ( + .CK(n_0_36), .D(registers[25]), .Q(registers_6__ap[25]), .QN(), .SE(dftIn), + .SI(registers_3__ap[26]) + ); + SDFF_X1_LVT \registers_reg[8][25] ( + .CK(n_0_38), .D(registers[25]), .Q(registers_8__ap[25]), .QN(), .SE(dftIn), + .SI(registers_6__ap[25]) + ); + AOI22_X1_LVT i_1_0_1203( + .A1(registers_6__ap[25]), .A2(n_1_0_1300), .B1(n_1_0_1282), .B2(registers_8__ap[25]), + .ZN(n_1_0_1145) + ); + SDFF_X1_LVT \registers_reg[20][25] ( + .CK(n_0_50), .D(registers[25]), .Q(registers_20__ap[25]), .QN(), .SE(dftIn), + .SI(registers_21__ap[25]) + ); + SDFF_X1_LVT \registers_reg[12][25] ( + .CK(n_0_42), .D(registers[25]), .Q(registers_12__ap[25]), .QN(), .SE(dftIn), + .SI(registers_10__ap[26]) + ); + AOI22_X1_LVT i_1_0_1201( + .A1(registers_20__ap[25]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[25]), + .ZN(n_1_0_1143) + ); + SDFF_X1_LVT \registers_reg[5][25] ( + .CK(n_0_35), .D(registers[25]), .Q(registers_5__ap[25]), .QN(), .SE(dftIn), + .SI(registers_8__ap[25]) + ); + SDFF_X1_LVT \registers_reg[11][25] ( + .CK(n_0_41), .D(registers[25]), .Q(registers_11__ap[25]), .QN(), .SE(dftIn), + .SI(registers_12__ap[25]) + ); + AOI22_X1_LVT i_1_0_1200( + .A1(registers_5__ap[25]), .A2(n_1_0_1273), .B1(n_1_0_1270), .B2(registers_11__ap[25]), + .ZN(n_1_0_1142) + ); + NAND3_X1_LVT i_1_0_1199( + .A1(n_1_0_1145), .A2(n_1_0_1143), .A3(n_1_0_1142), .ZN(n_1_0_1141) + ); + SDFF_X1_LVT \registers_reg[10][25] ( + .CK(n_0_40), .D(registers[25]), .Q(registers_10__ap[25]), .QN(), .SE(dftIn), + .SI(registers_11__ap[25]) + ); + SDFF_X1_LVT \registers_reg[2][25] ( + .CK(n_0_32), .D(registers[25]), .Q(registers_2__ap[25]), .QN(), .SE(dftIn), + .SI(registers_30__ap[26]) + ); + AOI221_X1_LVT i_1_0_1198( + .A(n_1_0_1141), .B1(n_1_0_1287), .B2(registers_10__ap[25]), .C1(registers_2__ap[25]), + .C2(n_1_0_1268), .ZN(n_1_0_1140) + ); + SDFF_X1_LVT \registers_reg[13][25] ( + .CK(n_0_43), .D(registers[25]), .Q(registers_13__ap[25]), .QN(), .SE(dftIn), + .SI(registers_10__ap[25]) + ); + SDFF_X1_LVT \registers_reg[30][25] ( + .CK(n_0_60), .D(registers[25]), .Q(registers_30__ap[25]), .QN(), .SE(dftIn), + .SI(registers_2__ap[25]) + ); + SDFF_X1_LVT \registers_reg[22][25] ( + .CK(n_0_52), .D(registers[25]), .Q(registers_22__ap[25]), .QN(), .SE(dftIn), + .SI(registers_20__ap[25]) + ); + AOI222_X1_LVT i_1_0_1197( + .A1(registers_13__ap[25]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[25]), + .C1(registers_22__ap[25]), .C2(n_1_0_1294), .ZN(n_1_0_1139) + ); + NAND2_X1_LVT i_1_0_1196( + .A1(n_1_0_1140), .A2(n_1_0_1139), .ZN(n_1_0_1138) + ); + SDFF_X1_LVT \registers_reg[1][25] ( + .CK(n_0_0), .D(registers[25]), .Q(registers_1__ap[25]), .QN(), .SE(dftIn), + .SI(registers_22__ap[25]) + ); + SDFF_X1_LVT \registers_reg[28][25] ( + .CK(n_0_58), .D(registers[25]), .Q(registers_28__ap[25]), .QN(), .SE(dftIn), + .SI(registers_30__ap[25]) + ); + AOI221_X1_LVT i_1_0_1195( + .A(n_1_0_1138), .B1(n_1_0_1274), .B2(registers_1__ap[25]), .C1(registers_28__ap[25]), + .C2(n_1_0_1283), .ZN(n_1_0_1137) + ); + SDFF_X1_LVT \registers_reg[18][25] ( + .CK(n_0_48), .D(registers[25]), .Q(registers_18__ap[25]), .QN(), .SE(dftIn), + .SI(registers_1__ap[25]) + ); + SDFF_X1_LVT \registers_reg[26][25] ( + .CK(n_0_56), .D(registers[25]), .Q(registers_26__ap[25]), .QN(), .SE(dftIn), + .SI(registers_28__ap[25]) + ); + AOI22_X1_LVT i_1_0_1194( + .A1(registers_18__ap[25]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[25]), + .ZN(n_1_0_1136) + ); + SDFF_X1_LVT \registers_reg[24][25] ( + .CK(n_0_54), .D(registers[25]), .Q(registers_24__ap[25]), .QN(), .SE(dftIn), + .SI(registers_26__ap[25]) + ); + SDFF_X1_LVT \registers_reg[4][25] ( + .CK(n_0_34), .D(registers[25]), .Q(registers_4__ap[25]), .QN(), .SE(dftIn), + .SI(registers_5__ap[25]) + ); + AOI22_X1_LVT i_1_0_1193( + .A1(registers_24__ap[25]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[25]), + .ZN(n_1_0_1135) + ); + SDFF_X1_LVT \registers_reg[15][25] ( + .CK(n_0_45), .D(registers[25]), .Q(registers_15__ap[25]), .QN(), .SE(dftIn), + .SI(registers_13__ap[25]) + ); + SDFF_X1_LVT \registers_reg[16][25] ( + .CK(n_0_46), .D(registers[25]), .Q(registers_16__ap[25]), .QN(), .SE(dftIn), + .SI(registers_15__ap[25]) + ); + AOI22_X1_LVT i_1_0_1192( + .A1(registers_15__ap[25]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[25]), + .ZN(n_1_0_1134) + ); + NAND3_X1_LVT i_1_0_1191( + .A1(n_1_0_1136), .A2(n_1_0_1135), .A3(n_1_0_1134), .ZN(n_1_0_1133) + ); + SDFF_X1_LVT \registers_reg[19][25] ( + .CK(n_0_49), .D(registers[25]), .Q(registers_19__ap[25]), .QN(), .SE(dftIn), + .SI(registers_18__ap[25]) + ); + SDFF_X1_LVT \registers_reg[25][25] ( + .CK(n_0_55), .D(registers[25]), .Q(registers_25__ap[25]), .QN(), .SE(dftIn), + .SI(registers_24__ap[25]) + ); + AOI221_X1_LVT i_1_0_1190( + .A(n_1_0_1133), .B1(n_1_0_1295), .B2(registers_19__ap[25]), .C1(registers_25__ap[25]), + .C2(n_1_0_1269), .ZN(n_1_0_1132) + ); + SDFF_X1_LVT \registers_reg[7][25] ( + .CK(n_0_37), .D(registers[25]), .Q(registers_7__ap[25]), .QN(), .SE(dftIn), + .SI(registers_4__ap[25]) + ); + SDFF_X1_LVT \registers_reg[14][25] ( + .CK(n_0_44), .D(registers[25]), .Q(registers_14__ap[25]), .QN(), .SE(dftIn), + .SI(registers_16__ap[25]) + ); + AOI22_X1_LVT i_1_0_1189( + .A1(registers_7__ap[25]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[25]), + .ZN(n_1_0_1131) + ); + SDFF_X1_LVT \registers_reg[9][25] ( + .CK(n_0_39), .D(registers[25]), .Q(registers_9__ap[25]), .QN(), .SE(dftIn), + .SI(registers_7__ap[25]) + ); + SDFF_X1_LVT \registers_reg[29][25] ( + .CK(n_0_59), .D(registers[25]), .Q(registers_29__ap[25]), .QN(), .SE(dftIn), + .SI(registers_25__ap[25]) + ); + AOI22_X1_LVT i_1_0_1188( + .A1(registers_9__ap[25]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[25]), + .ZN(n_1_0_1130) + ); + SDFF_X1_LVT \registers_reg[23][25] ( + .CK(n_0_53), .D(registers[25]), .Q(registers_23__ap[25]), .QN(), .SE(dftIn), + .SI(registers_19__ap[25]) + ); + SDFF_X1_LVT \registers_reg[3][25] ( + .CK(n_0_33), .D(registers[25]), .Q(registers_3__ap[25]), .QN(), .SE(dftIn), + .SI(registers_9__ap[25]) + ); + AOI22_X1_LVT i_1_0_1187( + .A1(registers_23__ap[25]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[25]), + .ZN(n_1_0_1129) + ); + NAND3_X1_LVT i_1_0_1186( + .A1(n_1_0_1131), .A2(n_1_0_1130), .A3(n_1_0_1129), .ZN(n_1_0_1128) + ); + SDFF_X1_LVT \registers_reg[27][25] ( + .CK(n_0_57), .D(registers[25]), .Q(registers_27__ap[25]), .QN(), .SE(dftIn), + .SI(registers_29__ap[25]) + ); + SDFF_X1_LVT \registers_reg[31][25] ( + .CK(n_0_61), .D(registers[25]), .Q(registers_31__ap[25]), .QN(), .SE(dftIn), + .SI(registers_3__ap[25]) + ); + AOI221_X1_LVT i_1_0_1185( + .A(n_1_0_1128), .B1(n_1_0_1279), .B2(registers_27__ap[25]), .C1(registers_31__ap[25]), + .C2(n_1_0_1266), .ZN(n_1_0_1127) + ); + NAND4_X1_LVT i_1_0_1184( + .A1(n_1_0_1144), .A2(n_1_0_1137), .A3(n_1_0_1132), .A4(n_1_0_1127), .ZN(RRs1[25]) + ); + AND2_X1_LVT i_0_0_24( + .A1(n_0_0_16), .A2(WRd[24]), .ZN(registers[24]) + ); + SDFF_X1_LVT \registers_reg[17][24] ( + .CK(n_0_47), .D(registers[24]), .Q(registers_17__ap[24]), .QN(), .SE(dftIn), + .SI(registers_23__ap[25]) + ); + SDFF_X1_LVT \registers_reg[21][24] ( + .CK(n_0_51), .D(registers[24]), .Q(registers_21__ap[24]), .QN(), .SE(dftIn), + .SI(registers_17__ap[24]) + ); + AOI22_X1_LVT i_1_0_1182( + .A1(registers_17__ap[24]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[24]), + .ZN(n_1_0_1125) + ); + SDFF_X1_LVT \registers_reg[6][24] ( + .CK(n_0_36), .D(registers[24]), .Q(registers_6__ap[24]), .QN(), .SE(dftIn), + .SI(registers_31__ap[25]) + ); + SDFF_X1_LVT \registers_reg[8][24] ( + .CK(n_0_38), .D(registers[24]), .Q(registers_8__ap[24]), .QN(), .SE(dftIn), + .SI(registers_6__ap[24]) + ); + AOI22_X1_LVT i_1_0_1183( + .A1(registers_6__ap[24]), .A2(n_1_0_1300), .B1(n_1_0_1282), .B2(registers_8__ap[24]), + .ZN(n_1_0_1126) + ); + SDFF_X1_LVT \registers_reg[20][24] ( + .CK(n_0_50), .D(registers[24]), .Q(registers_20__ap[24]), .QN(), .SE(dftIn), + .SI(registers_21__ap[24]) + ); + SDFF_X1_LVT \registers_reg[12][24] ( + .CK(n_0_42), .D(registers[24]), .Q(registers_12__ap[24]), .QN(), .SE(dftIn), + .SI(registers_14__ap[25]) + ); + AOI22_X1_LVT i_1_0_1181( + .A1(registers_20__ap[24]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[24]), + .ZN(n_1_0_1124) + ); + SDFF_X1_LVT \registers_reg[5][24] ( + .CK(n_0_35), .D(registers[24]), .Q(registers_5__ap[24]), .QN(), .SE(dftIn), + .SI(registers_8__ap[24]) + ); + SDFF_X1_LVT \registers_reg[11][24] ( + .CK(n_0_41), .D(registers[24]), .Q(registers_11__ap[24]), .QN(), .SE(dftIn), + .SI(registers_12__ap[24]) + ); + AOI22_X1_LVT i_1_0_1180( + .A1(registers_5__ap[24]), .A2(n_1_0_1273), .B1(n_1_0_1270), .B2(registers_11__ap[24]), + .ZN(n_1_0_1123) + ); + NAND3_X1_LVT i_1_0_1179( + .A1(n_1_0_1126), .A2(n_1_0_1124), .A3(n_1_0_1123), .ZN(n_1_0_1122) + ); + SDFF_X1_LVT \registers_reg[10][24] ( + .CK(n_0_40), .D(registers[24]), .Q(registers_10__ap[24]), .QN(), .SE(dftIn), + .SI(registers_11__ap[24]) + ); + SDFF_X1_LVT \registers_reg[2][24] ( + .CK(n_0_32), .D(registers[24]), .Q(registers_2__ap[24]), .QN(), .SE(dftIn), + .SI(registers_27__ap[25]) + ); + AOI221_X1_LVT i_1_0_1178( + .A(n_1_0_1122), .B1(n_1_0_1287), .B2(registers_10__ap[24]), .C1(registers_2__ap[24]), + .C2(n_1_0_1268), .ZN(n_1_0_1121) + ); + SDFF_X1_LVT \registers_reg[13][24] ( + .CK(n_0_43), .D(registers[24]), .Q(registers_13__ap[24]), .QN(), .SE(dftIn), + .SI(registers_10__ap[24]) + ); + SDFF_X1_LVT \registers_reg[30][24] ( + .CK(n_0_60), .D(registers[24]), .Q(registers_30__ap[24]), .QN(), .SE(dftIn), + .SI(registers_2__ap[24]) + ); + SDFF_X1_LVT \registers_reg[22][24] ( + .CK(n_0_52), .D(registers[24]), .Q(registers_22__ap[24]), .QN(), .SE(dftIn), + .SI(registers_20__ap[24]) + ); + AOI222_X1_LVT i_1_0_1177( + .A1(registers_13__ap[24]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[24]), + .C1(registers_22__ap[24]), .C2(n_1_0_1294), .ZN(n_1_0_1120) + ); + NAND2_X1_LVT i_1_0_1176( + .A1(n_1_0_1121), .A2(n_1_0_1120), .ZN(n_1_0_1119) + ); + SDFF_X1_LVT \registers_reg[1][24] ( + .CK(n_0_0), .D(registers[24]), .Q(registers_1__ap[24]), .QN(), .SE(dftIn), + .SI(registers_22__ap[24]) + ); + SDFF_X1_LVT \registers_reg[28][24] ( + .CK(n_0_58), .D(registers[24]), .Q(registers_28__ap[24]), .QN(), .SE(dftIn), + .SI(registers_30__ap[24]) + ); + AOI221_X1_LVT i_1_0_1175( + .A(n_1_0_1119), .B1(n_1_0_1274), .B2(registers_1__ap[24]), .C1(registers_28__ap[24]), + .C2(n_1_0_1283), .ZN(n_1_0_1118) + ); + SDFF_X1_LVT \registers_reg[18][24] ( + .CK(n_0_48), .D(registers[24]), .Q(registers_18__ap[24]), .QN(), .SE(dftIn), + .SI(registers_1__ap[24]) + ); + SDFF_X1_LVT \registers_reg[26][24] ( + .CK(n_0_56), .D(registers[24]), .Q(registers_26__ap[24]), .QN(), .SE(dftIn), + .SI(registers_28__ap[24]) + ); + AOI22_X1_LVT i_1_0_1174( + .A1(registers_18__ap[24]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[24]), + .ZN(n_1_0_1117) + ); + SDFF_X1_LVT \registers_reg[24][24] ( + .CK(n_0_54), .D(registers[24]), .Q(registers_24__ap[24]), .QN(), .SE(dftIn), + .SI(registers_26__ap[24]) + ); + SDFF_X1_LVT \registers_reg[4][24] ( + .CK(n_0_34), .D(registers[24]), .Q(registers_4__ap[24]), .QN(), .SE(dftIn), + .SI(registers_5__ap[24]) + ); + AOI22_X1_LVT i_1_0_1173( + .A1(registers_24__ap[24]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[24]), + .ZN(n_1_0_1116) + ); + SDFF_X1_LVT \registers_reg[15][24] ( + .CK(n_0_45), .D(registers[24]), .Q(registers_15__ap[24]), .QN(), .SE(dftIn), + .SI(registers_13__ap[24]) + ); + SDFF_X1_LVT \registers_reg[25][24] ( + .CK(n_0_55), .D(registers[24]), .Q(registers_25__ap[24]), .QN(), .SE(dftIn), + .SI(registers_24__ap[24]) + ); + AOI22_X1_LVT i_1_0_1172( + .A1(registers_15__ap[24]), .A2(n_1_0_1286), .B1(n_1_0_1269), .B2(registers_25__ap[24]), + .ZN(n_1_0_1115) + ); + NAND3_X1_LVT i_1_0_1171( + .A1(n_1_0_1117), .A2(n_1_0_1116), .A3(n_1_0_1115), .ZN(n_1_0_1114) + ); + SDFF_X1_LVT \registers_reg[19][24] ( + .CK(n_0_49), .D(registers[24]), .Q(registers_19__ap[24]), .QN(), .SE(dftIn), + .SI(registers_18__ap[24]) + ); + SDFF_X1_LVT \registers_reg[16][24] ( + .CK(n_0_46), .D(registers[24]), .Q(registers_16__ap[24]), .QN(), .SE(dftIn), + .SI(registers_15__ap[24]) + ); + AOI221_X1_LVT i_1_0_1170( + .A(n_1_0_1114), .B1(n_1_0_1295), .B2(registers_19__ap[24]), .C1(registers_16__ap[24]), + .C2(n_1_0_1267), .ZN(n_1_0_1113) + ); + SDFF_X1_LVT \registers_reg[7][24] ( + .CK(n_0_37), .D(registers[24]), .Q(registers_7__ap[24]), .QN(), .SE(dftIn), + .SI(registers_4__ap[24]) + ); + SDFF_X1_LVT \registers_reg[14][24] ( + .CK(n_0_44), .D(registers[24]), .Q(registers_14__ap[24]), .QN(), .SE(dftIn), + .SI(registers_16__ap[24]) + ); + AOI22_X1_LVT i_1_0_1169( + .A1(registers_7__ap[24]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[24]), + .ZN(n_1_0_1112) + ); + SDFF_X1_LVT \registers_reg[9][24] ( + .CK(n_0_39), .D(registers[24]), .Q(registers_9__ap[24]), .QN(), .SE(dftIn), + .SI(registers_7__ap[24]) + ); + SDFF_X1_LVT \registers_reg[29][24] ( + .CK(n_0_59), .D(registers[24]), .Q(registers_29__ap[24]), .QN(), .SE(dftIn), + .SI(registers_25__ap[24]) + ); + AOI22_X1_LVT i_1_0_1168( + .A1(registers_9__ap[24]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[24]), + .ZN(n_1_0_1111) + ); + SDFF_X1_LVT \registers_reg[23][24] ( + .CK(n_0_53), .D(registers[24]), .Q(registers_23__ap[24]), .QN(), .SE(dftIn), + .SI(registers_19__ap[24]) + ); + SDFF_X1_LVT \registers_reg[3][24] ( + .CK(n_0_33), .D(registers[24]), .Q(registers_3__ap[24]), .QN(), .SE(dftIn), + .SI(registers_9__ap[24]) + ); + AOI22_X1_LVT i_1_0_1167( + .A1(registers_23__ap[24]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[24]), + .ZN(n_1_0_1110) + ); + NAND3_X1_LVT i_1_0_1166( + .A1(n_1_0_1112), .A2(n_1_0_1111), .A3(n_1_0_1110), .ZN(n_1_0_1109) + ); + SDFF_X1_LVT \registers_reg[27][24] ( + .CK(n_0_57), .D(registers[24]), .Q(registers_27__ap[24]), .QN(), .SE(dftIn), + .SI(registers_29__ap[24]) + ); + SDFF_X1_LVT \registers_reg[31][24] ( + .CK(n_0_61), .D(registers[24]), .Q(registers_31__ap[24]), .QN(), .SE(dftIn), + .SI(registers_3__ap[24]) + ); + AOI221_X1_LVT i_1_0_1165( + .A(n_1_0_1109), .B1(n_1_0_1279), .B2(registers_27__ap[24]), .C1(registers_31__ap[24]), + .C2(n_1_0_1266), .ZN(n_1_0_1108) + ); + NAND4_X1_LVT i_1_0_1164( + .A1(n_1_0_1125), .A2(n_1_0_1118), .A3(n_1_0_1113), .A4(n_1_0_1108), .ZN(RRs1[24]) + ); + AND2_X1_LVT i_0_0_23( + .A1(n_0_0_16), .A2(WRd[23]), .ZN(registers[23]) + ); + SDFF_X1_LVT \registers_reg[9][23] ( + .CK(n_0_39), .D(registers[23]), .Q(registers_9__ap[23]), .QN(), .SE(dftIn), + .SI(registers_31__ap[24]) + ); + SDFF_X1_LVT \registers_reg[28][23] ( + .CK(n_0_58), .D(registers[23]), .Q(registers_28__ap[23]), .QN(), .SE(dftIn), + .SI(registers_27__ap[24]) + ); + AOI22_X1_LVT i_1_0_1163( + .A1(registers_9__ap[23]), .A2(n_1_0_1291), .B1(n_1_0_1283), .B2(registers_28__ap[23]), + .ZN(n_1_0_1107) + ); + SDFF_X1_LVT \registers_reg[18][23] ( + .CK(n_0_48), .D(registers[23]), .Q(registers_18__ap[23]), .QN(), .SE(dftIn), + .SI(registers_23__ap[24]) + ); + SDFF_X1_LVT \registers_reg[22][23] ( + .CK(n_0_52), .D(registers[23]), .Q(registers_22__ap[23]), .QN(), .SE(dftIn), + .SI(registers_18__ap[23]) + ); + AOI22_X1_LVT i_1_0_1160( + .A1(registers_18__ap[23]), .A2(n_1_0_1297), .B1(n_1_0_1294), .B2(registers_22__ap[23]), + .ZN(n_1_0_1104) + ); + SDFF_X1_LVT \registers_reg[1][23] ( + .CK(n_0_0), .D(registers[23]), .Q(registers_1__ap[23]), .QN(), .SE(dftIn), + .SI(registers_22__ap[23]) + ); + SDFF_X1_LVT \registers_reg[21][23] ( + .CK(n_0_51), .D(registers[23]), .Q(registers_21__ap[23]), .QN(), .SE(dftIn), + .SI(registers_1__ap[23]) + ); + AOI22_X1_LVT i_1_0_1159( + .A1(registers_1__ap[23]), .A2(n_1_0_1274), .B1(n_1_0_1259), .B2(registers_21__ap[23]), + .ZN(n_1_0_1103) + ); + NAND3_X1_LVT i_1_0_1157( + .A1(n_1_0_1107), .A2(n_1_0_1104), .A3(n_1_0_1103), .ZN(n_1_0_1101) + ); + SDFF_X1_LVT \registers_reg[20][23] ( + .CK(n_0_50), .D(registers[23]), .Q(registers_20__ap[23]), .QN(), .SE(dftIn), + .SI(registers_21__ap[23]) + ); + SDFF_X1_LVT \registers_reg[19][23] ( + .CK(n_0_49), .D(registers[23]), .Q(registers_19__ap[23]), .QN(), .SE(dftIn), + .SI(registers_20__ap[23]) + ); + AOI221_X1_LVT i_1_0_1156( + .A(n_1_0_1101), .B1(n_1_0_1281), .B2(registers_20__ap[23]), .C1(registers_19__ap[23]), + .C2(n_1_0_1295), .ZN(n_1_0_1100) + ); + SDFF_X1_LVT \registers_reg[26][23] ( + .CK(n_0_56), .D(registers[23]), .Q(registers_26__ap[23]), .QN(), .SE(dftIn), + .SI(registers_28__ap[23]) + ); + SDFF_X1_LVT \registers_reg[23][23] ( + .CK(n_0_53), .D(registers[23]), .Q(registers_23__ap[23]), .QN(), .SE(dftIn), + .SI(registers_19__ap[23]) + ); + AOI22_X1_LVT i_1_0_1162( + .A1(registers_26__ap[23]), .A2(n_1_0_1285), .B1(n_1_0_1264), .B2(registers_23__ap[23]), + .ZN(n_1_0_1106) + ); + SDFF_X1_LVT \registers_reg[29][23] ( + .CK(n_0_59), .D(registers[23]), .Q(registers_29__ap[23]), .QN(), .SE(dftIn), + .SI(registers_26__ap[23]) + ); + SDFF_X1_LVT \registers_reg[3][23] ( + .CK(n_0_33), .D(registers[23]), .Q(registers_3__ap[23]), .QN(), .SE(dftIn), + .SI(registers_9__ap[23]) + ); + AOI22_X1_LVT i_1_0_1161( + .A1(registers_29__ap[23]), .A2(n_1_0_1276), .B1(n_1_0_1257), .B2(registers_3__ap[23]), + .ZN(n_1_0_1105) + ); + SDFF_X1_LVT \registers_reg[30][23] ( + .CK(n_0_60), .D(registers[23]), .Q(registers_30__ap[23]), .QN(), .SE(dftIn), + .SI(registers_29__ap[23]) + ); + SDFF_X1_LVT \registers_reg[31][23] ( + .CK(n_0_61), .D(registers[23]), .Q(registers_31__ap[23]), .QN(), .SE(dftIn), + .SI(registers_3__ap[23]) + ); + AOI22_X1_LVT i_1_0_1158( + .A1(registers_30__ap[23]), .A2(n_1_0_1272), .B1(n_1_0_1266), .B2(registers_31__ap[23]), + .ZN(n_1_0_1102) + ); + NAND3_X1_LVT i_1_0_1155( + .A1(n_1_0_1106), .A2(n_1_0_1105), .A3(n_1_0_1102), .ZN(n_1_0_1099) + ); + SDFF_X1_LVT \registers_reg[8][23] ( + .CK(n_0_38), .D(registers[23]), .Q(registers_8__ap[23]), .QN(), .SE(dftIn), + .SI(registers_31__ap[23]) + ); + SDFF_X1_LVT \registers_reg[17][23] ( + .CK(n_0_47), .D(registers[23]), .Q(registers_17__ap[23]), .QN(), .SE(dftIn), + .SI(registers_23__ap[23]) + ); + AOI221_X1_LVT i_1_0_1154( + .A(n_1_0_1099), .B1(n_1_0_1282), .B2(registers_8__ap[23]), .C1(registers_17__ap[23]), + .C2(n_1_0_1271), .ZN(n_1_0_1098) + ); + SDFF_X1_LVT \registers_reg[24][23] ( + .CK(n_0_54), .D(registers[23]), .Q(registers_24__ap[23]), .QN(), .SE(dftIn), + .SI(registers_30__ap[23]) + ); + SDFF_X1_LVT \registers_reg[15][23] ( + .CK(n_0_45), .D(registers[23]), .Q(registers_15__ap[23]), .QN(), .SE(dftIn), + .SI(registers_14__ap[24]) + ); + SDFF_X1_LVT \registers_reg[14][23] ( + .CK(n_0_44), .D(registers[23]), .Q(registers_14__ap[23]), .QN(), .SE(dftIn), + .SI(registers_15__ap[23]) + ); + AOI222_X1_LVT i_1_0_1153( + .A1(registers_24__ap[23]), .A2(n_1_0_1289), .B1(n_1_0_1286), .B2(registers_15__ap[23]), + .C1(n_1_0_1258), .C2(registers_14__ap[23]), .ZN(n_1_0_1097) + ); + SDFF_X1_LVT \registers_reg[16][23] ( + .CK(n_0_46), .D(registers[23]), .Q(registers_16__ap[23]), .QN(), .SE(dftIn), + .SI(registers_14__ap[23]) + ); + SDFF_X1_LVT \registers_reg[7][23] ( + .CK(n_0_37), .D(registers[23]), .Q(registers_7__ap[23]), .QN(), .SE(dftIn), + .SI(registers_8__ap[23]) + ); + AOI22_X1_LVT i_1_0_1152( + .A1(registers_16__ap[23]), .A2(n_1_0_1267), .B1(n_1_0_1263), .B2(registers_7__ap[23]), + .ZN(n_1_0_1096) + ); + SDFF_X1_LVT \registers_reg[6][23] ( + .CK(n_0_36), .D(registers[23]), .Q(registers_6__ap[23]), .QN(), .SE(dftIn), + .SI(registers_7__ap[23]) + ); + SDFF_X1_LVT \registers_reg[25][23] ( + .CK(n_0_55), .D(registers[23]), .Q(registers_25__ap[23]), .QN(), .SE(dftIn), + .SI(registers_24__ap[23]) + ); + AOI22_X1_LVT i_1_0_1151( + .A1(registers_6__ap[23]), .A2(n_1_0_1300), .B1(n_1_0_1269), .B2(registers_25__ap[23]), + .ZN(n_1_0_1095) + ); + SDFF_X1_LVT \registers_reg[27][23] ( + .CK(n_0_57), .D(registers[23]), .Q(registers_27__ap[23]), .QN(), .SE(dftIn), + .SI(registers_25__ap[23]) + ); + SDFF_X1_LVT \registers_reg[11][23] ( + .CK(n_0_41), .D(registers[23]), .Q(registers_11__ap[23]), .QN(), .SE(dftIn), + .SI(registers_16__ap[23]) + ); + AOI22_X1_LVT i_1_0_1150( + .A1(registers_27__ap[23]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[23]), + .ZN(n_1_0_1094) + ); + SDFF_X1_LVT \registers_reg[13][23] ( + .CK(n_0_43), .D(registers[23]), .Q(registers_13__ap[23]), .QN(), .SE(dftIn), + .SI(registers_11__ap[23]) + ); + SDFF_X1_LVT \registers_reg[5][23] ( + .CK(n_0_35), .D(registers[23]), .Q(registers_5__ap[23]), .QN(), .SE(dftIn), + .SI(registers_6__ap[23]) + ); + AOI22_X1_LVT i_1_0_1149( + .A1(registers_13__ap[23]), .A2(n_1_0_1277), .B1(n_1_0_1273), .B2(registers_5__ap[23]), + .ZN(n_1_0_1093) + ); + SDFF_X1_LVT \registers_reg[4][23] ( + .CK(n_0_34), .D(registers[23]), .Q(registers_4__ap[23]), .QN(), .SE(dftIn), + .SI(registers_5__ap[23]) + ); + SDFF_X1_LVT \registers_reg[12][23] ( + .CK(n_0_42), .D(registers[23]), .Q(registers_12__ap[23]), .QN(), .SE(dftIn), + .SI(registers_13__ap[23]) + ); + AOI22_X1_LVT i_1_0_1148( + .A1(registers_4__ap[23]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[23]), + .ZN(n_1_0_1092) + ); + NAND3_X1_LVT i_1_0_1147( + .A1(n_1_0_1094), .A2(n_1_0_1093), .A3(n_1_0_1092), .ZN(n_1_0_1091) + ); + SDFF_X1_LVT \registers_reg[2][23] ( + .CK(n_0_32), .D(registers[23]), .Q(registers_2__ap[23]), .QN(), .SE(dftIn), + .SI(registers_27__ap[23]) + ); + SDFF_X1_LVT \registers_reg[10][23] ( + .CK(n_0_40), .D(registers[23]), .Q(registers_10__ap[23]), .QN(), .SE(dftIn), + .SI(registers_12__ap[23]) + ); + AOI221_X1_LVT i_1_0_1146( + .A(n_1_0_1091), .B1(n_1_0_1268), .B2(registers_2__ap[23]), .C1(registers_10__ap[23]), + .C2(n_1_0_1287), .ZN(n_1_0_1090) + ); + AND4_X1_LVT i_1_0_1145( + .A1(n_1_0_1097), .A2(n_1_0_1096), .A3(n_1_0_1095), .A4(n_1_0_1090), .ZN(n_1_0_1089) + ); + NAND3_X1_LVT i_1_0_1144( + .A1(n_1_0_1100), .A2(n_1_0_1098), .A3(n_1_0_1089), .ZN(RRs1[23]) + ); + AND2_X1_LVT i_0_0_22( + .A1(n_0_0_16), .A2(WRd[22]), .ZN(registers[22]) + ); + SDFF_X1_LVT \registers_reg[17][22] ( + .CK(n_0_47), .D(registers[22]), .Q(registers_17__ap[22]), .QN(), .SE(dftIn), + .SI(registers_17__ap[23]) + ); + SDFF_X1_LVT \registers_reg[21][22] ( + .CK(n_0_51), .D(registers[22]), .Q(registers_21__ap[22]), .QN(), .SE(dftIn), + .SI(registers_17__ap[22]) + ); + AOI22_X1_LVT i_1_0_1142( + .A1(registers_17__ap[22]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[22]), + .ZN(n_1_0_1087) + ); + SDFF_X1_LVT \registers_reg[6][22] ( + .CK(n_0_36), .D(registers[22]), .Q(registers_6__ap[22]), .QN(), .SE(dftIn), + .SI(registers_4__ap[23]) + ); + SDFF_X1_LVT \registers_reg[11][22] ( + .CK(n_0_41), .D(registers[22]), .Q(registers_11__ap[22]), .QN(), .SE(dftIn), + .SI(registers_10__ap[23]) + ); + AOI22_X1_LVT i_1_0_1143( + .A1(registers_6__ap[22]), .A2(n_1_0_1300), .B1(n_1_0_1270), .B2(registers_11__ap[22]), + .ZN(n_1_0_1088) + ); + SDFF_X1_LVT \registers_reg[20][22] ( + .CK(n_0_50), .D(registers[22]), .Q(registers_20__ap[22]), .QN(), .SE(dftIn), + .SI(registers_21__ap[22]) + ); + SDFF_X1_LVT \registers_reg[12][22] ( + .CK(n_0_42), .D(registers[22]), .Q(registers_12__ap[22]), .QN(), .SE(dftIn), + .SI(registers_11__ap[22]) + ); + AOI22_X1_LVT i_1_0_1141( + .A1(registers_20__ap[22]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[22]), + .ZN(n_1_0_1086) + ); + SDFF_X1_LVT \registers_reg[10][22] ( + .CK(n_0_40), .D(registers[22]), .Q(registers_10__ap[22]), .QN(), .SE(dftIn), + .SI(registers_12__ap[22]) + ); + SDFF_X1_LVT \registers_reg[5][22] ( + .CK(n_0_35), .D(registers[22]), .Q(registers_5__ap[22]), .QN(), .SE(dftIn), + .SI(registers_6__ap[22]) + ); + AOI22_X1_LVT i_1_0_1140( + .A1(registers_10__ap[22]), .A2(n_1_0_1287), .B1(n_1_0_1273), .B2(registers_5__ap[22]), + .ZN(n_1_0_1085) + ); + NAND3_X1_LVT i_1_0_1139( + .A1(n_1_0_1088), .A2(n_1_0_1086), .A3(n_1_0_1085), .ZN(n_1_0_1084) + ); + SDFF_X1_LVT \registers_reg[31][22] ( + .CK(n_0_61), .D(registers[22]), .Q(registers_31__ap[22]), .QN(), .SE(dftIn), + .SI(registers_5__ap[22]) + ); + SDFF_X1_LVT \registers_reg[2][22] ( + .CK(n_0_32), .D(registers[22]), .Q(registers_2__ap[22]), .QN(), .SE(dftIn), + .SI(registers_2__ap[23]) + ); + AOI221_X1_LVT i_1_0_1138( + .A(n_1_0_1084), .B1(n_1_0_1266), .B2(registers_31__ap[22]), .C1(registers_2__ap[22]), + .C2(n_1_0_1268), .ZN(n_1_0_1083) + ); + SDFF_X1_LVT \registers_reg[22][22] ( + .CK(n_0_52), .D(registers[22]), .Q(registers_22__ap[22]), .QN(), .SE(dftIn), + .SI(registers_20__ap[22]) + ); + SDFF_X1_LVT \registers_reg[26][22] ( + .CK(n_0_56), .D(registers[22]), .Q(registers_26__ap[22]), .QN(), .SE(dftIn), + .SI(registers_2__ap[22]) + ); + SDFF_X1_LVT \registers_reg[13][22] ( + .CK(n_0_43), .D(registers[22]), .Q(registers_13__ap[22]), .QN(), .SE(dftIn), + .SI(registers_10__ap[22]) + ); + AOI222_X1_LVT i_1_0_1137( + .A1(registers_22__ap[22]), .A2(n_1_0_1294), .B1(n_1_0_1285), .B2(registers_26__ap[22]), + .C1(n_1_0_1277), .C2(registers_13__ap[22]), .ZN(n_1_0_1082) + ); + NAND2_X1_LVT i_1_0_1136( + .A1(n_1_0_1083), .A2(n_1_0_1082), .ZN(n_1_0_1081) + ); + SDFF_X1_LVT \registers_reg[1][22] ( + .CK(n_0_0), .D(registers[22]), .Q(registers_1__ap[22]), .QN(), .SE(dftIn), + .SI(registers_22__ap[22]) + ); + SDFF_X1_LVT \registers_reg[28][22] ( + .CK(n_0_58), .D(registers[22]), .Q(registers_28__ap[22]), .QN(), .SE(dftIn), + .SI(registers_26__ap[22]) + ); + AOI221_X1_LVT i_1_0_1135( + .A(n_1_0_1081), .B1(n_1_0_1274), .B2(registers_1__ap[22]), .C1(registers_28__ap[22]), + .C2(n_1_0_1283), .ZN(n_1_0_1080) + ); + SDFF_X1_LVT \registers_reg[18][22] ( + .CK(n_0_48), .D(registers[22]), .Q(registers_18__ap[22]), .QN(), .SE(dftIn), + .SI(registers_1__ap[22]) + ); + SDFF_X1_LVT \registers_reg[30][22] ( + .CK(n_0_60), .D(registers[22]), .Q(registers_30__ap[22]), .QN(), .SE(dftIn), + .SI(registers_28__ap[22]) + ); + AOI22_X1_LVT i_1_0_1134( + .A1(registers_18__ap[22]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[22]), + .ZN(n_1_0_1079) + ); + SDFF_X1_LVT \registers_reg[24][22] ( + .CK(n_0_54), .D(registers[22]), .Q(registers_24__ap[22]), .QN(), .SE(dftIn), + .SI(registers_30__ap[22]) + ); + SDFF_X1_LVT \registers_reg[4][22] ( + .CK(n_0_34), .D(registers[22]), .Q(registers_4__ap[22]), .QN(), .SE(dftIn), + .SI(registers_31__ap[22]) + ); + AOI22_X1_LVT i_1_0_1133( + .A1(registers_24__ap[22]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[22]), + .ZN(n_1_0_1078) + ); + SDFF_X1_LVT \registers_reg[15][22] ( + .CK(n_0_45), .D(registers[22]), .Q(registers_15__ap[22]), .QN(), .SE(dftIn), + .SI(registers_13__ap[22]) + ); + SDFF_X1_LVT \registers_reg[16][22] ( + .CK(n_0_46), .D(registers[22]), .Q(registers_16__ap[22]), .QN(), .SE(dftIn), + .SI(registers_15__ap[22]) + ); + AOI22_X1_LVT i_1_0_1132( + .A1(registers_15__ap[22]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[22]), + .ZN(n_1_0_1077) + ); + NAND3_X1_LVT i_1_0_1131( + .A1(n_1_0_1079), .A2(n_1_0_1078), .A3(n_1_0_1077), .ZN(n_1_0_1076) + ); + SDFF_X1_LVT \registers_reg[19][22] ( + .CK(n_0_49), .D(registers[22]), .Q(registers_19__ap[22]), .QN(), .SE(dftIn), + .SI(registers_18__ap[22]) + ); + SDFF_X1_LVT \registers_reg[25][22] ( + .CK(n_0_55), .D(registers[22]), .Q(registers_25__ap[22]), .QN(), .SE(dftIn), + .SI(registers_24__ap[22]) + ); + AOI221_X1_LVT i_1_0_1130( + .A(n_1_0_1076), .B1(n_1_0_1295), .B2(registers_19__ap[22]), .C1(registers_25__ap[22]), + .C2(n_1_0_1269), .ZN(n_1_0_1075) + ); + SDFF_X1_LVT \registers_reg[7][22] ( + .CK(n_0_37), .D(registers[22]), .Q(registers_7__ap[22]), .QN(), .SE(dftIn), + .SI(registers_4__ap[22]) + ); + SDFF_X1_LVT \registers_reg[14][22] ( + .CK(n_0_44), .D(registers[22]), .Q(registers_14__ap[22]), .QN(), .SE(dftIn), + .SI(registers_16__ap[22]) + ); + AOI22_X1_LVT i_1_0_1129( + .A1(registers_7__ap[22]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[22]), + .ZN(n_1_0_1074) + ); + SDFF_X1_LVT \registers_reg[9][22] ( + .CK(n_0_39), .D(registers[22]), .Q(registers_9__ap[22]), .QN(), .SE(dftIn), + .SI(registers_7__ap[22]) + ); + SDFF_X1_LVT \registers_reg[29][22] ( + .CK(n_0_59), .D(registers[22]), .Q(registers_29__ap[22]), .QN(), .SE(dftIn), + .SI(registers_25__ap[22]) + ); + AOI22_X1_LVT i_1_0_1128( + .A1(registers_9__ap[22]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[22]), + .ZN(n_1_0_1073) + ); + SDFF_X1_LVT \registers_reg[8][22] ( + .CK(n_0_38), .D(registers[22]), .Q(registers_8__ap[22]), .QN(), .SE(dftIn), + .SI(registers_9__ap[22]) + ); + SDFF_X1_LVT \registers_reg[23][22] ( + .CK(n_0_53), .D(registers[22]), .Q(registers_23__ap[22]), .QN(), .SE(dftIn), + .SI(registers_19__ap[22]) + ); + AOI22_X1_LVT i_1_0_1127( + .A1(registers_8__ap[22]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[22]), + .ZN(n_1_0_1072) + ); + NAND3_X1_LVT i_1_0_1126( + .A1(n_1_0_1074), .A2(n_1_0_1073), .A3(n_1_0_1072), .ZN(n_1_0_1071) + ); + SDFF_X1_LVT \registers_reg[27][22] ( + .CK(n_0_57), .D(registers[22]), .Q(registers_27__ap[22]), .QN(), .SE(dftIn), + .SI(registers_29__ap[22]) + ); + SDFF_X1_LVT \registers_reg[3][22] ( + .CK(n_0_33), .D(registers[22]), .Q(registers_3__ap[22]), .QN(), .SE(dftIn), + .SI(registers_8__ap[22]) + ); + AOI221_X1_LVT i_1_0_1125( + .A(n_1_0_1071), .B1(n_1_0_1279), .B2(registers_27__ap[22]), .C1(registers_3__ap[22]), + .C2(n_1_0_1257), .ZN(n_1_0_1070) + ); + NAND4_X1_LVT i_1_0_1124( + .A1(n_1_0_1087), .A2(n_1_0_1080), .A3(n_1_0_1075), .A4(n_1_0_1070), .ZN(RRs1[22]) + ); + AND2_X1_LVT i_0_0_21( + .A1(n_0_0_16), .A2(WRd[21]), .ZN(registers[21]) + ); + SDFF_X1_LVT \registers_reg[17][21] ( + .CK(n_0_47), .D(registers[21]), .Q(registers_17__ap[21]), .QN(), .SE(dftIn), + .SI(registers_23__ap[22]) + ); + SDFF_X1_LVT \registers_reg[21][21] ( + .CK(n_0_51), .D(registers[21]), .Q(registers_21__ap[21]), .QN(), .SE(dftIn), + .SI(registers_17__ap[21]) + ); + AOI22_X1_LVT i_1_0_1122( + .A1(registers_17__ap[21]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[21]), + .ZN(n_1_0_1068) + ); + SDFF_X1_LVT \registers_reg[6][21] ( + .CK(n_0_36), .D(registers[21]), .Q(registers_6__ap[21]), .QN(), .SE(dftIn), + .SI(registers_3__ap[22]) + ); + SDFF_X1_LVT \registers_reg[8][21] ( + .CK(n_0_38), .D(registers[21]), .Q(registers_8__ap[21]), .QN(), .SE(dftIn), + .SI(registers_6__ap[21]) + ); + AOI22_X1_LVT i_1_0_1123( + .A1(registers_6__ap[21]), .A2(n_1_0_1300), .B1(n_1_0_1282), .B2(registers_8__ap[21]), + .ZN(n_1_0_1069) + ); + SDFF_X1_LVT \registers_reg[20][21] ( + .CK(n_0_50), .D(registers[21]), .Q(registers_20__ap[21]), .QN(), .SE(dftIn), + .SI(registers_21__ap[21]) + ); + SDFF_X1_LVT \registers_reg[12][21] ( + .CK(n_0_42), .D(registers[21]), .Q(registers_12__ap[21]), .QN(), .SE(dftIn), + .SI(registers_14__ap[22]) + ); + AOI22_X1_LVT i_1_0_1121( + .A1(registers_20__ap[21]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[21]), + .ZN(n_1_0_1067) + ); + SDFF_X1_LVT \registers_reg[5][21] ( + .CK(n_0_35), .D(registers[21]), .Q(registers_5__ap[21]), .QN(), .SE(dftIn), + .SI(registers_8__ap[21]) + ); + SDFF_X1_LVT \registers_reg[11][21] ( + .CK(n_0_41), .D(registers[21]), .Q(registers_11__ap[21]), .QN(), .SE(dftIn), + .SI(registers_12__ap[21]) + ); + AOI22_X1_LVT i_1_0_1120( + .A1(registers_5__ap[21]), .A2(n_1_0_1273), .B1(n_1_0_1270), .B2(registers_11__ap[21]), + .ZN(n_1_0_1066) + ); + NAND3_X1_LVT i_1_0_1119( + .A1(n_1_0_1069), .A2(n_1_0_1067), .A3(n_1_0_1066), .ZN(n_1_0_1065) + ); + SDFF_X1_LVT \registers_reg[10][21] ( + .CK(n_0_40), .D(registers[21]), .Q(registers_10__ap[21]), .QN(), .SE(dftIn), + .SI(registers_11__ap[21]) + ); + SDFF_X1_LVT \registers_reg[2][21] ( + .CK(n_0_32), .D(registers[21]), .Q(registers_2__ap[21]), .QN(), .SE(dftIn), + .SI(registers_27__ap[22]) + ); + AOI221_X1_LVT i_1_0_1118( + .A(n_1_0_1065), .B1(n_1_0_1287), .B2(registers_10__ap[21]), .C1(registers_2__ap[21]), + .C2(n_1_0_1268), .ZN(n_1_0_1064) + ); + SDFF_X1_LVT \registers_reg[13][21] ( + .CK(n_0_43), .D(registers[21]), .Q(registers_13__ap[21]), .QN(), .SE(dftIn), + .SI(registers_10__ap[21]) + ); + SDFF_X1_LVT \registers_reg[30][21] ( + .CK(n_0_60), .D(registers[21]), .Q(registers_30__ap[21]), .QN(), .SE(dftIn), + .SI(registers_2__ap[21]) + ); + SDFF_X1_LVT \registers_reg[22][21] ( + .CK(n_0_52), .D(registers[21]), .Q(registers_22__ap[21]), .QN(), .SE(dftIn), + .SI(registers_20__ap[21]) + ); + AOI222_X1_LVT i_1_0_1117( + .A1(registers_13__ap[21]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[21]), + .C1(registers_22__ap[21]), .C2(n_1_0_1294), .ZN(n_1_0_1063) + ); + NAND2_X1_LVT i_1_0_1116( + .A1(n_1_0_1064), .A2(n_1_0_1063), .ZN(n_1_0_1062) + ); + SDFF_X1_LVT \registers_reg[1][21] ( + .CK(n_0_0), .D(registers[21]), .Q(registers_1__ap[21]), .QN(), .SE(dftIn), + .SI(registers_22__ap[21]) + ); + SDFF_X1_LVT \registers_reg[28][21] ( + .CK(n_0_58), .D(registers[21]), .Q(registers_28__ap[21]), .QN(), .SE(dftIn), + .SI(registers_30__ap[21]) + ); + AOI221_X1_LVT i_1_0_1115( + .A(n_1_0_1062), .B1(n_1_0_1274), .B2(registers_1__ap[21]), .C1(registers_28__ap[21]), + .C2(n_1_0_1283), .ZN(n_1_0_1061) + ); + SDFF_X1_LVT \registers_reg[18][21] ( + .CK(n_0_48), .D(registers[21]), .Q(registers_18__ap[21]), .QN(), .SE(dftIn), + .SI(registers_1__ap[21]) + ); + SDFF_X1_LVT \registers_reg[26][21] ( + .CK(n_0_56), .D(registers[21]), .Q(registers_26__ap[21]), .QN(), .SE(dftIn), + .SI(registers_28__ap[21]) + ); + AOI22_X1_LVT i_1_0_1114( + .A1(registers_18__ap[21]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[21]), + .ZN(n_1_0_1060) + ); + SDFF_X1_LVT \registers_reg[24][21] ( + .CK(n_0_54), .D(registers[21]), .Q(registers_24__ap[21]), .QN(), .SE(dftIn), + .SI(registers_26__ap[21]) + ); + SDFF_X1_LVT \registers_reg[4][21] ( + .CK(n_0_34), .D(registers[21]), .Q(registers_4__ap[21]), .QN(), .SE(dftIn), + .SI(registers_5__ap[21]) + ); + AOI22_X1_LVT i_1_0_1113( + .A1(registers_24__ap[21]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[21]), + .ZN(n_1_0_1059) + ); + SDFF_X1_LVT \registers_reg[15][21] ( + .CK(n_0_45), .D(registers[21]), .Q(registers_15__ap[21]), .QN(), .SE(dftIn), + .SI(registers_13__ap[21]) + ); + SDFF_X1_LVT \registers_reg[16][21] ( + .CK(n_0_46), .D(registers[21]), .Q(registers_16__ap[21]), .QN(), .SE(dftIn), + .SI(registers_15__ap[21]) + ); + AOI22_X1_LVT i_1_0_1112( + .A1(registers_15__ap[21]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[21]), + .ZN(n_1_0_1058) + ); + NAND3_X1_LVT i_1_0_1111( + .A1(n_1_0_1060), .A2(n_1_0_1059), .A3(n_1_0_1058), .ZN(n_1_0_1057) + ); + SDFF_X1_LVT \registers_reg[19][21] ( + .CK(n_0_49), .D(registers[21]), .Q(registers_19__ap[21]), .QN(), .SE(dftIn), + .SI(registers_18__ap[21]) + ); + SDFF_X1_LVT \registers_reg[25][21] ( + .CK(n_0_55), .D(registers[21]), .Q(registers_25__ap[21]), .QN(), .SE(dftIn), + .SI(registers_24__ap[21]) + ); + AOI221_X1_LVT i_1_0_1110( + .A(n_1_0_1057), .B1(n_1_0_1295), .B2(registers_19__ap[21]), .C1(registers_25__ap[21]), + .C2(n_1_0_1269), .ZN(n_1_0_1056) + ); + SDFF_X1_LVT \registers_reg[7][21] ( + .CK(n_0_37), .D(registers[21]), .Q(registers_7__ap[21]), .QN(), .SE(dftIn), + .SI(registers_4__ap[21]) + ); + SDFF_X1_LVT \registers_reg[14][21] ( + .CK(n_0_44), .D(registers[21]), .Q(registers_14__ap[21]), .QN(), .SE(dftIn), + .SI(registers_16__ap[21]) + ); + AOI22_X1_LVT i_1_0_1109( + .A1(registers_7__ap[21]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[21]), + .ZN(n_1_0_1055) + ); + SDFF_X1_LVT \registers_reg[9][21] ( + .CK(n_0_39), .D(registers[21]), .Q(registers_9__ap[21]), .QN(), .SE(dftIn), + .SI(registers_7__ap[21]) + ); + SDFF_X1_LVT \registers_reg[29][21] ( + .CK(n_0_59), .D(registers[21]), .Q(registers_29__ap[21]), .QN(), .SE(dftIn), + .SI(registers_25__ap[21]) + ); + AOI22_X1_LVT i_1_0_1108( + .A1(registers_9__ap[21]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[21]), + .ZN(n_1_0_1054) + ); + SDFF_X1_LVT \registers_reg[23][21] ( + .CK(n_0_53), .D(registers[21]), .Q(registers_23__ap[21]), .QN(), .SE(dftIn), + .SI(registers_19__ap[21]) + ); + SDFF_X1_LVT \registers_reg[3][21] ( + .CK(n_0_33), .D(registers[21]), .Q(registers_3__ap[21]), .QN(), .SE(dftIn), + .SI(registers_9__ap[21]) + ); + AOI22_X1_LVT i_1_0_1107( + .A1(registers_23__ap[21]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[21]), + .ZN(n_1_0_1053) + ); + NAND3_X1_LVT i_1_0_1106( + .A1(n_1_0_1055), .A2(n_1_0_1054), .A3(n_1_0_1053), .ZN(n_1_0_1052) + ); + SDFF_X1_LVT \registers_reg[27][21] ( + .CK(n_0_57), .D(registers[21]), .Q(registers_27__ap[21]), .QN(), .SE(dftIn), + .SI(registers_29__ap[21]) + ); + SDFF_X1_LVT \registers_reg[31][21] ( + .CK(n_0_61), .D(registers[21]), .Q(registers_31__ap[21]), .QN(), .SE(dftIn), + .SI(registers_3__ap[21]) + ); + AOI221_X1_LVT i_1_0_1105( + .A(n_1_0_1052), .B1(n_1_0_1279), .B2(registers_27__ap[21]), .C1(registers_31__ap[21]), + .C2(n_1_0_1266), .ZN(n_1_0_1051) + ); + NAND4_X1_LVT i_1_0_1104( + .A1(n_1_0_1068), .A2(n_1_0_1061), .A3(n_1_0_1056), .A4(n_1_0_1051), .ZN(RRs1[21]) + ); + AND2_X1_LVT i_0_0_20( + .A1(n_0_0_16), .A2(WRd[20]), .ZN(registers[20]) + ); + SDFF_X1_LVT \registers_reg[17][20] ( + .CK(n_0_47), .D(registers[20]), .Q(registers_17__ap[20]), .QN(), .SE(dftIn), + .SI(registers_23__ap[21]) + ); + SDFF_X1_LVT \registers_reg[21][20] ( + .CK(n_0_51), .D(registers[20]), .Q(registers_21__ap[20]), .QN(), .SE(dftIn), + .SI(registers_17__ap[20]) + ); + AOI22_X1_LVT i_1_0_1100( + .A1(registers_17__ap[20]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[20]), + .ZN(n_1_0_1047) + ); + SDFF_X1_LVT \registers_reg[10][20] ( + .CK(n_0_40), .D(registers[20]), .Q(registers_10__ap[20]), .QN(), .SE(dftIn), + .SI(registers_14__ap[21]) + ); + SDFF_X1_LVT \registers_reg[2][20] ( + .CK(n_0_32), .D(registers[20]), .Q(registers_2__ap[20]), .QN(), .SE(dftIn), + .SI(registers_27__ap[21]) + ); + AOI22_X1_LVT i_1_0_1103( + .A1(registers_10__ap[20]), .A2(n_1_0_1287), .B1(n_1_0_1268), .B2(registers_2__ap[20]), + .ZN(n_1_0_1050) + ); + SDFF_X1_LVT \registers_reg[20][20] ( + .CK(n_0_50), .D(registers[20]), .Q(registers_20__ap[20]), .QN(), .SE(dftIn), + .SI(registers_21__ap[20]) + ); + SDFF_X1_LVT \registers_reg[12][20] ( + .CK(n_0_42), .D(registers[20]), .Q(registers_12__ap[20]), .QN(), .SE(dftIn), + .SI(registers_10__ap[20]) + ); + AOI22_X1_LVT i_1_0_1099( + .A1(registers_20__ap[20]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[20]), + .ZN(n_1_0_1046) + ); + SDFF_X1_LVT \registers_reg[15][20] ( + .CK(n_0_45), .D(registers[20]), .Q(registers_15__ap[20]), .QN(), .SE(dftIn), + .SI(registers_12__ap[20]) + ); + SDFF_X1_LVT \registers_reg[8][20] ( + .CK(n_0_38), .D(registers[20]), .Q(registers_8__ap[20]), .QN(), .SE(dftIn), + .SI(registers_31__ap[21]) + ); + AOI22_X1_LVT i_1_0_1102( + .A1(registers_15__ap[20]), .A2(n_1_0_1286), .B1(n_1_0_1282), .B2(registers_8__ap[20]), + .ZN(n_1_0_1049) + ); + INV_X1_LVT i_1_0_1101( + .A(n_1_0_1049), .ZN(n_1_0_1048) + ); + SDFF_X1_LVT \registers_reg[11][20] ( + .CK(n_0_41), .D(registers[20]), .Q(registers_11__ap[20]), .QN(), .SE(dftIn), + .SI(registers_15__ap[20]) + ); + SDFF_X1_LVT \registers_reg[5][20] ( + .CK(n_0_35), .D(registers[20]), .Q(registers_5__ap[20]), .QN(), .SE(dftIn), + .SI(registers_8__ap[20]) + ); + AOI221_X1_LVT i_1_0_1098( + .A(n_1_0_1048), .B1(n_1_0_1270), .B2(registers_11__ap[20]), .C1(registers_5__ap[20]), + .C2(n_1_0_1273), .ZN(n_1_0_1045) + ); + SDFF_X1_LVT \registers_reg[13][20] ( + .CK(n_0_43), .D(registers[20]), .Q(registers_13__ap[20]), .QN(), .SE(dftIn), + .SI(registers_11__ap[20]) + ); + SDFF_X1_LVT \registers_reg[30][20] ( + .CK(n_0_60), .D(registers[20]), .Q(registers_30__ap[20]), .QN(), .SE(dftIn), + .SI(registers_2__ap[20]) + ); + SDFF_X1_LVT \registers_reg[22][20] ( + .CK(n_0_52), .D(registers[20]), .Q(registers_22__ap[20]), .QN(), .SE(dftIn), + .SI(registers_20__ap[20]) + ); + AOI222_X1_LVT i_1_0_1097( + .A1(registers_13__ap[20]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[20]), + .C1(registers_22__ap[20]), .C2(n_1_0_1294), .ZN(n_1_0_1044) + ); + NAND4_X1_LVT i_1_0_1096( + .A1(n_1_0_1050), .A2(n_1_0_1046), .A3(n_1_0_1045), .A4(n_1_0_1044), .ZN(n_1_0_1043) + ); + SDFF_X1_LVT \registers_reg[1][20] ( + .CK(n_0_0), .D(registers[20]), .Q(registers_1__ap[20]), .QN(), .SE(dftIn), + .SI(registers_22__ap[20]) + ); + SDFF_X1_LVT \registers_reg[28][20] ( + .CK(n_0_58), .D(registers[20]), .Q(registers_28__ap[20]), .QN(), .SE(dftIn), + .SI(registers_30__ap[20]) + ); + AOI221_X1_LVT i_1_0_1095( + .A(n_1_0_1043), .B1(n_1_0_1274), .B2(registers_1__ap[20]), .C1(registers_28__ap[20]), + .C2(n_1_0_1283), .ZN(n_1_0_1042) + ); + SDFF_X1_LVT \registers_reg[18][20] ( + .CK(n_0_48), .D(registers[20]), .Q(registers_18__ap[20]), .QN(), .SE(dftIn), + .SI(registers_1__ap[20]) + ); + SDFF_X1_LVT \registers_reg[26][20] ( + .CK(n_0_56), .D(registers[20]), .Q(registers_26__ap[20]), .QN(), .SE(dftIn), + .SI(registers_28__ap[20]) + ); + AOI22_X1_LVT i_1_0_1094( + .A1(registers_18__ap[20]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[20]), + .ZN(n_1_0_1041) + ); + SDFF_X1_LVT \registers_reg[24][20] ( + .CK(n_0_54), .D(registers[20]), .Q(registers_24__ap[20]), .QN(), .SE(dftIn), + .SI(registers_26__ap[20]) + ); + SDFF_X1_LVT \registers_reg[4][20] ( + .CK(n_0_34), .D(registers[20]), .Q(registers_4__ap[20]), .QN(), .SE(dftIn), + .SI(registers_5__ap[20]) + ); + AOI22_X1_LVT i_1_0_1093( + .A1(registers_24__ap[20]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[20]), + .ZN(n_1_0_1040) + ); + SDFF_X1_LVT \registers_reg[6][20] ( + .CK(n_0_36), .D(registers[20]), .Q(registers_6__ap[20]), .QN(), .SE(dftIn), + .SI(registers_4__ap[20]) + ); + SDFF_X1_LVT \registers_reg[25][20] ( + .CK(n_0_55), .D(registers[20]), .Q(registers_25__ap[20]), .QN(), .SE(dftIn), + .SI(registers_24__ap[20]) + ); + AOI22_X1_LVT i_1_0_1092( + .A1(registers_6__ap[20]), .A2(n_1_0_1300), .B1(n_1_0_1269), .B2(registers_25__ap[20]), + .ZN(n_1_0_1039) + ); + NAND3_X1_LVT i_1_0_1091( + .A1(n_1_0_1041), .A2(n_1_0_1040), .A3(n_1_0_1039), .ZN(n_1_0_1038) + ); + SDFF_X1_LVT \registers_reg[19][20] ( + .CK(n_0_49), .D(registers[20]), .Q(registers_19__ap[20]), .QN(), .SE(dftIn), + .SI(registers_18__ap[20]) + ); + SDFF_X1_LVT \registers_reg[16][20] ( + .CK(n_0_46), .D(registers[20]), .Q(registers_16__ap[20]), .QN(), .SE(dftIn), + .SI(registers_13__ap[20]) + ); + AOI221_X1_LVT i_1_0_1090( + .A(n_1_0_1038), .B1(n_1_0_1295), .B2(registers_19__ap[20]), .C1(registers_16__ap[20]), + .C2(n_1_0_1267), .ZN(n_1_0_1037) + ); + SDFF_X1_LVT \registers_reg[7][20] ( + .CK(n_0_37), .D(registers[20]), .Q(registers_7__ap[20]), .QN(), .SE(dftIn), + .SI(registers_6__ap[20]) + ); + SDFF_X1_LVT \registers_reg[14][20] ( + .CK(n_0_44), .D(registers[20]), .Q(registers_14__ap[20]), .QN(), .SE(dftIn), + .SI(registers_16__ap[20]) + ); + AOI22_X1_LVT i_1_0_1089( + .A1(registers_7__ap[20]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[20]), + .ZN(n_1_0_1036) + ); + SDFF_X1_LVT \registers_reg[9][20] ( + .CK(n_0_39), .D(registers[20]), .Q(registers_9__ap[20]), .QN(), .SE(dftIn), + .SI(registers_7__ap[20]) + ); + SDFF_X1_LVT \registers_reg[29][20] ( + .CK(n_0_59), .D(registers[20]), .Q(registers_29__ap[20]), .QN(), .SE(dftIn), + .SI(registers_25__ap[20]) + ); + AOI22_X1_LVT i_1_0_1088( + .A1(registers_9__ap[20]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[20]), + .ZN(n_1_0_1035) + ); + SDFF_X1_LVT \registers_reg[23][20] ( + .CK(n_0_53), .D(registers[20]), .Q(registers_23__ap[20]), .QN(), .SE(dftIn), + .SI(registers_19__ap[20]) + ); + SDFF_X1_LVT \registers_reg[3][20] ( + .CK(n_0_33), .D(registers[20]), .Q(registers_3__ap[20]), .QN(), .SE(dftIn), + .SI(registers_9__ap[20]) + ); + AOI22_X1_LVT i_1_0_1087( + .A1(registers_23__ap[20]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[20]), + .ZN(n_1_0_1034) + ); + NAND3_X1_LVT i_1_0_1086( + .A1(n_1_0_1036), .A2(n_1_0_1035), .A3(n_1_0_1034), .ZN(n_1_0_1033) + ); + SDFF_X1_LVT \registers_reg[27][20] ( + .CK(n_0_57), .D(registers[20]), .Q(registers_27__ap[20]), .QN(), .SE(dftIn), + .SI(registers_29__ap[20]) + ); + SDFF_X1_LVT \registers_reg[31][20] ( + .CK(n_0_61), .D(registers[20]), .Q(registers_31__ap[20]), .QN(), .SE(dftIn), + .SI(registers_3__ap[20]) + ); + AOI221_X1_LVT i_1_0_1085( + .A(n_1_0_1033), .B1(n_1_0_1279), .B2(registers_27__ap[20]), .C1(registers_31__ap[20]), + .C2(n_1_0_1266), .ZN(n_1_0_1032) + ); + NAND4_X1_LVT i_1_0_1084( + .A1(n_1_0_1047), .A2(n_1_0_1042), .A3(n_1_0_1037), .A4(n_1_0_1032), .ZN(RRs1[20]) + ); + AND2_X1_LVT i_0_0_19( + .A1(n_0_0_16), .A2(WRd[19]), .ZN(registers[19]) + ); + SDFF_X1_LVT \registers_reg[17][19] ( + .CK(n_0_47), .D(registers[19]), .Q(registers_17__ap[19]), .QN(), .SE(dftIn), + .SI(registers_23__ap[20]) + ); + SDFF_X1_LVT \registers_reg[21][19] ( + .CK(n_0_51), .D(registers[19]), .Q(registers_21__ap[19]), .QN(), .SE(dftIn), + .SI(registers_17__ap[19]) + ); + AOI22_X1_LVT i_1_0_1080( + .A1(registers_17__ap[19]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[19]), + .ZN(n_1_0_1028) + ); + SDFF_X1_LVT \registers_reg[2][19] ( + .CK(n_0_32), .D(registers[19]), .Q(registers_2__ap[19]), .QN(), .SE(dftIn), + .SI(registers_27__ap[20]) + ); + SDFF_X1_LVT \registers_reg[31][19] ( + .CK(n_0_61), .D(registers[19]), .Q(registers_31__ap[19]), .QN(), .SE(dftIn), + .SI(registers_31__ap[20]) + ); + AOI22_X1_LVT i_1_0_1083( + .A1(registers_2__ap[19]), .A2(n_1_0_1268), .B1(n_1_0_1266), .B2(registers_31__ap[19]), + .ZN(n_1_0_1031) + ); + SDFF_X1_LVT \registers_reg[20][19] ( + .CK(n_0_50), .D(registers[19]), .Q(registers_20__ap[19]), .QN(), .SE(dftIn), + .SI(registers_21__ap[19]) + ); + SDFF_X1_LVT \registers_reg[12][19] ( + .CK(n_0_42), .D(registers[19]), .Q(registers_12__ap[19]), .QN(), .SE(dftIn), + .SI(registers_14__ap[20]) + ); + AOI22_X1_LVT i_1_0_1079( + .A1(registers_20__ap[19]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[19]), + .ZN(n_1_0_1027) + ); + SDFF_X1_LVT \registers_reg[15][19] ( + .CK(n_0_45), .D(registers[19]), .Q(registers_15__ap[19]), .QN(), .SE(dftIn), + .SI(registers_12__ap[19]) + ); + SDFF_X1_LVT \registers_reg[11][19] ( + .CK(n_0_41), .D(registers[19]), .Q(registers_11__ap[19]), .QN(), .SE(dftIn), + .SI(registers_15__ap[19]) + ); + AOI22_X1_LVT i_1_0_1082( + .A1(registers_15__ap[19]), .A2(n_1_0_1286), .B1(n_1_0_1270), .B2(registers_11__ap[19]), + .ZN(n_1_0_1030) + ); + INV_X1_LVT i_1_0_1081( + .A(n_1_0_1030), .ZN(n_1_0_1029) + ); + SDFF_X1_LVT \registers_reg[27][19] ( + .CK(n_0_57), .D(registers[19]), .Q(registers_27__ap[19]), .QN(), .SE(dftIn), + .SI(registers_2__ap[19]) + ); + SDFF_X1_LVT \registers_reg[24][19] ( + .CK(n_0_54), .D(registers[19]), .Q(registers_24__ap[19]), .QN(), .SE(dftIn), + .SI(registers_27__ap[19]) + ); + AOI221_X1_LVT i_1_0_1078( + .A(n_1_0_1029), .B1(n_1_0_1279), .B2(registers_27__ap[19]), .C1(registers_24__ap[19]), + .C2(n_1_0_1289), .ZN(n_1_0_1026) + ); + SDFF_X1_LVT \registers_reg[22][19] ( + .CK(n_0_52), .D(registers[19]), .Q(registers_22__ap[19]), .QN(), .SE(dftIn), + .SI(registers_20__ap[19]) + ); + SDFF_X1_LVT \registers_reg[26][19] ( + .CK(n_0_56), .D(registers[19]), .Q(registers_26__ap[19]), .QN(), .SE(dftIn), + .SI(registers_24__ap[19]) + ); + SDFF_X1_LVT \registers_reg[13][19] ( + .CK(n_0_43), .D(registers[19]), .Q(registers_13__ap[19]), .QN(), .SE(dftIn), + .SI(registers_11__ap[19]) + ); + AOI222_X1_LVT i_1_0_1077( + .A1(registers_22__ap[19]), .A2(n_1_0_1294), .B1(n_1_0_1285), .B2(registers_26__ap[19]), + .C1(n_1_0_1277), .C2(registers_13__ap[19]), .ZN(n_1_0_1025) + ); + NAND4_X1_LVT i_1_0_1076( + .A1(n_1_0_1031), .A2(n_1_0_1027), .A3(n_1_0_1026), .A4(n_1_0_1025), .ZN(n_1_0_1024) + ); + SDFF_X1_LVT \registers_reg[1][19] ( + .CK(n_0_0), .D(registers[19]), .Q(registers_1__ap[19]), .QN(), .SE(dftIn), + .SI(registers_22__ap[19]) + ); + SDFF_X1_LVT \registers_reg[28][19] ( + .CK(n_0_58), .D(registers[19]), .Q(registers_28__ap[19]), .QN(), .SE(dftIn), + .SI(registers_26__ap[19]) + ); + AOI221_X1_LVT i_1_0_1075( + .A(n_1_0_1024), .B1(n_1_0_1274), .B2(registers_1__ap[19]), .C1(registers_28__ap[19]), + .C2(n_1_0_1283), .ZN(n_1_0_1023) + ); + SDFF_X1_LVT \registers_reg[18][19] ( + .CK(n_0_48), .D(registers[19]), .Q(registers_18__ap[19]), .QN(), .SE(dftIn), + .SI(registers_1__ap[19]) + ); + SDFF_X1_LVT \registers_reg[30][19] ( + .CK(n_0_60), .D(registers[19]), .Q(registers_30__ap[19]), .QN(), .SE(dftIn), + .SI(registers_28__ap[19]) + ); + AOI22_X1_LVT i_1_0_1074( + .A1(registers_18__ap[19]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[19]), + .ZN(n_1_0_1022) + ); + SDFF_X1_LVT \registers_reg[4][19] ( + .CK(n_0_34), .D(registers[19]), .Q(registers_4__ap[19]), .QN(), .SE(dftIn), + .SI(registers_31__ap[19]) + ); + SDFF_X1_LVT \registers_reg[5][19] ( + .CK(n_0_35), .D(registers[19]), .Q(registers_5__ap[19]), .QN(), .SE(dftIn), + .SI(registers_4__ap[19]) + ); + AOI22_X1_LVT i_1_0_1073( + .A1(registers_4__ap[19]), .A2(n_1_0_1278), .B1(n_1_0_1273), .B2(registers_5__ap[19]), + .ZN(n_1_0_1021) + ); + SDFF_X1_LVT \registers_reg[6][19] ( + .CK(n_0_36), .D(registers[19]), .Q(registers_6__ap[19]), .QN(), .SE(dftIn), + .SI(registers_5__ap[19]) + ); + SDFF_X1_LVT \registers_reg[25][19] ( + .CK(n_0_55), .D(registers[19]), .Q(registers_25__ap[19]), .QN(), .SE(dftIn), + .SI(registers_30__ap[19]) + ); + AOI22_X1_LVT i_1_0_1072( + .A1(registers_6__ap[19]), .A2(n_1_0_1300), .B1(n_1_0_1269), .B2(registers_25__ap[19]), + .ZN(n_1_0_1020) + ); + NAND3_X1_LVT i_1_0_1071( + .A1(n_1_0_1022), .A2(n_1_0_1021), .A3(n_1_0_1020), .ZN(n_1_0_1019) + ); + SDFF_X1_LVT \registers_reg[19][19] ( + .CK(n_0_49), .D(registers[19]), .Q(registers_19__ap[19]), .QN(), .SE(dftIn), + .SI(registers_18__ap[19]) + ); + SDFF_X1_LVT \registers_reg[16][19] ( + .CK(n_0_46), .D(registers[19]), .Q(registers_16__ap[19]), .QN(), .SE(dftIn), + .SI(registers_13__ap[19]) + ); + AOI221_X1_LVT i_1_0_1070( + .A(n_1_0_1019), .B1(n_1_0_1295), .B2(registers_19__ap[19]), .C1(registers_16__ap[19]), + .C2(n_1_0_1267), .ZN(n_1_0_1018) + ); + SDFF_X1_LVT \registers_reg[9][19] ( + .CK(n_0_39), .D(registers[19]), .Q(registers_9__ap[19]), .QN(), .SE(dftIn), + .SI(registers_6__ap[19]) + ); + SDFF_X1_LVT \registers_reg[29][19] ( + .CK(n_0_59), .D(registers[19]), .Q(registers_29__ap[19]), .QN(), .SE(dftIn), + .SI(registers_25__ap[19]) + ); + AOI22_X1_LVT i_1_0_1069( + .A1(registers_9__ap[19]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[19]), + .ZN(n_1_0_1017) + ); + SDFF_X1_LVT \registers_reg[8][19] ( + .CK(n_0_38), .D(registers[19]), .Q(registers_8__ap[19]), .QN(), .SE(dftIn), + .SI(registers_9__ap[19]) + ); + SDFF_X1_LVT \registers_reg[23][19] ( + .CK(n_0_53), .D(registers[19]), .Q(registers_23__ap[19]), .QN(), .SE(dftIn), + .SI(registers_19__ap[19]) + ); + AOI22_X1_LVT i_1_0_1068( + .A1(registers_8__ap[19]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[19]), + .ZN(n_1_0_1016) + ); + SDFF_X1_LVT \registers_reg[7][19] ( + .CK(n_0_37), .D(registers[19]), .Q(registers_7__ap[19]), .QN(), .SE(dftIn), + .SI(registers_8__ap[19]) + ); + SDFF_X1_LVT \registers_reg[14][19] ( + .CK(n_0_44), .D(registers[19]), .Q(registers_14__ap[19]), .QN(), .SE(dftIn), + .SI(registers_16__ap[19]) + ); + AOI22_X1_LVT i_1_0_1067( + .A1(registers_7__ap[19]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[19]), + .ZN(n_1_0_1015) + ); + NAND3_X1_LVT i_1_0_1066( + .A1(n_1_0_1017), .A2(n_1_0_1016), .A3(n_1_0_1015), .ZN(n_1_0_1014) + ); + SDFF_X1_LVT \registers_reg[10][19] ( + .CK(n_0_40), .D(registers[19]), .Q(registers_10__ap[19]), .QN(), .SE(dftIn), + .SI(registers_14__ap[19]) + ); + SDFF_X1_LVT \registers_reg[3][19] ( + .CK(n_0_33), .D(registers[19]), .Q(registers_3__ap[19]), .QN(), .SE(dftIn), + .SI(registers_7__ap[19]) + ); + AOI221_X1_LVT i_1_0_1065( + .A(n_1_0_1014), .B1(n_1_0_1287), .B2(registers_10__ap[19]), .C1(registers_3__ap[19]), + .C2(n_1_0_1257), .ZN(n_1_0_1013) + ); + NAND4_X1_LVT i_1_0_1064( + .A1(n_1_0_1028), .A2(n_1_0_1023), .A3(n_1_0_1018), .A4(n_1_0_1013), .ZN(RRs1[19]) + ); + AND2_X1_LVT i_0_0_18( + .A1(n_0_0_16), .A2(WRd[18]), .ZN(registers[18]) + ); + SDFF_X1_LVT \registers_reg[24][18] ( + .CK(n_0_54), .D(registers[18]), .Q(registers_24__ap[18]), .QN(), .SE(dftIn), + .SI(registers_29__ap[19]) + ); + SDFF_X1_LVT \registers_reg[28][18] ( + .CK(n_0_58), .D(registers[18]), .Q(registers_28__ap[18]), .QN(), .SE(dftIn), + .SI(registers_24__ap[18]) + ); + AOI22_X1_LVT i_1_0_1062( + .A1(registers_24__ap[18]), .A2(n_1_0_1289), .B1(n_1_0_1283), .B2(registers_28__ap[18]), + .ZN(n_1_0_1011) + ); + SDFF_X1_LVT \registers_reg[11][18] ( + .CK(n_0_41), .D(registers[18]), .Q(registers_11__ap[18]), .QN(), .SE(dftIn), + .SI(registers_10__ap[19]) + ); + SDFF_X1_LVT \registers_reg[16][18] ( + .CK(n_0_46), .D(registers[18]), .Q(registers_16__ap[18]), .QN(), .SE(dftIn), + .SI(registers_11__ap[18]) + ); + AOI22_X1_LVT i_1_0_1063( + .A1(registers_11__ap[18]), .A2(n_1_0_1270), .B1(n_1_0_1267), .B2(registers_16__ap[18]), + .ZN(n_1_0_1012) + ); + SDFF_X1_LVT \registers_reg[9][18] ( + .CK(n_0_39), .D(registers[18]), .Q(registers_9__ap[18]), .QN(), .SE(dftIn), + .SI(registers_3__ap[19]) + ); + SDFF_X1_LVT \registers_reg[7][18] ( + .CK(n_0_37), .D(registers[18]), .Q(registers_7__ap[18]), .QN(), .SE(dftIn), + .SI(registers_9__ap[18]) + ); + AOI22_X1_LVT i_1_0_1061( + .A1(registers_9__ap[18]), .A2(n_1_0_1291), .B1(n_1_0_1263), .B2(registers_7__ap[18]), + .ZN(n_1_0_1010) + ); + SDFF_X1_LVT \registers_reg[27][18] ( + .CK(n_0_57), .D(registers[18]), .Q(registers_27__ap[18]), .QN(), .SE(dftIn), + .SI(registers_28__ap[18]) + ); + SDFF_X1_LVT \registers_reg[25][18] ( + .CK(n_0_55), .D(registers[18]), .Q(registers_25__ap[18]), .QN(), .SE(dftIn), + .SI(registers_27__ap[18]) + ); + AOI22_X1_LVT i_1_0_1060( + .A1(registers_27__ap[18]), .A2(n_1_0_1279), .B1(n_1_0_1269), .B2(registers_25__ap[18]), + .ZN(n_1_0_1009) + ); + NAND3_X1_LVT i_1_0_1059( + .A1(n_1_0_1012), .A2(n_1_0_1010), .A3(n_1_0_1009), .ZN(n_1_0_1008) + ); + SDFF_X1_LVT \registers_reg[31][18] ( + .CK(n_0_61), .D(registers[18]), .Q(registers_31__ap[18]), .QN(), .SE(dftIn), + .SI(registers_7__ap[18]) + ); + SDFF_X1_LVT \registers_reg[6][18] ( + .CK(n_0_36), .D(registers[18]), .Q(registers_6__ap[18]), .QN(), .SE(dftIn), + .SI(registers_31__ap[18]) + ); + AOI221_X1_LVT i_1_0_1058( + .A(n_1_0_1008), .B1(n_1_0_1266), .B2(registers_31__ap[18]), .C1(registers_6__ap[18]), + .C2(n_1_0_1300), .ZN(n_1_0_1007) + ); + SDFF_X1_LVT \registers_reg[22][18] ( + .CK(n_0_52), .D(registers[18]), .Q(registers_22__ap[18]), .QN(), .SE(dftIn), + .SI(registers_23__ap[19]) + ); + SDFF_X1_LVT \registers_reg[26][18] ( + .CK(n_0_56), .D(registers[18]), .Q(registers_26__ap[18]), .QN(), .SE(dftIn), + .SI(registers_25__ap[18]) + ); + SDFF_X1_LVT \registers_reg[1][18] ( + .CK(n_0_0), .D(registers[18]), .Q(registers_1__ap[18]), .QN(), .SE(dftIn), + .SI(registers_22__ap[18]) + ); + AOI222_X1_LVT i_1_0_1057( + .A1(registers_22__ap[18]), .A2(n_1_0_1294), .B1(n_1_0_1285), .B2(registers_26__ap[18]), + .C1(n_1_0_1274), .C2(registers_1__ap[18]), .ZN(n_1_0_1006) + ); + NAND2_X1_LVT i_1_0_1056( + .A1(n_1_0_1007), .A2(n_1_0_1006), .ZN(n_1_0_1005) + ); + SDFF_X1_LVT \registers_reg[29][18] ( + .CK(n_0_59), .D(registers[18]), .Q(registers_29__ap[18]), .QN(), .SE(dftIn), + .SI(registers_26__ap[18]) + ); + SDFF_X1_LVT \registers_reg[2][18] ( + .CK(n_0_32), .D(registers[18]), .Q(registers_2__ap[18]), .QN(), .SE(dftIn), + .SI(registers_29__ap[18]) + ); + AOI221_X1_LVT i_1_0_1055( + .A(n_1_0_1005), .B1(n_1_0_1276), .B2(registers_29__ap[18]), .C1(registers_2__ap[18]), + .C2(n_1_0_1268), .ZN(n_1_0_1004) + ); + SDFF_X1_LVT \registers_reg[18][18] ( + .CK(n_0_48), .D(registers[18]), .Q(registers_18__ap[18]), .QN(), .SE(dftIn), + .SI(registers_1__ap[18]) + ); + SDFF_X1_LVT \registers_reg[30][18] ( + .CK(n_0_60), .D(registers[18]), .Q(registers_30__ap[18]), .QN(), .SE(dftIn), + .SI(registers_2__ap[18]) + ); + AOI22_X1_LVT i_1_0_1054( + .A1(registers_18__ap[18]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[18]), + .ZN(n_1_0_1003) + ); + SDFF_X1_LVT \registers_reg[4][18] ( + .CK(n_0_34), .D(registers[18]), .Q(registers_4__ap[18]), .QN(), .SE(dftIn), + .SI(registers_6__ap[18]) + ); + SDFF_X1_LVT \registers_reg[12][18] ( + .CK(n_0_42), .D(registers[18]), .Q(registers_12__ap[18]), .QN(), .SE(dftIn), + .SI(registers_16__ap[18]) + ); + AOI22_X1_LVT i_1_0_1053( + .A1(registers_4__ap[18]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[18]), + .ZN(n_1_0_1002) + ); + SDFF_X1_LVT \registers_reg[19][18] ( + .CK(n_0_49), .D(registers[18]), .Q(registers_19__ap[18]), .QN(), .SE(dftIn), + .SI(registers_18__ap[18]) + ); + SDFF_X1_LVT \registers_reg[21][18] ( + .CK(n_0_51), .D(registers[18]), .Q(registers_21__ap[18]), .QN(), .SE(dftIn), + .SI(registers_19__ap[18]) + ); + AOI22_X1_LVT i_1_0_1052( + .A1(registers_19__ap[18]), .A2(n_1_0_1295), .B1(n_1_0_1259), .B2(registers_21__ap[18]), + .ZN(n_1_0_1001) + ); + NAND3_X1_LVT i_1_0_1051( + .A1(n_1_0_1003), .A2(n_1_0_1002), .A3(n_1_0_1001), .ZN(n_1_0_1000) + ); + SDFF_X1_LVT \registers_reg[5][18] ( + .CK(n_0_35), .D(registers[18]), .Q(registers_5__ap[18]), .QN(), .SE(dftIn), + .SI(registers_4__ap[18]) + ); + SDFF_X1_LVT \registers_reg[20][18] ( + .CK(n_0_50), .D(registers[18]), .Q(registers_20__ap[18]), .QN(), .SE(dftIn), + .SI(registers_21__ap[18]) + ); + AOI221_X1_LVT i_1_0_1050( + .A(n_1_0_1000), .B1(n_1_0_1273), .B2(registers_5__ap[18]), .C1(registers_20__ap[18]), + .C2(n_1_0_1281), .ZN(n_1_0_999) + ); + SDFF_X1_LVT \registers_reg[8][18] ( + .CK(n_0_38), .D(registers[18]), .Q(registers_8__ap[18]), .QN(), .SE(dftIn), + .SI(registers_5__ap[18]) + ); + SDFF_X1_LVT \registers_reg[23][18] ( + .CK(n_0_53), .D(registers[18]), .Q(registers_23__ap[18]), .QN(), .SE(dftIn), + .SI(registers_20__ap[18]) + ); + AOI22_X1_LVT i_1_0_1049( + .A1(registers_8__ap[18]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[18]), + .ZN(n_1_0_998) + ); + SDFF_X1_LVT \registers_reg[13][18] ( + .CK(n_0_43), .D(registers[18]), .Q(registers_13__ap[18]), .QN(), .SE(dftIn), + .SI(registers_12__ap[18]) + ); + SDFF_X1_LVT \registers_reg[17][18] ( + .CK(n_0_47), .D(registers[18]), .Q(registers_17__ap[18]), .QN(), .SE(dftIn), + .SI(registers_23__ap[18]) + ); + AOI22_X1_LVT i_1_0_1048( + .A1(registers_13__ap[18]), .A2(n_1_0_1277), .B1(n_1_0_1271), .B2(registers_17__ap[18]), + .ZN(n_1_0_997) + ); + SDFF_X1_LVT \registers_reg[15][18] ( + .CK(n_0_45), .D(registers[18]), .Q(registers_15__ap[18]), .QN(), .SE(dftIn), + .SI(registers_13__ap[18]) + ); + SDFF_X1_LVT \registers_reg[14][18] ( + .CK(n_0_44), .D(registers[18]), .Q(registers_14__ap[18]), .QN(), .SE(dftIn), + .SI(registers_15__ap[18]) + ); + AOI22_X1_LVT i_1_0_1047( + .A1(registers_15__ap[18]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[18]), + .ZN(n_1_0_996) + ); + NAND3_X1_LVT i_1_0_1046( + .A1(n_1_0_998), .A2(n_1_0_997), .A3(n_1_0_996), .ZN(n_1_0_995) + ); + SDFF_X1_LVT \registers_reg[10][18] ( + .CK(n_0_40), .D(registers[18]), .Q(registers_10__ap[18]), .QN(), .SE(dftIn), + .SI(registers_14__ap[18]) + ); + SDFF_X1_LVT \registers_reg[3][18] ( + .CK(n_0_33), .D(registers[18]), .Q(registers_3__ap[18]), .QN(), .SE(dftIn), + .SI(registers_8__ap[18]) + ); + AOI221_X1_LVT i_1_0_1045( + .A(n_1_0_995), .B1(n_1_0_1287), .B2(registers_10__ap[18]), .C1(registers_3__ap[18]), + .C2(n_1_0_1257), .ZN(n_1_0_994) + ); + NAND4_X1_LVT i_1_0_1044( + .A1(n_1_0_1011), .A2(n_1_0_1004), .A3(n_1_0_999), .A4(n_1_0_994), .ZN(RRs1[18]) + ); + AND2_X1_LVT i_0_0_17( + .A1(n_0_0_16), .A2(WRd[17]), .ZN(registers[17]) + ); + SDFF_X1_LVT \registers_reg[17][17] ( + .CK(n_0_47), .D(registers[17]), .Q(registers_17__ap[17]), .QN(), .SE(dftIn), + .SI(registers_17__ap[18]) + ); + SDFF_X1_LVT \registers_reg[21][17] ( + .CK(n_0_51), .D(registers[17]), .Q(registers_21__ap[17]), .QN(), .SE(dftIn), + .SI(registers_17__ap[17]) + ); + AOI22_X1_LVT i_1_0_1040( + .A1(registers_17__ap[17]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[17]), + .ZN(n_1_0_990) + ); + SDFF_X1_LVT \registers_reg[2][17] ( + .CK(n_0_32), .D(registers[17]), .Q(registers_2__ap[17]), .QN(), .SE(dftIn), + .SI(registers_30__ap[18]) + ); + SDFF_X1_LVT \registers_reg[31][17] ( + .CK(n_0_61), .D(registers[17]), .Q(registers_31__ap[17]), .QN(), .SE(dftIn), + .SI(registers_3__ap[18]) + ); + AOI22_X1_LVT i_1_0_1043( + .A1(registers_2__ap[17]), .A2(n_1_0_1268), .B1(n_1_0_1266), .B2(registers_31__ap[17]), + .ZN(n_1_0_993) + ); + SDFF_X1_LVT \registers_reg[20][17] ( + .CK(n_0_50), .D(registers[17]), .Q(registers_20__ap[17]), .QN(), .SE(dftIn), + .SI(registers_21__ap[17]) + ); + SDFF_X1_LVT \registers_reg[12][17] ( + .CK(n_0_42), .D(registers[17]), .Q(registers_12__ap[17]), .QN(), .SE(dftIn), + .SI(registers_10__ap[18]) + ); + AOI22_X1_LVT i_1_0_1039( + .A1(registers_20__ap[17]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[17]), + .ZN(n_1_0_989) + ); + SDFF_X1_LVT \registers_reg[15][17] ( + .CK(n_0_45), .D(registers[17]), .Q(registers_15__ap[17]), .QN(), .SE(dftIn), + .SI(registers_12__ap[17]) + ); + SDFF_X1_LVT \registers_reg[11][17] ( + .CK(n_0_41), .D(registers[17]), .Q(registers_11__ap[17]), .QN(), .SE(dftIn), + .SI(registers_15__ap[17]) + ); + AOI22_X1_LVT i_1_0_1042( + .A1(registers_15__ap[17]), .A2(n_1_0_1286), .B1(n_1_0_1270), .B2(registers_11__ap[17]), + .ZN(n_1_0_992) + ); + INV_X1_LVT i_1_0_1041( + .A(n_1_0_992), .ZN(n_1_0_991) + ); + SDFF_X1_LVT \registers_reg[10][17] ( + .CK(n_0_40), .D(registers[17]), .Q(registers_10__ap[17]), .QN(), .SE(dftIn), + .SI(registers_11__ap[17]) + ); + SDFF_X1_LVT \registers_reg[24][17] ( + .CK(n_0_54), .D(registers[17]), .Q(registers_24__ap[17]), .QN(), .SE(dftIn), + .SI(registers_2__ap[17]) + ); + AOI221_X1_LVT i_1_0_1038( + .A(n_1_0_991), .B1(n_1_0_1287), .B2(registers_10__ap[17]), .C1(registers_24__ap[17]), + .C2(n_1_0_1289), .ZN(n_1_0_988) + ); + SDFF_X1_LVT \registers_reg[22][17] ( + .CK(n_0_52), .D(registers[17]), .Q(registers_22__ap[17]), .QN(), .SE(dftIn), + .SI(registers_20__ap[17]) + ); + SDFF_X1_LVT \registers_reg[26][17] ( + .CK(n_0_56), .D(registers[17]), .Q(registers_26__ap[17]), .QN(), .SE(dftIn), + .SI(registers_24__ap[17]) + ); + SDFF_X1_LVT \registers_reg[13][17] ( + .CK(n_0_43), .D(registers[17]), .Q(registers_13__ap[17]), .QN(), .SE(dftIn), + .SI(registers_10__ap[17]) + ); + AOI222_X1_LVT i_1_0_1037( + .A1(registers_22__ap[17]), .A2(n_1_0_1294), .B1(n_1_0_1285), .B2(registers_26__ap[17]), + .C1(n_1_0_1277), .C2(registers_13__ap[17]), .ZN(n_1_0_987) + ); + NAND4_X1_LVT i_1_0_1036( + .A1(n_1_0_993), .A2(n_1_0_989), .A3(n_1_0_988), .A4(n_1_0_987), .ZN(n_1_0_986) + ); + SDFF_X1_LVT \registers_reg[1][17] ( + .CK(n_0_0), .D(registers[17]), .Q(registers_1__ap[17]), .QN(), .SE(dftIn), + .SI(registers_22__ap[17]) + ); + SDFF_X1_LVT \registers_reg[28][17] ( + .CK(n_0_58), .D(registers[17]), .Q(registers_28__ap[17]), .QN(), .SE(dftIn), + .SI(registers_26__ap[17]) + ); + AOI221_X1_LVT i_1_0_1035( + .A(n_1_0_986), .B1(n_1_0_1274), .B2(registers_1__ap[17]), .C1(registers_28__ap[17]), + .C2(n_1_0_1283), .ZN(n_1_0_985) + ); + SDFF_X1_LVT \registers_reg[18][17] ( + .CK(n_0_48), .D(registers[17]), .Q(registers_18__ap[17]), .QN(), .SE(dftIn), + .SI(registers_1__ap[17]) + ); + SDFF_X1_LVT \registers_reg[30][17] ( + .CK(n_0_60), .D(registers[17]), .Q(registers_30__ap[17]), .QN(), .SE(dftIn), + .SI(registers_28__ap[17]) + ); + AOI22_X1_LVT i_1_0_1034( + .A1(registers_18__ap[17]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[17]), + .ZN(n_1_0_984) + ); + SDFF_X1_LVT \registers_reg[4][17] ( + .CK(n_0_34), .D(registers[17]), .Q(registers_4__ap[17]), .QN(), .SE(dftIn), + .SI(registers_31__ap[17]) + ); + SDFF_X1_LVT \registers_reg[5][17] ( + .CK(n_0_35), .D(registers[17]), .Q(registers_5__ap[17]), .QN(), .SE(dftIn), + .SI(registers_4__ap[17]) + ); + AOI22_X1_LVT i_1_0_1033( + .A1(registers_4__ap[17]), .A2(n_1_0_1278), .B1(n_1_0_1273), .B2(registers_5__ap[17]), + .ZN(n_1_0_983) + ); + SDFF_X1_LVT \registers_reg[6][17] ( + .CK(n_0_36), .D(registers[17]), .Q(registers_6__ap[17]), .QN(), .SE(dftIn), + .SI(registers_5__ap[17]) + ); + SDFF_X1_LVT \registers_reg[25][17] ( + .CK(n_0_55), .D(registers[17]), .Q(registers_25__ap[17]), .QN(), .SE(dftIn), + .SI(registers_30__ap[17]) + ); + AOI22_X1_LVT i_1_0_1032( + .A1(registers_6__ap[17]), .A2(n_1_0_1300), .B1(n_1_0_1269), .B2(registers_25__ap[17]), + .ZN(n_1_0_982) + ); + NAND3_X1_LVT i_1_0_1031( + .A1(n_1_0_984), .A2(n_1_0_983), .A3(n_1_0_982), .ZN(n_1_0_981) + ); + SDFF_X1_LVT \registers_reg[19][17] ( + .CK(n_0_49), .D(registers[17]), .Q(registers_19__ap[17]), .QN(), .SE(dftIn), + .SI(registers_18__ap[17]) + ); + SDFF_X1_LVT \registers_reg[16][17] ( + .CK(n_0_46), .D(registers[17]), .Q(registers_16__ap[17]), .QN(), .SE(dftIn), + .SI(registers_13__ap[17]) + ); + AOI221_X1_LVT i_1_0_1030( + .A(n_1_0_981), .B1(n_1_0_1295), .B2(registers_19__ap[17]), .C1(registers_16__ap[17]), + .C2(n_1_0_1267), .ZN(n_1_0_980) + ); + SDFF_X1_LVT \registers_reg[7][17] ( + .CK(n_0_37), .D(registers[17]), .Q(registers_7__ap[17]), .QN(), .SE(dftIn), + .SI(registers_6__ap[17]) + ); + SDFF_X1_LVT \registers_reg[14][17] ( + .CK(n_0_44), .D(registers[17]), .Q(registers_14__ap[17]), .QN(), .SE(dftIn), + .SI(registers_16__ap[17]) + ); + AOI22_X1_LVT i_1_0_1029( + .A1(registers_7__ap[17]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[17]), + .ZN(n_1_0_979) + ); + SDFF_X1_LVT \registers_reg[9][17] ( + .CK(n_0_39), .D(registers[17]), .Q(registers_9__ap[17]), .QN(), .SE(dftIn), + .SI(registers_7__ap[17]) + ); + SDFF_X1_LVT \registers_reg[29][17] ( + .CK(n_0_59), .D(registers[17]), .Q(registers_29__ap[17]), .QN(), .SE(dftIn), + .SI(registers_25__ap[17]) + ); + AOI22_X1_LVT i_1_0_1028( + .A1(registers_9__ap[17]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[17]), + .ZN(n_1_0_978) + ); + SDFF_X1_LVT \registers_reg[8][17] ( + .CK(n_0_38), .D(registers[17]), .Q(registers_8__ap[17]), .QN(), .SE(dftIn), + .SI(registers_9__ap[17]) + ); + SDFF_X1_LVT \registers_reg[23][17] ( + .CK(n_0_53), .D(registers[17]), .Q(registers_23__ap[17]), .QN(), .SE(dftIn), + .SI(registers_19__ap[17]) + ); + AOI22_X1_LVT i_1_0_1027( + .A1(registers_8__ap[17]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[17]), + .ZN(n_1_0_977) + ); + NAND3_X1_LVT i_1_0_1026( + .A1(n_1_0_979), .A2(n_1_0_978), .A3(n_1_0_977), .ZN(n_1_0_976) + ); + SDFF_X1_LVT \registers_reg[27][17] ( + .CK(n_0_57), .D(registers[17]), .Q(registers_27__ap[17]), .QN(), .SE(dftIn), + .SI(registers_29__ap[17]) + ); + SDFF_X1_LVT \registers_reg[3][17] ( + .CK(n_0_33), .D(registers[17]), .Q(registers_3__ap[17]), .QN(), .SE(dftIn), + .SI(registers_8__ap[17]) + ); + AOI221_X1_LVT i_1_0_1025( + .A(n_1_0_976), .B1(n_1_0_1279), .B2(registers_27__ap[17]), .C1(registers_3__ap[17]), + .C2(n_1_0_1257), .ZN(n_1_0_975) + ); + NAND4_X1_LVT i_1_0_1024( + .A1(n_1_0_990), .A2(n_1_0_985), .A3(n_1_0_980), .A4(n_1_0_975), .ZN(RRs1[17]) + ); + AND2_X1_LVT i_0_0_16( + .A1(n_0_0_16), .A2(WRd[16]), .ZN(registers[16]) + ); + SDFF_X1_LVT \registers_reg[29][16] ( + .CK(n_0_59), .D(registers[16]), .Q(registers_29__ap[16]), .QN(), .SE(dftIn), + .SI(registers_27__ap[17]) + ); + SDFF_X1_LVT \registers_reg[2][16] ( + .CK(n_0_32), .D(registers[16]), .Q(registers_2__ap[16]), .QN(), .SE(dftIn), + .SI(registers_29__ap[16]) + ); + AOI22_X1_LVT i_1_0_1022( + .A1(registers_29__ap[16]), .A2(n_1_0_1276), .B1(n_1_0_1268), .B2(registers_2__ap[16]), + .ZN(n_1_0_973) + ); + SDFF_X1_LVT \registers_reg[11][16] ( + .CK(n_0_41), .D(registers[16]), .Q(registers_11__ap[16]), .QN(), .SE(dftIn), + .SI(registers_14__ap[17]) + ); + SDFF_X1_LVT \registers_reg[25][16] ( + .CK(n_0_55), .D(registers[16]), .Q(registers_25__ap[16]), .QN(), .SE(dftIn), + .SI(registers_2__ap[16]) + ); + AOI22_X1_LVT i_1_0_1023( + .A1(registers_11__ap[16]), .A2(n_1_0_1270), .B1(n_1_0_1269), .B2(registers_25__ap[16]), + .ZN(n_1_0_974) + ); + SDFF_X1_LVT \registers_reg[9][16] ( + .CK(n_0_39), .D(registers[16]), .Q(registers_9__ap[16]), .QN(), .SE(dftIn), + .SI(registers_3__ap[17]) + ); + SDFF_X1_LVT \registers_reg[7][16] ( + .CK(n_0_37), .D(registers[16]), .Q(registers_7__ap[16]), .QN(), .SE(dftIn), + .SI(registers_9__ap[16]) + ); + AOI22_X1_LVT i_1_0_1021( + .A1(registers_9__ap[16]), .A2(n_1_0_1291), .B1(n_1_0_1263), .B2(registers_7__ap[16]), + .ZN(n_1_0_972) + ); + SDFF_X1_LVT \registers_reg[10][16] ( + .CK(n_0_40), .D(registers[16]), .Q(registers_10__ap[16]), .QN(), .SE(dftIn), + .SI(registers_11__ap[16]) + ); + SDFF_X1_LVT \registers_reg[16][16] ( + .CK(n_0_46), .D(registers[16]), .Q(registers_16__ap[16]), .QN(), .SE(dftIn), + .SI(registers_10__ap[16]) + ); + AOI22_X1_LVT i_1_0_1020( + .A1(registers_10__ap[16]), .A2(n_1_0_1287), .B1(n_1_0_1267), .B2(registers_16__ap[16]), + .ZN(n_1_0_971) + ); + NAND3_X1_LVT i_1_0_1019( + .A1(n_1_0_974), .A2(n_1_0_972), .A3(n_1_0_971), .ZN(n_1_0_970) + ); + SDFF_X1_LVT \registers_reg[31][16] ( + .CK(n_0_61), .D(registers[16]), .Q(registers_31__ap[16]), .QN(), .SE(dftIn), + .SI(registers_7__ap[16]) + ); + SDFF_X1_LVT \registers_reg[6][16] ( + .CK(n_0_36), .D(registers[16]), .Q(registers_6__ap[16]), .QN(), .SE(dftIn), + .SI(registers_31__ap[16]) + ); + AOI221_X1_LVT i_1_0_1018( + .A(n_1_0_970), .B1(n_1_0_1266), .B2(registers_31__ap[16]), .C1(registers_6__ap[16]), + .C2(n_1_0_1300), .ZN(n_1_0_969) + ); + SDFF_X1_LVT \registers_reg[18][16] ( + .CK(n_0_48), .D(registers[16]), .Q(registers_18__ap[16]), .QN(), .SE(dftIn), + .SI(registers_23__ap[17]) + ); + SDFF_X1_LVT \registers_reg[22][16] ( + .CK(n_0_52), .D(registers[16]), .Q(registers_22__ap[16]), .QN(), .SE(dftIn), + .SI(registers_18__ap[16]) + ); + SDFF_X1_LVT \registers_reg[1][16] ( + .CK(n_0_0), .D(registers[16]), .Q(registers_1__ap[16]), .QN(), .SE(dftIn), + .SI(registers_22__ap[16]) + ); + AOI222_X1_LVT i_1_0_1017( + .A1(registers_18__ap[16]), .A2(n_1_0_1297), .B1(n_1_0_1294), .B2(registers_22__ap[16]), + .C1(registers_1__ap[16]), .C2(n_1_0_1274), .ZN(n_1_0_968) + ); + NAND3_X1_LVT i_1_0_1016( + .A1(n_1_0_973), .A2(n_1_0_969), .A3(n_1_0_968), .ZN(n_1_0_967) + ); + SDFF_X1_LVT \registers_reg[5][16] ( + .CK(n_0_35), .D(registers[16]), .Q(registers_5__ap[16]), .QN(), .SE(dftIn), + .SI(registers_6__ap[16]) + ); + SDFF_X1_LVT \registers_reg[28][16] ( + .CK(n_0_58), .D(registers[16]), .Q(registers_28__ap[16]), .QN(), .SE(dftIn), + .SI(registers_25__ap[16]) + ); + AOI221_X1_LVT i_1_0_1015( + .A(n_1_0_967), .B1(n_1_0_1273), .B2(registers_5__ap[16]), .C1(registers_28__ap[16]), + .C2(n_1_0_1283), .ZN(n_1_0_966) + ); + SDFF_X1_LVT \registers_reg[4][16] ( + .CK(n_0_34), .D(registers[16]), .Q(registers_4__ap[16]), .QN(), .SE(dftIn), + .SI(registers_5__ap[16]) + ); + SDFF_X1_LVT \registers_reg[12][16] ( + .CK(n_0_42), .D(registers[16]), .Q(registers_12__ap[16]), .QN(), .SE(dftIn), + .SI(registers_16__ap[16]) + ); + AOI22_X1_LVT i_1_0_1014( + .A1(registers_4__ap[16]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[16]), + .ZN(n_1_0_965) + ); + SDFF_X1_LVT \registers_reg[19][16] ( + .CK(n_0_49), .D(registers[16]), .Q(registers_19__ap[16]), .QN(), .SE(dftIn), + .SI(registers_1__ap[16]) + ); + SDFF_X1_LVT \registers_reg[21][16] ( + .CK(n_0_51), .D(registers[16]), .Q(registers_21__ap[16]), .QN(), .SE(dftIn), + .SI(registers_19__ap[16]) + ); + AOI22_X1_LVT i_1_0_1013( + .A1(registers_19__ap[16]), .A2(n_1_0_1295), .B1(n_1_0_1259), .B2(registers_21__ap[16]), + .ZN(n_1_0_964) + ); + SDFF_X1_LVT \registers_reg[24][16] ( + .CK(n_0_54), .D(registers[16]), .Q(registers_24__ap[16]), .QN(), .SE(dftIn), + .SI(registers_28__ap[16]) + ); + SDFF_X1_LVT \registers_reg[20][16] ( + .CK(n_0_50), .D(registers[16]), .Q(registers_20__ap[16]), .QN(), .SE(dftIn), + .SI(registers_21__ap[16]) + ); + AOI22_X1_LVT i_1_0_1012( + .A1(registers_24__ap[16]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[16]), + .ZN(n_1_0_963) + ); + NAND3_X1_LVT i_1_0_1011( + .A1(n_1_0_965), .A2(n_1_0_964), .A3(n_1_0_963), .ZN(n_1_0_962) + ); + SDFF_X1_LVT \registers_reg[26][16] ( + .CK(n_0_56), .D(registers[16]), .Q(registers_26__ap[16]), .QN(), .SE(dftIn), + .SI(registers_24__ap[16]) + ); + SDFF_X1_LVT \registers_reg[30][16] ( + .CK(n_0_60), .D(registers[16]), .Q(registers_30__ap[16]), .QN(), .SE(dftIn), + .SI(registers_26__ap[16]) + ); + AOI221_X1_LVT i_1_0_1010( + .A(n_1_0_962), .B1(n_1_0_1285), .B2(registers_26__ap[16]), .C1(registers_30__ap[16]), + .C2(n_1_0_1272), .ZN(n_1_0_961) + ); + SDFF_X1_LVT \registers_reg[8][16] ( + .CK(n_0_38), .D(registers[16]), .Q(registers_8__ap[16]), .QN(), .SE(dftIn), + .SI(registers_4__ap[16]) + ); + SDFF_X1_LVT \registers_reg[23][16] ( + .CK(n_0_53), .D(registers[16]), .Q(registers_23__ap[16]), .QN(), .SE(dftIn), + .SI(registers_20__ap[16]) + ); + AOI22_X1_LVT i_1_0_1009( + .A1(registers_8__ap[16]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[16]), + .ZN(n_1_0_960) + ); + SDFF_X1_LVT \registers_reg[13][16] ( + .CK(n_0_43), .D(registers[16]), .Q(registers_13__ap[16]), .QN(), .SE(dftIn), + .SI(registers_12__ap[16]) + ); + SDFF_X1_LVT \registers_reg[17][16] ( + .CK(n_0_47), .D(registers[16]), .Q(registers_17__ap[16]), .QN(), .SE(dftIn), + .SI(registers_23__ap[16]) + ); + AOI22_X1_LVT i_1_0_1008( + .A1(registers_13__ap[16]), .A2(n_1_0_1277), .B1(n_1_0_1271), .B2(registers_17__ap[16]), + .ZN(n_1_0_959) + ); + SDFF_X1_LVT \registers_reg[15][16] ( + .CK(n_0_45), .D(registers[16]), .Q(registers_15__ap[16]), .QN(), .SE(dftIn), + .SI(registers_13__ap[16]) + ); + SDFF_X1_LVT \registers_reg[14][16] ( + .CK(n_0_44), .D(registers[16]), .Q(registers_14__ap[16]), .QN(), .SE(dftIn), + .SI(registers_15__ap[16]) + ); + AOI22_X1_LVT i_1_0_1007( + .A1(registers_15__ap[16]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[16]), + .ZN(n_1_0_958) + ); + NAND3_X1_LVT i_1_0_1006( + .A1(n_1_0_960), .A2(n_1_0_959), .A3(n_1_0_958), .ZN(n_1_0_957) + ); + SDFF_X1_LVT \registers_reg[27][16] ( + .CK(n_0_57), .D(registers[16]), .Q(registers_27__ap[16]), .QN(), .SE(dftIn), + .SI(registers_30__ap[16]) + ); + SDFF_X1_LVT \registers_reg[3][16] ( + .CK(n_0_33), .D(registers[16]), .Q(registers_3__ap[16]), .QN(), .SE(dftIn), + .SI(registers_8__ap[16]) + ); + AOI221_X1_LVT i_1_0_1005( + .A(n_1_0_957), .B1(n_1_0_1279), .B2(registers_27__ap[16]), .C1(registers_3__ap[16]), + .C2(n_1_0_1257), .ZN(n_1_0_956) + ); + NAND3_X1_LVT i_1_0_1004( + .A1(n_1_0_966), .A2(n_1_0_961), .A3(n_1_0_956), .ZN(RRs1[16]) + ); + AND2_X1_LVT i_0_0_15( + .A1(n_0_0_16), .A2(WRd[15]), .ZN(registers[15]) + ); + SDFF_X1_LVT \registers_reg[17][15] ( + .CK(n_0_47), .D(registers[15]), .Q(registers_17__ap[15]), .QN(), .SE(dftIn), + .SI(registers_17__ap[16]) + ); + SDFF_X1_LVT \registers_reg[21][15] ( + .CK(n_0_51), .D(registers[15]), .Q(registers_21__ap[15]), .QN(), .SE(dftIn), + .SI(registers_17__ap[15]) + ); + AOI22_X1_LVT i_1_0_1000( + .A1(registers_17__ap[15]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[15]), + .ZN(n_1_0_952) + ); + SDFF_X1_LVT \registers_reg[10][15] ( + .CK(n_0_40), .D(registers[15]), .Q(registers_10__ap[15]), .QN(), .SE(dftIn), + .SI(registers_14__ap[16]) + ); + SDFF_X1_LVT \registers_reg[2][15] ( + .CK(n_0_32), .D(registers[15]), .Q(registers_2__ap[15]), .QN(), .SE(dftIn), + .SI(registers_27__ap[16]) + ); + AOI22_X1_LVT i_1_0_1003( + .A1(registers_10__ap[15]), .A2(n_1_0_1287), .B1(n_1_0_1268), .B2(registers_2__ap[15]), + .ZN(n_1_0_955) + ); + SDFF_X1_LVT \registers_reg[20][15] ( + .CK(n_0_50), .D(registers[15]), .Q(registers_20__ap[15]), .QN(), .SE(dftIn), + .SI(registers_21__ap[15]) + ); + SDFF_X1_LVT \registers_reg[12][15] ( + .CK(n_0_42), .D(registers[15]), .Q(registers_12__ap[15]), .QN(), .SE(dftIn), + .SI(registers_10__ap[15]) + ); + AOI22_X1_LVT i_1_0_999( + .A1(registers_20__ap[15]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[15]), + .ZN(n_1_0_951) + ); + SDFF_X1_LVT \registers_reg[15][15] ( + .CK(n_0_45), .D(registers[15]), .Q(registers_15__ap[15]), .QN(), .SE(dftIn), + .SI(registers_12__ap[15]) + ); + SDFF_X1_LVT \registers_reg[8][15] ( + .CK(n_0_38), .D(registers[15]), .Q(registers_8__ap[15]), .QN(), .SE(dftIn), + .SI(registers_3__ap[16]) + ); + AOI22_X1_LVT i_1_0_1002( + .A1(registers_15__ap[15]), .A2(n_1_0_1286), .B1(n_1_0_1282), .B2(registers_8__ap[15]), + .ZN(n_1_0_954) + ); + INV_X1_LVT i_1_0_1001( + .A(n_1_0_954), .ZN(n_1_0_953) + ); + SDFF_X1_LVT \registers_reg[11][15] ( + .CK(n_0_41), .D(registers[15]), .Q(registers_11__ap[15]), .QN(), .SE(dftIn), + .SI(registers_15__ap[15]) + ); + SDFF_X1_LVT \registers_reg[24][15] ( + .CK(n_0_54), .D(registers[15]), .Q(registers_24__ap[15]), .QN(), .SE(dftIn), + .SI(registers_2__ap[15]) + ); + AOI221_X1_LVT i_1_0_998( + .A(n_1_0_953), .B1(n_1_0_1270), .B2(registers_11__ap[15]), .C1(registers_24__ap[15]), + .C2(n_1_0_1289), .ZN(n_1_0_950) + ); + SDFF_X1_LVT \registers_reg[13][15] ( + .CK(n_0_43), .D(registers[15]), .Q(registers_13__ap[15]), .QN(), .SE(dftIn), + .SI(registers_11__ap[15]) + ); + SDFF_X1_LVT \registers_reg[30][15] ( + .CK(n_0_60), .D(registers[15]), .Q(registers_30__ap[15]), .QN(), .SE(dftIn), + .SI(registers_24__ap[15]) + ); + SDFF_X1_LVT \registers_reg[22][15] ( + .CK(n_0_52), .D(registers[15]), .Q(registers_22__ap[15]), .QN(), .SE(dftIn), + .SI(registers_20__ap[15]) + ); + AOI222_X1_LVT i_1_0_997( + .A1(registers_13__ap[15]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[15]), + .C1(registers_22__ap[15]), .C2(n_1_0_1294), .ZN(n_1_0_949) + ); + NAND4_X1_LVT i_1_0_996( + .A1(n_1_0_955), .A2(n_1_0_951), .A3(n_1_0_950), .A4(n_1_0_949), .ZN(n_1_0_948) + ); + SDFF_X1_LVT \registers_reg[1][15] ( + .CK(n_0_0), .D(registers[15]), .Q(registers_1__ap[15]), .QN(), .SE(dftIn), + .SI(registers_22__ap[15]) + ); + SDFF_X1_LVT \registers_reg[28][15] ( + .CK(n_0_58), .D(registers[15]), .Q(registers_28__ap[15]), .QN(), .SE(dftIn), + .SI(registers_30__ap[15]) + ); + AOI221_X1_LVT i_1_0_995( + .A(n_1_0_948), .B1(n_1_0_1274), .B2(registers_1__ap[15]), .C1(registers_28__ap[15]), + .C2(n_1_0_1283), .ZN(n_1_0_947) + ); + SDFF_X1_LVT \registers_reg[18][15] ( + .CK(n_0_48), .D(registers[15]), .Q(registers_18__ap[15]), .QN(), .SE(dftIn), + .SI(registers_1__ap[15]) + ); + SDFF_X1_LVT \registers_reg[26][15] ( + .CK(n_0_56), .D(registers[15]), .Q(registers_26__ap[15]), .QN(), .SE(dftIn), + .SI(registers_28__ap[15]) + ); + AOI22_X1_LVT i_1_0_994( + .A1(registers_18__ap[15]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[15]), + .ZN(n_1_0_946) + ); + SDFF_X1_LVT \registers_reg[4][15] ( + .CK(n_0_34), .D(registers[15]), .Q(registers_4__ap[15]), .QN(), .SE(dftIn), + .SI(registers_8__ap[15]) + ); + SDFF_X1_LVT \registers_reg[5][15] ( + .CK(n_0_35), .D(registers[15]), .Q(registers_5__ap[15]), .QN(), .SE(dftIn), + .SI(registers_4__ap[15]) + ); + AOI22_X1_LVT i_1_0_993( + .A1(registers_4__ap[15]), .A2(n_1_0_1278), .B1(n_1_0_1273), .B2(registers_5__ap[15]), + .ZN(n_1_0_945) + ); + SDFF_X1_LVT \registers_reg[6][15] ( + .CK(n_0_36), .D(registers[15]), .Q(registers_6__ap[15]), .QN(), .SE(dftIn), + .SI(registers_5__ap[15]) + ); + SDFF_X1_LVT \registers_reg[16][15] ( + .CK(n_0_46), .D(registers[15]), .Q(registers_16__ap[15]), .QN(), .SE(dftIn), + .SI(registers_13__ap[15]) + ); + AOI22_X1_LVT i_1_0_992( + .A1(registers_6__ap[15]), .A2(n_1_0_1300), .B1(n_1_0_1267), .B2(registers_16__ap[15]), + .ZN(n_1_0_944) + ); + NAND3_X1_LVT i_1_0_991( + .A1(n_1_0_946), .A2(n_1_0_945), .A3(n_1_0_944), .ZN(n_1_0_943) + ); + SDFF_X1_LVT \registers_reg[19][15] ( + .CK(n_0_49), .D(registers[15]), .Q(registers_19__ap[15]), .QN(), .SE(dftIn), + .SI(registers_18__ap[15]) + ); + SDFF_X1_LVT \registers_reg[25][15] ( + .CK(n_0_55), .D(registers[15]), .Q(registers_25__ap[15]), .QN(), .SE(dftIn), + .SI(registers_26__ap[15]) + ); + AOI221_X1_LVT i_1_0_990( + .A(n_1_0_943), .B1(n_1_0_1295), .B2(registers_19__ap[15]), .C1(registers_25__ap[15]), + .C2(n_1_0_1269), .ZN(n_1_0_942) + ); + SDFF_X1_LVT \registers_reg[7][15] ( + .CK(n_0_37), .D(registers[15]), .Q(registers_7__ap[15]), .QN(), .SE(dftIn), + .SI(registers_6__ap[15]) + ); + SDFF_X1_LVT \registers_reg[14][15] ( + .CK(n_0_44), .D(registers[15]), .Q(registers_14__ap[15]), .QN(), .SE(dftIn), + .SI(registers_16__ap[15]) + ); + AOI22_X1_LVT i_1_0_989( + .A1(registers_7__ap[15]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[15]), + .ZN(n_1_0_941) + ); + SDFF_X1_LVT \registers_reg[9][15] ( + .CK(n_0_39), .D(registers[15]), .Q(registers_9__ap[15]), .QN(), .SE(dftIn), + .SI(registers_7__ap[15]) + ); + SDFF_X1_LVT \registers_reg[29][15] ( + .CK(n_0_59), .D(registers[15]), .Q(registers_29__ap[15]), .QN(), .SE(dftIn), + .SI(registers_25__ap[15]) + ); + AOI22_X1_LVT i_1_0_988( + .A1(registers_9__ap[15]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[15]), + .ZN(n_1_0_940) + ); + SDFF_X1_LVT \registers_reg[23][15] ( + .CK(n_0_53), .D(registers[15]), .Q(registers_23__ap[15]), .QN(), .SE(dftIn), + .SI(registers_19__ap[15]) + ); + SDFF_X1_LVT \registers_reg[3][15] ( + .CK(n_0_33), .D(registers[15]), .Q(registers_3__ap[15]), .QN(), .SE(dftIn), + .SI(registers_9__ap[15]) + ); + AOI22_X1_LVT i_1_0_987( + .A1(registers_23__ap[15]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[15]), + .ZN(n_1_0_939) + ); + NAND3_X1_LVT i_1_0_986( + .A1(n_1_0_941), .A2(n_1_0_940), .A3(n_1_0_939), .ZN(n_1_0_938) + ); + SDFF_X1_LVT \registers_reg[27][15] ( + .CK(n_0_57), .D(registers[15]), .Q(registers_27__ap[15]), .QN(), .SE(dftIn), + .SI(registers_29__ap[15]) + ); + SDFF_X1_LVT \registers_reg[31][15] ( + .CK(n_0_61), .D(registers[15]), .Q(registers_31__ap[15]), .QN(), .SE(dftIn), + .SI(registers_3__ap[15]) + ); + AOI221_X1_LVT i_1_0_985( + .A(n_1_0_938), .B1(n_1_0_1279), .B2(registers_27__ap[15]), .C1(registers_31__ap[15]), + .C2(n_1_0_1266), .ZN(n_1_0_937) + ); + NAND4_X1_LVT i_1_0_984( + .A1(n_1_0_952), .A2(n_1_0_947), .A3(n_1_0_942), .A4(n_1_0_937), .ZN(RRs1[15]) + ); + AND2_X1_LVT i_0_0_14( + .A1(n_0_0_16), .A2(WRd[14]), .ZN(registers[14]) + ); + SDFF_X1_LVT \registers_reg[28][14] ( + .CK(n_0_58), .D(registers[14]), .Q(registers_28__ap[14]), .QN(), .SE(dftIn), + .SI(registers_27__ap[15]) + ); + SDFF_X1_LVT \registers_reg[5][14] ( + .CK(n_0_35), .D(registers[14]), .Q(registers_5__ap[14]), .QN(), .SE(dftIn), + .SI(registers_31__ap[15]) + ); + AOI22_X1_LVT i_1_0_983( + .A1(registers_28__ap[14]), .A2(n_1_0_1283), .B1(n_1_0_1273), .B2(registers_5__ap[14]), + .ZN(n_1_0_936) + ); + SDFF_X1_LVT \registers_reg[18][14] ( + .CK(n_0_48), .D(registers[14]), .Q(registers_18__ap[14]), .QN(), .SE(dftIn), + .SI(registers_23__ap[15]) + ); + SDFF_X1_LVT \registers_reg[10][14] ( + .CK(n_0_40), .D(registers[14]), .Q(registers_10__ap[14]), .QN(), .SE(dftIn), + .SI(registers_14__ap[15]) + ); + SDFF_X1_LVT \registers_reg[8][14] ( + .CK(n_0_38), .D(registers[14]), .Q(registers_8__ap[14]), .QN(), .SE(dftIn), + .SI(registers_5__ap[14]) + ); + AOI222_X1_LVT i_1_0_982( + .A1(registers_18__ap[14]), .A2(n_1_0_1297), .B1(n_1_0_1287), .B2(registers_10__ap[14]), + .C1(n_1_0_1282), .C2(registers_8__ap[14]), .ZN(n_1_0_935) + ); + SDFF_X1_LVT \registers_reg[9][14] ( + .CK(n_0_39), .D(registers[14]), .Q(registers_9__ap[14]), .QN(), .SE(dftIn), + .SI(registers_8__ap[14]) + ); + SDFF_X1_LVT \registers_reg[29][14] ( + .CK(n_0_59), .D(registers[14]), .Q(registers_29__ap[14]), .QN(), .SE(dftIn), + .SI(registers_28__ap[14]) + ); + AOI22_X1_LVT i_1_0_981( + .A1(registers_9__ap[14]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[14]), + .ZN(n_1_0_934) + ); + SDFF_X1_LVT \registers_reg[21][14] ( + .CK(n_0_51), .D(registers[14]), .Q(registers_21__ap[14]), .QN(), .SE(dftIn), + .SI(registers_18__ap[14]) + ); + SDFF_X1_LVT \registers_reg[14][14] ( + .CK(n_0_44), .D(registers[14]), .Q(registers_14__ap[14]), .QN(), .SE(dftIn), + .SI(registers_10__ap[14]) + ); + AOI22_X1_LVT i_1_0_980( + .A1(registers_21__ap[14]), .A2(n_1_0_1259), .B1(n_1_0_1258), .B2(registers_14__ap[14]), + .ZN(n_1_0_933) + ); + SDFF_X1_LVT \registers_reg[16][14] ( + .CK(n_0_46), .D(registers[14]), .Q(registers_16__ap[14]), .QN(), .SE(dftIn), + .SI(registers_14__ap[14]) + ); + SDFF_X1_LVT \registers_reg[3][14] ( + .CK(n_0_33), .D(registers[14]), .Q(registers_3__ap[14]), .QN(), .SE(dftIn), + .SI(registers_9__ap[14]) + ); + AOI22_X1_LVT i_1_0_979( + .A1(registers_16__ap[14]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[14]), + .ZN(n_1_0_932) + ); + SDFF_X1_LVT \registers_reg[17][14] ( + .CK(n_0_47), .D(registers[14]), .Q(registers_17__ap[14]), .QN(), .SE(dftIn), + .SI(registers_21__ap[14]) + ); + SDFF_X1_LVT \registers_reg[31][14] ( + .CK(n_0_61), .D(registers[14]), .Q(registers_31__ap[14]), .QN(), .SE(dftIn), + .SI(registers_3__ap[14]) + ); + AOI22_X1_LVT i_1_0_978( + .A1(registers_17__ap[14]), .A2(n_1_0_1271), .B1(n_1_0_1266), .B2(registers_31__ap[14]), + .ZN(n_1_0_931) + ); + SDFF_X1_LVT \registers_reg[15][14] ( + .CK(n_0_45), .D(registers[14]), .Q(registers_15__ap[14]), .QN(), .SE(dftIn), + .SI(registers_16__ap[14]) + ); + SDFF_X1_LVT \registers_reg[23][14] ( + .CK(n_0_53), .D(registers[14]), .Q(registers_23__ap[14]), .QN(), .SE(dftIn), + .SI(registers_17__ap[14]) + ); + AOI22_X1_LVT i_1_0_977( + .A1(registers_15__ap[14]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[14]), + .ZN(n_1_0_930) + ); + NAND4_X1_LVT i_1_0_976( + .A1(n_1_0_933), .A2(n_1_0_932), .A3(n_1_0_931), .A4(n_1_0_930), .ZN(n_1_0_929) + ); + SDFF_X1_LVT \registers_reg[26][14] ( + .CK(n_0_56), .D(registers[14]), .Q(registers_26__ap[14]), .QN(), .SE(dftIn), + .SI(registers_29__ap[14]) + ); + SDFF_X1_LVT \registers_reg[30][14] ( + .CK(n_0_60), .D(registers[14]), .Q(registers_30__ap[14]), .QN(), .SE(dftIn), + .SI(registers_26__ap[14]) + ); + AOI22_X1_LVT i_1_0_975( + .A1(registers_26__ap[14]), .A2(n_1_0_1285), .B1(n_1_0_1272), .B2(registers_30__ap[14]), + .ZN(n_1_0_928) + ); + SDFF_X1_LVT \registers_reg[20][14] ( + .CK(n_0_50), .D(registers[14]), .Q(registers_20__ap[14]), .QN(), .SE(dftIn), + .SI(registers_23__ap[14]) + ); + SDFF_X1_LVT \registers_reg[4][14] ( + .CK(n_0_34), .D(registers[14]), .Q(registers_4__ap[14]), .QN(), .SE(dftIn), + .SI(registers_31__ap[14]) + ); + AOI22_X1_LVT i_1_0_974( + .A1(registers_20__ap[14]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[14]), + .ZN(n_1_0_927) + ); + SDFF_X1_LVT \registers_reg[1][14] ( + .CK(n_0_0), .D(registers[14]), .Q(registers_1__ap[14]), .QN(), .SE(dftIn), + .SI(registers_20__ap[14]) + ); + SDFF_X1_LVT \registers_reg[2][14] ( + .CK(n_0_32), .D(registers[14]), .Q(registers_2__ap[14]), .QN(), .SE(dftIn), + .SI(registers_30__ap[14]) + ); + AOI22_X1_LVT i_1_0_973( + .A1(registers_1__ap[14]), .A2(n_1_0_1274), .B1(n_1_0_1268), .B2(registers_2__ap[14]), + .ZN(n_1_0_926) + ); + SDFF_X1_LVT \registers_reg[24][14] ( + .CK(n_0_54), .D(registers[14]), .Q(registers_24__ap[14]), .QN(), .SE(dftIn), + .SI(registers_2__ap[14]) + ); + SDFF_X1_LVT \registers_reg[12][14] ( + .CK(n_0_42), .D(registers[14]), .Q(registers_12__ap[14]), .QN(), .SE(dftIn), + .SI(registers_15__ap[14]) + ); + AOI22_X1_LVT i_1_0_972( + .A1(registers_24__ap[14]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[14]), + .ZN(n_1_0_925) + ); + NAND4_X1_LVT i_1_0_971( + .A1(n_1_0_928), .A2(n_1_0_927), .A3(n_1_0_926), .A4(n_1_0_925), .ZN(n_1_0_924) + ); + SDFF_X1_LVT \registers_reg[19][14] ( + .CK(n_0_49), .D(registers[14]), .Q(registers_19__ap[14]), .QN(), .SE(dftIn), + .SI(registers_1__ap[14]) + ); + SDFF_X1_LVT \registers_reg[22][14] ( + .CK(n_0_52), .D(registers[14]), .Q(registers_22__ap[14]), .QN(), .SE(dftIn), + .SI(registers_19__ap[14]) + ); + AOI22_X1_LVT i_1_0_970( + .A1(registers_19__ap[14]), .A2(n_1_0_1295), .B1(n_1_0_1294), .B2(registers_22__ap[14]), + .ZN(n_1_0_923) + ); + SDFF_X1_LVT \registers_reg[13][14] ( + .CK(n_0_43), .D(registers[14]), .Q(registers_13__ap[14]), .QN(), .SE(dftIn), + .SI(registers_12__ap[14]) + ); + SDFF_X1_LVT \registers_reg[25][14] ( + .CK(n_0_55), .D(registers[14]), .Q(registers_25__ap[14]), .QN(), .SE(dftIn), + .SI(registers_24__ap[14]) + ); + AOI22_X1_LVT i_1_0_969( + .A1(registers_13__ap[14]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[14]), + .ZN(n_1_0_922) + ); + SDFF_X1_LVT \registers_reg[6][14] ( + .CK(n_0_36), .D(registers[14]), .Q(registers_6__ap[14]), .QN(), .SE(dftIn), + .SI(registers_4__ap[14]) + ); + SDFF_X1_LVT \registers_reg[7][14] ( + .CK(n_0_37), .D(registers[14]), .Q(registers_7__ap[14]), .QN(), .SE(dftIn), + .SI(registers_6__ap[14]) + ); + AOI22_X1_LVT i_1_0_968( + .A1(registers_6__ap[14]), .A2(n_1_0_1300), .B1(n_1_0_1263), .B2(registers_7__ap[14]), + .ZN(n_1_0_921) + ); + SDFF_X1_LVT \registers_reg[27][14] ( + .CK(n_0_57), .D(registers[14]), .Q(registers_27__ap[14]), .QN(), .SE(dftIn), + .SI(registers_25__ap[14]) + ); + SDFF_X1_LVT \registers_reg[11][14] ( + .CK(n_0_41), .D(registers[14]), .Q(registers_11__ap[14]), .QN(), .SE(dftIn), + .SI(registers_13__ap[14]) + ); + AOI22_X1_LVT i_1_0_967( + .A1(registers_27__ap[14]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[14]), + .ZN(n_1_0_920) + ); + NAND4_X1_LVT i_1_0_966( + .A1(n_1_0_923), .A2(n_1_0_922), .A3(n_1_0_921), .A4(n_1_0_920), .ZN(n_1_0_919) + ); + NOR3_X1_LVT i_1_0_965( + .A1(n_1_0_929), .A2(n_1_0_924), .A3(n_1_0_919), .ZN(n_1_0_918) + ); + NAND4_X1_LVT i_1_0_964( + .A1(n_1_0_936), .A2(n_1_0_935), .A3(n_1_0_934), .A4(n_1_0_918), .ZN(RRs1[14]) + ); + AND2_X1_LVT i_0_0_13( + .A1(n_0_0_16), .A2(WRd[13]), .ZN(registers[13]) + ); + SDFF_X1_LVT \registers_reg[28][13] ( + .CK(n_0_58), .D(registers[13]), .Q(registers_28__ap[13]), .QN(), .SE(dftIn), + .SI(registers_27__ap[14]) + ); + SDFF_X1_LVT \registers_reg[4][13] ( + .CK(n_0_34), .D(registers[13]), .Q(registers_4__ap[13]), .QN(), .SE(dftIn), + .SI(registers_7__ap[14]) + ); + AOI22_X1_LVT i_1_0_963( + .A1(registers_28__ap[13]), .A2(n_1_0_1283), .B1(n_1_0_1278), .B2(registers_4__ap[13]), + .ZN(n_1_0_917) + ); + SDFF_X1_LVT \registers_reg[10][13] ( + .CK(n_0_40), .D(registers[13]), .Q(registers_10__ap[13]), .QN(), .SE(dftIn), + .SI(registers_11__ap[14]) + ); + SDFF_X1_LVT \registers_reg[26][13] ( + .CK(n_0_56), .D(registers[13]), .Q(registers_26__ap[13]), .QN(), .SE(dftIn), + .SI(registers_28__ap[13]) + ); + SDFF_X1_LVT \registers_reg[8][13] ( + .CK(n_0_38), .D(registers[13]), .Q(registers_8__ap[13]), .QN(), .SE(dftIn), + .SI(registers_4__ap[13]) + ); + AOI222_X1_LVT i_1_0_962( + .A1(registers_10__ap[13]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[13]), + .C1(registers_8__ap[13]), .C2(n_1_0_1282), .ZN(n_1_0_916) + ); + SDFF_X1_LVT \registers_reg[9][13] ( + .CK(n_0_39), .D(registers[13]), .Q(registers_9__ap[13]), .QN(), .SE(dftIn), + .SI(registers_8__ap[13]) + ); + SDFF_X1_LVT \registers_reg[29][13] ( + .CK(n_0_59), .D(registers[13]), .Q(registers_29__ap[13]), .QN(), .SE(dftIn), + .SI(registers_26__ap[13]) + ); + AOI22_X1_LVT i_1_0_961( + .A1(registers_9__ap[13]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[13]), + .ZN(n_1_0_915) + ); + SDFF_X1_LVT \registers_reg[6][13] ( + .CK(n_0_36), .D(registers[13]), .Q(registers_6__ap[13]), .QN(), .SE(dftIn), + .SI(registers_9__ap[13]) + ); + SDFF_X1_LVT \registers_reg[1][13] ( + .CK(n_0_0), .D(registers[13]), .Q(registers_1__ap[13]), .QN(), .SE(dftIn), + .SI(registers_22__ap[14]) + ); + AOI22_X1_LVT i_1_0_960( + .A1(registers_6__ap[13]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[13]), + .ZN(n_1_0_914) + ); + SDFF_X1_LVT \registers_reg[5][13] ( + .CK(n_0_35), .D(registers[13]), .Q(registers_5__ap[13]), .QN(), .SE(dftIn), + .SI(registers_6__ap[13]) + ); + SDFF_X1_LVT \registers_reg[3][13] ( + .CK(n_0_33), .D(registers[13]), .Q(registers_3__ap[13]), .QN(), .SE(dftIn), + .SI(registers_5__ap[13]) + ); + AOI22_X1_LVT i_1_0_959( + .A1(registers_5__ap[13]), .A2(n_1_0_1273), .B1(n_1_0_1257), .B2(registers_3__ap[13]), + .ZN(n_1_0_913) + ); + SDFF_X1_LVT \registers_reg[16][13] ( + .CK(n_0_46), .D(registers[13]), .Q(registers_16__ap[13]), .QN(), .SE(dftIn), + .SI(registers_10__ap[13]) + ); + SDFF_X1_LVT \registers_reg[31][13] ( + .CK(n_0_61), .D(registers[13]), .Q(registers_31__ap[13]), .QN(), .SE(dftIn), + .SI(registers_3__ap[13]) + ); + AOI22_X1_LVT i_1_0_958( + .A1(registers_16__ap[13]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[13]), + .ZN(n_1_0_912) + ); + SDFF_X1_LVT \registers_reg[15][13] ( + .CK(n_0_45), .D(registers[13]), .Q(registers_15__ap[13]), .QN(), .SE(dftIn), + .SI(registers_16__ap[13]) + ); + SDFF_X1_LVT \registers_reg[23][13] ( + .CK(n_0_53), .D(registers[13]), .Q(registers_23__ap[13]), .QN(), .SE(dftIn), + .SI(registers_1__ap[13]) + ); + AOI22_X1_LVT i_1_0_957( + .A1(registers_15__ap[13]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[13]), + .ZN(n_1_0_911) + ); + NAND4_X1_LVT i_1_0_956( + .A1(n_1_0_914), .A2(n_1_0_913), .A3(n_1_0_912), .A4(n_1_0_911), .ZN(n_1_0_910) + ); + SDFF_X1_LVT \registers_reg[18][13] ( + .CK(n_0_48), .D(registers[13]), .Q(registers_18__ap[13]), .QN(), .SE(dftIn), + .SI(registers_23__ap[13]) + ); + SDFF_X1_LVT \registers_reg[30][13] ( + .CK(n_0_60), .D(registers[13]), .Q(registers_30__ap[13]), .QN(), .SE(dftIn), + .SI(registers_29__ap[13]) + ); + AOI22_X1_LVT i_1_0_955( + .A1(registers_18__ap[13]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[13]), + .ZN(n_1_0_909) + ); + SDFF_X1_LVT \registers_reg[24][13] ( + .CK(n_0_54), .D(registers[13]), .Q(registers_24__ap[13]), .QN(), .SE(dftIn), + .SI(registers_30__ap[13]) + ); + SDFF_X1_LVT \registers_reg[12][13] ( + .CK(n_0_42), .D(registers[13]), .Q(registers_12__ap[13]), .QN(), .SE(dftIn), + .SI(registers_15__ap[13]) + ); + AOI22_X1_LVT i_1_0_954( + .A1(registers_24__ap[13]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[13]), + .ZN(n_1_0_908) + ); + SDFF_X1_LVT \registers_reg[22][13] ( + .CK(n_0_52), .D(registers[13]), .Q(registers_22__ap[13]), .QN(), .SE(dftIn), + .SI(registers_18__ap[13]) + ); + SDFF_X1_LVT \registers_reg[21][13] ( + .CK(n_0_51), .D(registers[13]), .Q(registers_21__ap[13]), .QN(), .SE(dftIn), + .SI(registers_22__ap[13]) + ); + AOI22_X1_LVT i_1_0_953( + .A1(registers_22__ap[13]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[13]), + .ZN(n_1_0_907) + ); + SDFF_X1_LVT \registers_reg[20][13] ( + .CK(n_0_50), .D(registers[13]), .Q(registers_20__ap[13]), .QN(), .SE(dftIn), + .SI(registers_21__ap[13]) + ); + SDFF_X1_LVT \registers_reg[17][13] ( + .CK(n_0_47), .D(registers[13]), .Q(registers_17__ap[13]), .QN(), .SE(dftIn), + .SI(registers_20__ap[13]) + ); + AOI22_X1_LVT i_1_0_952( + .A1(registers_20__ap[13]), .A2(n_1_0_1281), .B1(n_1_0_1271), .B2(registers_17__ap[13]), + .ZN(n_1_0_906) + ); + NAND4_X1_LVT i_1_0_951( + .A1(n_1_0_909), .A2(n_1_0_908), .A3(n_1_0_907), .A4(n_1_0_906), .ZN(n_1_0_905) + ); + SDFF_X1_LVT \registers_reg[13][13] ( + .CK(n_0_43), .D(registers[13]), .Q(registers_13__ap[13]), .QN(), .SE(dftIn), + .SI(registers_12__ap[13]) + ); + SDFF_X1_LVT \registers_reg[25][13] ( + .CK(n_0_55), .D(registers[13]), .Q(registers_25__ap[13]), .QN(), .SE(dftIn), + .SI(registers_24__ap[13]) + ); + AOI22_X1_LVT i_1_0_950( + .A1(registers_13__ap[13]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[13]), + .ZN(n_1_0_904) + ); + SDFF_X1_LVT \registers_reg[19][13] ( + .CK(n_0_49), .D(registers[13]), .Q(registers_19__ap[13]), .QN(), .SE(dftIn), + .SI(registers_17__ap[13]) + ); + SDFF_X1_LVT \registers_reg[2][13] ( + .CK(n_0_32), .D(registers[13]), .Q(registers_2__ap[13]), .QN(), .SE(dftIn), + .SI(registers_25__ap[13]) + ); + AOI22_X1_LVT i_1_0_949( + .A1(registers_19__ap[13]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[13]), + .ZN(n_1_0_903) + ); + SDFF_X1_LVT \registers_reg[7][13] ( + .CK(n_0_37), .D(registers[13]), .Q(registers_7__ap[13]), .QN(), .SE(dftIn), + .SI(registers_31__ap[13]) + ); + SDFF_X1_LVT \registers_reg[14][13] ( + .CK(n_0_44), .D(registers[13]), .Q(registers_14__ap[13]), .QN(), .SE(dftIn), + .SI(registers_13__ap[13]) + ); + AOI22_X1_LVT i_1_0_948( + .A1(registers_7__ap[13]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[13]), + .ZN(n_1_0_902) + ); + SDFF_X1_LVT \registers_reg[27][13] ( + .CK(n_0_57), .D(registers[13]), .Q(registers_27__ap[13]), .QN(), .SE(dftIn), + .SI(registers_2__ap[13]) + ); + SDFF_X1_LVT \registers_reg[11][13] ( + .CK(n_0_41), .D(registers[13]), .Q(registers_11__ap[13]), .QN(), .SE(dftIn), + .SI(registers_14__ap[13]) + ); + AOI22_X1_LVT i_1_0_947( + .A1(registers_27__ap[13]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[13]), + .ZN(n_1_0_901) + ); + NAND4_X1_LVT i_1_0_946( + .A1(n_1_0_904), .A2(n_1_0_903), .A3(n_1_0_902), .A4(n_1_0_901), .ZN(n_1_0_900) + ); + NOR3_X1_LVT i_1_0_945( + .A1(n_1_0_910), .A2(n_1_0_905), .A3(n_1_0_900), .ZN(n_1_0_899) + ); + NAND4_X1_LVT i_1_0_944( + .A1(n_1_0_917), .A2(n_1_0_916), .A3(n_1_0_915), .A4(n_1_0_899), .ZN(RRs1[13]) + ); + AND2_X1_LVT i_0_0_12( + .A1(n_0_0_16), .A2(WRd[12]), .ZN(registers[12]) + ); + SDFF_X1_LVT \registers_reg[28][12] ( + .CK(n_0_58), .D(registers[12]), .Q(registers_28__ap[12]), .QN(), .SE(dftIn), + .SI(registers_27__ap[13]) + ); + SDFF_X1_LVT \registers_reg[17][12] ( + .CK(n_0_47), .D(registers[12]), .Q(registers_17__ap[12]), .QN(), .SE(dftIn), + .SI(registers_19__ap[13]) + ); + AOI22_X1_LVT i_1_0_943( + .A1(registers_28__ap[12]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[12]), + .ZN(n_1_0_898) + ); + SDFF_X1_LVT \registers_reg[10][12] ( + .CK(n_0_40), .D(registers[12]), .Q(registers_10__ap[12]), .QN(), .SE(dftIn), + .SI(registers_11__ap[13]) + ); + SDFF_X1_LVT \registers_reg[26][12] ( + .CK(n_0_56), .D(registers[12]), .Q(registers_26__ap[12]), .QN(), .SE(dftIn), + .SI(registers_28__ap[12]) + ); + SDFF_X1_LVT \registers_reg[8][12] ( + .CK(n_0_38), .D(registers[12]), .Q(registers_8__ap[12]), .QN(), .SE(dftIn), + .SI(registers_7__ap[13]) + ); + AOI222_X1_LVT i_1_0_942( + .A1(registers_10__ap[12]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[12]), + .C1(registers_8__ap[12]), .C2(n_1_0_1282), .ZN(n_1_0_897) + ); + SDFF_X1_LVT \registers_reg[9][12] ( + .CK(n_0_39), .D(registers[12]), .Q(registers_9__ap[12]), .QN(), .SE(dftIn), + .SI(registers_8__ap[12]) + ); + SDFF_X1_LVT \registers_reg[29][12] ( + .CK(n_0_59), .D(registers[12]), .Q(registers_29__ap[12]), .QN(), .SE(dftIn), + .SI(registers_26__ap[12]) + ); + AOI22_X1_LVT i_1_0_941( + .A1(registers_9__ap[12]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[12]), + .ZN(n_1_0_896) + ); + SDFF_X1_LVT \registers_reg[6][12] ( + .CK(n_0_36), .D(registers[12]), .Q(registers_6__ap[12]), .QN(), .SE(dftIn), + .SI(registers_9__ap[12]) + ); + SDFF_X1_LVT \registers_reg[1][12] ( + .CK(n_0_0), .D(registers[12]), .Q(registers_1__ap[12]), .QN(), .SE(dftIn), + .SI(registers_17__ap[12]) + ); + AOI22_X1_LVT i_1_0_940( + .A1(registers_6__ap[12]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[12]), + .ZN(n_1_0_895) + ); + SDFF_X1_LVT \registers_reg[16][12] ( + .CK(n_0_46), .D(registers[12]), .Q(registers_16__ap[12]), .QN(), .SE(dftIn), + .SI(registers_10__ap[12]) + ); + SDFF_X1_LVT \registers_reg[3][12] ( + .CK(n_0_33), .D(registers[12]), .Q(registers_3__ap[12]), .QN(), .SE(dftIn), + .SI(registers_6__ap[12]) + ); + AOI22_X1_LVT i_1_0_939( + .A1(registers_16__ap[12]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[12]), + .ZN(n_1_0_894) + ); + SDFF_X1_LVT \registers_reg[5][12] ( + .CK(n_0_35), .D(registers[12]), .Q(registers_5__ap[12]), .QN(), .SE(dftIn), + .SI(registers_3__ap[12]) + ); + SDFF_X1_LVT \registers_reg[31][12] ( + .CK(n_0_61), .D(registers[12]), .Q(registers_31__ap[12]), .QN(), .SE(dftIn), + .SI(registers_5__ap[12]) + ); + AOI22_X1_LVT i_1_0_938( + .A1(registers_5__ap[12]), .A2(n_1_0_1273), .B1(n_1_0_1266), .B2(registers_31__ap[12]), + .ZN(n_1_0_893) + ); + SDFF_X1_LVT \registers_reg[15][12] ( + .CK(n_0_45), .D(registers[12]), .Q(registers_15__ap[12]), .QN(), .SE(dftIn), + .SI(registers_16__ap[12]) + ); + SDFF_X1_LVT \registers_reg[23][12] ( + .CK(n_0_53), .D(registers[12]), .Q(registers_23__ap[12]), .QN(), .SE(dftIn), + .SI(registers_1__ap[12]) + ); + AOI22_X1_LVT i_1_0_937( + .A1(registers_15__ap[12]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[12]), + .ZN(n_1_0_892) + ); + NAND4_X1_LVT i_1_0_936( + .A1(n_1_0_895), .A2(n_1_0_894), .A3(n_1_0_893), .A4(n_1_0_892), .ZN(n_1_0_891) + ); + SDFF_X1_LVT \registers_reg[18][12] ( + .CK(n_0_48), .D(registers[12]), .Q(registers_18__ap[12]), .QN(), .SE(dftIn), + .SI(registers_23__ap[12]) + ); + SDFF_X1_LVT \registers_reg[30][12] ( + .CK(n_0_60), .D(registers[12]), .Q(registers_30__ap[12]), .QN(), .SE(dftIn), + .SI(registers_29__ap[12]) + ); + AOI22_X1_LVT i_1_0_935( + .A1(registers_18__ap[12]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[12]), + .ZN(n_1_0_890) + ); + SDFF_X1_LVT \registers_reg[20][12] ( + .CK(n_0_50), .D(registers[12]), .Q(registers_20__ap[12]), .QN(), .SE(dftIn), + .SI(registers_18__ap[12]) + ); + SDFF_X1_LVT \registers_reg[4][12] ( + .CK(n_0_34), .D(registers[12]), .Q(registers_4__ap[12]), .QN(), .SE(dftIn), + .SI(registers_31__ap[12]) + ); + AOI22_X1_LVT i_1_0_934( + .A1(registers_20__ap[12]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[12]), + .ZN(n_1_0_889) + ); + SDFF_X1_LVT \registers_reg[22][12] ( + .CK(n_0_52), .D(registers[12]), .Q(registers_22__ap[12]), .QN(), .SE(dftIn), + .SI(registers_20__ap[12]) + ); + SDFF_X1_LVT \registers_reg[21][12] ( + .CK(n_0_51), .D(registers[12]), .Q(registers_21__ap[12]), .QN(), .SE(dftIn), + .SI(registers_22__ap[12]) + ); + AOI22_X1_LVT i_1_0_933( + .A1(registers_22__ap[12]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[12]), + .ZN(n_1_0_888) + ); + SDFF_X1_LVT \registers_reg[24][12] ( + .CK(n_0_54), .D(registers[12]), .Q(registers_24__ap[12]), .QN(), .SE(dftIn), + .SI(registers_30__ap[12]) + ); + SDFF_X1_LVT \registers_reg[12][12] ( + .CK(n_0_42), .D(registers[12]), .Q(registers_12__ap[12]), .QN(), .SE(dftIn), + .SI(registers_15__ap[12]) + ); + AOI22_X1_LVT i_1_0_932( + .A1(registers_24__ap[12]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[12]), + .ZN(n_1_0_887) + ); + NAND4_X1_LVT i_1_0_931( + .A1(n_1_0_890), .A2(n_1_0_889), .A3(n_1_0_888), .A4(n_1_0_887), .ZN(n_1_0_886) + ); + SDFF_X1_LVT \registers_reg[13][12] ( + .CK(n_0_43), .D(registers[12]), .Q(registers_13__ap[12]), .QN(), .SE(dftIn), + .SI(registers_12__ap[12]) + ); + SDFF_X1_LVT \registers_reg[25][12] ( + .CK(n_0_55), .D(registers[12]), .Q(registers_25__ap[12]), .QN(), .SE(dftIn), + .SI(registers_24__ap[12]) + ); + AOI22_X1_LVT i_1_0_930( + .A1(registers_13__ap[12]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[12]), + .ZN(n_1_0_885) + ); + SDFF_X1_LVT \registers_reg[19][12] ( + .CK(n_0_49), .D(registers[12]), .Q(registers_19__ap[12]), .QN(), .SE(dftIn), + .SI(registers_21__ap[12]) + ); + SDFF_X1_LVT \registers_reg[2][12] ( + .CK(n_0_32), .D(registers[12]), .Q(registers_2__ap[12]), .QN(), .SE(dftIn), + .SI(registers_25__ap[12]) + ); + AOI22_X1_LVT i_1_0_929( + .A1(registers_19__ap[12]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[12]), + .ZN(n_1_0_884) + ); + SDFF_X1_LVT \registers_reg[7][12] ( + .CK(n_0_37), .D(registers[12]), .Q(registers_7__ap[12]), .QN(), .SE(dftIn), + .SI(registers_4__ap[12]) + ); + SDFF_X1_LVT \registers_reg[14][12] ( + .CK(n_0_44), .D(registers[12]), .Q(registers_14__ap[12]), .QN(), .SE(dftIn), + .SI(registers_13__ap[12]) + ); + AOI22_X1_LVT i_1_0_928( + .A1(registers_7__ap[12]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[12]), + .ZN(n_1_0_883) + ); + SDFF_X1_LVT \registers_reg[27][12] ( + .CK(n_0_57), .D(registers[12]), .Q(registers_27__ap[12]), .QN(), .SE(dftIn), + .SI(registers_2__ap[12]) + ); + SDFF_X1_LVT \registers_reg[11][12] ( + .CK(n_0_41), .D(registers[12]), .Q(registers_11__ap[12]), .QN(), .SE(dftIn), + .SI(registers_14__ap[12]) + ); + AOI22_X1_LVT i_1_0_927( + .A1(registers_27__ap[12]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[12]), + .ZN(n_1_0_882) + ); + NAND4_X1_LVT i_1_0_926( + .A1(n_1_0_885), .A2(n_1_0_884), .A3(n_1_0_883), .A4(n_1_0_882), .ZN(n_1_0_881) + ); + NOR3_X1_LVT i_1_0_925( + .A1(n_1_0_891), .A2(n_1_0_886), .A3(n_1_0_881), .ZN(n_1_0_880) + ); + NAND4_X1_LVT i_1_0_924( + .A1(n_1_0_898), .A2(n_1_0_897), .A3(n_1_0_896), .A4(n_1_0_880), .ZN(RRs1[12]) + ); + AND2_X1_LVT i_0_0_11( + .A1(n_0_0_16), .A2(WRd[11]), .ZN(registers[11]) + ); + SDFF_X1_LVT \registers_reg[28][11] ( + .CK(n_0_58), .D(registers[11]), .Q(registers_28__ap[11]), .QN(), .SE(dftIn), + .SI(registers_27__ap[12]) + ); + SDFF_X1_LVT \registers_reg[17][11] ( + .CK(n_0_47), .D(registers[11]), .Q(registers_17__ap[11]), .QN(), .SE(dftIn), + .SI(registers_19__ap[12]) + ); + AOI22_X1_LVT i_1_0_923( + .A1(registers_28__ap[11]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[11]), + .ZN(n_1_0_879) + ); + SDFF_X1_LVT \registers_reg[10][11] ( + .CK(n_0_40), .D(registers[11]), .Q(registers_10__ap[11]), .QN(), .SE(dftIn), + .SI(registers_11__ap[12]) + ); + SDFF_X1_LVT \registers_reg[26][11] ( + .CK(n_0_56), .D(registers[11]), .Q(registers_26__ap[11]), .QN(), .SE(dftIn), + .SI(registers_28__ap[11]) + ); + SDFF_X1_LVT \registers_reg[8][11] ( + .CK(n_0_38), .D(registers[11]), .Q(registers_8__ap[11]), .QN(), .SE(dftIn), + .SI(registers_7__ap[12]) + ); + AOI222_X1_LVT i_1_0_922( + .A1(registers_10__ap[11]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[11]), + .C1(registers_8__ap[11]), .C2(n_1_0_1282), .ZN(n_1_0_878) + ); + SDFF_X1_LVT \registers_reg[9][11] ( + .CK(n_0_39), .D(registers[11]), .Q(registers_9__ap[11]), .QN(), .SE(dftIn), + .SI(registers_8__ap[11]) + ); + SDFF_X1_LVT \registers_reg[29][11] ( + .CK(n_0_59), .D(registers[11]), .Q(registers_29__ap[11]), .QN(), .SE(dftIn), + .SI(registers_26__ap[11]) + ); + AOI22_X1_LVT i_1_0_921( + .A1(registers_9__ap[11]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[11]), + .ZN(n_1_0_877) + ); + SDFF_X1_LVT \registers_reg[6][11] ( + .CK(n_0_36), .D(registers[11]), .Q(registers_6__ap[11]), .QN(), .SE(dftIn), + .SI(registers_9__ap[11]) + ); + SDFF_X1_LVT \registers_reg[1][11] ( + .CK(n_0_0), .D(registers[11]), .Q(registers_1__ap[11]), .QN(), .SE(dftIn), + .SI(registers_17__ap[11]) + ); + AOI22_X1_LVT i_1_0_920( + .A1(registers_6__ap[11]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[11]), + .ZN(n_1_0_876) + ); + SDFF_X1_LVT \registers_reg[5][11] ( + .CK(n_0_35), .D(registers[11]), .Q(registers_5__ap[11]), .QN(), .SE(dftIn), + .SI(registers_6__ap[11]) + ); + SDFF_X1_LVT \registers_reg[3][11] ( + .CK(n_0_33), .D(registers[11]), .Q(registers_3__ap[11]), .QN(), .SE(dftIn), + .SI(registers_5__ap[11]) + ); + AOI22_X1_LVT i_1_0_919( + .A1(registers_5__ap[11]), .A2(n_1_0_1273), .B1(n_1_0_1257), .B2(registers_3__ap[11]), + .ZN(n_1_0_875) + ); + SDFF_X1_LVT \registers_reg[16][11] ( + .CK(n_0_46), .D(registers[11]), .Q(registers_16__ap[11]), .QN(), .SE(dftIn), + .SI(registers_10__ap[11]) + ); + SDFF_X1_LVT \registers_reg[31][11] ( + .CK(n_0_61), .D(registers[11]), .Q(registers_31__ap[11]), .QN(), .SE(dftIn), + .SI(registers_3__ap[11]) + ); + AOI22_X1_LVT i_1_0_918( + .A1(registers_16__ap[11]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[11]), + .ZN(n_1_0_874) + ); + SDFF_X1_LVT \registers_reg[15][11] ( + .CK(n_0_45), .D(registers[11]), .Q(registers_15__ap[11]), .QN(), .SE(dftIn), + .SI(registers_16__ap[11]) + ); + SDFF_X1_LVT \registers_reg[23][11] ( + .CK(n_0_53), .D(registers[11]), .Q(registers_23__ap[11]), .QN(), .SE(dftIn), + .SI(registers_1__ap[11]) + ); + AOI22_X1_LVT i_1_0_917( + .A1(registers_15__ap[11]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[11]), + .ZN(n_1_0_873) + ); + NAND4_X1_LVT i_1_0_916( + .A1(n_1_0_876), .A2(n_1_0_875), .A3(n_1_0_874), .A4(n_1_0_873), .ZN(n_1_0_872) + ); + SDFF_X1_LVT \registers_reg[18][11] ( + .CK(n_0_48), .D(registers[11]), .Q(registers_18__ap[11]), .QN(), .SE(dftIn), + .SI(registers_23__ap[11]) + ); + SDFF_X1_LVT \registers_reg[30][11] ( + .CK(n_0_60), .D(registers[11]), .Q(registers_30__ap[11]), .QN(), .SE(dftIn), + .SI(registers_29__ap[11]) + ); + AOI22_X1_LVT i_1_0_915( + .A1(registers_18__ap[11]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[11]), + .ZN(n_1_0_871) + ); + SDFF_X1_LVT \registers_reg[20][11] ( + .CK(n_0_50), .D(registers[11]), .Q(registers_20__ap[11]), .QN(), .SE(dftIn), + .SI(registers_18__ap[11]) + ); + SDFF_X1_LVT \registers_reg[4][11] ( + .CK(n_0_34), .D(registers[11]), .Q(registers_4__ap[11]), .QN(), .SE(dftIn), + .SI(registers_31__ap[11]) + ); + AOI22_X1_LVT i_1_0_914( + .A1(registers_20__ap[11]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[11]), + .ZN(n_1_0_870) + ); + SDFF_X1_LVT \registers_reg[22][11] ( + .CK(n_0_52), .D(registers[11]), .Q(registers_22__ap[11]), .QN(), .SE(dftIn), + .SI(registers_20__ap[11]) + ); + SDFF_X1_LVT \registers_reg[21][11] ( + .CK(n_0_51), .D(registers[11]), .Q(registers_21__ap[11]), .QN(), .SE(dftIn), + .SI(registers_22__ap[11]) + ); + AOI22_X1_LVT i_1_0_913( + .A1(registers_22__ap[11]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[11]), + .ZN(n_1_0_869) + ); + SDFF_X1_LVT \registers_reg[24][11] ( + .CK(n_0_54), .D(registers[11]), .Q(registers_24__ap[11]), .QN(), .SE(dftIn), + .SI(registers_30__ap[11]) + ); + SDFF_X1_LVT \registers_reg[12][11] ( + .CK(n_0_42), .D(registers[11]), .Q(registers_12__ap[11]), .QN(), .SE(dftIn), + .SI(registers_15__ap[11]) + ); + AOI22_X1_LVT i_1_0_912( + .A1(registers_24__ap[11]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[11]), + .ZN(n_1_0_868) + ); + NAND4_X1_LVT i_1_0_911( + .A1(n_1_0_871), .A2(n_1_0_870), .A3(n_1_0_869), .A4(n_1_0_868), .ZN(n_1_0_867) + ); + SDFF_X1_LVT \registers_reg[13][11] ( + .CK(n_0_43), .D(registers[11]), .Q(registers_13__ap[11]), .QN(), .SE(dftIn), + .SI(registers_12__ap[11]) + ); + SDFF_X1_LVT \registers_reg[25][11] ( + .CK(n_0_55), .D(registers[11]), .Q(registers_25__ap[11]), .QN(), .SE(dftIn), + .SI(registers_24__ap[11]) + ); + AOI22_X1_LVT i_1_0_910( + .A1(registers_13__ap[11]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[11]), + .ZN(n_1_0_866) + ); + SDFF_X1_LVT \registers_reg[19][11] ( + .CK(n_0_49), .D(registers[11]), .Q(registers_19__ap[11]), .QN(), .SE(dftIn), + .SI(registers_21__ap[11]) + ); + SDFF_X1_LVT \registers_reg[2][11] ( + .CK(n_0_32), .D(registers[11]), .Q(registers_2__ap[11]), .QN(), .SE(dftIn), + .SI(registers_25__ap[11]) + ); + AOI22_X1_LVT i_1_0_909( + .A1(registers_19__ap[11]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[11]), + .ZN(n_1_0_865) + ); + SDFF_X1_LVT \registers_reg[7][11] ( + .CK(n_0_37), .D(registers[11]), .Q(registers_7__ap[11]), .QN(), .SE(dftIn), + .SI(registers_4__ap[11]) + ); + SDFF_X1_LVT \registers_reg[14][11] ( + .CK(n_0_44), .D(registers[11]), .Q(registers_14__ap[11]), .QN(), .SE(dftIn), + .SI(registers_13__ap[11]) + ); + AOI22_X1_LVT i_1_0_908( + .A1(registers_7__ap[11]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[11]), + .ZN(n_1_0_864) + ); + SDFF_X1_LVT \registers_reg[27][11] ( + .CK(n_0_57), .D(registers[11]), .Q(registers_27__ap[11]), .QN(), .SE(dftIn), + .SI(registers_2__ap[11]) + ); + SDFF_X1_LVT \registers_reg[11][11] ( + .CK(n_0_41), .D(registers[11]), .Q(registers_11__ap[11]), .QN(), .SE(dftIn), + .SI(registers_14__ap[11]) + ); + AOI22_X1_LVT i_1_0_907( + .A1(registers_27__ap[11]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[11]), + .ZN(n_1_0_863) + ); + NAND4_X1_LVT i_1_0_906( + .A1(n_1_0_866), .A2(n_1_0_865), .A3(n_1_0_864), .A4(n_1_0_863), .ZN(n_1_0_862) + ); + NOR3_X1_LVT i_1_0_905( + .A1(n_1_0_872), .A2(n_1_0_867), .A3(n_1_0_862), .ZN(n_1_0_861) + ); + NAND4_X1_LVT i_1_0_904( + .A1(n_1_0_879), .A2(n_1_0_878), .A3(n_1_0_877), .A4(n_1_0_861), .ZN(RRs1[11]) + ); + AND2_X1_LVT i_0_0_10( + .A1(n_0_0_16), .A2(WRd[10]), .ZN(registers[10]) + ); + SDFF_X1_LVT \registers_reg[28][10] ( + .CK(n_0_58), .D(registers[10]), .Q(registers_28__ap[10]), .QN(), .SE(dftIn), + .SI(registers_27__ap[11]) + ); + SDFF_X1_LVT \registers_reg[8][10] ( + .CK(n_0_38), .D(registers[10]), .Q(registers_8__ap[10]), .QN(), .SE(dftIn), + .SI(registers_7__ap[11]) + ); + AOI22_X1_LVT i_1_0_902( + .A1(registers_28__ap[10]), .A2(n_1_0_1283), .B1(n_1_0_1282), .B2(registers_8__ap[10]), + .ZN(n_1_0_859) + ); + SDFF_X1_LVT \registers_reg[31][10] ( + .CK(n_0_61), .D(registers[10]), .Q(registers_31__ap[10]), .QN(), .SE(dftIn), + .SI(registers_8__ap[10]) + ); + SDFF_X1_LVT \registers_reg[7][10] ( + .CK(n_0_37), .D(registers[10]), .Q(registers_7__ap[10]), .QN(), .SE(dftIn), + .SI(registers_31__ap[10]) + ); + AOI22_X1_LVT i_1_0_903( + .A1(registers_31__ap[10]), .A2(n_1_0_1266), .B1(n_1_0_1263), .B2(registers_7__ap[10]), + .ZN(n_1_0_860) + ); + SDFF_X1_LVT \registers_reg[24][10] ( + .CK(n_0_54), .D(registers[10]), .Q(registers_24__ap[10]), .QN(), .SE(dftIn), + .SI(registers_28__ap[10]) + ); + SDFF_X1_LVT \registers_reg[20][10] ( + .CK(n_0_50), .D(registers[10]), .Q(registers_20__ap[10]), .QN(), .SE(dftIn), + .SI(registers_19__ap[11]) + ); + AOI22_X1_LVT i_1_0_901( + .A1(registers_24__ap[10]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[10]), + .ZN(n_1_0_858) + ); + SDFF_X1_LVT \registers_reg[4][10] ( + .CK(n_0_34), .D(registers[10]), .Q(registers_4__ap[10]), .QN(), .SE(dftIn), + .SI(registers_7__ap[10]) + ); + SDFF_X1_LVT \registers_reg[23][10] ( + .CK(n_0_53), .D(registers[10]), .Q(registers_23__ap[10]), .QN(), .SE(dftIn), + .SI(registers_20__ap[10]) + ); + AOI22_X1_LVT i_1_0_900( + .A1(registers_4__ap[10]), .A2(n_1_0_1278), .B1(n_1_0_1264), .B2(registers_23__ap[10]), + .ZN(n_1_0_857) + ); + NAND3_X1_LVT i_1_0_899( + .A1(n_1_0_860), .A2(n_1_0_858), .A3(n_1_0_857), .ZN(n_1_0_856) + ); + SDFF_X1_LVT \registers_reg[27][10] ( + .CK(n_0_57), .D(registers[10]), .Q(registers_27__ap[10]), .QN(), .SE(dftIn), + .SI(registers_24__ap[10]) + ); + SDFF_X1_LVT \registers_reg[29][10] ( + .CK(n_0_59), .D(registers[10]), .Q(registers_29__ap[10]), .QN(), .SE(dftIn), + .SI(registers_27__ap[10]) + ); + AOI221_X1_LVT i_1_0_898( + .A(n_1_0_856), .B1(n_1_0_1279), .B2(registers_27__ap[10]), .C1(registers_29__ap[10]), + .C2(n_1_0_1276), .ZN(n_1_0_855) + ); + SDFF_X1_LVT \registers_reg[10][10] ( + .CK(n_0_40), .D(registers[10]), .Q(registers_10__ap[10]), .QN(), .SE(dftIn), + .SI(registers_11__ap[11]) + ); + SDFF_X1_LVT \registers_reg[30][10] ( + .CK(n_0_60), .D(registers[10]), .Q(registers_30__ap[10]), .QN(), .SE(dftIn), + .SI(registers_29__ap[10]) + ); + SDFF_X1_LVT \registers_reg[25][10] ( + .CK(n_0_55), .D(registers[10]), .Q(registers_25__ap[10]), .QN(), .SE(dftIn), + .SI(registers_30__ap[10]) + ); + AOI222_X1_LVT i_1_0_897( + .A1(registers_10__ap[10]), .A2(n_1_0_1287), .B1(n_1_0_1272), .B2(registers_30__ap[10]), + .C1(n_1_0_1269), .C2(registers_25__ap[10]), .ZN(n_1_0_854) + ); + NAND3_X1_LVT i_1_0_896( + .A1(n_1_0_859), .A2(n_1_0_855), .A3(n_1_0_854), .ZN(n_1_0_853) + ); + SDFF_X1_LVT \registers_reg[21][10] ( + .CK(n_0_51), .D(registers[10]), .Q(registers_21__ap[10]), .QN(), .SE(dftIn), + .SI(registers_23__ap[10]) + ); + SDFF_X1_LVT \registers_reg[13][10] ( + .CK(n_0_43), .D(registers[10]), .Q(registers_13__ap[10]), .QN(), .SE(dftIn), + .SI(registers_10__ap[10]) + ); + AOI221_X1_LVT i_1_0_895( + .A(n_1_0_853), .B1(n_1_0_1259), .B2(registers_21__ap[10]), .C1(registers_13__ap[10]), + .C2(n_1_0_1277), .ZN(n_1_0_852) + ); + SDFF_X1_LVT \registers_reg[18][10] ( + .CK(n_0_48), .D(registers[10]), .Q(registers_18__ap[10]), .QN(), .SE(dftIn), + .SI(registers_21__ap[10]) + ); + SDFF_X1_LVT \registers_reg[26][10] ( + .CK(n_0_56), .D(registers[10]), .Q(registers_26__ap[10]), .QN(), .SE(dftIn), + .SI(registers_25__ap[10]) + ); + AOI22_X1_LVT i_1_0_894( + .A1(registers_18__ap[10]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[10]), + .ZN(n_1_0_851) + ); + SDFF_X1_LVT \registers_reg[17][10] ( + .CK(n_0_47), .D(registers[10]), .Q(registers_17__ap[10]), .QN(), .SE(dftIn), + .SI(registers_18__ap[10]) + ); + SDFF_X1_LVT \registers_reg[12][10] ( + .CK(n_0_42), .D(registers[10]), .Q(registers_12__ap[10]), .QN(), .SE(dftIn), + .SI(registers_13__ap[10]) + ); + AOI22_X1_LVT i_1_0_893( + .A1(registers_17__ap[10]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[10]), + .ZN(n_1_0_850) + ); + SDFF_X1_LVT \registers_reg[15][10] ( + .CK(n_0_45), .D(registers[10]), .Q(registers_15__ap[10]), .QN(), .SE(dftIn), + .SI(registers_12__ap[10]) + ); + SDFF_X1_LVT \registers_reg[5][10] ( + .CK(n_0_35), .D(registers[10]), .Q(registers_5__ap[10]), .QN(), .SE(dftIn), + .SI(registers_4__ap[10]) + ); + AOI22_X1_LVT i_1_0_892( + .A1(registers_15__ap[10]), .A2(n_1_0_1286), .B1(n_1_0_1273), .B2(registers_5__ap[10]), + .ZN(n_1_0_849) + ); + NAND3_X1_LVT i_1_0_891( + .A1(n_1_0_851), .A2(n_1_0_850), .A3(n_1_0_849), .ZN(n_1_0_848) + ); + SDFF_X1_LVT \registers_reg[22][10] ( + .CK(n_0_52), .D(registers[10]), .Q(registers_22__ap[10]), .QN(), .SE(dftIn), + .SI(registers_17__ap[10]) + ); + SDFF_X1_LVT \registers_reg[16][10] ( + .CK(n_0_46), .D(registers[10]), .Q(registers_16__ap[10]), .QN(), .SE(dftIn), + .SI(registers_15__ap[10]) + ); + AOI221_X1_LVT i_1_0_890( + .A(n_1_0_848), .B1(n_1_0_1294), .B2(registers_22__ap[10]), .C1(registers_16__ap[10]), + .C2(n_1_0_1267), .ZN(n_1_0_847) + ); + SDFF_X1_LVT \registers_reg[9][10] ( + .CK(n_0_39), .D(registers[10]), .Q(registers_9__ap[10]), .QN(), .SE(dftIn), + .SI(registers_5__ap[10]) + ); + SDFF_X1_LVT \registers_reg[1][10] ( + .CK(n_0_0), .D(registers[10]), .Q(registers_1__ap[10]), .QN(), .SE(dftIn), + .SI(registers_22__ap[10]) + ); + AOI22_X1_LVT i_1_0_889( + .A1(registers_9__ap[10]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[10]), + .ZN(n_1_0_846) + ); + SDFF_X1_LVT \registers_reg[6][10] ( + .CK(n_0_36), .D(registers[10]), .Q(registers_6__ap[10]), .QN(), .SE(dftIn), + .SI(registers_9__ap[10]) + ); + SDFF_X1_LVT \registers_reg[14][10] ( + .CK(n_0_44), .D(registers[10]), .Q(registers_14__ap[10]), .QN(), .SE(dftIn), + .SI(registers_16__ap[10]) + ); + AOI22_X1_LVT i_1_0_888( + .A1(registers_6__ap[10]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[10]), + .ZN(n_1_0_845) + ); + SDFF_X1_LVT \registers_reg[19][10] ( + .CK(n_0_49), .D(registers[10]), .Q(registers_19__ap[10]), .QN(), .SE(dftIn), + .SI(registers_1__ap[10]) + ); + SDFF_X1_LVT \registers_reg[3][10] ( + .CK(n_0_33), .D(registers[10]), .Q(registers_3__ap[10]), .QN(), .SE(dftIn), + .SI(registers_6__ap[10]) + ); + AOI22_X1_LVT i_1_0_887( + .A1(registers_19__ap[10]), .A2(n_1_0_1295), .B1(n_1_0_1257), .B2(registers_3__ap[10]), + .ZN(n_1_0_844) + ); + NAND3_X1_LVT i_1_0_886( + .A1(n_1_0_846), .A2(n_1_0_845), .A3(n_1_0_844), .ZN(n_1_0_843) + ); + SDFF_X1_LVT \registers_reg[11][10] ( + .CK(n_0_41), .D(registers[10]), .Q(registers_11__ap[10]), .QN(), .SE(dftIn), + .SI(registers_14__ap[10]) + ); + SDFF_X1_LVT \registers_reg[2][10] ( + .CK(n_0_32), .D(registers[10]), .Q(registers_2__ap[10]), .QN(), .SE(dftIn), + .SI(registers_26__ap[10]) + ); + AOI221_X1_LVT i_1_0_885( + .A(n_1_0_843), .B1(n_1_0_1270), .B2(registers_11__ap[10]), .C1(registers_2__ap[10]), + .C2(n_1_0_1268), .ZN(n_1_0_842) + ); + NAND3_X1_LVT i_1_0_884( + .A1(n_1_0_852), .A2(n_1_0_847), .A3(n_1_0_842), .ZN(RRs1[10]) + ); + AND2_X1_LVT i_0_0_9( + .A1(n_0_0_16), .A2(WRd[9]), .ZN(registers[9]) + ); + SDFF_X1_LVT \registers_reg[13][9] ( + .CK(n_0_43), .D(registers[9]), .Q(registers_13__ap[9]), .QN(), .SE(dftIn), + .SI(registers_11__ap[10]) + ); + SDFF_X1_LVT \registers_reg[21][9] ( + .CK(n_0_51), .D(registers[9]), .Q(registers_21__ap[9]), .QN(), .SE(dftIn), + .SI(registers_19__ap[10]) + ); + AOI22_X1_LVT i_1_0_880( + .A1(registers_13__ap[9]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[9]), + .ZN(n_1_0_838) + ); + SDFF_X1_LVT \registers_reg[29][9] ( + .CK(n_0_59), .D(registers[9]), .Q(registers_29__ap[9]), .QN(), .SE(dftIn), + .SI(registers_2__ap[10]) + ); + SDFF_X1_LVT \registers_reg[23][9] ( + .CK(n_0_53), .D(registers[9]), .Q(registers_23__ap[9]), .QN(), .SE(dftIn), + .SI(registers_21__ap[9]) + ); + AOI22_X1_LVT i_1_0_883( + .A1(registers_29__ap[9]), .A2(n_1_0_1276), .B1(n_1_0_1264), .B2(registers_23__ap[9]), + .ZN(n_1_0_841) + ); + SDFF_X1_LVT \registers_reg[24][9] ( + .CK(n_0_54), .D(registers[9]), .Q(registers_24__ap[9]), .QN(), .SE(dftIn), + .SI(registers_29__ap[9]) + ); + SDFF_X1_LVT \registers_reg[20][9] ( + .CK(n_0_50), .D(registers[9]), .Q(registers_20__ap[9]), .QN(), .SE(dftIn), + .SI(registers_23__ap[9]) + ); + AOI22_X1_LVT i_1_0_879( + .A1(registers_24__ap[9]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[9]), + .ZN(n_1_0_837) + ); + SDFF_X1_LVT \registers_reg[7][9] ( + .CK(n_0_37), .D(registers[9]), .Q(registers_7__ap[9]), .QN(), .SE(dftIn), + .SI(registers_3__ap[10]) + ); + SDFF_X1_LVT \registers_reg[3][9] ( + .CK(n_0_33), .D(registers[9]), .Q(registers_3__ap[9]), .QN(), .SE(dftIn), + .SI(registers_7__ap[9]) + ); + AOI22_X1_LVT i_1_0_882( + .A1(registers_7__ap[9]), .A2(n_1_0_1263), .B1(n_1_0_1257), .B2(registers_3__ap[9]), + .ZN(n_1_0_840) + ); + INV_X1_LVT i_1_0_881( + .A(n_1_0_840), .ZN(n_1_0_839) + ); + SDFF_X1_LVT \registers_reg[31][9] ( + .CK(n_0_61), .D(registers[9]), .Q(registers_31__ap[9]), .QN(), .SE(dftIn), + .SI(registers_3__ap[9]) + ); + SDFF_X1_LVT \registers_reg[4][9] ( + .CK(n_0_34), .D(registers[9]), .Q(registers_4__ap[9]), .QN(), .SE(dftIn), + .SI(registers_31__ap[9]) + ); + AOI221_X1_LVT i_1_0_878( + .A(n_1_0_839), .B1(n_1_0_1266), .B2(registers_31__ap[9]), .C1(registers_4__ap[9]), + .C2(n_1_0_1278), .ZN(n_1_0_836) + ); + SDFF_X1_LVT \registers_reg[10][9] ( + .CK(n_0_40), .D(registers[9]), .Q(registers_10__ap[9]), .QN(), .SE(dftIn), + .SI(registers_13__ap[9]) + ); + SDFF_X1_LVT \registers_reg[26][9] ( + .CK(n_0_56), .D(registers[9]), .Q(registers_26__ap[9]), .QN(), .SE(dftIn), + .SI(registers_24__ap[9]) + ); + SDFF_X1_LVT \registers_reg[25][9] ( + .CK(n_0_55), .D(registers[9]), .Q(registers_25__ap[9]), .QN(), .SE(dftIn), + .SI(registers_26__ap[9]) + ); + AOI222_X1_LVT i_1_0_877( + .A1(registers_10__ap[9]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[9]), + .C1(registers_25__ap[9]), .C2(n_1_0_1269), .ZN(n_1_0_835) + ); + NAND4_X1_LVT i_1_0_876( + .A1(n_1_0_841), .A2(n_1_0_837), .A3(n_1_0_836), .A4(n_1_0_835), .ZN(n_1_0_834) + ); + SDFF_X1_LVT \registers_reg[8][9] ( + .CK(n_0_38), .D(registers[9]), .Q(registers_8__ap[9]), .QN(), .SE(dftIn), + .SI(registers_4__ap[9]) + ); + SDFF_X1_LVT \registers_reg[28][9] ( + .CK(n_0_58), .D(registers[9]), .Q(registers_28__ap[9]), .QN(), .SE(dftIn), + .SI(registers_25__ap[9]) + ); + AOI221_X1_LVT i_1_0_875( + .A(n_1_0_834), .B1(n_1_0_1282), .B2(registers_8__ap[9]), .C1(registers_28__ap[9]), + .C2(n_1_0_1283), .ZN(n_1_0_833) + ); + SDFF_X1_LVT \registers_reg[18][9] ( + .CK(n_0_48), .D(registers[9]), .Q(registers_18__ap[9]), .QN(), .SE(dftIn), + .SI(registers_20__ap[9]) + ); + SDFF_X1_LVT \registers_reg[30][9] ( + .CK(n_0_60), .D(registers[9]), .Q(registers_30__ap[9]), .QN(), .SE(dftIn), + .SI(registers_28__ap[9]) + ); + AOI22_X1_LVT i_1_0_874( + .A1(registers_18__ap[9]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[9]), + .ZN(n_1_0_832) + ); + SDFF_X1_LVT \registers_reg[17][9] ( + .CK(n_0_47), .D(registers[9]), .Q(registers_17__ap[9]), .QN(), .SE(dftIn), + .SI(registers_18__ap[9]) + ); + SDFF_X1_LVT \registers_reg[12][9] ( + .CK(n_0_42), .D(registers[9]), .Q(registers_12__ap[9]), .QN(), .SE(dftIn), + .SI(registers_10__ap[9]) + ); + AOI22_X1_LVT i_1_0_873( + .A1(registers_17__ap[9]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[9]), + .ZN(n_1_0_831) + ); + SDFF_X1_LVT \registers_reg[15][9] ( + .CK(n_0_45), .D(registers[9]), .Q(registers_15__ap[9]), .QN(), .SE(dftIn), + .SI(registers_12__ap[9]) + ); + SDFF_X1_LVT \registers_reg[5][9] ( + .CK(n_0_35), .D(registers[9]), .Q(registers_5__ap[9]), .QN(), .SE(dftIn), + .SI(registers_8__ap[9]) + ); + AOI22_X1_LVT i_1_0_872( + .A1(registers_15__ap[9]), .A2(n_1_0_1286), .B1(n_1_0_1273), .B2(registers_5__ap[9]), + .ZN(n_1_0_830) + ); + NAND3_X1_LVT i_1_0_871( + .A1(n_1_0_832), .A2(n_1_0_831), .A3(n_1_0_830), .ZN(n_1_0_829) + ); + SDFF_X1_LVT \registers_reg[22][9] ( + .CK(n_0_52), .D(registers[9]), .Q(registers_22__ap[9]), .QN(), .SE(dftIn), + .SI(registers_17__ap[9]) + ); + SDFF_X1_LVT \registers_reg[16][9] ( + .CK(n_0_46), .D(registers[9]), .Q(registers_16__ap[9]), .QN(), .SE(dftIn), + .SI(registers_15__ap[9]) + ); + AOI221_X1_LVT i_1_0_870( + .A(n_1_0_829), .B1(n_1_0_1294), .B2(registers_22__ap[9]), .C1(registers_16__ap[9]), + .C2(n_1_0_1267), .ZN(n_1_0_828) + ); + SDFF_X1_LVT \registers_reg[9][9] ( + .CK(n_0_39), .D(registers[9]), .Q(registers_9__ap[9]), .QN(), .SE(dftIn), + .SI(registers_5__ap[9]) + ); + SDFF_X1_LVT \registers_reg[1][9] ( + .CK(n_0_0), .D(registers[9]), .Q(registers_1__ap[9]), .QN(), .SE(dftIn), + .SI(registers_22__ap[9]) + ); + AOI22_X1_LVT i_1_0_869( + .A1(registers_9__ap[9]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[9]), + .ZN(n_1_0_827) + ); + SDFF_X1_LVT \registers_reg[6][9] ( + .CK(n_0_36), .D(registers[9]), .Q(registers_6__ap[9]), .QN(), .SE(dftIn), + .SI(registers_9__ap[9]) + ); + SDFF_X1_LVT \registers_reg[14][9] ( + .CK(n_0_44), .D(registers[9]), .Q(registers_14__ap[9]), .QN(), .SE(dftIn), + .SI(registers_16__ap[9]) + ); + AOI22_X1_LVT i_1_0_868( + .A1(registers_6__ap[9]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[9]), + .ZN(n_1_0_826) + ); + SDFF_X1_LVT \registers_reg[19][9] ( + .CK(n_0_49), .D(registers[9]), .Q(registers_19__ap[9]), .QN(), .SE(dftIn), + .SI(registers_1__ap[9]) + ); + SDFF_X1_LVT \registers_reg[2][9] ( + .CK(n_0_32), .D(registers[9]), .Q(registers_2__ap[9]), .QN(), .SE(dftIn), + .SI(registers_30__ap[9]) + ); + AOI22_X1_LVT i_1_0_867( + .A1(registers_19__ap[9]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[9]), + .ZN(n_1_0_825) + ); + NAND3_X1_LVT i_1_0_866( + .A1(n_1_0_827), .A2(n_1_0_826), .A3(n_1_0_825), .ZN(n_1_0_824) + ); + SDFF_X1_LVT \registers_reg[11][9] ( + .CK(n_0_41), .D(registers[9]), .Q(registers_11__ap[9]), .QN(), .SE(dftIn), + .SI(registers_14__ap[9]) + ); + SDFF_X1_LVT \registers_reg[27][9] ( + .CK(n_0_57), .D(registers[9]), .Q(registers_27__ap[9]), .QN(), .SE(dftIn), + .SI(registers_2__ap[9]) + ); + AOI221_X1_LVT i_1_0_865( + .A(n_1_0_824), .B1(n_1_0_1270), .B2(registers_11__ap[9]), .C1(registers_27__ap[9]), + .C2(n_1_0_1279), .ZN(n_1_0_823) + ); + NAND4_X1_LVT i_1_0_864( + .A1(n_1_0_838), .A2(n_1_0_833), .A3(n_1_0_828), .A4(n_1_0_823), .ZN(RRs1[9]) + ); + AND2_X1_LVT i_0_0_8( + .A1(n_0_0_16), .A2(WRd[8]), .ZN(registers[8]) + ); + SDFF_X1_LVT \registers_reg[13][8] ( + .CK(n_0_43), .D(registers[8]), .Q(registers_13__ap[8]), .QN(), .SE(dftIn), + .SI(registers_11__ap[9]) + ); + SDFF_X1_LVT \registers_reg[21][8] ( + .CK(n_0_51), .D(registers[8]), .Q(registers_21__ap[8]), .QN(), .SE(dftIn), + .SI(registers_19__ap[9]) + ); + AOI22_X1_LVT i_1_0_860( + .A1(registers_13__ap[8]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[8]), + .ZN(n_1_0_819) + ); + SDFF_X1_LVT \registers_reg[29][8] ( + .CK(n_0_59), .D(registers[8]), .Q(registers_29__ap[8]), .QN(), .SE(dftIn), + .SI(registers_27__ap[9]) + ); + SDFF_X1_LVT \registers_reg[23][8] ( + .CK(n_0_53), .D(registers[8]), .Q(registers_23__ap[8]), .QN(), .SE(dftIn), + .SI(registers_21__ap[8]) + ); + AOI22_X1_LVT i_1_0_863( + .A1(registers_29__ap[8]), .A2(n_1_0_1276), .B1(n_1_0_1264), .B2(registers_23__ap[8]), + .ZN(n_1_0_822) + ); + SDFF_X1_LVT \registers_reg[24][8] ( + .CK(n_0_54), .D(registers[8]), .Q(registers_24__ap[8]), .QN(), .SE(dftIn), + .SI(registers_29__ap[8]) + ); + SDFF_X1_LVT \registers_reg[20][8] ( + .CK(n_0_50), .D(registers[8]), .Q(registers_20__ap[8]), .QN(), .SE(dftIn), + .SI(registers_23__ap[8]) + ); + AOI22_X1_LVT i_1_0_859( + .A1(registers_24__ap[8]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[8]), + .ZN(n_1_0_818) + ); + SDFF_X1_LVT \registers_reg[7][8] ( + .CK(n_0_37), .D(registers[8]), .Q(registers_7__ap[8]), .QN(), .SE(dftIn), + .SI(registers_6__ap[9]) + ); + SDFF_X1_LVT \registers_reg[3][8] ( + .CK(n_0_33), .D(registers[8]), .Q(registers_3__ap[8]), .QN(), .SE(dftIn), + .SI(registers_7__ap[8]) + ); + AOI22_X1_LVT i_1_0_862( + .A1(registers_7__ap[8]), .A2(n_1_0_1263), .B1(n_1_0_1257), .B2(registers_3__ap[8]), + .ZN(n_1_0_821) + ); + INV_X1_LVT i_1_0_861( + .A(n_1_0_821), .ZN(n_1_0_820) + ); + SDFF_X1_LVT \registers_reg[31][8] ( + .CK(n_0_61), .D(registers[8]), .Q(registers_31__ap[8]), .QN(), .SE(dftIn), + .SI(registers_3__ap[8]) + ); + SDFF_X1_LVT \registers_reg[4][8] ( + .CK(n_0_34), .D(registers[8]), .Q(registers_4__ap[8]), .QN(), .SE(dftIn), + .SI(registers_31__ap[8]) + ); + AOI221_X1_LVT i_1_0_858( + .A(n_1_0_820), .B1(n_1_0_1266), .B2(registers_31__ap[8]), .C1(registers_4__ap[8]), + .C2(n_1_0_1278), .ZN(n_1_0_817) + ); + SDFF_X1_LVT \registers_reg[10][8] ( + .CK(n_0_40), .D(registers[8]), .Q(registers_10__ap[8]), .QN(), .SE(dftIn), + .SI(registers_13__ap[8]) + ); + SDFF_X1_LVT \registers_reg[26][8] ( + .CK(n_0_56), .D(registers[8]), .Q(registers_26__ap[8]), .QN(), .SE(dftIn), + .SI(registers_24__ap[8]) + ); + SDFF_X1_LVT \registers_reg[25][8] ( + .CK(n_0_55), .D(registers[8]), .Q(registers_25__ap[8]), .QN(), .SE(dftIn), + .SI(registers_26__ap[8]) + ); + AOI222_X1_LVT i_1_0_857( + .A1(registers_10__ap[8]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[8]), + .C1(registers_25__ap[8]), .C2(n_1_0_1269), .ZN(n_1_0_816) + ); + NAND4_X1_LVT i_1_0_856( + .A1(n_1_0_822), .A2(n_1_0_818), .A3(n_1_0_817), .A4(n_1_0_816), .ZN(n_1_0_815) + ); + SDFF_X1_LVT \registers_reg[8][8] ( + .CK(n_0_38), .D(registers[8]), .Q(registers_8__ap[8]), .QN(), .SE(dftIn), + .SI(registers_4__ap[8]) + ); + SDFF_X1_LVT \registers_reg[28][8] ( + .CK(n_0_58), .D(registers[8]), .Q(registers_28__ap[8]), .QN(), .SE(dftIn), + .SI(registers_25__ap[8]) + ); + AOI221_X1_LVT i_1_0_855( + .A(n_1_0_815), .B1(n_1_0_1282), .B2(registers_8__ap[8]), .C1(registers_28__ap[8]), + .C2(n_1_0_1283), .ZN(n_1_0_814) + ); + SDFF_X1_LVT \registers_reg[18][8] ( + .CK(n_0_48), .D(registers[8]), .Q(registers_18__ap[8]), .QN(), .SE(dftIn), + .SI(registers_20__ap[8]) + ); + SDFF_X1_LVT \registers_reg[30][8] ( + .CK(n_0_60), .D(registers[8]), .Q(registers_30__ap[8]), .QN(), .SE(dftIn), + .SI(registers_28__ap[8]) + ); + AOI22_X1_LVT i_1_0_854( + .A1(registers_18__ap[8]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[8]), + .ZN(n_1_0_813) + ); + SDFF_X1_LVT \registers_reg[17][8] ( + .CK(n_0_47), .D(registers[8]), .Q(registers_17__ap[8]), .QN(), .SE(dftIn), + .SI(registers_18__ap[8]) + ); + SDFF_X1_LVT \registers_reg[12][8] ( + .CK(n_0_42), .D(registers[8]), .Q(registers_12__ap[8]), .QN(), .SE(dftIn), + .SI(registers_10__ap[8]) + ); + AOI22_X1_LVT i_1_0_853( + .A1(registers_17__ap[8]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[8]), + .ZN(n_1_0_812) + ); + SDFF_X1_LVT \registers_reg[15][8] ( + .CK(n_0_45), .D(registers[8]), .Q(registers_15__ap[8]), .QN(), .SE(dftIn), + .SI(registers_12__ap[8]) + ); + SDFF_X1_LVT \registers_reg[5][8] ( + .CK(n_0_35), .D(registers[8]), .Q(registers_5__ap[8]), .QN(), .SE(dftIn), + .SI(registers_8__ap[8]) + ); + AOI22_X1_LVT i_1_0_852( + .A1(registers_15__ap[8]), .A2(n_1_0_1286), .B1(n_1_0_1273), .B2(registers_5__ap[8]), + .ZN(n_1_0_811) + ); + NAND3_X1_LVT i_1_0_851( + .A1(n_1_0_813), .A2(n_1_0_812), .A3(n_1_0_811), .ZN(n_1_0_810) + ); + SDFF_X1_LVT \registers_reg[22][8] ( + .CK(n_0_52), .D(registers[8]), .Q(registers_22__ap[8]), .QN(), .SE(dftIn), + .SI(registers_17__ap[8]) + ); + SDFF_X1_LVT \registers_reg[16][8] ( + .CK(n_0_46), .D(registers[8]), .Q(registers_16__ap[8]), .QN(), .SE(dftIn), + .SI(registers_15__ap[8]) + ); + AOI221_X1_LVT i_1_0_850( + .A(n_1_0_810), .B1(n_1_0_1294), .B2(registers_22__ap[8]), .C1(registers_16__ap[8]), + .C2(n_1_0_1267), .ZN(n_1_0_809) + ); + SDFF_X1_LVT \registers_reg[9][8] ( + .CK(n_0_39), .D(registers[8]), .Q(registers_9__ap[8]), .QN(), .SE(dftIn), + .SI(registers_5__ap[8]) + ); + SDFF_X1_LVT \registers_reg[1][8] ( + .CK(n_0_0), .D(registers[8]), .Q(registers_1__ap[8]), .QN(), .SE(dftIn), + .SI(registers_22__ap[8]) + ); + AOI22_X1_LVT i_1_0_849( + .A1(registers_9__ap[8]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[8]), + .ZN(n_1_0_808) + ); + SDFF_X1_LVT \registers_reg[6][8] ( + .CK(n_0_36), .D(registers[8]), .Q(registers_6__ap[8]), .QN(), .SE(dftIn), + .SI(registers_9__ap[8]) + ); + SDFF_X1_LVT \registers_reg[14][8] ( + .CK(n_0_44), .D(registers[8]), .Q(registers_14__ap[8]), .QN(), .SE(dftIn), + .SI(registers_16__ap[8]) + ); + AOI22_X1_LVT i_1_0_848( + .A1(registers_6__ap[8]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[8]), + .ZN(n_1_0_807) + ); + SDFF_X1_LVT \registers_reg[19][8] ( + .CK(n_0_49), .D(registers[8]), .Q(registers_19__ap[8]), .QN(), .SE(dftIn), + .SI(registers_1__ap[8]) + ); + SDFF_X1_LVT \registers_reg[2][8] ( + .CK(n_0_32), .D(registers[8]), .Q(registers_2__ap[8]), .QN(), .SE(dftIn), + .SI(registers_30__ap[8]) + ); + AOI22_X1_LVT i_1_0_847( + .A1(registers_19__ap[8]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[8]), + .ZN(n_1_0_806) + ); + NAND3_X1_LVT i_1_0_846( + .A1(n_1_0_808), .A2(n_1_0_807), .A3(n_1_0_806), .ZN(n_1_0_805) + ); + SDFF_X1_LVT \registers_reg[11][8] ( + .CK(n_0_41), .D(registers[8]), .Q(registers_11__ap[8]), .QN(), .SE(dftIn), + .SI(registers_14__ap[8]) + ); + SDFF_X1_LVT \registers_reg[27][8] ( + .CK(n_0_57), .D(registers[8]), .Q(registers_27__ap[8]), .QN(), .SE(dftIn), + .SI(registers_2__ap[8]) + ); + AOI221_X1_LVT i_1_0_845( + .A(n_1_0_805), .B1(n_1_0_1270), .B2(registers_11__ap[8]), .C1(registers_27__ap[8]), + .C2(n_1_0_1279), .ZN(n_1_0_804) + ); + NAND4_X1_LVT i_1_0_844( + .A1(n_1_0_819), .A2(n_1_0_814), .A3(n_1_0_809), .A4(n_1_0_804), .ZN(RRs1[8]) + ); + AND2_X1_LVT i_0_0_7( + .A1(n_0_0_16), .A2(WRd[7]), .ZN(registers[7]) + ); + SDFF_X1_LVT \registers_reg[13][7] ( + .CK(n_0_43), .D(registers[7]), .Q(registers_13__ap[7]), .QN(), .SE(dftIn), + .SI(registers_11__ap[8]) + ); + SDFF_X1_LVT \registers_reg[21][7] ( + .CK(n_0_51), .D(registers[7]), .Q(registers_21__ap[7]), .QN(), .SE(dftIn), + .SI(registers_19__ap[8]) + ); + AOI22_X1_LVT i_1_0_843( + .A1(registers_13__ap[7]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[7]), + .ZN(n_1_0_803) + ); + SDFF_X1_LVT \registers_reg[18][7] ( + .CK(n_0_48), .D(registers[7]), .Q(registers_18__ap[7]), .QN(), .SE(dftIn), + .SI(registers_21__ap[7]) + ); + SDFF_X1_LVT \registers_reg[10][7] ( + .CK(n_0_40), .D(registers[7]), .Q(registers_10__ap[7]), .QN(), .SE(dftIn), + .SI(registers_13__ap[7]) + ); + SDFF_X1_LVT \registers_reg[25][7] ( + .CK(n_0_55), .D(registers[7]), .Q(registers_25__ap[7]), .QN(), .SE(dftIn), + .SI(registers_27__ap[8]) + ); + AOI222_X1_LVT i_1_0_842( + .A1(registers_18__ap[7]), .A2(n_1_0_1297), .B1(n_1_0_1287), .B2(registers_10__ap[7]), + .C1(registers_25__ap[7]), .C2(n_1_0_1269), .ZN(n_1_0_802) + ); + SDFF_X1_LVT \registers_reg[28][7] ( + .CK(n_0_58), .D(registers[7]), .Q(registers_28__ap[7]), .QN(), .SE(dftIn), + .SI(registers_25__ap[7]) + ); + SDFF_X1_LVT \registers_reg[8][7] ( + .CK(n_0_38), .D(registers[7]), .Q(registers_8__ap[7]), .QN(), .SE(dftIn), + .SI(registers_6__ap[8]) + ); + AOI22_X1_LVT i_1_0_841( + .A1(registers_28__ap[7]), .A2(n_1_0_1283), .B1(n_1_0_1282), .B2(registers_8__ap[7]), + .ZN(n_1_0_801) + ); + SDFF_X1_LVT \registers_reg[24][7] ( + .CK(n_0_54), .D(registers[7]), .Q(registers_24__ap[7]), .QN(), .SE(dftIn), + .SI(registers_28__ap[7]) + ); + SDFF_X1_LVT \registers_reg[20][7] ( + .CK(n_0_50), .D(registers[7]), .Q(registers_20__ap[7]), .QN(), .SE(dftIn), + .SI(registers_18__ap[7]) + ); + AOI22_X1_LVT i_1_0_840( + .A1(registers_24__ap[7]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[7]), + .ZN(n_1_0_800) + ); + SDFF_X1_LVT \registers_reg[31][7] ( + .CK(n_0_61), .D(registers[7]), .Q(registers_31__ap[7]), .QN(), .SE(dftIn), + .SI(registers_8__ap[7]) + ); + SDFF_X1_LVT \registers_reg[7][7] ( + .CK(n_0_37), .D(registers[7]), .Q(registers_7__ap[7]), .QN(), .SE(dftIn), + .SI(registers_31__ap[7]) + ); + AOI22_X1_LVT i_1_0_839( + .A1(registers_31__ap[7]), .A2(n_1_0_1266), .B1(n_1_0_1263), .B2(registers_7__ap[7]), + .ZN(n_1_0_799) + ); + SDFF_X1_LVT \registers_reg[17][7] ( + .CK(n_0_47), .D(registers[7]), .Q(registers_17__ap[7]), .QN(), .SE(dftIn), + .SI(registers_20__ap[7]) + ); + SDFF_X1_LVT \registers_reg[11][7] ( + .CK(n_0_41), .D(registers[7]), .Q(registers_11__ap[7]), .QN(), .SE(dftIn), + .SI(registers_10__ap[7]) + ); + AOI22_X1_LVT i_1_0_838( + .A1(registers_17__ap[7]), .A2(n_1_0_1271), .B1(n_1_0_1270), .B2(registers_11__ap[7]), + .ZN(n_1_0_798) + ); + SDFF_X1_LVT \registers_reg[27][7] ( + .CK(n_0_57), .D(registers[7]), .Q(registers_27__ap[7]), .QN(), .SE(dftIn), + .SI(registers_24__ap[7]) + ); + SDFF_X1_LVT \registers_reg[29][7] ( + .CK(n_0_59), .D(registers[7]), .Q(registers_29__ap[7]), .QN(), .SE(dftIn), + .SI(registers_27__ap[7]) + ); + AOI22_X1_LVT i_1_0_837( + .A1(registers_27__ap[7]), .A2(n_1_0_1279), .B1(n_1_0_1276), .B2(registers_29__ap[7]), + .ZN(n_1_0_797) + ); + NAND4_X1_LVT i_1_0_836( + .A1(n_1_0_800), .A2(n_1_0_799), .A3(n_1_0_798), .A4(n_1_0_797), .ZN(n_1_0_796) + ); + SDFF_X1_LVT \registers_reg[26][7] ( + .CK(n_0_56), .D(registers[7]), .Q(registers_26__ap[7]), .QN(), .SE(dftIn), + .SI(registers_29__ap[7]) + ); + SDFF_X1_LVT \registers_reg[30][7] ( + .CK(n_0_60), .D(registers[7]), .Q(registers_30__ap[7]), .QN(), .SE(dftIn), + .SI(registers_26__ap[7]) + ); + AOI22_X1_LVT i_1_0_835( + .A1(registers_26__ap[7]), .A2(n_1_0_1285), .B1(n_1_0_1272), .B2(registers_30__ap[7]), + .ZN(n_1_0_795) + ); + SDFF_X1_LVT \registers_reg[4][7] ( + .CK(n_0_34), .D(registers[7]), .Q(registers_4__ap[7]), .QN(), .SE(dftIn), + .SI(registers_7__ap[7]) + ); + SDFF_X1_LVT \registers_reg[12][7] ( + .CK(n_0_42), .D(registers[7]), .Q(registers_12__ap[7]), .QN(), .SE(dftIn), + .SI(registers_11__ap[7]) + ); + AOI22_X1_LVT i_1_0_834( + .A1(registers_4__ap[7]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[7]), + .ZN(n_1_0_794) + ); + SDFF_X1_LVT \registers_reg[15][7] ( + .CK(n_0_45), .D(registers[7]), .Q(registers_15__ap[7]), .QN(), .SE(dftIn), + .SI(registers_12__ap[7]) + ); + SDFF_X1_LVT \registers_reg[16][7] ( + .CK(n_0_46), .D(registers[7]), .Q(registers_16__ap[7]), .QN(), .SE(dftIn), + .SI(registers_15__ap[7]) + ); + AOI22_X1_LVT i_1_0_833( + .A1(registers_15__ap[7]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[7]), + .ZN(n_1_0_793) + ); + SDFF_X1_LVT \registers_reg[22][7] ( + .CK(n_0_52), .D(registers[7]), .Q(registers_22__ap[7]), .QN(), .SE(dftIn), + .SI(registers_17__ap[7]) + ); + SDFF_X1_LVT \registers_reg[5][7] ( + .CK(n_0_35), .D(registers[7]), .Q(registers_5__ap[7]), .QN(), .SE(dftIn), + .SI(registers_4__ap[7]) + ); + AOI22_X1_LVT i_1_0_832( + .A1(registers_22__ap[7]), .A2(n_1_0_1294), .B1(n_1_0_1273), .B2(registers_5__ap[7]), + .ZN(n_1_0_792) + ); + NAND4_X1_LVT i_1_0_831( + .A1(n_1_0_795), .A2(n_1_0_794), .A3(n_1_0_793), .A4(n_1_0_792), .ZN(n_1_0_791) + ); + SDFF_X1_LVT \registers_reg[19][7] ( + .CK(n_0_49), .D(registers[7]), .Q(registers_19__ap[7]), .QN(), .SE(dftIn), + .SI(registers_22__ap[7]) + ); + SDFF_X1_LVT \registers_reg[3][7] ( + .CK(n_0_33), .D(registers[7]), .Q(registers_3__ap[7]), .QN(), .SE(dftIn), + .SI(registers_5__ap[7]) + ); + AOI22_X1_LVT i_1_0_830( + .A1(registers_19__ap[7]), .A2(n_1_0_1295), .B1(n_1_0_1257), .B2(registers_3__ap[7]), + .ZN(n_1_0_790) + ); + SDFF_X1_LVT \registers_reg[9][7] ( + .CK(n_0_39), .D(registers[7]), .Q(registers_9__ap[7]), .QN(), .SE(dftIn), + .SI(registers_3__ap[7]) + ); + SDFF_X1_LVT \registers_reg[1][7] ( + .CK(n_0_0), .D(registers[7]), .Q(registers_1__ap[7]), .QN(), .SE(dftIn), + .SI(registers_19__ap[7]) + ); + AOI22_X1_LVT i_1_0_829( + .A1(registers_9__ap[7]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[7]), + .ZN(n_1_0_789) + ); + SDFF_X1_LVT \registers_reg[6][7] ( + .CK(n_0_36), .D(registers[7]), .Q(registers_6__ap[7]), .QN(), .SE(dftIn), + .SI(registers_9__ap[7]) + ); + SDFF_X1_LVT \registers_reg[14][7] ( + .CK(n_0_44), .D(registers[7]), .Q(registers_14__ap[7]), .QN(), .SE(dftIn), + .SI(registers_16__ap[7]) + ); + AOI22_X1_LVT i_1_0_828( + .A1(registers_6__ap[7]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[7]), + .ZN(n_1_0_788) + ); + SDFF_X1_LVT \registers_reg[2][7] ( + .CK(n_0_32), .D(registers[7]), .Q(registers_2__ap[7]), .QN(), .SE(dftIn), + .SI(registers_30__ap[7]) + ); + SDFF_X1_LVT \registers_reg[23][7] ( + .CK(n_0_53), .D(registers[7]), .Q(registers_23__ap[7]), .QN(), .SE(dftIn), + .SI(registers_1__ap[7]) + ); + AOI22_X1_LVT i_1_0_827( + .A1(registers_2__ap[7]), .A2(n_1_0_1268), .B1(n_1_0_1264), .B2(registers_23__ap[7]), + .ZN(n_1_0_787) + ); + NAND4_X1_LVT i_1_0_826( + .A1(n_1_0_790), .A2(n_1_0_789), .A3(n_1_0_788), .A4(n_1_0_787), .ZN(n_1_0_786) + ); + NOR3_X1_LVT i_1_0_825( + .A1(n_1_0_796), .A2(n_1_0_791), .A3(n_1_0_786), .ZN(n_1_0_785) + ); + NAND4_X1_LVT i_1_0_824( + .A1(n_1_0_803), .A2(n_1_0_802), .A3(n_1_0_801), .A4(n_1_0_785), .ZN(RRs1[7]) + ); + AND2_X1_LVT i_0_0_6( + .A1(n_0_0_16), .A2(WRd[6]), .ZN(registers[6]) + ); + SDFF_X1_LVT \registers_reg[28][6] ( + .CK(n_0_58), .D(registers[6]), .Q(registers_28__ap[6]), .QN(), .SE(dftIn), + .SI(registers_2__ap[7]) + ); + SDFF_X1_LVT \registers_reg[17][6] ( + .CK(n_0_47), .D(registers[6]), .Q(registers_17__ap[6]), .QN(), .SE(dftIn), + .SI(registers_23__ap[7]) + ); + AOI22_X1_LVT i_1_0_823( + .A1(registers_28__ap[6]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[6]), + .ZN(n_1_0_784) + ); + SDFF_X1_LVT \registers_reg[18][6] ( + .CK(n_0_48), .D(registers[6]), .Q(registers_18__ap[6]), .QN(), .SE(dftIn), + .SI(registers_17__ap[6]) + ); + SDFF_X1_LVT \registers_reg[10][6] ( + .CK(n_0_40), .D(registers[6]), .Q(registers_10__ap[6]), .QN(), .SE(dftIn), + .SI(registers_14__ap[7]) + ); + SDFF_X1_LVT \registers_reg[8][6] ( + .CK(n_0_38), .D(registers[6]), .Q(registers_8__ap[6]), .QN(), .SE(dftIn), + .SI(registers_6__ap[7]) + ); + AOI222_X1_LVT i_1_0_822( + .A1(registers_18__ap[6]), .A2(n_1_0_1297), .B1(n_1_0_1287), .B2(registers_10__ap[6]), + .C1(registers_8__ap[6]), .C2(n_1_0_1282), .ZN(n_1_0_783) + ); + SDFF_X1_LVT \registers_reg[9][6] ( + .CK(n_0_39), .D(registers[6]), .Q(registers_9__ap[6]), .QN(), .SE(dftIn), + .SI(registers_8__ap[6]) + ); + SDFF_X1_LVT \registers_reg[29][6] ( + .CK(n_0_59), .D(registers[6]), .Q(registers_29__ap[6]), .QN(), .SE(dftIn), + .SI(registers_28__ap[6]) + ); + AOI22_X1_LVT i_1_0_821( + .A1(registers_9__ap[6]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[6]), + .ZN(n_1_0_782) + ); + SDFF_X1_LVT \registers_reg[6][6] ( + .CK(n_0_36), .D(registers[6]), .Q(registers_6__ap[6]), .QN(), .SE(dftIn), + .SI(registers_9__ap[6]) + ); + SDFF_X1_LVT \registers_reg[1][6] ( + .CK(n_0_0), .D(registers[6]), .Q(registers_1__ap[6]), .QN(), .SE(dftIn), + .SI(registers_18__ap[6]) + ); + AOI22_X1_LVT i_1_0_820( + .A1(registers_6__ap[6]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[6]), + .ZN(n_1_0_781) + ); + SDFF_X1_LVT \registers_reg[15][6] ( + .CK(n_0_45), .D(registers[6]), .Q(registers_15__ap[6]), .QN(), .SE(dftIn), + .SI(registers_10__ap[6]) + ); + SDFF_X1_LVT \registers_reg[27][6] ( + .CK(n_0_57), .D(registers[6]), .Q(registers_27__ap[6]), .QN(), .SE(dftIn), + .SI(registers_29__ap[6]) + ); + AOI22_X1_LVT i_1_0_819( + .A1(registers_15__ap[6]), .A2(n_1_0_1286), .B1(n_1_0_1279), .B2(registers_27__ap[6]), + .ZN(n_1_0_780) + ); + SDFF_X1_LVT \registers_reg[11][6] ( + .CK(n_0_41), .D(registers[6]), .Q(registers_11__ap[6]), .QN(), .SE(dftIn), + .SI(registers_15__ap[6]) + ); + SDFF_X1_LVT \registers_reg[16][6] ( + .CK(n_0_46), .D(registers[6]), .Q(registers_16__ap[6]), .QN(), .SE(dftIn), + .SI(registers_11__ap[6]) + ); + AOI22_X1_LVT i_1_0_818( + .A1(registers_11__ap[6]), .A2(n_1_0_1270), .B1(n_1_0_1267), .B2(registers_16__ap[6]), + .ZN(n_1_0_779) + ); + SDFF_X1_LVT \registers_reg[5][6] ( + .CK(n_0_35), .D(registers[6]), .Q(registers_5__ap[6]), .QN(), .SE(dftIn), + .SI(registers_6__ap[6]) + ); + SDFF_X1_LVT \registers_reg[31][6] ( + .CK(n_0_61), .D(registers[6]), .Q(registers_31__ap[6]), .QN(), .SE(dftIn), + .SI(registers_5__ap[6]) + ); + AOI22_X1_LVT i_1_0_817( + .A1(registers_5__ap[6]), .A2(n_1_0_1273), .B1(n_1_0_1266), .B2(registers_31__ap[6]), + .ZN(n_1_0_778) + ); + NAND4_X1_LVT i_1_0_816( + .A1(n_1_0_781), .A2(n_1_0_780), .A3(n_1_0_779), .A4(n_1_0_778), .ZN(n_1_0_777) + ); + SDFF_X1_LVT \registers_reg[26][6] ( + .CK(n_0_56), .D(registers[6]), .Q(registers_26__ap[6]), .QN(), .SE(dftIn), + .SI(registers_27__ap[6]) + ); + SDFF_X1_LVT \registers_reg[30][6] ( + .CK(n_0_60), .D(registers[6]), .Q(registers_30__ap[6]), .QN(), .SE(dftIn), + .SI(registers_26__ap[6]) + ); + AOI22_X1_LVT i_1_0_815( + .A1(registers_26__ap[6]), .A2(n_1_0_1285), .B1(n_1_0_1272), .B2(registers_30__ap[6]), + .ZN(n_1_0_776) + ); + SDFF_X1_LVT \registers_reg[20][6] ( + .CK(n_0_50), .D(registers[6]), .Q(registers_20__ap[6]), .QN(), .SE(dftIn), + .SI(registers_1__ap[6]) + ); + SDFF_X1_LVT \registers_reg[4][6] ( + .CK(n_0_34), .D(registers[6]), .Q(registers_4__ap[6]), .QN(), .SE(dftIn), + .SI(registers_31__ap[6]) + ); + AOI22_X1_LVT i_1_0_814( + .A1(registers_20__ap[6]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[6]), + .ZN(n_1_0_775) + ); + SDFF_X1_LVT \registers_reg[22][6] ( + .CK(n_0_52), .D(registers[6]), .Q(registers_22__ap[6]), .QN(), .SE(dftIn), + .SI(registers_20__ap[6]) + ); + SDFF_X1_LVT \registers_reg[21][6] ( + .CK(n_0_51), .D(registers[6]), .Q(registers_21__ap[6]), .QN(), .SE(dftIn), + .SI(registers_22__ap[6]) + ); + AOI22_X1_LVT i_1_0_813( + .A1(registers_22__ap[6]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[6]), + .ZN(n_1_0_774) + ); + SDFF_X1_LVT \registers_reg[24][6] ( + .CK(n_0_54), .D(registers[6]), .Q(registers_24__ap[6]), .QN(), .SE(dftIn), + .SI(registers_30__ap[6]) + ); + SDFF_X1_LVT \registers_reg[12][6] ( + .CK(n_0_42), .D(registers[6]), .Q(registers_12__ap[6]), .QN(), .SE(dftIn), + .SI(registers_16__ap[6]) + ); + AOI22_X1_LVT i_1_0_812( + .A1(registers_24__ap[6]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[6]), + .ZN(n_1_0_773) + ); + NAND4_X1_LVT i_1_0_811( + .A1(n_1_0_776), .A2(n_1_0_775), .A3(n_1_0_774), .A4(n_1_0_773), .ZN(n_1_0_772) + ); + SDFF_X1_LVT \registers_reg[13][6] ( + .CK(n_0_43), .D(registers[6]), .Q(registers_13__ap[6]), .QN(), .SE(dftIn), + .SI(registers_12__ap[6]) + ); + SDFF_X1_LVT \registers_reg[25][6] ( + .CK(n_0_55), .D(registers[6]), .Q(registers_25__ap[6]), .QN(), .SE(dftIn), + .SI(registers_24__ap[6]) + ); + AOI22_X1_LVT i_1_0_810( + .A1(registers_13__ap[6]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[6]), + .ZN(n_1_0_771) + ); + SDFF_X1_LVT \registers_reg[7][6] ( + .CK(n_0_37), .D(registers[6]), .Q(registers_7__ap[6]), .QN(), .SE(dftIn), + .SI(registers_4__ap[6]) + ); + SDFF_X1_LVT \registers_reg[14][6] ( + .CK(n_0_44), .D(registers[6]), .Q(registers_14__ap[6]), .QN(), .SE(dftIn), + .SI(registers_13__ap[6]) + ); + AOI22_X1_LVT i_1_0_809( + .A1(registers_7__ap[6]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[6]), + .ZN(n_1_0_770) + ); + SDFF_X1_LVT \registers_reg[19][6] ( + .CK(n_0_49), .D(registers[6]), .Q(registers_19__ap[6]), .QN(), .SE(dftIn), + .SI(registers_21__ap[6]) + ); + SDFF_X1_LVT \registers_reg[3][6] ( + .CK(n_0_33), .D(registers[6]), .Q(registers_3__ap[6]), .QN(), .SE(dftIn), + .SI(registers_7__ap[6]) + ); + AOI22_X1_LVT i_1_0_808( + .A1(registers_19__ap[6]), .A2(n_1_0_1295), .B1(n_1_0_1257), .B2(registers_3__ap[6]), + .ZN(n_1_0_769) + ); + SDFF_X1_LVT \registers_reg[2][6] ( + .CK(n_0_32), .D(registers[6]), .Q(registers_2__ap[6]), .QN(), .SE(dftIn), + .SI(registers_25__ap[6]) + ); + SDFF_X1_LVT \registers_reg[23][6] ( + .CK(n_0_53), .D(registers[6]), .Q(registers_23__ap[6]), .QN(), .SE(dftIn), + .SI(registers_19__ap[6]) + ); + AOI22_X1_LVT i_1_0_807( + .A1(registers_2__ap[6]), .A2(n_1_0_1268), .B1(n_1_0_1264), .B2(registers_23__ap[6]), + .ZN(n_1_0_768) + ); + NAND4_X1_LVT i_1_0_806( + .A1(n_1_0_771), .A2(n_1_0_770), .A3(n_1_0_769), .A4(n_1_0_768), .ZN(n_1_0_767) + ); + NOR3_X1_LVT i_1_0_805( + .A1(n_1_0_777), .A2(n_1_0_772), .A3(n_1_0_767), .ZN(n_1_0_766) + ); + NAND4_X1_LVT i_1_0_804( + .A1(n_1_0_784), .A2(n_1_0_783), .A3(n_1_0_782), .A4(n_1_0_766), .ZN(RRs1[6]) + ); + AND2_X1_LVT i_0_0_5( + .A1(n_0_0_16), .A2(WRd[5]), .ZN(registers[5]) + ); + SDFF_X1_LVT \registers_reg[28][5] ( + .CK(n_0_58), .D(registers[5]), .Q(registers_28__ap[5]), .QN(), .SE(dftIn), + .SI(registers_2__ap[6]) + ); + SDFF_X1_LVT \registers_reg[4][5] ( + .CK(n_0_34), .D(registers[5]), .Q(registers_4__ap[5]), .QN(), .SE(dftIn), + .SI(registers_3__ap[6]) + ); + AOI22_X1_LVT i_1_0_803( + .A1(registers_28__ap[5]), .A2(n_1_0_1283), .B1(n_1_0_1278), .B2(registers_4__ap[5]), + .ZN(n_1_0_765) + ); + SDFF_X1_LVT \registers_reg[10][5] ( + .CK(n_0_40), .D(registers[5]), .Q(registers_10__ap[5]), .QN(), .SE(dftIn), + .SI(registers_14__ap[6]) + ); + SDFF_X1_LVT \registers_reg[26][5] ( + .CK(n_0_56), .D(registers[5]), .Q(registers_26__ap[5]), .QN(), .SE(dftIn), + .SI(registers_28__ap[5]) + ); + SDFF_X1_LVT \registers_reg[8][5] ( + .CK(n_0_38), .D(registers[5]), .Q(registers_8__ap[5]), .QN(), .SE(dftIn), + .SI(registers_4__ap[5]) + ); + AOI222_X1_LVT i_1_0_802( + .A1(registers_10__ap[5]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[5]), + .C1(registers_8__ap[5]), .C2(n_1_0_1282), .ZN(n_1_0_764) + ); + SDFF_X1_LVT \registers_reg[9][5] ( + .CK(n_0_39), .D(registers[5]), .Q(registers_9__ap[5]), .QN(), .SE(dftIn), + .SI(registers_8__ap[5]) + ); + SDFF_X1_LVT \registers_reg[29][5] ( + .CK(n_0_59), .D(registers[5]), .Q(registers_29__ap[5]), .QN(), .SE(dftIn), + .SI(registers_26__ap[5]) + ); + AOI22_X1_LVT i_1_0_801( + .A1(registers_9__ap[5]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[5]), + .ZN(n_1_0_763) + ); + SDFF_X1_LVT \registers_reg[6][5] ( + .CK(n_0_36), .D(registers[5]), .Q(registers_6__ap[5]), .QN(), .SE(dftIn), + .SI(registers_9__ap[5]) + ); + SDFF_X1_LVT \registers_reg[1][5] ( + .CK(n_0_0), .D(registers[5]), .Q(registers_1__ap[5]), .QN(), .SE(dftIn), + .SI(registers_23__ap[6]) + ); + AOI22_X1_LVT i_1_0_800( + .A1(registers_6__ap[5]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[5]), + .ZN(n_1_0_762) + ); + SDFF_X1_LVT \registers_reg[16][5] ( + .CK(n_0_46), .D(registers[5]), .Q(registers_16__ap[5]), .QN(), .SE(dftIn), + .SI(registers_10__ap[5]) + ); + SDFF_X1_LVT \registers_reg[3][5] ( + .CK(n_0_33), .D(registers[5]), .Q(registers_3__ap[5]), .QN(), .SE(dftIn), + .SI(registers_6__ap[5]) + ); + AOI22_X1_LVT i_1_0_799( + .A1(registers_16__ap[5]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[5]), + .ZN(n_1_0_761) + ); + SDFF_X1_LVT \registers_reg[5][5] ( + .CK(n_0_35), .D(registers[5]), .Q(registers_5__ap[5]), .QN(), .SE(dftIn), + .SI(registers_3__ap[5]) + ); + SDFF_X1_LVT \registers_reg[31][5] ( + .CK(n_0_61), .D(registers[5]), .Q(registers_31__ap[5]), .QN(), .SE(dftIn), + .SI(registers_5__ap[5]) + ); + AOI22_X1_LVT i_1_0_798( + .A1(registers_5__ap[5]), .A2(n_1_0_1273), .B1(n_1_0_1266), .B2(registers_31__ap[5]), + .ZN(n_1_0_760) + ); + SDFF_X1_LVT \registers_reg[15][5] ( + .CK(n_0_45), .D(registers[5]), .Q(registers_15__ap[5]), .QN(), .SE(dftIn), + .SI(registers_16__ap[5]) + ); + SDFF_X1_LVT \registers_reg[23][5] ( + .CK(n_0_53), .D(registers[5]), .Q(registers_23__ap[5]), .QN(), .SE(dftIn), + .SI(registers_1__ap[5]) + ); + AOI22_X1_LVT i_1_0_797( + .A1(registers_15__ap[5]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[5]), + .ZN(n_1_0_759) + ); + NAND4_X1_LVT i_1_0_796( + .A1(n_1_0_762), .A2(n_1_0_761), .A3(n_1_0_760), .A4(n_1_0_759), .ZN(n_1_0_758) + ); + SDFF_X1_LVT \registers_reg[18][5] ( + .CK(n_0_48), .D(registers[5]), .Q(registers_18__ap[5]), .QN(), .SE(dftIn), + .SI(registers_23__ap[5]) + ); + SDFF_X1_LVT \registers_reg[30][5] ( + .CK(n_0_60), .D(registers[5]), .Q(registers_30__ap[5]), .QN(), .SE(dftIn), + .SI(registers_29__ap[5]) + ); + AOI22_X1_LVT i_1_0_795( + .A1(registers_18__ap[5]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[5]), + .ZN(n_1_0_757) + ); + SDFF_X1_LVT \registers_reg[24][5] ( + .CK(n_0_54), .D(registers[5]), .Q(registers_24__ap[5]), .QN(), .SE(dftIn), + .SI(registers_30__ap[5]) + ); + SDFF_X1_LVT \registers_reg[12][5] ( + .CK(n_0_42), .D(registers[5]), .Q(registers_12__ap[5]), .QN(), .SE(dftIn), + .SI(registers_15__ap[5]) + ); + AOI22_X1_LVT i_1_0_794( + .A1(registers_24__ap[5]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[5]), + .ZN(n_1_0_756) + ); + SDFF_X1_LVT \registers_reg[22][5] ( + .CK(n_0_52), .D(registers[5]), .Q(registers_22__ap[5]), .QN(), .SE(dftIn), + .SI(registers_18__ap[5]) + ); + SDFF_X1_LVT \registers_reg[21][5] ( + .CK(n_0_51), .D(registers[5]), .Q(registers_21__ap[5]), .QN(), .SE(dftIn), + .SI(registers_22__ap[5]) + ); + AOI22_X1_LVT i_1_0_793( + .A1(registers_22__ap[5]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[5]), + .ZN(n_1_0_755) + ); + SDFF_X1_LVT \registers_reg[20][5] ( + .CK(n_0_50), .D(registers[5]), .Q(registers_20__ap[5]), .QN(), .SE(dftIn), + .SI(registers_21__ap[5]) + ); + SDFF_X1_LVT \registers_reg[17][5] ( + .CK(n_0_47), .D(registers[5]), .Q(registers_17__ap[5]), .QN(), .SE(dftIn), + .SI(registers_20__ap[5]) + ); + AOI22_X1_LVT i_1_0_792( + .A1(registers_20__ap[5]), .A2(n_1_0_1281), .B1(n_1_0_1271), .B2(registers_17__ap[5]), + .ZN(n_1_0_754) + ); + NAND4_X1_LVT i_1_0_791( + .A1(n_1_0_757), .A2(n_1_0_756), .A3(n_1_0_755), .A4(n_1_0_754), .ZN(n_1_0_753) + ); + SDFF_X1_LVT \registers_reg[13][5] ( + .CK(n_0_43), .D(registers[5]), .Q(registers_13__ap[5]), .QN(), .SE(dftIn), + .SI(registers_12__ap[5]) + ); + SDFF_X1_LVT \registers_reg[25][5] ( + .CK(n_0_55), .D(registers[5]), .Q(registers_25__ap[5]), .QN(), .SE(dftIn), + .SI(registers_24__ap[5]) + ); + AOI22_X1_LVT i_1_0_790( + .A1(registers_13__ap[5]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[5]), + .ZN(n_1_0_752) + ); + SDFF_X1_LVT \registers_reg[19][5] ( + .CK(n_0_49), .D(registers[5]), .Q(registers_19__ap[5]), .QN(), .SE(dftIn), + .SI(registers_17__ap[5]) + ); + SDFF_X1_LVT \registers_reg[2][5] ( + .CK(n_0_32), .D(registers[5]), .Q(registers_2__ap[5]), .QN(), .SE(dftIn), + .SI(registers_25__ap[5]) + ); + AOI22_X1_LVT i_1_0_789( + .A1(registers_19__ap[5]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[5]), + .ZN(n_1_0_751) + ); + SDFF_X1_LVT \registers_reg[7][5] ( + .CK(n_0_37), .D(registers[5]), .Q(registers_7__ap[5]), .QN(), .SE(dftIn), + .SI(registers_31__ap[5]) + ); + SDFF_X1_LVT \registers_reg[14][5] ( + .CK(n_0_44), .D(registers[5]), .Q(registers_14__ap[5]), .QN(), .SE(dftIn), + .SI(registers_13__ap[5]) + ); + AOI22_X1_LVT i_1_0_788( + .A1(registers_7__ap[5]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[5]), + .ZN(n_1_0_750) + ); + SDFF_X1_LVT \registers_reg[27][5] ( + .CK(n_0_57), .D(registers[5]), .Q(registers_27__ap[5]), .QN(), .SE(dftIn), + .SI(registers_2__ap[5]) + ); + SDFF_X1_LVT \registers_reg[11][5] ( + .CK(n_0_41), .D(registers[5]), .Q(registers_11__ap[5]), .QN(), .SE(dftIn), + .SI(registers_14__ap[5]) + ); + AOI22_X1_LVT i_1_0_787( + .A1(registers_27__ap[5]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[5]), + .ZN(n_1_0_749) + ); + NAND4_X1_LVT i_1_0_786( + .A1(n_1_0_752), .A2(n_1_0_751), .A3(n_1_0_750), .A4(n_1_0_749), .ZN(n_1_0_748) + ); + NOR3_X1_LVT i_1_0_785( + .A1(n_1_0_758), .A2(n_1_0_753), .A3(n_1_0_748), .ZN(n_1_0_747) + ); + NAND4_X1_LVT i_1_0_784( + .A1(n_1_0_765), .A2(n_1_0_764), .A3(n_1_0_763), .A4(n_1_0_747), .ZN(RRs1[5]) + ); + AND2_X1_LVT i_0_0_4( + .A1(n_0_0_16), .A2(WRd[4]), .ZN(registers[4]) + ); + SDFF_X1_LVT \registers_reg[10][4] ( + .CK(n_0_40), .D(registers[4]), .Q(registers_10__ap[4]), .QN(), .SE(dftIn), + .SI(registers_11__ap[5]) + ); + SDFF_X1_LVT \registers_reg[21][4] ( + .CK(n_0_51), .D(registers[4]), .Q(registers_21__ap[4]), .QN(), .SE(dftIn), + .SI(registers_19__ap[5]) + ); + AOI22_X1_LVT i_1_0_783( + .A1(registers_10__ap[4]), .A2(n_1_0_1287), .B1(n_1_0_1259), .B2(registers_21__ap[4]), + .ZN(n_1_0_746) + ); + SDFF_X1_LVT \registers_reg[9][4] ( + .CK(n_0_39), .D(registers[4]), .Q(registers_9__ap[4]), .QN(), .SE(dftIn), + .SI(registers_7__ap[5]) + ); + SDFF_X1_LVT \registers_reg[1][4] ( + .CK(n_0_0), .D(registers[4]), .Q(registers_1__ap[4]), .QN(), .SE(dftIn), + .SI(registers_21__ap[4]) + ); + AOI22_X1_LVT i_1_0_778( + .A1(registers_9__ap[4]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[4]), + .ZN(n_1_0_741) + ); + SDFF_X1_LVT \registers_reg[18][4] ( + .CK(n_0_48), .D(registers[4]), .Q(registers_18__ap[4]), .QN(), .SE(dftIn), + .SI(registers_1__ap[4]) + ); + SDFF_X1_LVT \registers_reg[8][4] ( + .CK(n_0_38), .D(registers[4]), .Q(registers_8__ap[4]), .QN(), .SE(dftIn), + .SI(registers_9__ap[4]) + ); + AOI22_X1_LVT i_1_0_777( + .A1(registers_18__ap[4]), .A2(n_1_0_1297), .B1(n_1_0_1282), .B2(registers_8__ap[4]), + .ZN(n_1_0_740) + ); + NAND3_X1_LVT i_1_0_775( + .A1(n_1_0_746), .A2(n_1_0_741), .A3(n_1_0_740), .ZN(n_1_0_738) + ); + SDFF_X1_LVT \registers_reg[22][4] ( + .CK(n_0_52), .D(registers[4]), .Q(registers_22__ap[4]), .QN(), .SE(dftIn), + .SI(registers_18__ap[4]) + ); + SDFF_X1_LVT \registers_reg[23][4] ( + .CK(n_0_53), .D(registers[4]), .Q(registers_23__ap[4]), .QN(), .SE(dftIn), + .SI(registers_22__ap[4]) + ); + AOI221_X1_LVT i_1_0_774( + .A(n_1_0_738), .B1(n_1_0_1294), .B2(registers_22__ap[4]), .C1(registers_23__ap[4]), + .C2(n_1_0_1264), .ZN(n_1_0_737) + ); + SDFF_X1_LVT \registers_reg[28][4] ( + .CK(n_0_58), .D(registers[4]), .Q(registers_28__ap[4]), .QN(), .SE(dftIn), + .SI(registers_27__ap[5]) + ); + SDFF_X1_LVT \registers_reg[20][4] ( + .CK(n_0_50), .D(registers[4]), .Q(registers_20__ap[4]), .QN(), .SE(dftIn), + .SI(registers_23__ap[4]) + ); + AOI22_X1_LVT i_1_0_782( + .A1(registers_28__ap[4]), .A2(n_1_0_1283), .B1(n_1_0_1281), .B2(registers_20__ap[4]), + .ZN(n_1_0_745) + ); + SDFF_X1_LVT \registers_reg[19][4] ( + .CK(n_0_49), .D(registers[4]), .Q(registers_19__ap[4]), .QN(), .SE(dftIn), + .SI(registers_20__ap[4]) + ); + SDFF_X1_LVT \registers_reg[13][4] ( + .CK(n_0_43), .D(registers[4]), .Q(registers_13__ap[4]), .QN(), .SE(dftIn), + .SI(registers_10__ap[4]) + ); + AOI22_X1_LVT i_1_0_780( + .A1(registers_19__ap[4]), .A2(n_1_0_1295), .B1(n_1_0_1277), .B2(registers_13__ap[4]), + .ZN(n_1_0_743) + ); + SDFF_X1_LVT \registers_reg[26][4] ( + .CK(n_0_56), .D(registers[4]), .Q(registers_26__ap[4]), .QN(), .SE(dftIn), + .SI(registers_28__ap[4]) + ); + SDFF_X1_LVT \registers_reg[3][4] ( + .CK(n_0_33), .D(registers[4]), .Q(registers_3__ap[4]), .QN(), .SE(dftIn), + .SI(registers_8__ap[4]) + ); + AOI22_X1_LVT i_1_0_776( + .A1(registers_26__ap[4]), .A2(n_1_0_1285), .B1(n_1_0_1257), .B2(registers_3__ap[4]), + .ZN(n_1_0_739) + ); + NAND3_X1_LVT i_1_0_773( + .A1(n_1_0_745), .A2(n_1_0_743), .A3(n_1_0_739), .ZN(n_1_0_736) + ); + SDFF_X1_LVT \registers_reg[30][4] ( + .CK(n_0_60), .D(registers[4]), .Q(registers_30__ap[4]), .QN(), .SE(dftIn), + .SI(registers_26__ap[4]) + ); + SDFF_X1_LVT \registers_reg[31][4] ( + .CK(n_0_61), .D(registers[4]), .Q(registers_31__ap[4]), .QN(), .SE(dftIn), + .SI(registers_3__ap[4]) + ); + AOI221_X1_LVT i_1_0_772( + .A(n_1_0_736), .B1(n_1_0_1272), .B2(registers_30__ap[4]), .C1(registers_31__ap[4]), + .C2(n_1_0_1266), .ZN(n_1_0_735) + ); + SDFF_X1_LVT \registers_reg[24][4] ( + .CK(n_0_54), .D(registers[4]), .Q(registers_24__ap[4]), .QN(), .SE(dftIn), + .SI(registers_30__ap[4]) + ); + SDFF_X1_LVT \registers_reg[12][4] ( + .CK(n_0_42), .D(registers[4]), .Q(registers_12__ap[4]), .QN(), .SE(dftIn), + .SI(registers_13__ap[4]) + ); + AOI22_X1_LVT i_1_0_781( + .A1(registers_24__ap[4]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[4]), + .ZN(n_1_0_744) + ); + SDFF_X1_LVT \registers_reg[27][4] ( + .CK(n_0_57), .D(registers[4]), .Q(registers_27__ap[4]), .QN(), .SE(dftIn), + .SI(registers_24__ap[4]) + ); + SDFF_X1_LVT \registers_reg[11][4] ( + .CK(n_0_41), .D(registers[4]), .Q(registers_11__ap[4]), .QN(), .SE(dftIn), + .SI(registers_12__ap[4]) + ); + AOI22_X1_LVT i_1_0_779( + .A1(registers_27__ap[4]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[4]), + .ZN(n_1_0_742) + ); + SDFF_X1_LVT \registers_reg[17][4] ( + .CK(n_0_47), .D(registers[4]), .Q(registers_17__ap[4]), .QN(), .SE(dftIn), + .SI(registers_19__ap[4]) + ); + SDFF_X1_LVT \registers_reg[7][4] ( + .CK(n_0_37), .D(registers[4]), .Q(registers_7__ap[4]), .QN(), .SE(dftIn), + .SI(registers_31__ap[4]) + ); + SDFF_X1_LVT \registers_reg[14][4] ( + .CK(n_0_44), .D(registers[4]), .Q(registers_14__ap[4]), .QN(), .SE(dftIn), + .SI(registers_11__ap[4]) + ); + AOI222_X1_LVT i_1_0_771( + .A1(registers_17__ap[4]), .A2(n_1_0_1271), .B1(n_1_0_1263), .B2(registers_7__ap[4]), + .C1(n_1_0_1258), .C2(registers_14__ap[4]), .ZN(n_1_0_734) + ); + SDFF_X1_LVT \registers_reg[15][4] ( + .CK(n_0_45), .D(registers[4]), .Q(registers_15__ap[4]), .QN(), .SE(dftIn), + .SI(registers_14__ap[4]) + ); + SDFF_X1_LVT \registers_reg[16][4] ( + .CK(n_0_46), .D(registers[4]), .Q(registers_16__ap[4]), .QN(), .SE(dftIn), + .SI(registers_15__ap[4]) + ); + AOI22_X1_LVT i_1_0_770( + .A1(registers_15__ap[4]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[4]), + .ZN(n_1_0_733) + ); + SDFF_X1_LVT \registers_reg[4][4] ( + .CK(n_0_34), .D(registers[4]), .Q(registers_4__ap[4]), .QN(), .SE(dftIn), + .SI(registers_7__ap[4]) + ); + SDFF_X1_LVT \registers_reg[25][4] ( + .CK(n_0_55), .D(registers[4]), .Q(registers_25__ap[4]), .QN(), .SE(dftIn), + .SI(registers_27__ap[4]) + ); + AOI22_X1_LVT i_1_0_769( + .A1(registers_4__ap[4]), .A2(n_1_0_1278), .B1(n_1_0_1269), .B2(registers_25__ap[4]), + .ZN(n_1_0_732) + ); + SDFF_X1_LVT \registers_reg[29][4] ( + .CK(n_0_59), .D(registers[4]), .Q(registers_29__ap[4]), .QN(), .SE(dftIn), + .SI(registers_25__ap[4]) + ); + SDFF_X1_LVT \registers_reg[2][4] ( + .CK(n_0_32), .D(registers[4]), .Q(registers_2__ap[4]), .QN(), .SE(dftIn), + .SI(registers_29__ap[4]) + ); + AOI22_X1_LVT i_1_0_768( + .A1(registers_29__ap[4]), .A2(n_1_0_1276), .B1(n_1_0_1268), .B2(registers_2__ap[4]), + .ZN(n_1_0_731) + ); + NAND3_X1_LVT i_1_0_767( + .A1(n_1_0_733), .A2(n_1_0_732), .A3(n_1_0_731), .ZN(n_1_0_730) + ); + SDFF_X1_LVT \registers_reg[6][4] ( + .CK(n_0_36), .D(registers[4]), .Q(registers_6__ap[4]), .QN(), .SE(dftIn), + .SI(registers_4__ap[4]) + ); + SDFF_X1_LVT \registers_reg[5][4] ( + .CK(n_0_35), .D(registers[4]), .Q(registers_5__ap[4]), .QN(), .SE(dftIn), + .SI(registers_6__ap[4]) + ); + AOI221_X1_LVT i_1_0_766( + .A(n_1_0_730), .B1(n_1_0_1300), .B2(registers_6__ap[4]), .C1(registers_5__ap[4]), + .C2(n_1_0_1273), .ZN(n_1_0_729) + ); + AND4_X1_LVT i_1_0_765( + .A1(n_1_0_744), .A2(n_1_0_742), .A3(n_1_0_734), .A4(n_1_0_729), .ZN(n_1_0_728) + ); + NAND3_X1_LVT i_1_0_764( + .A1(n_1_0_737), .A2(n_1_0_735), .A3(n_1_0_728), .ZN(RRs1[4]) + ); + AND2_X1_LVT i_0_0_3( + .A1(n_0_0_16), .A2(WRd[3]), .ZN(registers[3]) + ); + SDFF_X1_LVT \registers_reg[28][3] ( + .CK(n_0_58), .D(registers[3]), .Q(registers_28__ap[3]), .QN(), .SE(dftIn), + .SI(registers_2__ap[4]) + ); + SDFF_X1_LVT \registers_reg[17][3] ( + .CK(n_0_47), .D(registers[3]), .Q(registers_17__ap[3]), .QN(), .SE(dftIn), + .SI(registers_17__ap[4]) + ); + AOI22_X1_LVT i_1_0_763( + .A1(registers_28__ap[3]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[3]), + .ZN(n_1_0_727) + ); + SDFF_X1_LVT \registers_reg[10][3] ( + .CK(n_0_40), .D(registers[3]), .Q(registers_10__ap[3]), .QN(), .SE(dftIn), + .SI(registers_16__ap[4]) + ); + SDFF_X1_LVT \registers_reg[26][3] ( + .CK(n_0_56), .D(registers[3]), .Q(registers_26__ap[3]), .QN(), .SE(dftIn), + .SI(registers_28__ap[3]) + ); + SDFF_X1_LVT \registers_reg[8][3] ( + .CK(n_0_38), .D(registers[3]), .Q(registers_8__ap[3]), .QN(), .SE(dftIn), + .SI(registers_5__ap[4]) + ); + AOI222_X1_LVT i_1_0_762( + .A1(registers_10__ap[3]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[3]), + .C1(registers_8__ap[3]), .C2(n_1_0_1282), .ZN(n_1_0_726) + ); + SDFF_X1_LVT \registers_reg[9][3] ( + .CK(n_0_39), .D(registers[3]), .Q(registers_9__ap[3]), .QN(), .SE(dftIn), + .SI(registers_8__ap[3]) + ); + SDFF_X1_LVT \registers_reg[29][3] ( + .CK(n_0_59), .D(registers[3]), .Q(registers_29__ap[3]), .QN(), .SE(dftIn), + .SI(registers_26__ap[3]) + ); + AOI22_X1_LVT i_1_0_761( + .A1(registers_9__ap[3]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[3]), + .ZN(n_1_0_725) + ); + SDFF_X1_LVT \registers_reg[6][3] ( + .CK(n_0_36), .D(registers[3]), .Q(registers_6__ap[3]), .QN(), .SE(dftIn), + .SI(registers_9__ap[3]) + ); + SDFF_X1_LVT \registers_reg[1][3] ( + .CK(n_0_0), .D(registers[3]), .Q(registers_1__ap[3]), .QN(), .SE(dftIn), + .SI(registers_17__ap[3]) + ); + AOI22_X1_LVT i_1_0_760( + .A1(registers_6__ap[3]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[3]), + .ZN(n_1_0_724) + ); + SDFF_X1_LVT \registers_reg[16][3] ( + .CK(n_0_46), .D(registers[3]), .Q(registers_16__ap[3]), .QN(), .SE(dftIn), + .SI(registers_10__ap[3]) + ); + SDFF_X1_LVT \registers_reg[3][3] ( + .CK(n_0_33), .D(registers[3]), .Q(registers_3__ap[3]), .QN(), .SE(dftIn), + .SI(registers_6__ap[3]) + ); + AOI22_X1_LVT i_1_0_759( + .A1(registers_16__ap[3]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[3]), + .ZN(n_1_0_723) + ); + SDFF_X1_LVT \registers_reg[5][3] ( + .CK(n_0_35), .D(registers[3]), .Q(registers_5__ap[3]), .QN(), .SE(dftIn), + .SI(registers_3__ap[3]) + ); + SDFF_X1_LVT \registers_reg[31][3] ( + .CK(n_0_61), .D(registers[3]), .Q(registers_31__ap[3]), .QN(), .SE(dftIn), + .SI(registers_5__ap[3]) + ); + AOI22_X1_LVT i_1_0_758( + .A1(registers_5__ap[3]), .A2(n_1_0_1273), .B1(n_1_0_1266), .B2(registers_31__ap[3]), + .ZN(n_1_0_722) + ); + SDFF_X1_LVT \registers_reg[15][3] ( + .CK(n_0_45), .D(registers[3]), .Q(registers_15__ap[3]), .QN(), .SE(dftIn), + .SI(registers_16__ap[3]) + ); + SDFF_X1_LVT \registers_reg[23][3] ( + .CK(n_0_53), .D(registers[3]), .Q(registers_23__ap[3]), .QN(), .SE(dftIn), + .SI(registers_1__ap[3]) + ); + AOI22_X1_LVT i_1_0_757( + .A1(registers_15__ap[3]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[3]), + .ZN(n_1_0_721) + ); + NAND4_X1_LVT i_1_0_756( + .A1(n_1_0_724), .A2(n_1_0_723), .A3(n_1_0_722), .A4(n_1_0_721), .ZN(n_1_0_720) + ); + SDFF_X1_LVT \registers_reg[18][3] ( + .CK(n_0_48), .D(registers[3]), .Q(registers_18__ap[3]), .QN(), .SE(dftIn), + .SI(registers_23__ap[3]) + ); + SDFF_X1_LVT \registers_reg[30][3] ( + .CK(n_0_60), .D(registers[3]), .Q(registers_30__ap[3]), .QN(), .SE(dftIn), + .SI(registers_29__ap[3]) + ); + AOI22_X1_LVT i_1_0_755( + .A1(registers_18__ap[3]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[3]), + .ZN(n_1_0_719) + ); + SDFF_X1_LVT \registers_reg[20][3] ( + .CK(n_0_50), .D(registers[3]), .Q(registers_20__ap[3]), .QN(), .SE(dftIn), + .SI(registers_18__ap[3]) + ); + SDFF_X1_LVT \registers_reg[4][3] ( + .CK(n_0_34), .D(registers[3]), .Q(registers_4__ap[3]), .QN(), .SE(dftIn), + .SI(registers_31__ap[3]) + ); + AOI22_X1_LVT i_1_0_754( + .A1(registers_20__ap[3]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[3]), + .ZN(n_1_0_718) + ); + SDFF_X1_LVT \registers_reg[22][3] ( + .CK(n_0_52), .D(registers[3]), .Q(registers_22__ap[3]), .QN(), .SE(dftIn), + .SI(registers_20__ap[3]) + ); + SDFF_X1_LVT \registers_reg[21][3] ( + .CK(n_0_51), .D(registers[3]), .Q(registers_21__ap[3]), .QN(), .SE(dftIn), + .SI(registers_22__ap[3]) + ); + AOI22_X1_LVT i_1_0_753( + .A1(registers_22__ap[3]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[3]), + .ZN(n_1_0_717) + ); + SDFF_X1_LVT \registers_reg[24][3] ( + .CK(n_0_54), .D(registers[3]), .Q(registers_24__ap[3]), .QN(), .SE(dftIn), + .SI(registers_30__ap[3]) + ); + SDFF_X1_LVT \registers_reg[12][3] ( + .CK(n_0_42), .D(registers[3]), .Q(registers_12__ap[3]), .QN(), .SE(dftIn), + .SI(registers_15__ap[3]) + ); + AOI22_X1_LVT i_1_0_752( + .A1(registers_24__ap[3]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[3]), + .ZN(n_1_0_716) + ); + NAND4_X1_LVT i_1_0_751( + .A1(n_1_0_719), .A2(n_1_0_718), .A3(n_1_0_717), .A4(n_1_0_716), .ZN(n_1_0_715) + ); + SDFF_X1_LVT \registers_reg[13][3] ( + .CK(n_0_43), .D(registers[3]), .Q(registers_13__ap[3]), .QN(), .SE(dftIn), + .SI(registers_12__ap[3]) + ); + SDFF_X1_LVT \registers_reg[25][3] ( + .CK(n_0_55), .D(registers[3]), .Q(registers_25__ap[3]), .QN(), .SE(dftIn), + .SI(registers_24__ap[3]) + ); + AOI22_X1_LVT i_1_0_750( + .A1(registers_13__ap[3]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[3]), + .ZN(n_1_0_714) + ); + SDFF_X1_LVT \registers_reg[19][3] ( + .CK(n_0_49), .D(registers[3]), .Q(registers_19__ap[3]), .QN(), .SE(dftIn), + .SI(registers_21__ap[3]) + ); + SDFF_X1_LVT \registers_reg[2][3] ( + .CK(n_0_32), .D(registers[3]), .Q(registers_2__ap[3]), .QN(), .SE(dftIn), + .SI(registers_25__ap[3]) + ); + AOI22_X1_LVT i_1_0_749( + .A1(registers_19__ap[3]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[3]), + .ZN(n_1_0_713) + ); + SDFF_X1_LVT \registers_reg[7][3] ( + .CK(n_0_37), .D(registers[3]), .Q(registers_7__ap[3]), .QN(), .SE(dftIn), + .SI(registers_4__ap[3]) + ); + SDFF_X1_LVT \registers_reg[14][3] ( + .CK(n_0_44), .D(registers[3]), .Q(registers_14__ap[3]), .QN(), .SE(dftIn), + .SI(registers_13__ap[3]) + ); + AOI22_X1_LVT i_1_0_748( + .A1(registers_7__ap[3]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[3]), + .ZN(n_1_0_712) + ); + SDFF_X1_LVT \registers_reg[27][3] ( + .CK(n_0_57), .D(registers[3]), .Q(registers_27__ap[3]), .QN(), .SE(dftIn), + .SI(registers_2__ap[3]) + ); + SDFF_X1_LVT \registers_reg[11][3] ( + .CK(n_0_41), .D(registers[3]), .Q(registers_11__ap[3]), .QN(), .SE(dftIn), + .SI(registers_14__ap[3]) + ); + AOI22_X1_LVT i_1_0_747( + .A1(registers_27__ap[3]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[3]), + .ZN(n_1_0_711) + ); + NAND4_X1_LVT i_1_0_746( + .A1(n_1_0_714), .A2(n_1_0_713), .A3(n_1_0_712), .A4(n_1_0_711), .ZN(n_1_0_710) + ); + NOR3_X1_LVT i_1_0_745( + .A1(n_1_0_720), .A2(n_1_0_715), .A3(n_1_0_710), .ZN(n_1_0_709) + ); + NAND4_X1_LVT i_1_0_744( + .A1(n_1_0_727), .A2(n_1_0_726), .A3(n_1_0_725), .A4(n_1_0_709), .ZN(RRs1[3]) + ); + AND2_X1_LVT i_0_0_2( + .A1(n_0_0_16), .A2(WRd[2]), .ZN(registers[2]) + ); + SDFF_X1_LVT \registers_reg[28][2] ( + .CK(n_0_58), .D(registers[2]), .Q(registers_28__ap[2]), .QN(), .SE(dftIn), + .SI(registers_27__ap[3]) + ); + SDFF_X1_LVT \registers_reg[4][2] ( + .CK(n_0_34), .D(registers[2]), .Q(registers_4__ap[2]), .QN(), .SE(dftIn), + .SI(registers_7__ap[3]) + ); + AOI22_X1_LVT i_1_0_740( + .A1(registers_28__ap[2]), .A2(n_1_0_1283), .B1(n_1_0_1278), .B2(registers_4__ap[2]), + .ZN(n_1_0_705) + ); + SDFF_X1_LVT \registers_reg[16][2] ( + .CK(n_0_46), .D(registers[2]), .Q(registers_16__ap[2]), .QN(), .SE(dftIn), + .SI(registers_11__ap[3]) + ); + SDFF_X1_LVT \registers_reg[31][2] ( + .CK(n_0_61), .D(registers[2]), .Q(registers_31__ap[2]), .QN(), .SE(dftIn), + .SI(registers_4__ap[2]) + ); + AOI22_X1_LVT i_1_0_743( + .A1(registers_16__ap[2]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[2]), + .ZN(n_1_0_708) + ); + SDFF_X1_LVT \registers_reg[6][2] ( + .CK(n_0_36), .D(registers[2]), .Q(registers_6__ap[2]), .QN(), .SE(dftIn), + .SI(registers_31__ap[2]) + ); + SDFF_X1_LVT \registers_reg[1][2] ( + .CK(n_0_0), .D(registers[2]), .Q(registers_1__ap[2]), .QN(), .SE(dftIn), + .SI(registers_19__ap[3]) + ); + AOI22_X1_LVT i_1_0_739( + .A1(registers_6__ap[2]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[2]), + .ZN(n_1_0_704) + ); + SDFF_X1_LVT \registers_reg[15][2] ( + .CK(n_0_45), .D(registers[2]), .Q(registers_15__ap[2]), .QN(), .SE(dftIn), + .SI(registers_16__ap[2]) + ); + SDFF_X1_LVT \registers_reg[27][2] ( + .CK(n_0_57), .D(registers[2]), .Q(registers_27__ap[2]), .QN(), .SE(dftIn), + .SI(registers_28__ap[2]) + ); + AOI22_X1_LVT i_1_0_742( + .A1(registers_15__ap[2]), .A2(n_1_0_1286), .B1(n_1_0_1279), .B2(registers_27__ap[2]), + .ZN(n_1_0_707) + ); + INV_X1_LVT i_1_0_741( + .A(n_1_0_707), .ZN(n_1_0_706) + ); + SDFF_X1_LVT \registers_reg[11][2] ( + .CK(n_0_41), .D(registers[2]), .Q(registers_11__ap[2]), .QN(), .SE(dftIn), + .SI(registers_15__ap[2]) + ); + SDFF_X1_LVT \registers_reg[5][2] ( + .CK(n_0_35), .D(registers[2]), .Q(registers_5__ap[2]), .QN(), .SE(dftIn), + .SI(registers_6__ap[2]) + ); + AOI221_X1_LVT i_1_0_738( + .A(n_1_0_706), .B1(n_1_0_1270), .B2(registers_11__ap[2]), .C1(registers_5__ap[2]), + .C2(n_1_0_1273), .ZN(n_1_0_703) + ); + SDFF_X1_LVT \registers_reg[10][2] ( + .CK(n_0_40), .D(registers[2]), .Q(registers_10__ap[2]), .QN(), .SE(dftIn), + .SI(registers_11__ap[2]) + ); + SDFF_X1_LVT \registers_reg[30][2] ( + .CK(n_0_60), .D(registers[2]), .Q(registers_30__ap[2]), .QN(), .SE(dftIn), + .SI(registers_27__ap[2]) + ); + SDFF_X1_LVT \registers_reg[8][2] ( + .CK(n_0_38), .D(registers[2]), .Q(registers_8__ap[2]), .QN(), .SE(dftIn), + .SI(registers_5__ap[2]) + ); + AOI222_X1_LVT i_1_0_737( + .A1(registers_10__ap[2]), .A2(n_1_0_1287), .B1(n_1_0_1272), .B2(registers_30__ap[2]), + .C1(n_1_0_1282), .C2(registers_8__ap[2]), .ZN(n_1_0_702) + ); + NAND4_X1_LVT i_1_0_736( + .A1(n_1_0_708), .A2(n_1_0_704), .A3(n_1_0_703), .A4(n_1_0_702), .ZN(n_1_0_701) + ); + SDFF_X1_LVT \registers_reg[9][2] ( + .CK(n_0_39), .D(registers[2]), .Q(registers_9__ap[2]), .QN(), .SE(dftIn), + .SI(registers_8__ap[2]) + ); + SDFF_X1_LVT \registers_reg[29][2] ( + .CK(n_0_59), .D(registers[2]), .Q(registers_29__ap[2]), .QN(), .SE(dftIn), + .SI(registers_30__ap[2]) + ); + AOI221_X1_LVT i_1_0_735( + .A(n_1_0_701), .B1(n_1_0_1291), .B2(registers_9__ap[2]), .C1(registers_29__ap[2]), + .C2(n_1_0_1276), .ZN(n_1_0_700) + ); + SDFF_X1_LVT \registers_reg[18][2] ( + .CK(n_0_48), .D(registers[2]), .Q(registers_18__ap[2]), .QN(), .SE(dftIn), + .SI(registers_1__ap[2]) + ); + SDFF_X1_LVT \registers_reg[26][2] ( + .CK(n_0_56), .D(registers[2]), .Q(registers_26__ap[2]), .QN(), .SE(dftIn), + .SI(registers_29__ap[2]) + ); + AOI22_X1_LVT i_1_0_734( + .A1(registers_18__ap[2]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[2]), + .ZN(n_1_0_699) + ); + SDFF_X1_LVT \registers_reg[24][2] ( + .CK(n_0_54), .D(registers[2]), .Q(registers_24__ap[2]), .QN(), .SE(dftIn), + .SI(registers_26__ap[2]) + ); + SDFF_X1_LVT \registers_reg[12][2] ( + .CK(n_0_42), .D(registers[2]), .Q(registers_12__ap[2]), .QN(), .SE(dftIn), + .SI(registers_10__ap[2]) + ); + AOI22_X1_LVT i_1_0_733( + .A1(registers_24__ap[2]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[2]), + .ZN(n_1_0_698) + ); + SDFF_X1_LVT \registers_reg[22][2] ( + .CK(n_0_52), .D(registers[2]), .Q(registers_22__ap[2]), .QN(), .SE(dftIn), + .SI(registers_18__ap[2]) + ); + SDFF_X1_LVT \registers_reg[21][2] ( + .CK(n_0_51), .D(registers[2]), .Q(registers_21__ap[2]), .QN(), .SE(dftIn), + .SI(registers_22__ap[2]) + ); + AOI22_X1_LVT i_1_0_732( + .A1(registers_22__ap[2]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[2]), + .ZN(n_1_0_697) + ); + NAND3_X1_LVT i_1_0_731( + .A1(n_1_0_699), .A2(n_1_0_698), .A3(n_1_0_697), .ZN(n_1_0_696) + ); + SDFF_X1_LVT \registers_reg[17][2] ( + .CK(n_0_47), .D(registers[2]), .Q(registers_17__ap[2]), .QN(), .SE(dftIn), + .SI(registers_21__ap[2]) + ); + SDFF_X1_LVT \registers_reg[20][2] ( + .CK(n_0_50), .D(registers[2]), .Q(registers_20__ap[2]), .QN(), .SE(dftIn), + .SI(registers_17__ap[2]) + ); + AOI221_X1_LVT i_1_0_730( + .A(n_1_0_696), .B1(n_1_0_1271), .B2(registers_17__ap[2]), .C1(registers_20__ap[2]), + .C2(n_1_0_1281), .ZN(n_1_0_695) + ); + SDFF_X1_LVT \registers_reg[13][2] ( + .CK(n_0_43), .D(registers[2]), .Q(registers_13__ap[2]), .QN(), .SE(dftIn), + .SI(registers_12__ap[2]) + ); + SDFF_X1_LVT \registers_reg[25][2] ( + .CK(n_0_55), .D(registers[2]), .Q(registers_25__ap[2]), .QN(), .SE(dftIn), + .SI(registers_24__ap[2]) + ); + AOI22_X1_LVT i_1_0_729( + .A1(registers_13__ap[2]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[2]), + .ZN(n_1_0_694) + ); + SDFF_X1_LVT \registers_reg[7][2] ( + .CK(n_0_37), .D(registers[2]), .Q(registers_7__ap[2]), .QN(), .SE(dftIn), + .SI(registers_9__ap[2]) + ); + SDFF_X1_LVT \registers_reg[14][2] ( + .CK(n_0_44), .D(registers[2]), .Q(registers_14__ap[2]), .QN(), .SE(dftIn), + .SI(registers_13__ap[2]) + ); + AOI22_X1_LVT i_1_0_728( + .A1(registers_7__ap[2]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[2]), + .ZN(n_1_0_693) + ); + SDFF_X1_LVT \registers_reg[19][2] ( + .CK(n_0_49), .D(registers[2]), .Q(registers_19__ap[2]), .QN(), .SE(dftIn), + .SI(registers_20__ap[2]) + ); + SDFF_X1_LVT \registers_reg[3][2] ( + .CK(n_0_33), .D(registers[2]), .Q(registers_3__ap[2]), .QN(), .SE(dftIn), + .SI(registers_7__ap[2]) + ); + AOI22_X1_LVT i_1_0_727( + .A1(registers_19__ap[2]), .A2(n_1_0_1295), .B1(n_1_0_1257), .B2(registers_3__ap[2]), + .ZN(n_1_0_692) + ); + NAND3_X1_LVT i_1_0_726( + .A1(n_1_0_694), .A2(n_1_0_693), .A3(n_1_0_692), .ZN(n_1_0_691) + ); + SDFF_X1_LVT \registers_reg[23][2] ( + .CK(n_0_53), .D(registers[2]), .Q(registers_23__ap[2]), .QN(), .SE(dftIn), + .SI(registers_19__ap[2]) + ); + SDFF_X1_LVT \registers_reg[2][2] ( + .CK(n_0_32), .D(registers[2]), .Q(registers_2__ap[2]), .QN(), .SE(dftIn), + .SI(registers_25__ap[2]) + ); + AOI221_X1_LVT i_1_0_725( + .A(n_1_0_691), .B1(n_1_0_1264), .B2(registers_23__ap[2]), .C1(registers_2__ap[2]), + .C2(n_1_0_1268), .ZN(n_1_0_690) + ); + NAND4_X1_LVT i_1_0_724( + .A1(n_1_0_705), .A2(n_1_0_700), .A3(n_1_0_695), .A4(n_1_0_690), .ZN(RRs1[2]) + ); + AND2_X1_LVT i_0_0_1( + .A1(n_0_0_16), .A2(WRd[1]), .ZN(registers[1]) + ); + SDFF_X1_LVT \registers_reg[13][1] ( + .CK(n_0_43), .D(registers[1]), .Q(registers_13__ap[1]), .QN(), .SE(dftIn), + .SI(registers_14__ap[2]) + ); + SDFF_X1_LVT \registers_reg[21][1] ( + .CK(n_0_51), .D(registers[1]), .Q(registers_21__ap[1]), .QN(), .SE(dftIn), + .SI(registers_23__ap[2]) + ); + AOI22_X1_LVT i_1_0_720( + .A1(registers_13__ap[1]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[1]), + .ZN(n_1_0_686) + ); + SDFF_X1_LVT \registers_reg[29][1] ( + .CK(n_0_59), .D(registers[1]), .Q(registers_29__ap[1]), .QN(), .SE(dftIn), + .SI(registers_2__ap[2]) + ); + SDFF_X1_LVT \registers_reg[23][1] ( + .CK(n_0_53), .D(registers[1]), .Q(registers_23__ap[1]), .QN(), .SE(dftIn), + .SI(registers_21__ap[1]) + ); + AOI22_X1_LVT i_1_0_723( + .A1(registers_29__ap[1]), .A2(n_1_0_1276), .B1(n_1_0_1264), .B2(registers_23__ap[1]), + .ZN(n_1_0_689) + ); + SDFF_X1_LVT \registers_reg[24][1] ( + .CK(n_0_54), .D(registers[1]), .Q(registers_24__ap[1]), .QN(), .SE(dftIn), + .SI(registers_29__ap[1]) + ); + SDFF_X1_LVT \registers_reg[20][1] ( + .CK(n_0_50), .D(registers[1]), .Q(registers_20__ap[1]), .QN(), .SE(dftIn), + .SI(registers_23__ap[1]) + ); + AOI22_X1_LVT i_1_0_719( + .A1(registers_24__ap[1]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[1]), + .ZN(n_1_0_685) + ); + SDFF_X1_LVT \registers_reg[7][1] ( + .CK(n_0_37), .D(registers[1]), .Q(registers_7__ap[1]), .QN(), .SE(dftIn), + .SI(registers_3__ap[2]) + ); + SDFF_X1_LVT \registers_reg[3][1] ( + .CK(n_0_33), .D(registers[1]), .Q(registers_3__ap[1]), .QN(), .SE(dftIn), + .SI(registers_7__ap[1]) + ); + AOI22_X1_LVT i_1_0_722( + .A1(registers_7__ap[1]), .A2(n_1_0_1263), .B1(n_1_0_1257), .B2(registers_3__ap[1]), + .ZN(n_1_0_688) + ); + INV_X1_LVT i_1_0_721( + .A(n_1_0_688), .ZN(n_1_0_687) + ); + SDFF_X1_LVT \registers_reg[31][1] ( + .CK(n_0_61), .D(registers[1]), .Q(registers_31__ap[1]), .QN(), .SE(dftIn), + .SI(registers_3__ap[1]) + ); + SDFF_X1_LVT \registers_reg[4][1] ( + .CK(n_0_34), .D(registers[1]), .Q(registers_4__ap[1]), .QN(), .SE(dftIn), + .SI(registers_31__ap[1]) + ); + AOI221_X1_LVT i_1_0_718( + .A(n_1_0_687), .B1(n_1_0_1266), .B2(registers_31__ap[1]), .C1(registers_4__ap[1]), + .C2(n_1_0_1278), .ZN(n_1_0_684) + ); + SDFF_X1_LVT \registers_reg[10][1] ( + .CK(n_0_40), .D(registers[1]), .Q(registers_10__ap[1]), .QN(), .SE(dftIn), + .SI(registers_13__ap[1]) + ); + SDFF_X1_LVT \registers_reg[26][1] ( + .CK(n_0_56), .D(registers[1]), .Q(registers_26__ap[1]), .QN(), .SE(dftIn), + .SI(registers_24__ap[1]) + ); + SDFF_X1_LVT \registers_reg[25][1] ( + .CK(n_0_55), .D(registers[1]), .Q(registers_25__ap[1]), .QN(), .SE(dftIn), + .SI(registers_26__ap[1]) + ); + AOI222_X1_LVT i_1_0_717( + .A1(registers_10__ap[1]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[1]), + .C1(registers_25__ap[1]), .C2(n_1_0_1269), .ZN(n_1_0_683) + ); + NAND4_X1_LVT i_1_0_716( + .A1(n_1_0_689), .A2(n_1_0_685), .A3(n_1_0_684), .A4(n_1_0_683), .ZN(n_1_0_682) + ); + SDFF_X1_LVT \registers_reg[8][1] ( + .CK(n_0_38), .D(registers[1]), .Q(registers_8__ap[1]), .QN(), .SE(dftIn), + .SI(registers_4__ap[1]) + ); + SDFF_X1_LVT \registers_reg[28][1] ( + .CK(n_0_58), .D(registers[1]), .Q(registers_28__ap[1]), .QN(), .SE(dftIn), + .SI(registers_25__ap[1]) + ); + AOI221_X1_LVT i_1_0_715( + .A(n_1_0_682), .B1(n_1_0_1282), .B2(registers_8__ap[1]), .C1(registers_28__ap[1]), + .C2(n_1_0_1283), .ZN(n_1_0_681) + ); + SDFF_X1_LVT \registers_reg[18][1] ( + .CK(n_0_48), .D(registers[1]), .Q(registers_18__ap[1]), .QN(), .SE(dftIn), + .SI(registers_20__ap[1]) + ); + SDFF_X1_LVT \registers_reg[30][1] ( + .CK(n_0_60), .D(registers[1]), .Q(registers_30__ap[1]), .QN(), .SE(dftIn), + .SI(registers_28__ap[1]) + ); + AOI22_X1_LVT i_1_0_714( + .A1(registers_18__ap[1]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[1]), + .ZN(n_1_0_680) + ); + SDFF_X1_LVT \registers_reg[17][1] ( + .CK(n_0_47), .D(registers[1]), .Q(registers_17__ap[1]), .QN(), .SE(dftIn), + .SI(registers_18__ap[1]) + ); + SDFF_X1_LVT \registers_reg[12][1] ( + .CK(n_0_42), .D(registers[1]), .Q(registers_12__ap[1]), .QN(), .SE(dftIn), + .SI(registers_10__ap[1]) + ); + AOI22_X1_LVT i_1_0_713( + .A1(registers_17__ap[1]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[1]), + .ZN(n_1_0_679) + ); + SDFF_X1_LVT \registers_reg[15][1] ( + .CK(n_0_45), .D(registers[1]), .Q(registers_15__ap[1]), .QN(), .SE(dftIn), + .SI(registers_12__ap[1]) + ); + SDFF_X1_LVT \registers_reg[5][1] ( + .CK(n_0_35), .D(registers[1]), .Q(registers_5__ap[1]), .QN(), .SE(dftIn), + .SI(registers_8__ap[1]) + ); + AOI22_X1_LVT i_1_0_712( + .A1(registers_15__ap[1]), .A2(n_1_0_1286), .B1(n_1_0_1273), .B2(registers_5__ap[1]), + .ZN(n_1_0_678) + ); + NAND3_X1_LVT i_1_0_711( + .A1(n_1_0_680), .A2(n_1_0_679), .A3(n_1_0_678), .ZN(n_1_0_677) + ); + SDFF_X1_LVT \registers_reg[22][1] ( + .CK(n_0_52), .D(registers[1]), .Q(registers_22__ap[1]), .QN(), .SE(dftIn), + .SI(registers_17__ap[1]) + ); + SDFF_X1_LVT \registers_reg[16][1] ( + .CK(n_0_46), .D(registers[1]), .Q(registers_16__ap[1]), .QN(), .SE(dftIn), + .SI(registers_15__ap[1]) + ); + AOI221_X1_LVT i_1_0_710( + .A(n_1_0_677), .B1(n_1_0_1294), .B2(registers_22__ap[1]), .C1(registers_16__ap[1]), + .C2(n_1_0_1267), .ZN(n_1_0_676) + ); + SDFF_X1_LVT \registers_reg[9][1] ( + .CK(n_0_39), .D(registers[1]), .Q(registers_9__ap[1]), .QN(), .SE(dftIn), + .SI(registers_5__ap[1]) + ); + SDFF_X1_LVT \registers_reg[1][1] ( + .CK(n_0_0), .D(registers[1]), .Q(registers_1__ap[1]), .QN(), .SE(dftIn), + .SI(registers_22__ap[1]) + ); + AOI22_X1_LVT i_1_0_709( + .A1(registers_9__ap[1]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[1]), + .ZN(n_1_0_675) + ); + SDFF_X1_LVT \registers_reg[6][1] ( + .CK(n_0_36), .D(registers[1]), .Q(registers_6__ap[1]), .QN(), .SE(dftIn), + .SI(registers_9__ap[1]) + ); + SDFF_X1_LVT \registers_reg[14][1] ( + .CK(n_0_44), .D(registers[1]), .Q(registers_14__ap[1]), .QN(), .SE(dftIn), + .SI(registers_16__ap[1]) + ); + AOI22_X1_LVT i_1_0_708( + .A1(registers_6__ap[1]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[1]), + .ZN(n_1_0_674) + ); + SDFF_X1_LVT \registers_reg[19][1] ( + .CK(n_0_49), .D(registers[1]), .Q(registers_19__ap[1]), .QN(), .SE(dftIn), + .SI(registers_1__ap[1]) + ); + SDFF_X1_LVT \registers_reg[2][1] ( + .CK(n_0_32), .D(registers[1]), .Q(registers_2__ap[1]), .QN(), .SE(dftIn), + .SI(registers_30__ap[1]) + ); + AOI22_X1_LVT i_1_0_707( + .A1(registers_19__ap[1]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[1]), + .ZN(n_1_0_673) + ); + NAND3_X1_LVT i_1_0_706( + .A1(n_1_0_675), .A2(n_1_0_674), .A3(n_1_0_673), .ZN(n_1_0_672) + ); + SDFF_X1_LVT \registers_reg[11][1] ( + .CK(n_0_41), .D(registers[1]), .Q(registers_11__ap[1]), .QN(), .SE(dftIn), + .SI(registers_14__ap[1]) + ); + SDFF_X1_LVT \registers_reg[27][1] ( + .CK(n_0_57), .D(registers[1]), .Q(registers_27__ap[1]), .QN(), .SE(dftIn), + .SI(registers_2__ap[1]) + ); + AOI221_X1_LVT i_1_0_705( + .A(n_1_0_672), .B1(n_1_0_1270), .B2(registers_11__ap[1]), .C1(registers_27__ap[1]), + .C2(n_1_0_1279), .ZN(n_1_0_671) + ); + NAND4_X1_LVT i_1_0_704( + .A1(n_1_0_686), .A2(n_1_0_681), .A3(n_1_0_676), .A4(n_1_0_671), .ZN(RRs1[1]) + ); + AND2_X1_LVT i_0_0_0( + .A1(n_0_0_16), .A2(WRd[0]), .ZN(registers[0]) + ); + SDFF_X1_LVT \registers_reg[13][0] ( + .CK(n_0_43), .D(registers[0]), .Q(registers_13__ap[0]), .QN(), .SE(dftIn), + .SI(registers_11__ap[1]) + ); + SDFF_X1_LVT \registers_reg[21][0] ( + .CK(n_0_51), .D(registers[0]), .Q(registers_21__ap[0]), .QN(), .SE(dftIn), + .SI(registers_19__ap[1]) + ); + AOI22_X1_LVT i_1_0_703( + .A1(registers_13__ap[0]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[0]), + .ZN(n_1_0_670) + ); + SDFF_X1_LVT \registers_reg[10][0] ( + .CK(n_0_40), .D(registers[0]), .Q(registers_10__ap[0]), .QN(), .SE(dftIn), + .SI(registers_13__ap[0]) + ); + SDFF_X1_LVT \registers_reg[26][0] ( + .CK(n_0_56), .D(registers[0]), .Q(registers_26__ap[0]), .QN(), .SE(dftIn), + .SI(registers_27__ap[1]) + ); + SDFF_X1_LVT \registers_reg[25][0] ( + .CK(n_0_55), .D(registers[0]), .Q(registers_25__ap[0]), .QN(), .SE(dftIn), + .SI(registers_26__ap[0]) + ); + AOI222_X1_LVT i_1_0_702( + .A1(registers_10__ap[0]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[0]), + .C1(registers_25__ap[0]), .C2(n_1_0_1269), .ZN(n_1_0_669) + ); + SDFF_X1_LVT \registers_reg[28][0] ( + .CK(n_0_58), .D(registers[0]), .Q(registers_28__ap[0]), .QN(), .SE(dftIn), + .SI(registers_25__ap[0]) + ); + SDFF_X1_LVT \registers_reg[8][0] ( + .CK(n_0_38), .D(registers[0]), .Q(registers_8__ap[0]), .QN(), .SE(dftIn), + .SI(registers_6__ap[1]) + ); + AOI22_X1_LVT i_1_0_701( + .A1(registers_28__ap[0]), .A2(n_1_0_1283), .B1(n_1_0_1282), .B2(registers_8__ap[0]), + .ZN(n_1_0_668) + ); + SDFF_X1_LVT \registers_reg[24][0] ( + .CK(n_0_54), .D(registers[0]), .Q(registers_24__ap[0]), .QN(), .SE(dftIn), + .SI(registers_28__ap[0]) + ); + SDFF_X1_LVT \registers_reg[20][0] ( + .CK(n_0_50), .D(registers[0]), .Q(registers_20__ap[0]), .QN(), .SE(dftIn), + .SI(registers_21__ap[0]) + ); + AOI22_X1_LVT i_1_0_700( + .A1(registers_24__ap[0]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[0]), + .ZN(n_1_0_667) + ); + SDFF_X1_LVT \registers_reg[7][0] ( + .CK(n_0_37), .D(registers[0]), .Q(registers_7__ap[0]), .QN(), .SE(dftIn), + .SI(registers_8__ap[0]) + ); + SDFF_X1_LVT \registers_reg[3][0] ( + .CK(n_0_33), .D(registers[0]), .Q(registers_3__ap[0]), .QN(), .SE(dftIn), + .SI(registers_7__ap[0]) + ); + AOI22_X1_LVT i_1_0_699( + .A1(registers_7__ap[0]), .A2(n_1_0_1263), .B1(n_1_0_1257), .B2(registers_3__ap[0]), + .ZN(n_1_0_666) + ); + SDFF_X1_LVT \registers_reg[17][0] ( + .CK(n_0_47), .D(registers[0]), .Q(registers_17__ap[0]), .QN(), .SE(dftIn), + .SI(registers_20__ap[0]) + ); + SDFF_X1_LVT \registers_reg[31][0] ( + .CK(n_0_61), .D(registers[0]), .Q(registers_31__ap[0]), .QN(), .SE(dftIn), + .SI(registers_3__ap[0]) + ); + AOI22_X1_LVT i_1_0_698( + .A1(registers_17__ap[0]), .A2(n_1_0_1271), .B1(n_1_0_1266), .B2(registers_31__ap[0]), + .ZN(n_1_0_665) + ); + SDFF_X1_LVT \registers_reg[29][0] ( + .CK(n_0_59), .D(registers[0]), .Q(registers_29__ap[0]), .QN(), .SE(dftIn), + .SI(registers_24__ap[0]) + ); + SDFF_X1_LVT \registers_reg[23][0] ( + .CK(n_0_53), .D(registers[0]), .Q(registers_23__ap[0]), .QN(), .SE(dftIn), + .SI(registers_17__ap[0]) + ); + AOI22_X1_LVT i_1_0_697( + .A1(registers_29__ap[0]), .A2(n_1_0_1276), .B1(n_1_0_1264), .B2(registers_23__ap[0]), + .ZN(n_1_0_664) + ); + NAND4_X1_LVT i_1_0_696( + .A1(n_1_0_667), .A2(n_1_0_666), .A3(n_1_0_665), .A4(n_1_0_664), .ZN(n_1_0_663) + ); + SDFF_X1_LVT \registers_reg[18][0] ( + .CK(n_0_48), .D(registers[0]), .Q(registers_18__ap[0]), .QN(), .SE(dftIn), + .SI(registers_23__ap[0]) + ); + SDFF_X1_LVT \registers_reg[30][0] ( + .CK(n_0_60), .D(registers[0]), .Q(registers_30__ap[0]), .QN(), .SE(dftIn), + .SI(registers_29__ap[0]) + ); + AOI22_X1_LVT i_1_0_695( + .A1(registers_18__ap[0]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[0]), + .ZN(n_1_0_662) + ); + SDFF_X1_LVT \registers_reg[4][0] ( + .CK(n_0_34), .D(registers[0]), .Q(registers_4__ap[0]), .QN(), .SE(dftIn), + .SI(registers_31__ap[0]) + ); + SDFF_X1_LVT \registers_reg[12][0] ( + .CK(n_0_42), .D(registers[0]), .Q(registers_12__ap[0]), .QN(), .SE(dftIn), + .SI(registers_10__ap[0]) + ); + AOI22_X1_LVT i_1_0_694( + .A1(registers_4__ap[0]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[0]), + .ZN(n_1_0_661) + ); + SDFF_X1_LVT \registers_reg[15][0] ( + .CK(n_0_45), .D(registers[0]), .Q(registers_15__ap[0]), .QN(), .SE(dftIn), + .SI(registers_12__ap[0]) + ); + SDFF_X1_LVT \registers_reg[16][0] ( + .CK(n_0_46), .D(registers[0]), .Q(registers_16__ap[0]), .QN(), .SE(dftIn), + .SI(registers_15__ap[0]) + ); + AOI22_X1_LVT i_1_0_693( + .A1(registers_15__ap[0]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[0]), + .ZN(n_1_0_660) + ); + SDFF_X1_LVT \registers_reg[22][0] ( + .CK(n_0_52), .D(registers[0]), .Q(registers_22__ap[0]), .QN(), .SE(dftIn), + .SI(registers_18__ap[0]) + ); + SDFF_X1_LVT \registers_reg[5][0] ( + .CK(n_0_35), .D(registers[0]), .Q(registers_5__ap[0]), .QN(), .SE(dftIn), + .SI(registers_4__ap[0]) + ); + AOI22_X1_LVT i_1_0_692( + .A1(registers_22__ap[0]), .A2(n_1_0_1294), .B1(n_1_0_1273), .B2(registers_5__ap[0]), + .ZN(n_1_0_659) + ); + NAND4_X1_LVT i_1_0_691( + .A1(n_1_0_662), .A2(n_1_0_661), .A3(n_1_0_660), .A4(n_1_0_659), .ZN(n_1_0_658) + ); + SDFF_X1_LVT \registers_reg[19][0] ( + .CK(n_0_49), .D(registers[0]), .Q(registers_19__ap[0]), .QN(), .SE(dftIn), + .SI(registers_22__ap[0]) + ); + SDFF_X1_LVT \registers_reg[2][0] ( + .CK(n_0_32), .D(registers[0]), .Q(registers_2__ap[0]), .QN(), .SE(dftIn), + .SI(registers_30__ap[0]) + ); + AOI22_X1_LVT i_1_0_690( + .A1(registers_19__ap[0]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[0]), + .ZN(n_1_0_657) + ); + SDFF_X1_LVT \registers_reg[9][0] ( + .CK(n_0_39), .D(registers[0]), .Q(registers_9__ap[0]), .QN(), .SE(dftIn), + .SI(registers_5__ap[0]) + ); + SDFF_X1_LVT \registers_reg[1][0] ( + .CK(n_0_0), .D(registers[0]), .Q(registers_1__ap[0]), .QN(), .SE(dftIn), + .SI(registers_19__ap[0]) + ); + AOI22_X1_LVT i_1_0_689( + .A1(registers_9__ap[0]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[0]), + .ZN(n_1_0_656) + ); + SDFF_X1_LVT \registers_reg[6][0] ( + .CK(n_0_36), .D(registers[0]), .Q(registers_6__ap[0]), .QN(), .SE(dftIn), + .SI(registers_9__ap[0]) + ); + SDFF_X1_LVT \registers_reg[14][0] ( + .CK(n_0_44), .D(registers[0]), .Q(registers_14__ap[0]), .QN(), .SE(dftIn), + .SI(registers_16__ap[0]) + ); + AOI22_X1_LVT i_1_0_688( + .A1(registers_6__ap[0]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[0]), + .ZN(n_1_0_655) + ); + SDFF_X1_LVT \registers_reg[27][0] ( + .CK(n_0_57), .D(registers[0]), .Q(registers_27__ap[0]), .QN(), .SE(dftIn), + .SI(registers_2__ap[0]) + ); + SDFF_X1_LVT \registers_reg[11][0] ( + .CK(n_0_41), .D(registers[0]), .Q(registers_11__ap[0]), .QN(), .SE(dftIn), + .SI(registers_14__ap[0]) + ); + AOI22_X1_LVT i_1_0_687( + .A1(registers_27__ap[0]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[0]), + .ZN(n_1_0_654) + ); + NAND4_X1_LVT i_1_0_686( + .A1(n_1_0_657), .A2(n_1_0_656), .A3(n_1_0_655), .A4(n_1_0_654), .ZN(n_1_0_653) + ); + NOR3_X1_LVT i_1_0_685( + .A1(n_1_0_663), .A2(n_1_0_658), .A3(n_1_0_653), .ZN(n_1_0_652) + ); + NAND4_X1_LVT i_1_0_684( + .A1(n_1_0_670), .A2(n_1_0_669), .A3(n_1_0_668), .A4(n_1_0_652), .ZN(RRs1[0]) + ); + INV_X1_LVT i_1_0_1366( + .A(Rs2[1]), .ZN(n_1_0_1302) + ); + NAND3_X1_LVT i_1_0_683( + .A1(n_1_0_1302), .A2(Rs2[4]), .A3(Rs2[2]), .ZN(n_1_0_651) + ); + INV_X1_LVT i_1_0_1369( + .A(Rs2[3]), .ZN(n_1_0_1305) + ); + OR2_X1_LVT i_1_0_673( + .A1(n_1_0_1305), .A2(Rs2[0]), .ZN(n_1_0_641) + ); + NOR2_X1_LVT i_1_0_666( + .A1(n_1_0_651), .A2(n_1_0_641), .ZN(n_1_0_634) + ); + NAND2_X1_LVT i_1_0_677( + .A1(n_1_0_1305), .A2(Rs2[0]), .ZN(n_1_0_645) + ); + INV_X1_LVT i_1_0_1368( + .A(Rs2[2]), .ZN(n_1_0_1304) + ); + NAND3_X1_LVT i_1_0_662( + .A1(n_1_0_1304), .A2(n_1_0_1302), .A3(Rs2[4]), .ZN(n_1_0_630) + ); + NOR2_X1_LVT i_1_0_661( + .A1(n_1_0_645), .A2(n_1_0_630), .ZN(n_1_0_629) + ); + AOI22_X1_LVT i_1_0_641( + .A1(registers_28__ap[31]), .A2(n_1_0_634), .B1(n_1_0_629), .B2(registers_17__ap[31]), + .ZN(n_1_0_609) + ); + NAND3_X1_LVT i_1_0_680( + .A1(n_1_0_1304), .A2(Rs2[4]), .A3(Rs2[1]), .ZN(n_1_0_648) + ); + NOR2_X1_LVT i_1_0_672( + .A1(n_1_0_648), .A2(n_1_0_641), .ZN(n_1_0_640) + ); + INV_X1_LVT i_1_0_1367( + .A(Rs2[4]), .ZN(n_1_0_1303) + ); + NAND3_X1_LVT i_1_0_657( + .A1(n_1_0_1304), .A2(n_1_0_1303), .A3(Rs2[1]), .ZN(n_1_0_625) + ); + NOR2_X1_LVT i_1_0_656( + .A1(n_1_0_641), .A2(n_1_0_625), .ZN(n_1_0_624) + ); + NOR4_X1_LVT i_1_0_658( + .A1(n_1_0_641), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), .ZN(n_1_0_626) + ); + AOI222_X1_LVT i_1_0_640( + .A1(registers_26__ap[31]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[31]), + .C1(n_1_0_626), .C2(registers_8__ap[31]), .ZN(n_1_0_608) + ); + NAND2_X1_LVT i_1_0_682( + .A1(Rs2[0]), .A2(Rs2[3]), .ZN(n_1_0_650) + ); + NOR2_X1_LVT i_1_0_681( + .A1(n_1_0_651), .A2(n_1_0_650), .ZN(n_1_0_649) + ); + NOR4_X1_LVT i_1_0_649( + .A1(n_1_0_650), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), .ZN(n_1_0_617) + ); + AOI22_X1_LVT i_1_0_639( + .A1(registers_29__ap[31]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[31]), + .ZN(n_1_0_607) + ); + NOR4_X1_LVT i_1_0_676( + .A1(n_1_0_645), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), .ZN(n_1_0_644) + ); + OR2_X1_LVT i_1_0_679( + .A1(Rs2[0]), .A2(Rs2[3]), .ZN(n_1_0_647) + ); + NAND3_X1_LVT i_1_0_660( + .A1(n_1_0_1303), .A2(Rs2[1]), .A3(Rs2[2]), .ZN(n_1_0_628) + ); + NOR2_X1_LVT i_1_0_648( + .A1(n_1_0_647), .A2(n_1_0_628), .ZN(n_1_0_616) + ); + AOI22_X1_LVT i_1_0_638( + .A1(registers_1__ap[31]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[31]), + .ZN(n_1_0_606) + ); + NOR2_X1_LVT i_1_0_655( + .A1(n_1_0_645), .A2(n_1_0_628), .ZN(n_1_0_623) + ); + NAND3_X1_LVT i_1_0_675( + .A1(Rs2[2]), .A2(Rs2[4]), .A3(Rs2[1]), .ZN(n_1_0_643) + ); + NOR2_X1_LVT i_1_0_647( + .A1(n_1_0_645), .A2(n_1_0_643), .ZN(n_1_0_615) + ); + AOI22_X1_LVT i_1_0_637( + .A1(registers_7__ap[31]), .A2(n_1_0_623), .B1(n_1_0_615), .B2(registers_23__ap[31]), + .ZN(n_1_0_605) + ); + NOR2_X1_LVT i_1_0_665( + .A1(n_1_0_648), .A2(n_1_0_645), .ZN(n_1_0_633) + ); + NOR2_X1_LVT i_1_0_646( + .A1(n_1_0_647), .A2(n_1_0_630), .ZN(n_1_0_614) + ); + AOI22_X1_LVT i_1_0_636( + .A1(registers_19__ap[31]), .A2(n_1_0_633), .B1(n_1_0_614), .B2(registers_16__ap[31]), + .ZN(n_1_0_604) + ); + NOR2_X1_LVT i_1_0_669( + .A1(n_1_0_650), .A2(n_1_0_643), .ZN(n_1_0_637) + ); + NAND3_X1_LVT i_1_0_671( + .A1(n_1_0_1303), .A2(n_1_0_1302), .A3(Rs2[2]), .ZN(n_1_0_639) + ); + NOR2_X1_LVT i_1_0_667( + .A1(n_1_0_645), .A2(n_1_0_639), .ZN(n_1_0_635) + ); + AOI22_X1_LVT i_1_0_635( + .A1(registers_31__ap[31]), .A2(n_1_0_637), .B1(n_1_0_635), .B2(registers_5__ap[31]), + .ZN(n_1_0_603) + ); + NAND4_X1_LVT i_1_0_634( + .A1(n_1_0_606), .A2(n_1_0_605), .A3(n_1_0_604), .A4(n_1_0_603), .ZN(n_1_0_602) + ); + NOR2_X1_LVT i_1_0_678( + .A1(n_1_0_648), .A2(n_1_0_647), .ZN(n_1_0_646) + ); + NOR2_X1_LVT i_1_0_654( + .A1(n_1_0_643), .A2(n_1_0_641), .ZN(n_1_0_622) + ); + AOI22_X1_LVT i_1_0_633( + .A1(registers_18__ap[31]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[31]), + .ZN(n_1_0_601) + ); + NOR2_X1_LVT i_1_0_670( + .A1(n_1_0_647), .A2(n_1_0_639), .ZN(n_1_0_638) + ); + NOR2_X1_LVT i_1_0_645( + .A1(n_1_0_651), .A2(n_1_0_647), .ZN(n_1_0_613) + ); + AOI22_X1_LVT i_1_0_632( + .A1(registers_4__ap[31]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[31]), + .ZN(n_1_0_600) + ); + NOR2_X1_LVT i_1_0_674( + .A1(n_1_0_647), .A2(n_1_0_643), .ZN(n_1_0_642) + ); + NOR2_X1_LVT i_1_0_644( + .A1(n_1_0_651), .A2(n_1_0_645), .ZN(n_1_0_612) + ); + AOI22_X1_LVT i_1_0_631( + .A1(registers_22__ap[31]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[31]), + .ZN(n_1_0_599) + ); + NOR2_X1_LVT i_1_0_664( + .A1(n_1_0_641), .A2(n_1_0_639), .ZN(n_1_0_632) + ); + NOR2_X1_LVT i_1_0_653( + .A1(n_1_0_641), .A2(n_1_0_630), .ZN(n_1_0_621) + ); + AOI22_X1_LVT i_1_0_630( + .A1(registers_12__ap[31]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[31]), + .ZN(n_1_0_598) + ); + NAND4_X1_LVT i_1_0_629( + .A1(n_1_0_601), .A2(n_1_0_600), .A3(n_1_0_599), .A4(n_1_0_598), .ZN(n_1_0_597) + ); + NOR2_X1_LVT i_1_0_663( + .A1(n_1_0_650), .A2(n_1_0_639), .ZN(n_1_0_631) + ); + NOR2_X1_LVT i_1_0_652( + .A1(n_1_0_650), .A2(n_1_0_630), .ZN(n_1_0_620) + ); + AOI22_X1_LVT i_1_0_628( + .A1(registers_13__ap[31]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[31]), + .ZN(n_1_0_596) + ); + NOR2_X1_LVT i_1_0_659( + .A1(n_1_0_650), .A2(n_1_0_628), .ZN(n_1_0_627) + ); + NOR2_X1_LVT i_1_0_651( + .A1(n_1_0_641), .A2(n_1_0_628), .ZN(n_1_0_619) + ); + AOI22_X1_LVT i_1_0_627( + .A1(registers_15__ap[31]), .A2(n_1_0_627), .B1(n_1_0_619), .B2(registers_14__ap[31]), + .ZN(n_1_0_595) + ); + NOR2_X1_LVT i_1_0_668( + .A1(n_1_0_650), .A2(n_1_0_648), .ZN(n_1_0_636) + ); + NOR2_X1_LVT i_1_0_643( + .A1(n_1_0_650), .A2(n_1_0_625), .ZN(n_1_0_611) + ); + AOI22_X1_LVT i_1_0_626( + .A1(registers_27__ap[31]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[31]), + .ZN(n_1_0_594) + ); + NOR2_X1_LVT i_1_0_650( + .A1(n_1_0_647), .A2(n_1_0_625), .ZN(n_1_0_618) + ); + NOR2_X1_LVT i_1_0_642( + .A1(n_1_0_645), .A2(n_1_0_625), .ZN(n_1_0_610) + ); + AOI22_X1_LVT i_1_0_625( + .A1(registers_2__ap[31]), .A2(n_1_0_618), .B1(n_1_0_610), .B2(registers_3__ap[31]), + .ZN(n_1_0_593) + ); + NAND4_X1_LVT i_1_0_624( + .A1(n_1_0_596), .A2(n_1_0_595), .A3(n_1_0_594), .A4(n_1_0_593), .ZN(n_1_0_592) + ); + NOR3_X1_LVT i_1_0_623( + .A1(n_1_0_602), .A2(n_1_0_597), .A3(n_1_0_592), .ZN(n_1_0_591) + ); + NAND4_X1_LVT i_1_0_622( + .A1(n_1_0_609), .A2(n_1_0_608), .A3(n_1_0_607), .A4(n_1_0_591), .ZN(RRs2[31]) + ); + AOI22_X1_LVT i_1_0_620( + .A1(registers_29__ap[30]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[30]), + .ZN(n_1_0_589) + ); + AOI22_X1_LVT i_1_0_621( + .A1(registers_7__ap[30]), .A2(n_1_0_623), .B1(n_1_0_615), .B2(registers_23__ap[30]), + .ZN(n_1_0_590) + ); + AOI22_X1_LVT i_1_0_619( + .A1(registers_1__ap[30]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[30]), + .ZN(n_1_0_588) + ); + AOI22_X1_LVT i_1_0_618( + .A1(registers_5__ap[30]), .A2(n_1_0_635), .B1(n_1_0_633), .B2(registers_19__ap[30]), + .ZN(n_1_0_587) + ); + NAND3_X1_LVT i_1_0_617( + .A1(n_1_0_590), .A2(n_1_0_588), .A3(n_1_0_587), .ZN(n_1_0_586) + ); + AOI221_X1_LVT i_1_0_616( + .A(n_1_0_586), .B1(n_1_0_637), .B2(registers_31__ap[30]), .C1(registers_16__ap[30]), + .C2(n_1_0_614), .ZN(n_1_0_585) + ); + AOI222_X1_LVT i_1_0_615( + .A1(registers_26__ap[30]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[30]), + .C1(n_1_0_626), .C2(registers_8__ap[30]), .ZN(n_1_0_584) + ); + NAND3_X1_LVT i_1_0_614( + .A1(n_1_0_589), .A2(n_1_0_585), .A3(n_1_0_584), .ZN(n_1_0_583) + ); + AOI221_X1_LVT i_1_0_613( + .A(n_1_0_583), .B1(n_1_0_629), .B2(registers_17__ap[30]), .C1(registers_28__ap[30]), + .C2(n_1_0_634), .ZN(n_1_0_582) + ); + AOI22_X1_LVT i_1_0_612( + .A1(registers_18__ap[30]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[30]), + .ZN(n_1_0_581) + ); + AOI22_X1_LVT i_1_0_611( + .A1(registers_4__ap[30]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[30]), + .ZN(n_1_0_580) + ); + AOI22_X1_LVT i_1_0_610( + .A1(registers_22__ap[30]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[30]), + .ZN(n_1_0_579) + ); + NAND3_X1_LVT i_1_0_609( + .A1(n_1_0_581), .A2(n_1_0_580), .A3(n_1_0_579), .ZN(n_1_0_578) + ); + AOI221_X1_LVT i_1_0_608( + .A(n_1_0_578), .B1(n_1_0_621), .B2(registers_24__ap[30]), .C1(registers_12__ap[30]), + .C2(n_1_0_632), .ZN(n_1_0_577) + ); + AOI22_X1_LVT i_1_0_607( + .A1(registers_13__ap[30]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[30]), + .ZN(n_1_0_576) + ); + AOI22_X1_LVT i_1_0_606( + .A1(registers_15__ap[30]), .A2(n_1_0_627), .B1(n_1_0_619), .B2(registers_14__ap[30]), + .ZN(n_1_0_575) + ); + AOI22_X1_LVT i_1_0_605( + .A1(registers_27__ap[30]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[30]), + .ZN(n_1_0_574) + ); + NAND3_X1_LVT i_1_0_604( + .A1(n_1_0_576), .A2(n_1_0_575), .A3(n_1_0_574), .ZN(n_1_0_573) + ); + AOI221_X1_LVT i_1_0_603( + .A(n_1_0_573), .B1(n_1_0_610), .B2(registers_3__ap[30]), .C1(registers_2__ap[30]), + .C2(n_1_0_618), .ZN(n_1_0_572) + ); + NAND3_X1_LVT i_1_0_602( + .A1(n_1_0_582), .A2(n_1_0_577), .A3(n_1_0_572), .ZN(RRs2[30]) + ); + AOI22_X1_LVT i_1_0_600( + .A1(registers_28__ap[29]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[29]), + .ZN(n_1_0_570) + ); + AOI22_X1_LVT i_1_0_601( + .A1(registers_31__ap[29]), .A2(n_1_0_637), .B1(n_1_0_627), .B2(registers_15__ap[29]), + .ZN(n_1_0_571) + ); + AOI22_X1_LVT i_1_0_599( + .A1(registers_24__ap[29]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[29]), + .ZN(n_1_0_569) + ); + AOI22_X1_LVT i_1_0_598( + .A1(registers_19__ap[29]), .A2(n_1_0_633), .B1(n_1_0_629), .B2(registers_17__ap[29]), + .ZN(n_1_0_568) + ); + NAND3_X1_LVT i_1_0_597( + .A1(n_1_0_571), .A2(n_1_0_569), .A3(n_1_0_568), .ZN(n_1_0_567) + ); + AOI221_X1_LVT i_1_0_596( + .A(n_1_0_567), .B1(n_1_0_615), .B2(registers_23__ap[29]), .C1(registers_29__ap[29]), + .C2(n_1_0_649), .ZN(n_1_0_566) + ); + AOI222_X1_LVT i_1_0_595( + .A1(registers_26__ap[29]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[29]), + .C1(n_1_0_620), .C2(registers_25__ap[29]), .ZN(n_1_0_565) + ); + NAND3_X1_LVT i_1_0_594( + .A1(n_1_0_570), .A2(n_1_0_566), .A3(n_1_0_565), .ZN(n_1_0_564) + ); + AOI221_X1_LVT i_1_0_593( + .A(n_1_0_564), .B1(n_1_0_612), .B2(registers_21__ap[29]), .C1(registers_13__ap[29]), + .C2(n_1_0_631), .ZN(n_1_0_563) + ); + AOI22_X1_LVT i_1_0_592( + .A1(registers_18__ap[29]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[29]), + .ZN(n_1_0_562) + ); + AOI22_X1_LVT i_1_0_591( + .A1(registers_4__ap[29]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[29]), + .ZN(n_1_0_561) + ); + AOI22_X1_LVT i_1_0_590( + .A1(registers_7__ap[29]), .A2(n_1_0_623), .B1(n_1_0_614), .B2(registers_16__ap[29]), + .ZN(n_1_0_560) + ); + NAND3_X1_LVT i_1_0_589( + .A1(n_1_0_562), .A2(n_1_0_561), .A3(n_1_0_560), .ZN(n_1_0_559) + ); + AOI221_X1_LVT i_1_0_588( + .A(n_1_0_559), .B1(n_1_0_642), .B2(registers_22__ap[29]), .C1(registers_5__ap[29]), + .C2(n_1_0_635), .ZN(n_1_0_558) + ); + AOI22_X1_LVT i_1_0_587( + .A1(registers_1__ap[29]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[29]), + .ZN(n_1_0_557) + ); + AOI22_X1_LVT i_1_0_586( + .A1(registers_14__ap[29]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[29]), + .ZN(n_1_0_556) + ); + AOI22_X1_LVT i_1_0_585( + .A1(registers_27__ap[29]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[29]), + .ZN(n_1_0_555) + ); + NAND3_X1_LVT i_1_0_584( + .A1(n_1_0_557), .A2(n_1_0_556), .A3(n_1_0_555), .ZN(n_1_0_554) + ); + AOI221_X1_LVT i_1_0_583( + .A(n_1_0_554), .B1(n_1_0_610), .B2(registers_3__ap[29]), .C1(registers_2__ap[29]), + .C2(n_1_0_618), .ZN(n_1_0_553) + ); + NAND3_X1_LVT i_1_0_582( + .A1(n_1_0_563), .A2(n_1_0_558), .A3(n_1_0_553), .ZN(RRs2[29]) + ); + AOI22_X1_LVT i_1_0_581( + .A1(registers_5__ap[28]), .A2(n_1_0_635), .B1(n_1_0_634), .B2(registers_28__ap[28]), + .ZN(n_1_0_552) + ); + AOI222_X1_LVT i_1_0_580( + .A1(registers_26__ap[28]), .A2(n_1_0_640), .B1(n_1_0_633), .B2(registers_19__ap[28]), + .C1(n_1_0_626), .C2(registers_8__ap[28]), .ZN(n_1_0_551) + ); + AOI22_X1_LVT i_1_0_579( + .A1(registers_2__ap[28]), .A2(n_1_0_618), .B1(n_1_0_617), .B2(registers_9__ap[28]), + .ZN(n_1_0_550) + ); + AOI22_X1_LVT i_1_0_578( + .A1(registers_7__ap[28]), .A2(n_1_0_623), .B1(n_1_0_612), .B2(registers_21__ap[28]), + .ZN(n_1_0_549) + ); + AOI22_X1_LVT i_1_0_577( + .A1(registers_16__ap[28]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[28]), + .ZN(n_1_0_548) + ); + AOI22_X1_LVT i_1_0_576( + .A1(registers_31__ap[28]), .A2(n_1_0_637), .B1(n_1_0_619), .B2(registers_14__ap[28]), + .ZN(n_1_0_547) + ); + AOI22_X1_LVT i_1_0_575( + .A1(registers_15__ap[28]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[28]), + .ZN(n_1_0_546) + ); + NAND4_X1_LVT i_1_0_574( + .A1(n_1_0_549), .A2(n_1_0_548), .A3(n_1_0_547), .A4(n_1_0_546), .ZN(n_1_0_545) + ); + AOI22_X1_LVT i_1_0_573( + .A1(registers_22__ap[28]), .A2(n_1_0_642), .B1(n_1_0_622), .B2(registers_30__ap[28]), + .ZN(n_1_0_544) + ); + AOI22_X1_LVT i_1_0_572( + .A1(registers_4__ap[28]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[28]), + .ZN(n_1_0_543) + ); + AOI22_X1_LVT i_1_0_571( + .A1(registers_29__ap[28]), .A2(n_1_0_649), .B1(n_1_0_644), .B2(registers_1__ap[28]), + .ZN(n_1_0_542) + ); + AOI22_X1_LVT i_1_0_570( + .A1(registers_12__ap[28]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[28]), + .ZN(n_1_0_541) + ); + NAND4_X1_LVT i_1_0_569( + .A1(n_1_0_544), .A2(n_1_0_543), .A3(n_1_0_542), .A4(n_1_0_541), .ZN(n_1_0_540) + ); + AOI22_X1_LVT i_1_0_568( + .A1(registers_13__ap[28]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[28]), + .ZN(n_1_0_539) + ); + AOI22_X1_LVT i_1_0_567( + .A1(registers_17__ap[28]), .A2(n_1_0_629), .B1(n_1_0_616), .B2(registers_6__ap[28]), + .ZN(n_1_0_538) + ); + AOI22_X1_LVT i_1_0_566( + .A1(registers_10__ap[28]), .A2(n_1_0_624), .B1(n_1_0_615), .B2(registers_23__ap[28]), + .ZN(n_1_0_537) + ); + AOI22_X1_LVT i_1_0_565( + .A1(registers_18__ap[28]), .A2(n_1_0_646), .B1(n_1_0_636), .B2(registers_27__ap[28]), + .ZN(n_1_0_536) + ); + NAND4_X1_LVT i_1_0_564( + .A1(n_1_0_539), .A2(n_1_0_538), .A3(n_1_0_537), .A4(n_1_0_536), .ZN(n_1_0_535) + ); + NOR3_X1_LVT i_1_0_563( + .A1(n_1_0_545), .A2(n_1_0_540), .A3(n_1_0_535), .ZN(n_1_0_534) + ); + NAND4_X1_LVT i_1_0_562( + .A1(n_1_0_552), .A2(n_1_0_551), .A3(n_1_0_550), .A4(n_1_0_534), .ZN(RRs2[28]) + ); + AOI22_X1_LVT i_1_0_561( + .A1(registers_17__ap[27]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[27]), + .ZN(n_1_0_533) + ); + AOI222_X1_LVT i_1_0_560( + .A1(registers_19__ap[27]), .A2(n_1_0_633), .B1(n_1_0_631), .B2(registers_13__ap[27]), + .C1(registers_30__ap[27]), .C2(n_1_0_622), .ZN(n_1_0_532) + ); + AOI22_X1_LVT i_1_0_559( + .A1(registers_1__ap[27]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[27]), + .ZN(n_1_0_531) + ); + AOI22_X1_LVT i_1_0_558( + .A1(registers_24__ap[27]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[27]), + .ZN(n_1_0_530) + ); + AOI22_X1_LVT i_1_0_557( + .A1(registers_15__ap[27]), .A2(n_1_0_627), .B1(n_1_0_611), .B2(registers_11__ap[27]), + .ZN(n_1_0_529) + ); + AOI22_X1_LVT i_1_0_556( + .A1(registers_4__ap[27]), .A2(n_1_0_638), .B1(n_1_0_636), .B2(registers_27__ap[27]), + .ZN(n_1_0_528) + ); + AOI22_X1_LVT i_1_0_555( + .A1(registers_31__ap[27]), .A2(n_1_0_637), .B1(n_1_0_618), .B2(registers_2__ap[27]), + .ZN(n_1_0_527) + ); + NAND4_X1_LVT i_1_0_554( + .A1(n_1_0_530), .A2(n_1_0_529), .A3(n_1_0_528), .A4(n_1_0_527), .ZN(n_1_0_526) + ); + AOI22_X1_LVT i_1_0_553( + .A1(registers_18__ap[27]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[27]), + .ZN(n_1_0_525) + ); + AOI22_X1_LVT i_1_0_552( + .A1(registers_5__ap[27]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[27]), + .ZN(n_1_0_524) + ); + AOI22_X1_LVT i_1_0_551( + .A1(registers_6__ap[27]), .A2(n_1_0_616), .B1(n_1_0_614), .B2(registers_16__ap[27]), + .ZN(n_1_0_523) + ); + AOI22_X1_LVT i_1_0_550( + .A1(registers_22__ap[27]), .A2(n_1_0_642), .B1(n_1_0_620), .B2(registers_25__ap[27]), + .ZN(n_1_0_522) + ); + NAND4_X1_LVT i_1_0_549( + .A1(n_1_0_525), .A2(n_1_0_524), .A3(n_1_0_523), .A4(n_1_0_522), .ZN(n_1_0_521) + ); + AOI22_X1_LVT i_1_0_548( + .A1(registers_29__ap[27]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[27]), + .ZN(n_1_0_520) + ); + AOI22_X1_LVT i_1_0_547( + .A1(registers_7__ap[27]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[27]), + .ZN(n_1_0_519) + ); + AOI22_X1_LVT i_1_0_546( + .A1(registers_8__ap[27]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[27]), + .ZN(n_1_0_518) + ); + AOI22_X1_LVT i_1_0_545( + .A1(registers_10__ap[27]), .A2(n_1_0_624), .B1(n_1_0_610), .B2(registers_3__ap[27]), + .ZN(n_1_0_517) + ); + NAND4_X1_LVT i_1_0_544( + .A1(n_1_0_520), .A2(n_1_0_519), .A3(n_1_0_518), .A4(n_1_0_517), .ZN(n_1_0_516) + ); + NOR3_X1_LVT i_1_0_543( + .A1(n_1_0_526), .A2(n_1_0_521), .A3(n_1_0_516), .ZN(n_1_0_515) + ); + NAND4_X1_LVT i_1_0_542( + .A1(n_1_0_533), .A2(n_1_0_532), .A3(n_1_0_531), .A4(n_1_0_515), .ZN(RRs2[27]) + ); + AOI22_X1_LVT i_1_0_541( + .A1(registers_17__ap[26]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[26]), + .ZN(n_1_0_514) + ); + AOI222_X1_LVT i_1_0_540( + .A1(registers_19__ap[26]), .A2(n_1_0_633), .B1(n_1_0_622), .B2(registers_30__ap[26]), + .C1(n_1_0_631), .C2(registers_13__ap[26]), .ZN(n_1_0_513) + ); + AOI22_X1_LVT i_1_0_539( + .A1(registers_1__ap[26]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[26]), + .ZN(n_1_0_512) + ); + AOI22_X1_LVT i_1_0_538( + .A1(registers_24__ap[26]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[26]), + .ZN(n_1_0_511) + ); + AOI22_X1_LVT i_1_0_537( + .A1(registers_15__ap[26]), .A2(n_1_0_627), .B1(n_1_0_611), .B2(registers_11__ap[26]), + .ZN(n_1_0_510) + ); + AOI22_X1_LVT i_1_0_536( + .A1(registers_4__ap[26]), .A2(n_1_0_638), .B1(n_1_0_636), .B2(registers_27__ap[26]), + .ZN(n_1_0_509) + ); + AOI22_X1_LVT i_1_0_535( + .A1(registers_31__ap[26]), .A2(n_1_0_637), .B1(n_1_0_618), .B2(registers_2__ap[26]), + .ZN(n_1_0_508) + ); + NAND4_X1_LVT i_1_0_534( + .A1(n_1_0_511), .A2(n_1_0_510), .A3(n_1_0_509), .A4(n_1_0_508), .ZN(n_1_0_507) + ); + AOI22_X1_LVT i_1_0_533( + .A1(registers_18__ap[26]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[26]), + .ZN(n_1_0_506) + ); + AOI22_X1_LVT i_1_0_532( + .A1(registers_5__ap[26]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[26]), + .ZN(n_1_0_505) + ); + AOI22_X1_LVT i_1_0_531( + .A1(registers_6__ap[26]), .A2(n_1_0_616), .B1(n_1_0_614), .B2(registers_16__ap[26]), + .ZN(n_1_0_504) + ); + AOI22_X1_LVT i_1_0_530( + .A1(registers_22__ap[26]), .A2(n_1_0_642), .B1(n_1_0_620), .B2(registers_25__ap[26]), + .ZN(n_1_0_503) + ); + NAND4_X1_LVT i_1_0_529( + .A1(n_1_0_506), .A2(n_1_0_505), .A3(n_1_0_504), .A4(n_1_0_503), .ZN(n_1_0_502) + ); + AOI22_X1_LVT i_1_0_528( + .A1(registers_29__ap[26]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[26]), + .ZN(n_1_0_501) + ); + AOI22_X1_LVT i_1_0_527( + .A1(registers_7__ap[26]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[26]), + .ZN(n_1_0_500) + ); + AOI22_X1_LVT i_1_0_526( + .A1(registers_8__ap[26]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[26]), + .ZN(n_1_0_499) + ); + AOI22_X1_LVT i_1_0_525( + .A1(registers_10__ap[26]), .A2(n_1_0_624), .B1(n_1_0_610), .B2(registers_3__ap[26]), + .ZN(n_1_0_498) + ); + NAND4_X1_LVT i_1_0_524( + .A1(n_1_0_501), .A2(n_1_0_500), .A3(n_1_0_499), .A4(n_1_0_498), .ZN(n_1_0_497) + ); + NOR3_X1_LVT i_1_0_523( + .A1(n_1_0_507), .A2(n_1_0_502), .A3(n_1_0_497), .ZN(n_1_0_496) + ); + NAND4_X1_LVT i_1_0_522( + .A1(n_1_0_514), .A2(n_1_0_513), .A3(n_1_0_512), .A4(n_1_0_496), .ZN(RRs2[26]) + ); + AOI22_X1_LVT i_1_0_520( + .A1(registers_5__ap[25]), .A2(n_1_0_635), .B1(n_1_0_634), .B2(registers_28__ap[25]), + .ZN(n_1_0_494) + ); + AOI22_X1_LVT i_1_0_521( + .A1(registers_8__ap[25]), .A2(n_1_0_626), .B1(n_1_0_620), .B2(registers_25__ap[25]), + .ZN(n_1_0_495) + ); + AOI22_X1_LVT i_1_0_519( + .A1(registers_14__ap[25]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[25]), + .ZN(n_1_0_493) + ); + AOI22_X1_LVT i_1_0_518( + .A1(registers_16__ap[25]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[25]), + .ZN(n_1_0_492) + ); + NAND3_X1_LVT i_1_0_517( + .A1(n_1_0_495), .A2(n_1_0_493), .A3(n_1_0_492), .ZN(n_1_0_491) + ); + AOI221_X1_LVT i_1_0_516( + .A(n_1_0_491), .B1(n_1_0_624), .B2(registers_10__ap[25]), .C1(registers_6__ap[25]), + .C2(n_1_0_616), .ZN(n_1_0_490) + ); + AOI222_X1_LVT i_1_0_515( + .A1(registers_1__ap[25]), .A2(n_1_0_644), .B1(n_1_0_640), .B2(registers_26__ap[25]), + .C1(n_1_0_622), .C2(registers_30__ap[25]), .ZN(n_1_0_489) + ); + NAND2_X1_LVT i_1_0_514( + .A1(n_1_0_490), .A2(n_1_0_489), .ZN(n_1_0_488) + ); + AOI221_X1_LVT i_1_0_513( + .A(n_1_0_488), .B1(n_1_0_649), .B2(registers_29__ap[25]), .C1(registers_2__ap[25]), + .C2(n_1_0_618), .ZN(n_1_0_487) + ); + AOI22_X1_LVT i_1_0_512( + .A1(registers_12__ap[25]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[25]), + .ZN(n_1_0_486) + ); + AOI22_X1_LVT i_1_0_511( + .A1(registers_22__ap[25]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[25]), + .ZN(n_1_0_485) + ); + AOI22_X1_LVT i_1_0_510( + .A1(registers_4__ap[25]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[25]), + .ZN(n_1_0_484) + ); + NAND3_X1_LVT i_1_0_509( + .A1(n_1_0_486), .A2(n_1_0_485), .A3(n_1_0_484), .ZN(n_1_0_483) + ); + AOI221_X1_LVT i_1_0_508( + .A(n_1_0_483), .B1(n_1_0_633), .B2(registers_19__ap[25]), .C1(registers_18__ap[25]), + .C2(n_1_0_646), .ZN(n_1_0_482) + ); + AOI22_X1_LVT i_1_0_507( + .A1(registers_15__ap[25]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[25]), + .ZN(n_1_0_481) + ); + AOI22_X1_LVT i_1_0_506( + .A1(registers_23__ap[25]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[25]), + .ZN(n_1_0_480) + ); + AOI22_X1_LVT i_1_0_505( + .A1(registers_13__ap[25]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[25]), + .ZN(n_1_0_479) + ); + NAND3_X1_LVT i_1_0_504( + .A1(n_1_0_481), .A2(n_1_0_480), .A3(n_1_0_479), .ZN(n_1_0_478) + ); + AOI221_X1_LVT i_1_0_503( + .A(n_1_0_478), .B1(n_1_0_636), .B2(registers_27__ap[25]), .C1(registers_31__ap[25]), + .C2(n_1_0_637), .ZN(n_1_0_477) + ); + NAND4_X1_LVT i_1_0_502( + .A1(n_1_0_494), .A2(n_1_0_487), .A3(n_1_0_482), .A4(n_1_0_477), .ZN(RRs2[25]) + ); + AOI22_X1_LVT i_1_0_501( + .A1(registers_17__ap[24]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[24]), + .ZN(n_1_0_476) + ); + AOI222_X1_LVT i_1_0_500( + .A1(registers_13__ap[24]), .A2(n_1_0_631), .B1(n_1_0_622), .B2(registers_30__ap[24]), + .C1(registers_26__ap[24]), .C2(n_1_0_640), .ZN(n_1_0_475) + ); + AOI22_X1_LVT i_1_0_499( + .A1(registers_1__ap[24]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[24]), + .ZN(n_1_0_474) + ); + AOI22_X1_LVT i_1_0_498( + .A1(registers_24__ap[24]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[24]), + .ZN(n_1_0_473) + ); + AOI22_X1_LVT i_1_0_497( + .A1(registers_8__ap[24]), .A2(n_1_0_626), .B1(n_1_0_616), .B2(registers_6__ap[24]), + .ZN(n_1_0_472) + ); + AOI22_X1_LVT i_1_0_496( + .A1(registers_4__ap[24]), .A2(n_1_0_638), .B1(n_1_0_611), .B2(registers_11__ap[24]), + .ZN(n_1_0_471) + ); + AOI22_X1_LVT i_1_0_495( + .A1(registers_10__ap[24]), .A2(n_1_0_624), .B1(n_1_0_618), .B2(registers_2__ap[24]), + .ZN(n_1_0_470) + ); + NAND4_X1_LVT i_1_0_494( + .A1(n_1_0_473), .A2(n_1_0_472), .A3(n_1_0_471), .A4(n_1_0_470), .ZN(n_1_0_469) + ); + AOI22_X1_LVT i_1_0_493( + .A1(registers_18__ap[24]), .A2(n_1_0_646), .B1(n_1_0_633), .B2(registers_19__ap[24]), + .ZN(n_1_0_468) + ); + AOI22_X1_LVT i_1_0_492( + .A1(registers_5__ap[24]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[24]), + .ZN(n_1_0_467) + ); + AOI22_X1_LVT i_1_0_491( + .A1(registers_15__ap[24]), .A2(n_1_0_627), .B1(n_1_0_614), .B2(registers_16__ap[24]), + .ZN(n_1_0_466) + ); + AOI22_X1_LVT i_1_0_490( + .A1(registers_22__ap[24]), .A2(n_1_0_642), .B1(n_1_0_620), .B2(registers_25__ap[24]), + .ZN(n_1_0_465) + ); + NAND4_X1_LVT i_1_0_489( + .A1(n_1_0_468), .A2(n_1_0_467), .A3(n_1_0_466), .A4(n_1_0_465), .ZN(n_1_0_464) + ); + AOI22_X1_LVT i_1_0_488( + .A1(registers_29__ap[24]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[24]), + .ZN(n_1_0_463) + ); + AOI22_X1_LVT i_1_0_487( + .A1(registers_7__ap[24]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[24]), + .ZN(n_1_0_462) + ); + AOI22_X1_LVT i_1_0_486( + .A1(registers_23__ap[24]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[24]), + .ZN(n_1_0_461) + ); + AOI22_X1_LVT i_1_0_485( + .A1(registers_31__ap[24]), .A2(n_1_0_637), .B1(n_1_0_636), .B2(registers_27__ap[24]), + .ZN(n_1_0_460) + ); + NAND4_X1_LVT i_1_0_484( + .A1(n_1_0_463), .A2(n_1_0_462), .A3(n_1_0_461), .A4(n_1_0_460), .ZN(n_1_0_459) + ); + NOR3_X1_LVT i_1_0_483( + .A1(n_1_0_469), .A2(n_1_0_464), .A3(n_1_0_459), .ZN(n_1_0_458) + ); + NAND4_X1_LVT i_1_0_482( + .A1(n_1_0_476), .A2(n_1_0_475), .A3(n_1_0_474), .A4(n_1_0_458), .ZN(RRs2[24]) + ); + AOI22_X1_LVT i_1_0_481( + .A1(registers_4__ap[23]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[23]), + .ZN(n_1_0_457) + ); + AOI222_X1_LVT i_1_0_480( + .A1(registers_18__ap[23]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[23]), + .C1(n_1_0_644), .C2(registers_1__ap[23]), .ZN(n_1_0_456) + ); + AOI22_X1_LVT i_1_0_479( + .A1(registers_29__ap[23]), .A2(n_1_0_649), .B1(n_1_0_618), .B2(registers_2__ap[23]), + .ZN(n_1_0_455) + ); + AOI22_X1_LVT i_1_0_478( + .A1(registers_14__ap[23]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[23]), + .ZN(n_1_0_454) + ); + AOI22_X1_LVT i_1_0_477( + .A1(registers_16__ap[23]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[23]), + .ZN(n_1_0_453) + ); + AOI22_X1_LVT i_1_0_476( + .A1(registers_27__ap[23]), .A2(n_1_0_636), .B1(n_1_0_620), .B2(registers_25__ap[23]), + .ZN(n_1_0_452) + ); + AOI22_X1_LVT i_1_0_475( + .A1(registers_31__ap[23]), .A2(n_1_0_637), .B1(n_1_0_616), .B2(registers_6__ap[23]), + .ZN(n_1_0_451) + ); + NAND4_X1_LVT i_1_0_474( + .A1(n_1_0_454), .A2(n_1_0_453), .A3(n_1_0_452), .A4(n_1_0_451), .ZN(n_1_0_450) + ); + AOI22_X1_LVT i_1_0_473( + .A1(registers_26__ap[23]), .A2(n_1_0_640), .B1(n_1_0_633), .B2(registers_19__ap[23]), + .ZN(n_1_0_449) + ); + AOI22_X1_LVT i_1_0_472( + .A1(registers_12__ap[23]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[23]), + .ZN(n_1_0_448) + ); + AOI22_X1_LVT i_1_0_471( + .A1(registers_22__ap[23]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[23]), + .ZN(n_1_0_447) + ); + AOI22_X1_LVT i_1_0_470( + .A1(registers_5__ap[23]), .A2(n_1_0_635), .B1(n_1_0_613), .B2(registers_20__ap[23]), + .ZN(n_1_0_446) + ); + NAND4_X1_LVT i_1_0_469( + .A1(n_1_0_449), .A2(n_1_0_448), .A3(n_1_0_447), .A4(n_1_0_446), .ZN(n_1_0_445) + ); + AOI22_X1_LVT i_1_0_468( + .A1(registers_15__ap[23]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[23]), + .ZN(n_1_0_444) + ); + AOI22_X1_LVT i_1_0_467( + .A1(registers_8__ap[23]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[23]), + .ZN(n_1_0_443) + ); + AOI22_X1_LVT i_1_0_466( + .A1(registers_13__ap[23]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[23]), + .ZN(n_1_0_442) + ); + AOI22_X1_LVT i_1_0_465( + .A1(registers_10__ap[23]), .A2(n_1_0_624), .B1(n_1_0_610), .B2(registers_3__ap[23]), + .ZN(n_1_0_441) + ); + NAND4_X1_LVT i_1_0_464( + .A1(n_1_0_444), .A2(n_1_0_443), .A3(n_1_0_442), .A4(n_1_0_441), .ZN(n_1_0_440) + ); + NOR3_X1_LVT i_1_0_463( + .A1(n_1_0_450), .A2(n_1_0_445), .A3(n_1_0_440), .ZN(n_1_0_439) + ); + NAND4_X1_LVT i_1_0_462( + .A1(n_1_0_457), .A2(n_1_0_456), .A3(n_1_0_455), .A4(n_1_0_439), .ZN(RRs2[23]) + ); + AOI22_X1_LVT i_1_0_460( + .A1(registers_17__ap[22]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[22]), + .ZN(n_1_0_437) + ); + AOI22_X1_LVT i_1_0_461( + .A1(registers_15__ap[22]), .A2(n_1_0_627), .B1(n_1_0_626), .B2(registers_8__ap[22]), + .ZN(n_1_0_438) + ); + AOI22_X1_LVT i_1_0_459( + .A1(registers_24__ap[22]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[22]), + .ZN(n_1_0_436) + ); + AOI22_X1_LVT i_1_0_458( + .A1(registers_5__ap[22]), .A2(n_1_0_635), .B1(n_1_0_611), .B2(registers_11__ap[22]), + .ZN(n_1_0_435) + ); + NAND3_X1_LVT i_1_0_457( + .A1(n_1_0_438), .A2(n_1_0_436), .A3(n_1_0_435), .ZN(n_1_0_434) + ); + AOI221_X1_LVT i_1_0_456( + .A(n_1_0_434), .B1(n_1_0_618), .B2(registers_2__ap[22]), .C1(registers_10__ap[22]), + .C2(n_1_0_624), .ZN(n_1_0_433) + ); + AOI222_X1_LVT i_1_0_455( + .A1(registers_26__ap[22]), .A2(n_1_0_640), .B1(n_1_0_622), .B2(registers_30__ap[22]), + .C1(n_1_0_631), .C2(registers_13__ap[22]), .ZN(n_1_0_432) + ); + NAND2_X1_LVT i_1_0_454( + .A1(n_1_0_433), .A2(n_1_0_432), .ZN(n_1_0_431) + ); + AOI221_X1_LVT i_1_0_453( + .A(n_1_0_431), .B1(n_1_0_644), .B2(registers_1__ap[22]), .C1(registers_28__ap[22]), + .C2(n_1_0_634), .ZN(n_1_0_430) + ); + AOI22_X1_LVT i_1_0_452( + .A1(registers_18__ap[22]), .A2(n_1_0_646), .B1(n_1_0_633), .B2(registers_19__ap[22]), + .ZN(n_1_0_429) + ); + AOI22_X1_LVT i_1_0_451( + .A1(registers_4__ap[22]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[22]), + .ZN(n_1_0_428) + ); + AOI22_X1_LVT i_1_0_450( + .A1(registers_6__ap[22]), .A2(n_1_0_616), .B1(n_1_0_614), .B2(registers_16__ap[22]), + .ZN(n_1_0_427) + ); + NAND3_X1_LVT i_1_0_449( + .A1(n_1_0_429), .A2(n_1_0_428), .A3(n_1_0_427), .ZN(n_1_0_426) + ); + AOI221_X1_LVT i_1_0_448( + .A(n_1_0_426), .B1(n_1_0_620), .B2(registers_25__ap[22]), .C1(registers_22__ap[22]), + .C2(n_1_0_642), .ZN(n_1_0_425) + ); + AOI22_X1_LVT i_1_0_447( + .A1(registers_29__ap[22]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[22]), + .ZN(n_1_0_424) + ); + AOI22_X1_LVT i_1_0_446( + .A1(registers_7__ap[22]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[22]), + .ZN(n_1_0_423) + ); + AOI22_X1_LVT i_1_0_445( + .A1(registers_23__ap[22]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[22]), + .ZN(n_1_0_422) + ); + NAND3_X1_LVT i_1_0_444( + .A1(n_1_0_424), .A2(n_1_0_423), .A3(n_1_0_422), .ZN(n_1_0_421) + ); + AOI221_X1_LVT i_1_0_443( + .A(n_1_0_421), .B1(n_1_0_636), .B2(registers_27__ap[22]), .C1(registers_31__ap[22]), + .C2(n_1_0_637), .ZN(n_1_0_420) + ); + NAND4_X1_LVT i_1_0_442( + .A1(n_1_0_437), .A2(n_1_0_430), .A3(n_1_0_425), .A4(n_1_0_420), .ZN(RRs2[22]) + ); + AOI22_X1_LVT i_1_0_441( + .A1(registers_5__ap[21]), .A2(n_1_0_635), .B1(n_1_0_634), .B2(registers_28__ap[21]), + .ZN(n_1_0_419) + ); + AOI222_X1_LVT i_1_0_440( + .A1(registers_1__ap[21]), .A2(n_1_0_644), .B1(n_1_0_640), .B2(registers_26__ap[21]), + .C1(n_1_0_622), .C2(registers_30__ap[21]), .ZN(n_1_0_418) + ); + AOI22_X1_LVT i_1_0_439( + .A1(registers_29__ap[21]), .A2(n_1_0_649), .B1(n_1_0_618), .B2(registers_2__ap[21]), + .ZN(n_1_0_417) + ); + AOI22_X1_LVT i_1_0_438( + .A1(registers_14__ap[21]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[21]), + .ZN(n_1_0_416) + ); + AOI22_X1_LVT i_1_0_437( + .A1(registers_8__ap[21]), .A2(n_1_0_626), .B1(n_1_0_614), .B2(registers_16__ap[21]), + .ZN(n_1_0_415) + ); + AOI22_X1_LVT i_1_0_436( + .A1(registers_25__ap[21]), .A2(n_1_0_620), .B1(n_1_0_611), .B2(registers_11__ap[21]), + .ZN(n_1_0_414) + ); + AOI22_X1_LVT i_1_0_435( + .A1(registers_10__ap[21]), .A2(n_1_0_624), .B1(n_1_0_616), .B2(registers_6__ap[21]), + .ZN(n_1_0_413) + ); + NAND4_X1_LVT i_1_0_434( + .A1(n_1_0_416), .A2(n_1_0_415), .A3(n_1_0_414), .A4(n_1_0_413), .ZN(n_1_0_412) + ); + AOI22_X1_LVT i_1_0_433( + .A1(registers_12__ap[21]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[21]), + .ZN(n_1_0_411) + ); + AOI22_X1_LVT i_1_0_432( + .A1(registers_22__ap[21]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[21]), + .ZN(n_1_0_410) + ); + AOI22_X1_LVT i_1_0_431( + .A1(registers_4__ap[21]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[21]), + .ZN(n_1_0_409) + ); + AOI22_X1_LVT i_1_0_430( + .A1(registers_18__ap[21]), .A2(n_1_0_646), .B1(n_1_0_633), .B2(registers_19__ap[21]), + .ZN(n_1_0_408) + ); + NAND4_X1_LVT i_1_0_429( + .A1(n_1_0_411), .A2(n_1_0_410), .A3(n_1_0_409), .A4(n_1_0_408), .ZN(n_1_0_407) + ); + AOI22_X1_LVT i_1_0_428( + .A1(registers_15__ap[21]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[21]), + .ZN(n_1_0_406) + ); + AOI22_X1_LVT i_1_0_427( + .A1(registers_23__ap[21]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[21]), + .ZN(n_1_0_405) + ); + AOI22_X1_LVT i_1_0_426( + .A1(registers_13__ap[21]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[21]), + .ZN(n_1_0_404) + ); + AOI22_X1_LVT i_1_0_425( + .A1(registers_31__ap[21]), .A2(n_1_0_637), .B1(n_1_0_636), .B2(registers_27__ap[21]), + .ZN(n_1_0_403) + ); + NAND4_X1_LVT i_1_0_424( + .A1(n_1_0_406), .A2(n_1_0_405), .A3(n_1_0_404), .A4(n_1_0_403), .ZN(n_1_0_402) + ); + NOR3_X1_LVT i_1_0_423( + .A1(n_1_0_412), .A2(n_1_0_407), .A3(n_1_0_402), .ZN(n_1_0_401) + ); + NAND4_X1_LVT i_1_0_422( + .A1(n_1_0_419), .A2(n_1_0_418), .A3(n_1_0_417), .A4(n_1_0_401), .ZN(RRs2[21]) + ); + AOI22_X1_LVT i_1_0_421( + .A1(registers_17__ap[20]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[20]), + .ZN(n_1_0_400) + ); + AOI222_X1_LVT i_1_0_420( + .A1(registers_13__ap[20]), .A2(n_1_0_631), .B1(n_1_0_622), .B2(registers_30__ap[20]), + .C1(registers_19__ap[20]), .C2(n_1_0_633), .ZN(n_1_0_399) + ); + AOI22_X1_LVT i_1_0_419( + .A1(registers_1__ap[20]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[20]), + .ZN(n_1_0_398) + ); + AOI22_X1_LVT i_1_0_418( + .A1(registers_24__ap[20]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[20]), + .ZN(n_1_0_397) + ); + AOI22_X1_LVT i_1_0_417( + .A1(registers_6__ap[20]), .A2(n_1_0_616), .B1(n_1_0_611), .B2(registers_11__ap[20]), + .ZN(n_1_0_396) + ); + AOI22_X1_LVT i_1_0_416( + .A1(registers_4__ap[20]), .A2(n_1_0_638), .B1(n_1_0_624), .B2(registers_10__ap[20]), + .ZN(n_1_0_395) + ); + AOI22_X1_LVT i_1_0_415( + .A1(registers_31__ap[20]), .A2(n_1_0_637), .B1(n_1_0_618), .B2(registers_2__ap[20]), + .ZN(n_1_0_394) + ); + NAND4_X1_LVT i_1_0_414( + .A1(n_1_0_397), .A2(n_1_0_396), .A3(n_1_0_395), .A4(n_1_0_394), .ZN(n_1_0_393) + ); + AOI22_X1_LVT i_1_0_413( + .A1(registers_18__ap[20]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[20]), + .ZN(n_1_0_392) + ); + AOI22_X1_LVT i_1_0_412( + .A1(registers_5__ap[20]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[20]), + .ZN(n_1_0_391) + ); + AOI22_X1_LVT i_1_0_411( + .A1(registers_15__ap[20]), .A2(n_1_0_627), .B1(n_1_0_614), .B2(registers_16__ap[20]), + .ZN(n_1_0_390) + ); + AOI22_X1_LVT i_1_0_410( + .A1(registers_22__ap[20]), .A2(n_1_0_642), .B1(n_1_0_620), .B2(registers_25__ap[20]), + .ZN(n_1_0_389) + ); + NAND4_X1_LVT i_1_0_409( + .A1(n_1_0_392), .A2(n_1_0_391), .A3(n_1_0_390), .A4(n_1_0_389), .ZN(n_1_0_388) + ); + AOI22_X1_LVT i_1_0_408( + .A1(registers_29__ap[20]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[20]), + .ZN(n_1_0_387) + ); + AOI22_X1_LVT i_1_0_407( + .A1(registers_7__ap[20]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[20]), + .ZN(n_1_0_386) + ); + AOI22_X1_LVT i_1_0_406( + .A1(registers_8__ap[20]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[20]), + .ZN(n_1_0_385) + ); + AOI22_X1_LVT i_1_0_405( + .A1(registers_27__ap[20]), .A2(n_1_0_636), .B1(n_1_0_610), .B2(registers_3__ap[20]), + .ZN(n_1_0_384) + ); + NAND4_X1_LVT i_1_0_404( + .A1(n_1_0_387), .A2(n_1_0_386), .A3(n_1_0_385), .A4(n_1_0_384), .ZN(n_1_0_383) + ); + NOR3_X1_LVT i_1_0_403( + .A1(n_1_0_393), .A2(n_1_0_388), .A3(n_1_0_383), .ZN(n_1_0_382) + ); + NAND4_X1_LVT i_1_0_402( + .A1(n_1_0_400), .A2(n_1_0_399), .A3(n_1_0_398), .A4(n_1_0_382), .ZN(RRs2[20]) + ); + AOI22_X1_LVT i_1_0_401( + .A1(registers_17__ap[19]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[19]), + .ZN(n_1_0_381) + ); + AOI222_X1_LVT i_1_0_400( + .A1(registers_13__ap[19]), .A2(n_1_0_631), .B1(n_1_0_622), .B2(registers_30__ap[19]), + .C1(registers_19__ap[19]), .C2(n_1_0_633), .ZN(n_1_0_380) + ); + AOI22_X1_LVT i_1_0_399( + .A1(registers_1__ap[19]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[19]), + .ZN(n_1_0_379) + ); + AOI22_X1_LVT i_1_0_398( + .A1(registers_24__ap[19]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[19]), + .ZN(n_1_0_378) + ); + AOI22_X1_LVT i_1_0_397( + .A1(registers_15__ap[19]), .A2(n_1_0_627), .B1(n_1_0_611), .B2(registers_11__ap[19]), + .ZN(n_1_0_377) + ); + AOI22_X1_LVT i_1_0_396( + .A1(registers_4__ap[19]), .A2(n_1_0_638), .B1(n_1_0_636), .B2(registers_27__ap[19]), + .ZN(n_1_0_376) + ); + AOI22_X1_LVT i_1_0_395( + .A1(registers_31__ap[19]), .A2(n_1_0_637), .B1(n_1_0_618), .B2(registers_2__ap[19]), + .ZN(n_1_0_375) + ); + NAND4_X1_LVT i_1_0_394( + .A1(n_1_0_378), .A2(n_1_0_377), .A3(n_1_0_376), .A4(n_1_0_375), .ZN(n_1_0_374) + ); + AOI22_X1_LVT i_1_0_393( + .A1(registers_18__ap[19]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[19]), + .ZN(n_1_0_373) + ); + AOI22_X1_LVT i_1_0_392( + .A1(registers_5__ap[19]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[19]), + .ZN(n_1_0_372) + ); + AOI22_X1_LVT i_1_0_391( + .A1(registers_25__ap[19]), .A2(n_1_0_620), .B1(n_1_0_616), .B2(registers_6__ap[19]), + .ZN(n_1_0_371) + ); + AOI22_X1_LVT i_1_0_390( + .A1(registers_22__ap[19]), .A2(n_1_0_642), .B1(n_1_0_614), .B2(registers_16__ap[19]), + .ZN(n_1_0_370) + ); + NAND4_X1_LVT i_1_0_389( + .A1(n_1_0_373), .A2(n_1_0_372), .A3(n_1_0_371), .A4(n_1_0_370), .ZN(n_1_0_369) + ); + AOI22_X1_LVT i_1_0_388( + .A1(registers_29__ap[19]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[19]), + .ZN(n_1_0_368) + ); + AOI22_X1_LVT i_1_0_387( + .A1(registers_7__ap[19]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[19]), + .ZN(n_1_0_367) + ); + AOI22_X1_LVT i_1_0_386( + .A1(registers_8__ap[19]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[19]), + .ZN(n_1_0_366) + ); + AOI22_X1_LVT i_1_0_385( + .A1(registers_10__ap[19]), .A2(n_1_0_624), .B1(n_1_0_610), .B2(registers_3__ap[19]), + .ZN(n_1_0_365) + ); + NAND4_X1_LVT i_1_0_384( + .A1(n_1_0_368), .A2(n_1_0_367), .A3(n_1_0_366), .A4(n_1_0_365), .ZN(n_1_0_364) + ); + NOR3_X1_LVT i_1_0_383( + .A1(n_1_0_374), .A2(n_1_0_369), .A3(n_1_0_364), .ZN(n_1_0_363) + ); + NAND4_X1_LVT i_1_0_382( + .A1(n_1_0_381), .A2(n_1_0_380), .A3(n_1_0_379), .A4(n_1_0_363), .ZN(RRs2[19]) + ); + AOI22_X1_LVT i_1_0_380( + .A1(registers_4__ap[18]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[18]), + .ZN(n_1_0_361) + ); + AOI22_X1_LVT i_1_0_381( + .A1(registers_8__ap[18]), .A2(n_1_0_626), .B1(n_1_0_614), .B2(registers_16__ap[18]), + .ZN(n_1_0_362) + ); + AOI22_X1_LVT i_1_0_379( + .A1(registers_14__ap[18]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[18]), + .ZN(n_1_0_360) + ); + AOI22_X1_LVT i_1_0_378( + .A1(registers_25__ap[18]), .A2(n_1_0_620), .B1(n_1_0_611), .B2(registers_11__ap[18]), + .ZN(n_1_0_359) + ); + NAND3_X1_LVT i_1_0_377( + .A1(n_1_0_362), .A2(n_1_0_360), .A3(n_1_0_359), .ZN(n_1_0_358) + ); + AOI221_X1_LVT i_1_0_376( + .A(n_1_0_358), .B1(n_1_0_624), .B2(registers_10__ap[18]), .C1(registers_6__ap[18]), + .C2(n_1_0_616), .ZN(n_1_0_357) + ); + AOI222_X1_LVT i_1_0_375( + .A1(registers_1__ap[18]), .A2(n_1_0_644), .B1(n_1_0_640), .B2(registers_26__ap[18]), + .C1(n_1_0_622), .C2(registers_30__ap[18]), .ZN(n_1_0_356) + ); + NAND2_X1_LVT i_1_0_374( + .A1(n_1_0_357), .A2(n_1_0_356), .ZN(n_1_0_355) + ); + AOI221_X1_LVT i_1_0_373( + .A(n_1_0_355), .B1(n_1_0_649), .B2(registers_29__ap[18]), .C1(registers_2__ap[18]), + .C2(n_1_0_618), .ZN(n_1_0_354) + ); + AOI22_X1_LVT i_1_0_372( + .A1(registers_18__ap[18]), .A2(n_1_0_646), .B1(n_1_0_633), .B2(registers_19__ap[18]), + .ZN(n_1_0_353) + ); + AOI22_X1_LVT i_1_0_371( + .A1(registers_12__ap[18]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[18]), + .ZN(n_1_0_352) + ); + AOI22_X1_LVT i_1_0_370( + .A1(registers_22__ap[18]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[18]), + .ZN(n_1_0_351) + ); + NAND3_X1_LVT i_1_0_369( + .A1(n_1_0_353), .A2(n_1_0_352), .A3(n_1_0_351), .ZN(n_1_0_350) + ); + AOI221_X1_LVT i_1_0_368( + .A(n_1_0_350), .B1(n_1_0_635), .B2(registers_5__ap[18]), .C1(registers_20__ap[18]), + .C2(n_1_0_613), .ZN(n_1_0_349) + ); + AOI22_X1_LVT i_1_0_367( + .A1(registers_15__ap[18]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[18]), + .ZN(n_1_0_348) + ); + AOI22_X1_LVT i_1_0_366( + .A1(registers_23__ap[18]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[18]), + .ZN(n_1_0_347) + ); + AOI22_X1_LVT i_1_0_365( + .A1(registers_13__ap[18]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[18]), + .ZN(n_1_0_346) + ); + NAND3_X1_LVT i_1_0_364( + .A1(n_1_0_348), .A2(n_1_0_347), .A3(n_1_0_346), .ZN(n_1_0_345) + ); + AOI221_X1_LVT i_1_0_363( + .A(n_1_0_345), .B1(n_1_0_637), .B2(registers_31__ap[18]), .C1(registers_27__ap[18]), + .C2(n_1_0_636), .ZN(n_1_0_344) + ); + NAND4_X1_LVT i_1_0_362( + .A1(n_1_0_361), .A2(n_1_0_354), .A3(n_1_0_349), .A4(n_1_0_344), .ZN(RRs2[18]) + ); + AOI22_X1_LVT i_1_0_358( + .A1(registers_4__ap[17]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[17]), + .ZN(n_1_0_340) + ); + AOI22_X1_LVT i_1_0_361( + .A1(registers_31__ap[17]), .A2(n_1_0_637), .B1(n_1_0_616), .B2(registers_6__ap[17]), + .ZN(n_1_0_343) + ); + AOI22_X1_LVT i_1_0_357( + .A1(registers_14__ap[17]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[17]), + .ZN(n_1_0_339) + ); + AOI22_X1_LVT i_1_0_360( + .A1(registers_25__ap[17]), .A2(n_1_0_620), .B1(n_1_0_611), .B2(registers_11__ap[17]), + .ZN(n_1_0_342) + ); + INV_X1_LVT i_1_0_359( + .A(n_1_0_342), .ZN(n_1_0_341) + ); + AOI221_X1_LVT i_1_0_356( + .A(n_1_0_341), .B1(n_1_0_614), .B2(registers_16__ap[17]), .C1(registers_10__ap[17]), + .C2(n_1_0_624), .ZN(n_1_0_338) + ); + AOI222_X1_LVT i_1_0_355( + .A1(registers_1__ap[17]), .A2(n_1_0_644), .B1(n_1_0_622), .B2(registers_30__ap[17]), + .C1(registers_18__ap[17]), .C2(n_1_0_646), .ZN(n_1_0_337) + ); + NAND4_X1_LVT i_1_0_354( + .A1(n_1_0_343), .A2(n_1_0_339), .A3(n_1_0_338), .A4(n_1_0_337), .ZN(n_1_0_336) + ); + AOI221_X1_LVT i_1_0_353( + .A(n_1_0_336), .B1(n_1_0_649), .B2(registers_29__ap[17]), .C1(registers_2__ap[17]), + .C2(n_1_0_618), .ZN(n_1_0_335) + ); + AOI22_X1_LVT i_1_0_352( + .A1(registers_26__ap[17]), .A2(n_1_0_640), .B1(n_1_0_633), .B2(registers_19__ap[17]), + .ZN(n_1_0_334) + ); + AOI22_X1_LVT i_1_0_351( + .A1(registers_12__ap[17]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[17]), + .ZN(n_1_0_333) + ); + AOI22_X1_LVT i_1_0_350( + .A1(registers_22__ap[17]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[17]), + .ZN(n_1_0_332) + ); + NAND3_X1_LVT i_1_0_349( + .A1(n_1_0_334), .A2(n_1_0_333), .A3(n_1_0_332), .ZN(n_1_0_331) + ); + AOI221_X1_LVT i_1_0_348( + .A(n_1_0_331), .B1(n_1_0_635), .B2(registers_5__ap[17]), .C1(registers_20__ap[17]), + .C2(n_1_0_613), .ZN(n_1_0_330) + ); + AOI22_X1_LVT i_1_0_347( + .A1(registers_15__ap[17]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[17]), + .ZN(n_1_0_329) + ); + AOI22_X1_LVT i_1_0_346( + .A1(registers_8__ap[17]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[17]), + .ZN(n_1_0_328) + ); + AOI22_X1_LVT i_1_0_345( + .A1(registers_13__ap[17]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[17]), + .ZN(n_1_0_327) + ); + NAND3_X1_LVT i_1_0_344( + .A1(n_1_0_329), .A2(n_1_0_328), .A3(n_1_0_327), .ZN(n_1_0_326) + ); + AOI221_X1_LVT i_1_0_343( + .A(n_1_0_326), .B1(n_1_0_636), .B2(registers_27__ap[17]), .C1(registers_3__ap[17]), + .C2(n_1_0_610), .ZN(n_1_0_325) + ); + NAND4_X1_LVT i_1_0_342( + .A1(n_1_0_340), .A2(n_1_0_335), .A3(n_1_0_330), .A4(n_1_0_325), .ZN(RRs2[17]) + ); + AOI22_X1_LVT i_1_0_341( + .A1(registers_4__ap[16]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[16]), + .ZN(n_1_0_324) + ); + AOI222_X1_LVT i_1_0_340( + .A1(registers_1__ap[16]), .A2(n_1_0_644), .B1(n_1_0_633), .B2(registers_19__ap[16]), + .C1(n_1_0_622), .C2(registers_30__ap[16]), .ZN(n_1_0_323) + ); + AOI22_X1_LVT i_1_0_339( + .A1(registers_29__ap[16]), .A2(n_1_0_649), .B1(n_1_0_618), .B2(registers_2__ap[16]), + .ZN(n_1_0_322) + ); + AOI22_X1_LVT i_1_0_338( + .A1(registers_14__ap[16]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[16]), + .ZN(n_1_0_321) + ); + AOI22_X1_LVT i_1_0_337( + .A1(registers_16__ap[16]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[16]), + .ZN(n_1_0_320) + ); + AOI22_X1_LVT i_1_0_336( + .A1(registers_10__ap[16]), .A2(n_1_0_624), .B1(n_1_0_620), .B2(registers_25__ap[16]), + .ZN(n_1_0_319) + ); + AOI22_X1_LVT i_1_0_335( + .A1(registers_31__ap[16]), .A2(n_1_0_637), .B1(n_1_0_616), .B2(registers_6__ap[16]), + .ZN(n_1_0_318) + ); + NAND4_X1_LVT i_1_0_334( + .A1(n_1_0_321), .A2(n_1_0_320), .A3(n_1_0_319), .A4(n_1_0_318), .ZN(n_1_0_317) + ); + AOI22_X1_LVT i_1_0_333( + .A1(registers_18__ap[16]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[16]), + .ZN(n_1_0_316) + ); + AOI22_X1_LVT i_1_0_332( + .A1(registers_12__ap[16]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[16]), + .ZN(n_1_0_315) + ); + AOI22_X1_LVT i_1_0_331( + .A1(registers_22__ap[16]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[16]), + .ZN(n_1_0_314) + ); + AOI22_X1_LVT i_1_0_330( + .A1(registers_5__ap[16]), .A2(n_1_0_635), .B1(n_1_0_613), .B2(registers_20__ap[16]), + .ZN(n_1_0_313) + ); + NAND4_X1_LVT i_1_0_329( + .A1(n_1_0_316), .A2(n_1_0_315), .A3(n_1_0_314), .A4(n_1_0_313), .ZN(n_1_0_312) + ); + AOI22_X1_LVT i_1_0_328( + .A1(registers_15__ap[16]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[16]), + .ZN(n_1_0_311) + ); + AOI22_X1_LVT i_1_0_327( + .A1(registers_8__ap[16]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[16]), + .ZN(n_1_0_310) + ); + AOI22_X1_LVT i_1_0_326( + .A1(registers_13__ap[16]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[16]), + .ZN(n_1_0_309) + ); + AOI22_X1_LVT i_1_0_325( + .A1(registers_27__ap[16]), .A2(n_1_0_636), .B1(n_1_0_610), .B2(registers_3__ap[16]), + .ZN(n_1_0_308) + ); + NAND4_X1_LVT i_1_0_324( + .A1(n_1_0_311), .A2(n_1_0_310), .A3(n_1_0_309), .A4(n_1_0_308), .ZN(n_1_0_307) + ); + NOR3_X1_LVT i_1_0_323( + .A1(n_1_0_317), .A2(n_1_0_312), .A3(n_1_0_307), .ZN(n_1_0_306) + ); + NAND4_X1_LVT i_1_0_322( + .A1(n_1_0_324), .A2(n_1_0_323), .A3(n_1_0_322), .A4(n_1_0_306), .ZN(RRs2[16]) + ); + AOI22_X1_LVT i_1_0_320( + .A1(registers_5__ap[15]), .A2(n_1_0_635), .B1(n_1_0_634), .B2(registers_28__ap[15]), + .ZN(n_1_0_304) + ); + AOI22_X1_LVT i_1_0_321( + .A1(registers_8__ap[15]), .A2(n_1_0_626), .B1(n_1_0_620), .B2(registers_25__ap[15]), + .ZN(n_1_0_305) + ); + AOI22_X1_LVT i_1_0_319( + .A1(registers_14__ap[15]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[15]), + .ZN(n_1_0_303) + ); + AOI22_X1_LVT i_1_0_318( + .A1(registers_16__ap[15]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[15]), + .ZN(n_1_0_302) + ); + NAND3_X1_LVT i_1_0_317( + .A1(n_1_0_305), .A2(n_1_0_303), .A3(n_1_0_302), .ZN(n_1_0_301) + ); + AOI221_X1_LVT i_1_0_316( + .A(n_1_0_301), .B1(n_1_0_616), .B2(registers_6__ap[15]), .C1(registers_10__ap[15]), + .C2(n_1_0_624), .ZN(n_1_0_300) + ); + AOI222_X1_LVT i_1_0_315( + .A1(registers_1__ap[15]), .A2(n_1_0_644), .B1(n_1_0_640), .B2(registers_26__ap[15]), + .C1(n_1_0_622), .C2(registers_30__ap[15]), .ZN(n_1_0_299) + ); + NAND2_X1_LVT i_1_0_314( + .A1(n_1_0_300), .A2(n_1_0_299), .ZN(n_1_0_298) + ); + AOI221_X1_LVT i_1_0_313( + .A(n_1_0_298), .B1(n_1_0_649), .B2(registers_29__ap[15]), .C1(registers_2__ap[15]), + .C2(n_1_0_618), .ZN(n_1_0_297) + ); + AOI22_X1_LVT i_1_0_312( + .A1(registers_12__ap[15]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[15]), + .ZN(n_1_0_296) + ); + AOI22_X1_LVT i_1_0_311( + .A1(registers_22__ap[15]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[15]), + .ZN(n_1_0_295) + ); + AOI22_X1_LVT i_1_0_310( + .A1(registers_4__ap[15]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[15]), + .ZN(n_1_0_294) + ); + NAND3_X1_LVT i_1_0_309( + .A1(n_1_0_296), .A2(n_1_0_295), .A3(n_1_0_294), .ZN(n_1_0_293) + ); + AOI221_X1_LVT i_1_0_308( + .A(n_1_0_293), .B1(n_1_0_633), .B2(registers_19__ap[15]), .C1(registers_18__ap[15]), + .C2(n_1_0_646), .ZN(n_1_0_292) + ); + AOI22_X1_LVT i_1_0_307( + .A1(registers_15__ap[15]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[15]), + .ZN(n_1_0_291) + ); + AOI22_X1_LVT i_1_0_306( + .A1(registers_23__ap[15]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[15]), + .ZN(n_1_0_290) + ); + AOI22_X1_LVT i_1_0_305( + .A1(registers_13__ap[15]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[15]), + .ZN(n_1_0_289) + ); + NAND3_X1_LVT i_1_0_304( + .A1(n_1_0_291), .A2(n_1_0_290), .A3(n_1_0_289), .ZN(n_1_0_288) + ); + AOI221_X1_LVT i_1_0_303( + .A(n_1_0_288), .B1(n_1_0_636), .B2(registers_27__ap[15]), .C1(registers_31__ap[15]), + .C2(n_1_0_637), .ZN(n_1_0_287) + ); + NAND4_X1_LVT i_1_0_302( + .A1(n_1_0_304), .A2(n_1_0_297), .A3(n_1_0_292), .A4(n_1_0_287), .ZN(RRs2[15]) + ); + AOI22_X1_LVT i_1_0_301( + .A1(registers_28__ap[14]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[14]), + .ZN(n_1_0_286) + ); + AOI222_X1_LVT i_1_0_300( + .A1(registers_18__ap[14]), .A2(n_1_0_646), .B1(n_1_0_620), .B2(registers_25__ap[14]), + .C1(n_1_0_618), .C2(registers_2__ap[14]), .ZN(n_1_0_285) + ); + AOI22_X1_LVT i_1_0_299( + .A1(registers_24__ap[14]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[14]), + .ZN(n_1_0_284) + ); + AOI22_X1_LVT i_1_0_298( + .A1(registers_15__ap[14]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[14]), + .ZN(n_1_0_283) + ); + AOI22_X1_LVT i_1_0_297( + .A1(registers_4__ap[14]), .A2(n_1_0_638), .B1(n_1_0_637), .B2(registers_31__ap[14]), + .ZN(n_1_0_282) + ); + AOI22_X1_LVT i_1_0_296( + .A1(registers_29__ap[14]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[14]), + .ZN(n_1_0_281) + ); + NAND4_X1_LVT i_1_0_295( + .A1(n_1_0_284), .A2(n_1_0_283), .A3(n_1_0_282), .A4(n_1_0_281), .ZN(n_1_0_280) + ); + AOI221_X1_LVT i_1_0_294( + .A(n_1_0_280), .B1(n_1_0_644), .B2(registers_1__ap[14]), .C1(registers_13__ap[14]), + .C2(n_1_0_631), .ZN(n_1_0_279) + ); + AOI22_X1_LVT i_1_0_293( + .A1(registers_17__ap[14]), .A2(n_1_0_629), .B1(n_1_0_623), .B2(registers_7__ap[14]), + .ZN(n_1_0_278) + ); + AOI22_X1_LVT i_1_0_292( + .A1(registers_5__ap[14]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[14]), + .ZN(n_1_0_277) + ); + AOI22_X1_LVT i_1_0_291( + .A1(registers_10__ap[14]), .A2(n_1_0_624), .B1(n_1_0_622), .B2(registers_30__ap[14]), + .ZN(n_1_0_276) + ); + AOI22_X1_LVT i_1_0_290( + .A1(registers_26__ap[14]), .A2(n_1_0_640), .B1(n_1_0_614), .B2(registers_16__ap[14]), + .ZN(n_1_0_275) + ); + NAND4_X1_LVT i_1_0_289( + .A1(n_1_0_278), .A2(n_1_0_277), .A3(n_1_0_276), .A4(n_1_0_275), .ZN(n_1_0_274) + ); + AOI22_X1_LVT i_1_0_288( + .A1(registers_9__ap[14]), .A2(n_1_0_617), .B1(n_1_0_612), .B2(registers_21__ap[14]), + .ZN(n_1_0_273) + ); + AOI22_X1_LVT i_1_0_287( + .A1(registers_14__ap[14]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[14]), + .ZN(n_1_0_272) + ); + AOI22_X1_LVT i_1_0_286( + .A1(registers_22__ap[14]), .A2(n_1_0_642), .B1(n_1_0_633), .B2(registers_19__ap[14]), + .ZN(n_1_0_271) + ); + AOI22_X1_LVT i_1_0_285( + .A1(registers_27__ap[14]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[14]), + .ZN(n_1_0_270) + ); + NAND4_X1_LVT i_1_0_284( + .A1(n_1_0_273), .A2(n_1_0_272), .A3(n_1_0_271), .A4(n_1_0_270), .ZN(n_1_0_269) + ); + NOR2_X1_LVT i_1_0_283( + .A1(n_1_0_274), .A2(n_1_0_269), .ZN(n_1_0_268) + ); + NAND4_X1_LVT i_1_0_282( + .A1(n_1_0_286), .A2(n_1_0_285), .A3(n_1_0_279), .A4(n_1_0_268), .ZN(RRs2[14]) + ); + AOI22_X1_LVT i_1_0_281( + .A1(registers_18__ap[13]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[13]), + .ZN(n_1_0_267) + ); + AOI22_X1_LVT i_1_0_280( + .A1(registers_12__ap[13]), .A2(n_1_0_632), .B1(n_1_0_629), .B2(registers_17__ap[13]), + .ZN(n_1_0_266) + ); + AOI22_X1_LVT i_1_0_279( + .A1(registers_7__ap[13]), .A2(n_1_0_623), .B1(n_1_0_614), .B2(registers_16__ap[13]), + .ZN(n_1_0_265) + ); + NAND3_X1_LVT i_1_0_277( + .A1(n_1_0_267), .A2(n_1_0_266), .A3(n_1_0_265), .ZN(n_1_0_263) + ); + AOI221_X1_LVT i_1_0_276( + .A(n_1_0_263), .B1(n_1_0_642), .B2(registers_22__ap[13]), .C1(registers_5__ap[13]), + .C2(n_1_0_635), .ZN(n_1_0_262) + ); + AOI22_X1_LVT i_1_0_278( + .A1(registers_13__ap[13]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[13]), + .ZN(n_1_0_264) + ); + AOI222_X1_LVT i_1_0_275( + .A1(registers_26__ap[13]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[13]), + .C1(n_1_0_620), .C2(registers_25__ap[13]), .ZN(n_1_0_261) + ); + AOI22_X1_LVT i_1_0_274( + .A1(registers_28__ap[13]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[13]), + .ZN(n_1_0_260) + ); + NAND3_X1_LVT i_1_0_273( + .A1(n_1_0_264), .A2(n_1_0_261), .A3(n_1_0_260), .ZN(n_1_0_259) + ); + AOI22_X1_LVT i_1_0_272( + .A1(registers_1__ap[13]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[13]), + .ZN(n_1_0_258) + ); + AOI22_X1_LVT i_1_0_271( + .A1(registers_19__ap[13]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[13]), + .ZN(n_1_0_257) + ); + AOI22_X1_LVT i_1_0_270( + .A1(registers_14__ap[13]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[13]), + .ZN(n_1_0_256) + ); + AOI22_X1_LVT i_1_0_269( + .A1(registers_27__ap[13]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[13]), + .ZN(n_1_0_255) + ); + NAND4_X1_LVT i_1_0_268( + .A1(n_1_0_258), .A2(n_1_0_257), .A3(n_1_0_256), .A4(n_1_0_255), .ZN(n_1_0_254) + ); + AOI22_X1_LVT i_1_0_267( + .A1(registers_24__ap[13]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[13]), + .ZN(n_1_0_253) + ); + AOI22_X1_LVT i_1_0_266( + .A1(registers_4__ap[13]), .A2(n_1_0_638), .B1(n_1_0_637), .B2(registers_31__ap[13]), + .ZN(n_1_0_252) + ); + AOI22_X1_LVT i_1_0_265( + .A1(registers_29__ap[13]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[13]), + .ZN(n_1_0_251) + ); + AOI22_X1_LVT i_1_0_264( + .A1(registers_15__ap[13]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[13]), + .ZN(n_1_0_250) + ); + NAND4_X1_LVT i_1_0_263( + .A1(n_1_0_253), .A2(n_1_0_252), .A3(n_1_0_251), .A4(n_1_0_250), .ZN(n_1_0_249) + ); + NOR3_X1_LVT i_1_0_262( + .A1(n_1_0_259), .A2(n_1_0_254), .A3(n_1_0_249), .ZN(n_1_0_248) + ); + NAND2_X1_LVT i_1_0_261( + .A1(n_1_0_262), .A2(n_1_0_248), .ZN(RRs2[13]) + ); + AOI22_X1_LVT i_1_0_260( + .A1(registers_18__ap[12]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[12]), + .ZN(n_1_0_247) + ); + AOI22_X1_LVT i_1_0_259( + .A1(registers_12__ap[12]), .A2(n_1_0_632), .B1(n_1_0_629), .B2(registers_17__ap[12]), + .ZN(n_1_0_246) + ); + AOI22_X1_LVT i_1_0_258( + .A1(registers_5__ap[12]), .A2(n_1_0_635), .B1(n_1_0_623), .B2(registers_7__ap[12]), + .ZN(n_1_0_245) + ); + NAND3_X1_LVT i_1_0_256( + .A1(n_1_0_247), .A2(n_1_0_246), .A3(n_1_0_245), .ZN(n_1_0_243) + ); + AOI221_X1_LVT i_1_0_255( + .A(n_1_0_243), .B1(n_1_0_642), .B2(registers_22__ap[12]), .C1(registers_16__ap[12]), + .C2(n_1_0_614), .ZN(n_1_0_242) + ); + AOI22_X1_LVT i_1_0_257( + .A1(registers_13__ap[12]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[12]), + .ZN(n_1_0_244) + ); + AOI222_X1_LVT i_1_0_254( + .A1(registers_26__ap[12]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[12]), + .C1(n_1_0_620), .C2(registers_25__ap[12]), .ZN(n_1_0_241) + ); + AOI22_X1_LVT i_1_0_253( + .A1(registers_28__ap[12]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[12]), + .ZN(n_1_0_240) + ); + NAND3_X1_LVT i_1_0_252( + .A1(n_1_0_244), .A2(n_1_0_241), .A3(n_1_0_240), .ZN(n_1_0_239) + ); + AOI22_X1_LVT i_1_0_251( + .A1(registers_1__ap[12]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[12]), + .ZN(n_1_0_238) + ); + AOI22_X1_LVT i_1_0_250( + .A1(registers_19__ap[12]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[12]), + .ZN(n_1_0_237) + ); + AOI22_X1_LVT i_1_0_249( + .A1(registers_14__ap[12]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[12]), + .ZN(n_1_0_236) + ); + AOI22_X1_LVT i_1_0_248( + .A1(registers_27__ap[12]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[12]), + .ZN(n_1_0_235) + ); + NAND4_X1_LVT i_1_0_247( + .A1(n_1_0_238), .A2(n_1_0_237), .A3(n_1_0_236), .A4(n_1_0_235), .ZN(n_1_0_234) + ); + AOI22_X1_LVT i_1_0_246( + .A1(registers_24__ap[12]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[12]), + .ZN(n_1_0_233) + ); + AOI22_X1_LVT i_1_0_245( + .A1(registers_4__ap[12]), .A2(n_1_0_638), .B1(n_1_0_637), .B2(registers_31__ap[12]), + .ZN(n_1_0_232) + ); + AOI22_X1_LVT i_1_0_244( + .A1(registers_29__ap[12]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[12]), + .ZN(n_1_0_231) + ); + AOI22_X1_LVT i_1_0_243( + .A1(registers_15__ap[12]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[12]), + .ZN(n_1_0_230) + ); + NAND4_X1_LVT i_1_0_242( + .A1(n_1_0_233), .A2(n_1_0_232), .A3(n_1_0_231), .A4(n_1_0_230), .ZN(n_1_0_229) + ); + NOR3_X1_LVT i_1_0_241( + .A1(n_1_0_239), .A2(n_1_0_234), .A3(n_1_0_229), .ZN(n_1_0_228) + ); + NAND2_X1_LVT i_1_0_240( + .A1(n_1_0_242), .A2(n_1_0_228), .ZN(RRs2[12]) + ); + AOI22_X1_LVT i_1_0_238( + .A1(registers_29__ap[11]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[11]), + .ZN(n_1_0_226) + ); + AOI22_X1_LVT i_1_0_239( + .A1(registers_27__ap[11]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[11]), + .ZN(n_1_0_227) + ); + AOI22_X1_LVT i_1_0_237( + .A1(registers_1__ap[11]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[11]), + .ZN(n_1_0_225) + ); + AOI22_X1_LVT i_1_0_236( + .A1(registers_5__ap[11]), .A2(n_1_0_635), .B1(n_1_0_615), .B2(registers_23__ap[11]), + .ZN(n_1_0_224) + ); + NAND3_X1_LVT i_1_0_235( + .A1(n_1_0_227), .A2(n_1_0_225), .A3(n_1_0_224), .ZN(n_1_0_223) + ); + AOI221_X1_LVT i_1_0_234( + .A(n_1_0_223), .B1(n_1_0_637), .B2(registers_31__ap[11]), .C1(registers_16__ap[11]), + .C2(n_1_0_614), .ZN(n_1_0_222) + ); + AOI222_X1_LVT i_1_0_233( + .A1(registers_8__ap[11]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[11]), + .C1(n_1_0_622), .C2(registers_30__ap[11]), .ZN(n_1_0_221) + ); + NAND3_X1_LVT i_1_0_232( + .A1(n_1_0_226), .A2(n_1_0_222), .A3(n_1_0_221), .ZN(n_1_0_220) + ); + AOI221_X1_LVT i_1_0_231( + .A(n_1_0_220), .B1(n_1_0_638), .B2(registers_4__ap[11]), .C1(registers_28__ap[11]), + .C2(n_1_0_634), .ZN(n_1_0_219) + ); + AOI22_X1_LVT i_1_0_230( + .A1(registers_18__ap[11]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[11]), + .ZN(n_1_0_218) + ); + AOI22_X1_LVT i_1_0_229( + .A1(registers_12__ap[11]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[11]), + .ZN(n_1_0_217) + ); + AOI22_X1_LVT i_1_0_228( + .A1(registers_22__ap[11]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[11]), + .ZN(n_1_0_216) + ); + NAND3_X1_LVT i_1_0_227( + .A1(n_1_0_218), .A2(n_1_0_217), .A3(n_1_0_216), .ZN(n_1_0_215) + ); + AOI221_X1_LVT i_1_0_226( + .A(n_1_0_215), .B1(n_1_0_613), .B2(registers_20__ap[11]), .C1(registers_17__ap[11]), + .C2(n_1_0_629), .ZN(n_1_0_214) + ); + AOI22_X1_LVT i_1_0_225( + .A1(registers_13__ap[11]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[11]), + .ZN(n_1_0_213) + ); + AOI22_X1_LVT i_1_0_224( + .A1(registers_7__ap[11]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[11]), + .ZN(n_1_0_212) + ); + AOI22_X1_LVT i_1_0_223( + .A1(registers_19__ap[11]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[11]), + .ZN(n_1_0_211) + ); + NAND3_X1_LVT i_1_0_222( + .A1(n_1_0_213), .A2(n_1_0_212), .A3(n_1_0_211), .ZN(n_1_0_210) + ); + AOI221_X1_LVT i_1_0_221( + .A(n_1_0_210), .B1(n_1_0_611), .B2(registers_11__ap[11]), .C1(registers_2__ap[11]), + .C2(n_1_0_618), .ZN(n_1_0_209) + ); + NAND3_X1_LVT i_1_0_220( + .A1(n_1_0_219), .A2(n_1_0_214), .A3(n_1_0_209), .ZN(RRs2[11]) + ); + AOI22_X1_LVT i_1_0_219( + .A1(registers_28__ap[10]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[10]), + .ZN(n_1_0_208) + ); + AOI222_X1_LVT i_1_0_218( + .A1(registers_26__ap[10]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[10]), + .C1(registers_25__ap[10]), .C2(n_1_0_620), .ZN(n_1_0_207) + ); + AOI22_X1_LVT i_1_0_217( + .A1(registers_13__ap[10]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[10]), + .ZN(n_1_0_206) + ); + AOI22_X1_LVT i_1_0_216( + .A1(registers_24__ap[10]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[10]), + .ZN(n_1_0_205) + ); + AOI22_X1_LVT i_1_0_215( + .A1(registers_15__ap[10]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[10]), + .ZN(n_1_0_204) + ); + AOI22_X1_LVT i_1_0_214( + .A1(registers_31__ap[10]), .A2(n_1_0_637), .B1(n_1_0_629), .B2(registers_17__ap[10]), + .ZN(n_1_0_203) + ); + AOI22_X1_LVT i_1_0_213( + .A1(registers_29__ap[10]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[10]), + .ZN(n_1_0_202) + ); + NAND4_X1_LVT i_1_0_212( + .A1(n_1_0_205), .A2(n_1_0_204), .A3(n_1_0_203), .A4(n_1_0_202), .ZN(n_1_0_201) + ); + AOI22_X1_LVT i_1_0_211( + .A1(registers_18__ap[10]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[10]), + .ZN(n_1_0_200) + ); + AOI22_X1_LVT i_1_0_210( + .A1(registers_4__ap[10]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[10]), + .ZN(n_1_0_199) + ); + AOI22_X1_LVT i_1_0_209( + .A1(registers_7__ap[10]), .A2(n_1_0_623), .B1(n_1_0_614), .B2(registers_16__ap[10]), + .ZN(n_1_0_198) + ); + AOI22_X1_LVT i_1_0_208( + .A1(registers_22__ap[10]), .A2(n_1_0_642), .B1(n_1_0_635), .B2(registers_5__ap[10]), + .ZN(n_1_0_197) + ); + NAND4_X1_LVT i_1_0_207( + .A1(n_1_0_200), .A2(n_1_0_199), .A3(n_1_0_198), .A4(n_1_0_197), .ZN(n_1_0_196) + ); + AOI22_X1_LVT i_1_0_206( + .A1(registers_1__ap[10]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[10]), + .ZN(n_1_0_195) + ); + AOI22_X1_LVT i_1_0_205( + .A1(registers_14__ap[10]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[10]), + .ZN(n_1_0_194) + ); + AOI22_X1_LVT i_1_0_204( + .A1(registers_19__ap[10]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[10]), + .ZN(n_1_0_193) + ); + AOI22_X1_LVT i_1_0_203( + .A1(registers_27__ap[10]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[10]), + .ZN(n_1_0_192) + ); + NAND4_X1_LVT i_1_0_202( + .A1(n_1_0_195), .A2(n_1_0_194), .A3(n_1_0_193), .A4(n_1_0_192), .ZN(n_1_0_191) + ); + NOR3_X1_LVT i_1_0_201( + .A1(n_1_0_201), .A2(n_1_0_196), .A3(n_1_0_191), .ZN(n_1_0_190) + ); + NAND4_X1_LVT i_1_0_200( + .A1(n_1_0_208), .A2(n_1_0_207), .A3(n_1_0_206), .A4(n_1_0_190), .ZN(RRs2[10]) + ); + AOI22_X1_LVT i_1_0_196( + .A1(registers_13__ap[9]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[9]), + .ZN(n_1_0_186) + ); + AOI22_X1_LVT i_1_0_199( + .A1(registers_29__ap[9]), .A2(n_1_0_649), .B1(n_1_0_636), .B2(registers_27__ap[9]), + .ZN(n_1_0_189) + ); + AOI22_X1_LVT i_1_0_195( + .A1(registers_24__ap[9]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[9]), + .ZN(n_1_0_185) + ); + AOI22_X1_LVT i_1_0_198( + .A1(registers_31__ap[9]), .A2(n_1_0_637), .B1(n_1_0_627), .B2(registers_15__ap[9]), + .ZN(n_1_0_188) + ); + INV_X1_LVT i_1_0_197( + .A(n_1_0_188), .ZN(n_1_0_187) + ); + AOI221_X1_LVT i_1_0_194( + .A(n_1_0_187), .B1(n_1_0_615), .B2(registers_23__ap[9]), .C1(registers_4__ap[9]), + .C2(n_1_0_638), .ZN(n_1_0_184) + ); + AOI222_X1_LVT i_1_0_193( + .A1(registers_18__ap[9]), .A2(n_1_0_646), .B1(n_1_0_624), .B2(registers_10__ap[9]), + .C1(registers_25__ap[9]), .C2(n_1_0_620), .ZN(n_1_0_183) + ); + NAND4_X1_LVT i_1_0_192( + .A1(n_1_0_189), .A2(n_1_0_185), .A3(n_1_0_184), .A4(n_1_0_183), .ZN(n_1_0_182) + ); + AOI221_X1_LVT i_1_0_191( + .A(n_1_0_182), .B1(n_1_0_626), .B2(registers_8__ap[9]), .C1(registers_28__ap[9]), + .C2(n_1_0_634), .ZN(n_1_0_181) + ); + AOI22_X1_LVT i_1_0_190( + .A1(registers_26__ap[9]), .A2(n_1_0_640), .B1(n_1_0_622), .B2(registers_30__ap[9]), + .ZN(n_1_0_180) + ); + AOI22_X1_LVT i_1_0_189( + .A1(registers_12__ap[9]), .A2(n_1_0_632), .B1(n_1_0_629), .B2(registers_17__ap[9]), + .ZN(n_1_0_179) + ); + AOI22_X1_LVT i_1_0_188( + .A1(registers_5__ap[9]), .A2(n_1_0_635), .B1(n_1_0_623), .B2(registers_7__ap[9]), + .ZN(n_1_0_178) + ); + NAND3_X1_LVT i_1_0_187( + .A1(n_1_0_180), .A2(n_1_0_179), .A3(n_1_0_178), .ZN(n_1_0_177) + ); + AOI221_X1_LVT i_1_0_186( + .A(n_1_0_177), .B1(n_1_0_642), .B2(registers_22__ap[9]), .C1(registers_16__ap[9]), + .C2(n_1_0_614), .ZN(n_1_0_176) + ); + AOI22_X1_LVT i_1_0_185( + .A1(registers_1__ap[9]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[9]), + .ZN(n_1_0_175) + ); + AOI22_X1_LVT i_1_0_184( + .A1(registers_14__ap[9]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[9]), + .ZN(n_1_0_174) + ); + AOI22_X1_LVT i_1_0_183( + .A1(registers_19__ap[9]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[9]), + .ZN(n_1_0_173) + ); + NAND3_X1_LVT i_1_0_182( + .A1(n_1_0_175), .A2(n_1_0_174), .A3(n_1_0_173), .ZN(n_1_0_172) + ); + AOI221_X1_LVT i_1_0_181( + .A(n_1_0_172), .B1(n_1_0_611), .B2(registers_11__ap[9]), .C1(registers_2__ap[9]), + .C2(n_1_0_618), .ZN(n_1_0_171) + ); + NAND4_X1_LVT i_1_0_180( + .A1(n_1_0_186), .A2(n_1_0_181), .A3(n_1_0_176), .A4(n_1_0_171), .ZN(RRs2[9]) + ); + AOI22_X1_LVT i_1_0_179( + .A1(registers_28__ap[8]), .A2(n_1_0_634), .B1(n_1_0_629), .B2(registers_17__ap[8]), + .ZN(n_1_0_170) + ); + AOI222_X1_LVT i_1_0_178( + .A1(registers_26__ap[8]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[8]), + .C1(n_1_0_626), .C2(registers_8__ap[8]), .ZN(n_1_0_169) + ); + AOI22_X1_LVT i_1_0_177( + .A1(registers_29__ap[8]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[8]), + .ZN(n_1_0_168) + ); + AOI22_X1_LVT i_1_0_176( + .A1(registers_1__ap[8]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[8]), + .ZN(n_1_0_167) + ); + AOI22_X1_LVT i_1_0_175( + .A1(registers_5__ap[8]), .A2(n_1_0_635), .B1(n_1_0_610), .B2(registers_3__ap[8]), + .ZN(n_1_0_166) + ); + AOI22_X1_LVT i_1_0_174( + .A1(registers_31__ap[8]), .A2(n_1_0_637), .B1(n_1_0_614), .B2(registers_16__ap[8]), + .ZN(n_1_0_165) + ); + AOI22_X1_LVT i_1_0_173( + .A1(registers_15__ap[8]), .A2(n_1_0_627), .B1(n_1_0_615), .B2(registers_23__ap[8]), + .ZN(n_1_0_164) + ); + NAND4_X1_LVT i_1_0_172( + .A1(n_1_0_167), .A2(n_1_0_166), .A3(n_1_0_165), .A4(n_1_0_164), .ZN(n_1_0_163) + ); + AOI22_X1_LVT i_1_0_171( + .A1(registers_18__ap[8]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[8]), + .ZN(n_1_0_162) + ); + AOI22_X1_LVT i_1_0_170( + .A1(registers_4__ap[8]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[8]), + .ZN(n_1_0_161) + ); + AOI22_X1_LVT i_1_0_169( + .A1(registers_22__ap[8]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[8]), + .ZN(n_1_0_160) + ); + AOI22_X1_LVT i_1_0_168( + .A1(registers_12__ap[8]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[8]), + .ZN(n_1_0_159) + ); + NAND4_X1_LVT i_1_0_167( + .A1(n_1_0_162), .A2(n_1_0_161), .A3(n_1_0_160), .A4(n_1_0_159), .ZN(n_1_0_158) + ); + AOI22_X1_LVT i_1_0_166( + .A1(registers_13__ap[8]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[8]), + .ZN(n_1_0_157) + ); + AOI22_X1_LVT i_1_0_165( + .A1(registers_7__ap[8]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[8]), + .ZN(n_1_0_156) + ); + AOI22_X1_LVT i_1_0_164( + .A1(registers_19__ap[8]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[8]), + .ZN(n_1_0_155) + ); + AOI22_X1_LVT i_1_0_163( + .A1(registers_27__ap[8]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[8]), + .ZN(n_1_0_154) + ); + NAND4_X1_LVT i_1_0_162( + .A1(n_1_0_157), .A2(n_1_0_156), .A3(n_1_0_155), .A4(n_1_0_154), .ZN(n_1_0_153) + ); + NOR3_X1_LVT i_1_0_161( + .A1(n_1_0_163), .A2(n_1_0_158), .A3(n_1_0_153), .ZN(n_1_0_152) + ); + NAND4_X1_LVT i_1_0_160( + .A1(n_1_0_170), .A2(n_1_0_169), .A3(n_1_0_168), .A4(n_1_0_152), .ZN(RRs2[8]) + ); + AOI22_X1_LVT i_1_0_159( + .A1(registers_28__ap[7]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[7]), + .ZN(n_1_0_151) + ); + AOI222_X1_LVT i_1_0_158( + .A1(registers_26__ap[7]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[7]), + .C1(registers_25__ap[7]), .C2(n_1_0_620), .ZN(n_1_0_150) + ); + AOI22_X1_LVT i_1_0_157( + .A1(registers_24__ap[7]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[7]), + .ZN(n_1_0_149) + ); + AOI22_X1_LVT i_1_0_156( + .A1(registers_15__ap[7]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[7]), + .ZN(n_1_0_148) + ); + AOI22_X1_LVT i_1_0_155( + .A1(registers_31__ap[7]), .A2(n_1_0_637), .B1(n_1_0_629), .B2(registers_17__ap[7]), + .ZN(n_1_0_147) + ); + AOI22_X1_LVT i_1_0_154( + .A1(registers_29__ap[7]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[7]), + .ZN(n_1_0_146) + ); + NAND4_X1_LVT i_1_0_153( + .A1(n_1_0_149), .A2(n_1_0_148), .A3(n_1_0_147), .A4(n_1_0_146), .ZN(n_1_0_145) + ); + AOI221_X1_LVT i_1_0_152( + .A(n_1_0_145), .B1(n_1_0_612), .B2(registers_21__ap[7]), .C1(registers_13__ap[7]), + .C2(n_1_0_631), .ZN(n_1_0_144) + ); + AOI22_X1_LVT i_1_0_151( + .A1(registers_18__ap[7]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[7]), + .ZN(n_1_0_143) + ); + AOI22_X1_LVT i_1_0_150( + .A1(registers_4__ap[7]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[7]), + .ZN(n_1_0_142) + ); + AOI22_X1_LVT i_1_0_149( + .A1(registers_5__ap[7]), .A2(n_1_0_635), .B1(n_1_0_623), .B2(registers_7__ap[7]), + .ZN(n_1_0_141) + ); + AOI22_X1_LVT i_1_0_148( + .A1(registers_22__ap[7]), .A2(n_1_0_642), .B1(n_1_0_614), .B2(registers_16__ap[7]), + .ZN(n_1_0_140) + ); + NAND4_X1_LVT i_1_0_147( + .A1(n_1_0_143), .A2(n_1_0_142), .A3(n_1_0_141), .A4(n_1_0_140), .ZN(n_1_0_139) + ); + AOI22_X1_LVT i_1_0_146( + .A1(registers_1__ap[7]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[7]), + .ZN(n_1_0_138) + ); + AOI22_X1_LVT i_1_0_145( + .A1(registers_14__ap[7]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[7]), + .ZN(n_1_0_137) + ); + AOI22_X1_LVT i_1_0_144( + .A1(registers_19__ap[7]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[7]), + .ZN(n_1_0_136) + ); + AOI22_X1_LVT i_1_0_143( + .A1(registers_27__ap[7]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[7]), + .ZN(n_1_0_135) + ); + NAND4_X1_LVT i_1_0_142( + .A1(n_1_0_138), .A2(n_1_0_137), .A3(n_1_0_136), .A4(n_1_0_135), .ZN(n_1_0_134) + ); + NOR2_X1_LVT i_1_0_141( + .A1(n_1_0_139), .A2(n_1_0_134), .ZN(n_1_0_133) + ); + NAND4_X1_LVT i_1_0_140( + .A1(n_1_0_151), .A2(n_1_0_150), .A3(n_1_0_144), .A4(n_1_0_133), .ZN(RRs2[7]) + ); + AOI22_X1_LVT i_1_0_136( + .A1(registers_13__ap[6]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[6]), + .ZN(n_1_0_129) + ); + AOI22_X1_LVT i_1_0_139( + .A1(registers_29__ap[6]), .A2(n_1_0_649), .B1(n_1_0_636), .B2(registers_27__ap[6]), + .ZN(n_1_0_132) + ); + AOI22_X1_LVT i_1_0_135( + .A1(registers_24__ap[6]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[6]), + .ZN(n_1_0_128) + ); + AOI22_X1_LVT i_1_0_138( + .A1(registers_31__ap[6]), .A2(n_1_0_637), .B1(n_1_0_627), .B2(registers_15__ap[6]), + .ZN(n_1_0_131) + ); + INV_X1_LVT i_1_0_137( + .A(n_1_0_131), .ZN(n_1_0_130) + ); + AOI221_X1_LVT i_1_0_134( + .A(n_1_0_130), .B1(n_1_0_638), .B2(registers_4__ap[6]), .C1(registers_23__ap[6]), + .C2(n_1_0_615), .ZN(n_1_0_127) + ); + AOI222_X1_LVT i_1_0_133( + .A1(registers_18__ap[6]), .A2(n_1_0_646), .B1(n_1_0_620), .B2(registers_25__ap[6]), + .C1(n_1_0_624), .C2(registers_10__ap[6]), .ZN(n_1_0_126) + ); + NAND4_X1_LVT i_1_0_132( + .A1(n_1_0_132), .A2(n_1_0_128), .A3(n_1_0_127), .A4(n_1_0_126), .ZN(n_1_0_125) + ); + AOI221_X1_LVT i_1_0_131( + .A(n_1_0_125), .B1(n_1_0_626), .B2(registers_8__ap[6]), .C1(registers_28__ap[6]), + .C2(n_1_0_634), .ZN(n_1_0_124) + ); + AOI22_X1_LVT i_1_0_130( + .A1(registers_26__ap[6]), .A2(n_1_0_640), .B1(n_1_0_622), .B2(registers_30__ap[6]), + .ZN(n_1_0_123) + ); + AOI22_X1_LVT i_1_0_129( + .A1(registers_12__ap[6]), .A2(n_1_0_632), .B1(n_1_0_629), .B2(registers_17__ap[6]), + .ZN(n_1_0_122) + ); + AOI22_X1_LVT i_1_0_128( + .A1(registers_7__ap[6]), .A2(n_1_0_623), .B1(n_1_0_614), .B2(registers_16__ap[6]), + .ZN(n_1_0_121) + ); + NAND3_X1_LVT i_1_0_127( + .A1(n_1_0_123), .A2(n_1_0_122), .A3(n_1_0_121), .ZN(n_1_0_120) + ); + AOI221_X1_LVT i_1_0_126( + .A(n_1_0_120), .B1(n_1_0_642), .B2(registers_22__ap[6]), .C1(registers_5__ap[6]), + .C2(n_1_0_635), .ZN(n_1_0_119) + ); + AOI22_X1_LVT i_1_0_125( + .A1(registers_1__ap[6]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[6]), + .ZN(n_1_0_118) + ); + AOI22_X1_LVT i_1_0_124( + .A1(registers_14__ap[6]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[6]), + .ZN(n_1_0_117) + ); + AOI22_X1_LVT i_1_0_123( + .A1(registers_19__ap[6]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[6]), + .ZN(n_1_0_116) + ); + NAND3_X1_LVT i_1_0_122( + .A1(n_1_0_118), .A2(n_1_0_117), .A3(n_1_0_116), .ZN(n_1_0_115) + ); + AOI221_X1_LVT i_1_0_121( + .A(n_1_0_115), .B1(n_1_0_618), .B2(registers_2__ap[6]), .C1(registers_11__ap[6]), + .C2(n_1_0_611), .ZN(n_1_0_114) + ); + NAND4_X1_LVT i_1_0_120( + .A1(n_1_0_129), .A2(n_1_0_124), .A3(n_1_0_119), .A4(n_1_0_114), .ZN(RRs2[6]) + ); + AOI22_X1_LVT i_1_0_118( + .A1(registers_28__ap[5]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[5]), + .ZN(n_1_0_112) + ); + AOI22_X1_LVT i_1_0_119( + .A1(registers_31__ap[5]), .A2(n_1_0_637), .B1(n_1_0_627), .B2(registers_15__ap[5]), + .ZN(n_1_0_113) + ); + AOI22_X1_LVT i_1_0_117( + .A1(registers_24__ap[5]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[5]), + .ZN(n_1_0_111) + ); + AOI22_X1_LVT i_1_0_116( + .A1(registers_17__ap[5]), .A2(n_1_0_629), .B1(n_1_0_615), .B2(registers_23__ap[5]), + .ZN(n_1_0_110) + ); + NAND3_X1_LVT i_1_0_115( + .A1(n_1_0_113), .A2(n_1_0_111), .A3(n_1_0_110), .ZN(n_1_0_109) + ); + AOI221_X1_LVT i_1_0_114( + .A(n_1_0_109), .B1(n_1_0_636), .B2(registers_27__ap[5]), .C1(registers_29__ap[5]), + .C2(n_1_0_649), .ZN(n_1_0_108) + ); + AOI222_X1_LVT i_1_0_113( + .A1(registers_10__ap[5]), .A2(n_1_0_624), .B1(n_1_0_620), .B2(registers_25__ap[5]), + .C1(registers_18__ap[5]), .C2(n_1_0_646), .ZN(n_1_0_107) + ); + NAND3_X1_LVT i_1_0_112( + .A1(n_1_0_112), .A2(n_1_0_108), .A3(n_1_0_107), .ZN(n_1_0_106) + ); + AOI221_X1_LVT i_1_0_111( + .A(n_1_0_106), .B1(n_1_0_612), .B2(registers_21__ap[5]), .C1(registers_13__ap[5]), + .C2(n_1_0_631), .ZN(n_1_0_105) + ); + AOI22_X1_LVT i_1_0_110( + .A1(registers_26__ap[5]), .A2(n_1_0_640), .B1(n_1_0_622), .B2(registers_30__ap[5]), + .ZN(n_1_0_104) + ); + AOI22_X1_LVT i_1_0_109( + .A1(registers_4__ap[5]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[5]), + .ZN(n_1_0_103) + ); + AOI22_X1_LVT i_1_0_108( + .A1(registers_5__ap[5]), .A2(n_1_0_635), .B1(n_1_0_623), .B2(registers_7__ap[5]), + .ZN(n_1_0_102) + ); + NAND3_X1_LVT i_1_0_107( + .A1(n_1_0_104), .A2(n_1_0_103), .A3(n_1_0_102), .ZN(n_1_0_101) + ); + AOI221_X1_LVT i_1_0_106( + .A(n_1_0_101), .B1(n_1_0_642), .B2(registers_22__ap[5]), .C1(registers_16__ap[5]), + .C2(n_1_0_614), .ZN(n_1_0_100) + ); + AOI22_X1_LVT i_1_0_105( + .A1(registers_1__ap[5]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[5]), + .ZN(n_1_0_99) + ); + AOI22_X1_LVT i_1_0_104( + .A1(registers_14__ap[5]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[5]), + .ZN(n_1_0_98) + ); + AOI22_X1_LVT i_1_0_103( + .A1(registers_19__ap[5]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[5]), + .ZN(n_1_0_97) + ); + NAND3_X1_LVT i_1_0_102( + .A1(n_1_0_99), .A2(n_1_0_98), .A3(n_1_0_97), .ZN(n_1_0_96) + ); + AOI221_X1_LVT i_1_0_101( + .A(n_1_0_96), .B1(n_1_0_611), .B2(registers_11__ap[5]), .C1(registers_2__ap[5]), + .C2(n_1_0_618), .ZN(n_1_0_95) + ); + NAND3_X1_LVT i_1_0_100( + .A1(n_1_0_105), .A2(n_1_0_100), .A3(n_1_0_95), .ZN(RRs2[5]) + ); + AOI22_X1_LVT i_1_0_99( + .A1(registers_4__ap[4]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[4]), + .ZN(n_1_0_94) + ); + AOI222_X1_LVT i_1_0_98( + .A1(registers_8__ap[4]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[4]), + .C1(n_1_0_622), .C2(registers_30__ap[4]), .ZN(n_1_0_93) + ); + AOI22_X1_LVT i_1_0_97( + .A1(registers_29__ap[4]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[4]), + .ZN(n_1_0_92) + ); + AOI22_X1_LVT i_1_0_96( + .A1(registers_1__ap[4]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[4]), + .ZN(n_1_0_91) + ); + AOI22_X1_LVT i_1_0_95( + .A1(registers_27__ap[4]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[4]), + .ZN(n_1_0_90) + ); + AOI22_X1_LVT i_1_0_94( + .A1(registers_23__ap[4]), .A2(n_1_0_615), .B1(n_1_0_614), .B2(registers_16__ap[4]), + .ZN(n_1_0_89) + ); + AOI22_X1_LVT i_1_0_93( + .A1(registers_31__ap[4]), .A2(n_1_0_637), .B1(n_1_0_635), .B2(registers_5__ap[4]), + .ZN(n_1_0_88) + ); + NAND4_X1_LVT i_1_0_92( + .A1(n_1_0_91), .A2(n_1_0_90), .A3(n_1_0_89), .A4(n_1_0_88), .ZN(n_1_0_87) + ); + AOI22_X1_LVT i_1_0_91( + .A1(registers_18__ap[4]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[4]), + .ZN(n_1_0_86) + ); + AOI22_X1_LVT i_1_0_90( + .A1(registers_12__ap[4]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[4]), + .ZN(n_1_0_85) + ); + AOI22_X1_LVT i_1_0_89( + .A1(registers_22__ap[4]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[4]), + .ZN(n_1_0_84) + ); + AOI22_X1_LVT i_1_0_88( + .A1(registers_17__ap[4]), .A2(n_1_0_629), .B1(n_1_0_613), .B2(registers_20__ap[4]), + .ZN(n_1_0_83) + ); + NAND4_X1_LVT i_1_0_87( + .A1(n_1_0_86), .A2(n_1_0_85), .A3(n_1_0_84), .A4(n_1_0_83), .ZN(n_1_0_82) + ); + AOI22_X1_LVT i_1_0_86( + .A1(registers_13__ap[4]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[4]), + .ZN(n_1_0_81) + ); + AOI22_X1_LVT i_1_0_85( + .A1(registers_7__ap[4]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[4]), + .ZN(n_1_0_80) + ); + AOI22_X1_LVT i_1_0_84( + .A1(registers_19__ap[4]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[4]), + .ZN(n_1_0_79) + ); + AOI22_X1_LVT i_1_0_83( + .A1(registers_2__ap[4]), .A2(n_1_0_618), .B1(n_1_0_611), .B2(registers_11__ap[4]), + .ZN(n_1_0_78) + ); + NAND4_X1_LVT i_1_0_82( + .A1(n_1_0_81), .A2(n_1_0_80), .A3(n_1_0_79), .A4(n_1_0_78), .ZN(n_1_0_77) + ); + NOR3_X1_LVT i_1_0_81( + .A1(n_1_0_87), .A2(n_1_0_82), .A3(n_1_0_77), .ZN(n_1_0_76) + ); + NAND4_X1_LVT i_1_0_80( + .A1(n_1_0_94), .A2(n_1_0_93), .A3(n_1_0_92), .A4(n_1_0_76), .ZN(RRs2[4]) + ); + AOI22_X1_LVT i_1_0_78( + .A1(registers_29__ap[3]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[3]), + .ZN(n_1_0_74) + ); + AOI22_X1_LVT i_1_0_79( + .A1(registers_27__ap[3]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[3]), + .ZN(n_1_0_75) + ); + AOI22_X1_LVT i_1_0_77( + .A1(registers_1__ap[3]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[3]), + .ZN(n_1_0_73) + ); + AOI22_X1_LVT i_1_0_76( + .A1(registers_5__ap[3]), .A2(n_1_0_635), .B1(n_1_0_611), .B2(registers_11__ap[3]), + .ZN(n_1_0_72) + ); + NAND3_X1_LVT i_1_0_75( + .A1(n_1_0_75), .A2(n_1_0_73), .A3(n_1_0_72), .ZN(n_1_0_71) + ); + AOI221_X1_LVT i_1_0_74( + .A(n_1_0_71), .B1(n_1_0_614), .B2(registers_16__ap[3]), .C1(registers_31__ap[3]), + .C2(n_1_0_637), .ZN(n_1_0_70) + ); + AOI222_X1_LVT i_1_0_73( + .A1(registers_8__ap[3]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[3]), + .C1(n_1_0_622), .C2(registers_30__ap[3]), .ZN(n_1_0_69) + ); + NAND3_X1_LVT i_1_0_72( + .A1(n_1_0_74), .A2(n_1_0_70), .A3(n_1_0_69), .ZN(n_1_0_68) + ); + AOI221_X1_LVT i_1_0_71( + .A(n_1_0_68), .B1(n_1_0_638), .B2(registers_4__ap[3]), .C1(registers_28__ap[3]), + .C2(n_1_0_634), .ZN(n_1_0_67) + ); + AOI22_X1_LVT i_1_0_70( + .A1(registers_18__ap[3]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[3]), + .ZN(n_1_0_66) + ); + AOI22_X1_LVT i_1_0_69( + .A1(registers_12__ap[3]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[3]), + .ZN(n_1_0_65) + ); + AOI22_X1_LVT i_1_0_68( + .A1(registers_22__ap[3]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[3]), + .ZN(n_1_0_64) + ); + NAND3_X1_LVT i_1_0_67( + .A1(n_1_0_66), .A2(n_1_0_65), .A3(n_1_0_64), .ZN(n_1_0_63) + ); + AOI221_X1_LVT i_1_0_66( + .A(n_1_0_63), .B1(n_1_0_613), .B2(registers_20__ap[3]), .C1(registers_17__ap[3]), + .C2(n_1_0_629), .ZN(n_1_0_62) + ); + AOI22_X1_LVT i_1_0_65( + .A1(registers_13__ap[3]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[3]), + .ZN(n_1_0_61) + ); + AOI22_X1_LVT i_1_0_64( + .A1(registers_7__ap[3]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[3]), + .ZN(n_1_0_60) + ); + AOI22_X1_LVT i_1_0_63( + .A1(registers_19__ap[3]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[3]), + .ZN(n_1_0_59) + ); + NAND3_X1_LVT i_1_0_62( + .A1(n_1_0_61), .A2(n_1_0_60), .A3(n_1_0_59), .ZN(n_1_0_58) + ); + AOI221_X1_LVT i_1_0_61( + .A(n_1_0_58), .B1(n_1_0_618), .B2(registers_2__ap[3]), .C1(registers_23__ap[3]), + .C2(n_1_0_615), .ZN(n_1_0_57) + ); + NAND3_X1_LVT i_1_0_60( + .A1(n_1_0_67), .A2(n_1_0_62), .A3(n_1_0_57), .ZN(RRs2[3]) + ); + AOI22_X1_LVT i_1_0_58( + .A1(registers_29__ap[2]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[2]), + .ZN(n_1_0_55) + ); + AOI22_X1_LVT i_1_0_59( + .A1(registers_27__ap[2]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[2]), + .ZN(n_1_0_56) + ); + AOI22_X1_LVT i_1_0_57( + .A1(registers_1__ap[2]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[2]), + .ZN(n_1_0_54) + ); + AOI22_X1_LVT i_1_0_56( + .A1(registers_5__ap[2]), .A2(n_1_0_635), .B1(n_1_0_615), .B2(registers_23__ap[2]), + .ZN(n_1_0_53) + ); + NAND3_X1_LVT i_1_0_55( + .A1(n_1_0_56), .A2(n_1_0_54), .A3(n_1_0_53), .ZN(n_1_0_52) + ); + AOI221_X1_LVT i_1_0_54( + .A(n_1_0_52), .B1(n_1_0_637), .B2(registers_31__ap[2]), .C1(registers_16__ap[2]), + .C2(n_1_0_614), .ZN(n_1_0_51) + ); + AOI222_X1_LVT i_1_0_53( + .A1(registers_8__ap[2]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[2]), + .C1(n_1_0_622), .C2(registers_30__ap[2]), .ZN(n_1_0_50) + ); + NAND3_X1_LVT i_1_0_52( + .A1(n_1_0_55), .A2(n_1_0_51), .A3(n_1_0_50), .ZN(n_1_0_49) + ); + AOI221_X1_LVT i_1_0_51( + .A(n_1_0_49), .B1(n_1_0_638), .B2(registers_4__ap[2]), .C1(registers_28__ap[2]), + .C2(n_1_0_634), .ZN(n_1_0_48) + ); + AOI22_X1_LVT i_1_0_50( + .A1(registers_18__ap[2]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[2]), + .ZN(n_1_0_47) + ); + AOI22_X1_LVT i_1_0_49( + .A1(registers_12__ap[2]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[2]), + .ZN(n_1_0_46) + ); + AOI22_X1_LVT i_1_0_48( + .A1(registers_22__ap[2]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[2]), + .ZN(n_1_0_45) + ); + NAND3_X1_LVT i_1_0_47( + .A1(n_1_0_47), .A2(n_1_0_46), .A3(n_1_0_45), .ZN(n_1_0_44) + ); + AOI221_X1_LVT i_1_0_46( + .A(n_1_0_44), .B1(n_1_0_629), .B2(registers_17__ap[2]), .C1(registers_20__ap[2]), + .C2(n_1_0_613), .ZN(n_1_0_43) + ); + AOI22_X1_LVT i_1_0_45( + .A1(registers_13__ap[2]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[2]), + .ZN(n_1_0_42) + ); + AOI22_X1_LVT i_1_0_44( + .A1(registers_7__ap[2]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[2]), + .ZN(n_1_0_41) + ); + AOI22_X1_LVT i_1_0_43( + .A1(registers_19__ap[2]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[2]), + .ZN(n_1_0_40) + ); + NAND3_X1_LVT i_1_0_42( + .A1(n_1_0_42), .A2(n_1_0_41), .A3(n_1_0_40), .ZN(n_1_0_39) + ); + AOI221_X1_LVT i_1_0_41( + .A(n_1_0_39), .B1(n_1_0_618), .B2(registers_2__ap[2]), .C1(registers_11__ap[2]), + .C2(n_1_0_611), .ZN(n_1_0_38) + ); + NAND3_X1_LVT i_1_0_40( + .A1(n_1_0_48), .A2(n_1_0_43), .A3(n_1_0_38), .ZN(RRs2[2]) + ); + AOI22_X1_LVT i_1_0_38( + .A1(registers_29__ap[1]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[1]), + .ZN(n_1_0_36) + ); + AOI22_X1_LVT i_1_0_39( + .A1(registers_16__ap[1]), .A2(n_1_0_614), .B1(n_1_0_610), .B2(registers_3__ap[1]), + .ZN(n_1_0_37) + ); + AOI22_X1_LVT i_1_0_37( + .A1(registers_1__ap[1]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[1]), + .ZN(n_1_0_35) + ); + AOI22_X1_LVT i_1_0_36( + .A1(registers_31__ap[1]), .A2(n_1_0_637), .B1(n_1_0_635), .B2(registers_5__ap[1]), + .ZN(n_1_0_34) + ); + NAND3_X1_LVT i_1_0_35( + .A1(n_1_0_37), .A2(n_1_0_35), .A3(n_1_0_34), .ZN(n_1_0_33) + ); + AOI221_X1_LVT i_1_0_34( + .A(n_1_0_33), .B1(n_1_0_627), .B2(registers_15__ap[1]), .C1(registers_23__ap[1]), + .C2(n_1_0_615), .ZN(n_1_0_32) + ); + AOI222_X1_LVT i_1_0_33( + .A1(registers_26__ap[1]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[1]), + .C1(n_1_0_626), .C2(registers_8__ap[1]), .ZN(n_1_0_31) + ); + NAND3_X1_LVT i_1_0_32( + .A1(n_1_0_36), .A2(n_1_0_32), .A3(n_1_0_31), .ZN(n_1_0_30) + ); + AOI221_X1_LVT i_1_0_31( + .A(n_1_0_30), .B1(n_1_0_629), .B2(registers_17__ap[1]), .C1(registers_28__ap[1]), + .C2(n_1_0_634), .ZN(n_1_0_29) + ); + AOI22_X1_LVT i_1_0_30( + .A1(registers_18__ap[1]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[1]), + .ZN(n_1_0_28) + ); + AOI22_X1_LVT i_1_0_29( + .A1(registers_4__ap[1]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[1]), + .ZN(n_1_0_27) + ); + AOI22_X1_LVT i_1_0_28( + .A1(registers_22__ap[1]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[1]), + .ZN(n_1_0_26) + ); + NAND3_X1_LVT i_1_0_27( + .A1(n_1_0_28), .A2(n_1_0_27), .A3(n_1_0_26), .ZN(n_1_0_25) + ); + AOI221_X1_LVT i_1_0_26( + .A(n_1_0_25), .B1(n_1_0_632), .B2(registers_12__ap[1]), .C1(registers_24__ap[1]), + .C2(n_1_0_621), .ZN(n_1_0_24) + ); + AOI22_X1_LVT i_1_0_25( + .A1(registers_13__ap[1]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[1]), + .ZN(n_1_0_23) + ); + AOI22_X1_LVT i_1_0_24( + .A1(registers_7__ap[1]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[1]), + .ZN(n_1_0_22) + ); + AOI22_X1_LVT i_1_0_23( + .A1(registers_19__ap[1]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[1]), + .ZN(n_1_0_21) + ); + NAND3_X1_LVT i_1_0_22( + .A1(n_1_0_23), .A2(n_1_0_22), .A3(n_1_0_21), .ZN(n_1_0_20) + ); + AOI221_X1_LVT i_1_0_21( + .A(n_1_0_20), .B1(n_1_0_611), .B2(registers_11__ap[1]), .C1(registers_27__ap[1]), + .C2(n_1_0_636), .ZN(n_1_0_19) + ); + NAND3_X1_LVT i_1_0_20( + .A1(n_1_0_29), .A2(n_1_0_24), .A3(n_1_0_19), .ZN(RRs2[1]) + ); + AOI22_X1_LVT i_1_0_19( + .A1(registers_4__ap[0]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[0]), + .ZN(n_1_0_18) + ); + AOI222_X1_LVT i_1_0_18( + .A1(registers_8__ap[0]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[0]), + .C1(n_1_0_622), .C2(registers_30__ap[0]), .ZN(n_1_0_17) + ); + AOI22_X1_LVT i_1_0_17( + .A1(registers_29__ap[0]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[0]), + .ZN(n_1_0_16) + ); + AOI22_X1_LVT i_1_0_16( + .A1(registers_1__ap[0]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[0]), + .ZN(n_1_0_15) + ); + AOI22_X1_LVT i_1_0_15( + .A1(registers_27__ap[0]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[0]), + .ZN(n_1_0_14) + ); + AOI22_X1_LVT i_1_0_14( + .A1(registers_23__ap[0]), .A2(n_1_0_615), .B1(n_1_0_614), .B2(registers_16__ap[0]), + .ZN(n_1_0_13) + ); + AOI22_X1_LVT i_1_0_13( + .A1(registers_31__ap[0]), .A2(n_1_0_637), .B1(n_1_0_635), .B2(registers_5__ap[0]), + .ZN(n_1_0_12) + ); + NAND4_X1_LVT i_1_0_12( + .A1(n_1_0_15), .A2(n_1_0_14), .A3(n_1_0_13), .A4(n_1_0_12), .ZN(n_1_0_11) + ); + AOI22_X1_LVT i_1_0_11( + .A1(registers_18__ap[0]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[0]), + .ZN(n_1_0_10) + ); + AOI22_X1_LVT i_1_0_10( + .A1(registers_12__ap[0]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[0]), + .ZN(n_1_0_9) + ); + AOI22_X1_LVT i_1_0_9( + .A1(registers_22__ap[0]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[0]), + .ZN(n_1_0_8) + ); + AOI22_X1_LVT i_1_0_8( + .A1(registers_17__ap[0]), .A2(n_1_0_629), .B1(n_1_0_613), .B2(registers_20__ap[0]), + .ZN(n_1_0_7) + ); + NAND4_X1_LVT i_1_0_7( + .A1(n_1_0_10), .A2(n_1_0_9), .A3(n_1_0_8), .A4(n_1_0_7), .ZN(n_1_0_6) + ); + AOI22_X1_LVT i_1_0_6( + .A1(registers_13__ap[0]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[0]), + .ZN(n_1_0_5) + ); + AOI22_X1_LVT i_1_0_5( + .A1(registers_7__ap[0]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[0]), + .ZN(n_1_0_4) + ); + AOI22_X1_LVT i_1_0_4( + .A1(registers_19__ap[0]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[0]), + .ZN(n_1_0_3) + ); + AOI22_X1_LVT i_1_0_3( + .A1(registers_2__ap[0]), .A2(n_1_0_618), .B1(n_1_0_611), .B2(registers_11__ap[0]), + .ZN(n_1_0_2) + ); + NAND4_X1_LVT i_1_0_2( + .A1(n_1_0_5), .A2(n_1_0_4), .A3(n_1_0_3), .A4(n_1_0_2), .ZN(n_1_0_1) + ); + NOR3_X1_LVT i_1_0_1( + .A1(n_1_0_11), .A2(n_1_0_6), .A3(n_1_0_1), .ZN(n_1_0_0) + ); + NAND4_X1_LVT i_1_0_0( + .A1(n_1_0_18), .A2(n_1_0_17), .A3(n_1_0_16), .A4(n_1_0_0), .ZN(RRs2[0]) + ); + DLL_X2_LVT ts_lockup_latchn_clkc2_intno1050_i( + .D(registers_1__ap[0]), .GN(n_0_0), .Q(ts_no1050) + ); + DLL_X2_LVT ts_lockup_latchn_clkc4_intno1051_i( + .D(registers_6__ap[0]), .GN(n_0_36), .Q(ts_no1051) + ); + DLL_X2_LVT ts_lockup_latchn_clkc3_intno1053_i( + .D(registers_27__ap[0]), .GN(n_0_57), .Q(ts_no1053) + ); + DLL_X2_LVT ts_lockup_latchn_clkc1_intno1054_i( + .D(registers_11__ap[0]), .GN(n_0_41), .Q(ts_no1054) + ); + CLKBUF_X3_LVT tessent_persistent_cell_buf_extsi1227_i( + .A(ts_extsi1227), .Z(ts_pbuf_extsi1227_) + ); + CLKBUF_X3_LVT tessent_persistent_cell_buf_extsi1228_i( + .A(ts_extsi1228), .Z(ts_pbuf_extsi1228_) + ); + CLKBUF_X3_LVT tessent_persistent_cell_buf_extsi1226_i( + .A(ts_extsi1226), .Z(ts_pbuf_extsi1226_) + ); +endmodule + +module cpu(led, btn, clk_25mhz, scan_en, SI_1, SO_1, SI_2, SO_2, SI_3, SO_3, SI_4, + SO_4); + input [6:0] btn; + input clk_25mhz, scan_en, SI_1, SI_2, SI_3, SI_4; + output [7:0] led; + output SO_1, SO_2, SO_3, SO_4; + + wire [31:0] Instruction, RData, RRs2, RRs1, WRd, DAddr, JumpOrBranchPC, + CurrentPC, NextPC; + wire [1:0] DWidth; + wire WrReg, JumpOrBranch, thePC_n_1, thePC_i_0_n_0, thePC_n_2, thePC_i_0_n_1, + thePC_n_3, thePC_i_0_n_2, thePC_n_4, thePC_i_0_n_3, thePC_n_5, + thePC_i_0_n_4, thePC_n_6, thePC_i_0_n_5, thePC_n_7, thePC_i_0_n_6, + thePC_n_8, thePC_i_0_n_7, thePC_n_9, thePC_i_0_n_8, thePC_n_10, + thePC_i_0_n_9, thePC_n_11, thePC_i_0_n_10, thePC_n_12, thePC_i_0_n_11, + thePC_n_13, thePC_i_0_n_12, thePC_n_14, thePC_i_0_n_13, thePC_n_15, + thePC_i_0_n_14, thePC_n_16, thePC_i_0_n_15, thePC_n_17, thePC_i_0_n_16, + thePC_n_18, thePC_i_0_n_17, thePC_n_19, thePC_i_0_n_18, thePC_n_20, + thePC_i_0_n_19, thePC_n_21, thePC_i_0_n_20, thePC_n_22, thePC_i_0_n_21, + thePC_n_23, thePC_i_0_n_22, thePC_n_24, thePC_i_0_n_23, thePC_n_25, + thePC_i_0_n_24, thePC_n_26, thePC_i_0_n_25, thePC_n_27, thePC_i_0_n_26, + thePC_n_28, thePC_i_0_n_27, thePC_n_29, thePC_n_0, thePC_n_30, n_0_0_0, + thePC_n_31, n_0_0_1, thePC_n_32, thePC_n_33, thePC_n_34, thePC_n_35, + thePC_n_36, thePC_n_37, thePC_n_38, thePC_n_39, thePC_n_40, thePC_n_41, + thePC_n_42, thePC_n_43, n_0_0_2, thePC_n_44, n_0_0_3, thePC_n_45, + n_0_0_4, thePC_n_46, n_0_0_5, thePC_n_47, n_0_0_6, thePC_n_48, n_0_0_7, + thePC_n_49, n_0_0_8, thePC_n_50, n_0_0_9, thePC_n_51, n_0_0_10, + thePC_n_52, n_0_0_11, thePC_n_53, n_0_0_12, thePC_n_54, n_0_0_13, + thePC_n_55, n_0_0_14, thePC_n_56, n_0_0_15, thePC_n_57, n_0_0_16, + thePC_n_58, n_0_0_17, thePC_n_59, n_0_0_18, thePC_n_60, n_0_0_19, + thePC_n_61, n_0_0_20, n_0_0_21, n_0_0_22, reset, uc_0, uc_1, uc_2, uc_3, + uc_4, uc_5, uc_6, uc_7, uc_8, uc_9, uc_10, uc_11, uc_12, uc_13, uc_14, + uc_15, uc_16, uc_17, uc_18, uc_19, uc_20, uc_21, uc_22, uc_23, uc_24, + uc_25, uc_26, uc_27, uc_28, uc_29, uc_30, uc_31, uc_32, uc_33, uc_34, + uc_35, uc_36, uc_37, uc_38, uc_39, uc_40, uc_41, uc_42, uc_43, uc_44, + uc_45, uc_46, uc_47, uc_48, uc_49, uc_50, uc_51, uc_52, uc_53, uc_54, + uc_55, uc_56, uc_57, uc_58, ts_pbuf_extsi1225_, ts_no1054, ts_no1050, + ts_no1053, ts_no1051; + + assign SO_1 = ts_no1054; + assign SO_2 = ts_no1050; + assign SO_3 = ts_no1053; + assign SO_4 = ts_no1051; + AND2_X1_LVT i_0_0_54( + .A1(JumpOrBranch), .A2(btn[0]), .ZN(n_0_0_22) + ); + INV_X1_LVT i_0_0_66( + .A(btn[0]), .ZN(reset) + ); + NOR2_X1_LVT i_0_0_53( + .A1(reset), .A2(JumpOrBranch), .ZN(n_0_0_21) + ); + AOI22_X1_LVT i_0_0_50( + .A1(JumpOrBranchPC[30]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_28), .ZN(n_0_0_19) + ); + INV_X1_LVT i_0_0_49( + .A(n_0_0_19), .ZN(thePC_n_60) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[30] ( + .CK(clk_25mhz), .D(thePC_n_60), .Q(CurrentPC[30]), .QN(), .SE(scan_en), .SI(ts_pbuf_extsi1225_) + ); + AOI22_X1_LVT i_0_0_48( + .A1(JumpOrBranchPC[29]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_27), .ZN(n_0_0_18) + ); + INV_X1_LVT i_0_0_47( + .A(n_0_0_18), .ZN(thePC_n_59) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[29] ( + .CK(clk_25mhz), .D(thePC_n_59), .Q(CurrentPC[29]), .QN(), .SE(scan_en), .SI(CurrentPC[30]) + ); + AOI22_X1_LVT i_0_0_46( + .A1(JumpOrBranchPC[28]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_26), .ZN(n_0_0_17) + ); + INV_X1_LVT i_0_0_45( + .A(n_0_0_17), .ZN(thePC_n_58) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[28] ( + .CK(clk_25mhz), .D(thePC_n_58), .Q(CurrentPC[28]), .QN(), .SE(scan_en), .SI(CurrentPC[29]) + ); + AOI22_X1_LVT i_0_0_44( + .A1(JumpOrBranchPC[27]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_25), .ZN(n_0_0_16) + ); + INV_X1_LVT i_0_0_43( + .A(n_0_0_16), .ZN(thePC_n_57) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[27] ( + .CK(clk_25mhz), .D(thePC_n_57), .Q(CurrentPC[27]), .QN(), .SE(scan_en), .SI(CurrentPC[28]) + ); + AOI22_X1_LVT i_0_0_42( + .A1(JumpOrBranchPC[26]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_24), .ZN(n_0_0_15) + ); + INV_X1_LVT i_0_0_41( + .A(n_0_0_15), .ZN(thePC_n_56) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[26] ( + .CK(clk_25mhz), .D(thePC_n_56), .Q(CurrentPC[26]), .QN(), .SE(scan_en), .SI(CurrentPC[27]) + ); + AOI22_X1_LVT i_0_0_40( + .A1(JumpOrBranchPC[25]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_23), .ZN(n_0_0_14) + ); + INV_X1_LVT i_0_0_39( + .A(n_0_0_14), .ZN(thePC_n_55) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[25] ( + .CK(clk_25mhz), .D(thePC_n_55), .Q(CurrentPC[25]), .QN(), .SE(scan_en), .SI(CurrentPC[26]) + ); + AOI22_X1_LVT i_0_0_38( + .A1(JumpOrBranchPC[24]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_22), .ZN(n_0_0_13) + ); + INV_X1_LVT i_0_0_37( + .A(n_0_0_13), .ZN(thePC_n_54) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[24] ( + .CK(clk_25mhz), .D(thePC_n_54), .Q(CurrentPC[24]), .QN(), .SE(scan_en), .SI(CurrentPC[25]) + ); + AOI22_X1_LVT i_0_0_36( + .A1(JumpOrBranchPC[23]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_21), .ZN(n_0_0_12) + ); + INV_X1_LVT i_0_0_35( + .A(n_0_0_12), .ZN(thePC_n_53) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[23] ( + .CK(clk_25mhz), .D(thePC_n_53), .Q(CurrentPC[23]), .QN(), .SE(scan_en), .SI(CurrentPC[24]) + ); + AOI22_X1_LVT i_0_0_34( + .A1(JumpOrBranchPC[22]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_20), .ZN(n_0_0_11) + ); + INV_X1_LVT i_0_0_33( + .A(n_0_0_11), .ZN(thePC_n_52) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[22] ( + .CK(clk_25mhz), .D(thePC_n_52), .Q(CurrentPC[22]), .QN(), .SE(scan_en), .SI(CurrentPC[23]) + ); + AOI22_X1_LVT i_0_0_32( + .A1(JumpOrBranchPC[21]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_19), .ZN(n_0_0_10) + ); + INV_X1_LVT i_0_0_31( + .A(n_0_0_10), .ZN(thePC_n_51) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[21] ( + .CK(clk_25mhz), .D(thePC_n_51), .Q(CurrentPC[21]), .QN(), .SE(scan_en), .SI(CurrentPC[22]) + ); + AOI22_X1_LVT i_0_0_30( + .A1(JumpOrBranchPC[20]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_18), .ZN(n_0_0_9) + ); + INV_X1_LVT i_0_0_29( + .A(n_0_0_9), .ZN(thePC_n_50) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[20] ( + .CK(clk_25mhz), .D(thePC_n_50), .Q(CurrentPC[20]), .QN(), .SE(scan_en), .SI(CurrentPC[21]) + ); + AOI22_X1_LVT i_0_0_28( + .A1(JumpOrBranchPC[19]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_17), .ZN(n_0_0_8) + ); + INV_X1_LVT i_0_0_27( + .A(n_0_0_8), .ZN(thePC_n_49) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[19] ( + .CK(clk_25mhz), .D(thePC_n_49), .Q(CurrentPC[19]), .QN(), .SE(scan_en), .SI(CurrentPC[20]) + ); + AOI22_X1_LVT i_0_0_26( + .A1(JumpOrBranchPC[18]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_16), .ZN(n_0_0_7) + ); + INV_X1_LVT i_0_0_25( + .A(n_0_0_7), .ZN(thePC_n_48) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[18] ( + .CK(clk_25mhz), .D(thePC_n_48), .Q(CurrentPC[18]), .QN(), .SE(scan_en), .SI(CurrentPC[19]) + ); + AOI22_X1_LVT i_0_0_24( + .A1(JumpOrBranchPC[17]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_15), .ZN(n_0_0_6) + ); + INV_X1_LVT i_0_0_23( + .A(n_0_0_6), .ZN(thePC_n_47) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[17] ( + .CK(clk_25mhz), .D(thePC_n_47), .Q(CurrentPC[17]), .QN(), .SE(scan_en), .SI(CurrentPC[18]) + ); + AOI22_X1_LVT i_0_0_22( + .A1(JumpOrBranchPC[16]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_14), .ZN(n_0_0_5) + ); + INV_X1_LVT i_0_0_21( + .A(n_0_0_5), .ZN(thePC_n_46) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[16] ( + .CK(clk_25mhz), .D(thePC_n_46), .Q(CurrentPC[16]), .QN(), .SE(scan_en), .SI(CurrentPC[17]) + ); + AOI22_X1_LVT i_0_0_20( + .A1(JumpOrBranchPC[15]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_13), .ZN(n_0_0_4) + ); + INV_X1_LVT i_0_0_19( + .A(n_0_0_4), .ZN(thePC_n_45) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[15] ( + .CK(clk_25mhz), .D(thePC_n_45), .Q(CurrentPC[15]), .QN(), .SE(scan_en), .SI(CurrentPC[16]) + ); + AOI22_X1_LVT i_0_0_18( + .A1(JumpOrBranchPC[14]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_12), .ZN(n_0_0_3) + ); + INV_X1_LVT i_0_0_17( + .A(n_0_0_3), .ZN(thePC_n_44) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[14] ( + .CK(clk_25mhz), .D(thePC_n_44), .Q(CurrentPC[14]), .QN(), .SE(scan_en), .SI(CurrentPC[15]) + ); + AOI22_X1_LVT i_0_0_16( + .A1(JumpOrBranchPC[13]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_11), .ZN(n_0_0_2) + ); + INV_X1_LVT i_0_0_15( + .A(n_0_0_2), .ZN(thePC_n_43) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[13] ( + .CK(clk_25mhz), .D(thePC_n_43), .Q(CurrentPC[13]), .QN(), .SE(scan_en), .SI(CurrentPC[14]) + ); + MUX2_X1_LVT i_0_0_65( + .A(thePC_n_10), .B(JumpOrBranchPC[12]), .S(JumpOrBranch), .Z(NextPC[12]) + ); + AND2_X1_LVT i_0_0_14( + .A1(NextPC[12]), .A2(btn[0]), .ZN(thePC_n_42) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[12] ( + .CK(clk_25mhz), .D(thePC_n_42), .Q(CurrentPC[12]), .QN(), .SE(scan_en), .SI(CurrentPC[13]) + ); + MUX2_X1_LVT i_0_0_64( + .A(thePC_n_9), .B(JumpOrBranchPC[11]), .S(JumpOrBranch), .Z(NextPC[11]) + ); + AND2_X1_LVT i_0_0_13( + .A1(NextPC[11]), .A2(btn[0]), .ZN(thePC_n_41) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[11] ( + .CK(clk_25mhz), .D(thePC_n_41), .Q(CurrentPC[11]), .QN(), .SE(scan_en), .SI(CurrentPC[12]) + ); + MUX2_X1_LVT i_0_0_63( + .A(thePC_n_8), .B(JumpOrBranchPC[10]), .S(JumpOrBranch), .Z(NextPC[10]) + ); + AND2_X1_LVT i_0_0_12( + .A1(NextPC[10]), .A2(btn[0]), .ZN(thePC_n_40) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[10] ( + .CK(clk_25mhz), .D(thePC_n_40), .Q(CurrentPC[10]), .QN(), .SE(scan_en), .SI(CurrentPC[11]) + ); + MUX2_X1_LVT i_0_0_62( + .A(thePC_n_7), .B(JumpOrBranchPC[9]), .S(JumpOrBranch), .Z(NextPC[9]) + ); + AND2_X1_LVT i_0_0_11( + .A1(NextPC[9]), .A2(btn[0]), .ZN(thePC_n_39) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[9] ( + .CK(clk_25mhz), .D(thePC_n_39), .Q(CurrentPC[9]), .QN(), .SE(scan_en), .SI(CurrentPC[10]) + ); + MUX2_X1_LVT i_0_0_61( + .A(thePC_n_6), .B(JumpOrBranchPC[8]), .S(JumpOrBranch), .Z(NextPC[8]) + ); + AND2_X1_LVT i_0_0_10( + .A1(NextPC[8]), .A2(btn[0]), .ZN(thePC_n_38) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[8] ( + .CK(clk_25mhz), .D(thePC_n_38), .Q(CurrentPC[8]), .QN(), .SE(scan_en), .SI(CurrentPC[9]) + ); + AND2_X1_LVT i_0_0_9( + .A1(led[7]), .A2(btn[0]), .ZN(thePC_n_37) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[7] ( + .CK(clk_25mhz), .D(thePC_n_37), .Q(CurrentPC[7]), .QN(), .SE(scan_en), .SI(CurrentPC[8]) + ); + MUX2_X1_LVT i_0_0_59( + .A(thePC_n_4), .B(JumpOrBranchPC[6]), .S(JumpOrBranch), .Z(led[6]) + ); + AND2_X1_LVT i_0_0_8( + .A1(led[6]), .A2(btn[0]), .ZN(thePC_n_36) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[6] ( + .CK(clk_25mhz), .D(thePC_n_36), .Q(CurrentPC[6]), .QN(), .SE(scan_en), .SI(CurrentPC[7]) + ); + MUX2_X1_LVT i_0_0_58( + .A(thePC_n_3), .B(JumpOrBranchPC[5]), .S(JumpOrBranch), .Z(led[5]) + ); + AND2_X1_LVT i_0_0_7( + .A1(led[5]), .A2(btn[0]), .ZN(thePC_n_35) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[5] ( + .CK(clk_25mhz), .D(thePC_n_35), .Q(CurrentPC[5]), .QN(), .SE(scan_en), .SI(CurrentPC[6]) + ); + MUX2_X1_LVT i_0_0_57( + .A(thePC_n_2), .B(JumpOrBranchPC[4]), .S(JumpOrBranch), .Z(led[4]) + ); + AND2_X1_LVT i_0_0_6( + .A1(led[4]), .A2(btn[0]), .ZN(thePC_n_34) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[4] ( + .CK(clk_25mhz), .D(thePC_n_34), .Q(CurrentPC[4]), .QN(), .SE(scan_en), .SI(CurrentPC[5]) + ); + MUX2_X1_LVT i_0_0_56( + .A(thePC_n_1), .B(JumpOrBranchPC[3]), .S(JumpOrBranch), .Z(led[3]) + ); + AND2_X1_LVT i_0_0_5( + .A1(led[3]), .A2(btn[0]), .ZN(thePC_n_33) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[3] ( + .CK(clk_25mhz), .D(thePC_n_33), .Q(CurrentPC[3]), .QN(), .SE(scan_en), .SI(CurrentPC[4]) + ); + INV_X1_LVT thePC_i_0_29( + .A(CurrentPC[2]), .ZN(thePC_n_0) + ); + MUX2_X1_LVT i_0_0_55( + .A(thePC_n_0), .B(JumpOrBranchPC[2]), .S(JumpOrBranch), .Z(led[2]) + ); + AND2_X1_LVT i_0_0_4( + .A1(led[2]), .A2(btn[0]), .ZN(thePC_n_32) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[2] ( + .CK(clk_25mhz), .D(thePC_n_32), .Q(CurrentPC[2]), .QN(), .SE(scan_en), .SI(CurrentPC[3]) + ); + HA_X1_LVT thePC_i_0_0( + .A(CurrentPC[3]), .B(CurrentPC[2]), .CO(thePC_i_0_n_0), .S(thePC_n_1) + ); + HA_X1_LVT thePC_i_0_1( + .A(CurrentPC[4]), .B(thePC_i_0_n_0), .CO(thePC_i_0_n_1), .S(thePC_n_2) + ); + HA_X1_LVT thePC_i_0_2( + .A(CurrentPC[5]), .B(thePC_i_0_n_1), .CO(thePC_i_0_n_2), .S(thePC_n_3) + ); + HA_X1_LVT thePC_i_0_3( + .A(CurrentPC[6]), .B(thePC_i_0_n_2), .CO(thePC_i_0_n_3), .S(thePC_n_4) + ); + HA_X1_LVT thePC_i_0_4( + .A(CurrentPC[7]), .B(thePC_i_0_n_3), .CO(thePC_i_0_n_4), .S(thePC_n_5) + ); + HA_X1_LVT thePC_i_0_5( + .A(CurrentPC[8]), .B(thePC_i_0_n_4), .CO(thePC_i_0_n_5), .S(thePC_n_6) + ); + HA_X1_LVT thePC_i_0_6( + .A(CurrentPC[9]), .B(thePC_i_0_n_5), .CO(thePC_i_0_n_6), .S(thePC_n_7) + ); + HA_X1_LVT thePC_i_0_7( + .A(CurrentPC[10]), .B(thePC_i_0_n_6), .CO(thePC_i_0_n_7), .S(thePC_n_8) + ); + HA_X1_LVT thePC_i_0_8( + .A(CurrentPC[11]), .B(thePC_i_0_n_7), .CO(thePC_i_0_n_8), .S(thePC_n_9) + ); + HA_X1_LVT thePC_i_0_9( + .A(CurrentPC[12]), .B(thePC_i_0_n_8), .CO(thePC_i_0_n_9), .S(thePC_n_10) + ); + HA_X1_LVT thePC_i_0_11( + .A(CurrentPC[13]), .B(thePC_i_0_n_9), .CO(thePC_i_0_n_10), .S(thePC_n_11) + ); + HA_X1_LVT thePC_i_0_12( + .A(CurrentPC[14]), .B(thePC_i_0_n_10), .CO(thePC_i_0_n_11), .S(thePC_n_12) + ); + HA_X1_LVT thePC_i_0_13( + .A(CurrentPC[15]), .B(thePC_i_0_n_11), .CO(thePC_i_0_n_12), .S(thePC_n_13) + ); + HA_X1_LVT thePC_i_0_14( + .A(CurrentPC[16]), .B(thePC_i_0_n_12), .CO(thePC_i_0_n_13), .S(thePC_n_14) + ); + HA_X1_LVT thePC_i_0_15( + .A(CurrentPC[17]), .B(thePC_i_0_n_13), .CO(thePC_i_0_n_14), .S(thePC_n_15) + ); + HA_X1_LVT thePC_i_0_16( + .A(CurrentPC[18]), .B(thePC_i_0_n_14), .CO(thePC_i_0_n_15), .S(thePC_n_16) + ); + HA_X1_LVT thePC_i_0_17( + .A(CurrentPC[19]), .B(thePC_i_0_n_15), .CO(thePC_i_0_n_16), .S(thePC_n_17) + ); + HA_X1_LVT thePC_i_0_10( + .A(CurrentPC[20]), .B(thePC_i_0_n_16), .CO(thePC_i_0_n_17), .S(thePC_n_18) + ); + HA_X1_LVT thePC_i_0_18( + .A(CurrentPC[21]), .B(thePC_i_0_n_17), .CO(thePC_i_0_n_18), .S(thePC_n_19) + ); + HA_X1_LVT thePC_i_0_19( + .A(CurrentPC[22]), .B(thePC_i_0_n_18), .CO(thePC_i_0_n_19), .S(thePC_n_20) + ); + HA_X1_LVT thePC_i_0_20( + .A(CurrentPC[23]), .B(thePC_i_0_n_19), .CO(thePC_i_0_n_20), .S(thePC_n_21) + ); + HA_X1_LVT thePC_i_0_21( + .A(CurrentPC[24]), .B(thePC_i_0_n_20), .CO(thePC_i_0_n_21), .S(thePC_n_22) + ); + HA_X1_LVT thePC_i_0_22( + .A(CurrentPC[25]), .B(thePC_i_0_n_21), .CO(thePC_i_0_n_22), .S(thePC_n_23) + ); + HA_X1_LVT thePC_i_0_23( + .A(CurrentPC[26]), .B(thePC_i_0_n_22), .CO(thePC_i_0_n_23), .S(thePC_n_24) + ); + HA_X1_LVT thePC_i_0_24( + .A(CurrentPC[27]), .B(thePC_i_0_n_23), .CO(thePC_i_0_n_24), .S(thePC_n_25) + ); + HA_X1_LVT thePC_i_0_25( + .A(CurrentPC[28]), .B(thePC_i_0_n_24), .CO(thePC_i_0_n_25), .S(thePC_n_26) + ); + HA_X1_LVT thePC_i_0_26( + .A(CurrentPC[29]), .B(thePC_i_0_n_25), .CO(thePC_i_0_n_26), .S(thePC_n_27) + ); + HA_X1_LVT thePC_i_0_27( + .A(CurrentPC[30]), .B(thePC_i_0_n_26), .CO(thePC_i_0_n_27), .S(thePC_n_28) + ); + XOR2_X1_LVT thePC_i_0_28( + .A(CurrentPC[31]), .B(thePC_i_0_n_27), .Z(thePC_n_29) + ); + AOI22_X1_LVT i_0_0_52( + .A1(JumpOrBranchPC[31]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_29), .ZN(n_0_0_20) + ); + INV_X1_LVT i_0_0_51( + .A(n_0_0_20), .ZN(thePC_n_61) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[31] ( + .CK(clk_25mhz), .D(thePC_n_61), .Q(CurrentPC[31]), .QN(), .SE(scan_en), .SI(CurrentPC[2]) + ); + AOI22_X1_LVT i_0_0_3( + .A1(JumpOrBranchPC[1]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(CurrentPC[1]), + .ZN(n_0_0_1) + ); + INV_X1_LVT i_0_0_2( + .A(n_0_0_1), .ZN(thePC_n_31) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[1] ( + .CK(clk_25mhz), .D(thePC_n_31), .Q(CurrentPC[1]), .QN(), .SE(scan_en), .SI(CurrentPC[31]) + ); + AOI22_X1_LVT i_0_0_1( + .A1(JumpOrBranchPC[0]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(CurrentPC[0]), + .ZN(n_0_0_0) + ); + INV_X1_LVT i_0_0_0( + .A(n_0_0_0), .ZN(thePC_n_30) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[0] ( + .CK(clk_25mhz), .D(thePC_n_30), .Q(CurrentPC[0]), .QN(), .SE(scan_en), .SI(CurrentPC[1]) + ); + reg_file theRegisters( + .Rs1({Instruction[19], Instruction[18], Instruction[17], + Instruction[16], Instruction[15]}), .Rs2({Instruction[24], + Instruction[23], Instruction[22], Instruction[21], Instruction[20]}), .Rd({ + Instruction[11], Instruction[10], Instruction[9], Instruction[8], + Instruction[7]}), .RRs1(RRs1), .RRs2(RRs2), .WRd(WRd), .WrReg(WrReg), .reset(reset), + .clk(clk_25mhz), .dftIn(scan_en), .ts_intno31(CurrentPC[0]), .ts_no1050(ts_no1050), + .ts_no1051(ts_no1051), .ts_no1053(ts_no1053), .ts_no1054(ts_no1054), .ts_extsi1226(SI_2), + .ts_extsi1227(SI_3), .ts_extsi1228(SI_4) + ); + main_mem theMem( + .clk(clk_25mhz), .reset(reset), .DAddr({uc_0, uc_1, uc_2, uc_3, uc_4, + uc_5, uc_6, uc_7, uc_8, uc_9, uc_10, uc_11, uc_12, uc_13, uc_14, uc_15, + uc_16, uc_17, uc_18, DAddr[12], DAddr[11], DAddr[10], DAddr[9], + DAddr[8], DAddr[7], DAddr[6], DAddr[5], DAddr[4], DAddr[3], DAddr[2], + DAddr[1], DAddr[0]}), .IAddr({uc_19, uc_20, uc_21, uc_22, uc_23, uc_24, + uc_25, uc_26, uc_27, uc_28, uc_29, uc_30, uc_31, uc_32, uc_33, uc_34, + uc_35, uc_36, uc_37, NextPC[12], NextPC[11], NextPC[10], NextPC[9], + NextPC[8], led[7], led[6], led[5], led[4], led[3], led[2], uc_38, uc_39}), + .DWData(RRs2), .DRData(RData), .IRData(Instruction), .DWE(led[1]), .DWidth(DWidth) + ); + decoder theDecoder( + .CurrentPC(CurrentPC), .JumpOrBranchPC(JumpOrBranchPC), .JumpOrBranch(JumpOrBranch), + .DAddr({uc_40, uc_41, uc_42, uc_43, uc_44, uc_45, uc_46, uc_47, uc_48, + uc_49, uc_50, uc_51, uc_52, uc_53, uc_54, uc_55, uc_56, uc_57, uc_58, + DAddr[12], DAddr[11], DAddr[10], DAddr[9], DAddr[8], DAddr[7], DAddr[6], + DAddr[5], DAddr[4], DAddr[3], DAddr[2], DAddr[1], DAddr[0]}), .WData(), .RData(RData), + .Instruction(Instruction), .WrMem(led[1]), .DWidth(DWidth), .Rs1(), .Rs2(), + .Rd(), .RRs1(RRs1), .RRs2(RRs2), .WRd(WRd), .WrReg(WrReg), .Illegal(led[0]) + ); + MUX2_X1_LVT i_0_0_60( + .A(thePC_n_5), .B(JumpOrBranchPC[7]), .S(JumpOrBranch), .Z(led[7]) + ); + CLKBUF_X3_LVT tessent_persistent_cell_buf_extsi1225_i( + .A(SI_1), .Z(ts_pbuf_extsi1225_) + ); +endmodule + diff --git a/oasys.tessent.02/Scan_0/scan.do b/oasys.tessent.02/Scan_0/scan.do new file mode 100644 index 0000000..ab7d2a1 --- /dev/null +++ b/oasys.tessent.02/Scan_0/scan.do @@ -0,0 +1,57 @@ +set_context dft -scan -no_rtl -design_id Scan_0 +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_low_temp_ccs.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_low_temp_ccs.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/PLL.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/IO.fslib +set_module_matching_options -suffix_pattern_list {{[_]+[0-9]+[_]+[0-9]+}} -regexp -append +set_module_matching_options -suffix_pattern_list {{[_]+[A-Z]+}} -regexp -append +set_module_matching_options -suffix_pattern_list {{[_]+[0-9]+[_]+[0-9]+[_]+[A-Z]+}} -regexp -append +read_verilog /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.02/Scan_0/oasys_netlist.v +set_tsdb_output_directory /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.02/tsdb_outdir +if { [info exists ::env(OASYS_TCD_SCAN_FOLDER)] } { +set_design_sources -format tcd_scan -Y $::env(OASYS_TCD_SCAN_FOLDER) -extensions tcd_scan +} +read_sdc /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.02/Scan_0/oasys.sdc +set_current_design cpu -show_elaboration_warnings +set_design_level physical_block +set_shift_register_identification off + +add_nonscan_instances -instances {{/theMem/\IRData_reg[31] } {/theMem/\IRData_reg[30] } {/theMem/\IRData_reg[29] } {/theMem/\IRData_reg[28] } {/theMem/\IRData_reg[27] } {/theMem/\IRData_reg[26] } {/theMem/\IRData_reg[25] } {/theMem/\IRData_reg[24] } {/theMem/\IRData_reg[23] } {/theMem/\IRData_reg[22] } {/theMem/\IRData_reg[21] } {/theMem/\IRData_reg[20] } {/theMem/\IRData_reg[19] } {/theMem/\IRData_reg[18] } {/theMem/\IRData_reg[17] } {/theMem/\IRData_reg[16] } {/theMem/\IRData_reg[15] } {/theMem/\IRData_reg[14] } {/theMem/\IRData_reg[13] } {/theMem/\IRData_reg[12] } {/theMem/\IRData_reg[11] } {/theMem/\IRData_reg[10] } {/theMem/\IRData_reg[9] } {/theMem/\IRData_reg[8] } {/theMem/\IRData_reg[7] } {/theMem/\IRData_reg[6] } {/theMem/\IRData_reg[5] } {/theMem/\IRData_reg[4] } {/theMem/\IRData_reg[3] } {/theMem/\IRData_reg[2] } {/theMem/\IRData_reg[1] } {/theMem/\IRData_reg[0] } {/theMem/\mem_addr_reg[10] } {/theMem/\mem_addr_reg[9] } {/theMem/\mem_addr_reg[8] } {/theMem/\mem_addr_reg[7] } {/theMem/\mem_addr_reg[6] } {/theMem/\mem_addr_reg[5] } {/theMem/\mem_addr_reg[4] } {/theMem/\mem_addr_reg[3] } {/theMem/\mem_addr_reg[2] } {/theMem/\mem_addr_reg[1] } {/theMem/\mem_addr_reg[0] } {/theMem/\drTmp_reg[31] } {/theMem/\drTmp_reg[30] } {/theMem/\drTmp_reg[29] } {/theMem/\drTmp_reg[28] } {/theMem/\drTmp_reg[27] } {/theMem/\drTmp_reg[26] } {/theMem/\drTmp_reg[25] } {/theMem/\drTmp_reg[24] } {/theMem/\drTmp_reg[23] } {/theMem/\drTmp_reg[22] } {/theMem/\drTmp_reg[21] } {/theMem/\drTmp_reg[20] } {/theMem/\drTmp_reg[19] } {/theMem/\drTmp_reg[18] } {/theMem/\drTmp_reg[17] } {/theMem/\drTmp_reg[16] } {/theMem/\drTmp_reg[15] } {/theMem/\drTmp_reg[14] } {/theMem/\drTmp_reg[13] } {/theMem/\drTmp_reg[12] } {/theMem/\drTmp_reg[11] } {/theMem/\drTmp_reg[10] } {/theMem/\drTmp_reg[9] } {/theMem/\drTmp_reg[8] } {/theMem/\drTmp_reg[7] } {/theMem/\drTmp_reg[6] } {/theMem/\drTmp_reg[5] } {/theMem/\drTmp_reg[4] } {/theMem/\drTmp_reg[3] } {/theMem/\drTmp_reg[2] } {/theMem/\drTmp_reg[1] } {/theMem/\drTmp_reg[0] } {/theMem/\mem_wdata_reg[31] } {/theMem/\mem_wdata_reg[30] } {/theMem/\mem_wdata_reg[29] } {/theMem/\mem_wdata_reg[28] } {/theMem/\mem_wdata_reg[27] } {/theMem/\mem_wdata_reg[26] } {/theMem/\mem_wdata_reg[25] } {/theMem/\mem_wdata_reg[24] } {/theMem/\mem_wdata_reg[23] } {/theMem/\mem_wdata_reg[22] } {/theMem/\mem_wdata_reg[21] } {/theMem/\mem_wdata_reg[20] } {/theMem/\mem_wdata_reg[19] } {/theMem/\mem_wdata_reg[18] } {/theMem/\mem_wdata_reg[17] } {/theMem/\mem_wdata_reg[16] } {/theMem/\mem_wdata_reg[15] } {/theMem/\mem_wdata_reg[14] } {/theMem/\mem_wdata_reg[13] } {/theMem/\mem_wdata_reg[12] } {/theMem/\mem_wdata_reg[11] } {/theMem/\mem_wdata_reg[10] } {/theMem/\mem_wdata_reg[9] } {/theMem/\mem_wdata_reg[8] } {/theMem/\mem_wdata_reg[7] } {/theMem/\mem_wdata_reg[6] } {/theMem/\mem_wdata_reg[5] } {/theMem/\mem_wdata_reg[4] } {/theMem/\mem_wdata_reg[3] } {/theMem/\mem_wdata_reg[2] } {/theMem/\mem_wdata_reg[1] } {/theMem/\mem_wdata_reg[0] } } +if {[catch {get_clocks clk_25mhz > /dev/null }] && +[catch {get_dft_signal clk_25mhz > /dev/null }]} { +add_clocks 0 { clk_25mhz } +} + +set_scan_enable scan_en -active high +add_input_constraints btn[0] -C1 +set_scan_enable scan_en -active high -cluster_name scanChain_1 +set_scan_enable scan_en -active high -cluster_name scanChain_2 +set_scan_enable scan_en -active high -cluster_name scanChain_3 +set_scan_enable scan_en -active high -cluster_name scanChain_4 + +add_black_boxes -modules { MemGen_16_10 } +set_scan_insertion_options -single_clock_edge_chains on -si_port_format {oas_ts_si[%d]} -so_port_format {oas_ts_so[%d]} +set_system_mode analysis +report_drc_rules + +create_scan_chain_family scanChain_1 -include_elements {{/\thePC_CurrentPC_reg[0] } {/\thePC_CurrentPC_reg[10] } {/\thePC_CurrentPC_reg[11] } {/\thePC_CurrentPC_reg[12] } {/\thePC_CurrentPC_reg[13] } {/\thePC_CurrentPC_reg[14] } {/\thePC_CurrentPC_reg[15] } {/\thePC_CurrentPC_reg[16] } {/\thePC_CurrentPC_reg[17] } {/\thePC_CurrentPC_reg[18] } {/\thePC_CurrentPC_reg[19] } {/\thePC_CurrentPC_reg[1] } {/\thePC_CurrentPC_reg[20] } {/\thePC_CurrentPC_reg[21] } {/\thePC_CurrentPC_reg[22] } {/\thePC_CurrentPC_reg[23] } {/\thePC_CurrentPC_reg[24] } {/\thePC_CurrentPC_reg[25] } {/\thePC_CurrentPC_reg[26] } {/\thePC_CurrentPC_reg[27] } {/\thePC_CurrentPC_reg[28] } {/\thePC_CurrentPC_reg[29] } {/\thePC_CurrentPC_reg[2] } {/\thePC_CurrentPC_reg[30] } {/\thePC_CurrentPC_reg[31] } {/\thePC_CurrentPC_reg[3] } {/\thePC_CurrentPC_reg[4] } {/\thePC_CurrentPC_reg[5] } {/\thePC_CurrentPC_reg[6] } {/\thePC_CurrentPC_reg[7] } {/\thePC_CurrentPC_reg[8] } {/\thePC_CurrentPC_reg[9] } {/theRegisters/\registers_reg[10][0] } {/theRegisters/\registers_reg[10][10] } {/theRegisters/\registers_reg[10][11] } {/theRegisters/\registers_reg[10][12] } {/theRegisters/\registers_reg[10][13] } {/theRegisters/\registers_reg[10][14] } {/theRegisters/\registers_reg[10][15] } {/theRegisters/\registers_reg[10][16] } {/theRegisters/\registers_reg[10][17] } {/theRegisters/\registers_reg[10][18] } {/theRegisters/\registers_reg[10][19] } {/theRegisters/\registers_reg[10][1] } {/theRegisters/\registers_reg[10][20] } {/theRegisters/\registers_reg[10][21] } {/theRegisters/\registers_reg[10][22] } {/theRegisters/\registers_reg[10][23] } {/theRegisters/\registers_reg[10][24] } {/theRegisters/\registers_reg[10][25] } {/theRegisters/\registers_reg[10][26] } {/theRegisters/\registers_reg[10][27] } {/theRegisters/\registers_reg[10][28] } {/theRegisters/\registers_reg[10][29] } {/theRegisters/\registers_reg[10][2] } {/theRegisters/\registers_reg[10][30] } {/theRegisters/\registers_reg[10][31] } {/theRegisters/\registers_reg[10][3] } {/theRegisters/\registers_reg[10][4] } {/theRegisters/\registers_reg[10][5] } {/theRegisters/\registers_reg[10][6] } {/theRegisters/\registers_reg[10][7] } {/theRegisters/\registers_reg[10][8] } {/theRegisters/\registers_reg[10][9] } {/theRegisters/\registers_reg[11][0] } {/theRegisters/\registers_reg[11][10] } {/theRegisters/\registers_reg[11][11] } {/theRegisters/\registers_reg[11][12] } {/theRegisters/\registers_reg[11][13] } {/theRegisters/\registers_reg[11][14] } {/theRegisters/\registers_reg[11][15] } {/theRegisters/\registers_reg[11][16] } {/theRegisters/\registers_reg[11][17] } {/theRegisters/\registers_reg[11][18] } {/theRegisters/\registers_reg[11][19] } {/theRegisters/\registers_reg[11][1] } {/theRegisters/\registers_reg[11][20] } {/theRegisters/\registers_reg[11][21] } {/theRegisters/\registers_reg[11][22] } {/theRegisters/\registers_reg[11][23] } {/theRegisters/\registers_reg[11][24] } {/theRegisters/\registers_reg[11][25] } {/theRegisters/\registers_reg[11][26] } {/theRegisters/\registers_reg[11][27] } {/theRegisters/\registers_reg[11][28] } {/theRegisters/\registers_reg[11][29] } {/theRegisters/\registers_reg[11][2] } {/theRegisters/\registers_reg[11][30] } {/theRegisters/\registers_reg[11][31] } {/theRegisters/\registers_reg[11][3] } {/theRegisters/\registers_reg[11][4] } {/theRegisters/\registers_reg[11][5] } {/theRegisters/\registers_reg[11][6] } {/theRegisters/\registers_reg[11][7] } {/theRegisters/\registers_reg[11][8] } {/theRegisters/\registers_reg[11][9] } {/theRegisters/\registers_reg[12][0] } {/theRegisters/\registers_reg[12][10] } {/theRegisters/\registers_reg[12][11] } {/theRegisters/\registers_reg[12][12] } {/theRegisters/\registers_reg[12][13] } {/theRegisters/\registers_reg[12][14] } {/theRegisters/\registers_reg[12][15] } {/theRegisters/\registers_reg[12][16] } {/theRegisters/\registers_reg[12][17] } {/theRegisters/\registers_reg[12][18] } {/theRegisters/\registers_reg[12][19] } {/theRegisters/\registers_reg[12][1] } {/theRegisters/\registers_reg[12][20] } {/theRegisters/\registers_reg[12][21] } {/theRegisters/\registers_reg[12][22] } {/theRegisters/\registers_reg[12][23] } {/theRegisters/\registers_reg[12][24] } {/theRegisters/\registers_reg[12][25] } {/theRegisters/\registers_reg[12][26] } {/theRegisters/\registers_reg[12][27] } {/theRegisters/\registers_reg[12][28] } {/theRegisters/\registers_reg[12][29] } {/theRegisters/\registers_reg[12][2] } {/theRegisters/\registers_reg[12][30] } {/theRegisters/\registers_reg[12][31] } {/theRegisters/\registers_reg[12][3] } {/theRegisters/\registers_reg[12][4] } {/theRegisters/\registers_reg[12][5] } {/theRegisters/\registers_reg[12][6] } {/theRegisters/\registers_reg[12][7] } {/theRegisters/\registers_reg[12][8] } {/theRegisters/\registers_reg[12][9] } {/theRegisters/\registers_reg[13][0] } {/theRegisters/\registers_reg[13][10] } {/theRegisters/\registers_reg[13][11] } {/theRegisters/\registers_reg[13][12] } {/theRegisters/\registers_reg[13][13] } {/theRegisters/\registers_reg[13][14] } {/theRegisters/\registers_reg[13][15] } {/theRegisters/\registers_reg[13][16] } {/theRegisters/\registers_reg[13][17] } {/theRegisters/\registers_reg[13][18] } {/theRegisters/\registers_reg[13][19] } {/theRegisters/\registers_reg[13][1] } {/theRegisters/\registers_reg[13][20] } {/theRegisters/\registers_reg[13][21] } {/theRegisters/\registers_reg[13][22] } {/theRegisters/\registers_reg[13][23] } {/theRegisters/\registers_reg[13][24] } {/theRegisters/\registers_reg[13][25] } {/theRegisters/\registers_reg[13][26] } {/theRegisters/\registers_reg[13][27] } {/theRegisters/\registers_reg[13][28] } {/theRegisters/\registers_reg[13][29] } {/theRegisters/\registers_reg[13][2] } {/theRegisters/\registers_reg[13][30] } {/theRegisters/\registers_reg[13][31] } {/theRegisters/\registers_reg[13][3] } {/theRegisters/\registers_reg[13][4] } {/theRegisters/\registers_reg[13][5] } {/theRegisters/\registers_reg[13][6] } {/theRegisters/\registers_reg[13][7] } {/theRegisters/\registers_reg[13][8] } {/theRegisters/\registers_reg[13][9] } {/theRegisters/\registers_reg[14][0] } {/theRegisters/\registers_reg[14][10] } {/theRegisters/\registers_reg[14][11] } {/theRegisters/\registers_reg[14][12] } {/theRegisters/\registers_reg[14][13] } {/theRegisters/\registers_reg[14][14] } {/theRegisters/\registers_reg[14][15] } {/theRegisters/\registers_reg[14][16] } {/theRegisters/\registers_reg[14][17] } {/theRegisters/\registers_reg[14][18] } {/theRegisters/\registers_reg[14][19] } {/theRegisters/\registers_reg[14][1] } {/theRegisters/\registers_reg[14][20] } {/theRegisters/\registers_reg[14][21] } {/theRegisters/\registers_reg[14][22] } {/theRegisters/\registers_reg[14][23] } {/theRegisters/\registers_reg[14][24] } {/theRegisters/\registers_reg[14][25] } {/theRegisters/\registers_reg[14][26] } {/theRegisters/\registers_reg[14][27] } {/theRegisters/\registers_reg[14][28] } {/theRegisters/\registers_reg[14][29] } {/theRegisters/\registers_reg[14][2] } {/theRegisters/\registers_reg[14][30] } {/theRegisters/\registers_reg[14][31] } {/theRegisters/\registers_reg[14][3] } {/theRegisters/\registers_reg[14][4] } {/theRegisters/\registers_reg[14][5] } {/theRegisters/\registers_reg[14][6] } {/theRegisters/\registers_reg[14][7] } {/theRegisters/\registers_reg[14][8] } {/theRegisters/\registers_reg[14][9] } {/theRegisters/\registers_reg[15][0] } {/theRegisters/\registers_reg[15][10] } {/theRegisters/\registers_reg[15][11] } {/theRegisters/\registers_reg[15][12] } {/theRegisters/\registers_reg[15][13] } {/theRegisters/\registers_reg[15][14] } {/theRegisters/\registers_reg[15][15] } {/theRegisters/\registers_reg[15][16] } {/theRegisters/\registers_reg[15][17] } {/theRegisters/\registers_reg[15][18] } {/theRegisters/\registers_reg[15][19] } {/theRegisters/\registers_reg[15][1] } {/theRegisters/\registers_reg[15][20] } {/theRegisters/\registers_reg[15][21] } {/theRegisters/\registers_reg[15][22] } {/theRegisters/\registers_reg[15][23] } {/theRegisters/\registers_reg[15][24] } {/theRegisters/\registers_reg[15][25] } {/theRegisters/\registers_reg[15][26] } {/theRegisters/\registers_reg[15][27] } {/theRegisters/\registers_reg[15][28] } {/theRegisters/\registers_reg[15][29] } {/theRegisters/\registers_reg[15][2] } {/theRegisters/\registers_reg[15][30] } {/theRegisters/\registers_reg[15][31] } {/theRegisters/\registers_reg[15][3] } {/theRegisters/\registers_reg[15][4] } {/theRegisters/\registers_reg[15][5] } {/theRegisters/\registers_reg[15][6] } {/theRegisters/\registers_reg[15][7] } {/theRegisters/\registers_reg[15][8] } {/theRegisters/\registers_reg[15][9] } {/theRegisters/\registers_reg[16][0] } {/theRegisters/\registers_reg[16][10] } {/theRegisters/\registers_reg[16][11] } {/theRegisters/\registers_reg[16][12] } {/theRegisters/\registers_reg[16][13] } {/theRegisters/\registers_reg[16][14] } {/theRegisters/\registers_reg[16][15] } {/theRegisters/\registers_reg[16][16] } {/theRegisters/\registers_reg[16][17] } {/theRegisters/\registers_reg[16][18] } {/theRegisters/\registers_reg[16][19] } {/theRegisters/\registers_reg[16][1] } {/theRegisters/\registers_reg[16][20] } {/theRegisters/\registers_reg[16][21] } {/theRegisters/\registers_reg[16][22] } {/theRegisters/\registers_reg[16][23] } {/theRegisters/\registers_reg[16][24] } {/theRegisters/\registers_reg[16][25] } {/theRegisters/\registers_reg[16][26] } {/theRegisters/\registers_reg[16][27] } {/theRegisters/\registers_reg[16][28] } {/theRegisters/\registers_reg[16][29] } {/theRegisters/\registers_reg[16][2] } {/theRegisters/\registers_reg[16][30] } {/theRegisters/\registers_reg[16][31] } {/theRegisters/\registers_reg[16][3] } {/theRegisters/\registers_reg[16][4] } {/theRegisters/\registers_reg[16][5] } {/theRegisters/\registers_reg[16][6] } {/theRegisters/\registers_reg[16][7] } {/theRegisters/\registers_reg[16][8] } {/theRegisters/\registers_reg[16][9] } } -si_connections {SI_1 } -so_connections {SO_1 } -chain_count 1 +create_scan_chain_family scanChain_2 -include_elements {{/theRegisters/\registers_reg[17][0] } {/theRegisters/\registers_reg[17][10] } {/theRegisters/\registers_reg[17][11] } {/theRegisters/\registers_reg[17][12] } {/theRegisters/\registers_reg[17][13] } {/theRegisters/\registers_reg[17][14] } {/theRegisters/\registers_reg[17][15] } {/theRegisters/\registers_reg[17][16] } {/theRegisters/\registers_reg[17][17] } {/theRegisters/\registers_reg[17][18] } {/theRegisters/\registers_reg[17][19] } {/theRegisters/\registers_reg[17][1] } {/theRegisters/\registers_reg[17][20] } {/theRegisters/\registers_reg[17][21] } {/theRegisters/\registers_reg[17][22] } {/theRegisters/\registers_reg[17][23] } {/theRegisters/\registers_reg[17][24] } {/theRegisters/\registers_reg[17][25] } {/theRegisters/\registers_reg[17][26] } {/theRegisters/\registers_reg[17][27] } {/theRegisters/\registers_reg[17][28] } {/theRegisters/\registers_reg[17][29] } {/theRegisters/\registers_reg[17][2] } {/theRegisters/\registers_reg[17][30] } {/theRegisters/\registers_reg[17][31] } {/theRegisters/\registers_reg[17][3] } {/theRegisters/\registers_reg[17][4] } {/theRegisters/\registers_reg[17][5] } {/theRegisters/\registers_reg[17][6] } {/theRegisters/\registers_reg[17][7] } {/theRegisters/\registers_reg[17][8] } {/theRegisters/\registers_reg[17][9] } {/theRegisters/\registers_reg[18][0] } {/theRegisters/\registers_reg[18][10] } {/theRegisters/\registers_reg[18][11] } {/theRegisters/\registers_reg[18][12] } {/theRegisters/\registers_reg[18][13] } {/theRegisters/\registers_reg[18][14] } {/theRegisters/\registers_reg[18][15] } {/theRegisters/\registers_reg[18][16] } {/theRegisters/\registers_reg[18][17] } {/theRegisters/\registers_reg[18][18] } {/theRegisters/\registers_reg[18][19] } {/theRegisters/\registers_reg[18][1] } {/theRegisters/\registers_reg[18][20] } {/theRegisters/\registers_reg[18][21] } {/theRegisters/\registers_reg[18][22] } {/theRegisters/\registers_reg[18][23] } {/theRegisters/\registers_reg[18][24] } {/theRegisters/\registers_reg[18][25] } {/theRegisters/\registers_reg[18][26] } {/theRegisters/\registers_reg[18][27] } {/theRegisters/\registers_reg[18][28] } {/theRegisters/\registers_reg[18][29] } {/theRegisters/\registers_reg[18][2] } {/theRegisters/\registers_reg[18][30] } {/theRegisters/\registers_reg[18][31] } {/theRegisters/\registers_reg[18][3] } {/theRegisters/\registers_reg[18][4] } {/theRegisters/\registers_reg[18][5] } {/theRegisters/\registers_reg[18][6] } {/theRegisters/\registers_reg[18][7] } {/theRegisters/\registers_reg[18][8] } {/theRegisters/\registers_reg[18][9] } {/theRegisters/\registers_reg[19][0] } {/theRegisters/\registers_reg[19][10] } {/theRegisters/\registers_reg[19][11] } {/theRegisters/\registers_reg[19][12] } {/theRegisters/\registers_reg[19][13] } {/theRegisters/\registers_reg[19][14] } {/theRegisters/\registers_reg[19][15] } {/theRegisters/\registers_reg[19][16] } {/theRegisters/\registers_reg[19][17] } {/theRegisters/\registers_reg[19][18] } {/theRegisters/\registers_reg[19][19] } {/theRegisters/\registers_reg[19][1] } {/theRegisters/\registers_reg[19][20] } {/theRegisters/\registers_reg[19][21] } {/theRegisters/\registers_reg[19][22] } {/theRegisters/\registers_reg[19][23] } {/theRegisters/\registers_reg[19][24] } {/theRegisters/\registers_reg[19][25] } {/theRegisters/\registers_reg[19][26] } {/theRegisters/\registers_reg[19][27] } {/theRegisters/\registers_reg[19][28] } {/theRegisters/\registers_reg[19][29] } {/theRegisters/\registers_reg[19][2] } {/theRegisters/\registers_reg[19][30] } {/theRegisters/\registers_reg[19][31] } {/theRegisters/\registers_reg[19][3] } {/theRegisters/\registers_reg[19][4] } {/theRegisters/\registers_reg[19][5] } {/theRegisters/\registers_reg[19][6] } {/theRegisters/\registers_reg[19][7] } {/theRegisters/\registers_reg[19][8] } {/theRegisters/\registers_reg[19][9] } {/theRegisters/\registers_reg[1][0] } {/theRegisters/\registers_reg[1][10] } {/theRegisters/\registers_reg[1][11] } {/theRegisters/\registers_reg[1][12] } {/theRegisters/\registers_reg[1][13] } {/theRegisters/\registers_reg[1][14] } {/theRegisters/\registers_reg[1][15] } {/theRegisters/\registers_reg[1][16] } {/theRegisters/\registers_reg[1][17] } {/theRegisters/\registers_reg[1][18] } {/theRegisters/\registers_reg[1][19] } {/theRegisters/\registers_reg[1][1] } {/theRegisters/\registers_reg[1][20] } {/theRegisters/\registers_reg[1][21] } {/theRegisters/\registers_reg[1][22] } {/theRegisters/\registers_reg[1][23] } {/theRegisters/\registers_reg[1][24] } {/theRegisters/\registers_reg[1][25] } {/theRegisters/\registers_reg[1][26] } {/theRegisters/\registers_reg[1][27] } {/theRegisters/\registers_reg[1][28] } {/theRegisters/\registers_reg[1][29] } {/theRegisters/\registers_reg[1][2] } {/theRegisters/\registers_reg[1][30] } {/theRegisters/\registers_reg[1][31] } {/theRegisters/\registers_reg[1][3] } {/theRegisters/\registers_reg[1][4] } {/theRegisters/\registers_reg[1][5] } {/theRegisters/\registers_reg[1][6] } {/theRegisters/\registers_reg[1][7] } {/theRegisters/\registers_reg[1][8] } {/theRegisters/\registers_reg[1][9] } {/theRegisters/\registers_reg[20][0] } {/theRegisters/\registers_reg[20][10] } {/theRegisters/\registers_reg[20][11] } {/theRegisters/\registers_reg[20][12] } {/theRegisters/\registers_reg[20][13] } {/theRegisters/\registers_reg[20][14] } {/theRegisters/\registers_reg[20][15] } {/theRegisters/\registers_reg[20][16] } {/theRegisters/\registers_reg[20][17] } {/theRegisters/\registers_reg[20][18] } {/theRegisters/\registers_reg[20][19] } {/theRegisters/\registers_reg[20][1] } {/theRegisters/\registers_reg[20][20] } {/theRegisters/\registers_reg[20][21] } {/theRegisters/\registers_reg[20][22] } {/theRegisters/\registers_reg[20][23] } {/theRegisters/\registers_reg[20][24] } {/theRegisters/\registers_reg[20][25] } {/theRegisters/\registers_reg[20][26] } {/theRegisters/\registers_reg[20][27] } {/theRegisters/\registers_reg[20][28] } {/theRegisters/\registers_reg[20][29] } {/theRegisters/\registers_reg[20][2] } {/theRegisters/\registers_reg[20][30] } {/theRegisters/\registers_reg[20][31] } {/theRegisters/\registers_reg[20][3] } {/theRegisters/\registers_reg[20][4] } {/theRegisters/\registers_reg[20][5] } {/theRegisters/\registers_reg[20][6] } {/theRegisters/\registers_reg[20][7] } {/theRegisters/\registers_reg[20][8] } {/theRegisters/\registers_reg[20][9] } {/theRegisters/\registers_reg[21][0] } {/theRegisters/\registers_reg[21][10] } {/theRegisters/\registers_reg[21][11] } {/theRegisters/\registers_reg[21][12] } {/theRegisters/\registers_reg[21][13] } {/theRegisters/\registers_reg[21][14] } {/theRegisters/\registers_reg[21][15] } {/theRegisters/\registers_reg[21][16] } {/theRegisters/\registers_reg[21][17] } {/theRegisters/\registers_reg[21][18] } {/theRegisters/\registers_reg[21][19] } {/theRegisters/\registers_reg[21][1] } {/theRegisters/\registers_reg[21][20] } {/theRegisters/\registers_reg[21][21] } {/theRegisters/\registers_reg[21][22] } {/theRegisters/\registers_reg[21][23] } {/theRegisters/\registers_reg[21][24] } {/theRegisters/\registers_reg[21][25] } {/theRegisters/\registers_reg[21][26] } {/theRegisters/\registers_reg[21][27] } {/theRegisters/\registers_reg[21][28] } {/theRegisters/\registers_reg[21][29] } {/theRegisters/\registers_reg[21][2] } {/theRegisters/\registers_reg[21][30] } {/theRegisters/\registers_reg[21][31] } {/theRegisters/\registers_reg[21][3] } {/theRegisters/\registers_reg[21][4] } {/theRegisters/\registers_reg[21][5] } {/theRegisters/\registers_reg[21][6] } {/theRegisters/\registers_reg[21][7] } {/theRegisters/\registers_reg[21][8] } {/theRegisters/\registers_reg[21][9] } {/theRegisters/\registers_reg[22][0] } {/theRegisters/\registers_reg[22][10] } {/theRegisters/\registers_reg[22][11] } {/theRegisters/\registers_reg[22][12] } {/theRegisters/\registers_reg[22][13] } {/theRegisters/\registers_reg[22][14] } {/theRegisters/\registers_reg[22][15] } {/theRegisters/\registers_reg[22][16] } {/theRegisters/\registers_reg[22][17] } {/theRegisters/\registers_reg[22][18] } {/theRegisters/\registers_reg[22][19] } {/theRegisters/\registers_reg[22][1] } {/theRegisters/\registers_reg[22][20] } {/theRegisters/\registers_reg[22][21] } {/theRegisters/\registers_reg[22][22] } {/theRegisters/\registers_reg[22][23] } {/theRegisters/\registers_reg[22][24] } {/theRegisters/\registers_reg[22][25] } {/theRegisters/\registers_reg[22][26] } {/theRegisters/\registers_reg[22][27] } {/theRegisters/\registers_reg[22][28] } {/theRegisters/\registers_reg[22][29] } {/theRegisters/\registers_reg[22][2] } {/theRegisters/\registers_reg[22][30] } {/theRegisters/\registers_reg[22][31] } {/theRegisters/\registers_reg[22][3] } {/theRegisters/\registers_reg[22][4] } {/theRegisters/\registers_reg[22][5] } {/theRegisters/\registers_reg[22][6] } {/theRegisters/\registers_reg[22][7] } {/theRegisters/\registers_reg[22][8] } {/theRegisters/\registers_reg[22][9] } {/theRegisters/\registers_reg[23][0] } {/theRegisters/\registers_reg[23][10] } {/theRegisters/\registers_reg[23][11] } {/theRegisters/\registers_reg[23][12] } {/theRegisters/\registers_reg[23][13] } {/theRegisters/\registers_reg[23][14] } {/theRegisters/\registers_reg[23][15] } {/theRegisters/\registers_reg[23][16] } {/theRegisters/\registers_reg[23][17] } {/theRegisters/\registers_reg[23][18] } {/theRegisters/\registers_reg[23][19] } {/theRegisters/\registers_reg[23][1] } {/theRegisters/\registers_reg[23][20] } {/theRegisters/\registers_reg[23][21] } {/theRegisters/\registers_reg[23][22] } {/theRegisters/\registers_reg[23][23] } {/theRegisters/\registers_reg[23][24] } {/theRegisters/\registers_reg[23][25] } {/theRegisters/\registers_reg[23][26] } {/theRegisters/\registers_reg[23][27] } {/theRegisters/\registers_reg[23][28] } {/theRegisters/\registers_reg[23][29] } {/theRegisters/\registers_reg[23][2] } {/theRegisters/\registers_reg[23][30] } {/theRegisters/\registers_reg[23][31] } {/theRegisters/\registers_reg[23][3] } {/theRegisters/\registers_reg[23][4] } {/theRegisters/\registers_reg[23][5] } {/theRegisters/\registers_reg[23][6] } {/theRegisters/\registers_reg[23][7] } {/theRegisters/\registers_reg[23][8] } {/theRegisters/\registers_reg[23][9] } } -si_connections {SI_2 } -so_connections {SO_2 } -chain_count 1 +create_scan_chain_family scanChain_3 -include_elements {{/theRegisters/\registers_reg[24][0] } {/theRegisters/\registers_reg[24][10] } {/theRegisters/\registers_reg[24][11] } {/theRegisters/\registers_reg[24][12] } {/theRegisters/\registers_reg[24][13] } {/theRegisters/\registers_reg[24][14] } {/theRegisters/\registers_reg[24][15] } {/theRegisters/\registers_reg[24][16] } {/theRegisters/\registers_reg[24][17] } {/theRegisters/\registers_reg[24][18] } {/theRegisters/\registers_reg[24][19] } {/theRegisters/\registers_reg[24][1] } {/theRegisters/\registers_reg[24][20] } {/theRegisters/\registers_reg[24][21] } {/theRegisters/\registers_reg[24][22] } {/theRegisters/\registers_reg[24][23] } {/theRegisters/\registers_reg[24][24] } {/theRegisters/\registers_reg[24][25] } {/theRegisters/\registers_reg[24][26] } {/theRegisters/\registers_reg[24][27] } {/theRegisters/\registers_reg[24][28] } {/theRegisters/\registers_reg[24][29] } {/theRegisters/\registers_reg[24][2] } {/theRegisters/\registers_reg[24][30] } {/theRegisters/\registers_reg[24][31] } {/theRegisters/\registers_reg[24][3] } {/theRegisters/\registers_reg[24][4] } {/theRegisters/\registers_reg[24][5] } {/theRegisters/\registers_reg[24][6] } {/theRegisters/\registers_reg[24][7] } {/theRegisters/\registers_reg[24][8] } {/theRegisters/\registers_reg[24][9] } {/theRegisters/\registers_reg[25][0] } {/theRegisters/\registers_reg[25][10] } {/theRegisters/\registers_reg[25][11] } {/theRegisters/\registers_reg[25][12] } {/theRegisters/\registers_reg[25][13] } {/theRegisters/\registers_reg[25][14] } {/theRegisters/\registers_reg[25][15] } {/theRegisters/\registers_reg[25][16] } {/theRegisters/\registers_reg[25][17] } {/theRegisters/\registers_reg[25][18] } {/theRegisters/\registers_reg[25][19] } {/theRegisters/\registers_reg[25][1] } {/theRegisters/\registers_reg[25][20] } {/theRegisters/\registers_reg[25][21] } {/theRegisters/\registers_reg[25][22] } {/theRegisters/\registers_reg[25][23] } {/theRegisters/\registers_reg[25][24] } {/theRegisters/\registers_reg[25][25] } {/theRegisters/\registers_reg[25][26] } {/theRegisters/\registers_reg[25][27] } {/theRegisters/\registers_reg[25][28] } {/theRegisters/\registers_reg[25][29] } {/theRegisters/\registers_reg[25][2] } {/theRegisters/\registers_reg[25][30] } {/theRegisters/\registers_reg[25][31] } {/theRegisters/\registers_reg[25][3] } {/theRegisters/\registers_reg[25][4] } {/theRegisters/\registers_reg[25][5] } {/theRegisters/\registers_reg[25][6] } {/theRegisters/\registers_reg[25][7] } {/theRegisters/\registers_reg[25][8] } {/theRegisters/\registers_reg[25][9] } {/theRegisters/\registers_reg[26][0] } {/theRegisters/\registers_reg[26][10] } {/theRegisters/\registers_reg[26][11] } {/theRegisters/\registers_reg[26][12] } {/theRegisters/\registers_reg[26][13] } {/theRegisters/\registers_reg[26][14] } {/theRegisters/\registers_reg[26][15] } {/theRegisters/\registers_reg[26][16] } {/theRegisters/\registers_reg[26][17] } {/theRegisters/\registers_reg[26][18] } {/theRegisters/\registers_reg[26][19] } {/theRegisters/\registers_reg[26][1] } {/theRegisters/\registers_reg[26][20] } {/theRegisters/\registers_reg[26][21] } {/theRegisters/\registers_reg[26][22] } {/theRegisters/\registers_reg[26][23] } {/theRegisters/\registers_reg[26][24] } {/theRegisters/\registers_reg[26][25] } {/theRegisters/\registers_reg[26][26] } {/theRegisters/\registers_reg[26][27] } {/theRegisters/\registers_reg[26][28] } {/theRegisters/\registers_reg[26][29] } {/theRegisters/\registers_reg[26][2] } {/theRegisters/\registers_reg[26][30] } {/theRegisters/\registers_reg[26][31] } {/theRegisters/\registers_reg[26][3] } {/theRegisters/\registers_reg[26][4] } {/theRegisters/\registers_reg[26][5] } {/theRegisters/\registers_reg[26][6] } {/theRegisters/\registers_reg[26][7] } {/theRegisters/\registers_reg[26][8] } {/theRegisters/\registers_reg[26][9] } {/theRegisters/\registers_reg[27][0] } {/theRegisters/\registers_reg[27][10] } {/theRegisters/\registers_reg[27][11] } {/theRegisters/\registers_reg[27][12] } {/theRegisters/\registers_reg[27][13] } {/theRegisters/\registers_reg[27][14] } {/theRegisters/\registers_reg[27][15] } {/theRegisters/\registers_reg[27][16] } {/theRegisters/\registers_reg[27][17] } {/theRegisters/\registers_reg[27][18] } {/theRegisters/\registers_reg[27][19] } {/theRegisters/\registers_reg[27][1] } {/theRegisters/\registers_reg[27][20] } {/theRegisters/\registers_reg[27][21] } {/theRegisters/\registers_reg[27][22] } {/theRegisters/\registers_reg[27][23] } {/theRegisters/\registers_reg[27][24] } {/theRegisters/\registers_reg[27][25] } {/theRegisters/\registers_reg[27][26] } {/theRegisters/\registers_reg[27][27] } {/theRegisters/\registers_reg[27][28] } {/theRegisters/\registers_reg[27][29] } {/theRegisters/\registers_reg[27][2] } {/theRegisters/\registers_reg[27][30] } {/theRegisters/\registers_reg[27][31] } {/theRegisters/\registers_reg[27][3] } {/theRegisters/\registers_reg[27][4] } {/theRegisters/\registers_reg[27][5] } {/theRegisters/\registers_reg[27][6] } {/theRegisters/\registers_reg[27][7] } {/theRegisters/\registers_reg[27][8] } {/theRegisters/\registers_reg[27][9] } {/theRegisters/\registers_reg[28][0] } {/theRegisters/\registers_reg[28][10] } {/theRegisters/\registers_reg[28][11] } {/theRegisters/\registers_reg[28][12] } {/theRegisters/\registers_reg[28][13] } {/theRegisters/\registers_reg[28][14] } {/theRegisters/\registers_reg[28][15] } {/theRegisters/\registers_reg[28][16] } {/theRegisters/\registers_reg[28][17] } {/theRegisters/\registers_reg[28][18] } {/theRegisters/\registers_reg[28][19] } {/theRegisters/\registers_reg[28][1] } {/theRegisters/\registers_reg[28][20] } {/theRegisters/\registers_reg[28][21] } {/theRegisters/\registers_reg[28][22] } {/theRegisters/\registers_reg[28][23] } {/theRegisters/\registers_reg[28][24] } {/theRegisters/\registers_reg[28][25] } {/theRegisters/\registers_reg[28][26] } {/theRegisters/\registers_reg[28][27] } {/theRegisters/\registers_reg[28][28] } {/theRegisters/\registers_reg[28][29] } {/theRegisters/\registers_reg[28][2] } {/theRegisters/\registers_reg[28][30] } {/theRegisters/\registers_reg[28][31] } {/theRegisters/\registers_reg[28][3] } {/theRegisters/\registers_reg[28][4] } {/theRegisters/\registers_reg[28][5] } {/theRegisters/\registers_reg[28][6] } {/theRegisters/\registers_reg[28][7] } {/theRegisters/\registers_reg[28][8] } {/theRegisters/\registers_reg[28][9] } {/theRegisters/\registers_reg[29][0] } {/theRegisters/\registers_reg[29][10] } {/theRegisters/\registers_reg[29][11] } {/theRegisters/\registers_reg[29][12] } {/theRegisters/\registers_reg[29][13] } {/theRegisters/\registers_reg[29][14] } {/theRegisters/\registers_reg[29][15] } {/theRegisters/\registers_reg[29][16] } {/theRegisters/\registers_reg[29][17] } {/theRegisters/\registers_reg[29][18] } {/theRegisters/\registers_reg[29][19] } {/theRegisters/\registers_reg[29][1] } {/theRegisters/\registers_reg[29][20] } {/theRegisters/\registers_reg[29][21] } {/theRegisters/\registers_reg[29][22] } {/theRegisters/\registers_reg[29][23] } {/theRegisters/\registers_reg[29][24] } {/theRegisters/\registers_reg[29][25] } {/theRegisters/\registers_reg[29][26] } {/theRegisters/\registers_reg[29][27] } {/theRegisters/\registers_reg[29][28] } {/theRegisters/\registers_reg[29][29] } {/theRegisters/\registers_reg[29][2] } {/theRegisters/\registers_reg[29][30] } {/theRegisters/\registers_reg[29][31] } {/theRegisters/\registers_reg[29][3] } {/theRegisters/\registers_reg[29][4] } {/theRegisters/\registers_reg[29][5] } {/theRegisters/\registers_reg[29][6] } {/theRegisters/\registers_reg[29][7] } {/theRegisters/\registers_reg[29][8] } {/theRegisters/\registers_reg[29][9] } {/theRegisters/\registers_reg[2][0] } {/theRegisters/\registers_reg[2][10] } {/theRegisters/\registers_reg[2][11] } {/theRegisters/\registers_reg[2][12] } {/theRegisters/\registers_reg[2][13] } {/theRegisters/\registers_reg[2][14] } {/theRegisters/\registers_reg[2][15] } {/theRegisters/\registers_reg[2][16] } {/theRegisters/\registers_reg[2][17] } {/theRegisters/\registers_reg[2][18] } {/theRegisters/\registers_reg[2][19] } {/theRegisters/\registers_reg[2][1] } {/theRegisters/\registers_reg[2][20] } {/theRegisters/\registers_reg[2][21] } {/theRegisters/\registers_reg[2][22] } {/theRegisters/\registers_reg[2][23] } {/theRegisters/\registers_reg[2][24] } {/theRegisters/\registers_reg[2][25] } {/theRegisters/\registers_reg[2][26] } {/theRegisters/\registers_reg[2][27] } {/theRegisters/\registers_reg[2][28] } {/theRegisters/\registers_reg[2][29] } {/theRegisters/\registers_reg[2][2] } {/theRegisters/\registers_reg[2][30] } {/theRegisters/\registers_reg[2][31] } {/theRegisters/\registers_reg[2][3] } {/theRegisters/\registers_reg[2][4] } {/theRegisters/\registers_reg[2][5] } {/theRegisters/\registers_reg[2][6] } {/theRegisters/\registers_reg[2][7] } {/theRegisters/\registers_reg[2][8] } {/theRegisters/\registers_reg[2][9] } {/theRegisters/\registers_reg[30][0] } {/theRegisters/\registers_reg[30][10] } {/theRegisters/\registers_reg[30][11] } {/theRegisters/\registers_reg[30][12] } {/theRegisters/\registers_reg[30][13] } {/theRegisters/\registers_reg[30][14] } {/theRegisters/\registers_reg[30][15] } {/theRegisters/\registers_reg[30][16] } {/theRegisters/\registers_reg[30][17] } {/theRegisters/\registers_reg[30][18] } {/theRegisters/\registers_reg[30][19] } {/theRegisters/\registers_reg[30][1] } {/theRegisters/\registers_reg[30][20] } {/theRegisters/\registers_reg[30][21] } {/theRegisters/\registers_reg[30][22] } {/theRegisters/\registers_reg[30][23] } {/theRegisters/\registers_reg[30][24] } {/theRegisters/\registers_reg[30][25] } {/theRegisters/\registers_reg[30][26] } {/theRegisters/\registers_reg[30][27] } {/theRegisters/\registers_reg[30][28] } {/theRegisters/\registers_reg[30][29] } {/theRegisters/\registers_reg[30][2] } {/theRegisters/\registers_reg[30][30] } {/theRegisters/\registers_reg[30][31] } {/theRegisters/\registers_reg[30][3] } {/theRegisters/\registers_reg[30][4] } {/theRegisters/\registers_reg[30][5] } {/theRegisters/\registers_reg[30][6] } {/theRegisters/\registers_reg[30][7] } {/theRegisters/\registers_reg[30][8] } {/theRegisters/\registers_reg[30][9] } } -si_connections {SI_3 } -so_connections {SO_3 } -chain_count 1 +create_scan_chain_family scanChain_4 -include_elements {{/theRegisters/\registers_reg[31][0] } {/theRegisters/\registers_reg[31][10] } {/theRegisters/\registers_reg[31][11] } {/theRegisters/\registers_reg[31][12] } {/theRegisters/\registers_reg[31][13] } {/theRegisters/\registers_reg[31][14] } {/theRegisters/\registers_reg[31][15] } {/theRegisters/\registers_reg[31][16] } {/theRegisters/\registers_reg[31][17] } {/theRegisters/\registers_reg[31][18] } {/theRegisters/\registers_reg[31][19] } {/theRegisters/\registers_reg[31][1] } {/theRegisters/\registers_reg[31][20] } {/theRegisters/\registers_reg[31][21] } {/theRegisters/\registers_reg[31][22] } {/theRegisters/\registers_reg[31][23] } {/theRegisters/\registers_reg[31][24] } {/theRegisters/\registers_reg[31][25] } {/theRegisters/\registers_reg[31][26] } {/theRegisters/\registers_reg[31][27] } {/theRegisters/\registers_reg[31][28] } {/theRegisters/\registers_reg[31][29] } {/theRegisters/\registers_reg[31][2] } {/theRegisters/\registers_reg[31][30] } {/theRegisters/\registers_reg[31][31] } {/theRegisters/\registers_reg[31][3] } {/theRegisters/\registers_reg[31][4] } {/theRegisters/\registers_reg[31][5] } {/theRegisters/\registers_reg[31][6] } {/theRegisters/\registers_reg[31][7] } {/theRegisters/\registers_reg[31][8] } {/theRegisters/\registers_reg[31][9] } {/theRegisters/\registers_reg[3][0] } {/theRegisters/\registers_reg[3][10] } {/theRegisters/\registers_reg[3][11] } {/theRegisters/\registers_reg[3][12] } {/theRegisters/\registers_reg[3][13] } {/theRegisters/\registers_reg[3][14] } {/theRegisters/\registers_reg[3][15] } {/theRegisters/\registers_reg[3][16] } {/theRegisters/\registers_reg[3][17] } {/theRegisters/\registers_reg[3][18] } {/theRegisters/\registers_reg[3][19] } {/theRegisters/\registers_reg[3][1] } {/theRegisters/\registers_reg[3][20] } {/theRegisters/\registers_reg[3][21] } {/theRegisters/\registers_reg[3][22] } {/theRegisters/\registers_reg[3][23] } {/theRegisters/\registers_reg[3][24] } {/theRegisters/\registers_reg[3][25] } {/theRegisters/\registers_reg[3][26] } {/theRegisters/\registers_reg[3][27] } {/theRegisters/\registers_reg[3][28] } {/theRegisters/\registers_reg[3][29] } {/theRegisters/\registers_reg[3][2] } {/theRegisters/\registers_reg[3][30] } {/theRegisters/\registers_reg[3][31] } {/theRegisters/\registers_reg[3][3] } {/theRegisters/\registers_reg[3][4] } {/theRegisters/\registers_reg[3][5] } {/theRegisters/\registers_reg[3][6] } {/theRegisters/\registers_reg[3][7] } {/theRegisters/\registers_reg[3][8] } {/theRegisters/\registers_reg[3][9] } {/theRegisters/\registers_reg[4][0] } {/theRegisters/\registers_reg[4][10] } {/theRegisters/\registers_reg[4][11] } {/theRegisters/\registers_reg[4][12] } {/theRegisters/\registers_reg[4][13] } {/theRegisters/\registers_reg[4][14] } {/theRegisters/\registers_reg[4][15] } {/theRegisters/\registers_reg[4][16] } {/theRegisters/\registers_reg[4][17] } {/theRegisters/\registers_reg[4][18] } {/theRegisters/\registers_reg[4][19] } {/theRegisters/\registers_reg[4][1] } {/theRegisters/\registers_reg[4][20] } {/theRegisters/\registers_reg[4][21] } {/theRegisters/\registers_reg[4][22] } {/theRegisters/\registers_reg[4][23] } {/theRegisters/\registers_reg[4][24] } {/theRegisters/\registers_reg[4][25] } {/theRegisters/\registers_reg[4][26] } {/theRegisters/\registers_reg[4][27] } {/theRegisters/\registers_reg[4][28] } {/theRegisters/\registers_reg[4][29] } {/theRegisters/\registers_reg[4][2] } {/theRegisters/\registers_reg[4][30] } {/theRegisters/\registers_reg[4][31] } {/theRegisters/\registers_reg[4][3] } {/theRegisters/\registers_reg[4][4] } {/theRegisters/\registers_reg[4][5] } {/theRegisters/\registers_reg[4][6] } {/theRegisters/\registers_reg[4][7] } {/theRegisters/\registers_reg[4][8] } {/theRegisters/\registers_reg[4][9] } {/theRegisters/\registers_reg[5][0] } {/theRegisters/\registers_reg[5][10] } {/theRegisters/\registers_reg[5][11] } {/theRegisters/\registers_reg[5][12] } {/theRegisters/\registers_reg[5][13] } {/theRegisters/\registers_reg[5][14] } {/theRegisters/\registers_reg[5][15] } {/theRegisters/\registers_reg[5][16] } {/theRegisters/\registers_reg[5][17] } {/theRegisters/\registers_reg[5][18] } {/theRegisters/\registers_reg[5][19] } {/theRegisters/\registers_reg[5][1] } {/theRegisters/\registers_reg[5][20] } {/theRegisters/\registers_reg[5][21] } {/theRegisters/\registers_reg[5][22] } {/theRegisters/\registers_reg[5][23] } {/theRegisters/\registers_reg[5][24] } {/theRegisters/\registers_reg[5][25] } {/theRegisters/\registers_reg[5][26] } {/theRegisters/\registers_reg[5][27] } {/theRegisters/\registers_reg[5][28] } {/theRegisters/\registers_reg[5][29] } {/theRegisters/\registers_reg[5][2] } {/theRegisters/\registers_reg[5][30] } {/theRegisters/\registers_reg[5][31] } {/theRegisters/\registers_reg[5][3] } {/theRegisters/\registers_reg[5][4] } {/theRegisters/\registers_reg[5][5] } {/theRegisters/\registers_reg[5][6] } {/theRegisters/\registers_reg[5][7] } {/theRegisters/\registers_reg[5][8] } {/theRegisters/\registers_reg[5][9] } {/theRegisters/\registers_reg[6][0] } {/theRegisters/\registers_reg[6][10] } {/theRegisters/\registers_reg[6][11] } {/theRegisters/\registers_reg[6][12] } {/theRegisters/\registers_reg[6][13] } {/theRegisters/\registers_reg[6][14] } {/theRegisters/\registers_reg[6][15] } {/theRegisters/\registers_reg[6][16] } {/theRegisters/\registers_reg[6][17] } {/theRegisters/\registers_reg[6][18] } {/theRegisters/\registers_reg[6][19] } {/theRegisters/\registers_reg[6][1] } {/theRegisters/\registers_reg[6][20] } {/theRegisters/\registers_reg[6][21] } {/theRegisters/\registers_reg[6][22] } {/theRegisters/\registers_reg[6][23] } {/theRegisters/\registers_reg[6][24] } {/theRegisters/\registers_reg[6][25] } {/theRegisters/\registers_reg[6][26] } {/theRegisters/\registers_reg[6][27] } {/theRegisters/\registers_reg[6][28] } {/theRegisters/\registers_reg[6][29] } {/theRegisters/\registers_reg[6][2] } {/theRegisters/\registers_reg[6][30] } {/theRegisters/\registers_reg[6][31] } {/theRegisters/\registers_reg[6][3] } {/theRegisters/\registers_reg[6][4] } {/theRegisters/\registers_reg[6][5] } {/theRegisters/\registers_reg[6][6] } {/theRegisters/\registers_reg[6][7] } {/theRegisters/\registers_reg[6][8] } {/theRegisters/\registers_reg[6][9] } {/theRegisters/\registers_reg[7][0] } {/theRegisters/\registers_reg[7][10] } {/theRegisters/\registers_reg[7][11] } {/theRegisters/\registers_reg[7][12] } {/theRegisters/\registers_reg[7][13] } {/theRegisters/\registers_reg[7][14] } {/theRegisters/\registers_reg[7][15] } {/theRegisters/\registers_reg[7][16] } {/theRegisters/\registers_reg[7][17] } {/theRegisters/\registers_reg[7][18] } {/theRegisters/\registers_reg[7][19] } {/theRegisters/\registers_reg[7][1] } {/theRegisters/\registers_reg[7][20] } {/theRegisters/\registers_reg[7][21] } {/theRegisters/\registers_reg[7][22] } {/theRegisters/\registers_reg[7][23] } {/theRegisters/\registers_reg[7][24] } {/theRegisters/\registers_reg[7][25] } {/theRegisters/\registers_reg[7][26] } {/theRegisters/\registers_reg[7][27] } {/theRegisters/\registers_reg[7][28] } {/theRegisters/\registers_reg[7][29] } {/theRegisters/\registers_reg[7][2] } {/theRegisters/\registers_reg[7][30] } {/theRegisters/\registers_reg[7][31] } {/theRegisters/\registers_reg[7][3] } {/theRegisters/\registers_reg[7][4] } {/theRegisters/\registers_reg[7][5] } {/theRegisters/\registers_reg[7][6] } {/theRegisters/\registers_reg[7][7] } {/theRegisters/\registers_reg[7][8] } {/theRegisters/\registers_reg[7][9] } {/theRegisters/\registers_reg[8][0] } {/theRegisters/\registers_reg[8][10] } {/theRegisters/\registers_reg[8][11] } {/theRegisters/\registers_reg[8][12] } {/theRegisters/\registers_reg[8][13] } {/theRegisters/\registers_reg[8][14] } {/theRegisters/\registers_reg[8][15] } {/theRegisters/\registers_reg[8][16] } {/theRegisters/\registers_reg[8][17] } {/theRegisters/\registers_reg[8][18] } {/theRegisters/\registers_reg[8][19] } {/theRegisters/\registers_reg[8][1] } {/theRegisters/\registers_reg[8][20] } {/theRegisters/\registers_reg[8][21] } {/theRegisters/\registers_reg[8][22] } {/theRegisters/\registers_reg[8][23] } {/theRegisters/\registers_reg[8][24] } {/theRegisters/\registers_reg[8][25] } {/theRegisters/\registers_reg[8][26] } {/theRegisters/\registers_reg[8][27] } {/theRegisters/\registers_reg[8][28] } {/theRegisters/\registers_reg[8][29] } {/theRegisters/\registers_reg[8][2] } {/theRegisters/\registers_reg[8][30] } {/theRegisters/\registers_reg[8][31] } {/theRegisters/\registers_reg[8][3] } {/theRegisters/\registers_reg[8][4] } {/theRegisters/\registers_reg[8][5] } {/theRegisters/\registers_reg[8][6] } {/theRegisters/\registers_reg[8][7] } {/theRegisters/\registers_reg[8][8] } {/theRegisters/\registers_reg[8][9] } {/theRegisters/\registers_reg[9][0] } {/theRegisters/\registers_reg[9][10] } {/theRegisters/\registers_reg[9][11] } {/theRegisters/\registers_reg[9][12] } {/theRegisters/\registers_reg[9][13] } {/theRegisters/\registers_reg[9][14] } {/theRegisters/\registers_reg[9][15] } {/theRegisters/\registers_reg[9][16] } {/theRegisters/\registers_reg[9][17] } {/theRegisters/\registers_reg[9][18] } {/theRegisters/\registers_reg[9][19] } {/theRegisters/\registers_reg[9][1] } {/theRegisters/\registers_reg[9][20] } {/theRegisters/\registers_reg[9][21] } {/theRegisters/\registers_reg[9][22] } {/theRegisters/\registers_reg[9][23] } {/theRegisters/\registers_reg[9][24] } {/theRegisters/\registers_reg[9][25] } {/theRegisters/\registers_reg[9][26] } {/theRegisters/\registers_reg[9][27] } {/theRegisters/\registers_reg[9][28] } {/theRegisters/\registers_reg[9][29] } {/theRegisters/\registers_reg[9][2] } {/theRegisters/\registers_reg[9][30] } {/theRegisters/\registers_reg[9][31] } {/theRegisters/\registers_reg[9][3] } {/theRegisters/\registers_reg[9][4] } {/theRegisters/\registers_reg[9][5] } {/theRegisters/\registers_reg[9][6] } {/theRegisters/\registers_reg[9][7] } {/theRegisters/\registers_reg[9][8] } {/theRegisters/\registers_reg[9][9] } } -si_connections {SI_4 } -so_connections {SO_4 } -chain_count 1 +source /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.02/Scan_0/scan_enable_cluster.cfg +analyze_scan_chains +insert_test_logic -write_in_tsdb on +report_scan_chains + +write_scan_order /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.02/Scan_0/cpu.scandef -use_escaping_rule Lefdef -replace +write_design -output_file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.02/Scan_0/post_scan.v -replace + diff --git a/oasys.tessent.02/Scan_0/scan.log b/oasys.tessent.02/Scan_0/scan.log new file mode 100644 index 0000000..0a43177 --- /dev/null +++ b/oasys.tessent.02/Scan_0/scan.log @@ -0,0 +1,409 @@ +/applications/SiemensEDA/siemenseda2023/tessent_2023.4-p1/bin/tessent -shell -dofile /tmp/oasys.2567737/.tmpTessentFile -log_file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.02/Scan_0/scan.log -replace +// Tessent Shell 2023.4-p1 Mon Feb 19 16:22:02 GMT 2024 +// Unpublished work. Copyright 2024 Siemens +// +// This material contains trade secrets or otherwise confidential +// information owned by Siemens Industry Software Inc. or its affiliates +// (collectively, "SISW"), or its licensors. Access to and use of this +// information is strictly limited as set forth in the Customer's +// applicable agreements with SISW. +// +// Siemens software executing under x86-64 Linux on Fri May 29 09:12:34 CEST 2026. +// 64 bit version +// Host: efiapps0.ads1.fh-nuernberg.de (12 x 3.5 GHz, 48014 MB RAM, 24575 MB Swap) +// +// command: if {[catch {source /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.02/Scan_0/scan.do} msg]} { +// puts "$msg" +// puts "TESSENT_ER_ORTL" } +// sub-command: set_context dft -scan -no_rtl -design_id Scan_0 +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_low_temp_ccs.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_low_temp_ccs.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_low_temp_ccs.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_low_temp_ccs.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_low_temp_ccs.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_low_temp_ccs.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/PLL.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/PLL.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/PLL.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/IO.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/IO.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/IO.fslib +// sub-command: set_module_matching_options -suffix_pattern_list {[_]+[0-9]+[_]+[0-9]+} -regexp -append +// sub-command: set_module_matching_options -suffix_pattern_list {[_]+[A-Z]+} -regexp -append +// sub-command: set_module_matching_options -suffix_pattern_list {[_]+[0-9]+[_]+[0-9]+[_]+[A-Z]+} -regexp -append +// sub-command: read_verilog /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.02/Scan_0/oasys_netlist.v +// sub-command: set_tsdb_output_directory /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.02/tsdb_outdir +// sub-command: read_sdc /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.02/Scan_0/oasys.sdc +// Command 'read_sdc' requires an elaborated design. Automatically elaborating the design ... +// Note: 640 duplicate cell library models were read. The last model read of the same name was kept. +// To see detailed messages per duplicate model, issue 'set_cell_library_options -report_duplicate_models on' +// before issuing 'read_cell_library'. +// Warning: 1 cell library model contained 2 floating model outputs. +// To see detailed messages per model, issue 'set_cell_library_options -report_floating_nets on' +// before issuing 'read_cell_library'. +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X1' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X2' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X4' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X8' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X1_HVT' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X2_HVT' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X4_HVT' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X8_HVT' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X1_SVT' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X2_SVT' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X4_SVT' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X8_SVT' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X1_LVT' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X2_LVT' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X4_LVT' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X8_LVT' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' +// Note: Top design is 'cpu'. +// Warning: Undefined modules were found. +// Before using "set_system_mode" or "create_flat_model", you must either define +// the missing modules using "read_verilog" and/or "read_cell_library", or use the +// following command to treat them as black boxes: + add_black_boxes -modules { \ + MemGen_16_10 \ + } +// You can also use "add_black_boxes -auto" to black box all undefined modules but +// it is recommended that you do not add this command to your dofile. Doing so may +// unintentionally black-box new undefined modules in future runs. +// Warning: 32 cases: Unused net in DFT library model +// Warning: 110 cases: Undriven net in netlist module +// Warning: 1 case: Floating input on instance in netlist +// Warning: 47 cases: Net in netlist not connected +// Note: Issue set_current_design with the -show_elaboration_warnings option to see more details about previous warnings +// Design elaboration successful. +// Reading SDC file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.02/Scan_0/oasys.sdc ... +// Finished reading SDC file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.02/Scan_0/oasys.sdc. +// Read SDC summary: 1 false path, 0 multi-cycle paths, 0 erroneous paths +// 0 disable timings, 0 case analysis, 0 clock groups +// sub-command: set_current_design cpu -show_elaboration_warnings +// Warning: Undefined modules were found. +// Before using "set_system_mode" or "create_flat_model", you must either define +// the missing modules using "read_verilog" and/or "read_cell_library", or use the +// following command to treat them as black boxes: + add_black_boxes -modules { \ + MemGen_16_10 \ + } +// You can also use "add_black_boxes -auto" to black box all undefined modules but +// it is recommended that you do not add this command to your dofile. Doing so may +// unintentionally black-box new undefined modules in future runs. +// Warning: Net 'SO_1' in module 'cpu' is not driven +// Warning: Net 'SO_2' in module 'cpu' is not driven +// Warning: Net 'SO_3' in module 'cpu' is not driven +// Warning: Net 'SO_4' in module 'cpu' is not driven +// Warning: Net 'DAddr[31]' in module 'cpu' has no pins +// Warning: Net 'DAddr[30]' in module 'cpu' has no pins +// Warning: Net 'DAddr[29]' in module 'cpu' has no pins +// Warning: Net 'DAddr[28]' in module 'cpu' has no pins +// Warning: Net 'DAddr[27]' in module 'cpu' has no pins +// Warning: Net 'DAddr[26]' in module 'cpu' has no pins +// Warning: Net 'DAddr[25]' in module 'cpu' has no pins +// Warning: Net 'DAddr[24]' in module 'cpu' has no pins +// Warning: Net 'DAddr[23]' in module 'cpu' has no pins +// Warning: Net 'DAddr[22]' in module 'cpu' has no pins +// Warning: Net 'DAddr[21]' in module 'cpu' has no pins +// Warning: Net 'DAddr[20]' in module 'cpu' has no pins +// Warning: Net 'DAddr[19]' in module 'cpu' has no pins +// Warning: Net 'DAddr[18]' in module 'cpu' has no pins +// Warning: Net 'DAddr[17]' in module 'cpu' has no pins +// Warning: Net 'DAddr[16]' in module 'cpu' has no pins +// Warning: Net 'DAddr[15]' in module 'cpu' has no pins +// Warning: Net 'DAddr[14]' in module 'cpu' has no pins +// Warning: Net 'DAddr[13]' in module 'cpu' has no pins +// Warning: Net 'NextPC[31]' in module 'cpu' has no pins +// Warning: Net 'NextPC[30]' in module 'cpu' has no pins +// Warning: Net 'NextPC[29]' in module 'cpu' has no pins +// Warning: Net 'NextPC[28]' in module 'cpu' has no pins +// Warning: Net 'NextPC[27]' in module 'cpu' has no pins +// Warning: Net 'NextPC[26]' in module 'cpu' has no pins +// Warning: Net 'NextPC[25]' in module 'cpu' has no pins +// Warning: Net 'NextPC[24]' in module 'cpu' has no pins +// Warning: Net 'NextPC[23]' in module 'cpu' has no pins +// Warning: Net 'NextPC[22]' in module 'cpu' has no pins +// Warning: Net 'NextPC[21]' in module 'cpu' has no pins +// Warning: Net 'NextPC[20]' in module 'cpu' has no pins +// Warning: Net 'NextPC[19]' in module 'cpu' has no pins +// Warning: Net 'NextPC[18]' in module 'cpu' has no pins +// Warning: Net 'NextPC[17]' in module 'cpu' has no pins +// Warning: Net 'NextPC[16]' in module 'cpu' has no pins +// Warning: Net 'NextPC[15]' in module 'cpu' has no pins +// Warning: Net 'NextPC[14]' in module 'cpu' has no pins +// Warning: Net 'NextPC[13]' in module 'cpu' has no pins +// Warning: Net 'NextPC[7]' in module 'cpu' has no pins +// Warning: Net 'NextPC[6]' in module 'cpu' has no pins +// Warning: Net 'NextPC[5]' in module 'cpu' has no pins +// Warning: Net 'NextPC[4]' in module 'cpu' has no pins +// Warning: Net 'NextPC[3]' in module 'cpu' has no pins +// Warning: Net 'NextPC[2]' in module 'cpu' has no pins +// Warning: Net 'NextPC[1]' in module 'cpu' has no pins +// Warning: Net 'NextPC[0]' in module 'cpu' has no pins +// Warning: Net 'uc_0' in module 'cpu' is not driven +// Warning: Net 'uc_1' in module 'cpu' is not driven +// Warning: Net 'uc_2' in module 'cpu' is not driven +// Warning: Net 'uc_3' in module 'cpu' is not driven +// Warning: Net 'uc_4' in module 'cpu' is not driven +// Warning: Net 'uc_5' in module 'cpu' is not driven +// Warning: Net 'uc_6' in module 'cpu' is not driven +// Warning: Net 'uc_7' in module 'cpu' is not driven +// Warning: Net 'uc_8' in module 'cpu' is not driven +// Warning: Net 'uc_9' in module 'cpu' is not driven +// Warning: Net 'uc_10' in module 'cpu' is not driven +// Warning: Net 'uc_11' in module 'cpu' is not driven +// Warning: Net 'uc_12' in module 'cpu' is not driven +// Warning: Net 'uc_13' in module 'cpu' is not driven +// Warning: Net 'uc_14' in module 'cpu' is not driven +// Warning: Net 'uc_15' in module 'cpu' is not driven +// Warning: Net 'uc_16' in module 'cpu' is not driven +// Warning: Net 'uc_17' in module 'cpu' is not driven +// Warning: Net 'uc_18' in module 'cpu' is not driven +// Warning: Net 'uc_19' in module 'cpu' is not driven +// Warning: Net 'uc_20' in module 'cpu' is not driven +// Warning: Net 'uc_21' in module 'cpu' is not driven +// Warning: Net 'uc_22' in module 'cpu' is not driven +// Warning: Net 'uc_23' in module 'cpu' is not driven +// Warning: Net 'uc_24' in module 'cpu' is not driven +// Warning: Net 'uc_25' in module 'cpu' is not driven +// Warning: Net 'uc_26' in module 'cpu' is not driven +// Warning: Net 'uc_27' in module 'cpu' is not driven +// Warning: Net 'uc_28' in module 'cpu' is not driven +// Warning: Net 'uc_29' in module 'cpu' is not driven +// Warning: Net 'uc_30' in module 'cpu' is not driven +// Warning: Net 'uc_31' in module 'cpu' is not driven +// Warning: Net 'uc_32' in module 'cpu' is not driven +// Warning: Net 'uc_33' in module 'cpu' is not driven +// Warning: Net 'uc_34' in module 'cpu' is not driven +// Warning: Net 'uc_35' in module 'cpu' is not driven +// Warning: Net 'uc_36' in module 'cpu' is not driven +// Warning: Net 'uc_37' in module 'cpu' is not driven +// Warning: Net 'uc_38' in module 'cpu' is not driven +// Warning: Net 'uc_39' in module 'cpu' is not driven +// Warning: Floating input 'chip_en' at instance 'RAM' in module 'main_mem' +// Warning: Net 'mem_sel[1]' in module 'MemGen_32_11' has no pins +// Warning: Net 'DAddr[31]' in module 'decoder' is not driven +// Warning: Net 'DAddr[30]' in module 'decoder' is not driven +// Warning: Net 'DAddr[29]' in module 'decoder' is not driven +// Warning: Net 'DAddr[28]' in module 'decoder' is not driven +// Warning: Net 'DAddr[27]' in module 'decoder' is not driven +// Warning: Net 'DAddr[26]' in module 'decoder' is not driven +// Warning: Net 'DAddr[25]' in module 'decoder' is not driven +// Warning: Net 'DAddr[24]' in module 'decoder' is not driven +// Warning: Net 'DAddr[23]' in module 'decoder' is not driven +// Warning: Net 'DAddr[22]' in module 'decoder' is not driven +// Warning: Net 'DAddr[21]' in module 'decoder' is not driven +// Warning: Net 'DAddr[20]' in module 'decoder' is not driven +// Warning: Net 'DAddr[19]' in module 'decoder' is not driven +// Warning: Net 'DAddr[18]' in module 'decoder' is not driven +// Warning: Net 'DAddr[17]' in module 'decoder' is not driven +// Warning: Net 'DAddr[16]' in module 'decoder' is not driven +// Warning: Net 'DAddr[15]' in module 'decoder' is not driven +// Warning: Net 'DAddr[14]' in module 'decoder' is not driven +// Warning: Net 'DAddr[13]' in module 'decoder' is not driven +// Warning: Net 'WData[31]' in module 'decoder' is not driven +// Warning: Net 'WData[30]' in module 'decoder' is not driven +// Warning: Net 'WData[29]' in module 'decoder' is not driven +// Warning: Net 'WData[28]' in module 'decoder' is not driven +// Warning: Net 'WData[27]' in module 'decoder' is not driven +// Warning: Net 'WData[26]' in module 'decoder' is not driven +// Warning: Net 'WData[25]' in module 'decoder' is not driven +// Warning: Net 'WData[24]' in module 'decoder' is not driven +// Warning: Net 'WData[23]' in module 'decoder' is not driven +// Warning: Net 'WData[22]' in module 'decoder' is not driven +// Warning: Net 'WData[21]' in module 'decoder' is not driven +// Warning: Net 'WData[20]' in module 'decoder' is not driven +// Warning: Net 'WData[19]' in module 'decoder' is not driven +// Warning: Net 'WData[18]' in module 'decoder' is not driven +// Warning: Net 'WData[17]' in module 'decoder' is not driven +// Warning: Net 'WData[16]' in module 'decoder' is not driven +// Warning: Net 'WData[15]' in module 'decoder' is not driven +// Warning: Net 'WData[14]' in module 'decoder' is not driven +// Warning: Net 'WData[13]' in module 'decoder' is not driven +// Warning: Net 'WData[12]' in module 'decoder' is not driven +// Warning: Net 'WData[11]' in module 'decoder' is not driven +// Warning: Net 'WData[10]' in module 'decoder' is not driven +// Warning: Net 'WData[9]' in module 'decoder' is not driven +// Warning: Net 'WData[8]' in module 'decoder' is not driven +// Warning: Net 'WData[7]' in module 'decoder' is not driven +// Warning: Net 'WData[6]' in module 'decoder' is not driven +// Warning: Net 'WData[5]' in module 'decoder' is not driven +// Warning: Net 'WData[4]' in module 'decoder' is not driven +// Warning: Net 'WData[3]' in module 'decoder' is not driven +// Warning: Net 'WData[2]' in module 'decoder' is not driven +// Warning: Net 'WData[1]' in module 'decoder' is not driven +// Warning: Net 'WData[0]' in module 'decoder' is not driven +// Warning: Net 'Rs1[4]' in module 'decoder' is not driven +// Warning: Net 'Rs1[3]' in module 'decoder' is not driven +// Warning: Net 'Rs1[2]' in module 'decoder' is not driven +// Warning: Net 'Rs1[1]' in module 'decoder' is not driven +// Warning: Net 'Rs1[0]' in module 'decoder' is not driven +// Warning: Net 'Rs2[4]' in module 'decoder' is not driven +// Warning: Net 'Rs2[3]' in module 'decoder' is not driven +// Warning: Net 'Rs2[2]' in module 'decoder' is not driven +// Warning: Net 'Rs2[1]' in module 'decoder' is not driven +// Warning: Net 'Rs2[0]' in module 'decoder' is not driven +// Warning: Net 'Rd[4]' in module 'decoder' is not driven +// Warning: Net 'Rd[3]' in module 'decoder' is not driven +// Warning: Net 'Rd[2]' in module 'decoder' is not driven +// Warning: Net 'Rd[1]' in module 'decoder' is not driven +// Warning: Net 'Rd[0]' in module 'decoder' is not driven +// sub-command: set_design_level physical_block +// sub-command: set_shift_register_identification off +// sub-command: add_nonscan_instances -instances "{/theMem/\IRData_reg[31] } {/theMem/\IRData_reg[30] } {/theMem/\IRData_reg[29] } {/theMem/\IRData_reg[28] } {/theMem/\IRData_reg[27] } {/theMem/\IRData_reg[26] } {/theMem/\IRData_reg[25] } {/theMem/\IRData_reg[24] } {/theMem/\IRData_reg[23] } {/theMem/\IRData_reg[22] } {/theMem/\IRData_reg[21] } {/theMem/\IRData_reg[20] } {/theMem/\IRData_reg[19] } {/theMem/\IRData_reg[18] } {/theMem/\IRData_reg[17] } {/theMem/\IRData_reg[16] } {/theMem/\IRData_reg[15] } {/theMem/\IRData_reg[14] } {/theMem/\IRData_reg[13] } {/theMem/\IRData_reg[12] } {/theMem/\IRData_reg[11] } {/theMem/\IRData_reg[10] } {/theMem/\IRData_reg[9] } {/theMem/\IRData_reg[8] } {/theMem/\IRData_reg[7] } {/theMem/\IRData_reg[6] } {/theMem/\IRData_reg[5] } {/theMem/\IRData_reg[4] } {/theMem/\IRData_reg[3] } {/theMem/\IRData_reg[2] } {/theMem/\IRData_reg[1] } {/theMem/\IRData_reg[0] } {/theMem/\mem_addr_reg[10] } {/theMem/\mem_addr_reg[9] } {/theMem/\mem_addr_reg[8] } {/theMem/\mem_addr_reg[7] } {/theMem/\mem_addr_reg[6] } {/theMem/\mem_addr_reg[5] } {/theMem/\mem_addr_reg[4] } {/theMem/\mem_addr_reg[3] } {/theMem/\mem_addr_reg[2] } {/theMem/\mem_addr_reg[1] } {/theMem/\mem_addr_reg[0] } {/theMem/\drTmp_reg[31] } {/theMem/\drTmp_reg[30] } {/theMem/\drTmp_reg[29] } {/theMem/\drTmp_reg[28] } {/theMem/\drTmp_reg[27] } {/theMem/\drTmp_reg[26] } {/theMem/\drTmp_reg[25] } {/theMem/\drTmp_reg[24] } {/theMem/\drTmp_reg[23] } {/theMem/\drTmp_reg[22] } {/theMem/\drTmp_reg[21] } {/theMem/\drTmp_reg[20] } {/theMem/\drTmp_reg[19] } {/theMem/\drTmp_reg[18] } {/theMem/\drTmp_reg[17] } {/theMem/\drTmp_reg[16] } {/theMem/\drTmp_reg[15] } {/theMem/\drTmp_reg[14] } {/theMem/\drTmp_reg[13] } {/theMem/\drTmp_reg[12] } {/theMem/\drTmp_reg[11] } {/theMem/\drTmp_reg[10] } {/theMem/\drTmp_reg[9] } {/theMem/\drTmp_reg[8] } {/theMem/\drTmp_reg[7] } {/theMem/\drTmp_reg[6] } {/theMem/\drTmp_reg[5] } {/theMem/\drTmp_reg[4] } {/theMem/\drTmp_reg[3] } {/theMem/\drTmp_reg[2] } {/theMem/\drTmp_reg[1] } {/theMem/\drTmp_reg[0] } {/theMem/\mem_wdata_reg[31] } {/theMem/\mem_wdata_reg[30] } {/theMem/\mem_wdata_reg[29] } {/theMem/\mem_wdata_reg[28] } {/theMem/\mem_wdata_reg[27] } {/theMem/\mem_wdata_reg[26] } {/theMem/\mem_wdata_reg[25] } {/theMem/\mem_wdata_reg[24] } {/theMem/\mem_wdata_reg[23] } {/theMem/\mem_wdata_reg[22] } {/theMem/\mem_wdata_reg[21] } {/theMem/\mem_wdata_reg[20] } {/theMem/\mem_wdata_reg[19] } {/theMem/\mem_wdata_reg[18] } {/theMem/\mem_wdata_reg[17] } {/theMem/\mem_wdata_reg[16] } {/theMem/\mem_wdata_reg[15] } {/theMem/\mem_wdata_reg[14] } {/theMem/\mem_wdata_reg[13] } {/theMem/\mem_wdata_reg[12] } {/theMem/\mem_wdata_reg[11] } {/theMem/\mem_wdata_reg[10] } {/theMem/\mem_wdata_reg[9] } {/theMem/\mem_wdata_reg[8] } {/theMem/\mem_wdata_reg[7] } {/theMem/\mem_wdata_reg[6] } {/theMem/\mem_wdata_reg[5] } {/theMem/\mem_wdata_reg[4] } {/theMem/\mem_wdata_reg[3] } {/theMem/\mem_wdata_reg[2] } {/theMem/\mem_wdata_reg[1] } {/theMem/\mem_wdata_reg[0] } " +// sub-command: add_clocks 0 " clk_25mhz " +// sub-command: set_scan_enable scan_en -active high +// sub-command: add_input_constraints btn[0] -C1 +// sub-command: set_scan_enable scan_en -active high -cluster_name scanChain_1 +// sub-command: set_scan_enable scan_en -active high -cluster_name scanChain_2 +// sub-command: set_scan_enable scan_en -active high -cluster_name scanChain_3 +// sub-command: set_scan_enable scan_en -active high -cluster_name scanChain_4 +// sub-command: add_black_boxes -modules " MemGen_16_10 " +// sub-command: set_scan_insertion_options -single_clock_edge_chains on -si_port_format oas_ts_si[%d] -so_port_format oas_ts_so[%d] +// sub-command: set_system_mode analysis +// Warning: Rule FN1 violation occurs 157 times +// Warning: Rule FP13 violation occurs 1 times +// Flattening process completed, cell instances=4379, gates=18234, PIs=13, POs=12, CPU time=0.09 sec. +// --------------------------------------------------------------------------- +// Begin circuit learning analyses. +// -------------------------------- +// Learning completed, CPU time=0.01 sec. +// --------------------------------------------------------------------------- +// Begin scan chain identification process, memory elements = 1194, +// sequential library cells = 1194. +// --------------------------------------------------------------------------- +// Warning: Model 'DLH_X1_LVT' has no muxscan scan equivalent and is treated as nonscan model +// ------------------------------------------------------------------------------ +// 170 sequential library cells are treated as non-scan. +// ------------------------------------------------------------------------------ +// 63 sequential library cells missing mux-scan equivalent. +// 107 sequential library cells defined non-scan. +// --------------------------------------------------------------------------- +// Begin scannability rules checking for 1024 sequential library cells. +// --------------------------------------------------------------------------- +// 1024 sequential library cells identified as scannable. +// --------------------------------------------------------------------------- +// Begin transparent latch checking for 63 latches. +// --------------------------------------------------------------------------- +// Warning: 32 latches not transparent due to uncontrollable. (D6) +// Number transparent latches = 31. +// --------------------------------------------------------------------------- +// Begin scan clock rules checking. +// --------------------------------------------------------------------------- +// 1 scan clock/set/reset lines have been identified. +// All scan clocks successfully passed off-state check. +// 1131 sequential cells passed clock stability checking. +// There were 43 clock rule C3 fails (clock may capture data affected by its captured data). +// Note: Trailing edge triggered device can capture data affected by leading edge. +// --------------------------------------------------------------------------- +// 170 non-scan memory elements are identified. +// --------------------------------------------------------------------------- +// 32 non-scan memory elements are identified as TIE-X. (D5) +// 107 non-scan memory elements are identified as INIT-X. (D5) +// 31 non-scan memory elements are identified as TLA. (D5) +// --------------------------------------------------------------------------- +// Number of targeted sequential library cells = 1024 +// Warning: The tool may require a shift-capture clock during insertion, +// but no 'shift_capture_clock' DFT signal was identified +// and no TCLK source was specified using the command 'set_scan_signals -tclk'. +// Note: The system clock 'clk_25mhz' will be used as the shift-capture clock, if needed. +// sub-command: report_drc_rules +C3: #fails=43 handling=note (clock may capture data affected by its captured data) +D5: #fails=170 handling=warning (non-scan memory element) +D6: #fails=32 handling=warning (non-transparent non-scan latches) +// sub-command: create_scan_chain_family scanChain_1 -include_elements "{/\thePC_CurrentPC_reg[0] } {/\thePC_CurrentPC_reg[10] } {/\thePC_CurrentPC_reg[11] } {/\thePC_CurrentPC_reg[12] } {/\thePC_CurrentPC_reg[13] } {/\thePC_CurrentPC_reg[14] } {/\thePC_CurrentPC_reg[15] } {/\thePC_CurrentPC_reg[16] } {/\thePC_CurrentPC_reg[17] } {/\thePC_CurrentPC_reg[18] } {/\thePC_CurrentPC_reg[19] } {/\thePC_CurrentPC_reg[1] } {/\thePC_CurrentPC_reg[20] } {/\thePC_CurrentPC_reg[21] } {/\thePC_CurrentPC_reg[22] } {/\thePC_CurrentPC_reg[23] } {/\thePC_CurrentPC_reg[24] } {/\thePC_CurrentPC_reg[25] } {/\thePC_CurrentPC_reg[26] } {/\thePC_CurrentPC_reg[27] } {/\thePC_CurrentPC_reg[28] } {/\thePC_CurrentPC_reg[29] } {/\thePC_CurrentPC_reg[2] } {/\thePC_CurrentPC_reg[30] } {/\thePC_CurrentPC_reg[31] } {/\thePC_CurrentPC_reg[3] } {/\thePC_CurrentPC_reg[4] } {/\thePC_CurrentPC_reg[5] } {/\thePC_CurrentPC_reg[6] } {/\thePC_CurrentPC_reg[7] } {/\thePC_CurrentPC_reg[8] } {/\thePC_CurrentPC_reg[9] } {/theRegisters/\registers_reg[10][0] } {/theRegisters/\registers_reg[10][10] } {/theRegisters/\registers_reg[10][11] } {/theRegisters/\registers_reg[10][12] } {/theRegisters/\registers_reg[10][13] } {/theRegisters/\registers_reg[10][14] } {/theRegisters/\registers_reg[10][15] } {/theRegisters/\registers_reg[10][16] } {/theRegisters/\registers_reg[10][17] } {/theRegisters/\registers_reg[10][18] } {/theRegisters/\registers_reg[10][19] } {/theRegisters/\registers_reg[10][1] } {/theRegisters/\registers_reg[10][20] } {/theRegisters/\registers_reg[10][21] } {/theRegisters/\registers_reg[10][22] } {/theRegisters/\registers_reg[10][23] } {/theRegisters/\registers_reg[10][24] } {/theRegisters/\registers_reg[10][25] } {/theRegisters/\registers_reg[10][26] } {/theRegisters/\registers_reg[10][27] } {/theRegisters/\registers_reg[10][28] } {/theRegisters/\registers_reg[10][29] } {/theRegisters/\registers_reg[10][2] } {/theRegisters/\registers_reg[10][30] } {/theRegisters/\registers_reg[10][31] } {/theRegisters/\registers_reg[10][3] } {/theRegisters/\registers_reg[10][4] } {/theRegisters/\registers_reg[10][5] } {/theRegisters/\registers_reg[10][6] } {/theRegisters/\registers_reg[10][7] } {/theRegisters/\registers_reg[10][8] } {/theRegisters/\registers_reg[10][9] } {/theRegisters/\registers_reg[11][0] } {/theRegisters/\registers_reg[11][10] } {/theRegisters/\registers_reg[11][11] } {/theRegisters/\registers_reg[11][12] } {/theRegisters/\registers_reg[11][13] } {/theRegisters/\registers_reg[11][14] } {/theRegisters/\registers_reg[11][15] } {/theRegisters/\registers_reg[11][16] } {/theRegisters/\registers_reg[11][17] } {/theRegisters/\registers_reg[11][18] } {/theRegisters/\registers_reg[11][19] } {/theRegisters/\registers_reg[11][1] } {/theRegisters/\registers_reg[11][20] } {/theRegisters/\registers_reg[11][21] } {/theRegisters/\registers_reg[11][22] } {/theRegisters/\registers_reg[11][23] } {/theRegisters/\registers_reg[11][24] } {/theRegisters/\registers_reg[11][25] } {/theRegisters/\registers_reg[11][26] } {/theRegisters/\registers_reg[11][27] } {/theRegisters/\registers_reg[11][28] } {/theRegisters/\registers_reg[11][29] } {/theRegisters/\registers_reg[11][2] } {/theRegisters/\registers_reg[11][30] } {/theRegisters/\registers_reg[11][31] } {/theRegisters/\registers_reg[11][3] } {/theRegisters/\registers_reg[11][4] } {/theRegisters/\registers_reg[11][5] } {/theRegisters/\registers_reg[11][6] } {/theRegisters/\registers_reg[11][7] } {/theRegisters/\registers_reg[11][8] } {/theRegisters/\registers_reg[11][9] } {/theRegisters/\registers_reg[12][0] } {/theRegisters/\registers_reg[12][10] } {/theRegisters/\registers_reg[12][11] } {/theRegisters/\registers_reg[12][12] } {/theRegisters/\registers_reg[12][13] } {/theRegisters/\registers_reg[12][14] } {/theRegisters/\registers_reg[12][15] } {/theRegisters/\registers_reg[12][16] } {/theRegisters/\registers_reg[12][17] } {/theRegisters/\registers_reg[12][18] } {/theRegisters/\registers_reg[12][19] } {/theRegisters/\registers_reg[12][1] } {/theRegisters/\registers_reg[12][20] } {/theRegisters/\registers_reg[12][21] } {/theRegisters/\registers_reg[12][22] } {/theRegisters/\registers_reg[12][23] } {/theRegisters/\registers_reg[12][24] } {/theRegisters/\registers_reg[12][25] } {/theRegisters/\registers_reg[12][26] } {/theRegisters/\registers_reg[12][27] } {/theRegisters/\registers_reg[12][28] } {/theRegisters/\registers_reg[12][29] } {/theRegisters/\registers_reg[12][2] } {/theRegisters/\registers_reg[12][30] } {/theRegisters/\registers_reg[12][31] } {/theRegisters/\registers_reg[12][3] } {/theRegisters/\registers_reg[12][4] } {/theRegisters/\registers_reg[12][5] } {/theRegisters/\registers_reg[12][6] } {/theRegisters/\registers_reg[12][7] } {/theRegisters/\registers_reg[12][8] } {/theRegisters/\registers_reg[12][9] } {/theRegisters/\registers_reg[13][0] } {/theRegisters/\registers_reg[13][10] } {/theRegisters/\registers_reg[13][11] } {/theRegisters/\registers_reg[13][12] } {/theRegisters/\registers_reg[13][13] } {/theRegisters/\registers_reg[13][14] } {/theRegisters/\registers_reg[13][15] } {/theRegisters/\registers_reg[13][16] } {/theRegisters/\registers_reg[13][17] } {/theRegisters/\registers_reg[13][18] } {/theRegisters/\registers_reg[13][19] } {/theRegisters/\registers_reg[13][1] } {/theRegisters/\registers_reg[13][20] } {/theRegisters/\registers_reg[13][21] } {/theRegisters/\registers_reg[13][22] } {/theRegisters/\registers_reg[13][23] } {/theRegisters/\registers_reg[13][24] } {/theRegisters/\registers_reg[13][25] } {/theRegisters/\registers_reg[13][26] } {/theRegisters/\registers_reg[13][27] } {/theRegisters/\registers_reg[13][28] } {/theRegisters/\registers_reg[13][29] } {/theRegisters/\registers_reg[13][2] } {/theRegisters/\registers_reg[13][30] } {/theRegisters/\registers_reg[13][31] } {/theRegisters/\registers_reg[13][3] } {/theRegisters/\registers_reg[13][4] } {/theRegisters/\registers_reg[13][5] } {/theRegisters/\registers_reg[13][6] } {/theRegisters/\registers_reg[13][7] } {/theRegisters/\registers_reg[13][8] } {/theRegisters/\registers_reg[13][9] } {/theRegisters/\registers_reg[14][0] } {/theRegisters/\registers_reg[14][10] } {/theRegisters/\registers_reg[14][11] } {/theRegisters/\registers_reg[14][12] } {/theRegisters/\registers_reg[14][13] } {/theRegisters/\registers_reg[14][14] } {/theRegisters/\registers_reg[14][15] } {/theRegisters/\registers_reg[14][16] } {/theRegisters/\registers_reg[14][17] } {/theRegisters/\registers_reg[14][18] } {/theRegisters/\registers_reg[14][19] } {/theRegisters/\registers_reg[14][1] } {/theRegisters/\registers_reg[14][20] } {/theRegisters/\registers_reg[14][21] } {/theRegisters/\registers_reg[14][22] } {/theRegisters/\registers_reg[14][23] } {/theRegisters/\registers_reg[14][24] } {/theRegisters/\registers_reg[14][25] } {/theRegisters/\registers_reg[14][26] } {/theRegisters/\registers_reg[14][27] } {/theRegisters/\registers_reg[14][28] } {/theRegisters/\registers_reg[14][29] } {/theRegisters/\registers_reg[14][2] } {/theRegisters/\registers_reg[14][30] } {/theRegisters/\registers_reg[14][31] } {/theRegisters/\registers_reg[14][3] } {/theRegisters/\registers_reg[14][4] } {/theRegisters/\registers_reg[14][5] } {/theRegisters/\registers_reg[14][6] } {/theRegisters/\registers_reg[14][7] } {/theRegisters/\registers_reg[14][8] } {/theRegisters/\registers_reg[14][9] } {/theRegisters/\registers_reg[15][0] } {/theRegisters/\registers_reg[15][10] } {/theRegisters/\registers_reg[15][11] } {/theRegisters/\registers_reg[15][12] } {/theRegisters/\registers_reg[15][13] } {/theRegisters/\registers_reg[15][14] } {/theRegisters/\registers_reg[15][15] } {/theRegisters/\registers_reg[15][16] } {/theRegisters/\registers_reg[15][17] } {/theRegisters/\registers_reg[15][18] } {/theRegisters/\registers_reg[15][19] } {/theRegisters/\registers_reg[15][1] } {/theRegisters/\registers_reg[15][20] } {/theRegisters/\registers_reg[15][21] } {/theRegisters/\registers_reg[15][22] } {/theRegisters/\registers_reg[15][23] } {/theRegisters/\registers_reg[15][24] } {/theRegisters/\registers_reg[15][25] } {/theRegisters/\registers_reg[15][26] } {/theRegisters/\registers_reg[15][27] } {/theRegisters/\registers_reg[15][28] } {/theRegisters/\registers_reg[15][29] } {/theRegisters/\registers_reg[15][2] } {/theRegisters/\registers_reg[15][30] } {/theRegisters/\registers_reg[15][31] } {/theRegisters/\registers_reg[15][3] } {/theRegisters/\registers_reg[15][4] } {/theRegisters/\registers_reg[15][5] } {/theRegisters/\registers_reg[15][6] } {/theRegisters/\registers_reg[15][7] } {/theRegisters/\registers_reg[15][8] } {/theRegisters/\registers_reg[15][9] } {/theRegisters/\registers_reg[16][0] } {/theRegisters/\registers_reg[16][10] } {/theRegisters/\registers_reg[16][11] } {/theRegisters/\registers_reg[16][12] } {/theRegisters/\registers_reg[16][13] } {/theRegisters/\registers_reg[16][14] } {/theRegisters/\registers_reg[16][15] } {/theRegisters/\registers_reg[16][16] } {/theRegisters/\registers_reg[16][17] } {/theRegisters/\registers_reg[16][18] } {/theRegisters/\registers_reg[16][19] } {/theRegisters/\registers_reg[16][1] } {/theRegisters/\registers_reg[16][20] } {/theRegisters/\registers_reg[16][21] } {/theRegisters/\registers_reg[16][22] } {/theRegisters/\registers_reg[16][23] } {/theRegisters/\registers_reg[16][24] } {/theRegisters/\registers_reg[16][25] } {/theRegisters/\registers_reg[16][26] } {/theRegisters/\registers_reg[16][27] } {/theRegisters/\registers_reg[16][28] } {/theRegisters/\registers_reg[16][29] } {/theRegisters/\registers_reg[16][2] } {/theRegisters/\registers_reg[16][30] } {/theRegisters/\registers_reg[16][31] } {/theRegisters/\registers_reg[16][3] } {/theRegisters/\registers_reg[16][4] } {/theRegisters/\registers_reg[16][5] } {/theRegisters/\registers_reg[16][6] } {/theRegisters/\registers_reg[16][7] } {/theRegisters/\registers_reg[16][8] } {/theRegisters/\registers_reg[16][9] } " -si_connections "SI_1 " -so_connections "SO_1 " -chain_count 1 +// sub-command: create_scan_chain_family scanChain_2 -include_elements "{/theRegisters/\registers_reg[17][0] } {/theRegisters/\registers_reg[17][10] } {/theRegisters/\registers_reg[17][11] } {/theRegisters/\registers_reg[17][12] } {/theRegisters/\registers_reg[17][13] } {/theRegisters/\registers_reg[17][14] } {/theRegisters/\registers_reg[17][15] } {/theRegisters/\registers_reg[17][16] } {/theRegisters/\registers_reg[17][17] } {/theRegisters/\registers_reg[17][18] } {/theRegisters/\registers_reg[17][19] } {/theRegisters/\registers_reg[17][1] } {/theRegisters/\registers_reg[17][20] } {/theRegisters/\registers_reg[17][21] } {/theRegisters/\registers_reg[17][22] } {/theRegisters/\registers_reg[17][23] } {/theRegisters/\registers_reg[17][24] } {/theRegisters/\registers_reg[17][25] } {/theRegisters/\registers_reg[17][26] } {/theRegisters/\registers_reg[17][27] } {/theRegisters/\registers_reg[17][28] } {/theRegisters/\registers_reg[17][29] } {/theRegisters/\registers_reg[17][2] } {/theRegisters/\registers_reg[17][30] } {/theRegisters/\registers_reg[17][31] } {/theRegisters/\registers_reg[17][3] } {/theRegisters/\registers_reg[17][4] } {/theRegisters/\registers_reg[17][5] } {/theRegisters/\registers_reg[17][6] } {/theRegisters/\registers_reg[17][7] } {/theRegisters/\registers_reg[17][8] } {/theRegisters/\registers_reg[17][9] } {/theRegisters/\registers_reg[18][0] } {/theRegisters/\registers_reg[18][10] } {/theRegisters/\registers_reg[18][11] } {/theRegisters/\registers_reg[18][12] } {/theRegisters/\registers_reg[18][13] } {/theRegisters/\registers_reg[18][14] } {/theRegisters/\registers_reg[18][15] } {/theRegisters/\registers_reg[18][16] } {/theRegisters/\registers_reg[18][17] } {/theRegisters/\registers_reg[18][18] } {/theRegisters/\registers_reg[18][19] } {/theRegisters/\registers_reg[18][1] } {/theRegisters/\registers_reg[18][20] } {/theRegisters/\registers_reg[18][21] } {/theRegisters/\registers_reg[18][22] } {/theRegisters/\registers_reg[18][23] } {/theRegisters/\registers_reg[18][24] } {/theRegisters/\registers_reg[18][25] } {/theRegisters/\registers_reg[18][26] } {/theRegisters/\registers_reg[18][27] } {/theRegisters/\registers_reg[18][28] } {/theRegisters/\registers_reg[18][29] } {/theRegisters/\registers_reg[18][2] } {/theRegisters/\registers_reg[18][30] } {/theRegisters/\registers_reg[18][31] } {/theRegisters/\registers_reg[18][3] } {/theRegisters/\registers_reg[18][4] } {/theRegisters/\registers_reg[18][5] } {/theRegisters/\registers_reg[18][6] } {/theRegisters/\registers_reg[18][7] } {/theRegisters/\registers_reg[18][8] } {/theRegisters/\registers_reg[18][9] } {/theRegisters/\registers_reg[19][0] } {/theRegisters/\registers_reg[19][10] } {/theRegisters/\registers_reg[19][11] } {/theRegisters/\registers_reg[19][12] } {/theRegisters/\registers_reg[19][13] } {/theRegisters/\registers_reg[19][14] } {/theRegisters/\registers_reg[19][15] } {/theRegisters/\registers_reg[19][16] } {/theRegisters/\registers_reg[19][17] } {/theRegisters/\registers_reg[19][18] } {/theRegisters/\registers_reg[19][19] } {/theRegisters/\registers_reg[19][1] } {/theRegisters/\registers_reg[19][20] } {/theRegisters/\registers_reg[19][21] } {/theRegisters/\registers_reg[19][22] } {/theRegisters/\registers_reg[19][23] } {/theRegisters/\registers_reg[19][24] } {/theRegisters/\registers_reg[19][25] } {/theRegisters/\registers_reg[19][26] } {/theRegisters/\registers_reg[19][27] } {/theRegisters/\registers_reg[19][28] } {/theRegisters/\registers_reg[19][29] } {/theRegisters/\registers_reg[19][2] } {/theRegisters/\registers_reg[19][30] } {/theRegisters/\registers_reg[19][31] } {/theRegisters/\registers_reg[19][3] } {/theRegisters/\registers_reg[19][4] } {/theRegisters/\registers_reg[19][5] } {/theRegisters/\registers_reg[19][6] } {/theRegisters/\registers_reg[19][7] } {/theRegisters/\registers_reg[19][8] } {/theRegisters/\registers_reg[19][9] } {/theRegisters/\registers_reg[1][0] } {/theRegisters/\registers_reg[1][10] } {/theRegisters/\registers_reg[1][11] } {/theRegisters/\registers_reg[1][12] } {/theRegisters/\registers_reg[1][13] } {/theRegisters/\registers_reg[1][14] } {/theRegisters/\registers_reg[1][15] } {/theRegisters/\registers_reg[1][16] } {/theRegisters/\registers_reg[1][17] } {/theRegisters/\registers_reg[1][18] } {/theRegisters/\registers_reg[1][19] } {/theRegisters/\registers_reg[1][1] } {/theRegisters/\registers_reg[1][20] } {/theRegisters/\registers_reg[1][21] } {/theRegisters/\registers_reg[1][22] } {/theRegisters/\registers_reg[1][23] } {/theRegisters/\registers_reg[1][24] } {/theRegisters/\registers_reg[1][25] } {/theRegisters/\registers_reg[1][26] } {/theRegisters/\registers_reg[1][27] } {/theRegisters/\registers_reg[1][28] } {/theRegisters/\registers_reg[1][29] } {/theRegisters/\registers_reg[1][2] } {/theRegisters/\registers_reg[1][30] } {/theRegisters/\registers_reg[1][31] } {/theRegisters/\registers_reg[1][3] } {/theRegisters/\registers_reg[1][4] } {/theRegisters/\registers_reg[1][5] } {/theRegisters/\registers_reg[1][6] } {/theRegisters/\registers_reg[1][7] } {/theRegisters/\registers_reg[1][8] } {/theRegisters/\registers_reg[1][9] } {/theRegisters/\registers_reg[20][0] } {/theRegisters/\registers_reg[20][10] } {/theRegisters/\registers_reg[20][11] } {/theRegisters/\registers_reg[20][12] } {/theRegisters/\registers_reg[20][13] } {/theRegisters/\registers_reg[20][14] } {/theRegisters/\registers_reg[20][15] } {/theRegisters/\registers_reg[20][16] } {/theRegisters/\registers_reg[20][17] } {/theRegisters/\registers_reg[20][18] } {/theRegisters/\registers_reg[20][19] } {/theRegisters/\registers_reg[20][1] } {/theRegisters/\registers_reg[20][20] } {/theRegisters/\registers_reg[20][21] } {/theRegisters/\registers_reg[20][22] } {/theRegisters/\registers_reg[20][23] } {/theRegisters/\registers_reg[20][24] } {/theRegisters/\registers_reg[20][25] } {/theRegisters/\registers_reg[20][26] } {/theRegisters/\registers_reg[20][27] } {/theRegisters/\registers_reg[20][28] } {/theRegisters/\registers_reg[20][29] } {/theRegisters/\registers_reg[20][2] } {/theRegisters/\registers_reg[20][30] } {/theRegisters/\registers_reg[20][31] } {/theRegisters/\registers_reg[20][3] } {/theRegisters/\registers_reg[20][4] } {/theRegisters/\registers_reg[20][5] } {/theRegisters/\registers_reg[20][6] } {/theRegisters/\registers_reg[20][7] } {/theRegisters/\registers_reg[20][8] } {/theRegisters/\registers_reg[20][9] } {/theRegisters/\registers_reg[21][0] } {/theRegisters/\registers_reg[21][10] } {/theRegisters/\registers_reg[21][11] } {/theRegisters/\registers_reg[21][12] } {/theRegisters/\registers_reg[21][13] } {/theRegisters/\registers_reg[21][14] } {/theRegisters/\registers_reg[21][15] } {/theRegisters/\registers_reg[21][16] } {/theRegisters/\registers_reg[21][17] } {/theRegisters/\registers_reg[21][18] } {/theRegisters/\registers_reg[21][19] } {/theRegisters/\registers_reg[21][1] } {/theRegisters/\registers_reg[21][20] } {/theRegisters/\registers_reg[21][21] } {/theRegisters/\registers_reg[21][22] } {/theRegisters/\registers_reg[21][23] } {/theRegisters/\registers_reg[21][24] } {/theRegisters/\registers_reg[21][25] } {/theRegisters/\registers_reg[21][26] } {/theRegisters/\registers_reg[21][27] } {/theRegisters/\registers_reg[21][28] } {/theRegisters/\registers_reg[21][29] } {/theRegisters/\registers_reg[21][2] } {/theRegisters/\registers_reg[21][30] } {/theRegisters/\registers_reg[21][31] } {/theRegisters/\registers_reg[21][3] } {/theRegisters/\registers_reg[21][4] } {/theRegisters/\registers_reg[21][5] } {/theRegisters/\registers_reg[21][6] } {/theRegisters/\registers_reg[21][7] } {/theRegisters/\registers_reg[21][8] } {/theRegisters/\registers_reg[21][9] } {/theRegisters/\registers_reg[22][0] } {/theRegisters/\registers_reg[22][10] } {/theRegisters/\registers_reg[22][11] } {/theRegisters/\registers_reg[22][12] } {/theRegisters/\registers_reg[22][13] } {/theRegisters/\registers_reg[22][14] } {/theRegisters/\registers_reg[22][15] } {/theRegisters/\registers_reg[22][16] } {/theRegisters/\registers_reg[22][17] } {/theRegisters/\registers_reg[22][18] } {/theRegisters/\registers_reg[22][19] } {/theRegisters/\registers_reg[22][1] } {/theRegisters/\registers_reg[22][20] } {/theRegisters/\registers_reg[22][21] } {/theRegisters/\registers_reg[22][22] } {/theRegisters/\registers_reg[22][23] } {/theRegisters/\registers_reg[22][24] } {/theRegisters/\registers_reg[22][25] } {/theRegisters/\registers_reg[22][26] } {/theRegisters/\registers_reg[22][27] } {/theRegisters/\registers_reg[22][28] } {/theRegisters/\registers_reg[22][29] } {/theRegisters/\registers_reg[22][2] } {/theRegisters/\registers_reg[22][30] } {/theRegisters/\registers_reg[22][31] } {/theRegisters/\registers_reg[22][3] } {/theRegisters/\registers_reg[22][4] } {/theRegisters/\registers_reg[22][5] } {/theRegisters/\registers_reg[22][6] } {/theRegisters/\registers_reg[22][7] } {/theRegisters/\registers_reg[22][8] } {/theRegisters/\registers_reg[22][9] } {/theRegisters/\registers_reg[23][0] } {/theRegisters/\registers_reg[23][10] } {/theRegisters/\registers_reg[23][11] } {/theRegisters/\registers_reg[23][12] } {/theRegisters/\registers_reg[23][13] } {/theRegisters/\registers_reg[23][14] } {/theRegisters/\registers_reg[23][15] } {/theRegisters/\registers_reg[23][16] } {/theRegisters/\registers_reg[23][17] } {/theRegisters/\registers_reg[23][18] } {/theRegisters/\registers_reg[23][19] } {/theRegisters/\registers_reg[23][1] } {/theRegisters/\registers_reg[23][20] } {/theRegisters/\registers_reg[23][21] } {/theRegisters/\registers_reg[23][22] } {/theRegisters/\registers_reg[23][23] } {/theRegisters/\registers_reg[23][24] } {/theRegisters/\registers_reg[23][25] } {/theRegisters/\registers_reg[23][26] } {/theRegisters/\registers_reg[23][27] } {/theRegisters/\registers_reg[23][28] } {/theRegisters/\registers_reg[23][29] } {/theRegisters/\registers_reg[23][2] } {/theRegisters/\registers_reg[23][30] } {/theRegisters/\registers_reg[23][31] } {/theRegisters/\registers_reg[23][3] } {/theRegisters/\registers_reg[23][4] } {/theRegisters/\registers_reg[23][5] } {/theRegisters/\registers_reg[23][6] } {/theRegisters/\registers_reg[23][7] } {/theRegisters/\registers_reg[23][8] } {/theRegisters/\registers_reg[23][9] } " -si_connections "SI_2 " -so_connections "SO_2 " -chain_count 1 +// sub-command: create_scan_chain_family scanChain_3 -include_elements "{/theRegisters/\registers_reg[24][0] } {/theRegisters/\registers_reg[24][10] } {/theRegisters/\registers_reg[24][11] } {/theRegisters/\registers_reg[24][12] } {/theRegisters/\registers_reg[24][13] } {/theRegisters/\registers_reg[24][14] } {/theRegisters/\registers_reg[24][15] } {/theRegisters/\registers_reg[24][16] } {/theRegisters/\registers_reg[24][17] } {/theRegisters/\registers_reg[24][18] } {/theRegisters/\registers_reg[24][19] } {/theRegisters/\registers_reg[24][1] } {/theRegisters/\registers_reg[24][20] } {/theRegisters/\registers_reg[24][21] } {/theRegisters/\registers_reg[24][22] } {/theRegisters/\registers_reg[24][23] } {/theRegisters/\registers_reg[24][24] } {/theRegisters/\registers_reg[24][25] } {/theRegisters/\registers_reg[24][26] } {/theRegisters/\registers_reg[24][27] } {/theRegisters/\registers_reg[24][28] } {/theRegisters/\registers_reg[24][29] } {/theRegisters/\registers_reg[24][2] } {/theRegisters/\registers_reg[24][30] } {/theRegisters/\registers_reg[24][31] } {/theRegisters/\registers_reg[24][3] } {/theRegisters/\registers_reg[24][4] } {/theRegisters/\registers_reg[24][5] } {/theRegisters/\registers_reg[24][6] } {/theRegisters/\registers_reg[24][7] } {/theRegisters/\registers_reg[24][8] } {/theRegisters/\registers_reg[24][9] } {/theRegisters/\registers_reg[25][0] } {/theRegisters/\registers_reg[25][10] } {/theRegisters/\registers_reg[25][11] } {/theRegisters/\registers_reg[25][12] } {/theRegisters/\registers_reg[25][13] } {/theRegisters/\registers_reg[25][14] } {/theRegisters/\registers_reg[25][15] } {/theRegisters/\registers_reg[25][16] } {/theRegisters/\registers_reg[25][17] } {/theRegisters/\registers_reg[25][18] } {/theRegisters/\registers_reg[25][19] } {/theRegisters/\registers_reg[25][1] } {/theRegisters/\registers_reg[25][20] } {/theRegisters/\registers_reg[25][21] } {/theRegisters/\registers_reg[25][22] } {/theRegisters/\registers_reg[25][23] } {/theRegisters/\registers_reg[25][24] } {/theRegisters/\registers_reg[25][25] } {/theRegisters/\registers_reg[25][26] } {/theRegisters/\registers_reg[25][27] } {/theRegisters/\registers_reg[25][28] } {/theRegisters/\registers_reg[25][29] } {/theRegisters/\registers_reg[25][2] } {/theRegisters/\registers_reg[25][30] } {/theRegisters/\registers_reg[25][31] } {/theRegisters/\registers_reg[25][3] } {/theRegisters/\registers_reg[25][4] } {/theRegisters/\registers_reg[25][5] } {/theRegisters/\registers_reg[25][6] } {/theRegisters/\registers_reg[25][7] } {/theRegisters/\registers_reg[25][8] } {/theRegisters/\registers_reg[25][9] } {/theRegisters/\registers_reg[26][0] } {/theRegisters/\registers_reg[26][10] } {/theRegisters/\registers_reg[26][11] } {/theRegisters/\registers_reg[26][12] } {/theRegisters/\registers_reg[26][13] } {/theRegisters/\registers_reg[26][14] } {/theRegisters/\registers_reg[26][15] } {/theRegisters/\registers_reg[26][16] } {/theRegisters/\registers_reg[26][17] } {/theRegisters/\registers_reg[26][18] } {/theRegisters/\registers_reg[26][19] } {/theRegisters/\registers_reg[26][1] } {/theRegisters/\registers_reg[26][20] } {/theRegisters/\registers_reg[26][21] } {/theRegisters/\registers_reg[26][22] } {/theRegisters/\registers_reg[26][23] } {/theRegisters/\registers_reg[26][24] } {/theRegisters/\registers_reg[26][25] } {/theRegisters/\registers_reg[26][26] } {/theRegisters/\registers_reg[26][27] } {/theRegisters/\registers_reg[26][28] } {/theRegisters/\registers_reg[26][29] } {/theRegisters/\registers_reg[26][2] } {/theRegisters/\registers_reg[26][30] } {/theRegisters/\registers_reg[26][31] } {/theRegisters/\registers_reg[26][3] } {/theRegisters/\registers_reg[26][4] } {/theRegisters/\registers_reg[26][5] } {/theRegisters/\registers_reg[26][6] } {/theRegisters/\registers_reg[26][7] } {/theRegisters/\registers_reg[26][8] } {/theRegisters/\registers_reg[26][9] } {/theRegisters/\registers_reg[27][0] } {/theRegisters/\registers_reg[27][10] } {/theRegisters/\registers_reg[27][11] } {/theRegisters/\registers_reg[27][12] } {/theRegisters/\registers_reg[27][13] } {/theRegisters/\registers_reg[27][14] } {/theRegisters/\registers_reg[27][15] } {/theRegisters/\registers_reg[27][16] } {/theRegisters/\registers_reg[27][17] } {/theRegisters/\registers_reg[27][18] } {/theRegisters/\registers_reg[27][19] } {/theRegisters/\registers_reg[27][1] } {/theRegisters/\registers_reg[27][20] } {/theRegisters/\registers_reg[27][21] } {/theRegisters/\registers_reg[27][22] } {/theRegisters/\registers_reg[27][23] } {/theRegisters/\registers_reg[27][24] } {/theRegisters/\registers_reg[27][25] } {/theRegisters/\registers_reg[27][26] } {/theRegisters/\registers_reg[27][27] } {/theRegisters/\registers_reg[27][28] } {/theRegisters/\registers_reg[27][29] } {/theRegisters/\registers_reg[27][2] } {/theRegisters/\registers_reg[27][30] } {/theRegisters/\registers_reg[27][31] } {/theRegisters/\registers_reg[27][3] } {/theRegisters/\registers_reg[27][4] } {/theRegisters/\registers_reg[27][5] } {/theRegisters/\registers_reg[27][6] } {/theRegisters/\registers_reg[27][7] } {/theRegisters/\registers_reg[27][8] } {/theRegisters/\registers_reg[27][9] } {/theRegisters/\registers_reg[28][0] } {/theRegisters/\registers_reg[28][10] } {/theRegisters/\registers_reg[28][11] } {/theRegisters/\registers_reg[28][12] } {/theRegisters/\registers_reg[28][13] } {/theRegisters/\registers_reg[28][14] } {/theRegisters/\registers_reg[28][15] } {/theRegisters/\registers_reg[28][16] } {/theRegisters/\registers_reg[28][17] } {/theRegisters/\registers_reg[28][18] } {/theRegisters/\registers_reg[28][19] } {/theRegisters/\registers_reg[28][1] } {/theRegisters/\registers_reg[28][20] } {/theRegisters/\registers_reg[28][21] } {/theRegisters/\registers_reg[28][22] } {/theRegisters/\registers_reg[28][23] } {/theRegisters/\registers_reg[28][24] } {/theRegisters/\registers_reg[28][25] } {/theRegisters/\registers_reg[28][26] } {/theRegisters/\registers_reg[28][27] } {/theRegisters/\registers_reg[28][28] } {/theRegisters/\registers_reg[28][29] } {/theRegisters/\registers_reg[28][2] } {/theRegisters/\registers_reg[28][30] } {/theRegisters/\registers_reg[28][31] } {/theRegisters/\registers_reg[28][3] } {/theRegisters/\registers_reg[28][4] } {/theRegisters/\registers_reg[28][5] } {/theRegisters/\registers_reg[28][6] } {/theRegisters/\registers_reg[28][7] } {/theRegisters/\registers_reg[28][8] } {/theRegisters/\registers_reg[28][9] } {/theRegisters/\registers_reg[29][0] } {/theRegisters/\registers_reg[29][10] } {/theRegisters/\registers_reg[29][11] } {/theRegisters/\registers_reg[29][12] } {/theRegisters/\registers_reg[29][13] } {/theRegisters/\registers_reg[29][14] } {/theRegisters/\registers_reg[29][15] } {/theRegisters/\registers_reg[29][16] } {/theRegisters/\registers_reg[29][17] } {/theRegisters/\registers_reg[29][18] } {/theRegisters/\registers_reg[29][19] } {/theRegisters/\registers_reg[29][1] } {/theRegisters/\registers_reg[29][20] } {/theRegisters/\registers_reg[29][21] } {/theRegisters/\registers_reg[29][22] } {/theRegisters/\registers_reg[29][23] } {/theRegisters/\registers_reg[29][24] } {/theRegisters/\registers_reg[29][25] } {/theRegisters/\registers_reg[29][26] } {/theRegisters/\registers_reg[29][27] } {/theRegisters/\registers_reg[29][28] } {/theRegisters/\registers_reg[29][29] } {/theRegisters/\registers_reg[29][2] } {/theRegisters/\registers_reg[29][30] } {/theRegisters/\registers_reg[29][31] } {/theRegisters/\registers_reg[29][3] } {/theRegisters/\registers_reg[29][4] } {/theRegisters/\registers_reg[29][5] } {/theRegisters/\registers_reg[29][6] } {/theRegisters/\registers_reg[29][7] } {/theRegisters/\registers_reg[29][8] } {/theRegisters/\registers_reg[29][9] } {/theRegisters/\registers_reg[2][0] } {/theRegisters/\registers_reg[2][10] } {/theRegisters/\registers_reg[2][11] } {/theRegisters/\registers_reg[2][12] } {/theRegisters/\registers_reg[2][13] } {/theRegisters/\registers_reg[2][14] } {/theRegisters/\registers_reg[2][15] } {/theRegisters/\registers_reg[2][16] } {/theRegisters/\registers_reg[2][17] } {/theRegisters/\registers_reg[2][18] } {/theRegisters/\registers_reg[2][19] } {/theRegisters/\registers_reg[2][1] } {/theRegisters/\registers_reg[2][20] } {/theRegisters/\registers_reg[2][21] } {/theRegisters/\registers_reg[2][22] } {/theRegisters/\registers_reg[2][23] } {/theRegisters/\registers_reg[2][24] } {/theRegisters/\registers_reg[2][25] } {/theRegisters/\registers_reg[2][26] } {/theRegisters/\registers_reg[2][27] } {/theRegisters/\registers_reg[2][28] } {/theRegisters/\registers_reg[2][29] } {/theRegisters/\registers_reg[2][2] } {/theRegisters/\registers_reg[2][30] } {/theRegisters/\registers_reg[2][31] } {/theRegisters/\registers_reg[2][3] } {/theRegisters/\registers_reg[2][4] } {/theRegisters/\registers_reg[2][5] } {/theRegisters/\registers_reg[2][6] } {/theRegisters/\registers_reg[2][7] } {/theRegisters/\registers_reg[2][8] } {/theRegisters/\registers_reg[2][9] } {/theRegisters/\registers_reg[30][0] } {/theRegisters/\registers_reg[30][10] } {/theRegisters/\registers_reg[30][11] } {/theRegisters/\registers_reg[30][12] } {/theRegisters/\registers_reg[30][13] } {/theRegisters/\registers_reg[30][14] } {/theRegisters/\registers_reg[30][15] } {/theRegisters/\registers_reg[30][16] } {/theRegisters/\registers_reg[30][17] } {/theRegisters/\registers_reg[30][18] } {/theRegisters/\registers_reg[30][19] } {/theRegisters/\registers_reg[30][1] } {/theRegisters/\registers_reg[30][20] } {/theRegisters/\registers_reg[30][21] } {/theRegisters/\registers_reg[30][22] } {/theRegisters/\registers_reg[30][23] } {/theRegisters/\registers_reg[30][24] } {/theRegisters/\registers_reg[30][25] } {/theRegisters/\registers_reg[30][26] } {/theRegisters/\registers_reg[30][27] } {/theRegisters/\registers_reg[30][28] } {/theRegisters/\registers_reg[30][29] } {/theRegisters/\registers_reg[30][2] } {/theRegisters/\registers_reg[30][30] } {/theRegisters/\registers_reg[30][31] } {/theRegisters/\registers_reg[30][3] } {/theRegisters/\registers_reg[30][4] } {/theRegisters/\registers_reg[30][5] } {/theRegisters/\registers_reg[30][6] } {/theRegisters/\registers_reg[30][7] } {/theRegisters/\registers_reg[30][8] } {/theRegisters/\registers_reg[30][9] } " -si_connections "SI_3 " -so_connections "SO_3 " -chain_count 1 +// sub-command: create_scan_chain_family scanChain_4 -include_elements "{/theRegisters/\registers_reg[31][0] } {/theRegisters/\registers_reg[31][10] } {/theRegisters/\registers_reg[31][11] } {/theRegisters/\registers_reg[31][12] } {/theRegisters/\registers_reg[31][13] } {/theRegisters/\registers_reg[31][14] } {/theRegisters/\registers_reg[31][15] } {/theRegisters/\registers_reg[31][16] } {/theRegisters/\registers_reg[31][17] } {/theRegisters/\registers_reg[31][18] } {/theRegisters/\registers_reg[31][19] } {/theRegisters/\registers_reg[31][1] } {/theRegisters/\registers_reg[31][20] } {/theRegisters/\registers_reg[31][21] } {/theRegisters/\registers_reg[31][22] } {/theRegisters/\registers_reg[31][23] } {/theRegisters/\registers_reg[31][24] } {/theRegisters/\registers_reg[31][25] } {/theRegisters/\registers_reg[31][26] } {/theRegisters/\registers_reg[31][27] } {/theRegisters/\registers_reg[31][28] } {/theRegisters/\registers_reg[31][29] } {/theRegisters/\registers_reg[31][2] } {/theRegisters/\registers_reg[31][30] } {/theRegisters/\registers_reg[31][31] } {/theRegisters/\registers_reg[31][3] } {/theRegisters/\registers_reg[31][4] } {/theRegisters/\registers_reg[31][5] } {/theRegisters/\registers_reg[31][6] } {/theRegisters/\registers_reg[31][7] } {/theRegisters/\registers_reg[31][8] } {/theRegisters/\registers_reg[31][9] } {/theRegisters/\registers_reg[3][0] } {/theRegisters/\registers_reg[3][10] } {/theRegisters/\registers_reg[3][11] } {/theRegisters/\registers_reg[3][12] } {/theRegisters/\registers_reg[3][13] } {/theRegisters/\registers_reg[3][14] } {/theRegisters/\registers_reg[3][15] } {/theRegisters/\registers_reg[3][16] } {/theRegisters/\registers_reg[3][17] } {/theRegisters/\registers_reg[3][18] } {/theRegisters/\registers_reg[3][19] } {/theRegisters/\registers_reg[3][1] } {/theRegisters/\registers_reg[3][20] } {/theRegisters/\registers_reg[3][21] } {/theRegisters/\registers_reg[3][22] } {/theRegisters/\registers_reg[3][23] } {/theRegisters/\registers_reg[3][24] } {/theRegisters/\registers_reg[3][25] } {/theRegisters/\registers_reg[3][26] } {/theRegisters/\registers_reg[3][27] } {/theRegisters/\registers_reg[3][28] } {/theRegisters/\registers_reg[3][29] } {/theRegisters/\registers_reg[3][2] } {/theRegisters/\registers_reg[3][30] } {/theRegisters/\registers_reg[3][31] } {/theRegisters/\registers_reg[3][3] } {/theRegisters/\registers_reg[3][4] } {/theRegisters/\registers_reg[3][5] } {/theRegisters/\registers_reg[3][6] } {/theRegisters/\registers_reg[3][7] } {/theRegisters/\registers_reg[3][8] } {/theRegisters/\registers_reg[3][9] } {/theRegisters/\registers_reg[4][0] } {/theRegisters/\registers_reg[4][10] } {/theRegisters/\registers_reg[4][11] } {/theRegisters/\registers_reg[4][12] } {/theRegisters/\registers_reg[4][13] } {/theRegisters/\registers_reg[4][14] } {/theRegisters/\registers_reg[4][15] } {/theRegisters/\registers_reg[4][16] } {/theRegisters/\registers_reg[4][17] } {/theRegisters/\registers_reg[4][18] } {/theRegisters/\registers_reg[4][19] } {/theRegisters/\registers_reg[4][1] } {/theRegisters/\registers_reg[4][20] } {/theRegisters/\registers_reg[4][21] } {/theRegisters/\registers_reg[4][22] } {/theRegisters/\registers_reg[4][23] } {/theRegisters/\registers_reg[4][24] } {/theRegisters/\registers_reg[4][25] } {/theRegisters/\registers_reg[4][26] } {/theRegisters/\registers_reg[4][27] } {/theRegisters/\registers_reg[4][28] } {/theRegisters/\registers_reg[4][29] } {/theRegisters/\registers_reg[4][2] } {/theRegisters/\registers_reg[4][30] } {/theRegisters/\registers_reg[4][31] } {/theRegisters/\registers_reg[4][3] } {/theRegisters/\registers_reg[4][4] } {/theRegisters/\registers_reg[4][5] } {/theRegisters/\registers_reg[4][6] } {/theRegisters/\registers_reg[4][7] } {/theRegisters/\registers_reg[4][8] } {/theRegisters/\registers_reg[4][9] } {/theRegisters/\registers_reg[5][0] } {/theRegisters/\registers_reg[5][10] } {/theRegisters/\registers_reg[5][11] } {/theRegisters/\registers_reg[5][12] } {/theRegisters/\registers_reg[5][13] } {/theRegisters/\registers_reg[5][14] } {/theRegisters/\registers_reg[5][15] } {/theRegisters/\registers_reg[5][16] } {/theRegisters/\registers_reg[5][17] } {/theRegisters/\registers_reg[5][18] } {/theRegisters/\registers_reg[5][19] } {/theRegisters/\registers_reg[5][1] } {/theRegisters/\registers_reg[5][20] } {/theRegisters/\registers_reg[5][21] } {/theRegisters/\registers_reg[5][22] } {/theRegisters/\registers_reg[5][23] } {/theRegisters/\registers_reg[5][24] } {/theRegisters/\registers_reg[5][25] } {/theRegisters/\registers_reg[5][26] } {/theRegisters/\registers_reg[5][27] } {/theRegisters/\registers_reg[5][28] } {/theRegisters/\registers_reg[5][29] } {/theRegisters/\registers_reg[5][2] } {/theRegisters/\registers_reg[5][30] } {/theRegisters/\registers_reg[5][31] } {/theRegisters/\registers_reg[5][3] } {/theRegisters/\registers_reg[5][4] } {/theRegisters/\registers_reg[5][5] } {/theRegisters/\registers_reg[5][6] } {/theRegisters/\registers_reg[5][7] } {/theRegisters/\registers_reg[5][8] } {/theRegisters/\registers_reg[5][9] } {/theRegisters/\registers_reg[6][0] } {/theRegisters/\registers_reg[6][10] } {/theRegisters/\registers_reg[6][11] } {/theRegisters/\registers_reg[6][12] } {/theRegisters/\registers_reg[6][13] } {/theRegisters/\registers_reg[6][14] } {/theRegisters/\registers_reg[6][15] } {/theRegisters/\registers_reg[6][16] } {/theRegisters/\registers_reg[6][17] } {/theRegisters/\registers_reg[6][18] } {/theRegisters/\registers_reg[6][19] } {/theRegisters/\registers_reg[6][1] } {/theRegisters/\registers_reg[6][20] } {/theRegisters/\registers_reg[6][21] } {/theRegisters/\registers_reg[6][22] } {/theRegisters/\registers_reg[6][23] } {/theRegisters/\registers_reg[6][24] } {/theRegisters/\registers_reg[6][25] } {/theRegisters/\registers_reg[6][26] } {/theRegisters/\registers_reg[6][27] } {/theRegisters/\registers_reg[6][28] } {/theRegisters/\registers_reg[6][29] } {/theRegisters/\registers_reg[6][2] } {/theRegisters/\registers_reg[6][30] } {/theRegisters/\registers_reg[6][31] } {/theRegisters/\registers_reg[6][3] } {/theRegisters/\registers_reg[6][4] } {/theRegisters/\registers_reg[6][5] } {/theRegisters/\registers_reg[6][6] } {/theRegisters/\registers_reg[6][7] } {/theRegisters/\registers_reg[6][8] } {/theRegisters/\registers_reg[6][9] } {/theRegisters/\registers_reg[7][0] } {/theRegisters/\registers_reg[7][10] } {/theRegisters/\registers_reg[7][11] } {/theRegisters/\registers_reg[7][12] } {/theRegisters/\registers_reg[7][13] } {/theRegisters/\registers_reg[7][14] } {/theRegisters/\registers_reg[7][15] } {/theRegisters/\registers_reg[7][16] } {/theRegisters/\registers_reg[7][17] } {/theRegisters/\registers_reg[7][18] } {/theRegisters/\registers_reg[7][19] } {/theRegisters/\registers_reg[7][1] } {/theRegisters/\registers_reg[7][20] } {/theRegisters/\registers_reg[7][21] } {/theRegisters/\registers_reg[7][22] } {/theRegisters/\registers_reg[7][23] } {/theRegisters/\registers_reg[7][24] } {/theRegisters/\registers_reg[7][25] } {/theRegisters/\registers_reg[7][26] } {/theRegisters/\registers_reg[7][27] } {/theRegisters/\registers_reg[7][28] } {/theRegisters/\registers_reg[7][29] } {/theRegisters/\registers_reg[7][2] } {/theRegisters/\registers_reg[7][30] } {/theRegisters/\registers_reg[7][31] } {/theRegisters/\registers_reg[7][3] } {/theRegisters/\registers_reg[7][4] } {/theRegisters/\registers_reg[7][5] } {/theRegisters/\registers_reg[7][6] } {/theRegisters/\registers_reg[7][7] } {/theRegisters/\registers_reg[7][8] } {/theRegisters/\registers_reg[7][9] } {/theRegisters/\registers_reg[8][0] } {/theRegisters/\registers_reg[8][10] } {/theRegisters/\registers_reg[8][11] } {/theRegisters/\registers_reg[8][12] } {/theRegisters/\registers_reg[8][13] } {/theRegisters/\registers_reg[8][14] } {/theRegisters/\registers_reg[8][15] } {/theRegisters/\registers_reg[8][16] } {/theRegisters/\registers_reg[8][17] } {/theRegisters/\registers_reg[8][18] } {/theRegisters/\registers_reg[8][19] } {/theRegisters/\registers_reg[8][1] } {/theRegisters/\registers_reg[8][20] } {/theRegisters/\registers_reg[8][21] } {/theRegisters/\registers_reg[8][22] } {/theRegisters/\registers_reg[8][23] } {/theRegisters/\registers_reg[8][24] } {/theRegisters/\registers_reg[8][25] } {/theRegisters/\registers_reg[8][26] } {/theRegisters/\registers_reg[8][27] } {/theRegisters/\registers_reg[8][28] } {/theRegisters/\registers_reg[8][29] } {/theRegisters/\registers_reg[8][2] } {/theRegisters/\registers_reg[8][30] } {/theRegisters/\registers_reg[8][31] } {/theRegisters/\registers_reg[8][3] } {/theRegisters/\registers_reg[8][4] } {/theRegisters/\registers_reg[8][5] } {/theRegisters/\registers_reg[8][6] } {/theRegisters/\registers_reg[8][7] } {/theRegisters/\registers_reg[8][8] } {/theRegisters/\registers_reg[8][9] } {/theRegisters/\registers_reg[9][0] } {/theRegisters/\registers_reg[9][10] } {/theRegisters/\registers_reg[9][11] } {/theRegisters/\registers_reg[9][12] } {/theRegisters/\registers_reg[9][13] } {/theRegisters/\registers_reg[9][14] } {/theRegisters/\registers_reg[9][15] } {/theRegisters/\registers_reg[9][16] } {/theRegisters/\registers_reg[9][17] } {/theRegisters/\registers_reg[9][18] } {/theRegisters/\registers_reg[9][19] } {/theRegisters/\registers_reg[9][1] } {/theRegisters/\registers_reg[9][20] } {/theRegisters/\registers_reg[9][21] } {/theRegisters/\registers_reg[9][22] } {/theRegisters/\registers_reg[9][23] } {/theRegisters/\registers_reg[9][24] } {/theRegisters/\registers_reg[9][25] } {/theRegisters/\registers_reg[9][26] } {/theRegisters/\registers_reg[9][27] } {/theRegisters/\registers_reg[9][28] } {/theRegisters/\registers_reg[9][29] } {/theRegisters/\registers_reg[9][2] } {/theRegisters/\registers_reg[9][30] } {/theRegisters/\registers_reg[9][31] } {/theRegisters/\registers_reg[9][3] } {/theRegisters/\registers_reg[9][4] } {/theRegisters/\registers_reg[9][5] } {/theRegisters/\registers_reg[9][6] } {/theRegisters/\registers_reg[9][7] } {/theRegisters/\registers_reg[9][8] } {/theRegisters/\registers_reg[9][9] } " -si_connections "SI_4 " -so_connections "SO_4 " -chain_count 1 +// sub-command: analyze_scan_chains +// Chain allocation of 'unwrapped' mode completed: +// 4 distributed chains of size 256 +// sub-command: insert_test_logic -write_in_tsdb on +============================= +Test Logic Insertion Summary: +============================= + + Structural Data: + ---------------- + Added top-level port count: 0 + Added instance count: 8 + + Logical Data: + ------------- + Added retiming logic count: 4 + Added scan chain count (unwrapped): 4 + +// Warning: Flattened model deleted. +// +// Writing out netlist and related files in /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.02/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design +// sub-command: report_scan_chains + +=============================== +Scan Chains Created by the Tool +=============================== + + Scan mode 'unwrapped' scan chains: + ---------------------------------- + + Cluster 'scanChain_1' chains: + ----------------------------- + chain = scanChain_1 group = dummy input = /SI_1 output = /SO_1 length = 256 + + Cluster 'scanChain_2' chains: + ----------------------------- + chain = scanChain_2 group = dummy input = /SI_2 output = /SO_2 length = 256 + + Cluster 'scanChain_3' chains: + ----------------------------- + chain = scanChain_3 group = dummy input = /SI_3 output = /SO_3 length = 256 + + Cluster 'scanChain_4' chains: + ----------------------------- + chain = scanChain_4 group = dummy input = /SI_4 output = /SO_4 length = 256 + + +// sub-command: write_scan_order /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.02/Scan_0/cpu.scandef -use_escaping_rule Lefdef -replace +// sub-command: write_design -output_file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.02/Scan_0/post_scan.v -replace +// command: exit diff --git a/oasys.tessent.02/Scan_0/scan_enable_cluster.cfg b/oasys.tessent.02/Scan_0/scan_enable_cluster.cfg new file mode 100644 index 0000000..838af56 --- /dev/null +++ b/oasys.tessent.02/Scan_0/scan_enable_cluster.cfg @@ -0,0 +1,8 @@ +set_attribute_value [get_scan_elements -of_chain_families scanChain_1 ] -name cluster_name -value scanChain_1 + +set_attribute_value [get_scan_elements -of_chain_families scanChain_2 ] -name cluster_name -value scanChain_2 + +set_attribute_value [get_scan_elements -of_chain_families scanChain_3 ] -name cluster_name -value scanChain_3 + +set_attribute_value [get_scan_elements -of_chain_families scanChain_4 ] -name cluster_name -value scanChain_4 + diff --git a/oasys.tessent.02/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.scandef b/oasys.tessent.02/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.scandef new file mode 100644 index 0000000..e5886ed --- /dev/null +++ b/oasys.tessent.02/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.scandef @@ -0,0 +1,1071 @@ +# +# DESC: ScanDEF written by Tessent Shell on Fri May 29 09:12:39 CEST 2026 +# + +VERSION 5.7 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN cpu ; +UNITS DISTANCE MICRONS 1000 ; + +SCANCHAINS 4 ; + +- scan_segment_0 + + START tessent_persistent_cell_buf_extsi1225_i Z + + FLOATING + \thePC_CurrentPC_reg[30] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[29] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[28] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[27] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[26] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[25] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[24] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[23] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[22] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[21] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[20] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[19] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[18] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[17] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[16] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[15] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[14] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[13] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[12] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[11] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[10] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[9] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[8] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[7] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[6] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[5] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[4] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[3] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[2] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[31] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[1] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][0] ( IN SI ) ( OUT Q ) + + STOP theRegisters/ts_lockup_latchn_clkc1_intno1054_i D + # Partition constraints - clock domain: clk_25mhz(+); cluster: scanChain_1; chain type: core; scan mode(s): unwrapped + + PARTITION partition_1 MAXBITS 256 ; + + +- scan_segment_1 + + START theRegisters/tessent_persistent_cell_buf_extsi1226_i Z + + FLOATING + theRegisters/\registers_reg[1][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][0] ( IN SI ) ( OUT Q ) + + STOP theRegisters/ts_lockup_latchn_clkc2_intno1050_i D + # Partition constraints - clock domain: clk_25mhz(+); cluster: scanChain_2; chain type: core; scan mode(s): unwrapped + + PARTITION partition_2 MAXBITS 256 ; + + +- scan_segment_2 + + START theRegisters/tessent_persistent_cell_buf_extsi1227_i Z + + FLOATING + theRegisters/\registers_reg[28][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][0] ( IN SI ) ( OUT Q ) + + STOP theRegisters/ts_lockup_latchn_clkc3_intno1053_i D + # Partition constraints - clock domain: clk_25mhz(+); cluster: scanChain_3; chain type: core; scan mode(s): unwrapped + + PARTITION partition_3 MAXBITS 256 ; + + +- scan_segment_3 + + START theRegisters/tessent_persistent_cell_buf_extsi1228_i Z + + FLOATING + theRegisters/\registers_reg[4][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][0] ( IN SI ) ( OUT Q ) + + STOP theRegisters/ts_lockup_latchn_clkc4_intno1051_i D + # Partition constraints - clock domain: clk_25mhz(+); cluster: scanChain_4; chain type: core; scan mode(s): unwrapped + + PARTITION partition_4 MAXBITS 256 ; + + +END SCANCHAINS + +END DESIGN diff --git a/oasys.tessent.02/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.tcd b/oasys.tessent.02/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.tcd new file mode 100644 index 0000000..05cf7ab --- /dev/null +++ b/oasys.tessent.02/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.tcd @@ -0,0 +1,61 @@ +//-------------------------------------------------- +// File created by: Tessent Shell +// Version: 2023.4-p1 +// Created on: Fri May 29 09:12:39 CEST 2026 +//-------------------------------------------------- + + +Core(cpu) { + Scan { + allow_internal_pins : 1; + is_hard_module : 1; + exclude_from_concatenated_netlist : 1; + internal_scan_only : 1; + Mode(unwrapped) { + type : unwrapped; + traceable : 1; + make_active_automatically : 1; + ScanChain { + length : 256; + scan_in_clock : clk_25mhz; + scan_out_clock : ~clk_25mhz; + scan_in_port : SI_1; + scan_out_port : SO_1; + } + ScanChain { + length : 256; + scan_in_clock : clk_25mhz; + scan_out_clock : ~clk_25mhz; + scan_in_port : SI_2; + scan_out_port : SO_2; + } + ScanChain { + length : 256; + scan_in_clock : clk_25mhz; + scan_out_clock : ~clk_25mhz; + scan_in_port : SI_3; + scan_out_port : SO_3; + } + ScanChain { + length : 256; + scan_in_clock : clk_25mhz; + scan_out_clock : ~clk_25mhz; + scan_in_port : SI_4; + scan_out_port : SO_4; + } + ScanEn(scan_en) { + pipeline_count : 0; + active_polarity : all_ones; + } + Clock(clk_25mhz) { + off_state : 1'b0; + } + } + } + DesignInfo { + design_id : Scan_0; + design_level : physical_block; + ChildBlockModules { + } + } +} diff --git a/oasys.tessent.02/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.tsdb_info b/oasys.tessent.02/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.tsdb_info new file mode 100644 index 0000000..fd8dbff --- /dev/null +++ b/oasys.tessent.02/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.tsdb_info @@ -0,0 +1,23 @@ +//-------------------------------------------------- +// File created by: Tessent Shell +// Version: 2023.4-p1 +// Created on: Fri May 29 09:12:39 CEST 2026 +//-------------------------------------------------- + + +TsdbInfo(cpu,Scan_0) { + tessent_tool_version : 2023.4-p1; + tessent_meta_version : 10; + version : 3; + creation_date : Fri May 29 07:12:39 GMT 2026; + creation_user : charapallivenkatsaja; + creation_step : insert_test_logic; + level : physical_block; + icl_extraction_needed : Off; + library_name : work; + gate_extension : vg; + interface_has_external_dependencies : 0; + OpenedTsdbDirectories { + /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.02/tsdb_outdir; + } +} diff --git a/oasys.tessent.02/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.v_interface b/oasys.tessent.02/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.v_interface new file mode 100644 index 0000000..c1e696d --- /dev/null +++ b/oasys.tessent.02/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.v_interface @@ -0,0 +1,9 @@ +/* Generated by Tessent Shell 2023.4-p1 at Fri May 29 09:12:39 CEST 2026 */ +module cpu(led, btn, clk_25mhz, scan_en, SI_1, SO_1, SI_2, SO_2, SI_3, SO_3, SI_4, + SO_4); + input clk_25mhz, scan_en, SI_1, SI_2, SI_3, SI_4; + output SO_1, SO_2, SO_3, SO_4; + output [7:0] led; + input [6:0] btn; +endmodule + diff --git a/oasys.tessent.02/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.vg b/oasys.tessent.02/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.vg new file mode 100644 index 0000000..87c8a8a --- /dev/null +++ b/oasys.tessent.02/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.vg @@ -0,0 +1,15792 @@ +/* Generated by Tessent Shell 2023.4-p1 at Fri May 29 09:12:39 CEST 2026 */ +module alu(aluOp, aluNegAr, aluBypass, op1, op2, result, eqFlag); + input [31:0] op1, op2; + input [2:0] aluOp; + input aluNegAr, aluBypass; + output [31:0] result; + output eqFlag; + + wire n_9_0, n_9_1, n_9_2, n_9_3, n_9_4, n_9_5, n_9_6, n_9_7, n_9_8, n_9_9, + n_9_10, n_9_11, n_9_12, n_9_13, n_9_14, n_9_15, n_9_16, n_9_17, n_9_18, + n_9_19, n_9_20, n_9_21, n_9_22, n_9_23, n_9_24, n_9_25, n_9_26, n_9_27, + n_9_28, n_9_29, n_9_30, n_9_31, n_10_0, n_10_1, n_10_2, n_10_3, n_10_4, + n_10_5, n_10_6, n_10_7, n_10_8, n_10_9, n_10_10, n_10_11, n_10_12, + n_10_13, n_10_14, n_10_15, n_10_16, n_10_17, n_10_18, n_10_19, n_10_20, + n_10_21, n_10_22, n_10_23, n_10_24, n_10_25, n_10_26, n_10_27, n_10_28, + n_10_29, n_10_30, n_10_31, n_10_32, n_10_33, n_10_34, n_10_35, n_10_36, + n_10_37, n_10_38, n_10_39, n_10_40, n_10_41, n_10_42, n_10_43, n_10_44, + n_10_45, n_10_46, n_10_47, n_10_48, n_10_49, n_10_50, n_10_51, n_10_52, + n_10_53, n_10_54, n_10_55, n_10_56, n_10_57, n_10_58, n_10_59, n_10_60, + n_10_61, n_10_62, n_10_63, n_10_64, n_10_65, n_10_66, n_10_67, n_10_68, + n_10_69, n_10_70, n_10_71, n_10_72, n_10_73, n_10_74, n_10_75, n_10_76, + n_10_77, n_10_78, n_10_79, n_10_80, n_10_81, n_10_82, n_10_83, n_10_84, + n_10_85, n_10_86, n_10_87, n_10_88, n_10_89, n_10_90, n_10_91, n_10_92, + n_10_93, n_10_94, n_10_95, n_10_96, n_10_97, n_10_98, n_10_99, n_10_100, + n_10_101, n_10_102, n_10_103, n_10_104, n_10_105, n_10_106, n_10_107, + n_10_108, n_10_109, n_10_110, n_10_111, n_10_112, n_10_113, n_10_114, + n_10_115, n_10_116, n_10_117, n_10_118, n_10_119, n_10_120, n_10_121, + n_10_122, n_10_123, n_0_0, n_0_1, n_0_2, n_0_3, n_0_4, n_0_5, n_0_6, + n_0_7, n_0_8, n_0_9, n_0_10, n_0_11, n_0_12, n_0_13, n_0_14, n_0_15, + n_0_16, n_0_17, n_0_18, n_0_19, n_0_20, n_0_21, n_0_22, n_0_23, n_0_24, + n_0_25, n_0_26, n_0_27, n_0_28, n_0_29, n_0_30, n_0_31, n_0_32, n_0_33, + n_0_34, n_0_35, n_0_36, n_0_37, n_0_38, n_0_39, n_0_40, n_0_41, n_0_42, + n_0_43, n_0_44, n_0_45, n_0_46, n_0_47, n_0_48, n_0_49, n_0_50, n_0_51, + n_0_52, n_0_53, n_0_54, n_0_55, n_0_56, n_0_57, n_0_58, n_0_59, n_0_60, + n_0_61, n_0_62, n_0_63, n_0_64, n_0_65, n_0_66, n_0_67, n_0_68, n_0_69, + n_0_70, n_0_71, n_0_72, n_0_73, n_0_74, n_0_75, n_0_76, n_0_77, n_0_78, + n_0_79, n_0_80, n_0_81, n_0_82, n_0_83, n_0_84, n_0_85, n_0_86, n_0_87, + n_0_88, n_0_89, n_0_90, n_0_91, n_0_92, n_0_93, n_0_94, n_0_95, n_0_96, + n_0_97, n_0_98, n_0_99, n_0_100, n_0_101, n_0_102, n_0_103, n_0_104, + n_0_105, n_0_106, n_0_107, n_0_108, n_0_109, n_0_110, n_0_111, n_0_112, + n_0_113, n_0_114, n_0_115, n_0_116, n_0_117, n_0_118, n_0_119, n_0_120, + n_0_121, n_0_122, n_0_123, n_0_124, n_0_125, n_0_126, n_0_127, n_0_128, + n_0_129, n_0_130, n_0_131, n_0_132, n_0_133, n_0_134, n_0_135, n_0_136, + n_0_137, n_0_138, n_0_139, n_0_140, n_0_141, n_0_142, n_0_143, n_0_144, + n_0_145, n_0_146, n_0_147, n_0_148, n_0_149, n_0_150, n_0_151, n_0_152, + n_0_153, n_0_154, n_0_155, n_0_156, n_0_157, n_0_158, n_0_159, n_0_160, + n_0_161, n_0_162, n_0_163, n_0_164, n_0_165, n_0_166, n_0_167, n_0_168, + n_0_169, n_0_170, n_0_171, n_0_172, n_0_173, n_0_174, n_0_175, n_0_176, + n_0_177, n_0_178, n_0_179, n_0_180, n_0_181, n_0_182, n_0_183, n_0_184, + n_0_185, n_0_186, n_0_187, n_0_188, n_0_189, n_0_190, n_0_191, n_0_192, + n_0_193, n_0_194, n_0_195, n_0_196, n_0_197, n_0_198, n_0_199, n_0_200, + n_0_201, n_0_202, n_0_203, n_0_204, n_0_205, n_0_206, n_0_207, n_0_208, + n_0_209, n_0_210, n_0_211, n_0_212, n_0_213, n_0_214, n_0_215, n_0_216, + n_0_217, n_0_218, n_0_219, n_0_220, n_0_221, n_0_222, n_0_223, n_0_224, + n_0_225, n_0_226, n_0_227, n_0_228, n_0_229, n_0_230, n_0_231, n_0_232, + n_0_233, n_0_234, n_0_235, n_0_236, n_0_237, n_0_238, n_0_239, n_0_240, + n_0_241, n_0_242, n_0_243, n_0_244, n_0_245, n_0_246, n_0_247, n_0_248, + n_0_249, n_0_250, n_0_251, n_0_252, n_0_253, n_0_254, n_0_255, n_0_256, + n_0_257, n_0_258, n_0_259, n_0_260, n_0_261, n_0_262, n_0_263, n_0_264, + n_0_265, n_0_266, n_0_267, n_0_268, n_0_269, n_0_270, n_0_271, n_0_272, + n_0_273, n_0_274, n_0_275, n_0_276, n_0_277, n_0_278, n_0_279, n_0_280, + n_0_281, n_0_282, n_0_283, n_0_284, n_0_285, n_0_286, n_0_287, n_0_288, + n_0_289, n_0_290, n_0_291, n_0_292, n_0_293, n_0_294, n_0_295, n_0_296, + n_0_297, n_0_298, n_0_299, n_0_300, n_0_301, n_0_302, n_0_303, n_0_304, + n_0_305, n_0_306, n_0_307, n_0_308, n_0_309, n_0_310, n_0_311, n_0_312, + n_0_313, n_0_314, n_0_315, n_0_316, n_0_317, n_0_318, n_0_319, n_0_320, + n_0_321, n_0_322, n_0_323, n_0_324, n_0_325, n_0_326, n_0_327, n_0_328, + n_0_329, n_0_330, n_0_331, n_0_332, n_0_333, n_0_334, n_0_335, n_0_336, + n_0_337, n_0_338, n_0_339, n_0_340, n_0_341, n_0_342, n_0_343, n_0_344, + n_0_345, n_0_346, n_0_347, n_0_348, n_0_349, n_0_350, n_0_351, n_0_352, + n_0_353, n_0_354, n_0_355, n_0_356, n_0_357, n_0_358, n_0_359, n_0_360, + n_0_361, n_0_362, n_0_363, n_0_364, n_0_365, n_0_366, n_0_367, n_0_368, + n_0_369, n_0_370, n_0_371, n_0_372, n_0_373, n_0_374, n_0_375, n_0_376, + n_0_377, n_0_378, n_0_379, n_0_380, n_0_381, n_0_382, n_0_383, n_0_384, + n_0_385, n_0_386, n_0_387, n_0_388, n_0_389, n_0_390, n_0_391, n_0_392, + n_0_393, n_0_394, n_0_395, n_0_396, n_0_397, n_0_398, n_0_399, n_0_400, + n_0_401, n_0_402, n_0_403, n_0_404, n_0_405, n_0_406, n_0_407, n_0_408, + n_0_409, n_0_410, n_0_411, n_0_412, n_0_413, n_0_414, n_0_415, n_0_416, + n_0_417, n_0_418, n_0_419, n_0_420, n_0_421, n_0_422, n_0_423, n_0_424, + n_0_425, n_0_426, n_0_427, n_0_428, n_0_429, n_0_430, n_0_431, n_0_432, + n_0_433, n_0_434, n_0_435, n_0_436, n_0_437, n_0_438, n_0_439, n_0_440, + n_0_441, n_0_442, n_0_443, n_0_444, n_0_445, n_0_446, n_0_447, n_0_448, + n_0_449, n_0_450, n_0_451, n_0_452, n_0_453, n_0_454, n_0_455, n_0_456, + n_0_457, n_0_458, n_0_459, n_0_460, n_0_461, n_0_462, n_0_463, n_0_464, + n_0_465, n_0_466, n_0_467, n_0_468, n_0_469, n_0_470, n_0_471, n_0_472, + n_0_473, n_0_474, n_0_475, n_0_476, n_0_477, n_0_478, n_0_479, n_0_480, + n_0_481, n_0_482, n_0_483, n_0_484, n_0_485, n_0_486, n_0_487, n_0_488, + n_0_489, n_0_490, n_0_491, n_0_492, n_0_493, n_0_494, n_0_495, n_0_496, + n_0_497, n_0_498, n_0_499, n_0_500, n_0_501, n_0_502, n_0_503, n_0_504, + n_0_505, n_0_506, n_0_507, n_0_508, n_0_509, n_0_510, n_0_511, n_0_512, + n_0_513, n_0_514, n_0_515, n_0_516, n_0_517, n_0_518, n_0_519, n_0_520, + n_0_521, n_0_522, n_0_523, n_0_524, n_0_525, n_0_526, n_0_527, n_0_528, + n_0_529, n_0_530, n_0_531, n_0_532, n_0_533, n_0_534, n_0_535, n_0_536, + n_0_537, n_0_538, n_0_539, n_0_540, n_0_541, n_0_542, n_0_543, n_0_544, + n_0_545, n_0_546, n_0_547, n_0_548, n_0_549, n_0_550, n_0_551, n_0_552, + n_0_553, n_0_554, n_0_555, n_0_556, n_0_557, n_0_558, n_0_559, n_0_560, + n_0_561, n_0_562, n_0_563, n_0_564, n_0_565, n_0_566, n_0_567, n_0_568, + n_0_569, n_0_570, n_0_571, n_0_572, n_0_573, n_0_574, n_0_575, n_0_576, + n_0_577, n_0_578, n_0_579, n_0_580, n_0_581, n_0_582, n_0_583, n_0_584, + n_0_585, n_0_586, n_0_587, n_0_588, n_0_589, n_0_590, n_0_591, n_0_592, + n_0_593, n_0_594, n_0_595, n_0_596, n_0_597, n_0_598, n_0_599, n_0_600, + n_0_601, n_0_602, n_0_603, n_0_604, n_0_605, n_0_606, n_0_607, n_0_608, + n_0_609, n_0_610, n_0_611, n_0_612, n_0_613, n_0_614, n_0_615, n_0_616, + n_0_617, n_0_618, n_0_619, n_0_620, n_0_621, n_0_622, n_0_623, n_0_624, + n_0_625, n_0_626, n_0_627, n_0_628, n_0_629, n_0_630, n_0_631, n_0_632, + n_0_633, n_0_634, n_0_635, n_0_636, n_0_637, n_0_638, n_0_639, n_0_640, + n_0_641, n_0_642, n_0_643, n_0_644, n_0_645, n_0_646, n_0_647, n_0_648, + n_0_649, n_0_650, n_0_651, n_0_652, n_0_653, n_0_654, n_0_655, n_0_656, + n_0_657, n_0_658, n_0_659, n_0_660, n_0_661, n_0_662, n_0_663, n_0_664, + n_0_665, n_0_666, n_0_667, n_0_668, n_0_669, n_0_670, n_0_671, n_0_672, + n_0_673, n_0_674, n_0_675, n_0_676, n_0_677, n_0_678, n_0_679, n_0_680, + n_0_681, n_0_682, n_0_683, n_0_684, n_0_685, n_0_686, n_0_687, n_0_688, + n_0_689, n_0_690, n_0_691, n_0_692, n_0_693, n_0_694, n_0_695, n_0_696, + n_0_697, n_0_698, n_0_699, n_0_700, n_0_701, n_0_702, n_0_703, n_0_704, + n_0_705, n_0_706, n_0_707, n_0_708, n_0_709, n_0_710, n_0_711, n_0_712, + n_0_713, n_0_714, n_0_715, n_0_716, n_0_717, n_0_718, n_0_719, n_0_720, + n_0_721, n_0_722, n_0_723, n_0_724, n_0_725, n_0_726, n_0_727, n_0_728, + n_0_729, n_0_730, n_0_731, n_0_732, n_0_733, n_0_734, n_0_735, n_0_736, + n_0_737, n_0_738, n_0_739, n_0_740, n_0, n_1, n_2, n_3, n_4, n_5, n_6, + n_7, n_8, n_9, n_10, n_11, n_12, n_13, n_14, n_15, n_16, n_17, n_18, + n_19, n_20, n_21, n_22, n_23, n_24, n_25, n_26, n_27, n_28, n_29, n_30, + n_31, n_63, n_62, n_61, n_60, n_59, n_58, n_57, n_56, n_55, n_54, n_53, + n_52, n_51, n_50, n_49, n_48, n_47, n_46, n_45, n_44, n_43, n_42, n_41, + n_40, n_39, n_38, n_37, n_36, n_35, n_34, n_33, n_32; + + INV_X1_LVT i_0_725( + .A(op2[31]), .ZN(n_0_692) + ); + INV_X1_LVT i_0_724( + .A(op1[31]), .ZN(n_0_691) + ); + INV_X1_LVT i_0_718( + .A(aluOp[1]), .ZN(n_0_685) + ); + INV_X1_LVT i_0_717( + .A(aluOp[2]), .ZN(n_0_684) + ); + NOR2_X1_LVT i_0_599( + .A1(n_0_685), .A2(n_0_684), .ZN(n_0_567) + ); + INV_X1_LVT i_0_598( + .A(n_0_567), .ZN(n_0_566) + ); + INV_X1_LVT i_0_716( + .A(aluOp[0]), .ZN(n_0_683) + ); + NAND2_X1_LVT i_0_602( + .A1(aluOp[2]), .A2(aluNegAr), .ZN(n_0_570) + ); + OAI21_X1_LVT i_0_590( + .A(n_0_566), .B1(n_0_683), .B2(n_0_570), .ZN(n_0_558) + ); + INV_X1_LVT i_0_714( + .A(aluBypass), .ZN(n_0_681) + ); + NOR2_X1_LVT i_0_601( + .A1(n_0_684), .A2(aluOp[0]), .ZN(n_0_569) + ); + NAND2_X1_LVT i_0_597( + .A1(n_0_681), .A2(n_0_569), .ZN(n_0_565) + ); + INV_X1_LVT i_0_596( + .A(n_0_565), .ZN(n_0_564) + ); + OAI22_X1_LVT i_0_589( + .A1(n_0_691), .A2(n_0_558), .B1(op1[31]), .B2(n_0_564), .ZN(n_0_557) + ); + NOR2_X1_LVT i_0_588( + .A1(n_0_692), .A2(n_0_557), .ZN(n_0_556) + ); + XNOR2_X1_LVT i_9_31( + .A(op2[31]), .B(op1[31]), .ZN(n_9_31) + ); + HA_X1_LVT i_9_0( + .A(op2[0]), .B(op1[0]), .CO(n_9_0), .S(n_0) + ); + FA_X1_LVT i_9_1( + .A(op2[1]), .B(op1[1]), .CI(n_9_0), .CO(n_9_1), .S(n_1) + ); + FA_X1_LVT i_9_2( + .A(op2[2]), .B(op1[2]), .CI(n_9_1), .CO(n_9_2), .S(n_2) + ); + FA_X1_LVT i_9_3( + .A(op2[3]), .B(op1[3]), .CI(n_9_2), .CO(n_9_3), .S(n_3) + ); + FA_X1_LVT i_9_4( + .A(op2[4]), .B(op1[4]), .CI(n_9_3), .CO(n_9_4), .S(n_4) + ); + FA_X1_LVT i_9_5( + .A(op2[5]), .B(op1[5]), .CI(n_9_4), .CO(n_9_5), .S(n_5) + ); + FA_X1_LVT i_9_6( + .A(op2[6]), .B(op1[6]), .CI(n_9_5), .CO(n_9_6), .S(n_6) + ); + FA_X1_LVT i_9_7( + .A(op2[7]), .B(op1[7]), .CI(n_9_6), .CO(n_9_7), .S(n_7) + ); + FA_X1_LVT i_9_8( + .A(op2[8]), .B(op1[8]), .CI(n_9_7), .CO(n_9_8), .S(n_8) + ); + FA_X1_LVT i_9_9( + .A(op2[9]), .B(op1[9]), .CI(n_9_8), .CO(n_9_9), .S(n_9) + ); + FA_X1_LVT i_9_10( + .A(op2[10]), .B(op1[10]), .CI(n_9_9), .CO(n_9_10), .S(n_10) + ); + FA_X1_LVT i_9_11( + .A(op2[11]), .B(op1[11]), .CI(n_9_10), .CO(n_9_11), .S(n_11) + ); + FA_X1_LVT i_9_12( + .A(op2[12]), .B(op1[12]), .CI(n_9_11), .CO(n_9_12), .S(n_12) + ); + FA_X1_LVT i_9_13( + .A(op2[13]), .B(op1[13]), .CI(n_9_12), .CO(n_9_13), .S(n_13) + ); + FA_X1_LVT i_9_14( + .A(op2[14]), .B(op1[14]), .CI(n_9_13), .CO(n_9_14), .S(n_14) + ); + FA_X1_LVT i_9_15( + .A(op2[15]), .B(op1[15]), .CI(n_9_14), .CO(n_9_15), .S(n_15) + ); + FA_X1_LVT i_9_16( + .A(op2[16]), .B(op1[16]), .CI(n_9_15), .CO(n_9_16), .S(n_16) + ); + FA_X1_LVT i_9_17( + .A(op2[17]), .B(op1[17]), .CI(n_9_16), .CO(n_9_17), .S(n_17) + ); + FA_X1_LVT i_9_18( + .A(op2[18]), .B(op1[18]), .CI(n_9_17), .CO(n_9_18), .S(n_18) + ); + FA_X1_LVT i_9_19( + .A(op2[19]), .B(op1[19]), .CI(n_9_18), .CO(n_9_19), .S(n_19) + ); + FA_X1_LVT i_9_20( + .A(op2[20]), .B(op1[20]), .CI(n_9_19), .CO(n_9_20), .S(n_20) + ); + FA_X1_LVT i_9_21( + .A(op2[21]), .B(op1[21]), .CI(n_9_20), .CO(n_9_21), .S(n_21) + ); + FA_X1_LVT i_9_22( + .A(op2[22]), .B(op1[22]), .CI(n_9_21), .CO(n_9_22), .S(n_22) + ); + FA_X1_LVT i_9_23( + .A(op2[23]), .B(op1[23]), .CI(n_9_22), .CO(n_9_23), .S(n_23) + ); + FA_X1_LVT i_9_24( + .A(op2[24]), .B(op1[24]), .CI(n_9_23), .CO(n_9_24), .S(n_24) + ); + FA_X1_LVT i_9_25( + .A(op2[25]), .B(op1[25]), .CI(n_9_24), .CO(n_9_25), .S(n_25) + ); + FA_X1_LVT i_9_26( + .A(op2[26]), .B(op1[26]), .CI(n_9_25), .CO(n_9_26), .S(n_26) + ); + FA_X1_LVT i_9_27( + .A(op2[27]), .B(op1[27]), .CI(n_9_26), .CO(n_9_27), .S(n_27) + ); + FA_X1_LVT i_9_28( + .A(op2[28]), .B(op1[28]), .CI(n_9_27), .CO(n_9_28), .S(n_28) + ); + FA_X1_LVT i_9_29( + .A(op2[29]), .B(op1[29]), .CI(n_9_28), .CO(n_9_29), .S(n_29) + ); + FA_X1_LVT i_9_30( + .A(op2[30]), .B(op1[30]), .CI(n_9_29), .CO(n_9_30), .S(n_30) + ); + XNOR2_X1_LVT i_9_32( + .A(n_9_31), .B(n_9_30), .ZN(n_31) + ); + NAND4_X1_LVT i_0_614( + .A1(n_0_685), .A2(n_0_681), .A3(n_0_684), .A4(n_0_683), .ZN(n_0_582) + ); + NOR2_X1_LVT i_0_613( + .A1(aluNegAr), .A2(n_0_582), .ZN(n_0_581) + ); + INV_X1_LVT i_10_147( + .A(op2[30]), .ZN(n_10_117) + ); + NAND2_X1_LVT i_10_149( + .A1(n_10_117), .A2(op1[30]), .ZN(n_10_119) + ); + INV_X1_LVT i_10_152( + .A(n_10_119), .ZN(n_10_121) + ); + INV_X1_LVT i_10_130( + .A(op1[26]), .ZN(n_10_104) + ); + NAND2_X1_LVT i_10_131( + .A1(n_10_104), .A2(op2[26]), .ZN(n_10_105) + ); + INV_X1_LVT i_10_123( + .A(op2[25]), .ZN(n_10_98) + ); + NAND2_X1_LVT i_10_125( + .A1(n_10_98), .A2(op1[25]), .ZN(n_10_100) + ); + INV_X1_LVT i_10_112( + .A(op2[23]), .ZN(n_10_89) + ); + NAND2_X1_LVT i_10_114( + .A1(n_10_89), .A2(op1[23]), .ZN(n_10_91) + ); + INV_X1_LVT i_10_101( + .A(op2[21]), .ZN(n_10_80) + ); + NAND2_X1_LVT i_10_103( + .A1(n_10_80), .A2(op1[21]), .ZN(n_10_82) + ); + INV_X1_LVT i_10_48( + .A(op1[8]), .ZN(n_10_40) + ); + NAND2_X1_LVT i_10_49( + .A1(n_10_40), .A2(op2[8]), .ZN(n_10_41) + ); + INV_X1_LVT i_10_41( + .A(op2[7]), .ZN(n_10_34) + ); + NAND2_X1_LVT i_10_43( + .A1(n_10_34), .A2(op1[7]), .ZN(n_10_36) + ); + INV_X1_LVT i_10_32( + .A(op2[5]), .ZN(n_10_27) + ); + NOR2_X1_LVT i_10_33( + .A1(n_10_27), .A2(op1[5]), .ZN(n_10_28) + ); + INV_X1_LVT i_10_24( + .A(op1[4]), .ZN(n_10_20) + ); + NOR2_X1_LVT i_10_27( + .A1(n_10_20), .A2(op2[4]), .ZN(n_10_23) + ); + INV_X1_LVT i_10_17( + .A(op2[3]), .ZN(n_10_14) + ); + NAND2_X1_LVT i_10_19( + .A1(n_10_14), .A2(op1[3]), .ZN(n_10_16) + ); + INV_X1_LVT i_10_22( + .A(n_10_16), .ZN(n_10_18) + ); + INV_X1_LVT i_10_10( + .A(op2[2]), .ZN(n_10_8) + ); + NAND2_X1_LVT i_10_12( + .A1(n_10_8), .A2(op1[2]), .ZN(n_10_10) + ); + INV_X1_LVT i_10_3( + .A(op1[1]), .ZN(n_10_2) + ); + NAND2_X1_LVT i_10_5( + .A1(n_10_2), .A2(op2[1]), .ZN(n_10_4) + ); + INV_X1_LVT i_10_0( + .A(op1[0]), .ZN(n_10_0) + ); + NAND2_X1_LVT i_10_1( + .A1(n_10_0), .A2(op2[0]), .ZN(n_10_1) + ); + OR2_X1_LVT i_10_4( + .A1(n_10_2), .A2(op2[1]), .ZN(n_10_3) + ); + INV_X1_LVT i_10_8( + .A(n_10_3), .ZN(n_10_6) + ); + OAI21_X1_LVT i_10_9( + .A(n_10_4), .B1(n_10_1), .B2(n_10_6), .ZN(n_10_7) + ); + NOR2_X1_LVT i_10_11( + .A1(n_10_8), .A2(op1[2]), .ZN(n_10_9) + ); + OAI21_X1_LVT i_10_16( + .A(n_10_10), .B1(n_10_7), .B2(n_10_9), .ZN(n_10_13) + ); + OR2_X1_LVT i_10_18( + .A1(n_10_14), .A2(op1[3]), .ZN(n_10_15) + ); + AOI21_X1_LVT i_10_23( + .A(n_10_18), .B1(n_10_13), .B2(n_10_15), .ZN(n_10_19) + ); + INV_X1_LVT i_10_30( + .A(n_10_19), .ZN(n_10_25) + ); + NAND2_X1_LVT i_10_25( + .A1(n_10_20), .A2(op2[4]), .ZN(n_10_21) + ); + AOI21_X1_LVT i_10_31( + .A(n_10_23), .B1(n_10_25), .B2(n_10_21), .ZN(n_10_26) + ); + AOI21_X1_LVT i_10_34( + .A(n_10_28), .B1(n_10_27), .B2(op1[5]), .ZN(n_10_29) + ); + AOI21_X1_LVT i_10_36( + .A(n_10_28), .B1(n_10_26), .B2(n_10_29), .ZN(n_10_30) + ); + XOR2_X1_LVT i_10_37( + .A(op2[6]), .B(op1[6]), .Z(n_10_31) + ); + INV_X1_LVT i_10_39( + .A(op2[6]), .ZN(n_10_32) + ); + OAI22_X1_LVT i_10_40( + .A1(n_10_30), .A2(n_10_31), .B1(n_10_32), .B2(op1[6]), .ZN(n_10_33) + ); + NOR2_X1_LVT i_10_42( + .A1(n_10_34), .A2(op1[7]), .ZN(n_10_35) + ); + OAI21_X1_LVT i_10_47( + .A(n_10_36), .B1(n_10_33), .B2(n_10_35), .ZN(n_10_39) + ); + OAI21_X1_LVT i_10_50( + .A(n_10_41), .B1(n_10_40), .B2(op2[8]), .ZN(n_10_42) + ); + OAI21_X1_LVT i_10_52( + .A(n_10_41), .B1(n_10_39), .B2(n_10_42), .ZN(n_10_43) + ); + XNOR2_X1_LVT i_10_53( + .A(op2[9]), .B(op1[9]), .ZN(n_10_44) + ); + INV_X1_LVT i_10_55( + .A(op1[9]), .ZN(n_10_45) + ); + AOI22_X1_LVT i_10_56( + .A1(n_10_43), .A2(n_10_44), .B1(n_10_45), .B2(op2[9]), .ZN(n_10_46) + ); + XOR2_X1_LVT i_10_57( + .A(op2[10]), .B(op1[10]), .Z(n_10_47) + ); + INV_X1_LVT i_10_59( + .A(op2[10]), .ZN(n_10_48) + ); + OAI22_X1_LVT i_10_60( + .A1(n_10_46), .A2(n_10_47), .B1(n_10_48), .B2(op1[10]), .ZN(n_10_49) + ); + XNOR2_X1_LVT i_10_61( + .A(op2[11]), .B(op1[11]), .ZN(n_10_50) + ); + INV_X1_LVT i_10_63( + .A(op1[11]), .ZN(n_10_51) + ); + AOI22_X1_LVT i_10_64( + .A1(n_10_49), .A2(n_10_50), .B1(n_10_51), .B2(op2[11]), .ZN(n_10_52) + ); + XOR2_X1_LVT i_10_65( + .A(op2[12]), .B(op1[12]), .Z(n_10_53) + ); + INV_X1_LVT i_10_67( + .A(op2[12]), .ZN(n_10_54) + ); + OAI22_X1_LVT i_10_68( + .A1(n_10_52), .A2(n_10_53), .B1(n_10_54), .B2(op1[12]), .ZN(n_10_55) + ); + XNOR2_X1_LVT i_10_69( + .A(op2[13]), .B(op1[13]), .ZN(n_10_56) + ); + INV_X1_LVT i_10_71( + .A(op1[13]), .ZN(n_10_57) + ); + AOI22_X1_LVT i_10_72( + .A1(n_10_55), .A2(n_10_56), .B1(n_10_57), .B2(op2[13]), .ZN(n_10_58) + ); + XOR2_X1_LVT i_10_73( + .A(op2[14]), .B(op1[14]), .Z(n_10_59) + ); + INV_X1_LVT i_10_75( + .A(op2[14]), .ZN(n_10_60) + ); + OAI22_X1_LVT i_10_76( + .A1(n_10_58), .A2(n_10_59), .B1(n_10_60), .B2(op1[14]), .ZN(n_10_61) + ); + XNOR2_X1_LVT i_10_77( + .A(op2[15]), .B(op1[15]), .ZN(n_10_62) + ); + INV_X1_LVT i_10_79( + .A(op1[15]), .ZN(n_10_63) + ); + AOI22_X1_LVT i_10_80( + .A1(n_10_61), .A2(n_10_62), .B1(n_10_63), .B2(op2[15]), .ZN(n_10_64) + ); + XOR2_X1_LVT i_10_81( + .A(op2[16]), .B(op1[16]), .Z(n_10_65) + ); + INV_X1_LVT i_10_83( + .A(op2[16]), .ZN(n_10_66) + ); + OAI22_X1_LVT i_10_84( + .A1(n_10_64), .A2(n_10_65), .B1(n_10_66), .B2(op1[16]), .ZN(n_10_67) + ); + XNOR2_X1_LVT i_10_85( + .A(op2[17]), .B(op1[17]), .ZN(n_10_68) + ); + INV_X1_LVT i_10_87( + .A(op1[17]), .ZN(n_10_69) + ); + AOI22_X1_LVT i_10_88( + .A1(n_10_67), .A2(n_10_68), .B1(n_10_69), .B2(op2[17]), .ZN(n_10_70) + ); + XOR2_X1_LVT i_10_89( + .A(op2[18]), .B(op1[18]), .Z(n_10_71) + ); + INV_X1_LVT i_10_91( + .A(op2[18]), .ZN(n_10_72) + ); + OAI22_X1_LVT i_10_92( + .A1(n_10_70), .A2(n_10_71), .B1(n_10_72), .B2(op1[18]), .ZN(n_10_73) + ); + XNOR2_X1_LVT i_10_93( + .A(op2[19]), .B(op1[19]), .ZN(n_10_74) + ); + INV_X1_LVT i_10_95( + .A(op1[19]), .ZN(n_10_75) + ); + AOI22_X1_LVT i_10_96( + .A1(n_10_73), .A2(n_10_74), .B1(n_10_75), .B2(op2[19]), .ZN(n_10_76) + ); + XOR2_X1_LVT i_10_97( + .A(op2[20]), .B(op1[20]), .Z(n_10_77) + ); + INV_X1_LVT i_10_99( + .A(op2[20]), .ZN(n_10_78) + ); + OAI22_X1_LVT i_10_100( + .A1(n_10_76), .A2(n_10_77), .B1(n_10_78), .B2(op1[20]), .ZN(n_10_79) + ); + NOR2_X1_LVT i_10_102( + .A1(n_10_80), .A2(op1[21]), .ZN(n_10_81) + ); + OAI21_X1_LVT i_10_107( + .A(n_10_82), .B1(n_10_79), .B2(n_10_81), .ZN(n_10_85) + ); + XOR2_X1_LVT i_10_108( + .A(op2[22]), .B(op1[22]), .Z(n_10_86) + ); + INV_X1_LVT i_10_110( + .A(op2[22]), .ZN(n_10_87) + ); + OAI22_X1_LVT i_10_111( + .A1(n_10_85), .A2(n_10_86), .B1(n_10_87), .B2(op1[22]), .ZN(n_10_88) + ); + NOR2_X1_LVT i_10_113( + .A1(n_10_89), .A2(op1[23]), .ZN(n_10_90) + ); + OAI21_X1_LVT i_10_118( + .A(n_10_91), .B1(n_10_88), .B2(n_10_90), .ZN(n_10_94) + ); + XOR2_X1_LVT i_10_119( + .A(op2[24]), .B(op1[24]), .Z(n_10_95) + ); + INV_X1_LVT i_10_121( + .A(op2[24]), .ZN(n_10_96) + ); + OAI22_X1_LVT i_10_122( + .A1(n_10_94), .A2(n_10_95), .B1(n_10_96), .B2(op1[24]), .ZN(n_10_97) + ); + NOR2_X1_LVT i_10_124( + .A1(n_10_98), .A2(op1[25]), .ZN(n_10_99) + ); + OAI21_X1_LVT i_10_129( + .A(n_10_100), .B1(n_10_97), .B2(n_10_99), .ZN(n_10_103) + ); + OAI21_X1_LVT i_10_132( + .A(n_10_105), .B1(n_10_104), .B2(op2[26]), .ZN(n_10_106) + ); + OAI21_X1_LVT i_10_134( + .A(n_10_105), .B1(n_10_103), .B2(n_10_106), .ZN(n_10_107) + ); + XNOR2_X1_LVT i_10_135( + .A(op2[27]), .B(op1[27]), .ZN(n_10_108) + ); + INV_X1_LVT i_10_137( + .A(op1[27]), .ZN(n_10_109) + ); + AOI22_X1_LVT i_10_138( + .A1(n_10_107), .A2(n_10_108), .B1(n_10_109), .B2(op2[27]), .ZN(n_10_110) + ); + XOR2_X1_LVT i_10_139( + .A(op2[28]), .B(op1[28]), .Z(n_10_111) + ); + INV_X1_LVT i_10_141( + .A(op2[28]), .ZN(n_10_112) + ); + OAI22_X1_LVT i_10_142( + .A1(n_10_110), .A2(n_10_111), .B1(n_10_112), .B2(op1[28]), .ZN(n_10_113) + ); + XNOR2_X1_LVT i_10_143( + .A(op2[29]), .B(op1[29]), .ZN(n_10_114) + ); + INV_X1_LVT i_10_145( + .A(op1[29]), .ZN(n_10_115) + ); + AOI22_X1_LVT i_10_146( + .A1(n_10_113), .A2(n_10_114), .B1(n_10_115), .B2(op2[29]), .ZN(n_10_116) + ); + OR2_X1_LVT i_10_148( + .A1(n_10_117), .A2(op1[30]), .ZN(n_10_118) + ); + AOI21_X1_LVT i_10_153( + .A(n_10_121), .B1(n_10_116), .B2(n_10_118), .ZN(n_10_122) + ); + XNOR2_X1_LVT i_10_154( + .A(op1[31]), .B(op2[31]), .ZN(n_10_123) + ); + XNOR2_X1_LVT i_10_155( + .A(n_10_122), .B(n_10_123), .ZN(n_63) + ); + INV_X1_LVT i_0_715( + .A(aluNegAr), .ZN(n_0_682) + ); + NOR2_X1_LVT i_0_612( + .A1(n_0_682), .A2(n_0_582), .ZN(n_0_580) + ); + AOI221_X1_LVT i_0_587( + .A(n_0_556), .B1(n_31), .B2(n_0_581), .C1(n_63), .C2(n_0_580), .ZN(n_0_555) + ); + NOR3_X1_LVT i_0_654( + .A1(aluOp[1]), .A2(aluBypass), .A3(n_0_683), .ZN(n_0_622) + ); + NAND2_X1_LVT i_0_653( + .A1(n_0_684), .A2(n_0_622), .ZN(n_0_621) + ); + INV_X1_LVT i_0_734( + .A(op2[0]), .ZN(n_0_701) + ); + INV_X1_LVT i_0_756( + .A(op2[3]), .ZN(n_0_723) + ); + NOR2_X1_LVT i_0_650( + .A1(op2[4]), .A2(n_0_723), .ZN(n_0_618) + ); + INV_X1_LVT i_0_649( + .A(n_0_618), .ZN(n_0_617) + ); + NOR2_X1_LVT i_0_648( + .A1(op2[4]), .A2(op2[3]), .ZN(n_0_616) + ); + INV_X1_LVT i_0_647( + .A(n_0_616), .ZN(n_0_615) + ); + INV_X1_LVT i_0_771( + .A(op2[4]), .ZN(n_0_738) + ); + INV_X1_LVT i_0_767( + .A(op1[15]), .ZN(n_0_734) + ); + INV_X1_LVT i_0_746( + .A(op1[7]), .ZN(n_0_713) + ); + AOI22_X1_LVT i_0_651( + .A1(n_0_734), .A2(n_0_723), .B1(op2[3]), .B2(n_0_713), .ZN(n_0_619) + ); + OAI222_X1_LVT i_0_646( + .A1(op1[23]), .A2(n_0_617), .B1(op1[31]), .B2(n_0_615), .C1(n_0_738), .C2(n_0_619), + .ZN(n_0_614) + ); + NOR2_X1_LVT i_0_645( + .A1(op2[2]), .A2(n_0_614), .ZN(n_0_613) + ); + NOR2_X1_LVT i_0_696( + .A1(op1[3]), .A2(n_0_723), .ZN(n_0_663) + ); + INV_X1_LVT i_0_739( + .A(op1[11]), .ZN(n_0_706) + ); + AOI21_X1_LVT i_0_644( + .A(n_0_663), .B1(n_0_723), .B2(n_0_706), .ZN(n_0_612) + ); + AOI22_X1_LVT i_0_643( + .A1(op2[4]), .A2(n_0_612), .B1(op1[27]), .B2(n_0_616), .ZN(n_0_611) + ); + INV_X1_LVT i_0_722( + .A(op1[19]), .ZN(n_0_689) + ); + OAI21_X1_LVT i_0_642( + .A(n_0_611), .B1(n_0_689), .B2(n_0_617), .ZN(n_0_610) + ); + AOI21_X1_LVT i_0_641( + .A(n_0_613), .B1(op2[2]), .B2(n_0_610), .ZN(n_0_609) + ); + INV_X1_LVT i_0_761( + .A(op2[1]), .ZN(n_0_728) + ); + OAI22_X1_LVT i_0_640( + .A1(op2[4]), .A2(op1[21]), .B1(n_0_738), .B2(op1[5]), .ZN(n_0_608) + ); + NAND2_X1_LVT i_0_639( + .A1(op2[3]), .A2(n_0_608), .ZN(n_0_607) + ); + INV_X1_LVT i_0_747( + .A(op1[13]), .ZN(n_0_714) + ); + NOR2_X1_LVT i_0_638( + .A1(n_0_738), .A2(op2[3]), .ZN(n_0_606) + ); + INV_X1_LVT i_0_743( + .A(op1[29]), .ZN(n_0_710) + ); + AOI221_X1_LVT i_0_636( + .A(op2[2]), .B1(n_0_714), .B2(n_0_606), .C1(n_0_710), .C2(n_0_616), .ZN(n_0_604) + ); + OAI22_X1_LVT i_0_635( + .A1(op2[4]), .A2(op1[17]), .B1(n_0_738), .B2(op1[1]), .ZN(n_0_603) + ); + INV_X1_LVT i_0_755( + .A(op1[9]), .ZN(n_0_722) + ); + INV_X1_LVT i_0_637( + .A(n_0_606), .ZN(n_0_605) + ); + INV_X1_LVT i_0_732( + .A(op1[25]), .ZN(n_0_699) + ); + OAI222_X1_LVT i_0_634( + .A1(n_0_723), .A2(n_0_603), .B1(n_0_722), .B2(n_0_605), .C1(n_0_699), .C2(n_0_615), + .ZN(n_0_602) + ); + AOI22_X1_LVT i_0_633( + .A1(n_0_607), .A2(n_0_604), .B1(op2[2]), .B2(n_0_602), .ZN(n_0_601) + ); + OAI221_X1_LVT i_0_616( + .A(n_0_701), .B1(op2[1]), .B2(n_0_609), .C1(n_0_728), .C2(n_0_601), .ZN(n_0_584) + ); + INV_X1_LVT i_0_729( + .A(op1[12]), .ZN(n_0_696) + ); + INV_X1_LVT i_0_731( + .A(op1[28]), .ZN(n_0_698) + ); + AOI22_X1_LVT i_0_622( + .A1(n_0_696), .A2(n_0_606), .B1(n_0_698), .B2(n_0_616), .ZN(n_0_590) + ); + INV_X1_LVT i_0_726( + .A(op2[2]), .ZN(n_0_693) + ); + NOR2_X1_LVT i_0_701( + .A1(n_0_738), .A2(op1[4]), .ZN(n_0_668) + ); + INV_X1_LVT i_0_760( + .A(op1[20]), .ZN(n_0_727) + ); + AOI21_X1_LVT i_0_623( + .A(n_0_668), .B1(n_0_738), .B2(n_0_727), .ZN(n_0_591) + ); + OAI211_X1_LVT i_0_621( + .A(n_0_590), .B(n_0_693), .C1(n_0_723), .C2(n_0_591), .ZN(n_0_589) + ); + OAI22_X1_LVT i_0_626( + .A1(op1[16]), .A2(op2[4]), .B1(n_0_738), .B2(op1[0]), .ZN(n_0_594) + ); + INV_X1_LVT i_0_769( + .A(op1[24]), .ZN(n_0_736) + ); + OAI22_X1_LVT i_0_625( + .A1(n_0_723), .A2(n_0_594), .B1(n_0_736), .B2(n_0_615), .ZN(n_0_593) + ); + AOI21_X1_LVT i_0_624( + .A(n_0_593), .B1(op1[8]), .B2(n_0_606), .ZN(n_0_592) + ); + OAI21_X1_LVT i_0_620( + .A(n_0_589), .B1(n_0_693), .B2(n_0_592), .ZN(n_0_588) + ); + INV_X1_LVT i_0_737( + .A(op1[6]), .ZN(n_0_704) + ); + INV_X1_LVT i_0_720( + .A(op1[22]), .ZN(n_0_687) + ); + OAI22_X1_LVT i_0_632( + .A1(n_0_738), .A2(n_0_704), .B1(op2[4]), .B2(n_0_687), .ZN(n_0_600) + ); + OAI221_X1_LVT i_0_631( + .A(n_0_693), .B1(n_0_723), .B2(n_0_600), .C1(op1[14]), .C2(n_0_605), .ZN(n_0_599) + ); + INV_X1_LVT i_0_750( + .A(op1[30]), .ZN(n_0_717) + ); + AOI21_X1_LVT i_0_630( + .A(n_0_599), .B1(n_0_717), .B2(n_0_616), .ZN(n_0_598) + ); + INV_X1_LVT i_0_738( + .A(op1[18]), .ZN(n_0_705) + ); + NOR2_X1_LVT i_0_628( + .A1(n_0_705), .A2(n_0_617), .ZN(n_0_596) + ); + INV_X1_LVT i_0_727( + .A(op1[2]), .ZN(n_0_694) + ); + INV_X1_LVT i_0_766( + .A(op1[10]), .ZN(n_0_733) + ); + OAI22_X1_LVT i_0_629( + .A1(n_0_723), .A2(n_0_694), .B1(n_0_733), .B2(op2[3]), .ZN(n_0_597) + ); + AOI221_X1_LVT i_0_627( + .A(n_0_596), .B1(op1[26]), .B2(n_0_616), .C1(op2[4]), .C2(n_0_597), .ZN(n_0_595) + ); + OAI21_X1_LVT i_0_619( + .A(n_0_728), .B1(n_0_693), .B2(n_0_595), .ZN(n_0_587) + ); + OAI22_X1_LVT i_0_618( + .A1(n_0_728), .A2(n_0_588), .B1(n_0_598), .B2(n_0_587), .ZN(n_0_586) + ); + INV_X1_LVT i_0_617( + .A(n_0_586), .ZN(n_0_585) + ); + OAI21_X1_LVT i_0_615( + .A(n_0_584), .B1(n_0_701), .B2(n_0_585), .ZN(n_0_583) + ); + NOR2_X1_LVT i_0_607( + .A1(op2[4]), .A2(op2[2]), .ZN(n_0_575) + ); + NAND2_X1_LVT i_0_606( + .A1(n_0_723), .A2(n_0_575), .ZN(n_0_574) + ); + INV_X1_LVT i_0_605( + .A(n_0_574), .ZN(n_0_573) + ); + NAND2_X1_LVT i_0_604( + .A1(n_0_728), .A2(n_0_573), .ZN(n_0_572) + ); + NAND2_X1_LVT i_0_611( + .A1(aluOp[2]), .A2(n_0_622), .ZN(n_0_579) + ); + INV_X1_LVT i_0_610( + .A(n_0_579), .ZN(n_0_578) + ); + NAND2_X1_LVT i_0_594( + .A1(n_0_701), .A2(n_0_578), .ZN(n_0_562) + ); + NOR3_X1_LVT i_0_592( + .A1(aluNegAr), .A2(n_0_572), .A3(n_0_562), .ZN(n_0_560) + ); + INV_X1_LVT i_0_600( + .A(n_0_569), .ZN(n_0_568) + ); + OAI21_X1_LVT i_0_595( + .A(n_0_568), .B1(aluOp[1]), .B2(n_0_570), .ZN(n_0_563) + ); + AOI211_X1_LVT i_0_591( + .A(aluBypass), .B(n_0_560), .C1(n_0_692), .C2(n_0_563), .ZN(n_0_559) + ); + OAI221_X1_LVT i_0_586( + .A(n_0_555), .B1(n_0_621), .B2(n_0_583), .C1(n_0_691), .C2(n_0_559), .ZN(result[31]) + ); + NAND2_X1_LVT i_10_150( + .A1(n_10_118), .A2(n_10_119), .ZN(n_10_120) + ); + XNOR2_X1_LVT i_10_151( + .A(n_10_116), .B(n_10_120), .ZN(n_62) + ); + AOI22_X1_LVT i_0_580( + .A1(n_62), .A2(n_0_580), .B1(n_30), .B2(n_0_581), .ZN(n_0_549) + ); + NAND2_X1_LVT i_0_576( + .A1(aluNegAr), .A2(n_0_578), .ZN(n_0_545) + ); + INV_X1_LVT i_0_603( + .A(n_0_572), .ZN(n_0_571) + ); + NOR3_X1_LVT i_0_574( + .A1(n_0_691), .A2(n_0_545), .A3(n_0_571), .ZN(n_0_543) + ); + AOI22_X1_LVT i_0_573( + .A1(n_0_717), .A2(n_0_565), .B1(op1[30]), .B2(n_0_566), .ZN(n_0_542) + ); + AOI21_X1_LVT i_0_572( + .A(n_0_543), .B1(op2[30]), .B2(n_0_542), .ZN(n_0_541) + ); + NAND2_X1_LVT i_0_579( + .A1(op2[0]), .A2(n_0_578), .ZN(n_0_548) + ); + NAND2_X1_LVT i_0_577( + .A1(op1[31]), .A2(n_0_571), .ZN(n_0_546) + ); + OAI211_X1_LVT i_0_571( + .A(n_0_549), .B(n_0_541), .C1(n_0_548), .C2(n_0_546), .ZN(n_0_540) + ); + OAI221_X1_LVT i_0_581( + .A(n_0_681), .B1(op2[30]), .B2(n_0_568), .C1(n_0_572), .C2(n_0_562), .ZN(n_0_550) + ); + AOI21_X1_LVT i_0_570( + .A(n_0_540), .B1(op1[30]), .B2(n_0_550), .ZN(n_0_539) + ); + INV_X1_LVT i_0_752( + .A(op1[23]), .ZN(n_0_719) + ); + OAI222_X1_LVT i_0_585( + .A1(n_0_713), .A2(n_0_605), .B1(n_0_719), .B2(n_0_615), .C1(n_0_734), .C2(n_0_617), + .ZN(n_0_554) + ); + AOI22_X1_LVT i_0_584( + .A1(op2[2]), .A2(n_0_554), .B1(n_0_693), .B2(n_0_610), .ZN(n_0_553) + ); + OAI22_X1_LVT i_0_583( + .A1(n_0_728), .A2(n_0_553), .B1(op2[1]), .B2(n_0_601), .ZN(n_0_552) + ); + AOI22_X1_LVT i_0_582( + .A1(n_0_701), .A2(n_0_585), .B1(op2[0]), .B2(n_0_552), .ZN(n_0_551) + ); + OAI21_X1_LVT i_0_569( + .A(n_0_539), .B1(n_0_621), .B2(n_0_551), .ZN(result[30]) + ); + INV_X1_LVT i_0_578( + .A(n_0_548), .ZN(n_0_547) + ); + NAND3_X1_LVT i_0_562( + .A1(op1[30]), .A2(n_0_571), .A3(n_0_547), .ZN(n_0_532) + ); + XNOR2_X1_LVT i_10_144( + .A(n_10_113), .B(n_10_114), .ZN(n_61) + ); + NAND2_X1_LVT i_0_558( + .A1(n_61), .A2(n_0_580), .ZN(n_0_528) + ); + OAI21_X1_LVT i_0_557( + .A(n_0_681), .B1(op2[29]), .B2(n_0_568), .ZN(n_0_527) + ); + NAND2_X1_LVT i_0_556( + .A1(op1[29]), .A2(n_0_566), .ZN(n_0_526) + ); + AOI22_X1_LVT i_0_555( + .A1(op1[29]), .A2(n_0_527), .B1(op2[29]), .B2(n_0_526), .ZN(n_0_525) + ); + AOI21_X1_LVT i_0_554( + .A(n_0_525), .B1(n_0_710), .B2(n_0_565), .ZN(n_0_524) + ); + AOI211_X1_LVT i_0_553( + .A(n_0_543), .B(n_0_524), .C1(n_29), .C2(n_0_581), .ZN(n_0_523) + ); + AND3_X1_LVT i_0_552( + .A1(n_0_532), .A2(n_0_528), .A3(n_0_523), .ZN(n_0_522) + ); + INV_X1_LVT i_0_652( + .A(n_0_621), .ZN(n_0_620) + ); + NAND2_X1_LVT i_0_565( + .A1(n_0_728), .A2(n_0_588), .ZN(n_0_535) + ); + AOI22_X1_LVT i_0_568( + .A1(n_0_723), .A2(n_0_600), .B1(op1[14]), .B2(n_0_618), .ZN(n_0_538) + ); + AOI22_X1_LVT i_0_567( + .A1(n_0_693), .A2(n_0_595), .B1(op2[2]), .B2(n_0_538), .ZN(n_0_537) + ); + INV_X1_LVT i_0_566( + .A(n_0_537), .ZN(n_0_536) + ); + OAI21_X1_LVT i_0_564( + .A(n_0_535), .B1(n_0_728), .B2(n_0_536), .ZN(n_0_534) + ); + OAI221_X1_LVT i_0_563( + .A(n_0_620), .B1(op2[0]), .B2(n_0_552), .C1(n_0_701), .C2(n_0_534), .ZN(n_0_533) + ); + NAND2_X1_LVT i_0_561( + .A1(op2[1]), .A2(n_0_573), .ZN(n_0_531) + ); + INV_X1_LVT i_0_560( + .A(n_0_531), .ZN(n_0_530) + ); + AOI22_X1_LVT i_0_559( + .A1(op1[31]), .A2(n_0_530), .B1(op1[29]), .B2(n_0_571), .ZN(n_0_529) + ); + OAI211_X1_LVT i_0_551( + .A(n_0_522), .B(n_0_533), .C1(n_0_562), .C2(n_0_529), .ZN(result[29]) + ); + INV_X1_LVT i_0_733( + .A(op2[28]), .ZN(n_0_700) + ); + AOI221_X1_LVT i_0_546( + .A(n_0_700), .B1(op1[28]), .B2(n_0_566), .C1(n_0_698), .C2(n_0_565), .ZN(n_0_517) + ); + OAI21_X1_LVT i_0_543( + .A(n_0_681), .B1(op2[28]), .B2(n_0_568), .ZN(n_0_514) + ); + AOI22_X1_LVT i_0_542( + .A1(n_28), .A2(n_0_581), .B1(op1[28]), .B2(n_0_514), .ZN(n_0_513) + ); + XNOR2_X1_LVT i_10_140( + .A(n_10_110), .B(n_10_111), .ZN(n_60) + ); + NAND2_X1_LVT i_0_544( + .A1(n_60), .A2(n_0_580), .ZN(n_0_515) + ); + NAND2_X1_LVT i_0_545( + .A1(op1[31]), .A2(n_0_574), .ZN(n_0_516) + ); + OAI211_X1_LVT i_0_541( + .A(n_0_513), .B(n_0_515), .C1(n_0_545), .C2(n_0_516), .ZN(n_0_512) + ); + AOI22_X1_LVT i_0_540( + .A1(op1[30]), .A2(n_0_530), .B1(op1[28]), .B2(n_0_571), .ZN(n_0_511) + ); + OAI22_X1_LVT i_0_539( + .A1(n_0_562), .A2(n_0_511), .B1(n_0_548), .B2(n_0_529), .ZN(n_0_510) + ); + NOR3_X1_LVT i_0_538( + .A1(n_0_517), .A2(n_0_512), .A3(n_0_510), .ZN(n_0_509) + ); + OAI22_X1_LVT i_0_550( + .A1(n_0_714), .A2(n_0_617), .B1(op2[3]), .B2(n_0_608), .ZN(n_0_521) + ); + OAI22_X1_LVT i_0_549( + .A1(op2[2]), .A2(n_0_602), .B1(n_0_693), .B2(n_0_521), .ZN(n_0_520) + ); + AOI22_X1_LVT i_0_548( + .A1(op2[1]), .A2(n_0_520), .B1(n_0_728), .B2(n_0_553), .ZN(n_0_519) + ); + OAI22_X1_LVT i_0_547( + .A1(op2[0]), .A2(n_0_534), .B1(n_0_701), .B2(n_0_519), .ZN(n_0_518) + ); + OAI21_X1_LVT i_0_537( + .A(n_0_509), .B1(n_0_621), .B2(n_0_518), .ZN(result[28]) + ); + XNOR2_X1_LVT i_10_136( + .A(n_10_107), .B(n_10_108), .ZN(n_59) + ); + AOI22_X1_LVT i_0_517( + .A1(n_27), .A2(n_0_581), .B1(n_59), .B2(n_0_580), .ZN(n_0_489) + ); + INV_X1_LVT i_0_721( + .A(op1[27]), .ZN(n_0_688) + ); + OAI21_X1_LVT i_0_516( + .A(n_0_681), .B1(op2[27]), .B2(n_0_568), .ZN(n_0_488) + ); + INV_X1_LVT i_0_515( + .A(n_0_488), .ZN(n_0_487) + ); + OAI221_X1_LVT i_0_514( + .A(n_0_489), .B1(n_0_545), .B2(n_0_516), .C1(n_0_688), .C2(n_0_487), .ZN(n_0_486) + ); + OAI21_X1_LVT i_0_530( + .A(op2[1]), .B1(n_0_710), .B2(n_0_574), .ZN(n_0_502) + ); + OAI21_X1_LVT i_0_529( + .A(n_0_728), .B1(n_0_688), .B2(n_0_574), .ZN(n_0_501) + ); + NAND2_X1_LVT i_0_528( + .A1(n_0_502), .A2(n_0_501), .ZN(n_0_500) + ); + AOI21_X1_LVT i_0_527( + .A(n_0_545), .B1(n_0_701), .B2(n_0_500), .ZN(n_0_499) + ); + NAND2_X1_LVT i_0_609( + .A1(n_0_682), .A2(n_0_578), .ZN(n_0_577) + ); + NOR2_X1_LVT i_0_526( + .A1(op2[4]), .A2(n_0_693), .ZN(n_0_498) + ); + NAND2_X1_LVT i_0_525( + .A1(n_0_723), .A2(n_0_498), .ZN(n_0_497) + ); + OAI22_X1_LVT i_0_523( + .A1(n_0_688), .A2(n_0_574), .B1(n_0_691), .B2(n_0_497), .ZN(n_0_495) + ); + OAI21_X1_LVT i_0_522( + .A(n_0_502), .B1(op2[1]), .B2(n_0_495), .ZN(n_0_494) + ); + AOI21_X1_LVT i_0_521( + .A(n_0_577), .B1(n_0_701), .B2(n_0_494), .ZN(n_0_493) + ); + NOR2_X1_LVT i_0_520( + .A1(n_0_499), .A2(n_0_493), .ZN(n_0_492) + ); + AOI21_X1_LVT i_0_519( + .A(n_0_492), .B1(op2[0]), .B2(n_0_511), .ZN(n_0_491) + ); + AOI22_X1_LVT i_0_518( + .A1(n_0_688), .A2(n_0_565), .B1(op1[27]), .B2(n_0_566), .ZN(n_0_490) + ); + AOI211_X1_LVT i_0_513( + .A(n_0_486), .B(n_0_491), .C1(op2[27]), .C2(n_0_490), .ZN(n_0_485) + ); + NOR3_X1_LVT i_0_536( + .A1(op2[4]), .A2(n_0_696), .A3(n_0_723), .ZN(n_0_508) + ); + AOI21_X1_LVT i_0_535( + .A(n_0_508), .B1(n_0_723), .B2(n_0_591), .ZN(n_0_507) + ); + OAI22_X1_LVT i_0_534( + .A1(op2[2]), .A2(n_0_592), .B1(n_0_693), .B2(n_0_507), .ZN(n_0_506) + ); + NOR2_X1_LVT i_0_533( + .A1(n_0_728), .A2(n_0_506), .ZN(n_0_505) + ); + AOI21_X1_LVT i_0_532( + .A(n_0_505), .B1(n_0_728), .B2(n_0_536), .ZN(n_0_504) + ); + OAI22_X1_LVT i_0_531( + .A1(n_0_701), .A2(n_0_504), .B1(op2[0]), .B2(n_0_519), .ZN(n_0_503) + ); + OAI21_X1_LVT i_0_512( + .A(n_0_485), .B1(n_0_621), .B2(n_0_503), .ZN(result[27]) + ); + OAI21_X1_LVT i_0_500( + .A(n_0_681), .B1(op2[26]), .B2(n_0_568), .ZN(n_0_473) + ); + NAND2_X1_LVT i_0_499( + .A1(op1[26]), .A2(n_0_473), .ZN(n_0_472) + ); + XNOR2_X1_LVT i_10_133( + .A(n_10_103), .B(n_10_106), .ZN(n_58) + ); + AOI22_X1_LVT i_0_498( + .A1(n_58), .A2(n_0_580), .B1(n_26), .B2(n_0_581), .ZN(n_0_471) + ); + INV_X1_LVT i_0_744( + .A(op1[26]), .ZN(n_0_711) + ); + OAI221_X1_LVT i_0_501( + .A(op2[26]), .B1(op1[26]), .B2(n_0_564), .C1(n_0_711), .C2(n_0_567), .ZN(n_0_474) + ); + NAND3_X1_LVT i_0_497( + .A1(n_0_472), .A2(n_0_471), .A3(n_0_474), .ZN(n_0_470) + ); + INV_X1_LVT i_0_524( + .A(n_0_497), .ZN(n_0_496) + ); + AOI22_X1_LVT i_0_505( + .A1(op1[30]), .A2(n_0_496), .B1(op1[26]), .B2(n_0_573), .ZN(n_0_478) + ); + NOR2_X1_LVT i_0_504( + .A1(op2[1]), .A2(n_0_478), .ZN(n_0_477) + ); + AOI21_X1_LVT i_0_503( + .A(n_0_477), .B1(op1[28]), .B2(n_0_530), .ZN(n_0_476) + ); + NAND2_X1_LVT i_0_502( + .A1(n_0_701), .A2(n_0_476), .ZN(n_0_475) + ); + AOI21_X1_LVT i_0_489( + .A(n_0_577), .B1(op2[0]), .B2(n_0_494), .ZN(n_0_462) + ); + AOI21_X1_LVT i_0_488( + .A(n_0_470), .B1(n_0_475), .B2(n_0_462), .ZN(n_0_461) + ); + AOI21_X1_LVT i_0_511( + .A(n_0_616), .B1(n_0_738), .B2(n_0_706), .ZN(n_0_484) + ); + AOI21_X1_LVT i_0_510( + .A(n_0_484), .B1(n_0_723), .B2(op1[19]), .ZN(n_0_483) + ); + INV_X1_LVT i_0_757( + .A(op1[3]), .ZN(n_0_724) + ); + NOR2_X1_LVT i_0_687( + .A1(n_0_724), .A2(op2[3]), .ZN(n_0_654) + ); + INV_X1_LVT i_0_686( + .A(n_0_654), .ZN(n_0_653) + ); + AOI21_X1_LVT i_0_509( + .A(n_0_483), .B1(op2[4]), .B2(n_0_653), .ZN(n_0_482) + ); + AOI22_X1_LVT i_0_508( + .A1(n_0_693), .A2(n_0_554), .B1(op2[2]), .B2(n_0_482), .ZN(n_0_481) + ); + OAI22_X1_LVT i_0_507( + .A1(n_0_728), .A2(n_0_481), .B1(op2[1]), .B2(n_0_520), .ZN(n_0_480) + ); + AOI22_X1_LVT i_0_506( + .A1(op2[0]), .A2(n_0_480), .B1(n_0_701), .B2(n_0_504), .ZN(n_0_479) + ); + NAND3_X1_LVT i_0_491( + .A1(op2[0]), .A2(n_0_516), .A3(n_0_500), .ZN(n_0_464) + ); + NAND2_X1_LVT i_0_494( + .A1(op1[31]), .A2(n_0_615), .ZN(n_0_467) + ); + OAI21_X1_LVT i_0_492( + .A(n_0_467), .B1(n_0_728), .B2(n_0_516), .ZN(n_0_465) + ); + OAI21_X1_LVT i_0_490( + .A(n_0_464), .B1(n_0_475), .B2(n_0_465), .ZN(n_0_463) + ); + OAI221_X1_LVT i_0_487( + .A(n_0_461), .B1(n_0_621), .B2(n_0_479), .C1(n_0_545), .C2(n_0_463), .ZN(result[26]) + ); + INV_X1_LVT i_10_126( + .A(n_10_100), .ZN(n_10_101) + ); + NOR2_X1_LVT i_10_127( + .A1(n_10_99), .A2(n_10_101), .ZN(n_10_102) + ); + XNOR2_X1_LVT i_10_128( + .A(n_10_97), .B(n_10_102), .ZN(n_57) + ); + AOI22_X1_LVT i_0_479( + .A1(n_57), .A2(n_0_580), .B1(n_25), .B2(n_0_581), .ZN(n_0_453) + ); + INV_X1_LVT i_0_730( + .A(op2[25]), .ZN(n_0_697) + ); + AOI21_X1_LVT i_0_478( + .A(aluBypass), .B1(n_0_697), .B2(n_0_569), .ZN(n_0_452) + ); + AOI22_X1_LVT i_0_480( + .A1(op1[25]), .A2(n_0_567), .B1(n_0_699), .B2(n_0_564), .ZN(n_0_454) + ); + OAI221_X1_LVT i_0_477( + .A(n_0_453), .B1(n_0_699), .B2(n_0_452), .C1(n_0_697), .C2(n_0_454), .ZN(n_0_451) + ); + INV_X1_LVT i_0_575( + .A(n_0_545), .ZN(n_0_544) + ); + AOI21_X1_LVT i_0_476( + .A(n_0_451), .B1(n_0_544), .B2(n_0_465), .ZN(n_0_450) + ); + AOI22_X1_LVT i_0_475( + .A1(op1[29]), .A2(n_0_496), .B1(op1[25]), .B2(n_0_573), .ZN(n_0_449) + ); + NAND2_X1_LVT i_0_474( + .A1(n_0_728), .A2(n_0_449), .ZN(n_0_448) + ); + OAI21_X1_LVT i_0_473( + .A(n_0_448), .B1(n_0_728), .B2(n_0_495), .ZN(n_0_447) + ); + OAI22_X1_LVT i_0_472( + .A1(n_0_548), .A2(n_0_476), .B1(n_0_562), .B2(n_0_447), .ZN(n_0_446) + ); + INV_X1_LVT i_0_471( + .A(n_0_446), .ZN(n_0_445) + ); + OAI222_X1_LVT i_0_486( + .A1(n_0_733), .A2(n_0_617), .B1(n_0_694), .B2(n_0_605), .C1(n_0_705), .C2(n_0_615), + .ZN(n_0_460) + ); + NOR2_X1_LVT i_0_485( + .A1(n_0_693), .A2(n_0_460), .ZN(n_0_459) + ); + AOI21_X1_LVT i_0_484( + .A(n_0_459), .B1(n_0_693), .B2(n_0_538), .ZN(n_0_458) + ); + OAI22_X1_LVT i_0_483( + .A1(n_0_728), .A2(n_0_458), .B1(op2[1]), .B2(n_0_506), .ZN(n_0_457) + ); + INV_X1_LVT i_0_482( + .A(n_0_457), .ZN(n_0_456) + ); + OAI221_X1_LVT i_0_481( + .A(n_0_620), .B1(n_0_701), .B2(n_0_456), .C1(op2[0]), .C2(n_0_480), .ZN(n_0_455) + ); + NAND3_X1_LVT i_0_470( + .A1(n_0_450), .A2(n_0_445), .A3(n_0_455), .ZN(result[25]) + ); + INV_X1_LVT i_0_493( + .A(n_0_467), .ZN(n_0_466) + ); + OAI211_X1_LVT i_0_455( + .A(n_0_544), .B(n_0_465), .C1(op2[0]), .C2(n_0_466), .ZN(n_0_430) + ); + OAI21_X1_LVT i_0_462( + .A(n_0_681), .B1(op2[24]), .B2(n_0_568), .ZN(n_0_437) + ); + XNOR2_X1_LVT i_10_120( + .A(n_10_94), .B(n_10_95), .ZN(n_56) + ); + AOI222_X1_LVT i_0_461( + .A1(op1[24]), .A2(n_0_437), .B1(n_56), .B2(n_0_580), .C1(n_24), .C2(n_0_581), + .ZN(n_0_436) + ); + INV_X1_LVT i_0_460( + .A(n_0_436), .ZN(n_0_435) + ); + AOI22_X1_LVT i_0_458( + .A1(op1[24]), .A2(n_0_573), .B1(op1[28]), .B2(n_0_496), .ZN(n_0_433) + ); + OAI22_X1_LVT i_0_457( + .A1(op2[1]), .A2(n_0_433), .B1(n_0_728), .B2(n_0_478), .ZN(n_0_432) + ); + INV_X1_LVT i_0_456( + .A(n_0_432), .ZN(n_0_431) + ); + OAI22_X1_LVT i_0_454( + .A1(n_0_562), .A2(n_0_431), .B1(n_0_548), .B2(n_0_447), .ZN(n_0_429) + ); + AOI22_X1_LVT i_0_459( + .A1(n_0_736), .A2(n_0_565), .B1(op1[24]), .B2(n_0_566), .ZN(n_0_434) + ); + AOI211_X1_LVT i_0_453( + .A(n_0_435), .B(n_0_429), .C1(op2[24]), .C2(n_0_434), .ZN(n_0_428) + ); + NAND2_X1_LVT i_0_467( + .A1(n_0_693), .A2(n_0_521), .ZN(n_0_442) + ); + NOR2_X1_LVT i_0_469( + .A1(op2[3]), .A2(n_0_603), .ZN(n_0_444) + ); + AOI21_X1_LVT i_0_468( + .A(n_0_444), .B1(op1[9]), .B2(n_0_618), .ZN(n_0_443) + ); + OAI21_X1_LVT i_0_466( + .A(n_0_442), .B1(n_0_693), .B2(n_0_443), .ZN(n_0_441) + ); + NAND2_X1_LVT i_0_465( + .A1(op2[1]), .A2(n_0_441), .ZN(n_0_440) + ); + OAI21_X1_LVT i_0_464( + .A(n_0_440), .B1(op2[1]), .B2(n_0_481), .ZN(n_0_439) + ); + OAI221_X1_LVT i_0_463( + .A(n_0_620), .B1(op2[0]), .B2(n_0_456), .C1(n_0_701), .C2(n_0_439), .ZN(n_0_438) + ); + NAND3_X1_LVT i_0_452( + .A1(n_0_430), .A2(n_0_428), .A3(n_0_438), .ZN(result[24]) + ); + INV_X1_LVT i_0_751( + .A(op2[23]), .ZN(n_0_718) + ); + AOI221_X1_LVT i_0_440( + .A(n_0_718), .B1(op1[23]), .B2(n_0_566), .C1(n_0_719), .C2(n_0_565), .ZN(n_0_416) + ); + INV_X1_LVT i_10_115( + .A(n_10_91), .ZN(n_10_92) + ); + NOR2_X1_LVT i_10_116( + .A1(n_10_90), .A2(n_10_92), .ZN(n_10_93) + ); + XNOR2_X1_LVT i_10_117( + .A(n_10_88), .B(n_10_93), .ZN(n_55) + ); + AOI222_X1_LVT i_0_438( + .A1(n_23), .A2(n_0_581), .B1(n_0_544), .B2(n_0_466), .C1(n_55), .C2(n_0_580), + .ZN(n_0_414) + ); + OAI21_X1_LVT i_0_437( + .A(n_0_414), .B1(n_0_548), .B2(n_0_431), .ZN(n_0_413) + ); + OAI21_X1_LVT i_0_439( + .A(n_0_681), .B1(op2[23]), .B2(n_0_568), .ZN(n_0_415) + ); + AOI211_X1_LVT i_0_436( + .A(n_0_416), .B(n_0_413), .C1(op1[23]), .C2(n_0_415), .ZN(n_0_412) + ); + AOI22_X1_LVT i_0_444( + .A1(n_0_723), .A2(n_0_719), .B1(op2[3]), .B2(n_0_691), .ZN(n_0_420) + ); + AOI22_X1_LVT i_0_443( + .A1(n_0_575), .A2(n_0_420), .B1(op1[27]), .B2(n_0_496), .ZN(n_0_419) + ); + AOI22_X1_LVT i_0_442( + .A1(op2[1]), .A2(n_0_449), .B1(n_0_728), .B2(n_0_419), .ZN(n_0_418) + ); + INV_X1_LVT i_0_441( + .A(n_0_418), .ZN(n_0_417) + ); + NAND2_X1_LVT i_0_447( + .A1(n_0_728), .A2(n_0_458), .ZN(n_0_423) + ); + NOR2_X1_LVT i_0_451( + .A1(op2[3]), .A2(n_0_594), .ZN(n_0_427) + ); + AOI21_X1_LVT i_0_450( + .A(n_0_427), .B1(op1[8]), .B2(n_0_618), .ZN(n_0_426) + ); + OAI22_X1_LVT i_0_449( + .A1(n_0_693), .A2(n_0_426), .B1(op2[2]), .B2(n_0_507), .ZN(n_0_425) + ); + INV_X1_LVT i_0_448( + .A(n_0_425), .ZN(n_0_424) + ); + OAI21_X1_LVT i_0_446( + .A(n_0_423), .B1(n_0_728), .B2(n_0_424), .ZN(n_0_422) + ); + AOI22_X1_LVT i_0_445( + .A1(op2[0]), .A2(n_0_422), .B1(n_0_701), .B2(n_0_439), .ZN(n_0_421) + ); + OAI221_X1_LVT i_0_435( + .A(n_0_412), .B1(n_0_562), .B2(n_0_417), .C1(n_0_621), .C2(n_0_421), .ZN(result[23]) + ); + XNOR2_X1_LVT i_10_109( + .A(n_10_85), .B(n_10_86), .ZN(n_54) + ); + AOI22_X1_LVT i_0_419( + .A1(n_54), .A2(n_0_580), .B1(n_22), .B2(n_0_581), .ZN(n_0_396) + ); + INV_X1_LVT i_0_719( + .A(op2[22]), .ZN(n_0_686) + ); + AOI21_X1_LVT i_0_420( + .A(aluBypass), .B1(n_0_686), .B2(n_0_569), .ZN(n_0_397) + ); + OAI21_X1_LVT i_0_418( + .A(n_0_396), .B1(n_0_687), .B2(n_0_397), .ZN(n_0_395) + ); + AOI22_X1_LVT i_0_421( + .A1(op1[22]), .A2(n_0_566), .B1(n_0_687), .B2(n_0_565), .ZN(n_0_398) + ); + AOI21_X1_LVT i_0_417( + .A(n_0_395), .B1(op2[22]), .B2(n_0_398), .ZN(n_0_394) + ); + NAND2_X1_LVT i_0_432( + .A1(n_0_728), .A2(n_0_441), .ZN(n_0_409) + ); + AND2_X1_LVT i_0_434( + .A1(n_0_738), .A2(n_0_619), .ZN(n_0_411) + ); + AOI22_X1_LVT i_0_433( + .A1(n_0_693), .A2(n_0_482), .B1(op2[2]), .B2(n_0_411), .ZN(n_0_410) + ); + OAI21_X1_LVT i_0_431( + .A(n_0_409), .B1(n_0_728), .B2(n_0_410), .ZN(n_0_408) + ); + OAI22_X1_LVT i_0_430( + .A1(n_0_701), .A2(n_0_408), .B1(op2[0]), .B2(n_0_422), .ZN(n_0_407) + ); + AOI22_X1_LVT i_0_429( + .A1(n_0_723), .A2(n_0_687), .B1(op2[3]), .B2(n_0_717), .ZN(n_0_406) + ); + AOI22_X1_LVT i_0_428( + .A1(n_0_575), .A2(n_0_406), .B1(op1[26]), .B2(n_0_496), .ZN(n_0_405) + ); + AND2_X1_LVT i_0_427( + .A1(n_0_728), .A2(n_0_405), .ZN(n_0_404) + ); + AOI21_X1_LVT i_0_426( + .A(n_0_404), .B1(op2[1]), .B2(n_0_433), .ZN(n_0_403) + ); + INV_X1_LVT i_0_425( + .A(n_0_403), .ZN(n_0_402) + ); + OAI222_X1_LVT i_0_424( + .A1(n_0_545), .A2(n_0_467), .B1(n_0_701), .B2(n_0_417), .C1(op2[0]), .C2(n_0_402), + .ZN(n_0_401) + ); + NOR2_X1_LVT i_0_496( + .A1(n_0_738), .A2(n_0_691), .ZN(n_0_469) + ); + INV_X1_LVT i_0_495( + .A(n_0_469), .ZN(n_0_468) + ); + NAND3_X1_LVT i_0_423( + .A1(n_0_693), .A2(n_0_468), .A3(n_0_404), .ZN(n_0_400) + ); + OAI21_X1_LVT i_0_422( + .A(n_0_401), .B1(op2[0]), .B2(n_0_400), .ZN(n_0_399) + ); + OAI221_X1_LVT i_0_416( + .A(n_0_394), .B1(n_0_621), .B2(n_0_407), .C1(n_0_579), .C2(n_0_399), .ZN(result[22]) + ); + INV_X1_LVT i_0_759( + .A(op1[21]), .ZN(n_0_726) + ); + AOI22_X1_LVT i_0_399( + .A1(op1[21]), .A2(n_0_566), .B1(n_0_726), .B2(n_0_565), .ZN(n_0_377) + ); + NOR2_X1_LVT i_0_692( + .A1(n_0_726), .A2(op2[21]), .ZN(n_0_659) + ); + AOI222_X1_LVT i_0_398( + .A1(op2[21]), .A2(n_0_377), .B1(n_21), .B2(n_0_581), .C1(n_0_659), .C2(n_0_569), + .ZN(n_0_376) + ); + INV_X1_LVT i_0_397( + .A(n_0_376), .ZN(n_0_375) + ); + INV_X1_LVT i_10_104( + .A(n_10_82), .ZN(n_10_83) + ); + NOR2_X1_LVT i_10_105( + .A1(n_10_81), .A2(n_10_83), .ZN(n_10_84) + ); + XNOR2_X1_LVT i_10_106( + .A(n_10_79), .B(n_10_84), .ZN(n_53) + ); + AOI221_X1_LVT i_0_396( + .A(n_0_375), .B1(n_53), .B2(n_0_580), .C1(op1[21]), .C2(aluBypass), .ZN(n_0_374) + ); + INV_X1_LVT i_0_608( + .A(n_0_577), .ZN(n_0_576) + ); + NAND2_X1_LVT i_0_403( + .A1(op2[0]), .A2(n_0_402), .ZN(n_0_381) + ); + AND2_X1_LVT i_0_410( + .A1(op2[1]), .A2(n_0_419), .ZN(n_0_388) + ); + OAI22_X1_LVT i_0_408( + .A1(n_0_723), .A2(n_0_710), .B1(n_0_726), .B2(op2[3]), .ZN(n_0_386) + ); + AOI22_X1_LVT i_0_407( + .A1(n_0_575), .A2(n_0_386), .B1(op1[25]), .B2(n_0_496), .ZN(n_0_385) + ); + AOI21_X1_LVT i_0_395( + .A(n_0_388), .B1(n_0_728), .B2(n_0_385), .ZN(n_0_373) + ); + OAI211_X1_LVT i_0_394( + .A(n_0_576), .B(n_0_381), .C1(op2[0]), .C2(n_0_373), .ZN(n_0_372) + ); + AOI21_X1_LVT i_0_402( + .A(n_0_381), .B1(n_0_466), .B2(n_0_400), .ZN(n_0_380) + ); + INV_X1_LVT i_0_401( + .A(n_0_380), .ZN(n_0_379) + ); + NOR2_X1_LVT i_0_409( + .A1(n_0_575), .A2(n_0_467), .ZN(n_0_387) + ); + INV_X1_LVT i_0_406( + .A(n_0_385), .ZN(n_0_384) + ); + NOR2_X1_LVT i_0_405( + .A1(n_0_387), .A2(n_0_384), .ZN(n_0_383) + ); + AOI22_X1_LVT i_0_404( + .A1(n_0_467), .A2(n_0_388), .B1(n_0_728), .B2(n_0_383), .ZN(n_0_382) + ); + OAI211_X1_LVT i_0_400( + .A(n_0_544), .B(n_0_379), .C1(op2[0]), .C2(n_0_382), .ZN(n_0_378) + ); + AOI22_X1_LVT i_0_415( + .A1(op1[14]), .A2(n_0_616), .B1(op1[6]), .B2(n_0_618), .ZN(n_0_393) + ); + NOR2_X1_LVT i_0_414( + .A1(n_0_693), .A2(n_0_393), .ZN(n_0_392) + ); + AOI21_X1_LVT i_0_413( + .A(n_0_392), .B1(n_0_693), .B2(n_0_460), .ZN(n_0_391) + ); + OAI22_X1_LVT i_0_412( + .A1(n_0_728), .A2(n_0_391), .B1(op2[1]), .B2(n_0_424), .ZN(n_0_390) + ); + OAI221_X1_LVT i_0_411( + .A(n_0_620), .B1(op2[0]), .B2(n_0_408), .C1(n_0_701), .C2(n_0_390), .ZN(n_0_389) + ); + NAND4_X1_LVT i_0_393( + .A1(n_0_374), .A2(n_0_372), .A3(n_0_378), .A4(n_0_389), .ZN(result[21]) + ); + OAI221_X1_LVT i_0_388( + .A(op2[20]), .B1(n_0_727), .B2(n_0_567), .C1(op1[20]), .C2(n_0_564), .ZN(n_0_367) + ); + NOR2_X1_LVT i_0_691( + .A1(n_0_727), .A2(op2[20]), .ZN(n_0_658) + ); + AOI22_X1_LVT i_0_387( + .A1(op1[20]), .A2(aluBypass), .B1(n_0_658), .B2(n_0_569), .ZN(n_0_366) + ); + XNOR2_X1_LVT i_10_98( + .A(n_10_76), .B(n_10_77), .ZN(n_52) + ); + AOI22_X1_LVT i_0_386( + .A1(n_52), .A2(n_0_580), .B1(n_20), .B2(n_0_581), .ZN(n_0_365) + ); + AOI221_X1_LVT i_0_392( + .A(op2[4]), .B1(n_0_727), .B2(n_0_723), .C1(op2[3]), .C2(n_0_698), .ZN(n_0_371) + ); + AOI22_X1_LVT i_0_391( + .A1(op1[24]), .A2(n_0_496), .B1(n_0_693), .B2(n_0_371), .ZN(n_0_370) + ); + OAI22_X1_LVT i_0_390( + .A1(op2[1]), .A2(n_0_370), .B1(n_0_728), .B2(n_0_405), .ZN(n_0_369) + ); + OAI221_X1_LVT i_0_385( + .A(n_0_576), .B1(n_0_701), .B2(n_0_373), .C1(op2[0]), .C2(n_0_369), .ZN(n_0_364) + ); + AND4_X1_LVT i_0_384( + .A1(n_0_367), .A2(n_0_366), .A3(n_0_365), .A4(n_0_364), .ZN(n_0_363) + ); + AOI22_X1_LVT i_0_383( + .A1(op1[13]), .A2(n_0_616), .B1(op1[5]), .B2(n_0_618), .ZN(n_0_362) + ); + AOI22_X1_LVT i_0_382( + .A1(op2[2]), .A2(n_0_362), .B1(n_0_693), .B2(n_0_443), .ZN(n_0_361) + ); + NAND2_X1_LVT i_0_381( + .A1(op2[1]), .A2(n_0_361), .ZN(n_0_360) + ); + OAI21_X1_LVT i_0_380( + .A(n_0_360), .B1(op2[1]), .B2(n_0_410), .ZN(n_0_359) + ); + OAI221_X1_LVT i_0_379( + .A(n_0_620), .B1(n_0_701), .B2(n_0_359), .C1(op2[0]), .C2(n_0_390), .ZN(n_0_358) + ); + OR2_X1_LVT i_0_389( + .A1(n_0_387), .A2(n_0_369), .ZN(n_0_368) + ); + AOI22_X1_LVT i_0_378( + .A1(op2[0]), .A2(n_0_382), .B1(n_0_701), .B2(n_0_368), .ZN(n_0_357) + ); + OAI211_X1_LVT i_0_377( + .A(n_0_363), .B(n_0_358), .C1(n_0_545), .C2(n_0_357), .ZN(result[20]) + ); + OAI22_X1_LVT i_0_370( + .A1(op2[3]), .A2(n_0_689), .B1(n_0_723), .B2(n_0_688), .ZN(n_0_350) + ); + AND2_X1_LVT i_0_369( + .A1(n_0_738), .A2(n_0_350), .ZN(n_0_349) + ); + AOI22_X1_LVT i_0_368( + .A1(n_0_498), .A2(n_0_420), .B1(n_0_693), .B2(n_0_349), .ZN(n_0_348) + ); + AND2_X1_LVT i_0_367( + .A1(n_0_728), .A2(n_0_348), .ZN(n_0_347) + ); + AOI21_X1_LVT i_0_359( + .A(n_0_347), .B1(op2[1]), .B2(n_0_385), .ZN(n_0_339) + ); + OAI221_X1_LVT i_0_357( + .A(n_0_576), .B1(n_0_701), .B2(n_0_369), .C1(op2[0]), .C2(n_0_339), .ZN(n_0_337) + ); + NAND2_X1_LVT i_0_363( + .A1(n_19), .A2(n_0_581), .ZN(n_0_343) + ); + INV_X1_LVT i_0_723( + .A(op2[19]), .ZN(n_0_690) + ); + AOI221_X1_LVT i_0_364( + .A(n_0_690), .B1(n_0_689), .B2(n_0_565), .C1(op1[19]), .C2(n_0_566), .ZN(n_0_344) + ); + XNOR2_X1_LVT i_10_94( + .A(n_10_73), .B(n_10_74), .ZN(n_51) + ); + AOI221_X1_LVT i_0_361( + .A(n_0_344), .B1(op1[19]), .B2(aluBypass), .C1(n_51), .C2(n_0_580), .ZN(n_0_341) + ); + NAND3_X1_LVT i_0_362( + .A1(n_0_690), .A2(op1[19]), .A3(n_0_569), .ZN(n_0_342) + ); + NAND3_X1_LVT i_0_360( + .A1(n_0_343), .A2(n_0_341), .A3(n_0_342), .ZN(n_0_340) + ); + AOI22_X1_LVT i_0_376( + .A1(op1[12]), .A2(n_0_616), .B1(op1[4]), .B2(n_0_618), .ZN(n_0_356) + ); + OAI22_X1_LVT i_0_375( + .A1(n_0_693), .A2(n_0_356), .B1(op2[2]), .B2(n_0_426), .ZN(n_0_355) + ); + INV_X1_LVT i_0_374( + .A(n_0_355), .ZN(n_0_354) + ); + OAI22_X1_LVT i_0_373( + .A1(op2[1]), .A2(n_0_391), .B1(n_0_728), .B2(n_0_354), .ZN(n_0_353) + ); + AOI22_X1_LVT i_0_372( + .A1(n_0_701), .A2(n_0_359), .B1(op2[0]), .B2(n_0_353), .ZN(n_0_352) + ); + INV_X1_LVT i_0_371( + .A(n_0_352), .ZN(n_0_351) + ); + AOI21_X1_LVT i_0_358( + .A(n_0_340), .B1(n_0_620), .B2(n_0_351), .ZN(n_0_338) + ); + AOI22_X1_LVT i_0_366( + .A1(n_0_468), .A2(n_0_347), .B1(op2[1]), .B2(n_0_383), .ZN(n_0_346) + ); + AOI22_X1_LVT i_0_365( + .A1(n_0_701), .A2(n_0_346), .B1(op2[0]), .B2(n_0_368), .ZN(n_0_345) + ); + OAI211_X1_LVT i_0_356( + .A(n_0_337), .B(n_0_338), .C1(n_0_545), .C2(n_0_345), .ZN(result[19]) + ); + XNOR2_X1_LVT i_10_90( + .A(n_10_70), .B(n_10_71), .ZN(n_50) + ); + NAND2_X1_LVT i_0_342( + .A1(n_50), .A2(n_0_580), .ZN(n_0_323) + ); + OAI21_X1_LVT i_0_343( + .A(n_0_681), .B1(op2[18]), .B2(n_0_568), .ZN(n_0_324) + ); + AOI22_X1_LVT i_0_341( + .A1(op1[18]), .A2(n_0_324), .B1(n_18), .B2(n_0_581), .ZN(n_0_322) + ); + OAI221_X1_LVT i_0_340( + .A(op2[18]), .B1(n_0_705), .B2(n_0_567), .C1(op1[18]), .C2(n_0_564), .ZN(n_0_321) + ); + NAND3_X1_LVT i_0_339( + .A1(n_0_323), .A2(n_0_322), .A3(n_0_321), .ZN(n_0_320) + ); + OAI22_X1_LVT i_0_351( + .A1(op2[3]), .A2(n_0_705), .B1(n_0_723), .B2(n_0_711), .ZN(n_0_332) + ); + AND2_X1_LVT i_0_350( + .A1(n_0_738), .A2(n_0_332), .ZN(n_0_331) + ); + AOI22_X1_LVT i_0_349( + .A1(n_0_498), .A2(n_0_406), .B1(n_0_693), .B2(n_0_331), .ZN(n_0_330) + ); + NAND2_X1_LVT i_0_348( + .A1(n_0_728), .A2(n_0_330), .ZN(n_0_329) + ); + NAND2_X1_LVT i_0_347( + .A1(op2[1]), .A2(n_0_370), .ZN(n_0_328) + ); + AND2_X1_LVT i_0_338( + .A1(n_0_329), .A2(n_0_328), .ZN(n_0_319) + ); + OAI22_X1_LVT i_0_337( + .A1(op2[0]), .A2(n_0_319), .B1(n_0_701), .B2(n_0_339), .ZN(n_0_318) + ); + INV_X1_LVT i_0_336( + .A(n_0_318), .ZN(n_0_317) + ); + AOI21_X1_LVT i_0_335( + .A(n_0_320), .B1(n_0_578), .B2(n_0_317), .ZN(n_0_316) + ); + OAI22_X1_LVT i_0_346( + .A1(n_0_469), .A2(n_0_329), .B1(n_0_387), .B2(n_0_328), .ZN(n_0_327) + ); + NAND2_X1_LVT i_0_344( + .A1(n_0_544), .A2(n_0_346), .ZN(n_0_325) + ); + NAND2_X1_LVT i_0_354( + .A1(n_0_728), .A2(n_0_361), .ZN(n_0_335) + ); + AOI22_X1_LVT i_0_355( + .A1(n_0_612), .A2(n_0_498), .B1(n_0_693), .B2(n_0_411), .ZN(n_0_336) + ); + OAI21_X1_LVT i_0_353( + .A(n_0_335), .B1(n_0_728), .B2(n_0_336), .ZN(n_0_334) + ); + AOI22_X1_LVT i_0_352( + .A1(n_0_701), .A2(n_0_353), .B1(op2[0]), .B2(n_0_334), .ZN(n_0_333) + ); + OAI221_X1_LVT i_0_334( + .A(n_0_316), .B1(n_0_327), .B2(n_0_325), .C1(n_0_621), .C2(n_0_333), .ZN(result[18]) + ); + NAND2_X1_LVT i_0_325( + .A1(n_17), .A2(n_0_581), .ZN(n_0_307) + ); + INV_X1_LVT i_0_765( + .A(op1[17]), .ZN(n_0_732) + ); + AOI22_X1_LVT i_0_324( + .A1(n_0_732), .A2(n_0_565), .B1(op1[17]), .B2(n_0_566), .ZN(n_0_306) + ); + NOR2_X1_LVT i_0_693( + .A1(n_0_732), .A2(op2[17]), .ZN(n_0_660) + ); + XNOR2_X1_LVT i_10_86( + .A(n_10_67), .B(n_10_68), .ZN(n_49) + ); + AOI222_X1_LVT i_0_323( + .A1(op2[17]), .A2(n_0_306), .B1(n_0_660), .B2(n_0_569), .C1(n_49), .C2(n_0_580), + .ZN(n_0_305) + ); + OAI211_X1_LVT i_0_322( + .A(n_0_307), .B(n_0_305), .C1(n_0_732), .C2(n_0_681), .ZN(n_0_304) + ); + AOI22_X1_LVT i_0_331( + .A1(op2[3]), .A2(op1[25]), .B1(op1[17]), .B2(n_0_723), .ZN(n_0_313) + ); + NOR2_X1_LVT i_0_330( + .A1(op2[4]), .A2(n_0_313), .ZN(n_0_312) + ); + AOI22_X1_LVT i_0_329( + .A1(n_0_498), .A2(n_0_386), .B1(n_0_693), .B2(n_0_312), .ZN(n_0_311) + ); + OAI22_X1_LVT i_0_328( + .A1(op2[1]), .A2(n_0_311), .B1(n_0_728), .B2(n_0_348), .ZN(n_0_310) + ); + OR2_X1_LVT i_0_327( + .A1(op2[0]), .A2(n_0_310), .ZN(n_0_309) + ); + OAI21_X1_LVT i_0_321( + .A(n_0_576), .B1(n_0_701), .B2(n_0_319), .ZN(n_0_303) + ); + INV_X1_LVT i_0_320( + .A(n_0_303), .ZN(n_0_302) + ); + AOI21_X1_LVT i_0_319( + .A(n_0_304), .B1(n_0_309), .B2(n_0_302), .ZN(n_0_301) + ); + INV_X1_LVT i_0_345( + .A(n_0_327), .ZN(n_0_326) + ); + OAI22_X1_LVT i_0_326( + .A1(n_0_701), .A2(n_0_326), .B1(n_0_469), .B2(n_0_309), .ZN(n_0_308) + ); + NOR2_X1_LVT i_0_318( + .A1(op2[2]), .A2(n_0_393), .ZN(n_0_300) + ); + AOI21_X1_LVT i_0_317( + .A(n_0_300), .B1(n_0_597), .B2(n_0_498), .ZN(n_0_299) + ); + OAI22_X1_LVT i_0_316( + .A1(n_0_728), .A2(n_0_299), .B1(op2[1]), .B2(n_0_354), .ZN(n_0_298) + ); + OAI22_X1_LVT i_0_315( + .A1(op2[0]), .A2(n_0_334), .B1(n_0_701), .B2(n_0_298), .ZN(n_0_297) + ); + OAI221_X1_LVT i_0_314( + .A(n_0_301), .B1(n_0_545), .B2(n_0_308), .C1(n_0_621), .C2(n_0_297), .ZN(result[17]) + ); + XNOR2_X1_LVT i_10_82( + .A(n_10_64), .B(n_10_65), .ZN(n_48) + ); + AOI22_X1_LVT i_0_301( + .A1(n_48), .A2(n_0_580), .B1(n_16), .B2(n_0_581), .ZN(n_0_284) + ); + NAND2_X1_LVT i_0_333( + .A1(n_0_544), .A2(n_0_469), .ZN(n_0_315) + ); + INV_X1_LVT i_0_332( + .A(n_0_315), .ZN(n_0_314) + ); + OAI21_X1_LVT i_0_302( + .A(n_0_681), .B1(op2[16]), .B2(n_0_568), .ZN(n_0_285) + ); + AOI21_X1_LVT i_0_300( + .A(n_0_314), .B1(op1[16]), .B2(n_0_285), .ZN(n_0_283) + ); + INV_X1_LVT i_0_772( + .A(op1[16]), .ZN(n_0_739) + ); + OAI221_X1_LVT i_0_303( + .A(op2[16]), .B1(op1[16]), .B2(n_0_564), .C1(n_0_739), .C2(n_0_567), .ZN(n_0_286) + ); + NAND3_X1_LVT i_0_299( + .A1(n_0_284), .A2(n_0_283), .A3(n_0_286), .ZN(n_0_282) + ); + INV_X1_LVT i_0_593( + .A(n_0_562), .ZN(n_0_561) + ); + OAI22_X1_LVT i_0_307( + .A1(op1[16]), .A2(op2[3]), .B1(op1[24]), .B2(n_0_723), .ZN(n_0_290) + ); + NOR2_X1_LVT i_0_306( + .A1(op2[4]), .A2(n_0_290), .ZN(n_0_289) + ); + AOI22_X1_LVT i_0_305( + .A1(n_0_693), .A2(n_0_289), .B1(op2[2]), .B2(n_0_371), .ZN(n_0_288) + ); + OAI22_X1_LVT i_0_304( + .A1(n_0_728), .A2(n_0_330), .B1(op2[1]), .B2(n_0_288), .ZN(n_0_287) + ); + AOI221_X1_LVT i_0_298( + .A(n_0_282), .B1(n_0_547), .B2(n_0_310), .C1(n_0_561), .C2(n_0_287), .ZN(n_0_281) + ); + INV_X1_LVT i_0_762( + .A(op1[1]), .ZN(n_0_729) + ); + OAI22_X1_LVT i_0_313( + .A1(n_0_722), .A2(n_0_615), .B1(n_0_729), .B2(n_0_617), .ZN(n_0_296) + ); + NAND2_X1_LVT i_0_312( + .A1(op2[2]), .A2(n_0_296), .ZN(n_0_295) + ); + OAI21_X1_LVT i_0_311( + .A(n_0_295), .B1(op2[2]), .B2(n_0_362), .ZN(n_0_294) + ); + NAND2_X1_LVT i_0_310( + .A1(op2[1]), .A2(n_0_294), .ZN(n_0_293) + ); + OAI21_X1_LVT i_0_309( + .A(n_0_293), .B1(op2[1]), .B2(n_0_336), .ZN(n_0_292) + ); + OAI22_X1_LVT i_0_308( + .A1(op2[0]), .A2(n_0_298), .B1(n_0_701), .B2(n_0_292), .ZN(n_0_291) + ); + OAI21_X1_LVT i_0_297( + .A(n_0_281), .B1(n_0_621), .B2(n_0_291), .ZN(result[16]) + ); + OAI221_X1_LVT i_0_286( + .A(op2[15]), .B1(n_0_734), .B2(n_0_567), .C1(op1[15]), .C2(n_0_564), .ZN(n_0_270) + ); + AOI21_X1_LVT i_0_288( + .A(n_0_314), .B1(n_15), .B2(n_0_581), .ZN(n_0_272) + ); + INV_X1_LVT i_0_287( + .A(n_0_272), .ZN(n_0_271) + ); + XNOR2_X1_LVT i_10_78( + .A(n_10_61), .B(n_10_62), .ZN(n_47) + ); + OAI21_X1_LVT i_0_285( + .A(n_0_681), .B1(op2[15]), .B2(n_0_568), .ZN(n_0_269) + ); + AOI221_X1_LVT i_0_284( + .A(n_0_271), .B1(n_47), .B2(n_0_580), .C1(op1[15]), .C2(n_0_269), .ZN(n_0_268) + ); + AOI22_X1_LVT i_0_296( + .A1(op1[8]), .A2(n_0_616), .B1(op1[0]), .B2(n_0_618), .ZN(n_0_280) + ); + AOI22_X1_LVT i_0_295( + .A1(op2[2]), .A2(n_0_280), .B1(n_0_693), .B2(n_0_356), .ZN(n_0_279) + ); + NAND2_X1_LVT i_0_294( + .A1(op2[1]), .A2(n_0_279), .ZN(n_0_278) + ); + OAI21_X1_LVT i_0_293( + .A(n_0_278), .B1(op2[1]), .B2(n_0_299), .ZN(n_0_277) + ); + OAI221_X1_LVT i_0_292( + .A(n_0_620), .B1(n_0_701), .B2(n_0_277), .C1(op2[0]), .C2(n_0_292), .ZN(n_0_276) + ); + OAI222_X1_LVT i_0_291( + .A1(n_0_719), .A2(n_0_617), .B1(n_0_691), .B2(n_0_605), .C1(n_0_734), .C2(n_0_615), + .ZN(n_0_275) + ); + OAI22_X1_LVT i_0_290( + .A1(n_0_693), .A2(n_0_349), .B1(op2[2]), .B2(n_0_275), .ZN(n_0_274) + ); + OAI22_X1_LVT i_0_289( + .A1(op2[1]), .A2(n_0_274), .B1(n_0_728), .B2(n_0_311), .ZN(n_0_273) + ); + AOI22_X1_LVT i_0_283( + .A1(n_0_561), .A2(n_0_273), .B1(n_0_547), .B2(n_0_287), .ZN(n_0_267) + ); + NAND4_X1_LVT i_0_282( + .A1(n_0_270), .A2(n_0_268), .A3(n_0_276), .A4(n_0_267), .ZN(result[15]) + ); + NOR2_X1_LVT i_0_278( + .A1(op2[0]), .A2(n_0_277), .ZN(n_0_263) + ); + NAND2_X1_LVT i_0_281( + .A1(n_0_612), .A2(n_0_575), .ZN(n_0_266) + ); + OAI21_X1_LVT i_0_280( + .A(n_0_266), .B1(n_0_713), .B2(n_0_497), .ZN(n_0_265) + ); + AOI22_X1_LVT i_0_279( + .A1(op2[1]), .A2(n_0_265), .B1(n_0_728), .B2(n_0_294), .ZN(n_0_264) + ); + AOI211_X1_LVT i_0_277( + .A(n_0_263), .B(n_0_621), .C1(op2[0]), .C2(n_0_264), .ZN(n_0_262) + ); + INV_X1_LVT i_0_754( + .A(op1[14]), .ZN(n_0_721) + ); + OAI21_X1_LVT i_0_273( + .A(op2[14]), .B1(n_0_721), .B2(n_0_567), .ZN(n_0_258) + ); + AOI21_X1_LVT i_0_272( + .A(n_0_258), .B1(n_0_721), .B2(n_0_565), .ZN(n_0_257) + ); + XNOR2_X1_LVT i_10_74( + .A(n_10_58), .B(n_10_59), .ZN(n_46) + ); + OAI21_X1_LVT i_0_276( + .A(n_0_681), .B1(op2[14]), .B2(n_0_568), .ZN(n_0_261) + ); + AOI222_X1_LVT i_0_275( + .A1(n_14), .A2(n_0_581), .B1(n_46), .B2(n_0_580), .C1(op1[14]), .C2(n_0_261), + .ZN(n_0_260) + ); + INV_X1_LVT i_0_274( + .A(n_0_260), .ZN(n_0_259) + ); + OAI222_X1_LVT i_0_271( + .A1(n_0_717), .A2(n_0_605), .B1(n_0_687), .B2(n_0_617), .C1(n_0_721), .C2(n_0_615), + .ZN(n_0_256) + ); + OAI22_X1_LVT i_0_270( + .A1(n_0_693), .A2(n_0_331), .B1(op2[2]), .B2(n_0_256), .ZN(n_0_255) + ); + AND2_X1_LVT i_0_269( + .A1(n_0_728), .A2(n_0_255), .ZN(n_0_254) + ); + NOR3_X1_LVT i_0_265( + .A1(op2[3]), .A2(op2[2]), .A3(op2[0]), .ZN(n_0_250) + ); + AOI21_X1_LVT i_0_268( + .A(n_0_254), .B1(op2[1]), .B2(n_0_288), .ZN(n_0_253) + ); + OAI22_X1_LVT i_0_266( + .A1(op2[0]), .A2(n_0_253), .B1(n_0_701), .B2(n_0_273), .ZN(n_0_251) + ); + AOI221_X1_LVT i_0_259( + .A(n_0_579), .B1(n_0_254), .B2(n_0_250), .C1(n_0_315), .C2(n_0_251), .ZN(n_0_244) + ); + OR4_X1_LVT i_0_258( + .A1(n_0_262), .A2(n_0_257), .A3(n_0_259), .A4(n_0_244), .ZN(result[14]) + ); + OAI221_X1_LVT i_0_245( + .A(op2[13]), .B1(op1[13]), .B2(n_0_564), .C1(n_0_714), .C2(n_0_567), .ZN(n_0_231) + ); + NAND2_X1_LVT i_0_244( + .A1(n_13), .A2(n_0_581), .ZN(n_0_230) + ); + OAI211_X1_LVT i_0_243( + .A(n_0_231), .B(n_0_230), .C1(n_0_714), .C2(n_0_681), .ZN(n_0_229) + ); + XNOR2_X1_LVT i_10_70( + .A(n_10_55), .B(n_10_56), .ZN(n_45) + ); + NOR2_X1_LVT i_0_695( + .A1(op2[13]), .A2(n_0_714), .ZN(n_0_662) + ); + AOI221_X1_LVT i_0_242( + .A(n_0_229), .B1(n_45), .B2(n_0_580), .C1(n_0_662), .C2(n_0_569), .ZN(n_0_228) + ); + INV_X1_LVT i_0_267( + .A(n_0_253), .ZN(n_0_252) + ); + OAI222_X1_LVT i_0_257( + .A1(n_0_714), .A2(n_0_615), .B1(n_0_726), .B2(n_0_617), .C1(n_0_710), .C2(n_0_605), + .ZN(n_0_243) + ); + OAI22_X1_LVT i_0_256( + .A1(n_0_693), .A2(n_0_312), .B1(op2[2]), .B2(n_0_243), .ZN(n_0_242) + ); + NAND2_X1_LVT i_0_255( + .A1(n_0_728), .A2(n_0_242), .ZN(n_0_241) + ); + NAND2_X1_LVT i_0_254( + .A1(op2[1]), .A2(n_0_274), .ZN(n_0_240) + ); + NAND2_X1_LVT i_0_241( + .A1(n_0_241), .A2(n_0_240), .ZN(n_0_227) + ); + OAI221_X1_LVT i_0_240( + .A(n_0_228), .B1(n_0_548), .B2(n_0_252), .C1(n_0_562), .C2(n_0_227), .ZN(n_0_226) + ); + NAND2_X1_LVT i_0_249( + .A1(n_0_728), .A2(n_0_279), .ZN(n_0_235) + ); + AOI22_X1_LVT i_0_250( + .A1(n_0_597), .A2(n_0_575), .B1(op1[6]), .B2(n_0_496), .ZN(n_0_236) + ); + OAI21_X1_LVT i_0_248( + .A(n_0_235), .B1(n_0_728), .B2(n_0_236), .ZN(n_0_234) + ); + INV_X1_LVT i_0_247( + .A(n_0_234), .ZN(n_0_233) + ); + AOI221_X1_LVT i_0_246( + .A(n_0_621), .B1(op2[0]), .B2(n_0_233), .C1(n_0_701), .C2(n_0_264), .ZN(n_0_232) + ); + NAND2_X1_LVT i_0_264( + .A1(op2[3]), .A2(n_0_469), .ZN(n_0_249) + ); + AOI21_X1_LVT i_0_262( + .A(n_0_468), .B1(n_0_693), .B2(n_0_249), .ZN(n_0_247) + ); + INV_X1_LVT i_0_261( + .A(n_0_247), .ZN(n_0_246) + ); + OAI211_X1_LVT i_0_260( + .A(n_0_252), .B(n_0_246), .C1(n_0_468), .C2(n_0_254), .ZN(n_0_245) + ); + OAI221_X1_LVT i_0_253( + .A(n_0_544), .B1(n_0_247), .B2(n_0_241), .C1(n_0_469), .C2(n_0_240), .ZN(n_0_239) + ); + INV_X1_LVT i_0_252( + .A(n_0_239), .ZN(n_0_238) + ); + AOI211_X1_LVT i_0_239( + .A(n_0_226), .B(n_0_232), .C1(n_0_245), .C2(n_0_238), .ZN(n_0_225) + ); + INV_X1_LVT i_0_238( + .A(n_0_225), .ZN(result[13]) + ); + OAI221_X1_LVT i_0_232( + .A(op2[12]), .B1(n_0_696), .B2(n_0_567), .C1(op1[12]), .C2(n_0_564), .ZN(n_0_219) + ); + OAI21_X1_LVT i_0_231( + .A(n_0_681), .B1(op2[12]), .B2(n_0_568), .ZN(n_0_218) + ); + XNOR2_X1_LVT i_10_66( + .A(n_10_52), .B(n_10_53), .ZN(n_44) + ); + AOI222_X1_LVT i_0_230( + .A1(n_12), .A2(n_0_581), .B1(op1[12]), .B2(n_0_218), .C1(n_44), .C2(n_0_580), + .ZN(n_0_217) + ); + OAI21_X1_LVT i_0_234( + .A(n_0_620), .B1(op2[1]), .B2(n_0_265), .ZN(n_0_221) + ); + INV_X1_LVT i_0_763( + .A(op1[5]), .ZN(n_0_730) + ); + OAI21_X1_LVT i_0_236( + .A(op2[2]), .B1(n_0_730), .B2(n_0_615), .ZN(n_0_223) + ); + OAI21_X1_LVT i_0_235( + .A(n_0_223), .B1(op2[2]), .B2(n_0_296), .ZN(n_0_222) + ); + AOI21_X1_LVT i_0_233( + .A(n_0_221), .B1(op2[1]), .B2(n_0_222), .ZN(n_0_220) + ); + NOR2_X1_LVT i_0_237( + .A1(n_0_577), .A2(n_0_227), .ZN(n_0_224) + ); + NOR4_X1_LVT i_0_223( + .A1(n_0_701), .A2(n_0_220), .A3(n_0_224), .A4(n_0_238), .ZN(n_0_210) + ); + NAND2_X1_LVT i_0_224( + .A1(n_0_544), .A2(n_0_247), .ZN(n_0_211) + ); + NAND2_X1_LVT i_0_222( + .A1(n_0_701), .A2(n_0_211), .ZN(n_0_209) + ); + OAI22_X1_LVT i_0_229( + .A1(op2[4]), .A2(n_0_696), .B1(n_0_738), .B2(n_0_698), .ZN(n_0_216) + ); + INV_X1_LVT i_0_228( + .A(n_0_216), .ZN(n_0_215) + ); + OAI22_X1_LVT i_0_227( + .A1(n_0_727), .A2(n_0_617), .B1(op2[3]), .B2(n_0_215), .ZN(n_0_214) + ); + OAI22_X1_LVT i_0_226( + .A1(n_0_693), .A2(n_0_289), .B1(op2[2]), .B2(n_0_214), .ZN(n_0_213) + ); + OAI22_X1_LVT i_0_225( + .A1(op2[1]), .A2(n_0_213), .B1(n_0_728), .B2(n_0_255), .ZN(n_0_212) + ); + AOI221_X1_LVT i_0_221( + .A(n_0_209), .B1(n_0_578), .B2(n_0_212), .C1(n_0_620), .C2(n_0_234), .ZN(n_0_208) + ); + OAI211_X1_LVT i_0_220( + .A(n_0_219), .B(n_0_217), .C1(n_0_210), .C2(n_0_208), .ZN(result[12]) + ); + OAI21_X1_LVT i_0_209( + .A(n_0_681), .B1(op2[11]), .B2(n_0_568), .ZN(n_0_197) + ); + AOI22_X1_LVT i_0_208( + .A1(n_11), .A2(n_0_581), .B1(op1[11]), .B2(n_0_197), .ZN(n_0_196) + ); + NAND2_X1_LVT i_0_207( + .A1(n_0_211), .A2(n_0_196), .ZN(n_0_195) + ); + AOI22_X1_LVT i_0_210( + .A1(op1[11]), .A2(n_0_566), .B1(n_0_706), .B2(n_0_565), .ZN(n_0_198) + ); + XNOR2_X1_LVT i_10_62( + .A(n_10_49), .B(n_10_50), .ZN(n_43) + ); + AOI221_X1_LVT i_0_206( + .A(n_0_195), .B1(op2[11]), .B2(n_0_198), .C1(n_43), .C2(n_0_580), .ZN(n_0_194) + ); + AOI221_X1_LVT i_0_215( + .A(op2[3]), .B1(n_0_738), .B2(n_0_706), .C1(op2[4]), .C2(n_0_688), .ZN(n_0_203) + ); + AOI21_X1_LVT i_0_214( + .A(n_0_203), .B1(op1[19]), .B2(n_0_618), .ZN(n_0_202) + ); + NAND2_X1_LVT i_0_213( + .A1(n_0_693), .A2(n_0_202), .ZN(n_0_201) + ); + OAI21_X1_LVT i_0_212( + .A(n_0_201), .B1(n_0_693), .B2(n_0_275), .ZN(n_0_200) + ); + OAI22_X1_LVT i_0_211( + .A1(n_0_728), .A2(n_0_242), .B1(op2[1]), .B2(n_0_200), .ZN(n_0_199) + ); + AOI22_X1_LVT i_0_205( + .A1(n_0_561), .A2(n_0_199), .B1(n_0_701), .B2(n_0_220), .ZN(n_0_193) + ); + NOR2_X1_LVT i_0_219( + .A1(op2[2]), .A2(n_0_280), .ZN(n_0_207) + ); + AOI21_X1_LVT i_0_218( + .A(n_0_207), .B1(op1[4]), .B2(n_0_496), .ZN(n_0_206) + ); + AOI22_X1_LVT i_0_217( + .A1(n_0_728), .A2(n_0_236), .B1(op2[1]), .B2(n_0_206), .ZN(n_0_205) + ); + AOI22_X1_LVT i_0_216( + .A1(n_0_578), .A2(n_0_212), .B1(n_0_620), .B2(n_0_205), .ZN(n_0_204) + ); + OAI211_X1_LVT i_0_204( + .A(n_0_194), .B(n_0_193), .C1(n_0_701), .C2(n_0_204), .ZN(result[11]) + ); + AOI22_X1_LVT i_0_194( + .A1(n_0_654), .A2(n_0_498), .B1(op1[7]), .B2(n_0_573), .ZN(n_0_183) + ); + OAI22_X1_LVT i_0_193( + .A1(n_0_728), .A2(n_0_183), .B1(op2[1]), .B2(n_0_222), .ZN(n_0_182) + ); + AOI22_X1_LVT i_0_192( + .A1(op2[0]), .A2(n_0_182), .B1(n_0_701), .B2(n_0_205), .ZN(n_0_181) + ); + NOR2_X1_LVT i_0_191( + .A1(n_0_621), .A2(n_0_181), .ZN(n_0_180) + ); + AOI22_X1_LVT i_0_190( + .A1(op1[10]), .A2(n_0_566), .B1(n_0_733), .B2(n_0_565), .ZN(n_0_179) + ); + XNOR2_X1_LVT i_10_58( + .A(n_10_46), .B(n_10_47), .ZN(n_42) + ); + AOI22_X1_LVT i_0_188( + .A1(op2[10]), .A2(n_0_179), .B1(n_42), .B2(n_0_580), .ZN(n_0_177) + ); + OAI21_X1_LVT i_0_189( + .A(n_0_681), .B1(op2[10]), .B2(n_0_568), .ZN(n_0_178) + ); + AOI22_X1_LVT i_0_187( + .A1(n_10), .A2(n_0_581), .B1(op1[10]), .B2(n_0_178), .ZN(n_0_176) + ); + NAND2_X1_LVT i_0_186( + .A1(n_0_177), .A2(n_0_176), .ZN(n_0_175) + ); + NOR2_X1_LVT i_0_203( + .A1(n_0_701), .A2(n_0_199), .ZN(n_0_192) + ); + NOR2_X1_LVT i_0_200( + .A1(n_0_693), .A2(n_0_256), .ZN(n_0_189) + ); + AOI221_X1_LVT i_0_202( + .A(n_0_596), .B1(op1[10]), .B2(n_0_616), .C1(op1[26]), .C2(n_0_606), .ZN(n_0_191) + ); + AOI21_X1_LVT i_0_199( + .A(n_0_189), .B1(n_0_693), .B2(n_0_191), .ZN(n_0_188) + ); + OR2_X1_LVT i_0_198( + .A1(op2[1]), .A2(n_0_188), .ZN(n_0_187) + ); + NAND2_X1_LVT i_0_197( + .A1(op2[1]), .A2(n_0_213), .ZN(n_0_186) + ); + NAND2_X1_LVT i_0_185( + .A1(n_0_187), .A2(n_0_186), .ZN(n_0_174) + ); + AOI211_X1_LVT i_0_184( + .A(n_0_577), .B(n_0_192), .C1(n_0_701), .C2(n_0_174), .ZN(n_0_173) + ); + INV_X1_LVT i_0_263( + .A(n_0_249), .ZN(n_0_248) + ); + OAI22_X1_LVT i_0_196( + .A1(n_0_248), .A2(n_0_187), .B1(n_0_247), .B2(n_0_186), .ZN(n_0_185) + ); + AOI221_X1_LVT i_0_195( + .A(n_0_545), .B1(n_0_246), .B2(n_0_192), .C1(n_0_701), .C2(n_0_185), .ZN(n_0_184) + ); + OR4_X1_LVT i_0_183( + .A1(n_0_180), .A2(n_0_175), .A3(n_0_173), .A4(n_0_184), .ZN(result[10]) + ); + INV_X1_LVT i_0_753( + .A(op2[9]), .ZN(n_0_720) + ); + AOI221_X1_LVT i_0_171( + .A(n_0_720), .B1(op1[9]), .B2(n_0_566), .C1(n_0_722), .C2(n_0_565), .ZN(n_0_161) + ); + XNOR2_X1_LVT i_10_54( + .A(n_10_43), .B(n_10_44), .ZN(n_41) + ); + AOI22_X1_LVT i_0_172( + .A1(n_9), .A2(n_0_581), .B1(n_41), .B2(n_0_580), .ZN(n_0_162) + ); + AOI21_X1_LVT i_0_170( + .A(aluBypass), .B1(n_0_720), .B2(n_0_569), .ZN(n_0_160) + ); + OAI21_X1_LVT i_0_169( + .A(n_0_162), .B1(n_0_722), .B2(n_0_160), .ZN(n_0_159) + ); + OAI222_X1_LVT i_0_182( + .A1(n_0_722), .A2(n_0_615), .B1(n_0_699), .B2(n_0_605), .C1(n_0_732), .C2(n_0_617), + .ZN(n_0_172) + ); + AOI22_X1_LVT i_0_181( + .A1(n_0_693), .A2(n_0_172), .B1(op2[2]), .B2(n_0_243), .ZN(n_0_171) + ); + NAND2_X1_LVT i_0_180( + .A1(n_0_728), .A2(n_0_171), .ZN(n_0_170) + ); + NAND2_X1_LVT i_0_179( + .A1(op2[1]), .A2(n_0_200), .ZN(n_0_169) + ); + OAI22_X1_LVT i_0_178( + .A1(n_0_248), .A2(n_0_170), .B1(n_0_247), .B2(n_0_169), .ZN(n_0_168) + ); + NOR3_X1_LVT i_0_177( + .A1(n_0_545), .A2(n_0_168), .A3(n_0_185), .ZN(n_0_167) + ); + NOR2_X1_LVT i_0_251( + .A1(n_0_704), .A2(n_0_615), .ZN(n_0_237) + ); + OAI22_X1_LVT i_0_176( + .A1(op1[2]), .A2(n_0_693), .B1(n_0_496), .B2(n_0_237), .ZN(n_0_166) + ); + OAI22_X1_LVT i_0_175( + .A1(op2[1]), .A2(n_0_206), .B1(n_0_728), .B2(n_0_166), .ZN(n_0_165) + ); + OAI221_X1_LVT i_0_174( + .A(n_0_620), .B1(op2[0]), .B2(n_0_182), .C1(n_0_701), .C2(n_0_165), .ZN(n_0_164) + ); + NAND2_X1_LVT i_0_173( + .A1(n_0_170), .A2(n_0_169), .ZN(n_0_163) + ); + OAI221_X1_LVT i_0_168( + .A(n_0_164), .B1(n_0_562), .B2(n_0_163), .C1(n_0_548), .C2(n_0_174), .ZN(n_0_158) + ); + OR4_X1_LVT i_0_167( + .A1(n_0_161), .A2(n_0_159), .A3(n_0_167), .A4(n_0_158), .ZN(result[9]) + ); + OAI21_X1_LVT i_0_160( + .A(n_0_693), .B1(n_0_730), .B2(n_0_615), .ZN(n_0_151) + ); + OAI21_X1_LVT i_0_159( + .A(op2[2]), .B1(n_0_729), .B2(n_0_615), .ZN(n_0_150) + ); + AND2_X1_LVT i_0_158( + .A1(n_0_151), .A2(n_0_150), .ZN(n_0_149) + ); + NAND2_X1_LVT i_0_157( + .A1(op2[1]), .A2(n_0_149), .ZN(n_0_148) + ); + OAI21_X1_LVT i_0_156( + .A(n_0_148), .B1(op2[1]), .B2(n_0_183), .ZN(n_0_147) + ); + OAI22_X1_LVT i_0_155( + .A1(op2[0]), .A2(n_0_165), .B1(n_0_701), .B2(n_0_147), .ZN(n_0_146) + ); + NOR2_X1_LVT i_0_154( + .A1(n_0_621), .A2(n_0_146), .ZN(n_0_145) + ); + INV_X1_LVT i_0_773( + .A(op1[8]), .ZN(n_0_740) + ); + NOR2_X1_LVT i_0_688( + .A1(n_0_740), .A2(op2[8]), .ZN(n_0_655) + ); + AOI22_X1_LVT i_0_153( + .A1(op1[8]), .A2(aluBypass), .B1(n_0_655), .B2(n_0_569), .ZN(n_0_144) + ); + OAI221_X1_LVT i_0_152( + .A(op2[8]), .B1(op1[8]), .B2(n_0_564), .C1(n_0_740), .C2(n_0_567), .ZN(n_0_143) + ); + XNOR2_X1_LVT i_10_51( + .A(n_10_39), .B(n_10_42), .ZN(n_40) + ); + AOI22_X1_LVT i_0_151( + .A1(n_40), .A2(n_0_580), .B1(n_8), .B2(n_0_581), .ZN(n_0_142) + ); + NAND3_X1_LVT i_0_150( + .A1(n_0_144), .A2(n_0_143), .A3(n_0_142), .ZN(n_0_141) + ); + OAI222_X1_LVT i_0_166( + .A1(n_0_740), .A2(n_0_615), .B1(n_0_739), .B2(n_0_617), .C1(n_0_736), .C2(n_0_605), + .ZN(n_0_157) + ); + OAI22_X1_LVT i_0_165( + .A1(op2[2]), .A2(n_0_157), .B1(n_0_693), .B2(n_0_214), .ZN(n_0_156) + ); + NOR2_X1_LVT i_0_164( + .A1(op2[1]), .A2(n_0_156), .ZN(n_0_155) + ); + AOI21_X1_LVT i_0_163( + .A(n_0_155), .B1(op2[1]), .B2(n_0_188), .ZN(n_0_154) + ); + AND2_X1_LVT i_0_162( + .A1(n_0_701), .A2(n_0_154), .ZN(n_0_153) + ); + AOI211_X1_LVT i_0_149( + .A(n_0_577), .B(n_0_153), .C1(op2[0]), .C2(n_0_163), .ZN(n_0_140) + ); + AOI221_X1_LVT i_0_161( + .A(n_0_545), .B1(op2[0]), .B2(n_0_168), .C1(n_0_249), .C2(n_0_153), .ZN(n_0_152) + ); + OR4_X1_LVT i_0_148( + .A1(n_0_145), .A2(n_0_141), .A3(n_0_140), .A4(n_0_152), .ZN(result[8]) + ); + AOI22_X1_LVT i_0_138( + .A1(op1[4]), .A2(n_0_573), .B1(op1[0]), .B2(n_0_496), .ZN(n_0_130) + ); + AOI22_X1_LVT i_0_137( + .A1(op2[1]), .A2(n_0_130), .B1(n_0_728), .B2(n_0_166), .ZN(n_0_129) + ); + OAI22_X1_LVT i_0_136( + .A1(n_0_701), .A2(n_0_129), .B1(op2[0]), .B2(n_0_147), .ZN(n_0_128) + ); + NOR2_X1_LVT i_0_135( + .A1(n_0_621), .A2(n_0_128), .ZN(n_0_127) + ); + OAI221_X1_LVT i_0_139( + .A(op2[7]), .B1(n_0_713), .B2(n_0_567), .C1(op1[7]), .C2(n_0_564), .ZN(n_0_131) + ); + INV_X1_LVT i_10_44( + .A(n_10_36), .ZN(n_10_37) + ); + NOR2_X1_LVT i_10_45( + .A1(n_10_35), .A2(n_10_37), .ZN(n_10_38) + ); + XNOR2_X1_LVT i_10_46( + .A(n_10_33), .B(n_10_38), .ZN(n_39) + ); + AOI22_X1_LVT i_0_141( + .A1(n_7), .A2(n_0_581), .B1(n_39), .B2(n_0_580), .ZN(n_0_133) + ); + INV_X1_LVT i_0_745( + .A(op2[7]), .ZN(n_0_712) + ); + AOI21_X1_LVT i_0_140( + .A(aluBypass), .B1(n_0_712), .B2(n_0_569), .ZN(n_0_132) + ); + OAI211_X1_LVT i_0_133( + .A(n_0_131), .B(n_0_133), .C1(n_0_713), .C2(n_0_132), .ZN(n_0_125) + ); + OAI22_X1_LVT i_0_147( + .A1(n_0_734), .A2(n_0_617), .B1(n_0_713), .B2(n_0_615), .ZN(n_0_139) + ); + AOI211_X1_LVT i_0_146( + .A(n_0_139), .B(n_0_248), .C1(op1[23]), .C2(n_0_606), .ZN(n_0_138) + ); + OAI22_X1_LVT i_0_145( + .A1(n_0_693), .A2(n_0_202), .B1(op2[2]), .B2(n_0_138), .ZN(n_0_137) + ); + NOR2_X1_LVT i_0_144( + .A1(op2[1]), .A2(n_0_137), .ZN(n_0_136) + ); + AOI21_X1_LVT i_0_143( + .A(n_0_136), .B1(op2[1]), .B2(n_0_171), .ZN(n_0_135) + ); + NAND2_X1_LVT i_0_142( + .A1(n_0_561), .A2(n_0_135), .ZN(n_0_134) + ); + OAI221_X1_LVT i_0_134( + .A(n_0_134), .B1(n_0_548), .B2(n_0_154), .C1(n_0_545), .C2(n_0_249), .ZN(n_0_126) + ); + OR3_X1_LVT i_0_132( + .A1(n_0_127), .A2(n_0_125), .A3(n_0_126), .ZN(result[7]) + ); + NAND2_X1_LVT i_0_124( + .A1(n_0_728), .A2(n_0_149), .ZN(n_0_117) + ); + OAI21_X1_LVT i_0_123( + .A(n_0_117), .B1(n_0_724), .B2(n_0_531), .ZN(n_0_116) + ); + OAI22_X1_LVT i_0_122( + .A1(n_0_701), .A2(n_0_116), .B1(op2[0]), .B2(n_0_129), .ZN(n_0_115) + ); + NOR2_X1_LVT i_0_121( + .A1(n_0_621), .A2(n_0_115), .ZN(n_0_114) + ); + XNOR2_X1_LVT i_10_38( + .A(n_10_30), .B(n_10_31), .ZN(n_38) + ); + AOI22_X1_LVT i_0_119( + .A1(n_6), .A2(n_0_581), .B1(n_38), .B2(n_0_580), .ZN(n_0_112) + ); + INV_X1_LVT i_0_735( + .A(op2[6]), .ZN(n_0_702) + ); + AOI21_X1_LVT i_0_120( + .A(aluBypass), .B1(n_0_702), .B2(n_0_569), .ZN(n_0_113) + ); + OAI21_X1_LVT i_0_118( + .A(n_0_112), .B1(n_0_704), .B2(n_0_113), .ZN(n_0_111) + ); + AOI221_X1_LVT i_0_117( + .A(n_0_702), .B1(n_0_704), .B2(n_0_565), .C1(op1[6]), .C2(n_0_566), .ZN(n_0_110) + ); + NOR3_X1_LVT i_0_116( + .A1(n_0_114), .A2(n_0_111), .A3(n_0_110), .ZN(n_0_109) + ); + AOI221_X1_LVT i_0_131( + .A(n_0_237), .B1(op1[14]), .B2(n_0_618), .C1(op2[4]), .C2(n_0_406), .ZN(n_0_124) + ); + NAND2_X1_LVT i_0_130( + .A1(n_0_693), .A2(n_0_124), .ZN(n_0_123) + ); + INV_X1_LVT i_0_201( + .A(n_0_191), .ZN(n_0_190) + ); + OAI21_X1_LVT i_0_129( + .A(n_0_123), .B1(n_0_693), .B2(n_0_190), .ZN(n_0_122) + ); + AOI22_X1_LVT i_0_128( + .A1(n_0_728), .A2(n_0_122), .B1(op2[1]), .B2(n_0_156), .ZN(n_0_121) + ); + INV_X1_LVT i_0_127( + .A(n_0_121), .ZN(n_0_120) + ); + OAI21_X1_LVT i_0_126( + .A(n_0_248), .B1(op2[1]), .B2(n_0_123), .ZN(n_0_119) + ); + AND2_X1_LVT i_0_125( + .A1(n_0_120), .A2(n_0_119), .ZN(n_0_118) + ); + NOR2_X1_LVT i_0_115( + .A1(n_0_545), .A2(n_0_118), .ZN(n_0_108) + ); + AOI21_X1_LVT i_0_114( + .A(n_0_108), .B1(n_0_576), .B2(n_0_121), .ZN(n_0_107) + ); + AOI22_X1_LVT i_0_113( + .A1(n_0_544), .A2(n_0_248), .B1(n_0_578), .B2(n_0_135), .ZN(n_0_106) + ); + OAI221_X1_LVT i_0_112( + .A(n_0_109), .B1(op2[0]), .B2(n_0_107), .C1(n_0_701), .C2(n_0_106), .ZN(result[6]) + ); + OAI221_X1_LVT i_0_100( + .A(op2[5]), .B1(op1[5]), .B2(n_0_564), .C1(n_0_730), .C2(n_0_567), .ZN(n_0_94) + ); + INV_X1_LVT i_0_764( + .A(op2[5]), .ZN(n_0_731) + ); + AOI21_X1_LVT i_0_99( + .A(aluBypass), .B1(n_0_731), .B2(n_0_569), .ZN(n_0_93) + ); + NOR2_X1_LVT i_0_98( + .A1(n_0_730), .A2(n_0_93), .ZN(n_0_92) + ); + XNOR2_X1_LVT i_10_35( + .A(n_10_26), .B(n_10_29), .ZN(n_37) + ); + AOI221_X1_LVT i_0_97( + .A(n_0_92), .B1(n_37), .B2(n_0_580), .C1(n_5), .C2(n_0_581), .ZN(n_0_91) + ); + OAI22_X1_LVT i_0_102( + .A1(n_0_694), .A2(n_0_531), .B1(op2[1]), .B2(n_0_130), .ZN(n_0_96) + ); + OAI221_X1_LVT i_0_101( + .A(n_0_620), .B1(n_0_701), .B2(n_0_96), .C1(op2[0]), .C2(n_0_116), .ZN(n_0_95) + ); + NAND3_X1_LVT i_0_111( + .A1(n_0_544), .A2(n_0_248), .A3(op2[2]), .ZN(n_0_105) + ); + NAND2_X1_LVT i_0_110( + .A1(op2[4]), .A2(n_0_386), .ZN(n_0_104) + ); + OAI21_X1_LVT i_0_109( + .A(n_0_104), .B1(n_0_714), .B2(n_0_617), .ZN(n_0_103) + ); + OAI22_X1_LVT i_0_108( + .A1(n_0_151), .A2(n_0_103), .B1(n_0_693), .B2(n_0_172), .ZN(n_0_102) + ); + NOR2_X1_LVT i_0_107( + .A1(op2[1]), .A2(n_0_102), .ZN(n_0_101) + ); + AOI21_X1_LVT i_0_106( + .A(n_0_101), .B1(op2[1]), .B2(n_0_137), .ZN(n_0_100) + ); + OAI21_X1_LVT i_0_105( + .A(n_0_105), .B1(n_0_579), .B2(n_0_100), .ZN(n_0_99) + ); + AOI21_X1_LVT i_0_104( + .A(n_0_118), .B1(n_0_682), .B2(n_0_120), .ZN(n_0_98) + ); + OAI22_X1_LVT i_0_103( + .A1(n_0_547), .A2(n_0_99), .B1(n_0_701), .B2(n_0_98), .ZN(n_0_97) + ); + NAND4_X1_LVT i_0_96( + .A1(n_0_94), .A2(n_0_91), .A3(n_0_95), .A4(n_0_97), .ZN(result[5]) + ); + INV_X1_LVT i_10_26( + .A(n_10_21), .ZN(n_10_22) + ); + NOR2_X1_LVT i_10_28( + .A1(n_10_22), .A2(n_10_23), .ZN(n_10_24) + ); + XNOR2_X1_LVT i_10_29( + .A(n_10_19), .B(n_10_24), .ZN(n_36) + ); + AOI222_X1_LVT i_0_89( + .A1(n_4), .A2(n_0_581), .B1(n_36), .B2(n_0_580), .C1(n_0_668), .C2(n_0_564), + .ZN(n_0_84) + ); + INV_X1_LVT i_0_770( + .A(op1[4]), .ZN(n_0_737) + ); + AOI221_X1_LVT i_0_90( + .A(aluBypass), .B1(op2[4]), .B2(n_0_567), .C1(n_0_738), .C2(n_0_569), .ZN(n_0_85) + ); + OAI21_X1_LVT i_0_88( + .A(n_0_84), .B1(n_0_737), .B2(n_0_85), .ZN(n_0_83) + ); + NOR2_X1_LVT i_0_689( + .A1(op2[4]), .A2(n_0_737), .ZN(n_0_656) + ); + AOI21_X1_LVT i_0_95( + .A(n_0_616), .B1(n_0_727), .B2(n_0_723), .ZN(n_0_90) + ); + OAI22_X1_LVT i_0_94( + .A1(n_0_723), .A2(n_0_216), .B1(n_0_656), .B2(n_0_90), .ZN(n_0_89) + ); + INV_X1_LVT i_0_93( + .A(n_0_89), .ZN(n_0_88) + ); + OAI22_X1_LVT i_0_92( + .A1(op2[2]), .A2(n_0_88), .B1(n_0_693), .B2(n_0_157), .ZN(n_0_87) + ); + OAI221_X1_LVT i_0_91( + .A(n_0_105), .B1(n_0_728), .B2(n_0_122), .C1(op2[1]), .C2(n_0_87), .ZN(n_0_86) + ); + AOI221_X1_LVT i_0_85( + .A(n_0_83), .B1(n_0_561), .B2(n_0_86), .C1(op2[0]), .C2(n_0_99), .ZN(n_0_80) + ); + AOI221_X1_LVT i_0_87( + .A(n_0_574), .B1(n_0_729), .B2(op2[1]), .C1(n_0_728), .C2(n_0_724), .ZN(n_0_82) + ); + OAI22_X1_LVT i_0_86( + .A1(op2[0]), .A2(n_0_96), .B1(n_0_701), .B2(n_0_82), .ZN(n_0_81) + ); + OAI21_X1_LVT i_0_84( + .A(n_0_80), .B1(n_0_621), .B2(n_0_81), .ZN(result[4]) + ); + AND2_X1_LVT i_0_81( + .A1(op2[1]), .A2(n_0_105), .ZN(n_0_77) + ); + NAND2_X1_LVT i_0_80( + .A1(n_0_102), .A2(n_0_77), .ZN(n_0_76) + ); + OAI221_X1_LVT i_0_83( + .A(n_0_693), .B1(n_0_654), .B2(n_0_484), .C1(n_0_738), .C2(n_0_350), .ZN(n_0_79) + ); + OAI21_X1_LVT i_0_82( + .A(n_0_79), .B1(n_0_693), .B2(n_0_138), .ZN(n_0_78) + ); + OAI21_X1_LVT i_0_79( + .A(n_0_76), .B1(op2[1]), .B2(n_0_78), .ZN(n_0_75) + ); + NOR2_X1_LVT i_0_78( + .A1(n_0_562), .A2(n_0_75), .ZN(n_0_74) + ); + NAND2_X1_LVT i_10_20( + .A1(n_10_15), .A2(n_10_16), .ZN(n_10_17) + ); + XNOR2_X1_LVT i_10_21( + .A(n_10_13), .B(n_10_17), .ZN(n_35) + ); + AOI22_X1_LVT i_0_75( + .A1(n_35), .A2(n_0_580), .B1(n_3), .B2(n_0_581), .ZN(n_0_71) + ); + OAI21_X1_LVT i_0_74( + .A(n_0_681), .B1(n_0_723), .B2(n_0_566), .ZN(n_0_70) + ); + AOI222_X1_LVT i_0_73( + .A1(n_0_654), .A2(n_0_569), .B1(n_0_663), .B2(n_0_564), .C1(op1[3]), .C2(n_0_70), + .ZN(n_0_69) + ); + INV_X1_LVT i_0_736( + .A(op1[0]), .ZN(n_0_703) + ); + OAI22_X1_LVT i_0_77( + .A1(n_0_703), .A2(n_0_531), .B1(n_0_694), .B2(n_0_572), .ZN(n_0_73) + ); + OAI22_X1_LVT i_0_76( + .A1(n_0_701), .A2(n_0_73), .B1(op2[0]), .B2(n_0_82), .ZN(n_0_72) + ); + OAI211_X1_LVT i_0_72( + .A(n_0_71), .B(n_0_69), .C1(n_0_621), .C2(n_0_72), .ZN(n_0_68) + ); + AOI211_X1_LVT i_0_71( + .A(n_0_74), .B(n_0_68), .C1(n_0_547), .C2(n_0_86), .ZN(n_0_67) + ); + INV_X1_LVT i_0_70( + .A(n_0_67), .ZN(result[3]) + ); + NAND2_X1_LVT i_0_65( + .A1(n_2), .A2(n_0_581), .ZN(n_0_62) + ); + OAI221_X1_LVT i_0_66( + .A(op2[2]), .B1(op1[2]), .B2(n_0_564), .C1(n_0_694), .C2(n_0_567), .ZN(n_0_63) + ); + AOI21_X1_LVT i_0_64( + .A(aluBypass), .B1(n_0_693), .B2(n_0_569), .ZN(n_0_61) + ); + OAI21_X1_LVT i_0_63( + .A(n_0_63), .B1(n_0_694), .B2(n_0_61), .ZN(n_0_60) + ); + INV_X1_LVT i_10_13( + .A(n_10_10), .ZN(n_10_11) + ); + NOR2_X1_LVT i_10_14( + .A1(n_10_9), .A2(n_10_11), .ZN(n_10_12) + ); + XNOR2_X1_LVT i_10_15( + .A(n_10_7), .B(n_10_12), .ZN(n_34) + ); + AOI21_X1_LVT i_0_62( + .A(n_0_60), .B1(n_34), .B2(n_0_580), .ZN(n_0_59) + ); + OAI211_X1_LVT i_0_57( + .A(n_0_62), .B(n_0_59), .C1(n_0_548), .C2(n_0_75), .ZN(n_0_54) + ); + NOR2_X1_LVT i_0_698( + .A1(n_0_729), .A2(op2[1]), .ZN(n_0_665) + ); + INV_X1_LVT i_0_697( + .A(n_0_665), .ZN(n_0_664) + ); + OAI21_X1_LVT i_0_69( + .A(op2[0]), .B1(n_0_664), .B2(n_0_574), .ZN(n_0_66) + ); + OAI21_X1_LVT i_0_68( + .A(n_0_620), .B1(op2[0]), .B2(n_0_73), .ZN(n_0_65) + ); + INV_X1_LVT i_0_67( + .A(n_0_65), .ZN(n_0_64) + ); + OAI222_X1_LVT i_0_61( + .A1(op1[10]), .A2(n_0_617), .B1(op1[2]), .B2(n_0_615), .C1(n_0_738), .C2(n_0_332), + .ZN(n_0_58) + ); + OAI22_X1_LVT i_0_60( + .A1(op2[2]), .A2(n_0_58), .B1(n_0_693), .B2(n_0_124), .ZN(n_0_57) + ); + INV_X1_LVT i_0_59( + .A(n_0_57), .ZN(n_0_56) + ); + AOI22_X1_LVT i_0_58( + .A1(n_0_728), .A2(n_0_56), .B1(n_0_87), .B2(n_0_77), .ZN(n_0_55) + ); + AOI221_X1_LVT i_0_56( + .A(n_0_54), .B1(n_0_66), .B2(n_0_64), .C1(n_0_561), .C2(n_0_55), .ZN(n_0_53) + ); + INV_X1_LVT i_0_55( + .A(n_0_53), .ZN(result[2]) + ); + NAND2_X1_LVT i_0_54( + .A1(n_0_547), .A2(n_0_55), .ZN(n_0_52) + ); + AOI221_X1_LVT i_0_47( + .A(n_0_728), .B1(n_0_729), .B2(n_0_565), .C1(op1[1]), .C2(n_0_566), .ZN(n_0_45) + ); + NOR2_X1_LVT i_0_700( + .A1(op1[0]), .A2(n_0_701), .ZN(n_0_667) + ); + AOI211_X1_LVT i_0_48( + .A(n_0_667), .B(n_0_621), .C1(n_0_729), .C2(n_0_701), .ZN(n_0_46) + ); + AOI221_X1_LVT i_0_44( + .A(n_0_45), .B1(op1[1]), .B2(aluBypass), .C1(n_0_571), .C2(n_0_46), .ZN(n_0_42) + ); + NAND2_X1_LVT i_10_6( + .A1(n_10_3), .A2(n_10_4), .ZN(n_10_5) + ); + XNOR2_X1_LVT i_10_7( + .A(n_10_5), .B(n_10_1), .ZN(n_33) + ); + AOI22_X1_LVT i_0_49( + .A1(n_33), .A2(n_0_580), .B1(n_1), .B2(n_0_581), .ZN(n_0_47) + ); + OAI21_X1_LVT i_0_46( + .A(n_0_47), .B1(n_0_664), .B2(n_0_568), .ZN(n_0_44) + ); + NAND2_X1_LVT i_0_51( + .A1(op2[1]), .A2(n_0_78), .ZN(n_0_49) + ); + OAI222_X1_LVT i_0_53( + .A1(n_0_722), .A2(n_0_617), .B1(n_0_729), .B2(n_0_615), .C1(n_0_738), .C2(n_0_313), + .ZN(n_0_51) + ); + OAI22_X1_LVT i_0_52( + .A1(n_0_223), .A2(n_0_103), .B1(op2[2]), .B2(n_0_51), .ZN(n_0_50) + ); + OAI21_X1_LVT i_0_50( + .A(n_0_49), .B1(op2[1]), .B2(n_0_50), .ZN(n_0_48) + ); + AOI21_X1_LVT i_0_45( + .A(n_0_44), .B1(n_0_561), .B2(n_0_48), .ZN(n_0_43) + ); + NAND3_X1_LVT i_0_43( + .A1(n_0_52), .A2(n_0_42), .A3(n_0_43), .ZN(result[1]) + ); + OAI222_X1_LVT i_0_11( + .A1(n_0_740), .A2(n_0_617), .B1(n_0_703), .B2(n_0_615), .C1(n_0_738), .C2(n_0_290), + .ZN(n_0_10) + ); + OAI22_X1_LVT i_0_10( + .A1(op2[2]), .A2(n_0_10), .B1(n_0_693), .B2(n_0_88), .ZN(n_0_9) + ); + OAI221_X1_LVT i_0_9( + .A(n_0_701), .B1(n_0_728), .B2(n_0_56), .C1(op2[1]), .C2(n_0_9), .ZN(n_0_8) + ); + OAI21_X1_LVT i_0_8( + .A(n_0_8), .B1(n_0_701), .B2(n_0_48), .ZN(n_0_7) + ); + NOR2_X1_LVT i_0_7( + .A1(n_0_579), .A2(n_0_7), .ZN(n_0_6) + ); + OAI221_X1_LVT i_0_3( + .A(op2[0]), .B1(op1[0]), .B2(n_0_564), .C1(n_0_703), .C2(n_0_567), .ZN(n_0_2) + ); + OAI21_X1_LVT i_10_2( + .A(n_10_1), .B1(n_10_0), .B2(op2[0]), .ZN(n_32) + ); + AOI22_X1_LVT i_0_2( + .A1(n_32), .A2(n_0_580), .B1(n_0), .B2(n_0_581), .ZN(n_0_1) + ); + NAND3_X1_LVT i_0_6( + .A1(n_0_701), .A2(n_0_571), .A3(n_0_620), .ZN(n_0_5) + ); + OAI211_X1_LVT i_0_5( + .A(n_0_681), .B(n_0_5), .C1(op2[0]), .C2(n_0_568), .ZN(n_0_4) + ); + NAND2_X1_LVT i_0_4( + .A1(op1[0]), .A2(n_0_4), .ZN(n_0_3) + ); + NAND3_X1_LVT i_0_1( + .A1(n_0_2), .A2(n_0_1), .A3(n_0_3), .ZN(n_0_0) + ); + OAI33_X1_LVT i_0_14( + .A1(n_0_692), .A2(op1[31]), .A3(n_0_683), .B1(op2[31]), .B2(n_0_691), .B3(aluOp[0]), + .ZN(n_0_13) + ); + INV_X1_LVT i_0_741( + .A(op2[29]), .ZN(n_0_708) + ); + NAND2_X1_LVT i_0_685( + .A1(op1[29]), .A2(n_0_708), .ZN(n_0_652) + ); + OAI22_X1_LVT i_0_713( + .A1(n_0_700), .A2(op1[28]), .B1(op1[29]), .B2(n_0_708), .ZN(n_0_680) + ); + NAND2_X1_LVT i_0_694( + .A1(n_0_688), .A2(op2[27]), .ZN(n_0_661) + ); + INV_X1_LVT i_0_742( + .A(op2[26]), .ZN(n_0_709) + ); + OAI22_X1_LVT i_0_712( + .A1(n_0_699), .A2(op2[25]), .B1(n_0_736), .B2(op2[24]), .ZN(n_0_679) + ); + NAND2_X1_LVT i_0_690( + .A1(n_0_727), .A2(op2[20]), .ZN(n_0_657) + ); + INV_X1_LVT i_0_740( + .A(op2[18]), .ZN(n_0_707) + ); + OAI22_X1_LVT i_0_711( + .A1(n_0_707), .A2(op1[18]), .B1(n_0_690), .B2(op1[19]), .ZN(n_0_678) + ); + OAI22_X1_LVT i_0_29( + .A1(n_0_739), .A2(op2[16]), .B1(n_0_734), .B2(op2[15]), .ZN(n_0_28) + ); + INV_X1_LVT i_0_728( + .A(op2[12]), .ZN(n_0_695) + ); + INV_X1_LVT i_0_748( + .A(op2[13]), .ZN(n_0_715) + ); + OAI22_X1_LVT i_0_704( + .A1(n_0_706), .A2(op2[11]), .B1(n_0_696), .B2(op2[12]), .ZN(n_0_671) + ); + AOI22_X1_LVT i_0_710( + .A1(n_0_740), .A2(op2[8]), .B1(n_0_713), .B2(op2[7]), .ZN(n_0_677) + ); + OAI22_X1_LVT i_0_707( + .A1(n_0_731), .A2(op1[5]), .B1(op1[6]), .B2(n_0_702), .ZN(n_0_674) + ); + OAI22_X1_LVT i_0_706( + .A1(op1[2]), .A2(n_0_693), .B1(op1[1]), .B2(n_0_728), .ZN(n_0_673) + ); + INV_X1_LVT i_0_705( + .A(n_0_673), .ZN(n_0_672) + ); + INV_X1_LVT i_0_699( + .A(n_0_667), .ZN(n_0_666) + ); + OAI21_X1_LVT i_0_42( + .A(n_0_672), .B1(n_0_666), .B2(n_0_665), .ZN(n_0_41) + ); + AOI21_X1_LVT i_0_41( + .A(n_0_654), .B1(op1[2]), .B2(n_0_693), .ZN(n_0_40) + ); + AOI211_X1_LVT i_0_40( + .A(n_0_668), .B(n_0_663), .C1(n_0_41), .C2(n_0_40), .ZN(n_0_39) + ); + AOI211_X1_LVT i_0_39( + .A(n_0_656), .B(n_0_39), .C1(n_0_731), .C2(op1[5]), .ZN(n_0_38) + ); + OAI222_X1_LVT i_0_38( + .A1(n_0_704), .A2(op2[6]), .B1(n_0_674), .B2(n_0_38), .C1(n_0_713), .C2(op2[7]), + .ZN(n_0_37) + ); + AOI221_X1_LVT i_0_37( + .A(n_0_655), .B1(op1[9]), .B2(n_0_720), .C1(n_0_677), .C2(n_0_37), .ZN(n_0_36) + ); + INV_X1_LVT i_0_768( + .A(op2[10]), .ZN(n_0_735) + ); + OAI22_X1_LVT i_0_36( + .A1(n_0_735), .A2(op1[10]), .B1(op1[9]), .B2(n_0_720), .ZN(n_0_35) + ); + OAI22_X1_LVT i_0_35( + .A1(op2[10]), .A2(n_0_733), .B1(n_0_36), .B2(n_0_35), .ZN(n_0_34) + ); + INV_X1_LVT i_0_34( + .A(n_0_34), .ZN(n_0_33) + ); + AOI21_X1_LVT i_0_33( + .A(n_0_33), .B1(n_0_706), .B2(op2[11]), .ZN(n_0_32) + ); + OAI222_X1_LVT i_0_32( + .A1(op1[12]), .A2(n_0_695), .B1(n_0_715), .B2(op1[13]), .C1(n_0_671), .C2(n_0_32), + .ZN(n_0_31) + ); + OAI221_X1_LVT i_0_31( + .A(n_0_31), .B1(n_0_721), .B2(op2[14]), .C1(op2[13]), .C2(n_0_714), .ZN(n_0_30) + ); + AOI22_X1_LVT i_0_30( + .A1(n_0_734), .A2(op2[15]), .B1(n_0_721), .B2(op2[14]), .ZN(n_0_29) + ); + AOI21_X1_LVT i_0_28( + .A(n_0_28), .B1(n_0_30), .B2(n_0_29), .ZN(n_0_27) + ); + AOI221_X1_LVT i_0_27( + .A(n_0_27), .B1(n_0_732), .B2(op2[17]), .C1(n_0_739), .C2(op2[16]), .ZN(n_0_26) + ); + AOI211_X1_LVT i_0_26( + .A(n_0_660), .B(n_0_26), .C1(n_0_707), .C2(op1[18]), .ZN(n_0_25) + ); + OAI22_X1_LVT i_0_25( + .A1(op2[19]), .A2(n_0_689), .B1(n_0_678), .B2(n_0_25), .ZN(n_0_24) + ); + AOI211_X1_LVT i_0_24( + .A(n_0_658), .B(n_0_659), .C1(n_0_657), .C2(n_0_24), .ZN(n_0_23) + ); + AOI221_X1_LVT i_0_23( + .A(n_0_23), .B1(n_0_726), .B2(op2[21]), .C1(n_0_687), .C2(op2[22]), .ZN(n_0_22) + ); + AOI221_X1_LVT i_0_22( + .A(n_0_22), .B1(op1[22]), .B2(n_0_686), .C1(op1[23]), .C2(n_0_718), .ZN(n_0_21) + ); + AOI221_X1_LVT i_0_21( + .A(n_0_21), .B1(n_0_736), .B2(op2[24]), .C1(n_0_719), .C2(op2[23]), .ZN(n_0_20) + ); + OAI222_X1_LVT i_0_20( + .A1(op1[26]), .A2(n_0_709), .B1(op1[25]), .B2(n_0_697), .C1(n_0_679), .C2(n_0_20), + .ZN(n_0_19) + ); + OAI221_X1_LVT i_0_19( + .A(n_0_19), .B1(n_0_711), .B2(op2[26]), .C1(n_0_688), .C2(op2[27]), .ZN(n_0_18) + ); + AOI22_X1_LVT i_0_18( + .A1(n_0_700), .A2(op1[28]), .B1(n_0_661), .B2(n_0_18), .ZN(n_0_17) + ); + OAI21_X1_LVT i_0_17( + .A(n_0_652), .B1(n_0_680), .B2(n_0_17), .ZN(n_0_16) + ); + INV_X1_LVT i_0_749( + .A(op2[30]), .ZN(n_0_716) + ); + OAI21_X1_LVT i_0_16( + .A(n_0_16), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_15) + ); + OAI22_X1_LVT i_0_708( + .A1(n_0_692), .A2(op1[31]), .B1(op2[31]), .B2(n_0_691), .ZN(n_0_675) + ); + AOI21_X1_LVT i_0_15( + .A(n_0_675), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_14) + ); + AOI21_X1_LVT i_0_13( + .A(n_0_13), .B1(n_0_15), .B2(n_0_14), .ZN(n_0_12) + ); + NOR4_X1_LVT i_0_12( + .A1(n_0_685), .A2(aluOp[2]), .A3(aluBypass), .A4(n_0_12), .ZN(n_0_11) + ); + OR3_X1_LVT i_0_0( + .A1(n_0_6), .A2(n_0_0), .A3(n_0_11), .ZN(result[0]) + ); + OR4_X1_LVT i_0_703( + .A1(n_0_680), .A2(n_0_673), .A3(n_0_675), .A4(n_0_678), .ZN(n_0_670) + ); + INV_X1_LVT i_0_709( + .A(n_0_677), .ZN(n_0_676) + ); + OR4_X1_LVT i_0_702( + .A1(n_0_679), .A2(n_0_674), .A3(n_0_676), .A4(n_0_671), .ZN(n_0_669) + ); + AOI22_X1_LVT i_0_663( + .A1(n_0_688), .A2(op2[27]), .B1(op1[22]), .B2(n_0_686), .ZN(n_0_630) + ); + OAI22_X1_LVT i_0_662( + .A1(n_0_694), .A2(op2[2]), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_629) + ); + AOI221_X1_LVT i_0_661( + .A(n_0_629), .B1(n_0_711), .B2(op2[26]), .C1(n_0_721), .C2(op2[14]), .ZN(n_0_628) + ); + AOI21_X1_LVT i_0_664( + .A(n_0_660), .B1(n_0_690), .B2(op1[19]), .ZN(n_0_631) + ); + OAI222_X1_LVT i_0_660( + .A1(op1[12]), .A2(n_0_695), .B1(n_0_688), .B2(op2[27]), .C1(op1[22]), .C2(n_0_686), + .ZN(n_0_627) + ); + AOI21_X1_LVT i_0_659( + .A(n_0_663), .B1(n_0_734), .B2(op2[15]), .ZN(n_0_626) + ); + OAI211_X1_LVT i_0_658( + .A(n_0_666), .B(n_0_626), .C1(n_0_715), .C2(op1[13]), .ZN(n_0_625) + ); + AOI211_X1_LVT i_0_657( + .A(n_0_627), .B(n_0_625), .C1(op1[23]), .C2(n_0_718), .ZN(n_0_624) + ); + NAND4_X1_LVT i_0_656( + .A1(n_0_630), .A2(n_0_628), .A3(n_0_631), .A4(n_0_624), .ZN(n_0_623) + ); + OAI22_X1_LVT i_0_684( + .A1(n_0_721), .A2(op2[14]), .B1(n_0_722), .B2(op2[9]), .ZN(n_0_651) + ); + AOI211_X1_LVT i_0_668( + .A(n_0_651), .B(n_0_654), .C1(n_0_719), .C2(op2[23]), .ZN(n_0_635) + ); + NAND2_X1_LVT i_0_667( + .A1(n_0_664), .A2(n_0_657), .ZN(n_0_634) + ); + NOR3_X1_LVT i_0_666( + .A1(n_0_659), .A2(n_0_656), .A3(n_0_634), .ZN(n_0_633) + ); + AOI21_X1_LVT i_0_671( + .A(n_0_655), .B1(n_0_739), .B2(op2[16]), .ZN(n_0_638) + ); + AOI21_X1_LVT i_0_670( + .A(n_0_668), .B1(n_0_736), .B2(op2[24]), .ZN(n_0_637) + ); + OAI22_X1_LVT i_0_673( + .A1(n_0_735), .A2(op1[10]), .B1(n_0_734), .B2(op2[15]), .ZN(n_0_640) + ); + AOI221_X1_LVT i_0_672( + .A(n_0_640), .B1(n_0_732), .B2(op2[17]), .C1(n_0_731), .C2(op1[5]), .ZN(n_0_639) + ); + AND3_X1_LVT i_0_669( + .A1(n_0_638), .A2(n_0_637), .A3(n_0_639), .ZN(n_0_636) + ); + OAI22_X1_LVT i_0_682( + .A1(n_0_703), .A2(op2[0]), .B1(n_0_704), .B2(op2[6]), .ZN(n_0_649) + ); + OAI22_X1_LVT i_0_681( + .A1(op2[28]), .A2(n_0_698), .B1(op1[25]), .B2(n_0_697), .ZN(n_0_648) + ); + AOI21_X1_LVT i_0_678( + .A(n_0_658), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_645) + ); + AOI21_X1_LVT i_0_677( + .A(n_0_662), .B1(n_0_735), .B2(op1[10]), .ZN(n_0_644) + ); + INV_X1_LVT i_0_758( + .A(op2[21]), .ZN(n_0_725) + ); + OAI22_X1_LVT i_0_683( + .A1(op1[21]), .A2(n_0_725), .B1(n_0_739), .B2(op2[16]), .ZN(n_0_650) + ); + AOI221_X1_LVT i_0_676( + .A(n_0_650), .B1(n_0_722), .B2(op2[9]), .C1(op1[7]), .C2(n_0_712), .ZN(n_0_643) + ); + OAI21_X1_LVT i_0_680( + .A(n_0_652), .B1(n_0_711), .B2(op2[26]), .ZN(n_0_647) + ); + AOI221_X1_LVT i_0_679( + .A(n_0_647), .B1(n_0_706), .B2(op2[11]), .C1(n_0_707), .C2(op1[18]), .ZN(n_0_646) + ); + NAND4_X1_LVT i_0_675( + .A1(n_0_645), .A2(n_0_644), .A3(n_0_643), .A4(n_0_646), .ZN(n_0_642) + ); + NOR3_X1_LVT i_0_674( + .A1(n_0_649), .A2(n_0_648), .A3(n_0_642), .ZN(n_0_641) + ); + NAND4_X1_LVT i_0_665( + .A1(n_0_635), .A2(n_0_633), .A3(n_0_636), .A4(n_0_641), .ZN(n_0_632) + ); + NOR4_X1_LVT i_0_655( + .A1(n_0_670), .A2(n_0_669), .A3(n_0_623), .A4(n_0_632), .ZN(eqFlag) + ); +endmodule + +module decoder(CurrentPC, JumpOrBranchPC, JumpOrBranch, DAddr, WData, RData, Instruction, + WrMem, DWidth, Rs1, Rs2, Rd, RRs1, RRs2, WRd, WrReg, Illegal); + input [31:0] CurrentPC, RData, Instruction, RRs1, RRs2; + output [31:0] JumpOrBranchPC, DAddr, WData, WRd; + output [4:0] Rs1, Rs2, Rd; + output [1:0] DWidth; + output JumpOrBranch, WrMem, WrReg, Illegal; + + wire [31:0] op1, op2; + wire [2:0] aluOp; + wire eqFlag, n_5_0, n_5_1, n_5_2, n_5_3, n_5_4, n_5_5, n_5_6, n_5_7, n_5_8, + n_5_9, n_5_10, n_5_11, n_5_12, n_5_13, n_5_14, n_5_15, n_5_16, n_5_17, + n_5_18, n_5_19, n_5_20, n_5_21, n_5_22, n_5_23, n_5_24, n_5_25, n_5_26, + n_5_27, n_5_28, n_5_29, n_5_30, n_5_31, n_5_32, n_5_33, n_17_0, n_17_1, + n_17_2, n_17_3, n_17_4, n_17_5, n_17_6, n_17_7, n_17_8, n_17_9, n_17_10, + n_17_11, n_17_12, n_17_13, n_17_14, n_17_15, n_17_16, n_17_17, n_17_18, + n_17_19, n_17_20, n_17_21, n_17_22, n_17_23, n_17_24, n_17_25, n_17_26, + n_17_27, n_17_28, n_17_29, n_17_30, n_17_31, n_17_32, n_18_0, n_18_1, + n_18_2, n_18_3, n_18_4, n_18_5, n_18_6, n_18_7, n_18_8, n_18_9, n_18_10, + n_18_11, n_18_12, n_18_13, n_18_14, n_18_15, n_18_16, n_18_17, n_18_18, + n_18_19, n_18_20, n_18_21, n_18_22, n_18_23, n_18_24, n_18_25, n_18_26, + n_18_27, n_18_28, n_18_29, n_18_30, n_18_31, n_18_32, n_0_15, n_0_2, + n_0_16, n_0_3, n_0_17, n_0_4, n_0_18, n_0_5, n_0_19, n_0_6, n_0_20, + n_0_7, n_0_21, n_0_8, n_0_22, n_0_9, n_0_23, n_0_10, n_0_24, n_0_11, + n_0_25, n_0_12, n_0_26, n_0_13, n_0_27, n_0_14, n_0_28, n_0_29, n_0_30, + n_0_31, n_0_32, n_0_33, n_0_34, n_0_35, n_0_36, n_0_37, n_0_38, n_0_39, + n_0_40, n_0_41, n_0_42, n_0_43, n_0_44, n_0_45, n_0_46, n_0_47, n_0_48, + n_0_49, n_0_50, n_0_51, n_0_52, n_0_53, n_0_54, n_0_55, n_0_56, n_0_57, + n_0_58, n_0_59, n_0_60, n_0_61, n_0_62, n_0_63, n_0_64, n_0_65, n_0_66, + n_0_67, n_0_68, n_0_69, n_0_70, n_0_71, n_0_72, n_0_73, n_0_74, n_0_75, + n_0_76, n_0_77, n_0_78, n_0_79, n_0_80, n_0_81, n_0_82, n_0_83, n_0_84, + n_0_85, n_0_86, n_0_87, n_0_88, n_0_89, n_0_90, n_0_91, n_0_92, n_0_93, + n_0_94, n_0_95, n_0_96, n_0_97, n_0_98, n_0_99, n_0_100, aluNegAr, + n_0_101, n_0_102, n_0_103, n_0_104, n_0_105, aluBypass, n_0_106, + n_0_107, n_0_108, n_0_109, n_0_110, n_0_111, n_0_112, n_0_113, n_0_114, + n_0_115, n_0_116, n_0_117, n_0_118, n_0_119, n_0_120, n_0_121, n_0_122, + n_0_123, n_0_124, n_0_125, n_0_126, n_0_127, n_0_128, n_0_129, n_0_130, + n_0_131, n_0_132, n_0_133, n_0_134, n_0_135, n_0_136, n_0_137, n_0_138, + n_0_139, n_0_140, n_0_141, n_0_142, n_0_143, n_0_144, n_0_145, n_0_146, + n_0_147, n_0_148, n_0_149, n_0_150, n_0_151, n_0_152, n_0_153, n_0_154, + n_0_155, n_0_156, n_0_157, n_0_158, n_0_159, n_0_160, n_0_161, n_0_162, + n_0_163, n_0_164, n_0_165, n_0_166, n_0_167, n_0_168, n_0_169, n_0_170, + n_0_171, n_0_172, n_0_173, n_0_174, n_0_175, n_0_176, n_0_177, n_0_178, + n_0_179, n_0_180, n_0_181, n_0_182, n_0_183, n_0_184, n_0_185, n_0_186, + n_0_187, n_0_188, n_0_189, n_0_190, n_0_191, n_0_192, n_0_193, n_0_194, + n_0_195, n_0_196, n_0_197, n_0_198, n_0_199, n_0_200, n_0_201, n_0_202, + n_0_203, n_0_204, n_0_205, n_0_206, n_0_207, n_0_208, n_0_209, n_0_210, + n_0_211, n_0_212, n_0_213, n_0_214, n_0_215, n_0_216, n_0_217, n_0_218, + n_0_219, n_0_220, n_0_221, n_0_222, n_0_223, n_0_224, n_0_225, n_0_226, + n_0_227, n_0_228, n_0_229, n_0_230, n_0_231, n_0_232, n_0_233, n_0_234, + n_0_235, n_0_236, n_0_237, n_0_238, n_0_239, n_0_240, n_0_241, n_0_242, + n_0_1, n_0_0, n_0_243, n_0_244, n_0_245, n_0_246, n_0_247, n_0_248, + n_0_249, n_63, n_64, n_65, n_66, n_67, n_68, n_69, n_70, n_71, n_72, + n_73, n_74, n_75, n_76, n_77, n_78, n_79, n_80, n_81, n_82, n_83, n_84, + n_85, n_86, n_87, n_88, n_89, n_90, n_91, n_92, n_93, n_32, n_33, n_34, + n_35, n_36, n_37, n_38, n_39, n_40, n_41, n_42, n_43, n_44, n_45, n_46, + n_47, n_48, n_49, n_50, n_51, n_52, n_53, n_54, n_55, n_56, n_57, n_58, + n_59, n_60, n_61, n_62, n_0, n_1, n_2, n_3, n_4, n_5, n_6, n_7, n_8, + n_9, n_10, n_11, n_12, n_13, n_14, n_15, n_16, n_17, n_18, n_19, n_20, + n_21, n_22, n_23, n_24, n_25, n_26, n_27, n_28, n_29, n_30, n_31; + + INV_X1_LVT i_18_1( + .A(CurrentPC[13]), .ZN(n_18_1) + ); + XNOR2_X1_LVT i_18_32( + .A(CurrentPC[31]), .B(n_18_1), .ZN(n_18_32) + ); + INV_X1_LVT i_18_0( + .A(Instruction[31]), .ZN(n_18_0) + ); + HA_X1_LVT i_18_2( + .A(Instruction[8]), .B(CurrentPC[1]), .CO(n_18_2), .S(n_63) + ); + FA_X1_LVT i_18_3( + .A(Instruction[9]), .B(CurrentPC[2]), .CI(n_18_2), .CO(n_18_3), .S(n_64) + ); + FA_X1_LVT i_18_4( + .A(Instruction[10]), .B(CurrentPC[3]), .CI(n_18_3), .CO(n_18_4), .S(n_65) + ); + FA_X1_LVT i_18_5( + .A(Instruction[11]), .B(CurrentPC[4]), .CI(n_18_4), .CO(n_18_5), .S(n_66) + ); + FA_X1_LVT i_18_6( + .A(Instruction[25]), .B(CurrentPC[5]), .CI(n_18_5), .CO(n_18_6), .S(n_67) + ); + FA_X1_LVT i_18_7( + .A(Instruction[26]), .B(CurrentPC[6]), .CI(n_18_6), .CO(n_18_7), .S(n_68) + ); + FA_X1_LVT i_18_8( + .A(Instruction[27]), .B(CurrentPC[7]), .CI(n_18_7), .CO(n_18_8), .S(n_69) + ); + FA_X1_LVT i_18_9( + .A(Instruction[28]), .B(CurrentPC[8]), .CI(n_18_8), .CO(n_18_9), .S(n_70) + ); + FA_X1_LVT i_18_10( + .A(Instruction[29]), .B(CurrentPC[9]), .CI(n_18_9), .CO(n_18_10), .S(n_71) + ); + FA_X1_LVT i_18_11( + .A(Instruction[30]), .B(CurrentPC[10]), .CI(n_18_10), .CO(n_18_11), .S(n_72) + ); + FA_X1_LVT i_18_12( + .A(Instruction[7]), .B(CurrentPC[11]), .CI(n_18_11), .CO(n_18_12), .S(n_73) + ); + FA_X1_LVT i_18_13( + .A(CurrentPC[12]), .B(Instruction[31]), .CI(n_18_12), .CO(n_18_13), .S(n_74) + ); + FA_X1_LVT i_18_14( + .A(n_18_0), .B(n_18_1), .CI(n_18_13), .CO(n_18_14), .S(n_75) + ); + FA_X1_LVT i_18_15( + .A(CurrentPC[14]), .B(n_18_1), .CI(n_18_14), .CO(n_18_15), .S(n_76) + ); + FA_X1_LVT i_18_16( + .A(CurrentPC[15]), .B(n_18_1), .CI(n_18_15), .CO(n_18_16), .S(n_77) + ); + FA_X1_LVT i_18_17( + .A(CurrentPC[16]), .B(n_18_1), .CI(n_18_16), .CO(n_18_17), .S(n_78) + ); + FA_X1_LVT i_18_18( + .A(CurrentPC[17]), .B(n_18_1), .CI(n_18_17), .CO(n_18_18), .S(n_79) + ); + FA_X1_LVT i_18_19( + .A(CurrentPC[18]), .B(n_18_1), .CI(n_18_18), .CO(n_18_19), .S(n_80) + ); + FA_X1_LVT i_18_20( + .A(CurrentPC[19]), .B(n_18_1), .CI(n_18_19), .CO(n_18_20), .S(n_81) + ); + FA_X1_LVT i_18_21( + .A(CurrentPC[20]), .B(n_18_1), .CI(n_18_20), .CO(n_18_21), .S(n_82) + ); + FA_X1_LVT i_18_22( + .A(CurrentPC[21]), .B(n_18_1), .CI(n_18_21), .CO(n_18_22), .S(n_83) + ); + FA_X1_LVT i_18_23( + .A(CurrentPC[22]), .B(n_18_1), .CI(n_18_22), .CO(n_18_23), .S(n_84) + ); + FA_X1_LVT i_18_24( + .A(CurrentPC[23]), .B(n_18_1), .CI(n_18_23), .CO(n_18_24), .S(n_85) + ); + FA_X1_LVT i_18_25( + .A(CurrentPC[24]), .B(n_18_1), .CI(n_18_24), .CO(n_18_25), .S(n_86) + ); + FA_X1_LVT i_18_26( + .A(CurrentPC[25]), .B(n_18_1), .CI(n_18_25), .CO(n_18_26), .S(n_87) + ); + FA_X1_LVT i_18_27( + .A(CurrentPC[26]), .B(n_18_1), .CI(n_18_26), .CO(n_18_27), .S(n_88) + ); + FA_X1_LVT i_18_28( + .A(CurrentPC[27]), .B(n_18_1), .CI(n_18_27), .CO(n_18_28), .S(n_89) + ); + FA_X1_LVT i_18_29( + .A(CurrentPC[28]), .B(n_18_1), .CI(n_18_28), .CO(n_18_29), .S(n_90) + ); + FA_X1_LVT i_18_30( + .A(CurrentPC[29]), .B(n_18_1), .CI(n_18_29), .CO(n_18_30), .S(n_91) + ); + FA_X1_LVT i_18_31( + .A(CurrentPC[30]), .B(n_18_1), .CI(n_18_30), .CO(n_18_31), .S(n_92) + ); + XNOR2_X1_LVT i_18_33( + .A(n_18_32), .B(n_18_31), .ZN(n_93) + ); + INV_X1_LVT i_0_350( + .A(Instruction[3]), .ZN(n_0_243) + ); + NAND3_X1_LVT i_0_343( + .A1(n_0_243), .A2(Instruction[0]), .A3(Instruction[1]), .ZN(n_0_238) + ); + OR2_X1_LVT i_0_332( + .A1(n_0_238), .A2(Instruction[2]), .ZN(n_0_228) + ); + INV_X1_LVT i_0_351( + .A(Instruction[5]), .ZN(n_0_244) + ); + NOR2_X1_LVT i_0_340( + .A1(n_0_244), .A2(Instruction[4]), .ZN(n_0_235) + ); + NAND2_X1_LVT i_0_329( + .A1(Instruction[6]), .A2(n_0_235), .ZN(n_0_225) + ); + INV_X1_LVT i_0_354( + .A(Instruction[13]), .ZN(n_0_247) + ); + NOR2_X1_LVT i_0_345( + .A1(n_0_247), .A2(Instruction[14]), .ZN(n_0_240) + ); + NOR3_X1_LVT i_0_118( + .A1(n_0_228), .A2(n_0_225), .A3(n_0_240), .ZN(n_0_99) + ); + NAND3_X1_LVT i_0_346( + .A1(Instruction[0]), .A2(Instruction[1]), .A3(Instruction[2]), .ZN(n_0_241) + ); + NOR2_X1_LVT i_0_328( + .A1(n_0_241), .A2(n_0_225), .ZN(n_0_224) + ); + INV_X1_LVT i_0_356( + .A(n_0_224), .ZN(n_0_249) + ); + NOR2_X1_LVT i_0_108( + .A1(n_0_243), .A2(n_0_249), .ZN(n_0_91) + ); + INV_X1_LVT i_17_1( + .A(CurrentPC[21]), .ZN(n_17_1) + ); + XNOR2_X1_LVT i_17_32( + .A(CurrentPC[31]), .B(n_17_1), .ZN(n_17_32) + ); + INV_X1_LVT i_17_0( + .A(Instruction[31]), .ZN(n_17_0) + ); + HA_X1_LVT i_17_2( + .A(Instruction[21]), .B(CurrentPC[1]), .CO(n_17_2), .S(n_32) + ); + FA_X1_LVT i_17_3( + .A(Instruction[22]), .B(CurrentPC[2]), .CI(n_17_2), .CO(n_17_3), .S(n_33) + ); + FA_X1_LVT i_17_4( + .A(Instruction[23]), .B(CurrentPC[3]), .CI(n_17_3), .CO(n_17_4), .S(n_34) + ); + FA_X1_LVT i_17_5( + .A(Instruction[24]), .B(CurrentPC[4]), .CI(n_17_4), .CO(n_17_5), .S(n_35) + ); + FA_X1_LVT i_17_6( + .A(Instruction[25]), .B(CurrentPC[5]), .CI(n_17_5), .CO(n_17_6), .S(n_36) + ); + FA_X1_LVT i_17_7( + .A(Instruction[26]), .B(CurrentPC[6]), .CI(n_17_6), .CO(n_17_7), .S(n_37) + ); + FA_X1_LVT i_17_8( + .A(Instruction[27]), .B(CurrentPC[7]), .CI(n_17_7), .CO(n_17_8), .S(n_38) + ); + FA_X1_LVT i_17_9( + .A(Instruction[28]), .B(CurrentPC[8]), .CI(n_17_8), .CO(n_17_9), .S(n_39) + ); + FA_X1_LVT i_17_10( + .A(Instruction[29]), .B(CurrentPC[9]), .CI(n_17_9), .CO(n_17_10), .S(n_40) + ); + FA_X1_LVT i_17_11( + .A(Instruction[30]), .B(CurrentPC[10]), .CI(n_17_10), .CO(n_17_11), .S(n_41) + ); + FA_X1_LVT i_17_12( + .A(Instruction[20]), .B(CurrentPC[11]), .CI(n_17_11), .CO(n_17_12), .S(n_42) + ); + FA_X1_LVT i_17_13( + .A(Instruction[12]), .B(CurrentPC[12]), .CI(n_17_12), .CO(n_17_13), .S(n_43) + ); + FA_X1_LVT i_17_14( + .A(Instruction[13]), .B(CurrentPC[13]), .CI(n_17_13), .CO(n_17_14), .S(n_44) + ); + FA_X1_LVT i_17_15( + .A(Instruction[14]), .B(CurrentPC[14]), .CI(n_17_14), .CO(n_17_15), .S(n_45) + ); + FA_X1_LVT i_17_16( + .A(Instruction[15]), .B(CurrentPC[15]), .CI(n_17_15), .CO(n_17_16), .S(n_46) + ); + FA_X1_LVT i_17_17( + .A(Instruction[16]), .B(CurrentPC[16]), .CI(n_17_16), .CO(n_17_17), .S(n_47) + ); + FA_X1_LVT i_17_18( + .A(Instruction[17]), .B(CurrentPC[17]), .CI(n_17_17), .CO(n_17_18), .S(n_48) + ); + FA_X1_LVT i_17_19( + .A(Instruction[18]), .B(CurrentPC[18]), .CI(n_17_18), .CO(n_17_19), .S(n_49) + ); + FA_X1_LVT i_17_20( + .A(Instruction[19]), .B(CurrentPC[19]), .CI(n_17_19), .CO(n_17_20), .S(n_50) + ); + FA_X1_LVT i_17_21( + .A(CurrentPC[20]), .B(Instruction[31]), .CI(n_17_20), .CO(n_17_21), .S(n_51) + ); + FA_X1_LVT i_17_22( + .A(n_17_0), .B(n_17_1), .CI(n_17_21), .CO(n_17_22), .S(n_52) + ); + FA_X1_LVT i_17_23( + .A(CurrentPC[22]), .B(n_17_1), .CI(n_17_22), .CO(n_17_23), .S(n_53) + ); + FA_X1_LVT i_17_24( + .A(CurrentPC[23]), .B(n_17_1), .CI(n_17_23), .CO(n_17_24), .S(n_54) + ); + FA_X1_LVT i_17_25( + .A(CurrentPC[24]), .B(n_17_1), .CI(n_17_24), .CO(n_17_25), .S(n_55) + ); + FA_X1_LVT i_17_26( + .A(CurrentPC[25]), .B(n_17_1), .CI(n_17_25), .CO(n_17_26), .S(n_56) + ); + FA_X1_LVT i_17_27( + .A(CurrentPC[26]), .B(n_17_1), .CI(n_17_26), .CO(n_17_27), .S(n_57) + ); + FA_X1_LVT i_17_28( + .A(CurrentPC[27]), .B(n_17_1), .CI(n_17_27), .CO(n_17_28), .S(n_58) + ); + FA_X1_LVT i_17_29( + .A(CurrentPC[28]), .B(n_17_1), .CI(n_17_28), .CO(n_17_29), .S(n_59) + ); + FA_X1_LVT i_17_30( + .A(CurrentPC[29]), .B(n_17_1), .CI(n_17_29), .CO(n_17_30), .S(n_60) + ); + FA_X1_LVT i_17_31( + .A(CurrentPC[30]), .B(n_17_1), .CI(n_17_30), .CO(n_17_31), .S(n_61) + ); + XNOR2_X1_LVT i_17_33( + .A(n_17_32), .B(n_17_31), .ZN(n_62) + ); + INV_X1_LVT i_5_1( + .A(RRs1[12]), .ZN(n_5_1) + ); + XNOR2_X1_LVT i_5_33( + .A(RRs1[31]), .B(n_5_1), .ZN(n_5_33) + ); + INV_X1_LVT i_5_0( + .A(Instruction[31]), .ZN(n_5_0) + ); + HA_X1_LVT i_5_2( + .A(Instruction[20]), .B(RRs1[0]), .CO(n_5_2), .S(n_0) + ); + FA_X1_LVT i_5_3( + .A(Instruction[21]), .B(RRs1[1]), .CI(n_5_2), .CO(n_5_3), .S(n_1) + ); + FA_X1_LVT i_5_4( + .A(Instruction[22]), .B(RRs1[2]), .CI(n_5_3), .CO(n_5_4), .S(n_2) + ); + FA_X1_LVT i_5_5( + .A(Instruction[23]), .B(RRs1[3]), .CI(n_5_4), .CO(n_5_5), .S(n_3) + ); + FA_X1_LVT i_5_6( + .A(Instruction[24]), .B(RRs1[4]), .CI(n_5_5), .CO(n_5_6), .S(n_4) + ); + FA_X1_LVT i_5_7( + .A(Instruction[25]), .B(RRs1[5]), .CI(n_5_6), .CO(n_5_7), .S(n_5) + ); + FA_X1_LVT i_5_8( + .A(Instruction[26]), .B(RRs1[6]), .CI(n_5_7), .CO(n_5_8), .S(n_6) + ); + FA_X1_LVT i_5_9( + .A(Instruction[27]), .B(RRs1[7]), .CI(n_5_8), .CO(n_5_9), .S(n_7) + ); + FA_X1_LVT i_5_10( + .A(Instruction[28]), .B(RRs1[8]), .CI(n_5_9), .CO(n_5_10), .S(n_8) + ); + FA_X1_LVT i_5_11( + .A(Instruction[29]), .B(RRs1[9]), .CI(n_5_10), .CO(n_5_11), .S(n_9) + ); + FA_X1_LVT i_5_12( + .A(Instruction[30]), .B(RRs1[10]), .CI(n_5_11), .CO(n_5_12), .S(n_10) + ); + FA_X1_LVT i_5_13( + .A(RRs1[11]), .B(Instruction[31]), .CI(n_5_12), .CO(n_5_13), .S(n_11) + ); + FA_X1_LVT i_5_14( + .A(n_5_0), .B(n_5_1), .CI(n_5_13), .CO(n_5_14), .S(n_12) + ); + FA_X1_LVT i_5_15( + .A(RRs1[13]), .B(n_5_1), .CI(n_5_14), .CO(n_5_15), .S(n_13) + ); + FA_X1_LVT i_5_16( + .A(RRs1[14]), .B(n_5_1), .CI(n_5_15), .CO(n_5_16), .S(n_14) + ); + FA_X1_LVT i_5_17( + .A(RRs1[15]), .B(n_5_1), .CI(n_5_16), .CO(n_5_17), .S(n_15) + ); + FA_X1_LVT i_5_18( + .A(RRs1[16]), .B(n_5_1), .CI(n_5_17), .CO(n_5_18), .S(n_16) + ); + FA_X1_LVT i_5_19( + .A(RRs1[17]), .B(n_5_1), .CI(n_5_18), .CO(n_5_19), .S(n_17) + ); + FA_X1_LVT i_5_20( + .A(RRs1[18]), .B(n_5_1), .CI(n_5_19), .CO(n_5_20), .S(n_18) + ); + FA_X1_LVT i_5_21( + .A(RRs1[19]), .B(n_5_1), .CI(n_5_20), .CO(n_5_21), .S(n_19) + ); + FA_X1_LVT i_5_22( + .A(RRs1[20]), .B(n_5_1), .CI(n_5_21), .CO(n_5_22), .S(n_20) + ); + FA_X1_LVT i_5_23( + .A(RRs1[21]), .B(n_5_1), .CI(n_5_22), .CO(n_5_23), .S(n_21) + ); + FA_X1_LVT i_5_24( + .A(RRs1[22]), .B(n_5_1), .CI(n_5_23), .CO(n_5_24), .S(n_22) + ); + FA_X1_LVT i_5_25( + .A(RRs1[23]), .B(n_5_1), .CI(n_5_24), .CO(n_5_25), .S(n_23) + ); + FA_X1_LVT i_5_26( + .A(RRs1[24]), .B(n_5_1), .CI(n_5_25), .CO(n_5_26), .S(n_24) + ); + FA_X1_LVT i_5_27( + .A(RRs1[25]), .B(n_5_1), .CI(n_5_26), .CO(n_5_27), .S(n_25) + ); + FA_X1_LVT i_5_28( + .A(RRs1[26]), .B(n_5_1), .CI(n_5_27), .CO(n_5_28), .S(n_26) + ); + FA_X1_LVT i_5_29( + .A(RRs1[27]), .B(n_5_1), .CI(n_5_28), .CO(n_5_29), .S(n_27) + ); + FA_X1_LVT i_5_30( + .A(RRs1[28]), .B(n_5_1), .CI(n_5_29), .CO(n_5_30), .S(n_28) + ); + FA_X1_LVT i_5_31( + .A(RRs1[29]), .B(n_5_1), .CI(n_5_30), .CO(n_5_31), .S(n_29) + ); + FA_X1_LVT i_5_32( + .A(RRs1[30]), .B(n_5_1), .CI(n_5_31), .CO(n_5_32), .S(n_30) + ); + XNOR2_X1_LVT i_5_34( + .A(n_5_33), .B(n_5_32), .ZN(n_31) + ); + NOR2_X1_LVT i_0_107( + .A1(n_0_249), .A2(Instruction[3]), .ZN(n_0_90) + ); + AOI222_X1_LVT i_0_106( + .A1(n_93), .A2(n_0_99), .B1(n_0_91), .B2(n_62), .C1(n_31), .C2(n_0_90), .ZN(n_0_89) + ); + INV_X1_LVT i_0_355( + .A(Instruction[6]), .ZN(n_0_248) + ); + NAND2_X1_LVT i_0_339( + .A1(n_0_248), .A2(Instruction[4]), .ZN(n_0_234) + ); + INV_X1_LVT i_0_338( + .A(n_0_234), .ZN(n_0_233) + ); + OAI21_X1_LVT i_0_341( + .A(Instruction[13]), .B1(Instruction[14]), .B2(Instruction[12]), .ZN(n_0_236) + ); + AOI211_X1_LVT i_0_337( + .A(n_0_235), .B(n_0_233), .C1(n_0_248), .C2(n_0_236), .ZN(n_0_232) + ); + INV_X1_LVT i_0_352( + .A(Instruction[4]), .ZN(n_0_245) + ); + NAND2_X1_LVT i_0_344( + .A1(n_0_245), .A2(Instruction[2]), .ZN(n_0_239) + ); + AOI21_X1_LVT i_0_335( + .A(Instruction[6]), .B1(n_0_243), .B2(n_0_239), .ZN(n_0_230) + ); + NOR2_X1_LVT i_0_334( + .A1(n_0_232), .A2(n_0_230), .ZN(n_0_229) + ); + NAND2_X1_LVT i_0_342( + .A1(n_0_241), .A2(n_0_238), .ZN(n_0_237) + ); + NAND2_X1_LVT i_0_336( + .A1(Instruction[6]), .A2(n_0_240), .ZN(n_0_231) + ); + OAI211_X1_LVT i_0_333( + .A(n_0_229), .B(n_0_237), .C1(Instruction[2]), .C2(n_0_231), .ZN(Illegal) + ); + NAND2_X1_LVT i_0_109( + .A1(Illegal), .A2(CurrentPC[31]), .ZN(n_0_92) + ); + NAND2_X1_LVT i_0_105( + .A1(n_0_89), .A2(n_0_92), .ZN(JumpOrBranchPC[31]) + ); + AOI222_X1_LVT i_0_103( + .A1(n_92), .A2(n_0_99), .B1(n_0_91), .B2(n_61), .C1(n_30), .C2(n_0_90), .ZN(n_0_87) + ); + NAND2_X1_LVT i_0_104( + .A1(Illegal), .A2(CurrentPC[30]), .ZN(n_0_88) + ); + NAND2_X1_LVT i_0_102( + .A1(n_0_87), .A2(n_0_88), .ZN(JumpOrBranchPC[30]) + ); + AOI222_X1_LVT i_0_100( + .A1(n_91), .A2(n_0_99), .B1(n_0_91), .B2(n_60), .C1(n_29), .C2(n_0_90), .ZN(n_0_85) + ); + NAND2_X1_LVT i_0_101( + .A1(Illegal), .A2(CurrentPC[29]), .ZN(n_0_86) + ); + NAND2_X1_LVT i_0_99( + .A1(n_0_85), .A2(n_0_86), .ZN(JumpOrBranchPC[29]) + ); + AOI222_X1_LVT i_0_97( + .A1(n_90), .A2(n_0_99), .B1(n_0_91), .B2(n_59), .C1(n_28), .C2(n_0_90), .ZN(n_0_83) + ); + NAND2_X1_LVT i_0_98( + .A1(Illegal), .A2(CurrentPC[28]), .ZN(n_0_84) + ); + NAND2_X1_LVT i_0_96( + .A1(n_0_83), .A2(n_0_84), .ZN(JumpOrBranchPC[28]) + ); + AOI222_X1_LVT i_0_94( + .A1(n_89), .A2(n_0_99), .B1(n_0_91), .B2(n_58), .C1(n_27), .C2(n_0_90), .ZN(n_0_81) + ); + NAND2_X1_LVT i_0_95( + .A1(Illegal), .A2(CurrentPC[27]), .ZN(n_0_82) + ); + NAND2_X1_LVT i_0_93( + .A1(n_0_81), .A2(n_0_82), .ZN(JumpOrBranchPC[27]) + ); + AOI222_X1_LVT i_0_91( + .A1(n_88), .A2(n_0_99), .B1(n_0_91), .B2(n_57), .C1(n_26), .C2(n_0_90), .ZN(n_0_79) + ); + NAND2_X1_LVT i_0_92( + .A1(Illegal), .A2(CurrentPC[26]), .ZN(n_0_80) + ); + NAND2_X1_LVT i_0_90( + .A1(n_0_79), .A2(n_0_80), .ZN(JumpOrBranchPC[26]) + ); + AOI222_X1_LVT i_0_88( + .A1(n_87), .A2(n_0_99), .B1(n_0_91), .B2(n_56), .C1(n_25), .C2(n_0_90), .ZN(n_0_77) + ); + NAND2_X1_LVT i_0_89( + .A1(Illegal), .A2(CurrentPC[25]), .ZN(n_0_78) + ); + NAND2_X1_LVT i_0_87( + .A1(n_0_77), .A2(n_0_78), .ZN(JumpOrBranchPC[25]) + ); + AOI222_X1_LVT i_0_85( + .A1(n_86), .A2(n_0_99), .B1(n_0_91), .B2(n_55), .C1(n_24), .C2(n_0_90), .ZN(n_0_75) + ); + NAND2_X1_LVT i_0_86( + .A1(Illegal), .A2(CurrentPC[24]), .ZN(n_0_76) + ); + NAND2_X1_LVT i_0_84( + .A1(n_0_75), .A2(n_0_76), .ZN(JumpOrBranchPC[24]) + ); + AOI222_X1_LVT i_0_82( + .A1(n_85), .A2(n_0_99), .B1(n_0_91), .B2(n_54), .C1(n_23), .C2(n_0_90), .ZN(n_0_73) + ); + NAND2_X1_LVT i_0_83( + .A1(Illegal), .A2(CurrentPC[23]), .ZN(n_0_74) + ); + NAND2_X1_LVT i_0_81( + .A1(n_0_73), .A2(n_0_74), .ZN(JumpOrBranchPC[23]) + ); + AOI222_X1_LVT i_0_79( + .A1(n_84), .A2(n_0_99), .B1(n_0_91), .B2(n_53), .C1(n_22), .C2(n_0_90), .ZN(n_0_71) + ); + NAND2_X1_LVT i_0_80( + .A1(Illegal), .A2(CurrentPC[22]), .ZN(n_0_72) + ); + NAND2_X1_LVT i_0_78( + .A1(n_0_71), .A2(n_0_72), .ZN(JumpOrBranchPC[22]) + ); + AOI222_X1_LVT i_0_76( + .A1(n_83), .A2(n_0_99), .B1(n_0_91), .B2(n_52), .C1(n_21), .C2(n_0_90), .ZN(n_0_69) + ); + NAND2_X1_LVT i_0_77( + .A1(Illegal), .A2(CurrentPC[21]), .ZN(n_0_70) + ); + NAND2_X1_LVT i_0_75( + .A1(n_0_69), .A2(n_0_70), .ZN(JumpOrBranchPC[21]) + ); + AOI222_X1_LVT i_0_73( + .A1(n_82), .A2(n_0_99), .B1(n_0_91), .B2(n_51), .C1(n_20), .C2(n_0_90), .ZN(n_0_67) + ); + NAND2_X1_LVT i_0_74( + .A1(Illegal), .A2(CurrentPC[20]), .ZN(n_0_68) + ); + NAND2_X1_LVT i_0_72( + .A1(n_0_67), .A2(n_0_68), .ZN(JumpOrBranchPC[20]) + ); + AOI222_X1_LVT i_0_70( + .A1(n_81), .A2(n_0_99), .B1(n_0_91), .B2(n_50), .C1(n_19), .C2(n_0_90), .ZN(n_0_65) + ); + NAND2_X1_LVT i_0_71( + .A1(Illegal), .A2(CurrentPC[19]), .ZN(n_0_66) + ); + NAND2_X1_LVT i_0_69( + .A1(n_0_65), .A2(n_0_66), .ZN(JumpOrBranchPC[19]) + ); + AOI222_X1_LVT i_0_67( + .A1(n_80), .A2(n_0_99), .B1(n_0_91), .B2(n_49), .C1(n_18), .C2(n_0_90), .ZN(n_0_63) + ); + NAND2_X1_LVT i_0_68( + .A1(Illegal), .A2(CurrentPC[18]), .ZN(n_0_64) + ); + NAND2_X1_LVT i_0_66( + .A1(n_0_63), .A2(n_0_64), .ZN(JumpOrBranchPC[18]) + ); + AOI222_X1_LVT i_0_64( + .A1(n_79), .A2(n_0_99), .B1(n_0_91), .B2(n_48), .C1(n_17), .C2(n_0_90), .ZN(n_0_61) + ); + NAND2_X1_LVT i_0_65( + .A1(Illegal), .A2(CurrentPC[17]), .ZN(n_0_62) + ); + NAND2_X1_LVT i_0_63( + .A1(n_0_61), .A2(n_0_62), .ZN(JumpOrBranchPC[17]) + ); + AOI222_X1_LVT i_0_61( + .A1(n_78), .A2(n_0_99), .B1(n_0_91), .B2(n_47), .C1(n_16), .C2(n_0_90), .ZN(n_0_59) + ); + NAND2_X1_LVT i_0_62( + .A1(Illegal), .A2(CurrentPC[16]), .ZN(n_0_60) + ); + NAND2_X1_LVT i_0_60( + .A1(n_0_59), .A2(n_0_60), .ZN(JumpOrBranchPC[16]) + ); + AOI222_X1_LVT i_0_58( + .A1(n_77), .A2(n_0_99), .B1(n_0_91), .B2(n_46), .C1(n_15), .C2(n_0_90), .ZN(n_0_57) + ); + NAND2_X1_LVT i_0_59( + .A1(Illegal), .A2(CurrentPC[15]), .ZN(n_0_58) + ); + NAND2_X1_LVT i_0_57( + .A1(n_0_57), .A2(n_0_58), .ZN(JumpOrBranchPC[15]) + ); + AOI222_X1_LVT i_0_55( + .A1(n_76), .A2(n_0_99), .B1(n_0_91), .B2(n_45), .C1(n_14), .C2(n_0_90), .ZN(n_0_55) + ); + NAND2_X1_LVT i_0_56( + .A1(Illegal), .A2(CurrentPC[14]), .ZN(n_0_56) + ); + NAND2_X1_LVT i_0_54( + .A1(n_0_55), .A2(n_0_56), .ZN(JumpOrBranchPC[14]) + ); + AOI222_X1_LVT i_0_52( + .A1(n_75), .A2(n_0_99), .B1(n_0_91), .B2(n_44), .C1(n_13), .C2(n_0_90), .ZN(n_0_53) + ); + NAND2_X1_LVT i_0_53( + .A1(Illegal), .A2(CurrentPC[13]), .ZN(n_0_54) + ); + NAND2_X1_LVT i_0_51( + .A1(n_0_53), .A2(n_0_54), .ZN(JumpOrBranchPC[13]) + ); + AOI222_X1_LVT i_0_49( + .A1(n_74), .A2(n_0_99), .B1(n_0_91), .B2(n_43), .C1(n_12), .C2(n_0_90), .ZN(n_0_51) + ); + NAND2_X1_LVT i_0_50( + .A1(Illegal), .A2(CurrentPC[12]), .ZN(n_0_52) + ); + NAND2_X1_LVT i_0_48( + .A1(n_0_51), .A2(n_0_52), .ZN(JumpOrBranchPC[12]) + ); + AOI222_X1_LVT i_0_46( + .A1(n_73), .A2(n_0_99), .B1(n_0_91), .B2(n_42), .C1(n_11), .C2(n_0_90), .ZN(n_0_49) + ); + NAND2_X1_LVT i_0_47( + .A1(Illegal), .A2(CurrentPC[11]), .ZN(n_0_50) + ); + NAND2_X1_LVT i_0_45( + .A1(n_0_49), .A2(n_0_50), .ZN(JumpOrBranchPC[11]) + ); + AOI222_X1_LVT i_0_43( + .A1(n_72), .A2(n_0_99), .B1(n_0_91), .B2(n_41), .C1(n_10), .C2(n_0_90), .ZN(n_0_47) + ); + NAND2_X1_LVT i_0_44( + .A1(Illegal), .A2(CurrentPC[10]), .ZN(n_0_48) + ); + NAND2_X1_LVT i_0_42( + .A1(n_0_47), .A2(n_0_48), .ZN(JumpOrBranchPC[10]) + ); + AOI222_X1_LVT i_0_40( + .A1(n_71), .A2(n_0_99), .B1(n_0_91), .B2(n_40), .C1(n_9), .C2(n_0_90), .ZN(n_0_45) + ); + NAND2_X1_LVT i_0_41( + .A1(Illegal), .A2(CurrentPC[9]), .ZN(n_0_46) + ); + NAND2_X1_LVT i_0_39( + .A1(n_0_45), .A2(n_0_46), .ZN(JumpOrBranchPC[9]) + ); + AOI222_X1_LVT i_0_37( + .A1(n_70), .A2(n_0_99), .B1(n_0_91), .B2(n_39), .C1(n_8), .C2(n_0_90), .ZN(n_0_43) + ); + NAND2_X1_LVT i_0_38( + .A1(Illegal), .A2(CurrentPC[8]), .ZN(n_0_44) + ); + NAND2_X1_LVT i_0_36( + .A1(n_0_43), .A2(n_0_44), .ZN(JumpOrBranchPC[8]) + ); + AOI222_X1_LVT i_0_34( + .A1(n_69), .A2(n_0_99), .B1(n_0_91), .B2(n_38), .C1(n_7), .C2(n_0_90), .ZN(n_0_41) + ); + NAND2_X1_LVT i_0_35( + .A1(Illegal), .A2(CurrentPC[7]), .ZN(n_0_42) + ); + NAND2_X1_LVT i_0_33( + .A1(n_0_41), .A2(n_0_42), .ZN(JumpOrBranchPC[7]) + ); + AOI222_X1_LVT i_0_31( + .A1(n_68), .A2(n_0_99), .B1(n_0_91), .B2(n_37), .C1(n_6), .C2(n_0_90), .ZN(n_0_39) + ); + NAND2_X1_LVT i_0_32( + .A1(Illegal), .A2(CurrentPC[6]), .ZN(n_0_40) + ); + NAND2_X1_LVT i_0_30( + .A1(n_0_39), .A2(n_0_40), .ZN(JumpOrBranchPC[6]) + ); + AOI222_X1_LVT i_0_28( + .A1(n_67), .A2(n_0_99), .B1(n_0_91), .B2(n_36), .C1(n_5), .C2(n_0_90), .ZN(n_0_37) + ); + NAND2_X1_LVT i_0_29( + .A1(Illegal), .A2(CurrentPC[5]), .ZN(n_0_38) + ); + NAND2_X1_LVT i_0_27( + .A1(n_0_37), .A2(n_0_38), .ZN(JumpOrBranchPC[5]) + ); + AOI222_X1_LVT i_0_25( + .A1(n_66), .A2(n_0_99), .B1(n_0_91), .B2(n_35), .C1(n_4), .C2(n_0_90), .ZN(n_0_35) + ); + NAND2_X1_LVT i_0_26( + .A1(Illegal), .A2(CurrentPC[4]), .ZN(n_0_36) + ); + NAND2_X1_LVT i_0_24( + .A1(n_0_35), .A2(n_0_36), .ZN(JumpOrBranchPC[4]) + ); + AOI222_X1_LVT i_0_22( + .A1(n_65), .A2(n_0_99), .B1(n_0_91), .B2(n_34), .C1(n_3), .C2(n_0_90), .ZN(n_0_33) + ); + NAND2_X1_LVT i_0_23( + .A1(Illegal), .A2(CurrentPC[3]), .ZN(n_0_34) + ); + NAND2_X1_LVT i_0_21( + .A1(n_0_33), .A2(n_0_34), .ZN(JumpOrBranchPC[3]) + ); + AOI222_X1_LVT i_0_19( + .A1(n_64), .A2(n_0_99), .B1(n_0_91), .B2(n_33), .C1(n_2), .C2(n_0_90), .ZN(n_0_31) + ); + NAND2_X1_LVT i_0_20( + .A1(Illegal), .A2(CurrentPC[2]), .ZN(n_0_32) + ); + NAND2_X1_LVT i_0_18( + .A1(n_0_31), .A2(n_0_32), .ZN(JumpOrBranchPC[2]) + ); + AOI222_X1_LVT i_0_16( + .A1(n_63), .A2(n_0_99), .B1(n_0_91), .B2(n_32), .C1(n_1), .C2(n_0_90), .ZN(n_0_29) + ); + NAND2_X1_LVT i_0_17( + .A1(Illegal), .A2(CurrentPC[1]), .ZN(n_0_30) + ); + NAND2_X1_LVT i_0_15( + .A1(n_0_29), .A2(n_0_30), .ZN(JumpOrBranchPC[1]) + ); + NOR2_X1_LVT i_0_112( + .A1(n_0_232), .A2(n_0_238), .ZN(n_0_94) + ); + OAI221_X1_LVT i_0_14( + .A(n_0_94), .B1(n_0_225), .B2(Instruction[2]), .C1(Instruction[6]), .C2(n_0_239), + .ZN(n_0_28) + ); + AND2_X1_LVT i_0_13( + .A1(n_0_28), .A2(CurrentPC[0]), .ZN(JumpOrBranchPC[0]) + ); + NOR2_X1_LVT i_0_221( + .A1(Instruction[13]), .A2(Instruction[14]), .ZN(n_0_166) + ); + NOR3_X1_LVT i_0_293( + .A1(n_0_241), .A2(n_0_234), .A3(Instruction[3]), .ZN(n_0_206) + ); + AND2_X1_LVT i_0_292( + .A1(n_0_206), .A2(n_0_244), .ZN(n_0_205) + ); + NOR3_X1_LVT i_0_330( + .A1(n_0_248), .A2(n_0_244), .A3(Instruction[4]), .ZN(n_0_226) + ); + AOI21_X1_LVT i_0_121( + .A(n_0_205), .B1(n_0_226), .B2(n_0_237), .ZN(n_0_100) + ); + AND2_X1_LVT i_0_120( + .A1(Instruction[14]), .A2(n_0_100), .ZN(aluOp[2]) + ); + OAI33_X1_LVT i_0_119( + .A1(n_0_205), .A2(n_0_247), .A3(n_0_224), .B1(Instruction[2]), .B2(n_0_238), + .B3(n_0_225), .ZN(aluOp[1]) + ); + AOI22_X1_LVT i_0_117( + .A1(Instruction[12]), .A2(n_0_100), .B1(n_0_99), .B2(Instruction[13]), .ZN(n_0_98) + ); + INV_X1_LVT i_0_116( + .A(n_0_98), .ZN(aluOp[0]) + ); + OR2_X1_LVT i_0_327( + .A1(n_0_238), .A2(n_0_234), .ZN(n_0_223) + ); + NOR4_X1_LVT i_0_125( + .A1(Instruction[28]), .A2(Instruction[27]), .A3(Instruction[26]), .A4(Instruction[25]), + .ZN(n_0_103) + ); + INV_X1_LVT i_0_347( + .A(Instruction[30]), .ZN(n_0_242) + ); + NOR4_X1_LVT i_0_124( + .A1(Instruction[13]), .A2(n_0_242), .A3(Instruction[29]), .A4(Instruction[31]), + .ZN(n_0_102) + ); + NAND2_X1_LVT i_0_123( + .A1(n_0_103), .A2(n_0_102), .ZN(n_0_101) + ); + NOR3_X1_LVT i_0_127( + .A1(n_0_244), .A2(Instruction[12]), .A3(Instruction[14]), .ZN(n_0_105) + ); + AOI21_X1_LVT i_0_126( + .A(n_0_105), .B1(Instruction[12]), .B2(Instruction[14]), .ZN(n_0_104) + ); + NOR4_X1_LVT i_0_122( + .A1(n_0_223), .A2(n_0_101), .A3(n_0_104), .A4(Instruction[2]), .ZN(aluNegAr) + ); + OR3_X1_LVT i_0_325( + .A1(n_0_228), .A2(Instruction[4]), .A3(Instruction[6]), .ZN(n_0_222) + ); + NOR2_X1_LVT i_0_321( + .A1(n_0_222), .A2(Instruction[5]), .ZN(n_0_221) + ); + NOR3_X1_LVT i_0_224( + .A1(n_0_224), .A2(n_0_221), .A3(n_0_206), .ZN(n_0_169) + ); + NOR3_X1_LVT i_0_129( + .A1(n_0_234), .A2(Instruction[3]), .A3(Instruction[5]), .ZN(n_0_106) + ); + NOR3_X1_LVT i_0_128( + .A1(n_0_226), .A2(n_0_169), .A3(n_0_106), .ZN(aluBypass) + ); + AOI22_X1_LVT i_0_223( + .A1(CurrentPC[31]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[31]), .ZN(n_0_168) + ); + NOR3_X1_LVT i_0_219( + .A1(n_0_247), .A2(n_0_222), .A3(Instruction[5]), .ZN(n_0_164) + ); + AOI22_X1_LVT i_0_218( + .A1(RRs1[31]), .A2(n_0_169), .B1(n_0_164), .B2(RData[31]), .ZN(n_0_163) + ); + MUX2_X1_LVT i_0_222( + .A(RData[7]), .B(RData[15]), .S(Instruction[12]), .Z(n_0_167) + ); + NAND3_X1_LVT i_0_220( + .A1(n_0_221), .A2(n_0_167), .A3(n_0_166), .ZN(n_0_165) + ); + NAND3_X1_LVT i_0_217( + .A1(n_0_168), .A2(n_0_163), .A3(n_0_165), .ZN(op1[31]) + ); + AOI22_X1_LVT i_0_216( + .A1(RRs1[30]), .A2(n_0_169), .B1(n_0_164), .B2(RData[30]), .ZN(n_0_162) + ); + AOI22_X1_LVT i_0_215( + .A1(CurrentPC[30]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[30]), .ZN(n_0_161) + ); + NAND3_X1_LVT i_0_214( + .A1(n_0_162), .A2(n_0_161), .A3(n_0_165), .ZN(op1[30]) + ); + AOI22_X1_LVT i_0_213( + .A1(RRs1[29]), .A2(n_0_169), .B1(n_0_164), .B2(RData[29]), .ZN(n_0_160) + ); + AOI22_X1_LVT i_0_212( + .A1(CurrentPC[29]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[29]), .ZN(n_0_159) + ); + NAND3_X1_LVT i_0_211( + .A1(n_0_160), .A2(n_0_159), .A3(n_0_165), .ZN(op1[29]) + ); + AOI22_X1_LVT i_0_210( + .A1(RRs1[28]), .A2(n_0_169), .B1(n_0_164), .B2(RData[28]), .ZN(n_0_158) + ); + AOI22_X1_LVT i_0_209( + .A1(CurrentPC[28]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[28]), .ZN(n_0_157) + ); + NAND3_X1_LVT i_0_208( + .A1(n_0_158), .A2(n_0_157), .A3(n_0_165), .ZN(op1[28]) + ); + AOI22_X1_LVT i_0_207( + .A1(RRs1[27]), .A2(n_0_169), .B1(n_0_164), .B2(RData[27]), .ZN(n_0_156) + ); + AOI22_X1_LVT i_0_206( + .A1(CurrentPC[27]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[27]), .ZN(n_0_155) + ); + NAND3_X1_LVT i_0_205( + .A1(n_0_156), .A2(n_0_155), .A3(n_0_165), .ZN(op1[27]) + ); + AOI22_X1_LVT i_0_204( + .A1(RRs1[26]), .A2(n_0_169), .B1(n_0_164), .B2(RData[26]), .ZN(n_0_154) + ); + AOI22_X1_LVT i_0_203( + .A1(CurrentPC[26]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[26]), .ZN(n_0_153) + ); + NAND3_X1_LVT i_0_202( + .A1(n_0_154), .A2(n_0_153), .A3(n_0_165), .ZN(op1[26]) + ); + AOI22_X1_LVT i_0_201( + .A1(RRs1[25]), .A2(n_0_169), .B1(n_0_164), .B2(RData[25]), .ZN(n_0_152) + ); + AOI22_X1_LVT i_0_200( + .A1(CurrentPC[25]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[25]), .ZN(n_0_151) + ); + NAND3_X1_LVT i_0_199( + .A1(n_0_152), .A2(n_0_151), .A3(n_0_165), .ZN(op1[25]) + ); + AOI22_X1_LVT i_0_198( + .A1(RRs1[24]), .A2(n_0_169), .B1(n_0_164), .B2(RData[24]), .ZN(n_0_150) + ); + AOI22_X1_LVT i_0_197( + .A1(CurrentPC[24]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[24]), .ZN(n_0_149) + ); + NAND3_X1_LVT i_0_196( + .A1(n_0_150), .A2(n_0_149), .A3(n_0_165), .ZN(op1[24]) + ); + AOI22_X1_LVT i_0_195( + .A1(RRs1[23]), .A2(n_0_169), .B1(n_0_164), .B2(RData[23]), .ZN(n_0_148) + ); + AOI22_X1_LVT i_0_194( + .A1(CurrentPC[23]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[23]), .ZN(n_0_147) + ); + NAND3_X1_LVT i_0_193( + .A1(n_0_148), .A2(n_0_147), .A3(n_0_165), .ZN(op1[23]) + ); + AOI22_X1_LVT i_0_192( + .A1(RRs1[22]), .A2(n_0_169), .B1(n_0_164), .B2(RData[22]), .ZN(n_0_146) + ); + AOI22_X1_LVT i_0_191( + .A1(CurrentPC[22]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[22]), .ZN(n_0_145) + ); + NAND3_X1_LVT i_0_190( + .A1(n_0_146), .A2(n_0_145), .A3(n_0_165), .ZN(op1[22]) + ); + AOI22_X1_LVT i_0_189( + .A1(RRs1[21]), .A2(n_0_169), .B1(n_0_164), .B2(RData[21]), .ZN(n_0_144) + ); + AOI22_X1_LVT i_0_188( + .A1(CurrentPC[21]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[21]), .ZN(n_0_143) + ); + NAND3_X1_LVT i_0_187( + .A1(n_0_144), .A2(n_0_143), .A3(n_0_165), .ZN(op1[21]) + ); + AOI22_X1_LVT i_0_186( + .A1(RRs1[20]), .A2(n_0_169), .B1(n_0_164), .B2(RData[20]), .ZN(n_0_142) + ); + AOI22_X1_LVT i_0_185( + .A1(CurrentPC[20]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[20]), .ZN(n_0_141) + ); + NAND3_X1_LVT i_0_184( + .A1(n_0_142), .A2(n_0_141), .A3(n_0_165), .ZN(op1[20]) + ); + AOI22_X1_LVT i_0_183( + .A1(RRs1[19]), .A2(n_0_169), .B1(n_0_164), .B2(RData[19]), .ZN(n_0_140) + ); + AOI22_X1_LVT i_0_182( + .A1(CurrentPC[19]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[19]), .ZN(n_0_139) + ); + NAND3_X1_LVT i_0_181( + .A1(n_0_140), .A2(n_0_139), .A3(n_0_165), .ZN(op1[19]) + ); + AOI22_X1_LVT i_0_180( + .A1(RRs1[18]), .A2(n_0_169), .B1(n_0_164), .B2(RData[18]), .ZN(n_0_138) + ); + AOI22_X1_LVT i_0_179( + .A1(CurrentPC[18]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[18]), .ZN(n_0_137) + ); + NAND3_X1_LVT i_0_178( + .A1(n_0_138), .A2(n_0_137), .A3(n_0_165), .ZN(op1[18]) + ); + AOI22_X1_LVT i_0_177( + .A1(RRs1[17]), .A2(n_0_169), .B1(n_0_164), .B2(RData[17]), .ZN(n_0_136) + ); + AOI22_X1_LVT i_0_176( + .A1(CurrentPC[17]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[17]), .ZN(n_0_135) + ); + NAND3_X1_LVT i_0_175( + .A1(n_0_136), .A2(n_0_135), .A3(n_0_165), .ZN(op1[17]) + ); + AOI22_X1_LVT i_0_174( + .A1(RRs1[16]), .A2(n_0_169), .B1(n_0_164), .B2(RData[16]), .ZN(n_0_134) + ); + AOI22_X1_LVT i_0_173( + .A1(CurrentPC[16]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[16]), .ZN(n_0_133) + ); + NAND3_X1_LVT i_0_172( + .A1(n_0_134), .A2(n_0_133), .A3(n_0_165), .ZN(op1[16]) + ); + AOI222_X1_LVT i_0_169( + .A1(CurrentPC[15]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[15]), .C1(n_0_169), + .C2(RRs1[15]), .ZN(n_0_130) + ); + INV_X1_LVT i_0_353( + .A(Instruction[12]), .ZN(n_0_246) + ); + AOI211_X1_LVT i_0_171( + .A(Instruction[5]), .B(n_0_222), .C1(n_0_247), .C2(n_0_246), .ZN(n_0_132) + ); + OAI211_X1_LVT i_0_170( + .A(RData[15]), .B(n_0_132), .C1(Instruction[13]), .C2(Instruction[14]), .ZN(n_0_131) + ); + NAND3_X1_LVT i_0_168( + .A1(n_0_130), .A2(n_0_131), .A3(n_0_165), .ZN(op1[15]) + ); + AOI22_X1_LVT i_0_167( + .A1(RRs1[14]), .A2(n_0_169), .B1(n_0_132), .B2(RData[14]), .ZN(n_0_129) + ); + AOI22_X1_LVT i_0_166( + .A1(CurrentPC[14]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[14]), .ZN(n_0_128) + ); + NAND4_X1_LVT i_0_165( + .A1(n_0_221), .A2(n_0_246), .A3(RData[7]), .A4(n_0_166), .ZN(n_0_127) + ); + NAND3_X1_LVT i_0_164( + .A1(n_0_129), .A2(n_0_128), .A3(n_0_127), .ZN(op1[14]) + ); + AOI22_X1_LVT i_0_163( + .A1(RRs1[13]), .A2(n_0_169), .B1(n_0_132), .B2(RData[13]), .ZN(n_0_126) + ); + AOI22_X1_LVT i_0_162( + .A1(CurrentPC[13]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[13]), .ZN(n_0_125) + ); + NAND3_X1_LVT i_0_161( + .A1(n_0_126), .A2(n_0_125), .A3(n_0_127), .ZN(op1[13]) + ); + AOI22_X1_LVT i_0_160( + .A1(RRs1[12]), .A2(n_0_169), .B1(n_0_132), .B2(RData[12]), .ZN(n_0_124) + ); + AOI22_X1_LVT i_0_159( + .A1(CurrentPC[12]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[12]), .ZN(n_0_123) + ); + NAND3_X1_LVT i_0_158( + .A1(n_0_124), .A2(n_0_123), .A3(n_0_127), .ZN(op1[12]) + ); + AOI22_X1_LVT i_0_156( + .A1(CurrentPC[11]), .A2(n_0_224), .B1(n_0_132), .B2(RData[11]), .ZN(n_0_121) + ); + NAND2_X1_LVT i_0_157( + .A1(RRs1[11]), .A2(n_0_169), .ZN(n_0_122) + ); + NAND3_X1_LVT i_0_155( + .A1(n_0_121), .A2(n_0_122), .A3(n_0_127), .ZN(op1[11]) + ); + AOI22_X1_LVT i_0_153( + .A1(CurrentPC[10]), .A2(n_0_224), .B1(n_0_132), .B2(RData[10]), .ZN(n_0_119) + ); + NAND2_X1_LVT i_0_154( + .A1(RRs1[10]), .A2(n_0_169), .ZN(n_0_120) + ); + NAND3_X1_LVT i_0_152( + .A1(n_0_119), .A2(n_0_120), .A3(n_0_127), .ZN(op1[10]) + ); + AOI22_X1_LVT i_0_150( + .A1(CurrentPC[9]), .A2(n_0_224), .B1(n_0_132), .B2(RData[9]), .ZN(n_0_117) + ); + NAND2_X1_LVT i_0_151( + .A1(RRs1[9]), .A2(n_0_169), .ZN(n_0_118) + ); + NAND3_X1_LVT i_0_149( + .A1(n_0_117), .A2(n_0_118), .A3(n_0_127), .ZN(op1[9]) + ); + AOI22_X1_LVT i_0_147( + .A1(CurrentPC[8]), .A2(n_0_224), .B1(n_0_132), .B2(RData[8]), .ZN(n_0_115) + ); + NAND2_X1_LVT i_0_148( + .A1(RRs1[8]), .A2(n_0_169), .ZN(n_0_116) + ); + NAND3_X1_LVT i_0_146( + .A1(n_0_115), .A2(n_0_116), .A3(n_0_127), .ZN(op1[8]) + ); + AOI222_X1_LVT i_0_145( + .A1(CurrentPC[7]), .A2(n_0_224), .B1(n_0_221), .B2(RData[7]), .C1(n_0_169), + .C2(RRs1[7]), .ZN(n_0_114) + ); + INV_X1_LVT i_0_144( + .A(n_0_114), .ZN(op1[7]) + ); + AOI222_X1_LVT i_0_143( + .A1(CurrentPC[6]), .A2(n_0_224), .B1(n_0_221), .B2(RData[6]), .C1(n_0_169), + .C2(RRs1[6]), .ZN(n_0_113) + ); + INV_X1_LVT i_0_142( + .A(n_0_113), .ZN(op1[6]) + ); + AOI222_X1_LVT i_0_141( + .A1(CurrentPC[5]), .A2(n_0_224), .B1(n_0_221), .B2(RData[5]), .C1(n_0_169), + .C2(RRs1[5]), .ZN(n_0_112) + ); + INV_X1_LVT i_0_140( + .A(n_0_112), .ZN(op1[5]) + ); + AOI222_X1_LVT i_0_139( + .A1(CurrentPC[4]), .A2(n_0_224), .B1(n_0_221), .B2(RData[4]), .C1(n_0_169), + .C2(RRs1[4]), .ZN(n_0_111) + ); + INV_X1_LVT i_0_138( + .A(n_0_111), .ZN(op1[4]) + ); + AOI222_X1_LVT i_0_137( + .A1(CurrentPC[3]), .A2(n_0_224), .B1(n_0_221), .B2(RData[3]), .C1(n_0_169), + .C2(RRs1[3]), .ZN(n_0_110) + ); + INV_X1_LVT i_0_136( + .A(n_0_110), .ZN(op1[3]) + ); + AOI222_X1_LVT i_0_135( + .A1(CurrentPC[2]), .A2(n_0_224), .B1(n_0_221), .B2(RData[2]), .C1(n_0_169), + .C2(RRs1[2]), .ZN(n_0_109) + ); + INV_X1_LVT i_0_134( + .A(n_0_109), .ZN(op1[2]) + ); + AOI222_X1_LVT i_0_133( + .A1(CurrentPC[1]), .A2(n_0_224), .B1(n_0_221), .B2(RData[1]), .C1(n_0_169), + .C2(RRs1[1]), .ZN(n_0_108) + ); + INV_X1_LVT i_0_132( + .A(n_0_108), .ZN(op1[1]) + ); + AOI222_X1_LVT i_0_131( + .A1(CurrentPC[0]), .A2(n_0_224), .B1(n_0_221), .B2(RData[0]), .C1(n_0_169), + .C2(RRs1[0]), .ZN(n_0_107) + ); + INV_X1_LVT i_0_130( + .A(n_0_107), .ZN(op1[0]) + ); + NOR3_X1_LVT i_0_294( + .A1(n_0_223), .A2(Instruction[2]), .A3(Instruction[5]), .ZN(n_0_207) + ); + NOR3_X1_LVT i_0_291( + .A1(n_0_224), .A2(n_0_207), .A3(n_0_205), .ZN(n_0_204) + ); + AOI22_X1_LVT i_0_289( + .A1(CurrentPC[31]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[31]), .ZN(n_0_202) + ); + NAND2_X1_LVT i_0_290( + .A1(Instruction[31]), .A2(n_0_207), .ZN(n_0_203) + ); + NAND2_X1_LVT i_0_288( + .A1(n_0_202), .A2(n_0_203), .ZN(op2[31]) + ); + AOI22_X1_LVT i_0_287( + .A1(CurrentPC[30]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[30]), .ZN(n_0_201) + ); + NAND2_X1_LVT i_0_286( + .A1(n_0_201), .A2(n_0_203), .ZN(op2[30]) + ); + AOI22_X1_LVT i_0_285( + .A1(CurrentPC[29]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[29]), .ZN(n_0_200) + ); + NAND2_X1_LVT i_0_284( + .A1(n_0_200), .A2(n_0_203), .ZN(op2[29]) + ); + AOI22_X1_LVT i_0_283( + .A1(CurrentPC[28]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[28]), .ZN(n_0_199) + ); + NAND2_X1_LVT i_0_282( + .A1(n_0_199), .A2(n_0_203), .ZN(op2[28]) + ); + AOI22_X1_LVT i_0_281( + .A1(CurrentPC[27]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[27]), .ZN(n_0_198) + ); + NAND2_X1_LVT i_0_280( + .A1(n_0_198), .A2(n_0_203), .ZN(op2[27]) + ); + AOI22_X1_LVT i_0_279( + .A1(CurrentPC[26]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[26]), .ZN(n_0_197) + ); + NAND2_X1_LVT i_0_278( + .A1(n_0_197), .A2(n_0_203), .ZN(op2[26]) + ); + AOI22_X1_LVT i_0_277( + .A1(CurrentPC[25]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[25]), .ZN(n_0_196) + ); + NAND2_X1_LVT i_0_276( + .A1(n_0_196), .A2(n_0_203), .ZN(op2[25]) + ); + AOI22_X1_LVT i_0_275( + .A1(CurrentPC[24]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[24]), .ZN(n_0_195) + ); + NAND2_X1_LVT i_0_274( + .A1(n_0_195), .A2(n_0_203), .ZN(op2[24]) + ); + AOI22_X1_LVT i_0_273( + .A1(CurrentPC[23]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[23]), .ZN(n_0_194) + ); + NAND2_X1_LVT i_0_272( + .A1(n_0_194), .A2(n_0_203), .ZN(op2[23]) + ); + AOI22_X1_LVT i_0_271( + .A1(CurrentPC[22]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[22]), .ZN(n_0_193) + ); + NAND2_X1_LVT i_0_270( + .A1(n_0_193), .A2(n_0_203), .ZN(op2[22]) + ); + AOI22_X1_LVT i_0_269( + .A1(CurrentPC[21]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[21]), .ZN(n_0_192) + ); + NAND2_X1_LVT i_0_268( + .A1(n_0_192), .A2(n_0_203), .ZN(op2[21]) + ); + AOI22_X1_LVT i_0_267( + .A1(CurrentPC[20]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[20]), .ZN(n_0_191) + ); + NAND2_X1_LVT i_0_266( + .A1(n_0_191), .A2(n_0_203), .ZN(op2[20]) + ); + AOI22_X1_LVT i_0_265( + .A1(CurrentPC[19]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[19]), .ZN(n_0_190) + ); + NAND2_X1_LVT i_0_264( + .A1(n_0_190), .A2(n_0_203), .ZN(op2[19]) + ); + AOI22_X1_LVT i_0_263( + .A1(CurrentPC[18]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[18]), .ZN(n_0_189) + ); + NAND2_X1_LVT i_0_262( + .A1(n_0_189), .A2(n_0_203), .ZN(op2[18]) + ); + AOI22_X1_LVT i_0_261( + .A1(CurrentPC[17]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[17]), .ZN(n_0_188) + ); + NAND2_X1_LVT i_0_260( + .A1(n_0_188), .A2(n_0_203), .ZN(op2[17]) + ); + AOI22_X1_LVT i_0_259( + .A1(CurrentPC[16]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[16]), .ZN(n_0_187) + ); + NAND2_X1_LVT i_0_258( + .A1(n_0_187), .A2(n_0_203), .ZN(op2[16]) + ); + AOI22_X1_LVT i_0_257( + .A1(CurrentPC[15]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[15]), .ZN(n_0_186) + ); + NAND2_X1_LVT i_0_256( + .A1(n_0_186), .A2(n_0_203), .ZN(op2[15]) + ); + AOI22_X1_LVT i_0_255( + .A1(CurrentPC[14]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[14]), .ZN(n_0_185) + ); + NAND2_X1_LVT i_0_254( + .A1(n_0_185), .A2(n_0_203), .ZN(op2[14]) + ); + AOI22_X1_LVT i_0_253( + .A1(CurrentPC[13]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[13]), .ZN(n_0_184) + ); + NAND2_X1_LVT i_0_252( + .A1(n_0_184), .A2(n_0_203), .ZN(op2[13]) + ); + AOI22_X1_LVT i_0_251( + .A1(CurrentPC[12]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[12]), .ZN(n_0_183) + ); + NAND2_X1_LVT i_0_250( + .A1(n_0_183), .A2(n_0_203), .ZN(op2[12]) + ); + AOI22_X1_LVT i_0_249( + .A1(CurrentPC[11]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[11]), .ZN(n_0_182) + ); + NAND2_X1_LVT i_0_248( + .A1(n_0_182), .A2(n_0_203), .ZN(op2[11]) + ); + AOI222_X1_LVT i_0_247( + .A1(Instruction[30]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[10]), .C1(n_0_204), + .C2(RRs2[10]), .ZN(n_0_181) + ); + INV_X1_LVT i_0_246( + .A(n_0_181), .ZN(op2[10]) + ); + AOI222_X1_LVT i_0_245( + .A1(Instruction[29]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[9]), .C1(n_0_204), + .C2(RRs2[9]), .ZN(n_0_180) + ); + INV_X1_LVT i_0_244( + .A(n_0_180), .ZN(op2[9]) + ); + AOI222_X1_LVT i_0_243( + .A1(Instruction[28]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[8]), .C1(n_0_204), + .C2(RRs2[8]), .ZN(n_0_179) + ); + INV_X1_LVT i_0_242( + .A(n_0_179), .ZN(op2[8]) + ); + AOI222_X1_LVT i_0_241( + .A1(Instruction[27]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[7]), .C1(n_0_204), + .C2(RRs2[7]), .ZN(n_0_178) + ); + INV_X1_LVT i_0_240( + .A(n_0_178), .ZN(op2[7]) + ); + AOI222_X1_LVT i_0_239( + .A1(Instruction[26]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[6]), .C1(n_0_204), + .C2(RRs2[6]), .ZN(n_0_177) + ); + INV_X1_LVT i_0_238( + .A(n_0_177), .ZN(op2[6]) + ); + AOI222_X1_LVT i_0_237( + .A1(Instruction[25]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[5]), .C1(n_0_204), + .C2(RRs2[5]), .ZN(n_0_176) + ); + INV_X1_LVT i_0_236( + .A(n_0_176), .ZN(op2[5]) + ); + AOI222_X1_LVT i_0_235( + .A1(Instruction[24]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[4]), .C1(n_0_204), + .C2(RRs2[4]), .ZN(n_0_175) + ); + INV_X1_LVT i_0_234( + .A(n_0_175), .ZN(op2[4]) + ); + AOI222_X1_LVT i_0_233( + .A1(Instruction[23]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[3]), .C1(n_0_204), + .C2(RRs2[3]), .ZN(n_0_174) + ); + INV_X1_LVT i_0_232( + .A(n_0_174), .ZN(op2[3]) + ); + AOI22_X1_LVT i_0_230( + .A1(Instruction[22]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[2]), .ZN(n_0_172) + ); + OAI21_X1_LVT i_0_231( + .A(RRs2[2]), .B1(n_0_223), .B2(Instruction[5]), .ZN(n_0_173) + ); + NAND3_X1_LVT i_0_229( + .A1(n_0_172), .A2(n_0_173), .A3(n_0_249), .ZN(op2[2]) + ); + AOI222_X1_LVT i_0_228( + .A1(Instruction[21]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[1]), .C1(n_0_204), + .C2(RRs2[1]), .ZN(n_0_171) + ); + INV_X1_LVT i_0_227( + .A(n_0_171), .ZN(op2[1]) + ); + AOI222_X1_LVT i_0_226( + .A1(Instruction[20]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[0]), .C1(n_0_204), + .C2(RRs2[0]), .ZN(n_0_170) + ); + INV_X1_LVT i_0_225( + .A(n_0_170), .ZN(op2[0]) + ); + alu theALU( + .aluOp(aluOp), .aluNegAr(aluNegAr), .aluBypass(aluBypass), .op1(op1), .op2(op2), + .result(WRd), .eqFlag(eqFlag) + ); + XNOR2_X1_LVT i_0_115( + .A(Instruction[12]), .B(eqFlag), .ZN(n_0_97) + ); + XNOR2_X1_LVT i_0_114( + .A(Instruction[12]), .B(WRd[0]), .ZN(n_0_96) + ); + AOI22_X1_LVT i_0_113( + .A1(n_0_166), .A2(n_0_97), .B1(n_0_96), .B2(Instruction[14]), .ZN(n_0_95) + ); + AOI22_X1_LVT i_0_111( + .A1(Instruction[6]), .A2(n_0_95), .B1(Instruction[2]), .B2(n_0_245), .ZN(n_0_93) + ); + NAND2_X1_LVT i_0_110( + .A1(n_0_94), .A2(n_0_93), .ZN(JumpOrBranch) + ); + INV_X1_LVT i_0_349( + .A(Instruction[31]), .ZN(n_0_0) + ); + INV_X1_LVT i_0_348( + .A(RRs1[12]), .ZN(n_0_1) + ); + HA_X1_LVT i_0_0( + .A(Instruction[7]), .B(RRs1[0]), .CO(n_0_2), .S(n_0_15) + ); + FA_X1_LVT i_0_1( + .A(Instruction[8]), .B(RRs1[1]), .CI(n_0_2), .CO(n_0_3), .S(n_0_16) + ); + FA_X1_LVT i_0_2( + .A(Instruction[9]), .B(RRs1[2]), .CI(n_0_3), .CO(n_0_4), .S(n_0_17) + ); + FA_X1_LVT i_0_3( + .A(Instruction[10]), .B(RRs1[3]), .CI(n_0_4), .CO(n_0_5), .S(n_0_18) + ); + FA_X1_LVT i_0_4( + .A(Instruction[11]), .B(RRs1[4]), .CI(n_0_5), .CO(n_0_6), .S(n_0_19) + ); + FA_X1_LVT i_0_5( + .A(Instruction[25]), .B(RRs1[5]), .CI(n_0_6), .CO(n_0_7), .S(n_0_20) + ); + FA_X1_LVT i_0_6( + .A(Instruction[26]), .B(RRs1[6]), .CI(n_0_7), .CO(n_0_8), .S(n_0_21) + ); + FA_X1_LVT i_0_7( + .A(Instruction[27]), .B(RRs1[7]), .CI(n_0_8), .CO(n_0_9), .S(n_0_22) + ); + FA_X1_LVT i_0_8( + .A(Instruction[28]), .B(RRs1[8]), .CI(n_0_9), .CO(n_0_10), .S(n_0_23) + ); + FA_X1_LVT i_0_9( + .A(Instruction[29]), .B(RRs1[9]), .CI(n_0_10), .CO(n_0_11), .S(n_0_24) + ); + FA_X1_LVT i_0_10( + .A(Instruction[30]), .B(RRs1[10]), .CI(n_0_11), .CO(n_0_12), .S(n_0_25) + ); + FA_X1_LVT i_0_11( + .A(RRs1[11]), .B(Instruction[31]), .CI(n_0_12), .CO(n_0_13), .S(n_0_26) + ); + FA_X1_LVT i_0_12( + .A(n_0_0), .B(n_0_1), .CI(n_0_13), .CO(n_0_14), .S(n_0_27) + ); + NOR2_X1_LVT i_0_322( + .A1(n_0_244), .A2(n_0_222), .ZN(WrMem) + ); + AOI22_X1_LVT i_0_320( + .A1(n_0_27), .A2(WrMem), .B1(n_0_221), .B2(n_12), .ZN(n_0_220) + ); + INV_X1_LVT i_0_319( + .A(n_0_220), .ZN(DAddr[12]) + ); + AOI22_X1_LVT i_0_318( + .A1(n_0_26), .A2(WrMem), .B1(n_0_221), .B2(n_11), .ZN(n_0_219) + ); + INV_X1_LVT i_0_317( + .A(n_0_219), .ZN(DAddr[11]) + ); + AOI22_X1_LVT i_0_316( + .A1(n_0_25), .A2(WrMem), .B1(n_0_221), .B2(n_10), .ZN(n_0_218) + ); + INV_X1_LVT i_0_315( + .A(n_0_218), .ZN(DAddr[10]) + ); + AOI22_X1_LVT i_0_314( + .A1(n_0_24), .A2(WrMem), .B1(n_0_221), .B2(n_9), .ZN(n_0_217) + ); + INV_X1_LVT i_0_313( + .A(n_0_217), .ZN(DAddr[9]) + ); + AOI22_X1_LVT i_0_312( + .A1(n_0_23), .A2(WrMem), .B1(n_0_221), .B2(n_8), .ZN(n_0_216) + ); + INV_X1_LVT i_0_311( + .A(n_0_216), .ZN(DAddr[8]) + ); + AOI22_X1_LVT i_0_310( + .A1(n_0_22), .A2(WrMem), .B1(n_0_221), .B2(n_7), .ZN(n_0_215) + ); + INV_X1_LVT i_0_309( + .A(n_0_215), .ZN(DAddr[7]) + ); + AOI22_X1_LVT i_0_308( + .A1(n_0_21), .A2(WrMem), .B1(n_0_221), .B2(n_6), .ZN(n_0_214) + ); + INV_X1_LVT i_0_307( + .A(n_0_214), .ZN(DAddr[6]) + ); + AOI22_X1_LVT i_0_306( + .A1(n_0_20), .A2(WrMem), .B1(n_0_221), .B2(n_5), .ZN(n_0_213) + ); + INV_X1_LVT i_0_305( + .A(n_0_213), .ZN(DAddr[5]) + ); + AOI22_X1_LVT i_0_304( + .A1(n_0_19), .A2(WrMem), .B1(n_0_221), .B2(n_4), .ZN(n_0_212) + ); + INV_X1_LVT i_0_303( + .A(n_0_212), .ZN(DAddr[4]) + ); + AOI22_X1_LVT i_0_302( + .A1(n_0_18), .A2(WrMem), .B1(n_0_221), .B2(n_3), .ZN(n_0_211) + ); + INV_X1_LVT i_0_301( + .A(n_0_211), .ZN(DAddr[3]) + ); + AOI22_X1_LVT i_0_300( + .A1(n_0_17), .A2(WrMem), .B1(n_0_221), .B2(n_2), .ZN(n_0_210) + ); + INV_X1_LVT i_0_299( + .A(n_0_210), .ZN(DAddr[2]) + ); + AOI22_X1_LVT i_0_298( + .A1(n_0_16), .A2(WrMem), .B1(n_0_221), .B2(n_1), .ZN(n_0_209) + ); + INV_X1_LVT i_0_297( + .A(n_0_209), .ZN(DAddr[1]) + ); + AOI22_X1_LVT i_0_296( + .A1(n_0_15), .A2(WrMem), .B1(n_0_221), .B2(n_0), .ZN(n_0_208) + ); + INV_X1_LVT i_0_295( + .A(n_0_208), .ZN(DAddr[0]) + ); + OR2_X1_LVT i_0_324( + .A1(n_0_222), .A2(Instruction[13]), .ZN(DWidth[1]) + ); + NOR2_X1_LVT i_0_323( + .A1(n_0_246), .A2(n_0_222), .ZN(DWidth[0]) + ); + NAND3_X1_LVT i_0_331( + .A1(n_0_248), .A2(n_0_244), .A3(n_0_236), .ZN(n_0_227) + ); + OAI211_X1_LVT i_0_326( + .A(n_0_249), .B(n_0_223), .C1(n_0_228), .C2(n_0_227), .ZN(WrReg) + ); +endmodule + +module MemGen_32_11(chip_en, clock, addr, rd_data, rd_en, wr_en, wr_data); + input [31:0] wr_data; + input [10:0] addr; + input chip_en, clock, rd_en, wr_en; + output [31:0] rd_data; + + wire [1:0] mem_sel; + wire n_63, n_62, n_61, n_60, n_59, n_58, n_57, n_56, n_55, n_54, n_53, n_52, + n_51, n_50, n_49, n_48, n_31, n_30, n_29, n_28, n_27, n_26, n_25, n_24, + n_23, n_22, n_21, n_20, n_19, n_18, n_17, n_16, n_47, n_46, n_45, n_44, + n_43, n_42, n_41, n_40, n_39, n_38, n_37, n_36, n_35, n_34, n_33, n_32, + n_15, n_14, n_13, n_12, n_11, n_10, n_9, n_8, n_7, n_6, n_5, n_4, n_3, + n_2, n_1, n_0; + + INV_X1_LVT i_1_3( + .A(addr[10]), .ZN(mem_sel[0]) + ); + MemGen_16_10 genblk1_0_U_hi( + .chip_en(mem_sel[0]), .wr_en(wr_en), .addr({addr[9], addr[8], addr[7], + addr[6], addr[5], addr[4], addr[3], addr[2], addr[1], addr[0]}), .wr_data({ + wr_data[31], wr_data[30], wr_data[29], wr_data[28], wr_data[27], + wr_data[26], wr_data[25], wr_data[24], wr_data[23], wr_data[22], + wr_data[21], wr_data[20], wr_data[19], wr_data[18], wr_data[17], + wr_data[16]}), .clock(clock), .rd_en(rd_en), .rd_data({n_63, n_62, n_61, + n_60, n_59, n_58, n_57, n_56, n_55, n_54, n_53, n_52, n_51, n_50, n_49, + n_48}) + ); + MemGen_16_10 genblk1_1_U_hi( + .chip_en(addr[10]), .wr_en(wr_en), .addr({addr[9], addr[8], addr[7], + addr[6], addr[5], addr[4], addr[3], addr[2], addr[1], addr[0]}), .wr_data({ + wr_data[31], wr_data[30], wr_data[29], wr_data[28], wr_data[27], + wr_data[26], wr_data[25], wr_data[24], wr_data[23], wr_data[22], + wr_data[21], wr_data[20], wr_data[19], wr_data[18], wr_data[17], + wr_data[16]}), .clock(clock), .rd_en(rd_en), .rd_data({n_31, n_30, n_29, + n_28, n_27, n_26, n_25, n_24, n_23, n_22, n_21, n_20, n_19, n_18, n_17, + n_16}) + ); + MUX2_X1_LVT i_1_1_31( + .A(n_63), .B(n_31), .S(addr[10]), .Z(rd_data[31]) + ); + MUX2_X1_LVT i_1_1_30( + .A(n_62), .B(n_30), .S(addr[10]), .Z(rd_data[30]) + ); + MUX2_X1_LVT i_1_1_29( + .A(n_61), .B(n_29), .S(addr[10]), .Z(rd_data[29]) + ); + MUX2_X1_LVT i_1_1_28( + .A(n_60), .B(n_28), .S(addr[10]), .Z(rd_data[28]) + ); + MUX2_X1_LVT i_1_1_27( + .A(n_59), .B(n_27), .S(addr[10]), .Z(rd_data[27]) + ); + MUX2_X1_LVT i_1_1_26( + .A(n_58), .B(n_26), .S(addr[10]), .Z(rd_data[26]) + ); + MUX2_X1_LVT i_1_1_25( + .A(n_57), .B(n_25), .S(addr[10]), .Z(rd_data[25]) + ); + MUX2_X1_LVT i_1_1_24( + .A(n_56), .B(n_24), .S(addr[10]), .Z(rd_data[24]) + ); + MUX2_X1_LVT i_1_1_23( + .A(n_55), .B(n_23), .S(addr[10]), .Z(rd_data[23]) + ); + MUX2_X1_LVT i_1_1_22( + .A(n_54), .B(n_22), .S(addr[10]), .Z(rd_data[22]) + ); + MUX2_X1_LVT i_1_1_21( + .A(n_53), .B(n_21), .S(addr[10]), .Z(rd_data[21]) + ); + MUX2_X1_LVT i_1_1_20( + .A(n_52), .B(n_20), .S(addr[10]), .Z(rd_data[20]) + ); + MUX2_X1_LVT i_1_1_19( + .A(n_51), .B(n_19), .S(addr[10]), .Z(rd_data[19]) + ); + MUX2_X1_LVT i_1_1_18( + .A(n_50), .B(n_18), .S(addr[10]), .Z(rd_data[18]) + ); + MUX2_X1_LVT i_1_1_17( + .A(n_49), .B(n_17), .S(addr[10]), .Z(rd_data[17]) + ); + MUX2_X1_LVT i_1_1_16( + .A(n_48), .B(n_16), .S(addr[10]), .Z(rd_data[16]) + ); + MemGen_16_10 genblk1_0_U_lo( + .chip_en(mem_sel[0]), .wr_en(wr_en), .addr({addr[9], addr[8], addr[7], + addr[6], addr[5], addr[4], addr[3], addr[2], addr[1], addr[0]}), .wr_data({ + wr_data[15], wr_data[14], wr_data[13], wr_data[12], wr_data[11], + wr_data[10], wr_data[9], wr_data[8], wr_data[7], wr_data[6], wr_data[5], + wr_data[4], wr_data[3], wr_data[2], wr_data[1], wr_data[0]}), .clock(clock), + .rd_en(rd_en), .rd_data({n_47, n_46, n_45, n_44, n_43, n_42, n_41, + n_40, n_39, n_38, n_37, n_36, n_35, n_34, n_33, n_32}) + ); + MemGen_16_10 genblk1_1_U_lo( + .chip_en(addr[10]), .wr_en(wr_en), .addr({addr[9], addr[8], addr[7], + addr[6], addr[5], addr[4], addr[3], addr[2], addr[1], addr[0]}), .wr_data({ + wr_data[15], wr_data[14], wr_data[13], wr_data[12], wr_data[11], + wr_data[10], wr_data[9], wr_data[8], wr_data[7], wr_data[6], wr_data[5], + wr_data[4], wr_data[3], wr_data[2], wr_data[1], wr_data[0]}), .clock(clock), + .rd_en(rd_en), .rd_data({n_15, n_14, n_13, n_12, n_11, n_10, n_9, n_8, + n_7, n_6, n_5, n_4, n_3, n_2, n_1, n_0}) + ); + MUX2_X1_LVT i_1_1_15( + .A(n_47), .B(n_15), .S(addr[10]), .Z(rd_data[15]) + ); + MUX2_X1_LVT i_1_1_14( + .A(n_46), .B(n_14), .S(addr[10]), .Z(rd_data[14]) + ); + MUX2_X1_LVT i_1_1_13( + .A(n_45), .B(n_13), .S(addr[10]), .Z(rd_data[13]) + ); + MUX2_X1_LVT i_1_1_12( + .A(n_44), .B(n_12), .S(addr[10]), .Z(rd_data[12]) + ); + MUX2_X1_LVT i_1_1_11( + .A(n_43), .B(n_11), .S(addr[10]), .Z(rd_data[11]) + ); + MUX2_X1_LVT i_1_1_10( + .A(n_42), .B(n_10), .S(addr[10]), .Z(rd_data[10]) + ); + MUX2_X1_LVT i_1_1_9( + .A(n_41), .B(n_9), .S(addr[10]), .Z(rd_data[9]) + ); + MUX2_X1_LVT i_1_1_8( + .A(n_40), .B(n_8), .S(addr[10]), .Z(rd_data[8]) + ); + MUX2_X1_LVT i_1_1_7( + .A(n_39), .B(n_7), .S(addr[10]), .Z(rd_data[7]) + ); + MUX2_X1_LVT i_1_1_6( + .A(n_38), .B(n_6), .S(addr[10]), .Z(rd_data[6]) + ); + MUX2_X1_LVT i_1_1_5( + .A(n_37), .B(n_5), .S(addr[10]), .Z(rd_data[5]) + ); + MUX2_X1_LVT i_1_1_4( + .A(n_36), .B(n_4), .S(addr[10]), .Z(rd_data[4]) + ); + MUX2_X1_LVT i_1_1_3( + .A(n_35), .B(n_3), .S(addr[10]), .Z(rd_data[3]) + ); + MUX2_X1_LVT i_1_1_2( + .A(n_34), .B(n_2), .S(addr[10]), .Z(rd_data[2]) + ); + MUX2_X1_LVT i_1_1_1( + .A(n_33), .B(n_1), .S(addr[10]), .Z(rd_data[1]) + ); + MUX2_X1_LVT i_1_1_0( + .A(n_32), .B(n_0), .S(addr[10]), .Z(rd_data[0]) + ); +endmodule + +module main_mem(clk, reset, DAddr, IAddr, DWData, DRData, IRData, DWE, DWidth); + input [31:0] DAddr, IAddr, DWData; + input [1:0] DWidth; + input clk, reset, DWE; + output [31:0] DRData, IRData; + + wire [31:0] mem_rdata, drTmp, mem_wdata; + wire [10:0] mem_addr; + wire n_0_0, n_0_0_0, n_0_1, n_0_0_1, n_0_2, n_0_0_2, n_0_3, n_0_0_3, n_0_4, + n_0_0_4, n_0_5, n_0_0_5, n_0_6, n_0_0_6, n_0_7, n_0_0_7, n_0_8, n_0_0_8, + n_0_9, n_0_0_9, n_0_10, n_0_0_10, n_0_0_11, n_0_11, n_0_0_12, n_0_0_13, + n_0_12, n_0_0_14, n_0_0_15, n_0_13, n_0_0_16, n_0_0_17, n_0_14, + n_0_0_18, n_0_0_19, n_0_15, n_0_0_20, n_0_0_21, n_0_16, n_0_0_22, + n_0_0_23, n_0_17, n_0_0_24, n_0_0_25, n_0_18, n_0_0_26, n_0_0_27, + n_0_0_28, n_0_19, n_0_0_29, n_0_20, n_0_0_30, n_0_21, n_0_0_31, n_0_22, + n_0_0_32, n_0_23, n_0_0_33, n_0_24, n_0_0_34, n_0_25, n_0_0_35, n_0_26, + n_0_0_36, n_0_0_37, n_0_27, n_0_28, n_0_29, n_0_30, n_0_31, n_0_32, + n_0_33, n_0_34, n_0_35, n_0_36, n_0_37, n_0_38, n_0_39, n_0_40, n_0_41, + n_0_42, n_0_65, n_0_64, n_0_63, n_0_62, n_0_61, n_0_60, n_0_59, n_0_58, + n_0_0_38, n_0_0_39, n_0_57, n_0_0_40, n_0_56, n_0_0_41, n_0_55, + n_0_0_42, n_0_54, n_0_0_43, n_0_53, n_0_0_44, n_0_52, n_0_0_45, n_0_51, + n_0_0_46, n_0_50, n_0_0_47, n_0_0_48, n_0_0_49, n_0_0_50, n_0_0_51, + n_0_49, n_0_0_52, n_0_48, n_0_0_53, n_0_47, n_0_0_54, n_0_46, n_0_0_55, + n_0_45, n_0_0_56, n_0_44, n_0_0_57, n_0_66, n_0_0_58, n_0_67, n_0_0_59, + n_0_0_60, n_0_0_61, n_0_68, n_0_0_62, n_0_0_63, n_0_69, n_0_0_64, + n_0_0_65, n_0_70, n_0_0_66, n_0_0_67, n_0_71, n_0_0_68, n_0_0_69, + n_0_72, n_0_0_70, n_0_0_71, n_0_73, n_0_0_72, n_0_0_73, n_0_74, + n_0_0_74, n_0_0_75, n_0_75, n_0_0_76, n_0_0_77, n_0_0_78, n_0_0_79, + n_0_0_80, n_0_0_81, n_0_0_82, n_0_0_83, n_0_0_84, n_0_0_85, n_0_0_86, + n_0_0_87, n_0_0_88, n_0_0_89, n_0_0_90, n_0_0_91, n_0_0_92, n_0_43, + n_0_0_93, n_0_0_94, n_0_76, n_0_0_95, n_0; + + INV_X1_LVT i_0_0_171( + .A(DWE), .ZN(n_0) + ); + NOR2_X1_LVT i_0_0_163( + .A1(n_0), .A2(reset), .ZN(n_0_0_88) + ); + NOR2_X1_LVT i_0_0_22( + .A1(DWE), .A2(reset), .ZN(n_0_0_11) + ); + AOI22_X1_LVT i_0_0_21( + .A1(DAddr[12]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[12]), .ZN(n_0_0_10) + ); + INV_X1_LVT i_0_0_20( + .A(n_0_0_10), .ZN(n_0_10) + ); + INV_X1_LVT i_0_0_172( + .A(clk), .ZN(n_0_76) + ); + DFF_X1_LVT \mem_addr_reg[10] ( + .CK(n_0_76), .D(n_0_10), .Q(mem_addr[10]), .QN() + ); + AOI22_X1_LVT i_0_0_19( + .A1(DAddr[11]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[11]), .ZN(n_0_0_9) + ); + INV_X1_LVT i_0_0_18( + .A(n_0_0_9), .ZN(n_0_9) + ); + DFF_X1_LVT \mem_addr_reg[9] ( + .CK(n_0_76), .D(n_0_9), .Q(mem_addr[9]), .QN() + ); + AOI22_X1_LVT i_0_0_17( + .A1(DAddr[10]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[10]), .ZN(n_0_0_8) + ); + INV_X1_LVT i_0_0_16( + .A(n_0_0_8), .ZN(n_0_8) + ); + DFF_X1_LVT \mem_addr_reg[8] ( + .CK(n_0_76), .D(n_0_8), .Q(mem_addr[8]), .QN() + ); + AOI22_X1_LVT i_0_0_15( + .A1(DAddr[9]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[9]), .ZN(n_0_0_7) + ); + INV_X1_LVT i_0_0_14( + .A(n_0_0_7), .ZN(n_0_7) + ); + DFF_X1_LVT \mem_addr_reg[7] ( + .CK(n_0_76), .D(n_0_7), .Q(mem_addr[7]), .QN() + ); + AOI22_X1_LVT i_0_0_13( + .A1(DAddr[8]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[8]), .ZN(n_0_0_6) + ); + INV_X1_LVT i_0_0_12( + .A(n_0_0_6), .ZN(n_0_6) + ); + DFF_X1_LVT \mem_addr_reg[6] ( + .CK(n_0_76), .D(n_0_6), .Q(mem_addr[6]), .QN() + ); + AOI22_X1_LVT i_0_0_11( + .A1(DAddr[7]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[7]), .ZN(n_0_0_5) + ); + INV_X1_LVT i_0_0_10( + .A(n_0_0_5), .ZN(n_0_5) + ); + DFF_X1_LVT \mem_addr_reg[5] ( + .CK(n_0_76), .D(n_0_5), .Q(mem_addr[5]), .QN() + ); + AOI22_X1_LVT i_0_0_9( + .A1(DAddr[6]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[6]), .ZN(n_0_0_4) + ); + INV_X1_LVT i_0_0_8( + .A(n_0_0_4), .ZN(n_0_4) + ); + DFF_X1_LVT \mem_addr_reg[4] ( + .CK(n_0_76), .D(n_0_4), .Q(mem_addr[4]), .QN() + ); + AOI22_X1_LVT i_0_0_7( + .A1(DAddr[5]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[5]), .ZN(n_0_0_3) + ); + INV_X1_LVT i_0_0_6( + .A(n_0_0_3), .ZN(n_0_3) + ); + DFF_X1_LVT \mem_addr_reg[3] ( + .CK(n_0_76), .D(n_0_3), .Q(mem_addr[3]), .QN() + ); + AOI22_X1_LVT i_0_0_5( + .A1(DAddr[4]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[4]), .ZN(n_0_0_2) + ); + INV_X1_LVT i_0_0_4( + .A(n_0_0_2), .ZN(n_0_2) + ); + DFF_X1_LVT \mem_addr_reg[2] ( + .CK(n_0_76), .D(n_0_2), .Q(mem_addr[2]), .QN() + ); + AOI22_X1_LVT i_0_0_3( + .A1(DAddr[3]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[3]), .ZN(n_0_0_1) + ); + INV_X1_LVT i_0_0_2( + .A(n_0_0_1), .ZN(n_0_1) + ); + DFF_X1_LVT \mem_addr_reg[1] ( + .CK(n_0_76), .D(n_0_1), .Q(mem_addr[1]), .QN() + ); + AOI22_X1_LVT i_0_0_1( + .A1(DAddr[2]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[2]), .ZN(n_0_0_0) + ); + INV_X1_LVT i_0_0_0( + .A(n_0_0_0), .ZN(n_0_0) + ); + DFF_X1_LVT \mem_addr_reg[0] ( + .CK(n_0_76), .D(n_0_0), .Q(mem_addr[0]), .QN() + ); + NOR2_X1_LVT i_0_0_162( + .A1(DWidth[1]), .A2(DAddr[1]), .ZN(n_0_0_87) + ); + NOR2_X1_LVT i_0_0_158( + .A1(DWidth[0]), .A2(DAddr[0]), .ZN(n_0_0_83) + ); + AND2_X1_LVT i_0_0_157( + .A1(n_0_0_87), .A2(n_0_0_83), .ZN(n_0_0_82) + ); + AND2_X1_LVT i_0_0_156( + .A1(n_0_0_88), .A2(n_0_0_82), .ZN(n_0_0_81) + ); + INV_X1_LVT i_0_0_173( + .A(n_0_0_88), .ZN(n_0_0_95) + ); + INV_X1_LVT i_0_0_169( + .A(DWidth[1]), .ZN(n_0_0_93) + ); + NOR3_X1_LVT i_0_0_155( + .A1(n_0_0_95), .A2(DWidth[0]), .A3(n_0_0_93), .ZN(n_0_0_80) + ); + AOI22_X1_LVT i_0_0_154( + .A1(DWData[7]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[31]), .ZN(n_0_0_79) + ); + NAND2_X1_LVT i_0_0_168( + .A1(DWidth[0]), .A2(DWidth[1]), .ZN(n_0_43) + ); + INV_X1_LVT i_0_0_167( + .A(n_0_43), .ZN(n_0_0_92) + ); + NOR2_X1_LVT i_0_0_160( + .A1(n_0_0_95), .A2(n_0_0_92), .ZN(n_0_0_85) + ); + NAND2_X1_LVT i_0_0_161( + .A1(n_0_0_93), .A2(DAddr[1]), .ZN(n_0_0_86) + ); + NOR2_X1_LVT i_0_0_166( + .A1(DWidth[0]), .A2(DWidth[1]), .ZN(n_0_0_91) + ); + NAND2_X1_LVT i_0_0_164( + .A1(DAddr[0]), .A2(n_0_0_91), .ZN(n_0_0_89) + ); + NAND3_X1_LVT i_0_0_159( + .A1(n_0_0_85), .A2(n_0_0_86), .A3(n_0_0_89), .ZN(n_0_0_84) + ); + INV_X1_LVT i_0_0_170( + .A(DWidth[0]), .ZN(n_0_0_94) + ); + NOR2_X1_LVT i_0_0_153( + .A1(n_0_0_94), .A2(DAddr[1]), .ZN(n_0_0_78) + ); + AND3_X1_LVT i_0_0_152( + .A1(n_0_0_88), .A2(n_0_0_78), .A3(n_0_0_93), .ZN(n_0_0_77) + ); + AOI22_X1_LVT i_0_0_151( + .A1(n_0_0_84), .A2(mem_wdata[31]), .B1(DWData[15]), .B2(n_0_0_77), .ZN(n_0_0_76) + ); + NAND2_X1_LVT i_0_0_150( + .A1(n_0_0_79), .A2(n_0_0_76), .ZN(n_0_75) + ); + DFF_X1_LVT \mem_wdata_reg[31] ( + .CK(n_0_76), .D(n_0_75), .Q(mem_wdata[31]), .QN() + ); + AOI22_X1_LVT i_0_0_149( + .A1(DWData[6]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[30]), .ZN(n_0_0_75) + ); + AOI22_X1_LVT i_0_0_148( + .A1(n_0_0_84), .A2(mem_wdata[30]), .B1(DWData[14]), .B2(n_0_0_77), .ZN(n_0_0_74) + ); + NAND2_X1_LVT i_0_0_147( + .A1(n_0_0_75), .A2(n_0_0_74), .ZN(n_0_74) + ); + DFF_X1_LVT \mem_wdata_reg[30] ( + .CK(n_0_76), .D(n_0_74), .Q(mem_wdata[30]), .QN() + ); + AOI22_X1_LVT i_0_0_146( + .A1(DWData[5]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[29]), .ZN(n_0_0_73) + ); + AOI22_X1_LVT i_0_0_145( + .A1(n_0_0_84), .A2(mem_wdata[29]), .B1(DWData[13]), .B2(n_0_0_77), .ZN(n_0_0_72) + ); + NAND2_X1_LVT i_0_0_144( + .A1(n_0_0_73), .A2(n_0_0_72), .ZN(n_0_73) + ); + DFF_X1_LVT \mem_wdata_reg[29] ( + .CK(n_0_76), .D(n_0_73), .Q(mem_wdata[29]), .QN() + ); + AOI22_X1_LVT i_0_0_143( + .A1(DWData[4]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[28]), .ZN(n_0_0_71) + ); + AOI22_X1_LVT i_0_0_142( + .A1(n_0_0_84), .A2(mem_wdata[28]), .B1(DWData[12]), .B2(n_0_0_77), .ZN(n_0_0_70) + ); + NAND2_X1_LVT i_0_0_141( + .A1(n_0_0_71), .A2(n_0_0_70), .ZN(n_0_72) + ); + DFF_X1_LVT \mem_wdata_reg[28] ( + .CK(n_0_76), .D(n_0_72), .Q(mem_wdata[28]), .QN() + ); + AOI22_X1_LVT i_0_0_140( + .A1(DWData[3]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[27]), .ZN(n_0_0_69) + ); + AOI22_X1_LVT i_0_0_139( + .A1(n_0_0_84), .A2(mem_wdata[27]), .B1(DWData[11]), .B2(n_0_0_77), .ZN(n_0_0_68) + ); + NAND2_X1_LVT i_0_0_138( + .A1(n_0_0_69), .A2(n_0_0_68), .ZN(n_0_71) + ); + DFF_X1_LVT \mem_wdata_reg[27] ( + .CK(n_0_76), .D(n_0_71), .Q(mem_wdata[27]), .QN() + ); + AOI22_X1_LVT i_0_0_137( + .A1(DWData[2]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[26]), .ZN(n_0_0_67) + ); + AOI22_X1_LVT i_0_0_136( + .A1(n_0_0_84), .A2(mem_wdata[26]), .B1(DWData[10]), .B2(n_0_0_77), .ZN(n_0_0_66) + ); + NAND2_X1_LVT i_0_0_135( + .A1(n_0_0_67), .A2(n_0_0_66), .ZN(n_0_70) + ); + DFF_X1_LVT \mem_wdata_reg[26] ( + .CK(n_0_76), .D(n_0_70), .Q(mem_wdata[26]), .QN() + ); + AOI22_X1_LVT i_0_0_134( + .A1(DWData[1]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[25]), .ZN(n_0_0_65) + ); + AOI22_X1_LVT i_0_0_133( + .A1(n_0_0_84), .A2(mem_wdata[25]), .B1(DWData[9]), .B2(n_0_0_77), .ZN(n_0_0_64) + ); + NAND2_X1_LVT i_0_0_132( + .A1(n_0_0_65), .A2(n_0_0_64), .ZN(n_0_69) + ); + DFF_X1_LVT \mem_wdata_reg[25] ( + .CK(n_0_76), .D(n_0_69), .Q(mem_wdata[25]), .QN() + ); + AOI22_X1_LVT i_0_0_131( + .A1(DWData[0]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[24]), .ZN(n_0_0_63) + ); + AOI22_X1_LVT i_0_0_130( + .A1(n_0_0_84), .A2(mem_wdata[24]), .B1(DWData[8]), .B2(n_0_0_77), .ZN(n_0_0_62) + ); + NAND2_X1_LVT i_0_0_129( + .A1(n_0_0_63), .A2(n_0_0_62), .ZN(n_0_68) + ); + DFF_X1_LVT \mem_wdata_reg[24] ( + .CK(n_0_76), .D(n_0_68), .Q(mem_wdata[24]), .QN() + ); + NOR4_X1_LVT i_0_0_127( + .A1(n_0_0_95), .A2(n_0_0_83), .A3(DWidth[1]), .A4(DAddr[1]), .ZN(n_0_0_60) + ); + INV_X1_LVT i_0_0_165( + .A(n_0_0_91), .ZN(n_0_0_90) + ); + OAI211_X1_LVT i_0_0_128( + .A(n_0_0_85), .B(n_0_0_86), .C1(n_0_0_90), .C2(DAddr[0]), .ZN(n_0_0_61) + ); + AOI222_X1_LVT i_0_0_126( + .A1(DWData[7]), .A2(n_0_0_60), .B1(mem_wdata[23]), .B2(n_0_0_61), .C1(DWData[23]), + .C2(n_0_0_80), .ZN(n_0_0_59) + ); + INV_X1_LVT i_0_0_125( + .A(n_0_0_59), .ZN(n_0_67) + ); + DFF_X1_LVT \mem_wdata_reg[23] ( + .CK(n_0_76), .D(n_0_67), .Q(mem_wdata[23]), .QN() + ); + AOI222_X1_LVT i_0_0_124( + .A1(DWData[6]), .A2(n_0_0_60), .B1(mem_wdata[22]), .B2(n_0_0_61), .C1(DWData[22]), + .C2(n_0_0_80), .ZN(n_0_0_58) + ); + INV_X1_LVT i_0_0_123( + .A(n_0_0_58), .ZN(n_0_66) + ); + DFF_X1_LVT \mem_wdata_reg[22] ( + .CK(n_0_76), .D(n_0_66), .Q(mem_wdata[22]), .QN() + ); + AOI222_X1_LVT i_0_0_122( + .A1(DWData[5]), .A2(n_0_0_60), .B1(mem_wdata[21]), .B2(n_0_0_61), .C1(DWData[21]), + .C2(n_0_0_80), .ZN(n_0_0_57) + ); + INV_X1_LVT i_0_0_121( + .A(n_0_0_57), .ZN(n_0_44) + ); + DFF_X1_LVT \mem_wdata_reg[21] ( + .CK(n_0_76), .D(n_0_44), .Q(mem_wdata[21]), .QN() + ); + AOI222_X1_LVT i_0_0_120( + .A1(DWData[4]), .A2(n_0_0_60), .B1(mem_wdata[20]), .B2(n_0_0_61), .C1(DWData[20]), + .C2(n_0_0_80), .ZN(n_0_0_56) + ); + INV_X1_LVT i_0_0_119( + .A(n_0_0_56), .ZN(n_0_45) + ); + DFF_X1_LVT \mem_wdata_reg[20] ( + .CK(n_0_76), .D(n_0_45), .Q(mem_wdata[20]), .QN() + ); + AOI222_X1_LVT i_0_0_118( + .A1(DWData[3]), .A2(n_0_0_60), .B1(mem_wdata[19]), .B2(n_0_0_61), .C1(DWData[19]), + .C2(n_0_0_80), .ZN(n_0_0_55) + ); + INV_X1_LVT i_0_0_117( + .A(n_0_0_55), .ZN(n_0_46) + ); + DFF_X1_LVT \mem_wdata_reg[19] ( + .CK(n_0_76), .D(n_0_46), .Q(mem_wdata[19]), .QN() + ); + AOI222_X1_LVT i_0_0_116( + .A1(DWData[2]), .A2(n_0_0_60), .B1(mem_wdata[18]), .B2(n_0_0_61), .C1(DWData[18]), + .C2(n_0_0_80), .ZN(n_0_0_54) + ); + INV_X1_LVT i_0_0_115( + .A(n_0_0_54), .ZN(n_0_47) + ); + DFF_X1_LVT \mem_wdata_reg[18] ( + .CK(n_0_76), .D(n_0_47), .Q(mem_wdata[18]), .QN() + ); + AOI222_X1_LVT i_0_0_114( + .A1(DWData[1]), .A2(n_0_0_60), .B1(mem_wdata[17]), .B2(n_0_0_61), .C1(DWData[17]), + .C2(n_0_0_80), .ZN(n_0_0_53) + ); + INV_X1_LVT i_0_0_113( + .A(n_0_0_53), .ZN(n_0_48) + ); + DFF_X1_LVT \mem_wdata_reg[17] ( + .CK(n_0_76), .D(n_0_48), .Q(mem_wdata[17]), .QN() + ); + AOI222_X1_LVT i_0_0_112( + .A1(DWData[0]), .A2(n_0_0_60), .B1(mem_wdata[16]), .B2(n_0_0_61), .C1(DWData[16]), + .C2(n_0_0_80), .ZN(n_0_0_52) + ); + INV_X1_LVT i_0_0_111( + .A(n_0_0_52), .ZN(n_0_49) + ); + DFF_X1_LVT \mem_wdata_reg[16] ( + .CK(n_0_76), .D(n_0_49), .Q(mem_wdata[16]), .QN() + ); + NOR4_X1_LVT i_0_0_110( + .A1(n_0_0_95), .A2(n_0_0_87), .A3(n_0_0_92), .A4(n_0_0_91), .ZN(n_0_0_51) + ); + NOR3_X1_LVT i_0_0_109( + .A1(n_0_0_86), .A2(DAddr[0]), .A3(DWidth[0]), .ZN(n_0_0_50) + ); + AND2_X1_LVT i_0_0_108( + .A1(n_0_0_88), .A2(n_0_0_50), .ZN(n_0_0_49) + ); + OAI211_X1_LVT i_0_0_107( + .A(n_0_0_85), .B(n_0_0_89), .C1(DAddr[1]), .C2(DWidth[1]), .ZN(n_0_0_48) + ); + AOI222_X1_LVT i_0_0_106( + .A1(DWData[15]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[7]), .C1(n_0_0_48), + .C2(mem_wdata[15]), .ZN(n_0_0_47) + ); + INV_X1_LVT i_0_0_105( + .A(n_0_0_47), .ZN(n_0_50) + ); + DFF_X1_LVT \mem_wdata_reg[15] ( + .CK(n_0_76), .D(n_0_50), .Q(mem_wdata[15]), .QN() + ); + AOI222_X1_LVT i_0_0_104( + .A1(DWData[14]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[6]), .C1(n_0_0_48), + .C2(mem_wdata[14]), .ZN(n_0_0_46) + ); + INV_X1_LVT i_0_0_103( + .A(n_0_0_46), .ZN(n_0_51) + ); + DFF_X1_LVT \mem_wdata_reg[14] ( + .CK(n_0_76), .D(n_0_51), .Q(mem_wdata[14]), .QN() + ); + AOI222_X1_LVT i_0_0_102( + .A1(DWData[13]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[5]), .C1(n_0_0_48), + .C2(mem_wdata[13]), .ZN(n_0_0_45) + ); + INV_X1_LVT i_0_0_101( + .A(n_0_0_45), .ZN(n_0_52) + ); + DFF_X1_LVT \mem_wdata_reg[13] ( + .CK(n_0_76), .D(n_0_52), .Q(mem_wdata[13]), .QN() + ); + AOI222_X1_LVT i_0_0_100( + .A1(DWData[12]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[4]), .C1(n_0_0_48), + .C2(mem_wdata[12]), .ZN(n_0_0_44) + ); + INV_X1_LVT i_0_0_99( + .A(n_0_0_44), .ZN(n_0_53) + ); + DFF_X1_LVT \mem_wdata_reg[12] ( + .CK(n_0_76), .D(n_0_53), .Q(mem_wdata[12]), .QN() + ); + AOI222_X1_LVT i_0_0_98( + .A1(DWData[11]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[3]), .C1(n_0_0_48), + .C2(mem_wdata[11]), .ZN(n_0_0_43) + ); + INV_X1_LVT i_0_0_97( + .A(n_0_0_43), .ZN(n_0_54) + ); + DFF_X1_LVT \mem_wdata_reg[11] ( + .CK(n_0_76), .D(n_0_54), .Q(mem_wdata[11]), .QN() + ); + AOI222_X1_LVT i_0_0_96( + .A1(DWData[10]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[2]), .C1(n_0_0_48), + .C2(mem_wdata[10]), .ZN(n_0_0_42) + ); + INV_X1_LVT i_0_0_95( + .A(n_0_0_42), .ZN(n_0_55) + ); + DFF_X1_LVT \mem_wdata_reg[10] ( + .CK(n_0_76), .D(n_0_55), .Q(mem_wdata[10]), .QN() + ); + AOI222_X1_LVT i_0_0_94( + .A1(DWData[9]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[1]), .C1(n_0_0_48), + .C2(mem_wdata[9]), .ZN(n_0_0_41) + ); + INV_X1_LVT i_0_0_93( + .A(n_0_0_41), .ZN(n_0_56) + ); + DFF_X1_LVT \mem_wdata_reg[9] ( + .CK(n_0_76), .D(n_0_56), .Q(mem_wdata[9]), .QN() + ); + AOI222_X1_LVT i_0_0_92( + .A1(DWData[8]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[0]), .C1(n_0_0_48), + .C2(mem_wdata[8]), .ZN(n_0_0_40) + ); + INV_X1_LVT i_0_0_91( + .A(n_0_0_40), .ZN(n_0_57) + ); + DFF_X1_LVT \mem_wdata_reg[8] ( + .CK(n_0_76), .D(n_0_57), .Q(mem_wdata[8]), .QN() + ); + AOI21_X1_LVT i_0_0_90( + .A(n_0_0_87), .B1(n_0_0_83), .B2(n_0_0_93), .ZN(n_0_0_39) + ); + NAND2_X1_LVT i_0_0_89( + .A1(n_0_0_85), .A2(n_0_0_39), .ZN(n_0_0_38) + ); + MUX2_X1_LVT i_0_0_88( + .A(DWData[7]), .B(mem_wdata[7]), .S(n_0_0_38), .Z(n_0_58) + ); + DFF_X1_LVT \mem_wdata_reg[7] ( + .CK(n_0_76), .D(n_0_58), .Q(mem_wdata[7]), .QN() + ); + MUX2_X1_LVT i_0_0_87( + .A(DWData[6]), .B(mem_wdata[6]), .S(n_0_0_38), .Z(n_0_59) + ); + DFF_X1_LVT \mem_wdata_reg[6] ( + .CK(n_0_76), .D(n_0_59), .Q(mem_wdata[6]), .QN() + ); + MUX2_X1_LVT i_0_0_86( + .A(DWData[5]), .B(mem_wdata[5]), .S(n_0_0_38), .Z(n_0_60) + ); + DFF_X1_LVT \mem_wdata_reg[5] ( + .CK(n_0_76), .D(n_0_60), .Q(mem_wdata[5]), .QN() + ); + MUX2_X1_LVT i_0_0_85( + .A(DWData[4]), .B(mem_wdata[4]), .S(n_0_0_38), .Z(n_0_61) + ); + DFF_X1_LVT \mem_wdata_reg[4] ( + .CK(n_0_76), .D(n_0_61), .Q(mem_wdata[4]), .QN() + ); + MUX2_X1_LVT i_0_0_84( + .A(DWData[3]), .B(mem_wdata[3]), .S(n_0_0_38), .Z(n_0_62) + ); + DFF_X1_LVT \mem_wdata_reg[3] ( + .CK(n_0_76), .D(n_0_62), .Q(mem_wdata[3]), .QN() + ); + MUX2_X1_LVT i_0_0_83( + .A(DWData[2]), .B(mem_wdata[2]), .S(n_0_0_38), .Z(n_0_63) + ); + DFF_X1_LVT \mem_wdata_reg[2] ( + .CK(n_0_76), .D(n_0_63), .Q(mem_wdata[2]), .QN() + ); + MUX2_X1_LVT i_0_0_82( + .A(DWData[1]), .B(mem_wdata[1]), .S(n_0_0_38), .Z(n_0_64) + ); + DFF_X1_LVT \mem_wdata_reg[1] ( + .CK(n_0_76), .D(n_0_64), .Q(mem_wdata[1]), .QN() + ); + MUX2_X1_LVT i_0_0_81( + .A(DWData[0]), .B(mem_wdata[0]), .S(n_0_0_38), .Z(n_0_65) + ); + DFF_X1_LVT \mem_wdata_reg[0] ( + .CK(n_0_76), .D(n_0_65), .Q(mem_wdata[0]), .QN() + ); + MemGen_32_11 RAM( + .chip_en(), .clock(clk), .addr(mem_addr), .rd_data(mem_rdata), .rd_en(n_0), + .wr_en(DWE), .wr_data(mem_wdata) + ); + DFF_X1_LVT \drTmp_reg[31] ( + .CK(n_0_76), .D(mem_rdata[31]), .Q(drTmp[31]), .QN() + ); + AND2_X1_LVT i_0_0_80( + .A1(DWidth[1]), .A2(drTmp[31]), .ZN(n_0_42) + ); + DLH_X1_LVT \DRData[31] ( + .D(n_0_42), .G(n_0_43), .Q(DRData[31]) + ); + DFF_X1_LVT \drTmp_reg[30] ( + .CK(n_0_76), .D(mem_rdata[30]), .Q(drTmp[30]), .QN() + ); + AND2_X1_LVT i_0_0_79( + .A1(DWidth[1]), .A2(drTmp[30]), .ZN(n_0_41) + ); + DLH_X1_LVT \DRData[30] ( + .D(n_0_41), .G(n_0_43), .Q(DRData[30]) + ); + DFF_X1_LVT \drTmp_reg[29] ( + .CK(n_0_76), .D(mem_rdata[29]), .Q(drTmp[29]), .QN() + ); + AND2_X1_LVT i_0_0_78( + .A1(DWidth[1]), .A2(drTmp[29]), .ZN(n_0_40) + ); + DLH_X1_LVT \DRData[29] ( + .D(n_0_40), .G(n_0_43), .Q(DRData[29]) + ); + DFF_X1_LVT \drTmp_reg[28] ( + .CK(n_0_76), .D(mem_rdata[28]), .Q(drTmp[28]), .QN() + ); + AND2_X1_LVT i_0_0_77( + .A1(DWidth[1]), .A2(drTmp[28]), .ZN(n_0_39) + ); + DLH_X1_LVT \DRData[28] ( + .D(n_0_39), .G(n_0_43), .Q(DRData[28]) + ); + DFF_X1_LVT \drTmp_reg[27] ( + .CK(n_0_76), .D(mem_rdata[27]), .Q(drTmp[27]), .QN() + ); + AND2_X1_LVT i_0_0_76( + .A1(DWidth[1]), .A2(drTmp[27]), .ZN(n_0_38) + ); + DLH_X1_LVT \DRData[27] ( + .D(n_0_38), .G(n_0_43), .Q(DRData[27]) + ); + DFF_X1_LVT \drTmp_reg[26] ( + .CK(n_0_76), .D(mem_rdata[26]), .Q(drTmp[26]), .QN() + ); + AND2_X1_LVT i_0_0_75( + .A1(DWidth[1]), .A2(drTmp[26]), .ZN(n_0_37) + ); + DLH_X1_LVT \DRData[26] ( + .D(n_0_37), .G(n_0_43), .Q(DRData[26]) + ); + DFF_X1_LVT \drTmp_reg[25] ( + .CK(n_0_76), .D(mem_rdata[25]), .Q(drTmp[25]), .QN() + ); + AND2_X1_LVT i_0_0_74( + .A1(DWidth[1]), .A2(drTmp[25]), .ZN(n_0_36) + ); + DLH_X1_LVT \DRData[25] ( + .D(n_0_36), .G(n_0_43), .Q(DRData[25]) + ); + DFF_X1_LVT \drTmp_reg[24] ( + .CK(n_0_76), .D(mem_rdata[24]), .Q(drTmp[24]), .QN() + ); + AND2_X1_LVT i_0_0_73( + .A1(DWidth[1]), .A2(drTmp[24]), .ZN(n_0_35) + ); + DLH_X1_LVT \DRData[24] ( + .D(n_0_35), .G(n_0_43), .Q(DRData[24]) + ); + DFF_X1_LVT \drTmp_reg[23] ( + .CK(n_0_76), .D(mem_rdata[23]), .Q(drTmp[23]), .QN() + ); + AND2_X1_LVT i_0_0_72( + .A1(DWidth[1]), .A2(drTmp[23]), .ZN(n_0_34) + ); + DLH_X1_LVT \DRData[23] ( + .D(n_0_34), .G(n_0_43), .Q(DRData[23]) + ); + DFF_X1_LVT \drTmp_reg[22] ( + .CK(n_0_76), .D(mem_rdata[22]), .Q(drTmp[22]), .QN() + ); + AND2_X1_LVT i_0_0_71( + .A1(DWidth[1]), .A2(drTmp[22]), .ZN(n_0_33) + ); + DLH_X1_LVT \DRData[22] ( + .D(n_0_33), .G(n_0_43), .Q(DRData[22]) + ); + DFF_X1_LVT \drTmp_reg[21] ( + .CK(n_0_76), .D(mem_rdata[21]), .Q(drTmp[21]), .QN() + ); + AND2_X1_LVT i_0_0_70( + .A1(DWidth[1]), .A2(drTmp[21]), .ZN(n_0_32) + ); + DLH_X1_LVT \DRData[21] ( + .D(n_0_32), .G(n_0_43), .Q(DRData[21]) + ); + DFF_X1_LVT \drTmp_reg[20] ( + .CK(n_0_76), .D(mem_rdata[20]), .Q(drTmp[20]), .QN() + ); + AND2_X1_LVT i_0_0_69( + .A1(DWidth[1]), .A2(drTmp[20]), .ZN(n_0_31) + ); + DLH_X1_LVT \DRData[20] ( + .D(n_0_31), .G(n_0_43), .Q(DRData[20]) + ); + DFF_X1_LVT \drTmp_reg[19] ( + .CK(n_0_76), .D(mem_rdata[19]), .Q(drTmp[19]), .QN() + ); + AND2_X1_LVT i_0_0_68( + .A1(DWidth[1]), .A2(drTmp[19]), .ZN(n_0_30) + ); + DLH_X1_LVT \DRData[19] ( + .D(n_0_30), .G(n_0_43), .Q(DRData[19]) + ); + DFF_X1_LVT \drTmp_reg[18] ( + .CK(n_0_76), .D(mem_rdata[18]), .Q(drTmp[18]), .QN() + ); + AND2_X1_LVT i_0_0_67( + .A1(DWidth[1]), .A2(drTmp[18]), .ZN(n_0_29) + ); + DLH_X1_LVT \DRData[18] ( + .D(n_0_29), .G(n_0_43), .Q(DRData[18]) + ); + DFF_X1_LVT \drTmp_reg[17] ( + .CK(n_0_76), .D(mem_rdata[17]), .Q(drTmp[17]), .QN() + ); + AND2_X1_LVT i_0_0_66( + .A1(DWidth[1]), .A2(drTmp[17]), .ZN(n_0_28) + ); + DLH_X1_LVT \DRData[17] ( + .D(n_0_28), .G(n_0_43), .Q(DRData[17]) + ); + DFF_X1_LVT \drTmp_reg[16] ( + .CK(n_0_76), .D(mem_rdata[16]), .Q(drTmp[16]), .QN() + ); + AND2_X1_LVT i_0_0_65( + .A1(DWidth[1]), .A2(drTmp[16]), .ZN(n_0_27) + ); + DLH_X1_LVT \DRData[16] ( + .D(n_0_27), .G(n_0_43), .Q(DRData[16]) + ); + NOR2_X1_LVT i_0_0_64( + .A1(n_0_0_91), .A2(n_0_0_87), .ZN(n_0_0_37) + ); + DFF_X1_LVT \drTmp_reg[15] ( + .CK(n_0_76), .D(mem_rdata[15]), .Q(drTmp[15]), .QN() + ); + AOI22_X1_LVT i_0_0_63( + .A1(drTmp[31]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[15]), .ZN(n_0_0_36) + ); + INV_X1_LVT i_0_0_62( + .A(n_0_0_36), .ZN(n_0_26) + ); + DLH_X1_LVT \DRData[15] ( + .D(n_0_26), .G(n_0_43), .Q(DRData[15]) + ); + DFF_X1_LVT \drTmp_reg[14] ( + .CK(n_0_76), .D(mem_rdata[14]), .Q(drTmp[14]), .QN() + ); + AOI22_X1_LVT i_0_0_61( + .A1(drTmp[30]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[14]), .ZN(n_0_0_35) + ); + INV_X1_LVT i_0_0_60( + .A(n_0_0_35), .ZN(n_0_25) + ); + DLH_X1_LVT \DRData[14] ( + .D(n_0_25), .G(n_0_43), .Q(DRData[14]) + ); + DFF_X1_LVT \drTmp_reg[13] ( + .CK(n_0_76), .D(mem_rdata[13]), .Q(drTmp[13]), .QN() + ); + AOI22_X1_LVT i_0_0_59( + .A1(drTmp[29]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[13]), .ZN(n_0_0_34) + ); + INV_X1_LVT i_0_0_58( + .A(n_0_0_34), .ZN(n_0_24) + ); + DLH_X1_LVT \DRData[13] ( + .D(n_0_24), .G(n_0_43), .Q(DRData[13]) + ); + DFF_X1_LVT \drTmp_reg[12] ( + .CK(n_0_76), .D(mem_rdata[12]), .Q(drTmp[12]), .QN() + ); + AOI22_X1_LVT i_0_0_57( + .A1(drTmp[28]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[12]), .ZN(n_0_0_33) + ); + INV_X1_LVT i_0_0_56( + .A(n_0_0_33), .ZN(n_0_23) + ); + DLH_X1_LVT \DRData[12] ( + .D(n_0_23), .G(n_0_43), .Q(DRData[12]) + ); + DFF_X1_LVT \drTmp_reg[11] ( + .CK(n_0_76), .D(mem_rdata[11]), .Q(drTmp[11]), .QN() + ); + AOI22_X1_LVT i_0_0_55( + .A1(drTmp[27]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[11]), .ZN(n_0_0_32) + ); + INV_X1_LVT i_0_0_54( + .A(n_0_0_32), .ZN(n_0_22) + ); + DLH_X1_LVT \DRData[11] ( + .D(n_0_22), .G(n_0_43), .Q(DRData[11]) + ); + DFF_X1_LVT \drTmp_reg[10] ( + .CK(n_0_76), .D(mem_rdata[10]), .Q(drTmp[10]), .QN() + ); + AOI22_X1_LVT i_0_0_53( + .A1(drTmp[26]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[10]), .ZN(n_0_0_31) + ); + INV_X1_LVT i_0_0_52( + .A(n_0_0_31), .ZN(n_0_21) + ); + DLH_X1_LVT \DRData[10] ( + .D(n_0_21), .G(n_0_43), .Q(DRData[10]) + ); + DFF_X1_LVT \drTmp_reg[9] ( + .CK(n_0_76), .D(mem_rdata[9]), .Q(drTmp[9]), .QN() + ); + AOI22_X1_LVT i_0_0_51( + .A1(drTmp[25]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[9]), .ZN(n_0_0_30) + ); + INV_X1_LVT i_0_0_50( + .A(n_0_0_30), .ZN(n_0_20) + ); + DLH_X1_LVT \DRData[9] ( + .D(n_0_20), .G(n_0_43), .Q(DRData[9]) + ); + DFF_X1_LVT \drTmp_reg[8] ( + .CK(n_0_76), .D(mem_rdata[8]), .Q(drTmp[8]), .QN() + ); + AOI22_X1_LVT i_0_0_49( + .A1(drTmp[24]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[8]), .ZN(n_0_0_29) + ); + INV_X1_LVT i_0_0_48( + .A(n_0_0_29), .ZN(n_0_19) + ); + DLH_X1_LVT \DRData[8] ( + .D(n_0_19), .G(n_0_43), .Q(DRData[8]) + ); + AOI22_X1_LVT i_0_0_46( + .A1(drTmp[31]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[15]), .ZN(n_0_0_27) + ); + AOI211_X1_LVT i_0_0_47( + .A(DAddr[1]), .B(n_0_0_83), .C1(n_0_0_94), .C2(DWidth[1]), .ZN(n_0_0_28) + ); + DFF_X1_LVT \drTmp_reg[7] ( + .CK(n_0_76), .D(mem_rdata[7]), .Q(drTmp[7]), .QN() + ); + AOI22_X1_LVT i_0_0_45( + .A1(drTmp[23]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[7]), .ZN(n_0_0_26) + ); + NAND2_X1_LVT i_0_0_44( + .A1(n_0_0_27), .A2(n_0_0_26), .ZN(n_0_18) + ); + DLH_X1_LVT \DRData[7] ( + .D(n_0_18), .G(n_0_43), .Q(DRData[7]) + ); + AOI22_X1_LVT i_0_0_43( + .A1(drTmp[30]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[14]), .ZN(n_0_0_25) + ); + DFF_X1_LVT \drTmp_reg[6] ( + .CK(n_0_76), .D(mem_rdata[6]), .Q(drTmp[6]), .QN() + ); + AOI22_X1_LVT i_0_0_42( + .A1(drTmp[22]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[6]), .ZN(n_0_0_24) + ); + NAND2_X1_LVT i_0_0_41( + .A1(n_0_0_25), .A2(n_0_0_24), .ZN(n_0_17) + ); + DLH_X1_LVT \DRData[6] ( + .D(n_0_17), .G(n_0_43), .Q(DRData[6]) + ); + AOI22_X1_LVT i_0_0_40( + .A1(drTmp[29]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[13]), .ZN(n_0_0_23) + ); + DFF_X1_LVT \drTmp_reg[5] ( + .CK(n_0_76), .D(mem_rdata[5]), .Q(drTmp[5]), .QN() + ); + AOI22_X1_LVT i_0_0_39( + .A1(drTmp[21]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[5]), .ZN(n_0_0_22) + ); + NAND2_X1_LVT i_0_0_38( + .A1(n_0_0_23), .A2(n_0_0_22), .ZN(n_0_16) + ); + DLH_X1_LVT \DRData[5] ( + .D(n_0_16), .G(n_0_43), .Q(DRData[5]) + ); + AOI22_X1_LVT i_0_0_37( + .A1(drTmp[28]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[12]), .ZN(n_0_0_21) + ); + DFF_X1_LVT \drTmp_reg[4] ( + .CK(n_0_76), .D(mem_rdata[4]), .Q(drTmp[4]), .QN() + ); + AOI22_X1_LVT i_0_0_36( + .A1(drTmp[20]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[4]), .ZN(n_0_0_20) + ); + NAND2_X1_LVT i_0_0_35( + .A1(n_0_0_21), .A2(n_0_0_20), .ZN(n_0_15) + ); + DLH_X1_LVT \DRData[4] ( + .D(n_0_15), .G(n_0_43), .Q(DRData[4]) + ); + AOI22_X1_LVT i_0_0_34( + .A1(drTmp[27]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[11]), .ZN(n_0_0_19) + ); + DFF_X1_LVT \drTmp_reg[3] ( + .CK(n_0_76), .D(mem_rdata[3]), .Q(drTmp[3]), .QN() + ); + AOI22_X1_LVT i_0_0_33( + .A1(drTmp[19]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[3]), .ZN(n_0_0_18) + ); + NAND2_X1_LVT i_0_0_32( + .A1(n_0_0_19), .A2(n_0_0_18), .ZN(n_0_14) + ); + DLH_X1_LVT \DRData[3] ( + .D(n_0_14), .G(n_0_43), .Q(DRData[3]) + ); + AOI22_X1_LVT i_0_0_31( + .A1(drTmp[26]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[10]), .ZN(n_0_0_17) + ); + DFF_X1_LVT \drTmp_reg[2] ( + .CK(n_0_76), .D(mem_rdata[2]), .Q(drTmp[2]), .QN() + ); + AOI22_X1_LVT i_0_0_30( + .A1(drTmp[18]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[2]), .ZN(n_0_0_16) + ); + NAND2_X1_LVT i_0_0_29( + .A1(n_0_0_17), .A2(n_0_0_16), .ZN(n_0_13) + ); + DLH_X1_LVT \DRData[2] ( + .D(n_0_13), .G(n_0_43), .Q(DRData[2]) + ); + AOI22_X1_LVT i_0_0_28( + .A1(drTmp[25]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[9]), .ZN(n_0_0_15) + ); + DFF_X1_LVT \drTmp_reg[1] ( + .CK(n_0_76), .D(mem_rdata[1]), .Q(drTmp[1]), .QN() + ); + AOI22_X1_LVT i_0_0_27( + .A1(drTmp[17]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[1]), .ZN(n_0_0_14) + ); + NAND2_X1_LVT i_0_0_26( + .A1(n_0_0_15), .A2(n_0_0_14), .ZN(n_0_12) + ); + DLH_X1_LVT \DRData[1] ( + .D(n_0_12), .G(n_0_43), .Q(DRData[1]) + ); + AOI22_X1_LVT i_0_0_25( + .A1(drTmp[24]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[8]), .ZN(n_0_0_13) + ); + DFF_X1_LVT \drTmp_reg[0] ( + .CK(n_0_76), .D(mem_rdata[0]), .Q(drTmp[0]), .QN() + ); + AOI22_X1_LVT i_0_0_24( + .A1(drTmp[16]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[0]), .ZN(n_0_0_12) + ); + NAND2_X1_LVT i_0_0_23( + .A1(n_0_0_13), .A2(n_0_0_12), .ZN(n_0_11) + ); + DLH_X1_LVT \DRData[0] ( + .D(n_0_11), .G(n_0_43), .Q(DRData[0]) + ); + DFF_X1_LVT \IRData_reg[31] ( + .CK(clk), .D(mem_rdata[31]), .Q(IRData[31]), .QN() + ); + DFF_X1_LVT \IRData_reg[30] ( + .CK(clk), .D(mem_rdata[30]), .Q(IRData[30]), .QN() + ); + DFF_X1_LVT \IRData_reg[29] ( + .CK(clk), .D(mem_rdata[29]), .Q(IRData[29]), .QN() + ); + DFF_X1_LVT \IRData_reg[28] ( + .CK(clk), .D(mem_rdata[28]), .Q(IRData[28]), .QN() + ); + DFF_X1_LVT \IRData_reg[27] ( + .CK(clk), .D(mem_rdata[27]), .Q(IRData[27]), .QN() + ); + DFF_X1_LVT \IRData_reg[26] ( + .CK(clk), .D(mem_rdata[26]), .Q(IRData[26]), .QN() + ); + DFF_X1_LVT \IRData_reg[25] ( + .CK(clk), .D(mem_rdata[25]), .Q(IRData[25]), .QN() + ); + DFF_X1_LVT \IRData_reg[24] ( + .CK(clk), .D(mem_rdata[24]), .Q(IRData[24]), .QN() + ); + DFF_X1_LVT \IRData_reg[23] ( + .CK(clk), .D(mem_rdata[23]), .Q(IRData[23]), .QN() + ); + DFF_X1_LVT \IRData_reg[22] ( + .CK(clk), .D(mem_rdata[22]), .Q(IRData[22]), .QN() + ); + DFF_X1_LVT \IRData_reg[21] ( + .CK(clk), .D(mem_rdata[21]), .Q(IRData[21]), .QN() + ); + DFF_X1_LVT \IRData_reg[20] ( + .CK(clk), .D(mem_rdata[20]), .Q(IRData[20]), .QN() + ); + DFF_X1_LVT \IRData_reg[19] ( + .CK(clk), .D(mem_rdata[19]), .Q(IRData[19]), .QN() + ); + DFF_X1_LVT \IRData_reg[18] ( + .CK(clk), .D(mem_rdata[18]), .Q(IRData[18]), .QN() + ); + DFF_X1_LVT \IRData_reg[17] ( + .CK(clk), .D(mem_rdata[17]), .Q(IRData[17]), .QN() + ); + DFF_X1_LVT \IRData_reg[16] ( + .CK(clk), .D(mem_rdata[16]), .Q(IRData[16]), .QN() + ); + DFF_X1_LVT \IRData_reg[15] ( + .CK(clk), .D(mem_rdata[15]), .Q(IRData[15]), .QN() + ); + DFF_X1_LVT \IRData_reg[14] ( + .CK(clk), .D(mem_rdata[14]), .Q(IRData[14]), .QN() + ); + DFF_X1_LVT \IRData_reg[13] ( + .CK(clk), .D(mem_rdata[13]), .Q(IRData[13]), .QN() + ); + DFF_X1_LVT \IRData_reg[12] ( + .CK(clk), .D(mem_rdata[12]), .Q(IRData[12]), .QN() + ); + DFF_X1_LVT \IRData_reg[11] ( + .CK(clk), .D(mem_rdata[11]), .Q(IRData[11]), .QN() + ); + DFF_X1_LVT \IRData_reg[10] ( + .CK(clk), .D(mem_rdata[10]), .Q(IRData[10]), .QN() + ); + DFF_X1_LVT \IRData_reg[9] ( + .CK(clk), .D(mem_rdata[9]), .Q(IRData[9]), .QN() + ); + DFF_X1_LVT \IRData_reg[8] ( + .CK(clk), .D(mem_rdata[8]), .Q(IRData[8]), .QN() + ); + DFF_X1_LVT \IRData_reg[7] ( + .CK(clk), .D(mem_rdata[7]), .Q(IRData[7]), .QN() + ); + DFF_X1_LVT \IRData_reg[6] ( + .CK(clk), .D(mem_rdata[6]), .Q(IRData[6]), .QN() + ); + DFF_X1_LVT \IRData_reg[5] ( + .CK(clk), .D(mem_rdata[5]), .Q(IRData[5]), .QN() + ); + DFF_X1_LVT \IRData_reg[4] ( + .CK(clk), .D(mem_rdata[4]), .Q(IRData[4]), .QN() + ); + DFF_X1_LVT \IRData_reg[3] ( + .CK(clk), .D(mem_rdata[3]), .Q(IRData[3]), .QN() + ); + DFF_X1_LVT \IRData_reg[2] ( + .CK(clk), .D(mem_rdata[2]), .Q(IRData[2]), .QN() + ); + DFF_X1_LVT \IRData_reg[1] ( + .CK(clk), .D(mem_rdata[1]), .Q(IRData[1]), .QN() + ); + DFF_X1_LVT \IRData_reg[0] ( + .CK(clk), .D(mem_rdata[0]), .Q(IRData[0]), .QN() + ); +endmodule + +module reg_file(Rs1, Rs2, Rd, RRs1, RRs2, WRd, WrReg, reset, clk, dftIn, ts_intno31, + ts_no1050, ts_no1051, ts_no1053, ts_no1054, ts_extsi1226, ts_extsi1227, + ts_extsi1228); + input [31:0] WRd; + input [4:0] Rs1, Rs2, Rd; + input WrReg, reset, clk, dftIn, ts_extsi1227, ts_extsi1228, ts_intno31, + ts_extsi1226; + output [31:0] RRs1, RRs2; + output ts_no1050, ts_no1051, ts_no1053, ts_no1054; + + wire [31:0] registers_1__ap, registers_2__ap, registers_3__ap, + registers_4__ap, registers_5__ap, registers_6__ap, + registers_7__ap, registers_8__ap, registers_9__ap, + registers_10__ap, registers_11__ap, registers_12__ap, + registers_13__ap, registers_14__ap, registers_15__ap, + registers_16__ap, registers_17__ap, registers_18__ap, + registers_19__ap, registers_20__ap, registers_21__ap, + registers_22__ap, registers_23__ap, registers_24__ap, + registers_25__ap, registers_26__ap, registers_27__ap, + registers_28__ap, registers_29__ap, registers_30__ap, + registers_31__ap, registers; + wire n_0_0, n_0_32, n_0_33, n_0_34, n_0_35, n_0_36, n_0_37, n_0_38, n_0_39, + n_0_40, n_0_41, n_0_42, n_0_43, n_0_44, n_0_45, n_0_46, n_0_47, n_0_48, + n_0_49, n_0_50, n_0_51, n_0_52, n_0_53, n_0_54, n_0_55, n_0_56, n_0_57, + n_0_58, n_0_59, n_0_60, n_0_61, n_0_31, n_0_30, n_0_29, n_0_28, n_0_27, + n_0_26, n_0_25, n_0_24, n_0_0_0, n_0_0_1, n_0_23, n_0_22, n_0_21, + n_0_20, n_0_19, n_0_18, n_0_17, n_0_16, n_0_0_2, n_0_0_3, n_0_15, + n_0_14, n_0_13, n_0_12, n_0_11, n_0_10, n_0_9, n_0_8, n_0_0_4, n_0_0_5, + n_0_7, n_0_0_6, n_0_6, n_0_0_7, n_0_5, n_0_0_8, n_0_4, n_0_0_9, + n_0_0_10, n_0_3, n_0_0_11, n_0_2, n_0_0_12, n_0_1, n_0_0_13, n_0_0_14, + n_0_0_15, n_0_0_16, n_0_0_17, n_0_0_18, n_0_0_19, n_0_0_20, n_1_0_0, + n_1_0_1, n_1_0_2, n_1_0_3, n_1_0_4, n_1_0_5, n_1_0_6, n_1_0_7, n_1_0_8, + n_1_0_9, n_1_0_10, n_1_0_11, n_1_0_12, n_1_0_13, n_1_0_14, n_1_0_15, + n_1_0_16, n_1_0_17, n_1_0_18, n_1_0_19, n_1_0_20, n_1_0_21, n_1_0_22, + n_1_0_23, n_1_0_24, n_1_0_25, n_1_0_26, n_1_0_27, n_1_0_28, n_1_0_29, + n_1_0_30, n_1_0_31, n_1_0_32, n_1_0_33, n_1_0_34, n_1_0_35, n_1_0_36, + n_1_0_37, n_1_0_38, n_1_0_39, n_1_0_40, n_1_0_41, n_1_0_42, n_1_0_43, + n_1_0_44, n_1_0_45, n_1_0_46, n_1_0_47, n_1_0_48, n_1_0_49, n_1_0_50, + n_1_0_51, n_1_0_52, n_1_0_53, n_1_0_54, n_1_0_55, n_1_0_56, n_1_0_57, + n_1_0_58, n_1_0_59, n_1_0_60, n_1_0_61, n_1_0_62, n_1_0_63, n_1_0_64, + n_1_0_65, n_1_0_66, n_1_0_67, n_1_0_68, n_1_0_69, n_1_0_70, n_1_0_71, + n_1_0_72, n_1_0_73, n_1_0_74, n_1_0_75, n_1_0_76, n_1_0_77, n_1_0_78, + n_1_0_79, n_1_0_80, n_1_0_81, n_1_0_82, n_1_0_83, n_1_0_84, n_1_0_85, + n_1_0_86, n_1_0_87, n_1_0_88, n_1_0_89, n_1_0_90, n_1_0_91, n_1_0_92, + n_1_0_93, n_1_0_94, n_1_0_95, n_1_0_96, n_1_0_97, n_1_0_98, n_1_0_99, + n_1_0_100, n_1_0_101, n_1_0_102, n_1_0_103, n_1_0_104, n_1_0_105, + n_1_0_106, n_1_0_107, n_1_0_108, n_1_0_109, n_1_0_110, n_1_0_111, + n_1_0_112, n_1_0_113, n_1_0_114, n_1_0_115, n_1_0_116, n_1_0_117, + n_1_0_118, n_1_0_119, n_1_0_120, n_1_0_121, n_1_0_122, n_1_0_123, + n_1_0_124, n_1_0_125, n_1_0_126, n_1_0_127, n_1_0_128, n_1_0_129, + n_1_0_130, n_1_0_131, n_1_0_132, n_1_0_133, n_1_0_134, n_1_0_135, + n_1_0_136, n_1_0_137, n_1_0_138, n_1_0_139, n_1_0_140, n_1_0_141, + n_1_0_142, n_1_0_143, n_1_0_144, n_1_0_145, n_1_0_146, n_1_0_147, + n_1_0_148, n_1_0_149, n_1_0_150, n_1_0_151, n_1_0_152, n_1_0_153, + n_1_0_154, n_1_0_155, n_1_0_156, n_1_0_157, n_1_0_158, n_1_0_159, + n_1_0_160, n_1_0_161, n_1_0_162, n_1_0_163, n_1_0_164, n_1_0_165, + n_1_0_166, n_1_0_167, n_1_0_168, n_1_0_169, n_1_0_170, n_1_0_171, + n_1_0_172, n_1_0_173, n_1_0_174, n_1_0_175, n_1_0_176, n_1_0_177, + n_1_0_178, n_1_0_179, n_1_0_180, n_1_0_181, n_1_0_182, n_1_0_183, + n_1_0_184, n_1_0_185, n_1_0_186, n_1_0_187, n_1_0_188, n_1_0_189, + n_1_0_190, n_1_0_191, n_1_0_192, n_1_0_193, n_1_0_194, n_1_0_195, + n_1_0_196, n_1_0_197, n_1_0_198, n_1_0_199, n_1_0_200, n_1_0_201, + n_1_0_202, n_1_0_203, n_1_0_204, n_1_0_205, n_1_0_206, n_1_0_207, + n_1_0_208, n_1_0_209, n_1_0_210, n_1_0_211, n_1_0_212, n_1_0_213, + n_1_0_214, n_1_0_215, n_1_0_216, n_1_0_217, n_1_0_218, n_1_0_219, + n_1_0_220, n_1_0_221, n_1_0_222, n_1_0_223, n_1_0_224, n_1_0_225, + n_1_0_226, n_1_0_227, n_1_0_228, n_1_0_229, n_1_0_230, n_1_0_231, + n_1_0_232, n_1_0_233, n_1_0_234, n_1_0_235, n_1_0_236, n_1_0_237, + n_1_0_238, n_1_0_239, n_1_0_240, n_1_0_241, n_1_0_242, n_1_0_243, + n_1_0_244, n_1_0_245, n_1_0_246, n_1_0_247, n_1_0_248, n_1_0_249, + n_1_0_250, n_1_0_251, n_1_0_252, n_1_0_253, n_1_0_254, n_1_0_255, + n_1_0_256, n_1_0_257, n_1_0_258, n_1_0_259, n_1_0_260, n_1_0_261, + n_1_0_262, n_1_0_263, n_1_0_264, n_1_0_265, n_1_0_266, n_1_0_267, + n_1_0_268, n_1_0_269, n_1_0_270, n_1_0_271, n_1_0_272, n_1_0_273, + n_1_0_274, n_1_0_275, n_1_0_276, n_1_0_277, n_1_0_278, n_1_0_279, + n_1_0_280, n_1_0_281, n_1_0_282, n_1_0_283, n_1_0_284, n_1_0_285, + n_1_0_286, n_1_0_287, n_1_0_288, n_1_0_289, n_1_0_290, n_1_0_291, + n_1_0_292, n_1_0_293, n_1_0_294, n_1_0_295, n_1_0_296, n_1_0_297, + n_1_0_298, n_1_0_299, n_1_0_300, n_1_0_301, n_1_0_302, n_1_0_303, + n_1_0_304, n_1_0_305, n_1_0_306, n_1_0_307, n_1_0_308, n_1_0_309, + n_1_0_310, n_1_0_311, n_1_0_312, n_1_0_313, n_1_0_314, n_1_0_315, + n_1_0_316, n_1_0_317, n_1_0_318, n_1_0_319, n_1_0_320, n_1_0_321, + n_1_0_322, n_1_0_323, n_1_0_324, n_1_0_325, n_1_0_326, n_1_0_327, + n_1_0_328, n_1_0_329, n_1_0_330, n_1_0_331, n_1_0_332, n_1_0_333, + n_1_0_334, n_1_0_335, n_1_0_336, n_1_0_337, n_1_0_338, n_1_0_339, + n_1_0_340, n_1_0_341, n_1_0_342, n_1_0_343, n_1_0_344, n_1_0_345, + n_1_0_346, n_1_0_347, n_1_0_348, n_1_0_349, n_1_0_350, n_1_0_351, + n_1_0_352, n_1_0_353, n_1_0_354, n_1_0_355, n_1_0_356, n_1_0_357, + n_1_0_358, n_1_0_359, n_1_0_360, n_1_0_361, n_1_0_362, n_1_0_363, + n_1_0_364, n_1_0_365, n_1_0_366, n_1_0_367, n_1_0_368, n_1_0_369, + n_1_0_370, n_1_0_371, n_1_0_372, n_1_0_373, n_1_0_374, n_1_0_375, + n_1_0_376, n_1_0_377, n_1_0_378, n_1_0_379, n_1_0_380, n_1_0_381, + n_1_0_382, n_1_0_383, n_1_0_384, n_1_0_385, n_1_0_386, n_1_0_387, + n_1_0_388, n_1_0_389, n_1_0_390, n_1_0_391, n_1_0_392, n_1_0_393, + n_1_0_394, n_1_0_395, n_1_0_396, n_1_0_397, n_1_0_398, n_1_0_399, + n_1_0_400, n_1_0_401, n_1_0_402, n_1_0_403, n_1_0_404, n_1_0_405, + n_1_0_406, n_1_0_407, n_1_0_408, n_1_0_409, n_1_0_410, n_1_0_411, + n_1_0_412, n_1_0_413, n_1_0_414, n_1_0_415, n_1_0_416, n_1_0_417, + n_1_0_418, n_1_0_419, n_1_0_420, n_1_0_421, n_1_0_422, n_1_0_423, + n_1_0_424, n_1_0_425, n_1_0_426, n_1_0_427, n_1_0_428, n_1_0_429, + n_1_0_430, n_1_0_431, n_1_0_432, n_1_0_433, n_1_0_434, n_1_0_435, + n_1_0_436, n_1_0_437, n_1_0_438, n_1_0_439, n_1_0_440, n_1_0_441, + n_1_0_442, n_1_0_443, n_1_0_444, n_1_0_445, n_1_0_446, n_1_0_447, + n_1_0_448, n_1_0_449, n_1_0_450, n_1_0_451, n_1_0_452, n_1_0_453, + n_1_0_454, n_1_0_455, n_1_0_456, n_1_0_457, n_1_0_458, n_1_0_459, + n_1_0_460, n_1_0_461, n_1_0_462, n_1_0_463, n_1_0_464, n_1_0_465, + n_1_0_466, n_1_0_467, n_1_0_468, n_1_0_469, n_1_0_470, n_1_0_471, + n_1_0_472, n_1_0_473, n_1_0_474, n_1_0_475, n_1_0_476, n_1_0_477, + n_1_0_478, n_1_0_479, n_1_0_480, n_1_0_481, n_1_0_482, n_1_0_483, + n_1_0_484, n_1_0_485, n_1_0_486, n_1_0_487, n_1_0_488, n_1_0_489, + n_1_0_490, n_1_0_491, n_1_0_492, n_1_0_493, n_1_0_494, n_1_0_495, + n_1_0_496, n_1_0_497, n_1_0_498, n_1_0_499, n_1_0_500, n_1_0_501, + n_1_0_502, n_1_0_503, n_1_0_504, n_1_0_505, n_1_0_506, n_1_0_507, + n_1_0_508, n_1_0_509, n_1_0_510, n_1_0_511, n_1_0_512, n_1_0_513, + n_1_0_514, n_1_0_515, n_1_0_516, n_1_0_517, n_1_0_518, n_1_0_519, + n_1_0_520, n_1_0_521, n_1_0_522, n_1_0_523, n_1_0_524, n_1_0_525, + n_1_0_526, n_1_0_527, n_1_0_528, n_1_0_529, n_1_0_530, n_1_0_531, + n_1_0_532, n_1_0_533, n_1_0_534, n_1_0_535, n_1_0_536, n_1_0_537, + n_1_0_538, n_1_0_539, n_1_0_540, n_1_0_541, n_1_0_542, n_1_0_543, + n_1_0_544, n_1_0_545, n_1_0_546, n_1_0_547, n_1_0_548, n_1_0_549, + n_1_0_550, n_1_0_551, n_1_0_552, n_1_0_553, n_1_0_554, n_1_0_555, + n_1_0_556, n_1_0_557, n_1_0_558, n_1_0_559, n_1_0_560, n_1_0_561, + n_1_0_562, n_1_0_563, n_1_0_564, n_1_0_565, n_1_0_566, n_1_0_567, + n_1_0_568, n_1_0_569, n_1_0_570, n_1_0_571, n_1_0_572, n_1_0_573, + n_1_0_574, n_1_0_575, n_1_0_576, n_1_0_577, n_1_0_578, n_1_0_579, + n_1_0_580, n_1_0_581, n_1_0_582, n_1_0_583, n_1_0_584, n_1_0_585, + n_1_0_586, n_1_0_587, n_1_0_588, n_1_0_589, n_1_0_590, n_1_0_591, + n_1_0_592, n_1_0_593, n_1_0_594, n_1_0_595, n_1_0_596, n_1_0_597, + n_1_0_598, n_1_0_599, n_1_0_600, n_1_0_601, n_1_0_602, n_1_0_603, + n_1_0_604, n_1_0_605, n_1_0_606, n_1_0_607, n_1_0_608, n_1_0_609, + n_1_0_610, n_1_0_611, n_1_0_612, n_1_0_613, n_1_0_614, n_1_0_615, + n_1_0_616, n_1_0_617, n_1_0_618, n_1_0_619, n_1_0_620, n_1_0_621, + n_1_0_622, n_1_0_623, n_1_0_624, n_1_0_625, n_1_0_626, n_1_0_627, + n_1_0_628, n_1_0_629, n_1_0_630, n_1_0_631, n_1_0_632, n_1_0_633, + n_1_0_634, n_1_0_635, n_1_0_636, n_1_0_637, n_1_0_638, n_1_0_639, + n_1_0_640, n_1_0_641, n_1_0_642, n_1_0_643, n_1_0_644, n_1_0_645, + n_1_0_646, n_1_0_647, n_1_0_648, n_1_0_649, n_1_0_650, n_1_0_651, + n_1_0_652, n_1_0_653, n_1_0_654, n_1_0_655, n_1_0_656, n_1_0_657, + n_1_0_658, n_1_0_659, n_1_0_660, n_1_0_661, n_1_0_662, n_1_0_663, + n_1_0_664, n_1_0_665, n_1_0_666, n_1_0_667, n_1_0_668, n_1_0_669, + n_1_0_670, n_1_0_671, n_1_0_672, n_1_0_673, n_1_0_674, n_1_0_675, + n_1_0_676, n_1_0_677, n_1_0_678, n_1_0_679, n_1_0_680, n_1_0_681, + n_1_0_682, n_1_0_683, n_1_0_684, n_1_0_685, n_1_0_686, n_1_0_687, + n_1_0_688, n_1_0_689, n_1_0_690, n_1_0_691, n_1_0_692, n_1_0_693, + n_1_0_694, n_1_0_695, n_1_0_696, n_1_0_697, n_1_0_698, n_1_0_699, + n_1_0_700, n_1_0_701, n_1_0_702, n_1_0_703, n_1_0_704, n_1_0_705, + n_1_0_706, n_1_0_707, n_1_0_708, n_1_0_709, n_1_0_710, n_1_0_711, + n_1_0_712, n_1_0_713, n_1_0_714, n_1_0_715, n_1_0_716, n_1_0_717, + n_1_0_718, n_1_0_719, n_1_0_720, n_1_0_721, n_1_0_722, n_1_0_723, + n_1_0_724, n_1_0_725, n_1_0_726, n_1_0_727, n_1_0_728, n_1_0_729, + n_1_0_730, n_1_0_731, n_1_0_732, n_1_0_733, n_1_0_734, n_1_0_735, + n_1_0_736, n_1_0_737, n_1_0_738, n_1_0_739, n_1_0_740, n_1_0_741, + n_1_0_742, n_1_0_743, n_1_0_744, n_1_0_745, n_1_0_746, n_1_0_747, + n_1_0_748, n_1_0_749, n_1_0_750, n_1_0_751, n_1_0_752, n_1_0_753, + n_1_0_754, n_1_0_755, n_1_0_756, n_1_0_757, n_1_0_758, n_1_0_759, + n_1_0_760, n_1_0_761, n_1_0_762, n_1_0_763, n_1_0_764, n_1_0_765, + n_1_0_766, n_1_0_767, n_1_0_768, n_1_0_769, n_1_0_770, n_1_0_771, + n_1_0_772, n_1_0_773, n_1_0_774, n_1_0_775, n_1_0_776, n_1_0_777, + n_1_0_778, n_1_0_779, n_1_0_780, n_1_0_781, n_1_0_782, n_1_0_783, + n_1_0_784, n_1_0_785, n_1_0_786, n_1_0_787, n_1_0_788, n_1_0_789, + n_1_0_790, n_1_0_791, n_1_0_792, n_1_0_793, n_1_0_794, n_1_0_795, + n_1_0_796, n_1_0_797, n_1_0_798, n_1_0_799, n_1_0_800, n_1_0_801, + n_1_0_802, n_1_0_803, n_1_0_804, n_1_0_805, n_1_0_806, n_1_0_807, + n_1_0_808, n_1_0_809, n_1_0_810, n_1_0_811, n_1_0_812, n_1_0_813, + n_1_0_814, n_1_0_815, n_1_0_816, n_1_0_817, n_1_0_818, n_1_0_819, + n_1_0_820, n_1_0_821, n_1_0_822, n_1_0_823, n_1_0_824, n_1_0_825, + n_1_0_826, n_1_0_827, n_1_0_828, n_1_0_829, n_1_0_830, n_1_0_831, + n_1_0_832, n_1_0_833, n_1_0_834, n_1_0_835, n_1_0_836, n_1_0_837, + n_1_0_838, n_1_0_839, n_1_0_840, n_1_0_841, n_1_0_842, n_1_0_843, + n_1_0_844, n_1_0_845, n_1_0_846, n_1_0_847, n_1_0_848, n_1_0_849, + n_1_0_850, n_1_0_851, n_1_0_852, n_1_0_853, n_1_0_854, n_1_0_855, + n_1_0_856, n_1_0_857, n_1_0_858, n_1_0_859, n_1_0_860, n_1_0_861, + n_1_0_862, n_1_0_863, n_1_0_864, n_1_0_865, n_1_0_866, n_1_0_867, + n_1_0_868, n_1_0_869, n_1_0_870, n_1_0_871, n_1_0_872, n_1_0_873, + n_1_0_874, n_1_0_875, n_1_0_876, n_1_0_877, n_1_0_878, n_1_0_879, + n_1_0_880, n_1_0_881, n_1_0_882, n_1_0_883, n_1_0_884, n_1_0_885, + n_1_0_886, n_1_0_887, n_1_0_888, n_1_0_889, n_1_0_890, n_1_0_891, + n_1_0_892, n_1_0_893, n_1_0_894, n_1_0_895, n_1_0_896, n_1_0_897, + n_1_0_898, n_1_0_899, n_1_0_900, n_1_0_901, n_1_0_902, n_1_0_903, + n_1_0_904, n_1_0_905, n_1_0_906, n_1_0_907, n_1_0_908, n_1_0_909, + n_1_0_910, n_1_0_911, n_1_0_912, n_1_0_913, n_1_0_914, n_1_0_915, + n_1_0_916, n_1_0_917, n_1_0_918, n_1_0_919, n_1_0_920, n_1_0_921, + n_1_0_922, n_1_0_923, n_1_0_924, n_1_0_925, n_1_0_926, n_1_0_927, + n_1_0_928, n_1_0_929, n_1_0_930, n_1_0_931, n_1_0_932, n_1_0_933, + n_1_0_934, n_1_0_935, n_1_0_936, n_1_0_937, n_1_0_938, n_1_0_939, + n_1_0_940, n_1_0_941, n_1_0_942, n_1_0_943, n_1_0_944, n_1_0_945, + n_1_0_946, n_1_0_947, n_1_0_948, n_1_0_949, n_1_0_950, n_1_0_951, + n_1_0_952, n_1_0_953, n_1_0_954, n_1_0_955, n_1_0_956, n_1_0_957, + n_1_0_958, n_1_0_959, n_1_0_960, n_1_0_961, n_1_0_962, n_1_0_963, + n_1_0_964, n_1_0_965, n_1_0_966, n_1_0_967, n_1_0_968, n_1_0_969, + n_1_0_970, n_1_0_971, n_1_0_972, n_1_0_973, n_1_0_974, n_1_0_975, + n_1_0_976, n_1_0_977, n_1_0_978, n_1_0_979, n_1_0_980, n_1_0_981, + n_1_0_982, n_1_0_983, n_1_0_984, n_1_0_985, n_1_0_986, n_1_0_987, + n_1_0_988, n_1_0_989, n_1_0_990, n_1_0_991, n_1_0_992, n_1_0_993, + n_1_0_994, n_1_0_995, n_1_0_996, n_1_0_997, n_1_0_998, n_1_0_999, + n_1_0_1000, n_1_0_1001, n_1_0_1002, n_1_0_1003, n_1_0_1004, n_1_0_1005, + n_1_0_1006, n_1_0_1007, n_1_0_1008, n_1_0_1009, n_1_0_1010, n_1_0_1011, + n_1_0_1012, n_1_0_1013, n_1_0_1014, n_1_0_1015, n_1_0_1016, n_1_0_1017, + n_1_0_1018, n_1_0_1019, n_1_0_1020, n_1_0_1021, n_1_0_1022, n_1_0_1023, + n_1_0_1024, n_1_0_1025, n_1_0_1026, n_1_0_1027, n_1_0_1028, n_1_0_1029, + n_1_0_1030, n_1_0_1031, n_1_0_1032, n_1_0_1033, n_1_0_1034, n_1_0_1035, + n_1_0_1036, n_1_0_1037, n_1_0_1038, n_1_0_1039, n_1_0_1040, n_1_0_1041, + n_1_0_1042, n_1_0_1043, n_1_0_1044, n_1_0_1045, n_1_0_1046, n_1_0_1047, + n_1_0_1048, n_1_0_1049, n_1_0_1050, n_1_0_1051, n_1_0_1052, n_1_0_1053, + n_1_0_1054, n_1_0_1055, n_1_0_1056, n_1_0_1057, n_1_0_1058, n_1_0_1059, + n_1_0_1060, n_1_0_1061, n_1_0_1062, n_1_0_1063, n_1_0_1064, n_1_0_1065, + n_1_0_1066, n_1_0_1067, n_1_0_1068, n_1_0_1069, n_1_0_1070, n_1_0_1071, + n_1_0_1072, n_1_0_1073, n_1_0_1074, n_1_0_1075, n_1_0_1076, n_1_0_1077, + n_1_0_1078, n_1_0_1079, n_1_0_1080, n_1_0_1081, n_1_0_1082, n_1_0_1083, + n_1_0_1084, n_1_0_1085, n_1_0_1086, n_1_0_1087, n_1_0_1088, n_1_0_1089, + n_1_0_1090, n_1_0_1091, n_1_0_1092, n_1_0_1093, n_1_0_1094, n_1_0_1095, + n_1_0_1096, n_1_0_1097, n_1_0_1098, n_1_0_1099, n_1_0_1100, n_1_0_1101, + n_1_0_1102, n_1_0_1103, n_1_0_1104, n_1_0_1105, n_1_0_1106, n_1_0_1107, + n_1_0_1108, n_1_0_1109, n_1_0_1110, n_1_0_1111, n_1_0_1112, n_1_0_1113, + n_1_0_1114, n_1_0_1115, n_1_0_1116, n_1_0_1117, n_1_0_1118, n_1_0_1119, + n_1_0_1120, n_1_0_1121, n_1_0_1122, n_1_0_1123, n_1_0_1124, n_1_0_1125, + n_1_0_1126, n_1_0_1127, n_1_0_1128, n_1_0_1129, n_1_0_1130, n_1_0_1131, + n_1_0_1132, n_1_0_1133, n_1_0_1134, n_1_0_1135, n_1_0_1136, n_1_0_1137, + n_1_0_1138, n_1_0_1139, n_1_0_1140, n_1_0_1141, n_1_0_1142, n_1_0_1143, + n_1_0_1144, n_1_0_1145, n_1_0_1146, n_1_0_1147, n_1_0_1148, n_1_0_1149, + n_1_0_1150, n_1_0_1151, n_1_0_1152, n_1_0_1153, n_1_0_1154, n_1_0_1155, + n_1_0_1156, n_1_0_1157, n_1_0_1158, n_1_0_1159, n_1_0_1160, n_1_0_1161, + n_1_0_1162, n_1_0_1163, n_1_0_1164, n_1_0_1165, n_1_0_1166, n_1_0_1167, + n_1_0_1168, n_1_0_1169, n_1_0_1170, n_1_0_1171, n_1_0_1172, n_1_0_1173, + n_1_0_1174, n_1_0_1175, n_1_0_1176, n_1_0_1177, n_1_0_1178, n_1_0_1179, + n_1_0_1180, n_1_0_1181, n_1_0_1182, n_1_0_1183, n_1_0_1184, n_1_0_1185, + n_1_0_1186, n_1_0_1187, n_1_0_1188, n_1_0_1189, n_1_0_1190, n_1_0_1191, + n_1_0_1192, n_1_0_1193, n_1_0_1194, n_1_0_1195, n_1_0_1196, n_1_0_1197, + n_1_0_1198, n_1_0_1199, n_1_0_1200, n_1_0_1201, n_1_0_1202, n_1_0_1203, + n_1_0_1204, n_1_0_1205, n_1_0_1206, n_1_0_1207, n_1_0_1208, n_1_0_1209, + n_1_0_1210, n_1_0_1211, n_1_0_1212, n_1_0_1213, n_1_0_1214, n_1_0_1215, + n_1_0_1216, n_1_0_1217, n_1_0_1218, n_1_0_1219, n_1_0_1220, n_1_0_1221, + n_1_0_1222, n_1_0_1223, n_1_0_1224, n_1_0_1225, n_1_0_1226, n_1_0_1227, + n_1_0_1228, n_1_0_1229, n_1_0_1230, n_1_0_1231, n_1_0_1232, n_1_0_1233, + n_1_0_1234, n_1_0_1235, n_1_0_1236, n_1_0_1237, n_1_0_1238, n_1_0_1239, + n_1_0_1240, n_1_0_1241, n_1_0_1242, n_1_0_1243, n_1_0_1244, n_1_0_1245, + n_1_0_1246, n_1_0_1247, n_1_0_1248, n_1_0_1249, n_1_0_1250, n_1_0_1251, + n_1_0_1252, n_1_0_1253, n_1_0_1254, n_1_0_1255, n_1_0_1256, n_1_0_1257, + n_1_0_1258, n_1_0_1259, n_1_0_1260, n_1_0_1261, n_1_0_1262, n_1_0_1263, + n_1_0_1264, n_1_0_1265, n_1_0_1266, n_1_0_1267, n_1_0_1268, n_1_0_1269, + n_1_0_1270, n_1_0_1271, n_1_0_1272, n_1_0_1273, n_1_0_1274, n_1_0_1275, + n_1_0_1276, n_1_0_1277, n_1_0_1278, n_1_0_1279, n_1_0_1280, n_1_0_1281, + n_1_0_1282, n_1_0_1283, n_1_0_1284, n_1_0_1285, n_1_0_1286, n_1_0_1287, + n_1_0_1288, n_1_0_1289, n_1_0_1290, n_1_0_1291, n_1_0_1292, n_1_0_1293, + n_1_0_1294, n_1_0_1295, n_1_0_1296, n_1_0_1297, n_1_0_1298, n_1_0_1299, + n_1_0_1300, n_1_0_1301, n_1_0_1302, n_1_0_1303, n_1_0_1304, n_1_0_1305, + n_1_0_1306, n_1_0_1307, n_1_0_1308, n_1_0_1309, ts_pbuf_extsi1227_, + ts_pbuf_extsi1228_, ts_pbuf_extsi1226_; + + INV_X1_LVT i_0_0_79( + .A(reset), .ZN(n_0_0_16) + ); + AND2_X1_LVT i_0_0_31( + .A1(n_0_0_16), .A2(WRd[31]), .ZN(registers[31]) + ); + INV_X1_LVT i_0_0_81( + .A(Rd[1]), .ZN(n_0_0_18) + ); + INV_X1_LVT i_0_0_80( + .A(Rd[0]), .ZN(n_0_0_17) + ); + NAND3_X1_LVT i_0_0_69( + .A1(n_0_0_18), .A2(n_0_0_17), .A3(Rd[2]), .ZN(n_0_0_9) + ); + NAND3_X1_LVT i_0_0_41( + .A1(Rd[3]), .A2(WrReg), .A3(Rd[4]), .ZN(n_0_0_1) + ); + OAI21_X1_LVT i_0_0_35( + .A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_1), .ZN(n_0_28) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[28]_reg ( + .CK(clk), .E(n_0_28), .GCK(n_0_58), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[28][31] ( + .CK(n_0_58), .D(registers[31]), .Q(registers_28__ap[31]), .QN(), .SE(dftIn), + .SI(ts_pbuf_extsi1227_) + ); + INV_X1_LVT i_1_0_1370( + .A(Rs1[0]), .ZN(n_1_0_1306) + ); + NAND3_X1_LVT i_1_0_1354( + .A1(n_1_0_1306), .A2(Rs1[3]), .A3(Rs1[4]), .ZN(n_1_0_1290) + ); + INV_X1_LVT i_1_0_1373( + .A(Rs1[2]), .ZN(n_1_0_1309) + ); + OR2_X1_LVT i_1_0_1348( + .A1(n_1_0_1309), .A2(Rs1[1]), .ZN(n_1_0_1284) + ); + NOR2_X1_LVT i_1_0_1347( + .A1(n_1_0_1290), .A2(n_1_0_1284), .ZN(n_1_0_1283) + ); + NOR4_X1_LVT i_1_0_1342( + .A1(n_1_0_1284), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), .ZN(n_1_0_1278) + ); + INV_X1_LVT i_0_0_83( + .A(WrReg), .ZN(n_0_0_20) + ); + OR3_X1_LVT i_0_0_77( + .A1(n_0_0_20), .A2(Rd[4]), .A3(Rd[3]), .ZN(n_0_0_14) + ); + OAI21_X1_LVT i_0_0_68( + .A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_9), .ZN(n_0_4) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[4]_reg ( + .CK(clk), .E(n_0_4), .GCK(n_0_34), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[4][31] ( + .CK(n_0_34), .D(registers[31]), .Q(registers_4__ap[31]), .QN(), .SE(dftIn), + .SI(ts_pbuf_extsi1228_) + ); + AOI22_X1_LVT i_1_0_1320( + .A1(registers_28__ap[31]), .A2(n_1_0_1283), .B1(n_1_0_1278), .B2(registers_4__ap[31]), + .ZN(n_1_0_1256) + ); + NAND2_X1_LVT i_0_0_70( + .A1(n_0_0_18), .A2(n_0_0_17), .ZN(n_0_0_10) + ); + INV_X1_LVT i_0_0_82( + .A(Rd[4]), .ZN(n_0_0_19) + ); + OR3_X1_LVT i_0_0_51( + .A1(n_0_0_20), .A2(n_0_0_19), .A3(Rd[3]), .ZN(n_0_0_3) + ); + OR2_X1_LVT i_0_0_50( + .A1(n_0_0_3), .A2(Rd[2]), .ZN(n_0_0_2) + ); + OAI21_X1_LVT i_0_0_49( + .A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_2), .ZN(n_0_16) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[16]_reg ( + .CK(clk), .E(n_0_16), .GCK(n_0_46), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[16][31] ( + .CK(n_0_46), .D(registers[31]), .Q(registers_16__ap[31]), .QN(), .SE(dftIn), + .SI(ts_intno31) + ); + INV_X1_LVT i_1_0_1371( + .A(Rs1[3]), .ZN(n_1_0_1307) + ); + NAND3_X1_LVT i_1_0_1363( + .A1(n_1_0_1307), .A2(n_1_0_1306), .A3(Rs1[4]), .ZN(n_1_0_1299) + ); + OR2_X1_LVT i_1_0_1357( + .A1(Rs1[1]), .A2(Rs1[2]), .ZN(n_1_0_1293) + ); + NOR2_X1_LVT i_1_0_1331( + .A1(n_1_0_1299), .A2(n_1_0_1293), .ZN(n_1_0_1267) + ); + NAND2_X1_LVT i_1_0_1365( + .A1(Rs1[1]), .A2(Rs1[2]), .ZN(n_1_0_1301) + ); + NAND3_X1_LVT i_1_0_1344( + .A1(Rs1[4]), .A2(Rs1[3]), .A3(Rs1[0]), .ZN(n_1_0_1280) + ); + NOR2_X1_LVT i_1_0_1330( + .A1(n_1_0_1301), .A2(n_1_0_1280), .ZN(n_1_0_1266) + ); + NAND3_X1_LVT i_0_0_63( + .A1(Rd[2]), .A2(Rd[1]), .A3(Rd[0]), .ZN(n_0_0_6) + ); + OAI21_X1_LVT i_0_0_32( + .A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_1), .ZN(n_0_31) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[31]_reg ( + .CK(clk), .E(n_0_31), .GCK(n_0_61), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[31][31] ( + .CK(n_0_61), .D(registers[31]), .Q(registers_31__ap[31]), .QN(), .SE(dftIn), + .SI(registers_4__ap[31]) + ); + AOI22_X1_LVT i_1_0_1329( + .A1(registers_16__ap[31]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[31]), + .ZN(n_1_0_1265) + ); + NAND3_X1_LVT i_0_0_65( + .A1(n_0_0_17), .A2(Rd[1]), .A3(Rd[2]), .ZN(n_0_0_7) + ); + OAI21_X1_LVT i_0_0_64( + .A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_7), .ZN(n_0_6) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[6]_reg ( + .CK(clk), .E(n_0_6), .GCK(n_0_36), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[6][31] ( + .CK(n_0_36), .D(registers[31]), .Q(registers_6__ap[31]), .QN(), .SE(dftIn), + .SI(registers_31__ap[31]) + ); + NOR4_X1_LVT i_1_0_1364( + .A1(n_1_0_1301), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), .ZN(n_1_0_1300) + ); + INV_X1_LVT i_1_0_1372( + .A(Rs1[4]), .ZN(n_1_0_1308) + ); + NAND3_X1_LVT i_1_0_1339( + .A1(n_1_0_1308), .A2(n_1_0_1307), .A3(Rs1[0]), .ZN(n_1_0_1275) + ); + NOR2_X1_LVT i_1_0_1338( + .A1(n_1_0_1293), .A2(n_1_0_1275), .ZN(n_1_0_1274) + ); + NAND2_X1_LVT i_0_0_78( + .A1(n_0_0_18), .A2(Rd[0]), .ZN(n_0_0_15) + ); + OR2_X1_LVT i_0_0_76( + .A1(n_0_0_14), .A2(Rd[2]), .ZN(n_0_0_13) + ); + OAI21_X1_LVT i_0_0_75( + .A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_13), .ZN(n_0_1) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[1]_reg ( + .CK(clk), .E(n_0_1), .GCK(n_0_0), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[1][31] ( + .CK(n_0_0), .D(registers[31]), .Q(registers_1__ap[31]), .QN(), .SE(dftIn), + .SI(ts_pbuf_extsi1226_) + ); + AOI22_X1_LVT i_1_0_1319( + .A1(registers_6__ap[31]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[31]), + .ZN(n_1_0_1255) + ); + OAI21_X1_LVT i_0_0_42( + .A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_3), .ZN(n_0_23) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[23]_reg ( + .CK(clk), .E(n_0_23), .GCK(n_0_53), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[23][31] ( + .CK(n_0_53), .D(registers[31]), .Q(registers_23__ap[31]), .QN(), .SE(dftIn), + .SI(registers_1__ap[31]) + ); + NAND3_X1_LVT i_1_0_1360( + .A1(n_1_0_1307), .A2(Rs1[0]), .A3(Rs1[4]), .ZN(n_1_0_1296) + ); + NOR2_X1_LVT i_1_0_1328( + .A1(n_1_0_1301), .A2(n_1_0_1296), .ZN(n_1_0_1264) + ); + NOR2_X1_LVT i_1_0_1327( + .A1(n_1_0_1301), .A2(n_1_0_1275), .ZN(n_1_0_1263) + ); + OAI21_X1_LVT i_0_0_62( + .A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_6), .ZN(n_0_7) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[7]_reg ( + .CK(clk), .E(n_0_7), .GCK(n_0_37), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[7][31] ( + .CK(n_0_37), .D(registers[31]), .Q(registers_7__ap[31]), .QN(), .SE(dftIn), + .SI(registers_6__ap[31]) + ); + AOI22_X1_LVT i_1_0_1326( + .A1(registers_23__ap[31]), .A2(n_1_0_1264), .B1(n_1_0_1263), .B2(registers_7__ap[31]), + .ZN(n_1_0_1262) + ); + INV_X1_LVT i_1_0_1325( + .A(n_1_0_1262), .ZN(n_1_0_1261) + ); + NAND2_X1_LVT i_1_0_1362( + .A1(n_1_0_1309), .A2(Rs1[1]), .ZN(n_1_0_1298) + ); + NOR2_X1_LVT i_1_0_1359( + .A1(n_1_0_1298), .A2(n_1_0_1296), .ZN(n_1_0_1295) + ); + NAND2_X1_LVT i_0_0_72( + .A1(Rd[1]), .A2(Rd[0]), .ZN(n_0_0_11) + ); + OAI21_X1_LVT i_0_0_46( + .A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_2), .ZN(n_0_19) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[19]_reg ( + .CK(clk), .E(n_0_19), .GCK(n_0_49), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[19][31] ( + .CK(n_0_49), .D(registers[31]), .Q(registers_19__ap[31]), .QN(), .SE(dftIn), + .SI(registers_23__ap[31]) + ); + NAND3_X1_LVT i_0_0_67( + .A1(n_0_0_18), .A2(Rd[0]), .A3(Rd[2]), .ZN(n_0_0_8) + ); + OAI21_X1_LVT i_0_0_66( + .A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_8), .ZN(n_0_5) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[5]_reg ( + .CK(clk), .E(n_0_5), .GCK(n_0_35), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[5][31] ( + .CK(n_0_35), .D(registers[31]), .Q(registers_5__ap[31]), .QN(), .SE(dftIn), + .SI(registers_7__ap[31]) + ); + NOR2_X1_LVT i_1_0_1337( + .A1(n_1_0_1284), .A2(n_1_0_1275), .ZN(n_1_0_1273) + ); + AOI221_X1_LVT i_1_0_1318( + .A(n_1_0_1261), .B1(n_1_0_1295), .B2(registers_19__ap[31]), .C1(registers_5__ap[31]), + .C2(n_1_0_1273), .ZN(n_1_0_1254) + ); + NAND2_X1_LVT i_0_0_74( + .A1(n_0_0_17), .A2(Rd[1]), .ZN(n_0_0_12) + ); + NAND3_X1_LVT i_0_0_61( + .A1(n_0_0_19), .A2(WrReg), .A3(Rd[3]), .ZN(n_0_0_5) + ); + OR2_X1_LVT i_0_0_60( + .A1(n_0_0_5), .A2(Rd[2]), .ZN(n_0_0_4) + ); + OAI21_X1_LVT i_0_0_57( + .A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_4), .ZN(n_0_10) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[10]_reg ( + .CK(clk), .E(n_0_10), .GCK(n_0_40), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[10][31] ( + .CK(n_0_40), .D(registers[31]), .Q(registers_10__ap[31]), .QN(), .SE(dftIn), + .SI(registers_16__ap[31]) + ); + NAND3_X1_LVT i_1_0_1352( + .A1(n_1_0_1308), .A2(n_1_0_1306), .A3(Rs1[3]), .ZN(n_1_0_1288) + ); + NOR2_X1_LVT i_1_0_1351( + .A1(n_1_0_1298), .A2(n_1_0_1288), .ZN(n_1_0_1287) + ); + NOR2_X1_LVT i_1_0_1349( + .A1(n_1_0_1298), .A2(n_1_0_1290), .ZN(n_1_0_1285) + ); + OR2_X1_LVT i_0_0_40( + .A1(n_0_0_1), .A2(Rd[2]), .ZN(n_0_0_0) + ); + OAI21_X1_LVT i_0_0_37( + .A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_0), .ZN(n_0_26) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[26]_reg ( + .CK(clk), .E(n_0_26), .GCK(n_0_56), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[26][31] ( + .CK(n_0_56), .D(registers[31]), .Q(registers_26__ap[31]), .QN(), .SE(dftIn), + .SI(registers_28__ap[31]) + ); + OAI21_X1_LVT i_0_0_59( + .A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_4), .ZN(n_0_8) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[8]_reg ( + .CK(clk), .E(n_0_8), .GCK(n_0_38), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[8][31] ( + .CK(n_0_38), .D(registers[31]), .Q(registers_8__ap[31]), .QN(), .SE(dftIn), + .SI(registers_5__ap[31]) + ); + NOR2_X1_LVT i_1_0_1346( + .A1(n_1_0_1293), .A2(n_1_0_1288), .ZN(n_1_0_1282) + ); + AOI222_X1_LVT i_1_0_1317( + .A1(registers_10__ap[31]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[31]), + .C1(registers_8__ap[31]), .C2(n_1_0_1282), .ZN(n_1_0_1253) + ); + NAND4_X1_LVT i_1_0_1316( + .A1(n_1_0_1265), .A2(n_1_0_1255), .A3(n_1_0_1254), .A4(n_1_0_1253), .ZN(n_1_0_1252) + ); + NAND3_X1_LVT i_1_0_1356( + .A1(n_1_0_1308), .A2(Rs1[3]), .A3(Rs1[0]), .ZN(n_1_0_1292) + ); + NOR2_X1_LVT i_1_0_1355( + .A1(n_1_0_1293), .A2(n_1_0_1292), .ZN(n_1_0_1291) + ); + OAI21_X1_LVT i_0_0_58( + .A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_4), .ZN(n_0_9) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[9]_reg ( + .CK(clk), .E(n_0_9), .GCK(n_0_39), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[9][31] ( + .CK(n_0_39), .D(registers[31]), .Q(registers_9__ap[31]), .QN(), .SE(dftIn), + .SI(registers_8__ap[31]) + ); + OAI21_X1_LVT i_0_0_34( + .A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_1), .ZN(n_0_29) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[29]_reg ( + .CK(clk), .E(n_0_29), .GCK(n_0_59), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[29][31] ( + .CK(n_0_59), .D(registers[31]), .Q(registers_29__ap[31]), .QN(), .SE(dftIn), + .SI(registers_26__ap[31]) + ); + NOR2_X1_LVT i_1_0_1340( + .A1(n_1_0_1284), .A2(n_1_0_1280), .ZN(n_1_0_1276) + ); + AOI221_X1_LVT i_1_0_1315( + .A(n_1_0_1252), .B1(n_1_0_1291), .B2(registers_9__ap[31]), .C1(registers_29__ap[31]), + .C2(n_1_0_1276), .ZN(n_1_0_1251) + ); + OAI21_X1_LVT i_0_0_47( + .A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_2), .ZN(n_0_18) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[18]_reg ( + .CK(clk), .E(n_0_18), .GCK(n_0_48), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[18][31] ( + .CK(n_0_48), .D(registers[31]), .Q(registers_18__ap[31]), .QN(), .SE(dftIn), + .SI(registers_19__ap[31]) + ); + NOR2_X1_LVT i_1_0_1361( + .A1(n_1_0_1299), .A2(n_1_0_1298), .ZN(n_1_0_1297) + ); + NOR2_X1_LVT i_1_0_1336( + .A1(n_1_0_1301), .A2(n_1_0_1290), .ZN(n_1_0_1272) + ); + OAI21_X1_LVT i_0_0_33( + .A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_1), .ZN(n_0_30) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[30]_reg ( + .CK(clk), .E(n_0_30), .GCK(n_0_60), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[30][31] ( + .CK(n_0_60), .D(registers[31]), .Q(registers_30__ap[31]), .QN(), .SE(dftIn), + .SI(registers_29__ap[31]) + ); + AOI22_X1_LVT i_1_0_1314( + .A1(registers_18__ap[31]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[31]), + .ZN(n_1_0_1250) + ); + OAI21_X1_LVT i_0_0_39( + .A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_0), .ZN(n_0_24) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[24]_reg ( + .CK(clk), .E(n_0_24), .GCK(n_0_54), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[24][31] ( + .CK(n_0_54), .D(registers[31]), .Q(registers_24__ap[31]), .QN(), .SE(dftIn), + .SI(registers_30__ap[31]) + ); + NOR2_X1_LVT i_1_0_1353( + .A1(n_1_0_1293), .A2(n_1_0_1290), .ZN(n_1_0_1289) + ); + NOR2_X1_LVT i_1_0_1324( + .A1(n_1_0_1288), .A2(n_1_0_1284), .ZN(n_1_0_1260) + ); + OAI21_X1_LVT i_0_0_55( + .A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_5), .ZN(n_0_12) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[12]_reg ( + .CK(clk), .E(n_0_12), .GCK(n_0_42), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[12][31] ( + .CK(n_0_42), .D(registers[31]), .Q(registers_12__ap[31]), .QN(), .SE(dftIn), + .SI(registers_10__ap[31]) + ); + AOI22_X1_LVT i_1_0_1313( + .A1(registers_24__ap[31]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[31]), + .ZN(n_1_0_1249) + ); + OAI21_X1_LVT i_0_0_43( + .A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_3), .ZN(n_0_22) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[22]_reg ( + .CK(clk), .E(n_0_22), .GCK(n_0_52), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[22][31] ( + .CK(n_0_52), .D(registers[31]), .Q(registers_22__ap[31]), .QN(), .SE(dftIn), + .SI(registers_18__ap[31]) + ); + NOR2_X1_LVT i_1_0_1358( + .A1(n_1_0_1301), .A2(n_1_0_1299), .ZN(n_1_0_1294) + ); + NOR2_X1_LVT i_1_0_1323( + .A1(n_1_0_1296), .A2(n_1_0_1284), .ZN(n_1_0_1259) + ); + OAI21_X1_LVT i_0_0_44( + .A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_3), .ZN(n_0_21) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[21]_reg ( + .CK(clk), .E(n_0_21), .GCK(n_0_51), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[21][31] ( + .CK(n_0_51), .D(registers[31]), .Q(registers_21__ap[31]), .QN(), .SE(dftIn), + .SI(registers_22__ap[31]) + ); + AOI22_X1_LVT i_1_0_1312( + .A1(registers_22__ap[31]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[31]), + .ZN(n_1_0_1248) + ); + NAND3_X1_LVT i_1_0_1311( + .A1(n_1_0_1250), .A2(n_1_0_1249), .A3(n_1_0_1248), .ZN(n_1_0_1247) + ); + NOR2_X1_LVT i_1_0_1335( + .A1(n_1_0_1296), .A2(n_1_0_1293), .ZN(n_1_0_1271) + ); + OAI21_X1_LVT i_0_0_48( + .A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_2), .ZN(n_0_17) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[17]_reg ( + .CK(clk), .E(n_0_17), .GCK(n_0_47), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[17][31] ( + .CK(n_0_47), .D(registers[31]), .Q(registers_17__ap[31]), .QN(), .SE(dftIn), + .SI(registers_21__ap[31]) + ); + OAI21_X1_LVT i_0_0_45( + .A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_3), .ZN(n_0_20) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[20]_reg ( + .CK(clk), .E(n_0_20), .GCK(n_0_50), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[20][31] ( + .CK(n_0_50), .D(registers[31]), .Q(registers_20__ap[31]), .QN(), .SE(dftIn), + .SI(registers_17__ap[31]) + ); + NOR2_X1_LVT i_1_0_1345( + .A1(n_1_0_1299), .A2(n_1_0_1284), .ZN(n_1_0_1281) + ); + AOI221_X1_LVT i_1_0_1310( + .A(n_1_0_1247), .B1(n_1_0_1271), .B2(registers_17__ap[31]), .C1(registers_20__ap[31]), + .C2(n_1_0_1281), .ZN(n_1_0_1246) + ); + OAI21_X1_LVT i_0_0_36( + .A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_0), .ZN(n_0_27) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[27]_reg ( + .CK(clk), .E(n_0_27), .GCK(n_0_57), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[27][31] ( + .CK(n_0_57), .D(registers[31]), .Q(registers_27__ap[31]), .QN(), .SE(dftIn), + .SI(registers_24__ap[31]) + ); + NOR2_X1_LVT i_1_0_1343( + .A1(n_1_0_1298), .A2(n_1_0_1280), .ZN(n_1_0_1279) + ); + NOR2_X1_LVT i_1_0_1334( + .A1(n_1_0_1298), .A2(n_1_0_1292), .ZN(n_1_0_1270) + ); + OAI21_X1_LVT i_0_0_56( + .A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_4), .ZN(n_0_11) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[11]_reg ( + .CK(clk), .E(n_0_11), .GCK(n_0_41), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[11][31] ( + .CK(n_0_41), .D(registers[31]), .Q(registers_11__ap[31]), .QN(), .SE(dftIn), + .SI(registers_12__ap[31]) + ); + AOI22_X1_LVT i_1_0_1309( + .A1(registers_27__ap[31]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[31]), + .ZN(n_1_0_1245) + ); + OAI21_X1_LVT i_0_0_54( + .A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_5), .ZN(n_0_13) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[13]_reg ( + .CK(clk), .E(n_0_13), .GCK(n_0_43), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[13][31] ( + .CK(n_0_43), .D(registers[31]), .Q(registers_13__ap[31]), .QN(), .SE(dftIn), + .SI(registers_11__ap[31]) + ); + NOR2_X1_LVT i_1_0_1341( + .A1(n_1_0_1292), .A2(n_1_0_1284), .ZN(n_1_0_1277) + ); + NOR2_X1_LVT i_1_0_1333( + .A1(n_1_0_1293), .A2(n_1_0_1280), .ZN(n_1_0_1269) + ); + OAI21_X1_LVT i_0_0_38( + .A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_0), .ZN(n_0_25) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[25]_reg ( + .CK(clk), .E(n_0_25), .GCK(n_0_55), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[25][31] ( + .CK(n_0_55), .D(registers[31]), .Q(registers_25__ap[31]), .QN(), .SE(dftIn), + .SI(registers_27__ap[31]) + ); + AOI22_X1_LVT i_1_0_1308( + .A1(registers_13__ap[31]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[31]), + .ZN(n_1_0_1244) + ); + OAI21_X1_LVT i_0_0_52( + .A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_5), .ZN(n_0_15) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[15]_reg ( + .CK(clk), .E(n_0_15), .GCK(n_0_45), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[15][31] ( + .CK(n_0_45), .D(registers[31]), .Q(registers_15__ap[31]), .QN(), .SE(dftIn), + .SI(registers_13__ap[31]) + ); + NOR2_X1_LVT i_1_0_1350( + .A1(n_1_0_1301), .A2(n_1_0_1292), .ZN(n_1_0_1286) + ); + NOR2_X1_LVT i_1_0_1322( + .A1(n_1_0_1301), .A2(n_1_0_1288), .ZN(n_1_0_1258) + ); + OAI21_X1_LVT i_0_0_53( + .A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_5), .ZN(n_0_14) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[14]_reg ( + .CK(clk), .E(n_0_14), .GCK(n_0_44), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[14][31] ( + .CK(n_0_44), .D(registers[31]), .Q(registers_14__ap[31]), .QN(), .SE(dftIn), + .SI(registers_15__ap[31]) + ); + AOI22_X1_LVT i_1_0_1307( + .A1(registers_15__ap[31]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[31]), + .ZN(n_1_0_1243) + ); + NAND3_X1_LVT i_1_0_1306( + .A1(n_1_0_1245), .A2(n_1_0_1244), .A3(n_1_0_1243), .ZN(n_1_0_1242) + ); + NOR2_X1_LVT i_1_0_1321( + .A1(n_1_0_1298), .A2(n_1_0_1275), .ZN(n_1_0_1257) + ); + OAI21_X1_LVT i_0_0_71( + .A(n_0_0_16), .B1(n_0_0_13), .B2(n_0_0_11), .ZN(n_0_3) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[3]_reg ( + .CK(clk), .E(n_0_3), .GCK(n_0_33), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[3][31] ( + .CK(n_0_33), .D(registers[31]), .Q(registers_3__ap[31]), .QN(), .SE(dftIn), + .SI(registers_9__ap[31]) + ); + OAI21_X1_LVT i_0_0_73( + .A(n_0_0_16), .B1(n_0_0_13), .B2(n_0_0_12), .ZN(n_0_2) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[2]_reg ( + .CK(clk), .E(n_0_2), .GCK(n_0_32), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[2][31] ( + .CK(n_0_32), .D(registers[31]), .Q(registers_2__ap[31]), .QN(), .SE(dftIn), + .SI(registers_25__ap[31]) + ); + NOR4_X1_LVT i_1_0_1332( + .A1(n_1_0_1298), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), .ZN(n_1_0_1268) + ); + AOI221_X1_LVT i_1_0_1305( + .A(n_1_0_1242), .B1(n_1_0_1257), .B2(registers_3__ap[31]), .C1(registers_2__ap[31]), + .C2(n_1_0_1268), .ZN(n_1_0_1241) + ); + NAND4_X1_LVT i_1_0_1304( + .A1(n_1_0_1256), .A2(n_1_0_1251), .A3(n_1_0_1246), .A4(n_1_0_1241), .ZN(RRs1[31]) + ); + AND2_X1_LVT i_0_0_30( + .A1(n_0_0_16), .A2(WRd[30]), .ZN(registers[30]) + ); + SDFF_X1_LVT \registers_reg[28][30] ( + .CK(n_0_58), .D(registers[30]), .Q(registers_28__ap[30]), .QN(), .SE(dftIn), + .SI(registers_2__ap[31]) + ); + SDFF_X1_LVT \registers_reg[17][30] ( + .CK(n_0_47), .D(registers[30]), .Q(registers_17__ap[30]), .QN(), .SE(dftIn), + .SI(registers_20__ap[31]) + ); + AOI22_X1_LVT i_1_0_1300( + .A1(registers_28__ap[30]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[30]), + .ZN(n_1_0_1237) + ); + SDFF_X1_LVT \registers_reg[16][30] ( + .CK(n_0_46), .D(registers[30]), .Q(registers_16__ap[30]), .QN(), .SE(dftIn), + .SI(registers_14__ap[31]) + ); + SDFF_X1_LVT \registers_reg[31][30] ( + .CK(n_0_61), .D(registers[30]), .Q(registers_31__ap[30]), .QN(), .SE(dftIn), + .SI(registers_3__ap[31]) + ); + AOI22_X1_LVT i_1_0_1303( + .A1(registers_16__ap[30]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[30]), + .ZN(n_1_0_1240) + ); + SDFF_X1_LVT \registers_reg[6][30] ( + .CK(n_0_36), .D(registers[30]), .Q(registers_6__ap[30]), .QN(), .SE(dftIn), + .SI(registers_31__ap[30]) + ); + SDFF_X1_LVT \registers_reg[1][30] ( + .CK(n_0_0), .D(registers[30]), .Q(registers_1__ap[30]), .QN(), .SE(dftIn), + .SI(registers_17__ap[30]) + ); + AOI22_X1_LVT i_1_0_1299( + .A1(registers_6__ap[30]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[30]), + .ZN(n_1_0_1236) + ); + SDFF_X1_LVT \registers_reg[23][30] ( + .CK(n_0_53), .D(registers[30]), .Q(registers_23__ap[30]), .QN(), .SE(dftIn), + .SI(registers_1__ap[30]) + ); + SDFF_X1_LVT \registers_reg[7][30] ( + .CK(n_0_37), .D(registers[30]), .Q(registers_7__ap[30]), .QN(), .SE(dftIn), + .SI(registers_6__ap[30]) + ); + AOI22_X1_LVT i_1_0_1302( + .A1(registers_23__ap[30]), .A2(n_1_0_1264), .B1(n_1_0_1263), .B2(registers_7__ap[30]), + .ZN(n_1_0_1239) + ); + INV_X1_LVT i_1_0_1301( + .A(n_1_0_1239), .ZN(n_1_0_1238) + ); + SDFF_X1_LVT \registers_reg[19][30] ( + .CK(n_0_49), .D(registers[30]), .Q(registers_19__ap[30]), .QN(), .SE(dftIn), + .SI(registers_23__ap[30]) + ); + SDFF_X1_LVT \registers_reg[5][30] ( + .CK(n_0_35), .D(registers[30]), .Q(registers_5__ap[30]), .QN(), .SE(dftIn), + .SI(registers_7__ap[30]) + ); + AOI221_X1_LVT i_1_0_1298( + .A(n_1_0_1238), .B1(n_1_0_1295), .B2(registers_19__ap[30]), .C1(registers_5__ap[30]), + .C2(n_1_0_1273), .ZN(n_1_0_1235) + ); + SDFF_X1_LVT \registers_reg[10][30] ( + .CK(n_0_40), .D(registers[30]), .Q(registers_10__ap[30]), .QN(), .SE(dftIn), + .SI(registers_16__ap[30]) + ); + SDFF_X1_LVT \registers_reg[26][30] ( + .CK(n_0_56), .D(registers[30]), .Q(registers_26__ap[30]), .QN(), .SE(dftIn), + .SI(registers_28__ap[30]) + ); + SDFF_X1_LVT \registers_reg[8][30] ( + .CK(n_0_38), .D(registers[30]), .Q(registers_8__ap[30]), .QN(), .SE(dftIn), + .SI(registers_5__ap[30]) + ); + AOI222_X1_LVT i_1_0_1297( + .A1(registers_10__ap[30]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[30]), + .C1(registers_8__ap[30]), .C2(n_1_0_1282), .ZN(n_1_0_1234) + ); + NAND4_X1_LVT i_1_0_1296( + .A1(n_1_0_1240), .A2(n_1_0_1236), .A3(n_1_0_1235), .A4(n_1_0_1234), .ZN(n_1_0_1233) + ); + SDFF_X1_LVT \registers_reg[9][30] ( + .CK(n_0_39), .D(registers[30]), .Q(registers_9__ap[30]), .QN(), .SE(dftIn), + .SI(registers_8__ap[30]) + ); + SDFF_X1_LVT \registers_reg[29][30] ( + .CK(n_0_59), .D(registers[30]), .Q(registers_29__ap[30]), .QN(), .SE(dftIn), + .SI(registers_26__ap[30]) + ); + AOI221_X1_LVT i_1_0_1295( + .A(n_1_0_1233), .B1(n_1_0_1291), .B2(registers_9__ap[30]), .C1(registers_29__ap[30]), + .C2(n_1_0_1276), .ZN(n_1_0_1232) + ); + SDFF_X1_LVT \registers_reg[18][30] ( + .CK(n_0_48), .D(registers[30]), .Q(registers_18__ap[30]), .QN(), .SE(dftIn), + .SI(registers_19__ap[30]) + ); + SDFF_X1_LVT \registers_reg[30][30] ( + .CK(n_0_60), .D(registers[30]), .Q(registers_30__ap[30]), .QN(), .SE(dftIn), + .SI(registers_29__ap[30]) + ); + AOI22_X1_LVT i_1_0_1294( + .A1(registers_18__ap[30]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[30]), + .ZN(n_1_0_1231) + ); + SDFF_X1_LVT \registers_reg[20][30] ( + .CK(n_0_50), .D(registers[30]), .Q(registers_20__ap[30]), .QN(), .SE(dftIn), + .SI(registers_18__ap[30]) + ); + SDFF_X1_LVT \registers_reg[4][30] ( + .CK(n_0_34), .D(registers[30]), .Q(registers_4__ap[30]), .QN(), .SE(dftIn), + .SI(registers_9__ap[30]) + ); + AOI22_X1_LVT i_1_0_1293( + .A1(registers_20__ap[30]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[30]), + .ZN(n_1_0_1230) + ); + SDFF_X1_LVT \registers_reg[22][30] ( + .CK(n_0_52), .D(registers[30]), .Q(registers_22__ap[30]), .QN(), .SE(dftIn), + .SI(registers_20__ap[30]) + ); + SDFF_X1_LVT \registers_reg[21][30] ( + .CK(n_0_51), .D(registers[30]), .Q(registers_21__ap[30]), .QN(), .SE(dftIn), + .SI(registers_22__ap[30]) + ); + AOI22_X1_LVT i_1_0_1292( + .A1(registers_22__ap[30]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[30]), + .ZN(n_1_0_1229) + ); + NAND3_X1_LVT i_1_0_1291( + .A1(n_1_0_1231), .A2(n_1_0_1230), .A3(n_1_0_1229), .ZN(n_1_0_1228) + ); + SDFF_X1_LVT \registers_reg[24][30] ( + .CK(n_0_54), .D(registers[30]), .Q(registers_24__ap[30]), .QN(), .SE(dftIn), + .SI(registers_30__ap[30]) + ); + SDFF_X1_LVT \registers_reg[12][30] ( + .CK(n_0_42), .D(registers[30]), .Q(registers_12__ap[30]), .QN(), .SE(dftIn), + .SI(registers_10__ap[30]) + ); + AOI221_X1_LVT i_1_0_1290( + .A(n_1_0_1228), .B1(n_1_0_1289), .B2(registers_24__ap[30]), .C1(registers_12__ap[30]), + .C2(n_1_0_1260), .ZN(n_1_0_1227) + ); + SDFF_X1_LVT \registers_reg[27][30] ( + .CK(n_0_57), .D(registers[30]), .Q(registers_27__ap[30]), .QN(), .SE(dftIn), + .SI(registers_24__ap[30]) + ); + SDFF_X1_LVT \registers_reg[11][30] ( + .CK(n_0_41), .D(registers[30]), .Q(registers_11__ap[30]), .QN(), .SE(dftIn), + .SI(registers_12__ap[30]) + ); + AOI22_X1_LVT i_1_0_1289( + .A1(registers_27__ap[30]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[30]), + .ZN(n_1_0_1226) + ); + SDFF_X1_LVT \registers_reg[13][30] ( + .CK(n_0_43), .D(registers[30]), .Q(registers_13__ap[30]), .QN(), .SE(dftIn), + .SI(registers_11__ap[30]) + ); + SDFF_X1_LVT \registers_reg[25][30] ( + .CK(n_0_55), .D(registers[30]), .Q(registers_25__ap[30]), .QN(), .SE(dftIn), + .SI(registers_27__ap[30]) + ); + AOI22_X1_LVT i_1_0_1288( + .A1(registers_13__ap[30]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[30]), + .ZN(n_1_0_1225) + ); + SDFF_X1_LVT \registers_reg[15][30] ( + .CK(n_0_45), .D(registers[30]), .Q(registers_15__ap[30]), .QN(), .SE(dftIn), + .SI(registers_13__ap[30]) + ); + SDFF_X1_LVT \registers_reg[14][30] ( + .CK(n_0_44), .D(registers[30]), .Q(registers_14__ap[30]), .QN(), .SE(dftIn), + .SI(registers_15__ap[30]) + ); + AOI22_X1_LVT i_1_0_1287( + .A1(registers_15__ap[30]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[30]), + .ZN(n_1_0_1224) + ); + NAND3_X1_LVT i_1_0_1286( + .A1(n_1_0_1226), .A2(n_1_0_1225), .A3(n_1_0_1224), .ZN(n_1_0_1223) + ); + SDFF_X1_LVT \registers_reg[3][30] ( + .CK(n_0_33), .D(registers[30]), .Q(registers_3__ap[30]), .QN(), .SE(dftIn), + .SI(registers_4__ap[30]) + ); + SDFF_X1_LVT \registers_reg[2][30] ( + .CK(n_0_32), .D(registers[30]), .Q(registers_2__ap[30]), .QN(), .SE(dftIn), + .SI(registers_25__ap[30]) + ); + AOI221_X1_LVT i_1_0_1285( + .A(n_1_0_1223), .B1(n_1_0_1257), .B2(registers_3__ap[30]), .C1(registers_2__ap[30]), + .C2(n_1_0_1268), .ZN(n_1_0_1222) + ); + NAND4_X1_LVT i_1_0_1284( + .A1(n_1_0_1237), .A2(n_1_0_1232), .A3(n_1_0_1227), .A4(n_1_0_1222), .ZN(RRs1[30]) + ); + AND2_X1_LVT i_0_0_29( + .A1(n_0_0_16), .A2(WRd[29]), .ZN(registers[29]) + ); + SDFF_X1_LVT \registers_reg[28][29] ( + .CK(n_0_58), .D(registers[29]), .Q(registers_28__ap[29]), .QN(), .SE(dftIn), + .SI(registers_2__ap[30]) + ); + SDFF_X1_LVT \registers_reg[8][29] ( + .CK(n_0_38), .D(registers[29]), .Q(registers_8__ap[29]), .QN(), .SE(dftIn), + .SI(registers_3__ap[30]) + ); + AOI22_X1_LVT i_1_0_1282( + .A1(registers_28__ap[29]), .A2(n_1_0_1283), .B1(n_1_0_1282), .B2(registers_8__ap[29]), + .ZN(n_1_0_1220) + ); + SDFF_X1_LVT \registers_reg[31][29] ( + .CK(n_0_61), .D(registers[29]), .Q(registers_31__ap[29]), .QN(), .SE(dftIn), + .SI(registers_8__ap[29]) + ); + SDFF_X1_LVT \registers_reg[7][29] ( + .CK(n_0_37), .D(registers[29]), .Q(registers_7__ap[29]), .QN(), .SE(dftIn), + .SI(registers_31__ap[29]) + ); + AOI22_X1_LVT i_1_0_1283( + .A1(registers_31__ap[29]), .A2(n_1_0_1266), .B1(n_1_0_1263), .B2(registers_7__ap[29]), + .ZN(n_1_0_1221) + ); + SDFF_X1_LVT \registers_reg[24][29] ( + .CK(n_0_54), .D(registers[29]), .Q(registers_24__ap[29]), .QN(), .SE(dftIn), + .SI(registers_28__ap[29]) + ); + SDFF_X1_LVT \registers_reg[20][29] ( + .CK(n_0_50), .D(registers[29]), .Q(registers_20__ap[29]), .QN(), .SE(dftIn), + .SI(registers_21__ap[30]) + ); + AOI22_X1_LVT i_1_0_1281( + .A1(registers_24__ap[29]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[29]), + .ZN(n_1_0_1219) + ); + SDFF_X1_LVT \registers_reg[19][29] ( + .CK(n_0_49), .D(registers[29]), .Q(registers_19__ap[29]), .QN(), .SE(dftIn), + .SI(registers_20__ap[29]) + ); + SDFF_X1_LVT \registers_reg[4][29] ( + .CK(n_0_34), .D(registers[29]), .Q(registers_4__ap[29]), .QN(), .SE(dftIn), + .SI(registers_7__ap[29]) + ); + AOI22_X1_LVT i_1_0_1280( + .A1(registers_19__ap[29]), .A2(n_1_0_1295), .B1(n_1_0_1278), .B2(registers_4__ap[29]), + .ZN(n_1_0_1218) + ); + NAND3_X1_LVT i_1_0_1279( + .A1(n_1_0_1221), .A2(n_1_0_1219), .A3(n_1_0_1218), .ZN(n_1_0_1217) + ); + SDFF_X1_LVT \registers_reg[23][29] ( + .CK(n_0_53), .D(registers[29]), .Q(registers_23__ap[29]), .QN(), .SE(dftIn), + .SI(registers_19__ap[29]) + ); + SDFF_X1_LVT \registers_reg[29][29] ( + .CK(n_0_59), .D(registers[29]), .Q(registers_29__ap[29]), .QN(), .SE(dftIn), + .SI(registers_24__ap[29]) + ); + AOI221_X1_LVT i_1_0_1278( + .A(n_1_0_1217), .B1(n_1_0_1264), .B2(registers_23__ap[29]), .C1(registers_29__ap[29]), + .C2(n_1_0_1276), .ZN(n_1_0_1216) + ); + SDFF_X1_LVT \registers_reg[10][29] ( + .CK(n_0_40), .D(registers[29]), .Q(registers_10__ap[29]), .QN(), .SE(dftIn), + .SI(registers_14__ap[30]) + ); + SDFF_X1_LVT \registers_reg[26][29] ( + .CK(n_0_56), .D(registers[29]), .Q(registers_26__ap[29]), .QN(), .SE(dftIn), + .SI(registers_29__ap[29]) + ); + SDFF_X1_LVT \registers_reg[25][29] ( + .CK(n_0_55), .D(registers[29]), .Q(registers_25__ap[29]), .QN(), .SE(dftIn), + .SI(registers_26__ap[29]) + ); + AOI222_X1_LVT i_1_0_1277( + .A1(registers_10__ap[29]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[29]), + .C1(registers_25__ap[29]), .C2(n_1_0_1269), .ZN(n_1_0_1215) + ); + NAND3_X1_LVT i_1_0_1276( + .A1(n_1_0_1220), .A2(n_1_0_1216), .A3(n_1_0_1215), .ZN(n_1_0_1214) + ); + SDFF_X1_LVT \registers_reg[21][29] ( + .CK(n_0_51), .D(registers[29]), .Q(registers_21__ap[29]), .QN(), .SE(dftIn), + .SI(registers_23__ap[29]) + ); + SDFF_X1_LVT \registers_reg[13][29] ( + .CK(n_0_43), .D(registers[29]), .Q(registers_13__ap[29]), .QN(), .SE(dftIn), + .SI(registers_10__ap[29]) + ); + AOI221_X1_LVT i_1_0_1275( + .A(n_1_0_1214), .B1(n_1_0_1259), .B2(registers_21__ap[29]), .C1(registers_13__ap[29]), + .C2(n_1_0_1277), .ZN(n_1_0_1213) + ); + SDFF_X1_LVT \registers_reg[18][29] ( + .CK(n_0_48), .D(registers[29]), .Q(registers_18__ap[29]), .QN(), .SE(dftIn), + .SI(registers_21__ap[29]) + ); + SDFF_X1_LVT \registers_reg[30][29] ( + .CK(n_0_60), .D(registers[29]), .Q(registers_30__ap[29]), .QN(), .SE(dftIn), + .SI(registers_25__ap[29]) + ); + AOI22_X1_LVT i_1_0_1274( + .A1(registers_18__ap[29]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[29]), + .ZN(n_1_0_1212) + ); + SDFF_X1_LVT \registers_reg[17][29] ( + .CK(n_0_47), .D(registers[29]), .Q(registers_17__ap[29]), .QN(), .SE(dftIn), + .SI(registers_18__ap[29]) + ); + SDFF_X1_LVT \registers_reg[12][29] ( + .CK(n_0_42), .D(registers[29]), .Q(registers_12__ap[29]), .QN(), .SE(dftIn), + .SI(registers_13__ap[29]) + ); + AOI22_X1_LVT i_1_0_1273( + .A1(registers_17__ap[29]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[29]), + .ZN(n_1_0_1211) + ); + SDFF_X1_LVT \registers_reg[15][29] ( + .CK(n_0_45), .D(registers[29]), .Q(registers_15__ap[29]), .QN(), .SE(dftIn), + .SI(registers_12__ap[29]) + ); + SDFF_X1_LVT \registers_reg[16][29] ( + .CK(n_0_46), .D(registers[29]), .Q(registers_16__ap[29]), .QN(), .SE(dftIn), + .SI(registers_15__ap[29]) + ); + AOI22_X1_LVT i_1_0_1272( + .A1(registers_15__ap[29]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[29]), + .ZN(n_1_0_1210) + ); + NAND3_X1_LVT i_1_0_1271( + .A1(n_1_0_1212), .A2(n_1_0_1211), .A3(n_1_0_1210), .ZN(n_1_0_1209) + ); + SDFF_X1_LVT \registers_reg[22][29] ( + .CK(n_0_52), .D(registers[29]), .Q(registers_22__ap[29]), .QN(), .SE(dftIn), + .SI(registers_17__ap[29]) + ); + SDFF_X1_LVT \registers_reg[5][29] ( + .CK(n_0_35), .D(registers[29]), .Q(registers_5__ap[29]), .QN(), .SE(dftIn), + .SI(registers_4__ap[29]) + ); + AOI221_X1_LVT i_1_0_1270( + .A(n_1_0_1209), .B1(n_1_0_1294), .B2(registers_22__ap[29]), .C1(registers_5__ap[29]), + .C2(n_1_0_1273), .ZN(n_1_0_1208) + ); + SDFF_X1_LVT \registers_reg[9][29] ( + .CK(n_0_39), .D(registers[29]), .Q(registers_9__ap[29]), .QN(), .SE(dftIn), + .SI(registers_5__ap[29]) + ); + SDFF_X1_LVT \registers_reg[1][29] ( + .CK(n_0_0), .D(registers[29]), .Q(registers_1__ap[29]), .QN(), .SE(dftIn), + .SI(registers_22__ap[29]) + ); + AOI22_X1_LVT i_1_0_1269( + .A1(registers_9__ap[29]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[29]), + .ZN(n_1_0_1207) + ); + SDFF_X1_LVT \registers_reg[6][29] ( + .CK(n_0_36), .D(registers[29]), .Q(registers_6__ap[29]), .QN(), .SE(dftIn), + .SI(registers_9__ap[29]) + ); + SDFF_X1_LVT \registers_reg[14][29] ( + .CK(n_0_44), .D(registers[29]), .Q(registers_14__ap[29]), .QN(), .SE(dftIn), + .SI(registers_16__ap[29]) + ); + AOI22_X1_LVT i_1_0_1268( + .A1(registers_6__ap[29]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[29]), + .ZN(n_1_0_1206) + ); + SDFF_X1_LVT \registers_reg[27][29] ( + .CK(n_0_57), .D(registers[29]), .Q(registers_27__ap[29]), .QN(), .SE(dftIn), + .SI(registers_30__ap[29]) + ); + SDFF_X1_LVT \registers_reg[11][29] ( + .CK(n_0_41), .D(registers[29]), .Q(registers_11__ap[29]), .QN(), .SE(dftIn), + .SI(registers_14__ap[29]) + ); + AOI22_X1_LVT i_1_0_1267( + .A1(registers_27__ap[29]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[29]), + .ZN(n_1_0_1205) + ); + NAND3_X1_LVT i_1_0_1266( + .A1(n_1_0_1207), .A2(n_1_0_1206), .A3(n_1_0_1205), .ZN(n_1_0_1204) + ); + SDFF_X1_LVT \registers_reg[3][29] ( + .CK(n_0_33), .D(registers[29]), .Q(registers_3__ap[29]), .QN(), .SE(dftIn), + .SI(registers_6__ap[29]) + ); + SDFF_X1_LVT \registers_reg[2][29] ( + .CK(n_0_32), .D(registers[29]), .Q(registers_2__ap[29]), .QN(), .SE(dftIn), + .SI(registers_27__ap[29]) + ); + AOI221_X1_LVT i_1_0_1265( + .A(n_1_0_1204), .B1(n_1_0_1257), .B2(registers_3__ap[29]), .C1(registers_2__ap[29]), + .C2(n_1_0_1268), .ZN(n_1_0_1203) + ); + NAND3_X1_LVT i_1_0_1264( + .A1(n_1_0_1213), .A2(n_1_0_1208), .A3(n_1_0_1203), .ZN(RRs1[29]) + ); + AND2_X1_LVT i_0_0_28( + .A1(n_0_0_16), .A2(WRd[28]), .ZN(registers[28]) + ); + SDFF_X1_LVT \registers_reg[15][28] ( + .CK(n_0_45), .D(registers[28]), .Q(registers_15__ap[28]), .QN(), .SE(dftIn), + .SI(registers_11__ap[29]) + ); + SDFF_X1_LVT \registers_reg[26][28] ( + .CK(n_0_56), .D(registers[28]), .Q(registers_26__ap[28]), .QN(), .SE(dftIn), + .SI(registers_2__ap[29]) + ); + SDFF_X1_LVT \registers_reg[22][28] ( + .CK(n_0_52), .D(registers[28]), .Q(registers_22__ap[28]), .QN(), .SE(dftIn), + .SI(registers_1__ap[29]) + ); + AOI222_X1_LVT i_1_0_1263( + .A1(registers_15__ap[28]), .A2(n_1_0_1286), .B1(n_1_0_1285), .B2(registers_26__ap[28]), + .C1(registers_22__ap[28]), .C2(n_1_0_1294), .ZN(n_1_0_1202) + ); + SDFF_X1_LVT \registers_reg[5][28] ( + .CK(n_0_35), .D(registers[28]), .Q(registers_5__ap[28]), .QN(), .SE(dftIn), + .SI(registers_3__ap[29]) + ); + SDFF_X1_LVT \registers_reg[12][28] ( + .CK(n_0_42), .D(registers[28]), .Q(registers_12__ap[28]), .QN(), .SE(dftIn), + .SI(registers_15__ap[28]) + ); + AOI22_X1_LVT i_1_0_1262( + .A1(registers_5__ap[28]), .A2(n_1_0_1273), .B1(n_1_0_1260), .B2(registers_12__ap[28]), + .ZN(n_1_0_1201) + ); + SDFF_X1_LVT \registers_reg[28][28] ( + .CK(n_0_58), .D(registers[28]), .Q(registers_28__ap[28]), .QN(), .SE(dftIn), + .SI(registers_26__ap[28]) + ); + SDFF_X1_LVT \registers_reg[14][28] ( + .CK(n_0_44), .D(registers[28]), .Q(registers_14__ap[28]), .QN(), .SE(dftIn), + .SI(registers_12__ap[28]) + ); + AOI22_X1_LVT i_1_0_1261( + .A1(registers_28__ap[28]), .A2(n_1_0_1283), .B1(n_1_0_1258), .B2(registers_14__ap[28]), + .ZN(n_1_0_1200) + ); + SDFF_X1_LVT \registers_reg[17][28] ( + .CK(n_0_47), .D(registers[28]), .Q(registers_17__ap[28]), .QN(), .SE(dftIn), + .SI(registers_22__ap[28]) + ); + SDFF_X1_LVT \registers_reg[2][28] ( + .CK(n_0_32), .D(registers[28]), .Q(registers_2__ap[28]), .QN(), .SE(dftIn), + .SI(registers_28__ap[28]) + ); + AOI22_X1_LVT i_1_0_1260( + .A1(registers_17__ap[28]), .A2(n_1_0_1271), .B1(n_1_0_1268), .B2(registers_2__ap[28]), + .ZN(n_1_0_1199) + ); + NAND3_X1_LVT i_1_0_1259( + .A1(n_1_0_1201), .A2(n_1_0_1200), .A3(n_1_0_1199), .ZN(n_1_0_1198) + ); + SDFF_X1_LVT \registers_reg[9][28] ( + .CK(n_0_39), .D(registers[28]), .Q(registers_9__ap[28]), .QN(), .SE(dftIn), + .SI(registers_5__ap[28]) + ); + SDFF_X1_LVT \registers_reg[29][28] ( + .CK(n_0_59), .D(registers[28]), .Q(registers_29__ap[28]), .QN(), .SE(dftIn), + .SI(registers_2__ap[28]) + ); + AOI221_X1_LVT i_1_0_1258( + .A(n_1_0_1198), .B1(n_1_0_1291), .B2(registers_9__ap[28]), .C1(registers_29__ap[28]), + .C2(n_1_0_1276), .ZN(n_1_0_1197) + ); + SDFF_X1_LVT \registers_reg[13][28] ( + .CK(n_0_43), .D(registers[28]), .Q(registers_13__ap[28]), .QN(), .SE(dftIn), + .SI(registers_14__ap[28]) + ); + SDFF_X1_LVT \registers_reg[25][28] ( + .CK(n_0_55), .D(registers[28]), .Q(registers_25__ap[28]), .QN(), .SE(dftIn), + .SI(registers_29__ap[28]) + ); + AOI22_X1_LVT i_1_0_1257( + .A1(registers_13__ap[28]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[28]), + .ZN(n_1_0_1196) + ); + NAND3_X1_LVT i_1_0_1256( + .A1(n_1_0_1202), .A2(n_1_0_1197), .A3(n_1_0_1196), .ZN(n_1_0_1195) + ); + SDFF_X1_LVT \registers_reg[4][28] ( + .CK(n_0_34), .D(registers[28]), .Q(registers_4__ap[28]), .QN(), .SE(dftIn), + .SI(registers_9__ap[28]) + ); + SDFF_X1_LVT \registers_reg[20][28] ( + .CK(n_0_50), .D(registers[28]), .Q(registers_20__ap[28]), .QN(), .SE(dftIn), + .SI(registers_17__ap[28]) + ); + AOI221_X1_LVT i_1_0_1255( + .A(n_1_0_1195), .B1(n_1_0_1278), .B2(registers_4__ap[28]), .C1(registers_20__ap[28]), + .C2(n_1_0_1281), .ZN(n_1_0_1194) + ); + SDFF_X1_LVT \registers_reg[1][28] ( + .CK(n_0_0), .D(registers[28]), .Q(registers_1__ap[28]), .QN(), .SE(dftIn), + .SI(registers_20__ap[28]) + ); + SDFF_X1_LVT \registers_reg[23][28] ( + .CK(n_0_53), .D(registers[28]), .Q(registers_23__ap[28]), .QN(), .SE(dftIn), + .SI(registers_1__ap[28]) + ); + AOI22_X1_LVT i_1_0_1254( + .A1(registers_1__ap[28]), .A2(n_1_0_1274), .B1(n_1_0_1264), .B2(registers_23__ap[28]), + .ZN(n_1_0_1193) + ); + SDFF_X1_LVT \registers_reg[10][28] ( + .CK(n_0_40), .D(registers[28]), .Q(registers_10__ap[28]), .QN(), .SE(dftIn), + .SI(registers_13__ap[28]) + ); + SDFF_X1_LVT \registers_reg[21][28] ( + .CK(n_0_51), .D(registers[28]), .Q(registers_21__ap[28]), .QN(), .SE(dftIn), + .SI(registers_23__ap[28]) + ); + AOI22_X1_LVT i_1_0_1253( + .A1(registers_10__ap[28]), .A2(n_1_0_1287), .B1(n_1_0_1259), .B2(registers_21__ap[28]), + .ZN(n_1_0_1192) + ); + SDFF_X1_LVT \registers_reg[6][28] ( + .CK(n_0_36), .D(registers[28]), .Q(registers_6__ap[28]), .QN(), .SE(dftIn), + .SI(registers_4__ap[28]) + ); + SDFF_X1_LVT \registers_reg[30][28] ( + .CK(n_0_60), .D(registers[28]), .Q(registers_30__ap[28]), .QN(), .SE(dftIn), + .SI(registers_25__ap[28]) + ); + AOI22_X1_LVT i_1_0_1252( + .A1(registers_6__ap[28]), .A2(n_1_0_1300), .B1(n_1_0_1272), .B2(registers_30__ap[28]), + .ZN(n_1_0_1191) + ); + NAND3_X1_LVT i_1_0_1251( + .A1(n_1_0_1193), .A2(n_1_0_1192), .A3(n_1_0_1191), .ZN(n_1_0_1190) + ); + SDFF_X1_LVT \registers_reg[8][28] ( + .CK(n_0_38), .D(registers[28]), .Q(registers_8__ap[28]), .QN(), .SE(dftIn), + .SI(registers_6__ap[28]) + ); + SDFF_X1_LVT \registers_reg[24][28] ( + .CK(n_0_54), .D(registers[28]), .Q(registers_24__ap[28]), .QN(), .SE(dftIn), + .SI(registers_30__ap[28]) + ); + AOI221_X1_LVT i_1_0_1250( + .A(n_1_0_1190), .B1(n_1_0_1282), .B2(registers_8__ap[28]), .C1(registers_24__ap[28]), + .C2(n_1_0_1289), .ZN(n_1_0_1189) + ); + SDFF_X1_LVT \registers_reg[16][28] ( + .CK(n_0_46), .D(registers[28]), .Q(registers_16__ap[28]), .QN(), .SE(dftIn), + .SI(registers_10__ap[28]) + ); + SDFF_X1_LVT \registers_reg[3][28] ( + .CK(n_0_33), .D(registers[28]), .Q(registers_3__ap[28]), .QN(), .SE(dftIn), + .SI(registers_8__ap[28]) + ); + AOI22_X1_LVT i_1_0_1249( + .A1(registers_16__ap[28]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[28]), + .ZN(n_1_0_1188) + ); + SDFF_X1_LVT \registers_reg[11][28] ( + .CK(n_0_41), .D(registers[28]), .Q(registers_11__ap[28]), .QN(), .SE(dftIn), + .SI(registers_16__ap[28]) + ); + SDFF_X1_LVT \registers_reg[31][28] ( + .CK(n_0_61), .D(registers[28]), .Q(registers_31__ap[28]), .QN(), .SE(dftIn), + .SI(registers_3__ap[28]) + ); + AOI22_X1_LVT i_1_0_1248( + .A1(registers_11__ap[28]), .A2(n_1_0_1270), .B1(n_1_0_1266), .B2(registers_31__ap[28]), + .ZN(n_1_0_1187) + ); + SDFF_X1_LVT \registers_reg[27][28] ( + .CK(n_0_57), .D(registers[28]), .Q(registers_27__ap[28]), .QN(), .SE(dftIn), + .SI(registers_24__ap[28]) + ); + SDFF_X1_LVT \registers_reg[7][28] ( + .CK(n_0_37), .D(registers[28]), .Q(registers_7__ap[28]), .QN(), .SE(dftIn), + .SI(registers_31__ap[28]) + ); + AOI22_X1_LVT i_1_0_1247( + .A1(registers_27__ap[28]), .A2(n_1_0_1279), .B1(n_1_0_1263), .B2(registers_7__ap[28]), + .ZN(n_1_0_1186) + ); + NAND3_X1_LVT i_1_0_1246( + .A1(n_1_0_1188), .A2(n_1_0_1187), .A3(n_1_0_1186), .ZN(n_1_0_1185) + ); + SDFF_X1_LVT \registers_reg[19][28] ( + .CK(n_0_49), .D(registers[28]), .Q(registers_19__ap[28]), .QN(), .SE(dftIn), + .SI(registers_21__ap[28]) + ); + SDFF_X1_LVT \registers_reg[18][28] ( + .CK(n_0_48), .D(registers[28]), .Q(registers_18__ap[28]), .QN(), .SE(dftIn), + .SI(registers_19__ap[28]) + ); + AOI221_X1_LVT i_1_0_1245( + .A(n_1_0_1185), .B1(n_1_0_1295), .B2(registers_19__ap[28]), .C1(registers_18__ap[28]), + .C2(n_1_0_1297), .ZN(n_1_0_1184) + ); + NAND3_X1_LVT i_1_0_1244( + .A1(n_1_0_1194), .A2(n_1_0_1189), .A3(n_1_0_1184), .ZN(RRs1[28]) + ); + AND2_X1_LVT i_0_0_27( + .A1(n_0_0_16), .A2(WRd[27]), .ZN(registers[27]) + ); + SDFF_X1_LVT \registers_reg[29][27] ( + .CK(n_0_59), .D(registers[27]), .Q(registers_29__ap[27]), .QN(), .SE(dftIn), + .SI(registers_27__ap[28]) + ); + SDFF_X1_LVT \registers_reg[2][27] ( + .CK(n_0_32), .D(registers[27]), .Q(registers_2__ap[27]), .QN(), .SE(dftIn), + .SI(registers_29__ap[27]) + ); + AOI22_X1_LVT i_1_0_1242( + .A1(registers_29__ap[27]), .A2(n_1_0_1276), .B1(n_1_0_1268), .B2(registers_2__ap[27]), + .ZN(n_1_0_1182) + ); + SDFF_X1_LVT \registers_reg[8][27] ( + .CK(n_0_38), .D(registers[27]), .Q(registers_8__ap[27]), .QN(), .SE(dftIn), + .SI(registers_7__ap[28]) + ); + SDFF_X1_LVT \registers_reg[25][27] ( + .CK(n_0_55), .D(registers[27]), .Q(registers_25__ap[27]), .QN(), .SE(dftIn), + .SI(registers_2__ap[27]) + ); + AOI22_X1_LVT i_1_0_1243( + .A1(registers_8__ap[27]), .A2(n_1_0_1282), .B1(n_1_0_1269), .B2(registers_25__ap[27]), + .ZN(n_1_0_1183) + ); + SDFF_X1_LVT \registers_reg[9][27] ( + .CK(n_0_39), .D(registers[27]), .Q(registers_9__ap[27]), .QN(), .SE(dftIn), + .SI(registers_8__ap[27]) + ); + SDFF_X1_LVT \registers_reg[7][27] ( + .CK(n_0_37), .D(registers[27]), .Q(registers_7__ap[27]), .QN(), .SE(dftIn), + .SI(registers_9__ap[27]) + ); + AOI22_X1_LVT i_1_0_1241( + .A1(registers_9__ap[27]), .A2(n_1_0_1291), .B1(n_1_0_1263), .B2(registers_7__ap[27]), + .ZN(n_1_0_1181) + ); + SDFF_X1_LVT \registers_reg[11][27] ( + .CK(n_0_41), .D(registers[27]), .Q(registers_11__ap[27]), .QN(), .SE(dftIn), + .SI(registers_11__ap[28]) + ); + SDFF_X1_LVT \registers_reg[16][27] ( + .CK(n_0_46), .D(registers[27]), .Q(registers_16__ap[27]), .QN(), .SE(dftIn), + .SI(registers_11__ap[27]) + ); + AOI22_X1_LVT i_1_0_1240( + .A1(registers_11__ap[27]), .A2(n_1_0_1270), .B1(n_1_0_1267), .B2(registers_16__ap[27]), + .ZN(n_1_0_1180) + ); + NAND3_X1_LVT i_1_0_1239( + .A1(n_1_0_1183), .A2(n_1_0_1181), .A3(n_1_0_1180), .ZN(n_1_0_1179) + ); + SDFF_X1_LVT \registers_reg[10][27] ( + .CK(n_0_40), .D(registers[27]), .Q(registers_10__ap[27]), .QN(), .SE(dftIn), + .SI(registers_16__ap[27]) + ); + SDFF_X1_LVT \registers_reg[6][27] ( + .CK(n_0_36), .D(registers[27]), .Q(registers_6__ap[27]), .QN(), .SE(dftIn), + .SI(registers_7__ap[27]) + ); + AOI221_X1_LVT i_1_0_1238( + .A(n_1_0_1179), .B1(n_1_0_1287), .B2(registers_10__ap[27]), .C1(registers_6__ap[27]), + .C2(n_1_0_1300), .ZN(n_1_0_1178) + ); + SDFF_X1_LVT \registers_reg[1][27] ( + .CK(n_0_0), .D(registers[27]), .Q(registers_1__ap[27]), .QN(), .SE(dftIn), + .SI(registers_18__ap[28]) + ); + SDFF_X1_LVT \registers_reg[30][27] ( + .CK(n_0_60), .D(registers[27]), .Q(registers_30__ap[27]), .QN(), .SE(dftIn), + .SI(registers_25__ap[27]) + ); + SDFF_X1_LVT \registers_reg[22][27] ( + .CK(n_0_52), .D(registers[27]), .Q(registers_22__ap[27]), .QN(), .SE(dftIn), + .SI(registers_1__ap[27]) + ); + AOI222_X1_LVT i_1_0_1237( + .A1(registers_1__ap[27]), .A2(n_1_0_1274), .B1(n_1_0_1272), .B2(registers_30__ap[27]), + .C1(registers_22__ap[27]), .C2(n_1_0_1294), .ZN(n_1_0_1177) + ); + NAND3_X1_LVT i_1_0_1236( + .A1(n_1_0_1182), .A2(n_1_0_1178), .A3(n_1_0_1177), .ZN(n_1_0_1176) + ); + SDFF_X1_LVT \registers_reg[5][27] ( + .CK(n_0_35), .D(registers[27]), .Q(registers_5__ap[27]), .QN(), .SE(dftIn), + .SI(registers_6__ap[27]) + ); + SDFF_X1_LVT \registers_reg[28][27] ( + .CK(n_0_58), .D(registers[27]), .Q(registers_28__ap[27]), .QN(), .SE(dftIn), + .SI(registers_30__ap[27]) + ); + AOI221_X1_LVT i_1_0_1235( + .A(n_1_0_1176), .B1(n_1_0_1273), .B2(registers_5__ap[27]), .C1(registers_28__ap[27]), + .C2(n_1_0_1283), .ZN(n_1_0_1175) + ); + SDFF_X1_LVT \registers_reg[4][27] ( + .CK(n_0_34), .D(registers[27]), .Q(registers_4__ap[27]), .QN(), .SE(dftIn), + .SI(registers_5__ap[27]) + ); + SDFF_X1_LVT \registers_reg[12][27] ( + .CK(n_0_42), .D(registers[27]), .Q(registers_12__ap[27]), .QN(), .SE(dftIn), + .SI(registers_10__ap[27]) + ); + AOI22_X1_LVT i_1_0_1234( + .A1(registers_4__ap[27]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[27]), + .ZN(n_1_0_1174) + ); + SDFF_X1_LVT \registers_reg[19][27] ( + .CK(n_0_49), .D(registers[27]), .Q(registers_19__ap[27]), .QN(), .SE(dftIn), + .SI(registers_22__ap[27]) + ); + SDFF_X1_LVT \registers_reg[21][27] ( + .CK(n_0_51), .D(registers[27]), .Q(registers_21__ap[27]), .QN(), .SE(dftIn), + .SI(registers_19__ap[27]) + ); + AOI22_X1_LVT i_1_0_1233( + .A1(registers_19__ap[27]), .A2(n_1_0_1295), .B1(n_1_0_1259), .B2(registers_21__ap[27]), + .ZN(n_1_0_1173) + ); + SDFF_X1_LVT \registers_reg[24][27] ( + .CK(n_0_54), .D(registers[27]), .Q(registers_24__ap[27]), .QN(), .SE(dftIn), + .SI(registers_28__ap[27]) + ); + SDFF_X1_LVT \registers_reg[20][27] ( + .CK(n_0_50), .D(registers[27]), .Q(registers_20__ap[27]), .QN(), .SE(dftIn), + .SI(registers_21__ap[27]) + ); + AOI22_X1_LVT i_1_0_1232( + .A1(registers_24__ap[27]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[27]), + .ZN(n_1_0_1172) + ); + NAND3_X1_LVT i_1_0_1231( + .A1(n_1_0_1174), .A2(n_1_0_1173), .A3(n_1_0_1172), .ZN(n_1_0_1171) + ); + SDFF_X1_LVT \registers_reg[18][27] ( + .CK(n_0_48), .D(registers[27]), .Q(registers_18__ap[27]), .QN(), .SE(dftIn), + .SI(registers_20__ap[27]) + ); + SDFF_X1_LVT \registers_reg[26][27] ( + .CK(n_0_56), .D(registers[27]), .Q(registers_26__ap[27]), .QN(), .SE(dftIn), + .SI(registers_24__ap[27]) + ); + AOI221_X1_LVT i_1_0_1230( + .A(n_1_0_1171), .B1(n_1_0_1297), .B2(registers_18__ap[27]), .C1(registers_26__ap[27]), + .C2(n_1_0_1285), .ZN(n_1_0_1170) + ); + SDFF_X1_LVT \registers_reg[23][27] ( + .CK(n_0_53), .D(registers[27]), .Q(registers_23__ap[27]), .QN(), .SE(dftIn), + .SI(registers_18__ap[27]) + ); + SDFF_X1_LVT \registers_reg[3][27] ( + .CK(n_0_33), .D(registers[27]), .Q(registers_3__ap[27]), .QN(), .SE(dftIn), + .SI(registers_4__ap[27]) + ); + AOI22_X1_LVT i_1_0_1229( + .A1(registers_23__ap[27]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[27]), + .ZN(n_1_0_1169) + ); + SDFF_X1_LVT \registers_reg[13][27] ( + .CK(n_0_43), .D(registers[27]), .Q(registers_13__ap[27]), .QN(), .SE(dftIn), + .SI(registers_12__ap[27]) + ); + SDFF_X1_LVT \registers_reg[17][27] ( + .CK(n_0_47), .D(registers[27]), .Q(registers_17__ap[27]), .QN(), .SE(dftIn), + .SI(registers_23__ap[27]) + ); + AOI22_X1_LVT i_1_0_1228( + .A1(registers_13__ap[27]), .A2(n_1_0_1277), .B1(n_1_0_1271), .B2(registers_17__ap[27]), + .ZN(n_1_0_1168) + ); + SDFF_X1_LVT \registers_reg[15][27] ( + .CK(n_0_45), .D(registers[27]), .Q(registers_15__ap[27]), .QN(), .SE(dftIn), + .SI(registers_13__ap[27]) + ); + SDFF_X1_LVT \registers_reg[14][27] ( + .CK(n_0_44), .D(registers[27]), .Q(registers_14__ap[27]), .QN(), .SE(dftIn), + .SI(registers_15__ap[27]) + ); + AOI22_X1_LVT i_1_0_1227( + .A1(registers_15__ap[27]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[27]), + .ZN(n_1_0_1167) + ); + NAND3_X1_LVT i_1_0_1226( + .A1(n_1_0_1169), .A2(n_1_0_1168), .A3(n_1_0_1167), .ZN(n_1_0_1166) + ); + SDFF_X1_LVT \registers_reg[27][27] ( + .CK(n_0_57), .D(registers[27]), .Q(registers_27__ap[27]), .QN(), .SE(dftIn), + .SI(registers_26__ap[27]) + ); + SDFF_X1_LVT \registers_reg[31][27] ( + .CK(n_0_61), .D(registers[27]), .Q(registers_31__ap[27]), .QN(), .SE(dftIn), + .SI(registers_3__ap[27]) + ); + AOI221_X1_LVT i_1_0_1225( + .A(n_1_0_1166), .B1(n_1_0_1279), .B2(registers_27__ap[27]), .C1(registers_31__ap[27]), + .C2(n_1_0_1266), .ZN(n_1_0_1165) + ); + NAND3_X1_LVT i_1_0_1224( + .A1(n_1_0_1175), .A2(n_1_0_1170), .A3(n_1_0_1165), .ZN(RRs1[27]) + ); + AND2_X1_LVT i_0_0_26( + .A1(n_0_0_16), .A2(WRd[26]), .ZN(registers[26]) + ); + SDFF_X1_LVT \registers_reg[18][26] ( + .CK(n_0_48), .D(registers[26]), .Q(registers_18__ap[26]), .QN(), .SE(dftIn), + .SI(registers_17__ap[27]) + ); + SDFF_X1_LVT \registers_reg[22][26] ( + .CK(n_0_52), .D(registers[26]), .Q(registers_22__ap[26]), .QN(), .SE(dftIn), + .SI(registers_18__ap[26]) + ); + SDFF_X1_LVT \registers_reg[1][26] ( + .CK(n_0_0), .D(registers[26]), .Q(registers_1__ap[26]), .QN(), .SE(dftIn), + .SI(registers_22__ap[26]) + ); + AOI222_X1_LVT i_1_0_1223( + .A1(registers_18__ap[26]), .A2(n_1_0_1297), .B1(n_1_0_1294), .B2(registers_22__ap[26]), + .C1(registers_1__ap[26]), .C2(n_1_0_1274), .ZN(n_1_0_1164) + ); + SDFF_X1_LVT \registers_reg[29][26] ( + .CK(n_0_59), .D(registers[26]), .Q(registers_29__ap[26]), .QN(), .SE(dftIn), + .SI(registers_27__ap[27]) + ); + SDFF_X1_LVT \registers_reg[2][26] ( + .CK(n_0_32), .D(registers[26]), .Q(registers_2__ap[26]), .QN(), .SE(dftIn), + .SI(registers_29__ap[26]) + ); + AOI22_X1_LVT i_1_0_1222( + .A1(registers_29__ap[26]), .A2(n_1_0_1276), .B1(n_1_0_1268), .B2(registers_2__ap[26]), + .ZN(n_1_0_1163) + ); + SDFF_X1_LVT \registers_reg[9][26] ( + .CK(n_0_39), .D(registers[26]), .Q(registers_9__ap[26]), .QN(), .SE(dftIn), + .SI(registers_31__ap[27]) + ); + SDFF_X1_LVT \registers_reg[7][26] ( + .CK(n_0_37), .D(registers[26]), .Q(registers_7__ap[26]), .QN(), .SE(dftIn), + .SI(registers_9__ap[26]) + ); + AOI22_X1_LVT i_1_0_1221( + .A1(registers_9__ap[26]), .A2(n_1_0_1291), .B1(n_1_0_1263), .B2(registers_7__ap[26]), + .ZN(n_1_0_1162) + ); + SDFF_X1_LVT \registers_reg[11][26] ( + .CK(n_0_41), .D(registers[26]), .Q(registers_11__ap[26]), .QN(), .SE(dftIn), + .SI(registers_14__ap[27]) + ); + SDFF_X1_LVT \registers_reg[25][26] ( + .CK(n_0_55), .D(registers[26]), .Q(registers_25__ap[26]), .QN(), .SE(dftIn), + .SI(registers_2__ap[26]) + ); + AOI22_X1_LVT i_1_0_1220( + .A1(registers_11__ap[26]), .A2(n_1_0_1270), .B1(n_1_0_1269), .B2(registers_25__ap[26]), + .ZN(n_1_0_1161) + ); + SDFF_X1_LVT \registers_reg[27][26] ( + .CK(n_0_57), .D(registers[26]), .Q(registers_27__ap[26]), .QN(), .SE(dftIn), + .SI(registers_25__ap[26]) + ); + SDFF_X1_LVT \registers_reg[16][26] ( + .CK(n_0_46), .D(registers[26]), .Q(registers_16__ap[26]), .QN(), .SE(dftIn), + .SI(registers_11__ap[26]) + ); + AOI22_X1_LVT i_1_0_1219( + .A1(registers_27__ap[26]), .A2(n_1_0_1279), .B1(n_1_0_1267), .B2(registers_16__ap[26]), + .ZN(n_1_0_1160) + ); + NAND3_X1_LVT i_1_0_1218( + .A1(n_1_0_1162), .A2(n_1_0_1161), .A3(n_1_0_1160), .ZN(n_1_0_1159) + ); + SDFF_X1_LVT \registers_reg[31][26] ( + .CK(n_0_61), .D(registers[26]), .Q(registers_31__ap[26]), .QN(), .SE(dftIn), + .SI(registers_7__ap[26]) + ); + SDFF_X1_LVT \registers_reg[6][26] ( + .CK(n_0_36), .D(registers[26]), .Q(registers_6__ap[26]), .QN(), .SE(dftIn), + .SI(registers_31__ap[26]) + ); + AOI221_X1_LVT i_1_0_1217( + .A(n_1_0_1159), .B1(n_1_0_1266), .B2(registers_31__ap[26]), .C1(registers_6__ap[26]), + .C2(n_1_0_1300), .ZN(n_1_0_1158) + ); + NAND3_X1_LVT i_1_0_1216( + .A1(n_1_0_1164), .A2(n_1_0_1163), .A3(n_1_0_1158), .ZN(n_1_0_1157) + ); + SDFF_X1_LVT \registers_reg[5][26] ( + .CK(n_0_35), .D(registers[26]), .Q(registers_5__ap[26]), .QN(), .SE(dftIn), + .SI(registers_6__ap[26]) + ); + SDFF_X1_LVT \registers_reg[28][26] ( + .CK(n_0_58), .D(registers[26]), .Q(registers_28__ap[26]), .QN(), .SE(dftIn), + .SI(registers_27__ap[26]) + ); + AOI221_X1_LVT i_1_0_1215( + .A(n_1_0_1157), .B1(n_1_0_1273), .B2(registers_5__ap[26]), .C1(registers_28__ap[26]), + .C2(n_1_0_1283), .ZN(n_1_0_1156) + ); + SDFF_X1_LVT \registers_reg[4][26] ( + .CK(n_0_34), .D(registers[26]), .Q(registers_4__ap[26]), .QN(), .SE(dftIn), + .SI(registers_5__ap[26]) + ); + SDFF_X1_LVT \registers_reg[12][26] ( + .CK(n_0_42), .D(registers[26]), .Q(registers_12__ap[26]), .QN(), .SE(dftIn), + .SI(registers_16__ap[26]) + ); + AOI22_X1_LVT i_1_0_1214( + .A1(registers_4__ap[26]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[26]), + .ZN(n_1_0_1155) + ); + SDFF_X1_LVT \registers_reg[19][26] ( + .CK(n_0_49), .D(registers[26]), .Q(registers_19__ap[26]), .QN(), .SE(dftIn), + .SI(registers_1__ap[26]) + ); + SDFF_X1_LVT \registers_reg[21][26] ( + .CK(n_0_51), .D(registers[26]), .Q(registers_21__ap[26]), .QN(), .SE(dftIn), + .SI(registers_19__ap[26]) + ); + AOI22_X1_LVT i_1_0_1213( + .A1(registers_19__ap[26]), .A2(n_1_0_1295), .B1(n_1_0_1259), .B2(registers_21__ap[26]), + .ZN(n_1_0_1154) + ); + SDFF_X1_LVT \registers_reg[24][26] ( + .CK(n_0_54), .D(registers[26]), .Q(registers_24__ap[26]), .QN(), .SE(dftIn), + .SI(registers_28__ap[26]) + ); + SDFF_X1_LVT \registers_reg[20][26] ( + .CK(n_0_50), .D(registers[26]), .Q(registers_20__ap[26]), .QN(), .SE(dftIn), + .SI(registers_21__ap[26]) + ); + AOI22_X1_LVT i_1_0_1212( + .A1(registers_24__ap[26]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[26]), + .ZN(n_1_0_1153) + ); + NAND3_X1_LVT i_1_0_1211( + .A1(n_1_0_1155), .A2(n_1_0_1154), .A3(n_1_0_1153), .ZN(n_1_0_1152) + ); + SDFF_X1_LVT \registers_reg[26][26] ( + .CK(n_0_56), .D(registers[26]), .Q(registers_26__ap[26]), .QN(), .SE(dftIn), + .SI(registers_24__ap[26]) + ); + SDFF_X1_LVT \registers_reg[30][26] ( + .CK(n_0_60), .D(registers[26]), .Q(registers_30__ap[26]), .QN(), .SE(dftIn), + .SI(registers_26__ap[26]) + ); + AOI221_X1_LVT i_1_0_1210( + .A(n_1_0_1152), .B1(n_1_0_1285), .B2(registers_26__ap[26]), .C1(registers_30__ap[26]), + .C2(n_1_0_1272), .ZN(n_1_0_1151) + ); + SDFF_X1_LVT \registers_reg[8][26] ( + .CK(n_0_38), .D(registers[26]), .Q(registers_8__ap[26]), .QN(), .SE(dftIn), + .SI(registers_4__ap[26]) + ); + SDFF_X1_LVT \registers_reg[23][26] ( + .CK(n_0_53), .D(registers[26]), .Q(registers_23__ap[26]), .QN(), .SE(dftIn), + .SI(registers_20__ap[26]) + ); + AOI22_X1_LVT i_1_0_1209( + .A1(registers_8__ap[26]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[26]), + .ZN(n_1_0_1150) + ); + SDFF_X1_LVT \registers_reg[13][26] ( + .CK(n_0_43), .D(registers[26]), .Q(registers_13__ap[26]), .QN(), .SE(dftIn), + .SI(registers_12__ap[26]) + ); + SDFF_X1_LVT \registers_reg[17][26] ( + .CK(n_0_47), .D(registers[26]), .Q(registers_17__ap[26]), .QN(), .SE(dftIn), + .SI(registers_23__ap[26]) + ); + AOI22_X1_LVT i_1_0_1208( + .A1(registers_13__ap[26]), .A2(n_1_0_1277), .B1(n_1_0_1271), .B2(registers_17__ap[26]), + .ZN(n_1_0_1149) + ); + SDFF_X1_LVT \registers_reg[15][26] ( + .CK(n_0_45), .D(registers[26]), .Q(registers_15__ap[26]), .QN(), .SE(dftIn), + .SI(registers_13__ap[26]) + ); + SDFF_X1_LVT \registers_reg[14][26] ( + .CK(n_0_44), .D(registers[26]), .Q(registers_14__ap[26]), .QN(), .SE(dftIn), + .SI(registers_15__ap[26]) + ); + AOI22_X1_LVT i_1_0_1207( + .A1(registers_15__ap[26]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[26]), + .ZN(n_1_0_1148) + ); + NAND3_X1_LVT i_1_0_1206( + .A1(n_1_0_1150), .A2(n_1_0_1149), .A3(n_1_0_1148), .ZN(n_1_0_1147) + ); + SDFF_X1_LVT \registers_reg[10][26] ( + .CK(n_0_40), .D(registers[26]), .Q(registers_10__ap[26]), .QN(), .SE(dftIn), + .SI(registers_14__ap[26]) + ); + SDFF_X1_LVT \registers_reg[3][26] ( + .CK(n_0_33), .D(registers[26]), .Q(registers_3__ap[26]), .QN(), .SE(dftIn), + .SI(registers_8__ap[26]) + ); + AOI221_X1_LVT i_1_0_1205( + .A(n_1_0_1147), .B1(n_1_0_1287), .B2(registers_10__ap[26]), .C1(registers_3__ap[26]), + .C2(n_1_0_1257), .ZN(n_1_0_1146) + ); + NAND3_X1_LVT i_1_0_1204( + .A1(n_1_0_1156), .A2(n_1_0_1151), .A3(n_1_0_1146), .ZN(RRs1[26]) + ); + AND2_X1_LVT i_0_0_25( + .A1(n_0_0_16), .A2(WRd[25]), .ZN(registers[25]) + ); + SDFF_X1_LVT \registers_reg[17][25] ( + .CK(n_0_47), .D(registers[25]), .Q(registers_17__ap[25]), .QN(), .SE(dftIn), + .SI(registers_17__ap[26]) + ); + SDFF_X1_LVT \registers_reg[21][25] ( + .CK(n_0_51), .D(registers[25]), .Q(registers_21__ap[25]), .QN(), .SE(dftIn), + .SI(registers_17__ap[25]) + ); + AOI22_X1_LVT i_1_0_1202( + .A1(registers_17__ap[25]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[25]), + .ZN(n_1_0_1144) + ); + SDFF_X1_LVT \registers_reg[6][25] ( + .CK(n_0_36), .D(registers[25]), .Q(registers_6__ap[25]), .QN(), .SE(dftIn), + .SI(registers_3__ap[26]) + ); + SDFF_X1_LVT \registers_reg[8][25] ( + .CK(n_0_38), .D(registers[25]), .Q(registers_8__ap[25]), .QN(), .SE(dftIn), + .SI(registers_6__ap[25]) + ); + AOI22_X1_LVT i_1_0_1203( + .A1(registers_6__ap[25]), .A2(n_1_0_1300), .B1(n_1_0_1282), .B2(registers_8__ap[25]), + .ZN(n_1_0_1145) + ); + SDFF_X1_LVT \registers_reg[20][25] ( + .CK(n_0_50), .D(registers[25]), .Q(registers_20__ap[25]), .QN(), .SE(dftIn), + .SI(registers_21__ap[25]) + ); + SDFF_X1_LVT \registers_reg[12][25] ( + .CK(n_0_42), .D(registers[25]), .Q(registers_12__ap[25]), .QN(), .SE(dftIn), + .SI(registers_10__ap[26]) + ); + AOI22_X1_LVT i_1_0_1201( + .A1(registers_20__ap[25]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[25]), + .ZN(n_1_0_1143) + ); + SDFF_X1_LVT \registers_reg[5][25] ( + .CK(n_0_35), .D(registers[25]), .Q(registers_5__ap[25]), .QN(), .SE(dftIn), + .SI(registers_8__ap[25]) + ); + SDFF_X1_LVT \registers_reg[11][25] ( + .CK(n_0_41), .D(registers[25]), .Q(registers_11__ap[25]), .QN(), .SE(dftIn), + .SI(registers_12__ap[25]) + ); + AOI22_X1_LVT i_1_0_1200( + .A1(registers_5__ap[25]), .A2(n_1_0_1273), .B1(n_1_0_1270), .B2(registers_11__ap[25]), + .ZN(n_1_0_1142) + ); + NAND3_X1_LVT i_1_0_1199( + .A1(n_1_0_1145), .A2(n_1_0_1143), .A3(n_1_0_1142), .ZN(n_1_0_1141) + ); + SDFF_X1_LVT \registers_reg[10][25] ( + .CK(n_0_40), .D(registers[25]), .Q(registers_10__ap[25]), .QN(), .SE(dftIn), + .SI(registers_11__ap[25]) + ); + SDFF_X1_LVT \registers_reg[2][25] ( + .CK(n_0_32), .D(registers[25]), .Q(registers_2__ap[25]), .QN(), .SE(dftIn), + .SI(registers_30__ap[26]) + ); + AOI221_X1_LVT i_1_0_1198( + .A(n_1_0_1141), .B1(n_1_0_1287), .B2(registers_10__ap[25]), .C1(registers_2__ap[25]), + .C2(n_1_0_1268), .ZN(n_1_0_1140) + ); + SDFF_X1_LVT \registers_reg[13][25] ( + .CK(n_0_43), .D(registers[25]), .Q(registers_13__ap[25]), .QN(), .SE(dftIn), + .SI(registers_10__ap[25]) + ); + SDFF_X1_LVT \registers_reg[30][25] ( + .CK(n_0_60), .D(registers[25]), .Q(registers_30__ap[25]), .QN(), .SE(dftIn), + .SI(registers_2__ap[25]) + ); + SDFF_X1_LVT \registers_reg[22][25] ( + .CK(n_0_52), .D(registers[25]), .Q(registers_22__ap[25]), .QN(), .SE(dftIn), + .SI(registers_20__ap[25]) + ); + AOI222_X1_LVT i_1_0_1197( + .A1(registers_13__ap[25]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[25]), + .C1(registers_22__ap[25]), .C2(n_1_0_1294), .ZN(n_1_0_1139) + ); + NAND2_X1_LVT i_1_0_1196( + .A1(n_1_0_1140), .A2(n_1_0_1139), .ZN(n_1_0_1138) + ); + SDFF_X1_LVT \registers_reg[1][25] ( + .CK(n_0_0), .D(registers[25]), .Q(registers_1__ap[25]), .QN(), .SE(dftIn), + .SI(registers_22__ap[25]) + ); + SDFF_X1_LVT \registers_reg[28][25] ( + .CK(n_0_58), .D(registers[25]), .Q(registers_28__ap[25]), .QN(), .SE(dftIn), + .SI(registers_30__ap[25]) + ); + AOI221_X1_LVT i_1_0_1195( + .A(n_1_0_1138), .B1(n_1_0_1274), .B2(registers_1__ap[25]), .C1(registers_28__ap[25]), + .C2(n_1_0_1283), .ZN(n_1_0_1137) + ); + SDFF_X1_LVT \registers_reg[18][25] ( + .CK(n_0_48), .D(registers[25]), .Q(registers_18__ap[25]), .QN(), .SE(dftIn), + .SI(registers_1__ap[25]) + ); + SDFF_X1_LVT \registers_reg[26][25] ( + .CK(n_0_56), .D(registers[25]), .Q(registers_26__ap[25]), .QN(), .SE(dftIn), + .SI(registers_28__ap[25]) + ); + AOI22_X1_LVT i_1_0_1194( + .A1(registers_18__ap[25]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[25]), + .ZN(n_1_0_1136) + ); + SDFF_X1_LVT \registers_reg[24][25] ( + .CK(n_0_54), .D(registers[25]), .Q(registers_24__ap[25]), .QN(), .SE(dftIn), + .SI(registers_26__ap[25]) + ); + SDFF_X1_LVT \registers_reg[4][25] ( + .CK(n_0_34), .D(registers[25]), .Q(registers_4__ap[25]), .QN(), .SE(dftIn), + .SI(registers_5__ap[25]) + ); + AOI22_X1_LVT i_1_0_1193( + .A1(registers_24__ap[25]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[25]), + .ZN(n_1_0_1135) + ); + SDFF_X1_LVT \registers_reg[15][25] ( + .CK(n_0_45), .D(registers[25]), .Q(registers_15__ap[25]), .QN(), .SE(dftIn), + .SI(registers_13__ap[25]) + ); + SDFF_X1_LVT \registers_reg[16][25] ( + .CK(n_0_46), .D(registers[25]), .Q(registers_16__ap[25]), .QN(), .SE(dftIn), + .SI(registers_15__ap[25]) + ); + AOI22_X1_LVT i_1_0_1192( + .A1(registers_15__ap[25]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[25]), + .ZN(n_1_0_1134) + ); + NAND3_X1_LVT i_1_0_1191( + .A1(n_1_0_1136), .A2(n_1_0_1135), .A3(n_1_0_1134), .ZN(n_1_0_1133) + ); + SDFF_X1_LVT \registers_reg[19][25] ( + .CK(n_0_49), .D(registers[25]), .Q(registers_19__ap[25]), .QN(), .SE(dftIn), + .SI(registers_18__ap[25]) + ); + SDFF_X1_LVT \registers_reg[25][25] ( + .CK(n_0_55), .D(registers[25]), .Q(registers_25__ap[25]), .QN(), .SE(dftIn), + .SI(registers_24__ap[25]) + ); + AOI221_X1_LVT i_1_0_1190( + .A(n_1_0_1133), .B1(n_1_0_1295), .B2(registers_19__ap[25]), .C1(registers_25__ap[25]), + .C2(n_1_0_1269), .ZN(n_1_0_1132) + ); + SDFF_X1_LVT \registers_reg[7][25] ( + .CK(n_0_37), .D(registers[25]), .Q(registers_7__ap[25]), .QN(), .SE(dftIn), + .SI(registers_4__ap[25]) + ); + SDFF_X1_LVT \registers_reg[14][25] ( + .CK(n_0_44), .D(registers[25]), .Q(registers_14__ap[25]), .QN(), .SE(dftIn), + .SI(registers_16__ap[25]) + ); + AOI22_X1_LVT i_1_0_1189( + .A1(registers_7__ap[25]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[25]), + .ZN(n_1_0_1131) + ); + SDFF_X1_LVT \registers_reg[9][25] ( + .CK(n_0_39), .D(registers[25]), .Q(registers_9__ap[25]), .QN(), .SE(dftIn), + .SI(registers_7__ap[25]) + ); + SDFF_X1_LVT \registers_reg[29][25] ( + .CK(n_0_59), .D(registers[25]), .Q(registers_29__ap[25]), .QN(), .SE(dftIn), + .SI(registers_25__ap[25]) + ); + AOI22_X1_LVT i_1_0_1188( + .A1(registers_9__ap[25]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[25]), + .ZN(n_1_0_1130) + ); + SDFF_X1_LVT \registers_reg[23][25] ( + .CK(n_0_53), .D(registers[25]), .Q(registers_23__ap[25]), .QN(), .SE(dftIn), + .SI(registers_19__ap[25]) + ); + SDFF_X1_LVT \registers_reg[3][25] ( + .CK(n_0_33), .D(registers[25]), .Q(registers_3__ap[25]), .QN(), .SE(dftIn), + .SI(registers_9__ap[25]) + ); + AOI22_X1_LVT i_1_0_1187( + .A1(registers_23__ap[25]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[25]), + .ZN(n_1_0_1129) + ); + NAND3_X1_LVT i_1_0_1186( + .A1(n_1_0_1131), .A2(n_1_0_1130), .A3(n_1_0_1129), .ZN(n_1_0_1128) + ); + SDFF_X1_LVT \registers_reg[27][25] ( + .CK(n_0_57), .D(registers[25]), .Q(registers_27__ap[25]), .QN(), .SE(dftIn), + .SI(registers_29__ap[25]) + ); + SDFF_X1_LVT \registers_reg[31][25] ( + .CK(n_0_61), .D(registers[25]), .Q(registers_31__ap[25]), .QN(), .SE(dftIn), + .SI(registers_3__ap[25]) + ); + AOI221_X1_LVT i_1_0_1185( + .A(n_1_0_1128), .B1(n_1_0_1279), .B2(registers_27__ap[25]), .C1(registers_31__ap[25]), + .C2(n_1_0_1266), .ZN(n_1_0_1127) + ); + NAND4_X1_LVT i_1_0_1184( + .A1(n_1_0_1144), .A2(n_1_0_1137), .A3(n_1_0_1132), .A4(n_1_0_1127), .ZN(RRs1[25]) + ); + AND2_X1_LVT i_0_0_24( + .A1(n_0_0_16), .A2(WRd[24]), .ZN(registers[24]) + ); + SDFF_X1_LVT \registers_reg[17][24] ( + .CK(n_0_47), .D(registers[24]), .Q(registers_17__ap[24]), .QN(), .SE(dftIn), + .SI(registers_23__ap[25]) + ); + SDFF_X1_LVT \registers_reg[21][24] ( + .CK(n_0_51), .D(registers[24]), .Q(registers_21__ap[24]), .QN(), .SE(dftIn), + .SI(registers_17__ap[24]) + ); + AOI22_X1_LVT i_1_0_1182( + .A1(registers_17__ap[24]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[24]), + .ZN(n_1_0_1125) + ); + SDFF_X1_LVT \registers_reg[6][24] ( + .CK(n_0_36), .D(registers[24]), .Q(registers_6__ap[24]), .QN(), .SE(dftIn), + .SI(registers_31__ap[25]) + ); + SDFF_X1_LVT \registers_reg[8][24] ( + .CK(n_0_38), .D(registers[24]), .Q(registers_8__ap[24]), .QN(), .SE(dftIn), + .SI(registers_6__ap[24]) + ); + AOI22_X1_LVT i_1_0_1183( + .A1(registers_6__ap[24]), .A2(n_1_0_1300), .B1(n_1_0_1282), .B2(registers_8__ap[24]), + .ZN(n_1_0_1126) + ); + SDFF_X1_LVT \registers_reg[20][24] ( + .CK(n_0_50), .D(registers[24]), .Q(registers_20__ap[24]), .QN(), .SE(dftIn), + .SI(registers_21__ap[24]) + ); + SDFF_X1_LVT \registers_reg[12][24] ( + .CK(n_0_42), .D(registers[24]), .Q(registers_12__ap[24]), .QN(), .SE(dftIn), + .SI(registers_14__ap[25]) + ); + AOI22_X1_LVT i_1_0_1181( + .A1(registers_20__ap[24]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[24]), + .ZN(n_1_0_1124) + ); + SDFF_X1_LVT \registers_reg[5][24] ( + .CK(n_0_35), .D(registers[24]), .Q(registers_5__ap[24]), .QN(), .SE(dftIn), + .SI(registers_8__ap[24]) + ); + SDFF_X1_LVT \registers_reg[11][24] ( + .CK(n_0_41), .D(registers[24]), .Q(registers_11__ap[24]), .QN(), .SE(dftIn), + .SI(registers_12__ap[24]) + ); + AOI22_X1_LVT i_1_0_1180( + .A1(registers_5__ap[24]), .A2(n_1_0_1273), .B1(n_1_0_1270), .B2(registers_11__ap[24]), + .ZN(n_1_0_1123) + ); + NAND3_X1_LVT i_1_0_1179( + .A1(n_1_0_1126), .A2(n_1_0_1124), .A3(n_1_0_1123), .ZN(n_1_0_1122) + ); + SDFF_X1_LVT \registers_reg[10][24] ( + .CK(n_0_40), .D(registers[24]), .Q(registers_10__ap[24]), .QN(), .SE(dftIn), + .SI(registers_11__ap[24]) + ); + SDFF_X1_LVT \registers_reg[2][24] ( + .CK(n_0_32), .D(registers[24]), .Q(registers_2__ap[24]), .QN(), .SE(dftIn), + .SI(registers_27__ap[25]) + ); + AOI221_X1_LVT i_1_0_1178( + .A(n_1_0_1122), .B1(n_1_0_1287), .B2(registers_10__ap[24]), .C1(registers_2__ap[24]), + .C2(n_1_0_1268), .ZN(n_1_0_1121) + ); + SDFF_X1_LVT \registers_reg[13][24] ( + .CK(n_0_43), .D(registers[24]), .Q(registers_13__ap[24]), .QN(), .SE(dftIn), + .SI(registers_10__ap[24]) + ); + SDFF_X1_LVT \registers_reg[30][24] ( + .CK(n_0_60), .D(registers[24]), .Q(registers_30__ap[24]), .QN(), .SE(dftIn), + .SI(registers_2__ap[24]) + ); + SDFF_X1_LVT \registers_reg[22][24] ( + .CK(n_0_52), .D(registers[24]), .Q(registers_22__ap[24]), .QN(), .SE(dftIn), + .SI(registers_20__ap[24]) + ); + AOI222_X1_LVT i_1_0_1177( + .A1(registers_13__ap[24]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[24]), + .C1(registers_22__ap[24]), .C2(n_1_0_1294), .ZN(n_1_0_1120) + ); + NAND2_X1_LVT i_1_0_1176( + .A1(n_1_0_1121), .A2(n_1_0_1120), .ZN(n_1_0_1119) + ); + SDFF_X1_LVT \registers_reg[1][24] ( + .CK(n_0_0), .D(registers[24]), .Q(registers_1__ap[24]), .QN(), .SE(dftIn), + .SI(registers_22__ap[24]) + ); + SDFF_X1_LVT \registers_reg[28][24] ( + .CK(n_0_58), .D(registers[24]), .Q(registers_28__ap[24]), .QN(), .SE(dftIn), + .SI(registers_30__ap[24]) + ); + AOI221_X1_LVT i_1_0_1175( + .A(n_1_0_1119), .B1(n_1_0_1274), .B2(registers_1__ap[24]), .C1(registers_28__ap[24]), + .C2(n_1_0_1283), .ZN(n_1_0_1118) + ); + SDFF_X1_LVT \registers_reg[18][24] ( + .CK(n_0_48), .D(registers[24]), .Q(registers_18__ap[24]), .QN(), .SE(dftIn), + .SI(registers_1__ap[24]) + ); + SDFF_X1_LVT \registers_reg[26][24] ( + .CK(n_0_56), .D(registers[24]), .Q(registers_26__ap[24]), .QN(), .SE(dftIn), + .SI(registers_28__ap[24]) + ); + AOI22_X1_LVT i_1_0_1174( + .A1(registers_18__ap[24]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[24]), + .ZN(n_1_0_1117) + ); + SDFF_X1_LVT \registers_reg[24][24] ( + .CK(n_0_54), .D(registers[24]), .Q(registers_24__ap[24]), .QN(), .SE(dftIn), + .SI(registers_26__ap[24]) + ); + SDFF_X1_LVT \registers_reg[4][24] ( + .CK(n_0_34), .D(registers[24]), .Q(registers_4__ap[24]), .QN(), .SE(dftIn), + .SI(registers_5__ap[24]) + ); + AOI22_X1_LVT i_1_0_1173( + .A1(registers_24__ap[24]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[24]), + .ZN(n_1_0_1116) + ); + SDFF_X1_LVT \registers_reg[15][24] ( + .CK(n_0_45), .D(registers[24]), .Q(registers_15__ap[24]), .QN(), .SE(dftIn), + .SI(registers_13__ap[24]) + ); + SDFF_X1_LVT \registers_reg[25][24] ( + .CK(n_0_55), .D(registers[24]), .Q(registers_25__ap[24]), .QN(), .SE(dftIn), + .SI(registers_24__ap[24]) + ); + AOI22_X1_LVT i_1_0_1172( + .A1(registers_15__ap[24]), .A2(n_1_0_1286), .B1(n_1_0_1269), .B2(registers_25__ap[24]), + .ZN(n_1_0_1115) + ); + NAND3_X1_LVT i_1_0_1171( + .A1(n_1_0_1117), .A2(n_1_0_1116), .A3(n_1_0_1115), .ZN(n_1_0_1114) + ); + SDFF_X1_LVT \registers_reg[19][24] ( + .CK(n_0_49), .D(registers[24]), .Q(registers_19__ap[24]), .QN(), .SE(dftIn), + .SI(registers_18__ap[24]) + ); + SDFF_X1_LVT \registers_reg[16][24] ( + .CK(n_0_46), .D(registers[24]), .Q(registers_16__ap[24]), .QN(), .SE(dftIn), + .SI(registers_15__ap[24]) + ); + AOI221_X1_LVT i_1_0_1170( + .A(n_1_0_1114), .B1(n_1_0_1295), .B2(registers_19__ap[24]), .C1(registers_16__ap[24]), + .C2(n_1_0_1267), .ZN(n_1_0_1113) + ); + SDFF_X1_LVT \registers_reg[7][24] ( + .CK(n_0_37), .D(registers[24]), .Q(registers_7__ap[24]), .QN(), .SE(dftIn), + .SI(registers_4__ap[24]) + ); + SDFF_X1_LVT \registers_reg[14][24] ( + .CK(n_0_44), .D(registers[24]), .Q(registers_14__ap[24]), .QN(), .SE(dftIn), + .SI(registers_16__ap[24]) + ); + AOI22_X1_LVT i_1_0_1169( + .A1(registers_7__ap[24]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[24]), + .ZN(n_1_0_1112) + ); + SDFF_X1_LVT \registers_reg[9][24] ( + .CK(n_0_39), .D(registers[24]), .Q(registers_9__ap[24]), .QN(), .SE(dftIn), + .SI(registers_7__ap[24]) + ); + SDFF_X1_LVT \registers_reg[29][24] ( + .CK(n_0_59), .D(registers[24]), .Q(registers_29__ap[24]), .QN(), .SE(dftIn), + .SI(registers_25__ap[24]) + ); + AOI22_X1_LVT i_1_0_1168( + .A1(registers_9__ap[24]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[24]), + .ZN(n_1_0_1111) + ); + SDFF_X1_LVT \registers_reg[23][24] ( + .CK(n_0_53), .D(registers[24]), .Q(registers_23__ap[24]), .QN(), .SE(dftIn), + .SI(registers_19__ap[24]) + ); + SDFF_X1_LVT \registers_reg[3][24] ( + .CK(n_0_33), .D(registers[24]), .Q(registers_3__ap[24]), .QN(), .SE(dftIn), + .SI(registers_9__ap[24]) + ); + AOI22_X1_LVT i_1_0_1167( + .A1(registers_23__ap[24]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[24]), + .ZN(n_1_0_1110) + ); + NAND3_X1_LVT i_1_0_1166( + .A1(n_1_0_1112), .A2(n_1_0_1111), .A3(n_1_0_1110), .ZN(n_1_0_1109) + ); + SDFF_X1_LVT \registers_reg[27][24] ( + .CK(n_0_57), .D(registers[24]), .Q(registers_27__ap[24]), .QN(), .SE(dftIn), + .SI(registers_29__ap[24]) + ); + SDFF_X1_LVT \registers_reg[31][24] ( + .CK(n_0_61), .D(registers[24]), .Q(registers_31__ap[24]), .QN(), .SE(dftIn), + .SI(registers_3__ap[24]) + ); + AOI221_X1_LVT i_1_0_1165( + .A(n_1_0_1109), .B1(n_1_0_1279), .B2(registers_27__ap[24]), .C1(registers_31__ap[24]), + .C2(n_1_0_1266), .ZN(n_1_0_1108) + ); + NAND4_X1_LVT i_1_0_1164( + .A1(n_1_0_1125), .A2(n_1_0_1118), .A3(n_1_0_1113), .A4(n_1_0_1108), .ZN(RRs1[24]) + ); + AND2_X1_LVT i_0_0_23( + .A1(n_0_0_16), .A2(WRd[23]), .ZN(registers[23]) + ); + SDFF_X1_LVT \registers_reg[9][23] ( + .CK(n_0_39), .D(registers[23]), .Q(registers_9__ap[23]), .QN(), .SE(dftIn), + .SI(registers_31__ap[24]) + ); + SDFF_X1_LVT \registers_reg[28][23] ( + .CK(n_0_58), .D(registers[23]), .Q(registers_28__ap[23]), .QN(), .SE(dftIn), + .SI(registers_27__ap[24]) + ); + AOI22_X1_LVT i_1_0_1163( + .A1(registers_9__ap[23]), .A2(n_1_0_1291), .B1(n_1_0_1283), .B2(registers_28__ap[23]), + .ZN(n_1_0_1107) + ); + SDFF_X1_LVT \registers_reg[18][23] ( + .CK(n_0_48), .D(registers[23]), .Q(registers_18__ap[23]), .QN(), .SE(dftIn), + .SI(registers_23__ap[24]) + ); + SDFF_X1_LVT \registers_reg[22][23] ( + .CK(n_0_52), .D(registers[23]), .Q(registers_22__ap[23]), .QN(), .SE(dftIn), + .SI(registers_18__ap[23]) + ); + AOI22_X1_LVT i_1_0_1160( + .A1(registers_18__ap[23]), .A2(n_1_0_1297), .B1(n_1_0_1294), .B2(registers_22__ap[23]), + .ZN(n_1_0_1104) + ); + SDFF_X1_LVT \registers_reg[1][23] ( + .CK(n_0_0), .D(registers[23]), .Q(registers_1__ap[23]), .QN(), .SE(dftIn), + .SI(registers_22__ap[23]) + ); + SDFF_X1_LVT \registers_reg[21][23] ( + .CK(n_0_51), .D(registers[23]), .Q(registers_21__ap[23]), .QN(), .SE(dftIn), + .SI(registers_1__ap[23]) + ); + AOI22_X1_LVT i_1_0_1159( + .A1(registers_1__ap[23]), .A2(n_1_0_1274), .B1(n_1_0_1259), .B2(registers_21__ap[23]), + .ZN(n_1_0_1103) + ); + NAND3_X1_LVT i_1_0_1157( + .A1(n_1_0_1107), .A2(n_1_0_1104), .A3(n_1_0_1103), .ZN(n_1_0_1101) + ); + SDFF_X1_LVT \registers_reg[20][23] ( + .CK(n_0_50), .D(registers[23]), .Q(registers_20__ap[23]), .QN(), .SE(dftIn), + .SI(registers_21__ap[23]) + ); + SDFF_X1_LVT \registers_reg[19][23] ( + .CK(n_0_49), .D(registers[23]), .Q(registers_19__ap[23]), .QN(), .SE(dftIn), + .SI(registers_20__ap[23]) + ); + AOI221_X1_LVT i_1_0_1156( + .A(n_1_0_1101), .B1(n_1_0_1281), .B2(registers_20__ap[23]), .C1(registers_19__ap[23]), + .C2(n_1_0_1295), .ZN(n_1_0_1100) + ); + SDFF_X1_LVT \registers_reg[26][23] ( + .CK(n_0_56), .D(registers[23]), .Q(registers_26__ap[23]), .QN(), .SE(dftIn), + .SI(registers_28__ap[23]) + ); + SDFF_X1_LVT \registers_reg[23][23] ( + .CK(n_0_53), .D(registers[23]), .Q(registers_23__ap[23]), .QN(), .SE(dftIn), + .SI(registers_19__ap[23]) + ); + AOI22_X1_LVT i_1_0_1162( + .A1(registers_26__ap[23]), .A2(n_1_0_1285), .B1(n_1_0_1264), .B2(registers_23__ap[23]), + .ZN(n_1_0_1106) + ); + SDFF_X1_LVT \registers_reg[29][23] ( + .CK(n_0_59), .D(registers[23]), .Q(registers_29__ap[23]), .QN(), .SE(dftIn), + .SI(registers_26__ap[23]) + ); + SDFF_X1_LVT \registers_reg[3][23] ( + .CK(n_0_33), .D(registers[23]), .Q(registers_3__ap[23]), .QN(), .SE(dftIn), + .SI(registers_9__ap[23]) + ); + AOI22_X1_LVT i_1_0_1161( + .A1(registers_29__ap[23]), .A2(n_1_0_1276), .B1(n_1_0_1257), .B2(registers_3__ap[23]), + .ZN(n_1_0_1105) + ); + SDFF_X1_LVT \registers_reg[30][23] ( + .CK(n_0_60), .D(registers[23]), .Q(registers_30__ap[23]), .QN(), .SE(dftIn), + .SI(registers_29__ap[23]) + ); + SDFF_X1_LVT \registers_reg[31][23] ( + .CK(n_0_61), .D(registers[23]), .Q(registers_31__ap[23]), .QN(), .SE(dftIn), + .SI(registers_3__ap[23]) + ); + AOI22_X1_LVT i_1_0_1158( + .A1(registers_30__ap[23]), .A2(n_1_0_1272), .B1(n_1_0_1266), .B2(registers_31__ap[23]), + .ZN(n_1_0_1102) + ); + NAND3_X1_LVT i_1_0_1155( + .A1(n_1_0_1106), .A2(n_1_0_1105), .A3(n_1_0_1102), .ZN(n_1_0_1099) + ); + SDFF_X1_LVT \registers_reg[8][23] ( + .CK(n_0_38), .D(registers[23]), .Q(registers_8__ap[23]), .QN(), .SE(dftIn), + .SI(registers_31__ap[23]) + ); + SDFF_X1_LVT \registers_reg[17][23] ( + .CK(n_0_47), .D(registers[23]), .Q(registers_17__ap[23]), .QN(), .SE(dftIn), + .SI(registers_23__ap[23]) + ); + AOI221_X1_LVT i_1_0_1154( + .A(n_1_0_1099), .B1(n_1_0_1282), .B2(registers_8__ap[23]), .C1(registers_17__ap[23]), + .C2(n_1_0_1271), .ZN(n_1_0_1098) + ); + SDFF_X1_LVT \registers_reg[24][23] ( + .CK(n_0_54), .D(registers[23]), .Q(registers_24__ap[23]), .QN(), .SE(dftIn), + .SI(registers_30__ap[23]) + ); + SDFF_X1_LVT \registers_reg[15][23] ( + .CK(n_0_45), .D(registers[23]), .Q(registers_15__ap[23]), .QN(), .SE(dftIn), + .SI(registers_14__ap[24]) + ); + SDFF_X1_LVT \registers_reg[14][23] ( + .CK(n_0_44), .D(registers[23]), .Q(registers_14__ap[23]), .QN(), .SE(dftIn), + .SI(registers_15__ap[23]) + ); + AOI222_X1_LVT i_1_0_1153( + .A1(registers_24__ap[23]), .A2(n_1_0_1289), .B1(n_1_0_1286), .B2(registers_15__ap[23]), + .C1(n_1_0_1258), .C2(registers_14__ap[23]), .ZN(n_1_0_1097) + ); + SDFF_X1_LVT \registers_reg[16][23] ( + .CK(n_0_46), .D(registers[23]), .Q(registers_16__ap[23]), .QN(), .SE(dftIn), + .SI(registers_14__ap[23]) + ); + SDFF_X1_LVT \registers_reg[7][23] ( + .CK(n_0_37), .D(registers[23]), .Q(registers_7__ap[23]), .QN(), .SE(dftIn), + .SI(registers_8__ap[23]) + ); + AOI22_X1_LVT i_1_0_1152( + .A1(registers_16__ap[23]), .A2(n_1_0_1267), .B1(n_1_0_1263), .B2(registers_7__ap[23]), + .ZN(n_1_0_1096) + ); + SDFF_X1_LVT \registers_reg[6][23] ( + .CK(n_0_36), .D(registers[23]), .Q(registers_6__ap[23]), .QN(), .SE(dftIn), + .SI(registers_7__ap[23]) + ); + SDFF_X1_LVT \registers_reg[25][23] ( + .CK(n_0_55), .D(registers[23]), .Q(registers_25__ap[23]), .QN(), .SE(dftIn), + .SI(registers_24__ap[23]) + ); + AOI22_X1_LVT i_1_0_1151( + .A1(registers_6__ap[23]), .A2(n_1_0_1300), .B1(n_1_0_1269), .B2(registers_25__ap[23]), + .ZN(n_1_0_1095) + ); + SDFF_X1_LVT \registers_reg[27][23] ( + .CK(n_0_57), .D(registers[23]), .Q(registers_27__ap[23]), .QN(), .SE(dftIn), + .SI(registers_25__ap[23]) + ); + SDFF_X1_LVT \registers_reg[11][23] ( + .CK(n_0_41), .D(registers[23]), .Q(registers_11__ap[23]), .QN(), .SE(dftIn), + .SI(registers_16__ap[23]) + ); + AOI22_X1_LVT i_1_0_1150( + .A1(registers_27__ap[23]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[23]), + .ZN(n_1_0_1094) + ); + SDFF_X1_LVT \registers_reg[13][23] ( + .CK(n_0_43), .D(registers[23]), .Q(registers_13__ap[23]), .QN(), .SE(dftIn), + .SI(registers_11__ap[23]) + ); + SDFF_X1_LVT \registers_reg[5][23] ( + .CK(n_0_35), .D(registers[23]), .Q(registers_5__ap[23]), .QN(), .SE(dftIn), + .SI(registers_6__ap[23]) + ); + AOI22_X1_LVT i_1_0_1149( + .A1(registers_13__ap[23]), .A2(n_1_0_1277), .B1(n_1_0_1273), .B2(registers_5__ap[23]), + .ZN(n_1_0_1093) + ); + SDFF_X1_LVT \registers_reg[4][23] ( + .CK(n_0_34), .D(registers[23]), .Q(registers_4__ap[23]), .QN(), .SE(dftIn), + .SI(registers_5__ap[23]) + ); + SDFF_X1_LVT \registers_reg[12][23] ( + .CK(n_0_42), .D(registers[23]), .Q(registers_12__ap[23]), .QN(), .SE(dftIn), + .SI(registers_13__ap[23]) + ); + AOI22_X1_LVT i_1_0_1148( + .A1(registers_4__ap[23]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[23]), + .ZN(n_1_0_1092) + ); + NAND3_X1_LVT i_1_0_1147( + .A1(n_1_0_1094), .A2(n_1_0_1093), .A3(n_1_0_1092), .ZN(n_1_0_1091) + ); + SDFF_X1_LVT \registers_reg[2][23] ( + .CK(n_0_32), .D(registers[23]), .Q(registers_2__ap[23]), .QN(), .SE(dftIn), + .SI(registers_27__ap[23]) + ); + SDFF_X1_LVT \registers_reg[10][23] ( + .CK(n_0_40), .D(registers[23]), .Q(registers_10__ap[23]), .QN(), .SE(dftIn), + .SI(registers_12__ap[23]) + ); + AOI221_X1_LVT i_1_0_1146( + .A(n_1_0_1091), .B1(n_1_0_1268), .B2(registers_2__ap[23]), .C1(registers_10__ap[23]), + .C2(n_1_0_1287), .ZN(n_1_0_1090) + ); + AND4_X1_LVT i_1_0_1145( + .A1(n_1_0_1097), .A2(n_1_0_1096), .A3(n_1_0_1095), .A4(n_1_0_1090), .ZN(n_1_0_1089) + ); + NAND3_X1_LVT i_1_0_1144( + .A1(n_1_0_1100), .A2(n_1_0_1098), .A3(n_1_0_1089), .ZN(RRs1[23]) + ); + AND2_X1_LVT i_0_0_22( + .A1(n_0_0_16), .A2(WRd[22]), .ZN(registers[22]) + ); + SDFF_X1_LVT \registers_reg[17][22] ( + .CK(n_0_47), .D(registers[22]), .Q(registers_17__ap[22]), .QN(), .SE(dftIn), + .SI(registers_17__ap[23]) + ); + SDFF_X1_LVT \registers_reg[21][22] ( + .CK(n_0_51), .D(registers[22]), .Q(registers_21__ap[22]), .QN(), .SE(dftIn), + .SI(registers_17__ap[22]) + ); + AOI22_X1_LVT i_1_0_1142( + .A1(registers_17__ap[22]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[22]), + .ZN(n_1_0_1087) + ); + SDFF_X1_LVT \registers_reg[6][22] ( + .CK(n_0_36), .D(registers[22]), .Q(registers_6__ap[22]), .QN(), .SE(dftIn), + .SI(registers_4__ap[23]) + ); + SDFF_X1_LVT \registers_reg[11][22] ( + .CK(n_0_41), .D(registers[22]), .Q(registers_11__ap[22]), .QN(), .SE(dftIn), + .SI(registers_10__ap[23]) + ); + AOI22_X1_LVT i_1_0_1143( + .A1(registers_6__ap[22]), .A2(n_1_0_1300), .B1(n_1_0_1270), .B2(registers_11__ap[22]), + .ZN(n_1_0_1088) + ); + SDFF_X1_LVT \registers_reg[20][22] ( + .CK(n_0_50), .D(registers[22]), .Q(registers_20__ap[22]), .QN(), .SE(dftIn), + .SI(registers_21__ap[22]) + ); + SDFF_X1_LVT \registers_reg[12][22] ( + .CK(n_0_42), .D(registers[22]), .Q(registers_12__ap[22]), .QN(), .SE(dftIn), + .SI(registers_11__ap[22]) + ); + AOI22_X1_LVT i_1_0_1141( + .A1(registers_20__ap[22]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[22]), + .ZN(n_1_0_1086) + ); + SDFF_X1_LVT \registers_reg[10][22] ( + .CK(n_0_40), .D(registers[22]), .Q(registers_10__ap[22]), .QN(), .SE(dftIn), + .SI(registers_12__ap[22]) + ); + SDFF_X1_LVT \registers_reg[5][22] ( + .CK(n_0_35), .D(registers[22]), .Q(registers_5__ap[22]), .QN(), .SE(dftIn), + .SI(registers_6__ap[22]) + ); + AOI22_X1_LVT i_1_0_1140( + .A1(registers_10__ap[22]), .A2(n_1_0_1287), .B1(n_1_0_1273), .B2(registers_5__ap[22]), + .ZN(n_1_0_1085) + ); + NAND3_X1_LVT i_1_0_1139( + .A1(n_1_0_1088), .A2(n_1_0_1086), .A3(n_1_0_1085), .ZN(n_1_0_1084) + ); + SDFF_X1_LVT \registers_reg[31][22] ( + .CK(n_0_61), .D(registers[22]), .Q(registers_31__ap[22]), .QN(), .SE(dftIn), + .SI(registers_5__ap[22]) + ); + SDFF_X1_LVT \registers_reg[2][22] ( + .CK(n_0_32), .D(registers[22]), .Q(registers_2__ap[22]), .QN(), .SE(dftIn), + .SI(registers_2__ap[23]) + ); + AOI221_X1_LVT i_1_0_1138( + .A(n_1_0_1084), .B1(n_1_0_1266), .B2(registers_31__ap[22]), .C1(registers_2__ap[22]), + .C2(n_1_0_1268), .ZN(n_1_0_1083) + ); + SDFF_X1_LVT \registers_reg[22][22] ( + .CK(n_0_52), .D(registers[22]), .Q(registers_22__ap[22]), .QN(), .SE(dftIn), + .SI(registers_20__ap[22]) + ); + SDFF_X1_LVT \registers_reg[26][22] ( + .CK(n_0_56), .D(registers[22]), .Q(registers_26__ap[22]), .QN(), .SE(dftIn), + .SI(registers_2__ap[22]) + ); + SDFF_X1_LVT \registers_reg[13][22] ( + .CK(n_0_43), .D(registers[22]), .Q(registers_13__ap[22]), .QN(), .SE(dftIn), + .SI(registers_10__ap[22]) + ); + AOI222_X1_LVT i_1_0_1137( + .A1(registers_22__ap[22]), .A2(n_1_0_1294), .B1(n_1_0_1285), .B2(registers_26__ap[22]), + .C1(n_1_0_1277), .C2(registers_13__ap[22]), .ZN(n_1_0_1082) + ); + NAND2_X1_LVT i_1_0_1136( + .A1(n_1_0_1083), .A2(n_1_0_1082), .ZN(n_1_0_1081) + ); + SDFF_X1_LVT \registers_reg[1][22] ( + .CK(n_0_0), .D(registers[22]), .Q(registers_1__ap[22]), .QN(), .SE(dftIn), + .SI(registers_22__ap[22]) + ); + SDFF_X1_LVT \registers_reg[28][22] ( + .CK(n_0_58), .D(registers[22]), .Q(registers_28__ap[22]), .QN(), .SE(dftIn), + .SI(registers_26__ap[22]) + ); + AOI221_X1_LVT i_1_0_1135( + .A(n_1_0_1081), .B1(n_1_0_1274), .B2(registers_1__ap[22]), .C1(registers_28__ap[22]), + .C2(n_1_0_1283), .ZN(n_1_0_1080) + ); + SDFF_X1_LVT \registers_reg[18][22] ( + .CK(n_0_48), .D(registers[22]), .Q(registers_18__ap[22]), .QN(), .SE(dftIn), + .SI(registers_1__ap[22]) + ); + SDFF_X1_LVT \registers_reg[30][22] ( + .CK(n_0_60), .D(registers[22]), .Q(registers_30__ap[22]), .QN(), .SE(dftIn), + .SI(registers_28__ap[22]) + ); + AOI22_X1_LVT i_1_0_1134( + .A1(registers_18__ap[22]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[22]), + .ZN(n_1_0_1079) + ); + SDFF_X1_LVT \registers_reg[24][22] ( + .CK(n_0_54), .D(registers[22]), .Q(registers_24__ap[22]), .QN(), .SE(dftIn), + .SI(registers_30__ap[22]) + ); + SDFF_X1_LVT \registers_reg[4][22] ( + .CK(n_0_34), .D(registers[22]), .Q(registers_4__ap[22]), .QN(), .SE(dftIn), + .SI(registers_31__ap[22]) + ); + AOI22_X1_LVT i_1_0_1133( + .A1(registers_24__ap[22]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[22]), + .ZN(n_1_0_1078) + ); + SDFF_X1_LVT \registers_reg[15][22] ( + .CK(n_0_45), .D(registers[22]), .Q(registers_15__ap[22]), .QN(), .SE(dftIn), + .SI(registers_13__ap[22]) + ); + SDFF_X1_LVT \registers_reg[16][22] ( + .CK(n_0_46), .D(registers[22]), .Q(registers_16__ap[22]), .QN(), .SE(dftIn), + .SI(registers_15__ap[22]) + ); + AOI22_X1_LVT i_1_0_1132( + .A1(registers_15__ap[22]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[22]), + .ZN(n_1_0_1077) + ); + NAND3_X1_LVT i_1_0_1131( + .A1(n_1_0_1079), .A2(n_1_0_1078), .A3(n_1_0_1077), .ZN(n_1_0_1076) + ); + SDFF_X1_LVT \registers_reg[19][22] ( + .CK(n_0_49), .D(registers[22]), .Q(registers_19__ap[22]), .QN(), .SE(dftIn), + .SI(registers_18__ap[22]) + ); + SDFF_X1_LVT \registers_reg[25][22] ( + .CK(n_0_55), .D(registers[22]), .Q(registers_25__ap[22]), .QN(), .SE(dftIn), + .SI(registers_24__ap[22]) + ); + AOI221_X1_LVT i_1_0_1130( + .A(n_1_0_1076), .B1(n_1_0_1295), .B2(registers_19__ap[22]), .C1(registers_25__ap[22]), + .C2(n_1_0_1269), .ZN(n_1_0_1075) + ); + SDFF_X1_LVT \registers_reg[7][22] ( + .CK(n_0_37), .D(registers[22]), .Q(registers_7__ap[22]), .QN(), .SE(dftIn), + .SI(registers_4__ap[22]) + ); + SDFF_X1_LVT \registers_reg[14][22] ( + .CK(n_0_44), .D(registers[22]), .Q(registers_14__ap[22]), .QN(), .SE(dftIn), + .SI(registers_16__ap[22]) + ); + AOI22_X1_LVT i_1_0_1129( + .A1(registers_7__ap[22]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[22]), + .ZN(n_1_0_1074) + ); + SDFF_X1_LVT \registers_reg[9][22] ( + .CK(n_0_39), .D(registers[22]), .Q(registers_9__ap[22]), .QN(), .SE(dftIn), + .SI(registers_7__ap[22]) + ); + SDFF_X1_LVT \registers_reg[29][22] ( + .CK(n_0_59), .D(registers[22]), .Q(registers_29__ap[22]), .QN(), .SE(dftIn), + .SI(registers_25__ap[22]) + ); + AOI22_X1_LVT i_1_0_1128( + .A1(registers_9__ap[22]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[22]), + .ZN(n_1_0_1073) + ); + SDFF_X1_LVT \registers_reg[8][22] ( + .CK(n_0_38), .D(registers[22]), .Q(registers_8__ap[22]), .QN(), .SE(dftIn), + .SI(registers_9__ap[22]) + ); + SDFF_X1_LVT \registers_reg[23][22] ( + .CK(n_0_53), .D(registers[22]), .Q(registers_23__ap[22]), .QN(), .SE(dftIn), + .SI(registers_19__ap[22]) + ); + AOI22_X1_LVT i_1_0_1127( + .A1(registers_8__ap[22]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[22]), + .ZN(n_1_0_1072) + ); + NAND3_X1_LVT i_1_0_1126( + .A1(n_1_0_1074), .A2(n_1_0_1073), .A3(n_1_0_1072), .ZN(n_1_0_1071) + ); + SDFF_X1_LVT \registers_reg[27][22] ( + .CK(n_0_57), .D(registers[22]), .Q(registers_27__ap[22]), .QN(), .SE(dftIn), + .SI(registers_29__ap[22]) + ); + SDFF_X1_LVT \registers_reg[3][22] ( + .CK(n_0_33), .D(registers[22]), .Q(registers_3__ap[22]), .QN(), .SE(dftIn), + .SI(registers_8__ap[22]) + ); + AOI221_X1_LVT i_1_0_1125( + .A(n_1_0_1071), .B1(n_1_0_1279), .B2(registers_27__ap[22]), .C1(registers_3__ap[22]), + .C2(n_1_0_1257), .ZN(n_1_0_1070) + ); + NAND4_X1_LVT i_1_0_1124( + .A1(n_1_0_1087), .A2(n_1_0_1080), .A3(n_1_0_1075), .A4(n_1_0_1070), .ZN(RRs1[22]) + ); + AND2_X1_LVT i_0_0_21( + .A1(n_0_0_16), .A2(WRd[21]), .ZN(registers[21]) + ); + SDFF_X1_LVT \registers_reg[17][21] ( + .CK(n_0_47), .D(registers[21]), .Q(registers_17__ap[21]), .QN(), .SE(dftIn), + .SI(registers_23__ap[22]) + ); + SDFF_X1_LVT \registers_reg[21][21] ( + .CK(n_0_51), .D(registers[21]), .Q(registers_21__ap[21]), .QN(), .SE(dftIn), + .SI(registers_17__ap[21]) + ); + AOI22_X1_LVT i_1_0_1122( + .A1(registers_17__ap[21]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[21]), + .ZN(n_1_0_1068) + ); + SDFF_X1_LVT \registers_reg[6][21] ( + .CK(n_0_36), .D(registers[21]), .Q(registers_6__ap[21]), .QN(), .SE(dftIn), + .SI(registers_3__ap[22]) + ); + SDFF_X1_LVT \registers_reg[8][21] ( + .CK(n_0_38), .D(registers[21]), .Q(registers_8__ap[21]), .QN(), .SE(dftIn), + .SI(registers_6__ap[21]) + ); + AOI22_X1_LVT i_1_0_1123( + .A1(registers_6__ap[21]), .A2(n_1_0_1300), .B1(n_1_0_1282), .B2(registers_8__ap[21]), + .ZN(n_1_0_1069) + ); + SDFF_X1_LVT \registers_reg[20][21] ( + .CK(n_0_50), .D(registers[21]), .Q(registers_20__ap[21]), .QN(), .SE(dftIn), + .SI(registers_21__ap[21]) + ); + SDFF_X1_LVT \registers_reg[12][21] ( + .CK(n_0_42), .D(registers[21]), .Q(registers_12__ap[21]), .QN(), .SE(dftIn), + .SI(registers_14__ap[22]) + ); + AOI22_X1_LVT i_1_0_1121( + .A1(registers_20__ap[21]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[21]), + .ZN(n_1_0_1067) + ); + SDFF_X1_LVT \registers_reg[5][21] ( + .CK(n_0_35), .D(registers[21]), .Q(registers_5__ap[21]), .QN(), .SE(dftIn), + .SI(registers_8__ap[21]) + ); + SDFF_X1_LVT \registers_reg[11][21] ( + .CK(n_0_41), .D(registers[21]), .Q(registers_11__ap[21]), .QN(), .SE(dftIn), + .SI(registers_12__ap[21]) + ); + AOI22_X1_LVT i_1_0_1120( + .A1(registers_5__ap[21]), .A2(n_1_0_1273), .B1(n_1_0_1270), .B2(registers_11__ap[21]), + .ZN(n_1_0_1066) + ); + NAND3_X1_LVT i_1_0_1119( + .A1(n_1_0_1069), .A2(n_1_0_1067), .A3(n_1_0_1066), .ZN(n_1_0_1065) + ); + SDFF_X1_LVT \registers_reg[10][21] ( + .CK(n_0_40), .D(registers[21]), .Q(registers_10__ap[21]), .QN(), .SE(dftIn), + .SI(registers_11__ap[21]) + ); + SDFF_X1_LVT \registers_reg[2][21] ( + .CK(n_0_32), .D(registers[21]), .Q(registers_2__ap[21]), .QN(), .SE(dftIn), + .SI(registers_27__ap[22]) + ); + AOI221_X1_LVT i_1_0_1118( + .A(n_1_0_1065), .B1(n_1_0_1287), .B2(registers_10__ap[21]), .C1(registers_2__ap[21]), + .C2(n_1_0_1268), .ZN(n_1_0_1064) + ); + SDFF_X1_LVT \registers_reg[13][21] ( + .CK(n_0_43), .D(registers[21]), .Q(registers_13__ap[21]), .QN(), .SE(dftIn), + .SI(registers_10__ap[21]) + ); + SDFF_X1_LVT \registers_reg[30][21] ( + .CK(n_0_60), .D(registers[21]), .Q(registers_30__ap[21]), .QN(), .SE(dftIn), + .SI(registers_2__ap[21]) + ); + SDFF_X1_LVT \registers_reg[22][21] ( + .CK(n_0_52), .D(registers[21]), .Q(registers_22__ap[21]), .QN(), .SE(dftIn), + .SI(registers_20__ap[21]) + ); + AOI222_X1_LVT i_1_0_1117( + .A1(registers_13__ap[21]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[21]), + .C1(registers_22__ap[21]), .C2(n_1_0_1294), .ZN(n_1_0_1063) + ); + NAND2_X1_LVT i_1_0_1116( + .A1(n_1_0_1064), .A2(n_1_0_1063), .ZN(n_1_0_1062) + ); + SDFF_X1_LVT \registers_reg[1][21] ( + .CK(n_0_0), .D(registers[21]), .Q(registers_1__ap[21]), .QN(), .SE(dftIn), + .SI(registers_22__ap[21]) + ); + SDFF_X1_LVT \registers_reg[28][21] ( + .CK(n_0_58), .D(registers[21]), .Q(registers_28__ap[21]), .QN(), .SE(dftIn), + .SI(registers_30__ap[21]) + ); + AOI221_X1_LVT i_1_0_1115( + .A(n_1_0_1062), .B1(n_1_0_1274), .B2(registers_1__ap[21]), .C1(registers_28__ap[21]), + .C2(n_1_0_1283), .ZN(n_1_0_1061) + ); + SDFF_X1_LVT \registers_reg[18][21] ( + .CK(n_0_48), .D(registers[21]), .Q(registers_18__ap[21]), .QN(), .SE(dftIn), + .SI(registers_1__ap[21]) + ); + SDFF_X1_LVT \registers_reg[26][21] ( + .CK(n_0_56), .D(registers[21]), .Q(registers_26__ap[21]), .QN(), .SE(dftIn), + .SI(registers_28__ap[21]) + ); + AOI22_X1_LVT i_1_0_1114( + .A1(registers_18__ap[21]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[21]), + .ZN(n_1_0_1060) + ); + SDFF_X1_LVT \registers_reg[24][21] ( + .CK(n_0_54), .D(registers[21]), .Q(registers_24__ap[21]), .QN(), .SE(dftIn), + .SI(registers_26__ap[21]) + ); + SDFF_X1_LVT \registers_reg[4][21] ( + .CK(n_0_34), .D(registers[21]), .Q(registers_4__ap[21]), .QN(), .SE(dftIn), + .SI(registers_5__ap[21]) + ); + AOI22_X1_LVT i_1_0_1113( + .A1(registers_24__ap[21]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[21]), + .ZN(n_1_0_1059) + ); + SDFF_X1_LVT \registers_reg[15][21] ( + .CK(n_0_45), .D(registers[21]), .Q(registers_15__ap[21]), .QN(), .SE(dftIn), + .SI(registers_13__ap[21]) + ); + SDFF_X1_LVT \registers_reg[16][21] ( + .CK(n_0_46), .D(registers[21]), .Q(registers_16__ap[21]), .QN(), .SE(dftIn), + .SI(registers_15__ap[21]) + ); + AOI22_X1_LVT i_1_0_1112( + .A1(registers_15__ap[21]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[21]), + .ZN(n_1_0_1058) + ); + NAND3_X1_LVT i_1_0_1111( + .A1(n_1_0_1060), .A2(n_1_0_1059), .A3(n_1_0_1058), .ZN(n_1_0_1057) + ); + SDFF_X1_LVT \registers_reg[19][21] ( + .CK(n_0_49), .D(registers[21]), .Q(registers_19__ap[21]), .QN(), .SE(dftIn), + .SI(registers_18__ap[21]) + ); + SDFF_X1_LVT \registers_reg[25][21] ( + .CK(n_0_55), .D(registers[21]), .Q(registers_25__ap[21]), .QN(), .SE(dftIn), + .SI(registers_24__ap[21]) + ); + AOI221_X1_LVT i_1_0_1110( + .A(n_1_0_1057), .B1(n_1_0_1295), .B2(registers_19__ap[21]), .C1(registers_25__ap[21]), + .C2(n_1_0_1269), .ZN(n_1_0_1056) + ); + SDFF_X1_LVT \registers_reg[7][21] ( + .CK(n_0_37), .D(registers[21]), .Q(registers_7__ap[21]), .QN(), .SE(dftIn), + .SI(registers_4__ap[21]) + ); + SDFF_X1_LVT \registers_reg[14][21] ( + .CK(n_0_44), .D(registers[21]), .Q(registers_14__ap[21]), .QN(), .SE(dftIn), + .SI(registers_16__ap[21]) + ); + AOI22_X1_LVT i_1_0_1109( + .A1(registers_7__ap[21]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[21]), + .ZN(n_1_0_1055) + ); + SDFF_X1_LVT \registers_reg[9][21] ( + .CK(n_0_39), .D(registers[21]), .Q(registers_9__ap[21]), .QN(), .SE(dftIn), + .SI(registers_7__ap[21]) + ); + SDFF_X1_LVT \registers_reg[29][21] ( + .CK(n_0_59), .D(registers[21]), .Q(registers_29__ap[21]), .QN(), .SE(dftIn), + .SI(registers_25__ap[21]) + ); + AOI22_X1_LVT i_1_0_1108( + .A1(registers_9__ap[21]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[21]), + .ZN(n_1_0_1054) + ); + SDFF_X1_LVT \registers_reg[23][21] ( + .CK(n_0_53), .D(registers[21]), .Q(registers_23__ap[21]), .QN(), .SE(dftIn), + .SI(registers_19__ap[21]) + ); + SDFF_X1_LVT \registers_reg[3][21] ( + .CK(n_0_33), .D(registers[21]), .Q(registers_3__ap[21]), .QN(), .SE(dftIn), + .SI(registers_9__ap[21]) + ); + AOI22_X1_LVT i_1_0_1107( + .A1(registers_23__ap[21]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[21]), + .ZN(n_1_0_1053) + ); + NAND3_X1_LVT i_1_0_1106( + .A1(n_1_0_1055), .A2(n_1_0_1054), .A3(n_1_0_1053), .ZN(n_1_0_1052) + ); + SDFF_X1_LVT \registers_reg[27][21] ( + .CK(n_0_57), .D(registers[21]), .Q(registers_27__ap[21]), .QN(), .SE(dftIn), + .SI(registers_29__ap[21]) + ); + SDFF_X1_LVT \registers_reg[31][21] ( + .CK(n_0_61), .D(registers[21]), .Q(registers_31__ap[21]), .QN(), .SE(dftIn), + .SI(registers_3__ap[21]) + ); + AOI221_X1_LVT i_1_0_1105( + .A(n_1_0_1052), .B1(n_1_0_1279), .B2(registers_27__ap[21]), .C1(registers_31__ap[21]), + .C2(n_1_0_1266), .ZN(n_1_0_1051) + ); + NAND4_X1_LVT i_1_0_1104( + .A1(n_1_0_1068), .A2(n_1_0_1061), .A3(n_1_0_1056), .A4(n_1_0_1051), .ZN(RRs1[21]) + ); + AND2_X1_LVT i_0_0_20( + .A1(n_0_0_16), .A2(WRd[20]), .ZN(registers[20]) + ); + SDFF_X1_LVT \registers_reg[17][20] ( + .CK(n_0_47), .D(registers[20]), .Q(registers_17__ap[20]), .QN(), .SE(dftIn), + .SI(registers_23__ap[21]) + ); + SDFF_X1_LVT \registers_reg[21][20] ( + .CK(n_0_51), .D(registers[20]), .Q(registers_21__ap[20]), .QN(), .SE(dftIn), + .SI(registers_17__ap[20]) + ); + AOI22_X1_LVT i_1_0_1100( + .A1(registers_17__ap[20]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[20]), + .ZN(n_1_0_1047) + ); + SDFF_X1_LVT \registers_reg[10][20] ( + .CK(n_0_40), .D(registers[20]), .Q(registers_10__ap[20]), .QN(), .SE(dftIn), + .SI(registers_14__ap[21]) + ); + SDFF_X1_LVT \registers_reg[2][20] ( + .CK(n_0_32), .D(registers[20]), .Q(registers_2__ap[20]), .QN(), .SE(dftIn), + .SI(registers_27__ap[21]) + ); + AOI22_X1_LVT i_1_0_1103( + .A1(registers_10__ap[20]), .A2(n_1_0_1287), .B1(n_1_0_1268), .B2(registers_2__ap[20]), + .ZN(n_1_0_1050) + ); + SDFF_X1_LVT \registers_reg[20][20] ( + .CK(n_0_50), .D(registers[20]), .Q(registers_20__ap[20]), .QN(), .SE(dftIn), + .SI(registers_21__ap[20]) + ); + SDFF_X1_LVT \registers_reg[12][20] ( + .CK(n_0_42), .D(registers[20]), .Q(registers_12__ap[20]), .QN(), .SE(dftIn), + .SI(registers_10__ap[20]) + ); + AOI22_X1_LVT i_1_0_1099( + .A1(registers_20__ap[20]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[20]), + .ZN(n_1_0_1046) + ); + SDFF_X1_LVT \registers_reg[15][20] ( + .CK(n_0_45), .D(registers[20]), .Q(registers_15__ap[20]), .QN(), .SE(dftIn), + .SI(registers_12__ap[20]) + ); + SDFF_X1_LVT \registers_reg[8][20] ( + .CK(n_0_38), .D(registers[20]), .Q(registers_8__ap[20]), .QN(), .SE(dftIn), + .SI(registers_31__ap[21]) + ); + AOI22_X1_LVT i_1_0_1102( + .A1(registers_15__ap[20]), .A2(n_1_0_1286), .B1(n_1_0_1282), .B2(registers_8__ap[20]), + .ZN(n_1_0_1049) + ); + INV_X1_LVT i_1_0_1101( + .A(n_1_0_1049), .ZN(n_1_0_1048) + ); + SDFF_X1_LVT \registers_reg[11][20] ( + .CK(n_0_41), .D(registers[20]), .Q(registers_11__ap[20]), .QN(), .SE(dftIn), + .SI(registers_15__ap[20]) + ); + SDFF_X1_LVT \registers_reg[5][20] ( + .CK(n_0_35), .D(registers[20]), .Q(registers_5__ap[20]), .QN(), .SE(dftIn), + .SI(registers_8__ap[20]) + ); + AOI221_X1_LVT i_1_0_1098( + .A(n_1_0_1048), .B1(n_1_0_1270), .B2(registers_11__ap[20]), .C1(registers_5__ap[20]), + .C2(n_1_0_1273), .ZN(n_1_0_1045) + ); + SDFF_X1_LVT \registers_reg[13][20] ( + .CK(n_0_43), .D(registers[20]), .Q(registers_13__ap[20]), .QN(), .SE(dftIn), + .SI(registers_11__ap[20]) + ); + SDFF_X1_LVT \registers_reg[30][20] ( + .CK(n_0_60), .D(registers[20]), .Q(registers_30__ap[20]), .QN(), .SE(dftIn), + .SI(registers_2__ap[20]) + ); + SDFF_X1_LVT \registers_reg[22][20] ( + .CK(n_0_52), .D(registers[20]), .Q(registers_22__ap[20]), .QN(), .SE(dftIn), + .SI(registers_20__ap[20]) + ); + AOI222_X1_LVT i_1_0_1097( + .A1(registers_13__ap[20]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[20]), + .C1(registers_22__ap[20]), .C2(n_1_0_1294), .ZN(n_1_0_1044) + ); + NAND4_X1_LVT i_1_0_1096( + .A1(n_1_0_1050), .A2(n_1_0_1046), .A3(n_1_0_1045), .A4(n_1_0_1044), .ZN(n_1_0_1043) + ); + SDFF_X1_LVT \registers_reg[1][20] ( + .CK(n_0_0), .D(registers[20]), .Q(registers_1__ap[20]), .QN(), .SE(dftIn), + .SI(registers_22__ap[20]) + ); + SDFF_X1_LVT \registers_reg[28][20] ( + .CK(n_0_58), .D(registers[20]), .Q(registers_28__ap[20]), .QN(), .SE(dftIn), + .SI(registers_30__ap[20]) + ); + AOI221_X1_LVT i_1_0_1095( + .A(n_1_0_1043), .B1(n_1_0_1274), .B2(registers_1__ap[20]), .C1(registers_28__ap[20]), + .C2(n_1_0_1283), .ZN(n_1_0_1042) + ); + SDFF_X1_LVT \registers_reg[18][20] ( + .CK(n_0_48), .D(registers[20]), .Q(registers_18__ap[20]), .QN(), .SE(dftIn), + .SI(registers_1__ap[20]) + ); + SDFF_X1_LVT \registers_reg[26][20] ( + .CK(n_0_56), .D(registers[20]), .Q(registers_26__ap[20]), .QN(), .SE(dftIn), + .SI(registers_28__ap[20]) + ); + AOI22_X1_LVT i_1_0_1094( + .A1(registers_18__ap[20]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[20]), + .ZN(n_1_0_1041) + ); + SDFF_X1_LVT \registers_reg[24][20] ( + .CK(n_0_54), .D(registers[20]), .Q(registers_24__ap[20]), .QN(), .SE(dftIn), + .SI(registers_26__ap[20]) + ); + SDFF_X1_LVT \registers_reg[4][20] ( + .CK(n_0_34), .D(registers[20]), .Q(registers_4__ap[20]), .QN(), .SE(dftIn), + .SI(registers_5__ap[20]) + ); + AOI22_X1_LVT i_1_0_1093( + .A1(registers_24__ap[20]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[20]), + .ZN(n_1_0_1040) + ); + SDFF_X1_LVT \registers_reg[6][20] ( + .CK(n_0_36), .D(registers[20]), .Q(registers_6__ap[20]), .QN(), .SE(dftIn), + .SI(registers_4__ap[20]) + ); + SDFF_X1_LVT \registers_reg[25][20] ( + .CK(n_0_55), .D(registers[20]), .Q(registers_25__ap[20]), .QN(), .SE(dftIn), + .SI(registers_24__ap[20]) + ); + AOI22_X1_LVT i_1_0_1092( + .A1(registers_6__ap[20]), .A2(n_1_0_1300), .B1(n_1_0_1269), .B2(registers_25__ap[20]), + .ZN(n_1_0_1039) + ); + NAND3_X1_LVT i_1_0_1091( + .A1(n_1_0_1041), .A2(n_1_0_1040), .A3(n_1_0_1039), .ZN(n_1_0_1038) + ); + SDFF_X1_LVT \registers_reg[19][20] ( + .CK(n_0_49), .D(registers[20]), .Q(registers_19__ap[20]), .QN(), .SE(dftIn), + .SI(registers_18__ap[20]) + ); + SDFF_X1_LVT \registers_reg[16][20] ( + .CK(n_0_46), .D(registers[20]), .Q(registers_16__ap[20]), .QN(), .SE(dftIn), + .SI(registers_13__ap[20]) + ); + AOI221_X1_LVT i_1_0_1090( + .A(n_1_0_1038), .B1(n_1_0_1295), .B2(registers_19__ap[20]), .C1(registers_16__ap[20]), + .C2(n_1_0_1267), .ZN(n_1_0_1037) + ); + SDFF_X1_LVT \registers_reg[7][20] ( + .CK(n_0_37), .D(registers[20]), .Q(registers_7__ap[20]), .QN(), .SE(dftIn), + .SI(registers_6__ap[20]) + ); + SDFF_X1_LVT \registers_reg[14][20] ( + .CK(n_0_44), .D(registers[20]), .Q(registers_14__ap[20]), .QN(), .SE(dftIn), + .SI(registers_16__ap[20]) + ); + AOI22_X1_LVT i_1_0_1089( + .A1(registers_7__ap[20]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[20]), + .ZN(n_1_0_1036) + ); + SDFF_X1_LVT \registers_reg[9][20] ( + .CK(n_0_39), .D(registers[20]), .Q(registers_9__ap[20]), .QN(), .SE(dftIn), + .SI(registers_7__ap[20]) + ); + SDFF_X1_LVT \registers_reg[29][20] ( + .CK(n_0_59), .D(registers[20]), .Q(registers_29__ap[20]), .QN(), .SE(dftIn), + .SI(registers_25__ap[20]) + ); + AOI22_X1_LVT i_1_0_1088( + .A1(registers_9__ap[20]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[20]), + .ZN(n_1_0_1035) + ); + SDFF_X1_LVT \registers_reg[23][20] ( + .CK(n_0_53), .D(registers[20]), .Q(registers_23__ap[20]), .QN(), .SE(dftIn), + .SI(registers_19__ap[20]) + ); + SDFF_X1_LVT \registers_reg[3][20] ( + .CK(n_0_33), .D(registers[20]), .Q(registers_3__ap[20]), .QN(), .SE(dftIn), + .SI(registers_9__ap[20]) + ); + AOI22_X1_LVT i_1_0_1087( + .A1(registers_23__ap[20]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[20]), + .ZN(n_1_0_1034) + ); + NAND3_X1_LVT i_1_0_1086( + .A1(n_1_0_1036), .A2(n_1_0_1035), .A3(n_1_0_1034), .ZN(n_1_0_1033) + ); + SDFF_X1_LVT \registers_reg[27][20] ( + .CK(n_0_57), .D(registers[20]), .Q(registers_27__ap[20]), .QN(), .SE(dftIn), + .SI(registers_29__ap[20]) + ); + SDFF_X1_LVT \registers_reg[31][20] ( + .CK(n_0_61), .D(registers[20]), .Q(registers_31__ap[20]), .QN(), .SE(dftIn), + .SI(registers_3__ap[20]) + ); + AOI221_X1_LVT i_1_0_1085( + .A(n_1_0_1033), .B1(n_1_0_1279), .B2(registers_27__ap[20]), .C1(registers_31__ap[20]), + .C2(n_1_0_1266), .ZN(n_1_0_1032) + ); + NAND4_X1_LVT i_1_0_1084( + .A1(n_1_0_1047), .A2(n_1_0_1042), .A3(n_1_0_1037), .A4(n_1_0_1032), .ZN(RRs1[20]) + ); + AND2_X1_LVT i_0_0_19( + .A1(n_0_0_16), .A2(WRd[19]), .ZN(registers[19]) + ); + SDFF_X1_LVT \registers_reg[17][19] ( + .CK(n_0_47), .D(registers[19]), .Q(registers_17__ap[19]), .QN(), .SE(dftIn), + .SI(registers_23__ap[20]) + ); + SDFF_X1_LVT \registers_reg[21][19] ( + .CK(n_0_51), .D(registers[19]), .Q(registers_21__ap[19]), .QN(), .SE(dftIn), + .SI(registers_17__ap[19]) + ); + AOI22_X1_LVT i_1_0_1080( + .A1(registers_17__ap[19]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[19]), + .ZN(n_1_0_1028) + ); + SDFF_X1_LVT \registers_reg[2][19] ( + .CK(n_0_32), .D(registers[19]), .Q(registers_2__ap[19]), .QN(), .SE(dftIn), + .SI(registers_27__ap[20]) + ); + SDFF_X1_LVT \registers_reg[31][19] ( + .CK(n_0_61), .D(registers[19]), .Q(registers_31__ap[19]), .QN(), .SE(dftIn), + .SI(registers_31__ap[20]) + ); + AOI22_X1_LVT i_1_0_1083( + .A1(registers_2__ap[19]), .A2(n_1_0_1268), .B1(n_1_0_1266), .B2(registers_31__ap[19]), + .ZN(n_1_0_1031) + ); + SDFF_X1_LVT \registers_reg[20][19] ( + .CK(n_0_50), .D(registers[19]), .Q(registers_20__ap[19]), .QN(), .SE(dftIn), + .SI(registers_21__ap[19]) + ); + SDFF_X1_LVT \registers_reg[12][19] ( + .CK(n_0_42), .D(registers[19]), .Q(registers_12__ap[19]), .QN(), .SE(dftIn), + .SI(registers_14__ap[20]) + ); + AOI22_X1_LVT i_1_0_1079( + .A1(registers_20__ap[19]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[19]), + .ZN(n_1_0_1027) + ); + SDFF_X1_LVT \registers_reg[15][19] ( + .CK(n_0_45), .D(registers[19]), .Q(registers_15__ap[19]), .QN(), .SE(dftIn), + .SI(registers_12__ap[19]) + ); + SDFF_X1_LVT \registers_reg[11][19] ( + .CK(n_0_41), .D(registers[19]), .Q(registers_11__ap[19]), .QN(), .SE(dftIn), + .SI(registers_15__ap[19]) + ); + AOI22_X1_LVT i_1_0_1082( + .A1(registers_15__ap[19]), .A2(n_1_0_1286), .B1(n_1_0_1270), .B2(registers_11__ap[19]), + .ZN(n_1_0_1030) + ); + INV_X1_LVT i_1_0_1081( + .A(n_1_0_1030), .ZN(n_1_0_1029) + ); + SDFF_X1_LVT \registers_reg[27][19] ( + .CK(n_0_57), .D(registers[19]), .Q(registers_27__ap[19]), .QN(), .SE(dftIn), + .SI(registers_2__ap[19]) + ); + SDFF_X1_LVT \registers_reg[24][19] ( + .CK(n_0_54), .D(registers[19]), .Q(registers_24__ap[19]), .QN(), .SE(dftIn), + .SI(registers_27__ap[19]) + ); + AOI221_X1_LVT i_1_0_1078( + .A(n_1_0_1029), .B1(n_1_0_1279), .B2(registers_27__ap[19]), .C1(registers_24__ap[19]), + .C2(n_1_0_1289), .ZN(n_1_0_1026) + ); + SDFF_X1_LVT \registers_reg[22][19] ( + .CK(n_0_52), .D(registers[19]), .Q(registers_22__ap[19]), .QN(), .SE(dftIn), + .SI(registers_20__ap[19]) + ); + SDFF_X1_LVT \registers_reg[26][19] ( + .CK(n_0_56), .D(registers[19]), .Q(registers_26__ap[19]), .QN(), .SE(dftIn), + .SI(registers_24__ap[19]) + ); + SDFF_X1_LVT \registers_reg[13][19] ( + .CK(n_0_43), .D(registers[19]), .Q(registers_13__ap[19]), .QN(), .SE(dftIn), + .SI(registers_11__ap[19]) + ); + AOI222_X1_LVT i_1_0_1077( + .A1(registers_22__ap[19]), .A2(n_1_0_1294), .B1(n_1_0_1285), .B2(registers_26__ap[19]), + .C1(n_1_0_1277), .C2(registers_13__ap[19]), .ZN(n_1_0_1025) + ); + NAND4_X1_LVT i_1_0_1076( + .A1(n_1_0_1031), .A2(n_1_0_1027), .A3(n_1_0_1026), .A4(n_1_0_1025), .ZN(n_1_0_1024) + ); + SDFF_X1_LVT \registers_reg[1][19] ( + .CK(n_0_0), .D(registers[19]), .Q(registers_1__ap[19]), .QN(), .SE(dftIn), + .SI(registers_22__ap[19]) + ); + SDFF_X1_LVT \registers_reg[28][19] ( + .CK(n_0_58), .D(registers[19]), .Q(registers_28__ap[19]), .QN(), .SE(dftIn), + .SI(registers_26__ap[19]) + ); + AOI221_X1_LVT i_1_0_1075( + .A(n_1_0_1024), .B1(n_1_0_1274), .B2(registers_1__ap[19]), .C1(registers_28__ap[19]), + .C2(n_1_0_1283), .ZN(n_1_0_1023) + ); + SDFF_X1_LVT \registers_reg[18][19] ( + .CK(n_0_48), .D(registers[19]), .Q(registers_18__ap[19]), .QN(), .SE(dftIn), + .SI(registers_1__ap[19]) + ); + SDFF_X1_LVT \registers_reg[30][19] ( + .CK(n_0_60), .D(registers[19]), .Q(registers_30__ap[19]), .QN(), .SE(dftIn), + .SI(registers_28__ap[19]) + ); + AOI22_X1_LVT i_1_0_1074( + .A1(registers_18__ap[19]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[19]), + .ZN(n_1_0_1022) + ); + SDFF_X1_LVT \registers_reg[4][19] ( + .CK(n_0_34), .D(registers[19]), .Q(registers_4__ap[19]), .QN(), .SE(dftIn), + .SI(registers_31__ap[19]) + ); + SDFF_X1_LVT \registers_reg[5][19] ( + .CK(n_0_35), .D(registers[19]), .Q(registers_5__ap[19]), .QN(), .SE(dftIn), + .SI(registers_4__ap[19]) + ); + AOI22_X1_LVT i_1_0_1073( + .A1(registers_4__ap[19]), .A2(n_1_0_1278), .B1(n_1_0_1273), .B2(registers_5__ap[19]), + .ZN(n_1_0_1021) + ); + SDFF_X1_LVT \registers_reg[6][19] ( + .CK(n_0_36), .D(registers[19]), .Q(registers_6__ap[19]), .QN(), .SE(dftIn), + .SI(registers_5__ap[19]) + ); + SDFF_X1_LVT \registers_reg[25][19] ( + .CK(n_0_55), .D(registers[19]), .Q(registers_25__ap[19]), .QN(), .SE(dftIn), + .SI(registers_30__ap[19]) + ); + AOI22_X1_LVT i_1_0_1072( + .A1(registers_6__ap[19]), .A2(n_1_0_1300), .B1(n_1_0_1269), .B2(registers_25__ap[19]), + .ZN(n_1_0_1020) + ); + NAND3_X1_LVT i_1_0_1071( + .A1(n_1_0_1022), .A2(n_1_0_1021), .A3(n_1_0_1020), .ZN(n_1_0_1019) + ); + SDFF_X1_LVT \registers_reg[19][19] ( + .CK(n_0_49), .D(registers[19]), .Q(registers_19__ap[19]), .QN(), .SE(dftIn), + .SI(registers_18__ap[19]) + ); + SDFF_X1_LVT \registers_reg[16][19] ( + .CK(n_0_46), .D(registers[19]), .Q(registers_16__ap[19]), .QN(), .SE(dftIn), + .SI(registers_13__ap[19]) + ); + AOI221_X1_LVT i_1_0_1070( + .A(n_1_0_1019), .B1(n_1_0_1295), .B2(registers_19__ap[19]), .C1(registers_16__ap[19]), + .C2(n_1_0_1267), .ZN(n_1_0_1018) + ); + SDFF_X1_LVT \registers_reg[9][19] ( + .CK(n_0_39), .D(registers[19]), .Q(registers_9__ap[19]), .QN(), .SE(dftIn), + .SI(registers_6__ap[19]) + ); + SDFF_X1_LVT \registers_reg[29][19] ( + .CK(n_0_59), .D(registers[19]), .Q(registers_29__ap[19]), .QN(), .SE(dftIn), + .SI(registers_25__ap[19]) + ); + AOI22_X1_LVT i_1_0_1069( + .A1(registers_9__ap[19]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[19]), + .ZN(n_1_0_1017) + ); + SDFF_X1_LVT \registers_reg[8][19] ( + .CK(n_0_38), .D(registers[19]), .Q(registers_8__ap[19]), .QN(), .SE(dftIn), + .SI(registers_9__ap[19]) + ); + SDFF_X1_LVT \registers_reg[23][19] ( + .CK(n_0_53), .D(registers[19]), .Q(registers_23__ap[19]), .QN(), .SE(dftIn), + .SI(registers_19__ap[19]) + ); + AOI22_X1_LVT i_1_0_1068( + .A1(registers_8__ap[19]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[19]), + .ZN(n_1_0_1016) + ); + SDFF_X1_LVT \registers_reg[7][19] ( + .CK(n_0_37), .D(registers[19]), .Q(registers_7__ap[19]), .QN(), .SE(dftIn), + .SI(registers_8__ap[19]) + ); + SDFF_X1_LVT \registers_reg[14][19] ( + .CK(n_0_44), .D(registers[19]), .Q(registers_14__ap[19]), .QN(), .SE(dftIn), + .SI(registers_16__ap[19]) + ); + AOI22_X1_LVT i_1_0_1067( + .A1(registers_7__ap[19]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[19]), + .ZN(n_1_0_1015) + ); + NAND3_X1_LVT i_1_0_1066( + .A1(n_1_0_1017), .A2(n_1_0_1016), .A3(n_1_0_1015), .ZN(n_1_0_1014) + ); + SDFF_X1_LVT \registers_reg[10][19] ( + .CK(n_0_40), .D(registers[19]), .Q(registers_10__ap[19]), .QN(), .SE(dftIn), + .SI(registers_14__ap[19]) + ); + SDFF_X1_LVT \registers_reg[3][19] ( + .CK(n_0_33), .D(registers[19]), .Q(registers_3__ap[19]), .QN(), .SE(dftIn), + .SI(registers_7__ap[19]) + ); + AOI221_X1_LVT i_1_0_1065( + .A(n_1_0_1014), .B1(n_1_0_1287), .B2(registers_10__ap[19]), .C1(registers_3__ap[19]), + .C2(n_1_0_1257), .ZN(n_1_0_1013) + ); + NAND4_X1_LVT i_1_0_1064( + .A1(n_1_0_1028), .A2(n_1_0_1023), .A3(n_1_0_1018), .A4(n_1_0_1013), .ZN(RRs1[19]) + ); + AND2_X1_LVT i_0_0_18( + .A1(n_0_0_16), .A2(WRd[18]), .ZN(registers[18]) + ); + SDFF_X1_LVT \registers_reg[24][18] ( + .CK(n_0_54), .D(registers[18]), .Q(registers_24__ap[18]), .QN(), .SE(dftIn), + .SI(registers_29__ap[19]) + ); + SDFF_X1_LVT \registers_reg[28][18] ( + .CK(n_0_58), .D(registers[18]), .Q(registers_28__ap[18]), .QN(), .SE(dftIn), + .SI(registers_24__ap[18]) + ); + AOI22_X1_LVT i_1_0_1062( + .A1(registers_24__ap[18]), .A2(n_1_0_1289), .B1(n_1_0_1283), .B2(registers_28__ap[18]), + .ZN(n_1_0_1011) + ); + SDFF_X1_LVT \registers_reg[11][18] ( + .CK(n_0_41), .D(registers[18]), .Q(registers_11__ap[18]), .QN(), .SE(dftIn), + .SI(registers_10__ap[19]) + ); + SDFF_X1_LVT \registers_reg[16][18] ( + .CK(n_0_46), .D(registers[18]), .Q(registers_16__ap[18]), .QN(), .SE(dftIn), + .SI(registers_11__ap[18]) + ); + AOI22_X1_LVT i_1_0_1063( + .A1(registers_11__ap[18]), .A2(n_1_0_1270), .B1(n_1_0_1267), .B2(registers_16__ap[18]), + .ZN(n_1_0_1012) + ); + SDFF_X1_LVT \registers_reg[9][18] ( + .CK(n_0_39), .D(registers[18]), .Q(registers_9__ap[18]), .QN(), .SE(dftIn), + .SI(registers_3__ap[19]) + ); + SDFF_X1_LVT \registers_reg[7][18] ( + .CK(n_0_37), .D(registers[18]), .Q(registers_7__ap[18]), .QN(), .SE(dftIn), + .SI(registers_9__ap[18]) + ); + AOI22_X1_LVT i_1_0_1061( + .A1(registers_9__ap[18]), .A2(n_1_0_1291), .B1(n_1_0_1263), .B2(registers_7__ap[18]), + .ZN(n_1_0_1010) + ); + SDFF_X1_LVT \registers_reg[27][18] ( + .CK(n_0_57), .D(registers[18]), .Q(registers_27__ap[18]), .QN(), .SE(dftIn), + .SI(registers_28__ap[18]) + ); + SDFF_X1_LVT \registers_reg[25][18] ( + .CK(n_0_55), .D(registers[18]), .Q(registers_25__ap[18]), .QN(), .SE(dftIn), + .SI(registers_27__ap[18]) + ); + AOI22_X1_LVT i_1_0_1060( + .A1(registers_27__ap[18]), .A2(n_1_0_1279), .B1(n_1_0_1269), .B2(registers_25__ap[18]), + .ZN(n_1_0_1009) + ); + NAND3_X1_LVT i_1_0_1059( + .A1(n_1_0_1012), .A2(n_1_0_1010), .A3(n_1_0_1009), .ZN(n_1_0_1008) + ); + SDFF_X1_LVT \registers_reg[31][18] ( + .CK(n_0_61), .D(registers[18]), .Q(registers_31__ap[18]), .QN(), .SE(dftIn), + .SI(registers_7__ap[18]) + ); + SDFF_X1_LVT \registers_reg[6][18] ( + .CK(n_0_36), .D(registers[18]), .Q(registers_6__ap[18]), .QN(), .SE(dftIn), + .SI(registers_31__ap[18]) + ); + AOI221_X1_LVT i_1_0_1058( + .A(n_1_0_1008), .B1(n_1_0_1266), .B2(registers_31__ap[18]), .C1(registers_6__ap[18]), + .C2(n_1_0_1300), .ZN(n_1_0_1007) + ); + SDFF_X1_LVT \registers_reg[22][18] ( + .CK(n_0_52), .D(registers[18]), .Q(registers_22__ap[18]), .QN(), .SE(dftIn), + .SI(registers_23__ap[19]) + ); + SDFF_X1_LVT \registers_reg[26][18] ( + .CK(n_0_56), .D(registers[18]), .Q(registers_26__ap[18]), .QN(), .SE(dftIn), + .SI(registers_25__ap[18]) + ); + SDFF_X1_LVT \registers_reg[1][18] ( + .CK(n_0_0), .D(registers[18]), .Q(registers_1__ap[18]), .QN(), .SE(dftIn), + .SI(registers_22__ap[18]) + ); + AOI222_X1_LVT i_1_0_1057( + .A1(registers_22__ap[18]), .A2(n_1_0_1294), .B1(n_1_0_1285), .B2(registers_26__ap[18]), + .C1(n_1_0_1274), .C2(registers_1__ap[18]), .ZN(n_1_0_1006) + ); + NAND2_X1_LVT i_1_0_1056( + .A1(n_1_0_1007), .A2(n_1_0_1006), .ZN(n_1_0_1005) + ); + SDFF_X1_LVT \registers_reg[29][18] ( + .CK(n_0_59), .D(registers[18]), .Q(registers_29__ap[18]), .QN(), .SE(dftIn), + .SI(registers_26__ap[18]) + ); + SDFF_X1_LVT \registers_reg[2][18] ( + .CK(n_0_32), .D(registers[18]), .Q(registers_2__ap[18]), .QN(), .SE(dftIn), + .SI(registers_29__ap[18]) + ); + AOI221_X1_LVT i_1_0_1055( + .A(n_1_0_1005), .B1(n_1_0_1276), .B2(registers_29__ap[18]), .C1(registers_2__ap[18]), + .C2(n_1_0_1268), .ZN(n_1_0_1004) + ); + SDFF_X1_LVT \registers_reg[18][18] ( + .CK(n_0_48), .D(registers[18]), .Q(registers_18__ap[18]), .QN(), .SE(dftIn), + .SI(registers_1__ap[18]) + ); + SDFF_X1_LVT \registers_reg[30][18] ( + .CK(n_0_60), .D(registers[18]), .Q(registers_30__ap[18]), .QN(), .SE(dftIn), + .SI(registers_2__ap[18]) + ); + AOI22_X1_LVT i_1_0_1054( + .A1(registers_18__ap[18]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[18]), + .ZN(n_1_0_1003) + ); + SDFF_X1_LVT \registers_reg[4][18] ( + .CK(n_0_34), .D(registers[18]), .Q(registers_4__ap[18]), .QN(), .SE(dftIn), + .SI(registers_6__ap[18]) + ); + SDFF_X1_LVT \registers_reg[12][18] ( + .CK(n_0_42), .D(registers[18]), .Q(registers_12__ap[18]), .QN(), .SE(dftIn), + .SI(registers_16__ap[18]) + ); + AOI22_X1_LVT i_1_0_1053( + .A1(registers_4__ap[18]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[18]), + .ZN(n_1_0_1002) + ); + SDFF_X1_LVT \registers_reg[19][18] ( + .CK(n_0_49), .D(registers[18]), .Q(registers_19__ap[18]), .QN(), .SE(dftIn), + .SI(registers_18__ap[18]) + ); + SDFF_X1_LVT \registers_reg[21][18] ( + .CK(n_0_51), .D(registers[18]), .Q(registers_21__ap[18]), .QN(), .SE(dftIn), + .SI(registers_19__ap[18]) + ); + AOI22_X1_LVT i_1_0_1052( + .A1(registers_19__ap[18]), .A2(n_1_0_1295), .B1(n_1_0_1259), .B2(registers_21__ap[18]), + .ZN(n_1_0_1001) + ); + NAND3_X1_LVT i_1_0_1051( + .A1(n_1_0_1003), .A2(n_1_0_1002), .A3(n_1_0_1001), .ZN(n_1_0_1000) + ); + SDFF_X1_LVT \registers_reg[5][18] ( + .CK(n_0_35), .D(registers[18]), .Q(registers_5__ap[18]), .QN(), .SE(dftIn), + .SI(registers_4__ap[18]) + ); + SDFF_X1_LVT \registers_reg[20][18] ( + .CK(n_0_50), .D(registers[18]), .Q(registers_20__ap[18]), .QN(), .SE(dftIn), + .SI(registers_21__ap[18]) + ); + AOI221_X1_LVT i_1_0_1050( + .A(n_1_0_1000), .B1(n_1_0_1273), .B2(registers_5__ap[18]), .C1(registers_20__ap[18]), + .C2(n_1_0_1281), .ZN(n_1_0_999) + ); + SDFF_X1_LVT \registers_reg[8][18] ( + .CK(n_0_38), .D(registers[18]), .Q(registers_8__ap[18]), .QN(), .SE(dftIn), + .SI(registers_5__ap[18]) + ); + SDFF_X1_LVT \registers_reg[23][18] ( + .CK(n_0_53), .D(registers[18]), .Q(registers_23__ap[18]), .QN(), .SE(dftIn), + .SI(registers_20__ap[18]) + ); + AOI22_X1_LVT i_1_0_1049( + .A1(registers_8__ap[18]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[18]), + .ZN(n_1_0_998) + ); + SDFF_X1_LVT \registers_reg[13][18] ( + .CK(n_0_43), .D(registers[18]), .Q(registers_13__ap[18]), .QN(), .SE(dftIn), + .SI(registers_12__ap[18]) + ); + SDFF_X1_LVT \registers_reg[17][18] ( + .CK(n_0_47), .D(registers[18]), .Q(registers_17__ap[18]), .QN(), .SE(dftIn), + .SI(registers_23__ap[18]) + ); + AOI22_X1_LVT i_1_0_1048( + .A1(registers_13__ap[18]), .A2(n_1_0_1277), .B1(n_1_0_1271), .B2(registers_17__ap[18]), + .ZN(n_1_0_997) + ); + SDFF_X1_LVT \registers_reg[15][18] ( + .CK(n_0_45), .D(registers[18]), .Q(registers_15__ap[18]), .QN(), .SE(dftIn), + .SI(registers_13__ap[18]) + ); + SDFF_X1_LVT \registers_reg[14][18] ( + .CK(n_0_44), .D(registers[18]), .Q(registers_14__ap[18]), .QN(), .SE(dftIn), + .SI(registers_15__ap[18]) + ); + AOI22_X1_LVT i_1_0_1047( + .A1(registers_15__ap[18]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[18]), + .ZN(n_1_0_996) + ); + NAND3_X1_LVT i_1_0_1046( + .A1(n_1_0_998), .A2(n_1_0_997), .A3(n_1_0_996), .ZN(n_1_0_995) + ); + SDFF_X1_LVT \registers_reg[10][18] ( + .CK(n_0_40), .D(registers[18]), .Q(registers_10__ap[18]), .QN(), .SE(dftIn), + .SI(registers_14__ap[18]) + ); + SDFF_X1_LVT \registers_reg[3][18] ( + .CK(n_0_33), .D(registers[18]), .Q(registers_3__ap[18]), .QN(), .SE(dftIn), + .SI(registers_8__ap[18]) + ); + AOI221_X1_LVT i_1_0_1045( + .A(n_1_0_995), .B1(n_1_0_1287), .B2(registers_10__ap[18]), .C1(registers_3__ap[18]), + .C2(n_1_0_1257), .ZN(n_1_0_994) + ); + NAND4_X1_LVT i_1_0_1044( + .A1(n_1_0_1011), .A2(n_1_0_1004), .A3(n_1_0_999), .A4(n_1_0_994), .ZN(RRs1[18]) + ); + AND2_X1_LVT i_0_0_17( + .A1(n_0_0_16), .A2(WRd[17]), .ZN(registers[17]) + ); + SDFF_X1_LVT \registers_reg[17][17] ( + .CK(n_0_47), .D(registers[17]), .Q(registers_17__ap[17]), .QN(), .SE(dftIn), + .SI(registers_17__ap[18]) + ); + SDFF_X1_LVT \registers_reg[21][17] ( + .CK(n_0_51), .D(registers[17]), .Q(registers_21__ap[17]), .QN(), .SE(dftIn), + .SI(registers_17__ap[17]) + ); + AOI22_X1_LVT i_1_0_1040( + .A1(registers_17__ap[17]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[17]), + .ZN(n_1_0_990) + ); + SDFF_X1_LVT \registers_reg[2][17] ( + .CK(n_0_32), .D(registers[17]), .Q(registers_2__ap[17]), .QN(), .SE(dftIn), + .SI(registers_30__ap[18]) + ); + SDFF_X1_LVT \registers_reg[31][17] ( + .CK(n_0_61), .D(registers[17]), .Q(registers_31__ap[17]), .QN(), .SE(dftIn), + .SI(registers_3__ap[18]) + ); + AOI22_X1_LVT i_1_0_1043( + .A1(registers_2__ap[17]), .A2(n_1_0_1268), .B1(n_1_0_1266), .B2(registers_31__ap[17]), + .ZN(n_1_0_993) + ); + SDFF_X1_LVT \registers_reg[20][17] ( + .CK(n_0_50), .D(registers[17]), .Q(registers_20__ap[17]), .QN(), .SE(dftIn), + .SI(registers_21__ap[17]) + ); + SDFF_X1_LVT \registers_reg[12][17] ( + .CK(n_0_42), .D(registers[17]), .Q(registers_12__ap[17]), .QN(), .SE(dftIn), + .SI(registers_10__ap[18]) + ); + AOI22_X1_LVT i_1_0_1039( + .A1(registers_20__ap[17]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[17]), + .ZN(n_1_0_989) + ); + SDFF_X1_LVT \registers_reg[15][17] ( + .CK(n_0_45), .D(registers[17]), .Q(registers_15__ap[17]), .QN(), .SE(dftIn), + .SI(registers_12__ap[17]) + ); + SDFF_X1_LVT \registers_reg[11][17] ( + .CK(n_0_41), .D(registers[17]), .Q(registers_11__ap[17]), .QN(), .SE(dftIn), + .SI(registers_15__ap[17]) + ); + AOI22_X1_LVT i_1_0_1042( + .A1(registers_15__ap[17]), .A2(n_1_0_1286), .B1(n_1_0_1270), .B2(registers_11__ap[17]), + .ZN(n_1_0_992) + ); + INV_X1_LVT i_1_0_1041( + .A(n_1_0_992), .ZN(n_1_0_991) + ); + SDFF_X1_LVT \registers_reg[10][17] ( + .CK(n_0_40), .D(registers[17]), .Q(registers_10__ap[17]), .QN(), .SE(dftIn), + .SI(registers_11__ap[17]) + ); + SDFF_X1_LVT \registers_reg[24][17] ( + .CK(n_0_54), .D(registers[17]), .Q(registers_24__ap[17]), .QN(), .SE(dftIn), + .SI(registers_2__ap[17]) + ); + AOI221_X1_LVT i_1_0_1038( + .A(n_1_0_991), .B1(n_1_0_1287), .B2(registers_10__ap[17]), .C1(registers_24__ap[17]), + .C2(n_1_0_1289), .ZN(n_1_0_988) + ); + SDFF_X1_LVT \registers_reg[22][17] ( + .CK(n_0_52), .D(registers[17]), .Q(registers_22__ap[17]), .QN(), .SE(dftIn), + .SI(registers_20__ap[17]) + ); + SDFF_X1_LVT \registers_reg[26][17] ( + .CK(n_0_56), .D(registers[17]), .Q(registers_26__ap[17]), .QN(), .SE(dftIn), + .SI(registers_24__ap[17]) + ); + SDFF_X1_LVT \registers_reg[13][17] ( + .CK(n_0_43), .D(registers[17]), .Q(registers_13__ap[17]), .QN(), .SE(dftIn), + .SI(registers_10__ap[17]) + ); + AOI222_X1_LVT i_1_0_1037( + .A1(registers_22__ap[17]), .A2(n_1_0_1294), .B1(n_1_0_1285), .B2(registers_26__ap[17]), + .C1(n_1_0_1277), .C2(registers_13__ap[17]), .ZN(n_1_0_987) + ); + NAND4_X1_LVT i_1_0_1036( + .A1(n_1_0_993), .A2(n_1_0_989), .A3(n_1_0_988), .A4(n_1_0_987), .ZN(n_1_0_986) + ); + SDFF_X1_LVT \registers_reg[1][17] ( + .CK(n_0_0), .D(registers[17]), .Q(registers_1__ap[17]), .QN(), .SE(dftIn), + .SI(registers_22__ap[17]) + ); + SDFF_X1_LVT \registers_reg[28][17] ( + .CK(n_0_58), .D(registers[17]), .Q(registers_28__ap[17]), .QN(), .SE(dftIn), + .SI(registers_26__ap[17]) + ); + AOI221_X1_LVT i_1_0_1035( + .A(n_1_0_986), .B1(n_1_0_1274), .B2(registers_1__ap[17]), .C1(registers_28__ap[17]), + .C2(n_1_0_1283), .ZN(n_1_0_985) + ); + SDFF_X1_LVT \registers_reg[18][17] ( + .CK(n_0_48), .D(registers[17]), .Q(registers_18__ap[17]), .QN(), .SE(dftIn), + .SI(registers_1__ap[17]) + ); + SDFF_X1_LVT \registers_reg[30][17] ( + .CK(n_0_60), .D(registers[17]), .Q(registers_30__ap[17]), .QN(), .SE(dftIn), + .SI(registers_28__ap[17]) + ); + AOI22_X1_LVT i_1_0_1034( + .A1(registers_18__ap[17]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[17]), + .ZN(n_1_0_984) + ); + SDFF_X1_LVT \registers_reg[4][17] ( + .CK(n_0_34), .D(registers[17]), .Q(registers_4__ap[17]), .QN(), .SE(dftIn), + .SI(registers_31__ap[17]) + ); + SDFF_X1_LVT \registers_reg[5][17] ( + .CK(n_0_35), .D(registers[17]), .Q(registers_5__ap[17]), .QN(), .SE(dftIn), + .SI(registers_4__ap[17]) + ); + AOI22_X1_LVT i_1_0_1033( + .A1(registers_4__ap[17]), .A2(n_1_0_1278), .B1(n_1_0_1273), .B2(registers_5__ap[17]), + .ZN(n_1_0_983) + ); + SDFF_X1_LVT \registers_reg[6][17] ( + .CK(n_0_36), .D(registers[17]), .Q(registers_6__ap[17]), .QN(), .SE(dftIn), + .SI(registers_5__ap[17]) + ); + SDFF_X1_LVT \registers_reg[25][17] ( + .CK(n_0_55), .D(registers[17]), .Q(registers_25__ap[17]), .QN(), .SE(dftIn), + .SI(registers_30__ap[17]) + ); + AOI22_X1_LVT i_1_0_1032( + .A1(registers_6__ap[17]), .A2(n_1_0_1300), .B1(n_1_0_1269), .B2(registers_25__ap[17]), + .ZN(n_1_0_982) + ); + NAND3_X1_LVT i_1_0_1031( + .A1(n_1_0_984), .A2(n_1_0_983), .A3(n_1_0_982), .ZN(n_1_0_981) + ); + SDFF_X1_LVT \registers_reg[19][17] ( + .CK(n_0_49), .D(registers[17]), .Q(registers_19__ap[17]), .QN(), .SE(dftIn), + .SI(registers_18__ap[17]) + ); + SDFF_X1_LVT \registers_reg[16][17] ( + .CK(n_0_46), .D(registers[17]), .Q(registers_16__ap[17]), .QN(), .SE(dftIn), + .SI(registers_13__ap[17]) + ); + AOI221_X1_LVT i_1_0_1030( + .A(n_1_0_981), .B1(n_1_0_1295), .B2(registers_19__ap[17]), .C1(registers_16__ap[17]), + .C2(n_1_0_1267), .ZN(n_1_0_980) + ); + SDFF_X1_LVT \registers_reg[7][17] ( + .CK(n_0_37), .D(registers[17]), .Q(registers_7__ap[17]), .QN(), .SE(dftIn), + .SI(registers_6__ap[17]) + ); + SDFF_X1_LVT \registers_reg[14][17] ( + .CK(n_0_44), .D(registers[17]), .Q(registers_14__ap[17]), .QN(), .SE(dftIn), + .SI(registers_16__ap[17]) + ); + AOI22_X1_LVT i_1_0_1029( + .A1(registers_7__ap[17]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[17]), + .ZN(n_1_0_979) + ); + SDFF_X1_LVT \registers_reg[9][17] ( + .CK(n_0_39), .D(registers[17]), .Q(registers_9__ap[17]), .QN(), .SE(dftIn), + .SI(registers_7__ap[17]) + ); + SDFF_X1_LVT \registers_reg[29][17] ( + .CK(n_0_59), .D(registers[17]), .Q(registers_29__ap[17]), .QN(), .SE(dftIn), + .SI(registers_25__ap[17]) + ); + AOI22_X1_LVT i_1_0_1028( + .A1(registers_9__ap[17]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[17]), + .ZN(n_1_0_978) + ); + SDFF_X1_LVT \registers_reg[8][17] ( + .CK(n_0_38), .D(registers[17]), .Q(registers_8__ap[17]), .QN(), .SE(dftIn), + .SI(registers_9__ap[17]) + ); + SDFF_X1_LVT \registers_reg[23][17] ( + .CK(n_0_53), .D(registers[17]), .Q(registers_23__ap[17]), .QN(), .SE(dftIn), + .SI(registers_19__ap[17]) + ); + AOI22_X1_LVT i_1_0_1027( + .A1(registers_8__ap[17]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[17]), + .ZN(n_1_0_977) + ); + NAND3_X1_LVT i_1_0_1026( + .A1(n_1_0_979), .A2(n_1_0_978), .A3(n_1_0_977), .ZN(n_1_0_976) + ); + SDFF_X1_LVT \registers_reg[27][17] ( + .CK(n_0_57), .D(registers[17]), .Q(registers_27__ap[17]), .QN(), .SE(dftIn), + .SI(registers_29__ap[17]) + ); + SDFF_X1_LVT \registers_reg[3][17] ( + .CK(n_0_33), .D(registers[17]), .Q(registers_3__ap[17]), .QN(), .SE(dftIn), + .SI(registers_8__ap[17]) + ); + AOI221_X1_LVT i_1_0_1025( + .A(n_1_0_976), .B1(n_1_0_1279), .B2(registers_27__ap[17]), .C1(registers_3__ap[17]), + .C2(n_1_0_1257), .ZN(n_1_0_975) + ); + NAND4_X1_LVT i_1_0_1024( + .A1(n_1_0_990), .A2(n_1_0_985), .A3(n_1_0_980), .A4(n_1_0_975), .ZN(RRs1[17]) + ); + AND2_X1_LVT i_0_0_16( + .A1(n_0_0_16), .A2(WRd[16]), .ZN(registers[16]) + ); + SDFF_X1_LVT \registers_reg[29][16] ( + .CK(n_0_59), .D(registers[16]), .Q(registers_29__ap[16]), .QN(), .SE(dftIn), + .SI(registers_27__ap[17]) + ); + SDFF_X1_LVT \registers_reg[2][16] ( + .CK(n_0_32), .D(registers[16]), .Q(registers_2__ap[16]), .QN(), .SE(dftIn), + .SI(registers_29__ap[16]) + ); + AOI22_X1_LVT i_1_0_1022( + .A1(registers_29__ap[16]), .A2(n_1_0_1276), .B1(n_1_0_1268), .B2(registers_2__ap[16]), + .ZN(n_1_0_973) + ); + SDFF_X1_LVT \registers_reg[11][16] ( + .CK(n_0_41), .D(registers[16]), .Q(registers_11__ap[16]), .QN(), .SE(dftIn), + .SI(registers_14__ap[17]) + ); + SDFF_X1_LVT \registers_reg[25][16] ( + .CK(n_0_55), .D(registers[16]), .Q(registers_25__ap[16]), .QN(), .SE(dftIn), + .SI(registers_2__ap[16]) + ); + AOI22_X1_LVT i_1_0_1023( + .A1(registers_11__ap[16]), .A2(n_1_0_1270), .B1(n_1_0_1269), .B2(registers_25__ap[16]), + .ZN(n_1_0_974) + ); + SDFF_X1_LVT \registers_reg[9][16] ( + .CK(n_0_39), .D(registers[16]), .Q(registers_9__ap[16]), .QN(), .SE(dftIn), + .SI(registers_3__ap[17]) + ); + SDFF_X1_LVT \registers_reg[7][16] ( + .CK(n_0_37), .D(registers[16]), .Q(registers_7__ap[16]), .QN(), .SE(dftIn), + .SI(registers_9__ap[16]) + ); + AOI22_X1_LVT i_1_0_1021( + .A1(registers_9__ap[16]), .A2(n_1_0_1291), .B1(n_1_0_1263), .B2(registers_7__ap[16]), + .ZN(n_1_0_972) + ); + SDFF_X1_LVT \registers_reg[10][16] ( + .CK(n_0_40), .D(registers[16]), .Q(registers_10__ap[16]), .QN(), .SE(dftIn), + .SI(registers_11__ap[16]) + ); + SDFF_X1_LVT \registers_reg[16][16] ( + .CK(n_0_46), .D(registers[16]), .Q(registers_16__ap[16]), .QN(), .SE(dftIn), + .SI(registers_10__ap[16]) + ); + AOI22_X1_LVT i_1_0_1020( + .A1(registers_10__ap[16]), .A2(n_1_0_1287), .B1(n_1_0_1267), .B2(registers_16__ap[16]), + .ZN(n_1_0_971) + ); + NAND3_X1_LVT i_1_0_1019( + .A1(n_1_0_974), .A2(n_1_0_972), .A3(n_1_0_971), .ZN(n_1_0_970) + ); + SDFF_X1_LVT \registers_reg[31][16] ( + .CK(n_0_61), .D(registers[16]), .Q(registers_31__ap[16]), .QN(), .SE(dftIn), + .SI(registers_7__ap[16]) + ); + SDFF_X1_LVT \registers_reg[6][16] ( + .CK(n_0_36), .D(registers[16]), .Q(registers_6__ap[16]), .QN(), .SE(dftIn), + .SI(registers_31__ap[16]) + ); + AOI221_X1_LVT i_1_0_1018( + .A(n_1_0_970), .B1(n_1_0_1266), .B2(registers_31__ap[16]), .C1(registers_6__ap[16]), + .C2(n_1_0_1300), .ZN(n_1_0_969) + ); + SDFF_X1_LVT \registers_reg[18][16] ( + .CK(n_0_48), .D(registers[16]), .Q(registers_18__ap[16]), .QN(), .SE(dftIn), + .SI(registers_23__ap[17]) + ); + SDFF_X1_LVT \registers_reg[22][16] ( + .CK(n_0_52), .D(registers[16]), .Q(registers_22__ap[16]), .QN(), .SE(dftIn), + .SI(registers_18__ap[16]) + ); + SDFF_X1_LVT \registers_reg[1][16] ( + .CK(n_0_0), .D(registers[16]), .Q(registers_1__ap[16]), .QN(), .SE(dftIn), + .SI(registers_22__ap[16]) + ); + AOI222_X1_LVT i_1_0_1017( + .A1(registers_18__ap[16]), .A2(n_1_0_1297), .B1(n_1_0_1294), .B2(registers_22__ap[16]), + .C1(registers_1__ap[16]), .C2(n_1_0_1274), .ZN(n_1_0_968) + ); + NAND3_X1_LVT i_1_0_1016( + .A1(n_1_0_973), .A2(n_1_0_969), .A3(n_1_0_968), .ZN(n_1_0_967) + ); + SDFF_X1_LVT \registers_reg[5][16] ( + .CK(n_0_35), .D(registers[16]), .Q(registers_5__ap[16]), .QN(), .SE(dftIn), + .SI(registers_6__ap[16]) + ); + SDFF_X1_LVT \registers_reg[28][16] ( + .CK(n_0_58), .D(registers[16]), .Q(registers_28__ap[16]), .QN(), .SE(dftIn), + .SI(registers_25__ap[16]) + ); + AOI221_X1_LVT i_1_0_1015( + .A(n_1_0_967), .B1(n_1_0_1273), .B2(registers_5__ap[16]), .C1(registers_28__ap[16]), + .C2(n_1_0_1283), .ZN(n_1_0_966) + ); + SDFF_X1_LVT \registers_reg[4][16] ( + .CK(n_0_34), .D(registers[16]), .Q(registers_4__ap[16]), .QN(), .SE(dftIn), + .SI(registers_5__ap[16]) + ); + SDFF_X1_LVT \registers_reg[12][16] ( + .CK(n_0_42), .D(registers[16]), .Q(registers_12__ap[16]), .QN(), .SE(dftIn), + .SI(registers_16__ap[16]) + ); + AOI22_X1_LVT i_1_0_1014( + .A1(registers_4__ap[16]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[16]), + .ZN(n_1_0_965) + ); + SDFF_X1_LVT \registers_reg[19][16] ( + .CK(n_0_49), .D(registers[16]), .Q(registers_19__ap[16]), .QN(), .SE(dftIn), + .SI(registers_1__ap[16]) + ); + SDFF_X1_LVT \registers_reg[21][16] ( + .CK(n_0_51), .D(registers[16]), .Q(registers_21__ap[16]), .QN(), .SE(dftIn), + .SI(registers_19__ap[16]) + ); + AOI22_X1_LVT i_1_0_1013( + .A1(registers_19__ap[16]), .A2(n_1_0_1295), .B1(n_1_0_1259), .B2(registers_21__ap[16]), + .ZN(n_1_0_964) + ); + SDFF_X1_LVT \registers_reg[24][16] ( + .CK(n_0_54), .D(registers[16]), .Q(registers_24__ap[16]), .QN(), .SE(dftIn), + .SI(registers_28__ap[16]) + ); + SDFF_X1_LVT \registers_reg[20][16] ( + .CK(n_0_50), .D(registers[16]), .Q(registers_20__ap[16]), .QN(), .SE(dftIn), + .SI(registers_21__ap[16]) + ); + AOI22_X1_LVT i_1_0_1012( + .A1(registers_24__ap[16]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[16]), + .ZN(n_1_0_963) + ); + NAND3_X1_LVT i_1_0_1011( + .A1(n_1_0_965), .A2(n_1_0_964), .A3(n_1_0_963), .ZN(n_1_0_962) + ); + SDFF_X1_LVT \registers_reg[26][16] ( + .CK(n_0_56), .D(registers[16]), .Q(registers_26__ap[16]), .QN(), .SE(dftIn), + .SI(registers_24__ap[16]) + ); + SDFF_X1_LVT \registers_reg[30][16] ( + .CK(n_0_60), .D(registers[16]), .Q(registers_30__ap[16]), .QN(), .SE(dftIn), + .SI(registers_26__ap[16]) + ); + AOI221_X1_LVT i_1_0_1010( + .A(n_1_0_962), .B1(n_1_0_1285), .B2(registers_26__ap[16]), .C1(registers_30__ap[16]), + .C2(n_1_0_1272), .ZN(n_1_0_961) + ); + SDFF_X1_LVT \registers_reg[8][16] ( + .CK(n_0_38), .D(registers[16]), .Q(registers_8__ap[16]), .QN(), .SE(dftIn), + .SI(registers_4__ap[16]) + ); + SDFF_X1_LVT \registers_reg[23][16] ( + .CK(n_0_53), .D(registers[16]), .Q(registers_23__ap[16]), .QN(), .SE(dftIn), + .SI(registers_20__ap[16]) + ); + AOI22_X1_LVT i_1_0_1009( + .A1(registers_8__ap[16]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[16]), + .ZN(n_1_0_960) + ); + SDFF_X1_LVT \registers_reg[13][16] ( + .CK(n_0_43), .D(registers[16]), .Q(registers_13__ap[16]), .QN(), .SE(dftIn), + .SI(registers_12__ap[16]) + ); + SDFF_X1_LVT \registers_reg[17][16] ( + .CK(n_0_47), .D(registers[16]), .Q(registers_17__ap[16]), .QN(), .SE(dftIn), + .SI(registers_23__ap[16]) + ); + AOI22_X1_LVT i_1_0_1008( + .A1(registers_13__ap[16]), .A2(n_1_0_1277), .B1(n_1_0_1271), .B2(registers_17__ap[16]), + .ZN(n_1_0_959) + ); + SDFF_X1_LVT \registers_reg[15][16] ( + .CK(n_0_45), .D(registers[16]), .Q(registers_15__ap[16]), .QN(), .SE(dftIn), + .SI(registers_13__ap[16]) + ); + SDFF_X1_LVT \registers_reg[14][16] ( + .CK(n_0_44), .D(registers[16]), .Q(registers_14__ap[16]), .QN(), .SE(dftIn), + .SI(registers_15__ap[16]) + ); + AOI22_X1_LVT i_1_0_1007( + .A1(registers_15__ap[16]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[16]), + .ZN(n_1_0_958) + ); + NAND3_X1_LVT i_1_0_1006( + .A1(n_1_0_960), .A2(n_1_0_959), .A3(n_1_0_958), .ZN(n_1_0_957) + ); + SDFF_X1_LVT \registers_reg[27][16] ( + .CK(n_0_57), .D(registers[16]), .Q(registers_27__ap[16]), .QN(), .SE(dftIn), + .SI(registers_30__ap[16]) + ); + SDFF_X1_LVT \registers_reg[3][16] ( + .CK(n_0_33), .D(registers[16]), .Q(registers_3__ap[16]), .QN(), .SE(dftIn), + .SI(registers_8__ap[16]) + ); + AOI221_X1_LVT i_1_0_1005( + .A(n_1_0_957), .B1(n_1_0_1279), .B2(registers_27__ap[16]), .C1(registers_3__ap[16]), + .C2(n_1_0_1257), .ZN(n_1_0_956) + ); + NAND3_X1_LVT i_1_0_1004( + .A1(n_1_0_966), .A2(n_1_0_961), .A3(n_1_0_956), .ZN(RRs1[16]) + ); + AND2_X1_LVT i_0_0_15( + .A1(n_0_0_16), .A2(WRd[15]), .ZN(registers[15]) + ); + SDFF_X1_LVT \registers_reg[17][15] ( + .CK(n_0_47), .D(registers[15]), .Q(registers_17__ap[15]), .QN(), .SE(dftIn), + .SI(registers_17__ap[16]) + ); + SDFF_X1_LVT \registers_reg[21][15] ( + .CK(n_0_51), .D(registers[15]), .Q(registers_21__ap[15]), .QN(), .SE(dftIn), + .SI(registers_17__ap[15]) + ); + AOI22_X1_LVT i_1_0_1000( + .A1(registers_17__ap[15]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[15]), + .ZN(n_1_0_952) + ); + SDFF_X1_LVT \registers_reg[10][15] ( + .CK(n_0_40), .D(registers[15]), .Q(registers_10__ap[15]), .QN(), .SE(dftIn), + .SI(registers_14__ap[16]) + ); + SDFF_X1_LVT \registers_reg[2][15] ( + .CK(n_0_32), .D(registers[15]), .Q(registers_2__ap[15]), .QN(), .SE(dftIn), + .SI(registers_27__ap[16]) + ); + AOI22_X1_LVT i_1_0_1003( + .A1(registers_10__ap[15]), .A2(n_1_0_1287), .B1(n_1_0_1268), .B2(registers_2__ap[15]), + .ZN(n_1_0_955) + ); + SDFF_X1_LVT \registers_reg[20][15] ( + .CK(n_0_50), .D(registers[15]), .Q(registers_20__ap[15]), .QN(), .SE(dftIn), + .SI(registers_21__ap[15]) + ); + SDFF_X1_LVT \registers_reg[12][15] ( + .CK(n_0_42), .D(registers[15]), .Q(registers_12__ap[15]), .QN(), .SE(dftIn), + .SI(registers_10__ap[15]) + ); + AOI22_X1_LVT i_1_0_999( + .A1(registers_20__ap[15]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[15]), + .ZN(n_1_0_951) + ); + SDFF_X1_LVT \registers_reg[15][15] ( + .CK(n_0_45), .D(registers[15]), .Q(registers_15__ap[15]), .QN(), .SE(dftIn), + .SI(registers_12__ap[15]) + ); + SDFF_X1_LVT \registers_reg[8][15] ( + .CK(n_0_38), .D(registers[15]), .Q(registers_8__ap[15]), .QN(), .SE(dftIn), + .SI(registers_3__ap[16]) + ); + AOI22_X1_LVT i_1_0_1002( + .A1(registers_15__ap[15]), .A2(n_1_0_1286), .B1(n_1_0_1282), .B2(registers_8__ap[15]), + .ZN(n_1_0_954) + ); + INV_X1_LVT i_1_0_1001( + .A(n_1_0_954), .ZN(n_1_0_953) + ); + SDFF_X1_LVT \registers_reg[11][15] ( + .CK(n_0_41), .D(registers[15]), .Q(registers_11__ap[15]), .QN(), .SE(dftIn), + .SI(registers_15__ap[15]) + ); + SDFF_X1_LVT \registers_reg[24][15] ( + .CK(n_0_54), .D(registers[15]), .Q(registers_24__ap[15]), .QN(), .SE(dftIn), + .SI(registers_2__ap[15]) + ); + AOI221_X1_LVT i_1_0_998( + .A(n_1_0_953), .B1(n_1_0_1270), .B2(registers_11__ap[15]), .C1(registers_24__ap[15]), + .C2(n_1_0_1289), .ZN(n_1_0_950) + ); + SDFF_X1_LVT \registers_reg[13][15] ( + .CK(n_0_43), .D(registers[15]), .Q(registers_13__ap[15]), .QN(), .SE(dftIn), + .SI(registers_11__ap[15]) + ); + SDFF_X1_LVT \registers_reg[30][15] ( + .CK(n_0_60), .D(registers[15]), .Q(registers_30__ap[15]), .QN(), .SE(dftIn), + .SI(registers_24__ap[15]) + ); + SDFF_X1_LVT \registers_reg[22][15] ( + .CK(n_0_52), .D(registers[15]), .Q(registers_22__ap[15]), .QN(), .SE(dftIn), + .SI(registers_20__ap[15]) + ); + AOI222_X1_LVT i_1_0_997( + .A1(registers_13__ap[15]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[15]), + .C1(registers_22__ap[15]), .C2(n_1_0_1294), .ZN(n_1_0_949) + ); + NAND4_X1_LVT i_1_0_996( + .A1(n_1_0_955), .A2(n_1_0_951), .A3(n_1_0_950), .A4(n_1_0_949), .ZN(n_1_0_948) + ); + SDFF_X1_LVT \registers_reg[1][15] ( + .CK(n_0_0), .D(registers[15]), .Q(registers_1__ap[15]), .QN(), .SE(dftIn), + .SI(registers_22__ap[15]) + ); + SDFF_X1_LVT \registers_reg[28][15] ( + .CK(n_0_58), .D(registers[15]), .Q(registers_28__ap[15]), .QN(), .SE(dftIn), + .SI(registers_30__ap[15]) + ); + AOI221_X1_LVT i_1_0_995( + .A(n_1_0_948), .B1(n_1_0_1274), .B2(registers_1__ap[15]), .C1(registers_28__ap[15]), + .C2(n_1_0_1283), .ZN(n_1_0_947) + ); + SDFF_X1_LVT \registers_reg[18][15] ( + .CK(n_0_48), .D(registers[15]), .Q(registers_18__ap[15]), .QN(), .SE(dftIn), + .SI(registers_1__ap[15]) + ); + SDFF_X1_LVT \registers_reg[26][15] ( + .CK(n_0_56), .D(registers[15]), .Q(registers_26__ap[15]), .QN(), .SE(dftIn), + .SI(registers_28__ap[15]) + ); + AOI22_X1_LVT i_1_0_994( + .A1(registers_18__ap[15]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[15]), + .ZN(n_1_0_946) + ); + SDFF_X1_LVT \registers_reg[4][15] ( + .CK(n_0_34), .D(registers[15]), .Q(registers_4__ap[15]), .QN(), .SE(dftIn), + .SI(registers_8__ap[15]) + ); + SDFF_X1_LVT \registers_reg[5][15] ( + .CK(n_0_35), .D(registers[15]), .Q(registers_5__ap[15]), .QN(), .SE(dftIn), + .SI(registers_4__ap[15]) + ); + AOI22_X1_LVT i_1_0_993( + .A1(registers_4__ap[15]), .A2(n_1_0_1278), .B1(n_1_0_1273), .B2(registers_5__ap[15]), + .ZN(n_1_0_945) + ); + SDFF_X1_LVT \registers_reg[6][15] ( + .CK(n_0_36), .D(registers[15]), .Q(registers_6__ap[15]), .QN(), .SE(dftIn), + .SI(registers_5__ap[15]) + ); + SDFF_X1_LVT \registers_reg[16][15] ( + .CK(n_0_46), .D(registers[15]), .Q(registers_16__ap[15]), .QN(), .SE(dftIn), + .SI(registers_13__ap[15]) + ); + AOI22_X1_LVT i_1_0_992( + .A1(registers_6__ap[15]), .A2(n_1_0_1300), .B1(n_1_0_1267), .B2(registers_16__ap[15]), + .ZN(n_1_0_944) + ); + NAND3_X1_LVT i_1_0_991( + .A1(n_1_0_946), .A2(n_1_0_945), .A3(n_1_0_944), .ZN(n_1_0_943) + ); + SDFF_X1_LVT \registers_reg[19][15] ( + .CK(n_0_49), .D(registers[15]), .Q(registers_19__ap[15]), .QN(), .SE(dftIn), + .SI(registers_18__ap[15]) + ); + SDFF_X1_LVT \registers_reg[25][15] ( + .CK(n_0_55), .D(registers[15]), .Q(registers_25__ap[15]), .QN(), .SE(dftIn), + .SI(registers_26__ap[15]) + ); + AOI221_X1_LVT i_1_0_990( + .A(n_1_0_943), .B1(n_1_0_1295), .B2(registers_19__ap[15]), .C1(registers_25__ap[15]), + .C2(n_1_0_1269), .ZN(n_1_0_942) + ); + SDFF_X1_LVT \registers_reg[7][15] ( + .CK(n_0_37), .D(registers[15]), .Q(registers_7__ap[15]), .QN(), .SE(dftIn), + .SI(registers_6__ap[15]) + ); + SDFF_X1_LVT \registers_reg[14][15] ( + .CK(n_0_44), .D(registers[15]), .Q(registers_14__ap[15]), .QN(), .SE(dftIn), + .SI(registers_16__ap[15]) + ); + AOI22_X1_LVT i_1_0_989( + .A1(registers_7__ap[15]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[15]), + .ZN(n_1_0_941) + ); + SDFF_X1_LVT \registers_reg[9][15] ( + .CK(n_0_39), .D(registers[15]), .Q(registers_9__ap[15]), .QN(), .SE(dftIn), + .SI(registers_7__ap[15]) + ); + SDFF_X1_LVT \registers_reg[29][15] ( + .CK(n_0_59), .D(registers[15]), .Q(registers_29__ap[15]), .QN(), .SE(dftIn), + .SI(registers_25__ap[15]) + ); + AOI22_X1_LVT i_1_0_988( + .A1(registers_9__ap[15]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[15]), + .ZN(n_1_0_940) + ); + SDFF_X1_LVT \registers_reg[23][15] ( + .CK(n_0_53), .D(registers[15]), .Q(registers_23__ap[15]), .QN(), .SE(dftIn), + .SI(registers_19__ap[15]) + ); + SDFF_X1_LVT \registers_reg[3][15] ( + .CK(n_0_33), .D(registers[15]), .Q(registers_3__ap[15]), .QN(), .SE(dftIn), + .SI(registers_9__ap[15]) + ); + AOI22_X1_LVT i_1_0_987( + .A1(registers_23__ap[15]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[15]), + .ZN(n_1_0_939) + ); + NAND3_X1_LVT i_1_0_986( + .A1(n_1_0_941), .A2(n_1_0_940), .A3(n_1_0_939), .ZN(n_1_0_938) + ); + SDFF_X1_LVT \registers_reg[27][15] ( + .CK(n_0_57), .D(registers[15]), .Q(registers_27__ap[15]), .QN(), .SE(dftIn), + .SI(registers_29__ap[15]) + ); + SDFF_X1_LVT \registers_reg[31][15] ( + .CK(n_0_61), .D(registers[15]), .Q(registers_31__ap[15]), .QN(), .SE(dftIn), + .SI(registers_3__ap[15]) + ); + AOI221_X1_LVT i_1_0_985( + .A(n_1_0_938), .B1(n_1_0_1279), .B2(registers_27__ap[15]), .C1(registers_31__ap[15]), + .C2(n_1_0_1266), .ZN(n_1_0_937) + ); + NAND4_X1_LVT i_1_0_984( + .A1(n_1_0_952), .A2(n_1_0_947), .A3(n_1_0_942), .A4(n_1_0_937), .ZN(RRs1[15]) + ); + AND2_X1_LVT i_0_0_14( + .A1(n_0_0_16), .A2(WRd[14]), .ZN(registers[14]) + ); + SDFF_X1_LVT \registers_reg[28][14] ( + .CK(n_0_58), .D(registers[14]), .Q(registers_28__ap[14]), .QN(), .SE(dftIn), + .SI(registers_27__ap[15]) + ); + SDFF_X1_LVT \registers_reg[5][14] ( + .CK(n_0_35), .D(registers[14]), .Q(registers_5__ap[14]), .QN(), .SE(dftIn), + .SI(registers_31__ap[15]) + ); + AOI22_X1_LVT i_1_0_983( + .A1(registers_28__ap[14]), .A2(n_1_0_1283), .B1(n_1_0_1273), .B2(registers_5__ap[14]), + .ZN(n_1_0_936) + ); + SDFF_X1_LVT \registers_reg[18][14] ( + .CK(n_0_48), .D(registers[14]), .Q(registers_18__ap[14]), .QN(), .SE(dftIn), + .SI(registers_23__ap[15]) + ); + SDFF_X1_LVT \registers_reg[10][14] ( + .CK(n_0_40), .D(registers[14]), .Q(registers_10__ap[14]), .QN(), .SE(dftIn), + .SI(registers_14__ap[15]) + ); + SDFF_X1_LVT \registers_reg[8][14] ( + .CK(n_0_38), .D(registers[14]), .Q(registers_8__ap[14]), .QN(), .SE(dftIn), + .SI(registers_5__ap[14]) + ); + AOI222_X1_LVT i_1_0_982( + .A1(registers_18__ap[14]), .A2(n_1_0_1297), .B1(n_1_0_1287), .B2(registers_10__ap[14]), + .C1(n_1_0_1282), .C2(registers_8__ap[14]), .ZN(n_1_0_935) + ); + SDFF_X1_LVT \registers_reg[9][14] ( + .CK(n_0_39), .D(registers[14]), .Q(registers_9__ap[14]), .QN(), .SE(dftIn), + .SI(registers_8__ap[14]) + ); + SDFF_X1_LVT \registers_reg[29][14] ( + .CK(n_0_59), .D(registers[14]), .Q(registers_29__ap[14]), .QN(), .SE(dftIn), + .SI(registers_28__ap[14]) + ); + AOI22_X1_LVT i_1_0_981( + .A1(registers_9__ap[14]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[14]), + .ZN(n_1_0_934) + ); + SDFF_X1_LVT \registers_reg[21][14] ( + .CK(n_0_51), .D(registers[14]), .Q(registers_21__ap[14]), .QN(), .SE(dftIn), + .SI(registers_18__ap[14]) + ); + SDFF_X1_LVT \registers_reg[14][14] ( + .CK(n_0_44), .D(registers[14]), .Q(registers_14__ap[14]), .QN(), .SE(dftIn), + .SI(registers_10__ap[14]) + ); + AOI22_X1_LVT i_1_0_980( + .A1(registers_21__ap[14]), .A2(n_1_0_1259), .B1(n_1_0_1258), .B2(registers_14__ap[14]), + .ZN(n_1_0_933) + ); + SDFF_X1_LVT \registers_reg[16][14] ( + .CK(n_0_46), .D(registers[14]), .Q(registers_16__ap[14]), .QN(), .SE(dftIn), + .SI(registers_14__ap[14]) + ); + SDFF_X1_LVT \registers_reg[3][14] ( + .CK(n_0_33), .D(registers[14]), .Q(registers_3__ap[14]), .QN(), .SE(dftIn), + .SI(registers_9__ap[14]) + ); + AOI22_X1_LVT i_1_0_979( + .A1(registers_16__ap[14]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[14]), + .ZN(n_1_0_932) + ); + SDFF_X1_LVT \registers_reg[17][14] ( + .CK(n_0_47), .D(registers[14]), .Q(registers_17__ap[14]), .QN(), .SE(dftIn), + .SI(registers_21__ap[14]) + ); + SDFF_X1_LVT \registers_reg[31][14] ( + .CK(n_0_61), .D(registers[14]), .Q(registers_31__ap[14]), .QN(), .SE(dftIn), + .SI(registers_3__ap[14]) + ); + AOI22_X1_LVT i_1_0_978( + .A1(registers_17__ap[14]), .A2(n_1_0_1271), .B1(n_1_0_1266), .B2(registers_31__ap[14]), + .ZN(n_1_0_931) + ); + SDFF_X1_LVT \registers_reg[15][14] ( + .CK(n_0_45), .D(registers[14]), .Q(registers_15__ap[14]), .QN(), .SE(dftIn), + .SI(registers_16__ap[14]) + ); + SDFF_X1_LVT \registers_reg[23][14] ( + .CK(n_0_53), .D(registers[14]), .Q(registers_23__ap[14]), .QN(), .SE(dftIn), + .SI(registers_17__ap[14]) + ); + AOI22_X1_LVT i_1_0_977( + .A1(registers_15__ap[14]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[14]), + .ZN(n_1_0_930) + ); + NAND4_X1_LVT i_1_0_976( + .A1(n_1_0_933), .A2(n_1_0_932), .A3(n_1_0_931), .A4(n_1_0_930), .ZN(n_1_0_929) + ); + SDFF_X1_LVT \registers_reg[26][14] ( + .CK(n_0_56), .D(registers[14]), .Q(registers_26__ap[14]), .QN(), .SE(dftIn), + .SI(registers_29__ap[14]) + ); + SDFF_X1_LVT \registers_reg[30][14] ( + .CK(n_0_60), .D(registers[14]), .Q(registers_30__ap[14]), .QN(), .SE(dftIn), + .SI(registers_26__ap[14]) + ); + AOI22_X1_LVT i_1_0_975( + .A1(registers_26__ap[14]), .A2(n_1_0_1285), .B1(n_1_0_1272), .B2(registers_30__ap[14]), + .ZN(n_1_0_928) + ); + SDFF_X1_LVT \registers_reg[20][14] ( + .CK(n_0_50), .D(registers[14]), .Q(registers_20__ap[14]), .QN(), .SE(dftIn), + .SI(registers_23__ap[14]) + ); + SDFF_X1_LVT \registers_reg[4][14] ( + .CK(n_0_34), .D(registers[14]), .Q(registers_4__ap[14]), .QN(), .SE(dftIn), + .SI(registers_31__ap[14]) + ); + AOI22_X1_LVT i_1_0_974( + .A1(registers_20__ap[14]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[14]), + .ZN(n_1_0_927) + ); + SDFF_X1_LVT \registers_reg[1][14] ( + .CK(n_0_0), .D(registers[14]), .Q(registers_1__ap[14]), .QN(), .SE(dftIn), + .SI(registers_20__ap[14]) + ); + SDFF_X1_LVT \registers_reg[2][14] ( + .CK(n_0_32), .D(registers[14]), .Q(registers_2__ap[14]), .QN(), .SE(dftIn), + .SI(registers_30__ap[14]) + ); + AOI22_X1_LVT i_1_0_973( + .A1(registers_1__ap[14]), .A2(n_1_0_1274), .B1(n_1_0_1268), .B2(registers_2__ap[14]), + .ZN(n_1_0_926) + ); + SDFF_X1_LVT \registers_reg[24][14] ( + .CK(n_0_54), .D(registers[14]), .Q(registers_24__ap[14]), .QN(), .SE(dftIn), + .SI(registers_2__ap[14]) + ); + SDFF_X1_LVT \registers_reg[12][14] ( + .CK(n_0_42), .D(registers[14]), .Q(registers_12__ap[14]), .QN(), .SE(dftIn), + .SI(registers_15__ap[14]) + ); + AOI22_X1_LVT i_1_0_972( + .A1(registers_24__ap[14]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[14]), + .ZN(n_1_0_925) + ); + NAND4_X1_LVT i_1_0_971( + .A1(n_1_0_928), .A2(n_1_0_927), .A3(n_1_0_926), .A4(n_1_0_925), .ZN(n_1_0_924) + ); + SDFF_X1_LVT \registers_reg[19][14] ( + .CK(n_0_49), .D(registers[14]), .Q(registers_19__ap[14]), .QN(), .SE(dftIn), + .SI(registers_1__ap[14]) + ); + SDFF_X1_LVT \registers_reg[22][14] ( + .CK(n_0_52), .D(registers[14]), .Q(registers_22__ap[14]), .QN(), .SE(dftIn), + .SI(registers_19__ap[14]) + ); + AOI22_X1_LVT i_1_0_970( + .A1(registers_19__ap[14]), .A2(n_1_0_1295), .B1(n_1_0_1294), .B2(registers_22__ap[14]), + .ZN(n_1_0_923) + ); + SDFF_X1_LVT \registers_reg[13][14] ( + .CK(n_0_43), .D(registers[14]), .Q(registers_13__ap[14]), .QN(), .SE(dftIn), + .SI(registers_12__ap[14]) + ); + SDFF_X1_LVT \registers_reg[25][14] ( + .CK(n_0_55), .D(registers[14]), .Q(registers_25__ap[14]), .QN(), .SE(dftIn), + .SI(registers_24__ap[14]) + ); + AOI22_X1_LVT i_1_0_969( + .A1(registers_13__ap[14]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[14]), + .ZN(n_1_0_922) + ); + SDFF_X1_LVT \registers_reg[6][14] ( + .CK(n_0_36), .D(registers[14]), .Q(registers_6__ap[14]), .QN(), .SE(dftIn), + .SI(registers_4__ap[14]) + ); + SDFF_X1_LVT \registers_reg[7][14] ( + .CK(n_0_37), .D(registers[14]), .Q(registers_7__ap[14]), .QN(), .SE(dftIn), + .SI(registers_6__ap[14]) + ); + AOI22_X1_LVT i_1_0_968( + .A1(registers_6__ap[14]), .A2(n_1_0_1300), .B1(n_1_0_1263), .B2(registers_7__ap[14]), + .ZN(n_1_0_921) + ); + SDFF_X1_LVT \registers_reg[27][14] ( + .CK(n_0_57), .D(registers[14]), .Q(registers_27__ap[14]), .QN(), .SE(dftIn), + .SI(registers_25__ap[14]) + ); + SDFF_X1_LVT \registers_reg[11][14] ( + .CK(n_0_41), .D(registers[14]), .Q(registers_11__ap[14]), .QN(), .SE(dftIn), + .SI(registers_13__ap[14]) + ); + AOI22_X1_LVT i_1_0_967( + .A1(registers_27__ap[14]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[14]), + .ZN(n_1_0_920) + ); + NAND4_X1_LVT i_1_0_966( + .A1(n_1_0_923), .A2(n_1_0_922), .A3(n_1_0_921), .A4(n_1_0_920), .ZN(n_1_0_919) + ); + NOR3_X1_LVT i_1_0_965( + .A1(n_1_0_929), .A2(n_1_0_924), .A3(n_1_0_919), .ZN(n_1_0_918) + ); + NAND4_X1_LVT i_1_0_964( + .A1(n_1_0_936), .A2(n_1_0_935), .A3(n_1_0_934), .A4(n_1_0_918), .ZN(RRs1[14]) + ); + AND2_X1_LVT i_0_0_13( + .A1(n_0_0_16), .A2(WRd[13]), .ZN(registers[13]) + ); + SDFF_X1_LVT \registers_reg[28][13] ( + .CK(n_0_58), .D(registers[13]), .Q(registers_28__ap[13]), .QN(), .SE(dftIn), + .SI(registers_27__ap[14]) + ); + SDFF_X1_LVT \registers_reg[4][13] ( + .CK(n_0_34), .D(registers[13]), .Q(registers_4__ap[13]), .QN(), .SE(dftIn), + .SI(registers_7__ap[14]) + ); + AOI22_X1_LVT i_1_0_963( + .A1(registers_28__ap[13]), .A2(n_1_0_1283), .B1(n_1_0_1278), .B2(registers_4__ap[13]), + .ZN(n_1_0_917) + ); + SDFF_X1_LVT \registers_reg[10][13] ( + .CK(n_0_40), .D(registers[13]), .Q(registers_10__ap[13]), .QN(), .SE(dftIn), + .SI(registers_11__ap[14]) + ); + SDFF_X1_LVT \registers_reg[26][13] ( + .CK(n_0_56), .D(registers[13]), .Q(registers_26__ap[13]), .QN(), .SE(dftIn), + .SI(registers_28__ap[13]) + ); + SDFF_X1_LVT \registers_reg[8][13] ( + .CK(n_0_38), .D(registers[13]), .Q(registers_8__ap[13]), .QN(), .SE(dftIn), + .SI(registers_4__ap[13]) + ); + AOI222_X1_LVT i_1_0_962( + .A1(registers_10__ap[13]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[13]), + .C1(registers_8__ap[13]), .C2(n_1_0_1282), .ZN(n_1_0_916) + ); + SDFF_X1_LVT \registers_reg[9][13] ( + .CK(n_0_39), .D(registers[13]), .Q(registers_9__ap[13]), .QN(), .SE(dftIn), + .SI(registers_8__ap[13]) + ); + SDFF_X1_LVT \registers_reg[29][13] ( + .CK(n_0_59), .D(registers[13]), .Q(registers_29__ap[13]), .QN(), .SE(dftIn), + .SI(registers_26__ap[13]) + ); + AOI22_X1_LVT i_1_0_961( + .A1(registers_9__ap[13]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[13]), + .ZN(n_1_0_915) + ); + SDFF_X1_LVT \registers_reg[6][13] ( + .CK(n_0_36), .D(registers[13]), .Q(registers_6__ap[13]), .QN(), .SE(dftIn), + .SI(registers_9__ap[13]) + ); + SDFF_X1_LVT \registers_reg[1][13] ( + .CK(n_0_0), .D(registers[13]), .Q(registers_1__ap[13]), .QN(), .SE(dftIn), + .SI(registers_22__ap[14]) + ); + AOI22_X1_LVT i_1_0_960( + .A1(registers_6__ap[13]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[13]), + .ZN(n_1_0_914) + ); + SDFF_X1_LVT \registers_reg[5][13] ( + .CK(n_0_35), .D(registers[13]), .Q(registers_5__ap[13]), .QN(), .SE(dftIn), + .SI(registers_6__ap[13]) + ); + SDFF_X1_LVT \registers_reg[3][13] ( + .CK(n_0_33), .D(registers[13]), .Q(registers_3__ap[13]), .QN(), .SE(dftIn), + .SI(registers_5__ap[13]) + ); + AOI22_X1_LVT i_1_0_959( + .A1(registers_5__ap[13]), .A2(n_1_0_1273), .B1(n_1_0_1257), .B2(registers_3__ap[13]), + .ZN(n_1_0_913) + ); + SDFF_X1_LVT \registers_reg[16][13] ( + .CK(n_0_46), .D(registers[13]), .Q(registers_16__ap[13]), .QN(), .SE(dftIn), + .SI(registers_10__ap[13]) + ); + SDFF_X1_LVT \registers_reg[31][13] ( + .CK(n_0_61), .D(registers[13]), .Q(registers_31__ap[13]), .QN(), .SE(dftIn), + .SI(registers_3__ap[13]) + ); + AOI22_X1_LVT i_1_0_958( + .A1(registers_16__ap[13]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[13]), + .ZN(n_1_0_912) + ); + SDFF_X1_LVT \registers_reg[15][13] ( + .CK(n_0_45), .D(registers[13]), .Q(registers_15__ap[13]), .QN(), .SE(dftIn), + .SI(registers_16__ap[13]) + ); + SDFF_X1_LVT \registers_reg[23][13] ( + .CK(n_0_53), .D(registers[13]), .Q(registers_23__ap[13]), .QN(), .SE(dftIn), + .SI(registers_1__ap[13]) + ); + AOI22_X1_LVT i_1_0_957( + .A1(registers_15__ap[13]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[13]), + .ZN(n_1_0_911) + ); + NAND4_X1_LVT i_1_0_956( + .A1(n_1_0_914), .A2(n_1_0_913), .A3(n_1_0_912), .A4(n_1_0_911), .ZN(n_1_0_910) + ); + SDFF_X1_LVT \registers_reg[18][13] ( + .CK(n_0_48), .D(registers[13]), .Q(registers_18__ap[13]), .QN(), .SE(dftIn), + .SI(registers_23__ap[13]) + ); + SDFF_X1_LVT \registers_reg[30][13] ( + .CK(n_0_60), .D(registers[13]), .Q(registers_30__ap[13]), .QN(), .SE(dftIn), + .SI(registers_29__ap[13]) + ); + AOI22_X1_LVT i_1_0_955( + .A1(registers_18__ap[13]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[13]), + .ZN(n_1_0_909) + ); + SDFF_X1_LVT \registers_reg[24][13] ( + .CK(n_0_54), .D(registers[13]), .Q(registers_24__ap[13]), .QN(), .SE(dftIn), + .SI(registers_30__ap[13]) + ); + SDFF_X1_LVT \registers_reg[12][13] ( + .CK(n_0_42), .D(registers[13]), .Q(registers_12__ap[13]), .QN(), .SE(dftIn), + .SI(registers_15__ap[13]) + ); + AOI22_X1_LVT i_1_0_954( + .A1(registers_24__ap[13]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[13]), + .ZN(n_1_0_908) + ); + SDFF_X1_LVT \registers_reg[22][13] ( + .CK(n_0_52), .D(registers[13]), .Q(registers_22__ap[13]), .QN(), .SE(dftIn), + .SI(registers_18__ap[13]) + ); + SDFF_X1_LVT \registers_reg[21][13] ( + .CK(n_0_51), .D(registers[13]), .Q(registers_21__ap[13]), .QN(), .SE(dftIn), + .SI(registers_22__ap[13]) + ); + AOI22_X1_LVT i_1_0_953( + .A1(registers_22__ap[13]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[13]), + .ZN(n_1_0_907) + ); + SDFF_X1_LVT \registers_reg[20][13] ( + .CK(n_0_50), .D(registers[13]), .Q(registers_20__ap[13]), .QN(), .SE(dftIn), + .SI(registers_21__ap[13]) + ); + SDFF_X1_LVT \registers_reg[17][13] ( + .CK(n_0_47), .D(registers[13]), .Q(registers_17__ap[13]), .QN(), .SE(dftIn), + .SI(registers_20__ap[13]) + ); + AOI22_X1_LVT i_1_0_952( + .A1(registers_20__ap[13]), .A2(n_1_0_1281), .B1(n_1_0_1271), .B2(registers_17__ap[13]), + .ZN(n_1_0_906) + ); + NAND4_X1_LVT i_1_0_951( + .A1(n_1_0_909), .A2(n_1_0_908), .A3(n_1_0_907), .A4(n_1_0_906), .ZN(n_1_0_905) + ); + SDFF_X1_LVT \registers_reg[13][13] ( + .CK(n_0_43), .D(registers[13]), .Q(registers_13__ap[13]), .QN(), .SE(dftIn), + .SI(registers_12__ap[13]) + ); + SDFF_X1_LVT \registers_reg[25][13] ( + .CK(n_0_55), .D(registers[13]), .Q(registers_25__ap[13]), .QN(), .SE(dftIn), + .SI(registers_24__ap[13]) + ); + AOI22_X1_LVT i_1_0_950( + .A1(registers_13__ap[13]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[13]), + .ZN(n_1_0_904) + ); + SDFF_X1_LVT \registers_reg[19][13] ( + .CK(n_0_49), .D(registers[13]), .Q(registers_19__ap[13]), .QN(), .SE(dftIn), + .SI(registers_17__ap[13]) + ); + SDFF_X1_LVT \registers_reg[2][13] ( + .CK(n_0_32), .D(registers[13]), .Q(registers_2__ap[13]), .QN(), .SE(dftIn), + .SI(registers_25__ap[13]) + ); + AOI22_X1_LVT i_1_0_949( + .A1(registers_19__ap[13]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[13]), + .ZN(n_1_0_903) + ); + SDFF_X1_LVT \registers_reg[7][13] ( + .CK(n_0_37), .D(registers[13]), .Q(registers_7__ap[13]), .QN(), .SE(dftIn), + .SI(registers_31__ap[13]) + ); + SDFF_X1_LVT \registers_reg[14][13] ( + .CK(n_0_44), .D(registers[13]), .Q(registers_14__ap[13]), .QN(), .SE(dftIn), + .SI(registers_13__ap[13]) + ); + AOI22_X1_LVT i_1_0_948( + .A1(registers_7__ap[13]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[13]), + .ZN(n_1_0_902) + ); + SDFF_X1_LVT \registers_reg[27][13] ( + .CK(n_0_57), .D(registers[13]), .Q(registers_27__ap[13]), .QN(), .SE(dftIn), + .SI(registers_2__ap[13]) + ); + SDFF_X1_LVT \registers_reg[11][13] ( + .CK(n_0_41), .D(registers[13]), .Q(registers_11__ap[13]), .QN(), .SE(dftIn), + .SI(registers_14__ap[13]) + ); + AOI22_X1_LVT i_1_0_947( + .A1(registers_27__ap[13]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[13]), + .ZN(n_1_0_901) + ); + NAND4_X1_LVT i_1_0_946( + .A1(n_1_0_904), .A2(n_1_0_903), .A3(n_1_0_902), .A4(n_1_0_901), .ZN(n_1_0_900) + ); + NOR3_X1_LVT i_1_0_945( + .A1(n_1_0_910), .A2(n_1_0_905), .A3(n_1_0_900), .ZN(n_1_0_899) + ); + NAND4_X1_LVT i_1_0_944( + .A1(n_1_0_917), .A2(n_1_0_916), .A3(n_1_0_915), .A4(n_1_0_899), .ZN(RRs1[13]) + ); + AND2_X1_LVT i_0_0_12( + .A1(n_0_0_16), .A2(WRd[12]), .ZN(registers[12]) + ); + SDFF_X1_LVT \registers_reg[28][12] ( + .CK(n_0_58), .D(registers[12]), .Q(registers_28__ap[12]), .QN(), .SE(dftIn), + .SI(registers_27__ap[13]) + ); + SDFF_X1_LVT \registers_reg[17][12] ( + .CK(n_0_47), .D(registers[12]), .Q(registers_17__ap[12]), .QN(), .SE(dftIn), + .SI(registers_19__ap[13]) + ); + AOI22_X1_LVT i_1_0_943( + .A1(registers_28__ap[12]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[12]), + .ZN(n_1_0_898) + ); + SDFF_X1_LVT \registers_reg[10][12] ( + .CK(n_0_40), .D(registers[12]), .Q(registers_10__ap[12]), .QN(), .SE(dftIn), + .SI(registers_11__ap[13]) + ); + SDFF_X1_LVT \registers_reg[26][12] ( + .CK(n_0_56), .D(registers[12]), .Q(registers_26__ap[12]), .QN(), .SE(dftIn), + .SI(registers_28__ap[12]) + ); + SDFF_X1_LVT \registers_reg[8][12] ( + .CK(n_0_38), .D(registers[12]), .Q(registers_8__ap[12]), .QN(), .SE(dftIn), + .SI(registers_7__ap[13]) + ); + AOI222_X1_LVT i_1_0_942( + .A1(registers_10__ap[12]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[12]), + .C1(registers_8__ap[12]), .C2(n_1_0_1282), .ZN(n_1_0_897) + ); + SDFF_X1_LVT \registers_reg[9][12] ( + .CK(n_0_39), .D(registers[12]), .Q(registers_9__ap[12]), .QN(), .SE(dftIn), + .SI(registers_8__ap[12]) + ); + SDFF_X1_LVT \registers_reg[29][12] ( + .CK(n_0_59), .D(registers[12]), .Q(registers_29__ap[12]), .QN(), .SE(dftIn), + .SI(registers_26__ap[12]) + ); + AOI22_X1_LVT i_1_0_941( + .A1(registers_9__ap[12]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[12]), + .ZN(n_1_0_896) + ); + SDFF_X1_LVT \registers_reg[6][12] ( + .CK(n_0_36), .D(registers[12]), .Q(registers_6__ap[12]), .QN(), .SE(dftIn), + .SI(registers_9__ap[12]) + ); + SDFF_X1_LVT \registers_reg[1][12] ( + .CK(n_0_0), .D(registers[12]), .Q(registers_1__ap[12]), .QN(), .SE(dftIn), + .SI(registers_17__ap[12]) + ); + AOI22_X1_LVT i_1_0_940( + .A1(registers_6__ap[12]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[12]), + .ZN(n_1_0_895) + ); + SDFF_X1_LVT \registers_reg[16][12] ( + .CK(n_0_46), .D(registers[12]), .Q(registers_16__ap[12]), .QN(), .SE(dftIn), + .SI(registers_10__ap[12]) + ); + SDFF_X1_LVT \registers_reg[3][12] ( + .CK(n_0_33), .D(registers[12]), .Q(registers_3__ap[12]), .QN(), .SE(dftIn), + .SI(registers_6__ap[12]) + ); + AOI22_X1_LVT i_1_0_939( + .A1(registers_16__ap[12]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[12]), + .ZN(n_1_0_894) + ); + SDFF_X1_LVT \registers_reg[5][12] ( + .CK(n_0_35), .D(registers[12]), .Q(registers_5__ap[12]), .QN(), .SE(dftIn), + .SI(registers_3__ap[12]) + ); + SDFF_X1_LVT \registers_reg[31][12] ( + .CK(n_0_61), .D(registers[12]), .Q(registers_31__ap[12]), .QN(), .SE(dftIn), + .SI(registers_5__ap[12]) + ); + AOI22_X1_LVT i_1_0_938( + .A1(registers_5__ap[12]), .A2(n_1_0_1273), .B1(n_1_0_1266), .B2(registers_31__ap[12]), + .ZN(n_1_0_893) + ); + SDFF_X1_LVT \registers_reg[15][12] ( + .CK(n_0_45), .D(registers[12]), .Q(registers_15__ap[12]), .QN(), .SE(dftIn), + .SI(registers_16__ap[12]) + ); + SDFF_X1_LVT \registers_reg[23][12] ( + .CK(n_0_53), .D(registers[12]), .Q(registers_23__ap[12]), .QN(), .SE(dftIn), + .SI(registers_1__ap[12]) + ); + AOI22_X1_LVT i_1_0_937( + .A1(registers_15__ap[12]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[12]), + .ZN(n_1_0_892) + ); + NAND4_X1_LVT i_1_0_936( + .A1(n_1_0_895), .A2(n_1_0_894), .A3(n_1_0_893), .A4(n_1_0_892), .ZN(n_1_0_891) + ); + SDFF_X1_LVT \registers_reg[18][12] ( + .CK(n_0_48), .D(registers[12]), .Q(registers_18__ap[12]), .QN(), .SE(dftIn), + .SI(registers_23__ap[12]) + ); + SDFF_X1_LVT \registers_reg[30][12] ( + .CK(n_0_60), .D(registers[12]), .Q(registers_30__ap[12]), .QN(), .SE(dftIn), + .SI(registers_29__ap[12]) + ); + AOI22_X1_LVT i_1_0_935( + .A1(registers_18__ap[12]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[12]), + .ZN(n_1_0_890) + ); + SDFF_X1_LVT \registers_reg[20][12] ( + .CK(n_0_50), .D(registers[12]), .Q(registers_20__ap[12]), .QN(), .SE(dftIn), + .SI(registers_18__ap[12]) + ); + SDFF_X1_LVT \registers_reg[4][12] ( + .CK(n_0_34), .D(registers[12]), .Q(registers_4__ap[12]), .QN(), .SE(dftIn), + .SI(registers_31__ap[12]) + ); + AOI22_X1_LVT i_1_0_934( + .A1(registers_20__ap[12]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[12]), + .ZN(n_1_0_889) + ); + SDFF_X1_LVT \registers_reg[22][12] ( + .CK(n_0_52), .D(registers[12]), .Q(registers_22__ap[12]), .QN(), .SE(dftIn), + .SI(registers_20__ap[12]) + ); + SDFF_X1_LVT \registers_reg[21][12] ( + .CK(n_0_51), .D(registers[12]), .Q(registers_21__ap[12]), .QN(), .SE(dftIn), + .SI(registers_22__ap[12]) + ); + AOI22_X1_LVT i_1_0_933( + .A1(registers_22__ap[12]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[12]), + .ZN(n_1_0_888) + ); + SDFF_X1_LVT \registers_reg[24][12] ( + .CK(n_0_54), .D(registers[12]), .Q(registers_24__ap[12]), .QN(), .SE(dftIn), + .SI(registers_30__ap[12]) + ); + SDFF_X1_LVT \registers_reg[12][12] ( + .CK(n_0_42), .D(registers[12]), .Q(registers_12__ap[12]), .QN(), .SE(dftIn), + .SI(registers_15__ap[12]) + ); + AOI22_X1_LVT i_1_0_932( + .A1(registers_24__ap[12]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[12]), + .ZN(n_1_0_887) + ); + NAND4_X1_LVT i_1_0_931( + .A1(n_1_0_890), .A2(n_1_0_889), .A3(n_1_0_888), .A4(n_1_0_887), .ZN(n_1_0_886) + ); + SDFF_X1_LVT \registers_reg[13][12] ( + .CK(n_0_43), .D(registers[12]), .Q(registers_13__ap[12]), .QN(), .SE(dftIn), + .SI(registers_12__ap[12]) + ); + SDFF_X1_LVT \registers_reg[25][12] ( + .CK(n_0_55), .D(registers[12]), .Q(registers_25__ap[12]), .QN(), .SE(dftIn), + .SI(registers_24__ap[12]) + ); + AOI22_X1_LVT i_1_0_930( + .A1(registers_13__ap[12]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[12]), + .ZN(n_1_0_885) + ); + SDFF_X1_LVT \registers_reg[19][12] ( + .CK(n_0_49), .D(registers[12]), .Q(registers_19__ap[12]), .QN(), .SE(dftIn), + .SI(registers_21__ap[12]) + ); + SDFF_X1_LVT \registers_reg[2][12] ( + .CK(n_0_32), .D(registers[12]), .Q(registers_2__ap[12]), .QN(), .SE(dftIn), + .SI(registers_25__ap[12]) + ); + AOI22_X1_LVT i_1_0_929( + .A1(registers_19__ap[12]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[12]), + .ZN(n_1_0_884) + ); + SDFF_X1_LVT \registers_reg[7][12] ( + .CK(n_0_37), .D(registers[12]), .Q(registers_7__ap[12]), .QN(), .SE(dftIn), + .SI(registers_4__ap[12]) + ); + SDFF_X1_LVT \registers_reg[14][12] ( + .CK(n_0_44), .D(registers[12]), .Q(registers_14__ap[12]), .QN(), .SE(dftIn), + .SI(registers_13__ap[12]) + ); + AOI22_X1_LVT i_1_0_928( + .A1(registers_7__ap[12]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[12]), + .ZN(n_1_0_883) + ); + SDFF_X1_LVT \registers_reg[27][12] ( + .CK(n_0_57), .D(registers[12]), .Q(registers_27__ap[12]), .QN(), .SE(dftIn), + .SI(registers_2__ap[12]) + ); + SDFF_X1_LVT \registers_reg[11][12] ( + .CK(n_0_41), .D(registers[12]), .Q(registers_11__ap[12]), .QN(), .SE(dftIn), + .SI(registers_14__ap[12]) + ); + AOI22_X1_LVT i_1_0_927( + .A1(registers_27__ap[12]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[12]), + .ZN(n_1_0_882) + ); + NAND4_X1_LVT i_1_0_926( + .A1(n_1_0_885), .A2(n_1_0_884), .A3(n_1_0_883), .A4(n_1_0_882), .ZN(n_1_0_881) + ); + NOR3_X1_LVT i_1_0_925( + .A1(n_1_0_891), .A2(n_1_0_886), .A3(n_1_0_881), .ZN(n_1_0_880) + ); + NAND4_X1_LVT i_1_0_924( + .A1(n_1_0_898), .A2(n_1_0_897), .A3(n_1_0_896), .A4(n_1_0_880), .ZN(RRs1[12]) + ); + AND2_X1_LVT i_0_0_11( + .A1(n_0_0_16), .A2(WRd[11]), .ZN(registers[11]) + ); + SDFF_X1_LVT \registers_reg[28][11] ( + .CK(n_0_58), .D(registers[11]), .Q(registers_28__ap[11]), .QN(), .SE(dftIn), + .SI(registers_27__ap[12]) + ); + SDFF_X1_LVT \registers_reg[17][11] ( + .CK(n_0_47), .D(registers[11]), .Q(registers_17__ap[11]), .QN(), .SE(dftIn), + .SI(registers_19__ap[12]) + ); + AOI22_X1_LVT i_1_0_923( + .A1(registers_28__ap[11]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[11]), + .ZN(n_1_0_879) + ); + SDFF_X1_LVT \registers_reg[10][11] ( + .CK(n_0_40), .D(registers[11]), .Q(registers_10__ap[11]), .QN(), .SE(dftIn), + .SI(registers_11__ap[12]) + ); + SDFF_X1_LVT \registers_reg[26][11] ( + .CK(n_0_56), .D(registers[11]), .Q(registers_26__ap[11]), .QN(), .SE(dftIn), + .SI(registers_28__ap[11]) + ); + SDFF_X1_LVT \registers_reg[8][11] ( + .CK(n_0_38), .D(registers[11]), .Q(registers_8__ap[11]), .QN(), .SE(dftIn), + .SI(registers_7__ap[12]) + ); + AOI222_X1_LVT i_1_0_922( + .A1(registers_10__ap[11]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[11]), + .C1(registers_8__ap[11]), .C2(n_1_0_1282), .ZN(n_1_0_878) + ); + SDFF_X1_LVT \registers_reg[9][11] ( + .CK(n_0_39), .D(registers[11]), .Q(registers_9__ap[11]), .QN(), .SE(dftIn), + .SI(registers_8__ap[11]) + ); + SDFF_X1_LVT \registers_reg[29][11] ( + .CK(n_0_59), .D(registers[11]), .Q(registers_29__ap[11]), .QN(), .SE(dftIn), + .SI(registers_26__ap[11]) + ); + AOI22_X1_LVT i_1_0_921( + .A1(registers_9__ap[11]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[11]), + .ZN(n_1_0_877) + ); + SDFF_X1_LVT \registers_reg[6][11] ( + .CK(n_0_36), .D(registers[11]), .Q(registers_6__ap[11]), .QN(), .SE(dftIn), + .SI(registers_9__ap[11]) + ); + SDFF_X1_LVT \registers_reg[1][11] ( + .CK(n_0_0), .D(registers[11]), .Q(registers_1__ap[11]), .QN(), .SE(dftIn), + .SI(registers_17__ap[11]) + ); + AOI22_X1_LVT i_1_0_920( + .A1(registers_6__ap[11]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[11]), + .ZN(n_1_0_876) + ); + SDFF_X1_LVT \registers_reg[5][11] ( + .CK(n_0_35), .D(registers[11]), .Q(registers_5__ap[11]), .QN(), .SE(dftIn), + .SI(registers_6__ap[11]) + ); + SDFF_X1_LVT \registers_reg[3][11] ( + .CK(n_0_33), .D(registers[11]), .Q(registers_3__ap[11]), .QN(), .SE(dftIn), + .SI(registers_5__ap[11]) + ); + AOI22_X1_LVT i_1_0_919( + .A1(registers_5__ap[11]), .A2(n_1_0_1273), .B1(n_1_0_1257), .B2(registers_3__ap[11]), + .ZN(n_1_0_875) + ); + SDFF_X1_LVT \registers_reg[16][11] ( + .CK(n_0_46), .D(registers[11]), .Q(registers_16__ap[11]), .QN(), .SE(dftIn), + .SI(registers_10__ap[11]) + ); + SDFF_X1_LVT \registers_reg[31][11] ( + .CK(n_0_61), .D(registers[11]), .Q(registers_31__ap[11]), .QN(), .SE(dftIn), + .SI(registers_3__ap[11]) + ); + AOI22_X1_LVT i_1_0_918( + .A1(registers_16__ap[11]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[11]), + .ZN(n_1_0_874) + ); + SDFF_X1_LVT \registers_reg[15][11] ( + .CK(n_0_45), .D(registers[11]), .Q(registers_15__ap[11]), .QN(), .SE(dftIn), + .SI(registers_16__ap[11]) + ); + SDFF_X1_LVT \registers_reg[23][11] ( + .CK(n_0_53), .D(registers[11]), .Q(registers_23__ap[11]), .QN(), .SE(dftIn), + .SI(registers_1__ap[11]) + ); + AOI22_X1_LVT i_1_0_917( + .A1(registers_15__ap[11]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[11]), + .ZN(n_1_0_873) + ); + NAND4_X1_LVT i_1_0_916( + .A1(n_1_0_876), .A2(n_1_0_875), .A3(n_1_0_874), .A4(n_1_0_873), .ZN(n_1_0_872) + ); + SDFF_X1_LVT \registers_reg[18][11] ( + .CK(n_0_48), .D(registers[11]), .Q(registers_18__ap[11]), .QN(), .SE(dftIn), + .SI(registers_23__ap[11]) + ); + SDFF_X1_LVT \registers_reg[30][11] ( + .CK(n_0_60), .D(registers[11]), .Q(registers_30__ap[11]), .QN(), .SE(dftIn), + .SI(registers_29__ap[11]) + ); + AOI22_X1_LVT i_1_0_915( + .A1(registers_18__ap[11]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[11]), + .ZN(n_1_0_871) + ); + SDFF_X1_LVT \registers_reg[20][11] ( + .CK(n_0_50), .D(registers[11]), .Q(registers_20__ap[11]), .QN(), .SE(dftIn), + .SI(registers_18__ap[11]) + ); + SDFF_X1_LVT \registers_reg[4][11] ( + .CK(n_0_34), .D(registers[11]), .Q(registers_4__ap[11]), .QN(), .SE(dftIn), + .SI(registers_31__ap[11]) + ); + AOI22_X1_LVT i_1_0_914( + .A1(registers_20__ap[11]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[11]), + .ZN(n_1_0_870) + ); + SDFF_X1_LVT \registers_reg[22][11] ( + .CK(n_0_52), .D(registers[11]), .Q(registers_22__ap[11]), .QN(), .SE(dftIn), + .SI(registers_20__ap[11]) + ); + SDFF_X1_LVT \registers_reg[21][11] ( + .CK(n_0_51), .D(registers[11]), .Q(registers_21__ap[11]), .QN(), .SE(dftIn), + .SI(registers_22__ap[11]) + ); + AOI22_X1_LVT i_1_0_913( + .A1(registers_22__ap[11]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[11]), + .ZN(n_1_0_869) + ); + SDFF_X1_LVT \registers_reg[24][11] ( + .CK(n_0_54), .D(registers[11]), .Q(registers_24__ap[11]), .QN(), .SE(dftIn), + .SI(registers_30__ap[11]) + ); + SDFF_X1_LVT \registers_reg[12][11] ( + .CK(n_0_42), .D(registers[11]), .Q(registers_12__ap[11]), .QN(), .SE(dftIn), + .SI(registers_15__ap[11]) + ); + AOI22_X1_LVT i_1_0_912( + .A1(registers_24__ap[11]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[11]), + .ZN(n_1_0_868) + ); + NAND4_X1_LVT i_1_0_911( + .A1(n_1_0_871), .A2(n_1_0_870), .A3(n_1_0_869), .A4(n_1_0_868), .ZN(n_1_0_867) + ); + SDFF_X1_LVT \registers_reg[13][11] ( + .CK(n_0_43), .D(registers[11]), .Q(registers_13__ap[11]), .QN(), .SE(dftIn), + .SI(registers_12__ap[11]) + ); + SDFF_X1_LVT \registers_reg[25][11] ( + .CK(n_0_55), .D(registers[11]), .Q(registers_25__ap[11]), .QN(), .SE(dftIn), + .SI(registers_24__ap[11]) + ); + AOI22_X1_LVT i_1_0_910( + .A1(registers_13__ap[11]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[11]), + .ZN(n_1_0_866) + ); + SDFF_X1_LVT \registers_reg[19][11] ( + .CK(n_0_49), .D(registers[11]), .Q(registers_19__ap[11]), .QN(), .SE(dftIn), + .SI(registers_21__ap[11]) + ); + SDFF_X1_LVT \registers_reg[2][11] ( + .CK(n_0_32), .D(registers[11]), .Q(registers_2__ap[11]), .QN(), .SE(dftIn), + .SI(registers_25__ap[11]) + ); + AOI22_X1_LVT i_1_0_909( + .A1(registers_19__ap[11]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[11]), + .ZN(n_1_0_865) + ); + SDFF_X1_LVT \registers_reg[7][11] ( + .CK(n_0_37), .D(registers[11]), .Q(registers_7__ap[11]), .QN(), .SE(dftIn), + .SI(registers_4__ap[11]) + ); + SDFF_X1_LVT \registers_reg[14][11] ( + .CK(n_0_44), .D(registers[11]), .Q(registers_14__ap[11]), .QN(), .SE(dftIn), + .SI(registers_13__ap[11]) + ); + AOI22_X1_LVT i_1_0_908( + .A1(registers_7__ap[11]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[11]), + .ZN(n_1_0_864) + ); + SDFF_X1_LVT \registers_reg[27][11] ( + .CK(n_0_57), .D(registers[11]), .Q(registers_27__ap[11]), .QN(), .SE(dftIn), + .SI(registers_2__ap[11]) + ); + SDFF_X1_LVT \registers_reg[11][11] ( + .CK(n_0_41), .D(registers[11]), .Q(registers_11__ap[11]), .QN(), .SE(dftIn), + .SI(registers_14__ap[11]) + ); + AOI22_X1_LVT i_1_0_907( + .A1(registers_27__ap[11]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[11]), + .ZN(n_1_0_863) + ); + NAND4_X1_LVT i_1_0_906( + .A1(n_1_0_866), .A2(n_1_0_865), .A3(n_1_0_864), .A4(n_1_0_863), .ZN(n_1_0_862) + ); + NOR3_X1_LVT i_1_0_905( + .A1(n_1_0_872), .A2(n_1_0_867), .A3(n_1_0_862), .ZN(n_1_0_861) + ); + NAND4_X1_LVT i_1_0_904( + .A1(n_1_0_879), .A2(n_1_0_878), .A3(n_1_0_877), .A4(n_1_0_861), .ZN(RRs1[11]) + ); + AND2_X1_LVT i_0_0_10( + .A1(n_0_0_16), .A2(WRd[10]), .ZN(registers[10]) + ); + SDFF_X1_LVT \registers_reg[28][10] ( + .CK(n_0_58), .D(registers[10]), .Q(registers_28__ap[10]), .QN(), .SE(dftIn), + .SI(registers_27__ap[11]) + ); + SDFF_X1_LVT \registers_reg[8][10] ( + .CK(n_0_38), .D(registers[10]), .Q(registers_8__ap[10]), .QN(), .SE(dftIn), + .SI(registers_7__ap[11]) + ); + AOI22_X1_LVT i_1_0_902( + .A1(registers_28__ap[10]), .A2(n_1_0_1283), .B1(n_1_0_1282), .B2(registers_8__ap[10]), + .ZN(n_1_0_859) + ); + SDFF_X1_LVT \registers_reg[31][10] ( + .CK(n_0_61), .D(registers[10]), .Q(registers_31__ap[10]), .QN(), .SE(dftIn), + .SI(registers_8__ap[10]) + ); + SDFF_X1_LVT \registers_reg[7][10] ( + .CK(n_0_37), .D(registers[10]), .Q(registers_7__ap[10]), .QN(), .SE(dftIn), + .SI(registers_31__ap[10]) + ); + AOI22_X1_LVT i_1_0_903( + .A1(registers_31__ap[10]), .A2(n_1_0_1266), .B1(n_1_0_1263), .B2(registers_7__ap[10]), + .ZN(n_1_0_860) + ); + SDFF_X1_LVT \registers_reg[24][10] ( + .CK(n_0_54), .D(registers[10]), .Q(registers_24__ap[10]), .QN(), .SE(dftIn), + .SI(registers_28__ap[10]) + ); + SDFF_X1_LVT \registers_reg[20][10] ( + .CK(n_0_50), .D(registers[10]), .Q(registers_20__ap[10]), .QN(), .SE(dftIn), + .SI(registers_19__ap[11]) + ); + AOI22_X1_LVT i_1_0_901( + .A1(registers_24__ap[10]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[10]), + .ZN(n_1_0_858) + ); + SDFF_X1_LVT \registers_reg[4][10] ( + .CK(n_0_34), .D(registers[10]), .Q(registers_4__ap[10]), .QN(), .SE(dftIn), + .SI(registers_7__ap[10]) + ); + SDFF_X1_LVT \registers_reg[23][10] ( + .CK(n_0_53), .D(registers[10]), .Q(registers_23__ap[10]), .QN(), .SE(dftIn), + .SI(registers_20__ap[10]) + ); + AOI22_X1_LVT i_1_0_900( + .A1(registers_4__ap[10]), .A2(n_1_0_1278), .B1(n_1_0_1264), .B2(registers_23__ap[10]), + .ZN(n_1_0_857) + ); + NAND3_X1_LVT i_1_0_899( + .A1(n_1_0_860), .A2(n_1_0_858), .A3(n_1_0_857), .ZN(n_1_0_856) + ); + SDFF_X1_LVT \registers_reg[27][10] ( + .CK(n_0_57), .D(registers[10]), .Q(registers_27__ap[10]), .QN(), .SE(dftIn), + .SI(registers_24__ap[10]) + ); + SDFF_X1_LVT \registers_reg[29][10] ( + .CK(n_0_59), .D(registers[10]), .Q(registers_29__ap[10]), .QN(), .SE(dftIn), + .SI(registers_27__ap[10]) + ); + AOI221_X1_LVT i_1_0_898( + .A(n_1_0_856), .B1(n_1_0_1279), .B2(registers_27__ap[10]), .C1(registers_29__ap[10]), + .C2(n_1_0_1276), .ZN(n_1_0_855) + ); + SDFF_X1_LVT \registers_reg[10][10] ( + .CK(n_0_40), .D(registers[10]), .Q(registers_10__ap[10]), .QN(), .SE(dftIn), + .SI(registers_11__ap[11]) + ); + SDFF_X1_LVT \registers_reg[30][10] ( + .CK(n_0_60), .D(registers[10]), .Q(registers_30__ap[10]), .QN(), .SE(dftIn), + .SI(registers_29__ap[10]) + ); + SDFF_X1_LVT \registers_reg[25][10] ( + .CK(n_0_55), .D(registers[10]), .Q(registers_25__ap[10]), .QN(), .SE(dftIn), + .SI(registers_30__ap[10]) + ); + AOI222_X1_LVT i_1_0_897( + .A1(registers_10__ap[10]), .A2(n_1_0_1287), .B1(n_1_0_1272), .B2(registers_30__ap[10]), + .C1(n_1_0_1269), .C2(registers_25__ap[10]), .ZN(n_1_0_854) + ); + NAND3_X1_LVT i_1_0_896( + .A1(n_1_0_859), .A2(n_1_0_855), .A3(n_1_0_854), .ZN(n_1_0_853) + ); + SDFF_X1_LVT \registers_reg[21][10] ( + .CK(n_0_51), .D(registers[10]), .Q(registers_21__ap[10]), .QN(), .SE(dftIn), + .SI(registers_23__ap[10]) + ); + SDFF_X1_LVT \registers_reg[13][10] ( + .CK(n_0_43), .D(registers[10]), .Q(registers_13__ap[10]), .QN(), .SE(dftIn), + .SI(registers_10__ap[10]) + ); + AOI221_X1_LVT i_1_0_895( + .A(n_1_0_853), .B1(n_1_0_1259), .B2(registers_21__ap[10]), .C1(registers_13__ap[10]), + .C2(n_1_0_1277), .ZN(n_1_0_852) + ); + SDFF_X1_LVT \registers_reg[18][10] ( + .CK(n_0_48), .D(registers[10]), .Q(registers_18__ap[10]), .QN(), .SE(dftIn), + .SI(registers_21__ap[10]) + ); + SDFF_X1_LVT \registers_reg[26][10] ( + .CK(n_0_56), .D(registers[10]), .Q(registers_26__ap[10]), .QN(), .SE(dftIn), + .SI(registers_25__ap[10]) + ); + AOI22_X1_LVT i_1_0_894( + .A1(registers_18__ap[10]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[10]), + .ZN(n_1_0_851) + ); + SDFF_X1_LVT \registers_reg[17][10] ( + .CK(n_0_47), .D(registers[10]), .Q(registers_17__ap[10]), .QN(), .SE(dftIn), + .SI(registers_18__ap[10]) + ); + SDFF_X1_LVT \registers_reg[12][10] ( + .CK(n_0_42), .D(registers[10]), .Q(registers_12__ap[10]), .QN(), .SE(dftIn), + .SI(registers_13__ap[10]) + ); + AOI22_X1_LVT i_1_0_893( + .A1(registers_17__ap[10]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[10]), + .ZN(n_1_0_850) + ); + SDFF_X1_LVT \registers_reg[15][10] ( + .CK(n_0_45), .D(registers[10]), .Q(registers_15__ap[10]), .QN(), .SE(dftIn), + .SI(registers_12__ap[10]) + ); + SDFF_X1_LVT \registers_reg[5][10] ( + .CK(n_0_35), .D(registers[10]), .Q(registers_5__ap[10]), .QN(), .SE(dftIn), + .SI(registers_4__ap[10]) + ); + AOI22_X1_LVT i_1_0_892( + .A1(registers_15__ap[10]), .A2(n_1_0_1286), .B1(n_1_0_1273), .B2(registers_5__ap[10]), + .ZN(n_1_0_849) + ); + NAND3_X1_LVT i_1_0_891( + .A1(n_1_0_851), .A2(n_1_0_850), .A3(n_1_0_849), .ZN(n_1_0_848) + ); + SDFF_X1_LVT \registers_reg[22][10] ( + .CK(n_0_52), .D(registers[10]), .Q(registers_22__ap[10]), .QN(), .SE(dftIn), + .SI(registers_17__ap[10]) + ); + SDFF_X1_LVT \registers_reg[16][10] ( + .CK(n_0_46), .D(registers[10]), .Q(registers_16__ap[10]), .QN(), .SE(dftIn), + .SI(registers_15__ap[10]) + ); + AOI221_X1_LVT i_1_0_890( + .A(n_1_0_848), .B1(n_1_0_1294), .B2(registers_22__ap[10]), .C1(registers_16__ap[10]), + .C2(n_1_0_1267), .ZN(n_1_0_847) + ); + SDFF_X1_LVT \registers_reg[9][10] ( + .CK(n_0_39), .D(registers[10]), .Q(registers_9__ap[10]), .QN(), .SE(dftIn), + .SI(registers_5__ap[10]) + ); + SDFF_X1_LVT \registers_reg[1][10] ( + .CK(n_0_0), .D(registers[10]), .Q(registers_1__ap[10]), .QN(), .SE(dftIn), + .SI(registers_22__ap[10]) + ); + AOI22_X1_LVT i_1_0_889( + .A1(registers_9__ap[10]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[10]), + .ZN(n_1_0_846) + ); + SDFF_X1_LVT \registers_reg[6][10] ( + .CK(n_0_36), .D(registers[10]), .Q(registers_6__ap[10]), .QN(), .SE(dftIn), + .SI(registers_9__ap[10]) + ); + SDFF_X1_LVT \registers_reg[14][10] ( + .CK(n_0_44), .D(registers[10]), .Q(registers_14__ap[10]), .QN(), .SE(dftIn), + .SI(registers_16__ap[10]) + ); + AOI22_X1_LVT i_1_0_888( + .A1(registers_6__ap[10]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[10]), + .ZN(n_1_0_845) + ); + SDFF_X1_LVT \registers_reg[19][10] ( + .CK(n_0_49), .D(registers[10]), .Q(registers_19__ap[10]), .QN(), .SE(dftIn), + .SI(registers_1__ap[10]) + ); + SDFF_X1_LVT \registers_reg[3][10] ( + .CK(n_0_33), .D(registers[10]), .Q(registers_3__ap[10]), .QN(), .SE(dftIn), + .SI(registers_6__ap[10]) + ); + AOI22_X1_LVT i_1_0_887( + .A1(registers_19__ap[10]), .A2(n_1_0_1295), .B1(n_1_0_1257), .B2(registers_3__ap[10]), + .ZN(n_1_0_844) + ); + NAND3_X1_LVT i_1_0_886( + .A1(n_1_0_846), .A2(n_1_0_845), .A3(n_1_0_844), .ZN(n_1_0_843) + ); + SDFF_X1_LVT \registers_reg[11][10] ( + .CK(n_0_41), .D(registers[10]), .Q(registers_11__ap[10]), .QN(), .SE(dftIn), + .SI(registers_14__ap[10]) + ); + SDFF_X1_LVT \registers_reg[2][10] ( + .CK(n_0_32), .D(registers[10]), .Q(registers_2__ap[10]), .QN(), .SE(dftIn), + .SI(registers_26__ap[10]) + ); + AOI221_X1_LVT i_1_0_885( + .A(n_1_0_843), .B1(n_1_0_1270), .B2(registers_11__ap[10]), .C1(registers_2__ap[10]), + .C2(n_1_0_1268), .ZN(n_1_0_842) + ); + NAND3_X1_LVT i_1_0_884( + .A1(n_1_0_852), .A2(n_1_0_847), .A3(n_1_0_842), .ZN(RRs1[10]) + ); + AND2_X1_LVT i_0_0_9( + .A1(n_0_0_16), .A2(WRd[9]), .ZN(registers[9]) + ); + SDFF_X1_LVT \registers_reg[13][9] ( + .CK(n_0_43), .D(registers[9]), .Q(registers_13__ap[9]), .QN(), .SE(dftIn), + .SI(registers_11__ap[10]) + ); + SDFF_X1_LVT \registers_reg[21][9] ( + .CK(n_0_51), .D(registers[9]), .Q(registers_21__ap[9]), .QN(), .SE(dftIn), + .SI(registers_19__ap[10]) + ); + AOI22_X1_LVT i_1_0_880( + .A1(registers_13__ap[9]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[9]), + .ZN(n_1_0_838) + ); + SDFF_X1_LVT \registers_reg[29][9] ( + .CK(n_0_59), .D(registers[9]), .Q(registers_29__ap[9]), .QN(), .SE(dftIn), + .SI(registers_2__ap[10]) + ); + SDFF_X1_LVT \registers_reg[23][9] ( + .CK(n_0_53), .D(registers[9]), .Q(registers_23__ap[9]), .QN(), .SE(dftIn), + .SI(registers_21__ap[9]) + ); + AOI22_X1_LVT i_1_0_883( + .A1(registers_29__ap[9]), .A2(n_1_0_1276), .B1(n_1_0_1264), .B2(registers_23__ap[9]), + .ZN(n_1_0_841) + ); + SDFF_X1_LVT \registers_reg[24][9] ( + .CK(n_0_54), .D(registers[9]), .Q(registers_24__ap[9]), .QN(), .SE(dftIn), + .SI(registers_29__ap[9]) + ); + SDFF_X1_LVT \registers_reg[20][9] ( + .CK(n_0_50), .D(registers[9]), .Q(registers_20__ap[9]), .QN(), .SE(dftIn), + .SI(registers_23__ap[9]) + ); + AOI22_X1_LVT i_1_0_879( + .A1(registers_24__ap[9]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[9]), + .ZN(n_1_0_837) + ); + SDFF_X1_LVT \registers_reg[7][9] ( + .CK(n_0_37), .D(registers[9]), .Q(registers_7__ap[9]), .QN(), .SE(dftIn), + .SI(registers_3__ap[10]) + ); + SDFF_X1_LVT \registers_reg[3][9] ( + .CK(n_0_33), .D(registers[9]), .Q(registers_3__ap[9]), .QN(), .SE(dftIn), + .SI(registers_7__ap[9]) + ); + AOI22_X1_LVT i_1_0_882( + .A1(registers_7__ap[9]), .A2(n_1_0_1263), .B1(n_1_0_1257), .B2(registers_3__ap[9]), + .ZN(n_1_0_840) + ); + INV_X1_LVT i_1_0_881( + .A(n_1_0_840), .ZN(n_1_0_839) + ); + SDFF_X1_LVT \registers_reg[31][9] ( + .CK(n_0_61), .D(registers[9]), .Q(registers_31__ap[9]), .QN(), .SE(dftIn), + .SI(registers_3__ap[9]) + ); + SDFF_X1_LVT \registers_reg[4][9] ( + .CK(n_0_34), .D(registers[9]), .Q(registers_4__ap[9]), .QN(), .SE(dftIn), + .SI(registers_31__ap[9]) + ); + AOI221_X1_LVT i_1_0_878( + .A(n_1_0_839), .B1(n_1_0_1266), .B2(registers_31__ap[9]), .C1(registers_4__ap[9]), + .C2(n_1_0_1278), .ZN(n_1_0_836) + ); + SDFF_X1_LVT \registers_reg[10][9] ( + .CK(n_0_40), .D(registers[9]), .Q(registers_10__ap[9]), .QN(), .SE(dftIn), + .SI(registers_13__ap[9]) + ); + SDFF_X1_LVT \registers_reg[26][9] ( + .CK(n_0_56), .D(registers[9]), .Q(registers_26__ap[9]), .QN(), .SE(dftIn), + .SI(registers_24__ap[9]) + ); + SDFF_X1_LVT \registers_reg[25][9] ( + .CK(n_0_55), .D(registers[9]), .Q(registers_25__ap[9]), .QN(), .SE(dftIn), + .SI(registers_26__ap[9]) + ); + AOI222_X1_LVT i_1_0_877( + .A1(registers_10__ap[9]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[9]), + .C1(registers_25__ap[9]), .C2(n_1_0_1269), .ZN(n_1_0_835) + ); + NAND4_X1_LVT i_1_0_876( + .A1(n_1_0_841), .A2(n_1_0_837), .A3(n_1_0_836), .A4(n_1_0_835), .ZN(n_1_0_834) + ); + SDFF_X1_LVT \registers_reg[8][9] ( + .CK(n_0_38), .D(registers[9]), .Q(registers_8__ap[9]), .QN(), .SE(dftIn), + .SI(registers_4__ap[9]) + ); + SDFF_X1_LVT \registers_reg[28][9] ( + .CK(n_0_58), .D(registers[9]), .Q(registers_28__ap[9]), .QN(), .SE(dftIn), + .SI(registers_25__ap[9]) + ); + AOI221_X1_LVT i_1_0_875( + .A(n_1_0_834), .B1(n_1_0_1282), .B2(registers_8__ap[9]), .C1(registers_28__ap[9]), + .C2(n_1_0_1283), .ZN(n_1_0_833) + ); + SDFF_X1_LVT \registers_reg[18][9] ( + .CK(n_0_48), .D(registers[9]), .Q(registers_18__ap[9]), .QN(), .SE(dftIn), + .SI(registers_20__ap[9]) + ); + SDFF_X1_LVT \registers_reg[30][9] ( + .CK(n_0_60), .D(registers[9]), .Q(registers_30__ap[9]), .QN(), .SE(dftIn), + .SI(registers_28__ap[9]) + ); + AOI22_X1_LVT i_1_0_874( + .A1(registers_18__ap[9]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[9]), + .ZN(n_1_0_832) + ); + SDFF_X1_LVT \registers_reg[17][9] ( + .CK(n_0_47), .D(registers[9]), .Q(registers_17__ap[9]), .QN(), .SE(dftIn), + .SI(registers_18__ap[9]) + ); + SDFF_X1_LVT \registers_reg[12][9] ( + .CK(n_0_42), .D(registers[9]), .Q(registers_12__ap[9]), .QN(), .SE(dftIn), + .SI(registers_10__ap[9]) + ); + AOI22_X1_LVT i_1_0_873( + .A1(registers_17__ap[9]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[9]), + .ZN(n_1_0_831) + ); + SDFF_X1_LVT \registers_reg[15][9] ( + .CK(n_0_45), .D(registers[9]), .Q(registers_15__ap[9]), .QN(), .SE(dftIn), + .SI(registers_12__ap[9]) + ); + SDFF_X1_LVT \registers_reg[5][9] ( + .CK(n_0_35), .D(registers[9]), .Q(registers_5__ap[9]), .QN(), .SE(dftIn), + .SI(registers_8__ap[9]) + ); + AOI22_X1_LVT i_1_0_872( + .A1(registers_15__ap[9]), .A2(n_1_0_1286), .B1(n_1_0_1273), .B2(registers_5__ap[9]), + .ZN(n_1_0_830) + ); + NAND3_X1_LVT i_1_0_871( + .A1(n_1_0_832), .A2(n_1_0_831), .A3(n_1_0_830), .ZN(n_1_0_829) + ); + SDFF_X1_LVT \registers_reg[22][9] ( + .CK(n_0_52), .D(registers[9]), .Q(registers_22__ap[9]), .QN(), .SE(dftIn), + .SI(registers_17__ap[9]) + ); + SDFF_X1_LVT \registers_reg[16][9] ( + .CK(n_0_46), .D(registers[9]), .Q(registers_16__ap[9]), .QN(), .SE(dftIn), + .SI(registers_15__ap[9]) + ); + AOI221_X1_LVT i_1_0_870( + .A(n_1_0_829), .B1(n_1_0_1294), .B2(registers_22__ap[9]), .C1(registers_16__ap[9]), + .C2(n_1_0_1267), .ZN(n_1_0_828) + ); + SDFF_X1_LVT \registers_reg[9][9] ( + .CK(n_0_39), .D(registers[9]), .Q(registers_9__ap[9]), .QN(), .SE(dftIn), + .SI(registers_5__ap[9]) + ); + SDFF_X1_LVT \registers_reg[1][9] ( + .CK(n_0_0), .D(registers[9]), .Q(registers_1__ap[9]), .QN(), .SE(dftIn), + .SI(registers_22__ap[9]) + ); + AOI22_X1_LVT i_1_0_869( + .A1(registers_9__ap[9]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[9]), + .ZN(n_1_0_827) + ); + SDFF_X1_LVT \registers_reg[6][9] ( + .CK(n_0_36), .D(registers[9]), .Q(registers_6__ap[9]), .QN(), .SE(dftIn), + .SI(registers_9__ap[9]) + ); + SDFF_X1_LVT \registers_reg[14][9] ( + .CK(n_0_44), .D(registers[9]), .Q(registers_14__ap[9]), .QN(), .SE(dftIn), + .SI(registers_16__ap[9]) + ); + AOI22_X1_LVT i_1_0_868( + .A1(registers_6__ap[9]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[9]), + .ZN(n_1_0_826) + ); + SDFF_X1_LVT \registers_reg[19][9] ( + .CK(n_0_49), .D(registers[9]), .Q(registers_19__ap[9]), .QN(), .SE(dftIn), + .SI(registers_1__ap[9]) + ); + SDFF_X1_LVT \registers_reg[2][9] ( + .CK(n_0_32), .D(registers[9]), .Q(registers_2__ap[9]), .QN(), .SE(dftIn), + .SI(registers_30__ap[9]) + ); + AOI22_X1_LVT i_1_0_867( + .A1(registers_19__ap[9]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[9]), + .ZN(n_1_0_825) + ); + NAND3_X1_LVT i_1_0_866( + .A1(n_1_0_827), .A2(n_1_0_826), .A3(n_1_0_825), .ZN(n_1_0_824) + ); + SDFF_X1_LVT \registers_reg[11][9] ( + .CK(n_0_41), .D(registers[9]), .Q(registers_11__ap[9]), .QN(), .SE(dftIn), + .SI(registers_14__ap[9]) + ); + SDFF_X1_LVT \registers_reg[27][9] ( + .CK(n_0_57), .D(registers[9]), .Q(registers_27__ap[9]), .QN(), .SE(dftIn), + .SI(registers_2__ap[9]) + ); + AOI221_X1_LVT i_1_0_865( + .A(n_1_0_824), .B1(n_1_0_1270), .B2(registers_11__ap[9]), .C1(registers_27__ap[9]), + .C2(n_1_0_1279), .ZN(n_1_0_823) + ); + NAND4_X1_LVT i_1_0_864( + .A1(n_1_0_838), .A2(n_1_0_833), .A3(n_1_0_828), .A4(n_1_0_823), .ZN(RRs1[9]) + ); + AND2_X1_LVT i_0_0_8( + .A1(n_0_0_16), .A2(WRd[8]), .ZN(registers[8]) + ); + SDFF_X1_LVT \registers_reg[13][8] ( + .CK(n_0_43), .D(registers[8]), .Q(registers_13__ap[8]), .QN(), .SE(dftIn), + .SI(registers_11__ap[9]) + ); + SDFF_X1_LVT \registers_reg[21][8] ( + .CK(n_0_51), .D(registers[8]), .Q(registers_21__ap[8]), .QN(), .SE(dftIn), + .SI(registers_19__ap[9]) + ); + AOI22_X1_LVT i_1_0_860( + .A1(registers_13__ap[8]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[8]), + .ZN(n_1_0_819) + ); + SDFF_X1_LVT \registers_reg[29][8] ( + .CK(n_0_59), .D(registers[8]), .Q(registers_29__ap[8]), .QN(), .SE(dftIn), + .SI(registers_27__ap[9]) + ); + SDFF_X1_LVT \registers_reg[23][8] ( + .CK(n_0_53), .D(registers[8]), .Q(registers_23__ap[8]), .QN(), .SE(dftIn), + .SI(registers_21__ap[8]) + ); + AOI22_X1_LVT i_1_0_863( + .A1(registers_29__ap[8]), .A2(n_1_0_1276), .B1(n_1_0_1264), .B2(registers_23__ap[8]), + .ZN(n_1_0_822) + ); + SDFF_X1_LVT \registers_reg[24][8] ( + .CK(n_0_54), .D(registers[8]), .Q(registers_24__ap[8]), .QN(), .SE(dftIn), + .SI(registers_29__ap[8]) + ); + SDFF_X1_LVT \registers_reg[20][8] ( + .CK(n_0_50), .D(registers[8]), .Q(registers_20__ap[8]), .QN(), .SE(dftIn), + .SI(registers_23__ap[8]) + ); + AOI22_X1_LVT i_1_0_859( + .A1(registers_24__ap[8]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[8]), + .ZN(n_1_0_818) + ); + SDFF_X1_LVT \registers_reg[7][8] ( + .CK(n_0_37), .D(registers[8]), .Q(registers_7__ap[8]), .QN(), .SE(dftIn), + .SI(registers_6__ap[9]) + ); + SDFF_X1_LVT \registers_reg[3][8] ( + .CK(n_0_33), .D(registers[8]), .Q(registers_3__ap[8]), .QN(), .SE(dftIn), + .SI(registers_7__ap[8]) + ); + AOI22_X1_LVT i_1_0_862( + .A1(registers_7__ap[8]), .A2(n_1_0_1263), .B1(n_1_0_1257), .B2(registers_3__ap[8]), + .ZN(n_1_0_821) + ); + INV_X1_LVT i_1_0_861( + .A(n_1_0_821), .ZN(n_1_0_820) + ); + SDFF_X1_LVT \registers_reg[31][8] ( + .CK(n_0_61), .D(registers[8]), .Q(registers_31__ap[8]), .QN(), .SE(dftIn), + .SI(registers_3__ap[8]) + ); + SDFF_X1_LVT \registers_reg[4][8] ( + .CK(n_0_34), .D(registers[8]), .Q(registers_4__ap[8]), .QN(), .SE(dftIn), + .SI(registers_31__ap[8]) + ); + AOI221_X1_LVT i_1_0_858( + .A(n_1_0_820), .B1(n_1_0_1266), .B2(registers_31__ap[8]), .C1(registers_4__ap[8]), + .C2(n_1_0_1278), .ZN(n_1_0_817) + ); + SDFF_X1_LVT \registers_reg[10][8] ( + .CK(n_0_40), .D(registers[8]), .Q(registers_10__ap[8]), .QN(), .SE(dftIn), + .SI(registers_13__ap[8]) + ); + SDFF_X1_LVT \registers_reg[26][8] ( + .CK(n_0_56), .D(registers[8]), .Q(registers_26__ap[8]), .QN(), .SE(dftIn), + .SI(registers_24__ap[8]) + ); + SDFF_X1_LVT \registers_reg[25][8] ( + .CK(n_0_55), .D(registers[8]), .Q(registers_25__ap[8]), .QN(), .SE(dftIn), + .SI(registers_26__ap[8]) + ); + AOI222_X1_LVT i_1_0_857( + .A1(registers_10__ap[8]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[8]), + .C1(registers_25__ap[8]), .C2(n_1_0_1269), .ZN(n_1_0_816) + ); + NAND4_X1_LVT i_1_0_856( + .A1(n_1_0_822), .A2(n_1_0_818), .A3(n_1_0_817), .A4(n_1_0_816), .ZN(n_1_0_815) + ); + SDFF_X1_LVT \registers_reg[8][8] ( + .CK(n_0_38), .D(registers[8]), .Q(registers_8__ap[8]), .QN(), .SE(dftIn), + .SI(registers_4__ap[8]) + ); + SDFF_X1_LVT \registers_reg[28][8] ( + .CK(n_0_58), .D(registers[8]), .Q(registers_28__ap[8]), .QN(), .SE(dftIn), + .SI(registers_25__ap[8]) + ); + AOI221_X1_LVT i_1_0_855( + .A(n_1_0_815), .B1(n_1_0_1282), .B2(registers_8__ap[8]), .C1(registers_28__ap[8]), + .C2(n_1_0_1283), .ZN(n_1_0_814) + ); + SDFF_X1_LVT \registers_reg[18][8] ( + .CK(n_0_48), .D(registers[8]), .Q(registers_18__ap[8]), .QN(), .SE(dftIn), + .SI(registers_20__ap[8]) + ); + SDFF_X1_LVT \registers_reg[30][8] ( + .CK(n_0_60), .D(registers[8]), .Q(registers_30__ap[8]), .QN(), .SE(dftIn), + .SI(registers_28__ap[8]) + ); + AOI22_X1_LVT i_1_0_854( + .A1(registers_18__ap[8]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[8]), + .ZN(n_1_0_813) + ); + SDFF_X1_LVT \registers_reg[17][8] ( + .CK(n_0_47), .D(registers[8]), .Q(registers_17__ap[8]), .QN(), .SE(dftIn), + .SI(registers_18__ap[8]) + ); + SDFF_X1_LVT \registers_reg[12][8] ( + .CK(n_0_42), .D(registers[8]), .Q(registers_12__ap[8]), .QN(), .SE(dftIn), + .SI(registers_10__ap[8]) + ); + AOI22_X1_LVT i_1_0_853( + .A1(registers_17__ap[8]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[8]), + .ZN(n_1_0_812) + ); + SDFF_X1_LVT \registers_reg[15][8] ( + .CK(n_0_45), .D(registers[8]), .Q(registers_15__ap[8]), .QN(), .SE(dftIn), + .SI(registers_12__ap[8]) + ); + SDFF_X1_LVT \registers_reg[5][8] ( + .CK(n_0_35), .D(registers[8]), .Q(registers_5__ap[8]), .QN(), .SE(dftIn), + .SI(registers_8__ap[8]) + ); + AOI22_X1_LVT i_1_0_852( + .A1(registers_15__ap[8]), .A2(n_1_0_1286), .B1(n_1_0_1273), .B2(registers_5__ap[8]), + .ZN(n_1_0_811) + ); + NAND3_X1_LVT i_1_0_851( + .A1(n_1_0_813), .A2(n_1_0_812), .A3(n_1_0_811), .ZN(n_1_0_810) + ); + SDFF_X1_LVT \registers_reg[22][8] ( + .CK(n_0_52), .D(registers[8]), .Q(registers_22__ap[8]), .QN(), .SE(dftIn), + .SI(registers_17__ap[8]) + ); + SDFF_X1_LVT \registers_reg[16][8] ( + .CK(n_0_46), .D(registers[8]), .Q(registers_16__ap[8]), .QN(), .SE(dftIn), + .SI(registers_15__ap[8]) + ); + AOI221_X1_LVT i_1_0_850( + .A(n_1_0_810), .B1(n_1_0_1294), .B2(registers_22__ap[8]), .C1(registers_16__ap[8]), + .C2(n_1_0_1267), .ZN(n_1_0_809) + ); + SDFF_X1_LVT \registers_reg[9][8] ( + .CK(n_0_39), .D(registers[8]), .Q(registers_9__ap[8]), .QN(), .SE(dftIn), + .SI(registers_5__ap[8]) + ); + SDFF_X1_LVT \registers_reg[1][8] ( + .CK(n_0_0), .D(registers[8]), .Q(registers_1__ap[8]), .QN(), .SE(dftIn), + .SI(registers_22__ap[8]) + ); + AOI22_X1_LVT i_1_0_849( + .A1(registers_9__ap[8]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[8]), + .ZN(n_1_0_808) + ); + SDFF_X1_LVT \registers_reg[6][8] ( + .CK(n_0_36), .D(registers[8]), .Q(registers_6__ap[8]), .QN(), .SE(dftIn), + .SI(registers_9__ap[8]) + ); + SDFF_X1_LVT \registers_reg[14][8] ( + .CK(n_0_44), .D(registers[8]), .Q(registers_14__ap[8]), .QN(), .SE(dftIn), + .SI(registers_16__ap[8]) + ); + AOI22_X1_LVT i_1_0_848( + .A1(registers_6__ap[8]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[8]), + .ZN(n_1_0_807) + ); + SDFF_X1_LVT \registers_reg[19][8] ( + .CK(n_0_49), .D(registers[8]), .Q(registers_19__ap[8]), .QN(), .SE(dftIn), + .SI(registers_1__ap[8]) + ); + SDFF_X1_LVT \registers_reg[2][8] ( + .CK(n_0_32), .D(registers[8]), .Q(registers_2__ap[8]), .QN(), .SE(dftIn), + .SI(registers_30__ap[8]) + ); + AOI22_X1_LVT i_1_0_847( + .A1(registers_19__ap[8]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[8]), + .ZN(n_1_0_806) + ); + NAND3_X1_LVT i_1_0_846( + .A1(n_1_0_808), .A2(n_1_0_807), .A3(n_1_0_806), .ZN(n_1_0_805) + ); + SDFF_X1_LVT \registers_reg[11][8] ( + .CK(n_0_41), .D(registers[8]), .Q(registers_11__ap[8]), .QN(), .SE(dftIn), + .SI(registers_14__ap[8]) + ); + SDFF_X1_LVT \registers_reg[27][8] ( + .CK(n_0_57), .D(registers[8]), .Q(registers_27__ap[8]), .QN(), .SE(dftIn), + .SI(registers_2__ap[8]) + ); + AOI221_X1_LVT i_1_0_845( + .A(n_1_0_805), .B1(n_1_0_1270), .B2(registers_11__ap[8]), .C1(registers_27__ap[8]), + .C2(n_1_0_1279), .ZN(n_1_0_804) + ); + NAND4_X1_LVT i_1_0_844( + .A1(n_1_0_819), .A2(n_1_0_814), .A3(n_1_0_809), .A4(n_1_0_804), .ZN(RRs1[8]) + ); + AND2_X1_LVT i_0_0_7( + .A1(n_0_0_16), .A2(WRd[7]), .ZN(registers[7]) + ); + SDFF_X1_LVT \registers_reg[13][7] ( + .CK(n_0_43), .D(registers[7]), .Q(registers_13__ap[7]), .QN(), .SE(dftIn), + .SI(registers_11__ap[8]) + ); + SDFF_X1_LVT \registers_reg[21][7] ( + .CK(n_0_51), .D(registers[7]), .Q(registers_21__ap[7]), .QN(), .SE(dftIn), + .SI(registers_19__ap[8]) + ); + AOI22_X1_LVT i_1_0_843( + .A1(registers_13__ap[7]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[7]), + .ZN(n_1_0_803) + ); + SDFF_X1_LVT \registers_reg[18][7] ( + .CK(n_0_48), .D(registers[7]), .Q(registers_18__ap[7]), .QN(), .SE(dftIn), + .SI(registers_21__ap[7]) + ); + SDFF_X1_LVT \registers_reg[10][7] ( + .CK(n_0_40), .D(registers[7]), .Q(registers_10__ap[7]), .QN(), .SE(dftIn), + .SI(registers_13__ap[7]) + ); + SDFF_X1_LVT \registers_reg[25][7] ( + .CK(n_0_55), .D(registers[7]), .Q(registers_25__ap[7]), .QN(), .SE(dftIn), + .SI(registers_27__ap[8]) + ); + AOI222_X1_LVT i_1_0_842( + .A1(registers_18__ap[7]), .A2(n_1_0_1297), .B1(n_1_0_1287), .B2(registers_10__ap[7]), + .C1(registers_25__ap[7]), .C2(n_1_0_1269), .ZN(n_1_0_802) + ); + SDFF_X1_LVT \registers_reg[28][7] ( + .CK(n_0_58), .D(registers[7]), .Q(registers_28__ap[7]), .QN(), .SE(dftIn), + .SI(registers_25__ap[7]) + ); + SDFF_X1_LVT \registers_reg[8][7] ( + .CK(n_0_38), .D(registers[7]), .Q(registers_8__ap[7]), .QN(), .SE(dftIn), + .SI(registers_6__ap[8]) + ); + AOI22_X1_LVT i_1_0_841( + .A1(registers_28__ap[7]), .A2(n_1_0_1283), .B1(n_1_0_1282), .B2(registers_8__ap[7]), + .ZN(n_1_0_801) + ); + SDFF_X1_LVT \registers_reg[24][7] ( + .CK(n_0_54), .D(registers[7]), .Q(registers_24__ap[7]), .QN(), .SE(dftIn), + .SI(registers_28__ap[7]) + ); + SDFF_X1_LVT \registers_reg[20][7] ( + .CK(n_0_50), .D(registers[7]), .Q(registers_20__ap[7]), .QN(), .SE(dftIn), + .SI(registers_18__ap[7]) + ); + AOI22_X1_LVT i_1_0_840( + .A1(registers_24__ap[7]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[7]), + .ZN(n_1_0_800) + ); + SDFF_X1_LVT \registers_reg[31][7] ( + .CK(n_0_61), .D(registers[7]), .Q(registers_31__ap[7]), .QN(), .SE(dftIn), + .SI(registers_8__ap[7]) + ); + SDFF_X1_LVT \registers_reg[7][7] ( + .CK(n_0_37), .D(registers[7]), .Q(registers_7__ap[7]), .QN(), .SE(dftIn), + .SI(registers_31__ap[7]) + ); + AOI22_X1_LVT i_1_0_839( + .A1(registers_31__ap[7]), .A2(n_1_0_1266), .B1(n_1_0_1263), .B2(registers_7__ap[7]), + .ZN(n_1_0_799) + ); + SDFF_X1_LVT \registers_reg[17][7] ( + .CK(n_0_47), .D(registers[7]), .Q(registers_17__ap[7]), .QN(), .SE(dftIn), + .SI(registers_20__ap[7]) + ); + SDFF_X1_LVT \registers_reg[11][7] ( + .CK(n_0_41), .D(registers[7]), .Q(registers_11__ap[7]), .QN(), .SE(dftIn), + .SI(registers_10__ap[7]) + ); + AOI22_X1_LVT i_1_0_838( + .A1(registers_17__ap[7]), .A2(n_1_0_1271), .B1(n_1_0_1270), .B2(registers_11__ap[7]), + .ZN(n_1_0_798) + ); + SDFF_X1_LVT \registers_reg[27][7] ( + .CK(n_0_57), .D(registers[7]), .Q(registers_27__ap[7]), .QN(), .SE(dftIn), + .SI(registers_24__ap[7]) + ); + SDFF_X1_LVT \registers_reg[29][7] ( + .CK(n_0_59), .D(registers[7]), .Q(registers_29__ap[7]), .QN(), .SE(dftIn), + .SI(registers_27__ap[7]) + ); + AOI22_X1_LVT i_1_0_837( + .A1(registers_27__ap[7]), .A2(n_1_0_1279), .B1(n_1_0_1276), .B2(registers_29__ap[7]), + .ZN(n_1_0_797) + ); + NAND4_X1_LVT i_1_0_836( + .A1(n_1_0_800), .A2(n_1_0_799), .A3(n_1_0_798), .A4(n_1_0_797), .ZN(n_1_0_796) + ); + SDFF_X1_LVT \registers_reg[26][7] ( + .CK(n_0_56), .D(registers[7]), .Q(registers_26__ap[7]), .QN(), .SE(dftIn), + .SI(registers_29__ap[7]) + ); + SDFF_X1_LVT \registers_reg[30][7] ( + .CK(n_0_60), .D(registers[7]), .Q(registers_30__ap[7]), .QN(), .SE(dftIn), + .SI(registers_26__ap[7]) + ); + AOI22_X1_LVT i_1_0_835( + .A1(registers_26__ap[7]), .A2(n_1_0_1285), .B1(n_1_0_1272), .B2(registers_30__ap[7]), + .ZN(n_1_0_795) + ); + SDFF_X1_LVT \registers_reg[4][7] ( + .CK(n_0_34), .D(registers[7]), .Q(registers_4__ap[7]), .QN(), .SE(dftIn), + .SI(registers_7__ap[7]) + ); + SDFF_X1_LVT \registers_reg[12][7] ( + .CK(n_0_42), .D(registers[7]), .Q(registers_12__ap[7]), .QN(), .SE(dftIn), + .SI(registers_11__ap[7]) + ); + AOI22_X1_LVT i_1_0_834( + .A1(registers_4__ap[7]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[7]), + .ZN(n_1_0_794) + ); + SDFF_X1_LVT \registers_reg[15][7] ( + .CK(n_0_45), .D(registers[7]), .Q(registers_15__ap[7]), .QN(), .SE(dftIn), + .SI(registers_12__ap[7]) + ); + SDFF_X1_LVT \registers_reg[16][7] ( + .CK(n_0_46), .D(registers[7]), .Q(registers_16__ap[7]), .QN(), .SE(dftIn), + .SI(registers_15__ap[7]) + ); + AOI22_X1_LVT i_1_0_833( + .A1(registers_15__ap[7]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[7]), + .ZN(n_1_0_793) + ); + SDFF_X1_LVT \registers_reg[22][7] ( + .CK(n_0_52), .D(registers[7]), .Q(registers_22__ap[7]), .QN(), .SE(dftIn), + .SI(registers_17__ap[7]) + ); + SDFF_X1_LVT \registers_reg[5][7] ( + .CK(n_0_35), .D(registers[7]), .Q(registers_5__ap[7]), .QN(), .SE(dftIn), + .SI(registers_4__ap[7]) + ); + AOI22_X1_LVT i_1_0_832( + .A1(registers_22__ap[7]), .A2(n_1_0_1294), .B1(n_1_0_1273), .B2(registers_5__ap[7]), + .ZN(n_1_0_792) + ); + NAND4_X1_LVT i_1_0_831( + .A1(n_1_0_795), .A2(n_1_0_794), .A3(n_1_0_793), .A4(n_1_0_792), .ZN(n_1_0_791) + ); + SDFF_X1_LVT \registers_reg[19][7] ( + .CK(n_0_49), .D(registers[7]), .Q(registers_19__ap[7]), .QN(), .SE(dftIn), + .SI(registers_22__ap[7]) + ); + SDFF_X1_LVT \registers_reg[3][7] ( + .CK(n_0_33), .D(registers[7]), .Q(registers_3__ap[7]), .QN(), .SE(dftIn), + .SI(registers_5__ap[7]) + ); + AOI22_X1_LVT i_1_0_830( + .A1(registers_19__ap[7]), .A2(n_1_0_1295), .B1(n_1_0_1257), .B2(registers_3__ap[7]), + .ZN(n_1_0_790) + ); + SDFF_X1_LVT \registers_reg[9][7] ( + .CK(n_0_39), .D(registers[7]), .Q(registers_9__ap[7]), .QN(), .SE(dftIn), + .SI(registers_3__ap[7]) + ); + SDFF_X1_LVT \registers_reg[1][7] ( + .CK(n_0_0), .D(registers[7]), .Q(registers_1__ap[7]), .QN(), .SE(dftIn), + .SI(registers_19__ap[7]) + ); + AOI22_X1_LVT i_1_0_829( + .A1(registers_9__ap[7]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[7]), + .ZN(n_1_0_789) + ); + SDFF_X1_LVT \registers_reg[6][7] ( + .CK(n_0_36), .D(registers[7]), .Q(registers_6__ap[7]), .QN(), .SE(dftIn), + .SI(registers_9__ap[7]) + ); + SDFF_X1_LVT \registers_reg[14][7] ( + .CK(n_0_44), .D(registers[7]), .Q(registers_14__ap[7]), .QN(), .SE(dftIn), + .SI(registers_16__ap[7]) + ); + AOI22_X1_LVT i_1_0_828( + .A1(registers_6__ap[7]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[7]), + .ZN(n_1_0_788) + ); + SDFF_X1_LVT \registers_reg[2][7] ( + .CK(n_0_32), .D(registers[7]), .Q(registers_2__ap[7]), .QN(), .SE(dftIn), + .SI(registers_30__ap[7]) + ); + SDFF_X1_LVT \registers_reg[23][7] ( + .CK(n_0_53), .D(registers[7]), .Q(registers_23__ap[7]), .QN(), .SE(dftIn), + .SI(registers_1__ap[7]) + ); + AOI22_X1_LVT i_1_0_827( + .A1(registers_2__ap[7]), .A2(n_1_0_1268), .B1(n_1_0_1264), .B2(registers_23__ap[7]), + .ZN(n_1_0_787) + ); + NAND4_X1_LVT i_1_0_826( + .A1(n_1_0_790), .A2(n_1_0_789), .A3(n_1_0_788), .A4(n_1_0_787), .ZN(n_1_0_786) + ); + NOR3_X1_LVT i_1_0_825( + .A1(n_1_0_796), .A2(n_1_0_791), .A3(n_1_0_786), .ZN(n_1_0_785) + ); + NAND4_X1_LVT i_1_0_824( + .A1(n_1_0_803), .A2(n_1_0_802), .A3(n_1_0_801), .A4(n_1_0_785), .ZN(RRs1[7]) + ); + AND2_X1_LVT i_0_0_6( + .A1(n_0_0_16), .A2(WRd[6]), .ZN(registers[6]) + ); + SDFF_X1_LVT \registers_reg[28][6] ( + .CK(n_0_58), .D(registers[6]), .Q(registers_28__ap[6]), .QN(), .SE(dftIn), + .SI(registers_2__ap[7]) + ); + SDFF_X1_LVT \registers_reg[17][6] ( + .CK(n_0_47), .D(registers[6]), .Q(registers_17__ap[6]), .QN(), .SE(dftIn), + .SI(registers_23__ap[7]) + ); + AOI22_X1_LVT i_1_0_823( + .A1(registers_28__ap[6]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[6]), + .ZN(n_1_0_784) + ); + SDFF_X1_LVT \registers_reg[18][6] ( + .CK(n_0_48), .D(registers[6]), .Q(registers_18__ap[6]), .QN(), .SE(dftIn), + .SI(registers_17__ap[6]) + ); + SDFF_X1_LVT \registers_reg[10][6] ( + .CK(n_0_40), .D(registers[6]), .Q(registers_10__ap[6]), .QN(), .SE(dftIn), + .SI(registers_14__ap[7]) + ); + SDFF_X1_LVT \registers_reg[8][6] ( + .CK(n_0_38), .D(registers[6]), .Q(registers_8__ap[6]), .QN(), .SE(dftIn), + .SI(registers_6__ap[7]) + ); + AOI222_X1_LVT i_1_0_822( + .A1(registers_18__ap[6]), .A2(n_1_0_1297), .B1(n_1_0_1287), .B2(registers_10__ap[6]), + .C1(registers_8__ap[6]), .C2(n_1_0_1282), .ZN(n_1_0_783) + ); + SDFF_X1_LVT \registers_reg[9][6] ( + .CK(n_0_39), .D(registers[6]), .Q(registers_9__ap[6]), .QN(), .SE(dftIn), + .SI(registers_8__ap[6]) + ); + SDFF_X1_LVT \registers_reg[29][6] ( + .CK(n_0_59), .D(registers[6]), .Q(registers_29__ap[6]), .QN(), .SE(dftIn), + .SI(registers_28__ap[6]) + ); + AOI22_X1_LVT i_1_0_821( + .A1(registers_9__ap[6]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[6]), + .ZN(n_1_0_782) + ); + SDFF_X1_LVT \registers_reg[6][6] ( + .CK(n_0_36), .D(registers[6]), .Q(registers_6__ap[6]), .QN(), .SE(dftIn), + .SI(registers_9__ap[6]) + ); + SDFF_X1_LVT \registers_reg[1][6] ( + .CK(n_0_0), .D(registers[6]), .Q(registers_1__ap[6]), .QN(), .SE(dftIn), + .SI(registers_18__ap[6]) + ); + AOI22_X1_LVT i_1_0_820( + .A1(registers_6__ap[6]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[6]), + .ZN(n_1_0_781) + ); + SDFF_X1_LVT \registers_reg[15][6] ( + .CK(n_0_45), .D(registers[6]), .Q(registers_15__ap[6]), .QN(), .SE(dftIn), + .SI(registers_10__ap[6]) + ); + SDFF_X1_LVT \registers_reg[27][6] ( + .CK(n_0_57), .D(registers[6]), .Q(registers_27__ap[6]), .QN(), .SE(dftIn), + .SI(registers_29__ap[6]) + ); + AOI22_X1_LVT i_1_0_819( + .A1(registers_15__ap[6]), .A2(n_1_0_1286), .B1(n_1_0_1279), .B2(registers_27__ap[6]), + .ZN(n_1_0_780) + ); + SDFF_X1_LVT \registers_reg[11][6] ( + .CK(n_0_41), .D(registers[6]), .Q(registers_11__ap[6]), .QN(), .SE(dftIn), + .SI(registers_15__ap[6]) + ); + SDFF_X1_LVT \registers_reg[16][6] ( + .CK(n_0_46), .D(registers[6]), .Q(registers_16__ap[6]), .QN(), .SE(dftIn), + .SI(registers_11__ap[6]) + ); + AOI22_X1_LVT i_1_0_818( + .A1(registers_11__ap[6]), .A2(n_1_0_1270), .B1(n_1_0_1267), .B2(registers_16__ap[6]), + .ZN(n_1_0_779) + ); + SDFF_X1_LVT \registers_reg[5][6] ( + .CK(n_0_35), .D(registers[6]), .Q(registers_5__ap[6]), .QN(), .SE(dftIn), + .SI(registers_6__ap[6]) + ); + SDFF_X1_LVT \registers_reg[31][6] ( + .CK(n_0_61), .D(registers[6]), .Q(registers_31__ap[6]), .QN(), .SE(dftIn), + .SI(registers_5__ap[6]) + ); + AOI22_X1_LVT i_1_0_817( + .A1(registers_5__ap[6]), .A2(n_1_0_1273), .B1(n_1_0_1266), .B2(registers_31__ap[6]), + .ZN(n_1_0_778) + ); + NAND4_X1_LVT i_1_0_816( + .A1(n_1_0_781), .A2(n_1_0_780), .A3(n_1_0_779), .A4(n_1_0_778), .ZN(n_1_0_777) + ); + SDFF_X1_LVT \registers_reg[26][6] ( + .CK(n_0_56), .D(registers[6]), .Q(registers_26__ap[6]), .QN(), .SE(dftIn), + .SI(registers_27__ap[6]) + ); + SDFF_X1_LVT \registers_reg[30][6] ( + .CK(n_0_60), .D(registers[6]), .Q(registers_30__ap[6]), .QN(), .SE(dftIn), + .SI(registers_26__ap[6]) + ); + AOI22_X1_LVT i_1_0_815( + .A1(registers_26__ap[6]), .A2(n_1_0_1285), .B1(n_1_0_1272), .B2(registers_30__ap[6]), + .ZN(n_1_0_776) + ); + SDFF_X1_LVT \registers_reg[20][6] ( + .CK(n_0_50), .D(registers[6]), .Q(registers_20__ap[6]), .QN(), .SE(dftIn), + .SI(registers_1__ap[6]) + ); + SDFF_X1_LVT \registers_reg[4][6] ( + .CK(n_0_34), .D(registers[6]), .Q(registers_4__ap[6]), .QN(), .SE(dftIn), + .SI(registers_31__ap[6]) + ); + AOI22_X1_LVT i_1_0_814( + .A1(registers_20__ap[6]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[6]), + .ZN(n_1_0_775) + ); + SDFF_X1_LVT \registers_reg[22][6] ( + .CK(n_0_52), .D(registers[6]), .Q(registers_22__ap[6]), .QN(), .SE(dftIn), + .SI(registers_20__ap[6]) + ); + SDFF_X1_LVT \registers_reg[21][6] ( + .CK(n_0_51), .D(registers[6]), .Q(registers_21__ap[6]), .QN(), .SE(dftIn), + .SI(registers_22__ap[6]) + ); + AOI22_X1_LVT i_1_0_813( + .A1(registers_22__ap[6]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[6]), + .ZN(n_1_0_774) + ); + SDFF_X1_LVT \registers_reg[24][6] ( + .CK(n_0_54), .D(registers[6]), .Q(registers_24__ap[6]), .QN(), .SE(dftIn), + .SI(registers_30__ap[6]) + ); + SDFF_X1_LVT \registers_reg[12][6] ( + .CK(n_0_42), .D(registers[6]), .Q(registers_12__ap[6]), .QN(), .SE(dftIn), + .SI(registers_16__ap[6]) + ); + AOI22_X1_LVT i_1_0_812( + .A1(registers_24__ap[6]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[6]), + .ZN(n_1_0_773) + ); + NAND4_X1_LVT i_1_0_811( + .A1(n_1_0_776), .A2(n_1_0_775), .A3(n_1_0_774), .A4(n_1_0_773), .ZN(n_1_0_772) + ); + SDFF_X1_LVT \registers_reg[13][6] ( + .CK(n_0_43), .D(registers[6]), .Q(registers_13__ap[6]), .QN(), .SE(dftIn), + .SI(registers_12__ap[6]) + ); + SDFF_X1_LVT \registers_reg[25][6] ( + .CK(n_0_55), .D(registers[6]), .Q(registers_25__ap[6]), .QN(), .SE(dftIn), + .SI(registers_24__ap[6]) + ); + AOI22_X1_LVT i_1_0_810( + .A1(registers_13__ap[6]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[6]), + .ZN(n_1_0_771) + ); + SDFF_X1_LVT \registers_reg[7][6] ( + .CK(n_0_37), .D(registers[6]), .Q(registers_7__ap[6]), .QN(), .SE(dftIn), + .SI(registers_4__ap[6]) + ); + SDFF_X1_LVT \registers_reg[14][6] ( + .CK(n_0_44), .D(registers[6]), .Q(registers_14__ap[6]), .QN(), .SE(dftIn), + .SI(registers_13__ap[6]) + ); + AOI22_X1_LVT i_1_0_809( + .A1(registers_7__ap[6]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[6]), + .ZN(n_1_0_770) + ); + SDFF_X1_LVT \registers_reg[19][6] ( + .CK(n_0_49), .D(registers[6]), .Q(registers_19__ap[6]), .QN(), .SE(dftIn), + .SI(registers_21__ap[6]) + ); + SDFF_X1_LVT \registers_reg[3][6] ( + .CK(n_0_33), .D(registers[6]), .Q(registers_3__ap[6]), .QN(), .SE(dftIn), + .SI(registers_7__ap[6]) + ); + AOI22_X1_LVT i_1_0_808( + .A1(registers_19__ap[6]), .A2(n_1_0_1295), .B1(n_1_0_1257), .B2(registers_3__ap[6]), + .ZN(n_1_0_769) + ); + SDFF_X1_LVT \registers_reg[2][6] ( + .CK(n_0_32), .D(registers[6]), .Q(registers_2__ap[6]), .QN(), .SE(dftIn), + .SI(registers_25__ap[6]) + ); + SDFF_X1_LVT \registers_reg[23][6] ( + .CK(n_0_53), .D(registers[6]), .Q(registers_23__ap[6]), .QN(), .SE(dftIn), + .SI(registers_19__ap[6]) + ); + AOI22_X1_LVT i_1_0_807( + .A1(registers_2__ap[6]), .A2(n_1_0_1268), .B1(n_1_0_1264), .B2(registers_23__ap[6]), + .ZN(n_1_0_768) + ); + NAND4_X1_LVT i_1_0_806( + .A1(n_1_0_771), .A2(n_1_0_770), .A3(n_1_0_769), .A4(n_1_0_768), .ZN(n_1_0_767) + ); + NOR3_X1_LVT i_1_0_805( + .A1(n_1_0_777), .A2(n_1_0_772), .A3(n_1_0_767), .ZN(n_1_0_766) + ); + NAND4_X1_LVT i_1_0_804( + .A1(n_1_0_784), .A2(n_1_0_783), .A3(n_1_0_782), .A4(n_1_0_766), .ZN(RRs1[6]) + ); + AND2_X1_LVT i_0_0_5( + .A1(n_0_0_16), .A2(WRd[5]), .ZN(registers[5]) + ); + SDFF_X1_LVT \registers_reg[28][5] ( + .CK(n_0_58), .D(registers[5]), .Q(registers_28__ap[5]), .QN(), .SE(dftIn), + .SI(registers_2__ap[6]) + ); + SDFF_X1_LVT \registers_reg[4][5] ( + .CK(n_0_34), .D(registers[5]), .Q(registers_4__ap[5]), .QN(), .SE(dftIn), + .SI(registers_3__ap[6]) + ); + AOI22_X1_LVT i_1_0_803( + .A1(registers_28__ap[5]), .A2(n_1_0_1283), .B1(n_1_0_1278), .B2(registers_4__ap[5]), + .ZN(n_1_0_765) + ); + SDFF_X1_LVT \registers_reg[10][5] ( + .CK(n_0_40), .D(registers[5]), .Q(registers_10__ap[5]), .QN(), .SE(dftIn), + .SI(registers_14__ap[6]) + ); + SDFF_X1_LVT \registers_reg[26][5] ( + .CK(n_0_56), .D(registers[5]), .Q(registers_26__ap[5]), .QN(), .SE(dftIn), + .SI(registers_28__ap[5]) + ); + SDFF_X1_LVT \registers_reg[8][5] ( + .CK(n_0_38), .D(registers[5]), .Q(registers_8__ap[5]), .QN(), .SE(dftIn), + .SI(registers_4__ap[5]) + ); + AOI222_X1_LVT i_1_0_802( + .A1(registers_10__ap[5]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[5]), + .C1(registers_8__ap[5]), .C2(n_1_0_1282), .ZN(n_1_0_764) + ); + SDFF_X1_LVT \registers_reg[9][5] ( + .CK(n_0_39), .D(registers[5]), .Q(registers_9__ap[5]), .QN(), .SE(dftIn), + .SI(registers_8__ap[5]) + ); + SDFF_X1_LVT \registers_reg[29][5] ( + .CK(n_0_59), .D(registers[5]), .Q(registers_29__ap[5]), .QN(), .SE(dftIn), + .SI(registers_26__ap[5]) + ); + AOI22_X1_LVT i_1_0_801( + .A1(registers_9__ap[5]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[5]), + .ZN(n_1_0_763) + ); + SDFF_X1_LVT \registers_reg[6][5] ( + .CK(n_0_36), .D(registers[5]), .Q(registers_6__ap[5]), .QN(), .SE(dftIn), + .SI(registers_9__ap[5]) + ); + SDFF_X1_LVT \registers_reg[1][5] ( + .CK(n_0_0), .D(registers[5]), .Q(registers_1__ap[5]), .QN(), .SE(dftIn), + .SI(registers_23__ap[6]) + ); + AOI22_X1_LVT i_1_0_800( + .A1(registers_6__ap[5]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[5]), + .ZN(n_1_0_762) + ); + SDFF_X1_LVT \registers_reg[16][5] ( + .CK(n_0_46), .D(registers[5]), .Q(registers_16__ap[5]), .QN(), .SE(dftIn), + .SI(registers_10__ap[5]) + ); + SDFF_X1_LVT \registers_reg[3][5] ( + .CK(n_0_33), .D(registers[5]), .Q(registers_3__ap[5]), .QN(), .SE(dftIn), + .SI(registers_6__ap[5]) + ); + AOI22_X1_LVT i_1_0_799( + .A1(registers_16__ap[5]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[5]), + .ZN(n_1_0_761) + ); + SDFF_X1_LVT \registers_reg[5][5] ( + .CK(n_0_35), .D(registers[5]), .Q(registers_5__ap[5]), .QN(), .SE(dftIn), + .SI(registers_3__ap[5]) + ); + SDFF_X1_LVT \registers_reg[31][5] ( + .CK(n_0_61), .D(registers[5]), .Q(registers_31__ap[5]), .QN(), .SE(dftIn), + .SI(registers_5__ap[5]) + ); + AOI22_X1_LVT i_1_0_798( + .A1(registers_5__ap[5]), .A2(n_1_0_1273), .B1(n_1_0_1266), .B2(registers_31__ap[5]), + .ZN(n_1_0_760) + ); + SDFF_X1_LVT \registers_reg[15][5] ( + .CK(n_0_45), .D(registers[5]), .Q(registers_15__ap[5]), .QN(), .SE(dftIn), + .SI(registers_16__ap[5]) + ); + SDFF_X1_LVT \registers_reg[23][5] ( + .CK(n_0_53), .D(registers[5]), .Q(registers_23__ap[5]), .QN(), .SE(dftIn), + .SI(registers_1__ap[5]) + ); + AOI22_X1_LVT i_1_0_797( + .A1(registers_15__ap[5]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[5]), + .ZN(n_1_0_759) + ); + NAND4_X1_LVT i_1_0_796( + .A1(n_1_0_762), .A2(n_1_0_761), .A3(n_1_0_760), .A4(n_1_0_759), .ZN(n_1_0_758) + ); + SDFF_X1_LVT \registers_reg[18][5] ( + .CK(n_0_48), .D(registers[5]), .Q(registers_18__ap[5]), .QN(), .SE(dftIn), + .SI(registers_23__ap[5]) + ); + SDFF_X1_LVT \registers_reg[30][5] ( + .CK(n_0_60), .D(registers[5]), .Q(registers_30__ap[5]), .QN(), .SE(dftIn), + .SI(registers_29__ap[5]) + ); + AOI22_X1_LVT i_1_0_795( + .A1(registers_18__ap[5]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[5]), + .ZN(n_1_0_757) + ); + SDFF_X1_LVT \registers_reg[24][5] ( + .CK(n_0_54), .D(registers[5]), .Q(registers_24__ap[5]), .QN(), .SE(dftIn), + .SI(registers_30__ap[5]) + ); + SDFF_X1_LVT \registers_reg[12][5] ( + .CK(n_0_42), .D(registers[5]), .Q(registers_12__ap[5]), .QN(), .SE(dftIn), + .SI(registers_15__ap[5]) + ); + AOI22_X1_LVT i_1_0_794( + .A1(registers_24__ap[5]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[5]), + .ZN(n_1_0_756) + ); + SDFF_X1_LVT \registers_reg[22][5] ( + .CK(n_0_52), .D(registers[5]), .Q(registers_22__ap[5]), .QN(), .SE(dftIn), + .SI(registers_18__ap[5]) + ); + SDFF_X1_LVT \registers_reg[21][5] ( + .CK(n_0_51), .D(registers[5]), .Q(registers_21__ap[5]), .QN(), .SE(dftIn), + .SI(registers_22__ap[5]) + ); + AOI22_X1_LVT i_1_0_793( + .A1(registers_22__ap[5]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[5]), + .ZN(n_1_0_755) + ); + SDFF_X1_LVT \registers_reg[20][5] ( + .CK(n_0_50), .D(registers[5]), .Q(registers_20__ap[5]), .QN(), .SE(dftIn), + .SI(registers_21__ap[5]) + ); + SDFF_X1_LVT \registers_reg[17][5] ( + .CK(n_0_47), .D(registers[5]), .Q(registers_17__ap[5]), .QN(), .SE(dftIn), + .SI(registers_20__ap[5]) + ); + AOI22_X1_LVT i_1_0_792( + .A1(registers_20__ap[5]), .A2(n_1_0_1281), .B1(n_1_0_1271), .B2(registers_17__ap[5]), + .ZN(n_1_0_754) + ); + NAND4_X1_LVT i_1_0_791( + .A1(n_1_0_757), .A2(n_1_0_756), .A3(n_1_0_755), .A4(n_1_0_754), .ZN(n_1_0_753) + ); + SDFF_X1_LVT \registers_reg[13][5] ( + .CK(n_0_43), .D(registers[5]), .Q(registers_13__ap[5]), .QN(), .SE(dftIn), + .SI(registers_12__ap[5]) + ); + SDFF_X1_LVT \registers_reg[25][5] ( + .CK(n_0_55), .D(registers[5]), .Q(registers_25__ap[5]), .QN(), .SE(dftIn), + .SI(registers_24__ap[5]) + ); + AOI22_X1_LVT i_1_0_790( + .A1(registers_13__ap[5]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[5]), + .ZN(n_1_0_752) + ); + SDFF_X1_LVT \registers_reg[19][5] ( + .CK(n_0_49), .D(registers[5]), .Q(registers_19__ap[5]), .QN(), .SE(dftIn), + .SI(registers_17__ap[5]) + ); + SDFF_X1_LVT \registers_reg[2][5] ( + .CK(n_0_32), .D(registers[5]), .Q(registers_2__ap[5]), .QN(), .SE(dftIn), + .SI(registers_25__ap[5]) + ); + AOI22_X1_LVT i_1_0_789( + .A1(registers_19__ap[5]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[5]), + .ZN(n_1_0_751) + ); + SDFF_X1_LVT \registers_reg[7][5] ( + .CK(n_0_37), .D(registers[5]), .Q(registers_7__ap[5]), .QN(), .SE(dftIn), + .SI(registers_31__ap[5]) + ); + SDFF_X1_LVT \registers_reg[14][5] ( + .CK(n_0_44), .D(registers[5]), .Q(registers_14__ap[5]), .QN(), .SE(dftIn), + .SI(registers_13__ap[5]) + ); + AOI22_X1_LVT i_1_0_788( + .A1(registers_7__ap[5]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[5]), + .ZN(n_1_0_750) + ); + SDFF_X1_LVT \registers_reg[27][5] ( + .CK(n_0_57), .D(registers[5]), .Q(registers_27__ap[5]), .QN(), .SE(dftIn), + .SI(registers_2__ap[5]) + ); + SDFF_X1_LVT \registers_reg[11][5] ( + .CK(n_0_41), .D(registers[5]), .Q(registers_11__ap[5]), .QN(), .SE(dftIn), + .SI(registers_14__ap[5]) + ); + AOI22_X1_LVT i_1_0_787( + .A1(registers_27__ap[5]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[5]), + .ZN(n_1_0_749) + ); + NAND4_X1_LVT i_1_0_786( + .A1(n_1_0_752), .A2(n_1_0_751), .A3(n_1_0_750), .A4(n_1_0_749), .ZN(n_1_0_748) + ); + NOR3_X1_LVT i_1_0_785( + .A1(n_1_0_758), .A2(n_1_0_753), .A3(n_1_0_748), .ZN(n_1_0_747) + ); + NAND4_X1_LVT i_1_0_784( + .A1(n_1_0_765), .A2(n_1_0_764), .A3(n_1_0_763), .A4(n_1_0_747), .ZN(RRs1[5]) + ); + AND2_X1_LVT i_0_0_4( + .A1(n_0_0_16), .A2(WRd[4]), .ZN(registers[4]) + ); + SDFF_X1_LVT \registers_reg[10][4] ( + .CK(n_0_40), .D(registers[4]), .Q(registers_10__ap[4]), .QN(), .SE(dftIn), + .SI(registers_11__ap[5]) + ); + SDFF_X1_LVT \registers_reg[21][4] ( + .CK(n_0_51), .D(registers[4]), .Q(registers_21__ap[4]), .QN(), .SE(dftIn), + .SI(registers_19__ap[5]) + ); + AOI22_X1_LVT i_1_0_783( + .A1(registers_10__ap[4]), .A2(n_1_0_1287), .B1(n_1_0_1259), .B2(registers_21__ap[4]), + .ZN(n_1_0_746) + ); + SDFF_X1_LVT \registers_reg[9][4] ( + .CK(n_0_39), .D(registers[4]), .Q(registers_9__ap[4]), .QN(), .SE(dftIn), + .SI(registers_7__ap[5]) + ); + SDFF_X1_LVT \registers_reg[1][4] ( + .CK(n_0_0), .D(registers[4]), .Q(registers_1__ap[4]), .QN(), .SE(dftIn), + .SI(registers_21__ap[4]) + ); + AOI22_X1_LVT i_1_0_778( + .A1(registers_9__ap[4]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[4]), + .ZN(n_1_0_741) + ); + SDFF_X1_LVT \registers_reg[18][4] ( + .CK(n_0_48), .D(registers[4]), .Q(registers_18__ap[4]), .QN(), .SE(dftIn), + .SI(registers_1__ap[4]) + ); + SDFF_X1_LVT \registers_reg[8][4] ( + .CK(n_0_38), .D(registers[4]), .Q(registers_8__ap[4]), .QN(), .SE(dftIn), + .SI(registers_9__ap[4]) + ); + AOI22_X1_LVT i_1_0_777( + .A1(registers_18__ap[4]), .A2(n_1_0_1297), .B1(n_1_0_1282), .B2(registers_8__ap[4]), + .ZN(n_1_0_740) + ); + NAND3_X1_LVT i_1_0_775( + .A1(n_1_0_746), .A2(n_1_0_741), .A3(n_1_0_740), .ZN(n_1_0_738) + ); + SDFF_X1_LVT \registers_reg[22][4] ( + .CK(n_0_52), .D(registers[4]), .Q(registers_22__ap[4]), .QN(), .SE(dftIn), + .SI(registers_18__ap[4]) + ); + SDFF_X1_LVT \registers_reg[23][4] ( + .CK(n_0_53), .D(registers[4]), .Q(registers_23__ap[4]), .QN(), .SE(dftIn), + .SI(registers_22__ap[4]) + ); + AOI221_X1_LVT i_1_0_774( + .A(n_1_0_738), .B1(n_1_0_1294), .B2(registers_22__ap[4]), .C1(registers_23__ap[4]), + .C2(n_1_0_1264), .ZN(n_1_0_737) + ); + SDFF_X1_LVT \registers_reg[28][4] ( + .CK(n_0_58), .D(registers[4]), .Q(registers_28__ap[4]), .QN(), .SE(dftIn), + .SI(registers_27__ap[5]) + ); + SDFF_X1_LVT \registers_reg[20][4] ( + .CK(n_0_50), .D(registers[4]), .Q(registers_20__ap[4]), .QN(), .SE(dftIn), + .SI(registers_23__ap[4]) + ); + AOI22_X1_LVT i_1_0_782( + .A1(registers_28__ap[4]), .A2(n_1_0_1283), .B1(n_1_0_1281), .B2(registers_20__ap[4]), + .ZN(n_1_0_745) + ); + SDFF_X1_LVT \registers_reg[19][4] ( + .CK(n_0_49), .D(registers[4]), .Q(registers_19__ap[4]), .QN(), .SE(dftIn), + .SI(registers_20__ap[4]) + ); + SDFF_X1_LVT \registers_reg[13][4] ( + .CK(n_0_43), .D(registers[4]), .Q(registers_13__ap[4]), .QN(), .SE(dftIn), + .SI(registers_10__ap[4]) + ); + AOI22_X1_LVT i_1_0_780( + .A1(registers_19__ap[4]), .A2(n_1_0_1295), .B1(n_1_0_1277), .B2(registers_13__ap[4]), + .ZN(n_1_0_743) + ); + SDFF_X1_LVT \registers_reg[26][4] ( + .CK(n_0_56), .D(registers[4]), .Q(registers_26__ap[4]), .QN(), .SE(dftIn), + .SI(registers_28__ap[4]) + ); + SDFF_X1_LVT \registers_reg[3][4] ( + .CK(n_0_33), .D(registers[4]), .Q(registers_3__ap[4]), .QN(), .SE(dftIn), + .SI(registers_8__ap[4]) + ); + AOI22_X1_LVT i_1_0_776( + .A1(registers_26__ap[4]), .A2(n_1_0_1285), .B1(n_1_0_1257), .B2(registers_3__ap[4]), + .ZN(n_1_0_739) + ); + NAND3_X1_LVT i_1_0_773( + .A1(n_1_0_745), .A2(n_1_0_743), .A3(n_1_0_739), .ZN(n_1_0_736) + ); + SDFF_X1_LVT \registers_reg[30][4] ( + .CK(n_0_60), .D(registers[4]), .Q(registers_30__ap[4]), .QN(), .SE(dftIn), + .SI(registers_26__ap[4]) + ); + SDFF_X1_LVT \registers_reg[31][4] ( + .CK(n_0_61), .D(registers[4]), .Q(registers_31__ap[4]), .QN(), .SE(dftIn), + .SI(registers_3__ap[4]) + ); + AOI221_X1_LVT i_1_0_772( + .A(n_1_0_736), .B1(n_1_0_1272), .B2(registers_30__ap[4]), .C1(registers_31__ap[4]), + .C2(n_1_0_1266), .ZN(n_1_0_735) + ); + SDFF_X1_LVT \registers_reg[24][4] ( + .CK(n_0_54), .D(registers[4]), .Q(registers_24__ap[4]), .QN(), .SE(dftIn), + .SI(registers_30__ap[4]) + ); + SDFF_X1_LVT \registers_reg[12][4] ( + .CK(n_0_42), .D(registers[4]), .Q(registers_12__ap[4]), .QN(), .SE(dftIn), + .SI(registers_13__ap[4]) + ); + AOI22_X1_LVT i_1_0_781( + .A1(registers_24__ap[4]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[4]), + .ZN(n_1_0_744) + ); + SDFF_X1_LVT \registers_reg[27][4] ( + .CK(n_0_57), .D(registers[4]), .Q(registers_27__ap[4]), .QN(), .SE(dftIn), + .SI(registers_24__ap[4]) + ); + SDFF_X1_LVT \registers_reg[11][4] ( + .CK(n_0_41), .D(registers[4]), .Q(registers_11__ap[4]), .QN(), .SE(dftIn), + .SI(registers_12__ap[4]) + ); + AOI22_X1_LVT i_1_0_779( + .A1(registers_27__ap[4]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[4]), + .ZN(n_1_0_742) + ); + SDFF_X1_LVT \registers_reg[17][4] ( + .CK(n_0_47), .D(registers[4]), .Q(registers_17__ap[4]), .QN(), .SE(dftIn), + .SI(registers_19__ap[4]) + ); + SDFF_X1_LVT \registers_reg[7][4] ( + .CK(n_0_37), .D(registers[4]), .Q(registers_7__ap[4]), .QN(), .SE(dftIn), + .SI(registers_31__ap[4]) + ); + SDFF_X1_LVT \registers_reg[14][4] ( + .CK(n_0_44), .D(registers[4]), .Q(registers_14__ap[4]), .QN(), .SE(dftIn), + .SI(registers_11__ap[4]) + ); + AOI222_X1_LVT i_1_0_771( + .A1(registers_17__ap[4]), .A2(n_1_0_1271), .B1(n_1_0_1263), .B2(registers_7__ap[4]), + .C1(n_1_0_1258), .C2(registers_14__ap[4]), .ZN(n_1_0_734) + ); + SDFF_X1_LVT \registers_reg[15][4] ( + .CK(n_0_45), .D(registers[4]), .Q(registers_15__ap[4]), .QN(), .SE(dftIn), + .SI(registers_14__ap[4]) + ); + SDFF_X1_LVT \registers_reg[16][4] ( + .CK(n_0_46), .D(registers[4]), .Q(registers_16__ap[4]), .QN(), .SE(dftIn), + .SI(registers_15__ap[4]) + ); + AOI22_X1_LVT i_1_0_770( + .A1(registers_15__ap[4]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[4]), + .ZN(n_1_0_733) + ); + SDFF_X1_LVT \registers_reg[4][4] ( + .CK(n_0_34), .D(registers[4]), .Q(registers_4__ap[4]), .QN(), .SE(dftIn), + .SI(registers_7__ap[4]) + ); + SDFF_X1_LVT \registers_reg[25][4] ( + .CK(n_0_55), .D(registers[4]), .Q(registers_25__ap[4]), .QN(), .SE(dftIn), + .SI(registers_27__ap[4]) + ); + AOI22_X1_LVT i_1_0_769( + .A1(registers_4__ap[4]), .A2(n_1_0_1278), .B1(n_1_0_1269), .B2(registers_25__ap[4]), + .ZN(n_1_0_732) + ); + SDFF_X1_LVT \registers_reg[29][4] ( + .CK(n_0_59), .D(registers[4]), .Q(registers_29__ap[4]), .QN(), .SE(dftIn), + .SI(registers_25__ap[4]) + ); + SDFF_X1_LVT \registers_reg[2][4] ( + .CK(n_0_32), .D(registers[4]), .Q(registers_2__ap[4]), .QN(), .SE(dftIn), + .SI(registers_29__ap[4]) + ); + AOI22_X1_LVT i_1_0_768( + .A1(registers_29__ap[4]), .A2(n_1_0_1276), .B1(n_1_0_1268), .B2(registers_2__ap[4]), + .ZN(n_1_0_731) + ); + NAND3_X1_LVT i_1_0_767( + .A1(n_1_0_733), .A2(n_1_0_732), .A3(n_1_0_731), .ZN(n_1_0_730) + ); + SDFF_X1_LVT \registers_reg[6][4] ( + .CK(n_0_36), .D(registers[4]), .Q(registers_6__ap[4]), .QN(), .SE(dftIn), + .SI(registers_4__ap[4]) + ); + SDFF_X1_LVT \registers_reg[5][4] ( + .CK(n_0_35), .D(registers[4]), .Q(registers_5__ap[4]), .QN(), .SE(dftIn), + .SI(registers_6__ap[4]) + ); + AOI221_X1_LVT i_1_0_766( + .A(n_1_0_730), .B1(n_1_0_1300), .B2(registers_6__ap[4]), .C1(registers_5__ap[4]), + .C2(n_1_0_1273), .ZN(n_1_0_729) + ); + AND4_X1_LVT i_1_0_765( + .A1(n_1_0_744), .A2(n_1_0_742), .A3(n_1_0_734), .A4(n_1_0_729), .ZN(n_1_0_728) + ); + NAND3_X1_LVT i_1_0_764( + .A1(n_1_0_737), .A2(n_1_0_735), .A3(n_1_0_728), .ZN(RRs1[4]) + ); + AND2_X1_LVT i_0_0_3( + .A1(n_0_0_16), .A2(WRd[3]), .ZN(registers[3]) + ); + SDFF_X1_LVT \registers_reg[28][3] ( + .CK(n_0_58), .D(registers[3]), .Q(registers_28__ap[3]), .QN(), .SE(dftIn), + .SI(registers_2__ap[4]) + ); + SDFF_X1_LVT \registers_reg[17][3] ( + .CK(n_0_47), .D(registers[3]), .Q(registers_17__ap[3]), .QN(), .SE(dftIn), + .SI(registers_17__ap[4]) + ); + AOI22_X1_LVT i_1_0_763( + .A1(registers_28__ap[3]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[3]), + .ZN(n_1_0_727) + ); + SDFF_X1_LVT \registers_reg[10][3] ( + .CK(n_0_40), .D(registers[3]), .Q(registers_10__ap[3]), .QN(), .SE(dftIn), + .SI(registers_16__ap[4]) + ); + SDFF_X1_LVT \registers_reg[26][3] ( + .CK(n_0_56), .D(registers[3]), .Q(registers_26__ap[3]), .QN(), .SE(dftIn), + .SI(registers_28__ap[3]) + ); + SDFF_X1_LVT \registers_reg[8][3] ( + .CK(n_0_38), .D(registers[3]), .Q(registers_8__ap[3]), .QN(), .SE(dftIn), + .SI(registers_5__ap[4]) + ); + AOI222_X1_LVT i_1_0_762( + .A1(registers_10__ap[3]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[3]), + .C1(registers_8__ap[3]), .C2(n_1_0_1282), .ZN(n_1_0_726) + ); + SDFF_X1_LVT \registers_reg[9][3] ( + .CK(n_0_39), .D(registers[3]), .Q(registers_9__ap[3]), .QN(), .SE(dftIn), + .SI(registers_8__ap[3]) + ); + SDFF_X1_LVT \registers_reg[29][3] ( + .CK(n_0_59), .D(registers[3]), .Q(registers_29__ap[3]), .QN(), .SE(dftIn), + .SI(registers_26__ap[3]) + ); + AOI22_X1_LVT i_1_0_761( + .A1(registers_9__ap[3]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[3]), + .ZN(n_1_0_725) + ); + SDFF_X1_LVT \registers_reg[6][3] ( + .CK(n_0_36), .D(registers[3]), .Q(registers_6__ap[3]), .QN(), .SE(dftIn), + .SI(registers_9__ap[3]) + ); + SDFF_X1_LVT \registers_reg[1][3] ( + .CK(n_0_0), .D(registers[3]), .Q(registers_1__ap[3]), .QN(), .SE(dftIn), + .SI(registers_17__ap[3]) + ); + AOI22_X1_LVT i_1_0_760( + .A1(registers_6__ap[3]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[3]), + .ZN(n_1_0_724) + ); + SDFF_X1_LVT \registers_reg[16][3] ( + .CK(n_0_46), .D(registers[3]), .Q(registers_16__ap[3]), .QN(), .SE(dftIn), + .SI(registers_10__ap[3]) + ); + SDFF_X1_LVT \registers_reg[3][3] ( + .CK(n_0_33), .D(registers[3]), .Q(registers_3__ap[3]), .QN(), .SE(dftIn), + .SI(registers_6__ap[3]) + ); + AOI22_X1_LVT i_1_0_759( + .A1(registers_16__ap[3]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[3]), + .ZN(n_1_0_723) + ); + SDFF_X1_LVT \registers_reg[5][3] ( + .CK(n_0_35), .D(registers[3]), .Q(registers_5__ap[3]), .QN(), .SE(dftIn), + .SI(registers_3__ap[3]) + ); + SDFF_X1_LVT \registers_reg[31][3] ( + .CK(n_0_61), .D(registers[3]), .Q(registers_31__ap[3]), .QN(), .SE(dftIn), + .SI(registers_5__ap[3]) + ); + AOI22_X1_LVT i_1_0_758( + .A1(registers_5__ap[3]), .A2(n_1_0_1273), .B1(n_1_0_1266), .B2(registers_31__ap[3]), + .ZN(n_1_0_722) + ); + SDFF_X1_LVT \registers_reg[15][3] ( + .CK(n_0_45), .D(registers[3]), .Q(registers_15__ap[3]), .QN(), .SE(dftIn), + .SI(registers_16__ap[3]) + ); + SDFF_X1_LVT \registers_reg[23][3] ( + .CK(n_0_53), .D(registers[3]), .Q(registers_23__ap[3]), .QN(), .SE(dftIn), + .SI(registers_1__ap[3]) + ); + AOI22_X1_LVT i_1_0_757( + .A1(registers_15__ap[3]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[3]), + .ZN(n_1_0_721) + ); + NAND4_X1_LVT i_1_0_756( + .A1(n_1_0_724), .A2(n_1_0_723), .A3(n_1_0_722), .A4(n_1_0_721), .ZN(n_1_0_720) + ); + SDFF_X1_LVT \registers_reg[18][3] ( + .CK(n_0_48), .D(registers[3]), .Q(registers_18__ap[3]), .QN(), .SE(dftIn), + .SI(registers_23__ap[3]) + ); + SDFF_X1_LVT \registers_reg[30][3] ( + .CK(n_0_60), .D(registers[3]), .Q(registers_30__ap[3]), .QN(), .SE(dftIn), + .SI(registers_29__ap[3]) + ); + AOI22_X1_LVT i_1_0_755( + .A1(registers_18__ap[3]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[3]), + .ZN(n_1_0_719) + ); + SDFF_X1_LVT \registers_reg[20][3] ( + .CK(n_0_50), .D(registers[3]), .Q(registers_20__ap[3]), .QN(), .SE(dftIn), + .SI(registers_18__ap[3]) + ); + SDFF_X1_LVT \registers_reg[4][3] ( + .CK(n_0_34), .D(registers[3]), .Q(registers_4__ap[3]), .QN(), .SE(dftIn), + .SI(registers_31__ap[3]) + ); + AOI22_X1_LVT i_1_0_754( + .A1(registers_20__ap[3]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[3]), + .ZN(n_1_0_718) + ); + SDFF_X1_LVT \registers_reg[22][3] ( + .CK(n_0_52), .D(registers[3]), .Q(registers_22__ap[3]), .QN(), .SE(dftIn), + .SI(registers_20__ap[3]) + ); + SDFF_X1_LVT \registers_reg[21][3] ( + .CK(n_0_51), .D(registers[3]), .Q(registers_21__ap[3]), .QN(), .SE(dftIn), + .SI(registers_22__ap[3]) + ); + AOI22_X1_LVT i_1_0_753( + .A1(registers_22__ap[3]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[3]), + .ZN(n_1_0_717) + ); + SDFF_X1_LVT \registers_reg[24][3] ( + .CK(n_0_54), .D(registers[3]), .Q(registers_24__ap[3]), .QN(), .SE(dftIn), + .SI(registers_30__ap[3]) + ); + SDFF_X1_LVT \registers_reg[12][3] ( + .CK(n_0_42), .D(registers[3]), .Q(registers_12__ap[3]), .QN(), .SE(dftIn), + .SI(registers_15__ap[3]) + ); + AOI22_X1_LVT i_1_0_752( + .A1(registers_24__ap[3]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[3]), + .ZN(n_1_0_716) + ); + NAND4_X1_LVT i_1_0_751( + .A1(n_1_0_719), .A2(n_1_0_718), .A3(n_1_0_717), .A4(n_1_0_716), .ZN(n_1_0_715) + ); + SDFF_X1_LVT \registers_reg[13][3] ( + .CK(n_0_43), .D(registers[3]), .Q(registers_13__ap[3]), .QN(), .SE(dftIn), + .SI(registers_12__ap[3]) + ); + SDFF_X1_LVT \registers_reg[25][3] ( + .CK(n_0_55), .D(registers[3]), .Q(registers_25__ap[3]), .QN(), .SE(dftIn), + .SI(registers_24__ap[3]) + ); + AOI22_X1_LVT i_1_0_750( + .A1(registers_13__ap[3]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[3]), + .ZN(n_1_0_714) + ); + SDFF_X1_LVT \registers_reg[19][3] ( + .CK(n_0_49), .D(registers[3]), .Q(registers_19__ap[3]), .QN(), .SE(dftIn), + .SI(registers_21__ap[3]) + ); + SDFF_X1_LVT \registers_reg[2][3] ( + .CK(n_0_32), .D(registers[3]), .Q(registers_2__ap[3]), .QN(), .SE(dftIn), + .SI(registers_25__ap[3]) + ); + AOI22_X1_LVT i_1_0_749( + .A1(registers_19__ap[3]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[3]), + .ZN(n_1_0_713) + ); + SDFF_X1_LVT \registers_reg[7][3] ( + .CK(n_0_37), .D(registers[3]), .Q(registers_7__ap[3]), .QN(), .SE(dftIn), + .SI(registers_4__ap[3]) + ); + SDFF_X1_LVT \registers_reg[14][3] ( + .CK(n_0_44), .D(registers[3]), .Q(registers_14__ap[3]), .QN(), .SE(dftIn), + .SI(registers_13__ap[3]) + ); + AOI22_X1_LVT i_1_0_748( + .A1(registers_7__ap[3]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[3]), + .ZN(n_1_0_712) + ); + SDFF_X1_LVT \registers_reg[27][3] ( + .CK(n_0_57), .D(registers[3]), .Q(registers_27__ap[3]), .QN(), .SE(dftIn), + .SI(registers_2__ap[3]) + ); + SDFF_X1_LVT \registers_reg[11][3] ( + .CK(n_0_41), .D(registers[3]), .Q(registers_11__ap[3]), .QN(), .SE(dftIn), + .SI(registers_14__ap[3]) + ); + AOI22_X1_LVT i_1_0_747( + .A1(registers_27__ap[3]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[3]), + .ZN(n_1_0_711) + ); + NAND4_X1_LVT i_1_0_746( + .A1(n_1_0_714), .A2(n_1_0_713), .A3(n_1_0_712), .A4(n_1_0_711), .ZN(n_1_0_710) + ); + NOR3_X1_LVT i_1_0_745( + .A1(n_1_0_720), .A2(n_1_0_715), .A3(n_1_0_710), .ZN(n_1_0_709) + ); + NAND4_X1_LVT i_1_0_744( + .A1(n_1_0_727), .A2(n_1_0_726), .A3(n_1_0_725), .A4(n_1_0_709), .ZN(RRs1[3]) + ); + AND2_X1_LVT i_0_0_2( + .A1(n_0_0_16), .A2(WRd[2]), .ZN(registers[2]) + ); + SDFF_X1_LVT \registers_reg[28][2] ( + .CK(n_0_58), .D(registers[2]), .Q(registers_28__ap[2]), .QN(), .SE(dftIn), + .SI(registers_27__ap[3]) + ); + SDFF_X1_LVT \registers_reg[4][2] ( + .CK(n_0_34), .D(registers[2]), .Q(registers_4__ap[2]), .QN(), .SE(dftIn), + .SI(registers_7__ap[3]) + ); + AOI22_X1_LVT i_1_0_740( + .A1(registers_28__ap[2]), .A2(n_1_0_1283), .B1(n_1_0_1278), .B2(registers_4__ap[2]), + .ZN(n_1_0_705) + ); + SDFF_X1_LVT \registers_reg[16][2] ( + .CK(n_0_46), .D(registers[2]), .Q(registers_16__ap[2]), .QN(), .SE(dftIn), + .SI(registers_11__ap[3]) + ); + SDFF_X1_LVT \registers_reg[31][2] ( + .CK(n_0_61), .D(registers[2]), .Q(registers_31__ap[2]), .QN(), .SE(dftIn), + .SI(registers_4__ap[2]) + ); + AOI22_X1_LVT i_1_0_743( + .A1(registers_16__ap[2]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[2]), + .ZN(n_1_0_708) + ); + SDFF_X1_LVT \registers_reg[6][2] ( + .CK(n_0_36), .D(registers[2]), .Q(registers_6__ap[2]), .QN(), .SE(dftIn), + .SI(registers_31__ap[2]) + ); + SDFF_X1_LVT \registers_reg[1][2] ( + .CK(n_0_0), .D(registers[2]), .Q(registers_1__ap[2]), .QN(), .SE(dftIn), + .SI(registers_19__ap[3]) + ); + AOI22_X1_LVT i_1_0_739( + .A1(registers_6__ap[2]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[2]), + .ZN(n_1_0_704) + ); + SDFF_X1_LVT \registers_reg[15][2] ( + .CK(n_0_45), .D(registers[2]), .Q(registers_15__ap[2]), .QN(), .SE(dftIn), + .SI(registers_16__ap[2]) + ); + SDFF_X1_LVT \registers_reg[27][2] ( + .CK(n_0_57), .D(registers[2]), .Q(registers_27__ap[2]), .QN(), .SE(dftIn), + .SI(registers_28__ap[2]) + ); + AOI22_X1_LVT i_1_0_742( + .A1(registers_15__ap[2]), .A2(n_1_0_1286), .B1(n_1_0_1279), .B2(registers_27__ap[2]), + .ZN(n_1_0_707) + ); + INV_X1_LVT i_1_0_741( + .A(n_1_0_707), .ZN(n_1_0_706) + ); + SDFF_X1_LVT \registers_reg[11][2] ( + .CK(n_0_41), .D(registers[2]), .Q(registers_11__ap[2]), .QN(), .SE(dftIn), + .SI(registers_15__ap[2]) + ); + SDFF_X1_LVT \registers_reg[5][2] ( + .CK(n_0_35), .D(registers[2]), .Q(registers_5__ap[2]), .QN(), .SE(dftIn), + .SI(registers_6__ap[2]) + ); + AOI221_X1_LVT i_1_0_738( + .A(n_1_0_706), .B1(n_1_0_1270), .B2(registers_11__ap[2]), .C1(registers_5__ap[2]), + .C2(n_1_0_1273), .ZN(n_1_0_703) + ); + SDFF_X1_LVT \registers_reg[10][2] ( + .CK(n_0_40), .D(registers[2]), .Q(registers_10__ap[2]), .QN(), .SE(dftIn), + .SI(registers_11__ap[2]) + ); + SDFF_X1_LVT \registers_reg[30][2] ( + .CK(n_0_60), .D(registers[2]), .Q(registers_30__ap[2]), .QN(), .SE(dftIn), + .SI(registers_27__ap[2]) + ); + SDFF_X1_LVT \registers_reg[8][2] ( + .CK(n_0_38), .D(registers[2]), .Q(registers_8__ap[2]), .QN(), .SE(dftIn), + .SI(registers_5__ap[2]) + ); + AOI222_X1_LVT i_1_0_737( + .A1(registers_10__ap[2]), .A2(n_1_0_1287), .B1(n_1_0_1272), .B2(registers_30__ap[2]), + .C1(n_1_0_1282), .C2(registers_8__ap[2]), .ZN(n_1_0_702) + ); + NAND4_X1_LVT i_1_0_736( + .A1(n_1_0_708), .A2(n_1_0_704), .A3(n_1_0_703), .A4(n_1_0_702), .ZN(n_1_0_701) + ); + SDFF_X1_LVT \registers_reg[9][2] ( + .CK(n_0_39), .D(registers[2]), .Q(registers_9__ap[2]), .QN(), .SE(dftIn), + .SI(registers_8__ap[2]) + ); + SDFF_X1_LVT \registers_reg[29][2] ( + .CK(n_0_59), .D(registers[2]), .Q(registers_29__ap[2]), .QN(), .SE(dftIn), + .SI(registers_30__ap[2]) + ); + AOI221_X1_LVT i_1_0_735( + .A(n_1_0_701), .B1(n_1_0_1291), .B2(registers_9__ap[2]), .C1(registers_29__ap[2]), + .C2(n_1_0_1276), .ZN(n_1_0_700) + ); + SDFF_X1_LVT \registers_reg[18][2] ( + .CK(n_0_48), .D(registers[2]), .Q(registers_18__ap[2]), .QN(), .SE(dftIn), + .SI(registers_1__ap[2]) + ); + SDFF_X1_LVT \registers_reg[26][2] ( + .CK(n_0_56), .D(registers[2]), .Q(registers_26__ap[2]), .QN(), .SE(dftIn), + .SI(registers_29__ap[2]) + ); + AOI22_X1_LVT i_1_0_734( + .A1(registers_18__ap[2]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[2]), + .ZN(n_1_0_699) + ); + SDFF_X1_LVT \registers_reg[24][2] ( + .CK(n_0_54), .D(registers[2]), .Q(registers_24__ap[2]), .QN(), .SE(dftIn), + .SI(registers_26__ap[2]) + ); + SDFF_X1_LVT \registers_reg[12][2] ( + .CK(n_0_42), .D(registers[2]), .Q(registers_12__ap[2]), .QN(), .SE(dftIn), + .SI(registers_10__ap[2]) + ); + AOI22_X1_LVT i_1_0_733( + .A1(registers_24__ap[2]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[2]), + .ZN(n_1_0_698) + ); + SDFF_X1_LVT \registers_reg[22][2] ( + .CK(n_0_52), .D(registers[2]), .Q(registers_22__ap[2]), .QN(), .SE(dftIn), + .SI(registers_18__ap[2]) + ); + SDFF_X1_LVT \registers_reg[21][2] ( + .CK(n_0_51), .D(registers[2]), .Q(registers_21__ap[2]), .QN(), .SE(dftIn), + .SI(registers_22__ap[2]) + ); + AOI22_X1_LVT i_1_0_732( + .A1(registers_22__ap[2]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[2]), + .ZN(n_1_0_697) + ); + NAND3_X1_LVT i_1_0_731( + .A1(n_1_0_699), .A2(n_1_0_698), .A3(n_1_0_697), .ZN(n_1_0_696) + ); + SDFF_X1_LVT \registers_reg[17][2] ( + .CK(n_0_47), .D(registers[2]), .Q(registers_17__ap[2]), .QN(), .SE(dftIn), + .SI(registers_21__ap[2]) + ); + SDFF_X1_LVT \registers_reg[20][2] ( + .CK(n_0_50), .D(registers[2]), .Q(registers_20__ap[2]), .QN(), .SE(dftIn), + .SI(registers_17__ap[2]) + ); + AOI221_X1_LVT i_1_0_730( + .A(n_1_0_696), .B1(n_1_0_1271), .B2(registers_17__ap[2]), .C1(registers_20__ap[2]), + .C2(n_1_0_1281), .ZN(n_1_0_695) + ); + SDFF_X1_LVT \registers_reg[13][2] ( + .CK(n_0_43), .D(registers[2]), .Q(registers_13__ap[2]), .QN(), .SE(dftIn), + .SI(registers_12__ap[2]) + ); + SDFF_X1_LVT \registers_reg[25][2] ( + .CK(n_0_55), .D(registers[2]), .Q(registers_25__ap[2]), .QN(), .SE(dftIn), + .SI(registers_24__ap[2]) + ); + AOI22_X1_LVT i_1_0_729( + .A1(registers_13__ap[2]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[2]), + .ZN(n_1_0_694) + ); + SDFF_X1_LVT \registers_reg[7][2] ( + .CK(n_0_37), .D(registers[2]), .Q(registers_7__ap[2]), .QN(), .SE(dftIn), + .SI(registers_9__ap[2]) + ); + SDFF_X1_LVT \registers_reg[14][2] ( + .CK(n_0_44), .D(registers[2]), .Q(registers_14__ap[2]), .QN(), .SE(dftIn), + .SI(registers_13__ap[2]) + ); + AOI22_X1_LVT i_1_0_728( + .A1(registers_7__ap[2]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[2]), + .ZN(n_1_0_693) + ); + SDFF_X1_LVT \registers_reg[19][2] ( + .CK(n_0_49), .D(registers[2]), .Q(registers_19__ap[2]), .QN(), .SE(dftIn), + .SI(registers_20__ap[2]) + ); + SDFF_X1_LVT \registers_reg[3][2] ( + .CK(n_0_33), .D(registers[2]), .Q(registers_3__ap[2]), .QN(), .SE(dftIn), + .SI(registers_7__ap[2]) + ); + AOI22_X1_LVT i_1_0_727( + .A1(registers_19__ap[2]), .A2(n_1_0_1295), .B1(n_1_0_1257), .B2(registers_3__ap[2]), + .ZN(n_1_0_692) + ); + NAND3_X1_LVT i_1_0_726( + .A1(n_1_0_694), .A2(n_1_0_693), .A3(n_1_0_692), .ZN(n_1_0_691) + ); + SDFF_X1_LVT \registers_reg[23][2] ( + .CK(n_0_53), .D(registers[2]), .Q(registers_23__ap[2]), .QN(), .SE(dftIn), + .SI(registers_19__ap[2]) + ); + SDFF_X1_LVT \registers_reg[2][2] ( + .CK(n_0_32), .D(registers[2]), .Q(registers_2__ap[2]), .QN(), .SE(dftIn), + .SI(registers_25__ap[2]) + ); + AOI221_X1_LVT i_1_0_725( + .A(n_1_0_691), .B1(n_1_0_1264), .B2(registers_23__ap[2]), .C1(registers_2__ap[2]), + .C2(n_1_0_1268), .ZN(n_1_0_690) + ); + NAND4_X1_LVT i_1_0_724( + .A1(n_1_0_705), .A2(n_1_0_700), .A3(n_1_0_695), .A4(n_1_0_690), .ZN(RRs1[2]) + ); + AND2_X1_LVT i_0_0_1( + .A1(n_0_0_16), .A2(WRd[1]), .ZN(registers[1]) + ); + SDFF_X1_LVT \registers_reg[13][1] ( + .CK(n_0_43), .D(registers[1]), .Q(registers_13__ap[1]), .QN(), .SE(dftIn), + .SI(registers_14__ap[2]) + ); + SDFF_X1_LVT \registers_reg[21][1] ( + .CK(n_0_51), .D(registers[1]), .Q(registers_21__ap[1]), .QN(), .SE(dftIn), + .SI(registers_23__ap[2]) + ); + AOI22_X1_LVT i_1_0_720( + .A1(registers_13__ap[1]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[1]), + .ZN(n_1_0_686) + ); + SDFF_X1_LVT \registers_reg[29][1] ( + .CK(n_0_59), .D(registers[1]), .Q(registers_29__ap[1]), .QN(), .SE(dftIn), + .SI(registers_2__ap[2]) + ); + SDFF_X1_LVT \registers_reg[23][1] ( + .CK(n_0_53), .D(registers[1]), .Q(registers_23__ap[1]), .QN(), .SE(dftIn), + .SI(registers_21__ap[1]) + ); + AOI22_X1_LVT i_1_0_723( + .A1(registers_29__ap[1]), .A2(n_1_0_1276), .B1(n_1_0_1264), .B2(registers_23__ap[1]), + .ZN(n_1_0_689) + ); + SDFF_X1_LVT \registers_reg[24][1] ( + .CK(n_0_54), .D(registers[1]), .Q(registers_24__ap[1]), .QN(), .SE(dftIn), + .SI(registers_29__ap[1]) + ); + SDFF_X1_LVT \registers_reg[20][1] ( + .CK(n_0_50), .D(registers[1]), .Q(registers_20__ap[1]), .QN(), .SE(dftIn), + .SI(registers_23__ap[1]) + ); + AOI22_X1_LVT i_1_0_719( + .A1(registers_24__ap[1]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[1]), + .ZN(n_1_0_685) + ); + SDFF_X1_LVT \registers_reg[7][1] ( + .CK(n_0_37), .D(registers[1]), .Q(registers_7__ap[1]), .QN(), .SE(dftIn), + .SI(registers_3__ap[2]) + ); + SDFF_X1_LVT \registers_reg[3][1] ( + .CK(n_0_33), .D(registers[1]), .Q(registers_3__ap[1]), .QN(), .SE(dftIn), + .SI(registers_7__ap[1]) + ); + AOI22_X1_LVT i_1_0_722( + .A1(registers_7__ap[1]), .A2(n_1_0_1263), .B1(n_1_0_1257), .B2(registers_3__ap[1]), + .ZN(n_1_0_688) + ); + INV_X1_LVT i_1_0_721( + .A(n_1_0_688), .ZN(n_1_0_687) + ); + SDFF_X1_LVT \registers_reg[31][1] ( + .CK(n_0_61), .D(registers[1]), .Q(registers_31__ap[1]), .QN(), .SE(dftIn), + .SI(registers_3__ap[1]) + ); + SDFF_X1_LVT \registers_reg[4][1] ( + .CK(n_0_34), .D(registers[1]), .Q(registers_4__ap[1]), .QN(), .SE(dftIn), + .SI(registers_31__ap[1]) + ); + AOI221_X1_LVT i_1_0_718( + .A(n_1_0_687), .B1(n_1_0_1266), .B2(registers_31__ap[1]), .C1(registers_4__ap[1]), + .C2(n_1_0_1278), .ZN(n_1_0_684) + ); + SDFF_X1_LVT \registers_reg[10][1] ( + .CK(n_0_40), .D(registers[1]), .Q(registers_10__ap[1]), .QN(), .SE(dftIn), + .SI(registers_13__ap[1]) + ); + SDFF_X1_LVT \registers_reg[26][1] ( + .CK(n_0_56), .D(registers[1]), .Q(registers_26__ap[1]), .QN(), .SE(dftIn), + .SI(registers_24__ap[1]) + ); + SDFF_X1_LVT \registers_reg[25][1] ( + .CK(n_0_55), .D(registers[1]), .Q(registers_25__ap[1]), .QN(), .SE(dftIn), + .SI(registers_26__ap[1]) + ); + AOI222_X1_LVT i_1_0_717( + .A1(registers_10__ap[1]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[1]), + .C1(registers_25__ap[1]), .C2(n_1_0_1269), .ZN(n_1_0_683) + ); + NAND4_X1_LVT i_1_0_716( + .A1(n_1_0_689), .A2(n_1_0_685), .A3(n_1_0_684), .A4(n_1_0_683), .ZN(n_1_0_682) + ); + SDFF_X1_LVT \registers_reg[8][1] ( + .CK(n_0_38), .D(registers[1]), .Q(registers_8__ap[1]), .QN(), .SE(dftIn), + .SI(registers_4__ap[1]) + ); + SDFF_X1_LVT \registers_reg[28][1] ( + .CK(n_0_58), .D(registers[1]), .Q(registers_28__ap[1]), .QN(), .SE(dftIn), + .SI(registers_25__ap[1]) + ); + AOI221_X1_LVT i_1_0_715( + .A(n_1_0_682), .B1(n_1_0_1282), .B2(registers_8__ap[1]), .C1(registers_28__ap[1]), + .C2(n_1_0_1283), .ZN(n_1_0_681) + ); + SDFF_X1_LVT \registers_reg[18][1] ( + .CK(n_0_48), .D(registers[1]), .Q(registers_18__ap[1]), .QN(), .SE(dftIn), + .SI(registers_20__ap[1]) + ); + SDFF_X1_LVT \registers_reg[30][1] ( + .CK(n_0_60), .D(registers[1]), .Q(registers_30__ap[1]), .QN(), .SE(dftIn), + .SI(registers_28__ap[1]) + ); + AOI22_X1_LVT i_1_0_714( + .A1(registers_18__ap[1]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[1]), + .ZN(n_1_0_680) + ); + SDFF_X1_LVT \registers_reg[17][1] ( + .CK(n_0_47), .D(registers[1]), .Q(registers_17__ap[1]), .QN(), .SE(dftIn), + .SI(registers_18__ap[1]) + ); + SDFF_X1_LVT \registers_reg[12][1] ( + .CK(n_0_42), .D(registers[1]), .Q(registers_12__ap[1]), .QN(), .SE(dftIn), + .SI(registers_10__ap[1]) + ); + AOI22_X1_LVT i_1_0_713( + .A1(registers_17__ap[1]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[1]), + .ZN(n_1_0_679) + ); + SDFF_X1_LVT \registers_reg[15][1] ( + .CK(n_0_45), .D(registers[1]), .Q(registers_15__ap[1]), .QN(), .SE(dftIn), + .SI(registers_12__ap[1]) + ); + SDFF_X1_LVT \registers_reg[5][1] ( + .CK(n_0_35), .D(registers[1]), .Q(registers_5__ap[1]), .QN(), .SE(dftIn), + .SI(registers_8__ap[1]) + ); + AOI22_X1_LVT i_1_0_712( + .A1(registers_15__ap[1]), .A2(n_1_0_1286), .B1(n_1_0_1273), .B2(registers_5__ap[1]), + .ZN(n_1_0_678) + ); + NAND3_X1_LVT i_1_0_711( + .A1(n_1_0_680), .A2(n_1_0_679), .A3(n_1_0_678), .ZN(n_1_0_677) + ); + SDFF_X1_LVT \registers_reg[22][1] ( + .CK(n_0_52), .D(registers[1]), .Q(registers_22__ap[1]), .QN(), .SE(dftIn), + .SI(registers_17__ap[1]) + ); + SDFF_X1_LVT \registers_reg[16][1] ( + .CK(n_0_46), .D(registers[1]), .Q(registers_16__ap[1]), .QN(), .SE(dftIn), + .SI(registers_15__ap[1]) + ); + AOI221_X1_LVT i_1_0_710( + .A(n_1_0_677), .B1(n_1_0_1294), .B2(registers_22__ap[1]), .C1(registers_16__ap[1]), + .C2(n_1_0_1267), .ZN(n_1_0_676) + ); + SDFF_X1_LVT \registers_reg[9][1] ( + .CK(n_0_39), .D(registers[1]), .Q(registers_9__ap[1]), .QN(), .SE(dftIn), + .SI(registers_5__ap[1]) + ); + SDFF_X1_LVT \registers_reg[1][1] ( + .CK(n_0_0), .D(registers[1]), .Q(registers_1__ap[1]), .QN(), .SE(dftIn), + .SI(registers_22__ap[1]) + ); + AOI22_X1_LVT i_1_0_709( + .A1(registers_9__ap[1]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[1]), + .ZN(n_1_0_675) + ); + SDFF_X1_LVT \registers_reg[6][1] ( + .CK(n_0_36), .D(registers[1]), .Q(registers_6__ap[1]), .QN(), .SE(dftIn), + .SI(registers_9__ap[1]) + ); + SDFF_X1_LVT \registers_reg[14][1] ( + .CK(n_0_44), .D(registers[1]), .Q(registers_14__ap[1]), .QN(), .SE(dftIn), + .SI(registers_16__ap[1]) + ); + AOI22_X1_LVT i_1_0_708( + .A1(registers_6__ap[1]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[1]), + .ZN(n_1_0_674) + ); + SDFF_X1_LVT \registers_reg[19][1] ( + .CK(n_0_49), .D(registers[1]), .Q(registers_19__ap[1]), .QN(), .SE(dftIn), + .SI(registers_1__ap[1]) + ); + SDFF_X1_LVT \registers_reg[2][1] ( + .CK(n_0_32), .D(registers[1]), .Q(registers_2__ap[1]), .QN(), .SE(dftIn), + .SI(registers_30__ap[1]) + ); + AOI22_X1_LVT i_1_0_707( + .A1(registers_19__ap[1]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[1]), + .ZN(n_1_0_673) + ); + NAND3_X1_LVT i_1_0_706( + .A1(n_1_0_675), .A2(n_1_0_674), .A3(n_1_0_673), .ZN(n_1_0_672) + ); + SDFF_X1_LVT \registers_reg[11][1] ( + .CK(n_0_41), .D(registers[1]), .Q(registers_11__ap[1]), .QN(), .SE(dftIn), + .SI(registers_14__ap[1]) + ); + SDFF_X1_LVT \registers_reg[27][1] ( + .CK(n_0_57), .D(registers[1]), .Q(registers_27__ap[1]), .QN(), .SE(dftIn), + .SI(registers_2__ap[1]) + ); + AOI221_X1_LVT i_1_0_705( + .A(n_1_0_672), .B1(n_1_0_1270), .B2(registers_11__ap[1]), .C1(registers_27__ap[1]), + .C2(n_1_0_1279), .ZN(n_1_0_671) + ); + NAND4_X1_LVT i_1_0_704( + .A1(n_1_0_686), .A2(n_1_0_681), .A3(n_1_0_676), .A4(n_1_0_671), .ZN(RRs1[1]) + ); + AND2_X1_LVT i_0_0_0( + .A1(n_0_0_16), .A2(WRd[0]), .ZN(registers[0]) + ); + SDFF_X1_LVT \registers_reg[13][0] ( + .CK(n_0_43), .D(registers[0]), .Q(registers_13__ap[0]), .QN(), .SE(dftIn), + .SI(registers_11__ap[1]) + ); + SDFF_X1_LVT \registers_reg[21][0] ( + .CK(n_0_51), .D(registers[0]), .Q(registers_21__ap[0]), .QN(), .SE(dftIn), + .SI(registers_19__ap[1]) + ); + AOI22_X1_LVT i_1_0_703( + .A1(registers_13__ap[0]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[0]), + .ZN(n_1_0_670) + ); + SDFF_X1_LVT \registers_reg[10][0] ( + .CK(n_0_40), .D(registers[0]), .Q(registers_10__ap[0]), .QN(), .SE(dftIn), + .SI(registers_13__ap[0]) + ); + SDFF_X1_LVT \registers_reg[26][0] ( + .CK(n_0_56), .D(registers[0]), .Q(registers_26__ap[0]), .QN(), .SE(dftIn), + .SI(registers_27__ap[1]) + ); + SDFF_X1_LVT \registers_reg[25][0] ( + .CK(n_0_55), .D(registers[0]), .Q(registers_25__ap[0]), .QN(), .SE(dftIn), + .SI(registers_26__ap[0]) + ); + AOI222_X1_LVT i_1_0_702( + .A1(registers_10__ap[0]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[0]), + .C1(registers_25__ap[0]), .C2(n_1_0_1269), .ZN(n_1_0_669) + ); + SDFF_X1_LVT \registers_reg[28][0] ( + .CK(n_0_58), .D(registers[0]), .Q(registers_28__ap[0]), .QN(), .SE(dftIn), + .SI(registers_25__ap[0]) + ); + SDFF_X1_LVT \registers_reg[8][0] ( + .CK(n_0_38), .D(registers[0]), .Q(registers_8__ap[0]), .QN(), .SE(dftIn), + .SI(registers_6__ap[1]) + ); + AOI22_X1_LVT i_1_0_701( + .A1(registers_28__ap[0]), .A2(n_1_0_1283), .B1(n_1_0_1282), .B2(registers_8__ap[0]), + .ZN(n_1_0_668) + ); + SDFF_X1_LVT \registers_reg[24][0] ( + .CK(n_0_54), .D(registers[0]), .Q(registers_24__ap[0]), .QN(), .SE(dftIn), + .SI(registers_28__ap[0]) + ); + SDFF_X1_LVT \registers_reg[20][0] ( + .CK(n_0_50), .D(registers[0]), .Q(registers_20__ap[0]), .QN(), .SE(dftIn), + .SI(registers_21__ap[0]) + ); + AOI22_X1_LVT i_1_0_700( + .A1(registers_24__ap[0]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[0]), + .ZN(n_1_0_667) + ); + SDFF_X1_LVT \registers_reg[7][0] ( + .CK(n_0_37), .D(registers[0]), .Q(registers_7__ap[0]), .QN(), .SE(dftIn), + .SI(registers_8__ap[0]) + ); + SDFF_X1_LVT \registers_reg[3][0] ( + .CK(n_0_33), .D(registers[0]), .Q(registers_3__ap[0]), .QN(), .SE(dftIn), + .SI(registers_7__ap[0]) + ); + AOI22_X1_LVT i_1_0_699( + .A1(registers_7__ap[0]), .A2(n_1_0_1263), .B1(n_1_0_1257), .B2(registers_3__ap[0]), + .ZN(n_1_0_666) + ); + SDFF_X1_LVT \registers_reg[17][0] ( + .CK(n_0_47), .D(registers[0]), .Q(registers_17__ap[0]), .QN(), .SE(dftIn), + .SI(registers_20__ap[0]) + ); + SDFF_X1_LVT \registers_reg[31][0] ( + .CK(n_0_61), .D(registers[0]), .Q(registers_31__ap[0]), .QN(), .SE(dftIn), + .SI(registers_3__ap[0]) + ); + AOI22_X1_LVT i_1_0_698( + .A1(registers_17__ap[0]), .A2(n_1_0_1271), .B1(n_1_0_1266), .B2(registers_31__ap[0]), + .ZN(n_1_0_665) + ); + SDFF_X1_LVT \registers_reg[29][0] ( + .CK(n_0_59), .D(registers[0]), .Q(registers_29__ap[0]), .QN(), .SE(dftIn), + .SI(registers_24__ap[0]) + ); + SDFF_X1_LVT \registers_reg[23][0] ( + .CK(n_0_53), .D(registers[0]), .Q(registers_23__ap[0]), .QN(), .SE(dftIn), + .SI(registers_17__ap[0]) + ); + AOI22_X1_LVT i_1_0_697( + .A1(registers_29__ap[0]), .A2(n_1_0_1276), .B1(n_1_0_1264), .B2(registers_23__ap[0]), + .ZN(n_1_0_664) + ); + NAND4_X1_LVT i_1_0_696( + .A1(n_1_0_667), .A2(n_1_0_666), .A3(n_1_0_665), .A4(n_1_0_664), .ZN(n_1_0_663) + ); + SDFF_X1_LVT \registers_reg[18][0] ( + .CK(n_0_48), .D(registers[0]), .Q(registers_18__ap[0]), .QN(), .SE(dftIn), + .SI(registers_23__ap[0]) + ); + SDFF_X1_LVT \registers_reg[30][0] ( + .CK(n_0_60), .D(registers[0]), .Q(registers_30__ap[0]), .QN(), .SE(dftIn), + .SI(registers_29__ap[0]) + ); + AOI22_X1_LVT i_1_0_695( + .A1(registers_18__ap[0]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[0]), + .ZN(n_1_0_662) + ); + SDFF_X1_LVT \registers_reg[4][0] ( + .CK(n_0_34), .D(registers[0]), .Q(registers_4__ap[0]), .QN(), .SE(dftIn), + .SI(registers_31__ap[0]) + ); + SDFF_X1_LVT \registers_reg[12][0] ( + .CK(n_0_42), .D(registers[0]), .Q(registers_12__ap[0]), .QN(), .SE(dftIn), + .SI(registers_10__ap[0]) + ); + AOI22_X1_LVT i_1_0_694( + .A1(registers_4__ap[0]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[0]), + .ZN(n_1_0_661) + ); + SDFF_X1_LVT \registers_reg[15][0] ( + .CK(n_0_45), .D(registers[0]), .Q(registers_15__ap[0]), .QN(), .SE(dftIn), + .SI(registers_12__ap[0]) + ); + SDFF_X1_LVT \registers_reg[16][0] ( + .CK(n_0_46), .D(registers[0]), .Q(registers_16__ap[0]), .QN(), .SE(dftIn), + .SI(registers_15__ap[0]) + ); + AOI22_X1_LVT i_1_0_693( + .A1(registers_15__ap[0]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[0]), + .ZN(n_1_0_660) + ); + SDFF_X1_LVT \registers_reg[22][0] ( + .CK(n_0_52), .D(registers[0]), .Q(registers_22__ap[0]), .QN(), .SE(dftIn), + .SI(registers_18__ap[0]) + ); + SDFF_X1_LVT \registers_reg[5][0] ( + .CK(n_0_35), .D(registers[0]), .Q(registers_5__ap[0]), .QN(), .SE(dftIn), + .SI(registers_4__ap[0]) + ); + AOI22_X1_LVT i_1_0_692( + .A1(registers_22__ap[0]), .A2(n_1_0_1294), .B1(n_1_0_1273), .B2(registers_5__ap[0]), + .ZN(n_1_0_659) + ); + NAND4_X1_LVT i_1_0_691( + .A1(n_1_0_662), .A2(n_1_0_661), .A3(n_1_0_660), .A4(n_1_0_659), .ZN(n_1_0_658) + ); + SDFF_X1_LVT \registers_reg[19][0] ( + .CK(n_0_49), .D(registers[0]), .Q(registers_19__ap[0]), .QN(), .SE(dftIn), + .SI(registers_22__ap[0]) + ); + SDFF_X1_LVT \registers_reg[2][0] ( + .CK(n_0_32), .D(registers[0]), .Q(registers_2__ap[0]), .QN(), .SE(dftIn), + .SI(registers_30__ap[0]) + ); + AOI22_X1_LVT i_1_0_690( + .A1(registers_19__ap[0]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[0]), + .ZN(n_1_0_657) + ); + SDFF_X1_LVT \registers_reg[9][0] ( + .CK(n_0_39), .D(registers[0]), .Q(registers_9__ap[0]), .QN(), .SE(dftIn), + .SI(registers_5__ap[0]) + ); + SDFF_X1_LVT \registers_reg[1][0] ( + .CK(n_0_0), .D(registers[0]), .Q(registers_1__ap[0]), .QN(), .SE(dftIn), + .SI(registers_19__ap[0]) + ); + AOI22_X1_LVT i_1_0_689( + .A1(registers_9__ap[0]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[0]), + .ZN(n_1_0_656) + ); + SDFF_X1_LVT \registers_reg[6][0] ( + .CK(n_0_36), .D(registers[0]), .Q(registers_6__ap[0]), .QN(), .SE(dftIn), + .SI(registers_9__ap[0]) + ); + SDFF_X1_LVT \registers_reg[14][0] ( + .CK(n_0_44), .D(registers[0]), .Q(registers_14__ap[0]), .QN(), .SE(dftIn), + .SI(registers_16__ap[0]) + ); + AOI22_X1_LVT i_1_0_688( + .A1(registers_6__ap[0]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[0]), + .ZN(n_1_0_655) + ); + SDFF_X1_LVT \registers_reg[27][0] ( + .CK(n_0_57), .D(registers[0]), .Q(registers_27__ap[0]), .QN(), .SE(dftIn), + .SI(registers_2__ap[0]) + ); + SDFF_X1_LVT \registers_reg[11][0] ( + .CK(n_0_41), .D(registers[0]), .Q(registers_11__ap[0]), .QN(), .SE(dftIn), + .SI(registers_14__ap[0]) + ); + AOI22_X1_LVT i_1_0_687( + .A1(registers_27__ap[0]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[0]), + .ZN(n_1_0_654) + ); + NAND4_X1_LVT i_1_0_686( + .A1(n_1_0_657), .A2(n_1_0_656), .A3(n_1_0_655), .A4(n_1_0_654), .ZN(n_1_0_653) + ); + NOR3_X1_LVT i_1_0_685( + .A1(n_1_0_663), .A2(n_1_0_658), .A3(n_1_0_653), .ZN(n_1_0_652) + ); + NAND4_X1_LVT i_1_0_684( + .A1(n_1_0_670), .A2(n_1_0_669), .A3(n_1_0_668), .A4(n_1_0_652), .ZN(RRs1[0]) + ); + INV_X1_LVT i_1_0_1366( + .A(Rs2[1]), .ZN(n_1_0_1302) + ); + NAND3_X1_LVT i_1_0_683( + .A1(n_1_0_1302), .A2(Rs2[4]), .A3(Rs2[2]), .ZN(n_1_0_651) + ); + INV_X1_LVT i_1_0_1369( + .A(Rs2[3]), .ZN(n_1_0_1305) + ); + OR2_X1_LVT i_1_0_673( + .A1(n_1_0_1305), .A2(Rs2[0]), .ZN(n_1_0_641) + ); + NOR2_X1_LVT i_1_0_666( + .A1(n_1_0_651), .A2(n_1_0_641), .ZN(n_1_0_634) + ); + NAND2_X1_LVT i_1_0_677( + .A1(n_1_0_1305), .A2(Rs2[0]), .ZN(n_1_0_645) + ); + INV_X1_LVT i_1_0_1368( + .A(Rs2[2]), .ZN(n_1_0_1304) + ); + NAND3_X1_LVT i_1_0_662( + .A1(n_1_0_1304), .A2(n_1_0_1302), .A3(Rs2[4]), .ZN(n_1_0_630) + ); + NOR2_X1_LVT i_1_0_661( + .A1(n_1_0_645), .A2(n_1_0_630), .ZN(n_1_0_629) + ); + AOI22_X1_LVT i_1_0_641( + .A1(registers_28__ap[31]), .A2(n_1_0_634), .B1(n_1_0_629), .B2(registers_17__ap[31]), + .ZN(n_1_0_609) + ); + NAND3_X1_LVT i_1_0_680( + .A1(n_1_0_1304), .A2(Rs2[4]), .A3(Rs2[1]), .ZN(n_1_0_648) + ); + NOR2_X1_LVT i_1_0_672( + .A1(n_1_0_648), .A2(n_1_0_641), .ZN(n_1_0_640) + ); + INV_X1_LVT i_1_0_1367( + .A(Rs2[4]), .ZN(n_1_0_1303) + ); + NAND3_X1_LVT i_1_0_657( + .A1(n_1_0_1304), .A2(n_1_0_1303), .A3(Rs2[1]), .ZN(n_1_0_625) + ); + NOR2_X1_LVT i_1_0_656( + .A1(n_1_0_641), .A2(n_1_0_625), .ZN(n_1_0_624) + ); + NOR4_X1_LVT i_1_0_658( + .A1(n_1_0_641), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), .ZN(n_1_0_626) + ); + AOI222_X1_LVT i_1_0_640( + .A1(registers_26__ap[31]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[31]), + .C1(n_1_0_626), .C2(registers_8__ap[31]), .ZN(n_1_0_608) + ); + NAND2_X1_LVT i_1_0_682( + .A1(Rs2[0]), .A2(Rs2[3]), .ZN(n_1_0_650) + ); + NOR2_X1_LVT i_1_0_681( + .A1(n_1_0_651), .A2(n_1_0_650), .ZN(n_1_0_649) + ); + NOR4_X1_LVT i_1_0_649( + .A1(n_1_0_650), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), .ZN(n_1_0_617) + ); + AOI22_X1_LVT i_1_0_639( + .A1(registers_29__ap[31]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[31]), + .ZN(n_1_0_607) + ); + NOR4_X1_LVT i_1_0_676( + .A1(n_1_0_645), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), .ZN(n_1_0_644) + ); + OR2_X1_LVT i_1_0_679( + .A1(Rs2[0]), .A2(Rs2[3]), .ZN(n_1_0_647) + ); + NAND3_X1_LVT i_1_0_660( + .A1(n_1_0_1303), .A2(Rs2[1]), .A3(Rs2[2]), .ZN(n_1_0_628) + ); + NOR2_X1_LVT i_1_0_648( + .A1(n_1_0_647), .A2(n_1_0_628), .ZN(n_1_0_616) + ); + AOI22_X1_LVT i_1_0_638( + .A1(registers_1__ap[31]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[31]), + .ZN(n_1_0_606) + ); + NOR2_X1_LVT i_1_0_655( + .A1(n_1_0_645), .A2(n_1_0_628), .ZN(n_1_0_623) + ); + NAND3_X1_LVT i_1_0_675( + .A1(Rs2[2]), .A2(Rs2[4]), .A3(Rs2[1]), .ZN(n_1_0_643) + ); + NOR2_X1_LVT i_1_0_647( + .A1(n_1_0_645), .A2(n_1_0_643), .ZN(n_1_0_615) + ); + AOI22_X1_LVT i_1_0_637( + .A1(registers_7__ap[31]), .A2(n_1_0_623), .B1(n_1_0_615), .B2(registers_23__ap[31]), + .ZN(n_1_0_605) + ); + NOR2_X1_LVT i_1_0_665( + .A1(n_1_0_648), .A2(n_1_0_645), .ZN(n_1_0_633) + ); + NOR2_X1_LVT i_1_0_646( + .A1(n_1_0_647), .A2(n_1_0_630), .ZN(n_1_0_614) + ); + AOI22_X1_LVT i_1_0_636( + .A1(registers_19__ap[31]), .A2(n_1_0_633), .B1(n_1_0_614), .B2(registers_16__ap[31]), + .ZN(n_1_0_604) + ); + NOR2_X1_LVT i_1_0_669( + .A1(n_1_0_650), .A2(n_1_0_643), .ZN(n_1_0_637) + ); + NAND3_X1_LVT i_1_0_671( + .A1(n_1_0_1303), .A2(n_1_0_1302), .A3(Rs2[2]), .ZN(n_1_0_639) + ); + NOR2_X1_LVT i_1_0_667( + .A1(n_1_0_645), .A2(n_1_0_639), .ZN(n_1_0_635) + ); + AOI22_X1_LVT i_1_0_635( + .A1(registers_31__ap[31]), .A2(n_1_0_637), .B1(n_1_0_635), .B2(registers_5__ap[31]), + .ZN(n_1_0_603) + ); + NAND4_X1_LVT i_1_0_634( + .A1(n_1_0_606), .A2(n_1_0_605), .A3(n_1_0_604), .A4(n_1_0_603), .ZN(n_1_0_602) + ); + NOR2_X1_LVT i_1_0_678( + .A1(n_1_0_648), .A2(n_1_0_647), .ZN(n_1_0_646) + ); + NOR2_X1_LVT i_1_0_654( + .A1(n_1_0_643), .A2(n_1_0_641), .ZN(n_1_0_622) + ); + AOI22_X1_LVT i_1_0_633( + .A1(registers_18__ap[31]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[31]), + .ZN(n_1_0_601) + ); + NOR2_X1_LVT i_1_0_670( + .A1(n_1_0_647), .A2(n_1_0_639), .ZN(n_1_0_638) + ); + NOR2_X1_LVT i_1_0_645( + .A1(n_1_0_651), .A2(n_1_0_647), .ZN(n_1_0_613) + ); + AOI22_X1_LVT i_1_0_632( + .A1(registers_4__ap[31]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[31]), + .ZN(n_1_0_600) + ); + NOR2_X1_LVT i_1_0_674( + .A1(n_1_0_647), .A2(n_1_0_643), .ZN(n_1_0_642) + ); + NOR2_X1_LVT i_1_0_644( + .A1(n_1_0_651), .A2(n_1_0_645), .ZN(n_1_0_612) + ); + AOI22_X1_LVT i_1_0_631( + .A1(registers_22__ap[31]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[31]), + .ZN(n_1_0_599) + ); + NOR2_X1_LVT i_1_0_664( + .A1(n_1_0_641), .A2(n_1_0_639), .ZN(n_1_0_632) + ); + NOR2_X1_LVT i_1_0_653( + .A1(n_1_0_641), .A2(n_1_0_630), .ZN(n_1_0_621) + ); + AOI22_X1_LVT i_1_0_630( + .A1(registers_12__ap[31]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[31]), + .ZN(n_1_0_598) + ); + NAND4_X1_LVT i_1_0_629( + .A1(n_1_0_601), .A2(n_1_0_600), .A3(n_1_0_599), .A4(n_1_0_598), .ZN(n_1_0_597) + ); + NOR2_X1_LVT i_1_0_663( + .A1(n_1_0_650), .A2(n_1_0_639), .ZN(n_1_0_631) + ); + NOR2_X1_LVT i_1_0_652( + .A1(n_1_0_650), .A2(n_1_0_630), .ZN(n_1_0_620) + ); + AOI22_X1_LVT i_1_0_628( + .A1(registers_13__ap[31]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[31]), + .ZN(n_1_0_596) + ); + NOR2_X1_LVT i_1_0_659( + .A1(n_1_0_650), .A2(n_1_0_628), .ZN(n_1_0_627) + ); + NOR2_X1_LVT i_1_0_651( + .A1(n_1_0_641), .A2(n_1_0_628), .ZN(n_1_0_619) + ); + AOI22_X1_LVT i_1_0_627( + .A1(registers_15__ap[31]), .A2(n_1_0_627), .B1(n_1_0_619), .B2(registers_14__ap[31]), + .ZN(n_1_0_595) + ); + NOR2_X1_LVT i_1_0_668( + .A1(n_1_0_650), .A2(n_1_0_648), .ZN(n_1_0_636) + ); + NOR2_X1_LVT i_1_0_643( + .A1(n_1_0_650), .A2(n_1_0_625), .ZN(n_1_0_611) + ); + AOI22_X1_LVT i_1_0_626( + .A1(registers_27__ap[31]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[31]), + .ZN(n_1_0_594) + ); + NOR2_X1_LVT i_1_0_650( + .A1(n_1_0_647), .A2(n_1_0_625), .ZN(n_1_0_618) + ); + NOR2_X1_LVT i_1_0_642( + .A1(n_1_0_645), .A2(n_1_0_625), .ZN(n_1_0_610) + ); + AOI22_X1_LVT i_1_0_625( + .A1(registers_2__ap[31]), .A2(n_1_0_618), .B1(n_1_0_610), .B2(registers_3__ap[31]), + .ZN(n_1_0_593) + ); + NAND4_X1_LVT i_1_0_624( + .A1(n_1_0_596), .A2(n_1_0_595), .A3(n_1_0_594), .A4(n_1_0_593), .ZN(n_1_0_592) + ); + NOR3_X1_LVT i_1_0_623( + .A1(n_1_0_602), .A2(n_1_0_597), .A3(n_1_0_592), .ZN(n_1_0_591) + ); + NAND4_X1_LVT i_1_0_622( + .A1(n_1_0_609), .A2(n_1_0_608), .A3(n_1_0_607), .A4(n_1_0_591), .ZN(RRs2[31]) + ); + AOI22_X1_LVT i_1_0_620( + .A1(registers_29__ap[30]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[30]), + .ZN(n_1_0_589) + ); + AOI22_X1_LVT i_1_0_621( + .A1(registers_7__ap[30]), .A2(n_1_0_623), .B1(n_1_0_615), .B2(registers_23__ap[30]), + .ZN(n_1_0_590) + ); + AOI22_X1_LVT i_1_0_619( + .A1(registers_1__ap[30]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[30]), + .ZN(n_1_0_588) + ); + AOI22_X1_LVT i_1_0_618( + .A1(registers_5__ap[30]), .A2(n_1_0_635), .B1(n_1_0_633), .B2(registers_19__ap[30]), + .ZN(n_1_0_587) + ); + NAND3_X1_LVT i_1_0_617( + .A1(n_1_0_590), .A2(n_1_0_588), .A3(n_1_0_587), .ZN(n_1_0_586) + ); + AOI221_X1_LVT i_1_0_616( + .A(n_1_0_586), .B1(n_1_0_637), .B2(registers_31__ap[30]), .C1(registers_16__ap[30]), + .C2(n_1_0_614), .ZN(n_1_0_585) + ); + AOI222_X1_LVT i_1_0_615( + .A1(registers_26__ap[30]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[30]), + .C1(n_1_0_626), .C2(registers_8__ap[30]), .ZN(n_1_0_584) + ); + NAND3_X1_LVT i_1_0_614( + .A1(n_1_0_589), .A2(n_1_0_585), .A3(n_1_0_584), .ZN(n_1_0_583) + ); + AOI221_X1_LVT i_1_0_613( + .A(n_1_0_583), .B1(n_1_0_629), .B2(registers_17__ap[30]), .C1(registers_28__ap[30]), + .C2(n_1_0_634), .ZN(n_1_0_582) + ); + AOI22_X1_LVT i_1_0_612( + .A1(registers_18__ap[30]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[30]), + .ZN(n_1_0_581) + ); + AOI22_X1_LVT i_1_0_611( + .A1(registers_4__ap[30]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[30]), + .ZN(n_1_0_580) + ); + AOI22_X1_LVT i_1_0_610( + .A1(registers_22__ap[30]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[30]), + .ZN(n_1_0_579) + ); + NAND3_X1_LVT i_1_0_609( + .A1(n_1_0_581), .A2(n_1_0_580), .A3(n_1_0_579), .ZN(n_1_0_578) + ); + AOI221_X1_LVT i_1_0_608( + .A(n_1_0_578), .B1(n_1_0_621), .B2(registers_24__ap[30]), .C1(registers_12__ap[30]), + .C2(n_1_0_632), .ZN(n_1_0_577) + ); + AOI22_X1_LVT i_1_0_607( + .A1(registers_13__ap[30]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[30]), + .ZN(n_1_0_576) + ); + AOI22_X1_LVT i_1_0_606( + .A1(registers_15__ap[30]), .A2(n_1_0_627), .B1(n_1_0_619), .B2(registers_14__ap[30]), + .ZN(n_1_0_575) + ); + AOI22_X1_LVT i_1_0_605( + .A1(registers_27__ap[30]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[30]), + .ZN(n_1_0_574) + ); + NAND3_X1_LVT i_1_0_604( + .A1(n_1_0_576), .A2(n_1_0_575), .A3(n_1_0_574), .ZN(n_1_0_573) + ); + AOI221_X1_LVT i_1_0_603( + .A(n_1_0_573), .B1(n_1_0_610), .B2(registers_3__ap[30]), .C1(registers_2__ap[30]), + .C2(n_1_0_618), .ZN(n_1_0_572) + ); + NAND3_X1_LVT i_1_0_602( + .A1(n_1_0_582), .A2(n_1_0_577), .A3(n_1_0_572), .ZN(RRs2[30]) + ); + AOI22_X1_LVT i_1_0_600( + .A1(registers_28__ap[29]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[29]), + .ZN(n_1_0_570) + ); + AOI22_X1_LVT i_1_0_601( + .A1(registers_31__ap[29]), .A2(n_1_0_637), .B1(n_1_0_627), .B2(registers_15__ap[29]), + .ZN(n_1_0_571) + ); + AOI22_X1_LVT i_1_0_599( + .A1(registers_24__ap[29]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[29]), + .ZN(n_1_0_569) + ); + AOI22_X1_LVT i_1_0_598( + .A1(registers_19__ap[29]), .A2(n_1_0_633), .B1(n_1_0_629), .B2(registers_17__ap[29]), + .ZN(n_1_0_568) + ); + NAND3_X1_LVT i_1_0_597( + .A1(n_1_0_571), .A2(n_1_0_569), .A3(n_1_0_568), .ZN(n_1_0_567) + ); + AOI221_X1_LVT i_1_0_596( + .A(n_1_0_567), .B1(n_1_0_615), .B2(registers_23__ap[29]), .C1(registers_29__ap[29]), + .C2(n_1_0_649), .ZN(n_1_0_566) + ); + AOI222_X1_LVT i_1_0_595( + .A1(registers_26__ap[29]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[29]), + .C1(n_1_0_620), .C2(registers_25__ap[29]), .ZN(n_1_0_565) + ); + NAND3_X1_LVT i_1_0_594( + .A1(n_1_0_570), .A2(n_1_0_566), .A3(n_1_0_565), .ZN(n_1_0_564) + ); + AOI221_X1_LVT i_1_0_593( + .A(n_1_0_564), .B1(n_1_0_612), .B2(registers_21__ap[29]), .C1(registers_13__ap[29]), + .C2(n_1_0_631), .ZN(n_1_0_563) + ); + AOI22_X1_LVT i_1_0_592( + .A1(registers_18__ap[29]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[29]), + .ZN(n_1_0_562) + ); + AOI22_X1_LVT i_1_0_591( + .A1(registers_4__ap[29]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[29]), + .ZN(n_1_0_561) + ); + AOI22_X1_LVT i_1_0_590( + .A1(registers_7__ap[29]), .A2(n_1_0_623), .B1(n_1_0_614), .B2(registers_16__ap[29]), + .ZN(n_1_0_560) + ); + NAND3_X1_LVT i_1_0_589( + .A1(n_1_0_562), .A2(n_1_0_561), .A3(n_1_0_560), .ZN(n_1_0_559) + ); + AOI221_X1_LVT i_1_0_588( + .A(n_1_0_559), .B1(n_1_0_642), .B2(registers_22__ap[29]), .C1(registers_5__ap[29]), + .C2(n_1_0_635), .ZN(n_1_0_558) + ); + AOI22_X1_LVT i_1_0_587( + .A1(registers_1__ap[29]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[29]), + .ZN(n_1_0_557) + ); + AOI22_X1_LVT i_1_0_586( + .A1(registers_14__ap[29]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[29]), + .ZN(n_1_0_556) + ); + AOI22_X1_LVT i_1_0_585( + .A1(registers_27__ap[29]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[29]), + .ZN(n_1_0_555) + ); + NAND3_X1_LVT i_1_0_584( + .A1(n_1_0_557), .A2(n_1_0_556), .A3(n_1_0_555), .ZN(n_1_0_554) + ); + AOI221_X1_LVT i_1_0_583( + .A(n_1_0_554), .B1(n_1_0_610), .B2(registers_3__ap[29]), .C1(registers_2__ap[29]), + .C2(n_1_0_618), .ZN(n_1_0_553) + ); + NAND3_X1_LVT i_1_0_582( + .A1(n_1_0_563), .A2(n_1_0_558), .A3(n_1_0_553), .ZN(RRs2[29]) + ); + AOI22_X1_LVT i_1_0_581( + .A1(registers_5__ap[28]), .A2(n_1_0_635), .B1(n_1_0_634), .B2(registers_28__ap[28]), + .ZN(n_1_0_552) + ); + AOI222_X1_LVT i_1_0_580( + .A1(registers_26__ap[28]), .A2(n_1_0_640), .B1(n_1_0_633), .B2(registers_19__ap[28]), + .C1(n_1_0_626), .C2(registers_8__ap[28]), .ZN(n_1_0_551) + ); + AOI22_X1_LVT i_1_0_579( + .A1(registers_2__ap[28]), .A2(n_1_0_618), .B1(n_1_0_617), .B2(registers_9__ap[28]), + .ZN(n_1_0_550) + ); + AOI22_X1_LVT i_1_0_578( + .A1(registers_7__ap[28]), .A2(n_1_0_623), .B1(n_1_0_612), .B2(registers_21__ap[28]), + .ZN(n_1_0_549) + ); + AOI22_X1_LVT i_1_0_577( + .A1(registers_16__ap[28]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[28]), + .ZN(n_1_0_548) + ); + AOI22_X1_LVT i_1_0_576( + .A1(registers_31__ap[28]), .A2(n_1_0_637), .B1(n_1_0_619), .B2(registers_14__ap[28]), + .ZN(n_1_0_547) + ); + AOI22_X1_LVT i_1_0_575( + .A1(registers_15__ap[28]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[28]), + .ZN(n_1_0_546) + ); + NAND4_X1_LVT i_1_0_574( + .A1(n_1_0_549), .A2(n_1_0_548), .A3(n_1_0_547), .A4(n_1_0_546), .ZN(n_1_0_545) + ); + AOI22_X1_LVT i_1_0_573( + .A1(registers_22__ap[28]), .A2(n_1_0_642), .B1(n_1_0_622), .B2(registers_30__ap[28]), + .ZN(n_1_0_544) + ); + AOI22_X1_LVT i_1_0_572( + .A1(registers_4__ap[28]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[28]), + .ZN(n_1_0_543) + ); + AOI22_X1_LVT i_1_0_571( + .A1(registers_29__ap[28]), .A2(n_1_0_649), .B1(n_1_0_644), .B2(registers_1__ap[28]), + .ZN(n_1_0_542) + ); + AOI22_X1_LVT i_1_0_570( + .A1(registers_12__ap[28]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[28]), + .ZN(n_1_0_541) + ); + NAND4_X1_LVT i_1_0_569( + .A1(n_1_0_544), .A2(n_1_0_543), .A3(n_1_0_542), .A4(n_1_0_541), .ZN(n_1_0_540) + ); + AOI22_X1_LVT i_1_0_568( + .A1(registers_13__ap[28]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[28]), + .ZN(n_1_0_539) + ); + AOI22_X1_LVT i_1_0_567( + .A1(registers_17__ap[28]), .A2(n_1_0_629), .B1(n_1_0_616), .B2(registers_6__ap[28]), + .ZN(n_1_0_538) + ); + AOI22_X1_LVT i_1_0_566( + .A1(registers_10__ap[28]), .A2(n_1_0_624), .B1(n_1_0_615), .B2(registers_23__ap[28]), + .ZN(n_1_0_537) + ); + AOI22_X1_LVT i_1_0_565( + .A1(registers_18__ap[28]), .A2(n_1_0_646), .B1(n_1_0_636), .B2(registers_27__ap[28]), + .ZN(n_1_0_536) + ); + NAND4_X1_LVT i_1_0_564( + .A1(n_1_0_539), .A2(n_1_0_538), .A3(n_1_0_537), .A4(n_1_0_536), .ZN(n_1_0_535) + ); + NOR3_X1_LVT i_1_0_563( + .A1(n_1_0_545), .A2(n_1_0_540), .A3(n_1_0_535), .ZN(n_1_0_534) + ); + NAND4_X1_LVT i_1_0_562( + .A1(n_1_0_552), .A2(n_1_0_551), .A3(n_1_0_550), .A4(n_1_0_534), .ZN(RRs2[28]) + ); + AOI22_X1_LVT i_1_0_561( + .A1(registers_17__ap[27]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[27]), + .ZN(n_1_0_533) + ); + AOI222_X1_LVT i_1_0_560( + .A1(registers_19__ap[27]), .A2(n_1_0_633), .B1(n_1_0_631), .B2(registers_13__ap[27]), + .C1(registers_30__ap[27]), .C2(n_1_0_622), .ZN(n_1_0_532) + ); + AOI22_X1_LVT i_1_0_559( + .A1(registers_1__ap[27]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[27]), + .ZN(n_1_0_531) + ); + AOI22_X1_LVT i_1_0_558( + .A1(registers_24__ap[27]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[27]), + .ZN(n_1_0_530) + ); + AOI22_X1_LVT i_1_0_557( + .A1(registers_15__ap[27]), .A2(n_1_0_627), .B1(n_1_0_611), .B2(registers_11__ap[27]), + .ZN(n_1_0_529) + ); + AOI22_X1_LVT i_1_0_556( + .A1(registers_4__ap[27]), .A2(n_1_0_638), .B1(n_1_0_636), .B2(registers_27__ap[27]), + .ZN(n_1_0_528) + ); + AOI22_X1_LVT i_1_0_555( + .A1(registers_31__ap[27]), .A2(n_1_0_637), .B1(n_1_0_618), .B2(registers_2__ap[27]), + .ZN(n_1_0_527) + ); + NAND4_X1_LVT i_1_0_554( + .A1(n_1_0_530), .A2(n_1_0_529), .A3(n_1_0_528), .A4(n_1_0_527), .ZN(n_1_0_526) + ); + AOI22_X1_LVT i_1_0_553( + .A1(registers_18__ap[27]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[27]), + .ZN(n_1_0_525) + ); + AOI22_X1_LVT i_1_0_552( + .A1(registers_5__ap[27]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[27]), + .ZN(n_1_0_524) + ); + AOI22_X1_LVT i_1_0_551( + .A1(registers_6__ap[27]), .A2(n_1_0_616), .B1(n_1_0_614), .B2(registers_16__ap[27]), + .ZN(n_1_0_523) + ); + AOI22_X1_LVT i_1_0_550( + .A1(registers_22__ap[27]), .A2(n_1_0_642), .B1(n_1_0_620), .B2(registers_25__ap[27]), + .ZN(n_1_0_522) + ); + NAND4_X1_LVT i_1_0_549( + .A1(n_1_0_525), .A2(n_1_0_524), .A3(n_1_0_523), .A4(n_1_0_522), .ZN(n_1_0_521) + ); + AOI22_X1_LVT i_1_0_548( + .A1(registers_29__ap[27]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[27]), + .ZN(n_1_0_520) + ); + AOI22_X1_LVT i_1_0_547( + .A1(registers_7__ap[27]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[27]), + .ZN(n_1_0_519) + ); + AOI22_X1_LVT i_1_0_546( + .A1(registers_8__ap[27]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[27]), + .ZN(n_1_0_518) + ); + AOI22_X1_LVT i_1_0_545( + .A1(registers_10__ap[27]), .A2(n_1_0_624), .B1(n_1_0_610), .B2(registers_3__ap[27]), + .ZN(n_1_0_517) + ); + NAND4_X1_LVT i_1_0_544( + .A1(n_1_0_520), .A2(n_1_0_519), .A3(n_1_0_518), .A4(n_1_0_517), .ZN(n_1_0_516) + ); + NOR3_X1_LVT i_1_0_543( + .A1(n_1_0_526), .A2(n_1_0_521), .A3(n_1_0_516), .ZN(n_1_0_515) + ); + NAND4_X1_LVT i_1_0_542( + .A1(n_1_0_533), .A2(n_1_0_532), .A3(n_1_0_531), .A4(n_1_0_515), .ZN(RRs2[27]) + ); + AOI22_X1_LVT i_1_0_541( + .A1(registers_17__ap[26]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[26]), + .ZN(n_1_0_514) + ); + AOI222_X1_LVT i_1_0_540( + .A1(registers_19__ap[26]), .A2(n_1_0_633), .B1(n_1_0_622), .B2(registers_30__ap[26]), + .C1(n_1_0_631), .C2(registers_13__ap[26]), .ZN(n_1_0_513) + ); + AOI22_X1_LVT i_1_0_539( + .A1(registers_1__ap[26]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[26]), + .ZN(n_1_0_512) + ); + AOI22_X1_LVT i_1_0_538( + .A1(registers_24__ap[26]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[26]), + .ZN(n_1_0_511) + ); + AOI22_X1_LVT i_1_0_537( + .A1(registers_15__ap[26]), .A2(n_1_0_627), .B1(n_1_0_611), .B2(registers_11__ap[26]), + .ZN(n_1_0_510) + ); + AOI22_X1_LVT i_1_0_536( + .A1(registers_4__ap[26]), .A2(n_1_0_638), .B1(n_1_0_636), .B2(registers_27__ap[26]), + .ZN(n_1_0_509) + ); + AOI22_X1_LVT i_1_0_535( + .A1(registers_31__ap[26]), .A2(n_1_0_637), .B1(n_1_0_618), .B2(registers_2__ap[26]), + .ZN(n_1_0_508) + ); + NAND4_X1_LVT i_1_0_534( + .A1(n_1_0_511), .A2(n_1_0_510), .A3(n_1_0_509), .A4(n_1_0_508), .ZN(n_1_0_507) + ); + AOI22_X1_LVT i_1_0_533( + .A1(registers_18__ap[26]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[26]), + .ZN(n_1_0_506) + ); + AOI22_X1_LVT i_1_0_532( + .A1(registers_5__ap[26]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[26]), + .ZN(n_1_0_505) + ); + AOI22_X1_LVT i_1_0_531( + .A1(registers_6__ap[26]), .A2(n_1_0_616), .B1(n_1_0_614), .B2(registers_16__ap[26]), + .ZN(n_1_0_504) + ); + AOI22_X1_LVT i_1_0_530( + .A1(registers_22__ap[26]), .A2(n_1_0_642), .B1(n_1_0_620), .B2(registers_25__ap[26]), + .ZN(n_1_0_503) + ); + NAND4_X1_LVT i_1_0_529( + .A1(n_1_0_506), .A2(n_1_0_505), .A3(n_1_0_504), .A4(n_1_0_503), .ZN(n_1_0_502) + ); + AOI22_X1_LVT i_1_0_528( + .A1(registers_29__ap[26]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[26]), + .ZN(n_1_0_501) + ); + AOI22_X1_LVT i_1_0_527( + .A1(registers_7__ap[26]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[26]), + .ZN(n_1_0_500) + ); + AOI22_X1_LVT i_1_0_526( + .A1(registers_8__ap[26]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[26]), + .ZN(n_1_0_499) + ); + AOI22_X1_LVT i_1_0_525( + .A1(registers_10__ap[26]), .A2(n_1_0_624), .B1(n_1_0_610), .B2(registers_3__ap[26]), + .ZN(n_1_0_498) + ); + NAND4_X1_LVT i_1_0_524( + .A1(n_1_0_501), .A2(n_1_0_500), .A3(n_1_0_499), .A4(n_1_0_498), .ZN(n_1_0_497) + ); + NOR3_X1_LVT i_1_0_523( + .A1(n_1_0_507), .A2(n_1_0_502), .A3(n_1_0_497), .ZN(n_1_0_496) + ); + NAND4_X1_LVT i_1_0_522( + .A1(n_1_0_514), .A2(n_1_0_513), .A3(n_1_0_512), .A4(n_1_0_496), .ZN(RRs2[26]) + ); + AOI22_X1_LVT i_1_0_520( + .A1(registers_5__ap[25]), .A2(n_1_0_635), .B1(n_1_0_634), .B2(registers_28__ap[25]), + .ZN(n_1_0_494) + ); + AOI22_X1_LVT i_1_0_521( + .A1(registers_8__ap[25]), .A2(n_1_0_626), .B1(n_1_0_620), .B2(registers_25__ap[25]), + .ZN(n_1_0_495) + ); + AOI22_X1_LVT i_1_0_519( + .A1(registers_14__ap[25]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[25]), + .ZN(n_1_0_493) + ); + AOI22_X1_LVT i_1_0_518( + .A1(registers_16__ap[25]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[25]), + .ZN(n_1_0_492) + ); + NAND3_X1_LVT i_1_0_517( + .A1(n_1_0_495), .A2(n_1_0_493), .A3(n_1_0_492), .ZN(n_1_0_491) + ); + AOI221_X1_LVT i_1_0_516( + .A(n_1_0_491), .B1(n_1_0_624), .B2(registers_10__ap[25]), .C1(registers_6__ap[25]), + .C2(n_1_0_616), .ZN(n_1_0_490) + ); + AOI222_X1_LVT i_1_0_515( + .A1(registers_1__ap[25]), .A2(n_1_0_644), .B1(n_1_0_640), .B2(registers_26__ap[25]), + .C1(n_1_0_622), .C2(registers_30__ap[25]), .ZN(n_1_0_489) + ); + NAND2_X1_LVT i_1_0_514( + .A1(n_1_0_490), .A2(n_1_0_489), .ZN(n_1_0_488) + ); + AOI221_X1_LVT i_1_0_513( + .A(n_1_0_488), .B1(n_1_0_649), .B2(registers_29__ap[25]), .C1(registers_2__ap[25]), + .C2(n_1_0_618), .ZN(n_1_0_487) + ); + AOI22_X1_LVT i_1_0_512( + .A1(registers_12__ap[25]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[25]), + .ZN(n_1_0_486) + ); + AOI22_X1_LVT i_1_0_511( + .A1(registers_22__ap[25]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[25]), + .ZN(n_1_0_485) + ); + AOI22_X1_LVT i_1_0_510( + .A1(registers_4__ap[25]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[25]), + .ZN(n_1_0_484) + ); + NAND3_X1_LVT i_1_0_509( + .A1(n_1_0_486), .A2(n_1_0_485), .A3(n_1_0_484), .ZN(n_1_0_483) + ); + AOI221_X1_LVT i_1_0_508( + .A(n_1_0_483), .B1(n_1_0_633), .B2(registers_19__ap[25]), .C1(registers_18__ap[25]), + .C2(n_1_0_646), .ZN(n_1_0_482) + ); + AOI22_X1_LVT i_1_0_507( + .A1(registers_15__ap[25]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[25]), + .ZN(n_1_0_481) + ); + AOI22_X1_LVT i_1_0_506( + .A1(registers_23__ap[25]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[25]), + .ZN(n_1_0_480) + ); + AOI22_X1_LVT i_1_0_505( + .A1(registers_13__ap[25]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[25]), + .ZN(n_1_0_479) + ); + NAND3_X1_LVT i_1_0_504( + .A1(n_1_0_481), .A2(n_1_0_480), .A3(n_1_0_479), .ZN(n_1_0_478) + ); + AOI221_X1_LVT i_1_0_503( + .A(n_1_0_478), .B1(n_1_0_636), .B2(registers_27__ap[25]), .C1(registers_31__ap[25]), + .C2(n_1_0_637), .ZN(n_1_0_477) + ); + NAND4_X1_LVT i_1_0_502( + .A1(n_1_0_494), .A2(n_1_0_487), .A3(n_1_0_482), .A4(n_1_0_477), .ZN(RRs2[25]) + ); + AOI22_X1_LVT i_1_0_501( + .A1(registers_17__ap[24]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[24]), + .ZN(n_1_0_476) + ); + AOI222_X1_LVT i_1_0_500( + .A1(registers_13__ap[24]), .A2(n_1_0_631), .B1(n_1_0_622), .B2(registers_30__ap[24]), + .C1(registers_26__ap[24]), .C2(n_1_0_640), .ZN(n_1_0_475) + ); + AOI22_X1_LVT i_1_0_499( + .A1(registers_1__ap[24]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[24]), + .ZN(n_1_0_474) + ); + AOI22_X1_LVT i_1_0_498( + .A1(registers_24__ap[24]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[24]), + .ZN(n_1_0_473) + ); + AOI22_X1_LVT i_1_0_497( + .A1(registers_8__ap[24]), .A2(n_1_0_626), .B1(n_1_0_616), .B2(registers_6__ap[24]), + .ZN(n_1_0_472) + ); + AOI22_X1_LVT i_1_0_496( + .A1(registers_4__ap[24]), .A2(n_1_0_638), .B1(n_1_0_611), .B2(registers_11__ap[24]), + .ZN(n_1_0_471) + ); + AOI22_X1_LVT i_1_0_495( + .A1(registers_10__ap[24]), .A2(n_1_0_624), .B1(n_1_0_618), .B2(registers_2__ap[24]), + .ZN(n_1_0_470) + ); + NAND4_X1_LVT i_1_0_494( + .A1(n_1_0_473), .A2(n_1_0_472), .A3(n_1_0_471), .A4(n_1_0_470), .ZN(n_1_0_469) + ); + AOI22_X1_LVT i_1_0_493( + .A1(registers_18__ap[24]), .A2(n_1_0_646), .B1(n_1_0_633), .B2(registers_19__ap[24]), + .ZN(n_1_0_468) + ); + AOI22_X1_LVT i_1_0_492( + .A1(registers_5__ap[24]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[24]), + .ZN(n_1_0_467) + ); + AOI22_X1_LVT i_1_0_491( + .A1(registers_15__ap[24]), .A2(n_1_0_627), .B1(n_1_0_614), .B2(registers_16__ap[24]), + .ZN(n_1_0_466) + ); + AOI22_X1_LVT i_1_0_490( + .A1(registers_22__ap[24]), .A2(n_1_0_642), .B1(n_1_0_620), .B2(registers_25__ap[24]), + .ZN(n_1_0_465) + ); + NAND4_X1_LVT i_1_0_489( + .A1(n_1_0_468), .A2(n_1_0_467), .A3(n_1_0_466), .A4(n_1_0_465), .ZN(n_1_0_464) + ); + AOI22_X1_LVT i_1_0_488( + .A1(registers_29__ap[24]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[24]), + .ZN(n_1_0_463) + ); + AOI22_X1_LVT i_1_0_487( + .A1(registers_7__ap[24]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[24]), + .ZN(n_1_0_462) + ); + AOI22_X1_LVT i_1_0_486( + .A1(registers_23__ap[24]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[24]), + .ZN(n_1_0_461) + ); + AOI22_X1_LVT i_1_0_485( + .A1(registers_31__ap[24]), .A2(n_1_0_637), .B1(n_1_0_636), .B2(registers_27__ap[24]), + .ZN(n_1_0_460) + ); + NAND4_X1_LVT i_1_0_484( + .A1(n_1_0_463), .A2(n_1_0_462), .A3(n_1_0_461), .A4(n_1_0_460), .ZN(n_1_0_459) + ); + NOR3_X1_LVT i_1_0_483( + .A1(n_1_0_469), .A2(n_1_0_464), .A3(n_1_0_459), .ZN(n_1_0_458) + ); + NAND4_X1_LVT i_1_0_482( + .A1(n_1_0_476), .A2(n_1_0_475), .A3(n_1_0_474), .A4(n_1_0_458), .ZN(RRs2[24]) + ); + AOI22_X1_LVT i_1_0_481( + .A1(registers_4__ap[23]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[23]), + .ZN(n_1_0_457) + ); + AOI222_X1_LVT i_1_0_480( + .A1(registers_18__ap[23]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[23]), + .C1(n_1_0_644), .C2(registers_1__ap[23]), .ZN(n_1_0_456) + ); + AOI22_X1_LVT i_1_0_479( + .A1(registers_29__ap[23]), .A2(n_1_0_649), .B1(n_1_0_618), .B2(registers_2__ap[23]), + .ZN(n_1_0_455) + ); + AOI22_X1_LVT i_1_0_478( + .A1(registers_14__ap[23]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[23]), + .ZN(n_1_0_454) + ); + AOI22_X1_LVT i_1_0_477( + .A1(registers_16__ap[23]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[23]), + .ZN(n_1_0_453) + ); + AOI22_X1_LVT i_1_0_476( + .A1(registers_27__ap[23]), .A2(n_1_0_636), .B1(n_1_0_620), .B2(registers_25__ap[23]), + .ZN(n_1_0_452) + ); + AOI22_X1_LVT i_1_0_475( + .A1(registers_31__ap[23]), .A2(n_1_0_637), .B1(n_1_0_616), .B2(registers_6__ap[23]), + .ZN(n_1_0_451) + ); + NAND4_X1_LVT i_1_0_474( + .A1(n_1_0_454), .A2(n_1_0_453), .A3(n_1_0_452), .A4(n_1_0_451), .ZN(n_1_0_450) + ); + AOI22_X1_LVT i_1_0_473( + .A1(registers_26__ap[23]), .A2(n_1_0_640), .B1(n_1_0_633), .B2(registers_19__ap[23]), + .ZN(n_1_0_449) + ); + AOI22_X1_LVT i_1_0_472( + .A1(registers_12__ap[23]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[23]), + .ZN(n_1_0_448) + ); + AOI22_X1_LVT i_1_0_471( + .A1(registers_22__ap[23]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[23]), + .ZN(n_1_0_447) + ); + AOI22_X1_LVT i_1_0_470( + .A1(registers_5__ap[23]), .A2(n_1_0_635), .B1(n_1_0_613), .B2(registers_20__ap[23]), + .ZN(n_1_0_446) + ); + NAND4_X1_LVT i_1_0_469( + .A1(n_1_0_449), .A2(n_1_0_448), .A3(n_1_0_447), .A4(n_1_0_446), .ZN(n_1_0_445) + ); + AOI22_X1_LVT i_1_0_468( + .A1(registers_15__ap[23]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[23]), + .ZN(n_1_0_444) + ); + AOI22_X1_LVT i_1_0_467( + .A1(registers_8__ap[23]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[23]), + .ZN(n_1_0_443) + ); + AOI22_X1_LVT i_1_0_466( + .A1(registers_13__ap[23]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[23]), + .ZN(n_1_0_442) + ); + AOI22_X1_LVT i_1_0_465( + .A1(registers_10__ap[23]), .A2(n_1_0_624), .B1(n_1_0_610), .B2(registers_3__ap[23]), + .ZN(n_1_0_441) + ); + NAND4_X1_LVT i_1_0_464( + .A1(n_1_0_444), .A2(n_1_0_443), .A3(n_1_0_442), .A4(n_1_0_441), .ZN(n_1_0_440) + ); + NOR3_X1_LVT i_1_0_463( + .A1(n_1_0_450), .A2(n_1_0_445), .A3(n_1_0_440), .ZN(n_1_0_439) + ); + NAND4_X1_LVT i_1_0_462( + .A1(n_1_0_457), .A2(n_1_0_456), .A3(n_1_0_455), .A4(n_1_0_439), .ZN(RRs2[23]) + ); + AOI22_X1_LVT i_1_0_460( + .A1(registers_17__ap[22]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[22]), + .ZN(n_1_0_437) + ); + AOI22_X1_LVT i_1_0_461( + .A1(registers_15__ap[22]), .A2(n_1_0_627), .B1(n_1_0_626), .B2(registers_8__ap[22]), + .ZN(n_1_0_438) + ); + AOI22_X1_LVT i_1_0_459( + .A1(registers_24__ap[22]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[22]), + .ZN(n_1_0_436) + ); + AOI22_X1_LVT i_1_0_458( + .A1(registers_5__ap[22]), .A2(n_1_0_635), .B1(n_1_0_611), .B2(registers_11__ap[22]), + .ZN(n_1_0_435) + ); + NAND3_X1_LVT i_1_0_457( + .A1(n_1_0_438), .A2(n_1_0_436), .A3(n_1_0_435), .ZN(n_1_0_434) + ); + AOI221_X1_LVT i_1_0_456( + .A(n_1_0_434), .B1(n_1_0_618), .B2(registers_2__ap[22]), .C1(registers_10__ap[22]), + .C2(n_1_0_624), .ZN(n_1_0_433) + ); + AOI222_X1_LVT i_1_0_455( + .A1(registers_26__ap[22]), .A2(n_1_0_640), .B1(n_1_0_622), .B2(registers_30__ap[22]), + .C1(n_1_0_631), .C2(registers_13__ap[22]), .ZN(n_1_0_432) + ); + NAND2_X1_LVT i_1_0_454( + .A1(n_1_0_433), .A2(n_1_0_432), .ZN(n_1_0_431) + ); + AOI221_X1_LVT i_1_0_453( + .A(n_1_0_431), .B1(n_1_0_644), .B2(registers_1__ap[22]), .C1(registers_28__ap[22]), + .C2(n_1_0_634), .ZN(n_1_0_430) + ); + AOI22_X1_LVT i_1_0_452( + .A1(registers_18__ap[22]), .A2(n_1_0_646), .B1(n_1_0_633), .B2(registers_19__ap[22]), + .ZN(n_1_0_429) + ); + AOI22_X1_LVT i_1_0_451( + .A1(registers_4__ap[22]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[22]), + .ZN(n_1_0_428) + ); + AOI22_X1_LVT i_1_0_450( + .A1(registers_6__ap[22]), .A2(n_1_0_616), .B1(n_1_0_614), .B2(registers_16__ap[22]), + .ZN(n_1_0_427) + ); + NAND3_X1_LVT i_1_0_449( + .A1(n_1_0_429), .A2(n_1_0_428), .A3(n_1_0_427), .ZN(n_1_0_426) + ); + AOI221_X1_LVT i_1_0_448( + .A(n_1_0_426), .B1(n_1_0_620), .B2(registers_25__ap[22]), .C1(registers_22__ap[22]), + .C2(n_1_0_642), .ZN(n_1_0_425) + ); + AOI22_X1_LVT i_1_0_447( + .A1(registers_29__ap[22]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[22]), + .ZN(n_1_0_424) + ); + AOI22_X1_LVT i_1_0_446( + .A1(registers_7__ap[22]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[22]), + .ZN(n_1_0_423) + ); + AOI22_X1_LVT i_1_0_445( + .A1(registers_23__ap[22]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[22]), + .ZN(n_1_0_422) + ); + NAND3_X1_LVT i_1_0_444( + .A1(n_1_0_424), .A2(n_1_0_423), .A3(n_1_0_422), .ZN(n_1_0_421) + ); + AOI221_X1_LVT i_1_0_443( + .A(n_1_0_421), .B1(n_1_0_636), .B2(registers_27__ap[22]), .C1(registers_31__ap[22]), + .C2(n_1_0_637), .ZN(n_1_0_420) + ); + NAND4_X1_LVT i_1_0_442( + .A1(n_1_0_437), .A2(n_1_0_430), .A3(n_1_0_425), .A4(n_1_0_420), .ZN(RRs2[22]) + ); + AOI22_X1_LVT i_1_0_441( + .A1(registers_5__ap[21]), .A2(n_1_0_635), .B1(n_1_0_634), .B2(registers_28__ap[21]), + .ZN(n_1_0_419) + ); + AOI222_X1_LVT i_1_0_440( + .A1(registers_1__ap[21]), .A2(n_1_0_644), .B1(n_1_0_640), .B2(registers_26__ap[21]), + .C1(n_1_0_622), .C2(registers_30__ap[21]), .ZN(n_1_0_418) + ); + AOI22_X1_LVT i_1_0_439( + .A1(registers_29__ap[21]), .A2(n_1_0_649), .B1(n_1_0_618), .B2(registers_2__ap[21]), + .ZN(n_1_0_417) + ); + AOI22_X1_LVT i_1_0_438( + .A1(registers_14__ap[21]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[21]), + .ZN(n_1_0_416) + ); + AOI22_X1_LVT i_1_0_437( + .A1(registers_8__ap[21]), .A2(n_1_0_626), .B1(n_1_0_614), .B2(registers_16__ap[21]), + .ZN(n_1_0_415) + ); + AOI22_X1_LVT i_1_0_436( + .A1(registers_25__ap[21]), .A2(n_1_0_620), .B1(n_1_0_611), .B2(registers_11__ap[21]), + .ZN(n_1_0_414) + ); + AOI22_X1_LVT i_1_0_435( + .A1(registers_10__ap[21]), .A2(n_1_0_624), .B1(n_1_0_616), .B2(registers_6__ap[21]), + .ZN(n_1_0_413) + ); + NAND4_X1_LVT i_1_0_434( + .A1(n_1_0_416), .A2(n_1_0_415), .A3(n_1_0_414), .A4(n_1_0_413), .ZN(n_1_0_412) + ); + AOI22_X1_LVT i_1_0_433( + .A1(registers_12__ap[21]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[21]), + .ZN(n_1_0_411) + ); + AOI22_X1_LVT i_1_0_432( + .A1(registers_22__ap[21]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[21]), + .ZN(n_1_0_410) + ); + AOI22_X1_LVT i_1_0_431( + .A1(registers_4__ap[21]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[21]), + .ZN(n_1_0_409) + ); + AOI22_X1_LVT i_1_0_430( + .A1(registers_18__ap[21]), .A2(n_1_0_646), .B1(n_1_0_633), .B2(registers_19__ap[21]), + .ZN(n_1_0_408) + ); + NAND4_X1_LVT i_1_0_429( + .A1(n_1_0_411), .A2(n_1_0_410), .A3(n_1_0_409), .A4(n_1_0_408), .ZN(n_1_0_407) + ); + AOI22_X1_LVT i_1_0_428( + .A1(registers_15__ap[21]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[21]), + .ZN(n_1_0_406) + ); + AOI22_X1_LVT i_1_0_427( + .A1(registers_23__ap[21]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[21]), + .ZN(n_1_0_405) + ); + AOI22_X1_LVT i_1_0_426( + .A1(registers_13__ap[21]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[21]), + .ZN(n_1_0_404) + ); + AOI22_X1_LVT i_1_0_425( + .A1(registers_31__ap[21]), .A2(n_1_0_637), .B1(n_1_0_636), .B2(registers_27__ap[21]), + .ZN(n_1_0_403) + ); + NAND4_X1_LVT i_1_0_424( + .A1(n_1_0_406), .A2(n_1_0_405), .A3(n_1_0_404), .A4(n_1_0_403), .ZN(n_1_0_402) + ); + NOR3_X1_LVT i_1_0_423( + .A1(n_1_0_412), .A2(n_1_0_407), .A3(n_1_0_402), .ZN(n_1_0_401) + ); + NAND4_X1_LVT i_1_0_422( + .A1(n_1_0_419), .A2(n_1_0_418), .A3(n_1_0_417), .A4(n_1_0_401), .ZN(RRs2[21]) + ); + AOI22_X1_LVT i_1_0_421( + .A1(registers_17__ap[20]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[20]), + .ZN(n_1_0_400) + ); + AOI222_X1_LVT i_1_0_420( + .A1(registers_13__ap[20]), .A2(n_1_0_631), .B1(n_1_0_622), .B2(registers_30__ap[20]), + .C1(registers_19__ap[20]), .C2(n_1_0_633), .ZN(n_1_0_399) + ); + AOI22_X1_LVT i_1_0_419( + .A1(registers_1__ap[20]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[20]), + .ZN(n_1_0_398) + ); + AOI22_X1_LVT i_1_0_418( + .A1(registers_24__ap[20]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[20]), + .ZN(n_1_0_397) + ); + AOI22_X1_LVT i_1_0_417( + .A1(registers_6__ap[20]), .A2(n_1_0_616), .B1(n_1_0_611), .B2(registers_11__ap[20]), + .ZN(n_1_0_396) + ); + AOI22_X1_LVT i_1_0_416( + .A1(registers_4__ap[20]), .A2(n_1_0_638), .B1(n_1_0_624), .B2(registers_10__ap[20]), + .ZN(n_1_0_395) + ); + AOI22_X1_LVT i_1_0_415( + .A1(registers_31__ap[20]), .A2(n_1_0_637), .B1(n_1_0_618), .B2(registers_2__ap[20]), + .ZN(n_1_0_394) + ); + NAND4_X1_LVT i_1_0_414( + .A1(n_1_0_397), .A2(n_1_0_396), .A3(n_1_0_395), .A4(n_1_0_394), .ZN(n_1_0_393) + ); + AOI22_X1_LVT i_1_0_413( + .A1(registers_18__ap[20]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[20]), + .ZN(n_1_0_392) + ); + AOI22_X1_LVT i_1_0_412( + .A1(registers_5__ap[20]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[20]), + .ZN(n_1_0_391) + ); + AOI22_X1_LVT i_1_0_411( + .A1(registers_15__ap[20]), .A2(n_1_0_627), .B1(n_1_0_614), .B2(registers_16__ap[20]), + .ZN(n_1_0_390) + ); + AOI22_X1_LVT i_1_0_410( + .A1(registers_22__ap[20]), .A2(n_1_0_642), .B1(n_1_0_620), .B2(registers_25__ap[20]), + .ZN(n_1_0_389) + ); + NAND4_X1_LVT i_1_0_409( + .A1(n_1_0_392), .A2(n_1_0_391), .A3(n_1_0_390), .A4(n_1_0_389), .ZN(n_1_0_388) + ); + AOI22_X1_LVT i_1_0_408( + .A1(registers_29__ap[20]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[20]), + .ZN(n_1_0_387) + ); + AOI22_X1_LVT i_1_0_407( + .A1(registers_7__ap[20]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[20]), + .ZN(n_1_0_386) + ); + AOI22_X1_LVT i_1_0_406( + .A1(registers_8__ap[20]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[20]), + .ZN(n_1_0_385) + ); + AOI22_X1_LVT i_1_0_405( + .A1(registers_27__ap[20]), .A2(n_1_0_636), .B1(n_1_0_610), .B2(registers_3__ap[20]), + .ZN(n_1_0_384) + ); + NAND4_X1_LVT i_1_0_404( + .A1(n_1_0_387), .A2(n_1_0_386), .A3(n_1_0_385), .A4(n_1_0_384), .ZN(n_1_0_383) + ); + NOR3_X1_LVT i_1_0_403( + .A1(n_1_0_393), .A2(n_1_0_388), .A3(n_1_0_383), .ZN(n_1_0_382) + ); + NAND4_X1_LVT i_1_0_402( + .A1(n_1_0_400), .A2(n_1_0_399), .A3(n_1_0_398), .A4(n_1_0_382), .ZN(RRs2[20]) + ); + AOI22_X1_LVT i_1_0_401( + .A1(registers_17__ap[19]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[19]), + .ZN(n_1_0_381) + ); + AOI222_X1_LVT i_1_0_400( + .A1(registers_13__ap[19]), .A2(n_1_0_631), .B1(n_1_0_622), .B2(registers_30__ap[19]), + .C1(registers_19__ap[19]), .C2(n_1_0_633), .ZN(n_1_0_380) + ); + AOI22_X1_LVT i_1_0_399( + .A1(registers_1__ap[19]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[19]), + .ZN(n_1_0_379) + ); + AOI22_X1_LVT i_1_0_398( + .A1(registers_24__ap[19]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[19]), + .ZN(n_1_0_378) + ); + AOI22_X1_LVT i_1_0_397( + .A1(registers_15__ap[19]), .A2(n_1_0_627), .B1(n_1_0_611), .B2(registers_11__ap[19]), + .ZN(n_1_0_377) + ); + AOI22_X1_LVT i_1_0_396( + .A1(registers_4__ap[19]), .A2(n_1_0_638), .B1(n_1_0_636), .B2(registers_27__ap[19]), + .ZN(n_1_0_376) + ); + AOI22_X1_LVT i_1_0_395( + .A1(registers_31__ap[19]), .A2(n_1_0_637), .B1(n_1_0_618), .B2(registers_2__ap[19]), + .ZN(n_1_0_375) + ); + NAND4_X1_LVT i_1_0_394( + .A1(n_1_0_378), .A2(n_1_0_377), .A3(n_1_0_376), .A4(n_1_0_375), .ZN(n_1_0_374) + ); + AOI22_X1_LVT i_1_0_393( + .A1(registers_18__ap[19]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[19]), + .ZN(n_1_0_373) + ); + AOI22_X1_LVT i_1_0_392( + .A1(registers_5__ap[19]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[19]), + .ZN(n_1_0_372) + ); + AOI22_X1_LVT i_1_0_391( + .A1(registers_25__ap[19]), .A2(n_1_0_620), .B1(n_1_0_616), .B2(registers_6__ap[19]), + .ZN(n_1_0_371) + ); + AOI22_X1_LVT i_1_0_390( + .A1(registers_22__ap[19]), .A2(n_1_0_642), .B1(n_1_0_614), .B2(registers_16__ap[19]), + .ZN(n_1_0_370) + ); + NAND4_X1_LVT i_1_0_389( + .A1(n_1_0_373), .A2(n_1_0_372), .A3(n_1_0_371), .A4(n_1_0_370), .ZN(n_1_0_369) + ); + AOI22_X1_LVT i_1_0_388( + .A1(registers_29__ap[19]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[19]), + .ZN(n_1_0_368) + ); + AOI22_X1_LVT i_1_0_387( + .A1(registers_7__ap[19]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[19]), + .ZN(n_1_0_367) + ); + AOI22_X1_LVT i_1_0_386( + .A1(registers_8__ap[19]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[19]), + .ZN(n_1_0_366) + ); + AOI22_X1_LVT i_1_0_385( + .A1(registers_10__ap[19]), .A2(n_1_0_624), .B1(n_1_0_610), .B2(registers_3__ap[19]), + .ZN(n_1_0_365) + ); + NAND4_X1_LVT i_1_0_384( + .A1(n_1_0_368), .A2(n_1_0_367), .A3(n_1_0_366), .A4(n_1_0_365), .ZN(n_1_0_364) + ); + NOR3_X1_LVT i_1_0_383( + .A1(n_1_0_374), .A2(n_1_0_369), .A3(n_1_0_364), .ZN(n_1_0_363) + ); + NAND4_X1_LVT i_1_0_382( + .A1(n_1_0_381), .A2(n_1_0_380), .A3(n_1_0_379), .A4(n_1_0_363), .ZN(RRs2[19]) + ); + AOI22_X1_LVT i_1_0_380( + .A1(registers_4__ap[18]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[18]), + .ZN(n_1_0_361) + ); + AOI22_X1_LVT i_1_0_381( + .A1(registers_8__ap[18]), .A2(n_1_0_626), .B1(n_1_0_614), .B2(registers_16__ap[18]), + .ZN(n_1_0_362) + ); + AOI22_X1_LVT i_1_0_379( + .A1(registers_14__ap[18]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[18]), + .ZN(n_1_0_360) + ); + AOI22_X1_LVT i_1_0_378( + .A1(registers_25__ap[18]), .A2(n_1_0_620), .B1(n_1_0_611), .B2(registers_11__ap[18]), + .ZN(n_1_0_359) + ); + NAND3_X1_LVT i_1_0_377( + .A1(n_1_0_362), .A2(n_1_0_360), .A3(n_1_0_359), .ZN(n_1_0_358) + ); + AOI221_X1_LVT i_1_0_376( + .A(n_1_0_358), .B1(n_1_0_624), .B2(registers_10__ap[18]), .C1(registers_6__ap[18]), + .C2(n_1_0_616), .ZN(n_1_0_357) + ); + AOI222_X1_LVT i_1_0_375( + .A1(registers_1__ap[18]), .A2(n_1_0_644), .B1(n_1_0_640), .B2(registers_26__ap[18]), + .C1(n_1_0_622), .C2(registers_30__ap[18]), .ZN(n_1_0_356) + ); + NAND2_X1_LVT i_1_0_374( + .A1(n_1_0_357), .A2(n_1_0_356), .ZN(n_1_0_355) + ); + AOI221_X1_LVT i_1_0_373( + .A(n_1_0_355), .B1(n_1_0_649), .B2(registers_29__ap[18]), .C1(registers_2__ap[18]), + .C2(n_1_0_618), .ZN(n_1_0_354) + ); + AOI22_X1_LVT i_1_0_372( + .A1(registers_18__ap[18]), .A2(n_1_0_646), .B1(n_1_0_633), .B2(registers_19__ap[18]), + .ZN(n_1_0_353) + ); + AOI22_X1_LVT i_1_0_371( + .A1(registers_12__ap[18]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[18]), + .ZN(n_1_0_352) + ); + AOI22_X1_LVT i_1_0_370( + .A1(registers_22__ap[18]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[18]), + .ZN(n_1_0_351) + ); + NAND3_X1_LVT i_1_0_369( + .A1(n_1_0_353), .A2(n_1_0_352), .A3(n_1_0_351), .ZN(n_1_0_350) + ); + AOI221_X1_LVT i_1_0_368( + .A(n_1_0_350), .B1(n_1_0_635), .B2(registers_5__ap[18]), .C1(registers_20__ap[18]), + .C2(n_1_0_613), .ZN(n_1_0_349) + ); + AOI22_X1_LVT i_1_0_367( + .A1(registers_15__ap[18]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[18]), + .ZN(n_1_0_348) + ); + AOI22_X1_LVT i_1_0_366( + .A1(registers_23__ap[18]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[18]), + .ZN(n_1_0_347) + ); + AOI22_X1_LVT i_1_0_365( + .A1(registers_13__ap[18]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[18]), + .ZN(n_1_0_346) + ); + NAND3_X1_LVT i_1_0_364( + .A1(n_1_0_348), .A2(n_1_0_347), .A3(n_1_0_346), .ZN(n_1_0_345) + ); + AOI221_X1_LVT i_1_0_363( + .A(n_1_0_345), .B1(n_1_0_637), .B2(registers_31__ap[18]), .C1(registers_27__ap[18]), + .C2(n_1_0_636), .ZN(n_1_0_344) + ); + NAND4_X1_LVT i_1_0_362( + .A1(n_1_0_361), .A2(n_1_0_354), .A3(n_1_0_349), .A4(n_1_0_344), .ZN(RRs2[18]) + ); + AOI22_X1_LVT i_1_0_358( + .A1(registers_4__ap[17]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[17]), + .ZN(n_1_0_340) + ); + AOI22_X1_LVT i_1_0_361( + .A1(registers_31__ap[17]), .A2(n_1_0_637), .B1(n_1_0_616), .B2(registers_6__ap[17]), + .ZN(n_1_0_343) + ); + AOI22_X1_LVT i_1_0_357( + .A1(registers_14__ap[17]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[17]), + .ZN(n_1_0_339) + ); + AOI22_X1_LVT i_1_0_360( + .A1(registers_25__ap[17]), .A2(n_1_0_620), .B1(n_1_0_611), .B2(registers_11__ap[17]), + .ZN(n_1_0_342) + ); + INV_X1_LVT i_1_0_359( + .A(n_1_0_342), .ZN(n_1_0_341) + ); + AOI221_X1_LVT i_1_0_356( + .A(n_1_0_341), .B1(n_1_0_614), .B2(registers_16__ap[17]), .C1(registers_10__ap[17]), + .C2(n_1_0_624), .ZN(n_1_0_338) + ); + AOI222_X1_LVT i_1_0_355( + .A1(registers_1__ap[17]), .A2(n_1_0_644), .B1(n_1_0_622), .B2(registers_30__ap[17]), + .C1(registers_18__ap[17]), .C2(n_1_0_646), .ZN(n_1_0_337) + ); + NAND4_X1_LVT i_1_0_354( + .A1(n_1_0_343), .A2(n_1_0_339), .A3(n_1_0_338), .A4(n_1_0_337), .ZN(n_1_0_336) + ); + AOI221_X1_LVT i_1_0_353( + .A(n_1_0_336), .B1(n_1_0_649), .B2(registers_29__ap[17]), .C1(registers_2__ap[17]), + .C2(n_1_0_618), .ZN(n_1_0_335) + ); + AOI22_X1_LVT i_1_0_352( + .A1(registers_26__ap[17]), .A2(n_1_0_640), .B1(n_1_0_633), .B2(registers_19__ap[17]), + .ZN(n_1_0_334) + ); + AOI22_X1_LVT i_1_0_351( + .A1(registers_12__ap[17]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[17]), + .ZN(n_1_0_333) + ); + AOI22_X1_LVT i_1_0_350( + .A1(registers_22__ap[17]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[17]), + .ZN(n_1_0_332) + ); + NAND3_X1_LVT i_1_0_349( + .A1(n_1_0_334), .A2(n_1_0_333), .A3(n_1_0_332), .ZN(n_1_0_331) + ); + AOI221_X1_LVT i_1_0_348( + .A(n_1_0_331), .B1(n_1_0_635), .B2(registers_5__ap[17]), .C1(registers_20__ap[17]), + .C2(n_1_0_613), .ZN(n_1_0_330) + ); + AOI22_X1_LVT i_1_0_347( + .A1(registers_15__ap[17]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[17]), + .ZN(n_1_0_329) + ); + AOI22_X1_LVT i_1_0_346( + .A1(registers_8__ap[17]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[17]), + .ZN(n_1_0_328) + ); + AOI22_X1_LVT i_1_0_345( + .A1(registers_13__ap[17]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[17]), + .ZN(n_1_0_327) + ); + NAND3_X1_LVT i_1_0_344( + .A1(n_1_0_329), .A2(n_1_0_328), .A3(n_1_0_327), .ZN(n_1_0_326) + ); + AOI221_X1_LVT i_1_0_343( + .A(n_1_0_326), .B1(n_1_0_636), .B2(registers_27__ap[17]), .C1(registers_3__ap[17]), + .C2(n_1_0_610), .ZN(n_1_0_325) + ); + NAND4_X1_LVT i_1_0_342( + .A1(n_1_0_340), .A2(n_1_0_335), .A3(n_1_0_330), .A4(n_1_0_325), .ZN(RRs2[17]) + ); + AOI22_X1_LVT i_1_0_341( + .A1(registers_4__ap[16]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[16]), + .ZN(n_1_0_324) + ); + AOI222_X1_LVT i_1_0_340( + .A1(registers_1__ap[16]), .A2(n_1_0_644), .B1(n_1_0_633), .B2(registers_19__ap[16]), + .C1(n_1_0_622), .C2(registers_30__ap[16]), .ZN(n_1_0_323) + ); + AOI22_X1_LVT i_1_0_339( + .A1(registers_29__ap[16]), .A2(n_1_0_649), .B1(n_1_0_618), .B2(registers_2__ap[16]), + .ZN(n_1_0_322) + ); + AOI22_X1_LVT i_1_0_338( + .A1(registers_14__ap[16]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[16]), + .ZN(n_1_0_321) + ); + AOI22_X1_LVT i_1_0_337( + .A1(registers_16__ap[16]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[16]), + .ZN(n_1_0_320) + ); + AOI22_X1_LVT i_1_0_336( + .A1(registers_10__ap[16]), .A2(n_1_0_624), .B1(n_1_0_620), .B2(registers_25__ap[16]), + .ZN(n_1_0_319) + ); + AOI22_X1_LVT i_1_0_335( + .A1(registers_31__ap[16]), .A2(n_1_0_637), .B1(n_1_0_616), .B2(registers_6__ap[16]), + .ZN(n_1_0_318) + ); + NAND4_X1_LVT i_1_0_334( + .A1(n_1_0_321), .A2(n_1_0_320), .A3(n_1_0_319), .A4(n_1_0_318), .ZN(n_1_0_317) + ); + AOI22_X1_LVT i_1_0_333( + .A1(registers_18__ap[16]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[16]), + .ZN(n_1_0_316) + ); + AOI22_X1_LVT i_1_0_332( + .A1(registers_12__ap[16]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[16]), + .ZN(n_1_0_315) + ); + AOI22_X1_LVT i_1_0_331( + .A1(registers_22__ap[16]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[16]), + .ZN(n_1_0_314) + ); + AOI22_X1_LVT i_1_0_330( + .A1(registers_5__ap[16]), .A2(n_1_0_635), .B1(n_1_0_613), .B2(registers_20__ap[16]), + .ZN(n_1_0_313) + ); + NAND4_X1_LVT i_1_0_329( + .A1(n_1_0_316), .A2(n_1_0_315), .A3(n_1_0_314), .A4(n_1_0_313), .ZN(n_1_0_312) + ); + AOI22_X1_LVT i_1_0_328( + .A1(registers_15__ap[16]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[16]), + .ZN(n_1_0_311) + ); + AOI22_X1_LVT i_1_0_327( + .A1(registers_8__ap[16]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[16]), + .ZN(n_1_0_310) + ); + AOI22_X1_LVT i_1_0_326( + .A1(registers_13__ap[16]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[16]), + .ZN(n_1_0_309) + ); + AOI22_X1_LVT i_1_0_325( + .A1(registers_27__ap[16]), .A2(n_1_0_636), .B1(n_1_0_610), .B2(registers_3__ap[16]), + .ZN(n_1_0_308) + ); + NAND4_X1_LVT i_1_0_324( + .A1(n_1_0_311), .A2(n_1_0_310), .A3(n_1_0_309), .A4(n_1_0_308), .ZN(n_1_0_307) + ); + NOR3_X1_LVT i_1_0_323( + .A1(n_1_0_317), .A2(n_1_0_312), .A3(n_1_0_307), .ZN(n_1_0_306) + ); + NAND4_X1_LVT i_1_0_322( + .A1(n_1_0_324), .A2(n_1_0_323), .A3(n_1_0_322), .A4(n_1_0_306), .ZN(RRs2[16]) + ); + AOI22_X1_LVT i_1_0_320( + .A1(registers_5__ap[15]), .A2(n_1_0_635), .B1(n_1_0_634), .B2(registers_28__ap[15]), + .ZN(n_1_0_304) + ); + AOI22_X1_LVT i_1_0_321( + .A1(registers_8__ap[15]), .A2(n_1_0_626), .B1(n_1_0_620), .B2(registers_25__ap[15]), + .ZN(n_1_0_305) + ); + AOI22_X1_LVT i_1_0_319( + .A1(registers_14__ap[15]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[15]), + .ZN(n_1_0_303) + ); + AOI22_X1_LVT i_1_0_318( + .A1(registers_16__ap[15]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[15]), + .ZN(n_1_0_302) + ); + NAND3_X1_LVT i_1_0_317( + .A1(n_1_0_305), .A2(n_1_0_303), .A3(n_1_0_302), .ZN(n_1_0_301) + ); + AOI221_X1_LVT i_1_0_316( + .A(n_1_0_301), .B1(n_1_0_616), .B2(registers_6__ap[15]), .C1(registers_10__ap[15]), + .C2(n_1_0_624), .ZN(n_1_0_300) + ); + AOI222_X1_LVT i_1_0_315( + .A1(registers_1__ap[15]), .A2(n_1_0_644), .B1(n_1_0_640), .B2(registers_26__ap[15]), + .C1(n_1_0_622), .C2(registers_30__ap[15]), .ZN(n_1_0_299) + ); + NAND2_X1_LVT i_1_0_314( + .A1(n_1_0_300), .A2(n_1_0_299), .ZN(n_1_0_298) + ); + AOI221_X1_LVT i_1_0_313( + .A(n_1_0_298), .B1(n_1_0_649), .B2(registers_29__ap[15]), .C1(registers_2__ap[15]), + .C2(n_1_0_618), .ZN(n_1_0_297) + ); + AOI22_X1_LVT i_1_0_312( + .A1(registers_12__ap[15]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[15]), + .ZN(n_1_0_296) + ); + AOI22_X1_LVT i_1_0_311( + .A1(registers_22__ap[15]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[15]), + .ZN(n_1_0_295) + ); + AOI22_X1_LVT i_1_0_310( + .A1(registers_4__ap[15]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[15]), + .ZN(n_1_0_294) + ); + NAND3_X1_LVT i_1_0_309( + .A1(n_1_0_296), .A2(n_1_0_295), .A3(n_1_0_294), .ZN(n_1_0_293) + ); + AOI221_X1_LVT i_1_0_308( + .A(n_1_0_293), .B1(n_1_0_633), .B2(registers_19__ap[15]), .C1(registers_18__ap[15]), + .C2(n_1_0_646), .ZN(n_1_0_292) + ); + AOI22_X1_LVT i_1_0_307( + .A1(registers_15__ap[15]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[15]), + .ZN(n_1_0_291) + ); + AOI22_X1_LVT i_1_0_306( + .A1(registers_23__ap[15]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[15]), + .ZN(n_1_0_290) + ); + AOI22_X1_LVT i_1_0_305( + .A1(registers_13__ap[15]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[15]), + .ZN(n_1_0_289) + ); + NAND3_X1_LVT i_1_0_304( + .A1(n_1_0_291), .A2(n_1_0_290), .A3(n_1_0_289), .ZN(n_1_0_288) + ); + AOI221_X1_LVT i_1_0_303( + .A(n_1_0_288), .B1(n_1_0_636), .B2(registers_27__ap[15]), .C1(registers_31__ap[15]), + .C2(n_1_0_637), .ZN(n_1_0_287) + ); + NAND4_X1_LVT i_1_0_302( + .A1(n_1_0_304), .A2(n_1_0_297), .A3(n_1_0_292), .A4(n_1_0_287), .ZN(RRs2[15]) + ); + AOI22_X1_LVT i_1_0_301( + .A1(registers_28__ap[14]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[14]), + .ZN(n_1_0_286) + ); + AOI222_X1_LVT i_1_0_300( + .A1(registers_18__ap[14]), .A2(n_1_0_646), .B1(n_1_0_620), .B2(registers_25__ap[14]), + .C1(n_1_0_618), .C2(registers_2__ap[14]), .ZN(n_1_0_285) + ); + AOI22_X1_LVT i_1_0_299( + .A1(registers_24__ap[14]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[14]), + .ZN(n_1_0_284) + ); + AOI22_X1_LVT i_1_0_298( + .A1(registers_15__ap[14]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[14]), + .ZN(n_1_0_283) + ); + AOI22_X1_LVT i_1_0_297( + .A1(registers_4__ap[14]), .A2(n_1_0_638), .B1(n_1_0_637), .B2(registers_31__ap[14]), + .ZN(n_1_0_282) + ); + AOI22_X1_LVT i_1_0_296( + .A1(registers_29__ap[14]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[14]), + .ZN(n_1_0_281) + ); + NAND4_X1_LVT i_1_0_295( + .A1(n_1_0_284), .A2(n_1_0_283), .A3(n_1_0_282), .A4(n_1_0_281), .ZN(n_1_0_280) + ); + AOI221_X1_LVT i_1_0_294( + .A(n_1_0_280), .B1(n_1_0_644), .B2(registers_1__ap[14]), .C1(registers_13__ap[14]), + .C2(n_1_0_631), .ZN(n_1_0_279) + ); + AOI22_X1_LVT i_1_0_293( + .A1(registers_17__ap[14]), .A2(n_1_0_629), .B1(n_1_0_623), .B2(registers_7__ap[14]), + .ZN(n_1_0_278) + ); + AOI22_X1_LVT i_1_0_292( + .A1(registers_5__ap[14]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[14]), + .ZN(n_1_0_277) + ); + AOI22_X1_LVT i_1_0_291( + .A1(registers_10__ap[14]), .A2(n_1_0_624), .B1(n_1_0_622), .B2(registers_30__ap[14]), + .ZN(n_1_0_276) + ); + AOI22_X1_LVT i_1_0_290( + .A1(registers_26__ap[14]), .A2(n_1_0_640), .B1(n_1_0_614), .B2(registers_16__ap[14]), + .ZN(n_1_0_275) + ); + NAND4_X1_LVT i_1_0_289( + .A1(n_1_0_278), .A2(n_1_0_277), .A3(n_1_0_276), .A4(n_1_0_275), .ZN(n_1_0_274) + ); + AOI22_X1_LVT i_1_0_288( + .A1(registers_9__ap[14]), .A2(n_1_0_617), .B1(n_1_0_612), .B2(registers_21__ap[14]), + .ZN(n_1_0_273) + ); + AOI22_X1_LVT i_1_0_287( + .A1(registers_14__ap[14]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[14]), + .ZN(n_1_0_272) + ); + AOI22_X1_LVT i_1_0_286( + .A1(registers_22__ap[14]), .A2(n_1_0_642), .B1(n_1_0_633), .B2(registers_19__ap[14]), + .ZN(n_1_0_271) + ); + AOI22_X1_LVT i_1_0_285( + .A1(registers_27__ap[14]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[14]), + .ZN(n_1_0_270) + ); + NAND4_X1_LVT i_1_0_284( + .A1(n_1_0_273), .A2(n_1_0_272), .A3(n_1_0_271), .A4(n_1_0_270), .ZN(n_1_0_269) + ); + NOR2_X1_LVT i_1_0_283( + .A1(n_1_0_274), .A2(n_1_0_269), .ZN(n_1_0_268) + ); + NAND4_X1_LVT i_1_0_282( + .A1(n_1_0_286), .A2(n_1_0_285), .A3(n_1_0_279), .A4(n_1_0_268), .ZN(RRs2[14]) + ); + AOI22_X1_LVT i_1_0_281( + .A1(registers_18__ap[13]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[13]), + .ZN(n_1_0_267) + ); + AOI22_X1_LVT i_1_0_280( + .A1(registers_12__ap[13]), .A2(n_1_0_632), .B1(n_1_0_629), .B2(registers_17__ap[13]), + .ZN(n_1_0_266) + ); + AOI22_X1_LVT i_1_0_279( + .A1(registers_7__ap[13]), .A2(n_1_0_623), .B1(n_1_0_614), .B2(registers_16__ap[13]), + .ZN(n_1_0_265) + ); + NAND3_X1_LVT i_1_0_277( + .A1(n_1_0_267), .A2(n_1_0_266), .A3(n_1_0_265), .ZN(n_1_0_263) + ); + AOI221_X1_LVT i_1_0_276( + .A(n_1_0_263), .B1(n_1_0_642), .B2(registers_22__ap[13]), .C1(registers_5__ap[13]), + .C2(n_1_0_635), .ZN(n_1_0_262) + ); + AOI22_X1_LVT i_1_0_278( + .A1(registers_13__ap[13]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[13]), + .ZN(n_1_0_264) + ); + AOI222_X1_LVT i_1_0_275( + .A1(registers_26__ap[13]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[13]), + .C1(n_1_0_620), .C2(registers_25__ap[13]), .ZN(n_1_0_261) + ); + AOI22_X1_LVT i_1_0_274( + .A1(registers_28__ap[13]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[13]), + .ZN(n_1_0_260) + ); + NAND3_X1_LVT i_1_0_273( + .A1(n_1_0_264), .A2(n_1_0_261), .A3(n_1_0_260), .ZN(n_1_0_259) + ); + AOI22_X1_LVT i_1_0_272( + .A1(registers_1__ap[13]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[13]), + .ZN(n_1_0_258) + ); + AOI22_X1_LVT i_1_0_271( + .A1(registers_19__ap[13]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[13]), + .ZN(n_1_0_257) + ); + AOI22_X1_LVT i_1_0_270( + .A1(registers_14__ap[13]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[13]), + .ZN(n_1_0_256) + ); + AOI22_X1_LVT i_1_0_269( + .A1(registers_27__ap[13]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[13]), + .ZN(n_1_0_255) + ); + NAND4_X1_LVT i_1_0_268( + .A1(n_1_0_258), .A2(n_1_0_257), .A3(n_1_0_256), .A4(n_1_0_255), .ZN(n_1_0_254) + ); + AOI22_X1_LVT i_1_0_267( + .A1(registers_24__ap[13]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[13]), + .ZN(n_1_0_253) + ); + AOI22_X1_LVT i_1_0_266( + .A1(registers_4__ap[13]), .A2(n_1_0_638), .B1(n_1_0_637), .B2(registers_31__ap[13]), + .ZN(n_1_0_252) + ); + AOI22_X1_LVT i_1_0_265( + .A1(registers_29__ap[13]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[13]), + .ZN(n_1_0_251) + ); + AOI22_X1_LVT i_1_0_264( + .A1(registers_15__ap[13]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[13]), + .ZN(n_1_0_250) + ); + NAND4_X1_LVT i_1_0_263( + .A1(n_1_0_253), .A2(n_1_0_252), .A3(n_1_0_251), .A4(n_1_0_250), .ZN(n_1_0_249) + ); + NOR3_X1_LVT i_1_0_262( + .A1(n_1_0_259), .A2(n_1_0_254), .A3(n_1_0_249), .ZN(n_1_0_248) + ); + NAND2_X1_LVT i_1_0_261( + .A1(n_1_0_262), .A2(n_1_0_248), .ZN(RRs2[13]) + ); + AOI22_X1_LVT i_1_0_260( + .A1(registers_18__ap[12]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[12]), + .ZN(n_1_0_247) + ); + AOI22_X1_LVT i_1_0_259( + .A1(registers_12__ap[12]), .A2(n_1_0_632), .B1(n_1_0_629), .B2(registers_17__ap[12]), + .ZN(n_1_0_246) + ); + AOI22_X1_LVT i_1_0_258( + .A1(registers_5__ap[12]), .A2(n_1_0_635), .B1(n_1_0_623), .B2(registers_7__ap[12]), + .ZN(n_1_0_245) + ); + NAND3_X1_LVT i_1_0_256( + .A1(n_1_0_247), .A2(n_1_0_246), .A3(n_1_0_245), .ZN(n_1_0_243) + ); + AOI221_X1_LVT i_1_0_255( + .A(n_1_0_243), .B1(n_1_0_642), .B2(registers_22__ap[12]), .C1(registers_16__ap[12]), + .C2(n_1_0_614), .ZN(n_1_0_242) + ); + AOI22_X1_LVT i_1_0_257( + .A1(registers_13__ap[12]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[12]), + .ZN(n_1_0_244) + ); + AOI222_X1_LVT i_1_0_254( + .A1(registers_26__ap[12]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[12]), + .C1(n_1_0_620), .C2(registers_25__ap[12]), .ZN(n_1_0_241) + ); + AOI22_X1_LVT i_1_0_253( + .A1(registers_28__ap[12]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[12]), + .ZN(n_1_0_240) + ); + NAND3_X1_LVT i_1_0_252( + .A1(n_1_0_244), .A2(n_1_0_241), .A3(n_1_0_240), .ZN(n_1_0_239) + ); + AOI22_X1_LVT i_1_0_251( + .A1(registers_1__ap[12]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[12]), + .ZN(n_1_0_238) + ); + AOI22_X1_LVT i_1_0_250( + .A1(registers_19__ap[12]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[12]), + .ZN(n_1_0_237) + ); + AOI22_X1_LVT i_1_0_249( + .A1(registers_14__ap[12]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[12]), + .ZN(n_1_0_236) + ); + AOI22_X1_LVT i_1_0_248( + .A1(registers_27__ap[12]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[12]), + .ZN(n_1_0_235) + ); + NAND4_X1_LVT i_1_0_247( + .A1(n_1_0_238), .A2(n_1_0_237), .A3(n_1_0_236), .A4(n_1_0_235), .ZN(n_1_0_234) + ); + AOI22_X1_LVT i_1_0_246( + .A1(registers_24__ap[12]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[12]), + .ZN(n_1_0_233) + ); + AOI22_X1_LVT i_1_0_245( + .A1(registers_4__ap[12]), .A2(n_1_0_638), .B1(n_1_0_637), .B2(registers_31__ap[12]), + .ZN(n_1_0_232) + ); + AOI22_X1_LVT i_1_0_244( + .A1(registers_29__ap[12]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[12]), + .ZN(n_1_0_231) + ); + AOI22_X1_LVT i_1_0_243( + .A1(registers_15__ap[12]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[12]), + .ZN(n_1_0_230) + ); + NAND4_X1_LVT i_1_0_242( + .A1(n_1_0_233), .A2(n_1_0_232), .A3(n_1_0_231), .A4(n_1_0_230), .ZN(n_1_0_229) + ); + NOR3_X1_LVT i_1_0_241( + .A1(n_1_0_239), .A2(n_1_0_234), .A3(n_1_0_229), .ZN(n_1_0_228) + ); + NAND2_X1_LVT i_1_0_240( + .A1(n_1_0_242), .A2(n_1_0_228), .ZN(RRs2[12]) + ); + AOI22_X1_LVT i_1_0_238( + .A1(registers_29__ap[11]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[11]), + .ZN(n_1_0_226) + ); + AOI22_X1_LVT i_1_0_239( + .A1(registers_27__ap[11]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[11]), + .ZN(n_1_0_227) + ); + AOI22_X1_LVT i_1_0_237( + .A1(registers_1__ap[11]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[11]), + .ZN(n_1_0_225) + ); + AOI22_X1_LVT i_1_0_236( + .A1(registers_5__ap[11]), .A2(n_1_0_635), .B1(n_1_0_615), .B2(registers_23__ap[11]), + .ZN(n_1_0_224) + ); + NAND3_X1_LVT i_1_0_235( + .A1(n_1_0_227), .A2(n_1_0_225), .A3(n_1_0_224), .ZN(n_1_0_223) + ); + AOI221_X1_LVT i_1_0_234( + .A(n_1_0_223), .B1(n_1_0_637), .B2(registers_31__ap[11]), .C1(registers_16__ap[11]), + .C2(n_1_0_614), .ZN(n_1_0_222) + ); + AOI222_X1_LVT i_1_0_233( + .A1(registers_8__ap[11]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[11]), + .C1(n_1_0_622), .C2(registers_30__ap[11]), .ZN(n_1_0_221) + ); + NAND3_X1_LVT i_1_0_232( + .A1(n_1_0_226), .A2(n_1_0_222), .A3(n_1_0_221), .ZN(n_1_0_220) + ); + AOI221_X1_LVT i_1_0_231( + .A(n_1_0_220), .B1(n_1_0_638), .B2(registers_4__ap[11]), .C1(registers_28__ap[11]), + .C2(n_1_0_634), .ZN(n_1_0_219) + ); + AOI22_X1_LVT i_1_0_230( + .A1(registers_18__ap[11]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[11]), + .ZN(n_1_0_218) + ); + AOI22_X1_LVT i_1_0_229( + .A1(registers_12__ap[11]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[11]), + .ZN(n_1_0_217) + ); + AOI22_X1_LVT i_1_0_228( + .A1(registers_22__ap[11]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[11]), + .ZN(n_1_0_216) + ); + NAND3_X1_LVT i_1_0_227( + .A1(n_1_0_218), .A2(n_1_0_217), .A3(n_1_0_216), .ZN(n_1_0_215) + ); + AOI221_X1_LVT i_1_0_226( + .A(n_1_0_215), .B1(n_1_0_613), .B2(registers_20__ap[11]), .C1(registers_17__ap[11]), + .C2(n_1_0_629), .ZN(n_1_0_214) + ); + AOI22_X1_LVT i_1_0_225( + .A1(registers_13__ap[11]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[11]), + .ZN(n_1_0_213) + ); + AOI22_X1_LVT i_1_0_224( + .A1(registers_7__ap[11]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[11]), + .ZN(n_1_0_212) + ); + AOI22_X1_LVT i_1_0_223( + .A1(registers_19__ap[11]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[11]), + .ZN(n_1_0_211) + ); + NAND3_X1_LVT i_1_0_222( + .A1(n_1_0_213), .A2(n_1_0_212), .A3(n_1_0_211), .ZN(n_1_0_210) + ); + AOI221_X1_LVT i_1_0_221( + .A(n_1_0_210), .B1(n_1_0_611), .B2(registers_11__ap[11]), .C1(registers_2__ap[11]), + .C2(n_1_0_618), .ZN(n_1_0_209) + ); + NAND3_X1_LVT i_1_0_220( + .A1(n_1_0_219), .A2(n_1_0_214), .A3(n_1_0_209), .ZN(RRs2[11]) + ); + AOI22_X1_LVT i_1_0_219( + .A1(registers_28__ap[10]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[10]), + .ZN(n_1_0_208) + ); + AOI222_X1_LVT i_1_0_218( + .A1(registers_26__ap[10]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[10]), + .C1(registers_25__ap[10]), .C2(n_1_0_620), .ZN(n_1_0_207) + ); + AOI22_X1_LVT i_1_0_217( + .A1(registers_13__ap[10]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[10]), + .ZN(n_1_0_206) + ); + AOI22_X1_LVT i_1_0_216( + .A1(registers_24__ap[10]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[10]), + .ZN(n_1_0_205) + ); + AOI22_X1_LVT i_1_0_215( + .A1(registers_15__ap[10]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[10]), + .ZN(n_1_0_204) + ); + AOI22_X1_LVT i_1_0_214( + .A1(registers_31__ap[10]), .A2(n_1_0_637), .B1(n_1_0_629), .B2(registers_17__ap[10]), + .ZN(n_1_0_203) + ); + AOI22_X1_LVT i_1_0_213( + .A1(registers_29__ap[10]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[10]), + .ZN(n_1_0_202) + ); + NAND4_X1_LVT i_1_0_212( + .A1(n_1_0_205), .A2(n_1_0_204), .A3(n_1_0_203), .A4(n_1_0_202), .ZN(n_1_0_201) + ); + AOI22_X1_LVT i_1_0_211( + .A1(registers_18__ap[10]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[10]), + .ZN(n_1_0_200) + ); + AOI22_X1_LVT i_1_0_210( + .A1(registers_4__ap[10]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[10]), + .ZN(n_1_0_199) + ); + AOI22_X1_LVT i_1_0_209( + .A1(registers_7__ap[10]), .A2(n_1_0_623), .B1(n_1_0_614), .B2(registers_16__ap[10]), + .ZN(n_1_0_198) + ); + AOI22_X1_LVT i_1_0_208( + .A1(registers_22__ap[10]), .A2(n_1_0_642), .B1(n_1_0_635), .B2(registers_5__ap[10]), + .ZN(n_1_0_197) + ); + NAND4_X1_LVT i_1_0_207( + .A1(n_1_0_200), .A2(n_1_0_199), .A3(n_1_0_198), .A4(n_1_0_197), .ZN(n_1_0_196) + ); + AOI22_X1_LVT i_1_0_206( + .A1(registers_1__ap[10]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[10]), + .ZN(n_1_0_195) + ); + AOI22_X1_LVT i_1_0_205( + .A1(registers_14__ap[10]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[10]), + .ZN(n_1_0_194) + ); + AOI22_X1_LVT i_1_0_204( + .A1(registers_19__ap[10]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[10]), + .ZN(n_1_0_193) + ); + AOI22_X1_LVT i_1_0_203( + .A1(registers_27__ap[10]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[10]), + .ZN(n_1_0_192) + ); + NAND4_X1_LVT i_1_0_202( + .A1(n_1_0_195), .A2(n_1_0_194), .A3(n_1_0_193), .A4(n_1_0_192), .ZN(n_1_0_191) + ); + NOR3_X1_LVT i_1_0_201( + .A1(n_1_0_201), .A2(n_1_0_196), .A3(n_1_0_191), .ZN(n_1_0_190) + ); + NAND4_X1_LVT i_1_0_200( + .A1(n_1_0_208), .A2(n_1_0_207), .A3(n_1_0_206), .A4(n_1_0_190), .ZN(RRs2[10]) + ); + AOI22_X1_LVT i_1_0_196( + .A1(registers_13__ap[9]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[9]), + .ZN(n_1_0_186) + ); + AOI22_X1_LVT i_1_0_199( + .A1(registers_29__ap[9]), .A2(n_1_0_649), .B1(n_1_0_636), .B2(registers_27__ap[9]), + .ZN(n_1_0_189) + ); + AOI22_X1_LVT i_1_0_195( + .A1(registers_24__ap[9]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[9]), + .ZN(n_1_0_185) + ); + AOI22_X1_LVT i_1_0_198( + .A1(registers_31__ap[9]), .A2(n_1_0_637), .B1(n_1_0_627), .B2(registers_15__ap[9]), + .ZN(n_1_0_188) + ); + INV_X1_LVT i_1_0_197( + .A(n_1_0_188), .ZN(n_1_0_187) + ); + AOI221_X1_LVT i_1_0_194( + .A(n_1_0_187), .B1(n_1_0_615), .B2(registers_23__ap[9]), .C1(registers_4__ap[9]), + .C2(n_1_0_638), .ZN(n_1_0_184) + ); + AOI222_X1_LVT i_1_0_193( + .A1(registers_18__ap[9]), .A2(n_1_0_646), .B1(n_1_0_624), .B2(registers_10__ap[9]), + .C1(registers_25__ap[9]), .C2(n_1_0_620), .ZN(n_1_0_183) + ); + NAND4_X1_LVT i_1_0_192( + .A1(n_1_0_189), .A2(n_1_0_185), .A3(n_1_0_184), .A4(n_1_0_183), .ZN(n_1_0_182) + ); + AOI221_X1_LVT i_1_0_191( + .A(n_1_0_182), .B1(n_1_0_626), .B2(registers_8__ap[9]), .C1(registers_28__ap[9]), + .C2(n_1_0_634), .ZN(n_1_0_181) + ); + AOI22_X1_LVT i_1_0_190( + .A1(registers_26__ap[9]), .A2(n_1_0_640), .B1(n_1_0_622), .B2(registers_30__ap[9]), + .ZN(n_1_0_180) + ); + AOI22_X1_LVT i_1_0_189( + .A1(registers_12__ap[9]), .A2(n_1_0_632), .B1(n_1_0_629), .B2(registers_17__ap[9]), + .ZN(n_1_0_179) + ); + AOI22_X1_LVT i_1_0_188( + .A1(registers_5__ap[9]), .A2(n_1_0_635), .B1(n_1_0_623), .B2(registers_7__ap[9]), + .ZN(n_1_0_178) + ); + NAND3_X1_LVT i_1_0_187( + .A1(n_1_0_180), .A2(n_1_0_179), .A3(n_1_0_178), .ZN(n_1_0_177) + ); + AOI221_X1_LVT i_1_0_186( + .A(n_1_0_177), .B1(n_1_0_642), .B2(registers_22__ap[9]), .C1(registers_16__ap[9]), + .C2(n_1_0_614), .ZN(n_1_0_176) + ); + AOI22_X1_LVT i_1_0_185( + .A1(registers_1__ap[9]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[9]), + .ZN(n_1_0_175) + ); + AOI22_X1_LVT i_1_0_184( + .A1(registers_14__ap[9]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[9]), + .ZN(n_1_0_174) + ); + AOI22_X1_LVT i_1_0_183( + .A1(registers_19__ap[9]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[9]), + .ZN(n_1_0_173) + ); + NAND3_X1_LVT i_1_0_182( + .A1(n_1_0_175), .A2(n_1_0_174), .A3(n_1_0_173), .ZN(n_1_0_172) + ); + AOI221_X1_LVT i_1_0_181( + .A(n_1_0_172), .B1(n_1_0_611), .B2(registers_11__ap[9]), .C1(registers_2__ap[9]), + .C2(n_1_0_618), .ZN(n_1_0_171) + ); + NAND4_X1_LVT i_1_0_180( + .A1(n_1_0_186), .A2(n_1_0_181), .A3(n_1_0_176), .A4(n_1_0_171), .ZN(RRs2[9]) + ); + AOI22_X1_LVT i_1_0_179( + .A1(registers_28__ap[8]), .A2(n_1_0_634), .B1(n_1_0_629), .B2(registers_17__ap[8]), + .ZN(n_1_0_170) + ); + AOI222_X1_LVT i_1_0_178( + .A1(registers_26__ap[8]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[8]), + .C1(n_1_0_626), .C2(registers_8__ap[8]), .ZN(n_1_0_169) + ); + AOI22_X1_LVT i_1_0_177( + .A1(registers_29__ap[8]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[8]), + .ZN(n_1_0_168) + ); + AOI22_X1_LVT i_1_0_176( + .A1(registers_1__ap[8]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[8]), + .ZN(n_1_0_167) + ); + AOI22_X1_LVT i_1_0_175( + .A1(registers_5__ap[8]), .A2(n_1_0_635), .B1(n_1_0_610), .B2(registers_3__ap[8]), + .ZN(n_1_0_166) + ); + AOI22_X1_LVT i_1_0_174( + .A1(registers_31__ap[8]), .A2(n_1_0_637), .B1(n_1_0_614), .B2(registers_16__ap[8]), + .ZN(n_1_0_165) + ); + AOI22_X1_LVT i_1_0_173( + .A1(registers_15__ap[8]), .A2(n_1_0_627), .B1(n_1_0_615), .B2(registers_23__ap[8]), + .ZN(n_1_0_164) + ); + NAND4_X1_LVT i_1_0_172( + .A1(n_1_0_167), .A2(n_1_0_166), .A3(n_1_0_165), .A4(n_1_0_164), .ZN(n_1_0_163) + ); + AOI22_X1_LVT i_1_0_171( + .A1(registers_18__ap[8]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[8]), + .ZN(n_1_0_162) + ); + AOI22_X1_LVT i_1_0_170( + .A1(registers_4__ap[8]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[8]), + .ZN(n_1_0_161) + ); + AOI22_X1_LVT i_1_0_169( + .A1(registers_22__ap[8]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[8]), + .ZN(n_1_0_160) + ); + AOI22_X1_LVT i_1_0_168( + .A1(registers_12__ap[8]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[8]), + .ZN(n_1_0_159) + ); + NAND4_X1_LVT i_1_0_167( + .A1(n_1_0_162), .A2(n_1_0_161), .A3(n_1_0_160), .A4(n_1_0_159), .ZN(n_1_0_158) + ); + AOI22_X1_LVT i_1_0_166( + .A1(registers_13__ap[8]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[8]), + .ZN(n_1_0_157) + ); + AOI22_X1_LVT i_1_0_165( + .A1(registers_7__ap[8]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[8]), + .ZN(n_1_0_156) + ); + AOI22_X1_LVT i_1_0_164( + .A1(registers_19__ap[8]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[8]), + .ZN(n_1_0_155) + ); + AOI22_X1_LVT i_1_0_163( + .A1(registers_27__ap[8]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[8]), + .ZN(n_1_0_154) + ); + NAND4_X1_LVT i_1_0_162( + .A1(n_1_0_157), .A2(n_1_0_156), .A3(n_1_0_155), .A4(n_1_0_154), .ZN(n_1_0_153) + ); + NOR3_X1_LVT i_1_0_161( + .A1(n_1_0_163), .A2(n_1_0_158), .A3(n_1_0_153), .ZN(n_1_0_152) + ); + NAND4_X1_LVT i_1_0_160( + .A1(n_1_0_170), .A2(n_1_0_169), .A3(n_1_0_168), .A4(n_1_0_152), .ZN(RRs2[8]) + ); + AOI22_X1_LVT i_1_0_159( + .A1(registers_28__ap[7]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[7]), + .ZN(n_1_0_151) + ); + AOI222_X1_LVT i_1_0_158( + .A1(registers_26__ap[7]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[7]), + .C1(registers_25__ap[7]), .C2(n_1_0_620), .ZN(n_1_0_150) + ); + AOI22_X1_LVT i_1_0_157( + .A1(registers_24__ap[7]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[7]), + .ZN(n_1_0_149) + ); + AOI22_X1_LVT i_1_0_156( + .A1(registers_15__ap[7]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[7]), + .ZN(n_1_0_148) + ); + AOI22_X1_LVT i_1_0_155( + .A1(registers_31__ap[7]), .A2(n_1_0_637), .B1(n_1_0_629), .B2(registers_17__ap[7]), + .ZN(n_1_0_147) + ); + AOI22_X1_LVT i_1_0_154( + .A1(registers_29__ap[7]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[7]), + .ZN(n_1_0_146) + ); + NAND4_X1_LVT i_1_0_153( + .A1(n_1_0_149), .A2(n_1_0_148), .A3(n_1_0_147), .A4(n_1_0_146), .ZN(n_1_0_145) + ); + AOI221_X1_LVT i_1_0_152( + .A(n_1_0_145), .B1(n_1_0_612), .B2(registers_21__ap[7]), .C1(registers_13__ap[7]), + .C2(n_1_0_631), .ZN(n_1_0_144) + ); + AOI22_X1_LVT i_1_0_151( + .A1(registers_18__ap[7]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[7]), + .ZN(n_1_0_143) + ); + AOI22_X1_LVT i_1_0_150( + .A1(registers_4__ap[7]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[7]), + .ZN(n_1_0_142) + ); + AOI22_X1_LVT i_1_0_149( + .A1(registers_5__ap[7]), .A2(n_1_0_635), .B1(n_1_0_623), .B2(registers_7__ap[7]), + .ZN(n_1_0_141) + ); + AOI22_X1_LVT i_1_0_148( + .A1(registers_22__ap[7]), .A2(n_1_0_642), .B1(n_1_0_614), .B2(registers_16__ap[7]), + .ZN(n_1_0_140) + ); + NAND4_X1_LVT i_1_0_147( + .A1(n_1_0_143), .A2(n_1_0_142), .A3(n_1_0_141), .A4(n_1_0_140), .ZN(n_1_0_139) + ); + AOI22_X1_LVT i_1_0_146( + .A1(registers_1__ap[7]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[7]), + .ZN(n_1_0_138) + ); + AOI22_X1_LVT i_1_0_145( + .A1(registers_14__ap[7]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[7]), + .ZN(n_1_0_137) + ); + AOI22_X1_LVT i_1_0_144( + .A1(registers_19__ap[7]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[7]), + .ZN(n_1_0_136) + ); + AOI22_X1_LVT i_1_0_143( + .A1(registers_27__ap[7]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[7]), + .ZN(n_1_0_135) + ); + NAND4_X1_LVT i_1_0_142( + .A1(n_1_0_138), .A2(n_1_0_137), .A3(n_1_0_136), .A4(n_1_0_135), .ZN(n_1_0_134) + ); + NOR2_X1_LVT i_1_0_141( + .A1(n_1_0_139), .A2(n_1_0_134), .ZN(n_1_0_133) + ); + NAND4_X1_LVT i_1_0_140( + .A1(n_1_0_151), .A2(n_1_0_150), .A3(n_1_0_144), .A4(n_1_0_133), .ZN(RRs2[7]) + ); + AOI22_X1_LVT i_1_0_136( + .A1(registers_13__ap[6]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[6]), + .ZN(n_1_0_129) + ); + AOI22_X1_LVT i_1_0_139( + .A1(registers_29__ap[6]), .A2(n_1_0_649), .B1(n_1_0_636), .B2(registers_27__ap[6]), + .ZN(n_1_0_132) + ); + AOI22_X1_LVT i_1_0_135( + .A1(registers_24__ap[6]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[6]), + .ZN(n_1_0_128) + ); + AOI22_X1_LVT i_1_0_138( + .A1(registers_31__ap[6]), .A2(n_1_0_637), .B1(n_1_0_627), .B2(registers_15__ap[6]), + .ZN(n_1_0_131) + ); + INV_X1_LVT i_1_0_137( + .A(n_1_0_131), .ZN(n_1_0_130) + ); + AOI221_X1_LVT i_1_0_134( + .A(n_1_0_130), .B1(n_1_0_638), .B2(registers_4__ap[6]), .C1(registers_23__ap[6]), + .C2(n_1_0_615), .ZN(n_1_0_127) + ); + AOI222_X1_LVT i_1_0_133( + .A1(registers_18__ap[6]), .A2(n_1_0_646), .B1(n_1_0_620), .B2(registers_25__ap[6]), + .C1(n_1_0_624), .C2(registers_10__ap[6]), .ZN(n_1_0_126) + ); + NAND4_X1_LVT i_1_0_132( + .A1(n_1_0_132), .A2(n_1_0_128), .A3(n_1_0_127), .A4(n_1_0_126), .ZN(n_1_0_125) + ); + AOI221_X1_LVT i_1_0_131( + .A(n_1_0_125), .B1(n_1_0_626), .B2(registers_8__ap[6]), .C1(registers_28__ap[6]), + .C2(n_1_0_634), .ZN(n_1_0_124) + ); + AOI22_X1_LVT i_1_0_130( + .A1(registers_26__ap[6]), .A2(n_1_0_640), .B1(n_1_0_622), .B2(registers_30__ap[6]), + .ZN(n_1_0_123) + ); + AOI22_X1_LVT i_1_0_129( + .A1(registers_12__ap[6]), .A2(n_1_0_632), .B1(n_1_0_629), .B2(registers_17__ap[6]), + .ZN(n_1_0_122) + ); + AOI22_X1_LVT i_1_0_128( + .A1(registers_7__ap[6]), .A2(n_1_0_623), .B1(n_1_0_614), .B2(registers_16__ap[6]), + .ZN(n_1_0_121) + ); + NAND3_X1_LVT i_1_0_127( + .A1(n_1_0_123), .A2(n_1_0_122), .A3(n_1_0_121), .ZN(n_1_0_120) + ); + AOI221_X1_LVT i_1_0_126( + .A(n_1_0_120), .B1(n_1_0_642), .B2(registers_22__ap[6]), .C1(registers_5__ap[6]), + .C2(n_1_0_635), .ZN(n_1_0_119) + ); + AOI22_X1_LVT i_1_0_125( + .A1(registers_1__ap[6]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[6]), + .ZN(n_1_0_118) + ); + AOI22_X1_LVT i_1_0_124( + .A1(registers_14__ap[6]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[6]), + .ZN(n_1_0_117) + ); + AOI22_X1_LVT i_1_0_123( + .A1(registers_19__ap[6]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[6]), + .ZN(n_1_0_116) + ); + NAND3_X1_LVT i_1_0_122( + .A1(n_1_0_118), .A2(n_1_0_117), .A3(n_1_0_116), .ZN(n_1_0_115) + ); + AOI221_X1_LVT i_1_0_121( + .A(n_1_0_115), .B1(n_1_0_618), .B2(registers_2__ap[6]), .C1(registers_11__ap[6]), + .C2(n_1_0_611), .ZN(n_1_0_114) + ); + NAND4_X1_LVT i_1_0_120( + .A1(n_1_0_129), .A2(n_1_0_124), .A3(n_1_0_119), .A4(n_1_0_114), .ZN(RRs2[6]) + ); + AOI22_X1_LVT i_1_0_118( + .A1(registers_28__ap[5]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[5]), + .ZN(n_1_0_112) + ); + AOI22_X1_LVT i_1_0_119( + .A1(registers_31__ap[5]), .A2(n_1_0_637), .B1(n_1_0_627), .B2(registers_15__ap[5]), + .ZN(n_1_0_113) + ); + AOI22_X1_LVT i_1_0_117( + .A1(registers_24__ap[5]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[5]), + .ZN(n_1_0_111) + ); + AOI22_X1_LVT i_1_0_116( + .A1(registers_17__ap[5]), .A2(n_1_0_629), .B1(n_1_0_615), .B2(registers_23__ap[5]), + .ZN(n_1_0_110) + ); + NAND3_X1_LVT i_1_0_115( + .A1(n_1_0_113), .A2(n_1_0_111), .A3(n_1_0_110), .ZN(n_1_0_109) + ); + AOI221_X1_LVT i_1_0_114( + .A(n_1_0_109), .B1(n_1_0_636), .B2(registers_27__ap[5]), .C1(registers_29__ap[5]), + .C2(n_1_0_649), .ZN(n_1_0_108) + ); + AOI222_X1_LVT i_1_0_113( + .A1(registers_10__ap[5]), .A2(n_1_0_624), .B1(n_1_0_620), .B2(registers_25__ap[5]), + .C1(registers_18__ap[5]), .C2(n_1_0_646), .ZN(n_1_0_107) + ); + NAND3_X1_LVT i_1_0_112( + .A1(n_1_0_112), .A2(n_1_0_108), .A3(n_1_0_107), .ZN(n_1_0_106) + ); + AOI221_X1_LVT i_1_0_111( + .A(n_1_0_106), .B1(n_1_0_612), .B2(registers_21__ap[5]), .C1(registers_13__ap[5]), + .C2(n_1_0_631), .ZN(n_1_0_105) + ); + AOI22_X1_LVT i_1_0_110( + .A1(registers_26__ap[5]), .A2(n_1_0_640), .B1(n_1_0_622), .B2(registers_30__ap[5]), + .ZN(n_1_0_104) + ); + AOI22_X1_LVT i_1_0_109( + .A1(registers_4__ap[5]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[5]), + .ZN(n_1_0_103) + ); + AOI22_X1_LVT i_1_0_108( + .A1(registers_5__ap[5]), .A2(n_1_0_635), .B1(n_1_0_623), .B2(registers_7__ap[5]), + .ZN(n_1_0_102) + ); + NAND3_X1_LVT i_1_0_107( + .A1(n_1_0_104), .A2(n_1_0_103), .A3(n_1_0_102), .ZN(n_1_0_101) + ); + AOI221_X1_LVT i_1_0_106( + .A(n_1_0_101), .B1(n_1_0_642), .B2(registers_22__ap[5]), .C1(registers_16__ap[5]), + .C2(n_1_0_614), .ZN(n_1_0_100) + ); + AOI22_X1_LVT i_1_0_105( + .A1(registers_1__ap[5]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[5]), + .ZN(n_1_0_99) + ); + AOI22_X1_LVT i_1_0_104( + .A1(registers_14__ap[5]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[5]), + .ZN(n_1_0_98) + ); + AOI22_X1_LVT i_1_0_103( + .A1(registers_19__ap[5]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[5]), + .ZN(n_1_0_97) + ); + NAND3_X1_LVT i_1_0_102( + .A1(n_1_0_99), .A2(n_1_0_98), .A3(n_1_0_97), .ZN(n_1_0_96) + ); + AOI221_X1_LVT i_1_0_101( + .A(n_1_0_96), .B1(n_1_0_611), .B2(registers_11__ap[5]), .C1(registers_2__ap[5]), + .C2(n_1_0_618), .ZN(n_1_0_95) + ); + NAND3_X1_LVT i_1_0_100( + .A1(n_1_0_105), .A2(n_1_0_100), .A3(n_1_0_95), .ZN(RRs2[5]) + ); + AOI22_X1_LVT i_1_0_99( + .A1(registers_4__ap[4]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[4]), + .ZN(n_1_0_94) + ); + AOI222_X1_LVT i_1_0_98( + .A1(registers_8__ap[4]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[4]), + .C1(n_1_0_622), .C2(registers_30__ap[4]), .ZN(n_1_0_93) + ); + AOI22_X1_LVT i_1_0_97( + .A1(registers_29__ap[4]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[4]), + .ZN(n_1_0_92) + ); + AOI22_X1_LVT i_1_0_96( + .A1(registers_1__ap[4]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[4]), + .ZN(n_1_0_91) + ); + AOI22_X1_LVT i_1_0_95( + .A1(registers_27__ap[4]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[4]), + .ZN(n_1_0_90) + ); + AOI22_X1_LVT i_1_0_94( + .A1(registers_23__ap[4]), .A2(n_1_0_615), .B1(n_1_0_614), .B2(registers_16__ap[4]), + .ZN(n_1_0_89) + ); + AOI22_X1_LVT i_1_0_93( + .A1(registers_31__ap[4]), .A2(n_1_0_637), .B1(n_1_0_635), .B2(registers_5__ap[4]), + .ZN(n_1_0_88) + ); + NAND4_X1_LVT i_1_0_92( + .A1(n_1_0_91), .A2(n_1_0_90), .A3(n_1_0_89), .A4(n_1_0_88), .ZN(n_1_0_87) + ); + AOI22_X1_LVT i_1_0_91( + .A1(registers_18__ap[4]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[4]), + .ZN(n_1_0_86) + ); + AOI22_X1_LVT i_1_0_90( + .A1(registers_12__ap[4]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[4]), + .ZN(n_1_0_85) + ); + AOI22_X1_LVT i_1_0_89( + .A1(registers_22__ap[4]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[4]), + .ZN(n_1_0_84) + ); + AOI22_X1_LVT i_1_0_88( + .A1(registers_17__ap[4]), .A2(n_1_0_629), .B1(n_1_0_613), .B2(registers_20__ap[4]), + .ZN(n_1_0_83) + ); + NAND4_X1_LVT i_1_0_87( + .A1(n_1_0_86), .A2(n_1_0_85), .A3(n_1_0_84), .A4(n_1_0_83), .ZN(n_1_0_82) + ); + AOI22_X1_LVT i_1_0_86( + .A1(registers_13__ap[4]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[4]), + .ZN(n_1_0_81) + ); + AOI22_X1_LVT i_1_0_85( + .A1(registers_7__ap[4]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[4]), + .ZN(n_1_0_80) + ); + AOI22_X1_LVT i_1_0_84( + .A1(registers_19__ap[4]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[4]), + .ZN(n_1_0_79) + ); + AOI22_X1_LVT i_1_0_83( + .A1(registers_2__ap[4]), .A2(n_1_0_618), .B1(n_1_0_611), .B2(registers_11__ap[4]), + .ZN(n_1_0_78) + ); + NAND4_X1_LVT i_1_0_82( + .A1(n_1_0_81), .A2(n_1_0_80), .A3(n_1_0_79), .A4(n_1_0_78), .ZN(n_1_0_77) + ); + NOR3_X1_LVT i_1_0_81( + .A1(n_1_0_87), .A2(n_1_0_82), .A3(n_1_0_77), .ZN(n_1_0_76) + ); + NAND4_X1_LVT i_1_0_80( + .A1(n_1_0_94), .A2(n_1_0_93), .A3(n_1_0_92), .A4(n_1_0_76), .ZN(RRs2[4]) + ); + AOI22_X1_LVT i_1_0_78( + .A1(registers_29__ap[3]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[3]), + .ZN(n_1_0_74) + ); + AOI22_X1_LVT i_1_0_79( + .A1(registers_27__ap[3]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[3]), + .ZN(n_1_0_75) + ); + AOI22_X1_LVT i_1_0_77( + .A1(registers_1__ap[3]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[3]), + .ZN(n_1_0_73) + ); + AOI22_X1_LVT i_1_0_76( + .A1(registers_5__ap[3]), .A2(n_1_0_635), .B1(n_1_0_611), .B2(registers_11__ap[3]), + .ZN(n_1_0_72) + ); + NAND3_X1_LVT i_1_0_75( + .A1(n_1_0_75), .A2(n_1_0_73), .A3(n_1_0_72), .ZN(n_1_0_71) + ); + AOI221_X1_LVT i_1_0_74( + .A(n_1_0_71), .B1(n_1_0_614), .B2(registers_16__ap[3]), .C1(registers_31__ap[3]), + .C2(n_1_0_637), .ZN(n_1_0_70) + ); + AOI222_X1_LVT i_1_0_73( + .A1(registers_8__ap[3]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[3]), + .C1(n_1_0_622), .C2(registers_30__ap[3]), .ZN(n_1_0_69) + ); + NAND3_X1_LVT i_1_0_72( + .A1(n_1_0_74), .A2(n_1_0_70), .A3(n_1_0_69), .ZN(n_1_0_68) + ); + AOI221_X1_LVT i_1_0_71( + .A(n_1_0_68), .B1(n_1_0_638), .B2(registers_4__ap[3]), .C1(registers_28__ap[3]), + .C2(n_1_0_634), .ZN(n_1_0_67) + ); + AOI22_X1_LVT i_1_0_70( + .A1(registers_18__ap[3]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[3]), + .ZN(n_1_0_66) + ); + AOI22_X1_LVT i_1_0_69( + .A1(registers_12__ap[3]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[3]), + .ZN(n_1_0_65) + ); + AOI22_X1_LVT i_1_0_68( + .A1(registers_22__ap[3]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[3]), + .ZN(n_1_0_64) + ); + NAND3_X1_LVT i_1_0_67( + .A1(n_1_0_66), .A2(n_1_0_65), .A3(n_1_0_64), .ZN(n_1_0_63) + ); + AOI221_X1_LVT i_1_0_66( + .A(n_1_0_63), .B1(n_1_0_613), .B2(registers_20__ap[3]), .C1(registers_17__ap[3]), + .C2(n_1_0_629), .ZN(n_1_0_62) + ); + AOI22_X1_LVT i_1_0_65( + .A1(registers_13__ap[3]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[3]), + .ZN(n_1_0_61) + ); + AOI22_X1_LVT i_1_0_64( + .A1(registers_7__ap[3]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[3]), + .ZN(n_1_0_60) + ); + AOI22_X1_LVT i_1_0_63( + .A1(registers_19__ap[3]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[3]), + .ZN(n_1_0_59) + ); + NAND3_X1_LVT i_1_0_62( + .A1(n_1_0_61), .A2(n_1_0_60), .A3(n_1_0_59), .ZN(n_1_0_58) + ); + AOI221_X1_LVT i_1_0_61( + .A(n_1_0_58), .B1(n_1_0_618), .B2(registers_2__ap[3]), .C1(registers_23__ap[3]), + .C2(n_1_0_615), .ZN(n_1_0_57) + ); + NAND3_X1_LVT i_1_0_60( + .A1(n_1_0_67), .A2(n_1_0_62), .A3(n_1_0_57), .ZN(RRs2[3]) + ); + AOI22_X1_LVT i_1_0_58( + .A1(registers_29__ap[2]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[2]), + .ZN(n_1_0_55) + ); + AOI22_X1_LVT i_1_0_59( + .A1(registers_27__ap[2]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[2]), + .ZN(n_1_0_56) + ); + AOI22_X1_LVT i_1_0_57( + .A1(registers_1__ap[2]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[2]), + .ZN(n_1_0_54) + ); + AOI22_X1_LVT i_1_0_56( + .A1(registers_5__ap[2]), .A2(n_1_0_635), .B1(n_1_0_615), .B2(registers_23__ap[2]), + .ZN(n_1_0_53) + ); + NAND3_X1_LVT i_1_0_55( + .A1(n_1_0_56), .A2(n_1_0_54), .A3(n_1_0_53), .ZN(n_1_0_52) + ); + AOI221_X1_LVT i_1_0_54( + .A(n_1_0_52), .B1(n_1_0_637), .B2(registers_31__ap[2]), .C1(registers_16__ap[2]), + .C2(n_1_0_614), .ZN(n_1_0_51) + ); + AOI222_X1_LVT i_1_0_53( + .A1(registers_8__ap[2]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[2]), + .C1(n_1_0_622), .C2(registers_30__ap[2]), .ZN(n_1_0_50) + ); + NAND3_X1_LVT i_1_0_52( + .A1(n_1_0_55), .A2(n_1_0_51), .A3(n_1_0_50), .ZN(n_1_0_49) + ); + AOI221_X1_LVT i_1_0_51( + .A(n_1_0_49), .B1(n_1_0_638), .B2(registers_4__ap[2]), .C1(registers_28__ap[2]), + .C2(n_1_0_634), .ZN(n_1_0_48) + ); + AOI22_X1_LVT i_1_0_50( + .A1(registers_18__ap[2]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[2]), + .ZN(n_1_0_47) + ); + AOI22_X1_LVT i_1_0_49( + .A1(registers_12__ap[2]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[2]), + .ZN(n_1_0_46) + ); + AOI22_X1_LVT i_1_0_48( + .A1(registers_22__ap[2]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[2]), + .ZN(n_1_0_45) + ); + NAND3_X1_LVT i_1_0_47( + .A1(n_1_0_47), .A2(n_1_0_46), .A3(n_1_0_45), .ZN(n_1_0_44) + ); + AOI221_X1_LVT i_1_0_46( + .A(n_1_0_44), .B1(n_1_0_629), .B2(registers_17__ap[2]), .C1(registers_20__ap[2]), + .C2(n_1_0_613), .ZN(n_1_0_43) + ); + AOI22_X1_LVT i_1_0_45( + .A1(registers_13__ap[2]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[2]), + .ZN(n_1_0_42) + ); + AOI22_X1_LVT i_1_0_44( + .A1(registers_7__ap[2]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[2]), + .ZN(n_1_0_41) + ); + AOI22_X1_LVT i_1_0_43( + .A1(registers_19__ap[2]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[2]), + .ZN(n_1_0_40) + ); + NAND3_X1_LVT i_1_0_42( + .A1(n_1_0_42), .A2(n_1_0_41), .A3(n_1_0_40), .ZN(n_1_0_39) + ); + AOI221_X1_LVT i_1_0_41( + .A(n_1_0_39), .B1(n_1_0_618), .B2(registers_2__ap[2]), .C1(registers_11__ap[2]), + .C2(n_1_0_611), .ZN(n_1_0_38) + ); + NAND3_X1_LVT i_1_0_40( + .A1(n_1_0_48), .A2(n_1_0_43), .A3(n_1_0_38), .ZN(RRs2[2]) + ); + AOI22_X1_LVT i_1_0_38( + .A1(registers_29__ap[1]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[1]), + .ZN(n_1_0_36) + ); + AOI22_X1_LVT i_1_0_39( + .A1(registers_16__ap[1]), .A2(n_1_0_614), .B1(n_1_0_610), .B2(registers_3__ap[1]), + .ZN(n_1_0_37) + ); + AOI22_X1_LVT i_1_0_37( + .A1(registers_1__ap[1]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[1]), + .ZN(n_1_0_35) + ); + AOI22_X1_LVT i_1_0_36( + .A1(registers_31__ap[1]), .A2(n_1_0_637), .B1(n_1_0_635), .B2(registers_5__ap[1]), + .ZN(n_1_0_34) + ); + NAND3_X1_LVT i_1_0_35( + .A1(n_1_0_37), .A2(n_1_0_35), .A3(n_1_0_34), .ZN(n_1_0_33) + ); + AOI221_X1_LVT i_1_0_34( + .A(n_1_0_33), .B1(n_1_0_627), .B2(registers_15__ap[1]), .C1(registers_23__ap[1]), + .C2(n_1_0_615), .ZN(n_1_0_32) + ); + AOI222_X1_LVT i_1_0_33( + .A1(registers_26__ap[1]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[1]), + .C1(n_1_0_626), .C2(registers_8__ap[1]), .ZN(n_1_0_31) + ); + NAND3_X1_LVT i_1_0_32( + .A1(n_1_0_36), .A2(n_1_0_32), .A3(n_1_0_31), .ZN(n_1_0_30) + ); + AOI221_X1_LVT i_1_0_31( + .A(n_1_0_30), .B1(n_1_0_629), .B2(registers_17__ap[1]), .C1(registers_28__ap[1]), + .C2(n_1_0_634), .ZN(n_1_0_29) + ); + AOI22_X1_LVT i_1_0_30( + .A1(registers_18__ap[1]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[1]), + .ZN(n_1_0_28) + ); + AOI22_X1_LVT i_1_0_29( + .A1(registers_4__ap[1]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[1]), + .ZN(n_1_0_27) + ); + AOI22_X1_LVT i_1_0_28( + .A1(registers_22__ap[1]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[1]), + .ZN(n_1_0_26) + ); + NAND3_X1_LVT i_1_0_27( + .A1(n_1_0_28), .A2(n_1_0_27), .A3(n_1_0_26), .ZN(n_1_0_25) + ); + AOI221_X1_LVT i_1_0_26( + .A(n_1_0_25), .B1(n_1_0_632), .B2(registers_12__ap[1]), .C1(registers_24__ap[1]), + .C2(n_1_0_621), .ZN(n_1_0_24) + ); + AOI22_X1_LVT i_1_0_25( + .A1(registers_13__ap[1]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[1]), + .ZN(n_1_0_23) + ); + AOI22_X1_LVT i_1_0_24( + .A1(registers_7__ap[1]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[1]), + .ZN(n_1_0_22) + ); + AOI22_X1_LVT i_1_0_23( + .A1(registers_19__ap[1]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[1]), + .ZN(n_1_0_21) + ); + NAND3_X1_LVT i_1_0_22( + .A1(n_1_0_23), .A2(n_1_0_22), .A3(n_1_0_21), .ZN(n_1_0_20) + ); + AOI221_X1_LVT i_1_0_21( + .A(n_1_0_20), .B1(n_1_0_611), .B2(registers_11__ap[1]), .C1(registers_27__ap[1]), + .C2(n_1_0_636), .ZN(n_1_0_19) + ); + NAND3_X1_LVT i_1_0_20( + .A1(n_1_0_29), .A2(n_1_0_24), .A3(n_1_0_19), .ZN(RRs2[1]) + ); + AOI22_X1_LVT i_1_0_19( + .A1(registers_4__ap[0]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[0]), + .ZN(n_1_0_18) + ); + AOI222_X1_LVT i_1_0_18( + .A1(registers_8__ap[0]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[0]), + .C1(n_1_0_622), .C2(registers_30__ap[0]), .ZN(n_1_0_17) + ); + AOI22_X1_LVT i_1_0_17( + .A1(registers_29__ap[0]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[0]), + .ZN(n_1_0_16) + ); + AOI22_X1_LVT i_1_0_16( + .A1(registers_1__ap[0]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[0]), + .ZN(n_1_0_15) + ); + AOI22_X1_LVT i_1_0_15( + .A1(registers_27__ap[0]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[0]), + .ZN(n_1_0_14) + ); + AOI22_X1_LVT i_1_0_14( + .A1(registers_23__ap[0]), .A2(n_1_0_615), .B1(n_1_0_614), .B2(registers_16__ap[0]), + .ZN(n_1_0_13) + ); + AOI22_X1_LVT i_1_0_13( + .A1(registers_31__ap[0]), .A2(n_1_0_637), .B1(n_1_0_635), .B2(registers_5__ap[0]), + .ZN(n_1_0_12) + ); + NAND4_X1_LVT i_1_0_12( + .A1(n_1_0_15), .A2(n_1_0_14), .A3(n_1_0_13), .A4(n_1_0_12), .ZN(n_1_0_11) + ); + AOI22_X1_LVT i_1_0_11( + .A1(registers_18__ap[0]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[0]), + .ZN(n_1_0_10) + ); + AOI22_X1_LVT i_1_0_10( + .A1(registers_12__ap[0]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[0]), + .ZN(n_1_0_9) + ); + AOI22_X1_LVT i_1_0_9( + .A1(registers_22__ap[0]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[0]), + .ZN(n_1_0_8) + ); + AOI22_X1_LVT i_1_0_8( + .A1(registers_17__ap[0]), .A2(n_1_0_629), .B1(n_1_0_613), .B2(registers_20__ap[0]), + .ZN(n_1_0_7) + ); + NAND4_X1_LVT i_1_0_7( + .A1(n_1_0_10), .A2(n_1_0_9), .A3(n_1_0_8), .A4(n_1_0_7), .ZN(n_1_0_6) + ); + AOI22_X1_LVT i_1_0_6( + .A1(registers_13__ap[0]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[0]), + .ZN(n_1_0_5) + ); + AOI22_X1_LVT i_1_0_5( + .A1(registers_7__ap[0]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[0]), + .ZN(n_1_0_4) + ); + AOI22_X1_LVT i_1_0_4( + .A1(registers_19__ap[0]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[0]), + .ZN(n_1_0_3) + ); + AOI22_X1_LVT i_1_0_3( + .A1(registers_2__ap[0]), .A2(n_1_0_618), .B1(n_1_0_611), .B2(registers_11__ap[0]), + .ZN(n_1_0_2) + ); + NAND4_X1_LVT i_1_0_2( + .A1(n_1_0_5), .A2(n_1_0_4), .A3(n_1_0_3), .A4(n_1_0_2), .ZN(n_1_0_1) + ); + NOR3_X1_LVT i_1_0_1( + .A1(n_1_0_11), .A2(n_1_0_6), .A3(n_1_0_1), .ZN(n_1_0_0) + ); + NAND4_X1_LVT i_1_0_0( + .A1(n_1_0_18), .A2(n_1_0_17), .A3(n_1_0_16), .A4(n_1_0_0), .ZN(RRs2[0]) + ); + DLL_X2_LVT ts_lockup_latchn_clkc2_intno1050_i( + .D(registers_1__ap[0]), .GN(n_0_0), .Q(ts_no1050) + ); + DLL_X2_LVT ts_lockup_latchn_clkc4_intno1051_i( + .D(registers_6__ap[0]), .GN(n_0_36), .Q(ts_no1051) + ); + DLL_X2_LVT ts_lockup_latchn_clkc3_intno1053_i( + .D(registers_27__ap[0]), .GN(n_0_57), .Q(ts_no1053) + ); + DLL_X2_LVT ts_lockup_latchn_clkc1_intno1054_i( + .D(registers_11__ap[0]), .GN(n_0_41), .Q(ts_no1054) + ); + CLKBUF_X3_LVT tessent_persistent_cell_buf_extsi1227_i( + .A(ts_extsi1227), .Z(ts_pbuf_extsi1227_) + ); + CLKBUF_X3_LVT tessent_persistent_cell_buf_extsi1228_i( + .A(ts_extsi1228), .Z(ts_pbuf_extsi1228_) + ); + CLKBUF_X3_LVT tessent_persistent_cell_buf_extsi1226_i( + .A(ts_extsi1226), .Z(ts_pbuf_extsi1226_) + ); +endmodule + +module cpu(led, btn, clk_25mhz, scan_en, SI_1, SO_1, SI_2, SO_2, SI_3, SO_3, SI_4, + SO_4); + input [6:0] btn; + input clk_25mhz, scan_en, SI_1, SI_2, SI_3, SI_4; + output [7:0] led; + output SO_1, SO_2, SO_3, SO_4; + + wire [31:0] Instruction, RData, RRs2, RRs1, WRd, DAddr, JumpOrBranchPC, + CurrentPC, NextPC; + wire [1:0] DWidth; + wire WrReg, JumpOrBranch, thePC_n_1, thePC_i_0_n_0, thePC_n_2, thePC_i_0_n_1, + thePC_n_3, thePC_i_0_n_2, thePC_n_4, thePC_i_0_n_3, thePC_n_5, + thePC_i_0_n_4, thePC_n_6, thePC_i_0_n_5, thePC_n_7, thePC_i_0_n_6, + thePC_n_8, thePC_i_0_n_7, thePC_n_9, thePC_i_0_n_8, thePC_n_10, + thePC_i_0_n_9, thePC_n_11, thePC_i_0_n_10, thePC_n_12, thePC_i_0_n_11, + thePC_n_13, thePC_i_0_n_12, thePC_n_14, thePC_i_0_n_13, thePC_n_15, + thePC_i_0_n_14, thePC_n_16, thePC_i_0_n_15, thePC_n_17, thePC_i_0_n_16, + thePC_n_18, thePC_i_0_n_17, thePC_n_19, thePC_i_0_n_18, thePC_n_20, + thePC_i_0_n_19, thePC_n_21, thePC_i_0_n_20, thePC_n_22, thePC_i_0_n_21, + thePC_n_23, thePC_i_0_n_22, thePC_n_24, thePC_i_0_n_23, thePC_n_25, + thePC_i_0_n_24, thePC_n_26, thePC_i_0_n_25, thePC_n_27, thePC_i_0_n_26, + thePC_n_28, thePC_i_0_n_27, thePC_n_29, thePC_n_0, thePC_n_30, n_0_0_0, + thePC_n_31, n_0_0_1, thePC_n_32, thePC_n_33, thePC_n_34, thePC_n_35, + thePC_n_36, thePC_n_37, thePC_n_38, thePC_n_39, thePC_n_40, thePC_n_41, + thePC_n_42, thePC_n_43, n_0_0_2, thePC_n_44, n_0_0_3, thePC_n_45, + n_0_0_4, thePC_n_46, n_0_0_5, thePC_n_47, n_0_0_6, thePC_n_48, n_0_0_7, + thePC_n_49, n_0_0_8, thePC_n_50, n_0_0_9, thePC_n_51, n_0_0_10, + thePC_n_52, n_0_0_11, thePC_n_53, n_0_0_12, thePC_n_54, n_0_0_13, + thePC_n_55, n_0_0_14, thePC_n_56, n_0_0_15, thePC_n_57, n_0_0_16, + thePC_n_58, n_0_0_17, thePC_n_59, n_0_0_18, thePC_n_60, n_0_0_19, + thePC_n_61, n_0_0_20, n_0_0_21, n_0_0_22, reset, uc_0, uc_1, uc_2, uc_3, + uc_4, uc_5, uc_6, uc_7, uc_8, uc_9, uc_10, uc_11, uc_12, uc_13, uc_14, + uc_15, uc_16, uc_17, uc_18, uc_19, uc_20, uc_21, uc_22, uc_23, uc_24, + uc_25, uc_26, uc_27, uc_28, uc_29, uc_30, uc_31, uc_32, uc_33, uc_34, + uc_35, uc_36, uc_37, uc_38, uc_39, uc_40, uc_41, uc_42, uc_43, uc_44, + uc_45, uc_46, uc_47, uc_48, uc_49, uc_50, uc_51, uc_52, uc_53, uc_54, + uc_55, uc_56, uc_57, uc_58, ts_pbuf_extsi1225_, ts_no1054, ts_no1050, + ts_no1053, ts_no1051; + + assign SO_1 = ts_no1054; + assign SO_2 = ts_no1050; + assign SO_3 = ts_no1053; + assign SO_4 = ts_no1051; + AND2_X1_LVT i_0_0_54( + .A1(JumpOrBranch), .A2(btn[0]), .ZN(n_0_0_22) + ); + INV_X1_LVT i_0_0_66( + .A(btn[0]), .ZN(reset) + ); + NOR2_X1_LVT i_0_0_53( + .A1(reset), .A2(JumpOrBranch), .ZN(n_0_0_21) + ); + AOI22_X1_LVT i_0_0_50( + .A1(JumpOrBranchPC[30]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_28), .ZN(n_0_0_19) + ); + INV_X1_LVT i_0_0_49( + .A(n_0_0_19), .ZN(thePC_n_60) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[30] ( + .CK(clk_25mhz), .D(thePC_n_60), .Q(CurrentPC[30]), .QN(), .SE(scan_en), .SI(ts_pbuf_extsi1225_) + ); + AOI22_X1_LVT i_0_0_48( + .A1(JumpOrBranchPC[29]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_27), .ZN(n_0_0_18) + ); + INV_X1_LVT i_0_0_47( + .A(n_0_0_18), .ZN(thePC_n_59) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[29] ( + .CK(clk_25mhz), .D(thePC_n_59), .Q(CurrentPC[29]), .QN(), .SE(scan_en), .SI(CurrentPC[30]) + ); + AOI22_X1_LVT i_0_0_46( + .A1(JumpOrBranchPC[28]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_26), .ZN(n_0_0_17) + ); + INV_X1_LVT i_0_0_45( + .A(n_0_0_17), .ZN(thePC_n_58) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[28] ( + .CK(clk_25mhz), .D(thePC_n_58), .Q(CurrentPC[28]), .QN(), .SE(scan_en), .SI(CurrentPC[29]) + ); + AOI22_X1_LVT i_0_0_44( + .A1(JumpOrBranchPC[27]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_25), .ZN(n_0_0_16) + ); + INV_X1_LVT i_0_0_43( + .A(n_0_0_16), .ZN(thePC_n_57) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[27] ( + .CK(clk_25mhz), .D(thePC_n_57), .Q(CurrentPC[27]), .QN(), .SE(scan_en), .SI(CurrentPC[28]) + ); + AOI22_X1_LVT i_0_0_42( + .A1(JumpOrBranchPC[26]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_24), .ZN(n_0_0_15) + ); + INV_X1_LVT i_0_0_41( + .A(n_0_0_15), .ZN(thePC_n_56) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[26] ( + .CK(clk_25mhz), .D(thePC_n_56), .Q(CurrentPC[26]), .QN(), .SE(scan_en), .SI(CurrentPC[27]) + ); + AOI22_X1_LVT i_0_0_40( + .A1(JumpOrBranchPC[25]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_23), .ZN(n_0_0_14) + ); + INV_X1_LVT i_0_0_39( + .A(n_0_0_14), .ZN(thePC_n_55) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[25] ( + .CK(clk_25mhz), .D(thePC_n_55), .Q(CurrentPC[25]), .QN(), .SE(scan_en), .SI(CurrentPC[26]) + ); + AOI22_X1_LVT i_0_0_38( + .A1(JumpOrBranchPC[24]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_22), .ZN(n_0_0_13) + ); + INV_X1_LVT i_0_0_37( + .A(n_0_0_13), .ZN(thePC_n_54) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[24] ( + .CK(clk_25mhz), .D(thePC_n_54), .Q(CurrentPC[24]), .QN(), .SE(scan_en), .SI(CurrentPC[25]) + ); + AOI22_X1_LVT i_0_0_36( + .A1(JumpOrBranchPC[23]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_21), .ZN(n_0_0_12) + ); + INV_X1_LVT i_0_0_35( + .A(n_0_0_12), .ZN(thePC_n_53) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[23] ( + .CK(clk_25mhz), .D(thePC_n_53), .Q(CurrentPC[23]), .QN(), .SE(scan_en), .SI(CurrentPC[24]) + ); + AOI22_X1_LVT i_0_0_34( + .A1(JumpOrBranchPC[22]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_20), .ZN(n_0_0_11) + ); + INV_X1_LVT i_0_0_33( + .A(n_0_0_11), .ZN(thePC_n_52) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[22] ( + .CK(clk_25mhz), .D(thePC_n_52), .Q(CurrentPC[22]), .QN(), .SE(scan_en), .SI(CurrentPC[23]) + ); + AOI22_X1_LVT i_0_0_32( + .A1(JumpOrBranchPC[21]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_19), .ZN(n_0_0_10) + ); + INV_X1_LVT i_0_0_31( + .A(n_0_0_10), .ZN(thePC_n_51) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[21] ( + .CK(clk_25mhz), .D(thePC_n_51), .Q(CurrentPC[21]), .QN(), .SE(scan_en), .SI(CurrentPC[22]) + ); + AOI22_X1_LVT i_0_0_30( + .A1(JumpOrBranchPC[20]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_18), .ZN(n_0_0_9) + ); + INV_X1_LVT i_0_0_29( + .A(n_0_0_9), .ZN(thePC_n_50) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[20] ( + .CK(clk_25mhz), .D(thePC_n_50), .Q(CurrentPC[20]), .QN(), .SE(scan_en), .SI(CurrentPC[21]) + ); + AOI22_X1_LVT i_0_0_28( + .A1(JumpOrBranchPC[19]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_17), .ZN(n_0_0_8) + ); + INV_X1_LVT i_0_0_27( + .A(n_0_0_8), .ZN(thePC_n_49) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[19] ( + .CK(clk_25mhz), .D(thePC_n_49), .Q(CurrentPC[19]), .QN(), .SE(scan_en), .SI(CurrentPC[20]) + ); + AOI22_X1_LVT i_0_0_26( + .A1(JumpOrBranchPC[18]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_16), .ZN(n_0_0_7) + ); + INV_X1_LVT i_0_0_25( + .A(n_0_0_7), .ZN(thePC_n_48) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[18] ( + .CK(clk_25mhz), .D(thePC_n_48), .Q(CurrentPC[18]), .QN(), .SE(scan_en), .SI(CurrentPC[19]) + ); + AOI22_X1_LVT i_0_0_24( + .A1(JumpOrBranchPC[17]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_15), .ZN(n_0_0_6) + ); + INV_X1_LVT i_0_0_23( + .A(n_0_0_6), .ZN(thePC_n_47) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[17] ( + .CK(clk_25mhz), .D(thePC_n_47), .Q(CurrentPC[17]), .QN(), .SE(scan_en), .SI(CurrentPC[18]) + ); + AOI22_X1_LVT i_0_0_22( + .A1(JumpOrBranchPC[16]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_14), .ZN(n_0_0_5) + ); + INV_X1_LVT i_0_0_21( + .A(n_0_0_5), .ZN(thePC_n_46) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[16] ( + .CK(clk_25mhz), .D(thePC_n_46), .Q(CurrentPC[16]), .QN(), .SE(scan_en), .SI(CurrentPC[17]) + ); + AOI22_X1_LVT i_0_0_20( + .A1(JumpOrBranchPC[15]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_13), .ZN(n_0_0_4) + ); + INV_X1_LVT i_0_0_19( + .A(n_0_0_4), .ZN(thePC_n_45) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[15] ( + .CK(clk_25mhz), .D(thePC_n_45), .Q(CurrentPC[15]), .QN(), .SE(scan_en), .SI(CurrentPC[16]) + ); + AOI22_X1_LVT i_0_0_18( + .A1(JumpOrBranchPC[14]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_12), .ZN(n_0_0_3) + ); + INV_X1_LVT i_0_0_17( + .A(n_0_0_3), .ZN(thePC_n_44) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[14] ( + .CK(clk_25mhz), .D(thePC_n_44), .Q(CurrentPC[14]), .QN(), .SE(scan_en), .SI(CurrentPC[15]) + ); + AOI22_X1_LVT i_0_0_16( + .A1(JumpOrBranchPC[13]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_11), .ZN(n_0_0_2) + ); + INV_X1_LVT i_0_0_15( + .A(n_0_0_2), .ZN(thePC_n_43) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[13] ( + .CK(clk_25mhz), .D(thePC_n_43), .Q(CurrentPC[13]), .QN(), .SE(scan_en), .SI(CurrentPC[14]) + ); + MUX2_X1_LVT i_0_0_65( + .A(thePC_n_10), .B(JumpOrBranchPC[12]), .S(JumpOrBranch), .Z(NextPC[12]) + ); + AND2_X1_LVT i_0_0_14( + .A1(NextPC[12]), .A2(btn[0]), .ZN(thePC_n_42) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[12] ( + .CK(clk_25mhz), .D(thePC_n_42), .Q(CurrentPC[12]), .QN(), .SE(scan_en), .SI(CurrentPC[13]) + ); + MUX2_X1_LVT i_0_0_64( + .A(thePC_n_9), .B(JumpOrBranchPC[11]), .S(JumpOrBranch), .Z(NextPC[11]) + ); + AND2_X1_LVT i_0_0_13( + .A1(NextPC[11]), .A2(btn[0]), .ZN(thePC_n_41) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[11] ( + .CK(clk_25mhz), .D(thePC_n_41), .Q(CurrentPC[11]), .QN(), .SE(scan_en), .SI(CurrentPC[12]) + ); + MUX2_X1_LVT i_0_0_63( + .A(thePC_n_8), .B(JumpOrBranchPC[10]), .S(JumpOrBranch), .Z(NextPC[10]) + ); + AND2_X1_LVT i_0_0_12( + .A1(NextPC[10]), .A2(btn[0]), .ZN(thePC_n_40) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[10] ( + .CK(clk_25mhz), .D(thePC_n_40), .Q(CurrentPC[10]), .QN(), .SE(scan_en), .SI(CurrentPC[11]) + ); + MUX2_X1_LVT i_0_0_62( + .A(thePC_n_7), .B(JumpOrBranchPC[9]), .S(JumpOrBranch), .Z(NextPC[9]) + ); + AND2_X1_LVT i_0_0_11( + .A1(NextPC[9]), .A2(btn[0]), .ZN(thePC_n_39) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[9] ( + .CK(clk_25mhz), .D(thePC_n_39), .Q(CurrentPC[9]), .QN(), .SE(scan_en), .SI(CurrentPC[10]) + ); + MUX2_X1_LVT i_0_0_61( + .A(thePC_n_6), .B(JumpOrBranchPC[8]), .S(JumpOrBranch), .Z(NextPC[8]) + ); + AND2_X1_LVT i_0_0_10( + .A1(NextPC[8]), .A2(btn[0]), .ZN(thePC_n_38) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[8] ( + .CK(clk_25mhz), .D(thePC_n_38), .Q(CurrentPC[8]), .QN(), .SE(scan_en), .SI(CurrentPC[9]) + ); + AND2_X1_LVT i_0_0_9( + .A1(led[7]), .A2(btn[0]), .ZN(thePC_n_37) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[7] ( + .CK(clk_25mhz), .D(thePC_n_37), .Q(CurrentPC[7]), .QN(), .SE(scan_en), .SI(CurrentPC[8]) + ); + MUX2_X1_LVT i_0_0_59( + .A(thePC_n_4), .B(JumpOrBranchPC[6]), .S(JumpOrBranch), .Z(led[6]) + ); + AND2_X1_LVT i_0_0_8( + .A1(led[6]), .A2(btn[0]), .ZN(thePC_n_36) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[6] ( + .CK(clk_25mhz), .D(thePC_n_36), .Q(CurrentPC[6]), .QN(), .SE(scan_en), .SI(CurrentPC[7]) + ); + MUX2_X1_LVT i_0_0_58( + .A(thePC_n_3), .B(JumpOrBranchPC[5]), .S(JumpOrBranch), .Z(led[5]) + ); + AND2_X1_LVT i_0_0_7( + .A1(led[5]), .A2(btn[0]), .ZN(thePC_n_35) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[5] ( + .CK(clk_25mhz), .D(thePC_n_35), .Q(CurrentPC[5]), .QN(), .SE(scan_en), .SI(CurrentPC[6]) + ); + MUX2_X1_LVT i_0_0_57( + .A(thePC_n_2), .B(JumpOrBranchPC[4]), .S(JumpOrBranch), .Z(led[4]) + ); + AND2_X1_LVT i_0_0_6( + .A1(led[4]), .A2(btn[0]), .ZN(thePC_n_34) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[4] ( + .CK(clk_25mhz), .D(thePC_n_34), .Q(CurrentPC[4]), .QN(), .SE(scan_en), .SI(CurrentPC[5]) + ); + MUX2_X1_LVT i_0_0_56( + .A(thePC_n_1), .B(JumpOrBranchPC[3]), .S(JumpOrBranch), .Z(led[3]) + ); + AND2_X1_LVT i_0_0_5( + .A1(led[3]), .A2(btn[0]), .ZN(thePC_n_33) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[3] ( + .CK(clk_25mhz), .D(thePC_n_33), .Q(CurrentPC[3]), .QN(), .SE(scan_en), .SI(CurrentPC[4]) + ); + INV_X1_LVT thePC_i_0_29( + .A(CurrentPC[2]), .ZN(thePC_n_0) + ); + MUX2_X1_LVT i_0_0_55( + .A(thePC_n_0), .B(JumpOrBranchPC[2]), .S(JumpOrBranch), .Z(led[2]) + ); + AND2_X1_LVT i_0_0_4( + .A1(led[2]), .A2(btn[0]), .ZN(thePC_n_32) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[2] ( + .CK(clk_25mhz), .D(thePC_n_32), .Q(CurrentPC[2]), .QN(), .SE(scan_en), .SI(CurrentPC[3]) + ); + HA_X1_LVT thePC_i_0_0( + .A(CurrentPC[3]), .B(CurrentPC[2]), .CO(thePC_i_0_n_0), .S(thePC_n_1) + ); + HA_X1_LVT thePC_i_0_1( + .A(CurrentPC[4]), .B(thePC_i_0_n_0), .CO(thePC_i_0_n_1), .S(thePC_n_2) + ); + HA_X1_LVT thePC_i_0_2( + .A(CurrentPC[5]), .B(thePC_i_0_n_1), .CO(thePC_i_0_n_2), .S(thePC_n_3) + ); + HA_X1_LVT thePC_i_0_3( + .A(CurrentPC[6]), .B(thePC_i_0_n_2), .CO(thePC_i_0_n_3), .S(thePC_n_4) + ); + HA_X1_LVT thePC_i_0_4( + .A(CurrentPC[7]), .B(thePC_i_0_n_3), .CO(thePC_i_0_n_4), .S(thePC_n_5) + ); + HA_X1_LVT thePC_i_0_5( + .A(CurrentPC[8]), .B(thePC_i_0_n_4), .CO(thePC_i_0_n_5), .S(thePC_n_6) + ); + HA_X1_LVT thePC_i_0_6( + .A(CurrentPC[9]), .B(thePC_i_0_n_5), .CO(thePC_i_0_n_6), .S(thePC_n_7) + ); + HA_X1_LVT thePC_i_0_7( + .A(CurrentPC[10]), .B(thePC_i_0_n_6), .CO(thePC_i_0_n_7), .S(thePC_n_8) + ); + HA_X1_LVT thePC_i_0_8( + .A(CurrentPC[11]), .B(thePC_i_0_n_7), .CO(thePC_i_0_n_8), .S(thePC_n_9) + ); + HA_X1_LVT thePC_i_0_9( + .A(CurrentPC[12]), .B(thePC_i_0_n_8), .CO(thePC_i_0_n_9), .S(thePC_n_10) + ); + HA_X1_LVT thePC_i_0_11( + .A(CurrentPC[13]), .B(thePC_i_0_n_9), .CO(thePC_i_0_n_10), .S(thePC_n_11) + ); + HA_X1_LVT thePC_i_0_12( + .A(CurrentPC[14]), .B(thePC_i_0_n_10), .CO(thePC_i_0_n_11), .S(thePC_n_12) + ); + HA_X1_LVT thePC_i_0_13( + .A(CurrentPC[15]), .B(thePC_i_0_n_11), .CO(thePC_i_0_n_12), .S(thePC_n_13) + ); + HA_X1_LVT thePC_i_0_14( + .A(CurrentPC[16]), .B(thePC_i_0_n_12), .CO(thePC_i_0_n_13), .S(thePC_n_14) + ); + HA_X1_LVT thePC_i_0_15( + .A(CurrentPC[17]), .B(thePC_i_0_n_13), .CO(thePC_i_0_n_14), .S(thePC_n_15) + ); + HA_X1_LVT thePC_i_0_16( + .A(CurrentPC[18]), .B(thePC_i_0_n_14), .CO(thePC_i_0_n_15), .S(thePC_n_16) + ); + HA_X1_LVT thePC_i_0_17( + .A(CurrentPC[19]), .B(thePC_i_0_n_15), .CO(thePC_i_0_n_16), .S(thePC_n_17) + ); + HA_X1_LVT thePC_i_0_10( + .A(CurrentPC[20]), .B(thePC_i_0_n_16), .CO(thePC_i_0_n_17), .S(thePC_n_18) + ); + HA_X1_LVT thePC_i_0_18( + .A(CurrentPC[21]), .B(thePC_i_0_n_17), .CO(thePC_i_0_n_18), .S(thePC_n_19) + ); + HA_X1_LVT thePC_i_0_19( + .A(CurrentPC[22]), .B(thePC_i_0_n_18), .CO(thePC_i_0_n_19), .S(thePC_n_20) + ); + HA_X1_LVT thePC_i_0_20( + .A(CurrentPC[23]), .B(thePC_i_0_n_19), .CO(thePC_i_0_n_20), .S(thePC_n_21) + ); + HA_X1_LVT thePC_i_0_21( + .A(CurrentPC[24]), .B(thePC_i_0_n_20), .CO(thePC_i_0_n_21), .S(thePC_n_22) + ); + HA_X1_LVT thePC_i_0_22( + .A(CurrentPC[25]), .B(thePC_i_0_n_21), .CO(thePC_i_0_n_22), .S(thePC_n_23) + ); + HA_X1_LVT thePC_i_0_23( + .A(CurrentPC[26]), .B(thePC_i_0_n_22), .CO(thePC_i_0_n_23), .S(thePC_n_24) + ); + HA_X1_LVT thePC_i_0_24( + .A(CurrentPC[27]), .B(thePC_i_0_n_23), .CO(thePC_i_0_n_24), .S(thePC_n_25) + ); + HA_X1_LVT thePC_i_0_25( + .A(CurrentPC[28]), .B(thePC_i_0_n_24), .CO(thePC_i_0_n_25), .S(thePC_n_26) + ); + HA_X1_LVT thePC_i_0_26( + .A(CurrentPC[29]), .B(thePC_i_0_n_25), .CO(thePC_i_0_n_26), .S(thePC_n_27) + ); + HA_X1_LVT thePC_i_0_27( + .A(CurrentPC[30]), .B(thePC_i_0_n_26), .CO(thePC_i_0_n_27), .S(thePC_n_28) + ); + XOR2_X1_LVT thePC_i_0_28( + .A(CurrentPC[31]), .B(thePC_i_0_n_27), .Z(thePC_n_29) + ); + AOI22_X1_LVT i_0_0_52( + .A1(JumpOrBranchPC[31]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_29), .ZN(n_0_0_20) + ); + INV_X1_LVT i_0_0_51( + .A(n_0_0_20), .ZN(thePC_n_61) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[31] ( + .CK(clk_25mhz), .D(thePC_n_61), .Q(CurrentPC[31]), .QN(), .SE(scan_en), .SI(CurrentPC[2]) + ); + AOI22_X1_LVT i_0_0_3( + .A1(JumpOrBranchPC[1]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(CurrentPC[1]), + .ZN(n_0_0_1) + ); + INV_X1_LVT i_0_0_2( + .A(n_0_0_1), .ZN(thePC_n_31) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[1] ( + .CK(clk_25mhz), .D(thePC_n_31), .Q(CurrentPC[1]), .QN(), .SE(scan_en), .SI(CurrentPC[31]) + ); + AOI22_X1_LVT i_0_0_1( + .A1(JumpOrBranchPC[0]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(CurrentPC[0]), + .ZN(n_0_0_0) + ); + INV_X1_LVT i_0_0_0( + .A(n_0_0_0), .ZN(thePC_n_30) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[0] ( + .CK(clk_25mhz), .D(thePC_n_30), .Q(CurrentPC[0]), .QN(), .SE(scan_en), .SI(CurrentPC[1]) + ); + reg_file theRegisters( + .Rs1({Instruction[19], Instruction[18], Instruction[17], + Instruction[16], Instruction[15]}), .Rs2({Instruction[24], + Instruction[23], Instruction[22], Instruction[21], Instruction[20]}), .Rd({ + Instruction[11], Instruction[10], Instruction[9], Instruction[8], + Instruction[7]}), .RRs1(RRs1), .RRs2(RRs2), .WRd(WRd), .WrReg(WrReg), .reset(reset), + .clk(clk_25mhz), .dftIn(scan_en), .ts_intno31(CurrentPC[0]), .ts_no1050(ts_no1050), + .ts_no1051(ts_no1051), .ts_no1053(ts_no1053), .ts_no1054(ts_no1054), .ts_extsi1226(SI_2), + .ts_extsi1227(SI_3), .ts_extsi1228(SI_4) + ); + main_mem theMem( + .clk(clk_25mhz), .reset(reset), .DAddr({uc_0, uc_1, uc_2, uc_3, uc_4, + uc_5, uc_6, uc_7, uc_8, uc_9, uc_10, uc_11, uc_12, uc_13, uc_14, uc_15, + uc_16, uc_17, uc_18, DAddr[12], DAddr[11], DAddr[10], DAddr[9], + DAddr[8], DAddr[7], DAddr[6], DAddr[5], DAddr[4], DAddr[3], DAddr[2], + DAddr[1], DAddr[0]}), .IAddr({uc_19, uc_20, uc_21, uc_22, uc_23, uc_24, + uc_25, uc_26, uc_27, uc_28, uc_29, uc_30, uc_31, uc_32, uc_33, uc_34, + uc_35, uc_36, uc_37, NextPC[12], NextPC[11], NextPC[10], NextPC[9], + NextPC[8], led[7], led[6], led[5], led[4], led[3], led[2], uc_38, uc_39}), + .DWData(RRs2), .DRData(RData), .IRData(Instruction), .DWE(led[1]), .DWidth(DWidth) + ); + decoder theDecoder( + .CurrentPC(CurrentPC), .JumpOrBranchPC(JumpOrBranchPC), .JumpOrBranch(JumpOrBranch), + .DAddr({uc_40, uc_41, uc_42, uc_43, uc_44, uc_45, uc_46, uc_47, uc_48, + uc_49, uc_50, uc_51, uc_52, uc_53, uc_54, uc_55, uc_56, uc_57, uc_58, + DAddr[12], DAddr[11], DAddr[10], DAddr[9], DAddr[8], DAddr[7], DAddr[6], + DAddr[5], DAddr[4], DAddr[3], DAddr[2], DAddr[1], DAddr[0]}), .WData(), .RData(RData), + .Instruction(Instruction), .WrMem(led[1]), .DWidth(DWidth), .Rs1(), .Rs2(), + .Rd(), .RRs1(RRs1), .RRs2(RRs2), .WRd(WRd), .WrReg(WrReg), .Illegal(led[0]) + ); + MUX2_X1_LVT i_0_0_60( + .A(thePC_n_5), .B(JumpOrBranchPC[7]), .S(JumpOrBranch), .Z(led[7]) + ); + CLKBUF_X3_LVT tessent_persistent_cell_buf_extsi1225_i( + .A(SI_1), .Z(ts_pbuf_extsi1225_) + ); +endmodule + diff --git a/oasys.tessent.03/Scan_0/.oasys_netlist.v.swp b/oasys.tessent.03/Scan_0/.oasys_netlist.v.swp new file mode 100644 index 0000000..911dad4 Binary files /dev/null and b/oasys.tessent.03/Scan_0/.oasys_netlist.v.swp differ diff --git a/oasys.tessent.03/Scan_0/cpu.scandef b/oasys.tessent.03/Scan_0/cpu.scandef new file mode 100644 index 0000000..542144d --- /dev/null +++ b/oasys.tessent.03/Scan_0/cpu.scandef @@ -0,0 +1,1071 @@ +# +# DESC: ScanDEF written by Tessent Shell on Fri May 29 09:14:23 CEST 2026 +# + +VERSION 5.7 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN cpu ; +UNITS DISTANCE MICRONS 1000 ; + +SCANCHAINS 4 ; + +- scan_segment_0 + + START tessent_persistent_cell_buf_extsi1225_i Z + + FLOATING + thePC_CurrentPC_reg\[30\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[29\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[28\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[27\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[26\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[25\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[24\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[23\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[22\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[21\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[20\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[19\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[18\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[17\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[16\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[15\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[14\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[13\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[12\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[11\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[10\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[9\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[8\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[7\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[6\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[5\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[4\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[3\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[2\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[31\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[1\] ( IN SI ) ( OUT Q ) + thePC_CurrentPC_reg\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[13\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[10\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[12\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[15\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[16\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[14\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[11\]\[0\] ( IN SI ) ( OUT Q ) + + STOP theRegisters/ts_lockup_latchn_clkc1_intno1054_i D + # Partition constraints - clock domain: clk_25mhz(+); cluster: scanChain_1; chain type: core; scan mode(s): unwrapped + + PARTITION partition_1 MAXBITS 256 ; + + +- scan_segment_1 + + START theRegisters/tessent_persistent_cell_buf_extsi1226_i Z + + FLOATING + theRegisters/registers_reg\[1\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[21\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[20\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[17\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[23\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[18\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[22\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[19\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[1\]\[0\] ( IN SI ) ( OUT Q ) + + STOP theRegisters/ts_lockup_latchn_clkc2_intno1050_i D + # Partition constraints - clock domain: clk_25mhz(+); cluster: scanChain_2; chain type: core; scan mode(s): unwrapped + + PARTITION partition_2 MAXBITS 256 ; + + +- scan_segment_2 + + START theRegisters/tessent_persistent_cell_buf_extsi1227_i Z + + FLOATING + theRegisters/registers_reg\[28\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[26\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[25\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[28\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[24\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[29\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[30\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[2\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[27\]\[0\] ( IN SI ) ( OUT Q ) + + STOP theRegisters/ts_lockup_latchn_clkc3_intno1053_i D + # Partition constraints - clock domain: clk_25mhz(+); cluster: scanChain_3; chain type: core; scan mode(s): unwrapped + + PARTITION partition_3 MAXBITS 256 ; + + +- scan_segment_3 + + START theRegisters/tessent_persistent_cell_buf_extsi1228_i Z + + FLOATING + theRegisters/registers_reg\[4\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[31\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[30\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[29\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[28\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[27\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[26\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[25\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[24\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[23\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[22\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[21\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[20\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[19\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[18\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[17\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[16\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[15\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[14\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[13\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[12\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[11\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[10\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[9\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[8\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[7\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[6\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[5\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[4\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[3\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[2\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[1\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[8\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[7\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[3\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[31\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[4\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[5\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[9\]\[0\] ( IN SI ) ( OUT Q ) + theRegisters/registers_reg\[6\]\[0\] ( IN SI ) ( OUT Q ) + + STOP theRegisters/ts_lockup_latchn_clkc4_intno1051_i D + # Partition constraints - clock domain: clk_25mhz(+); cluster: scanChain_4; chain type: core; scan mode(s): unwrapped + + PARTITION partition_4 MAXBITS 256 ; + + +END SCANCHAINS + +END DESIGN diff --git a/oasys.tessent.03/Scan_0/oasys.sdc b/oasys.tessent.03/Scan_0/oasys.sdc new file mode 100644 index 0000000..cc1d2d9 --- /dev/null +++ b/oasys.tessent.03/Scan_0/oasys.sdc @@ -0,0 +1,62 @@ +# +# Created by +# ../bin/Linux-x86_64-O/oasysGui 22.2-p002 on Fri May 29 09:14:17 2026 +# (C) Mentor Graphics Corporation +# +set_units -time ns -capacitance pf -resistance kohm -power nW -voltage V -current uA +create_clock -period 40 -waveform {0 20} -name clk_25mhz [get_ports clk_25mhz] +set_clock_transition 0.1 [get_clocks clk_25mhz] +set_clock_uncertainty -setup 0.5 [get_clocks clk_25mhz] +set_clock_uncertainty -hold 0.2 [get_clocks clk_25mhz] +set_false_path -from [get_ports {btn[0]}] +group_path -name I2R -from [list [get_ports clk_25mhz] [get_ports {btn[0]}] [get_ports {btn[1]}] [get_ports {btn[2]}] [get_ports {btn[3]}] [get_ports {btn[4]}] [get_ports {btn[5]}] [get_ports {btn[6]}]] +group_path -name I2O -from [list [get_ports clk_25mhz] [get_ports {btn[0]}] [get_ports {btn[1]}] [get_ports {btn[2]}] [get_ports {btn[3]}] [get_ports {btn[4]}] [get_ports {btn[5]}] [get_ports {btn[6]}]] -to [list [get_ports {led[0]}] [get_ports {led[1]}] [get_ports {led[2]}] [get_ports {led[3]}] [get_ports {led[4]}] [get_ports {led[5]}] [get_ports {led[6]}] [get_ports {led[7]}]] +group_path -name R2O -to [list [get_ports {led[0]}] [get_ports {led[1]}] [get_ports {led[2]}] [get_ports {led[3]}] [get_ports {led[4]}] [get_ports {led[5]}] [get_ports {led[6]}] [get_ports {led[7]}]] +set_input_delay 2 -clock clk_25mhz -max [get_ports {btn[6]}] +set_input_delay 2 -clock clk_25mhz -max [get_ports {btn[5]}] +set_input_delay 2 -clock clk_25mhz -max [get_ports {btn[4]}] +set_input_delay 2 -clock clk_25mhz -max [get_ports {btn[3]}] +set_input_delay 2 -clock clk_25mhz -max [get_ports {btn[2]}] +set_input_delay 2 -clock clk_25mhz -max [get_ports {btn[1]}] +set_input_delay 2 -clock clk_25mhz -max [get_ports {btn[0]}] +set_input_delay 0.5 -clock clk_25mhz -min [get_ports {btn[6]}] +set_input_delay 0.5 -clock clk_25mhz -min [get_ports {btn[5]}] +set_input_delay 0.5 -clock clk_25mhz -min [get_ports {btn[4]}] +set_input_delay 0.5 -clock clk_25mhz -min [get_ports {btn[3]}] +set_input_delay 0.5 -clock clk_25mhz -min [get_ports {btn[2]}] +set_input_delay 0.5 -clock clk_25mhz -min [get_ports {btn[1]}] +set_input_delay 0.5 -clock clk_25mhz -min [get_ports {btn[0]}] +set_output_delay 2 -clock clk_25mhz -max [get_ports {led[7]}] +set_output_delay 2 -clock clk_25mhz -max [get_ports {led[6]}] +set_output_delay 2 -clock clk_25mhz -max [get_ports {led[5]}] +set_output_delay 2 -clock clk_25mhz -max [get_ports {led[4]}] +set_output_delay 2 -clock clk_25mhz -max [get_ports {led[3]}] +set_output_delay 2 -clock clk_25mhz -max [get_ports {led[2]}] +set_output_delay 2 -clock clk_25mhz -max [get_ports {led[1]}] +set_output_delay 2 -clock clk_25mhz -max [get_ports {led[0]}] +set_output_delay 0.5 -clock clk_25mhz -min [get_ports {led[7]}] +set_output_delay 0.5 -clock clk_25mhz -min [get_ports {led[6]}] +set_output_delay 0.5 -clock clk_25mhz -min [get_ports {led[5]}] +set_output_delay 0.5 -clock clk_25mhz -min [get_ports {led[4]}] +set_output_delay 0.5 -clock clk_25mhz -min [get_ports {led[3]}] +set_output_delay 0.5 -clock clk_25mhz -min [get_ports {led[2]}] +set_output_delay 0.5 -clock clk_25mhz -min [get_ports {led[1]}] +set_output_delay 0.5 -clock clk_25mhz -min [get_ports {led[0]}] +set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 [get_ports {btn[6]}] +set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 [get_ports {btn[5]}] +set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 [get_ports {btn[4]}] +set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 [get_ports {btn[3]}] +set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 [get_ports {btn[2]}] +set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 [get_ports {btn[1]}] +set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 [get_ports {btn[0]}] +set_load 0.05 [get_ports {led[7]}] +set_load 0.05 [get_ports {led[6]}] +set_load 0.05 [get_ports {led[5]}] +set_load 0.05 [get_ports {led[4]}] +set_load 0.05 [get_ports {led[3]}] +set_load 0.05 [get_ports {led[2]}] +set_load 0.05 [get_ports {led[1]}] +set_load 0.05 [get_ports {led[0]}] +set_operating_conditions -library [get_libs {NangateOpenCellLibrary_45nm_LVT_0p85}] -max slow_0p85V -min slow_0p85V +set_max_fanout 20.000000 [current_design] +set_max_transition 0.500000 [current_design] diff --git a/oasys.tessent.03/Scan_0/oasys_netlist.v b/oasys.tessent.03/Scan_0/oasys_netlist.v new file mode 100644 index 0000000..ee2d9b0 --- /dev/null +++ b/oasys.tessent.03/Scan_0/oasys_netlist.v @@ -0,0 +1,10896 @@ +/* + * Created by + ../bin/Linux-x86_64-O/oasysGui 22.2-p002 on Fri May 29 09:14:16 2026 + * (C) Mentor Graphics Corporation + */ +/* CheckSum: 514746972 */ + +module reg_file(Rs1, Rs2, Rd, RRs1, RRs2, WRd, WrReg, reset, clk, dftIn); + input [4:0]Rs1; + input [4:0]Rs2; + input [4:0]Rd; + output [31:0]RRs1; + output [31:0]RRs2; + input [31:0]WRd; + input WrReg; + input reset; + input clk; + input dftIn; + + wire [31:0]registers_1__ap; + wire n_0_0; + wire [31:0]registers_2__ap; + wire n_0_32; + wire [31:0]registers_3__ap; + wire n_0_33; + wire [31:0]registers_4__ap; + wire n_0_34; + wire [31:0]registers_5__ap; + wire n_0_35; + wire [31:0]registers_6__ap; + wire n_0_36; + wire [31:0]registers_7__ap; + wire n_0_37; + wire [31:0]registers_8__ap; + wire n_0_38; + wire [31:0]registers_9__ap; + wire n_0_39; + wire [31:0]registers_10__ap; + wire n_0_40; + wire [31:0]registers_11__ap; + wire n_0_41; + wire [31:0]registers_12__ap; + wire n_0_42; + wire [31:0]registers_13__ap; + wire n_0_43; + wire [31:0]registers_14__ap; + wire n_0_44; + wire [31:0]registers_15__ap; + wire n_0_45; + wire [31:0]registers_16__ap; + wire n_0_46; + wire [31:0]registers_17__ap; + wire n_0_47; + wire [31:0]registers_18__ap; + wire n_0_48; + wire [31:0]registers_19__ap; + wire n_0_49; + wire [31:0]registers_20__ap; + wire n_0_50; + wire [31:0]registers_21__ap; + wire n_0_51; + wire [31:0]registers_22__ap; + wire n_0_52; + wire [31:0]registers_23__ap; + wire n_0_53; + wire [31:0]registers_24__ap; + wire n_0_54; + wire [31:0]registers_25__ap; + wire n_0_55; + wire [31:0]registers_26__ap; + wire n_0_56; + wire [31:0]registers_27__ap; + wire n_0_57; + wire [31:0]registers_28__ap; + wire n_0_58; + wire [31:0]registers_29__ap; + wire n_0_59; + wire [31:0]registers_30__ap; + wire n_0_60; + wire [31:0]registers_31__ap; + wire n_0_61; + wire [31:0]registers; + wire n_0_31; + wire n_0_30; + wire n_0_29; + wire n_0_28; + wire n_0_27; + wire n_0_26; + wire n_0_25; + wire n_0_24; + wire n_0_0_0; + wire n_0_0_1; + wire n_0_23; + wire n_0_22; + wire n_0_21; + wire n_0_20; + wire n_0_19; + wire n_0_18; + wire n_0_17; + wire n_0_16; + wire n_0_0_2; + wire n_0_0_3; + wire n_0_15; + wire n_0_14; + wire n_0_13; + wire n_0_12; + wire n_0_11; + wire n_0_10; + wire n_0_9; + wire n_0_8; + wire n_0_0_4; + wire n_0_0_5; + wire n_0_7; + wire n_0_0_6; + wire n_0_6; + wire n_0_0_7; + wire n_0_5; + wire n_0_0_8; + wire n_0_4; + wire n_0_0_9; + wire n_0_0_10; + wire n_0_3; + wire n_0_0_11; + wire n_0_2; + wire n_0_0_12; + wire n_0_1; + wire n_0_0_13; + wire n_0_0_14; + wire n_0_0_15; + wire n_0_0_16; + wire n_0_0_17; + wire n_0_0_18; + wire n_0_0_19; + wire n_0_0_20; + wire n_1_0_0; + wire n_1_0_1; + wire n_1_0_2; + wire n_1_0_3; + wire n_1_0_4; + wire n_1_0_5; + wire n_1_0_6; + wire n_1_0_7; + wire n_1_0_8; + wire n_1_0_9; + wire n_1_0_10; + wire n_1_0_11; + wire n_1_0_12; + wire n_1_0_13; + wire n_1_0_14; + wire n_1_0_15; + wire n_1_0_16; + wire n_1_0_17; + wire n_1_0_18; + wire n_1_0_19; + wire n_1_0_20; + wire n_1_0_21; + wire n_1_0_22; + wire n_1_0_23; + wire n_1_0_24; + wire n_1_0_25; + wire n_1_0_26; + wire n_1_0_27; + wire n_1_0_28; + wire n_1_0_29; + wire n_1_0_30; + wire n_1_0_31; + wire n_1_0_32; + wire n_1_0_33; + wire n_1_0_34; + wire n_1_0_35; + wire n_1_0_36; + wire n_1_0_37; + wire n_1_0_38; + wire n_1_0_39; + wire n_1_0_40; + wire n_1_0_41; + wire n_1_0_42; + wire n_1_0_43; + wire n_1_0_44; + wire n_1_0_45; + wire n_1_0_46; + wire n_1_0_47; + wire n_1_0_48; + wire n_1_0_49; + wire n_1_0_50; + wire n_1_0_51; + wire n_1_0_52; + wire n_1_0_53; + wire n_1_0_54; + wire n_1_0_55; + wire n_1_0_56; + wire n_1_0_57; + wire n_1_0_58; + wire n_1_0_59; + wire n_1_0_60; + wire n_1_0_61; + wire n_1_0_62; + wire n_1_0_63; + wire n_1_0_64; + wire n_1_0_65; + wire n_1_0_66; + wire n_1_0_67; + wire n_1_0_68; + wire n_1_0_69; + wire n_1_0_70; + wire n_1_0_71; + wire n_1_0_72; + wire n_1_0_73; + wire n_1_0_74; + wire n_1_0_75; + wire n_1_0_76; + wire n_1_0_77; + wire n_1_0_78; + wire n_1_0_79; + wire n_1_0_80; + wire n_1_0_81; + wire n_1_0_82; + wire n_1_0_83; + wire n_1_0_84; + wire n_1_0_85; + wire n_1_0_86; + wire n_1_0_87; + wire n_1_0_88; + wire n_1_0_89; + wire n_1_0_90; + wire n_1_0_91; + wire n_1_0_92; + wire n_1_0_93; + wire n_1_0_94; + wire n_1_0_95; + wire n_1_0_96; + wire n_1_0_97; + wire n_1_0_98; + wire n_1_0_99; + wire n_1_0_100; + wire n_1_0_101; + wire n_1_0_102; + wire n_1_0_103; + wire n_1_0_104; + wire n_1_0_105; + wire n_1_0_106; + wire n_1_0_107; + wire n_1_0_108; + wire n_1_0_109; + wire n_1_0_110; + wire n_1_0_111; + wire n_1_0_112; + wire n_1_0_113; + wire n_1_0_114; + wire n_1_0_115; + wire n_1_0_116; + wire n_1_0_117; + wire n_1_0_118; + wire n_1_0_119; + wire n_1_0_120; + wire n_1_0_121; + wire n_1_0_122; + wire n_1_0_123; + wire n_1_0_124; + wire n_1_0_125; + wire n_1_0_126; + wire n_1_0_127; + wire n_1_0_128; + wire n_1_0_129; + wire n_1_0_130; + wire n_1_0_131; + wire n_1_0_132; + wire n_1_0_133; + wire n_1_0_134; + wire n_1_0_135; + wire n_1_0_136; + wire n_1_0_137; + wire n_1_0_138; + wire n_1_0_139; + wire n_1_0_140; + wire n_1_0_141; + wire n_1_0_142; + wire n_1_0_143; + wire n_1_0_144; + wire n_1_0_145; + wire n_1_0_146; + wire n_1_0_147; + wire n_1_0_148; + wire n_1_0_149; + wire n_1_0_150; + wire n_1_0_151; + wire n_1_0_152; + wire n_1_0_153; + wire n_1_0_154; + wire n_1_0_155; + wire n_1_0_156; + wire n_1_0_157; + wire n_1_0_158; + wire n_1_0_159; + wire n_1_0_160; + wire n_1_0_161; + wire n_1_0_162; + wire n_1_0_163; + wire n_1_0_164; + wire n_1_0_165; + wire n_1_0_166; + wire n_1_0_167; + wire n_1_0_168; + wire n_1_0_169; + wire n_1_0_170; + wire n_1_0_171; + wire n_1_0_172; + wire n_1_0_173; + wire n_1_0_174; + wire n_1_0_175; + wire n_1_0_176; + wire n_1_0_177; + wire n_1_0_178; + wire n_1_0_179; + wire n_1_0_180; + wire n_1_0_181; + wire n_1_0_182; + wire n_1_0_183; + wire n_1_0_184; + wire n_1_0_185; + wire n_1_0_186; + wire n_1_0_187; + wire n_1_0_188; + wire n_1_0_189; + wire n_1_0_190; + wire n_1_0_191; + wire n_1_0_192; + wire n_1_0_193; + wire n_1_0_194; + wire n_1_0_195; + wire n_1_0_196; + wire n_1_0_197; + wire n_1_0_198; + wire n_1_0_199; + wire n_1_0_200; + wire n_1_0_201; + wire n_1_0_202; + wire n_1_0_203; + wire n_1_0_204; + wire n_1_0_205; + wire n_1_0_206; + wire n_1_0_207; + wire n_1_0_208; + wire n_1_0_209; + wire n_1_0_210; + wire n_1_0_211; + wire n_1_0_212; + wire n_1_0_213; + wire n_1_0_214; + wire n_1_0_215; + wire n_1_0_216; + wire n_1_0_217; + wire n_1_0_218; + wire n_1_0_219; + wire n_1_0_220; + wire n_1_0_221; + wire n_1_0_222; + wire n_1_0_223; + wire n_1_0_224; + wire n_1_0_225; + wire n_1_0_226; + wire n_1_0_227; + wire n_1_0_228; + wire n_1_0_229; + wire n_1_0_230; + wire n_1_0_231; + wire n_1_0_232; + wire n_1_0_233; + wire n_1_0_234; + wire n_1_0_235; + wire n_1_0_236; + wire n_1_0_237; + wire n_1_0_238; + wire n_1_0_239; + wire n_1_0_240; + wire n_1_0_241; + wire n_1_0_242; + wire n_1_0_243; + wire n_1_0_244; + wire n_1_0_245; + wire n_1_0_246; + wire n_1_0_247; + wire n_1_0_248; + wire n_1_0_249; + wire n_1_0_250; + wire n_1_0_251; + wire n_1_0_252; + wire n_1_0_253; + wire n_1_0_254; + wire n_1_0_255; + wire n_1_0_256; + wire n_1_0_257; + wire n_1_0_258; + wire n_1_0_259; + wire n_1_0_260; + wire n_1_0_261; + wire n_1_0_262; + wire n_1_0_263; + wire n_1_0_264; + wire n_1_0_265; + wire n_1_0_266; + wire n_1_0_267; + wire n_1_0_268; + wire n_1_0_269; + wire n_1_0_270; + wire n_1_0_271; + wire n_1_0_272; + wire n_1_0_273; + wire n_1_0_274; + wire n_1_0_275; + wire n_1_0_276; + wire n_1_0_277; + wire n_1_0_278; + wire n_1_0_279; + wire n_1_0_280; + wire n_1_0_281; + wire n_1_0_282; + wire n_1_0_283; + wire n_1_0_284; + wire n_1_0_285; + wire n_1_0_286; + wire n_1_0_287; + wire n_1_0_288; + wire n_1_0_289; + wire n_1_0_290; + wire n_1_0_291; + wire n_1_0_292; + wire n_1_0_293; + wire n_1_0_294; + wire n_1_0_295; + wire n_1_0_296; + wire n_1_0_297; + wire n_1_0_298; + wire n_1_0_299; + wire n_1_0_300; + wire n_1_0_301; + wire n_1_0_302; + wire n_1_0_303; + wire n_1_0_304; + wire n_1_0_305; + wire n_1_0_306; + wire n_1_0_307; + wire n_1_0_308; + wire n_1_0_309; + wire n_1_0_310; + wire n_1_0_311; + wire n_1_0_312; + wire n_1_0_313; + wire n_1_0_314; + wire n_1_0_315; + wire n_1_0_316; + wire n_1_0_317; + wire n_1_0_318; + wire n_1_0_319; + wire n_1_0_320; + wire n_1_0_321; + wire n_1_0_322; + wire n_1_0_323; + wire n_1_0_324; + wire n_1_0_325; + wire n_1_0_326; + wire n_1_0_327; + wire n_1_0_328; + wire n_1_0_329; + wire n_1_0_330; + wire n_1_0_331; + wire n_1_0_332; + wire n_1_0_333; + wire n_1_0_334; + wire n_1_0_335; + wire n_1_0_336; + wire n_1_0_337; + wire n_1_0_338; + wire n_1_0_339; + wire n_1_0_340; + wire n_1_0_341; + wire n_1_0_342; + wire n_1_0_343; + wire n_1_0_344; + wire n_1_0_345; + wire n_1_0_346; + wire n_1_0_347; + wire n_1_0_348; + wire n_1_0_349; + wire n_1_0_350; + wire n_1_0_351; + wire n_1_0_352; + wire n_1_0_353; + wire n_1_0_354; + wire n_1_0_355; + wire n_1_0_356; + wire n_1_0_357; + wire n_1_0_358; + wire n_1_0_359; + wire n_1_0_360; + wire n_1_0_361; + wire n_1_0_362; + wire n_1_0_363; + wire n_1_0_364; + wire n_1_0_365; + wire n_1_0_366; + wire n_1_0_367; + wire n_1_0_368; + wire n_1_0_369; + wire n_1_0_370; + wire n_1_0_371; + wire n_1_0_372; + wire n_1_0_373; + wire n_1_0_374; + wire n_1_0_375; + wire n_1_0_376; + wire n_1_0_377; + wire n_1_0_378; + wire n_1_0_379; + wire n_1_0_380; + wire n_1_0_381; + wire n_1_0_382; + wire n_1_0_383; + wire n_1_0_384; + wire n_1_0_385; + wire n_1_0_386; + wire n_1_0_387; + wire n_1_0_388; + wire n_1_0_389; + wire n_1_0_390; + wire n_1_0_391; + wire n_1_0_392; + wire n_1_0_393; + wire n_1_0_394; + wire n_1_0_395; + wire n_1_0_396; + wire n_1_0_397; + wire n_1_0_398; + wire n_1_0_399; + wire n_1_0_400; + wire n_1_0_401; + wire n_1_0_402; + wire n_1_0_403; + wire n_1_0_404; + wire n_1_0_405; + wire n_1_0_406; + wire n_1_0_407; + wire n_1_0_408; + wire n_1_0_409; + wire n_1_0_410; + wire n_1_0_411; + wire n_1_0_412; + wire n_1_0_413; + wire n_1_0_414; + wire n_1_0_415; + wire n_1_0_416; + wire n_1_0_417; + wire n_1_0_418; + wire n_1_0_419; + wire n_1_0_420; + wire n_1_0_421; + wire n_1_0_422; + wire n_1_0_423; + wire n_1_0_424; + wire n_1_0_425; + wire n_1_0_426; + wire n_1_0_427; + wire n_1_0_428; + wire n_1_0_429; + wire n_1_0_430; + wire n_1_0_431; + wire n_1_0_432; + wire n_1_0_433; + wire n_1_0_434; + wire n_1_0_435; + wire n_1_0_436; + wire n_1_0_437; + wire n_1_0_438; + wire n_1_0_439; + wire n_1_0_440; + wire n_1_0_441; + wire n_1_0_442; + wire n_1_0_443; + wire n_1_0_444; + wire n_1_0_445; + wire n_1_0_446; + wire n_1_0_447; + wire n_1_0_448; + wire n_1_0_449; + wire n_1_0_450; + wire n_1_0_451; + wire n_1_0_452; + wire n_1_0_453; + wire n_1_0_454; + wire n_1_0_455; + wire n_1_0_456; + wire n_1_0_457; + wire n_1_0_458; + wire n_1_0_459; + wire n_1_0_460; + wire n_1_0_461; + wire n_1_0_462; + wire n_1_0_463; + wire n_1_0_464; + wire n_1_0_465; + wire n_1_0_466; + wire n_1_0_467; + wire n_1_0_468; + wire n_1_0_469; + wire n_1_0_470; + wire n_1_0_471; + wire n_1_0_472; + wire n_1_0_473; + wire n_1_0_474; + wire n_1_0_475; + wire n_1_0_476; + wire n_1_0_477; + wire n_1_0_478; + wire n_1_0_479; + wire n_1_0_480; + wire n_1_0_481; + wire n_1_0_482; + wire n_1_0_483; + wire n_1_0_484; + wire n_1_0_485; + wire n_1_0_486; + wire n_1_0_487; + wire n_1_0_488; + wire n_1_0_489; + wire n_1_0_490; + wire n_1_0_491; + wire n_1_0_492; + wire n_1_0_493; + wire n_1_0_494; + wire n_1_0_495; + wire n_1_0_496; + wire n_1_0_497; + wire n_1_0_498; + wire n_1_0_499; + wire n_1_0_500; + wire n_1_0_501; + wire n_1_0_502; + wire n_1_0_503; + wire n_1_0_504; + wire n_1_0_505; + wire n_1_0_506; + wire n_1_0_507; + wire n_1_0_508; + wire n_1_0_509; + wire n_1_0_510; + wire n_1_0_511; + wire n_1_0_512; + wire n_1_0_513; + wire n_1_0_514; + wire n_1_0_515; + wire n_1_0_516; + wire n_1_0_517; + wire n_1_0_518; + wire n_1_0_519; + wire n_1_0_520; + wire n_1_0_521; + wire n_1_0_522; + wire n_1_0_523; + wire n_1_0_524; + wire n_1_0_525; + wire n_1_0_526; + wire n_1_0_527; + wire n_1_0_528; + wire n_1_0_529; + wire n_1_0_530; + wire n_1_0_531; + wire n_1_0_532; + wire n_1_0_533; + wire n_1_0_534; + wire n_1_0_535; + wire n_1_0_536; + wire n_1_0_537; + wire n_1_0_538; + wire n_1_0_539; + wire n_1_0_540; + wire n_1_0_541; + wire n_1_0_542; + wire n_1_0_543; + wire n_1_0_544; + wire n_1_0_545; + wire n_1_0_546; + wire n_1_0_547; + wire n_1_0_548; + wire n_1_0_549; + wire n_1_0_550; + wire n_1_0_551; + wire n_1_0_552; + wire n_1_0_553; + wire n_1_0_554; + wire n_1_0_555; + wire n_1_0_556; + wire n_1_0_557; + wire n_1_0_558; + wire n_1_0_559; + wire n_1_0_560; + wire n_1_0_561; + wire n_1_0_562; + wire n_1_0_563; + wire n_1_0_564; + wire n_1_0_565; + wire n_1_0_566; + wire n_1_0_567; + wire n_1_0_568; + wire n_1_0_569; + wire n_1_0_570; + wire n_1_0_571; + wire n_1_0_572; + wire n_1_0_573; + wire n_1_0_574; + wire n_1_0_575; + wire n_1_0_576; + wire n_1_0_577; + wire n_1_0_578; + wire n_1_0_579; + wire n_1_0_580; + wire n_1_0_581; + wire n_1_0_582; + wire n_1_0_583; + wire n_1_0_584; + wire n_1_0_585; + wire n_1_0_586; + wire n_1_0_587; + wire n_1_0_588; + wire n_1_0_589; + wire n_1_0_590; + wire n_1_0_591; + wire n_1_0_592; + wire n_1_0_593; + wire n_1_0_594; + wire n_1_0_595; + wire n_1_0_596; + wire n_1_0_597; + wire n_1_0_598; + wire n_1_0_599; + wire n_1_0_600; + wire n_1_0_601; + wire n_1_0_602; + wire n_1_0_603; + wire n_1_0_604; + wire n_1_0_605; + wire n_1_0_606; + wire n_1_0_607; + wire n_1_0_608; + wire n_1_0_609; + wire n_1_0_610; + wire n_1_0_611; + wire n_1_0_612; + wire n_1_0_613; + wire n_1_0_614; + wire n_1_0_615; + wire n_1_0_616; + wire n_1_0_617; + wire n_1_0_618; + wire n_1_0_619; + wire n_1_0_620; + wire n_1_0_621; + wire n_1_0_622; + wire n_1_0_623; + wire n_1_0_624; + wire n_1_0_625; + wire n_1_0_626; + wire n_1_0_627; + wire n_1_0_628; + wire n_1_0_629; + wire n_1_0_630; + wire n_1_0_631; + wire n_1_0_632; + wire n_1_0_633; + wire n_1_0_634; + wire n_1_0_635; + wire n_1_0_636; + wire n_1_0_637; + wire n_1_0_638; + wire n_1_0_639; + wire n_1_0_640; + wire n_1_0_641; + wire n_1_0_642; + wire n_1_0_643; + wire n_1_0_644; + wire n_1_0_645; + wire n_1_0_646; + wire n_1_0_647; + wire n_1_0_648; + wire n_1_0_649; + wire n_1_0_650; + wire n_1_0_651; + wire n_1_0_652; + wire n_1_0_653; + wire n_1_0_654; + wire n_1_0_655; + wire n_1_0_656; + wire n_1_0_657; + wire n_1_0_658; + wire n_1_0_659; + wire n_1_0_660; + wire n_1_0_661; + wire n_1_0_662; + wire n_1_0_663; + wire n_1_0_664; + wire n_1_0_665; + wire n_1_0_666; + wire n_1_0_667; + wire n_1_0_668; + wire n_1_0_669; + wire n_1_0_670; + wire n_1_0_671; + wire n_1_0_672; + wire n_1_0_673; + wire n_1_0_674; + wire n_1_0_675; + wire n_1_0_676; + wire n_1_0_677; + wire n_1_0_678; + wire n_1_0_679; + wire n_1_0_680; + wire n_1_0_681; + wire n_1_0_682; + wire n_1_0_683; + wire n_1_0_684; + wire n_1_0_685; + wire n_1_0_686; + wire n_1_0_687; + wire n_1_0_688; + wire n_1_0_689; + wire n_1_0_690; + wire n_1_0_691; + wire n_1_0_692; + wire n_1_0_693; + wire n_1_0_694; + wire n_1_0_695; + wire n_1_0_696; + wire n_1_0_697; + wire n_1_0_698; + wire n_1_0_699; + wire n_1_0_700; + wire n_1_0_701; + wire n_1_0_702; + wire n_1_0_703; + wire n_1_0_704; + wire n_1_0_705; + wire n_1_0_706; + wire n_1_0_707; + wire n_1_0_708; + wire n_1_0_709; + wire n_1_0_710; + wire n_1_0_711; + wire n_1_0_712; + wire n_1_0_713; + wire n_1_0_714; + wire n_1_0_715; + wire n_1_0_716; + wire n_1_0_717; + wire n_1_0_718; + wire n_1_0_719; + wire n_1_0_720; + wire n_1_0_721; + wire n_1_0_722; + wire n_1_0_723; + wire n_1_0_724; + wire n_1_0_725; + wire n_1_0_726; + wire n_1_0_727; + wire n_1_0_728; + wire n_1_0_729; + wire n_1_0_730; + wire n_1_0_731; + wire n_1_0_732; + wire n_1_0_733; + wire n_1_0_734; + wire n_1_0_735; + wire n_1_0_736; + wire n_1_0_737; + wire n_1_0_738; + wire n_1_0_739; + wire n_1_0_740; + wire n_1_0_741; + wire n_1_0_742; + wire n_1_0_743; + wire n_1_0_744; + wire n_1_0_745; + wire n_1_0_746; + wire n_1_0_747; + wire n_1_0_748; + wire n_1_0_749; + wire n_1_0_750; + wire n_1_0_751; + wire n_1_0_752; + wire n_1_0_753; + wire n_1_0_754; + wire n_1_0_755; + wire n_1_0_756; + wire n_1_0_757; + wire n_1_0_758; + wire n_1_0_759; + wire n_1_0_760; + wire n_1_0_761; + wire n_1_0_762; + wire n_1_0_763; + wire n_1_0_764; + wire n_1_0_765; + wire n_1_0_766; + wire n_1_0_767; + wire n_1_0_768; + wire n_1_0_769; + wire n_1_0_770; + wire n_1_0_771; + wire n_1_0_772; + wire n_1_0_773; + wire n_1_0_774; + wire n_1_0_775; + wire n_1_0_776; + wire n_1_0_777; + wire n_1_0_778; + wire n_1_0_779; + wire n_1_0_780; + wire n_1_0_781; + wire n_1_0_782; + wire n_1_0_783; + wire n_1_0_784; + wire n_1_0_785; + wire n_1_0_786; + wire n_1_0_787; + wire n_1_0_788; + wire n_1_0_789; + wire n_1_0_790; + wire n_1_0_791; + wire n_1_0_792; + wire n_1_0_793; + wire n_1_0_794; + wire n_1_0_795; + wire n_1_0_796; + wire n_1_0_797; + wire n_1_0_798; + wire n_1_0_799; + wire n_1_0_800; + wire n_1_0_801; + wire n_1_0_802; + wire n_1_0_803; + wire n_1_0_804; + wire n_1_0_805; + wire n_1_0_806; + wire n_1_0_807; + wire n_1_0_808; + wire n_1_0_809; + wire n_1_0_810; + wire n_1_0_811; + wire n_1_0_812; + wire n_1_0_813; + wire n_1_0_814; + wire n_1_0_815; + wire n_1_0_816; + wire n_1_0_817; + wire n_1_0_818; + wire n_1_0_819; + wire n_1_0_820; + wire n_1_0_821; + wire n_1_0_822; + wire n_1_0_823; + wire n_1_0_824; + wire n_1_0_825; + wire n_1_0_826; + wire n_1_0_827; + wire n_1_0_828; + wire n_1_0_829; + wire n_1_0_830; + wire n_1_0_831; + wire n_1_0_832; + wire n_1_0_833; + wire n_1_0_834; + wire n_1_0_835; + wire n_1_0_836; + wire n_1_0_837; + wire n_1_0_838; + wire n_1_0_839; + wire n_1_0_840; + wire n_1_0_841; + wire n_1_0_842; + wire n_1_0_843; + wire n_1_0_844; + wire n_1_0_845; + wire n_1_0_846; + wire n_1_0_847; + wire n_1_0_848; + wire n_1_0_849; + wire n_1_0_850; + wire n_1_0_851; + wire n_1_0_852; + wire n_1_0_853; + wire n_1_0_854; + wire n_1_0_855; + wire n_1_0_856; + wire n_1_0_857; + wire n_1_0_858; + wire n_1_0_859; + wire n_1_0_860; + wire n_1_0_861; + wire n_1_0_862; + wire n_1_0_863; + wire n_1_0_864; + wire n_1_0_865; + wire n_1_0_866; + wire n_1_0_867; + wire n_1_0_868; + wire n_1_0_869; + wire n_1_0_870; + wire n_1_0_871; + wire n_1_0_872; + wire n_1_0_873; + wire n_1_0_874; + wire n_1_0_875; + wire n_1_0_876; + wire n_1_0_877; + wire n_1_0_878; + wire n_1_0_879; + wire n_1_0_880; + wire n_1_0_881; + wire n_1_0_882; + wire n_1_0_883; + wire n_1_0_884; + wire n_1_0_885; + wire n_1_0_886; + wire n_1_0_887; + wire n_1_0_888; + wire n_1_0_889; + wire n_1_0_890; + wire n_1_0_891; + wire n_1_0_892; + wire n_1_0_893; + wire n_1_0_894; + wire n_1_0_895; + wire n_1_0_896; + wire n_1_0_897; + wire n_1_0_898; + wire n_1_0_899; + wire n_1_0_900; + wire n_1_0_901; + wire n_1_0_902; + wire n_1_0_903; + wire n_1_0_904; + wire n_1_0_905; + wire n_1_0_906; + wire n_1_0_907; + wire n_1_0_908; + wire n_1_0_909; + wire n_1_0_910; + wire n_1_0_911; + wire n_1_0_912; + wire n_1_0_913; + wire n_1_0_914; + wire n_1_0_915; + wire n_1_0_916; + wire n_1_0_917; + wire n_1_0_918; + wire n_1_0_919; + wire n_1_0_920; + wire n_1_0_921; + wire n_1_0_922; + wire n_1_0_923; + wire n_1_0_924; + wire n_1_0_925; + wire n_1_0_926; + wire n_1_0_927; + wire n_1_0_928; + wire n_1_0_929; + wire n_1_0_930; + wire n_1_0_931; + wire n_1_0_932; + wire n_1_0_933; + wire n_1_0_934; + wire n_1_0_935; + wire n_1_0_936; + wire n_1_0_937; + wire n_1_0_938; + wire n_1_0_939; + wire n_1_0_940; + wire n_1_0_941; + wire n_1_0_942; + wire n_1_0_943; + wire n_1_0_944; + wire n_1_0_945; + wire n_1_0_946; + wire n_1_0_947; + wire n_1_0_948; + wire n_1_0_949; + wire n_1_0_950; + wire n_1_0_951; + wire n_1_0_952; + wire n_1_0_953; + wire n_1_0_954; + wire n_1_0_955; + wire n_1_0_956; + wire n_1_0_957; + wire n_1_0_958; + wire n_1_0_959; + wire n_1_0_960; + wire n_1_0_961; + wire n_1_0_962; + wire n_1_0_963; + wire n_1_0_964; + wire n_1_0_965; + wire n_1_0_966; + wire n_1_0_967; + wire n_1_0_968; + wire n_1_0_969; + wire n_1_0_970; + wire n_1_0_971; + wire n_1_0_972; + wire n_1_0_973; + wire n_1_0_974; + wire n_1_0_975; + wire n_1_0_976; + wire n_1_0_977; + wire n_1_0_978; + wire n_1_0_979; + wire n_1_0_980; + wire n_1_0_981; + wire n_1_0_982; + wire n_1_0_983; + wire n_1_0_984; + wire n_1_0_985; + wire n_1_0_986; + wire n_1_0_987; + wire n_1_0_988; + wire n_1_0_989; + wire n_1_0_990; + wire n_1_0_991; + wire n_1_0_992; + wire n_1_0_993; + wire n_1_0_994; + wire n_1_0_995; + wire n_1_0_996; + wire n_1_0_997; + wire n_1_0_998; + wire n_1_0_999; + wire n_1_0_1000; + wire n_1_0_1001; + wire n_1_0_1002; + wire n_1_0_1003; + wire n_1_0_1004; + wire n_1_0_1005; + wire n_1_0_1006; + wire n_1_0_1007; + wire n_1_0_1008; + wire n_1_0_1009; + wire n_1_0_1010; + wire n_1_0_1011; + wire n_1_0_1012; + wire n_1_0_1013; + wire n_1_0_1014; + wire n_1_0_1015; + wire n_1_0_1016; + wire n_1_0_1017; + wire n_1_0_1018; + wire n_1_0_1019; + wire n_1_0_1020; + wire n_1_0_1021; + wire n_1_0_1022; + wire n_1_0_1023; + wire n_1_0_1024; + wire n_1_0_1025; + wire n_1_0_1026; + wire n_1_0_1027; + wire n_1_0_1028; + wire n_1_0_1029; + wire n_1_0_1030; + wire n_1_0_1031; + wire n_1_0_1032; + wire n_1_0_1033; + wire n_1_0_1034; + wire n_1_0_1035; + wire n_1_0_1036; + wire n_1_0_1037; + wire n_1_0_1038; + wire n_1_0_1039; + wire n_1_0_1040; + wire n_1_0_1041; + wire n_1_0_1042; + wire n_1_0_1043; + wire n_1_0_1044; + wire n_1_0_1045; + wire n_1_0_1046; + wire n_1_0_1047; + wire n_1_0_1048; + wire n_1_0_1049; + wire n_1_0_1050; + wire n_1_0_1051; + wire n_1_0_1052; + wire n_1_0_1053; + wire n_1_0_1054; + wire n_1_0_1055; + wire n_1_0_1056; + wire n_1_0_1057; + wire n_1_0_1058; + wire n_1_0_1059; + wire n_1_0_1060; + wire n_1_0_1061; + wire n_1_0_1062; + wire n_1_0_1063; + wire n_1_0_1064; + wire n_1_0_1065; + wire n_1_0_1066; + wire n_1_0_1067; + wire n_1_0_1068; + wire n_1_0_1069; + wire n_1_0_1070; + wire n_1_0_1071; + wire n_1_0_1072; + wire n_1_0_1073; + wire n_1_0_1074; + wire n_1_0_1075; + wire n_1_0_1076; + wire n_1_0_1077; + wire n_1_0_1078; + wire n_1_0_1079; + wire n_1_0_1080; + wire n_1_0_1081; + wire n_1_0_1082; + wire n_1_0_1083; + wire n_1_0_1084; + wire n_1_0_1085; + wire n_1_0_1086; + wire n_1_0_1087; + wire n_1_0_1088; + wire n_1_0_1089; + wire n_1_0_1090; + wire n_1_0_1091; + wire n_1_0_1092; + wire n_1_0_1093; + wire n_1_0_1094; + wire n_1_0_1095; + wire n_1_0_1096; + wire n_1_0_1097; + wire n_1_0_1098; + wire n_1_0_1099; + wire n_1_0_1100; + wire n_1_0_1101; + wire n_1_0_1102; + wire n_1_0_1103; + wire n_1_0_1104; + wire n_1_0_1105; + wire n_1_0_1106; + wire n_1_0_1107; + wire n_1_0_1108; + wire n_1_0_1109; + wire n_1_0_1110; + wire n_1_0_1111; + wire n_1_0_1112; + wire n_1_0_1113; + wire n_1_0_1114; + wire n_1_0_1115; + wire n_1_0_1116; + wire n_1_0_1117; + wire n_1_0_1118; + wire n_1_0_1119; + wire n_1_0_1120; + wire n_1_0_1121; + wire n_1_0_1122; + wire n_1_0_1123; + wire n_1_0_1124; + wire n_1_0_1125; + wire n_1_0_1126; + wire n_1_0_1127; + wire n_1_0_1128; + wire n_1_0_1129; + wire n_1_0_1130; + wire n_1_0_1131; + wire n_1_0_1132; + wire n_1_0_1133; + wire n_1_0_1134; + wire n_1_0_1135; + wire n_1_0_1136; + wire n_1_0_1137; + wire n_1_0_1138; + wire n_1_0_1139; + wire n_1_0_1140; + wire n_1_0_1141; + wire n_1_0_1142; + wire n_1_0_1143; + wire n_1_0_1144; + wire n_1_0_1145; + wire n_1_0_1146; + wire n_1_0_1147; + wire n_1_0_1148; + wire n_1_0_1149; + wire n_1_0_1150; + wire n_1_0_1151; + wire n_1_0_1152; + wire n_1_0_1153; + wire n_1_0_1154; + wire n_1_0_1155; + wire n_1_0_1156; + wire n_1_0_1157; + wire n_1_0_1158; + wire n_1_0_1159; + wire n_1_0_1160; + wire n_1_0_1161; + wire n_1_0_1162; + wire n_1_0_1163; + wire n_1_0_1164; + wire n_1_0_1165; + wire n_1_0_1166; + wire n_1_0_1167; + wire n_1_0_1168; + wire n_1_0_1169; + wire n_1_0_1170; + wire n_1_0_1171; + wire n_1_0_1172; + wire n_1_0_1173; + wire n_1_0_1174; + wire n_1_0_1175; + wire n_1_0_1176; + wire n_1_0_1177; + wire n_1_0_1178; + wire n_1_0_1179; + wire n_1_0_1180; + wire n_1_0_1181; + wire n_1_0_1182; + wire n_1_0_1183; + wire n_1_0_1184; + wire n_1_0_1185; + wire n_1_0_1186; + wire n_1_0_1187; + wire n_1_0_1188; + wire n_1_0_1189; + wire n_1_0_1190; + wire n_1_0_1191; + wire n_1_0_1192; + wire n_1_0_1193; + wire n_1_0_1194; + wire n_1_0_1195; + wire n_1_0_1196; + wire n_1_0_1197; + wire n_1_0_1198; + wire n_1_0_1199; + wire n_1_0_1200; + wire n_1_0_1201; + wire n_1_0_1202; + wire n_1_0_1203; + wire n_1_0_1204; + wire n_1_0_1205; + wire n_1_0_1206; + wire n_1_0_1207; + wire n_1_0_1208; + wire n_1_0_1209; + wire n_1_0_1210; + wire n_1_0_1211; + wire n_1_0_1212; + wire n_1_0_1213; + wire n_1_0_1214; + wire n_1_0_1215; + wire n_1_0_1216; + wire n_1_0_1217; + wire n_1_0_1218; + wire n_1_0_1219; + wire n_1_0_1220; + wire n_1_0_1221; + wire n_1_0_1222; + wire n_1_0_1223; + wire n_1_0_1224; + wire n_1_0_1225; + wire n_1_0_1226; + wire n_1_0_1227; + wire n_1_0_1228; + wire n_1_0_1229; + wire n_1_0_1230; + wire n_1_0_1231; + wire n_1_0_1232; + wire n_1_0_1233; + wire n_1_0_1234; + wire n_1_0_1235; + wire n_1_0_1236; + wire n_1_0_1237; + wire n_1_0_1238; + wire n_1_0_1239; + wire n_1_0_1240; + wire n_1_0_1241; + wire n_1_0_1242; + wire n_1_0_1243; + wire n_1_0_1244; + wire n_1_0_1245; + wire n_1_0_1246; + wire n_1_0_1247; + wire n_1_0_1248; + wire n_1_0_1249; + wire n_1_0_1250; + wire n_1_0_1251; + wire n_1_0_1252; + wire n_1_0_1253; + wire n_1_0_1254; + wire n_1_0_1255; + wire n_1_0_1256; + wire n_1_0_1257; + wire n_1_0_1258; + wire n_1_0_1259; + wire n_1_0_1260; + wire n_1_0_1261; + wire n_1_0_1262; + wire n_1_0_1263; + wire n_1_0_1264; + wire n_1_0_1265; + wire n_1_0_1266; + wire n_1_0_1267; + wire n_1_0_1268; + wire n_1_0_1269; + wire n_1_0_1270; + wire n_1_0_1271; + wire n_1_0_1272; + wire n_1_0_1273; + wire n_1_0_1274; + wire n_1_0_1275; + wire n_1_0_1276; + wire n_1_0_1277; + wire n_1_0_1278; + wire n_1_0_1279; + wire n_1_0_1280; + wire n_1_0_1281; + wire n_1_0_1282; + wire n_1_0_1283; + wire n_1_0_1284; + wire n_1_0_1285; + wire n_1_0_1286; + wire n_1_0_1287; + wire n_1_0_1288; + wire n_1_0_1289; + wire n_1_0_1290; + wire n_1_0_1291; + wire n_1_0_1292; + wire n_1_0_1293; + wire n_1_0_1294; + wire n_1_0_1295; + wire n_1_0_1296; + wire n_1_0_1297; + wire n_1_0_1298; + wire n_1_0_1299; + wire n_1_0_1300; + wire n_1_0_1301; + wire n_1_0_1302; + wire n_1_0_1303; + wire n_1_0_1304; + wire n_1_0_1305; + wire n_1_0_1306; + wire n_1_0_1307; + wire n_1_0_1308; + wire n_1_0_1309; + + INV_X1_LVT i_0_0_79 (.A(reset), .ZN(n_0_0_16)); + AND2_X1_LVT i_0_0_31 (.A1(n_0_0_16), .A2(WRd[31]), .ZN(registers[31])); + INV_X1_LVT i_0_0_81 (.A(Rd[1]), .ZN(n_0_0_18)); + INV_X1_LVT i_0_0_80 (.A(Rd[0]), .ZN(n_0_0_17)); + NAND3_X1_LVT i_0_0_69 (.A1(n_0_0_18), .A2(n_0_0_17), .A3(Rd[2]), .ZN(n_0_0_9)); + NAND3_X1_LVT i_0_0_41 (.A1(Rd[3]), .A2(WrReg), .A3(Rd[4]), .ZN(n_0_0_1)); + OAI21_X1_LVT i_0_0_35 (.A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_1), .ZN(n_0_28)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[28]_reg (.CK(clk), .E(n_0_28), + .SE(dftIn), .GCK(n_0_58)); + SDFF_X1_LVT \registers_reg[28][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_28__ap[31]), .CK(n_0_58), .Q(registers_28__ap[31]), .QN()); + INV_X1_LVT i_1_0_1370 (.A(Rs1[0]), .ZN(n_1_0_1306)); + NAND3_X1_LVT i_1_0_1354 (.A1(n_1_0_1306), .A2(Rs1[3]), .A3(Rs1[4]), .ZN( + n_1_0_1290)); + INV_X1_LVT i_1_0_1373 (.A(Rs1[2]), .ZN(n_1_0_1309)); + OR2_X1_LVT i_1_0_1348 (.A1(n_1_0_1309), .A2(Rs1[1]), .ZN(n_1_0_1284)); + NOR2_X1_LVT i_1_0_1347 (.A1(n_1_0_1290), .A2(n_1_0_1284), .ZN(n_1_0_1283)); + NOR4_X1_LVT i_1_0_1342 (.A1(n_1_0_1284), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), + .ZN(n_1_0_1278)); + INV_X1_LVT i_0_0_83 (.A(WrReg), .ZN(n_0_0_20)); + OR3_X1_LVT i_0_0_77 (.A1(n_0_0_20), .A2(Rd[4]), .A3(Rd[3]), .ZN(n_0_0_14)); + OAI21_X1_LVT i_0_0_68 (.A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_9), .ZN(n_0_4)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[4]_reg (.CK(clk), .E(n_0_4), + .SE(dftIn), .GCK(n_0_34)); + SDFF_X1_LVT \registers_reg[4][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_4__ap[31]), .CK(n_0_34), .Q(registers_4__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1320 (.A1(registers_28__ap[31]), .A2(n_1_0_1283), .B1( + n_1_0_1278), .B2(registers_4__ap[31]), .ZN(n_1_0_1256)); + NAND2_X1_LVT i_0_0_70 (.A1(n_0_0_18), .A2(n_0_0_17), .ZN(n_0_0_10)); + INV_X1_LVT i_0_0_82 (.A(Rd[4]), .ZN(n_0_0_19)); + OR3_X1_LVT i_0_0_51 (.A1(n_0_0_20), .A2(n_0_0_19), .A3(Rd[3]), .ZN(n_0_0_3)); + OR2_X1_LVT i_0_0_50 (.A1(n_0_0_3), .A2(Rd[2]), .ZN(n_0_0_2)); + OAI21_X1_LVT i_0_0_49 (.A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_2), .ZN(n_0_16)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[16]_reg (.CK(clk), .E(n_0_16), + .SE(dftIn), .GCK(n_0_46)); + SDFF_X1_LVT \registers_reg[16][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_16__ap[31]), .CK(n_0_46), .Q(registers_16__ap[31]), .QN()); + INV_X1_LVT i_1_0_1371 (.A(Rs1[3]), .ZN(n_1_0_1307)); + NAND3_X1_LVT i_1_0_1363 (.A1(n_1_0_1307), .A2(n_1_0_1306), .A3(Rs1[4]), + .ZN(n_1_0_1299)); + OR2_X1_LVT i_1_0_1357 (.A1(Rs1[1]), .A2(Rs1[2]), .ZN(n_1_0_1293)); + NOR2_X1_LVT i_1_0_1331 (.A1(n_1_0_1299), .A2(n_1_0_1293), .ZN(n_1_0_1267)); + NAND2_X1_LVT i_1_0_1365 (.A1(Rs1[1]), .A2(Rs1[2]), .ZN(n_1_0_1301)); + NAND3_X1_LVT i_1_0_1344 (.A1(Rs1[4]), .A2(Rs1[3]), .A3(Rs1[0]), .ZN( + n_1_0_1280)); + NOR2_X1_LVT i_1_0_1330 (.A1(n_1_0_1301), .A2(n_1_0_1280), .ZN(n_1_0_1266)); + NAND3_X1_LVT i_0_0_63 (.A1(Rd[2]), .A2(Rd[1]), .A3(Rd[0]), .ZN(n_0_0_6)); + OAI21_X1_LVT i_0_0_32 (.A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_1), .ZN(n_0_31)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[31]_reg (.CK(clk), .E(n_0_31), + .SE(dftIn), .GCK(n_0_61)); + SDFF_X1_LVT \registers_reg[31][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_31__ap[31]), .CK(n_0_61), .Q(registers_31__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1329 (.A1(registers_16__ap[31]), .A2(n_1_0_1267), .B1( + n_1_0_1266), .B2(registers_31__ap[31]), .ZN(n_1_0_1265)); + NAND3_X1_LVT i_0_0_65 (.A1(n_0_0_17), .A2(Rd[1]), .A3(Rd[2]), .ZN(n_0_0_7)); + OAI21_X1_LVT i_0_0_64 (.A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_7), .ZN(n_0_6)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[6]_reg (.CK(clk), .E(n_0_6), + .SE(dftIn), .GCK(n_0_36)); + SDFF_X1_LVT \registers_reg[6][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_6__ap[31]), .CK(n_0_36), .Q(registers_6__ap[31]), .QN()); + NOR4_X1_LVT i_1_0_1364 (.A1(n_1_0_1301), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), + .ZN(n_1_0_1300)); + INV_X1_LVT i_1_0_1372 (.A(Rs1[4]), .ZN(n_1_0_1308)); + NAND3_X1_LVT i_1_0_1339 (.A1(n_1_0_1308), .A2(n_1_0_1307), .A3(Rs1[0]), + .ZN(n_1_0_1275)); + NOR2_X1_LVT i_1_0_1338 (.A1(n_1_0_1293), .A2(n_1_0_1275), .ZN(n_1_0_1274)); + NAND2_X1_LVT i_0_0_78 (.A1(n_0_0_18), .A2(Rd[0]), .ZN(n_0_0_15)); + OR2_X1_LVT i_0_0_76 (.A1(n_0_0_14), .A2(Rd[2]), .ZN(n_0_0_13)); + OAI21_X1_LVT i_0_0_75 (.A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_13), .ZN(n_0_1)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[1]_reg (.CK(clk), .E(n_0_1), + .SE(dftIn), .GCK(n_0_0)); + SDFF_X1_LVT \registers_reg[1][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_1__ap[31]), .CK(n_0_0), .Q(registers_1__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1319 (.A1(registers_6__ap[31]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[31]), .ZN(n_1_0_1255)); + OAI21_X1_LVT i_0_0_42 (.A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_3), .ZN(n_0_23)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[23]_reg (.CK(clk), .E(n_0_23), + .SE(dftIn), .GCK(n_0_53)); + SDFF_X1_LVT \registers_reg[23][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_23__ap[31]), .CK(n_0_53), .Q(registers_23__ap[31]), .QN()); + NAND3_X1_LVT i_1_0_1360 (.A1(n_1_0_1307), .A2(Rs1[0]), .A3(Rs1[4]), .ZN( + n_1_0_1296)); + NOR2_X1_LVT i_1_0_1328 (.A1(n_1_0_1301), .A2(n_1_0_1296), .ZN(n_1_0_1264)); + NOR2_X1_LVT i_1_0_1327 (.A1(n_1_0_1301), .A2(n_1_0_1275), .ZN(n_1_0_1263)); + OAI21_X1_LVT i_0_0_62 (.A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_6), .ZN(n_0_7)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[7]_reg (.CK(clk), .E(n_0_7), + .SE(dftIn), .GCK(n_0_37)); + SDFF_X1_LVT \registers_reg[7][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_7__ap[31]), .CK(n_0_37), .Q(registers_7__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1326 (.A1(registers_23__ap[31]), .A2(n_1_0_1264), .B1( + n_1_0_1263), .B2(registers_7__ap[31]), .ZN(n_1_0_1262)); + INV_X1_LVT i_1_0_1325 (.A(n_1_0_1262), .ZN(n_1_0_1261)); + NAND2_X1_LVT i_1_0_1362 (.A1(n_1_0_1309), .A2(Rs1[1]), .ZN(n_1_0_1298)); + NOR2_X1_LVT i_1_0_1359 (.A1(n_1_0_1298), .A2(n_1_0_1296), .ZN(n_1_0_1295)); + NAND2_X1_LVT i_0_0_72 (.A1(Rd[1]), .A2(Rd[0]), .ZN(n_0_0_11)); + OAI21_X1_LVT i_0_0_46 (.A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_2), .ZN(n_0_19)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[19]_reg (.CK(clk), .E(n_0_19), + .SE(dftIn), .GCK(n_0_49)); + SDFF_X1_LVT \registers_reg[19][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_19__ap[31]), .CK(n_0_49), .Q(registers_19__ap[31]), .QN()); + NAND3_X1_LVT i_0_0_67 (.A1(n_0_0_18), .A2(Rd[0]), .A3(Rd[2]), .ZN(n_0_0_8)); + OAI21_X1_LVT i_0_0_66 (.A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_8), .ZN(n_0_5)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[5]_reg (.CK(clk), .E(n_0_5), + .SE(dftIn), .GCK(n_0_35)); + SDFF_X1_LVT \registers_reg[5][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_5__ap[31]), .CK(n_0_35), .Q(registers_5__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1337 (.A1(n_1_0_1284), .A2(n_1_0_1275), .ZN(n_1_0_1273)); + AOI221_X1_LVT i_1_0_1318 (.A(n_1_0_1261), .B1(n_1_0_1295), .B2( + registers_19__ap[31]), .C1(registers_5__ap[31]), .C2(n_1_0_1273), .ZN( + n_1_0_1254)); + NAND2_X1_LVT i_0_0_74 (.A1(n_0_0_17), .A2(Rd[1]), .ZN(n_0_0_12)); + NAND3_X1_LVT i_0_0_61 (.A1(n_0_0_19), .A2(WrReg), .A3(Rd[3]), .ZN(n_0_0_5)); + OR2_X1_LVT i_0_0_60 (.A1(n_0_0_5), .A2(Rd[2]), .ZN(n_0_0_4)); + OAI21_X1_LVT i_0_0_57 (.A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_4), .ZN(n_0_10)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[10]_reg (.CK(clk), .E(n_0_10), + .SE(dftIn), .GCK(n_0_40)); + SDFF_X1_LVT \registers_reg[10][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_10__ap[31]), .CK(n_0_40), .Q(registers_10__ap[31]), .QN()); + NAND3_X1_LVT i_1_0_1352 (.A1(n_1_0_1308), .A2(n_1_0_1306), .A3(Rs1[3]), + .ZN(n_1_0_1288)); + NOR2_X1_LVT i_1_0_1351 (.A1(n_1_0_1298), .A2(n_1_0_1288), .ZN(n_1_0_1287)); + NOR2_X1_LVT i_1_0_1349 (.A1(n_1_0_1298), .A2(n_1_0_1290), .ZN(n_1_0_1285)); + OR2_X1_LVT i_0_0_40 (.A1(n_0_0_1), .A2(Rd[2]), .ZN(n_0_0_0)); + OAI21_X1_LVT i_0_0_37 (.A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_0), .ZN(n_0_26)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[26]_reg (.CK(clk), .E(n_0_26), + .SE(dftIn), .GCK(n_0_56)); + SDFF_X1_LVT \registers_reg[26][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_26__ap[31]), .CK(n_0_56), .Q(registers_26__ap[31]), .QN()); + OAI21_X1_LVT i_0_0_59 (.A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_4), .ZN(n_0_8)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[8]_reg (.CK(clk), .E(n_0_8), + .SE(dftIn), .GCK(n_0_38)); + SDFF_X1_LVT \registers_reg[8][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_8__ap[31]), .CK(n_0_38), .Q(registers_8__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1346 (.A1(n_1_0_1293), .A2(n_1_0_1288), .ZN(n_1_0_1282)); + AOI222_X1_LVT i_1_0_1317 (.A1(registers_10__ap[31]), .A2(n_1_0_1287), + .B1(n_1_0_1285), .B2(registers_26__ap[31]), .C1(registers_8__ap[31]), + .C2(n_1_0_1282), .ZN(n_1_0_1253)); + NAND4_X1_LVT i_1_0_1316 (.A1(n_1_0_1265), .A2(n_1_0_1255), .A3(n_1_0_1254), + .A4(n_1_0_1253), .ZN(n_1_0_1252)); + NAND3_X1_LVT i_1_0_1356 (.A1(n_1_0_1308), .A2(Rs1[3]), .A3(Rs1[0]), .ZN( + n_1_0_1292)); + NOR2_X1_LVT i_1_0_1355 (.A1(n_1_0_1293), .A2(n_1_0_1292), .ZN(n_1_0_1291)); + OAI21_X1_LVT i_0_0_58 (.A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_4), .ZN(n_0_9)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[9]_reg (.CK(clk), .E(n_0_9), + .SE(dftIn), .GCK(n_0_39)); + SDFF_X1_LVT \registers_reg[9][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_9__ap[31]), .CK(n_0_39), .Q(registers_9__ap[31]), .QN()); + OAI21_X1_LVT i_0_0_34 (.A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_1), .ZN(n_0_29)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[29]_reg (.CK(clk), .E(n_0_29), + .SE(dftIn), .GCK(n_0_59)); + SDFF_X1_LVT \registers_reg[29][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_29__ap[31]), .CK(n_0_59), .Q(registers_29__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1340 (.A1(n_1_0_1284), .A2(n_1_0_1280), .ZN(n_1_0_1276)); + AOI221_X1_LVT i_1_0_1315 (.A(n_1_0_1252), .B1(n_1_0_1291), .B2( + registers_9__ap[31]), .C1(registers_29__ap[31]), .C2(n_1_0_1276), .ZN( + n_1_0_1251)); + OAI21_X1_LVT i_0_0_47 (.A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_2), .ZN(n_0_18)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[18]_reg (.CK(clk), .E(n_0_18), + .SE(dftIn), .GCK(n_0_48)); + SDFF_X1_LVT \registers_reg[18][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_18__ap[31]), .CK(n_0_48), .Q(registers_18__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1361 (.A1(n_1_0_1299), .A2(n_1_0_1298), .ZN(n_1_0_1297)); + NOR2_X1_LVT i_1_0_1336 (.A1(n_1_0_1301), .A2(n_1_0_1290), .ZN(n_1_0_1272)); + OAI21_X1_LVT i_0_0_33 (.A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_1), .ZN(n_0_30)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[30]_reg (.CK(clk), .E(n_0_30), + .SE(dftIn), .GCK(n_0_60)); + SDFF_X1_LVT \registers_reg[30][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_30__ap[31]), .CK(n_0_60), .Q(registers_30__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1314 (.A1(registers_18__ap[31]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[31]), .ZN(n_1_0_1250)); + OAI21_X1_LVT i_0_0_39 (.A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_0), .ZN(n_0_24)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[24]_reg (.CK(clk), .E(n_0_24), + .SE(dftIn), .GCK(n_0_54)); + SDFF_X1_LVT \registers_reg[24][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_24__ap[31]), .CK(n_0_54), .Q(registers_24__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1353 (.A1(n_1_0_1293), .A2(n_1_0_1290), .ZN(n_1_0_1289)); + NOR2_X1_LVT i_1_0_1324 (.A1(n_1_0_1288), .A2(n_1_0_1284), .ZN(n_1_0_1260)); + OAI21_X1_LVT i_0_0_55 (.A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_5), .ZN(n_0_12)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[12]_reg (.CK(clk), .E(n_0_12), + .SE(dftIn), .GCK(n_0_42)); + SDFF_X1_LVT \registers_reg[12][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_12__ap[31]), .CK(n_0_42), .Q(registers_12__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1313 (.A1(registers_24__ap[31]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[31]), .ZN(n_1_0_1249)); + OAI21_X1_LVT i_0_0_43 (.A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_3), .ZN(n_0_22)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[22]_reg (.CK(clk), .E(n_0_22), + .SE(dftIn), .GCK(n_0_52)); + SDFF_X1_LVT \registers_reg[22][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_22__ap[31]), .CK(n_0_52), .Q(registers_22__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1358 (.A1(n_1_0_1301), .A2(n_1_0_1299), .ZN(n_1_0_1294)); + NOR2_X1_LVT i_1_0_1323 (.A1(n_1_0_1296), .A2(n_1_0_1284), .ZN(n_1_0_1259)); + OAI21_X1_LVT i_0_0_44 (.A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_3), .ZN(n_0_21)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[21]_reg (.CK(clk), .E(n_0_21), + .SE(dftIn), .GCK(n_0_51)); + SDFF_X1_LVT \registers_reg[21][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_21__ap[31]), .CK(n_0_51), .Q(registers_21__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1312 (.A1(registers_22__ap[31]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[31]), .ZN(n_1_0_1248)); + NAND3_X1_LVT i_1_0_1311 (.A1(n_1_0_1250), .A2(n_1_0_1249), .A3(n_1_0_1248), + .ZN(n_1_0_1247)); + NOR2_X1_LVT i_1_0_1335 (.A1(n_1_0_1296), .A2(n_1_0_1293), .ZN(n_1_0_1271)); + OAI21_X1_LVT i_0_0_48 (.A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_2), .ZN(n_0_17)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[17]_reg (.CK(clk), .E(n_0_17), + .SE(dftIn), .GCK(n_0_47)); + SDFF_X1_LVT \registers_reg[17][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_17__ap[31]), .CK(n_0_47), .Q(registers_17__ap[31]), .QN()); + OAI21_X1_LVT i_0_0_45 (.A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_3), .ZN(n_0_20)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[20]_reg (.CK(clk), .E(n_0_20), + .SE(dftIn), .GCK(n_0_50)); + SDFF_X1_LVT \registers_reg[20][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_20__ap[31]), .CK(n_0_50), .Q(registers_20__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1345 (.A1(n_1_0_1299), .A2(n_1_0_1284), .ZN(n_1_0_1281)); + AOI221_X1_LVT i_1_0_1310 (.A(n_1_0_1247), .B1(n_1_0_1271), .B2( + registers_17__ap[31]), .C1(registers_20__ap[31]), .C2(n_1_0_1281), + .ZN(n_1_0_1246)); + OAI21_X1_LVT i_0_0_36 (.A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_0), .ZN(n_0_27)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[27]_reg (.CK(clk), .E(n_0_27), + .SE(dftIn), .GCK(n_0_57)); + SDFF_X1_LVT \registers_reg[27][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_27__ap[31]), .CK(n_0_57), .Q(registers_27__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1343 (.A1(n_1_0_1298), .A2(n_1_0_1280), .ZN(n_1_0_1279)); + NOR2_X1_LVT i_1_0_1334 (.A1(n_1_0_1298), .A2(n_1_0_1292), .ZN(n_1_0_1270)); + OAI21_X1_LVT i_0_0_56 (.A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_4), .ZN(n_0_11)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[11]_reg (.CK(clk), .E(n_0_11), + .SE(dftIn), .GCK(n_0_41)); + SDFF_X1_LVT \registers_reg[11][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_11__ap[31]), .CK(n_0_41), .Q(registers_11__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1309 (.A1(registers_27__ap[31]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[31]), .ZN(n_1_0_1245)); + OAI21_X1_LVT i_0_0_54 (.A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_5), .ZN(n_0_13)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[13]_reg (.CK(clk), .E(n_0_13), + .SE(dftIn), .GCK(n_0_43)); + SDFF_X1_LVT \registers_reg[13][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_13__ap[31]), .CK(n_0_43), .Q(registers_13__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1341 (.A1(n_1_0_1292), .A2(n_1_0_1284), .ZN(n_1_0_1277)); + NOR2_X1_LVT i_1_0_1333 (.A1(n_1_0_1293), .A2(n_1_0_1280), .ZN(n_1_0_1269)); + OAI21_X1_LVT i_0_0_38 (.A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_0), .ZN(n_0_25)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[25]_reg (.CK(clk), .E(n_0_25), + .SE(dftIn), .GCK(n_0_55)); + SDFF_X1_LVT \registers_reg[25][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_25__ap[31]), .CK(n_0_55), .Q(registers_25__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1308 (.A1(registers_13__ap[31]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[31]), .ZN(n_1_0_1244)); + OAI21_X1_LVT i_0_0_52 (.A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_5), .ZN(n_0_15)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[15]_reg (.CK(clk), .E(n_0_15), + .SE(dftIn), .GCK(n_0_45)); + SDFF_X1_LVT \registers_reg[15][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_15__ap[31]), .CK(n_0_45), .Q(registers_15__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1350 (.A1(n_1_0_1301), .A2(n_1_0_1292), .ZN(n_1_0_1286)); + NOR2_X1_LVT i_1_0_1322 (.A1(n_1_0_1301), .A2(n_1_0_1288), .ZN(n_1_0_1258)); + OAI21_X1_LVT i_0_0_53 (.A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_5), .ZN(n_0_14)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[14]_reg (.CK(clk), .E(n_0_14), + .SE(dftIn), .GCK(n_0_44)); + SDFF_X1_LVT \registers_reg[14][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_14__ap[31]), .CK(n_0_44), .Q(registers_14__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1307 (.A1(registers_15__ap[31]), .A2(n_1_0_1286), .B1( + n_1_0_1258), .B2(registers_14__ap[31]), .ZN(n_1_0_1243)); + NAND3_X1_LVT i_1_0_1306 (.A1(n_1_0_1245), .A2(n_1_0_1244), .A3(n_1_0_1243), + .ZN(n_1_0_1242)); + NOR2_X1_LVT i_1_0_1321 (.A1(n_1_0_1298), .A2(n_1_0_1275), .ZN(n_1_0_1257)); + OAI21_X1_LVT i_0_0_71 (.A(n_0_0_16), .B1(n_0_0_13), .B2(n_0_0_11), .ZN(n_0_3)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[3]_reg (.CK(clk), .E(n_0_3), + .SE(dftIn), .GCK(n_0_33)); + SDFF_X1_LVT \registers_reg[3][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_3__ap[31]), .CK(n_0_33), .Q(registers_3__ap[31]), .QN()); + OAI21_X1_LVT i_0_0_73 (.A(n_0_0_16), .B1(n_0_0_13), .B2(n_0_0_12), .ZN(n_0_2)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[2]_reg (.CK(clk), .E(n_0_2), + .SE(dftIn), .GCK(n_0_32)); + SDFF_X1_LVT \registers_reg[2][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_2__ap[31]), .CK(n_0_32), .Q(registers_2__ap[31]), .QN()); + NOR4_X1_LVT i_1_0_1332 (.A1(n_1_0_1298), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), + .ZN(n_1_0_1268)); + AOI221_X1_LVT i_1_0_1305 (.A(n_1_0_1242), .B1(n_1_0_1257), .B2( + registers_3__ap[31]), .C1(registers_2__ap[31]), .C2(n_1_0_1268), .ZN( + n_1_0_1241)); + NAND4_X1_LVT i_1_0_1304 (.A1(n_1_0_1256), .A2(n_1_0_1251), .A3(n_1_0_1246), + .A4(n_1_0_1241), .ZN(RRs1[31])); + AND2_X1_LVT i_0_0_30 (.A1(n_0_0_16), .A2(WRd[30]), .ZN(registers[30])); + SDFF_X1_LVT \registers_reg[28][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_28__ap[30]), .CK(n_0_58), .Q(registers_28__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[17][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_17__ap[30]), .CK(n_0_47), .Q(registers_17__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1300 (.A1(registers_28__ap[30]), .A2(n_1_0_1283), .B1( + n_1_0_1271), .B2(registers_17__ap[30]), .ZN(n_1_0_1237)); + SDFF_X1_LVT \registers_reg[16][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_16__ap[30]), .CK(n_0_46), .Q(registers_16__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[31][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_31__ap[30]), .CK(n_0_61), .Q(registers_31__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1303 (.A1(registers_16__ap[30]), .A2(n_1_0_1267), .B1( + n_1_0_1266), .B2(registers_31__ap[30]), .ZN(n_1_0_1240)); + SDFF_X1_LVT \registers_reg[6][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_6__ap[30]), .CK(n_0_36), .Q(registers_6__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[1][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_1__ap[30]), .CK(n_0_0), .Q(registers_1__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1299 (.A1(registers_6__ap[30]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[30]), .ZN(n_1_0_1236)); + SDFF_X1_LVT \registers_reg[23][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_23__ap[30]), .CK(n_0_53), .Q(registers_23__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[7][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_7__ap[30]), .CK(n_0_37), .Q(registers_7__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1302 (.A1(registers_23__ap[30]), .A2(n_1_0_1264), .B1( + n_1_0_1263), .B2(registers_7__ap[30]), .ZN(n_1_0_1239)); + INV_X1_LVT i_1_0_1301 (.A(n_1_0_1239), .ZN(n_1_0_1238)); + SDFF_X1_LVT \registers_reg[19][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_19__ap[30]), .CK(n_0_49), .Q(registers_19__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[5][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_5__ap[30]), .CK(n_0_35), .Q(registers_5__ap[30]), .QN()); + AOI221_X1_LVT i_1_0_1298 (.A(n_1_0_1238), .B1(n_1_0_1295), .B2( + registers_19__ap[30]), .C1(registers_5__ap[30]), .C2(n_1_0_1273), .ZN( + n_1_0_1235)); + SDFF_X1_LVT \registers_reg[10][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_10__ap[30]), .CK(n_0_40), .Q(registers_10__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[26][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_26__ap[30]), .CK(n_0_56), .Q(registers_26__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[8][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_8__ap[30]), .CK(n_0_38), .Q(registers_8__ap[30]), .QN()); + AOI222_X1_LVT i_1_0_1297 (.A1(registers_10__ap[30]), .A2(n_1_0_1287), + .B1(n_1_0_1285), .B2(registers_26__ap[30]), .C1(registers_8__ap[30]), + .C2(n_1_0_1282), .ZN(n_1_0_1234)); + NAND4_X1_LVT i_1_0_1296 (.A1(n_1_0_1240), .A2(n_1_0_1236), .A3(n_1_0_1235), + .A4(n_1_0_1234), .ZN(n_1_0_1233)); + SDFF_X1_LVT \registers_reg[9][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_9__ap[30]), .CK(n_0_39), .Q(registers_9__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[29][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_29__ap[30]), .CK(n_0_59), .Q(registers_29__ap[30]), .QN()); + AOI221_X1_LVT i_1_0_1295 (.A(n_1_0_1233), .B1(n_1_0_1291), .B2( + registers_9__ap[30]), .C1(registers_29__ap[30]), .C2(n_1_0_1276), .ZN( + n_1_0_1232)); + SDFF_X1_LVT \registers_reg[18][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_18__ap[30]), .CK(n_0_48), .Q(registers_18__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[30][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_30__ap[30]), .CK(n_0_60), .Q(registers_30__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1294 (.A1(registers_18__ap[30]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[30]), .ZN(n_1_0_1231)); + SDFF_X1_LVT \registers_reg[20][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_20__ap[30]), .CK(n_0_50), .Q(registers_20__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[4][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_4__ap[30]), .CK(n_0_34), .Q(registers_4__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1293 (.A1(registers_20__ap[30]), .A2(n_1_0_1281), .B1( + n_1_0_1278), .B2(registers_4__ap[30]), .ZN(n_1_0_1230)); + SDFF_X1_LVT \registers_reg[22][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_22__ap[30]), .CK(n_0_52), .Q(registers_22__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[21][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_21__ap[30]), .CK(n_0_51), .Q(registers_21__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1292 (.A1(registers_22__ap[30]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[30]), .ZN(n_1_0_1229)); + NAND3_X1_LVT i_1_0_1291 (.A1(n_1_0_1231), .A2(n_1_0_1230), .A3(n_1_0_1229), + .ZN(n_1_0_1228)); + SDFF_X1_LVT \registers_reg[24][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_24__ap[30]), .CK(n_0_54), .Q(registers_24__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[12][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_12__ap[30]), .CK(n_0_42), .Q(registers_12__ap[30]), .QN()); + AOI221_X1_LVT i_1_0_1290 (.A(n_1_0_1228), .B1(n_1_0_1289), .B2( + registers_24__ap[30]), .C1(registers_12__ap[30]), .C2(n_1_0_1260), + .ZN(n_1_0_1227)); + SDFF_X1_LVT \registers_reg[27][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_27__ap[30]), .CK(n_0_57), .Q(registers_27__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[11][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_11__ap[30]), .CK(n_0_41), .Q(registers_11__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1289 (.A1(registers_27__ap[30]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[30]), .ZN(n_1_0_1226)); + SDFF_X1_LVT \registers_reg[13][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_13__ap[30]), .CK(n_0_43), .Q(registers_13__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[25][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_25__ap[30]), .CK(n_0_55), .Q(registers_25__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1288 (.A1(registers_13__ap[30]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[30]), .ZN(n_1_0_1225)); + SDFF_X1_LVT \registers_reg[15][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_15__ap[30]), .CK(n_0_45), .Q(registers_15__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[14][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_14__ap[30]), .CK(n_0_44), .Q(registers_14__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1287 (.A1(registers_15__ap[30]), .A2(n_1_0_1286), .B1( + n_1_0_1258), .B2(registers_14__ap[30]), .ZN(n_1_0_1224)); + NAND3_X1_LVT i_1_0_1286 (.A1(n_1_0_1226), .A2(n_1_0_1225), .A3(n_1_0_1224), + .ZN(n_1_0_1223)); + SDFF_X1_LVT \registers_reg[3][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_3__ap[30]), .CK(n_0_33), .Q(registers_3__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[2][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_2__ap[30]), .CK(n_0_32), .Q(registers_2__ap[30]), .QN()); + AOI221_X1_LVT i_1_0_1285 (.A(n_1_0_1223), .B1(n_1_0_1257), .B2( + registers_3__ap[30]), .C1(registers_2__ap[30]), .C2(n_1_0_1268), .ZN( + n_1_0_1222)); + NAND4_X1_LVT i_1_0_1284 (.A1(n_1_0_1237), .A2(n_1_0_1232), .A3(n_1_0_1227), + .A4(n_1_0_1222), .ZN(RRs1[30])); + AND2_X1_LVT i_0_0_29 (.A1(n_0_0_16), .A2(WRd[29]), .ZN(registers[29])); + SDFF_X1_LVT \registers_reg[28][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_28__ap[29]), .CK(n_0_58), .Q(registers_28__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[8][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_8__ap[29]), .CK(n_0_38), .Q(registers_8__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1282 (.A1(registers_28__ap[29]), .A2(n_1_0_1283), .B1( + n_1_0_1282), .B2(registers_8__ap[29]), .ZN(n_1_0_1220)); + SDFF_X1_LVT \registers_reg[31][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_31__ap[29]), .CK(n_0_61), .Q(registers_31__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[7][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_7__ap[29]), .CK(n_0_37), .Q(registers_7__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1283 (.A1(registers_31__ap[29]), .A2(n_1_0_1266), .B1( + n_1_0_1263), .B2(registers_7__ap[29]), .ZN(n_1_0_1221)); + SDFF_X1_LVT \registers_reg[24][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_24__ap[29]), .CK(n_0_54), .Q(registers_24__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[20][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_20__ap[29]), .CK(n_0_50), .Q(registers_20__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1281 (.A1(registers_24__ap[29]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[29]), .ZN(n_1_0_1219)); + SDFF_X1_LVT \registers_reg[19][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_19__ap[29]), .CK(n_0_49), .Q(registers_19__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[4][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_4__ap[29]), .CK(n_0_34), .Q(registers_4__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1280 (.A1(registers_19__ap[29]), .A2(n_1_0_1295), .B1( + n_1_0_1278), .B2(registers_4__ap[29]), .ZN(n_1_0_1218)); + NAND3_X1_LVT i_1_0_1279 (.A1(n_1_0_1221), .A2(n_1_0_1219), .A3(n_1_0_1218), + .ZN(n_1_0_1217)); + SDFF_X1_LVT \registers_reg[23][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_23__ap[29]), .CK(n_0_53), .Q(registers_23__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[29][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_29__ap[29]), .CK(n_0_59), .Q(registers_29__ap[29]), .QN()); + AOI221_X1_LVT i_1_0_1278 (.A(n_1_0_1217), .B1(n_1_0_1264), .B2( + registers_23__ap[29]), .C1(registers_29__ap[29]), .C2(n_1_0_1276), + .ZN(n_1_0_1216)); + SDFF_X1_LVT \registers_reg[10][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_10__ap[29]), .CK(n_0_40), .Q(registers_10__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[26][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_26__ap[29]), .CK(n_0_56), .Q(registers_26__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[25][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_25__ap[29]), .CK(n_0_55), .Q(registers_25__ap[29]), .QN()); + AOI222_X1_LVT i_1_0_1277 (.A1(registers_10__ap[29]), .A2(n_1_0_1287), + .B1(n_1_0_1285), .B2(registers_26__ap[29]), .C1(registers_25__ap[29]), + .C2(n_1_0_1269), .ZN(n_1_0_1215)); + NAND3_X1_LVT i_1_0_1276 (.A1(n_1_0_1220), .A2(n_1_0_1216), .A3(n_1_0_1215), + .ZN(n_1_0_1214)); + SDFF_X1_LVT \registers_reg[21][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_21__ap[29]), .CK(n_0_51), .Q(registers_21__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[13][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_13__ap[29]), .CK(n_0_43), .Q(registers_13__ap[29]), .QN()); + AOI221_X1_LVT i_1_0_1275 (.A(n_1_0_1214), .B1(n_1_0_1259), .B2( + registers_21__ap[29]), .C1(registers_13__ap[29]), .C2(n_1_0_1277), + .ZN(n_1_0_1213)); + SDFF_X1_LVT \registers_reg[18][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_18__ap[29]), .CK(n_0_48), .Q(registers_18__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[30][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_30__ap[29]), .CK(n_0_60), .Q(registers_30__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1274 (.A1(registers_18__ap[29]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[29]), .ZN(n_1_0_1212)); + SDFF_X1_LVT \registers_reg[17][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_17__ap[29]), .CK(n_0_47), .Q(registers_17__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[12][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_12__ap[29]), .CK(n_0_42), .Q(registers_12__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1273 (.A1(registers_17__ap[29]), .A2(n_1_0_1271), .B1( + n_1_0_1260), .B2(registers_12__ap[29]), .ZN(n_1_0_1211)); + SDFF_X1_LVT \registers_reg[15][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_15__ap[29]), .CK(n_0_45), .Q(registers_15__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[16][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_16__ap[29]), .CK(n_0_46), .Q(registers_16__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1272 (.A1(registers_15__ap[29]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[29]), .ZN(n_1_0_1210)); + NAND3_X1_LVT i_1_0_1271 (.A1(n_1_0_1212), .A2(n_1_0_1211), .A3(n_1_0_1210), + .ZN(n_1_0_1209)); + SDFF_X1_LVT \registers_reg[22][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_22__ap[29]), .CK(n_0_52), .Q(registers_22__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[5][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_5__ap[29]), .CK(n_0_35), .Q(registers_5__ap[29]), .QN()); + AOI221_X1_LVT i_1_0_1270 (.A(n_1_0_1209), .B1(n_1_0_1294), .B2( + registers_22__ap[29]), .C1(registers_5__ap[29]), .C2(n_1_0_1273), .ZN( + n_1_0_1208)); + SDFF_X1_LVT \registers_reg[9][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_9__ap[29]), .CK(n_0_39), .Q(registers_9__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[1][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_1__ap[29]), .CK(n_0_0), .Q(registers_1__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1269 (.A1(registers_9__ap[29]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[29]), .ZN(n_1_0_1207)); + SDFF_X1_LVT \registers_reg[6][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_6__ap[29]), .CK(n_0_36), .Q(registers_6__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[14][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_14__ap[29]), .CK(n_0_44), .Q(registers_14__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1268 (.A1(registers_6__ap[29]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[29]), .ZN(n_1_0_1206)); + SDFF_X1_LVT \registers_reg[27][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_27__ap[29]), .CK(n_0_57), .Q(registers_27__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[11][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_11__ap[29]), .CK(n_0_41), .Q(registers_11__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1267 (.A1(registers_27__ap[29]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[29]), .ZN(n_1_0_1205)); + NAND3_X1_LVT i_1_0_1266 (.A1(n_1_0_1207), .A2(n_1_0_1206), .A3(n_1_0_1205), + .ZN(n_1_0_1204)); + SDFF_X1_LVT \registers_reg[3][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_3__ap[29]), .CK(n_0_33), .Q(registers_3__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[2][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_2__ap[29]), .CK(n_0_32), .Q(registers_2__ap[29]), .QN()); + AOI221_X1_LVT i_1_0_1265 (.A(n_1_0_1204), .B1(n_1_0_1257), .B2( + registers_3__ap[29]), .C1(registers_2__ap[29]), .C2(n_1_0_1268), .ZN( + n_1_0_1203)); + NAND3_X1_LVT i_1_0_1264 (.A1(n_1_0_1213), .A2(n_1_0_1208), .A3(n_1_0_1203), + .ZN(RRs1[29])); + AND2_X1_LVT i_0_0_28 (.A1(n_0_0_16), .A2(WRd[28]), .ZN(registers[28])); + SDFF_X1_LVT \registers_reg[15][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_15__ap[28]), .CK(n_0_45), .Q(registers_15__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[26][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_26__ap[28]), .CK(n_0_56), .Q(registers_26__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[22][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_22__ap[28]), .CK(n_0_52), .Q(registers_22__ap[28]), .QN()); + AOI222_X1_LVT i_1_0_1263 (.A1(registers_15__ap[28]), .A2(n_1_0_1286), + .B1(n_1_0_1285), .B2(registers_26__ap[28]), .C1(registers_22__ap[28]), + .C2(n_1_0_1294), .ZN(n_1_0_1202)); + SDFF_X1_LVT \registers_reg[5][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_5__ap[28]), .CK(n_0_35), .Q(registers_5__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[12][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_12__ap[28]), .CK(n_0_42), .Q(registers_12__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1262 (.A1(registers_5__ap[28]), .A2(n_1_0_1273), .B1( + n_1_0_1260), .B2(registers_12__ap[28]), .ZN(n_1_0_1201)); + SDFF_X1_LVT \registers_reg[28][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_28__ap[28]), .CK(n_0_58), .Q(registers_28__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[14][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_14__ap[28]), .CK(n_0_44), .Q(registers_14__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1261 (.A1(registers_28__ap[28]), .A2(n_1_0_1283), .B1( + n_1_0_1258), .B2(registers_14__ap[28]), .ZN(n_1_0_1200)); + SDFF_X1_LVT \registers_reg[17][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_17__ap[28]), .CK(n_0_47), .Q(registers_17__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[2][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_2__ap[28]), .CK(n_0_32), .Q(registers_2__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1260 (.A1(registers_17__ap[28]), .A2(n_1_0_1271), .B1( + n_1_0_1268), .B2(registers_2__ap[28]), .ZN(n_1_0_1199)); + NAND3_X1_LVT i_1_0_1259 (.A1(n_1_0_1201), .A2(n_1_0_1200), .A3(n_1_0_1199), + .ZN(n_1_0_1198)); + SDFF_X1_LVT \registers_reg[9][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_9__ap[28]), .CK(n_0_39), .Q(registers_9__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[29][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_29__ap[28]), .CK(n_0_59), .Q(registers_29__ap[28]), .QN()); + AOI221_X1_LVT i_1_0_1258 (.A(n_1_0_1198), .B1(n_1_0_1291), .B2( + registers_9__ap[28]), .C1(registers_29__ap[28]), .C2(n_1_0_1276), .ZN( + n_1_0_1197)); + SDFF_X1_LVT \registers_reg[13][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_13__ap[28]), .CK(n_0_43), .Q(registers_13__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[25][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_25__ap[28]), .CK(n_0_55), .Q(registers_25__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1257 (.A1(registers_13__ap[28]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[28]), .ZN(n_1_0_1196)); + NAND3_X1_LVT i_1_0_1256 (.A1(n_1_0_1202), .A2(n_1_0_1197), .A3(n_1_0_1196), + .ZN(n_1_0_1195)); + SDFF_X1_LVT \registers_reg[4][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_4__ap[28]), .CK(n_0_34), .Q(registers_4__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[20][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_20__ap[28]), .CK(n_0_50), .Q(registers_20__ap[28]), .QN()); + AOI221_X1_LVT i_1_0_1255 (.A(n_1_0_1195), .B1(n_1_0_1278), .B2( + registers_4__ap[28]), .C1(registers_20__ap[28]), .C2(n_1_0_1281), .ZN( + n_1_0_1194)); + SDFF_X1_LVT \registers_reg[1][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_1__ap[28]), .CK(n_0_0), .Q(registers_1__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[23][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_23__ap[28]), .CK(n_0_53), .Q(registers_23__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1254 (.A1(registers_1__ap[28]), .A2(n_1_0_1274), .B1( + n_1_0_1264), .B2(registers_23__ap[28]), .ZN(n_1_0_1193)); + SDFF_X1_LVT \registers_reg[10][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_10__ap[28]), .CK(n_0_40), .Q(registers_10__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[21][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_21__ap[28]), .CK(n_0_51), .Q(registers_21__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1253 (.A1(registers_10__ap[28]), .A2(n_1_0_1287), .B1( + n_1_0_1259), .B2(registers_21__ap[28]), .ZN(n_1_0_1192)); + SDFF_X1_LVT \registers_reg[6][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_6__ap[28]), .CK(n_0_36), .Q(registers_6__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[30][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_30__ap[28]), .CK(n_0_60), .Q(registers_30__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1252 (.A1(registers_6__ap[28]), .A2(n_1_0_1300), .B1( + n_1_0_1272), .B2(registers_30__ap[28]), .ZN(n_1_0_1191)); + NAND3_X1_LVT i_1_0_1251 (.A1(n_1_0_1193), .A2(n_1_0_1192), .A3(n_1_0_1191), + .ZN(n_1_0_1190)); + SDFF_X1_LVT \registers_reg[8][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_8__ap[28]), .CK(n_0_38), .Q(registers_8__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[24][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_24__ap[28]), .CK(n_0_54), .Q(registers_24__ap[28]), .QN()); + AOI221_X1_LVT i_1_0_1250 (.A(n_1_0_1190), .B1(n_1_0_1282), .B2( + registers_8__ap[28]), .C1(registers_24__ap[28]), .C2(n_1_0_1289), .ZN( + n_1_0_1189)); + SDFF_X1_LVT \registers_reg[16][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_16__ap[28]), .CK(n_0_46), .Q(registers_16__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[3][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_3__ap[28]), .CK(n_0_33), .Q(registers_3__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1249 (.A1(registers_16__ap[28]), .A2(n_1_0_1267), .B1( + n_1_0_1257), .B2(registers_3__ap[28]), .ZN(n_1_0_1188)); + SDFF_X1_LVT \registers_reg[11][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_11__ap[28]), .CK(n_0_41), .Q(registers_11__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[31][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_31__ap[28]), .CK(n_0_61), .Q(registers_31__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1248 (.A1(registers_11__ap[28]), .A2(n_1_0_1270), .B1( + n_1_0_1266), .B2(registers_31__ap[28]), .ZN(n_1_0_1187)); + SDFF_X1_LVT \registers_reg[27][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_27__ap[28]), .CK(n_0_57), .Q(registers_27__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[7][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_7__ap[28]), .CK(n_0_37), .Q(registers_7__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1247 (.A1(registers_27__ap[28]), .A2(n_1_0_1279), .B1( + n_1_0_1263), .B2(registers_7__ap[28]), .ZN(n_1_0_1186)); + NAND3_X1_LVT i_1_0_1246 (.A1(n_1_0_1188), .A2(n_1_0_1187), .A3(n_1_0_1186), + .ZN(n_1_0_1185)); + SDFF_X1_LVT \registers_reg[19][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_19__ap[28]), .CK(n_0_49), .Q(registers_19__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[18][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_18__ap[28]), .CK(n_0_48), .Q(registers_18__ap[28]), .QN()); + AOI221_X1_LVT i_1_0_1245 (.A(n_1_0_1185), .B1(n_1_0_1295), .B2( + registers_19__ap[28]), .C1(registers_18__ap[28]), .C2(n_1_0_1297), + .ZN(n_1_0_1184)); + NAND3_X1_LVT i_1_0_1244 (.A1(n_1_0_1194), .A2(n_1_0_1189), .A3(n_1_0_1184), + .ZN(RRs1[28])); + AND2_X1_LVT i_0_0_27 (.A1(n_0_0_16), .A2(WRd[27]), .ZN(registers[27])); + SDFF_X1_LVT \registers_reg[29][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_29__ap[27]), .CK(n_0_59), .Q(registers_29__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[2][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_2__ap[27]), .CK(n_0_32), .Q(registers_2__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1242 (.A1(registers_29__ap[27]), .A2(n_1_0_1276), .B1( + n_1_0_1268), .B2(registers_2__ap[27]), .ZN(n_1_0_1182)); + SDFF_X1_LVT \registers_reg[8][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_8__ap[27]), .CK(n_0_38), .Q(registers_8__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[25][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_25__ap[27]), .CK(n_0_55), .Q(registers_25__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1243 (.A1(registers_8__ap[27]), .A2(n_1_0_1282), .B1( + n_1_0_1269), .B2(registers_25__ap[27]), .ZN(n_1_0_1183)); + SDFF_X1_LVT \registers_reg[9][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_9__ap[27]), .CK(n_0_39), .Q(registers_9__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[7][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_7__ap[27]), .CK(n_0_37), .Q(registers_7__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1241 (.A1(registers_9__ap[27]), .A2(n_1_0_1291), .B1( + n_1_0_1263), .B2(registers_7__ap[27]), .ZN(n_1_0_1181)); + SDFF_X1_LVT \registers_reg[11][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_11__ap[27]), .CK(n_0_41), .Q(registers_11__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[16][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_16__ap[27]), .CK(n_0_46), .Q(registers_16__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1240 (.A1(registers_11__ap[27]), .A2(n_1_0_1270), .B1( + n_1_0_1267), .B2(registers_16__ap[27]), .ZN(n_1_0_1180)); + NAND3_X1_LVT i_1_0_1239 (.A1(n_1_0_1183), .A2(n_1_0_1181), .A3(n_1_0_1180), + .ZN(n_1_0_1179)); + SDFF_X1_LVT \registers_reg[10][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_10__ap[27]), .CK(n_0_40), .Q(registers_10__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[6][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_6__ap[27]), .CK(n_0_36), .Q(registers_6__ap[27]), .QN()); + AOI221_X1_LVT i_1_0_1238 (.A(n_1_0_1179), .B1(n_1_0_1287), .B2( + registers_10__ap[27]), .C1(registers_6__ap[27]), .C2(n_1_0_1300), .ZN( + n_1_0_1178)); + SDFF_X1_LVT \registers_reg[1][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_1__ap[27]), .CK(n_0_0), .Q(registers_1__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[30][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_30__ap[27]), .CK(n_0_60), .Q(registers_30__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[22][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_22__ap[27]), .CK(n_0_52), .Q(registers_22__ap[27]), .QN()); + AOI222_X1_LVT i_1_0_1237 (.A1(registers_1__ap[27]), .A2(n_1_0_1274), .B1( + n_1_0_1272), .B2(registers_30__ap[27]), .C1(registers_22__ap[27]), + .C2(n_1_0_1294), .ZN(n_1_0_1177)); + NAND3_X1_LVT i_1_0_1236 (.A1(n_1_0_1182), .A2(n_1_0_1178), .A3(n_1_0_1177), + .ZN(n_1_0_1176)); + SDFF_X1_LVT \registers_reg[5][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_5__ap[27]), .CK(n_0_35), .Q(registers_5__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[28][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_28__ap[27]), .CK(n_0_58), .Q(registers_28__ap[27]), .QN()); + AOI221_X1_LVT i_1_0_1235 (.A(n_1_0_1176), .B1(n_1_0_1273), .B2( + registers_5__ap[27]), .C1(registers_28__ap[27]), .C2(n_1_0_1283), .ZN( + n_1_0_1175)); + SDFF_X1_LVT \registers_reg[4][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_4__ap[27]), .CK(n_0_34), .Q(registers_4__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[12][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_12__ap[27]), .CK(n_0_42), .Q(registers_12__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1234 (.A1(registers_4__ap[27]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[27]), .ZN(n_1_0_1174)); + SDFF_X1_LVT \registers_reg[19][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_19__ap[27]), .CK(n_0_49), .Q(registers_19__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[21][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_21__ap[27]), .CK(n_0_51), .Q(registers_21__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1233 (.A1(registers_19__ap[27]), .A2(n_1_0_1295), .B1( + n_1_0_1259), .B2(registers_21__ap[27]), .ZN(n_1_0_1173)); + SDFF_X1_LVT \registers_reg[24][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_24__ap[27]), .CK(n_0_54), .Q(registers_24__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[20][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_20__ap[27]), .CK(n_0_50), .Q(registers_20__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1232 (.A1(registers_24__ap[27]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[27]), .ZN(n_1_0_1172)); + NAND3_X1_LVT i_1_0_1231 (.A1(n_1_0_1174), .A2(n_1_0_1173), .A3(n_1_0_1172), + .ZN(n_1_0_1171)); + SDFF_X1_LVT \registers_reg[18][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_18__ap[27]), .CK(n_0_48), .Q(registers_18__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[26][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_26__ap[27]), .CK(n_0_56), .Q(registers_26__ap[27]), .QN()); + AOI221_X1_LVT i_1_0_1230 (.A(n_1_0_1171), .B1(n_1_0_1297), .B2( + registers_18__ap[27]), .C1(registers_26__ap[27]), .C2(n_1_0_1285), + .ZN(n_1_0_1170)); + SDFF_X1_LVT \registers_reg[23][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_23__ap[27]), .CK(n_0_53), .Q(registers_23__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[3][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_3__ap[27]), .CK(n_0_33), .Q(registers_3__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1229 (.A1(registers_23__ap[27]), .A2(n_1_0_1264), .B1( + n_1_0_1257), .B2(registers_3__ap[27]), .ZN(n_1_0_1169)); + SDFF_X1_LVT \registers_reg[13][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_13__ap[27]), .CK(n_0_43), .Q(registers_13__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[17][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_17__ap[27]), .CK(n_0_47), .Q(registers_17__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1228 (.A1(registers_13__ap[27]), .A2(n_1_0_1277), .B1( + n_1_0_1271), .B2(registers_17__ap[27]), .ZN(n_1_0_1168)); + SDFF_X1_LVT \registers_reg[15][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_15__ap[27]), .CK(n_0_45), .Q(registers_15__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[14][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_14__ap[27]), .CK(n_0_44), .Q(registers_14__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1227 (.A1(registers_15__ap[27]), .A2(n_1_0_1286), .B1( + n_1_0_1258), .B2(registers_14__ap[27]), .ZN(n_1_0_1167)); + NAND3_X1_LVT i_1_0_1226 (.A1(n_1_0_1169), .A2(n_1_0_1168), .A3(n_1_0_1167), + .ZN(n_1_0_1166)); + SDFF_X1_LVT \registers_reg[27][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_27__ap[27]), .CK(n_0_57), .Q(registers_27__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[31][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_31__ap[27]), .CK(n_0_61), .Q(registers_31__ap[27]), .QN()); + AOI221_X1_LVT i_1_0_1225 (.A(n_1_0_1166), .B1(n_1_0_1279), .B2( + registers_27__ap[27]), .C1(registers_31__ap[27]), .C2(n_1_0_1266), + .ZN(n_1_0_1165)); + NAND3_X1_LVT i_1_0_1224 (.A1(n_1_0_1175), .A2(n_1_0_1170), .A3(n_1_0_1165), + .ZN(RRs1[27])); + AND2_X1_LVT i_0_0_26 (.A1(n_0_0_16), .A2(WRd[26]), .ZN(registers[26])); + SDFF_X1_LVT \registers_reg[18][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_18__ap[26]), .CK(n_0_48), .Q(registers_18__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[22][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_22__ap[26]), .CK(n_0_52), .Q(registers_22__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[1][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_1__ap[26]), .CK(n_0_0), .Q(registers_1__ap[26]), .QN()); + AOI222_X1_LVT i_1_0_1223 (.A1(registers_18__ap[26]), .A2(n_1_0_1297), + .B1(n_1_0_1294), .B2(registers_22__ap[26]), .C1(registers_1__ap[26]), + .C2(n_1_0_1274), .ZN(n_1_0_1164)); + SDFF_X1_LVT \registers_reg[29][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_29__ap[26]), .CK(n_0_59), .Q(registers_29__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[2][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_2__ap[26]), .CK(n_0_32), .Q(registers_2__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1222 (.A1(registers_29__ap[26]), .A2(n_1_0_1276), .B1( + n_1_0_1268), .B2(registers_2__ap[26]), .ZN(n_1_0_1163)); + SDFF_X1_LVT \registers_reg[9][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_9__ap[26]), .CK(n_0_39), .Q(registers_9__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[7][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_7__ap[26]), .CK(n_0_37), .Q(registers_7__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1221 (.A1(registers_9__ap[26]), .A2(n_1_0_1291), .B1( + n_1_0_1263), .B2(registers_7__ap[26]), .ZN(n_1_0_1162)); + SDFF_X1_LVT \registers_reg[11][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_11__ap[26]), .CK(n_0_41), .Q(registers_11__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[25][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_25__ap[26]), .CK(n_0_55), .Q(registers_25__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1220 (.A1(registers_11__ap[26]), .A2(n_1_0_1270), .B1( + n_1_0_1269), .B2(registers_25__ap[26]), .ZN(n_1_0_1161)); + SDFF_X1_LVT \registers_reg[27][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_27__ap[26]), .CK(n_0_57), .Q(registers_27__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[16][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_16__ap[26]), .CK(n_0_46), .Q(registers_16__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1219 (.A1(registers_27__ap[26]), .A2(n_1_0_1279), .B1( + n_1_0_1267), .B2(registers_16__ap[26]), .ZN(n_1_0_1160)); + NAND3_X1_LVT i_1_0_1218 (.A1(n_1_0_1162), .A2(n_1_0_1161), .A3(n_1_0_1160), + .ZN(n_1_0_1159)); + SDFF_X1_LVT \registers_reg[31][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_31__ap[26]), .CK(n_0_61), .Q(registers_31__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[6][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_6__ap[26]), .CK(n_0_36), .Q(registers_6__ap[26]), .QN()); + AOI221_X1_LVT i_1_0_1217 (.A(n_1_0_1159), .B1(n_1_0_1266), .B2( + registers_31__ap[26]), .C1(registers_6__ap[26]), .C2(n_1_0_1300), .ZN( + n_1_0_1158)); + NAND3_X1_LVT i_1_0_1216 (.A1(n_1_0_1164), .A2(n_1_0_1163), .A3(n_1_0_1158), + .ZN(n_1_0_1157)); + SDFF_X1_LVT \registers_reg[5][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_5__ap[26]), .CK(n_0_35), .Q(registers_5__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[28][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_28__ap[26]), .CK(n_0_58), .Q(registers_28__ap[26]), .QN()); + AOI221_X1_LVT i_1_0_1215 (.A(n_1_0_1157), .B1(n_1_0_1273), .B2( + registers_5__ap[26]), .C1(registers_28__ap[26]), .C2(n_1_0_1283), .ZN( + n_1_0_1156)); + SDFF_X1_LVT \registers_reg[4][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_4__ap[26]), .CK(n_0_34), .Q(registers_4__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[12][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_12__ap[26]), .CK(n_0_42), .Q(registers_12__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1214 (.A1(registers_4__ap[26]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[26]), .ZN(n_1_0_1155)); + SDFF_X1_LVT \registers_reg[19][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_19__ap[26]), .CK(n_0_49), .Q(registers_19__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[21][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_21__ap[26]), .CK(n_0_51), .Q(registers_21__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1213 (.A1(registers_19__ap[26]), .A2(n_1_0_1295), .B1( + n_1_0_1259), .B2(registers_21__ap[26]), .ZN(n_1_0_1154)); + SDFF_X1_LVT \registers_reg[24][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_24__ap[26]), .CK(n_0_54), .Q(registers_24__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[20][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_20__ap[26]), .CK(n_0_50), .Q(registers_20__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1212 (.A1(registers_24__ap[26]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[26]), .ZN(n_1_0_1153)); + NAND3_X1_LVT i_1_0_1211 (.A1(n_1_0_1155), .A2(n_1_0_1154), .A3(n_1_0_1153), + .ZN(n_1_0_1152)); + SDFF_X1_LVT \registers_reg[26][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_26__ap[26]), .CK(n_0_56), .Q(registers_26__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[30][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_30__ap[26]), .CK(n_0_60), .Q(registers_30__ap[26]), .QN()); + AOI221_X1_LVT i_1_0_1210 (.A(n_1_0_1152), .B1(n_1_0_1285), .B2( + registers_26__ap[26]), .C1(registers_30__ap[26]), .C2(n_1_0_1272), + .ZN(n_1_0_1151)); + SDFF_X1_LVT \registers_reg[8][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_8__ap[26]), .CK(n_0_38), .Q(registers_8__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[23][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_23__ap[26]), .CK(n_0_53), .Q(registers_23__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1209 (.A1(registers_8__ap[26]), .A2(n_1_0_1282), .B1( + n_1_0_1264), .B2(registers_23__ap[26]), .ZN(n_1_0_1150)); + SDFF_X1_LVT \registers_reg[13][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_13__ap[26]), .CK(n_0_43), .Q(registers_13__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[17][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_17__ap[26]), .CK(n_0_47), .Q(registers_17__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1208 (.A1(registers_13__ap[26]), .A2(n_1_0_1277), .B1( + n_1_0_1271), .B2(registers_17__ap[26]), .ZN(n_1_0_1149)); + SDFF_X1_LVT \registers_reg[15][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_15__ap[26]), .CK(n_0_45), .Q(registers_15__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[14][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_14__ap[26]), .CK(n_0_44), .Q(registers_14__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1207 (.A1(registers_15__ap[26]), .A2(n_1_0_1286), .B1( + n_1_0_1258), .B2(registers_14__ap[26]), .ZN(n_1_0_1148)); + NAND3_X1_LVT i_1_0_1206 (.A1(n_1_0_1150), .A2(n_1_0_1149), .A3(n_1_0_1148), + .ZN(n_1_0_1147)); + SDFF_X1_LVT \registers_reg[10][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_10__ap[26]), .CK(n_0_40), .Q(registers_10__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[3][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_3__ap[26]), .CK(n_0_33), .Q(registers_3__ap[26]), .QN()); + AOI221_X1_LVT i_1_0_1205 (.A(n_1_0_1147), .B1(n_1_0_1287), .B2( + registers_10__ap[26]), .C1(registers_3__ap[26]), .C2(n_1_0_1257), .ZN( + n_1_0_1146)); + NAND3_X1_LVT i_1_0_1204 (.A1(n_1_0_1156), .A2(n_1_0_1151), .A3(n_1_0_1146), + .ZN(RRs1[26])); + AND2_X1_LVT i_0_0_25 (.A1(n_0_0_16), .A2(WRd[25]), .ZN(registers[25])); + SDFF_X1_LVT \registers_reg[17][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_17__ap[25]), .CK(n_0_47), .Q(registers_17__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[21][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_21__ap[25]), .CK(n_0_51), .Q(registers_21__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1202 (.A1(registers_17__ap[25]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[25]), .ZN(n_1_0_1144)); + SDFF_X1_LVT \registers_reg[6][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_6__ap[25]), .CK(n_0_36), .Q(registers_6__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[8][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_8__ap[25]), .CK(n_0_38), .Q(registers_8__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1203 (.A1(registers_6__ap[25]), .A2(n_1_0_1300), .B1( + n_1_0_1282), .B2(registers_8__ap[25]), .ZN(n_1_0_1145)); + SDFF_X1_LVT \registers_reg[20][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_20__ap[25]), .CK(n_0_50), .Q(registers_20__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[12][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_12__ap[25]), .CK(n_0_42), .Q(registers_12__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1201 (.A1(registers_20__ap[25]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[25]), .ZN(n_1_0_1143)); + SDFF_X1_LVT \registers_reg[5][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_5__ap[25]), .CK(n_0_35), .Q(registers_5__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[11][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_11__ap[25]), .CK(n_0_41), .Q(registers_11__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1200 (.A1(registers_5__ap[25]), .A2(n_1_0_1273), .B1( + n_1_0_1270), .B2(registers_11__ap[25]), .ZN(n_1_0_1142)); + NAND3_X1_LVT i_1_0_1199 (.A1(n_1_0_1145), .A2(n_1_0_1143), .A3(n_1_0_1142), + .ZN(n_1_0_1141)); + SDFF_X1_LVT \registers_reg[10][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_10__ap[25]), .CK(n_0_40), .Q(registers_10__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[2][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_2__ap[25]), .CK(n_0_32), .Q(registers_2__ap[25]), .QN()); + AOI221_X1_LVT i_1_0_1198 (.A(n_1_0_1141), .B1(n_1_0_1287), .B2( + registers_10__ap[25]), .C1(registers_2__ap[25]), .C2(n_1_0_1268), .ZN( + n_1_0_1140)); + SDFF_X1_LVT \registers_reg[13][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_13__ap[25]), .CK(n_0_43), .Q(registers_13__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[30][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_30__ap[25]), .CK(n_0_60), .Q(registers_30__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[22][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_22__ap[25]), .CK(n_0_52), .Q(registers_22__ap[25]), .QN()); + AOI222_X1_LVT i_1_0_1197 (.A1(registers_13__ap[25]), .A2(n_1_0_1277), + .B1(n_1_0_1272), .B2(registers_30__ap[25]), .C1(registers_22__ap[25]), + .C2(n_1_0_1294), .ZN(n_1_0_1139)); + NAND2_X1_LVT i_1_0_1196 (.A1(n_1_0_1140), .A2(n_1_0_1139), .ZN(n_1_0_1138)); + SDFF_X1_LVT \registers_reg[1][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_1__ap[25]), .CK(n_0_0), .Q(registers_1__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[28][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_28__ap[25]), .CK(n_0_58), .Q(registers_28__ap[25]), .QN()); + AOI221_X1_LVT i_1_0_1195 (.A(n_1_0_1138), .B1(n_1_0_1274), .B2( + registers_1__ap[25]), .C1(registers_28__ap[25]), .C2(n_1_0_1283), .ZN( + n_1_0_1137)); + SDFF_X1_LVT \registers_reg[18][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_18__ap[25]), .CK(n_0_48), .Q(registers_18__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[26][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_26__ap[25]), .CK(n_0_56), .Q(registers_26__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1194 (.A1(registers_18__ap[25]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[25]), .ZN(n_1_0_1136)); + SDFF_X1_LVT \registers_reg[24][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_24__ap[25]), .CK(n_0_54), .Q(registers_24__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[4][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_4__ap[25]), .CK(n_0_34), .Q(registers_4__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1193 (.A1(registers_24__ap[25]), .A2(n_1_0_1289), .B1( + n_1_0_1278), .B2(registers_4__ap[25]), .ZN(n_1_0_1135)); + SDFF_X1_LVT \registers_reg[15][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_15__ap[25]), .CK(n_0_45), .Q(registers_15__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[16][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_16__ap[25]), .CK(n_0_46), .Q(registers_16__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1192 (.A1(registers_15__ap[25]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[25]), .ZN(n_1_0_1134)); + NAND3_X1_LVT i_1_0_1191 (.A1(n_1_0_1136), .A2(n_1_0_1135), .A3(n_1_0_1134), + .ZN(n_1_0_1133)); + SDFF_X1_LVT \registers_reg[19][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_19__ap[25]), .CK(n_0_49), .Q(registers_19__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[25][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_25__ap[25]), .CK(n_0_55), .Q(registers_25__ap[25]), .QN()); + AOI221_X1_LVT i_1_0_1190 (.A(n_1_0_1133), .B1(n_1_0_1295), .B2( + registers_19__ap[25]), .C1(registers_25__ap[25]), .C2(n_1_0_1269), + .ZN(n_1_0_1132)); + SDFF_X1_LVT \registers_reg[7][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_7__ap[25]), .CK(n_0_37), .Q(registers_7__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[14][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_14__ap[25]), .CK(n_0_44), .Q(registers_14__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1189 (.A1(registers_7__ap[25]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[25]), .ZN(n_1_0_1131)); + SDFF_X1_LVT \registers_reg[9][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_9__ap[25]), .CK(n_0_39), .Q(registers_9__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[29][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_29__ap[25]), .CK(n_0_59), .Q(registers_29__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1188 (.A1(registers_9__ap[25]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[25]), .ZN(n_1_0_1130)); + SDFF_X1_LVT \registers_reg[23][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_23__ap[25]), .CK(n_0_53), .Q(registers_23__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[3][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_3__ap[25]), .CK(n_0_33), .Q(registers_3__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1187 (.A1(registers_23__ap[25]), .A2(n_1_0_1264), .B1( + n_1_0_1257), .B2(registers_3__ap[25]), .ZN(n_1_0_1129)); + NAND3_X1_LVT i_1_0_1186 (.A1(n_1_0_1131), .A2(n_1_0_1130), .A3(n_1_0_1129), + .ZN(n_1_0_1128)); + SDFF_X1_LVT \registers_reg[27][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_27__ap[25]), .CK(n_0_57), .Q(registers_27__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[31][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_31__ap[25]), .CK(n_0_61), .Q(registers_31__ap[25]), .QN()); + AOI221_X1_LVT i_1_0_1185 (.A(n_1_0_1128), .B1(n_1_0_1279), .B2( + registers_27__ap[25]), .C1(registers_31__ap[25]), .C2(n_1_0_1266), + .ZN(n_1_0_1127)); + NAND4_X1_LVT i_1_0_1184 (.A1(n_1_0_1144), .A2(n_1_0_1137), .A3(n_1_0_1132), + .A4(n_1_0_1127), .ZN(RRs1[25])); + AND2_X1_LVT i_0_0_24 (.A1(n_0_0_16), .A2(WRd[24]), .ZN(registers[24])); + SDFF_X1_LVT \registers_reg[17][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_17__ap[24]), .CK(n_0_47), .Q(registers_17__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[21][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_21__ap[24]), .CK(n_0_51), .Q(registers_21__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1182 (.A1(registers_17__ap[24]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[24]), .ZN(n_1_0_1125)); + SDFF_X1_LVT \registers_reg[6][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_6__ap[24]), .CK(n_0_36), .Q(registers_6__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[8][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_8__ap[24]), .CK(n_0_38), .Q(registers_8__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1183 (.A1(registers_6__ap[24]), .A2(n_1_0_1300), .B1( + n_1_0_1282), .B2(registers_8__ap[24]), .ZN(n_1_0_1126)); + SDFF_X1_LVT \registers_reg[20][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_20__ap[24]), .CK(n_0_50), .Q(registers_20__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[12][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_12__ap[24]), .CK(n_0_42), .Q(registers_12__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1181 (.A1(registers_20__ap[24]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[24]), .ZN(n_1_0_1124)); + SDFF_X1_LVT \registers_reg[5][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_5__ap[24]), .CK(n_0_35), .Q(registers_5__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[11][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_11__ap[24]), .CK(n_0_41), .Q(registers_11__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1180 (.A1(registers_5__ap[24]), .A2(n_1_0_1273), .B1( + n_1_0_1270), .B2(registers_11__ap[24]), .ZN(n_1_0_1123)); + NAND3_X1_LVT i_1_0_1179 (.A1(n_1_0_1126), .A2(n_1_0_1124), .A3(n_1_0_1123), + .ZN(n_1_0_1122)); + SDFF_X1_LVT \registers_reg[10][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_10__ap[24]), .CK(n_0_40), .Q(registers_10__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[2][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_2__ap[24]), .CK(n_0_32), .Q(registers_2__ap[24]), .QN()); + AOI221_X1_LVT i_1_0_1178 (.A(n_1_0_1122), .B1(n_1_0_1287), .B2( + registers_10__ap[24]), .C1(registers_2__ap[24]), .C2(n_1_0_1268), .ZN( + n_1_0_1121)); + SDFF_X1_LVT \registers_reg[13][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_13__ap[24]), .CK(n_0_43), .Q(registers_13__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[30][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_30__ap[24]), .CK(n_0_60), .Q(registers_30__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[22][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_22__ap[24]), .CK(n_0_52), .Q(registers_22__ap[24]), .QN()); + AOI222_X1_LVT i_1_0_1177 (.A1(registers_13__ap[24]), .A2(n_1_0_1277), + .B1(n_1_0_1272), .B2(registers_30__ap[24]), .C1(registers_22__ap[24]), + .C2(n_1_0_1294), .ZN(n_1_0_1120)); + NAND2_X1_LVT i_1_0_1176 (.A1(n_1_0_1121), .A2(n_1_0_1120), .ZN(n_1_0_1119)); + SDFF_X1_LVT \registers_reg[1][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_1__ap[24]), .CK(n_0_0), .Q(registers_1__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[28][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_28__ap[24]), .CK(n_0_58), .Q(registers_28__ap[24]), .QN()); + AOI221_X1_LVT i_1_0_1175 (.A(n_1_0_1119), .B1(n_1_0_1274), .B2( + registers_1__ap[24]), .C1(registers_28__ap[24]), .C2(n_1_0_1283), .ZN( + n_1_0_1118)); + SDFF_X1_LVT \registers_reg[18][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_18__ap[24]), .CK(n_0_48), .Q(registers_18__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[26][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_26__ap[24]), .CK(n_0_56), .Q(registers_26__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1174 (.A1(registers_18__ap[24]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[24]), .ZN(n_1_0_1117)); + SDFF_X1_LVT \registers_reg[24][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_24__ap[24]), .CK(n_0_54), .Q(registers_24__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[4][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_4__ap[24]), .CK(n_0_34), .Q(registers_4__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1173 (.A1(registers_24__ap[24]), .A2(n_1_0_1289), .B1( + n_1_0_1278), .B2(registers_4__ap[24]), .ZN(n_1_0_1116)); + SDFF_X1_LVT \registers_reg[15][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_15__ap[24]), .CK(n_0_45), .Q(registers_15__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[25][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_25__ap[24]), .CK(n_0_55), .Q(registers_25__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1172 (.A1(registers_15__ap[24]), .A2(n_1_0_1286), .B1( + n_1_0_1269), .B2(registers_25__ap[24]), .ZN(n_1_0_1115)); + NAND3_X1_LVT i_1_0_1171 (.A1(n_1_0_1117), .A2(n_1_0_1116), .A3(n_1_0_1115), + .ZN(n_1_0_1114)); + SDFF_X1_LVT \registers_reg[19][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_19__ap[24]), .CK(n_0_49), .Q(registers_19__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[16][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_16__ap[24]), .CK(n_0_46), .Q(registers_16__ap[24]), .QN()); + AOI221_X1_LVT i_1_0_1170 (.A(n_1_0_1114), .B1(n_1_0_1295), .B2( + registers_19__ap[24]), .C1(registers_16__ap[24]), .C2(n_1_0_1267), + .ZN(n_1_0_1113)); + SDFF_X1_LVT \registers_reg[7][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_7__ap[24]), .CK(n_0_37), .Q(registers_7__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[14][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_14__ap[24]), .CK(n_0_44), .Q(registers_14__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1169 (.A1(registers_7__ap[24]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[24]), .ZN(n_1_0_1112)); + SDFF_X1_LVT \registers_reg[9][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_9__ap[24]), .CK(n_0_39), .Q(registers_9__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[29][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_29__ap[24]), .CK(n_0_59), .Q(registers_29__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1168 (.A1(registers_9__ap[24]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[24]), .ZN(n_1_0_1111)); + SDFF_X1_LVT \registers_reg[23][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_23__ap[24]), .CK(n_0_53), .Q(registers_23__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[3][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_3__ap[24]), .CK(n_0_33), .Q(registers_3__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1167 (.A1(registers_23__ap[24]), .A2(n_1_0_1264), .B1( + n_1_0_1257), .B2(registers_3__ap[24]), .ZN(n_1_0_1110)); + NAND3_X1_LVT i_1_0_1166 (.A1(n_1_0_1112), .A2(n_1_0_1111), .A3(n_1_0_1110), + .ZN(n_1_0_1109)); + SDFF_X1_LVT \registers_reg[27][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_27__ap[24]), .CK(n_0_57), .Q(registers_27__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[31][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_31__ap[24]), .CK(n_0_61), .Q(registers_31__ap[24]), .QN()); + AOI221_X1_LVT i_1_0_1165 (.A(n_1_0_1109), .B1(n_1_0_1279), .B2( + registers_27__ap[24]), .C1(registers_31__ap[24]), .C2(n_1_0_1266), + .ZN(n_1_0_1108)); + NAND4_X1_LVT i_1_0_1164 (.A1(n_1_0_1125), .A2(n_1_0_1118), .A3(n_1_0_1113), + .A4(n_1_0_1108), .ZN(RRs1[24])); + AND2_X1_LVT i_0_0_23 (.A1(n_0_0_16), .A2(WRd[23]), .ZN(registers[23])); + SDFF_X1_LVT \registers_reg[9][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_9__ap[23]), .CK(n_0_39), .Q(registers_9__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[28][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_28__ap[23]), .CK(n_0_58), .Q(registers_28__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1163 (.A1(registers_9__ap[23]), .A2(n_1_0_1291), .B1( + n_1_0_1283), .B2(registers_28__ap[23]), .ZN(n_1_0_1107)); + SDFF_X1_LVT \registers_reg[18][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_18__ap[23]), .CK(n_0_48), .Q(registers_18__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[22][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_22__ap[23]), .CK(n_0_52), .Q(registers_22__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1160 (.A1(registers_18__ap[23]), .A2(n_1_0_1297), .B1( + n_1_0_1294), .B2(registers_22__ap[23]), .ZN(n_1_0_1104)); + SDFF_X1_LVT \registers_reg[1][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_1__ap[23]), .CK(n_0_0), .Q(registers_1__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[21][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_21__ap[23]), .CK(n_0_51), .Q(registers_21__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1159 (.A1(registers_1__ap[23]), .A2(n_1_0_1274), .B1( + n_1_0_1259), .B2(registers_21__ap[23]), .ZN(n_1_0_1103)); + NAND3_X1_LVT i_1_0_1157 (.A1(n_1_0_1107), .A2(n_1_0_1104), .A3(n_1_0_1103), + .ZN(n_1_0_1101)); + SDFF_X1_LVT \registers_reg[20][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_20__ap[23]), .CK(n_0_50), .Q(registers_20__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[19][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_19__ap[23]), .CK(n_0_49), .Q(registers_19__ap[23]), .QN()); + AOI221_X1_LVT i_1_0_1156 (.A(n_1_0_1101), .B1(n_1_0_1281), .B2( + registers_20__ap[23]), .C1(registers_19__ap[23]), .C2(n_1_0_1295), + .ZN(n_1_0_1100)); + SDFF_X1_LVT \registers_reg[26][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_26__ap[23]), .CK(n_0_56), .Q(registers_26__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[23][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_23__ap[23]), .CK(n_0_53), .Q(registers_23__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1162 (.A1(registers_26__ap[23]), .A2(n_1_0_1285), .B1( + n_1_0_1264), .B2(registers_23__ap[23]), .ZN(n_1_0_1106)); + SDFF_X1_LVT \registers_reg[29][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_29__ap[23]), .CK(n_0_59), .Q(registers_29__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[3][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_3__ap[23]), .CK(n_0_33), .Q(registers_3__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1161 (.A1(registers_29__ap[23]), .A2(n_1_0_1276), .B1( + n_1_0_1257), .B2(registers_3__ap[23]), .ZN(n_1_0_1105)); + SDFF_X1_LVT \registers_reg[30][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_30__ap[23]), .CK(n_0_60), .Q(registers_30__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[31][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_31__ap[23]), .CK(n_0_61), .Q(registers_31__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1158 (.A1(registers_30__ap[23]), .A2(n_1_0_1272), .B1( + n_1_0_1266), .B2(registers_31__ap[23]), .ZN(n_1_0_1102)); + NAND3_X1_LVT i_1_0_1155 (.A1(n_1_0_1106), .A2(n_1_0_1105), .A3(n_1_0_1102), + .ZN(n_1_0_1099)); + SDFF_X1_LVT \registers_reg[8][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_8__ap[23]), .CK(n_0_38), .Q(registers_8__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[17][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_17__ap[23]), .CK(n_0_47), .Q(registers_17__ap[23]), .QN()); + AOI221_X1_LVT i_1_0_1154 (.A(n_1_0_1099), .B1(n_1_0_1282), .B2( + registers_8__ap[23]), .C1(registers_17__ap[23]), .C2(n_1_0_1271), .ZN( + n_1_0_1098)); + SDFF_X1_LVT \registers_reg[24][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_24__ap[23]), .CK(n_0_54), .Q(registers_24__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[15][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_15__ap[23]), .CK(n_0_45), .Q(registers_15__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[14][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_14__ap[23]), .CK(n_0_44), .Q(registers_14__ap[23]), .QN()); + AOI222_X1_LVT i_1_0_1153 (.A1(registers_24__ap[23]), .A2(n_1_0_1289), + .B1(n_1_0_1286), .B2(registers_15__ap[23]), .C1(n_1_0_1258), .C2( + registers_14__ap[23]), .ZN(n_1_0_1097)); + SDFF_X1_LVT \registers_reg[16][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_16__ap[23]), .CK(n_0_46), .Q(registers_16__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[7][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_7__ap[23]), .CK(n_0_37), .Q(registers_7__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1152 (.A1(registers_16__ap[23]), .A2(n_1_0_1267), .B1( + n_1_0_1263), .B2(registers_7__ap[23]), .ZN(n_1_0_1096)); + SDFF_X1_LVT \registers_reg[6][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_6__ap[23]), .CK(n_0_36), .Q(registers_6__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[25][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_25__ap[23]), .CK(n_0_55), .Q(registers_25__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1151 (.A1(registers_6__ap[23]), .A2(n_1_0_1300), .B1( + n_1_0_1269), .B2(registers_25__ap[23]), .ZN(n_1_0_1095)); + SDFF_X1_LVT \registers_reg[27][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_27__ap[23]), .CK(n_0_57), .Q(registers_27__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[11][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_11__ap[23]), .CK(n_0_41), .Q(registers_11__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1150 (.A1(registers_27__ap[23]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[23]), .ZN(n_1_0_1094)); + SDFF_X1_LVT \registers_reg[13][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_13__ap[23]), .CK(n_0_43), .Q(registers_13__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[5][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_5__ap[23]), .CK(n_0_35), .Q(registers_5__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1149 (.A1(registers_13__ap[23]), .A2(n_1_0_1277), .B1( + n_1_0_1273), .B2(registers_5__ap[23]), .ZN(n_1_0_1093)); + SDFF_X1_LVT \registers_reg[4][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_4__ap[23]), .CK(n_0_34), .Q(registers_4__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[12][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_12__ap[23]), .CK(n_0_42), .Q(registers_12__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1148 (.A1(registers_4__ap[23]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[23]), .ZN(n_1_0_1092)); + NAND3_X1_LVT i_1_0_1147 (.A1(n_1_0_1094), .A2(n_1_0_1093), .A3(n_1_0_1092), + .ZN(n_1_0_1091)); + SDFF_X1_LVT \registers_reg[2][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_2__ap[23]), .CK(n_0_32), .Q(registers_2__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[10][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_10__ap[23]), .CK(n_0_40), .Q(registers_10__ap[23]), .QN()); + AOI221_X1_LVT i_1_0_1146 (.A(n_1_0_1091), .B1(n_1_0_1268), .B2( + registers_2__ap[23]), .C1(registers_10__ap[23]), .C2(n_1_0_1287), .ZN( + n_1_0_1090)); + AND4_X1_LVT i_1_0_1145 (.A1(n_1_0_1097), .A2(n_1_0_1096), .A3(n_1_0_1095), + .A4(n_1_0_1090), .ZN(n_1_0_1089)); + NAND3_X1_LVT i_1_0_1144 (.A1(n_1_0_1100), .A2(n_1_0_1098), .A3(n_1_0_1089), + .ZN(RRs1[23])); + AND2_X1_LVT i_0_0_22 (.A1(n_0_0_16), .A2(WRd[22]), .ZN(registers[22])); + SDFF_X1_LVT \registers_reg[17][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_17__ap[22]), .CK(n_0_47), .Q(registers_17__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[21][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_21__ap[22]), .CK(n_0_51), .Q(registers_21__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1142 (.A1(registers_17__ap[22]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[22]), .ZN(n_1_0_1087)); + SDFF_X1_LVT \registers_reg[6][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_6__ap[22]), .CK(n_0_36), .Q(registers_6__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[11][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_11__ap[22]), .CK(n_0_41), .Q(registers_11__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1143 (.A1(registers_6__ap[22]), .A2(n_1_0_1300), .B1( + n_1_0_1270), .B2(registers_11__ap[22]), .ZN(n_1_0_1088)); + SDFF_X1_LVT \registers_reg[20][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_20__ap[22]), .CK(n_0_50), .Q(registers_20__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[12][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_12__ap[22]), .CK(n_0_42), .Q(registers_12__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1141 (.A1(registers_20__ap[22]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[22]), .ZN(n_1_0_1086)); + SDFF_X1_LVT \registers_reg[10][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_10__ap[22]), .CK(n_0_40), .Q(registers_10__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[5][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_5__ap[22]), .CK(n_0_35), .Q(registers_5__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1140 (.A1(registers_10__ap[22]), .A2(n_1_0_1287), .B1( + n_1_0_1273), .B2(registers_5__ap[22]), .ZN(n_1_0_1085)); + NAND3_X1_LVT i_1_0_1139 (.A1(n_1_0_1088), .A2(n_1_0_1086), .A3(n_1_0_1085), + .ZN(n_1_0_1084)); + SDFF_X1_LVT \registers_reg[31][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_31__ap[22]), .CK(n_0_61), .Q(registers_31__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[2][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_2__ap[22]), .CK(n_0_32), .Q(registers_2__ap[22]), .QN()); + AOI221_X1_LVT i_1_0_1138 (.A(n_1_0_1084), .B1(n_1_0_1266), .B2( + registers_31__ap[22]), .C1(registers_2__ap[22]), .C2(n_1_0_1268), .ZN( + n_1_0_1083)); + SDFF_X1_LVT \registers_reg[22][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_22__ap[22]), .CK(n_0_52), .Q(registers_22__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[26][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_26__ap[22]), .CK(n_0_56), .Q(registers_26__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[13][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_13__ap[22]), .CK(n_0_43), .Q(registers_13__ap[22]), .QN()); + AOI222_X1_LVT i_1_0_1137 (.A1(registers_22__ap[22]), .A2(n_1_0_1294), + .B1(n_1_0_1285), .B2(registers_26__ap[22]), .C1(n_1_0_1277), .C2( + registers_13__ap[22]), .ZN(n_1_0_1082)); + NAND2_X1_LVT i_1_0_1136 (.A1(n_1_0_1083), .A2(n_1_0_1082), .ZN(n_1_0_1081)); + SDFF_X1_LVT \registers_reg[1][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_1__ap[22]), .CK(n_0_0), .Q(registers_1__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[28][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_28__ap[22]), .CK(n_0_58), .Q(registers_28__ap[22]), .QN()); + AOI221_X1_LVT i_1_0_1135 (.A(n_1_0_1081), .B1(n_1_0_1274), .B2( + registers_1__ap[22]), .C1(registers_28__ap[22]), .C2(n_1_0_1283), .ZN( + n_1_0_1080)); + SDFF_X1_LVT \registers_reg[18][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_18__ap[22]), .CK(n_0_48), .Q(registers_18__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[30][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_30__ap[22]), .CK(n_0_60), .Q(registers_30__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1134 (.A1(registers_18__ap[22]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[22]), .ZN(n_1_0_1079)); + SDFF_X1_LVT \registers_reg[24][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_24__ap[22]), .CK(n_0_54), .Q(registers_24__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[4][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_4__ap[22]), .CK(n_0_34), .Q(registers_4__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1133 (.A1(registers_24__ap[22]), .A2(n_1_0_1289), .B1( + n_1_0_1278), .B2(registers_4__ap[22]), .ZN(n_1_0_1078)); + SDFF_X1_LVT \registers_reg[15][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_15__ap[22]), .CK(n_0_45), .Q(registers_15__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[16][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_16__ap[22]), .CK(n_0_46), .Q(registers_16__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1132 (.A1(registers_15__ap[22]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[22]), .ZN(n_1_0_1077)); + NAND3_X1_LVT i_1_0_1131 (.A1(n_1_0_1079), .A2(n_1_0_1078), .A3(n_1_0_1077), + .ZN(n_1_0_1076)); + SDFF_X1_LVT \registers_reg[19][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_19__ap[22]), .CK(n_0_49), .Q(registers_19__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[25][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_25__ap[22]), .CK(n_0_55), .Q(registers_25__ap[22]), .QN()); + AOI221_X1_LVT i_1_0_1130 (.A(n_1_0_1076), .B1(n_1_0_1295), .B2( + registers_19__ap[22]), .C1(registers_25__ap[22]), .C2(n_1_0_1269), + .ZN(n_1_0_1075)); + SDFF_X1_LVT \registers_reg[7][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_7__ap[22]), .CK(n_0_37), .Q(registers_7__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[14][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_14__ap[22]), .CK(n_0_44), .Q(registers_14__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1129 (.A1(registers_7__ap[22]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[22]), .ZN(n_1_0_1074)); + SDFF_X1_LVT \registers_reg[9][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_9__ap[22]), .CK(n_0_39), .Q(registers_9__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[29][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_29__ap[22]), .CK(n_0_59), .Q(registers_29__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1128 (.A1(registers_9__ap[22]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[22]), .ZN(n_1_0_1073)); + SDFF_X1_LVT \registers_reg[8][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_8__ap[22]), .CK(n_0_38), .Q(registers_8__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[23][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_23__ap[22]), .CK(n_0_53), .Q(registers_23__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1127 (.A1(registers_8__ap[22]), .A2(n_1_0_1282), .B1( + n_1_0_1264), .B2(registers_23__ap[22]), .ZN(n_1_0_1072)); + NAND3_X1_LVT i_1_0_1126 (.A1(n_1_0_1074), .A2(n_1_0_1073), .A3(n_1_0_1072), + .ZN(n_1_0_1071)); + SDFF_X1_LVT \registers_reg[27][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_27__ap[22]), .CK(n_0_57), .Q(registers_27__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[3][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_3__ap[22]), .CK(n_0_33), .Q(registers_3__ap[22]), .QN()); + AOI221_X1_LVT i_1_0_1125 (.A(n_1_0_1071), .B1(n_1_0_1279), .B2( + registers_27__ap[22]), .C1(registers_3__ap[22]), .C2(n_1_0_1257), .ZN( + n_1_0_1070)); + NAND4_X1_LVT i_1_0_1124 (.A1(n_1_0_1087), .A2(n_1_0_1080), .A3(n_1_0_1075), + .A4(n_1_0_1070), .ZN(RRs1[22])); + AND2_X1_LVT i_0_0_21 (.A1(n_0_0_16), .A2(WRd[21]), .ZN(registers[21])); + SDFF_X1_LVT \registers_reg[17][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_17__ap[21]), .CK(n_0_47), .Q(registers_17__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[21][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_21__ap[21]), .CK(n_0_51), .Q(registers_21__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1122 (.A1(registers_17__ap[21]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[21]), .ZN(n_1_0_1068)); + SDFF_X1_LVT \registers_reg[6][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_6__ap[21]), .CK(n_0_36), .Q(registers_6__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[8][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_8__ap[21]), .CK(n_0_38), .Q(registers_8__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1123 (.A1(registers_6__ap[21]), .A2(n_1_0_1300), .B1( + n_1_0_1282), .B2(registers_8__ap[21]), .ZN(n_1_0_1069)); + SDFF_X1_LVT \registers_reg[20][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_20__ap[21]), .CK(n_0_50), .Q(registers_20__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[12][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_12__ap[21]), .CK(n_0_42), .Q(registers_12__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1121 (.A1(registers_20__ap[21]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[21]), .ZN(n_1_0_1067)); + SDFF_X1_LVT \registers_reg[5][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_5__ap[21]), .CK(n_0_35), .Q(registers_5__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[11][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_11__ap[21]), .CK(n_0_41), .Q(registers_11__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1120 (.A1(registers_5__ap[21]), .A2(n_1_0_1273), .B1( + n_1_0_1270), .B2(registers_11__ap[21]), .ZN(n_1_0_1066)); + NAND3_X1_LVT i_1_0_1119 (.A1(n_1_0_1069), .A2(n_1_0_1067), .A3(n_1_0_1066), + .ZN(n_1_0_1065)); + SDFF_X1_LVT \registers_reg[10][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_10__ap[21]), .CK(n_0_40), .Q(registers_10__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[2][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_2__ap[21]), .CK(n_0_32), .Q(registers_2__ap[21]), .QN()); + AOI221_X1_LVT i_1_0_1118 (.A(n_1_0_1065), .B1(n_1_0_1287), .B2( + registers_10__ap[21]), .C1(registers_2__ap[21]), .C2(n_1_0_1268), .ZN( + n_1_0_1064)); + SDFF_X1_LVT \registers_reg[13][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_13__ap[21]), .CK(n_0_43), .Q(registers_13__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[30][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_30__ap[21]), .CK(n_0_60), .Q(registers_30__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[22][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_22__ap[21]), .CK(n_0_52), .Q(registers_22__ap[21]), .QN()); + AOI222_X1_LVT i_1_0_1117 (.A1(registers_13__ap[21]), .A2(n_1_0_1277), + .B1(n_1_0_1272), .B2(registers_30__ap[21]), .C1(registers_22__ap[21]), + .C2(n_1_0_1294), .ZN(n_1_0_1063)); + NAND2_X1_LVT i_1_0_1116 (.A1(n_1_0_1064), .A2(n_1_0_1063), .ZN(n_1_0_1062)); + SDFF_X1_LVT \registers_reg[1][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_1__ap[21]), .CK(n_0_0), .Q(registers_1__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[28][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_28__ap[21]), .CK(n_0_58), .Q(registers_28__ap[21]), .QN()); + AOI221_X1_LVT i_1_0_1115 (.A(n_1_0_1062), .B1(n_1_0_1274), .B2( + registers_1__ap[21]), .C1(registers_28__ap[21]), .C2(n_1_0_1283), .ZN( + n_1_0_1061)); + SDFF_X1_LVT \registers_reg[18][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_18__ap[21]), .CK(n_0_48), .Q(registers_18__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[26][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_26__ap[21]), .CK(n_0_56), .Q(registers_26__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1114 (.A1(registers_18__ap[21]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[21]), .ZN(n_1_0_1060)); + SDFF_X1_LVT \registers_reg[24][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_24__ap[21]), .CK(n_0_54), .Q(registers_24__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[4][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_4__ap[21]), .CK(n_0_34), .Q(registers_4__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1113 (.A1(registers_24__ap[21]), .A2(n_1_0_1289), .B1( + n_1_0_1278), .B2(registers_4__ap[21]), .ZN(n_1_0_1059)); + SDFF_X1_LVT \registers_reg[15][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_15__ap[21]), .CK(n_0_45), .Q(registers_15__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[16][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_16__ap[21]), .CK(n_0_46), .Q(registers_16__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1112 (.A1(registers_15__ap[21]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[21]), .ZN(n_1_0_1058)); + NAND3_X1_LVT i_1_0_1111 (.A1(n_1_0_1060), .A2(n_1_0_1059), .A3(n_1_0_1058), + .ZN(n_1_0_1057)); + SDFF_X1_LVT \registers_reg[19][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_19__ap[21]), .CK(n_0_49), .Q(registers_19__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[25][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_25__ap[21]), .CK(n_0_55), .Q(registers_25__ap[21]), .QN()); + AOI221_X1_LVT i_1_0_1110 (.A(n_1_0_1057), .B1(n_1_0_1295), .B2( + registers_19__ap[21]), .C1(registers_25__ap[21]), .C2(n_1_0_1269), + .ZN(n_1_0_1056)); + SDFF_X1_LVT \registers_reg[7][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_7__ap[21]), .CK(n_0_37), .Q(registers_7__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[14][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_14__ap[21]), .CK(n_0_44), .Q(registers_14__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1109 (.A1(registers_7__ap[21]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[21]), .ZN(n_1_0_1055)); + SDFF_X1_LVT \registers_reg[9][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_9__ap[21]), .CK(n_0_39), .Q(registers_9__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[29][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_29__ap[21]), .CK(n_0_59), .Q(registers_29__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1108 (.A1(registers_9__ap[21]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[21]), .ZN(n_1_0_1054)); + SDFF_X1_LVT \registers_reg[23][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_23__ap[21]), .CK(n_0_53), .Q(registers_23__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[3][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_3__ap[21]), .CK(n_0_33), .Q(registers_3__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1107 (.A1(registers_23__ap[21]), .A2(n_1_0_1264), .B1( + n_1_0_1257), .B2(registers_3__ap[21]), .ZN(n_1_0_1053)); + NAND3_X1_LVT i_1_0_1106 (.A1(n_1_0_1055), .A2(n_1_0_1054), .A3(n_1_0_1053), + .ZN(n_1_0_1052)); + SDFF_X1_LVT \registers_reg[27][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_27__ap[21]), .CK(n_0_57), .Q(registers_27__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[31][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_31__ap[21]), .CK(n_0_61), .Q(registers_31__ap[21]), .QN()); + AOI221_X1_LVT i_1_0_1105 (.A(n_1_0_1052), .B1(n_1_0_1279), .B2( + registers_27__ap[21]), .C1(registers_31__ap[21]), .C2(n_1_0_1266), + .ZN(n_1_0_1051)); + NAND4_X1_LVT i_1_0_1104 (.A1(n_1_0_1068), .A2(n_1_0_1061), .A3(n_1_0_1056), + .A4(n_1_0_1051), .ZN(RRs1[21])); + AND2_X1_LVT i_0_0_20 (.A1(n_0_0_16), .A2(WRd[20]), .ZN(registers[20])); + SDFF_X1_LVT \registers_reg[17][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_17__ap[20]), .CK(n_0_47), .Q(registers_17__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[21][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_21__ap[20]), .CK(n_0_51), .Q(registers_21__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1100 (.A1(registers_17__ap[20]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[20]), .ZN(n_1_0_1047)); + SDFF_X1_LVT \registers_reg[10][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_10__ap[20]), .CK(n_0_40), .Q(registers_10__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[2][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_2__ap[20]), .CK(n_0_32), .Q(registers_2__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1103 (.A1(registers_10__ap[20]), .A2(n_1_0_1287), .B1( + n_1_0_1268), .B2(registers_2__ap[20]), .ZN(n_1_0_1050)); + SDFF_X1_LVT \registers_reg[20][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_20__ap[20]), .CK(n_0_50), .Q(registers_20__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[12][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_12__ap[20]), .CK(n_0_42), .Q(registers_12__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1099 (.A1(registers_20__ap[20]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[20]), .ZN(n_1_0_1046)); + SDFF_X1_LVT \registers_reg[15][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_15__ap[20]), .CK(n_0_45), .Q(registers_15__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[8][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_8__ap[20]), .CK(n_0_38), .Q(registers_8__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1102 (.A1(registers_15__ap[20]), .A2(n_1_0_1286), .B1( + n_1_0_1282), .B2(registers_8__ap[20]), .ZN(n_1_0_1049)); + INV_X1_LVT i_1_0_1101 (.A(n_1_0_1049), .ZN(n_1_0_1048)); + SDFF_X1_LVT \registers_reg[11][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_11__ap[20]), .CK(n_0_41), .Q(registers_11__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[5][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_5__ap[20]), .CK(n_0_35), .Q(registers_5__ap[20]), .QN()); + AOI221_X1_LVT i_1_0_1098 (.A(n_1_0_1048), .B1(n_1_0_1270), .B2( + registers_11__ap[20]), .C1(registers_5__ap[20]), .C2(n_1_0_1273), .ZN( + n_1_0_1045)); + SDFF_X1_LVT \registers_reg[13][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_13__ap[20]), .CK(n_0_43), .Q(registers_13__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[30][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_30__ap[20]), .CK(n_0_60), .Q(registers_30__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[22][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_22__ap[20]), .CK(n_0_52), .Q(registers_22__ap[20]), .QN()); + AOI222_X1_LVT i_1_0_1097 (.A1(registers_13__ap[20]), .A2(n_1_0_1277), + .B1(n_1_0_1272), .B2(registers_30__ap[20]), .C1(registers_22__ap[20]), + .C2(n_1_0_1294), .ZN(n_1_0_1044)); + NAND4_X1_LVT i_1_0_1096 (.A1(n_1_0_1050), .A2(n_1_0_1046), .A3(n_1_0_1045), + .A4(n_1_0_1044), .ZN(n_1_0_1043)); + SDFF_X1_LVT \registers_reg[1][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_1__ap[20]), .CK(n_0_0), .Q(registers_1__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[28][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_28__ap[20]), .CK(n_0_58), .Q(registers_28__ap[20]), .QN()); + AOI221_X1_LVT i_1_0_1095 (.A(n_1_0_1043), .B1(n_1_0_1274), .B2( + registers_1__ap[20]), .C1(registers_28__ap[20]), .C2(n_1_0_1283), .ZN( + n_1_0_1042)); + SDFF_X1_LVT \registers_reg[18][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_18__ap[20]), .CK(n_0_48), .Q(registers_18__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[26][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_26__ap[20]), .CK(n_0_56), .Q(registers_26__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1094 (.A1(registers_18__ap[20]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[20]), .ZN(n_1_0_1041)); + SDFF_X1_LVT \registers_reg[24][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_24__ap[20]), .CK(n_0_54), .Q(registers_24__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[4][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_4__ap[20]), .CK(n_0_34), .Q(registers_4__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1093 (.A1(registers_24__ap[20]), .A2(n_1_0_1289), .B1( + n_1_0_1278), .B2(registers_4__ap[20]), .ZN(n_1_0_1040)); + SDFF_X1_LVT \registers_reg[6][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_6__ap[20]), .CK(n_0_36), .Q(registers_6__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[25][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_25__ap[20]), .CK(n_0_55), .Q(registers_25__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1092 (.A1(registers_6__ap[20]), .A2(n_1_0_1300), .B1( + n_1_0_1269), .B2(registers_25__ap[20]), .ZN(n_1_0_1039)); + NAND3_X1_LVT i_1_0_1091 (.A1(n_1_0_1041), .A2(n_1_0_1040), .A3(n_1_0_1039), + .ZN(n_1_0_1038)); + SDFF_X1_LVT \registers_reg[19][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_19__ap[20]), .CK(n_0_49), .Q(registers_19__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[16][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_16__ap[20]), .CK(n_0_46), .Q(registers_16__ap[20]), .QN()); + AOI221_X1_LVT i_1_0_1090 (.A(n_1_0_1038), .B1(n_1_0_1295), .B2( + registers_19__ap[20]), .C1(registers_16__ap[20]), .C2(n_1_0_1267), + .ZN(n_1_0_1037)); + SDFF_X1_LVT \registers_reg[7][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_7__ap[20]), .CK(n_0_37), .Q(registers_7__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[14][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_14__ap[20]), .CK(n_0_44), .Q(registers_14__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1089 (.A1(registers_7__ap[20]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[20]), .ZN(n_1_0_1036)); + SDFF_X1_LVT \registers_reg[9][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_9__ap[20]), .CK(n_0_39), .Q(registers_9__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[29][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_29__ap[20]), .CK(n_0_59), .Q(registers_29__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1088 (.A1(registers_9__ap[20]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[20]), .ZN(n_1_0_1035)); + SDFF_X1_LVT \registers_reg[23][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_23__ap[20]), .CK(n_0_53), .Q(registers_23__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[3][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_3__ap[20]), .CK(n_0_33), .Q(registers_3__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1087 (.A1(registers_23__ap[20]), .A2(n_1_0_1264), .B1( + n_1_0_1257), .B2(registers_3__ap[20]), .ZN(n_1_0_1034)); + NAND3_X1_LVT i_1_0_1086 (.A1(n_1_0_1036), .A2(n_1_0_1035), .A3(n_1_0_1034), + .ZN(n_1_0_1033)); + SDFF_X1_LVT \registers_reg[27][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_27__ap[20]), .CK(n_0_57), .Q(registers_27__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[31][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_31__ap[20]), .CK(n_0_61), .Q(registers_31__ap[20]), .QN()); + AOI221_X1_LVT i_1_0_1085 (.A(n_1_0_1033), .B1(n_1_0_1279), .B2( + registers_27__ap[20]), .C1(registers_31__ap[20]), .C2(n_1_0_1266), + .ZN(n_1_0_1032)); + NAND4_X1_LVT i_1_0_1084 (.A1(n_1_0_1047), .A2(n_1_0_1042), .A3(n_1_0_1037), + .A4(n_1_0_1032), .ZN(RRs1[20])); + AND2_X1_LVT i_0_0_19 (.A1(n_0_0_16), .A2(WRd[19]), .ZN(registers[19])); + SDFF_X1_LVT \registers_reg[17][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_17__ap[19]), .CK(n_0_47), .Q(registers_17__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[21][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_21__ap[19]), .CK(n_0_51), .Q(registers_21__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1080 (.A1(registers_17__ap[19]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[19]), .ZN(n_1_0_1028)); + SDFF_X1_LVT \registers_reg[2][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_2__ap[19]), .CK(n_0_32), .Q(registers_2__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[31][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_31__ap[19]), .CK(n_0_61), .Q(registers_31__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1083 (.A1(registers_2__ap[19]), .A2(n_1_0_1268), .B1( + n_1_0_1266), .B2(registers_31__ap[19]), .ZN(n_1_0_1031)); + SDFF_X1_LVT \registers_reg[20][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_20__ap[19]), .CK(n_0_50), .Q(registers_20__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[12][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_12__ap[19]), .CK(n_0_42), .Q(registers_12__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1079 (.A1(registers_20__ap[19]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[19]), .ZN(n_1_0_1027)); + SDFF_X1_LVT \registers_reg[15][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_15__ap[19]), .CK(n_0_45), .Q(registers_15__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[11][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_11__ap[19]), .CK(n_0_41), .Q(registers_11__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1082 (.A1(registers_15__ap[19]), .A2(n_1_0_1286), .B1( + n_1_0_1270), .B2(registers_11__ap[19]), .ZN(n_1_0_1030)); + INV_X1_LVT i_1_0_1081 (.A(n_1_0_1030), .ZN(n_1_0_1029)); + SDFF_X1_LVT \registers_reg[27][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_27__ap[19]), .CK(n_0_57), .Q(registers_27__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[24][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_24__ap[19]), .CK(n_0_54), .Q(registers_24__ap[19]), .QN()); + AOI221_X1_LVT i_1_0_1078 (.A(n_1_0_1029), .B1(n_1_0_1279), .B2( + registers_27__ap[19]), .C1(registers_24__ap[19]), .C2(n_1_0_1289), + .ZN(n_1_0_1026)); + SDFF_X1_LVT \registers_reg[22][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_22__ap[19]), .CK(n_0_52), .Q(registers_22__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[26][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_26__ap[19]), .CK(n_0_56), .Q(registers_26__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[13][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_13__ap[19]), .CK(n_0_43), .Q(registers_13__ap[19]), .QN()); + AOI222_X1_LVT i_1_0_1077 (.A1(registers_22__ap[19]), .A2(n_1_0_1294), + .B1(n_1_0_1285), .B2(registers_26__ap[19]), .C1(n_1_0_1277), .C2( + registers_13__ap[19]), .ZN(n_1_0_1025)); + NAND4_X1_LVT i_1_0_1076 (.A1(n_1_0_1031), .A2(n_1_0_1027), .A3(n_1_0_1026), + .A4(n_1_0_1025), .ZN(n_1_0_1024)); + SDFF_X1_LVT \registers_reg[1][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_1__ap[19]), .CK(n_0_0), .Q(registers_1__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[28][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_28__ap[19]), .CK(n_0_58), .Q(registers_28__ap[19]), .QN()); + AOI221_X1_LVT i_1_0_1075 (.A(n_1_0_1024), .B1(n_1_0_1274), .B2( + registers_1__ap[19]), .C1(registers_28__ap[19]), .C2(n_1_0_1283), .ZN( + n_1_0_1023)); + SDFF_X1_LVT \registers_reg[18][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_18__ap[19]), .CK(n_0_48), .Q(registers_18__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[30][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_30__ap[19]), .CK(n_0_60), .Q(registers_30__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1074 (.A1(registers_18__ap[19]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[19]), .ZN(n_1_0_1022)); + SDFF_X1_LVT \registers_reg[4][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_4__ap[19]), .CK(n_0_34), .Q(registers_4__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[5][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_5__ap[19]), .CK(n_0_35), .Q(registers_5__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1073 (.A1(registers_4__ap[19]), .A2(n_1_0_1278), .B1( + n_1_0_1273), .B2(registers_5__ap[19]), .ZN(n_1_0_1021)); + SDFF_X1_LVT \registers_reg[6][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_6__ap[19]), .CK(n_0_36), .Q(registers_6__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[25][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_25__ap[19]), .CK(n_0_55), .Q(registers_25__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1072 (.A1(registers_6__ap[19]), .A2(n_1_0_1300), .B1( + n_1_0_1269), .B2(registers_25__ap[19]), .ZN(n_1_0_1020)); + NAND3_X1_LVT i_1_0_1071 (.A1(n_1_0_1022), .A2(n_1_0_1021), .A3(n_1_0_1020), + .ZN(n_1_0_1019)); + SDFF_X1_LVT \registers_reg[19][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_19__ap[19]), .CK(n_0_49), .Q(registers_19__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[16][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_16__ap[19]), .CK(n_0_46), .Q(registers_16__ap[19]), .QN()); + AOI221_X1_LVT i_1_0_1070 (.A(n_1_0_1019), .B1(n_1_0_1295), .B2( + registers_19__ap[19]), .C1(registers_16__ap[19]), .C2(n_1_0_1267), + .ZN(n_1_0_1018)); + SDFF_X1_LVT \registers_reg[9][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_9__ap[19]), .CK(n_0_39), .Q(registers_9__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[29][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_29__ap[19]), .CK(n_0_59), .Q(registers_29__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1069 (.A1(registers_9__ap[19]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[19]), .ZN(n_1_0_1017)); + SDFF_X1_LVT \registers_reg[8][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_8__ap[19]), .CK(n_0_38), .Q(registers_8__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[23][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_23__ap[19]), .CK(n_0_53), .Q(registers_23__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1068 (.A1(registers_8__ap[19]), .A2(n_1_0_1282), .B1( + n_1_0_1264), .B2(registers_23__ap[19]), .ZN(n_1_0_1016)); + SDFF_X1_LVT \registers_reg[7][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_7__ap[19]), .CK(n_0_37), .Q(registers_7__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[14][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_14__ap[19]), .CK(n_0_44), .Q(registers_14__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1067 (.A1(registers_7__ap[19]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[19]), .ZN(n_1_0_1015)); + NAND3_X1_LVT i_1_0_1066 (.A1(n_1_0_1017), .A2(n_1_0_1016), .A3(n_1_0_1015), + .ZN(n_1_0_1014)); + SDFF_X1_LVT \registers_reg[10][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_10__ap[19]), .CK(n_0_40), .Q(registers_10__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[3][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_3__ap[19]), .CK(n_0_33), .Q(registers_3__ap[19]), .QN()); + AOI221_X1_LVT i_1_0_1065 (.A(n_1_0_1014), .B1(n_1_0_1287), .B2( + registers_10__ap[19]), .C1(registers_3__ap[19]), .C2(n_1_0_1257), .ZN( + n_1_0_1013)); + NAND4_X1_LVT i_1_0_1064 (.A1(n_1_0_1028), .A2(n_1_0_1023), .A3(n_1_0_1018), + .A4(n_1_0_1013), .ZN(RRs1[19])); + AND2_X1_LVT i_0_0_18 (.A1(n_0_0_16), .A2(WRd[18]), .ZN(registers[18])); + SDFF_X1_LVT \registers_reg[24][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_24__ap[18]), .CK(n_0_54), .Q(registers_24__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[28][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_28__ap[18]), .CK(n_0_58), .Q(registers_28__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1062 (.A1(registers_24__ap[18]), .A2(n_1_0_1289), .B1( + n_1_0_1283), .B2(registers_28__ap[18]), .ZN(n_1_0_1011)); + SDFF_X1_LVT \registers_reg[11][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_11__ap[18]), .CK(n_0_41), .Q(registers_11__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[16][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_16__ap[18]), .CK(n_0_46), .Q(registers_16__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1063 (.A1(registers_11__ap[18]), .A2(n_1_0_1270), .B1( + n_1_0_1267), .B2(registers_16__ap[18]), .ZN(n_1_0_1012)); + SDFF_X1_LVT \registers_reg[9][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_9__ap[18]), .CK(n_0_39), .Q(registers_9__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[7][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_7__ap[18]), .CK(n_0_37), .Q(registers_7__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1061 (.A1(registers_9__ap[18]), .A2(n_1_0_1291), .B1( + n_1_0_1263), .B2(registers_7__ap[18]), .ZN(n_1_0_1010)); + SDFF_X1_LVT \registers_reg[27][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_27__ap[18]), .CK(n_0_57), .Q(registers_27__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[25][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_25__ap[18]), .CK(n_0_55), .Q(registers_25__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1060 (.A1(registers_27__ap[18]), .A2(n_1_0_1279), .B1( + n_1_0_1269), .B2(registers_25__ap[18]), .ZN(n_1_0_1009)); + NAND3_X1_LVT i_1_0_1059 (.A1(n_1_0_1012), .A2(n_1_0_1010), .A3(n_1_0_1009), + .ZN(n_1_0_1008)); + SDFF_X1_LVT \registers_reg[31][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_31__ap[18]), .CK(n_0_61), .Q(registers_31__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[6][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_6__ap[18]), .CK(n_0_36), .Q(registers_6__ap[18]), .QN()); + AOI221_X1_LVT i_1_0_1058 (.A(n_1_0_1008), .B1(n_1_0_1266), .B2( + registers_31__ap[18]), .C1(registers_6__ap[18]), .C2(n_1_0_1300), .ZN( + n_1_0_1007)); + SDFF_X1_LVT \registers_reg[22][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_22__ap[18]), .CK(n_0_52), .Q(registers_22__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[26][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_26__ap[18]), .CK(n_0_56), .Q(registers_26__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[1][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_1__ap[18]), .CK(n_0_0), .Q(registers_1__ap[18]), .QN()); + AOI222_X1_LVT i_1_0_1057 (.A1(registers_22__ap[18]), .A2(n_1_0_1294), + .B1(n_1_0_1285), .B2(registers_26__ap[18]), .C1(n_1_0_1274), .C2( + registers_1__ap[18]), .ZN(n_1_0_1006)); + NAND2_X1_LVT i_1_0_1056 (.A1(n_1_0_1007), .A2(n_1_0_1006), .ZN(n_1_0_1005)); + SDFF_X1_LVT \registers_reg[29][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_29__ap[18]), .CK(n_0_59), .Q(registers_29__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[2][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_2__ap[18]), .CK(n_0_32), .Q(registers_2__ap[18]), .QN()); + AOI221_X1_LVT i_1_0_1055 (.A(n_1_0_1005), .B1(n_1_0_1276), .B2( + registers_29__ap[18]), .C1(registers_2__ap[18]), .C2(n_1_0_1268), .ZN( + n_1_0_1004)); + SDFF_X1_LVT \registers_reg[18][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_18__ap[18]), .CK(n_0_48), .Q(registers_18__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[30][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_30__ap[18]), .CK(n_0_60), .Q(registers_30__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1054 (.A1(registers_18__ap[18]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[18]), .ZN(n_1_0_1003)); + SDFF_X1_LVT \registers_reg[4][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_4__ap[18]), .CK(n_0_34), .Q(registers_4__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[12][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_12__ap[18]), .CK(n_0_42), .Q(registers_12__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1053 (.A1(registers_4__ap[18]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[18]), .ZN(n_1_0_1002)); + SDFF_X1_LVT \registers_reg[19][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_19__ap[18]), .CK(n_0_49), .Q(registers_19__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[21][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_21__ap[18]), .CK(n_0_51), .Q(registers_21__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1052 (.A1(registers_19__ap[18]), .A2(n_1_0_1295), .B1( + n_1_0_1259), .B2(registers_21__ap[18]), .ZN(n_1_0_1001)); + NAND3_X1_LVT i_1_0_1051 (.A1(n_1_0_1003), .A2(n_1_0_1002), .A3(n_1_0_1001), + .ZN(n_1_0_1000)); + SDFF_X1_LVT \registers_reg[5][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_5__ap[18]), .CK(n_0_35), .Q(registers_5__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[20][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_20__ap[18]), .CK(n_0_50), .Q(registers_20__ap[18]), .QN()); + AOI221_X1_LVT i_1_0_1050 (.A(n_1_0_1000), .B1(n_1_0_1273), .B2( + registers_5__ap[18]), .C1(registers_20__ap[18]), .C2(n_1_0_1281), .ZN( + n_1_0_999)); + SDFF_X1_LVT \registers_reg[8][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_8__ap[18]), .CK(n_0_38), .Q(registers_8__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[23][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_23__ap[18]), .CK(n_0_53), .Q(registers_23__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1049 (.A1(registers_8__ap[18]), .A2(n_1_0_1282), .B1( + n_1_0_1264), .B2(registers_23__ap[18]), .ZN(n_1_0_998)); + SDFF_X1_LVT \registers_reg[13][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_13__ap[18]), .CK(n_0_43), .Q(registers_13__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[17][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_17__ap[18]), .CK(n_0_47), .Q(registers_17__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1048 (.A1(registers_13__ap[18]), .A2(n_1_0_1277), .B1( + n_1_0_1271), .B2(registers_17__ap[18]), .ZN(n_1_0_997)); + SDFF_X1_LVT \registers_reg[15][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_15__ap[18]), .CK(n_0_45), .Q(registers_15__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[14][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_14__ap[18]), .CK(n_0_44), .Q(registers_14__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1047 (.A1(registers_15__ap[18]), .A2(n_1_0_1286), .B1( + n_1_0_1258), .B2(registers_14__ap[18]), .ZN(n_1_0_996)); + NAND3_X1_LVT i_1_0_1046 (.A1(n_1_0_998), .A2(n_1_0_997), .A3(n_1_0_996), + .ZN(n_1_0_995)); + SDFF_X1_LVT \registers_reg[10][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_10__ap[18]), .CK(n_0_40), .Q(registers_10__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[3][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_3__ap[18]), .CK(n_0_33), .Q(registers_3__ap[18]), .QN()); + AOI221_X1_LVT i_1_0_1045 (.A(n_1_0_995), .B1(n_1_0_1287), .B2( + registers_10__ap[18]), .C1(registers_3__ap[18]), .C2(n_1_0_1257), .ZN( + n_1_0_994)); + NAND4_X1_LVT i_1_0_1044 (.A1(n_1_0_1011), .A2(n_1_0_1004), .A3(n_1_0_999), + .A4(n_1_0_994), .ZN(RRs1[18])); + AND2_X1_LVT i_0_0_17 (.A1(n_0_0_16), .A2(WRd[17]), .ZN(registers[17])); + SDFF_X1_LVT \registers_reg[17][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_17__ap[17]), .CK(n_0_47), .Q(registers_17__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[21][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_21__ap[17]), .CK(n_0_51), .Q(registers_21__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1040 (.A1(registers_17__ap[17]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[17]), .ZN(n_1_0_990)); + SDFF_X1_LVT \registers_reg[2][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_2__ap[17]), .CK(n_0_32), .Q(registers_2__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[31][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_31__ap[17]), .CK(n_0_61), .Q(registers_31__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1043 (.A1(registers_2__ap[17]), .A2(n_1_0_1268), .B1( + n_1_0_1266), .B2(registers_31__ap[17]), .ZN(n_1_0_993)); + SDFF_X1_LVT \registers_reg[20][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_20__ap[17]), .CK(n_0_50), .Q(registers_20__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[12][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_12__ap[17]), .CK(n_0_42), .Q(registers_12__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1039 (.A1(registers_20__ap[17]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[17]), .ZN(n_1_0_989)); + SDFF_X1_LVT \registers_reg[15][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_15__ap[17]), .CK(n_0_45), .Q(registers_15__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[11][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_11__ap[17]), .CK(n_0_41), .Q(registers_11__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1042 (.A1(registers_15__ap[17]), .A2(n_1_0_1286), .B1( + n_1_0_1270), .B2(registers_11__ap[17]), .ZN(n_1_0_992)); + INV_X1_LVT i_1_0_1041 (.A(n_1_0_992), .ZN(n_1_0_991)); + SDFF_X1_LVT \registers_reg[10][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_10__ap[17]), .CK(n_0_40), .Q(registers_10__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[24][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_24__ap[17]), .CK(n_0_54), .Q(registers_24__ap[17]), .QN()); + AOI221_X1_LVT i_1_0_1038 (.A(n_1_0_991), .B1(n_1_0_1287), .B2( + registers_10__ap[17]), .C1(registers_24__ap[17]), .C2(n_1_0_1289), + .ZN(n_1_0_988)); + SDFF_X1_LVT \registers_reg[22][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_22__ap[17]), .CK(n_0_52), .Q(registers_22__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[26][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_26__ap[17]), .CK(n_0_56), .Q(registers_26__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[13][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_13__ap[17]), .CK(n_0_43), .Q(registers_13__ap[17]), .QN()); + AOI222_X1_LVT i_1_0_1037 (.A1(registers_22__ap[17]), .A2(n_1_0_1294), + .B1(n_1_0_1285), .B2(registers_26__ap[17]), .C1(n_1_0_1277), .C2( + registers_13__ap[17]), .ZN(n_1_0_987)); + NAND4_X1_LVT i_1_0_1036 (.A1(n_1_0_993), .A2(n_1_0_989), .A3(n_1_0_988), + .A4(n_1_0_987), .ZN(n_1_0_986)); + SDFF_X1_LVT \registers_reg[1][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_1__ap[17]), .CK(n_0_0), .Q(registers_1__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[28][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_28__ap[17]), .CK(n_0_58), .Q(registers_28__ap[17]), .QN()); + AOI221_X1_LVT i_1_0_1035 (.A(n_1_0_986), .B1(n_1_0_1274), .B2( + registers_1__ap[17]), .C1(registers_28__ap[17]), .C2(n_1_0_1283), .ZN( + n_1_0_985)); + SDFF_X1_LVT \registers_reg[18][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_18__ap[17]), .CK(n_0_48), .Q(registers_18__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[30][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_30__ap[17]), .CK(n_0_60), .Q(registers_30__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1034 (.A1(registers_18__ap[17]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[17]), .ZN(n_1_0_984)); + SDFF_X1_LVT \registers_reg[4][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_4__ap[17]), .CK(n_0_34), .Q(registers_4__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[5][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_5__ap[17]), .CK(n_0_35), .Q(registers_5__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1033 (.A1(registers_4__ap[17]), .A2(n_1_0_1278), .B1( + n_1_0_1273), .B2(registers_5__ap[17]), .ZN(n_1_0_983)); + SDFF_X1_LVT \registers_reg[6][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_6__ap[17]), .CK(n_0_36), .Q(registers_6__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[25][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_25__ap[17]), .CK(n_0_55), .Q(registers_25__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1032 (.A1(registers_6__ap[17]), .A2(n_1_0_1300), .B1( + n_1_0_1269), .B2(registers_25__ap[17]), .ZN(n_1_0_982)); + NAND3_X1_LVT i_1_0_1031 (.A1(n_1_0_984), .A2(n_1_0_983), .A3(n_1_0_982), + .ZN(n_1_0_981)); + SDFF_X1_LVT \registers_reg[19][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_19__ap[17]), .CK(n_0_49), .Q(registers_19__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[16][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_16__ap[17]), .CK(n_0_46), .Q(registers_16__ap[17]), .QN()); + AOI221_X1_LVT i_1_0_1030 (.A(n_1_0_981), .B1(n_1_0_1295), .B2( + registers_19__ap[17]), .C1(registers_16__ap[17]), .C2(n_1_0_1267), + .ZN(n_1_0_980)); + SDFF_X1_LVT \registers_reg[7][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_7__ap[17]), .CK(n_0_37), .Q(registers_7__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[14][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_14__ap[17]), .CK(n_0_44), .Q(registers_14__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1029 (.A1(registers_7__ap[17]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[17]), .ZN(n_1_0_979)); + SDFF_X1_LVT \registers_reg[9][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_9__ap[17]), .CK(n_0_39), .Q(registers_9__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[29][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_29__ap[17]), .CK(n_0_59), .Q(registers_29__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1028 (.A1(registers_9__ap[17]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[17]), .ZN(n_1_0_978)); + SDFF_X1_LVT \registers_reg[8][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_8__ap[17]), .CK(n_0_38), .Q(registers_8__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[23][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_23__ap[17]), .CK(n_0_53), .Q(registers_23__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1027 (.A1(registers_8__ap[17]), .A2(n_1_0_1282), .B1( + n_1_0_1264), .B2(registers_23__ap[17]), .ZN(n_1_0_977)); + NAND3_X1_LVT i_1_0_1026 (.A1(n_1_0_979), .A2(n_1_0_978), .A3(n_1_0_977), + .ZN(n_1_0_976)); + SDFF_X1_LVT \registers_reg[27][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_27__ap[17]), .CK(n_0_57), .Q(registers_27__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[3][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_3__ap[17]), .CK(n_0_33), .Q(registers_3__ap[17]), .QN()); + AOI221_X1_LVT i_1_0_1025 (.A(n_1_0_976), .B1(n_1_0_1279), .B2( + registers_27__ap[17]), .C1(registers_3__ap[17]), .C2(n_1_0_1257), .ZN( + n_1_0_975)); + NAND4_X1_LVT i_1_0_1024 (.A1(n_1_0_990), .A2(n_1_0_985), .A3(n_1_0_980), + .A4(n_1_0_975), .ZN(RRs1[17])); + AND2_X1_LVT i_0_0_16 (.A1(n_0_0_16), .A2(WRd[16]), .ZN(registers[16])); + SDFF_X1_LVT \registers_reg[29][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_29__ap[16]), .CK(n_0_59), .Q(registers_29__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[2][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_2__ap[16]), .CK(n_0_32), .Q(registers_2__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1022 (.A1(registers_29__ap[16]), .A2(n_1_0_1276), .B1( + n_1_0_1268), .B2(registers_2__ap[16]), .ZN(n_1_0_973)); + SDFF_X1_LVT \registers_reg[11][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_11__ap[16]), .CK(n_0_41), .Q(registers_11__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[25][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_25__ap[16]), .CK(n_0_55), .Q(registers_25__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1023 (.A1(registers_11__ap[16]), .A2(n_1_0_1270), .B1( + n_1_0_1269), .B2(registers_25__ap[16]), .ZN(n_1_0_974)); + SDFF_X1_LVT \registers_reg[9][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_9__ap[16]), .CK(n_0_39), .Q(registers_9__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[7][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_7__ap[16]), .CK(n_0_37), .Q(registers_7__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1021 (.A1(registers_9__ap[16]), .A2(n_1_0_1291), .B1( + n_1_0_1263), .B2(registers_7__ap[16]), .ZN(n_1_0_972)); + SDFF_X1_LVT \registers_reg[10][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_10__ap[16]), .CK(n_0_40), .Q(registers_10__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[16][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_16__ap[16]), .CK(n_0_46), .Q(registers_16__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1020 (.A1(registers_10__ap[16]), .A2(n_1_0_1287), .B1( + n_1_0_1267), .B2(registers_16__ap[16]), .ZN(n_1_0_971)); + NAND3_X1_LVT i_1_0_1019 (.A1(n_1_0_974), .A2(n_1_0_972), .A3(n_1_0_971), + .ZN(n_1_0_970)); + SDFF_X1_LVT \registers_reg[31][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_31__ap[16]), .CK(n_0_61), .Q(registers_31__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[6][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_6__ap[16]), .CK(n_0_36), .Q(registers_6__ap[16]), .QN()); + AOI221_X1_LVT i_1_0_1018 (.A(n_1_0_970), .B1(n_1_0_1266), .B2( + registers_31__ap[16]), .C1(registers_6__ap[16]), .C2(n_1_0_1300), .ZN( + n_1_0_969)); + SDFF_X1_LVT \registers_reg[18][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_18__ap[16]), .CK(n_0_48), .Q(registers_18__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[22][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_22__ap[16]), .CK(n_0_52), .Q(registers_22__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[1][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_1__ap[16]), .CK(n_0_0), .Q(registers_1__ap[16]), .QN()); + AOI222_X1_LVT i_1_0_1017 (.A1(registers_18__ap[16]), .A2(n_1_0_1297), + .B1(n_1_0_1294), .B2(registers_22__ap[16]), .C1(registers_1__ap[16]), + .C2(n_1_0_1274), .ZN(n_1_0_968)); + NAND3_X1_LVT i_1_0_1016 (.A1(n_1_0_973), .A2(n_1_0_969), .A3(n_1_0_968), + .ZN(n_1_0_967)); + SDFF_X1_LVT \registers_reg[5][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_5__ap[16]), .CK(n_0_35), .Q(registers_5__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[28][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_28__ap[16]), .CK(n_0_58), .Q(registers_28__ap[16]), .QN()); + AOI221_X1_LVT i_1_0_1015 (.A(n_1_0_967), .B1(n_1_0_1273), .B2( + registers_5__ap[16]), .C1(registers_28__ap[16]), .C2(n_1_0_1283), .ZN( + n_1_0_966)); + SDFF_X1_LVT \registers_reg[4][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_4__ap[16]), .CK(n_0_34), .Q(registers_4__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[12][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_12__ap[16]), .CK(n_0_42), .Q(registers_12__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1014 (.A1(registers_4__ap[16]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[16]), .ZN(n_1_0_965)); + SDFF_X1_LVT \registers_reg[19][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_19__ap[16]), .CK(n_0_49), .Q(registers_19__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[21][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_21__ap[16]), .CK(n_0_51), .Q(registers_21__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1013 (.A1(registers_19__ap[16]), .A2(n_1_0_1295), .B1( + n_1_0_1259), .B2(registers_21__ap[16]), .ZN(n_1_0_964)); + SDFF_X1_LVT \registers_reg[24][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_24__ap[16]), .CK(n_0_54), .Q(registers_24__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[20][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_20__ap[16]), .CK(n_0_50), .Q(registers_20__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1012 (.A1(registers_24__ap[16]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[16]), .ZN(n_1_0_963)); + NAND3_X1_LVT i_1_0_1011 (.A1(n_1_0_965), .A2(n_1_0_964), .A3(n_1_0_963), + .ZN(n_1_0_962)); + SDFF_X1_LVT \registers_reg[26][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_26__ap[16]), .CK(n_0_56), .Q(registers_26__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[30][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_30__ap[16]), .CK(n_0_60), .Q(registers_30__ap[16]), .QN()); + AOI221_X1_LVT i_1_0_1010 (.A(n_1_0_962), .B1(n_1_0_1285), .B2( + registers_26__ap[16]), .C1(registers_30__ap[16]), .C2(n_1_0_1272), + .ZN(n_1_0_961)); + SDFF_X1_LVT \registers_reg[8][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_8__ap[16]), .CK(n_0_38), .Q(registers_8__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[23][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_23__ap[16]), .CK(n_0_53), .Q(registers_23__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1009 (.A1(registers_8__ap[16]), .A2(n_1_0_1282), .B1( + n_1_0_1264), .B2(registers_23__ap[16]), .ZN(n_1_0_960)); + SDFF_X1_LVT \registers_reg[13][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_13__ap[16]), .CK(n_0_43), .Q(registers_13__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[17][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_17__ap[16]), .CK(n_0_47), .Q(registers_17__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1008 (.A1(registers_13__ap[16]), .A2(n_1_0_1277), .B1( + n_1_0_1271), .B2(registers_17__ap[16]), .ZN(n_1_0_959)); + SDFF_X1_LVT \registers_reg[15][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_15__ap[16]), .CK(n_0_45), .Q(registers_15__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[14][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_14__ap[16]), .CK(n_0_44), .Q(registers_14__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1007 (.A1(registers_15__ap[16]), .A2(n_1_0_1286), .B1( + n_1_0_1258), .B2(registers_14__ap[16]), .ZN(n_1_0_958)); + NAND3_X1_LVT i_1_0_1006 (.A1(n_1_0_960), .A2(n_1_0_959), .A3(n_1_0_958), + .ZN(n_1_0_957)); + SDFF_X1_LVT \registers_reg[27][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_27__ap[16]), .CK(n_0_57), .Q(registers_27__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[3][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_3__ap[16]), .CK(n_0_33), .Q(registers_3__ap[16]), .QN()); + AOI221_X1_LVT i_1_0_1005 (.A(n_1_0_957), .B1(n_1_0_1279), .B2( + registers_27__ap[16]), .C1(registers_3__ap[16]), .C2(n_1_0_1257), .ZN( + n_1_0_956)); + NAND3_X1_LVT i_1_0_1004 (.A1(n_1_0_966), .A2(n_1_0_961), .A3(n_1_0_956), + .ZN(RRs1[16])); + AND2_X1_LVT i_0_0_15 (.A1(n_0_0_16), .A2(WRd[15]), .ZN(registers[15])); + SDFF_X1_LVT \registers_reg[17][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_17__ap[15]), .CK(n_0_47), .Q(registers_17__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[21][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_21__ap[15]), .CK(n_0_51), .Q(registers_21__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_1000 (.A1(registers_17__ap[15]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[15]), .ZN(n_1_0_952)); + SDFF_X1_LVT \registers_reg[10][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_10__ap[15]), .CK(n_0_40), .Q(registers_10__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[2][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_2__ap[15]), .CK(n_0_32), .Q(registers_2__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_1003 (.A1(registers_10__ap[15]), .A2(n_1_0_1287), .B1( + n_1_0_1268), .B2(registers_2__ap[15]), .ZN(n_1_0_955)); + SDFF_X1_LVT \registers_reg[20][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_20__ap[15]), .CK(n_0_50), .Q(registers_20__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[12][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_12__ap[15]), .CK(n_0_42), .Q(registers_12__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_999 (.A1(registers_20__ap[15]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[15]), .ZN(n_1_0_951)); + SDFF_X1_LVT \registers_reg[15][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_15__ap[15]), .CK(n_0_45), .Q(registers_15__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[8][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_8__ap[15]), .CK(n_0_38), .Q(registers_8__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_1002 (.A1(registers_15__ap[15]), .A2(n_1_0_1286), .B1( + n_1_0_1282), .B2(registers_8__ap[15]), .ZN(n_1_0_954)); + INV_X1_LVT i_1_0_1001 (.A(n_1_0_954), .ZN(n_1_0_953)); + SDFF_X1_LVT \registers_reg[11][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_11__ap[15]), .CK(n_0_41), .Q(registers_11__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[24][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_24__ap[15]), .CK(n_0_54), .Q(registers_24__ap[15]), .QN()); + AOI221_X1_LVT i_1_0_998 (.A(n_1_0_953), .B1(n_1_0_1270), .B2( + registers_11__ap[15]), .C1(registers_24__ap[15]), .C2(n_1_0_1289), + .ZN(n_1_0_950)); + SDFF_X1_LVT \registers_reg[13][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_13__ap[15]), .CK(n_0_43), .Q(registers_13__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[30][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_30__ap[15]), .CK(n_0_60), .Q(registers_30__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[22][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_22__ap[15]), .CK(n_0_52), .Q(registers_22__ap[15]), .QN()); + AOI222_X1_LVT i_1_0_997 (.A1(registers_13__ap[15]), .A2(n_1_0_1277), .B1( + n_1_0_1272), .B2(registers_30__ap[15]), .C1(registers_22__ap[15]), + .C2(n_1_0_1294), .ZN(n_1_0_949)); + NAND4_X1_LVT i_1_0_996 (.A1(n_1_0_955), .A2(n_1_0_951), .A3(n_1_0_950), + .A4(n_1_0_949), .ZN(n_1_0_948)); + SDFF_X1_LVT \registers_reg[1][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_1__ap[15]), .CK(n_0_0), .Q(registers_1__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[28][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_28__ap[15]), .CK(n_0_58), .Q(registers_28__ap[15]), .QN()); + AOI221_X1_LVT i_1_0_995 (.A(n_1_0_948), .B1(n_1_0_1274), .B2( + registers_1__ap[15]), .C1(registers_28__ap[15]), .C2(n_1_0_1283), .ZN( + n_1_0_947)); + SDFF_X1_LVT \registers_reg[18][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_18__ap[15]), .CK(n_0_48), .Q(registers_18__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[26][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_26__ap[15]), .CK(n_0_56), .Q(registers_26__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_994 (.A1(registers_18__ap[15]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[15]), .ZN(n_1_0_946)); + SDFF_X1_LVT \registers_reg[4][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_4__ap[15]), .CK(n_0_34), .Q(registers_4__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[5][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_5__ap[15]), .CK(n_0_35), .Q(registers_5__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_993 (.A1(registers_4__ap[15]), .A2(n_1_0_1278), .B1( + n_1_0_1273), .B2(registers_5__ap[15]), .ZN(n_1_0_945)); + SDFF_X1_LVT \registers_reg[6][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_6__ap[15]), .CK(n_0_36), .Q(registers_6__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[16][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_16__ap[15]), .CK(n_0_46), .Q(registers_16__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_992 (.A1(registers_6__ap[15]), .A2(n_1_0_1300), .B1( + n_1_0_1267), .B2(registers_16__ap[15]), .ZN(n_1_0_944)); + NAND3_X1_LVT i_1_0_991 (.A1(n_1_0_946), .A2(n_1_0_945), .A3(n_1_0_944), + .ZN(n_1_0_943)); + SDFF_X1_LVT \registers_reg[19][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_19__ap[15]), .CK(n_0_49), .Q(registers_19__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[25][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_25__ap[15]), .CK(n_0_55), .Q(registers_25__ap[15]), .QN()); + AOI221_X1_LVT i_1_0_990 (.A(n_1_0_943), .B1(n_1_0_1295), .B2( + registers_19__ap[15]), .C1(registers_25__ap[15]), .C2(n_1_0_1269), + .ZN(n_1_0_942)); + SDFF_X1_LVT \registers_reg[7][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_7__ap[15]), .CK(n_0_37), .Q(registers_7__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[14][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_14__ap[15]), .CK(n_0_44), .Q(registers_14__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_989 (.A1(registers_7__ap[15]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[15]), .ZN(n_1_0_941)); + SDFF_X1_LVT \registers_reg[9][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_9__ap[15]), .CK(n_0_39), .Q(registers_9__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[29][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_29__ap[15]), .CK(n_0_59), .Q(registers_29__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_988 (.A1(registers_9__ap[15]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[15]), .ZN(n_1_0_940)); + SDFF_X1_LVT \registers_reg[23][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_23__ap[15]), .CK(n_0_53), .Q(registers_23__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[3][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_3__ap[15]), .CK(n_0_33), .Q(registers_3__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_987 (.A1(registers_23__ap[15]), .A2(n_1_0_1264), .B1( + n_1_0_1257), .B2(registers_3__ap[15]), .ZN(n_1_0_939)); + NAND3_X1_LVT i_1_0_986 (.A1(n_1_0_941), .A2(n_1_0_940), .A3(n_1_0_939), + .ZN(n_1_0_938)); + SDFF_X1_LVT \registers_reg[27][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_27__ap[15]), .CK(n_0_57), .Q(registers_27__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[31][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_31__ap[15]), .CK(n_0_61), .Q(registers_31__ap[15]), .QN()); + AOI221_X1_LVT i_1_0_985 (.A(n_1_0_938), .B1(n_1_0_1279), .B2( + registers_27__ap[15]), .C1(registers_31__ap[15]), .C2(n_1_0_1266), + .ZN(n_1_0_937)); + NAND4_X1_LVT i_1_0_984 (.A1(n_1_0_952), .A2(n_1_0_947), .A3(n_1_0_942), + .A4(n_1_0_937), .ZN(RRs1[15])); + AND2_X1_LVT i_0_0_14 (.A1(n_0_0_16), .A2(WRd[14]), .ZN(registers[14])); + SDFF_X1_LVT \registers_reg[28][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_28__ap[14]), .CK(n_0_58), .Q(registers_28__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[5][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_5__ap[14]), .CK(n_0_35), .Q(registers_5__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_983 (.A1(registers_28__ap[14]), .A2(n_1_0_1283), .B1( + n_1_0_1273), .B2(registers_5__ap[14]), .ZN(n_1_0_936)); + SDFF_X1_LVT \registers_reg[18][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_18__ap[14]), .CK(n_0_48), .Q(registers_18__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[10][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_10__ap[14]), .CK(n_0_40), .Q(registers_10__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[8][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_8__ap[14]), .CK(n_0_38), .Q(registers_8__ap[14]), .QN()); + AOI222_X1_LVT i_1_0_982 (.A1(registers_18__ap[14]), .A2(n_1_0_1297), .B1( + n_1_0_1287), .B2(registers_10__ap[14]), .C1(n_1_0_1282), .C2( + registers_8__ap[14]), .ZN(n_1_0_935)); + SDFF_X1_LVT \registers_reg[9][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_9__ap[14]), .CK(n_0_39), .Q(registers_9__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[29][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_29__ap[14]), .CK(n_0_59), .Q(registers_29__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_981 (.A1(registers_9__ap[14]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[14]), .ZN(n_1_0_934)); + SDFF_X1_LVT \registers_reg[21][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_21__ap[14]), .CK(n_0_51), .Q(registers_21__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[14][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_14__ap[14]), .CK(n_0_44), .Q(registers_14__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_980 (.A1(registers_21__ap[14]), .A2(n_1_0_1259), .B1( + n_1_0_1258), .B2(registers_14__ap[14]), .ZN(n_1_0_933)); + SDFF_X1_LVT \registers_reg[16][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_16__ap[14]), .CK(n_0_46), .Q(registers_16__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[3][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_3__ap[14]), .CK(n_0_33), .Q(registers_3__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_979 (.A1(registers_16__ap[14]), .A2(n_1_0_1267), .B1( + n_1_0_1257), .B2(registers_3__ap[14]), .ZN(n_1_0_932)); + SDFF_X1_LVT \registers_reg[17][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_17__ap[14]), .CK(n_0_47), .Q(registers_17__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[31][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_31__ap[14]), .CK(n_0_61), .Q(registers_31__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_978 (.A1(registers_17__ap[14]), .A2(n_1_0_1271), .B1( + n_1_0_1266), .B2(registers_31__ap[14]), .ZN(n_1_0_931)); + SDFF_X1_LVT \registers_reg[15][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_15__ap[14]), .CK(n_0_45), .Q(registers_15__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[23][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_23__ap[14]), .CK(n_0_53), .Q(registers_23__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_977 (.A1(registers_15__ap[14]), .A2(n_1_0_1286), .B1( + n_1_0_1264), .B2(registers_23__ap[14]), .ZN(n_1_0_930)); + NAND4_X1_LVT i_1_0_976 (.A1(n_1_0_933), .A2(n_1_0_932), .A3(n_1_0_931), + .A4(n_1_0_930), .ZN(n_1_0_929)); + SDFF_X1_LVT \registers_reg[26][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_26__ap[14]), .CK(n_0_56), .Q(registers_26__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[30][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_30__ap[14]), .CK(n_0_60), .Q(registers_30__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_975 (.A1(registers_26__ap[14]), .A2(n_1_0_1285), .B1( + n_1_0_1272), .B2(registers_30__ap[14]), .ZN(n_1_0_928)); + SDFF_X1_LVT \registers_reg[20][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_20__ap[14]), .CK(n_0_50), .Q(registers_20__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[4][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_4__ap[14]), .CK(n_0_34), .Q(registers_4__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_974 (.A1(registers_20__ap[14]), .A2(n_1_0_1281), .B1( + n_1_0_1278), .B2(registers_4__ap[14]), .ZN(n_1_0_927)); + SDFF_X1_LVT \registers_reg[1][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_1__ap[14]), .CK(n_0_0), .Q(registers_1__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[2][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_2__ap[14]), .CK(n_0_32), .Q(registers_2__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_973 (.A1(registers_1__ap[14]), .A2(n_1_0_1274), .B1( + n_1_0_1268), .B2(registers_2__ap[14]), .ZN(n_1_0_926)); + SDFF_X1_LVT \registers_reg[24][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_24__ap[14]), .CK(n_0_54), .Q(registers_24__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[12][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_12__ap[14]), .CK(n_0_42), .Q(registers_12__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_972 (.A1(registers_24__ap[14]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[14]), .ZN(n_1_0_925)); + NAND4_X1_LVT i_1_0_971 (.A1(n_1_0_928), .A2(n_1_0_927), .A3(n_1_0_926), + .A4(n_1_0_925), .ZN(n_1_0_924)); + SDFF_X1_LVT \registers_reg[19][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_19__ap[14]), .CK(n_0_49), .Q(registers_19__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[22][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_22__ap[14]), .CK(n_0_52), .Q(registers_22__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_970 (.A1(registers_19__ap[14]), .A2(n_1_0_1295), .B1( + n_1_0_1294), .B2(registers_22__ap[14]), .ZN(n_1_0_923)); + SDFF_X1_LVT \registers_reg[13][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_13__ap[14]), .CK(n_0_43), .Q(registers_13__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[25][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_25__ap[14]), .CK(n_0_55), .Q(registers_25__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_969 (.A1(registers_13__ap[14]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[14]), .ZN(n_1_0_922)); + SDFF_X1_LVT \registers_reg[6][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_6__ap[14]), .CK(n_0_36), .Q(registers_6__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[7][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_7__ap[14]), .CK(n_0_37), .Q(registers_7__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_968 (.A1(registers_6__ap[14]), .A2(n_1_0_1300), .B1( + n_1_0_1263), .B2(registers_7__ap[14]), .ZN(n_1_0_921)); + SDFF_X1_LVT \registers_reg[27][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_27__ap[14]), .CK(n_0_57), .Q(registers_27__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[11][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_11__ap[14]), .CK(n_0_41), .Q(registers_11__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_967 (.A1(registers_27__ap[14]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[14]), .ZN(n_1_0_920)); + NAND4_X1_LVT i_1_0_966 (.A1(n_1_0_923), .A2(n_1_0_922), .A3(n_1_0_921), + .A4(n_1_0_920), .ZN(n_1_0_919)); + NOR3_X1_LVT i_1_0_965 (.A1(n_1_0_929), .A2(n_1_0_924), .A3(n_1_0_919), + .ZN(n_1_0_918)); + NAND4_X1_LVT i_1_0_964 (.A1(n_1_0_936), .A2(n_1_0_935), .A3(n_1_0_934), + .A4(n_1_0_918), .ZN(RRs1[14])); + AND2_X1_LVT i_0_0_13 (.A1(n_0_0_16), .A2(WRd[13]), .ZN(registers[13])); + SDFF_X1_LVT \registers_reg[28][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_28__ap[13]), .CK(n_0_58), .Q(registers_28__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[4][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_4__ap[13]), .CK(n_0_34), .Q(registers_4__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_963 (.A1(registers_28__ap[13]), .A2(n_1_0_1283), .B1( + n_1_0_1278), .B2(registers_4__ap[13]), .ZN(n_1_0_917)); + SDFF_X1_LVT \registers_reg[10][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_10__ap[13]), .CK(n_0_40), .Q(registers_10__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[26][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_26__ap[13]), .CK(n_0_56), .Q(registers_26__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[8][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_8__ap[13]), .CK(n_0_38), .Q(registers_8__ap[13]), .QN()); + AOI222_X1_LVT i_1_0_962 (.A1(registers_10__ap[13]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[13]), .C1(registers_8__ap[13]), .C2( + n_1_0_1282), .ZN(n_1_0_916)); + SDFF_X1_LVT \registers_reg[9][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_9__ap[13]), .CK(n_0_39), .Q(registers_9__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[29][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_29__ap[13]), .CK(n_0_59), .Q(registers_29__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_961 (.A1(registers_9__ap[13]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[13]), .ZN(n_1_0_915)); + SDFF_X1_LVT \registers_reg[6][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_6__ap[13]), .CK(n_0_36), .Q(registers_6__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[1][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_1__ap[13]), .CK(n_0_0), .Q(registers_1__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_960 (.A1(registers_6__ap[13]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[13]), .ZN(n_1_0_914)); + SDFF_X1_LVT \registers_reg[5][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_5__ap[13]), .CK(n_0_35), .Q(registers_5__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[3][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_3__ap[13]), .CK(n_0_33), .Q(registers_3__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_959 (.A1(registers_5__ap[13]), .A2(n_1_0_1273), .B1( + n_1_0_1257), .B2(registers_3__ap[13]), .ZN(n_1_0_913)); + SDFF_X1_LVT \registers_reg[16][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_16__ap[13]), .CK(n_0_46), .Q(registers_16__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[31][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_31__ap[13]), .CK(n_0_61), .Q(registers_31__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_958 (.A1(registers_16__ap[13]), .A2(n_1_0_1267), .B1( + n_1_0_1266), .B2(registers_31__ap[13]), .ZN(n_1_0_912)); + SDFF_X1_LVT \registers_reg[15][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_15__ap[13]), .CK(n_0_45), .Q(registers_15__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[23][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_23__ap[13]), .CK(n_0_53), .Q(registers_23__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_957 (.A1(registers_15__ap[13]), .A2(n_1_0_1286), .B1( + n_1_0_1264), .B2(registers_23__ap[13]), .ZN(n_1_0_911)); + NAND4_X1_LVT i_1_0_956 (.A1(n_1_0_914), .A2(n_1_0_913), .A3(n_1_0_912), + .A4(n_1_0_911), .ZN(n_1_0_910)); + SDFF_X1_LVT \registers_reg[18][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_18__ap[13]), .CK(n_0_48), .Q(registers_18__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[30][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_30__ap[13]), .CK(n_0_60), .Q(registers_30__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_955 (.A1(registers_18__ap[13]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[13]), .ZN(n_1_0_909)); + SDFF_X1_LVT \registers_reg[24][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_24__ap[13]), .CK(n_0_54), .Q(registers_24__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[12][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_12__ap[13]), .CK(n_0_42), .Q(registers_12__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_954 (.A1(registers_24__ap[13]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[13]), .ZN(n_1_0_908)); + SDFF_X1_LVT \registers_reg[22][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_22__ap[13]), .CK(n_0_52), .Q(registers_22__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[21][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_21__ap[13]), .CK(n_0_51), .Q(registers_21__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_953 (.A1(registers_22__ap[13]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[13]), .ZN(n_1_0_907)); + SDFF_X1_LVT \registers_reg[20][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_20__ap[13]), .CK(n_0_50), .Q(registers_20__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[17][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_17__ap[13]), .CK(n_0_47), .Q(registers_17__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_952 (.A1(registers_20__ap[13]), .A2(n_1_0_1281), .B1( + n_1_0_1271), .B2(registers_17__ap[13]), .ZN(n_1_0_906)); + NAND4_X1_LVT i_1_0_951 (.A1(n_1_0_909), .A2(n_1_0_908), .A3(n_1_0_907), + .A4(n_1_0_906), .ZN(n_1_0_905)); + SDFF_X1_LVT \registers_reg[13][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_13__ap[13]), .CK(n_0_43), .Q(registers_13__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[25][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_25__ap[13]), .CK(n_0_55), .Q(registers_25__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_950 (.A1(registers_13__ap[13]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[13]), .ZN(n_1_0_904)); + SDFF_X1_LVT \registers_reg[19][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_19__ap[13]), .CK(n_0_49), .Q(registers_19__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[2][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_2__ap[13]), .CK(n_0_32), .Q(registers_2__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_949 (.A1(registers_19__ap[13]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[13]), .ZN(n_1_0_903)); + SDFF_X1_LVT \registers_reg[7][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_7__ap[13]), .CK(n_0_37), .Q(registers_7__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[14][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_14__ap[13]), .CK(n_0_44), .Q(registers_14__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_948 (.A1(registers_7__ap[13]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[13]), .ZN(n_1_0_902)); + SDFF_X1_LVT \registers_reg[27][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_27__ap[13]), .CK(n_0_57), .Q(registers_27__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[11][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_11__ap[13]), .CK(n_0_41), .Q(registers_11__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_947 (.A1(registers_27__ap[13]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[13]), .ZN(n_1_0_901)); + NAND4_X1_LVT i_1_0_946 (.A1(n_1_0_904), .A2(n_1_0_903), .A3(n_1_0_902), + .A4(n_1_0_901), .ZN(n_1_0_900)); + NOR3_X1_LVT i_1_0_945 (.A1(n_1_0_910), .A2(n_1_0_905), .A3(n_1_0_900), + .ZN(n_1_0_899)); + NAND4_X1_LVT i_1_0_944 (.A1(n_1_0_917), .A2(n_1_0_916), .A3(n_1_0_915), + .A4(n_1_0_899), .ZN(RRs1[13])); + AND2_X1_LVT i_0_0_12 (.A1(n_0_0_16), .A2(WRd[12]), .ZN(registers[12])); + SDFF_X1_LVT \registers_reg[28][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_28__ap[12]), .CK(n_0_58), .Q(registers_28__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[17][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_17__ap[12]), .CK(n_0_47), .Q(registers_17__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_943 (.A1(registers_28__ap[12]), .A2(n_1_0_1283), .B1( + n_1_0_1271), .B2(registers_17__ap[12]), .ZN(n_1_0_898)); + SDFF_X1_LVT \registers_reg[10][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_10__ap[12]), .CK(n_0_40), .Q(registers_10__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[26][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_26__ap[12]), .CK(n_0_56), .Q(registers_26__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[8][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_8__ap[12]), .CK(n_0_38), .Q(registers_8__ap[12]), .QN()); + AOI222_X1_LVT i_1_0_942 (.A1(registers_10__ap[12]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[12]), .C1(registers_8__ap[12]), .C2( + n_1_0_1282), .ZN(n_1_0_897)); + SDFF_X1_LVT \registers_reg[9][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_9__ap[12]), .CK(n_0_39), .Q(registers_9__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[29][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_29__ap[12]), .CK(n_0_59), .Q(registers_29__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_941 (.A1(registers_9__ap[12]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[12]), .ZN(n_1_0_896)); + SDFF_X1_LVT \registers_reg[6][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_6__ap[12]), .CK(n_0_36), .Q(registers_6__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[1][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_1__ap[12]), .CK(n_0_0), .Q(registers_1__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_940 (.A1(registers_6__ap[12]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[12]), .ZN(n_1_0_895)); + SDFF_X1_LVT \registers_reg[16][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_16__ap[12]), .CK(n_0_46), .Q(registers_16__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[3][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_3__ap[12]), .CK(n_0_33), .Q(registers_3__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_939 (.A1(registers_16__ap[12]), .A2(n_1_0_1267), .B1( + n_1_0_1257), .B2(registers_3__ap[12]), .ZN(n_1_0_894)); + SDFF_X1_LVT \registers_reg[5][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_5__ap[12]), .CK(n_0_35), .Q(registers_5__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[31][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_31__ap[12]), .CK(n_0_61), .Q(registers_31__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_938 (.A1(registers_5__ap[12]), .A2(n_1_0_1273), .B1( + n_1_0_1266), .B2(registers_31__ap[12]), .ZN(n_1_0_893)); + SDFF_X1_LVT \registers_reg[15][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_15__ap[12]), .CK(n_0_45), .Q(registers_15__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[23][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_23__ap[12]), .CK(n_0_53), .Q(registers_23__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_937 (.A1(registers_15__ap[12]), .A2(n_1_0_1286), .B1( + n_1_0_1264), .B2(registers_23__ap[12]), .ZN(n_1_0_892)); + NAND4_X1_LVT i_1_0_936 (.A1(n_1_0_895), .A2(n_1_0_894), .A3(n_1_0_893), + .A4(n_1_0_892), .ZN(n_1_0_891)); + SDFF_X1_LVT \registers_reg[18][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_18__ap[12]), .CK(n_0_48), .Q(registers_18__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[30][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_30__ap[12]), .CK(n_0_60), .Q(registers_30__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_935 (.A1(registers_18__ap[12]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[12]), .ZN(n_1_0_890)); + SDFF_X1_LVT \registers_reg[20][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_20__ap[12]), .CK(n_0_50), .Q(registers_20__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[4][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_4__ap[12]), .CK(n_0_34), .Q(registers_4__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_934 (.A1(registers_20__ap[12]), .A2(n_1_0_1281), .B1( + n_1_0_1278), .B2(registers_4__ap[12]), .ZN(n_1_0_889)); + SDFF_X1_LVT \registers_reg[22][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_22__ap[12]), .CK(n_0_52), .Q(registers_22__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[21][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_21__ap[12]), .CK(n_0_51), .Q(registers_21__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_933 (.A1(registers_22__ap[12]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[12]), .ZN(n_1_0_888)); + SDFF_X1_LVT \registers_reg[24][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_24__ap[12]), .CK(n_0_54), .Q(registers_24__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[12][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_12__ap[12]), .CK(n_0_42), .Q(registers_12__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_932 (.A1(registers_24__ap[12]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[12]), .ZN(n_1_0_887)); + NAND4_X1_LVT i_1_0_931 (.A1(n_1_0_890), .A2(n_1_0_889), .A3(n_1_0_888), + .A4(n_1_0_887), .ZN(n_1_0_886)); + SDFF_X1_LVT \registers_reg[13][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_13__ap[12]), .CK(n_0_43), .Q(registers_13__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[25][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_25__ap[12]), .CK(n_0_55), .Q(registers_25__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_930 (.A1(registers_13__ap[12]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[12]), .ZN(n_1_0_885)); + SDFF_X1_LVT \registers_reg[19][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_19__ap[12]), .CK(n_0_49), .Q(registers_19__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[2][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_2__ap[12]), .CK(n_0_32), .Q(registers_2__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_929 (.A1(registers_19__ap[12]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[12]), .ZN(n_1_0_884)); + SDFF_X1_LVT \registers_reg[7][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_7__ap[12]), .CK(n_0_37), .Q(registers_7__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[14][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_14__ap[12]), .CK(n_0_44), .Q(registers_14__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_928 (.A1(registers_7__ap[12]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[12]), .ZN(n_1_0_883)); + SDFF_X1_LVT \registers_reg[27][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_27__ap[12]), .CK(n_0_57), .Q(registers_27__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[11][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_11__ap[12]), .CK(n_0_41), .Q(registers_11__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_927 (.A1(registers_27__ap[12]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[12]), .ZN(n_1_0_882)); + NAND4_X1_LVT i_1_0_926 (.A1(n_1_0_885), .A2(n_1_0_884), .A3(n_1_0_883), + .A4(n_1_0_882), .ZN(n_1_0_881)); + NOR3_X1_LVT i_1_0_925 (.A1(n_1_0_891), .A2(n_1_0_886), .A3(n_1_0_881), + .ZN(n_1_0_880)); + NAND4_X1_LVT i_1_0_924 (.A1(n_1_0_898), .A2(n_1_0_897), .A3(n_1_0_896), + .A4(n_1_0_880), .ZN(RRs1[12])); + AND2_X1_LVT i_0_0_11 (.A1(n_0_0_16), .A2(WRd[11]), .ZN(registers[11])); + SDFF_X1_LVT \registers_reg[28][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_28__ap[11]), .CK(n_0_58), .Q(registers_28__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[17][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_17__ap[11]), .CK(n_0_47), .Q(registers_17__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_923 (.A1(registers_28__ap[11]), .A2(n_1_0_1283), .B1( + n_1_0_1271), .B2(registers_17__ap[11]), .ZN(n_1_0_879)); + SDFF_X1_LVT \registers_reg[10][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_10__ap[11]), .CK(n_0_40), .Q(registers_10__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[26][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_26__ap[11]), .CK(n_0_56), .Q(registers_26__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[8][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_8__ap[11]), .CK(n_0_38), .Q(registers_8__ap[11]), .QN()); + AOI222_X1_LVT i_1_0_922 (.A1(registers_10__ap[11]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[11]), .C1(registers_8__ap[11]), .C2( + n_1_0_1282), .ZN(n_1_0_878)); + SDFF_X1_LVT \registers_reg[9][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_9__ap[11]), .CK(n_0_39), .Q(registers_9__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[29][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_29__ap[11]), .CK(n_0_59), .Q(registers_29__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_921 (.A1(registers_9__ap[11]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[11]), .ZN(n_1_0_877)); + SDFF_X1_LVT \registers_reg[6][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_6__ap[11]), .CK(n_0_36), .Q(registers_6__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[1][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_1__ap[11]), .CK(n_0_0), .Q(registers_1__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_920 (.A1(registers_6__ap[11]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[11]), .ZN(n_1_0_876)); + SDFF_X1_LVT \registers_reg[5][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_5__ap[11]), .CK(n_0_35), .Q(registers_5__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[3][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_3__ap[11]), .CK(n_0_33), .Q(registers_3__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_919 (.A1(registers_5__ap[11]), .A2(n_1_0_1273), .B1( + n_1_0_1257), .B2(registers_3__ap[11]), .ZN(n_1_0_875)); + SDFF_X1_LVT \registers_reg[16][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_16__ap[11]), .CK(n_0_46), .Q(registers_16__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[31][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_31__ap[11]), .CK(n_0_61), .Q(registers_31__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_918 (.A1(registers_16__ap[11]), .A2(n_1_0_1267), .B1( + n_1_0_1266), .B2(registers_31__ap[11]), .ZN(n_1_0_874)); + SDFF_X1_LVT \registers_reg[15][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_15__ap[11]), .CK(n_0_45), .Q(registers_15__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[23][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_23__ap[11]), .CK(n_0_53), .Q(registers_23__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_917 (.A1(registers_15__ap[11]), .A2(n_1_0_1286), .B1( + n_1_0_1264), .B2(registers_23__ap[11]), .ZN(n_1_0_873)); + NAND4_X1_LVT i_1_0_916 (.A1(n_1_0_876), .A2(n_1_0_875), .A3(n_1_0_874), + .A4(n_1_0_873), .ZN(n_1_0_872)); + SDFF_X1_LVT \registers_reg[18][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_18__ap[11]), .CK(n_0_48), .Q(registers_18__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[30][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_30__ap[11]), .CK(n_0_60), .Q(registers_30__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_915 (.A1(registers_18__ap[11]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[11]), .ZN(n_1_0_871)); + SDFF_X1_LVT \registers_reg[20][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_20__ap[11]), .CK(n_0_50), .Q(registers_20__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[4][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_4__ap[11]), .CK(n_0_34), .Q(registers_4__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_914 (.A1(registers_20__ap[11]), .A2(n_1_0_1281), .B1( + n_1_0_1278), .B2(registers_4__ap[11]), .ZN(n_1_0_870)); + SDFF_X1_LVT \registers_reg[22][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_22__ap[11]), .CK(n_0_52), .Q(registers_22__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[21][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_21__ap[11]), .CK(n_0_51), .Q(registers_21__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_913 (.A1(registers_22__ap[11]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[11]), .ZN(n_1_0_869)); + SDFF_X1_LVT \registers_reg[24][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_24__ap[11]), .CK(n_0_54), .Q(registers_24__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[12][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_12__ap[11]), .CK(n_0_42), .Q(registers_12__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_912 (.A1(registers_24__ap[11]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[11]), .ZN(n_1_0_868)); + NAND4_X1_LVT i_1_0_911 (.A1(n_1_0_871), .A2(n_1_0_870), .A3(n_1_0_869), + .A4(n_1_0_868), .ZN(n_1_0_867)); + SDFF_X1_LVT \registers_reg[13][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_13__ap[11]), .CK(n_0_43), .Q(registers_13__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[25][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_25__ap[11]), .CK(n_0_55), .Q(registers_25__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_910 (.A1(registers_13__ap[11]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[11]), .ZN(n_1_0_866)); + SDFF_X1_LVT \registers_reg[19][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_19__ap[11]), .CK(n_0_49), .Q(registers_19__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[2][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_2__ap[11]), .CK(n_0_32), .Q(registers_2__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_909 (.A1(registers_19__ap[11]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[11]), .ZN(n_1_0_865)); + SDFF_X1_LVT \registers_reg[7][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_7__ap[11]), .CK(n_0_37), .Q(registers_7__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[14][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_14__ap[11]), .CK(n_0_44), .Q(registers_14__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_908 (.A1(registers_7__ap[11]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[11]), .ZN(n_1_0_864)); + SDFF_X1_LVT \registers_reg[27][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_27__ap[11]), .CK(n_0_57), .Q(registers_27__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[11][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_11__ap[11]), .CK(n_0_41), .Q(registers_11__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_907 (.A1(registers_27__ap[11]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[11]), .ZN(n_1_0_863)); + NAND4_X1_LVT i_1_0_906 (.A1(n_1_0_866), .A2(n_1_0_865), .A3(n_1_0_864), + .A4(n_1_0_863), .ZN(n_1_0_862)); + NOR3_X1_LVT i_1_0_905 (.A1(n_1_0_872), .A2(n_1_0_867), .A3(n_1_0_862), + .ZN(n_1_0_861)); + NAND4_X1_LVT i_1_0_904 (.A1(n_1_0_879), .A2(n_1_0_878), .A3(n_1_0_877), + .A4(n_1_0_861), .ZN(RRs1[11])); + AND2_X1_LVT i_0_0_10 (.A1(n_0_0_16), .A2(WRd[10]), .ZN(registers[10])); + SDFF_X1_LVT \registers_reg[28][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_28__ap[10]), .CK(n_0_58), .Q(registers_28__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[8][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_8__ap[10]), .CK(n_0_38), .Q(registers_8__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_902 (.A1(registers_28__ap[10]), .A2(n_1_0_1283), .B1( + n_1_0_1282), .B2(registers_8__ap[10]), .ZN(n_1_0_859)); + SDFF_X1_LVT \registers_reg[31][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_31__ap[10]), .CK(n_0_61), .Q(registers_31__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[7][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_7__ap[10]), .CK(n_0_37), .Q(registers_7__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_903 (.A1(registers_31__ap[10]), .A2(n_1_0_1266), .B1( + n_1_0_1263), .B2(registers_7__ap[10]), .ZN(n_1_0_860)); + SDFF_X1_LVT \registers_reg[24][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_24__ap[10]), .CK(n_0_54), .Q(registers_24__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[20][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_20__ap[10]), .CK(n_0_50), .Q(registers_20__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_901 (.A1(registers_24__ap[10]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[10]), .ZN(n_1_0_858)); + SDFF_X1_LVT \registers_reg[4][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_4__ap[10]), .CK(n_0_34), .Q(registers_4__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[23][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_23__ap[10]), .CK(n_0_53), .Q(registers_23__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_900 (.A1(registers_4__ap[10]), .A2(n_1_0_1278), .B1( + n_1_0_1264), .B2(registers_23__ap[10]), .ZN(n_1_0_857)); + NAND3_X1_LVT i_1_0_899 (.A1(n_1_0_860), .A2(n_1_0_858), .A3(n_1_0_857), + .ZN(n_1_0_856)); + SDFF_X1_LVT \registers_reg[27][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_27__ap[10]), .CK(n_0_57), .Q(registers_27__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[29][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_29__ap[10]), .CK(n_0_59), .Q(registers_29__ap[10]), .QN()); + AOI221_X1_LVT i_1_0_898 (.A(n_1_0_856), .B1(n_1_0_1279), .B2( + registers_27__ap[10]), .C1(registers_29__ap[10]), .C2(n_1_0_1276), + .ZN(n_1_0_855)); + SDFF_X1_LVT \registers_reg[10][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_10__ap[10]), .CK(n_0_40), .Q(registers_10__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[30][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_30__ap[10]), .CK(n_0_60), .Q(registers_30__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[25][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_25__ap[10]), .CK(n_0_55), .Q(registers_25__ap[10]), .QN()); + AOI222_X1_LVT i_1_0_897 (.A1(registers_10__ap[10]), .A2(n_1_0_1287), .B1( + n_1_0_1272), .B2(registers_30__ap[10]), .C1(n_1_0_1269), .C2( + registers_25__ap[10]), .ZN(n_1_0_854)); + NAND3_X1_LVT i_1_0_896 (.A1(n_1_0_859), .A2(n_1_0_855), .A3(n_1_0_854), + .ZN(n_1_0_853)); + SDFF_X1_LVT \registers_reg[21][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_21__ap[10]), .CK(n_0_51), .Q(registers_21__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[13][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_13__ap[10]), .CK(n_0_43), .Q(registers_13__ap[10]), .QN()); + AOI221_X1_LVT i_1_0_895 (.A(n_1_0_853), .B1(n_1_0_1259), .B2( + registers_21__ap[10]), .C1(registers_13__ap[10]), .C2(n_1_0_1277), + .ZN(n_1_0_852)); + SDFF_X1_LVT \registers_reg[18][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_18__ap[10]), .CK(n_0_48), .Q(registers_18__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[26][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_26__ap[10]), .CK(n_0_56), .Q(registers_26__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_894 (.A1(registers_18__ap[10]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[10]), .ZN(n_1_0_851)); + SDFF_X1_LVT \registers_reg[17][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_17__ap[10]), .CK(n_0_47), .Q(registers_17__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[12][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_12__ap[10]), .CK(n_0_42), .Q(registers_12__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_893 (.A1(registers_17__ap[10]), .A2(n_1_0_1271), .B1( + n_1_0_1260), .B2(registers_12__ap[10]), .ZN(n_1_0_850)); + SDFF_X1_LVT \registers_reg[15][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_15__ap[10]), .CK(n_0_45), .Q(registers_15__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[5][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_5__ap[10]), .CK(n_0_35), .Q(registers_5__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_892 (.A1(registers_15__ap[10]), .A2(n_1_0_1286), .B1( + n_1_0_1273), .B2(registers_5__ap[10]), .ZN(n_1_0_849)); + NAND3_X1_LVT i_1_0_891 (.A1(n_1_0_851), .A2(n_1_0_850), .A3(n_1_0_849), + .ZN(n_1_0_848)); + SDFF_X1_LVT \registers_reg[22][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_22__ap[10]), .CK(n_0_52), .Q(registers_22__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[16][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_16__ap[10]), .CK(n_0_46), .Q(registers_16__ap[10]), .QN()); + AOI221_X1_LVT i_1_0_890 (.A(n_1_0_848), .B1(n_1_0_1294), .B2( + registers_22__ap[10]), .C1(registers_16__ap[10]), .C2(n_1_0_1267), + .ZN(n_1_0_847)); + SDFF_X1_LVT \registers_reg[9][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_9__ap[10]), .CK(n_0_39), .Q(registers_9__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[1][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_1__ap[10]), .CK(n_0_0), .Q(registers_1__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_889 (.A1(registers_9__ap[10]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[10]), .ZN(n_1_0_846)); + SDFF_X1_LVT \registers_reg[6][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_6__ap[10]), .CK(n_0_36), .Q(registers_6__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[14][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_14__ap[10]), .CK(n_0_44), .Q(registers_14__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_888 (.A1(registers_6__ap[10]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[10]), .ZN(n_1_0_845)); + SDFF_X1_LVT \registers_reg[19][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_19__ap[10]), .CK(n_0_49), .Q(registers_19__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[3][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_3__ap[10]), .CK(n_0_33), .Q(registers_3__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_887 (.A1(registers_19__ap[10]), .A2(n_1_0_1295), .B1( + n_1_0_1257), .B2(registers_3__ap[10]), .ZN(n_1_0_844)); + NAND3_X1_LVT i_1_0_886 (.A1(n_1_0_846), .A2(n_1_0_845), .A3(n_1_0_844), + .ZN(n_1_0_843)); + SDFF_X1_LVT \registers_reg[11][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_11__ap[10]), .CK(n_0_41), .Q(registers_11__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[2][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_2__ap[10]), .CK(n_0_32), .Q(registers_2__ap[10]), .QN()); + AOI221_X1_LVT i_1_0_885 (.A(n_1_0_843), .B1(n_1_0_1270), .B2( + registers_11__ap[10]), .C1(registers_2__ap[10]), .C2(n_1_0_1268), .ZN( + n_1_0_842)); + NAND3_X1_LVT i_1_0_884 (.A1(n_1_0_852), .A2(n_1_0_847), .A3(n_1_0_842), + .ZN(RRs1[10])); + AND2_X1_LVT i_0_0_9 (.A1(n_0_0_16), .A2(WRd[9]), .ZN(registers[9])); + SDFF_X1_LVT \registers_reg[13][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_13__ap[9]), .CK(n_0_43), .Q(registers_13__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[21][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_21__ap[9]), .CK(n_0_51), .Q(registers_21__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_880 (.A1(registers_13__ap[9]), .A2(n_1_0_1277), .B1( + n_1_0_1259), .B2(registers_21__ap[9]), .ZN(n_1_0_838)); + SDFF_X1_LVT \registers_reg[29][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_29__ap[9]), .CK(n_0_59), .Q(registers_29__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[23][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_23__ap[9]), .CK(n_0_53), .Q(registers_23__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_883 (.A1(registers_29__ap[9]), .A2(n_1_0_1276), .B1( + n_1_0_1264), .B2(registers_23__ap[9]), .ZN(n_1_0_841)); + SDFF_X1_LVT \registers_reg[24][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_24__ap[9]), .CK(n_0_54), .Q(registers_24__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[20][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_20__ap[9]), .CK(n_0_50), .Q(registers_20__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_879 (.A1(registers_24__ap[9]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[9]), .ZN(n_1_0_837)); + SDFF_X1_LVT \registers_reg[7][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_7__ap[9]), .CK(n_0_37), .Q(registers_7__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[3][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_3__ap[9]), .CK(n_0_33), .Q(registers_3__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_882 (.A1(registers_7__ap[9]), .A2(n_1_0_1263), .B1( + n_1_0_1257), .B2(registers_3__ap[9]), .ZN(n_1_0_840)); + INV_X1_LVT i_1_0_881 (.A(n_1_0_840), .ZN(n_1_0_839)); + SDFF_X1_LVT \registers_reg[31][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_31__ap[9]), .CK(n_0_61), .Q(registers_31__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[4][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_4__ap[9]), .CK(n_0_34), .Q(registers_4__ap[9]), .QN()); + AOI221_X1_LVT i_1_0_878 (.A(n_1_0_839), .B1(n_1_0_1266), .B2( + registers_31__ap[9]), .C1(registers_4__ap[9]), .C2(n_1_0_1278), .ZN( + n_1_0_836)); + SDFF_X1_LVT \registers_reg[10][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_10__ap[9]), .CK(n_0_40), .Q(registers_10__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[26][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_26__ap[9]), .CK(n_0_56), .Q(registers_26__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[25][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_25__ap[9]), .CK(n_0_55), .Q(registers_25__ap[9]), .QN()); + AOI222_X1_LVT i_1_0_877 (.A1(registers_10__ap[9]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[9]), .C1(registers_25__ap[9]), .C2( + n_1_0_1269), .ZN(n_1_0_835)); + NAND4_X1_LVT i_1_0_876 (.A1(n_1_0_841), .A2(n_1_0_837), .A3(n_1_0_836), + .A4(n_1_0_835), .ZN(n_1_0_834)); + SDFF_X1_LVT \registers_reg[8][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_8__ap[9]), .CK(n_0_38), .Q(registers_8__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[28][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_28__ap[9]), .CK(n_0_58), .Q(registers_28__ap[9]), .QN()); + AOI221_X1_LVT i_1_0_875 (.A(n_1_0_834), .B1(n_1_0_1282), .B2( + registers_8__ap[9]), .C1(registers_28__ap[9]), .C2(n_1_0_1283), .ZN( + n_1_0_833)); + SDFF_X1_LVT \registers_reg[18][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_18__ap[9]), .CK(n_0_48), .Q(registers_18__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[30][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_30__ap[9]), .CK(n_0_60), .Q(registers_30__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_874 (.A1(registers_18__ap[9]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[9]), .ZN(n_1_0_832)); + SDFF_X1_LVT \registers_reg[17][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_17__ap[9]), .CK(n_0_47), .Q(registers_17__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[12][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_12__ap[9]), .CK(n_0_42), .Q(registers_12__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_873 (.A1(registers_17__ap[9]), .A2(n_1_0_1271), .B1( + n_1_0_1260), .B2(registers_12__ap[9]), .ZN(n_1_0_831)); + SDFF_X1_LVT \registers_reg[15][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_15__ap[9]), .CK(n_0_45), .Q(registers_15__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[5][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_5__ap[9]), .CK(n_0_35), .Q(registers_5__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_872 (.A1(registers_15__ap[9]), .A2(n_1_0_1286), .B1( + n_1_0_1273), .B2(registers_5__ap[9]), .ZN(n_1_0_830)); + NAND3_X1_LVT i_1_0_871 (.A1(n_1_0_832), .A2(n_1_0_831), .A3(n_1_0_830), + .ZN(n_1_0_829)); + SDFF_X1_LVT \registers_reg[22][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_22__ap[9]), .CK(n_0_52), .Q(registers_22__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[16][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_16__ap[9]), .CK(n_0_46), .Q(registers_16__ap[9]), .QN()); + AOI221_X1_LVT i_1_0_870 (.A(n_1_0_829), .B1(n_1_0_1294), .B2( + registers_22__ap[9]), .C1(registers_16__ap[9]), .C2(n_1_0_1267), .ZN( + n_1_0_828)); + SDFF_X1_LVT \registers_reg[9][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_9__ap[9]), .CK(n_0_39), .Q(registers_9__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[1][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_1__ap[9]), .CK(n_0_0), .Q(registers_1__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_869 (.A1(registers_9__ap[9]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[9]), .ZN(n_1_0_827)); + SDFF_X1_LVT \registers_reg[6][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_6__ap[9]), .CK(n_0_36), .Q(registers_6__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[14][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_14__ap[9]), .CK(n_0_44), .Q(registers_14__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_868 (.A1(registers_6__ap[9]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[9]), .ZN(n_1_0_826)); + SDFF_X1_LVT \registers_reg[19][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_19__ap[9]), .CK(n_0_49), .Q(registers_19__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[2][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_2__ap[9]), .CK(n_0_32), .Q(registers_2__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_867 (.A1(registers_19__ap[9]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[9]), .ZN(n_1_0_825)); + NAND3_X1_LVT i_1_0_866 (.A1(n_1_0_827), .A2(n_1_0_826), .A3(n_1_0_825), + .ZN(n_1_0_824)); + SDFF_X1_LVT \registers_reg[11][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_11__ap[9]), .CK(n_0_41), .Q(registers_11__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[27][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_27__ap[9]), .CK(n_0_57), .Q(registers_27__ap[9]), .QN()); + AOI221_X1_LVT i_1_0_865 (.A(n_1_0_824), .B1(n_1_0_1270), .B2( + registers_11__ap[9]), .C1(registers_27__ap[9]), .C2(n_1_0_1279), .ZN( + n_1_0_823)); + NAND4_X1_LVT i_1_0_864 (.A1(n_1_0_838), .A2(n_1_0_833), .A3(n_1_0_828), + .A4(n_1_0_823), .ZN(RRs1[9])); + AND2_X1_LVT i_0_0_8 (.A1(n_0_0_16), .A2(WRd[8]), .ZN(registers[8])); + SDFF_X1_LVT \registers_reg[13][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_13__ap[8]), .CK(n_0_43), .Q(registers_13__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[21][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_21__ap[8]), .CK(n_0_51), .Q(registers_21__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_860 (.A1(registers_13__ap[8]), .A2(n_1_0_1277), .B1( + n_1_0_1259), .B2(registers_21__ap[8]), .ZN(n_1_0_819)); + SDFF_X1_LVT \registers_reg[29][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_29__ap[8]), .CK(n_0_59), .Q(registers_29__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[23][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_23__ap[8]), .CK(n_0_53), .Q(registers_23__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_863 (.A1(registers_29__ap[8]), .A2(n_1_0_1276), .B1( + n_1_0_1264), .B2(registers_23__ap[8]), .ZN(n_1_0_822)); + SDFF_X1_LVT \registers_reg[24][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_24__ap[8]), .CK(n_0_54), .Q(registers_24__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[20][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_20__ap[8]), .CK(n_0_50), .Q(registers_20__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_859 (.A1(registers_24__ap[8]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[8]), .ZN(n_1_0_818)); + SDFF_X1_LVT \registers_reg[7][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_7__ap[8]), .CK(n_0_37), .Q(registers_7__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[3][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_3__ap[8]), .CK(n_0_33), .Q(registers_3__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_862 (.A1(registers_7__ap[8]), .A2(n_1_0_1263), .B1( + n_1_0_1257), .B2(registers_3__ap[8]), .ZN(n_1_0_821)); + INV_X1_LVT i_1_0_861 (.A(n_1_0_821), .ZN(n_1_0_820)); + SDFF_X1_LVT \registers_reg[31][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_31__ap[8]), .CK(n_0_61), .Q(registers_31__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[4][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_4__ap[8]), .CK(n_0_34), .Q(registers_4__ap[8]), .QN()); + AOI221_X1_LVT i_1_0_858 (.A(n_1_0_820), .B1(n_1_0_1266), .B2( + registers_31__ap[8]), .C1(registers_4__ap[8]), .C2(n_1_0_1278), .ZN( + n_1_0_817)); + SDFF_X1_LVT \registers_reg[10][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_10__ap[8]), .CK(n_0_40), .Q(registers_10__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[26][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_26__ap[8]), .CK(n_0_56), .Q(registers_26__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[25][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_25__ap[8]), .CK(n_0_55), .Q(registers_25__ap[8]), .QN()); + AOI222_X1_LVT i_1_0_857 (.A1(registers_10__ap[8]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[8]), .C1(registers_25__ap[8]), .C2( + n_1_0_1269), .ZN(n_1_0_816)); + NAND4_X1_LVT i_1_0_856 (.A1(n_1_0_822), .A2(n_1_0_818), .A3(n_1_0_817), + .A4(n_1_0_816), .ZN(n_1_0_815)); + SDFF_X1_LVT \registers_reg[8][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_8__ap[8]), .CK(n_0_38), .Q(registers_8__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[28][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_28__ap[8]), .CK(n_0_58), .Q(registers_28__ap[8]), .QN()); + AOI221_X1_LVT i_1_0_855 (.A(n_1_0_815), .B1(n_1_0_1282), .B2( + registers_8__ap[8]), .C1(registers_28__ap[8]), .C2(n_1_0_1283), .ZN( + n_1_0_814)); + SDFF_X1_LVT \registers_reg[18][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_18__ap[8]), .CK(n_0_48), .Q(registers_18__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[30][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_30__ap[8]), .CK(n_0_60), .Q(registers_30__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_854 (.A1(registers_18__ap[8]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[8]), .ZN(n_1_0_813)); + SDFF_X1_LVT \registers_reg[17][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_17__ap[8]), .CK(n_0_47), .Q(registers_17__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[12][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_12__ap[8]), .CK(n_0_42), .Q(registers_12__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_853 (.A1(registers_17__ap[8]), .A2(n_1_0_1271), .B1( + n_1_0_1260), .B2(registers_12__ap[8]), .ZN(n_1_0_812)); + SDFF_X1_LVT \registers_reg[15][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_15__ap[8]), .CK(n_0_45), .Q(registers_15__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[5][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_5__ap[8]), .CK(n_0_35), .Q(registers_5__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_852 (.A1(registers_15__ap[8]), .A2(n_1_0_1286), .B1( + n_1_0_1273), .B2(registers_5__ap[8]), .ZN(n_1_0_811)); + NAND3_X1_LVT i_1_0_851 (.A1(n_1_0_813), .A2(n_1_0_812), .A3(n_1_0_811), + .ZN(n_1_0_810)); + SDFF_X1_LVT \registers_reg[22][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_22__ap[8]), .CK(n_0_52), .Q(registers_22__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[16][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_16__ap[8]), .CK(n_0_46), .Q(registers_16__ap[8]), .QN()); + AOI221_X1_LVT i_1_0_850 (.A(n_1_0_810), .B1(n_1_0_1294), .B2( + registers_22__ap[8]), .C1(registers_16__ap[8]), .C2(n_1_0_1267), .ZN( + n_1_0_809)); + SDFF_X1_LVT \registers_reg[9][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_9__ap[8]), .CK(n_0_39), .Q(registers_9__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[1][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_1__ap[8]), .CK(n_0_0), .Q(registers_1__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_849 (.A1(registers_9__ap[8]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[8]), .ZN(n_1_0_808)); + SDFF_X1_LVT \registers_reg[6][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_6__ap[8]), .CK(n_0_36), .Q(registers_6__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[14][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_14__ap[8]), .CK(n_0_44), .Q(registers_14__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_848 (.A1(registers_6__ap[8]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[8]), .ZN(n_1_0_807)); + SDFF_X1_LVT \registers_reg[19][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_19__ap[8]), .CK(n_0_49), .Q(registers_19__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[2][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_2__ap[8]), .CK(n_0_32), .Q(registers_2__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_847 (.A1(registers_19__ap[8]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[8]), .ZN(n_1_0_806)); + NAND3_X1_LVT i_1_0_846 (.A1(n_1_0_808), .A2(n_1_0_807), .A3(n_1_0_806), + .ZN(n_1_0_805)); + SDFF_X1_LVT \registers_reg[11][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_11__ap[8]), .CK(n_0_41), .Q(registers_11__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[27][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_27__ap[8]), .CK(n_0_57), .Q(registers_27__ap[8]), .QN()); + AOI221_X1_LVT i_1_0_845 (.A(n_1_0_805), .B1(n_1_0_1270), .B2( + registers_11__ap[8]), .C1(registers_27__ap[8]), .C2(n_1_0_1279), .ZN( + n_1_0_804)); + NAND4_X1_LVT i_1_0_844 (.A1(n_1_0_819), .A2(n_1_0_814), .A3(n_1_0_809), + .A4(n_1_0_804), .ZN(RRs1[8])); + AND2_X1_LVT i_0_0_7 (.A1(n_0_0_16), .A2(WRd[7]), .ZN(registers[7])); + SDFF_X1_LVT \registers_reg[13][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_13__ap[7]), .CK(n_0_43), .Q(registers_13__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[21][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_21__ap[7]), .CK(n_0_51), .Q(registers_21__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_843 (.A1(registers_13__ap[7]), .A2(n_1_0_1277), .B1( + n_1_0_1259), .B2(registers_21__ap[7]), .ZN(n_1_0_803)); + SDFF_X1_LVT \registers_reg[18][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_18__ap[7]), .CK(n_0_48), .Q(registers_18__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[10][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_10__ap[7]), .CK(n_0_40), .Q(registers_10__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[25][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_25__ap[7]), .CK(n_0_55), .Q(registers_25__ap[7]), .QN()); + AOI222_X1_LVT i_1_0_842 (.A1(registers_18__ap[7]), .A2(n_1_0_1297), .B1( + n_1_0_1287), .B2(registers_10__ap[7]), .C1(registers_25__ap[7]), .C2( + n_1_0_1269), .ZN(n_1_0_802)); + SDFF_X1_LVT \registers_reg[28][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_28__ap[7]), .CK(n_0_58), .Q(registers_28__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[8][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_8__ap[7]), .CK(n_0_38), .Q(registers_8__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_841 (.A1(registers_28__ap[7]), .A2(n_1_0_1283), .B1( + n_1_0_1282), .B2(registers_8__ap[7]), .ZN(n_1_0_801)); + SDFF_X1_LVT \registers_reg[24][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_24__ap[7]), .CK(n_0_54), .Q(registers_24__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[20][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_20__ap[7]), .CK(n_0_50), .Q(registers_20__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_840 (.A1(registers_24__ap[7]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[7]), .ZN(n_1_0_800)); + SDFF_X1_LVT \registers_reg[31][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_31__ap[7]), .CK(n_0_61), .Q(registers_31__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[7][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_7__ap[7]), .CK(n_0_37), .Q(registers_7__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_839 (.A1(registers_31__ap[7]), .A2(n_1_0_1266), .B1( + n_1_0_1263), .B2(registers_7__ap[7]), .ZN(n_1_0_799)); + SDFF_X1_LVT \registers_reg[17][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_17__ap[7]), .CK(n_0_47), .Q(registers_17__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[11][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_11__ap[7]), .CK(n_0_41), .Q(registers_11__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_838 (.A1(registers_17__ap[7]), .A2(n_1_0_1271), .B1( + n_1_0_1270), .B2(registers_11__ap[7]), .ZN(n_1_0_798)); + SDFF_X1_LVT \registers_reg[27][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_27__ap[7]), .CK(n_0_57), .Q(registers_27__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[29][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_29__ap[7]), .CK(n_0_59), .Q(registers_29__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_837 (.A1(registers_27__ap[7]), .A2(n_1_0_1279), .B1( + n_1_0_1276), .B2(registers_29__ap[7]), .ZN(n_1_0_797)); + NAND4_X1_LVT i_1_0_836 (.A1(n_1_0_800), .A2(n_1_0_799), .A3(n_1_0_798), + .A4(n_1_0_797), .ZN(n_1_0_796)); + SDFF_X1_LVT \registers_reg[26][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_26__ap[7]), .CK(n_0_56), .Q(registers_26__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[30][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_30__ap[7]), .CK(n_0_60), .Q(registers_30__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_835 (.A1(registers_26__ap[7]), .A2(n_1_0_1285), .B1( + n_1_0_1272), .B2(registers_30__ap[7]), .ZN(n_1_0_795)); + SDFF_X1_LVT \registers_reg[4][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_4__ap[7]), .CK(n_0_34), .Q(registers_4__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[12][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_12__ap[7]), .CK(n_0_42), .Q(registers_12__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_834 (.A1(registers_4__ap[7]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[7]), .ZN(n_1_0_794)); + SDFF_X1_LVT \registers_reg[15][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_15__ap[7]), .CK(n_0_45), .Q(registers_15__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[16][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_16__ap[7]), .CK(n_0_46), .Q(registers_16__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_833 (.A1(registers_15__ap[7]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[7]), .ZN(n_1_0_793)); + SDFF_X1_LVT \registers_reg[22][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_22__ap[7]), .CK(n_0_52), .Q(registers_22__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[5][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_5__ap[7]), .CK(n_0_35), .Q(registers_5__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_832 (.A1(registers_22__ap[7]), .A2(n_1_0_1294), .B1( + n_1_0_1273), .B2(registers_5__ap[7]), .ZN(n_1_0_792)); + NAND4_X1_LVT i_1_0_831 (.A1(n_1_0_795), .A2(n_1_0_794), .A3(n_1_0_793), + .A4(n_1_0_792), .ZN(n_1_0_791)); + SDFF_X1_LVT \registers_reg[19][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_19__ap[7]), .CK(n_0_49), .Q(registers_19__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[3][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_3__ap[7]), .CK(n_0_33), .Q(registers_3__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_830 (.A1(registers_19__ap[7]), .A2(n_1_0_1295), .B1( + n_1_0_1257), .B2(registers_3__ap[7]), .ZN(n_1_0_790)); + SDFF_X1_LVT \registers_reg[9][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_9__ap[7]), .CK(n_0_39), .Q(registers_9__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[1][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_1__ap[7]), .CK(n_0_0), .Q(registers_1__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_829 (.A1(registers_9__ap[7]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[7]), .ZN(n_1_0_789)); + SDFF_X1_LVT \registers_reg[6][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_6__ap[7]), .CK(n_0_36), .Q(registers_6__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[14][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_14__ap[7]), .CK(n_0_44), .Q(registers_14__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_828 (.A1(registers_6__ap[7]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[7]), .ZN(n_1_0_788)); + SDFF_X1_LVT \registers_reg[2][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_2__ap[7]), .CK(n_0_32), .Q(registers_2__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[23][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_23__ap[7]), .CK(n_0_53), .Q(registers_23__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_827 (.A1(registers_2__ap[7]), .A2(n_1_0_1268), .B1( + n_1_0_1264), .B2(registers_23__ap[7]), .ZN(n_1_0_787)); + NAND4_X1_LVT i_1_0_826 (.A1(n_1_0_790), .A2(n_1_0_789), .A3(n_1_0_788), + .A4(n_1_0_787), .ZN(n_1_0_786)); + NOR3_X1_LVT i_1_0_825 (.A1(n_1_0_796), .A2(n_1_0_791), .A3(n_1_0_786), + .ZN(n_1_0_785)); + NAND4_X1_LVT i_1_0_824 (.A1(n_1_0_803), .A2(n_1_0_802), .A3(n_1_0_801), + .A4(n_1_0_785), .ZN(RRs1[7])); + AND2_X1_LVT i_0_0_6 (.A1(n_0_0_16), .A2(WRd[6]), .ZN(registers[6])); + SDFF_X1_LVT \registers_reg[28][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_28__ap[6]), .CK(n_0_58), .Q(registers_28__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[17][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_17__ap[6]), .CK(n_0_47), .Q(registers_17__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_823 (.A1(registers_28__ap[6]), .A2(n_1_0_1283), .B1( + n_1_0_1271), .B2(registers_17__ap[6]), .ZN(n_1_0_784)); + SDFF_X1_LVT \registers_reg[18][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_18__ap[6]), .CK(n_0_48), .Q(registers_18__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[10][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_10__ap[6]), .CK(n_0_40), .Q(registers_10__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[8][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_8__ap[6]), .CK(n_0_38), .Q(registers_8__ap[6]), .QN()); + AOI222_X1_LVT i_1_0_822 (.A1(registers_18__ap[6]), .A2(n_1_0_1297), .B1( + n_1_0_1287), .B2(registers_10__ap[6]), .C1(registers_8__ap[6]), .C2( + n_1_0_1282), .ZN(n_1_0_783)); + SDFF_X1_LVT \registers_reg[9][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_9__ap[6]), .CK(n_0_39), .Q(registers_9__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[29][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_29__ap[6]), .CK(n_0_59), .Q(registers_29__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_821 (.A1(registers_9__ap[6]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[6]), .ZN(n_1_0_782)); + SDFF_X1_LVT \registers_reg[6][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_6__ap[6]), .CK(n_0_36), .Q(registers_6__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[1][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_1__ap[6]), .CK(n_0_0), .Q(registers_1__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_820 (.A1(registers_6__ap[6]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[6]), .ZN(n_1_0_781)); + SDFF_X1_LVT \registers_reg[15][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_15__ap[6]), .CK(n_0_45), .Q(registers_15__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[27][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_27__ap[6]), .CK(n_0_57), .Q(registers_27__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_819 (.A1(registers_15__ap[6]), .A2(n_1_0_1286), .B1( + n_1_0_1279), .B2(registers_27__ap[6]), .ZN(n_1_0_780)); + SDFF_X1_LVT \registers_reg[11][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_11__ap[6]), .CK(n_0_41), .Q(registers_11__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[16][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_16__ap[6]), .CK(n_0_46), .Q(registers_16__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_818 (.A1(registers_11__ap[6]), .A2(n_1_0_1270), .B1( + n_1_0_1267), .B2(registers_16__ap[6]), .ZN(n_1_0_779)); + SDFF_X1_LVT \registers_reg[5][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_5__ap[6]), .CK(n_0_35), .Q(registers_5__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[31][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_31__ap[6]), .CK(n_0_61), .Q(registers_31__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_817 (.A1(registers_5__ap[6]), .A2(n_1_0_1273), .B1( + n_1_0_1266), .B2(registers_31__ap[6]), .ZN(n_1_0_778)); + NAND4_X1_LVT i_1_0_816 (.A1(n_1_0_781), .A2(n_1_0_780), .A3(n_1_0_779), + .A4(n_1_0_778), .ZN(n_1_0_777)); + SDFF_X1_LVT \registers_reg[26][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_26__ap[6]), .CK(n_0_56), .Q(registers_26__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[30][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_30__ap[6]), .CK(n_0_60), .Q(registers_30__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_815 (.A1(registers_26__ap[6]), .A2(n_1_0_1285), .B1( + n_1_0_1272), .B2(registers_30__ap[6]), .ZN(n_1_0_776)); + SDFF_X1_LVT \registers_reg[20][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_20__ap[6]), .CK(n_0_50), .Q(registers_20__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[4][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_4__ap[6]), .CK(n_0_34), .Q(registers_4__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_814 (.A1(registers_20__ap[6]), .A2(n_1_0_1281), .B1( + n_1_0_1278), .B2(registers_4__ap[6]), .ZN(n_1_0_775)); + SDFF_X1_LVT \registers_reg[22][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_22__ap[6]), .CK(n_0_52), .Q(registers_22__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[21][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_21__ap[6]), .CK(n_0_51), .Q(registers_21__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_813 (.A1(registers_22__ap[6]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[6]), .ZN(n_1_0_774)); + SDFF_X1_LVT \registers_reg[24][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_24__ap[6]), .CK(n_0_54), .Q(registers_24__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[12][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_12__ap[6]), .CK(n_0_42), .Q(registers_12__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_812 (.A1(registers_24__ap[6]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[6]), .ZN(n_1_0_773)); + NAND4_X1_LVT i_1_0_811 (.A1(n_1_0_776), .A2(n_1_0_775), .A3(n_1_0_774), + .A4(n_1_0_773), .ZN(n_1_0_772)); + SDFF_X1_LVT \registers_reg[13][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_13__ap[6]), .CK(n_0_43), .Q(registers_13__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[25][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_25__ap[6]), .CK(n_0_55), .Q(registers_25__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_810 (.A1(registers_13__ap[6]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[6]), .ZN(n_1_0_771)); + SDFF_X1_LVT \registers_reg[7][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_7__ap[6]), .CK(n_0_37), .Q(registers_7__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[14][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_14__ap[6]), .CK(n_0_44), .Q(registers_14__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_809 (.A1(registers_7__ap[6]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[6]), .ZN(n_1_0_770)); + SDFF_X1_LVT \registers_reg[19][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_19__ap[6]), .CK(n_0_49), .Q(registers_19__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[3][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_3__ap[6]), .CK(n_0_33), .Q(registers_3__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_808 (.A1(registers_19__ap[6]), .A2(n_1_0_1295), .B1( + n_1_0_1257), .B2(registers_3__ap[6]), .ZN(n_1_0_769)); + SDFF_X1_LVT \registers_reg[2][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_2__ap[6]), .CK(n_0_32), .Q(registers_2__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[23][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_23__ap[6]), .CK(n_0_53), .Q(registers_23__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_807 (.A1(registers_2__ap[6]), .A2(n_1_0_1268), .B1( + n_1_0_1264), .B2(registers_23__ap[6]), .ZN(n_1_0_768)); + NAND4_X1_LVT i_1_0_806 (.A1(n_1_0_771), .A2(n_1_0_770), .A3(n_1_0_769), + .A4(n_1_0_768), .ZN(n_1_0_767)); + NOR3_X1_LVT i_1_0_805 (.A1(n_1_0_777), .A2(n_1_0_772), .A3(n_1_0_767), + .ZN(n_1_0_766)); + NAND4_X1_LVT i_1_0_804 (.A1(n_1_0_784), .A2(n_1_0_783), .A3(n_1_0_782), + .A4(n_1_0_766), .ZN(RRs1[6])); + AND2_X1_LVT i_0_0_5 (.A1(n_0_0_16), .A2(WRd[5]), .ZN(registers[5])); + SDFF_X1_LVT \registers_reg[28][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_28__ap[5]), .CK(n_0_58), .Q(registers_28__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[4][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_4__ap[5]), .CK(n_0_34), .Q(registers_4__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_803 (.A1(registers_28__ap[5]), .A2(n_1_0_1283), .B1( + n_1_0_1278), .B2(registers_4__ap[5]), .ZN(n_1_0_765)); + SDFF_X1_LVT \registers_reg[10][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_10__ap[5]), .CK(n_0_40), .Q(registers_10__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[26][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_26__ap[5]), .CK(n_0_56), .Q(registers_26__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[8][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_8__ap[5]), .CK(n_0_38), .Q(registers_8__ap[5]), .QN()); + AOI222_X1_LVT i_1_0_802 (.A1(registers_10__ap[5]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[5]), .C1(registers_8__ap[5]), .C2( + n_1_0_1282), .ZN(n_1_0_764)); + SDFF_X1_LVT \registers_reg[9][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_9__ap[5]), .CK(n_0_39), .Q(registers_9__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[29][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_29__ap[5]), .CK(n_0_59), .Q(registers_29__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_801 (.A1(registers_9__ap[5]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[5]), .ZN(n_1_0_763)); + SDFF_X1_LVT \registers_reg[6][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_6__ap[5]), .CK(n_0_36), .Q(registers_6__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[1][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_1__ap[5]), .CK(n_0_0), .Q(registers_1__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_800 (.A1(registers_6__ap[5]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[5]), .ZN(n_1_0_762)); + SDFF_X1_LVT \registers_reg[16][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_16__ap[5]), .CK(n_0_46), .Q(registers_16__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[3][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_3__ap[5]), .CK(n_0_33), .Q(registers_3__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_799 (.A1(registers_16__ap[5]), .A2(n_1_0_1267), .B1( + n_1_0_1257), .B2(registers_3__ap[5]), .ZN(n_1_0_761)); + SDFF_X1_LVT \registers_reg[5][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_5__ap[5]), .CK(n_0_35), .Q(registers_5__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[31][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_31__ap[5]), .CK(n_0_61), .Q(registers_31__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_798 (.A1(registers_5__ap[5]), .A2(n_1_0_1273), .B1( + n_1_0_1266), .B2(registers_31__ap[5]), .ZN(n_1_0_760)); + SDFF_X1_LVT \registers_reg[15][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_15__ap[5]), .CK(n_0_45), .Q(registers_15__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[23][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_23__ap[5]), .CK(n_0_53), .Q(registers_23__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_797 (.A1(registers_15__ap[5]), .A2(n_1_0_1286), .B1( + n_1_0_1264), .B2(registers_23__ap[5]), .ZN(n_1_0_759)); + NAND4_X1_LVT i_1_0_796 (.A1(n_1_0_762), .A2(n_1_0_761), .A3(n_1_0_760), + .A4(n_1_0_759), .ZN(n_1_0_758)); + SDFF_X1_LVT \registers_reg[18][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_18__ap[5]), .CK(n_0_48), .Q(registers_18__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[30][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_30__ap[5]), .CK(n_0_60), .Q(registers_30__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_795 (.A1(registers_18__ap[5]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[5]), .ZN(n_1_0_757)); + SDFF_X1_LVT \registers_reg[24][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_24__ap[5]), .CK(n_0_54), .Q(registers_24__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[12][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_12__ap[5]), .CK(n_0_42), .Q(registers_12__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_794 (.A1(registers_24__ap[5]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[5]), .ZN(n_1_0_756)); + SDFF_X1_LVT \registers_reg[22][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_22__ap[5]), .CK(n_0_52), .Q(registers_22__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[21][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_21__ap[5]), .CK(n_0_51), .Q(registers_21__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_793 (.A1(registers_22__ap[5]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[5]), .ZN(n_1_0_755)); + SDFF_X1_LVT \registers_reg[20][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_20__ap[5]), .CK(n_0_50), .Q(registers_20__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[17][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_17__ap[5]), .CK(n_0_47), .Q(registers_17__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_792 (.A1(registers_20__ap[5]), .A2(n_1_0_1281), .B1( + n_1_0_1271), .B2(registers_17__ap[5]), .ZN(n_1_0_754)); + NAND4_X1_LVT i_1_0_791 (.A1(n_1_0_757), .A2(n_1_0_756), .A3(n_1_0_755), + .A4(n_1_0_754), .ZN(n_1_0_753)); + SDFF_X1_LVT \registers_reg[13][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_13__ap[5]), .CK(n_0_43), .Q(registers_13__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[25][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_25__ap[5]), .CK(n_0_55), .Q(registers_25__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_790 (.A1(registers_13__ap[5]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[5]), .ZN(n_1_0_752)); + SDFF_X1_LVT \registers_reg[19][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_19__ap[5]), .CK(n_0_49), .Q(registers_19__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[2][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_2__ap[5]), .CK(n_0_32), .Q(registers_2__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_789 (.A1(registers_19__ap[5]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[5]), .ZN(n_1_0_751)); + SDFF_X1_LVT \registers_reg[7][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_7__ap[5]), .CK(n_0_37), .Q(registers_7__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[14][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_14__ap[5]), .CK(n_0_44), .Q(registers_14__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_788 (.A1(registers_7__ap[5]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[5]), .ZN(n_1_0_750)); + SDFF_X1_LVT \registers_reg[27][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_27__ap[5]), .CK(n_0_57), .Q(registers_27__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[11][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_11__ap[5]), .CK(n_0_41), .Q(registers_11__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_787 (.A1(registers_27__ap[5]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[5]), .ZN(n_1_0_749)); + NAND4_X1_LVT i_1_0_786 (.A1(n_1_0_752), .A2(n_1_0_751), .A3(n_1_0_750), + .A4(n_1_0_749), .ZN(n_1_0_748)); + NOR3_X1_LVT i_1_0_785 (.A1(n_1_0_758), .A2(n_1_0_753), .A3(n_1_0_748), + .ZN(n_1_0_747)); + NAND4_X1_LVT i_1_0_784 (.A1(n_1_0_765), .A2(n_1_0_764), .A3(n_1_0_763), + .A4(n_1_0_747), .ZN(RRs1[5])); + AND2_X1_LVT i_0_0_4 (.A1(n_0_0_16), .A2(WRd[4]), .ZN(registers[4])); + SDFF_X1_LVT \registers_reg[10][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_10__ap[4]), .CK(n_0_40), .Q(registers_10__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[21][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_21__ap[4]), .CK(n_0_51), .Q(registers_21__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_783 (.A1(registers_10__ap[4]), .A2(n_1_0_1287), .B1( + n_1_0_1259), .B2(registers_21__ap[4]), .ZN(n_1_0_746)); + SDFF_X1_LVT \registers_reg[9][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_9__ap[4]), .CK(n_0_39), .Q(registers_9__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[1][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_1__ap[4]), .CK(n_0_0), .Q(registers_1__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_778 (.A1(registers_9__ap[4]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[4]), .ZN(n_1_0_741)); + SDFF_X1_LVT \registers_reg[18][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_18__ap[4]), .CK(n_0_48), .Q(registers_18__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[8][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_8__ap[4]), .CK(n_0_38), .Q(registers_8__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_777 (.A1(registers_18__ap[4]), .A2(n_1_0_1297), .B1( + n_1_0_1282), .B2(registers_8__ap[4]), .ZN(n_1_0_740)); + NAND3_X1_LVT i_1_0_775 (.A1(n_1_0_746), .A2(n_1_0_741), .A3(n_1_0_740), + .ZN(n_1_0_738)); + SDFF_X1_LVT \registers_reg[22][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_22__ap[4]), .CK(n_0_52), .Q(registers_22__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[23][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_23__ap[4]), .CK(n_0_53), .Q(registers_23__ap[4]), .QN()); + AOI221_X1_LVT i_1_0_774 (.A(n_1_0_738), .B1(n_1_0_1294), .B2( + registers_22__ap[4]), .C1(registers_23__ap[4]), .C2(n_1_0_1264), .ZN( + n_1_0_737)); + SDFF_X1_LVT \registers_reg[28][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_28__ap[4]), .CK(n_0_58), .Q(registers_28__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[20][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_20__ap[4]), .CK(n_0_50), .Q(registers_20__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_782 (.A1(registers_28__ap[4]), .A2(n_1_0_1283), .B1( + n_1_0_1281), .B2(registers_20__ap[4]), .ZN(n_1_0_745)); + SDFF_X1_LVT \registers_reg[19][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_19__ap[4]), .CK(n_0_49), .Q(registers_19__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[13][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_13__ap[4]), .CK(n_0_43), .Q(registers_13__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_780 (.A1(registers_19__ap[4]), .A2(n_1_0_1295), .B1( + n_1_0_1277), .B2(registers_13__ap[4]), .ZN(n_1_0_743)); + SDFF_X1_LVT \registers_reg[26][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_26__ap[4]), .CK(n_0_56), .Q(registers_26__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[3][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_3__ap[4]), .CK(n_0_33), .Q(registers_3__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_776 (.A1(registers_26__ap[4]), .A2(n_1_0_1285), .B1( + n_1_0_1257), .B2(registers_3__ap[4]), .ZN(n_1_0_739)); + NAND3_X1_LVT i_1_0_773 (.A1(n_1_0_745), .A2(n_1_0_743), .A3(n_1_0_739), + .ZN(n_1_0_736)); + SDFF_X1_LVT \registers_reg[30][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_30__ap[4]), .CK(n_0_60), .Q(registers_30__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[31][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_31__ap[4]), .CK(n_0_61), .Q(registers_31__ap[4]), .QN()); + AOI221_X1_LVT i_1_0_772 (.A(n_1_0_736), .B1(n_1_0_1272), .B2( + registers_30__ap[4]), .C1(registers_31__ap[4]), .C2(n_1_0_1266), .ZN( + n_1_0_735)); + SDFF_X1_LVT \registers_reg[24][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_24__ap[4]), .CK(n_0_54), .Q(registers_24__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[12][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_12__ap[4]), .CK(n_0_42), .Q(registers_12__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_781 (.A1(registers_24__ap[4]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[4]), .ZN(n_1_0_744)); + SDFF_X1_LVT \registers_reg[27][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_27__ap[4]), .CK(n_0_57), .Q(registers_27__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[11][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_11__ap[4]), .CK(n_0_41), .Q(registers_11__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_779 (.A1(registers_27__ap[4]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[4]), .ZN(n_1_0_742)); + SDFF_X1_LVT \registers_reg[17][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_17__ap[4]), .CK(n_0_47), .Q(registers_17__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[7][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_7__ap[4]), .CK(n_0_37), .Q(registers_7__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[14][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_14__ap[4]), .CK(n_0_44), .Q(registers_14__ap[4]), .QN()); + AOI222_X1_LVT i_1_0_771 (.A1(registers_17__ap[4]), .A2(n_1_0_1271), .B1( + n_1_0_1263), .B2(registers_7__ap[4]), .C1(n_1_0_1258), .C2( + registers_14__ap[4]), .ZN(n_1_0_734)); + SDFF_X1_LVT \registers_reg[15][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_15__ap[4]), .CK(n_0_45), .Q(registers_15__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[16][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_16__ap[4]), .CK(n_0_46), .Q(registers_16__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_770 (.A1(registers_15__ap[4]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[4]), .ZN(n_1_0_733)); + SDFF_X1_LVT \registers_reg[4][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_4__ap[4]), .CK(n_0_34), .Q(registers_4__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[25][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_25__ap[4]), .CK(n_0_55), .Q(registers_25__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_769 (.A1(registers_4__ap[4]), .A2(n_1_0_1278), .B1( + n_1_0_1269), .B2(registers_25__ap[4]), .ZN(n_1_0_732)); + SDFF_X1_LVT \registers_reg[29][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_29__ap[4]), .CK(n_0_59), .Q(registers_29__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[2][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_2__ap[4]), .CK(n_0_32), .Q(registers_2__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_768 (.A1(registers_29__ap[4]), .A2(n_1_0_1276), .B1( + n_1_0_1268), .B2(registers_2__ap[4]), .ZN(n_1_0_731)); + NAND3_X1_LVT i_1_0_767 (.A1(n_1_0_733), .A2(n_1_0_732), .A3(n_1_0_731), + .ZN(n_1_0_730)); + SDFF_X1_LVT \registers_reg[6][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_6__ap[4]), .CK(n_0_36), .Q(registers_6__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[5][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_5__ap[4]), .CK(n_0_35), .Q(registers_5__ap[4]), .QN()); + AOI221_X1_LVT i_1_0_766 (.A(n_1_0_730), .B1(n_1_0_1300), .B2( + registers_6__ap[4]), .C1(registers_5__ap[4]), .C2(n_1_0_1273), .ZN( + n_1_0_729)); + AND4_X1_LVT i_1_0_765 (.A1(n_1_0_744), .A2(n_1_0_742), .A3(n_1_0_734), + .A4(n_1_0_729), .ZN(n_1_0_728)); + NAND3_X1_LVT i_1_0_764 (.A1(n_1_0_737), .A2(n_1_0_735), .A3(n_1_0_728), + .ZN(RRs1[4])); + AND2_X1_LVT i_0_0_3 (.A1(n_0_0_16), .A2(WRd[3]), .ZN(registers[3])); + SDFF_X1_LVT \registers_reg[28][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_28__ap[3]), .CK(n_0_58), .Q(registers_28__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[17][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_17__ap[3]), .CK(n_0_47), .Q(registers_17__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_763 (.A1(registers_28__ap[3]), .A2(n_1_0_1283), .B1( + n_1_0_1271), .B2(registers_17__ap[3]), .ZN(n_1_0_727)); + SDFF_X1_LVT \registers_reg[10][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_10__ap[3]), .CK(n_0_40), .Q(registers_10__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[26][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_26__ap[3]), .CK(n_0_56), .Q(registers_26__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[8][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_8__ap[3]), .CK(n_0_38), .Q(registers_8__ap[3]), .QN()); + AOI222_X1_LVT i_1_0_762 (.A1(registers_10__ap[3]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[3]), .C1(registers_8__ap[3]), .C2( + n_1_0_1282), .ZN(n_1_0_726)); + SDFF_X1_LVT \registers_reg[9][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_9__ap[3]), .CK(n_0_39), .Q(registers_9__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[29][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_29__ap[3]), .CK(n_0_59), .Q(registers_29__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_761 (.A1(registers_9__ap[3]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[3]), .ZN(n_1_0_725)); + SDFF_X1_LVT \registers_reg[6][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_6__ap[3]), .CK(n_0_36), .Q(registers_6__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[1][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_1__ap[3]), .CK(n_0_0), .Q(registers_1__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_760 (.A1(registers_6__ap[3]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[3]), .ZN(n_1_0_724)); + SDFF_X1_LVT \registers_reg[16][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_16__ap[3]), .CK(n_0_46), .Q(registers_16__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[3][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_3__ap[3]), .CK(n_0_33), .Q(registers_3__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_759 (.A1(registers_16__ap[3]), .A2(n_1_0_1267), .B1( + n_1_0_1257), .B2(registers_3__ap[3]), .ZN(n_1_0_723)); + SDFF_X1_LVT \registers_reg[5][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_5__ap[3]), .CK(n_0_35), .Q(registers_5__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[31][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_31__ap[3]), .CK(n_0_61), .Q(registers_31__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_758 (.A1(registers_5__ap[3]), .A2(n_1_0_1273), .B1( + n_1_0_1266), .B2(registers_31__ap[3]), .ZN(n_1_0_722)); + SDFF_X1_LVT \registers_reg[15][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_15__ap[3]), .CK(n_0_45), .Q(registers_15__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[23][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_23__ap[3]), .CK(n_0_53), .Q(registers_23__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_757 (.A1(registers_15__ap[3]), .A2(n_1_0_1286), .B1( + n_1_0_1264), .B2(registers_23__ap[3]), .ZN(n_1_0_721)); + NAND4_X1_LVT i_1_0_756 (.A1(n_1_0_724), .A2(n_1_0_723), .A3(n_1_0_722), + .A4(n_1_0_721), .ZN(n_1_0_720)); + SDFF_X1_LVT \registers_reg[18][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_18__ap[3]), .CK(n_0_48), .Q(registers_18__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[30][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_30__ap[3]), .CK(n_0_60), .Q(registers_30__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_755 (.A1(registers_18__ap[3]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[3]), .ZN(n_1_0_719)); + SDFF_X1_LVT \registers_reg[20][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_20__ap[3]), .CK(n_0_50), .Q(registers_20__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[4][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_4__ap[3]), .CK(n_0_34), .Q(registers_4__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_754 (.A1(registers_20__ap[3]), .A2(n_1_0_1281), .B1( + n_1_0_1278), .B2(registers_4__ap[3]), .ZN(n_1_0_718)); + SDFF_X1_LVT \registers_reg[22][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_22__ap[3]), .CK(n_0_52), .Q(registers_22__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[21][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_21__ap[3]), .CK(n_0_51), .Q(registers_21__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_753 (.A1(registers_22__ap[3]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[3]), .ZN(n_1_0_717)); + SDFF_X1_LVT \registers_reg[24][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_24__ap[3]), .CK(n_0_54), .Q(registers_24__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[12][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_12__ap[3]), .CK(n_0_42), .Q(registers_12__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_752 (.A1(registers_24__ap[3]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[3]), .ZN(n_1_0_716)); + NAND4_X1_LVT i_1_0_751 (.A1(n_1_0_719), .A2(n_1_0_718), .A3(n_1_0_717), + .A4(n_1_0_716), .ZN(n_1_0_715)); + SDFF_X1_LVT \registers_reg[13][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_13__ap[3]), .CK(n_0_43), .Q(registers_13__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[25][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_25__ap[3]), .CK(n_0_55), .Q(registers_25__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_750 (.A1(registers_13__ap[3]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[3]), .ZN(n_1_0_714)); + SDFF_X1_LVT \registers_reg[19][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_19__ap[3]), .CK(n_0_49), .Q(registers_19__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[2][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_2__ap[3]), .CK(n_0_32), .Q(registers_2__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_749 (.A1(registers_19__ap[3]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[3]), .ZN(n_1_0_713)); + SDFF_X1_LVT \registers_reg[7][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_7__ap[3]), .CK(n_0_37), .Q(registers_7__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[14][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_14__ap[3]), .CK(n_0_44), .Q(registers_14__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_748 (.A1(registers_7__ap[3]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[3]), .ZN(n_1_0_712)); + SDFF_X1_LVT \registers_reg[27][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_27__ap[3]), .CK(n_0_57), .Q(registers_27__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[11][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_11__ap[3]), .CK(n_0_41), .Q(registers_11__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_747 (.A1(registers_27__ap[3]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[3]), .ZN(n_1_0_711)); + NAND4_X1_LVT i_1_0_746 (.A1(n_1_0_714), .A2(n_1_0_713), .A3(n_1_0_712), + .A4(n_1_0_711), .ZN(n_1_0_710)); + NOR3_X1_LVT i_1_0_745 (.A1(n_1_0_720), .A2(n_1_0_715), .A3(n_1_0_710), + .ZN(n_1_0_709)); + NAND4_X1_LVT i_1_0_744 (.A1(n_1_0_727), .A2(n_1_0_726), .A3(n_1_0_725), + .A4(n_1_0_709), .ZN(RRs1[3])); + AND2_X1_LVT i_0_0_2 (.A1(n_0_0_16), .A2(WRd[2]), .ZN(registers[2])); + SDFF_X1_LVT \registers_reg[28][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_28__ap[2]), .CK(n_0_58), .Q(registers_28__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[4][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_4__ap[2]), .CK(n_0_34), .Q(registers_4__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_740 (.A1(registers_28__ap[2]), .A2(n_1_0_1283), .B1( + n_1_0_1278), .B2(registers_4__ap[2]), .ZN(n_1_0_705)); + SDFF_X1_LVT \registers_reg[16][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_16__ap[2]), .CK(n_0_46), .Q(registers_16__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[31][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_31__ap[2]), .CK(n_0_61), .Q(registers_31__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_743 (.A1(registers_16__ap[2]), .A2(n_1_0_1267), .B1( + n_1_0_1266), .B2(registers_31__ap[2]), .ZN(n_1_0_708)); + SDFF_X1_LVT \registers_reg[6][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_6__ap[2]), .CK(n_0_36), .Q(registers_6__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[1][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_1__ap[2]), .CK(n_0_0), .Q(registers_1__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_739 (.A1(registers_6__ap[2]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[2]), .ZN(n_1_0_704)); + SDFF_X1_LVT \registers_reg[15][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_15__ap[2]), .CK(n_0_45), .Q(registers_15__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[27][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_27__ap[2]), .CK(n_0_57), .Q(registers_27__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_742 (.A1(registers_15__ap[2]), .A2(n_1_0_1286), .B1( + n_1_0_1279), .B2(registers_27__ap[2]), .ZN(n_1_0_707)); + INV_X1_LVT i_1_0_741 (.A(n_1_0_707), .ZN(n_1_0_706)); + SDFF_X1_LVT \registers_reg[11][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_11__ap[2]), .CK(n_0_41), .Q(registers_11__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[5][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_5__ap[2]), .CK(n_0_35), .Q(registers_5__ap[2]), .QN()); + AOI221_X1_LVT i_1_0_738 (.A(n_1_0_706), .B1(n_1_0_1270), .B2( + registers_11__ap[2]), .C1(registers_5__ap[2]), .C2(n_1_0_1273), .ZN( + n_1_0_703)); + SDFF_X1_LVT \registers_reg[10][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_10__ap[2]), .CK(n_0_40), .Q(registers_10__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[30][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_30__ap[2]), .CK(n_0_60), .Q(registers_30__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[8][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_8__ap[2]), .CK(n_0_38), .Q(registers_8__ap[2]), .QN()); + AOI222_X1_LVT i_1_0_737 (.A1(registers_10__ap[2]), .A2(n_1_0_1287), .B1( + n_1_0_1272), .B2(registers_30__ap[2]), .C1(n_1_0_1282), .C2( + registers_8__ap[2]), .ZN(n_1_0_702)); + NAND4_X1_LVT i_1_0_736 (.A1(n_1_0_708), .A2(n_1_0_704), .A3(n_1_0_703), + .A4(n_1_0_702), .ZN(n_1_0_701)); + SDFF_X1_LVT \registers_reg[9][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_9__ap[2]), .CK(n_0_39), .Q(registers_9__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[29][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_29__ap[2]), .CK(n_0_59), .Q(registers_29__ap[2]), .QN()); + AOI221_X1_LVT i_1_0_735 (.A(n_1_0_701), .B1(n_1_0_1291), .B2( + registers_9__ap[2]), .C1(registers_29__ap[2]), .C2(n_1_0_1276), .ZN( + n_1_0_700)); + SDFF_X1_LVT \registers_reg[18][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_18__ap[2]), .CK(n_0_48), .Q(registers_18__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[26][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_26__ap[2]), .CK(n_0_56), .Q(registers_26__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_734 (.A1(registers_18__ap[2]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[2]), .ZN(n_1_0_699)); + SDFF_X1_LVT \registers_reg[24][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_24__ap[2]), .CK(n_0_54), .Q(registers_24__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[12][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_12__ap[2]), .CK(n_0_42), .Q(registers_12__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_733 (.A1(registers_24__ap[2]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[2]), .ZN(n_1_0_698)); + SDFF_X1_LVT \registers_reg[22][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_22__ap[2]), .CK(n_0_52), .Q(registers_22__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[21][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_21__ap[2]), .CK(n_0_51), .Q(registers_21__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_732 (.A1(registers_22__ap[2]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[2]), .ZN(n_1_0_697)); + NAND3_X1_LVT i_1_0_731 (.A1(n_1_0_699), .A2(n_1_0_698), .A3(n_1_0_697), + .ZN(n_1_0_696)); + SDFF_X1_LVT \registers_reg[17][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_17__ap[2]), .CK(n_0_47), .Q(registers_17__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[20][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_20__ap[2]), .CK(n_0_50), .Q(registers_20__ap[2]), .QN()); + AOI221_X1_LVT i_1_0_730 (.A(n_1_0_696), .B1(n_1_0_1271), .B2( + registers_17__ap[2]), .C1(registers_20__ap[2]), .C2(n_1_0_1281), .ZN( + n_1_0_695)); + SDFF_X1_LVT \registers_reg[13][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_13__ap[2]), .CK(n_0_43), .Q(registers_13__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[25][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_25__ap[2]), .CK(n_0_55), .Q(registers_25__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_729 (.A1(registers_13__ap[2]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[2]), .ZN(n_1_0_694)); + SDFF_X1_LVT \registers_reg[7][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_7__ap[2]), .CK(n_0_37), .Q(registers_7__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[14][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_14__ap[2]), .CK(n_0_44), .Q(registers_14__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_728 (.A1(registers_7__ap[2]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[2]), .ZN(n_1_0_693)); + SDFF_X1_LVT \registers_reg[19][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_19__ap[2]), .CK(n_0_49), .Q(registers_19__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[3][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_3__ap[2]), .CK(n_0_33), .Q(registers_3__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_727 (.A1(registers_19__ap[2]), .A2(n_1_0_1295), .B1( + n_1_0_1257), .B2(registers_3__ap[2]), .ZN(n_1_0_692)); + NAND3_X1_LVT i_1_0_726 (.A1(n_1_0_694), .A2(n_1_0_693), .A3(n_1_0_692), + .ZN(n_1_0_691)); + SDFF_X1_LVT \registers_reg[23][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_23__ap[2]), .CK(n_0_53), .Q(registers_23__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[2][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_2__ap[2]), .CK(n_0_32), .Q(registers_2__ap[2]), .QN()); + AOI221_X1_LVT i_1_0_725 (.A(n_1_0_691), .B1(n_1_0_1264), .B2( + registers_23__ap[2]), .C1(registers_2__ap[2]), .C2(n_1_0_1268), .ZN( + n_1_0_690)); + NAND4_X1_LVT i_1_0_724 (.A1(n_1_0_705), .A2(n_1_0_700), .A3(n_1_0_695), + .A4(n_1_0_690), .ZN(RRs1[2])); + AND2_X1_LVT i_0_0_1 (.A1(n_0_0_16), .A2(WRd[1]), .ZN(registers[1])); + SDFF_X1_LVT \registers_reg[13][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_13__ap[1]), .CK(n_0_43), .Q(registers_13__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[21][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_21__ap[1]), .CK(n_0_51), .Q(registers_21__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_720 (.A1(registers_13__ap[1]), .A2(n_1_0_1277), .B1( + n_1_0_1259), .B2(registers_21__ap[1]), .ZN(n_1_0_686)); + SDFF_X1_LVT \registers_reg[29][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_29__ap[1]), .CK(n_0_59), .Q(registers_29__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[23][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_23__ap[1]), .CK(n_0_53), .Q(registers_23__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_723 (.A1(registers_29__ap[1]), .A2(n_1_0_1276), .B1( + n_1_0_1264), .B2(registers_23__ap[1]), .ZN(n_1_0_689)); + SDFF_X1_LVT \registers_reg[24][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_24__ap[1]), .CK(n_0_54), .Q(registers_24__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[20][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_20__ap[1]), .CK(n_0_50), .Q(registers_20__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_719 (.A1(registers_24__ap[1]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[1]), .ZN(n_1_0_685)); + SDFF_X1_LVT \registers_reg[7][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_7__ap[1]), .CK(n_0_37), .Q(registers_7__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[3][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_3__ap[1]), .CK(n_0_33), .Q(registers_3__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_722 (.A1(registers_7__ap[1]), .A2(n_1_0_1263), .B1( + n_1_0_1257), .B2(registers_3__ap[1]), .ZN(n_1_0_688)); + INV_X1_LVT i_1_0_721 (.A(n_1_0_688), .ZN(n_1_0_687)); + SDFF_X1_LVT \registers_reg[31][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_31__ap[1]), .CK(n_0_61), .Q(registers_31__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[4][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_4__ap[1]), .CK(n_0_34), .Q(registers_4__ap[1]), .QN()); + AOI221_X1_LVT i_1_0_718 (.A(n_1_0_687), .B1(n_1_0_1266), .B2( + registers_31__ap[1]), .C1(registers_4__ap[1]), .C2(n_1_0_1278), .ZN( + n_1_0_684)); + SDFF_X1_LVT \registers_reg[10][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_10__ap[1]), .CK(n_0_40), .Q(registers_10__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[26][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_26__ap[1]), .CK(n_0_56), .Q(registers_26__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[25][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_25__ap[1]), .CK(n_0_55), .Q(registers_25__ap[1]), .QN()); + AOI222_X1_LVT i_1_0_717 (.A1(registers_10__ap[1]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[1]), .C1(registers_25__ap[1]), .C2( + n_1_0_1269), .ZN(n_1_0_683)); + NAND4_X1_LVT i_1_0_716 (.A1(n_1_0_689), .A2(n_1_0_685), .A3(n_1_0_684), + .A4(n_1_0_683), .ZN(n_1_0_682)); + SDFF_X1_LVT \registers_reg[8][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_8__ap[1]), .CK(n_0_38), .Q(registers_8__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[28][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_28__ap[1]), .CK(n_0_58), .Q(registers_28__ap[1]), .QN()); + AOI221_X1_LVT i_1_0_715 (.A(n_1_0_682), .B1(n_1_0_1282), .B2( + registers_8__ap[1]), .C1(registers_28__ap[1]), .C2(n_1_0_1283), .ZN( + n_1_0_681)); + SDFF_X1_LVT \registers_reg[18][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_18__ap[1]), .CK(n_0_48), .Q(registers_18__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[30][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_30__ap[1]), .CK(n_0_60), .Q(registers_30__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_714 (.A1(registers_18__ap[1]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[1]), .ZN(n_1_0_680)); + SDFF_X1_LVT \registers_reg[17][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_17__ap[1]), .CK(n_0_47), .Q(registers_17__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[12][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_12__ap[1]), .CK(n_0_42), .Q(registers_12__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_713 (.A1(registers_17__ap[1]), .A2(n_1_0_1271), .B1( + n_1_0_1260), .B2(registers_12__ap[1]), .ZN(n_1_0_679)); + SDFF_X1_LVT \registers_reg[15][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_15__ap[1]), .CK(n_0_45), .Q(registers_15__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[5][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_5__ap[1]), .CK(n_0_35), .Q(registers_5__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_712 (.A1(registers_15__ap[1]), .A2(n_1_0_1286), .B1( + n_1_0_1273), .B2(registers_5__ap[1]), .ZN(n_1_0_678)); + NAND3_X1_LVT i_1_0_711 (.A1(n_1_0_680), .A2(n_1_0_679), .A3(n_1_0_678), + .ZN(n_1_0_677)); + SDFF_X1_LVT \registers_reg[22][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_22__ap[1]), .CK(n_0_52), .Q(registers_22__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[16][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_16__ap[1]), .CK(n_0_46), .Q(registers_16__ap[1]), .QN()); + AOI221_X1_LVT i_1_0_710 (.A(n_1_0_677), .B1(n_1_0_1294), .B2( + registers_22__ap[1]), .C1(registers_16__ap[1]), .C2(n_1_0_1267), .ZN( + n_1_0_676)); + SDFF_X1_LVT \registers_reg[9][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_9__ap[1]), .CK(n_0_39), .Q(registers_9__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[1][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_1__ap[1]), .CK(n_0_0), .Q(registers_1__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_709 (.A1(registers_9__ap[1]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[1]), .ZN(n_1_0_675)); + SDFF_X1_LVT \registers_reg[6][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_6__ap[1]), .CK(n_0_36), .Q(registers_6__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[14][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_14__ap[1]), .CK(n_0_44), .Q(registers_14__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_708 (.A1(registers_6__ap[1]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[1]), .ZN(n_1_0_674)); + SDFF_X1_LVT \registers_reg[19][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_19__ap[1]), .CK(n_0_49), .Q(registers_19__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[2][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_2__ap[1]), .CK(n_0_32), .Q(registers_2__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_707 (.A1(registers_19__ap[1]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[1]), .ZN(n_1_0_673)); + NAND3_X1_LVT i_1_0_706 (.A1(n_1_0_675), .A2(n_1_0_674), .A3(n_1_0_673), + .ZN(n_1_0_672)); + SDFF_X1_LVT \registers_reg[11][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_11__ap[1]), .CK(n_0_41), .Q(registers_11__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[27][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_27__ap[1]), .CK(n_0_57), .Q(registers_27__ap[1]), .QN()); + AOI221_X1_LVT i_1_0_705 (.A(n_1_0_672), .B1(n_1_0_1270), .B2( + registers_11__ap[1]), .C1(registers_27__ap[1]), .C2(n_1_0_1279), .ZN( + n_1_0_671)); + NAND4_X1_LVT i_1_0_704 (.A1(n_1_0_686), .A2(n_1_0_681), .A3(n_1_0_676), + .A4(n_1_0_671), .ZN(RRs1[1])); + AND2_X1_LVT i_0_0_0 (.A1(n_0_0_16), .A2(WRd[0]), .ZN(registers[0])); + SDFF_X1_LVT \registers_reg[13][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_13__ap[0]), .CK(n_0_43), .Q(registers_13__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[21][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_21__ap[0]), .CK(n_0_51), .Q(registers_21__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_703 (.A1(registers_13__ap[0]), .A2(n_1_0_1277), .B1( + n_1_0_1259), .B2(registers_21__ap[0]), .ZN(n_1_0_670)); + SDFF_X1_LVT \registers_reg[10][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_10__ap[0]), .CK(n_0_40), .Q(registers_10__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[26][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_26__ap[0]), .CK(n_0_56), .Q(registers_26__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[25][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_25__ap[0]), .CK(n_0_55), .Q(registers_25__ap[0]), .QN()); + AOI222_X1_LVT i_1_0_702 (.A1(registers_10__ap[0]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[0]), .C1(registers_25__ap[0]), .C2( + n_1_0_1269), .ZN(n_1_0_669)); + SDFF_X1_LVT \registers_reg[28][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_28__ap[0]), .CK(n_0_58), .Q(registers_28__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[8][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_8__ap[0]), .CK(n_0_38), .Q(registers_8__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_701 (.A1(registers_28__ap[0]), .A2(n_1_0_1283), .B1( + n_1_0_1282), .B2(registers_8__ap[0]), .ZN(n_1_0_668)); + SDFF_X1_LVT \registers_reg[24][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_24__ap[0]), .CK(n_0_54), .Q(registers_24__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[20][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_20__ap[0]), .CK(n_0_50), .Q(registers_20__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_700 (.A1(registers_24__ap[0]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[0]), .ZN(n_1_0_667)); + SDFF_X1_LVT \registers_reg[7][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_7__ap[0]), .CK(n_0_37), .Q(registers_7__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[3][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_3__ap[0]), .CK(n_0_33), .Q(registers_3__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_699 (.A1(registers_7__ap[0]), .A2(n_1_0_1263), .B1( + n_1_0_1257), .B2(registers_3__ap[0]), .ZN(n_1_0_666)); + SDFF_X1_LVT \registers_reg[17][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_17__ap[0]), .CK(n_0_47), .Q(registers_17__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[31][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_31__ap[0]), .CK(n_0_61), .Q(registers_31__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_698 (.A1(registers_17__ap[0]), .A2(n_1_0_1271), .B1( + n_1_0_1266), .B2(registers_31__ap[0]), .ZN(n_1_0_665)); + SDFF_X1_LVT \registers_reg[29][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_29__ap[0]), .CK(n_0_59), .Q(registers_29__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[23][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_23__ap[0]), .CK(n_0_53), .Q(registers_23__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_697 (.A1(registers_29__ap[0]), .A2(n_1_0_1276), .B1( + n_1_0_1264), .B2(registers_23__ap[0]), .ZN(n_1_0_664)); + NAND4_X1_LVT i_1_0_696 (.A1(n_1_0_667), .A2(n_1_0_666), .A3(n_1_0_665), + .A4(n_1_0_664), .ZN(n_1_0_663)); + SDFF_X1_LVT \registers_reg[18][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_18__ap[0]), .CK(n_0_48), .Q(registers_18__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[30][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_30__ap[0]), .CK(n_0_60), .Q(registers_30__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_695 (.A1(registers_18__ap[0]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[0]), .ZN(n_1_0_662)); + SDFF_X1_LVT \registers_reg[4][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_4__ap[0]), .CK(n_0_34), .Q(registers_4__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[12][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_12__ap[0]), .CK(n_0_42), .Q(registers_12__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_694 (.A1(registers_4__ap[0]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[0]), .ZN(n_1_0_661)); + SDFF_X1_LVT \registers_reg[15][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_15__ap[0]), .CK(n_0_45), .Q(registers_15__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[16][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_16__ap[0]), .CK(n_0_46), .Q(registers_16__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_693 (.A1(registers_15__ap[0]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[0]), .ZN(n_1_0_660)); + SDFF_X1_LVT \registers_reg[22][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_22__ap[0]), .CK(n_0_52), .Q(registers_22__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[5][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_5__ap[0]), .CK(n_0_35), .Q(registers_5__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_692 (.A1(registers_22__ap[0]), .A2(n_1_0_1294), .B1( + n_1_0_1273), .B2(registers_5__ap[0]), .ZN(n_1_0_659)); + NAND4_X1_LVT i_1_0_691 (.A1(n_1_0_662), .A2(n_1_0_661), .A3(n_1_0_660), + .A4(n_1_0_659), .ZN(n_1_0_658)); + SDFF_X1_LVT \registers_reg[19][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_19__ap[0]), .CK(n_0_49), .Q(registers_19__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[2][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_2__ap[0]), .CK(n_0_32), .Q(registers_2__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_690 (.A1(registers_19__ap[0]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[0]), .ZN(n_1_0_657)); + SDFF_X1_LVT \registers_reg[9][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_9__ap[0]), .CK(n_0_39), .Q(registers_9__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[1][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_1__ap[0]), .CK(n_0_0), .Q(registers_1__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_689 (.A1(registers_9__ap[0]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[0]), .ZN(n_1_0_656)); + SDFF_X1_LVT \registers_reg[6][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_6__ap[0]), .CK(n_0_36), .Q(registers_6__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[14][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_14__ap[0]), .CK(n_0_44), .Q(registers_14__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_688 (.A1(registers_6__ap[0]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[0]), .ZN(n_1_0_655)); + SDFF_X1_LVT \registers_reg[27][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_27__ap[0]), .CK(n_0_57), .Q(registers_27__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[11][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_11__ap[0]), .CK(n_0_41), .Q(registers_11__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_687 (.A1(registers_27__ap[0]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[0]), .ZN(n_1_0_654)); + NAND4_X1_LVT i_1_0_686 (.A1(n_1_0_657), .A2(n_1_0_656), .A3(n_1_0_655), + .A4(n_1_0_654), .ZN(n_1_0_653)); + NOR3_X1_LVT i_1_0_685 (.A1(n_1_0_663), .A2(n_1_0_658), .A3(n_1_0_653), + .ZN(n_1_0_652)); + NAND4_X1_LVT i_1_0_684 (.A1(n_1_0_670), .A2(n_1_0_669), .A3(n_1_0_668), + .A4(n_1_0_652), .ZN(RRs1[0])); + INV_X1_LVT i_1_0_1366 (.A(Rs2[1]), .ZN(n_1_0_1302)); + NAND3_X1_LVT i_1_0_683 (.A1(n_1_0_1302), .A2(Rs2[4]), .A3(Rs2[2]), .ZN( + n_1_0_651)); + INV_X1_LVT i_1_0_1369 (.A(Rs2[3]), .ZN(n_1_0_1305)); + OR2_X1_LVT i_1_0_673 (.A1(n_1_0_1305), .A2(Rs2[0]), .ZN(n_1_0_641)); + NOR2_X1_LVT i_1_0_666 (.A1(n_1_0_651), .A2(n_1_0_641), .ZN(n_1_0_634)); + NAND2_X1_LVT i_1_0_677 (.A1(n_1_0_1305), .A2(Rs2[0]), .ZN(n_1_0_645)); + INV_X1_LVT i_1_0_1368 (.A(Rs2[2]), .ZN(n_1_0_1304)); + NAND3_X1_LVT i_1_0_662 (.A1(n_1_0_1304), .A2(n_1_0_1302), .A3(Rs2[4]), + .ZN(n_1_0_630)); + NOR2_X1_LVT i_1_0_661 (.A1(n_1_0_645), .A2(n_1_0_630), .ZN(n_1_0_629)); + AOI22_X1_LVT i_1_0_641 (.A1(registers_28__ap[31]), .A2(n_1_0_634), .B1( + n_1_0_629), .B2(registers_17__ap[31]), .ZN(n_1_0_609)); + NAND3_X1_LVT i_1_0_680 (.A1(n_1_0_1304), .A2(Rs2[4]), .A3(Rs2[1]), .ZN( + n_1_0_648)); + NOR2_X1_LVT i_1_0_672 (.A1(n_1_0_648), .A2(n_1_0_641), .ZN(n_1_0_640)); + INV_X1_LVT i_1_0_1367 (.A(Rs2[4]), .ZN(n_1_0_1303)); + NAND3_X1_LVT i_1_0_657 (.A1(n_1_0_1304), .A2(n_1_0_1303), .A3(Rs2[1]), + .ZN(n_1_0_625)); + NOR2_X1_LVT i_1_0_656 (.A1(n_1_0_641), .A2(n_1_0_625), .ZN(n_1_0_624)); + NOR4_X1_LVT i_1_0_658 (.A1(n_1_0_641), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), + .ZN(n_1_0_626)); + AOI222_X1_LVT i_1_0_640 (.A1(registers_26__ap[31]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[31]), .C1(n_1_0_626), .C2( + registers_8__ap[31]), .ZN(n_1_0_608)); + NAND2_X1_LVT i_1_0_682 (.A1(Rs2[0]), .A2(Rs2[3]), .ZN(n_1_0_650)); + NOR2_X1_LVT i_1_0_681 (.A1(n_1_0_651), .A2(n_1_0_650), .ZN(n_1_0_649)); + NOR4_X1_LVT i_1_0_649 (.A1(n_1_0_650), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), + .ZN(n_1_0_617)); + AOI22_X1_LVT i_1_0_639 (.A1(registers_29__ap[31]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[31]), .ZN(n_1_0_607)); + NOR4_X1_LVT i_1_0_676 (.A1(n_1_0_645), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), + .ZN(n_1_0_644)); + OR2_X1_LVT i_1_0_679 (.A1(Rs2[0]), .A2(Rs2[3]), .ZN(n_1_0_647)); + NAND3_X1_LVT i_1_0_660 (.A1(n_1_0_1303), .A2(Rs2[1]), .A3(Rs2[2]), .ZN( + n_1_0_628)); + NOR2_X1_LVT i_1_0_648 (.A1(n_1_0_647), .A2(n_1_0_628), .ZN(n_1_0_616)); + AOI22_X1_LVT i_1_0_638 (.A1(registers_1__ap[31]), .A2(n_1_0_644), .B1( + n_1_0_616), .B2(registers_6__ap[31]), .ZN(n_1_0_606)); + NOR2_X1_LVT i_1_0_655 (.A1(n_1_0_645), .A2(n_1_0_628), .ZN(n_1_0_623)); + NAND3_X1_LVT i_1_0_675 (.A1(Rs2[2]), .A2(Rs2[4]), .A3(Rs2[1]), .ZN(n_1_0_643)); + NOR2_X1_LVT i_1_0_647 (.A1(n_1_0_645), .A2(n_1_0_643), .ZN(n_1_0_615)); + AOI22_X1_LVT i_1_0_637 (.A1(registers_7__ap[31]), .A2(n_1_0_623), .B1( + n_1_0_615), .B2(registers_23__ap[31]), .ZN(n_1_0_605)); + NOR2_X1_LVT i_1_0_665 (.A1(n_1_0_648), .A2(n_1_0_645), .ZN(n_1_0_633)); + NOR2_X1_LVT i_1_0_646 (.A1(n_1_0_647), .A2(n_1_0_630), .ZN(n_1_0_614)); + AOI22_X1_LVT i_1_0_636 (.A1(registers_19__ap[31]), .A2(n_1_0_633), .B1( + n_1_0_614), .B2(registers_16__ap[31]), .ZN(n_1_0_604)); + NOR2_X1_LVT i_1_0_669 (.A1(n_1_0_650), .A2(n_1_0_643), .ZN(n_1_0_637)); + NAND3_X1_LVT i_1_0_671 (.A1(n_1_0_1303), .A2(n_1_0_1302), .A3(Rs2[2]), + .ZN(n_1_0_639)); + NOR2_X1_LVT i_1_0_667 (.A1(n_1_0_645), .A2(n_1_0_639), .ZN(n_1_0_635)); + AOI22_X1_LVT i_1_0_635 (.A1(registers_31__ap[31]), .A2(n_1_0_637), .B1( + n_1_0_635), .B2(registers_5__ap[31]), .ZN(n_1_0_603)); + NAND4_X1_LVT i_1_0_634 (.A1(n_1_0_606), .A2(n_1_0_605), .A3(n_1_0_604), + .A4(n_1_0_603), .ZN(n_1_0_602)); + NOR2_X1_LVT i_1_0_678 (.A1(n_1_0_648), .A2(n_1_0_647), .ZN(n_1_0_646)); + NOR2_X1_LVT i_1_0_654 (.A1(n_1_0_643), .A2(n_1_0_641), .ZN(n_1_0_622)); + AOI22_X1_LVT i_1_0_633 (.A1(registers_18__ap[31]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[31]), .ZN(n_1_0_601)); + NOR2_X1_LVT i_1_0_670 (.A1(n_1_0_647), .A2(n_1_0_639), .ZN(n_1_0_638)); + NOR2_X1_LVT i_1_0_645 (.A1(n_1_0_651), .A2(n_1_0_647), .ZN(n_1_0_613)); + AOI22_X1_LVT i_1_0_632 (.A1(registers_4__ap[31]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[31]), .ZN(n_1_0_600)); + NOR2_X1_LVT i_1_0_674 (.A1(n_1_0_647), .A2(n_1_0_643), .ZN(n_1_0_642)); + NOR2_X1_LVT i_1_0_644 (.A1(n_1_0_651), .A2(n_1_0_645), .ZN(n_1_0_612)); + AOI22_X1_LVT i_1_0_631 (.A1(registers_22__ap[31]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[31]), .ZN(n_1_0_599)); + NOR2_X1_LVT i_1_0_664 (.A1(n_1_0_641), .A2(n_1_0_639), .ZN(n_1_0_632)); + NOR2_X1_LVT i_1_0_653 (.A1(n_1_0_641), .A2(n_1_0_630), .ZN(n_1_0_621)); + AOI22_X1_LVT i_1_0_630 (.A1(registers_12__ap[31]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[31]), .ZN(n_1_0_598)); + NAND4_X1_LVT i_1_0_629 (.A1(n_1_0_601), .A2(n_1_0_600), .A3(n_1_0_599), + .A4(n_1_0_598), .ZN(n_1_0_597)); + NOR2_X1_LVT i_1_0_663 (.A1(n_1_0_650), .A2(n_1_0_639), .ZN(n_1_0_631)); + NOR2_X1_LVT i_1_0_652 (.A1(n_1_0_650), .A2(n_1_0_630), .ZN(n_1_0_620)); + AOI22_X1_LVT i_1_0_628 (.A1(registers_13__ap[31]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[31]), .ZN(n_1_0_596)); + NOR2_X1_LVT i_1_0_659 (.A1(n_1_0_650), .A2(n_1_0_628), .ZN(n_1_0_627)); + NOR2_X1_LVT i_1_0_651 (.A1(n_1_0_641), .A2(n_1_0_628), .ZN(n_1_0_619)); + AOI22_X1_LVT i_1_0_627 (.A1(registers_15__ap[31]), .A2(n_1_0_627), .B1( + n_1_0_619), .B2(registers_14__ap[31]), .ZN(n_1_0_595)); + NOR2_X1_LVT i_1_0_668 (.A1(n_1_0_650), .A2(n_1_0_648), .ZN(n_1_0_636)); + NOR2_X1_LVT i_1_0_643 (.A1(n_1_0_650), .A2(n_1_0_625), .ZN(n_1_0_611)); + AOI22_X1_LVT i_1_0_626 (.A1(registers_27__ap[31]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[31]), .ZN(n_1_0_594)); + NOR2_X1_LVT i_1_0_650 (.A1(n_1_0_647), .A2(n_1_0_625), .ZN(n_1_0_618)); + NOR2_X1_LVT i_1_0_642 (.A1(n_1_0_645), .A2(n_1_0_625), .ZN(n_1_0_610)); + AOI22_X1_LVT i_1_0_625 (.A1(registers_2__ap[31]), .A2(n_1_0_618), .B1( + n_1_0_610), .B2(registers_3__ap[31]), .ZN(n_1_0_593)); + NAND4_X1_LVT i_1_0_624 (.A1(n_1_0_596), .A2(n_1_0_595), .A3(n_1_0_594), + .A4(n_1_0_593), .ZN(n_1_0_592)); + NOR3_X1_LVT i_1_0_623 (.A1(n_1_0_602), .A2(n_1_0_597), .A3(n_1_0_592), + .ZN(n_1_0_591)); + NAND4_X1_LVT i_1_0_622 (.A1(n_1_0_609), .A2(n_1_0_608), .A3(n_1_0_607), + .A4(n_1_0_591), .ZN(RRs2[31])); + AOI22_X1_LVT i_1_0_620 (.A1(registers_29__ap[30]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[30]), .ZN(n_1_0_589)); + AOI22_X1_LVT i_1_0_621 (.A1(registers_7__ap[30]), .A2(n_1_0_623), .B1( + n_1_0_615), .B2(registers_23__ap[30]), .ZN(n_1_0_590)); + AOI22_X1_LVT i_1_0_619 (.A1(registers_1__ap[30]), .A2(n_1_0_644), .B1( + n_1_0_616), .B2(registers_6__ap[30]), .ZN(n_1_0_588)); + AOI22_X1_LVT i_1_0_618 (.A1(registers_5__ap[30]), .A2(n_1_0_635), .B1( + n_1_0_633), .B2(registers_19__ap[30]), .ZN(n_1_0_587)); + NAND3_X1_LVT i_1_0_617 (.A1(n_1_0_590), .A2(n_1_0_588), .A3(n_1_0_587), + .ZN(n_1_0_586)); + AOI221_X1_LVT i_1_0_616 (.A(n_1_0_586), .B1(n_1_0_637), .B2( + registers_31__ap[30]), .C1(registers_16__ap[30]), .C2(n_1_0_614), .ZN( + n_1_0_585)); + AOI222_X1_LVT i_1_0_615 (.A1(registers_26__ap[30]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[30]), .C1(n_1_0_626), .C2( + registers_8__ap[30]), .ZN(n_1_0_584)); + NAND3_X1_LVT i_1_0_614 (.A1(n_1_0_589), .A2(n_1_0_585), .A3(n_1_0_584), + .ZN(n_1_0_583)); + AOI221_X1_LVT i_1_0_613 (.A(n_1_0_583), .B1(n_1_0_629), .B2( + registers_17__ap[30]), .C1(registers_28__ap[30]), .C2(n_1_0_634), .ZN( + n_1_0_582)); + AOI22_X1_LVT i_1_0_612 (.A1(registers_18__ap[30]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[30]), .ZN(n_1_0_581)); + AOI22_X1_LVT i_1_0_611 (.A1(registers_4__ap[30]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[30]), .ZN(n_1_0_580)); + AOI22_X1_LVT i_1_0_610 (.A1(registers_22__ap[30]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[30]), .ZN(n_1_0_579)); + NAND3_X1_LVT i_1_0_609 (.A1(n_1_0_581), .A2(n_1_0_580), .A3(n_1_0_579), + .ZN(n_1_0_578)); + AOI221_X1_LVT i_1_0_608 (.A(n_1_0_578), .B1(n_1_0_621), .B2( + registers_24__ap[30]), .C1(registers_12__ap[30]), .C2(n_1_0_632), .ZN( + n_1_0_577)); + AOI22_X1_LVT i_1_0_607 (.A1(registers_13__ap[30]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[30]), .ZN(n_1_0_576)); + AOI22_X1_LVT i_1_0_606 (.A1(registers_15__ap[30]), .A2(n_1_0_627), .B1( + n_1_0_619), .B2(registers_14__ap[30]), .ZN(n_1_0_575)); + AOI22_X1_LVT i_1_0_605 (.A1(registers_27__ap[30]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[30]), .ZN(n_1_0_574)); + NAND3_X1_LVT i_1_0_604 (.A1(n_1_0_576), .A2(n_1_0_575), .A3(n_1_0_574), + .ZN(n_1_0_573)); + AOI221_X1_LVT i_1_0_603 (.A(n_1_0_573), .B1(n_1_0_610), .B2( + registers_3__ap[30]), .C1(registers_2__ap[30]), .C2(n_1_0_618), .ZN( + n_1_0_572)); + NAND3_X1_LVT i_1_0_602 (.A1(n_1_0_582), .A2(n_1_0_577), .A3(n_1_0_572), + .ZN(RRs2[30])); + AOI22_X1_LVT i_1_0_600 (.A1(registers_28__ap[29]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[29]), .ZN(n_1_0_570)); + AOI22_X1_LVT i_1_0_601 (.A1(registers_31__ap[29]), .A2(n_1_0_637), .B1( + n_1_0_627), .B2(registers_15__ap[29]), .ZN(n_1_0_571)); + AOI22_X1_LVT i_1_0_599 (.A1(registers_24__ap[29]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[29]), .ZN(n_1_0_569)); + AOI22_X1_LVT i_1_0_598 (.A1(registers_19__ap[29]), .A2(n_1_0_633), .B1( + n_1_0_629), .B2(registers_17__ap[29]), .ZN(n_1_0_568)); + NAND3_X1_LVT i_1_0_597 (.A1(n_1_0_571), .A2(n_1_0_569), .A3(n_1_0_568), + .ZN(n_1_0_567)); + AOI221_X1_LVT i_1_0_596 (.A(n_1_0_567), .B1(n_1_0_615), .B2( + registers_23__ap[29]), .C1(registers_29__ap[29]), .C2(n_1_0_649), .ZN( + n_1_0_566)); + AOI222_X1_LVT i_1_0_595 (.A1(registers_26__ap[29]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[29]), .C1(n_1_0_620), .C2( + registers_25__ap[29]), .ZN(n_1_0_565)); + NAND3_X1_LVT i_1_0_594 (.A1(n_1_0_570), .A2(n_1_0_566), .A3(n_1_0_565), + .ZN(n_1_0_564)); + AOI221_X1_LVT i_1_0_593 (.A(n_1_0_564), .B1(n_1_0_612), .B2( + registers_21__ap[29]), .C1(registers_13__ap[29]), .C2(n_1_0_631), .ZN( + n_1_0_563)); + AOI22_X1_LVT i_1_0_592 (.A1(registers_18__ap[29]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[29]), .ZN(n_1_0_562)); + AOI22_X1_LVT i_1_0_591 (.A1(registers_4__ap[29]), .A2(n_1_0_638), .B1( + n_1_0_632), .B2(registers_12__ap[29]), .ZN(n_1_0_561)); + AOI22_X1_LVT i_1_0_590 (.A1(registers_7__ap[29]), .A2(n_1_0_623), .B1( + n_1_0_614), .B2(registers_16__ap[29]), .ZN(n_1_0_560)); + NAND3_X1_LVT i_1_0_589 (.A1(n_1_0_562), .A2(n_1_0_561), .A3(n_1_0_560), + .ZN(n_1_0_559)); + AOI221_X1_LVT i_1_0_588 (.A(n_1_0_559), .B1(n_1_0_642), .B2( + registers_22__ap[29]), .C1(registers_5__ap[29]), .C2(n_1_0_635), .ZN( + n_1_0_558)); + AOI22_X1_LVT i_1_0_587 (.A1(registers_1__ap[29]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[29]), .ZN(n_1_0_557)); + AOI22_X1_LVT i_1_0_586 (.A1(registers_14__ap[29]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[29]), .ZN(n_1_0_556)); + AOI22_X1_LVT i_1_0_585 (.A1(registers_27__ap[29]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[29]), .ZN(n_1_0_555)); + NAND3_X1_LVT i_1_0_584 (.A1(n_1_0_557), .A2(n_1_0_556), .A3(n_1_0_555), + .ZN(n_1_0_554)); + AOI221_X1_LVT i_1_0_583 (.A(n_1_0_554), .B1(n_1_0_610), .B2( + registers_3__ap[29]), .C1(registers_2__ap[29]), .C2(n_1_0_618), .ZN( + n_1_0_553)); + NAND3_X1_LVT i_1_0_582 (.A1(n_1_0_563), .A2(n_1_0_558), .A3(n_1_0_553), + .ZN(RRs2[29])); + AOI22_X1_LVT i_1_0_581 (.A1(registers_5__ap[28]), .A2(n_1_0_635), .B1( + n_1_0_634), .B2(registers_28__ap[28]), .ZN(n_1_0_552)); + AOI222_X1_LVT i_1_0_580 (.A1(registers_26__ap[28]), .A2(n_1_0_640), .B1( + n_1_0_633), .B2(registers_19__ap[28]), .C1(n_1_0_626), .C2( + registers_8__ap[28]), .ZN(n_1_0_551)); + AOI22_X1_LVT i_1_0_579 (.A1(registers_2__ap[28]), .A2(n_1_0_618), .B1( + n_1_0_617), .B2(registers_9__ap[28]), .ZN(n_1_0_550)); + AOI22_X1_LVT i_1_0_578 (.A1(registers_7__ap[28]), .A2(n_1_0_623), .B1( + n_1_0_612), .B2(registers_21__ap[28]), .ZN(n_1_0_549)); + AOI22_X1_LVT i_1_0_577 (.A1(registers_16__ap[28]), .A2(n_1_0_614), .B1( + n_1_0_611), .B2(registers_11__ap[28]), .ZN(n_1_0_548)); + AOI22_X1_LVT i_1_0_576 (.A1(registers_31__ap[28]), .A2(n_1_0_637), .B1( + n_1_0_619), .B2(registers_14__ap[28]), .ZN(n_1_0_547)); + AOI22_X1_LVT i_1_0_575 (.A1(registers_15__ap[28]), .A2(n_1_0_627), .B1( + n_1_0_610), .B2(registers_3__ap[28]), .ZN(n_1_0_546)); + NAND4_X1_LVT i_1_0_574 (.A1(n_1_0_549), .A2(n_1_0_548), .A3(n_1_0_547), + .A4(n_1_0_546), .ZN(n_1_0_545)); + AOI22_X1_LVT i_1_0_573 (.A1(registers_22__ap[28]), .A2(n_1_0_642), .B1( + n_1_0_622), .B2(registers_30__ap[28]), .ZN(n_1_0_544)); + AOI22_X1_LVT i_1_0_572 (.A1(registers_4__ap[28]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[28]), .ZN(n_1_0_543)); + AOI22_X1_LVT i_1_0_571 (.A1(registers_29__ap[28]), .A2(n_1_0_649), .B1( + n_1_0_644), .B2(registers_1__ap[28]), .ZN(n_1_0_542)); + AOI22_X1_LVT i_1_0_570 (.A1(registers_12__ap[28]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[28]), .ZN(n_1_0_541)); + NAND4_X1_LVT i_1_0_569 (.A1(n_1_0_544), .A2(n_1_0_543), .A3(n_1_0_542), + .A4(n_1_0_541), .ZN(n_1_0_540)); + AOI22_X1_LVT i_1_0_568 (.A1(registers_13__ap[28]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[28]), .ZN(n_1_0_539)); + AOI22_X1_LVT i_1_0_567 (.A1(registers_17__ap[28]), .A2(n_1_0_629), .B1( + n_1_0_616), .B2(registers_6__ap[28]), .ZN(n_1_0_538)); + AOI22_X1_LVT i_1_0_566 (.A1(registers_10__ap[28]), .A2(n_1_0_624), .B1( + n_1_0_615), .B2(registers_23__ap[28]), .ZN(n_1_0_537)); + AOI22_X1_LVT i_1_0_565 (.A1(registers_18__ap[28]), .A2(n_1_0_646), .B1( + n_1_0_636), .B2(registers_27__ap[28]), .ZN(n_1_0_536)); + NAND4_X1_LVT i_1_0_564 (.A1(n_1_0_539), .A2(n_1_0_538), .A3(n_1_0_537), + .A4(n_1_0_536), .ZN(n_1_0_535)); + NOR3_X1_LVT i_1_0_563 (.A1(n_1_0_545), .A2(n_1_0_540), .A3(n_1_0_535), + .ZN(n_1_0_534)); + NAND4_X1_LVT i_1_0_562 (.A1(n_1_0_552), .A2(n_1_0_551), .A3(n_1_0_550), + .A4(n_1_0_534), .ZN(RRs2[28])); + AOI22_X1_LVT i_1_0_561 (.A1(registers_17__ap[27]), .A2(n_1_0_629), .B1( + n_1_0_612), .B2(registers_21__ap[27]), .ZN(n_1_0_533)); + AOI222_X1_LVT i_1_0_560 (.A1(registers_19__ap[27]), .A2(n_1_0_633), .B1( + n_1_0_631), .B2(registers_13__ap[27]), .C1(registers_30__ap[27]), .C2( + n_1_0_622), .ZN(n_1_0_532)); + AOI22_X1_LVT i_1_0_559 (.A1(registers_1__ap[27]), .A2(n_1_0_644), .B1( + n_1_0_634), .B2(registers_28__ap[27]), .ZN(n_1_0_531)); + AOI22_X1_LVT i_1_0_558 (.A1(registers_24__ap[27]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[27]), .ZN(n_1_0_530)); + AOI22_X1_LVT i_1_0_557 (.A1(registers_15__ap[27]), .A2(n_1_0_627), .B1( + n_1_0_611), .B2(registers_11__ap[27]), .ZN(n_1_0_529)); + AOI22_X1_LVT i_1_0_556 (.A1(registers_4__ap[27]), .A2(n_1_0_638), .B1( + n_1_0_636), .B2(registers_27__ap[27]), .ZN(n_1_0_528)); + AOI22_X1_LVT i_1_0_555 (.A1(registers_31__ap[27]), .A2(n_1_0_637), .B1( + n_1_0_618), .B2(registers_2__ap[27]), .ZN(n_1_0_527)); + NAND4_X1_LVT i_1_0_554 (.A1(n_1_0_530), .A2(n_1_0_529), .A3(n_1_0_528), + .A4(n_1_0_527), .ZN(n_1_0_526)); + AOI22_X1_LVT i_1_0_553 (.A1(registers_18__ap[27]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[27]), .ZN(n_1_0_525)); + AOI22_X1_LVT i_1_0_552 (.A1(registers_5__ap[27]), .A2(n_1_0_635), .B1( + n_1_0_632), .B2(registers_12__ap[27]), .ZN(n_1_0_524)); + AOI22_X1_LVT i_1_0_551 (.A1(registers_6__ap[27]), .A2(n_1_0_616), .B1( + n_1_0_614), .B2(registers_16__ap[27]), .ZN(n_1_0_523)); + AOI22_X1_LVT i_1_0_550 (.A1(registers_22__ap[27]), .A2(n_1_0_642), .B1( + n_1_0_620), .B2(registers_25__ap[27]), .ZN(n_1_0_522)); + NAND4_X1_LVT i_1_0_549 (.A1(n_1_0_525), .A2(n_1_0_524), .A3(n_1_0_523), + .A4(n_1_0_522), .ZN(n_1_0_521)); + AOI22_X1_LVT i_1_0_548 (.A1(registers_29__ap[27]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[27]), .ZN(n_1_0_520)); + AOI22_X1_LVT i_1_0_547 (.A1(registers_7__ap[27]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[27]), .ZN(n_1_0_519)); + AOI22_X1_LVT i_1_0_546 (.A1(registers_8__ap[27]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[27]), .ZN(n_1_0_518)); + AOI22_X1_LVT i_1_0_545 (.A1(registers_10__ap[27]), .A2(n_1_0_624), .B1( + n_1_0_610), .B2(registers_3__ap[27]), .ZN(n_1_0_517)); + NAND4_X1_LVT i_1_0_544 (.A1(n_1_0_520), .A2(n_1_0_519), .A3(n_1_0_518), + .A4(n_1_0_517), .ZN(n_1_0_516)); + NOR3_X1_LVT i_1_0_543 (.A1(n_1_0_526), .A2(n_1_0_521), .A3(n_1_0_516), + .ZN(n_1_0_515)); + NAND4_X1_LVT i_1_0_542 (.A1(n_1_0_533), .A2(n_1_0_532), .A3(n_1_0_531), + .A4(n_1_0_515), .ZN(RRs2[27])); + AOI22_X1_LVT i_1_0_541 (.A1(registers_17__ap[26]), .A2(n_1_0_629), .B1( + n_1_0_612), .B2(registers_21__ap[26]), .ZN(n_1_0_514)); + AOI222_X1_LVT i_1_0_540 (.A1(registers_19__ap[26]), .A2(n_1_0_633), .B1( + n_1_0_622), .B2(registers_30__ap[26]), .C1(n_1_0_631), .C2( + registers_13__ap[26]), .ZN(n_1_0_513)); + AOI22_X1_LVT i_1_0_539 (.A1(registers_1__ap[26]), .A2(n_1_0_644), .B1( + n_1_0_634), .B2(registers_28__ap[26]), .ZN(n_1_0_512)); + AOI22_X1_LVT i_1_0_538 (.A1(registers_24__ap[26]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[26]), .ZN(n_1_0_511)); + AOI22_X1_LVT i_1_0_537 (.A1(registers_15__ap[26]), .A2(n_1_0_627), .B1( + n_1_0_611), .B2(registers_11__ap[26]), .ZN(n_1_0_510)); + AOI22_X1_LVT i_1_0_536 (.A1(registers_4__ap[26]), .A2(n_1_0_638), .B1( + n_1_0_636), .B2(registers_27__ap[26]), .ZN(n_1_0_509)); + AOI22_X1_LVT i_1_0_535 (.A1(registers_31__ap[26]), .A2(n_1_0_637), .B1( + n_1_0_618), .B2(registers_2__ap[26]), .ZN(n_1_0_508)); + NAND4_X1_LVT i_1_0_534 (.A1(n_1_0_511), .A2(n_1_0_510), .A3(n_1_0_509), + .A4(n_1_0_508), .ZN(n_1_0_507)); + AOI22_X1_LVT i_1_0_533 (.A1(registers_18__ap[26]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[26]), .ZN(n_1_0_506)); + AOI22_X1_LVT i_1_0_532 (.A1(registers_5__ap[26]), .A2(n_1_0_635), .B1( + n_1_0_632), .B2(registers_12__ap[26]), .ZN(n_1_0_505)); + AOI22_X1_LVT i_1_0_531 (.A1(registers_6__ap[26]), .A2(n_1_0_616), .B1( + n_1_0_614), .B2(registers_16__ap[26]), .ZN(n_1_0_504)); + AOI22_X1_LVT i_1_0_530 (.A1(registers_22__ap[26]), .A2(n_1_0_642), .B1( + n_1_0_620), .B2(registers_25__ap[26]), .ZN(n_1_0_503)); + NAND4_X1_LVT i_1_0_529 (.A1(n_1_0_506), .A2(n_1_0_505), .A3(n_1_0_504), + .A4(n_1_0_503), .ZN(n_1_0_502)); + AOI22_X1_LVT i_1_0_528 (.A1(registers_29__ap[26]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[26]), .ZN(n_1_0_501)); + AOI22_X1_LVT i_1_0_527 (.A1(registers_7__ap[26]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[26]), .ZN(n_1_0_500)); + AOI22_X1_LVT i_1_0_526 (.A1(registers_8__ap[26]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[26]), .ZN(n_1_0_499)); + AOI22_X1_LVT i_1_0_525 (.A1(registers_10__ap[26]), .A2(n_1_0_624), .B1( + n_1_0_610), .B2(registers_3__ap[26]), .ZN(n_1_0_498)); + NAND4_X1_LVT i_1_0_524 (.A1(n_1_0_501), .A2(n_1_0_500), .A3(n_1_0_499), + .A4(n_1_0_498), .ZN(n_1_0_497)); + NOR3_X1_LVT i_1_0_523 (.A1(n_1_0_507), .A2(n_1_0_502), .A3(n_1_0_497), + .ZN(n_1_0_496)); + NAND4_X1_LVT i_1_0_522 (.A1(n_1_0_514), .A2(n_1_0_513), .A3(n_1_0_512), + .A4(n_1_0_496), .ZN(RRs2[26])); + AOI22_X1_LVT i_1_0_520 (.A1(registers_5__ap[25]), .A2(n_1_0_635), .B1( + n_1_0_634), .B2(registers_28__ap[25]), .ZN(n_1_0_494)); + AOI22_X1_LVT i_1_0_521 (.A1(registers_8__ap[25]), .A2(n_1_0_626), .B1( + n_1_0_620), .B2(registers_25__ap[25]), .ZN(n_1_0_495)); + AOI22_X1_LVT i_1_0_519 (.A1(registers_14__ap[25]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[25]), .ZN(n_1_0_493)); + AOI22_X1_LVT i_1_0_518 (.A1(registers_16__ap[25]), .A2(n_1_0_614), .B1( + n_1_0_611), .B2(registers_11__ap[25]), .ZN(n_1_0_492)); + NAND3_X1_LVT i_1_0_517 (.A1(n_1_0_495), .A2(n_1_0_493), .A3(n_1_0_492), + .ZN(n_1_0_491)); + AOI221_X1_LVT i_1_0_516 (.A(n_1_0_491), .B1(n_1_0_624), .B2( + registers_10__ap[25]), .C1(registers_6__ap[25]), .C2(n_1_0_616), .ZN( + n_1_0_490)); + AOI222_X1_LVT i_1_0_515 (.A1(registers_1__ap[25]), .A2(n_1_0_644), .B1( + n_1_0_640), .B2(registers_26__ap[25]), .C1(n_1_0_622), .C2( + registers_30__ap[25]), .ZN(n_1_0_489)); + NAND2_X1_LVT i_1_0_514 (.A1(n_1_0_490), .A2(n_1_0_489), .ZN(n_1_0_488)); + AOI221_X1_LVT i_1_0_513 (.A(n_1_0_488), .B1(n_1_0_649), .B2( + registers_29__ap[25]), .C1(registers_2__ap[25]), .C2(n_1_0_618), .ZN( + n_1_0_487)); + AOI22_X1_LVT i_1_0_512 (.A1(registers_12__ap[25]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[25]), .ZN(n_1_0_486)); + AOI22_X1_LVT i_1_0_511 (.A1(registers_22__ap[25]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[25]), .ZN(n_1_0_485)); + AOI22_X1_LVT i_1_0_510 (.A1(registers_4__ap[25]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[25]), .ZN(n_1_0_484)); + NAND3_X1_LVT i_1_0_509 (.A1(n_1_0_486), .A2(n_1_0_485), .A3(n_1_0_484), + .ZN(n_1_0_483)); + AOI221_X1_LVT i_1_0_508 (.A(n_1_0_483), .B1(n_1_0_633), .B2( + registers_19__ap[25]), .C1(registers_18__ap[25]), .C2(n_1_0_646), .ZN( + n_1_0_482)); + AOI22_X1_LVT i_1_0_507 (.A1(registers_15__ap[25]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[25]), .ZN(n_1_0_481)); + AOI22_X1_LVT i_1_0_506 (.A1(registers_23__ap[25]), .A2(n_1_0_615), .B1( + n_1_0_610), .B2(registers_3__ap[25]), .ZN(n_1_0_480)); + AOI22_X1_LVT i_1_0_505 (.A1(registers_13__ap[25]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[25]), .ZN(n_1_0_479)); + NAND3_X1_LVT i_1_0_504 (.A1(n_1_0_481), .A2(n_1_0_480), .A3(n_1_0_479), + .ZN(n_1_0_478)); + AOI221_X1_LVT i_1_0_503 (.A(n_1_0_478), .B1(n_1_0_636), .B2( + registers_27__ap[25]), .C1(registers_31__ap[25]), .C2(n_1_0_637), .ZN( + n_1_0_477)); + NAND4_X1_LVT i_1_0_502 (.A1(n_1_0_494), .A2(n_1_0_487), .A3(n_1_0_482), + .A4(n_1_0_477), .ZN(RRs2[25])); + AOI22_X1_LVT i_1_0_501 (.A1(registers_17__ap[24]), .A2(n_1_0_629), .B1( + n_1_0_612), .B2(registers_21__ap[24]), .ZN(n_1_0_476)); + AOI222_X1_LVT i_1_0_500 (.A1(registers_13__ap[24]), .A2(n_1_0_631), .B1( + n_1_0_622), .B2(registers_30__ap[24]), .C1(registers_26__ap[24]), .C2( + n_1_0_640), .ZN(n_1_0_475)); + AOI22_X1_LVT i_1_0_499 (.A1(registers_1__ap[24]), .A2(n_1_0_644), .B1( + n_1_0_634), .B2(registers_28__ap[24]), .ZN(n_1_0_474)); + AOI22_X1_LVT i_1_0_498 (.A1(registers_24__ap[24]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[24]), .ZN(n_1_0_473)); + AOI22_X1_LVT i_1_0_497 (.A1(registers_8__ap[24]), .A2(n_1_0_626), .B1( + n_1_0_616), .B2(registers_6__ap[24]), .ZN(n_1_0_472)); + AOI22_X1_LVT i_1_0_496 (.A1(registers_4__ap[24]), .A2(n_1_0_638), .B1( + n_1_0_611), .B2(registers_11__ap[24]), .ZN(n_1_0_471)); + AOI22_X1_LVT i_1_0_495 (.A1(registers_10__ap[24]), .A2(n_1_0_624), .B1( + n_1_0_618), .B2(registers_2__ap[24]), .ZN(n_1_0_470)); + NAND4_X1_LVT i_1_0_494 (.A1(n_1_0_473), .A2(n_1_0_472), .A3(n_1_0_471), + .A4(n_1_0_470), .ZN(n_1_0_469)); + AOI22_X1_LVT i_1_0_493 (.A1(registers_18__ap[24]), .A2(n_1_0_646), .B1( + n_1_0_633), .B2(registers_19__ap[24]), .ZN(n_1_0_468)); + AOI22_X1_LVT i_1_0_492 (.A1(registers_5__ap[24]), .A2(n_1_0_635), .B1( + n_1_0_632), .B2(registers_12__ap[24]), .ZN(n_1_0_467)); + AOI22_X1_LVT i_1_0_491 (.A1(registers_15__ap[24]), .A2(n_1_0_627), .B1( + n_1_0_614), .B2(registers_16__ap[24]), .ZN(n_1_0_466)); + AOI22_X1_LVT i_1_0_490 (.A1(registers_22__ap[24]), .A2(n_1_0_642), .B1( + n_1_0_620), .B2(registers_25__ap[24]), .ZN(n_1_0_465)); + NAND4_X1_LVT i_1_0_489 (.A1(n_1_0_468), .A2(n_1_0_467), .A3(n_1_0_466), + .A4(n_1_0_465), .ZN(n_1_0_464)); + AOI22_X1_LVT i_1_0_488 (.A1(registers_29__ap[24]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[24]), .ZN(n_1_0_463)); + AOI22_X1_LVT i_1_0_487 (.A1(registers_7__ap[24]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[24]), .ZN(n_1_0_462)); + AOI22_X1_LVT i_1_0_486 (.A1(registers_23__ap[24]), .A2(n_1_0_615), .B1( + n_1_0_610), .B2(registers_3__ap[24]), .ZN(n_1_0_461)); + AOI22_X1_LVT i_1_0_485 (.A1(registers_31__ap[24]), .A2(n_1_0_637), .B1( + n_1_0_636), .B2(registers_27__ap[24]), .ZN(n_1_0_460)); + NAND4_X1_LVT i_1_0_484 (.A1(n_1_0_463), .A2(n_1_0_462), .A3(n_1_0_461), + .A4(n_1_0_460), .ZN(n_1_0_459)); + NOR3_X1_LVT i_1_0_483 (.A1(n_1_0_469), .A2(n_1_0_464), .A3(n_1_0_459), + .ZN(n_1_0_458)); + NAND4_X1_LVT i_1_0_482 (.A1(n_1_0_476), .A2(n_1_0_475), .A3(n_1_0_474), + .A4(n_1_0_458), .ZN(RRs2[24])); + AOI22_X1_LVT i_1_0_481 (.A1(registers_4__ap[23]), .A2(n_1_0_638), .B1( + n_1_0_634), .B2(registers_28__ap[23]), .ZN(n_1_0_457)); + AOI222_X1_LVT i_1_0_480 (.A1(registers_18__ap[23]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[23]), .C1(n_1_0_644), .C2( + registers_1__ap[23]), .ZN(n_1_0_456)); + AOI22_X1_LVT i_1_0_479 (.A1(registers_29__ap[23]), .A2(n_1_0_649), .B1( + n_1_0_618), .B2(registers_2__ap[23]), .ZN(n_1_0_455)); + AOI22_X1_LVT i_1_0_478 (.A1(registers_14__ap[23]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[23]), .ZN(n_1_0_454)); + AOI22_X1_LVT i_1_0_477 (.A1(registers_16__ap[23]), .A2(n_1_0_614), .B1( + n_1_0_611), .B2(registers_11__ap[23]), .ZN(n_1_0_453)); + AOI22_X1_LVT i_1_0_476 (.A1(registers_27__ap[23]), .A2(n_1_0_636), .B1( + n_1_0_620), .B2(registers_25__ap[23]), .ZN(n_1_0_452)); + AOI22_X1_LVT i_1_0_475 (.A1(registers_31__ap[23]), .A2(n_1_0_637), .B1( + n_1_0_616), .B2(registers_6__ap[23]), .ZN(n_1_0_451)); + NAND4_X1_LVT i_1_0_474 (.A1(n_1_0_454), .A2(n_1_0_453), .A3(n_1_0_452), + .A4(n_1_0_451), .ZN(n_1_0_450)); + AOI22_X1_LVT i_1_0_473 (.A1(registers_26__ap[23]), .A2(n_1_0_640), .B1( + n_1_0_633), .B2(registers_19__ap[23]), .ZN(n_1_0_449)); + AOI22_X1_LVT i_1_0_472 (.A1(registers_12__ap[23]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[23]), .ZN(n_1_0_448)); + AOI22_X1_LVT i_1_0_471 (.A1(registers_22__ap[23]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[23]), .ZN(n_1_0_447)); + AOI22_X1_LVT i_1_0_470 (.A1(registers_5__ap[23]), .A2(n_1_0_635), .B1( + n_1_0_613), .B2(registers_20__ap[23]), .ZN(n_1_0_446)); + NAND4_X1_LVT i_1_0_469 (.A1(n_1_0_449), .A2(n_1_0_448), .A3(n_1_0_447), + .A4(n_1_0_446), .ZN(n_1_0_445)); + AOI22_X1_LVT i_1_0_468 (.A1(registers_15__ap[23]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[23]), .ZN(n_1_0_444)); + AOI22_X1_LVT i_1_0_467 (.A1(registers_8__ap[23]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[23]), .ZN(n_1_0_443)); + AOI22_X1_LVT i_1_0_466 (.A1(registers_13__ap[23]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[23]), .ZN(n_1_0_442)); + AOI22_X1_LVT i_1_0_465 (.A1(registers_10__ap[23]), .A2(n_1_0_624), .B1( + n_1_0_610), .B2(registers_3__ap[23]), .ZN(n_1_0_441)); + NAND4_X1_LVT i_1_0_464 (.A1(n_1_0_444), .A2(n_1_0_443), .A3(n_1_0_442), + .A4(n_1_0_441), .ZN(n_1_0_440)); + NOR3_X1_LVT i_1_0_463 (.A1(n_1_0_450), .A2(n_1_0_445), .A3(n_1_0_440), + .ZN(n_1_0_439)); + NAND4_X1_LVT i_1_0_462 (.A1(n_1_0_457), .A2(n_1_0_456), .A3(n_1_0_455), + .A4(n_1_0_439), .ZN(RRs2[23])); + AOI22_X1_LVT i_1_0_460 (.A1(registers_17__ap[22]), .A2(n_1_0_629), .B1( + n_1_0_612), .B2(registers_21__ap[22]), .ZN(n_1_0_437)); + AOI22_X1_LVT i_1_0_461 (.A1(registers_15__ap[22]), .A2(n_1_0_627), .B1( + n_1_0_626), .B2(registers_8__ap[22]), .ZN(n_1_0_438)); + AOI22_X1_LVT i_1_0_459 (.A1(registers_24__ap[22]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[22]), .ZN(n_1_0_436)); + AOI22_X1_LVT i_1_0_458 (.A1(registers_5__ap[22]), .A2(n_1_0_635), .B1( + n_1_0_611), .B2(registers_11__ap[22]), .ZN(n_1_0_435)); + NAND3_X1_LVT i_1_0_457 (.A1(n_1_0_438), .A2(n_1_0_436), .A3(n_1_0_435), + .ZN(n_1_0_434)); + AOI221_X1_LVT i_1_0_456 (.A(n_1_0_434), .B1(n_1_0_618), .B2( + registers_2__ap[22]), .C1(registers_10__ap[22]), .C2(n_1_0_624), .ZN( + n_1_0_433)); + AOI222_X1_LVT i_1_0_455 (.A1(registers_26__ap[22]), .A2(n_1_0_640), .B1( + n_1_0_622), .B2(registers_30__ap[22]), .C1(n_1_0_631), .C2( + registers_13__ap[22]), .ZN(n_1_0_432)); + NAND2_X1_LVT i_1_0_454 (.A1(n_1_0_433), .A2(n_1_0_432), .ZN(n_1_0_431)); + AOI221_X1_LVT i_1_0_453 (.A(n_1_0_431), .B1(n_1_0_644), .B2( + registers_1__ap[22]), .C1(registers_28__ap[22]), .C2(n_1_0_634), .ZN( + n_1_0_430)); + AOI22_X1_LVT i_1_0_452 (.A1(registers_18__ap[22]), .A2(n_1_0_646), .B1( + n_1_0_633), .B2(registers_19__ap[22]), .ZN(n_1_0_429)); + AOI22_X1_LVT i_1_0_451 (.A1(registers_4__ap[22]), .A2(n_1_0_638), .B1( + n_1_0_632), .B2(registers_12__ap[22]), .ZN(n_1_0_428)); + AOI22_X1_LVT i_1_0_450 (.A1(registers_6__ap[22]), .A2(n_1_0_616), .B1( + n_1_0_614), .B2(registers_16__ap[22]), .ZN(n_1_0_427)); + NAND3_X1_LVT i_1_0_449 (.A1(n_1_0_429), .A2(n_1_0_428), .A3(n_1_0_427), + .ZN(n_1_0_426)); + AOI221_X1_LVT i_1_0_448 (.A(n_1_0_426), .B1(n_1_0_620), .B2( + registers_25__ap[22]), .C1(registers_22__ap[22]), .C2(n_1_0_642), .ZN( + n_1_0_425)); + AOI22_X1_LVT i_1_0_447 (.A1(registers_29__ap[22]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[22]), .ZN(n_1_0_424)); + AOI22_X1_LVT i_1_0_446 (.A1(registers_7__ap[22]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[22]), .ZN(n_1_0_423)); + AOI22_X1_LVT i_1_0_445 (.A1(registers_23__ap[22]), .A2(n_1_0_615), .B1( + n_1_0_610), .B2(registers_3__ap[22]), .ZN(n_1_0_422)); + NAND3_X1_LVT i_1_0_444 (.A1(n_1_0_424), .A2(n_1_0_423), .A3(n_1_0_422), + .ZN(n_1_0_421)); + AOI221_X1_LVT i_1_0_443 (.A(n_1_0_421), .B1(n_1_0_636), .B2( + registers_27__ap[22]), .C1(registers_31__ap[22]), .C2(n_1_0_637), .ZN( + n_1_0_420)); + NAND4_X1_LVT i_1_0_442 (.A1(n_1_0_437), .A2(n_1_0_430), .A3(n_1_0_425), + .A4(n_1_0_420), .ZN(RRs2[22])); + AOI22_X1_LVT i_1_0_441 (.A1(registers_5__ap[21]), .A2(n_1_0_635), .B1( + n_1_0_634), .B2(registers_28__ap[21]), .ZN(n_1_0_419)); + AOI222_X1_LVT i_1_0_440 (.A1(registers_1__ap[21]), .A2(n_1_0_644), .B1( + n_1_0_640), .B2(registers_26__ap[21]), .C1(n_1_0_622), .C2( + registers_30__ap[21]), .ZN(n_1_0_418)); + AOI22_X1_LVT i_1_0_439 (.A1(registers_29__ap[21]), .A2(n_1_0_649), .B1( + n_1_0_618), .B2(registers_2__ap[21]), .ZN(n_1_0_417)); + AOI22_X1_LVT i_1_0_438 (.A1(registers_14__ap[21]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[21]), .ZN(n_1_0_416)); + AOI22_X1_LVT i_1_0_437 (.A1(registers_8__ap[21]), .A2(n_1_0_626), .B1( + n_1_0_614), .B2(registers_16__ap[21]), .ZN(n_1_0_415)); + AOI22_X1_LVT i_1_0_436 (.A1(registers_25__ap[21]), .A2(n_1_0_620), .B1( + n_1_0_611), .B2(registers_11__ap[21]), .ZN(n_1_0_414)); + AOI22_X1_LVT i_1_0_435 (.A1(registers_10__ap[21]), .A2(n_1_0_624), .B1( + n_1_0_616), .B2(registers_6__ap[21]), .ZN(n_1_0_413)); + NAND4_X1_LVT i_1_0_434 (.A1(n_1_0_416), .A2(n_1_0_415), .A3(n_1_0_414), + .A4(n_1_0_413), .ZN(n_1_0_412)); + AOI22_X1_LVT i_1_0_433 (.A1(registers_12__ap[21]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[21]), .ZN(n_1_0_411)); + AOI22_X1_LVT i_1_0_432 (.A1(registers_22__ap[21]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[21]), .ZN(n_1_0_410)); + AOI22_X1_LVT i_1_0_431 (.A1(registers_4__ap[21]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[21]), .ZN(n_1_0_409)); + AOI22_X1_LVT i_1_0_430 (.A1(registers_18__ap[21]), .A2(n_1_0_646), .B1( + n_1_0_633), .B2(registers_19__ap[21]), .ZN(n_1_0_408)); + NAND4_X1_LVT i_1_0_429 (.A1(n_1_0_411), .A2(n_1_0_410), .A3(n_1_0_409), + .A4(n_1_0_408), .ZN(n_1_0_407)); + AOI22_X1_LVT i_1_0_428 (.A1(registers_15__ap[21]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[21]), .ZN(n_1_0_406)); + AOI22_X1_LVT i_1_0_427 (.A1(registers_23__ap[21]), .A2(n_1_0_615), .B1( + n_1_0_610), .B2(registers_3__ap[21]), .ZN(n_1_0_405)); + AOI22_X1_LVT i_1_0_426 (.A1(registers_13__ap[21]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[21]), .ZN(n_1_0_404)); + AOI22_X1_LVT i_1_0_425 (.A1(registers_31__ap[21]), .A2(n_1_0_637), .B1( + n_1_0_636), .B2(registers_27__ap[21]), .ZN(n_1_0_403)); + NAND4_X1_LVT i_1_0_424 (.A1(n_1_0_406), .A2(n_1_0_405), .A3(n_1_0_404), + .A4(n_1_0_403), .ZN(n_1_0_402)); + NOR3_X1_LVT i_1_0_423 (.A1(n_1_0_412), .A2(n_1_0_407), .A3(n_1_0_402), + .ZN(n_1_0_401)); + NAND4_X1_LVT i_1_0_422 (.A1(n_1_0_419), .A2(n_1_0_418), .A3(n_1_0_417), + .A4(n_1_0_401), .ZN(RRs2[21])); + AOI22_X1_LVT i_1_0_421 (.A1(registers_17__ap[20]), .A2(n_1_0_629), .B1( + n_1_0_612), .B2(registers_21__ap[20]), .ZN(n_1_0_400)); + AOI222_X1_LVT i_1_0_420 (.A1(registers_13__ap[20]), .A2(n_1_0_631), .B1( + n_1_0_622), .B2(registers_30__ap[20]), .C1(registers_19__ap[20]), .C2( + n_1_0_633), .ZN(n_1_0_399)); + AOI22_X1_LVT i_1_0_419 (.A1(registers_1__ap[20]), .A2(n_1_0_644), .B1( + n_1_0_634), .B2(registers_28__ap[20]), .ZN(n_1_0_398)); + AOI22_X1_LVT i_1_0_418 (.A1(registers_24__ap[20]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[20]), .ZN(n_1_0_397)); + AOI22_X1_LVT i_1_0_417 (.A1(registers_6__ap[20]), .A2(n_1_0_616), .B1( + n_1_0_611), .B2(registers_11__ap[20]), .ZN(n_1_0_396)); + AOI22_X1_LVT i_1_0_416 (.A1(registers_4__ap[20]), .A2(n_1_0_638), .B1( + n_1_0_624), .B2(registers_10__ap[20]), .ZN(n_1_0_395)); + AOI22_X1_LVT i_1_0_415 (.A1(registers_31__ap[20]), .A2(n_1_0_637), .B1( + n_1_0_618), .B2(registers_2__ap[20]), .ZN(n_1_0_394)); + NAND4_X1_LVT i_1_0_414 (.A1(n_1_0_397), .A2(n_1_0_396), .A3(n_1_0_395), + .A4(n_1_0_394), .ZN(n_1_0_393)); + AOI22_X1_LVT i_1_0_413 (.A1(registers_18__ap[20]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[20]), .ZN(n_1_0_392)); + AOI22_X1_LVT i_1_0_412 (.A1(registers_5__ap[20]), .A2(n_1_0_635), .B1( + n_1_0_632), .B2(registers_12__ap[20]), .ZN(n_1_0_391)); + AOI22_X1_LVT i_1_0_411 (.A1(registers_15__ap[20]), .A2(n_1_0_627), .B1( + n_1_0_614), .B2(registers_16__ap[20]), .ZN(n_1_0_390)); + AOI22_X1_LVT i_1_0_410 (.A1(registers_22__ap[20]), .A2(n_1_0_642), .B1( + n_1_0_620), .B2(registers_25__ap[20]), .ZN(n_1_0_389)); + NAND4_X1_LVT i_1_0_409 (.A1(n_1_0_392), .A2(n_1_0_391), .A3(n_1_0_390), + .A4(n_1_0_389), .ZN(n_1_0_388)); + AOI22_X1_LVT i_1_0_408 (.A1(registers_29__ap[20]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[20]), .ZN(n_1_0_387)); + AOI22_X1_LVT i_1_0_407 (.A1(registers_7__ap[20]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[20]), .ZN(n_1_0_386)); + AOI22_X1_LVT i_1_0_406 (.A1(registers_8__ap[20]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[20]), .ZN(n_1_0_385)); + AOI22_X1_LVT i_1_0_405 (.A1(registers_27__ap[20]), .A2(n_1_0_636), .B1( + n_1_0_610), .B2(registers_3__ap[20]), .ZN(n_1_0_384)); + NAND4_X1_LVT i_1_0_404 (.A1(n_1_0_387), .A2(n_1_0_386), .A3(n_1_0_385), + .A4(n_1_0_384), .ZN(n_1_0_383)); + NOR3_X1_LVT i_1_0_403 (.A1(n_1_0_393), .A2(n_1_0_388), .A3(n_1_0_383), + .ZN(n_1_0_382)); + NAND4_X1_LVT i_1_0_402 (.A1(n_1_0_400), .A2(n_1_0_399), .A3(n_1_0_398), + .A4(n_1_0_382), .ZN(RRs2[20])); + AOI22_X1_LVT i_1_0_401 (.A1(registers_17__ap[19]), .A2(n_1_0_629), .B1( + n_1_0_612), .B2(registers_21__ap[19]), .ZN(n_1_0_381)); + AOI222_X1_LVT i_1_0_400 (.A1(registers_13__ap[19]), .A2(n_1_0_631), .B1( + n_1_0_622), .B2(registers_30__ap[19]), .C1(registers_19__ap[19]), .C2( + n_1_0_633), .ZN(n_1_0_380)); + AOI22_X1_LVT i_1_0_399 (.A1(registers_1__ap[19]), .A2(n_1_0_644), .B1( + n_1_0_634), .B2(registers_28__ap[19]), .ZN(n_1_0_379)); + AOI22_X1_LVT i_1_0_398 (.A1(registers_24__ap[19]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[19]), .ZN(n_1_0_378)); + AOI22_X1_LVT i_1_0_397 (.A1(registers_15__ap[19]), .A2(n_1_0_627), .B1( + n_1_0_611), .B2(registers_11__ap[19]), .ZN(n_1_0_377)); + AOI22_X1_LVT i_1_0_396 (.A1(registers_4__ap[19]), .A2(n_1_0_638), .B1( + n_1_0_636), .B2(registers_27__ap[19]), .ZN(n_1_0_376)); + AOI22_X1_LVT i_1_0_395 (.A1(registers_31__ap[19]), .A2(n_1_0_637), .B1( + n_1_0_618), .B2(registers_2__ap[19]), .ZN(n_1_0_375)); + NAND4_X1_LVT i_1_0_394 (.A1(n_1_0_378), .A2(n_1_0_377), .A3(n_1_0_376), + .A4(n_1_0_375), .ZN(n_1_0_374)); + AOI22_X1_LVT i_1_0_393 (.A1(registers_18__ap[19]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[19]), .ZN(n_1_0_373)); + AOI22_X1_LVT i_1_0_392 (.A1(registers_5__ap[19]), .A2(n_1_0_635), .B1( + n_1_0_632), .B2(registers_12__ap[19]), .ZN(n_1_0_372)); + AOI22_X1_LVT i_1_0_391 (.A1(registers_25__ap[19]), .A2(n_1_0_620), .B1( + n_1_0_616), .B2(registers_6__ap[19]), .ZN(n_1_0_371)); + AOI22_X1_LVT i_1_0_390 (.A1(registers_22__ap[19]), .A2(n_1_0_642), .B1( + n_1_0_614), .B2(registers_16__ap[19]), .ZN(n_1_0_370)); + NAND4_X1_LVT i_1_0_389 (.A1(n_1_0_373), .A2(n_1_0_372), .A3(n_1_0_371), + .A4(n_1_0_370), .ZN(n_1_0_369)); + AOI22_X1_LVT i_1_0_388 (.A1(registers_29__ap[19]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[19]), .ZN(n_1_0_368)); + AOI22_X1_LVT i_1_0_387 (.A1(registers_7__ap[19]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[19]), .ZN(n_1_0_367)); + AOI22_X1_LVT i_1_0_386 (.A1(registers_8__ap[19]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[19]), .ZN(n_1_0_366)); + AOI22_X1_LVT i_1_0_385 (.A1(registers_10__ap[19]), .A2(n_1_0_624), .B1( + n_1_0_610), .B2(registers_3__ap[19]), .ZN(n_1_0_365)); + NAND4_X1_LVT i_1_0_384 (.A1(n_1_0_368), .A2(n_1_0_367), .A3(n_1_0_366), + .A4(n_1_0_365), .ZN(n_1_0_364)); + NOR3_X1_LVT i_1_0_383 (.A1(n_1_0_374), .A2(n_1_0_369), .A3(n_1_0_364), + .ZN(n_1_0_363)); + NAND4_X1_LVT i_1_0_382 (.A1(n_1_0_381), .A2(n_1_0_380), .A3(n_1_0_379), + .A4(n_1_0_363), .ZN(RRs2[19])); + AOI22_X1_LVT i_1_0_380 (.A1(registers_4__ap[18]), .A2(n_1_0_638), .B1( + n_1_0_634), .B2(registers_28__ap[18]), .ZN(n_1_0_361)); + AOI22_X1_LVT i_1_0_381 (.A1(registers_8__ap[18]), .A2(n_1_0_626), .B1( + n_1_0_614), .B2(registers_16__ap[18]), .ZN(n_1_0_362)); + AOI22_X1_LVT i_1_0_379 (.A1(registers_14__ap[18]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[18]), .ZN(n_1_0_360)); + AOI22_X1_LVT i_1_0_378 (.A1(registers_25__ap[18]), .A2(n_1_0_620), .B1( + n_1_0_611), .B2(registers_11__ap[18]), .ZN(n_1_0_359)); + NAND3_X1_LVT i_1_0_377 (.A1(n_1_0_362), .A2(n_1_0_360), .A3(n_1_0_359), + .ZN(n_1_0_358)); + AOI221_X1_LVT i_1_0_376 (.A(n_1_0_358), .B1(n_1_0_624), .B2( + registers_10__ap[18]), .C1(registers_6__ap[18]), .C2(n_1_0_616), .ZN( + n_1_0_357)); + AOI222_X1_LVT i_1_0_375 (.A1(registers_1__ap[18]), .A2(n_1_0_644), .B1( + n_1_0_640), .B2(registers_26__ap[18]), .C1(n_1_0_622), .C2( + registers_30__ap[18]), .ZN(n_1_0_356)); + NAND2_X1_LVT i_1_0_374 (.A1(n_1_0_357), .A2(n_1_0_356), .ZN(n_1_0_355)); + AOI221_X1_LVT i_1_0_373 (.A(n_1_0_355), .B1(n_1_0_649), .B2( + registers_29__ap[18]), .C1(registers_2__ap[18]), .C2(n_1_0_618), .ZN( + n_1_0_354)); + AOI22_X1_LVT i_1_0_372 (.A1(registers_18__ap[18]), .A2(n_1_0_646), .B1( + n_1_0_633), .B2(registers_19__ap[18]), .ZN(n_1_0_353)); + AOI22_X1_LVT i_1_0_371 (.A1(registers_12__ap[18]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[18]), .ZN(n_1_0_352)); + AOI22_X1_LVT i_1_0_370 (.A1(registers_22__ap[18]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[18]), .ZN(n_1_0_351)); + NAND3_X1_LVT i_1_0_369 (.A1(n_1_0_353), .A2(n_1_0_352), .A3(n_1_0_351), + .ZN(n_1_0_350)); + AOI221_X1_LVT i_1_0_368 (.A(n_1_0_350), .B1(n_1_0_635), .B2( + registers_5__ap[18]), .C1(registers_20__ap[18]), .C2(n_1_0_613), .ZN( + n_1_0_349)); + AOI22_X1_LVT i_1_0_367 (.A1(registers_15__ap[18]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[18]), .ZN(n_1_0_348)); + AOI22_X1_LVT i_1_0_366 (.A1(registers_23__ap[18]), .A2(n_1_0_615), .B1( + n_1_0_610), .B2(registers_3__ap[18]), .ZN(n_1_0_347)); + AOI22_X1_LVT i_1_0_365 (.A1(registers_13__ap[18]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[18]), .ZN(n_1_0_346)); + NAND3_X1_LVT i_1_0_364 (.A1(n_1_0_348), .A2(n_1_0_347), .A3(n_1_0_346), + .ZN(n_1_0_345)); + AOI221_X1_LVT i_1_0_363 (.A(n_1_0_345), .B1(n_1_0_637), .B2( + registers_31__ap[18]), .C1(registers_27__ap[18]), .C2(n_1_0_636), .ZN( + n_1_0_344)); + NAND4_X1_LVT i_1_0_362 (.A1(n_1_0_361), .A2(n_1_0_354), .A3(n_1_0_349), + .A4(n_1_0_344), .ZN(RRs2[18])); + AOI22_X1_LVT i_1_0_358 (.A1(registers_4__ap[17]), .A2(n_1_0_638), .B1( + n_1_0_634), .B2(registers_28__ap[17]), .ZN(n_1_0_340)); + AOI22_X1_LVT i_1_0_361 (.A1(registers_31__ap[17]), .A2(n_1_0_637), .B1( + n_1_0_616), .B2(registers_6__ap[17]), .ZN(n_1_0_343)); + AOI22_X1_LVT i_1_0_357 (.A1(registers_14__ap[17]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[17]), .ZN(n_1_0_339)); + AOI22_X1_LVT i_1_0_360 (.A1(registers_25__ap[17]), .A2(n_1_0_620), .B1( + n_1_0_611), .B2(registers_11__ap[17]), .ZN(n_1_0_342)); + INV_X1_LVT i_1_0_359 (.A(n_1_0_342), .ZN(n_1_0_341)); + AOI221_X1_LVT i_1_0_356 (.A(n_1_0_341), .B1(n_1_0_614), .B2( + registers_16__ap[17]), .C1(registers_10__ap[17]), .C2(n_1_0_624), .ZN( + n_1_0_338)); + AOI222_X1_LVT i_1_0_355 (.A1(registers_1__ap[17]), .A2(n_1_0_644), .B1( + n_1_0_622), .B2(registers_30__ap[17]), .C1(registers_18__ap[17]), .C2( + n_1_0_646), .ZN(n_1_0_337)); + NAND4_X1_LVT i_1_0_354 (.A1(n_1_0_343), .A2(n_1_0_339), .A3(n_1_0_338), + .A4(n_1_0_337), .ZN(n_1_0_336)); + AOI221_X1_LVT i_1_0_353 (.A(n_1_0_336), .B1(n_1_0_649), .B2( + registers_29__ap[17]), .C1(registers_2__ap[17]), .C2(n_1_0_618), .ZN( + n_1_0_335)); + AOI22_X1_LVT i_1_0_352 (.A1(registers_26__ap[17]), .A2(n_1_0_640), .B1( + n_1_0_633), .B2(registers_19__ap[17]), .ZN(n_1_0_334)); + AOI22_X1_LVT i_1_0_351 (.A1(registers_12__ap[17]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[17]), .ZN(n_1_0_333)); + AOI22_X1_LVT i_1_0_350 (.A1(registers_22__ap[17]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[17]), .ZN(n_1_0_332)); + NAND3_X1_LVT i_1_0_349 (.A1(n_1_0_334), .A2(n_1_0_333), .A3(n_1_0_332), + .ZN(n_1_0_331)); + AOI221_X1_LVT i_1_0_348 (.A(n_1_0_331), .B1(n_1_0_635), .B2( + registers_5__ap[17]), .C1(registers_20__ap[17]), .C2(n_1_0_613), .ZN( + n_1_0_330)); + AOI22_X1_LVT i_1_0_347 (.A1(registers_15__ap[17]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[17]), .ZN(n_1_0_329)); + AOI22_X1_LVT i_1_0_346 (.A1(registers_8__ap[17]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[17]), .ZN(n_1_0_328)); + AOI22_X1_LVT i_1_0_345 (.A1(registers_13__ap[17]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[17]), .ZN(n_1_0_327)); + NAND3_X1_LVT i_1_0_344 (.A1(n_1_0_329), .A2(n_1_0_328), .A3(n_1_0_327), + .ZN(n_1_0_326)); + AOI221_X1_LVT i_1_0_343 (.A(n_1_0_326), .B1(n_1_0_636), .B2( + registers_27__ap[17]), .C1(registers_3__ap[17]), .C2(n_1_0_610), .ZN( + n_1_0_325)); + NAND4_X1_LVT i_1_0_342 (.A1(n_1_0_340), .A2(n_1_0_335), .A3(n_1_0_330), + .A4(n_1_0_325), .ZN(RRs2[17])); + AOI22_X1_LVT i_1_0_341 (.A1(registers_4__ap[16]), .A2(n_1_0_638), .B1( + n_1_0_634), .B2(registers_28__ap[16]), .ZN(n_1_0_324)); + AOI222_X1_LVT i_1_0_340 (.A1(registers_1__ap[16]), .A2(n_1_0_644), .B1( + n_1_0_633), .B2(registers_19__ap[16]), .C1(n_1_0_622), .C2( + registers_30__ap[16]), .ZN(n_1_0_323)); + AOI22_X1_LVT i_1_0_339 (.A1(registers_29__ap[16]), .A2(n_1_0_649), .B1( + n_1_0_618), .B2(registers_2__ap[16]), .ZN(n_1_0_322)); + AOI22_X1_LVT i_1_0_338 (.A1(registers_14__ap[16]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[16]), .ZN(n_1_0_321)); + AOI22_X1_LVT i_1_0_337 (.A1(registers_16__ap[16]), .A2(n_1_0_614), .B1( + n_1_0_611), .B2(registers_11__ap[16]), .ZN(n_1_0_320)); + AOI22_X1_LVT i_1_0_336 (.A1(registers_10__ap[16]), .A2(n_1_0_624), .B1( + n_1_0_620), .B2(registers_25__ap[16]), .ZN(n_1_0_319)); + AOI22_X1_LVT i_1_0_335 (.A1(registers_31__ap[16]), .A2(n_1_0_637), .B1( + n_1_0_616), .B2(registers_6__ap[16]), .ZN(n_1_0_318)); + NAND4_X1_LVT i_1_0_334 (.A1(n_1_0_321), .A2(n_1_0_320), .A3(n_1_0_319), + .A4(n_1_0_318), .ZN(n_1_0_317)); + AOI22_X1_LVT i_1_0_333 (.A1(registers_18__ap[16]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[16]), .ZN(n_1_0_316)); + AOI22_X1_LVT i_1_0_332 (.A1(registers_12__ap[16]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[16]), .ZN(n_1_0_315)); + AOI22_X1_LVT i_1_0_331 (.A1(registers_22__ap[16]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[16]), .ZN(n_1_0_314)); + AOI22_X1_LVT i_1_0_330 (.A1(registers_5__ap[16]), .A2(n_1_0_635), .B1( + n_1_0_613), .B2(registers_20__ap[16]), .ZN(n_1_0_313)); + NAND4_X1_LVT i_1_0_329 (.A1(n_1_0_316), .A2(n_1_0_315), .A3(n_1_0_314), + .A4(n_1_0_313), .ZN(n_1_0_312)); + AOI22_X1_LVT i_1_0_328 (.A1(registers_15__ap[16]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[16]), .ZN(n_1_0_311)); + AOI22_X1_LVT i_1_0_327 (.A1(registers_8__ap[16]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[16]), .ZN(n_1_0_310)); + AOI22_X1_LVT i_1_0_326 (.A1(registers_13__ap[16]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[16]), .ZN(n_1_0_309)); + AOI22_X1_LVT i_1_0_325 (.A1(registers_27__ap[16]), .A2(n_1_0_636), .B1( + n_1_0_610), .B2(registers_3__ap[16]), .ZN(n_1_0_308)); + NAND4_X1_LVT i_1_0_324 (.A1(n_1_0_311), .A2(n_1_0_310), .A3(n_1_0_309), + .A4(n_1_0_308), .ZN(n_1_0_307)); + NOR3_X1_LVT i_1_0_323 (.A1(n_1_0_317), .A2(n_1_0_312), .A3(n_1_0_307), + .ZN(n_1_0_306)); + NAND4_X1_LVT i_1_0_322 (.A1(n_1_0_324), .A2(n_1_0_323), .A3(n_1_0_322), + .A4(n_1_0_306), .ZN(RRs2[16])); + AOI22_X1_LVT i_1_0_320 (.A1(registers_5__ap[15]), .A2(n_1_0_635), .B1( + n_1_0_634), .B2(registers_28__ap[15]), .ZN(n_1_0_304)); + AOI22_X1_LVT i_1_0_321 (.A1(registers_8__ap[15]), .A2(n_1_0_626), .B1( + n_1_0_620), .B2(registers_25__ap[15]), .ZN(n_1_0_305)); + AOI22_X1_LVT i_1_0_319 (.A1(registers_14__ap[15]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[15]), .ZN(n_1_0_303)); + AOI22_X1_LVT i_1_0_318 (.A1(registers_16__ap[15]), .A2(n_1_0_614), .B1( + n_1_0_611), .B2(registers_11__ap[15]), .ZN(n_1_0_302)); + NAND3_X1_LVT i_1_0_317 (.A1(n_1_0_305), .A2(n_1_0_303), .A3(n_1_0_302), + .ZN(n_1_0_301)); + AOI221_X1_LVT i_1_0_316 (.A(n_1_0_301), .B1(n_1_0_616), .B2( + registers_6__ap[15]), .C1(registers_10__ap[15]), .C2(n_1_0_624), .ZN( + n_1_0_300)); + AOI222_X1_LVT i_1_0_315 (.A1(registers_1__ap[15]), .A2(n_1_0_644), .B1( + n_1_0_640), .B2(registers_26__ap[15]), .C1(n_1_0_622), .C2( + registers_30__ap[15]), .ZN(n_1_0_299)); + NAND2_X1_LVT i_1_0_314 (.A1(n_1_0_300), .A2(n_1_0_299), .ZN(n_1_0_298)); + AOI221_X1_LVT i_1_0_313 (.A(n_1_0_298), .B1(n_1_0_649), .B2( + registers_29__ap[15]), .C1(registers_2__ap[15]), .C2(n_1_0_618), .ZN( + n_1_0_297)); + AOI22_X1_LVT i_1_0_312 (.A1(registers_12__ap[15]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[15]), .ZN(n_1_0_296)); + AOI22_X1_LVT i_1_0_311 (.A1(registers_22__ap[15]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[15]), .ZN(n_1_0_295)); + AOI22_X1_LVT i_1_0_310 (.A1(registers_4__ap[15]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[15]), .ZN(n_1_0_294)); + NAND3_X1_LVT i_1_0_309 (.A1(n_1_0_296), .A2(n_1_0_295), .A3(n_1_0_294), + .ZN(n_1_0_293)); + AOI221_X1_LVT i_1_0_308 (.A(n_1_0_293), .B1(n_1_0_633), .B2( + registers_19__ap[15]), .C1(registers_18__ap[15]), .C2(n_1_0_646), .ZN( + n_1_0_292)); + AOI22_X1_LVT i_1_0_307 (.A1(registers_15__ap[15]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[15]), .ZN(n_1_0_291)); + AOI22_X1_LVT i_1_0_306 (.A1(registers_23__ap[15]), .A2(n_1_0_615), .B1( + n_1_0_610), .B2(registers_3__ap[15]), .ZN(n_1_0_290)); + AOI22_X1_LVT i_1_0_305 (.A1(registers_13__ap[15]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[15]), .ZN(n_1_0_289)); + NAND3_X1_LVT i_1_0_304 (.A1(n_1_0_291), .A2(n_1_0_290), .A3(n_1_0_289), + .ZN(n_1_0_288)); + AOI221_X1_LVT i_1_0_303 (.A(n_1_0_288), .B1(n_1_0_636), .B2( + registers_27__ap[15]), .C1(registers_31__ap[15]), .C2(n_1_0_637), .ZN( + n_1_0_287)); + NAND4_X1_LVT i_1_0_302 (.A1(n_1_0_304), .A2(n_1_0_297), .A3(n_1_0_292), + .A4(n_1_0_287), .ZN(RRs2[15])); + AOI22_X1_LVT i_1_0_301 (.A1(registers_28__ap[14]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[14]), .ZN(n_1_0_286)); + AOI222_X1_LVT i_1_0_300 (.A1(registers_18__ap[14]), .A2(n_1_0_646), .B1( + n_1_0_620), .B2(registers_25__ap[14]), .C1(n_1_0_618), .C2( + registers_2__ap[14]), .ZN(n_1_0_285)); + AOI22_X1_LVT i_1_0_299 (.A1(registers_24__ap[14]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[14]), .ZN(n_1_0_284)); + AOI22_X1_LVT i_1_0_298 (.A1(registers_15__ap[14]), .A2(n_1_0_627), .B1( + n_1_0_610), .B2(registers_3__ap[14]), .ZN(n_1_0_283)); + AOI22_X1_LVT i_1_0_297 (.A1(registers_4__ap[14]), .A2(n_1_0_638), .B1( + n_1_0_637), .B2(registers_31__ap[14]), .ZN(n_1_0_282)); + AOI22_X1_LVT i_1_0_296 (.A1(registers_29__ap[14]), .A2(n_1_0_649), .B1( + n_1_0_615), .B2(registers_23__ap[14]), .ZN(n_1_0_281)); + NAND4_X1_LVT i_1_0_295 (.A1(n_1_0_284), .A2(n_1_0_283), .A3(n_1_0_282), + .A4(n_1_0_281), .ZN(n_1_0_280)); + AOI221_X1_LVT i_1_0_294 (.A(n_1_0_280), .B1(n_1_0_644), .B2( + registers_1__ap[14]), .C1(registers_13__ap[14]), .C2(n_1_0_631), .ZN( + n_1_0_279)); + AOI22_X1_LVT i_1_0_293 (.A1(registers_17__ap[14]), .A2(n_1_0_629), .B1( + n_1_0_623), .B2(registers_7__ap[14]), .ZN(n_1_0_278)); + AOI22_X1_LVT i_1_0_292 (.A1(registers_5__ap[14]), .A2(n_1_0_635), .B1( + n_1_0_632), .B2(registers_12__ap[14]), .ZN(n_1_0_277)); + AOI22_X1_LVT i_1_0_291 (.A1(registers_10__ap[14]), .A2(n_1_0_624), .B1( + n_1_0_622), .B2(registers_30__ap[14]), .ZN(n_1_0_276)); + AOI22_X1_LVT i_1_0_290 (.A1(registers_26__ap[14]), .A2(n_1_0_640), .B1( + n_1_0_614), .B2(registers_16__ap[14]), .ZN(n_1_0_275)); + NAND4_X1_LVT i_1_0_289 (.A1(n_1_0_278), .A2(n_1_0_277), .A3(n_1_0_276), + .A4(n_1_0_275), .ZN(n_1_0_274)); + AOI22_X1_LVT i_1_0_288 (.A1(registers_9__ap[14]), .A2(n_1_0_617), .B1( + n_1_0_612), .B2(registers_21__ap[14]), .ZN(n_1_0_273)); + AOI22_X1_LVT i_1_0_287 (.A1(registers_14__ap[14]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[14]), .ZN(n_1_0_272)); + AOI22_X1_LVT i_1_0_286 (.A1(registers_22__ap[14]), .A2(n_1_0_642), .B1( + n_1_0_633), .B2(registers_19__ap[14]), .ZN(n_1_0_271)); + AOI22_X1_LVT i_1_0_285 (.A1(registers_27__ap[14]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[14]), .ZN(n_1_0_270)); + NAND4_X1_LVT i_1_0_284 (.A1(n_1_0_273), .A2(n_1_0_272), .A3(n_1_0_271), + .A4(n_1_0_270), .ZN(n_1_0_269)); + NOR2_X1_LVT i_1_0_283 (.A1(n_1_0_274), .A2(n_1_0_269), .ZN(n_1_0_268)); + NAND4_X1_LVT i_1_0_282 (.A1(n_1_0_286), .A2(n_1_0_285), .A3(n_1_0_279), + .A4(n_1_0_268), .ZN(RRs2[14])); + AOI22_X1_LVT i_1_0_281 (.A1(registers_18__ap[13]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[13]), .ZN(n_1_0_267)); + AOI22_X1_LVT i_1_0_280 (.A1(registers_12__ap[13]), .A2(n_1_0_632), .B1( + n_1_0_629), .B2(registers_17__ap[13]), .ZN(n_1_0_266)); + AOI22_X1_LVT i_1_0_279 (.A1(registers_7__ap[13]), .A2(n_1_0_623), .B1( + n_1_0_614), .B2(registers_16__ap[13]), .ZN(n_1_0_265)); + NAND3_X1_LVT i_1_0_277 (.A1(n_1_0_267), .A2(n_1_0_266), .A3(n_1_0_265), + .ZN(n_1_0_263)); + AOI221_X1_LVT i_1_0_276 (.A(n_1_0_263), .B1(n_1_0_642), .B2( + registers_22__ap[13]), .C1(registers_5__ap[13]), .C2(n_1_0_635), .ZN( + n_1_0_262)); + AOI22_X1_LVT i_1_0_278 (.A1(registers_13__ap[13]), .A2(n_1_0_631), .B1( + n_1_0_612), .B2(registers_21__ap[13]), .ZN(n_1_0_264)); + AOI222_X1_LVT i_1_0_275 (.A1(registers_26__ap[13]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[13]), .C1(n_1_0_620), .C2( + registers_25__ap[13]), .ZN(n_1_0_261)); + AOI22_X1_LVT i_1_0_274 (.A1(registers_28__ap[13]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[13]), .ZN(n_1_0_260)); + NAND3_X1_LVT i_1_0_273 (.A1(n_1_0_264), .A2(n_1_0_261), .A3(n_1_0_260), + .ZN(n_1_0_259)); + AOI22_X1_LVT i_1_0_272 (.A1(registers_1__ap[13]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[13]), .ZN(n_1_0_258)); + AOI22_X1_LVT i_1_0_271 (.A1(registers_19__ap[13]), .A2(n_1_0_633), .B1( + n_1_0_618), .B2(registers_2__ap[13]), .ZN(n_1_0_257)); + AOI22_X1_LVT i_1_0_270 (.A1(registers_14__ap[13]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[13]), .ZN(n_1_0_256)); + AOI22_X1_LVT i_1_0_269 (.A1(registers_27__ap[13]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[13]), .ZN(n_1_0_255)); + NAND4_X1_LVT i_1_0_268 (.A1(n_1_0_258), .A2(n_1_0_257), .A3(n_1_0_256), + .A4(n_1_0_255), .ZN(n_1_0_254)); + AOI22_X1_LVT i_1_0_267 (.A1(registers_24__ap[13]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[13]), .ZN(n_1_0_253)); + AOI22_X1_LVT i_1_0_266 (.A1(registers_4__ap[13]), .A2(n_1_0_638), .B1( + n_1_0_637), .B2(registers_31__ap[13]), .ZN(n_1_0_252)); + AOI22_X1_LVT i_1_0_265 (.A1(registers_29__ap[13]), .A2(n_1_0_649), .B1( + n_1_0_615), .B2(registers_23__ap[13]), .ZN(n_1_0_251)); + AOI22_X1_LVT i_1_0_264 (.A1(registers_15__ap[13]), .A2(n_1_0_627), .B1( + n_1_0_610), .B2(registers_3__ap[13]), .ZN(n_1_0_250)); + NAND4_X1_LVT i_1_0_263 (.A1(n_1_0_253), .A2(n_1_0_252), .A3(n_1_0_251), + .A4(n_1_0_250), .ZN(n_1_0_249)); + NOR3_X1_LVT i_1_0_262 (.A1(n_1_0_259), .A2(n_1_0_254), .A3(n_1_0_249), + .ZN(n_1_0_248)); + NAND2_X1_LVT i_1_0_261 (.A1(n_1_0_262), .A2(n_1_0_248), .ZN(RRs2[13])); + AOI22_X1_LVT i_1_0_260 (.A1(registers_18__ap[12]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[12]), .ZN(n_1_0_247)); + AOI22_X1_LVT i_1_0_259 (.A1(registers_12__ap[12]), .A2(n_1_0_632), .B1( + n_1_0_629), .B2(registers_17__ap[12]), .ZN(n_1_0_246)); + AOI22_X1_LVT i_1_0_258 (.A1(registers_5__ap[12]), .A2(n_1_0_635), .B1( + n_1_0_623), .B2(registers_7__ap[12]), .ZN(n_1_0_245)); + NAND3_X1_LVT i_1_0_256 (.A1(n_1_0_247), .A2(n_1_0_246), .A3(n_1_0_245), + .ZN(n_1_0_243)); + AOI221_X1_LVT i_1_0_255 (.A(n_1_0_243), .B1(n_1_0_642), .B2( + registers_22__ap[12]), .C1(registers_16__ap[12]), .C2(n_1_0_614), .ZN( + n_1_0_242)); + AOI22_X1_LVT i_1_0_257 (.A1(registers_13__ap[12]), .A2(n_1_0_631), .B1( + n_1_0_612), .B2(registers_21__ap[12]), .ZN(n_1_0_244)); + AOI222_X1_LVT i_1_0_254 (.A1(registers_26__ap[12]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[12]), .C1(n_1_0_620), .C2( + registers_25__ap[12]), .ZN(n_1_0_241)); + AOI22_X1_LVT i_1_0_253 (.A1(registers_28__ap[12]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[12]), .ZN(n_1_0_240)); + NAND3_X1_LVT i_1_0_252 (.A1(n_1_0_244), .A2(n_1_0_241), .A3(n_1_0_240), + .ZN(n_1_0_239)); + AOI22_X1_LVT i_1_0_251 (.A1(registers_1__ap[12]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[12]), .ZN(n_1_0_238)); + AOI22_X1_LVT i_1_0_250 (.A1(registers_19__ap[12]), .A2(n_1_0_633), .B1( + n_1_0_618), .B2(registers_2__ap[12]), .ZN(n_1_0_237)); + AOI22_X1_LVT i_1_0_249 (.A1(registers_14__ap[12]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[12]), .ZN(n_1_0_236)); + AOI22_X1_LVT i_1_0_248 (.A1(registers_27__ap[12]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[12]), .ZN(n_1_0_235)); + NAND4_X1_LVT i_1_0_247 (.A1(n_1_0_238), .A2(n_1_0_237), .A3(n_1_0_236), + .A4(n_1_0_235), .ZN(n_1_0_234)); + AOI22_X1_LVT i_1_0_246 (.A1(registers_24__ap[12]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[12]), .ZN(n_1_0_233)); + AOI22_X1_LVT i_1_0_245 (.A1(registers_4__ap[12]), .A2(n_1_0_638), .B1( + n_1_0_637), .B2(registers_31__ap[12]), .ZN(n_1_0_232)); + AOI22_X1_LVT i_1_0_244 (.A1(registers_29__ap[12]), .A2(n_1_0_649), .B1( + n_1_0_615), .B2(registers_23__ap[12]), .ZN(n_1_0_231)); + AOI22_X1_LVT i_1_0_243 (.A1(registers_15__ap[12]), .A2(n_1_0_627), .B1( + n_1_0_610), .B2(registers_3__ap[12]), .ZN(n_1_0_230)); + NAND4_X1_LVT i_1_0_242 (.A1(n_1_0_233), .A2(n_1_0_232), .A3(n_1_0_231), + .A4(n_1_0_230), .ZN(n_1_0_229)); + NOR3_X1_LVT i_1_0_241 (.A1(n_1_0_239), .A2(n_1_0_234), .A3(n_1_0_229), + .ZN(n_1_0_228)); + NAND2_X1_LVT i_1_0_240 (.A1(n_1_0_242), .A2(n_1_0_228), .ZN(RRs2[12])); + AOI22_X1_LVT i_1_0_238 (.A1(registers_29__ap[11]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[11]), .ZN(n_1_0_226)); + AOI22_X1_LVT i_1_0_239 (.A1(registers_27__ap[11]), .A2(n_1_0_636), .B1( + n_1_0_627), .B2(registers_15__ap[11]), .ZN(n_1_0_227)); + AOI22_X1_LVT i_1_0_237 (.A1(registers_1__ap[11]), .A2(n_1_0_644), .B1( + n_1_0_616), .B2(registers_6__ap[11]), .ZN(n_1_0_225)); + AOI22_X1_LVT i_1_0_236 (.A1(registers_5__ap[11]), .A2(n_1_0_635), .B1( + n_1_0_615), .B2(registers_23__ap[11]), .ZN(n_1_0_224)); + NAND3_X1_LVT i_1_0_235 (.A1(n_1_0_227), .A2(n_1_0_225), .A3(n_1_0_224), + .ZN(n_1_0_223)); + AOI221_X1_LVT i_1_0_234 (.A(n_1_0_223), .B1(n_1_0_637), .B2( + registers_31__ap[11]), .C1(registers_16__ap[11]), .C2(n_1_0_614), .ZN( + n_1_0_222)); + AOI222_X1_LVT i_1_0_233 (.A1(registers_8__ap[11]), .A2(n_1_0_626), .B1( + n_1_0_624), .B2(registers_10__ap[11]), .C1(n_1_0_622), .C2( + registers_30__ap[11]), .ZN(n_1_0_221)); + NAND3_X1_LVT i_1_0_232 (.A1(n_1_0_226), .A2(n_1_0_222), .A3(n_1_0_221), + .ZN(n_1_0_220)); + AOI221_X1_LVT i_1_0_231 (.A(n_1_0_220), .B1(n_1_0_638), .B2( + registers_4__ap[11]), .C1(registers_28__ap[11]), .C2(n_1_0_634), .ZN( + n_1_0_219)); + AOI22_X1_LVT i_1_0_230 (.A1(registers_18__ap[11]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[11]), .ZN(n_1_0_218)); + AOI22_X1_LVT i_1_0_229 (.A1(registers_12__ap[11]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[11]), .ZN(n_1_0_217)); + AOI22_X1_LVT i_1_0_228 (.A1(registers_22__ap[11]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[11]), .ZN(n_1_0_216)); + NAND3_X1_LVT i_1_0_227 (.A1(n_1_0_218), .A2(n_1_0_217), .A3(n_1_0_216), + .ZN(n_1_0_215)); + AOI221_X1_LVT i_1_0_226 (.A(n_1_0_215), .B1(n_1_0_613), .B2( + registers_20__ap[11]), .C1(registers_17__ap[11]), .C2(n_1_0_629), .ZN( + n_1_0_214)); + AOI22_X1_LVT i_1_0_225 (.A1(registers_13__ap[11]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[11]), .ZN(n_1_0_213)); + AOI22_X1_LVT i_1_0_224 (.A1(registers_7__ap[11]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[11]), .ZN(n_1_0_212)); + AOI22_X1_LVT i_1_0_223 (.A1(registers_19__ap[11]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[11]), .ZN(n_1_0_211)); + NAND3_X1_LVT i_1_0_222 (.A1(n_1_0_213), .A2(n_1_0_212), .A3(n_1_0_211), + .ZN(n_1_0_210)); + AOI221_X1_LVT i_1_0_221 (.A(n_1_0_210), .B1(n_1_0_611), .B2( + registers_11__ap[11]), .C1(registers_2__ap[11]), .C2(n_1_0_618), .ZN( + n_1_0_209)); + NAND3_X1_LVT i_1_0_220 (.A1(n_1_0_219), .A2(n_1_0_214), .A3(n_1_0_209), + .ZN(RRs2[11])); + AOI22_X1_LVT i_1_0_219 (.A1(registers_28__ap[10]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[10]), .ZN(n_1_0_208)); + AOI222_X1_LVT i_1_0_218 (.A1(registers_26__ap[10]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[10]), .C1(registers_25__ap[10]), .C2( + n_1_0_620), .ZN(n_1_0_207)); + AOI22_X1_LVT i_1_0_217 (.A1(registers_13__ap[10]), .A2(n_1_0_631), .B1( + n_1_0_612), .B2(registers_21__ap[10]), .ZN(n_1_0_206)); + AOI22_X1_LVT i_1_0_216 (.A1(registers_24__ap[10]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[10]), .ZN(n_1_0_205)); + AOI22_X1_LVT i_1_0_215 (.A1(registers_15__ap[10]), .A2(n_1_0_627), .B1( + n_1_0_610), .B2(registers_3__ap[10]), .ZN(n_1_0_204)); + AOI22_X1_LVT i_1_0_214 (.A1(registers_31__ap[10]), .A2(n_1_0_637), .B1( + n_1_0_629), .B2(registers_17__ap[10]), .ZN(n_1_0_203)); + AOI22_X1_LVT i_1_0_213 (.A1(registers_29__ap[10]), .A2(n_1_0_649), .B1( + n_1_0_615), .B2(registers_23__ap[10]), .ZN(n_1_0_202)); + NAND4_X1_LVT i_1_0_212 (.A1(n_1_0_205), .A2(n_1_0_204), .A3(n_1_0_203), + .A4(n_1_0_202), .ZN(n_1_0_201)); + AOI22_X1_LVT i_1_0_211 (.A1(registers_18__ap[10]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[10]), .ZN(n_1_0_200)); + AOI22_X1_LVT i_1_0_210 (.A1(registers_4__ap[10]), .A2(n_1_0_638), .B1( + n_1_0_632), .B2(registers_12__ap[10]), .ZN(n_1_0_199)); + AOI22_X1_LVT i_1_0_209 (.A1(registers_7__ap[10]), .A2(n_1_0_623), .B1( + n_1_0_614), .B2(registers_16__ap[10]), .ZN(n_1_0_198)); + AOI22_X1_LVT i_1_0_208 (.A1(registers_22__ap[10]), .A2(n_1_0_642), .B1( + n_1_0_635), .B2(registers_5__ap[10]), .ZN(n_1_0_197)); + NAND4_X1_LVT i_1_0_207 (.A1(n_1_0_200), .A2(n_1_0_199), .A3(n_1_0_198), + .A4(n_1_0_197), .ZN(n_1_0_196)); + AOI22_X1_LVT i_1_0_206 (.A1(registers_1__ap[10]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[10]), .ZN(n_1_0_195)); + AOI22_X1_LVT i_1_0_205 (.A1(registers_14__ap[10]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[10]), .ZN(n_1_0_194)); + AOI22_X1_LVT i_1_0_204 (.A1(registers_19__ap[10]), .A2(n_1_0_633), .B1( + n_1_0_618), .B2(registers_2__ap[10]), .ZN(n_1_0_193)); + AOI22_X1_LVT i_1_0_203 (.A1(registers_27__ap[10]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[10]), .ZN(n_1_0_192)); + NAND4_X1_LVT i_1_0_202 (.A1(n_1_0_195), .A2(n_1_0_194), .A3(n_1_0_193), + .A4(n_1_0_192), .ZN(n_1_0_191)); + NOR3_X1_LVT i_1_0_201 (.A1(n_1_0_201), .A2(n_1_0_196), .A3(n_1_0_191), + .ZN(n_1_0_190)); + NAND4_X1_LVT i_1_0_200 (.A1(n_1_0_208), .A2(n_1_0_207), .A3(n_1_0_206), + .A4(n_1_0_190), .ZN(RRs2[10])); + AOI22_X1_LVT i_1_0_196 (.A1(registers_13__ap[9]), .A2(n_1_0_631), .B1( + n_1_0_612), .B2(registers_21__ap[9]), .ZN(n_1_0_186)); + AOI22_X1_LVT i_1_0_199 (.A1(registers_29__ap[9]), .A2(n_1_0_649), .B1( + n_1_0_636), .B2(registers_27__ap[9]), .ZN(n_1_0_189)); + AOI22_X1_LVT i_1_0_195 (.A1(registers_24__ap[9]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[9]), .ZN(n_1_0_185)); + AOI22_X1_LVT i_1_0_198 (.A1(registers_31__ap[9]), .A2(n_1_0_637), .B1( + n_1_0_627), .B2(registers_15__ap[9]), .ZN(n_1_0_188)); + INV_X1_LVT i_1_0_197 (.A(n_1_0_188), .ZN(n_1_0_187)); + AOI221_X1_LVT i_1_0_194 (.A(n_1_0_187), .B1(n_1_0_615), .B2( + registers_23__ap[9]), .C1(registers_4__ap[9]), .C2(n_1_0_638), .ZN( + n_1_0_184)); + AOI222_X1_LVT i_1_0_193 (.A1(registers_18__ap[9]), .A2(n_1_0_646), .B1( + n_1_0_624), .B2(registers_10__ap[9]), .C1(registers_25__ap[9]), .C2( + n_1_0_620), .ZN(n_1_0_183)); + NAND4_X1_LVT i_1_0_192 (.A1(n_1_0_189), .A2(n_1_0_185), .A3(n_1_0_184), + .A4(n_1_0_183), .ZN(n_1_0_182)); + AOI221_X1_LVT i_1_0_191 (.A(n_1_0_182), .B1(n_1_0_626), .B2( + registers_8__ap[9]), .C1(registers_28__ap[9]), .C2(n_1_0_634), .ZN( + n_1_0_181)); + AOI22_X1_LVT i_1_0_190 (.A1(registers_26__ap[9]), .A2(n_1_0_640), .B1( + n_1_0_622), .B2(registers_30__ap[9]), .ZN(n_1_0_180)); + AOI22_X1_LVT i_1_0_189 (.A1(registers_12__ap[9]), .A2(n_1_0_632), .B1( + n_1_0_629), .B2(registers_17__ap[9]), .ZN(n_1_0_179)); + AOI22_X1_LVT i_1_0_188 (.A1(registers_5__ap[9]), .A2(n_1_0_635), .B1( + n_1_0_623), .B2(registers_7__ap[9]), .ZN(n_1_0_178)); + NAND3_X1_LVT i_1_0_187 (.A1(n_1_0_180), .A2(n_1_0_179), .A3(n_1_0_178), + .ZN(n_1_0_177)); + AOI221_X1_LVT i_1_0_186 (.A(n_1_0_177), .B1(n_1_0_642), .B2( + registers_22__ap[9]), .C1(registers_16__ap[9]), .C2(n_1_0_614), .ZN( + n_1_0_176)); + AOI22_X1_LVT i_1_0_185 (.A1(registers_1__ap[9]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[9]), .ZN(n_1_0_175)); + AOI22_X1_LVT i_1_0_184 (.A1(registers_14__ap[9]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[9]), .ZN(n_1_0_174)); + AOI22_X1_LVT i_1_0_183 (.A1(registers_19__ap[9]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[9]), .ZN(n_1_0_173)); + NAND3_X1_LVT i_1_0_182 (.A1(n_1_0_175), .A2(n_1_0_174), .A3(n_1_0_173), + .ZN(n_1_0_172)); + AOI221_X1_LVT i_1_0_181 (.A(n_1_0_172), .B1(n_1_0_611), .B2( + registers_11__ap[9]), .C1(registers_2__ap[9]), .C2(n_1_0_618), .ZN( + n_1_0_171)); + NAND4_X1_LVT i_1_0_180 (.A1(n_1_0_186), .A2(n_1_0_181), .A3(n_1_0_176), + .A4(n_1_0_171), .ZN(RRs2[9])); + AOI22_X1_LVT i_1_0_179 (.A1(registers_28__ap[8]), .A2(n_1_0_634), .B1( + n_1_0_629), .B2(registers_17__ap[8]), .ZN(n_1_0_170)); + AOI222_X1_LVT i_1_0_178 (.A1(registers_26__ap[8]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[8]), .C1(n_1_0_626), .C2( + registers_8__ap[8]), .ZN(n_1_0_169)); + AOI22_X1_LVT i_1_0_177 (.A1(registers_29__ap[8]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[8]), .ZN(n_1_0_168)); + AOI22_X1_LVT i_1_0_176 (.A1(registers_1__ap[8]), .A2(n_1_0_644), .B1( + n_1_0_616), .B2(registers_6__ap[8]), .ZN(n_1_0_167)); + AOI22_X1_LVT i_1_0_175 (.A1(registers_5__ap[8]), .A2(n_1_0_635), .B1( + n_1_0_610), .B2(registers_3__ap[8]), .ZN(n_1_0_166)); + AOI22_X1_LVT i_1_0_174 (.A1(registers_31__ap[8]), .A2(n_1_0_637), .B1( + n_1_0_614), .B2(registers_16__ap[8]), .ZN(n_1_0_165)); + AOI22_X1_LVT i_1_0_173 (.A1(registers_15__ap[8]), .A2(n_1_0_627), .B1( + n_1_0_615), .B2(registers_23__ap[8]), .ZN(n_1_0_164)); + NAND4_X1_LVT i_1_0_172 (.A1(n_1_0_167), .A2(n_1_0_166), .A3(n_1_0_165), + .A4(n_1_0_164), .ZN(n_1_0_163)); + AOI22_X1_LVT i_1_0_171 (.A1(registers_18__ap[8]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[8]), .ZN(n_1_0_162)); + AOI22_X1_LVT i_1_0_170 (.A1(registers_4__ap[8]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[8]), .ZN(n_1_0_161)); + AOI22_X1_LVT i_1_0_169 (.A1(registers_22__ap[8]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[8]), .ZN(n_1_0_160)); + AOI22_X1_LVT i_1_0_168 (.A1(registers_12__ap[8]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[8]), .ZN(n_1_0_159)); + NAND4_X1_LVT i_1_0_167 (.A1(n_1_0_162), .A2(n_1_0_161), .A3(n_1_0_160), + .A4(n_1_0_159), .ZN(n_1_0_158)); + AOI22_X1_LVT i_1_0_166 (.A1(registers_13__ap[8]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[8]), .ZN(n_1_0_157)); + AOI22_X1_LVT i_1_0_165 (.A1(registers_7__ap[8]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[8]), .ZN(n_1_0_156)); + AOI22_X1_LVT i_1_0_164 (.A1(registers_19__ap[8]), .A2(n_1_0_633), .B1( + n_1_0_618), .B2(registers_2__ap[8]), .ZN(n_1_0_155)); + AOI22_X1_LVT i_1_0_163 (.A1(registers_27__ap[8]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[8]), .ZN(n_1_0_154)); + NAND4_X1_LVT i_1_0_162 (.A1(n_1_0_157), .A2(n_1_0_156), .A3(n_1_0_155), + .A4(n_1_0_154), .ZN(n_1_0_153)); + NOR3_X1_LVT i_1_0_161 (.A1(n_1_0_163), .A2(n_1_0_158), .A3(n_1_0_153), + .ZN(n_1_0_152)); + NAND4_X1_LVT i_1_0_160 (.A1(n_1_0_170), .A2(n_1_0_169), .A3(n_1_0_168), + .A4(n_1_0_152), .ZN(RRs2[8])); + AOI22_X1_LVT i_1_0_159 (.A1(registers_28__ap[7]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[7]), .ZN(n_1_0_151)); + AOI222_X1_LVT i_1_0_158 (.A1(registers_26__ap[7]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[7]), .C1(registers_25__ap[7]), .C2( + n_1_0_620), .ZN(n_1_0_150)); + AOI22_X1_LVT i_1_0_157 (.A1(registers_24__ap[7]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[7]), .ZN(n_1_0_149)); + AOI22_X1_LVT i_1_0_156 (.A1(registers_15__ap[7]), .A2(n_1_0_627), .B1( + n_1_0_610), .B2(registers_3__ap[7]), .ZN(n_1_0_148)); + AOI22_X1_LVT i_1_0_155 (.A1(registers_31__ap[7]), .A2(n_1_0_637), .B1( + n_1_0_629), .B2(registers_17__ap[7]), .ZN(n_1_0_147)); + AOI22_X1_LVT i_1_0_154 (.A1(registers_29__ap[7]), .A2(n_1_0_649), .B1( + n_1_0_615), .B2(registers_23__ap[7]), .ZN(n_1_0_146)); + NAND4_X1_LVT i_1_0_153 (.A1(n_1_0_149), .A2(n_1_0_148), .A3(n_1_0_147), + .A4(n_1_0_146), .ZN(n_1_0_145)); + AOI221_X1_LVT i_1_0_152 (.A(n_1_0_145), .B1(n_1_0_612), .B2( + registers_21__ap[7]), .C1(registers_13__ap[7]), .C2(n_1_0_631), .ZN( + n_1_0_144)); + AOI22_X1_LVT i_1_0_151 (.A1(registers_18__ap[7]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[7]), .ZN(n_1_0_143)); + AOI22_X1_LVT i_1_0_150 (.A1(registers_4__ap[7]), .A2(n_1_0_638), .B1( + n_1_0_632), .B2(registers_12__ap[7]), .ZN(n_1_0_142)); + AOI22_X1_LVT i_1_0_149 (.A1(registers_5__ap[7]), .A2(n_1_0_635), .B1( + n_1_0_623), .B2(registers_7__ap[7]), .ZN(n_1_0_141)); + AOI22_X1_LVT i_1_0_148 (.A1(registers_22__ap[7]), .A2(n_1_0_642), .B1( + n_1_0_614), .B2(registers_16__ap[7]), .ZN(n_1_0_140)); + NAND4_X1_LVT i_1_0_147 (.A1(n_1_0_143), .A2(n_1_0_142), .A3(n_1_0_141), + .A4(n_1_0_140), .ZN(n_1_0_139)); + AOI22_X1_LVT i_1_0_146 (.A1(registers_1__ap[7]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[7]), .ZN(n_1_0_138)); + AOI22_X1_LVT i_1_0_145 (.A1(registers_14__ap[7]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[7]), .ZN(n_1_0_137)); + AOI22_X1_LVT i_1_0_144 (.A1(registers_19__ap[7]), .A2(n_1_0_633), .B1( + n_1_0_618), .B2(registers_2__ap[7]), .ZN(n_1_0_136)); + AOI22_X1_LVT i_1_0_143 (.A1(registers_27__ap[7]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[7]), .ZN(n_1_0_135)); + NAND4_X1_LVT i_1_0_142 (.A1(n_1_0_138), .A2(n_1_0_137), .A3(n_1_0_136), + .A4(n_1_0_135), .ZN(n_1_0_134)); + NOR2_X1_LVT i_1_0_141 (.A1(n_1_0_139), .A2(n_1_0_134), .ZN(n_1_0_133)); + NAND4_X1_LVT i_1_0_140 (.A1(n_1_0_151), .A2(n_1_0_150), .A3(n_1_0_144), + .A4(n_1_0_133), .ZN(RRs2[7])); + AOI22_X1_LVT i_1_0_136 (.A1(registers_13__ap[6]), .A2(n_1_0_631), .B1( + n_1_0_612), .B2(registers_21__ap[6]), .ZN(n_1_0_129)); + AOI22_X1_LVT i_1_0_139 (.A1(registers_29__ap[6]), .A2(n_1_0_649), .B1( + n_1_0_636), .B2(registers_27__ap[6]), .ZN(n_1_0_132)); + AOI22_X1_LVT i_1_0_135 (.A1(registers_24__ap[6]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[6]), .ZN(n_1_0_128)); + AOI22_X1_LVT i_1_0_138 (.A1(registers_31__ap[6]), .A2(n_1_0_637), .B1( + n_1_0_627), .B2(registers_15__ap[6]), .ZN(n_1_0_131)); + INV_X1_LVT i_1_0_137 (.A(n_1_0_131), .ZN(n_1_0_130)); + AOI221_X1_LVT i_1_0_134 (.A(n_1_0_130), .B1(n_1_0_638), .B2( + registers_4__ap[6]), .C1(registers_23__ap[6]), .C2(n_1_0_615), .ZN( + n_1_0_127)); + AOI222_X1_LVT i_1_0_133 (.A1(registers_18__ap[6]), .A2(n_1_0_646), .B1( + n_1_0_620), .B2(registers_25__ap[6]), .C1(n_1_0_624), .C2( + registers_10__ap[6]), .ZN(n_1_0_126)); + NAND4_X1_LVT i_1_0_132 (.A1(n_1_0_132), .A2(n_1_0_128), .A3(n_1_0_127), + .A4(n_1_0_126), .ZN(n_1_0_125)); + AOI221_X1_LVT i_1_0_131 (.A(n_1_0_125), .B1(n_1_0_626), .B2( + registers_8__ap[6]), .C1(registers_28__ap[6]), .C2(n_1_0_634), .ZN( + n_1_0_124)); + AOI22_X1_LVT i_1_0_130 (.A1(registers_26__ap[6]), .A2(n_1_0_640), .B1( + n_1_0_622), .B2(registers_30__ap[6]), .ZN(n_1_0_123)); + AOI22_X1_LVT i_1_0_129 (.A1(registers_12__ap[6]), .A2(n_1_0_632), .B1( + n_1_0_629), .B2(registers_17__ap[6]), .ZN(n_1_0_122)); + AOI22_X1_LVT i_1_0_128 (.A1(registers_7__ap[6]), .A2(n_1_0_623), .B1( + n_1_0_614), .B2(registers_16__ap[6]), .ZN(n_1_0_121)); + NAND3_X1_LVT i_1_0_127 (.A1(n_1_0_123), .A2(n_1_0_122), .A3(n_1_0_121), + .ZN(n_1_0_120)); + AOI221_X1_LVT i_1_0_126 (.A(n_1_0_120), .B1(n_1_0_642), .B2( + registers_22__ap[6]), .C1(registers_5__ap[6]), .C2(n_1_0_635), .ZN( + n_1_0_119)); + AOI22_X1_LVT i_1_0_125 (.A1(registers_1__ap[6]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[6]), .ZN(n_1_0_118)); + AOI22_X1_LVT i_1_0_124 (.A1(registers_14__ap[6]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[6]), .ZN(n_1_0_117)); + AOI22_X1_LVT i_1_0_123 (.A1(registers_19__ap[6]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[6]), .ZN(n_1_0_116)); + NAND3_X1_LVT i_1_0_122 (.A1(n_1_0_118), .A2(n_1_0_117), .A3(n_1_0_116), + .ZN(n_1_0_115)); + AOI221_X1_LVT i_1_0_121 (.A(n_1_0_115), .B1(n_1_0_618), .B2( + registers_2__ap[6]), .C1(registers_11__ap[6]), .C2(n_1_0_611), .ZN( + n_1_0_114)); + NAND4_X1_LVT i_1_0_120 (.A1(n_1_0_129), .A2(n_1_0_124), .A3(n_1_0_119), + .A4(n_1_0_114), .ZN(RRs2[6])); + AOI22_X1_LVT i_1_0_118 (.A1(registers_28__ap[5]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[5]), .ZN(n_1_0_112)); + AOI22_X1_LVT i_1_0_119 (.A1(registers_31__ap[5]), .A2(n_1_0_637), .B1( + n_1_0_627), .B2(registers_15__ap[5]), .ZN(n_1_0_113)); + AOI22_X1_LVT i_1_0_117 (.A1(registers_24__ap[5]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[5]), .ZN(n_1_0_111)); + AOI22_X1_LVT i_1_0_116 (.A1(registers_17__ap[5]), .A2(n_1_0_629), .B1( + n_1_0_615), .B2(registers_23__ap[5]), .ZN(n_1_0_110)); + NAND3_X1_LVT i_1_0_115 (.A1(n_1_0_113), .A2(n_1_0_111), .A3(n_1_0_110), + .ZN(n_1_0_109)); + AOI221_X1_LVT i_1_0_114 (.A(n_1_0_109), .B1(n_1_0_636), .B2( + registers_27__ap[5]), .C1(registers_29__ap[5]), .C2(n_1_0_649), .ZN( + n_1_0_108)); + AOI222_X1_LVT i_1_0_113 (.A1(registers_10__ap[5]), .A2(n_1_0_624), .B1( + n_1_0_620), .B2(registers_25__ap[5]), .C1(registers_18__ap[5]), .C2( + n_1_0_646), .ZN(n_1_0_107)); + NAND3_X1_LVT i_1_0_112 (.A1(n_1_0_112), .A2(n_1_0_108), .A3(n_1_0_107), + .ZN(n_1_0_106)); + AOI221_X1_LVT i_1_0_111 (.A(n_1_0_106), .B1(n_1_0_612), .B2( + registers_21__ap[5]), .C1(registers_13__ap[5]), .C2(n_1_0_631), .ZN( + n_1_0_105)); + AOI22_X1_LVT i_1_0_110 (.A1(registers_26__ap[5]), .A2(n_1_0_640), .B1( + n_1_0_622), .B2(registers_30__ap[5]), .ZN(n_1_0_104)); + AOI22_X1_LVT i_1_0_109 (.A1(registers_4__ap[5]), .A2(n_1_0_638), .B1( + n_1_0_632), .B2(registers_12__ap[5]), .ZN(n_1_0_103)); + AOI22_X1_LVT i_1_0_108 (.A1(registers_5__ap[5]), .A2(n_1_0_635), .B1( + n_1_0_623), .B2(registers_7__ap[5]), .ZN(n_1_0_102)); + NAND3_X1_LVT i_1_0_107 (.A1(n_1_0_104), .A2(n_1_0_103), .A3(n_1_0_102), + .ZN(n_1_0_101)); + AOI221_X1_LVT i_1_0_106 (.A(n_1_0_101), .B1(n_1_0_642), .B2( + registers_22__ap[5]), .C1(registers_16__ap[5]), .C2(n_1_0_614), .ZN( + n_1_0_100)); + AOI22_X1_LVT i_1_0_105 (.A1(registers_1__ap[5]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[5]), .ZN(n_1_0_99)); + AOI22_X1_LVT i_1_0_104 (.A1(registers_14__ap[5]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[5]), .ZN(n_1_0_98)); + AOI22_X1_LVT i_1_0_103 (.A1(registers_19__ap[5]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[5]), .ZN(n_1_0_97)); + NAND3_X1_LVT i_1_0_102 (.A1(n_1_0_99), .A2(n_1_0_98), .A3(n_1_0_97), .ZN( + n_1_0_96)); + AOI221_X1_LVT i_1_0_101 (.A(n_1_0_96), .B1(n_1_0_611), .B2( + registers_11__ap[5]), .C1(registers_2__ap[5]), .C2(n_1_0_618), .ZN( + n_1_0_95)); + NAND3_X1_LVT i_1_0_100 (.A1(n_1_0_105), .A2(n_1_0_100), .A3(n_1_0_95), + .ZN(RRs2[5])); + AOI22_X1_LVT i_1_0_99 (.A1(registers_4__ap[4]), .A2(n_1_0_638), .B1(n_1_0_634), + .B2(registers_28__ap[4]), .ZN(n_1_0_94)); + AOI222_X1_LVT i_1_0_98 (.A1(registers_8__ap[4]), .A2(n_1_0_626), .B1( + n_1_0_624), .B2(registers_10__ap[4]), .C1(n_1_0_622), .C2( + registers_30__ap[4]), .ZN(n_1_0_93)); + AOI22_X1_LVT i_1_0_97 (.A1(registers_29__ap[4]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[4]), .ZN(n_1_0_92)); + AOI22_X1_LVT i_1_0_96 (.A1(registers_1__ap[4]), .A2(n_1_0_644), .B1(n_1_0_616), + .B2(registers_6__ap[4]), .ZN(n_1_0_91)); + AOI22_X1_LVT i_1_0_95 (.A1(registers_27__ap[4]), .A2(n_1_0_636), .B1( + n_1_0_627), .B2(registers_15__ap[4]), .ZN(n_1_0_90)); + AOI22_X1_LVT i_1_0_94 (.A1(registers_23__ap[4]), .A2(n_1_0_615), .B1( + n_1_0_614), .B2(registers_16__ap[4]), .ZN(n_1_0_89)); + AOI22_X1_LVT i_1_0_93 (.A1(registers_31__ap[4]), .A2(n_1_0_637), .B1( + n_1_0_635), .B2(registers_5__ap[4]), .ZN(n_1_0_88)); + NAND4_X1_LVT i_1_0_92 (.A1(n_1_0_91), .A2(n_1_0_90), .A3(n_1_0_89), .A4( + n_1_0_88), .ZN(n_1_0_87)); + AOI22_X1_LVT i_1_0_91 (.A1(registers_18__ap[4]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[4]), .ZN(n_1_0_86)); + AOI22_X1_LVT i_1_0_90 (.A1(registers_12__ap[4]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[4]), .ZN(n_1_0_85)); + AOI22_X1_LVT i_1_0_89 (.A1(registers_22__ap[4]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[4]), .ZN(n_1_0_84)); + AOI22_X1_LVT i_1_0_88 (.A1(registers_17__ap[4]), .A2(n_1_0_629), .B1( + n_1_0_613), .B2(registers_20__ap[4]), .ZN(n_1_0_83)); + NAND4_X1_LVT i_1_0_87 (.A1(n_1_0_86), .A2(n_1_0_85), .A3(n_1_0_84), .A4( + n_1_0_83), .ZN(n_1_0_82)); + AOI22_X1_LVT i_1_0_86 (.A1(registers_13__ap[4]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[4]), .ZN(n_1_0_81)); + AOI22_X1_LVT i_1_0_85 (.A1(registers_7__ap[4]), .A2(n_1_0_623), .B1(n_1_0_619), + .B2(registers_14__ap[4]), .ZN(n_1_0_80)); + AOI22_X1_LVT i_1_0_84 (.A1(registers_19__ap[4]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[4]), .ZN(n_1_0_79)); + AOI22_X1_LVT i_1_0_83 (.A1(registers_2__ap[4]), .A2(n_1_0_618), .B1(n_1_0_611), + .B2(registers_11__ap[4]), .ZN(n_1_0_78)); + NAND4_X1_LVT i_1_0_82 (.A1(n_1_0_81), .A2(n_1_0_80), .A3(n_1_0_79), .A4( + n_1_0_78), .ZN(n_1_0_77)); + NOR3_X1_LVT i_1_0_81 (.A1(n_1_0_87), .A2(n_1_0_82), .A3(n_1_0_77), .ZN( + n_1_0_76)); + NAND4_X1_LVT i_1_0_80 (.A1(n_1_0_94), .A2(n_1_0_93), .A3(n_1_0_92), .A4( + n_1_0_76), .ZN(RRs2[4])); + AOI22_X1_LVT i_1_0_78 (.A1(registers_29__ap[3]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[3]), .ZN(n_1_0_74)); + AOI22_X1_LVT i_1_0_79 (.A1(registers_27__ap[3]), .A2(n_1_0_636), .B1( + n_1_0_627), .B2(registers_15__ap[3]), .ZN(n_1_0_75)); + AOI22_X1_LVT i_1_0_77 (.A1(registers_1__ap[3]), .A2(n_1_0_644), .B1(n_1_0_616), + .B2(registers_6__ap[3]), .ZN(n_1_0_73)); + AOI22_X1_LVT i_1_0_76 (.A1(registers_5__ap[3]), .A2(n_1_0_635), .B1(n_1_0_611), + .B2(registers_11__ap[3]), .ZN(n_1_0_72)); + NAND3_X1_LVT i_1_0_75 (.A1(n_1_0_75), .A2(n_1_0_73), .A3(n_1_0_72), .ZN( + n_1_0_71)); + AOI221_X1_LVT i_1_0_74 (.A(n_1_0_71), .B1(n_1_0_614), .B2(registers_16__ap[3]), + .C1(registers_31__ap[3]), .C2(n_1_0_637), .ZN(n_1_0_70)); + AOI222_X1_LVT i_1_0_73 (.A1(registers_8__ap[3]), .A2(n_1_0_626), .B1( + n_1_0_624), .B2(registers_10__ap[3]), .C1(n_1_0_622), .C2( + registers_30__ap[3]), .ZN(n_1_0_69)); + NAND3_X1_LVT i_1_0_72 (.A1(n_1_0_74), .A2(n_1_0_70), .A3(n_1_0_69), .ZN( + n_1_0_68)); + AOI221_X1_LVT i_1_0_71 (.A(n_1_0_68), .B1(n_1_0_638), .B2(registers_4__ap[3]), + .C1(registers_28__ap[3]), .C2(n_1_0_634), .ZN(n_1_0_67)); + AOI22_X1_LVT i_1_0_70 (.A1(registers_18__ap[3]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[3]), .ZN(n_1_0_66)); + AOI22_X1_LVT i_1_0_69 (.A1(registers_12__ap[3]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[3]), .ZN(n_1_0_65)); + AOI22_X1_LVT i_1_0_68 (.A1(registers_22__ap[3]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[3]), .ZN(n_1_0_64)); + NAND3_X1_LVT i_1_0_67 (.A1(n_1_0_66), .A2(n_1_0_65), .A3(n_1_0_64), .ZN( + n_1_0_63)); + AOI221_X1_LVT i_1_0_66 (.A(n_1_0_63), .B1(n_1_0_613), .B2(registers_20__ap[3]), + .C1(registers_17__ap[3]), .C2(n_1_0_629), .ZN(n_1_0_62)); + AOI22_X1_LVT i_1_0_65 (.A1(registers_13__ap[3]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[3]), .ZN(n_1_0_61)); + AOI22_X1_LVT i_1_0_64 (.A1(registers_7__ap[3]), .A2(n_1_0_623), .B1(n_1_0_619), + .B2(registers_14__ap[3]), .ZN(n_1_0_60)); + AOI22_X1_LVT i_1_0_63 (.A1(registers_19__ap[3]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[3]), .ZN(n_1_0_59)); + NAND3_X1_LVT i_1_0_62 (.A1(n_1_0_61), .A2(n_1_0_60), .A3(n_1_0_59), .ZN( + n_1_0_58)); + AOI221_X1_LVT i_1_0_61 (.A(n_1_0_58), .B1(n_1_0_618), .B2(registers_2__ap[3]), + .C1(registers_23__ap[3]), .C2(n_1_0_615), .ZN(n_1_0_57)); + NAND3_X1_LVT i_1_0_60 (.A1(n_1_0_67), .A2(n_1_0_62), .A3(n_1_0_57), .ZN( + RRs2[3])); + AOI22_X1_LVT i_1_0_58 (.A1(registers_29__ap[2]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[2]), .ZN(n_1_0_55)); + AOI22_X1_LVT i_1_0_59 (.A1(registers_27__ap[2]), .A2(n_1_0_636), .B1( + n_1_0_627), .B2(registers_15__ap[2]), .ZN(n_1_0_56)); + AOI22_X1_LVT i_1_0_57 (.A1(registers_1__ap[2]), .A2(n_1_0_644), .B1(n_1_0_616), + .B2(registers_6__ap[2]), .ZN(n_1_0_54)); + AOI22_X1_LVT i_1_0_56 (.A1(registers_5__ap[2]), .A2(n_1_0_635), .B1(n_1_0_615), + .B2(registers_23__ap[2]), .ZN(n_1_0_53)); + NAND3_X1_LVT i_1_0_55 (.A1(n_1_0_56), .A2(n_1_0_54), .A3(n_1_0_53), .ZN( + n_1_0_52)); + AOI221_X1_LVT i_1_0_54 (.A(n_1_0_52), .B1(n_1_0_637), .B2(registers_31__ap[2]), + .C1(registers_16__ap[2]), .C2(n_1_0_614), .ZN(n_1_0_51)); + AOI222_X1_LVT i_1_0_53 (.A1(registers_8__ap[2]), .A2(n_1_0_626), .B1( + n_1_0_624), .B2(registers_10__ap[2]), .C1(n_1_0_622), .C2( + registers_30__ap[2]), .ZN(n_1_0_50)); + NAND3_X1_LVT i_1_0_52 (.A1(n_1_0_55), .A2(n_1_0_51), .A3(n_1_0_50), .ZN( + n_1_0_49)); + AOI221_X1_LVT i_1_0_51 (.A(n_1_0_49), .B1(n_1_0_638), .B2(registers_4__ap[2]), + .C1(registers_28__ap[2]), .C2(n_1_0_634), .ZN(n_1_0_48)); + AOI22_X1_LVT i_1_0_50 (.A1(registers_18__ap[2]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[2]), .ZN(n_1_0_47)); + AOI22_X1_LVT i_1_0_49 (.A1(registers_12__ap[2]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[2]), .ZN(n_1_0_46)); + AOI22_X1_LVT i_1_0_48 (.A1(registers_22__ap[2]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[2]), .ZN(n_1_0_45)); + NAND3_X1_LVT i_1_0_47 (.A1(n_1_0_47), .A2(n_1_0_46), .A3(n_1_0_45), .ZN( + n_1_0_44)); + AOI221_X1_LVT i_1_0_46 (.A(n_1_0_44), .B1(n_1_0_629), .B2(registers_17__ap[2]), + .C1(registers_20__ap[2]), .C2(n_1_0_613), .ZN(n_1_0_43)); + AOI22_X1_LVT i_1_0_45 (.A1(registers_13__ap[2]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[2]), .ZN(n_1_0_42)); + AOI22_X1_LVT i_1_0_44 (.A1(registers_7__ap[2]), .A2(n_1_0_623), .B1(n_1_0_619), + .B2(registers_14__ap[2]), .ZN(n_1_0_41)); + AOI22_X1_LVT i_1_0_43 (.A1(registers_19__ap[2]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[2]), .ZN(n_1_0_40)); + NAND3_X1_LVT i_1_0_42 (.A1(n_1_0_42), .A2(n_1_0_41), .A3(n_1_0_40), .ZN( + n_1_0_39)); + AOI221_X1_LVT i_1_0_41 (.A(n_1_0_39), .B1(n_1_0_618), .B2(registers_2__ap[2]), + .C1(registers_11__ap[2]), .C2(n_1_0_611), .ZN(n_1_0_38)); + NAND3_X1_LVT i_1_0_40 (.A1(n_1_0_48), .A2(n_1_0_43), .A3(n_1_0_38), .ZN( + RRs2[2])); + AOI22_X1_LVT i_1_0_38 (.A1(registers_29__ap[1]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[1]), .ZN(n_1_0_36)); + AOI22_X1_LVT i_1_0_39 (.A1(registers_16__ap[1]), .A2(n_1_0_614), .B1( + n_1_0_610), .B2(registers_3__ap[1]), .ZN(n_1_0_37)); + AOI22_X1_LVT i_1_0_37 (.A1(registers_1__ap[1]), .A2(n_1_0_644), .B1(n_1_0_616), + .B2(registers_6__ap[1]), .ZN(n_1_0_35)); + AOI22_X1_LVT i_1_0_36 (.A1(registers_31__ap[1]), .A2(n_1_0_637), .B1( + n_1_0_635), .B2(registers_5__ap[1]), .ZN(n_1_0_34)); + NAND3_X1_LVT i_1_0_35 (.A1(n_1_0_37), .A2(n_1_0_35), .A3(n_1_0_34), .ZN( + n_1_0_33)); + AOI221_X1_LVT i_1_0_34 (.A(n_1_0_33), .B1(n_1_0_627), .B2(registers_15__ap[1]), + .C1(registers_23__ap[1]), .C2(n_1_0_615), .ZN(n_1_0_32)); + AOI222_X1_LVT i_1_0_33 (.A1(registers_26__ap[1]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[1]), .C1(n_1_0_626), .C2( + registers_8__ap[1]), .ZN(n_1_0_31)); + NAND3_X1_LVT i_1_0_32 (.A1(n_1_0_36), .A2(n_1_0_32), .A3(n_1_0_31), .ZN( + n_1_0_30)); + AOI221_X1_LVT i_1_0_31 (.A(n_1_0_30), .B1(n_1_0_629), .B2(registers_17__ap[1]), + .C1(registers_28__ap[1]), .C2(n_1_0_634), .ZN(n_1_0_29)); + AOI22_X1_LVT i_1_0_30 (.A1(registers_18__ap[1]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[1]), .ZN(n_1_0_28)); + AOI22_X1_LVT i_1_0_29 (.A1(registers_4__ap[1]), .A2(n_1_0_638), .B1(n_1_0_613), + .B2(registers_20__ap[1]), .ZN(n_1_0_27)); + AOI22_X1_LVT i_1_0_28 (.A1(registers_22__ap[1]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[1]), .ZN(n_1_0_26)); + NAND3_X1_LVT i_1_0_27 (.A1(n_1_0_28), .A2(n_1_0_27), .A3(n_1_0_26), .ZN( + n_1_0_25)); + AOI221_X1_LVT i_1_0_26 (.A(n_1_0_25), .B1(n_1_0_632), .B2(registers_12__ap[1]), + .C1(registers_24__ap[1]), .C2(n_1_0_621), .ZN(n_1_0_24)); + AOI22_X1_LVT i_1_0_25 (.A1(registers_13__ap[1]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[1]), .ZN(n_1_0_23)); + AOI22_X1_LVT i_1_0_24 (.A1(registers_7__ap[1]), .A2(n_1_0_623), .B1(n_1_0_619), + .B2(registers_14__ap[1]), .ZN(n_1_0_22)); + AOI22_X1_LVT i_1_0_23 (.A1(registers_19__ap[1]), .A2(n_1_0_633), .B1( + n_1_0_618), .B2(registers_2__ap[1]), .ZN(n_1_0_21)); + NAND3_X1_LVT i_1_0_22 (.A1(n_1_0_23), .A2(n_1_0_22), .A3(n_1_0_21), .ZN( + n_1_0_20)); + AOI221_X1_LVT i_1_0_21 (.A(n_1_0_20), .B1(n_1_0_611), .B2(registers_11__ap[1]), + .C1(registers_27__ap[1]), .C2(n_1_0_636), .ZN(n_1_0_19)); + NAND3_X1_LVT i_1_0_20 (.A1(n_1_0_29), .A2(n_1_0_24), .A3(n_1_0_19), .ZN( + RRs2[1])); + AOI22_X1_LVT i_1_0_19 (.A1(registers_4__ap[0]), .A2(n_1_0_638), .B1(n_1_0_634), + .B2(registers_28__ap[0]), .ZN(n_1_0_18)); + AOI222_X1_LVT i_1_0_18 (.A1(registers_8__ap[0]), .A2(n_1_0_626), .B1( + n_1_0_624), .B2(registers_10__ap[0]), .C1(n_1_0_622), .C2( + registers_30__ap[0]), .ZN(n_1_0_17)); + AOI22_X1_LVT i_1_0_17 (.A1(registers_29__ap[0]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[0]), .ZN(n_1_0_16)); + AOI22_X1_LVT i_1_0_16 (.A1(registers_1__ap[0]), .A2(n_1_0_644), .B1(n_1_0_616), + .B2(registers_6__ap[0]), .ZN(n_1_0_15)); + AOI22_X1_LVT i_1_0_15 (.A1(registers_27__ap[0]), .A2(n_1_0_636), .B1( + n_1_0_627), .B2(registers_15__ap[0]), .ZN(n_1_0_14)); + AOI22_X1_LVT i_1_0_14 (.A1(registers_23__ap[0]), .A2(n_1_0_615), .B1( + n_1_0_614), .B2(registers_16__ap[0]), .ZN(n_1_0_13)); + AOI22_X1_LVT i_1_0_13 (.A1(registers_31__ap[0]), .A2(n_1_0_637), .B1( + n_1_0_635), .B2(registers_5__ap[0]), .ZN(n_1_0_12)); + NAND4_X1_LVT i_1_0_12 (.A1(n_1_0_15), .A2(n_1_0_14), .A3(n_1_0_13), .A4( + n_1_0_12), .ZN(n_1_0_11)); + AOI22_X1_LVT i_1_0_11 (.A1(registers_18__ap[0]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[0]), .ZN(n_1_0_10)); + AOI22_X1_LVT i_1_0_10 (.A1(registers_12__ap[0]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[0]), .ZN(n_1_0_9)); + AOI22_X1_LVT i_1_0_9 (.A1(registers_22__ap[0]), .A2(n_1_0_642), .B1(n_1_0_612), + .B2(registers_21__ap[0]), .ZN(n_1_0_8)); + AOI22_X1_LVT i_1_0_8 (.A1(registers_17__ap[0]), .A2(n_1_0_629), .B1(n_1_0_613), + .B2(registers_20__ap[0]), .ZN(n_1_0_7)); + NAND4_X1_LVT i_1_0_7 (.A1(n_1_0_10), .A2(n_1_0_9), .A3(n_1_0_8), .A4(n_1_0_7), + .ZN(n_1_0_6)); + AOI22_X1_LVT i_1_0_6 (.A1(registers_13__ap[0]), .A2(n_1_0_631), .B1(n_1_0_620), + .B2(registers_25__ap[0]), .ZN(n_1_0_5)); + AOI22_X1_LVT i_1_0_5 (.A1(registers_7__ap[0]), .A2(n_1_0_623), .B1(n_1_0_619), + .B2(registers_14__ap[0]), .ZN(n_1_0_4)); + AOI22_X1_LVT i_1_0_4 (.A1(registers_19__ap[0]), .A2(n_1_0_633), .B1(n_1_0_610), + .B2(registers_3__ap[0]), .ZN(n_1_0_3)); + AOI22_X1_LVT i_1_0_3 (.A1(registers_2__ap[0]), .A2(n_1_0_618), .B1(n_1_0_611), + .B2(registers_11__ap[0]), .ZN(n_1_0_2)); + NAND4_X1_LVT i_1_0_2 (.A1(n_1_0_5), .A2(n_1_0_4), .A3(n_1_0_3), .A4(n_1_0_2), + .ZN(n_1_0_1)); + NOR3_X1_LVT i_1_0_1 (.A1(n_1_0_11), .A2(n_1_0_6), .A3(n_1_0_1), .ZN(n_1_0_0)); + NAND4_X1_LVT i_1_0_0 (.A1(n_1_0_18), .A2(n_1_0_17), .A3(n_1_0_16), .A4( + n_1_0_0), .ZN(RRs2[0])); +endmodule + +module MemGen_32_11(chip_en, clock, addr, rd_data, rd_en, wr_en, wr_data); + input chip_en; + input clock; + input [10:0]addr; + output [31:0]rd_data; + input rd_en; + input wr_en; + input [31:0]wr_data; + + wire [1:0]mem_sel; + + INV_X1_LVT i_1_3 (.A(addr[10]), .ZN(mem_sel[0])); + MemGen_16_10 genblk1_0_U_hi (.chip_en(mem_sel[0]), .wr_en(wr_en), .addr({ + addr[9], addr[8], addr[7], addr[6], addr[5], addr[4], addr[3], addr[2], + addr[1], addr[0]}), .wr_data({wr_data[31], wr_data[30], wr_data[29], + wr_data[28], wr_data[27], wr_data[26], wr_data[25], wr_data[24], + wr_data[23], wr_data[22], wr_data[21], wr_data[20], wr_data[19], + wr_data[18], wr_data[17], wr_data[16]}), .clock(clock), .rd_en(rd_en), + .rd_data({n_63, n_62, n_61, n_60, n_59, n_58, n_57, n_56, n_55, n_54, n_53, + n_52, n_51, n_50, n_49, n_48})); + MemGen_16_10 genblk1_1_U_hi (.chip_en(addr[10]), .wr_en(wr_en), .addr({ + addr[9], addr[8], addr[7], addr[6], addr[5], addr[4], addr[3], addr[2], + addr[1], addr[0]}), .wr_data({wr_data[31], wr_data[30], wr_data[29], + wr_data[28], wr_data[27], wr_data[26], wr_data[25], wr_data[24], + wr_data[23], wr_data[22], wr_data[21], wr_data[20], wr_data[19], + wr_data[18], wr_data[17], wr_data[16]}), .clock(clock), .rd_en(rd_en), + .rd_data({n_31, n_30, n_29, n_28, n_27, n_26, n_25, n_24, n_23, n_22, n_21, + n_20, n_19, n_18, n_17, n_16})); + MUX2_X1_LVT i_1_1_31 (.A(n_63), .B(n_31), .S(addr[10]), .Z(rd_data[31])); + MUX2_X1_LVT i_1_1_30 (.A(n_62), .B(n_30), .S(addr[10]), .Z(rd_data[30])); + MUX2_X1_LVT i_1_1_29 (.A(n_61), .B(n_29), .S(addr[10]), .Z(rd_data[29])); + MUX2_X1_LVT i_1_1_28 (.A(n_60), .B(n_28), .S(addr[10]), .Z(rd_data[28])); + MUX2_X1_LVT i_1_1_27 (.A(n_59), .B(n_27), .S(addr[10]), .Z(rd_data[27])); + MUX2_X1_LVT i_1_1_26 (.A(n_58), .B(n_26), .S(addr[10]), .Z(rd_data[26])); + MUX2_X1_LVT i_1_1_25 (.A(n_57), .B(n_25), .S(addr[10]), .Z(rd_data[25])); + MUX2_X1_LVT i_1_1_24 (.A(n_56), .B(n_24), .S(addr[10]), .Z(rd_data[24])); + MUX2_X1_LVT i_1_1_23 (.A(n_55), .B(n_23), .S(addr[10]), .Z(rd_data[23])); + MUX2_X1_LVT i_1_1_22 (.A(n_54), .B(n_22), .S(addr[10]), .Z(rd_data[22])); + MUX2_X1_LVT i_1_1_21 (.A(n_53), .B(n_21), .S(addr[10]), .Z(rd_data[21])); + MUX2_X1_LVT i_1_1_20 (.A(n_52), .B(n_20), .S(addr[10]), .Z(rd_data[20])); + MUX2_X1_LVT i_1_1_19 (.A(n_51), .B(n_19), .S(addr[10]), .Z(rd_data[19])); + MUX2_X1_LVT i_1_1_18 (.A(n_50), .B(n_18), .S(addr[10]), .Z(rd_data[18])); + MUX2_X1_LVT i_1_1_17 (.A(n_49), .B(n_17), .S(addr[10]), .Z(rd_data[17])); + MUX2_X1_LVT i_1_1_16 (.A(n_48), .B(n_16), .S(addr[10]), .Z(rd_data[16])); + MemGen_16_10 genblk1_0_U_lo (.chip_en(mem_sel[0]), .wr_en(wr_en), .addr({ + addr[9], addr[8], addr[7], addr[6], addr[5], addr[4], addr[3], addr[2], + addr[1], addr[0]}), .wr_data({wr_data[15], wr_data[14], wr_data[13], + wr_data[12], wr_data[11], wr_data[10], wr_data[9], wr_data[8], wr_data[7], + wr_data[6], wr_data[5], wr_data[4], wr_data[3], wr_data[2], wr_data[1], + wr_data[0]}), .clock(clock), .rd_en(rd_en), .rd_data({n_47, n_46, n_45, + n_44, n_43, n_42, n_41, n_40, n_39, n_38, n_37, n_36, n_35, n_34, n_33, + n_32})); + MemGen_16_10 genblk1_1_U_lo (.chip_en(addr[10]), .wr_en(wr_en), .addr({ + addr[9], addr[8], addr[7], addr[6], addr[5], addr[4], addr[3], addr[2], + addr[1], addr[0]}), .wr_data({wr_data[15], wr_data[14], wr_data[13], + wr_data[12], wr_data[11], wr_data[10], wr_data[9], wr_data[8], wr_data[7], + wr_data[6], wr_data[5], wr_data[4], wr_data[3], wr_data[2], wr_data[1], + wr_data[0]}), .clock(clock), .rd_en(rd_en), .rd_data({n_15, n_14, n_13, + n_12, n_11, n_10, n_9, n_8, n_7, n_6, n_5, n_4, n_3, n_2, n_1, n_0})); + MUX2_X1_LVT i_1_1_15 (.A(n_47), .B(n_15), .S(addr[10]), .Z(rd_data[15])); + MUX2_X1_LVT i_1_1_14 (.A(n_46), .B(n_14), .S(addr[10]), .Z(rd_data[14])); + MUX2_X1_LVT i_1_1_13 (.A(n_45), .B(n_13), .S(addr[10]), .Z(rd_data[13])); + MUX2_X1_LVT i_1_1_12 (.A(n_44), .B(n_12), .S(addr[10]), .Z(rd_data[12])); + MUX2_X1_LVT i_1_1_11 (.A(n_43), .B(n_11), .S(addr[10]), .Z(rd_data[11])); + MUX2_X1_LVT i_1_1_10 (.A(n_42), .B(n_10), .S(addr[10]), .Z(rd_data[10])); + MUX2_X1_LVT i_1_1_9 (.A(n_41), .B(n_9), .S(addr[10]), .Z(rd_data[9])); + MUX2_X1_LVT i_1_1_8 (.A(n_40), .B(n_8), .S(addr[10]), .Z(rd_data[8])); + MUX2_X1_LVT i_1_1_7 (.A(n_39), .B(n_7), .S(addr[10]), .Z(rd_data[7])); + MUX2_X1_LVT i_1_1_6 (.A(n_38), .B(n_6), .S(addr[10]), .Z(rd_data[6])); + MUX2_X1_LVT i_1_1_5 (.A(n_37), .B(n_5), .S(addr[10]), .Z(rd_data[5])); + MUX2_X1_LVT i_1_1_4 (.A(n_36), .B(n_4), .S(addr[10]), .Z(rd_data[4])); + MUX2_X1_LVT i_1_1_3 (.A(n_35), .B(n_3), .S(addr[10]), .Z(rd_data[3])); + MUX2_X1_LVT i_1_1_2 (.A(n_34), .B(n_2), .S(addr[10]), .Z(rd_data[2])); + MUX2_X1_LVT i_1_1_1 (.A(n_33), .B(n_1), .S(addr[10]), .Z(rd_data[1])); + MUX2_X1_LVT i_1_1_0 (.A(n_32), .B(n_0), .S(addr[10]), .Z(rd_data[0])); +endmodule + +module main_mem(clk, reset, DAddr, IAddr, DWData, DRData, IRData, DWE, DWidth); + input clk; + input reset; + input [31:0]DAddr; + input [31:0]IAddr; + input [31:0]DWData; + output [31:0]DRData; + output [31:0]IRData; + input DWE; + input [1:0]DWidth; + + wire [31:0]mem_rdata; + wire [10:0]mem_addr; + wire n_0_0; + wire n_0_0_0; + wire n_0_1; + wire n_0_0_1; + wire n_0_2; + wire n_0_0_2; + wire n_0_3; + wire n_0_0_3; + wire n_0_4; + wire n_0_0_4; + wire n_0_5; + wire n_0_0_5; + wire n_0_6; + wire n_0_0_6; + wire n_0_7; + wire n_0_0_7; + wire n_0_8; + wire n_0_0_8; + wire n_0_9; + wire n_0_0_9; + wire n_0_10; + wire n_0_0_10; + wire n_0_0_11; + wire n_0_11; + wire n_0_0_12; + wire n_0_0_13; + wire n_0_12; + wire n_0_0_14; + wire n_0_0_15; + wire n_0_13; + wire n_0_0_16; + wire n_0_0_17; + wire n_0_14; + wire n_0_0_18; + wire n_0_0_19; + wire n_0_15; + wire n_0_0_20; + wire n_0_0_21; + wire n_0_16; + wire n_0_0_22; + wire n_0_0_23; + wire n_0_17; + wire n_0_0_24; + wire n_0_0_25; + wire n_0_18; + wire n_0_0_26; + wire n_0_0_27; + wire n_0_0_28; + wire n_0_19; + wire n_0_0_29; + wire n_0_20; + wire n_0_0_30; + wire n_0_21; + wire n_0_0_31; + wire n_0_22; + wire n_0_0_32; + wire n_0_23; + wire n_0_0_33; + wire n_0_24; + wire n_0_0_34; + wire n_0_25; + wire n_0_0_35; + wire n_0_26; + wire n_0_0_36; + wire n_0_0_37; + wire n_0_27; + wire n_0_28; + wire n_0_29; + wire n_0_30; + wire n_0_31; + wire n_0_32; + wire n_0_33; + wire n_0_34; + wire n_0_35; + wire n_0_36; + wire n_0_37; + wire n_0_38; + wire n_0_39; + wire n_0_40; + wire n_0_41; + wire n_0_42; + wire n_0_65; + wire n_0_64; + wire n_0_63; + wire n_0_62; + wire n_0_61; + wire n_0_60; + wire n_0_59; + wire n_0_58; + wire n_0_0_38; + wire n_0_0_39; + wire n_0_57; + wire n_0_0_40; + wire n_0_56; + wire n_0_0_41; + wire n_0_55; + wire n_0_0_42; + wire n_0_54; + wire n_0_0_43; + wire n_0_53; + wire n_0_0_44; + wire n_0_52; + wire n_0_0_45; + wire n_0_51; + wire n_0_0_46; + wire n_0_50; + wire n_0_0_47; + wire n_0_0_48; + wire n_0_0_49; + wire n_0_0_50; + wire n_0_0_51; + wire n_0_49; + wire n_0_0_52; + wire n_0_48; + wire n_0_0_53; + wire n_0_47; + wire n_0_0_54; + wire n_0_46; + wire n_0_0_55; + wire n_0_45; + wire n_0_0_56; + wire n_0_44; + wire n_0_0_57; + wire n_0_66; + wire n_0_0_58; + wire n_0_67; + wire n_0_0_59; + wire n_0_0_60; + wire n_0_0_61; + wire n_0_68; + wire n_0_0_62; + wire n_0_0_63; + wire n_0_69; + wire n_0_0_64; + wire n_0_0_65; + wire n_0_70; + wire n_0_0_66; + wire n_0_0_67; + wire n_0_71; + wire n_0_0_68; + wire n_0_0_69; + wire n_0_72; + wire n_0_0_70; + wire n_0_0_71; + wire n_0_73; + wire n_0_0_72; + wire n_0_0_73; + wire n_0_74; + wire n_0_0_74; + wire n_0_0_75; + wire n_0_75; + wire n_0_0_76; + wire n_0_0_77; + wire n_0_0_78; + wire n_0_0_79; + wire n_0_0_80; + wire n_0_0_81; + wire n_0_0_82; + wire n_0_0_83; + wire n_0_0_84; + wire n_0_0_85; + wire n_0_0_86; + wire n_0_0_87; + wire n_0_0_88; + wire n_0_0_89; + wire n_0_0_90; + wire n_0_0_91; + wire n_0_0_92; + wire n_0_43; + wire n_0_0_93; + wire n_0_0_94; + wire n_0_76; + wire n_0_0_95; + wire [31:0]drTmp; + wire [31:0]mem_wdata; + + INV_X1_LVT i_0_0_171 (.A(DWE), .ZN(n_0)); + NOR2_X1_LVT i_0_0_163 (.A1(n_0), .A2(reset), .ZN(n_0_0_88)); + NOR2_X1_LVT i_0_0_22 (.A1(DWE), .A2(reset), .ZN(n_0_0_11)); + AOI22_X1_LVT i_0_0_21 (.A1(DAddr[12]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[12]), .ZN(n_0_0_10)); + INV_X1_LVT i_0_0_20 (.A(n_0_0_10), .ZN(n_0_10)); + INV_X1_LVT i_0_0_172 (.A(clk), .ZN(n_0_76)); + DFF_X1_LVT \mem_addr_reg[10] (.D(n_0_10), .CK(n_0_76), .Q(mem_addr[10]), + .QN()); + AOI22_X1_LVT i_0_0_19 (.A1(DAddr[11]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[11]), .ZN(n_0_0_9)); + INV_X1_LVT i_0_0_18 (.A(n_0_0_9), .ZN(n_0_9)); + DFF_X1_LVT \mem_addr_reg[9] (.D(n_0_9), .CK(n_0_76), .Q(mem_addr[9]), .QN()); + AOI22_X1_LVT i_0_0_17 (.A1(DAddr[10]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[10]), .ZN(n_0_0_8)); + INV_X1_LVT i_0_0_16 (.A(n_0_0_8), .ZN(n_0_8)); + DFF_X1_LVT \mem_addr_reg[8] (.D(n_0_8), .CK(n_0_76), .Q(mem_addr[8]), .QN()); + AOI22_X1_LVT i_0_0_15 (.A1(DAddr[9]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[9]), .ZN(n_0_0_7)); + INV_X1_LVT i_0_0_14 (.A(n_0_0_7), .ZN(n_0_7)); + DFF_X1_LVT \mem_addr_reg[7] (.D(n_0_7), .CK(n_0_76), .Q(mem_addr[7]), .QN()); + AOI22_X1_LVT i_0_0_13 (.A1(DAddr[8]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[8]), .ZN(n_0_0_6)); + INV_X1_LVT i_0_0_12 (.A(n_0_0_6), .ZN(n_0_6)); + DFF_X1_LVT \mem_addr_reg[6] (.D(n_0_6), .CK(n_0_76), .Q(mem_addr[6]), .QN()); + AOI22_X1_LVT i_0_0_11 (.A1(DAddr[7]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[7]), .ZN(n_0_0_5)); + INV_X1_LVT i_0_0_10 (.A(n_0_0_5), .ZN(n_0_5)); + DFF_X1_LVT \mem_addr_reg[5] (.D(n_0_5), .CK(n_0_76), .Q(mem_addr[5]), .QN()); + AOI22_X1_LVT i_0_0_9 (.A1(DAddr[6]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[6]), .ZN(n_0_0_4)); + INV_X1_LVT i_0_0_8 (.A(n_0_0_4), .ZN(n_0_4)); + DFF_X1_LVT \mem_addr_reg[4] (.D(n_0_4), .CK(n_0_76), .Q(mem_addr[4]), .QN()); + AOI22_X1_LVT i_0_0_7 (.A1(DAddr[5]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[5]), .ZN(n_0_0_3)); + INV_X1_LVT i_0_0_6 (.A(n_0_0_3), .ZN(n_0_3)); + DFF_X1_LVT \mem_addr_reg[3] (.D(n_0_3), .CK(n_0_76), .Q(mem_addr[3]), .QN()); + AOI22_X1_LVT i_0_0_5 (.A1(DAddr[4]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[4]), .ZN(n_0_0_2)); + INV_X1_LVT i_0_0_4 (.A(n_0_0_2), .ZN(n_0_2)); + DFF_X1_LVT \mem_addr_reg[2] (.D(n_0_2), .CK(n_0_76), .Q(mem_addr[2]), .QN()); + AOI22_X1_LVT i_0_0_3 (.A1(DAddr[3]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[3]), .ZN(n_0_0_1)); + INV_X1_LVT i_0_0_2 (.A(n_0_0_1), .ZN(n_0_1)); + DFF_X1_LVT \mem_addr_reg[1] (.D(n_0_1), .CK(n_0_76), .Q(mem_addr[1]), .QN()); + AOI22_X1_LVT i_0_0_1 (.A1(DAddr[2]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[2]), .ZN(n_0_0_0)); + INV_X1_LVT i_0_0_0 (.A(n_0_0_0), .ZN(n_0_0)); + DFF_X1_LVT \mem_addr_reg[0] (.D(n_0_0), .CK(n_0_76), .Q(mem_addr[0]), .QN()); + NOR2_X1_LVT i_0_0_162 (.A1(DWidth[1]), .A2(DAddr[1]), .ZN(n_0_0_87)); + NOR2_X1_LVT i_0_0_158 (.A1(DWidth[0]), .A2(DAddr[0]), .ZN(n_0_0_83)); + AND2_X1_LVT i_0_0_157 (.A1(n_0_0_87), .A2(n_0_0_83), .ZN(n_0_0_82)); + AND2_X1_LVT i_0_0_156 (.A1(n_0_0_88), .A2(n_0_0_82), .ZN(n_0_0_81)); + INV_X1_LVT i_0_0_173 (.A(n_0_0_88), .ZN(n_0_0_95)); + INV_X1_LVT i_0_0_169 (.A(DWidth[1]), .ZN(n_0_0_93)); + NOR3_X1_LVT i_0_0_155 (.A1(n_0_0_95), .A2(DWidth[0]), .A3(n_0_0_93), .ZN( + n_0_0_80)); + AOI22_X1_LVT i_0_0_154 (.A1(DWData[7]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[31]), .ZN(n_0_0_79)); + NAND2_X1_LVT i_0_0_168 (.A1(DWidth[0]), .A2(DWidth[1]), .ZN(n_0_43)); + INV_X1_LVT i_0_0_167 (.A(n_0_43), .ZN(n_0_0_92)); + NOR2_X1_LVT i_0_0_160 (.A1(n_0_0_95), .A2(n_0_0_92), .ZN(n_0_0_85)); + NAND2_X1_LVT i_0_0_161 (.A1(n_0_0_93), .A2(DAddr[1]), .ZN(n_0_0_86)); + NOR2_X1_LVT i_0_0_166 (.A1(DWidth[0]), .A2(DWidth[1]), .ZN(n_0_0_91)); + NAND2_X1_LVT i_0_0_164 (.A1(DAddr[0]), .A2(n_0_0_91), .ZN(n_0_0_89)); + NAND3_X1_LVT i_0_0_159 (.A1(n_0_0_85), .A2(n_0_0_86), .A3(n_0_0_89), .ZN( + n_0_0_84)); + INV_X1_LVT i_0_0_170 (.A(DWidth[0]), .ZN(n_0_0_94)); + NOR2_X1_LVT i_0_0_153 (.A1(n_0_0_94), .A2(DAddr[1]), .ZN(n_0_0_78)); + AND3_X1_LVT i_0_0_152 (.A1(n_0_0_88), .A2(n_0_0_78), .A3(n_0_0_93), .ZN( + n_0_0_77)); + AOI22_X1_LVT i_0_0_151 (.A1(n_0_0_84), .A2(mem_wdata[31]), .B1(DWData[15]), + .B2(n_0_0_77), .ZN(n_0_0_76)); + NAND2_X1_LVT i_0_0_150 (.A1(n_0_0_79), .A2(n_0_0_76), .ZN(n_0_75)); + DFF_X1_LVT \mem_wdata_reg[31] (.D(n_0_75), .CK(n_0_76), .Q(mem_wdata[31]), + .QN()); + AOI22_X1_LVT i_0_0_149 (.A1(DWData[6]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[30]), .ZN(n_0_0_75)); + AOI22_X1_LVT i_0_0_148 (.A1(n_0_0_84), .A2(mem_wdata[30]), .B1(DWData[14]), + .B2(n_0_0_77), .ZN(n_0_0_74)); + NAND2_X1_LVT i_0_0_147 (.A1(n_0_0_75), .A2(n_0_0_74), .ZN(n_0_74)); + DFF_X1_LVT \mem_wdata_reg[30] (.D(n_0_74), .CK(n_0_76), .Q(mem_wdata[30]), + .QN()); + AOI22_X1_LVT i_0_0_146 (.A1(DWData[5]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[29]), .ZN(n_0_0_73)); + AOI22_X1_LVT i_0_0_145 (.A1(n_0_0_84), .A2(mem_wdata[29]), .B1(DWData[13]), + .B2(n_0_0_77), .ZN(n_0_0_72)); + NAND2_X1_LVT i_0_0_144 (.A1(n_0_0_73), .A2(n_0_0_72), .ZN(n_0_73)); + DFF_X1_LVT \mem_wdata_reg[29] (.D(n_0_73), .CK(n_0_76), .Q(mem_wdata[29]), + .QN()); + AOI22_X1_LVT i_0_0_143 (.A1(DWData[4]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[28]), .ZN(n_0_0_71)); + AOI22_X1_LVT i_0_0_142 (.A1(n_0_0_84), .A2(mem_wdata[28]), .B1(DWData[12]), + .B2(n_0_0_77), .ZN(n_0_0_70)); + NAND2_X1_LVT i_0_0_141 (.A1(n_0_0_71), .A2(n_0_0_70), .ZN(n_0_72)); + DFF_X1_LVT \mem_wdata_reg[28] (.D(n_0_72), .CK(n_0_76), .Q(mem_wdata[28]), + .QN()); + AOI22_X1_LVT i_0_0_140 (.A1(DWData[3]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[27]), .ZN(n_0_0_69)); + AOI22_X1_LVT i_0_0_139 (.A1(n_0_0_84), .A2(mem_wdata[27]), .B1(DWData[11]), + .B2(n_0_0_77), .ZN(n_0_0_68)); + NAND2_X1_LVT i_0_0_138 (.A1(n_0_0_69), .A2(n_0_0_68), .ZN(n_0_71)); + DFF_X1_LVT \mem_wdata_reg[27] (.D(n_0_71), .CK(n_0_76), .Q(mem_wdata[27]), + .QN()); + AOI22_X1_LVT i_0_0_137 (.A1(DWData[2]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[26]), .ZN(n_0_0_67)); + AOI22_X1_LVT i_0_0_136 (.A1(n_0_0_84), .A2(mem_wdata[26]), .B1(DWData[10]), + .B2(n_0_0_77), .ZN(n_0_0_66)); + NAND2_X1_LVT i_0_0_135 (.A1(n_0_0_67), .A2(n_0_0_66), .ZN(n_0_70)); + DFF_X1_LVT \mem_wdata_reg[26] (.D(n_0_70), .CK(n_0_76), .Q(mem_wdata[26]), + .QN()); + AOI22_X1_LVT i_0_0_134 (.A1(DWData[1]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[25]), .ZN(n_0_0_65)); + AOI22_X1_LVT i_0_0_133 (.A1(n_0_0_84), .A2(mem_wdata[25]), .B1(DWData[9]), + .B2(n_0_0_77), .ZN(n_0_0_64)); + NAND2_X1_LVT i_0_0_132 (.A1(n_0_0_65), .A2(n_0_0_64), .ZN(n_0_69)); + DFF_X1_LVT \mem_wdata_reg[25] (.D(n_0_69), .CK(n_0_76), .Q(mem_wdata[25]), + .QN()); + AOI22_X1_LVT i_0_0_131 (.A1(DWData[0]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[24]), .ZN(n_0_0_63)); + AOI22_X1_LVT i_0_0_130 (.A1(n_0_0_84), .A2(mem_wdata[24]), .B1(DWData[8]), + .B2(n_0_0_77), .ZN(n_0_0_62)); + NAND2_X1_LVT i_0_0_129 (.A1(n_0_0_63), .A2(n_0_0_62), .ZN(n_0_68)); + DFF_X1_LVT \mem_wdata_reg[24] (.D(n_0_68), .CK(n_0_76), .Q(mem_wdata[24]), + .QN()); + NOR4_X1_LVT i_0_0_127 (.A1(n_0_0_95), .A2(n_0_0_83), .A3(DWidth[1]), .A4( + DAddr[1]), .ZN(n_0_0_60)); + INV_X1_LVT i_0_0_165 (.A(n_0_0_91), .ZN(n_0_0_90)); + OAI211_X1_LVT i_0_0_128 (.A(n_0_0_85), .B(n_0_0_86), .C1(n_0_0_90), .C2( + DAddr[0]), .ZN(n_0_0_61)); + AOI222_X1_LVT i_0_0_126 (.A1(DWData[7]), .A2(n_0_0_60), .B1(mem_wdata[23]), + .B2(n_0_0_61), .C1(DWData[23]), .C2(n_0_0_80), .ZN(n_0_0_59)); + INV_X1_LVT i_0_0_125 (.A(n_0_0_59), .ZN(n_0_67)); + DFF_X1_LVT \mem_wdata_reg[23] (.D(n_0_67), .CK(n_0_76), .Q(mem_wdata[23]), + .QN()); + AOI222_X1_LVT i_0_0_124 (.A1(DWData[6]), .A2(n_0_0_60), .B1(mem_wdata[22]), + .B2(n_0_0_61), .C1(DWData[22]), .C2(n_0_0_80), .ZN(n_0_0_58)); + INV_X1_LVT i_0_0_123 (.A(n_0_0_58), .ZN(n_0_66)); + DFF_X1_LVT \mem_wdata_reg[22] (.D(n_0_66), .CK(n_0_76), .Q(mem_wdata[22]), + .QN()); + AOI222_X1_LVT i_0_0_122 (.A1(DWData[5]), .A2(n_0_0_60), .B1(mem_wdata[21]), + .B2(n_0_0_61), .C1(DWData[21]), .C2(n_0_0_80), .ZN(n_0_0_57)); + INV_X1_LVT i_0_0_121 (.A(n_0_0_57), .ZN(n_0_44)); + DFF_X1_LVT \mem_wdata_reg[21] (.D(n_0_44), .CK(n_0_76), .Q(mem_wdata[21]), + .QN()); + AOI222_X1_LVT i_0_0_120 (.A1(DWData[4]), .A2(n_0_0_60), .B1(mem_wdata[20]), + .B2(n_0_0_61), .C1(DWData[20]), .C2(n_0_0_80), .ZN(n_0_0_56)); + INV_X1_LVT i_0_0_119 (.A(n_0_0_56), .ZN(n_0_45)); + DFF_X1_LVT \mem_wdata_reg[20] (.D(n_0_45), .CK(n_0_76), .Q(mem_wdata[20]), + .QN()); + AOI222_X1_LVT i_0_0_118 (.A1(DWData[3]), .A2(n_0_0_60), .B1(mem_wdata[19]), + .B2(n_0_0_61), .C1(DWData[19]), .C2(n_0_0_80), .ZN(n_0_0_55)); + INV_X1_LVT i_0_0_117 (.A(n_0_0_55), .ZN(n_0_46)); + DFF_X1_LVT \mem_wdata_reg[19] (.D(n_0_46), .CK(n_0_76), .Q(mem_wdata[19]), + .QN()); + AOI222_X1_LVT i_0_0_116 (.A1(DWData[2]), .A2(n_0_0_60), .B1(mem_wdata[18]), + .B2(n_0_0_61), .C1(DWData[18]), .C2(n_0_0_80), .ZN(n_0_0_54)); + INV_X1_LVT i_0_0_115 (.A(n_0_0_54), .ZN(n_0_47)); + DFF_X1_LVT \mem_wdata_reg[18] (.D(n_0_47), .CK(n_0_76), .Q(mem_wdata[18]), + .QN()); + AOI222_X1_LVT i_0_0_114 (.A1(DWData[1]), .A2(n_0_0_60), .B1(mem_wdata[17]), + .B2(n_0_0_61), .C1(DWData[17]), .C2(n_0_0_80), .ZN(n_0_0_53)); + INV_X1_LVT i_0_0_113 (.A(n_0_0_53), .ZN(n_0_48)); + DFF_X1_LVT \mem_wdata_reg[17] (.D(n_0_48), .CK(n_0_76), .Q(mem_wdata[17]), + .QN()); + AOI222_X1_LVT i_0_0_112 (.A1(DWData[0]), .A2(n_0_0_60), .B1(mem_wdata[16]), + .B2(n_0_0_61), .C1(DWData[16]), .C2(n_0_0_80), .ZN(n_0_0_52)); + INV_X1_LVT i_0_0_111 (.A(n_0_0_52), .ZN(n_0_49)); + DFF_X1_LVT \mem_wdata_reg[16] (.D(n_0_49), .CK(n_0_76), .Q(mem_wdata[16]), + .QN()); + NOR4_X1_LVT i_0_0_110 (.A1(n_0_0_95), .A2(n_0_0_87), .A3(n_0_0_92), .A4( + n_0_0_91), .ZN(n_0_0_51)); + NOR3_X1_LVT i_0_0_109 (.A1(n_0_0_86), .A2(DAddr[0]), .A3(DWidth[0]), .ZN( + n_0_0_50)); + AND2_X1_LVT i_0_0_108 (.A1(n_0_0_88), .A2(n_0_0_50), .ZN(n_0_0_49)); + OAI211_X1_LVT i_0_0_107 (.A(n_0_0_85), .B(n_0_0_89), .C1(DAddr[1]), .C2( + DWidth[1]), .ZN(n_0_0_48)); + AOI222_X1_LVT i_0_0_106 (.A1(DWData[15]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[7]), .C1(n_0_0_48), .C2(mem_wdata[15]), .ZN(n_0_0_47)); + INV_X1_LVT i_0_0_105 (.A(n_0_0_47), .ZN(n_0_50)); + DFF_X1_LVT \mem_wdata_reg[15] (.D(n_0_50), .CK(n_0_76), .Q(mem_wdata[15]), + .QN()); + AOI222_X1_LVT i_0_0_104 (.A1(DWData[14]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[6]), .C1(n_0_0_48), .C2(mem_wdata[14]), .ZN(n_0_0_46)); + INV_X1_LVT i_0_0_103 (.A(n_0_0_46), .ZN(n_0_51)); + DFF_X1_LVT \mem_wdata_reg[14] (.D(n_0_51), .CK(n_0_76), .Q(mem_wdata[14]), + .QN()); + AOI222_X1_LVT i_0_0_102 (.A1(DWData[13]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[5]), .C1(n_0_0_48), .C2(mem_wdata[13]), .ZN(n_0_0_45)); + INV_X1_LVT i_0_0_101 (.A(n_0_0_45), .ZN(n_0_52)); + DFF_X1_LVT \mem_wdata_reg[13] (.D(n_0_52), .CK(n_0_76), .Q(mem_wdata[13]), + .QN()); + AOI222_X1_LVT i_0_0_100 (.A1(DWData[12]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[4]), .C1(n_0_0_48), .C2(mem_wdata[12]), .ZN(n_0_0_44)); + INV_X1_LVT i_0_0_99 (.A(n_0_0_44), .ZN(n_0_53)); + DFF_X1_LVT \mem_wdata_reg[12] (.D(n_0_53), .CK(n_0_76), .Q(mem_wdata[12]), + .QN()); + AOI222_X1_LVT i_0_0_98 (.A1(DWData[11]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[3]), .C1(n_0_0_48), .C2(mem_wdata[11]), .ZN(n_0_0_43)); + INV_X1_LVT i_0_0_97 (.A(n_0_0_43), .ZN(n_0_54)); + DFF_X1_LVT \mem_wdata_reg[11] (.D(n_0_54), .CK(n_0_76), .Q(mem_wdata[11]), + .QN()); + AOI222_X1_LVT i_0_0_96 (.A1(DWData[10]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[2]), .C1(n_0_0_48), .C2(mem_wdata[10]), .ZN(n_0_0_42)); + INV_X1_LVT i_0_0_95 (.A(n_0_0_42), .ZN(n_0_55)); + DFF_X1_LVT \mem_wdata_reg[10] (.D(n_0_55), .CK(n_0_76), .Q(mem_wdata[10]), + .QN()); + AOI222_X1_LVT i_0_0_94 (.A1(DWData[9]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[1]), .C1(n_0_0_48), .C2(mem_wdata[9]), .ZN(n_0_0_41)); + INV_X1_LVT i_0_0_93 (.A(n_0_0_41), .ZN(n_0_56)); + DFF_X1_LVT \mem_wdata_reg[9] (.D(n_0_56), .CK(n_0_76), .Q(mem_wdata[9]), + .QN()); + AOI222_X1_LVT i_0_0_92 (.A1(DWData[8]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[0]), .C1(n_0_0_48), .C2(mem_wdata[8]), .ZN(n_0_0_40)); + INV_X1_LVT i_0_0_91 (.A(n_0_0_40), .ZN(n_0_57)); + DFF_X1_LVT \mem_wdata_reg[8] (.D(n_0_57), .CK(n_0_76), .Q(mem_wdata[8]), + .QN()); + AOI21_X1_LVT i_0_0_90 (.A(n_0_0_87), .B1(n_0_0_83), .B2(n_0_0_93), .ZN( + n_0_0_39)); + NAND2_X1_LVT i_0_0_89 (.A1(n_0_0_85), .A2(n_0_0_39), .ZN(n_0_0_38)); + MUX2_X1_LVT i_0_0_88 (.A(DWData[7]), .B(mem_wdata[7]), .S(n_0_0_38), .Z( + n_0_58)); + DFF_X1_LVT \mem_wdata_reg[7] (.D(n_0_58), .CK(n_0_76), .Q(mem_wdata[7]), + .QN()); + MUX2_X1_LVT i_0_0_87 (.A(DWData[6]), .B(mem_wdata[6]), .S(n_0_0_38), .Z( + n_0_59)); + DFF_X1_LVT \mem_wdata_reg[6] (.D(n_0_59), .CK(n_0_76), .Q(mem_wdata[6]), + .QN()); + MUX2_X1_LVT i_0_0_86 (.A(DWData[5]), .B(mem_wdata[5]), .S(n_0_0_38), .Z( + n_0_60)); + DFF_X1_LVT \mem_wdata_reg[5] (.D(n_0_60), .CK(n_0_76), .Q(mem_wdata[5]), + .QN()); + MUX2_X1_LVT i_0_0_85 (.A(DWData[4]), .B(mem_wdata[4]), .S(n_0_0_38), .Z( + n_0_61)); + DFF_X1_LVT \mem_wdata_reg[4] (.D(n_0_61), .CK(n_0_76), .Q(mem_wdata[4]), + .QN()); + MUX2_X1_LVT i_0_0_84 (.A(DWData[3]), .B(mem_wdata[3]), .S(n_0_0_38), .Z( + n_0_62)); + DFF_X1_LVT \mem_wdata_reg[3] (.D(n_0_62), .CK(n_0_76), .Q(mem_wdata[3]), + .QN()); + MUX2_X1_LVT i_0_0_83 (.A(DWData[2]), .B(mem_wdata[2]), .S(n_0_0_38), .Z( + n_0_63)); + DFF_X1_LVT \mem_wdata_reg[2] (.D(n_0_63), .CK(n_0_76), .Q(mem_wdata[2]), + .QN()); + MUX2_X1_LVT i_0_0_82 (.A(DWData[1]), .B(mem_wdata[1]), .S(n_0_0_38), .Z( + n_0_64)); + DFF_X1_LVT \mem_wdata_reg[1] (.D(n_0_64), .CK(n_0_76), .Q(mem_wdata[1]), + .QN()); + MUX2_X1_LVT i_0_0_81 (.A(DWData[0]), .B(mem_wdata[0]), .S(n_0_0_38), .Z( + n_0_65)); + DFF_X1_LVT \mem_wdata_reg[0] (.D(n_0_65), .CK(n_0_76), .Q(mem_wdata[0]), + .QN()); + MemGen_32_11 RAM (.chip_en(), .clock(clk), .addr(mem_addr), .rd_data( + mem_rdata), .rd_en(n_0), .wr_en(DWE), .wr_data(mem_wdata)); + DFF_X1_LVT \drTmp_reg[31] (.D(mem_rdata[31]), .CK(n_0_76), .Q(drTmp[31]), + .QN()); + AND2_X1_LVT i_0_0_80 (.A1(DWidth[1]), .A2(drTmp[31]), .ZN(n_0_42)); + DLH_X1_LVT \DRData[31] (.D(n_0_42), .G(n_0_43), .Q(DRData[31])); + DFF_X1_LVT \drTmp_reg[30] (.D(mem_rdata[30]), .CK(n_0_76), .Q(drTmp[30]), + .QN()); + AND2_X1_LVT i_0_0_79 (.A1(DWidth[1]), .A2(drTmp[30]), .ZN(n_0_41)); + DLH_X1_LVT \DRData[30] (.D(n_0_41), .G(n_0_43), .Q(DRData[30])); + DFF_X1_LVT \drTmp_reg[29] (.D(mem_rdata[29]), .CK(n_0_76), .Q(drTmp[29]), + .QN()); + AND2_X1_LVT i_0_0_78 (.A1(DWidth[1]), .A2(drTmp[29]), .ZN(n_0_40)); + DLH_X1_LVT \DRData[29] (.D(n_0_40), .G(n_0_43), .Q(DRData[29])); + DFF_X1_LVT \drTmp_reg[28] (.D(mem_rdata[28]), .CK(n_0_76), .Q(drTmp[28]), + .QN()); + AND2_X1_LVT i_0_0_77 (.A1(DWidth[1]), .A2(drTmp[28]), .ZN(n_0_39)); + DLH_X1_LVT \DRData[28] (.D(n_0_39), .G(n_0_43), .Q(DRData[28])); + DFF_X1_LVT \drTmp_reg[27] (.D(mem_rdata[27]), .CK(n_0_76), .Q(drTmp[27]), + .QN()); + AND2_X1_LVT i_0_0_76 (.A1(DWidth[1]), .A2(drTmp[27]), .ZN(n_0_38)); + DLH_X1_LVT \DRData[27] (.D(n_0_38), .G(n_0_43), .Q(DRData[27])); + DFF_X1_LVT \drTmp_reg[26] (.D(mem_rdata[26]), .CK(n_0_76), .Q(drTmp[26]), + .QN()); + AND2_X1_LVT i_0_0_75 (.A1(DWidth[1]), .A2(drTmp[26]), .ZN(n_0_37)); + DLH_X1_LVT \DRData[26] (.D(n_0_37), .G(n_0_43), .Q(DRData[26])); + DFF_X1_LVT \drTmp_reg[25] (.D(mem_rdata[25]), .CK(n_0_76), .Q(drTmp[25]), + .QN()); + AND2_X1_LVT i_0_0_74 (.A1(DWidth[1]), .A2(drTmp[25]), .ZN(n_0_36)); + DLH_X1_LVT \DRData[25] (.D(n_0_36), .G(n_0_43), .Q(DRData[25])); + DFF_X1_LVT \drTmp_reg[24] (.D(mem_rdata[24]), .CK(n_0_76), .Q(drTmp[24]), + .QN()); + AND2_X1_LVT i_0_0_73 (.A1(DWidth[1]), .A2(drTmp[24]), .ZN(n_0_35)); + DLH_X1_LVT \DRData[24] (.D(n_0_35), .G(n_0_43), .Q(DRData[24])); + DFF_X1_LVT \drTmp_reg[23] (.D(mem_rdata[23]), .CK(n_0_76), .Q(drTmp[23]), + .QN()); + AND2_X1_LVT i_0_0_72 (.A1(DWidth[1]), .A2(drTmp[23]), .ZN(n_0_34)); + DLH_X1_LVT \DRData[23] (.D(n_0_34), .G(n_0_43), .Q(DRData[23])); + DFF_X1_LVT \drTmp_reg[22] (.D(mem_rdata[22]), .CK(n_0_76), .Q(drTmp[22]), + .QN()); + AND2_X1_LVT i_0_0_71 (.A1(DWidth[1]), .A2(drTmp[22]), .ZN(n_0_33)); + DLH_X1_LVT \DRData[22] (.D(n_0_33), .G(n_0_43), .Q(DRData[22])); + DFF_X1_LVT \drTmp_reg[21] (.D(mem_rdata[21]), .CK(n_0_76), .Q(drTmp[21]), + .QN()); + AND2_X1_LVT i_0_0_70 (.A1(DWidth[1]), .A2(drTmp[21]), .ZN(n_0_32)); + DLH_X1_LVT \DRData[21] (.D(n_0_32), .G(n_0_43), .Q(DRData[21])); + DFF_X1_LVT \drTmp_reg[20] (.D(mem_rdata[20]), .CK(n_0_76), .Q(drTmp[20]), + .QN()); + AND2_X1_LVT i_0_0_69 (.A1(DWidth[1]), .A2(drTmp[20]), .ZN(n_0_31)); + DLH_X1_LVT \DRData[20] (.D(n_0_31), .G(n_0_43), .Q(DRData[20])); + DFF_X1_LVT \drTmp_reg[19] (.D(mem_rdata[19]), .CK(n_0_76), .Q(drTmp[19]), + .QN()); + AND2_X1_LVT i_0_0_68 (.A1(DWidth[1]), .A2(drTmp[19]), .ZN(n_0_30)); + DLH_X1_LVT \DRData[19] (.D(n_0_30), .G(n_0_43), .Q(DRData[19])); + DFF_X1_LVT \drTmp_reg[18] (.D(mem_rdata[18]), .CK(n_0_76), .Q(drTmp[18]), + .QN()); + AND2_X1_LVT i_0_0_67 (.A1(DWidth[1]), .A2(drTmp[18]), .ZN(n_0_29)); + DLH_X1_LVT \DRData[18] (.D(n_0_29), .G(n_0_43), .Q(DRData[18])); + DFF_X1_LVT \drTmp_reg[17] (.D(mem_rdata[17]), .CK(n_0_76), .Q(drTmp[17]), + .QN()); + AND2_X1_LVT i_0_0_66 (.A1(DWidth[1]), .A2(drTmp[17]), .ZN(n_0_28)); + DLH_X1_LVT \DRData[17] (.D(n_0_28), .G(n_0_43), .Q(DRData[17])); + DFF_X1_LVT \drTmp_reg[16] (.D(mem_rdata[16]), .CK(n_0_76), .Q(drTmp[16]), + .QN()); + AND2_X1_LVT i_0_0_65 (.A1(DWidth[1]), .A2(drTmp[16]), .ZN(n_0_27)); + DLH_X1_LVT \DRData[16] (.D(n_0_27), .G(n_0_43), .Q(DRData[16])); + NOR2_X1_LVT i_0_0_64 (.A1(n_0_0_91), .A2(n_0_0_87), .ZN(n_0_0_37)); + DFF_X1_LVT \drTmp_reg[15] (.D(mem_rdata[15]), .CK(n_0_76), .Q(drTmp[15]), + .QN()); + AOI22_X1_LVT i_0_0_63 (.A1(drTmp[31]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[15]), .ZN(n_0_0_36)); + INV_X1_LVT i_0_0_62 (.A(n_0_0_36), .ZN(n_0_26)); + DLH_X1_LVT \DRData[15] (.D(n_0_26), .G(n_0_43), .Q(DRData[15])); + DFF_X1_LVT \drTmp_reg[14] (.D(mem_rdata[14]), .CK(n_0_76), .Q(drTmp[14]), + .QN()); + AOI22_X1_LVT i_0_0_61 (.A1(drTmp[30]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[14]), .ZN(n_0_0_35)); + INV_X1_LVT i_0_0_60 (.A(n_0_0_35), .ZN(n_0_25)); + DLH_X1_LVT \DRData[14] (.D(n_0_25), .G(n_0_43), .Q(DRData[14])); + DFF_X1_LVT \drTmp_reg[13] (.D(mem_rdata[13]), .CK(n_0_76), .Q(drTmp[13]), + .QN()); + AOI22_X1_LVT i_0_0_59 (.A1(drTmp[29]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[13]), .ZN(n_0_0_34)); + INV_X1_LVT i_0_0_58 (.A(n_0_0_34), .ZN(n_0_24)); + DLH_X1_LVT \DRData[13] (.D(n_0_24), .G(n_0_43), .Q(DRData[13])); + DFF_X1_LVT \drTmp_reg[12] (.D(mem_rdata[12]), .CK(n_0_76), .Q(drTmp[12]), + .QN()); + AOI22_X1_LVT i_0_0_57 (.A1(drTmp[28]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[12]), .ZN(n_0_0_33)); + INV_X1_LVT i_0_0_56 (.A(n_0_0_33), .ZN(n_0_23)); + DLH_X1_LVT \DRData[12] (.D(n_0_23), .G(n_0_43), .Q(DRData[12])); + DFF_X1_LVT \drTmp_reg[11] (.D(mem_rdata[11]), .CK(n_0_76), .Q(drTmp[11]), + .QN()); + AOI22_X1_LVT i_0_0_55 (.A1(drTmp[27]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[11]), .ZN(n_0_0_32)); + INV_X1_LVT i_0_0_54 (.A(n_0_0_32), .ZN(n_0_22)); + DLH_X1_LVT \DRData[11] (.D(n_0_22), .G(n_0_43), .Q(DRData[11])); + DFF_X1_LVT \drTmp_reg[10] (.D(mem_rdata[10]), .CK(n_0_76), .Q(drTmp[10]), + .QN()); + AOI22_X1_LVT i_0_0_53 (.A1(drTmp[26]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[10]), .ZN(n_0_0_31)); + INV_X1_LVT i_0_0_52 (.A(n_0_0_31), .ZN(n_0_21)); + DLH_X1_LVT \DRData[10] (.D(n_0_21), .G(n_0_43), .Q(DRData[10])); + DFF_X1_LVT \drTmp_reg[9] (.D(mem_rdata[9]), .CK(n_0_76), .Q(drTmp[9]), .QN()); + AOI22_X1_LVT i_0_0_51 (.A1(drTmp[25]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[9]), .ZN(n_0_0_30)); + INV_X1_LVT i_0_0_50 (.A(n_0_0_30), .ZN(n_0_20)); + DLH_X1_LVT \DRData[9] (.D(n_0_20), .G(n_0_43), .Q(DRData[9])); + DFF_X1_LVT \drTmp_reg[8] (.D(mem_rdata[8]), .CK(n_0_76), .Q(drTmp[8]), .QN()); + AOI22_X1_LVT i_0_0_49 (.A1(drTmp[24]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[8]), .ZN(n_0_0_29)); + INV_X1_LVT i_0_0_48 (.A(n_0_0_29), .ZN(n_0_19)); + DLH_X1_LVT \DRData[8] (.D(n_0_19), .G(n_0_43), .Q(DRData[8])); + AOI22_X1_LVT i_0_0_46 (.A1(drTmp[31]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[15]), .ZN(n_0_0_27)); + AOI211_X1_LVT i_0_0_47 (.A(DAddr[1]), .B(n_0_0_83), .C1(n_0_0_94), .C2( + DWidth[1]), .ZN(n_0_0_28)); + DFF_X1_LVT \drTmp_reg[7] (.D(mem_rdata[7]), .CK(n_0_76), .Q(drTmp[7]), .QN()); + AOI22_X1_LVT i_0_0_45 (.A1(drTmp[23]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[7]), .ZN(n_0_0_26)); + NAND2_X1_LVT i_0_0_44 (.A1(n_0_0_27), .A2(n_0_0_26), .ZN(n_0_18)); + DLH_X1_LVT \DRData[7] (.D(n_0_18), .G(n_0_43), .Q(DRData[7])); + AOI22_X1_LVT i_0_0_43 (.A1(drTmp[30]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[14]), .ZN(n_0_0_25)); + DFF_X1_LVT \drTmp_reg[6] (.D(mem_rdata[6]), .CK(n_0_76), .Q(drTmp[6]), .QN()); + AOI22_X1_LVT i_0_0_42 (.A1(drTmp[22]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[6]), .ZN(n_0_0_24)); + NAND2_X1_LVT i_0_0_41 (.A1(n_0_0_25), .A2(n_0_0_24), .ZN(n_0_17)); + DLH_X1_LVT \DRData[6] (.D(n_0_17), .G(n_0_43), .Q(DRData[6])); + AOI22_X1_LVT i_0_0_40 (.A1(drTmp[29]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[13]), .ZN(n_0_0_23)); + DFF_X1_LVT \drTmp_reg[5] (.D(mem_rdata[5]), .CK(n_0_76), .Q(drTmp[5]), .QN()); + AOI22_X1_LVT i_0_0_39 (.A1(drTmp[21]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[5]), .ZN(n_0_0_22)); + NAND2_X1_LVT i_0_0_38 (.A1(n_0_0_23), .A2(n_0_0_22), .ZN(n_0_16)); + DLH_X1_LVT \DRData[5] (.D(n_0_16), .G(n_0_43), .Q(DRData[5])); + AOI22_X1_LVT i_0_0_37 (.A1(drTmp[28]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[12]), .ZN(n_0_0_21)); + DFF_X1_LVT \drTmp_reg[4] (.D(mem_rdata[4]), .CK(n_0_76), .Q(drTmp[4]), .QN()); + AOI22_X1_LVT i_0_0_36 (.A1(drTmp[20]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[4]), .ZN(n_0_0_20)); + NAND2_X1_LVT i_0_0_35 (.A1(n_0_0_21), .A2(n_0_0_20), .ZN(n_0_15)); + DLH_X1_LVT \DRData[4] (.D(n_0_15), .G(n_0_43), .Q(DRData[4])); + AOI22_X1_LVT i_0_0_34 (.A1(drTmp[27]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[11]), .ZN(n_0_0_19)); + DFF_X1_LVT \drTmp_reg[3] (.D(mem_rdata[3]), .CK(n_0_76), .Q(drTmp[3]), .QN()); + AOI22_X1_LVT i_0_0_33 (.A1(drTmp[19]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[3]), .ZN(n_0_0_18)); + NAND2_X1_LVT i_0_0_32 (.A1(n_0_0_19), .A2(n_0_0_18), .ZN(n_0_14)); + DLH_X1_LVT \DRData[3] (.D(n_0_14), .G(n_0_43), .Q(DRData[3])); + AOI22_X1_LVT i_0_0_31 (.A1(drTmp[26]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[10]), .ZN(n_0_0_17)); + DFF_X1_LVT \drTmp_reg[2] (.D(mem_rdata[2]), .CK(n_0_76), .Q(drTmp[2]), .QN()); + AOI22_X1_LVT i_0_0_30 (.A1(drTmp[18]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[2]), .ZN(n_0_0_16)); + NAND2_X1_LVT i_0_0_29 (.A1(n_0_0_17), .A2(n_0_0_16), .ZN(n_0_13)); + DLH_X1_LVT \DRData[2] (.D(n_0_13), .G(n_0_43), .Q(DRData[2])); + AOI22_X1_LVT i_0_0_28 (.A1(drTmp[25]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[9]), .ZN(n_0_0_15)); + DFF_X1_LVT \drTmp_reg[1] (.D(mem_rdata[1]), .CK(n_0_76), .Q(drTmp[1]), .QN()); + AOI22_X1_LVT i_0_0_27 (.A1(drTmp[17]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[1]), .ZN(n_0_0_14)); + NAND2_X1_LVT i_0_0_26 (.A1(n_0_0_15), .A2(n_0_0_14), .ZN(n_0_12)); + DLH_X1_LVT \DRData[1] (.D(n_0_12), .G(n_0_43), .Q(DRData[1])); + AOI22_X1_LVT i_0_0_25 (.A1(drTmp[24]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[8]), .ZN(n_0_0_13)); + DFF_X1_LVT \drTmp_reg[0] (.D(mem_rdata[0]), .CK(n_0_76), .Q(drTmp[0]), .QN()); + AOI22_X1_LVT i_0_0_24 (.A1(drTmp[16]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[0]), .ZN(n_0_0_12)); + NAND2_X1_LVT i_0_0_23 (.A1(n_0_0_13), .A2(n_0_0_12), .ZN(n_0_11)); + DLH_X1_LVT \DRData[0] (.D(n_0_11), .G(n_0_43), .Q(DRData[0])); + DFF_X1_LVT \IRData_reg[31] (.D(mem_rdata[31]), .CK(clk), .Q(IRData[31]), + .QN()); + DFF_X1_LVT \IRData_reg[30] (.D(mem_rdata[30]), .CK(clk), .Q(IRData[30]), + .QN()); + DFF_X1_LVT \IRData_reg[29] (.D(mem_rdata[29]), .CK(clk), .Q(IRData[29]), + .QN()); + DFF_X1_LVT \IRData_reg[28] (.D(mem_rdata[28]), .CK(clk), .Q(IRData[28]), + .QN()); + DFF_X1_LVT \IRData_reg[27] (.D(mem_rdata[27]), .CK(clk), .Q(IRData[27]), + .QN()); + DFF_X1_LVT \IRData_reg[26] (.D(mem_rdata[26]), .CK(clk), .Q(IRData[26]), + .QN()); + DFF_X1_LVT \IRData_reg[25] (.D(mem_rdata[25]), .CK(clk), .Q(IRData[25]), + .QN()); + DFF_X1_LVT \IRData_reg[24] (.D(mem_rdata[24]), .CK(clk), .Q(IRData[24]), + .QN()); + DFF_X1_LVT \IRData_reg[23] (.D(mem_rdata[23]), .CK(clk), .Q(IRData[23]), + .QN()); + DFF_X1_LVT \IRData_reg[22] (.D(mem_rdata[22]), .CK(clk), .Q(IRData[22]), + .QN()); + DFF_X1_LVT \IRData_reg[21] (.D(mem_rdata[21]), .CK(clk), .Q(IRData[21]), + .QN()); + DFF_X1_LVT \IRData_reg[20] (.D(mem_rdata[20]), .CK(clk), .Q(IRData[20]), + .QN()); + DFF_X1_LVT \IRData_reg[19] (.D(mem_rdata[19]), .CK(clk), .Q(IRData[19]), + .QN()); + DFF_X1_LVT \IRData_reg[18] (.D(mem_rdata[18]), .CK(clk), .Q(IRData[18]), + .QN()); + DFF_X1_LVT \IRData_reg[17] (.D(mem_rdata[17]), .CK(clk), .Q(IRData[17]), + .QN()); + DFF_X1_LVT \IRData_reg[16] (.D(mem_rdata[16]), .CK(clk), .Q(IRData[16]), + .QN()); + DFF_X1_LVT \IRData_reg[15] (.D(mem_rdata[15]), .CK(clk), .Q(IRData[15]), + .QN()); + DFF_X1_LVT \IRData_reg[14] (.D(mem_rdata[14]), .CK(clk), .Q(IRData[14]), + .QN()); + DFF_X1_LVT \IRData_reg[13] (.D(mem_rdata[13]), .CK(clk), .Q(IRData[13]), + .QN()); + DFF_X1_LVT \IRData_reg[12] (.D(mem_rdata[12]), .CK(clk), .Q(IRData[12]), + .QN()); + DFF_X1_LVT \IRData_reg[11] (.D(mem_rdata[11]), .CK(clk), .Q(IRData[11]), + .QN()); + DFF_X1_LVT \IRData_reg[10] (.D(mem_rdata[10]), .CK(clk), .Q(IRData[10]), + .QN()); + DFF_X1_LVT \IRData_reg[9] (.D(mem_rdata[9]), .CK(clk), .Q(IRData[9]), .QN()); + DFF_X1_LVT \IRData_reg[8] (.D(mem_rdata[8]), .CK(clk), .Q(IRData[8]), .QN()); + DFF_X1_LVT \IRData_reg[7] (.D(mem_rdata[7]), .CK(clk), .Q(IRData[7]), .QN()); + DFF_X1_LVT \IRData_reg[6] (.D(mem_rdata[6]), .CK(clk), .Q(IRData[6]), .QN()); + DFF_X1_LVT \IRData_reg[5] (.D(mem_rdata[5]), .CK(clk), .Q(IRData[5]), .QN()); + DFF_X1_LVT \IRData_reg[4] (.D(mem_rdata[4]), .CK(clk), .Q(IRData[4]), .QN()); + DFF_X1_LVT \IRData_reg[3] (.D(mem_rdata[3]), .CK(clk), .Q(IRData[3]), .QN()); + DFF_X1_LVT \IRData_reg[2] (.D(mem_rdata[2]), .CK(clk), .Q(IRData[2]), .QN()); + DFF_X1_LVT \IRData_reg[1] (.D(mem_rdata[1]), .CK(clk), .Q(IRData[1]), .QN()); + DFF_X1_LVT \IRData_reg[0] (.D(mem_rdata[0]), .CK(clk), .Q(IRData[0]), .QN()); +endmodule + +module alu(aluOp, aluNegAr, aluBypass, op1, op2, result, eqFlag); + input [2:0]aluOp; + input aluNegAr; + input aluBypass; + input [31:0]op1; + input [31:0]op2; + output [31:0]result; + output eqFlag; + + wire n_9_0; + wire n_9_1; + wire n_9_2; + wire n_9_3; + wire n_9_4; + wire n_9_5; + wire n_9_6; + wire n_9_7; + wire n_9_8; + wire n_9_9; + wire n_9_10; + wire n_9_11; + wire n_9_12; + wire n_9_13; + wire n_9_14; + wire n_9_15; + wire n_9_16; + wire n_9_17; + wire n_9_18; + wire n_9_19; + wire n_9_20; + wire n_9_21; + wire n_9_22; + wire n_9_23; + wire n_9_24; + wire n_9_25; + wire n_9_26; + wire n_9_27; + wire n_9_28; + wire n_9_29; + wire n_9_30; + wire n_9_31; + wire n_10_0; + wire n_10_1; + wire n_10_2; + wire n_10_3; + wire n_10_4; + wire n_10_5; + wire n_10_6; + wire n_10_7; + wire n_10_8; + wire n_10_9; + wire n_10_10; + wire n_10_11; + wire n_10_12; + wire n_10_13; + wire n_10_14; + wire n_10_15; + wire n_10_16; + wire n_10_17; + wire n_10_18; + wire n_10_19; + wire n_10_20; + wire n_10_21; + wire n_10_22; + wire n_10_23; + wire n_10_24; + wire n_10_25; + wire n_10_26; + wire n_10_27; + wire n_10_28; + wire n_10_29; + wire n_10_30; + wire n_10_31; + wire n_10_32; + wire n_10_33; + wire n_10_34; + wire n_10_35; + wire n_10_36; + wire n_10_37; + wire n_10_38; + wire n_10_39; + wire n_10_40; + wire n_10_41; + wire n_10_42; + wire n_10_43; + wire n_10_44; + wire n_10_45; + wire n_10_46; + wire n_10_47; + wire n_10_48; + wire n_10_49; + wire n_10_50; + wire n_10_51; + wire n_10_52; + wire n_10_53; + wire n_10_54; + wire n_10_55; + wire n_10_56; + wire n_10_57; + wire n_10_58; + wire n_10_59; + wire n_10_60; + wire n_10_61; + wire n_10_62; + wire n_10_63; + wire n_10_64; + wire n_10_65; + wire n_10_66; + wire n_10_67; + wire n_10_68; + wire n_10_69; + wire n_10_70; + wire n_10_71; + wire n_10_72; + wire n_10_73; + wire n_10_74; + wire n_10_75; + wire n_10_76; + wire n_10_77; + wire n_10_78; + wire n_10_79; + wire n_10_80; + wire n_10_81; + wire n_10_82; + wire n_10_83; + wire n_10_84; + wire n_10_85; + wire n_10_86; + wire n_10_87; + wire n_10_88; + wire n_10_89; + wire n_10_90; + wire n_10_91; + wire n_10_92; + wire n_10_93; + wire n_10_94; + wire n_10_95; + wire n_10_96; + wire n_10_97; + wire n_10_98; + wire n_10_99; + wire n_10_100; + wire n_10_101; + wire n_10_102; + wire n_10_103; + wire n_10_104; + wire n_10_105; + wire n_10_106; + wire n_10_107; + wire n_10_108; + wire n_10_109; + wire n_10_110; + wire n_10_111; + wire n_10_112; + wire n_10_113; + wire n_10_114; + wire n_10_115; + wire n_10_116; + wire n_10_117; + wire n_10_118; + wire n_10_119; + wire n_10_120; + wire n_10_121; + wire n_10_122; + wire n_10_123; + wire n_0_0; + wire n_0_1; + wire n_0_2; + wire n_0_3; + wire n_0_4; + wire n_0_5; + wire n_0_6; + wire n_0_7; + wire n_0_8; + wire n_0_9; + wire n_0_10; + wire n_0_11; + wire n_0_12; + wire n_0_13; + wire n_0_14; + wire n_0_15; + wire n_0_16; + wire n_0_17; + wire n_0_18; + wire n_0_19; + wire n_0_20; + wire n_0_21; + wire n_0_22; + wire n_0_23; + wire n_0_24; + wire n_0_25; + wire n_0_26; + wire n_0_27; + wire n_0_28; + wire n_0_29; + wire n_0_30; + wire n_0_31; + wire n_0_32; + wire n_0_33; + wire n_0_34; + wire n_0_35; + wire n_0_36; + wire n_0_37; + wire n_0_38; + wire n_0_39; + wire n_0_40; + wire n_0_41; + wire n_0_42; + wire n_0_43; + wire n_0_44; + wire n_0_45; + wire n_0_46; + wire n_0_47; + wire n_0_48; + wire n_0_49; + wire n_0_50; + wire n_0_51; + wire n_0_52; + wire n_0_53; + wire n_0_54; + wire n_0_55; + wire n_0_56; + wire n_0_57; + wire n_0_58; + wire n_0_59; + wire n_0_60; + wire n_0_61; + wire n_0_62; + wire n_0_63; + wire n_0_64; + wire n_0_65; + wire n_0_66; + wire n_0_67; + wire n_0_68; + wire n_0_69; + wire n_0_70; + wire n_0_71; + wire n_0_72; + wire n_0_73; + wire n_0_74; + wire n_0_75; + wire n_0_76; + wire n_0_77; + wire n_0_78; + wire n_0_79; + wire n_0_80; + wire n_0_81; + wire n_0_82; + wire n_0_83; + wire n_0_84; + wire n_0_85; + wire n_0_86; + wire n_0_87; + wire n_0_88; + wire n_0_89; + wire n_0_90; + wire n_0_91; + wire n_0_92; + wire n_0_93; + wire n_0_94; + wire n_0_95; + wire n_0_96; + wire n_0_97; + wire n_0_98; + wire n_0_99; + wire n_0_100; + wire n_0_101; + wire n_0_102; + wire n_0_103; + wire n_0_104; + wire n_0_105; + wire n_0_106; + wire n_0_107; + wire n_0_108; + wire n_0_109; + wire n_0_110; + wire n_0_111; + wire n_0_112; + wire n_0_113; + wire n_0_114; + wire n_0_115; + wire n_0_116; + wire n_0_117; + wire n_0_118; + wire n_0_119; + wire n_0_120; + wire n_0_121; + wire n_0_122; + wire n_0_123; + wire n_0_124; + wire n_0_125; + wire n_0_126; + wire n_0_127; + wire n_0_128; + wire n_0_129; + wire n_0_130; + wire n_0_131; + wire n_0_132; + wire n_0_133; + wire n_0_134; + wire n_0_135; + wire n_0_136; + wire n_0_137; + wire n_0_138; + wire n_0_139; + wire n_0_140; + wire n_0_141; + wire n_0_142; + wire n_0_143; + wire n_0_144; + wire n_0_145; + wire n_0_146; + wire n_0_147; + wire n_0_148; + wire n_0_149; + wire n_0_150; + wire n_0_151; + wire n_0_152; + wire n_0_153; + wire n_0_154; + wire n_0_155; + wire n_0_156; + wire n_0_157; + wire n_0_158; + wire n_0_159; + wire n_0_160; + wire n_0_161; + wire n_0_162; + wire n_0_163; + wire n_0_164; + wire n_0_165; + wire n_0_166; + wire n_0_167; + wire n_0_168; + wire n_0_169; + wire n_0_170; + wire n_0_171; + wire n_0_172; + wire n_0_173; + wire n_0_174; + wire n_0_175; + wire n_0_176; + wire n_0_177; + wire n_0_178; + wire n_0_179; + wire n_0_180; + wire n_0_181; + wire n_0_182; + wire n_0_183; + wire n_0_184; + wire n_0_185; + wire n_0_186; + wire n_0_187; + wire n_0_188; + wire n_0_189; + wire n_0_190; + wire n_0_191; + wire n_0_192; + wire n_0_193; + wire n_0_194; + wire n_0_195; + wire n_0_196; + wire n_0_197; + wire n_0_198; + wire n_0_199; + wire n_0_200; + wire n_0_201; + wire n_0_202; + wire n_0_203; + wire n_0_204; + wire n_0_205; + wire n_0_206; + wire n_0_207; + wire n_0_208; + wire n_0_209; + wire n_0_210; + wire n_0_211; + wire n_0_212; + wire n_0_213; + wire n_0_214; + wire n_0_215; + wire n_0_216; + wire n_0_217; + wire n_0_218; + wire n_0_219; + wire n_0_220; + wire n_0_221; + wire n_0_222; + wire n_0_223; + wire n_0_224; + wire n_0_225; + wire n_0_226; + wire n_0_227; + wire n_0_228; + wire n_0_229; + wire n_0_230; + wire n_0_231; + wire n_0_232; + wire n_0_233; + wire n_0_234; + wire n_0_235; + wire n_0_236; + wire n_0_237; + wire n_0_238; + wire n_0_239; + wire n_0_240; + wire n_0_241; + wire n_0_242; + wire n_0_243; + wire n_0_244; + wire n_0_245; + wire n_0_246; + wire n_0_247; + wire n_0_248; + wire n_0_249; + wire n_0_250; + wire n_0_251; + wire n_0_252; + wire n_0_253; + wire n_0_254; + wire n_0_255; + wire n_0_256; + wire n_0_257; + wire n_0_258; + wire n_0_259; + wire n_0_260; + wire n_0_261; + wire n_0_262; + wire n_0_263; + wire n_0_264; + wire n_0_265; + wire n_0_266; + wire n_0_267; + wire n_0_268; + wire n_0_269; + wire n_0_270; + wire n_0_271; + wire n_0_272; + wire n_0_273; + wire n_0_274; + wire n_0_275; + wire n_0_276; + wire n_0_277; + wire n_0_278; + wire n_0_279; + wire n_0_280; + wire n_0_281; + wire n_0_282; + wire n_0_283; + wire n_0_284; + wire n_0_285; + wire n_0_286; + wire n_0_287; + wire n_0_288; + wire n_0_289; + wire n_0_290; + wire n_0_291; + wire n_0_292; + wire n_0_293; + wire n_0_294; + wire n_0_295; + wire n_0_296; + wire n_0_297; + wire n_0_298; + wire n_0_299; + wire n_0_300; + wire n_0_301; + wire n_0_302; + wire n_0_303; + wire n_0_304; + wire n_0_305; + wire n_0_306; + wire n_0_307; + wire n_0_308; + wire n_0_309; + wire n_0_310; + wire n_0_311; + wire n_0_312; + wire n_0_313; + wire n_0_314; + wire n_0_315; + wire n_0_316; + wire n_0_317; + wire n_0_318; + wire n_0_319; + wire n_0_320; + wire n_0_321; + wire n_0_322; + wire n_0_323; + wire n_0_324; + wire n_0_325; + wire n_0_326; + wire n_0_327; + wire n_0_328; + wire n_0_329; + wire n_0_330; + wire n_0_331; + wire n_0_332; + wire n_0_333; + wire n_0_334; + wire n_0_335; + wire n_0_336; + wire n_0_337; + wire n_0_338; + wire n_0_339; + wire n_0_340; + wire n_0_341; + wire n_0_342; + wire n_0_343; + wire n_0_344; + wire n_0_345; + wire n_0_346; + wire n_0_347; + wire n_0_348; + wire n_0_349; + wire n_0_350; + wire n_0_351; + wire n_0_352; + wire n_0_353; + wire n_0_354; + wire n_0_355; + wire n_0_356; + wire n_0_357; + wire n_0_358; + wire n_0_359; + wire n_0_360; + wire n_0_361; + wire n_0_362; + wire n_0_363; + wire n_0_364; + wire n_0_365; + wire n_0_366; + wire n_0_367; + wire n_0_368; + wire n_0_369; + wire n_0_370; + wire n_0_371; + wire n_0_372; + wire n_0_373; + wire n_0_374; + wire n_0_375; + wire n_0_376; + wire n_0_377; + wire n_0_378; + wire n_0_379; + wire n_0_380; + wire n_0_381; + wire n_0_382; + wire n_0_383; + wire n_0_384; + wire n_0_385; + wire n_0_386; + wire n_0_387; + wire n_0_388; + wire n_0_389; + wire n_0_390; + wire n_0_391; + wire n_0_392; + wire n_0_393; + wire n_0_394; + wire n_0_395; + wire n_0_396; + wire n_0_397; + wire n_0_398; + wire n_0_399; + wire n_0_400; + wire n_0_401; + wire n_0_402; + wire n_0_403; + wire n_0_404; + wire n_0_405; + wire n_0_406; + wire n_0_407; + wire n_0_408; + wire n_0_409; + wire n_0_410; + wire n_0_411; + wire n_0_412; + wire n_0_413; + wire n_0_414; + wire n_0_415; + wire n_0_416; + wire n_0_417; + wire n_0_418; + wire n_0_419; + wire n_0_420; + wire n_0_421; + wire n_0_422; + wire n_0_423; + wire n_0_424; + wire n_0_425; + wire n_0_426; + wire n_0_427; + wire n_0_428; + wire n_0_429; + wire n_0_430; + wire n_0_431; + wire n_0_432; + wire n_0_433; + wire n_0_434; + wire n_0_435; + wire n_0_436; + wire n_0_437; + wire n_0_438; + wire n_0_439; + wire n_0_440; + wire n_0_441; + wire n_0_442; + wire n_0_443; + wire n_0_444; + wire n_0_445; + wire n_0_446; + wire n_0_447; + wire n_0_448; + wire n_0_449; + wire n_0_450; + wire n_0_451; + wire n_0_452; + wire n_0_453; + wire n_0_454; + wire n_0_455; + wire n_0_456; + wire n_0_457; + wire n_0_458; + wire n_0_459; + wire n_0_460; + wire n_0_461; + wire n_0_462; + wire n_0_463; + wire n_0_464; + wire n_0_465; + wire n_0_466; + wire n_0_467; + wire n_0_468; + wire n_0_469; + wire n_0_470; + wire n_0_471; + wire n_0_472; + wire n_0_473; + wire n_0_474; + wire n_0_475; + wire n_0_476; + wire n_0_477; + wire n_0_478; + wire n_0_479; + wire n_0_480; + wire n_0_481; + wire n_0_482; + wire n_0_483; + wire n_0_484; + wire n_0_485; + wire n_0_486; + wire n_0_487; + wire n_0_488; + wire n_0_489; + wire n_0_490; + wire n_0_491; + wire n_0_492; + wire n_0_493; + wire n_0_494; + wire n_0_495; + wire n_0_496; + wire n_0_497; + wire n_0_498; + wire n_0_499; + wire n_0_500; + wire n_0_501; + wire n_0_502; + wire n_0_503; + wire n_0_504; + wire n_0_505; + wire n_0_506; + wire n_0_507; + wire n_0_508; + wire n_0_509; + wire n_0_510; + wire n_0_511; + wire n_0_512; + wire n_0_513; + wire n_0_514; + wire n_0_515; + wire n_0_516; + wire n_0_517; + wire n_0_518; + wire n_0_519; + wire n_0_520; + wire n_0_521; + wire n_0_522; + wire n_0_523; + wire n_0_524; + wire n_0_525; + wire n_0_526; + wire n_0_527; + wire n_0_528; + wire n_0_529; + wire n_0_530; + wire n_0_531; + wire n_0_532; + wire n_0_533; + wire n_0_534; + wire n_0_535; + wire n_0_536; + wire n_0_537; + wire n_0_538; + wire n_0_539; + wire n_0_540; + wire n_0_541; + wire n_0_542; + wire n_0_543; + wire n_0_544; + wire n_0_545; + wire n_0_546; + wire n_0_547; + wire n_0_548; + wire n_0_549; + wire n_0_550; + wire n_0_551; + wire n_0_552; + wire n_0_553; + wire n_0_554; + wire n_0_555; + wire n_0_556; + wire n_0_557; + wire n_0_558; + wire n_0_559; + wire n_0_560; + wire n_0_561; + wire n_0_562; + wire n_0_563; + wire n_0_564; + wire n_0_565; + wire n_0_566; + wire n_0_567; + wire n_0_568; + wire n_0_569; + wire n_0_570; + wire n_0_571; + wire n_0_572; + wire n_0_573; + wire n_0_574; + wire n_0_575; + wire n_0_576; + wire n_0_577; + wire n_0_578; + wire n_0_579; + wire n_0_580; + wire n_0_581; + wire n_0_582; + wire n_0_583; + wire n_0_584; + wire n_0_585; + wire n_0_586; + wire n_0_587; + wire n_0_588; + wire n_0_589; + wire n_0_590; + wire n_0_591; + wire n_0_592; + wire n_0_593; + wire n_0_594; + wire n_0_595; + wire n_0_596; + wire n_0_597; + wire n_0_598; + wire n_0_599; + wire n_0_600; + wire n_0_601; + wire n_0_602; + wire n_0_603; + wire n_0_604; + wire n_0_605; + wire n_0_606; + wire n_0_607; + wire n_0_608; + wire n_0_609; + wire n_0_610; + wire n_0_611; + wire n_0_612; + wire n_0_613; + wire n_0_614; + wire n_0_615; + wire n_0_616; + wire n_0_617; + wire n_0_618; + wire n_0_619; + wire n_0_620; + wire n_0_621; + wire n_0_622; + wire n_0_623; + wire n_0_624; + wire n_0_625; + wire n_0_626; + wire n_0_627; + wire n_0_628; + wire n_0_629; + wire n_0_630; + wire n_0_631; + wire n_0_632; + wire n_0_633; + wire n_0_634; + wire n_0_635; + wire n_0_636; + wire n_0_637; + wire n_0_638; + wire n_0_639; + wire n_0_640; + wire n_0_641; + wire n_0_642; + wire n_0_643; + wire n_0_644; + wire n_0_645; + wire n_0_646; + wire n_0_647; + wire n_0_648; + wire n_0_649; + wire n_0_650; + wire n_0_651; + wire n_0_652; + wire n_0_653; + wire n_0_654; + wire n_0_655; + wire n_0_656; + wire n_0_657; + wire n_0_658; + wire n_0_659; + wire n_0_660; + wire n_0_661; + wire n_0_662; + wire n_0_663; + wire n_0_664; + wire n_0_665; + wire n_0_666; + wire n_0_667; + wire n_0_668; + wire n_0_669; + wire n_0_670; + wire n_0_671; + wire n_0_672; + wire n_0_673; + wire n_0_674; + wire n_0_675; + wire n_0_676; + wire n_0_677; + wire n_0_678; + wire n_0_679; + wire n_0_680; + wire n_0_681; + wire n_0_682; + wire n_0_683; + wire n_0_684; + wire n_0_685; + wire n_0_686; + wire n_0_687; + wire n_0_688; + wire n_0_689; + wire n_0_690; + wire n_0_691; + wire n_0_692; + wire n_0_693; + wire n_0_694; + wire n_0_695; + wire n_0_696; + wire n_0_697; + wire n_0_698; + wire n_0_699; + wire n_0_700; + wire n_0_701; + wire n_0_702; + wire n_0_703; + wire n_0_704; + wire n_0_705; + wire n_0_706; + wire n_0_707; + wire n_0_708; + wire n_0_709; + wire n_0_710; + wire n_0_711; + wire n_0_712; + wire n_0_713; + wire n_0_714; + wire n_0_715; + wire n_0_716; + wire n_0_717; + wire n_0_718; + wire n_0_719; + wire n_0_720; + wire n_0_721; + wire n_0_722; + wire n_0_723; + wire n_0_724; + wire n_0_725; + wire n_0_726; + wire n_0_727; + wire n_0_728; + wire n_0_729; + wire n_0_730; + wire n_0_731; + wire n_0_732; + wire n_0_733; + wire n_0_734; + wire n_0_735; + wire n_0_736; + wire n_0_737; + wire n_0_738; + wire n_0_739; + wire n_0_740; + + INV_X1_LVT i_0_725 (.A(op2[31]), .ZN(n_0_692)); + INV_X1_LVT i_0_724 (.A(op1[31]), .ZN(n_0_691)); + INV_X1_LVT i_0_718 (.A(aluOp[1]), .ZN(n_0_685)); + INV_X1_LVT i_0_717 (.A(aluOp[2]), .ZN(n_0_684)); + NOR2_X1_LVT i_0_599 (.A1(n_0_685), .A2(n_0_684), .ZN(n_0_567)); + INV_X1_LVT i_0_598 (.A(n_0_567), .ZN(n_0_566)); + INV_X1_LVT i_0_716 (.A(aluOp[0]), .ZN(n_0_683)); + NAND2_X1_LVT i_0_602 (.A1(aluOp[2]), .A2(aluNegAr), .ZN(n_0_570)); + OAI21_X1_LVT i_0_590 (.A(n_0_566), .B1(n_0_683), .B2(n_0_570), .ZN(n_0_558)); + INV_X1_LVT i_0_714 (.A(aluBypass), .ZN(n_0_681)); + NOR2_X1_LVT i_0_601 (.A1(n_0_684), .A2(aluOp[0]), .ZN(n_0_569)); + NAND2_X1_LVT i_0_597 (.A1(n_0_681), .A2(n_0_569), .ZN(n_0_565)); + INV_X1_LVT i_0_596 (.A(n_0_565), .ZN(n_0_564)); + OAI22_X1_LVT i_0_589 (.A1(n_0_691), .A2(n_0_558), .B1(op1[31]), .B2(n_0_564), + .ZN(n_0_557)); + NOR2_X1_LVT i_0_588 (.A1(n_0_692), .A2(n_0_557), .ZN(n_0_556)); + XNOR2_X1_LVT i_9_31 (.A(op2[31]), .B(op1[31]), .ZN(n_9_31)); + HA_X1_LVT i_9_0 (.A(op2[0]), .B(op1[0]), .CO(n_9_0), .S(n_0)); + FA_X1_LVT i_9_1 (.A(op2[1]), .B(op1[1]), .CI(n_9_0), .CO(n_9_1), .S(n_1)); + FA_X1_LVT i_9_2 (.A(op2[2]), .B(op1[2]), .CI(n_9_1), .CO(n_9_2), .S(n_2)); + FA_X1_LVT i_9_3 (.A(op2[3]), .B(op1[3]), .CI(n_9_2), .CO(n_9_3), .S(n_3)); + FA_X1_LVT i_9_4 (.A(op2[4]), .B(op1[4]), .CI(n_9_3), .CO(n_9_4), .S(n_4)); + FA_X1_LVT i_9_5 (.A(op2[5]), .B(op1[5]), .CI(n_9_4), .CO(n_9_5), .S(n_5)); + FA_X1_LVT i_9_6 (.A(op2[6]), .B(op1[6]), .CI(n_9_5), .CO(n_9_6), .S(n_6)); + FA_X1_LVT i_9_7 (.A(op2[7]), .B(op1[7]), .CI(n_9_6), .CO(n_9_7), .S(n_7)); + FA_X1_LVT i_9_8 (.A(op2[8]), .B(op1[8]), .CI(n_9_7), .CO(n_9_8), .S(n_8)); + FA_X1_LVT i_9_9 (.A(op2[9]), .B(op1[9]), .CI(n_9_8), .CO(n_9_9), .S(n_9)); + FA_X1_LVT i_9_10 (.A(op2[10]), .B(op1[10]), .CI(n_9_9), .CO(n_9_10), .S(n_10)); + FA_X1_LVT i_9_11 (.A(op2[11]), .B(op1[11]), .CI(n_9_10), .CO(n_9_11), + .S(n_11)); + FA_X1_LVT i_9_12 (.A(op2[12]), .B(op1[12]), .CI(n_9_11), .CO(n_9_12), + .S(n_12)); + FA_X1_LVT i_9_13 (.A(op2[13]), .B(op1[13]), .CI(n_9_12), .CO(n_9_13), + .S(n_13)); + FA_X1_LVT i_9_14 (.A(op2[14]), .B(op1[14]), .CI(n_9_13), .CO(n_9_14), + .S(n_14)); + FA_X1_LVT i_9_15 (.A(op2[15]), .B(op1[15]), .CI(n_9_14), .CO(n_9_15), + .S(n_15)); + FA_X1_LVT i_9_16 (.A(op2[16]), .B(op1[16]), .CI(n_9_15), .CO(n_9_16), + .S(n_16)); + FA_X1_LVT i_9_17 (.A(op2[17]), .B(op1[17]), .CI(n_9_16), .CO(n_9_17), + .S(n_17)); + FA_X1_LVT i_9_18 (.A(op2[18]), .B(op1[18]), .CI(n_9_17), .CO(n_9_18), + .S(n_18)); + FA_X1_LVT i_9_19 (.A(op2[19]), .B(op1[19]), .CI(n_9_18), .CO(n_9_19), + .S(n_19)); + FA_X1_LVT i_9_20 (.A(op2[20]), .B(op1[20]), .CI(n_9_19), .CO(n_9_20), + .S(n_20)); + FA_X1_LVT i_9_21 (.A(op2[21]), .B(op1[21]), .CI(n_9_20), .CO(n_9_21), + .S(n_21)); + FA_X1_LVT i_9_22 (.A(op2[22]), .B(op1[22]), .CI(n_9_21), .CO(n_9_22), + .S(n_22)); + FA_X1_LVT i_9_23 (.A(op2[23]), .B(op1[23]), .CI(n_9_22), .CO(n_9_23), + .S(n_23)); + FA_X1_LVT i_9_24 (.A(op2[24]), .B(op1[24]), .CI(n_9_23), .CO(n_9_24), + .S(n_24)); + FA_X1_LVT i_9_25 (.A(op2[25]), .B(op1[25]), .CI(n_9_24), .CO(n_9_25), + .S(n_25)); + FA_X1_LVT i_9_26 (.A(op2[26]), .B(op1[26]), .CI(n_9_25), .CO(n_9_26), + .S(n_26)); + FA_X1_LVT i_9_27 (.A(op2[27]), .B(op1[27]), .CI(n_9_26), .CO(n_9_27), + .S(n_27)); + FA_X1_LVT i_9_28 (.A(op2[28]), .B(op1[28]), .CI(n_9_27), .CO(n_9_28), + .S(n_28)); + FA_X1_LVT i_9_29 (.A(op2[29]), .B(op1[29]), .CI(n_9_28), .CO(n_9_29), + .S(n_29)); + FA_X1_LVT i_9_30 (.A(op2[30]), .B(op1[30]), .CI(n_9_29), .CO(n_9_30), + .S(n_30)); + XNOR2_X1_LVT i_9_32 (.A(n_9_31), .B(n_9_30), .ZN(n_31)); + NAND4_X1_LVT i_0_614 (.A1(n_0_685), .A2(n_0_681), .A3(n_0_684), .A4(n_0_683), + .ZN(n_0_582)); + NOR2_X1_LVT i_0_613 (.A1(aluNegAr), .A2(n_0_582), .ZN(n_0_581)); + INV_X1_LVT i_10_147 (.A(op2[30]), .ZN(n_10_117)); + NAND2_X1_LVT i_10_149 (.A1(n_10_117), .A2(op1[30]), .ZN(n_10_119)); + INV_X1_LVT i_10_152 (.A(n_10_119), .ZN(n_10_121)); + INV_X1_LVT i_10_130 (.A(op1[26]), .ZN(n_10_104)); + NAND2_X1_LVT i_10_131 (.A1(n_10_104), .A2(op2[26]), .ZN(n_10_105)); + INV_X1_LVT i_10_123 (.A(op2[25]), .ZN(n_10_98)); + NAND2_X1_LVT i_10_125 (.A1(n_10_98), .A2(op1[25]), .ZN(n_10_100)); + INV_X1_LVT i_10_112 (.A(op2[23]), .ZN(n_10_89)); + NAND2_X1_LVT i_10_114 (.A1(n_10_89), .A2(op1[23]), .ZN(n_10_91)); + INV_X1_LVT i_10_101 (.A(op2[21]), .ZN(n_10_80)); + NAND2_X1_LVT i_10_103 (.A1(n_10_80), .A2(op1[21]), .ZN(n_10_82)); + INV_X1_LVT i_10_48 (.A(op1[8]), .ZN(n_10_40)); + NAND2_X1_LVT i_10_49 (.A1(n_10_40), .A2(op2[8]), .ZN(n_10_41)); + INV_X1_LVT i_10_41 (.A(op2[7]), .ZN(n_10_34)); + NAND2_X1_LVT i_10_43 (.A1(n_10_34), .A2(op1[7]), .ZN(n_10_36)); + INV_X1_LVT i_10_32 (.A(op2[5]), .ZN(n_10_27)); + NOR2_X1_LVT i_10_33 (.A1(n_10_27), .A2(op1[5]), .ZN(n_10_28)); + INV_X1_LVT i_10_24 (.A(op1[4]), .ZN(n_10_20)); + NOR2_X1_LVT i_10_27 (.A1(n_10_20), .A2(op2[4]), .ZN(n_10_23)); + INV_X1_LVT i_10_17 (.A(op2[3]), .ZN(n_10_14)); + NAND2_X1_LVT i_10_19 (.A1(n_10_14), .A2(op1[3]), .ZN(n_10_16)); + INV_X1_LVT i_10_22 (.A(n_10_16), .ZN(n_10_18)); + INV_X1_LVT i_10_10 (.A(op2[2]), .ZN(n_10_8)); + NAND2_X1_LVT i_10_12 (.A1(n_10_8), .A2(op1[2]), .ZN(n_10_10)); + INV_X1_LVT i_10_3 (.A(op1[1]), .ZN(n_10_2)); + NAND2_X1_LVT i_10_5 (.A1(n_10_2), .A2(op2[1]), .ZN(n_10_4)); + INV_X1_LVT i_10_0 (.A(op1[0]), .ZN(n_10_0)); + NAND2_X1_LVT i_10_1 (.A1(n_10_0), .A2(op2[0]), .ZN(n_10_1)); + OR2_X1_LVT i_10_4 (.A1(n_10_2), .A2(op2[1]), .ZN(n_10_3)); + INV_X1_LVT i_10_8 (.A(n_10_3), .ZN(n_10_6)); + OAI21_X1_LVT i_10_9 (.A(n_10_4), .B1(n_10_1), .B2(n_10_6), .ZN(n_10_7)); + NOR2_X1_LVT i_10_11 (.A1(n_10_8), .A2(op1[2]), .ZN(n_10_9)); + OAI21_X1_LVT i_10_16 (.A(n_10_10), .B1(n_10_7), .B2(n_10_9), .ZN(n_10_13)); + OR2_X1_LVT i_10_18 (.A1(n_10_14), .A2(op1[3]), .ZN(n_10_15)); + AOI21_X1_LVT i_10_23 (.A(n_10_18), .B1(n_10_13), .B2(n_10_15), .ZN(n_10_19)); + INV_X1_LVT i_10_30 (.A(n_10_19), .ZN(n_10_25)); + NAND2_X1_LVT i_10_25 (.A1(n_10_20), .A2(op2[4]), .ZN(n_10_21)); + AOI21_X1_LVT i_10_31 (.A(n_10_23), .B1(n_10_25), .B2(n_10_21), .ZN(n_10_26)); + AOI21_X1_LVT i_10_34 (.A(n_10_28), .B1(n_10_27), .B2(op1[5]), .ZN(n_10_29)); + AOI21_X1_LVT i_10_36 (.A(n_10_28), .B1(n_10_26), .B2(n_10_29), .ZN(n_10_30)); + XOR2_X1_LVT i_10_37 (.A(op2[6]), .B(op1[6]), .Z(n_10_31)); + INV_X1_LVT i_10_39 (.A(op2[6]), .ZN(n_10_32)); + OAI22_X1_LVT i_10_40 (.A1(n_10_30), .A2(n_10_31), .B1(n_10_32), .B2(op1[6]), + .ZN(n_10_33)); + NOR2_X1_LVT i_10_42 (.A1(n_10_34), .A2(op1[7]), .ZN(n_10_35)); + OAI21_X1_LVT i_10_47 (.A(n_10_36), .B1(n_10_33), .B2(n_10_35), .ZN(n_10_39)); + OAI21_X1_LVT i_10_50 (.A(n_10_41), .B1(n_10_40), .B2(op2[8]), .ZN(n_10_42)); + OAI21_X1_LVT i_10_52 (.A(n_10_41), .B1(n_10_39), .B2(n_10_42), .ZN(n_10_43)); + XNOR2_X1_LVT i_10_53 (.A(op2[9]), .B(op1[9]), .ZN(n_10_44)); + INV_X1_LVT i_10_55 (.A(op1[9]), .ZN(n_10_45)); + AOI22_X1_LVT i_10_56 (.A1(n_10_43), .A2(n_10_44), .B1(n_10_45), .B2(op2[9]), + .ZN(n_10_46)); + XOR2_X1_LVT i_10_57 (.A(op2[10]), .B(op1[10]), .Z(n_10_47)); + INV_X1_LVT i_10_59 (.A(op2[10]), .ZN(n_10_48)); + OAI22_X1_LVT i_10_60 (.A1(n_10_46), .A2(n_10_47), .B1(n_10_48), .B2(op1[10]), + .ZN(n_10_49)); + XNOR2_X1_LVT i_10_61 (.A(op2[11]), .B(op1[11]), .ZN(n_10_50)); + INV_X1_LVT i_10_63 (.A(op1[11]), .ZN(n_10_51)); + AOI22_X1_LVT i_10_64 (.A1(n_10_49), .A2(n_10_50), .B1(n_10_51), .B2(op2[11]), + .ZN(n_10_52)); + XOR2_X1_LVT i_10_65 (.A(op2[12]), .B(op1[12]), .Z(n_10_53)); + INV_X1_LVT i_10_67 (.A(op2[12]), .ZN(n_10_54)); + OAI22_X1_LVT i_10_68 (.A1(n_10_52), .A2(n_10_53), .B1(n_10_54), .B2(op1[12]), + .ZN(n_10_55)); + XNOR2_X1_LVT i_10_69 (.A(op2[13]), .B(op1[13]), .ZN(n_10_56)); + INV_X1_LVT i_10_71 (.A(op1[13]), .ZN(n_10_57)); + AOI22_X1_LVT i_10_72 (.A1(n_10_55), .A2(n_10_56), .B1(n_10_57), .B2(op2[13]), + .ZN(n_10_58)); + XOR2_X1_LVT i_10_73 (.A(op2[14]), .B(op1[14]), .Z(n_10_59)); + INV_X1_LVT i_10_75 (.A(op2[14]), .ZN(n_10_60)); + OAI22_X1_LVT i_10_76 (.A1(n_10_58), .A2(n_10_59), .B1(n_10_60), .B2(op1[14]), + .ZN(n_10_61)); + XNOR2_X1_LVT i_10_77 (.A(op2[15]), .B(op1[15]), .ZN(n_10_62)); + INV_X1_LVT i_10_79 (.A(op1[15]), .ZN(n_10_63)); + AOI22_X1_LVT i_10_80 (.A1(n_10_61), .A2(n_10_62), .B1(n_10_63), .B2(op2[15]), + .ZN(n_10_64)); + XOR2_X1_LVT i_10_81 (.A(op2[16]), .B(op1[16]), .Z(n_10_65)); + INV_X1_LVT i_10_83 (.A(op2[16]), .ZN(n_10_66)); + OAI22_X1_LVT i_10_84 (.A1(n_10_64), .A2(n_10_65), .B1(n_10_66), .B2(op1[16]), + .ZN(n_10_67)); + XNOR2_X1_LVT i_10_85 (.A(op2[17]), .B(op1[17]), .ZN(n_10_68)); + INV_X1_LVT i_10_87 (.A(op1[17]), .ZN(n_10_69)); + AOI22_X1_LVT i_10_88 (.A1(n_10_67), .A2(n_10_68), .B1(n_10_69), .B2(op2[17]), + .ZN(n_10_70)); + XOR2_X1_LVT i_10_89 (.A(op2[18]), .B(op1[18]), .Z(n_10_71)); + INV_X1_LVT i_10_91 (.A(op2[18]), .ZN(n_10_72)); + OAI22_X1_LVT i_10_92 (.A1(n_10_70), .A2(n_10_71), .B1(n_10_72), .B2(op1[18]), + .ZN(n_10_73)); + XNOR2_X1_LVT i_10_93 (.A(op2[19]), .B(op1[19]), .ZN(n_10_74)); + INV_X1_LVT i_10_95 (.A(op1[19]), .ZN(n_10_75)); + AOI22_X1_LVT i_10_96 (.A1(n_10_73), .A2(n_10_74), .B1(n_10_75), .B2(op2[19]), + .ZN(n_10_76)); + XOR2_X1_LVT i_10_97 (.A(op2[20]), .B(op1[20]), .Z(n_10_77)); + INV_X1_LVT i_10_99 (.A(op2[20]), .ZN(n_10_78)); + OAI22_X1_LVT i_10_100 (.A1(n_10_76), .A2(n_10_77), .B1(n_10_78), .B2(op1[20]), + .ZN(n_10_79)); + NOR2_X1_LVT i_10_102 (.A1(n_10_80), .A2(op1[21]), .ZN(n_10_81)); + OAI21_X1_LVT i_10_107 (.A(n_10_82), .B1(n_10_79), .B2(n_10_81), .ZN(n_10_85)); + XOR2_X1_LVT i_10_108 (.A(op2[22]), .B(op1[22]), .Z(n_10_86)); + INV_X1_LVT i_10_110 (.A(op2[22]), .ZN(n_10_87)); + OAI22_X1_LVT i_10_111 (.A1(n_10_85), .A2(n_10_86), .B1(n_10_87), .B2(op1[22]), + .ZN(n_10_88)); + NOR2_X1_LVT i_10_113 (.A1(n_10_89), .A2(op1[23]), .ZN(n_10_90)); + OAI21_X1_LVT i_10_118 (.A(n_10_91), .B1(n_10_88), .B2(n_10_90), .ZN(n_10_94)); + XOR2_X1_LVT i_10_119 (.A(op2[24]), .B(op1[24]), .Z(n_10_95)); + INV_X1_LVT i_10_121 (.A(op2[24]), .ZN(n_10_96)); + OAI22_X1_LVT i_10_122 (.A1(n_10_94), .A2(n_10_95), .B1(n_10_96), .B2(op1[24]), + .ZN(n_10_97)); + NOR2_X1_LVT i_10_124 (.A1(n_10_98), .A2(op1[25]), .ZN(n_10_99)); + OAI21_X1_LVT i_10_129 (.A(n_10_100), .B1(n_10_97), .B2(n_10_99), .ZN(n_10_103)); + OAI21_X1_LVT i_10_132 (.A(n_10_105), .B1(n_10_104), .B2(op2[26]), .ZN( + n_10_106)); + OAI21_X1_LVT i_10_134 (.A(n_10_105), .B1(n_10_103), .B2(n_10_106), .ZN( + n_10_107)); + XNOR2_X1_LVT i_10_135 (.A(op2[27]), .B(op1[27]), .ZN(n_10_108)); + INV_X1_LVT i_10_137 (.A(op1[27]), .ZN(n_10_109)); + AOI22_X1_LVT i_10_138 (.A1(n_10_107), .A2(n_10_108), .B1(n_10_109), .B2( + op2[27]), .ZN(n_10_110)); + XOR2_X1_LVT i_10_139 (.A(op2[28]), .B(op1[28]), .Z(n_10_111)); + INV_X1_LVT i_10_141 (.A(op2[28]), .ZN(n_10_112)); + OAI22_X1_LVT i_10_142 (.A1(n_10_110), .A2(n_10_111), .B1(n_10_112), .B2( + op1[28]), .ZN(n_10_113)); + XNOR2_X1_LVT i_10_143 (.A(op2[29]), .B(op1[29]), .ZN(n_10_114)); + INV_X1_LVT i_10_145 (.A(op1[29]), .ZN(n_10_115)); + AOI22_X1_LVT i_10_146 (.A1(n_10_113), .A2(n_10_114), .B1(n_10_115), .B2( + op2[29]), .ZN(n_10_116)); + OR2_X1_LVT i_10_148 (.A1(n_10_117), .A2(op1[30]), .ZN(n_10_118)); + AOI21_X1_LVT i_10_153 (.A(n_10_121), .B1(n_10_116), .B2(n_10_118), .ZN( + n_10_122)); + XNOR2_X1_LVT i_10_154 (.A(op1[31]), .B(op2[31]), .ZN(n_10_123)); + XNOR2_X1_LVT i_10_155 (.A(n_10_122), .B(n_10_123), .ZN(n_63)); + INV_X1_LVT i_0_715 (.A(aluNegAr), .ZN(n_0_682)); + NOR2_X1_LVT i_0_612 (.A1(n_0_682), .A2(n_0_582), .ZN(n_0_580)); + AOI221_X1_LVT i_0_587 (.A(n_0_556), .B1(n_31), .B2(n_0_581), .C1(n_63), + .C2(n_0_580), .ZN(n_0_555)); + NOR3_X1_LVT i_0_654 (.A1(aluOp[1]), .A2(aluBypass), .A3(n_0_683), .ZN(n_0_622)); + NAND2_X1_LVT i_0_653 (.A1(n_0_684), .A2(n_0_622), .ZN(n_0_621)); + INV_X1_LVT i_0_734 (.A(op2[0]), .ZN(n_0_701)); + INV_X1_LVT i_0_756 (.A(op2[3]), .ZN(n_0_723)); + NOR2_X1_LVT i_0_650 (.A1(op2[4]), .A2(n_0_723), .ZN(n_0_618)); + INV_X1_LVT i_0_649 (.A(n_0_618), .ZN(n_0_617)); + NOR2_X1_LVT i_0_648 (.A1(op2[4]), .A2(op2[3]), .ZN(n_0_616)); + INV_X1_LVT i_0_647 (.A(n_0_616), .ZN(n_0_615)); + INV_X1_LVT i_0_771 (.A(op2[4]), .ZN(n_0_738)); + INV_X1_LVT i_0_767 (.A(op1[15]), .ZN(n_0_734)); + INV_X1_LVT i_0_746 (.A(op1[7]), .ZN(n_0_713)); + AOI22_X1_LVT i_0_651 (.A1(n_0_734), .A2(n_0_723), .B1(op2[3]), .B2(n_0_713), + .ZN(n_0_619)); + OAI222_X1_LVT i_0_646 (.A1(op1[23]), .A2(n_0_617), .B1(op1[31]), .B2(n_0_615), + .C1(n_0_738), .C2(n_0_619), .ZN(n_0_614)); + NOR2_X1_LVT i_0_645 (.A1(op2[2]), .A2(n_0_614), .ZN(n_0_613)); + NOR2_X1_LVT i_0_696 (.A1(op1[3]), .A2(n_0_723), .ZN(n_0_663)); + INV_X1_LVT i_0_739 (.A(op1[11]), .ZN(n_0_706)); + AOI21_X1_LVT i_0_644 (.A(n_0_663), .B1(n_0_723), .B2(n_0_706), .ZN(n_0_612)); + AOI22_X1_LVT i_0_643 (.A1(op2[4]), .A2(n_0_612), .B1(op1[27]), .B2(n_0_616), + .ZN(n_0_611)); + INV_X1_LVT i_0_722 (.A(op1[19]), .ZN(n_0_689)); + OAI21_X1_LVT i_0_642 (.A(n_0_611), .B1(n_0_689), .B2(n_0_617), .ZN(n_0_610)); + AOI21_X1_LVT i_0_641 (.A(n_0_613), .B1(op2[2]), .B2(n_0_610), .ZN(n_0_609)); + INV_X1_LVT i_0_761 (.A(op2[1]), .ZN(n_0_728)); + OAI22_X1_LVT i_0_640 (.A1(op2[4]), .A2(op1[21]), .B1(n_0_738), .B2(op1[5]), + .ZN(n_0_608)); + NAND2_X1_LVT i_0_639 (.A1(op2[3]), .A2(n_0_608), .ZN(n_0_607)); + INV_X1_LVT i_0_747 (.A(op1[13]), .ZN(n_0_714)); + NOR2_X1_LVT i_0_638 (.A1(n_0_738), .A2(op2[3]), .ZN(n_0_606)); + INV_X1_LVT i_0_743 (.A(op1[29]), .ZN(n_0_710)); + AOI221_X1_LVT i_0_636 (.A(op2[2]), .B1(n_0_714), .B2(n_0_606), .C1(n_0_710), + .C2(n_0_616), .ZN(n_0_604)); + OAI22_X1_LVT i_0_635 (.A1(op2[4]), .A2(op1[17]), .B1(n_0_738), .B2(op1[1]), + .ZN(n_0_603)); + INV_X1_LVT i_0_755 (.A(op1[9]), .ZN(n_0_722)); + INV_X1_LVT i_0_637 (.A(n_0_606), .ZN(n_0_605)); + INV_X1_LVT i_0_732 (.A(op1[25]), .ZN(n_0_699)); + OAI222_X1_LVT i_0_634 (.A1(n_0_723), .A2(n_0_603), .B1(n_0_722), .B2(n_0_605), + .C1(n_0_699), .C2(n_0_615), .ZN(n_0_602)); + AOI22_X1_LVT i_0_633 (.A1(n_0_607), .A2(n_0_604), .B1(op2[2]), .B2(n_0_602), + .ZN(n_0_601)); + OAI221_X1_LVT i_0_616 (.A(n_0_701), .B1(op2[1]), .B2(n_0_609), .C1(n_0_728), + .C2(n_0_601), .ZN(n_0_584)); + INV_X1_LVT i_0_729 (.A(op1[12]), .ZN(n_0_696)); + INV_X1_LVT i_0_731 (.A(op1[28]), .ZN(n_0_698)); + AOI22_X1_LVT i_0_622 (.A1(n_0_696), .A2(n_0_606), .B1(n_0_698), .B2(n_0_616), + .ZN(n_0_590)); + INV_X1_LVT i_0_726 (.A(op2[2]), .ZN(n_0_693)); + NOR2_X1_LVT i_0_701 (.A1(n_0_738), .A2(op1[4]), .ZN(n_0_668)); + INV_X1_LVT i_0_760 (.A(op1[20]), .ZN(n_0_727)); + AOI21_X1_LVT i_0_623 (.A(n_0_668), .B1(n_0_738), .B2(n_0_727), .ZN(n_0_591)); + OAI211_X1_LVT i_0_621 (.A(n_0_590), .B(n_0_693), .C1(n_0_723), .C2(n_0_591), + .ZN(n_0_589)); + OAI22_X1_LVT i_0_626 (.A1(op1[16]), .A2(op2[4]), .B1(n_0_738), .B2(op1[0]), + .ZN(n_0_594)); + INV_X1_LVT i_0_769 (.A(op1[24]), .ZN(n_0_736)); + OAI22_X1_LVT i_0_625 (.A1(n_0_723), .A2(n_0_594), .B1(n_0_736), .B2(n_0_615), + .ZN(n_0_593)); + AOI21_X1_LVT i_0_624 (.A(n_0_593), .B1(op1[8]), .B2(n_0_606), .ZN(n_0_592)); + OAI21_X1_LVT i_0_620 (.A(n_0_589), .B1(n_0_693), .B2(n_0_592), .ZN(n_0_588)); + INV_X1_LVT i_0_737 (.A(op1[6]), .ZN(n_0_704)); + INV_X1_LVT i_0_720 (.A(op1[22]), .ZN(n_0_687)); + OAI22_X1_LVT i_0_632 (.A1(n_0_738), .A2(n_0_704), .B1(op2[4]), .B2(n_0_687), + .ZN(n_0_600)); + OAI221_X1_LVT i_0_631 (.A(n_0_693), .B1(n_0_723), .B2(n_0_600), .C1(op1[14]), + .C2(n_0_605), .ZN(n_0_599)); + INV_X1_LVT i_0_750 (.A(op1[30]), .ZN(n_0_717)); + AOI21_X1_LVT i_0_630 (.A(n_0_599), .B1(n_0_717), .B2(n_0_616), .ZN(n_0_598)); + INV_X1_LVT i_0_738 (.A(op1[18]), .ZN(n_0_705)); + NOR2_X1_LVT i_0_628 (.A1(n_0_705), .A2(n_0_617), .ZN(n_0_596)); + INV_X1_LVT i_0_727 (.A(op1[2]), .ZN(n_0_694)); + INV_X1_LVT i_0_766 (.A(op1[10]), .ZN(n_0_733)); + OAI22_X1_LVT i_0_629 (.A1(n_0_723), .A2(n_0_694), .B1(n_0_733), .B2(op2[3]), + .ZN(n_0_597)); + AOI221_X1_LVT i_0_627 (.A(n_0_596), .B1(op1[26]), .B2(n_0_616), .C1(op2[4]), + .C2(n_0_597), .ZN(n_0_595)); + OAI21_X1_LVT i_0_619 (.A(n_0_728), .B1(n_0_693), .B2(n_0_595), .ZN(n_0_587)); + OAI22_X1_LVT i_0_618 (.A1(n_0_728), .A2(n_0_588), .B1(n_0_598), .B2(n_0_587), + .ZN(n_0_586)); + INV_X1_LVT i_0_617 (.A(n_0_586), .ZN(n_0_585)); + OAI21_X1_LVT i_0_615 (.A(n_0_584), .B1(n_0_701), .B2(n_0_585), .ZN(n_0_583)); + NOR2_X1_LVT i_0_607 (.A1(op2[4]), .A2(op2[2]), .ZN(n_0_575)); + NAND2_X1_LVT i_0_606 (.A1(n_0_723), .A2(n_0_575), .ZN(n_0_574)); + INV_X1_LVT i_0_605 (.A(n_0_574), .ZN(n_0_573)); + NAND2_X1_LVT i_0_604 (.A1(n_0_728), .A2(n_0_573), .ZN(n_0_572)); + NAND2_X1_LVT i_0_611 (.A1(aluOp[2]), .A2(n_0_622), .ZN(n_0_579)); + INV_X1_LVT i_0_610 (.A(n_0_579), .ZN(n_0_578)); + NAND2_X1_LVT i_0_594 (.A1(n_0_701), .A2(n_0_578), .ZN(n_0_562)); + NOR3_X1_LVT i_0_592 (.A1(aluNegAr), .A2(n_0_572), .A3(n_0_562), .ZN(n_0_560)); + INV_X1_LVT i_0_600 (.A(n_0_569), .ZN(n_0_568)); + OAI21_X1_LVT i_0_595 (.A(n_0_568), .B1(aluOp[1]), .B2(n_0_570), .ZN(n_0_563)); + AOI211_X1_LVT i_0_591 (.A(aluBypass), .B(n_0_560), .C1(n_0_692), .C2(n_0_563), + .ZN(n_0_559)); + OAI221_X1_LVT i_0_586 (.A(n_0_555), .B1(n_0_621), .B2(n_0_583), .C1(n_0_691), + .C2(n_0_559), .ZN(result[31])); + NAND2_X1_LVT i_10_150 (.A1(n_10_118), .A2(n_10_119), .ZN(n_10_120)); + XNOR2_X1_LVT i_10_151 (.A(n_10_116), .B(n_10_120), .ZN(n_62)); + AOI22_X1_LVT i_0_580 (.A1(n_62), .A2(n_0_580), .B1(n_30), .B2(n_0_581), + .ZN(n_0_549)); + NAND2_X1_LVT i_0_576 (.A1(aluNegAr), .A2(n_0_578), .ZN(n_0_545)); + INV_X1_LVT i_0_603 (.A(n_0_572), .ZN(n_0_571)); + NOR3_X1_LVT i_0_574 (.A1(n_0_691), .A2(n_0_545), .A3(n_0_571), .ZN(n_0_543)); + AOI22_X1_LVT i_0_573 (.A1(n_0_717), .A2(n_0_565), .B1(op1[30]), .B2(n_0_566), + .ZN(n_0_542)); + AOI21_X1_LVT i_0_572 (.A(n_0_543), .B1(op2[30]), .B2(n_0_542), .ZN(n_0_541)); + NAND2_X1_LVT i_0_579 (.A1(op2[0]), .A2(n_0_578), .ZN(n_0_548)); + NAND2_X1_LVT i_0_577 (.A1(op1[31]), .A2(n_0_571), .ZN(n_0_546)); + OAI211_X1_LVT i_0_571 (.A(n_0_549), .B(n_0_541), .C1(n_0_548), .C2(n_0_546), + .ZN(n_0_540)); + OAI221_X1_LVT i_0_581 (.A(n_0_681), .B1(op2[30]), .B2(n_0_568), .C1(n_0_572), + .C2(n_0_562), .ZN(n_0_550)); + AOI21_X1_LVT i_0_570 (.A(n_0_540), .B1(op1[30]), .B2(n_0_550), .ZN(n_0_539)); + INV_X1_LVT i_0_752 (.A(op1[23]), .ZN(n_0_719)); + OAI222_X1_LVT i_0_585 (.A1(n_0_713), .A2(n_0_605), .B1(n_0_719), .B2(n_0_615), + .C1(n_0_734), .C2(n_0_617), .ZN(n_0_554)); + AOI22_X1_LVT i_0_584 (.A1(op2[2]), .A2(n_0_554), .B1(n_0_693), .B2(n_0_610), + .ZN(n_0_553)); + OAI22_X1_LVT i_0_583 (.A1(n_0_728), .A2(n_0_553), .B1(op2[1]), .B2(n_0_601), + .ZN(n_0_552)); + AOI22_X1_LVT i_0_582 (.A1(n_0_701), .A2(n_0_585), .B1(op2[0]), .B2(n_0_552), + .ZN(n_0_551)); + OAI21_X1_LVT i_0_569 (.A(n_0_539), .B1(n_0_621), .B2(n_0_551), .ZN(result[30])); + INV_X1_LVT i_0_578 (.A(n_0_548), .ZN(n_0_547)); + NAND3_X1_LVT i_0_562 (.A1(op1[30]), .A2(n_0_571), .A3(n_0_547), .ZN(n_0_532)); + XNOR2_X1_LVT i_10_144 (.A(n_10_113), .B(n_10_114), .ZN(n_61)); + NAND2_X1_LVT i_0_558 (.A1(n_61), .A2(n_0_580), .ZN(n_0_528)); + OAI21_X1_LVT i_0_557 (.A(n_0_681), .B1(op2[29]), .B2(n_0_568), .ZN(n_0_527)); + NAND2_X1_LVT i_0_556 (.A1(op1[29]), .A2(n_0_566), .ZN(n_0_526)); + AOI22_X1_LVT i_0_555 (.A1(op1[29]), .A2(n_0_527), .B1(op2[29]), .B2(n_0_526), + .ZN(n_0_525)); + AOI21_X1_LVT i_0_554 (.A(n_0_525), .B1(n_0_710), .B2(n_0_565), .ZN(n_0_524)); + AOI211_X1_LVT i_0_553 (.A(n_0_543), .B(n_0_524), .C1(n_29), .C2(n_0_581), + .ZN(n_0_523)); + AND3_X1_LVT i_0_552 (.A1(n_0_532), .A2(n_0_528), .A3(n_0_523), .ZN(n_0_522)); + INV_X1_LVT i_0_652 (.A(n_0_621), .ZN(n_0_620)); + NAND2_X1_LVT i_0_565 (.A1(n_0_728), .A2(n_0_588), .ZN(n_0_535)); + AOI22_X1_LVT i_0_568 (.A1(n_0_723), .A2(n_0_600), .B1(op1[14]), .B2(n_0_618), + .ZN(n_0_538)); + AOI22_X1_LVT i_0_567 (.A1(n_0_693), .A2(n_0_595), .B1(op2[2]), .B2(n_0_538), + .ZN(n_0_537)); + INV_X1_LVT i_0_566 (.A(n_0_537), .ZN(n_0_536)); + OAI21_X1_LVT i_0_564 (.A(n_0_535), .B1(n_0_728), .B2(n_0_536), .ZN(n_0_534)); + OAI221_X1_LVT i_0_563 (.A(n_0_620), .B1(op2[0]), .B2(n_0_552), .C1(n_0_701), + .C2(n_0_534), .ZN(n_0_533)); + NAND2_X1_LVT i_0_561 (.A1(op2[1]), .A2(n_0_573), .ZN(n_0_531)); + INV_X1_LVT i_0_560 (.A(n_0_531), .ZN(n_0_530)); + AOI22_X1_LVT i_0_559 (.A1(op1[31]), .A2(n_0_530), .B1(op1[29]), .B2(n_0_571), + .ZN(n_0_529)); + OAI211_X1_LVT i_0_551 (.A(n_0_522), .B(n_0_533), .C1(n_0_562), .C2(n_0_529), + .ZN(result[29])); + INV_X1_LVT i_0_733 (.A(op2[28]), .ZN(n_0_700)); + AOI221_X1_LVT i_0_546 (.A(n_0_700), .B1(op1[28]), .B2(n_0_566), .C1(n_0_698), + .C2(n_0_565), .ZN(n_0_517)); + OAI21_X1_LVT i_0_543 (.A(n_0_681), .B1(op2[28]), .B2(n_0_568), .ZN(n_0_514)); + AOI22_X1_LVT i_0_542 (.A1(n_28), .A2(n_0_581), .B1(op1[28]), .B2(n_0_514), + .ZN(n_0_513)); + XNOR2_X1_LVT i_10_140 (.A(n_10_110), .B(n_10_111), .ZN(n_60)); + NAND2_X1_LVT i_0_544 (.A1(n_60), .A2(n_0_580), .ZN(n_0_515)); + NAND2_X1_LVT i_0_545 (.A1(op1[31]), .A2(n_0_574), .ZN(n_0_516)); + OAI211_X1_LVT i_0_541 (.A(n_0_513), .B(n_0_515), .C1(n_0_545), .C2(n_0_516), + .ZN(n_0_512)); + AOI22_X1_LVT i_0_540 (.A1(op1[30]), .A2(n_0_530), .B1(op1[28]), .B2(n_0_571), + .ZN(n_0_511)); + OAI22_X1_LVT i_0_539 (.A1(n_0_562), .A2(n_0_511), .B1(n_0_548), .B2(n_0_529), + .ZN(n_0_510)); + NOR3_X1_LVT i_0_538 (.A1(n_0_517), .A2(n_0_512), .A3(n_0_510), .ZN(n_0_509)); + OAI22_X1_LVT i_0_550 (.A1(n_0_714), .A2(n_0_617), .B1(op2[3]), .B2(n_0_608), + .ZN(n_0_521)); + OAI22_X1_LVT i_0_549 (.A1(op2[2]), .A2(n_0_602), .B1(n_0_693), .B2(n_0_521), + .ZN(n_0_520)); + AOI22_X1_LVT i_0_548 (.A1(op2[1]), .A2(n_0_520), .B1(n_0_728), .B2(n_0_553), + .ZN(n_0_519)); + OAI22_X1_LVT i_0_547 (.A1(op2[0]), .A2(n_0_534), .B1(n_0_701), .B2(n_0_519), + .ZN(n_0_518)); + OAI21_X1_LVT i_0_537 (.A(n_0_509), .B1(n_0_621), .B2(n_0_518), .ZN(result[28])); + XNOR2_X1_LVT i_10_136 (.A(n_10_107), .B(n_10_108), .ZN(n_59)); + AOI22_X1_LVT i_0_517 (.A1(n_27), .A2(n_0_581), .B1(n_59), .B2(n_0_580), + .ZN(n_0_489)); + INV_X1_LVT i_0_721 (.A(op1[27]), .ZN(n_0_688)); + OAI21_X1_LVT i_0_516 (.A(n_0_681), .B1(op2[27]), .B2(n_0_568), .ZN(n_0_488)); + INV_X1_LVT i_0_515 (.A(n_0_488), .ZN(n_0_487)); + OAI221_X1_LVT i_0_514 (.A(n_0_489), .B1(n_0_545), .B2(n_0_516), .C1(n_0_688), + .C2(n_0_487), .ZN(n_0_486)); + OAI21_X1_LVT i_0_530 (.A(op2[1]), .B1(n_0_710), .B2(n_0_574), .ZN(n_0_502)); + OAI21_X1_LVT i_0_529 (.A(n_0_728), .B1(n_0_688), .B2(n_0_574), .ZN(n_0_501)); + NAND2_X1_LVT i_0_528 (.A1(n_0_502), .A2(n_0_501), .ZN(n_0_500)); + AOI21_X1_LVT i_0_527 (.A(n_0_545), .B1(n_0_701), .B2(n_0_500), .ZN(n_0_499)); + NAND2_X1_LVT i_0_609 (.A1(n_0_682), .A2(n_0_578), .ZN(n_0_577)); + NOR2_X1_LVT i_0_526 (.A1(op2[4]), .A2(n_0_693), .ZN(n_0_498)); + NAND2_X1_LVT i_0_525 (.A1(n_0_723), .A2(n_0_498), .ZN(n_0_497)); + OAI22_X1_LVT i_0_523 (.A1(n_0_688), .A2(n_0_574), .B1(n_0_691), .B2(n_0_497), + .ZN(n_0_495)); + OAI21_X1_LVT i_0_522 (.A(n_0_502), .B1(op2[1]), .B2(n_0_495), .ZN(n_0_494)); + AOI21_X1_LVT i_0_521 (.A(n_0_577), .B1(n_0_701), .B2(n_0_494), .ZN(n_0_493)); + NOR2_X1_LVT i_0_520 (.A1(n_0_499), .A2(n_0_493), .ZN(n_0_492)); + AOI21_X1_LVT i_0_519 (.A(n_0_492), .B1(op2[0]), .B2(n_0_511), .ZN(n_0_491)); + AOI22_X1_LVT i_0_518 (.A1(n_0_688), .A2(n_0_565), .B1(op1[27]), .B2(n_0_566), + .ZN(n_0_490)); + AOI211_X1_LVT i_0_513 (.A(n_0_486), .B(n_0_491), .C1(op2[27]), .C2(n_0_490), + .ZN(n_0_485)); + NOR3_X1_LVT i_0_536 (.A1(op2[4]), .A2(n_0_696), .A3(n_0_723), .ZN(n_0_508)); + AOI21_X1_LVT i_0_535 (.A(n_0_508), .B1(n_0_723), .B2(n_0_591), .ZN(n_0_507)); + OAI22_X1_LVT i_0_534 (.A1(op2[2]), .A2(n_0_592), .B1(n_0_693), .B2(n_0_507), + .ZN(n_0_506)); + NOR2_X1_LVT i_0_533 (.A1(n_0_728), .A2(n_0_506), .ZN(n_0_505)); + AOI21_X1_LVT i_0_532 (.A(n_0_505), .B1(n_0_728), .B2(n_0_536), .ZN(n_0_504)); + OAI22_X1_LVT i_0_531 (.A1(n_0_701), .A2(n_0_504), .B1(op2[0]), .B2(n_0_519), + .ZN(n_0_503)); + OAI21_X1_LVT i_0_512 (.A(n_0_485), .B1(n_0_621), .B2(n_0_503), .ZN(result[27])); + OAI21_X1_LVT i_0_500 (.A(n_0_681), .B1(op2[26]), .B2(n_0_568), .ZN(n_0_473)); + NAND2_X1_LVT i_0_499 (.A1(op1[26]), .A2(n_0_473), .ZN(n_0_472)); + XNOR2_X1_LVT i_10_133 (.A(n_10_103), .B(n_10_106), .ZN(n_58)); + AOI22_X1_LVT i_0_498 (.A1(n_58), .A2(n_0_580), .B1(n_26), .B2(n_0_581), + .ZN(n_0_471)); + INV_X1_LVT i_0_744 (.A(op1[26]), .ZN(n_0_711)); + OAI221_X1_LVT i_0_501 (.A(op2[26]), .B1(op1[26]), .B2(n_0_564), .C1(n_0_711), + .C2(n_0_567), .ZN(n_0_474)); + NAND3_X1_LVT i_0_497 (.A1(n_0_472), .A2(n_0_471), .A3(n_0_474), .ZN(n_0_470)); + INV_X1_LVT i_0_524 (.A(n_0_497), .ZN(n_0_496)); + AOI22_X1_LVT i_0_505 (.A1(op1[30]), .A2(n_0_496), .B1(op1[26]), .B2(n_0_573), + .ZN(n_0_478)); + NOR2_X1_LVT i_0_504 (.A1(op2[1]), .A2(n_0_478), .ZN(n_0_477)); + AOI21_X1_LVT i_0_503 (.A(n_0_477), .B1(op1[28]), .B2(n_0_530), .ZN(n_0_476)); + NAND2_X1_LVT i_0_502 (.A1(n_0_701), .A2(n_0_476), .ZN(n_0_475)); + AOI21_X1_LVT i_0_489 (.A(n_0_577), .B1(op2[0]), .B2(n_0_494), .ZN(n_0_462)); + AOI21_X1_LVT i_0_488 (.A(n_0_470), .B1(n_0_475), .B2(n_0_462), .ZN(n_0_461)); + AOI21_X1_LVT i_0_511 (.A(n_0_616), .B1(n_0_738), .B2(n_0_706), .ZN(n_0_484)); + AOI21_X1_LVT i_0_510 (.A(n_0_484), .B1(n_0_723), .B2(op1[19]), .ZN(n_0_483)); + INV_X1_LVT i_0_757 (.A(op1[3]), .ZN(n_0_724)); + NOR2_X1_LVT i_0_687 (.A1(n_0_724), .A2(op2[3]), .ZN(n_0_654)); + INV_X1_LVT i_0_686 (.A(n_0_654), .ZN(n_0_653)); + AOI21_X1_LVT i_0_509 (.A(n_0_483), .B1(op2[4]), .B2(n_0_653), .ZN(n_0_482)); + AOI22_X1_LVT i_0_508 (.A1(n_0_693), .A2(n_0_554), .B1(op2[2]), .B2(n_0_482), + .ZN(n_0_481)); + OAI22_X1_LVT i_0_507 (.A1(n_0_728), .A2(n_0_481), .B1(op2[1]), .B2(n_0_520), + .ZN(n_0_480)); + AOI22_X1_LVT i_0_506 (.A1(op2[0]), .A2(n_0_480), .B1(n_0_701), .B2(n_0_504), + .ZN(n_0_479)); + NAND3_X1_LVT i_0_491 (.A1(op2[0]), .A2(n_0_516), .A3(n_0_500), .ZN(n_0_464)); + NAND2_X1_LVT i_0_494 (.A1(op1[31]), .A2(n_0_615), .ZN(n_0_467)); + OAI21_X1_LVT i_0_492 (.A(n_0_467), .B1(n_0_728), .B2(n_0_516), .ZN(n_0_465)); + OAI21_X1_LVT i_0_490 (.A(n_0_464), .B1(n_0_475), .B2(n_0_465), .ZN(n_0_463)); + OAI221_X1_LVT i_0_487 (.A(n_0_461), .B1(n_0_621), .B2(n_0_479), .C1(n_0_545), + .C2(n_0_463), .ZN(result[26])); + INV_X1_LVT i_10_126 (.A(n_10_100), .ZN(n_10_101)); + NOR2_X1_LVT i_10_127 (.A1(n_10_99), .A2(n_10_101), .ZN(n_10_102)); + XNOR2_X1_LVT i_10_128 (.A(n_10_97), .B(n_10_102), .ZN(n_57)); + AOI22_X1_LVT i_0_479 (.A1(n_57), .A2(n_0_580), .B1(n_25), .B2(n_0_581), + .ZN(n_0_453)); + INV_X1_LVT i_0_730 (.A(op2[25]), .ZN(n_0_697)); + AOI21_X1_LVT i_0_478 (.A(aluBypass), .B1(n_0_697), .B2(n_0_569), .ZN(n_0_452)); + AOI22_X1_LVT i_0_480 (.A1(op1[25]), .A2(n_0_567), .B1(n_0_699), .B2(n_0_564), + .ZN(n_0_454)); + OAI221_X1_LVT i_0_477 (.A(n_0_453), .B1(n_0_699), .B2(n_0_452), .C1(n_0_697), + .C2(n_0_454), .ZN(n_0_451)); + INV_X1_LVT i_0_575 (.A(n_0_545), .ZN(n_0_544)); + AOI21_X1_LVT i_0_476 (.A(n_0_451), .B1(n_0_544), .B2(n_0_465), .ZN(n_0_450)); + AOI22_X1_LVT i_0_475 (.A1(op1[29]), .A2(n_0_496), .B1(op1[25]), .B2(n_0_573), + .ZN(n_0_449)); + NAND2_X1_LVT i_0_474 (.A1(n_0_728), .A2(n_0_449), .ZN(n_0_448)); + OAI21_X1_LVT i_0_473 (.A(n_0_448), .B1(n_0_728), .B2(n_0_495), .ZN(n_0_447)); + OAI22_X1_LVT i_0_472 (.A1(n_0_548), .A2(n_0_476), .B1(n_0_562), .B2(n_0_447), + .ZN(n_0_446)); + INV_X1_LVT i_0_471 (.A(n_0_446), .ZN(n_0_445)); + OAI222_X1_LVT i_0_486 (.A1(n_0_733), .A2(n_0_617), .B1(n_0_694), .B2(n_0_605), + .C1(n_0_705), .C2(n_0_615), .ZN(n_0_460)); + NOR2_X1_LVT i_0_485 (.A1(n_0_693), .A2(n_0_460), .ZN(n_0_459)); + AOI21_X1_LVT i_0_484 (.A(n_0_459), .B1(n_0_693), .B2(n_0_538), .ZN(n_0_458)); + OAI22_X1_LVT i_0_483 (.A1(n_0_728), .A2(n_0_458), .B1(op2[1]), .B2(n_0_506), + .ZN(n_0_457)); + INV_X1_LVT i_0_482 (.A(n_0_457), .ZN(n_0_456)); + OAI221_X1_LVT i_0_481 (.A(n_0_620), .B1(n_0_701), .B2(n_0_456), .C1(op2[0]), + .C2(n_0_480), .ZN(n_0_455)); + NAND3_X1_LVT i_0_470 (.A1(n_0_450), .A2(n_0_445), .A3(n_0_455), .ZN( + result[25])); + INV_X1_LVT i_0_493 (.A(n_0_467), .ZN(n_0_466)); + OAI211_X1_LVT i_0_455 (.A(n_0_544), .B(n_0_465), .C1(op2[0]), .C2(n_0_466), + .ZN(n_0_430)); + OAI21_X1_LVT i_0_462 (.A(n_0_681), .B1(op2[24]), .B2(n_0_568), .ZN(n_0_437)); + XNOR2_X1_LVT i_10_120 (.A(n_10_94), .B(n_10_95), .ZN(n_56)); + AOI222_X1_LVT i_0_461 (.A1(op1[24]), .A2(n_0_437), .B1(n_56), .B2(n_0_580), + .C1(n_24), .C2(n_0_581), .ZN(n_0_436)); + INV_X1_LVT i_0_460 (.A(n_0_436), .ZN(n_0_435)); + AOI22_X1_LVT i_0_458 (.A1(op1[24]), .A2(n_0_573), .B1(op1[28]), .B2(n_0_496), + .ZN(n_0_433)); + OAI22_X1_LVT i_0_457 (.A1(op2[1]), .A2(n_0_433), .B1(n_0_728), .B2(n_0_478), + .ZN(n_0_432)); + INV_X1_LVT i_0_456 (.A(n_0_432), .ZN(n_0_431)); + OAI22_X1_LVT i_0_454 (.A1(n_0_562), .A2(n_0_431), .B1(n_0_548), .B2(n_0_447), + .ZN(n_0_429)); + AOI22_X1_LVT i_0_459 (.A1(n_0_736), .A2(n_0_565), .B1(op1[24]), .B2(n_0_566), + .ZN(n_0_434)); + AOI211_X1_LVT i_0_453 (.A(n_0_435), .B(n_0_429), .C1(op2[24]), .C2(n_0_434), + .ZN(n_0_428)); + NAND2_X1_LVT i_0_467 (.A1(n_0_693), .A2(n_0_521), .ZN(n_0_442)); + NOR2_X1_LVT i_0_469 (.A1(op2[3]), .A2(n_0_603), .ZN(n_0_444)); + AOI21_X1_LVT i_0_468 (.A(n_0_444), .B1(op1[9]), .B2(n_0_618), .ZN(n_0_443)); + OAI21_X1_LVT i_0_466 (.A(n_0_442), .B1(n_0_693), .B2(n_0_443), .ZN(n_0_441)); + NAND2_X1_LVT i_0_465 (.A1(op2[1]), .A2(n_0_441), .ZN(n_0_440)); + OAI21_X1_LVT i_0_464 (.A(n_0_440), .B1(op2[1]), .B2(n_0_481), .ZN(n_0_439)); + OAI221_X1_LVT i_0_463 (.A(n_0_620), .B1(op2[0]), .B2(n_0_456), .C1(n_0_701), + .C2(n_0_439), .ZN(n_0_438)); + NAND3_X1_LVT i_0_452 (.A1(n_0_430), .A2(n_0_428), .A3(n_0_438), .ZN( + result[24])); + INV_X1_LVT i_0_751 (.A(op2[23]), .ZN(n_0_718)); + AOI221_X1_LVT i_0_440 (.A(n_0_718), .B1(op1[23]), .B2(n_0_566), .C1(n_0_719), + .C2(n_0_565), .ZN(n_0_416)); + INV_X1_LVT i_10_115 (.A(n_10_91), .ZN(n_10_92)); + NOR2_X1_LVT i_10_116 (.A1(n_10_90), .A2(n_10_92), .ZN(n_10_93)); + XNOR2_X1_LVT i_10_117 (.A(n_10_88), .B(n_10_93), .ZN(n_55)); + AOI222_X1_LVT i_0_438 (.A1(n_23), .A2(n_0_581), .B1(n_0_544), .B2(n_0_466), + .C1(n_55), .C2(n_0_580), .ZN(n_0_414)); + OAI21_X1_LVT i_0_437 (.A(n_0_414), .B1(n_0_548), .B2(n_0_431), .ZN(n_0_413)); + OAI21_X1_LVT i_0_439 (.A(n_0_681), .B1(op2[23]), .B2(n_0_568), .ZN(n_0_415)); + AOI211_X1_LVT i_0_436 (.A(n_0_416), .B(n_0_413), .C1(op1[23]), .C2(n_0_415), + .ZN(n_0_412)); + AOI22_X1_LVT i_0_444 (.A1(n_0_723), .A2(n_0_719), .B1(op2[3]), .B2(n_0_691), + .ZN(n_0_420)); + AOI22_X1_LVT i_0_443 (.A1(n_0_575), .A2(n_0_420), .B1(op1[27]), .B2(n_0_496), + .ZN(n_0_419)); + AOI22_X1_LVT i_0_442 (.A1(op2[1]), .A2(n_0_449), .B1(n_0_728), .B2(n_0_419), + .ZN(n_0_418)); + INV_X1_LVT i_0_441 (.A(n_0_418), .ZN(n_0_417)); + NAND2_X1_LVT i_0_447 (.A1(n_0_728), .A2(n_0_458), .ZN(n_0_423)); + NOR2_X1_LVT i_0_451 (.A1(op2[3]), .A2(n_0_594), .ZN(n_0_427)); + AOI21_X1_LVT i_0_450 (.A(n_0_427), .B1(op1[8]), .B2(n_0_618), .ZN(n_0_426)); + OAI22_X1_LVT i_0_449 (.A1(n_0_693), .A2(n_0_426), .B1(op2[2]), .B2(n_0_507), + .ZN(n_0_425)); + INV_X1_LVT i_0_448 (.A(n_0_425), .ZN(n_0_424)); + OAI21_X1_LVT i_0_446 (.A(n_0_423), .B1(n_0_728), .B2(n_0_424), .ZN(n_0_422)); + AOI22_X1_LVT i_0_445 (.A1(op2[0]), .A2(n_0_422), .B1(n_0_701), .B2(n_0_439), + .ZN(n_0_421)); + OAI221_X1_LVT i_0_435 (.A(n_0_412), .B1(n_0_562), .B2(n_0_417), .C1(n_0_621), + .C2(n_0_421), .ZN(result[23])); + XNOR2_X1_LVT i_10_109 (.A(n_10_85), .B(n_10_86), .ZN(n_54)); + AOI22_X1_LVT i_0_419 (.A1(n_54), .A2(n_0_580), .B1(n_22), .B2(n_0_581), + .ZN(n_0_396)); + INV_X1_LVT i_0_719 (.A(op2[22]), .ZN(n_0_686)); + AOI21_X1_LVT i_0_420 (.A(aluBypass), .B1(n_0_686), .B2(n_0_569), .ZN(n_0_397)); + OAI21_X1_LVT i_0_418 (.A(n_0_396), .B1(n_0_687), .B2(n_0_397), .ZN(n_0_395)); + AOI22_X1_LVT i_0_421 (.A1(op1[22]), .A2(n_0_566), .B1(n_0_687), .B2(n_0_565), + .ZN(n_0_398)); + AOI21_X1_LVT i_0_417 (.A(n_0_395), .B1(op2[22]), .B2(n_0_398), .ZN(n_0_394)); + NAND2_X1_LVT i_0_432 (.A1(n_0_728), .A2(n_0_441), .ZN(n_0_409)); + AND2_X1_LVT i_0_434 (.A1(n_0_738), .A2(n_0_619), .ZN(n_0_411)); + AOI22_X1_LVT i_0_433 (.A1(n_0_693), .A2(n_0_482), .B1(op2[2]), .B2(n_0_411), + .ZN(n_0_410)); + OAI21_X1_LVT i_0_431 (.A(n_0_409), .B1(n_0_728), .B2(n_0_410), .ZN(n_0_408)); + OAI22_X1_LVT i_0_430 (.A1(n_0_701), .A2(n_0_408), .B1(op2[0]), .B2(n_0_422), + .ZN(n_0_407)); + AOI22_X1_LVT i_0_429 (.A1(n_0_723), .A2(n_0_687), .B1(op2[3]), .B2(n_0_717), + .ZN(n_0_406)); + AOI22_X1_LVT i_0_428 (.A1(n_0_575), .A2(n_0_406), .B1(op1[26]), .B2(n_0_496), + .ZN(n_0_405)); + AND2_X1_LVT i_0_427 (.A1(n_0_728), .A2(n_0_405), .ZN(n_0_404)); + AOI21_X1_LVT i_0_426 (.A(n_0_404), .B1(op2[1]), .B2(n_0_433), .ZN(n_0_403)); + INV_X1_LVT i_0_425 (.A(n_0_403), .ZN(n_0_402)); + OAI222_X1_LVT i_0_424 (.A1(n_0_545), .A2(n_0_467), .B1(n_0_701), .B2(n_0_417), + .C1(op2[0]), .C2(n_0_402), .ZN(n_0_401)); + NOR2_X1_LVT i_0_496 (.A1(n_0_738), .A2(n_0_691), .ZN(n_0_469)); + INV_X1_LVT i_0_495 (.A(n_0_469), .ZN(n_0_468)); + NAND3_X1_LVT i_0_423 (.A1(n_0_693), .A2(n_0_468), .A3(n_0_404), .ZN(n_0_400)); + OAI21_X1_LVT i_0_422 (.A(n_0_401), .B1(op2[0]), .B2(n_0_400), .ZN(n_0_399)); + OAI221_X1_LVT i_0_416 (.A(n_0_394), .B1(n_0_621), .B2(n_0_407), .C1(n_0_579), + .C2(n_0_399), .ZN(result[22])); + INV_X1_LVT i_0_759 (.A(op1[21]), .ZN(n_0_726)); + AOI22_X1_LVT i_0_399 (.A1(op1[21]), .A2(n_0_566), .B1(n_0_726), .B2(n_0_565), + .ZN(n_0_377)); + NOR2_X1_LVT i_0_692 (.A1(n_0_726), .A2(op2[21]), .ZN(n_0_659)); + AOI222_X1_LVT i_0_398 (.A1(op2[21]), .A2(n_0_377), .B1(n_21), .B2(n_0_581), + .C1(n_0_659), .C2(n_0_569), .ZN(n_0_376)); + INV_X1_LVT i_0_397 (.A(n_0_376), .ZN(n_0_375)); + INV_X1_LVT i_10_104 (.A(n_10_82), .ZN(n_10_83)); + NOR2_X1_LVT i_10_105 (.A1(n_10_81), .A2(n_10_83), .ZN(n_10_84)); + XNOR2_X1_LVT i_10_106 (.A(n_10_79), .B(n_10_84), .ZN(n_53)); + AOI221_X1_LVT i_0_396 (.A(n_0_375), .B1(n_53), .B2(n_0_580), .C1(op1[21]), + .C2(aluBypass), .ZN(n_0_374)); + INV_X1_LVT i_0_608 (.A(n_0_577), .ZN(n_0_576)); + NAND2_X1_LVT i_0_403 (.A1(op2[0]), .A2(n_0_402), .ZN(n_0_381)); + AND2_X1_LVT i_0_410 (.A1(op2[1]), .A2(n_0_419), .ZN(n_0_388)); + OAI22_X1_LVT i_0_408 (.A1(n_0_723), .A2(n_0_710), .B1(n_0_726), .B2(op2[3]), + .ZN(n_0_386)); + AOI22_X1_LVT i_0_407 (.A1(n_0_575), .A2(n_0_386), .B1(op1[25]), .B2(n_0_496), + .ZN(n_0_385)); + AOI21_X1_LVT i_0_395 (.A(n_0_388), .B1(n_0_728), .B2(n_0_385), .ZN(n_0_373)); + OAI211_X1_LVT i_0_394 (.A(n_0_576), .B(n_0_381), .C1(op2[0]), .C2(n_0_373), + .ZN(n_0_372)); + AOI21_X1_LVT i_0_402 (.A(n_0_381), .B1(n_0_466), .B2(n_0_400), .ZN(n_0_380)); + INV_X1_LVT i_0_401 (.A(n_0_380), .ZN(n_0_379)); + NOR2_X1_LVT i_0_409 (.A1(n_0_575), .A2(n_0_467), .ZN(n_0_387)); + INV_X1_LVT i_0_406 (.A(n_0_385), .ZN(n_0_384)); + NOR2_X1_LVT i_0_405 (.A1(n_0_387), .A2(n_0_384), .ZN(n_0_383)); + AOI22_X1_LVT i_0_404 (.A1(n_0_467), .A2(n_0_388), .B1(n_0_728), .B2(n_0_383), + .ZN(n_0_382)); + OAI211_X1_LVT i_0_400 (.A(n_0_544), .B(n_0_379), .C1(op2[0]), .C2(n_0_382), + .ZN(n_0_378)); + AOI22_X1_LVT i_0_415 (.A1(op1[14]), .A2(n_0_616), .B1(op1[6]), .B2(n_0_618), + .ZN(n_0_393)); + NOR2_X1_LVT i_0_414 (.A1(n_0_693), .A2(n_0_393), .ZN(n_0_392)); + AOI21_X1_LVT i_0_413 (.A(n_0_392), .B1(n_0_693), .B2(n_0_460), .ZN(n_0_391)); + OAI22_X1_LVT i_0_412 (.A1(n_0_728), .A2(n_0_391), .B1(op2[1]), .B2(n_0_424), + .ZN(n_0_390)); + OAI221_X1_LVT i_0_411 (.A(n_0_620), .B1(op2[0]), .B2(n_0_408), .C1(n_0_701), + .C2(n_0_390), .ZN(n_0_389)); + NAND4_X1_LVT i_0_393 (.A1(n_0_374), .A2(n_0_372), .A3(n_0_378), .A4(n_0_389), + .ZN(result[21])); + OAI221_X1_LVT i_0_388 (.A(op2[20]), .B1(n_0_727), .B2(n_0_567), .C1(op1[20]), + .C2(n_0_564), .ZN(n_0_367)); + NOR2_X1_LVT i_0_691 (.A1(n_0_727), .A2(op2[20]), .ZN(n_0_658)); + AOI22_X1_LVT i_0_387 (.A1(op1[20]), .A2(aluBypass), .B1(n_0_658), .B2(n_0_569), + .ZN(n_0_366)); + XNOR2_X1_LVT i_10_98 (.A(n_10_76), .B(n_10_77), .ZN(n_52)); + AOI22_X1_LVT i_0_386 (.A1(n_52), .A2(n_0_580), .B1(n_20), .B2(n_0_581), + .ZN(n_0_365)); + AOI221_X1_LVT i_0_392 (.A(op2[4]), .B1(n_0_727), .B2(n_0_723), .C1(op2[3]), + .C2(n_0_698), .ZN(n_0_371)); + AOI22_X1_LVT i_0_391 (.A1(op1[24]), .A2(n_0_496), .B1(n_0_693), .B2(n_0_371), + .ZN(n_0_370)); + OAI22_X1_LVT i_0_390 (.A1(op2[1]), .A2(n_0_370), .B1(n_0_728), .B2(n_0_405), + .ZN(n_0_369)); + OAI221_X1_LVT i_0_385 (.A(n_0_576), .B1(n_0_701), .B2(n_0_373), .C1(op2[0]), + .C2(n_0_369), .ZN(n_0_364)); + AND4_X1_LVT i_0_384 (.A1(n_0_367), .A2(n_0_366), .A3(n_0_365), .A4(n_0_364), + .ZN(n_0_363)); + AOI22_X1_LVT i_0_383 (.A1(op1[13]), .A2(n_0_616), .B1(op1[5]), .B2(n_0_618), + .ZN(n_0_362)); + AOI22_X1_LVT i_0_382 (.A1(op2[2]), .A2(n_0_362), .B1(n_0_693), .B2(n_0_443), + .ZN(n_0_361)); + NAND2_X1_LVT i_0_381 (.A1(op2[1]), .A2(n_0_361), .ZN(n_0_360)); + OAI21_X1_LVT i_0_380 (.A(n_0_360), .B1(op2[1]), .B2(n_0_410), .ZN(n_0_359)); + OAI221_X1_LVT i_0_379 (.A(n_0_620), .B1(n_0_701), .B2(n_0_359), .C1(op2[0]), + .C2(n_0_390), .ZN(n_0_358)); + OR2_X1_LVT i_0_389 (.A1(n_0_387), .A2(n_0_369), .ZN(n_0_368)); + AOI22_X1_LVT i_0_378 (.A1(op2[0]), .A2(n_0_382), .B1(n_0_701), .B2(n_0_368), + .ZN(n_0_357)); + OAI211_X1_LVT i_0_377 (.A(n_0_363), .B(n_0_358), .C1(n_0_545), .C2(n_0_357), + .ZN(result[20])); + OAI22_X1_LVT i_0_370 (.A1(op2[3]), .A2(n_0_689), .B1(n_0_723), .B2(n_0_688), + .ZN(n_0_350)); + AND2_X1_LVT i_0_369 (.A1(n_0_738), .A2(n_0_350), .ZN(n_0_349)); + AOI22_X1_LVT i_0_368 (.A1(n_0_498), .A2(n_0_420), .B1(n_0_693), .B2(n_0_349), + .ZN(n_0_348)); + AND2_X1_LVT i_0_367 (.A1(n_0_728), .A2(n_0_348), .ZN(n_0_347)); + AOI21_X1_LVT i_0_359 (.A(n_0_347), .B1(op2[1]), .B2(n_0_385), .ZN(n_0_339)); + OAI221_X1_LVT i_0_357 (.A(n_0_576), .B1(n_0_701), .B2(n_0_369), .C1(op2[0]), + .C2(n_0_339), .ZN(n_0_337)); + NAND2_X1_LVT i_0_363 (.A1(n_19), .A2(n_0_581), .ZN(n_0_343)); + INV_X1_LVT i_0_723 (.A(op2[19]), .ZN(n_0_690)); + AOI221_X1_LVT i_0_364 (.A(n_0_690), .B1(n_0_689), .B2(n_0_565), .C1(op1[19]), + .C2(n_0_566), .ZN(n_0_344)); + XNOR2_X1_LVT i_10_94 (.A(n_10_73), .B(n_10_74), .ZN(n_51)); + AOI221_X1_LVT i_0_361 (.A(n_0_344), .B1(op1[19]), .B2(aluBypass), .C1(n_51), + .C2(n_0_580), .ZN(n_0_341)); + NAND3_X1_LVT i_0_362 (.A1(n_0_690), .A2(op1[19]), .A3(n_0_569), .ZN(n_0_342)); + NAND3_X1_LVT i_0_360 (.A1(n_0_343), .A2(n_0_341), .A3(n_0_342), .ZN(n_0_340)); + AOI22_X1_LVT i_0_376 (.A1(op1[12]), .A2(n_0_616), .B1(op1[4]), .B2(n_0_618), + .ZN(n_0_356)); + OAI22_X1_LVT i_0_375 (.A1(n_0_693), .A2(n_0_356), .B1(op2[2]), .B2(n_0_426), + .ZN(n_0_355)); + INV_X1_LVT i_0_374 (.A(n_0_355), .ZN(n_0_354)); + OAI22_X1_LVT i_0_373 (.A1(op2[1]), .A2(n_0_391), .B1(n_0_728), .B2(n_0_354), + .ZN(n_0_353)); + AOI22_X1_LVT i_0_372 (.A1(n_0_701), .A2(n_0_359), .B1(op2[0]), .B2(n_0_353), + .ZN(n_0_352)); + INV_X1_LVT i_0_371 (.A(n_0_352), .ZN(n_0_351)); + AOI21_X1_LVT i_0_358 (.A(n_0_340), .B1(n_0_620), .B2(n_0_351), .ZN(n_0_338)); + AOI22_X1_LVT i_0_366 (.A1(n_0_468), .A2(n_0_347), .B1(op2[1]), .B2(n_0_383), + .ZN(n_0_346)); + AOI22_X1_LVT i_0_365 (.A1(n_0_701), .A2(n_0_346), .B1(op2[0]), .B2(n_0_368), + .ZN(n_0_345)); + OAI211_X1_LVT i_0_356 (.A(n_0_337), .B(n_0_338), .C1(n_0_545), .C2(n_0_345), + .ZN(result[19])); + XNOR2_X1_LVT i_10_90 (.A(n_10_70), .B(n_10_71), .ZN(n_50)); + NAND2_X1_LVT i_0_342 (.A1(n_50), .A2(n_0_580), .ZN(n_0_323)); + OAI21_X1_LVT i_0_343 (.A(n_0_681), .B1(op2[18]), .B2(n_0_568), .ZN(n_0_324)); + AOI22_X1_LVT i_0_341 (.A1(op1[18]), .A2(n_0_324), .B1(n_18), .B2(n_0_581), + .ZN(n_0_322)); + OAI221_X1_LVT i_0_340 (.A(op2[18]), .B1(n_0_705), .B2(n_0_567), .C1(op1[18]), + .C2(n_0_564), .ZN(n_0_321)); + NAND3_X1_LVT i_0_339 (.A1(n_0_323), .A2(n_0_322), .A3(n_0_321), .ZN(n_0_320)); + OAI22_X1_LVT i_0_351 (.A1(op2[3]), .A2(n_0_705), .B1(n_0_723), .B2(n_0_711), + .ZN(n_0_332)); + AND2_X1_LVT i_0_350 (.A1(n_0_738), .A2(n_0_332), .ZN(n_0_331)); + AOI22_X1_LVT i_0_349 (.A1(n_0_498), .A2(n_0_406), .B1(n_0_693), .B2(n_0_331), + .ZN(n_0_330)); + NAND2_X1_LVT i_0_348 (.A1(n_0_728), .A2(n_0_330), .ZN(n_0_329)); + NAND2_X1_LVT i_0_347 (.A1(op2[1]), .A2(n_0_370), .ZN(n_0_328)); + AND2_X1_LVT i_0_338 (.A1(n_0_329), .A2(n_0_328), .ZN(n_0_319)); + OAI22_X1_LVT i_0_337 (.A1(op2[0]), .A2(n_0_319), .B1(n_0_701), .B2(n_0_339), + .ZN(n_0_318)); + INV_X1_LVT i_0_336 (.A(n_0_318), .ZN(n_0_317)); + AOI21_X1_LVT i_0_335 (.A(n_0_320), .B1(n_0_578), .B2(n_0_317), .ZN(n_0_316)); + OAI22_X1_LVT i_0_346 (.A1(n_0_469), .A2(n_0_329), .B1(n_0_387), .B2(n_0_328), + .ZN(n_0_327)); + NAND2_X1_LVT i_0_344 (.A1(n_0_544), .A2(n_0_346), .ZN(n_0_325)); + NAND2_X1_LVT i_0_354 (.A1(n_0_728), .A2(n_0_361), .ZN(n_0_335)); + AOI22_X1_LVT i_0_355 (.A1(n_0_612), .A2(n_0_498), .B1(n_0_693), .B2(n_0_411), + .ZN(n_0_336)); + OAI21_X1_LVT i_0_353 (.A(n_0_335), .B1(n_0_728), .B2(n_0_336), .ZN(n_0_334)); + AOI22_X1_LVT i_0_352 (.A1(n_0_701), .A2(n_0_353), .B1(op2[0]), .B2(n_0_334), + .ZN(n_0_333)); + OAI221_X1_LVT i_0_334 (.A(n_0_316), .B1(n_0_327), .B2(n_0_325), .C1(n_0_621), + .C2(n_0_333), .ZN(result[18])); + NAND2_X1_LVT i_0_325 (.A1(n_17), .A2(n_0_581), .ZN(n_0_307)); + INV_X1_LVT i_0_765 (.A(op1[17]), .ZN(n_0_732)); + AOI22_X1_LVT i_0_324 (.A1(n_0_732), .A2(n_0_565), .B1(op1[17]), .B2(n_0_566), + .ZN(n_0_306)); + NOR2_X1_LVT i_0_693 (.A1(n_0_732), .A2(op2[17]), .ZN(n_0_660)); + XNOR2_X1_LVT i_10_86 (.A(n_10_67), .B(n_10_68), .ZN(n_49)); + AOI222_X1_LVT i_0_323 (.A1(op2[17]), .A2(n_0_306), .B1(n_0_660), .B2(n_0_569), + .C1(n_49), .C2(n_0_580), .ZN(n_0_305)); + OAI211_X1_LVT i_0_322 (.A(n_0_307), .B(n_0_305), .C1(n_0_732), .C2(n_0_681), + .ZN(n_0_304)); + AOI22_X1_LVT i_0_331 (.A1(op2[3]), .A2(op1[25]), .B1(op1[17]), .B2(n_0_723), + .ZN(n_0_313)); + NOR2_X1_LVT i_0_330 (.A1(op2[4]), .A2(n_0_313), .ZN(n_0_312)); + AOI22_X1_LVT i_0_329 (.A1(n_0_498), .A2(n_0_386), .B1(n_0_693), .B2(n_0_312), + .ZN(n_0_311)); + OAI22_X1_LVT i_0_328 (.A1(op2[1]), .A2(n_0_311), .B1(n_0_728), .B2(n_0_348), + .ZN(n_0_310)); + OR2_X1_LVT i_0_327 (.A1(op2[0]), .A2(n_0_310), .ZN(n_0_309)); + OAI21_X1_LVT i_0_321 (.A(n_0_576), .B1(n_0_701), .B2(n_0_319), .ZN(n_0_303)); + INV_X1_LVT i_0_320 (.A(n_0_303), .ZN(n_0_302)); + AOI21_X1_LVT i_0_319 (.A(n_0_304), .B1(n_0_309), .B2(n_0_302), .ZN(n_0_301)); + INV_X1_LVT i_0_345 (.A(n_0_327), .ZN(n_0_326)); + OAI22_X1_LVT i_0_326 (.A1(n_0_701), .A2(n_0_326), .B1(n_0_469), .B2(n_0_309), + .ZN(n_0_308)); + NOR2_X1_LVT i_0_318 (.A1(op2[2]), .A2(n_0_393), .ZN(n_0_300)); + AOI21_X1_LVT i_0_317 (.A(n_0_300), .B1(n_0_597), .B2(n_0_498), .ZN(n_0_299)); + OAI22_X1_LVT i_0_316 (.A1(n_0_728), .A2(n_0_299), .B1(op2[1]), .B2(n_0_354), + .ZN(n_0_298)); + OAI22_X1_LVT i_0_315 (.A1(op2[0]), .A2(n_0_334), .B1(n_0_701), .B2(n_0_298), + .ZN(n_0_297)); + OAI221_X1_LVT i_0_314 (.A(n_0_301), .B1(n_0_545), .B2(n_0_308), .C1(n_0_621), + .C2(n_0_297), .ZN(result[17])); + XNOR2_X1_LVT i_10_82 (.A(n_10_64), .B(n_10_65), .ZN(n_48)); + AOI22_X1_LVT i_0_301 (.A1(n_48), .A2(n_0_580), .B1(n_16), .B2(n_0_581), + .ZN(n_0_284)); + NAND2_X1_LVT i_0_333 (.A1(n_0_544), .A2(n_0_469), .ZN(n_0_315)); + INV_X1_LVT i_0_332 (.A(n_0_315), .ZN(n_0_314)); + OAI21_X1_LVT i_0_302 (.A(n_0_681), .B1(op2[16]), .B2(n_0_568), .ZN(n_0_285)); + AOI21_X1_LVT i_0_300 (.A(n_0_314), .B1(op1[16]), .B2(n_0_285), .ZN(n_0_283)); + INV_X1_LVT i_0_772 (.A(op1[16]), .ZN(n_0_739)); + OAI221_X1_LVT i_0_303 (.A(op2[16]), .B1(op1[16]), .B2(n_0_564), .C1(n_0_739), + .C2(n_0_567), .ZN(n_0_286)); + NAND3_X1_LVT i_0_299 (.A1(n_0_284), .A2(n_0_283), .A3(n_0_286), .ZN(n_0_282)); + INV_X1_LVT i_0_593 (.A(n_0_562), .ZN(n_0_561)); + OAI22_X1_LVT i_0_307 (.A1(op1[16]), .A2(op2[3]), .B1(op1[24]), .B2(n_0_723), + .ZN(n_0_290)); + NOR2_X1_LVT i_0_306 (.A1(op2[4]), .A2(n_0_290), .ZN(n_0_289)); + AOI22_X1_LVT i_0_305 (.A1(n_0_693), .A2(n_0_289), .B1(op2[2]), .B2(n_0_371), + .ZN(n_0_288)); + OAI22_X1_LVT i_0_304 (.A1(n_0_728), .A2(n_0_330), .B1(op2[1]), .B2(n_0_288), + .ZN(n_0_287)); + AOI221_X1_LVT i_0_298 (.A(n_0_282), .B1(n_0_547), .B2(n_0_310), .C1(n_0_561), + .C2(n_0_287), .ZN(n_0_281)); + INV_X1_LVT i_0_762 (.A(op1[1]), .ZN(n_0_729)); + OAI22_X1_LVT i_0_313 (.A1(n_0_722), .A2(n_0_615), .B1(n_0_729), .B2(n_0_617), + .ZN(n_0_296)); + NAND2_X1_LVT i_0_312 (.A1(op2[2]), .A2(n_0_296), .ZN(n_0_295)); + OAI21_X1_LVT i_0_311 (.A(n_0_295), .B1(op2[2]), .B2(n_0_362), .ZN(n_0_294)); + NAND2_X1_LVT i_0_310 (.A1(op2[1]), .A2(n_0_294), .ZN(n_0_293)); + OAI21_X1_LVT i_0_309 (.A(n_0_293), .B1(op2[1]), .B2(n_0_336), .ZN(n_0_292)); + OAI22_X1_LVT i_0_308 (.A1(op2[0]), .A2(n_0_298), .B1(n_0_701), .B2(n_0_292), + .ZN(n_0_291)); + OAI21_X1_LVT i_0_297 (.A(n_0_281), .B1(n_0_621), .B2(n_0_291), .ZN(result[16])); + OAI221_X1_LVT i_0_286 (.A(op2[15]), .B1(n_0_734), .B2(n_0_567), .C1(op1[15]), + .C2(n_0_564), .ZN(n_0_270)); + AOI21_X1_LVT i_0_288 (.A(n_0_314), .B1(n_15), .B2(n_0_581), .ZN(n_0_272)); + INV_X1_LVT i_0_287 (.A(n_0_272), .ZN(n_0_271)); + XNOR2_X1_LVT i_10_78 (.A(n_10_61), .B(n_10_62), .ZN(n_47)); + OAI21_X1_LVT i_0_285 (.A(n_0_681), .B1(op2[15]), .B2(n_0_568), .ZN(n_0_269)); + AOI221_X1_LVT i_0_284 (.A(n_0_271), .B1(n_47), .B2(n_0_580), .C1(op1[15]), + .C2(n_0_269), .ZN(n_0_268)); + AOI22_X1_LVT i_0_296 (.A1(op1[8]), .A2(n_0_616), .B1(op1[0]), .B2(n_0_618), + .ZN(n_0_280)); + AOI22_X1_LVT i_0_295 (.A1(op2[2]), .A2(n_0_280), .B1(n_0_693), .B2(n_0_356), + .ZN(n_0_279)); + NAND2_X1_LVT i_0_294 (.A1(op2[1]), .A2(n_0_279), .ZN(n_0_278)); + OAI21_X1_LVT i_0_293 (.A(n_0_278), .B1(op2[1]), .B2(n_0_299), .ZN(n_0_277)); + OAI221_X1_LVT i_0_292 (.A(n_0_620), .B1(n_0_701), .B2(n_0_277), .C1(op2[0]), + .C2(n_0_292), .ZN(n_0_276)); + OAI222_X1_LVT i_0_291 (.A1(n_0_719), .A2(n_0_617), .B1(n_0_691), .B2(n_0_605), + .C1(n_0_734), .C2(n_0_615), .ZN(n_0_275)); + OAI22_X1_LVT i_0_290 (.A1(n_0_693), .A2(n_0_349), .B1(op2[2]), .B2(n_0_275), + .ZN(n_0_274)); + OAI22_X1_LVT i_0_289 (.A1(op2[1]), .A2(n_0_274), .B1(n_0_728), .B2(n_0_311), + .ZN(n_0_273)); + AOI22_X1_LVT i_0_283 (.A1(n_0_561), .A2(n_0_273), .B1(n_0_547), .B2(n_0_287), + .ZN(n_0_267)); + NAND4_X1_LVT i_0_282 (.A1(n_0_270), .A2(n_0_268), .A3(n_0_276), .A4(n_0_267), + .ZN(result[15])); + NOR2_X1_LVT i_0_278 (.A1(op2[0]), .A2(n_0_277), .ZN(n_0_263)); + NAND2_X1_LVT i_0_281 (.A1(n_0_612), .A2(n_0_575), .ZN(n_0_266)); + OAI21_X1_LVT i_0_280 (.A(n_0_266), .B1(n_0_713), .B2(n_0_497), .ZN(n_0_265)); + AOI22_X1_LVT i_0_279 (.A1(op2[1]), .A2(n_0_265), .B1(n_0_728), .B2(n_0_294), + .ZN(n_0_264)); + AOI211_X1_LVT i_0_277 (.A(n_0_263), .B(n_0_621), .C1(op2[0]), .C2(n_0_264), + .ZN(n_0_262)); + INV_X1_LVT i_0_754 (.A(op1[14]), .ZN(n_0_721)); + OAI21_X1_LVT i_0_273 (.A(op2[14]), .B1(n_0_721), .B2(n_0_567), .ZN(n_0_258)); + AOI21_X1_LVT i_0_272 (.A(n_0_258), .B1(n_0_721), .B2(n_0_565), .ZN(n_0_257)); + XNOR2_X1_LVT i_10_74 (.A(n_10_58), .B(n_10_59), .ZN(n_46)); + OAI21_X1_LVT i_0_276 (.A(n_0_681), .B1(op2[14]), .B2(n_0_568), .ZN(n_0_261)); + AOI222_X1_LVT i_0_275 (.A1(n_14), .A2(n_0_581), .B1(n_46), .B2(n_0_580), + .C1(op1[14]), .C2(n_0_261), .ZN(n_0_260)); + INV_X1_LVT i_0_274 (.A(n_0_260), .ZN(n_0_259)); + OAI222_X1_LVT i_0_271 (.A1(n_0_717), .A2(n_0_605), .B1(n_0_687), .B2(n_0_617), + .C1(n_0_721), .C2(n_0_615), .ZN(n_0_256)); + OAI22_X1_LVT i_0_270 (.A1(n_0_693), .A2(n_0_331), .B1(op2[2]), .B2(n_0_256), + .ZN(n_0_255)); + AND2_X1_LVT i_0_269 (.A1(n_0_728), .A2(n_0_255), .ZN(n_0_254)); + NOR3_X1_LVT i_0_265 (.A1(op2[3]), .A2(op2[2]), .A3(op2[0]), .ZN(n_0_250)); + AOI21_X1_LVT i_0_268 (.A(n_0_254), .B1(op2[1]), .B2(n_0_288), .ZN(n_0_253)); + OAI22_X1_LVT i_0_266 (.A1(op2[0]), .A2(n_0_253), .B1(n_0_701), .B2(n_0_273), + .ZN(n_0_251)); + AOI221_X1_LVT i_0_259 (.A(n_0_579), .B1(n_0_254), .B2(n_0_250), .C1(n_0_315), + .C2(n_0_251), .ZN(n_0_244)); + OR4_X1_LVT i_0_258 (.A1(n_0_262), .A2(n_0_257), .A3(n_0_259), .A4(n_0_244), + .ZN(result[14])); + OAI221_X1_LVT i_0_245 (.A(op2[13]), .B1(op1[13]), .B2(n_0_564), .C1(n_0_714), + .C2(n_0_567), .ZN(n_0_231)); + NAND2_X1_LVT i_0_244 (.A1(n_13), .A2(n_0_581), .ZN(n_0_230)); + OAI211_X1_LVT i_0_243 (.A(n_0_231), .B(n_0_230), .C1(n_0_714), .C2(n_0_681), + .ZN(n_0_229)); + XNOR2_X1_LVT i_10_70 (.A(n_10_55), .B(n_10_56), .ZN(n_45)); + NOR2_X1_LVT i_0_695 (.A1(op2[13]), .A2(n_0_714), .ZN(n_0_662)); + AOI221_X1_LVT i_0_242 (.A(n_0_229), .B1(n_45), .B2(n_0_580), .C1(n_0_662), + .C2(n_0_569), .ZN(n_0_228)); + INV_X1_LVT i_0_267 (.A(n_0_253), .ZN(n_0_252)); + OAI222_X1_LVT i_0_257 (.A1(n_0_714), .A2(n_0_615), .B1(n_0_726), .B2(n_0_617), + .C1(n_0_710), .C2(n_0_605), .ZN(n_0_243)); + OAI22_X1_LVT i_0_256 (.A1(n_0_693), .A2(n_0_312), .B1(op2[2]), .B2(n_0_243), + .ZN(n_0_242)); + NAND2_X1_LVT i_0_255 (.A1(n_0_728), .A2(n_0_242), .ZN(n_0_241)); + NAND2_X1_LVT i_0_254 (.A1(op2[1]), .A2(n_0_274), .ZN(n_0_240)); + NAND2_X1_LVT i_0_241 (.A1(n_0_241), .A2(n_0_240), .ZN(n_0_227)); + OAI221_X1_LVT i_0_240 (.A(n_0_228), .B1(n_0_548), .B2(n_0_252), .C1(n_0_562), + .C2(n_0_227), .ZN(n_0_226)); + NAND2_X1_LVT i_0_249 (.A1(n_0_728), .A2(n_0_279), .ZN(n_0_235)); + AOI22_X1_LVT i_0_250 (.A1(n_0_597), .A2(n_0_575), .B1(op1[6]), .B2(n_0_496), + .ZN(n_0_236)); + OAI21_X1_LVT i_0_248 (.A(n_0_235), .B1(n_0_728), .B2(n_0_236), .ZN(n_0_234)); + INV_X1_LVT i_0_247 (.A(n_0_234), .ZN(n_0_233)); + AOI221_X1_LVT i_0_246 (.A(n_0_621), .B1(op2[0]), .B2(n_0_233), .C1(n_0_701), + .C2(n_0_264), .ZN(n_0_232)); + NAND2_X1_LVT i_0_264 (.A1(op2[3]), .A2(n_0_469), .ZN(n_0_249)); + AOI21_X1_LVT i_0_262 (.A(n_0_468), .B1(n_0_693), .B2(n_0_249), .ZN(n_0_247)); + INV_X1_LVT i_0_261 (.A(n_0_247), .ZN(n_0_246)); + OAI211_X1_LVT i_0_260 (.A(n_0_252), .B(n_0_246), .C1(n_0_468), .C2(n_0_254), + .ZN(n_0_245)); + OAI221_X1_LVT i_0_253 (.A(n_0_544), .B1(n_0_247), .B2(n_0_241), .C1(n_0_469), + .C2(n_0_240), .ZN(n_0_239)); + INV_X1_LVT i_0_252 (.A(n_0_239), .ZN(n_0_238)); + AOI211_X1_LVT i_0_239 (.A(n_0_226), .B(n_0_232), .C1(n_0_245), .C2(n_0_238), + .ZN(n_0_225)); + INV_X1_LVT i_0_238 (.A(n_0_225), .ZN(result[13])); + OAI221_X1_LVT i_0_232 (.A(op2[12]), .B1(n_0_696), .B2(n_0_567), .C1(op1[12]), + .C2(n_0_564), .ZN(n_0_219)); + OAI21_X1_LVT i_0_231 (.A(n_0_681), .B1(op2[12]), .B2(n_0_568), .ZN(n_0_218)); + XNOR2_X1_LVT i_10_66 (.A(n_10_52), .B(n_10_53), .ZN(n_44)); + AOI222_X1_LVT i_0_230 (.A1(n_12), .A2(n_0_581), .B1(op1[12]), .B2(n_0_218), + .C1(n_44), .C2(n_0_580), .ZN(n_0_217)); + OAI21_X1_LVT i_0_234 (.A(n_0_620), .B1(op2[1]), .B2(n_0_265), .ZN(n_0_221)); + INV_X1_LVT i_0_763 (.A(op1[5]), .ZN(n_0_730)); + OAI21_X1_LVT i_0_236 (.A(op2[2]), .B1(n_0_730), .B2(n_0_615), .ZN(n_0_223)); + OAI21_X1_LVT i_0_235 (.A(n_0_223), .B1(op2[2]), .B2(n_0_296), .ZN(n_0_222)); + AOI21_X1_LVT i_0_233 (.A(n_0_221), .B1(op2[1]), .B2(n_0_222), .ZN(n_0_220)); + NOR2_X1_LVT i_0_237 (.A1(n_0_577), .A2(n_0_227), .ZN(n_0_224)); + NOR4_X1_LVT i_0_223 (.A1(n_0_701), .A2(n_0_220), .A3(n_0_224), .A4(n_0_238), + .ZN(n_0_210)); + NAND2_X1_LVT i_0_224 (.A1(n_0_544), .A2(n_0_247), .ZN(n_0_211)); + NAND2_X1_LVT i_0_222 (.A1(n_0_701), .A2(n_0_211), .ZN(n_0_209)); + OAI22_X1_LVT i_0_229 (.A1(op2[4]), .A2(n_0_696), .B1(n_0_738), .B2(n_0_698), + .ZN(n_0_216)); + INV_X1_LVT i_0_228 (.A(n_0_216), .ZN(n_0_215)); + OAI22_X1_LVT i_0_227 (.A1(n_0_727), .A2(n_0_617), .B1(op2[3]), .B2(n_0_215), + .ZN(n_0_214)); + OAI22_X1_LVT i_0_226 (.A1(n_0_693), .A2(n_0_289), .B1(op2[2]), .B2(n_0_214), + .ZN(n_0_213)); + OAI22_X1_LVT i_0_225 (.A1(op2[1]), .A2(n_0_213), .B1(n_0_728), .B2(n_0_255), + .ZN(n_0_212)); + AOI221_X1_LVT i_0_221 (.A(n_0_209), .B1(n_0_578), .B2(n_0_212), .C1(n_0_620), + .C2(n_0_234), .ZN(n_0_208)); + OAI211_X1_LVT i_0_220 (.A(n_0_219), .B(n_0_217), .C1(n_0_210), .C2(n_0_208), + .ZN(result[12])); + OAI21_X1_LVT i_0_209 (.A(n_0_681), .B1(op2[11]), .B2(n_0_568), .ZN(n_0_197)); + AOI22_X1_LVT i_0_208 (.A1(n_11), .A2(n_0_581), .B1(op1[11]), .B2(n_0_197), + .ZN(n_0_196)); + NAND2_X1_LVT i_0_207 (.A1(n_0_211), .A2(n_0_196), .ZN(n_0_195)); + AOI22_X1_LVT i_0_210 (.A1(op1[11]), .A2(n_0_566), .B1(n_0_706), .B2(n_0_565), + .ZN(n_0_198)); + XNOR2_X1_LVT i_10_62 (.A(n_10_49), .B(n_10_50), .ZN(n_43)); + AOI221_X1_LVT i_0_206 (.A(n_0_195), .B1(op2[11]), .B2(n_0_198), .C1(n_43), + .C2(n_0_580), .ZN(n_0_194)); + AOI221_X1_LVT i_0_215 (.A(op2[3]), .B1(n_0_738), .B2(n_0_706), .C1(op2[4]), + .C2(n_0_688), .ZN(n_0_203)); + AOI21_X1_LVT i_0_214 (.A(n_0_203), .B1(op1[19]), .B2(n_0_618), .ZN(n_0_202)); + NAND2_X1_LVT i_0_213 (.A1(n_0_693), .A2(n_0_202), .ZN(n_0_201)); + OAI21_X1_LVT i_0_212 (.A(n_0_201), .B1(n_0_693), .B2(n_0_275), .ZN(n_0_200)); + OAI22_X1_LVT i_0_211 (.A1(n_0_728), .A2(n_0_242), .B1(op2[1]), .B2(n_0_200), + .ZN(n_0_199)); + AOI22_X1_LVT i_0_205 (.A1(n_0_561), .A2(n_0_199), .B1(n_0_701), .B2(n_0_220), + .ZN(n_0_193)); + NOR2_X1_LVT i_0_219 (.A1(op2[2]), .A2(n_0_280), .ZN(n_0_207)); + AOI21_X1_LVT i_0_218 (.A(n_0_207), .B1(op1[4]), .B2(n_0_496), .ZN(n_0_206)); + AOI22_X1_LVT i_0_217 (.A1(n_0_728), .A2(n_0_236), .B1(op2[1]), .B2(n_0_206), + .ZN(n_0_205)); + AOI22_X1_LVT i_0_216 (.A1(n_0_578), .A2(n_0_212), .B1(n_0_620), .B2(n_0_205), + .ZN(n_0_204)); + OAI211_X1_LVT i_0_204 (.A(n_0_194), .B(n_0_193), .C1(n_0_701), .C2(n_0_204), + .ZN(result[11])); + AOI22_X1_LVT i_0_194 (.A1(n_0_654), .A2(n_0_498), .B1(op1[7]), .B2(n_0_573), + .ZN(n_0_183)); + OAI22_X1_LVT i_0_193 (.A1(n_0_728), .A2(n_0_183), .B1(op2[1]), .B2(n_0_222), + .ZN(n_0_182)); + AOI22_X1_LVT i_0_192 (.A1(op2[0]), .A2(n_0_182), .B1(n_0_701), .B2(n_0_205), + .ZN(n_0_181)); + NOR2_X1_LVT i_0_191 (.A1(n_0_621), .A2(n_0_181), .ZN(n_0_180)); + AOI22_X1_LVT i_0_190 (.A1(op1[10]), .A2(n_0_566), .B1(n_0_733), .B2(n_0_565), + .ZN(n_0_179)); + XNOR2_X1_LVT i_10_58 (.A(n_10_46), .B(n_10_47), .ZN(n_42)); + AOI22_X1_LVT i_0_188 (.A1(op2[10]), .A2(n_0_179), .B1(n_42), .B2(n_0_580), + .ZN(n_0_177)); + OAI21_X1_LVT i_0_189 (.A(n_0_681), .B1(op2[10]), .B2(n_0_568), .ZN(n_0_178)); + AOI22_X1_LVT i_0_187 (.A1(n_10), .A2(n_0_581), .B1(op1[10]), .B2(n_0_178), + .ZN(n_0_176)); + NAND2_X1_LVT i_0_186 (.A1(n_0_177), .A2(n_0_176), .ZN(n_0_175)); + NOR2_X1_LVT i_0_203 (.A1(n_0_701), .A2(n_0_199), .ZN(n_0_192)); + NOR2_X1_LVT i_0_200 (.A1(n_0_693), .A2(n_0_256), .ZN(n_0_189)); + AOI221_X1_LVT i_0_202 (.A(n_0_596), .B1(op1[10]), .B2(n_0_616), .C1(op1[26]), + .C2(n_0_606), .ZN(n_0_191)); + AOI21_X1_LVT i_0_199 (.A(n_0_189), .B1(n_0_693), .B2(n_0_191), .ZN(n_0_188)); + OR2_X1_LVT i_0_198 (.A1(op2[1]), .A2(n_0_188), .ZN(n_0_187)); + NAND2_X1_LVT i_0_197 (.A1(op2[1]), .A2(n_0_213), .ZN(n_0_186)); + NAND2_X1_LVT i_0_185 (.A1(n_0_187), .A2(n_0_186), .ZN(n_0_174)); + AOI211_X1_LVT i_0_184 (.A(n_0_577), .B(n_0_192), .C1(n_0_701), .C2(n_0_174), + .ZN(n_0_173)); + INV_X1_LVT i_0_263 (.A(n_0_249), .ZN(n_0_248)); + OAI22_X1_LVT i_0_196 (.A1(n_0_248), .A2(n_0_187), .B1(n_0_247), .B2(n_0_186), + .ZN(n_0_185)); + AOI221_X1_LVT i_0_195 (.A(n_0_545), .B1(n_0_246), .B2(n_0_192), .C1(n_0_701), + .C2(n_0_185), .ZN(n_0_184)); + OR4_X1_LVT i_0_183 (.A1(n_0_180), .A2(n_0_175), .A3(n_0_173), .A4(n_0_184), + .ZN(result[10])); + INV_X1_LVT i_0_753 (.A(op2[9]), .ZN(n_0_720)); + AOI221_X1_LVT i_0_171 (.A(n_0_720), .B1(op1[9]), .B2(n_0_566), .C1(n_0_722), + .C2(n_0_565), .ZN(n_0_161)); + XNOR2_X1_LVT i_10_54 (.A(n_10_43), .B(n_10_44), .ZN(n_41)); + AOI22_X1_LVT i_0_172 (.A1(n_9), .A2(n_0_581), .B1(n_41), .B2(n_0_580), + .ZN(n_0_162)); + AOI21_X1_LVT i_0_170 (.A(aluBypass), .B1(n_0_720), .B2(n_0_569), .ZN(n_0_160)); + OAI21_X1_LVT i_0_169 (.A(n_0_162), .B1(n_0_722), .B2(n_0_160), .ZN(n_0_159)); + OAI222_X1_LVT i_0_182 (.A1(n_0_722), .A2(n_0_615), .B1(n_0_699), .B2(n_0_605), + .C1(n_0_732), .C2(n_0_617), .ZN(n_0_172)); + AOI22_X1_LVT i_0_181 (.A1(n_0_693), .A2(n_0_172), .B1(op2[2]), .B2(n_0_243), + .ZN(n_0_171)); + NAND2_X1_LVT i_0_180 (.A1(n_0_728), .A2(n_0_171), .ZN(n_0_170)); + NAND2_X1_LVT i_0_179 (.A1(op2[1]), .A2(n_0_200), .ZN(n_0_169)); + OAI22_X1_LVT i_0_178 (.A1(n_0_248), .A2(n_0_170), .B1(n_0_247), .B2(n_0_169), + .ZN(n_0_168)); + NOR3_X1_LVT i_0_177 (.A1(n_0_545), .A2(n_0_168), .A3(n_0_185), .ZN(n_0_167)); + NOR2_X1_LVT i_0_251 (.A1(n_0_704), .A2(n_0_615), .ZN(n_0_237)); + OAI22_X1_LVT i_0_176 (.A1(op1[2]), .A2(n_0_693), .B1(n_0_496), .B2(n_0_237), + .ZN(n_0_166)); + OAI22_X1_LVT i_0_175 (.A1(op2[1]), .A2(n_0_206), .B1(n_0_728), .B2(n_0_166), + .ZN(n_0_165)); + OAI221_X1_LVT i_0_174 (.A(n_0_620), .B1(op2[0]), .B2(n_0_182), .C1(n_0_701), + .C2(n_0_165), .ZN(n_0_164)); + NAND2_X1_LVT i_0_173 (.A1(n_0_170), .A2(n_0_169), .ZN(n_0_163)); + OAI221_X1_LVT i_0_168 (.A(n_0_164), .B1(n_0_562), .B2(n_0_163), .C1(n_0_548), + .C2(n_0_174), .ZN(n_0_158)); + OR4_X1_LVT i_0_167 (.A1(n_0_161), .A2(n_0_159), .A3(n_0_167), .A4(n_0_158), + .ZN(result[9])); + OAI21_X1_LVT i_0_160 (.A(n_0_693), .B1(n_0_730), .B2(n_0_615), .ZN(n_0_151)); + OAI21_X1_LVT i_0_159 (.A(op2[2]), .B1(n_0_729), .B2(n_0_615), .ZN(n_0_150)); + AND2_X1_LVT i_0_158 (.A1(n_0_151), .A2(n_0_150), .ZN(n_0_149)); + NAND2_X1_LVT i_0_157 (.A1(op2[1]), .A2(n_0_149), .ZN(n_0_148)); + OAI21_X1_LVT i_0_156 (.A(n_0_148), .B1(op2[1]), .B2(n_0_183), .ZN(n_0_147)); + OAI22_X1_LVT i_0_155 (.A1(op2[0]), .A2(n_0_165), .B1(n_0_701), .B2(n_0_147), + .ZN(n_0_146)); + NOR2_X1_LVT i_0_154 (.A1(n_0_621), .A2(n_0_146), .ZN(n_0_145)); + INV_X1_LVT i_0_773 (.A(op1[8]), .ZN(n_0_740)); + NOR2_X1_LVT i_0_688 (.A1(n_0_740), .A2(op2[8]), .ZN(n_0_655)); + AOI22_X1_LVT i_0_153 (.A1(op1[8]), .A2(aluBypass), .B1(n_0_655), .B2(n_0_569), + .ZN(n_0_144)); + OAI221_X1_LVT i_0_152 (.A(op2[8]), .B1(op1[8]), .B2(n_0_564), .C1(n_0_740), + .C2(n_0_567), .ZN(n_0_143)); + XNOR2_X1_LVT i_10_51 (.A(n_10_39), .B(n_10_42), .ZN(n_40)); + AOI22_X1_LVT i_0_151 (.A1(n_40), .A2(n_0_580), .B1(n_8), .B2(n_0_581), + .ZN(n_0_142)); + NAND3_X1_LVT i_0_150 (.A1(n_0_144), .A2(n_0_143), .A3(n_0_142), .ZN(n_0_141)); + OAI222_X1_LVT i_0_166 (.A1(n_0_740), .A2(n_0_615), .B1(n_0_739), .B2(n_0_617), + .C1(n_0_736), .C2(n_0_605), .ZN(n_0_157)); + OAI22_X1_LVT i_0_165 (.A1(op2[2]), .A2(n_0_157), .B1(n_0_693), .B2(n_0_214), + .ZN(n_0_156)); + NOR2_X1_LVT i_0_164 (.A1(op2[1]), .A2(n_0_156), .ZN(n_0_155)); + AOI21_X1_LVT i_0_163 (.A(n_0_155), .B1(op2[1]), .B2(n_0_188), .ZN(n_0_154)); + AND2_X1_LVT i_0_162 (.A1(n_0_701), .A2(n_0_154), .ZN(n_0_153)); + AOI211_X1_LVT i_0_149 (.A(n_0_577), .B(n_0_153), .C1(op2[0]), .C2(n_0_163), + .ZN(n_0_140)); + AOI221_X1_LVT i_0_161 (.A(n_0_545), .B1(op2[0]), .B2(n_0_168), .C1(n_0_249), + .C2(n_0_153), .ZN(n_0_152)); + OR4_X1_LVT i_0_148 (.A1(n_0_145), .A2(n_0_141), .A3(n_0_140), .A4(n_0_152), + .ZN(result[8])); + AOI22_X1_LVT i_0_138 (.A1(op1[4]), .A2(n_0_573), .B1(op1[0]), .B2(n_0_496), + .ZN(n_0_130)); + AOI22_X1_LVT i_0_137 (.A1(op2[1]), .A2(n_0_130), .B1(n_0_728), .B2(n_0_166), + .ZN(n_0_129)); + OAI22_X1_LVT i_0_136 (.A1(n_0_701), .A2(n_0_129), .B1(op2[0]), .B2(n_0_147), + .ZN(n_0_128)); + NOR2_X1_LVT i_0_135 (.A1(n_0_621), .A2(n_0_128), .ZN(n_0_127)); + OAI221_X1_LVT i_0_139 (.A(op2[7]), .B1(n_0_713), .B2(n_0_567), .C1(op1[7]), + .C2(n_0_564), .ZN(n_0_131)); + INV_X1_LVT i_10_44 (.A(n_10_36), .ZN(n_10_37)); + NOR2_X1_LVT i_10_45 (.A1(n_10_35), .A2(n_10_37), .ZN(n_10_38)); + XNOR2_X1_LVT i_10_46 (.A(n_10_33), .B(n_10_38), .ZN(n_39)); + AOI22_X1_LVT i_0_141 (.A1(n_7), .A2(n_0_581), .B1(n_39), .B2(n_0_580), + .ZN(n_0_133)); + INV_X1_LVT i_0_745 (.A(op2[7]), .ZN(n_0_712)); + AOI21_X1_LVT i_0_140 (.A(aluBypass), .B1(n_0_712), .B2(n_0_569), .ZN(n_0_132)); + OAI211_X1_LVT i_0_133 (.A(n_0_131), .B(n_0_133), .C1(n_0_713), .C2(n_0_132), + .ZN(n_0_125)); + OAI22_X1_LVT i_0_147 (.A1(n_0_734), .A2(n_0_617), .B1(n_0_713), .B2(n_0_615), + .ZN(n_0_139)); + AOI211_X1_LVT i_0_146 (.A(n_0_139), .B(n_0_248), .C1(op1[23]), .C2(n_0_606), + .ZN(n_0_138)); + OAI22_X1_LVT i_0_145 (.A1(n_0_693), .A2(n_0_202), .B1(op2[2]), .B2(n_0_138), + .ZN(n_0_137)); + NOR2_X1_LVT i_0_144 (.A1(op2[1]), .A2(n_0_137), .ZN(n_0_136)); + AOI21_X1_LVT i_0_143 (.A(n_0_136), .B1(op2[1]), .B2(n_0_171), .ZN(n_0_135)); + NAND2_X1_LVT i_0_142 (.A1(n_0_561), .A2(n_0_135), .ZN(n_0_134)); + OAI221_X1_LVT i_0_134 (.A(n_0_134), .B1(n_0_548), .B2(n_0_154), .C1(n_0_545), + .C2(n_0_249), .ZN(n_0_126)); + OR3_X1_LVT i_0_132 (.A1(n_0_127), .A2(n_0_125), .A3(n_0_126), .ZN(result[7])); + NAND2_X1_LVT i_0_124 (.A1(n_0_728), .A2(n_0_149), .ZN(n_0_117)); + OAI21_X1_LVT i_0_123 (.A(n_0_117), .B1(n_0_724), .B2(n_0_531), .ZN(n_0_116)); + OAI22_X1_LVT i_0_122 (.A1(n_0_701), .A2(n_0_116), .B1(op2[0]), .B2(n_0_129), + .ZN(n_0_115)); + NOR2_X1_LVT i_0_121 (.A1(n_0_621), .A2(n_0_115), .ZN(n_0_114)); + XNOR2_X1_LVT i_10_38 (.A(n_10_30), .B(n_10_31), .ZN(n_38)); + AOI22_X1_LVT i_0_119 (.A1(n_6), .A2(n_0_581), .B1(n_38), .B2(n_0_580), + .ZN(n_0_112)); + INV_X1_LVT i_0_735 (.A(op2[6]), .ZN(n_0_702)); + AOI21_X1_LVT i_0_120 (.A(aluBypass), .B1(n_0_702), .B2(n_0_569), .ZN(n_0_113)); + OAI21_X1_LVT i_0_118 (.A(n_0_112), .B1(n_0_704), .B2(n_0_113), .ZN(n_0_111)); + AOI221_X1_LVT i_0_117 (.A(n_0_702), .B1(n_0_704), .B2(n_0_565), .C1(op1[6]), + .C2(n_0_566), .ZN(n_0_110)); + NOR3_X1_LVT i_0_116 (.A1(n_0_114), .A2(n_0_111), .A3(n_0_110), .ZN(n_0_109)); + AOI221_X1_LVT i_0_131 (.A(n_0_237), .B1(op1[14]), .B2(n_0_618), .C1(op2[4]), + .C2(n_0_406), .ZN(n_0_124)); + NAND2_X1_LVT i_0_130 (.A1(n_0_693), .A2(n_0_124), .ZN(n_0_123)); + INV_X1_LVT i_0_201 (.A(n_0_191), .ZN(n_0_190)); + OAI21_X1_LVT i_0_129 (.A(n_0_123), .B1(n_0_693), .B2(n_0_190), .ZN(n_0_122)); + AOI22_X1_LVT i_0_128 (.A1(n_0_728), .A2(n_0_122), .B1(op2[1]), .B2(n_0_156), + .ZN(n_0_121)); + INV_X1_LVT i_0_127 (.A(n_0_121), .ZN(n_0_120)); + OAI21_X1_LVT i_0_126 (.A(n_0_248), .B1(op2[1]), .B2(n_0_123), .ZN(n_0_119)); + AND2_X1_LVT i_0_125 (.A1(n_0_120), .A2(n_0_119), .ZN(n_0_118)); + NOR2_X1_LVT i_0_115 (.A1(n_0_545), .A2(n_0_118), .ZN(n_0_108)); + AOI21_X1_LVT i_0_114 (.A(n_0_108), .B1(n_0_576), .B2(n_0_121), .ZN(n_0_107)); + AOI22_X1_LVT i_0_113 (.A1(n_0_544), .A2(n_0_248), .B1(n_0_578), .B2(n_0_135), + .ZN(n_0_106)); + OAI221_X1_LVT i_0_112 (.A(n_0_109), .B1(op2[0]), .B2(n_0_107), .C1(n_0_701), + .C2(n_0_106), .ZN(result[6])); + OAI221_X1_LVT i_0_100 (.A(op2[5]), .B1(op1[5]), .B2(n_0_564), .C1(n_0_730), + .C2(n_0_567), .ZN(n_0_94)); + INV_X1_LVT i_0_764 (.A(op2[5]), .ZN(n_0_731)); + AOI21_X1_LVT i_0_99 (.A(aluBypass), .B1(n_0_731), .B2(n_0_569), .ZN(n_0_93)); + NOR2_X1_LVT i_0_98 (.A1(n_0_730), .A2(n_0_93), .ZN(n_0_92)); + XNOR2_X1_LVT i_10_35 (.A(n_10_26), .B(n_10_29), .ZN(n_37)); + AOI221_X1_LVT i_0_97 (.A(n_0_92), .B1(n_37), .B2(n_0_580), .C1(n_5), .C2( + n_0_581), .ZN(n_0_91)); + OAI22_X1_LVT i_0_102 (.A1(n_0_694), .A2(n_0_531), .B1(op2[1]), .B2(n_0_130), + .ZN(n_0_96)); + OAI221_X1_LVT i_0_101 (.A(n_0_620), .B1(n_0_701), .B2(n_0_96), .C1(op2[0]), + .C2(n_0_116), .ZN(n_0_95)); + NAND3_X1_LVT i_0_111 (.A1(n_0_544), .A2(n_0_248), .A3(op2[2]), .ZN(n_0_105)); + NAND2_X1_LVT i_0_110 (.A1(op2[4]), .A2(n_0_386), .ZN(n_0_104)); + OAI21_X1_LVT i_0_109 (.A(n_0_104), .B1(n_0_714), .B2(n_0_617), .ZN(n_0_103)); + OAI22_X1_LVT i_0_108 (.A1(n_0_151), .A2(n_0_103), .B1(n_0_693), .B2(n_0_172), + .ZN(n_0_102)); + NOR2_X1_LVT i_0_107 (.A1(op2[1]), .A2(n_0_102), .ZN(n_0_101)); + AOI21_X1_LVT i_0_106 (.A(n_0_101), .B1(op2[1]), .B2(n_0_137), .ZN(n_0_100)); + OAI21_X1_LVT i_0_105 (.A(n_0_105), .B1(n_0_579), .B2(n_0_100), .ZN(n_0_99)); + AOI21_X1_LVT i_0_104 (.A(n_0_118), .B1(n_0_682), .B2(n_0_120), .ZN(n_0_98)); + OAI22_X1_LVT i_0_103 (.A1(n_0_547), .A2(n_0_99), .B1(n_0_701), .B2(n_0_98), + .ZN(n_0_97)); + NAND4_X1_LVT i_0_96 (.A1(n_0_94), .A2(n_0_91), .A3(n_0_95), .A4(n_0_97), + .ZN(result[5])); + INV_X1_LVT i_10_26 (.A(n_10_21), .ZN(n_10_22)); + NOR2_X1_LVT i_10_28 (.A1(n_10_22), .A2(n_10_23), .ZN(n_10_24)); + XNOR2_X1_LVT i_10_29 (.A(n_10_19), .B(n_10_24), .ZN(n_36)); + AOI222_X1_LVT i_0_89 (.A1(n_4), .A2(n_0_581), .B1(n_36), .B2(n_0_580), + .C1(n_0_668), .C2(n_0_564), .ZN(n_0_84)); + INV_X1_LVT i_0_770 (.A(op1[4]), .ZN(n_0_737)); + AOI221_X1_LVT i_0_90 (.A(aluBypass), .B1(op2[4]), .B2(n_0_567), .C1(n_0_738), + .C2(n_0_569), .ZN(n_0_85)); + OAI21_X1_LVT i_0_88 (.A(n_0_84), .B1(n_0_737), .B2(n_0_85), .ZN(n_0_83)); + NOR2_X1_LVT i_0_689 (.A1(op2[4]), .A2(n_0_737), .ZN(n_0_656)); + AOI21_X1_LVT i_0_95 (.A(n_0_616), .B1(n_0_727), .B2(n_0_723), .ZN(n_0_90)); + OAI22_X1_LVT i_0_94 (.A1(n_0_723), .A2(n_0_216), .B1(n_0_656), .B2(n_0_90), + .ZN(n_0_89)); + INV_X1_LVT i_0_93 (.A(n_0_89), .ZN(n_0_88)); + OAI22_X1_LVT i_0_92 (.A1(op2[2]), .A2(n_0_88), .B1(n_0_693), .B2(n_0_157), + .ZN(n_0_87)); + OAI221_X1_LVT i_0_91 (.A(n_0_105), .B1(n_0_728), .B2(n_0_122), .C1(op2[1]), + .C2(n_0_87), .ZN(n_0_86)); + AOI221_X1_LVT i_0_85 (.A(n_0_83), .B1(n_0_561), .B2(n_0_86), .C1(op2[0]), + .C2(n_0_99), .ZN(n_0_80)); + AOI221_X1_LVT i_0_87 (.A(n_0_574), .B1(n_0_729), .B2(op2[1]), .C1(n_0_728), + .C2(n_0_724), .ZN(n_0_82)); + OAI22_X1_LVT i_0_86 (.A1(op2[0]), .A2(n_0_96), .B1(n_0_701), .B2(n_0_82), + .ZN(n_0_81)); + OAI21_X1_LVT i_0_84 (.A(n_0_80), .B1(n_0_621), .B2(n_0_81), .ZN(result[4])); + AND2_X1_LVT i_0_81 (.A1(op2[1]), .A2(n_0_105), .ZN(n_0_77)); + NAND2_X1_LVT i_0_80 (.A1(n_0_102), .A2(n_0_77), .ZN(n_0_76)); + OAI221_X1_LVT i_0_83 (.A(n_0_693), .B1(n_0_654), .B2(n_0_484), .C1(n_0_738), + .C2(n_0_350), .ZN(n_0_79)); + OAI21_X1_LVT i_0_82 (.A(n_0_79), .B1(n_0_693), .B2(n_0_138), .ZN(n_0_78)); + OAI21_X1_LVT i_0_79 (.A(n_0_76), .B1(op2[1]), .B2(n_0_78), .ZN(n_0_75)); + NOR2_X1_LVT i_0_78 (.A1(n_0_562), .A2(n_0_75), .ZN(n_0_74)); + NAND2_X1_LVT i_10_20 (.A1(n_10_15), .A2(n_10_16), .ZN(n_10_17)); + XNOR2_X1_LVT i_10_21 (.A(n_10_13), .B(n_10_17), .ZN(n_35)); + AOI22_X1_LVT i_0_75 (.A1(n_35), .A2(n_0_580), .B1(n_3), .B2(n_0_581), + .ZN(n_0_71)); + OAI21_X1_LVT i_0_74 (.A(n_0_681), .B1(n_0_723), .B2(n_0_566), .ZN(n_0_70)); + AOI222_X1_LVT i_0_73 (.A1(n_0_654), .A2(n_0_569), .B1(n_0_663), .B2(n_0_564), + .C1(op1[3]), .C2(n_0_70), .ZN(n_0_69)); + INV_X1_LVT i_0_736 (.A(op1[0]), .ZN(n_0_703)); + OAI22_X1_LVT i_0_77 (.A1(n_0_703), .A2(n_0_531), .B1(n_0_694), .B2(n_0_572), + .ZN(n_0_73)); + OAI22_X1_LVT i_0_76 (.A1(n_0_701), .A2(n_0_73), .B1(op2[0]), .B2(n_0_82), + .ZN(n_0_72)); + OAI211_X1_LVT i_0_72 (.A(n_0_71), .B(n_0_69), .C1(n_0_621), .C2(n_0_72), + .ZN(n_0_68)); + AOI211_X1_LVT i_0_71 (.A(n_0_74), .B(n_0_68), .C1(n_0_547), .C2(n_0_86), + .ZN(n_0_67)); + INV_X1_LVT i_0_70 (.A(n_0_67), .ZN(result[3])); + NAND2_X1_LVT i_0_65 (.A1(n_2), .A2(n_0_581), .ZN(n_0_62)); + OAI221_X1_LVT i_0_66 (.A(op2[2]), .B1(op1[2]), .B2(n_0_564), .C1(n_0_694), + .C2(n_0_567), .ZN(n_0_63)); + AOI21_X1_LVT i_0_64 (.A(aluBypass), .B1(n_0_693), .B2(n_0_569), .ZN(n_0_61)); + OAI21_X1_LVT i_0_63 (.A(n_0_63), .B1(n_0_694), .B2(n_0_61), .ZN(n_0_60)); + INV_X1_LVT i_10_13 (.A(n_10_10), .ZN(n_10_11)); + NOR2_X1_LVT i_10_14 (.A1(n_10_9), .A2(n_10_11), .ZN(n_10_12)); + XNOR2_X1_LVT i_10_15 (.A(n_10_7), .B(n_10_12), .ZN(n_34)); + AOI21_X1_LVT i_0_62 (.A(n_0_60), .B1(n_34), .B2(n_0_580), .ZN(n_0_59)); + OAI211_X1_LVT i_0_57 (.A(n_0_62), .B(n_0_59), .C1(n_0_548), .C2(n_0_75), + .ZN(n_0_54)); + NOR2_X1_LVT i_0_698 (.A1(n_0_729), .A2(op2[1]), .ZN(n_0_665)); + INV_X1_LVT i_0_697 (.A(n_0_665), .ZN(n_0_664)); + OAI21_X1_LVT i_0_69 (.A(op2[0]), .B1(n_0_664), .B2(n_0_574), .ZN(n_0_66)); + OAI21_X1_LVT i_0_68 (.A(n_0_620), .B1(op2[0]), .B2(n_0_73), .ZN(n_0_65)); + INV_X1_LVT i_0_67 (.A(n_0_65), .ZN(n_0_64)); + OAI222_X1_LVT i_0_61 (.A1(op1[10]), .A2(n_0_617), .B1(op1[2]), .B2(n_0_615), + .C1(n_0_738), .C2(n_0_332), .ZN(n_0_58)); + OAI22_X1_LVT i_0_60 (.A1(op2[2]), .A2(n_0_58), .B1(n_0_693), .B2(n_0_124), + .ZN(n_0_57)); + INV_X1_LVT i_0_59 (.A(n_0_57), .ZN(n_0_56)); + AOI22_X1_LVT i_0_58 (.A1(n_0_728), .A2(n_0_56), .B1(n_0_87), .B2(n_0_77), + .ZN(n_0_55)); + AOI221_X1_LVT i_0_56 (.A(n_0_54), .B1(n_0_66), .B2(n_0_64), .C1(n_0_561), + .C2(n_0_55), .ZN(n_0_53)); + INV_X1_LVT i_0_55 (.A(n_0_53), .ZN(result[2])); + NAND2_X1_LVT i_0_54 (.A1(n_0_547), .A2(n_0_55), .ZN(n_0_52)); + AOI221_X1_LVT i_0_47 (.A(n_0_728), .B1(n_0_729), .B2(n_0_565), .C1(op1[1]), + .C2(n_0_566), .ZN(n_0_45)); + NOR2_X1_LVT i_0_700 (.A1(op1[0]), .A2(n_0_701), .ZN(n_0_667)); + AOI211_X1_LVT i_0_48 (.A(n_0_667), .B(n_0_621), .C1(n_0_729), .C2(n_0_701), + .ZN(n_0_46)); + AOI221_X1_LVT i_0_44 (.A(n_0_45), .B1(op1[1]), .B2(aluBypass), .C1(n_0_571), + .C2(n_0_46), .ZN(n_0_42)); + NAND2_X1_LVT i_10_6 (.A1(n_10_3), .A2(n_10_4), .ZN(n_10_5)); + XNOR2_X1_LVT i_10_7 (.A(n_10_5), .B(n_10_1), .ZN(n_33)); + AOI22_X1_LVT i_0_49 (.A1(n_33), .A2(n_0_580), .B1(n_1), .B2(n_0_581), + .ZN(n_0_47)); + OAI21_X1_LVT i_0_46 (.A(n_0_47), .B1(n_0_664), .B2(n_0_568), .ZN(n_0_44)); + NAND2_X1_LVT i_0_51 (.A1(op2[1]), .A2(n_0_78), .ZN(n_0_49)); + OAI222_X1_LVT i_0_53 (.A1(n_0_722), .A2(n_0_617), .B1(n_0_729), .B2(n_0_615), + .C1(n_0_738), .C2(n_0_313), .ZN(n_0_51)); + OAI22_X1_LVT i_0_52 (.A1(n_0_223), .A2(n_0_103), .B1(op2[2]), .B2(n_0_51), + .ZN(n_0_50)); + OAI21_X1_LVT i_0_50 (.A(n_0_49), .B1(op2[1]), .B2(n_0_50), .ZN(n_0_48)); + AOI21_X1_LVT i_0_45 (.A(n_0_44), .B1(n_0_561), .B2(n_0_48), .ZN(n_0_43)); + NAND3_X1_LVT i_0_43 (.A1(n_0_52), .A2(n_0_42), .A3(n_0_43), .ZN(result[1])); + OAI222_X1_LVT i_0_11 (.A1(n_0_740), .A2(n_0_617), .B1(n_0_703), .B2(n_0_615), + .C1(n_0_738), .C2(n_0_290), .ZN(n_0_10)); + OAI22_X1_LVT i_0_10 (.A1(op2[2]), .A2(n_0_10), .B1(n_0_693), .B2(n_0_88), + .ZN(n_0_9)); + OAI221_X1_LVT i_0_9 (.A(n_0_701), .B1(n_0_728), .B2(n_0_56), .C1(op2[1]), + .C2(n_0_9), .ZN(n_0_8)); + OAI21_X1_LVT i_0_8 (.A(n_0_8), .B1(n_0_701), .B2(n_0_48), .ZN(n_0_7)); + NOR2_X1_LVT i_0_7 (.A1(n_0_579), .A2(n_0_7), .ZN(n_0_6)); + OAI221_X1_LVT i_0_3 (.A(op2[0]), .B1(op1[0]), .B2(n_0_564), .C1(n_0_703), + .C2(n_0_567), .ZN(n_0_2)); + OAI21_X1_LVT i_10_2 (.A(n_10_1), .B1(n_10_0), .B2(op2[0]), .ZN(n_32)); + AOI22_X1_LVT i_0_2 (.A1(n_32), .A2(n_0_580), .B1(n_0), .B2(n_0_581), .ZN( + n_0_1)); + NAND3_X1_LVT i_0_6 (.A1(n_0_701), .A2(n_0_571), .A3(n_0_620), .ZN(n_0_5)); + OAI211_X1_LVT i_0_5 (.A(n_0_681), .B(n_0_5), .C1(op2[0]), .C2(n_0_568), + .ZN(n_0_4)); + NAND2_X1_LVT i_0_4 (.A1(op1[0]), .A2(n_0_4), .ZN(n_0_3)); + NAND3_X1_LVT i_0_1 (.A1(n_0_2), .A2(n_0_1), .A3(n_0_3), .ZN(n_0_0)); + OAI33_X1_LVT i_0_14 (.A1(n_0_692), .A2(op1[31]), .A3(n_0_683), .B1(op2[31]), + .B2(n_0_691), .B3(aluOp[0]), .ZN(n_0_13)); + INV_X1_LVT i_0_741 (.A(op2[29]), .ZN(n_0_708)); + NAND2_X1_LVT i_0_685 (.A1(op1[29]), .A2(n_0_708), .ZN(n_0_652)); + OAI22_X1_LVT i_0_713 (.A1(n_0_700), .A2(op1[28]), .B1(op1[29]), .B2(n_0_708), + .ZN(n_0_680)); + NAND2_X1_LVT i_0_694 (.A1(n_0_688), .A2(op2[27]), .ZN(n_0_661)); + INV_X1_LVT i_0_742 (.A(op2[26]), .ZN(n_0_709)); + OAI22_X1_LVT i_0_712 (.A1(n_0_699), .A2(op2[25]), .B1(n_0_736), .B2(op2[24]), + .ZN(n_0_679)); + NAND2_X1_LVT i_0_690 (.A1(n_0_727), .A2(op2[20]), .ZN(n_0_657)); + INV_X1_LVT i_0_740 (.A(op2[18]), .ZN(n_0_707)); + OAI22_X1_LVT i_0_711 (.A1(n_0_707), .A2(op1[18]), .B1(n_0_690), .B2(op1[19]), + .ZN(n_0_678)); + OAI22_X1_LVT i_0_29 (.A1(n_0_739), .A2(op2[16]), .B1(n_0_734), .B2(op2[15]), + .ZN(n_0_28)); + INV_X1_LVT i_0_728 (.A(op2[12]), .ZN(n_0_695)); + INV_X1_LVT i_0_748 (.A(op2[13]), .ZN(n_0_715)); + OAI22_X1_LVT i_0_704 (.A1(n_0_706), .A2(op2[11]), .B1(n_0_696), .B2(op2[12]), + .ZN(n_0_671)); + AOI22_X1_LVT i_0_710 (.A1(n_0_740), .A2(op2[8]), .B1(n_0_713), .B2(op2[7]), + .ZN(n_0_677)); + OAI22_X1_LVT i_0_707 (.A1(n_0_731), .A2(op1[5]), .B1(op1[6]), .B2(n_0_702), + .ZN(n_0_674)); + OAI22_X1_LVT i_0_706 (.A1(op1[2]), .A2(n_0_693), .B1(op1[1]), .B2(n_0_728), + .ZN(n_0_673)); + INV_X1_LVT i_0_705 (.A(n_0_673), .ZN(n_0_672)); + INV_X1_LVT i_0_699 (.A(n_0_667), .ZN(n_0_666)); + OAI21_X1_LVT i_0_42 (.A(n_0_672), .B1(n_0_666), .B2(n_0_665), .ZN(n_0_41)); + AOI21_X1_LVT i_0_41 (.A(n_0_654), .B1(op1[2]), .B2(n_0_693), .ZN(n_0_40)); + AOI211_X1_LVT i_0_40 (.A(n_0_668), .B(n_0_663), .C1(n_0_41), .C2(n_0_40), + .ZN(n_0_39)); + AOI211_X1_LVT i_0_39 (.A(n_0_656), .B(n_0_39), .C1(n_0_731), .C2(op1[5]), + .ZN(n_0_38)); + OAI222_X1_LVT i_0_38 (.A1(n_0_704), .A2(op2[6]), .B1(n_0_674), .B2(n_0_38), + .C1(n_0_713), .C2(op2[7]), .ZN(n_0_37)); + AOI221_X1_LVT i_0_37 (.A(n_0_655), .B1(op1[9]), .B2(n_0_720), .C1(n_0_677), + .C2(n_0_37), .ZN(n_0_36)); + INV_X1_LVT i_0_768 (.A(op2[10]), .ZN(n_0_735)); + OAI22_X1_LVT i_0_36 (.A1(n_0_735), .A2(op1[10]), .B1(op1[9]), .B2(n_0_720), + .ZN(n_0_35)); + OAI22_X1_LVT i_0_35 (.A1(op2[10]), .A2(n_0_733), .B1(n_0_36), .B2(n_0_35), + .ZN(n_0_34)); + INV_X1_LVT i_0_34 (.A(n_0_34), .ZN(n_0_33)); + AOI21_X1_LVT i_0_33 (.A(n_0_33), .B1(n_0_706), .B2(op2[11]), .ZN(n_0_32)); + OAI222_X1_LVT i_0_32 (.A1(op1[12]), .A2(n_0_695), .B1(n_0_715), .B2(op1[13]), + .C1(n_0_671), .C2(n_0_32), .ZN(n_0_31)); + OAI221_X1_LVT i_0_31 (.A(n_0_31), .B1(n_0_721), .B2(op2[14]), .C1(op2[13]), + .C2(n_0_714), .ZN(n_0_30)); + AOI22_X1_LVT i_0_30 (.A1(n_0_734), .A2(op2[15]), .B1(n_0_721), .B2(op2[14]), + .ZN(n_0_29)); + AOI21_X1_LVT i_0_28 (.A(n_0_28), .B1(n_0_30), .B2(n_0_29), .ZN(n_0_27)); + AOI221_X1_LVT i_0_27 (.A(n_0_27), .B1(n_0_732), .B2(op2[17]), .C1(n_0_739), + .C2(op2[16]), .ZN(n_0_26)); + AOI211_X1_LVT i_0_26 (.A(n_0_660), .B(n_0_26), .C1(n_0_707), .C2(op1[18]), + .ZN(n_0_25)); + OAI22_X1_LVT i_0_25 (.A1(op2[19]), .A2(n_0_689), .B1(n_0_678), .B2(n_0_25), + .ZN(n_0_24)); + AOI211_X1_LVT i_0_24 (.A(n_0_658), .B(n_0_659), .C1(n_0_657), .C2(n_0_24), + .ZN(n_0_23)); + AOI221_X1_LVT i_0_23 (.A(n_0_23), .B1(n_0_726), .B2(op2[21]), .C1(n_0_687), + .C2(op2[22]), .ZN(n_0_22)); + AOI221_X1_LVT i_0_22 (.A(n_0_22), .B1(op1[22]), .B2(n_0_686), .C1(op1[23]), + .C2(n_0_718), .ZN(n_0_21)); + AOI221_X1_LVT i_0_21 (.A(n_0_21), .B1(n_0_736), .B2(op2[24]), .C1(n_0_719), + .C2(op2[23]), .ZN(n_0_20)); + OAI222_X1_LVT i_0_20 (.A1(op1[26]), .A2(n_0_709), .B1(op1[25]), .B2(n_0_697), + .C1(n_0_679), .C2(n_0_20), .ZN(n_0_19)); + OAI221_X1_LVT i_0_19 (.A(n_0_19), .B1(n_0_711), .B2(op2[26]), .C1(n_0_688), + .C2(op2[27]), .ZN(n_0_18)); + AOI22_X1_LVT i_0_18 (.A1(n_0_700), .A2(op1[28]), .B1(n_0_661), .B2(n_0_18), + .ZN(n_0_17)); + OAI21_X1_LVT i_0_17 (.A(n_0_652), .B1(n_0_680), .B2(n_0_17), .ZN(n_0_16)); + INV_X1_LVT i_0_749 (.A(op2[30]), .ZN(n_0_716)); + OAI21_X1_LVT i_0_16 (.A(n_0_16), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_15)); + OAI22_X1_LVT i_0_708 (.A1(n_0_692), .A2(op1[31]), .B1(op2[31]), .B2(n_0_691), + .ZN(n_0_675)); + AOI21_X1_LVT i_0_15 (.A(n_0_675), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_14)); + AOI21_X1_LVT i_0_13 (.A(n_0_13), .B1(n_0_15), .B2(n_0_14), .ZN(n_0_12)); + NOR4_X1_LVT i_0_12 (.A1(n_0_685), .A2(aluOp[2]), .A3(aluBypass), .A4(n_0_12), + .ZN(n_0_11)); + OR3_X1_LVT i_0_0 (.A1(n_0_6), .A2(n_0_0), .A3(n_0_11), .ZN(result[0])); + OR4_X1_LVT i_0_703 (.A1(n_0_680), .A2(n_0_673), .A3(n_0_675), .A4(n_0_678), + .ZN(n_0_670)); + INV_X1_LVT i_0_709 (.A(n_0_677), .ZN(n_0_676)); + OR4_X1_LVT i_0_702 (.A1(n_0_679), .A2(n_0_674), .A3(n_0_676), .A4(n_0_671), + .ZN(n_0_669)); + AOI22_X1_LVT i_0_663 (.A1(n_0_688), .A2(op2[27]), .B1(op1[22]), .B2(n_0_686), + .ZN(n_0_630)); + OAI22_X1_LVT i_0_662 (.A1(n_0_694), .A2(op2[2]), .B1(op1[30]), .B2(n_0_716), + .ZN(n_0_629)); + AOI221_X1_LVT i_0_661 (.A(n_0_629), .B1(n_0_711), .B2(op2[26]), .C1(n_0_721), + .C2(op2[14]), .ZN(n_0_628)); + AOI21_X1_LVT i_0_664 (.A(n_0_660), .B1(n_0_690), .B2(op1[19]), .ZN(n_0_631)); + OAI222_X1_LVT i_0_660 (.A1(op1[12]), .A2(n_0_695), .B1(n_0_688), .B2(op2[27]), + .C1(op1[22]), .C2(n_0_686), .ZN(n_0_627)); + AOI21_X1_LVT i_0_659 (.A(n_0_663), .B1(n_0_734), .B2(op2[15]), .ZN(n_0_626)); + OAI211_X1_LVT i_0_658 (.A(n_0_666), .B(n_0_626), .C1(n_0_715), .C2(op1[13]), + .ZN(n_0_625)); + AOI211_X1_LVT i_0_657 (.A(n_0_627), .B(n_0_625), .C1(op1[23]), .C2(n_0_718), + .ZN(n_0_624)); + NAND4_X1_LVT i_0_656 (.A1(n_0_630), .A2(n_0_628), .A3(n_0_631), .A4(n_0_624), + .ZN(n_0_623)); + OAI22_X1_LVT i_0_684 (.A1(n_0_721), .A2(op2[14]), .B1(n_0_722), .B2(op2[9]), + .ZN(n_0_651)); + AOI211_X1_LVT i_0_668 (.A(n_0_651), .B(n_0_654), .C1(n_0_719), .C2(op2[23]), + .ZN(n_0_635)); + NAND2_X1_LVT i_0_667 (.A1(n_0_664), .A2(n_0_657), .ZN(n_0_634)); + NOR3_X1_LVT i_0_666 (.A1(n_0_659), .A2(n_0_656), .A3(n_0_634), .ZN(n_0_633)); + AOI21_X1_LVT i_0_671 (.A(n_0_655), .B1(n_0_739), .B2(op2[16]), .ZN(n_0_638)); + AOI21_X1_LVT i_0_670 (.A(n_0_668), .B1(n_0_736), .B2(op2[24]), .ZN(n_0_637)); + OAI22_X1_LVT i_0_673 (.A1(n_0_735), .A2(op1[10]), .B1(n_0_734), .B2(op2[15]), + .ZN(n_0_640)); + AOI221_X1_LVT i_0_672 (.A(n_0_640), .B1(n_0_732), .B2(op2[17]), .C1(n_0_731), + .C2(op1[5]), .ZN(n_0_639)); + AND3_X1_LVT i_0_669 (.A1(n_0_638), .A2(n_0_637), .A3(n_0_639), .ZN(n_0_636)); + OAI22_X1_LVT i_0_682 (.A1(n_0_703), .A2(op2[0]), .B1(n_0_704), .B2(op2[6]), + .ZN(n_0_649)); + OAI22_X1_LVT i_0_681 (.A1(op2[28]), .A2(n_0_698), .B1(op1[25]), .B2(n_0_697), + .ZN(n_0_648)); + AOI21_X1_LVT i_0_678 (.A(n_0_658), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_645)); + AOI21_X1_LVT i_0_677 (.A(n_0_662), .B1(n_0_735), .B2(op1[10]), .ZN(n_0_644)); + INV_X1_LVT i_0_758 (.A(op2[21]), .ZN(n_0_725)); + OAI22_X1_LVT i_0_683 (.A1(op1[21]), .A2(n_0_725), .B1(n_0_739), .B2(op2[16]), + .ZN(n_0_650)); + AOI221_X1_LVT i_0_676 (.A(n_0_650), .B1(n_0_722), .B2(op2[9]), .C1(op1[7]), + .C2(n_0_712), .ZN(n_0_643)); + OAI21_X1_LVT i_0_680 (.A(n_0_652), .B1(n_0_711), .B2(op2[26]), .ZN(n_0_647)); + AOI221_X1_LVT i_0_679 (.A(n_0_647), .B1(n_0_706), .B2(op2[11]), .C1(n_0_707), + .C2(op1[18]), .ZN(n_0_646)); + NAND4_X1_LVT i_0_675 (.A1(n_0_645), .A2(n_0_644), .A3(n_0_643), .A4(n_0_646), + .ZN(n_0_642)); + NOR3_X1_LVT i_0_674 (.A1(n_0_649), .A2(n_0_648), .A3(n_0_642), .ZN(n_0_641)); + NAND4_X1_LVT i_0_665 (.A1(n_0_635), .A2(n_0_633), .A3(n_0_636), .A4(n_0_641), + .ZN(n_0_632)); + NOR4_X1_LVT i_0_655 (.A1(n_0_670), .A2(n_0_669), .A3(n_0_623), .A4(n_0_632), + .ZN(eqFlag)); +endmodule + +module decoder(CurrentPC, JumpOrBranchPC, JumpOrBranch, DAddr, WData, RData, + Instruction, WrMem, DWidth, Rs1, Rs2, Rd, RRs1, RRs2, WRd, WrReg, Illegal); + input [31:0]CurrentPC; + output [31:0]JumpOrBranchPC; + output JumpOrBranch; + output [31:0]DAddr; + output [31:0]WData; + input [31:0]RData; + input [31:0]Instruction; + output WrMem; + output [1:0]DWidth; + output [4:0]Rs1; + output [4:0]Rs2; + output [4:0]Rd; + input [31:0]RRs1; + input [31:0]RRs2; + output [31:0]WRd; + output WrReg; + output Illegal; + + wire eqFlag; + wire n_5_0; + wire n_5_1; + wire n_5_2; + wire n_5_3; + wire n_5_4; + wire n_5_5; + wire n_5_6; + wire n_5_7; + wire n_5_8; + wire n_5_9; + wire n_5_10; + wire n_5_11; + wire n_5_12; + wire n_5_13; + wire n_5_14; + wire n_5_15; + wire n_5_16; + wire n_5_17; + wire n_5_18; + wire n_5_19; + wire n_5_20; + wire n_5_21; + wire n_5_22; + wire n_5_23; + wire n_5_24; + wire n_5_25; + wire n_5_26; + wire n_5_27; + wire n_5_28; + wire n_5_29; + wire n_5_30; + wire n_5_31; + wire n_5_32; + wire n_5_33; + wire n_17_0; + wire n_17_1; + wire n_17_2; + wire n_17_3; + wire n_17_4; + wire n_17_5; + wire n_17_6; + wire n_17_7; + wire n_17_8; + wire n_17_9; + wire n_17_10; + wire n_17_11; + wire n_17_12; + wire n_17_13; + wire n_17_14; + wire n_17_15; + wire n_17_16; + wire n_17_17; + wire n_17_18; + wire n_17_19; + wire n_17_20; + wire n_17_21; + wire n_17_22; + wire n_17_23; + wire n_17_24; + wire n_17_25; + wire n_17_26; + wire n_17_27; + wire n_17_28; + wire n_17_29; + wire n_17_30; + wire n_17_31; + wire n_17_32; + wire n_18_0; + wire n_18_1; + wire n_18_2; + wire n_18_3; + wire n_18_4; + wire n_18_5; + wire n_18_6; + wire n_18_7; + wire n_18_8; + wire n_18_9; + wire n_18_10; + wire n_18_11; + wire n_18_12; + wire n_18_13; + wire n_18_14; + wire n_18_15; + wire n_18_16; + wire n_18_17; + wire n_18_18; + wire n_18_19; + wire n_18_20; + wire n_18_21; + wire n_18_22; + wire n_18_23; + wire n_18_24; + wire n_18_25; + wire n_18_26; + wire n_18_27; + wire n_18_28; + wire n_18_29; + wire n_18_30; + wire n_18_31; + wire n_18_32; + wire n_0_15; + wire n_0_2; + wire n_0_16; + wire n_0_3; + wire n_0_17; + wire n_0_4; + wire n_0_18; + wire n_0_5; + wire n_0_19; + wire n_0_6; + wire n_0_20; + wire n_0_7; + wire n_0_21; + wire n_0_8; + wire n_0_22; + wire n_0_9; + wire n_0_23; + wire n_0_10; + wire n_0_24; + wire n_0_11; + wire n_0_25; + wire n_0_12; + wire n_0_26; + wire n_0_13; + wire n_0_27; + wire n_0_14; + wire n_0_28; + wire n_0_29; + wire n_0_30; + wire n_0_31; + wire n_0_32; + wire n_0_33; + wire n_0_34; + wire n_0_35; + wire n_0_36; + wire n_0_37; + wire n_0_38; + wire n_0_39; + wire n_0_40; + wire n_0_41; + wire n_0_42; + wire n_0_43; + wire n_0_44; + wire n_0_45; + wire n_0_46; + wire n_0_47; + wire n_0_48; + wire n_0_49; + wire n_0_50; + wire n_0_51; + wire n_0_52; + wire n_0_53; + wire n_0_54; + wire n_0_55; + wire n_0_56; + wire n_0_57; + wire n_0_58; + wire n_0_59; + wire n_0_60; + wire n_0_61; + wire n_0_62; + wire n_0_63; + wire n_0_64; + wire n_0_65; + wire n_0_66; + wire n_0_67; + wire n_0_68; + wire n_0_69; + wire n_0_70; + wire n_0_71; + wire n_0_72; + wire n_0_73; + wire n_0_74; + wire n_0_75; + wire n_0_76; + wire n_0_77; + wire n_0_78; + wire n_0_79; + wire n_0_80; + wire n_0_81; + wire n_0_82; + wire n_0_83; + wire n_0_84; + wire n_0_85; + wire n_0_86; + wire n_0_87; + wire n_0_88; + wire n_0_89; + wire n_0_90; + wire n_0_91; + wire n_0_92; + wire n_0_93; + wire n_0_94; + wire n_0_95; + wire n_0_96; + wire n_0_97; + wire [2:0]aluOp; + wire n_0_98; + wire n_0_99; + wire n_0_100; + wire aluNegAr; + wire n_0_101; + wire n_0_102; + wire n_0_103; + wire n_0_104; + wire n_0_105; + wire aluBypass; + wire n_0_106; + wire [31:0]op1; + wire n_0_107; + wire n_0_108; + wire n_0_109; + wire n_0_110; + wire n_0_111; + wire n_0_112; + wire n_0_113; + wire n_0_114; + wire n_0_115; + wire n_0_116; + wire n_0_117; + wire n_0_118; + wire n_0_119; + wire n_0_120; + wire n_0_121; + wire n_0_122; + wire n_0_123; + wire n_0_124; + wire n_0_125; + wire n_0_126; + wire n_0_127; + wire n_0_128; + wire n_0_129; + wire n_0_130; + wire n_0_131; + wire n_0_132; + wire n_0_133; + wire n_0_134; + wire n_0_135; + wire n_0_136; + wire n_0_137; + wire n_0_138; + wire n_0_139; + wire n_0_140; + wire n_0_141; + wire n_0_142; + wire n_0_143; + wire n_0_144; + wire n_0_145; + wire n_0_146; + wire n_0_147; + wire n_0_148; + wire n_0_149; + wire n_0_150; + wire n_0_151; + wire n_0_152; + wire n_0_153; + wire n_0_154; + wire n_0_155; + wire n_0_156; + wire n_0_157; + wire n_0_158; + wire n_0_159; + wire n_0_160; + wire n_0_161; + wire n_0_162; + wire n_0_163; + wire n_0_164; + wire n_0_165; + wire n_0_166; + wire n_0_167; + wire n_0_168; + wire n_0_169; + wire [31:0]op2; + wire n_0_170; + wire n_0_171; + wire n_0_172; + wire n_0_173; + wire n_0_174; + wire n_0_175; + wire n_0_176; + wire n_0_177; + wire n_0_178; + wire n_0_179; + wire n_0_180; + wire n_0_181; + wire n_0_182; + wire n_0_183; + wire n_0_184; + wire n_0_185; + wire n_0_186; + wire n_0_187; + wire n_0_188; + wire n_0_189; + wire n_0_190; + wire n_0_191; + wire n_0_192; + wire n_0_193; + wire n_0_194; + wire n_0_195; + wire n_0_196; + wire n_0_197; + wire n_0_198; + wire n_0_199; + wire n_0_200; + wire n_0_201; + wire n_0_202; + wire n_0_203; + wire n_0_204; + wire n_0_205; + wire n_0_206; + wire n_0_207; + wire n_0_208; + wire n_0_209; + wire n_0_210; + wire n_0_211; + wire n_0_212; + wire n_0_213; + wire n_0_214; + wire n_0_215; + wire n_0_216; + wire n_0_217; + wire n_0_218; + wire n_0_219; + wire n_0_220; + wire n_0_221; + wire n_0_222; + wire n_0_223; + wire n_0_224; + wire n_0_225; + wire n_0_226; + wire n_0_227; + wire n_0_228; + wire n_0_229; + wire n_0_230; + wire n_0_231; + wire n_0_232; + wire n_0_233; + wire n_0_234; + wire n_0_235; + wire n_0_236; + wire n_0_237; + wire n_0_238; + wire n_0_239; + wire n_0_240; + wire n_0_241; + wire n_0_242; + wire n_0_1; + wire n_0_0; + wire n_0_243; + wire n_0_244; + wire n_0_245; + wire n_0_246; + wire n_0_247; + wire n_0_248; + wire n_0_249; + + INV_X1_LVT i_18_1 (.A(CurrentPC[13]), .ZN(n_18_1)); + XNOR2_X1_LVT i_18_32 (.A(CurrentPC[31]), .B(n_18_1), .ZN(n_18_32)); + INV_X1_LVT i_18_0 (.A(Instruction[31]), .ZN(n_18_0)); + HA_X1_LVT i_18_2 (.A(Instruction[8]), .B(CurrentPC[1]), .CO(n_18_2), .S(n_63)); + FA_X1_LVT i_18_3 (.A(Instruction[9]), .B(CurrentPC[2]), .CI(n_18_2), .CO( + n_18_3), .S(n_64)); + FA_X1_LVT i_18_4 (.A(Instruction[10]), .B(CurrentPC[3]), .CI(n_18_3), + .CO(n_18_4), .S(n_65)); + FA_X1_LVT i_18_5 (.A(Instruction[11]), .B(CurrentPC[4]), .CI(n_18_4), + .CO(n_18_5), .S(n_66)); + FA_X1_LVT i_18_6 (.A(Instruction[25]), .B(CurrentPC[5]), .CI(n_18_5), + .CO(n_18_6), .S(n_67)); + FA_X1_LVT i_18_7 (.A(Instruction[26]), .B(CurrentPC[6]), .CI(n_18_6), + .CO(n_18_7), .S(n_68)); + FA_X1_LVT i_18_8 (.A(Instruction[27]), .B(CurrentPC[7]), .CI(n_18_7), + .CO(n_18_8), .S(n_69)); + FA_X1_LVT i_18_9 (.A(Instruction[28]), .B(CurrentPC[8]), .CI(n_18_8), + .CO(n_18_9), .S(n_70)); + FA_X1_LVT i_18_10 (.A(Instruction[29]), .B(CurrentPC[9]), .CI(n_18_9), + .CO(n_18_10), .S(n_71)); + FA_X1_LVT i_18_11 (.A(Instruction[30]), .B(CurrentPC[10]), .CI(n_18_10), + .CO(n_18_11), .S(n_72)); + FA_X1_LVT i_18_12 (.A(Instruction[7]), .B(CurrentPC[11]), .CI(n_18_11), + .CO(n_18_12), .S(n_73)); + FA_X1_LVT i_18_13 (.A(CurrentPC[12]), .B(Instruction[31]), .CI(n_18_12), + .CO(n_18_13), .S(n_74)); + FA_X1_LVT i_18_14 (.A(n_18_0), .B(n_18_1), .CI(n_18_13), .CO(n_18_14), + .S(n_75)); + FA_X1_LVT i_18_15 (.A(CurrentPC[14]), .B(n_18_1), .CI(n_18_14), .CO(n_18_15), + .S(n_76)); + FA_X1_LVT i_18_16 (.A(CurrentPC[15]), .B(n_18_1), .CI(n_18_15), .CO(n_18_16), + .S(n_77)); + FA_X1_LVT i_18_17 (.A(CurrentPC[16]), .B(n_18_1), .CI(n_18_16), .CO(n_18_17), + .S(n_78)); + FA_X1_LVT i_18_18 (.A(CurrentPC[17]), .B(n_18_1), .CI(n_18_17), .CO(n_18_18), + .S(n_79)); + FA_X1_LVT i_18_19 (.A(CurrentPC[18]), .B(n_18_1), .CI(n_18_18), .CO(n_18_19), + .S(n_80)); + FA_X1_LVT i_18_20 (.A(CurrentPC[19]), .B(n_18_1), .CI(n_18_19), .CO(n_18_20), + .S(n_81)); + FA_X1_LVT i_18_21 (.A(CurrentPC[20]), .B(n_18_1), .CI(n_18_20), .CO(n_18_21), + .S(n_82)); + FA_X1_LVT i_18_22 (.A(CurrentPC[21]), .B(n_18_1), .CI(n_18_21), .CO(n_18_22), + .S(n_83)); + FA_X1_LVT i_18_23 (.A(CurrentPC[22]), .B(n_18_1), .CI(n_18_22), .CO(n_18_23), + .S(n_84)); + FA_X1_LVT i_18_24 (.A(CurrentPC[23]), .B(n_18_1), .CI(n_18_23), .CO(n_18_24), + .S(n_85)); + FA_X1_LVT i_18_25 (.A(CurrentPC[24]), .B(n_18_1), .CI(n_18_24), .CO(n_18_25), + .S(n_86)); + FA_X1_LVT i_18_26 (.A(CurrentPC[25]), .B(n_18_1), .CI(n_18_25), .CO(n_18_26), + .S(n_87)); + FA_X1_LVT i_18_27 (.A(CurrentPC[26]), .B(n_18_1), .CI(n_18_26), .CO(n_18_27), + .S(n_88)); + FA_X1_LVT i_18_28 (.A(CurrentPC[27]), .B(n_18_1), .CI(n_18_27), .CO(n_18_28), + .S(n_89)); + FA_X1_LVT i_18_29 (.A(CurrentPC[28]), .B(n_18_1), .CI(n_18_28), .CO(n_18_29), + .S(n_90)); + FA_X1_LVT i_18_30 (.A(CurrentPC[29]), .B(n_18_1), .CI(n_18_29), .CO(n_18_30), + .S(n_91)); + FA_X1_LVT i_18_31 (.A(CurrentPC[30]), .B(n_18_1), .CI(n_18_30), .CO(n_18_31), + .S(n_92)); + XNOR2_X1_LVT i_18_33 (.A(n_18_32), .B(n_18_31), .ZN(n_93)); + INV_X1_LVT i_0_350 (.A(Instruction[3]), .ZN(n_0_243)); + NAND3_X1_LVT i_0_343 (.A1(n_0_243), .A2(Instruction[0]), .A3(Instruction[1]), + .ZN(n_0_238)); + OR2_X1_LVT i_0_332 (.A1(n_0_238), .A2(Instruction[2]), .ZN(n_0_228)); + INV_X1_LVT i_0_351 (.A(Instruction[5]), .ZN(n_0_244)); + NOR2_X1_LVT i_0_340 (.A1(n_0_244), .A2(Instruction[4]), .ZN(n_0_235)); + NAND2_X1_LVT i_0_329 (.A1(Instruction[6]), .A2(n_0_235), .ZN(n_0_225)); + INV_X1_LVT i_0_354 (.A(Instruction[13]), .ZN(n_0_247)); + NOR2_X1_LVT i_0_345 (.A1(n_0_247), .A2(Instruction[14]), .ZN(n_0_240)); + NOR3_X1_LVT i_0_118 (.A1(n_0_228), .A2(n_0_225), .A3(n_0_240), .ZN(n_0_99)); + NAND3_X1_LVT i_0_346 (.A1(Instruction[0]), .A2(Instruction[1]), .A3( + Instruction[2]), .ZN(n_0_241)); + NOR2_X1_LVT i_0_328 (.A1(n_0_241), .A2(n_0_225), .ZN(n_0_224)); + INV_X1_LVT i_0_356 (.A(n_0_224), .ZN(n_0_249)); + NOR2_X1_LVT i_0_108 (.A1(n_0_243), .A2(n_0_249), .ZN(n_0_91)); + INV_X1_LVT i_17_1 (.A(CurrentPC[21]), .ZN(n_17_1)); + XNOR2_X1_LVT i_17_32 (.A(CurrentPC[31]), .B(n_17_1), .ZN(n_17_32)); + INV_X1_LVT i_17_0 (.A(Instruction[31]), .ZN(n_17_0)); + HA_X1_LVT i_17_2 (.A(Instruction[21]), .B(CurrentPC[1]), .CO(n_17_2), + .S(n_32)); + FA_X1_LVT i_17_3 (.A(Instruction[22]), .B(CurrentPC[2]), .CI(n_17_2), + .CO(n_17_3), .S(n_33)); + FA_X1_LVT i_17_4 (.A(Instruction[23]), .B(CurrentPC[3]), .CI(n_17_3), + .CO(n_17_4), .S(n_34)); + FA_X1_LVT i_17_5 (.A(Instruction[24]), .B(CurrentPC[4]), .CI(n_17_4), + .CO(n_17_5), .S(n_35)); + FA_X1_LVT i_17_6 (.A(Instruction[25]), .B(CurrentPC[5]), .CI(n_17_5), + .CO(n_17_6), .S(n_36)); + FA_X1_LVT i_17_7 (.A(Instruction[26]), .B(CurrentPC[6]), .CI(n_17_6), + .CO(n_17_7), .S(n_37)); + FA_X1_LVT i_17_8 (.A(Instruction[27]), .B(CurrentPC[7]), .CI(n_17_7), + .CO(n_17_8), .S(n_38)); + FA_X1_LVT i_17_9 (.A(Instruction[28]), .B(CurrentPC[8]), .CI(n_17_8), + .CO(n_17_9), .S(n_39)); + FA_X1_LVT i_17_10 (.A(Instruction[29]), .B(CurrentPC[9]), .CI(n_17_9), + .CO(n_17_10), .S(n_40)); + FA_X1_LVT i_17_11 (.A(Instruction[30]), .B(CurrentPC[10]), .CI(n_17_10), + .CO(n_17_11), .S(n_41)); + FA_X1_LVT i_17_12 (.A(Instruction[20]), .B(CurrentPC[11]), .CI(n_17_11), + .CO(n_17_12), .S(n_42)); + FA_X1_LVT i_17_13 (.A(Instruction[12]), .B(CurrentPC[12]), .CI(n_17_12), + .CO(n_17_13), .S(n_43)); + FA_X1_LVT i_17_14 (.A(Instruction[13]), .B(CurrentPC[13]), .CI(n_17_13), + .CO(n_17_14), .S(n_44)); + FA_X1_LVT i_17_15 (.A(Instruction[14]), .B(CurrentPC[14]), .CI(n_17_14), + .CO(n_17_15), .S(n_45)); + FA_X1_LVT i_17_16 (.A(Instruction[15]), .B(CurrentPC[15]), .CI(n_17_15), + .CO(n_17_16), .S(n_46)); + FA_X1_LVT i_17_17 (.A(Instruction[16]), .B(CurrentPC[16]), .CI(n_17_16), + .CO(n_17_17), .S(n_47)); + FA_X1_LVT i_17_18 (.A(Instruction[17]), .B(CurrentPC[17]), .CI(n_17_17), + .CO(n_17_18), .S(n_48)); + FA_X1_LVT i_17_19 (.A(Instruction[18]), .B(CurrentPC[18]), .CI(n_17_18), + .CO(n_17_19), .S(n_49)); + FA_X1_LVT i_17_20 (.A(Instruction[19]), .B(CurrentPC[19]), .CI(n_17_19), + .CO(n_17_20), .S(n_50)); + FA_X1_LVT i_17_21 (.A(CurrentPC[20]), .B(Instruction[31]), .CI(n_17_20), + .CO(n_17_21), .S(n_51)); + FA_X1_LVT i_17_22 (.A(n_17_0), .B(n_17_1), .CI(n_17_21), .CO(n_17_22), + .S(n_52)); + FA_X1_LVT i_17_23 (.A(CurrentPC[22]), .B(n_17_1), .CI(n_17_22), .CO(n_17_23), + .S(n_53)); + FA_X1_LVT i_17_24 (.A(CurrentPC[23]), .B(n_17_1), .CI(n_17_23), .CO(n_17_24), + .S(n_54)); + FA_X1_LVT i_17_25 (.A(CurrentPC[24]), .B(n_17_1), .CI(n_17_24), .CO(n_17_25), + .S(n_55)); + FA_X1_LVT i_17_26 (.A(CurrentPC[25]), .B(n_17_1), .CI(n_17_25), .CO(n_17_26), + .S(n_56)); + FA_X1_LVT i_17_27 (.A(CurrentPC[26]), .B(n_17_1), .CI(n_17_26), .CO(n_17_27), + .S(n_57)); + FA_X1_LVT i_17_28 (.A(CurrentPC[27]), .B(n_17_1), .CI(n_17_27), .CO(n_17_28), + .S(n_58)); + FA_X1_LVT i_17_29 (.A(CurrentPC[28]), .B(n_17_1), .CI(n_17_28), .CO(n_17_29), + .S(n_59)); + FA_X1_LVT i_17_30 (.A(CurrentPC[29]), .B(n_17_1), .CI(n_17_29), .CO(n_17_30), + .S(n_60)); + FA_X1_LVT i_17_31 (.A(CurrentPC[30]), .B(n_17_1), .CI(n_17_30), .CO(n_17_31), + .S(n_61)); + XNOR2_X1_LVT i_17_33 (.A(n_17_32), .B(n_17_31), .ZN(n_62)); + INV_X1_LVT i_5_1 (.A(RRs1[12]), .ZN(n_5_1)); + XNOR2_X1_LVT i_5_33 (.A(RRs1[31]), .B(n_5_1), .ZN(n_5_33)); + INV_X1_LVT i_5_0 (.A(Instruction[31]), .ZN(n_5_0)); + HA_X1_LVT i_5_2 (.A(Instruction[20]), .B(RRs1[0]), .CO(n_5_2), .S(n_0)); + FA_X1_LVT i_5_3 (.A(Instruction[21]), .B(RRs1[1]), .CI(n_5_2), .CO(n_5_3), + .S(n_1)); + FA_X1_LVT i_5_4 (.A(Instruction[22]), .B(RRs1[2]), .CI(n_5_3), .CO(n_5_4), + .S(n_2)); + FA_X1_LVT i_5_5 (.A(Instruction[23]), .B(RRs1[3]), .CI(n_5_4), .CO(n_5_5), + .S(n_3)); + FA_X1_LVT i_5_6 (.A(Instruction[24]), .B(RRs1[4]), .CI(n_5_5), .CO(n_5_6), + .S(n_4)); + FA_X1_LVT i_5_7 (.A(Instruction[25]), .B(RRs1[5]), .CI(n_5_6), .CO(n_5_7), + .S(n_5)); + FA_X1_LVT i_5_8 (.A(Instruction[26]), .B(RRs1[6]), .CI(n_5_7), .CO(n_5_8), + .S(n_6)); + FA_X1_LVT i_5_9 (.A(Instruction[27]), .B(RRs1[7]), .CI(n_5_8), .CO(n_5_9), + .S(n_7)); + FA_X1_LVT i_5_10 (.A(Instruction[28]), .B(RRs1[8]), .CI(n_5_9), .CO(n_5_10), + .S(n_8)); + FA_X1_LVT i_5_11 (.A(Instruction[29]), .B(RRs1[9]), .CI(n_5_10), .CO(n_5_11), + .S(n_9)); + FA_X1_LVT i_5_12 (.A(Instruction[30]), .B(RRs1[10]), .CI(n_5_11), .CO(n_5_12), + .S(n_10)); + FA_X1_LVT i_5_13 (.A(RRs1[11]), .B(Instruction[31]), .CI(n_5_12), .CO(n_5_13), + .S(n_11)); + FA_X1_LVT i_5_14 (.A(n_5_0), .B(n_5_1), .CI(n_5_13), .CO(n_5_14), .S(n_12)); + FA_X1_LVT i_5_15 (.A(RRs1[13]), .B(n_5_1), .CI(n_5_14), .CO(n_5_15), .S(n_13)); + FA_X1_LVT i_5_16 (.A(RRs1[14]), .B(n_5_1), .CI(n_5_15), .CO(n_5_16), .S(n_14)); + FA_X1_LVT i_5_17 (.A(RRs1[15]), .B(n_5_1), .CI(n_5_16), .CO(n_5_17), .S(n_15)); + FA_X1_LVT i_5_18 (.A(RRs1[16]), .B(n_5_1), .CI(n_5_17), .CO(n_5_18), .S(n_16)); + FA_X1_LVT i_5_19 (.A(RRs1[17]), .B(n_5_1), .CI(n_5_18), .CO(n_5_19), .S(n_17)); + FA_X1_LVT i_5_20 (.A(RRs1[18]), .B(n_5_1), .CI(n_5_19), .CO(n_5_20), .S(n_18)); + FA_X1_LVT i_5_21 (.A(RRs1[19]), .B(n_5_1), .CI(n_5_20), .CO(n_5_21), .S(n_19)); + FA_X1_LVT i_5_22 (.A(RRs1[20]), .B(n_5_1), .CI(n_5_21), .CO(n_5_22), .S(n_20)); + FA_X1_LVT i_5_23 (.A(RRs1[21]), .B(n_5_1), .CI(n_5_22), .CO(n_5_23), .S(n_21)); + FA_X1_LVT i_5_24 (.A(RRs1[22]), .B(n_5_1), .CI(n_5_23), .CO(n_5_24), .S(n_22)); + FA_X1_LVT i_5_25 (.A(RRs1[23]), .B(n_5_1), .CI(n_5_24), .CO(n_5_25), .S(n_23)); + FA_X1_LVT i_5_26 (.A(RRs1[24]), .B(n_5_1), .CI(n_5_25), .CO(n_5_26), .S(n_24)); + FA_X1_LVT i_5_27 (.A(RRs1[25]), .B(n_5_1), .CI(n_5_26), .CO(n_5_27), .S(n_25)); + FA_X1_LVT i_5_28 (.A(RRs1[26]), .B(n_5_1), .CI(n_5_27), .CO(n_5_28), .S(n_26)); + FA_X1_LVT i_5_29 (.A(RRs1[27]), .B(n_5_1), .CI(n_5_28), .CO(n_5_29), .S(n_27)); + FA_X1_LVT i_5_30 (.A(RRs1[28]), .B(n_5_1), .CI(n_5_29), .CO(n_5_30), .S(n_28)); + FA_X1_LVT i_5_31 (.A(RRs1[29]), .B(n_5_1), .CI(n_5_30), .CO(n_5_31), .S(n_29)); + FA_X1_LVT i_5_32 (.A(RRs1[30]), .B(n_5_1), .CI(n_5_31), .CO(n_5_32), .S(n_30)); + XNOR2_X1_LVT i_5_34 (.A(n_5_33), .B(n_5_32), .ZN(n_31)); + NOR2_X1_LVT i_0_107 (.A1(n_0_249), .A2(Instruction[3]), .ZN(n_0_90)); + AOI222_X1_LVT i_0_106 (.A1(n_93), .A2(n_0_99), .B1(n_0_91), .B2(n_62), + .C1(n_31), .C2(n_0_90), .ZN(n_0_89)); + INV_X1_LVT i_0_355 (.A(Instruction[6]), .ZN(n_0_248)); + NAND2_X1_LVT i_0_339 (.A1(n_0_248), .A2(Instruction[4]), .ZN(n_0_234)); + INV_X1_LVT i_0_338 (.A(n_0_234), .ZN(n_0_233)); + OAI21_X1_LVT i_0_341 (.A(Instruction[13]), .B1(Instruction[14]), .B2( + Instruction[12]), .ZN(n_0_236)); + AOI211_X1_LVT i_0_337 (.A(n_0_235), .B(n_0_233), .C1(n_0_248), .C2(n_0_236), + .ZN(n_0_232)); + INV_X1_LVT i_0_352 (.A(Instruction[4]), .ZN(n_0_245)); + NAND2_X1_LVT i_0_344 (.A1(n_0_245), .A2(Instruction[2]), .ZN(n_0_239)); + AOI21_X1_LVT i_0_335 (.A(Instruction[6]), .B1(n_0_243), .B2(n_0_239), + .ZN(n_0_230)); + NOR2_X1_LVT i_0_334 (.A1(n_0_232), .A2(n_0_230), .ZN(n_0_229)); + NAND2_X1_LVT i_0_342 (.A1(n_0_241), .A2(n_0_238), .ZN(n_0_237)); + NAND2_X1_LVT i_0_336 (.A1(Instruction[6]), .A2(n_0_240), .ZN(n_0_231)); + OAI211_X1_LVT i_0_333 (.A(n_0_229), .B(n_0_237), .C1(Instruction[2]), + .C2(n_0_231), .ZN(Illegal)); + NAND2_X1_LVT i_0_109 (.A1(Illegal), .A2(CurrentPC[31]), .ZN(n_0_92)); + NAND2_X1_LVT i_0_105 (.A1(n_0_89), .A2(n_0_92), .ZN(JumpOrBranchPC[31])); + AOI222_X1_LVT i_0_103 (.A1(n_92), .A2(n_0_99), .B1(n_0_91), .B2(n_61), + .C1(n_30), .C2(n_0_90), .ZN(n_0_87)); + NAND2_X1_LVT i_0_104 (.A1(Illegal), .A2(CurrentPC[30]), .ZN(n_0_88)); + NAND2_X1_LVT i_0_102 (.A1(n_0_87), .A2(n_0_88), .ZN(JumpOrBranchPC[30])); + AOI222_X1_LVT i_0_100 (.A1(n_91), .A2(n_0_99), .B1(n_0_91), .B2(n_60), + .C1(n_29), .C2(n_0_90), .ZN(n_0_85)); + NAND2_X1_LVT i_0_101 (.A1(Illegal), .A2(CurrentPC[29]), .ZN(n_0_86)); + NAND2_X1_LVT i_0_99 (.A1(n_0_85), .A2(n_0_86), .ZN(JumpOrBranchPC[29])); + AOI222_X1_LVT i_0_97 (.A1(n_90), .A2(n_0_99), .B1(n_0_91), .B2(n_59), + .C1(n_28), .C2(n_0_90), .ZN(n_0_83)); + NAND2_X1_LVT i_0_98 (.A1(Illegal), .A2(CurrentPC[28]), .ZN(n_0_84)); + NAND2_X1_LVT i_0_96 (.A1(n_0_83), .A2(n_0_84), .ZN(JumpOrBranchPC[28])); + AOI222_X1_LVT i_0_94 (.A1(n_89), .A2(n_0_99), .B1(n_0_91), .B2(n_58), + .C1(n_27), .C2(n_0_90), .ZN(n_0_81)); + NAND2_X1_LVT i_0_95 (.A1(Illegal), .A2(CurrentPC[27]), .ZN(n_0_82)); + NAND2_X1_LVT i_0_93 (.A1(n_0_81), .A2(n_0_82), .ZN(JumpOrBranchPC[27])); + AOI222_X1_LVT i_0_91 (.A1(n_88), .A2(n_0_99), .B1(n_0_91), .B2(n_57), + .C1(n_26), .C2(n_0_90), .ZN(n_0_79)); + NAND2_X1_LVT i_0_92 (.A1(Illegal), .A2(CurrentPC[26]), .ZN(n_0_80)); + NAND2_X1_LVT i_0_90 (.A1(n_0_79), .A2(n_0_80), .ZN(JumpOrBranchPC[26])); + AOI222_X1_LVT i_0_88 (.A1(n_87), .A2(n_0_99), .B1(n_0_91), .B2(n_56), + .C1(n_25), .C2(n_0_90), .ZN(n_0_77)); + NAND2_X1_LVT i_0_89 (.A1(Illegal), .A2(CurrentPC[25]), .ZN(n_0_78)); + NAND2_X1_LVT i_0_87 (.A1(n_0_77), .A2(n_0_78), .ZN(JumpOrBranchPC[25])); + AOI222_X1_LVT i_0_85 (.A1(n_86), .A2(n_0_99), .B1(n_0_91), .B2(n_55), + .C1(n_24), .C2(n_0_90), .ZN(n_0_75)); + NAND2_X1_LVT i_0_86 (.A1(Illegal), .A2(CurrentPC[24]), .ZN(n_0_76)); + NAND2_X1_LVT i_0_84 (.A1(n_0_75), .A2(n_0_76), .ZN(JumpOrBranchPC[24])); + AOI222_X1_LVT i_0_82 (.A1(n_85), .A2(n_0_99), .B1(n_0_91), .B2(n_54), + .C1(n_23), .C2(n_0_90), .ZN(n_0_73)); + NAND2_X1_LVT i_0_83 (.A1(Illegal), .A2(CurrentPC[23]), .ZN(n_0_74)); + NAND2_X1_LVT i_0_81 (.A1(n_0_73), .A2(n_0_74), .ZN(JumpOrBranchPC[23])); + AOI222_X1_LVT i_0_79 (.A1(n_84), .A2(n_0_99), .B1(n_0_91), .B2(n_53), + .C1(n_22), .C2(n_0_90), .ZN(n_0_71)); + NAND2_X1_LVT i_0_80 (.A1(Illegal), .A2(CurrentPC[22]), .ZN(n_0_72)); + NAND2_X1_LVT i_0_78 (.A1(n_0_71), .A2(n_0_72), .ZN(JumpOrBranchPC[22])); + AOI222_X1_LVT i_0_76 (.A1(n_83), .A2(n_0_99), .B1(n_0_91), .B2(n_52), + .C1(n_21), .C2(n_0_90), .ZN(n_0_69)); + NAND2_X1_LVT i_0_77 (.A1(Illegal), .A2(CurrentPC[21]), .ZN(n_0_70)); + NAND2_X1_LVT i_0_75 (.A1(n_0_69), .A2(n_0_70), .ZN(JumpOrBranchPC[21])); + AOI222_X1_LVT i_0_73 (.A1(n_82), .A2(n_0_99), .B1(n_0_91), .B2(n_51), + .C1(n_20), .C2(n_0_90), .ZN(n_0_67)); + NAND2_X1_LVT i_0_74 (.A1(Illegal), .A2(CurrentPC[20]), .ZN(n_0_68)); + NAND2_X1_LVT i_0_72 (.A1(n_0_67), .A2(n_0_68), .ZN(JumpOrBranchPC[20])); + AOI222_X1_LVT i_0_70 (.A1(n_81), .A2(n_0_99), .B1(n_0_91), .B2(n_50), + .C1(n_19), .C2(n_0_90), .ZN(n_0_65)); + NAND2_X1_LVT i_0_71 (.A1(Illegal), .A2(CurrentPC[19]), .ZN(n_0_66)); + NAND2_X1_LVT i_0_69 (.A1(n_0_65), .A2(n_0_66), .ZN(JumpOrBranchPC[19])); + AOI222_X1_LVT i_0_67 (.A1(n_80), .A2(n_0_99), .B1(n_0_91), .B2(n_49), + .C1(n_18), .C2(n_0_90), .ZN(n_0_63)); + NAND2_X1_LVT i_0_68 (.A1(Illegal), .A2(CurrentPC[18]), .ZN(n_0_64)); + NAND2_X1_LVT i_0_66 (.A1(n_0_63), .A2(n_0_64), .ZN(JumpOrBranchPC[18])); + AOI222_X1_LVT i_0_64 (.A1(n_79), .A2(n_0_99), .B1(n_0_91), .B2(n_48), + .C1(n_17), .C2(n_0_90), .ZN(n_0_61)); + NAND2_X1_LVT i_0_65 (.A1(Illegal), .A2(CurrentPC[17]), .ZN(n_0_62)); + NAND2_X1_LVT i_0_63 (.A1(n_0_61), .A2(n_0_62), .ZN(JumpOrBranchPC[17])); + AOI222_X1_LVT i_0_61 (.A1(n_78), .A2(n_0_99), .B1(n_0_91), .B2(n_47), + .C1(n_16), .C2(n_0_90), .ZN(n_0_59)); + NAND2_X1_LVT i_0_62 (.A1(Illegal), .A2(CurrentPC[16]), .ZN(n_0_60)); + NAND2_X1_LVT i_0_60 (.A1(n_0_59), .A2(n_0_60), .ZN(JumpOrBranchPC[16])); + AOI222_X1_LVT i_0_58 (.A1(n_77), .A2(n_0_99), .B1(n_0_91), .B2(n_46), + .C1(n_15), .C2(n_0_90), .ZN(n_0_57)); + NAND2_X1_LVT i_0_59 (.A1(Illegal), .A2(CurrentPC[15]), .ZN(n_0_58)); + NAND2_X1_LVT i_0_57 (.A1(n_0_57), .A2(n_0_58), .ZN(JumpOrBranchPC[15])); + AOI222_X1_LVT i_0_55 (.A1(n_76), .A2(n_0_99), .B1(n_0_91), .B2(n_45), + .C1(n_14), .C2(n_0_90), .ZN(n_0_55)); + NAND2_X1_LVT i_0_56 (.A1(Illegal), .A2(CurrentPC[14]), .ZN(n_0_56)); + NAND2_X1_LVT i_0_54 (.A1(n_0_55), .A2(n_0_56), .ZN(JumpOrBranchPC[14])); + AOI222_X1_LVT i_0_52 (.A1(n_75), .A2(n_0_99), .B1(n_0_91), .B2(n_44), + .C1(n_13), .C2(n_0_90), .ZN(n_0_53)); + NAND2_X1_LVT i_0_53 (.A1(Illegal), .A2(CurrentPC[13]), .ZN(n_0_54)); + NAND2_X1_LVT i_0_51 (.A1(n_0_53), .A2(n_0_54), .ZN(JumpOrBranchPC[13])); + AOI222_X1_LVT i_0_49 (.A1(n_74), .A2(n_0_99), .B1(n_0_91), .B2(n_43), + .C1(n_12), .C2(n_0_90), .ZN(n_0_51)); + NAND2_X1_LVT i_0_50 (.A1(Illegal), .A2(CurrentPC[12]), .ZN(n_0_52)); + NAND2_X1_LVT i_0_48 (.A1(n_0_51), .A2(n_0_52), .ZN(JumpOrBranchPC[12])); + AOI222_X1_LVT i_0_46 (.A1(n_73), .A2(n_0_99), .B1(n_0_91), .B2(n_42), + .C1(n_11), .C2(n_0_90), .ZN(n_0_49)); + NAND2_X1_LVT i_0_47 (.A1(Illegal), .A2(CurrentPC[11]), .ZN(n_0_50)); + NAND2_X1_LVT i_0_45 (.A1(n_0_49), .A2(n_0_50), .ZN(JumpOrBranchPC[11])); + AOI222_X1_LVT i_0_43 (.A1(n_72), .A2(n_0_99), .B1(n_0_91), .B2(n_41), + .C1(n_10), .C2(n_0_90), .ZN(n_0_47)); + NAND2_X1_LVT i_0_44 (.A1(Illegal), .A2(CurrentPC[10]), .ZN(n_0_48)); + NAND2_X1_LVT i_0_42 (.A1(n_0_47), .A2(n_0_48), .ZN(JumpOrBranchPC[10])); + AOI222_X1_LVT i_0_40 (.A1(n_71), .A2(n_0_99), .B1(n_0_91), .B2(n_40), + .C1(n_9), .C2(n_0_90), .ZN(n_0_45)); + NAND2_X1_LVT i_0_41 (.A1(Illegal), .A2(CurrentPC[9]), .ZN(n_0_46)); + NAND2_X1_LVT i_0_39 (.A1(n_0_45), .A2(n_0_46), .ZN(JumpOrBranchPC[9])); + AOI222_X1_LVT i_0_37 (.A1(n_70), .A2(n_0_99), .B1(n_0_91), .B2(n_39), + .C1(n_8), .C2(n_0_90), .ZN(n_0_43)); + NAND2_X1_LVT i_0_38 (.A1(Illegal), .A2(CurrentPC[8]), .ZN(n_0_44)); + NAND2_X1_LVT i_0_36 (.A1(n_0_43), .A2(n_0_44), .ZN(JumpOrBranchPC[8])); + AOI222_X1_LVT i_0_34 (.A1(n_69), .A2(n_0_99), .B1(n_0_91), .B2(n_38), + .C1(n_7), .C2(n_0_90), .ZN(n_0_41)); + NAND2_X1_LVT i_0_35 (.A1(Illegal), .A2(CurrentPC[7]), .ZN(n_0_42)); + NAND2_X1_LVT i_0_33 (.A1(n_0_41), .A2(n_0_42), .ZN(JumpOrBranchPC[7])); + AOI222_X1_LVT i_0_31 (.A1(n_68), .A2(n_0_99), .B1(n_0_91), .B2(n_37), + .C1(n_6), .C2(n_0_90), .ZN(n_0_39)); + NAND2_X1_LVT i_0_32 (.A1(Illegal), .A2(CurrentPC[6]), .ZN(n_0_40)); + NAND2_X1_LVT i_0_30 (.A1(n_0_39), .A2(n_0_40), .ZN(JumpOrBranchPC[6])); + AOI222_X1_LVT i_0_28 (.A1(n_67), .A2(n_0_99), .B1(n_0_91), .B2(n_36), + .C1(n_5), .C2(n_0_90), .ZN(n_0_37)); + NAND2_X1_LVT i_0_29 (.A1(Illegal), .A2(CurrentPC[5]), .ZN(n_0_38)); + NAND2_X1_LVT i_0_27 (.A1(n_0_37), .A2(n_0_38), .ZN(JumpOrBranchPC[5])); + AOI222_X1_LVT i_0_25 (.A1(n_66), .A2(n_0_99), .B1(n_0_91), .B2(n_35), + .C1(n_4), .C2(n_0_90), .ZN(n_0_35)); + NAND2_X1_LVT i_0_26 (.A1(Illegal), .A2(CurrentPC[4]), .ZN(n_0_36)); + NAND2_X1_LVT i_0_24 (.A1(n_0_35), .A2(n_0_36), .ZN(JumpOrBranchPC[4])); + AOI222_X1_LVT i_0_22 (.A1(n_65), .A2(n_0_99), .B1(n_0_91), .B2(n_34), + .C1(n_3), .C2(n_0_90), .ZN(n_0_33)); + NAND2_X1_LVT i_0_23 (.A1(Illegal), .A2(CurrentPC[3]), .ZN(n_0_34)); + NAND2_X1_LVT i_0_21 (.A1(n_0_33), .A2(n_0_34), .ZN(JumpOrBranchPC[3])); + AOI222_X1_LVT i_0_19 (.A1(n_64), .A2(n_0_99), .B1(n_0_91), .B2(n_33), + .C1(n_2), .C2(n_0_90), .ZN(n_0_31)); + NAND2_X1_LVT i_0_20 (.A1(Illegal), .A2(CurrentPC[2]), .ZN(n_0_32)); + NAND2_X1_LVT i_0_18 (.A1(n_0_31), .A2(n_0_32), .ZN(JumpOrBranchPC[2])); + AOI222_X1_LVT i_0_16 (.A1(n_63), .A2(n_0_99), .B1(n_0_91), .B2(n_32), + .C1(n_1), .C2(n_0_90), .ZN(n_0_29)); + NAND2_X1_LVT i_0_17 (.A1(Illegal), .A2(CurrentPC[1]), .ZN(n_0_30)); + NAND2_X1_LVT i_0_15 (.A1(n_0_29), .A2(n_0_30), .ZN(JumpOrBranchPC[1])); + NOR2_X1_LVT i_0_112 (.A1(n_0_232), .A2(n_0_238), .ZN(n_0_94)); + OAI221_X1_LVT i_0_14 (.A(n_0_94), .B1(n_0_225), .B2(Instruction[2]), .C1( + Instruction[6]), .C2(n_0_239), .ZN(n_0_28)); + AND2_X1_LVT i_0_13 (.A1(n_0_28), .A2(CurrentPC[0]), .ZN(JumpOrBranchPC[0])); + NOR2_X1_LVT i_0_221 (.A1(Instruction[13]), .A2(Instruction[14]), .ZN(n_0_166)); + NOR3_X1_LVT i_0_293 (.A1(n_0_241), .A2(n_0_234), .A3(Instruction[3]), + .ZN(n_0_206)); + AND2_X1_LVT i_0_292 (.A1(n_0_206), .A2(n_0_244), .ZN(n_0_205)); + NOR3_X1_LVT i_0_330 (.A1(n_0_248), .A2(n_0_244), .A3(Instruction[4]), + .ZN(n_0_226)); + AOI21_X1_LVT i_0_121 (.A(n_0_205), .B1(n_0_226), .B2(n_0_237), .ZN(n_0_100)); + AND2_X1_LVT i_0_120 (.A1(Instruction[14]), .A2(n_0_100), .ZN(aluOp[2])); + OAI33_X1_LVT i_0_119 (.A1(n_0_205), .A2(n_0_247), .A3(n_0_224), .B1( + Instruction[2]), .B2(n_0_238), .B3(n_0_225), .ZN(aluOp[1])); + AOI22_X1_LVT i_0_117 (.A1(Instruction[12]), .A2(n_0_100), .B1(n_0_99), + .B2(Instruction[13]), .ZN(n_0_98)); + INV_X1_LVT i_0_116 (.A(n_0_98), .ZN(aluOp[0])); + OR2_X1_LVT i_0_327 (.A1(n_0_238), .A2(n_0_234), .ZN(n_0_223)); + NOR4_X1_LVT i_0_125 (.A1(Instruction[28]), .A2(Instruction[27]), .A3( + Instruction[26]), .A4(Instruction[25]), .ZN(n_0_103)); + INV_X1_LVT i_0_347 (.A(Instruction[30]), .ZN(n_0_242)); + NOR4_X1_LVT i_0_124 (.A1(Instruction[13]), .A2(n_0_242), .A3(Instruction[29]), + .A4(Instruction[31]), .ZN(n_0_102)); + NAND2_X1_LVT i_0_123 (.A1(n_0_103), .A2(n_0_102), .ZN(n_0_101)); + NOR3_X1_LVT i_0_127 (.A1(n_0_244), .A2(Instruction[12]), .A3(Instruction[14]), + .ZN(n_0_105)); + AOI21_X1_LVT i_0_126 (.A(n_0_105), .B1(Instruction[12]), .B2(Instruction[14]), + .ZN(n_0_104)); + NOR4_X1_LVT i_0_122 (.A1(n_0_223), .A2(n_0_101), .A3(n_0_104), .A4( + Instruction[2]), .ZN(aluNegAr)); + OR3_X1_LVT i_0_325 (.A1(n_0_228), .A2(Instruction[4]), .A3(Instruction[6]), + .ZN(n_0_222)); + NOR2_X1_LVT i_0_321 (.A1(n_0_222), .A2(Instruction[5]), .ZN(n_0_221)); + NOR3_X1_LVT i_0_224 (.A1(n_0_224), .A2(n_0_221), .A3(n_0_206), .ZN(n_0_169)); + NOR3_X1_LVT i_0_129 (.A1(n_0_234), .A2(Instruction[3]), .A3(Instruction[5]), + .ZN(n_0_106)); + NOR3_X1_LVT i_0_128 (.A1(n_0_226), .A2(n_0_169), .A3(n_0_106), .ZN(aluBypass)); + AOI22_X1_LVT i_0_223 (.A1(CurrentPC[31]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[31]), .ZN(n_0_168)); + NOR3_X1_LVT i_0_219 (.A1(n_0_247), .A2(n_0_222), .A3(Instruction[5]), + .ZN(n_0_164)); + AOI22_X1_LVT i_0_218 (.A1(RRs1[31]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[31]), .ZN(n_0_163)); + MUX2_X1_LVT i_0_222 (.A(RData[7]), .B(RData[15]), .S(Instruction[12]), + .Z(n_0_167)); + NAND3_X1_LVT i_0_220 (.A1(n_0_221), .A2(n_0_167), .A3(n_0_166), .ZN(n_0_165)); + NAND3_X1_LVT i_0_217 (.A1(n_0_168), .A2(n_0_163), .A3(n_0_165), .ZN(op1[31])); + AOI22_X1_LVT i_0_216 (.A1(RRs1[30]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[30]), .ZN(n_0_162)); + AOI22_X1_LVT i_0_215 (.A1(CurrentPC[30]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[30]), .ZN(n_0_161)); + NAND3_X1_LVT i_0_214 (.A1(n_0_162), .A2(n_0_161), .A3(n_0_165), .ZN(op1[30])); + AOI22_X1_LVT i_0_213 (.A1(RRs1[29]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[29]), .ZN(n_0_160)); + AOI22_X1_LVT i_0_212 (.A1(CurrentPC[29]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[29]), .ZN(n_0_159)); + NAND3_X1_LVT i_0_211 (.A1(n_0_160), .A2(n_0_159), .A3(n_0_165), .ZN(op1[29])); + AOI22_X1_LVT i_0_210 (.A1(RRs1[28]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[28]), .ZN(n_0_158)); + AOI22_X1_LVT i_0_209 (.A1(CurrentPC[28]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[28]), .ZN(n_0_157)); + NAND3_X1_LVT i_0_208 (.A1(n_0_158), .A2(n_0_157), .A3(n_0_165), .ZN(op1[28])); + AOI22_X1_LVT i_0_207 (.A1(RRs1[27]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[27]), .ZN(n_0_156)); + AOI22_X1_LVT i_0_206 (.A1(CurrentPC[27]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[27]), .ZN(n_0_155)); + NAND3_X1_LVT i_0_205 (.A1(n_0_156), .A2(n_0_155), .A3(n_0_165), .ZN(op1[27])); + AOI22_X1_LVT i_0_204 (.A1(RRs1[26]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[26]), .ZN(n_0_154)); + AOI22_X1_LVT i_0_203 (.A1(CurrentPC[26]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[26]), .ZN(n_0_153)); + NAND3_X1_LVT i_0_202 (.A1(n_0_154), .A2(n_0_153), .A3(n_0_165), .ZN(op1[26])); + AOI22_X1_LVT i_0_201 (.A1(RRs1[25]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[25]), .ZN(n_0_152)); + AOI22_X1_LVT i_0_200 (.A1(CurrentPC[25]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[25]), .ZN(n_0_151)); + NAND3_X1_LVT i_0_199 (.A1(n_0_152), .A2(n_0_151), .A3(n_0_165), .ZN(op1[25])); + AOI22_X1_LVT i_0_198 (.A1(RRs1[24]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[24]), .ZN(n_0_150)); + AOI22_X1_LVT i_0_197 (.A1(CurrentPC[24]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[24]), .ZN(n_0_149)); + NAND3_X1_LVT i_0_196 (.A1(n_0_150), .A2(n_0_149), .A3(n_0_165), .ZN(op1[24])); + AOI22_X1_LVT i_0_195 (.A1(RRs1[23]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[23]), .ZN(n_0_148)); + AOI22_X1_LVT i_0_194 (.A1(CurrentPC[23]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[23]), .ZN(n_0_147)); + NAND3_X1_LVT i_0_193 (.A1(n_0_148), .A2(n_0_147), .A3(n_0_165), .ZN(op1[23])); + AOI22_X1_LVT i_0_192 (.A1(RRs1[22]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[22]), .ZN(n_0_146)); + AOI22_X1_LVT i_0_191 (.A1(CurrentPC[22]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[22]), .ZN(n_0_145)); + NAND3_X1_LVT i_0_190 (.A1(n_0_146), .A2(n_0_145), .A3(n_0_165), .ZN(op1[22])); + AOI22_X1_LVT i_0_189 (.A1(RRs1[21]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[21]), .ZN(n_0_144)); + AOI22_X1_LVT i_0_188 (.A1(CurrentPC[21]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[21]), .ZN(n_0_143)); + NAND3_X1_LVT i_0_187 (.A1(n_0_144), .A2(n_0_143), .A3(n_0_165), .ZN(op1[21])); + AOI22_X1_LVT i_0_186 (.A1(RRs1[20]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[20]), .ZN(n_0_142)); + AOI22_X1_LVT i_0_185 (.A1(CurrentPC[20]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[20]), .ZN(n_0_141)); + NAND3_X1_LVT i_0_184 (.A1(n_0_142), .A2(n_0_141), .A3(n_0_165), .ZN(op1[20])); + AOI22_X1_LVT i_0_183 (.A1(RRs1[19]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[19]), .ZN(n_0_140)); + AOI22_X1_LVT i_0_182 (.A1(CurrentPC[19]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[19]), .ZN(n_0_139)); + NAND3_X1_LVT i_0_181 (.A1(n_0_140), .A2(n_0_139), .A3(n_0_165), .ZN(op1[19])); + AOI22_X1_LVT i_0_180 (.A1(RRs1[18]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[18]), .ZN(n_0_138)); + AOI22_X1_LVT i_0_179 (.A1(CurrentPC[18]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[18]), .ZN(n_0_137)); + NAND3_X1_LVT i_0_178 (.A1(n_0_138), .A2(n_0_137), .A3(n_0_165), .ZN(op1[18])); + AOI22_X1_LVT i_0_177 (.A1(RRs1[17]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[17]), .ZN(n_0_136)); + AOI22_X1_LVT i_0_176 (.A1(CurrentPC[17]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[17]), .ZN(n_0_135)); + NAND3_X1_LVT i_0_175 (.A1(n_0_136), .A2(n_0_135), .A3(n_0_165), .ZN(op1[17])); + AOI22_X1_LVT i_0_174 (.A1(RRs1[16]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[16]), .ZN(n_0_134)); + AOI22_X1_LVT i_0_173 (.A1(CurrentPC[16]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[16]), .ZN(n_0_133)); + NAND3_X1_LVT i_0_172 (.A1(n_0_134), .A2(n_0_133), .A3(n_0_165), .ZN(op1[16])); + AOI222_X1_LVT i_0_169 (.A1(CurrentPC[15]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[15]), .C1(n_0_169), .C2(RRs1[15]), .ZN(n_0_130)); + INV_X1_LVT i_0_353 (.A(Instruction[12]), .ZN(n_0_246)); + AOI211_X1_LVT i_0_171 (.A(Instruction[5]), .B(n_0_222), .C1(n_0_247), + .C2(n_0_246), .ZN(n_0_132)); + OAI211_X1_LVT i_0_170 (.A(RData[15]), .B(n_0_132), .C1(Instruction[13]), + .C2(Instruction[14]), .ZN(n_0_131)); + NAND3_X1_LVT i_0_168 (.A1(n_0_130), .A2(n_0_131), .A3(n_0_165), .ZN(op1[15])); + AOI22_X1_LVT i_0_167 (.A1(RRs1[14]), .A2(n_0_169), .B1(n_0_132), .B2( + RData[14]), .ZN(n_0_129)); + AOI22_X1_LVT i_0_166 (.A1(CurrentPC[14]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[14]), .ZN(n_0_128)); + NAND4_X1_LVT i_0_165 (.A1(n_0_221), .A2(n_0_246), .A3(RData[7]), .A4(n_0_166), + .ZN(n_0_127)); + NAND3_X1_LVT i_0_164 (.A1(n_0_129), .A2(n_0_128), .A3(n_0_127), .ZN(op1[14])); + AOI22_X1_LVT i_0_163 (.A1(RRs1[13]), .A2(n_0_169), .B1(n_0_132), .B2( + RData[13]), .ZN(n_0_126)); + AOI22_X1_LVT i_0_162 (.A1(CurrentPC[13]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[13]), .ZN(n_0_125)); + NAND3_X1_LVT i_0_161 (.A1(n_0_126), .A2(n_0_125), .A3(n_0_127), .ZN(op1[13])); + AOI22_X1_LVT i_0_160 (.A1(RRs1[12]), .A2(n_0_169), .B1(n_0_132), .B2( + RData[12]), .ZN(n_0_124)); + AOI22_X1_LVT i_0_159 (.A1(CurrentPC[12]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[12]), .ZN(n_0_123)); + NAND3_X1_LVT i_0_158 (.A1(n_0_124), .A2(n_0_123), .A3(n_0_127), .ZN(op1[12])); + AOI22_X1_LVT i_0_156 (.A1(CurrentPC[11]), .A2(n_0_224), .B1(n_0_132), + .B2(RData[11]), .ZN(n_0_121)); + NAND2_X1_LVT i_0_157 (.A1(RRs1[11]), .A2(n_0_169), .ZN(n_0_122)); + NAND3_X1_LVT i_0_155 (.A1(n_0_121), .A2(n_0_122), .A3(n_0_127), .ZN(op1[11])); + AOI22_X1_LVT i_0_153 (.A1(CurrentPC[10]), .A2(n_0_224), .B1(n_0_132), + .B2(RData[10]), .ZN(n_0_119)); + NAND2_X1_LVT i_0_154 (.A1(RRs1[10]), .A2(n_0_169), .ZN(n_0_120)); + NAND3_X1_LVT i_0_152 (.A1(n_0_119), .A2(n_0_120), .A3(n_0_127), .ZN(op1[10])); + AOI22_X1_LVT i_0_150 (.A1(CurrentPC[9]), .A2(n_0_224), .B1(n_0_132), .B2( + RData[9]), .ZN(n_0_117)); + NAND2_X1_LVT i_0_151 (.A1(RRs1[9]), .A2(n_0_169), .ZN(n_0_118)); + NAND3_X1_LVT i_0_149 (.A1(n_0_117), .A2(n_0_118), .A3(n_0_127), .ZN(op1[9])); + AOI22_X1_LVT i_0_147 (.A1(CurrentPC[8]), .A2(n_0_224), .B1(n_0_132), .B2( + RData[8]), .ZN(n_0_115)); + NAND2_X1_LVT i_0_148 (.A1(RRs1[8]), .A2(n_0_169), .ZN(n_0_116)); + NAND3_X1_LVT i_0_146 (.A1(n_0_115), .A2(n_0_116), .A3(n_0_127), .ZN(op1[8])); + AOI222_X1_LVT i_0_145 (.A1(CurrentPC[7]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[7]), .C1(n_0_169), .C2(RRs1[7]), .ZN(n_0_114)); + INV_X1_LVT i_0_144 (.A(n_0_114), .ZN(op1[7])); + AOI222_X1_LVT i_0_143 (.A1(CurrentPC[6]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[6]), .C1(n_0_169), .C2(RRs1[6]), .ZN(n_0_113)); + INV_X1_LVT i_0_142 (.A(n_0_113), .ZN(op1[6])); + AOI222_X1_LVT i_0_141 (.A1(CurrentPC[5]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[5]), .C1(n_0_169), .C2(RRs1[5]), .ZN(n_0_112)); + INV_X1_LVT i_0_140 (.A(n_0_112), .ZN(op1[5])); + AOI222_X1_LVT i_0_139 (.A1(CurrentPC[4]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[4]), .C1(n_0_169), .C2(RRs1[4]), .ZN(n_0_111)); + INV_X1_LVT i_0_138 (.A(n_0_111), .ZN(op1[4])); + AOI222_X1_LVT i_0_137 (.A1(CurrentPC[3]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[3]), .C1(n_0_169), .C2(RRs1[3]), .ZN(n_0_110)); + INV_X1_LVT i_0_136 (.A(n_0_110), .ZN(op1[3])); + AOI222_X1_LVT i_0_135 (.A1(CurrentPC[2]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[2]), .C1(n_0_169), .C2(RRs1[2]), .ZN(n_0_109)); + INV_X1_LVT i_0_134 (.A(n_0_109), .ZN(op1[2])); + AOI222_X1_LVT i_0_133 (.A1(CurrentPC[1]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[1]), .C1(n_0_169), .C2(RRs1[1]), .ZN(n_0_108)); + INV_X1_LVT i_0_132 (.A(n_0_108), .ZN(op1[1])); + AOI222_X1_LVT i_0_131 (.A1(CurrentPC[0]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[0]), .C1(n_0_169), .C2(RRs1[0]), .ZN(n_0_107)); + INV_X1_LVT i_0_130 (.A(n_0_107), .ZN(op1[0])); + NOR3_X1_LVT i_0_294 (.A1(n_0_223), .A2(Instruction[2]), .A3(Instruction[5]), + .ZN(n_0_207)); + NOR3_X1_LVT i_0_291 (.A1(n_0_224), .A2(n_0_207), .A3(n_0_205), .ZN(n_0_204)); + AOI22_X1_LVT i_0_289 (.A1(CurrentPC[31]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[31]), .ZN(n_0_202)); + NAND2_X1_LVT i_0_290 (.A1(Instruction[31]), .A2(n_0_207), .ZN(n_0_203)); + NAND2_X1_LVT i_0_288 (.A1(n_0_202), .A2(n_0_203), .ZN(op2[31])); + AOI22_X1_LVT i_0_287 (.A1(CurrentPC[30]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[30]), .ZN(n_0_201)); + NAND2_X1_LVT i_0_286 (.A1(n_0_201), .A2(n_0_203), .ZN(op2[30])); + AOI22_X1_LVT i_0_285 (.A1(CurrentPC[29]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[29]), .ZN(n_0_200)); + NAND2_X1_LVT i_0_284 (.A1(n_0_200), .A2(n_0_203), .ZN(op2[29])); + AOI22_X1_LVT i_0_283 (.A1(CurrentPC[28]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[28]), .ZN(n_0_199)); + NAND2_X1_LVT i_0_282 (.A1(n_0_199), .A2(n_0_203), .ZN(op2[28])); + AOI22_X1_LVT i_0_281 (.A1(CurrentPC[27]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[27]), .ZN(n_0_198)); + NAND2_X1_LVT i_0_280 (.A1(n_0_198), .A2(n_0_203), .ZN(op2[27])); + AOI22_X1_LVT i_0_279 (.A1(CurrentPC[26]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[26]), .ZN(n_0_197)); + NAND2_X1_LVT i_0_278 (.A1(n_0_197), .A2(n_0_203), .ZN(op2[26])); + AOI22_X1_LVT i_0_277 (.A1(CurrentPC[25]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[25]), .ZN(n_0_196)); + NAND2_X1_LVT i_0_276 (.A1(n_0_196), .A2(n_0_203), .ZN(op2[25])); + AOI22_X1_LVT i_0_275 (.A1(CurrentPC[24]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[24]), .ZN(n_0_195)); + NAND2_X1_LVT i_0_274 (.A1(n_0_195), .A2(n_0_203), .ZN(op2[24])); + AOI22_X1_LVT i_0_273 (.A1(CurrentPC[23]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[23]), .ZN(n_0_194)); + NAND2_X1_LVT i_0_272 (.A1(n_0_194), .A2(n_0_203), .ZN(op2[23])); + AOI22_X1_LVT i_0_271 (.A1(CurrentPC[22]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[22]), .ZN(n_0_193)); + NAND2_X1_LVT i_0_270 (.A1(n_0_193), .A2(n_0_203), .ZN(op2[22])); + AOI22_X1_LVT i_0_269 (.A1(CurrentPC[21]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[21]), .ZN(n_0_192)); + NAND2_X1_LVT i_0_268 (.A1(n_0_192), .A2(n_0_203), .ZN(op2[21])); + AOI22_X1_LVT i_0_267 (.A1(CurrentPC[20]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[20]), .ZN(n_0_191)); + NAND2_X1_LVT i_0_266 (.A1(n_0_191), .A2(n_0_203), .ZN(op2[20])); + AOI22_X1_LVT i_0_265 (.A1(CurrentPC[19]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[19]), .ZN(n_0_190)); + NAND2_X1_LVT i_0_264 (.A1(n_0_190), .A2(n_0_203), .ZN(op2[19])); + AOI22_X1_LVT i_0_263 (.A1(CurrentPC[18]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[18]), .ZN(n_0_189)); + NAND2_X1_LVT i_0_262 (.A1(n_0_189), .A2(n_0_203), .ZN(op2[18])); + AOI22_X1_LVT i_0_261 (.A1(CurrentPC[17]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[17]), .ZN(n_0_188)); + NAND2_X1_LVT i_0_260 (.A1(n_0_188), .A2(n_0_203), .ZN(op2[17])); + AOI22_X1_LVT i_0_259 (.A1(CurrentPC[16]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[16]), .ZN(n_0_187)); + NAND2_X1_LVT i_0_258 (.A1(n_0_187), .A2(n_0_203), .ZN(op2[16])); + AOI22_X1_LVT i_0_257 (.A1(CurrentPC[15]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[15]), .ZN(n_0_186)); + NAND2_X1_LVT i_0_256 (.A1(n_0_186), .A2(n_0_203), .ZN(op2[15])); + AOI22_X1_LVT i_0_255 (.A1(CurrentPC[14]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[14]), .ZN(n_0_185)); + NAND2_X1_LVT i_0_254 (.A1(n_0_185), .A2(n_0_203), .ZN(op2[14])); + AOI22_X1_LVT i_0_253 (.A1(CurrentPC[13]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[13]), .ZN(n_0_184)); + NAND2_X1_LVT i_0_252 (.A1(n_0_184), .A2(n_0_203), .ZN(op2[13])); + AOI22_X1_LVT i_0_251 (.A1(CurrentPC[12]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[12]), .ZN(n_0_183)); + NAND2_X1_LVT i_0_250 (.A1(n_0_183), .A2(n_0_203), .ZN(op2[12])); + AOI22_X1_LVT i_0_249 (.A1(CurrentPC[11]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[11]), .ZN(n_0_182)); + NAND2_X1_LVT i_0_248 (.A1(n_0_182), .A2(n_0_203), .ZN(op2[11])); + AOI222_X1_LVT i_0_247 (.A1(Instruction[30]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[10]), .C1(n_0_204), .C2(RRs2[10]), .ZN(n_0_181)); + INV_X1_LVT i_0_246 (.A(n_0_181), .ZN(op2[10])); + AOI222_X1_LVT i_0_245 (.A1(Instruction[29]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[9]), .C1(n_0_204), .C2(RRs2[9]), .ZN(n_0_180)); + INV_X1_LVT i_0_244 (.A(n_0_180), .ZN(op2[9])); + AOI222_X1_LVT i_0_243 (.A1(Instruction[28]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[8]), .C1(n_0_204), .C2(RRs2[8]), .ZN(n_0_179)); + INV_X1_LVT i_0_242 (.A(n_0_179), .ZN(op2[8])); + AOI222_X1_LVT i_0_241 (.A1(Instruction[27]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[7]), .C1(n_0_204), .C2(RRs2[7]), .ZN(n_0_178)); + INV_X1_LVT i_0_240 (.A(n_0_178), .ZN(op2[7])); + AOI222_X1_LVT i_0_239 (.A1(Instruction[26]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[6]), .C1(n_0_204), .C2(RRs2[6]), .ZN(n_0_177)); + INV_X1_LVT i_0_238 (.A(n_0_177), .ZN(op2[6])); + AOI222_X1_LVT i_0_237 (.A1(Instruction[25]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[5]), .C1(n_0_204), .C2(RRs2[5]), .ZN(n_0_176)); + INV_X1_LVT i_0_236 (.A(n_0_176), .ZN(op2[5])); + AOI222_X1_LVT i_0_235 (.A1(Instruction[24]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[4]), .C1(n_0_204), .C2(RRs2[4]), .ZN(n_0_175)); + INV_X1_LVT i_0_234 (.A(n_0_175), .ZN(op2[4])); + AOI222_X1_LVT i_0_233 (.A1(Instruction[23]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[3]), .C1(n_0_204), .C2(RRs2[3]), .ZN(n_0_174)); + INV_X1_LVT i_0_232 (.A(n_0_174), .ZN(op2[3])); + AOI22_X1_LVT i_0_230 (.A1(Instruction[22]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[2]), .ZN(n_0_172)); + OAI21_X1_LVT i_0_231 (.A(RRs2[2]), .B1(n_0_223), .B2(Instruction[5]), + .ZN(n_0_173)); + NAND3_X1_LVT i_0_229 (.A1(n_0_172), .A2(n_0_173), .A3(n_0_249), .ZN(op2[2])); + AOI222_X1_LVT i_0_228 (.A1(Instruction[21]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[1]), .C1(n_0_204), .C2(RRs2[1]), .ZN(n_0_171)); + INV_X1_LVT i_0_227 (.A(n_0_171), .ZN(op2[1])); + AOI222_X1_LVT i_0_226 (.A1(Instruction[20]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[0]), .C1(n_0_204), .C2(RRs2[0]), .ZN(n_0_170)); + INV_X1_LVT i_0_225 (.A(n_0_170), .ZN(op2[0])); + alu theALU (.aluOp(aluOp), .aluNegAr(aluNegAr), .aluBypass(aluBypass), + .op1(op1), .op2(op2), .result(WRd), .eqFlag(eqFlag)); + XNOR2_X1_LVT i_0_115 (.A(Instruction[12]), .B(eqFlag), .ZN(n_0_97)); + XNOR2_X1_LVT i_0_114 (.A(Instruction[12]), .B(WRd[0]), .ZN(n_0_96)); + AOI22_X1_LVT i_0_113 (.A1(n_0_166), .A2(n_0_97), .B1(n_0_96), .B2( + Instruction[14]), .ZN(n_0_95)); + AOI22_X1_LVT i_0_111 (.A1(Instruction[6]), .A2(n_0_95), .B1(Instruction[2]), + .B2(n_0_245), .ZN(n_0_93)); + NAND2_X1_LVT i_0_110 (.A1(n_0_94), .A2(n_0_93), .ZN(JumpOrBranch)); + INV_X1_LVT i_0_349 (.A(Instruction[31]), .ZN(n_0_0)); + INV_X1_LVT i_0_348 (.A(RRs1[12]), .ZN(n_0_1)); + HA_X1_LVT i_0_0 (.A(Instruction[7]), .B(RRs1[0]), .CO(n_0_2), .S(n_0_15)); + FA_X1_LVT i_0_1 (.A(Instruction[8]), .B(RRs1[1]), .CI(n_0_2), .CO(n_0_3), + .S(n_0_16)); + FA_X1_LVT i_0_2 (.A(Instruction[9]), .B(RRs1[2]), .CI(n_0_3), .CO(n_0_4), + .S(n_0_17)); + FA_X1_LVT i_0_3 (.A(Instruction[10]), .B(RRs1[3]), .CI(n_0_4), .CO(n_0_5), + .S(n_0_18)); + FA_X1_LVT i_0_4 (.A(Instruction[11]), .B(RRs1[4]), .CI(n_0_5), .CO(n_0_6), + .S(n_0_19)); + FA_X1_LVT i_0_5 (.A(Instruction[25]), .B(RRs1[5]), .CI(n_0_6), .CO(n_0_7), + .S(n_0_20)); + FA_X1_LVT i_0_6 (.A(Instruction[26]), .B(RRs1[6]), .CI(n_0_7), .CO(n_0_8), + .S(n_0_21)); + FA_X1_LVT i_0_7 (.A(Instruction[27]), .B(RRs1[7]), .CI(n_0_8), .CO(n_0_9), + .S(n_0_22)); + FA_X1_LVT i_0_8 (.A(Instruction[28]), .B(RRs1[8]), .CI(n_0_9), .CO(n_0_10), + .S(n_0_23)); + FA_X1_LVT i_0_9 (.A(Instruction[29]), .B(RRs1[9]), .CI(n_0_10), .CO(n_0_11), + .S(n_0_24)); + FA_X1_LVT i_0_10 (.A(Instruction[30]), .B(RRs1[10]), .CI(n_0_11), .CO(n_0_12), + .S(n_0_25)); + FA_X1_LVT i_0_11 (.A(RRs1[11]), .B(Instruction[31]), .CI(n_0_12), .CO(n_0_13), + .S(n_0_26)); + FA_X1_LVT i_0_12 (.A(n_0_0), .B(n_0_1), .CI(n_0_13), .CO(n_0_14), .S(n_0_27)); + NOR2_X1_LVT i_0_322 (.A1(n_0_244), .A2(n_0_222), .ZN(WrMem)); + AOI22_X1_LVT i_0_320 (.A1(n_0_27), .A2(WrMem), .B1(n_0_221), .B2(n_12), + .ZN(n_0_220)); + INV_X1_LVT i_0_319 (.A(n_0_220), .ZN(DAddr[12])); + AOI22_X1_LVT i_0_318 (.A1(n_0_26), .A2(WrMem), .B1(n_0_221), .B2(n_11), + .ZN(n_0_219)); + INV_X1_LVT i_0_317 (.A(n_0_219), .ZN(DAddr[11])); + AOI22_X1_LVT i_0_316 (.A1(n_0_25), .A2(WrMem), .B1(n_0_221), .B2(n_10), + .ZN(n_0_218)); + INV_X1_LVT i_0_315 (.A(n_0_218), .ZN(DAddr[10])); + AOI22_X1_LVT i_0_314 (.A1(n_0_24), .A2(WrMem), .B1(n_0_221), .B2(n_9), + .ZN(n_0_217)); + INV_X1_LVT i_0_313 (.A(n_0_217), .ZN(DAddr[9])); + AOI22_X1_LVT i_0_312 (.A1(n_0_23), .A2(WrMem), .B1(n_0_221), .B2(n_8), + .ZN(n_0_216)); + INV_X1_LVT i_0_311 (.A(n_0_216), .ZN(DAddr[8])); + AOI22_X1_LVT i_0_310 (.A1(n_0_22), .A2(WrMem), .B1(n_0_221), .B2(n_7), + .ZN(n_0_215)); + INV_X1_LVT i_0_309 (.A(n_0_215), .ZN(DAddr[7])); + AOI22_X1_LVT i_0_308 (.A1(n_0_21), .A2(WrMem), .B1(n_0_221), .B2(n_6), + .ZN(n_0_214)); + INV_X1_LVT i_0_307 (.A(n_0_214), .ZN(DAddr[6])); + AOI22_X1_LVT i_0_306 (.A1(n_0_20), .A2(WrMem), .B1(n_0_221), .B2(n_5), + .ZN(n_0_213)); + INV_X1_LVT i_0_305 (.A(n_0_213), .ZN(DAddr[5])); + AOI22_X1_LVT i_0_304 (.A1(n_0_19), .A2(WrMem), .B1(n_0_221), .B2(n_4), + .ZN(n_0_212)); + INV_X1_LVT i_0_303 (.A(n_0_212), .ZN(DAddr[4])); + AOI22_X1_LVT i_0_302 (.A1(n_0_18), .A2(WrMem), .B1(n_0_221), .B2(n_3), + .ZN(n_0_211)); + INV_X1_LVT i_0_301 (.A(n_0_211), .ZN(DAddr[3])); + AOI22_X1_LVT i_0_300 (.A1(n_0_17), .A2(WrMem), .B1(n_0_221), .B2(n_2), + .ZN(n_0_210)); + INV_X1_LVT i_0_299 (.A(n_0_210), .ZN(DAddr[2])); + AOI22_X1_LVT i_0_298 (.A1(n_0_16), .A2(WrMem), .B1(n_0_221), .B2(n_1), + .ZN(n_0_209)); + INV_X1_LVT i_0_297 (.A(n_0_209), .ZN(DAddr[1])); + AOI22_X1_LVT i_0_296 (.A1(n_0_15), .A2(WrMem), .B1(n_0_221), .B2(n_0), + .ZN(n_0_208)); + INV_X1_LVT i_0_295 (.A(n_0_208), .ZN(DAddr[0])); + OR2_X1_LVT i_0_324 (.A1(n_0_222), .A2(Instruction[13]), .ZN(DWidth[1])); + NOR2_X1_LVT i_0_323 (.A1(n_0_246), .A2(n_0_222), .ZN(DWidth[0])); + NAND3_X1_LVT i_0_331 (.A1(n_0_248), .A2(n_0_244), .A3(n_0_236), .ZN(n_0_227)); + OAI211_X1_LVT i_0_326 (.A(n_0_249), .B(n_0_223), .C1(n_0_228), .C2(n_0_227), + .ZN(WrReg)); +endmodule + +module cpu(led, btn, clk_25mhz, scan_en, SI_1, SO_1, SI_2, SO_2, SI_3, SO_3, + SI_4, SO_4); + output [7:0]led; + input [6:0]btn; + input clk_25mhz; + input scan_en; + input SI_1; + output SO_1; + input SI_2; + output SO_2; + input SI_3; + output SO_3; + input SI_4; + output SO_4; + + wire [31:0]Instruction; + wire [31:0]RData; + wire [31:0]RRs2; + wire [31:0]RRs1; + wire WrReg; + wire [31:0]WRd; + wire [1:0]DWidth; + wire [31:0]DAddr; + wire JumpOrBranch; + wire [31:0]JumpOrBranchPC; + wire thePC_n_1; + wire thePC_i_0_n_0; + wire thePC_n_2; + wire thePC_i_0_n_1; + wire thePC_n_3; + wire thePC_i_0_n_2; + wire thePC_n_4; + wire thePC_i_0_n_3; + wire thePC_n_5; + wire thePC_i_0_n_4; + wire thePC_n_6; + wire thePC_i_0_n_5; + wire thePC_n_7; + wire thePC_i_0_n_6; + wire thePC_n_8; + wire thePC_i_0_n_7; + wire thePC_n_9; + wire thePC_i_0_n_8; + wire thePC_n_10; + wire thePC_i_0_n_9; + wire thePC_n_11; + wire thePC_i_0_n_10; + wire thePC_n_12; + wire thePC_i_0_n_11; + wire thePC_n_13; + wire thePC_i_0_n_12; + wire thePC_n_14; + wire thePC_i_0_n_13; + wire thePC_n_15; + wire thePC_i_0_n_14; + wire thePC_n_16; + wire thePC_i_0_n_15; + wire thePC_n_17; + wire thePC_i_0_n_16; + wire thePC_n_18; + wire thePC_i_0_n_17; + wire thePC_n_19; + wire thePC_i_0_n_18; + wire thePC_n_20; + wire thePC_i_0_n_19; + wire thePC_n_21; + wire thePC_i_0_n_20; + wire thePC_n_22; + wire thePC_i_0_n_21; + wire thePC_n_23; + wire thePC_i_0_n_22; + wire thePC_n_24; + wire thePC_i_0_n_23; + wire thePC_n_25; + wire thePC_i_0_n_24; + wire thePC_n_26; + wire thePC_i_0_n_25; + wire thePC_n_27; + wire thePC_i_0_n_26; + wire thePC_n_28; + wire thePC_i_0_n_27; + wire thePC_n_29; + wire thePC_n_0; + wire [31:0]CurrentPC; + wire thePC_n_30; + wire n_0_0_0; + wire thePC_n_31; + wire n_0_0_1; + wire thePC_n_32; + wire thePC_n_33; + wire thePC_n_34; + wire thePC_n_35; + wire thePC_n_36; + wire thePC_n_37; + wire thePC_n_38; + wire thePC_n_39; + wire thePC_n_40; + wire thePC_n_41; + wire thePC_n_42; + wire thePC_n_43; + wire n_0_0_2; + wire thePC_n_44; + wire n_0_0_3; + wire thePC_n_45; + wire n_0_0_4; + wire thePC_n_46; + wire n_0_0_5; + wire thePC_n_47; + wire n_0_0_6; + wire thePC_n_48; + wire n_0_0_7; + wire thePC_n_49; + wire n_0_0_8; + wire thePC_n_50; + wire n_0_0_9; + wire thePC_n_51; + wire n_0_0_10; + wire thePC_n_52; + wire n_0_0_11; + wire thePC_n_53; + wire n_0_0_12; + wire thePC_n_54; + wire n_0_0_13; + wire thePC_n_55; + wire n_0_0_14; + wire thePC_n_56; + wire n_0_0_15; + wire thePC_n_57; + wire n_0_0_16; + wire thePC_n_58; + wire n_0_0_17; + wire thePC_n_59; + wire n_0_0_18; + wire thePC_n_60; + wire n_0_0_19; + wire thePC_n_61; + wire n_0_0_20; + wire n_0_0_21; + wire n_0_0_22; + wire [31:0]NextPC; + wire reset; + + AND2_X1_LVT i_0_0_54 (.A1(JumpOrBranch), .A2(btn[0]), .ZN(n_0_0_22)); + INV_X1_LVT i_0_0_66 (.A(btn[0]), .ZN(reset)); + NOR2_X1_LVT i_0_0_53 (.A1(reset), .A2(JumpOrBranch), .ZN(n_0_0_21)); + AOI22_X1_LVT i_0_0_50 (.A1(JumpOrBranchPC[30]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_28), .ZN(n_0_0_19)); + INV_X1_LVT i_0_0_49 (.A(n_0_0_19), .ZN(thePC_n_60)); + SDFF_X1_LVT \thePC_CurrentPC_reg[30] (.D(thePC_n_60), .SE(1'b0), .SI( + CurrentPC[30]), .CK(clk_25mhz), .Q(CurrentPC[30]), .QN()); + AOI22_X1_LVT i_0_0_48 (.A1(JumpOrBranchPC[29]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_27), .ZN(n_0_0_18)); + INV_X1_LVT i_0_0_47 (.A(n_0_0_18), .ZN(thePC_n_59)); + SDFF_X1_LVT \thePC_CurrentPC_reg[29] (.D(thePC_n_59), .SE(1'b0), .SI( + CurrentPC[29]), .CK(clk_25mhz), .Q(CurrentPC[29]), .QN()); + AOI22_X1_LVT i_0_0_46 (.A1(JumpOrBranchPC[28]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_26), .ZN(n_0_0_17)); + INV_X1_LVT i_0_0_45 (.A(n_0_0_17), .ZN(thePC_n_58)); + SDFF_X1_LVT \thePC_CurrentPC_reg[28] (.D(thePC_n_58), .SE(1'b0), .SI( + CurrentPC[28]), .CK(clk_25mhz), .Q(CurrentPC[28]), .QN()); + AOI22_X1_LVT i_0_0_44 (.A1(JumpOrBranchPC[27]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_25), .ZN(n_0_0_16)); + INV_X1_LVT i_0_0_43 (.A(n_0_0_16), .ZN(thePC_n_57)); + SDFF_X1_LVT \thePC_CurrentPC_reg[27] (.D(thePC_n_57), .SE(1'b0), .SI( + CurrentPC[27]), .CK(clk_25mhz), .Q(CurrentPC[27]), .QN()); + AOI22_X1_LVT i_0_0_42 (.A1(JumpOrBranchPC[26]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_24), .ZN(n_0_0_15)); + INV_X1_LVT i_0_0_41 (.A(n_0_0_15), .ZN(thePC_n_56)); + SDFF_X1_LVT \thePC_CurrentPC_reg[26] (.D(thePC_n_56), .SE(1'b0), .SI( + CurrentPC[26]), .CK(clk_25mhz), .Q(CurrentPC[26]), .QN()); + AOI22_X1_LVT i_0_0_40 (.A1(JumpOrBranchPC[25]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_23), .ZN(n_0_0_14)); + INV_X1_LVT i_0_0_39 (.A(n_0_0_14), .ZN(thePC_n_55)); + SDFF_X1_LVT \thePC_CurrentPC_reg[25] (.D(thePC_n_55), .SE(1'b0), .SI( + CurrentPC[25]), .CK(clk_25mhz), .Q(CurrentPC[25]), .QN()); + AOI22_X1_LVT i_0_0_38 (.A1(JumpOrBranchPC[24]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_22), .ZN(n_0_0_13)); + INV_X1_LVT i_0_0_37 (.A(n_0_0_13), .ZN(thePC_n_54)); + SDFF_X1_LVT \thePC_CurrentPC_reg[24] (.D(thePC_n_54), .SE(1'b0), .SI( + CurrentPC[24]), .CK(clk_25mhz), .Q(CurrentPC[24]), .QN()); + AOI22_X1_LVT i_0_0_36 (.A1(JumpOrBranchPC[23]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_21), .ZN(n_0_0_12)); + INV_X1_LVT i_0_0_35 (.A(n_0_0_12), .ZN(thePC_n_53)); + SDFF_X1_LVT \thePC_CurrentPC_reg[23] (.D(thePC_n_53), .SE(1'b0), .SI( + CurrentPC[23]), .CK(clk_25mhz), .Q(CurrentPC[23]), .QN()); + AOI22_X1_LVT i_0_0_34 (.A1(JumpOrBranchPC[22]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_20), .ZN(n_0_0_11)); + INV_X1_LVT i_0_0_33 (.A(n_0_0_11), .ZN(thePC_n_52)); + SDFF_X1_LVT \thePC_CurrentPC_reg[22] (.D(thePC_n_52), .SE(1'b0), .SI( + CurrentPC[22]), .CK(clk_25mhz), .Q(CurrentPC[22]), .QN()); + AOI22_X1_LVT i_0_0_32 (.A1(JumpOrBranchPC[21]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_19), .ZN(n_0_0_10)); + INV_X1_LVT i_0_0_31 (.A(n_0_0_10), .ZN(thePC_n_51)); + SDFF_X1_LVT \thePC_CurrentPC_reg[21] (.D(thePC_n_51), .SE(1'b0), .SI( + CurrentPC[21]), .CK(clk_25mhz), .Q(CurrentPC[21]), .QN()); + AOI22_X1_LVT i_0_0_30 (.A1(JumpOrBranchPC[20]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_18), .ZN(n_0_0_9)); + INV_X1_LVT i_0_0_29 (.A(n_0_0_9), .ZN(thePC_n_50)); + SDFF_X1_LVT \thePC_CurrentPC_reg[20] (.D(thePC_n_50), .SE(1'b0), .SI( + CurrentPC[20]), .CK(clk_25mhz), .Q(CurrentPC[20]), .QN()); + AOI22_X1_LVT i_0_0_28 (.A1(JumpOrBranchPC[19]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_17), .ZN(n_0_0_8)); + INV_X1_LVT i_0_0_27 (.A(n_0_0_8), .ZN(thePC_n_49)); + SDFF_X1_LVT \thePC_CurrentPC_reg[19] (.D(thePC_n_49), .SE(1'b0), .SI( + CurrentPC[19]), .CK(clk_25mhz), .Q(CurrentPC[19]), .QN()); + AOI22_X1_LVT i_0_0_26 (.A1(JumpOrBranchPC[18]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_16), .ZN(n_0_0_7)); + INV_X1_LVT i_0_0_25 (.A(n_0_0_7), .ZN(thePC_n_48)); + SDFF_X1_LVT \thePC_CurrentPC_reg[18] (.D(thePC_n_48), .SE(1'b0), .SI( + CurrentPC[18]), .CK(clk_25mhz), .Q(CurrentPC[18]), .QN()); + AOI22_X1_LVT i_0_0_24 (.A1(JumpOrBranchPC[17]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_15), .ZN(n_0_0_6)); + INV_X1_LVT i_0_0_23 (.A(n_0_0_6), .ZN(thePC_n_47)); + SDFF_X1_LVT \thePC_CurrentPC_reg[17] (.D(thePC_n_47), .SE(1'b0), .SI( + CurrentPC[17]), .CK(clk_25mhz), .Q(CurrentPC[17]), .QN()); + AOI22_X1_LVT i_0_0_22 (.A1(JumpOrBranchPC[16]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_14), .ZN(n_0_0_5)); + INV_X1_LVT i_0_0_21 (.A(n_0_0_5), .ZN(thePC_n_46)); + SDFF_X1_LVT \thePC_CurrentPC_reg[16] (.D(thePC_n_46), .SE(1'b0), .SI( + CurrentPC[16]), .CK(clk_25mhz), .Q(CurrentPC[16]), .QN()); + AOI22_X1_LVT i_0_0_20 (.A1(JumpOrBranchPC[15]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_13), .ZN(n_0_0_4)); + INV_X1_LVT i_0_0_19 (.A(n_0_0_4), .ZN(thePC_n_45)); + SDFF_X1_LVT \thePC_CurrentPC_reg[15] (.D(thePC_n_45), .SE(1'b0), .SI( + CurrentPC[15]), .CK(clk_25mhz), .Q(CurrentPC[15]), .QN()); + AOI22_X1_LVT i_0_0_18 (.A1(JumpOrBranchPC[14]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_12), .ZN(n_0_0_3)); + INV_X1_LVT i_0_0_17 (.A(n_0_0_3), .ZN(thePC_n_44)); + SDFF_X1_LVT \thePC_CurrentPC_reg[14] (.D(thePC_n_44), .SE(1'b0), .SI( + CurrentPC[14]), .CK(clk_25mhz), .Q(CurrentPC[14]), .QN()); + AOI22_X1_LVT i_0_0_16 (.A1(JumpOrBranchPC[13]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_11), .ZN(n_0_0_2)); + INV_X1_LVT i_0_0_15 (.A(n_0_0_2), .ZN(thePC_n_43)); + SDFF_X1_LVT \thePC_CurrentPC_reg[13] (.D(thePC_n_43), .SE(1'b0), .SI( + CurrentPC[13]), .CK(clk_25mhz), .Q(CurrentPC[13]), .QN()); + MUX2_X1_LVT i_0_0_65 (.A(thePC_n_10), .B(JumpOrBranchPC[12]), .S(JumpOrBranch), + .Z(NextPC[12])); + AND2_X1_LVT i_0_0_14 (.A1(NextPC[12]), .A2(btn[0]), .ZN(thePC_n_42)); + SDFF_X1_LVT \thePC_CurrentPC_reg[12] (.D(thePC_n_42), .SE(1'b0), .SI( + CurrentPC[12]), .CK(clk_25mhz), .Q(CurrentPC[12]), .QN()); + MUX2_X1_LVT i_0_0_64 (.A(thePC_n_9), .B(JumpOrBranchPC[11]), .S(JumpOrBranch), + .Z(NextPC[11])); + AND2_X1_LVT i_0_0_13 (.A1(NextPC[11]), .A2(btn[0]), .ZN(thePC_n_41)); + SDFF_X1_LVT \thePC_CurrentPC_reg[11] (.D(thePC_n_41), .SE(1'b0), .SI( + CurrentPC[11]), .CK(clk_25mhz), .Q(CurrentPC[11]), .QN()); + MUX2_X1_LVT i_0_0_63 (.A(thePC_n_8), .B(JumpOrBranchPC[10]), .S(JumpOrBranch), + .Z(NextPC[10])); + AND2_X1_LVT i_0_0_12 (.A1(NextPC[10]), .A2(btn[0]), .ZN(thePC_n_40)); + SDFF_X1_LVT \thePC_CurrentPC_reg[10] (.D(thePC_n_40), .SE(1'b0), .SI( + CurrentPC[10]), .CK(clk_25mhz), .Q(CurrentPC[10]), .QN()); + MUX2_X1_LVT i_0_0_62 (.A(thePC_n_7), .B(JumpOrBranchPC[9]), .S(JumpOrBranch), + .Z(NextPC[9])); + AND2_X1_LVT i_0_0_11 (.A1(NextPC[9]), .A2(btn[0]), .ZN(thePC_n_39)); + SDFF_X1_LVT \thePC_CurrentPC_reg[9] (.D(thePC_n_39), .SE(1'b0), .SI( + CurrentPC[9]), .CK(clk_25mhz), .Q(CurrentPC[9]), .QN()); + MUX2_X1_LVT i_0_0_61 (.A(thePC_n_6), .B(JumpOrBranchPC[8]), .S(JumpOrBranch), + .Z(NextPC[8])); + AND2_X1_LVT i_0_0_10 (.A1(NextPC[8]), .A2(btn[0]), .ZN(thePC_n_38)); + SDFF_X1_LVT \thePC_CurrentPC_reg[8] (.D(thePC_n_38), .SE(1'b0), .SI( + CurrentPC[8]), .CK(clk_25mhz), .Q(CurrentPC[8]), .QN()); + AND2_X1_LVT i_0_0_9 (.A1(led[7]), .A2(btn[0]), .ZN(thePC_n_37)); + SDFF_X1_LVT \thePC_CurrentPC_reg[7] (.D(thePC_n_37), .SE(1'b0), .SI( + CurrentPC[7]), .CK(clk_25mhz), .Q(CurrentPC[7]), .QN()); + MUX2_X1_LVT i_0_0_59 (.A(thePC_n_4), .B(JumpOrBranchPC[6]), .S(JumpOrBranch), + .Z(led[6])); + AND2_X1_LVT i_0_0_8 (.A1(led[6]), .A2(btn[0]), .ZN(thePC_n_36)); + SDFF_X1_LVT \thePC_CurrentPC_reg[6] (.D(thePC_n_36), .SE(1'b0), .SI( + CurrentPC[6]), .CK(clk_25mhz), .Q(CurrentPC[6]), .QN()); + MUX2_X1_LVT i_0_0_58 (.A(thePC_n_3), .B(JumpOrBranchPC[5]), .S(JumpOrBranch), + .Z(led[5])); + AND2_X1_LVT i_0_0_7 (.A1(led[5]), .A2(btn[0]), .ZN(thePC_n_35)); + SDFF_X1_LVT \thePC_CurrentPC_reg[5] (.D(thePC_n_35), .SE(1'b0), .SI( + CurrentPC[5]), .CK(clk_25mhz), .Q(CurrentPC[5]), .QN()); + MUX2_X1_LVT i_0_0_57 (.A(thePC_n_2), .B(JumpOrBranchPC[4]), .S(JumpOrBranch), + .Z(led[4])); + AND2_X1_LVT i_0_0_6 (.A1(led[4]), .A2(btn[0]), .ZN(thePC_n_34)); + SDFF_X1_LVT \thePC_CurrentPC_reg[4] (.D(thePC_n_34), .SE(1'b0), .SI( + CurrentPC[4]), .CK(clk_25mhz), .Q(CurrentPC[4]), .QN()); + MUX2_X1_LVT i_0_0_56 (.A(thePC_n_1), .B(JumpOrBranchPC[3]), .S(JumpOrBranch), + .Z(led[3])); + AND2_X1_LVT i_0_0_5 (.A1(led[3]), .A2(btn[0]), .ZN(thePC_n_33)); + SDFF_X1_LVT \thePC_CurrentPC_reg[3] (.D(thePC_n_33), .SE(1'b0), .SI( + CurrentPC[3]), .CK(clk_25mhz), .Q(CurrentPC[3]), .QN()); + INV_X1_LVT thePC_i_0_29 (.A(CurrentPC[2]), .ZN(thePC_n_0)); + MUX2_X1_LVT i_0_0_55 (.A(thePC_n_0), .B(JumpOrBranchPC[2]), .S(JumpOrBranch), + .Z(led[2])); + AND2_X1_LVT i_0_0_4 (.A1(led[2]), .A2(btn[0]), .ZN(thePC_n_32)); + SDFF_X1_LVT \thePC_CurrentPC_reg[2] (.D(thePC_n_32), .SE(1'b0), .SI( + CurrentPC[2]), .CK(clk_25mhz), .Q(CurrentPC[2]), .QN()); + HA_X1_LVT thePC_i_0_0 (.A(CurrentPC[3]), .B(CurrentPC[2]), .CO(thePC_i_0_n_0), + .S(thePC_n_1)); + HA_X1_LVT thePC_i_0_1 (.A(CurrentPC[4]), .B(thePC_i_0_n_0), .CO(thePC_i_0_n_1), + .S(thePC_n_2)); + HA_X1_LVT thePC_i_0_2 (.A(CurrentPC[5]), .B(thePC_i_0_n_1), .CO(thePC_i_0_n_2), + .S(thePC_n_3)); + HA_X1_LVT thePC_i_0_3 (.A(CurrentPC[6]), .B(thePC_i_0_n_2), .CO(thePC_i_0_n_3), + .S(thePC_n_4)); + HA_X1_LVT thePC_i_0_4 (.A(CurrentPC[7]), .B(thePC_i_0_n_3), .CO(thePC_i_0_n_4), + .S(thePC_n_5)); + HA_X1_LVT thePC_i_0_5 (.A(CurrentPC[8]), .B(thePC_i_0_n_4), .CO(thePC_i_0_n_5), + .S(thePC_n_6)); + HA_X1_LVT thePC_i_0_6 (.A(CurrentPC[9]), .B(thePC_i_0_n_5), .CO(thePC_i_0_n_6), + .S(thePC_n_7)); + HA_X1_LVT thePC_i_0_7 (.A(CurrentPC[10]), .B(thePC_i_0_n_6), .CO( + thePC_i_0_n_7), .S(thePC_n_8)); + HA_X1_LVT thePC_i_0_8 (.A(CurrentPC[11]), .B(thePC_i_0_n_7), .CO( + thePC_i_0_n_8), .S(thePC_n_9)); + HA_X1_LVT thePC_i_0_9 (.A(CurrentPC[12]), .B(thePC_i_0_n_8), .CO( + thePC_i_0_n_9), .S(thePC_n_10)); + HA_X1_LVT thePC_i_0_11 (.A(CurrentPC[13]), .B(thePC_i_0_n_9), .CO( + thePC_i_0_n_10), .S(thePC_n_11)); + HA_X1_LVT thePC_i_0_12 (.A(CurrentPC[14]), .B(thePC_i_0_n_10), .CO( + thePC_i_0_n_11), .S(thePC_n_12)); + HA_X1_LVT thePC_i_0_13 (.A(CurrentPC[15]), .B(thePC_i_0_n_11), .CO( + thePC_i_0_n_12), .S(thePC_n_13)); + HA_X1_LVT thePC_i_0_14 (.A(CurrentPC[16]), .B(thePC_i_0_n_12), .CO( + thePC_i_0_n_13), .S(thePC_n_14)); + HA_X1_LVT thePC_i_0_15 (.A(CurrentPC[17]), .B(thePC_i_0_n_13), .CO( + thePC_i_0_n_14), .S(thePC_n_15)); + HA_X1_LVT thePC_i_0_16 (.A(CurrentPC[18]), .B(thePC_i_0_n_14), .CO( + thePC_i_0_n_15), .S(thePC_n_16)); + HA_X1_LVT thePC_i_0_17 (.A(CurrentPC[19]), .B(thePC_i_0_n_15), .CO( + thePC_i_0_n_16), .S(thePC_n_17)); + HA_X1_LVT thePC_i_0_10 (.A(CurrentPC[20]), .B(thePC_i_0_n_16), .CO( + thePC_i_0_n_17), .S(thePC_n_18)); + HA_X1_LVT thePC_i_0_18 (.A(CurrentPC[21]), .B(thePC_i_0_n_17), .CO( + thePC_i_0_n_18), .S(thePC_n_19)); + HA_X1_LVT thePC_i_0_19 (.A(CurrentPC[22]), .B(thePC_i_0_n_18), .CO( + thePC_i_0_n_19), .S(thePC_n_20)); + HA_X1_LVT thePC_i_0_20 (.A(CurrentPC[23]), .B(thePC_i_0_n_19), .CO( + thePC_i_0_n_20), .S(thePC_n_21)); + HA_X1_LVT thePC_i_0_21 (.A(CurrentPC[24]), .B(thePC_i_0_n_20), .CO( + thePC_i_0_n_21), .S(thePC_n_22)); + HA_X1_LVT thePC_i_0_22 (.A(CurrentPC[25]), .B(thePC_i_0_n_21), .CO( + thePC_i_0_n_22), .S(thePC_n_23)); + HA_X1_LVT thePC_i_0_23 (.A(CurrentPC[26]), .B(thePC_i_0_n_22), .CO( + thePC_i_0_n_23), .S(thePC_n_24)); + HA_X1_LVT thePC_i_0_24 (.A(CurrentPC[27]), .B(thePC_i_0_n_23), .CO( + thePC_i_0_n_24), .S(thePC_n_25)); + HA_X1_LVT thePC_i_0_25 (.A(CurrentPC[28]), .B(thePC_i_0_n_24), .CO( + thePC_i_0_n_25), .S(thePC_n_26)); + HA_X1_LVT thePC_i_0_26 (.A(CurrentPC[29]), .B(thePC_i_0_n_25), .CO( + thePC_i_0_n_26), .S(thePC_n_27)); + HA_X1_LVT thePC_i_0_27 (.A(CurrentPC[30]), .B(thePC_i_0_n_26), .CO( + thePC_i_0_n_27), .S(thePC_n_28)); + XOR2_X1_LVT thePC_i_0_28 (.A(CurrentPC[31]), .B(thePC_i_0_n_27), .Z( + thePC_n_29)); + AOI22_X1_LVT i_0_0_52 (.A1(JumpOrBranchPC[31]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_29), .ZN(n_0_0_20)); + INV_X1_LVT i_0_0_51 (.A(n_0_0_20), .ZN(thePC_n_61)); + SDFF_X1_LVT \thePC_CurrentPC_reg[31] (.D(thePC_n_61), .SE(1'b0), .SI( + CurrentPC[31]), .CK(clk_25mhz), .Q(CurrentPC[31]), .QN()); + AOI22_X1_LVT i_0_0_3 (.A1(JumpOrBranchPC[1]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(CurrentPC[1]), .ZN(n_0_0_1)); + INV_X1_LVT i_0_0_2 (.A(n_0_0_1), .ZN(thePC_n_31)); + SDFF_X1_LVT \thePC_CurrentPC_reg[1] (.D(thePC_n_31), .SE(1'b0), .SI( + CurrentPC[1]), .CK(clk_25mhz), .Q(CurrentPC[1]), .QN()); + AOI22_X1_LVT i_0_0_1 (.A1(JumpOrBranchPC[0]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(CurrentPC[0]), .ZN(n_0_0_0)); + INV_X1_LVT i_0_0_0 (.A(n_0_0_0), .ZN(thePC_n_30)); + SDFF_X1_LVT \thePC_CurrentPC_reg[0] (.D(thePC_n_30), .SE(1'b0), .SI( + CurrentPC[0]), .CK(clk_25mhz), .Q(CurrentPC[0]), .QN()); + reg_file theRegisters (.Rs1({Instruction[19], Instruction[18], + Instruction[17], Instruction[16], Instruction[15]}), .Rs2({Instruction[24], + Instruction[23], Instruction[22], Instruction[21], Instruction[20]}), + .Rd({Instruction[11], Instruction[10], Instruction[9], Instruction[8], + Instruction[7]}), .RRs1(RRs1), .RRs2(RRs2), .WRd(WRd), .WrReg(WrReg), + .reset(reset), .clk(clk_25mhz), .dftIn(scan_en)); + main_mem theMem (.clk(clk_25mhz), .reset(reset), .DAddr({uc_0, uc_1, uc_2, + uc_3, uc_4, uc_5, uc_6, uc_7, uc_8, uc_9, uc_10, uc_11, uc_12, uc_13, + uc_14, uc_15, uc_16, uc_17, uc_18, DAddr[12], DAddr[11], DAddr[10], + DAddr[9], DAddr[8], DAddr[7], DAddr[6], DAddr[5], DAddr[4], DAddr[3], + DAddr[2], DAddr[1], DAddr[0]}), .IAddr({uc_19, uc_20, uc_21, uc_22, uc_23, + uc_24, uc_25, uc_26, uc_27, uc_28, uc_29, uc_30, uc_31, uc_32, uc_33, + uc_34, uc_35, uc_36, uc_37, NextPC[12], NextPC[11], NextPC[10], NextPC[9], + NextPC[8], led[7], led[6], led[5], led[4], led[3], led[2], uc_38, uc_39}), + .DWData(RRs2), .DRData(RData), .IRData(Instruction), .DWE(led[1]), + .DWidth(DWidth)); + decoder theDecoder (.CurrentPC(CurrentPC), .JumpOrBranchPC(JumpOrBranchPC), + .JumpOrBranch(JumpOrBranch), .DAddr({uc_40, uc_41, uc_42, uc_43, uc_44, + uc_45, uc_46, uc_47, uc_48, uc_49, uc_50, uc_51, uc_52, uc_53, uc_54, + uc_55, uc_56, uc_57, uc_58, DAddr[12], DAddr[11], DAddr[10], DAddr[9], + DAddr[8], DAddr[7], DAddr[6], DAddr[5], DAddr[4], DAddr[3], DAddr[2], + DAddr[1], DAddr[0]}), .WData(), .RData(RData), .Instruction(Instruction), + .WrMem(led[1]), .DWidth(DWidth), .Rs1(), .Rs2(), .Rd(), .RRs1(RRs1), + .RRs2(RRs2), .WRd(WRd), .WrReg(WrReg), .Illegal(led[0])); + MUX2_X1_LVT i_0_0_60 (.A(thePC_n_5), .B(JumpOrBranchPC[7]), .S(JumpOrBranch), + .Z(led[7])); +endmodule diff --git a/oasys.tessent.03/Scan_0/post_scan.v b/oasys.tessent.03/Scan_0/post_scan.v new file mode 100644 index 0000000..1f7fa5c --- /dev/null +++ b/oasys.tessent.03/Scan_0/post_scan.v @@ -0,0 +1,15792 @@ +/* Generated by Tessent Shell 2023.4-p1 at Fri May 29 09:14:23 CEST 2026 */ +module alu(aluOp, aluNegAr, aluBypass, op1, op2, result, eqFlag); + input [31:0] op1, op2; + input [2:0] aluOp; + input aluNegAr, aluBypass; + output [31:0] result; + output eqFlag; + + wire n_9_0, n_9_1, n_9_2, n_9_3, n_9_4, n_9_5, n_9_6, n_9_7, n_9_8, n_9_9, + n_9_10, n_9_11, n_9_12, n_9_13, n_9_14, n_9_15, n_9_16, n_9_17, n_9_18, + n_9_19, n_9_20, n_9_21, n_9_22, n_9_23, n_9_24, n_9_25, n_9_26, n_9_27, + n_9_28, n_9_29, n_9_30, n_9_31, n_10_0, n_10_1, n_10_2, n_10_3, n_10_4, + n_10_5, n_10_6, n_10_7, n_10_8, n_10_9, n_10_10, n_10_11, n_10_12, + n_10_13, n_10_14, n_10_15, n_10_16, n_10_17, n_10_18, n_10_19, n_10_20, + n_10_21, n_10_22, n_10_23, n_10_24, n_10_25, n_10_26, n_10_27, n_10_28, + n_10_29, n_10_30, n_10_31, n_10_32, n_10_33, n_10_34, n_10_35, n_10_36, + n_10_37, n_10_38, n_10_39, n_10_40, n_10_41, n_10_42, n_10_43, n_10_44, + n_10_45, n_10_46, n_10_47, n_10_48, n_10_49, n_10_50, n_10_51, n_10_52, + n_10_53, n_10_54, n_10_55, n_10_56, n_10_57, n_10_58, n_10_59, n_10_60, + n_10_61, n_10_62, n_10_63, n_10_64, n_10_65, n_10_66, n_10_67, n_10_68, + n_10_69, n_10_70, n_10_71, n_10_72, n_10_73, n_10_74, n_10_75, n_10_76, + n_10_77, n_10_78, n_10_79, n_10_80, n_10_81, n_10_82, n_10_83, n_10_84, + n_10_85, n_10_86, n_10_87, n_10_88, n_10_89, n_10_90, n_10_91, n_10_92, + n_10_93, n_10_94, n_10_95, n_10_96, n_10_97, n_10_98, n_10_99, n_10_100, + n_10_101, n_10_102, n_10_103, n_10_104, n_10_105, n_10_106, n_10_107, + n_10_108, n_10_109, n_10_110, n_10_111, n_10_112, n_10_113, n_10_114, + n_10_115, n_10_116, n_10_117, n_10_118, n_10_119, n_10_120, n_10_121, + n_10_122, n_10_123, n_0_0, n_0_1, n_0_2, n_0_3, n_0_4, n_0_5, n_0_6, + n_0_7, n_0_8, n_0_9, n_0_10, n_0_11, n_0_12, n_0_13, n_0_14, n_0_15, + n_0_16, n_0_17, n_0_18, n_0_19, n_0_20, n_0_21, n_0_22, n_0_23, n_0_24, + n_0_25, n_0_26, n_0_27, n_0_28, n_0_29, n_0_30, n_0_31, n_0_32, n_0_33, + n_0_34, n_0_35, n_0_36, n_0_37, n_0_38, n_0_39, n_0_40, n_0_41, n_0_42, + n_0_43, n_0_44, n_0_45, n_0_46, n_0_47, n_0_48, n_0_49, n_0_50, n_0_51, + n_0_52, n_0_53, n_0_54, n_0_55, n_0_56, n_0_57, n_0_58, n_0_59, n_0_60, + n_0_61, n_0_62, n_0_63, n_0_64, n_0_65, n_0_66, n_0_67, n_0_68, n_0_69, + n_0_70, n_0_71, n_0_72, n_0_73, n_0_74, n_0_75, n_0_76, n_0_77, n_0_78, + n_0_79, n_0_80, n_0_81, n_0_82, n_0_83, n_0_84, n_0_85, n_0_86, n_0_87, + n_0_88, n_0_89, n_0_90, n_0_91, n_0_92, n_0_93, n_0_94, n_0_95, n_0_96, + n_0_97, n_0_98, n_0_99, n_0_100, n_0_101, n_0_102, n_0_103, n_0_104, + n_0_105, n_0_106, n_0_107, n_0_108, n_0_109, n_0_110, n_0_111, n_0_112, + n_0_113, n_0_114, n_0_115, n_0_116, n_0_117, n_0_118, n_0_119, n_0_120, + n_0_121, n_0_122, n_0_123, n_0_124, n_0_125, n_0_126, n_0_127, n_0_128, + n_0_129, n_0_130, n_0_131, n_0_132, n_0_133, n_0_134, n_0_135, n_0_136, + n_0_137, n_0_138, n_0_139, n_0_140, n_0_141, n_0_142, n_0_143, n_0_144, + n_0_145, n_0_146, n_0_147, n_0_148, n_0_149, n_0_150, n_0_151, n_0_152, + n_0_153, n_0_154, n_0_155, n_0_156, n_0_157, n_0_158, n_0_159, n_0_160, + n_0_161, n_0_162, n_0_163, n_0_164, n_0_165, n_0_166, n_0_167, n_0_168, + n_0_169, n_0_170, n_0_171, n_0_172, n_0_173, n_0_174, n_0_175, n_0_176, + n_0_177, n_0_178, n_0_179, n_0_180, n_0_181, n_0_182, n_0_183, n_0_184, + n_0_185, n_0_186, n_0_187, n_0_188, n_0_189, n_0_190, n_0_191, n_0_192, + n_0_193, n_0_194, n_0_195, n_0_196, n_0_197, n_0_198, n_0_199, n_0_200, + n_0_201, n_0_202, n_0_203, n_0_204, n_0_205, n_0_206, n_0_207, n_0_208, + n_0_209, n_0_210, n_0_211, n_0_212, n_0_213, n_0_214, n_0_215, n_0_216, + n_0_217, n_0_218, n_0_219, n_0_220, n_0_221, n_0_222, n_0_223, n_0_224, + n_0_225, n_0_226, n_0_227, n_0_228, n_0_229, n_0_230, n_0_231, n_0_232, + n_0_233, n_0_234, n_0_235, n_0_236, n_0_237, n_0_238, n_0_239, n_0_240, + n_0_241, n_0_242, n_0_243, n_0_244, n_0_245, n_0_246, n_0_247, n_0_248, + n_0_249, n_0_250, n_0_251, n_0_252, n_0_253, n_0_254, n_0_255, n_0_256, + n_0_257, n_0_258, n_0_259, n_0_260, n_0_261, n_0_262, n_0_263, n_0_264, + n_0_265, n_0_266, n_0_267, n_0_268, n_0_269, n_0_270, n_0_271, n_0_272, + n_0_273, n_0_274, n_0_275, n_0_276, n_0_277, n_0_278, n_0_279, n_0_280, + n_0_281, n_0_282, n_0_283, n_0_284, n_0_285, n_0_286, n_0_287, n_0_288, + n_0_289, n_0_290, n_0_291, n_0_292, n_0_293, n_0_294, n_0_295, n_0_296, + n_0_297, n_0_298, n_0_299, n_0_300, n_0_301, n_0_302, n_0_303, n_0_304, + n_0_305, n_0_306, n_0_307, n_0_308, n_0_309, n_0_310, n_0_311, n_0_312, + n_0_313, n_0_314, n_0_315, n_0_316, n_0_317, n_0_318, n_0_319, n_0_320, + n_0_321, n_0_322, n_0_323, n_0_324, n_0_325, n_0_326, n_0_327, n_0_328, + n_0_329, n_0_330, n_0_331, n_0_332, n_0_333, n_0_334, n_0_335, n_0_336, + n_0_337, n_0_338, n_0_339, n_0_340, n_0_341, n_0_342, n_0_343, n_0_344, + n_0_345, n_0_346, n_0_347, n_0_348, n_0_349, n_0_350, n_0_351, n_0_352, + n_0_353, n_0_354, n_0_355, n_0_356, n_0_357, n_0_358, n_0_359, n_0_360, + n_0_361, n_0_362, n_0_363, n_0_364, n_0_365, n_0_366, n_0_367, n_0_368, + n_0_369, n_0_370, n_0_371, n_0_372, n_0_373, n_0_374, n_0_375, n_0_376, + n_0_377, n_0_378, n_0_379, n_0_380, n_0_381, n_0_382, n_0_383, n_0_384, + n_0_385, n_0_386, n_0_387, n_0_388, n_0_389, n_0_390, n_0_391, n_0_392, + n_0_393, n_0_394, n_0_395, n_0_396, n_0_397, n_0_398, n_0_399, n_0_400, + n_0_401, n_0_402, n_0_403, n_0_404, n_0_405, n_0_406, n_0_407, n_0_408, + n_0_409, n_0_410, n_0_411, n_0_412, n_0_413, n_0_414, n_0_415, n_0_416, + n_0_417, n_0_418, n_0_419, n_0_420, n_0_421, n_0_422, n_0_423, n_0_424, + n_0_425, n_0_426, n_0_427, n_0_428, n_0_429, n_0_430, n_0_431, n_0_432, + n_0_433, n_0_434, n_0_435, n_0_436, n_0_437, n_0_438, n_0_439, n_0_440, + n_0_441, n_0_442, n_0_443, n_0_444, n_0_445, n_0_446, n_0_447, n_0_448, + n_0_449, n_0_450, n_0_451, n_0_452, n_0_453, n_0_454, n_0_455, n_0_456, + n_0_457, n_0_458, n_0_459, n_0_460, n_0_461, n_0_462, n_0_463, n_0_464, + n_0_465, n_0_466, n_0_467, n_0_468, n_0_469, n_0_470, n_0_471, n_0_472, + n_0_473, n_0_474, n_0_475, n_0_476, n_0_477, n_0_478, n_0_479, n_0_480, + n_0_481, n_0_482, n_0_483, n_0_484, n_0_485, n_0_486, n_0_487, n_0_488, + n_0_489, n_0_490, n_0_491, n_0_492, n_0_493, n_0_494, n_0_495, n_0_496, + n_0_497, n_0_498, n_0_499, n_0_500, n_0_501, n_0_502, n_0_503, n_0_504, + n_0_505, n_0_506, n_0_507, n_0_508, n_0_509, n_0_510, n_0_511, n_0_512, + n_0_513, n_0_514, n_0_515, n_0_516, n_0_517, n_0_518, n_0_519, n_0_520, + n_0_521, n_0_522, n_0_523, n_0_524, n_0_525, n_0_526, n_0_527, n_0_528, + n_0_529, n_0_530, n_0_531, n_0_532, n_0_533, n_0_534, n_0_535, n_0_536, + n_0_537, n_0_538, n_0_539, n_0_540, n_0_541, n_0_542, n_0_543, n_0_544, + n_0_545, n_0_546, n_0_547, n_0_548, n_0_549, n_0_550, n_0_551, n_0_552, + n_0_553, n_0_554, n_0_555, n_0_556, n_0_557, n_0_558, n_0_559, n_0_560, + n_0_561, n_0_562, n_0_563, n_0_564, n_0_565, n_0_566, n_0_567, n_0_568, + n_0_569, n_0_570, n_0_571, n_0_572, n_0_573, n_0_574, n_0_575, n_0_576, + n_0_577, n_0_578, n_0_579, n_0_580, n_0_581, n_0_582, n_0_583, n_0_584, + n_0_585, n_0_586, n_0_587, n_0_588, n_0_589, n_0_590, n_0_591, n_0_592, + n_0_593, n_0_594, n_0_595, n_0_596, n_0_597, n_0_598, n_0_599, n_0_600, + n_0_601, n_0_602, n_0_603, n_0_604, n_0_605, n_0_606, n_0_607, n_0_608, + n_0_609, n_0_610, n_0_611, n_0_612, n_0_613, n_0_614, n_0_615, n_0_616, + n_0_617, n_0_618, n_0_619, n_0_620, n_0_621, n_0_622, n_0_623, n_0_624, + n_0_625, n_0_626, n_0_627, n_0_628, n_0_629, n_0_630, n_0_631, n_0_632, + n_0_633, n_0_634, n_0_635, n_0_636, n_0_637, n_0_638, n_0_639, n_0_640, + n_0_641, n_0_642, n_0_643, n_0_644, n_0_645, n_0_646, n_0_647, n_0_648, + n_0_649, n_0_650, n_0_651, n_0_652, n_0_653, n_0_654, n_0_655, n_0_656, + n_0_657, n_0_658, n_0_659, n_0_660, n_0_661, n_0_662, n_0_663, n_0_664, + n_0_665, n_0_666, n_0_667, n_0_668, n_0_669, n_0_670, n_0_671, n_0_672, + n_0_673, n_0_674, n_0_675, n_0_676, n_0_677, n_0_678, n_0_679, n_0_680, + n_0_681, n_0_682, n_0_683, n_0_684, n_0_685, n_0_686, n_0_687, n_0_688, + n_0_689, n_0_690, n_0_691, n_0_692, n_0_693, n_0_694, n_0_695, n_0_696, + n_0_697, n_0_698, n_0_699, n_0_700, n_0_701, n_0_702, n_0_703, n_0_704, + n_0_705, n_0_706, n_0_707, n_0_708, n_0_709, n_0_710, n_0_711, n_0_712, + n_0_713, n_0_714, n_0_715, n_0_716, n_0_717, n_0_718, n_0_719, n_0_720, + n_0_721, n_0_722, n_0_723, n_0_724, n_0_725, n_0_726, n_0_727, n_0_728, + n_0_729, n_0_730, n_0_731, n_0_732, n_0_733, n_0_734, n_0_735, n_0_736, + n_0_737, n_0_738, n_0_739, n_0_740, n_0, n_1, n_2, n_3, n_4, n_5, n_6, + n_7, n_8, n_9, n_10, n_11, n_12, n_13, n_14, n_15, n_16, n_17, n_18, + n_19, n_20, n_21, n_22, n_23, n_24, n_25, n_26, n_27, n_28, n_29, n_30, + n_31, n_63, n_62, n_61, n_60, n_59, n_58, n_57, n_56, n_55, n_54, n_53, + n_52, n_51, n_50, n_49, n_48, n_47, n_46, n_45, n_44, n_43, n_42, n_41, + n_40, n_39, n_38, n_37, n_36, n_35, n_34, n_33, n_32; + + INV_X1_LVT i_0_725( + .A(op2[31]), .ZN(n_0_692) + ); + INV_X1_LVT i_0_724( + .A(op1[31]), .ZN(n_0_691) + ); + INV_X1_LVT i_0_718( + .A(aluOp[1]), .ZN(n_0_685) + ); + INV_X1_LVT i_0_717( + .A(aluOp[2]), .ZN(n_0_684) + ); + NOR2_X1_LVT i_0_599( + .A1(n_0_685), .A2(n_0_684), .ZN(n_0_567) + ); + INV_X1_LVT i_0_598( + .A(n_0_567), .ZN(n_0_566) + ); + INV_X1_LVT i_0_716( + .A(aluOp[0]), .ZN(n_0_683) + ); + NAND2_X1_LVT i_0_602( + .A1(aluOp[2]), .A2(aluNegAr), .ZN(n_0_570) + ); + OAI21_X1_LVT i_0_590( + .A(n_0_566), .B1(n_0_683), .B2(n_0_570), .ZN(n_0_558) + ); + INV_X1_LVT i_0_714( + .A(aluBypass), .ZN(n_0_681) + ); + NOR2_X1_LVT i_0_601( + .A1(n_0_684), .A2(aluOp[0]), .ZN(n_0_569) + ); + NAND2_X1_LVT i_0_597( + .A1(n_0_681), .A2(n_0_569), .ZN(n_0_565) + ); + INV_X1_LVT i_0_596( + .A(n_0_565), .ZN(n_0_564) + ); + OAI22_X1_LVT i_0_589( + .A1(n_0_691), .A2(n_0_558), .B1(op1[31]), .B2(n_0_564), .ZN(n_0_557) + ); + NOR2_X1_LVT i_0_588( + .A1(n_0_692), .A2(n_0_557), .ZN(n_0_556) + ); + XNOR2_X1_LVT i_9_31( + .A(op2[31]), .B(op1[31]), .ZN(n_9_31) + ); + HA_X1_LVT i_9_0( + .A(op2[0]), .B(op1[0]), .CO(n_9_0), .S(n_0) + ); + FA_X1_LVT i_9_1( + .A(op2[1]), .B(op1[1]), .CI(n_9_0), .CO(n_9_1), .S(n_1) + ); + FA_X1_LVT i_9_2( + .A(op2[2]), .B(op1[2]), .CI(n_9_1), .CO(n_9_2), .S(n_2) + ); + FA_X1_LVT i_9_3( + .A(op2[3]), .B(op1[3]), .CI(n_9_2), .CO(n_9_3), .S(n_3) + ); + FA_X1_LVT i_9_4( + .A(op2[4]), .B(op1[4]), .CI(n_9_3), .CO(n_9_4), .S(n_4) + ); + FA_X1_LVT i_9_5( + .A(op2[5]), .B(op1[5]), .CI(n_9_4), .CO(n_9_5), .S(n_5) + ); + FA_X1_LVT i_9_6( + .A(op2[6]), .B(op1[6]), .CI(n_9_5), .CO(n_9_6), .S(n_6) + ); + FA_X1_LVT i_9_7( + .A(op2[7]), .B(op1[7]), .CI(n_9_6), .CO(n_9_7), .S(n_7) + ); + FA_X1_LVT i_9_8( + .A(op2[8]), .B(op1[8]), .CI(n_9_7), .CO(n_9_8), .S(n_8) + ); + FA_X1_LVT i_9_9( + .A(op2[9]), .B(op1[9]), .CI(n_9_8), .CO(n_9_9), .S(n_9) + ); + FA_X1_LVT i_9_10( + .A(op2[10]), .B(op1[10]), .CI(n_9_9), .CO(n_9_10), .S(n_10) + ); + FA_X1_LVT i_9_11( + .A(op2[11]), .B(op1[11]), .CI(n_9_10), .CO(n_9_11), .S(n_11) + ); + FA_X1_LVT i_9_12( + .A(op2[12]), .B(op1[12]), .CI(n_9_11), .CO(n_9_12), .S(n_12) + ); + FA_X1_LVT i_9_13( + .A(op2[13]), .B(op1[13]), .CI(n_9_12), .CO(n_9_13), .S(n_13) + ); + FA_X1_LVT i_9_14( + .A(op2[14]), .B(op1[14]), .CI(n_9_13), .CO(n_9_14), .S(n_14) + ); + FA_X1_LVT i_9_15( + .A(op2[15]), .B(op1[15]), .CI(n_9_14), .CO(n_9_15), .S(n_15) + ); + FA_X1_LVT i_9_16( + .A(op2[16]), .B(op1[16]), .CI(n_9_15), .CO(n_9_16), .S(n_16) + ); + FA_X1_LVT i_9_17( + .A(op2[17]), .B(op1[17]), .CI(n_9_16), .CO(n_9_17), .S(n_17) + ); + FA_X1_LVT i_9_18( + .A(op2[18]), .B(op1[18]), .CI(n_9_17), .CO(n_9_18), .S(n_18) + ); + FA_X1_LVT i_9_19( + .A(op2[19]), .B(op1[19]), .CI(n_9_18), .CO(n_9_19), .S(n_19) + ); + FA_X1_LVT i_9_20( + .A(op2[20]), .B(op1[20]), .CI(n_9_19), .CO(n_9_20), .S(n_20) + ); + FA_X1_LVT i_9_21( + .A(op2[21]), .B(op1[21]), .CI(n_9_20), .CO(n_9_21), .S(n_21) + ); + FA_X1_LVT i_9_22( + .A(op2[22]), .B(op1[22]), .CI(n_9_21), .CO(n_9_22), .S(n_22) + ); + FA_X1_LVT i_9_23( + .A(op2[23]), .B(op1[23]), .CI(n_9_22), .CO(n_9_23), .S(n_23) + ); + FA_X1_LVT i_9_24( + .A(op2[24]), .B(op1[24]), .CI(n_9_23), .CO(n_9_24), .S(n_24) + ); + FA_X1_LVT i_9_25( + .A(op2[25]), .B(op1[25]), .CI(n_9_24), .CO(n_9_25), .S(n_25) + ); + FA_X1_LVT i_9_26( + .A(op2[26]), .B(op1[26]), .CI(n_9_25), .CO(n_9_26), .S(n_26) + ); + FA_X1_LVT i_9_27( + .A(op2[27]), .B(op1[27]), .CI(n_9_26), .CO(n_9_27), .S(n_27) + ); + FA_X1_LVT i_9_28( + .A(op2[28]), .B(op1[28]), .CI(n_9_27), .CO(n_9_28), .S(n_28) + ); + FA_X1_LVT i_9_29( + .A(op2[29]), .B(op1[29]), .CI(n_9_28), .CO(n_9_29), .S(n_29) + ); + FA_X1_LVT i_9_30( + .A(op2[30]), .B(op1[30]), .CI(n_9_29), .CO(n_9_30), .S(n_30) + ); + XNOR2_X1_LVT i_9_32( + .A(n_9_31), .B(n_9_30), .ZN(n_31) + ); + NAND4_X1_LVT i_0_614( + .A1(n_0_685), .A2(n_0_681), .A3(n_0_684), .A4(n_0_683), .ZN(n_0_582) + ); + NOR2_X1_LVT i_0_613( + .A1(aluNegAr), .A2(n_0_582), .ZN(n_0_581) + ); + INV_X1_LVT i_10_147( + .A(op2[30]), .ZN(n_10_117) + ); + NAND2_X1_LVT i_10_149( + .A1(n_10_117), .A2(op1[30]), .ZN(n_10_119) + ); + INV_X1_LVT i_10_152( + .A(n_10_119), .ZN(n_10_121) + ); + INV_X1_LVT i_10_130( + .A(op1[26]), .ZN(n_10_104) + ); + NAND2_X1_LVT i_10_131( + .A1(n_10_104), .A2(op2[26]), .ZN(n_10_105) + ); + INV_X1_LVT i_10_123( + .A(op2[25]), .ZN(n_10_98) + ); + NAND2_X1_LVT i_10_125( + .A1(n_10_98), .A2(op1[25]), .ZN(n_10_100) + ); + INV_X1_LVT i_10_112( + .A(op2[23]), .ZN(n_10_89) + ); + NAND2_X1_LVT i_10_114( + .A1(n_10_89), .A2(op1[23]), .ZN(n_10_91) + ); + INV_X1_LVT i_10_101( + .A(op2[21]), .ZN(n_10_80) + ); + NAND2_X1_LVT i_10_103( + .A1(n_10_80), .A2(op1[21]), .ZN(n_10_82) + ); + INV_X1_LVT i_10_48( + .A(op1[8]), .ZN(n_10_40) + ); + NAND2_X1_LVT i_10_49( + .A1(n_10_40), .A2(op2[8]), .ZN(n_10_41) + ); + INV_X1_LVT i_10_41( + .A(op2[7]), .ZN(n_10_34) + ); + NAND2_X1_LVT i_10_43( + .A1(n_10_34), .A2(op1[7]), .ZN(n_10_36) + ); + INV_X1_LVT i_10_32( + .A(op2[5]), .ZN(n_10_27) + ); + NOR2_X1_LVT i_10_33( + .A1(n_10_27), .A2(op1[5]), .ZN(n_10_28) + ); + INV_X1_LVT i_10_24( + .A(op1[4]), .ZN(n_10_20) + ); + NOR2_X1_LVT i_10_27( + .A1(n_10_20), .A2(op2[4]), .ZN(n_10_23) + ); + INV_X1_LVT i_10_17( + .A(op2[3]), .ZN(n_10_14) + ); + NAND2_X1_LVT i_10_19( + .A1(n_10_14), .A2(op1[3]), .ZN(n_10_16) + ); + INV_X1_LVT i_10_22( + .A(n_10_16), .ZN(n_10_18) + ); + INV_X1_LVT i_10_10( + .A(op2[2]), .ZN(n_10_8) + ); + NAND2_X1_LVT i_10_12( + .A1(n_10_8), .A2(op1[2]), .ZN(n_10_10) + ); + INV_X1_LVT i_10_3( + .A(op1[1]), .ZN(n_10_2) + ); + NAND2_X1_LVT i_10_5( + .A1(n_10_2), .A2(op2[1]), .ZN(n_10_4) + ); + INV_X1_LVT i_10_0( + .A(op1[0]), .ZN(n_10_0) + ); + NAND2_X1_LVT i_10_1( + .A1(n_10_0), .A2(op2[0]), .ZN(n_10_1) + ); + OR2_X1_LVT i_10_4( + .A1(n_10_2), .A2(op2[1]), .ZN(n_10_3) + ); + INV_X1_LVT i_10_8( + .A(n_10_3), .ZN(n_10_6) + ); + OAI21_X1_LVT i_10_9( + .A(n_10_4), .B1(n_10_1), .B2(n_10_6), .ZN(n_10_7) + ); + NOR2_X1_LVT i_10_11( + .A1(n_10_8), .A2(op1[2]), .ZN(n_10_9) + ); + OAI21_X1_LVT i_10_16( + .A(n_10_10), .B1(n_10_7), .B2(n_10_9), .ZN(n_10_13) + ); + OR2_X1_LVT i_10_18( + .A1(n_10_14), .A2(op1[3]), .ZN(n_10_15) + ); + AOI21_X1_LVT i_10_23( + .A(n_10_18), .B1(n_10_13), .B2(n_10_15), .ZN(n_10_19) + ); + INV_X1_LVT i_10_30( + .A(n_10_19), .ZN(n_10_25) + ); + NAND2_X1_LVT i_10_25( + .A1(n_10_20), .A2(op2[4]), .ZN(n_10_21) + ); + AOI21_X1_LVT i_10_31( + .A(n_10_23), .B1(n_10_25), .B2(n_10_21), .ZN(n_10_26) + ); + AOI21_X1_LVT i_10_34( + .A(n_10_28), .B1(n_10_27), .B2(op1[5]), .ZN(n_10_29) + ); + AOI21_X1_LVT i_10_36( + .A(n_10_28), .B1(n_10_26), .B2(n_10_29), .ZN(n_10_30) + ); + XOR2_X1_LVT i_10_37( + .A(op2[6]), .B(op1[6]), .Z(n_10_31) + ); + INV_X1_LVT i_10_39( + .A(op2[6]), .ZN(n_10_32) + ); + OAI22_X1_LVT i_10_40( + .A1(n_10_30), .A2(n_10_31), .B1(n_10_32), .B2(op1[6]), .ZN(n_10_33) + ); + NOR2_X1_LVT i_10_42( + .A1(n_10_34), .A2(op1[7]), .ZN(n_10_35) + ); + OAI21_X1_LVT i_10_47( + .A(n_10_36), .B1(n_10_33), .B2(n_10_35), .ZN(n_10_39) + ); + OAI21_X1_LVT i_10_50( + .A(n_10_41), .B1(n_10_40), .B2(op2[8]), .ZN(n_10_42) + ); + OAI21_X1_LVT i_10_52( + .A(n_10_41), .B1(n_10_39), .B2(n_10_42), .ZN(n_10_43) + ); + XNOR2_X1_LVT i_10_53( + .A(op2[9]), .B(op1[9]), .ZN(n_10_44) + ); + INV_X1_LVT i_10_55( + .A(op1[9]), .ZN(n_10_45) + ); + AOI22_X1_LVT i_10_56( + .A1(n_10_43), .A2(n_10_44), .B1(n_10_45), .B2(op2[9]), .ZN(n_10_46) + ); + XOR2_X1_LVT i_10_57( + .A(op2[10]), .B(op1[10]), .Z(n_10_47) + ); + INV_X1_LVT i_10_59( + .A(op2[10]), .ZN(n_10_48) + ); + OAI22_X1_LVT i_10_60( + .A1(n_10_46), .A2(n_10_47), .B1(n_10_48), .B2(op1[10]), .ZN(n_10_49) + ); + XNOR2_X1_LVT i_10_61( + .A(op2[11]), .B(op1[11]), .ZN(n_10_50) + ); + INV_X1_LVT i_10_63( + .A(op1[11]), .ZN(n_10_51) + ); + AOI22_X1_LVT i_10_64( + .A1(n_10_49), .A2(n_10_50), .B1(n_10_51), .B2(op2[11]), .ZN(n_10_52) + ); + XOR2_X1_LVT i_10_65( + .A(op2[12]), .B(op1[12]), .Z(n_10_53) + ); + INV_X1_LVT i_10_67( + .A(op2[12]), .ZN(n_10_54) + ); + OAI22_X1_LVT i_10_68( + .A1(n_10_52), .A2(n_10_53), .B1(n_10_54), .B2(op1[12]), .ZN(n_10_55) + ); + XNOR2_X1_LVT i_10_69( + .A(op2[13]), .B(op1[13]), .ZN(n_10_56) + ); + INV_X1_LVT i_10_71( + .A(op1[13]), .ZN(n_10_57) + ); + AOI22_X1_LVT i_10_72( + .A1(n_10_55), .A2(n_10_56), .B1(n_10_57), .B2(op2[13]), .ZN(n_10_58) + ); + XOR2_X1_LVT i_10_73( + .A(op2[14]), .B(op1[14]), .Z(n_10_59) + ); + INV_X1_LVT i_10_75( + .A(op2[14]), .ZN(n_10_60) + ); + OAI22_X1_LVT i_10_76( + .A1(n_10_58), .A2(n_10_59), .B1(n_10_60), .B2(op1[14]), .ZN(n_10_61) + ); + XNOR2_X1_LVT i_10_77( + .A(op2[15]), .B(op1[15]), .ZN(n_10_62) + ); + INV_X1_LVT i_10_79( + .A(op1[15]), .ZN(n_10_63) + ); + AOI22_X1_LVT i_10_80( + .A1(n_10_61), .A2(n_10_62), .B1(n_10_63), .B2(op2[15]), .ZN(n_10_64) + ); + XOR2_X1_LVT i_10_81( + .A(op2[16]), .B(op1[16]), .Z(n_10_65) + ); + INV_X1_LVT i_10_83( + .A(op2[16]), .ZN(n_10_66) + ); + OAI22_X1_LVT i_10_84( + .A1(n_10_64), .A2(n_10_65), .B1(n_10_66), .B2(op1[16]), .ZN(n_10_67) + ); + XNOR2_X1_LVT i_10_85( + .A(op2[17]), .B(op1[17]), .ZN(n_10_68) + ); + INV_X1_LVT i_10_87( + .A(op1[17]), .ZN(n_10_69) + ); + AOI22_X1_LVT i_10_88( + .A1(n_10_67), .A2(n_10_68), .B1(n_10_69), .B2(op2[17]), .ZN(n_10_70) + ); + XOR2_X1_LVT i_10_89( + .A(op2[18]), .B(op1[18]), .Z(n_10_71) + ); + INV_X1_LVT i_10_91( + .A(op2[18]), .ZN(n_10_72) + ); + OAI22_X1_LVT i_10_92( + .A1(n_10_70), .A2(n_10_71), .B1(n_10_72), .B2(op1[18]), .ZN(n_10_73) + ); + XNOR2_X1_LVT i_10_93( + .A(op2[19]), .B(op1[19]), .ZN(n_10_74) + ); + INV_X1_LVT i_10_95( + .A(op1[19]), .ZN(n_10_75) + ); + AOI22_X1_LVT i_10_96( + .A1(n_10_73), .A2(n_10_74), .B1(n_10_75), .B2(op2[19]), .ZN(n_10_76) + ); + XOR2_X1_LVT i_10_97( + .A(op2[20]), .B(op1[20]), .Z(n_10_77) + ); + INV_X1_LVT i_10_99( + .A(op2[20]), .ZN(n_10_78) + ); + OAI22_X1_LVT i_10_100( + .A1(n_10_76), .A2(n_10_77), .B1(n_10_78), .B2(op1[20]), .ZN(n_10_79) + ); + NOR2_X1_LVT i_10_102( + .A1(n_10_80), .A2(op1[21]), .ZN(n_10_81) + ); + OAI21_X1_LVT i_10_107( + .A(n_10_82), .B1(n_10_79), .B2(n_10_81), .ZN(n_10_85) + ); + XOR2_X1_LVT i_10_108( + .A(op2[22]), .B(op1[22]), .Z(n_10_86) + ); + INV_X1_LVT i_10_110( + .A(op2[22]), .ZN(n_10_87) + ); + OAI22_X1_LVT i_10_111( + .A1(n_10_85), .A2(n_10_86), .B1(n_10_87), .B2(op1[22]), .ZN(n_10_88) + ); + NOR2_X1_LVT i_10_113( + .A1(n_10_89), .A2(op1[23]), .ZN(n_10_90) + ); + OAI21_X1_LVT i_10_118( + .A(n_10_91), .B1(n_10_88), .B2(n_10_90), .ZN(n_10_94) + ); + XOR2_X1_LVT i_10_119( + .A(op2[24]), .B(op1[24]), .Z(n_10_95) + ); + INV_X1_LVT i_10_121( + .A(op2[24]), .ZN(n_10_96) + ); + OAI22_X1_LVT i_10_122( + .A1(n_10_94), .A2(n_10_95), .B1(n_10_96), .B2(op1[24]), .ZN(n_10_97) + ); + NOR2_X1_LVT i_10_124( + .A1(n_10_98), .A2(op1[25]), .ZN(n_10_99) + ); + OAI21_X1_LVT i_10_129( + .A(n_10_100), .B1(n_10_97), .B2(n_10_99), .ZN(n_10_103) + ); + OAI21_X1_LVT i_10_132( + .A(n_10_105), .B1(n_10_104), .B2(op2[26]), .ZN(n_10_106) + ); + OAI21_X1_LVT i_10_134( + .A(n_10_105), .B1(n_10_103), .B2(n_10_106), .ZN(n_10_107) + ); + XNOR2_X1_LVT i_10_135( + .A(op2[27]), .B(op1[27]), .ZN(n_10_108) + ); + INV_X1_LVT i_10_137( + .A(op1[27]), .ZN(n_10_109) + ); + AOI22_X1_LVT i_10_138( + .A1(n_10_107), .A2(n_10_108), .B1(n_10_109), .B2(op2[27]), .ZN(n_10_110) + ); + XOR2_X1_LVT i_10_139( + .A(op2[28]), .B(op1[28]), .Z(n_10_111) + ); + INV_X1_LVT i_10_141( + .A(op2[28]), .ZN(n_10_112) + ); + OAI22_X1_LVT i_10_142( + .A1(n_10_110), .A2(n_10_111), .B1(n_10_112), .B2(op1[28]), .ZN(n_10_113) + ); + XNOR2_X1_LVT i_10_143( + .A(op2[29]), .B(op1[29]), .ZN(n_10_114) + ); + INV_X1_LVT i_10_145( + .A(op1[29]), .ZN(n_10_115) + ); + AOI22_X1_LVT i_10_146( + .A1(n_10_113), .A2(n_10_114), .B1(n_10_115), .B2(op2[29]), .ZN(n_10_116) + ); + OR2_X1_LVT i_10_148( + .A1(n_10_117), .A2(op1[30]), .ZN(n_10_118) + ); + AOI21_X1_LVT i_10_153( + .A(n_10_121), .B1(n_10_116), .B2(n_10_118), .ZN(n_10_122) + ); + XNOR2_X1_LVT i_10_154( + .A(op1[31]), .B(op2[31]), .ZN(n_10_123) + ); + XNOR2_X1_LVT i_10_155( + .A(n_10_122), .B(n_10_123), .ZN(n_63) + ); + INV_X1_LVT i_0_715( + .A(aluNegAr), .ZN(n_0_682) + ); + NOR2_X1_LVT i_0_612( + .A1(n_0_682), .A2(n_0_582), .ZN(n_0_580) + ); + AOI221_X1_LVT i_0_587( + .A(n_0_556), .B1(n_31), .B2(n_0_581), .C1(n_63), .C2(n_0_580), .ZN(n_0_555) + ); + NOR3_X1_LVT i_0_654( + .A1(aluOp[1]), .A2(aluBypass), .A3(n_0_683), .ZN(n_0_622) + ); + NAND2_X1_LVT i_0_653( + .A1(n_0_684), .A2(n_0_622), .ZN(n_0_621) + ); + INV_X1_LVT i_0_734( + .A(op2[0]), .ZN(n_0_701) + ); + INV_X1_LVT i_0_756( + .A(op2[3]), .ZN(n_0_723) + ); + NOR2_X1_LVT i_0_650( + .A1(op2[4]), .A2(n_0_723), .ZN(n_0_618) + ); + INV_X1_LVT i_0_649( + .A(n_0_618), .ZN(n_0_617) + ); + NOR2_X1_LVT i_0_648( + .A1(op2[4]), .A2(op2[3]), .ZN(n_0_616) + ); + INV_X1_LVT i_0_647( + .A(n_0_616), .ZN(n_0_615) + ); + INV_X1_LVT i_0_771( + .A(op2[4]), .ZN(n_0_738) + ); + INV_X1_LVT i_0_767( + .A(op1[15]), .ZN(n_0_734) + ); + INV_X1_LVT i_0_746( + .A(op1[7]), .ZN(n_0_713) + ); + AOI22_X1_LVT i_0_651( + .A1(n_0_734), .A2(n_0_723), .B1(op2[3]), .B2(n_0_713), .ZN(n_0_619) + ); + OAI222_X1_LVT i_0_646( + .A1(op1[23]), .A2(n_0_617), .B1(op1[31]), .B2(n_0_615), .C1(n_0_738), .C2(n_0_619), + .ZN(n_0_614) + ); + NOR2_X1_LVT i_0_645( + .A1(op2[2]), .A2(n_0_614), .ZN(n_0_613) + ); + NOR2_X1_LVT i_0_696( + .A1(op1[3]), .A2(n_0_723), .ZN(n_0_663) + ); + INV_X1_LVT i_0_739( + .A(op1[11]), .ZN(n_0_706) + ); + AOI21_X1_LVT i_0_644( + .A(n_0_663), .B1(n_0_723), .B2(n_0_706), .ZN(n_0_612) + ); + AOI22_X1_LVT i_0_643( + .A1(op2[4]), .A2(n_0_612), .B1(op1[27]), .B2(n_0_616), .ZN(n_0_611) + ); + INV_X1_LVT i_0_722( + .A(op1[19]), .ZN(n_0_689) + ); + OAI21_X1_LVT i_0_642( + .A(n_0_611), .B1(n_0_689), .B2(n_0_617), .ZN(n_0_610) + ); + AOI21_X1_LVT i_0_641( + .A(n_0_613), .B1(op2[2]), .B2(n_0_610), .ZN(n_0_609) + ); + INV_X1_LVT i_0_761( + .A(op2[1]), .ZN(n_0_728) + ); + OAI22_X1_LVT i_0_640( + .A1(op2[4]), .A2(op1[21]), .B1(n_0_738), .B2(op1[5]), .ZN(n_0_608) + ); + NAND2_X1_LVT i_0_639( + .A1(op2[3]), .A2(n_0_608), .ZN(n_0_607) + ); + INV_X1_LVT i_0_747( + .A(op1[13]), .ZN(n_0_714) + ); + NOR2_X1_LVT i_0_638( + .A1(n_0_738), .A2(op2[3]), .ZN(n_0_606) + ); + INV_X1_LVT i_0_743( + .A(op1[29]), .ZN(n_0_710) + ); + AOI221_X1_LVT i_0_636( + .A(op2[2]), .B1(n_0_714), .B2(n_0_606), .C1(n_0_710), .C2(n_0_616), .ZN(n_0_604) + ); + OAI22_X1_LVT i_0_635( + .A1(op2[4]), .A2(op1[17]), .B1(n_0_738), .B2(op1[1]), .ZN(n_0_603) + ); + INV_X1_LVT i_0_755( + .A(op1[9]), .ZN(n_0_722) + ); + INV_X1_LVT i_0_637( + .A(n_0_606), .ZN(n_0_605) + ); + INV_X1_LVT i_0_732( + .A(op1[25]), .ZN(n_0_699) + ); + OAI222_X1_LVT i_0_634( + .A1(n_0_723), .A2(n_0_603), .B1(n_0_722), .B2(n_0_605), .C1(n_0_699), .C2(n_0_615), + .ZN(n_0_602) + ); + AOI22_X1_LVT i_0_633( + .A1(n_0_607), .A2(n_0_604), .B1(op2[2]), .B2(n_0_602), .ZN(n_0_601) + ); + OAI221_X1_LVT i_0_616( + .A(n_0_701), .B1(op2[1]), .B2(n_0_609), .C1(n_0_728), .C2(n_0_601), .ZN(n_0_584) + ); + INV_X1_LVT i_0_729( + .A(op1[12]), .ZN(n_0_696) + ); + INV_X1_LVT i_0_731( + .A(op1[28]), .ZN(n_0_698) + ); + AOI22_X1_LVT i_0_622( + .A1(n_0_696), .A2(n_0_606), .B1(n_0_698), .B2(n_0_616), .ZN(n_0_590) + ); + INV_X1_LVT i_0_726( + .A(op2[2]), .ZN(n_0_693) + ); + NOR2_X1_LVT i_0_701( + .A1(n_0_738), .A2(op1[4]), .ZN(n_0_668) + ); + INV_X1_LVT i_0_760( + .A(op1[20]), .ZN(n_0_727) + ); + AOI21_X1_LVT i_0_623( + .A(n_0_668), .B1(n_0_738), .B2(n_0_727), .ZN(n_0_591) + ); + OAI211_X1_LVT i_0_621( + .A(n_0_590), .B(n_0_693), .C1(n_0_723), .C2(n_0_591), .ZN(n_0_589) + ); + OAI22_X1_LVT i_0_626( + .A1(op1[16]), .A2(op2[4]), .B1(n_0_738), .B2(op1[0]), .ZN(n_0_594) + ); + INV_X1_LVT i_0_769( + .A(op1[24]), .ZN(n_0_736) + ); + OAI22_X1_LVT i_0_625( + .A1(n_0_723), .A2(n_0_594), .B1(n_0_736), .B2(n_0_615), .ZN(n_0_593) + ); + AOI21_X1_LVT i_0_624( + .A(n_0_593), .B1(op1[8]), .B2(n_0_606), .ZN(n_0_592) + ); + OAI21_X1_LVT i_0_620( + .A(n_0_589), .B1(n_0_693), .B2(n_0_592), .ZN(n_0_588) + ); + INV_X1_LVT i_0_737( + .A(op1[6]), .ZN(n_0_704) + ); + INV_X1_LVT i_0_720( + .A(op1[22]), .ZN(n_0_687) + ); + OAI22_X1_LVT i_0_632( + .A1(n_0_738), .A2(n_0_704), .B1(op2[4]), .B2(n_0_687), .ZN(n_0_600) + ); + OAI221_X1_LVT i_0_631( + .A(n_0_693), .B1(n_0_723), .B2(n_0_600), .C1(op1[14]), .C2(n_0_605), .ZN(n_0_599) + ); + INV_X1_LVT i_0_750( + .A(op1[30]), .ZN(n_0_717) + ); + AOI21_X1_LVT i_0_630( + .A(n_0_599), .B1(n_0_717), .B2(n_0_616), .ZN(n_0_598) + ); + INV_X1_LVT i_0_738( + .A(op1[18]), .ZN(n_0_705) + ); + NOR2_X1_LVT i_0_628( + .A1(n_0_705), .A2(n_0_617), .ZN(n_0_596) + ); + INV_X1_LVT i_0_727( + .A(op1[2]), .ZN(n_0_694) + ); + INV_X1_LVT i_0_766( + .A(op1[10]), .ZN(n_0_733) + ); + OAI22_X1_LVT i_0_629( + .A1(n_0_723), .A2(n_0_694), .B1(n_0_733), .B2(op2[3]), .ZN(n_0_597) + ); + AOI221_X1_LVT i_0_627( + .A(n_0_596), .B1(op1[26]), .B2(n_0_616), .C1(op2[4]), .C2(n_0_597), .ZN(n_0_595) + ); + OAI21_X1_LVT i_0_619( + .A(n_0_728), .B1(n_0_693), .B2(n_0_595), .ZN(n_0_587) + ); + OAI22_X1_LVT i_0_618( + .A1(n_0_728), .A2(n_0_588), .B1(n_0_598), .B2(n_0_587), .ZN(n_0_586) + ); + INV_X1_LVT i_0_617( + .A(n_0_586), .ZN(n_0_585) + ); + OAI21_X1_LVT i_0_615( + .A(n_0_584), .B1(n_0_701), .B2(n_0_585), .ZN(n_0_583) + ); + NOR2_X1_LVT i_0_607( + .A1(op2[4]), .A2(op2[2]), .ZN(n_0_575) + ); + NAND2_X1_LVT i_0_606( + .A1(n_0_723), .A2(n_0_575), .ZN(n_0_574) + ); + INV_X1_LVT i_0_605( + .A(n_0_574), .ZN(n_0_573) + ); + NAND2_X1_LVT i_0_604( + .A1(n_0_728), .A2(n_0_573), .ZN(n_0_572) + ); + NAND2_X1_LVT i_0_611( + .A1(aluOp[2]), .A2(n_0_622), .ZN(n_0_579) + ); + INV_X1_LVT i_0_610( + .A(n_0_579), .ZN(n_0_578) + ); + NAND2_X1_LVT i_0_594( + .A1(n_0_701), .A2(n_0_578), .ZN(n_0_562) + ); + NOR3_X1_LVT i_0_592( + .A1(aluNegAr), .A2(n_0_572), .A3(n_0_562), .ZN(n_0_560) + ); + INV_X1_LVT i_0_600( + .A(n_0_569), .ZN(n_0_568) + ); + OAI21_X1_LVT i_0_595( + .A(n_0_568), .B1(aluOp[1]), .B2(n_0_570), .ZN(n_0_563) + ); + AOI211_X1_LVT i_0_591( + .A(aluBypass), .B(n_0_560), .C1(n_0_692), .C2(n_0_563), .ZN(n_0_559) + ); + OAI221_X1_LVT i_0_586( + .A(n_0_555), .B1(n_0_621), .B2(n_0_583), .C1(n_0_691), .C2(n_0_559), .ZN(result[31]) + ); + NAND2_X1_LVT i_10_150( + .A1(n_10_118), .A2(n_10_119), .ZN(n_10_120) + ); + XNOR2_X1_LVT i_10_151( + .A(n_10_116), .B(n_10_120), .ZN(n_62) + ); + AOI22_X1_LVT i_0_580( + .A1(n_62), .A2(n_0_580), .B1(n_30), .B2(n_0_581), .ZN(n_0_549) + ); + NAND2_X1_LVT i_0_576( + .A1(aluNegAr), .A2(n_0_578), .ZN(n_0_545) + ); + INV_X1_LVT i_0_603( + .A(n_0_572), .ZN(n_0_571) + ); + NOR3_X1_LVT i_0_574( + .A1(n_0_691), .A2(n_0_545), .A3(n_0_571), .ZN(n_0_543) + ); + AOI22_X1_LVT i_0_573( + .A1(n_0_717), .A2(n_0_565), .B1(op1[30]), .B2(n_0_566), .ZN(n_0_542) + ); + AOI21_X1_LVT i_0_572( + .A(n_0_543), .B1(op2[30]), .B2(n_0_542), .ZN(n_0_541) + ); + NAND2_X1_LVT i_0_579( + .A1(op2[0]), .A2(n_0_578), .ZN(n_0_548) + ); + NAND2_X1_LVT i_0_577( + .A1(op1[31]), .A2(n_0_571), .ZN(n_0_546) + ); + OAI211_X1_LVT i_0_571( + .A(n_0_549), .B(n_0_541), .C1(n_0_548), .C2(n_0_546), .ZN(n_0_540) + ); + OAI221_X1_LVT i_0_581( + .A(n_0_681), .B1(op2[30]), .B2(n_0_568), .C1(n_0_572), .C2(n_0_562), .ZN(n_0_550) + ); + AOI21_X1_LVT i_0_570( + .A(n_0_540), .B1(op1[30]), .B2(n_0_550), .ZN(n_0_539) + ); + INV_X1_LVT i_0_752( + .A(op1[23]), .ZN(n_0_719) + ); + OAI222_X1_LVT i_0_585( + .A1(n_0_713), .A2(n_0_605), .B1(n_0_719), .B2(n_0_615), .C1(n_0_734), .C2(n_0_617), + .ZN(n_0_554) + ); + AOI22_X1_LVT i_0_584( + .A1(op2[2]), .A2(n_0_554), .B1(n_0_693), .B2(n_0_610), .ZN(n_0_553) + ); + OAI22_X1_LVT i_0_583( + .A1(n_0_728), .A2(n_0_553), .B1(op2[1]), .B2(n_0_601), .ZN(n_0_552) + ); + AOI22_X1_LVT i_0_582( + .A1(n_0_701), .A2(n_0_585), .B1(op2[0]), .B2(n_0_552), .ZN(n_0_551) + ); + OAI21_X1_LVT i_0_569( + .A(n_0_539), .B1(n_0_621), .B2(n_0_551), .ZN(result[30]) + ); + INV_X1_LVT i_0_578( + .A(n_0_548), .ZN(n_0_547) + ); + NAND3_X1_LVT i_0_562( + .A1(op1[30]), .A2(n_0_571), .A3(n_0_547), .ZN(n_0_532) + ); + XNOR2_X1_LVT i_10_144( + .A(n_10_113), .B(n_10_114), .ZN(n_61) + ); + NAND2_X1_LVT i_0_558( + .A1(n_61), .A2(n_0_580), .ZN(n_0_528) + ); + OAI21_X1_LVT i_0_557( + .A(n_0_681), .B1(op2[29]), .B2(n_0_568), .ZN(n_0_527) + ); + NAND2_X1_LVT i_0_556( + .A1(op1[29]), .A2(n_0_566), .ZN(n_0_526) + ); + AOI22_X1_LVT i_0_555( + .A1(op1[29]), .A2(n_0_527), .B1(op2[29]), .B2(n_0_526), .ZN(n_0_525) + ); + AOI21_X1_LVT i_0_554( + .A(n_0_525), .B1(n_0_710), .B2(n_0_565), .ZN(n_0_524) + ); + AOI211_X1_LVT i_0_553( + .A(n_0_543), .B(n_0_524), .C1(n_29), .C2(n_0_581), .ZN(n_0_523) + ); + AND3_X1_LVT i_0_552( + .A1(n_0_532), .A2(n_0_528), .A3(n_0_523), .ZN(n_0_522) + ); + INV_X1_LVT i_0_652( + .A(n_0_621), .ZN(n_0_620) + ); + NAND2_X1_LVT i_0_565( + .A1(n_0_728), .A2(n_0_588), .ZN(n_0_535) + ); + AOI22_X1_LVT i_0_568( + .A1(n_0_723), .A2(n_0_600), .B1(op1[14]), .B2(n_0_618), .ZN(n_0_538) + ); + AOI22_X1_LVT i_0_567( + .A1(n_0_693), .A2(n_0_595), .B1(op2[2]), .B2(n_0_538), .ZN(n_0_537) + ); + INV_X1_LVT i_0_566( + .A(n_0_537), .ZN(n_0_536) + ); + OAI21_X1_LVT i_0_564( + .A(n_0_535), .B1(n_0_728), .B2(n_0_536), .ZN(n_0_534) + ); + OAI221_X1_LVT i_0_563( + .A(n_0_620), .B1(op2[0]), .B2(n_0_552), .C1(n_0_701), .C2(n_0_534), .ZN(n_0_533) + ); + NAND2_X1_LVT i_0_561( + .A1(op2[1]), .A2(n_0_573), .ZN(n_0_531) + ); + INV_X1_LVT i_0_560( + .A(n_0_531), .ZN(n_0_530) + ); + AOI22_X1_LVT i_0_559( + .A1(op1[31]), .A2(n_0_530), .B1(op1[29]), .B2(n_0_571), .ZN(n_0_529) + ); + OAI211_X1_LVT i_0_551( + .A(n_0_522), .B(n_0_533), .C1(n_0_562), .C2(n_0_529), .ZN(result[29]) + ); + INV_X1_LVT i_0_733( + .A(op2[28]), .ZN(n_0_700) + ); + AOI221_X1_LVT i_0_546( + .A(n_0_700), .B1(op1[28]), .B2(n_0_566), .C1(n_0_698), .C2(n_0_565), .ZN(n_0_517) + ); + OAI21_X1_LVT i_0_543( + .A(n_0_681), .B1(op2[28]), .B2(n_0_568), .ZN(n_0_514) + ); + AOI22_X1_LVT i_0_542( + .A1(n_28), .A2(n_0_581), .B1(op1[28]), .B2(n_0_514), .ZN(n_0_513) + ); + XNOR2_X1_LVT i_10_140( + .A(n_10_110), .B(n_10_111), .ZN(n_60) + ); + NAND2_X1_LVT i_0_544( + .A1(n_60), .A2(n_0_580), .ZN(n_0_515) + ); + NAND2_X1_LVT i_0_545( + .A1(op1[31]), .A2(n_0_574), .ZN(n_0_516) + ); + OAI211_X1_LVT i_0_541( + .A(n_0_513), .B(n_0_515), .C1(n_0_545), .C2(n_0_516), .ZN(n_0_512) + ); + AOI22_X1_LVT i_0_540( + .A1(op1[30]), .A2(n_0_530), .B1(op1[28]), .B2(n_0_571), .ZN(n_0_511) + ); + OAI22_X1_LVT i_0_539( + .A1(n_0_562), .A2(n_0_511), .B1(n_0_548), .B2(n_0_529), .ZN(n_0_510) + ); + NOR3_X1_LVT i_0_538( + .A1(n_0_517), .A2(n_0_512), .A3(n_0_510), .ZN(n_0_509) + ); + OAI22_X1_LVT i_0_550( + .A1(n_0_714), .A2(n_0_617), .B1(op2[3]), .B2(n_0_608), .ZN(n_0_521) + ); + OAI22_X1_LVT i_0_549( + .A1(op2[2]), .A2(n_0_602), .B1(n_0_693), .B2(n_0_521), .ZN(n_0_520) + ); + AOI22_X1_LVT i_0_548( + .A1(op2[1]), .A2(n_0_520), .B1(n_0_728), .B2(n_0_553), .ZN(n_0_519) + ); + OAI22_X1_LVT i_0_547( + .A1(op2[0]), .A2(n_0_534), .B1(n_0_701), .B2(n_0_519), .ZN(n_0_518) + ); + OAI21_X1_LVT i_0_537( + .A(n_0_509), .B1(n_0_621), .B2(n_0_518), .ZN(result[28]) + ); + XNOR2_X1_LVT i_10_136( + .A(n_10_107), .B(n_10_108), .ZN(n_59) + ); + AOI22_X1_LVT i_0_517( + .A1(n_27), .A2(n_0_581), .B1(n_59), .B2(n_0_580), .ZN(n_0_489) + ); + INV_X1_LVT i_0_721( + .A(op1[27]), .ZN(n_0_688) + ); + OAI21_X1_LVT i_0_516( + .A(n_0_681), .B1(op2[27]), .B2(n_0_568), .ZN(n_0_488) + ); + INV_X1_LVT i_0_515( + .A(n_0_488), .ZN(n_0_487) + ); + OAI221_X1_LVT i_0_514( + .A(n_0_489), .B1(n_0_545), .B2(n_0_516), .C1(n_0_688), .C2(n_0_487), .ZN(n_0_486) + ); + OAI21_X1_LVT i_0_530( + .A(op2[1]), .B1(n_0_710), .B2(n_0_574), .ZN(n_0_502) + ); + OAI21_X1_LVT i_0_529( + .A(n_0_728), .B1(n_0_688), .B2(n_0_574), .ZN(n_0_501) + ); + NAND2_X1_LVT i_0_528( + .A1(n_0_502), .A2(n_0_501), .ZN(n_0_500) + ); + AOI21_X1_LVT i_0_527( + .A(n_0_545), .B1(n_0_701), .B2(n_0_500), .ZN(n_0_499) + ); + NAND2_X1_LVT i_0_609( + .A1(n_0_682), .A2(n_0_578), .ZN(n_0_577) + ); + NOR2_X1_LVT i_0_526( + .A1(op2[4]), .A2(n_0_693), .ZN(n_0_498) + ); + NAND2_X1_LVT i_0_525( + .A1(n_0_723), .A2(n_0_498), .ZN(n_0_497) + ); + OAI22_X1_LVT i_0_523( + .A1(n_0_688), .A2(n_0_574), .B1(n_0_691), .B2(n_0_497), .ZN(n_0_495) + ); + OAI21_X1_LVT i_0_522( + .A(n_0_502), .B1(op2[1]), .B2(n_0_495), .ZN(n_0_494) + ); + AOI21_X1_LVT i_0_521( + .A(n_0_577), .B1(n_0_701), .B2(n_0_494), .ZN(n_0_493) + ); + NOR2_X1_LVT i_0_520( + .A1(n_0_499), .A2(n_0_493), .ZN(n_0_492) + ); + AOI21_X1_LVT i_0_519( + .A(n_0_492), .B1(op2[0]), .B2(n_0_511), .ZN(n_0_491) + ); + AOI22_X1_LVT i_0_518( + .A1(n_0_688), .A2(n_0_565), .B1(op1[27]), .B2(n_0_566), .ZN(n_0_490) + ); + AOI211_X1_LVT i_0_513( + .A(n_0_486), .B(n_0_491), .C1(op2[27]), .C2(n_0_490), .ZN(n_0_485) + ); + NOR3_X1_LVT i_0_536( + .A1(op2[4]), .A2(n_0_696), .A3(n_0_723), .ZN(n_0_508) + ); + AOI21_X1_LVT i_0_535( + .A(n_0_508), .B1(n_0_723), .B2(n_0_591), .ZN(n_0_507) + ); + OAI22_X1_LVT i_0_534( + .A1(op2[2]), .A2(n_0_592), .B1(n_0_693), .B2(n_0_507), .ZN(n_0_506) + ); + NOR2_X1_LVT i_0_533( + .A1(n_0_728), .A2(n_0_506), .ZN(n_0_505) + ); + AOI21_X1_LVT i_0_532( + .A(n_0_505), .B1(n_0_728), .B2(n_0_536), .ZN(n_0_504) + ); + OAI22_X1_LVT i_0_531( + .A1(n_0_701), .A2(n_0_504), .B1(op2[0]), .B2(n_0_519), .ZN(n_0_503) + ); + OAI21_X1_LVT i_0_512( + .A(n_0_485), .B1(n_0_621), .B2(n_0_503), .ZN(result[27]) + ); + OAI21_X1_LVT i_0_500( + .A(n_0_681), .B1(op2[26]), .B2(n_0_568), .ZN(n_0_473) + ); + NAND2_X1_LVT i_0_499( + .A1(op1[26]), .A2(n_0_473), .ZN(n_0_472) + ); + XNOR2_X1_LVT i_10_133( + .A(n_10_103), .B(n_10_106), .ZN(n_58) + ); + AOI22_X1_LVT i_0_498( + .A1(n_58), .A2(n_0_580), .B1(n_26), .B2(n_0_581), .ZN(n_0_471) + ); + INV_X1_LVT i_0_744( + .A(op1[26]), .ZN(n_0_711) + ); + OAI221_X1_LVT i_0_501( + .A(op2[26]), .B1(op1[26]), .B2(n_0_564), .C1(n_0_711), .C2(n_0_567), .ZN(n_0_474) + ); + NAND3_X1_LVT i_0_497( + .A1(n_0_472), .A2(n_0_471), .A3(n_0_474), .ZN(n_0_470) + ); + INV_X1_LVT i_0_524( + .A(n_0_497), .ZN(n_0_496) + ); + AOI22_X1_LVT i_0_505( + .A1(op1[30]), .A2(n_0_496), .B1(op1[26]), .B2(n_0_573), .ZN(n_0_478) + ); + NOR2_X1_LVT i_0_504( + .A1(op2[1]), .A2(n_0_478), .ZN(n_0_477) + ); + AOI21_X1_LVT i_0_503( + .A(n_0_477), .B1(op1[28]), .B2(n_0_530), .ZN(n_0_476) + ); + NAND2_X1_LVT i_0_502( + .A1(n_0_701), .A2(n_0_476), .ZN(n_0_475) + ); + AOI21_X1_LVT i_0_489( + .A(n_0_577), .B1(op2[0]), .B2(n_0_494), .ZN(n_0_462) + ); + AOI21_X1_LVT i_0_488( + .A(n_0_470), .B1(n_0_475), .B2(n_0_462), .ZN(n_0_461) + ); + AOI21_X1_LVT i_0_511( + .A(n_0_616), .B1(n_0_738), .B2(n_0_706), .ZN(n_0_484) + ); + AOI21_X1_LVT i_0_510( + .A(n_0_484), .B1(n_0_723), .B2(op1[19]), .ZN(n_0_483) + ); + INV_X1_LVT i_0_757( + .A(op1[3]), .ZN(n_0_724) + ); + NOR2_X1_LVT i_0_687( + .A1(n_0_724), .A2(op2[3]), .ZN(n_0_654) + ); + INV_X1_LVT i_0_686( + .A(n_0_654), .ZN(n_0_653) + ); + AOI21_X1_LVT i_0_509( + .A(n_0_483), .B1(op2[4]), .B2(n_0_653), .ZN(n_0_482) + ); + AOI22_X1_LVT i_0_508( + .A1(n_0_693), .A2(n_0_554), .B1(op2[2]), .B2(n_0_482), .ZN(n_0_481) + ); + OAI22_X1_LVT i_0_507( + .A1(n_0_728), .A2(n_0_481), .B1(op2[1]), .B2(n_0_520), .ZN(n_0_480) + ); + AOI22_X1_LVT i_0_506( + .A1(op2[0]), .A2(n_0_480), .B1(n_0_701), .B2(n_0_504), .ZN(n_0_479) + ); + NAND3_X1_LVT i_0_491( + .A1(op2[0]), .A2(n_0_516), .A3(n_0_500), .ZN(n_0_464) + ); + NAND2_X1_LVT i_0_494( + .A1(op1[31]), .A2(n_0_615), .ZN(n_0_467) + ); + OAI21_X1_LVT i_0_492( + .A(n_0_467), .B1(n_0_728), .B2(n_0_516), .ZN(n_0_465) + ); + OAI21_X1_LVT i_0_490( + .A(n_0_464), .B1(n_0_475), .B2(n_0_465), .ZN(n_0_463) + ); + OAI221_X1_LVT i_0_487( + .A(n_0_461), .B1(n_0_621), .B2(n_0_479), .C1(n_0_545), .C2(n_0_463), .ZN(result[26]) + ); + INV_X1_LVT i_10_126( + .A(n_10_100), .ZN(n_10_101) + ); + NOR2_X1_LVT i_10_127( + .A1(n_10_99), .A2(n_10_101), .ZN(n_10_102) + ); + XNOR2_X1_LVT i_10_128( + .A(n_10_97), .B(n_10_102), .ZN(n_57) + ); + AOI22_X1_LVT i_0_479( + .A1(n_57), .A2(n_0_580), .B1(n_25), .B2(n_0_581), .ZN(n_0_453) + ); + INV_X1_LVT i_0_730( + .A(op2[25]), .ZN(n_0_697) + ); + AOI21_X1_LVT i_0_478( + .A(aluBypass), .B1(n_0_697), .B2(n_0_569), .ZN(n_0_452) + ); + AOI22_X1_LVT i_0_480( + .A1(op1[25]), .A2(n_0_567), .B1(n_0_699), .B2(n_0_564), .ZN(n_0_454) + ); + OAI221_X1_LVT i_0_477( + .A(n_0_453), .B1(n_0_699), .B2(n_0_452), .C1(n_0_697), .C2(n_0_454), .ZN(n_0_451) + ); + INV_X1_LVT i_0_575( + .A(n_0_545), .ZN(n_0_544) + ); + AOI21_X1_LVT i_0_476( + .A(n_0_451), .B1(n_0_544), .B2(n_0_465), .ZN(n_0_450) + ); + AOI22_X1_LVT i_0_475( + .A1(op1[29]), .A2(n_0_496), .B1(op1[25]), .B2(n_0_573), .ZN(n_0_449) + ); + NAND2_X1_LVT i_0_474( + .A1(n_0_728), .A2(n_0_449), .ZN(n_0_448) + ); + OAI21_X1_LVT i_0_473( + .A(n_0_448), .B1(n_0_728), .B2(n_0_495), .ZN(n_0_447) + ); + OAI22_X1_LVT i_0_472( + .A1(n_0_548), .A2(n_0_476), .B1(n_0_562), .B2(n_0_447), .ZN(n_0_446) + ); + INV_X1_LVT i_0_471( + .A(n_0_446), .ZN(n_0_445) + ); + OAI222_X1_LVT i_0_486( + .A1(n_0_733), .A2(n_0_617), .B1(n_0_694), .B2(n_0_605), .C1(n_0_705), .C2(n_0_615), + .ZN(n_0_460) + ); + NOR2_X1_LVT i_0_485( + .A1(n_0_693), .A2(n_0_460), .ZN(n_0_459) + ); + AOI21_X1_LVT i_0_484( + .A(n_0_459), .B1(n_0_693), .B2(n_0_538), .ZN(n_0_458) + ); + OAI22_X1_LVT i_0_483( + .A1(n_0_728), .A2(n_0_458), .B1(op2[1]), .B2(n_0_506), .ZN(n_0_457) + ); + INV_X1_LVT i_0_482( + .A(n_0_457), .ZN(n_0_456) + ); + OAI221_X1_LVT i_0_481( + .A(n_0_620), .B1(n_0_701), .B2(n_0_456), .C1(op2[0]), .C2(n_0_480), .ZN(n_0_455) + ); + NAND3_X1_LVT i_0_470( + .A1(n_0_450), .A2(n_0_445), .A3(n_0_455), .ZN(result[25]) + ); + INV_X1_LVT i_0_493( + .A(n_0_467), .ZN(n_0_466) + ); + OAI211_X1_LVT i_0_455( + .A(n_0_544), .B(n_0_465), .C1(op2[0]), .C2(n_0_466), .ZN(n_0_430) + ); + OAI21_X1_LVT i_0_462( + .A(n_0_681), .B1(op2[24]), .B2(n_0_568), .ZN(n_0_437) + ); + XNOR2_X1_LVT i_10_120( + .A(n_10_94), .B(n_10_95), .ZN(n_56) + ); + AOI222_X1_LVT i_0_461( + .A1(op1[24]), .A2(n_0_437), .B1(n_56), .B2(n_0_580), .C1(n_24), .C2(n_0_581), + .ZN(n_0_436) + ); + INV_X1_LVT i_0_460( + .A(n_0_436), .ZN(n_0_435) + ); + AOI22_X1_LVT i_0_458( + .A1(op1[24]), .A2(n_0_573), .B1(op1[28]), .B2(n_0_496), .ZN(n_0_433) + ); + OAI22_X1_LVT i_0_457( + .A1(op2[1]), .A2(n_0_433), .B1(n_0_728), .B2(n_0_478), .ZN(n_0_432) + ); + INV_X1_LVT i_0_456( + .A(n_0_432), .ZN(n_0_431) + ); + OAI22_X1_LVT i_0_454( + .A1(n_0_562), .A2(n_0_431), .B1(n_0_548), .B2(n_0_447), .ZN(n_0_429) + ); + AOI22_X1_LVT i_0_459( + .A1(n_0_736), .A2(n_0_565), .B1(op1[24]), .B2(n_0_566), .ZN(n_0_434) + ); + AOI211_X1_LVT i_0_453( + .A(n_0_435), .B(n_0_429), .C1(op2[24]), .C2(n_0_434), .ZN(n_0_428) + ); + NAND2_X1_LVT i_0_467( + .A1(n_0_693), .A2(n_0_521), .ZN(n_0_442) + ); + NOR2_X1_LVT i_0_469( + .A1(op2[3]), .A2(n_0_603), .ZN(n_0_444) + ); + AOI21_X1_LVT i_0_468( + .A(n_0_444), .B1(op1[9]), .B2(n_0_618), .ZN(n_0_443) + ); + OAI21_X1_LVT i_0_466( + .A(n_0_442), .B1(n_0_693), .B2(n_0_443), .ZN(n_0_441) + ); + NAND2_X1_LVT i_0_465( + .A1(op2[1]), .A2(n_0_441), .ZN(n_0_440) + ); + OAI21_X1_LVT i_0_464( + .A(n_0_440), .B1(op2[1]), .B2(n_0_481), .ZN(n_0_439) + ); + OAI221_X1_LVT i_0_463( + .A(n_0_620), .B1(op2[0]), .B2(n_0_456), .C1(n_0_701), .C2(n_0_439), .ZN(n_0_438) + ); + NAND3_X1_LVT i_0_452( + .A1(n_0_430), .A2(n_0_428), .A3(n_0_438), .ZN(result[24]) + ); + INV_X1_LVT i_0_751( + .A(op2[23]), .ZN(n_0_718) + ); + AOI221_X1_LVT i_0_440( + .A(n_0_718), .B1(op1[23]), .B2(n_0_566), .C1(n_0_719), .C2(n_0_565), .ZN(n_0_416) + ); + INV_X1_LVT i_10_115( + .A(n_10_91), .ZN(n_10_92) + ); + NOR2_X1_LVT i_10_116( + .A1(n_10_90), .A2(n_10_92), .ZN(n_10_93) + ); + XNOR2_X1_LVT i_10_117( + .A(n_10_88), .B(n_10_93), .ZN(n_55) + ); + AOI222_X1_LVT i_0_438( + .A1(n_23), .A2(n_0_581), .B1(n_0_544), .B2(n_0_466), .C1(n_55), .C2(n_0_580), + .ZN(n_0_414) + ); + OAI21_X1_LVT i_0_437( + .A(n_0_414), .B1(n_0_548), .B2(n_0_431), .ZN(n_0_413) + ); + OAI21_X1_LVT i_0_439( + .A(n_0_681), .B1(op2[23]), .B2(n_0_568), .ZN(n_0_415) + ); + AOI211_X1_LVT i_0_436( + .A(n_0_416), .B(n_0_413), .C1(op1[23]), .C2(n_0_415), .ZN(n_0_412) + ); + AOI22_X1_LVT i_0_444( + .A1(n_0_723), .A2(n_0_719), .B1(op2[3]), .B2(n_0_691), .ZN(n_0_420) + ); + AOI22_X1_LVT i_0_443( + .A1(n_0_575), .A2(n_0_420), .B1(op1[27]), .B2(n_0_496), .ZN(n_0_419) + ); + AOI22_X1_LVT i_0_442( + .A1(op2[1]), .A2(n_0_449), .B1(n_0_728), .B2(n_0_419), .ZN(n_0_418) + ); + INV_X1_LVT i_0_441( + .A(n_0_418), .ZN(n_0_417) + ); + NAND2_X1_LVT i_0_447( + .A1(n_0_728), .A2(n_0_458), .ZN(n_0_423) + ); + NOR2_X1_LVT i_0_451( + .A1(op2[3]), .A2(n_0_594), .ZN(n_0_427) + ); + AOI21_X1_LVT i_0_450( + .A(n_0_427), .B1(op1[8]), .B2(n_0_618), .ZN(n_0_426) + ); + OAI22_X1_LVT i_0_449( + .A1(n_0_693), .A2(n_0_426), .B1(op2[2]), .B2(n_0_507), .ZN(n_0_425) + ); + INV_X1_LVT i_0_448( + .A(n_0_425), .ZN(n_0_424) + ); + OAI21_X1_LVT i_0_446( + .A(n_0_423), .B1(n_0_728), .B2(n_0_424), .ZN(n_0_422) + ); + AOI22_X1_LVT i_0_445( + .A1(op2[0]), .A2(n_0_422), .B1(n_0_701), .B2(n_0_439), .ZN(n_0_421) + ); + OAI221_X1_LVT i_0_435( + .A(n_0_412), .B1(n_0_562), .B2(n_0_417), .C1(n_0_621), .C2(n_0_421), .ZN(result[23]) + ); + XNOR2_X1_LVT i_10_109( + .A(n_10_85), .B(n_10_86), .ZN(n_54) + ); + AOI22_X1_LVT i_0_419( + .A1(n_54), .A2(n_0_580), .B1(n_22), .B2(n_0_581), .ZN(n_0_396) + ); + INV_X1_LVT i_0_719( + .A(op2[22]), .ZN(n_0_686) + ); + AOI21_X1_LVT i_0_420( + .A(aluBypass), .B1(n_0_686), .B2(n_0_569), .ZN(n_0_397) + ); + OAI21_X1_LVT i_0_418( + .A(n_0_396), .B1(n_0_687), .B2(n_0_397), .ZN(n_0_395) + ); + AOI22_X1_LVT i_0_421( + .A1(op1[22]), .A2(n_0_566), .B1(n_0_687), .B2(n_0_565), .ZN(n_0_398) + ); + AOI21_X1_LVT i_0_417( + .A(n_0_395), .B1(op2[22]), .B2(n_0_398), .ZN(n_0_394) + ); + NAND2_X1_LVT i_0_432( + .A1(n_0_728), .A2(n_0_441), .ZN(n_0_409) + ); + AND2_X1_LVT i_0_434( + .A1(n_0_738), .A2(n_0_619), .ZN(n_0_411) + ); + AOI22_X1_LVT i_0_433( + .A1(n_0_693), .A2(n_0_482), .B1(op2[2]), .B2(n_0_411), .ZN(n_0_410) + ); + OAI21_X1_LVT i_0_431( + .A(n_0_409), .B1(n_0_728), .B2(n_0_410), .ZN(n_0_408) + ); + OAI22_X1_LVT i_0_430( + .A1(n_0_701), .A2(n_0_408), .B1(op2[0]), .B2(n_0_422), .ZN(n_0_407) + ); + AOI22_X1_LVT i_0_429( + .A1(n_0_723), .A2(n_0_687), .B1(op2[3]), .B2(n_0_717), .ZN(n_0_406) + ); + AOI22_X1_LVT i_0_428( + .A1(n_0_575), .A2(n_0_406), .B1(op1[26]), .B2(n_0_496), .ZN(n_0_405) + ); + AND2_X1_LVT i_0_427( + .A1(n_0_728), .A2(n_0_405), .ZN(n_0_404) + ); + AOI21_X1_LVT i_0_426( + .A(n_0_404), .B1(op2[1]), .B2(n_0_433), .ZN(n_0_403) + ); + INV_X1_LVT i_0_425( + .A(n_0_403), .ZN(n_0_402) + ); + OAI222_X1_LVT i_0_424( + .A1(n_0_545), .A2(n_0_467), .B1(n_0_701), .B2(n_0_417), .C1(op2[0]), .C2(n_0_402), + .ZN(n_0_401) + ); + NOR2_X1_LVT i_0_496( + .A1(n_0_738), .A2(n_0_691), .ZN(n_0_469) + ); + INV_X1_LVT i_0_495( + .A(n_0_469), .ZN(n_0_468) + ); + NAND3_X1_LVT i_0_423( + .A1(n_0_693), .A2(n_0_468), .A3(n_0_404), .ZN(n_0_400) + ); + OAI21_X1_LVT i_0_422( + .A(n_0_401), .B1(op2[0]), .B2(n_0_400), .ZN(n_0_399) + ); + OAI221_X1_LVT i_0_416( + .A(n_0_394), .B1(n_0_621), .B2(n_0_407), .C1(n_0_579), .C2(n_0_399), .ZN(result[22]) + ); + INV_X1_LVT i_0_759( + .A(op1[21]), .ZN(n_0_726) + ); + AOI22_X1_LVT i_0_399( + .A1(op1[21]), .A2(n_0_566), .B1(n_0_726), .B2(n_0_565), .ZN(n_0_377) + ); + NOR2_X1_LVT i_0_692( + .A1(n_0_726), .A2(op2[21]), .ZN(n_0_659) + ); + AOI222_X1_LVT i_0_398( + .A1(op2[21]), .A2(n_0_377), .B1(n_21), .B2(n_0_581), .C1(n_0_659), .C2(n_0_569), + .ZN(n_0_376) + ); + INV_X1_LVT i_0_397( + .A(n_0_376), .ZN(n_0_375) + ); + INV_X1_LVT i_10_104( + .A(n_10_82), .ZN(n_10_83) + ); + NOR2_X1_LVT i_10_105( + .A1(n_10_81), .A2(n_10_83), .ZN(n_10_84) + ); + XNOR2_X1_LVT i_10_106( + .A(n_10_79), .B(n_10_84), .ZN(n_53) + ); + AOI221_X1_LVT i_0_396( + .A(n_0_375), .B1(n_53), .B2(n_0_580), .C1(op1[21]), .C2(aluBypass), .ZN(n_0_374) + ); + INV_X1_LVT i_0_608( + .A(n_0_577), .ZN(n_0_576) + ); + NAND2_X1_LVT i_0_403( + .A1(op2[0]), .A2(n_0_402), .ZN(n_0_381) + ); + AND2_X1_LVT i_0_410( + .A1(op2[1]), .A2(n_0_419), .ZN(n_0_388) + ); + OAI22_X1_LVT i_0_408( + .A1(n_0_723), .A2(n_0_710), .B1(n_0_726), .B2(op2[3]), .ZN(n_0_386) + ); + AOI22_X1_LVT i_0_407( + .A1(n_0_575), .A2(n_0_386), .B1(op1[25]), .B2(n_0_496), .ZN(n_0_385) + ); + AOI21_X1_LVT i_0_395( + .A(n_0_388), .B1(n_0_728), .B2(n_0_385), .ZN(n_0_373) + ); + OAI211_X1_LVT i_0_394( + .A(n_0_576), .B(n_0_381), .C1(op2[0]), .C2(n_0_373), .ZN(n_0_372) + ); + AOI21_X1_LVT i_0_402( + .A(n_0_381), .B1(n_0_466), .B2(n_0_400), .ZN(n_0_380) + ); + INV_X1_LVT i_0_401( + .A(n_0_380), .ZN(n_0_379) + ); + NOR2_X1_LVT i_0_409( + .A1(n_0_575), .A2(n_0_467), .ZN(n_0_387) + ); + INV_X1_LVT i_0_406( + .A(n_0_385), .ZN(n_0_384) + ); + NOR2_X1_LVT i_0_405( + .A1(n_0_387), .A2(n_0_384), .ZN(n_0_383) + ); + AOI22_X1_LVT i_0_404( + .A1(n_0_467), .A2(n_0_388), .B1(n_0_728), .B2(n_0_383), .ZN(n_0_382) + ); + OAI211_X1_LVT i_0_400( + .A(n_0_544), .B(n_0_379), .C1(op2[0]), .C2(n_0_382), .ZN(n_0_378) + ); + AOI22_X1_LVT i_0_415( + .A1(op1[14]), .A2(n_0_616), .B1(op1[6]), .B2(n_0_618), .ZN(n_0_393) + ); + NOR2_X1_LVT i_0_414( + .A1(n_0_693), .A2(n_0_393), .ZN(n_0_392) + ); + AOI21_X1_LVT i_0_413( + .A(n_0_392), .B1(n_0_693), .B2(n_0_460), .ZN(n_0_391) + ); + OAI22_X1_LVT i_0_412( + .A1(n_0_728), .A2(n_0_391), .B1(op2[1]), .B2(n_0_424), .ZN(n_0_390) + ); + OAI221_X1_LVT i_0_411( + .A(n_0_620), .B1(op2[0]), .B2(n_0_408), .C1(n_0_701), .C2(n_0_390), .ZN(n_0_389) + ); + NAND4_X1_LVT i_0_393( + .A1(n_0_374), .A2(n_0_372), .A3(n_0_378), .A4(n_0_389), .ZN(result[21]) + ); + OAI221_X1_LVT i_0_388( + .A(op2[20]), .B1(n_0_727), .B2(n_0_567), .C1(op1[20]), .C2(n_0_564), .ZN(n_0_367) + ); + NOR2_X1_LVT i_0_691( + .A1(n_0_727), .A2(op2[20]), .ZN(n_0_658) + ); + AOI22_X1_LVT i_0_387( + .A1(op1[20]), .A2(aluBypass), .B1(n_0_658), .B2(n_0_569), .ZN(n_0_366) + ); + XNOR2_X1_LVT i_10_98( + .A(n_10_76), .B(n_10_77), .ZN(n_52) + ); + AOI22_X1_LVT i_0_386( + .A1(n_52), .A2(n_0_580), .B1(n_20), .B2(n_0_581), .ZN(n_0_365) + ); + AOI221_X1_LVT i_0_392( + .A(op2[4]), .B1(n_0_727), .B2(n_0_723), .C1(op2[3]), .C2(n_0_698), .ZN(n_0_371) + ); + AOI22_X1_LVT i_0_391( + .A1(op1[24]), .A2(n_0_496), .B1(n_0_693), .B2(n_0_371), .ZN(n_0_370) + ); + OAI22_X1_LVT i_0_390( + .A1(op2[1]), .A2(n_0_370), .B1(n_0_728), .B2(n_0_405), .ZN(n_0_369) + ); + OAI221_X1_LVT i_0_385( + .A(n_0_576), .B1(n_0_701), .B2(n_0_373), .C1(op2[0]), .C2(n_0_369), .ZN(n_0_364) + ); + AND4_X1_LVT i_0_384( + .A1(n_0_367), .A2(n_0_366), .A3(n_0_365), .A4(n_0_364), .ZN(n_0_363) + ); + AOI22_X1_LVT i_0_383( + .A1(op1[13]), .A2(n_0_616), .B1(op1[5]), .B2(n_0_618), .ZN(n_0_362) + ); + AOI22_X1_LVT i_0_382( + .A1(op2[2]), .A2(n_0_362), .B1(n_0_693), .B2(n_0_443), .ZN(n_0_361) + ); + NAND2_X1_LVT i_0_381( + .A1(op2[1]), .A2(n_0_361), .ZN(n_0_360) + ); + OAI21_X1_LVT i_0_380( + .A(n_0_360), .B1(op2[1]), .B2(n_0_410), .ZN(n_0_359) + ); + OAI221_X1_LVT i_0_379( + .A(n_0_620), .B1(n_0_701), .B2(n_0_359), .C1(op2[0]), .C2(n_0_390), .ZN(n_0_358) + ); + OR2_X1_LVT i_0_389( + .A1(n_0_387), .A2(n_0_369), .ZN(n_0_368) + ); + AOI22_X1_LVT i_0_378( + .A1(op2[0]), .A2(n_0_382), .B1(n_0_701), .B2(n_0_368), .ZN(n_0_357) + ); + OAI211_X1_LVT i_0_377( + .A(n_0_363), .B(n_0_358), .C1(n_0_545), .C2(n_0_357), .ZN(result[20]) + ); + OAI22_X1_LVT i_0_370( + .A1(op2[3]), .A2(n_0_689), .B1(n_0_723), .B2(n_0_688), .ZN(n_0_350) + ); + AND2_X1_LVT i_0_369( + .A1(n_0_738), .A2(n_0_350), .ZN(n_0_349) + ); + AOI22_X1_LVT i_0_368( + .A1(n_0_498), .A2(n_0_420), .B1(n_0_693), .B2(n_0_349), .ZN(n_0_348) + ); + AND2_X1_LVT i_0_367( + .A1(n_0_728), .A2(n_0_348), .ZN(n_0_347) + ); + AOI21_X1_LVT i_0_359( + .A(n_0_347), .B1(op2[1]), .B2(n_0_385), .ZN(n_0_339) + ); + OAI221_X1_LVT i_0_357( + .A(n_0_576), .B1(n_0_701), .B2(n_0_369), .C1(op2[0]), .C2(n_0_339), .ZN(n_0_337) + ); + NAND2_X1_LVT i_0_363( + .A1(n_19), .A2(n_0_581), .ZN(n_0_343) + ); + INV_X1_LVT i_0_723( + .A(op2[19]), .ZN(n_0_690) + ); + AOI221_X1_LVT i_0_364( + .A(n_0_690), .B1(n_0_689), .B2(n_0_565), .C1(op1[19]), .C2(n_0_566), .ZN(n_0_344) + ); + XNOR2_X1_LVT i_10_94( + .A(n_10_73), .B(n_10_74), .ZN(n_51) + ); + AOI221_X1_LVT i_0_361( + .A(n_0_344), .B1(op1[19]), .B2(aluBypass), .C1(n_51), .C2(n_0_580), .ZN(n_0_341) + ); + NAND3_X1_LVT i_0_362( + .A1(n_0_690), .A2(op1[19]), .A3(n_0_569), .ZN(n_0_342) + ); + NAND3_X1_LVT i_0_360( + .A1(n_0_343), .A2(n_0_341), .A3(n_0_342), .ZN(n_0_340) + ); + AOI22_X1_LVT i_0_376( + .A1(op1[12]), .A2(n_0_616), .B1(op1[4]), .B2(n_0_618), .ZN(n_0_356) + ); + OAI22_X1_LVT i_0_375( + .A1(n_0_693), .A2(n_0_356), .B1(op2[2]), .B2(n_0_426), .ZN(n_0_355) + ); + INV_X1_LVT i_0_374( + .A(n_0_355), .ZN(n_0_354) + ); + OAI22_X1_LVT i_0_373( + .A1(op2[1]), .A2(n_0_391), .B1(n_0_728), .B2(n_0_354), .ZN(n_0_353) + ); + AOI22_X1_LVT i_0_372( + .A1(n_0_701), .A2(n_0_359), .B1(op2[0]), .B2(n_0_353), .ZN(n_0_352) + ); + INV_X1_LVT i_0_371( + .A(n_0_352), .ZN(n_0_351) + ); + AOI21_X1_LVT i_0_358( + .A(n_0_340), .B1(n_0_620), .B2(n_0_351), .ZN(n_0_338) + ); + AOI22_X1_LVT i_0_366( + .A1(n_0_468), .A2(n_0_347), .B1(op2[1]), .B2(n_0_383), .ZN(n_0_346) + ); + AOI22_X1_LVT i_0_365( + .A1(n_0_701), .A2(n_0_346), .B1(op2[0]), .B2(n_0_368), .ZN(n_0_345) + ); + OAI211_X1_LVT i_0_356( + .A(n_0_337), .B(n_0_338), .C1(n_0_545), .C2(n_0_345), .ZN(result[19]) + ); + XNOR2_X1_LVT i_10_90( + .A(n_10_70), .B(n_10_71), .ZN(n_50) + ); + NAND2_X1_LVT i_0_342( + .A1(n_50), .A2(n_0_580), .ZN(n_0_323) + ); + OAI21_X1_LVT i_0_343( + .A(n_0_681), .B1(op2[18]), .B2(n_0_568), .ZN(n_0_324) + ); + AOI22_X1_LVT i_0_341( + .A1(op1[18]), .A2(n_0_324), .B1(n_18), .B2(n_0_581), .ZN(n_0_322) + ); + OAI221_X1_LVT i_0_340( + .A(op2[18]), .B1(n_0_705), .B2(n_0_567), .C1(op1[18]), .C2(n_0_564), .ZN(n_0_321) + ); + NAND3_X1_LVT i_0_339( + .A1(n_0_323), .A2(n_0_322), .A3(n_0_321), .ZN(n_0_320) + ); + OAI22_X1_LVT i_0_351( + .A1(op2[3]), .A2(n_0_705), .B1(n_0_723), .B2(n_0_711), .ZN(n_0_332) + ); + AND2_X1_LVT i_0_350( + .A1(n_0_738), .A2(n_0_332), .ZN(n_0_331) + ); + AOI22_X1_LVT i_0_349( + .A1(n_0_498), .A2(n_0_406), .B1(n_0_693), .B2(n_0_331), .ZN(n_0_330) + ); + NAND2_X1_LVT i_0_348( + .A1(n_0_728), .A2(n_0_330), .ZN(n_0_329) + ); + NAND2_X1_LVT i_0_347( + .A1(op2[1]), .A2(n_0_370), .ZN(n_0_328) + ); + AND2_X1_LVT i_0_338( + .A1(n_0_329), .A2(n_0_328), .ZN(n_0_319) + ); + OAI22_X1_LVT i_0_337( + .A1(op2[0]), .A2(n_0_319), .B1(n_0_701), .B2(n_0_339), .ZN(n_0_318) + ); + INV_X1_LVT i_0_336( + .A(n_0_318), .ZN(n_0_317) + ); + AOI21_X1_LVT i_0_335( + .A(n_0_320), .B1(n_0_578), .B2(n_0_317), .ZN(n_0_316) + ); + OAI22_X1_LVT i_0_346( + .A1(n_0_469), .A2(n_0_329), .B1(n_0_387), .B2(n_0_328), .ZN(n_0_327) + ); + NAND2_X1_LVT i_0_344( + .A1(n_0_544), .A2(n_0_346), .ZN(n_0_325) + ); + NAND2_X1_LVT i_0_354( + .A1(n_0_728), .A2(n_0_361), .ZN(n_0_335) + ); + AOI22_X1_LVT i_0_355( + .A1(n_0_612), .A2(n_0_498), .B1(n_0_693), .B2(n_0_411), .ZN(n_0_336) + ); + OAI21_X1_LVT i_0_353( + .A(n_0_335), .B1(n_0_728), .B2(n_0_336), .ZN(n_0_334) + ); + AOI22_X1_LVT i_0_352( + .A1(n_0_701), .A2(n_0_353), .B1(op2[0]), .B2(n_0_334), .ZN(n_0_333) + ); + OAI221_X1_LVT i_0_334( + .A(n_0_316), .B1(n_0_327), .B2(n_0_325), .C1(n_0_621), .C2(n_0_333), .ZN(result[18]) + ); + NAND2_X1_LVT i_0_325( + .A1(n_17), .A2(n_0_581), .ZN(n_0_307) + ); + INV_X1_LVT i_0_765( + .A(op1[17]), .ZN(n_0_732) + ); + AOI22_X1_LVT i_0_324( + .A1(n_0_732), .A2(n_0_565), .B1(op1[17]), .B2(n_0_566), .ZN(n_0_306) + ); + NOR2_X1_LVT i_0_693( + .A1(n_0_732), .A2(op2[17]), .ZN(n_0_660) + ); + XNOR2_X1_LVT i_10_86( + .A(n_10_67), .B(n_10_68), .ZN(n_49) + ); + AOI222_X1_LVT i_0_323( + .A1(op2[17]), .A2(n_0_306), .B1(n_0_660), .B2(n_0_569), .C1(n_49), .C2(n_0_580), + .ZN(n_0_305) + ); + OAI211_X1_LVT i_0_322( + .A(n_0_307), .B(n_0_305), .C1(n_0_732), .C2(n_0_681), .ZN(n_0_304) + ); + AOI22_X1_LVT i_0_331( + .A1(op2[3]), .A2(op1[25]), .B1(op1[17]), .B2(n_0_723), .ZN(n_0_313) + ); + NOR2_X1_LVT i_0_330( + .A1(op2[4]), .A2(n_0_313), .ZN(n_0_312) + ); + AOI22_X1_LVT i_0_329( + .A1(n_0_498), .A2(n_0_386), .B1(n_0_693), .B2(n_0_312), .ZN(n_0_311) + ); + OAI22_X1_LVT i_0_328( + .A1(op2[1]), .A2(n_0_311), .B1(n_0_728), .B2(n_0_348), .ZN(n_0_310) + ); + OR2_X1_LVT i_0_327( + .A1(op2[0]), .A2(n_0_310), .ZN(n_0_309) + ); + OAI21_X1_LVT i_0_321( + .A(n_0_576), .B1(n_0_701), .B2(n_0_319), .ZN(n_0_303) + ); + INV_X1_LVT i_0_320( + .A(n_0_303), .ZN(n_0_302) + ); + AOI21_X1_LVT i_0_319( + .A(n_0_304), .B1(n_0_309), .B2(n_0_302), .ZN(n_0_301) + ); + INV_X1_LVT i_0_345( + .A(n_0_327), .ZN(n_0_326) + ); + OAI22_X1_LVT i_0_326( + .A1(n_0_701), .A2(n_0_326), .B1(n_0_469), .B2(n_0_309), .ZN(n_0_308) + ); + NOR2_X1_LVT i_0_318( + .A1(op2[2]), .A2(n_0_393), .ZN(n_0_300) + ); + AOI21_X1_LVT i_0_317( + .A(n_0_300), .B1(n_0_597), .B2(n_0_498), .ZN(n_0_299) + ); + OAI22_X1_LVT i_0_316( + .A1(n_0_728), .A2(n_0_299), .B1(op2[1]), .B2(n_0_354), .ZN(n_0_298) + ); + OAI22_X1_LVT i_0_315( + .A1(op2[0]), .A2(n_0_334), .B1(n_0_701), .B2(n_0_298), .ZN(n_0_297) + ); + OAI221_X1_LVT i_0_314( + .A(n_0_301), .B1(n_0_545), .B2(n_0_308), .C1(n_0_621), .C2(n_0_297), .ZN(result[17]) + ); + XNOR2_X1_LVT i_10_82( + .A(n_10_64), .B(n_10_65), .ZN(n_48) + ); + AOI22_X1_LVT i_0_301( + .A1(n_48), .A2(n_0_580), .B1(n_16), .B2(n_0_581), .ZN(n_0_284) + ); + NAND2_X1_LVT i_0_333( + .A1(n_0_544), .A2(n_0_469), .ZN(n_0_315) + ); + INV_X1_LVT i_0_332( + .A(n_0_315), .ZN(n_0_314) + ); + OAI21_X1_LVT i_0_302( + .A(n_0_681), .B1(op2[16]), .B2(n_0_568), .ZN(n_0_285) + ); + AOI21_X1_LVT i_0_300( + .A(n_0_314), .B1(op1[16]), .B2(n_0_285), .ZN(n_0_283) + ); + INV_X1_LVT i_0_772( + .A(op1[16]), .ZN(n_0_739) + ); + OAI221_X1_LVT i_0_303( + .A(op2[16]), .B1(op1[16]), .B2(n_0_564), .C1(n_0_739), .C2(n_0_567), .ZN(n_0_286) + ); + NAND3_X1_LVT i_0_299( + .A1(n_0_284), .A2(n_0_283), .A3(n_0_286), .ZN(n_0_282) + ); + INV_X1_LVT i_0_593( + .A(n_0_562), .ZN(n_0_561) + ); + OAI22_X1_LVT i_0_307( + .A1(op1[16]), .A2(op2[3]), .B1(op1[24]), .B2(n_0_723), .ZN(n_0_290) + ); + NOR2_X1_LVT i_0_306( + .A1(op2[4]), .A2(n_0_290), .ZN(n_0_289) + ); + AOI22_X1_LVT i_0_305( + .A1(n_0_693), .A2(n_0_289), .B1(op2[2]), .B2(n_0_371), .ZN(n_0_288) + ); + OAI22_X1_LVT i_0_304( + .A1(n_0_728), .A2(n_0_330), .B1(op2[1]), .B2(n_0_288), .ZN(n_0_287) + ); + AOI221_X1_LVT i_0_298( + .A(n_0_282), .B1(n_0_547), .B2(n_0_310), .C1(n_0_561), .C2(n_0_287), .ZN(n_0_281) + ); + INV_X1_LVT i_0_762( + .A(op1[1]), .ZN(n_0_729) + ); + OAI22_X1_LVT i_0_313( + .A1(n_0_722), .A2(n_0_615), .B1(n_0_729), .B2(n_0_617), .ZN(n_0_296) + ); + NAND2_X1_LVT i_0_312( + .A1(op2[2]), .A2(n_0_296), .ZN(n_0_295) + ); + OAI21_X1_LVT i_0_311( + .A(n_0_295), .B1(op2[2]), .B2(n_0_362), .ZN(n_0_294) + ); + NAND2_X1_LVT i_0_310( + .A1(op2[1]), .A2(n_0_294), .ZN(n_0_293) + ); + OAI21_X1_LVT i_0_309( + .A(n_0_293), .B1(op2[1]), .B2(n_0_336), .ZN(n_0_292) + ); + OAI22_X1_LVT i_0_308( + .A1(op2[0]), .A2(n_0_298), .B1(n_0_701), .B2(n_0_292), .ZN(n_0_291) + ); + OAI21_X1_LVT i_0_297( + .A(n_0_281), .B1(n_0_621), .B2(n_0_291), .ZN(result[16]) + ); + OAI221_X1_LVT i_0_286( + .A(op2[15]), .B1(n_0_734), .B2(n_0_567), .C1(op1[15]), .C2(n_0_564), .ZN(n_0_270) + ); + AOI21_X1_LVT i_0_288( + .A(n_0_314), .B1(n_15), .B2(n_0_581), .ZN(n_0_272) + ); + INV_X1_LVT i_0_287( + .A(n_0_272), .ZN(n_0_271) + ); + XNOR2_X1_LVT i_10_78( + .A(n_10_61), .B(n_10_62), .ZN(n_47) + ); + OAI21_X1_LVT i_0_285( + .A(n_0_681), .B1(op2[15]), .B2(n_0_568), .ZN(n_0_269) + ); + AOI221_X1_LVT i_0_284( + .A(n_0_271), .B1(n_47), .B2(n_0_580), .C1(op1[15]), .C2(n_0_269), .ZN(n_0_268) + ); + AOI22_X1_LVT i_0_296( + .A1(op1[8]), .A2(n_0_616), .B1(op1[0]), .B2(n_0_618), .ZN(n_0_280) + ); + AOI22_X1_LVT i_0_295( + .A1(op2[2]), .A2(n_0_280), .B1(n_0_693), .B2(n_0_356), .ZN(n_0_279) + ); + NAND2_X1_LVT i_0_294( + .A1(op2[1]), .A2(n_0_279), .ZN(n_0_278) + ); + OAI21_X1_LVT i_0_293( + .A(n_0_278), .B1(op2[1]), .B2(n_0_299), .ZN(n_0_277) + ); + OAI221_X1_LVT i_0_292( + .A(n_0_620), .B1(n_0_701), .B2(n_0_277), .C1(op2[0]), .C2(n_0_292), .ZN(n_0_276) + ); + OAI222_X1_LVT i_0_291( + .A1(n_0_719), .A2(n_0_617), .B1(n_0_691), .B2(n_0_605), .C1(n_0_734), .C2(n_0_615), + .ZN(n_0_275) + ); + OAI22_X1_LVT i_0_290( + .A1(n_0_693), .A2(n_0_349), .B1(op2[2]), .B2(n_0_275), .ZN(n_0_274) + ); + OAI22_X1_LVT i_0_289( + .A1(op2[1]), .A2(n_0_274), .B1(n_0_728), .B2(n_0_311), .ZN(n_0_273) + ); + AOI22_X1_LVT i_0_283( + .A1(n_0_561), .A2(n_0_273), .B1(n_0_547), .B2(n_0_287), .ZN(n_0_267) + ); + NAND4_X1_LVT i_0_282( + .A1(n_0_270), .A2(n_0_268), .A3(n_0_276), .A4(n_0_267), .ZN(result[15]) + ); + NOR2_X1_LVT i_0_278( + .A1(op2[0]), .A2(n_0_277), .ZN(n_0_263) + ); + NAND2_X1_LVT i_0_281( + .A1(n_0_612), .A2(n_0_575), .ZN(n_0_266) + ); + OAI21_X1_LVT i_0_280( + .A(n_0_266), .B1(n_0_713), .B2(n_0_497), .ZN(n_0_265) + ); + AOI22_X1_LVT i_0_279( + .A1(op2[1]), .A2(n_0_265), .B1(n_0_728), .B2(n_0_294), .ZN(n_0_264) + ); + AOI211_X1_LVT i_0_277( + .A(n_0_263), .B(n_0_621), .C1(op2[0]), .C2(n_0_264), .ZN(n_0_262) + ); + INV_X1_LVT i_0_754( + .A(op1[14]), .ZN(n_0_721) + ); + OAI21_X1_LVT i_0_273( + .A(op2[14]), .B1(n_0_721), .B2(n_0_567), .ZN(n_0_258) + ); + AOI21_X1_LVT i_0_272( + .A(n_0_258), .B1(n_0_721), .B2(n_0_565), .ZN(n_0_257) + ); + XNOR2_X1_LVT i_10_74( + .A(n_10_58), .B(n_10_59), .ZN(n_46) + ); + OAI21_X1_LVT i_0_276( + .A(n_0_681), .B1(op2[14]), .B2(n_0_568), .ZN(n_0_261) + ); + AOI222_X1_LVT i_0_275( + .A1(n_14), .A2(n_0_581), .B1(n_46), .B2(n_0_580), .C1(op1[14]), .C2(n_0_261), + .ZN(n_0_260) + ); + INV_X1_LVT i_0_274( + .A(n_0_260), .ZN(n_0_259) + ); + OAI222_X1_LVT i_0_271( + .A1(n_0_717), .A2(n_0_605), .B1(n_0_687), .B2(n_0_617), .C1(n_0_721), .C2(n_0_615), + .ZN(n_0_256) + ); + OAI22_X1_LVT i_0_270( + .A1(n_0_693), .A2(n_0_331), .B1(op2[2]), .B2(n_0_256), .ZN(n_0_255) + ); + AND2_X1_LVT i_0_269( + .A1(n_0_728), .A2(n_0_255), .ZN(n_0_254) + ); + NOR3_X1_LVT i_0_265( + .A1(op2[3]), .A2(op2[2]), .A3(op2[0]), .ZN(n_0_250) + ); + AOI21_X1_LVT i_0_268( + .A(n_0_254), .B1(op2[1]), .B2(n_0_288), .ZN(n_0_253) + ); + OAI22_X1_LVT i_0_266( + .A1(op2[0]), .A2(n_0_253), .B1(n_0_701), .B2(n_0_273), .ZN(n_0_251) + ); + AOI221_X1_LVT i_0_259( + .A(n_0_579), .B1(n_0_254), .B2(n_0_250), .C1(n_0_315), .C2(n_0_251), .ZN(n_0_244) + ); + OR4_X1_LVT i_0_258( + .A1(n_0_262), .A2(n_0_257), .A3(n_0_259), .A4(n_0_244), .ZN(result[14]) + ); + OAI221_X1_LVT i_0_245( + .A(op2[13]), .B1(op1[13]), .B2(n_0_564), .C1(n_0_714), .C2(n_0_567), .ZN(n_0_231) + ); + NAND2_X1_LVT i_0_244( + .A1(n_13), .A2(n_0_581), .ZN(n_0_230) + ); + OAI211_X1_LVT i_0_243( + .A(n_0_231), .B(n_0_230), .C1(n_0_714), .C2(n_0_681), .ZN(n_0_229) + ); + XNOR2_X1_LVT i_10_70( + .A(n_10_55), .B(n_10_56), .ZN(n_45) + ); + NOR2_X1_LVT i_0_695( + .A1(op2[13]), .A2(n_0_714), .ZN(n_0_662) + ); + AOI221_X1_LVT i_0_242( + .A(n_0_229), .B1(n_45), .B2(n_0_580), .C1(n_0_662), .C2(n_0_569), .ZN(n_0_228) + ); + INV_X1_LVT i_0_267( + .A(n_0_253), .ZN(n_0_252) + ); + OAI222_X1_LVT i_0_257( + .A1(n_0_714), .A2(n_0_615), .B1(n_0_726), .B2(n_0_617), .C1(n_0_710), .C2(n_0_605), + .ZN(n_0_243) + ); + OAI22_X1_LVT i_0_256( + .A1(n_0_693), .A2(n_0_312), .B1(op2[2]), .B2(n_0_243), .ZN(n_0_242) + ); + NAND2_X1_LVT i_0_255( + .A1(n_0_728), .A2(n_0_242), .ZN(n_0_241) + ); + NAND2_X1_LVT i_0_254( + .A1(op2[1]), .A2(n_0_274), .ZN(n_0_240) + ); + NAND2_X1_LVT i_0_241( + .A1(n_0_241), .A2(n_0_240), .ZN(n_0_227) + ); + OAI221_X1_LVT i_0_240( + .A(n_0_228), .B1(n_0_548), .B2(n_0_252), .C1(n_0_562), .C2(n_0_227), .ZN(n_0_226) + ); + NAND2_X1_LVT i_0_249( + .A1(n_0_728), .A2(n_0_279), .ZN(n_0_235) + ); + AOI22_X1_LVT i_0_250( + .A1(n_0_597), .A2(n_0_575), .B1(op1[6]), .B2(n_0_496), .ZN(n_0_236) + ); + OAI21_X1_LVT i_0_248( + .A(n_0_235), .B1(n_0_728), .B2(n_0_236), .ZN(n_0_234) + ); + INV_X1_LVT i_0_247( + .A(n_0_234), .ZN(n_0_233) + ); + AOI221_X1_LVT i_0_246( + .A(n_0_621), .B1(op2[0]), .B2(n_0_233), .C1(n_0_701), .C2(n_0_264), .ZN(n_0_232) + ); + NAND2_X1_LVT i_0_264( + .A1(op2[3]), .A2(n_0_469), .ZN(n_0_249) + ); + AOI21_X1_LVT i_0_262( + .A(n_0_468), .B1(n_0_693), .B2(n_0_249), .ZN(n_0_247) + ); + INV_X1_LVT i_0_261( + .A(n_0_247), .ZN(n_0_246) + ); + OAI211_X1_LVT i_0_260( + .A(n_0_252), .B(n_0_246), .C1(n_0_468), .C2(n_0_254), .ZN(n_0_245) + ); + OAI221_X1_LVT i_0_253( + .A(n_0_544), .B1(n_0_247), .B2(n_0_241), .C1(n_0_469), .C2(n_0_240), .ZN(n_0_239) + ); + INV_X1_LVT i_0_252( + .A(n_0_239), .ZN(n_0_238) + ); + AOI211_X1_LVT i_0_239( + .A(n_0_226), .B(n_0_232), .C1(n_0_245), .C2(n_0_238), .ZN(n_0_225) + ); + INV_X1_LVT i_0_238( + .A(n_0_225), .ZN(result[13]) + ); + OAI221_X1_LVT i_0_232( + .A(op2[12]), .B1(n_0_696), .B2(n_0_567), .C1(op1[12]), .C2(n_0_564), .ZN(n_0_219) + ); + OAI21_X1_LVT i_0_231( + .A(n_0_681), .B1(op2[12]), .B2(n_0_568), .ZN(n_0_218) + ); + XNOR2_X1_LVT i_10_66( + .A(n_10_52), .B(n_10_53), .ZN(n_44) + ); + AOI222_X1_LVT i_0_230( + .A1(n_12), .A2(n_0_581), .B1(op1[12]), .B2(n_0_218), .C1(n_44), .C2(n_0_580), + .ZN(n_0_217) + ); + OAI21_X1_LVT i_0_234( + .A(n_0_620), .B1(op2[1]), .B2(n_0_265), .ZN(n_0_221) + ); + INV_X1_LVT i_0_763( + .A(op1[5]), .ZN(n_0_730) + ); + OAI21_X1_LVT i_0_236( + .A(op2[2]), .B1(n_0_730), .B2(n_0_615), .ZN(n_0_223) + ); + OAI21_X1_LVT i_0_235( + .A(n_0_223), .B1(op2[2]), .B2(n_0_296), .ZN(n_0_222) + ); + AOI21_X1_LVT i_0_233( + .A(n_0_221), .B1(op2[1]), .B2(n_0_222), .ZN(n_0_220) + ); + NOR2_X1_LVT i_0_237( + .A1(n_0_577), .A2(n_0_227), .ZN(n_0_224) + ); + NOR4_X1_LVT i_0_223( + .A1(n_0_701), .A2(n_0_220), .A3(n_0_224), .A4(n_0_238), .ZN(n_0_210) + ); + NAND2_X1_LVT i_0_224( + .A1(n_0_544), .A2(n_0_247), .ZN(n_0_211) + ); + NAND2_X1_LVT i_0_222( + .A1(n_0_701), .A2(n_0_211), .ZN(n_0_209) + ); + OAI22_X1_LVT i_0_229( + .A1(op2[4]), .A2(n_0_696), .B1(n_0_738), .B2(n_0_698), .ZN(n_0_216) + ); + INV_X1_LVT i_0_228( + .A(n_0_216), .ZN(n_0_215) + ); + OAI22_X1_LVT i_0_227( + .A1(n_0_727), .A2(n_0_617), .B1(op2[3]), .B2(n_0_215), .ZN(n_0_214) + ); + OAI22_X1_LVT i_0_226( + .A1(n_0_693), .A2(n_0_289), .B1(op2[2]), .B2(n_0_214), .ZN(n_0_213) + ); + OAI22_X1_LVT i_0_225( + .A1(op2[1]), .A2(n_0_213), .B1(n_0_728), .B2(n_0_255), .ZN(n_0_212) + ); + AOI221_X1_LVT i_0_221( + .A(n_0_209), .B1(n_0_578), .B2(n_0_212), .C1(n_0_620), .C2(n_0_234), .ZN(n_0_208) + ); + OAI211_X1_LVT i_0_220( + .A(n_0_219), .B(n_0_217), .C1(n_0_210), .C2(n_0_208), .ZN(result[12]) + ); + OAI21_X1_LVT i_0_209( + .A(n_0_681), .B1(op2[11]), .B2(n_0_568), .ZN(n_0_197) + ); + AOI22_X1_LVT i_0_208( + .A1(n_11), .A2(n_0_581), .B1(op1[11]), .B2(n_0_197), .ZN(n_0_196) + ); + NAND2_X1_LVT i_0_207( + .A1(n_0_211), .A2(n_0_196), .ZN(n_0_195) + ); + AOI22_X1_LVT i_0_210( + .A1(op1[11]), .A2(n_0_566), .B1(n_0_706), .B2(n_0_565), .ZN(n_0_198) + ); + XNOR2_X1_LVT i_10_62( + .A(n_10_49), .B(n_10_50), .ZN(n_43) + ); + AOI221_X1_LVT i_0_206( + .A(n_0_195), .B1(op2[11]), .B2(n_0_198), .C1(n_43), .C2(n_0_580), .ZN(n_0_194) + ); + AOI221_X1_LVT i_0_215( + .A(op2[3]), .B1(n_0_738), .B2(n_0_706), .C1(op2[4]), .C2(n_0_688), .ZN(n_0_203) + ); + AOI21_X1_LVT i_0_214( + .A(n_0_203), .B1(op1[19]), .B2(n_0_618), .ZN(n_0_202) + ); + NAND2_X1_LVT i_0_213( + .A1(n_0_693), .A2(n_0_202), .ZN(n_0_201) + ); + OAI21_X1_LVT i_0_212( + .A(n_0_201), .B1(n_0_693), .B2(n_0_275), .ZN(n_0_200) + ); + OAI22_X1_LVT i_0_211( + .A1(n_0_728), .A2(n_0_242), .B1(op2[1]), .B2(n_0_200), .ZN(n_0_199) + ); + AOI22_X1_LVT i_0_205( + .A1(n_0_561), .A2(n_0_199), .B1(n_0_701), .B2(n_0_220), .ZN(n_0_193) + ); + NOR2_X1_LVT i_0_219( + .A1(op2[2]), .A2(n_0_280), .ZN(n_0_207) + ); + AOI21_X1_LVT i_0_218( + .A(n_0_207), .B1(op1[4]), .B2(n_0_496), .ZN(n_0_206) + ); + AOI22_X1_LVT i_0_217( + .A1(n_0_728), .A2(n_0_236), .B1(op2[1]), .B2(n_0_206), .ZN(n_0_205) + ); + AOI22_X1_LVT i_0_216( + .A1(n_0_578), .A2(n_0_212), .B1(n_0_620), .B2(n_0_205), .ZN(n_0_204) + ); + OAI211_X1_LVT i_0_204( + .A(n_0_194), .B(n_0_193), .C1(n_0_701), .C2(n_0_204), .ZN(result[11]) + ); + AOI22_X1_LVT i_0_194( + .A1(n_0_654), .A2(n_0_498), .B1(op1[7]), .B2(n_0_573), .ZN(n_0_183) + ); + OAI22_X1_LVT i_0_193( + .A1(n_0_728), .A2(n_0_183), .B1(op2[1]), .B2(n_0_222), .ZN(n_0_182) + ); + AOI22_X1_LVT i_0_192( + .A1(op2[0]), .A2(n_0_182), .B1(n_0_701), .B2(n_0_205), .ZN(n_0_181) + ); + NOR2_X1_LVT i_0_191( + .A1(n_0_621), .A2(n_0_181), .ZN(n_0_180) + ); + AOI22_X1_LVT i_0_190( + .A1(op1[10]), .A2(n_0_566), .B1(n_0_733), .B2(n_0_565), .ZN(n_0_179) + ); + XNOR2_X1_LVT i_10_58( + .A(n_10_46), .B(n_10_47), .ZN(n_42) + ); + AOI22_X1_LVT i_0_188( + .A1(op2[10]), .A2(n_0_179), .B1(n_42), .B2(n_0_580), .ZN(n_0_177) + ); + OAI21_X1_LVT i_0_189( + .A(n_0_681), .B1(op2[10]), .B2(n_0_568), .ZN(n_0_178) + ); + AOI22_X1_LVT i_0_187( + .A1(n_10), .A2(n_0_581), .B1(op1[10]), .B2(n_0_178), .ZN(n_0_176) + ); + NAND2_X1_LVT i_0_186( + .A1(n_0_177), .A2(n_0_176), .ZN(n_0_175) + ); + NOR2_X1_LVT i_0_203( + .A1(n_0_701), .A2(n_0_199), .ZN(n_0_192) + ); + NOR2_X1_LVT i_0_200( + .A1(n_0_693), .A2(n_0_256), .ZN(n_0_189) + ); + AOI221_X1_LVT i_0_202( + .A(n_0_596), .B1(op1[10]), .B2(n_0_616), .C1(op1[26]), .C2(n_0_606), .ZN(n_0_191) + ); + AOI21_X1_LVT i_0_199( + .A(n_0_189), .B1(n_0_693), .B2(n_0_191), .ZN(n_0_188) + ); + OR2_X1_LVT i_0_198( + .A1(op2[1]), .A2(n_0_188), .ZN(n_0_187) + ); + NAND2_X1_LVT i_0_197( + .A1(op2[1]), .A2(n_0_213), .ZN(n_0_186) + ); + NAND2_X1_LVT i_0_185( + .A1(n_0_187), .A2(n_0_186), .ZN(n_0_174) + ); + AOI211_X1_LVT i_0_184( + .A(n_0_577), .B(n_0_192), .C1(n_0_701), .C2(n_0_174), .ZN(n_0_173) + ); + INV_X1_LVT i_0_263( + .A(n_0_249), .ZN(n_0_248) + ); + OAI22_X1_LVT i_0_196( + .A1(n_0_248), .A2(n_0_187), .B1(n_0_247), .B2(n_0_186), .ZN(n_0_185) + ); + AOI221_X1_LVT i_0_195( + .A(n_0_545), .B1(n_0_246), .B2(n_0_192), .C1(n_0_701), .C2(n_0_185), .ZN(n_0_184) + ); + OR4_X1_LVT i_0_183( + .A1(n_0_180), .A2(n_0_175), .A3(n_0_173), .A4(n_0_184), .ZN(result[10]) + ); + INV_X1_LVT i_0_753( + .A(op2[9]), .ZN(n_0_720) + ); + AOI221_X1_LVT i_0_171( + .A(n_0_720), .B1(op1[9]), .B2(n_0_566), .C1(n_0_722), .C2(n_0_565), .ZN(n_0_161) + ); + XNOR2_X1_LVT i_10_54( + .A(n_10_43), .B(n_10_44), .ZN(n_41) + ); + AOI22_X1_LVT i_0_172( + .A1(n_9), .A2(n_0_581), .B1(n_41), .B2(n_0_580), .ZN(n_0_162) + ); + AOI21_X1_LVT i_0_170( + .A(aluBypass), .B1(n_0_720), .B2(n_0_569), .ZN(n_0_160) + ); + OAI21_X1_LVT i_0_169( + .A(n_0_162), .B1(n_0_722), .B2(n_0_160), .ZN(n_0_159) + ); + OAI222_X1_LVT i_0_182( + .A1(n_0_722), .A2(n_0_615), .B1(n_0_699), .B2(n_0_605), .C1(n_0_732), .C2(n_0_617), + .ZN(n_0_172) + ); + AOI22_X1_LVT i_0_181( + .A1(n_0_693), .A2(n_0_172), .B1(op2[2]), .B2(n_0_243), .ZN(n_0_171) + ); + NAND2_X1_LVT i_0_180( + .A1(n_0_728), .A2(n_0_171), .ZN(n_0_170) + ); + NAND2_X1_LVT i_0_179( + .A1(op2[1]), .A2(n_0_200), .ZN(n_0_169) + ); + OAI22_X1_LVT i_0_178( + .A1(n_0_248), .A2(n_0_170), .B1(n_0_247), .B2(n_0_169), .ZN(n_0_168) + ); + NOR3_X1_LVT i_0_177( + .A1(n_0_545), .A2(n_0_168), .A3(n_0_185), .ZN(n_0_167) + ); + NOR2_X1_LVT i_0_251( + .A1(n_0_704), .A2(n_0_615), .ZN(n_0_237) + ); + OAI22_X1_LVT i_0_176( + .A1(op1[2]), .A2(n_0_693), .B1(n_0_496), .B2(n_0_237), .ZN(n_0_166) + ); + OAI22_X1_LVT i_0_175( + .A1(op2[1]), .A2(n_0_206), .B1(n_0_728), .B2(n_0_166), .ZN(n_0_165) + ); + OAI221_X1_LVT i_0_174( + .A(n_0_620), .B1(op2[0]), .B2(n_0_182), .C1(n_0_701), .C2(n_0_165), .ZN(n_0_164) + ); + NAND2_X1_LVT i_0_173( + .A1(n_0_170), .A2(n_0_169), .ZN(n_0_163) + ); + OAI221_X1_LVT i_0_168( + .A(n_0_164), .B1(n_0_562), .B2(n_0_163), .C1(n_0_548), .C2(n_0_174), .ZN(n_0_158) + ); + OR4_X1_LVT i_0_167( + .A1(n_0_161), .A2(n_0_159), .A3(n_0_167), .A4(n_0_158), .ZN(result[9]) + ); + OAI21_X1_LVT i_0_160( + .A(n_0_693), .B1(n_0_730), .B2(n_0_615), .ZN(n_0_151) + ); + OAI21_X1_LVT i_0_159( + .A(op2[2]), .B1(n_0_729), .B2(n_0_615), .ZN(n_0_150) + ); + AND2_X1_LVT i_0_158( + .A1(n_0_151), .A2(n_0_150), .ZN(n_0_149) + ); + NAND2_X1_LVT i_0_157( + .A1(op2[1]), .A2(n_0_149), .ZN(n_0_148) + ); + OAI21_X1_LVT i_0_156( + .A(n_0_148), .B1(op2[1]), .B2(n_0_183), .ZN(n_0_147) + ); + OAI22_X1_LVT i_0_155( + .A1(op2[0]), .A2(n_0_165), .B1(n_0_701), .B2(n_0_147), .ZN(n_0_146) + ); + NOR2_X1_LVT i_0_154( + .A1(n_0_621), .A2(n_0_146), .ZN(n_0_145) + ); + INV_X1_LVT i_0_773( + .A(op1[8]), .ZN(n_0_740) + ); + NOR2_X1_LVT i_0_688( + .A1(n_0_740), .A2(op2[8]), .ZN(n_0_655) + ); + AOI22_X1_LVT i_0_153( + .A1(op1[8]), .A2(aluBypass), .B1(n_0_655), .B2(n_0_569), .ZN(n_0_144) + ); + OAI221_X1_LVT i_0_152( + .A(op2[8]), .B1(op1[8]), .B2(n_0_564), .C1(n_0_740), .C2(n_0_567), .ZN(n_0_143) + ); + XNOR2_X1_LVT i_10_51( + .A(n_10_39), .B(n_10_42), .ZN(n_40) + ); + AOI22_X1_LVT i_0_151( + .A1(n_40), .A2(n_0_580), .B1(n_8), .B2(n_0_581), .ZN(n_0_142) + ); + NAND3_X1_LVT i_0_150( + .A1(n_0_144), .A2(n_0_143), .A3(n_0_142), .ZN(n_0_141) + ); + OAI222_X1_LVT i_0_166( + .A1(n_0_740), .A2(n_0_615), .B1(n_0_739), .B2(n_0_617), .C1(n_0_736), .C2(n_0_605), + .ZN(n_0_157) + ); + OAI22_X1_LVT i_0_165( + .A1(op2[2]), .A2(n_0_157), .B1(n_0_693), .B2(n_0_214), .ZN(n_0_156) + ); + NOR2_X1_LVT i_0_164( + .A1(op2[1]), .A2(n_0_156), .ZN(n_0_155) + ); + AOI21_X1_LVT i_0_163( + .A(n_0_155), .B1(op2[1]), .B2(n_0_188), .ZN(n_0_154) + ); + AND2_X1_LVT i_0_162( + .A1(n_0_701), .A2(n_0_154), .ZN(n_0_153) + ); + AOI211_X1_LVT i_0_149( + .A(n_0_577), .B(n_0_153), .C1(op2[0]), .C2(n_0_163), .ZN(n_0_140) + ); + AOI221_X1_LVT i_0_161( + .A(n_0_545), .B1(op2[0]), .B2(n_0_168), .C1(n_0_249), .C2(n_0_153), .ZN(n_0_152) + ); + OR4_X1_LVT i_0_148( + .A1(n_0_145), .A2(n_0_141), .A3(n_0_140), .A4(n_0_152), .ZN(result[8]) + ); + AOI22_X1_LVT i_0_138( + .A1(op1[4]), .A2(n_0_573), .B1(op1[0]), .B2(n_0_496), .ZN(n_0_130) + ); + AOI22_X1_LVT i_0_137( + .A1(op2[1]), .A2(n_0_130), .B1(n_0_728), .B2(n_0_166), .ZN(n_0_129) + ); + OAI22_X1_LVT i_0_136( + .A1(n_0_701), .A2(n_0_129), .B1(op2[0]), .B2(n_0_147), .ZN(n_0_128) + ); + NOR2_X1_LVT i_0_135( + .A1(n_0_621), .A2(n_0_128), .ZN(n_0_127) + ); + OAI221_X1_LVT i_0_139( + .A(op2[7]), .B1(n_0_713), .B2(n_0_567), .C1(op1[7]), .C2(n_0_564), .ZN(n_0_131) + ); + INV_X1_LVT i_10_44( + .A(n_10_36), .ZN(n_10_37) + ); + NOR2_X1_LVT i_10_45( + .A1(n_10_35), .A2(n_10_37), .ZN(n_10_38) + ); + XNOR2_X1_LVT i_10_46( + .A(n_10_33), .B(n_10_38), .ZN(n_39) + ); + AOI22_X1_LVT i_0_141( + .A1(n_7), .A2(n_0_581), .B1(n_39), .B2(n_0_580), .ZN(n_0_133) + ); + INV_X1_LVT i_0_745( + .A(op2[7]), .ZN(n_0_712) + ); + AOI21_X1_LVT i_0_140( + .A(aluBypass), .B1(n_0_712), .B2(n_0_569), .ZN(n_0_132) + ); + OAI211_X1_LVT i_0_133( + .A(n_0_131), .B(n_0_133), .C1(n_0_713), .C2(n_0_132), .ZN(n_0_125) + ); + OAI22_X1_LVT i_0_147( + .A1(n_0_734), .A2(n_0_617), .B1(n_0_713), .B2(n_0_615), .ZN(n_0_139) + ); + AOI211_X1_LVT i_0_146( + .A(n_0_139), .B(n_0_248), .C1(op1[23]), .C2(n_0_606), .ZN(n_0_138) + ); + OAI22_X1_LVT i_0_145( + .A1(n_0_693), .A2(n_0_202), .B1(op2[2]), .B2(n_0_138), .ZN(n_0_137) + ); + NOR2_X1_LVT i_0_144( + .A1(op2[1]), .A2(n_0_137), .ZN(n_0_136) + ); + AOI21_X1_LVT i_0_143( + .A(n_0_136), .B1(op2[1]), .B2(n_0_171), .ZN(n_0_135) + ); + NAND2_X1_LVT i_0_142( + .A1(n_0_561), .A2(n_0_135), .ZN(n_0_134) + ); + OAI221_X1_LVT i_0_134( + .A(n_0_134), .B1(n_0_548), .B2(n_0_154), .C1(n_0_545), .C2(n_0_249), .ZN(n_0_126) + ); + OR3_X1_LVT i_0_132( + .A1(n_0_127), .A2(n_0_125), .A3(n_0_126), .ZN(result[7]) + ); + NAND2_X1_LVT i_0_124( + .A1(n_0_728), .A2(n_0_149), .ZN(n_0_117) + ); + OAI21_X1_LVT i_0_123( + .A(n_0_117), .B1(n_0_724), .B2(n_0_531), .ZN(n_0_116) + ); + OAI22_X1_LVT i_0_122( + .A1(n_0_701), .A2(n_0_116), .B1(op2[0]), .B2(n_0_129), .ZN(n_0_115) + ); + NOR2_X1_LVT i_0_121( + .A1(n_0_621), .A2(n_0_115), .ZN(n_0_114) + ); + XNOR2_X1_LVT i_10_38( + .A(n_10_30), .B(n_10_31), .ZN(n_38) + ); + AOI22_X1_LVT i_0_119( + .A1(n_6), .A2(n_0_581), .B1(n_38), .B2(n_0_580), .ZN(n_0_112) + ); + INV_X1_LVT i_0_735( + .A(op2[6]), .ZN(n_0_702) + ); + AOI21_X1_LVT i_0_120( + .A(aluBypass), .B1(n_0_702), .B2(n_0_569), .ZN(n_0_113) + ); + OAI21_X1_LVT i_0_118( + .A(n_0_112), .B1(n_0_704), .B2(n_0_113), .ZN(n_0_111) + ); + AOI221_X1_LVT i_0_117( + .A(n_0_702), .B1(n_0_704), .B2(n_0_565), .C1(op1[6]), .C2(n_0_566), .ZN(n_0_110) + ); + NOR3_X1_LVT i_0_116( + .A1(n_0_114), .A2(n_0_111), .A3(n_0_110), .ZN(n_0_109) + ); + AOI221_X1_LVT i_0_131( + .A(n_0_237), .B1(op1[14]), .B2(n_0_618), .C1(op2[4]), .C2(n_0_406), .ZN(n_0_124) + ); + NAND2_X1_LVT i_0_130( + .A1(n_0_693), .A2(n_0_124), .ZN(n_0_123) + ); + INV_X1_LVT i_0_201( + .A(n_0_191), .ZN(n_0_190) + ); + OAI21_X1_LVT i_0_129( + .A(n_0_123), .B1(n_0_693), .B2(n_0_190), .ZN(n_0_122) + ); + AOI22_X1_LVT i_0_128( + .A1(n_0_728), .A2(n_0_122), .B1(op2[1]), .B2(n_0_156), .ZN(n_0_121) + ); + INV_X1_LVT i_0_127( + .A(n_0_121), .ZN(n_0_120) + ); + OAI21_X1_LVT i_0_126( + .A(n_0_248), .B1(op2[1]), .B2(n_0_123), .ZN(n_0_119) + ); + AND2_X1_LVT i_0_125( + .A1(n_0_120), .A2(n_0_119), .ZN(n_0_118) + ); + NOR2_X1_LVT i_0_115( + .A1(n_0_545), .A2(n_0_118), .ZN(n_0_108) + ); + AOI21_X1_LVT i_0_114( + .A(n_0_108), .B1(n_0_576), .B2(n_0_121), .ZN(n_0_107) + ); + AOI22_X1_LVT i_0_113( + .A1(n_0_544), .A2(n_0_248), .B1(n_0_578), .B2(n_0_135), .ZN(n_0_106) + ); + OAI221_X1_LVT i_0_112( + .A(n_0_109), .B1(op2[0]), .B2(n_0_107), .C1(n_0_701), .C2(n_0_106), .ZN(result[6]) + ); + OAI221_X1_LVT i_0_100( + .A(op2[5]), .B1(op1[5]), .B2(n_0_564), .C1(n_0_730), .C2(n_0_567), .ZN(n_0_94) + ); + INV_X1_LVT i_0_764( + .A(op2[5]), .ZN(n_0_731) + ); + AOI21_X1_LVT i_0_99( + .A(aluBypass), .B1(n_0_731), .B2(n_0_569), .ZN(n_0_93) + ); + NOR2_X1_LVT i_0_98( + .A1(n_0_730), .A2(n_0_93), .ZN(n_0_92) + ); + XNOR2_X1_LVT i_10_35( + .A(n_10_26), .B(n_10_29), .ZN(n_37) + ); + AOI221_X1_LVT i_0_97( + .A(n_0_92), .B1(n_37), .B2(n_0_580), .C1(n_5), .C2(n_0_581), .ZN(n_0_91) + ); + OAI22_X1_LVT i_0_102( + .A1(n_0_694), .A2(n_0_531), .B1(op2[1]), .B2(n_0_130), .ZN(n_0_96) + ); + OAI221_X1_LVT i_0_101( + .A(n_0_620), .B1(n_0_701), .B2(n_0_96), .C1(op2[0]), .C2(n_0_116), .ZN(n_0_95) + ); + NAND3_X1_LVT i_0_111( + .A1(n_0_544), .A2(n_0_248), .A3(op2[2]), .ZN(n_0_105) + ); + NAND2_X1_LVT i_0_110( + .A1(op2[4]), .A2(n_0_386), .ZN(n_0_104) + ); + OAI21_X1_LVT i_0_109( + .A(n_0_104), .B1(n_0_714), .B2(n_0_617), .ZN(n_0_103) + ); + OAI22_X1_LVT i_0_108( + .A1(n_0_151), .A2(n_0_103), .B1(n_0_693), .B2(n_0_172), .ZN(n_0_102) + ); + NOR2_X1_LVT i_0_107( + .A1(op2[1]), .A2(n_0_102), .ZN(n_0_101) + ); + AOI21_X1_LVT i_0_106( + .A(n_0_101), .B1(op2[1]), .B2(n_0_137), .ZN(n_0_100) + ); + OAI21_X1_LVT i_0_105( + .A(n_0_105), .B1(n_0_579), .B2(n_0_100), .ZN(n_0_99) + ); + AOI21_X1_LVT i_0_104( + .A(n_0_118), .B1(n_0_682), .B2(n_0_120), .ZN(n_0_98) + ); + OAI22_X1_LVT i_0_103( + .A1(n_0_547), .A2(n_0_99), .B1(n_0_701), .B2(n_0_98), .ZN(n_0_97) + ); + NAND4_X1_LVT i_0_96( + .A1(n_0_94), .A2(n_0_91), .A3(n_0_95), .A4(n_0_97), .ZN(result[5]) + ); + INV_X1_LVT i_10_26( + .A(n_10_21), .ZN(n_10_22) + ); + NOR2_X1_LVT i_10_28( + .A1(n_10_22), .A2(n_10_23), .ZN(n_10_24) + ); + XNOR2_X1_LVT i_10_29( + .A(n_10_19), .B(n_10_24), .ZN(n_36) + ); + AOI222_X1_LVT i_0_89( + .A1(n_4), .A2(n_0_581), .B1(n_36), .B2(n_0_580), .C1(n_0_668), .C2(n_0_564), + .ZN(n_0_84) + ); + INV_X1_LVT i_0_770( + .A(op1[4]), .ZN(n_0_737) + ); + AOI221_X1_LVT i_0_90( + .A(aluBypass), .B1(op2[4]), .B2(n_0_567), .C1(n_0_738), .C2(n_0_569), .ZN(n_0_85) + ); + OAI21_X1_LVT i_0_88( + .A(n_0_84), .B1(n_0_737), .B2(n_0_85), .ZN(n_0_83) + ); + NOR2_X1_LVT i_0_689( + .A1(op2[4]), .A2(n_0_737), .ZN(n_0_656) + ); + AOI21_X1_LVT i_0_95( + .A(n_0_616), .B1(n_0_727), .B2(n_0_723), .ZN(n_0_90) + ); + OAI22_X1_LVT i_0_94( + .A1(n_0_723), .A2(n_0_216), .B1(n_0_656), .B2(n_0_90), .ZN(n_0_89) + ); + INV_X1_LVT i_0_93( + .A(n_0_89), .ZN(n_0_88) + ); + OAI22_X1_LVT i_0_92( + .A1(op2[2]), .A2(n_0_88), .B1(n_0_693), .B2(n_0_157), .ZN(n_0_87) + ); + OAI221_X1_LVT i_0_91( + .A(n_0_105), .B1(n_0_728), .B2(n_0_122), .C1(op2[1]), .C2(n_0_87), .ZN(n_0_86) + ); + AOI221_X1_LVT i_0_85( + .A(n_0_83), .B1(n_0_561), .B2(n_0_86), .C1(op2[0]), .C2(n_0_99), .ZN(n_0_80) + ); + AOI221_X1_LVT i_0_87( + .A(n_0_574), .B1(n_0_729), .B2(op2[1]), .C1(n_0_728), .C2(n_0_724), .ZN(n_0_82) + ); + OAI22_X1_LVT i_0_86( + .A1(op2[0]), .A2(n_0_96), .B1(n_0_701), .B2(n_0_82), .ZN(n_0_81) + ); + OAI21_X1_LVT i_0_84( + .A(n_0_80), .B1(n_0_621), .B2(n_0_81), .ZN(result[4]) + ); + AND2_X1_LVT i_0_81( + .A1(op2[1]), .A2(n_0_105), .ZN(n_0_77) + ); + NAND2_X1_LVT i_0_80( + .A1(n_0_102), .A2(n_0_77), .ZN(n_0_76) + ); + OAI221_X1_LVT i_0_83( + .A(n_0_693), .B1(n_0_654), .B2(n_0_484), .C1(n_0_738), .C2(n_0_350), .ZN(n_0_79) + ); + OAI21_X1_LVT i_0_82( + .A(n_0_79), .B1(n_0_693), .B2(n_0_138), .ZN(n_0_78) + ); + OAI21_X1_LVT i_0_79( + .A(n_0_76), .B1(op2[1]), .B2(n_0_78), .ZN(n_0_75) + ); + NOR2_X1_LVT i_0_78( + .A1(n_0_562), .A2(n_0_75), .ZN(n_0_74) + ); + NAND2_X1_LVT i_10_20( + .A1(n_10_15), .A2(n_10_16), .ZN(n_10_17) + ); + XNOR2_X1_LVT i_10_21( + .A(n_10_13), .B(n_10_17), .ZN(n_35) + ); + AOI22_X1_LVT i_0_75( + .A1(n_35), .A2(n_0_580), .B1(n_3), .B2(n_0_581), .ZN(n_0_71) + ); + OAI21_X1_LVT i_0_74( + .A(n_0_681), .B1(n_0_723), .B2(n_0_566), .ZN(n_0_70) + ); + AOI222_X1_LVT i_0_73( + .A1(n_0_654), .A2(n_0_569), .B1(n_0_663), .B2(n_0_564), .C1(op1[3]), .C2(n_0_70), + .ZN(n_0_69) + ); + INV_X1_LVT i_0_736( + .A(op1[0]), .ZN(n_0_703) + ); + OAI22_X1_LVT i_0_77( + .A1(n_0_703), .A2(n_0_531), .B1(n_0_694), .B2(n_0_572), .ZN(n_0_73) + ); + OAI22_X1_LVT i_0_76( + .A1(n_0_701), .A2(n_0_73), .B1(op2[0]), .B2(n_0_82), .ZN(n_0_72) + ); + OAI211_X1_LVT i_0_72( + .A(n_0_71), .B(n_0_69), .C1(n_0_621), .C2(n_0_72), .ZN(n_0_68) + ); + AOI211_X1_LVT i_0_71( + .A(n_0_74), .B(n_0_68), .C1(n_0_547), .C2(n_0_86), .ZN(n_0_67) + ); + INV_X1_LVT i_0_70( + .A(n_0_67), .ZN(result[3]) + ); + NAND2_X1_LVT i_0_65( + .A1(n_2), .A2(n_0_581), .ZN(n_0_62) + ); + OAI221_X1_LVT i_0_66( + .A(op2[2]), .B1(op1[2]), .B2(n_0_564), .C1(n_0_694), .C2(n_0_567), .ZN(n_0_63) + ); + AOI21_X1_LVT i_0_64( + .A(aluBypass), .B1(n_0_693), .B2(n_0_569), .ZN(n_0_61) + ); + OAI21_X1_LVT i_0_63( + .A(n_0_63), .B1(n_0_694), .B2(n_0_61), .ZN(n_0_60) + ); + INV_X1_LVT i_10_13( + .A(n_10_10), .ZN(n_10_11) + ); + NOR2_X1_LVT i_10_14( + .A1(n_10_9), .A2(n_10_11), .ZN(n_10_12) + ); + XNOR2_X1_LVT i_10_15( + .A(n_10_7), .B(n_10_12), .ZN(n_34) + ); + AOI21_X1_LVT i_0_62( + .A(n_0_60), .B1(n_34), .B2(n_0_580), .ZN(n_0_59) + ); + OAI211_X1_LVT i_0_57( + .A(n_0_62), .B(n_0_59), .C1(n_0_548), .C2(n_0_75), .ZN(n_0_54) + ); + NOR2_X1_LVT i_0_698( + .A1(n_0_729), .A2(op2[1]), .ZN(n_0_665) + ); + INV_X1_LVT i_0_697( + .A(n_0_665), .ZN(n_0_664) + ); + OAI21_X1_LVT i_0_69( + .A(op2[0]), .B1(n_0_664), .B2(n_0_574), .ZN(n_0_66) + ); + OAI21_X1_LVT i_0_68( + .A(n_0_620), .B1(op2[0]), .B2(n_0_73), .ZN(n_0_65) + ); + INV_X1_LVT i_0_67( + .A(n_0_65), .ZN(n_0_64) + ); + OAI222_X1_LVT i_0_61( + .A1(op1[10]), .A2(n_0_617), .B1(op1[2]), .B2(n_0_615), .C1(n_0_738), .C2(n_0_332), + .ZN(n_0_58) + ); + OAI22_X1_LVT i_0_60( + .A1(op2[2]), .A2(n_0_58), .B1(n_0_693), .B2(n_0_124), .ZN(n_0_57) + ); + INV_X1_LVT i_0_59( + .A(n_0_57), .ZN(n_0_56) + ); + AOI22_X1_LVT i_0_58( + .A1(n_0_728), .A2(n_0_56), .B1(n_0_87), .B2(n_0_77), .ZN(n_0_55) + ); + AOI221_X1_LVT i_0_56( + .A(n_0_54), .B1(n_0_66), .B2(n_0_64), .C1(n_0_561), .C2(n_0_55), .ZN(n_0_53) + ); + INV_X1_LVT i_0_55( + .A(n_0_53), .ZN(result[2]) + ); + NAND2_X1_LVT i_0_54( + .A1(n_0_547), .A2(n_0_55), .ZN(n_0_52) + ); + AOI221_X1_LVT i_0_47( + .A(n_0_728), .B1(n_0_729), .B2(n_0_565), .C1(op1[1]), .C2(n_0_566), .ZN(n_0_45) + ); + NOR2_X1_LVT i_0_700( + .A1(op1[0]), .A2(n_0_701), .ZN(n_0_667) + ); + AOI211_X1_LVT i_0_48( + .A(n_0_667), .B(n_0_621), .C1(n_0_729), .C2(n_0_701), .ZN(n_0_46) + ); + AOI221_X1_LVT i_0_44( + .A(n_0_45), .B1(op1[1]), .B2(aluBypass), .C1(n_0_571), .C2(n_0_46), .ZN(n_0_42) + ); + NAND2_X1_LVT i_10_6( + .A1(n_10_3), .A2(n_10_4), .ZN(n_10_5) + ); + XNOR2_X1_LVT i_10_7( + .A(n_10_5), .B(n_10_1), .ZN(n_33) + ); + AOI22_X1_LVT i_0_49( + .A1(n_33), .A2(n_0_580), .B1(n_1), .B2(n_0_581), .ZN(n_0_47) + ); + OAI21_X1_LVT i_0_46( + .A(n_0_47), .B1(n_0_664), .B2(n_0_568), .ZN(n_0_44) + ); + NAND2_X1_LVT i_0_51( + .A1(op2[1]), .A2(n_0_78), .ZN(n_0_49) + ); + OAI222_X1_LVT i_0_53( + .A1(n_0_722), .A2(n_0_617), .B1(n_0_729), .B2(n_0_615), .C1(n_0_738), .C2(n_0_313), + .ZN(n_0_51) + ); + OAI22_X1_LVT i_0_52( + .A1(n_0_223), .A2(n_0_103), .B1(op2[2]), .B2(n_0_51), .ZN(n_0_50) + ); + OAI21_X1_LVT i_0_50( + .A(n_0_49), .B1(op2[1]), .B2(n_0_50), .ZN(n_0_48) + ); + AOI21_X1_LVT i_0_45( + .A(n_0_44), .B1(n_0_561), .B2(n_0_48), .ZN(n_0_43) + ); + NAND3_X1_LVT i_0_43( + .A1(n_0_52), .A2(n_0_42), .A3(n_0_43), .ZN(result[1]) + ); + OAI222_X1_LVT i_0_11( + .A1(n_0_740), .A2(n_0_617), .B1(n_0_703), .B2(n_0_615), .C1(n_0_738), .C2(n_0_290), + .ZN(n_0_10) + ); + OAI22_X1_LVT i_0_10( + .A1(op2[2]), .A2(n_0_10), .B1(n_0_693), .B2(n_0_88), .ZN(n_0_9) + ); + OAI221_X1_LVT i_0_9( + .A(n_0_701), .B1(n_0_728), .B2(n_0_56), .C1(op2[1]), .C2(n_0_9), .ZN(n_0_8) + ); + OAI21_X1_LVT i_0_8( + .A(n_0_8), .B1(n_0_701), .B2(n_0_48), .ZN(n_0_7) + ); + NOR2_X1_LVT i_0_7( + .A1(n_0_579), .A2(n_0_7), .ZN(n_0_6) + ); + OAI221_X1_LVT i_0_3( + .A(op2[0]), .B1(op1[0]), .B2(n_0_564), .C1(n_0_703), .C2(n_0_567), .ZN(n_0_2) + ); + OAI21_X1_LVT i_10_2( + .A(n_10_1), .B1(n_10_0), .B2(op2[0]), .ZN(n_32) + ); + AOI22_X1_LVT i_0_2( + .A1(n_32), .A2(n_0_580), .B1(n_0), .B2(n_0_581), .ZN(n_0_1) + ); + NAND3_X1_LVT i_0_6( + .A1(n_0_701), .A2(n_0_571), .A3(n_0_620), .ZN(n_0_5) + ); + OAI211_X1_LVT i_0_5( + .A(n_0_681), .B(n_0_5), .C1(op2[0]), .C2(n_0_568), .ZN(n_0_4) + ); + NAND2_X1_LVT i_0_4( + .A1(op1[0]), .A2(n_0_4), .ZN(n_0_3) + ); + NAND3_X1_LVT i_0_1( + .A1(n_0_2), .A2(n_0_1), .A3(n_0_3), .ZN(n_0_0) + ); + OAI33_X1_LVT i_0_14( + .A1(n_0_692), .A2(op1[31]), .A3(n_0_683), .B1(op2[31]), .B2(n_0_691), .B3(aluOp[0]), + .ZN(n_0_13) + ); + INV_X1_LVT i_0_741( + .A(op2[29]), .ZN(n_0_708) + ); + NAND2_X1_LVT i_0_685( + .A1(op1[29]), .A2(n_0_708), .ZN(n_0_652) + ); + OAI22_X1_LVT i_0_713( + .A1(n_0_700), .A2(op1[28]), .B1(op1[29]), .B2(n_0_708), .ZN(n_0_680) + ); + NAND2_X1_LVT i_0_694( + .A1(n_0_688), .A2(op2[27]), .ZN(n_0_661) + ); + INV_X1_LVT i_0_742( + .A(op2[26]), .ZN(n_0_709) + ); + OAI22_X1_LVT i_0_712( + .A1(n_0_699), .A2(op2[25]), .B1(n_0_736), .B2(op2[24]), .ZN(n_0_679) + ); + NAND2_X1_LVT i_0_690( + .A1(n_0_727), .A2(op2[20]), .ZN(n_0_657) + ); + INV_X1_LVT i_0_740( + .A(op2[18]), .ZN(n_0_707) + ); + OAI22_X1_LVT i_0_711( + .A1(n_0_707), .A2(op1[18]), .B1(n_0_690), .B2(op1[19]), .ZN(n_0_678) + ); + OAI22_X1_LVT i_0_29( + .A1(n_0_739), .A2(op2[16]), .B1(n_0_734), .B2(op2[15]), .ZN(n_0_28) + ); + INV_X1_LVT i_0_728( + .A(op2[12]), .ZN(n_0_695) + ); + INV_X1_LVT i_0_748( + .A(op2[13]), .ZN(n_0_715) + ); + OAI22_X1_LVT i_0_704( + .A1(n_0_706), .A2(op2[11]), .B1(n_0_696), .B2(op2[12]), .ZN(n_0_671) + ); + AOI22_X1_LVT i_0_710( + .A1(n_0_740), .A2(op2[8]), .B1(n_0_713), .B2(op2[7]), .ZN(n_0_677) + ); + OAI22_X1_LVT i_0_707( + .A1(n_0_731), .A2(op1[5]), .B1(op1[6]), .B2(n_0_702), .ZN(n_0_674) + ); + OAI22_X1_LVT i_0_706( + .A1(op1[2]), .A2(n_0_693), .B1(op1[1]), .B2(n_0_728), .ZN(n_0_673) + ); + INV_X1_LVT i_0_705( + .A(n_0_673), .ZN(n_0_672) + ); + INV_X1_LVT i_0_699( + .A(n_0_667), .ZN(n_0_666) + ); + OAI21_X1_LVT i_0_42( + .A(n_0_672), .B1(n_0_666), .B2(n_0_665), .ZN(n_0_41) + ); + AOI21_X1_LVT i_0_41( + .A(n_0_654), .B1(op1[2]), .B2(n_0_693), .ZN(n_0_40) + ); + AOI211_X1_LVT i_0_40( + .A(n_0_668), .B(n_0_663), .C1(n_0_41), .C2(n_0_40), .ZN(n_0_39) + ); + AOI211_X1_LVT i_0_39( + .A(n_0_656), .B(n_0_39), .C1(n_0_731), .C2(op1[5]), .ZN(n_0_38) + ); + OAI222_X1_LVT i_0_38( + .A1(n_0_704), .A2(op2[6]), .B1(n_0_674), .B2(n_0_38), .C1(n_0_713), .C2(op2[7]), + .ZN(n_0_37) + ); + AOI221_X1_LVT i_0_37( + .A(n_0_655), .B1(op1[9]), .B2(n_0_720), .C1(n_0_677), .C2(n_0_37), .ZN(n_0_36) + ); + INV_X1_LVT i_0_768( + .A(op2[10]), .ZN(n_0_735) + ); + OAI22_X1_LVT i_0_36( + .A1(n_0_735), .A2(op1[10]), .B1(op1[9]), .B2(n_0_720), .ZN(n_0_35) + ); + OAI22_X1_LVT i_0_35( + .A1(op2[10]), .A2(n_0_733), .B1(n_0_36), .B2(n_0_35), .ZN(n_0_34) + ); + INV_X1_LVT i_0_34( + .A(n_0_34), .ZN(n_0_33) + ); + AOI21_X1_LVT i_0_33( + .A(n_0_33), .B1(n_0_706), .B2(op2[11]), .ZN(n_0_32) + ); + OAI222_X1_LVT i_0_32( + .A1(op1[12]), .A2(n_0_695), .B1(n_0_715), .B2(op1[13]), .C1(n_0_671), .C2(n_0_32), + .ZN(n_0_31) + ); + OAI221_X1_LVT i_0_31( + .A(n_0_31), .B1(n_0_721), .B2(op2[14]), .C1(op2[13]), .C2(n_0_714), .ZN(n_0_30) + ); + AOI22_X1_LVT i_0_30( + .A1(n_0_734), .A2(op2[15]), .B1(n_0_721), .B2(op2[14]), .ZN(n_0_29) + ); + AOI21_X1_LVT i_0_28( + .A(n_0_28), .B1(n_0_30), .B2(n_0_29), .ZN(n_0_27) + ); + AOI221_X1_LVT i_0_27( + .A(n_0_27), .B1(n_0_732), .B2(op2[17]), .C1(n_0_739), .C2(op2[16]), .ZN(n_0_26) + ); + AOI211_X1_LVT i_0_26( + .A(n_0_660), .B(n_0_26), .C1(n_0_707), .C2(op1[18]), .ZN(n_0_25) + ); + OAI22_X1_LVT i_0_25( + .A1(op2[19]), .A2(n_0_689), .B1(n_0_678), .B2(n_0_25), .ZN(n_0_24) + ); + AOI211_X1_LVT i_0_24( + .A(n_0_658), .B(n_0_659), .C1(n_0_657), .C2(n_0_24), .ZN(n_0_23) + ); + AOI221_X1_LVT i_0_23( + .A(n_0_23), .B1(n_0_726), .B2(op2[21]), .C1(n_0_687), .C2(op2[22]), .ZN(n_0_22) + ); + AOI221_X1_LVT i_0_22( + .A(n_0_22), .B1(op1[22]), .B2(n_0_686), .C1(op1[23]), .C2(n_0_718), .ZN(n_0_21) + ); + AOI221_X1_LVT i_0_21( + .A(n_0_21), .B1(n_0_736), .B2(op2[24]), .C1(n_0_719), .C2(op2[23]), .ZN(n_0_20) + ); + OAI222_X1_LVT i_0_20( + .A1(op1[26]), .A2(n_0_709), .B1(op1[25]), .B2(n_0_697), .C1(n_0_679), .C2(n_0_20), + .ZN(n_0_19) + ); + OAI221_X1_LVT i_0_19( + .A(n_0_19), .B1(n_0_711), .B2(op2[26]), .C1(n_0_688), .C2(op2[27]), .ZN(n_0_18) + ); + AOI22_X1_LVT i_0_18( + .A1(n_0_700), .A2(op1[28]), .B1(n_0_661), .B2(n_0_18), .ZN(n_0_17) + ); + OAI21_X1_LVT i_0_17( + .A(n_0_652), .B1(n_0_680), .B2(n_0_17), .ZN(n_0_16) + ); + INV_X1_LVT i_0_749( + .A(op2[30]), .ZN(n_0_716) + ); + OAI21_X1_LVT i_0_16( + .A(n_0_16), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_15) + ); + OAI22_X1_LVT i_0_708( + .A1(n_0_692), .A2(op1[31]), .B1(op2[31]), .B2(n_0_691), .ZN(n_0_675) + ); + AOI21_X1_LVT i_0_15( + .A(n_0_675), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_14) + ); + AOI21_X1_LVT i_0_13( + .A(n_0_13), .B1(n_0_15), .B2(n_0_14), .ZN(n_0_12) + ); + NOR4_X1_LVT i_0_12( + .A1(n_0_685), .A2(aluOp[2]), .A3(aluBypass), .A4(n_0_12), .ZN(n_0_11) + ); + OR3_X1_LVT i_0_0( + .A1(n_0_6), .A2(n_0_0), .A3(n_0_11), .ZN(result[0]) + ); + OR4_X1_LVT i_0_703( + .A1(n_0_680), .A2(n_0_673), .A3(n_0_675), .A4(n_0_678), .ZN(n_0_670) + ); + INV_X1_LVT i_0_709( + .A(n_0_677), .ZN(n_0_676) + ); + OR4_X1_LVT i_0_702( + .A1(n_0_679), .A2(n_0_674), .A3(n_0_676), .A4(n_0_671), .ZN(n_0_669) + ); + AOI22_X1_LVT i_0_663( + .A1(n_0_688), .A2(op2[27]), .B1(op1[22]), .B2(n_0_686), .ZN(n_0_630) + ); + OAI22_X1_LVT i_0_662( + .A1(n_0_694), .A2(op2[2]), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_629) + ); + AOI221_X1_LVT i_0_661( + .A(n_0_629), .B1(n_0_711), .B2(op2[26]), .C1(n_0_721), .C2(op2[14]), .ZN(n_0_628) + ); + AOI21_X1_LVT i_0_664( + .A(n_0_660), .B1(n_0_690), .B2(op1[19]), .ZN(n_0_631) + ); + OAI222_X1_LVT i_0_660( + .A1(op1[12]), .A2(n_0_695), .B1(n_0_688), .B2(op2[27]), .C1(op1[22]), .C2(n_0_686), + .ZN(n_0_627) + ); + AOI21_X1_LVT i_0_659( + .A(n_0_663), .B1(n_0_734), .B2(op2[15]), .ZN(n_0_626) + ); + OAI211_X1_LVT i_0_658( + .A(n_0_666), .B(n_0_626), .C1(n_0_715), .C2(op1[13]), .ZN(n_0_625) + ); + AOI211_X1_LVT i_0_657( + .A(n_0_627), .B(n_0_625), .C1(op1[23]), .C2(n_0_718), .ZN(n_0_624) + ); + NAND4_X1_LVT i_0_656( + .A1(n_0_630), .A2(n_0_628), .A3(n_0_631), .A4(n_0_624), .ZN(n_0_623) + ); + OAI22_X1_LVT i_0_684( + .A1(n_0_721), .A2(op2[14]), .B1(n_0_722), .B2(op2[9]), .ZN(n_0_651) + ); + AOI211_X1_LVT i_0_668( + .A(n_0_651), .B(n_0_654), .C1(n_0_719), .C2(op2[23]), .ZN(n_0_635) + ); + NAND2_X1_LVT i_0_667( + .A1(n_0_664), .A2(n_0_657), .ZN(n_0_634) + ); + NOR3_X1_LVT i_0_666( + .A1(n_0_659), .A2(n_0_656), .A3(n_0_634), .ZN(n_0_633) + ); + AOI21_X1_LVT i_0_671( + .A(n_0_655), .B1(n_0_739), .B2(op2[16]), .ZN(n_0_638) + ); + AOI21_X1_LVT i_0_670( + .A(n_0_668), .B1(n_0_736), .B2(op2[24]), .ZN(n_0_637) + ); + OAI22_X1_LVT i_0_673( + .A1(n_0_735), .A2(op1[10]), .B1(n_0_734), .B2(op2[15]), .ZN(n_0_640) + ); + AOI221_X1_LVT i_0_672( + .A(n_0_640), .B1(n_0_732), .B2(op2[17]), .C1(n_0_731), .C2(op1[5]), .ZN(n_0_639) + ); + AND3_X1_LVT i_0_669( + .A1(n_0_638), .A2(n_0_637), .A3(n_0_639), .ZN(n_0_636) + ); + OAI22_X1_LVT i_0_682( + .A1(n_0_703), .A2(op2[0]), .B1(n_0_704), .B2(op2[6]), .ZN(n_0_649) + ); + OAI22_X1_LVT i_0_681( + .A1(op2[28]), .A2(n_0_698), .B1(op1[25]), .B2(n_0_697), .ZN(n_0_648) + ); + AOI21_X1_LVT i_0_678( + .A(n_0_658), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_645) + ); + AOI21_X1_LVT i_0_677( + .A(n_0_662), .B1(n_0_735), .B2(op1[10]), .ZN(n_0_644) + ); + INV_X1_LVT i_0_758( + .A(op2[21]), .ZN(n_0_725) + ); + OAI22_X1_LVT i_0_683( + .A1(op1[21]), .A2(n_0_725), .B1(n_0_739), .B2(op2[16]), .ZN(n_0_650) + ); + AOI221_X1_LVT i_0_676( + .A(n_0_650), .B1(n_0_722), .B2(op2[9]), .C1(op1[7]), .C2(n_0_712), .ZN(n_0_643) + ); + OAI21_X1_LVT i_0_680( + .A(n_0_652), .B1(n_0_711), .B2(op2[26]), .ZN(n_0_647) + ); + AOI221_X1_LVT i_0_679( + .A(n_0_647), .B1(n_0_706), .B2(op2[11]), .C1(n_0_707), .C2(op1[18]), .ZN(n_0_646) + ); + NAND4_X1_LVT i_0_675( + .A1(n_0_645), .A2(n_0_644), .A3(n_0_643), .A4(n_0_646), .ZN(n_0_642) + ); + NOR3_X1_LVT i_0_674( + .A1(n_0_649), .A2(n_0_648), .A3(n_0_642), .ZN(n_0_641) + ); + NAND4_X1_LVT i_0_665( + .A1(n_0_635), .A2(n_0_633), .A3(n_0_636), .A4(n_0_641), .ZN(n_0_632) + ); + NOR4_X1_LVT i_0_655( + .A1(n_0_670), .A2(n_0_669), .A3(n_0_623), .A4(n_0_632), .ZN(eqFlag) + ); +endmodule + +module decoder(CurrentPC, JumpOrBranchPC, JumpOrBranch, DAddr, WData, RData, Instruction, + WrMem, DWidth, Rs1, Rs2, Rd, RRs1, RRs2, WRd, WrReg, Illegal); + input [31:0] CurrentPC, RData, Instruction, RRs1, RRs2; + output [31:0] JumpOrBranchPC, DAddr, WData, WRd; + output [4:0] Rs1, Rs2, Rd; + output [1:0] DWidth; + output JumpOrBranch, WrMem, WrReg, Illegal; + + wire [31:0] op1, op2; + wire [2:0] aluOp; + wire eqFlag, n_5_0, n_5_1, n_5_2, n_5_3, n_5_4, n_5_5, n_5_6, n_5_7, n_5_8, + n_5_9, n_5_10, n_5_11, n_5_12, n_5_13, n_5_14, n_5_15, n_5_16, n_5_17, + n_5_18, n_5_19, n_5_20, n_5_21, n_5_22, n_5_23, n_5_24, n_5_25, n_5_26, + n_5_27, n_5_28, n_5_29, n_5_30, n_5_31, n_5_32, n_5_33, n_17_0, n_17_1, + n_17_2, n_17_3, n_17_4, n_17_5, n_17_6, n_17_7, n_17_8, n_17_9, n_17_10, + n_17_11, n_17_12, n_17_13, n_17_14, n_17_15, n_17_16, n_17_17, n_17_18, + n_17_19, n_17_20, n_17_21, n_17_22, n_17_23, n_17_24, n_17_25, n_17_26, + n_17_27, n_17_28, n_17_29, n_17_30, n_17_31, n_17_32, n_18_0, n_18_1, + n_18_2, n_18_3, n_18_4, n_18_5, n_18_6, n_18_7, n_18_8, n_18_9, n_18_10, + n_18_11, n_18_12, n_18_13, n_18_14, n_18_15, n_18_16, n_18_17, n_18_18, + n_18_19, n_18_20, n_18_21, n_18_22, n_18_23, n_18_24, n_18_25, n_18_26, + n_18_27, n_18_28, n_18_29, n_18_30, n_18_31, n_18_32, n_0_15, n_0_2, + n_0_16, n_0_3, n_0_17, n_0_4, n_0_18, n_0_5, n_0_19, n_0_6, n_0_20, + n_0_7, n_0_21, n_0_8, n_0_22, n_0_9, n_0_23, n_0_10, n_0_24, n_0_11, + n_0_25, n_0_12, n_0_26, n_0_13, n_0_27, n_0_14, n_0_28, n_0_29, n_0_30, + n_0_31, n_0_32, n_0_33, n_0_34, n_0_35, n_0_36, n_0_37, n_0_38, n_0_39, + n_0_40, n_0_41, n_0_42, n_0_43, n_0_44, n_0_45, n_0_46, n_0_47, n_0_48, + n_0_49, n_0_50, n_0_51, n_0_52, n_0_53, n_0_54, n_0_55, n_0_56, n_0_57, + n_0_58, n_0_59, n_0_60, n_0_61, n_0_62, n_0_63, n_0_64, n_0_65, n_0_66, + n_0_67, n_0_68, n_0_69, n_0_70, n_0_71, n_0_72, n_0_73, n_0_74, n_0_75, + n_0_76, n_0_77, n_0_78, n_0_79, n_0_80, n_0_81, n_0_82, n_0_83, n_0_84, + n_0_85, n_0_86, n_0_87, n_0_88, n_0_89, n_0_90, n_0_91, n_0_92, n_0_93, + n_0_94, n_0_95, n_0_96, n_0_97, n_0_98, n_0_99, n_0_100, aluNegAr, + n_0_101, n_0_102, n_0_103, n_0_104, n_0_105, aluBypass, n_0_106, + n_0_107, n_0_108, n_0_109, n_0_110, n_0_111, n_0_112, n_0_113, n_0_114, + n_0_115, n_0_116, n_0_117, n_0_118, n_0_119, n_0_120, n_0_121, n_0_122, + n_0_123, n_0_124, n_0_125, n_0_126, n_0_127, n_0_128, n_0_129, n_0_130, + n_0_131, n_0_132, n_0_133, n_0_134, n_0_135, n_0_136, n_0_137, n_0_138, + n_0_139, n_0_140, n_0_141, n_0_142, n_0_143, n_0_144, n_0_145, n_0_146, + n_0_147, n_0_148, n_0_149, n_0_150, n_0_151, n_0_152, n_0_153, n_0_154, + n_0_155, n_0_156, n_0_157, n_0_158, n_0_159, n_0_160, n_0_161, n_0_162, + n_0_163, n_0_164, n_0_165, n_0_166, n_0_167, n_0_168, n_0_169, n_0_170, + n_0_171, n_0_172, n_0_173, n_0_174, n_0_175, n_0_176, n_0_177, n_0_178, + n_0_179, n_0_180, n_0_181, n_0_182, n_0_183, n_0_184, n_0_185, n_0_186, + n_0_187, n_0_188, n_0_189, n_0_190, n_0_191, n_0_192, n_0_193, n_0_194, + n_0_195, n_0_196, n_0_197, n_0_198, n_0_199, n_0_200, n_0_201, n_0_202, + n_0_203, n_0_204, n_0_205, n_0_206, n_0_207, n_0_208, n_0_209, n_0_210, + n_0_211, n_0_212, n_0_213, n_0_214, n_0_215, n_0_216, n_0_217, n_0_218, + n_0_219, n_0_220, n_0_221, n_0_222, n_0_223, n_0_224, n_0_225, n_0_226, + n_0_227, n_0_228, n_0_229, n_0_230, n_0_231, n_0_232, n_0_233, n_0_234, + n_0_235, n_0_236, n_0_237, n_0_238, n_0_239, n_0_240, n_0_241, n_0_242, + n_0_1, n_0_0, n_0_243, n_0_244, n_0_245, n_0_246, n_0_247, n_0_248, + n_0_249, n_63, n_64, n_65, n_66, n_67, n_68, n_69, n_70, n_71, n_72, + n_73, n_74, n_75, n_76, n_77, n_78, n_79, n_80, n_81, n_82, n_83, n_84, + n_85, n_86, n_87, n_88, n_89, n_90, n_91, n_92, n_93, n_32, n_33, n_34, + n_35, n_36, n_37, n_38, n_39, n_40, n_41, n_42, n_43, n_44, n_45, n_46, + n_47, n_48, n_49, n_50, n_51, n_52, n_53, n_54, n_55, n_56, n_57, n_58, + n_59, n_60, n_61, n_62, n_0, n_1, n_2, n_3, n_4, n_5, n_6, n_7, n_8, + n_9, n_10, n_11, n_12, n_13, n_14, n_15, n_16, n_17, n_18, n_19, n_20, + n_21, n_22, n_23, n_24, n_25, n_26, n_27, n_28, n_29, n_30, n_31; + + INV_X1_LVT i_18_1( + .A(CurrentPC[13]), .ZN(n_18_1) + ); + XNOR2_X1_LVT i_18_32( + .A(CurrentPC[31]), .B(n_18_1), .ZN(n_18_32) + ); + INV_X1_LVT i_18_0( + .A(Instruction[31]), .ZN(n_18_0) + ); + HA_X1_LVT i_18_2( + .A(Instruction[8]), .B(CurrentPC[1]), .CO(n_18_2), .S(n_63) + ); + FA_X1_LVT i_18_3( + .A(Instruction[9]), .B(CurrentPC[2]), .CI(n_18_2), .CO(n_18_3), .S(n_64) + ); + FA_X1_LVT i_18_4( + .A(Instruction[10]), .B(CurrentPC[3]), .CI(n_18_3), .CO(n_18_4), .S(n_65) + ); + FA_X1_LVT i_18_5( + .A(Instruction[11]), .B(CurrentPC[4]), .CI(n_18_4), .CO(n_18_5), .S(n_66) + ); + FA_X1_LVT i_18_6( + .A(Instruction[25]), .B(CurrentPC[5]), .CI(n_18_5), .CO(n_18_6), .S(n_67) + ); + FA_X1_LVT i_18_7( + .A(Instruction[26]), .B(CurrentPC[6]), .CI(n_18_6), .CO(n_18_7), .S(n_68) + ); + FA_X1_LVT i_18_8( + .A(Instruction[27]), .B(CurrentPC[7]), .CI(n_18_7), .CO(n_18_8), .S(n_69) + ); + FA_X1_LVT i_18_9( + .A(Instruction[28]), .B(CurrentPC[8]), .CI(n_18_8), .CO(n_18_9), .S(n_70) + ); + FA_X1_LVT i_18_10( + .A(Instruction[29]), .B(CurrentPC[9]), .CI(n_18_9), .CO(n_18_10), .S(n_71) + ); + FA_X1_LVT i_18_11( + .A(Instruction[30]), .B(CurrentPC[10]), .CI(n_18_10), .CO(n_18_11), .S(n_72) + ); + FA_X1_LVT i_18_12( + .A(Instruction[7]), .B(CurrentPC[11]), .CI(n_18_11), .CO(n_18_12), .S(n_73) + ); + FA_X1_LVT i_18_13( + .A(CurrentPC[12]), .B(Instruction[31]), .CI(n_18_12), .CO(n_18_13), .S(n_74) + ); + FA_X1_LVT i_18_14( + .A(n_18_0), .B(n_18_1), .CI(n_18_13), .CO(n_18_14), .S(n_75) + ); + FA_X1_LVT i_18_15( + .A(CurrentPC[14]), .B(n_18_1), .CI(n_18_14), .CO(n_18_15), .S(n_76) + ); + FA_X1_LVT i_18_16( + .A(CurrentPC[15]), .B(n_18_1), .CI(n_18_15), .CO(n_18_16), .S(n_77) + ); + FA_X1_LVT i_18_17( + .A(CurrentPC[16]), .B(n_18_1), .CI(n_18_16), .CO(n_18_17), .S(n_78) + ); + FA_X1_LVT i_18_18( + .A(CurrentPC[17]), .B(n_18_1), .CI(n_18_17), .CO(n_18_18), .S(n_79) + ); + FA_X1_LVT i_18_19( + .A(CurrentPC[18]), .B(n_18_1), .CI(n_18_18), .CO(n_18_19), .S(n_80) + ); + FA_X1_LVT i_18_20( + .A(CurrentPC[19]), .B(n_18_1), .CI(n_18_19), .CO(n_18_20), .S(n_81) + ); + FA_X1_LVT i_18_21( + .A(CurrentPC[20]), .B(n_18_1), .CI(n_18_20), .CO(n_18_21), .S(n_82) + ); + FA_X1_LVT i_18_22( + .A(CurrentPC[21]), .B(n_18_1), .CI(n_18_21), .CO(n_18_22), .S(n_83) + ); + FA_X1_LVT i_18_23( + .A(CurrentPC[22]), .B(n_18_1), .CI(n_18_22), .CO(n_18_23), .S(n_84) + ); + FA_X1_LVT i_18_24( + .A(CurrentPC[23]), .B(n_18_1), .CI(n_18_23), .CO(n_18_24), .S(n_85) + ); + FA_X1_LVT i_18_25( + .A(CurrentPC[24]), .B(n_18_1), .CI(n_18_24), .CO(n_18_25), .S(n_86) + ); + FA_X1_LVT i_18_26( + .A(CurrentPC[25]), .B(n_18_1), .CI(n_18_25), .CO(n_18_26), .S(n_87) + ); + FA_X1_LVT i_18_27( + .A(CurrentPC[26]), .B(n_18_1), .CI(n_18_26), .CO(n_18_27), .S(n_88) + ); + FA_X1_LVT i_18_28( + .A(CurrentPC[27]), .B(n_18_1), .CI(n_18_27), .CO(n_18_28), .S(n_89) + ); + FA_X1_LVT i_18_29( + .A(CurrentPC[28]), .B(n_18_1), .CI(n_18_28), .CO(n_18_29), .S(n_90) + ); + FA_X1_LVT i_18_30( + .A(CurrentPC[29]), .B(n_18_1), .CI(n_18_29), .CO(n_18_30), .S(n_91) + ); + FA_X1_LVT i_18_31( + .A(CurrentPC[30]), .B(n_18_1), .CI(n_18_30), .CO(n_18_31), .S(n_92) + ); + XNOR2_X1_LVT i_18_33( + .A(n_18_32), .B(n_18_31), .ZN(n_93) + ); + INV_X1_LVT i_0_350( + .A(Instruction[3]), .ZN(n_0_243) + ); + NAND3_X1_LVT i_0_343( + .A1(n_0_243), .A2(Instruction[0]), .A3(Instruction[1]), .ZN(n_0_238) + ); + OR2_X1_LVT i_0_332( + .A1(n_0_238), .A2(Instruction[2]), .ZN(n_0_228) + ); + INV_X1_LVT i_0_351( + .A(Instruction[5]), .ZN(n_0_244) + ); + NOR2_X1_LVT i_0_340( + .A1(n_0_244), .A2(Instruction[4]), .ZN(n_0_235) + ); + NAND2_X1_LVT i_0_329( + .A1(Instruction[6]), .A2(n_0_235), .ZN(n_0_225) + ); + INV_X1_LVT i_0_354( + .A(Instruction[13]), .ZN(n_0_247) + ); + NOR2_X1_LVT i_0_345( + .A1(n_0_247), .A2(Instruction[14]), .ZN(n_0_240) + ); + NOR3_X1_LVT i_0_118( + .A1(n_0_228), .A2(n_0_225), .A3(n_0_240), .ZN(n_0_99) + ); + NAND3_X1_LVT i_0_346( + .A1(Instruction[0]), .A2(Instruction[1]), .A3(Instruction[2]), .ZN(n_0_241) + ); + NOR2_X1_LVT i_0_328( + .A1(n_0_241), .A2(n_0_225), .ZN(n_0_224) + ); + INV_X1_LVT i_0_356( + .A(n_0_224), .ZN(n_0_249) + ); + NOR2_X1_LVT i_0_108( + .A1(n_0_243), .A2(n_0_249), .ZN(n_0_91) + ); + INV_X1_LVT i_17_1( + .A(CurrentPC[21]), .ZN(n_17_1) + ); + XNOR2_X1_LVT i_17_32( + .A(CurrentPC[31]), .B(n_17_1), .ZN(n_17_32) + ); + INV_X1_LVT i_17_0( + .A(Instruction[31]), .ZN(n_17_0) + ); + HA_X1_LVT i_17_2( + .A(Instruction[21]), .B(CurrentPC[1]), .CO(n_17_2), .S(n_32) + ); + FA_X1_LVT i_17_3( + .A(Instruction[22]), .B(CurrentPC[2]), .CI(n_17_2), .CO(n_17_3), .S(n_33) + ); + FA_X1_LVT i_17_4( + .A(Instruction[23]), .B(CurrentPC[3]), .CI(n_17_3), .CO(n_17_4), .S(n_34) + ); + FA_X1_LVT i_17_5( + .A(Instruction[24]), .B(CurrentPC[4]), .CI(n_17_4), .CO(n_17_5), .S(n_35) + ); + FA_X1_LVT i_17_6( + .A(Instruction[25]), .B(CurrentPC[5]), .CI(n_17_5), .CO(n_17_6), .S(n_36) + ); + FA_X1_LVT i_17_7( + .A(Instruction[26]), .B(CurrentPC[6]), .CI(n_17_6), .CO(n_17_7), .S(n_37) + ); + FA_X1_LVT i_17_8( + .A(Instruction[27]), .B(CurrentPC[7]), .CI(n_17_7), .CO(n_17_8), .S(n_38) + ); + FA_X1_LVT i_17_9( + .A(Instruction[28]), .B(CurrentPC[8]), .CI(n_17_8), .CO(n_17_9), .S(n_39) + ); + FA_X1_LVT i_17_10( + .A(Instruction[29]), .B(CurrentPC[9]), .CI(n_17_9), .CO(n_17_10), .S(n_40) + ); + FA_X1_LVT i_17_11( + .A(Instruction[30]), .B(CurrentPC[10]), .CI(n_17_10), .CO(n_17_11), .S(n_41) + ); + FA_X1_LVT i_17_12( + .A(Instruction[20]), .B(CurrentPC[11]), .CI(n_17_11), .CO(n_17_12), .S(n_42) + ); + FA_X1_LVT i_17_13( + .A(Instruction[12]), .B(CurrentPC[12]), .CI(n_17_12), .CO(n_17_13), .S(n_43) + ); + FA_X1_LVT i_17_14( + .A(Instruction[13]), .B(CurrentPC[13]), .CI(n_17_13), .CO(n_17_14), .S(n_44) + ); + FA_X1_LVT i_17_15( + .A(Instruction[14]), .B(CurrentPC[14]), .CI(n_17_14), .CO(n_17_15), .S(n_45) + ); + FA_X1_LVT i_17_16( + .A(Instruction[15]), .B(CurrentPC[15]), .CI(n_17_15), .CO(n_17_16), .S(n_46) + ); + FA_X1_LVT i_17_17( + .A(Instruction[16]), .B(CurrentPC[16]), .CI(n_17_16), .CO(n_17_17), .S(n_47) + ); + FA_X1_LVT i_17_18( + .A(Instruction[17]), .B(CurrentPC[17]), .CI(n_17_17), .CO(n_17_18), .S(n_48) + ); + FA_X1_LVT i_17_19( + .A(Instruction[18]), .B(CurrentPC[18]), .CI(n_17_18), .CO(n_17_19), .S(n_49) + ); + FA_X1_LVT i_17_20( + .A(Instruction[19]), .B(CurrentPC[19]), .CI(n_17_19), .CO(n_17_20), .S(n_50) + ); + FA_X1_LVT i_17_21( + .A(CurrentPC[20]), .B(Instruction[31]), .CI(n_17_20), .CO(n_17_21), .S(n_51) + ); + FA_X1_LVT i_17_22( + .A(n_17_0), .B(n_17_1), .CI(n_17_21), .CO(n_17_22), .S(n_52) + ); + FA_X1_LVT i_17_23( + .A(CurrentPC[22]), .B(n_17_1), .CI(n_17_22), .CO(n_17_23), .S(n_53) + ); + FA_X1_LVT i_17_24( + .A(CurrentPC[23]), .B(n_17_1), .CI(n_17_23), .CO(n_17_24), .S(n_54) + ); + FA_X1_LVT i_17_25( + .A(CurrentPC[24]), .B(n_17_1), .CI(n_17_24), .CO(n_17_25), .S(n_55) + ); + FA_X1_LVT i_17_26( + .A(CurrentPC[25]), .B(n_17_1), .CI(n_17_25), .CO(n_17_26), .S(n_56) + ); + FA_X1_LVT i_17_27( + .A(CurrentPC[26]), .B(n_17_1), .CI(n_17_26), .CO(n_17_27), .S(n_57) + ); + FA_X1_LVT i_17_28( + .A(CurrentPC[27]), .B(n_17_1), .CI(n_17_27), .CO(n_17_28), .S(n_58) + ); + FA_X1_LVT i_17_29( + .A(CurrentPC[28]), .B(n_17_1), .CI(n_17_28), .CO(n_17_29), .S(n_59) + ); + FA_X1_LVT i_17_30( + .A(CurrentPC[29]), .B(n_17_1), .CI(n_17_29), .CO(n_17_30), .S(n_60) + ); + FA_X1_LVT i_17_31( + .A(CurrentPC[30]), .B(n_17_1), .CI(n_17_30), .CO(n_17_31), .S(n_61) + ); + XNOR2_X1_LVT i_17_33( + .A(n_17_32), .B(n_17_31), .ZN(n_62) + ); + INV_X1_LVT i_5_1( + .A(RRs1[12]), .ZN(n_5_1) + ); + XNOR2_X1_LVT i_5_33( + .A(RRs1[31]), .B(n_5_1), .ZN(n_5_33) + ); + INV_X1_LVT i_5_0( + .A(Instruction[31]), .ZN(n_5_0) + ); + HA_X1_LVT i_5_2( + .A(Instruction[20]), .B(RRs1[0]), .CO(n_5_2), .S(n_0) + ); + FA_X1_LVT i_5_3( + .A(Instruction[21]), .B(RRs1[1]), .CI(n_5_2), .CO(n_5_3), .S(n_1) + ); + FA_X1_LVT i_5_4( + .A(Instruction[22]), .B(RRs1[2]), .CI(n_5_3), .CO(n_5_4), .S(n_2) + ); + FA_X1_LVT i_5_5( + .A(Instruction[23]), .B(RRs1[3]), .CI(n_5_4), .CO(n_5_5), .S(n_3) + ); + FA_X1_LVT i_5_6( + .A(Instruction[24]), .B(RRs1[4]), .CI(n_5_5), .CO(n_5_6), .S(n_4) + ); + FA_X1_LVT i_5_7( + .A(Instruction[25]), .B(RRs1[5]), .CI(n_5_6), .CO(n_5_7), .S(n_5) + ); + FA_X1_LVT i_5_8( + .A(Instruction[26]), .B(RRs1[6]), .CI(n_5_7), .CO(n_5_8), .S(n_6) + ); + FA_X1_LVT i_5_9( + .A(Instruction[27]), .B(RRs1[7]), .CI(n_5_8), .CO(n_5_9), .S(n_7) + ); + FA_X1_LVT i_5_10( + .A(Instruction[28]), .B(RRs1[8]), .CI(n_5_9), .CO(n_5_10), .S(n_8) + ); + FA_X1_LVT i_5_11( + .A(Instruction[29]), .B(RRs1[9]), .CI(n_5_10), .CO(n_5_11), .S(n_9) + ); + FA_X1_LVT i_5_12( + .A(Instruction[30]), .B(RRs1[10]), .CI(n_5_11), .CO(n_5_12), .S(n_10) + ); + FA_X1_LVT i_5_13( + .A(RRs1[11]), .B(Instruction[31]), .CI(n_5_12), .CO(n_5_13), .S(n_11) + ); + FA_X1_LVT i_5_14( + .A(n_5_0), .B(n_5_1), .CI(n_5_13), .CO(n_5_14), .S(n_12) + ); + FA_X1_LVT i_5_15( + .A(RRs1[13]), .B(n_5_1), .CI(n_5_14), .CO(n_5_15), .S(n_13) + ); + FA_X1_LVT i_5_16( + .A(RRs1[14]), .B(n_5_1), .CI(n_5_15), .CO(n_5_16), .S(n_14) + ); + FA_X1_LVT i_5_17( + .A(RRs1[15]), .B(n_5_1), .CI(n_5_16), .CO(n_5_17), .S(n_15) + ); + FA_X1_LVT i_5_18( + .A(RRs1[16]), .B(n_5_1), .CI(n_5_17), .CO(n_5_18), .S(n_16) + ); + FA_X1_LVT i_5_19( + .A(RRs1[17]), .B(n_5_1), .CI(n_5_18), .CO(n_5_19), .S(n_17) + ); + FA_X1_LVT i_5_20( + .A(RRs1[18]), .B(n_5_1), .CI(n_5_19), .CO(n_5_20), .S(n_18) + ); + FA_X1_LVT i_5_21( + .A(RRs1[19]), .B(n_5_1), .CI(n_5_20), .CO(n_5_21), .S(n_19) + ); + FA_X1_LVT i_5_22( + .A(RRs1[20]), .B(n_5_1), .CI(n_5_21), .CO(n_5_22), .S(n_20) + ); + FA_X1_LVT i_5_23( + .A(RRs1[21]), .B(n_5_1), .CI(n_5_22), .CO(n_5_23), .S(n_21) + ); + FA_X1_LVT i_5_24( + .A(RRs1[22]), .B(n_5_1), .CI(n_5_23), .CO(n_5_24), .S(n_22) + ); + FA_X1_LVT i_5_25( + .A(RRs1[23]), .B(n_5_1), .CI(n_5_24), .CO(n_5_25), .S(n_23) + ); + FA_X1_LVT i_5_26( + .A(RRs1[24]), .B(n_5_1), .CI(n_5_25), .CO(n_5_26), .S(n_24) + ); + FA_X1_LVT i_5_27( + .A(RRs1[25]), .B(n_5_1), .CI(n_5_26), .CO(n_5_27), .S(n_25) + ); + FA_X1_LVT i_5_28( + .A(RRs1[26]), .B(n_5_1), .CI(n_5_27), .CO(n_5_28), .S(n_26) + ); + FA_X1_LVT i_5_29( + .A(RRs1[27]), .B(n_5_1), .CI(n_5_28), .CO(n_5_29), .S(n_27) + ); + FA_X1_LVT i_5_30( + .A(RRs1[28]), .B(n_5_1), .CI(n_5_29), .CO(n_5_30), .S(n_28) + ); + FA_X1_LVT i_5_31( + .A(RRs1[29]), .B(n_5_1), .CI(n_5_30), .CO(n_5_31), .S(n_29) + ); + FA_X1_LVT i_5_32( + .A(RRs1[30]), .B(n_5_1), .CI(n_5_31), .CO(n_5_32), .S(n_30) + ); + XNOR2_X1_LVT i_5_34( + .A(n_5_33), .B(n_5_32), .ZN(n_31) + ); + NOR2_X1_LVT i_0_107( + .A1(n_0_249), .A2(Instruction[3]), .ZN(n_0_90) + ); + AOI222_X1_LVT i_0_106( + .A1(n_93), .A2(n_0_99), .B1(n_0_91), .B2(n_62), .C1(n_31), .C2(n_0_90), .ZN(n_0_89) + ); + INV_X1_LVT i_0_355( + .A(Instruction[6]), .ZN(n_0_248) + ); + NAND2_X1_LVT i_0_339( + .A1(n_0_248), .A2(Instruction[4]), .ZN(n_0_234) + ); + INV_X1_LVT i_0_338( + .A(n_0_234), .ZN(n_0_233) + ); + OAI21_X1_LVT i_0_341( + .A(Instruction[13]), .B1(Instruction[14]), .B2(Instruction[12]), .ZN(n_0_236) + ); + AOI211_X1_LVT i_0_337( + .A(n_0_235), .B(n_0_233), .C1(n_0_248), .C2(n_0_236), .ZN(n_0_232) + ); + INV_X1_LVT i_0_352( + .A(Instruction[4]), .ZN(n_0_245) + ); + NAND2_X1_LVT i_0_344( + .A1(n_0_245), .A2(Instruction[2]), .ZN(n_0_239) + ); + AOI21_X1_LVT i_0_335( + .A(Instruction[6]), .B1(n_0_243), .B2(n_0_239), .ZN(n_0_230) + ); + NOR2_X1_LVT i_0_334( + .A1(n_0_232), .A2(n_0_230), .ZN(n_0_229) + ); + NAND2_X1_LVT i_0_342( + .A1(n_0_241), .A2(n_0_238), .ZN(n_0_237) + ); + NAND2_X1_LVT i_0_336( + .A1(Instruction[6]), .A2(n_0_240), .ZN(n_0_231) + ); + OAI211_X1_LVT i_0_333( + .A(n_0_229), .B(n_0_237), .C1(Instruction[2]), .C2(n_0_231), .ZN(Illegal) + ); + NAND2_X1_LVT i_0_109( + .A1(Illegal), .A2(CurrentPC[31]), .ZN(n_0_92) + ); + NAND2_X1_LVT i_0_105( + .A1(n_0_89), .A2(n_0_92), .ZN(JumpOrBranchPC[31]) + ); + AOI222_X1_LVT i_0_103( + .A1(n_92), .A2(n_0_99), .B1(n_0_91), .B2(n_61), .C1(n_30), .C2(n_0_90), .ZN(n_0_87) + ); + NAND2_X1_LVT i_0_104( + .A1(Illegal), .A2(CurrentPC[30]), .ZN(n_0_88) + ); + NAND2_X1_LVT i_0_102( + .A1(n_0_87), .A2(n_0_88), .ZN(JumpOrBranchPC[30]) + ); + AOI222_X1_LVT i_0_100( + .A1(n_91), .A2(n_0_99), .B1(n_0_91), .B2(n_60), .C1(n_29), .C2(n_0_90), .ZN(n_0_85) + ); + NAND2_X1_LVT i_0_101( + .A1(Illegal), .A2(CurrentPC[29]), .ZN(n_0_86) + ); + NAND2_X1_LVT i_0_99( + .A1(n_0_85), .A2(n_0_86), .ZN(JumpOrBranchPC[29]) + ); + AOI222_X1_LVT i_0_97( + .A1(n_90), .A2(n_0_99), .B1(n_0_91), .B2(n_59), .C1(n_28), .C2(n_0_90), .ZN(n_0_83) + ); + NAND2_X1_LVT i_0_98( + .A1(Illegal), .A2(CurrentPC[28]), .ZN(n_0_84) + ); + NAND2_X1_LVT i_0_96( + .A1(n_0_83), .A2(n_0_84), .ZN(JumpOrBranchPC[28]) + ); + AOI222_X1_LVT i_0_94( + .A1(n_89), .A2(n_0_99), .B1(n_0_91), .B2(n_58), .C1(n_27), .C2(n_0_90), .ZN(n_0_81) + ); + NAND2_X1_LVT i_0_95( + .A1(Illegal), .A2(CurrentPC[27]), .ZN(n_0_82) + ); + NAND2_X1_LVT i_0_93( + .A1(n_0_81), .A2(n_0_82), .ZN(JumpOrBranchPC[27]) + ); + AOI222_X1_LVT i_0_91( + .A1(n_88), .A2(n_0_99), .B1(n_0_91), .B2(n_57), .C1(n_26), .C2(n_0_90), .ZN(n_0_79) + ); + NAND2_X1_LVT i_0_92( + .A1(Illegal), .A2(CurrentPC[26]), .ZN(n_0_80) + ); + NAND2_X1_LVT i_0_90( + .A1(n_0_79), .A2(n_0_80), .ZN(JumpOrBranchPC[26]) + ); + AOI222_X1_LVT i_0_88( + .A1(n_87), .A2(n_0_99), .B1(n_0_91), .B2(n_56), .C1(n_25), .C2(n_0_90), .ZN(n_0_77) + ); + NAND2_X1_LVT i_0_89( + .A1(Illegal), .A2(CurrentPC[25]), .ZN(n_0_78) + ); + NAND2_X1_LVT i_0_87( + .A1(n_0_77), .A2(n_0_78), .ZN(JumpOrBranchPC[25]) + ); + AOI222_X1_LVT i_0_85( + .A1(n_86), .A2(n_0_99), .B1(n_0_91), .B2(n_55), .C1(n_24), .C2(n_0_90), .ZN(n_0_75) + ); + NAND2_X1_LVT i_0_86( + .A1(Illegal), .A2(CurrentPC[24]), .ZN(n_0_76) + ); + NAND2_X1_LVT i_0_84( + .A1(n_0_75), .A2(n_0_76), .ZN(JumpOrBranchPC[24]) + ); + AOI222_X1_LVT i_0_82( + .A1(n_85), .A2(n_0_99), .B1(n_0_91), .B2(n_54), .C1(n_23), .C2(n_0_90), .ZN(n_0_73) + ); + NAND2_X1_LVT i_0_83( + .A1(Illegal), .A2(CurrentPC[23]), .ZN(n_0_74) + ); + NAND2_X1_LVT i_0_81( + .A1(n_0_73), .A2(n_0_74), .ZN(JumpOrBranchPC[23]) + ); + AOI222_X1_LVT i_0_79( + .A1(n_84), .A2(n_0_99), .B1(n_0_91), .B2(n_53), .C1(n_22), .C2(n_0_90), .ZN(n_0_71) + ); + NAND2_X1_LVT i_0_80( + .A1(Illegal), .A2(CurrentPC[22]), .ZN(n_0_72) + ); + NAND2_X1_LVT i_0_78( + .A1(n_0_71), .A2(n_0_72), .ZN(JumpOrBranchPC[22]) + ); + AOI222_X1_LVT i_0_76( + .A1(n_83), .A2(n_0_99), .B1(n_0_91), .B2(n_52), .C1(n_21), .C2(n_0_90), .ZN(n_0_69) + ); + NAND2_X1_LVT i_0_77( + .A1(Illegal), .A2(CurrentPC[21]), .ZN(n_0_70) + ); + NAND2_X1_LVT i_0_75( + .A1(n_0_69), .A2(n_0_70), .ZN(JumpOrBranchPC[21]) + ); + AOI222_X1_LVT i_0_73( + .A1(n_82), .A2(n_0_99), .B1(n_0_91), .B2(n_51), .C1(n_20), .C2(n_0_90), .ZN(n_0_67) + ); + NAND2_X1_LVT i_0_74( + .A1(Illegal), .A2(CurrentPC[20]), .ZN(n_0_68) + ); + NAND2_X1_LVT i_0_72( + .A1(n_0_67), .A2(n_0_68), .ZN(JumpOrBranchPC[20]) + ); + AOI222_X1_LVT i_0_70( + .A1(n_81), .A2(n_0_99), .B1(n_0_91), .B2(n_50), .C1(n_19), .C2(n_0_90), .ZN(n_0_65) + ); + NAND2_X1_LVT i_0_71( + .A1(Illegal), .A2(CurrentPC[19]), .ZN(n_0_66) + ); + NAND2_X1_LVT i_0_69( + .A1(n_0_65), .A2(n_0_66), .ZN(JumpOrBranchPC[19]) + ); + AOI222_X1_LVT i_0_67( + .A1(n_80), .A2(n_0_99), .B1(n_0_91), .B2(n_49), .C1(n_18), .C2(n_0_90), .ZN(n_0_63) + ); + NAND2_X1_LVT i_0_68( + .A1(Illegal), .A2(CurrentPC[18]), .ZN(n_0_64) + ); + NAND2_X1_LVT i_0_66( + .A1(n_0_63), .A2(n_0_64), .ZN(JumpOrBranchPC[18]) + ); + AOI222_X1_LVT i_0_64( + .A1(n_79), .A2(n_0_99), .B1(n_0_91), .B2(n_48), .C1(n_17), .C2(n_0_90), .ZN(n_0_61) + ); + NAND2_X1_LVT i_0_65( + .A1(Illegal), .A2(CurrentPC[17]), .ZN(n_0_62) + ); + NAND2_X1_LVT i_0_63( + .A1(n_0_61), .A2(n_0_62), .ZN(JumpOrBranchPC[17]) + ); + AOI222_X1_LVT i_0_61( + .A1(n_78), .A2(n_0_99), .B1(n_0_91), .B2(n_47), .C1(n_16), .C2(n_0_90), .ZN(n_0_59) + ); + NAND2_X1_LVT i_0_62( + .A1(Illegal), .A2(CurrentPC[16]), .ZN(n_0_60) + ); + NAND2_X1_LVT i_0_60( + .A1(n_0_59), .A2(n_0_60), .ZN(JumpOrBranchPC[16]) + ); + AOI222_X1_LVT i_0_58( + .A1(n_77), .A2(n_0_99), .B1(n_0_91), .B2(n_46), .C1(n_15), .C2(n_0_90), .ZN(n_0_57) + ); + NAND2_X1_LVT i_0_59( + .A1(Illegal), .A2(CurrentPC[15]), .ZN(n_0_58) + ); + NAND2_X1_LVT i_0_57( + .A1(n_0_57), .A2(n_0_58), .ZN(JumpOrBranchPC[15]) + ); + AOI222_X1_LVT i_0_55( + .A1(n_76), .A2(n_0_99), .B1(n_0_91), .B2(n_45), .C1(n_14), .C2(n_0_90), .ZN(n_0_55) + ); + NAND2_X1_LVT i_0_56( + .A1(Illegal), .A2(CurrentPC[14]), .ZN(n_0_56) + ); + NAND2_X1_LVT i_0_54( + .A1(n_0_55), .A2(n_0_56), .ZN(JumpOrBranchPC[14]) + ); + AOI222_X1_LVT i_0_52( + .A1(n_75), .A2(n_0_99), .B1(n_0_91), .B2(n_44), .C1(n_13), .C2(n_0_90), .ZN(n_0_53) + ); + NAND2_X1_LVT i_0_53( + .A1(Illegal), .A2(CurrentPC[13]), .ZN(n_0_54) + ); + NAND2_X1_LVT i_0_51( + .A1(n_0_53), .A2(n_0_54), .ZN(JumpOrBranchPC[13]) + ); + AOI222_X1_LVT i_0_49( + .A1(n_74), .A2(n_0_99), .B1(n_0_91), .B2(n_43), .C1(n_12), .C2(n_0_90), .ZN(n_0_51) + ); + NAND2_X1_LVT i_0_50( + .A1(Illegal), .A2(CurrentPC[12]), .ZN(n_0_52) + ); + NAND2_X1_LVT i_0_48( + .A1(n_0_51), .A2(n_0_52), .ZN(JumpOrBranchPC[12]) + ); + AOI222_X1_LVT i_0_46( + .A1(n_73), .A2(n_0_99), .B1(n_0_91), .B2(n_42), .C1(n_11), .C2(n_0_90), .ZN(n_0_49) + ); + NAND2_X1_LVT i_0_47( + .A1(Illegal), .A2(CurrentPC[11]), .ZN(n_0_50) + ); + NAND2_X1_LVT i_0_45( + .A1(n_0_49), .A2(n_0_50), .ZN(JumpOrBranchPC[11]) + ); + AOI222_X1_LVT i_0_43( + .A1(n_72), .A2(n_0_99), .B1(n_0_91), .B2(n_41), .C1(n_10), .C2(n_0_90), .ZN(n_0_47) + ); + NAND2_X1_LVT i_0_44( + .A1(Illegal), .A2(CurrentPC[10]), .ZN(n_0_48) + ); + NAND2_X1_LVT i_0_42( + .A1(n_0_47), .A2(n_0_48), .ZN(JumpOrBranchPC[10]) + ); + AOI222_X1_LVT i_0_40( + .A1(n_71), .A2(n_0_99), .B1(n_0_91), .B2(n_40), .C1(n_9), .C2(n_0_90), .ZN(n_0_45) + ); + NAND2_X1_LVT i_0_41( + .A1(Illegal), .A2(CurrentPC[9]), .ZN(n_0_46) + ); + NAND2_X1_LVT i_0_39( + .A1(n_0_45), .A2(n_0_46), .ZN(JumpOrBranchPC[9]) + ); + AOI222_X1_LVT i_0_37( + .A1(n_70), .A2(n_0_99), .B1(n_0_91), .B2(n_39), .C1(n_8), .C2(n_0_90), .ZN(n_0_43) + ); + NAND2_X1_LVT i_0_38( + .A1(Illegal), .A2(CurrentPC[8]), .ZN(n_0_44) + ); + NAND2_X1_LVT i_0_36( + .A1(n_0_43), .A2(n_0_44), .ZN(JumpOrBranchPC[8]) + ); + AOI222_X1_LVT i_0_34( + .A1(n_69), .A2(n_0_99), .B1(n_0_91), .B2(n_38), .C1(n_7), .C2(n_0_90), .ZN(n_0_41) + ); + NAND2_X1_LVT i_0_35( + .A1(Illegal), .A2(CurrentPC[7]), .ZN(n_0_42) + ); + NAND2_X1_LVT i_0_33( + .A1(n_0_41), .A2(n_0_42), .ZN(JumpOrBranchPC[7]) + ); + AOI222_X1_LVT i_0_31( + .A1(n_68), .A2(n_0_99), .B1(n_0_91), .B2(n_37), .C1(n_6), .C2(n_0_90), .ZN(n_0_39) + ); + NAND2_X1_LVT i_0_32( + .A1(Illegal), .A2(CurrentPC[6]), .ZN(n_0_40) + ); + NAND2_X1_LVT i_0_30( + .A1(n_0_39), .A2(n_0_40), .ZN(JumpOrBranchPC[6]) + ); + AOI222_X1_LVT i_0_28( + .A1(n_67), .A2(n_0_99), .B1(n_0_91), .B2(n_36), .C1(n_5), .C2(n_0_90), .ZN(n_0_37) + ); + NAND2_X1_LVT i_0_29( + .A1(Illegal), .A2(CurrentPC[5]), .ZN(n_0_38) + ); + NAND2_X1_LVT i_0_27( + .A1(n_0_37), .A2(n_0_38), .ZN(JumpOrBranchPC[5]) + ); + AOI222_X1_LVT i_0_25( + .A1(n_66), .A2(n_0_99), .B1(n_0_91), .B2(n_35), .C1(n_4), .C2(n_0_90), .ZN(n_0_35) + ); + NAND2_X1_LVT i_0_26( + .A1(Illegal), .A2(CurrentPC[4]), .ZN(n_0_36) + ); + NAND2_X1_LVT i_0_24( + .A1(n_0_35), .A2(n_0_36), .ZN(JumpOrBranchPC[4]) + ); + AOI222_X1_LVT i_0_22( + .A1(n_65), .A2(n_0_99), .B1(n_0_91), .B2(n_34), .C1(n_3), .C2(n_0_90), .ZN(n_0_33) + ); + NAND2_X1_LVT i_0_23( + .A1(Illegal), .A2(CurrentPC[3]), .ZN(n_0_34) + ); + NAND2_X1_LVT i_0_21( + .A1(n_0_33), .A2(n_0_34), .ZN(JumpOrBranchPC[3]) + ); + AOI222_X1_LVT i_0_19( + .A1(n_64), .A2(n_0_99), .B1(n_0_91), .B2(n_33), .C1(n_2), .C2(n_0_90), .ZN(n_0_31) + ); + NAND2_X1_LVT i_0_20( + .A1(Illegal), .A2(CurrentPC[2]), .ZN(n_0_32) + ); + NAND2_X1_LVT i_0_18( + .A1(n_0_31), .A2(n_0_32), .ZN(JumpOrBranchPC[2]) + ); + AOI222_X1_LVT i_0_16( + .A1(n_63), .A2(n_0_99), .B1(n_0_91), .B2(n_32), .C1(n_1), .C2(n_0_90), .ZN(n_0_29) + ); + NAND2_X1_LVT i_0_17( + .A1(Illegal), .A2(CurrentPC[1]), .ZN(n_0_30) + ); + NAND2_X1_LVT i_0_15( + .A1(n_0_29), .A2(n_0_30), .ZN(JumpOrBranchPC[1]) + ); + NOR2_X1_LVT i_0_112( + .A1(n_0_232), .A2(n_0_238), .ZN(n_0_94) + ); + OAI221_X1_LVT i_0_14( + .A(n_0_94), .B1(n_0_225), .B2(Instruction[2]), .C1(Instruction[6]), .C2(n_0_239), + .ZN(n_0_28) + ); + AND2_X1_LVT i_0_13( + .A1(n_0_28), .A2(CurrentPC[0]), .ZN(JumpOrBranchPC[0]) + ); + NOR2_X1_LVT i_0_221( + .A1(Instruction[13]), .A2(Instruction[14]), .ZN(n_0_166) + ); + NOR3_X1_LVT i_0_293( + .A1(n_0_241), .A2(n_0_234), .A3(Instruction[3]), .ZN(n_0_206) + ); + AND2_X1_LVT i_0_292( + .A1(n_0_206), .A2(n_0_244), .ZN(n_0_205) + ); + NOR3_X1_LVT i_0_330( + .A1(n_0_248), .A2(n_0_244), .A3(Instruction[4]), .ZN(n_0_226) + ); + AOI21_X1_LVT i_0_121( + .A(n_0_205), .B1(n_0_226), .B2(n_0_237), .ZN(n_0_100) + ); + AND2_X1_LVT i_0_120( + .A1(Instruction[14]), .A2(n_0_100), .ZN(aluOp[2]) + ); + OAI33_X1_LVT i_0_119( + .A1(n_0_205), .A2(n_0_247), .A3(n_0_224), .B1(Instruction[2]), .B2(n_0_238), + .B3(n_0_225), .ZN(aluOp[1]) + ); + AOI22_X1_LVT i_0_117( + .A1(Instruction[12]), .A2(n_0_100), .B1(n_0_99), .B2(Instruction[13]), .ZN(n_0_98) + ); + INV_X1_LVT i_0_116( + .A(n_0_98), .ZN(aluOp[0]) + ); + OR2_X1_LVT i_0_327( + .A1(n_0_238), .A2(n_0_234), .ZN(n_0_223) + ); + NOR4_X1_LVT i_0_125( + .A1(Instruction[28]), .A2(Instruction[27]), .A3(Instruction[26]), .A4(Instruction[25]), + .ZN(n_0_103) + ); + INV_X1_LVT i_0_347( + .A(Instruction[30]), .ZN(n_0_242) + ); + NOR4_X1_LVT i_0_124( + .A1(Instruction[13]), .A2(n_0_242), .A3(Instruction[29]), .A4(Instruction[31]), + .ZN(n_0_102) + ); + NAND2_X1_LVT i_0_123( + .A1(n_0_103), .A2(n_0_102), .ZN(n_0_101) + ); + NOR3_X1_LVT i_0_127( + .A1(n_0_244), .A2(Instruction[12]), .A3(Instruction[14]), .ZN(n_0_105) + ); + AOI21_X1_LVT i_0_126( + .A(n_0_105), .B1(Instruction[12]), .B2(Instruction[14]), .ZN(n_0_104) + ); + NOR4_X1_LVT i_0_122( + .A1(n_0_223), .A2(n_0_101), .A3(n_0_104), .A4(Instruction[2]), .ZN(aluNegAr) + ); + OR3_X1_LVT i_0_325( + .A1(n_0_228), .A2(Instruction[4]), .A3(Instruction[6]), .ZN(n_0_222) + ); + NOR2_X1_LVT i_0_321( + .A1(n_0_222), .A2(Instruction[5]), .ZN(n_0_221) + ); + NOR3_X1_LVT i_0_224( + .A1(n_0_224), .A2(n_0_221), .A3(n_0_206), .ZN(n_0_169) + ); + NOR3_X1_LVT i_0_129( + .A1(n_0_234), .A2(Instruction[3]), .A3(Instruction[5]), .ZN(n_0_106) + ); + NOR3_X1_LVT i_0_128( + .A1(n_0_226), .A2(n_0_169), .A3(n_0_106), .ZN(aluBypass) + ); + AOI22_X1_LVT i_0_223( + .A1(CurrentPC[31]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[31]), .ZN(n_0_168) + ); + NOR3_X1_LVT i_0_219( + .A1(n_0_247), .A2(n_0_222), .A3(Instruction[5]), .ZN(n_0_164) + ); + AOI22_X1_LVT i_0_218( + .A1(RRs1[31]), .A2(n_0_169), .B1(n_0_164), .B2(RData[31]), .ZN(n_0_163) + ); + MUX2_X1_LVT i_0_222( + .A(RData[7]), .B(RData[15]), .S(Instruction[12]), .Z(n_0_167) + ); + NAND3_X1_LVT i_0_220( + .A1(n_0_221), .A2(n_0_167), .A3(n_0_166), .ZN(n_0_165) + ); + NAND3_X1_LVT i_0_217( + .A1(n_0_168), .A2(n_0_163), .A3(n_0_165), .ZN(op1[31]) + ); + AOI22_X1_LVT i_0_216( + .A1(RRs1[30]), .A2(n_0_169), .B1(n_0_164), .B2(RData[30]), .ZN(n_0_162) + ); + AOI22_X1_LVT i_0_215( + .A1(CurrentPC[30]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[30]), .ZN(n_0_161) + ); + NAND3_X1_LVT i_0_214( + .A1(n_0_162), .A2(n_0_161), .A3(n_0_165), .ZN(op1[30]) + ); + AOI22_X1_LVT i_0_213( + .A1(RRs1[29]), .A2(n_0_169), .B1(n_0_164), .B2(RData[29]), .ZN(n_0_160) + ); + AOI22_X1_LVT i_0_212( + .A1(CurrentPC[29]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[29]), .ZN(n_0_159) + ); + NAND3_X1_LVT i_0_211( + .A1(n_0_160), .A2(n_0_159), .A3(n_0_165), .ZN(op1[29]) + ); + AOI22_X1_LVT i_0_210( + .A1(RRs1[28]), .A2(n_0_169), .B1(n_0_164), .B2(RData[28]), .ZN(n_0_158) + ); + AOI22_X1_LVT i_0_209( + .A1(CurrentPC[28]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[28]), .ZN(n_0_157) + ); + NAND3_X1_LVT i_0_208( + .A1(n_0_158), .A2(n_0_157), .A3(n_0_165), .ZN(op1[28]) + ); + AOI22_X1_LVT i_0_207( + .A1(RRs1[27]), .A2(n_0_169), .B1(n_0_164), .B2(RData[27]), .ZN(n_0_156) + ); + AOI22_X1_LVT i_0_206( + .A1(CurrentPC[27]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[27]), .ZN(n_0_155) + ); + NAND3_X1_LVT i_0_205( + .A1(n_0_156), .A2(n_0_155), .A3(n_0_165), .ZN(op1[27]) + ); + AOI22_X1_LVT i_0_204( + .A1(RRs1[26]), .A2(n_0_169), .B1(n_0_164), .B2(RData[26]), .ZN(n_0_154) + ); + AOI22_X1_LVT i_0_203( + .A1(CurrentPC[26]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[26]), .ZN(n_0_153) + ); + NAND3_X1_LVT i_0_202( + .A1(n_0_154), .A2(n_0_153), .A3(n_0_165), .ZN(op1[26]) + ); + AOI22_X1_LVT i_0_201( + .A1(RRs1[25]), .A2(n_0_169), .B1(n_0_164), .B2(RData[25]), .ZN(n_0_152) + ); + AOI22_X1_LVT i_0_200( + .A1(CurrentPC[25]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[25]), .ZN(n_0_151) + ); + NAND3_X1_LVT i_0_199( + .A1(n_0_152), .A2(n_0_151), .A3(n_0_165), .ZN(op1[25]) + ); + AOI22_X1_LVT i_0_198( + .A1(RRs1[24]), .A2(n_0_169), .B1(n_0_164), .B2(RData[24]), .ZN(n_0_150) + ); + AOI22_X1_LVT i_0_197( + .A1(CurrentPC[24]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[24]), .ZN(n_0_149) + ); + NAND3_X1_LVT i_0_196( + .A1(n_0_150), .A2(n_0_149), .A3(n_0_165), .ZN(op1[24]) + ); + AOI22_X1_LVT i_0_195( + .A1(RRs1[23]), .A2(n_0_169), .B1(n_0_164), .B2(RData[23]), .ZN(n_0_148) + ); + AOI22_X1_LVT i_0_194( + .A1(CurrentPC[23]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[23]), .ZN(n_0_147) + ); + NAND3_X1_LVT i_0_193( + .A1(n_0_148), .A2(n_0_147), .A3(n_0_165), .ZN(op1[23]) + ); + AOI22_X1_LVT i_0_192( + .A1(RRs1[22]), .A2(n_0_169), .B1(n_0_164), .B2(RData[22]), .ZN(n_0_146) + ); + AOI22_X1_LVT i_0_191( + .A1(CurrentPC[22]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[22]), .ZN(n_0_145) + ); + NAND3_X1_LVT i_0_190( + .A1(n_0_146), .A2(n_0_145), .A3(n_0_165), .ZN(op1[22]) + ); + AOI22_X1_LVT i_0_189( + .A1(RRs1[21]), .A2(n_0_169), .B1(n_0_164), .B2(RData[21]), .ZN(n_0_144) + ); + AOI22_X1_LVT i_0_188( + .A1(CurrentPC[21]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[21]), .ZN(n_0_143) + ); + NAND3_X1_LVT i_0_187( + .A1(n_0_144), .A2(n_0_143), .A3(n_0_165), .ZN(op1[21]) + ); + AOI22_X1_LVT i_0_186( + .A1(RRs1[20]), .A2(n_0_169), .B1(n_0_164), .B2(RData[20]), .ZN(n_0_142) + ); + AOI22_X1_LVT i_0_185( + .A1(CurrentPC[20]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[20]), .ZN(n_0_141) + ); + NAND3_X1_LVT i_0_184( + .A1(n_0_142), .A2(n_0_141), .A3(n_0_165), .ZN(op1[20]) + ); + AOI22_X1_LVT i_0_183( + .A1(RRs1[19]), .A2(n_0_169), .B1(n_0_164), .B2(RData[19]), .ZN(n_0_140) + ); + AOI22_X1_LVT i_0_182( + .A1(CurrentPC[19]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[19]), .ZN(n_0_139) + ); + NAND3_X1_LVT i_0_181( + .A1(n_0_140), .A2(n_0_139), .A3(n_0_165), .ZN(op1[19]) + ); + AOI22_X1_LVT i_0_180( + .A1(RRs1[18]), .A2(n_0_169), .B1(n_0_164), .B2(RData[18]), .ZN(n_0_138) + ); + AOI22_X1_LVT i_0_179( + .A1(CurrentPC[18]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[18]), .ZN(n_0_137) + ); + NAND3_X1_LVT i_0_178( + .A1(n_0_138), .A2(n_0_137), .A3(n_0_165), .ZN(op1[18]) + ); + AOI22_X1_LVT i_0_177( + .A1(RRs1[17]), .A2(n_0_169), .B1(n_0_164), .B2(RData[17]), .ZN(n_0_136) + ); + AOI22_X1_LVT i_0_176( + .A1(CurrentPC[17]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[17]), .ZN(n_0_135) + ); + NAND3_X1_LVT i_0_175( + .A1(n_0_136), .A2(n_0_135), .A3(n_0_165), .ZN(op1[17]) + ); + AOI22_X1_LVT i_0_174( + .A1(RRs1[16]), .A2(n_0_169), .B1(n_0_164), .B2(RData[16]), .ZN(n_0_134) + ); + AOI22_X1_LVT i_0_173( + .A1(CurrentPC[16]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[16]), .ZN(n_0_133) + ); + NAND3_X1_LVT i_0_172( + .A1(n_0_134), .A2(n_0_133), .A3(n_0_165), .ZN(op1[16]) + ); + AOI222_X1_LVT i_0_169( + .A1(CurrentPC[15]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[15]), .C1(n_0_169), + .C2(RRs1[15]), .ZN(n_0_130) + ); + INV_X1_LVT i_0_353( + .A(Instruction[12]), .ZN(n_0_246) + ); + AOI211_X1_LVT i_0_171( + .A(Instruction[5]), .B(n_0_222), .C1(n_0_247), .C2(n_0_246), .ZN(n_0_132) + ); + OAI211_X1_LVT i_0_170( + .A(RData[15]), .B(n_0_132), .C1(Instruction[13]), .C2(Instruction[14]), .ZN(n_0_131) + ); + NAND3_X1_LVT i_0_168( + .A1(n_0_130), .A2(n_0_131), .A3(n_0_165), .ZN(op1[15]) + ); + AOI22_X1_LVT i_0_167( + .A1(RRs1[14]), .A2(n_0_169), .B1(n_0_132), .B2(RData[14]), .ZN(n_0_129) + ); + AOI22_X1_LVT i_0_166( + .A1(CurrentPC[14]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[14]), .ZN(n_0_128) + ); + NAND4_X1_LVT i_0_165( + .A1(n_0_221), .A2(n_0_246), .A3(RData[7]), .A4(n_0_166), .ZN(n_0_127) + ); + NAND3_X1_LVT i_0_164( + .A1(n_0_129), .A2(n_0_128), .A3(n_0_127), .ZN(op1[14]) + ); + AOI22_X1_LVT i_0_163( + .A1(RRs1[13]), .A2(n_0_169), .B1(n_0_132), .B2(RData[13]), .ZN(n_0_126) + ); + AOI22_X1_LVT i_0_162( + .A1(CurrentPC[13]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[13]), .ZN(n_0_125) + ); + NAND3_X1_LVT i_0_161( + .A1(n_0_126), .A2(n_0_125), .A3(n_0_127), .ZN(op1[13]) + ); + AOI22_X1_LVT i_0_160( + .A1(RRs1[12]), .A2(n_0_169), .B1(n_0_132), .B2(RData[12]), .ZN(n_0_124) + ); + AOI22_X1_LVT i_0_159( + .A1(CurrentPC[12]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[12]), .ZN(n_0_123) + ); + NAND3_X1_LVT i_0_158( + .A1(n_0_124), .A2(n_0_123), .A3(n_0_127), .ZN(op1[12]) + ); + AOI22_X1_LVT i_0_156( + .A1(CurrentPC[11]), .A2(n_0_224), .B1(n_0_132), .B2(RData[11]), .ZN(n_0_121) + ); + NAND2_X1_LVT i_0_157( + .A1(RRs1[11]), .A2(n_0_169), .ZN(n_0_122) + ); + NAND3_X1_LVT i_0_155( + .A1(n_0_121), .A2(n_0_122), .A3(n_0_127), .ZN(op1[11]) + ); + AOI22_X1_LVT i_0_153( + .A1(CurrentPC[10]), .A2(n_0_224), .B1(n_0_132), .B2(RData[10]), .ZN(n_0_119) + ); + NAND2_X1_LVT i_0_154( + .A1(RRs1[10]), .A2(n_0_169), .ZN(n_0_120) + ); + NAND3_X1_LVT i_0_152( + .A1(n_0_119), .A2(n_0_120), .A3(n_0_127), .ZN(op1[10]) + ); + AOI22_X1_LVT i_0_150( + .A1(CurrentPC[9]), .A2(n_0_224), .B1(n_0_132), .B2(RData[9]), .ZN(n_0_117) + ); + NAND2_X1_LVT i_0_151( + .A1(RRs1[9]), .A2(n_0_169), .ZN(n_0_118) + ); + NAND3_X1_LVT i_0_149( + .A1(n_0_117), .A2(n_0_118), .A3(n_0_127), .ZN(op1[9]) + ); + AOI22_X1_LVT i_0_147( + .A1(CurrentPC[8]), .A2(n_0_224), .B1(n_0_132), .B2(RData[8]), .ZN(n_0_115) + ); + NAND2_X1_LVT i_0_148( + .A1(RRs1[8]), .A2(n_0_169), .ZN(n_0_116) + ); + NAND3_X1_LVT i_0_146( + .A1(n_0_115), .A2(n_0_116), .A3(n_0_127), .ZN(op1[8]) + ); + AOI222_X1_LVT i_0_145( + .A1(CurrentPC[7]), .A2(n_0_224), .B1(n_0_221), .B2(RData[7]), .C1(n_0_169), + .C2(RRs1[7]), .ZN(n_0_114) + ); + INV_X1_LVT i_0_144( + .A(n_0_114), .ZN(op1[7]) + ); + AOI222_X1_LVT i_0_143( + .A1(CurrentPC[6]), .A2(n_0_224), .B1(n_0_221), .B2(RData[6]), .C1(n_0_169), + .C2(RRs1[6]), .ZN(n_0_113) + ); + INV_X1_LVT i_0_142( + .A(n_0_113), .ZN(op1[6]) + ); + AOI222_X1_LVT i_0_141( + .A1(CurrentPC[5]), .A2(n_0_224), .B1(n_0_221), .B2(RData[5]), .C1(n_0_169), + .C2(RRs1[5]), .ZN(n_0_112) + ); + INV_X1_LVT i_0_140( + .A(n_0_112), .ZN(op1[5]) + ); + AOI222_X1_LVT i_0_139( + .A1(CurrentPC[4]), .A2(n_0_224), .B1(n_0_221), .B2(RData[4]), .C1(n_0_169), + .C2(RRs1[4]), .ZN(n_0_111) + ); + INV_X1_LVT i_0_138( + .A(n_0_111), .ZN(op1[4]) + ); + AOI222_X1_LVT i_0_137( + .A1(CurrentPC[3]), .A2(n_0_224), .B1(n_0_221), .B2(RData[3]), .C1(n_0_169), + .C2(RRs1[3]), .ZN(n_0_110) + ); + INV_X1_LVT i_0_136( + .A(n_0_110), .ZN(op1[3]) + ); + AOI222_X1_LVT i_0_135( + .A1(CurrentPC[2]), .A2(n_0_224), .B1(n_0_221), .B2(RData[2]), .C1(n_0_169), + .C2(RRs1[2]), .ZN(n_0_109) + ); + INV_X1_LVT i_0_134( + .A(n_0_109), .ZN(op1[2]) + ); + AOI222_X1_LVT i_0_133( + .A1(CurrentPC[1]), .A2(n_0_224), .B1(n_0_221), .B2(RData[1]), .C1(n_0_169), + .C2(RRs1[1]), .ZN(n_0_108) + ); + INV_X1_LVT i_0_132( + .A(n_0_108), .ZN(op1[1]) + ); + AOI222_X1_LVT i_0_131( + .A1(CurrentPC[0]), .A2(n_0_224), .B1(n_0_221), .B2(RData[0]), .C1(n_0_169), + .C2(RRs1[0]), .ZN(n_0_107) + ); + INV_X1_LVT i_0_130( + .A(n_0_107), .ZN(op1[0]) + ); + NOR3_X1_LVT i_0_294( + .A1(n_0_223), .A2(Instruction[2]), .A3(Instruction[5]), .ZN(n_0_207) + ); + NOR3_X1_LVT i_0_291( + .A1(n_0_224), .A2(n_0_207), .A3(n_0_205), .ZN(n_0_204) + ); + AOI22_X1_LVT i_0_289( + .A1(CurrentPC[31]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[31]), .ZN(n_0_202) + ); + NAND2_X1_LVT i_0_290( + .A1(Instruction[31]), .A2(n_0_207), .ZN(n_0_203) + ); + NAND2_X1_LVT i_0_288( + .A1(n_0_202), .A2(n_0_203), .ZN(op2[31]) + ); + AOI22_X1_LVT i_0_287( + .A1(CurrentPC[30]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[30]), .ZN(n_0_201) + ); + NAND2_X1_LVT i_0_286( + .A1(n_0_201), .A2(n_0_203), .ZN(op2[30]) + ); + AOI22_X1_LVT i_0_285( + .A1(CurrentPC[29]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[29]), .ZN(n_0_200) + ); + NAND2_X1_LVT i_0_284( + .A1(n_0_200), .A2(n_0_203), .ZN(op2[29]) + ); + AOI22_X1_LVT i_0_283( + .A1(CurrentPC[28]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[28]), .ZN(n_0_199) + ); + NAND2_X1_LVT i_0_282( + .A1(n_0_199), .A2(n_0_203), .ZN(op2[28]) + ); + AOI22_X1_LVT i_0_281( + .A1(CurrentPC[27]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[27]), .ZN(n_0_198) + ); + NAND2_X1_LVT i_0_280( + .A1(n_0_198), .A2(n_0_203), .ZN(op2[27]) + ); + AOI22_X1_LVT i_0_279( + .A1(CurrentPC[26]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[26]), .ZN(n_0_197) + ); + NAND2_X1_LVT i_0_278( + .A1(n_0_197), .A2(n_0_203), .ZN(op2[26]) + ); + AOI22_X1_LVT i_0_277( + .A1(CurrentPC[25]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[25]), .ZN(n_0_196) + ); + NAND2_X1_LVT i_0_276( + .A1(n_0_196), .A2(n_0_203), .ZN(op2[25]) + ); + AOI22_X1_LVT i_0_275( + .A1(CurrentPC[24]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[24]), .ZN(n_0_195) + ); + NAND2_X1_LVT i_0_274( + .A1(n_0_195), .A2(n_0_203), .ZN(op2[24]) + ); + AOI22_X1_LVT i_0_273( + .A1(CurrentPC[23]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[23]), .ZN(n_0_194) + ); + NAND2_X1_LVT i_0_272( + .A1(n_0_194), .A2(n_0_203), .ZN(op2[23]) + ); + AOI22_X1_LVT i_0_271( + .A1(CurrentPC[22]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[22]), .ZN(n_0_193) + ); + NAND2_X1_LVT i_0_270( + .A1(n_0_193), .A2(n_0_203), .ZN(op2[22]) + ); + AOI22_X1_LVT i_0_269( + .A1(CurrentPC[21]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[21]), .ZN(n_0_192) + ); + NAND2_X1_LVT i_0_268( + .A1(n_0_192), .A2(n_0_203), .ZN(op2[21]) + ); + AOI22_X1_LVT i_0_267( + .A1(CurrentPC[20]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[20]), .ZN(n_0_191) + ); + NAND2_X1_LVT i_0_266( + .A1(n_0_191), .A2(n_0_203), .ZN(op2[20]) + ); + AOI22_X1_LVT i_0_265( + .A1(CurrentPC[19]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[19]), .ZN(n_0_190) + ); + NAND2_X1_LVT i_0_264( + .A1(n_0_190), .A2(n_0_203), .ZN(op2[19]) + ); + AOI22_X1_LVT i_0_263( + .A1(CurrentPC[18]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[18]), .ZN(n_0_189) + ); + NAND2_X1_LVT i_0_262( + .A1(n_0_189), .A2(n_0_203), .ZN(op2[18]) + ); + AOI22_X1_LVT i_0_261( + .A1(CurrentPC[17]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[17]), .ZN(n_0_188) + ); + NAND2_X1_LVT i_0_260( + .A1(n_0_188), .A2(n_0_203), .ZN(op2[17]) + ); + AOI22_X1_LVT i_0_259( + .A1(CurrentPC[16]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[16]), .ZN(n_0_187) + ); + NAND2_X1_LVT i_0_258( + .A1(n_0_187), .A2(n_0_203), .ZN(op2[16]) + ); + AOI22_X1_LVT i_0_257( + .A1(CurrentPC[15]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[15]), .ZN(n_0_186) + ); + NAND2_X1_LVT i_0_256( + .A1(n_0_186), .A2(n_0_203), .ZN(op2[15]) + ); + AOI22_X1_LVT i_0_255( + .A1(CurrentPC[14]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[14]), .ZN(n_0_185) + ); + NAND2_X1_LVT i_0_254( + .A1(n_0_185), .A2(n_0_203), .ZN(op2[14]) + ); + AOI22_X1_LVT i_0_253( + .A1(CurrentPC[13]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[13]), .ZN(n_0_184) + ); + NAND2_X1_LVT i_0_252( + .A1(n_0_184), .A2(n_0_203), .ZN(op2[13]) + ); + AOI22_X1_LVT i_0_251( + .A1(CurrentPC[12]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[12]), .ZN(n_0_183) + ); + NAND2_X1_LVT i_0_250( + .A1(n_0_183), .A2(n_0_203), .ZN(op2[12]) + ); + AOI22_X1_LVT i_0_249( + .A1(CurrentPC[11]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[11]), .ZN(n_0_182) + ); + NAND2_X1_LVT i_0_248( + .A1(n_0_182), .A2(n_0_203), .ZN(op2[11]) + ); + AOI222_X1_LVT i_0_247( + .A1(Instruction[30]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[10]), .C1(n_0_204), + .C2(RRs2[10]), .ZN(n_0_181) + ); + INV_X1_LVT i_0_246( + .A(n_0_181), .ZN(op2[10]) + ); + AOI222_X1_LVT i_0_245( + .A1(Instruction[29]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[9]), .C1(n_0_204), + .C2(RRs2[9]), .ZN(n_0_180) + ); + INV_X1_LVT i_0_244( + .A(n_0_180), .ZN(op2[9]) + ); + AOI222_X1_LVT i_0_243( + .A1(Instruction[28]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[8]), .C1(n_0_204), + .C2(RRs2[8]), .ZN(n_0_179) + ); + INV_X1_LVT i_0_242( + .A(n_0_179), .ZN(op2[8]) + ); + AOI222_X1_LVT i_0_241( + .A1(Instruction[27]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[7]), .C1(n_0_204), + .C2(RRs2[7]), .ZN(n_0_178) + ); + INV_X1_LVT i_0_240( + .A(n_0_178), .ZN(op2[7]) + ); + AOI222_X1_LVT i_0_239( + .A1(Instruction[26]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[6]), .C1(n_0_204), + .C2(RRs2[6]), .ZN(n_0_177) + ); + INV_X1_LVT i_0_238( + .A(n_0_177), .ZN(op2[6]) + ); + AOI222_X1_LVT i_0_237( + .A1(Instruction[25]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[5]), .C1(n_0_204), + .C2(RRs2[5]), .ZN(n_0_176) + ); + INV_X1_LVT i_0_236( + .A(n_0_176), .ZN(op2[5]) + ); + AOI222_X1_LVT i_0_235( + .A1(Instruction[24]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[4]), .C1(n_0_204), + .C2(RRs2[4]), .ZN(n_0_175) + ); + INV_X1_LVT i_0_234( + .A(n_0_175), .ZN(op2[4]) + ); + AOI222_X1_LVT i_0_233( + .A1(Instruction[23]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[3]), .C1(n_0_204), + .C2(RRs2[3]), .ZN(n_0_174) + ); + INV_X1_LVT i_0_232( + .A(n_0_174), .ZN(op2[3]) + ); + AOI22_X1_LVT i_0_230( + .A1(Instruction[22]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[2]), .ZN(n_0_172) + ); + OAI21_X1_LVT i_0_231( + .A(RRs2[2]), .B1(n_0_223), .B2(Instruction[5]), .ZN(n_0_173) + ); + NAND3_X1_LVT i_0_229( + .A1(n_0_172), .A2(n_0_173), .A3(n_0_249), .ZN(op2[2]) + ); + AOI222_X1_LVT i_0_228( + .A1(Instruction[21]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[1]), .C1(n_0_204), + .C2(RRs2[1]), .ZN(n_0_171) + ); + INV_X1_LVT i_0_227( + .A(n_0_171), .ZN(op2[1]) + ); + AOI222_X1_LVT i_0_226( + .A1(Instruction[20]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[0]), .C1(n_0_204), + .C2(RRs2[0]), .ZN(n_0_170) + ); + INV_X1_LVT i_0_225( + .A(n_0_170), .ZN(op2[0]) + ); + alu theALU( + .aluOp(aluOp), .aluNegAr(aluNegAr), .aluBypass(aluBypass), .op1(op1), .op2(op2), + .result(WRd), .eqFlag(eqFlag) + ); + XNOR2_X1_LVT i_0_115( + .A(Instruction[12]), .B(eqFlag), .ZN(n_0_97) + ); + XNOR2_X1_LVT i_0_114( + .A(Instruction[12]), .B(WRd[0]), .ZN(n_0_96) + ); + AOI22_X1_LVT i_0_113( + .A1(n_0_166), .A2(n_0_97), .B1(n_0_96), .B2(Instruction[14]), .ZN(n_0_95) + ); + AOI22_X1_LVT i_0_111( + .A1(Instruction[6]), .A2(n_0_95), .B1(Instruction[2]), .B2(n_0_245), .ZN(n_0_93) + ); + NAND2_X1_LVT i_0_110( + .A1(n_0_94), .A2(n_0_93), .ZN(JumpOrBranch) + ); + INV_X1_LVT i_0_349( + .A(Instruction[31]), .ZN(n_0_0) + ); + INV_X1_LVT i_0_348( + .A(RRs1[12]), .ZN(n_0_1) + ); + HA_X1_LVT i_0_0( + .A(Instruction[7]), .B(RRs1[0]), .CO(n_0_2), .S(n_0_15) + ); + FA_X1_LVT i_0_1( + .A(Instruction[8]), .B(RRs1[1]), .CI(n_0_2), .CO(n_0_3), .S(n_0_16) + ); + FA_X1_LVT i_0_2( + .A(Instruction[9]), .B(RRs1[2]), .CI(n_0_3), .CO(n_0_4), .S(n_0_17) + ); + FA_X1_LVT i_0_3( + .A(Instruction[10]), .B(RRs1[3]), .CI(n_0_4), .CO(n_0_5), .S(n_0_18) + ); + FA_X1_LVT i_0_4( + .A(Instruction[11]), .B(RRs1[4]), .CI(n_0_5), .CO(n_0_6), .S(n_0_19) + ); + FA_X1_LVT i_0_5( + .A(Instruction[25]), .B(RRs1[5]), .CI(n_0_6), .CO(n_0_7), .S(n_0_20) + ); + FA_X1_LVT i_0_6( + .A(Instruction[26]), .B(RRs1[6]), .CI(n_0_7), .CO(n_0_8), .S(n_0_21) + ); + FA_X1_LVT i_0_7( + .A(Instruction[27]), .B(RRs1[7]), .CI(n_0_8), .CO(n_0_9), .S(n_0_22) + ); + FA_X1_LVT i_0_8( + .A(Instruction[28]), .B(RRs1[8]), .CI(n_0_9), .CO(n_0_10), .S(n_0_23) + ); + FA_X1_LVT i_0_9( + .A(Instruction[29]), .B(RRs1[9]), .CI(n_0_10), .CO(n_0_11), .S(n_0_24) + ); + FA_X1_LVT i_0_10( + .A(Instruction[30]), .B(RRs1[10]), .CI(n_0_11), .CO(n_0_12), .S(n_0_25) + ); + FA_X1_LVT i_0_11( + .A(RRs1[11]), .B(Instruction[31]), .CI(n_0_12), .CO(n_0_13), .S(n_0_26) + ); + FA_X1_LVT i_0_12( + .A(n_0_0), .B(n_0_1), .CI(n_0_13), .CO(n_0_14), .S(n_0_27) + ); + NOR2_X1_LVT i_0_322( + .A1(n_0_244), .A2(n_0_222), .ZN(WrMem) + ); + AOI22_X1_LVT i_0_320( + .A1(n_0_27), .A2(WrMem), .B1(n_0_221), .B2(n_12), .ZN(n_0_220) + ); + INV_X1_LVT i_0_319( + .A(n_0_220), .ZN(DAddr[12]) + ); + AOI22_X1_LVT i_0_318( + .A1(n_0_26), .A2(WrMem), .B1(n_0_221), .B2(n_11), .ZN(n_0_219) + ); + INV_X1_LVT i_0_317( + .A(n_0_219), .ZN(DAddr[11]) + ); + AOI22_X1_LVT i_0_316( + .A1(n_0_25), .A2(WrMem), .B1(n_0_221), .B2(n_10), .ZN(n_0_218) + ); + INV_X1_LVT i_0_315( + .A(n_0_218), .ZN(DAddr[10]) + ); + AOI22_X1_LVT i_0_314( + .A1(n_0_24), .A2(WrMem), .B1(n_0_221), .B2(n_9), .ZN(n_0_217) + ); + INV_X1_LVT i_0_313( + .A(n_0_217), .ZN(DAddr[9]) + ); + AOI22_X1_LVT i_0_312( + .A1(n_0_23), .A2(WrMem), .B1(n_0_221), .B2(n_8), .ZN(n_0_216) + ); + INV_X1_LVT i_0_311( + .A(n_0_216), .ZN(DAddr[8]) + ); + AOI22_X1_LVT i_0_310( + .A1(n_0_22), .A2(WrMem), .B1(n_0_221), .B2(n_7), .ZN(n_0_215) + ); + INV_X1_LVT i_0_309( + .A(n_0_215), .ZN(DAddr[7]) + ); + AOI22_X1_LVT i_0_308( + .A1(n_0_21), .A2(WrMem), .B1(n_0_221), .B2(n_6), .ZN(n_0_214) + ); + INV_X1_LVT i_0_307( + .A(n_0_214), .ZN(DAddr[6]) + ); + AOI22_X1_LVT i_0_306( + .A1(n_0_20), .A2(WrMem), .B1(n_0_221), .B2(n_5), .ZN(n_0_213) + ); + INV_X1_LVT i_0_305( + .A(n_0_213), .ZN(DAddr[5]) + ); + AOI22_X1_LVT i_0_304( + .A1(n_0_19), .A2(WrMem), .B1(n_0_221), .B2(n_4), .ZN(n_0_212) + ); + INV_X1_LVT i_0_303( + .A(n_0_212), .ZN(DAddr[4]) + ); + AOI22_X1_LVT i_0_302( + .A1(n_0_18), .A2(WrMem), .B1(n_0_221), .B2(n_3), .ZN(n_0_211) + ); + INV_X1_LVT i_0_301( + .A(n_0_211), .ZN(DAddr[3]) + ); + AOI22_X1_LVT i_0_300( + .A1(n_0_17), .A2(WrMem), .B1(n_0_221), .B2(n_2), .ZN(n_0_210) + ); + INV_X1_LVT i_0_299( + .A(n_0_210), .ZN(DAddr[2]) + ); + AOI22_X1_LVT i_0_298( + .A1(n_0_16), .A2(WrMem), .B1(n_0_221), .B2(n_1), .ZN(n_0_209) + ); + INV_X1_LVT i_0_297( + .A(n_0_209), .ZN(DAddr[1]) + ); + AOI22_X1_LVT i_0_296( + .A1(n_0_15), .A2(WrMem), .B1(n_0_221), .B2(n_0), .ZN(n_0_208) + ); + INV_X1_LVT i_0_295( + .A(n_0_208), .ZN(DAddr[0]) + ); + OR2_X1_LVT i_0_324( + .A1(n_0_222), .A2(Instruction[13]), .ZN(DWidth[1]) + ); + NOR2_X1_LVT i_0_323( + .A1(n_0_246), .A2(n_0_222), .ZN(DWidth[0]) + ); + NAND3_X1_LVT i_0_331( + .A1(n_0_248), .A2(n_0_244), .A3(n_0_236), .ZN(n_0_227) + ); + OAI211_X1_LVT i_0_326( + .A(n_0_249), .B(n_0_223), .C1(n_0_228), .C2(n_0_227), .ZN(WrReg) + ); +endmodule + +module MemGen_32_11(chip_en, clock, addr, rd_data, rd_en, wr_en, wr_data); + input [31:0] wr_data; + input [10:0] addr; + input chip_en, clock, rd_en, wr_en; + output [31:0] rd_data; + + wire [1:0] mem_sel; + wire n_63, n_62, n_61, n_60, n_59, n_58, n_57, n_56, n_55, n_54, n_53, n_52, + n_51, n_50, n_49, n_48, n_31, n_30, n_29, n_28, n_27, n_26, n_25, n_24, + n_23, n_22, n_21, n_20, n_19, n_18, n_17, n_16, n_47, n_46, n_45, n_44, + n_43, n_42, n_41, n_40, n_39, n_38, n_37, n_36, n_35, n_34, n_33, n_32, + n_15, n_14, n_13, n_12, n_11, n_10, n_9, n_8, n_7, n_6, n_5, n_4, n_3, + n_2, n_1, n_0; + + INV_X1_LVT i_1_3( + .A(addr[10]), .ZN(mem_sel[0]) + ); + MemGen_16_10 genblk1_0_U_hi( + .chip_en(mem_sel[0]), .wr_en(wr_en), .addr({addr[9], addr[8], addr[7], + addr[6], addr[5], addr[4], addr[3], addr[2], addr[1], addr[0]}), .wr_data({ + wr_data[31], wr_data[30], wr_data[29], wr_data[28], wr_data[27], + wr_data[26], wr_data[25], wr_data[24], wr_data[23], wr_data[22], + wr_data[21], wr_data[20], wr_data[19], wr_data[18], wr_data[17], + wr_data[16]}), .clock(clock), .rd_en(rd_en), .rd_data({n_63, n_62, n_61, + n_60, n_59, n_58, n_57, n_56, n_55, n_54, n_53, n_52, n_51, n_50, n_49, + n_48}) + ); + MemGen_16_10 genblk1_1_U_hi( + .chip_en(addr[10]), .wr_en(wr_en), .addr({addr[9], addr[8], addr[7], + addr[6], addr[5], addr[4], addr[3], addr[2], addr[1], addr[0]}), .wr_data({ + wr_data[31], wr_data[30], wr_data[29], wr_data[28], wr_data[27], + wr_data[26], wr_data[25], wr_data[24], wr_data[23], wr_data[22], + wr_data[21], wr_data[20], wr_data[19], wr_data[18], wr_data[17], + wr_data[16]}), .clock(clock), .rd_en(rd_en), .rd_data({n_31, n_30, n_29, + n_28, n_27, n_26, n_25, n_24, n_23, n_22, n_21, n_20, n_19, n_18, n_17, + n_16}) + ); + MUX2_X1_LVT i_1_1_31( + .A(n_63), .B(n_31), .S(addr[10]), .Z(rd_data[31]) + ); + MUX2_X1_LVT i_1_1_30( + .A(n_62), .B(n_30), .S(addr[10]), .Z(rd_data[30]) + ); + MUX2_X1_LVT i_1_1_29( + .A(n_61), .B(n_29), .S(addr[10]), .Z(rd_data[29]) + ); + MUX2_X1_LVT i_1_1_28( + .A(n_60), .B(n_28), .S(addr[10]), .Z(rd_data[28]) + ); + MUX2_X1_LVT i_1_1_27( + .A(n_59), .B(n_27), .S(addr[10]), .Z(rd_data[27]) + ); + MUX2_X1_LVT i_1_1_26( + .A(n_58), .B(n_26), .S(addr[10]), .Z(rd_data[26]) + ); + MUX2_X1_LVT i_1_1_25( + .A(n_57), .B(n_25), .S(addr[10]), .Z(rd_data[25]) + ); + MUX2_X1_LVT i_1_1_24( + .A(n_56), .B(n_24), .S(addr[10]), .Z(rd_data[24]) + ); + MUX2_X1_LVT i_1_1_23( + .A(n_55), .B(n_23), .S(addr[10]), .Z(rd_data[23]) + ); + MUX2_X1_LVT i_1_1_22( + .A(n_54), .B(n_22), .S(addr[10]), .Z(rd_data[22]) + ); + MUX2_X1_LVT i_1_1_21( + .A(n_53), .B(n_21), .S(addr[10]), .Z(rd_data[21]) + ); + MUX2_X1_LVT i_1_1_20( + .A(n_52), .B(n_20), .S(addr[10]), .Z(rd_data[20]) + ); + MUX2_X1_LVT i_1_1_19( + .A(n_51), .B(n_19), .S(addr[10]), .Z(rd_data[19]) + ); + MUX2_X1_LVT i_1_1_18( + .A(n_50), .B(n_18), .S(addr[10]), .Z(rd_data[18]) + ); + MUX2_X1_LVT i_1_1_17( + .A(n_49), .B(n_17), .S(addr[10]), .Z(rd_data[17]) + ); + MUX2_X1_LVT i_1_1_16( + .A(n_48), .B(n_16), .S(addr[10]), .Z(rd_data[16]) + ); + MemGen_16_10 genblk1_0_U_lo( + .chip_en(mem_sel[0]), .wr_en(wr_en), .addr({addr[9], addr[8], addr[7], + addr[6], addr[5], addr[4], addr[3], addr[2], addr[1], addr[0]}), .wr_data({ + wr_data[15], wr_data[14], wr_data[13], wr_data[12], wr_data[11], + wr_data[10], wr_data[9], wr_data[8], wr_data[7], wr_data[6], wr_data[5], + wr_data[4], wr_data[3], wr_data[2], wr_data[1], wr_data[0]}), .clock(clock), + .rd_en(rd_en), .rd_data({n_47, n_46, n_45, n_44, n_43, n_42, n_41, + n_40, n_39, n_38, n_37, n_36, n_35, n_34, n_33, n_32}) + ); + MemGen_16_10 genblk1_1_U_lo( + .chip_en(addr[10]), .wr_en(wr_en), .addr({addr[9], addr[8], addr[7], + addr[6], addr[5], addr[4], addr[3], addr[2], addr[1], addr[0]}), .wr_data({ + wr_data[15], wr_data[14], wr_data[13], wr_data[12], wr_data[11], + wr_data[10], wr_data[9], wr_data[8], wr_data[7], wr_data[6], wr_data[5], + wr_data[4], wr_data[3], wr_data[2], wr_data[1], wr_data[0]}), .clock(clock), + .rd_en(rd_en), .rd_data({n_15, n_14, n_13, n_12, n_11, n_10, n_9, n_8, + n_7, n_6, n_5, n_4, n_3, n_2, n_1, n_0}) + ); + MUX2_X1_LVT i_1_1_15( + .A(n_47), .B(n_15), .S(addr[10]), .Z(rd_data[15]) + ); + MUX2_X1_LVT i_1_1_14( + .A(n_46), .B(n_14), .S(addr[10]), .Z(rd_data[14]) + ); + MUX2_X1_LVT i_1_1_13( + .A(n_45), .B(n_13), .S(addr[10]), .Z(rd_data[13]) + ); + MUX2_X1_LVT i_1_1_12( + .A(n_44), .B(n_12), .S(addr[10]), .Z(rd_data[12]) + ); + MUX2_X1_LVT i_1_1_11( + .A(n_43), .B(n_11), .S(addr[10]), .Z(rd_data[11]) + ); + MUX2_X1_LVT i_1_1_10( + .A(n_42), .B(n_10), .S(addr[10]), .Z(rd_data[10]) + ); + MUX2_X1_LVT i_1_1_9( + .A(n_41), .B(n_9), .S(addr[10]), .Z(rd_data[9]) + ); + MUX2_X1_LVT i_1_1_8( + .A(n_40), .B(n_8), .S(addr[10]), .Z(rd_data[8]) + ); + MUX2_X1_LVT i_1_1_7( + .A(n_39), .B(n_7), .S(addr[10]), .Z(rd_data[7]) + ); + MUX2_X1_LVT i_1_1_6( + .A(n_38), .B(n_6), .S(addr[10]), .Z(rd_data[6]) + ); + MUX2_X1_LVT i_1_1_5( + .A(n_37), .B(n_5), .S(addr[10]), .Z(rd_data[5]) + ); + MUX2_X1_LVT i_1_1_4( + .A(n_36), .B(n_4), .S(addr[10]), .Z(rd_data[4]) + ); + MUX2_X1_LVT i_1_1_3( + .A(n_35), .B(n_3), .S(addr[10]), .Z(rd_data[3]) + ); + MUX2_X1_LVT i_1_1_2( + .A(n_34), .B(n_2), .S(addr[10]), .Z(rd_data[2]) + ); + MUX2_X1_LVT i_1_1_1( + .A(n_33), .B(n_1), .S(addr[10]), .Z(rd_data[1]) + ); + MUX2_X1_LVT i_1_1_0( + .A(n_32), .B(n_0), .S(addr[10]), .Z(rd_data[0]) + ); +endmodule + +module main_mem(clk, reset, DAddr, IAddr, DWData, DRData, IRData, DWE, DWidth); + input [31:0] DAddr, IAddr, DWData; + input [1:0] DWidth; + input clk, reset, DWE; + output [31:0] DRData, IRData; + + wire [31:0] mem_rdata, drTmp, mem_wdata; + wire [10:0] mem_addr; + wire n_0_0, n_0_0_0, n_0_1, n_0_0_1, n_0_2, n_0_0_2, n_0_3, n_0_0_3, n_0_4, + n_0_0_4, n_0_5, n_0_0_5, n_0_6, n_0_0_6, n_0_7, n_0_0_7, n_0_8, n_0_0_8, + n_0_9, n_0_0_9, n_0_10, n_0_0_10, n_0_0_11, n_0_11, n_0_0_12, n_0_0_13, + n_0_12, n_0_0_14, n_0_0_15, n_0_13, n_0_0_16, n_0_0_17, n_0_14, + n_0_0_18, n_0_0_19, n_0_15, n_0_0_20, n_0_0_21, n_0_16, n_0_0_22, + n_0_0_23, n_0_17, n_0_0_24, n_0_0_25, n_0_18, n_0_0_26, n_0_0_27, + n_0_0_28, n_0_19, n_0_0_29, n_0_20, n_0_0_30, n_0_21, n_0_0_31, n_0_22, + n_0_0_32, n_0_23, n_0_0_33, n_0_24, n_0_0_34, n_0_25, n_0_0_35, n_0_26, + n_0_0_36, n_0_0_37, n_0_27, n_0_28, n_0_29, n_0_30, n_0_31, n_0_32, + n_0_33, n_0_34, n_0_35, n_0_36, n_0_37, n_0_38, n_0_39, n_0_40, n_0_41, + n_0_42, n_0_65, n_0_64, n_0_63, n_0_62, n_0_61, n_0_60, n_0_59, n_0_58, + n_0_0_38, n_0_0_39, n_0_57, n_0_0_40, n_0_56, n_0_0_41, n_0_55, + n_0_0_42, n_0_54, n_0_0_43, n_0_53, n_0_0_44, n_0_52, n_0_0_45, n_0_51, + n_0_0_46, n_0_50, n_0_0_47, n_0_0_48, n_0_0_49, n_0_0_50, n_0_0_51, + n_0_49, n_0_0_52, n_0_48, n_0_0_53, n_0_47, n_0_0_54, n_0_46, n_0_0_55, + n_0_45, n_0_0_56, n_0_44, n_0_0_57, n_0_66, n_0_0_58, n_0_67, n_0_0_59, + n_0_0_60, n_0_0_61, n_0_68, n_0_0_62, n_0_0_63, n_0_69, n_0_0_64, + n_0_0_65, n_0_70, n_0_0_66, n_0_0_67, n_0_71, n_0_0_68, n_0_0_69, + n_0_72, n_0_0_70, n_0_0_71, n_0_73, n_0_0_72, n_0_0_73, n_0_74, + n_0_0_74, n_0_0_75, n_0_75, n_0_0_76, n_0_0_77, n_0_0_78, n_0_0_79, + n_0_0_80, n_0_0_81, n_0_0_82, n_0_0_83, n_0_0_84, n_0_0_85, n_0_0_86, + n_0_0_87, n_0_0_88, n_0_0_89, n_0_0_90, n_0_0_91, n_0_0_92, n_0_43, + n_0_0_93, n_0_0_94, n_0_76, n_0_0_95, n_0; + + INV_X1_LVT i_0_0_171( + .A(DWE), .ZN(n_0) + ); + NOR2_X1_LVT i_0_0_163( + .A1(n_0), .A2(reset), .ZN(n_0_0_88) + ); + NOR2_X1_LVT i_0_0_22( + .A1(DWE), .A2(reset), .ZN(n_0_0_11) + ); + AOI22_X1_LVT i_0_0_21( + .A1(DAddr[12]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[12]), .ZN(n_0_0_10) + ); + INV_X1_LVT i_0_0_20( + .A(n_0_0_10), .ZN(n_0_10) + ); + INV_X1_LVT i_0_0_172( + .A(clk), .ZN(n_0_76) + ); + DFF_X1_LVT \mem_addr_reg[10] ( + .CK(n_0_76), .D(n_0_10), .Q(mem_addr[10]), .QN() + ); + AOI22_X1_LVT i_0_0_19( + .A1(DAddr[11]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[11]), .ZN(n_0_0_9) + ); + INV_X1_LVT i_0_0_18( + .A(n_0_0_9), .ZN(n_0_9) + ); + DFF_X1_LVT \mem_addr_reg[9] ( + .CK(n_0_76), .D(n_0_9), .Q(mem_addr[9]), .QN() + ); + AOI22_X1_LVT i_0_0_17( + .A1(DAddr[10]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[10]), .ZN(n_0_0_8) + ); + INV_X1_LVT i_0_0_16( + .A(n_0_0_8), .ZN(n_0_8) + ); + DFF_X1_LVT \mem_addr_reg[8] ( + .CK(n_0_76), .D(n_0_8), .Q(mem_addr[8]), .QN() + ); + AOI22_X1_LVT i_0_0_15( + .A1(DAddr[9]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[9]), .ZN(n_0_0_7) + ); + INV_X1_LVT i_0_0_14( + .A(n_0_0_7), .ZN(n_0_7) + ); + DFF_X1_LVT \mem_addr_reg[7] ( + .CK(n_0_76), .D(n_0_7), .Q(mem_addr[7]), .QN() + ); + AOI22_X1_LVT i_0_0_13( + .A1(DAddr[8]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[8]), .ZN(n_0_0_6) + ); + INV_X1_LVT i_0_0_12( + .A(n_0_0_6), .ZN(n_0_6) + ); + DFF_X1_LVT \mem_addr_reg[6] ( + .CK(n_0_76), .D(n_0_6), .Q(mem_addr[6]), .QN() + ); + AOI22_X1_LVT i_0_0_11( + .A1(DAddr[7]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[7]), .ZN(n_0_0_5) + ); + INV_X1_LVT i_0_0_10( + .A(n_0_0_5), .ZN(n_0_5) + ); + DFF_X1_LVT \mem_addr_reg[5] ( + .CK(n_0_76), .D(n_0_5), .Q(mem_addr[5]), .QN() + ); + AOI22_X1_LVT i_0_0_9( + .A1(DAddr[6]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[6]), .ZN(n_0_0_4) + ); + INV_X1_LVT i_0_0_8( + .A(n_0_0_4), .ZN(n_0_4) + ); + DFF_X1_LVT \mem_addr_reg[4] ( + .CK(n_0_76), .D(n_0_4), .Q(mem_addr[4]), .QN() + ); + AOI22_X1_LVT i_0_0_7( + .A1(DAddr[5]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[5]), .ZN(n_0_0_3) + ); + INV_X1_LVT i_0_0_6( + .A(n_0_0_3), .ZN(n_0_3) + ); + DFF_X1_LVT \mem_addr_reg[3] ( + .CK(n_0_76), .D(n_0_3), .Q(mem_addr[3]), .QN() + ); + AOI22_X1_LVT i_0_0_5( + .A1(DAddr[4]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[4]), .ZN(n_0_0_2) + ); + INV_X1_LVT i_0_0_4( + .A(n_0_0_2), .ZN(n_0_2) + ); + DFF_X1_LVT \mem_addr_reg[2] ( + .CK(n_0_76), .D(n_0_2), .Q(mem_addr[2]), .QN() + ); + AOI22_X1_LVT i_0_0_3( + .A1(DAddr[3]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[3]), .ZN(n_0_0_1) + ); + INV_X1_LVT i_0_0_2( + .A(n_0_0_1), .ZN(n_0_1) + ); + DFF_X1_LVT \mem_addr_reg[1] ( + .CK(n_0_76), .D(n_0_1), .Q(mem_addr[1]), .QN() + ); + AOI22_X1_LVT i_0_0_1( + .A1(DAddr[2]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[2]), .ZN(n_0_0_0) + ); + INV_X1_LVT i_0_0_0( + .A(n_0_0_0), .ZN(n_0_0) + ); + DFF_X1_LVT \mem_addr_reg[0] ( + .CK(n_0_76), .D(n_0_0), .Q(mem_addr[0]), .QN() + ); + NOR2_X1_LVT i_0_0_162( + .A1(DWidth[1]), .A2(DAddr[1]), .ZN(n_0_0_87) + ); + NOR2_X1_LVT i_0_0_158( + .A1(DWidth[0]), .A2(DAddr[0]), .ZN(n_0_0_83) + ); + AND2_X1_LVT i_0_0_157( + .A1(n_0_0_87), .A2(n_0_0_83), .ZN(n_0_0_82) + ); + AND2_X1_LVT i_0_0_156( + .A1(n_0_0_88), .A2(n_0_0_82), .ZN(n_0_0_81) + ); + INV_X1_LVT i_0_0_173( + .A(n_0_0_88), .ZN(n_0_0_95) + ); + INV_X1_LVT i_0_0_169( + .A(DWidth[1]), .ZN(n_0_0_93) + ); + NOR3_X1_LVT i_0_0_155( + .A1(n_0_0_95), .A2(DWidth[0]), .A3(n_0_0_93), .ZN(n_0_0_80) + ); + AOI22_X1_LVT i_0_0_154( + .A1(DWData[7]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[31]), .ZN(n_0_0_79) + ); + NAND2_X1_LVT i_0_0_168( + .A1(DWidth[0]), .A2(DWidth[1]), .ZN(n_0_43) + ); + INV_X1_LVT i_0_0_167( + .A(n_0_43), .ZN(n_0_0_92) + ); + NOR2_X1_LVT i_0_0_160( + .A1(n_0_0_95), .A2(n_0_0_92), .ZN(n_0_0_85) + ); + NAND2_X1_LVT i_0_0_161( + .A1(n_0_0_93), .A2(DAddr[1]), .ZN(n_0_0_86) + ); + NOR2_X1_LVT i_0_0_166( + .A1(DWidth[0]), .A2(DWidth[1]), .ZN(n_0_0_91) + ); + NAND2_X1_LVT i_0_0_164( + .A1(DAddr[0]), .A2(n_0_0_91), .ZN(n_0_0_89) + ); + NAND3_X1_LVT i_0_0_159( + .A1(n_0_0_85), .A2(n_0_0_86), .A3(n_0_0_89), .ZN(n_0_0_84) + ); + INV_X1_LVT i_0_0_170( + .A(DWidth[0]), .ZN(n_0_0_94) + ); + NOR2_X1_LVT i_0_0_153( + .A1(n_0_0_94), .A2(DAddr[1]), .ZN(n_0_0_78) + ); + AND3_X1_LVT i_0_0_152( + .A1(n_0_0_88), .A2(n_0_0_78), .A3(n_0_0_93), .ZN(n_0_0_77) + ); + AOI22_X1_LVT i_0_0_151( + .A1(n_0_0_84), .A2(mem_wdata[31]), .B1(DWData[15]), .B2(n_0_0_77), .ZN(n_0_0_76) + ); + NAND2_X1_LVT i_0_0_150( + .A1(n_0_0_79), .A2(n_0_0_76), .ZN(n_0_75) + ); + DFF_X1_LVT \mem_wdata_reg[31] ( + .CK(n_0_76), .D(n_0_75), .Q(mem_wdata[31]), .QN() + ); + AOI22_X1_LVT i_0_0_149( + .A1(DWData[6]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[30]), .ZN(n_0_0_75) + ); + AOI22_X1_LVT i_0_0_148( + .A1(n_0_0_84), .A2(mem_wdata[30]), .B1(DWData[14]), .B2(n_0_0_77), .ZN(n_0_0_74) + ); + NAND2_X1_LVT i_0_0_147( + .A1(n_0_0_75), .A2(n_0_0_74), .ZN(n_0_74) + ); + DFF_X1_LVT \mem_wdata_reg[30] ( + .CK(n_0_76), .D(n_0_74), .Q(mem_wdata[30]), .QN() + ); + AOI22_X1_LVT i_0_0_146( + .A1(DWData[5]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[29]), .ZN(n_0_0_73) + ); + AOI22_X1_LVT i_0_0_145( + .A1(n_0_0_84), .A2(mem_wdata[29]), .B1(DWData[13]), .B2(n_0_0_77), .ZN(n_0_0_72) + ); + NAND2_X1_LVT i_0_0_144( + .A1(n_0_0_73), .A2(n_0_0_72), .ZN(n_0_73) + ); + DFF_X1_LVT \mem_wdata_reg[29] ( + .CK(n_0_76), .D(n_0_73), .Q(mem_wdata[29]), .QN() + ); + AOI22_X1_LVT i_0_0_143( + .A1(DWData[4]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[28]), .ZN(n_0_0_71) + ); + AOI22_X1_LVT i_0_0_142( + .A1(n_0_0_84), .A2(mem_wdata[28]), .B1(DWData[12]), .B2(n_0_0_77), .ZN(n_0_0_70) + ); + NAND2_X1_LVT i_0_0_141( + .A1(n_0_0_71), .A2(n_0_0_70), .ZN(n_0_72) + ); + DFF_X1_LVT \mem_wdata_reg[28] ( + .CK(n_0_76), .D(n_0_72), .Q(mem_wdata[28]), .QN() + ); + AOI22_X1_LVT i_0_0_140( + .A1(DWData[3]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[27]), .ZN(n_0_0_69) + ); + AOI22_X1_LVT i_0_0_139( + .A1(n_0_0_84), .A2(mem_wdata[27]), .B1(DWData[11]), .B2(n_0_0_77), .ZN(n_0_0_68) + ); + NAND2_X1_LVT i_0_0_138( + .A1(n_0_0_69), .A2(n_0_0_68), .ZN(n_0_71) + ); + DFF_X1_LVT \mem_wdata_reg[27] ( + .CK(n_0_76), .D(n_0_71), .Q(mem_wdata[27]), .QN() + ); + AOI22_X1_LVT i_0_0_137( + .A1(DWData[2]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[26]), .ZN(n_0_0_67) + ); + AOI22_X1_LVT i_0_0_136( + .A1(n_0_0_84), .A2(mem_wdata[26]), .B1(DWData[10]), .B2(n_0_0_77), .ZN(n_0_0_66) + ); + NAND2_X1_LVT i_0_0_135( + .A1(n_0_0_67), .A2(n_0_0_66), .ZN(n_0_70) + ); + DFF_X1_LVT \mem_wdata_reg[26] ( + .CK(n_0_76), .D(n_0_70), .Q(mem_wdata[26]), .QN() + ); + AOI22_X1_LVT i_0_0_134( + .A1(DWData[1]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[25]), .ZN(n_0_0_65) + ); + AOI22_X1_LVT i_0_0_133( + .A1(n_0_0_84), .A2(mem_wdata[25]), .B1(DWData[9]), .B2(n_0_0_77), .ZN(n_0_0_64) + ); + NAND2_X1_LVT i_0_0_132( + .A1(n_0_0_65), .A2(n_0_0_64), .ZN(n_0_69) + ); + DFF_X1_LVT \mem_wdata_reg[25] ( + .CK(n_0_76), .D(n_0_69), .Q(mem_wdata[25]), .QN() + ); + AOI22_X1_LVT i_0_0_131( + .A1(DWData[0]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[24]), .ZN(n_0_0_63) + ); + AOI22_X1_LVT i_0_0_130( + .A1(n_0_0_84), .A2(mem_wdata[24]), .B1(DWData[8]), .B2(n_0_0_77), .ZN(n_0_0_62) + ); + NAND2_X1_LVT i_0_0_129( + .A1(n_0_0_63), .A2(n_0_0_62), .ZN(n_0_68) + ); + DFF_X1_LVT \mem_wdata_reg[24] ( + .CK(n_0_76), .D(n_0_68), .Q(mem_wdata[24]), .QN() + ); + NOR4_X1_LVT i_0_0_127( + .A1(n_0_0_95), .A2(n_0_0_83), .A3(DWidth[1]), .A4(DAddr[1]), .ZN(n_0_0_60) + ); + INV_X1_LVT i_0_0_165( + .A(n_0_0_91), .ZN(n_0_0_90) + ); + OAI211_X1_LVT i_0_0_128( + .A(n_0_0_85), .B(n_0_0_86), .C1(n_0_0_90), .C2(DAddr[0]), .ZN(n_0_0_61) + ); + AOI222_X1_LVT i_0_0_126( + .A1(DWData[7]), .A2(n_0_0_60), .B1(mem_wdata[23]), .B2(n_0_0_61), .C1(DWData[23]), + .C2(n_0_0_80), .ZN(n_0_0_59) + ); + INV_X1_LVT i_0_0_125( + .A(n_0_0_59), .ZN(n_0_67) + ); + DFF_X1_LVT \mem_wdata_reg[23] ( + .CK(n_0_76), .D(n_0_67), .Q(mem_wdata[23]), .QN() + ); + AOI222_X1_LVT i_0_0_124( + .A1(DWData[6]), .A2(n_0_0_60), .B1(mem_wdata[22]), .B2(n_0_0_61), .C1(DWData[22]), + .C2(n_0_0_80), .ZN(n_0_0_58) + ); + INV_X1_LVT i_0_0_123( + .A(n_0_0_58), .ZN(n_0_66) + ); + DFF_X1_LVT \mem_wdata_reg[22] ( + .CK(n_0_76), .D(n_0_66), .Q(mem_wdata[22]), .QN() + ); + AOI222_X1_LVT i_0_0_122( + .A1(DWData[5]), .A2(n_0_0_60), .B1(mem_wdata[21]), .B2(n_0_0_61), .C1(DWData[21]), + .C2(n_0_0_80), .ZN(n_0_0_57) + ); + INV_X1_LVT i_0_0_121( + .A(n_0_0_57), .ZN(n_0_44) + ); + DFF_X1_LVT \mem_wdata_reg[21] ( + .CK(n_0_76), .D(n_0_44), .Q(mem_wdata[21]), .QN() + ); + AOI222_X1_LVT i_0_0_120( + .A1(DWData[4]), .A2(n_0_0_60), .B1(mem_wdata[20]), .B2(n_0_0_61), .C1(DWData[20]), + .C2(n_0_0_80), .ZN(n_0_0_56) + ); + INV_X1_LVT i_0_0_119( + .A(n_0_0_56), .ZN(n_0_45) + ); + DFF_X1_LVT \mem_wdata_reg[20] ( + .CK(n_0_76), .D(n_0_45), .Q(mem_wdata[20]), .QN() + ); + AOI222_X1_LVT i_0_0_118( + .A1(DWData[3]), .A2(n_0_0_60), .B1(mem_wdata[19]), .B2(n_0_0_61), .C1(DWData[19]), + .C2(n_0_0_80), .ZN(n_0_0_55) + ); + INV_X1_LVT i_0_0_117( + .A(n_0_0_55), .ZN(n_0_46) + ); + DFF_X1_LVT \mem_wdata_reg[19] ( + .CK(n_0_76), .D(n_0_46), .Q(mem_wdata[19]), .QN() + ); + AOI222_X1_LVT i_0_0_116( + .A1(DWData[2]), .A2(n_0_0_60), .B1(mem_wdata[18]), .B2(n_0_0_61), .C1(DWData[18]), + .C2(n_0_0_80), .ZN(n_0_0_54) + ); + INV_X1_LVT i_0_0_115( + .A(n_0_0_54), .ZN(n_0_47) + ); + DFF_X1_LVT \mem_wdata_reg[18] ( + .CK(n_0_76), .D(n_0_47), .Q(mem_wdata[18]), .QN() + ); + AOI222_X1_LVT i_0_0_114( + .A1(DWData[1]), .A2(n_0_0_60), .B1(mem_wdata[17]), .B2(n_0_0_61), .C1(DWData[17]), + .C2(n_0_0_80), .ZN(n_0_0_53) + ); + INV_X1_LVT i_0_0_113( + .A(n_0_0_53), .ZN(n_0_48) + ); + DFF_X1_LVT \mem_wdata_reg[17] ( + .CK(n_0_76), .D(n_0_48), .Q(mem_wdata[17]), .QN() + ); + AOI222_X1_LVT i_0_0_112( + .A1(DWData[0]), .A2(n_0_0_60), .B1(mem_wdata[16]), .B2(n_0_0_61), .C1(DWData[16]), + .C2(n_0_0_80), .ZN(n_0_0_52) + ); + INV_X1_LVT i_0_0_111( + .A(n_0_0_52), .ZN(n_0_49) + ); + DFF_X1_LVT \mem_wdata_reg[16] ( + .CK(n_0_76), .D(n_0_49), .Q(mem_wdata[16]), .QN() + ); + NOR4_X1_LVT i_0_0_110( + .A1(n_0_0_95), .A2(n_0_0_87), .A3(n_0_0_92), .A4(n_0_0_91), .ZN(n_0_0_51) + ); + NOR3_X1_LVT i_0_0_109( + .A1(n_0_0_86), .A2(DAddr[0]), .A3(DWidth[0]), .ZN(n_0_0_50) + ); + AND2_X1_LVT i_0_0_108( + .A1(n_0_0_88), .A2(n_0_0_50), .ZN(n_0_0_49) + ); + OAI211_X1_LVT i_0_0_107( + .A(n_0_0_85), .B(n_0_0_89), .C1(DAddr[1]), .C2(DWidth[1]), .ZN(n_0_0_48) + ); + AOI222_X1_LVT i_0_0_106( + .A1(DWData[15]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[7]), .C1(n_0_0_48), + .C2(mem_wdata[15]), .ZN(n_0_0_47) + ); + INV_X1_LVT i_0_0_105( + .A(n_0_0_47), .ZN(n_0_50) + ); + DFF_X1_LVT \mem_wdata_reg[15] ( + .CK(n_0_76), .D(n_0_50), .Q(mem_wdata[15]), .QN() + ); + AOI222_X1_LVT i_0_0_104( + .A1(DWData[14]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[6]), .C1(n_0_0_48), + .C2(mem_wdata[14]), .ZN(n_0_0_46) + ); + INV_X1_LVT i_0_0_103( + .A(n_0_0_46), .ZN(n_0_51) + ); + DFF_X1_LVT \mem_wdata_reg[14] ( + .CK(n_0_76), .D(n_0_51), .Q(mem_wdata[14]), .QN() + ); + AOI222_X1_LVT i_0_0_102( + .A1(DWData[13]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[5]), .C1(n_0_0_48), + .C2(mem_wdata[13]), .ZN(n_0_0_45) + ); + INV_X1_LVT i_0_0_101( + .A(n_0_0_45), .ZN(n_0_52) + ); + DFF_X1_LVT \mem_wdata_reg[13] ( + .CK(n_0_76), .D(n_0_52), .Q(mem_wdata[13]), .QN() + ); + AOI222_X1_LVT i_0_0_100( + .A1(DWData[12]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[4]), .C1(n_0_0_48), + .C2(mem_wdata[12]), .ZN(n_0_0_44) + ); + INV_X1_LVT i_0_0_99( + .A(n_0_0_44), .ZN(n_0_53) + ); + DFF_X1_LVT \mem_wdata_reg[12] ( + .CK(n_0_76), .D(n_0_53), .Q(mem_wdata[12]), .QN() + ); + AOI222_X1_LVT i_0_0_98( + .A1(DWData[11]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[3]), .C1(n_0_0_48), + .C2(mem_wdata[11]), .ZN(n_0_0_43) + ); + INV_X1_LVT i_0_0_97( + .A(n_0_0_43), .ZN(n_0_54) + ); + DFF_X1_LVT \mem_wdata_reg[11] ( + .CK(n_0_76), .D(n_0_54), .Q(mem_wdata[11]), .QN() + ); + AOI222_X1_LVT i_0_0_96( + .A1(DWData[10]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[2]), .C1(n_0_0_48), + .C2(mem_wdata[10]), .ZN(n_0_0_42) + ); + INV_X1_LVT i_0_0_95( + .A(n_0_0_42), .ZN(n_0_55) + ); + DFF_X1_LVT \mem_wdata_reg[10] ( + .CK(n_0_76), .D(n_0_55), .Q(mem_wdata[10]), .QN() + ); + AOI222_X1_LVT i_0_0_94( + .A1(DWData[9]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[1]), .C1(n_0_0_48), + .C2(mem_wdata[9]), .ZN(n_0_0_41) + ); + INV_X1_LVT i_0_0_93( + .A(n_0_0_41), .ZN(n_0_56) + ); + DFF_X1_LVT \mem_wdata_reg[9] ( + .CK(n_0_76), .D(n_0_56), .Q(mem_wdata[9]), .QN() + ); + AOI222_X1_LVT i_0_0_92( + .A1(DWData[8]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[0]), .C1(n_0_0_48), + .C2(mem_wdata[8]), .ZN(n_0_0_40) + ); + INV_X1_LVT i_0_0_91( + .A(n_0_0_40), .ZN(n_0_57) + ); + DFF_X1_LVT \mem_wdata_reg[8] ( + .CK(n_0_76), .D(n_0_57), .Q(mem_wdata[8]), .QN() + ); + AOI21_X1_LVT i_0_0_90( + .A(n_0_0_87), .B1(n_0_0_83), .B2(n_0_0_93), .ZN(n_0_0_39) + ); + NAND2_X1_LVT i_0_0_89( + .A1(n_0_0_85), .A2(n_0_0_39), .ZN(n_0_0_38) + ); + MUX2_X1_LVT i_0_0_88( + .A(DWData[7]), .B(mem_wdata[7]), .S(n_0_0_38), .Z(n_0_58) + ); + DFF_X1_LVT \mem_wdata_reg[7] ( + .CK(n_0_76), .D(n_0_58), .Q(mem_wdata[7]), .QN() + ); + MUX2_X1_LVT i_0_0_87( + .A(DWData[6]), .B(mem_wdata[6]), .S(n_0_0_38), .Z(n_0_59) + ); + DFF_X1_LVT \mem_wdata_reg[6] ( + .CK(n_0_76), .D(n_0_59), .Q(mem_wdata[6]), .QN() + ); + MUX2_X1_LVT i_0_0_86( + .A(DWData[5]), .B(mem_wdata[5]), .S(n_0_0_38), .Z(n_0_60) + ); + DFF_X1_LVT \mem_wdata_reg[5] ( + .CK(n_0_76), .D(n_0_60), .Q(mem_wdata[5]), .QN() + ); + MUX2_X1_LVT i_0_0_85( + .A(DWData[4]), .B(mem_wdata[4]), .S(n_0_0_38), .Z(n_0_61) + ); + DFF_X1_LVT \mem_wdata_reg[4] ( + .CK(n_0_76), .D(n_0_61), .Q(mem_wdata[4]), .QN() + ); + MUX2_X1_LVT i_0_0_84( + .A(DWData[3]), .B(mem_wdata[3]), .S(n_0_0_38), .Z(n_0_62) + ); + DFF_X1_LVT \mem_wdata_reg[3] ( + .CK(n_0_76), .D(n_0_62), .Q(mem_wdata[3]), .QN() + ); + MUX2_X1_LVT i_0_0_83( + .A(DWData[2]), .B(mem_wdata[2]), .S(n_0_0_38), .Z(n_0_63) + ); + DFF_X1_LVT \mem_wdata_reg[2] ( + .CK(n_0_76), .D(n_0_63), .Q(mem_wdata[2]), .QN() + ); + MUX2_X1_LVT i_0_0_82( + .A(DWData[1]), .B(mem_wdata[1]), .S(n_0_0_38), .Z(n_0_64) + ); + DFF_X1_LVT \mem_wdata_reg[1] ( + .CK(n_0_76), .D(n_0_64), .Q(mem_wdata[1]), .QN() + ); + MUX2_X1_LVT i_0_0_81( + .A(DWData[0]), .B(mem_wdata[0]), .S(n_0_0_38), .Z(n_0_65) + ); + DFF_X1_LVT \mem_wdata_reg[0] ( + .CK(n_0_76), .D(n_0_65), .Q(mem_wdata[0]), .QN() + ); + MemGen_32_11 RAM( + .chip_en(), .clock(clk), .addr(mem_addr), .rd_data(mem_rdata), .rd_en(n_0), + .wr_en(DWE), .wr_data(mem_wdata) + ); + DFF_X1_LVT \drTmp_reg[31] ( + .CK(n_0_76), .D(mem_rdata[31]), .Q(drTmp[31]), .QN() + ); + AND2_X1_LVT i_0_0_80( + .A1(DWidth[1]), .A2(drTmp[31]), .ZN(n_0_42) + ); + DLH_X1_LVT \DRData[31] ( + .D(n_0_42), .G(n_0_43), .Q(DRData[31]) + ); + DFF_X1_LVT \drTmp_reg[30] ( + .CK(n_0_76), .D(mem_rdata[30]), .Q(drTmp[30]), .QN() + ); + AND2_X1_LVT i_0_0_79( + .A1(DWidth[1]), .A2(drTmp[30]), .ZN(n_0_41) + ); + DLH_X1_LVT \DRData[30] ( + .D(n_0_41), .G(n_0_43), .Q(DRData[30]) + ); + DFF_X1_LVT \drTmp_reg[29] ( + .CK(n_0_76), .D(mem_rdata[29]), .Q(drTmp[29]), .QN() + ); + AND2_X1_LVT i_0_0_78( + .A1(DWidth[1]), .A2(drTmp[29]), .ZN(n_0_40) + ); + DLH_X1_LVT \DRData[29] ( + .D(n_0_40), .G(n_0_43), .Q(DRData[29]) + ); + DFF_X1_LVT \drTmp_reg[28] ( + .CK(n_0_76), .D(mem_rdata[28]), .Q(drTmp[28]), .QN() + ); + AND2_X1_LVT i_0_0_77( + .A1(DWidth[1]), .A2(drTmp[28]), .ZN(n_0_39) + ); + DLH_X1_LVT \DRData[28] ( + .D(n_0_39), .G(n_0_43), .Q(DRData[28]) + ); + DFF_X1_LVT \drTmp_reg[27] ( + .CK(n_0_76), .D(mem_rdata[27]), .Q(drTmp[27]), .QN() + ); + AND2_X1_LVT i_0_0_76( + .A1(DWidth[1]), .A2(drTmp[27]), .ZN(n_0_38) + ); + DLH_X1_LVT \DRData[27] ( + .D(n_0_38), .G(n_0_43), .Q(DRData[27]) + ); + DFF_X1_LVT \drTmp_reg[26] ( + .CK(n_0_76), .D(mem_rdata[26]), .Q(drTmp[26]), .QN() + ); + AND2_X1_LVT i_0_0_75( + .A1(DWidth[1]), .A2(drTmp[26]), .ZN(n_0_37) + ); + DLH_X1_LVT \DRData[26] ( + .D(n_0_37), .G(n_0_43), .Q(DRData[26]) + ); + DFF_X1_LVT \drTmp_reg[25] ( + .CK(n_0_76), .D(mem_rdata[25]), .Q(drTmp[25]), .QN() + ); + AND2_X1_LVT i_0_0_74( + .A1(DWidth[1]), .A2(drTmp[25]), .ZN(n_0_36) + ); + DLH_X1_LVT \DRData[25] ( + .D(n_0_36), .G(n_0_43), .Q(DRData[25]) + ); + DFF_X1_LVT \drTmp_reg[24] ( + .CK(n_0_76), .D(mem_rdata[24]), .Q(drTmp[24]), .QN() + ); + AND2_X1_LVT i_0_0_73( + .A1(DWidth[1]), .A2(drTmp[24]), .ZN(n_0_35) + ); + DLH_X1_LVT \DRData[24] ( + .D(n_0_35), .G(n_0_43), .Q(DRData[24]) + ); + DFF_X1_LVT \drTmp_reg[23] ( + .CK(n_0_76), .D(mem_rdata[23]), .Q(drTmp[23]), .QN() + ); + AND2_X1_LVT i_0_0_72( + .A1(DWidth[1]), .A2(drTmp[23]), .ZN(n_0_34) + ); + DLH_X1_LVT \DRData[23] ( + .D(n_0_34), .G(n_0_43), .Q(DRData[23]) + ); + DFF_X1_LVT \drTmp_reg[22] ( + .CK(n_0_76), .D(mem_rdata[22]), .Q(drTmp[22]), .QN() + ); + AND2_X1_LVT i_0_0_71( + .A1(DWidth[1]), .A2(drTmp[22]), .ZN(n_0_33) + ); + DLH_X1_LVT \DRData[22] ( + .D(n_0_33), .G(n_0_43), .Q(DRData[22]) + ); + DFF_X1_LVT \drTmp_reg[21] ( + .CK(n_0_76), .D(mem_rdata[21]), .Q(drTmp[21]), .QN() + ); + AND2_X1_LVT i_0_0_70( + .A1(DWidth[1]), .A2(drTmp[21]), .ZN(n_0_32) + ); + DLH_X1_LVT \DRData[21] ( + .D(n_0_32), .G(n_0_43), .Q(DRData[21]) + ); + DFF_X1_LVT \drTmp_reg[20] ( + .CK(n_0_76), .D(mem_rdata[20]), .Q(drTmp[20]), .QN() + ); + AND2_X1_LVT i_0_0_69( + .A1(DWidth[1]), .A2(drTmp[20]), .ZN(n_0_31) + ); + DLH_X1_LVT \DRData[20] ( + .D(n_0_31), .G(n_0_43), .Q(DRData[20]) + ); + DFF_X1_LVT \drTmp_reg[19] ( + .CK(n_0_76), .D(mem_rdata[19]), .Q(drTmp[19]), .QN() + ); + AND2_X1_LVT i_0_0_68( + .A1(DWidth[1]), .A2(drTmp[19]), .ZN(n_0_30) + ); + DLH_X1_LVT \DRData[19] ( + .D(n_0_30), .G(n_0_43), .Q(DRData[19]) + ); + DFF_X1_LVT \drTmp_reg[18] ( + .CK(n_0_76), .D(mem_rdata[18]), .Q(drTmp[18]), .QN() + ); + AND2_X1_LVT i_0_0_67( + .A1(DWidth[1]), .A2(drTmp[18]), .ZN(n_0_29) + ); + DLH_X1_LVT \DRData[18] ( + .D(n_0_29), .G(n_0_43), .Q(DRData[18]) + ); + DFF_X1_LVT \drTmp_reg[17] ( + .CK(n_0_76), .D(mem_rdata[17]), .Q(drTmp[17]), .QN() + ); + AND2_X1_LVT i_0_0_66( + .A1(DWidth[1]), .A2(drTmp[17]), .ZN(n_0_28) + ); + DLH_X1_LVT \DRData[17] ( + .D(n_0_28), .G(n_0_43), .Q(DRData[17]) + ); + DFF_X1_LVT \drTmp_reg[16] ( + .CK(n_0_76), .D(mem_rdata[16]), .Q(drTmp[16]), .QN() + ); + AND2_X1_LVT i_0_0_65( + .A1(DWidth[1]), .A2(drTmp[16]), .ZN(n_0_27) + ); + DLH_X1_LVT \DRData[16] ( + .D(n_0_27), .G(n_0_43), .Q(DRData[16]) + ); + NOR2_X1_LVT i_0_0_64( + .A1(n_0_0_91), .A2(n_0_0_87), .ZN(n_0_0_37) + ); + DFF_X1_LVT \drTmp_reg[15] ( + .CK(n_0_76), .D(mem_rdata[15]), .Q(drTmp[15]), .QN() + ); + AOI22_X1_LVT i_0_0_63( + .A1(drTmp[31]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[15]), .ZN(n_0_0_36) + ); + INV_X1_LVT i_0_0_62( + .A(n_0_0_36), .ZN(n_0_26) + ); + DLH_X1_LVT \DRData[15] ( + .D(n_0_26), .G(n_0_43), .Q(DRData[15]) + ); + DFF_X1_LVT \drTmp_reg[14] ( + .CK(n_0_76), .D(mem_rdata[14]), .Q(drTmp[14]), .QN() + ); + AOI22_X1_LVT i_0_0_61( + .A1(drTmp[30]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[14]), .ZN(n_0_0_35) + ); + INV_X1_LVT i_0_0_60( + .A(n_0_0_35), .ZN(n_0_25) + ); + DLH_X1_LVT \DRData[14] ( + .D(n_0_25), .G(n_0_43), .Q(DRData[14]) + ); + DFF_X1_LVT \drTmp_reg[13] ( + .CK(n_0_76), .D(mem_rdata[13]), .Q(drTmp[13]), .QN() + ); + AOI22_X1_LVT i_0_0_59( + .A1(drTmp[29]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[13]), .ZN(n_0_0_34) + ); + INV_X1_LVT i_0_0_58( + .A(n_0_0_34), .ZN(n_0_24) + ); + DLH_X1_LVT \DRData[13] ( + .D(n_0_24), .G(n_0_43), .Q(DRData[13]) + ); + DFF_X1_LVT \drTmp_reg[12] ( + .CK(n_0_76), .D(mem_rdata[12]), .Q(drTmp[12]), .QN() + ); + AOI22_X1_LVT i_0_0_57( + .A1(drTmp[28]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[12]), .ZN(n_0_0_33) + ); + INV_X1_LVT i_0_0_56( + .A(n_0_0_33), .ZN(n_0_23) + ); + DLH_X1_LVT \DRData[12] ( + .D(n_0_23), .G(n_0_43), .Q(DRData[12]) + ); + DFF_X1_LVT \drTmp_reg[11] ( + .CK(n_0_76), .D(mem_rdata[11]), .Q(drTmp[11]), .QN() + ); + AOI22_X1_LVT i_0_0_55( + .A1(drTmp[27]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[11]), .ZN(n_0_0_32) + ); + INV_X1_LVT i_0_0_54( + .A(n_0_0_32), .ZN(n_0_22) + ); + DLH_X1_LVT \DRData[11] ( + .D(n_0_22), .G(n_0_43), .Q(DRData[11]) + ); + DFF_X1_LVT \drTmp_reg[10] ( + .CK(n_0_76), .D(mem_rdata[10]), .Q(drTmp[10]), .QN() + ); + AOI22_X1_LVT i_0_0_53( + .A1(drTmp[26]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[10]), .ZN(n_0_0_31) + ); + INV_X1_LVT i_0_0_52( + .A(n_0_0_31), .ZN(n_0_21) + ); + DLH_X1_LVT \DRData[10] ( + .D(n_0_21), .G(n_0_43), .Q(DRData[10]) + ); + DFF_X1_LVT \drTmp_reg[9] ( + .CK(n_0_76), .D(mem_rdata[9]), .Q(drTmp[9]), .QN() + ); + AOI22_X1_LVT i_0_0_51( + .A1(drTmp[25]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[9]), .ZN(n_0_0_30) + ); + INV_X1_LVT i_0_0_50( + .A(n_0_0_30), .ZN(n_0_20) + ); + DLH_X1_LVT \DRData[9] ( + .D(n_0_20), .G(n_0_43), .Q(DRData[9]) + ); + DFF_X1_LVT \drTmp_reg[8] ( + .CK(n_0_76), .D(mem_rdata[8]), .Q(drTmp[8]), .QN() + ); + AOI22_X1_LVT i_0_0_49( + .A1(drTmp[24]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[8]), .ZN(n_0_0_29) + ); + INV_X1_LVT i_0_0_48( + .A(n_0_0_29), .ZN(n_0_19) + ); + DLH_X1_LVT \DRData[8] ( + .D(n_0_19), .G(n_0_43), .Q(DRData[8]) + ); + AOI22_X1_LVT i_0_0_46( + .A1(drTmp[31]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[15]), .ZN(n_0_0_27) + ); + AOI211_X1_LVT i_0_0_47( + .A(DAddr[1]), .B(n_0_0_83), .C1(n_0_0_94), .C2(DWidth[1]), .ZN(n_0_0_28) + ); + DFF_X1_LVT \drTmp_reg[7] ( + .CK(n_0_76), .D(mem_rdata[7]), .Q(drTmp[7]), .QN() + ); + AOI22_X1_LVT i_0_0_45( + .A1(drTmp[23]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[7]), .ZN(n_0_0_26) + ); + NAND2_X1_LVT i_0_0_44( + .A1(n_0_0_27), .A2(n_0_0_26), .ZN(n_0_18) + ); + DLH_X1_LVT \DRData[7] ( + .D(n_0_18), .G(n_0_43), .Q(DRData[7]) + ); + AOI22_X1_LVT i_0_0_43( + .A1(drTmp[30]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[14]), .ZN(n_0_0_25) + ); + DFF_X1_LVT \drTmp_reg[6] ( + .CK(n_0_76), .D(mem_rdata[6]), .Q(drTmp[6]), .QN() + ); + AOI22_X1_LVT i_0_0_42( + .A1(drTmp[22]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[6]), .ZN(n_0_0_24) + ); + NAND2_X1_LVT i_0_0_41( + .A1(n_0_0_25), .A2(n_0_0_24), .ZN(n_0_17) + ); + DLH_X1_LVT \DRData[6] ( + .D(n_0_17), .G(n_0_43), .Q(DRData[6]) + ); + AOI22_X1_LVT i_0_0_40( + .A1(drTmp[29]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[13]), .ZN(n_0_0_23) + ); + DFF_X1_LVT \drTmp_reg[5] ( + .CK(n_0_76), .D(mem_rdata[5]), .Q(drTmp[5]), .QN() + ); + AOI22_X1_LVT i_0_0_39( + .A1(drTmp[21]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[5]), .ZN(n_0_0_22) + ); + NAND2_X1_LVT i_0_0_38( + .A1(n_0_0_23), .A2(n_0_0_22), .ZN(n_0_16) + ); + DLH_X1_LVT \DRData[5] ( + .D(n_0_16), .G(n_0_43), .Q(DRData[5]) + ); + AOI22_X1_LVT i_0_0_37( + .A1(drTmp[28]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[12]), .ZN(n_0_0_21) + ); + DFF_X1_LVT \drTmp_reg[4] ( + .CK(n_0_76), .D(mem_rdata[4]), .Q(drTmp[4]), .QN() + ); + AOI22_X1_LVT i_0_0_36( + .A1(drTmp[20]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[4]), .ZN(n_0_0_20) + ); + NAND2_X1_LVT i_0_0_35( + .A1(n_0_0_21), .A2(n_0_0_20), .ZN(n_0_15) + ); + DLH_X1_LVT \DRData[4] ( + .D(n_0_15), .G(n_0_43), .Q(DRData[4]) + ); + AOI22_X1_LVT i_0_0_34( + .A1(drTmp[27]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[11]), .ZN(n_0_0_19) + ); + DFF_X1_LVT \drTmp_reg[3] ( + .CK(n_0_76), .D(mem_rdata[3]), .Q(drTmp[3]), .QN() + ); + AOI22_X1_LVT i_0_0_33( + .A1(drTmp[19]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[3]), .ZN(n_0_0_18) + ); + NAND2_X1_LVT i_0_0_32( + .A1(n_0_0_19), .A2(n_0_0_18), .ZN(n_0_14) + ); + DLH_X1_LVT \DRData[3] ( + .D(n_0_14), .G(n_0_43), .Q(DRData[3]) + ); + AOI22_X1_LVT i_0_0_31( + .A1(drTmp[26]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[10]), .ZN(n_0_0_17) + ); + DFF_X1_LVT \drTmp_reg[2] ( + .CK(n_0_76), .D(mem_rdata[2]), .Q(drTmp[2]), .QN() + ); + AOI22_X1_LVT i_0_0_30( + .A1(drTmp[18]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[2]), .ZN(n_0_0_16) + ); + NAND2_X1_LVT i_0_0_29( + .A1(n_0_0_17), .A2(n_0_0_16), .ZN(n_0_13) + ); + DLH_X1_LVT \DRData[2] ( + .D(n_0_13), .G(n_0_43), .Q(DRData[2]) + ); + AOI22_X1_LVT i_0_0_28( + .A1(drTmp[25]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[9]), .ZN(n_0_0_15) + ); + DFF_X1_LVT \drTmp_reg[1] ( + .CK(n_0_76), .D(mem_rdata[1]), .Q(drTmp[1]), .QN() + ); + AOI22_X1_LVT i_0_0_27( + .A1(drTmp[17]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[1]), .ZN(n_0_0_14) + ); + NAND2_X1_LVT i_0_0_26( + .A1(n_0_0_15), .A2(n_0_0_14), .ZN(n_0_12) + ); + DLH_X1_LVT \DRData[1] ( + .D(n_0_12), .G(n_0_43), .Q(DRData[1]) + ); + AOI22_X1_LVT i_0_0_25( + .A1(drTmp[24]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[8]), .ZN(n_0_0_13) + ); + DFF_X1_LVT \drTmp_reg[0] ( + .CK(n_0_76), .D(mem_rdata[0]), .Q(drTmp[0]), .QN() + ); + AOI22_X1_LVT i_0_0_24( + .A1(drTmp[16]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[0]), .ZN(n_0_0_12) + ); + NAND2_X1_LVT i_0_0_23( + .A1(n_0_0_13), .A2(n_0_0_12), .ZN(n_0_11) + ); + DLH_X1_LVT \DRData[0] ( + .D(n_0_11), .G(n_0_43), .Q(DRData[0]) + ); + DFF_X1_LVT \IRData_reg[31] ( + .CK(clk), .D(mem_rdata[31]), .Q(IRData[31]), .QN() + ); + DFF_X1_LVT \IRData_reg[30] ( + .CK(clk), .D(mem_rdata[30]), .Q(IRData[30]), .QN() + ); + DFF_X1_LVT \IRData_reg[29] ( + .CK(clk), .D(mem_rdata[29]), .Q(IRData[29]), .QN() + ); + DFF_X1_LVT \IRData_reg[28] ( + .CK(clk), .D(mem_rdata[28]), .Q(IRData[28]), .QN() + ); + DFF_X1_LVT \IRData_reg[27] ( + .CK(clk), .D(mem_rdata[27]), .Q(IRData[27]), .QN() + ); + DFF_X1_LVT \IRData_reg[26] ( + .CK(clk), .D(mem_rdata[26]), .Q(IRData[26]), .QN() + ); + DFF_X1_LVT \IRData_reg[25] ( + .CK(clk), .D(mem_rdata[25]), .Q(IRData[25]), .QN() + ); + DFF_X1_LVT \IRData_reg[24] ( + .CK(clk), .D(mem_rdata[24]), .Q(IRData[24]), .QN() + ); + DFF_X1_LVT \IRData_reg[23] ( + .CK(clk), .D(mem_rdata[23]), .Q(IRData[23]), .QN() + ); + DFF_X1_LVT \IRData_reg[22] ( + .CK(clk), .D(mem_rdata[22]), .Q(IRData[22]), .QN() + ); + DFF_X1_LVT \IRData_reg[21] ( + .CK(clk), .D(mem_rdata[21]), .Q(IRData[21]), .QN() + ); + DFF_X1_LVT \IRData_reg[20] ( + .CK(clk), .D(mem_rdata[20]), .Q(IRData[20]), .QN() + ); + DFF_X1_LVT \IRData_reg[19] ( + .CK(clk), .D(mem_rdata[19]), .Q(IRData[19]), .QN() + ); + DFF_X1_LVT \IRData_reg[18] ( + .CK(clk), .D(mem_rdata[18]), .Q(IRData[18]), .QN() + ); + DFF_X1_LVT \IRData_reg[17] ( + .CK(clk), .D(mem_rdata[17]), .Q(IRData[17]), .QN() + ); + DFF_X1_LVT \IRData_reg[16] ( + .CK(clk), .D(mem_rdata[16]), .Q(IRData[16]), .QN() + ); + DFF_X1_LVT \IRData_reg[15] ( + .CK(clk), .D(mem_rdata[15]), .Q(IRData[15]), .QN() + ); + DFF_X1_LVT \IRData_reg[14] ( + .CK(clk), .D(mem_rdata[14]), .Q(IRData[14]), .QN() + ); + DFF_X1_LVT \IRData_reg[13] ( + .CK(clk), .D(mem_rdata[13]), .Q(IRData[13]), .QN() + ); + DFF_X1_LVT \IRData_reg[12] ( + .CK(clk), .D(mem_rdata[12]), .Q(IRData[12]), .QN() + ); + DFF_X1_LVT \IRData_reg[11] ( + .CK(clk), .D(mem_rdata[11]), .Q(IRData[11]), .QN() + ); + DFF_X1_LVT \IRData_reg[10] ( + .CK(clk), .D(mem_rdata[10]), .Q(IRData[10]), .QN() + ); + DFF_X1_LVT \IRData_reg[9] ( + .CK(clk), .D(mem_rdata[9]), .Q(IRData[9]), .QN() + ); + DFF_X1_LVT \IRData_reg[8] ( + .CK(clk), .D(mem_rdata[8]), .Q(IRData[8]), .QN() + ); + DFF_X1_LVT \IRData_reg[7] ( + .CK(clk), .D(mem_rdata[7]), .Q(IRData[7]), .QN() + ); + DFF_X1_LVT \IRData_reg[6] ( + .CK(clk), .D(mem_rdata[6]), .Q(IRData[6]), .QN() + ); + DFF_X1_LVT \IRData_reg[5] ( + .CK(clk), .D(mem_rdata[5]), .Q(IRData[5]), .QN() + ); + DFF_X1_LVT \IRData_reg[4] ( + .CK(clk), .D(mem_rdata[4]), .Q(IRData[4]), .QN() + ); + DFF_X1_LVT \IRData_reg[3] ( + .CK(clk), .D(mem_rdata[3]), .Q(IRData[3]), .QN() + ); + DFF_X1_LVT \IRData_reg[2] ( + .CK(clk), .D(mem_rdata[2]), .Q(IRData[2]), .QN() + ); + DFF_X1_LVT \IRData_reg[1] ( + .CK(clk), .D(mem_rdata[1]), .Q(IRData[1]), .QN() + ); + DFF_X1_LVT \IRData_reg[0] ( + .CK(clk), .D(mem_rdata[0]), .Q(IRData[0]), .QN() + ); +endmodule + +module reg_file(Rs1, Rs2, Rd, RRs1, RRs2, WRd, WrReg, reset, clk, dftIn, ts_intno31, + ts_no1050, ts_no1051, ts_no1053, ts_no1054, ts_extsi1226, ts_extsi1227, + ts_extsi1228); + input [31:0] WRd; + input [4:0] Rs1, Rs2, Rd; + input WrReg, reset, clk, dftIn, ts_extsi1227, ts_extsi1228, ts_intno31, + ts_extsi1226; + output [31:0] RRs1, RRs2; + output ts_no1050, ts_no1051, ts_no1053, ts_no1054; + + wire [31:0] registers_1__ap, registers_2__ap, registers_3__ap, + registers_4__ap, registers_5__ap, registers_6__ap, + registers_7__ap, registers_8__ap, registers_9__ap, + registers_10__ap, registers_11__ap, registers_12__ap, + registers_13__ap, registers_14__ap, registers_15__ap, + registers_16__ap, registers_17__ap, registers_18__ap, + registers_19__ap, registers_20__ap, registers_21__ap, + registers_22__ap, registers_23__ap, registers_24__ap, + registers_25__ap, registers_26__ap, registers_27__ap, + registers_28__ap, registers_29__ap, registers_30__ap, + registers_31__ap, registers; + wire n_0_0, n_0_32, n_0_33, n_0_34, n_0_35, n_0_36, n_0_37, n_0_38, n_0_39, + n_0_40, n_0_41, n_0_42, n_0_43, n_0_44, n_0_45, n_0_46, n_0_47, n_0_48, + n_0_49, n_0_50, n_0_51, n_0_52, n_0_53, n_0_54, n_0_55, n_0_56, n_0_57, + n_0_58, n_0_59, n_0_60, n_0_61, n_0_31, n_0_30, n_0_29, n_0_28, n_0_27, + n_0_26, n_0_25, n_0_24, n_0_0_0, n_0_0_1, n_0_23, n_0_22, n_0_21, + n_0_20, n_0_19, n_0_18, n_0_17, n_0_16, n_0_0_2, n_0_0_3, n_0_15, + n_0_14, n_0_13, n_0_12, n_0_11, n_0_10, n_0_9, n_0_8, n_0_0_4, n_0_0_5, + n_0_7, n_0_0_6, n_0_6, n_0_0_7, n_0_5, n_0_0_8, n_0_4, n_0_0_9, + n_0_0_10, n_0_3, n_0_0_11, n_0_2, n_0_0_12, n_0_1, n_0_0_13, n_0_0_14, + n_0_0_15, n_0_0_16, n_0_0_17, n_0_0_18, n_0_0_19, n_0_0_20, n_1_0_0, + n_1_0_1, n_1_0_2, n_1_0_3, n_1_0_4, n_1_0_5, n_1_0_6, n_1_0_7, n_1_0_8, + n_1_0_9, n_1_0_10, n_1_0_11, n_1_0_12, n_1_0_13, n_1_0_14, n_1_0_15, + n_1_0_16, n_1_0_17, n_1_0_18, n_1_0_19, n_1_0_20, n_1_0_21, n_1_0_22, + n_1_0_23, n_1_0_24, n_1_0_25, n_1_0_26, n_1_0_27, n_1_0_28, n_1_0_29, + n_1_0_30, n_1_0_31, n_1_0_32, n_1_0_33, n_1_0_34, n_1_0_35, n_1_0_36, + n_1_0_37, n_1_0_38, n_1_0_39, n_1_0_40, n_1_0_41, n_1_0_42, n_1_0_43, + n_1_0_44, n_1_0_45, n_1_0_46, n_1_0_47, n_1_0_48, n_1_0_49, n_1_0_50, + n_1_0_51, n_1_0_52, n_1_0_53, n_1_0_54, n_1_0_55, n_1_0_56, n_1_0_57, + n_1_0_58, n_1_0_59, n_1_0_60, n_1_0_61, n_1_0_62, n_1_0_63, n_1_0_64, + n_1_0_65, n_1_0_66, n_1_0_67, n_1_0_68, n_1_0_69, n_1_0_70, n_1_0_71, + n_1_0_72, n_1_0_73, n_1_0_74, n_1_0_75, n_1_0_76, n_1_0_77, n_1_0_78, + n_1_0_79, n_1_0_80, n_1_0_81, n_1_0_82, n_1_0_83, n_1_0_84, n_1_0_85, + n_1_0_86, n_1_0_87, n_1_0_88, n_1_0_89, n_1_0_90, n_1_0_91, n_1_0_92, + n_1_0_93, n_1_0_94, n_1_0_95, n_1_0_96, n_1_0_97, n_1_0_98, n_1_0_99, + n_1_0_100, n_1_0_101, n_1_0_102, n_1_0_103, n_1_0_104, n_1_0_105, + n_1_0_106, n_1_0_107, n_1_0_108, n_1_0_109, n_1_0_110, n_1_0_111, + n_1_0_112, n_1_0_113, n_1_0_114, n_1_0_115, n_1_0_116, n_1_0_117, + n_1_0_118, n_1_0_119, n_1_0_120, n_1_0_121, n_1_0_122, n_1_0_123, + n_1_0_124, n_1_0_125, n_1_0_126, n_1_0_127, n_1_0_128, n_1_0_129, + n_1_0_130, n_1_0_131, n_1_0_132, n_1_0_133, n_1_0_134, n_1_0_135, + n_1_0_136, n_1_0_137, n_1_0_138, n_1_0_139, n_1_0_140, n_1_0_141, + n_1_0_142, n_1_0_143, n_1_0_144, n_1_0_145, n_1_0_146, n_1_0_147, + n_1_0_148, n_1_0_149, n_1_0_150, n_1_0_151, n_1_0_152, n_1_0_153, + n_1_0_154, n_1_0_155, n_1_0_156, n_1_0_157, n_1_0_158, n_1_0_159, + n_1_0_160, n_1_0_161, n_1_0_162, n_1_0_163, n_1_0_164, n_1_0_165, + n_1_0_166, n_1_0_167, n_1_0_168, n_1_0_169, n_1_0_170, n_1_0_171, + n_1_0_172, n_1_0_173, n_1_0_174, n_1_0_175, n_1_0_176, n_1_0_177, + n_1_0_178, n_1_0_179, n_1_0_180, n_1_0_181, n_1_0_182, n_1_0_183, + n_1_0_184, n_1_0_185, n_1_0_186, n_1_0_187, n_1_0_188, n_1_0_189, + n_1_0_190, n_1_0_191, n_1_0_192, n_1_0_193, n_1_0_194, n_1_0_195, + n_1_0_196, n_1_0_197, n_1_0_198, n_1_0_199, n_1_0_200, n_1_0_201, + n_1_0_202, n_1_0_203, n_1_0_204, n_1_0_205, n_1_0_206, n_1_0_207, + n_1_0_208, n_1_0_209, n_1_0_210, n_1_0_211, n_1_0_212, n_1_0_213, + n_1_0_214, n_1_0_215, n_1_0_216, n_1_0_217, n_1_0_218, n_1_0_219, + n_1_0_220, n_1_0_221, n_1_0_222, n_1_0_223, n_1_0_224, n_1_0_225, + n_1_0_226, n_1_0_227, n_1_0_228, n_1_0_229, n_1_0_230, n_1_0_231, + n_1_0_232, n_1_0_233, n_1_0_234, n_1_0_235, n_1_0_236, n_1_0_237, + n_1_0_238, n_1_0_239, n_1_0_240, n_1_0_241, n_1_0_242, n_1_0_243, + n_1_0_244, n_1_0_245, n_1_0_246, n_1_0_247, n_1_0_248, n_1_0_249, + n_1_0_250, n_1_0_251, n_1_0_252, n_1_0_253, n_1_0_254, n_1_0_255, + n_1_0_256, n_1_0_257, n_1_0_258, n_1_0_259, n_1_0_260, n_1_0_261, + n_1_0_262, n_1_0_263, n_1_0_264, n_1_0_265, n_1_0_266, n_1_0_267, + n_1_0_268, n_1_0_269, n_1_0_270, n_1_0_271, n_1_0_272, n_1_0_273, + n_1_0_274, n_1_0_275, n_1_0_276, n_1_0_277, n_1_0_278, n_1_0_279, + n_1_0_280, n_1_0_281, n_1_0_282, n_1_0_283, n_1_0_284, n_1_0_285, + n_1_0_286, n_1_0_287, n_1_0_288, n_1_0_289, n_1_0_290, n_1_0_291, + n_1_0_292, n_1_0_293, n_1_0_294, n_1_0_295, n_1_0_296, n_1_0_297, + n_1_0_298, n_1_0_299, n_1_0_300, n_1_0_301, n_1_0_302, n_1_0_303, + n_1_0_304, n_1_0_305, n_1_0_306, n_1_0_307, n_1_0_308, n_1_0_309, + n_1_0_310, n_1_0_311, n_1_0_312, n_1_0_313, n_1_0_314, n_1_0_315, + n_1_0_316, n_1_0_317, n_1_0_318, n_1_0_319, n_1_0_320, n_1_0_321, + n_1_0_322, n_1_0_323, n_1_0_324, n_1_0_325, n_1_0_326, n_1_0_327, + n_1_0_328, n_1_0_329, n_1_0_330, n_1_0_331, n_1_0_332, n_1_0_333, + n_1_0_334, n_1_0_335, n_1_0_336, n_1_0_337, n_1_0_338, n_1_0_339, + n_1_0_340, n_1_0_341, n_1_0_342, n_1_0_343, n_1_0_344, n_1_0_345, + n_1_0_346, n_1_0_347, n_1_0_348, n_1_0_349, n_1_0_350, n_1_0_351, + n_1_0_352, n_1_0_353, n_1_0_354, n_1_0_355, n_1_0_356, n_1_0_357, + n_1_0_358, n_1_0_359, n_1_0_360, n_1_0_361, n_1_0_362, n_1_0_363, + n_1_0_364, n_1_0_365, n_1_0_366, n_1_0_367, n_1_0_368, n_1_0_369, + n_1_0_370, n_1_0_371, n_1_0_372, n_1_0_373, n_1_0_374, n_1_0_375, + n_1_0_376, n_1_0_377, n_1_0_378, n_1_0_379, n_1_0_380, n_1_0_381, + n_1_0_382, n_1_0_383, n_1_0_384, n_1_0_385, n_1_0_386, n_1_0_387, + n_1_0_388, n_1_0_389, n_1_0_390, n_1_0_391, n_1_0_392, n_1_0_393, + n_1_0_394, n_1_0_395, n_1_0_396, n_1_0_397, n_1_0_398, n_1_0_399, + n_1_0_400, n_1_0_401, n_1_0_402, n_1_0_403, n_1_0_404, n_1_0_405, + n_1_0_406, n_1_0_407, n_1_0_408, n_1_0_409, n_1_0_410, n_1_0_411, + n_1_0_412, n_1_0_413, n_1_0_414, n_1_0_415, n_1_0_416, n_1_0_417, + n_1_0_418, n_1_0_419, n_1_0_420, n_1_0_421, n_1_0_422, n_1_0_423, + n_1_0_424, n_1_0_425, n_1_0_426, n_1_0_427, n_1_0_428, n_1_0_429, + n_1_0_430, n_1_0_431, n_1_0_432, n_1_0_433, n_1_0_434, n_1_0_435, + n_1_0_436, n_1_0_437, n_1_0_438, n_1_0_439, n_1_0_440, n_1_0_441, + n_1_0_442, n_1_0_443, n_1_0_444, n_1_0_445, n_1_0_446, n_1_0_447, + n_1_0_448, n_1_0_449, n_1_0_450, n_1_0_451, n_1_0_452, n_1_0_453, + n_1_0_454, n_1_0_455, n_1_0_456, n_1_0_457, n_1_0_458, n_1_0_459, + n_1_0_460, n_1_0_461, n_1_0_462, n_1_0_463, n_1_0_464, n_1_0_465, + n_1_0_466, n_1_0_467, n_1_0_468, n_1_0_469, n_1_0_470, n_1_0_471, + n_1_0_472, n_1_0_473, n_1_0_474, n_1_0_475, n_1_0_476, n_1_0_477, + n_1_0_478, n_1_0_479, n_1_0_480, n_1_0_481, n_1_0_482, n_1_0_483, + n_1_0_484, n_1_0_485, n_1_0_486, n_1_0_487, n_1_0_488, n_1_0_489, + n_1_0_490, n_1_0_491, n_1_0_492, n_1_0_493, n_1_0_494, n_1_0_495, + n_1_0_496, n_1_0_497, n_1_0_498, n_1_0_499, n_1_0_500, n_1_0_501, + n_1_0_502, n_1_0_503, n_1_0_504, n_1_0_505, n_1_0_506, n_1_0_507, + n_1_0_508, n_1_0_509, n_1_0_510, n_1_0_511, n_1_0_512, n_1_0_513, + n_1_0_514, n_1_0_515, n_1_0_516, n_1_0_517, n_1_0_518, n_1_0_519, + n_1_0_520, n_1_0_521, n_1_0_522, n_1_0_523, n_1_0_524, n_1_0_525, + n_1_0_526, n_1_0_527, n_1_0_528, n_1_0_529, n_1_0_530, n_1_0_531, + n_1_0_532, n_1_0_533, n_1_0_534, n_1_0_535, n_1_0_536, n_1_0_537, + n_1_0_538, n_1_0_539, n_1_0_540, n_1_0_541, n_1_0_542, n_1_0_543, + n_1_0_544, n_1_0_545, n_1_0_546, n_1_0_547, n_1_0_548, n_1_0_549, + n_1_0_550, n_1_0_551, n_1_0_552, n_1_0_553, n_1_0_554, n_1_0_555, + n_1_0_556, n_1_0_557, n_1_0_558, n_1_0_559, n_1_0_560, n_1_0_561, + n_1_0_562, n_1_0_563, n_1_0_564, n_1_0_565, n_1_0_566, n_1_0_567, + n_1_0_568, n_1_0_569, n_1_0_570, n_1_0_571, n_1_0_572, n_1_0_573, + n_1_0_574, n_1_0_575, n_1_0_576, n_1_0_577, n_1_0_578, n_1_0_579, + n_1_0_580, n_1_0_581, n_1_0_582, n_1_0_583, n_1_0_584, n_1_0_585, + n_1_0_586, n_1_0_587, n_1_0_588, n_1_0_589, n_1_0_590, n_1_0_591, + n_1_0_592, n_1_0_593, n_1_0_594, n_1_0_595, n_1_0_596, n_1_0_597, + n_1_0_598, n_1_0_599, n_1_0_600, n_1_0_601, n_1_0_602, n_1_0_603, + n_1_0_604, n_1_0_605, n_1_0_606, n_1_0_607, n_1_0_608, n_1_0_609, + n_1_0_610, n_1_0_611, n_1_0_612, n_1_0_613, n_1_0_614, n_1_0_615, + n_1_0_616, n_1_0_617, n_1_0_618, n_1_0_619, n_1_0_620, n_1_0_621, + n_1_0_622, n_1_0_623, n_1_0_624, n_1_0_625, n_1_0_626, n_1_0_627, + n_1_0_628, n_1_0_629, n_1_0_630, n_1_0_631, n_1_0_632, n_1_0_633, + n_1_0_634, n_1_0_635, n_1_0_636, n_1_0_637, n_1_0_638, n_1_0_639, + n_1_0_640, n_1_0_641, n_1_0_642, n_1_0_643, n_1_0_644, n_1_0_645, + n_1_0_646, n_1_0_647, n_1_0_648, n_1_0_649, n_1_0_650, n_1_0_651, + n_1_0_652, n_1_0_653, n_1_0_654, n_1_0_655, n_1_0_656, n_1_0_657, + n_1_0_658, n_1_0_659, n_1_0_660, n_1_0_661, n_1_0_662, n_1_0_663, + n_1_0_664, n_1_0_665, n_1_0_666, n_1_0_667, n_1_0_668, n_1_0_669, + n_1_0_670, n_1_0_671, n_1_0_672, n_1_0_673, n_1_0_674, n_1_0_675, + n_1_0_676, n_1_0_677, n_1_0_678, n_1_0_679, n_1_0_680, n_1_0_681, + n_1_0_682, n_1_0_683, n_1_0_684, n_1_0_685, n_1_0_686, n_1_0_687, + n_1_0_688, n_1_0_689, n_1_0_690, n_1_0_691, n_1_0_692, n_1_0_693, + n_1_0_694, n_1_0_695, n_1_0_696, n_1_0_697, n_1_0_698, n_1_0_699, + n_1_0_700, n_1_0_701, n_1_0_702, n_1_0_703, n_1_0_704, n_1_0_705, + n_1_0_706, n_1_0_707, n_1_0_708, n_1_0_709, n_1_0_710, n_1_0_711, + n_1_0_712, n_1_0_713, n_1_0_714, n_1_0_715, n_1_0_716, n_1_0_717, + n_1_0_718, n_1_0_719, n_1_0_720, n_1_0_721, n_1_0_722, n_1_0_723, + n_1_0_724, n_1_0_725, n_1_0_726, n_1_0_727, n_1_0_728, n_1_0_729, + n_1_0_730, n_1_0_731, n_1_0_732, n_1_0_733, n_1_0_734, n_1_0_735, + n_1_0_736, n_1_0_737, n_1_0_738, n_1_0_739, n_1_0_740, n_1_0_741, + n_1_0_742, n_1_0_743, n_1_0_744, n_1_0_745, n_1_0_746, n_1_0_747, + n_1_0_748, n_1_0_749, n_1_0_750, n_1_0_751, n_1_0_752, n_1_0_753, + n_1_0_754, n_1_0_755, n_1_0_756, n_1_0_757, n_1_0_758, n_1_0_759, + n_1_0_760, n_1_0_761, n_1_0_762, n_1_0_763, n_1_0_764, n_1_0_765, + n_1_0_766, n_1_0_767, n_1_0_768, n_1_0_769, n_1_0_770, n_1_0_771, + n_1_0_772, n_1_0_773, n_1_0_774, n_1_0_775, n_1_0_776, n_1_0_777, + n_1_0_778, n_1_0_779, n_1_0_780, n_1_0_781, n_1_0_782, n_1_0_783, + n_1_0_784, n_1_0_785, n_1_0_786, n_1_0_787, n_1_0_788, n_1_0_789, + n_1_0_790, n_1_0_791, n_1_0_792, n_1_0_793, n_1_0_794, n_1_0_795, + n_1_0_796, n_1_0_797, n_1_0_798, n_1_0_799, n_1_0_800, n_1_0_801, + n_1_0_802, n_1_0_803, n_1_0_804, n_1_0_805, n_1_0_806, n_1_0_807, + n_1_0_808, n_1_0_809, n_1_0_810, n_1_0_811, n_1_0_812, n_1_0_813, + n_1_0_814, n_1_0_815, n_1_0_816, n_1_0_817, n_1_0_818, n_1_0_819, + n_1_0_820, n_1_0_821, n_1_0_822, n_1_0_823, n_1_0_824, n_1_0_825, + n_1_0_826, n_1_0_827, n_1_0_828, n_1_0_829, n_1_0_830, n_1_0_831, + n_1_0_832, n_1_0_833, n_1_0_834, n_1_0_835, n_1_0_836, n_1_0_837, + n_1_0_838, n_1_0_839, n_1_0_840, n_1_0_841, n_1_0_842, n_1_0_843, + n_1_0_844, n_1_0_845, n_1_0_846, n_1_0_847, n_1_0_848, n_1_0_849, + n_1_0_850, n_1_0_851, n_1_0_852, n_1_0_853, n_1_0_854, n_1_0_855, + n_1_0_856, n_1_0_857, n_1_0_858, n_1_0_859, n_1_0_860, n_1_0_861, + n_1_0_862, n_1_0_863, n_1_0_864, n_1_0_865, n_1_0_866, n_1_0_867, + n_1_0_868, n_1_0_869, n_1_0_870, n_1_0_871, n_1_0_872, n_1_0_873, + n_1_0_874, n_1_0_875, n_1_0_876, n_1_0_877, n_1_0_878, n_1_0_879, + n_1_0_880, n_1_0_881, n_1_0_882, n_1_0_883, n_1_0_884, n_1_0_885, + n_1_0_886, n_1_0_887, n_1_0_888, n_1_0_889, n_1_0_890, n_1_0_891, + n_1_0_892, n_1_0_893, n_1_0_894, n_1_0_895, n_1_0_896, n_1_0_897, + n_1_0_898, n_1_0_899, n_1_0_900, n_1_0_901, n_1_0_902, n_1_0_903, + n_1_0_904, n_1_0_905, n_1_0_906, n_1_0_907, n_1_0_908, n_1_0_909, + n_1_0_910, n_1_0_911, n_1_0_912, n_1_0_913, n_1_0_914, n_1_0_915, + n_1_0_916, n_1_0_917, n_1_0_918, n_1_0_919, n_1_0_920, n_1_0_921, + n_1_0_922, n_1_0_923, n_1_0_924, n_1_0_925, n_1_0_926, n_1_0_927, + n_1_0_928, n_1_0_929, n_1_0_930, n_1_0_931, n_1_0_932, n_1_0_933, + n_1_0_934, n_1_0_935, n_1_0_936, n_1_0_937, n_1_0_938, n_1_0_939, + n_1_0_940, n_1_0_941, n_1_0_942, n_1_0_943, n_1_0_944, n_1_0_945, + n_1_0_946, n_1_0_947, n_1_0_948, n_1_0_949, n_1_0_950, n_1_0_951, + n_1_0_952, n_1_0_953, n_1_0_954, n_1_0_955, n_1_0_956, n_1_0_957, + n_1_0_958, n_1_0_959, n_1_0_960, n_1_0_961, n_1_0_962, n_1_0_963, + n_1_0_964, n_1_0_965, n_1_0_966, n_1_0_967, n_1_0_968, n_1_0_969, + n_1_0_970, n_1_0_971, n_1_0_972, n_1_0_973, n_1_0_974, n_1_0_975, + n_1_0_976, n_1_0_977, n_1_0_978, n_1_0_979, n_1_0_980, n_1_0_981, + n_1_0_982, n_1_0_983, n_1_0_984, n_1_0_985, n_1_0_986, n_1_0_987, + n_1_0_988, n_1_0_989, n_1_0_990, n_1_0_991, n_1_0_992, n_1_0_993, + n_1_0_994, n_1_0_995, n_1_0_996, n_1_0_997, n_1_0_998, n_1_0_999, + n_1_0_1000, n_1_0_1001, n_1_0_1002, n_1_0_1003, n_1_0_1004, n_1_0_1005, + n_1_0_1006, n_1_0_1007, n_1_0_1008, n_1_0_1009, n_1_0_1010, n_1_0_1011, + n_1_0_1012, n_1_0_1013, n_1_0_1014, n_1_0_1015, n_1_0_1016, n_1_0_1017, + n_1_0_1018, n_1_0_1019, n_1_0_1020, n_1_0_1021, n_1_0_1022, n_1_0_1023, + n_1_0_1024, n_1_0_1025, n_1_0_1026, n_1_0_1027, n_1_0_1028, n_1_0_1029, + n_1_0_1030, n_1_0_1031, n_1_0_1032, n_1_0_1033, n_1_0_1034, n_1_0_1035, + n_1_0_1036, n_1_0_1037, n_1_0_1038, n_1_0_1039, n_1_0_1040, n_1_0_1041, + n_1_0_1042, n_1_0_1043, n_1_0_1044, n_1_0_1045, n_1_0_1046, n_1_0_1047, + n_1_0_1048, n_1_0_1049, n_1_0_1050, n_1_0_1051, n_1_0_1052, n_1_0_1053, + n_1_0_1054, n_1_0_1055, n_1_0_1056, n_1_0_1057, n_1_0_1058, n_1_0_1059, + n_1_0_1060, n_1_0_1061, n_1_0_1062, n_1_0_1063, n_1_0_1064, n_1_0_1065, + n_1_0_1066, n_1_0_1067, n_1_0_1068, n_1_0_1069, n_1_0_1070, n_1_0_1071, + n_1_0_1072, n_1_0_1073, n_1_0_1074, n_1_0_1075, n_1_0_1076, n_1_0_1077, + n_1_0_1078, n_1_0_1079, n_1_0_1080, n_1_0_1081, n_1_0_1082, n_1_0_1083, + n_1_0_1084, n_1_0_1085, n_1_0_1086, n_1_0_1087, n_1_0_1088, n_1_0_1089, + n_1_0_1090, n_1_0_1091, n_1_0_1092, n_1_0_1093, n_1_0_1094, n_1_0_1095, + n_1_0_1096, n_1_0_1097, n_1_0_1098, n_1_0_1099, n_1_0_1100, n_1_0_1101, + n_1_0_1102, n_1_0_1103, n_1_0_1104, n_1_0_1105, n_1_0_1106, n_1_0_1107, + n_1_0_1108, n_1_0_1109, n_1_0_1110, n_1_0_1111, n_1_0_1112, n_1_0_1113, + n_1_0_1114, n_1_0_1115, n_1_0_1116, n_1_0_1117, n_1_0_1118, n_1_0_1119, + n_1_0_1120, n_1_0_1121, n_1_0_1122, n_1_0_1123, n_1_0_1124, n_1_0_1125, + n_1_0_1126, n_1_0_1127, n_1_0_1128, n_1_0_1129, n_1_0_1130, n_1_0_1131, + n_1_0_1132, n_1_0_1133, n_1_0_1134, n_1_0_1135, n_1_0_1136, n_1_0_1137, + n_1_0_1138, n_1_0_1139, n_1_0_1140, n_1_0_1141, n_1_0_1142, n_1_0_1143, + n_1_0_1144, n_1_0_1145, n_1_0_1146, n_1_0_1147, n_1_0_1148, n_1_0_1149, + n_1_0_1150, n_1_0_1151, n_1_0_1152, n_1_0_1153, n_1_0_1154, n_1_0_1155, + n_1_0_1156, n_1_0_1157, n_1_0_1158, n_1_0_1159, n_1_0_1160, n_1_0_1161, + n_1_0_1162, n_1_0_1163, n_1_0_1164, n_1_0_1165, n_1_0_1166, n_1_0_1167, + n_1_0_1168, n_1_0_1169, n_1_0_1170, n_1_0_1171, n_1_0_1172, n_1_0_1173, + n_1_0_1174, n_1_0_1175, n_1_0_1176, n_1_0_1177, n_1_0_1178, n_1_0_1179, + n_1_0_1180, n_1_0_1181, n_1_0_1182, n_1_0_1183, n_1_0_1184, n_1_0_1185, + n_1_0_1186, n_1_0_1187, n_1_0_1188, n_1_0_1189, n_1_0_1190, n_1_0_1191, + n_1_0_1192, n_1_0_1193, n_1_0_1194, n_1_0_1195, n_1_0_1196, n_1_0_1197, + n_1_0_1198, n_1_0_1199, n_1_0_1200, n_1_0_1201, n_1_0_1202, n_1_0_1203, + n_1_0_1204, n_1_0_1205, n_1_0_1206, n_1_0_1207, n_1_0_1208, n_1_0_1209, + n_1_0_1210, n_1_0_1211, n_1_0_1212, n_1_0_1213, n_1_0_1214, n_1_0_1215, + n_1_0_1216, n_1_0_1217, n_1_0_1218, n_1_0_1219, n_1_0_1220, n_1_0_1221, + n_1_0_1222, n_1_0_1223, n_1_0_1224, n_1_0_1225, n_1_0_1226, n_1_0_1227, + n_1_0_1228, n_1_0_1229, n_1_0_1230, n_1_0_1231, n_1_0_1232, n_1_0_1233, + n_1_0_1234, n_1_0_1235, n_1_0_1236, n_1_0_1237, n_1_0_1238, n_1_0_1239, + n_1_0_1240, n_1_0_1241, n_1_0_1242, n_1_0_1243, n_1_0_1244, n_1_0_1245, + n_1_0_1246, n_1_0_1247, n_1_0_1248, n_1_0_1249, n_1_0_1250, n_1_0_1251, + n_1_0_1252, n_1_0_1253, n_1_0_1254, n_1_0_1255, n_1_0_1256, n_1_0_1257, + n_1_0_1258, n_1_0_1259, n_1_0_1260, n_1_0_1261, n_1_0_1262, n_1_0_1263, + n_1_0_1264, n_1_0_1265, n_1_0_1266, n_1_0_1267, n_1_0_1268, n_1_0_1269, + n_1_0_1270, n_1_0_1271, n_1_0_1272, n_1_0_1273, n_1_0_1274, n_1_0_1275, + n_1_0_1276, n_1_0_1277, n_1_0_1278, n_1_0_1279, n_1_0_1280, n_1_0_1281, + n_1_0_1282, n_1_0_1283, n_1_0_1284, n_1_0_1285, n_1_0_1286, n_1_0_1287, + n_1_0_1288, n_1_0_1289, n_1_0_1290, n_1_0_1291, n_1_0_1292, n_1_0_1293, + n_1_0_1294, n_1_0_1295, n_1_0_1296, n_1_0_1297, n_1_0_1298, n_1_0_1299, + n_1_0_1300, n_1_0_1301, n_1_0_1302, n_1_0_1303, n_1_0_1304, n_1_0_1305, + n_1_0_1306, n_1_0_1307, n_1_0_1308, n_1_0_1309, ts_pbuf_extsi1227_, + ts_pbuf_extsi1228_, ts_pbuf_extsi1226_; + + INV_X1_LVT i_0_0_79( + .A(reset), .ZN(n_0_0_16) + ); + AND2_X1_LVT i_0_0_31( + .A1(n_0_0_16), .A2(WRd[31]), .ZN(registers[31]) + ); + INV_X1_LVT i_0_0_81( + .A(Rd[1]), .ZN(n_0_0_18) + ); + INV_X1_LVT i_0_0_80( + .A(Rd[0]), .ZN(n_0_0_17) + ); + NAND3_X1_LVT i_0_0_69( + .A1(n_0_0_18), .A2(n_0_0_17), .A3(Rd[2]), .ZN(n_0_0_9) + ); + NAND3_X1_LVT i_0_0_41( + .A1(Rd[3]), .A2(WrReg), .A3(Rd[4]), .ZN(n_0_0_1) + ); + OAI21_X1_LVT i_0_0_35( + .A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_1), .ZN(n_0_28) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[28]_reg ( + .CK(clk), .E(n_0_28), .GCK(n_0_58), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[28][31] ( + .CK(n_0_58), .D(registers[31]), .Q(registers_28__ap[31]), .QN(), .SE(dftIn), + .SI(ts_pbuf_extsi1227_) + ); + INV_X1_LVT i_1_0_1370( + .A(Rs1[0]), .ZN(n_1_0_1306) + ); + NAND3_X1_LVT i_1_0_1354( + .A1(n_1_0_1306), .A2(Rs1[3]), .A3(Rs1[4]), .ZN(n_1_0_1290) + ); + INV_X1_LVT i_1_0_1373( + .A(Rs1[2]), .ZN(n_1_0_1309) + ); + OR2_X1_LVT i_1_0_1348( + .A1(n_1_0_1309), .A2(Rs1[1]), .ZN(n_1_0_1284) + ); + NOR2_X1_LVT i_1_0_1347( + .A1(n_1_0_1290), .A2(n_1_0_1284), .ZN(n_1_0_1283) + ); + NOR4_X1_LVT i_1_0_1342( + .A1(n_1_0_1284), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), .ZN(n_1_0_1278) + ); + INV_X1_LVT i_0_0_83( + .A(WrReg), .ZN(n_0_0_20) + ); + OR3_X1_LVT i_0_0_77( + .A1(n_0_0_20), .A2(Rd[4]), .A3(Rd[3]), .ZN(n_0_0_14) + ); + OAI21_X1_LVT i_0_0_68( + .A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_9), .ZN(n_0_4) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[4]_reg ( + .CK(clk), .E(n_0_4), .GCK(n_0_34), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[4][31] ( + .CK(n_0_34), .D(registers[31]), .Q(registers_4__ap[31]), .QN(), .SE(dftIn), + .SI(ts_pbuf_extsi1228_) + ); + AOI22_X1_LVT i_1_0_1320( + .A1(registers_28__ap[31]), .A2(n_1_0_1283), .B1(n_1_0_1278), .B2(registers_4__ap[31]), + .ZN(n_1_0_1256) + ); + NAND2_X1_LVT i_0_0_70( + .A1(n_0_0_18), .A2(n_0_0_17), .ZN(n_0_0_10) + ); + INV_X1_LVT i_0_0_82( + .A(Rd[4]), .ZN(n_0_0_19) + ); + OR3_X1_LVT i_0_0_51( + .A1(n_0_0_20), .A2(n_0_0_19), .A3(Rd[3]), .ZN(n_0_0_3) + ); + OR2_X1_LVT i_0_0_50( + .A1(n_0_0_3), .A2(Rd[2]), .ZN(n_0_0_2) + ); + OAI21_X1_LVT i_0_0_49( + .A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_2), .ZN(n_0_16) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[16]_reg ( + .CK(clk), .E(n_0_16), .GCK(n_0_46), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[16][31] ( + .CK(n_0_46), .D(registers[31]), .Q(registers_16__ap[31]), .QN(), .SE(dftIn), + .SI(ts_intno31) + ); + INV_X1_LVT i_1_0_1371( + .A(Rs1[3]), .ZN(n_1_0_1307) + ); + NAND3_X1_LVT i_1_0_1363( + .A1(n_1_0_1307), .A2(n_1_0_1306), .A3(Rs1[4]), .ZN(n_1_0_1299) + ); + OR2_X1_LVT i_1_0_1357( + .A1(Rs1[1]), .A2(Rs1[2]), .ZN(n_1_0_1293) + ); + NOR2_X1_LVT i_1_0_1331( + .A1(n_1_0_1299), .A2(n_1_0_1293), .ZN(n_1_0_1267) + ); + NAND2_X1_LVT i_1_0_1365( + .A1(Rs1[1]), .A2(Rs1[2]), .ZN(n_1_0_1301) + ); + NAND3_X1_LVT i_1_0_1344( + .A1(Rs1[4]), .A2(Rs1[3]), .A3(Rs1[0]), .ZN(n_1_0_1280) + ); + NOR2_X1_LVT i_1_0_1330( + .A1(n_1_0_1301), .A2(n_1_0_1280), .ZN(n_1_0_1266) + ); + NAND3_X1_LVT i_0_0_63( + .A1(Rd[2]), .A2(Rd[1]), .A3(Rd[0]), .ZN(n_0_0_6) + ); + OAI21_X1_LVT i_0_0_32( + .A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_1), .ZN(n_0_31) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[31]_reg ( + .CK(clk), .E(n_0_31), .GCK(n_0_61), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[31][31] ( + .CK(n_0_61), .D(registers[31]), .Q(registers_31__ap[31]), .QN(), .SE(dftIn), + .SI(registers_4__ap[31]) + ); + AOI22_X1_LVT i_1_0_1329( + .A1(registers_16__ap[31]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[31]), + .ZN(n_1_0_1265) + ); + NAND3_X1_LVT i_0_0_65( + .A1(n_0_0_17), .A2(Rd[1]), .A3(Rd[2]), .ZN(n_0_0_7) + ); + OAI21_X1_LVT i_0_0_64( + .A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_7), .ZN(n_0_6) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[6]_reg ( + .CK(clk), .E(n_0_6), .GCK(n_0_36), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[6][31] ( + .CK(n_0_36), .D(registers[31]), .Q(registers_6__ap[31]), .QN(), .SE(dftIn), + .SI(registers_31__ap[31]) + ); + NOR4_X1_LVT i_1_0_1364( + .A1(n_1_0_1301), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), .ZN(n_1_0_1300) + ); + INV_X1_LVT i_1_0_1372( + .A(Rs1[4]), .ZN(n_1_0_1308) + ); + NAND3_X1_LVT i_1_0_1339( + .A1(n_1_0_1308), .A2(n_1_0_1307), .A3(Rs1[0]), .ZN(n_1_0_1275) + ); + NOR2_X1_LVT i_1_0_1338( + .A1(n_1_0_1293), .A2(n_1_0_1275), .ZN(n_1_0_1274) + ); + NAND2_X1_LVT i_0_0_78( + .A1(n_0_0_18), .A2(Rd[0]), .ZN(n_0_0_15) + ); + OR2_X1_LVT i_0_0_76( + .A1(n_0_0_14), .A2(Rd[2]), .ZN(n_0_0_13) + ); + OAI21_X1_LVT i_0_0_75( + .A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_13), .ZN(n_0_1) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[1]_reg ( + .CK(clk), .E(n_0_1), .GCK(n_0_0), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[1][31] ( + .CK(n_0_0), .D(registers[31]), .Q(registers_1__ap[31]), .QN(), .SE(dftIn), + .SI(ts_pbuf_extsi1226_) + ); + AOI22_X1_LVT i_1_0_1319( + .A1(registers_6__ap[31]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[31]), + .ZN(n_1_0_1255) + ); + OAI21_X1_LVT i_0_0_42( + .A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_3), .ZN(n_0_23) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[23]_reg ( + .CK(clk), .E(n_0_23), .GCK(n_0_53), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[23][31] ( + .CK(n_0_53), .D(registers[31]), .Q(registers_23__ap[31]), .QN(), .SE(dftIn), + .SI(registers_1__ap[31]) + ); + NAND3_X1_LVT i_1_0_1360( + .A1(n_1_0_1307), .A2(Rs1[0]), .A3(Rs1[4]), .ZN(n_1_0_1296) + ); + NOR2_X1_LVT i_1_0_1328( + .A1(n_1_0_1301), .A2(n_1_0_1296), .ZN(n_1_0_1264) + ); + NOR2_X1_LVT i_1_0_1327( + .A1(n_1_0_1301), .A2(n_1_0_1275), .ZN(n_1_0_1263) + ); + OAI21_X1_LVT i_0_0_62( + .A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_6), .ZN(n_0_7) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[7]_reg ( + .CK(clk), .E(n_0_7), .GCK(n_0_37), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[7][31] ( + .CK(n_0_37), .D(registers[31]), .Q(registers_7__ap[31]), .QN(), .SE(dftIn), + .SI(registers_6__ap[31]) + ); + AOI22_X1_LVT i_1_0_1326( + .A1(registers_23__ap[31]), .A2(n_1_0_1264), .B1(n_1_0_1263), .B2(registers_7__ap[31]), + .ZN(n_1_0_1262) + ); + INV_X1_LVT i_1_0_1325( + .A(n_1_0_1262), .ZN(n_1_0_1261) + ); + NAND2_X1_LVT i_1_0_1362( + .A1(n_1_0_1309), .A2(Rs1[1]), .ZN(n_1_0_1298) + ); + NOR2_X1_LVT i_1_0_1359( + .A1(n_1_0_1298), .A2(n_1_0_1296), .ZN(n_1_0_1295) + ); + NAND2_X1_LVT i_0_0_72( + .A1(Rd[1]), .A2(Rd[0]), .ZN(n_0_0_11) + ); + OAI21_X1_LVT i_0_0_46( + .A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_2), .ZN(n_0_19) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[19]_reg ( + .CK(clk), .E(n_0_19), .GCK(n_0_49), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[19][31] ( + .CK(n_0_49), .D(registers[31]), .Q(registers_19__ap[31]), .QN(), .SE(dftIn), + .SI(registers_23__ap[31]) + ); + NAND3_X1_LVT i_0_0_67( + .A1(n_0_0_18), .A2(Rd[0]), .A3(Rd[2]), .ZN(n_0_0_8) + ); + OAI21_X1_LVT i_0_0_66( + .A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_8), .ZN(n_0_5) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[5]_reg ( + .CK(clk), .E(n_0_5), .GCK(n_0_35), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[5][31] ( + .CK(n_0_35), .D(registers[31]), .Q(registers_5__ap[31]), .QN(), .SE(dftIn), + .SI(registers_7__ap[31]) + ); + NOR2_X1_LVT i_1_0_1337( + .A1(n_1_0_1284), .A2(n_1_0_1275), .ZN(n_1_0_1273) + ); + AOI221_X1_LVT i_1_0_1318( + .A(n_1_0_1261), .B1(n_1_0_1295), .B2(registers_19__ap[31]), .C1(registers_5__ap[31]), + .C2(n_1_0_1273), .ZN(n_1_0_1254) + ); + NAND2_X1_LVT i_0_0_74( + .A1(n_0_0_17), .A2(Rd[1]), .ZN(n_0_0_12) + ); + NAND3_X1_LVT i_0_0_61( + .A1(n_0_0_19), .A2(WrReg), .A3(Rd[3]), .ZN(n_0_0_5) + ); + OR2_X1_LVT i_0_0_60( + .A1(n_0_0_5), .A2(Rd[2]), .ZN(n_0_0_4) + ); + OAI21_X1_LVT i_0_0_57( + .A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_4), .ZN(n_0_10) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[10]_reg ( + .CK(clk), .E(n_0_10), .GCK(n_0_40), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[10][31] ( + .CK(n_0_40), .D(registers[31]), .Q(registers_10__ap[31]), .QN(), .SE(dftIn), + .SI(registers_16__ap[31]) + ); + NAND3_X1_LVT i_1_0_1352( + .A1(n_1_0_1308), .A2(n_1_0_1306), .A3(Rs1[3]), .ZN(n_1_0_1288) + ); + NOR2_X1_LVT i_1_0_1351( + .A1(n_1_0_1298), .A2(n_1_0_1288), .ZN(n_1_0_1287) + ); + NOR2_X1_LVT i_1_0_1349( + .A1(n_1_0_1298), .A2(n_1_0_1290), .ZN(n_1_0_1285) + ); + OR2_X1_LVT i_0_0_40( + .A1(n_0_0_1), .A2(Rd[2]), .ZN(n_0_0_0) + ); + OAI21_X1_LVT i_0_0_37( + .A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_0), .ZN(n_0_26) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[26]_reg ( + .CK(clk), .E(n_0_26), .GCK(n_0_56), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[26][31] ( + .CK(n_0_56), .D(registers[31]), .Q(registers_26__ap[31]), .QN(), .SE(dftIn), + .SI(registers_28__ap[31]) + ); + OAI21_X1_LVT i_0_0_59( + .A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_4), .ZN(n_0_8) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[8]_reg ( + .CK(clk), .E(n_0_8), .GCK(n_0_38), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[8][31] ( + .CK(n_0_38), .D(registers[31]), .Q(registers_8__ap[31]), .QN(), .SE(dftIn), + .SI(registers_5__ap[31]) + ); + NOR2_X1_LVT i_1_0_1346( + .A1(n_1_0_1293), .A2(n_1_0_1288), .ZN(n_1_0_1282) + ); + AOI222_X1_LVT i_1_0_1317( + .A1(registers_10__ap[31]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[31]), + .C1(registers_8__ap[31]), .C2(n_1_0_1282), .ZN(n_1_0_1253) + ); + NAND4_X1_LVT i_1_0_1316( + .A1(n_1_0_1265), .A2(n_1_0_1255), .A3(n_1_0_1254), .A4(n_1_0_1253), .ZN(n_1_0_1252) + ); + NAND3_X1_LVT i_1_0_1356( + .A1(n_1_0_1308), .A2(Rs1[3]), .A3(Rs1[0]), .ZN(n_1_0_1292) + ); + NOR2_X1_LVT i_1_0_1355( + .A1(n_1_0_1293), .A2(n_1_0_1292), .ZN(n_1_0_1291) + ); + OAI21_X1_LVT i_0_0_58( + .A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_4), .ZN(n_0_9) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[9]_reg ( + .CK(clk), .E(n_0_9), .GCK(n_0_39), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[9][31] ( + .CK(n_0_39), .D(registers[31]), .Q(registers_9__ap[31]), .QN(), .SE(dftIn), + .SI(registers_8__ap[31]) + ); + OAI21_X1_LVT i_0_0_34( + .A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_1), .ZN(n_0_29) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[29]_reg ( + .CK(clk), .E(n_0_29), .GCK(n_0_59), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[29][31] ( + .CK(n_0_59), .D(registers[31]), .Q(registers_29__ap[31]), .QN(), .SE(dftIn), + .SI(registers_26__ap[31]) + ); + NOR2_X1_LVT i_1_0_1340( + .A1(n_1_0_1284), .A2(n_1_0_1280), .ZN(n_1_0_1276) + ); + AOI221_X1_LVT i_1_0_1315( + .A(n_1_0_1252), .B1(n_1_0_1291), .B2(registers_9__ap[31]), .C1(registers_29__ap[31]), + .C2(n_1_0_1276), .ZN(n_1_0_1251) + ); + OAI21_X1_LVT i_0_0_47( + .A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_2), .ZN(n_0_18) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[18]_reg ( + .CK(clk), .E(n_0_18), .GCK(n_0_48), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[18][31] ( + .CK(n_0_48), .D(registers[31]), .Q(registers_18__ap[31]), .QN(), .SE(dftIn), + .SI(registers_19__ap[31]) + ); + NOR2_X1_LVT i_1_0_1361( + .A1(n_1_0_1299), .A2(n_1_0_1298), .ZN(n_1_0_1297) + ); + NOR2_X1_LVT i_1_0_1336( + .A1(n_1_0_1301), .A2(n_1_0_1290), .ZN(n_1_0_1272) + ); + OAI21_X1_LVT i_0_0_33( + .A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_1), .ZN(n_0_30) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[30]_reg ( + .CK(clk), .E(n_0_30), .GCK(n_0_60), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[30][31] ( + .CK(n_0_60), .D(registers[31]), .Q(registers_30__ap[31]), .QN(), .SE(dftIn), + .SI(registers_29__ap[31]) + ); + AOI22_X1_LVT i_1_0_1314( + .A1(registers_18__ap[31]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[31]), + .ZN(n_1_0_1250) + ); + OAI21_X1_LVT i_0_0_39( + .A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_0), .ZN(n_0_24) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[24]_reg ( + .CK(clk), .E(n_0_24), .GCK(n_0_54), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[24][31] ( + .CK(n_0_54), .D(registers[31]), .Q(registers_24__ap[31]), .QN(), .SE(dftIn), + .SI(registers_30__ap[31]) + ); + NOR2_X1_LVT i_1_0_1353( + .A1(n_1_0_1293), .A2(n_1_0_1290), .ZN(n_1_0_1289) + ); + NOR2_X1_LVT i_1_0_1324( + .A1(n_1_0_1288), .A2(n_1_0_1284), .ZN(n_1_0_1260) + ); + OAI21_X1_LVT i_0_0_55( + .A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_5), .ZN(n_0_12) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[12]_reg ( + .CK(clk), .E(n_0_12), .GCK(n_0_42), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[12][31] ( + .CK(n_0_42), .D(registers[31]), .Q(registers_12__ap[31]), .QN(), .SE(dftIn), + .SI(registers_10__ap[31]) + ); + AOI22_X1_LVT i_1_0_1313( + .A1(registers_24__ap[31]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[31]), + .ZN(n_1_0_1249) + ); + OAI21_X1_LVT i_0_0_43( + .A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_3), .ZN(n_0_22) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[22]_reg ( + .CK(clk), .E(n_0_22), .GCK(n_0_52), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[22][31] ( + .CK(n_0_52), .D(registers[31]), .Q(registers_22__ap[31]), .QN(), .SE(dftIn), + .SI(registers_18__ap[31]) + ); + NOR2_X1_LVT i_1_0_1358( + .A1(n_1_0_1301), .A2(n_1_0_1299), .ZN(n_1_0_1294) + ); + NOR2_X1_LVT i_1_0_1323( + .A1(n_1_0_1296), .A2(n_1_0_1284), .ZN(n_1_0_1259) + ); + OAI21_X1_LVT i_0_0_44( + .A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_3), .ZN(n_0_21) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[21]_reg ( + .CK(clk), .E(n_0_21), .GCK(n_0_51), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[21][31] ( + .CK(n_0_51), .D(registers[31]), .Q(registers_21__ap[31]), .QN(), .SE(dftIn), + .SI(registers_22__ap[31]) + ); + AOI22_X1_LVT i_1_0_1312( + .A1(registers_22__ap[31]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[31]), + .ZN(n_1_0_1248) + ); + NAND3_X1_LVT i_1_0_1311( + .A1(n_1_0_1250), .A2(n_1_0_1249), .A3(n_1_0_1248), .ZN(n_1_0_1247) + ); + NOR2_X1_LVT i_1_0_1335( + .A1(n_1_0_1296), .A2(n_1_0_1293), .ZN(n_1_0_1271) + ); + OAI21_X1_LVT i_0_0_48( + .A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_2), .ZN(n_0_17) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[17]_reg ( + .CK(clk), .E(n_0_17), .GCK(n_0_47), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[17][31] ( + .CK(n_0_47), .D(registers[31]), .Q(registers_17__ap[31]), .QN(), .SE(dftIn), + .SI(registers_21__ap[31]) + ); + OAI21_X1_LVT i_0_0_45( + .A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_3), .ZN(n_0_20) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[20]_reg ( + .CK(clk), .E(n_0_20), .GCK(n_0_50), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[20][31] ( + .CK(n_0_50), .D(registers[31]), .Q(registers_20__ap[31]), .QN(), .SE(dftIn), + .SI(registers_17__ap[31]) + ); + NOR2_X1_LVT i_1_0_1345( + .A1(n_1_0_1299), .A2(n_1_0_1284), .ZN(n_1_0_1281) + ); + AOI221_X1_LVT i_1_0_1310( + .A(n_1_0_1247), .B1(n_1_0_1271), .B2(registers_17__ap[31]), .C1(registers_20__ap[31]), + .C2(n_1_0_1281), .ZN(n_1_0_1246) + ); + OAI21_X1_LVT i_0_0_36( + .A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_0), .ZN(n_0_27) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[27]_reg ( + .CK(clk), .E(n_0_27), .GCK(n_0_57), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[27][31] ( + .CK(n_0_57), .D(registers[31]), .Q(registers_27__ap[31]), .QN(), .SE(dftIn), + .SI(registers_24__ap[31]) + ); + NOR2_X1_LVT i_1_0_1343( + .A1(n_1_0_1298), .A2(n_1_0_1280), .ZN(n_1_0_1279) + ); + NOR2_X1_LVT i_1_0_1334( + .A1(n_1_0_1298), .A2(n_1_0_1292), .ZN(n_1_0_1270) + ); + OAI21_X1_LVT i_0_0_56( + .A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_4), .ZN(n_0_11) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[11]_reg ( + .CK(clk), .E(n_0_11), .GCK(n_0_41), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[11][31] ( + .CK(n_0_41), .D(registers[31]), .Q(registers_11__ap[31]), .QN(), .SE(dftIn), + .SI(registers_12__ap[31]) + ); + AOI22_X1_LVT i_1_0_1309( + .A1(registers_27__ap[31]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[31]), + .ZN(n_1_0_1245) + ); + OAI21_X1_LVT i_0_0_54( + .A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_5), .ZN(n_0_13) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[13]_reg ( + .CK(clk), .E(n_0_13), .GCK(n_0_43), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[13][31] ( + .CK(n_0_43), .D(registers[31]), .Q(registers_13__ap[31]), .QN(), .SE(dftIn), + .SI(registers_11__ap[31]) + ); + NOR2_X1_LVT i_1_0_1341( + .A1(n_1_0_1292), .A2(n_1_0_1284), .ZN(n_1_0_1277) + ); + NOR2_X1_LVT i_1_0_1333( + .A1(n_1_0_1293), .A2(n_1_0_1280), .ZN(n_1_0_1269) + ); + OAI21_X1_LVT i_0_0_38( + .A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_0), .ZN(n_0_25) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[25]_reg ( + .CK(clk), .E(n_0_25), .GCK(n_0_55), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[25][31] ( + .CK(n_0_55), .D(registers[31]), .Q(registers_25__ap[31]), .QN(), .SE(dftIn), + .SI(registers_27__ap[31]) + ); + AOI22_X1_LVT i_1_0_1308( + .A1(registers_13__ap[31]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[31]), + .ZN(n_1_0_1244) + ); + OAI21_X1_LVT i_0_0_52( + .A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_5), .ZN(n_0_15) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[15]_reg ( + .CK(clk), .E(n_0_15), .GCK(n_0_45), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[15][31] ( + .CK(n_0_45), .D(registers[31]), .Q(registers_15__ap[31]), .QN(), .SE(dftIn), + .SI(registers_13__ap[31]) + ); + NOR2_X1_LVT i_1_0_1350( + .A1(n_1_0_1301), .A2(n_1_0_1292), .ZN(n_1_0_1286) + ); + NOR2_X1_LVT i_1_0_1322( + .A1(n_1_0_1301), .A2(n_1_0_1288), .ZN(n_1_0_1258) + ); + OAI21_X1_LVT i_0_0_53( + .A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_5), .ZN(n_0_14) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[14]_reg ( + .CK(clk), .E(n_0_14), .GCK(n_0_44), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[14][31] ( + .CK(n_0_44), .D(registers[31]), .Q(registers_14__ap[31]), .QN(), .SE(dftIn), + .SI(registers_15__ap[31]) + ); + AOI22_X1_LVT i_1_0_1307( + .A1(registers_15__ap[31]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[31]), + .ZN(n_1_0_1243) + ); + NAND3_X1_LVT i_1_0_1306( + .A1(n_1_0_1245), .A2(n_1_0_1244), .A3(n_1_0_1243), .ZN(n_1_0_1242) + ); + NOR2_X1_LVT i_1_0_1321( + .A1(n_1_0_1298), .A2(n_1_0_1275), .ZN(n_1_0_1257) + ); + OAI21_X1_LVT i_0_0_71( + .A(n_0_0_16), .B1(n_0_0_13), .B2(n_0_0_11), .ZN(n_0_3) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[3]_reg ( + .CK(clk), .E(n_0_3), .GCK(n_0_33), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[3][31] ( + .CK(n_0_33), .D(registers[31]), .Q(registers_3__ap[31]), .QN(), .SE(dftIn), + .SI(registers_9__ap[31]) + ); + OAI21_X1_LVT i_0_0_73( + .A(n_0_0_16), .B1(n_0_0_13), .B2(n_0_0_12), .ZN(n_0_2) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[2]_reg ( + .CK(clk), .E(n_0_2), .GCK(n_0_32), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[2][31] ( + .CK(n_0_32), .D(registers[31]), .Q(registers_2__ap[31]), .QN(), .SE(dftIn), + .SI(registers_25__ap[31]) + ); + NOR4_X1_LVT i_1_0_1332( + .A1(n_1_0_1298), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), .ZN(n_1_0_1268) + ); + AOI221_X1_LVT i_1_0_1305( + .A(n_1_0_1242), .B1(n_1_0_1257), .B2(registers_3__ap[31]), .C1(registers_2__ap[31]), + .C2(n_1_0_1268), .ZN(n_1_0_1241) + ); + NAND4_X1_LVT i_1_0_1304( + .A1(n_1_0_1256), .A2(n_1_0_1251), .A3(n_1_0_1246), .A4(n_1_0_1241), .ZN(RRs1[31]) + ); + AND2_X1_LVT i_0_0_30( + .A1(n_0_0_16), .A2(WRd[30]), .ZN(registers[30]) + ); + SDFF_X1_LVT \registers_reg[28][30] ( + .CK(n_0_58), .D(registers[30]), .Q(registers_28__ap[30]), .QN(), .SE(dftIn), + .SI(registers_2__ap[31]) + ); + SDFF_X1_LVT \registers_reg[17][30] ( + .CK(n_0_47), .D(registers[30]), .Q(registers_17__ap[30]), .QN(), .SE(dftIn), + .SI(registers_20__ap[31]) + ); + AOI22_X1_LVT i_1_0_1300( + .A1(registers_28__ap[30]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[30]), + .ZN(n_1_0_1237) + ); + SDFF_X1_LVT \registers_reg[16][30] ( + .CK(n_0_46), .D(registers[30]), .Q(registers_16__ap[30]), .QN(), .SE(dftIn), + .SI(registers_14__ap[31]) + ); + SDFF_X1_LVT \registers_reg[31][30] ( + .CK(n_0_61), .D(registers[30]), .Q(registers_31__ap[30]), .QN(), .SE(dftIn), + .SI(registers_3__ap[31]) + ); + AOI22_X1_LVT i_1_0_1303( + .A1(registers_16__ap[30]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[30]), + .ZN(n_1_0_1240) + ); + SDFF_X1_LVT \registers_reg[6][30] ( + .CK(n_0_36), .D(registers[30]), .Q(registers_6__ap[30]), .QN(), .SE(dftIn), + .SI(registers_31__ap[30]) + ); + SDFF_X1_LVT \registers_reg[1][30] ( + .CK(n_0_0), .D(registers[30]), .Q(registers_1__ap[30]), .QN(), .SE(dftIn), + .SI(registers_17__ap[30]) + ); + AOI22_X1_LVT i_1_0_1299( + .A1(registers_6__ap[30]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[30]), + .ZN(n_1_0_1236) + ); + SDFF_X1_LVT \registers_reg[23][30] ( + .CK(n_0_53), .D(registers[30]), .Q(registers_23__ap[30]), .QN(), .SE(dftIn), + .SI(registers_1__ap[30]) + ); + SDFF_X1_LVT \registers_reg[7][30] ( + .CK(n_0_37), .D(registers[30]), .Q(registers_7__ap[30]), .QN(), .SE(dftIn), + .SI(registers_6__ap[30]) + ); + AOI22_X1_LVT i_1_0_1302( + .A1(registers_23__ap[30]), .A2(n_1_0_1264), .B1(n_1_0_1263), .B2(registers_7__ap[30]), + .ZN(n_1_0_1239) + ); + INV_X1_LVT i_1_0_1301( + .A(n_1_0_1239), .ZN(n_1_0_1238) + ); + SDFF_X1_LVT \registers_reg[19][30] ( + .CK(n_0_49), .D(registers[30]), .Q(registers_19__ap[30]), .QN(), .SE(dftIn), + .SI(registers_23__ap[30]) + ); + SDFF_X1_LVT \registers_reg[5][30] ( + .CK(n_0_35), .D(registers[30]), .Q(registers_5__ap[30]), .QN(), .SE(dftIn), + .SI(registers_7__ap[30]) + ); + AOI221_X1_LVT i_1_0_1298( + .A(n_1_0_1238), .B1(n_1_0_1295), .B2(registers_19__ap[30]), .C1(registers_5__ap[30]), + .C2(n_1_0_1273), .ZN(n_1_0_1235) + ); + SDFF_X1_LVT \registers_reg[10][30] ( + .CK(n_0_40), .D(registers[30]), .Q(registers_10__ap[30]), .QN(), .SE(dftIn), + .SI(registers_16__ap[30]) + ); + SDFF_X1_LVT \registers_reg[26][30] ( + .CK(n_0_56), .D(registers[30]), .Q(registers_26__ap[30]), .QN(), .SE(dftIn), + .SI(registers_28__ap[30]) + ); + SDFF_X1_LVT \registers_reg[8][30] ( + .CK(n_0_38), .D(registers[30]), .Q(registers_8__ap[30]), .QN(), .SE(dftIn), + .SI(registers_5__ap[30]) + ); + AOI222_X1_LVT i_1_0_1297( + .A1(registers_10__ap[30]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[30]), + .C1(registers_8__ap[30]), .C2(n_1_0_1282), .ZN(n_1_0_1234) + ); + NAND4_X1_LVT i_1_0_1296( + .A1(n_1_0_1240), .A2(n_1_0_1236), .A3(n_1_0_1235), .A4(n_1_0_1234), .ZN(n_1_0_1233) + ); + SDFF_X1_LVT \registers_reg[9][30] ( + .CK(n_0_39), .D(registers[30]), .Q(registers_9__ap[30]), .QN(), .SE(dftIn), + .SI(registers_8__ap[30]) + ); + SDFF_X1_LVT \registers_reg[29][30] ( + .CK(n_0_59), .D(registers[30]), .Q(registers_29__ap[30]), .QN(), .SE(dftIn), + .SI(registers_26__ap[30]) + ); + AOI221_X1_LVT i_1_0_1295( + .A(n_1_0_1233), .B1(n_1_0_1291), .B2(registers_9__ap[30]), .C1(registers_29__ap[30]), + .C2(n_1_0_1276), .ZN(n_1_0_1232) + ); + SDFF_X1_LVT \registers_reg[18][30] ( + .CK(n_0_48), .D(registers[30]), .Q(registers_18__ap[30]), .QN(), .SE(dftIn), + .SI(registers_19__ap[30]) + ); + SDFF_X1_LVT \registers_reg[30][30] ( + .CK(n_0_60), .D(registers[30]), .Q(registers_30__ap[30]), .QN(), .SE(dftIn), + .SI(registers_29__ap[30]) + ); + AOI22_X1_LVT i_1_0_1294( + .A1(registers_18__ap[30]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[30]), + .ZN(n_1_0_1231) + ); + SDFF_X1_LVT \registers_reg[20][30] ( + .CK(n_0_50), .D(registers[30]), .Q(registers_20__ap[30]), .QN(), .SE(dftIn), + .SI(registers_18__ap[30]) + ); + SDFF_X1_LVT \registers_reg[4][30] ( + .CK(n_0_34), .D(registers[30]), .Q(registers_4__ap[30]), .QN(), .SE(dftIn), + .SI(registers_9__ap[30]) + ); + AOI22_X1_LVT i_1_0_1293( + .A1(registers_20__ap[30]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[30]), + .ZN(n_1_0_1230) + ); + SDFF_X1_LVT \registers_reg[22][30] ( + .CK(n_0_52), .D(registers[30]), .Q(registers_22__ap[30]), .QN(), .SE(dftIn), + .SI(registers_20__ap[30]) + ); + SDFF_X1_LVT \registers_reg[21][30] ( + .CK(n_0_51), .D(registers[30]), .Q(registers_21__ap[30]), .QN(), .SE(dftIn), + .SI(registers_22__ap[30]) + ); + AOI22_X1_LVT i_1_0_1292( + .A1(registers_22__ap[30]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[30]), + .ZN(n_1_0_1229) + ); + NAND3_X1_LVT i_1_0_1291( + .A1(n_1_0_1231), .A2(n_1_0_1230), .A3(n_1_0_1229), .ZN(n_1_0_1228) + ); + SDFF_X1_LVT \registers_reg[24][30] ( + .CK(n_0_54), .D(registers[30]), .Q(registers_24__ap[30]), .QN(), .SE(dftIn), + .SI(registers_30__ap[30]) + ); + SDFF_X1_LVT \registers_reg[12][30] ( + .CK(n_0_42), .D(registers[30]), .Q(registers_12__ap[30]), .QN(), .SE(dftIn), + .SI(registers_10__ap[30]) + ); + AOI221_X1_LVT i_1_0_1290( + .A(n_1_0_1228), .B1(n_1_0_1289), .B2(registers_24__ap[30]), .C1(registers_12__ap[30]), + .C2(n_1_0_1260), .ZN(n_1_0_1227) + ); + SDFF_X1_LVT \registers_reg[27][30] ( + .CK(n_0_57), .D(registers[30]), .Q(registers_27__ap[30]), .QN(), .SE(dftIn), + .SI(registers_24__ap[30]) + ); + SDFF_X1_LVT \registers_reg[11][30] ( + .CK(n_0_41), .D(registers[30]), .Q(registers_11__ap[30]), .QN(), .SE(dftIn), + .SI(registers_12__ap[30]) + ); + AOI22_X1_LVT i_1_0_1289( + .A1(registers_27__ap[30]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[30]), + .ZN(n_1_0_1226) + ); + SDFF_X1_LVT \registers_reg[13][30] ( + .CK(n_0_43), .D(registers[30]), .Q(registers_13__ap[30]), .QN(), .SE(dftIn), + .SI(registers_11__ap[30]) + ); + SDFF_X1_LVT \registers_reg[25][30] ( + .CK(n_0_55), .D(registers[30]), .Q(registers_25__ap[30]), .QN(), .SE(dftIn), + .SI(registers_27__ap[30]) + ); + AOI22_X1_LVT i_1_0_1288( + .A1(registers_13__ap[30]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[30]), + .ZN(n_1_0_1225) + ); + SDFF_X1_LVT \registers_reg[15][30] ( + .CK(n_0_45), .D(registers[30]), .Q(registers_15__ap[30]), .QN(), .SE(dftIn), + .SI(registers_13__ap[30]) + ); + SDFF_X1_LVT \registers_reg[14][30] ( + .CK(n_0_44), .D(registers[30]), .Q(registers_14__ap[30]), .QN(), .SE(dftIn), + .SI(registers_15__ap[30]) + ); + AOI22_X1_LVT i_1_0_1287( + .A1(registers_15__ap[30]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[30]), + .ZN(n_1_0_1224) + ); + NAND3_X1_LVT i_1_0_1286( + .A1(n_1_0_1226), .A2(n_1_0_1225), .A3(n_1_0_1224), .ZN(n_1_0_1223) + ); + SDFF_X1_LVT \registers_reg[3][30] ( + .CK(n_0_33), .D(registers[30]), .Q(registers_3__ap[30]), .QN(), .SE(dftIn), + .SI(registers_4__ap[30]) + ); + SDFF_X1_LVT \registers_reg[2][30] ( + .CK(n_0_32), .D(registers[30]), .Q(registers_2__ap[30]), .QN(), .SE(dftIn), + .SI(registers_25__ap[30]) + ); + AOI221_X1_LVT i_1_0_1285( + .A(n_1_0_1223), .B1(n_1_0_1257), .B2(registers_3__ap[30]), .C1(registers_2__ap[30]), + .C2(n_1_0_1268), .ZN(n_1_0_1222) + ); + NAND4_X1_LVT i_1_0_1284( + .A1(n_1_0_1237), .A2(n_1_0_1232), .A3(n_1_0_1227), .A4(n_1_0_1222), .ZN(RRs1[30]) + ); + AND2_X1_LVT i_0_0_29( + .A1(n_0_0_16), .A2(WRd[29]), .ZN(registers[29]) + ); + SDFF_X1_LVT \registers_reg[28][29] ( + .CK(n_0_58), .D(registers[29]), .Q(registers_28__ap[29]), .QN(), .SE(dftIn), + .SI(registers_2__ap[30]) + ); + SDFF_X1_LVT \registers_reg[8][29] ( + .CK(n_0_38), .D(registers[29]), .Q(registers_8__ap[29]), .QN(), .SE(dftIn), + .SI(registers_3__ap[30]) + ); + AOI22_X1_LVT i_1_0_1282( + .A1(registers_28__ap[29]), .A2(n_1_0_1283), .B1(n_1_0_1282), .B2(registers_8__ap[29]), + .ZN(n_1_0_1220) + ); + SDFF_X1_LVT \registers_reg[31][29] ( + .CK(n_0_61), .D(registers[29]), .Q(registers_31__ap[29]), .QN(), .SE(dftIn), + .SI(registers_8__ap[29]) + ); + SDFF_X1_LVT \registers_reg[7][29] ( + .CK(n_0_37), .D(registers[29]), .Q(registers_7__ap[29]), .QN(), .SE(dftIn), + .SI(registers_31__ap[29]) + ); + AOI22_X1_LVT i_1_0_1283( + .A1(registers_31__ap[29]), .A2(n_1_0_1266), .B1(n_1_0_1263), .B2(registers_7__ap[29]), + .ZN(n_1_0_1221) + ); + SDFF_X1_LVT \registers_reg[24][29] ( + .CK(n_0_54), .D(registers[29]), .Q(registers_24__ap[29]), .QN(), .SE(dftIn), + .SI(registers_28__ap[29]) + ); + SDFF_X1_LVT \registers_reg[20][29] ( + .CK(n_0_50), .D(registers[29]), .Q(registers_20__ap[29]), .QN(), .SE(dftIn), + .SI(registers_21__ap[30]) + ); + AOI22_X1_LVT i_1_0_1281( + .A1(registers_24__ap[29]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[29]), + .ZN(n_1_0_1219) + ); + SDFF_X1_LVT \registers_reg[19][29] ( + .CK(n_0_49), .D(registers[29]), .Q(registers_19__ap[29]), .QN(), .SE(dftIn), + .SI(registers_20__ap[29]) + ); + SDFF_X1_LVT \registers_reg[4][29] ( + .CK(n_0_34), .D(registers[29]), .Q(registers_4__ap[29]), .QN(), .SE(dftIn), + .SI(registers_7__ap[29]) + ); + AOI22_X1_LVT i_1_0_1280( + .A1(registers_19__ap[29]), .A2(n_1_0_1295), .B1(n_1_0_1278), .B2(registers_4__ap[29]), + .ZN(n_1_0_1218) + ); + NAND3_X1_LVT i_1_0_1279( + .A1(n_1_0_1221), .A2(n_1_0_1219), .A3(n_1_0_1218), .ZN(n_1_0_1217) + ); + SDFF_X1_LVT \registers_reg[23][29] ( + .CK(n_0_53), .D(registers[29]), .Q(registers_23__ap[29]), .QN(), .SE(dftIn), + .SI(registers_19__ap[29]) + ); + SDFF_X1_LVT \registers_reg[29][29] ( + .CK(n_0_59), .D(registers[29]), .Q(registers_29__ap[29]), .QN(), .SE(dftIn), + .SI(registers_24__ap[29]) + ); + AOI221_X1_LVT i_1_0_1278( + .A(n_1_0_1217), .B1(n_1_0_1264), .B2(registers_23__ap[29]), .C1(registers_29__ap[29]), + .C2(n_1_0_1276), .ZN(n_1_0_1216) + ); + SDFF_X1_LVT \registers_reg[10][29] ( + .CK(n_0_40), .D(registers[29]), .Q(registers_10__ap[29]), .QN(), .SE(dftIn), + .SI(registers_14__ap[30]) + ); + SDFF_X1_LVT \registers_reg[26][29] ( + .CK(n_0_56), .D(registers[29]), .Q(registers_26__ap[29]), .QN(), .SE(dftIn), + .SI(registers_29__ap[29]) + ); + SDFF_X1_LVT \registers_reg[25][29] ( + .CK(n_0_55), .D(registers[29]), .Q(registers_25__ap[29]), .QN(), .SE(dftIn), + .SI(registers_26__ap[29]) + ); + AOI222_X1_LVT i_1_0_1277( + .A1(registers_10__ap[29]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[29]), + .C1(registers_25__ap[29]), .C2(n_1_0_1269), .ZN(n_1_0_1215) + ); + NAND3_X1_LVT i_1_0_1276( + .A1(n_1_0_1220), .A2(n_1_0_1216), .A3(n_1_0_1215), .ZN(n_1_0_1214) + ); + SDFF_X1_LVT \registers_reg[21][29] ( + .CK(n_0_51), .D(registers[29]), .Q(registers_21__ap[29]), .QN(), .SE(dftIn), + .SI(registers_23__ap[29]) + ); + SDFF_X1_LVT \registers_reg[13][29] ( + .CK(n_0_43), .D(registers[29]), .Q(registers_13__ap[29]), .QN(), .SE(dftIn), + .SI(registers_10__ap[29]) + ); + AOI221_X1_LVT i_1_0_1275( + .A(n_1_0_1214), .B1(n_1_0_1259), .B2(registers_21__ap[29]), .C1(registers_13__ap[29]), + .C2(n_1_0_1277), .ZN(n_1_0_1213) + ); + SDFF_X1_LVT \registers_reg[18][29] ( + .CK(n_0_48), .D(registers[29]), .Q(registers_18__ap[29]), .QN(), .SE(dftIn), + .SI(registers_21__ap[29]) + ); + SDFF_X1_LVT \registers_reg[30][29] ( + .CK(n_0_60), .D(registers[29]), .Q(registers_30__ap[29]), .QN(), .SE(dftIn), + .SI(registers_25__ap[29]) + ); + AOI22_X1_LVT i_1_0_1274( + .A1(registers_18__ap[29]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[29]), + .ZN(n_1_0_1212) + ); + SDFF_X1_LVT \registers_reg[17][29] ( + .CK(n_0_47), .D(registers[29]), .Q(registers_17__ap[29]), .QN(), .SE(dftIn), + .SI(registers_18__ap[29]) + ); + SDFF_X1_LVT \registers_reg[12][29] ( + .CK(n_0_42), .D(registers[29]), .Q(registers_12__ap[29]), .QN(), .SE(dftIn), + .SI(registers_13__ap[29]) + ); + AOI22_X1_LVT i_1_0_1273( + .A1(registers_17__ap[29]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[29]), + .ZN(n_1_0_1211) + ); + SDFF_X1_LVT \registers_reg[15][29] ( + .CK(n_0_45), .D(registers[29]), .Q(registers_15__ap[29]), .QN(), .SE(dftIn), + .SI(registers_12__ap[29]) + ); + SDFF_X1_LVT \registers_reg[16][29] ( + .CK(n_0_46), .D(registers[29]), .Q(registers_16__ap[29]), .QN(), .SE(dftIn), + .SI(registers_15__ap[29]) + ); + AOI22_X1_LVT i_1_0_1272( + .A1(registers_15__ap[29]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[29]), + .ZN(n_1_0_1210) + ); + NAND3_X1_LVT i_1_0_1271( + .A1(n_1_0_1212), .A2(n_1_0_1211), .A3(n_1_0_1210), .ZN(n_1_0_1209) + ); + SDFF_X1_LVT \registers_reg[22][29] ( + .CK(n_0_52), .D(registers[29]), .Q(registers_22__ap[29]), .QN(), .SE(dftIn), + .SI(registers_17__ap[29]) + ); + SDFF_X1_LVT \registers_reg[5][29] ( + .CK(n_0_35), .D(registers[29]), .Q(registers_5__ap[29]), .QN(), .SE(dftIn), + .SI(registers_4__ap[29]) + ); + AOI221_X1_LVT i_1_0_1270( + .A(n_1_0_1209), .B1(n_1_0_1294), .B2(registers_22__ap[29]), .C1(registers_5__ap[29]), + .C2(n_1_0_1273), .ZN(n_1_0_1208) + ); + SDFF_X1_LVT \registers_reg[9][29] ( + .CK(n_0_39), .D(registers[29]), .Q(registers_9__ap[29]), .QN(), .SE(dftIn), + .SI(registers_5__ap[29]) + ); + SDFF_X1_LVT \registers_reg[1][29] ( + .CK(n_0_0), .D(registers[29]), .Q(registers_1__ap[29]), .QN(), .SE(dftIn), + .SI(registers_22__ap[29]) + ); + AOI22_X1_LVT i_1_0_1269( + .A1(registers_9__ap[29]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[29]), + .ZN(n_1_0_1207) + ); + SDFF_X1_LVT \registers_reg[6][29] ( + .CK(n_0_36), .D(registers[29]), .Q(registers_6__ap[29]), .QN(), .SE(dftIn), + .SI(registers_9__ap[29]) + ); + SDFF_X1_LVT \registers_reg[14][29] ( + .CK(n_0_44), .D(registers[29]), .Q(registers_14__ap[29]), .QN(), .SE(dftIn), + .SI(registers_16__ap[29]) + ); + AOI22_X1_LVT i_1_0_1268( + .A1(registers_6__ap[29]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[29]), + .ZN(n_1_0_1206) + ); + SDFF_X1_LVT \registers_reg[27][29] ( + .CK(n_0_57), .D(registers[29]), .Q(registers_27__ap[29]), .QN(), .SE(dftIn), + .SI(registers_30__ap[29]) + ); + SDFF_X1_LVT \registers_reg[11][29] ( + .CK(n_0_41), .D(registers[29]), .Q(registers_11__ap[29]), .QN(), .SE(dftIn), + .SI(registers_14__ap[29]) + ); + AOI22_X1_LVT i_1_0_1267( + .A1(registers_27__ap[29]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[29]), + .ZN(n_1_0_1205) + ); + NAND3_X1_LVT i_1_0_1266( + .A1(n_1_0_1207), .A2(n_1_0_1206), .A3(n_1_0_1205), .ZN(n_1_0_1204) + ); + SDFF_X1_LVT \registers_reg[3][29] ( + .CK(n_0_33), .D(registers[29]), .Q(registers_3__ap[29]), .QN(), .SE(dftIn), + .SI(registers_6__ap[29]) + ); + SDFF_X1_LVT \registers_reg[2][29] ( + .CK(n_0_32), .D(registers[29]), .Q(registers_2__ap[29]), .QN(), .SE(dftIn), + .SI(registers_27__ap[29]) + ); + AOI221_X1_LVT i_1_0_1265( + .A(n_1_0_1204), .B1(n_1_0_1257), .B2(registers_3__ap[29]), .C1(registers_2__ap[29]), + .C2(n_1_0_1268), .ZN(n_1_0_1203) + ); + NAND3_X1_LVT i_1_0_1264( + .A1(n_1_0_1213), .A2(n_1_0_1208), .A3(n_1_0_1203), .ZN(RRs1[29]) + ); + AND2_X1_LVT i_0_0_28( + .A1(n_0_0_16), .A2(WRd[28]), .ZN(registers[28]) + ); + SDFF_X1_LVT \registers_reg[15][28] ( + .CK(n_0_45), .D(registers[28]), .Q(registers_15__ap[28]), .QN(), .SE(dftIn), + .SI(registers_11__ap[29]) + ); + SDFF_X1_LVT \registers_reg[26][28] ( + .CK(n_0_56), .D(registers[28]), .Q(registers_26__ap[28]), .QN(), .SE(dftIn), + .SI(registers_2__ap[29]) + ); + SDFF_X1_LVT \registers_reg[22][28] ( + .CK(n_0_52), .D(registers[28]), .Q(registers_22__ap[28]), .QN(), .SE(dftIn), + .SI(registers_1__ap[29]) + ); + AOI222_X1_LVT i_1_0_1263( + .A1(registers_15__ap[28]), .A2(n_1_0_1286), .B1(n_1_0_1285), .B2(registers_26__ap[28]), + .C1(registers_22__ap[28]), .C2(n_1_0_1294), .ZN(n_1_0_1202) + ); + SDFF_X1_LVT \registers_reg[5][28] ( + .CK(n_0_35), .D(registers[28]), .Q(registers_5__ap[28]), .QN(), .SE(dftIn), + .SI(registers_3__ap[29]) + ); + SDFF_X1_LVT \registers_reg[12][28] ( + .CK(n_0_42), .D(registers[28]), .Q(registers_12__ap[28]), .QN(), .SE(dftIn), + .SI(registers_15__ap[28]) + ); + AOI22_X1_LVT i_1_0_1262( + .A1(registers_5__ap[28]), .A2(n_1_0_1273), .B1(n_1_0_1260), .B2(registers_12__ap[28]), + .ZN(n_1_0_1201) + ); + SDFF_X1_LVT \registers_reg[28][28] ( + .CK(n_0_58), .D(registers[28]), .Q(registers_28__ap[28]), .QN(), .SE(dftIn), + .SI(registers_26__ap[28]) + ); + SDFF_X1_LVT \registers_reg[14][28] ( + .CK(n_0_44), .D(registers[28]), .Q(registers_14__ap[28]), .QN(), .SE(dftIn), + .SI(registers_12__ap[28]) + ); + AOI22_X1_LVT i_1_0_1261( + .A1(registers_28__ap[28]), .A2(n_1_0_1283), .B1(n_1_0_1258), .B2(registers_14__ap[28]), + .ZN(n_1_0_1200) + ); + SDFF_X1_LVT \registers_reg[17][28] ( + .CK(n_0_47), .D(registers[28]), .Q(registers_17__ap[28]), .QN(), .SE(dftIn), + .SI(registers_22__ap[28]) + ); + SDFF_X1_LVT \registers_reg[2][28] ( + .CK(n_0_32), .D(registers[28]), .Q(registers_2__ap[28]), .QN(), .SE(dftIn), + .SI(registers_28__ap[28]) + ); + AOI22_X1_LVT i_1_0_1260( + .A1(registers_17__ap[28]), .A2(n_1_0_1271), .B1(n_1_0_1268), .B2(registers_2__ap[28]), + .ZN(n_1_0_1199) + ); + NAND3_X1_LVT i_1_0_1259( + .A1(n_1_0_1201), .A2(n_1_0_1200), .A3(n_1_0_1199), .ZN(n_1_0_1198) + ); + SDFF_X1_LVT \registers_reg[9][28] ( + .CK(n_0_39), .D(registers[28]), .Q(registers_9__ap[28]), .QN(), .SE(dftIn), + .SI(registers_5__ap[28]) + ); + SDFF_X1_LVT \registers_reg[29][28] ( + .CK(n_0_59), .D(registers[28]), .Q(registers_29__ap[28]), .QN(), .SE(dftIn), + .SI(registers_2__ap[28]) + ); + AOI221_X1_LVT i_1_0_1258( + .A(n_1_0_1198), .B1(n_1_0_1291), .B2(registers_9__ap[28]), .C1(registers_29__ap[28]), + .C2(n_1_0_1276), .ZN(n_1_0_1197) + ); + SDFF_X1_LVT \registers_reg[13][28] ( + .CK(n_0_43), .D(registers[28]), .Q(registers_13__ap[28]), .QN(), .SE(dftIn), + .SI(registers_14__ap[28]) + ); + SDFF_X1_LVT \registers_reg[25][28] ( + .CK(n_0_55), .D(registers[28]), .Q(registers_25__ap[28]), .QN(), .SE(dftIn), + .SI(registers_29__ap[28]) + ); + AOI22_X1_LVT i_1_0_1257( + .A1(registers_13__ap[28]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[28]), + .ZN(n_1_0_1196) + ); + NAND3_X1_LVT i_1_0_1256( + .A1(n_1_0_1202), .A2(n_1_0_1197), .A3(n_1_0_1196), .ZN(n_1_0_1195) + ); + SDFF_X1_LVT \registers_reg[4][28] ( + .CK(n_0_34), .D(registers[28]), .Q(registers_4__ap[28]), .QN(), .SE(dftIn), + .SI(registers_9__ap[28]) + ); + SDFF_X1_LVT \registers_reg[20][28] ( + .CK(n_0_50), .D(registers[28]), .Q(registers_20__ap[28]), .QN(), .SE(dftIn), + .SI(registers_17__ap[28]) + ); + AOI221_X1_LVT i_1_0_1255( + .A(n_1_0_1195), .B1(n_1_0_1278), .B2(registers_4__ap[28]), .C1(registers_20__ap[28]), + .C2(n_1_0_1281), .ZN(n_1_0_1194) + ); + SDFF_X1_LVT \registers_reg[1][28] ( + .CK(n_0_0), .D(registers[28]), .Q(registers_1__ap[28]), .QN(), .SE(dftIn), + .SI(registers_20__ap[28]) + ); + SDFF_X1_LVT \registers_reg[23][28] ( + .CK(n_0_53), .D(registers[28]), .Q(registers_23__ap[28]), .QN(), .SE(dftIn), + .SI(registers_1__ap[28]) + ); + AOI22_X1_LVT i_1_0_1254( + .A1(registers_1__ap[28]), .A2(n_1_0_1274), .B1(n_1_0_1264), .B2(registers_23__ap[28]), + .ZN(n_1_0_1193) + ); + SDFF_X1_LVT \registers_reg[10][28] ( + .CK(n_0_40), .D(registers[28]), .Q(registers_10__ap[28]), .QN(), .SE(dftIn), + .SI(registers_13__ap[28]) + ); + SDFF_X1_LVT \registers_reg[21][28] ( + .CK(n_0_51), .D(registers[28]), .Q(registers_21__ap[28]), .QN(), .SE(dftIn), + .SI(registers_23__ap[28]) + ); + AOI22_X1_LVT i_1_0_1253( + .A1(registers_10__ap[28]), .A2(n_1_0_1287), .B1(n_1_0_1259), .B2(registers_21__ap[28]), + .ZN(n_1_0_1192) + ); + SDFF_X1_LVT \registers_reg[6][28] ( + .CK(n_0_36), .D(registers[28]), .Q(registers_6__ap[28]), .QN(), .SE(dftIn), + .SI(registers_4__ap[28]) + ); + SDFF_X1_LVT \registers_reg[30][28] ( + .CK(n_0_60), .D(registers[28]), .Q(registers_30__ap[28]), .QN(), .SE(dftIn), + .SI(registers_25__ap[28]) + ); + AOI22_X1_LVT i_1_0_1252( + .A1(registers_6__ap[28]), .A2(n_1_0_1300), .B1(n_1_0_1272), .B2(registers_30__ap[28]), + .ZN(n_1_0_1191) + ); + NAND3_X1_LVT i_1_0_1251( + .A1(n_1_0_1193), .A2(n_1_0_1192), .A3(n_1_0_1191), .ZN(n_1_0_1190) + ); + SDFF_X1_LVT \registers_reg[8][28] ( + .CK(n_0_38), .D(registers[28]), .Q(registers_8__ap[28]), .QN(), .SE(dftIn), + .SI(registers_6__ap[28]) + ); + SDFF_X1_LVT \registers_reg[24][28] ( + .CK(n_0_54), .D(registers[28]), .Q(registers_24__ap[28]), .QN(), .SE(dftIn), + .SI(registers_30__ap[28]) + ); + AOI221_X1_LVT i_1_0_1250( + .A(n_1_0_1190), .B1(n_1_0_1282), .B2(registers_8__ap[28]), .C1(registers_24__ap[28]), + .C2(n_1_0_1289), .ZN(n_1_0_1189) + ); + SDFF_X1_LVT \registers_reg[16][28] ( + .CK(n_0_46), .D(registers[28]), .Q(registers_16__ap[28]), .QN(), .SE(dftIn), + .SI(registers_10__ap[28]) + ); + SDFF_X1_LVT \registers_reg[3][28] ( + .CK(n_0_33), .D(registers[28]), .Q(registers_3__ap[28]), .QN(), .SE(dftIn), + .SI(registers_8__ap[28]) + ); + AOI22_X1_LVT i_1_0_1249( + .A1(registers_16__ap[28]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[28]), + .ZN(n_1_0_1188) + ); + SDFF_X1_LVT \registers_reg[11][28] ( + .CK(n_0_41), .D(registers[28]), .Q(registers_11__ap[28]), .QN(), .SE(dftIn), + .SI(registers_16__ap[28]) + ); + SDFF_X1_LVT \registers_reg[31][28] ( + .CK(n_0_61), .D(registers[28]), .Q(registers_31__ap[28]), .QN(), .SE(dftIn), + .SI(registers_3__ap[28]) + ); + AOI22_X1_LVT i_1_0_1248( + .A1(registers_11__ap[28]), .A2(n_1_0_1270), .B1(n_1_0_1266), .B2(registers_31__ap[28]), + .ZN(n_1_0_1187) + ); + SDFF_X1_LVT \registers_reg[27][28] ( + .CK(n_0_57), .D(registers[28]), .Q(registers_27__ap[28]), .QN(), .SE(dftIn), + .SI(registers_24__ap[28]) + ); + SDFF_X1_LVT \registers_reg[7][28] ( + .CK(n_0_37), .D(registers[28]), .Q(registers_7__ap[28]), .QN(), .SE(dftIn), + .SI(registers_31__ap[28]) + ); + AOI22_X1_LVT i_1_0_1247( + .A1(registers_27__ap[28]), .A2(n_1_0_1279), .B1(n_1_0_1263), .B2(registers_7__ap[28]), + .ZN(n_1_0_1186) + ); + NAND3_X1_LVT i_1_0_1246( + .A1(n_1_0_1188), .A2(n_1_0_1187), .A3(n_1_0_1186), .ZN(n_1_0_1185) + ); + SDFF_X1_LVT \registers_reg[19][28] ( + .CK(n_0_49), .D(registers[28]), .Q(registers_19__ap[28]), .QN(), .SE(dftIn), + .SI(registers_21__ap[28]) + ); + SDFF_X1_LVT \registers_reg[18][28] ( + .CK(n_0_48), .D(registers[28]), .Q(registers_18__ap[28]), .QN(), .SE(dftIn), + .SI(registers_19__ap[28]) + ); + AOI221_X1_LVT i_1_0_1245( + .A(n_1_0_1185), .B1(n_1_0_1295), .B2(registers_19__ap[28]), .C1(registers_18__ap[28]), + .C2(n_1_0_1297), .ZN(n_1_0_1184) + ); + NAND3_X1_LVT i_1_0_1244( + .A1(n_1_0_1194), .A2(n_1_0_1189), .A3(n_1_0_1184), .ZN(RRs1[28]) + ); + AND2_X1_LVT i_0_0_27( + .A1(n_0_0_16), .A2(WRd[27]), .ZN(registers[27]) + ); + SDFF_X1_LVT \registers_reg[29][27] ( + .CK(n_0_59), .D(registers[27]), .Q(registers_29__ap[27]), .QN(), .SE(dftIn), + .SI(registers_27__ap[28]) + ); + SDFF_X1_LVT \registers_reg[2][27] ( + .CK(n_0_32), .D(registers[27]), .Q(registers_2__ap[27]), .QN(), .SE(dftIn), + .SI(registers_29__ap[27]) + ); + AOI22_X1_LVT i_1_0_1242( + .A1(registers_29__ap[27]), .A2(n_1_0_1276), .B1(n_1_0_1268), .B2(registers_2__ap[27]), + .ZN(n_1_0_1182) + ); + SDFF_X1_LVT \registers_reg[8][27] ( + .CK(n_0_38), .D(registers[27]), .Q(registers_8__ap[27]), .QN(), .SE(dftIn), + .SI(registers_7__ap[28]) + ); + SDFF_X1_LVT \registers_reg[25][27] ( + .CK(n_0_55), .D(registers[27]), .Q(registers_25__ap[27]), .QN(), .SE(dftIn), + .SI(registers_2__ap[27]) + ); + AOI22_X1_LVT i_1_0_1243( + .A1(registers_8__ap[27]), .A2(n_1_0_1282), .B1(n_1_0_1269), .B2(registers_25__ap[27]), + .ZN(n_1_0_1183) + ); + SDFF_X1_LVT \registers_reg[9][27] ( + .CK(n_0_39), .D(registers[27]), .Q(registers_9__ap[27]), .QN(), .SE(dftIn), + .SI(registers_8__ap[27]) + ); + SDFF_X1_LVT \registers_reg[7][27] ( + .CK(n_0_37), .D(registers[27]), .Q(registers_7__ap[27]), .QN(), .SE(dftIn), + .SI(registers_9__ap[27]) + ); + AOI22_X1_LVT i_1_0_1241( + .A1(registers_9__ap[27]), .A2(n_1_0_1291), .B1(n_1_0_1263), .B2(registers_7__ap[27]), + .ZN(n_1_0_1181) + ); + SDFF_X1_LVT \registers_reg[11][27] ( + .CK(n_0_41), .D(registers[27]), .Q(registers_11__ap[27]), .QN(), .SE(dftIn), + .SI(registers_11__ap[28]) + ); + SDFF_X1_LVT \registers_reg[16][27] ( + .CK(n_0_46), .D(registers[27]), .Q(registers_16__ap[27]), .QN(), .SE(dftIn), + .SI(registers_11__ap[27]) + ); + AOI22_X1_LVT i_1_0_1240( + .A1(registers_11__ap[27]), .A2(n_1_0_1270), .B1(n_1_0_1267), .B2(registers_16__ap[27]), + .ZN(n_1_0_1180) + ); + NAND3_X1_LVT i_1_0_1239( + .A1(n_1_0_1183), .A2(n_1_0_1181), .A3(n_1_0_1180), .ZN(n_1_0_1179) + ); + SDFF_X1_LVT \registers_reg[10][27] ( + .CK(n_0_40), .D(registers[27]), .Q(registers_10__ap[27]), .QN(), .SE(dftIn), + .SI(registers_16__ap[27]) + ); + SDFF_X1_LVT \registers_reg[6][27] ( + .CK(n_0_36), .D(registers[27]), .Q(registers_6__ap[27]), .QN(), .SE(dftIn), + .SI(registers_7__ap[27]) + ); + AOI221_X1_LVT i_1_0_1238( + .A(n_1_0_1179), .B1(n_1_0_1287), .B2(registers_10__ap[27]), .C1(registers_6__ap[27]), + .C2(n_1_0_1300), .ZN(n_1_0_1178) + ); + SDFF_X1_LVT \registers_reg[1][27] ( + .CK(n_0_0), .D(registers[27]), .Q(registers_1__ap[27]), .QN(), .SE(dftIn), + .SI(registers_18__ap[28]) + ); + SDFF_X1_LVT \registers_reg[30][27] ( + .CK(n_0_60), .D(registers[27]), .Q(registers_30__ap[27]), .QN(), .SE(dftIn), + .SI(registers_25__ap[27]) + ); + SDFF_X1_LVT \registers_reg[22][27] ( + .CK(n_0_52), .D(registers[27]), .Q(registers_22__ap[27]), .QN(), .SE(dftIn), + .SI(registers_1__ap[27]) + ); + AOI222_X1_LVT i_1_0_1237( + .A1(registers_1__ap[27]), .A2(n_1_0_1274), .B1(n_1_0_1272), .B2(registers_30__ap[27]), + .C1(registers_22__ap[27]), .C2(n_1_0_1294), .ZN(n_1_0_1177) + ); + NAND3_X1_LVT i_1_0_1236( + .A1(n_1_0_1182), .A2(n_1_0_1178), .A3(n_1_0_1177), .ZN(n_1_0_1176) + ); + SDFF_X1_LVT \registers_reg[5][27] ( + .CK(n_0_35), .D(registers[27]), .Q(registers_5__ap[27]), .QN(), .SE(dftIn), + .SI(registers_6__ap[27]) + ); + SDFF_X1_LVT \registers_reg[28][27] ( + .CK(n_0_58), .D(registers[27]), .Q(registers_28__ap[27]), .QN(), .SE(dftIn), + .SI(registers_30__ap[27]) + ); + AOI221_X1_LVT i_1_0_1235( + .A(n_1_0_1176), .B1(n_1_0_1273), .B2(registers_5__ap[27]), .C1(registers_28__ap[27]), + .C2(n_1_0_1283), .ZN(n_1_0_1175) + ); + SDFF_X1_LVT \registers_reg[4][27] ( + .CK(n_0_34), .D(registers[27]), .Q(registers_4__ap[27]), .QN(), .SE(dftIn), + .SI(registers_5__ap[27]) + ); + SDFF_X1_LVT \registers_reg[12][27] ( + .CK(n_0_42), .D(registers[27]), .Q(registers_12__ap[27]), .QN(), .SE(dftIn), + .SI(registers_10__ap[27]) + ); + AOI22_X1_LVT i_1_0_1234( + .A1(registers_4__ap[27]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[27]), + .ZN(n_1_0_1174) + ); + SDFF_X1_LVT \registers_reg[19][27] ( + .CK(n_0_49), .D(registers[27]), .Q(registers_19__ap[27]), .QN(), .SE(dftIn), + .SI(registers_22__ap[27]) + ); + SDFF_X1_LVT \registers_reg[21][27] ( + .CK(n_0_51), .D(registers[27]), .Q(registers_21__ap[27]), .QN(), .SE(dftIn), + .SI(registers_19__ap[27]) + ); + AOI22_X1_LVT i_1_0_1233( + .A1(registers_19__ap[27]), .A2(n_1_0_1295), .B1(n_1_0_1259), .B2(registers_21__ap[27]), + .ZN(n_1_0_1173) + ); + SDFF_X1_LVT \registers_reg[24][27] ( + .CK(n_0_54), .D(registers[27]), .Q(registers_24__ap[27]), .QN(), .SE(dftIn), + .SI(registers_28__ap[27]) + ); + SDFF_X1_LVT \registers_reg[20][27] ( + .CK(n_0_50), .D(registers[27]), .Q(registers_20__ap[27]), .QN(), .SE(dftIn), + .SI(registers_21__ap[27]) + ); + AOI22_X1_LVT i_1_0_1232( + .A1(registers_24__ap[27]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[27]), + .ZN(n_1_0_1172) + ); + NAND3_X1_LVT i_1_0_1231( + .A1(n_1_0_1174), .A2(n_1_0_1173), .A3(n_1_0_1172), .ZN(n_1_0_1171) + ); + SDFF_X1_LVT \registers_reg[18][27] ( + .CK(n_0_48), .D(registers[27]), .Q(registers_18__ap[27]), .QN(), .SE(dftIn), + .SI(registers_20__ap[27]) + ); + SDFF_X1_LVT \registers_reg[26][27] ( + .CK(n_0_56), .D(registers[27]), .Q(registers_26__ap[27]), .QN(), .SE(dftIn), + .SI(registers_24__ap[27]) + ); + AOI221_X1_LVT i_1_0_1230( + .A(n_1_0_1171), .B1(n_1_0_1297), .B2(registers_18__ap[27]), .C1(registers_26__ap[27]), + .C2(n_1_0_1285), .ZN(n_1_0_1170) + ); + SDFF_X1_LVT \registers_reg[23][27] ( + .CK(n_0_53), .D(registers[27]), .Q(registers_23__ap[27]), .QN(), .SE(dftIn), + .SI(registers_18__ap[27]) + ); + SDFF_X1_LVT \registers_reg[3][27] ( + .CK(n_0_33), .D(registers[27]), .Q(registers_3__ap[27]), .QN(), .SE(dftIn), + .SI(registers_4__ap[27]) + ); + AOI22_X1_LVT i_1_0_1229( + .A1(registers_23__ap[27]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[27]), + .ZN(n_1_0_1169) + ); + SDFF_X1_LVT \registers_reg[13][27] ( + .CK(n_0_43), .D(registers[27]), .Q(registers_13__ap[27]), .QN(), .SE(dftIn), + .SI(registers_12__ap[27]) + ); + SDFF_X1_LVT \registers_reg[17][27] ( + .CK(n_0_47), .D(registers[27]), .Q(registers_17__ap[27]), .QN(), .SE(dftIn), + .SI(registers_23__ap[27]) + ); + AOI22_X1_LVT i_1_0_1228( + .A1(registers_13__ap[27]), .A2(n_1_0_1277), .B1(n_1_0_1271), .B2(registers_17__ap[27]), + .ZN(n_1_0_1168) + ); + SDFF_X1_LVT \registers_reg[15][27] ( + .CK(n_0_45), .D(registers[27]), .Q(registers_15__ap[27]), .QN(), .SE(dftIn), + .SI(registers_13__ap[27]) + ); + SDFF_X1_LVT \registers_reg[14][27] ( + .CK(n_0_44), .D(registers[27]), .Q(registers_14__ap[27]), .QN(), .SE(dftIn), + .SI(registers_15__ap[27]) + ); + AOI22_X1_LVT i_1_0_1227( + .A1(registers_15__ap[27]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[27]), + .ZN(n_1_0_1167) + ); + NAND3_X1_LVT i_1_0_1226( + .A1(n_1_0_1169), .A2(n_1_0_1168), .A3(n_1_0_1167), .ZN(n_1_0_1166) + ); + SDFF_X1_LVT \registers_reg[27][27] ( + .CK(n_0_57), .D(registers[27]), .Q(registers_27__ap[27]), .QN(), .SE(dftIn), + .SI(registers_26__ap[27]) + ); + SDFF_X1_LVT \registers_reg[31][27] ( + .CK(n_0_61), .D(registers[27]), .Q(registers_31__ap[27]), .QN(), .SE(dftIn), + .SI(registers_3__ap[27]) + ); + AOI221_X1_LVT i_1_0_1225( + .A(n_1_0_1166), .B1(n_1_0_1279), .B2(registers_27__ap[27]), .C1(registers_31__ap[27]), + .C2(n_1_0_1266), .ZN(n_1_0_1165) + ); + NAND3_X1_LVT i_1_0_1224( + .A1(n_1_0_1175), .A2(n_1_0_1170), .A3(n_1_0_1165), .ZN(RRs1[27]) + ); + AND2_X1_LVT i_0_0_26( + .A1(n_0_0_16), .A2(WRd[26]), .ZN(registers[26]) + ); + SDFF_X1_LVT \registers_reg[18][26] ( + .CK(n_0_48), .D(registers[26]), .Q(registers_18__ap[26]), .QN(), .SE(dftIn), + .SI(registers_17__ap[27]) + ); + SDFF_X1_LVT \registers_reg[22][26] ( + .CK(n_0_52), .D(registers[26]), .Q(registers_22__ap[26]), .QN(), .SE(dftIn), + .SI(registers_18__ap[26]) + ); + SDFF_X1_LVT \registers_reg[1][26] ( + .CK(n_0_0), .D(registers[26]), .Q(registers_1__ap[26]), .QN(), .SE(dftIn), + .SI(registers_22__ap[26]) + ); + AOI222_X1_LVT i_1_0_1223( + .A1(registers_18__ap[26]), .A2(n_1_0_1297), .B1(n_1_0_1294), .B2(registers_22__ap[26]), + .C1(registers_1__ap[26]), .C2(n_1_0_1274), .ZN(n_1_0_1164) + ); + SDFF_X1_LVT \registers_reg[29][26] ( + .CK(n_0_59), .D(registers[26]), .Q(registers_29__ap[26]), .QN(), .SE(dftIn), + .SI(registers_27__ap[27]) + ); + SDFF_X1_LVT \registers_reg[2][26] ( + .CK(n_0_32), .D(registers[26]), .Q(registers_2__ap[26]), .QN(), .SE(dftIn), + .SI(registers_29__ap[26]) + ); + AOI22_X1_LVT i_1_0_1222( + .A1(registers_29__ap[26]), .A2(n_1_0_1276), .B1(n_1_0_1268), .B2(registers_2__ap[26]), + .ZN(n_1_0_1163) + ); + SDFF_X1_LVT \registers_reg[9][26] ( + .CK(n_0_39), .D(registers[26]), .Q(registers_9__ap[26]), .QN(), .SE(dftIn), + .SI(registers_31__ap[27]) + ); + SDFF_X1_LVT \registers_reg[7][26] ( + .CK(n_0_37), .D(registers[26]), .Q(registers_7__ap[26]), .QN(), .SE(dftIn), + .SI(registers_9__ap[26]) + ); + AOI22_X1_LVT i_1_0_1221( + .A1(registers_9__ap[26]), .A2(n_1_0_1291), .B1(n_1_0_1263), .B2(registers_7__ap[26]), + .ZN(n_1_0_1162) + ); + SDFF_X1_LVT \registers_reg[11][26] ( + .CK(n_0_41), .D(registers[26]), .Q(registers_11__ap[26]), .QN(), .SE(dftIn), + .SI(registers_14__ap[27]) + ); + SDFF_X1_LVT \registers_reg[25][26] ( + .CK(n_0_55), .D(registers[26]), .Q(registers_25__ap[26]), .QN(), .SE(dftIn), + .SI(registers_2__ap[26]) + ); + AOI22_X1_LVT i_1_0_1220( + .A1(registers_11__ap[26]), .A2(n_1_0_1270), .B1(n_1_0_1269), .B2(registers_25__ap[26]), + .ZN(n_1_0_1161) + ); + SDFF_X1_LVT \registers_reg[27][26] ( + .CK(n_0_57), .D(registers[26]), .Q(registers_27__ap[26]), .QN(), .SE(dftIn), + .SI(registers_25__ap[26]) + ); + SDFF_X1_LVT \registers_reg[16][26] ( + .CK(n_0_46), .D(registers[26]), .Q(registers_16__ap[26]), .QN(), .SE(dftIn), + .SI(registers_11__ap[26]) + ); + AOI22_X1_LVT i_1_0_1219( + .A1(registers_27__ap[26]), .A2(n_1_0_1279), .B1(n_1_0_1267), .B2(registers_16__ap[26]), + .ZN(n_1_0_1160) + ); + NAND3_X1_LVT i_1_0_1218( + .A1(n_1_0_1162), .A2(n_1_0_1161), .A3(n_1_0_1160), .ZN(n_1_0_1159) + ); + SDFF_X1_LVT \registers_reg[31][26] ( + .CK(n_0_61), .D(registers[26]), .Q(registers_31__ap[26]), .QN(), .SE(dftIn), + .SI(registers_7__ap[26]) + ); + SDFF_X1_LVT \registers_reg[6][26] ( + .CK(n_0_36), .D(registers[26]), .Q(registers_6__ap[26]), .QN(), .SE(dftIn), + .SI(registers_31__ap[26]) + ); + AOI221_X1_LVT i_1_0_1217( + .A(n_1_0_1159), .B1(n_1_0_1266), .B2(registers_31__ap[26]), .C1(registers_6__ap[26]), + .C2(n_1_0_1300), .ZN(n_1_0_1158) + ); + NAND3_X1_LVT i_1_0_1216( + .A1(n_1_0_1164), .A2(n_1_0_1163), .A3(n_1_0_1158), .ZN(n_1_0_1157) + ); + SDFF_X1_LVT \registers_reg[5][26] ( + .CK(n_0_35), .D(registers[26]), .Q(registers_5__ap[26]), .QN(), .SE(dftIn), + .SI(registers_6__ap[26]) + ); + SDFF_X1_LVT \registers_reg[28][26] ( + .CK(n_0_58), .D(registers[26]), .Q(registers_28__ap[26]), .QN(), .SE(dftIn), + .SI(registers_27__ap[26]) + ); + AOI221_X1_LVT i_1_0_1215( + .A(n_1_0_1157), .B1(n_1_0_1273), .B2(registers_5__ap[26]), .C1(registers_28__ap[26]), + .C2(n_1_0_1283), .ZN(n_1_0_1156) + ); + SDFF_X1_LVT \registers_reg[4][26] ( + .CK(n_0_34), .D(registers[26]), .Q(registers_4__ap[26]), .QN(), .SE(dftIn), + .SI(registers_5__ap[26]) + ); + SDFF_X1_LVT \registers_reg[12][26] ( + .CK(n_0_42), .D(registers[26]), .Q(registers_12__ap[26]), .QN(), .SE(dftIn), + .SI(registers_16__ap[26]) + ); + AOI22_X1_LVT i_1_0_1214( + .A1(registers_4__ap[26]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[26]), + .ZN(n_1_0_1155) + ); + SDFF_X1_LVT \registers_reg[19][26] ( + .CK(n_0_49), .D(registers[26]), .Q(registers_19__ap[26]), .QN(), .SE(dftIn), + .SI(registers_1__ap[26]) + ); + SDFF_X1_LVT \registers_reg[21][26] ( + .CK(n_0_51), .D(registers[26]), .Q(registers_21__ap[26]), .QN(), .SE(dftIn), + .SI(registers_19__ap[26]) + ); + AOI22_X1_LVT i_1_0_1213( + .A1(registers_19__ap[26]), .A2(n_1_0_1295), .B1(n_1_0_1259), .B2(registers_21__ap[26]), + .ZN(n_1_0_1154) + ); + SDFF_X1_LVT \registers_reg[24][26] ( + .CK(n_0_54), .D(registers[26]), .Q(registers_24__ap[26]), .QN(), .SE(dftIn), + .SI(registers_28__ap[26]) + ); + SDFF_X1_LVT \registers_reg[20][26] ( + .CK(n_0_50), .D(registers[26]), .Q(registers_20__ap[26]), .QN(), .SE(dftIn), + .SI(registers_21__ap[26]) + ); + AOI22_X1_LVT i_1_0_1212( + .A1(registers_24__ap[26]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[26]), + .ZN(n_1_0_1153) + ); + NAND3_X1_LVT i_1_0_1211( + .A1(n_1_0_1155), .A2(n_1_0_1154), .A3(n_1_0_1153), .ZN(n_1_0_1152) + ); + SDFF_X1_LVT \registers_reg[26][26] ( + .CK(n_0_56), .D(registers[26]), .Q(registers_26__ap[26]), .QN(), .SE(dftIn), + .SI(registers_24__ap[26]) + ); + SDFF_X1_LVT \registers_reg[30][26] ( + .CK(n_0_60), .D(registers[26]), .Q(registers_30__ap[26]), .QN(), .SE(dftIn), + .SI(registers_26__ap[26]) + ); + AOI221_X1_LVT i_1_0_1210( + .A(n_1_0_1152), .B1(n_1_0_1285), .B2(registers_26__ap[26]), .C1(registers_30__ap[26]), + .C2(n_1_0_1272), .ZN(n_1_0_1151) + ); + SDFF_X1_LVT \registers_reg[8][26] ( + .CK(n_0_38), .D(registers[26]), .Q(registers_8__ap[26]), .QN(), .SE(dftIn), + .SI(registers_4__ap[26]) + ); + SDFF_X1_LVT \registers_reg[23][26] ( + .CK(n_0_53), .D(registers[26]), .Q(registers_23__ap[26]), .QN(), .SE(dftIn), + .SI(registers_20__ap[26]) + ); + AOI22_X1_LVT i_1_0_1209( + .A1(registers_8__ap[26]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[26]), + .ZN(n_1_0_1150) + ); + SDFF_X1_LVT \registers_reg[13][26] ( + .CK(n_0_43), .D(registers[26]), .Q(registers_13__ap[26]), .QN(), .SE(dftIn), + .SI(registers_12__ap[26]) + ); + SDFF_X1_LVT \registers_reg[17][26] ( + .CK(n_0_47), .D(registers[26]), .Q(registers_17__ap[26]), .QN(), .SE(dftIn), + .SI(registers_23__ap[26]) + ); + AOI22_X1_LVT i_1_0_1208( + .A1(registers_13__ap[26]), .A2(n_1_0_1277), .B1(n_1_0_1271), .B2(registers_17__ap[26]), + .ZN(n_1_0_1149) + ); + SDFF_X1_LVT \registers_reg[15][26] ( + .CK(n_0_45), .D(registers[26]), .Q(registers_15__ap[26]), .QN(), .SE(dftIn), + .SI(registers_13__ap[26]) + ); + SDFF_X1_LVT \registers_reg[14][26] ( + .CK(n_0_44), .D(registers[26]), .Q(registers_14__ap[26]), .QN(), .SE(dftIn), + .SI(registers_15__ap[26]) + ); + AOI22_X1_LVT i_1_0_1207( + .A1(registers_15__ap[26]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[26]), + .ZN(n_1_0_1148) + ); + NAND3_X1_LVT i_1_0_1206( + .A1(n_1_0_1150), .A2(n_1_0_1149), .A3(n_1_0_1148), .ZN(n_1_0_1147) + ); + SDFF_X1_LVT \registers_reg[10][26] ( + .CK(n_0_40), .D(registers[26]), .Q(registers_10__ap[26]), .QN(), .SE(dftIn), + .SI(registers_14__ap[26]) + ); + SDFF_X1_LVT \registers_reg[3][26] ( + .CK(n_0_33), .D(registers[26]), .Q(registers_3__ap[26]), .QN(), .SE(dftIn), + .SI(registers_8__ap[26]) + ); + AOI221_X1_LVT i_1_0_1205( + .A(n_1_0_1147), .B1(n_1_0_1287), .B2(registers_10__ap[26]), .C1(registers_3__ap[26]), + .C2(n_1_0_1257), .ZN(n_1_0_1146) + ); + NAND3_X1_LVT i_1_0_1204( + .A1(n_1_0_1156), .A2(n_1_0_1151), .A3(n_1_0_1146), .ZN(RRs1[26]) + ); + AND2_X1_LVT i_0_0_25( + .A1(n_0_0_16), .A2(WRd[25]), .ZN(registers[25]) + ); + SDFF_X1_LVT \registers_reg[17][25] ( + .CK(n_0_47), .D(registers[25]), .Q(registers_17__ap[25]), .QN(), .SE(dftIn), + .SI(registers_17__ap[26]) + ); + SDFF_X1_LVT \registers_reg[21][25] ( + .CK(n_0_51), .D(registers[25]), .Q(registers_21__ap[25]), .QN(), .SE(dftIn), + .SI(registers_17__ap[25]) + ); + AOI22_X1_LVT i_1_0_1202( + .A1(registers_17__ap[25]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[25]), + .ZN(n_1_0_1144) + ); + SDFF_X1_LVT \registers_reg[6][25] ( + .CK(n_0_36), .D(registers[25]), .Q(registers_6__ap[25]), .QN(), .SE(dftIn), + .SI(registers_3__ap[26]) + ); + SDFF_X1_LVT \registers_reg[8][25] ( + .CK(n_0_38), .D(registers[25]), .Q(registers_8__ap[25]), .QN(), .SE(dftIn), + .SI(registers_6__ap[25]) + ); + AOI22_X1_LVT i_1_0_1203( + .A1(registers_6__ap[25]), .A2(n_1_0_1300), .B1(n_1_0_1282), .B2(registers_8__ap[25]), + .ZN(n_1_0_1145) + ); + SDFF_X1_LVT \registers_reg[20][25] ( + .CK(n_0_50), .D(registers[25]), .Q(registers_20__ap[25]), .QN(), .SE(dftIn), + .SI(registers_21__ap[25]) + ); + SDFF_X1_LVT \registers_reg[12][25] ( + .CK(n_0_42), .D(registers[25]), .Q(registers_12__ap[25]), .QN(), .SE(dftIn), + .SI(registers_10__ap[26]) + ); + AOI22_X1_LVT i_1_0_1201( + .A1(registers_20__ap[25]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[25]), + .ZN(n_1_0_1143) + ); + SDFF_X1_LVT \registers_reg[5][25] ( + .CK(n_0_35), .D(registers[25]), .Q(registers_5__ap[25]), .QN(), .SE(dftIn), + .SI(registers_8__ap[25]) + ); + SDFF_X1_LVT \registers_reg[11][25] ( + .CK(n_0_41), .D(registers[25]), .Q(registers_11__ap[25]), .QN(), .SE(dftIn), + .SI(registers_12__ap[25]) + ); + AOI22_X1_LVT i_1_0_1200( + .A1(registers_5__ap[25]), .A2(n_1_0_1273), .B1(n_1_0_1270), .B2(registers_11__ap[25]), + .ZN(n_1_0_1142) + ); + NAND3_X1_LVT i_1_0_1199( + .A1(n_1_0_1145), .A2(n_1_0_1143), .A3(n_1_0_1142), .ZN(n_1_0_1141) + ); + SDFF_X1_LVT \registers_reg[10][25] ( + .CK(n_0_40), .D(registers[25]), .Q(registers_10__ap[25]), .QN(), .SE(dftIn), + .SI(registers_11__ap[25]) + ); + SDFF_X1_LVT \registers_reg[2][25] ( + .CK(n_0_32), .D(registers[25]), .Q(registers_2__ap[25]), .QN(), .SE(dftIn), + .SI(registers_30__ap[26]) + ); + AOI221_X1_LVT i_1_0_1198( + .A(n_1_0_1141), .B1(n_1_0_1287), .B2(registers_10__ap[25]), .C1(registers_2__ap[25]), + .C2(n_1_0_1268), .ZN(n_1_0_1140) + ); + SDFF_X1_LVT \registers_reg[13][25] ( + .CK(n_0_43), .D(registers[25]), .Q(registers_13__ap[25]), .QN(), .SE(dftIn), + .SI(registers_10__ap[25]) + ); + SDFF_X1_LVT \registers_reg[30][25] ( + .CK(n_0_60), .D(registers[25]), .Q(registers_30__ap[25]), .QN(), .SE(dftIn), + .SI(registers_2__ap[25]) + ); + SDFF_X1_LVT \registers_reg[22][25] ( + .CK(n_0_52), .D(registers[25]), .Q(registers_22__ap[25]), .QN(), .SE(dftIn), + .SI(registers_20__ap[25]) + ); + AOI222_X1_LVT i_1_0_1197( + .A1(registers_13__ap[25]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[25]), + .C1(registers_22__ap[25]), .C2(n_1_0_1294), .ZN(n_1_0_1139) + ); + NAND2_X1_LVT i_1_0_1196( + .A1(n_1_0_1140), .A2(n_1_0_1139), .ZN(n_1_0_1138) + ); + SDFF_X1_LVT \registers_reg[1][25] ( + .CK(n_0_0), .D(registers[25]), .Q(registers_1__ap[25]), .QN(), .SE(dftIn), + .SI(registers_22__ap[25]) + ); + SDFF_X1_LVT \registers_reg[28][25] ( + .CK(n_0_58), .D(registers[25]), .Q(registers_28__ap[25]), .QN(), .SE(dftIn), + .SI(registers_30__ap[25]) + ); + AOI221_X1_LVT i_1_0_1195( + .A(n_1_0_1138), .B1(n_1_0_1274), .B2(registers_1__ap[25]), .C1(registers_28__ap[25]), + .C2(n_1_0_1283), .ZN(n_1_0_1137) + ); + SDFF_X1_LVT \registers_reg[18][25] ( + .CK(n_0_48), .D(registers[25]), .Q(registers_18__ap[25]), .QN(), .SE(dftIn), + .SI(registers_1__ap[25]) + ); + SDFF_X1_LVT \registers_reg[26][25] ( + .CK(n_0_56), .D(registers[25]), .Q(registers_26__ap[25]), .QN(), .SE(dftIn), + .SI(registers_28__ap[25]) + ); + AOI22_X1_LVT i_1_0_1194( + .A1(registers_18__ap[25]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[25]), + .ZN(n_1_0_1136) + ); + SDFF_X1_LVT \registers_reg[24][25] ( + .CK(n_0_54), .D(registers[25]), .Q(registers_24__ap[25]), .QN(), .SE(dftIn), + .SI(registers_26__ap[25]) + ); + SDFF_X1_LVT \registers_reg[4][25] ( + .CK(n_0_34), .D(registers[25]), .Q(registers_4__ap[25]), .QN(), .SE(dftIn), + .SI(registers_5__ap[25]) + ); + AOI22_X1_LVT i_1_0_1193( + .A1(registers_24__ap[25]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[25]), + .ZN(n_1_0_1135) + ); + SDFF_X1_LVT \registers_reg[15][25] ( + .CK(n_0_45), .D(registers[25]), .Q(registers_15__ap[25]), .QN(), .SE(dftIn), + .SI(registers_13__ap[25]) + ); + SDFF_X1_LVT \registers_reg[16][25] ( + .CK(n_0_46), .D(registers[25]), .Q(registers_16__ap[25]), .QN(), .SE(dftIn), + .SI(registers_15__ap[25]) + ); + AOI22_X1_LVT i_1_0_1192( + .A1(registers_15__ap[25]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[25]), + .ZN(n_1_0_1134) + ); + NAND3_X1_LVT i_1_0_1191( + .A1(n_1_0_1136), .A2(n_1_0_1135), .A3(n_1_0_1134), .ZN(n_1_0_1133) + ); + SDFF_X1_LVT \registers_reg[19][25] ( + .CK(n_0_49), .D(registers[25]), .Q(registers_19__ap[25]), .QN(), .SE(dftIn), + .SI(registers_18__ap[25]) + ); + SDFF_X1_LVT \registers_reg[25][25] ( + .CK(n_0_55), .D(registers[25]), .Q(registers_25__ap[25]), .QN(), .SE(dftIn), + .SI(registers_24__ap[25]) + ); + AOI221_X1_LVT i_1_0_1190( + .A(n_1_0_1133), .B1(n_1_0_1295), .B2(registers_19__ap[25]), .C1(registers_25__ap[25]), + .C2(n_1_0_1269), .ZN(n_1_0_1132) + ); + SDFF_X1_LVT \registers_reg[7][25] ( + .CK(n_0_37), .D(registers[25]), .Q(registers_7__ap[25]), .QN(), .SE(dftIn), + .SI(registers_4__ap[25]) + ); + SDFF_X1_LVT \registers_reg[14][25] ( + .CK(n_0_44), .D(registers[25]), .Q(registers_14__ap[25]), .QN(), .SE(dftIn), + .SI(registers_16__ap[25]) + ); + AOI22_X1_LVT i_1_0_1189( + .A1(registers_7__ap[25]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[25]), + .ZN(n_1_0_1131) + ); + SDFF_X1_LVT \registers_reg[9][25] ( + .CK(n_0_39), .D(registers[25]), .Q(registers_9__ap[25]), .QN(), .SE(dftIn), + .SI(registers_7__ap[25]) + ); + SDFF_X1_LVT \registers_reg[29][25] ( + .CK(n_0_59), .D(registers[25]), .Q(registers_29__ap[25]), .QN(), .SE(dftIn), + .SI(registers_25__ap[25]) + ); + AOI22_X1_LVT i_1_0_1188( + .A1(registers_9__ap[25]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[25]), + .ZN(n_1_0_1130) + ); + SDFF_X1_LVT \registers_reg[23][25] ( + .CK(n_0_53), .D(registers[25]), .Q(registers_23__ap[25]), .QN(), .SE(dftIn), + .SI(registers_19__ap[25]) + ); + SDFF_X1_LVT \registers_reg[3][25] ( + .CK(n_0_33), .D(registers[25]), .Q(registers_3__ap[25]), .QN(), .SE(dftIn), + .SI(registers_9__ap[25]) + ); + AOI22_X1_LVT i_1_0_1187( + .A1(registers_23__ap[25]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[25]), + .ZN(n_1_0_1129) + ); + NAND3_X1_LVT i_1_0_1186( + .A1(n_1_0_1131), .A2(n_1_0_1130), .A3(n_1_0_1129), .ZN(n_1_0_1128) + ); + SDFF_X1_LVT \registers_reg[27][25] ( + .CK(n_0_57), .D(registers[25]), .Q(registers_27__ap[25]), .QN(), .SE(dftIn), + .SI(registers_29__ap[25]) + ); + SDFF_X1_LVT \registers_reg[31][25] ( + .CK(n_0_61), .D(registers[25]), .Q(registers_31__ap[25]), .QN(), .SE(dftIn), + .SI(registers_3__ap[25]) + ); + AOI221_X1_LVT i_1_0_1185( + .A(n_1_0_1128), .B1(n_1_0_1279), .B2(registers_27__ap[25]), .C1(registers_31__ap[25]), + .C2(n_1_0_1266), .ZN(n_1_0_1127) + ); + NAND4_X1_LVT i_1_0_1184( + .A1(n_1_0_1144), .A2(n_1_0_1137), .A3(n_1_0_1132), .A4(n_1_0_1127), .ZN(RRs1[25]) + ); + AND2_X1_LVT i_0_0_24( + .A1(n_0_0_16), .A2(WRd[24]), .ZN(registers[24]) + ); + SDFF_X1_LVT \registers_reg[17][24] ( + .CK(n_0_47), .D(registers[24]), .Q(registers_17__ap[24]), .QN(), .SE(dftIn), + .SI(registers_23__ap[25]) + ); + SDFF_X1_LVT \registers_reg[21][24] ( + .CK(n_0_51), .D(registers[24]), .Q(registers_21__ap[24]), .QN(), .SE(dftIn), + .SI(registers_17__ap[24]) + ); + AOI22_X1_LVT i_1_0_1182( + .A1(registers_17__ap[24]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[24]), + .ZN(n_1_0_1125) + ); + SDFF_X1_LVT \registers_reg[6][24] ( + .CK(n_0_36), .D(registers[24]), .Q(registers_6__ap[24]), .QN(), .SE(dftIn), + .SI(registers_31__ap[25]) + ); + SDFF_X1_LVT \registers_reg[8][24] ( + .CK(n_0_38), .D(registers[24]), .Q(registers_8__ap[24]), .QN(), .SE(dftIn), + .SI(registers_6__ap[24]) + ); + AOI22_X1_LVT i_1_0_1183( + .A1(registers_6__ap[24]), .A2(n_1_0_1300), .B1(n_1_0_1282), .B2(registers_8__ap[24]), + .ZN(n_1_0_1126) + ); + SDFF_X1_LVT \registers_reg[20][24] ( + .CK(n_0_50), .D(registers[24]), .Q(registers_20__ap[24]), .QN(), .SE(dftIn), + .SI(registers_21__ap[24]) + ); + SDFF_X1_LVT \registers_reg[12][24] ( + .CK(n_0_42), .D(registers[24]), .Q(registers_12__ap[24]), .QN(), .SE(dftIn), + .SI(registers_14__ap[25]) + ); + AOI22_X1_LVT i_1_0_1181( + .A1(registers_20__ap[24]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[24]), + .ZN(n_1_0_1124) + ); + SDFF_X1_LVT \registers_reg[5][24] ( + .CK(n_0_35), .D(registers[24]), .Q(registers_5__ap[24]), .QN(), .SE(dftIn), + .SI(registers_8__ap[24]) + ); + SDFF_X1_LVT \registers_reg[11][24] ( + .CK(n_0_41), .D(registers[24]), .Q(registers_11__ap[24]), .QN(), .SE(dftIn), + .SI(registers_12__ap[24]) + ); + AOI22_X1_LVT i_1_0_1180( + .A1(registers_5__ap[24]), .A2(n_1_0_1273), .B1(n_1_0_1270), .B2(registers_11__ap[24]), + .ZN(n_1_0_1123) + ); + NAND3_X1_LVT i_1_0_1179( + .A1(n_1_0_1126), .A2(n_1_0_1124), .A3(n_1_0_1123), .ZN(n_1_0_1122) + ); + SDFF_X1_LVT \registers_reg[10][24] ( + .CK(n_0_40), .D(registers[24]), .Q(registers_10__ap[24]), .QN(), .SE(dftIn), + .SI(registers_11__ap[24]) + ); + SDFF_X1_LVT \registers_reg[2][24] ( + .CK(n_0_32), .D(registers[24]), .Q(registers_2__ap[24]), .QN(), .SE(dftIn), + .SI(registers_27__ap[25]) + ); + AOI221_X1_LVT i_1_0_1178( + .A(n_1_0_1122), .B1(n_1_0_1287), .B2(registers_10__ap[24]), .C1(registers_2__ap[24]), + .C2(n_1_0_1268), .ZN(n_1_0_1121) + ); + SDFF_X1_LVT \registers_reg[13][24] ( + .CK(n_0_43), .D(registers[24]), .Q(registers_13__ap[24]), .QN(), .SE(dftIn), + .SI(registers_10__ap[24]) + ); + SDFF_X1_LVT \registers_reg[30][24] ( + .CK(n_0_60), .D(registers[24]), .Q(registers_30__ap[24]), .QN(), .SE(dftIn), + .SI(registers_2__ap[24]) + ); + SDFF_X1_LVT \registers_reg[22][24] ( + .CK(n_0_52), .D(registers[24]), .Q(registers_22__ap[24]), .QN(), .SE(dftIn), + .SI(registers_20__ap[24]) + ); + AOI222_X1_LVT i_1_0_1177( + .A1(registers_13__ap[24]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[24]), + .C1(registers_22__ap[24]), .C2(n_1_0_1294), .ZN(n_1_0_1120) + ); + NAND2_X1_LVT i_1_0_1176( + .A1(n_1_0_1121), .A2(n_1_0_1120), .ZN(n_1_0_1119) + ); + SDFF_X1_LVT \registers_reg[1][24] ( + .CK(n_0_0), .D(registers[24]), .Q(registers_1__ap[24]), .QN(), .SE(dftIn), + .SI(registers_22__ap[24]) + ); + SDFF_X1_LVT \registers_reg[28][24] ( + .CK(n_0_58), .D(registers[24]), .Q(registers_28__ap[24]), .QN(), .SE(dftIn), + .SI(registers_30__ap[24]) + ); + AOI221_X1_LVT i_1_0_1175( + .A(n_1_0_1119), .B1(n_1_0_1274), .B2(registers_1__ap[24]), .C1(registers_28__ap[24]), + .C2(n_1_0_1283), .ZN(n_1_0_1118) + ); + SDFF_X1_LVT \registers_reg[18][24] ( + .CK(n_0_48), .D(registers[24]), .Q(registers_18__ap[24]), .QN(), .SE(dftIn), + .SI(registers_1__ap[24]) + ); + SDFF_X1_LVT \registers_reg[26][24] ( + .CK(n_0_56), .D(registers[24]), .Q(registers_26__ap[24]), .QN(), .SE(dftIn), + .SI(registers_28__ap[24]) + ); + AOI22_X1_LVT i_1_0_1174( + .A1(registers_18__ap[24]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[24]), + .ZN(n_1_0_1117) + ); + SDFF_X1_LVT \registers_reg[24][24] ( + .CK(n_0_54), .D(registers[24]), .Q(registers_24__ap[24]), .QN(), .SE(dftIn), + .SI(registers_26__ap[24]) + ); + SDFF_X1_LVT \registers_reg[4][24] ( + .CK(n_0_34), .D(registers[24]), .Q(registers_4__ap[24]), .QN(), .SE(dftIn), + .SI(registers_5__ap[24]) + ); + AOI22_X1_LVT i_1_0_1173( + .A1(registers_24__ap[24]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[24]), + .ZN(n_1_0_1116) + ); + SDFF_X1_LVT \registers_reg[15][24] ( + .CK(n_0_45), .D(registers[24]), .Q(registers_15__ap[24]), .QN(), .SE(dftIn), + .SI(registers_13__ap[24]) + ); + SDFF_X1_LVT \registers_reg[25][24] ( + .CK(n_0_55), .D(registers[24]), .Q(registers_25__ap[24]), .QN(), .SE(dftIn), + .SI(registers_24__ap[24]) + ); + AOI22_X1_LVT i_1_0_1172( + .A1(registers_15__ap[24]), .A2(n_1_0_1286), .B1(n_1_0_1269), .B2(registers_25__ap[24]), + .ZN(n_1_0_1115) + ); + NAND3_X1_LVT i_1_0_1171( + .A1(n_1_0_1117), .A2(n_1_0_1116), .A3(n_1_0_1115), .ZN(n_1_0_1114) + ); + SDFF_X1_LVT \registers_reg[19][24] ( + .CK(n_0_49), .D(registers[24]), .Q(registers_19__ap[24]), .QN(), .SE(dftIn), + .SI(registers_18__ap[24]) + ); + SDFF_X1_LVT \registers_reg[16][24] ( + .CK(n_0_46), .D(registers[24]), .Q(registers_16__ap[24]), .QN(), .SE(dftIn), + .SI(registers_15__ap[24]) + ); + AOI221_X1_LVT i_1_0_1170( + .A(n_1_0_1114), .B1(n_1_0_1295), .B2(registers_19__ap[24]), .C1(registers_16__ap[24]), + .C2(n_1_0_1267), .ZN(n_1_0_1113) + ); + SDFF_X1_LVT \registers_reg[7][24] ( + .CK(n_0_37), .D(registers[24]), .Q(registers_7__ap[24]), .QN(), .SE(dftIn), + .SI(registers_4__ap[24]) + ); + SDFF_X1_LVT \registers_reg[14][24] ( + .CK(n_0_44), .D(registers[24]), .Q(registers_14__ap[24]), .QN(), .SE(dftIn), + .SI(registers_16__ap[24]) + ); + AOI22_X1_LVT i_1_0_1169( + .A1(registers_7__ap[24]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[24]), + .ZN(n_1_0_1112) + ); + SDFF_X1_LVT \registers_reg[9][24] ( + .CK(n_0_39), .D(registers[24]), .Q(registers_9__ap[24]), .QN(), .SE(dftIn), + .SI(registers_7__ap[24]) + ); + SDFF_X1_LVT \registers_reg[29][24] ( + .CK(n_0_59), .D(registers[24]), .Q(registers_29__ap[24]), .QN(), .SE(dftIn), + .SI(registers_25__ap[24]) + ); + AOI22_X1_LVT i_1_0_1168( + .A1(registers_9__ap[24]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[24]), + .ZN(n_1_0_1111) + ); + SDFF_X1_LVT \registers_reg[23][24] ( + .CK(n_0_53), .D(registers[24]), .Q(registers_23__ap[24]), .QN(), .SE(dftIn), + .SI(registers_19__ap[24]) + ); + SDFF_X1_LVT \registers_reg[3][24] ( + .CK(n_0_33), .D(registers[24]), .Q(registers_3__ap[24]), .QN(), .SE(dftIn), + .SI(registers_9__ap[24]) + ); + AOI22_X1_LVT i_1_0_1167( + .A1(registers_23__ap[24]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[24]), + .ZN(n_1_0_1110) + ); + NAND3_X1_LVT i_1_0_1166( + .A1(n_1_0_1112), .A2(n_1_0_1111), .A3(n_1_0_1110), .ZN(n_1_0_1109) + ); + SDFF_X1_LVT \registers_reg[27][24] ( + .CK(n_0_57), .D(registers[24]), .Q(registers_27__ap[24]), .QN(), .SE(dftIn), + .SI(registers_29__ap[24]) + ); + SDFF_X1_LVT \registers_reg[31][24] ( + .CK(n_0_61), .D(registers[24]), .Q(registers_31__ap[24]), .QN(), .SE(dftIn), + .SI(registers_3__ap[24]) + ); + AOI221_X1_LVT i_1_0_1165( + .A(n_1_0_1109), .B1(n_1_0_1279), .B2(registers_27__ap[24]), .C1(registers_31__ap[24]), + .C2(n_1_0_1266), .ZN(n_1_0_1108) + ); + NAND4_X1_LVT i_1_0_1164( + .A1(n_1_0_1125), .A2(n_1_0_1118), .A3(n_1_0_1113), .A4(n_1_0_1108), .ZN(RRs1[24]) + ); + AND2_X1_LVT i_0_0_23( + .A1(n_0_0_16), .A2(WRd[23]), .ZN(registers[23]) + ); + SDFF_X1_LVT \registers_reg[9][23] ( + .CK(n_0_39), .D(registers[23]), .Q(registers_9__ap[23]), .QN(), .SE(dftIn), + .SI(registers_31__ap[24]) + ); + SDFF_X1_LVT \registers_reg[28][23] ( + .CK(n_0_58), .D(registers[23]), .Q(registers_28__ap[23]), .QN(), .SE(dftIn), + .SI(registers_27__ap[24]) + ); + AOI22_X1_LVT i_1_0_1163( + .A1(registers_9__ap[23]), .A2(n_1_0_1291), .B1(n_1_0_1283), .B2(registers_28__ap[23]), + .ZN(n_1_0_1107) + ); + SDFF_X1_LVT \registers_reg[18][23] ( + .CK(n_0_48), .D(registers[23]), .Q(registers_18__ap[23]), .QN(), .SE(dftIn), + .SI(registers_23__ap[24]) + ); + SDFF_X1_LVT \registers_reg[22][23] ( + .CK(n_0_52), .D(registers[23]), .Q(registers_22__ap[23]), .QN(), .SE(dftIn), + .SI(registers_18__ap[23]) + ); + AOI22_X1_LVT i_1_0_1160( + .A1(registers_18__ap[23]), .A2(n_1_0_1297), .B1(n_1_0_1294), .B2(registers_22__ap[23]), + .ZN(n_1_0_1104) + ); + SDFF_X1_LVT \registers_reg[1][23] ( + .CK(n_0_0), .D(registers[23]), .Q(registers_1__ap[23]), .QN(), .SE(dftIn), + .SI(registers_22__ap[23]) + ); + SDFF_X1_LVT \registers_reg[21][23] ( + .CK(n_0_51), .D(registers[23]), .Q(registers_21__ap[23]), .QN(), .SE(dftIn), + .SI(registers_1__ap[23]) + ); + AOI22_X1_LVT i_1_0_1159( + .A1(registers_1__ap[23]), .A2(n_1_0_1274), .B1(n_1_0_1259), .B2(registers_21__ap[23]), + .ZN(n_1_0_1103) + ); + NAND3_X1_LVT i_1_0_1157( + .A1(n_1_0_1107), .A2(n_1_0_1104), .A3(n_1_0_1103), .ZN(n_1_0_1101) + ); + SDFF_X1_LVT \registers_reg[20][23] ( + .CK(n_0_50), .D(registers[23]), .Q(registers_20__ap[23]), .QN(), .SE(dftIn), + .SI(registers_21__ap[23]) + ); + SDFF_X1_LVT \registers_reg[19][23] ( + .CK(n_0_49), .D(registers[23]), .Q(registers_19__ap[23]), .QN(), .SE(dftIn), + .SI(registers_20__ap[23]) + ); + AOI221_X1_LVT i_1_0_1156( + .A(n_1_0_1101), .B1(n_1_0_1281), .B2(registers_20__ap[23]), .C1(registers_19__ap[23]), + .C2(n_1_0_1295), .ZN(n_1_0_1100) + ); + SDFF_X1_LVT \registers_reg[26][23] ( + .CK(n_0_56), .D(registers[23]), .Q(registers_26__ap[23]), .QN(), .SE(dftIn), + .SI(registers_28__ap[23]) + ); + SDFF_X1_LVT \registers_reg[23][23] ( + .CK(n_0_53), .D(registers[23]), .Q(registers_23__ap[23]), .QN(), .SE(dftIn), + .SI(registers_19__ap[23]) + ); + AOI22_X1_LVT i_1_0_1162( + .A1(registers_26__ap[23]), .A2(n_1_0_1285), .B1(n_1_0_1264), .B2(registers_23__ap[23]), + .ZN(n_1_0_1106) + ); + SDFF_X1_LVT \registers_reg[29][23] ( + .CK(n_0_59), .D(registers[23]), .Q(registers_29__ap[23]), .QN(), .SE(dftIn), + .SI(registers_26__ap[23]) + ); + SDFF_X1_LVT \registers_reg[3][23] ( + .CK(n_0_33), .D(registers[23]), .Q(registers_3__ap[23]), .QN(), .SE(dftIn), + .SI(registers_9__ap[23]) + ); + AOI22_X1_LVT i_1_0_1161( + .A1(registers_29__ap[23]), .A2(n_1_0_1276), .B1(n_1_0_1257), .B2(registers_3__ap[23]), + .ZN(n_1_0_1105) + ); + SDFF_X1_LVT \registers_reg[30][23] ( + .CK(n_0_60), .D(registers[23]), .Q(registers_30__ap[23]), .QN(), .SE(dftIn), + .SI(registers_29__ap[23]) + ); + SDFF_X1_LVT \registers_reg[31][23] ( + .CK(n_0_61), .D(registers[23]), .Q(registers_31__ap[23]), .QN(), .SE(dftIn), + .SI(registers_3__ap[23]) + ); + AOI22_X1_LVT i_1_0_1158( + .A1(registers_30__ap[23]), .A2(n_1_0_1272), .B1(n_1_0_1266), .B2(registers_31__ap[23]), + .ZN(n_1_0_1102) + ); + NAND3_X1_LVT i_1_0_1155( + .A1(n_1_0_1106), .A2(n_1_0_1105), .A3(n_1_0_1102), .ZN(n_1_0_1099) + ); + SDFF_X1_LVT \registers_reg[8][23] ( + .CK(n_0_38), .D(registers[23]), .Q(registers_8__ap[23]), .QN(), .SE(dftIn), + .SI(registers_31__ap[23]) + ); + SDFF_X1_LVT \registers_reg[17][23] ( + .CK(n_0_47), .D(registers[23]), .Q(registers_17__ap[23]), .QN(), .SE(dftIn), + .SI(registers_23__ap[23]) + ); + AOI221_X1_LVT i_1_0_1154( + .A(n_1_0_1099), .B1(n_1_0_1282), .B2(registers_8__ap[23]), .C1(registers_17__ap[23]), + .C2(n_1_0_1271), .ZN(n_1_0_1098) + ); + SDFF_X1_LVT \registers_reg[24][23] ( + .CK(n_0_54), .D(registers[23]), .Q(registers_24__ap[23]), .QN(), .SE(dftIn), + .SI(registers_30__ap[23]) + ); + SDFF_X1_LVT \registers_reg[15][23] ( + .CK(n_0_45), .D(registers[23]), .Q(registers_15__ap[23]), .QN(), .SE(dftIn), + .SI(registers_14__ap[24]) + ); + SDFF_X1_LVT \registers_reg[14][23] ( + .CK(n_0_44), .D(registers[23]), .Q(registers_14__ap[23]), .QN(), .SE(dftIn), + .SI(registers_15__ap[23]) + ); + AOI222_X1_LVT i_1_0_1153( + .A1(registers_24__ap[23]), .A2(n_1_0_1289), .B1(n_1_0_1286), .B2(registers_15__ap[23]), + .C1(n_1_0_1258), .C2(registers_14__ap[23]), .ZN(n_1_0_1097) + ); + SDFF_X1_LVT \registers_reg[16][23] ( + .CK(n_0_46), .D(registers[23]), .Q(registers_16__ap[23]), .QN(), .SE(dftIn), + .SI(registers_14__ap[23]) + ); + SDFF_X1_LVT \registers_reg[7][23] ( + .CK(n_0_37), .D(registers[23]), .Q(registers_7__ap[23]), .QN(), .SE(dftIn), + .SI(registers_8__ap[23]) + ); + AOI22_X1_LVT i_1_0_1152( + .A1(registers_16__ap[23]), .A2(n_1_0_1267), .B1(n_1_0_1263), .B2(registers_7__ap[23]), + .ZN(n_1_0_1096) + ); + SDFF_X1_LVT \registers_reg[6][23] ( + .CK(n_0_36), .D(registers[23]), .Q(registers_6__ap[23]), .QN(), .SE(dftIn), + .SI(registers_7__ap[23]) + ); + SDFF_X1_LVT \registers_reg[25][23] ( + .CK(n_0_55), .D(registers[23]), .Q(registers_25__ap[23]), .QN(), .SE(dftIn), + .SI(registers_24__ap[23]) + ); + AOI22_X1_LVT i_1_0_1151( + .A1(registers_6__ap[23]), .A2(n_1_0_1300), .B1(n_1_0_1269), .B2(registers_25__ap[23]), + .ZN(n_1_0_1095) + ); + SDFF_X1_LVT \registers_reg[27][23] ( + .CK(n_0_57), .D(registers[23]), .Q(registers_27__ap[23]), .QN(), .SE(dftIn), + .SI(registers_25__ap[23]) + ); + SDFF_X1_LVT \registers_reg[11][23] ( + .CK(n_0_41), .D(registers[23]), .Q(registers_11__ap[23]), .QN(), .SE(dftIn), + .SI(registers_16__ap[23]) + ); + AOI22_X1_LVT i_1_0_1150( + .A1(registers_27__ap[23]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[23]), + .ZN(n_1_0_1094) + ); + SDFF_X1_LVT \registers_reg[13][23] ( + .CK(n_0_43), .D(registers[23]), .Q(registers_13__ap[23]), .QN(), .SE(dftIn), + .SI(registers_11__ap[23]) + ); + SDFF_X1_LVT \registers_reg[5][23] ( + .CK(n_0_35), .D(registers[23]), .Q(registers_5__ap[23]), .QN(), .SE(dftIn), + .SI(registers_6__ap[23]) + ); + AOI22_X1_LVT i_1_0_1149( + .A1(registers_13__ap[23]), .A2(n_1_0_1277), .B1(n_1_0_1273), .B2(registers_5__ap[23]), + .ZN(n_1_0_1093) + ); + SDFF_X1_LVT \registers_reg[4][23] ( + .CK(n_0_34), .D(registers[23]), .Q(registers_4__ap[23]), .QN(), .SE(dftIn), + .SI(registers_5__ap[23]) + ); + SDFF_X1_LVT \registers_reg[12][23] ( + .CK(n_0_42), .D(registers[23]), .Q(registers_12__ap[23]), .QN(), .SE(dftIn), + .SI(registers_13__ap[23]) + ); + AOI22_X1_LVT i_1_0_1148( + .A1(registers_4__ap[23]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[23]), + .ZN(n_1_0_1092) + ); + NAND3_X1_LVT i_1_0_1147( + .A1(n_1_0_1094), .A2(n_1_0_1093), .A3(n_1_0_1092), .ZN(n_1_0_1091) + ); + SDFF_X1_LVT \registers_reg[2][23] ( + .CK(n_0_32), .D(registers[23]), .Q(registers_2__ap[23]), .QN(), .SE(dftIn), + .SI(registers_27__ap[23]) + ); + SDFF_X1_LVT \registers_reg[10][23] ( + .CK(n_0_40), .D(registers[23]), .Q(registers_10__ap[23]), .QN(), .SE(dftIn), + .SI(registers_12__ap[23]) + ); + AOI221_X1_LVT i_1_0_1146( + .A(n_1_0_1091), .B1(n_1_0_1268), .B2(registers_2__ap[23]), .C1(registers_10__ap[23]), + .C2(n_1_0_1287), .ZN(n_1_0_1090) + ); + AND4_X1_LVT i_1_0_1145( + .A1(n_1_0_1097), .A2(n_1_0_1096), .A3(n_1_0_1095), .A4(n_1_0_1090), .ZN(n_1_0_1089) + ); + NAND3_X1_LVT i_1_0_1144( + .A1(n_1_0_1100), .A2(n_1_0_1098), .A3(n_1_0_1089), .ZN(RRs1[23]) + ); + AND2_X1_LVT i_0_0_22( + .A1(n_0_0_16), .A2(WRd[22]), .ZN(registers[22]) + ); + SDFF_X1_LVT \registers_reg[17][22] ( + .CK(n_0_47), .D(registers[22]), .Q(registers_17__ap[22]), .QN(), .SE(dftIn), + .SI(registers_17__ap[23]) + ); + SDFF_X1_LVT \registers_reg[21][22] ( + .CK(n_0_51), .D(registers[22]), .Q(registers_21__ap[22]), .QN(), .SE(dftIn), + .SI(registers_17__ap[22]) + ); + AOI22_X1_LVT i_1_0_1142( + .A1(registers_17__ap[22]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[22]), + .ZN(n_1_0_1087) + ); + SDFF_X1_LVT \registers_reg[6][22] ( + .CK(n_0_36), .D(registers[22]), .Q(registers_6__ap[22]), .QN(), .SE(dftIn), + .SI(registers_4__ap[23]) + ); + SDFF_X1_LVT \registers_reg[11][22] ( + .CK(n_0_41), .D(registers[22]), .Q(registers_11__ap[22]), .QN(), .SE(dftIn), + .SI(registers_10__ap[23]) + ); + AOI22_X1_LVT i_1_0_1143( + .A1(registers_6__ap[22]), .A2(n_1_0_1300), .B1(n_1_0_1270), .B2(registers_11__ap[22]), + .ZN(n_1_0_1088) + ); + SDFF_X1_LVT \registers_reg[20][22] ( + .CK(n_0_50), .D(registers[22]), .Q(registers_20__ap[22]), .QN(), .SE(dftIn), + .SI(registers_21__ap[22]) + ); + SDFF_X1_LVT \registers_reg[12][22] ( + .CK(n_0_42), .D(registers[22]), .Q(registers_12__ap[22]), .QN(), .SE(dftIn), + .SI(registers_11__ap[22]) + ); + AOI22_X1_LVT i_1_0_1141( + .A1(registers_20__ap[22]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[22]), + .ZN(n_1_0_1086) + ); + SDFF_X1_LVT \registers_reg[10][22] ( + .CK(n_0_40), .D(registers[22]), .Q(registers_10__ap[22]), .QN(), .SE(dftIn), + .SI(registers_12__ap[22]) + ); + SDFF_X1_LVT \registers_reg[5][22] ( + .CK(n_0_35), .D(registers[22]), .Q(registers_5__ap[22]), .QN(), .SE(dftIn), + .SI(registers_6__ap[22]) + ); + AOI22_X1_LVT i_1_0_1140( + .A1(registers_10__ap[22]), .A2(n_1_0_1287), .B1(n_1_0_1273), .B2(registers_5__ap[22]), + .ZN(n_1_0_1085) + ); + NAND3_X1_LVT i_1_0_1139( + .A1(n_1_0_1088), .A2(n_1_0_1086), .A3(n_1_0_1085), .ZN(n_1_0_1084) + ); + SDFF_X1_LVT \registers_reg[31][22] ( + .CK(n_0_61), .D(registers[22]), .Q(registers_31__ap[22]), .QN(), .SE(dftIn), + .SI(registers_5__ap[22]) + ); + SDFF_X1_LVT \registers_reg[2][22] ( + .CK(n_0_32), .D(registers[22]), .Q(registers_2__ap[22]), .QN(), .SE(dftIn), + .SI(registers_2__ap[23]) + ); + AOI221_X1_LVT i_1_0_1138( + .A(n_1_0_1084), .B1(n_1_0_1266), .B2(registers_31__ap[22]), .C1(registers_2__ap[22]), + .C2(n_1_0_1268), .ZN(n_1_0_1083) + ); + SDFF_X1_LVT \registers_reg[22][22] ( + .CK(n_0_52), .D(registers[22]), .Q(registers_22__ap[22]), .QN(), .SE(dftIn), + .SI(registers_20__ap[22]) + ); + SDFF_X1_LVT \registers_reg[26][22] ( + .CK(n_0_56), .D(registers[22]), .Q(registers_26__ap[22]), .QN(), .SE(dftIn), + .SI(registers_2__ap[22]) + ); + SDFF_X1_LVT \registers_reg[13][22] ( + .CK(n_0_43), .D(registers[22]), .Q(registers_13__ap[22]), .QN(), .SE(dftIn), + .SI(registers_10__ap[22]) + ); + AOI222_X1_LVT i_1_0_1137( + .A1(registers_22__ap[22]), .A2(n_1_0_1294), .B1(n_1_0_1285), .B2(registers_26__ap[22]), + .C1(n_1_0_1277), .C2(registers_13__ap[22]), .ZN(n_1_0_1082) + ); + NAND2_X1_LVT i_1_0_1136( + .A1(n_1_0_1083), .A2(n_1_0_1082), .ZN(n_1_0_1081) + ); + SDFF_X1_LVT \registers_reg[1][22] ( + .CK(n_0_0), .D(registers[22]), .Q(registers_1__ap[22]), .QN(), .SE(dftIn), + .SI(registers_22__ap[22]) + ); + SDFF_X1_LVT \registers_reg[28][22] ( + .CK(n_0_58), .D(registers[22]), .Q(registers_28__ap[22]), .QN(), .SE(dftIn), + .SI(registers_26__ap[22]) + ); + AOI221_X1_LVT i_1_0_1135( + .A(n_1_0_1081), .B1(n_1_0_1274), .B2(registers_1__ap[22]), .C1(registers_28__ap[22]), + .C2(n_1_0_1283), .ZN(n_1_0_1080) + ); + SDFF_X1_LVT \registers_reg[18][22] ( + .CK(n_0_48), .D(registers[22]), .Q(registers_18__ap[22]), .QN(), .SE(dftIn), + .SI(registers_1__ap[22]) + ); + SDFF_X1_LVT \registers_reg[30][22] ( + .CK(n_0_60), .D(registers[22]), .Q(registers_30__ap[22]), .QN(), .SE(dftIn), + .SI(registers_28__ap[22]) + ); + AOI22_X1_LVT i_1_0_1134( + .A1(registers_18__ap[22]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[22]), + .ZN(n_1_0_1079) + ); + SDFF_X1_LVT \registers_reg[24][22] ( + .CK(n_0_54), .D(registers[22]), .Q(registers_24__ap[22]), .QN(), .SE(dftIn), + .SI(registers_30__ap[22]) + ); + SDFF_X1_LVT \registers_reg[4][22] ( + .CK(n_0_34), .D(registers[22]), .Q(registers_4__ap[22]), .QN(), .SE(dftIn), + .SI(registers_31__ap[22]) + ); + AOI22_X1_LVT i_1_0_1133( + .A1(registers_24__ap[22]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[22]), + .ZN(n_1_0_1078) + ); + SDFF_X1_LVT \registers_reg[15][22] ( + .CK(n_0_45), .D(registers[22]), .Q(registers_15__ap[22]), .QN(), .SE(dftIn), + .SI(registers_13__ap[22]) + ); + SDFF_X1_LVT \registers_reg[16][22] ( + .CK(n_0_46), .D(registers[22]), .Q(registers_16__ap[22]), .QN(), .SE(dftIn), + .SI(registers_15__ap[22]) + ); + AOI22_X1_LVT i_1_0_1132( + .A1(registers_15__ap[22]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[22]), + .ZN(n_1_0_1077) + ); + NAND3_X1_LVT i_1_0_1131( + .A1(n_1_0_1079), .A2(n_1_0_1078), .A3(n_1_0_1077), .ZN(n_1_0_1076) + ); + SDFF_X1_LVT \registers_reg[19][22] ( + .CK(n_0_49), .D(registers[22]), .Q(registers_19__ap[22]), .QN(), .SE(dftIn), + .SI(registers_18__ap[22]) + ); + SDFF_X1_LVT \registers_reg[25][22] ( + .CK(n_0_55), .D(registers[22]), .Q(registers_25__ap[22]), .QN(), .SE(dftIn), + .SI(registers_24__ap[22]) + ); + AOI221_X1_LVT i_1_0_1130( + .A(n_1_0_1076), .B1(n_1_0_1295), .B2(registers_19__ap[22]), .C1(registers_25__ap[22]), + .C2(n_1_0_1269), .ZN(n_1_0_1075) + ); + SDFF_X1_LVT \registers_reg[7][22] ( + .CK(n_0_37), .D(registers[22]), .Q(registers_7__ap[22]), .QN(), .SE(dftIn), + .SI(registers_4__ap[22]) + ); + SDFF_X1_LVT \registers_reg[14][22] ( + .CK(n_0_44), .D(registers[22]), .Q(registers_14__ap[22]), .QN(), .SE(dftIn), + .SI(registers_16__ap[22]) + ); + AOI22_X1_LVT i_1_0_1129( + .A1(registers_7__ap[22]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[22]), + .ZN(n_1_0_1074) + ); + SDFF_X1_LVT \registers_reg[9][22] ( + .CK(n_0_39), .D(registers[22]), .Q(registers_9__ap[22]), .QN(), .SE(dftIn), + .SI(registers_7__ap[22]) + ); + SDFF_X1_LVT \registers_reg[29][22] ( + .CK(n_0_59), .D(registers[22]), .Q(registers_29__ap[22]), .QN(), .SE(dftIn), + .SI(registers_25__ap[22]) + ); + AOI22_X1_LVT i_1_0_1128( + .A1(registers_9__ap[22]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[22]), + .ZN(n_1_0_1073) + ); + SDFF_X1_LVT \registers_reg[8][22] ( + .CK(n_0_38), .D(registers[22]), .Q(registers_8__ap[22]), .QN(), .SE(dftIn), + .SI(registers_9__ap[22]) + ); + SDFF_X1_LVT \registers_reg[23][22] ( + .CK(n_0_53), .D(registers[22]), .Q(registers_23__ap[22]), .QN(), .SE(dftIn), + .SI(registers_19__ap[22]) + ); + AOI22_X1_LVT i_1_0_1127( + .A1(registers_8__ap[22]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[22]), + .ZN(n_1_0_1072) + ); + NAND3_X1_LVT i_1_0_1126( + .A1(n_1_0_1074), .A2(n_1_0_1073), .A3(n_1_0_1072), .ZN(n_1_0_1071) + ); + SDFF_X1_LVT \registers_reg[27][22] ( + .CK(n_0_57), .D(registers[22]), .Q(registers_27__ap[22]), .QN(), .SE(dftIn), + .SI(registers_29__ap[22]) + ); + SDFF_X1_LVT \registers_reg[3][22] ( + .CK(n_0_33), .D(registers[22]), .Q(registers_3__ap[22]), .QN(), .SE(dftIn), + .SI(registers_8__ap[22]) + ); + AOI221_X1_LVT i_1_0_1125( + .A(n_1_0_1071), .B1(n_1_0_1279), .B2(registers_27__ap[22]), .C1(registers_3__ap[22]), + .C2(n_1_0_1257), .ZN(n_1_0_1070) + ); + NAND4_X1_LVT i_1_0_1124( + .A1(n_1_0_1087), .A2(n_1_0_1080), .A3(n_1_0_1075), .A4(n_1_0_1070), .ZN(RRs1[22]) + ); + AND2_X1_LVT i_0_0_21( + .A1(n_0_0_16), .A2(WRd[21]), .ZN(registers[21]) + ); + SDFF_X1_LVT \registers_reg[17][21] ( + .CK(n_0_47), .D(registers[21]), .Q(registers_17__ap[21]), .QN(), .SE(dftIn), + .SI(registers_23__ap[22]) + ); + SDFF_X1_LVT \registers_reg[21][21] ( + .CK(n_0_51), .D(registers[21]), .Q(registers_21__ap[21]), .QN(), .SE(dftIn), + .SI(registers_17__ap[21]) + ); + AOI22_X1_LVT i_1_0_1122( + .A1(registers_17__ap[21]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[21]), + .ZN(n_1_0_1068) + ); + SDFF_X1_LVT \registers_reg[6][21] ( + .CK(n_0_36), .D(registers[21]), .Q(registers_6__ap[21]), .QN(), .SE(dftIn), + .SI(registers_3__ap[22]) + ); + SDFF_X1_LVT \registers_reg[8][21] ( + .CK(n_0_38), .D(registers[21]), .Q(registers_8__ap[21]), .QN(), .SE(dftIn), + .SI(registers_6__ap[21]) + ); + AOI22_X1_LVT i_1_0_1123( + .A1(registers_6__ap[21]), .A2(n_1_0_1300), .B1(n_1_0_1282), .B2(registers_8__ap[21]), + .ZN(n_1_0_1069) + ); + SDFF_X1_LVT \registers_reg[20][21] ( + .CK(n_0_50), .D(registers[21]), .Q(registers_20__ap[21]), .QN(), .SE(dftIn), + .SI(registers_21__ap[21]) + ); + SDFF_X1_LVT \registers_reg[12][21] ( + .CK(n_0_42), .D(registers[21]), .Q(registers_12__ap[21]), .QN(), .SE(dftIn), + .SI(registers_14__ap[22]) + ); + AOI22_X1_LVT i_1_0_1121( + .A1(registers_20__ap[21]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[21]), + .ZN(n_1_0_1067) + ); + SDFF_X1_LVT \registers_reg[5][21] ( + .CK(n_0_35), .D(registers[21]), .Q(registers_5__ap[21]), .QN(), .SE(dftIn), + .SI(registers_8__ap[21]) + ); + SDFF_X1_LVT \registers_reg[11][21] ( + .CK(n_0_41), .D(registers[21]), .Q(registers_11__ap[21]), .QN(), .SE(dftIn), + .SI(registers_12__ap[21]) + ); + AOI22_X1_LVT i_1_0_1120( + .A1(registers_5__ap[21]), .A2(n_1_0_1273), .B1(n_1_0_1270), .B2(registers_11__ap[21]), + .ZN(n_1_0_1066) + ); + NAND3_X1_LVT i_1_0_1119( + .A1(n_1_0_1069), .A2(n_1_0_1067), .A3(n_1_0_1066), .ZN(n_1_0_1065) + ); + SDFF_X1_LVT \registers_reg[10][21] ( + .CK(n_0_40), .D(registers[21]), .Q(registers_10__ap[21]), .QN(), .SE(dftIn), + .SI(registers_11__ap[21]) + ); + SDFF_X1_LVT \registers_reg[2][21] ( + .CK(n_0_32), .D(registers[21]), .Q(registers_2__ap[21]), .QN(), .SE(dftIn), + .SI(registers_27__ap[22]) + ); + AOI221_X1_LVT i_1_0_1118( + .A(n_1_0_1065), .B1(n_1_0_1287), .B2(registers_10__ap[21]), .C1(registers_2__ap[21]), + .C2(n_1_0_1268), .ZN(n_1_0_1064) + ); + SDFF_X1_LVT \registers_reg[13][21] ( + .CK(n_0_43), .D(registers[21]), .Q(registers_13__ap[21]), .QN(), .SE(dftIn), + .SI(registers_10__ap[21]) + ); + SDFF_X1_LVT \registers_reg[30][21] ( + .CK(n_0_60), .D(registers[21]), .Q(registers_30__ap[21]), .QN(), .SE(dftIn), + .SI(registers_2__ap[21]) + ); + SDFF_X1_LVT \registers_reg[22][21] ( + .CK(n_0_52), .D(registers[21]), .Q(registers_22__ap[21]), .QN(), .SE(dftIn), + .SI(registers_20__ap[21]) + ); + AOI222_X1_LVT i_1_0_1117( + .A1(registers_13__ap[21]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[21]), + .C1(registers_22__ap[21]), .C2(n_1_0_1294), .ZN(n_1_0_1063) + ); + NAND2_X1_LVT i_1_0_1116( + .A1(n_1_0_1064), .A2(n_1_0_1063), .ZN(n_1_0_1062) + ); + SDFF_X1_LVT \registers_reg[1][21] ( + .CK(n_0_0), .D(registers[21]), .Q(registers_1__ap[21]), .QN(), .SE(dftIn), + .SI(registers_22__ap[21]) + ); + SDFF_X1_LVT \registers_reg[28][21] ( + .CK(n_0_58), .D(registers[21]), .Q(registers_28__ap[21]), .QN(), .SE(dftIn), + .SI(registers_30__ap[21]) + ); + AOI221_X1_LVT i_1_0_1115( + .A(n_1_0_1062), .B1(n_1_0_1274), .B2(registers_1__ap[21]), .C1(registers_28__ap[21]), + .C2(n_1_0_1283), .ZN(n_1_0_1061) + ); + SDFF_X1_LVT \registers_reg[18][21] ( + .CK(n_0_48), .D(registers[21]), .Q(registers_18__ap[21]), .QN(), .SE(dftIn), + .SI(registers_1__ap[21]) + ); + SDFF_X1_LVT \registers_reg[26][21] ( + .CK(n_0_56), .D(registers[21]), .Q(registers_26__ap[21]), .QN(), .SE(dftIn), + .SI(registers_28__ap[21]) + ); + AOI22_X1_LVT i_1_0_1114( + .A1(registers_18__ap[21]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[21]), + .ZN(n_1_0_1060) + ); + SDFF_X1_LVT \registers_reg[24][21] ( + .CK(n_0_54), .D(registers[21]), .Q(registers_24__ap[21]), .QN(), .SE(dftIn), + .SI(registers_26__ap[21]) + ); + SDFF_X1_LVT \registers_reg[4][21] ( + .CK(n_0_34), .D(registers[21]), .Q(registers_4__ap[21]), .QN(), .SE(dftIn), + .SI(registers_5__ap[21]) + ); + AOI22_X1_LVT i_1_0_1113( + .A1(registers_24__ap[21]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[21]), + .ZN(n_1_0_1059) + ); + SDFF_X1_LVT \registers_reg[15][21] ( + .CK(n_0_45), .D(registers[21]), .Q(registers_15__ap[21]), .QN(), .SE(dftIn), + .SI(registers_13__ap[21]) + ); + SDFF_X1_LVT \registers_reg[16][21] ( + .CK(n_0_46), .D(registers[21]), .Q(registers_16__ap[21]), .QN(), .SE(dftIn), + .SI(registers_15__ap[21]) + ); + AOI22_X1_LVT i_1_0_1112( + .A1(registers_15__ap[21]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[21]), + .ZN(n_1_0_1058) + ); + NAND3_X1_LVT i_1_0_1111( + .A1(n_1_0_1060), .A2(n_1_0_1059), .A3(n_1_0_1058), .ZN(n_1_0_1057) + ); + SDFF_X1_LVT \registers_reg[19][21] ( + .CK(n_0_49), .D(registers[21]), .Q(registers_19__ap[21]), .QN(), .SE(dftIn), + .SI(registers_18__ap[21]) + ); + SDFF_X1_LVT \registers_reg[25][21] ( + .CK(n_0_55), .D(registers[21]), .Q(registers_25__ap[21]), .QN(), .SE(dftIn), + .SI(registers_24__ap[21]) + ); + AOI221_X1_LVT i_1_0_1110( + .A(n_1_0_1057), .B1(n_1_0_1295), .B2(registers_19__ap[21]), .C1(registers_25__ap[21]), + .C2(n_1_0_1269), .ZN(n_1_0_1056) + ); + SDFF_X1_LVT \registers_reg[7][21] ( + .CK(n_0_37), .D(registers[21]), .Q(registers_7__ap[21]), .QN(), .SE(dftIn), + .SI(registers_4__ap[21]) + ); + SDFF_X1_LVT \registers_reg[14][21] ( + .CK(n_0_44), .D(registers[21]), .Q(registers_14__ap[21]), .QN(), .SE(dftIn), + .SI(registers_16__ap[21]) + ); + AOI22_X1_LVT i_1_0_1109( + .A1(registers_7__ap[21]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[21]), + .ZN(n_1_0_1055) + ); + SDFF_X1_LVT \registers_reg[9][21] ( + .CK(n_0_39), .D(registers[21]), .Q(registers_9__ap[21]), .QN(), .SE(dftIn), + .SI(registers_7__ap[21]) + ); + SDFF_X1_LVT \registers_reg[29][21] ( + .CK(n_0_59), .D(registers[21]), .Q(registers_29__ap[21]), .QN(), .SE(dftIn), + .SI(registers_25__ap[21]) + ); + AOI22_X1_LVT i_1_0_1108( + .A1(registers_9__ap[21]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[21]), + .ZN(n_1_0_1054) + ); + SDFF_X1_LVT \registers_reg[23][21] ( + .CK(n_0_53), .D(registers[21]), .Q(registers_23__ap[21]), .QN(), .SE(dftIn), + .SI(registers_19__ap[21]) + ); + SDFF_X1_LVT \registers_reg[3][21] ( + .CK(n_0_33), .D(registers[21]), .Q(registers_3__ap[21]), .QN(), .SE(dftIn), + .SI(registers_9__ap[21]) + ); + AOI22_X1_LVT i_1_0_1107( + .A1(registers_23__ap[21]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[21]), + .ZN(n_1_0_1053) + ); + NAND3_X1_LVT i_1_0_1106( + .A1(n_1_0_1055), .A2(n_1_0_1054), .A3(n_1_0_1053), .ZN(n_1_0_1052) + ); + SDFF_X1_LVT \registers_reg[27][21] ( + .CK(n_0_57), .D(registers[21]), .Q(registers_27__ap[21]), .QN(), .SE(dftIn), + .SI(registers_29__ap[21]) + ); + SDFF_X1_LVT \registers_reg[31][21] ( + .CK(n_0_61), .D(registers[21]), .Q(registers_31__ap[21]), .QN(), .SE(dftIn), + .SI(registers_3__ap[21]) + ); + AOI221_X1_LVT i_1_0_1105( + .A(n_1_0_1052), .B1(n_1_0_1279), .B2(registers_27__ap[21]), .C1(registers_31__ap[21]), + .C2(n_1_0_1266), .ZN(n_1_0_1051) + ); + NAND4_X1_LVT i_1_0_1104( + .A1(n_1_0_1068), .A2(n_1_0_1061), .A3(n_1_0_1056), .A4(n_1_0_1051), .ZN(RRs1[21]) + ); + AND2_X1_LVT i_0_0_20( + .A1(n_0_0_16), .A2(WRd[20]), .ZN(registers[20]) + ); + SDFF_X1_LVT \registers_reg[17][20] ( + .CK(n_0_47), .D(registers[20]), .Q(registers_17__ap[20]), .QN(), .SE(dftIn), + .SI(registers_23__ap[21]) + ); + SDFF_X1_LVT \registers_reg[21][20] ( + .CK(n_0_51), .D(registers[20]), .Q(registers_21__ap[20]), .QN(), .SE(dftIn), + .SI(registers_17__ap[20]) + ); + AOI22_X1_LVT i_1_0_1100( + .A1(registers_17__ap[20]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[20]), + .ZN(n_1_0_1047) + ); + SDFF_X1_LVT \registers_reg[10][20] ( + .CK(n_0_40), .D(registers[20]), .Q(registers_10__ap[20]), .QN(), .SE(dftIn), + .SI(registers_14__ap[21]) + ); + SDFF_X1_LVT \registers_reg[2][20] ( + .CK(n_0_32), .D(registers[20]), .Q(registers_2__ap[20]), .QN(), .SE(dftIn), + .SI(registers_27__ap[21]) + ); + AOI22_X1_LVT i_1_0_1103( + .A1(registers_10__ap[20]), .A2(n_1_0_1287), .B1(n_1_0_1268), .B2(registers_2__ap[20]), + .ZN(n_1_0_1050) + ); + SDFF_X1_LVT \registers_reg[20][20] ( + .CK(n_0_50), .D(registers[20]), .Q(registers_20__ap[20]), .QN(), .SE(dftIn), + .SI(registers_21__ap[20]) + ); + SDFF_X1_LVT \registers_reg[12][20] ( + .CK(n_0_42), .D(registers[20]), .Q(registers_12__ap[20]), .QN(), .SE(dftIn), + .SI(registers_10__ap[20]) + ); + AOI22_X1_LVT i_1_0_1099( + .A1(registers_20__ap[20]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[20]), + .ZN(n_1_0_1046) + ); + SDFF_X1_LVT \registers_reg[15][20] ( + .CK(n_0_45), .D(registers[20]), .Q(registers_15__ap[20]), .QN(), .SE(dftIn), + .SI(registers_12__ap[20]) + ); + SDFF_X1_LVT \registers_reg[8][20] ( + .CK(n_0_38), .D(registers[20]), .Q(registers_8__ap[20]), .QN(), .SE(dftIn), + .SI(registers_31__ap[21]) + ); + AOI22_X1_LVT i_1_0_1102( + .A1(registers_15__ap[20]), .A2(n_1_0_1286), .B1(n_1_0_1282), .B2(registers_8__ap[20]), + .ZN(n_1_0_1049) + ); + INV_X1_LVT i_1_0_1101( + .A(n_1_0_1049), .ZN(n_1_0_1048) + ); + SDFF_X1_LVT \registers_reg[11][20] ( + .CK(n_0_41), .D(registers[20]), .Q(registers_11__ap[20]), .QN(), .SE(dftIn), + .SI(registers_15__ap[20]) + ); + SDFF_X1_LVT \registers_reg[5][20] ( + .CK(n_0_35), .D(registers[20]), .Q(registers_5__ap[20]), .QN(), .SE(dftIn), + .SI(registers_8__ap[20]) + ); + AOI221_X1_LVT i_1_0_1098( + .A(n_1_0_1048), .B1(n_1_0_1270), .B2(registers_11__ap[20]), .C1(registers_5__ap[20]), + .C2(n_1_0_1273), .ZN(n_1_0_1045) + ); + SDFF_X1_LVT \registers_reg[13][20] ( + .CK(n_0_43), .D(registers[20]), .Q(registers_13__ap[20]), .QN(), .SE(dftIn), + .SI(registers_11__ap[20]) + ); + SDFF_X1_LVT \registers_reg[30][20] ( + .CK(n_0_60), .D(registers[20]), .Q(registers_30__ap[20]), .QN(), .SE(dftIn), + .SI(registers_2__ap[20]) + ); + SDFF_X1_LVT \registers_reg[22][20] ( + .CK(n_0_52), .D(registers[20]), .Q(registers_22__ap[20]), .QN(), .SE(dftIn), + .SI(registers_20__ap[20]) + ); + AOI222_X1_LVT i_1_0_1097( + .A1(registers_13__ap[20]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[20]), + .C1(registers_22__ap[20]), .C2(n_1_0_1294), .ZN(n_1_0_1044) + ); + NAND4_X1_LVT i_1_0_1096( + .A1(n_1_0_1050), .A2(n_1_0_1046), .A3(n_1_0_1045), .A4(n_1_0_1044), .ZN(n_1_0_1043) + ); + SDFF_X1_LVT \registers_reg[1][20] ( + .CK(n_0_0), .D(registers[20]), .Q(registers_1__ap[20]), .QN(), .SE(dftIn), + .SI(registers_22__ap[20]) + ); + SDFF_X1_LVT \registers_reg[28][20] ( + .CK(n_0_58), .D(registers[20]), .Q(registers_28__ap[20]), .QN(), .SE(dftIn), + .SI(registers_30__ap[20]) + ); + AOI221_X1_LVT i_1_0_1095( + .A(n_1_0_1043), .B1(n_1_0_1274), .B2(registers_1__ap[20]), .C1(registers_28__ap[20]), + .C2(n_1_0_1283), .ZN(n_1_0_1042) + ); + SDFF_X1_LVT \registers_reg[18][20] ( + .CK(n_0_48), .D(registers[20]), .Q(registers_18__ap[20]), .QN(), .SE(dftIn), + .SI(registers_1__ap[20]) + ); + SDFF_X1_LVT \registers_reg[26][20] ( + .CK(n_0_56), .D(registers[20]), .Q(registers_26__ap[20]), .QN(), .SE(dftIn), + .SI(registers_28__ap[20]) + ); + AOI22_X1_LVT i_1_0_1094( + .A1(registers_18__ap[20]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[20]), + .ZN(n_1_0_1041) + ); + SDFF_X1_LVT \registers_reg[24][20] ( + .CK(n_0_54), .D(registers[20]), .Q(registers_24__ap[20]), .QN(), .SE(dftIn), + .SI(registers_26__ap[20]) + ); + SDFF_X1_LVT \registers_reg[4][20] ( + .CK(n_0_34), .D(registers[20]), .Q(registers_4__ap[20]), .QN(), .SE(dftIn), + .SI(registers_5__ap[20]) + ); + AOI22_X1_LVT i_1_0_1093( + .A1(registers_24__ap[20]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[20]), + .ZN(n_1_0_1040) + ); + SDFF_X1_LVT \registers_reg[6][20] ( + .CK(n_0_36), .D(registers[20]), .Q(registers_6__ap[20]), .QN(), .SE(dftIn), + .SI(registers_4__ap[20]) + ); + SDFF_X1_LVT \registers_reg[25][20] ( + .CK(n_0_55), .D(registers[20]), .Q(registers_25__ap[20]), .QN(), .SE(dftIn), + .SI(registers_24__ap[20]) + ); + AOI22_X1_LVT i_1_0_1092( + .A1(registers_6__ap[20]), .A2(n_1_0_1300), .B1(n_1_0_1269), .B2(registers_25__ap[20]), + .ZN(n_1_0_1039) + ); + NAND3_X1_LVT i_1_0_1091( + .A1(n_1_0_1041), .A2(n_1_0_1040), .A3(n_1_0_1039), .ZN(n_1_0_1038) + ); + SDFF_X1_LVT \registers_reg[19][20] ( + .CK(n_0_49), .D(registers[20]), .Q(registers_19__ap[20]), .QN(), .SE(dftIn), + .SI(registers_18__ap[20]) + ); + SDFF_X1_LVT \registers_reg[16][20] ( + .CK(n_0_46), .D(registers[20]), .Q(registers_16__ap[20]), .QN(), .SE(dftIn), + .SI(registers_13__ap[20]) + ); + AOI221_X1_LVT i_1_0_1090( + .A(n_1_0_1038), .B1(n_1_0_1295), .B2(registers_19__ap[20]), .C1(registers_16__ap[20]), + .C2(n_1_0_1267), .ZN(n_1_0_1037) + ); + SDFF_X1_LVT \registers_reg[7][20] ( + .CK(n_0_37), .D(registers[20]), .Q(registers_7__ap[20]), .QN(), .SE(dftIn), + .SI(registers_6__ap[20]) + ); + SDFF_X1_LVT \registers_reg[14][20] ( + .CK(n_0_44), .D(registers[20]), .Q(registers_14__ap[20]), .QN(), .SE(dftIn), + .SI(registers_16__ap[20]) + ); + AOI22_X1_LVT i_1_0_1089( + .A1(registers_7__ap[20]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[20]), + .ZN(n_1_0_1036) + ); + SDFF_X1_LVT \registers_reg[9][20] ( + .CK(n_0_39), .D(registers[20]), .Q(registers_9__ap[20]), .QN(), .SE(dftIn), + .SI(registers_7__ap[20]) + ); + SDFF_X1_LVT \registers_reg[29][20] ( + .CK(n_0_59), .D(registers[20]), .Q(registers_29__ap[20]), .QN(), .SE(dftIn), + .SI(registers_25__ap[20]) + ); + AOI22_X1_LVT i_1_0_1088( + .A1(registers_9__ap[20]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[20]), + .ZN(n_1_0_1035) + ); + SDFF_X1_LVT \registers_reg[23][20] ( + .CK(n_0_53), .D(registers[20]), .Q(registers_23__ap[20]), .QN(), .SE(dftIn), + .SI(registers_19__ap[20]) + ); + SDFF_X1_LVT \registers_reg[3][20] ( + .CK(n_0_33), .D(registers[20]), .Q(registers_3__ap[20]), .QN(), .SE(dftIn), + .SI(registers_9__ap[20]) + ); + AOI22_X1_LVT i_1_0_1087( + .A1(registers_23__ap[20]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[20]), + .ZN(n_1_0_1034) + ); + NAND3_X1_LVT i_1_0_1086( + .A1(n_1_0_1036), .A2(n_1_0_1035), .A3(n_1_0_1034), .ZN(n_1_0_1033) + ); + SDFF_X1_LVT \registers_reg[27][20] ( + .CK(n_0_57), .D(registers[20]), .Q(registers_27__ap[20]), .QN(), .SE(dftIn), + .SI(registers_29__ap[20]) + ); + SDFF_X1_LVT \registers_reg[31][20] ( + .CK(n_0_61), .D(registers[20]), .Q(registers_31__ap[20]), .QN(), .SE(dftIn), + .SI(registers_3__ap[20]) + ); + AOI221_X1_LVT i_1_0_1085( + .A(n_1_0_1033), .B1(n_1_0_1279), .B2(registers_27__ap[20]), .C1(registers_31__ap[20]), + .C2(n_1_0_1266), .ZN(n_1_0_1032) + ); + NAND4_X1_LVT i_1_0_1084( + .A1(n_1_0_1047), .A2(n_1_0_1042), .A3(n_1_0_1037), .A4(n_1_0_1032), .ZN(RRs1[20]) + ); + AND2_X1_LVT i_0_0_19( + .A1(n_0_0_16), .A2(WRd[19]), .ZN(registers[19]) + ); + SDFF_X1_LVT \registers_reg[17][19] ( + .CK(n_0_47), .D(registers[19]), .Q(registers_17__ap[19]), .QN(), .SE(dftIn), + .SI(registers_23__ap[20]) + ); + SDFF_X1_LVT \registers_reg[21][19] ( + .CK(n_0_51), .D(registers[19]), .Q(registers_21__ap[19]), .QN(), .SE(dftIn), + .SI(registers_17__ap[19]) + ); + AOI22_X1_LVT i_1_0_1080( + .A1(registers_17__ap[19]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[19]), + .ZN(n_1_0_1028) + ); + SDFF_X1_LVT \registers_reg[2][19] ( + .CK(n_0_32), .D(registers[19]), .Q(registers_2__ap[19]), .QN(), .SE(dftIn), + .SI(registers_27__ap[20]) + ); + SDFF_X1_LVT \registers_reg[31][19] ( + .CK(n_0_61), .D(registers[19]), .Q(registers_31__ap[19]), .QN(), .SE(dftIn), + .SI(registers_31__ap[20]) + ); + AOI22_X1_LVT i_1_0_1083( + .A1(registers_2__ap[19]), .A2(n_1_0_1268), .B1(n_1_0_1266), .B2(registers_31__ap[19]), + .ZN(n_1_0_1031) + ); + SDFF_X1_LVT \registers_reg[20][19] ( + .CK(n_0_50), .D(registers[19]), .Q(registers_20__ap[19]), .QN(), .SE(dftIn), + .SI(registers_21__ap[19]) + ); + SDFF_X1_LVT \registers_reg[12][19] ( + .CK(n_0_42), .D(registers[19]), .Q(registers_12__ap[19]), .QN(), .SE(dftIn), + .SI(registers_14__ap[20]) + ); + AOI22_X1_LVT i_1_0_1079( + .A1(registers_20__ap[19]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[19]), + .ZN(n_1_0_1027) + ); + SDFF_X1_LVT \registers_reg[15][19] ( + .CK(n_0_45), .D(registers[19]), .Q(registers_15__ap[19]), .QN(), .SE(dftIn), + .SI(registers_12__ap[19]) + ); + SDFF_X1_LVT \registers_reg[11][19] ( + .CK(n_0_41), .D(registers[19]), .Q(registers_11__ap[19]), .QN(), .SE(dftIn), + .SI(registers_15__ap[19]) + ); + AOI22_X1_LVT i_1_0_1082( + .A1(registers_15__ap[19]), .A2(n_1_0_1286), .B1(n_1_0_1270), .B2(registers_11__ap[19]), + .ZN(n_1_0_1030) + ); + INV_X1_LVT i_1_0_1081( + .A(n_1_0_1030), .ZN(n_1_0_1029) + ); + SDFF_X1_LVT \registers_reg[27][19] ( + .CK(n_0_57), .D(registers[19]), .Q(registers_27__ap[19]), .QN(), .SE(dftIn), + .SI(registers_2__ap[19]) + ); + SDFF_X1_LVT \registers_reg[24][19] ( + .CK(n_0_54), .D(registers[19]), .Q(registers_24__ap[19]), .QN(), .SE(dftIn), + .SI(registers_27__ap[19]) + ); + AOI221_X1_LVT i_1_0_1078( + .A(n_1_0_1029), .B1(n_1_0_1279), .B2(registers_27__ap[19]), .C1(registers_24__ap[19]), + .C2(n_1_0_1289), .ZN(n_1_0_1026) + ); + SDFF_X1_LVT \registers_reg[22][19] ( + .CK(n_0_52), .D(registers[19]), .Q(registers_22__ap[19]), .QN(), .SE(dftIn), + .SI(registers_20__ap[19]) + ); + SDFF_X1_LVT \registers_reg[26][19] ( + .CK(n_0_56), .D(registers[19]), .Q(registers_26__ap[19]), .QN(), .SE(dftIn), + .SI(registers_24__ap[19]) + ); + SDFF_X1_LVT \registers_reg[13][19] ( + .CK(n_0_43), .D(registers[19]), .Q(registers_13__ap[19]), .QN(), .SE(dftIn), + .SI(registers_11__ap[19]) + ); + AOI222_X1_LVT i_1_0_1077( + .A1(registers_22__ap[19]), .A2(n_1_0_1294), .B1(n_1_0_1285), .B2(registers_26__ap[19]), + .C1(n_1_0_1277), .C2(registers_13__ap[19]), .ZN(n_1_0_1025) + ); + NAND4_X1_LVT i_1_0_1076( + .A1(n_1_0_1031), .A2(n_1_0_1027), .A3(n_1_0_1026), .A4(n_1_0_1025), .ZN(n_1_0_1024) + ); + SDFF_X1_LVT \registers_reg[1][19] ( + .CK(n_0_0), .D(registers[19]), .Q(registers_1__ap[19]), .QN(), .SE(dftIn), + .SI(registers_22__ap[19]) + ); + SDFF_X1_LVT \registers_reg[28][19] ( + .CK(n_0_58), .D(registers[19]), .Q(registers_28__ap[19]), .QN(), .SE(dftIn), + .SI(registers_26__ap[19]) + ); + AOI221_X1_LVT i_1_0_1075( + .A(n_1_0_1024), .B1(n_1_0_1274), .B2(registers_1__ap[19]), .C1(registers_28__ap[19]), + .C2(n_1_0_1283), .ZN(n_1_0_1023) + ); + SDFF_X1_LVT \registers_reg[18][19] ( + .CK(n_0_48), .D(registers[19]), .Q(registers_18__ap[19]), .QN(), .SE(dftIn), + .SI(registers_1__ap[19]) + ); + SDFF_X1_LVT \registers_reg[30][19] ( + .CK(n_0_60), .D(registers[19]), .Q(registers_30__ap[19]), .QN(), .SE(dftIn), + .SI(registers_28__ap[19]) + ); + AOI22_X1_LVT i_1_0_1074( + .A1(registers_18__ap[19]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[19]), + .ZN(n_1_0_1022) + ); + SDFF_X1_LVT \registers_reg[4][19] ( + .CK(n_0_34), .D(registers[19]), .Q(registers_4__ap[19]), .QN(), .SE(dftIn), + .SI(registers_31__ap[19]) + ); + SDFF_X1_LVT \registers_reg[5][19] ( + .CK(n_0_35), .D(registers[19]), .Q(registers_5__ap[19]), .QN(), .SE(dftIn), + .SI(registers_4__ap[19]) + ); + AOI22_X1_LVT i_1_0_1073( + .A1(registers_4__ap[19]), .A2(n_1_0_1278), .B1(n_1_0_1273), .B2(registers_5__ap[19]), + .ZN(n_1_0_1021) + ); + SDFF_X1_LVT \registers_reg[6][19] ( + .CK(n_0_36), .D(registers[19]), .Q(registers_6__ap[19]), .QN(), .SE(dftIn), + .SI(registers_5__ap[19]) + ); + SDFF_X1_LVT \registers_reg[25][19] ( + .CK(n_0_55), .D(registers[19]), .Q(registers_25__ap[19]), .QN(), .SE(dftIn), + .SI(registers_30__ap[19]) + ); + AOI22_X1_LVT i_1_0_1072( + .A1(registers_6__ap[19]), .A2(n_1_0_1300), .B1(n_1_0_1269), .B2(registers_25__ap[19]), + .ZN(n_1_0_1020) + ); + NAND3_X1_LVT i_1_0_1071( + .A1(n_1_0_1022), .A2(n_1_0_1021), .A3(n_1_0_1020), .ZN(n_1_0_1019) + ); + SDFF_X1_LVT \registers_reg[19][19] ( + .CK(n_0_49), .D(registers[19]), .Q(registers_19__ap[19]), .QN(), .SE(dftIn), + .SI(registers_18__ap[19]) + ); + SDFF_X1_LVT \registers_reg[16][19] ( + .CK(n_0_46), .D(registers[19]), .Q(registers_16__ap[19]), .QN(), .SE(dftIn), + .SI(registers_13__ap[19]) + ); + AOI221_X1_LVT i_1_0_1070( + .A(n_1_0_1019), .B1(n_1_0_1295), .B2(registers_19__ap[19]), .C1(registers_16__ap[19]), + .C2(n_1_0_1267), .ZN(n_1_0_1018) + ); + SDFF_X1_LVT \registers_reg[9][19] ( + .CK(n_0_39), .D(registers[19]), .Q(registers_9__ap[19]), .QN(), .SE(dftIn), + .SI(registers_6__ap[19]) + ); + SDFF_X1_LVT \registers_reg[29][19] ( + .CK(n_0_59), .D(registers[19]), .Q(registers_29__ap[19]), .QN(), .SE(dftIn), + .SI(registers_25__ap[19]) + ); + AOI22_X1_LVT i_1_0_1069( + .A1(registers_9__ap[19]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[19]), + .ZN(n_1_0_1017) + ); + SDFF_X1_LVT \registers_reg[8][19] ( + .CK(n_0_38), .D(registers[19]), .Q(registers_8__ap[19]), .QN(), .SE(dftIn), + .SI(registers_9__ap[19]) + ); + SDFF_X1_LVT \registers_reg[23][19] ( + .CK(n_0_53), .D(registers[19]), .Q(registers_23__ap[19]), .QN(), .SE(dftIn), + .SI(registers_19__ap[19]) + ); + AOI22_X1_LVT i_1_0_1068( + .A1(registers_8__ap[19]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[19]), + .ZN(n_1_0_1016) + ); + SDFF_X1_LVT \registers_reg[7][19] ( + .CK(n_0_37), .D(registers[19]), .Q(registers_7__ap[19]), .QN(), .SE(dftIn), + .SI(registers_8__ap[19]) + ); + SDFF_X1_LVT \registers_reg[14][19] ( + .CK(n_0_44), .D(registers[19]), .Q(registers_14__ap[19]), .QN(), .SE(dftIn), + .SI(registers_16__ap[19]) + ); + AOI22_X1_LVT i_1_0_1067( + .A1(registers_7__ap[19]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[19]), + .ZN(n_1_0_1015) + ); + NAND3_X1_LVT i_1_0_1066( + .A1(n_1_0_1017), .A2(n_1_0_1016), .A3(n_1_0_1015), .ZN(n_1_0_1014) + ); + SDFF_X1_LVT \registers_reg[10][19] ( + .CK(n_0_40), .D(registers[19]), .Q(registers_10__ap[19]), .QN(), .SE(dftIn), + .SI(registers_14__ap[19]) + ); + SDFF_X1_LVT \registers_reg[3][19] ( + .CK(n_0_33), .D(registers[19]), .Q(registers_3__ap[19]), .QN(), .SE(dftIn), + .SI(registers_7__ap[19]) + ); + AOI221_X1_LVT i_1_0_1065( + .A(n_1_0_1014), .B1(n_1_0_1287), .B2(registers_10__ap[19]), .C1(registers_3__ap[19]), + .C2(n_1_0_1257), .ZN(n_1_0_1013) + ); + NAND4_X1_LVT i_1_0_1064( + .A1(n_1_0_1028), .A2(n_1_0_1023), .A3(n_1_0_1018), .A4(n_1_0_1013), .ZN(RRs1[19]) + ); + AND2_X1_LVT i_0_0_18( + .A1(n_0_0_16), .A2(WRd[18]), .ZN(registers[18]) + ); + SDFF_X1_LVT \registers_reg[24][18] ( + .CK(n_0_54), .D(registers[18]), .Q(registers_24__ap[18]), .QN(), .SE(dftIn), + .SI(registers_29__ap[19]) + ); + SDFF_X1_LVT \registers_reg[28][18] ( + .CK(n_0_58), .D(registers[18]), .Q(registers_28__ap[18]), .QN(), .SE(dftIn), + .SI(registers_24__ap[18]) + ); + AOI22_X1_LVT i_1_0_1062( + .A1(registers_24__ap[18]), .A2(n_1_0_1289), .B1(n_1_0_1283), .B2(registers_28__ap[18]), + .ZN(n_1_0_1011) + ); + SDFF_X1_LVT \registers_reg[11][18] ( + .CK(n_0_41), .D(registers[18]), .Q(registers_11__ap[18]), .QN(), .SE(dftIn), + .SI(registers_10__ap[19]) + ); + SDFF_X1_LVT \registers_reg[16][18] ( + .CK(n_0_46), .D(registers[18]), .Q(registers_16__ap[18]), .QN(), .SE(dftIn), + .SI(registers_11__ap[18]) + ); + AOI22_X1_LVT i_1_0_1063( + .A1(registers_11__ap[18]), .A2(n_1_0_1270), .B1(n_1_0_1267), .B2(registers_16__ap[18]), + .ZN(n_1_0_1012) + ); + SDFF_X1_LVT \registers_reg[9][18] ( + .CK(n_0_39), .D(registers[18]), .Q(registers_9__ap[18]), .QN(), .SE(dftIn), + .SI(registers_3__ap[19]) + ); + SDFF_X1_LVT \registers_reg[7][18] ( + .CK(n_0_37), .D(registers[18]), .Q(registers_7__ap[18]), .QN(), .SE(dftIn), + .SI(registers_9__ap[18]) + ); + AOI22_X1_LVT i_1_0_1061( + .A1(registers_9__ap[18]), .A2(n_1_0_1291), .B1(n_1_0_1263), .B2(registers_7__ap[18]), + .ZN(n_1_0_1010) + ); + SDFF_X1_LVT \registers_reg[27][18] ( + .CK(n_0_57), .D(registers[18]), .Q(registers_27__ap[18]), .QN(), .SE(dftIn), + .SI(registers_28__ap[18]) + ); + SDFF_X1_LVT \registers_reg[25][18] ( + .CK(n_0_55), .D(registers[18]), .Q(registers_25__ap[18]), .QN(), .SE(dftIn), + .SI(registers_27__ap[18]) + ); + AOI22_X1_LVT i_1_0_1060( + .A1(registers_27__ap[18]), .A2(n_1_0_1279), .B1(n_1_0_1269), .B2(registers_25__ap[18]), + .ZN(n_1_0_1009) + ); + NAND3_X1_LVT i_1_0_1059( + .A1(n_1_0_1012), .A2(n_1_0_1010), .A3(n_1_0_1009), .ZN(n_1_0_1008) + ); + SDFF_X1_LVT \registers_reg[31][18] ( + .CK(n_0_61), .D(registers[18]), .Q(registers_31__ap[18]), .QN(), .SE(dftIn), + .SI(registers_7__ap[18]) + ); + SDFF_X1_LVT \registers_reg[6][18] ( + .CK(n_0_36), .D(registers[18]), .Q(registers_6__ap[18]), .QN(), .SE(dftIn), + .SI(registers_31__ap[18]) + ); + AOI221_X1_LVT i_1_0_1058( + .A(n_1_0_1008), .B1(n_1_0_1266), .B2(registers_31__ap[18]), .C1(registers_6__ap[18]), + .C2(n_1_0_1300), .ZN(n_1_0_1007) + ); + SDFF_X1_LVT \registers_reg[22][18] ( + .CK(n_0_52), .D(registers[18]), .Q(registers_22__ap[18]), .QN(), .SE(dftIn), + .SI(registers_23__ap[19]) + ); + SDFF_X1_LVT \registers_reg[26][18] ( + .CK(n_0_56), .D(registers[18]), .Q(registers_26__ap[18]), .QN(), .SE(dftIn), + .SI(registers_25__ap[18]) + ); + SDFF_X1_LVT \registers_reg[1][18] ( + .CK(n_0_0), .D(registers[18]), .Q(registers_1__ap[18]), .QN(), .SE(dftIn), + .SI(registers_22__ap[18]) + ); + AOI222_X1_LVT i_1_0_1057( + .A1(registers_22__ap[18]), .A2(n_1_0_1294), .B1(n_1_0_1285), .B2(registers_26__ap[18]), + .C1(n_1_0_1274), .C2(registers_1__ap[18]), .ZN(n_1_0_1006) + ); + NAND2_X1_LVT i_1_0_1056( + .A1(n_1_0_1007), .A2(n_1_0_1006), .ZN(n_1_0_1005) + ); + SDFF_X1_LVT \registers_reg[29][18] ( + .CK(n_0_59), .D(registers[18]), .Q(registers_29__ap[18]), .QN(), .SE(dftIn), + .SI(registers_26__ap[18]) + ); + SDFF_X1_LVT \registers_reg[2][18] ( + .CK(n_0_32), .D(registers[18]), .Q(registers_2__ap[18]), .QN(), .SE(dftIn), + .SI(registers_29__ap[18]) + ); + AOI221_X1_LVT i_1_0_1055( + .A(n_1_0_1005), .B1(n_1_0_1276), .B2(registers_29__ap[18]), .C1(registers_2__ap[18]), + .C2(n_1_0_1268), .ZN(n_1_0_1004) + ); + SDFF_X1_LVT \registers_reg[18][18] ( + .CK(n_0_48), .D(registers[18]), .Q(registers_18__ap[18]), .QN(), .SE(dftIn), + .SI(registers_1__ap[18]) + ); + SDFF_X1_LVT \registers_reg[30][18] ( + .CK(n_0_60), .D(registers[18]), .Q(registers_30__ap[18]), .QN(), .SE(dftIn), + .SI(registers_2__ap[18]) + ); + AOI22_X1_LVT i_1_0_1054( + .A1(registers_18__ap[18]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[18]), + .ZN(n_1_0_1003) + ); + SDFF_X1_LVT \registers_reg[4][18] ( + .CK(n_0_34), .D(registers[18]), .Q(registers_4__ap[18]), .QN(), .SE(dftIn), + .SI(registers_6__ap[18]) + ); + SDFF_X1_LVT \registers_reg[12][18] ( + .CK(n_0_42), .D(registers[18]), .Q(registers_12__ap[18]), .QN(), .SE(dftIn), + .SI(registers_16__ap[18]) + ); + AOI22_X1_LVT i_1_0_1053( + .A1(registers_4__ap[18]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[18]), + .ZN(n_1_0_1002) + ); + SDFF_X1_LVT \registers_reg[19][18] ( + .CK(n_0_49), .D(registers[18]), .Q(registers_19__ap[18]), .QN(), .SE(dftIn), + .SI(registers_18__ap[18]) + ); + SDFF_X1_LVT \registers_reg[21][18] ( + .CK(n_0_51), .D(registers[18]), .Q(registers_21__ap[18]), .QN(), .SE(dftIn), + .SI(registers_19__ap[18]) + ); + AOI22_X1_LVT i_1_0_1052( + .A1(registers_19__ap[18]), .A2(n_1_0_1295), .B1(n_1_0_1259), .B2(registers_21__ap[18]), + .ZN(n_1_0_1001) + ); + NAND3_X1_LVT i_1_0_1051( + .A1(n_1_0_1003), .A2(n_1_0_1002), .A3(n_1_0_1001), .ZN(n_1_0_1000) + ); + SDFF_X1_LVT \registers_reg[5][18] ( + .CK(n_0_35), .D(registers[18]), .Q(registers_5__ap[18]), .QN(), .SE(dftIn), + .SI(registers_4__ap[18]) + ); + SDFF_X1_LVT \registers_reg[20][18] ( + .CK(n_0_50), .D(registers[18]), .Q(registers_20__ap[18]), .QN(), .SE(dftIn), + .SI(registers_21__ap[18]) + ); + AOI221_X1_LVT i_1_0_1050( + .A(n_1_0_1000), .B1(n_1_0_1273), .B2(registers_5__ap[18]), .C1(registers_20__ap[18]), + .C2(n_1_0_1281), .ZN(n_1_0_999) + ); + SDFF_X1_LVT \registers_reg[8][18] ( + .CK(n_0_38), .D(registers[18]), .Q(registers_8__ap[18]), .QN(), .SE(dftIn), + .SI(registers_5__ap[18]) + ); + SDFF_X1_LVT \registers_reg[23][18] ( + .CK(n_0_53), .D(registers[18]), .Q(registers_23__ap[18]), .QN(), .SE(dftIn), + .SI(registers_20__ap[18]) + ); + AOI22_X1_LVT i_1_0_1049( + .A1(registers_8__ap[18]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[18]), + .ZN(n_1_0_998) + ); + SDFF_X1_LVT \registers_reg[13][18] ( + .CK(n_0_43), .D(registers[18]), .Q(registers_13__ap[18]), .QN(), .SE(dftIn), + .SI(registers_12__ap[18]) + ); + SDFF_X1_LVT \registers_reg[17][18] ( + .CK(n_0_47), .D(registers[18]), .Q(registers_17__ap[18]), .QN(), .SE(dftIn), + .SI(registers_23__ap[18]) + ); + AOI22_X1_LVT i_1_0_1048( + .A1(registers_13__ap[18]), .A2(n_1_0_1277), .B1(n_1_0_1271), .B2(registers_17__ap[18]), + .ZN(n_1_0_997) + ); + SDFF_X1_LVT \registers_reg[15][18] ( + .CK(n_0_45), .D(registers[18]), .Q(registers_15__ap[18]), .QN(), .SE(dftIn), + .SI(registers_13__ap[18]) + ); + SDFF_X1_LVT \registers_reg[14][18] ( + .CK(n_0_44), .D(registers[18]), .Q(registers_14__ap[18]), .QN(), .SE(dftIn), + .SI(registers_15__ap[18]) + ); + AOI22_X1_LVT i_1_0_1047( + .A1(registers_15__ap[18]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[18]), + .ZN(n_1_0_996) + ); + NAND3_X1_LVT i_1_0_1046( + .A1(n_1_0_998), .A2(n_1_0_997), .A3(n_1_0_996), .ZN(n_1_0_995) + ); + SDFF_X1_LVT \registers_reg[10][18] ( + .CK(n_0_40), .D(registers[18]), .Q(registers_10__ap[18]), .QN(), .SE(dftIn), + .SI(registers_14__ap[18]) + ); + SDFF_X1_LVT \registers_reg[3][18] ( + .CK(n_0_33), .D(registers[18]), .Q(registers_3__ap[18]), .QN(), .SE(dftIn), + .SI(registers_8__ap[18]) + ); + AOI221_X1_LVT i_1_0_1045( + .A(n_1_0_995), .B1(n_1_0_1287), .B2(registers_10__ap[18]), .C1(registers_3__ap[18]), + .C2(n_1_0_1257), .ZN(n_1_0_994) + ); + NAND4_X1_LVT i_1_0_1044( + .A1(n_1_0_1011), .A2(n_1_0_1004), .A3(n_1_0_999), .A4(n_1_0_994), .ZN(RRs1[18]) + ); + AND2_X1_LVT i_0_0_17( + .A1(n_0_0_16), .A2(WRd[17]), .ZN(registers[17]) + ); + SDFF_X1_LVT \registers_reg[17][17] ( + .CK(n_0_47), .D(registers[17]), .Q(registers_17__ap[17]), .QN(), .SE(dftIn), + .SI(registers_17__ap[18]) + ); + SDFF_X1_LVT \registers_reg[21][17] ( + .CK(n_0_51), .D(registers[17]), .Q(registers_21__ap[17]), .QN(), .SE(dftIn), + .SI(registers_17__ap[17]) + ); + AOI22_X1_LVT i_1_0_1040( + .A1(registers_17__ap[17]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[17]), + .ZN(n_1_0_990) + ); + SDFF_X1_LVT \registers_reg[2][17] ( + .CK(n_0_32), .D(registers[17]), .Q(registers_2__ap[17]), .QN(), .SE(dftIn), + .SI(registers_30__ap[18]) + ); + SDFF_X1_LVT \registers_reg[31][17] ( + .CK(n_0_61), .D(registers[17]), .Q(registers_31__ap[17]), .QN(), .SE(dftIn), + .SI(registers_3__ap[18]) + ); + AOI22_X1_LVT i_1_0_1043( + .A1(registers_2__ap[17]), .A2(n_1_0_1268), .B1(n_1_0_1266), .B2(registers_31__ap[17]), + .ZN(n_1_0_993) + ); + SDFF_X1_LVT \registers_reg[20][17] ( + .CK(n_0_50), .D(registers[17]), .Q(registers_20__ap[17]), .QN(), .SE(dftIn), + .SI(registers_21__ap[17]) + ); + SDFF_X1_LVT \registers_reg[12][17] ( + .CK(n_0_42), .D(registers[17]), .Q(registers_12__ap[17]), .QN(), .SE(dftIn), + .SI(registers_10__ap[18]) + ); + AOI22_X1_LVT i_1_0_1039( + .A1(registers_20__ap[17]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[17]), + .ZN(n_1_0_989) + ); + SDFF_X1_LVT \registers_reg[15][17] ( + .CK(n_0_45), .D(registers[17]), .Q(registers_15__ap[17]), .QN(), .SE(dftIn), + .SI(registers_12__ap[17]) + ); + SDFF_X1_LVT \registers_reg[11][17] ( + .CK(n_0_41), .D(registers[17]), .Q(registers_11__ap[17]), .QN(), .SE(dftIn), + .SI(registers_15__ap[17]) + ); + AOI22_X1_LVT i_1_0_1042( + .A1(registers_15__ap[17]), .A2(n_1_0_1286), .B1(n_1_0_1270), .B2(registers_11__ap[17]), + .ZN(n_1_0_992) + ); + INV_X1_LVT i_1_0_1041( + .A(n_1_0_992), .ZN(n_1_0_991) + ); + SDFF_X1_LVT \registers_reg[10][17] ( + .CK(n_0_40), .D(registers[17]), .Q(registers_10__ap[17]), .QN(), .SE(dftIn), + .SI(registers_11__ap[17]) + ); + SDFF_X1_LVT \registers_reg[24][17] ( + .CK(n_0_54), .D(registers[17]), .Q(registers_24__ap[17]), .QN(), .SE(dftIn), + .SI(registers_2__ap[17]) + ); + AOI221_X1_LVT i_1_0_1038( + .A(n_1_0_991), .B1(n_1_0_1287), .B2(registers_10__ap[17]), .C1(registers_24__ap[17]), + .C2(n_1_0_1289), .ZN(n_1_0_988) + ); + SDFF_X1_LVT \registers_reg[22][17] ( + .CK(n_0_52), .D(registers[17]), .Q(registers_22__ap[17]), .QN(), .SE(dftIn), + .SI(registers_20__ap[17]) + ); + SDFF_X1_LVT \registers_reg[26][17] ( + .CK(n_0_56), .D(registers[17]), .Q(registers_26__ap[17]), .QN(), .SE(dftIn), + .SI(registers_24__ap[17]) + ); + SDFF_X1_LVT \registers_reg[13][17] ( + .CK(n_0_43), .D(registers[17]), .Q(registers_13__ap[17]), .QN(), .SE(dftIn), + .SI(registers_10__ap[17]) + ); + AOI222_X1_LVT i_1_0_1037( + .A1(registers_22__ap[17]), .A2(n_1_0_1294), .B1(n_1_0_1285), .B2(registers_26__ap[17]), + .C1(n_1_0_1277), .C2(registers_13__ap[17]), .ZN(n_1_0_987) + ); + NAND4_X1_LVT i_1_0_1036( + .A1(n_1_0_993), .A2(n_1_0_989), .A3(n_1_0_988), .A4(n_1_0_987), .ZN(n_1_0_986) + ); + SDFF_X1_LVT \registers_reg[1][17] ( + .CK(n_0_0), .D(registers[17]), .Q(registers_1__ap[17]), .QN(), .SE(dftIn), + .SI(registers_22__ap[17]) + ); + SDFF_X1_LVT \registers_reg[28][17] ( + .CK(n_0_58), .D(registers[17]), .Q(registers_28__ap[17]), .QN(), .SE(dftIn), + .SI(registers_26__ap[17]) + ); + AOI221_X1_LVT i_1_0_1035( + .A(n_1_0_986), .B1(n_1_0_1274), .B2(registers_1__ap[17]), .C1(registers_28__ap[17]), + .C2(n_1_0_1283), .ZN(n_1_0_985) + ); + SDFF_X1_LVT \registers_reg[18][17] ( + .CK(n_0_48), .D(registers[17]), .Q(registers_18__ap[17]), .QN(), .SE(dftIn), + .SI(registers_1__ap[17]) + ); + SDFF_X1_LVT \registers_reg[30][17] ( + .CK(n_0_60), .D(registers[17]), .Q(registers_30__ap[17]), .QN(), .SE(dftIn), + .SI(registers_28__ap[17]) + ); + AOI22_X1_LVT i_1_0_1034( + .A1(registers_18__ap[17]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[17]), + .ZN(n_1_0_984) + ); + SDFF_X1_LVT \registers_reg[4][17] ( + .CK(n_0_34), .D(registers[17]), .Q(registers_4__ap[17]), .QN(), .SE(dftIn), + .SI(registers_31__ap[17]) + ); + SDFF_X1_LVT \registers_reg[5][17] ( + .CK(n_0_35), .D(registers[17]), .Q(registers_5__ap[17]), .QN(), .SE(dftIn), + .SI(registers_4__ap[17]) + ); + AOI22_X1_LVT i_1_0_1033( + .A1(registers_4__ap[17]), .A2(n_1_0_1278), .B1(n_1_0_1273), .B2(registers_5__ap[17]), + .ZN(n_1_0_983) + ); + SDFF_X1_LVT \registers_reg[6][17] ( + .CK(n_0_36), .D(registers[17]), .Q(registers_6__ap[17]), .QN(), .SE(dftIn), + .SI(registers_5__ap[17]) + ); + SDFF_X1_LVT \registers_reg[25][17] ( + .CK(n_0_55), .D(registers[17]), .Q(registers_25__ap[17]), .QN(), .SE(dftIn), + .SI(registers_30__ap[17]) + ); + AOI22_X1_LVT i_1_0_1032( + .A1(registers_6__ap[17]), .A2(n_1_0_1300), .B1(n_1_0_1269), .B2(registers_25__ap[17]), + .ZN(n_1_0_982) + ); + NAND3_X1_LVT i_1_0_1031( + .A1(n_1_0_984), .A2(n_1_0_983), .A3(n_1_0_982), .ZN(n_1_0_981) + ); + SDFF_X1_LVT \registers_reg[19][17] ( + .CK(n_0_49), .D(registers[17]), .Q(registers_19__ap[17]), .QN(), .SE(dftIn), + .SI(registers_18__ap[17]) + ); + SDFF_X1_LVT \registers_reg[16][17] ( + .CK(n_0_46), .D(registers[17]), .Q(registers_16__ap[17]), .QN(), .SE(dftIn), + .SI(registers_13__ap[17]) + ); + AOI221_X1_LVT i_1_0_1030( + .A(n_1_0_981), .B1(n_1_0_1295), .B2(registers_19__ap[17]), .C1(registers_16__ap[17]), + .C2(n_1_0_1267), .ZN(n_1_0_980) + ); + SDFF_X1_LVT \registers_reg[7][17] ( + .CK(n_0_37), .D(registers[17]), .Q(registers_7__ap[17]), .QN(), .SE(dftIn), + .SI(registers_6__ap[17]) + ); + SDFF_X1_LVT \registers_reg[14][17] ( + .CK(n_0_44), .D(registers[17]), .Q(registers_14__ap[17]), .QN(), .SE(dftIn), + .SI(registers_16__ap[17]) + ); + AOI22_X1_LVT i_1_0_1029( + .A1(registers_7__ap[17]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[17]), + .ZN(n_1_0_979) + ); + SDFF_X1_LVT \registers_reg[9][17] ( + .CK(n_0_39), .D(registers[17]), .Q(registers_9__ap[17]), .QN(), .SE(dftIn), + .SI(registers_7__ap[17]) + ); + SDFF_X1_LVT \registers_reg[29][17] ( + .CK(n_0_59), .D(registers[17]), .Q(registers_29__ap[17]), .QN(), .SE(dftIn), + .SI(registers_25__ap[17]) + ); + AOI22_X1_LVT i_1_0_1028( + .A1(registers_9__ap[17]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[17]), + .ZN(n_1_0_978) + ); + SDFF_X1_LVT \registers_reg[8][17] ( + .CK(n_0_38), .D(registers[17]), .Q(registers_8__ap[17]), .QN(), .SE(dftIn), + .SI(registers_9__ap[17]) + ); + SDFF_X1_LVT \registers_reg[23][17] ( + .CK(n_0_53), .D(registers[17]), .Q(registers_23__ap[17]), .QN(), .SE(dftIn), + .SI(registers_19__ap[17]) + ); + AOI22_X1_LVT i_1_0_1027( + .A1(registers_8__ap[17]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[17]), + .ZN(n_1_0_977) + ); + NAND3_X1_LVT i_1_0_1026( + .A1(n_1_0_979), .A2(n_1_0_978), .A3(n_1_0_977), .ZN(n_1_0_976) + ); + SDFF_X1_LVT \registers_reg[27][17] ( + .CK(n_0_57), .D(registers[17]), .Q(registers_27__ap[17]), .QN(), .SE(dftIn), + .SI(registers_29__ap[17]) + ); + SDFF_X1_LVT \registers_reg[3][17] ( + .CK(n_0_33), .D(registers[17]), .Q(registers_3__ap[17]), .QN(), .SE(dftIn), + .SI(registers_8__ap[17]) + ); + AOI221_X1_LVT i_1_0_1025( + .A(n_1_0_976), .B1(n_1_0_1279), .B2(registers_27__ap[17]), .C1(registers_3__ap[17]), + .C2(n_1_0_1257), .ZN(n_1_0_975) + ); + NAND4_X1_LVT i_1_0_1024( + .A1(n_1_0_990), .A2(n_1_0_985), .A3(n_1_0_980), .A4(n_1_0_975), .ZN(RRs1[17]) + ); + AND2_X1_LVT i_0_0_16( + .A1(n_0_0_16), .A2(WRd[16]), .ZN(registers[16]) + ); + SDFF_X1_LVT \registers_reg[29][16] ( + .CK(n_0_59), .D(registers[16]), .Q(registers_29__ap[16]), .QN(), .SE(dftIn), + .SI(registers_27__ap[17]) + ); + SDFF_X1_LVT \registers_reg[2][16] ( + .CK(n_0_32), .D(registers[16]), .Q(registers_2__ap[16]), .QN(), .SE(dftIn), + .SI(registers_29__ap[16]) + ); + AOI22_X1_LVT i_1_0_1022( + .A1(registers_29__ap[16]), .A2(n_1_0_1276), .B1(n_1_0_1268), .B2(registers_2__ap[16]), + .ZN(n_1_0_973) + ); + SDFF_X1_LVT \registers_reg[11][16] ( + .CK(n_0_41), .D(registers[16]), .Q(registers_11__ap[16]), .QN(), .SE(dftIn), + .SI(registers_14__ap[17]) + ); + SDFF_X1_LVT \registers_reg[25][16] ( + .CK(n_0_55), .D(registers[16]), .Q(registers_25__ap[16]), .QN(), .SE(dftIn), + .SI(registers_2__ap[16]) + ); + AOI22_X1_LVT i_1_0_1023( + .A1(registers_11__ap[16]), .A2(n_1_0_1270), .B1(n_1_0_1269), .B2(registers_25__ap[16]), + .ZN(n_1_0_974) + ); + SDFF_X1_LVT \registers_reg[9][16] ( + .CK(n_0_39), .D(registers[16]), .Q(registers_9__ap[16]), .QN(), .SE(dftIn), + .SI(registers_3__ap[17]) + ); + SDFF_X1_LVT \registers_reg[7][16] ( + .CK(n_0_37), .D(registers[16]), .Q(registers_7__ap[16]), .QN(), .SE(dftIn), + .SI(registers_9__ap[16]) + ); + AOI22_X1_LVT i_1_0_1021( + .A1(registers_9__ap[16]), .A2(n_1_0_1291), .B1(n_1_0_1263), .B2(registers_7__ap[16]), + .ZN(n_1_0_972) + ); + SDFF_X1_LVT \registers_reg[10][16] ( + .CK(n_0_40), .D(registers[16]), .Q(registers_10__ap[16]), .QN(), .SE(dftIn), + .SI(registers_11__ap[16]) + ); + SDFF_X1_LVT \registers_reg[16][16] ( + .CK(n_0_46), .D(registers[16]), .Q(registers_16__ap[16]), .QN(), .SE(dftIn), + .SI(registers_10__ap[16]) + ); + AOI22_X1_LVT i_1_0_1020( + .A1(registers_10__ap[16]), .A2(n_1_0_1287), .B1(n_1_0_1267), .B2(registers_16__ap[16]), + .ZN(n_1_0_971) + ); + NAND3_X1_LVT i_1_0_1019( + .A1(n_1_0_974), .A2(n_1_0_972), .A3(n_1_0_971), .ZN(n_1_0_970) + ); + SDFF_X1_LVT \registers_reg[31][16] ( + .CK(n_0_61), .D(registers[16]), .Q(registers_31__ap[16]), .QN(), .SE(dftIn), + .SI(registers_7__ap[16]) + ); + SDFF_X1_LVT \registers_reg[6][16] ( + .CK(n_0_36), .D(registers[16]), .Q(registers_6__ap[16]), .QN(), .SE(dftIn), + .SI(registers_31__ap[16]) + ); + AOI221_X1_LVT i_1_0_1018( + .A(n_1_0_970), .B1(n_1_0_1266), .B2(registers_31__ap[16]), .C1(registers_6__ap[16]), + .C2(n_1_0_1300), .ZN(n_1_0_969) + ); + SDFF_X1_LVT \registers_reg[18][16] ( + .CK(n_0_48), .D(registers[16]), .Q(registers_18__ap[16]), .QN(), .SE(dftIn), + .SI(registers_23__ap[17]) + ); + SDFF_X1_LVT \registers_reg[22][16] ( + .CK(n_0_52), .D(registers[16]), .Q(registers_22__ap[16]), .QN(), .SE(dftIn), + .SI(registers_18__ap[16]) + ); + SDFF_X1_LVT \registers_reg[1][16] ( + .CK(n_0_0), .D(registers[16]), .Q(registers_1__ap[16]), .QN(), .SE(dftIn), + .SI(registers_22__ap[16]) + ); + AOI222_X1_LVT i_1_0_1017( + .A1(registers_18__ap[16]), .A2(n_1_0_1297), .B1(n_1_0_1294), .B2(registers_22__ap[16]), + .C1(registers_1__ap[16]), .C2(n_1_0_1274), .ZN(n_1_0_968) + ); + NAND3_X1_LVT i_1_0_1016( + .A1(n_1_0_973), .A2(n_1_0_969), .A3(n_1_0_968), .ZN(n_1_0_967) + ); + SDFF_X1_LVT \registers_reg[5][16] ( + .CK(n_0_35), .D(registers[16]), .Q(registers_5__ap[16]), .QN(), .SE(dftIn), + .SI(registers_6__ap[16]) + ); + SDFF_X1_LVT \registers_reg[28][16] ( + .CK(n_0_58), .D(registers[16]), .Q(registers_28__ap[16]), .QN(), .SE(dftIn), + .SI(registers_25__ap[16]) + ); + AOI221_X1_LVT i_1_0_1015( + .A(n_1_0_967), .B1(n_1_0_1273), .B2(registers_5__ap[16]), .C1(registers_28__ap[16]), + .C2(n_1_0_1283), .ZN(n_1_0_966) + ); + SDFF_X1_LVT \registers_reg[4][16] ( + .CK(n_0_34), .D(registers[16]), .Q(registers_4__ap[16]), .QN(), .SE(dftIn), + .SI(registers_5__ap[16]) + ); + SDFF_X1_LVT \registers_reg[12][16] ( + .CK(n_0_42), .D(registers[16]), .Q(registers_12__ap[16]), .QN(), .SE(dftIn), + .SI(registers_16__ap[16]) + ); + AOI22_X1_LVT i_1_0_1014( + .A1(registers_4__ap[16]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[16]), + .ZN(n_1_0_965) + ); + SDFF_X1_LVT \registers_reg[19][16] ( + .CK(n_0_49), .D(registers[16]), .Q(registers_19__ap[16]), .QN(), .SE(dftIn), + .SI(registers_1__ap[16]) + ); + SDFF_X1_LVT \registers_reg[21][16] ( + .CK(n_0_51), .D(registers[16]), .Q(registers_21__ap[16]), .QN(), .SE(dftIn), + .SI(registers_19__ap[16]) + ); + AOI22_X1_LVT i_1_0_1013( + .A1(registers_19__ap[16]), .A2(n_1_0_1295), .B1(n_1_0_1259), .B2(registers_21__ap[16]), + .ZN(n_1_0_964) + ); + SDFF_X1_LVT \registers_reg[24][16] ( + .CK(n_0_54), .D(registers[16]), .Q(registers_24__ap[16]), .QN(), .SE(dftIn), + .SI(registers_28__ap[16]) + ); + SDFF_X1_LVT \registers_reg[20][16] ( + .CK(n_0_50), .D(registers[16]), .Q(registers_20__ap[16]), .QN(), .SE(dftIn), + .SI(registers_21__ap[16]) + ); + AOI22_X1_LVT i_1_0_1012( + .A1(registers_24__ap[16]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[16]), + .ZN(n_1_0_963) + ); + NAND3_X1_LVT i_1_0_1011( + .A1(n_1_0_965), .A2(n_1_0_964), .A3(n_1_0_963), .ZN(n_1_0_962) + ); + SDFF_X1_LVT \registers_reg[26][16] ( + .CK(n_0_56), .D(registers[16]), .Q(registers_26__ap[16]), .QN(), .SE(dftIn), + .SI(registers_24__ap[16]) + ); + SDFF_X1_LVT \registers_reg[30][16] ( + .CK(n_0_60), .D(registers[16]), .Q(registers_30__ap[16]), .QN(), .SE(dftIn), + .SI(registers_26__ap[16]) + ); + AOI221_X1_LVT i_1_0_1010( + .A(n_1_0_962), .B1(n_1_0_1285), .B2(registers_26__ap[16]), .C1(registers_30__ap[16]), + .C2(n_1_0_1272), .ZN(n_1_0_961) + ); + SDFF_X1_LVT \registers_reg[8][16] ( + .CK(n_0_38), .D(registers[16]), .Q(registers_8__ap[16]), .QN(), .SE(dftIn), + .SI(registers_4__ap[16]) + ); + SDFF_X1_LVT \registers_reg[23][16] ( + .CK(n_0_53), .D(registers[16]), .Q(registers_23__ap[16]), .QN(), .SE(dftIn), + .SI(registers_20__ap[16]) + ); + AOI22_X1_LVT i_1_0_1009( + .A1(registers_8__ap[16]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[16]), + .ZN(n_1_0_960) + ); + SDFF_X1_LVT \registers_reg[13][16] ( + .CK(n_0_43), .D(registers[16]), .Q(registers_13__ap[16]), .QN(), .SE(dftIn), + .SI(registers_12__ap[16]) + ); + SDFF_X1_LVT \registers_reg[17][16] ( + .CK(n_0_47), .D(registers[16]), .Q(registers_17__ap[16]), .QN(), .SE(dftIn), + .SI(registers_23__ap[16]) + ); + AOI22_X1_LVT i_1_0_1008( + .A1(registers_13__ap[16]), .A2(n_1_0_1277), .B1(n_1_0_1271), .B2(registers_17__ap[16]), + .ZN(n_1_0_959) + ); + SDFF_X1_LVT \registers_reg[15][16] ( + .CK(n_0_45), .D(registers[16]), .Q(registers_15__ap[16]), .QN(), .SE(dftIn), + .SI(registers_13__ap[16]) + ); + SDFF_X1_LVT \registers_reg[14][16] ( + .CK(n_0_44), .D(registers[16]), .Q(registers_14__ap[16]), .QN(), .SE(dftIn), + .SI(registers_15__ap[16]) + ); + AOI22_X1_LVT i_1_0_1007( + .A1(registers_15__ap[16]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[16]), + .ZN(n_1_0_958) + ); + NAND3_X1_LVT i_1_0_1006( + .A1(n_1_0_960), .A2(n_1_0_959), .A3(n_1_0_958), .ZN(n_1_0_957) + ); + SDFF_X1_LVT \registers_reg[27][16] ( + .CK(n_0_57), .D(registers[16]), .Q(registers_27__ap[16]), .QN(), .SE(dftIn), + .SI(registers_30__ap[16]) + ); + SDFF_X1_LVT \registers_reg[3][16] ( + .CK(n_0_33), .D(registers[16]), .Q(registers_3__ap[16]), .QN(), .SE(dftIn), + .SI(registers_8__ap[16]) + ); + AOI221_X1_LVT i_1_0_1005( + .A(n_1_0_957), .B1(n_1_0_1279), .B2(registers_27__ap[16]), .C1(registers_3__ap[16]), + .C2(n_1_0_1257), .ZN(n_1_0_956) + ); + NAND3_X1_LVT i_1_0_1004( + .A1(n_1_0_966), .A2(n_1_0_961), .A3(n_1_0_956), .ZN(RRs1[16]) + ); + AND2_X1_LVT i_0_0_15( + .A1(n_0_0_16), .A2(WRd[15]), .ZN(registers[15]) + ); + SDFF_X1_LVT \registers_reg[17][15] ( + .CK(n_0_47), .D(registers[15]), .Q(registers_17__ap[15]), .QN(), .SE(dftIn), + .SI(registers_17__ap[16]) + ); + SDFF_X1_LVT \registers_reg[21][15] ( + .CK(n_0_51), .D(registers[15]), .Q(registers_21__ap[15]), .QN(), .SE(dftIn), + .SI(registers_17__ap[15]) + ); + AOI22_X1_LVT i_1_0_1000( + .A1(registers_17__ap[15]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[15]), + .ZN(n_1_0_952) + ); + SDFF_X1_LVT \registers_reg[10][15] ( + .CK(n_0_40), .D(registers[15]), .Q(registers_10__ap[15]), .QN(), .SE(dftIn), + .SI(registers_14__ap[16]) + ); + SDFF_X1_LVT \registers_reg[2][15] ( + .CK(n_0_32), .D(registers[15]), .Q(registers_2__ap[15]), .QN(), .SE(dftIn), + .SI(registers_27__ap[16]) + ); + AOI22_X1_LVT i_1_0_1003( + .A1(registers_10__ap[15]), .A2(n_1_0_1287), .B1(n_1_0_1268), .B2(registers_2__ap[15]), + .ZN(n_1_0_955) + ); + SDFF_X1_LVT \registers_reg[20][15] ( + .CK(n_0_50), .D(registers[15]), .Q(registers_20__ap[15]), .QN(), .SE(dftIn), + .SI(registers_21__ap[15]) + ); + SDFF_X1_LVT \registers_reg[12][15] ( + .CK(n_0_42), .D(registers[15]), .Q(registers_12__ap[15]), .QN(), .SE(dftIn), + .SI(registers_10__ap[15]) + ); + AOI22_X1_LVT i_1_0_999( + .A1(registers_20__ap[15]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[15]), + .ZN(n_1_0_951) + ); + SDFF_X1_LVT \registers_reg[15][15] ( + .CK(n_0_45), .D(registers[15]), .Q(registers_15__ap[15]), .QN(), .SE(dftIn), + .SI(registers_12__ap[15]) + ); + SDFF_X1_LVT \registers_reg[8][15] ( + .CK(n_0_38), .D(registers[15]), .Q(registers_8__ap[15]), .QN(), .SE(dftIn), + .SI(registers_3__ap[16]) + ); + AOI22_X1_LVT i_1_0_1002( + .A1(registers_15__ap[15]), .A2(n_1_0_1286), .B1(n_1_0_1282), .B2(registers_8__ap[15]), + .ZN(n_1_0_954) + ); + INV_X1_LVT i_1_0_1001( + .A(n_1_0_954), .ZN(n_1_0_953) + ); + SDFF_X1_LVT \registers_reg[11][15] ( + .CK(n_0_41), .D(registers[15]), .Q(registers_11__ap[15]), .QN(), .SE(dftIn), + .SI(registers_15__ap[15]) + ); + SDFF_X1_LVT \registers_reg[24][15] ( + .CK(n_0_54), .D(registers[15]), .Q(registers_24__ap[15]), .QN(), .SE(dftIn), + .SI(registers_2__ap[15]) + ); + AOI221_X1_LVT i_1_0_998( + .A(n_1_0_953), .B1(n_1_0_1270), .B2(registers_11__ap[15]), .C1(registers_24__ap[15]), + .C2(n_1_0_1289), .ZN(n_1_0_950) + ); + SDFF_X1_LVT \registers_reg[13][15] ( + .CK(n_0_43), .D(registers[15]), .Q(registers_13__ap[15]), .QN(), .SE(dftIn), + .SI(registers_11__ap[15]) + ); + SDFF_X1_LVT \registers_reg[30][15] ( + .CK(n_0_60), .D(registers[15]), .Q(registers_30__ap[15]), .QN(), .SE(dftIn), + .SI(registers_24__ap[15]) + ); + SDFF_X1_LVT \registers_reg[22][15] ( + .CK(n_0_52), .D(registers[15]), .Q(registers_22__ap[15]), .QN(), .SE(dftIn), + .SI(registers_20__ap[15]) + ); + AOI222_X1_LVT i_1_0_997( + .A1(registers_13__ap[15]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[15]), + .C1(registers_22__ap[15]), .C2(n_1_0_1294), .ZN(n_1_0_949) + ); + NAND4_X1_LVT i_1_0_996( + .A1(n_1_0_955), .A2(n_1_0_951), .A3(n_1_0_950), .A4(n_1_0_949), .ZN(n_1_0_948) + ); + SDFF_X1_LVT \registers_reg[1][15] ( + .CK(n_0_0), .D(registers[15]), .Q(registers_1__ap[15]), .QN(), .SE(dftIn), + .SI(registers_22__ap[15]) + ); + SDFF_X1_LVT \registers_reg[28][15] ( + .CK(n_0_58), .D(registers[15]), .Q(registers_28__ap[15]), .QN(), .SE(dftIn), + .SI(registers_30__ap[15]) + ); + AOI221_X1_LVT i_1_0_995( + .A(n_1_0_948), .B1(n_1_0_1274), .B2(registers_1__ap[15]), .C1(registers_28__ap[15]), + .C2(n_1_0_1283), .ZN(n_1_0_947) + ); + SDFF_X1_LVT \registers_reg[18][15] ( + .CK(n_0_48), .D(registers[15]), .Q(registers_18__ap[15]), .QN(), .SE(dftIn), + .SI(registers_1__ap[15]) + ); + SDFF_X1_LVT \registers_reg[26][15] ( + .CK(n_0_56), .D(registers[15]), .Q(registers_26__ap[15]), .QN(), .SE(dftIn), + .SI(registers_28__ap[15]) + ); + AOI22_X1_LVT i_1_0_994( + .A1(registers_18__ap[15]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[15]), + .ZN(n_1_0_946) + ); + SDFF_X1_LVT \registers_reg[4][15] ( + .CK(n_0_34), .D(registers[15]), .Q(registers_4__ap[15]), .QN(), .SE(dftIn), + .SI(registers_8__ap[15]) + ); + SDFF_X1_LVT \registers_reg[5][15] ( + .CK(n_0_35), .D(registers[15]), .Q(registers_5__ap[15]), .QN(), .SE(dftIn), + .SI(registers_4__ap[15]) + ); + AOI22_X1_LVT i_1_0_993( + .A1(registers_4__ap[15]), .A2(n_1_0_1278), .B1(n_1_0_1273), .B2(registers_5__ap[15]), + .ZN(n_1_0_945) + ); + SDFF_X1_LVT \registers_reg[6][15] ( + .CK(n_0_36), .D(registers[15]), .Q(registers_6__ap[15]), .QN(), .SE(dftIn), + .SI(registers_5__ap[15]) + ); + SDFF_X1_LVT \registers_reg[16][15] ( + .CK(n_0_46), .D(registers[15]), .Q(registers_16__ap[15]), .QN(), .SE(dftIn), + .SI(registers_13__ap[15]) + ); + AOI22_X1_LVT i_1_0_992( + .A1(registers_6__ap[15]), .A2(n_1_0_1300), .B1(n_1_0_1267), .B2(registers_16__ap[15]), + .ZN(n_1_0_944) + ); + NAND3_X1_LVT i_1_0_991( + .A1(n_1_0_946), .A2(n_1_0_945), .A3(n_1_0_944), .ZN(n_1_0_943) + ); + SDFF_X1_LVT \registers_reg[19][15] ( + .CK(n_0_49), .D(registers[15]), .Q(registers_19__ap[15]), .QN(), .SE(dftIn), + .SI(registers_18__ap[15]) + ); + SDFF_X1_LVT \registers_reg[25][15] ( + .CK(n_0_55), .D(registers[15]), .Q(registers_25__ap[15]), .QN(), .SE(dftIn), + .SI(registers_26__ap[15]) + ); + AOI221_X1_LVT i_1_0_990( + .A(n_1_0_943), .B1(n_1_0_1295), .B2(registers_19__ap[15]), .C1(registers_25__ap[15]), + .C2(n_1_0_1269), .ZN(n_1_0_942) + ); + SDFF_X1_LVT \registers_reg[7][15] ( + .CK(n_0_37), .D(registers[15]), .Q(registers_7__ap[15]), .QN(), .SE(dftIn), + .SI(registers_6__ap[15]) + ); + SDFF_X1_LVT \registers_reg[14][15] ( + .CK(n_0_44), .D(registers[15]), .Q(registers_14__ap[15]), .QN(), .SE(dftIn), + .SI(registers_16__ap[15]) + ); + AOI22_X1_LVT i_1_0_989( + .A1(registers_7__ap[15]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[15]), + .ZN(n_1_0_941) + ); + SDFF_X1_LVT \registers_reg[9][15] ( + .CK(n_0_39), .D(registers[15]), .Q(registers_9__ap[15]), .QN(), .SE(dftIn), + .SI(registers_7__ap[15]) + ); + SDFF_X1_LVT \registers_reg[29][15] ( + .CK(n_0_59), .D(registers[15]), .Q(registers_29__ap[15]), .QN(), .SE(dftIn), + .SI(registers_25__ap[15]) + ); + AOI22_X1_LVT i_1_0_988( + .A1(registers_9__ap[15]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[15]), + .ZN(n_1_0_940) + ); + SDFF_X1_LVT \registers_reg[23][15] ( + .CK(n_0_53), .D(registers[15]), .Q(registers_23__ap[15]), .QN(), .SE(dftIn), + .SI(registers_19__ap[15]) + ); + SDFF_X1_LVT \registers_reg[3][15] ( + .CK(n_0_33), .D(registers[15]), .Q(registers_3__ap[15]), .QN(), .SE(dftIn), + .SI(registers_9__ap[15]) + ); + AOI22_X1_LVT i_1_0_987( + .A1(registers_23__ap[15]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[15]), + .ZN(n_1_0_939) + ); + NAND3_X1_LVT i_1_0_986( + .A1(n_1_0_941), .A2(n_1_0_940), .A3(n_1_0_939), .ZN(n_1_0_938) + ); + SDFF_X1_LVT \registers_reg[27][15] ( + .CK(n_0_57), .D(registers[15]), .Q(registers_27__ap[15]), .QN(), .SE(dftIn), + .SI(registers_29__ap[15]) + ); + SDFF_X1_LVT \registers_reg[31][15] ( + .CK(n_0_61), .D(registers[15]), .Q(registers_31__ap[15]), .QN(), .SE(dftIn), + .SI(registers_3__ap[15]) + ); + AOI221_X1_LVT i_1_0_985( + .A(n_1_0_938), .B1(n_1_0_1279), .B2(registers_27__ap[15]), .C1(registers_31__ap[15]), + .C2(n_1_0_1266), .ZN(n_1_0_937) + ); + NAND4_X1_LVT i_1_0_984( + .A1(n_1_0_952), .A2(n_1_0_947), .A3(n_1_0_942), .A4(n_1_0_937), .ZN(RRs1[15]) + ); + AND2_X1_LVT i_0_0_14( + .A1(n_0_0_16), .A2(WRd[14]), .ZN(registers[14]) + ); + SDFF_X1_LVT \registers_reg[28][14] ( + .CK(n_0_58), .D(registers[14]), .Q(registers_28__ap[14]), .QN(), .SE(dftIn), + .SI(registers_27__ap[15]) + ); + SDFF_X1_LVT \registers_reg[5][14] ( + .CK(n_0_35), .D(registers[14]), .Q(registers_5__ap[14]), .QN(), .SE(dftIn), + .SI(registers_31__ap[15]) + ); + AOI22_X1_LVT i_1_0_983( + .A1(registers_28__ap[14]), .A2(n_1_0_1283), .B1(n_1_0_1273), .B2(registers_5__ap[14]), + .ZN(n_1_0_936) + ); + SDFF_X1_LVT \registers_reg[18][14] ( + .CK(n_0_48), .D(registers[14]), .Q(registers_18__ap[14]), .QN(), .SE(dftIn), + .SI(registers_23__ap[15]) + ); + SDFF_X1_LVT \registers_reg[10][14] ( + .CK(n_0_40), .D(registers[14]), .Q(registers_10__ap[14]), .QN(), .SE(dftIn), + .SI(registers_14__ap[15]) + ); + SDFF_X1_LVT \registers_reg[8][14] ( + .CK(n_0_38), .D(registers[14]), .Q(registers_8__ap[14]), .QN(), .SE(dftIn), + .SI(registers_5__ap[14]) + ); + AOI222_X1_LVT i_1_0_982( + .A1(registers_18__ap[14]), .A2(n_1_0_1297), .B1(n_1_0_1287), .B2(registers_10__ap[14]), + .C1(n_1_0_1282), .C2(registers_8__ap[14]), .ZN(n_1_0_935) + ); + SDFF_X1_LVT \registers_reg[9][14] ( + .CK(n_0_39), .D(registers[14]), .Q(registers_9__ap[14]), .QN(), .SE(dftIn), + .SI(registers_8__ap[14]) + ); + SDFF_X1_LVT \registers_reg[29][14] ( + .CK(n_0_59), .D(registers[14]), .Q(registers_29__ap[14]), .QN(), .SE(dftIn), + .SI(registers_28__ap[14]) + ); + AOI22_X1_LVT i_1_0_981( + .A1(registers_9__ap[14]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[14]), + .ZN(n_1_0_934) + ); + SDFF_X1_LVT \registers_reg[21][14] ( + .CK(n_0_51), .D(registers[14]), .Q(registers_21__ap[14]), .QN(), .SE(dftIn), + .SI(registers_18__ap[14]) + ); + SDFF_X1_LVT \registers_reg[14][14] ( + .CK(n_0_44), .D(registers[14]), .Q(registers_14__ap[14]), .QN(), .SE(dftIn), + .SI(registers_10__ap[14]) + ); + AOI22_X1_LVT i_1_0_980( + .A1(registers_21__ap[14]), .A2(n_1_0_1259), .B1(n_1_0_1258), .B2(registers_14__ap[14]), + .ZN(n_1_0_933) + ); + SDFF_X1_LVT \registers_reg[16][14] ( + .CK(n_0_46), .D(registers[14]), .Q(registers_16__ap[14]), .QN(), .SE(dftIn), + .SI(registers_14__ap[14]) + ); + SDFF_X1_LVT \registers_reg[3][14] ( + .CK(n_0_33), .D(registers[14]), .Q(registers_3__ap[14]), .QN(), .SE(dftIn), + .SI(registers_9__ap[14]) + ); + AOI22_X1_LVT i_1_0_979( + .A1(registers_16__ap[14]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[14]), + .ZN(n_1_0_932) + ); + SDFF_X1_LVT \registers_reg[17][14] ( + .CK(n_0_47), .D(registers[14]), .Q(registers_17__ap[14]), .QN(), .SE(dftIn), + .SI(registers_21__ap[14]) + ); + SDFF_X1_LVT \registers_reg[31][14] ( + .CK(n_0_61), .D(registers[14]), .Q(registers_31__ap[14]), .QN(), .SE(dftIn), + .SI(registers_3__ap[14]) + ); + AOI22_X1_LVT i_1_0_978( + .A1(registers_17__ap[14]), .A2(n_1_0_1271), .B1(n_1_0_1266), .B2(registers_31__ap[14]), + .ZN(n_1_0_931) + ); + SDFF_X1_LVT \registers_reg[15][14] ( + .CK(n_0_45), .D(registers[14]), .Q(registers_15__ap[14]), .QN(), .SE(dftIn), + .SI(registers_16__ap[14]) + ); + SDFF_X1_LVT \registers_reg[23][14] ( + .CK(n_0_53), .D(registers[14]), .Q(registers_23__ap[14]), .QN(), .SE(dftIn), + .SI(registers_17__ap[14]) + ); + AOI22_X1_LVT i_1_0_977( + .A1(registers_15__ap[14]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[14]), + .ZN(n_1_0_930) + ); + NAND4_X1_LVT i_1_0_976( + .A1(n_1_0_933), .A2(n_1_0_932), .A3(n_1_0_931), .A4(n_1_0_930), .ZN(n_1_0_929) + ); + SDFF_X1_LVT \registers_reg[26][14] ( + .CK(n_0_56), .D(registers[14]), .Q(registers_26__ap[14]), .QN(), .SE(dftIn), + .SI(registers_29__ap[14]) + ); + SDFF_X1_LVT \registers_reg[30][14] ( + .CK(n_0_60), .D(registers[14]), .Q(registers_30__ap[14]), .QN(), .SE(dftIn), + .SI(registers_26__ap[14]) + ); + AOI22_X1_LVT i_1_0_975( + .A1(registers_26__ap[14]), .A2(n_1_0_1285), .B1(n_1_0_1272), .B2(registers_30__ap[14]), + .ZN(n_1_0_928) + ); + SDFF_X1_LVT \registers_reg[20][14] ( + .CK(n_0_50), .D(registers[14]), .Q(registers_20__ap[14]), .QN(), .SE(dftIn), + .SI(registers_23__ap[14]) + ); + SDFF_X1_LVT \registers_reg[4][14] ( + .CK(n_0_34), .D(registers[14]), .Q(registers_4__ap[14]), .QN(), .SE(dftIn), + .SI(registers_31__ap[14]) + ); + AOI22_X1_LVT i_1_0_974( + .A1(registers_20__ap[14]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[14]), + .ZN(n_1_0_927) + ); + SDFF_X1_LVT \registers_reg[1][14] ( + .CK(n_0_0), .D(registers[14]), .Q(registers_1__ap[14]), .QN(), .SE(dftIn), + .SI(registers_20__ap[14]) + ); + SDFF_X1_LVT \registers_reg[2][14] ( + .CK(n_0_32), .D(registers[14]), .Q(registers_2__ap[14]), .QN(), .SE(dftIn), + .SI(registers_30__ap[14]) + ); + AOI22_X1_LVT i_1_0_973( + .A1(registers_1__ap[14]), .A2(n_1_0_1274), .B1(n_1_0_1268), .B2(registers_2__ap[14]), + .ZN(n_1_0_926) + ); + SDFF_X1_LVT \registers_reg[24][14] ( + .CK(n_0_54), .D(registers[14]), .Q(registers_24__ap[14]), .QN(), .SE(dftIn), + .SI(registers_2__ap[14]) + ); + SDFF_X1_LVT \registers_reg[12][14] ( + .CK(n_0_42), .D(registers[14]), .Q(registers_12__ap[14]), .QN(), .SE(dftIn), + .SI(registers_15__ap[14]) + ); + AOI22_X1_LVT i_1_0_972( + .A1(registers_24__ap[14]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[14]), + .ZN(n_1_0_925) + ); + NAND4_X1_LVT i_1_0_971( + .A1(n_1_0_928), .A2(n_1_0_927), .A3(n_1_0_926), .A4(n_1_0_925), .ZN(n_1_0_924) + ); + SDFF_X1_LVT \registers_reg[19][14] ( + .CK(n_0_49), .D(registers[14]), .Q(registers_19__ap[14]), .QN(), .SE(dftIn), + .SI(registers_1__ap[14]) + ); + SDFF_X1_LVT \registers_reg[22][14] ( + .CK(n_0_52), .D(registers[14]), .Q(registers_22__ap[14]), .QN(), .SE(dftIn), + .SI(registers_19__ap[14]) + ); + AOI22_X1_LVT i_1_0_970( + .A1(registers_19__ap[14]), .A2(n_1_0_1295), .B1(n_1_0_1294), .B2(registers_22__ap[14]), + .ZN(n_1_0_923) + ); + SDFF_X1_LVT \registers_reg[13][14] ( + .CK(n_0_43), .D(registers[14]), .Q(registers_13__ap[14]), .QN(), .SE(dftIn), + .SI(registers_12__ap[14]) + ); + SDFF_X1_LVT \registers_reg[25][14] ( + .CK(n_0_55), .D(registers[14]), .Q(registers_25__ap[14]), .QN(), .SE(dftIn), + .SI(registers_24__ap[14]) + ); + AOI22_X1_LVT i_1_0_969( + .A1(registers_13__ap[14]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[14]), + .ZN(n_1_0_922) + ); + SDFF_X1_LVT \registers_reg[6][14] ( + .CK(n_0_36), .D(registers[14]), .Q(registers_6__ap[14]), .QN(), .SE(dftIn), + .SI(registers_4__ap[14]) + ); + SDFF_X1_LVT \registers_reg[7][14] ( + .CK(n_0_37), .D(registers[14]), .Q(registers_7__ap[14]), .QN(), .SE(dftIn), + .SI(registers_6__ap[14]) + ); + AOI22_X1_LVT i_1_0_968( + .A1(registers_6__ap[14]), .A2(n_1_0_1300), .B1(n_1_0_1263), .B2(registers_7__ap[14]), + .ZN(n_1_0_921) + ); + SDFF_X1_LVT \registers_reg[27][14] ( + .CK(n_0_57), .D(registers[14]), .Q(registers_27__ap[14]), .QN(), .SE(dftIn), + .SI(registers_25__ap[14]) + ); + SDFF_X1_LVT \registers_reg[11][14] ( + .CK(n_0_41), .D(registers[14]), .Q(registers_11__ap[14]), .QN(), .SE(dftIn), + .SI(registers_13__ap[14]) + ); + AOI22_X1_LVT i_1_0_967( + .A1(registers_27__ap[14]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[14]), + .ZN(n_1_0_920) + ); + NAND4_X1_LVT i_1_0_966( + .A1(n_1_0_923), .A2(n_1_0_922), .A3(n_1_0_921), .A4(n_1_0_920), .ZN(n_1_0_919) + ); + NOR3_X1_LVT i_1_0_965( + .A1(n_1_0_929), .A2(n_1_0_924), .A3(n_1_0_919), .ZN(n_1_0_918) + ); + NAND4_X1_LVT i_1_0_964( + .A1(n_1_0_936), .A2(n_1_0_935), .A3(n_1_0_934), .A4(n_1_0_918), .ZN(RRs1[14]) + ); + AND2_X1_LVT i_0_0_13( + .A1(n_0_0_16), .A2(WRd[13]), .ZN(registers[13]) + ); + SDFF_X1_LVT \registers_reg[28][13] ( + .CK(n_0_58), .D(registers[13]), .Q(registers_28__ap[13]), .QN(), .SE(dftIn), + .SI(registers_27__ap[14]) + ); + SDFF_X1_LVT \registers_reg[4][13] ( + .CK(n_0_34), .D(registers[13]), .Q(registers_4__ap[13]), .QN(), .SE(dftIn), + .SI(registers_7__ap[14]) + ); + AOI22_X1_LVT i_1_0_963( + .A1(registers_28__ap[13]), .A2(n_1_0_1283), .B1(n_1_0_1278), .B2(registers_4__ap[13]), + .ZN(n_1_0_917) + ); + SDFF_X1_LVT \registers_reg[10][13] ( + .CK(n_0_40), .D(registers[13]), .Q(registers_10__ap[13]), .QN(), .SE(dftIn), + .SI(registers_11__ap[14]) + ); + SDFF_X1_LVT \registers_reg[26][13] ( + .CK(n_0_56), .D(registers[13]), .Q(registers_26__ap[13]), .QN(), .SE(dftIn), + .SI(registers_28__ap[13]) + ); + SDFF_X1_LVT \registers_reg[8][13] ( + .CK(n_0_38), .D(registers[13]), .Q(registers_8__ap[13]), .QN(), .SE(dftIn), + .SI(registers_4__ap[13]) + ); + AOI222_X1_LVT i_1_0_962( + .A1(registers_10__ap[13]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[13]), + .C1(registers_8__ap[13]), .C2(n_1_0_1282), .ZN(n_1_0_916) + ); + SDFF_X1_LVT \registers_reg[9][13] ( + .CK(n_0_39), .D(registers[13]), .Q(registers_9__ap[13]), .QN(), .SE(dftIn), + .SI(registers_8__ap[13]) + ); + SDFF_X1_LVT \registers_reg[29][13] ( + .CK(n_0_59), .D(registers[13]), .Q(registers_29__ap[13]), .QN(), .SE(dftIn), + .SI(registers_26__ap[13]) + ); + AOI22_X1_LVT i_1_0_961( + .A1(registers_9__ap[13]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[13]), + .ZN(n_1_0_915) + ); + SDFF_X1_LVT \registers_reg[6][13] ( + .CK(n_0_36), .D(registers[13]), .Q(registers_6__ap[13]), .QN(), .SE(dftIn), + .SI(registers_9__ap[13]) + ); + SDFF_X1_LVT \registers_reg[1][13] ( + .CK(n_0_0), .D(registers[13]), .Q(registers_1__ap[13]), .QN(), .SE(dftIn), + .SI(registers_22__ap[14]) + ); + AOI22_X1_LVT i_1_0_960( + .A1(registers_6__ap[13]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[13]), + .ZN(n_1_0_914) + ); + SDFF_X1_LVT \registers_reg[5][13] ( + .CK(n_0_35), .D(registers[13]), .Q(registers_5__ap[13]), .QN(), .SE(dftIn), + .SI(registers_6__ap[13]) + ); + SDFF_X1_LVT \registers_reg[3][13] ( + .CK(n_0_33), .D(registers[13]), .Q(registers_3__ap[13]), .QN(), .SE(dftIn), + .SI(registers_5__ap[13]) + ); + AOI22_X1_LVT i_1_0_959( + .A1(registers_5__ap[13]), .A2(n_1_0_1273), .B1(n_1_0_1257), .B2(registers_3__ap[13]), + .ZN(n_1_0_913) + ); + SDFF_X1_LVT \registers_reg[16][13] ( + .CK(n_0_46), .D(registers[13]), .Q(registers_16__ap[13]), .QN(), .SE(dftIn), + .SI(registers_10__ap[13]) + ); + SDFF_X1_LVT \registers_reg[31][13] ( + .CK(n_0_61), .D(registers[13]), .Q(registers_31__ap[13]), .QN(), .SE(dftIn), + .SI(registers_3__ap[13]) + ); + AOI22_X1_LVT i_1_0_958( + .A1(registers_16__ap[13]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[13]), + .ZN(n_1_0_912) + ); + SDFF_X1_LVT \registers_reg[15][13] ( + .CK(n_0_45), .D(registers[13]), .Q(registers_15__ap[13]), .QN(), .SE(dftIn), + .SI(registers_16__ap[13]) + ); + SDFF_X1_LVT \registers_reg[23][13] ( + .CK(n_0_53), .D(registers[13]), .Q(registers_23__ap[13]), .QN(), .SE(dftIn), + .SI(registers_1__ap[13]) + ); + AOI22_X1_LVT i_1_0_957( + .A1(registers_15__ap[13]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[13]), + .ZN(n_1_0_911) + ); + NAND4_X1_LVT i_1_0_956( + .A1(n_1_0_914), .A2(n_1_0_913), .A3(n_1_0_912), .A4(n_1_0_911), .ZN(n_1_0_910) + ); + SDFF_X1_LVT \registers_reg[18][13] ( + .CK(n_0_48), .D(registers[13]), .Q(registers_18__ap[13]), .QN(), .SE(dftIn), + .SI(registers_23__ap[13]) + ); + SDFF_X1_LVT \registers_reg[30][13] ( + .CK(n_0_60), .D(registers[13]), .Q(registers_30__ap[13]), .QN(), .SE(dftIn), + .SI(registers_29__ap[13]) + ); + AOI22_X1_LVT i_1_0_955( + .A1(registers_18__ap[13]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[13]), + .ZN(n_1_0_909) + ); + SDFF_X1_LVT \registers_reg[24][13] ( + .CK(n_0_54), .D(registers[13]), .Q(registers_24__ap[13]), .QN(), .SE(dftIn), + .SI(registers_30__ap[13]) + ); + SDFF_X1_LVT \registers_reg[12][13] ( + .CK(n_0_42), .D(registers[13]), .Q(registers_12__ap[13]), .QN(), .SE(dftIn), + .SI(registers_15__ap[13]) + ); + AOI22_X1_LVT i_1_0_954( + .A1(registers_24__ap[13]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[13]), + .ZN(n_1_0_908) + ); + SDFF_X1_LVT \registers_reg[22][13] ( + .CK(n_0_52), .D(registers[13]), .Q(registers_22__ap[13]), .QN(), .SE(dftIn), + .SI(registers_18__ap[13]) + ); + SDFF_X1_LVT \registers_reg[21][13] ( + .CK(n_0_51), .D(registers[13]), .Q(registers_21__ap[13]), .QN(), .SE(dftIn), + .SI(registers_22__ap[13]) + ); + AOI22_X1_LVT i_1_0_953( + .A1(registers_22__ap[13]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[13]), + .ZN(n_1_0_907) + ); + SDFF_X1_LVT \registers_reg[20][13] ( + .CK(n_0_50), .D(registers[13]), .Q(registers_20__ap[13]), .QN(), .SE(dftIn), + .SI(registers_21__ap[13]) + ); + SDFF_X1_LVT \registers_reg[17][13] ( + .CK(n_0_47), .D(registers[13]), .Q(registers_17__ap[13]), .QN(), .SE(dftIn), + .SI(registers_20__ap[13]) + ); + AOI22_X1_LVT i_1_0_952( + .A1(registers_20__ap[13]), .A2(n_1_0_1281), .B1(n_1_0_1271), .B2(registers_17__ap[13]), + .ZN(n_1_0_906) + ); + NAND4_X1_LVT i_1_0_951( + .A1(n_1_0_909), .A2(n_1_0_908), .A3(n_1_0_907), .A4(n_1_0_906), .ZN(n_1_0_905) + ); + SDFF_X1_LVT \registers_reg[13][13] ( + .CK(n_0_43), .D(registers[13]), .Q(registers_13__ap[13]), .QN(), .SE(dftIn), + .SI(registers_12__ap[13]) + ); + SDFF_X1_LVT \registers_reg[25][13] ( + .CK(n_0_55), .D(registers[13]), .Q(registers_25__ap[13]), .QN(), .SE(dftIn), + .SI(registers_24__ap[13]) + ); + AOI22_X1_LVT i_1_0_950( + .A1(registers_13__ap[13]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[13]), + .ZN(n_1_0_904) + ); + SDFF_X1_LVT \registers_reg[19][13] ( + .CK(n_0_49), .D(registers[13]), .Q(registers_19__ap[13]), .QN(), .SE(dftIn), + .SI(registers_17__ap[13]) + ); + SDFF_X1_LVT \registers_reg[2][13] ( + .CK(n_0_32), .D(registers[13]), .Q(registers_2__ap[13]), .QN(), .SE(dftIn), + .SI(registers_25__ap[13]) + ); + AOI22_X1_LVT i_1_0_949( + .A1(registers_19__ap[13]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[13]), + .ZN(n_1_0_903) + ); + SDFF_X1_LVT \registers_reg[7][13] ( + .CK(n_0_37), .D(registers[13]), .Q(registers_7__ap[13]), .QN(), .SE(dftIn), + .SI(registers_31__ap[13]) + ); + SDFF_X1_LVT \registers_reg[14][13] ( + .CK(n_0_44), .D(registers[13]), .Q(registers_14__ap[13]), .QN(), .SE(dftIn), + .SI(registers_13__ap[13]) + ); + AOI22_X1_LVT i_1_0_948( + .A1(registers_7__ap[13]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[13]), + .ZN(n_1_0_902) + ); + SDFF_X1_LVT \registers_reg[27][13] ( + .CK(n_0_57), .D(registers[13]), .Q(registers_27__ap[13]), .QN(), .SE(dftIn), + .SI(registers_2__ap[13]) + ); + SDFF_X1_LVT \registers_reg[11][13] ( + .CK(n_0_41), .D(registers[13]), .Q(registers_11__ap[13]), .QN(), .SE(dftIn), + .SI(registers_14__ap[13]) + ); + AOI22_X1_LVT i_1_0_947( + .A1(registers_27__ap[13]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[13]), + .ZN(n_1_0_901) + ); + NAND4_X1_LVT i_1_0_946( + .A1(n_1_0_904), .A2(n_1_0_903), .A3(n_1_0_902), .A4(n_1_0_901), .ZN(n_1_0_900) + ); + NOR3_X1_LVT i_1_0_945( + .A1(n_1_0_910), .A2(n_1_0_905), .A3(n_1_0_900), .ZN(n_1_0_899) + ); + NAND4_X1_LVT i_1_0_944( + .A1(n_1_0_917), .A2(n_1_0_916), .A3(n_1_0_915), .A4(n_1_0_899), .ZN(RRs1[13]) + ); + AND2_X1_LVT i_0_0_12( + .A1(n_0_0_16), .A2(WRd[12]), .ZN(registers[12]) + ); + SDFF_X1_LVT \registers_reg[28][12] ( + .CK(n_0_58), .D(registers[12]), .Q(registers_28__ap[12]), .QN(), .SE(dftIn), + .SI(registers_27__ap[13]) + ); + SDFF_X1_LVT \registers_reg[17][12] ( + .CK(n_0_47), .D(registers[12]), .Q(registers_17__ap[12]), .QN(), .SE(dftIn), + .SI(registers_19__ap[13]) + ); + AOI22_X1_LVT i_1_0_943( + .A1(registers_28__ap[12]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[12]), + .ZN(n_1_0_898) + ); + SDFF_X1_LVT \registers_reg[10][12] ( + .CK(n_0_40), .D(registers[12]), .Q(registers_10__ap[12]), .QN(), .SE(dftIn), + .SI(registers_11__ap[13]) + ); + SDFF_X1_LVT \registers_reg[26][12] ( + .CK(n_0_56), .D(registers[12]), .Q(registers_26__ap[12]), .QN(), .SE(dftIn), + .SI(registers_28__ap[12]) + ); + SDFF_X1_LVT \registers_reg[8][12] ( + .CK(n_0_38), .D(registers[12]), .Q(registers_8__ap[12]), .QN(), .SE(dftIn), + .SI(registers_7__ap[13]) + ); + AOI222_X1_LVT i_1_0_942( + .A1(registers_10__ap[12]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[12]), + .C1(registers_8__ap[12]), .C2(n_1_0_1282), .ZN(n_1_0_897) + ); + SDFF_X1_LVT \registers_reg[9][12] ( + .CK(n_0_39), .D(registers[12]), .Q(registers_9__ap[12]), .QN(), .SE(dftIn), + .SI(registers_8__ap[12]) + ); + SDFF_X1_LVT \registers_reg[29][12] ( + .CK(n_0_59), .D(registers[12]), .Q(registers_29__ap[12]), .QN(), .SE(dftIn), + .SI(registers_26__ap[12]) + ); + AOI22_X1_LVT i_1_0_941( + .A1(registers_9__ap[12]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[12]), + .ZN(n_1_0_896) + ); + SDFF_X1_LVT \registers_reg[6][12] ( + .CK(n_0_36), .D(registers[12]), .Q(registers_6__ap[12]), .QN(), .SE(dftIn), + .SI(registers_9__ap[12]) + ); + SDFF_X1_LVT \registers_reg[1][12] ( + .CK(n_0_0), .D(registers[12]), .Q(registers_1__ap[12]), .QN(), .SE(dftIn), + .SI(registers_17__ap[12]) + ); + AOI22_X1_LVT i_1_0_940( + .A1(registers_6__ap[12]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[12]), + .ZN(n_1_0_895) + ); + SDFF_X1_LVT \registers_reg[16][12] ( + .CK(n_0_46), .D(registers[12]), .Q(registers_16__ap[12]), .QN(), .SE(dftIn), + .SI(registers_10__ap[12]) + ); + SDFF_X1_LVT \registers_reg[3][12] ( + .CK(n_0_33), .D(registers[12]), .Q(registers_3__ap[12]), .QN(), .SE(dftIn), + .SI(registers_6__ap[12]) + ); + AOI22_X1_LVT i_1_0_939( + .A1(registers_16__ap[12]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[12]), + .ZN(n_1_0_894) + ); + SDFF_X1_LVT \registers_reg[5][12] ( + .CK(n_0_35), .D(registers[12]), .Q(registers_5__ap[12]), .QN(), .SE(dftIn), + .SI(registers_3__ap[12]) + ); + SDFF_X1_LVT \registers_reg[31][12] ( + .CK(n_0_61), .D(registers[12]), .Q(registers_31__ap[12]), .QN(), .SE(dftIn), + .SI(registers_5__ap[12]) + ); + AOI22_X1_LVT i_1_0_938( + .A1(registers_5__ap[12]), .A2(n_1_0_1273), .B1(n_1_0_1266), .B2(registers_31__ap[12]), + .ZN(n_1_0_893) + ); + SDFF_X1_LVT \registers_reg[15][12] ( + .CK(n_0_45), .D(registers[12]), .Q(registers_15__ap[12]), .QN(), .SE(dftIn), + .SI(registers_16__ap[12]) + ); + SDFF_X1_LVT \registers_reg[23][12] ( + .CK(n_0_53), .D(registers[12]), .Q(registers_23__ap[12]), .QN(), .SE(dftIn), + .SI(registers_1__ap[12]) + ); + AOI22_X1_LVT i_1_0_937( + .A1(registers_15__ap[12]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[12]), + .ZN(n_1_0_892) + ); + NAND4_X1_LVT i_1_0_936( + .A1(n_1_0_895), .A2(n_1_0_894), .A3(n_1_0_893), .A4(n_1_0_892), .ZN(n_1_0_891) + ); + SDFF_X1_LVT \registers_reg[18][12] ( + .CK(n_0_48), .D(registers[12]), .Q(registers_18__ap[12]), .QN(), .SE(dftIn), + .SI(registers_23__ap[12]) + ); + SDFF_X1_LVT \registers_reg[30][12] ( + .CK(n_0_60), .D(registers[12]), .Q(registers_30__ap[12]), .QN(), .SE(dftIn), + .SI(registers_29__ap[12]) + ); + AOI22_X1_LVT i_1_0_935( + .A1(registers_18__ap[12]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[12]), + .ZN(n_1_0_890) + ); + SDFF_X1_LVT \registers_reg[20][12] ( + .CK(n_0_50), .D(registers[12]), .Q(registers_20__ap[12]), .QN(), .SE(dftIn), + .SI(registers_18__ap[12]) + ); + SDFF_X1_LVT \registers_reg[4][12] ( + .CK(n_0_34), .D(registers[12]), .Q(registers_4__ap[12]), .QN(), .SE(dftIn), + .SI(registers_31__ap[12]) + ); + AOI22_X1_LVT i_1_0_934( + .A1(registers_20__ap[12]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[12]), + .ZN(n_1_0_889) + ); + SDFF_X1_LVT \registers_reg[22][12] ( + .CK(n_0_52), .D(registers[12]), .Q(registers_22__ap[12]), .QN(), .SE(dftIn), + .SI(registers_20__ap[12]) + ); + SDFF_X1_LVT \registers_reg[21][12] ( + .CK(n_0_51), .D(registers[12]), .Q(registers_21__ap[12]), .QN(), .SE(dftIn), + .SI(registers_22__ap[12]) + ); + AOI22_X1_LVT i_1_0_933( + .A1(registers_22__ap[12]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[12]), + .ZN(n_1_0_888) + ); + SDFF_X1_LVT \registers_reg[24][12] ( + .CK(n_0_54), .D(registers[12]), .Q(registers_24__ap[12]), .QN(), .SE(dftIn), + .SI(registers_30__ap[12]) + ); + SDFF_X1_LVT \registers_reg[12][12] ( + .CK(n_0_42), .D(registers[12]), .Q(registers_12__ap[12]), .QN(), .SE(dftIn), + .SI(registers_15__ap[12]) + ); + AOI22_X1_LVT i_1_0_932( + .A1(registers_24__ap[12]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[12]), + .ZN(n_1_0_887) + ); + NAND4_X1_LVT i_1_0_931( + .A1(n_1_0_890), .A2(n_1_0_889), .A3(n_1_0_888), .A4(n_1_0_887), .ZN(n_1_0_886) + ); + SDFF_X1_LVT \registers_reg[13][12] ( + .CK(n_0_43), .D(registers[12]), .Q(registers_13__ap[12]), .QN(), .SE(dftIn), + .SI(registers_12__ap[12]) + ); + SDFF_X1_LVT \registers_reg[25][12] ( + .CK(n_0_55), .D(registers[12]), .Q(registers_25__ap[12]), .QN(), .SE(dftIn), + .SI(registers_24__ap[12]) + ); + AOI22_X1_LVT i_1_0_930( + .A1(registers_13__ap[12]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[12]), + .ZN(n_1_0_885) + ); + SDFF_X1_LVT \registers_reg[19][12] ( + .CK(n_0_49), .D(registers[12]), .Q(registers_19__ap[12]), .QN(), .SE(dftIn), + .SI(registers_21__ap[12]) + ); + SDFF_X1_LVT \registers_reg[2][12] ( + .CK(n_0_32), .D(registers[12]), .Q(registers_2__ap[12]), .QN(), .SE(dftIn), + .SI(registers_25__ap[12]) + ); + AOI22_X1_LVT i_1_0_929( + .A1(registers_19__ap[12]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[12]), + .ZN(n_1_0_884) + ); + SDFF_X1_LVT \registers_reg[7][12] ( + .CK(n_0_37), .D(registers[12]), .Q(registers_7__ap[12]), .QN(), .SE(dftIn), + .SI(registers_4__ap[12]) + ); + SDFF_X1_LVT \registers_reg[14][12] ( + .CK(n_0_44), .D(registers[12]), .Q(registers_14__ap[12]), .QN(), .SE(dftIn), + .SI(registers_13__ap[12]) + ); + AOI22_X1_LVT i_1_0_928( + .A1(registers_7__ap[12]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[12]), + .ZN(n_1_0_883) + ); + SDFF_X1_LVT \registers_reg[27][12] ( + .CK(n_0_57), .D(registers[12]), .Q(registers_27__ap[12]), .QN(), .SE(dftIn), + .SI(registers_2__ap[12]) + ); + SDFF_X1_LVT \registers_reg[11][12] ( + .CK(n_0_41), .D(registers[12]), .Q(registers_11__ap[12]), .QN(), .SE(dftIn), + .SI(registers_14__ap[12]) + ); + AOI22_X1_LVT i_1_0_927( + .A1(registers_27__ap[12]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[12]), + .ZN(n_1_0_882) + ); + NAND4_X1_LVT i_1_0_926( + .A1(n_1_0_885), .A2(n_1_0_884), .A3(n_1_0_883), .A4(n_1_0_882), .ZN(n_1_0_881) + ); + NOR3_X1_LVT i_1_0_925( + .A1(n_1_0_891), .A2(n_1_0_886), .A3(n_1_0_881), .ZN(n_1_0_880) + ); + NAND4_X1_LVT i_1_0_924( + .A1(n_1_0_898), .A2(n_1_0_897), .A3(n_1_0_896), .A4(n_1_0_880), .ZN(RRs1[12]) + ); + AND2_X1_LVT i_0_0_11( + .A1(n_0_0_16), .A2(WRd[11]), .ZN(registers[11]) + ); + SDFF_X1_LVT \registers_reg[28][11] ( + .CK(n_0_58), .D(registers[11]), .Q(registers_28__ap[11]), .QN(), .SE(dftIn), + .SI(registers_27__ap[12]) + ); + SDFF_X1_LVT \registers_reg[17][11] ( + .CK(n_0_47), .D(registers[11]), .Q(registers_17__ap[11]), .QN(), .SE(dftIn), + .SI(registers_19__ap[12]) + ); + AOI22_X1_LVT i_1_0_923( + .A1(registers_28__ap[11]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[11]), + .ZN(n_1_0_879) + ); + SDFF_X1_LVT \registers_reg[10][11] ( + .CK(n_0_40), .D(registers[11]), .Q(registers_10__ap[11]), .QN(), .SE(dftIn), + .SI(registers_11__ap[12]) + ); + SDFF_X1_LVT \registers_reg[26][11] ( + .CK(n_0_56), .D(registers[11]), .Q(registers_26__ap[11]), .QN(), .SE(dftIn), + .SI(registers_28__ap[11]) + ); + SDFF_X1_LVT \registers_reg[8][11] ( + .CK(n_0_38), .D(registers[11]), .Q(registers_8__ap[11]), .QN(), .SE(dftIn), + .SI(registers_7__ap[12]) + ); + AOI222_X1_LVT i_1_0_922( + .A1(registers_10__ap[11]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[11]), + .C1(registers_8__ap[11]), .C2(n_1_0_1282), .ZN(n_1_0_878) + ); + SDFF_X1_LVT \registers_reg[9][11] ( + .CK(n_0_39), .D(registers[11]), .Q(registers_9__ap[11]), .QN(), .SE(dftIn), + .SI(registers_8__ap[11]) + ); + SDFF_X1_LVT \registers_reg[29][11] ( + .CK(n_0_59), .D(registers[11]), .Q(registers_29__ap[11]), .QN(), .SE(dftIn), + .SI(registers_26__ap[11]) + ); + AOI22_X1_LVT i_1_0_921( + .A1(registers_9__ap[11]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[11]), + .ZN(n_1_0_877) + ); + SDFF_X1_LVT \registers_reg[6][11] ( + .CK(n_0_36), .D(registers[11]), .Q(registers_6__ap[11]), .QN(), .SE(dftIn), + .SI(registers_9__ap[11]) + ); + SDFF_X1_LVT \registers_reg[1][11] ( + .CK(n_0_0), .D(registers[11]), .Q(registers_1__ap[11]), .QN(), .SE(dftIn), + .SI(registers_17__ap[11]) + ); + AOI22_X1_LVT i_1_0_920( + .A1(registers_6__ap[11]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[11]), + .ZN(n_1_0_876) + ); + SDFF_X1_LVT \registers_reg[5][11] ( + .CK(n_0_35), .D(registers[11]), .Q(registers_5__ap[11]), .QN(), .SE(dftIn), + .SI(registers_6__ap[11]) + ); + SDFF_X1_LVT \registers_reg[3][11] ( + .CK(n_0_33), .D(registers[11]), .Q(registers_3__ap[11]), .QN(), .SE(dftIn), + .SI(registers_5__ap[11]) + ); + AOI22_X1_LVT i_1_0_919( + .A1(registers_5__ap[11]), .A2(n_1_0_1273), .B1(n_1_0_1257), .B2(registers_3__ap[11]), + .ZN(n_1_0_875) + ); + SDFF_X1_LVT \registers_reg[16][11] ( + .CK(n_0_46), .D(registers[11]), .Q(registers_16__ap[11]), .QN(), .SE(dftIn), + .SI(registers_10__ap[11]) + ); + SDFF_X1_LVT \registers_reg[31][11] ( + .CK(n_0_61), .D(registers[11]), .Q(registers_31__ap[11]), .QN(), .SE(dftIn), + .SI(registers_3__ap[11]) + ); + AOI22_X1_LVT i_1_0_918( + .A1(registers_16__ap[11]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[11]), + .ZN(n_1_0_874) + ); + SDFF_X1_LVT \registers_reg[15][11] ( + .CK(n_0_45), .D(registers[11]), .Q(registers_15__ap[11]), .QN(), .SE(dftIn), + .SI(registers_16__ap[11]) + ); + SDFF_X1_LVT \registers_reg[23][11] ( + .CK(n_0_53), .D(registers[11]), .Q(registers_23__ap[11]), .QN(), .SE(dftIn), + .SI(registers_1__ap[11]) + ); + AOI22_X1_LVT i_1_0_917( + .A1(registers_15__ap[11]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[11]), + .ZN(n_1_0_873) + ); + NAND4_X1_LVT i_1_0_916( + .A1(n_1_0_876), .A2(n_1_0_875), .A3(n_1_0_874), .A4(n_1_0_873), .ZN(n_1_0_872) + ); + SDFF_X1_LVT \registers_reg[18][11] ( + .CK(n_0_48), .D(registers[11]), .Q(registers_18__ap[11]), .QN(), .SE(dftIn), + .SI(registers_23__ap[11]) + ); + SDFF_X1_LVT \registers_reg[30][11] ( + .CK(n_0_60), .D(registers[11]), .Q(registers_30__ap[11]), .QN(), .SE(dftIn), + .SI(registers_29__ap[11]) + ); + AOI22_X1_LVT i_1_0_915( + .A1(registers_18__ap[11]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[11]), + .ZN(n_1_0_871) + ); + SDFF_X1_LVT \registers_reg[20][11] ( + .CK(n_0_50), .D(registers[11]), .Q(registers_20__ap[11]), .QN(), .SE(dftIn), + .SI(registers_18__ap[11]) + ); + SDFF_X1_LVT \registers_reg[4][11] ( + .CK(n_0_34), .D(registers[11]), .Q(registers_4__ap[11]), .QN(), .SE(dftIn), + .SI(registers_31__ap[11]) + ); + AOI22_X1_LVT i_1_0_914( + .A1(registers_20__ap[11]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[11]), + .ZN(n_1_0_870) + ); + SDFF_X1_LVT \registers_reg[22][11] ( + .CK(n_0_52), .D(registers[11]), .Q(registers_22__ap[11]), .QN(), .SE(dftIn), + .SI(registers_20__ap[11]) + ); + SDFF_X1_LVT \registers_reg[21][11] ( + .CK(n_0_51), .D(registers[11]), .Q(registers_21__ap[11]), .QN(), .SE(dftIn), + .SI(registers_22__ap[11]) + ); + AOI22_X1_LVT i_1_0_913( + .A1(registers_22__ap[11]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[11]), + .ZN(n_1_0_869) + ); + SDFF_X1_LVT \registers_reg[24][11] ( + .CK(n_0_54), .D(registers[11]), .Q(registers_24__ap[11]), .QN(), .SE(dftIn), + .SI(registers_30__ap[11]) + ); + SDFF_X1_LVT \registers_reg[12][11] ( + .CK(n_0_42), .D(registers[11]), .Q(registers_12__ap[11]), .QN(), .SE(dftIn), + .SI(registers_15__ap[11]) + ); + AOI22_X1_LVT i_1_0_912( + .A1(registers_24__ap[11]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[11]), + .ZN(n_1_0_868) + ); + NAND4_X1_LVT i_1_0_911( + .A1(n_1_0_871), .A2(n_1_0_870), .A3(n_1_0_869), .A4(n_1_0_868), .ZN(n_1_0_867) + ); + SDFF_X1_LVT \registers_reg[13][11] ( + .CK(n_0_43), .D(registers[11]), .Q(registers_13__ap[11]), .QN(), .SE(dftIn), + .SI(registers_12__ap[11]) + ); + SDFF_X1_LVT \registers_reg[25][11] ( + .CK(n_0_55), .D(registers[11]), .Q(registers_25__ap[11]), .QN(), .SE(dftIn), + .SI(registers_24__ap[11]) + ); + AOI22_X1_LVT i_1_0_910( + .A1(registers_13__ap[11]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[11]), + .ZN(n_1_0_866) + ); + SDFF_X1_LVT \registers_reg[19][11] ( + .CK(n_0_49), .D(registers[11]), .Q(registers_19__ap[11]), .QN(), .SE(dftIn), + .SI(registers_21__ap[11]) + ); + SDFF_X1_LVT \registers_reg[2][11] ( + .CK(n_0_32), .D(registers[11]), .Q(registers_2__ap[11]), .QN(), .SE(dftIn), + .SI(registers_25__ap[11]) + ); + AOI22_X1_LVT i_1_0_909( + .A1(registers_19__ap[11]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[11]), + .ZN(n_1_0_865) + ); + SDFF_X1_LVT \registers_reg[7][11] ( + .CK(n_0_37), .D(registers[11]), .Q(registers_7__ap[11]), .QN(), .SE(dftIn), + .SI(registers_4__ap[11]) + ); + SDFF_X1_LVT \registers_reg[14][11] ( + .CK(n_0_44), .D(registers[11]), .Q(registers_14__ap[11]), .QN(), .SE(dftIn), + .SI(registers_13__ap[11]) + ); + AOI22_X1_LVT i_1_0_908( + .A1(registers_7__ap[11]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[11]), + .ZN(n_1_0_864) + ); + SDFF_X1_LVT \registers_reg[27][11] ( + .CK(n_0_57), .D(registers[11]), .Q(registers_27__ap[11]), .QN(), .SE(dftIn), + .SI(registers_2__ap[11]) + ); + SDFF_X1_LVT \registers_reg[11][11] ( + .CK(n_0_41), .D(registers[11]), .Q(registers_11__ap[11]), .QN(), .SE(dftIn), + .SI(registers_14__ap[11]) + ); + AOI22_X1_LVT i_1_0_907( + .A1(registers_27__ap[11]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[11]), + .ZN(n_1_0_863) + ); + NAND4_X1_LVT i_1_0_906( + .A1(n_1_0_866), .A2(n_1_0_865), .A3(n_1_0_864), .A4(n_1_0_863), .ZN(n_1_0_862) + ); + NOR3_X1_LVT i_1_0_905( + .A1(n_1_0_872), .A2(n_1_0_867), .A3(n_1_0_862), .ZN(n_1_0_861) + ); + NAND4_X1_LVT i_1_0_904( + .A1(n_1_0_879), .A2(n_1_0_878), .A3(n_1_0_877), .A4(n_1_0_861), .ZN(RRs1[11]) + ); + AND2_X1_LVT i_0_0_10( + .A1(n_0_0_16), .A2(WRd[10]), .ZN(registers[10]) + ); + SDFF_X1_LVT \registers_reg[28][10] ( + .CK(n_0_58), .D(registers[10]), .Q(registers_28__ap[10]), .QN(), .SE(dftIn), + .SI(registers_27__ap[11]) + ); + SDFF_X1_LVT \registers_reg[8][10] ( + .CK(n_0_38), .D(registers[10]), .Q(registers_8__ap[10]), .QN(), .SE(dftIn), + .SI(registers_7__ap[11]) + ); + AOI22_X1_LVT i_1_0_902( + .A1(registers_28__ap[10]), .A2(n_1_0_1283), .B1(n_1_0_1282), .B2(registers_8__ap[10]), + .ZN(n_1_0_859) + ); + SDFF_X1_LVT \registers_reg[31][10] ( + .CK(n_0_61), .D(registers[10]), .Q(registers_31__ap[10]), .QN(), .SE(dftIn), + .SI(registers_8__ap[10]) + ); + SDFF_X1_LVT \registers_reg[7][10] ( + .CK(n_0_37), .D(registers[10]), .Q(registers_7__ap[10]), .QN(), .SE(dftIn), + .SI(registers_31__ap[10]) + ); + AOI22_X1_LVT i_1_0_903( + .A1(registers_31__ap[10]), .A2(n_1_0_1266), .B1(n_1_0_1263), .B2(registers_7__ap[10]), + .ZN(n_1_0_860) + ); + SDFF_X1_LVT \registers_reg[24][10] ( + .CK(n_0_54), .D(registers[10]), .Q(registers_24__ap[10]), .QN(), .SE(dftIn), + .SI(registers_28__ap[10]) + ); + SDFF_X1_LVT \registers_reg[20][10] ( + .CK(n_0_50), .D(registers[10]), .Q(registers_20__ap[10]), .QN(), .SE(dftIn), + .SI(registers_19__ap[11]) + ); + AOI22_X1_LVT i_1_0_901( + .A1(registers_24__ap[10]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[10]), + .ZN(n_1_0_858) + ); + SDFF_X1_LVT \registers_reg[4][10] ( + .CK(n_0_34), .D(registers[10]), .Q(registers_4__ap[10]), .QN(), .SE(dftIn), + .SI(registers_7__ap[10]) + ); + SDFF_X1_LVT \registers_reg[23][10] ( + .CK(n_0_53), .D(registers[10]), .Q(registers_23__ap[10]), .QN(), .SE(dftIn), + .SI(registers_20__ap[10]) + ); + AOI22_X1_LVT i_1_0_900( + .A1(registers_4__ap[10]), .A2(n_1_0_1278), .B1(n_1_0_1264), .B2(registers_23__ap[10]), + .ZN(n_1_0_857) + ); + NAND3_X1_LVT i_1_0_899( + .A1(n_1_0_860), .A2(n_1_0_858), .A3(n_1_0_857), .ZN(n_1_0_856) + ); + SDFF_X1_LVT \registers_reg[27][10] ( + .CK(n_0_57), .D(registers[10]), .Q(registers_27__ap[10]), .QN(), .SE(dftIn), + .SI(registers_24__ap[10]) + ); + SDFF_X1_LVT \registers_reg[29][10] ( + .CK(n_0_59), .D(registers[10]), .Q(registers_29__ap[10]), .QN(), .SE(dftIn), + .SI(registers_27__ap[10]) + ); + AOI221_X1_LVT i_1_0_898( + .A(n_1_0_856), .B1(n_1_0_1279), .B2(registers_27__ap[10]), .C1(registers_29__ap[10]), + .C2(n_1_0_1276), .ZN(n_1_0_855) + ); + SDFF_X1_LVT \registers_reg[10][10] ( + .CK(n_0_40), .D(registers[10]), .Q(registers_10__ap[10]), .QN(), .SE(dftIn), + .SI(registers_11__ap[11]) + ); + SDFF_X1_LVT \registers_reg[30][10] ( + .CK(n_0_60), .D(registers[10]), .Q(registers_30__ap[10]), .QN(), .SE(dftIn), + .SI(registers_29__ap[10]) + ); + SDFF_X1_LVT \registers_reg[25][10] ( + .CK(n_0_55), .D(registers[10]), .Q(registers_25__ap[10]), .QN(), .SE(dftIn), + .SI(registers_30__ap[10]) + ); + AOI222_X1_LVT i_1_0_897( + .A1(registers_10__ap[10]), .A2(n_1_0_1287), .B1(n_1_0_1272), .B2(registers_30__ap[10]), + .C1(n_1_0_1269), .C2(registers_25__ap[10]), .ZN(n_1_0_854) + ); + NAND3_X1_LVT i_1_0_896( + .A1(n_1_0_859), .A2(n_1_0_855), .A3(n_1_0_854), .ZN(n_1_0_853) + ); + SDFF_X1_LVT \registers_reg[21][10] ( + .CK(n_0_51), .D(registers[10]), .Q(registers_21__ap[10]), .QN(), .SE(dftIn), + .SI(registers_23__ap[10]) + ); + SDFF_X1_LVT \registers_reg[13][10] ( + .CK(n_0_43), .D(registers[10]), .Q(registers_13__ap[10]), .QN(), .SE(dftIn), + .SI(registers_10__ap[10]) + ); + AOI221_X1_LVT i_1_0_895( + .A(n_1_0_853), .B1(n_1_0_1259), .B2(registers_21__ap[10]), .C1(registers_13__ap[10]), + .C2(n_1_0_1277), .ZN(n_1_0_852) + ); + SDFF_X1_LVT \registers_reg[18][10] ( + .CK(n_0_48), .D(registers[10]), .Q(registers_18__ap[10]), .QN(), .SE(dftIn), + .SI(registers_21__ap[10]) + ); + SDFF_X1_LVT \registers_reg[26][10] ( + .CK(n_0_56), .D(registers[10]), .Q(registers_26__ap[10]), .QN(), .SE(dftIn), + .SI(registers_25__ap[10]) + ); + AOI22_X1_LVT i_1_0_894( + .A1(registers_18__ap[10]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[10]), + .ZN(n_1_0_851) + ); + SDFF_X1_LVT \registers_reg[17][10] ( + .CK(n_0_47), .D(registers[10]), .Q(registers_17__ap[10]), .QN(), .SE(dftIn), + .SI(registers_18__ap[10]) + ); + SDFF_X1_LVT \registers_reg[12][10] ( + .CK(n_0_42), .D(registers[10]), .Q(registers_12__ap[10]), .QN(), .SE(dftIn), + .SI(registers_13__ap[10]) + ); + AOI22_X1_LVT i_1_0_893( + .A1(registers_17__ap[10]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[10]), + .ZN(n_1_0_850) + ); + SDFF_X1_LVT \registers_reg[15][10] ( + .CK(n_0_45), .D(registers[10]), .Q(registers_15__ap[10]), .QN(), .SE(dftIn), + .SI(registers_12__ap[10]) + ); + SDFF_X1_LVT \registers_reg[5][10] ( + .CK(n_0_35), .D(registers[10]), .Q(registers_5__ap[10]), .QN(), .SE(dftIn), + .SI(registers_4__ap[10]) + ); + AOI22_X1_LVT i_1_0_892( + .A1(registers_15__ap[10]), .A2(n_1_0_1286), .B1(n_1_0_1273), .B2(registers_5__ap[10]), + .ZN(n_1_0_849) + ); + NAND3_X1_LVT i_1_0_891( + .A1(n_1_0_851), .A2(n_1_0_850), .A3(n_1_0_849), .ZN(n_1_0_848) + ); + SDFF_X1_LVT \registers_reg[22][10] ( + .CK(n_0_52), .D(registers[10]), .Q(registers_22__ap[10]), .QN(), .SE(dftIn), + .SI(registers_17__ap[10]) + ); + SDFF_X1_LVT \registers_reg[16][10] ( + .CK(n_0_46), .D(registers[10]), .Q(registers_16__ap[10]), .QN(), .SE(dftIn), + .SI(registers_15__ap[10]) + ); + AOI221_X1_LVT i_1_0_890( + .A(n_1_0_848), .B1(n_1_0_1294), .B2(registers_22__ap[10]), .C1(registers_16__ap[10]), + .C2(n_1_0_1267), .ZN(n_1_0_847) + ); + SDFF_X1_LVT \registers_reg[9][10] ( + .CK(n_0_39), .D(registers[10]), .Q(registers_9__ap[10]), .QN(), .SE(dftIn), + .SI(registers_5__ap[10]) + ); + SDFF_X1_LVT \registers_reg[1][10] ( + .CK(n_0_0), .D(registers[10]), .Q(registers_1__ap[10]), .QN(), .SE(dftIn), + .SI(registers_22__ap[10]) + ); + AOI22_X1_LVT i_1_0_889( + .A1(registers_9__ap[10]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[10]), + .ZN(n_1_0_846) + ); + SDFF_X1_LVT \registers_reg[6][10] ( + .CK(n_0_36), .D(registers[10]), .Q(registers_6__ap[10]), .QN(), .SE(dftIn), + .SI(registers_9__ap[10]) + ); + SDFF_X1_LVT \registers_reg[14][10] ( + .CK(n_0_44), .D(registers[10]), .Q(registers_14__ap[10]), .QN(), .SE(dftIn), + .SI(registers_16__ap[10]) + ); + AOI22_X1_LVT i_1_0_888( + .A1(registers_6__ap[10]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[10]), + .ZN(n_1_0_845) + ); + SDFF_X1_LVT \registers_reg[19][10] ( + .CK(n_0_49), .D(registers[10]), .Q(registers_19__ap[10]), .QN(), .SE(dftIn), + .SI(registers_1__ap[10]) + ); + SDFF_X1_LVT \registers_reg[3][10] ( + .CK(n_0_33), .D(registers[10]), .Q(registers_3__ap[10]), .QN(), .SE(dftIn), + .SI(registers_6__ap[10]) + ); + AOI22_X1_LVT i_1_0_887( + .A1(registers_19__ap[10]), .A2(n_1_0_1295), .B1(n_1_0_1257), .B2(registers_3__ap[10]), + .ZN(n_1_0_844) + ); + NAND3_X1_LVT i_1_0_886( + .A1(n_1_0_846), .A2(n_1_0_845), .A3(n_1_0_844), .ZN(n_1_0_843) + ); + SDFF_X1_LVT \registers_reg[11][10] ( + .CK(n_0_41), .D(registers[10]), .Q(registers_11__ap[10]), .QN(), .SE(dftIn), + .SI(registers_14__ap[10]) + ); + SDFF_X1_LVT \registers_reg[2][10] ( + .CK(n_0_32), .D(registers[10]), .Q(registers_2__ap[10]), .QN(), .SE(dftIn), + .SI(registers_26__ap[10]) + ); + AOI221_X1_LVT i_1_0_885( + .A(n_1_0_843), .B1(n_1_0_1270), .B2(registers_11__ap[10]), .C1(registers_2__ap[10]), + .C2(n_1_0_1268), .ZN(n_1_0_842) + ); + NAND3_X1_LVT i_1_0_884( + .A1(n_1_0_852), .A2(n_1_0_847), .A3(n_1_0_842), .ZN(RRs1[10]) + ); + AND2_X1_LVT i_0_0_9( + .A1(n_0_0_16), .A2(WRd[9]), .ZN(registers[9]) + ); + SDFF_X1_LVT \registers_reg[13][9] ( + .CK(n_0_43), .D(registers[9]), .Q(registers_13__ap[9]), .QN(), .SE(dftIn), + .SI(registers_11__ap[10]) + ); + SDFF_X1_LVT \registers_reg[21][9] ( + .CK(n_0_51), .D(registers[9]), .Q(registers_21__ap[9]), .QN(), .SE(dftIn), + .SI(registers_19__ap[10]) + ); + AOI22_X1_LVT i_1_0_880( + .A1(registers_13__ap[9]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[9]), + .ZN(n_1_0_838) + ); + SDFF_X1_LVT \registers_reg[29][9] ( + .CK(n_0_59), .D(registers[9]), .Q(registers_29__ap[9]), .QN(), .SE(dftIn), + .SI(registers_2__ap[10]) + ); + SDFF_X1_LVT \registers_reg[23][9] ( + .CK(n_0_53), .D(registers[9]), .Q(registers_23__ap[9]), .QN(), .SE(dftIn), + .SI(registers_21__ap[9]) + ); + AOI22_X1_LVT i_1_0_883( + .A1(registers_29__ap[9]), .A2(n_1_0_1276), .B1(n_1_0_1264), .B2(registers_23__ap[9]), + .ZN(n_1_0_841) + ); + SDFF_X1_LVT \registers_reg[24][9] ( + .CK(n_0_54), .D(registers[9]), .Q(registers_24__ap[9]), .QN(), .SE(dftIn), + .SI(registers_29__ap[9]) + ); + SDFF_X1_LVT \registers_reg[20][9] ( + .CK(n_0_50), .D(registers[9]), .Q(registers_20__ap[9]), .QN(), .SE(dftIn), + .SI(registers_23__ap[9]) + ); + AOI22_X1_LVT i_1_0_879( + .A1(registers_24__ap[9]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[9]), + .ZN(n_1_0_837) + ); + SDFF_X1_LVT \registers_reg[7][9] ( + .CK(n_0_37), .D(registers[9]), .Q(registers_7__ap[9]), .QN(), .SE(dftIn), + .SI(registers_3__ap[10]) + ); + SDFF_X1_LVT \registers_reg[3][9] ( + .CK(n_0_33), .D(registers[9]), .Q(registers_3__ap[9]), .QN(), .SE(dftIn), + .SI(registers_7__ap[9]) + ); + AOI22_X1_LVT i_1_0_882( + .A1(registers_7__ap[9]), .A2(n_1_0_1263), .B1(n_1_0_1257), .B2(registers_3__ap[9]), + .ZN(n_1_0_840) + ); + INV_X1_LVT i_1_0_881( + .A(n_1_0_840), .ZN(n_1_0_839) + ); + SDFF_X1_LVT \registers_reg[31][9] ( + .CK(n_0_61), .D(registers[9]), .Q(registers_31__ap[9]), .QN(), .SE(dftIn), + .SI(registers_3__ap[9]) + ); + SDFF_X1_LVT \registers_reg[4][9] ( + .CK(n_0_34), .D(registers[9]), .Q(registers_4__ap[9]), .QN(), .SE(dftIn), + .SI(registers_31__ap[9]) + ); + AOI221_X1_LVT i_1_0_878( + .A(n_1_0_839), .B1(n_1_0_1266), .B2(registers_31__ap[9]), .C1(registers_4__ap[9]), + .C2(n_1_0_1278), .ZN(n_1_0_836) + ); + SDFF_X1_LVT \registers_reg[10][9] ( + .CK(n_0_40), .D(registers[9]), .Q(registers_10__ap[9]), .QN(), .SE(dftIn), + .SI(registers_13__ap[9]) + ); + SDFF_X1_LVT \registers_reg[26][9] ( + .CK(n_0_56), .D(registers[9]), .Q(registers_26__ap[9]), .QN(), .SE(dftIn), + .SI(registers_24__ap[9]) + ); + SDFF_X1_LVT \registers_reg[25][9] ( + .CK(n_0_55), .D(registers[9]), .Q(registers_25__ap[9]), .QN(), .SE(dftIn), + .SI(registers_26__ap[9]) + ); + AOI222_X1_LVT i_1_0_877( + .A1(registers_10__ap[9]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[9]), + .C1(registers_25__ap[9]), .C2(n_1_0_1269), .ZN(n_1_0_835) + ); + NAND4_X1_LVT i_1_0_876( + .A1(n_1_0_841), .A2(n_1_0_837), .A3(n_1_0_836), .A4(n_1_0_835), .ZN(n_1_0_834) + ); + SDFF_X1_LVT \registers_reg[8][9] ( + .CK(n_0_38), .D(registers[9]), .Q(registers_8__ap[9]), .QN(), .SE(dftIn), + .SI(registers_4__ap[9]) + ); + SDFF_X1_LVT \registers_reg[28][9] ( + .CK(n_0_58), .D(registers[9]), .Q(registers_28__ap[9]), .QN(), .SE(dftIn), + .SI(registers_25__ap[9]) + ); + AOI221_X1_LVT i_1_0_875( + .A(n_1_0_834), .B1(n_1_0_1282), .B2(registers_8__ap[9]), .C1(registers_28__ap[9]), + .C2(n_1_0_1283), .ZN(n_1_0_833) + ); + SDFF_X1_LVT \registers_reg[18][9] ( + .CK(n_0_48), .D(registers[9]), .Q(registers_18__ap[9]), .QN(), .SE(dftIn), + .SI(registers_20__ap[9]) + ); + SDFF_X1_LVT \registers_reg[30][9] ( + .CK(n_0_60), .D(registers[9]), .Q(registers_30__ap[9]), .QN(), .SE(dftIn), + .SI(registers_28__ap[9]) + ); + AOI22_X1_LVT i_1_0_874( + .A1(registers_18__ap[9]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[9]), + .ZN(n_1_0_832) + ); + SDFF_X1_LVT \registers_reg[17][9] ( + .CK(n_0_47), .D(registers[9]), .Q(registers_17__ap[9]), .QN(), .SE(dftIn), + .SI(registers_18__ap[9]) + ); + SDFF_X1_LVT \registers_reg[12][9] ( + .CK(n_0_42), .D(registers[9]), .Q(registers_12__ap[9]), .QN(), .SE(dftIn), + .SI(registers_10__ap[9]) + ); + AOI22_X1_LVT i_1_0_873( + .A1(registers_17__ap[9]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[9]), + .ZN(n_1_0_831) + ); + SDFF_X1_LVT \registers_reg[15][9] ( + .CK(n_0_45), .D(registers[9]), .Q(registers_15__ap[9]), .QN(), .SE(dftIn), + .SI(registers_12__ap[9]) + ); + SDFF_X1_LVT \registers_reg[5][9] ( + .CK(n_0_35), .D(registers[9]), .Q(registers_5__ap[9]), .QN(), .SE(dftIn), + .SI(registers_8__ap[9]) + ); + AOI22_X1_LVT i_1_0_872( + .A1(registers_15__ap[9]), .A2(n_1_0_1286), .B1(n_1_0_1273), .B2(registers_5__ap[9]), + .ZN(n_1_0_830) + ); + NAND3_X1_LVT i_1_0_871( + .A1(n_1_0_832), .A2(n_1_0_831), .A3(n_1_0_830), .ZN(n_1_0_829) + ); + SDFF_X1_LVT \registers_reg[22][9] ( + .CK(n_0_52), .D(registers[9]), .Q(registers_22__ap[9]), .QN(), .SE(dftIn), + .SI(registers_17__ap[9]) + ); + SDFF_X1_LVT \registers_reg[16][9] ( + .CK(n_0_46), .D(registers[9]), .Q(registers_16__ap[9]), .QN(), .SE(dftIn), + .SI(registers_15__ap[9]) + ); + AOI221_X1_LVT i_1_0_870( + .A(n_1_0_829), .B1(n_1_0_1294), .B2(registers_22__ap[9]), .C1(registers_16__ap[9]), + .C2(n_1_0_1267), .ZN(n_1_0_828) + ); + SDFF_X1_LVT \registers_reg[9][9] ( + .CK(n_0_39), .D(registers[9]), .Q(registers_9__ap[9]), .QN(), .SE(dftIn), + .SI(registers_5__ap[9]) + ); + SDFF_X1_LVT \registers_reg[1][9] ( + .CK(n_0_0), .D(registers[9]), .Q(registers_1__ap[9]), .QN(), .SE(dftIn), + .SI(registers_22__ap[9]) + ); + AOI22_X1_LVT i_1_0_869( + .A1(registers_9__ap[9]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[9]), + .ZN(n_1_0_827) + ); + SDFF_X1_LVT \registers_reg[6][9] ( + .CK(n_0_36), .D(registers[9]), .Q(registers_6__ap[9]), .QN(), .SE(dftIn), + .SI(registers_9__ap[9]) + ); + SDFF_X1_LVT \registers_reg[14][9] ( + .CK(n_0_44), .D(registers[9]), .Q(registers_14__ap[9]), .QN(), .SE(dftIn), + .SI(registers_16__ap[9]) + ); + AOI22_X1_LVT i_1_0_868( + .A1(registers_6__ap[9]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[9]), + .ZN(n_1_0_826) + ); + SDFF_X1_LVT \registers_reg[19][9] ( + .CK(n_0_49), .D(registers[9]), .Q(registers_19__ap[9]), .QN(), .SE(dftIn), + .SI(registers_1__ap[9]) + ); + SDFF_X1_LVT \registers_reg[2][9] ( + .CK(n_0_32), .D(registers[9]), .Q(registers_2__ap[9]), .QN(), .SE(dftIn), + .SI(registers_30__ap[9]) + ); + AOI22_X1_LVT i_1_0_867( + .A1(registers_19__ap[9]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[9]), + .ZN(n_1_0_825) + ); + NAND3_X1_LVT i_1_0_866( + .A1(n_1_0_827), .A2(n_1_0_826), .A3(n_1_0_825), .ZN(n_1_0_824) + ); + SDFF_X1_LVT \registers_reg[11][9] ( + .CK(n_0_41), .D(registers[9]), .Q(registers_11__ap[9]), .QN(), .SE(dftIn), + .SI(registers_14__ap[9]) + ); + SDFF_X1_LVT \registers_reg[27][9] ( + .CK(n_0_57), .D(registers[9]), .Q(registers_27__ap[9]), .QN(), .SE(dftIn), + .SI(registers_2__ap[9]) + ); + AOI221_X1_LVT i_1_0_865( + .A(n_1_0_824), .B1(n_1_0_1270), .B2(registers_11__ap[9]), .C1(registers_27__ap[9]), + .C2(n_1_0_1279), .ZN(n_1_0_823) + ); + NAND4_X1_LVT i_1_0_864( + .A1(n_1_0_838), .A2(n_1_0_833), .A3(n_1_0_828), .A4(n_1_0_823), .ZN(RRs1[9]) + ); + AND2_X1_LVT i_0_0_8( + .A1(n_0_0_16), .A2(WRd[8]), .ZN(registers[8]) + ); + SDFF_X1_LVT \registers_reg[13][8] ( + .CK(n_0_43), .D(registers[8]), .Q(registers_13__ap[8]), .QN(), .SE(dftIn), + .SI(registers_11__ap[9]) + ); + SDFF_X1_LVT \registers_reg[21][8] ( + .CK(n_0_51), .D(registers[8]), .Q(registers_21__ap[8]), .QN(), .SE(dftIn), + .SI(registers_19__ap[9]) + ); + AOI22_X1_LVT i_1_0_860( + .A1(registers_13__ap[8]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[8]), + .ZN(n_1_0_819) + ); + SDFF_X1_LVT \registers_reg[29][8] ( + .CK(n_0_59), .D(registers[8]), .Q(registers_29__ap[8]), .QN(), .SE(dftIn), + .SI(registers_27__ap[9]) + ); + SDFF_X1_LVT \registers_reg[23][8] ( + .CK(n_0_53), .D(registers[8]), .Q(registers_23__ap[8]), .QN(), .SE(dftIn), + .SI(registers_21__ap[8]) + ); + AOI22_X1_LVT i_1_0_863( + .A1(registers_29__ap[8]), .A2(n_1_0_1276), .B1(n_1_0_1264), .B2(registers_23__ap[8]), + .ZN(n_1_0_822) + ); + SDFF_X1_LVT \registers_reg[24][8] ( + .CK(n_0_54), .D(registers[8]), .Q(registers_24__ap[8]), .QN(), .SE(dftIn), + .SI(registers_29__ap[8]) + ); + SDFF_X1_LVT \registers_reg[20][8] ( + .CK(n_0_50), .D(registers[8]), .Q(registers_20__ap[8]), .QN(), .SE(dftIn), + .SI(registers_23__ap[8]) + ); + AOI22_X1_LVT i_1_0_859( + .A1(registers_24__ap[8]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[8]), + .ZN(n_1_0_818) + ); + SDFF_X1_LVT \registers_reg[7][8] ( + .CK(n_0_37), .D(registers[8]), .Q(registers_7__ap[8]), .QN(), .SE(dftIn), + .SI(registers_6__ap[9]) + ); + SDFF_X1_LVT \registers_reg[3][8] ( + .CK(n_0_33), .D(registers[8]), .Q(registers_3__ap[8]), .QN(), .SE(dftIn), + .SI(registers_7__ap[8]) + ); + AOI22_X1_LVT i_1_0_862( + .A1(registers_7__ap[8]), .A2(n_1_0_1263), .B1(n_1_0_1257), .B2(registers_3__ap[8]), + .ZN(n_1_0_821) + ); + INV_X1_LVT i_1_0_861( + .A(n_1_0_821), .ZN(n_1_0_820) + ); + SDFF_X1_LVT \registers_reg[31][8] ( + .CK(n_0_61), .D(registers[8]), .Q(registers_31__ap[8]), .QN(), .SE(dftIn), + .SI(registers_3__ap[8]) + ); + SDFF_X1_LVT \registers_reg[4][8] ( + .CK(n_0_34), .D(registers[8]), .Q(registers_4__ap[8]), .QN(), .SE(dftIn), + .SI(registers_31__ap[8]) + ); + AOI221_X1_LVT i_1_0_858( + .A(n_1_0_820), .B1(n_1_0_1266), .B2(registers_31__ap[8]), .C1(registers_4__ap[8]), + .C2(n_1_0_1278), .ZN(n_1_0_817) + ); + SDFF_X1_LVT \registers_reg[10][8] ( + .CK(n_0_40), .D(registers[8]), .Q(registers_10__ap[8]), .QN(), .SE(dftIn), + .SI(registers_13__ap[8]) + ); + SDFF_X1_LVT \registers_reg[26][8] ( + .CK(n_0_56), .D(registers[8]), .Q(registers_26__ap[8]), .QN(), .SE(dftIn), + .SI(registers_24__ap[8]) + ); + SDFF_X1_LVT \registers_reg[25][8] ( + .CK(n_0_55), .D(registers[8]), .Q(registers_25__ap[8]), .QN(), .SE(dftIn), + .SI(registers_26__ap[8]) + ); + AOI222_X1_LVT i_1_0_857( + .A1(registers_10__ap[8]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[8]), + .C1(registers_25__ap[8]), .C2(n_1_0_1269), .ZN(n_1_0_816) + ); + NAND4_X1_LVT i_1_0_856( + .A1(n_1_0_822), .A2(n_1_0_818), .A3(n_1_0_817), .A4(n_1_0_816), .ZN(n_1_0_815) + ); + SDFF_X1_LVT \registers_reg[8][8] ( + .CK(n_0_38), .D(registers[8]), .Q(registers_8__ap[8]), .QN(), .SE(dftIn), + .SI(registers_4__ap[8]) + ); + SDFF_X1_LVT \registers_reg[28][8] ( + .CK(n_0_58), .D(registers[8]), .Q(registers_28__ap[8]), .QN(), .SE(dftIn), + .SI(registers_25__ap[8]) + ); + AOI221_X1_LVT i_1_0_855( + .A(n_1_0_815), .B1(n_1_0_1282), .B2(registers_8__ap[8]), .C1(registers_28__ap[8]), + .C2(n_1_0_1283), .ZN(n_1_0_814) + ); + SDFF_X1_LVT \registers_reg[18][8] ( + .CK(n_0_48), .D(registers[8]), .Q(registers_18__ap[8]), .QN(), .SE(dftIn), + .SI(registers_20__ap[8]) + ); + SDFF_X1_LVT \registers_reg[30][8] ( + .CK(n_0_60), .D(registers[8]), .Q(registers_30__ap[8]), .QN(), .SE(dftIn), + .SI(registers_28__ap[8]) + ); + AOI22_X1_LVT i_1_0_854( + .A1(registers_18__ap[8]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[8]), + .ZN(n_1_0_813) + ); + SDFF_X1_LVT \registers_reg[17][8] ( + .CK(n_0_47), .D(registers[8]), .Q(registers_17__ap[8]), .QN(), .SE(dftIn), + .SI(registers_18__ap[8]) + ); + SDFF_X1_LVT \registers_reg[12][8] ( + .CK(n_0_42), .D(registers[8]), .Q(registers_12__ap[8]), .QN(), .SE(dftIn), + .SI(registers_10__ap[8]) + ); + AOI22_X1_LVT i_1_0_853( + .A1(registers_17__ap[8]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[8]), + .ZN(n_1_0_812) + ); + SDFF_X1_LVT \registers_reg[15][8] ( + .CK(n_0_45), .D(registers[8]), .Q(registers_15__ap[8]), .QN(), .SE(dftIn), + .SI(registers_12__ap[8]) + ); + SDFF_X1_LVT \registers_reg[5][8] ( + .CK(n_0_35), .D(registers[8]), .Q(registers_5__ap[8]), .QN(), .SE(dftIn), + .SI(registers_8__ap[8]) + ); + AOI22_X1_LVT i_1_0_852( + .A1(registers_15__ap[8]), .A2(n_1_0_1286), .B1(n_1_0_1273), .B2(registers_5__ap[8]), + .ZN(n_1_0_811) + ); + NAND3_X1_LVT i_1_0_851( + .A1(n_1_0_813), .A2(n_1_0_812), .A3(n_1_0_811), .ZN(n_1_0_810) + ); + SDFF_X1_LVT \registers_reg[22][8] ( + .CK(n_0_52), .D(registers[8]), .Q(registers_22__ap[8]), .QN(), .SE(dftIn), + .SI(registers_17__ap[8]) + ); + SDFF_X1_LVT \registers_reg[16][8] ( + .CK(n_0_46), .D(registers[8]), .Q(registers_16__ap[8]), .QN(), .SE(dftIn), + .SI(registers_15__ap[8]) + ); + AOI221_X1_LVT i_1_0_850( + .A(n_1_0_810), .B1(n_1_0_1294), .B2(registers_22__ap[8]), .C1(registers_16__ap[8]), + .C2(n_1_0_1267), .ZN(n_1_0_809) + ); + SDFF_X1_LVT \registers_reg[9][8] ( + .CK(n_0_39), .D(registers[8]), .Q(registers_9__ap[8]), .QN(), .SE(dftIn), + .SI(registers_5__ap[8]) + ); + SDFF_X1_LVT \registers_reg[1][8] ( + .CK(n_0_0), .D(registers[8]), .Q(registers_1__ap[8]), .QN(), .SE(dftIn), + .SI(registers_22__ap[8]) + ); + AOI22_X1_LVT i_1_0_849( + .A1(registers_9__ap[8]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[8]), + .ZN(n_1_0_808) + ); + SDFF_X1_LVT \registers_reg[6][8] ( + .CK(n_0_36), .D(registers[8]), .Q(registers_6__ap[8]), .QN(), .SE(dftIn), + .SI(registers_9__ap[8]) + ); + SDFF_X1_LVT \registers_reg[14][8] ( + .CK(n_0_44), .D(registers[8]), .Q(registers_14__ap[8]), .QN(), .SE(dftIn), + .SI(registers_16__ap[8]) + ); + AOI22_X1_LVT i_1_0_848( + .A1(registers_6__ap[8]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[8]), + .ZN(n_1_0_807) + ); + SDFF_X1_LVT \registers_reg[19][8] ( + .CK(n_0_49), .D(registers[8]), .Q(registers_19__ap[8]), .QN(), .SE(dftIn), + .SI(registers_1__ap[8]) + ); + SDFF_X1_LVT \registers_reg[2][8] ( + .CK(n_0_32), .D(registers[8]), .Q(registers_2__ap[8]), .QN(), .SE(dftIn), + .SI(registers_30__ap[8]) + ); + AOI22_X1_LVT i_1_0_847( + .A1(registers_19__ap[8]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[8]), + .ZN(n_1_0_806) + ); + NAND3_X1_LVT i_1_0_846( + .A1(n_1_0_808), .A2(n_1_0_807), .A3(n_1_0_806), .ZN(n_1_0_805) + ); + SDFF_X1_LVT \registers_reg[11][8] ( + .CK(n_0_41), .D(registers[8]), .Q(registers_11__ap[8]), .QN(), .SE(dftIn), + .SI(registers_14__ap[8]) + ); + SDFF_X1_LVT \registers_reg[27][8] ( + .CK(n_0_57), .D(registers[8]), .Q(registers_27__ap[8]), .QN(), .SE(dftIn), + .SI(registers_2__ap[8]) + ); + AOI221_X1_LVT i_1_0_845( + .A(n_1_0_805), .B1(n_1_0_1270), .B2(registers_11__ap[8]), .C1(registers_27__ap[8]), + .C2(n_1_0_1279), .ZN(n_1_0_804) + ); + NAND4_X1_LVT i_1_0_844( + .A1(n_1_0_819), .A2(n_1_0_814), .A3(n_1_0_809), .A4(n_1_0_804), .ZN(RRs1[8]) + ); + AND2_X1_LVT i_0_0_7( + .A1(n_0_0_16), .A2(WRd[7]), .ZN(registers[7]) + ); + SDFF_X1_LVT \registers_reg[13][7] ( + .CK(n_0_43), .D(registers[7]), .Q(registers_13__ap[7]), .QN(), .SE(dftIn), + .SI(registers_11__ap[8]) + ); + SDFF_X1_LVT \registers_reg[21][7] ( + .CK(n_0_51), .D(registers[7]), .Q(registers_21__ap[7]), .QN(), .SE(dftIn), + .SI(registers_19__ap[8]) + ); + AOI22_X1_LVT i_1_0_843( + .A1(registers_13__ap[7]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[7]), + .ZN(n_1_0_803) + ); + SDFF_X1_LVT \registers_reg[18][7] ( + .CK(n_0_48), .D(registers[7]), .Q(registers_18__ap[7]), .QN(), .SE(dftIn), + .SI(registers_21__ap[7]) + ); + SDFF_X1_LVT \registers_reg[10][7] ( + .CK(n_0_40), .D(registers[7]), .Q(registers_10__ap[7]), .QN(), .SE(dftIn), + .SI(registers_13__ap[7]) + ); + SDFF_X1_LVT \registers_reg[25][7] ( + .CK(n_0_55), .D(registers[7]), .Q(registers_25__ap[7]), .QN(), .SE(dftIn), + .SI(registers_27__ap[8]) + ); + AOI222_X1_LVT i_1_0_842( + .A1(registers_18__ap[7]), .A2(n_1_0_1297), .B1(n_1_0_1287), .B2(registers_10__ap[7]), + .C1(registers_25__ap[7]), .C2(n_1_0_1269), .ZN(n_1_0_802) + ); + SDFF_X1_LVT \registers_reg[28][7] ( + .CK(n_0_58), .D(registers[7]), .Q(registers_28__ap[7]), .QN(), .SE(dftIn), + .SI(registers_25__ap[7]) + ); + SDFF_X1_LVT \registers_reg[8][7] ( + .CK(n_0_38), .D(registers[7]), .Q(registers_8__ap[7]), .QN(), .SE(dftIn), + .SI(registers_6__ap[8]) + ); + AOI22_X1_LVT i_1_0_841( + .A1(registers_28__ap[7]), .A2(n_1_0_1283), .B1(n_1_0_1282), .B2(registers_8__ap[7]), + .ZN(n_1_0_801) + ); + SDFF_X1_LVT \registers_reg[24][7] ( + .CK(n_0_54), .D(registers[7]), .Q(registers_24__ap[7]), .QN(), .SE(dftIn), + .SI(registers_28__ap[7]) + ); + SDFF_X1_LVT \registers_reg[20][7] ( + .CK(n_0_50), .D(registers[7]), .Q(registers_20__ap[7]), .QN(), .SE(dftIn), + .SI(registers_18__ap[7]) + ); + AOI22_X1_LVT i_1_0_840( + .A1(registers_24__ap[7]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[7]), + .ZN(n_1_0_800) + ); + SDFF_X1_LVT \registers_reg[31][7] ( + .CK(n_0_61), .D(registers[7]), .Q(registers_31__ap[7]), .QN(), .SE(dftIn), + .SI(registers_8__ap[7]) + ); + SDFF_X1_LVT \registers_reg[7][7] ( + .CK(n_0_37), .D(registers[7]), .Q(registers_7__ap[7]), .QN(), .SE(dftIn), + .SI(registers_31__ap[7]) + ); + AOI22_X1_LVT i_1_0_839( + .A1(registers_31__ap[7]), .A2(n_1_0_1266), .B1(n_1_0_1263), .B2(registers_7__ap[7]), + .ZN(n_1_0_799) + ); + SDFF_X1_LVT \registers_reg[17][7] ( + .CK(n_0_47), .D(registers[7]), .Q(registers_17__ap[7]), .QN(), .SE(dftIn), + .SI(registers_20__ap[7]) + ); + SDFF_X1_LVT \registers_reg[11][7] ( + .CK(n_0_41), .D(registers[7]), .Q(registers_11__ap[7]), .QN(), .SE(dftIn), + .SI(registers_10__ap[7]) + ); + AOI22_X1_LVT i_1_0_838( + .A1(registers_17__ap[7]), .A2(n_1_0_1271), .B1(n_1_0_1270), .B2(registers_11__ap[7]), + .ZN(n_1_0_798) + ); + SDFF_X1_LVT \registers_reg[27][7] ( + .CK(n_0_57), .D(registers[7]), .Q(registers_27__ap[7]), .QN(), .SE(dftIn), + .SI(registers_24__ap[7]) + ); + SDFF_X1_LVT \registers_reg[29][7] ( + .CK(n_0_59), .D(registers[7]), .Q(registers_29__ap[7]), .QN(), .SE(dftIn), + .SI(registers_27__ap[7]) + ); + AOI22_X1_LVT i_1_0_837( + .A1(registers_27__ap[7]), .A2(n_1_0_1279), .B1(n_1_0_1276), .B2(registers_29__ap[7]), + .ZN(n_1_0_797) + ); + NAND4_X1_LVT i_1_0_836( + .A1(n_1_0_800), .A2(n_1_0_799), .A3(n_1_0_798), .A4(n_1_0_797), .ZN(n_1_0_796) + ); + SDFF_X1_LVT \registers_reg[26][7] ( + .CK(n_0_56), .D(registers[7]), .Q(registers_26__ap[7]), .QN(), .SE(dftIn), + .SI(registers_29__ap[7]) + ); + SDFF_X1_LVT \registers_reg[30][7] ( + .CK(n_0_60), .D(registers[7]), .Q(registers_30__ap[7]), .QN(), .SE(dftIn), + .SI(registers_26__ap[7]) + ); + AOI22_X1_LVT i_1_0_835( + .A1(registers_26__ap[7]), .A2(n_1_0_1285), .B1(n_1_0_1272), .B2(registers_30__ap[7]), + .ZN(n_1_0_795) + ); + SDFF_X1_LVT \registers_reg[4][7] ( + .CK(n_0_34), .D(registers[7]), .Q(registers_4__ap[7]), .QN(), .SE(dftIn), + .SI(registers_7__ap[7]) + ); + SDFF_X1_LVT \registers_reg[12][7] ( + .CK(n_0_42), .D(registers[7]), .Q(registers_12__ap[7]), .QN(), .SE(dftIn), + .SI(registers_11__ap[7]) + ); + AOI22_X1_LVT i_1_0_834( + .A1(registers_4__ap[7]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[7]), + .ZN(n_1_0_794) + ); + SDFF_X1_LVT \registers_reg[15][7] ( + .CK(n_0_45), .D(registers[7]), .Q(registers_15__ap[7]), .QN(), .SE(dftIn), + .SI(registers_12__ap[7]) + ); + SDFF_X1_LVT \registers_reg[16][7] ( + .CK(n_0_46), .D(registers[7]), .Q(registers_16__ap[7]), .QN(), .SE(dftIn), + .SI(registers_15__ap[7]) + ); + AOI22_X1_LVT i_1_0_833( + .A1(registers_15__ap[7]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[7]), + .ZN(n_1_0_793) + ); + SDFF_X1_LVT \registers_reg[22][7] ( + .CK(n_0_52), .D(registers[7]), .Q(registers_22__ap[7]), .QN(), .SE(dftIn), + .SI(registers_17__ap[7]) + ); + SDFF_X1_LVT \registers_reg[5][7] ( + .CK(n_0_35), .D(registers[7]), .Q(registers_5__ap[7]), .QN(), .SE(dftIn), + .SI(registers_4__ap[7]) + ); + AOI22_X1_LVT i_1_0_832( + .A1(registers_22__ap[7]), .A2(n_1_0_1294), .B1(n_1_0_1273), .B2(registers_5__ap[7]), + .ZN(n_1_0_792) + ); + NAND4_X1_LVT i_1_0_831( + .A1(n_1_0_795), .A2(n_1_0_794), .A3(n_1_0_793), .A4(n_1_0_792), .ZN(n_1_0_791) + ); + SDFF_X1_LVT \registers_reg[19][7] ( + .CK(n_0_49), .D(registers[7]), .Q(registers_19__ap[7]), .QN(), .SE(dftIn), + .SI(registers_22__ap[7]) + ); + SDFF_X1_LVT \registers_reg[3][7] ( + .CK(n_0_33), .D(registers[7]), .Q(registers_3__ap[7]), .QN(), .SE(dftIn), + .SI(registers_5__ap[7]) + ); + AOI22_X1_LVT i_1_0_830( + .A1(registers_19__ap[7]), .A2(n_1_0_1295), .B1(n_1_0_1257), .B2(registers_3__ap[7]), + .ZN(n_1_0_790) + ); + SDFF_X1_LVT \registers_reg[9][7] ( + .CK(n_0_39), .D(registers[7]), .Q(registers_9__ap[7]), .QN(), .SE(dftIn), + .SI(registers_3__ap[7]) + ); + SDFF_X1_LVT \registers_reg[1][7] ( + .CK(n_0_0), .D(registers[7]), .Q(registers_1__ap[7]), .QN(), .SE(dftIn), + .SI(registers_19__ap[7]) + ); + AOI22_X1_LVT i_1_0_829( + .A1(registers_9__ap[7]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[7]), + .ZN(n_1_0_789) + ); + SDFF_X1_LVT \registers_reg[6][7] ( + .CK(n_0_36), .D(registers[7]), .Q(registers_6__ap[7]), .QN(), .SE(dftIn), + .SI(registers_9__ap[7]) + ); + SDFF_X1_LVT \registers_reg[14][7] ( + .CK(n_0_44), .D(registers[7]), .Q(registers_14__ap[7]), .QN(), .SE(dftIn), + .SI(registers_16__ap[7]) + ); + AOI22_X1_LVT i_1_0_828( + .A1(registers_6__ap[7]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[7]), + .ZN(n_1_0_788) + ); + SDFF_X1_LVT \registers_reg[2][7] ( + .CK(n_0_32), .D(registers[7]), .Q(registers_2__ap[7]), .QN(), .SE(dftIn), + .SI(registers_30__ap[7]) + ); + SDFF_X1_LVT \registers_reg[23][7] ( + .CK(n_0_53), .D(registers[7]), .Q(registers_23__ap[7]), .QN(), .SE(dftIn), + .SI(registers_1__ap[7]) + ); + AOI22_X1_LVT i_1_0_827( + .A1(registers_2__ap[7]), .A2(n_1_0_1268), .B1(n_1_0_1264), .B2(registers_23__ap[7]), + .ZN(n_1_0_787) + ); + NAND4_X1_LVT i_1_0_826( + .A1(n_1_0_790), .A2(n_1_0_789), .A3(n_1_0_788), .A4(n_1_0_787), .ZN(n_1_0_786) + ); + NOR3_X1_LVT i_1_0_825( + .A1(n_1_0_796), .A2(n_1_0_791), .A3(n_1_0_786), .ZN(n_1_0_785) + ); + NAND4_X1_LVT i_1_0_824( + .A1(n_1_0_803), .A2(n_1_0_802), .A3(n_1_0_801), .A4(n_1_0_785), .ZN(RRs1[7]) + ); + AND2_X1_LVT i_0_0_6( + .A1(n_0_0_16), .A2(WRd[6]), .ZN(registers[6]) + ); + SDFF_X1_LVT \registers_reg[28][6] ( + .CK(n_0_58), .D(registers[6]), .Q(registers_28__ap[6]), .QN(), .SE(dftIn), + .SI(registers_2__ap[7]) + ); + SDFF_X1_LVT \registers_reg[17][6] ( + .CK(n_0_47), .D(registers[6]), .Q(registers_17__ap[6]), .QN(), .SE(dftIn), + .SI(registers_23__ap[7]) + ); + AOI22_X1_LVT i_1_0_823( + .A1(registers_28__ap[6]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[6]), + .ZN(n_1_0_784) + ); + SDFF_X1_LVT \registers_reg[18][6] ( + .CK(n_0_48), .D(registers[6]), .Q(registers_18__ap[6]), .QN(), .SE(dftIn), + .SI(registers_17__ap[6]) + ); + SDFF_X1_LVT \registers_reg[10][6] ( + .CK(n_0_40), .D(registers[6]), .Q(registers_10__ap[6]), .QN(), .SE(dftIn), + .SI(registers_14__ap[7]) + ); + SDFF_X1_LVT \registers_reg[8][6] ( + .CK(n_0_38), .D(registers[6]), .Q(registers_8__ap[6]), .QN(), .SE(dftIn), + .SI(registers_6__ap[7]) + ); + AOI222_X1_LVT i_1_0_822( + .A1(registers_18__ap[6]), .A2(n_1_0_1297), .B1(n_1_0_1287), .B2(registers_10__ap[6]), + .C1(registers_8__ap[6]), .C2(n_1_0_1282), .ZN(n_1_0_783) + ); + SDFF_X1_LVT \registers_reg[9][6] ( + .CK(n_0_39), .D(registers[6]), .Q(registers_9__ap[6]), .QN(), .SE(dftIn), + .SI(registers_8__ap[6]) + ); + SDFF_X1_LVT \registers_reg[29][6] ( + .CK(n_0_59), .D(registers[6]), .Q(registers_29__ap[6]), .QN(), .SE(dftIn), + .SI(registers_28__ap[6]) + ); + AOI22_X1_LVT i_1_0_821( + .A1(registers_9__ap[6]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[6]), + .ZN(n_1_0_782) + ); + SDFF_X1_LVT \registers_reg[6][6] ( + .CK(n_0_36), .D(registers[6]), .Q(registers_6__ap[6]), .QN(), .SE(dftIn), + .SI(registers_9__ap[6]) + ); + SDFF_X1_LVT \registers_reg[1][6] ( + .CK(n_0_0), .D(registers[6]), .Q(registers_1__ap[6]), .QN(), .SE(dftIn), + .SI(registers_18__ap[6]) + ); + AOI22_X1_LVT i_1_0_820( + .A1(registers_6__ap[6]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[6]), + .ZN(n_1_0_781) + ); + SDFF_X1_LVT \registers_reg[15][6] ( + .CK(n_0_45), .D(registers[6]), .Q(registers_15__ap[6]), .QN(), .SE(dftIn), + .SI(registers_10__ap[6]) + ); + SDFF_X1_LVT \registers_reg[27][6] ( + .CK(n_0_57), .D(registers[6]), .Q(registers_27__ap[6]), .QN(), .SE(dftIn), + .SI(registers_29__ap[6]) + ); + AOI22_X1_LVT i_1_0_819( + .A1(registers_15__ap[6]), .A2(n_1_0_1286), .B1(n_1_0_1279), .B2(registers_27__ap[6]), + .ZN(n_1_0_780) + ); + SDFF_X1_LVT \registers_reg[11][6] ( + .CK(n_0_41), .D(registers[6]), .Q(registers_11__ap[6]), .QN(), .SE(dftIn), + .SI(registers_15__ap[6]) + ); + SDFF_X1_LVT \registers_reg[16][6] ( + .CK(n_0_46), .D(registers[6]), .Q(registers_16__ap[6]), .QN(), .SE(dftIn), + .SI(registers_11__ap[6]) + ); + AOI22_X1_LVT i_1_0_818( + .A1(registers_11__ap[6]), .A2(n_1_0_1270), .B1(n_1_0_1267), .B2(registers_16__ap[6]), + .ZN(n_1_0_779) + ); + SDFF_X1_LVT \registers_reg[5][6] ( + .CK(n_0_35), .D(registers[6]), .Q(registers_5__ap[6]), .QN(), .SE(dftIn), + .SI(registers_6__ap[6]) + ); + SDFF_X1_LVT \registers_reg[31][6] ( + .CK(n_0_61), .D(registers[6]), .Q(registers_31__ap[6]), .QN(), .SE(dftIn), + .SI(registers_5__ap[6]) + ); + AOI22_X1_LVT i_1_0_817( + .A1(registers_5__ap[6]), .A2(n_1_0_1273), .B1(n_1_0_1266), .B2(registers_31__ap[6]), + .ZN(n_1_0_778) + ); + NAND4_X1_LVT i_1_0_816( + .A1(n_1_0_781), .A2(n_1_0_780), .A3(n_1_0_779), .A4(n_1_0_778), .ZN(n_1_0_777) + ); + SDFF_X1_LVT \registers_reg[26][6] ( + .CK(n_0_56), .D(registers[6]), .Q(registers_26__ap[6]), .QN(), .SE(dftIn), + .SI(registers_27__ap[6]) + ); + SDFF_X1_LVT \registers_reg[30][6] ( + .CK(n_0_60), .D(registers[6]), .Q(registers_30__ap[6]), .QN(), .SE(dftIn), + .SI(registers_26__ap[6]) + ); + AOI22_X1_LVT i_1_0_815( + .A1(registers_26__ap[6]), .A2(n_1_0_1285), .B1(n_1_0_1272), .B2(registers_30__ap[6]), + .ZN(n_1_0_776) + ); + SDFF_X1_LVT \registers_reg[20][6] ( + .CK(n_0_50), .D(registers[6]), .Q(registers_20__ap[6]), .QN(), .SE(dftIn), + .SI(registers_1__ap[6]) + ); + SDFF_X1_LVT \registers_reg[4][6] ( + .CK(n_0_34), .D(registers[6]), .Q(registers_4__ap[6]), .QN(), .SE(dftIn), + .SI(registers_31__ap[6]) + ); + AOI22_X1_LVT i_1_0_814( + .A1(registers_20__ap[6]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[6]), + .ZN(n_1_0_775) + ); + SDFF_X1_LVT \registers_reg[22][6] ( + .CK(n_0_52), .D(registers[6]), .Q(registers_22__ap[6]), .QN(), .SE(dftIn), + .SI(registers_20__ap[6]) + ); + SDFF_X1_LVT \registers_reg[21][6] ( + .CK(n_0_51), .D(registers[6]), .Q(registers_21__ap[6]), .QN(), .SE(dftIn), + .SI(registers_22__ap[6]) + ); + AOI22_X1_LVT i_1_0_813( + .A1(registers_22__ap[6]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[6]), + .ZN(n_1_0_774) + ); + SDFF_X1_LVT \registers_reg[24][6] ( + .CK(n_0_54), .D(registers[6]), .Q(registers_24__ap[6]), .QN(), .SE(dftIn), + .SI(registers_30__ap[6]) + ); + SDFF_X1_LVT \registers_reg[12][6] ( + .CK(n_0_42), .D(registers[6]), .Q(registers_12__ap[6]), .QN(), .SE(dftIn), + .SI(registers_16__ap[6]) + ); + AOI22_X1_LVT i_1_0_812( + .A1(registers_24__ap[6]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[6]), + .ZN(n_1_0_773) + ); + NAND4_X1_LVT i_1_0_811( + .A1(n_1_0_776), .A2(n_1_0_775), .A3(n_1_0_774), .A4(n_1_0_773), .ZN(n_1_0_772) + ); + SDFF_X1_LVT \registers_reg[13][6] ( + .CK(n_0_43), .D(registers[6]), .Q(registers_13__ap[6]), .QN(), .SE(dftIn), + .SI(registers_12__ap[6]) + ); + SDFF_X1_LVT \registers_reg[25][6] ( + .CK(n_0_55), .D(registers[6]), .Q(registers_25__ap[6]), .QN(), .SE(dftIn), + .SI(registers_24__ap[6]) + ); + AOI22_X1_LVT i_1_0_810( + .A1(registers_13__ap[6]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[6]), + .ZN(n_1_0_771) + ); + SDFF_X1_LVT \registers_reg[7][6] ( + .CK(n_0_37), .D(registers[6]), .Q(registers_7__ap[6]), .QN(), .SE(dftIn), + .SI(registers_4__ap[6]) + ); + SDFF_X1_LVT \registers_reg[14][6] ( + .CK(n_0_44), .D(registers[6]), .Q(registers_14__ap[6]), .QN(), .SE(dftIn), + .SI(registers_13__ap[6]) + ); + AOI22_X1_LVT i_1_0_809( + .A1(registers_7__ap[6]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[6]), + .ZN(n_1_0_770) + ); + SDFF_X1_LVT \registers_reg[19][6] ( + .CK(n_0_49), .D(registers[6]), .Q(registers_19__ap[6]), .QN(), .SE(dftIn), + .SI(registers_21__ap[6]) + ); + SDFF_X1_LVT \registers_reg[3][6] ( + .CK(n_0_33), .D(registers[6]), .Q(registers_3__ap[6]), .QN(), .SE(dftIn), + .SI(registers_7__ap[6]) + ); + AOI22_X1_LVT i_1_0_808( + .A1(registers_19__ap[6]), .A2(n_1_0_1295), .B1(n_1_0_1257), .B2(registers_3__ap[6]), + .ZN(n_1_0_769) + ); + SDFF_X1_LVT \registers_reg[2][6] ( + .CK(n_0_32), .D(registers[6]), .Q(registers_2__ap[6]), .QN(), .SE(dftIn), + .SI(registers_25__ap[6]) + ); + SDFF_X1_LVT \registers_reg[23][6] ( + .CK(n_0_53), .D(registers[6]), .Q(registers_23__ap[6]), .QN(), .SE(dftIn), + .SI(registers_19__ap[6]) + ); + AOI22_X1_LVT i_1_0_807( + .A1(registers_2__ap[6]), .A2(n_1_0_1268), .B1(n_1_0_1264), .B2(registers_23__ap[6]), + .ZN(n_1_0_768) + ); + NAND4_X1_LVT i_1_0_806( + .A1(n_1_0_771), .A2(n_1_0_770), .A3(n_1_0_769), .A4(n_1_0_768), .ZN(n_1_0_767) + ); + NOR3_X1_LVT i_1_0_805( + .A1(n_1_0_777), .A2(n_1_0_772), .A3(n_1_0_767), .ZN(n_1_0_766) + ); + NAND4_X1_LVT i_1_0_804( + .A1(n_1_0_784), .A2(n_1_0_783), .A3(n_1_0_782), .A4(n_1_0_766), .ZN(RRs1[6]) + ); + AND2_X1_LVT i_0_0_5( + .A1(n_0_0_16), .A2(WRd[5]), .ZN(registers[5]) + ); + SDFF_X1_LVT \registers_reg[28][5] ( + .CK(n_0_58), .D(registers[5]), .Q(registers_28__ap[5]), .QN(), .SE(dftIn), + .SI(registers_2__ap[6]) + ); + SDFF_X1_LVT \registers_reg[4][5] ( + .CK(n_0_34), .D(registers[5]), .Q(registers_4__ap[5]), .QN(), .SE(dftIn), + .SI(registers_3__ap[6]) + ); + AOI22_X1_LVT i_1_0_803( + .A1(registers_28__ap[5]), .A2(n_1_0_1283), .B1(n_1_0_1278), .B2(registers_4__ap[5]), + .ZN(n_1_0_765) + ); + SDFF_X1_LVT \registers_reg[10][5] ( + .CK(n_0_40), .D(registers[5]), .Q(registers_10__ap[5]), .QN(), .SE(dftIn), + .SI(registers_14__ap[6]) + ); + SDFF_X1_LVT \registers_reg[26][5] ( + .CK(n_0_56), .D(registers[5]), .Q(registers_26__ap[5]), .QN(), .SE(dftIn), + .SI(registers_28__ap[5]) + ); + SDFF_X1_LVT \registers_reg[8][5] ( + .CK(n_0_38), .D(registers[5]), .Q(registers_8__ap[5]), .QN(), .SE(dftIn), + .SI(registers_4__ap[5]) + ); + AOI222_X1_LVT i_1_0_802( + .A1(registers_10__ap[5]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[5]), + .C1(registers_8__ap[5]), .C2(n_1_0_1282), .ZN(n_1_0_764) + ); + SDFF_X1_LVT \registers_reg[9][5] ( + .CK(n_0_39), .D(registers[5]), .Q(registers_9__ap[5]), .QN(), .SE(dftIn), + .SI(registers_8__ap[5]) + ); + SDFF_X1_LVT \registers_reg[29][5] ( + .CK(n_0_59), .D(registers[5]), .Q(registers_29__ap[5]), .QN(), .SE(dftIn), + .SI(registers_26__ap[5]) + ); + AOI22_X1_LVT i_1_0_801( + .A1(registers_9__ap[5]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[5]), + .ZN(n_1_0_763) + ); + SDFF_X1_LVT \registers_reg[6][5] ( + .CK(n_0_36), .D(registers[5]), .Q(registers_6__ap[5]), .QN(), .SE(dftIn), + .SI(registers_9__ap[5]) + ); + SDFF_X1_LVT \registers_reg[1][5] ( + .CK(n_0_0), .D(registers[5]), .Q(registers_1__ap[5]), .QN(), .SE(dftIn), + .SI(registers_23__ap[6]) + ); + AOI22_X1_LVT i_1_0_800( + .A1(registers_6__ap[5]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[5]), + .ZN(n_1_0_762) + ); + SDFF_X1_LVT \registers_reg[16][5] ( + .CK(n_0_46), .D(registers[5]), .Q(registers_16__ap[5]), .QN(), .SE(dftIn), + .SI(registers_10__ap[5]) + ); + SDFF_X1_LVT \registers_reg[3][5] ( + .CK(n_0_33), .D(registers[5]), .Q(registers_3__ap[5]), .QN(), .SE(dftIn), + .SI(registers_6__ap[5]) + ); + AOI22_X1_LVT i_1_0_799( + .A1(registers_16__ap[5]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[5]), + .ZN(n_1_0_761) + ); + SDFF_X1_LVT \registers_reg[5][5] ( + .CK(n_0_35), .D(registers[5]), .Q(registers_5__ap[5]), .QN(), .SE(dftIn), + .SI(registers_3__ap[5]) + ); + SDFF_X1_LVT \registers_reg[31][5] ( + .CK(n_0_61), .D(registers[5]), .Q(registers_31__ap[5]), .QN(), .SE(dftIn), + .SI(registers_5__ap[5]) + ); + AOI22_X1_LVT i_1_0_798( + .A1(registers_5__ap[5]), .A2(n_1_0_1273), .B1(n_1_0_1266), .B2(registers_31__ap[5]), + .ZN(n_1_0_760) + ); + SDFF_X1_LVT \registers_reg[15][5] ( + .CK(n_0_45), .D(registers[5]), .Q(registers_15__ap[5]), .QN(), .SE(dftIn), + .SI(registers_16__ap[5]) + ); + SDFF_X1_LVT \registers_reg[23][5] ( + .CK(n_0_53), .D(registers[5]), .Q(registers_23__ap[5]), .QN(), .SE(dftIn), + .SI(registers_1__ap[5]) + ); + AOI22_X1_LVT i_1_0_797( + .A1(registers_15__ap[5]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[5]), + .ZN(n_1_0_759) + ); + NAND4_X1_LVT i_1_0_796( + .A1(n_1_0_762), .A2(n_1_0_761), .A3(n_1_0_760), .A4(n_1_0_759), .ZN(n_1_0_758) + ); + SDFF_X1_LVT \registers_reg[18][5] ( + .CK(n_0_48), .D(registers[5]), .Q(registers_18__ap[5]), .QN(), .SE(dftIn), + .SI(registers_23__ap[5]) + ); + SDFF_X1_LVT \registers_reg[30][5] ( + .CK(n_0_60), .D(registers[5]), .Q(registers_30__ap[5]), .QN(), .SE(dftIn), + .SI(registers_29__ap[5]) + ); + AOI22_X1_LVT i_1_0_795( + .A1(registers_18__ap[5]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[5]), + .ZN(n_1_0_757) + ); + SDFF_X1_LVT \registers_reg[24][5] ( + .CK(n_0_54), .D(registers[5]), .Q(registers_24__ap[5]), .QN(), .SE(dftIn), + .SI(registers_30__ap[5]) + ); + SDFF_X1_LVT \registers_reg[12][5] ( + .CK(n_0_42), .D(registers[5]), .Q(registers_12__ap[5]), .QN(), .SE(dftIn), + .SI(registers_15__ap[5]) + ); + AOI22_X1_LVT i_1_0_794( + .A1(registers_24__ap[5]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[5]), + .ZN(n_1_0_756) + ); + SDFF_X1_LVT \registers_reg[22][5] ( + .CK(n_0_52), .D(registers[5]), .Q(registers_22__ap[5]), .QN(), .SE(dftIn), + .SI(registers_18__ap[5]) + ); + SDFF_X1_LVT \registers_reg[21][5] ( + .CK(n_0_51), .D(registers[5]), .Q(registers_21__ap[5]), .QN(), .SE(dftIn), + .SI(registers_22__ap[5]) + ); + AOI22_X1_LVT i_1_0_793( + .A1(registers_22__ap[5]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[5]), + .ZN(n_1_0_755) + ); + SDFF_X1_LVT \registers_reg[20][5] ( + .CK(n_0_50), .D(registers[5]), .Q(registers_20__ap[5]), .QN(), .SE(dftIn), + .SI(registers_21__ap[5]) + ); + SDFF_X1_LVT \registers_reg[17][5] ( + .CK(n_0_47), .D(registers[5]), .Q(registers_17__ap[5]), .QN(), .SE(dftIn), + .SI(registers_20__ap[5]) + ); + AOI22_X1_LVT i_1_0_792( + .A1(registers_20__ap[5]), .A2(n_1_0_1281), .B1(n_1_0_1271), .B2(registers_17__ap[5]), + .ZN(n_1_0_754) + ); + NAND4_X1_LVT i_1_0_791( + .A1(n_1_0_757), .A2(n_1_0_756), .A3(n_1_0_755), .A4(n_1_0_754), .ZN(n_1_0_753) + ); + SDFF_X1_LVT \registers_reg[13][5] ( + .CK(n_0_43), .D(registers[5]), .Q(registers_13__ap[5]), .QN(), .SE(dftIn), + .SI(registers_12__ap[5]) + ); + SDFF_X1_LVT \registers_reg[25][5] ( + .CK(n_0_55), .D(registers[5]), .Q(registers_25__ap[5]), .QN(), .SE(dftIn), + .SI(registers_24__ap[5]) + ); + AOI22_X1_LVT i_1_0_790( + .A1(registers_13__ap[5]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[5]), + .ZN(n_1_0_752) + ); + SDFF_X1_LVT \registers_reg[19][5] ( + .CK(n_0_49), .D(registers[5]), .Q(registers_19__ap[5]), .QN(), .SE(dftIn), + .SI(registers_17__ap[5]) + ); + SDFF_X1_LVT \registers_reg[2][5] ( + .CK(n_0_32), .D(registers[5]), .Q(registers_2__ap[5]), .QN(), .SE(dftIn), + .SI(registers_25__ap[5]) + ); + AOI22_X1_LVT i_1_0_789( + .A1(registers_19__ap[5]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[5]), + .ZN(n_1_0_751) + ); + SDFF_X1_LVT \registers_reg[7][5] ( + .CK(n_0_37), .D(registers[5]), .Q(registers_7__ap[5]), .QN(), .SE(dftIn), + .SI(registers_31__ap[5]) + ); + SDFF_X1_LVT \registers_reg[14][5] ( + .CK(n_0_44), .D(registers[5]), .Q(registers_14__ap[5]), .QN(), .SE(dftIn), + .SI(registers_13__ap[5]) + ); + AOI22_X1_LVT i_1_0_788( + .A1(registers_7__ap[5]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[5]), + .ZN(n_1_0_750) + ); + SDFF_X1_LVT \registers_reg[27][5] ( + .CK(n_0_57), .D(registers[5]), .Q(registers_27__ap[5]), .QN(), .SE(dftIn), + .SI(registers_2__ap[5]) + ); + SDFF_X1_LVT \registers_reg[11][5] ( + .CK(n_0_41), .D(registers[5]), .Q(registers_11__ap[5]), .QN(), .SE(dftIn), + .SI(registers_14__ap[5]) + ); + AOI22_X1_LVT i_1_0_787( + .A1(registers_27__ap[5]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[5]), + .ZN(n_1_0_749) + ); + NAND4_X1_LVT i_1_0_786( + .A1(n_1_0_752), .A2(n_1_0_751), .A3(n_1_0_750), .A4(n_1_0_749), .ZN(n_1_0_748) + ); + NOR3_X1_LVT i_1_0_785( + .A1(n_1_0_758), .A2(n_1_0_753), .A3(n_1_0_748), .ZN(n_1_0_747) + ); + NAND4_X1_LVT i_1_0_784( + .A1(n_1_0_765), .A2(n_1_0_764), .A3(n_1_0_763), .A4(n_1_0_747), .ZN(RRs1[5]) + ); + AND2_X1_LVT i_0_0_4( + .A1(n_0_0_16), .A2(WRd[4]), .ZN(registers[4]) + ); + SDFF_X1_LVT \registers_reg[10][4] ( + .CK(n_0_40), .D(registers[4]), .Q(registers_10__ap[4]), .QN(), .SE(dftIn), + .SI(registers_11__ap[5]) + ); + SDFF_X1_LVT \registers_reg[21][4] ( + .CK(n_0_51), .D(registers[4]), .Q(registers_21__ap[4]), .QN(), .SE(dftIn), + .SI(registers_19__ap[5]) + ); + AOI22_X1_LVT i_1_0_783( + .A1(registers_10__ap[4]), .A2(n_1_0_1287), .B1(n_1_0_1259), .B2(registers_21__ap[4]), + .ZN(n_1_0_746) + ); + SDFF_X1_LVT \registers_reg[9][4] ( + .CK(n_0_39), .D(registers[4]), .Q(registers_9__ap[4]), .QN(), .SE(dftIn), + .SI(registers_7__ap[5]) + ); + SDFF_X1_LVT \registers_reg[1][4] ( + .CK(n_0_0), .D(registers[4]), .Q(registers_1__ap[4]), .QN(), .SE(dftIn), + .SI(registers_21__ap[4]) + ); + AOI22_X1_LVT i_1_0_778( + .A1(registers_9__ap[4]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[4]), + .ZN(n_1_0_741) + ); + SDFF_X1_LVT \registers_reg[18][4] ( + .CK(n_0_48), .D(registers[4]), .Q(registers_18__ap[4]), .QN(), .SE(dftIn), + .SI(registers_1__ap[4]) + ); + SDFF_X1_LVT \registers_reg[8][4] ( + .CK(n_0_38), .D(registers[4]), .Q(registers_8__ap[4]), .QN(), .SE(dftIn), + .SI(registers_9__ap[4]) + ); + AOI22_X1_LVT i_1_0_777( + .A1(registers_18__ap[4]), .A2(n_1_0_1297), .B1(n_1_0_1282), .B2(registers_8__ap[4]), + .ZN(n_1_0_740) + ); + NAND3_X1_LVT i_1_0_775( + .A1(n_1_0_746), .A2(n_1_0_741), .A3(n_1_0_740), .ZN(n_1_0_738) + ); + SDFF_X1_LVT \registers_reg[22][4] ( + .CK(n_0_52), .D(registers[4]), .Q(registers_22__ap[4]), .QN(), .SE(dftIn), + .SI(registers_18__ap[4]) + ); + SDFF_X1_LVT \registers_reg[23][4] ( + .CK(n_0_53), .D(registers[4]), .Q(registers_23__ap[4]), .QN(), .SE(dftIn), + .SI(registers_22__ap[4]) + ); + AOI221_X1_LVT i_1_0_774( + .A(n_1_0_738), .B1(n_1_0_1294), .B2(registers_22__ap[4]), .C1(registers_23__ap[4]), + .C2(n_1_0_1264), .ZN(n_1_0_737) + ); + SDFF_X1_LVT \registers_reg[28][4] ( + .CK(n_0_58), .D(registers[4]), .Q(registers_28__ap[4]), .QN(), .SE(dftIn), + .SI(registers_27__ap[5]) + ); + SDFF_X1_LVT \registers_reg[20][4] ( + .CK(n_0_50), .D(registers[4]), .Q(registers_20__ap[4]), .QN(), .SE(dftIn), + .SI(registers_23__ap[4]) + ); + AOI22_X1_LVT i_1_0_782( + .A1(registers_28__ap[4]), .A2(n_1_0_1283), .B1(n_1_0_1281), .B2(registers_20__ap[4]), + .ZN(n_1_0_745) + ); + SDFF_X1_LVT \registers_reg[19][4] ( + .CK(n_0_49), .D(registers[4]), .Q(registers_19__ap[4]), .QN(), .SE(dftIn), + .SI(registers_20__ap[4]) + ); + SDFF_X1_LVT \registers_reg[13][4] ( + .CK(n_0_43), .D(registers[4]), .Q(registers_13__ap[4]), .QN(), .SE(dftIn), + .SI(registers_10__ap[4]) + ); + AOI22_X1_LVT i_1_0_780( + .A1(registers_19__ap[4]), .A2(n_1_0_1295), .B1(n_1_0_1277), .B2(registers_13__ap[4]), + .ZN(n_1_0_743) + ); + SDFF_X1_LVT \registers_reg[26][4] ( + .CK(n_0_56), .D(registers[4]), .Q(registers_26__ap[4]), .QN(), .SE(dftIn), + .SI(registers_28__ap[4]) + ); + SDFF_X1_LVT \registers_reg[3][4] ( + .CK(n_0_33), .D(registers[4]), .Q(registers_3__ap[4]), .QN(), .SE(dftIn), + .SI(registers_8__ap[4]) + ); + AOI22_X1_LVT i_1_0_776( + .A1(registers_26__ap[4]), .A2(n_1_0_1285), .B1(n_1_0_1257), .B2(registers_3__ap[4]), + .ZN(n_1_0_739) + ); + NAND3_X1_LVT i_1_0_773( + .A1(n_1_0_745), .A2(n_1_0_743), .A3(n_1_0_739), .ZN(n_1_0_736) + ); + SDFF_X1_LVT \registers_reg[30][4] ( + .CK(n_0_60), .D(registers[4]), .Q(registers_30__ap[4]), .QN(), .SE(dftIn), + .SI(registers_26__ap[4]) + ); + SDFF_X1_LVT \registers_reg[31][4] ( + .CK(n_0_61), .D(registers[4]), .Q(registers_31__ap[4]), .QN(), .SE(dftIn), + .SI(registers_3__ap[4]) + ); + AOI221_X1_LVT i_1_0_772( + .A(n_1_0_736), .B1(n_1_0_1272), .B2(registers_30__ap[4]), .C1(registers_31__ap[4]), + .C2(n_1_0_1266), .ZN(n_1_0_735) + ); + SDFF_X1_LVT \registers_reg[24][4] ( + .CK(n_0_54), .D(registers[4]), .Q(registers_24__ap[4]), .QN(), .SE(dftIn), + .SI(registers_30__ap[4]) + ); + SDFF_X1_LVT \registers_reg[12][4] ( + .CK(n_0_42), .D(registers[4]), .Q(registers_12__ap[4]), .QN(), .SE(dftIn), + .SI(registers_13__ap[4]) + ); + AOI22_X1_LVT i_1_0_781( + .A1(registers_24__ap[4]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[4]), + .ZN(n_1_0_744) + ); + SDFF_X1_LVT \registers_reg[27][4] ( + .CK(n_0_57), .D(registers[4]), .Q(registers_27__ap[4]), .QN(), .SE(dftIn), + .SI(registers_24__ap[4]) + ); + SDFF_X1_LVT \registers_reg[11][4] ( + .CK(n_0_41), .D(registers[4]), .Q(registers_11__ap[4]), .QN(), .SE(dftIn), + .SI(registers_12__ap[4]) + ); + AOI22_X1_LVT i_1_0_779( + .A1(registers_27__ap[4]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[4]), + .ZN(n_1_0_742) + ); + SDFF_X1_LVT \registers_reg[17][4] ( + .CK(n_0_47), .D(registers[4]), .Q(registers_17__ap[4]), .QN(), .SE(dftIn), + .SI(registers_19__ap[4]) + ); + SDFF_X1_LVT \registers_reg[7][4] ( + .CK(n_0_37), .D(registers[4]), .Q(registers_7__ap[4]), .QN(), .SE(dftIn), + .SI(registers_31__ap[4]) + ); + SDFF_X1_LVT \registers_reg[14][4] ( + .CK(n_0_44), .D(registers[4]), .Q(registers_14__ap[4]), .QN(), .SE(dftIn), + .SI(registers_11__ap[4]) + ); + AOI222_X1_LVT i_1_0_771( + .A1(registers_17__ap[4]), .A2(n_1_0_1271), .B1(n_1_0_1263), .B2(registers_7__ap[4]), + .C1(n_1_0_1258), .C2(registers_14__ap[4]), .ZN(n_1_0_734) + ); + SDFF_X1_LVT \registers_reg[15][4] ( + .CK(n_0_45), .D(registers[4]), .Q(registers_15__ap[4]), .QN(), .SE(dftIn), + .SI(registers_14__ap[4]) + ); + SDFF_X1_LVT \registers_reg[16][4] ( + .CK(n_0_46), .D(registers[4]), .Q(registers_16__ap[4]), .QN(), .SE(dftIn), + .SI(registers_15__ap[4]) + ); + AOI22_X1_LVT i_1_0_770( + .A1(registers_15__ap[4]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[4]), + .ZN(n_1_0_733) + ); + SDFF_X1_LVT \registers_reg[4][4] ( + .CK(n_0_34), .D(registers[4]), .Q(registers_4__ap[4]), .QN(), .SE(dftIn), + .SI(registers_7__ap[4]) + ); + SDFF_X1_LVT \registers_reg[25][4] ( + .CK(n_0_55), .D(registers[4]), .Q(registers_25__ap[4]), .QN(), .SE(dftIn), + .SI(registers_27__ap[4]) + ); + AOI22_X1_LVT i_1_0_769( + .A1(registers_4__ap[4]), .A2(n_1_0_1278), .B1(n_1_0_1269), .B2(registers_25__ap[4]), + .ZN(n_1_0_732) + ); + SDFF_X1_LVT \registers_reg[29][4] ( + .CK(n_0_59), .D(registers[4]), .Q(registers_29__ap[4]), .QN(), .SE(dftIn), + .SI(registers_25__ap[4]) + ); + SDFF_X1_LVT \registers_reg[2][4] ( + .CK(n_0_32), .D(registers[4]), .Q(registers_2__ap[4]), .QN(), .SE(dftIn), + .SI(registers_29__ap[4]) + ); + AOI22_X1_LVT i_1_0_768( + .A1(registers_29__ap[4]), .A2(n_1_0_1276), .B1(n_1_0_1268), .B2(registers_2__ap[4]), + .ZN(n_1_0_731) + ); + NAND3_X1_LVT i_1_0_767( + .A1(n_1_0_733), .A2(n_1_0_732), .A3(n_1_0_731), .ZN(n_1_0_730) + ); + SDFF_X1_LVT \registers_reg[6][4] ( + .CK(n_0_36), .D(registers[4]), .Q(registers_6__ap[4]), .QN(), .SE(dftIn), + .SI(registers_4__ap[4]) + ); + SDFF_X1_LVT \registers_reg[5][4] ( + .CK(n_0_35), .D(registers[4]), .Q(registers_5__ap[4]), .QN(), .SE(dftIn), + .SI(registers_6__ap[4]) + ); + AOI221_X1_LVT i_1_0_766( + .A(n_1_0_730), .B1(n_1_0_1300), .B2(registers_6__ap[4]), .C1(registers_5__ap[4]), + .C2(n_1_0_1273), .ZN(n_1_0_729) + ); + AND4_X1_LVT i_1_0_765( + .A1(n_1_0_744), .A2(n_1_0_742), .A3(n_1_0_734), .A4(n_1_0_729), .ZN(n_1_0_728) + ); + NAND3_X1_LVT i_1_0_764( + .A1(n_1_0_737), .A2(n_1_0_735), .A3(n_1_0_728), .ZN(RRs1[4]) + ); + AND2_X1_LVT i_0_0_3( + .A1(n_0_0_16), .A2(WRd[3]), .ZN(registers[3]) + ); + SDFF_X1_LVT \registers_reg[28][3] ( + .CK(n_0_58), .D(registers[3]), .Q(registers_28__ap[3]), .QN(), .SE(dftIn), + .SI(registers_2__ap[4]) + ); + SDFF_X1_LVT \registers_reg[17][3] ( + .CK(n_0_47), .D(registers[3]), .Q(registers_17__ap[3]), .QN(), .SE(dftIn), + .SI(registers_17__ap[4]) + ); + AOI22_X1_LVT i_1_0_763( + .A1(registers_28__ap[3]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[3]), + .ZN(n_1_0_727) + ); + SDFF_X1_LVT \registers_reg[10][3] ( + .CK(n_0_40), .D(registers[3]), .Q(registers_10__ap[3]), .QN(), .SE(dftIn), + .SI(registers_16__ap[4]) + ); + SDFF_X1_LVT \registers_reg[26][3] ( + .CK(n_0_56), .D(registers[3]), .Q(registers_26__ap[3]), .QN(), .SE(dftIn), + .SI(registers_28__ap[3]) + ); + SDFF_X1_LVT \registers_reg[8][3] ( + .CK(n_0_38), .D(registers[3]), .Q(registers_8__ap[3]), .QN(), .SE(dftIn), + .SI(registers_5__ap[4]) + ); + AOI222_X1_LVT i_1_0_762( + .A1(registers_10__ap[3]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[3]), + .C1(registers_8__ap[3]), .C2(n_1_0_1282), .ZN(n_1_0_726) + ); + SDFF_X1_LVT \registers_reg[9][3] ( + .CK(n_0_39), .D(registers[3]), .Q(registers_9__ap[3]), .QN(), .SE(dftIn), + .SI(registers_8__ap[3]) + ); + SDFF_X1_LVT \registers_reg[29][3] ( + .CK(n_0_59), .D(registers[3]), .Q(registers_29__ap[3]), .QN(), .SE(dftIn), + .SI(registers_26__ap[3]) + ); + AOI22_X1_LVT i_1_0_761( + .A1(registers_9__ap[3]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[3]), + .ZN(n_1_0_725) + ); + SDFF_X1_LVT \registers_reg[6][3] ( + .CK(n_0_36), .D(registers[3]), .Q(registers_6__ap[3]), .QN(), .SE(dftIn), + .SI(registers_9__ap[3]) + ); + SDFF_X1_LVT \registers_reg[1][3] ( + .CK(n_0_0), .D(registers[3]), .Q(registers_1__ap[3]), .QN(), .SE(dftIn), + .SI(registers_17__ap[3]) + ); + AOI22_X1_LVT i_1_0_760( + .A1(registers_6__ap[3]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[3]), + .ZN(n_1_0_724) + ); + SDFF_X1_LVT \registers_reg[16][3] ( + .CK(n_0_46), .D(registers[3]), .Q(registers_16__ap[3]), .QN(), .SE(dftIn), + .SI(registers_10__ap[3]) + ); + SDFF_X1_LVT \registers_reg[3][3] ( + .CK(n_0_33), .D(registers[3]), .Q(registers_3__ap[3]), .QN(), .SE(dftIn), + .SI(registers_6__ap[3]) + ); + AOI22_X1_LVT i_1_0_759( + .A1(registers_16__ap[3]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[3]), + .ZN(n_1_0_723) + ); + SDFF_X1_LVT \registers_reg[5][3] ( + .CK(n_0_35), .D(registers[3]), .Q(registers_5__ap[3]), .QN(), .SE(dftIn), + .SI(registers_3__ap[3]) + ); + SDFF_X1_LVT \registers_reg[31][3] ( + .CK(n_0_61), .D(registers[3]), .Q(registers_31__ap[3]), .QN(), .SE(dftIn), + .SI(registers_5__ap[3]) + ); + AOI22_X1_LVT i_1_0_758( + .A1(registers_5__ap[3]), .A2(n_1_0_1273), .B1(n_1_0_1266), .B2(registers_31__ap[3]), + .ZN(n_1_0_722) + ); + SDFF_X1_LVT \registers_reg[15][3] ( + .CK(n_0_45), .D(registers[3]), .Q(registers_15__ap[3]), .QN(), .SE(dftIn), + .SI(registers_16__ap[3]) + ); + SDFF_X1_LVT \registers_reg[23][3] ( + .CK(n_0_53), .D(registers[3]), .Q(registers_23__ap[3]), .QN(), .SE(dftIn), + .SI(registers_1__ap[3]) + ); + AOI22_X1_LVT i_1_0_757( + .A1(registers_15__ap[3]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[3]), + .ZN(n_1_0_721) + ); + NAND4_X1_LVT i_1_0_756( + .A1(n_1_0_724), .A2(n_1_0_723), .A3(n_1_0_722), .A4(n_1_0_721), .ZN(n_1_0_720) + ); + SDFF_X1_LVT \registers_reg[18][3] ( + .CK(n_0_48), .D(registers[3]), .Q(registers_18__ap[3]), .QN(), .SE(dftIn), + .SI(registers_23__ap[3]) + ); + SDFF_X1_LVT \registers_reg[30][3] ( + .CK(n_0_60), .D(registers[3]), .Q(registers_30__ap[3]), .QN(), .SE(dftIn), + .SI(registers_29__ap[3]) + ); + AOI22_X1_LVT i_1_0_755( + .A1(registers_18__ap[3]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[3]), + .ZN(n_1_0_719) + ); + SDFF_X1_LVT \registers_reg[20][3] ( + .CK(n_0_50), .D(registers[3]), .Q(registers_20__ap[3]), .QN(), .SE(dftIn), + .SI(registers_18__ap[3]) + ); + SDFF_X1_LVT \registers_reg[4][3] ( + .CK(n_0_34), .D(registers[3]), .Q(registers_4__ap[3]), .QN(), .SE(dftIn), + .SI(registers_31__ap[3]) + ); + AOI22_X1_LVT i_1_0_754( + .A1(registers_20__ap[3]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[3]), + .ZN(n_1_0_718) + ); + SDFF_X1_LVT \registers_reg[22][3] ( + .CK(n_0_52), .D(registers[3]), .Q(registers_22__ap[3]), .QN(), .SE(dftIn), + .SI(registers_20__ap[3]) + ); + SDFF_X1_LVT \registers_reg[21][3] ( + .CK(n_0_51), .D(registers[3]), .Q(registers_21__ap[3]), .QN(), .SE(dftIn), + .SI(registers_22__ap[3]) + ); + AOI22_X1_LVT i_1_0_753( + .A1(registers_22__ap[3]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[3]), + .ZN(n_1_0_717) + ); + SDFF_X1_LVT \registers_reg[24][3] ( + .CK(n_0_54), .D(registers[3]), .Q(registers_24__ap[3]), .QN(), .SE(dftIn), + .SI(registers_30__ap[3]) + ); + SDFF_X1_LVT \registers_reg[12][3] ( + .CK(n_0_42), .D(registers[3]), .Q(registers_12__ap[3]), .QN(), .SE(dftIn), + .SI(registers_15__ap[3]) + ); + AOI22_X1_LVT i_1_0_752( + .A1(registers_24__ap[3]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[3]), + .ZN(n_1_0_716) + ); + NAND4_X1_LVT i_1_0_751( + .A1(n_1_0_719), .A2(n_1_0_718), .A3(n_1_0_717), .A4(n_1_0_716), .ZN(n_1_0_715) + ); + SDFF_X1_LVT \registers_reg[13][3] ( + .CK(n_0_43), .D(registers[3]), .Q(registers_13__ap[3]), .QN(), .SE(dftIn), + .SI(registers_12__ap[3]) + ); + SDFF_X1_LVT \registers_reg[25][3] ( + .CK(n_0_55), .D(registers[3]), .Q(registers_25__ap[3]), .QN(), .SE(dftIn), + .SI(registers_24__ap[3]) + ); + AOI22_X1_LVT i_1_0_750( + .A1(registers_13__ap[3]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[3]), + .ZN(n_1_0_714) + ); + SDFF_X1_LVT \registers_reg[19][3] ( + .CK(n_0_49), .D(registers[3]), .Q(registers_19__ap[3]), .QN(), .SE(dftIn), + .SI(registers_21__ap[3]) + ); + SDFF_X1_LVT \registers_reg[2][3] ( + .CK(n_0_32), .D(registers[3]), .Q(registers_2__ap[3]), .QN(), .SE(dftIn), + .SI(registers_25__ap[3]) + ); + AOI22_X1_LVT i_1_0_749( + .A1(registers_19__ap[3]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[3]), + .ZN(n_1_0_713) + ); + SDFF_X1_LVT \registers_reg[7][3] ( + .CK(n_0_37), .D(registers[3]), .Q(registers_7__ap[3]), .QN(), .SE(dftIn), + .SI(registers_4__ap[3]) + ); + SDFF_X1_LVT \registers_reg[14][3] ( + .CK(n_0_44), .D(registers[3]), .Q(registers_14__ap[3]), .QN(), .SE(dftIn), + .SI(registers_13__ap[3]) + ); + AOI22_X1_LVT i_1_0_748( + .A1(registers_7__ap[3]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[3]), + .ZN(n_1_0_712) + ); + SDFF_X1_LVT \registers_reg[27][3] ( + .CK(n_0_57), .D(registers[3]), .Q(registers_27__ap[3]), .QN(), .SE(dftIn), + .SI(registers_2__ap[3]) + ); + SDFF_X1_LVT \registers_reg[11][3] ( + .CK(n_0_41), .D(registers[3]), .Q(registers_11__ap[3]), .QN(), .SE(dftIn), + .SI(registers_14__ap[3]) + ); + AOI22_X1_LVT i_1_0_747( + .A1(registers_27__ap[3]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[3]), + .ZN(n_1_0_711) + ); + NAND4_X1_LVT i_1_0_746( + .A1(n_1_0_714), .A2(n_1_0_713), .A3(n_1_0_712), .A4(n_1_0_711), .ZN(n_1_0_710) + ); + NOR3_X1_LVT i_1_0_745( + .A1(n_1_0_720), .A2(n_1_0_715), .A3(n_1_0_710), .ZN(n_1_0_709) + ); + NAND4_X1_LVT i_1_0_744( + .A1(n_1_0_727), .A2(n_1_0_726), .A3(n_1_0_725), .A4(n_1_0_709), .ZN(RRs1[3]) + ); + AND2_X1_LVT i_0_0_2( + .A1(n_0_0_16), .A2(WRd[2]), .ZN(registers[2]) + ); + SDFF_X1_LVT \registers_reg[28][2] ( + .CK(n_0_58), .D(registers[2]), .Q(registers_28__ap[2]), .QN(), .SE(dftIn), + .SI(registers_27__ap[3]) + ); + SDFF_X1_LVT \registers_reg[4][2] ( + .CK(n_0_34), .D(registers[2]), .Q(registers_4__ap[2]), .QN(), .SE(dftIn), + .SI(registers_7__ap[3]) + ); + AOI22_X1_LVT i_1_0_740( + .A1(registers_28__ap[2]), .A2(n_1_0_1283), .B1(n_1_0_1278), .B2(registers_4__ap[2]), + .ZN(n_1_0_705) + ); + SDFF_X1_LVT \registers_reg[16][2] ( + .CK(n_0_46), .D(registers[2]), .Q(registers_16__ap[2]), .QN(), .SE(dftIn), + .SI(registers_11__ap[3]) + ); + SDFF_X1_LVT \registers_reg[31][2] ( + .CK(n_0_61), .D(registers[2]), .Q(registers_31__ap[2]), .QN(), .SE(dftIn), + .SI(registers_4__ap[2]) + ); + AOI22_X1_LVT i_1_0_743( + .A1(registers_16__ap[2]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[2]), + .ZN(n_1_0_708) + ); + SDFF_X1_LVT \registers_reg[6][2] ( + .CK(n_0_36), .D(registers[2]), .Q(registers_6__ap[2]), .QN(), .SE(dftIn), + .SI(registers_31__ap[2]) + ); + SDFF_X1_LVT \registers_reg[1][2] ( + .CK(n_0_0), .D(registers[2]), .Q(registers_1__ap[2]), .QN(), .SE(dftIn), + .SI(registers_19__ap[3]) + ); + AOI22_X1_LVT i_1_0_739( + .A1(registers_6__ap[2]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[2]), + .ZN(n_1_0_704) + ); + SDFF_X1_LVT \registers_reg[15][2] ( + .CK(n_0_45), .D(registers[2]), .Q(registers_15__ap[2]), .QN(), .SE(dftIn), + .SI(registers_16__ap[2]) + ); + SDFF_X1_LVT \registers_reg[27][2] ( + .CK(n_0_57), .D(registers[2]), .Q(registers_27__ap[2]), .QN(), .SE(dftIn), + .SI(registers_28__ap[2]) + ); + AOI22_X1_LVT i_1_0_742( + .A1(registers_15__ap[2]), .A2(n_1_0_1286), .B1(n_1_0_1279), .B2(registers_27__ap[2]), + .ZN(n_1_0_707) + ); + INV_X1_LVT i_1_0_741( + .A(n_1_0_707), .ZN(n_1_0_706) + ); + SDFF_X1_LVT \registers_reg[11][2] ( + .CK(n_0_41), .D(registers[2]), .Q(registers_11__ap[2]), .QN(), .SE(dftIn), + .SI(registers_15__ap[2]) + ); + SDFF_X1_LVT \registers_reg[5][2] ( + .CK(n_0_35), .D(registers[2]), .Q(registers_5__ap[2]), .QN(), .SE(dftIn), + .SI(registers_6__ap[2]) + ); + AOI221_X1_LVT i_1_0_738( + .A(n_1_0_706), .B1(n_1_0_1270), .B2(registers_11__ap[2]), .C1(registers_5__ap[2]), + .C2(n_1_0_1273), .ZN(n_1_0_703) + ); + SDFF_X1_LVT \registers_reg[10][2] ( + .CK(n_0_40), .D(registers[2]), .Q(registers_10__ap[2]), .QN(), .SE(dftIn), + .SI(registers_11__ap[2]) + ); + SDFF_X1_LVT \registers_reg[30][2] ( + .CK(n_0_60), .D(registers[2]), .Q(registers_30__ap[2]), .QN(), .SE(dftIn), + .SI(registers_27__ap[2]) + ); + SDFF_X1_LVT \registers_reg[8][2] ( + .CK(n_0_38), .D(registers[2]), .Q(registers_8__ap[2]), .QN(), .SE(dftIn), + .SI(registers_5__ap[2]) + ); + AOI222_X1_LVT i_1_0_737( + .A1(registers_10__ap[2]), .A2(n_1_0_1287), .B1(n_1_0_1272), .B2(registers_30__ap[2]), + .C1(n_1_0_1282), .C2(registers_8__ap[2]), .ZN(n_1_0_702) + ); + NAND4_X1_LVT i_1_0_736( + .A1(n_1_0_708), .A2(n_1_0_704), .A3(n_1_0_703), .A4(n_1_0_702), .ZN(n_1_0_701) + ); + SDFF_X1_LVT \registers_reg[9][2] ( + .CK(n_0_39), .D(registers[2]), .Q(registers_9__ap[2]), .QN(), .SE(dftIn), + .SI(registers_8__ap[2]) + ); + SDFF_X1_LVT \registers_reg[29][2] ( + .CK(n_0_59), .D(registers[2]), .Q(registers_29__ap[2]), .QN(), .SE(dftIn), + .SI(registers_30__ap[2]) + ); + AOI221_X1_LVT i_1_0_735( + .A(n_1_0_701), .B1(n_1_0_1291), .B2(registers_9__ap[2]), .C1(registers_29__ap[2]), + .C2(n_1_0_1276), .ZN(n_1_0_700) + ); + SDFF_X1_LVT \registers_reg[18][2] ( + .CK(n_0_48), .D(registers[2]), .Q(registers_18__ap[2]), .QN(), .SE(dftIn), + .SI(registers_1__ap[2]) + ); + SDFF_X1_LVT \registers_reg[26][2] ( + .CK(n_0_56), .D(registers[2]), .Q(registers_26__ap[2]), .QN(), .SE(dftIn), + .SI(registers_29__ap[2]) + ); + AOI22_X1_LVT i_1_0_734( + .A1(registers_18__ap[2]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[2]), + .ZN(n_1_0_699) + ); + SDFF_X1_LVT \registers_reg[24][2] ( + .CK(n_0_54), .D(registers[2]), .Q(registers_24__ap[2]), .QN(), .SE(dftIn), + .SI(registers_26__ap[2]) + ); + SDFF_X1_LVT \registers_reg[12][2] ( + .CK(n_0_42), .D(registers[2]), .Q(registers_12__ap[2]), .QN(), .SE(dftIn), + .SI(registers_10__ap[2]) + ); + AOI22_X1_LVT i_1_0_733( + .A1(registers_24__ap[2]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[2]), + .ZN(n_1_0_698) + ); + SDFF_X1_LVT \registers_reg[22][2] ( + .CK(n_0_52), .D(registers[2]), .Q(registers_22__ap[2]), .QN(), .SE(dftIn), + .SI(registers_18__ap[2]) + ); + SDFF_X1_LVT \registers_reg[21][2] ( + .CK(n_0_51), .D(registers[2]), .Q(registers_21__ap[2]), .QN(), .SE(dftIn), + .SI(registers_22__ap[2]) + ); + AOI22_X1_LVT i_1_0_732( + .A1(registers_22__ap[2]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[2]), + .ZN(n_1_0_697) + ); + NAND3_X1_LVT i_1_0_731( + .A1(n_1_0_699), .A2(n_1_0_698), .A3(n_1_0_697), .ZN(n_1_0_696) + ); + SDFF_X1_LVT \registers_reg[17][2] ( + .CK(n_0_47), .D(registers[2]), .Q(registers_17__ap[2]), .QN(), .SE(dftIn), + .SI(registers_21__ap[2]) + ); + SDFF_X1_LVT \registers_reg[20][2] ( + .CK(n_0_50), .D(registers[2]), .Q(registers_20__ap[2]), .QN(), .SE(dftIn), + .SI(registers_17__ap[2]) + ); + AOI221_X1_LVT i_1_0_730( + .A(n_1_0_696), .B1(n_1_0_1271), .B2(registers_17__ap[2]), .C1(registers_20__ap[2]), + .C2(n_1_0_1281), .ZN(n_1_0_695) + ); + SDFF_X1_LVT \registers_reg[13][2] ( + .CK(n_0_43), .D(registers[2]), .Q(registers_13__ap[2]), .QN(), .SE(dftIn), + .SI(registers_12__ap[2]) + ); + SDFF_X1_LVT \registers_reg[25][2] ( + .CK(n_0_55), .D(registers[2]), .Q(registers_25__ap[2]), .QN(), .SE(dftIn), + .SI(registers_24__ap[2]) + ); + AOI22_X1_LVT i_1_0_729( + .A1(registers_13__ap[2]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[2]), + .ZN(n_1_0_694) + ); + SDFF_X1_LVT \registers_reg[7][2] ( + .CK(n_0_37), .D(registers[2]), .Q(registers_7__ap[2]), .QN(), .SE(dftIn), + .SI(registers_9__ap[2]) + ); + SDFF_X1_LVT \registers_reg[14][2] ( + .CK(n_0_44), .D(registers[2]), .Q(registers_14__ap[2]), .QN(), .SE(dftIn), + .SI(registers_13__ap[2]) + ); + AOI22_X1_LVT i_1_0_728( + .A1(registers_7__ap[2]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[2]), + .ZN(n_1_0_693) + ); + SDFF_X1_LVT \registers_reg[19][2] ( + .CK(n_0_49), .D(registers[2]), .Q(registers_19__ap[2]), .QN(), .SE(dftIn), + .SI(registers_20__ap[2]) + ); + SDFF_X1_LVT \registers_reg[3][2] ( + .CK(n_0_33), .D(registers[2]), .Q(registers_3__ap[2]), .QN(), .SE(dftIn), + .SI(registers_7__ap[2]) + ); + AOI22_X1_LVT i_1_0_727( + .A1(registers_19__ap[2]), .A2(n_1_0_1295), .B1(n_1_0_1257), .B2(registers_3__ap[2]), + .ZN(n_1_0_692) + ); + NAND3_X1_LVT i_1_0_726( + .A1(n_1_0_694), .A2(n_1_0_693), .A3(n_1_0_692), .ZN(n_1_0_691) + ); + SDFF_X1_LVT \registers_reg[23][2] ( + .CK(n_0_53), .D(registers[2]), .Q(registers_23__ap[2]), .QN(), .SE(dftIn), + .SI(registers_19__ap[2]) + ); + SDFF_X1_LVT \registers_reg[2][2] ( + .CK(n_0_32), .D(registers[2]), .Q(registers_2__ap[2]), .QN(), .SE(dftIn), + .SI(registers_25__ap[2]) + ); + AOI221_X1_LVT i_1_0_725( + .A(n_1_0_691), .B1(n_1_0_1264), .B2(registers_23__ap[2]), .C1(registers_2__ap[2]), + .C2(n_1_0_1268), .ZN(n_1_0_690) + ); + NAND4_X1_LVT i_1_0_724( + .A1(n_1_0_705), .A2(n_1_0_700), .A3(n_1_0_695), .A4(n_1_0_690), .ZN(RRs1[2]) + ); + AND2_X1_LVT i_0_0_1( + .A1(n_0_0_16), .A2(WRd[1]), .ZN(registers[1]) + ); + SDFF_X1_LVT \registers_reg[13][1] ( + .CK(n_0_43), .D(registers[1]), .Q(registers_13__ap[1]), .QN(), .SE(dftIn), + .SI(registers_14__ap[2]) + ); + SDFF_X1_LVT \registers_reg[21][1] ( + .CK(n_0_51), .D(registers[1]), .Q(registers_21__ap[1]), .QN(), .SE(dftIn), + .SI(registers_23__ap[2]) + ); + AOI22_X1_LVT i_1_0_720( + .A1(registers_13__ap[1]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[1]), + .ZN(n_1_0_686) + ); + SDFF_X1_LVT \registers_reg[29][1] ( + .CK(n_0_59), .D(registers[1]), .Q(registers_29__ap[1]), .QN(), .SE(dftIn), + .SI(registers_2__ap[2]) + ); + SDFF_X1_LVT \registers_reg[23][1] ( + .CK(n_0_53), .D(registers[1]), .Q(registers_23__ap[1]), .QN(), .SE(dftIn), + .SI(registers_21__ap[1]) + ); + AOI22_X1_LVT i_1_0_723( + .A1(registers_29__ap[1]), .A2(n_1_0_1276), .B1(n_1_0_1264), .B2(registers_23__ap[1]), + .ZN(n_1_0_689) + ); + SDFF_X1_LVT \registers_reg[24][1] ( + .CK(n_0_54), .D(registers[1]), .Q(registers_24__ap[1]), .QN(), .SE(dftIn), + .SI(registers_29__ap[1]) + ); + SDFF_X1_LVT \registers_reg[20][1] ( + .CK(n_0_50), .D(registers[1]), .Q(registers_20__ap[1]), .QN(), .SE(dftIn), + .SI(registers_23__ap[1]) + ); + AOI22_X1_LVT i_1_0_719( + .A1(registers_24__ap[1]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[1]), + .ZN(n_1_0_685) + ); + SDFF_X1_LVT \registers_reg[7][1] ( + .CK(n_0_37), .D(registers[1]), .Q(registers_7__ap[1]), .QN(), .SE(dftIn), + .SI(registers_3__ap[2]) + ); + SDFF_X1_LVT \registers_reg[3][1] ( + .CK(n_0_33), .D(registers[1]), .Q(registers_3__ap[1]), .QN(), .SE(dftIn), + .SI(registers_7__ap[1]) + ); + AOI22_X1_LVT i_1_0_722( + .A1(registers_7__ap[1]), .A2(n_1_0_1263), .B1(n_1_0_1257), .B2(registers_3__ap[1]), + .ZN(n_1_0_688) + ); + INV_X1_LVT i_1_0_721( + .A(n_1_0_688), .ZN(n_1_0_687) + ); + SDFF_X1_LVT \registers_reg[31][1] ( + .CK(n_0_61), .D(registers[1]), .Q(registers_31__ap[1]), .QN(), .SE(dftIn), + .SI(registers_3__ap[1]) + ); + SDFF_X1_LVT \registers_reg[4][1] ( + .CK(n_0_34), .D(registers[1]), .Q(registers_4__ap[1]), .QN(), .SE(dftIn), + .SI(registers_31__ap[1]) + ); + AOI221_X1_LVT i_1_0_718( + .A(n_1_0_687), .B1(n_1_0_1266), .B2(registers_31__ap[1]), .C1(registers_4__ap[1]), + .C2(n_1_0_1278), .ZN(n_1_0_684) + ); + SDFF_X1_LVT \registers_reg[10][1] ( + .CK(n_0_40), .D(registers[1]), .Q(registers_10__ap[1]), .QN(), .SE(dftIn), + .SI(registers_13__ap[1]) + ); + SDFF_X1_LVT \registers_reg[26][1] ( + .CK(n_0_56), .D(registers[1]), .Q(registers_26__ap[1]), .QN(), .SE(dftIn), + .SI(registers_24__ap[1]) + ); + SDFF_X1_LVT \registers_reg[25][1] ( + .CK(n_0_55), .D(registers[1]), .Q(registers_25__ap[1]), .QN(), .SE(dftIn), + .SI(registers_26__ap[1]) + ); + AOI222_X1_LVT i_1_0_717( + .A1(registers_10__ap[1]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[1]), + .C1(registers_25__ap[1]), .C2(n_1_0_1269), .ZN(n_1_0_683) + ); + NAND4_X1_LVT i_1_0_716( + .A1(n_1_0_689), .A2(n_1_0_685), .A3(n_1_0_684), .A4(n_1_0_683), .ZN(n_1_0_682) + ); + SDFF_X1_LVT \registers_reg[8][1] ( + .CK(n_0_38), .D(registers[1]), .Q(registers_8__ap[1]), .QN(), .SE(dftIn), + .SI(registers_4__ap[1]) + ); + SDFF_X1_LVT \registers_reg[28][1] ( + .CK(n_0_58), .D(registers[1]), .Q(registers_28__ap[1]), .QN(), .SE(dftIn), + .SI(registers_25__ap[1]) + ); + AOI221_X1_LVT i_1_0_715( + .A(n_1_0_682), .B1(n_1_0_1282), .B2(registers_8__ap[1]), .C1(registers_28__ap[1]), + .C2(n_1_0_1283), .ZN(n_1_0_681) + ); + SDFF_X1_LVT \registers_reg[18][1] ( + .CK(n_0_48), .D(registers[1]), .Q(registers_18__ap[1]), .QN(), .SE(dftIn), + .SI(registers_20__ap[1]) + ); + SDFF_X1_LVT \registers_reg[30][1] ( + .CK(n_0_60), .D(registers[1]), .Q(registers_30__ap[1]), .QN(), .SE(dftIn), + .SI(registers_28__ap[1]) + ); + AOI22_X1_LVT i_1_0_714( + .A1(registers_18__ap[1]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[1]), + .ZN(n_1_0_680) + ); + SDFF_X1_LVT \registers_reg[17][1] ( + .CK(n_0_47), .D(registers[1]), .Q(registers_17__ap[1]), .QN(), .SE(dftIn), + .SI(registers_18__ap[1]) + ); + SDFF_X1_LVT \registers_reg[12][1] ( + .CK(n_0_42), .D(registers[1]), .Q(registers_12__ap[1]), .QN(), .SE(dftIn), + .SI(registers_10__ap[1]) + ); + AOI22_X1_LVT i_1_0_713( + .A1(registers_17__ap[1]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[1]), + .ZN(n_1_0_679) + ); + SDFF_X1_LVT \registers_reg[15][1] ( + .CK(n_0_45), .D(registers[1]), .Q(registers_15__ap[1]), .QN(), .SE(dftIn), + .SI(registers_12__ap[1]) + ); + SDFF_X1_LVT \registers_reg[5][1] ( + .CK(n_0_35), .D(registers[1]), .Q(registers_5__ap[1]), .QN(), .SE(dftIn), + .SI(registers_8__ap[1]) + ); + AOI22_X1_LVT i_1_0_712( + .A1(registers_15__ap[1]), .A2(n_1_0_1286), .B1(n_1_0_1273), .B2(registers_5__ap[1]), + .ZN(n_1_0_678) + ); + NAND3_X1_LVT i_1_0_711( + .A1(n_1_0_680), .A2(n_1_0_679), .A3(n_1_0_678), .ZN(n_1_0_677) + ); + SDFF_X1_LVT \registers_reg[22][1] ( + .CK(n_0_52), .D(registers[1]), .Q(registers_22__ap[1]), .QN(), .SE(dftIn), + .SI(registers_17__ap[1]) + ); + SDFF_X1_LVT \registers_reg[16][1] ( + .CK(n_0_46), .D(registers[1]), .Q(registers_16__ap[1]), .QN(), .SE(dftIn), + .SI(registers_15__ap[1]) + ); + AOI221_X1_LVT i_1_0_710( + .A(n_1_0_677), .B1(n_1_0_1294), .B2(registers_22__ap[1]), .C1(registers_16__ap[1]), + .C2(n_1_0_1267), .ZN(n_1_0_676) + ); + SDFF_X1_LVT \registers_reg[9][1] ( + .CK(n_0_39), .D(registers[1]), .Q(registers_9__ap[1]), .QN(), .SE(dftIn), + .SI(registers_5__ap[1]) + ); + SDFF_X1_LVT \registers_reg[1][1] ( + .CK(n_0_0), .D(registers[1]), .Q(registers_1__ap[1]), .QN(), .SE(dftIn), + .SI(registers_22__ap[1]) + ); + AOI22_X1_LVT i_1_0_709( + .A1(registers_9__ap[1]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[1]), + .ZN(n_1_0_675) + ); + SDFF_X1_LVT \registers_reg[6][1] ( + .CK(n_0_36), .D(registers[1]), .Q(registers_6__ap[1]), .QN(), .SE(dftIn), + .SI(registers_9__ap[1]) + ); + SDFF_X1_LVT \registers_reg[14][1] ( + .CK(n_0_44), .D(registers[1]), .Q(registers_14__ap[1]), .QN(), .SE(dftIn), + .SI(registers_16__ap[1]) + ); + AOI22_X1_LVT i_1_0_708( + .A1(registers_6__ap[1]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[1]), + .ZN(n_1_0_674) + ); + SDFF_X1_LVT \registers_reg[19][1] ( + .CK(n_0_49), .D(registers[1]), .Q(registers_19__ap[1]), .QN(), .SE(dftIn), + .SI(registers_1__ap[1]) + ); + SDFF_X1_LVT \registers_reg[2][1] ( + .CK(n_0_32), .D(registers[1]), .Q(registers_2__ap[1]), .QN(), .SE(dftIn), + .SI(registers_30__ap[1]) + ); + AOI22_X1_LVT i_1_0_707( + .A1(registers_19__ap[1]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[1]), + .ZN(n_1_0_673) + ); + NAND3_X1_LVT i_1_0_706( + .A1(n_1_0_675), .A2(n_1_0_674), .A3(n_1_0_673), .ZN(n_1_0_672) + ); + SDFF_X1_LVT \registers_reg[11][1] ( + .CK(n_0_41), .D(registers[1]), .Q(registers_11__ap[1]), .QN(), .SE(dftIn), + .SI(registers_14__ap[1]) + ); + SDFF_X1_LVT \registers_reg[27][1] ( + .CK(n_0_57), .D(registers[1]), .Q(registers_27__ap[1]), .QN(), .SE(dftIn), + .SI(registers_2__ap[1]) + ); + AOI221_X1_LVT i_1_0_705( + .A(n_1_0_672), .B1(n_1_0_1270), .B2(registers_11__ap[1]), .C1(registers_27__ap[1]), + .C2(n_1_0_1279), .ZN(n_1_0_671) + ); + NAND4_X1_LVT i_1_0_704( + .A1(n_1_0_686), .A2(n_1_0_681), .A3(n_1_0_676), .A4(n_1_0_671), .ZN(RRs1[1]) + ); + AND2_X1_LVT i_0_0_0( + .A1(n_0_0_16), .A2(WRd[0]), .ZN(registers[0]) + ); + SDFF_X1_LVT \registers_reg[13][0] ( + .CK(n_0_43), .D(registers[0]), .Q(registers_13__ap[0]), .QN(), .SE(dftIn), + .SI(registers_11__ap[1]) + ); + SDFF_X1_LVT \registers_reg[21][0] ( + .CK(n_0_51), .D(registers[0]), .Q(registers_21__ap[0]), .QN(), .SE(dftIn), + .SI(registers_19__ap[1]) + ); + AOI22_X1_LVT i_1_0_703( + .A1(registers_13__ap[0]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[0]), + .ZN(n_1_0_670) + ); + SDFF_X1_LVT \registers_reg[10][0] ( + .CK(n_0_40), .D(registers[0]), .Q(registers_10__ap[0]), .QN(), .SE(dftIn), + .SI(registers_13__ap[0]) + ); + SDFF_X1_LVT \registers_reg[26][0] ( + .CK(n_0_56), .D(registers[0]), .Q(registers_26__ap[0]), .QN(), .SE(dftIn), + .SI(registers_27__ap[1]) + ); + SDFF_X1_LVT \registers_reg[25][0] ( + .CK(n_0_55), .D(registers[0]), .Q(registers_25__ap[0]), .QN(), .SE(dftIn), + .SI(registers_26__ap[0]) + ); + AOI222_X1_LVT i_1_0_702( + .A1(registers_10__ap[0]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[0]), + .C1(registers_25__ap[0]), .C2(n_1_0_1269), .ZN(n_1_0_669) + ); + SDFF_X1_LVT \registers_reg[28][0] ( + .CK(n_0_58), .D(registers[0]), .Q(registers_28__ap[0]), .QN(), .SE(dftIn), + .SI(registers_25__ap[0]) + ); + SDFF_X1_LVT \registers_reg[8][0] ( + .CK(n_0_38), .D(registers[0]), .Q(registers_8__ap[0]), .QN(), .SE(dftIn), + .SI(registers_6__ap[1]) + ); + AOI22_X1_LVT i_1_0_701( + .A1(registers_28__ap[0]), .A2(n_1_0_1283), .B1(n_1_0_1282), .B2(registers_8__ap[0]), + .ZN(n_1_0_668) + ); + SDFF_X1_LVT \registers_reg[24][0] ( + .CK(n_0_54), .D(registers[0]), .Q(registers_24__ap[0]), .QN(), .SE(dftIn), + .SI(registers_28__ap[0]) + ); + SDFF_X1_LVT \registers_reg[20][0] ( + .CK(n_0_50), .D(registers[0]), .Q(registers_20__ap[0]), .QN(), .SE(dftIn), + .SI(registers_21__ap[0]) + ); + AOI22_X1_LVT i_1_0_700( + .A1(registers_24__ap[0]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[0]), + .ZN(n_1_0_667) + ); + SDFF_X1_LVT \registers_reg[7][0] ( + .CK(n_0_37), .D(registers[0]), .Q(registers_7__ap[0]), .QN(), .SE(dftIn), + .SI(registers_8__ap[0]) + ); + SDFF_X1_LVT \registers_reg[3][0] ( + .CK(n_0_33), .D(registers[0]), .Q(registers_3__ap[0]), .QN(), .SE(dftIn), + .SI(registers_7__ap[0]) + ); + AOI22_X1_LVT i_1_0_699( + .A1(registers_7__ap[0]), .A2(n_1_0_1263), .B1(n_1_0_1257), .B2(registers_3__ap[0]), + .ZN(n_1_0_666) + ); + SDFF_X1_LVT \registers_reg[17][0] ( + .CK(n_0_47), .D(registers[0]), .Q(registers_17__ap[0]), .QN(), .SE(dftIn), + .SI(registers_20__ap[0]) + ); + SDFF_X1_LVT \registers_reg[31][0] ( + .CK(n_0_61), .D(registers[0]), .Q(registers_31__ap[0]), .QN(), .SE(dftIn), + .SI(registers_3__ap[0]) + ); + AOI22_X1_LVT i_1_0_698( + .A1(registers_17__ap[0]), .A2(n_1_0_1271), .B1(n_1_0_1266), .B2(registers_31__ap[0]), + .ZN(n_1_0_665) + ); + SDFF_X1_LVT \registers_reg[29][0] ( + .CK(n_0_59), .D(registers[0]), .Q(registers_29__ap[0]), .QN(), .SE(dftIn), + .SI(registers_24__ap[0]) + ); + SDFF_X1_LVT \registers_reg[23][0] ( + .CK(n_0_53), .D(registers[0]), .Q(registers_23__ap[0]), .QN(), .SE(dftIn), + .SI(registers_17__ap[0]) + ); + AOI22_X1_LVT i_1_0_697( + .A1(registers_29__ap[0]), .A2(n_1_0_1276), .B1(n_1_0_1264), .B2(registers_23__ap[0]), + .ZN(n_1_0_664) + ); + NAND4_X1_LVT i_1_0_696( + .A1(n_1_0_667), .A2(n_1_0_666), .A3(n_1_0_665), .A4(n_1_0_664), .ZN(n_1_0_663) + ); + SDFF_X1_LVT \registers_reg[18][0] ( + .CK(n_0_48), .D(registers[0]), .Q(registers_18__ap[0]), .QN(), .SE(dftIn), + .SI(registers_23__ap[0]) + ); + SDFF_X1_LVT \registers_reg[30][0] ( + .CK(n_0_60), .D(registers[0]), .Q(registers_30__ap[0]), .QN(), .SE(dftIn), + .SI(registers_29__ap[0]) + ); + AOI22_X1_LVT i_1_0_695( + .A1(registers_18__ap[0]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[0]), + .ZN(n_1_0_662) + ); + SDFF_X1_LVT \registers_reg[4][0] ( + .CK(n_0_34), .D(registers[0]), .Q(registers_4__ap[0]), .QN(), .SE(dftIn), + .SI(registers_31__ap[0]) + ); + SDFF_X1_LVT \registers_reg[12][0] ( + .CK(n_0_42), .D(registers[0]), .Q(registers_12__ap[0]), .QN(), .SE(dftIn), + .SI(registers_10__ap[0]) + ); + AOI22_X1_LVT i_1_0_694( + .A1(registers_4__ap[0]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[0]), + .ZN(n_1_0_661) + ); + SDFF_X1_LVT \registers_reg[15][0] ( + .CK(n_0_45), .D(registers[0]), .Q(registers_15__ap[0]), .QN(), .SE(dftIn), + .SI(registers_12__ap[0]) + ); + SDFF_X1_LVT \registers_reg[16][0] ( + .CK(n_0_46), .D(registers[0]), .Q(registers_16__ap[0]), .QN(), .SE(dftIn), + .SI(registers_15__ap[0]) + ); + AOI22_X1_LVT i_1_0_693( + .A1(registers_15__ap[0]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[0]), + .ZN(n_1_0_660) + ); + SDFF_X1_LVT \registers_reg[22][0] ( + .CK(n_0_52), .D(registers[0]), .Q(registers_22__ap[0]), .QN(), .SE(dftIn), + .SI(registers_18__ap[0]) + ); + SDFF_X1_LVT \registers_reg[5][0] ( + .CK(n_0_35), .D(registers[0]), .Q(registers_5__ap[0]), .QN(), .SE(dftIn), + .SI(registers_4__ap[0]) + ); + AOI22_X1_LVT i_1_0_692( + .A1(registers_22__ap[0]), .A2(n_1_0_1294), .B1(n_1_0_1273), .B2(registers_5__ap[0]), + .ZN(n_1_0_659) + ); + NAND4_X1_LVT i_1_0_691( + .A1(n_1_0_662), .A2(n_1_0_661), .A3(n_1_0_660), .A4(n_1_0_659), .ZN(n_1_0_658) + ); + SDFF_X1_LVT \registers_reg[19][0] ( + .CK(n_0_49), .D(registers[0]), .Q(registers_19__ap[0]), .QN(), .SE(dftIn), + .SI(registers_22__ap[0]) + ); + SDFF_X1_LVT \registers_reg[2][0] ( + .CK(n_0_32), .D(registers[0]), .Q(registers_2__ap[0]), .QN(), .SE(dftIn), + .SI(registers_30__ap[0]) + ); + AOI22_X1_LVT i_1_0_690( + .A1(registers_19__ap[0]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[0]), + .ZN(n_1_0_657) + ); + SDFF_X1_LVT \registers_reg[9][0] ( + .CK(n_0_39), .D(registers[0]), .Q(registers_9__ap[0]), .QN(), .SE(dftIn), + .SI(registers_5__ap[0]) + ); + SDFF_X1_LVT \registers_reg[1][0] ( + .CK(n_0_0), .D(registers[0]), .Q(registers_1__ap[0]), .QN(), .SE(dftIn), + .SI(registers_19__ap[0]) + ); + AOI22_X1_LVT i_1_0_689( + .A1(registers_9__ap[0]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[0]), + .ZN(n_1_0_656) + ); + SDFF_X1_LVT \registers_reg[6][0] ( + .CK(n_0_36), .D(registers[0]), .Q(registers_6__ap[0]), .QN(), .SE(dftIn), + .SI(registers_9__ap[0]) + ); + SDFF_X1_LVT \registers_reg[14][0] ( + .CK(n_0_44), .D(registers[0]), .Q(registers_14__ap[0]), .QN(), .SE(dftIn), + .SI(registers_16__ap[0]) + ); + AOI22_X1_LVT i_1_0_688( + .A1(registers_6__ap[0]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[0]), + .ZN(n_1_0_655) + ); + SDFF_X1_LVT \registers_reg[27][0] ( + .CK(n_0_57), .D(registers[0]), .Q(registers_27__ap[0]), .QN(), .SE(dftIn), + .SI(registers_2__ap[0]) + ); + SDFF_X1_LVT \registers_reg[11][0] ( + .CK(n_0_41), .D(registers[0]), .Q(registers_11__ap[0]), .QN(), .SE(dftIn), + .SI(registers_14__ap[0]) + ); + AOI22_X1_LVT i_1_0_687( + .A1(registers_27__ap[0]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[0]), + .ZN(n_1_0_654) + ); + NAND4_X1_LVT i_1_0_686( + .A1(n_1_0_657), .A2(n_1_0_656), .A3(n_1_0_655), .A4(n_1_0_654), .ZN(n_1_0_653) + ); + NOR3_X1_LVT i_1_0_685( + .A1(n_1_0_663), .A2(n_1_0_658), .A3(n_1_0_653), .ZN(n_1_0_652) + ); + NAND4_X1_LVT i_1_0_684( + .A1(n_1_0_670), .A2(n_1_0_669), .A3(n_1_0_668), .A4(n_1_0_652), .ZN(RRs1[0]) + ); + INV_X1_LVT i_1_0_1366( + .A(Rs2[1]), .ZN(n_1_0_1302) + ); + NAND3_X1_LVT i_1_0_683( + .A1(n_1_0_1302), .A2(Rs2[4]), .A3(Rs2[2]), .ZN(n_1_0_651) + ); + INV_X1_LVT i_1_0_1369( + .A(Rs2[3]), .ZN(n_1_0_1305) + ); + OR2_X1_LVT i_1_0_673( + .A1(n_1_0_1305), .A2(Rs2[0]), .ZN(n_1_0_641) + ); + NOR2_X1_LVT i_1_0_666( + .A1(n_1_0_651), .A2(n_1_0_641), .ZN(n_1_0_634) + ); + NAND2_X1_LVT i_1_0_677( + .A1(n_1_0_1305), .A2(Rs2[0]), .ZN(n_1_0_645) + ); + INV_X1_LVT i_1_0_1368( + .A(Rs2[2]), .ZN(n_1_0_1304) + ); + NAND3_X1_LVT i_1_0_662( + .A1(n_1_0_1304), .A2(n_1_0_1302), .A3(Rs2[4]), .ZN(n_1_0_630) + ); + NOR2_X1_LVT i_1_0_661( + .A1(n_1_0_645), .A2(n_1_0_630), .ZN(n_1_0_629) + ); + AOI22_X1_LVT i_1_0_641( + .A1(registers_28__ap[31]), .A2(n_1_0_634), .B1(n_1_0_629), .B2(registers_17__ap[31]), + .ZN(n_1_0_609) + ); + NAND3_X1_LVT i_1_0_680( + .A1(n_1_0_1304), .A2(Rs2[4]), .A3(Rs2[1]), .ZN(n_1_0_648) + ); + NOR2_X1_LVT i_1_0_672( + .A1(n_1_0_648), .A2(n_1_0_641), .ZN(n_1_0_640) + ); + INV_X1_LVT i_1_0_1367( + .A(Rs2[4]), .ZN(n_1_0_1303) + ); + NAND3_X1_LVT i_1_0_657( + .A1(n_1_0_1304), .A2(n_1_0_1303), .A3(Rs2[1]), .ZN(n_1_0_625) + ); + NOR2_X1_LVT i_1_0_656( + .A1(n_1_0_641), .A2(n_1_0_625), .ZN(n_1_0_624) + ); + NOR4_X1_LVT i_1_0_658( + .A1(n_1_0_641), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), .ZN(n_1_0_626) + ); + AOI222_X1_LVT i_1_0_640( + .A1(registers_26__ap[31]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[31]), + .C1(n_1_0_626), .C2(registers_8__ap[31]), .ZN(n_1_0_608) + ); + NAND2_X1_LVT i_1_0_682( + .A1(Rs2[0]), .A2(Rs2[3]), .ZN(n_1_0_650) + ); + NOR2_X1_LVT i_1_0_681( + .A1(n_1_0_651), .A2(n_1_0_650), .ZN(n_1_0_649) + ); + NOR4_X1_LVT i_1_0_649( + .A1(n_1_0_650), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), .ZN(n_1_0_617) + ); + AOI22_X1_LVT i_1_0_639( + .A1(registers_29__ap[31]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[31]), + .ZN(n_1_0_607) + ); + NOR4_X1_LVT i_1_0_676( + .A1(n_1_0_645), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), .ZN(n_1_0_644) + ); + OR2_X1_LVT i_1_0_679( + .A1(Rs2[0]), .A2(Rs2[3]), .ZN(n_1_0_647) + ); + NAND3_X1_LVT i_1_0_660( + .A1(n_1_0_1303), .A2(Rs2[1]), .A3(Rs2[2]), .ZN(n_1_0_628) + ); + NOR2_X1_LVT i_1_0_648( + .A1(n_1_0_647), .A2(n_1_0_628), .ZN(n_1_0_616) + ); + AOI22_X1_LVT i_1_0_638( + .A1(registers_1__ap[31]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[31]), + .ZN(n_1_0_606) + ); + NOR2_X1_LVT i_1_0_655( + .A1(n_1_0_645), .A2(n_1_0_628), .ZN(n_1_0_623) + ); + NAND3_X1_LVT i_1_0_675( + .A1(Rs2[2]), .A2(Rs2[4]), .A3(Rs2[1]), .ZN(n_1_0_643) + ); + NOR2_X1_LVT i_1_0_647( + .A1(n_1_0_645), .A2(n_1_0_643), .ZN(n_1_0_615) + ); + AOI22_X1_LVT i_1_0_637( + .A1(registers_7__ap[31]), .A2(n_1_0_623), .B1(n_1_0_615), .B2(registers_23__ap[31]), + .ZN(n_1_0_605) + ); + NOR2_X1_LVT i_1_0_665( + .A1(n_1_0_648), .A2(n_1_0_645), .ZN(n_1_0_633) + ); + NOR2_X1_LVT i_1_0_646( + .A1(n_1_0_647), .A2(n_1_0_630), .ZN(n_1_0_614) + ); + AOI22_X1_LVT i_1_0_636( + .A1(registers_19__ap[31]), .A2(n_1_0_633), .B1(n_1_0_614), .B2(registers_16__ap[31]), + .ZN(n_1_0_604) + ); + NOR2_X1_LVT i_1_0_669( + .A1(n_1_0_650), .A2(n_1_0_643), .ZN(n_1_0_637) + ); + NAND3_X1_LVT i_1_0_671( + .A1(n_1_0_1303), .A2(n_1_0_1302), .A3(Rs2[2]), .ZN(n_1_0_639) + ); + NOR2_X1_LVT i_1_0_667( + .A1(n_1_0_645), .A2(n_1_0_639), .ZN(n_1_0_635) + ); + AOI22_X1_LVT i_1_0_635( + .A1(registers_31__ap[31]), .A2(n_1_0_637), .B1(n_1_0_635), .B2(registers_5__ap[31]), + .ZN(n_1_0_603) + ); + NAND4_X1_LVT i_1_0_634( + .A1(n_1_0_606), .A2(n_1_0_605), .A3(n_1_0_604), .A4(n_1_0_603), .ZN(n_1_0_602) + ); + NOR2_X1_LVT i_1_0_678( + .A1(n_1_0_648), .A2(n_1_0_647), .ZN(n_1_0_646) + ); + NOR2_X1_LVT i_1_0_654( + .A1(n_1_0_643), .A2(n_1_0_641), .ZN(n_1_0_622) + ); + AOI22_X1_LVT i_1_0_633( + .A1(registers_18__ap[31]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[31]), + .ZN(n_1_0_601) + ); + NOR2_X1_LVT i_1_0_670( + .A1(n_1_0_647), .A2(n_1_0_639), .ZN(n_1_0_638) + ); + NOR2_X1_LVT i_1_0_645( + .A1(n_1_0_651), .A2(n_1_0_647), .ZN(n_1_0_613) + ); + AOI22_X1_LVT i_1_0_632( + .A1(registers_4__ap[31]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[31]), + .ZN(n_1_0_600) + ); + NOR2_X1_LVT i_1_0_674( + .A1(n_1_0_647), .A2(n_1_0_643), .ZN(n_1_0_642) + ); + NOR2_X1_LVT i_1_0_644( + .A1(n_1_0_651), .A2(n_1_0_645), .ZN(n_1_0_612) + ); + AOI22_X1_LVT i_1_0_631( + .A1(registers_22__ap[31]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[31]), + .ZN(n_1_0_599) + ); + NOR2_X1_LVT i_1_0_664( + .A1(n_1_0_641), .A2(n_1_0_639), .ZN(n_1_0_632) + ); + NOR2_X1_LVT i_1_0_653( + .A1(n_1_0_641), .A2(n_1_0_630), .ZN(n_1_0_621) + ); + AOI22_X1_LVT i_1_0_630( + .A1(registers_12__ap[31]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[31]), + .ZN(n_1_0_598) + ); + NAND4_X1_LVT i_1_0_629( + .A1(n_1_0_601), .A2(n_1_0_600), .A3(n_1_0_599), .A4(n_1_0_598), .ZN(n_1_0_597) + ); + NOR2_X1_LVT i_1_0_663( + .A1(n_1_0_650), .A2(n_1_0_639), .ZN(n_1_0_631) + ); + NOR2_X1_LVT i_1_0_652( + .A1(n_1_0_650), .A2(n_1_0_630), .ZN(n_1_0_620) + ); + AOI22_X1_LVT i_1_0_628( + .A1(registers_13__ap[31]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[31]), + .ZN(n_1_0_596) + ); + NOR2_X1_LVT i_1_0_659( + .A1(n_1_0_650), .A2(n_1_0_628), .ZN(n_1_0_627) + ); + NOR2_X1_LVT i_1_0_651( + .A1(n_1_0_641), .A2(n_1_0_628), .ZN(n_1_0_619) + ); + AOI22_X1_LVT i_1_0_627( + .A1(registers_15__ap[31]), .A2(n_1_0_627), .B1(n_1_0_619), .B2(registers_14__ap[31]), + .ZN(n_1_0_595) + ); + NOR2_X1_LVT i_1_0_668( + .A1(n_1_0_650), .A2(n_1_0_648), .ZN(n_1_0_636) + ); + NOR2_X1_LVT i_1_0_643( + .A1(n_1_0_650), .A2(n_1_0_625), .ZN(n_1_0_611) + ); + AOI22_X1_LVT i_1_0_626( + .A1(registers_27__ap[31]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[31]), + .ZN(n_1_0_594) + ); + NOR2_X1_LVT i_1_0_650( + .A1(n_1_0_647), .A2(n_1_0_625), .ZN(n_1_0_618) + ); + NOR2_X1_LVT i_1_0_642( + .A1(n_1_0_645), .A2(n_1_0_625), .ZN(n_1_0_610) + ); + AOI22_X1_LVT i_1_0_625( + .A1(registers_2__ap[31]), .A2(n_1_0_618), .B1(n_1_0_610), .B2(registers_3__ap[31]), + .ZN(n_1_0_593) + ); + NAND4_X1_LVT i_1_0_624( + .A1(n_1_0_596), .A2(n_1_0_595), .A3(n_1_0_594), .A4(n_1_0_593), .ZN(n_1_0_592) + ); + NOR3_X1_LVT i_1_0_623( + .A1(n_1_0_602), .A2(n_1_0_597), .A3(n_1_0_592), .ZN(n_1_0_591) + ); + NAND4_X1_LVT i_1_0_622( + .A1(n_1_0_609), .A2(n_1_0_608), .A3(n_1_0_607), .A4(n_1_0_591), .ZN(RRs2[31]) + ); + AOI22_X1_LVT i_1_0_620( + .A1(registers_29__ap[30]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[30]), + .ZN(n_1_0_589) + ); + AOI22_X1_LVT i_1_0_621( + .A1(registers_7__ap[30]), .A2(n_1_0_623), .B1(n_1_0_615), .B2(registers_23__ap[30]), + .ZN(n_1_0_590) + ); + AOI22_X1_LVT i_1_0_619( + .A1(registers_1__ap[30]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[30]), + .ZN(n_1_0_588) + ); + AOI22_X1_LVT i_1_0_618( + .A1(registers_5__ap[30]), .A2(n_1_0_635), .B1(n_1_0_633), .B2(registers_19__ap[30]), + .ZN(n_1_0_587) + ); + NAND3_X1_LVT i_1_0_617( + .A1(n_1_0_590), .A2(n_1_0_588), .A3(n_1_0_587), .ZN(n_1_0_586) + ); + AOI221_X1_LVT i_1_0_616( + .A(n_1_0_586), .B1(n_1_0_637), .B2(registers_31__ap[30]), .C1(registers_16__ap[30]), + .C2(n_1_0_614), .ZN(n_1_0_585) + ); + AOI222_X1_LVT i_1_0_615( + .A1(registers_26__ap[30]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[30]), + .C1(n_1_0_626), .C2(registers_8__ap[30]), .ZN(n_1_0_584) + ); + NAND3_X1_LVT i_1_0_614( + .A1(n_1_0_589), .A2(n_1_0_585), .A3(n_1_0_584), .ZN(n_1_0_583) + ); + AOI221_X1_LVT i_1_0_613( + .A(n_1_0_583), .B1(n_1_0_629), .B2(registers_17__ap[30]), .C1(registers_28__ap[30]), + .C2(n_1_0_634), .ZN(n_1_0_582) + ); + AOI22_X1_LVT i_1_0_612( + .A1(registers_18__ap[30]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[30]), + .ZN(n_1_0_581) + ); + AOI22_X1_LVT i_1_0_611( + .A1(registers_4__ap[30]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[30]), + .ZN(n_1_0_580) + ); + AOI22_X1_LVT i_1_0_610( + .A1(registers_22__ap[30]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[30]), + .ZN(n_1_0_579) + ); + NAND3_X1_LVT i_1_0_609( + .A1(n_1_0_581), .A2(n_1_0_580), .A3(n_1_0_579), .ZN(n_1_0_578) + ); + AOI221_X1_LVT i_1_0_608( + .A(n_1_0_578), .B1(n_1_0_621), .B2(registers_24__ap[30]), .C1(registers_12__ap[30]), + .C2(n_1_0_632), .ZN(n_1_0_577) + ); + AOI22_X1_LVT i_1_0_607( + .A1(registers_13__ap[30]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[30]), + .ZN(n_1_0_576) + ); + AOI22_X1_LVT i_1_0_606( + .A1(registers_15__ap[30]), .A2(n_1_0_627), .B1(n_1_0_619), .B2(registers_14__ap[30]), + .ZN(n_1_0_575) + ); + AOI22_X1_LVT i_1_0_605( + .A1(registers_27__ap[30]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[30]), + .ZN(n_1_0_574) + ); + NAND3_X1_LVT i_1_0_604( + .A1(n_1_0_576), .A2(n_1_0_575), .A3(n_1_0_574), .ZN(n_1_0_573) + ); + AOI221_X1_LVT i_1_0_603( + .A(n_1_0_573), .B1(n_1_0_610), .B2(registers_3__ap[30]), .C1(registers_2__ap[30]), + .C2(n_1_0_618), .ZN(n_1_0_572) + ); + NAND3_X1_LVT i_1_0_602( + .A1(n_1_0_582), .A2(n_1_0_577), .A3(n_1_0_572), .ZN(RRs2[30]) + ); + AOI22_X1_LVT i_1_0_600( + .A1(registers_28__ap[29]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[29]), + .ZN(n_1_0_570) + ); + AOI22_X1_LVT i_1_0_601( + .A1(registers_31__ap[29]), .A2(n_1_0_637), .B1(n_1_0_627), .B2(registers_15__ap[29]), + .ZN(n_1_0_571) + ); + AOI22_X1_LVT i_1_0_599( + .A1(registers_24__ap[29]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[29]), + .ZN(n_1_0_569) + ); + AOI22_X1_LVT i_1_0_598( + .A1(registers_19__ap[29]), .A2(n_1_0_633), .B1(n_1_0_629), .B2(registers_17__ap[29]), + .ZN(n_1_0_568) + ); + NAND3_X1_LVT i_1_0_597( + .A1(n_1_0_571), .A2(n_1_0_569), .A3(n_1_0_568), .ZN(n_1_0_567) + ); + AOI221_X1_LVT i_1_0_596( + .A(n_1_0_567), .B1(n_1_0_615), .B2(registers_23__ap[29]), .C1(registers_29__ap[29]), + .C2(n_1_0_649), .ZN(n_1_0_566) + ); + AOI222_X1_LVT i_1_0_595( + .A1(registers_26__ap[29]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[29]), + .C1(n_1_0_620), .C2(registers_25__ap[29]), .ZN(n_1_0_565) + ); + NAND3_X1_LVT i_1_0_594( + .A1(n_1_0_570), .A2(n_1_0_566), .A3(n_1_0_565), .ZN(n_1_0_564) + ); + AOI221_X1_LVT i_1_0_593( + .A(n_1_0_564), .B1(n_1_0_612), .B2(registers_21__ap[29]), .C1(registers_13__ap[29]), + .C2(n_1_0_631), .ZN(n_1_0_563) + ); + AOI22_X1_LVT i_1_0_592( + .A1(registers_18__ap[29]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[29]), + .ZN(n_1_0_562) + ); + AOI22_X1_LVT i_1_0_591( + .A1(registers_4__ap[29]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[29]), + .ZN(n_1_0_561) + ); + AOI22_X1_LVT i_1_0_590( + .A1(registers_7__ap[29]), .A2(n_1_0_623), .B1(n_1_0_614), .B2(registers_16__ap[29]), + .ZN(n_1_0_560) + ); + NAND3_X1_LVT i_1_0_589( + .A1(n_1_0_562), .A2(n_1_0_561), .A3(n_1_0_560), .ZN(n_1_0_559) + ); + AOI221_X1_LVT i_1_0_588( + .A(n_1_0_559), .B1(n_1_0_642), .B2(registers_22__ap[29]), .C1(registers_5__ap[29]), + .C2(n_1_0_635), .ZN(n_1_0_558) + ); + AOI22_X1_LVT i_1_0_587( + .A1(registers_1__ap[29]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[29]), + .ZN(n_1_0_557) + ); + AOI22_X1_LVT i_1_0_586( + .A1(registers_14__ap[29]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[29]), + .ZN(n_1_0_556) + ); + AOI22_X1_LVT i_1_0_585( + .A1(registers_27__ap[29]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[29]), + .ZN(n_1_0_555) + ); + NAND3_X1_LVT i_1_0_584( + .A1(n_1_0_557), .A2(n_1_0_556), .A3(n_1_0_555), .ZN(n_1_0_554) + ); + AOI221_X1_LVT i_1_0_583( + .A(n_1_0_554), .B1(n_1_0_610), .B2(registers_3__ap[29]), .C1(registers_2__ap[29]), + .C2(n_1_0_618), .ZN(n_1_0_553) + ); + NAND3_X1_LVT i_1_0_582( + .A1(n_1_0_563), .A2(n_1_0_558), .A3(n_1_0_553), .ZN(RRs2[29]) + ); + AOI22_X1_LVT i_1_0_581( + .A1(registers_5__ap[28]), .A2(n_1_0_635), .B1(n_1_0_634), .B2(registers_28__ap[28]), + .ZN(n_1_0_552) + ); + AOI222_X1_LVT i_1_0_580( + .A1(registers_26__ap[28]), .A2(n_1_0_640), .B1(n_1_0_633), .B2(registers_19__ap[28]), + .C1(n_1_0_626), .C2(registers_8__ap[28]), .ZN(n_1_0_551) + ); + AOI22_X1_LVT i_1_0_579( + .A1(registers_2__ap[28]), .A2(n_1_0_618), .B1(n_1_0_617), .B2(registers_9__ap[28]), + .ZN(n_1_0_550) + ); + AOI22_X1_LVT i_1_0_578( + .A1(registers_7__ap[28]), .A2(n_1_0_623), .B1(n_1_0_612), .B2(registers_21__ap[28]), + .ZN(n_1_0_549) + ); + AOI22_X1_LVT i_1_0_577( + .A1(registers_16__ap[28]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[28]), + .ZN(n_1_0_548) + ); + AOI22_X1_LVT i_1_0_576( + .A1(registers_31__ap[28]), .A2(n_1_0_637), .B1(n_1_0_619), .B2(registers_14__ap[28]), + .ZN(n_1_0_547) + ); + AOI22_X1_LVT i_1_0_575( + .A1(registers_15__ap[28]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[28]), + .ZN(n_1_0_546) + ); + NAND4_X1_LVT i_1_0_574( + .A1(n_1_0_549), .A2(n_1_0_548), .A3(n_1_0_547), .A4(n_1_0_546), .ZN(n_1_0_545) + ); + AOI22_X1_LVT i_1_0_573( + .A1(registers_22__ap[28]), .A2(n_1_0_642), .B1(n_1_0_622), .B2(registers_30__ap[28]), + .ZN(n_1_0_544) + ); + AOI22_X1_LVT i_1_0_572( + .A1(registers_4__ap[28]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[28]), + .ZN(n_1_0_543) + ); + AOI22_X1_LVT i_1_0_571( + .A1(registers_29__ap[28]), .A2(n_1_0_649), .B1(n_1_0_644), .B2(registers_1__ap[28]), + .ZN(n_1_0_542) + ); + AOI22_X1_LVT i_1_0_570( + .A1(registers_12__ap[28]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[28]), + .ZN(n_1_0_541) + ); + NAND4_X1_LVT i_1_0_569( + .A1(n_1_0_544), .A2(n_1_0_543), .A3(n_1_0_542), .A4(n_1_0_541), .ZN(n_1_0_540) + ); + AOI22_X1_LVT i_1_0_568( + .A1(registers_13__ap[28]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[28]), + .ZN(n_1_0_539) + ); + AOI22_X1_LVT i_1_0_567( + .A1(registers_17__ap[28]), .A2(n_1_0_629), .B1(n_1_0_616), .B2(registers_6__ap[28]), + .ZN(n_1_0_538) + ); + AOI22_X1_LVT i_1_0_566( + .A1(registers_10__ap[28]), .A2(n_1_0_624), .B1(n_1_0_615), .B2(registers_23__ap[28]), + .ZN(n_1_0_537) + ); + AOI22_X1_LVT i_1_0_565( + .A1(registers_18__ap[28]), .A2(n_1_0_646), .B1(n_1_0_636), .B2(registers_27__ap[28]), + .ZN(n_1_0_536) + ); + NAND4_X1_LVT i_1_0_564( + .A1(n_1_0_539), .A2(n_1_0_538), .A3(n_1_0_537), .A4(n_1_0_536), .ZN(n_1_0_535) + ); + NOR3_X1_LVT i_1_0_563( + .A1(n_1_0_545), .A2(n_1_0_540), .A3(n_1_0_535), .ZN(n_1_0_534) + ); + NAND4_X1_LVT i_1_0_562( + .A1(n_1_0_552), .A2(n_1_0_551), .A3(n_1_0_550), .A4(n_1_0_534), .ZN(RRs2[28]) + ); + AOI22_X1_LVT i_1_0_561( + .A1(registers_17__ap[27]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[27]), + .ZN(n_1_0_533) + ); + AOI222_X1_LVT i_1_0_560( + .A1(registers_19__ap[27]), .A2(n_1_0_633), .B1(n_1_0_631), .B2(registers_13__ap[27]), + .C1(registers_30__ap[27]), .C2(n_1_0_622), .ZN(n_1_0_532) + ); + AOI22_X1_LVT i_1_0_559( + .A1(registers_1__ap[27]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[27]), + .ZN(n_1_0_531) + ); + AOI22_X1_LVT i_1_0_558( + .A1(registers_24__ap[27]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[27]), + .ZN(n_1_0_530) + ); + AOI22_X1_LVT i_1_0_557( + .A1(registers_15__ap[27]), .A2(n_1_0_627), .B1(n_1_0_611), .B2(registers_11__ap[27]), + .ZN(n_1_0_529) + ); + AOI22_X1_LVT i_1_0_556( + .A1(registers_4__ap[27]), .A2(n_1_0_638), .B1(n_1_0_636), .B2(registers_27__ap[27]), + .ZN(n_1_0_528) + ); + AOI22_X1_LVT i_1_0_555( + .A1(registers_31__ap[27]), .A2(n_1_0_637), .B1(n_1_0_618), .B2(registers_2__ap[27]), + .ZN(n_1_0_527) + ); + NAND4_X1_LVT i_1_0_554( + .A1(n_1_0_530), .A2(n_1_0_529), .A3(n_1_0_528), .A4(n_1_0_527), .ZN(n_1_0_526) + ); + AOI22_X1_LVT i_1_0_553( + .A1(registers_18__ap[27]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[27]), + .ZN(n_1_0_525) + ); + AOI22_X1_LVT i_1_0_552( + .A1(registers_5__ap[27]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[27]), + .ZN(n_1_0_524) + ); + AOI22_X1_LVT i_1_0_551( + .A1(registers_6__ap[27]), .A2(n_1_0_616), .B1(n_1_0_614), .B2(registers_16__ap[27]), + .ZN(n_1_0_523) + ); + AOI22_X1_LVT i_1_0_550( + .A1(registers_22__ap[27]), .A2(n_1_0_642), .B1(n_1_0_620), .B2(registers_25__ap[27]), + .ZN(n_1_0_522) + ); + NAND4_X1_LVT i_1_0_549( + .A1(n_1_0_525), .A2(n_1_0_524), .A3(n_1_0_523), .A4(n_1_0_522), .ZN(n_1_0_521) + ); + AOI22_X1_LVT i_1_0_548( + .A1(registers_29__ap[27]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[27]), + .ZN(n_1_0_520) + ); + AOI22_X1_LVT i_1_0_547( + .A1(registers_7__ap[27]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[27]), + .ZN(n_1_0_519) + ); + AOI22_X1_LVT i_1_0_546( + .A1(registers_8__ap[27]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[27]), + .ZN(n_1_0_518) + ); + AOI22_X1_LVT i_1_0_545( + .A1(registers_10__ap[27]), .A2(n_1_0_624), .B1(n_1_0_610), .B2(registers_3__ap[27]), + .ZN(n_1_0_517) + ); + NAND4_X1_LVT i_1_0_544( + .A1(n_1_0_520), .A2(n_1_0_519), .A3(n_1_0_518), .A4(n_1_0_517), .ZN(n_1_0_516) + ); + NOR3_X1_LVT i_1_0_543( + .A1(n_1_0_526), .A2(n_1_0_521), .A3(n_1_0_516), .ZN(n_1_0_515) + ); + NAND4_X1_LVT i_1_0_542( + .A1(n_1_0_533), .A2(n_1_0_532), .A3(n_1_0_531), .A4(n_1_0_515), .ZN(RRs2[27]) + ); + AOI22_X1_LVT i_1_0_541( + .A1(registers_17__ap[26]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[26]), + .ZN(n_1_0_514) + ); + AOI222_X1_LVT i_1_0_540( + .A1(registers_19__ap[26]), .A2(n_1_0_633), .B1(n_1_0_622), .B2(registers_30__ap[26]), + .C1(n_1_0_631), .C2(registers_13__ap[26]), .ZN(n_1_0_513) + ); + AOI22_X1_LVT i_1_0_539( + .A1(registers_1__ap[26]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[26]), + .ZN(n_1_0_512) + ); + AOI22_X1_LVT i_1_0_538( + .A1(registers_24__ap[26]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[26]), + .ZN(n_1_0_511) + ); + AOI22_X1_LVT i_1_0_537( + .A1(registers_15__ap[26]), .A2(n_1_0_627), .B1(n_1_0_611), .B2(registers_11__ap[26]), + .ZN(n_1_0_510) + ); + AOI22_X1_LVT i_1_0_536( + .A1(registers_4__ap[26]), .A2(n_1_0_638), .B1(n_1_0_636), .B2(registers_27__ap[26]), + .ZN(n_1_0_509) + ); + AOI22_X1_LVT i_1_0_535( + .A1(registers_31__ap[26]), .A2(n_1_0_637), .B1(n_1_0_618), .B2(registers_2__ap[26]), + .ZN(n_1_0_508) + ); + NAND4_X1_LVT i_1_0_534( + .A1(n_1_0_511), .A2(n_1_0_510), .A3(n_1_0_509), .A4(n_1_0_508), .ZN(n_1_0_507) + ); + AOI22_X1_LVT i_1_0_533( + .A1(registers_18__ap[26]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[26]), + .ZN(n_1_0_506) + ); + AOI22_X1_LVT i_1_0_532( + .A1(registers_5__ap[26]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[26]), + .ZN(n_1_0_505) + ); + AOI22_X1_LVT i_1_0_531( + .A1(registers_6__ap[26]), .A2(n_1_0_616), .B1(n_1_0_614), .B2(registers_16__ap[26]), + .ZN(n_1_0_504) + ); + AOI22_X1_LVT i_1_0_530( + .A1(registers_22__ap[26]), .A2(n_1_0_642), .B1(n_1_0_620), .B2(registers_25__ap[26]), + .ZN(n_1_0_503) + ); + NAND4_X1_LVT i_1_0_529( + .A1(n_1_0_506), .A2(n_1_0_505), .A3(n_1_0_504), .A4(n_1_0_503), .ZN(n_1_0_502) + ); + AOI22_X1_LVT i_1_0_528( + .A1(registers_29__ap[26]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[26]), + .ZN(n_1_0_501) + ); + AOI22_X1_LVT i_1_0_527( + .A1(registers_7__ap[26]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[26]), + .ZN(n_1_0_500) + ); + AOI22_X1_LVT i_1_0_526( + .A1(registers_8__ap[26]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[26]), + .ZN(n_1_0_499) + ); + AOI22_X1_LVT i_1_0_525( + .A1(registers_10__ap[26]), .A2(n_1_0_624), .B1(n_1_0_610), .B2(registers_3__ap[26]), + .ZN(n_1_0_498) + ); + NAND4_X1_LVT i_1_0_524( + .A1(n_1_0_501), .A2(n_1_0_500), .A3(n_1_0_499), .A4(n_1_0_498), .ZN(n_1_0_497) + ); + NOR3_X1_LVT i_1_0_523( + .A1(n_1_0_507), .A2(n_1_0_502), .A3(n_1_0_497), .ZN(n_1_0_496) + ); + NAND4_X1_LVT i_1_0_522( + .A1(n_1_0_514), .A2(n_1_0_513), .A3(n_1_0_512), .A4(n_1_0_496), .ZN(RRs2[26]) + ); + AOI22_X1_LVT i_1_0_520( + .A1(registers_5__ap[25]), .A2(n_1_0_635), .B1(n_1_0_634), .B2(registers_28__ap[25]), + .ZN(n_1_0_494) + ); + AOI22_X1_LVT i_1_0_521( + .A1(registers_8__ap[25]), .A2(n_1_0_626), .B1(n_1_0_620), .B2(registers_25__ap[25]), + .ZN(n_1_0_495) + ); + AOI22_X1_LVT i_1_0_519( + .A1(registers_14__ap[25]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[25]), + .ZN(n_1_0_493) + ); + AOI22_X1_LVT i_1_0_518( + .A1(registers_16__ap[25]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[25]), + .ZN(n_1_0_492) + ); + NAND3_X1_LVT i_1_0_517( + .A1(n_1_0_495), .A2(n_1_0_493), .A3(n_1_0_492), .ZN(n_1_0_491) + ); + AOI221_X1_LVT i_1_0_516( + .A(n_1_0_491), .B1(n_1_0_624), .B2(registers_10__ap[25]), .C1(registers_6__ap[25]), + .C2(n_1_0_616), .ZN(n_1_0_490) + ); + AOI222_X1_LVT i_1_0_515( + .A1(registers_1__ap[25]), .A2(n_1_0_644), .B1(n_1_0_640), .B2(registers_26__ap[25]), + .C1(n_1_0_622), .C2(registers_30__ap[25]), .ZN(n_1_0_489) + ); + NAND2_X1_LVT i_1_0_514( + .A1(n_1_0_490), .A2(n_1_0_489), .ZN(n_1_0_488) + ); + AOI221_X1_LVT i_1_0_513( + .A(n_1_0_488), .B1(n_1_0_649), .B2(registers_29__ap[25]), .C1(registers_2__ap[25]), + .C2(n_1_0_618), .ZN(n_1_0_487) + ); + AOI22_X1_LVT i_1_0_512( + .A1(registers_12__ap[25]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[25]), + .ZN(n_1_0_486) + ); + AOI22_X1_LVT i_1_0_511( + .A1(registers_22__ap[25]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[25]), + .ZN(n_1_0_485) + ); + AOI22_X1_LVT i_1_0_510( + .A1(registers_4__ap[25]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[25]), + .ZN(n_1_0_484) + ); + NAND3_X1_LVT i_1_0_509( + .A1(n_1_0_486), .A2(n_1_0_485), .A3(n_1_0_484), .ZN(n_1_0_483) + ); + AOI221_X1_LVT i_1_0_508( + .A(n_1_0_483), .B1(n_1_0_633), .B2(registers_19__ap[25]), .C1(registers_18__ap[25]), + .C2(n_1_0_646), .ZN(n_1_0_482) + ); + AOI22_X1_LVT i_1_0_507( + .A1(registers_15__ap[25]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[25]), + .ZN(n_1_0_481) + ); + AOI22_X1_LVT i_1_0_506( + .A1(registers_23__ap[25]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[25]), + .ZN(n_1_0_480) + ); + AOI22_X1_LVT i_1_0_505( + .A1(registers_13__ap[25]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[25]), + .ZN(n_1_0_479) + ); + NAND3_X1_LVT i_1_0_504( + .A1(n_1_0_481), .A2(n_1_0_480), .A3(n_1_0_479), .ZN(n_1_0_478) + ); + AOI221_X1_LVT i_1_0_503( + .A(n_1_0_478), .B1(n_1_0_636), .B2(registers_27__ap[25]), .C1(registers_31__ap[25]), + .C2(n_1_0_637), .ZN(n_1_0_477) + ); + NAND4_X1_LVT i_1_0_502( + .A1(n_1_0_494), .A2(n_1_0_487), .A3(n_1_0_482), .A4(n_1_0_477), .ZN(RRs2[25]) + ); + AOI22_X1_LVT i_1_0_501( + .A1(registers_17__ap[24]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[24]), + .ZN(n_1_0_476) + ); + AOI222_X1_LVT i_1_0_500( + .A1(registers_13__ap[24]), .A2(n_1_0_631), .B1(n_1_0_622), .B2(registers_30__ap[24]), + .C1(registers_26__ap[24]), .C2(n_1_0_640), .ZN(n_1_0_475) + ); + AOI22_X1_LVT i_1_0_499( + .A1(registers_1__ap[24]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[24]), + .ZN(n_1_0_474) + ); + AOI22_X1_LVT i_1_0_498( + .A1(registers_24__ap[24]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[24]), + .ZN(n_1_0_473) + ); + AOI22_X1_LVT i_1_0_497( + .A1(registers_8__ap[24]), .A2(n_1_0_626), .B1(n_1_0_616), .B2(registers_6__ap[24]), + .ZN(n_1_0_472) + ); + AOI22_X1_LVT i_1_0_496( + .A1(registers_4__ap[24]), .A2(n_1_0_638), .B1(n_1_0_611), .B2(registers_11__ap[24]), + .ZN(n_1_0_471) + ); + AOI22_X1_LVT i_1_0_495( + .A1(registers_10__ap[24]), .A2(n_1_0_624), .B1(n_1_0_618), .B2(registers_2__ap[24]), + .ZN(n_1_0_470) + ); + NAND4_X1_LVT i_1_0_494( + .A1(n_1_0_473), .A2(n_1_0_472), .A3(n_1_0_471), .A4(n_1_0_470), .ZN(n_1_0_469) + ); + AOI22_X1_LVT i_1_0_493( + .A1(registers_18__ap[24]), .A2(n_1_0_646), .B1(n_1_0_633), .B2(registers_19__ap[24]), + .ZN(n_1_0_468) + ); + AOI22_X1_LVT i_1_0_492( + .A1(registers_5__ap[24]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[24]), + .ZN(n_1_0_467) + ); + AOI22_X1_LVT i_1_0_491( + .A1(registers_15__ap[24]), .A2(n_1_0_627), .B1(n_1_0_614), .B2(registers_16__ap[24]), + .ZN(n_1_0_466) + ); + AOI22_X1_LVT i_1_0_490( + .A1(registers_22__ap[24]), .A2(n_1_0_642), .B1(n_1_0_620), .B2(registers_25__ap[24]), + .ZN(n_1_0_465) + ); + NAND4_X1_LVT i_1_0_489( + .A1(n_1_0_468), .A2(n_1_0_467), .A3(n_1_0_466), .A4(n_1_0_465), .ZN(n_1_0_464) + ); + AOI22_X1_LVT i_1_0_488( + .A1(registers_29__ap[24]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[24]), + .ZN(n_1_0_463) + ); + AOI22_X1_LVT i_1_0_487( + .A1(registers_7__ap[24]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[24]), + .ZN(n_1_0_462) + ); + AOI22_X1_LVT i_1_0_486( + .A1(registers_23__ap[24]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[24]), + .ZN(n_1_0_461) + ); + AOI22_X1_LVT i_1_0_485( + .A1(registers_31__ap[24]), .A2(n_1_0_637), .B1(n_1_0_636), .B2(registers_27__ap[24]), + .ZN(n_1_0_460) + ); + NAND4_X1_LVT i_1_0_484( + .A1(n_1_0_463), .A2(n_1_0_462), .A3(n_1_0_461), .A4(n_1_0_460), .ZN(n_1_0_459) + ); + NOR3_X1_LVT i_1_0_483( + .A1(n_1_0_469), .A2(n_1_0_464), .A3(n_1_0_459), .ZN(n_1_0_458) + ); + NAND4_X1_LVT i_1_0_482( + .A1(n_1_0_476), .A2(n_1_0_475), .A3(n_1_0_474), .A4(n_1_0_458), .ZN(RRs2[24]) + ); + AOI22_X1_LVT i_1_0_481( + .A1(registers_4__ap[23]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[23]), + .ZN(n_1_0_457) + ); + AOI222_X1_LVT i_1_0_480( + .A1(registers_18__ap[23]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[23]), + .C1(n_1_0_644), .C2(registers_1__ap[23]), .ZN(n_1_0_456) + ); + AOI22_X1_LVT i_1_0_479( + .A1(registers_29__ap[23]), .A2(n_1_0_649), .B1(n_1_0_618), .B2(registers_2__ap[23]), + .ZN(n_1_0_455) + ); + AOI22_X1_LVT i_1_0_478( + .A1(registers_14__ap[23]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[23]), + .ZN(n_1_0_454) + ); + AOI22_X1_LVT i_1_0_477( + .A1(registers_16__ap[23]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[23]), + .ZN(n_1_0_453) + ); + AOI22_X1_LVT i_1_0_476( + .A1(registers_27__ap[23]), .A2(n_1_0_636), .B1(n_1_0_620), .B2(registers_25__ap[23]), + .ZN(n_1_0_452) + ); + AOI22_X1_LVT i_1_0_475( + .A1(registers_31__ap[23]), .A2(n_1_0_637), .B1(n_1_0_616), .B2(registers_6__ap[23]), + .ZN(n_1_0_451) + ); + NAND4_X1_LVT i_1_0_474( + .A1(n_1_0_454), .A2(n_1_0_453), .A3(n_1_0_452), .A4(n_1_0_451), .ZN(n_1_0_450) + ); + AOI22_X1_LVT i_1_0_473( + .A1(registers_26__ap[23]), .A2(n_1_0_640), .B1(n_1_0_633), .B2(registers_19__ap[23]), + .ZN(n_1_0_449) + ); + AOI22_X1_LVT i_1_0_472( + .A1(registers_12__ap[23]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[23]), + .ZN(n_1_0_448) + ); + AOI22_X1_LVT i_1_0_471( + .A1(registers_22__ap[23]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[23]), + .ZN(n_1_0_447) + ); + AOI22_X1_LVT i_1_0_470( + .A1(registers_5__ap[23]), .A2(n_1_0_635), .B1(n_1_0_613), .B2(registers_20__ap[23]), + .ZN(n_1_0_446) + ); + NAND4_X1_LVT i_1_0_469( + .A1(n_1_0_449), .A2(n_1_0_448), .A3(n_1_0_447), .A4(n_1_0_446), .ZN(n_1_0_445) + ); + AOI22_X1_LVT i_1_0_468( + .A1(registers_15__ap[23]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[23]), + .ZN(n_1_0_444) + ); + AOI22_X1_LVT i_1_0_467( + .A1(registers_8__ap[23]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[23]), + .ZN(n_1_0_443) + ); + AOI22_X1_LVT i_1_0_466( + .A1(registers_13__ap[23]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[23]), + .ZN(n_1_0_442) + ); + AOI22_X1_LVT i_1_0_465( + .A1(registers_10__ap[23]), .A2(n_1_0_624), .B1(n_1_0_610), .B2(registers_3__ap[23]), + .ZN(n_1_0_441) + ); + NAND4_X1_LVT i_1_0_464( + .A1(n_1_0_444), .A2(n_1_0_443), .A3(n_1_0_442), .A4(n_1_0_441), .ZN(n_1_0_440) + ); + NOR3_X1_LVT i_1_0_463( + .A1(n_1_0_450), .A2(n_1_0_445), .A3(n_1_0_440), .ZN(n_1_0_439) + ); + NAND4_X1_LVT i_1_0_462( + .A1(n_1_0_457), .A2(n_1_0_456), .A3(n_1_0_455), .A4(n_1_0_439), .ZN(RRs2[23]) + ); + AOI22_X1_LVT i_1_0_460( + .A1(registers_17__ap[22]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[22]), + .ZN(n_1_0_437) + ); + AOI22_X1_LVT i_1_0_461( + .A1(registers_15__ap[22]), .A2(n_1_0_627), .B1(n_1_0_626), .B2(registers_8__ap[22]), + .ZN(n_1_0_438) + ); + AOI22_X1_LVT i_1_0_459( + .A1(registers_24__ap[22]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[22]), + .ZN(n_1_0_436) + ); + AOI22_X1_LVT i_1_0_458( + .A1(registers_5__ap[22]), .A2(n_1_0_635), .B1(n_1_0_611), .B2(registers_11__ap[22]), + .ZN(n_1_0_435) + ); + NAND3_X1_LVT i_1_0_457( + .A1(n_1_0_438), .A2(n_1_0_436), .A3(n_1_0_435), .ZN(n_1_0_434) + ); + AOI221_X1_LVT i_1_0_456( + .A(n_1_0_434), .B1(n_1_0_618), .B2(registers_2__ap[22]), .C1(registers_10__ap[22]), + .C2(n_1_0_624), .ZN(n_1_0_433) + ); + AOI222_X1_LVT i_1_0_455( + .A1(registers_26__ap[22]), .A2(n_1_0_640), .B1(n_1_0_622), .B2(registers_30__ap[22]), + .C1(n_1_0_631), .C2(registers_13__ap[22]), .ZN(n_1_0_432) + ); + NAND2_X1_LVT i_1_0_454( + .A1(n_1_0_433), .A2(n_1_0_432), .ZN(n_1_0_431) + ); + AOI221_X1_LVT i_1_0_453( + .A(n_1_0_431), .B1(n_1_0_644), .B2(registers_1__ap[22]), .C1(registers_28__ap[22]), + .C2(n_1_0_634), .ZN(n_1_0_430) + ); + AOI22_X1_LVT i_1_0_452( + .A1(registers_18__ap[22]), .A2(n_1_0_646), .B1(n_1_0_633), .B2(registers_19__ap[22]), + .ZN(n_1_0_429) + ); + AOI22_X1_LVT i_1_0_451( + .A1(registers_4__ap[22]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[22]), + .ZN(n_1_0_428) + ); + AOI22_X1_LVT i_1_0_450( + .A1(registers_6__ap[22]), .A2(n_1_0_616), .B1(n_1_0_614), .B2(registers_16__ap[22]), + .ZN(n_1_0_427) + ); + NAND3_X1_LVT i_1_0_449( + .A1(n_1_0_429), .A2(n_1_0_428), .A3(n_1_0_427), .ZN(n_1_0_426) + ); + AOI221_X1_LVT i_1_0_448( + .A(n_1_0_426), .B1(n_1_0_620), .B2(registers_25__ap[22]), .C1(registers_22__ap[22]), + .C2(n_1_0_642), .ZN(n_1_0_425) + ); + AOI22_X1_LVT i_1_0_447( + .A1(registers_29__ap[22]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[22]), + .ZN(n_1_0_424) + ); + AOI22_X1_LVT i_1_0_446( + .A1(registers_7__ap[22]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[22]), + .ZN(n_1_0_423) + ); + AOI22_X1_LVT i_1_0_445( + .A1(registers_23__ap[22]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[22]), + .ZN(n_1_0_422) + ); + NAND3_X1_LVT i_1_0_444( + .A1(n_1_0_424), .A2(n_1_0_423), .A3(n_1_0_422), .ZN(n_1_0_421) + ); + AOI221_X1_LVT i_1_0_443( + .A(n_1_0_421), .B1(n_1_0_636), .B2(registers_27__ap[22]), .C1(registers_31__ap[22]), + .C2(n_1_0_637), .ZN(n_1_0_420) + ); + NAND4_X1_LVT i_1_0_442( + .A1(n_1_0_437), .A2(n_1_0_430), .A3(n_1_0_425), .A4(n_1_0_420), .ZN(RRs2[22]) + ); + AOI22_X1_LVT i_1_0_441( + .A1(registers_5__ap[21]), .A2(n_1_0_635), .B1(n_1_0_634), .B2(registers_28__ap[21]), + .ZN(n_1_0_419) + ); + AOI222_X1_LVT i_1_0_440( + .A1(registers_1__ap[21]), .A2(n_1_0_644), .B1(n_1_0_640), .B2(registers_26__ap[21]), + .C1(n_1_0_622), .C2(registers_30__ap[21]), .ZN(n_1_0_418) + ); + AOI22_X1_LVT i_1_0_439( + .A1(registers_29__ap[21]), .A2(n_1_0_649), .B1(n_1_0_618), .B2(registers_2__ap[21]), + .ZN(n_1_0_417) + ); + AOI22_X1_LVT i_1_0_438( + .A1(registers_14__ap[21]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[21]), + .ZN(n_1_0_416) + ); + AOI22_X1_LVT i_1_0_437( + .A1(registers_8__ap[21]), .A2(n_1_0_626), .B1(n_1_0_614), .B2(registers_16__ap[21]), + .ZN(n_1_0_415) + ); + AOI22_X1_LVT i_1_0_436( + .A1(registers_25__ap[21]), .A2(n_1_0_620), .B1(n_1_0_611), .B2(registers_11__ap[21]), + .ZN(n_1_0_414) + ); + AOI22_X1_LVT i_1_0_435( + .A1(registers_10__ap[21]), .A2(n_1_0_624), .B1(n_1_0_616), .B2(registers_6__ap[21]), + .ZN(n_1_0_413) + ); + NAND4_X1_LVT i_1_0_434( + .A1(n_1_0_416), .A2(n_1_0_415), .A3(n_1_0_414), .A4(n_1_0_413), .ZN(n_1_0_412) + ); + AOI22_X1_LVT i_1_0_433( + .A1(registers_12__ap[21]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[21]), + .ZN(n_1_0_411) + ); + AOI22_X1_LVT i_1_0_432( + .A1(registers_22__ap[21]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[21]), + .ZN(n_1_0_410) + ); + AOI22_X1_LVT i_1_0_431( + .A1(registers_4__ap[21]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[21]), + .ZN(n_1_0_409) + ); + AOI22_X1_LVT i_1_0_430( + .A1(registers_18__ap[21]), .A2(n_1_0_646), .B1(n_1_0_633), .B2(registers_19__ap[21]), + .ZN(n_1_0_408) + ); + NAND4_X1_LVT i_1_0_429( + .A1(n_1_0_411), .A2(n_1_0_410), .A3(n_1_0_409), .A4(n_1_0_408), .ZN(n_1_0_407) + ); + AOI22_X1_LVT i_1_0_428( + .A1(registers_15__ap[21]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[21]), + .ZN(n_1_0_406) + ); + AOI22_X1_LVT i_1_0_427( + .A1(registers_23__ap[21]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[21]), + .ZN(n_1_0_405) + ); + AOI22_X1_LVT i_1_0_426( + .A1(registers_13__ap[21]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[21]), + .ZN(n_1_0_404) + ); + AOI22_X1_LVT i_1_0_425( + .A1(registers_31__ap[21]), .A2(n_1_0_637), .B1(n_1_0_636), .B2(registers_27__ap[21]), + .ZN(n_1_0_403) + ); + NAND4_X1_LVT i_1_0_424( + .A1(n_1_0_406), .A2(n_1_0_405), .A3(n_1_0_404), .A4(n_1_0_403), .ZN(n_1_0_402) + ); + NOR3_X1_LVT i_1_0_423( + .A1(n_1_0_412), .A2(n_1_0_407), .A3(n_1_0_402), .ZN(n_1_0_401) + ); + NAND4_X1_LVT i_1_0_422( + .A1(n_1_0_419), .A2(n_1_0_418), .A3(n_1_0_417), .A4(n_1_0_401), .ZN(RRs2[21]) + ); + AOI22_X1_LVT i_1_0_421( + .A1(registers_17__ap[20]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[20]), + .ZN(n_1_0_400) + ); + AOI222_X1_LVT i_1_0_420( + .A1(registers_13__ap[20]), .A2(n_1_0_631), .B1(n_1_0_622), .B2(registers_30__ap[20]), + .C1(registers_19__ap[20]), .C2(n_1_0_633), .ZN(n_1_0_399) + ); + AOI22_X1_LVT i_1_0_419( + .A1(registers_1__ap[20]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[20]), + .ZN(n_1_0_398) + ); + AOI22_X1_LVT i_1_0_418( + .A1(registers_24__ap[20]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[20]), + .ZN(n_1_0_397) + ); + AOI22_X1_LVT i_1_0_417( + .A1(registers_6__ap[20]), .A2(n_1_0_616), .B1(n_1_0_611), .B2(registers_11__ap[20]), + .ZN(n_1_0_396) + ); + AOI22_X1_LVT i_1_0_416( + .A1(registers_4__ap[20]), .A2(n_1_0_638), .B1(n_1_0_624), .B2(registers_10__ap[20]), + .ZN(n_1_0_395) + ); + AOI22_X1_LVT i_1_0_415( + .A1(registers_31__ap[20]), .A2(n_1_0_637), .B1(n_1_0_618), .B2(registers_2__ap[20]), + .ZN(n_1_0_394) + ); + NAND4_X1_LVT i_1_0_414( + .A1(n_1_0_397), .A2(n_1_0_396), .A3(n_1_0_395), .A4(n_1_0_394), .ZN(n_1_0_393) + ); + AOI22_X1_LVT i_1_0_413( + .A1(registers_18__ap[20]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[20]), + .ZN(n_1_0_392) + ); + AOI22_X1_LVT i_1_0_412( + .A1(registers_5__ap[20]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[20]), + .ZN(n_1_0_391) + ); + AOI22_X1_LVT i_1_0_411( + .A1(registers_15__ap[20]), .A2(n_1_0_627), .B1(n_1_0_614), .B2(registers_16__ap[20]), + .ZN(n_1_0_390) + ); + AOI22_X1_LVT i_1_0_410( + .A1(registers_22__ap[20]), .A2(n_1_0_642), .B1(n_1_0_620), .B2(registers_25__ap[20]), + .ZN(n_1_0_389) + ); + NAND4_X1_LVT i_1_0_409( + .A1(n_1_0_392), .A2(n_1_0_391), .A3(n_1_0_390), .A4(n_1_0_389), .ZN(n_1_0_388) + ); + AOI22_X1_LVT i_1_0_408( + .A1(registers_29__ap[20]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[20]), + .ZN(n_1_0_387) + ); + AOI22_X1_LVT i_1_0_407( + .A1(registers_7__ap[20]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[20]), + .ZN(n_1_0_386) + ); + AOI22_X1_LVT i_1_0_406( + .A1(registers_8__ap[20]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[20]), + .ZN(n_1_0_385) + ); + AOI22_X1_LVT i_1_0_405( + .A1(registers_27__ap[20]), .A2(n_1_0_636), .B1(n_1_0_610), .B2(registers_3__ap[20]), + .ZN(n_1_0_384) + ); + NAND4_X1_LVT i_1_0_404( + .A1(n_1_0_387), .A2(n_1_0_386), .A3(n_1_0_385), .A4(n_1_0_384), .ZN(n_1_0_383) + ); + NOR3_X1_LVT i_1_0_403( + .A1(n_1_0_393), .A2(n_1_0_388), .A3(n_1_0_383), .ZN(n_1_0_382) + ); + NAND4_X1_LVT i_1_0_402( + .A1(n_1_0_400), .A2(n_1_0_399), .A3(n_1_0_398), .A4(n_1_0_382), .ZN(RRs2[20]) + ); + AOI22_X1_LVT i_1_0_401( + .A1(registers_17__ap[19]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[19]), + .ZN(n_1_0_381) + ); + AOI222_X1_LVT i_1_0_400( + .A1(registers_13__ap[19]), .A2(n_1_0_631), .B1(n_1_0_622), .B2(registers_30__ap[19]), + .C1(registers_19__ap[19]), .C2(n_1_0_633), .ZN(n_1_0_380) + ); + AOI22_X1_LVT i_1_0_399( + .A1(registers_1__ap[19]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[19]), + .ZN(n_1_0_379) + ); + AOI22_X1_LVT i_1_0_398( + .A1(registers_24__ap[19]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[19]), + .ZN(n_1_0_378) + ); + AOI22_X1_LVT i_1_0_397( + .A1(registers_15__ap[19]), .A2(n_1_0_627), .B1(n_1_0_611), .B2(registers_11__ap[19]), + .ZN(n_1_0_377) + ); + AOI22_X1_LVT i_1_0_396( + .A1(registers_4__ap[19]), .A2(n_1_0_638), .B1(n_1_0_636), .B2(registers_27__ap[19]), + .ZN(n_1_0_376) + ); + AOI22_X1_LVT i_1_0_395( + .A1(registers_31__ap[19]), .A2(n_1_0_637), .B1(n_1_0_618), .B2(registers_2__ap[19]), + .ZN(n_1_0_375) + ); + NAND4_X1_LVT i_1_0_394( + .A1(n_1_0_378), .A2(n_1_0_377), .A3(n_1_0_376), .A4(n_1_0_375), .ZN(n_1_0_374) + ); + AOI22_X1_LVT i_1_0_393( + .A1(registers_18__ap[19]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[19]), + .ZN(n_1_0_373) + ); + AOI22_X1_LVT i_1_0_392( + .A1(registers_5__ap[19]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[19]), + .ZN(n_1_0_372) + ); + AOI22_X1_LVT i_1_0_391( + .A1(registers_25__ap[19]), .A2(n_1_0_620), .B1(n_1_0_616), .B2(registers_6__ap[19]), + .ZN(n_1_0_371) + ); + AOI22_X1_LVT i_1_0_390( + .A1(registers_22__ap[19]), .A2(n_1_0_642), .B1(n_1_0_614), .B2(registers_16__ap[19]), + .ZN(n_1_0_370) + ); + NAND4_X1_LVT i_1_0_389( + .A1(n_1_0_373), .A2(n_1_0_372), .A3(n_1_0_371), .A4(n_1_0_370), .ZN(n_1_0_369) + ); + AOI22_X1_LVT i_1_0_388( + .A1(registers_29__ap[19]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[19]), + .ZN(n_1_0_368) + ); + AOI22_X1_LVT i_1_0_387( + .A1(registers_7__ap[19]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[19]), + .ZN(n_1_0_367) + ); + AOI22_X1_LVT i_1_0_386( + .A1(registers_8__ap[19]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[19]), + .ZN(n_1_0_366) + ); + AOI22_X1_LVT i_1_0_385( + .A1(registers_10__ap[19]), .A2(n_1_0_624), .B1(n_1_0_610), .B2(registers_3__ap[19]), + .ZN(n_1_0_365) + ); + NAND4_X1_LVT i_1_0_384( + .A1(n_1_0_368), .A2(n_1_0_367), .A3(n_1_0_366), .A4(n_1_0_365), .ZN(n_1_0_364) + ); + NOR3_X1_LVT i_1_0_383( + .A1(n_1_0_374), .A2(n_1_0_369), .A3(n_1_0_364), .ZN(n_1_0_363) + ); + NAND4_X1_LVT i_1_0_382( + .A1(n_1_0_381), .A2(n_1_0_380), .A3(n_1_0_379), .A4(n_1_0_363), .ZN(RRs2[19]) + ); + AOI22_X1_LVT i_1_0_380( + .A1(registers_4__ap[18]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[18]), + .ZN(n_1_0_361) + ); + AOI22_X1_LVT i_1_0_381( + .A1(registers_8__ap[18]), .A2(n_1_0_626), .B1(n_1_0_614), .B2(registers_16__ap[18]), + .ZN(n_1_0_362) + ); + AOI22_X1_LVT i_1_0_379( + .A1(registers_14__ap[18]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[18]), + .ZN(n_1_0_360) + ); + AOI22_X1_LVT i_1_0_378( + .A1(registers_25__ap[18]), .A2(n_1_0_620), .B1(n_1_0_611), .B2(registers_11__ap[18]), + .ZN(n_1_0_359) + ); + NAND3_X1_LVT i_1_0_377( + .A1(n_1_0_362), .A2(n_1_0_360), .A3(n_1_0_359), .ZN(n_1_0_358) + ); + AOI221_X1_LVT i_1_0_376( + .A(n_1_0_358), .B1(n_1_0_624), .B2(registers_10__ap[18]), .C1(registers_6__ap[18]), + .C2(n_1_0_616), .ZN(n_1_0_357) + ); + AOI222_X1_LVT i_1_0_375( + .A1(registers_1__ap[18]), .A2(n_1_0_644), .B1(n_1_0_640), .B2(registers_26__ap[18]), + .C1(n_1_0_622), .C2(registers_30__ap[18]), .ZN(n_1_0_356) + ); + NAND2_X1_LVT i_1_0_374( + .A1(n_1_0_357), .A2(n_1_0_356), .ZN(n_1_0_355) + ); + AOI221_X1_LVT i_1_0_373( + .A(n_1_0_355), .B1(n_1_0_649), .B2(registers_29__ap[18]), .C1(registers_2__ap[18]), + .C2(n_1_0_618), .ZN(n_1_0_354) + ); + AOI22_X1_LVT i_1_0_372( + .A1(registers_18__ap[18]), .A2(n_1_0_646), .B1(n_1_0_633), .B2(registers_19__ap[18]), + .ZN(n_1_0_353) + ); + AOI22_X1_LVT i_1_0_371( + .A1(registers_12__ap[18]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[18]), + .ZN(n_1_0_352) + ); + AOI22_X1_LVT i_1_0_370( + .A1(registers_22__ap[18]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[18]), + .ZN(n_1_0_351) + ); + NAND3_X1_LVT i_1_0_369( + .A1(n_1_0_353), .A2(n_1_0_352), .A3(n_1_0_351), .ZN(n_1_0_350) + ); + AOI221_X1_LVT i_1_0_368( + .A(n_1_0_350), .B1(n_1_0_635), .B2(registers_5__ap[18]), .C1(registers_20__ap[18]), + .C2(n_1_0_613), .ZN(n_1_0_349) + ); + AOI22_X1_LVT i_1_0_367( + .A1(registers_15__ap[18]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[18]), + .ZN(n_1_0_348) + ); + AOI22_X1_LVT i_1_0_366( + .A1(registers_23__ap[18]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[18]), + .ZN(n_1_0_347) + ); + AOI22_X1_LVT i_1_0_365( + .A1(registers_13__ap[18]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[18]), + .ZN(n_1_0_346) + ); + NAND3_X1_LVT i_1_0_364( + .A1(n_1_0_348), .A2(n_1_0_347), .A3(n_1_0_346), .ZN(n_1_0_345) + ); + AOI221_X1_LVT i_1_0_363( + .A(n_1_0_345), .B1(n_1_0_637), .B2(registers_31__ap[18]), .C1(registers_27__ap[18]), + .C2(n_1_0_636), .ZN(n_1_0_344) + ); + NAND4_X1_LVT i_1_0_362( + .A1(n_1_0_361), .A2(n_1_0_354), .A3(n_1_0_349), .A4(n_1_0_344), .ZN(RRs2[18]) + ); + AOI22_X1_LVT i_1_0_358( + .A1(registers_4__ap[17]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[17]), + .ZN(n_1_0_340) + ); + AOI22_X1_LVT i_1_0_361( + .A1(registers_31__ap[17]), .A2(n_1_0_637), .B1(n_1_0_616), .B2(registers_6__ap[17]), + .ZN(n_1_0_343) + ); + AOI22_X1_LVT i_1_0_357( + .A1(registers_14__ap[17]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[17]), + .ZN(n_1_0_339) + ); + AOI22_X1_LVT i_1_0_360( + .A1(registers_25__ap[17]), .A2(n_1_0_620), .B1(n_1_0_611), .B2(registers_11__ap[17]), + .ZN(n_1_0_342) + ); + INV_X1_LVT i_1_0_359( + .A(n_1_0_342), .ZN(n_1_0_341) + ); + AOI221_X1_LVT i_1_0_356( + .A(n_1_0_341), .B1(n_1_0_614), .B2(registers_16__ap[17]), .C1(registers_10__ap[17]), + .C2(n_1_0_624), .ZN(n_1_0_338) + ); + AOI222_X1_LVT i_1_0_355( + .A1(registers_1__ap[17]), .A2(n_1_0_644), .B1(n_1_0_622), .B2(registers_30__ap[17]), + .C1(registers_18__ap[17]), .C2(n_1_0_646), .ZN(n_1_0_337) + ); + NAND4_X1_LVT i_1_0_354( + .A1(n_1_0_343), .A2(n_1_0_339), .A3(n_1_0_338), .A4(n_1_0_337), .ZN(n_1_0_336) + ); + AOI221_X1_LVT i_1_0_353( + .A(n_1_0_336), .B1(n_1_0_649), .B2(registers_29__ap[17]), .C1(registers_2__ap[17]), + .C2(n_1_0_618), .ZN(n_1_0_335) + ); + AOI22_X1_LVT i_1_0_352( + .A1(registers_26__ap[17]), .A2(n_1_0_640), .B1(n_1_0_633), .B2(registers_19__ap[17]), + .ZN(n_1_0_334) + ); + AOI22_X1_LVT i_1_0_351( + .A1(registers_12__ap[17]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[17]), + .ZN(n_1_0_333) + ); + AOI22_X1_LVT i_1_0_350( + .A1(registers_22__ap[17]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[17]), + .ZN(n_1_0_332) + ); + NAND3_X1_LVT i_1_0_349( + .A1(n_1_0_334), .A2(n_1_0_333), .A3(n_1_0_332), .ZN(n_1_0_331) + ); + AOI221_X1_LVT i_1_0_348( + .A(n_1_0_331), .B1(n_1_0_635), .B2(registers_5__ap[17]), .C1(registers_20__ap[17]), + .C2(n_1_0_613), .ZN(n_1_0_330) + ); + AOI22_X1_LVT i_1_0_347( + .A1(registers_15__ap[17]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[17]), + .ZN(n_1_0_329) + ); + AOI22_X1_LVT i_1_0_346( + .A1(registers_8__ap[17]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[17]), + .ZN(n_1_0_328) + ); + AOI22_X1_LVT i_1_0_345( + .A1(registers_13__ap[17]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[17]), + .ZN(n_1_0_327) + ); + NAND3_X1_LVT i_1_0_344( + .A1(n_1_0_329), .A2(n_1_0_328), .A3(n_1_0_327), .ZN(n_1_0_326) + ); + AOI221_X1_LVT i_1_0_343( + .A(n_1_0_326), .B1(n_1_0_636), .B2(registers_27__ap[17]), .C1(registers_3__ap[17]), + .C2(n_1_0_610), .ZN(n_1_0_325) + ); + NAND4_X1_LVT i_1_0_342( + .A1(n_1_0_340), .A2(n_1_0_335), .A3(n_1_0_330), .A4(n_1_0_325), .ZN(RRs2[17]) + ); + AOI22_X1_LVT i_1_0_341( + .A1(registers_4__ap[16]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[16]), + .ZN(n_1_0_324) + ); + AOI222_X1_LVT i_1_0_340( + .A1(registers_1__ap[16]), .A2(n_1_0_644), .B1(n_1_0_633), .B2(registers_19__ap[16]), + .C1(n_1_0_622), .C2(registers_30__ap[16]), .ZN(n_1_0_323) + ); + AOI22_X1_LVT i_1_0_339( + .A1(registers_29__ap[16]), .A2(n_1_0_649), .B1(n_1_0_618), .B2(registers_2__ap[16]), + .ZN(n_1_0_322) + ); + AOI22_X1_LVT i_1_0_338( + .A1(registers_14__ap[16]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[16]), + .ZN(n_1_0_321) + ); + AOI22_X1_LVT i_1_0_337( + .A1(registers_16__ap[16]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[16]), + .ZN(n_1_0_320) + ); + AOI22_X1_LVT i_1_0_336( + .A1(registers_10__ap[16]), .A2(n_1_0_624), .B1(n_1_0_620), .B2(registers_25__ap[16]), + .ZN(n_1_0_319) + ); + AOI22_X1_LVT i_1_0_335( + .A1(registers_31__ap[16]), .A2(n_1_0_637), .B1(n_1_0_616), .B2(registers_6__ap[16]), + .ZN(n_1_0_318) + ); + NAND4_X1_LVT i_1_0_334( + .A1(n_1_0_321), .A2(n_1_0_320), .A3(n_1_0_319), .A4(n_1_0_318), .ZN(n_1_0_317) + ); + AOI22_X1_LVT i_1_0_333( + .A1(registers_18__ap[16]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[16]), + .ZN(n_1_0_316) + ); + AOI22_X1_LVT i_1_0_332( + .A1(registers_12__ap[16]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[16]), + .ZN(n_1_0_315) + ); + AOI22_X1_LVT i_1_0_331( + .A1(registers_22__ap[16]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[16]), + .ZN(n_1_0_314) + ); + AOI22_X1_LVT i_1_0_330( + .A1(registers_5__ap[16]), .A2(n_1_0_635), .B1(n_1_0_613), .B2(registers_20__ap[16]), + .ZN(n_1_0_313) + ); + NAND4_X1_LVT i_1_0_329( + .A1(n_1_0_316), .A2(n_1_0_315), .A3(n_1_0_314), .A4(n_1_0_313), .ZN(n_1_0_312) + ); + AOI22_X1_LVT i_1_0_328( + .A1(registers_15__ap[16]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[16]), + .ZN(n_1_0_311) + ); + AOI22_X1_LVT i_1_0_327( + .A1(registers_8__ap[16]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[16]), + .ZN(n_1_0_310) + ); + AOI22_X1_LVT i_1_0_326( + .A1(registers_13__ap[16]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[16]), + .ZN(n_1_0_309) + ); + AOI22_X1_LVT i_1_0_325( + .A1(registers_27__ap[16]), .A2(n_1_0_636), .B1(n_1_0_610), .B2(registers_3__ap[16]), + .ZN(n_1_0_308) + ); + NAND4_X1_LVT i_1_0_324( + .A1(n_1_0_311), .A2(n_1_0_310), .A3(n_1_0_309), .A4(n_1_0_308), .ZN(n_1_0_307) + ); + NOR3_X1_LVT i_1_0_323( + .A1(n_1_0_317), .A2(n_1_0_312), .A3(n_1_0_307), .ZN(n_1_0_306) + ); + NAND4_X1_LVT i_1_0_322( + .A1(n_1_0_324), .A2(n_1_0_323), .A3(n_1_0_322), .A4(n_1_0_306), .ZN(RRs2[16]) + ); + AOI22_X1_LVT i_1_0_320( + .A1(registers_5__ap[15]), .A2(n_1_0_635), .B1(n_1_0_634), .B2(registers_28__ap[15]), + .ZN(n_1_0_304) + ); + AOI22_X1_LVT i_1_0_321( + .A1(registers_8__ap[15]), .A2(n_1_0_626), .B1(n_1_0_620), .B2(registers_25__ap[15]), + .ZN(n_1_0_305) + ); + AOI22_X1_LVT i_1_0_319( + .A1(registers_14__ap[15]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[15]), + .ZN(n_1_0_303) + ); + AOI22_X1_LVT i_1_0_318( + .A1(registers_16__ap[15]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[15]), + .ZN(n_1_0_302) + ); + NAND3_X1_LVT i_1_0_317( + .A1(n_1_0_305), .A2(n_1_0_303), .A3(n_1_0_302), .ZN(n_1_0_301) + ); + AOI221_X1_LVT i_1_0_316( + .A(n_1_0_301), .B1(n_1_0_616), .B2(registers_6__ap[15]), .C1(registers_10__ap[15]), + .C2(n_1_0_624), .ZN(n_1_0_300) + ); + AOI222_X1_LVT i_1_0_315( + .A1(registers_1__ap[15]), .A2(n_1_0_644), .B1(n_1_0_640), .B2(registers_26__ap[15]), + .C1(n_1_0_622), .C2(registers_30__ap[15]), .ZN(n_1_0_299) + ); + NAND2_X1_LVT i_1_0_314( + .A1(n_1_0_300), .A2(n_1_0_299), .ZN(n_1_0_298) + ); + AOI221_X1_LVT i_1_0_313( + .A(n_1_0_298), .B1(n_1_0_649), .B2(registers_29__ap[15]), .C1(registers_2__ap[15]), + .C2(n_1_0_618), .ZN(n_1_0_297) + ); + AOI22_X1_LVT i_1_0_312( + .A1(registers_12__ap[15]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[15]), + .ZN(n_1_0_296) + ); + AOI22_X1_LVT i_1_0_311( + .A1(registers_22__ap[15]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[15]), + .ZN(n_1_0_295) + ); + AOI22_X1_LVT i_1_0_310( + .A1(registers_4__ap[15]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[15]), + .ZN(n_1_0_294) + ); + NAND3_X1_LVT i_1_0_309( + .A1(n_1_0_296), .A2(n_1_0_295), .A3(n_1_0_294), .ZN(n_1_0_293) + ); + AOI221_X1_LVT i_1_0_308( + .A(n_1_0_293), .B1(n_1_0_633), .B2(registers_19__ap[15]), .C1(registers_18__ap[15]), + .C2(n_1_0_646), .ZN(n_1_0_292) + ); + AOI22_X1_LVT i_1_0_307( + .A1(registers_15__ap[15]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[15]), + .ZN(n_1_0_291) + ); + AOI22_X1_LVT i_1_0_306( + .A1(registers_23__ap[15]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[15]), + .ZN(n_1_0_290) + ); + AOI22_X1_LVT i_1_0_305( + .A1(registers_13__ap[15]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[15]), + .ZN(n_1_0_289) + ); + NAND3_X1_LVT i_1_0_304( + .A1(n_1_0_291), .A2(n_1_0_290), .A3(n_1_0_289), .ZN(n_1_0_288) + ); + AOI221_X1_LVT i_1_0_303( + .A(n_1_0_288), .B1(n_1_0_636), .B2(registers_27__ap[15]), .C1(registers_31__ap[15]), + .C2(n_1_0_637), .ZN(n_1_0_287) + ); + NAND4_X1_LVT i_1_0_302( + .A1(n_1_0_304), .A2(n_1_0_297), .A3(n_1_0_292), .A4(n_1_0_287), .ZN(RRs2[15]) + ); + AOI22_X1_LVT i_1_0_301( + .A1(registers_28__ap[14]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[14]), + .ZN(n_1_0_286) + ); + AOI222_X1_LVT i_1_0_300( + .A1(registers_18__ap[14]), .A2(n_1_0_646), .B1(n_1_0_620), .B2(registers_25__ap[14]), + .C1(n_1_0_618), .C2(registers_2__ap[14]), .ZN(n_1_0_285) + ); + AOI22_X1_LVT i_1_0_299( + .A1(registers_24__ap[14]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[14]), + .ZN(n_1_0_284) + ); + AOI22_X1_LVT i_1_0_298( + .A1(registers_15__ap[14]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[14]), + .ZN(n_1_0_283) + ); + AOI22_X1_LVT i_1_0_297( + .A1(registers_4__ap[14]), .A2(n_1_0_638), .B1(n_1_0_637), .B2(registers_31__ap[14]), + .ZN(n_1_0_282) + ); + AOI22_X1_LVT i_1_0_296( + .A1(registers_29__ap[14]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[14]), + .ZN(n_1_0_281) + ); + NAND4_X1_LVT i_1_0_295( + .A1(n_1_0_284), .A2(n_1_0_283), .A3(n_1_0_282), .A4(n_1_0_281), .ZN(n_1_0_280) + ); + AOI221_X1_LVT i_1_0_294( + .A(n_1_0_280), .B1(n_1_0_644), .B2(registers_1__ap[14]), .C1(registers_13__ap[14]), + .C2(n_1_0_631), .ZN(n_1_0_279) + ); + AOI22_X1_LVT i_1_0_293( + .A1(registers_17__ap[14]), .A2(n_1_0_629), .B1(n_1_0_623), .B2(registers_7__ap[14]), + .ZN(n_1_0_278) + ); + AOI22_X1_LVT i_1_0_292( + .A1(registers_5__ap[14]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[14]), + .ZN(n_1_0_277) + ); + AOI22_X1_LVT i_1_0_291( + .A1(registers_10__ap[14]), .A2(n_1_0_624), .B1(n_1_0_622), .B2(registers_30__ap[14]), + .ZN(n_1_0_276) + ); + AOI22_X1_LVT i_1_0_290( + .A1(registers_26__ap[14]), .A2(n_1_0_640), .B1(n_1_0_614), .B2(registers_16__ap[14]), + .ZN(n_1_0_275) + ); + NAND4_X1_LVT i_1_0_289( + .A1(n_1_0_278), .A2(n_1_0_277), .A3(n_1_0_276), .A4(n_1_0_275), .ZN(n_1_0_274) + ); + AOI22_X1_LVT i_1_0_288( + .A1(registers_9__ap[14]), .A2(n_1_0_617), .B1(n_1_0_612), .B2(registers_21__ap[14]), + .ZN(n_1_0_273) + ); + AOI22_X1_LVT i_1_0_287( + .A1(registers_14__ap[14]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[14]), + .ZN(n_1_0_272) + ); + AOI22_X1_LVT i_1_0_286( + .A1(registers_22__ap[14]), .A2(n_1_0_642), .B1(n_1_0_633), .B2(registers_19__ap[14]), + .ZN(n_1_0_271) + ); + AOI22_X1_LVT i_1_0_285( + .A1(registers_27__ap[14]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[14]), + .ZN(n_1_0_270) + ); + NAND4_X1_LVT i_1_0_284( + .A1(n_1_0_273), .A2(n_1_0_272), .A3(n_1_0_271), .A4(n_1_0_270), .ZN(n_1_0_269) + ); + NOR2_X1_LVT i_1_0_283( + .A1(n_1_0_274), .A2(n_1_0_269), .ZN(n_1_0_268) + ); + NAND4_X1_LVT i_1_0_282( + .A1(n_1_0_286), .A2(n_1_0_285), .A3(n_1_0_279), .A4(n_1_0_268), .ZN(RRs2[14]) + ); + AOI22_X1_LVT i_1_0_281( + .A1(registers_18__ap[13]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[13]), + .ZN(n_1_0_267) + ); + AOI22_X1_LVT i_1_0_280( + .A1(registers_12__ap[13]), .A2(n_1_0_632), .B1(n_1_0_629), .B2(registers_17__ap[13]), + .ZN(n_1_0_266) + ); + AOI22_X1_LVT i_1_0_279( + .A1(registers_7__ap[13]), .A2(n_1_0_623), .B1(n_1_0_614), .B2(registers_16__ap[13]), + .ZN(n_1_0_265) + ); + NAND3_X1_LVT i_1_0_277( + .A1(n_1_0_267), .A2(n_1_0_266), .A3(n_1_0_265), .ZN(n_1_0_263) + ); + AOI221_X1_LVT i_1_0_276( + .A(n_1_0_263), .B1(n_1_0_642), .B2(registers_22__ap[13]), .C1(registers_5__ap[13]), + .C2(n_1_0_635), .ZN(n_1_0_262) + ); + AOI22_X1_LVT i_1_0_278( + .A1(registers_13__ap[13]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[13]), + .ZN(n_1_0_264) + ); + AOI222_X1_LVT i_1_0_275( + .A1(registers_26__ap[13]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[13]), + .C1(n_1_0_620), .C2(registers_25__ap[13]), .ZN(n_1_0_261) + ); + AOI22_X1_LVT i_1_0_274( + .A1(registers_28__ap[13]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[13]), + .ZN(n_1_0_260) + ); + NAND3_X1_LVT i_1_0_273( + .A1(n_1_0_264), .A2(n_1_0_261), .A3(n_1_0_260), .ZN(n_1_0_259) + ); + AOI22_X1_LVT i_1_0_272( + .A1(registers_1__ap[13]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[13]), + .ZN(n_1_0_258) + ); + AOI22_X1_LVT i_1_0_271( + .A1(registers_19__ap[13]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[13]), + .ZN(n_1_0_257) + ); + AOI22_X1_LVT i_1_0_270( + .A1(registers_14__ap[13]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[13]), + .ZN(n_1_0_256) + ); + AOI22_X1_LVT i_1_0_269( + .A1(registers_27__ap[13]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[13]), + .ZN(n_1_0_255) + ); + NAND4_X1_LVT i_1_0_268( + .A1(n_1_0_258), .A2(n_1_0_257), .A3(n_1_0_256), .A4(n_1_0_255), .ZN(n_1_0_254) + ); + AOI22_X1_LVT i_1_0_267( + .A1(registers_24__ap[13]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[13]), + .ZN(n_1_0_253) + ); + AOI22_X1_LVT i_1_0_266( + .A1(registers_4__ap[13]), .A2(n_1_0_638), .B1(n_1_0_637), .B2(registers_31__ap[13]), + .ZN(n_1_0_252) + ); + AOI22_X1_LVT i_1_0_265( + .A1(registers_29__ap[13]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[13]), + .ZN(n_1_0_251) + ); + AOI22_X1_LVT i_1_0_264( + .A1(registers_15__ap[13]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[13]), + .ZN(n_1_0_250) + ); + NAND4_X1_LVT i_1_0_263( + .A1(n_1_0_253), .A2(n_1_0_252), .A3(n_1_0_251), .A4(n_1_0_250), .ZN(n_1_0_249) + ); + NOR3_X1_LVT i_1_0_262( + .A1(n_1_0_259), .A2(n_1_0_254), .A3(n_1_0_249), .ZN(n_1_0_248) + ); + NAND2_X1_LVT i_1_0_261( + .A1(n_1_0_262), .A2(n_1_0_248), .ZN(RRs2[13]) + ); + AOI22_X1_LVT i_1_0_260( + .A1(registers_18__ap[12]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[12]), + .ZN(n_1_0_247) + ); + AOI22_X1_LVT i_1_0_259( + .A1(registers_12__ap[12]), .A2(n_1_0_632), .B1(n_1_0_629), .B2(registers_17__ap[12]), + .ZN(n_1_0_246) + ); + AOI22_X1_LVT i_1_0_258( + .A1(registers_5__ap[12]), .A2(n_1_0_635), .B1(n_1_0_623), .B2(registers_7__ap[12]), + .ZN(n_1_0_245) + ); + NAND3_X1_LVT i_1_0_256( + .A1(n_1_0_247), .A2(n_1_0_246), .A3(n_1_0_245), .ZN(n_1_0_243) + ); + AOI221_X1_LVT i_1_0_255( + .A(n_1_0_243), .B1(n_1_0_642), .B2(registers_22__ap[12]), .C1(registers_16__ap[12]), + .C2(n_1_0_614), .ZN(n_1_0_242) + ); + AOI22_X1_LVT i_1_0_257( + .A1(registers_13__ap[12]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[12]), + .ZN(n_1_0_244) + ); + AOI222_X1_LVT i_1_0_254( + .A1(registers_26__ap[12]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[12]), + .C1(n_1_0_620), .C2(registers_25__ap[12]), .ZN(n_1_0_241) + ); + AOI22_X1_LVT i_1_0_253( + .A1(registers_28__ap[12]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[12]), + .ZN(n_1_0_240) + ); + NAND3_X1_LVT i_1_0_252( + .A1(n_1_0_244), .A2(n_1_0_241), .A3(n_1_0_240), .ZN(n_1_0_239) + ); + AOI22_X1_LVT i_1_0_251( + .A1(registers_1__ap[12]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[12]), + .ZN(n_1_0_238) + ); + AOI22_X1_LVT i_1_0_250( + .A1(registers_19__ap[12]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[12]), + .ZN(n_1_0_237) + ); + AOI22_X1_LVT i_1_0_249( + .A1(registers_14__ap[12]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[12]), + .ZN(n_1_0_236) + ); + AOI22_X1_LVT i_1_0_248( + .A1(registers_27__ap[12]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[12]), + .ZN(n_1_0_235) + ); + NAND4_X1_LVT i_1_0_247( + .A1(n_1_0_238), .A2(n_1_0_237), .A3(n_1_0_236), .A4(n_1_0_235), .ZN(n_1_0_234) + ); + AOI22_X1_LVT i_1_0_246( + .A1(registers_24__ap[12]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[12]), + .ZN(n_1_0_233) + ); + AOI22_X1_LVT i_1_0_245( + .A1(registers_4__ap[12]), .A2(n_1_0_638), .B1(n_1_0_637), .B2(registers_31__ap[12]), + .ZN(n_1_0_232) + ); + AOI22_X1_LVT i_1_0_244( + .A1(registers_29__ap[12]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[12]), + .ZN(n_1_0_231) + ); + AOI22_X1_LVT i_1_0_243( + .A1(registers_15__ap[12]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[12]), + .ZN(n_1_0_230) + ); + NAND4_X1_LVT i_1_0_242( + .A1(n_1_0_233), .A2(n_1_0_232), .A3(n_1_0_231), .A4(n_1_0_230), .ZN(n_1_0_229) + ); + NOR3_X1_LVT i_1_0_241( + .A1(n_1_0_239), .A2(n_1_0_234), .A3(n_1_0_229), .ZN(n_1_0_228) + ); + NAND2_X1_LVT i_1_0_240( + .A1(n_1_0_242), .A2(n_1_0_228), .ZN(RRs2[12]) + ); + AOI22_X1_LVT i_1_0_238( + .A1(registers_29__ap[11]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[11]), + .ZN(n_1_0_226) + ); + AOI22_X1_LVT i_1_0_239( + .A1(registers_27__ap[11]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[11]), + .ZN(n_1_0_227) + ); + AOI22_X1_LVT i_1_0_237( + .A1(registers_1__ap[11]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[11]), + .ZN(n_1_0_225) + ); + AOI22_X1_LVT i_1_0_236( + .A1(registers_5__ap[11]), .A2(n_1_0_635), .B1(n_1_0_615), .B2(registers_23__ap[11]), + .ZN(n_1_0_224) + ); + NAND3_X1_LVT i_1_0_235( + .A1(n_1_0_227), .A2(n_1_0_225), .A3(n_1_0_224), .ZN(n_1_0_223) + ); + AOI221_X1_LVT i_1_0_234( + .A(n_1_0_223), .B1(n_1_0_637), .B2(registers_31__ap[11]), .C1(registers_16__ap[11]), + .C2(n_1_0_614), .ZN(n_1_0_222) + ); + AOI222_X1_LVT i_1_0_233( + .A1(registers_8__ap[11]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[11]), + .C1(n_1_0_622), .C2(registers_30__ap[11]), .ZN(n_1_0_221) + ); + NAND3_X1_LVT i_1_0_232( + .A1(n_1_0_226), .A2(n_1_0_222), .A3(n_1_0_221), .ZN(n_1_0_220) + ); + AOI221_X1_LVT i_1_0_231( + .A(n_1_0_220), .B1(n_1_0_638), .B2(registers_4__ap[11]), .C1(registers_28__ap[11]), + .C2(n_1_0_634), .ZN(n_1_0_219) + ); + AOI22_X1_LVT i_1_0_230( + .A1(registers_18__ap[11]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[11]), + .ZN(n_1_0_218) + ); + AOI22_X1_LVT i_1_0_229( + .A1(registers_12__ap[11]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[11]), + .ZN(n_1_0_217) + ); + AOI22_X1_LVT i_1_0_228( + .A1(registers_22__ap[11]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[11]), + .ZN(n_1_0_216) + ); + NAND3_X1_LVT i_1_0_227( + .A1(n_1_0_218), .A2(n_1_0_217), .A3(n_1_0_216), .ZN(n_1_0_215) + ); + AOI221_X1_LVT i_1_0_226( + .A(n_1_0_215), .B1(n_1_0_613), .B2(registers_20__ap[11]), .C1(registers_17__ap[11]), + .C2(n_1_0_629), .ZN(n_1_0_214) + ); + AOI22_X1_LVT i_1_0_225( + .A1(registers_13__ap[11]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[11]), + .ZN(n_1_0_213) + ); + AOI22_X1_LVT i_1_0_224( + .A1(registers_7__ap[11]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[11]), + .ZN(n_1_0_212) + ); + AOI22_X1_LVT i_1_0_223( + .A1(registers_19__ap[11]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[11]), + .ZN(n_1_0_211) + ); + NAND3_X1_LVT i_1_0_222( + .A1(n_1_0_213), .A2(n_1_0_212), .A3(n_1_0_211), .ZN(n_1_0_210) + ); + AOI221_X1_LVT i_1_0_221( + .A(n_1_0_210), .B1(n_1_0_611), .B2(registers_11__ap[11]), .C1(registers_2__ap[11]), + .C2(n_1_0_618), .ZN(n_1_0_209) + ); + NAND3_X1_LVT i_1_0_220( + .A1(n_1_0_219), .A2(n_1_0_214), .A3(n_1_0_209), .ZN(RRs2[11]) + ); + AOI22_X1_LVT i_1_0_219( + .A1(registers_28__ap[10]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[10]), + .ZN(n_1_0_208) + ); + AOI222_X1_LVT i_1_0_218( + .A1(registers_26__ap[10]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[10]), + .C1(registers_25__ap[10]), .C2(n_1_0_620), .ZN(n_1_0_207) + ); + AOI22_X1_LVT i_1_0_217( + .A1(registers_13__ap[10]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[10]), + .ZN(n_1_0_206) + ); + AOI22_X1_LVT i_1_0_216( + .A1(registers_24__ap[10]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[10]), + .ZN(n_1_0_205) + ); + AOI22_X1_LVT i_1_0_215( + .A1(registers_15__ap[10]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[10]), + .ZN(n_1_0_204) + ); + AOI22_X1_LVT i_1_0_214( + .A1(registers_31__ap[10]), .A2(n_1_0_637), .B1(n_1_0_629), .B2(registers_17__ap[10]), + .ZN(n_1_0_203) + ); + AOI22_X1_LVT i_1_0_213( + .A1(registers_29__ap[10]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[10]), + .ZN(n_1_0_202) + ); + NAND4_X1_LVT i_1_0_212( + .A1(n_1_0_205), .A2(n_1_0_204), .A3(n_1_0_203), .A4(n_1_0_202), .ZN(n_1_0_201) + ); + AOI22_X1_LVT i_1_0_211( + .A1(registers_18__ap[10]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[10]), + .ZN(n_1_0_200) + ); + AOI22_X1_LVT i_1_0_210( + .A1(registers_4__ap[10]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[10]), + .ZN(n_1_0_199) + ); + AOI22_X1_LVT i_1_0_209( + .A1(registers_7__ap[10]), .A2(n_1_0_623), .B1(n_1_0_614), .B2(registers_16__ap[10]), + .ZN(n_1_0_198) + ); + AOI22_X1_LVT i_1_0_208( + .A1(registers_22__ap[10]), .A2(n_1_0_642), .B1(n_1_0_635), .B2(registers_5__ap[10]), + .ZN(n_1_0_197) + ); + NAND4_X1_LVT i_1_0_207( + .A1(n_1_0_200), .A2(n_1_0_199), .A3(n_1_0_198), .A4(n_1_0_197), .ZN(n_1_0_196) + ); + AOI22_X1_LVT i_1_0_206( + .A1(registers_1__ap[10]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[10]), + .ZN(n_1_0_195) + ); + AOI22_X1_LVT i_1_0_205( + .A1(registers_14__ap[10]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[10]), + .ZN(n_1_0_194) + ); + AOI22_X1_LVT i_1_0_204( + .A1(registers_19__ap[10]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[10]), + .ZN(n_1_0_193) + ); + AOI22_X1_LVT i_1_0_203( + .A1(registers_27__ap[10]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[10]), + .ZN(n_1_0_192) + ); + NAND4_X1_LVT i_1_0_202( + .A1(n_1_0_195), .A2(n_1_0_194), .A3(n_1_0_193), .A4(n_1_0_192), .ZN(n_1_0_191) + ); + NOR3_X1_LVT i_1_0_201( + .A1(n_1_0_201), .A2(n_1_0_196), .A3(n_1_0_191), .ZN(n_1_0_190) + ); + NAND4_X1_LVT i_1_0_200( + .A1(n_1_0_208), .A2(n_1_0_207), .A3(n_1_0_206), .A4(n_1_0_190), .ZN(RRs2[10]) + ); + AOI22_X1_LVT i_1_0_196( + .A1(registers_13__ap[9]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[9]), + .ZN(n_1_0_186) + ); + AOI22_X1_LVT i_1_0_199( + .A1(registers_29__ap[9]), .A2(n_1_0_649), .B1(n_1_0_636), .B2(registers_27__ap[9]), + .ZN(n_1_0_189) + ); + AOI22_X1_LVT i_1_0_195( + .A1(registers_24__ap[9]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[9]), + .ZN(n_1_0_185) + ); + AOI22_X1_LVT i_1_0_198( + .A1(registers_31__ap[9]), .A2(n_1_0_637), .B1(n_1_0_627), .B2(registers_15__ap[9]), + .ZN(n_1_0_188) + ); + INV_X1_LVT i_1_0_197( + .A(n_1_0_188), .ZN(n_1_0_187) + ); + AOI221_X1_LVT i_1_0_194( + .A(n_1_0_187), .B1(n_1_0_615), .B2(registers_23__ap[9]), .C1(registers_4__ap[9]), + .C2(n_1_0_638), .ZN(n_1_0_184) + ); + AOI222_X1_LVT i_1_0_193( + .A1(registers_18__ap[9]), .A2(n_1_0_646), .B1(n_1_0_624), .B2(registers_10__ap[9]), + .C1(registers_25__ap[9]), .C2(n_1_0_620), .ZN(n_1_0_183) + ); + NAND4_X1_LVT i_1_0_192( + .A1(n_1_0_189), .A2(n_1_0_185), .A3(n_1_0_184), .A4(n_1_0_183), .ZN(n_1_0_182) + ); + AOI221_X1_LVT i_1_0_191( + .A(n_1_0_182), .B1(n_1_0_626), .B2(registers_8__ap[9]), .C1(registers_28__ap[9]), + .C2(n_1_0_634), .ZN(n_1_0_181) + ); + AOI22_X1_LVT i_1_0_190( + .A1(registers_26__ap[9]), .A2(n_1_0_640), .B1(n_1_0_622), .B2(registers_30__ap[9]), + .ZN(n_1_0_180) + ); + AOI22_X1_LVT i_1_0_189( + .A1(registers_12__ap[9]), .A2(n_1_0_632), .B1(n_1_0_629), .B2(registers_17__ap[9]), + .ZN(n_1_0_179) + ); + AOI22_X1_LVT i_1_0_188( + .A1(registers_5__ap[9]), .A2(n_1_0_635), .B1(n_1_0_623), .B2(registers_7__ap[9]), + .ZN(n_1_0_178) + ); + NAND3_X1_LVT i_1_0_187( + .A1(n_1_0_180), .A2(n_1_0_179), .A3(n_1_0_178), .ZN(n_1_0_177) + ); + AOI221_X1_LVT i_1_0_186( + .A(n_1_0_177), .B1(n_1_0_642), .B2(registers_22__ap[9]), .C1(registers_16__ap[9]), + .C2(n_1_0_614), .ZN(n_1_0_176) + ); + AOI22_X1_LVT i_1_0_185( + .A1(registers_1__ap[9]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[9]), + .ZN(n_1_0_175) + ); + AOI22_X1_LVT i_1_0_184( + .A1(registers_14__ap[9]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[9]), + .ZN(n_1_0_174) + ); + AOI22_X1_LVT i_1_0_183( + .A1(registers_19__ap[9]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[9]), + .ZN(n_1_0_173) + ); + NAND3_X1_LVT i_1_0_182( + .A1(n_1_0_175), .A2(n_1_0_174), .A3(n_1_0_173), .ZN(n_1_0_172) + ); + AOI221_X1_LVT i_1_0_181( + .A(n_1_0_172), .B1(n_1_0_611), .B2(registers_11__ap[9]), .C1(registers_2__ap[9]), + .C2(n_1_0_618), .ZN(n_1_0_171) + ); + NAND4_X1_LVT i_1_0_180( + .A1(n_1_0_186), .A2(n_1_0_181), .A3(n_1_0_176), .A4(n_1_0_171), .ZN(RRs2[9]) + ); + AOI22_X1_LVT i_1_0_179( + .A1(registers_28__ap[8]), .A2(n_1_0_634), .B1(n_1_0_629), .B2(registers_17__ap[8]), + .ZN(n_1_0_170) + ); + AOI222_X1_LVT i_1_0_178( + .A1(registers_26__ap[8]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[8]), + .C1(n_1_0_626), .C2(registers_8__ap[8]), .ZN(n_1_0_169) + ); + AOI22_X1_LVT i_1_0_177( + .A1(registers_29__ap[8]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[8]), + .ZN(n_1_0_168) + ); + AOI22_X1_LVT i_1_0_176( + .A1(registers_1__ap[8]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[8]), + .ZN(n_1_0_167) + ); + AOI22_X1_LVT i_1_0_175( + .A1(registers_5__ap[8]), .A2(n_1_0_635), .B1(n_1_0_610), .B2(registers_3__ap[8]), + .ZN(n_1_0_166) + ); + AOI22_X1_LVT i_1_0_174( + .A1(registers_31__ap[8]), .A2(n_1_0_637), .B1(n_1_0_614), .B2(registers_16__ap[8]), + .ZN(n_1_0_165) + ); + AOI22_X1_LVT i_1_0_173( + .A1(registers_15__ap[8]), .A2(n_1_0_627), .B1(n_1_0_615), .B2(registers_23__ap[8]), + .ZN(n_1_0_164) + ); + NAND4_X1_LVT i_1_0_172( + .A1(n_1_0_167), .A2(n_1_0_166), .A3(n_1_0_165), .A4(n_1_0_164), .ZN(n_1_0_163) + ); + AOI22_X1_LVT i_1_0_171( + .A1(registers_18__ap[8]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[8]), + .ZN(n_1_0_162) + ); + AOI22_X1_LVT i_1_0_170( + .A1(registers_4__ap[8]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[8]), + .ZN(n_1_0_161) + ); + AOI22_X1_LVT i_1_0_169( + .A1(registers_22__ap[8]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[8]), + .ZN(n_1_0_160) + ); + AOI22_X1_LVT i_1_0_168( + .A1(registers_12__ap[8]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[8]), + .ZN(n_1_0_159) + ); + NAND4_X1_LVT i_1_0_167( + .A1(n_1_0_162), .A2(n_1_0_161), .A3(n_1_0_160), .A4(n_1_0_159), .ZN(n_1_0_158) + ); + AOI22_X1_LVT i_1_0_166( + .A1(registers_13__ap[8]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[8]), + .ZN(n_1_0_157) + ); + AOI22_X1_LVT i_1_0_165( + .A1(registers_7__ap[8]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[8]), + .ZN(n_1_0_156) + ); + AOI22_X1_LVT i_1_0_164( + .A1(registers_19__ap[8]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[8]), + .ZN(n_1_0_155) + ); + AOI22_X1_LVT i_1_0_163( + .A1(registers_27__ap[8]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[8]), + .ZN(n_1_0_154) + ); + NAND4_X1_LVT i_1_0_162( + .A1(n_1_0_157), .A2(n_1_0_156), .A3(n_1_0_155), .A4(n_1_0_154), .ZN(n_1_0_153) + ); + NOR3_X1_LVT i_1_0_161( + .A1(n_1_0_163), .A2(n_1_0_158), .A3(n_1_0_153), .ZN(n_1_0_152) + ); + NAND4_X1_LVT i_1_0_160( + .A1(n_1_0_170), .A2(n_1_0_169), .A3(n_1_0_168), .A4(n_1_0_152), .ZN(RRs2[8]) + ); + AOI22_X1_LVT i_1_0_159( + .A1(registers_28__ap[7]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[7]), + .ZN(n_1_0_151) + ); + AOI222_X1_LVT i_1_0_158( + .A1(registers_26__ap[7]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[7]), + .C1(registers_25__ap[7]), .C2(n_1_0_620), .ZN(n_1_0_150) + ); + AOI22_X1_LVT i_1_0_157( + .A1(registers_24__ap[7]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[7]), + .ZN(n_1_0_149) + ); + AOI22_X1_LVT i_1_0_156( + .A1(registers_15__ap[7]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[7]), + .ZN(n_1_0_148) + ); + AOI22_X1_LVT i_1_0_155( + .A1(registers_31__ap[7]), .A2(n_1_0_637), .B1(n_1_0_629), .B2(registers_17__ap[7]), + .ZN(n_1_0_147) + ); + AOI22_X1_LVT i_1_0_154( + .A1(registers_29__ap[7]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[7]), + .ZN(n_1_0_146) + ); + NAND4_X1_LVT i_1_0_153( + .A1(n_1_0_149), .A2(n_1_0_148), .A3(n_1_0_147), .A4(n_1_0_146), .ZN(n_1_0_145) + ); + AOI221_X1_LVT i_1_0_152( + .A(n_1_0_145), .B1(n_1_0_612), .B2(registers_21__ap[7]), .C1(registers_13__ap[7]), + .C2(n_1_0_631), .ZN(n_1_0_144) + ); + AOI22_X1_LVT i_1_0_151( + .A1(registers_18__ap[7]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[7]), + .ZN(n_1_0_143) + ); + AOI22_X1_LVT i_1_0_150( + .A1(registers_4__ap[7]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[7]), + .ZN(n_1_0_142) + ); + AOI22_X1_LVT i_1_0_149( + .A1(registers_5__ap[7]), .A2(n_1_0_635), .B1(n_1_0_623), .B2(registers_7__ap[7]), + .ZN(n_1_0_141) + ); + AOI22_X1_LVT i_1_0_148( + .A1(registers_22__ap[7]), .A2(n_1_0_642), .B1(n_1_0_614), .B2(registers_16__ap[7]), + .ZN(n_1_0_140) + ); + NAND4_X1_LVT i_1_0_147( + .A1(n_1_0_143), .A2(n_1_0_142), .A3(n_1_0_141), .A4(n_1_0_140), .ZN(n_1_0_139) + ); + AOI22_X1_LVT i_1_0_146( + .A1(registers_1__ap[7]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[7]), + .ZN(n_1_0_138) + ); + AOI22_X1_LVT i_1_0_145( + .A1(registers_14__ap[7]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[7]), + .ZN(n_1_0_137) + ); + AOI22_X1_LVT i_1_0_144( + .A1(registers_19__ap[7]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[7]), + .ZN(n_1_0_136) + ); + AOI22_X1_LVT i_1_0_143( + .A1(registers_27__ap[7]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[7]), + .ZN(n_1_0_135) + ); + NAND4_X1_LVT i_1_0_142( + .A1(n_1_0_138), .A2(n_1_0_137), .A3(n_1_0_136), .A4(n_1_0_135), .ZN(n_1_0_134) + ); + NOR2_X1_LVT i_1_0_141( + .A1(n_1_0_139), .A2(n_1_0_134), .ZN(n_1_0_133) + ); + NAND4_X1_LVT i_1_0_140( + .A1(n_1_0_151), .A2(n_1_0_150), .A3(n_1_0_144), .A4(n_1_0_133), .ZN(RRs2[7]) + ); + AOI22_X1_LVT i_1_0_136( + .A1(registers_13__ap[6]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[6]), + .ZN(n_1_0_129) + ); + AOI22_X1_LVT i_1_0_139( + .A1(registers_29__ap[6]), .A2(n_1_0_649), .B1(n_1_0_636), .B2(registers_27__ap[6]), + .ZN(n_1_0_132) + ); + AOI22_X1_LVT i_1_0_135( + .A1(registers_24__ap[6]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[6]), + .ZN(n_1_0_128) + ); + AOI22_X1_LVT i_1_0_138( + .A1(registers_31__ap[6]), .A2(n_1_0_637), .B1(n_1_0_627), .B2(registers_15__ap[6]), + .ZN(n_1_0_131) + ); + INV_X1_LVT i_1_0_137( + .A(n_1_0_131), .ZN(n_1_0_130) + ); + AOI221_X1_LVT i_1_0_134( + .A(n_1_0_130), .B1(n_1_0_638), .B2(registers_4__ap[6]), .C1(registers_23__ap[6]), + .C2(n_1_0_615), .ZN(n_1_0_127) + ); + AOI222_X1_LVT i_1_0_133( + .A1(registers_18__ap[6]), .A2(n_1_0_646), .B1(n_1_0_620), .B2(registers_25__ap[6]), + .C1(n_1_0_624), .C2(registers_10__ap[6]), .ZN(n_1_0_126) + ); + NAND4_X1_LVT i_1_0_132( + .A1(n_1_0_132), .A2(n_1_0_128), .A3(n_1_0_127), .A4(n_1_0_126), .ZN(n_1_0_125) + ); + AOI221_X1_LVT i_1_0_131( + .A(n_1_0_125), .B1(n_1_0_626), .B2(registers_8__ap[6]), .C1(registers_28__ap[6]), + .C2(n_1_0_634), .ZN(n_1_0_124) + ); + AOI22_X1_LVT i_1_0_130( + .A1(registers_26__ap[6]), .A2(n_1_0_640), .B1(n_1_0_622), .B2(registers_30__ap[6]), + .ZN(n_1_0_123) + ); + AOI22_X1_LVT i_1_0_129( + .A1(registers_12__ap[6]), .A2(n_1_0_632), .B1(n_1_0_629), .B2(registers_17__ap[6]), + .ZN(n_1_0_122) + ); + AOI22_X1_LVT i_1_0_128( + .A1(registers_7__ap[6]), .A2(n_1_0_623), .B1(n_1_0_614), .B2(registers_16__ap[6]), + .ZN(n_1_0_121) + ); + NAND3_X1_LVT i_1_0_127( + .A1(n_1_0_123), .A2(n_1_0_122), .A3(n_1_0_121), .ZN(n_1_0_120) + ); + AOI221_X1_LVT i_1_0_126( + .A(n_1_0_120), .B1(n_1_0_642), .B2(registers_22__ap[6]), .C1(registers_5__ap[6]), + .C2(n_1_0_635), .ZN(n_1_0_119) + ); + AOI22_X1_LVT i_1_0_125( + .A1(registers_1__ap[6]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[6]), + .ZN(n_1_0_118) + ); + AOI22_X1_LVT i_1_0_124( + .A1(registers_14__ap[6]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[6]), + .ZN(n_1_0_117) + ); + AOI22_X1_LVT i_1_0_123( + .A1(registers_19__ap[6]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[6]), + .ZN(n_1_0_116) + ); + NAND3_X1_LVT i_1_0_122( + .A1(n_1_0_118), .A2(n_1_0_117), .A3(n_1_0_116), .ZN(n_1_0_115) + ); + AOI221_X1_LVT i_1_0_121( + .A(n_1_0_115), .B1(n_1_0_618), .B2(registers_2__ap[6]), .C1(registers_11__ap[6]), + .C2(n_1_0_611), .ZN(n_1_0_114) + ); + NAND4_X1_LVT i_1_0_120( + .A1(n_1_0_129), .A2(n_1_0_124), .A3(n_1_0_119), .A4(n_1_0_114), .ZN(RRs2[6]) + ); + AOI22_X1_LVT i_1_0_118( + .A1(registers_28__ap[5]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[5]), + .ZN(n_1_0_112) + ); + AOI22_X1_LVT i_1_0_119( + .A1(registers_31__ap[5]), .A2(n_1_0_637), .B1(n_1_0_627), .B2(registers_15__ap[5]), + .ZN(n_1_0_113) + ); + AOI22_X1_LVT i_1_0_117( + .A1(registers_24__ap[5]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[5]), + .ZN(n_1_0_111) + ); + AOI22_X1_LVT i_1_0_116( + .A1(registers_17__ap[5]), .A2(n_1_0_629), .B1(n_1_0_615), .B2(registers_23__ap[5]), + .ZN(n_1_0_110) + ); + NAND3_X1_LVT i_1_0_115( + .A1(n_1_0_113), .A2(n_1_0_111), .A3(n_1_0_110), .ZN(n_1_0_109) + ); + AOI221_X1_LVT i_1_0_114( + .A(n_1_0_109), .B1(n_1_0_636), .B2(registers_27__ap[5]), .C1(registers_29__ap[5]), + .C2(n_1_0_649), .ZN(n_1_0_108) + ); + AOI222_X1_LVT i_1_0_113( + .A1(registers_10__ap[5]), .A2(n_1_0_624), .B1(n_1_0_620), .B2(registers_25__ap[5]), + .C1(registers_18__ap[5]), .C2(n_1_0_646), .ZN(n_1_0_107) + ); + NAND3_X1_LVT i_1_0_112( + .A1(n_1_0_112), .A2(n_1_0_108), .A3(n_1_0_107), .ZN(n_1_0_106) + ); + AOI221_X1_LVT i_1_0_111( + .A(n_1_0_106), .B1(n_1_0_612), .B2(registers_21__ap[5]), .C1(registers_13__ap[5]), + .C2(n_1_0_631), .ZN(n_1_0_105) + ); + AOI22_X1_LVT i_1_0_110( + .A1(registers_26__ap[5]), .A2(n_1_0_640), .B1(n_1_0_622), .B2(registers_30__ap[5]), + .ZN(n_1_0_104) + ); + AOI22_X1_LVT i_1_0_109( + .A1(registers_4__ap[5]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[5]), + .ZN(n_1_0_103) + ); + AOI22_X1_LVT i_1_0_108( + .A1(registers_5__ap[5]), .A2(n_1_0_635), .B1(n_1_0_623), .B2(registers_7__ap[5]), + .ZN(n_1_0_102) + ); + NAND3_X1_LVT i_1_0_107( + .A1(n_1_0_104), .A2(n_1_0_103), .A3(n_1_0_102), .ZN(n_1_0_101) + ); + AOI221_X1_LVT i_1_0_106( + .A(n_1_0_101), .B1(n_1_0_642), .B2(registers_22__ap[5]), .C1(registers_16__ap[5]), + .C2(n_1_0_614), .ZN(n_1_0_100) + ); + AOI22_X1_LVT i_1_0_105( + .A1(registers_1__ap[5]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[5]), + .ZN(n_1_0_99) + ); + AOI22_X1_LVT i_1_0_104( + .A1(registers_14__ap[5]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[5]), + .ZN(n_1_0_98) + ); + AOI22_X1_LVT i_1_0_103( + .A1(registers_19__ap[5]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[5]), + .ZN(n_1_0_97) + ); + NAND3_X1_LVT i_1_0_102( + .A1(n_1_0_99), .A2(n_1_0_98), .A3(n_1_0_97), .ZN(n_1_0_96) + ); + AOI221_X1_LVT i_1_0_101( + .A(n_1_0_96), .B1(n_1_0_611), .B2(registers_11__ap[5]), .C1(registers_2__ap[5]), + .C2(n_1_0_618), .ZN(n_1_0_95) + ); + NAND3_X1_LVT i_1_0_100( + .A1(n_1_0_105), .A2(n_1_0_100), .A3(n_1_0_95), .ZN(RRs2[5]) + ); + AOI22_X1_LVT i_1_0_99( + .A1(registers_4__ap[4]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[4]), + .ZN(n_1_0_94) + ); + AOI222_X1_LVT i_1_0_98( + .A1(registers_8__ap[4]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[4]), + .C1(n_1_0_622), .C2(registers_30__ap[4]), .ZN(n_1_0_93) + ); + AOI22_X1_LVT i_1_0_97( + .A1(registers_29__ap[4]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[4]), + .ZN(n_1_0_92) + ); + AOI22_X1_LVT i_1_0_96( + .A1(registers_1__ap[4]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[4]), + .ZN(n_1_0_91) + ); + AOI22_X1_LVT i_1_0_95( + .A1(registers_27__ap[4]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[4]), + .ZN(n_1_0_90) + ); + AOI22_X1_LVT i_1_0_94( + .A1(registers_23__ap[4]), .A2(n_1_0_615), .B1(n_1_0_614), .B2(registers_16__ap[4]), + .ZN(n_1_0_89) + ); + AOI22_X1_LVT i_1_0_93( + .A1(registers_31__ap[4]), .A2(n_1_0_637), .B1(n_1_0_635), .B2(registers_5__ap[4]), + .ZN(n_1_0_88) + ); + NAND4_X1_LVT i_1_0_92( + .A1(n_1_0_91), .A2(n_1_0_90), .A3(n_1_0_89), .A4(n_1_0_88), .ZN(n_1_0_87) + ); + AOI22_X1_LVT i_1_0_91( + .A1(registers_18__ap[4]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[4]), + .ZN(n_1_0_86) + ); + AOI22_X1_LVT i_1_0_90( + .A1(registers_12__ap[4]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[4]), + .ZN(n_1_0_85) + ); + AOI22_X1_LVT i_1_0_89( + .A1(registers_22__ap[4]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[4]), + .ZN(n_1_0_84) + ); + AOI22_X1_LVT i_1_0_88( + .A1(registers_17__ap[4]), .A2(n_1_0_629), .B1(n_1_0_613), .B2(registers_20__ap[4]), + .ZN(n_1_0_83) + ); + NAND4_X1_LVT i_1_0_87( + .A1(n_1_0_86), .A2(n_1_0_85), .A3(n_1_0_84), .A4(n_1_0_83), .ZN(n_1_0_82) + ); + AOI22_X1_LVT i_1_0_86( + .A1(registers_13__ap[4]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[4]), + .ZN(n_1_0_81) + ); + AOI22_X1_LVT i_1_0_85( + .A1(registers_7__ap[4]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[4]), + .ZN(n_1_0_80) + ); + AOI22_X1_LVT i_1_0_84( + .A1(registers_19__ap[4]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[4]), + .ZN(n_1_0_79) + ); + AOI22_X1_LVT i_1_0_83( + .A1(registers_2__ap[4]), .A2(n_1_0_618), .B1(n_1_0_611), .B2(registers_11__ap[4]), + .ZN(n_1_0_78) + ); + NAND4_X1_LVT i_1_0_82( + .A1(n_1_0_81), .A2(n_1_0_80), .A3(n_1_0_79), .A4(n_1_0_78), .ZN(n_1_0_77) + ); + NOR3_X1_LVT i_1_0_81( + .A1(n_1_0_87), .A2(n_1_0_82), .A3(n_1_0_77), .ZN(n_1_0_76) + ); + NAND4_X1_LVT i_1_0_80( + .A1(n_1_0_94), .A2(n_1_0_93), .A3(n_1_0_92), .A4(n_1_0_76), .ZN(RRs2[4]) + ); + AOI22_X1_LVT i_1_0_78( + .A1(registers_29__ap[3]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[3]), + .ZN(n_1_0_74) + ); + AOI22_X1_LVT i_1_0_79( + .A1(registers_27__ap[3]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[3]), + .ZN(n_1_0_75) + ); + AOI22_X1_LVT i_1_0_77( + .A1(registers_1__ap[3]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[3]), + .ZN(n_1_0_73) + ); + AOI22_X1_LVT i_1_0_76( + .A1(registers_5__ap[3]), .A2(n_1_0_635), .B1(n_1_0_611), .B2(registers_11__ap[3]), + .ZN(n_1_0_72) + ); + NAND3_X1_LVT i_1_0_75( + .A1(n_1_0_75), .A2(n_1_0_73), .A3(n_1_0_72), .ZN(n_1_0_71) + ); + AOI221_X1_LVT i_1_0_74( + .A(n_1_0_71), .B1(n_1_0_614), .B2(registers_16__ap[3]), .C1(registers_31__ap[3]), + .C2(n_1_0_637), .ZN(n_1_0_70) + ); + AOI222_X1_LVT i_1_0_73( + .A1(registers_8__ap[3]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[3]), + .C1(n_1_0_622), .C2(registers_30__ap[3]), .ZN(n_1_0_69) + ); + NAND3_X1_LVT i_1_0_72( + .A1(n_1_0_74), .A2(n_1_0_70), .A3(n_1_0_69), .ZN(n_1_0_68) + ); + AOI221_X1_LVT i_1_0_71( + .A(n_1_0_68), .B1(n_1_0_638), .B2(registers_4__ap[3]), .C1(registers_28__ap[3]), + .C2(n_1_0_634), .ZN(n_1_0_67) + ); + AOI22_X1_LVT i_1_0_70( + .A1(registers_18__ap[3]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[3]), + .ZN(n_1_0_66) + ); + AOI22_X1_LVT i_1_0_69( + .A1(registers_12__ap[3]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[3]), + .ZN(n_1_0_65) + ); + AOI22_X1_LVT i_1_0_68( + .A1(registers_22__ap[3]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[3]), + .ZN(n_1_0_64) + ); + NAND3_X1_LVT i_1_0_67( + .A1(n_1_0_66), .A2(n_1_0_65), .A3(n_1_0_64), .ZN(n_1_0_63) + ); + AOI221_X1_LVT i_1_0_66( + .A(n_1_0_63), .B1(n_1_0_613), .B2(registers_20__ap[3]), .C1(registers_17__ap[3]), + .C2(n_1_0_629), .ZN(n_1_0_62) + ); + AOI22_X1_LVT i_1_0_65( + .A1(registers_13__ap[3]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[3]), + .ZN(n_1_0_61) + ); + AOI22_X1_LVT i_1_0_64( + .A1(registers_7__ap[3]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[3]), + .ZN(n_1_0_60) + ); + AOI22_X1_LVT i_1_0_63( + .A1(registers_19__ap[3]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[3]), + .ZN(n_1_0_59) + ); + NAND3_X1_LVT i_1_0_62( + .A1(n_1_0_61), .A2(n_1_0_60), .A3(n_1_0_59), .ZN(n_1_0_58) + ); + AOI221_X1_LVT i_1_0_61( + .A(n_1_0_58), .B1(n_1_0_618), .B2(registers_2__ap[3]), .C1(registers_23__ap[3]), + .C2(n_1_0_615), .ZN(n_1_0_57) + ); + NAND3_X1_LVT i_1_0_60( + .A1(n_1_0_67), .A2(n_1_0_62), .A3(n_1_0_57), .ZN(RRs2[3]) + ); + AOI22_X1_LVT i_1_0_58( + .A1(registers_29__ap[2]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[2]), + .ZN(n_1_0_55) + ); + AOI22_X1_LVT i_1_0_59( + .A1(registers_27__ap[2]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[2]), + .ZN(n_1_0_56) + ); + AOI22_X1_LVT i_1_0_57( + .A1(registers_1__ap[2]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[2]), + .ZN(n_1_0_54) + ); + AOI22_X1_LVT i_1_0_56( + .A1(registers_5__ap[2]), .A2(n_1_0_635), .B1(n_1_0_615), .B2(registers_23__ap[2]), + .ZN(n_1_0_53) + ); + NAND3_X1_LVT i_1_0_55( + .A1(n_1_0_56), .A2(n_1_0_54), .A3(n_1_0_53), .ZN(n_1_0_52) + ); + AOI221_X1_LVT i_1_0_54( + .A(n_1_0_52), .B1(n_1_0_637), .B2(registers_31__ap[2]), .C1(registers_16__ap[2]), + .C2(n_1_0_614), .ZN(n_1_0_51) + ); + AOI222_X1_LVT i_1_0_53( + .A1(registers_8__ap[2]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[2]), + .C1(n_1_0_622), .C2(registers_30__ap[2]), .ZN(n_1_0_50) + ); + NAND3_X1_LVT i_1_0_52( + .A1(n_1_0_55), .A2(n_1_0_51), .A3(n_1_0_50), .ZN(n_1_0_49) + ); + AOI221_X1_LVT i_1_0_51( + .A(n_1_0_49), .B1(n_1_0_638), .B2(registers_4__ap[2]), .C1(registers_28__ap[2]), + .C2(n_1_0_634), .ZN(n_1_0_48) + ); + AOI22_X1_LVT i_1_0_50( + .A1(registers_18__ap[2]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[2]), + .ZN(n_1_0_47) + ); + AOI22_X1_LVT i_1_0_49( + .A1(registers_12__ap[2]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[2]), + .ZN(n_1_0_46) + ); + AOI22_X1_LVT i_1_0_48( + .A1(registers_22__ap[2]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[2]), + .ZN(n_1_0_45) + ); + NAND3_X1_LVT i_1_0_47( + .A1(n_1_0_47), .A2(n_1_0_46), .A3(n_1_0_45), .ZN(n_1_0_44) + ); + AOI221_X1_LVT i_1_0_46( + .A(n_1_0_44), .B1(n_1_0_629), .B2(registers_17__ap[2]), .C1(registers_20__ap[2]), + .C2(n_1_0_613), .ZN(n_1_0_43) + ); + AOI22_X1_LVT i_1_0_45( + .A1(registers_13__ap[2]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[2]), + .ZN(n_1_0_42) + ); + AOI22_X1_LVT i_1_0_44( + .A1(registers_7__ap[2]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[2]), + .ZN(n_1_0_41) + ); + AOI22_X1_LVT i_1_0_43( + .A1(registers_19__ap[2]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[2]), + .ZN(n_1_0_40) + ); + NAND3_X1_LVT i_1_0_42( + .A1(n_1_0_42), .A2(n_1_0_41), .A3(n_1_0_40), .ZN(n_1_0_39) + ); + AOI221_X1_LVT i_1_0_41( + .A(n_1_0_39), .B1(n_1_0_618), .B2(registers_2__ap[2]), .C1(registers_11__ap[2]), + .C2(n_1_0_611), .ZN(n_1_0_38) + ); + NAND3_X1_LVT i_1_0_40( + .A1(n_1_0_48), .A2(n_1_0_43), .A3(n_1_0_38), .ZN(RRs2[2]) + ); + AOI22_X1_LVT i_1_0_38( + .A1(registers_29__ap[1]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[1]), + .ZN(n_1_0_36) + ); + AOI22_X1_LVT i_1_0_39( + .A1(registers_16__ap[1]), .A2(n_1_0_614), .B1(n_1_0_610), .B2(registers_3__ap[1]), + .ZN(n_1_0_37) + ); + AOI22_X1_LVT i_1_0_37( + .A1(registers_1__ap[1]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[1]), + .ZN(n_1_0_35) + ); + AOI22_X1_LVT i_1_0_36( + .A1(registers_31__ap[1]), .A2(n_1_0_637), .B1(n_1_0_635), .B2(registers_5__ap[1]), + .ZN(n_1_0_34) + ); + NAND3_X1_LVT i_1_0_35( + .A1(n_1_0_37), .A2(n_1_0_35), .A3(n_1_0_34), .ZN(n_1_0_33) + ); + AOI221_X1_LVT i_1_0_34( + .A(n_1_0_33), .B1(n_1_0_627), .B2(registers_15__ap[1]), .C1(registers_23__ap[1]), + .C2(n_1_0_615), .ZN(n_1_0_32) + ); + AOI222_X1_LVT i_1_0_33( + .A1(registers_26__ap[1]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[1]), + .C1(n_1_0_626), .C2(registers_8__ap[1]), .ZN(n_1_0_31) + ); + NAND3_X1_LVT i_1_0_32( + .A1(n_1_0_36), .A2(n_1_0_32), .A3(n_1_0_31), .ZN(n_1_0_30) + ); + AOI221_X1_LVT i_1_0_31( + .A(n_1_0_30), .B1(n_1_0_629), .B2(registers_17__ap[1]), .C1(registers_28__ap[1]), + .C2(n_1_0_634), .ZN(n_1_0_29) + ); + AOI22_X1_LVT i_1_0_30( + .A1(registers_18__ap[1]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[1]), + .ZN(n_1_0_28) + ); + AOI22_X1_LVT i_1_0_29( + .A1(registers_4__ap[1]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[1]), + .ZN(n_1_0_27) + ); + AOI22_X1_LVT i_1_0_28( + .A1(registers_22__ap[1]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[1]), + .ZN(n_1_0_26) + ); + NAND3_X1_LVT i_1_0_27( + .A1(n_1_0_28), .A2(n_1_0_27), .A3(n_1_0_26), .ZN(n_1_0_25) + ); + AOI221_X1_LVT i_1_0_26( + .A(n_1_0_25), .B1(n_1_0_632), .B2(registers_12__ap[1]), .C1(registers_24__ap[1]), + .C2(n_1_0_621), .ZN(n_1_0_24) + ); + AOI22_X1_LVT i_1_0_25( + .A1(registers_13__ap[1]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[1]), + .ZN(n_1_0_23) + ); + AOI22_X1_LVT i_1_0_24( + .A1(registers_7__ap[1]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[1]), + .ZN(n_1_0_22) + ); + AOI22_X1_LVT i_1_0_23( + .A1(registers_19__ap[1]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[1]), + .ZN(n_1_0_21) + ); + NAND3_X1_LVT i_1_0_22( + .A1(n_1_0_23), .A2(n_1_0_22), .A3(n_1_0_21), .ZN(n_1_0_20) + ); + AOI221_X1_LVT i_1_0_21( + .A(n_1_0_20), .B1(n_1_0_611), .B2(registers_11__ap[1]), .C1(registers_27__ap[1]), + .C2(n_1_0_636), .ZN(n_1_0_19) + ); + NAND3_X1_LVT i_1_0_20( + .A1(n_1_0_29), .A2(n_1_0_24), .A3(n_1_0_19), .ZN(RRs2[1]) + ); + AOI22_X1_LVT i_1_0_19( + .A1(registers_4__ap[0]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[0]), + .ZN(n_1_0_18) + ); + AOI222_X1_LVT i_1_0_18( + .A1(registers_8__ap[0]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[0]), + .C1(n_1_0_622), .C2(registers_30__ap[0]), .ZN(n_1_0_17) + ); + AOI22_X1_LVT i_1_0_17( + .A1(registers_29__ap[0]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[0]), + .ZN(n_1_0_16) + ); + AOI22_X1_LVT i_1_0_16( + .A1(registers_1__ap[0]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[0]), + .ZN(n_1_0_15) + ); + AOI22_X1_LVT i_1_0_15( + .A1(registers_27__ap[0]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[0]), + .ZN(n_1_0_14) + ); + AOI22_X1_LVT i_1_0_14( + .A1(registers_23__ap[0]), .A2(n_1_0_615), .B1(n_1_0_614), .B2(registers_16__ap[0]), + .ZN(n_1_0_13) + ); + AOI22_X1_LVT i_1_0_13( + .A1(registers_31__ap[0]), .A2(n_1_0_637), .B1(n_1_0_635), .B2(registers_5__ap[0]), + .ZN(n_1_0_12) + ); + NAND4_X1_LVT i_1_0_12( + .A1(n_1_0_15), .A2(n_1_0_14), .A3(n_1_0_13), .A4(n_1_0_12), .ZN(n_1_0_11) + ); + AOI22_X1_LVT i_1_0_11( + .A1(registers_18__ap[0]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[0]), + .ZN(n_1_0_10) + ); + AOI22_X1_LVT i_1_0_10( + .A1(registers_12__ap[0]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[0]), + .ZN(n_1_0_9) + ); + AOI22_X1_LVT i_1_0_9( + .A1(registers_22__ap[0]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[0]), + .ZN(n_1_0_8) + ); + AOI22_X1_LVT i_1_0_8( + .A1(registers_17__ap[0]), .A2(n_1_0_629), .B1(n_1_0_613), .B2(registers_20__ap[0]), + .ZN(n_1_0_7) + ); + NAND4_X1_LVT i_1_0_7( + .A1(n_1_0_10), .A2(n_1_0_9), .A3(n_1_0_8), .A4(n_1_0_7), .ZN(n_1_0_6) + ); + AOI22_X1_LVT i_1_0_6( + .A1(registers_13__ap[0]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[0]), + .ZN(n_1_0_5) + ); + AOI22_X1_LVT i_1_0_5( + .A1(registers_7__ap[0]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[0]), + .ZN(n_1_0_4) + ); + AOI22_X1_LVT i_1_0_4( + .A1(registers_19__ap[0]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[0]), + .ZN(n_1_0_3) + ); + AOI22_X1_LVT i_1_0_3( + .A1(registers_2__ap[0]), .A2(n_1_0_618), .B1(n_1_0_611), .B2(registers_11__ap[0]), + .ZN(n_1_0_2) + ); + NAND4_X1_LVT i_1_0_2( + .A1(n_1_0_5), .A2(n_1_0_4), .A3(n_1_0_3), .A4(n_1_0_2), .ZN(n_1_0_1) + ); + NOR3_X1_LVT i_1_0_1( + .A1(n_1_0_11), .A2(n_1_0_6), .A3(n_1_0_1), .ZN(n_1_0_0) + ); + NAND4_X1_LVT i_1_0_0( + .A1(n_1_0_18), .A2(n_1_0_17), .A3(n_1_0_16), .A4(n_1_0_0), .ZN(RRs2[0]) + ); + DLL_X2_LVT ts_lockup_latchn_clkc2_intno1050_i( + .D(registers_1__ap[0]), .GN(n_0_0), .Q(ts_no1050) + ); + DLL_X2_LVT ts_lockup_latchn_clkc4_intno1051_i( + .D(registers_6__ap[0]), .GN(n_0_36), .Q(ts_no1051) + ); + DLL_X2_LVT ts_lockup_latchn_clkc3_intno1053_i( + .D(registers_27__ap[0]), .GN(n_0_57), .Q(ts_no1053) + ); + DLL_X2_LVT ts_lockup_latchn_clkc1_intno1054_i( + .D(registers_11__ap[0]), .GN(n_0_41), .Q(ts_no1054) + ); + CLKBUF_X3_LVT tessent_persistent_cell_buf_extsi1227_i( + .A(ts_extsi1227), .Z(ts_pbuf_extsi1227_) + ); + CLKBUF_X3_LVT tessent_persistent_cell_buf_extsi1228_i( + .A(ts_extsi1228), .Z(ts_pbuf_extsi1228_) + ); + CLKBUF_X3_LVT tessent_persistent_cell_buf_extsi1226_i( + .A(ts_extsi1226), .Z(ts_pbuf_extsi1226_) + ); +endmodule + +module cpu(led, btn, clk_25mhz, scan_en, SI_1, SO_1, SI_2, SO_2, SI_3, SO_3, SI_4, + SO_4); + input [6:0] btn; + input clk_25mhz, scan_en, SI_1, SI_2, SI_3, SI_4; + output [7:0] led; + output SO_1, SO_2, SO_3, SO_4; + + wire [31:0] Instruction, RData, RRs2, RRs1, WRd, DAddr, JumpOrBranchPC, + CurrentPC, NextPC; + wire [1:0] DWidth; + wire WrReg, JumpOrBranch, thePC_n_1, thePC_i_0_n_0, thePC_n_2, thePC_i_0_n_1, + thePC_n_3, thePC_i_0_n_2, thePC_n_4, thePC_i_0_n_3, thePC_n_5, + thePC_i_0_n_4, thePC_n_6, thePC_i_0_n_5, thePC_n_7, thePC_i_0_n_6, + thePC_n_8, thePC_i_0_n_7, thePC_n_9, thePC_i_0_n_8, thePC_n_10, + thePC_i_0_n_9, thePC_n_11, thePC_i_0_n_10, thePC_n_12, thePC_i_0_n_11, + thePC_n_13, thePC_i_0_n_12, thePC_n_14, thePC_i_0_n_13, thePC_n_15, + thePC_i_0_n_14, thePC_n_16, thePC_i_0_n_15, thePC_n_17, thePC_i_0_n_16, + thePC_n_18, thePC_i_0_n_17, thePC_n_19, thePC_i_0_n_18, thePC_n_20, + thePC_i_0_n_19, thePC_n_21, thePC_i_0_n_20, thePC_n_22, thePC_i_0_n_21, + thePC_n_23, thePC_i_0_n_22, thePC_n_24, thePC_i_0_n_23, thePC_n_25, + thePC_i_0_n_24, thePC_n_26, thePC_i_0_n_25, thePC_n_27, thePC_i_0_n_26, + thePC_n_28, thePC_i_0_n_27, thePC_n_29, thePC_n_0, thePC_n_30, n_0_0_0, + thePC_n_31, n_0_0_1, thePC_n_32, thePC_n_33, thePC_n_34, thePC_n_35, + thePC_n_36, thePC_n_37, thePC_n_38, thePC_n_39, thePC_n_40, thePC_n_41, + thePC_n_42, thePC_n_43, n_0_0_2, thePC_n_44, n_0_0_3, thePC_n_45, + n_0_0_4, thePC_n_46, n_0_0_5, thePC_n_47, n_0_0_6, thePC_n_48, n_0_0_7, + thePC_n_49, n_0_0_8, thePC_n_50, n_0_0_9, thePC_n_51, n_0_0_10, + thePC_n_52, n_0_0_11, thePC_n_53, n_0_0_12, thePC_n_54, n_0_0_13, + thePC_n_55, n_0_0_14, thePC_n_56, n_0_0_15, thePC_n_57, n_0_0_16, + thePC_n_58, n_0_0_17, thePC_n_59, n_0_0_18, thePC_n_60, n_0_0_19, + thePC_n_61, n_0_0_20, n_0_0_21, n_0_0_22, reset, uc_0, uc_1, uc_2, uc_3, + uc_4, uc_5, uc_6, uc_7, uc_8, uc_9, uc_10, uc_11, uc_12, uc_13, uc_14, + uc_15, uc_16, uc_17, uc_18, uc_19, uc_20, uc_21, uc_22, uc_23, uc_24, + uc_25, uc_26, uc_27, uc_28, uc_29, uc_30, uc_31, uc_32, uc_33, uc_34, + uc_35, uc_36, uc_37, uc_38, uc_39, uc_40, uc_41, uc_42, uc_43, uc_44, + uc_45, uc_46, uc_47, uc_48, uc_49, uc_50, uc_51, uc_52, uc_53, uc_54, + uc_55, uc_56, uc_57, uc_58, ts_pbuf_extsi1225_, ts_no1054, ts_no1050, + ts_no1053, ts_no1051; + + assign SO_1 = ts_no1054; + assign SO_2 = ts_no1050; + assign SO_3 = ts_no1053; + assign SO_4 = ts_no1051; + AND2_X1_LVT i_0_0_54( + .A1(JumpOrBranch), .A2(btn[0]), .ZN(n_0_0_22) + ); + INV_X1_LVT i_0_0_66( + .A(btn[0]), .ZN(reset) + ); + NOR2_X1_LVT i_0_0_53( + .A1(reset), .A2(JumpOrBranch), .ZN(n_0_0_21) + ); + AOI22_X1_LVT i_0_0_50( + .A1(JumpOrBranchPC[30]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_28), .ZN(n_0_0_19) + ); + INV_X1_LVT i_0_0_49( + .A(n_0_0_19), .ZN(thePC_n_60) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[30] ( + .CK(clk_25mhz), .D(thePC_n_60), .Q(CurrentPC[30]), .QN(), .SE(scan_en), .SI(ts_pbuf_extsi1225_) + ); + AOI22_X1_LVT i_0_0_48( + .A1(JumpOrBranchPC[29]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_27), .ZN(n_0_0_18) + ); + INV_X1_LVT i_0_0_47( + .A(n_0_0_18), .ZN(thePC_n_59) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[29] ( + .CK(clk_25mhz), .D(thePC_n_59), .Q(CurrentPC[29]), .QN(), .SE(scan_en), .SI(CurrentPC[30]) + ); + AOI22_X1_LVT i_0_0_46( + .A1(JumpOrBranchPC[28]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_26), .ZN(n_0_0_17) + ); + INV_X1_LVT i_0_0_45( + .A(n_0_0_17), .ZN(thePC_n_58) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[28] ( + .CK(clk_25mhz), .D(thePC_n_58), .Q(CurrentPC[28]), .QN(), .SE(scan_en), .SI(CurrentPC[29]) + ); + AOI22_X1_LVT i_0_0_44( + .A1(JumpOrBranchPC[27]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_25), .ZN(n_0_0_16) + ); + INV_X1_LVT i_0_0_43( + .A(n_0_0_16), .ZN(thePC_n_57) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[27] ( + .CK(clk_25mhz), .D(thePC_n_57), .Q(CurrentPC[27]), .QN(), .SE(scan_en), .SI(CurrentPC[28]) + ); + AOI22_X1_LVT i_0_0_42( + .A1(JumpOrBranchPC[26]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_24), .ZN(n_0_0_15) + ); + INV_X1_LVT i_0_0_41( + .A(n_0_0_15), .ZN(thePC_n_56) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[26] ( + .CK(clk_25mhz), .D(thePC_n_56), .Q(CurrentPC[26]), .QN(), .SE(scan_en), .SI(CurrentPC[27]) + ); + AOI22_X1_LVT i_0_0_40( + .A1(JumpOrBranchPC[25]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_23), .ZN(n_0_0_14) + ); + INV_X1_LVT i_0_0_39( + .A(n_0_0_14), .ZN(thePC_n_55) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[25] ( + .CK(clk_25mhz), .D(thePC_n_55), .Q(CurrentPC[25]), .QN(), .SE(scan_en), .SI(CurrentPC[26]) + ); + AOI22_X1_LVT i_0_0_38( + .A1(JumpOrBranchPC[24]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_22), .ZN(n_0_0_13) + ); + INV_X1_LVT i_0_0_37( + .A(n_0_0_13), .ZN(thePC_n_54) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[24] ( + .CK(clk_25mhz), .D(thePC_n_54), .Q(CurrentPC[24]), .QN(), .SE(scan_en), .SI(CurrentPC[25]) + ); + AOI22_X1_LVT i_0_0_36( + .A1(JumpOrBranchPC[23]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_21), .ZN(n_0_0_12) + ); + INV_X1_LVT i_0_0_35( + .A(n_0_0_12), .ZN(thePC_n_53) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[23] ( + .CK(clk_25mhz), .D(thePC_n_53), .Q(CurrentPC[23]), .QN(), .SE(scan_en), .SI(CurrentPC[24]) + ); + AOI22_X1_LVT i_0_0_34( + .A1(JumpOrBranchPC[22]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_20), .ZN(n_0_0_11) + ); + INV_X1_LVT i_0_0_33( + .A(n_0_0_11), .ZN(thePC_n_52) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[22] ( + .CK(clk_25mhz), .D(thePC_n_52), .Q(CurrentPC[22]), .QN(), .SE(scan_en), .SI(CurrentPC[23]) + ); + AOI22_X1_LVT i_0_0_32( + .A1(JumpOrBranchPC[21]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_19), .ZN(n_0_0_10) + ); + INV_X1_LVT i_0_0_31( + .A(n_0_0_10), .ZN(thePC_n_51) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[21] ( + .CK(clk_25mhz), .D(thePC_n_51), .Q(CurrentPC[21]), .QN(), .SE(scan_en), .SI(CurrentPC[22]) + ); + AOI22_X1_LVT i_0_0_30( + .A1(JumpOrBranchPC[20]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_18), .ZN(n_0_0_9) + ); + INV_X1_LVT i_0_0_29( + .A(n_0_0_9), .ZN(thePC_n_50) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[20] ( + .CK(clk_25mhz), .D(thePC_n_50), .Q(CurrentPC[20]), .QN(), .SE(scan_en), .SI(CurrentPC[21]) + ); + AOI22_X1_LVT i_0_0_28( + .A1(JumpOrBranchPC[19]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_17), .ZN(n_0_0_8) + ); + INV_X1_LVT i_0_0_27( + .A(n_0_0_8), .ZN(thePC_n_49) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[19] ( + .CK(clk_25mhz), .D(thePC_n_49), .Q(CurrentPC[19]), .QN(), .SE(scan_en), .SI(CurrentPC[20]) + ); + AOI22_X1_LVT i_0_0_26( + .A1(JumpOrBranchPC[18]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_16), .ZN(n_0_0_7) + ); + INV_X1_LVT i_0_0_25( + .A(n_0_0_7), .ZN(thePC_n_48) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[18] ( + .CK(clk_25mhz), .D(thePC_n_48), .Q(CurrentPC[18]), .QN(), .SE(scan_en), .SI(CurrentPC[19]) + ); + AOI22_X1_LVT i_0_0_24( + .A1(JumpOrBranchPC[17]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_15), .ZN(n_0_0_6) + ); + INV_X1_LVT i_0_0_23( + .A(n_0_0_6), .ZN(thePC_n_47) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[17] ( + .CK(clk_25mhz), .D(thePC_n_47), .Q(CurrentPC[17]), .QN(), .SE(scan_en), .SI(CurrentPC[18]) + ); + AOI22_X1_LVT i_0_0_22( + .A1(JumpOrBranchPC[16]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_14), .ZN(n_0_0_5) + ); + INV_X1_LVT i_0_0_21( + .A(n_0_0_5), .ZN(thePC_n_46) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[16] ( + .CK(clk_25mhz), .D(thePC_n_46), .Q(CurrentPC[16]), .QN(), .SE(scan_en), .SI(CurrentPC[17]) + ); + AOI22_X1_LVT i_0_0_20( + .A1(JumpOrBranchPC[15]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_13), .ZN(n_0_0_4) + ); + INV_X1_LVT i_0_0_19( + .A(n_0_0_4), .ZN(thePC_n_45) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[15] ( + .CK(clk_25mhz), .D(thePC_n_45), .Q(CurrentPC[15]), .QN(), .SE(scan_en), .SI(CurrentPC[16]) + ); + AOI22_X1_LVT i_0_0_18( + .A1(JumpOrBranchPC[14]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_12), .ZN(n_0_0_3) + ); + INV_X1_LVT i_0_0_17( + .A(n_0_0_3), .ZN(thePC_n_44) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[14] ( + .CK(clk_25mhz), .D(thePC_n_44), .Q(CurrentPC[14]), .QN(), .SE(scan_en), .SI(CurrentPC[15]) + ); + AOI22_X1_LVT i_0_0_16( + .A1(JumpOrBranchPC[13]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_11), .ZN(n_0_0_2) + ); + INV_X1_LVT i_0_0_15( + .A(n_0_0_2), .ZN(thePC_n_43) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[13] ( + .CK(clk_25mhz), .D(thePC_n_43), .Q(CurrentPC[13]), .QN(), .SE(scan_en), .SI(CurrentPC[14]) + ); + MUX2_X1_LVT i_0_0_65( + .A(thePC_n_10), .B(JumpOrBranchPC[12]), .S(JumpOrBranch), .Z(NextPC[12]) + ); + AND2_X1_LVT i_0_0_14( + .A1(NextPC[12]), .A2(btn[0]), .ZN(thePC_n_42) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[12] ( + .CK(clk_25mhz), .D(thePC_n_42), .Q(CurrentPC[12]), .QN(), .SE(scan_en), .SI(CurrentPC[13]) + ); + MUX2_X1_LVT i_0_0_64( + .A(thePC_n_9), .B(JumpOrBranchPC[11]), .S(JumpOrBranch), .Z(NextPC[11]) + ); + AND2_X1_LVT i_0_0_13( + .A1(NextPC[11]), .A2(btn[0]), .ZN(thePC_n_41) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[11] ( + .CK(clk_25mhz), .D(thePC_n_41), .Q(CurrentPC[11]), .QN(), .SE(scan_en), .SI(CurrentPC[12]) + ); + MUX2_X1_LVT i_0_0_63( + .A(thePC_n_8), .B(JumpOrBranchPC[10]), .S(JumpOrBranch), .Z(NextPC[10]) + ); + AND2_X1_LVT i_0_0_12( + .A1(NextPC[10]), .A2(btn[0]), .ZN(thePC_n_40) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[10] ( + .CK(clk_25mhz), .D(thePC_n_40), .Q(CurrentPC[10]), .QN(), .SE(scan_en), .SI(CurrentPC[11]) + ); + MUX2_X1_LVT i_0_0_62( + .A(thePC_n_7), .B(JumpOrBranchPC[9]), .S(JumpOrBranch), .Z(NextPC[9]) + ); + AND2_X1_LVT i_0_0_11( + .A1(NextPC[9]), .A2(btn[0]), .ZN(thePC_n_39) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[9] ( + .CK(clk_25mhz), .D(thePC_n_39), .Q(CurrentPC[9]), .QN(), .SE(scan_en), .SI(CurrentPC[10]) + ); + MUX2_X1_LVT i_0_0_61( + .A(thePC_n_6), .B(JumpOrBranchPC[8]), .S(JumpOrBranch), .Z(NextPC[8]) + ); + AND2_X1_LVT i_0_0_10( + .A1(NextPC[8]), .A2(btn[0]), .ZN(thePC_n_38) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[8] ( + .CK(clk_25mhz), .D(thePC_n_38), .Q(CurrentPC[8]), .QN(), .SE(scan_en), .SI(CurrentPC[9]) + ); + AND2_X1_LVT i_0_0_9( + .A1(led[7]), .A2(btn[0]), .ZN(thePC_n_37) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[7] ( + .CK(clk_25mhz), .D(thePC_n_37), .Q(CurrentPC[7]), .QN(), .SE(scan_en), .SI(CurrentPC[8]) + ); + MUX2_X1_LVT i_0_0_59( + .A(thePC_n_4), .B(JumpOrBranchPC[6]), .S(JumpOrBranch), .Z(led[6]) + ); + AND2_X1_LVT i_0_0_8( + .A1(led[6]), .A2(btn[0]), .ZN(thePC_n_36) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[6] ( + .CK(clk_25mhz), .D(thePC_n_36), .Q(CurrentPC[6]), .QN(), .SE(scan_en), .SI(CurrentPC[7]) + ); + MUX2_X1_LVT i_0_0_58( + .A(thePC_n_3), .B(JumpOrBranchPC[5]), .S(JumpOrBranch), .Z(led[5]) + ); + AND2_X1_LVT i_0_0_7( + .A1(led[5]), .A2(btn[0]), .ZN(thePC_n_35) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[5] ( + .CK(clk_25mhz), .D(thePC_n_35), .Q(CurrentPC[5]), .QN(), .SE(scan_en), .SI(CurrentPC[6]) + ); + MUX2_X1_LVT i_0_0_57( + .A(thePC_n_2), .B(JumpOrBranchPC[4]), .S(JumpOrBranch), .Z(led[4]) + ); + AND2_X1_LVT i_0_0_6( + .A1(led[4]), .A2(btn[0]), .ZN(thePC_n_34) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[4] ( + .CK(clk_25mhz), .D(thePC_n_34), .Q(CurrentPC[4]), .QN(), .SE(scan_en), .SI(CurrentPC[5]) + ); + MUX2_X1_LVT i_0_0_56( + .A(thePC_n_1), .B(JumpOrBranchPC[3]), .S(JumpOrBranch), .Z(led[3]) + ); + AND2_X1_LVT i_0_0_5( + .A1(led[3]), .A2(btn[0]), .ZN(thePC_n_33) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[3] ( + .CK(clk_25mhz), .D(thePC_n_33), .Q(CurrentPC[3]), .QN(), .SE(scan_en), .SI(CurrentPC[4]) + ); + INV_X1_LVT thePC_i_0_29( + .A(CurrentPC[2]), .ZN(thePC_n_0) + ); + MUX2_X1_LVT i_0_0_55( + .A(thePC_n_0), .B(JumpOrBranchPC[2]), .S(JumpOrBranch), .Z(led[2]) + ); + AND2_X1_LVT i_0_0_4( + .A1(led[2]), .A2(btn[0]), .ZN(thePC_n_32) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[2] ( + .CK(clk_25mhz), .D(thePC_n_32), .Q(CurrentPC[2]), .QN(), .SE(scan_en), .SI(CurrentPC[3]) + ); + HA_X1_LVT thePC_i_0_0( + .A(CurrentPC[3]), .B(CurrentPC[2]), .CO(thePC_i_0_n_0), .S(thePC_n_1) + ); + HA_X1_LVT thePC_i_0_1( + .A(CurrentPC[4]), .B(thePC_i_0_n_0), .CO(thePC_i_0_n_1), .S(thePC_n_2) + ); + HA_X1_LVT thePC_i_0_2( + .A(CurrentPC[5]), .B(thePC_i_0_n_1), .CO(thePC_i_0_n_2), .S(thePC_n_3) + ); + HA_X1_LVT thePC_i_0_3( + .A(CurrentPC[6]), .B(thePC_i_0_n_2), .CO(thePC_i_0_n_3), .S(thePC_n_4) + ); + HA_X1_LVT thePC_i_0_4( + .A(CurrentPC[7]), .B(thePC_i_0_n_3), .CO(thePC_i_0_n_4), .S(thePC_n_5) + ); + HA_X1_LVT thePC_i_0_5( + .A(CurrentPC[8]), .B(thePC_i_0_n_4), .CO(thePC_i_0_n_5), .S(thePC_n_6) + ); + HA_X1_LVT thePC_i_0_6( + .A(CurrentPC[9]), .B(thePC_i_0_n_5), .CO(thePC_i_0_n_6), .S(thePC_n_7) + ); + HA_X1_LVT thePC_i_0_7( + .A(CurrentPC[10]), .B(thePC_i_0_n_6), .CO(thePC_i_0_n_7), .S(thePC_n_8) + ); + HA_X1_LVT thePC_i_0_8( + .A(CurrentPC[11]), .B(thePC_i_0_n_7), .CO(thePC_i_0_n_8), .S(thePC_n_9) + ); + HA_X1_LVT thePC_i_0_9( + .A(CurrentPC[12]), .B(thePC_i_0_n_8), .CO(thePC_i_0_n_9), .S(thePC_n_10) + ); + HA_X1_LVT thePC_i_0_11( + .A(CurrentPC[13]), .B(thePC_i_0_n_9), .CO(thePC_i_0_n_10), .S(thePC_n_11) + ); + HA_X1_LVT thePC_i_0_12( + .A(CurrentPC[14]), .B(thePC_i_0_n_10), .CO(thePC_i_0_n_11), .S(thePC_n_12) + ); + HA_X1_LVT thePC_i_0_13( + .A(CurrentPC[15]), .B(thePC_i_0_n_11), .CO(thePC_i_0_n_12), .S(thePC_n_13) + ); + HA_X1_LVT thePC_i_0_14( + .A(CurrentPC[16]), .B(thePC_i_0_n_12), .CO(thePC_i_0_n_13), .S(thePC_n_14) + ); + HA_X1_LVT thePC_i_0_15( + .A(CurrentPC[17]), .B(thePC_i_0_n_13), .CO(thePC_i_0_n_14), .S(thePC_n_15) + ); + HA_X1_LVT thePC_i_0_16( + .A(CurrentPC[18]), .B(thePC_i_0_n_14), .CO(thePC_i_0_n_15), .S(thePC_n_16) + ); + HA_X1_LVT thePC_i_0_17( + .A(CurrentPC[19]), .B(thePC_i_0_n_15), .CO(thePC_i_0_n_16), .S(thePC_n_17) + ); + HA_X1_LVT thePC_i_0_10( + .A(CurrentPC[20]), .B(thePC_i_0_n_16), .CO(thePC_i_0_n_17), .S(thePC_n_18) + ); + HA_X1_LVT thePC_i_0_18( + .A(CurrentPC[21]), .B(thePC_i_0_n_17), .CO(thePC_i_0_n_18), .S(thePC_n_19) + ); + HA_X1_LVT thePC_i_0_19( + .A(CurrentPC[22]), .B(thePC_i_0_n_18), .CO(thePC_i_0_n_19), .S(thePC_n_20) + ); + HA_X1_LVT thePC_i_0_20( + .A(CurrentPC[23]), .B(thePC_i_0_n_19), .CO(thePC_i_0_n_20), .S(thePC_n_21) + ); + HA_X1_LVT thePC_i_0_21( + .A(CurrentPC[24]), .B(thePC_i_0_n_20), .CO(thePC_i_0_n_21), .S(thePC_n_22) + ); + HA_X1_LVT thePC_i_0_22( + .A(CurrentPC[25]), .B(thePC_i_0_n_21), .CO(thePC_i_0_n_22), .S(thePC_n_23) + ); + HA_X1_LVT thePC_i_0_23( + .A(CurrentPC[26]), .B(thePC_i_0_n_22), .CO(thePC_i_0_n_23), .S(thePC_n_24) + ); + HA_X1_LVT thePC_i_0_24( + .A(CurrentPC[27]), .B(thePC_i_0_n_23), .CO(thePC_i_0_n_24), .S(thePC_n_25) + ); + HA_X1_LVT thePC_i_0_25( + .A(CurrentPC[28]), .B(thePC_i_0_n_24), .CO(thePC_i_0_n_25), .S(thePC_n_26) + ); + HA_X1_LVT thePC_i_0_26( + .A(CurrentPC[29]), .B(thePC_i_0_n_25), .CO(thePC_i_0_n_26), .S(thePC_n_27) + ); + HA_X1_LVT thePC_i_0_27( + .A(CurrentPC[30]), .B(thePC_i_0_n_26), .CO(thePC_i_0_n_27), .S(thePC_n_28) + ); + XOR2_X1_LVT thePC_i_0_28( + .A(CurrentPC[31]), .B(thePC_i_0_n_27), .Z(thePC_n_29) + ); + AOI22_X1_LVT i_0_0_52( + .A1(JumpOrBranchPC[31]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_29), .ZN(n_0_0_20) + ); + INV_X1_LVT i_0_0_51( + .A(n_0_0_20), .ZN(thePC_n_61) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[31] ( + .CK(clk_25mhz), .D(thePC_n_61), .Q(CurrentPC[31]), .QN(), .SE(scan_en), .SI(CurrentPC[2]) + ); + AOI22_X1_LVT i_0_0_3( + .A1(JumpOrBranchPC[1]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(CurrentPC[1]), + .ZN(n_0_0_1) + ); + INV_X1_LVT i_0_0_2( + .A(n_0_0_1), .ZN(thePC_n_31) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[1] ( + .CK(clk_25mhz), .D(thePC_n_31), .Q(CurrentPC[1]), .QN(), .SE(scan_en), .SI(CurrentPC[31]) + ); + AOI22_X1_LVT i_0_0_1( + .A1(JumpOrBranchPC[0]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(CurrentPC[0]), + .ZN(n_0_0_0) + ); + INV_X1_LVT i_0_0_0( + .A(n_0_0_0), .ZN(thePC_n_30) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[0] ( + .CK(clk_25mhz), .D(thePC_n_30), .Q(CurrentPC[0]), .QN(), .SE(scan_en), .SI(CurrentPC[1]) + ); + reg_file theRegisters( + .Rs1({Instruction[19], Instruction[18], Instruction[17], + Instruction[16], Instruction[15]}), .Rs2({Instruction[24], + Instruction[23], Instruction[22], Instruction[21], Instruction[20]}), .Rd({ + Instruction[11], Instruction[10], Instruction[9], Instruction[8], + Instruction[7]}), .RRs1(RRs1), .RRs2(RRs2), .WRd(WRd), .WrReg(WrReg), .reset(reset), + .clk(clk_25mhz), .dftIn(scan_en), .ts_intno31(CurrentPC[0]), .ts_no1050(ts_no1050), + .ts_no1051(ts_no1051), .ts_no1053(ts_no1053), .ts_no1054(ts_no1054), .ts_extsi1226(SI_2), + .ts_extsi1227(SI_3), .ts_extsi1228(SI_4) + ); + main_mem theMem( + .clk(clk_25mhz), .reset(reset), .DAddr({uc_0, uc_1, uc_2, uc_3, uc_4, + uc_5, uc_6, uc_7, uc_8, uc_9, uc_10, uc_11, uc_12, uc_13, uc_14, uc_15, + uc_16, uc_17, uc_18, DAddr[12], DAddr[11], DAddr[10], DAddr[9], + DAddr[8], DAddr[7], DAddr[6], DAddr[5], DAddr[4], DAddr[3], DAddr[2], + DAddr[1], DAddr[0]}), .IAddr({uc_19, uc_20, uc_21, uc_22, uc_23, uc_24, + uc_25, uc_26, uc_27, uc_28, uc_29, uc_30, uc_31, uc_32, uc_33, uc_34, + uc_35, uc_36, uc_37, NextPC[12], NextPC[11], NextPC[10], NextPC[9], + NextPC[8], led[7], led[6], led[5], led[4], led[3], led[2], uc_38, uc_39}), + .DWData(RRs2), .DRData(RData), .IRData(Instruction), .DWE(led[1]), .DWidth(DWidth) + ); + decoder theDecoder( + .CurrentPC(CurrentPC), .JumpOrBranchPC(JumpOrBranchPC), .JumpOrBranch(JumpOrBranch), + .DAddr({uc_40, uc_41, uc_42, uc_43, uc_44, uc_45, uc_46, uc_47, uc_48, + uc_49, uc_50, uc_51, uc_52, uc_53, uc_54, uc_55, uc_56, uc_57, uc_58, + DAddr[12], DAddr[11], DAddr[10], DAddr[9], DAddr[8], DAddr[7], DAddr[6], + DAddr[5], DAddr[4], DAddr[3], DAddr[2], DAddr[1], DAddr[0]}), .WData(), .RData(RData), + .Instruction(Instruction), .WrMem(led[1]), .DWidth(DWidth), .Rs1(), .Rs2(), + .Rd(), .RRs1(RRs1), .RRs2(RRs2), .WRd(WRd), .WrReg(WrReg), .Illegal(led[0]) + ); + MUX2_X1_LVT i_0_0_60( + .A(thePC_n_5), .B(JumpOrBranchPC[7]), .S(JumpOrBranch), .Z(led[7]) + ); + CLKBUF_X3_LVT tessent_persistent_cell_buf_extsi1225_i( + .A(SI_1), .Z(ts_pbuf_extsi1225_) + ); +endmodule + diff --git a/oasys.tessent.03/Scan_0/scan.do b/oasys.tessent.03/Scan_0/scan.do new file mode 100644 index 0000000..d0dbc55 --- /dev/null +++ b/oasys.tessent.03/Scan_0/scan.do @@ -0,0 +1,57 @@ +set_context dft -scan -no_rtl -design_id Scan_0 +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_low_temp_ccs.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_low_temp_ccs.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/PLL.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/IO.fslib +set_module_matching_options -suffix_pattern_list {{[_]+[0-9]+[_]+[0-9]+}} -regexp -append +set_module_matching_options -suffix_pattern_list {{[_]+[A-Z]+}} -regexp -append +set_module_matching_options -suffix_pattern_list {{[_]+[0-9]+[_]+[0-9]+[_]+[A-Z]+}} -regexp -append +read_verilog /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.03/Scan_0/oasys_netlist.v +set_tsdb_output_directory /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.03/tsdb_outdir +if { [info exists ::env(OASYS_TCD_SCAN_FOLDER)] } { +set_design_sources -format tcd_scan -Y $::env(OASYS_TCD_SCAN_FOLDER) -extensions tcd_scan +} +read_sdc /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.03/Scan_0/oasys.sdc +set_current_design cpu -show_elaboration_warnings +set_design_level physical_block +set_shift_register_identification off + +add_nonscan_instances -instances {{/theMem/\IRData_reg[31] } {/theMem/\IRData_reg[30] } {/theMem/\IRData_reg[29] } {/theMem/\IRData_reg[28] } {/theMem/\IRData_reg[27] } {/theMem/\IRData_reg[26] } {/theMem/\IRData_reg[25] } {/theMem/\IRData_reg[24] } {/theMem/\IRData_reg[23] } {/theMem/\IRData_reg[22] } {/theMem/\IRData_reg[21] } {/theMem/\IRData_reg[20] } {/theMem/\IRData_reg[19] } {/theMem/\IRData_reg[18] } {/theMem/\IRData_reg[17] } {/theMem/\IRData_reg[16] } {/theMem/\IRData_reg[15] } {/theMem/\IRData_reg[14] } {/theMem/\IRData_reg[13] } {/theMem/\IRData_reg[12] } {/theMem/\IRData_reg[11] } {/theMem/\IRData_reg[10] } {/theMem/\IRData_reg[9] } {/theMem/\IRData_reg[8] } {/theMem/\IRData_reg[7] } {/theMem/\IRData_reg[6] } {/theMem/\IRData_reg[5] } {/theMem/\IRData_reg[4] } {/theMem/\IRData_reg[3] } {/theMem/\IRData_reg[2] } {/theMem/\IRData_reg[1] } {/theMem/\IRData_reg[0] } {/theMem/\mem_addr_reg[10] } {/theMem/\mem_addr_reg[9] } {/theMem/\mem_addr_reg[8] } {/theMem/\mem_addr_reg[7] } {/theMem/\mem_addr_reg[6] } {/theMem/\mem_addr_reg[5] } {/theMem/\mem_addr_reg[4] } {/theMem/\mem_addr_reg[3] } {/theMem/\mem_addr_reg[2] } {/theMem/\mem_addr_reg[1] } {/theMem/\mem_addr_reg[0] } {/theMem/\drTmp_reg[31] } {/theMem/\drTmp_reg[30] } {/theMem/\drTmp_reg[29] } {/theMem/\drTmp_reg[28] } {/theMem/\drTmp_reg[27] } {/theMem/\drTmp_reg[26] } {/theMem/\drTmp_reg[25] } {/theMem/\drTmp_reg[24] } {/theMem/\drTmp_reg[23] } {/theMem/\drTmp_reg[22] } {/theMem/\drTmp_reg[21] } {/theMem/\drTmp_reg[20] } {/theMem/\drTmp_reg[19] } {/theMem/\drTmp_reg[18] } {/theMem/\drTmp_reg[17] } {/theMem/\drTmp_reg[16] } {/theMem/\drTmp_reg[15] } {/theMem/\drTmp_reg[14] } {/theMem/\drTmp_reg[13] } {/theMem/\drTmp_reg[12] } {/theMem/\drTmp_reg[11] } {/theMem/\drTmp_reg[10] } {/theMem/\drTmp_reg[9] } {/theMem/\drTmp_reg[8] } {/theMem/\drTmp_reg[7] } {/theMem/\drTmp_reg[6] } {/theMem/\drTmp_reg[5] } {/theMem/\drTmp_reg[4] } {/theMem/\drTmp_reg[3] } {/theMem/\drTmp_reg[2] } {/theMem/\drTmp_reg[1] } {/theMem/\drTmp_reg[0] } {/theMem/\mem_wdata_reg[31] } {/theMem/\mem_wdata_reg[30] } {/theMem/\mem_wdata_reg[29] } {/theMem/\mem_wdata_reg[28] } {/theMem/\mem_wdata_reg[27] } {/theMem/\mem_wdata_reg[26] } {/theMem/\mem_wdata_reg[25] } {/theMem/\mem_wdata_reg[24] } {/theMem/\mem_wdata_reg[23] } {/theMem/\mem_wdata_reg[22] } {/theMem/\mem_wdata_reg[21] } {/theMem/\mem_wdata_reg[20] } {/theMem/\mem_wdata_reg[19] } {/theMem/\mem_wdata_reg[18] } {/theMem/\mem_wdata_reg[17] } {/theMem/\mem_wdata_reg[16] } {/theMem/\mem_wdata_reg[15] } {/theMem/\mem_wdata_reg[14] } {/theMem/\mem_wdata_reg[13] } {/theMem/\mem_wdata_reg[12] } {/theMem/\mem_wdata_reg[11] } {/theMem/\mem_wdata_reg[10] } {/theMem/\mem_wdata_reg[9] } {/theMem/\mem_wdata_reg[8] } {/theMem/\mem_wdata_reg[7] } {/theMem/\mem_wdata_reg[6] } {/theMem/\mem_wdata_reg[5] } {/theMem/\mem_wdata_reg[4] } {/theMem/\mem_wdata_reg[3] } {/theMem/\mem_wdata_reg[2] } {/theMem/\mem_wdata_reg[1] } {/theMem/\mem_wdata_reg[0] } } +if {[catch {get_clocks clk_25mhz > /dev/null }] && +[catch {get_dft_signal clk_25mhz > /dev/null }]} { +add_clocks 0 { clk_25mhz } +} + +set_scan_enable scan_en -active high +add_input_constraints btn[0] -C1 +set_scan_enable scan_en -active high -cluster_name scanChain_1 +set_scan_enable scan_en -active high -cluster_name scanChain_2 +set_scan_enable scan_en -active high -cluster_name scanChain_3 +set_scan_enable scan_en -active high -cluster_name scanChain_4 + +add_black_boxes -modules { MemGen_16_10 } +set_scan_insertion_options -single_clock_edge_chains on -si_port_format {oas_ts_si[%d]} -so_port_format {oas_ts_so[%d]} +set_system_mode analysis +report_drc_rules + +create_scan_chain_family scanChain_1 -include_elements {{/\thePC_CurrentPC_reg[0] } {/\thePC_CurrentPC_reg[10] } {/\thePC_CurrentPC_reg[11] } {/\thePC_CurrentPC_reg[12] } {/\thePC_CurrentPC_reg[13] } {/\thePC_CurrentPC_reg[14] } {/\thePC_CurrentPC_reg[15] } {/\thePC_CurrentPC_reg[16] } {/\thePC_CurrentPC_reg[17] } {/\thePC_CurrentPC_reg[18] } {/\thePC_CurrentPC_reg[19] } {/\thePC_CurrentPC_reg[1] } {/\thePC_CurrentPC_reg[20] } {/\thePC_CurrentPC_reg[21] } {/\thePC_CurrentPC_reg[22] } {/\thePC_CurrentPC_reg[23] } {/\thePC_CurrentPC_reg[24] } {/\thePC_CurrentPC_reg[25] } {/\thePC_CurrentPC_reg[26] } {/\thePC_CurrentPC_reg[27] } {/\thePC_CurrentPC_reg[28] } {/\thePC_CurrentPC_reg[29] } {/\thePC_CurrentPC_reg[2] } {/\thePC_CurrentPC_reg[30] } {/\thePC_CurrentPC_reg[31] } {/\thePC_CurrentPC_reg[3] } {/\thePC_CurrentPC_reg[4] } {/\thePC_CurrentPC_reg[5] } {/\thePC_CurrentPC_reg[6] } {/\thePC_CurrentPC_reg[7] } {/\thePC_CurrentPC_reg[8] } {/\thePC_CurrentPC_reg[9] } {/theRegisters/\registers_reg[10][0] } {/theRegisters/\registers_reg[10][10] } {/theRegisters/\registers_reg[10][11] } {/theRegisters/\registers_reg[10][12] } {/theRegisters/\registers_reg[10][13] } {/theRegisters/\registers_reg[10][14] } {/theRegisters/\registers_reg[10][15] } {/theRegisters/\registers_reg[10][16] } {/theRegisters/\registers_reg[10][17] } {/theRegisters/\registers_reg[10][18] } {/theRegisters/\registers_reg[10][19] } {/theRegisters/\registers_reg[10][1] } {/theRegisters/\registers_reg[10][20] } {/theRegisters/\registers_reg[10][21] } {/theRegisters/\registers_reg[10][22] } {/theRegisters/\registers_reg[10][23] } {/theRegisters/\registers_reg[10][24] } {/theRegisters/\registers_reg[10][25] } {/theRegisters/\registers_reg[10][26] } {/theRegisters/\registers_reg[10][27] } {/theRegisters/\registers_reg[10][28] } {/theRegisters/\registers_reg[10][29] } {/theRegisters/\registers_reg[10][2] } {/theRegisters/\registers_reg[10][30] } {/theRegisters/\registers_reg[10][31] } {/theRegisters/\registers_reg[10][3] } {/theRegisters/\registers_reg[10][4] } {/theRegisters/\registers_reg[10][5] } {/theRegisters/\registers_reg[10][6] } {/theRegisters/\registers_reg[10][7] } {/theRegisters/\registers_reg[10][8] } {/theRegisters/\registers_reg[10][9] } {/theRegisters/\registers_reg[11][0] } {/theRegisters/\registers_reg[11][10] } {/theRegisters/\registers_reg[11][11] } {/theRegisters/\registers_reg[11][12] } {/theRegisters/\registers_reg[11][13] } {/theRegisters/\registers_reg[11][14] } {/theRegisters/\registers_reg[11][15] } {/theRegisters/\registers_reg[11][16] } {/theRegisters/\registers_reg[11][17] } {/theRegisters/\registers_reg[11][18] } {/theRegisters/\registers_reg[11][19] } {/theRegisters/\registers_reg[11][1] } {/theRegisters/\registers_reg[11][20] } {/theRegisters/\registers_reg[11][21] } {/theRegisters/\registers_reg[11][22] } {/theRegisters/\registers_reg[11][23] } {/theRegisters/\registers_reg[11][24] } {/theRegisters/\registers_reg[11][25] } {/theRegisters/\registers_reg[11][26] } {/theRegisters/\registers_reg[11][27] } {/theRegisters/\registers_reg[11][28] } {/theRegisters/\registers_reg[11][29] } {/theRegisters/\registers_reg[11][2] } {/theRegisters/\registers_reg[11][30] } {/theRegisters/\registers_reg[11][31] } {/theRegisters/\registers_reg[11][3] } {/theRegisters/\registers_reg[11][4] } {/theRegisters/\registers_reg[11][5] } {/theRegisters/\registers_reg[11][6] } {/theRegisters/\registers_reg[11][7] } {/theRegisters/\registers_reg[11][8] } {/theRegisters/\registers_reg[11][9] } {/theRegisters/\registers_reg[12][0] } {/theRegisters/\registers_reg[12][10] } {/theRegisters/\registers_reg[12][11] } {/theRegisters/\registers_reg[12][12] } {/theRegisters/\registers_reg[12][13] } {/theRegisters/\registers_reg[12][14] } {/theRegisters/\registers_reg[12][15] } {/theRegisters/\registers_reg[12][16] } {/theRegisters/\registers_reg[12][17] } {/theRegisters/\registers_reg[12][18] } {/theRegisters/\registers_reg[12][19] } {/theRegisters/\registers_reg[12][1] } {/theRegisters/\registers_reg[12][20] } {/theRegisters/\registers_reg[12][21] } {/theRegisters/\registers_reg[12][22] } {/theRegisters/\registers_reg[12][23] } {/theRegisters/\registers_reg[12][24] } {/theRegisters/\registers_reg[12][25] } {/theRegisters/\registers_reg[12][26] } {/theRegisters/\registers_reg[12][27] } {/theRegisters/\registers_reg[12][28] } {/theRegisters/\registers_reg[12][29] } {/theRegisters/\registers_reg[12][2] } {/theRegisters/\registers_reg[12][30] } {/theRegisters/\registers_reg[12][31] } {/theRegisters/\registers_reg[12][3] } {/theRegisters/\registers_reg[12][4] } {/theRegisters/\registers_reg[12][5] } {/theRegisters/\registers_reg[12][6] } {/theRegisters/\registers_reg[12][7] } {/theRegisters/\registers_reg[12][8] } {/theRegisters/\registers_reg[12][9] } {/theRegisters/\registers_reg[13][0] } {/theRegisters/\registers_reg[13][10] } {/theRegisters/\registers_reg[13][11] } {/theRegisters/\registers_reg[13][12] } {/theRegisters/\registers_reg[13][13] } {/theRegisters/\registers_reg[13][14] } {/theRegisters/\registers_reg[13][15] } {/theRegisters/\registers_reg[13][16] } {/theRegisters/\registers_reg[13][17] } {/theRegisters/\registers_reg[13][18] } {/theRegisters/\registers_reg[13][19] } {/theRegisters/\registers_reg[13][1] } {/theRegisters/\registers_reg[13][20] } {/theRegisters/\registers_reg[13][21] } {/theRegisters/\registers_reg[13][22] } {/theRegisters/\registers_reg[13][23] } {/theRegisters/\registers_reg[13][24] } {/theRegisters/\registers_reg[13][25] } {/theRegisters/\registers_reg[13][26] } {/theRegisters/\registers_reg[13][27] } {/theRegisters/\registers_reg[13][28] } {/theRegisters/\registers_reg[13][29] } {/theRegisters/\registers_reg[13][2] } {/theRegisters/\registers_reg[13][30] } {/theRegisters/\registers_reg[13][31] } {/theRegisters/\registers_reg[13][3] } {/theRegisters/\registers_reg[13][4] } {/theRegisters/\registers_reg[13][5] } {/theRegisters/\registers_reg[13][6] } {/theRegisters/\registers_reg[13][7] } {/theRegisters/\registers_reg[13][8] } {/theRegisters/\registers_reg[13][9] } {/theRegisters/\registers_reg[14][0] } {/theRegisters/\registers_reg[14][10] } {/theRegisters/\registers_reg[14][11] } {/theRegisters/\registers_reg[14][12] } {/theRegisters/\registers_reg[14][13] } {/theRegisters/\registers_reg[14][14] } {/theRegisters/\registers_reg[14][15] } {/theRegisters/\registers_reg[14][16] } {/theRegisters/\registers_reg[14][17] } {/theRegisters/\registers_reg[14][18] } {/theRegisters/\registers_reg[14][19] } {/theRegisters/\registers_reg[14][1] } {/theRegisters/\registers_reg[14][20] } {/theRegisters/\registers_reg[14][21] } {/theRegisters/\registers_reg[14][22] } {/theRegisters/\registers_reg[14][23] } {/theRegisters/\registers_reg[14][24] } {/theRegisters/\registers_reg[14][25] } {/theRegisters/\registers_reg[14][26] } {/theRegisters/\registers_reg[14][27] } {/theRegisters/\registers_reg[14][28] } {/theRegisters/\registers_reg[14][29] } {/theRegisters/\registers_reg[14][2] } {/theRegisters/\registers_reg[14][30] } {/theRegisters/\registers_reg[14][31] } {/theRegisters/\registers_reg[14][3] } {/theRegisters/\registers_reg[14][4] } {/theRegisters/\registers_reg[14][5] } {/theRegisters/\registers_reg[14][6] } {/theRegisters/\registers_reg[14][7] } {/theRegisters/\registers_reg[14][8] } {/theRegisters/\registers_reg[14][9] } {/theRegisters/\registers_reg[15][0] } {/theRegisters/\registers_reg[15][10] } {/theRegisters/\registers_reg[15][11] } {/theRegisters/\registers_reg[15][12] } {/theRegisters/\registers_reg[15][13] } {/theRegisters/\registers_reg[15][14] } {/theRegisters/\registers_reg[15][15] } {/theRegisters/\registers_reg[15][16] } {/theRegisters/\registers_reg[15][17] } {/theRegisters/\registers_reg[15][18] } {/theRegisters/\registers_reg[15][19] } {/theRegisters/\registers_reg[15][1] } {/theRegisters/\registers_reg[15][20] } {/theRegisters/\registers_reg[15][21] } {/theRegisters/\registers_reg[15][22] } {/theRegisters/\registers_reg[15][23] } {/theRegisters/\registers_reg[15][24] } {/theRegisters/\registers_reg[15][25] } {/theRegisters/\registers_reg[15][26] } {/theRegisters/\registers_reg[15][27] } {/theRegisters/\registers_reg[15][28] } {/theRegisters/\registers_reg[15][29] } {/theRegisters/\registers_reg[15][2] } {/theRegisters/\registers_reg[15][30] } {/theRegisters/\registers_reg[15][31] } {/theRegisters/\registers_reg[15][3] } {/theRegisters/\registers_reg[15][4] } {/theRegisters/\registers_reg[15][5] } {/theRegisters/\registers_reg[15][6] } {/theRegisters/\registers_reg[15][7] } {/theRegisters/\registers_reg[15][8] } {/theRegisters/\registers_reg[15][9] } {/theRegisters/\registers_reg[16][0] } {/theRegisters/\registers_reg[16][10] } {/theRegisters/\registers_reg[16][11] } {/theRegisters/\registers_reg[16][12] } {/theRegisters/\registers_reg[16][13] } {/theRegisters/\registers_reg[16][14] } {/theRegisters/\registers_reg[16][15] } {/theRegisters/\registers_reg[16][16] } {/theRegisters/\registers_reg[16][17] } {/theRegisters/\registers_reg[16][18] } {/theRegisters/\registers_reg[16][19] } {/theRegisters/\registers_reg[16][1] } {/theRegisters/\registers_reg[16][20] } {/theRegisters/\registers_reg[16][21] } {/theRegisters/\registers_reg[16][22] } {/theRegisters/\registers_reg[16][23] } {/theRegisters/\registers_reg[16][24] } {/theRegisters/\registers_reg[16][25] } {/theRegisters/\registers_reg[16][26] } {/theRegisters/\registers_reg[16][27] } {/theRegisters/\registers_reg[16][28] } {/theRegisters/\registers_reg[16][29] } {/theRegisters/\registers_reg[16][2] } {/theRegisters/\registers_reg[16][30] } {/theRegisters/\registers_reg[16][31] } {/theRegisters/\registers_reg[16][3] } {/theRegisters/\registers_reg[16][4] } {/theRegisters/\registers_reg[16][5] } {/theRegisters/\registers_reg[16][6] } {/theRegisters/\registers_reg[16][7] } {/theRegisters/\registers_reg[16][8] } {/theRegisters/\registers_reg[16][9] } } -si_connections {SI_1 } -so_connections {SO_1 } -chain_count 1 +create_scan_chain_family scanChain_2 -include_elements {{/theRegisters/\registers_reg[17][0] } {/theRegisters/\registers_reg[17][10] } {/theRegisters/\registers_reg[17][11] } {/theRegisters/\registers_reg[17][12] } {/theRegisters/\registers_reg[17][13] } {/theRegisters/\registers_reg[17][14] } {/theRegisters/\registers_reg[17][15] } {/theRegisters/\registers_reg[17][16] } {/theRegisters/\registers_reg[17][17] } {/theRegisters/\registers_reg[17][18] } {/theRegisters/\registers_reg[17][19] } {/theRegisters/\registers_reg[17][1] } {/theRegisters/\registers_reg[17][20] } {/theRegisters/\registers_reg[17][21] } {/theRegisters/\registers_reg[17][22] } {/theRegisters/\registers_reg[17][23] } {/theRegisters/\registers_reg[17][24] } {/theRegisters/\registers_reg[17][25] } {/theRegisters/\registers_reg[17][26] } {/theRegisters/\registers_reg[17][27] } {/theRegisters/\registers_reg[17][28] } {/theRegisters/\registers_reg[17][29] } {/theRegisters/\registers_reg[17][2] } {/theRegisters/\registers_reg[17][30] } {/theRegisters/\registers_reg[17][31] } {/theRegisters/\registers_reg[17][3] } {/theRegisters/\registers_reg[17][4] } {/theRegisters/\registers_reg[17][5] } {/theRegisters/\registers_reg[17][6] } {/theRegisters/\registers_reg[17][7] } {/theRegisters/\registers_reg[17][8] } {/theRegisters/\registers_reg[17][9] } {/theRegisters/\registers_reg[18][0] } {/theRegisters/\registers_reg[18][10] } {/theRegisters/\registers_reg[18][11] } {/theRegisters/\registers_reg[18][12] } {/theRegisters/\registers_reg[18][13] } {/theRegisters/\registers_reg[18][14] } {/theRegisters/\registers_reg[18][15] } {/theRegisters/\registers_reg[18][16] } {/theRegisters/\registers_reg[18][17] } {/theRegisters/\registers_reg[18][18] } {/theRegisters/\registers_reg[18][19] } {/theRegisters/\registers_reg[18][1] } {/theRegisters/\registers_reg[18][20] } {/theRegisters/\registers_reg[18][21] } {/theRegisters/\registers_reg[18][22] } {/theRegisters/\registers_reg[18][23] } {/theRegisters/\registers_reg[18][24] } {/theRegisters/\registers_reg[18][25] } {/theRegisters/\registers_reg[18][26] } {/theRegisters/\registers_reg[18][27] } {/theRegisters/\registers_reg[18][28] } {/theRegisters/\registers_reg[18][29] } {/theRegisters/\registers_reg[18][2] } {/theRegisters/\registers_reg[18][30] } {/theRegisters/\registers_reg[18][31] } {/theRegisters/\registers_reg[18][3] } {/theRegisters/\registers_reg[18][4] } {/theRegisters/\registers_reg[18][5] } {/theRegisters/\registers_reg[18][6] } {/theRegisters/\registers_reg[18][7] } {/theRegisters/\registers_reg[18][8] } {/theRegisters/\registers_reg[18][9] } {/theRegisters/\registers_reg[19][0] } {/theRegisters/\registers_reg[19][10] } {/theRegisters/\registers_reg[19][11] } {/theRegisters/\registers_reg[19][12] } {/theRegisters/\registers_reg[19][13] } {/theRegisters/\registers_reg[19][14] } {/theRegisters/\registers_reg[19][15] } {/theRegisters/\registers_reg[19][16] } {/theRegisters/\registers_reg[19][17] } {/theRegisters/\registers_reg[19][18] } {/theRegisters/\registers_reg[19][19] } {/theRegisters/\registers_reg[19][1] } {/theRegisters/\registers_reg[19][20] } {/theRegisters/\registers_reg[19][21] } {/theRegisters/\registers_reg[19][22] } {/theRegisters/\registers_reg[19][23] } {/theRegisters/\registers_reg[19][24] } {/theRegisters/\registers_reg[19][25] } {/theRegisters/\registers_reg[19][26] } {/theRegisters/\registers_reg[19][27] } {/theRegisters/\registers_reg[19][28] } {/theRegisters/\registers_reg[19][29] } {/theRegisters/\registers_reg[19][2] } {/theRegisters/\registers_reg[19][30] } {/theRegisters/\registers_reg[19][31] } {/theRegisters/\registers_reg[19][3] } {/theRegisters/\registers_reg[19][4] } {/theRegisters/\registers_reg[19][5] } {/theRegisters/\registers_reg[19][6] } {/theRegisters/\registers_reg[19][7] } {/theRegisters/\registers_reg[19][8] } {/theRegisters/\registers_reg[19][9] } {/theRegisters/\registers_reg[1][0] } {/theRegisters/\registers_reg[1][10] } {/theRegisters/\registers_reg[1][11] } {/theRegisters/\registers_reg[1][12] } {/theRegisters/\registers_reg[1][13] } {/theRegisters/\registers_reg[1][14] } {/theRegisters/\registers_reg[1][15] } {/theRegisters/\registers_reg[1][16] } {/theRegisters/\registers_reg[1][17] } {/theRegisters/\registers_reg[1][18] } {/theRegisters/\registers_reg[1][19] } {/theRegisters/\registers_reg[1][1] } {/theRegisters/\registers_reg[1][20] } {/theRegisters/\registers_reg[1][21] } {/theRegisters/\registers_reg[1][22] } {/theRegisters/\registers_reg[1][23] } {/theRegisters/\registers_reg[1][24] } {/theRegisters/\registers_reg[1][25] } {/theRegisters/\registers_reg[1][26] } {/theRegisters/\registers_reg[1][27] } {/theRegisters/\registers_reg[1][28] } {/theRegisters/\registers_reg[1][29] } {/theRegisters/\registers_reg[1][2] } {/theRegisters/\registers_reg[1][30] } {/theRegisters/\registers_reg[1][31] } {/theRegisters/\registers_reg[1][3] } {/theRegisters/\registers_reg[1][4] } {/theRegisters/\registers_reg[1][5] } {/theRegisters/\registers_reg[1][6] } {/theRegisters/\registers_reg[1][7] } {/theRegisters/\registers_reg[1][8] } {/theRegisters/\registers_reg[1][9] } {/theRegisters/\registers_reg[20][0] } {/theRegisters/\registers_reg[20][10] } {/theRegisters/\registers_reg[20][11] } {/theRegisters/\registers_reg[20][12] } {/theRegisters/\registers_reg[20][13] } {/theRegisters/\registers_reg[20][14] } {/theRegisters/\registers_reg[20][15] } {/theRegisters/\registers_reg[20][16] } {/theRegisters/\registers_reg[20][17] } {/theRegisters/\registers_reg[20][18] } {/theRegisters/\registers_reg[20][19] } {/theRegisters/\registers_reg[20][1] } {/theRegisters/\registers_reg[20][20] } {/theRegisters/\registers_reg[20][21] } {/theRegisters/\registers_reg[20][22] } {/theRegisters/\registers_reg[20][23] } {/theRegisters/\registers_reg[20][24] } {/theRegisters/\registers_reg[20][25] } {/theRegisters/\registers_reg[20][26] } {/theRegisters/\registers_reg[20][27] } {/theRegisters/\registers_reg[20][28] } {/theRegisters/\registers_reg[20][29] } {/theRegisters/\registers_reg[20][2] } {/theRegisters/\registers_reg[20][30] } {/theRegisters/\registers_reg[20][31] } {/theRegisters/\registers_reg[20][3] } {/theRegisters/\registers_reg[20][4] } {/theRegisters/\registers_reg[20][5] } {/theRegisters/\registers_reg[20][6] } {/theRegisters/\registers_reg[20][7] } {/theRegisters/\registers_reg[20][8] } {/theRegisters/\registers_reg[20][9] } {/theRegisters/\registers_reg[21][0] } {/theRegisters/\registers_reg[21][10] } {/theRegisters/\registers_reg[21][11] } {/theRegisters/\registers_reg[21][12] } {/theRegisters/\registers_reg[21][13] } {/theRegisters/\registers_reg[21][14] } {/theRegisters/\registers_reg[21][15] } {/theRegisters/\registers_reg[21][16] } {/theRegisters/\registers_reg[21][17] } {/theRegisters/\registers_reg[21][18] } {/theRegisters/\registers_reg[21][19] } {/theRegisters/\registers_reg[21][1] } {/theRegisters/\registers_reg[21][20] } {/theRegisters/\registers_reg[21][21] } {/theRegisters/\registers_reg[21][22] } {/theRegisters/\registers_reg[21][23] } {/theRegisters/\registers_reg[21][24] } {/theRegisters/\registers_reg[21][25] } {/theRegisters/\registers_reg[21][26] } {/theRegisters/\registers_reg[21][27] } {/theRegisters/\registers_reg[21][28] } {/theRegisters/\registers_reg[21][29] } {/theRegisters/\registers_reg[21][2] } {/theRegisters/\registers_reg[21][30] } {/theRegisters/\registers_reg[21][31] } {/theRegisters/\registers_reg[21][3] } {/theRegisters/\registers_reg[21][4] } {/theRegisters/\registers_reg[21][5] } {/theRegisters/\registers_reg[21][6] } {/theRegisters/\registers_reg[21][7] } {/theRegisters/\registers_reg[21][8] } {/theRegisters/\registers_reg[21][9] } {/theRegisters/\registers_reg[22][0] } {/theRegisters/\registers_reg[22][10] } {/theRegisters/\registers_reg[22][11] } {/theRegisters/\registers_reg[22][12] } {/theRegisters/\registers_reg[22][13] } {/theRegisters/\registers_reg[22][14] } {/theRegisters/\registers_reg[22][15] } {/theRegisters/\registers_reg[22][16] } {/theRegisters/\registers_reg[22][17] } {/theRegisters/\registers_reg[22][18] } {/theRegisters/\registers_reg[22][19] } {/theRegisters/\registers_reg[22][1] } {/theRegisters/\registers_reg[22][20] } {/theRegisters/\registers_reg[22][21] } {/theRegisters/\registers_reg[22][22] } {/theRegisters/\registers_reg[22][23] } {/theRegisters/\registers_reg[22][24] } {/theRegisters/\registers_reg[22][25] } {/theRegisters/\registers_reg[22][26] } {/theRegisters/\registers_reg[22][27] } {/theRegisters/\registers_reg[22][28] } {/theRegisters/\registers_reg[22][29] } {/theRegisters/\registers_reg[22][2] } {/theRegisters/\registers_reg[22][30] } {/theRegisters/\registers_reg[22][31] } {/theRegisters/\registers_reg[22][3] } {/theRegisters/\registers_reg[22][4] } {/theRegisters/\registers_reg[22][5] } {/theRegisters/\registers_reg[22][6] } {/theRegisters/\registers_reg[22][7] } {/theRegisters/\registers_reg[22][8] } {/theRegisters/\registers_reg[22][9] } {/theRegisters/\registers_reg[23][0] } {/theRegisters/\registers_reg[23][10] } {/theRegisters/\registers_reg[23][11] } {/theRegisters/\registers_reg[23][12] } {/theRegisters/\registers_reg[23][13] } {/theRegisters/\registers_reg[23][14] } {/theRegisters/\registers_reg[23][15] } {/theRegisters/\registers_reg[23][16] } {/theRegisters/\registers_reg[23][17] } {/theRegisters/\registers_reg[23][18] } {/theRegisters/\registers_reg[23][19] } {/theRegisters/\registers_reg[23][1] } {/theRegisters/\registers_reg[23][20] } {/theRegisters/\registers_reg[23][21] } {/theRegisters/\registers_reg[23][22] } {/theRegisters/\registers_reg[23][23] } {/theRegisters/\registers_reg[23][24] } {/theRegisters/\registers_reg[23][25] } {/theRegisters/\registers_reg[23][26] } {/theRegisters/\registers_reg[23][27] } {/theRegisters/\registers_reg[23][28] } {/theRegisters/\registers_reg[23][29] } {/theRegisters/\registers_reg[23][2] } {/theRegisters/\registers_reg[23][30] } {/theRegisters/\registers_reg[23][31] } {/theRegisters/\registers_reg[23][3] } {/theRegisters/\registers_reg[23][4] } {/theRegisters/\registers_reg[23][5] } {/theRegisters/\registers_reg[23][6] } {/theRegisters/\registers_reg[23][7] } {/theRegisters/\registers_reg[23][8] } {/theRegisters/\registers_reg[23][9] } } -si_connections {SI_2 } -so_connections {SO_2 } -chain_count 1 +create_scan_chain_family scanChain_3 -include_elements {{/theRegisters/\registers_reg[24][0] } {/theRegisters/\registers_reg[24][10] } {/theRegisters/\registers_reg[24][11] } {/theRegisters/\registers_reg[24][12] } {/theRegisters/\registers_reg[24][13] } {/theRegisters/\registers_reg[24][14] } {/theRegisters/\registers_reg[24][15] } {/theRegisters/\registers_reg[24][16] } {/theRegisters/\registers_reg[24][17] } {/theRegisters/\registers_reg[24][18] } {/theRegisters/\registers_reg[24][19] } {/theRegisters/\registers_reg[24][1] } {/theRegisters/\registers_reg[24][20] } {/theRegisters/\registers_reg[24][21] } {/theRegisters/\registers_reg[24][22] } {/theRegisters/\registers_reg[24][23] } {/theRegisters/\registers_reg[24][24] } {/theRegisters/\registers_reg[24][25] } {/theRegisters/\registers_reg[24][26] } {/theRegisters/\registers_reg[24][27] } {/theRegisters/\registers_reg[24][28] } {/theRegisters/\registers_reg[24][29] } {/theRegisters/\registers_reg[24][2] } {/theRegisters/\registers_reg[24][30] } {/theRegisters/\registers_reg[24][31] } {/theRegisters/\registers_reg[24][3] } {/theRegisters/\registers_reg[24][4] } {/theRegisters/\registers_reg[24][5] } {/theRegisters/\registers_reg[24][6] } {/theRegisters/\registers_reg[24][7] } {/theRegisters/\registers_reg[24][8] } {/theRegisters/\registers_reg[24][9] } {/theRegisters/\registers_reg[25][0] } {/theRegisters/\registers_reg[25][10] } {/theRegisters/\registers_reg[25][11] } {/theRegisters/\registers_reg[25][12] } {/theRegisters/\registers_reg[25][13] } {/theRegisters/\registers_reg[25][14] } {/theRegisters/\registers_reg[25][15] } {/theRegisters/\registers_reg[25][16] } {/theRegisters/\registers_reg[25][17] } {/theRegisters/\registers_reg[25][18] } {/theRegisters/\registers_reg[25][19] } {/theRegisters/\registers_reg[25][1] } {/theRegisters/\registers_reg[25][20] } {/theRegisters/\registers_reg[25][21] } {/theRegisters/\registers_reg[25][22] } {/theRegisters/\registers_reg[25][23] } {/theRegisters/\registers_reg[25][24] } {/theRegisters/\registers_reg[25][25] } {/theRegisters/\registers_reg[25][26] } {/theRegisters/\registers_reg[25][27] } {/theRegisters/\registers_reg[25][28] } {/theRegisters/\registers_reg[25][29] } {/theRegisters/\registers_reg[25][2] } {/theRegisters/\registers_reg[25][30] } {/theRegisters/\registers_reg[25][31] } {/theRegisters/\registers_reg[25][3] } {/theRegisters/\registers_reg[25][4] } {/theRegisters/\registers_reg[25][5] } {/theRegisters/\registers_reg[25][6] } {/theRegisters/\registers_reg[25][7] } {/theRegisters/\registers_reg[25][8] } {/theRegisters/\registers_reg[25][9] } {/theRegisters/\registers_reg[26][0] } {/theRegisters/\registers_reg[26][10] } {/theRegisters/\registers_reg[26][11] } {/theRegisters/\registers_reg[26][12] } {/theRegisters/\registers_reg[26][13] } {/theRegisters/\registers_reg[26][14] } {/theRegisters/\registers_reg[26][15] } {/theRegisters/\registers_reg[26][16] } {/theRegisters/\registers_reg[26][17] } {/theRegisters/\registers_reg[26][18] } {/theRegisters/\registers_reg[26][19] } {/theRegisters/\registers_reg[26][1] } {/theRegisters/\registers_reg[26][20] } {/theRegisters/\registers_reg[26][21] } {/theRegisters/\registers_reg[26][22] } {/theRegisters/\registers_reg[26][23] } {/theRegisters/\registers_reg[26][24] } {/theRegisters/\registers_reg[26][25] } {/theRegisters/\registers_reg[26][26] } {/theRegisters/\registers_reg[26][27] } {/theRegisters/\registers_reg[26][28] } {/theRegisters/\registers_reg[26][29] } {/theRegisters/\registers_reg[26][2] } {/theRegisters/\registers_reg[26][30] } {/theRegisters/\registers_reg[26][31] } {/theRegisters/\registers_reg[26][3] } {/theRegisters/\registers_reg[26][4] } {/theRegisters/\registers_reg[26][5] } {/theRegisters/\registers_reg[26][6] } {/theRegisters/\registers_reg[26][7] } {/theRegisters/\registers_reg[26][8] } {/theRegisters/\registers_reg[26][9] } {/theRegisters/\registers_reg[27][0] } {/theRegisters/\registers_reg[27][10] } {/theRegisters/\registers_reg[27][11] } {/theRegisters/\registers_reg[27][12] } {/theRegisters/\registers_reg[27][13] } {/theRegisters/\registers_reg[27][14] } {/theRegisters/\registers_reg[27][15] } {/theRegisters/\registers_reg[27][16] } {/theRegisters/\registers_reg[27][17] } {/theRegisters/\registers_reg[27][18] } {/theRegisters/\registers_reg[27][19] } {/theRegisters/\registers_reg[27][1] } {/theRegisters/\registers_reg[27][20] } {/theRegisters/\registers_reg[27][21] } {/theRegisters/\registers_reg[27][22] } {/theRegisters/\registers_reg[27][23] } {/theRegisters/\registers_reg[27][24] } {/theRegisters/\registers_reg[27][25] } {/theRegisters/\registers_reg[27][26] } {/theRegisters/\registers_reg[27][27] } {/theRegisters/\registers_reg[27][28] } {/theRegisters/\registers_reg[27][29] } {/theRegisters/\registers_reg[27][2] } {/theRegisters/\registers_reg[27][30] } {/theRegisters/\registers_reg[27][31] } {/theRegisters/\registers_reg[27][3] } {/theRegisters/\registers_reg[27][4] } {/theRegisters/\registers_reg[27][5] } {/theRegisters/\registers_reg[27][6] } {/theRegisters/\registers_reg[27][7] } {/theRegisters/\registers_reg[27][8] } {/theRegisters/\registers_reg[27][9] } {/theRegisters/\registers_reg[28][0] } {/theRegisters/\registers_reg[28][10] } {/theRegisters/\registers_reg[28][11] } {/theRegisters/\registers_reg[28][12] } {/theRegisters/\registers_reg[28][13] } {/theRegisters/\registers_reg[28][14] } {/theRegisters/\registers_reg[28][15] } {/theRegisters/\registers_reg[28][16] } {/theRegisters/\registers_reg[28][17] } {/theRegisters/\registers_reg[28][18] } {/theRegisters/\registers_reg[28][19] } {/theRegisters/\registers_reg[28][1] } {/theRegisters/\registers_reg[28][20] } {/theRegisters/\registers_reg[28][21] } {/theRegisters/\registers_reg[28][22] } {/theRegisters/\registers_reg[28][23] } {/theRegisters/\registers_reg[28][24] } {/theRegisters/\registers_reg[28][25] } {/theRegisters/\registers_reg[28][26] } {/theRegisters/\registers_reg[28][27] } {/theRegisters/\registers_reg[28][28] } {/theRegisters/\registers_reg[28][29] } {/theRegisters/\registers_reg[28][2] } {/theRegisters/\registers_reg[28][30] } {/theRegisters/\registers_reg[28][31] } {/theRegisters/\registers_reg[28][3] } {/theRegisters/\registers_reg[28][4] } {/theRegisters/\registers_reg[28][5] } {/theRegisters/\registers_reg[28][6] } {/theRegisters/\registers_reg[28][7] } {/theRegisters/\registers_reg[28][8] } {/theRegisters/\registers_reg[28][9] } {/theRegisters/\registers_reg[29][0] } {/theRegisters/\registers_reg[29][10] } {/theRegisters/\registers_reg[29][11] } {/theRegisters/\registers_reg[29][12] } {/theRegisters/\registers_reg[29][13] } {/theRegisters/\registers_reg[29][14] } {/theRegisters/\registers_reg[29][15] } {/theRegisters/\registers_reg[29][16] } {/theRegisters/\registers_reg[29][17] } {/theRegisters/\registers_reg[29][18] } {/theRegisters/\registers_reg[29][19] } {/theRegisters/\registers_reg[29][1] } {/theRegisters/\registers_reg[29][20] } {/theRegisters/\registers_reg[29][21] } {/theRegisters/\registers_reg[29][22] } {/theRegisters/\registers_reg[29][23] } {/theRegisters/\registers_reg[29][24] } {/theRegisters/\registers_reg[29][25] } {/theRegisters/\registers_reg[29][26] } {/theRegisters/\registers_reg[29][27] } {/theRegisters/\registers_reg[29][28] } {/theRegisters/\registers_reg[29][29] } {/theRegisters/\registers_reg[29][2] } {/theRegisters/\registers_reg[29][30] } {/theRegisters/\registers_reg[29][31] } {/theRegisters/\registers_reg[29][3] } {/theRegisters/\registers_reg[29][4] } {/theRegisters/\registers_reg[29][5] } {/theRegisters/\registers_reg[29][6] } {/theRegisters/\registers_reg[29][7] } {/theRegisters/\registers_reg[29][8] } {/theRegisters/\registers_reg[29][9] } {/theRegisters/\registers_reg[2][0] } {/theRegisters/\registers_reg[2][10] } {/theRegisters/\registers_reg[2][11] } {/theRegisters/\registers_reg[2][12] } {/theRegisters/\registers_reg[2][13] } {/theRegisters/\registers_reg[2][14] } {/theRegisters/\registers_reg[2][15] } {/theRegisters/\registers_reg[2][16] } {/theRegisters/\registers_reg[2][17] } {/theRegisters/\registers_reg[2][18] } {/theRegisters/\registers_reg[2][19] } {/theRegisters/\registers_reg[2][1] } {/theRegisters/\registers_reg[2][20] } {/theRegisters/\registers_reg[2][21] } {/theRegisters/\registers_reg[2][22] } {/theRegisters/\registers_reg[2][23] } {/theRegisters/\registers_reg[2][24] } {/theRegisters/\registers_reg[2][25] } {/theRegisters/\registers_reg[2][26] } {/theRegisters/\registers_reg[2][27] } {/theRegisters/\registers_reg[2][28] } {/theRegisters/\registers_reg[2][29] } {/theRegisters/\registers_reg[2][2] } {/theRegisters/\registers_reg[2][30] } {/theRegisters/\registers_reg[2][31] } {/theRegisters/\registers_reg[2][3] } {/theRegisters/\registers_reg[2][4] } {/theRegisters/\registers_reg[2][5] } {/theRegisters/\registers_reg[2][6] } {/theRegisters/\registers_reg[2][7] } {/theRegisters/\registers_reg[2][8] } {/theRegisters/\registers_reg[2][9] } {/theRegisters/\registers_reg[30][0] } {/theRegisters/\registers_reg[30][10] } {/theRegisters/\registers_reg[30][11] } {/theRegisters/\registers_reg[30][12] } {/theRegisters/\registers_reg[30][13] } {/theRegisters/\registers_reg[30][14] } {/theRegisters/\registers_reg[30][15] } {/theRegisters/\registers_reg[30][16] } {/theRegisters/\registers_reg[30][17] } {/theRegisters/\registers_reg[30][18] } {/theRegisters/\registers_reg[30][19] } {/theRegisters/\registers_reg[30][1] } {/theRegisters/\registers_reg[30][20] } {/theRegisters/\registers_reg[30][21] } {/theRegisters/\registers_reg[30][22] } {/theRegisters/\registers_reg[30][23] } {/theRegisters/\registers_reg[30][24] } {/theRegisters/\registers_reg[30][25] } {/theRegisters/\registers_reg[30][26] } {/theRegisters/\registers_reg[30][27] } {/theRegisters/\registers_reg[30][28] } {/theRegisters/\registers_reg[30][29] } {/theRegisters/\registers_reg[30][2] } {/theRegisters/\registers_reg[30][30] } {/theRegisters/\registers_reg[30][31] } {/theRegisters/\registers_reg[30][3] } {/theRegisters/\registers_reg[30][4] } {/theRegisters/\registers_reg[30][5] } {/theRegisters/\registers_reg[30][6] } {/theRegisters/\registers_reg[30][7] } {/theRegisters/\registers_reg[30][8] } {/theRegisters/\registers_reg[30][9] } } -si_connections {SI_3 } -so_connections {SO_3 } -chain_count 1 +create_scan_chain_family scanChain_4 -include_elements {{/theRegisters/\registers_reg[31][0] } {/theRegisters/\registers_reg[31][10] } {/theRegisters/\registers_reg[31][11] } {/theRegisters/\registers_reg[31][12] } {/theRegisters/\registers_reg[31][13] } {/theRegisters/\registers_reg[31][14] } {/theRegisters/\registers_reg[31][15] } {/theRegisters/\registers_reg[31][16] } {/theRegisters/\registers_reg[31][17] } {/theRegisters/\registers_reg[31][18] } {/theRegisters/\registers_reg[31][19] } {/theRegisters/\registers_reg[31][1] } {/theRegisters/\registers_reg[31][20] } {/theRegisters/\registers_reg[31][21] } {/theRegisters/\registers_reg[31][22] } {/theRegisters/\registers_reg[31][23] } {/theRegisters/\registers_reg[31][24] } {/theRegisters/\registers_reg[31][25] } {/theRegisters/\registers_reg[31][26] } {/theRegisters/\registers_reg[31][27] } {/theRegisters/\registers_reg[31][28] } {/theRegisters/\registers_reg[31][29] } {/theRegisters/\registers_reg[31][2] } {/theRegisters/\registers_reg[31][30] } {/theRegisters/\registers_reg[31][31] } {/theRegisters/\registers_reg[31][3] } {/theRegisters/\registers_reg[31][4] } {/theRegisters/\registers_reg[31][5] } {/theRegisters/\registers_reg[31][6] } {/theRegisters/\registers_reg[31][7] } {/theRegisters/\registers_reg[31][8] } {/theRegisters/\registers_reg[31][9] } {/theRegisters/\registers_reg[3][0] } {/theRegisters/\registers_reg[3][10] } {/theRegisters/\registers_reg[3][11] } {/theRegisters/\registers_reg[3][12] } {/theRegisters/\registers_reg[3][13] } {/theRegisters/\registers_reg[3][14] } {/theRegisters/\registers_reg[3][15] } {/theRegisters/\registers_reg[3][16] } {/theRegisters/\registers_reg[3][17] } {/theRegisters/\registers_reg[3][18] } {/theRegisters/\registers_reg[3][19] } {/theRegisters/\registers_reg[3][1] } {/theRegisters/\registers_reg[3][20] } {/theRegisters/\registers_reg[3][21] } {/theRegisters/\registers_reg[3][22] } {/theRegisters/\registers_reg[3][23] } {/theRegisters/\registers_reg[3][24] } {/theRegisters/\registers_reg[3][25] } {/theRegisters/\registers_reg[3][26] } {/theRegisters/\registers_reg[3][27] } {/theRegisters/\registers_reg[3][28] } {/theRegisters/\registers_reg[3][29] } {/theRegisters/\registers_reg[3][2] } {/theRegisters/\registers_reg[3][30] } {/theRegisters/\registers_reg[3][31] } {/theRegisters/\registers_reg[3][3] } {/theRegisters/\registers_reg[3][4] } {/theRegisters/\registers_reg[3][5] } {/theRegisters/\registers_reg[3][6] } {/theRegisters/\registers_reg[3][7] } {/theRegisters/\registers_reg[3][8] } {/theRegisters/\registers_reg[3][9] } {/theRegisters/\registers_reg[4][0] } {/theRegisters/\registers_reg[4][10] } {/theRegisters/\registers_reg[4][11] } {/theRegisters/\registers_reg[4][12] } {/theRegisters/\registers_reg[4][13] } {/theRegisters/\registers_reg[4][14] } {/theRegisters/\registers_reg[4][15] } {/theRegisters/\registers_reg[4][16] } {/theRegisters/\registers_reg[4][17] } {/theRegisters/\registers_reg[4][18] } {/theRegisters/\registers_reg[4][19] } {/theRegisters/\registers_reg[4][1] } {/theRegisters/\registers_reg[4][20] } {/theRegisters/\registers_reg[4][21] } {/theRegisters/\registers_reg[4][22] } {/theRegisters/\registers_reg[4][23] } {/theRegisters/\registers_reg[4][24] } {/theRegisters/\registers_reg[4][25] } {/theRegisters/\registers_reg[4][26] } {/theRegisters/\registers_reg[4][27] } {/theRegisters/\registers_reg[4][28] } {/theRegisters/\registers_reg[4][29] } {/theRegisters/\registers_reg[4][2] } {/theRegisters/\registers_reg[4][30] } {/theRegisters/\registers_reg[4][31] } {/theRegisters/\registers_reg[4][3] } {/theRegisters/\registers_reg[4][4] } {/theRegisters/\registers_reg[4][5] } {/theRegisters/\registers_reg[4][6] } {/theRegisters/\registers_reg[4][7] } {/theRegisters/\registers_reg[4][8] } {/theRegisters/\registers_reg[4][9] } {/theRegisters/\registers_reg[5][0] } {/theRegisters/\registers_reg[5][10] } {/theRegisters/\registers_reg[5][11] } {/theRegisters/\registers_reg[5][12] } {/theRegisters/\registers_reg[5][13] } {/theRegisters/\registers_reg[5][14] } {/theRegisters/\registers_reg[5][15] } {/theRegisters/\registers_reg[5][16] } {/theRegisters/\registers_reg[5][17] } {/theRegisters/\registers_reg[5][18] } {/theRegisters/\registers_reg[5][19] } {/theRegisters/\registers_reg[5][1] } {/theRegisters/\registers_reg[5][20] } {/theRegisters/\registers_reg[5][21] } {/theRegisters/\registers_reg[5][22] } {/theRegisters/\registers_reg[5][23] } {/theRegisters/\registers_reg[5][24] } {/theRegisters/\registers_reg[5][25] } {/theRegisters/\registers_reg[5][26] } {/theRegisters/\registers_reg[5][27] } {/theRegisters/\registers_reg[5][28] } {/theRegisters/\registers_reg[5][29] } {/theRegisters/\registers_reg[5][2] } {/theRegisters/\registers_reg[5][30] } {/theRegisters/\registers_reg[5][31] } {/theRegisters/\registers_reg[5][3] } {/theRegisters/\registers_reg[5][4] } {/theRegisters/\registers_reg[5][5] } {/theRegisters/\registers_reg[5][6] } {/theRegisters/\registers_reg[5][7] } {/theRegisters/\registers_reg[5][8] } {/theRegisters/\registers_reg[5][9] } {/theRegisters/\registers_reg[6][0] } {/theRegisters/\registers_reg[6][10] } {/theRegisters/\registers_reg[6][11] } {/theRegisters/\registers_reg[6][12] } {/theRegisters/\registers_reg[6][13] } {/theRegisters/\registers_reg[6][14] } {/theRegisters/\registers_reg[6][15] } {/theRegisters/\registers_reg[6][16] } {/theRegisters/\registers_reg[6][17] } {/theRegisters/\registers_reg[6][18] } {/theRegisters/\registers_reg[6][19] } {/theRegisters/\registers_reg[6][1] } {/theRegisters/\registers_reg[6][20] } {/theRegisters/\registers_reg[6][21] } {/theRegisters/\registers_reg[6][22] } {/theRegisters/\registers_reg[6][23] } {/theRegisters/\registers_reg[6][24] } {/theRegisters/\registers_reg[6][25] } {/theRegisters/\registers_reg[6][26] } {/theRegisters/\registers_reg[6][27] } {/theRegisters/\registers_reg[6][28] } {/theRegisters/\registers_reg[6][29] } {/theRegisters/\registers_reg[6][2] } {/theRegisters/\registers_reg[6][30] } {/theRegisters/\registers_reg[6][31] } {/theRegisters/\registers_reg[6][3] } {/theRegisters/\registers_reg[6][4] } {/theRegisters/\registers_reg[6][5] } {/theRegisters/\registers_reg[6][6] } {/theRegisters/\registers_reg[6][7] } {/theRegisters/\registers_reg[6][8] } {/theRegisters/\registers_reg[6][9] } {/theRegisters/\registers_reg[7][0] } {/theRegisters/\registers_reg[7][10] } {/theRegisters/\registers_reg[7][11] } {/theRegisters/\registers_reg[7][12] } {/theRegisters/\registers_reg[7][13] } {/theRegisters/\registers_reg[7][14] } {/theRegisters/\registers_reg[7][15] } {/theRegisters/\registers_reg[7][16] } {/theRegisters/\registers_reg[7][17] } {/theRegisters/\registers_reg[7][18] } {/theRegisters/\registers_reg[7][19] } {/theRegisters/\registers_reg[7][1] } {/theRegisters/\registers_reg[7][20] } {/theRegisters/\registers_reg[7][21] } {/theRegisters/\registers_reg[7][22] } {/theRegisters/\registers_reg[7][23] } {/theRegisters/\registers_reg[7][24] } {/theRegisters/\registers_reg[7][25] } {/theRegisters/\registers_reg[7][26] } {/theRegisters/\registers_reg[7][27] } {/theRegisters/\registers_reg[7][28] } {/theRegisters/\registers_reg[7][29] } {/theRegisters/\registers_reg[7][2] } {/theRegisters/\registers_reg[7][30] } {/theRegisters/\registers_reg[7][31] } {/theRegisters/\registers_reg[7][3] } {/theRegisters/\registers_reg[7][4] } {/theRegisters/\registers_reg[7][5] } {/theRegisters/\registers_reg[7][6] } {/theRegisters/\registers_reg[7][7] } {/theRegisters/\registers_reg[7][8] } {/theRegisters/\registers_reg[7][9] } {/theRegisters/\registers_reg[8][0] } {/theRegisters/\registers_reg[8][10] } {/theRegisters/\registers_reg[8][11] } {/theRegisters/\registers_reg[8][12] } {/theRegisters/\registers_reg[8][13] } {/theRegisters/\registers_reg[8][14] } {/theRegisters/\registers_reg[8][15] } {/theRegisters/\registers_reg[8][16] } {/theRegisters/\registers_reg[8][17] } {/theRegisters/\registers_reg[8][18] } {/theRegisters/\registers_reg[8][19] } {/theRegisters/\registers_reg[8][1] } {/theRegisters/\registers_reg[8][20] } {/theRegisters/\registers_reg[8][21] } {/theRegisters/\registers_reg[8][22] } {/theRegisters/\registers_reg[8][23] } {/theRegisters/\registers_reg[8][24] } {/theRegisters/\registers_reg[8][25] } {/theRegisters/\registers_reg[8][26] } {/theRegisters/\registers_reg[8][27] } {/theRegisters/\registers_reg[8][28] } {/theRegisters/\registers_reg[8][29] } {/theRegisters/\registers_reg[8][2] } {/theRegisters/\registers_reg[8][30] } {/theRegisters/\registers_reg[8][31] } {/theRegisters/\registers_reg[8][3] } {/theRegisters/\registers_reg[8][4] } {/theRegisters/\registers_reg[8][5] } {/theRegisters/\registers_reg[8][6] } {/theRegisters/\registers_reg[8][7] } {/theRegisters/\registers_reg[8][8] } {/theRegisters/\registers_reg[8][9] } {/theRegisters/\registers_reg[9][0] } {/theRegisters/\registers_reg[9][10] } {/theRegisters/\registers_reg[9][11] } {/theRegisters/\registers_reg[9][12] } {/theRegisters/\registers_reg[9][13] } {/theRegisters/\registers_reg[9][14] } {/theRegisters/\registers_reg[9][15] } {/theRegisters/\registers_reg[9][16] } {/theRegisters/\registers_reg[9][17] } {/theRegisters/\registers_reg[9][18] } {/theRegisters/\registers_reg[9][19] } {/theRegisters/\registers_reg[9][1] } {/theRegisters/\registers_reg[9][20] } {/theRegisters/\registers_reg[9][21] } {/theRegisters/\registers_reg[9][22] } {/theRegisters/\registers_reg[9][23] } {/theRegisters/\registers_reg[9][24] } {/theRegisters/\registers_reg[9][25] } {/theRegisters/\registers_reg[9][26] } {/theRegisters/\registers_reg[9][27] } {/theRegisters/\registers_reg[9][28] } {/theRegisters/\registers_reg[9][29] } {/theRegisters/\registers_reg[9][2] } {/theRegisters/\registers_reg[9][30] } {/theRegisters/\registers_reg[9][31] } {/theRegisters/\registers_reg[9][3] } {/theRegisters/\registers_reg[9][4] } {/theRegisters/\registers_reg[9][5] } {/theRegisters/\registers_reg[9][6] } {/theRegisters/\registers_reg[9][7] } {/theRegisters/\registers_reg[9][8] } {/theRegisters/\registers_reg[9][9] } } -si_connections {SI_4 } -so_connections {SO_4 } -chain_count 1 +source /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.03/Scan_0/scan_enable_cluster.cfg +analyze_scan_chains +insert_test_logic -write_in_tsdb on +report_scan_chains + +write_scan_order /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.03/Scan_0/cpu.scandef -use_escaping_rule Lefdef -replace +write_design -output_file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.03/Scan_0/post_scan.v -replace + diff --git a/oasys.tessent.03/Scan_0/scan.log b/oasys.tessent.03/Scan_0/scan.log new file mode 100644 index 0000000..223b8bc --- /dev/null +++ b/oasys.tessent.03/Scan_0/scan.log @@ -0,0 +1,409 @@ +/applications/SiemensEDA/siemenseda2023/tessent_2023.4-p1/bin/tessent -shell -dofile /tmp/oasys.2568101/.tmpTessentFile -log_file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.03/Scan_0/scan.log -replace +// Tessent Shell 2023.4-p1 Mon Feb 19 16:22:02 GMT 2024 +// Unpublished work. Copyright 2024 Siemens +// +// This material contains trade secrets or otherwise confidential +// information owned by Siemens Industry Software Inc. or its affiliates +// (collectively, "SISW"), or its licensors. Access to and use of this +// information is strictly limited as set forth in the Customer's +// applicable agreements with SISW. +// +// Siemens software executing under x86-64 Linux on Fri May 29 09:14:17 CEST 2026. +// 64 bit version +// Host: efiapps0.ads1.fh-nuernberg.de (12 x 3.5 GHz, 48014 MB RAM, 24575 MB Swap) +// +// command: if {[catch {source /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.03/Scan_0/scan.do} msg]} { +// puts "$msg" +// puts "TESSENT_ER_ORTL" } +// sub-command: set_context dft -scan -no_rtl -design_id Scan_0 +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_low_temp_ccs.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_low_temp_ccs.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_low_temp_ccs.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_low_temp_ccs.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_low_temp_ccs.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_low_temp_ccs.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/PLL.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/PLL.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/PLL.fslib +// sub-command: read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/IO.fslib +// Reading DFT Library file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/IO.fslib +// Finished reading file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/IO.fslib +// sub-command: set_module_matching_options -suffix_pattern_list {[_]+[0-9]+[_]+[0-9]+} -regexp -append +// sub-command: set_module_matching_options -suffix_pattern_list {[_]+[A-Z]+} -regexp -append +// sub-command: set_module_matching_options -suffix_pattern_list {[_]+[0-9]+[_]+[0-9]+[_]+[A-Z]+} -regexp -append +// sub-command: read_verilog /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.03/Scan_0/oasys_netlist.v +// sub-command: set_tsdb_output_directory /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.03/tsdb_outdir +// sub-command: read_sdc /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.03/Scan_0/oasys.sdc +// Command 'read_sdc' requires an elaborated design. Automatically elaborating the design ... +// Note: 640 duplicate cell library models were read. The last model read of the same name was kept. +// To see detailed messages per duplicate model, issue 'set_cell_library_options -report_duplicate_models on' +// before issuing 'read_cell_library'. +// Warning: 1 cell library model contained 2 floating model outputs. +// To see detailed messages per model, issue 'set_cell_library_options -report_floating_nets on' +// before issuing 'read_cell_library'. +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X1' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X2' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X4' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X8' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X1_HVT' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X2_HVT' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X4_HVT' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X8_HVT' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X1_SVT' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X2_SVT' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X4_SVT' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X8_SVT' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X1_LVT' line 812 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X2_LVT' line 843 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X4_LVT' line 874 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' +// Note: Changing pin 'CK' function from 'active_low_clock' to 'clock_in' +// Model 'CLKGATE_X8_LVT' line 905 file '/users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib' +// Note: Top design is 'cpu'. +// Warning: Undefined modules were found. +// Before using "set_system_mode" or "create_flat_model", you must either define +// the missing modules using "read_verilog" and/or "read_cell_library", or use the +// following command to treat them as black boxes: + add_black_boxes -modules { \ + MemGen_16_10 \ + } +// You can also use "add_black_boxes -auto" to black box all undefined modules but +// it is recommended that you do not add this command to your dofile. Doing so may +// unintentionally black-box new undefined modules in future runs. +// Warning: 32 cases: Unused net in DFT library model +// Warning: 110 cases: Undriven net in netlist module +// Warning: 1 case: Floating input on instance in netlist +// Warning: 47 cases: Net in netlist not connected +// Note: Issue set_current_design with the -show_elaboration_warnings option to see more details about previous warnings +// Design elaboration successful. +// Reading SDC file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.03/Scan_0/oasys.sdc ... +// Finished reading SDC file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.03/Scan_0/oasys.sdc. +// Read SDC summary: 1 false path, 0 multi-cycle paths, 0 erroneous paths +// 0 disable timings, 0 case analysis, 0 clock groups +// sub-command: set_current_design cpu -show_elaboration_warnings +// Warning: Undefined modules were found. +// Before using "set_system_mode" or "create_flat_model", you must either define +// the missing modules using "read_verilog" and/or "read_cell_library", or use the +// following command to treat them as black boxes: + add_black_boxes -modules { \ + MemGen_16_10 \ + } +// You can also use "add_black_boxes -auto" to black box all undefined modules but +// it is recommended that you do not add this command to your dofile. Doing so may +// unintentionally black-box new undefined modules in future runs. +// Warning: Net 'SO_1' in module 'cpu' is not driven +// Warning: Net 'SO_2' in module 'cpu' is not driven +// Warning: Net 'SO_3' in module 'cpu' is not driven +// Warning: Net 'SO_4' in module 'cpu' is not driven +// Warning: Net 'DAddr[31]' in module 'cpu' has no pins +// Warning: Net 'DAddr[30]' in module 'cpu' has no pins +// Warning: Net 'DAddr[29]' in module 'cpu' has no pins +// Warning: Net 'DAddr[28]' in module 'cpu' has no pins +// Warning: Net 'DAddr[27]' in module 'cpu' has no pins +// Warning: Net 'DAddr[26]' in module 'cpu' has no pins +// Warning: Net 'DAddr[25]' in module 'cpu' has no pins +// Warning: Net 'DAddr[24]' in module 'cpu' has no pins +// Warning: Net 'DAddr[23]' in module 'cpu' has no pins +// Warning: Net 'DAddr[22]' in module 'cpu' has no pins +// Warning: Net 'DAddr[21]' in module 'cpu' has no pins +// Warning: Net 'DAddr[20]' in module 'cpu' has no pins +// Warning: Net 'DAddr[19]' in module 'cpu' has no pins +// Warning: Net 'DAddr[18]' in module 'cpu' has no pins +// Warning: Net 'DAddr[17]' in module 'cpu' has no pins +// Warning: Net 'DAddr[16]' in module 'cpu' has no pins +// Warning: Net 'DAddr[15]' in module 'cpu' has no pins +// Warning: Net 'DAddr[14]' in module 'cpu' has no pins +// Warning: Net 'DAddr[13]' in module 'cpu' has no pins +// Warning: Net 'NextPC[31]' in module 'cpu' has no pins +// Warning: Net 'NextPC[30]' in module 'cpu' has no pins +// Warning: Net 'NextPC[29]' in module 'cpu' has no pins +// Warning: Net 'NextPC[28]' in module 'cpu' has no pins +// Warning: Net 'NextPC[27]' in module 'cpu' has no pins +// Warning: Net 'NextPC[26]' in module 'cpu' has no pins +// Warning: Net 'NextPC[25]' in module 'cpu' has no pins +// Warning: Net 'NextPC[24]' in module 'cpu' has no pins +// Warning: Net 'NextPC[23]' in module 'cpu' has no pins +// Warning: Net 'NextPC[22]' in module 'cpu' has no pins +// Warning: Net 'NextPC[21]' in module 'cpu' has no pins +// Warning: Net 'NextPC[20]' in module 'cpu' has no pins +// Warning: Net 'NextPC[19]' in module 'cpu' has no pins +// Warning: Net 'NextPC[18]' in module 'cpu' has no pins +// Warning: Net 'NextPC[17]' in module 'cpu' has no pins +// Warning: Net 'NextPC[16]' in module 'cpu' has no pins +// Warning: Net 'NextPC[15]' in module 'cpu' has no pins +// Warning: Net 'NextPC[14]' in module 'cpu' has no pins +// Warning: Net 'NextPC[13]' in module 'cpu' has no pins +// Warning: Net 'NextPC[7]' in module 'cpu' has no pins +// Warning: Net 'NextPC[6]' in module 'cpu' has no pins +// Warning: Net 'NextPC[5]' in module 'cpu' has no pins +// Warning: Net 'NextPC[4]' in module 'cpu' has no pins +// Warning: Net 'NextPC[3]' in module 'cpu' has no pins +// Warning: Net 'NextPC[2]' in module 'cpu' has no pins +// Warning: Net 'NextPC[1]' in module 'cpu' has no pins +// Warning: Net 'NextPC[0]' in module 'cpu' has no pins +// Warning: Net 'uc_0' in module 'cpu' is not driven +// Warning: Net 'uc_1' in module 'cpu' is not driven +// Warning: Net 'uc_2' in module 'cpu' is not driven +// Warning: Net 'uc_3' in module 'cpu' is not driven +// Warning: Net 'uc_4' in module 'cpu' is not driven +// Warning: Net 'uc_5' in module 'cpu' is not driven +// Warning: Net 'uc_6' in module 'cpu' is not driven +// Warning: Net 'uc_7' in module 'cpu' is not driven +// Warning: Net 'uc_8' in module 'cpu' is not driven +// Warning: Net 'uc_9' in module 'cpu' is not driven +// Warning: Net 'uc_10' in module 'cpu' is not driven +// Warning: Net 'uc_11' in module 'cpu' is not driven +// Warning: Net 'uc_12' in module 'cpu' is not driven +// Warning: Net 'uc_13' in module 'cpu' is not driven +// Warning: Net 'uc_14' in module 'cpu' is not driven +// Warning: Net 'uc_15' in module 'cpu' is not driven +// Warning: Net 'uc_16' in module 'cpu' is not driven +// Warning: Net 'uc_17' in module 'cpu' is not driven +// Warning: Net 'uc_18' in module 'cpu' is not driven +// Warning: Net 'uc_19' in module 'cpu' is not driven +// Warning: Net 'uc_20' in module 'cpu' is not driven +// Warning: Net 'uc_21' in module 'cpu' is not driven +// Warning: Net 'uc_22' in module 'cpu' is not driven +// Warning: Net 'uc_23' in module 'cpu' is not driven +// Warning: Net 'uc_24' in module 'cpu' is not driven +// Warning: Net 'uc_25' in module 'cpu' is not driven +// Warning: Net 'uc_26' in module 'cpu' is not driven +// Warning: Net 'uc_27' in module 'cpu' is not driven +// Warning: Net 'uc_28' in module 'cpu' is not driven +// Warning: Net 'uc_29' in module 'cpu' is not driven +// Warning: Net 'uc_30' in module 'cpu' is not driven +// Warning: Net 'uc_31' in module 'cpu' is not driven +// Warning: Net 'uc_32' in module 'cpu' is not driven +// Warning: Net 'uc_33' in module 'cpu' is not driven +// Warning: Net 'uc_34' in module 'cpu' is not driven +// Warning: Net 'uc_35' in module 'cpu' is not driven +// Warning: Net 'uc_36' in module 'cpu' is not driven +// Warning: Net 'uc_37' in module 'cpu' is not driven +// Warning: Net 'uc_38' in module 'cpu' is not driven +// Warning: Net 'uc_39' in module 'cpu' is not driven +// Warning: Floating input 'chip_en' at instance 'RAM' in module 'main_mem' +// Warning: Net 'mem_sel[1]' in module 'MemGen_32_11' has no pins +// Warning: Net 'DAddr[31]' in module 'decoder' is not driven +// Warning: Net 'DAddr[30]' in module 'decoder' is not driven +// Warning: Net 'DAddr[29]' in module 'decoder' is not driven +// Warning: Net 'DAddr[28]' in module 'decoder' is not driven +// Warning: Net 'DAddr[27]' in module 'decoder' is not driven +// Warning: Net 'DAddr[26]' in module 'decoder' is not driven +// Warning: Net 'DAddr[25]' in module 'decoder' is not driven +// Warning: Net 'DAddr[24]' in module 'decoder' is not driven +// Warning: Net 'DAddr[23]' in module 'decoder' is not driven +// Warning: Net 'DAddr[22]' in module 'decoder' is not driven +// Warning: Net 'DAddr[21]' in module 'decoder' is not driven +// Warning: Net 'DAddr[20]' in module 'decoder' is not driven +// Warning: Net 'DAddr[19]' in module 'decoder' is not driven +// Warning: Net 'DAddr[18]' in module 'decoder' is not driven +// Warning: Net 'DAddr[17]' in module 'decoder' is not driven +// Warning: Net 'DAddr[16]' in module 'decoder' is not driven +// Warning: Net 'DAddr[15]' in module 'decoder' is not driven +// Warning: Net 'DAddr[14]' in module 'decoder' is not driven +// Warning: Net 'DAddr[13]' in module 'decoder' is not driven +// Warning: Net 'WData[31]' in module 'decoder' is not driven +// Warning: Net 'WData[30]' in module 'decoder' is not driven +// Warning: Net 'WData[29]' in module 'decoder' is not driven +// Warning: Net 'WData[28]' in module 'decoder' is not driven +// Warning: Net 'WData[27]' in module 'decoder' is not driven +// Warning: Net 'WData[26]' in module 'decoder' is not driven +// Warning: Net 'WData[25]' in module 'decoder' is not driven +// Warning: Net 'WData[24]' in module 'decoder' is not driven +// Warning: Net 'WData[23]' in module 'decoder' is not driven +// Warning: Net 'WData[22]' in module 'decoder' is not driven +// Warning: Net 'WData[21]' in module 'decoder' is not driven +// Warning: Net 'WData[20]' in module 'decoder' is not driven +// Warning: Net 'WData[19]' in module 'decoder' is not driven +// Warning: Net 'WData[18]' in module 'decoder' is not driven +// Warning: Net 'WData[17]' in module 'decoder' is not driven +// Warning: Net 'WData[16]' in module 'decoder' is not driven +// Warning: Net 'WData[15]' in module 'decoder' is not driven +// Warning: Net 'WData[14]' in module 'decoder' is not driven +// Warning: Net 'WData[13]' in module 'decoder' is not driven +// Warning: Net 'WData[12]' in module 'decoder' is not driven +// Warning: Net 'WData[11]' in module 'decoder' is not driven +// Warning: Net 'WData[10]' in module 'decoder' is not driven +// Warning: Net 'WData[9]' in module 'decoder' is not driven +// Warning: Net 'WData[8]' in module 'decoder' is not driven +// Warning: Net 'WData[7]' in module 'decoder' is not driven +// Warning: Net 'WData[6]' in module 'decoder' is not driven +// Warning: Net 'WData[5]' in module 'decoder' is not driven +// Warning: Net 'WData[4]' in module 'decoder' is not driven +// Warning: Net 'WData[3]' in module 'decoder' is not driven +// Warning: Net 'WData[2]' in module 'decoder' is not driven +// Warning: Net 'WData[1]' in module 'decoder' is not driven +// Warning: Net 'WData[0]' in module 'decoder' is not driven +// Warning: Net 'Rs1[4]' in module 'decoder' is not driven +// Warning: Net 'Rs1[3]' in module 'decoder' is not driven +// Warning: Net 'Rs1[2]' in module 'decoder' is not driven +// Warning: Net 'Rs1[1]' in module 'decoder' is not driven +// Warning: Net 'Rs1[0]' in module 'decoder' is not driven +// Warning: Net 'Rs2[4]' in module 'decoder' is not driven +// Warning: Net 'Rs2[3]' in module 'decoder' is not driven +// Warning: Net 'Rs2[2]' in module 'decoder' is not driven +// Warning: Net 'Rs2[1]' in module 'decoder' is not driven +// Warning: Net 'Rs2[0]' in module 'decoder' is not driven +// Warning: Net 'Rd[4]' in module 'decoder' is not driven +// Warning: Net 'Rd[3]' in module 'decoder' is not driven +// Warning: Net 'Rd[2]' in module 'decoder' is not driven +// Warning: Net 'Rd[1]' in module 'decoder' is not driven +// Warning: Net 'Rd[0]' in module 'decoder' is not driven +// sub-command: set_design_level physical_block +// sub-command: set_shift_register_identification off +// sub-command: add_nonscan_instances -instances "{/theMem/\IRData_reg[31] } {/theMem/\IRData_reg[30] } {/theMem/\IRData_reg[29] } {/theMem/\IRData_reg[28] } {/theMem/\IRData_reg[27] } {/theMem/\IRData_reg[26] } {/theMem/\IRData_reg[25] } {/theMem/\IRData_reg[24] } {/theMem/\IRData_reg[23] } {/theMem/\IRData_reg[22] } {/theMem/\IRData_reg[21] } {/theMem/\IRData_reg[20] } {/theMem/\IRData_reg[19] } {/theMem/\IRData_reg[18] } {/theMem/\IRData_reg[17] } {/theMem/\IRData_reg[16] } {/theMem/\IRData_reg[15] } {/theMem/\IRData_reg[14] } {/theMem/\IRData_reg[13] } {/theMem/\IRData_reg[12] } {/theMem/\IRData_reg[11] } {/theMem/\IRData_reg[10] } {/theMem/\IRData_reg[9] } {/theMem/\IRData_reg[8] } {/theMem/\IRData_reg[7] } {/theMem/\IRData_reg[6] } {/theMem/\IRData_reg[5] } {/theMem/\IRData_reg[4] } {/theMem/\IRData_reg[3] } {/theMem/\IRData_reg[2] } {/theMem/\IRData_reg[1] } {/theMem/\IRData_reg[0] } {/theMem/\mem_addr_reg[10] } {/theMem/\mem_addr_reg[9] } {/theMem/\mem_addr_reg[8] } {/theMem/\mem_addr_reg[7] } {/theMem/\mem_addr_reg[6] } {/theMem/\mem_addr_reg[5] } {/theMem/\mem_addr_reg[4] } {/theMem/\mem_addr_reg[3] } {/theMem/\mem_addr_reg[2] } {/theMem/\mem_addr_reg[1] } {/theMem/\mem_addr_reg[0] } {/theMem/\drTmp_reg[31] } {/theMem/\drTmp_reg[30] } {/theMem/\drTmp_reg[29] } {/theMem/\drTmp_reg[28] } {/theMem/\drTmp_reg[27] } {/theMem/\drTmp_reg[26] } {/theMem/\drTmp_reg[25] } {/theMem/\drTmp_reg[24] } {/theMem/\drTmp_reg[23] } {/theMem/\drTmp_reg[22] } {/theMem/\drTmp_reg[21] } {/theMem/\drTmp_reg[20] } {/theMem/\drTmp_reg[19] } {/theMem/\drTmp_reg[18] } {/theMem/\drTmp_reg[17] } {/theMem/\drTmp_reg[16] } {/theMem/\drTmp_reg[15] } {/theMem/\drTmp_reg[14] } {/theMem/\drTmp_reg[13] } {/theMem/\drTmp_reg[12] } {/theMem/\drTmp_reg[11] } {/theMem/\drTmp_reg[10] } {/theMem/\drTmp_reg[9] } {/theMem/\drTmp_reg[8] } {/theMem/\drTmp_reg[7] } {/theMem/\drTmp_reg[6] } {/theMem/\drTmp_reg[5] } {/theMem/\drTmp_reg[4] } {/theMem/\drTmp_reg[3] } {/theMem/\drTmp_reg[2] } {/theMem/\drTmp_reg[1] } {/theMem/\drTmp_reg[0] } {/theMem/\mem_wdata_reg[31] } {/theMem/\mem_wdata_reg[30] } {/theMem/\mem_wdata_reg[29] } {/theMem/\mem_wdata_reg[28] } {/theMem/\mem_wdata_reg[27] } {/theMem/\mem_wdata_reg[26] } {/theMem/\mem_wdata_reg[25] } {/theMem/\mem_wdata_reg[24] } {/theMem/\mem_wdata_reg[23] } {/theMem/\mem_wdata_reg[22] } {/theMem/\mem_wdata_reg[21] } {/theMem/\mem_wdata_reg[20] } {/theMem/\mem_wdata_reg[19] } {/theMem/\mem_wdata_reg[18] } {/theMem/\mem_wdata_reg[17] } {/theMem/\mem_wdata_reg[16] } {/theMem/\mem_wdata_reg[15] } {/theMem/\mem_wdata_reg[14] } {/theMem/\mem_wdata_reg[13] } {/theMem/\mem_wdata_reg[12] } {/theMem/\mem_wdata_reg[11] } {/theMem/\mem_wdata_reg[10] } {/theMem/\mem_wdata_reg[9] } {/theMem/\mem_wdata_reg[8] } {/theMem/\mem_wdata_reg[7] } {/theMem/\mem_wdata_reg[6] } {/theMem/\mem_wdata_reg[5] } {/theMem/\mem_wdata_reg[4] } {/theMem/\mem_wdata_reg[3] } {/theMem/\mem_wdata_reg[2] } {/theMem/\mem_wdata_reg[1] } {/theMem/\mem_wdata_reg[0] } " +// sub-command: add_clocks 0 " clk_25mhz " +// sub-command: set_scan_enable scan_en -active high +// sub-command: add_input_constraints btn[0] -C1 +// sub-command: set_scan_enable scan_en -active high -cluster_name scanChain_1 +// sub-command: set_scan_enable scan_en -active high -cluster_name scanChain_2 +// sub-command: set_scan_enable scan_en -active high -cluster_name scanChain_3 +// sub-command: set_scan_enable scan_en -active high -cluster_name scanChain_4 +// sub-command: add_black_boxes -modules " MemGen_16_10 " +// sub-command: set_scan_insertion_options -single_clock_edge_chains on -si_port_format oas_ts_si[%d] -so_port_format oas_ts_so[%d] +// sub-command: set_system_mode analysis +// Warning: Rule FN1 violation occurs 157 times +// Warning: Rule FP13 violation occurs 1 times +// Flattening process completed, cell instances=4379, gates=18234, PIs=13, POs=12, CPU time=0.09 sec. +// --------------------------------------------------------------------------- +// Begin circuit learning analyses. +// -------------------------------- +// Learning completed, CPU time=0.01 sec. +// --------------------------------------------------------------------------- +// Begin scan chain identification process, memory elements = 1194, +// sequential library cells = 1194. +// --------------------------------------------------------------------------- +// Warning: Model 'DLH_X1_LVT' has no muxscan scan equivalent and is treated as nonscan model +// ------------------------------------------------------------------------------ +// 170 sequential library cells are treated as non-scan. +// ------------------------------------------------------------------------------ +// 63 sequential library cells missing mux-scan equivalent. +// 107 sequential library cells defined non-scan. +// --------------------------------------------------------------------------- +// Begin scannability rules checking for 1024 sequential library cells. +// --------------------------------------------------------------------------- +// 1024 sequential library cells identified as scannable. +// --------------------------------------------------------------------------- +// Begin transparent latch checking for 63 latches. +// --------------------------------------------------------------------------- +// Warning: 32 latches not transparent due to uncontrollable. (D6) +// Number transparent latches = 31. +// --------------------------------------------------------------------------- +// Begin scan clock rules checking. +// --------------------------------------------------------------------------- +// 1 scan clock/set/reset lines have been identified. +// All scan clocks successfully passed off-state check. +// 1131 sequential cells passed clock stability checking. +// There were 43 clock rule C3 fails (clock may capture data affected by its captured data). +// Note: Trailing edge triggered device can capture data affected by leading edge. +// --------------------------------------------------------------------------- +// 170 non-scan memory elements are identified. +// --------------------------------------------------------------------------- +// 32 non-scan memory elements are identified as TIE-X. (D5) +// 107 non-scan memory elements are identified as INIT-X. (D5) +// 31 non-scan memory elements are identified as TLA. (D5) +// --------------------------------------------------------------------------- +// Number of targeted sequential library cells = 1024 +// Warning: The tool may require a shift-capture clock during insertion, +// but no 'shift_capture_clock' DFT signal was identified +// and no TCLK source was specified using the command 'set_scan_signals -tclk'. +// Note: The system clock 'clk_25mhz' will be used as the shift-capture clock, if needed. +// sub-command: report_drc_rules +C3: #fails=43 handling=note (clock may capture data affected by its captured data) +D5: #fails=170 handling=warning (non-scan memory element) +D6: #fails=32 handling=warning (non-transparent non-scan latches) +// sub-command: create_scan_chain_family scanChain_1 -include_elements "{/\thePC_CurrentPC_reg[0] } {/\thePC_CurrentPC_reg[10] } {/\thePC_CurrentPC_reg[11] } {/\thePC_CurrentPC_reg[12] } {/\thePC_CurrentPC_reg[13] } {/\thePC_CurrentPC_reg[14] } {/\thePC_CurrentPC_reg[15] } {/\thePC_CurrentPC_reg[16] } {/\thePC_CurrentPC_reg[17] } {/\thePC_CurrentPC_reg[18] } {/\thePC_CurrentPC_reg[19] } {/\thePC_CurrentPC_reg[1] } {/\thePC_CurrentPC_reg[20] } {/\thePC_CurrentPC_reg[21] } {/\thePC_CurrentPC_reg[22] } {/\thePC_CurrentPC_reg[23] } {/\thePC_CurrentPC_reg[24] } {/\thePC_CurrentPC_reg[25] } {/\thePC_CurrentPC_reg[26] } {/\thePC_CurrentPC_reg[27] } {/\thePC_CurrentPC_reg[28] } {/\thePC_CurrentPC_reg[29] } {/\thePC_CurrentPC_reg[2] } {/\thePC_CurrentPC_reg[30] } {/\thePC_CurrentPC_reg[31] } {/\thePC_CurrentPC_reg[3] } {/\thePC_CurrentPC_reg[4] } {/\thePC_CurrentPC_reg[5] } {/\thePC_CurrentPC_reg[6] } {/\thePC_CurrentPC_reg[7] } {/\thePC_CurrentPC_reg[8] } {/\thePC_CurrentPC_reg[9] } {/theRegisters/\registers_reg[10][0] } {/theRegisters/\registers_reg[10][10] } {/theRegisters/\registers_reg[10][11] } {/theRegisters/\registers_reg[10][12] } {/theRegisters/\registers_reg[10][13] } {/theRegisters/\registers_reg[10][14] } {/theRegisters/\registers_reg[10][15] } {/theRegisters/\registers_reg[10][16] } {/theRegisters/\registers_reg[10][17] } {/theRegisters/\registers_reg[10][18] } {/theRegisters/\registers_reg[10][19] } {/theRegisters/\registers_reg[10][1] } {/theRegisters/\registers_reg[10][20] } {/theRegisters/\registers_reg[10][21] } {/theRegisters/\registers_reg[10][22] } {/theRegisters/\registers_reg[10][23] } {/theRegisters/\registers_reg[10][24] } {/theRegisters/\registers_reg[10][25] } {/theRegisters/\registers_reg[10][26] } {/theRegisters/\registers_reg[10][27] } {/theRegisters/\registers_reg[10][28] } {/theRegisters/\registers_reg[10][29] } {/theRegisters/\registers_reg[10][2] } {/theRegisters/\registers_reg[10][30] } {/theRegisters/\registers_reg[10][31] } {/theRegisters/\registers_reg[10][3] } {/theRegisters/\registers_reg[10][4] } {/theRegisters/\registers_reg[10][5] } {/theRegisters/\registers_reg[10][6] } {/theRegisters/\registers_reg[10][7] } {/theRegisters/\registers_reg[10][8] } {/theRegisters/\registers_reg[10][9] } {/theRegisters/\registers_reg[11][0] } {/theRegisters/\registers_reg[11][10] } {/theRegisters/\registers_reg[11][11] } {/theRegisters/\registers_reg[11][12] } {/theRegisters/\registers_reg[11][13] } {/theRegisters/\registers_reg[11][14] } {/theRegisters/\registers_reg[11][15] } {/theRegisters/\registers_reg[11][16] } {/theRegisters/\registers_reg[11][17] } {/theRegisters/\registers_reg[11][18] } {/theRegisters/\registers_reg[11][19] } {/theRegisters/\registers_reg[11][1] } {/theRegisters/\registers_reg[11][20] } {/theRegisters/\registers_reg[11][21] } {/theRegisters/\registers_reg[11][22] } {/theRegisters/\registers_reg[11][23] } {/theRegisters/\registers_reg[11][24] } {/theRegisters/\registers_reg[11][25] } {/theRegisters/\registers_reg[11][26] } {/theRegisters/\registers_reg[11][27] } {/theRegisters/\registers_reg[11][28] } {/theRegisters/\registers_reg[11][29] } {/theRegisters/\registers_reg[11][2] } {/theRegisters/\registers_reg[11][30] } {/theRegisters/\registers_reg[11][31] } {/theRegisters/\registers_reg[11][3] } {/theRegisters/\registers_reg[11][4] } {/theRegisters/\registers_reg[11][5] } {/theRegisters/\registers_reg[11][6] } {/theRegisters/\registers_reg[11][7] } {/theRegisters/\registers_reg[11][8] } {/theRegisters/\registers_reg[11][9] } {/theRegisters/\registers_reg[12][0] } {/theRegisters/\registers_reg[12][10] } {/theRegisters/\registers_reg[12][11] } {/theRegisters/\registers_reg[12][12] } {/theRegisters/\registers_reg[12][13] } {/theRegisters/\registers_reg[12][14] } {/theRegisters/\registers_reg[12][15] } {/theRegisters/\registers_reg[12][16] } {/theRegisters/\registers_reg[12][17] } {/theRegisters/\registers_reg[12][18] } {/theRegisters/\registers_reg[12][19] } {/theRegisters/\registers_reg[12][1] } {/theRegisters/\registers_reg[12][20] } {/theRegisters/\registers_reg[12][21] } {/theRegisters/\registers_reg[12][22] } {/theRegisters/\registers_reg[12][23] } {/theRegisters/\registers_reg[12][24] } {/theRegisters/\registers_reg[12][25] } {/theRegisters/\registers_reg[12][26] } {/theRegisters/\registers_reg[12][27] } {/theRegisters/\registers_reg[12][28] } {/theRegisters/\registers_reg[12][29] } {/theRegisters/\registers_reg[12][2] } {/theRegisters/\registers_reg[12][30] } {/theRegisters/\registers_reg[12][31] } {/theRegisters/\registers_reg[12][3] } {/theRegisters/\registers_reg[12][4] } {/theRegisters/\registers_reg[12][5] } {/theRegisters/\registers_reg[12][6] } {/theRegisters/\registers_reg[12][7] } {/theRegisters/\registers_reg[12][8] } {/theRegisters/\registers_reg[12][9] } {/theRegisters/\registers_reg[13][0] } {/theRegisters/\registers_reg[13][10] } {/theRegisters/\registers_reg[13][11] } {/theRegisters/\registers_reg[13][12] } {/theRegisters/\registers_reg[13][13] } {/theRegisters/\registers_reg[13][14] } {/theRegisters/\registers_reg[13][15] } {/theRegisters/\registers_reg[13][16] } {/theRegisters/\registers_reg[13][17] } {/theRegisters/\registers_reg[13][18] } {/theRegisters/\registers_reg[13][19] } {/theRegisters/\registers_reg[13][1] } {/theRegisters/\registers_reg[13][20] } {/theRegisters/\registers_reg[13][21] } {/theRegisters/\registers_reg[13][22] } {/theRegisters/\registers_reg[13][23] } {/theRegisters/\registers_reg[13][24] } {/theRegisters/\registers_reg[13][25] } {/theRegisters/\registers_reg[13][26] } {/theRegisters/\registers_reg[13][27] } {/theRegisters/\registers_reg[13][28] } {/theRegisters/\registers_reg[13][29] } {/theRegisters/\registers_reg[13][2] } {/theRegisters/\registers_reg[13][30] } {/theRegisters/\registers_reg[13][31] } {/theRegisters/\registers_reg[13][3] } {/theRegisters/\registers_reg[13][4] } {/theRegisters/\registers_reg[13][5] } {/theRegisters/\registers_reg[13][6] } {/theRegisters/\registers_reg[13][7] } {/theRegisters/\registers_reg[13][8] } {/theRegisters/\registers_reg[13][9] } {/theRegisters/\registers_reg[14][0] } {/theRegisters/\registers_reg[14][10] } {/theRegisters/\registers_reg[14][11] } {/theRegisters/\registers_reg[14][12] } {/theRegisters/\registers_reg[14][13] } {/theRegisters/\registers_reg[14][14] } {/theRegisters/\registers_reg[14][15] } {/theRegisters/\registers_reg[14][16] } {/theRegisters/\registers_reg[14][17] } {/theRegisters/\registers_reg[14][18] } {/theRegisters/\registers_reg[14][19] } {/theRegisters/\registers_reg[14][1] } {/theRegisters/\registers_reg[14][20] } {/theRegisters/\registers_reg[14][21] } {/theRegisters/\registers_reg[14][22] } {/theRegisters/\registers_reg[14][23] } {/theRegisters/\registers_reg[14][24] } {/theRegisters/\registers_reg[14][25] } {/theRegisters/\registers_reg[14][26] } {/theRegisters/\registers_reg[14][27] } {/theRegisters/\registers_reg[14][28] } {/theRegisters/\registers_reg[14][29] } {/theRegisters/\registers_reg[14][2] } {/theRegisters/\registers_reg[14][30] } {/theRegisters/\registers_reg[14][31] } {/theRegisters/\registers_reg[14][3] } {/theRegisters/\registers_reg[14][4] } {/theRegisters/\registers_reg[14][5] } {/theRegisters/\registers_reg[14][6] } {/theRegisters/\registers_reg[14][7] } {/theRegisters/\registers_reg[14][8] } {/theRegisters/\registers_reg[14][9] } {/theRegisters/\registers_reg[15][0] } {/theRegisters/\registers_reg[15][10] } {/theRegisters/\registers_reg[15][11] } {/theRegisters/\registers_reg[15][12] } {/theRegisters/\registers_reg[15][13] } {/theRegisters/\registers_reg[15][14] } {/theRegisters/\registers_reg[15][15] } {/theRegisters/\registers_reg[15][16] } {/theRegisters/\registers_reg[15][17] } {/theRegisters/\registers_reg[15][18] } {/theRegisters/\registers_reg[15][19] } {/theRegisters/\registers_reg[15][1] } {/theRegisters/\registers_reg[15][20] } {/theRegisters/\registers_reg[15][21] } {/theRegisters/\registers_reg[15][22] } {/theRegisters/\registers_reg[15][23] } {/theRegisters/\registers_reg[15][24] } {/theRegisters/\registers_reg[15][25] } {/theRegisters/\registers_reg[15][26] } {/theRegisters/\registers_reg[15][27] } {/theRegisters/\registers_reg[15][28] } {/theRegisters/\registers_reg[15][29] } {/theRegisters/\registers_reg[15][2] } {/theRegisters/\registers_reg[15][30] } {/theRegisters/\registers_reg[15][31] } {/theRegisters/\registers_reg[15][3] } {/theRegisters/\registers_reg[15][4] } {/theRegisters/\registers_reg[15][5] } {/theRegisters/\registers_reg[15][6] } {/theRegisters/\registers_reg[15][7] } {/theRegisters/\registers_reg[15][8] } {/theRegisters/\registers_reg[15][9] } {/theRegisters/\registers_reg[16][0] } {/theRegisters/\registers_reg[16][10] } {/theRegisters/\registers_reg[16][11] } {/theRegisters/\registers_reg[16][12] } {/theRegisters/\registers_reg[16][13] } {/theRegisters/\registers_reg[16][14] } {/theRegisters/\registers_reg[16][15] } {/theRegisters/\registers_reg[16][16] } {/theRegisters/\registers_reg[16][17] } {/theRegisters/\registers_reg[16][18] } {/theRegisters/\registers_reg[16][19] } {/theRegisters/\registers_reg[16][1] } {/theRegisters/\registers_reg[16][20] } {/theRegisters/\registers_reg[16][21] } {/theRegisters/\registers_reg[16][22] } {/theRegisters/\registers_reg[16][23] } {/theRegisters/\registers_reg[16][24] } {/theRegisters/\registers_reg[16][25] } {/theRegisters/\registers_reg[16][26] } {/theRegisters/\registers_reg[16][27] } {/theRegisters/\registers_reg[16][28] } {/theRegisters/\registers_reg[16][29] } {/theRegisters/\registers_reg[16][2] } {/theRegisters/\registers_reg[16][30] } {/theRegisters/\registers_reg[16][31] } {/theRegisters/\registers_reg[16][3] } {/theRegisters/\registers_reg[16][4] } {/theRegisters/\registers_reg[16][5] } {/theRegisters/\registers_reg[16][6] } {/theRegisters/\registers_reg[16][7] } {/theRegisters/\registers_reg[16][8] } {/theRegisters/\registers_reg[16][9] } " -si_connections "SI_1 " -so_connections "SO_1 " -chain_count 1 +// sub-command: create_scan_chain_family scanChain_2 -include_elements "{/theRegisters/\registers_reg[17][0] } {/theRegisters/\registers_reg[17][10] } {/theRegisters/\registers_reg[17][11] } {/theRegisters/\registers_reg[17][12] } {/theRegisters/\registers_reg[17][13] } {/theRegisters/\registers_reg[17][14] } {/theRegisters/\registers_reg[17][15] } {/theRegisters/\registers_reg[17][16] } {/theRegisters/\registers_reg[17][17] } {/theRegisters/\registers_reg[17][18] } {/theRegisters/\registers_reg[17][19] } {/theRegisters/\registers_reg[17][1] } {/theRegisters/\registers_reg[17][20] } {/theRegisters/\registers_reg[17][21] } {/theRegisters/\registers_reg[17][22] } {/theRegisters/\registers_reg[17][23] } {/theRegisters/\registers_reg[17][24] } {/theRegisters/\registers_reg[17][25] } {/theRegisters/\registers_reg[17][26] } {/theRegisters/\registers_reg[17][27] } {/theRegisters/\registers_reg[17][28] } {/theRegisters/\registers_reg[17][29] } {/theRegisters/\registers_reg[17][2] } {/theRegisters/\registers_reg[17][30] } {/theRegisters/\registers_reg[17][31] } {/theRegisters/\registers_reg[17][3] } {/theRegisters/\registers_reg[17][4] } {/theRegisters/\registers_reg[17][5] } {/theRegisters/\registers_reg[17][6] } {/theRegisters/\registers_reg[17][7] } {/theRegisters/\registers_reg[17][8] } {/theRegisters/\registers_reg[17][9] } {/theRegisters/\registers_reg[18][0] } {/theRegisters/\registers_reg[18][10] } {/theRegisters/\registers_reg[18][11] } {/theRegisters/\registers_reg[18][12] } {/theRegisters/\registers_reg[18][13] } {/theRegisters/\registers_reg[18][14] } {/theRegisters/\registers_reg[18][15] } {/theRegisters/\registers_reg[18][16] } {/theRegisters/\registers_reg[18][17] } {/theRegisters/\registers_reg[18][18] } {/theRegisters/\registers_reg[18][19] } {/theRegisters/\registers_reg[18][1] } {/theRegisters/\registers_reg[18][20] } {/theRegisters/\registers_reg[18][21] } {/theRegisters/\registers_reg[18][22] } {/theRegisters/\registers_reg[18][23] } {/theRegisters/\registers_reg[18][24] } {/theRegisters/\registers_reg[18][25] } {/theRegisters/\registers_reg[18][26] } {/theRegisters/\registers_reg[18][27] } {/theRegisters/\registers_reg[18][28] } {/theRegisters/\registers_reg[18][29] } {/theRegisters/\registers_reg[18][2] } {/theRegisters/\registers_reg[18][30] } {/theRegisters/\registers_reg[18][31] } {/theRegisters/\registers_reg[18][3] } {/theRegisters/\registers_reg[18][4] } {/theRegisters/\registers_reg[18][5] } {/theRegisters/\registers_reg[18][6] } {/theRegisters/\registers_reg[18][7] } {/theRegisters/\registers_reg[18][8] } {/theRegisters/\registers_reg[18][9] } {/theRegisters/\registers_reg[19][0] } {/theRegisters/\registers_reg[19][10] } {/theRegisters/\registers_reg[19][11] } {/theRegisters/\registers_reg[19][12] } {/theRegisters/\registers_reg[19][13] } {/theRegisters/\registers_reg[19][14] } {/theRegisters/\registers_reg[19][15] } {/theRegisters/\registers_reg[19][16] } {/theRegisters/\registers_reg[19][17] } {/theRegisters/\registers_reg[19][18] } {/theRegisters/\registers_reg[19][19] } {/theRegisters/\registers_reg[19][1] } {/theRegisters/\registers_reg[19][20] } {/theRegisters/\registers_reg[19][21] } {/theRegisters/\registers_reg[19][22] } {/theRegisters/\registers_reg[19][23] } {/theRegisters/\registers_reg[19][24] } {/theRegisters/\registers_reg[19][25] } {/theRegisters/\registers_reg[19][26] } {/theRegisters/\registers_reg[19][27] } {/theRegisters/\registers_reg[19][28] } {/theRegisters/\registers_reg[19][29] } {/theRegisters/\registers_reg[19][2] } {/theRegisters/\registers_reg[19][30] } {/theRegisters/\registers_reg[19][31] } {/theRegisters/\registers_reg[19][3] } {/theRegisters/\registers_reg[19][4] } {/theRegisters/\registers_reg[19][5] } {/theRegisters/\registers_reg[19][6] } {/theRegisters/\registers_reg[19][7] } {/theRegisters/\registers_reg[19][8] } {/theRegisters/\registers_reg[19][9] } {/theRegisters/\registers_reg[1][0] } {/theRegisters/\registers_reg[1][10] } {/theRegisters/\registers_reg[1][11] } {/theRegisters/\registers_reg[1][12] } {/theRegisters/\registers_reg[1][13] } {/theRegisters/\registers_reg[1][14] } {/theRegisters/\registers_reg[1][15] } {/theRegisters/\registers_reg[1][16] } {/theRegisters/\registers_reg[1][17] } {/theRegisters/\registers_reg[1][18] } {/theRegisters/\registers_reg[1][19] } {/theRegisters/\registers_reg[1][1] } {/theRegisters/\registers_reg[1][20] } {/theRegisters/\registers_reg[1][21] } {/theRegisters/\registers_reg[1][22] } {/theRegisters/\registers_reg[1][23] } {/theRegisters/\registers_reg[1][24] } {/theRegisters/\registers_reg[1][25] } {/theRegisters/\registers_reg[1][26] } {/theRegisters/\registers_reg[1][27] } {/theRegisters/\registers_reg[1][28] } {/theRegisters/\registers_reg[1][29] } {/theRegisters/\registers_reg[1][2] } {/theRegisters/\registers_reg[1][30] } {/theRegisters/\registers_reg[1][31] } {/theRegisters/\registers_reg[1][3] } {/theRegisters/\registers_reg[1][4] } {/theRegisters/\registers_reg[1][5] } {/theRegisters/\registers_reg[1][6] } {/theRegisters/\registers_reg[1][7] } {/theRegisters/\registers_reg[1][8] } {/theRegisters/\registers_reg[1][9] } {/theRegisters/\registers_reg[20][0] } {/theRegisters/\registers_reg[20][10] } {/theRegisters/\registers_reg[20][11] } {/theRegisters/\registers_reg[20][12] } {/theRegisters/\registers_reg[20][13] } {/theRegisters/\registers_reg[20][14] } {/theRegisters/\registers_reg[20][15] } {/theRegisters/\registers_reg[20][16] } {/theRegisters/\registers_reg[20][17] } {/theRegisters/\registers_reg[20][18] } {/theRegisters/\registers_reg[20][19] } {/theRegisters/\registers_reg[20][1] } {/theRegisters/\registers_reg[20][20] } {/theRegisters/\registers_reg[20][21] } {/theRegisters/\registers_reg[20][22] } {/theRegisters/\registers_reg[20][23] } {/theRegisters/\registers_reg[20][24] } {/theRegisters/\registers_reg[20][25] } {/theRegisters/\registers_reg[20][26] } {/theRegisters/\registers_reg[20][27] } {/theRegisters/\registers_reg[20][28] } {/theRegisters/\registers_reg[20][29] } {/theRegisters/\registers_reg[20][2] } {/theRegisters/\registers_reg[20][30] } {/theRegisters/\registers_reg[20][31] } {/theRegisters/\registers_reg[20][3] } {/theRegisters/\registers_reg[20][4] } {/theRegisters/\registers_reg[20][5] } {/theRegisters/\registers_reg[20][6] } {/theRegisters/\registers_reg[20][7] } {/theRegisters/\registers_reg[20][8] } {/theRegisters/\registers_reg[20][9] } {/theRegisters/\registers_reg[21][0] } {/theRegisters/\registers_reg[21][10] } {/theRegisters/\registers_reg[21][11] } {/theRegisters/\registers_reg[21][12] } {/theRegisters/\registers_reg[21][13] } {/theRegisters/\registers_reg[21][14] } {/theRegisters/\registers_reg[21][15] } {/theRegisters/\registers_reg[21][16] } {/theRegisters/\registers_reg[21][17] } {/theRegisters/\registers_reg[21][18] } {/theRegisters/\registers_reg[21][19] } {/theRegisters/\registers_reg[21][1] } {/theRegisters/\registers_reg[21][20] } {/theRegisters/\registers_reg[21][21] } {/theRegisters/\registers_reg[21][22] } {/theRegisters/\registers_reg[21][23] } {/theRegisters/\registers_reg[21][24] } {/theRegisters/\registers_reg[21][25] } {/theRegisters/\registers_reg[21][26] } {/theRegisters/\registers_reg[21][27] } {/theRegisters/\registers_reg[21][28] } {/theRegisters/\registers_reg[21][29] } {/theRegisters/\registers_reg[21][2] } {/theRegisters/\registers_reg[21][30] } {/theRegisters/\registers_reg[21][31] } {/theRegisters/\registers_reg[21][3] } {/theRegisters/\registers_reg[21][4] } {/theRegisters/\registers_reg[21][5] } {/theRegisters/\registers_reg[21][6] } {/theRegisters/\registers_reg[21][7] } {/theRegisters/\registers_reg[21][8] } {/theRegisters/\registers_reg[21][9] } {/theRegisters/\registers_reg[22][0] } {/theRegisters/\registers_reg[22][10] } {/theRegisters/\registers_reg[22][11] } {/theRegisters/\registers_reg[22][12] } {/theRegisters/\registers_reg[22][13] } {/theRegisters/\registers_reg[22][14] } {/theRegisters/\registers_reg[22][15] } {/theRegisters/\registers_reg[22][16] } {/theRegisters/\registers_reg[22][17] } {/theRegisters/\registers_reg[22][18] } {/theRegisters/\registers_reg[22][19] } {/theRegisters/\registers_reg[22][1] } {/theRegisters/\registers_reg[22][20] } {/theRegisters/\registers_reg[22][21] } {/theRegisters/\registers_reg[22][22] } {/theRegisters/\registers_reg[22][23] } {/theRegisters/\registers_reg[22][24] } {/theRegisters/\registers_reg[22][25] } {/theRegisters/\registers_reg[22][26] } {/theRegisters/\registers_reg[22][27] } {/theRegisters/\registers_reg[22][28] } {/theRegisters/\registers_reg[22][29] } {/theRegisters/\registers_reg[22][2] } {/theRegisters/\registers_reg[22][30] } {/theRegisters/\registers_reg[22][31] } {/theRegisters/\registers_reg[22][3] } {/theRegisters/\registers_reg[22][4] } {/theRegisters/\registers_reg[22][5] } {/theRegisters/\registers_reg[22][6] } {/theRegisters/\registers_reg[22][7] } {/theRegisters/\registers_reg[22][8] } {/theRegisters/\registers_reg[22][9] } {/theRegisters/\registers_reg[23][0] } {/theRegisters/\registers_reg[23][10] } {/theRegisters/\registers_reg[23][11] } {/theRegisters/\registers_reg[23][12] } {/theRegisters/\registers_reg[23][13] } {/theRegisters/\registers_reg[23][14] } {/theRegisters/\registers_reg[23][15] } {/theRegisters/\registers_reg[23][16] } {/theRegisters/\registers_reg[23][17] } {/theRegisters/\registers_reg[23][18] } {/theRegisters/\registers_reg[23][19] } {/theRegisters/\registers_reg[23][1] } {/theRegisters/\registers_reg[23][20] } {/theRegisters/\registers_reg[23][21] } {/theRegisters/\registers_reg[23][22] } {/theRegisters/\registers_reg[23][23] } {/theRegisters/\registers_reg[23][24] } {/theRegisters/\registers_reg[23][25] } {/theRegisters/\registers_reg[23][26] } {/theRegisters/\registers_reg[23][27] } {/theRegisters/\registers_reg[23][28] } {/theRegisters/\registers_reg[23][29] } {/theRegisters/\registers_reg[23][2] } {/theRegisters/\registers_reg[23][30] } {/theRegisters/\registers_reg[23][31] } {/theRegisters/\registers_reg[23][3] } {/theRegisters/\registers_reg[23][4] } {/theRegisters/\registers_reg[23][5] } {/theRegisters/\registers_reg[23][6] } {/theRegisters/\registers_reg[23][7] } {/theRegisters/\registers_reg[23][8] } {/theRegisters/\registers_reg[23][9] } " -si_connections "SI_2 " -so_connections "SO_2 " -chain_count 1 +// sub-command: create_scan_chain_family scanChain_3 -include_elements "{/theRegisters/\registers_reg[24][0] } {/theRegisters/\registers_reg[24][10] } {/theRegisters/\registers_reg[24][11] } {/theRegisters/\registers_reg[24][12] } {/theRegisters/\registers_reg[24][13] } {/theRegisters/\registers_reg[24][14] } {/theRegisters/\registers_reg[24][15] } {/theRegisters/\registers_reg[24][16] } {/theRegisters/\registers_reg[24][17] } {/theRegisters/\registers_reg[24][18] } {/theRegisters/\registers_reg[24][19] } {/theRegisters/\registers_reg[24][1] } {/theRegisters/\registers_reg[24][20] } {/theRegisters/\registers_reg[24][21] } {/theRegisters/\registers_reg[24][22] } {/theRegisters/\registers_reg[24][23] } {/theRegisters/\registers_reg[24][24] } {/theRegisters/\registers_reg[24][25] } {/theRegisters/\registers_reg[24][26] } {/theRegisters/\registers_reg[24][27] } {/theRegisters/\registers_reg[24][28] } {/theRegisters/\registers_reg[24][29] } {/theRegisters/\registers_reg[24][2] } {/theRegisters/\registers_reg[24][30] } {/theRegisters/\registers_reg[24][31] } {/theRegisters/\registers_reg[24][3] } {/theRegisters/\registers_reg[24][4] } {/theRegisters/\registers_reg[24][5] } {/theRegisters/\registers_reg[24][6] } {/theRegisters/\registers_reg[24][7] } {/theRegisters/\registers_reg[24][8] } {/theRegisters/\registers_reg[24][9] } {/theRegisters/\registers_reg[25][0] } {/theRegisters/\registers_reg[25][10] } {/theRegisters/\registers_reg[25][11] } {/theRegisters/\registers_reg[25][12] } {/theRegisters/\registers_reg[25][13] } {/theRegisters/\registers_reg[25][14] } {/theRegisters/\registers_reg[25][15] } {/theRegisters/\registers_reg[25][16] } {/theRegisters/\registers_reg[25][17] } {/theRegisters/\registers_reg[25][18] } {/theRegisters/\registers_reg[25][19] } {/theRegisters/\registers_reg[25][1] } {/theRegisters/\registers_reg[25][20] } {/theRegisters/\registers_reg[25][21] } {/theRegisters/\registers_reg[25][22] } {/theRegisters/\registers_reg[25][23] } {/theRegisters/\registers_reg[25][24] } {/theRegisters/\registers_reg[25][25] } {/theRegisters/\registers_reg[25][26] } {/theRegisters/\registers_reg[25][27] } {/theRegisters/\registers_reg[25][28] } {/theRegisters/\registers_reg[25][29] } {/theRegisters/\registers_reg[25][2] } {/theRegisters/\registers_reg[25][30] } {/theRegisters/\registers_reg[25][31] } {/theRegisters/\registers_reg[25][3] } {/theRegisters/\registers_reg[25][4] } {/theRegisters/\registers_reg[25][5] } {/theRegisters/\registers_reg[25][6] } {/theRegisters/\registers_reg[25][7] } {/theRegisters/\registers_reg[25][8] } {/theRegisters/\registers_reg[25][9] } {/theRegisters/\registers_reg[26][0] } {/theRegisters/\registers_reg[26][10] } {/theRegisters/\registers_reg[26][11] } {/theRegisters/\registers_reg[26][12] } {/theRegisters/\registers_reg[26][13] } {/theRegisters/\registers_reg[26][14] } {/theRegisters/\registers_reg[26][15] } {/theRegisters/\registers_reg[26][16] } {/theRegisters/\registers_reg[26][17] } {/theRegisters/\registers_reg[26][18] } {/theRegisters/\registers_reg[26][19] } {/theRegisters/\registers_reg[26][1] } {/theRegisters/\registers_reg[26][20] } {/theRegisters/\registers_reg[26][21] } {/theRegisters/\registers_reg[26][22] } {/theRegisters/\registers_reg[26][23] } {/theRegisters/\registers_reg[26][24] } {/theRegisters/\registers_reg[26][25] } {/theRegisters/\registers_reg[26][26] } {/theRegisters/\registers_reg[26][27] } {/theRegisters/\registers_reg[26][28] } {/theRegisters/\registers_reg[26][29] } {/theRegisters/\registers_reg[26][2] } {/theRegisters/\registers_reg[26][30] } {/theRegisters/\registers_reg[26][31] } {/theRegisters/\registers_reg[26][3] } {/theRegisters/\registers_reg[26][4] } {/theRegisters/\registers_reg[26][5] } {/theRegisters/\registers_reg[26][6] } {/theRegisters/\registers_reg[26][7] } {/theRegisters/\registers_reg[26][8] } {/theRegisters/\registers_reg[26][9] } {/theRegisters/\registers_reg[27][0] } {/theRegisters/\registers_reg[27][10] } {/theRegisters/\registers_reg[27][11] } {/theRegisters/\registers_reg[27][12] } {/theRegisters/\registers_reg[27][13] } {/theRegisters/\registers_reg[27][14] } {/theRegisters/\registers_reg[27][15] } {/theRegisters/\registers_reg[27][16] } {/theRegisters/\registers_reg[27][17] } {/theRegisters/\registers_reg[27][18] } {/theRegisters/\registers_reg[27][19] } {/theRegisters/\registers_reg[27][1] } {/theRegisters/\registers_reg[27][20] } {/theRegisters/\registers_reg[27][21] } {/theRegisters/\registers_reg[27][22] } {/theRegisters/\registers_reg[27][23] } {/theRegisters/\registers_reg[27][24] } {/theRegisters/\registers_reg[27][25] } {/theRegisters/\registers_reg[27][26] } {/theRegisters/\registers_reg[27][27] } {/theRegisters/\registers_reg[27][28] } {/theRegisters/\registers_reg[27][29] } {/theRegisters/\registers_reg[27][2] } {/theRegisters/\registers_reg[27][30] } {/theRegisters/\registers_reg[27][31] } {/theRegisters/\registers_reg[27][3] } {/theRegisters/\registers_reg[27][4] } {/theRegisters/\registers_reg[27][5] } {/theRegisters/\registers_reg[27][6] } {/theRegisters/\registers_reg[27][7] } {/theRegisters/\registers_reg[27][8] } {/theRegisters/\registers_reg[27][9] } {/theRegisters/\registers_reg[28][0] } {/theRegisters/\registers_reg[28][10] } {/theRegisters/\registers_reg[28][11] } {/theRegisters/\registers_reg[28][12] } {/theRegisters/\registers_reg[28][13] } {/theRegisters/\registers_reg[28][14] } {/theRegisters/\registers_reg[28][15] } {/theRegisters/\registers_reg[28][16] } {/theRegisters/\registers_reg[28][17] } {/theRegisters/\registers_reg[28][18] } {/theRegisters/\registers_reg[28][19] } {/theRegisters/\registers_reg[28][1] } {/theRegisters/\registers_reg[28][20] } {/theRegisters/\registers_reg[28][21] } {/theRegisters/\registers_reg[28][22] } {/theRegisters/\registers_reg[28][23] } {/theRegisters/\registers_reg[28][24] } {/theRegisters/\registers_reg[28][25] } {/theRegisters/\registers_reg[28][26] } {/theRegisters/\registers_reg[28][27] } {/theRegisters/\registers_reg[28][28] } {/theRegisters/\registers_reg[28][29] } {/theRegisters/\registers_reg[28][2] } {/theRegisters/\registers_reg[28][30] } {/theRegisters/\registers_reg[28][31] } {/theRegisters/\registers_reg[28][3] } {/theRegisters/\registers_reg[28][4] } {/theRegisters/\registers_reg[28][5] } {/theRegisters/\registers_reg[28][6] } {/theRegisters/\registers_reg[28][7] } {/theRegisters/\registers_reg[28][8] } {/theRegisters/\registers_reg[28][9] } {/theRegisters/\registers_reg[29][0] } {/theRegisters/\registers_reg[29][10] } {/theRegisters/\registers_reg[29][11] } {/theRegisters/\registers_reg[29][12] } {/theRegisters/\registers_reg[29][13] } {/theRegisters/\registers_reg[29][14] } {/theRegisters/\registers_reg[29][15] } {/theRegisters/\registers_reg[29][16] } {/theRegisters/\registers_reg[29][17] } {/theRegisters/\registers_reg[29][18] } {/theRegisters/\registers_reg[29][19] } {/theRegisters/\registers_reg[29][1] } {/theRegisters/\registers_reg[29][20] } {/theRegisters/\registers_reg[29][21] } {/theRegisters/\registers_reg[29][22] } {/theRegisters/\registers_reg[29][23] } {/theRegisters/\registers_reg[29][24] } {/theRegisters/\registers_reg[29][25] } {/theRegisters/\registers_reg[29][26] } {/theRegisters/\registers_reg[29][27] } {/theRegisters/\registers_reg[29][28] } {/theRegisters/\registers_reg[29][29] } {/theRegisters/\registers_reg[29][2] } {/theRegisters/\registers_reg[29][30] } {/theRegisters/\registers_reg[29][31] } {/theRegisters/\registers_reg[29][3] } {/theRegisters/\registers_reg[29][4] } {/theRegisters/\registers_reg[29][5] } {/theRegisters/\registers_reg[29][6] } {/theRegisters/\registers_reg[29][7] } {/theRegisters/\registers_reg[29][8] } {/theRegisters/\registers_reg[29][9] } {/theRegisters/\registers_reg[2][0] } {/theRegisters/\registers_reg[2][10] } {/theRegisters/\registers_reg[2][11] } {/theRegisters/\registers_reg[2][12] } {/theRegisters/\registers_reg[2][13] } {/theRegisters/\registers_reg[2][14] } {/theRegisters/\registers_reg[2][15] } {/theRegisters/\registers_reg[2][16] } {/theRegisters/\registers_reg[2][17] } {/theRegisters/\registers_reg[2][18] } {/theRegisters/\registers_reg[2][19] } {/theRegisters/\registers_reg[2][1] } {/theRegisters/\registers_reg[2][20] } {/theRegisters/\registers_reg[2][21] } {/theRegisters/\registers_reg[2][22] } {/theRegisters/\registers_reg[2][23] } {/theRegisters/\registers_reg[2][24] } {/theRegisters/\registers_reg[2][25] } {/theRegisters/\registers_reg[2][26] } {/theRegisters/\registers_reg[2][27] } {/theRegisters/\registers_reg[2][28] } {/theRegisters/\registers_reg[2][29] } {/theRegisters/\registers_reg[2][2] } {/theRegisters/\registers_reg[2][30] } {/theRegisters/\registers_reg[2][31] } {/theRegisters/\registers_reg[2][3] } {/theRegisters/\registers_reg[2][4] } {/theRegisters/\registers_reg[2][5] } {/theRegisters/\registers_reg[2][6] } {/theRegisters/\registers_reg[2][7] } {/theRegisters/\registers_reg[2][8] } {/theRegisters/\registers_reg[2][9] } {/theRegisters/\registers_reg[30][0] } {/theRegisters/\registers_reg[30][10] } {/theRegisters/\registers_reg[30][11] } {/theRegisters/\registers_reg[30][12] } {/theRegisters/\registers_reg[30][13] } {/theRegisters/\registers_reg[30][14] } {/theRegisters/\registers_reg[30][15] } {/theRegisters/\registers_reg[30][16] } {/theRegisters/\registers_reg[30][17] } {/theRegisters/\registers_reg[30][18] } {/theRegisters/\registers_reg[30][19] } {/theRegisters/\registers_reg[30][1] } {/theRegisters/\registers_reg[30][20] } {/theRegisters/\registers_reg[30][21] } {/theRegisters/\registers_reg[30][22] } {/theRegisters/\registers_reg[30][23] } {/theRegisters/\registers_reg[30][24] } {/theRegisters/\registers_reg[30][25] } {/theRegisters/\registers_reg[30][26] } {/theRegisters/\registers_reg[30][27] } {/theRegisters/\registers_reg[30][28] } {/theRegisters/\registers_reg[30][29] } {/theRegisters/\registers_reg[30][2] } {/theRegisters/\registers_reg[30][30] } {/theRegisters/\registers_reg[30][31] } {/theRegisters/\registers_reg[30][3] } {/theRegisters/\registers_reg[30][4] } {/theRegisters/\registers_reg[30][5] } {/theRegisters/\registers_reg[30][6] } {/theRegisters/\registers_reg[30][7] } {/theRegisters/\registers_reg[30][8] } {/theRegisters/\registers_reg[30][9] } " -si_connections "SI_3 " -so_connections "SO_3 " -chain_count 1 +// sub-command: create_scan_chain_family scanChain_4 -include_elements "{/theRegisters/\registers_reg[31][0] } {/theRegisters/\registers_reg[31][10] } {/theRegisters/\registers_reg[31][11] } {/theRegisters/\registers_reg[31][12] } {/theRegisters/\registers_reg[31][13] } {/theRegisters/\registers_reg[31][14] } {/theRegisters/\registers_reg[31][15] } {/theRegisters/\registers_reg[31][16] } {/theRegisters/\registers_reg[31][17] } {/theRegisters/\registers_reg[31][18] } {/theRegisters/\registers_reg[31][19] } {/theRegisters/\registers_reg[31][1] } {/theRegisters/\registers_reg[31][20] } {/theRegisters/\registers_reg[31][21] } {/theRegisters/\registers_reg[31][22] } {/theRegisters/\registers_reg[31][23] } {/theRegisters/\registers_reg[31][24] } {/theRegisters/\registers_reg[31][25] } {/theRegisters/\registers_reg[31][26] } {/theRegisters/\registers_reg[31][27] } {/theRegisters/\registers_reg[31][28] } {/theRegisters/\registers_reg[31][29] } {/theRegisters/\registers_reg[31][2] } {/theRegisters/\registers_reg[31][30] } {/theRegisters/\registers_reg[31][31] } {/theRegisters/\registers_reg[31][3] } {/theRegisters/\registers_reg[31][4] } {/theRegisters/\registers_reg[31][5] } {/theRegisters/\registers_reg[31][6] } {/theRegisters/\registers_reg[31][7] } {/theRegisters/\registers_reg[31][8] } {/theRegisters/\registers_reg[31][9] } {/theRegisters/\registers_reg[3][0] } {/theRegisters/\registers_reg[3][10] } {/theRegisters/\registers_reg[3][11] } {/theRegisters/\registers_reg[3][12] } {/theRegisters/\registers_reg[3][13] } {/theRegisters/\registers_reg[3][14] } {/theRegisters/\registers_reg[3][15] } {/theRegisters/\registers_reg[3][16] } {/theRegisters/\registers_reg[3][17] } {/theRegisters/\registers_reg[3][18] } {/theRegisters/\registers_reg[3][19] } {/theRegisters/\registers_reg[3][1] } {/theRegisters/\registers_reg[3][20] } {/theRegisters/\registers_reg[3][21] } {/theRegisters/\registers_reg[3][22] } {/theRegisters/\registers_reg[3][23] } {/theRegisters/\registers_reg[3][24] } {/theRegisters/\registers_reg[3][25] } {/theRegisters/\registers_reg[3][26] } {/theRegisters/\registers_reg[3][27] } {/theRegisters/\registers_reg[3][28] } {/theRegisters/\registers_reg[3][29] } {/theRegisters/\registers_reg[3][2] } {/theRegisters/\registers_reg[3][30] } {/theRegisters/\registers_reg[3][31] } {/theRegisters/\registers_reg[3][3] } {/theRegisters/\registers_reg[3][4] } {/theRegisters/\registers_reg[3][5] } {/theRegisters/\registers_reg[3][6] } {/theRegisters/\registers_reg[3][7] } {/theRegisters/\registers_reg[3][8] } {/theRegisters/\registers_reg[3][9] } {/theRegisters/\registers_reg[4][0] } {/theRegisters/\registers_reg[4][10] } {/theRegisters/\registers_reg[4][11] } {/theRegisters/\registers_reg[4][12] } {/theRegisters/\registers_reg[4][13] } {/theRegisters/\registers_reg[4][14] } {/theRegisters/\registers_reg[4][15] } {/theRegisters/\registers_reg[4][16] } {/theRegisters/\registers_reg[4][17] } {/theRegisters/\registers_reg[4][18] } {/theRegisters/\registers_reg[4][19] } {/theRegisters/\registers_reg[4][1] } {/theRegisters/\registers_reg[4][20] } {/theRegisters/\registers_reg[4][21] } {/theRegisters/\registers_reg[4][22] } {/theRegisters/\registers_reg[4][23] } {/theRegisters/\registers_reg[4][24] } {/theRegisters/\registers_reg[4][25] } {/theRegisters/\registers_reg[4][26] } {/theRegisters/\registers_reg[4][27] } {/theRegisters/\registers_reg[4][28] } {/theRegisters/\registers_reg[4][29] } {/theRegisters/\registers_reg[4][2] } {/theRegisters/\registers_reg[4][30] } {/theRegisters/\registers_reg[4][31] } {/theRegisters/\registers_reg[4][3] } {/theRegisters/\registers_reg[4][4] } {/theRegisters/\registers_reg[4][5] } {/theRegisters/\registers_reg[4][6] } {/theRegisters/\registers_reg[4][7] } {/theRegisters/\registers_reg[4][8] } {/theRegisters/\registers_reg[4][9] } {/theRegisters/\registers_reg[5][0] } {/theRegisters/\registers_reg[5][10] } {/theRegisters/\registers_reg[5][11] } {/theRegisters/\registers_reg[5][12] } {/theRegisters/\registers_reg[5][13] } {/theRegisters/\registers_reg[5][14] } {/theRegisters/\registers_reg[5][15] } {/theRegisters/\registers_reg[5][16] } {/theRegisters/\registers_reg[5][17] } {/theRegisters/\registers_reg[5][18] } {/theRegisters/\registers_reg[5][19] } {/theRegisters/\registers_reg[5][1] } {/theRegisters/\registers_reg[5][20] } {/theRegisters/\registers_reg[5][21] } {/theRegisters/\registers_reg[5][22] } {/theRegisters/\registers_reg[5][23] } {/theRegisters/\registers_reg[5][24] } {/theRegisters/\registers_reg[5][25] } {/theRegisters/\registers_reg[5][26] } {/theRegisters/\registers_reg[5][27] } {/theRegisters/\registers_reg[5][28] } {/theRegisters/\registers_reg[5][29] } {/theRegisters/\registers_reg[5][2] } {/theRegisters/\registers_reg[5][30] } {/theRegisters/\registers_reg[5][31] } {/theRegisters/\registers_reg[5][3] } {/theRegisters/\registers_reg[5][4] } {/theRegisters/\registers_reg[5][5] } {/theRegisters/\registers_reg[5][6] } {/theRegisters/\registers_reg[5][7] } {/theRegisters/\registers_reg[5][8] } {/theRegisters/\registers_reg[5][9] } {/theRegisters/\registers_reg[6][0] } {/theRegisters/\registers_reg[6][10] } {/theRegisters/\registers_reg[6][11] } {/theRegisters/\registers_reg[6][12] } {/theRegisters/\registers_reg[6][13] } {/theRegisters/\registers_reg[6][14] } {/theRegisters/\registers_reg[6][15] } {/theRegisters/\registers_reg[6][16] } {/theRegisters/\registers_reg[6][17] } {/theRegisters/\registers_reg[6][18] } {/theRegisters/\registers_reg[6][19] } {/theRegisters/\registers_reg[6][1] } {/theRegisters/\registers_reg[6][20] } {/theRegisters/\registers_reg[6][21] } {/theRegisters/\registers_reg[6][22] } {/theRegisters/\registers_reg[6][23] } {/theRegisters/\registers_reg[6][24] } {/theRegisters/\registers_reg[6][25] } {/theRegisters/\registers_reg[6][26] } {/theRegisters/\registers_reg[6][27] } {/theRegisters/\registers_reg[6][28] } {/theRegisters/\registers_reg[6][29] } {/theRegisters/\registers_reg[6][2] } {/theRegisters/\registers_reg[6][30] } {/theRegisters/\registers_reg[6][31] } {/theRegisters/\registers_reg[6][3] } {/theRegisters/\registers_reg[6][4] } {/theRegisters/\registers_reg[6][5] } {/theRegisters/\registers_reg[6][6] } {/theRegisters/\registers_reg[6][7] } {/theRegisters/\registers_reg[6][8] } {/theRegisters/\registers_reg[6][9] } {/theRegisters/\registers_reg[7][0] } {/theRegisters/\registers_reg[7][10] } {/theRegisters/\registers_reg[7][11] } {/theRegisters/\registers_reg[7][12] } {/theRegisters/\registers_reg[7][13] } {/theRegisters/\registers_reg[7][14] } {/theRegisters/\registers_reg[7][15] } {/theRegisters/\registers_reg[7][16] } {/theRegisters/\registers_reg[7][17] } {/theRegisters/\registers_reg[7][18] } {/theRegisters/\registers_reg[7][19] } {/theRegisters/\registers_reg[7][1] } {/theRegisters/\registers_reg[7][20] } {/theRegisters/\registers_reg[7][21] } {/theRegisters/\registers_reg[7][22] } {/theRegisters/\registers_reg[7][23] } {/theRegisters/\registers_reg[7][24] } {/theRegisters/\registers_reg[7][25] } {/theRegisters/\registers_reg[7][26] } {/theRegisters/\registers_reg[7][27] } {/theRegisters/\registers_reg[7][28] } {/theRegisters/\registers_reg[7][29] } {/theRegisters/\registers_reg[7][2] } {/theRegisters/\registers_reg[7][30] } {/theRegisters/\registers_reg[7][31] } {/theRegisters/\registers_reg[7][3] } {/theRegisters/\registers_reg[7][4] } {/theRegisters/\registers_reg[7][5] } {/theRegisters/\registers_reg[7][6] } {/theRegisters/\registers_reg[7][7] } {/theRegisters/\registers_reg[7][8] } {/theRegisters/\registers_reg[7][9] } {/theRegisters/\registers_reg[8][0] } {/theRegisters/\registers_reg[8][10] } {/theRegisters/\registers_reg[8][11] } {/theRegisters/\registers_reg[8][12] } {/theRegisters/\registers_reg[8][13] } {/theRegisters/\registers_reg[8][14] } {/theRegisters/\registers_reg[8][15] } {/theRegisters/\registers_reg[8][16] } {/theRegisters/\registers_reg[8][17] } {/theRegisters/\registers_reg[8][18] } {/theRegisters/\registers_reg[8][19] } {/theRegisters/\registers_reg[8][1] } {/theRegisters/\registers_reg[8][20] } {/theRegisters/\registers_reg[8][21] } {/theRegisters/\registers_reg[8][22] } {/theRegisters/\registers_reg[8][23] } {/theRegisters/\registers_reg[8][24] } {/theRegisters/\registers_reg[8][25] } {/theRegisters/\registers_reg[8][26] } {/theRegisters/\registers_reg[8][27] } {/theRegisters/\registers_reg[8][28] } {/theRegisters/\registers_reg[8][29] } {/theRegisters/\registers_reg[8][2] } {/theRegisters/\registers_reg[8][30] } {/theRegisters/\registers_reg[8][31] } {/theRegisters/\registers_reg[8][3] } {/theRegisters/\registers_reg[8][4] } {/theRegisters/\registers_reg[8][5] } {/theRegisters/\registers_reg[8][6] } {/theRegisters/\registers_reg[8][7] } {/theRegisters/\registers_reg[8][8] } {/theRegisters/\registers_reg[8][9] } {/theRegisters/\registers_reg[9][0] } {/theRegisters/\registers_reg[9][10] } {/theRegisters/\registers_reg[9][11] } {/theRegisters/\registers_reg[9][12] } {/theRegisters/\registers_reg[9][13] } {/theRegisters/\registers_reg[9][14] } {/theRegisters/\registers_reg[9][15] } {/theRegisters/\registers_reg[9][16] } {/theRegisters/\registers_reg[9][17] } {/theRegisters/\registers_reg[9][18] } {/theRegisters/\registers_reg[9][19] } {/theRegisters/\registers_reg[9][1] } {/theRegisters/\registers_reg[9][20] } {/theRegisters/\registers_reg[9][21] } {/theRegisters/\registers_reg[9][22] } {/theRegisters/\registers_reg[9][23] } {/theRegisters/\registers_reg[9][24] } {/theRegisters/\registers_reg[9][25] } {/theRegisters/\registers_reg[9][26] } {/theRegisters/\registers_reg[9][27] } {/theRegisters/\registers_reg[9][28] } {/theRegisters/\registers_reg[9][29] } {/theRegisters/\registers_reg[9][2] } {/theRegisters/\registers_reg[9][30] } {/theRegisters/\registers_reg[9][31] } {/theRegisters/\registers_reg[9][3] } {/theRegisters/\registers_reg[9][4] } {/theRegisters/\registers_reg[9][5] } {/theRegisters/\registers_reg[9][6] } {/theRegisters/\registers_reg[9][7] } {/theRegisters/\registers_reg[9][8] } {/theRegisters/\registers_reg[9][9] } " -si_connections "SI_4 " -so_connections "SO_4 " -chain_count 1 +// sub-command: analyze_scan_chains +// Chain allocation of 'unwrapped' mode completed: +// 4 distributed chains of size 256 +// sub-command: insert_test_logic -write_in_tsdb on +============================= +Test Logic Insertion Summary: +============================= + + Structural Data: + ---------------- + Added top-level port count: 0 + Added instance count: 8 + + Logical Data: + ------------- + Added retiming logic count: 4 + Added scan chain count (unwrapped): 4 + +// Warning: Flattened model deleted. +// +// Writing out netlist and related files in /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.03/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design +// sub-command: report_scan_chains + +=============================== +Scan Chains Created by the Tool +=============================== + + Scan mode 'unwrapped' scan chains: + ---------------------------------- + + Cluster 'scanChain_1' chains: + ----------------------------- + chain = scanChain_1 group = dummy input = /SI_1 output = /SO_1 length = 256 + + Cluster 'scanChain_2' chains: + ----------------------------- + chain = scanChain_2 group = dummy input = /SI_2 output = /SO_2 length = 256 + + Cluster 'scanChain_3' chains: + ----------------------------- + chain = scanChain_3 group = dummy input = /SI_3 output = /SO_3 length = 256 + + Cluster 'scanChain_4' chains: + ----------------------------- + chain = scanChain_4 group = dummy input = /SI_4 output = /SO_4 length = 256 + + +// sub-command: write_scan_order /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.03/Scan_0/cpu.scandef -use_escaping_rule Lefdef -replace +// sub-command: write_design -output_file /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.03/Scan_0/post_scan.v -replace +// command: exit diff --git a/oasys.tessent.03/Scan_0/scan_enable_cluster.cfg b/oasys.tessent.03/Scan_0/scan_enable_cluster.cfg new file mode 100644 index 0000000..838af56 --- /dev/null +++ b/oasys.tessent.03/Scan_0/scan_enable_cluster.cfg @@ -0,0 +1,8 @@ +set_attribute_value [get_scan_elements -of_chain_families scanChain_1 ] -name cluster_name -value scanChain_1 + +set_attribute_value [get_scan_elements -of_chain_families scanChain_2 ] -name cluster_name -value scanChain_2 + +set_attribute_value [get_scan_elements -of_chain_families scanChain_3 ] -name cluster_name -value scanChain_3 + +set_attribute_value [get_scan_elements -of_chain_families scanChain_4 ] -name cluster_name -value scanChain_4 + diff --git a/oasys.tessent.03/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.scandef b/oasys.tessent.03/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.scandef new file mode 100644 index 0000000..9d78e79 --- /dev/null +++ b/oasys.tessent.03/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.scandef @@ -0,0 +1,1071 @@ +# +# DESC: ScanDEF written by Tessent Shell on Fri May 29 09:14:23 CEST 2026 +# + +VERSION 5.7 ; +DIVIDERCHAR "/" ; +BUSBITCHARS "[]" ; +DESIGN cpu ; +UNITS DISTANCE MICRONS 1000 ; + +SCANCHAINS 4 ; + +- scan_segment_0 + + START tessent_persistent_cell_buf_extsi1225_i Z + + FLOATING + \thePC_CurrentPC_reg[30] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[29] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[28] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[27] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[26] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[25] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[24] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[23] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[22] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[21] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[20] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[19] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[18] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[17] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[16] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[15] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[14] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[13] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[12] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[11] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[10] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[9] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[8] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[7] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[6] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[5] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[4] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[3] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[2] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[31] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[1] ( IN SI ) ( OUT Q ) + \thePC_CurrentPC_reg[0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[13][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[10][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[12][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[15][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[16][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[14][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[11][0] ( IN SI ) ( OUT Q ) + + STOP theRegisters/ts_lockup_latchn_clkc1_intno1054_i D + # Partition constraints - clock domain: clk_25mhz(+); cluster: scanChain_1; chain type: core; scan mode(s): unwrapped + + PARTITION partition_1 MAXBITS 256 ; + + +- scan_segment_1 + + START theRegisters/tessent_persistent_cell_buf_extsi1226_i Z + + FLOATING + theRegisters/\registers_reg[1][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[21][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[20][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[17][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[23][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[18][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[22][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[19][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[1][0] ( IN SI ) ( OUT Q ) + + STOP theRegisters/ts_lockup_latchn_clkc2_intno1050_i D + # Partition constraints - clock domain: clk_25mhz(+); cluster: scanChain_2; chain type: core; scan mode(s): unwrapped + + PARTITION partition_2 MAXBITS 256 ; + + +- scan_segment_2 + + START theRegisters/tessent_persistent_cell_buf_extsi1227_i Z + + FLOATING + theRegisters/\registers_reg[28][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[26][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[25][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[28][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[24][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[29][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[30][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[2][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[27][0] ( IN SI ) ( OUT Q ) + + STOP theRegisters/ts_lockup_latchn_clkc3_intno1053_i D + # Partition constraints - clock domain: clk_25mhz(+); cluster: scanChain_3; chain type: core; scan mode(s): unwrapped + + PARTITION partition_3 MAXBITS 256 ; + + +- scan_segment_3 + + START theRegisters/tessent_persistent_cell_buf_extsi1228_i Z + + FLOATING + theRegisters/\registers_reg[4][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][31] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][30] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][29] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][28] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][27] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][26] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][25] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][24] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][23] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][22] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][21] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][20] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][19] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][18] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][17] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][16] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][15] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][14] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][13] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][12] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][11] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][10] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][9] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][8] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][7] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][6] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][5] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][4] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][3] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][2] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][1] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[8][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[7][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[3][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[31][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[4][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[5][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[9][0] ( IN SI ) ( OUT Q ) + theRegisters/\registers_reg[6][0] ( IN SI ) ( OUT Q ) + + STOP theRegisters/ts_lockup_latchn_clkc4_intno1051_i D + # Partition constraints - clock domain: clk_25mhz(+); cluster: scanChain_4; chain type: core; scan mode(s): unwrapped + + PARTITION partition_4 MAXBITS 256 ; + + +END SCANCHAINS + +END DESIGN diff --git a/oasys.tessent.03/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.tcd b/oasys.tessent.03/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.tcd new file mode 100644 index 0000000..c1d0b02 --- /dev/null +++ b/oasys.tessent.03/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.tcd @@ -0,0 +1,61 @@ +//-------------------------------------------------- +// File created by: Tessent Shell +// Version: 2023.4-p1 +// Created on: Fri May 29 09:14:23 CEST 2026 +//-------------------------------------------------- + + +Core(cpu) { + Scan { + allow_internal_pins : 1; + is_hard_module : 1; + exclude_from_concatenated_netlist : 1; + internal_scan_only : 1; + Mode(unwrapped) { + type : unwrapped; + traceable : 1; + make_active_automatically : 1; + ScanChain { + length : 256; + scan_in_clock : clk_25mhz; + scan_out_clock : ~clk_25mhz; + scan_in_port : SI_1; + scan_out_port : SO_1; + } + ScanChain { + length : 256; + scan_in_clock : clk_25mhz; + scan_out_clock : ~clk_25mhz; + scan_in_port : SI_2; + scan_out_port : SO_2; + } + ScanChain { + length : 256; + scan_in_clock : clk_25mhz; + scan_out_clock : ~clk_25mhz; + scan_in_port : SI_3; + scan_out_port : SO_3; + } + ScanChain { + length : 256; + scan_in_clock : clk_25mhz; + scan_out_clock : ~clk_25mhz; + scan_in_port : SI_4; + scan_out_port : SO_4; + } + ScanEn(scan_en) { + pipeline_count : 0; + active_polarity : all_ones; + } + Clock(clk_25mhz) { + off_state : 1'b0; + } + } + } + DesignInfo { + design_id : Scan_0; + design_level : physical_block; + ChildBlockModules { + } + } +} diff --git a/oasys.tessent.03/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.tsdb_info b/oasys.tessent.03/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.tsdb_info new file mode 100644 index 0000000..bc6de5d --- /dev/null +++ b/oasys.tessent.03/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.tsdb_info @@ -0,0 +1,23 @@ +//-------------------------------------------------- +// File created by: Tessent Shell +// Version: 2023.4-p1 +// Created on: Fri May 29 09:14:23 CEST 2026 +//-------------------------------------------------- + + +TsdbInfo(cpu,Scan_0) { + tessent_tool_version : 2023.4-p1; + tessent_meta_version : 10; + version : 3; + creation_date : Fri May 29 07:14:23 GMT 2026; + creation_user : charapallivenkatsaja; + creation_step : insert_test_logic; + level : physical_block; + icl_extraction_needed : Off; + library_name : work; + gate_extension : vg; + interface_has_external_dependencies : 0; + OpenedTsdbDirectories { + /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.03/tsdb_outdir; + } +} diff --git a/oasys.tessent.03/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.v_interface b/oasys.tessent.03/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.v_interface new file mode 100644 index 0000000..8bd833a --- /dev/null +++ b/oasys.tessent.03/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.v_interface @@ -0,0 +1,9 @@ +/* Generated by Tessent Shell 2023.4-p1 at Fri May 29 09:14:23 CEST 2026 */ +module cpu(led, btn, clk_25mhz, scan_en, SI_1, SO_1, SI_2, SO_2, SI_3, SO_3, SI_4, + SO_4); + input clk_25mhz, scan_en, SI_1, SI_2, SI_3, SI_4; + output SO_1, SO_2, SO_3, SO_4; + output [7:0] led; + input [6:0] btn; +endmodule + diff --git a/oasys.tessent.03/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.vg b/oasys.tessent.03/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.vg new file mode 100644 index 0000000..1f7fa5c --- /dev/null +++ b/oasys.tessent.03/tsdb_outdir/dft_inserted_designs/cpu_Scan_0.dft_inserted_design/cpu.vg @@ -0,0 +1,15792 @@ +/* Generated by Tessent Shell 2023.4-p1 at Fri May 29 09:14:23 CEST 2026 */ +module alu(aluOp, aluNegAr, aluBypass, op1, op2, result, eqFlag); + input [31:0] op1, op2; + input [2:0] aluOp; + input aluNegAr, aluBypass; + output [31:0] result; + output eqFlag; + + wire n_9_0, n_9_1, n_9_2, n_9_3, n_9_4, n_9_5, n_9_6, n_9_7, n_9_8, n_9_9, + n_9_10, n_9_11, n_9_12, n_9_13, n_9_14, n_9_15, n_9_16, n_9_17, n_9_18, + n_9_19, n_9_20, n_9_21, n_9_22, n_9_23, n_9_24, n_9_25, n_9_26, n_9_27, + n_9_28, n_9_29, n_9_30, n_9_31, n_10_0, n_10_1, n_10_2, n_10_3, n_10_4, + n_10_5, n_10_6, n_10_7, n_10_8, n_10_9, n_10_10, n_10_11, n_10_12, + n_10_13, n_10_14, n_10_15, n_10_16, n_10_17, n_10_18, n_10_19, n_10_20, + n_10_21, n_10_22, n_10_23, n_10_24, n_10_25, n_10_26, n_10_27, n_10_28, + n_10_29, n_10_30, n_10_31, n_10_32, n_10_33, n_10_34, n_10_35, n_10_36, + n_10_37, n_10_38, n_10_39, n_10_40, n_10_41, n_10_42, n_10_43, n_10_44, + n_10_45, n_10_46, n_10_47, n_10_48, n_10_49, n_10_50, n_10_51, n_10_52, + n_10_53, n_10_54, n_10_55, n_10_56, n_10_57, n_10_58, n_10_59, n_10_60, + n_10_61, n_10_62, n_10_63, n_10_64, n_10_65, n_10_66, n_10_67, n_10_68, + n_10_69, n_10_70, n_10_71, n_10_72, n_10_73, n_10_74, n_10_75, n_10_76, + n_10_77, n_10_78, n_10_79, n_10_80, n_10_81, n_10_82, n_10_83, n_10_84, + n_10_85, n_10_86, n_10_87, n_10_88, n_10_89, n_10_90, n_10_91, n_10_92, + n_10_93, n_10_94, n_10_95, n_10_96, n_10_97, n_10_98, n_10_99, n_10_100, + n_10_101, n_10_102, n_10_103, n_10_104, n_10_105, n_10_106, n_10_107, + n_10_108, n_10_109, n_10_110, n_10_111, n_10_112, n_10_113, n_10_114, + n_10_115, n_10_116, n_10_117, n_10_118, n_10_119, n_10_120, n_10_121, + n_10_122, n_10_123, n_0_0, n_0_1, n_0_2, n_0_3, n_0_4, n_0_5, n_0_6, + n_0_7, n_0_8, n_0_9, n_0_10, n_0_11, n_0_12, n_0_13, n_0_14, n_0_15, + n_0_16, n_0_17, n_0_18, n_0_19, n_0_20, n_0_21, n_0_22, n_0_23, n_0_24, + n_0_25, n_0_26, n_0_27, n_0_28, n_0_29, n_0_30, n_0_31, n_0_32, n_0_33, + n_0_34, n_0_35, n_0_36, n_0_37, n_0_38, n_0_39, n_0_40, n_0_41, n_0_42, + n_0_43, n_0_44, n_0_45, n_0_46, n_0_47, n_0_48, n_0_49, n_0_50, n_0_51, + n_0_52, n_0_53, n_0_54, n_0_55, n_0_56, n_0_57, n_0_58, n_0_59, n_0_60, + n_0_61, n_0_62, n_0_63, n_0_64, n_0_65, n_0_66, n_0_67, n_0_68, n_0_69, + n_0_70, n_0_71, n_0_72, n_0_73, n_0_74, n_0_75, n_0_76, n_0_77, n_0_78, + n_0_79, n_0_80, n_0_81, n_0_82, n_0_83, n_0_84, n_0_85, n_0_86, n_0_87, + n_0_88, n_0_89, n_0_90, n_0_91, n_0_92, n_0_93, n_0_94, n_0_95, n_0_96, + n_0_97, n_0_98, n_0_99, n_0_100, n_0_101, n_0_102, n_0_103, n_0_104, + n_0_105, n_0_106, n_0_107, n_0_108, n_0_109, n_0_110, n_0_111, n_0_112, + n_0_113, n_0_114, n_0_115, n_0_116, n_0_117, n_0_118, n_0_119, n_0_120, + n_0_121, n_0_122, n_0_123, n_0_124, n_0_125, n_0_126, n_0_127, n_0_128, + n_0_129, n_0_130, n_0_131, n_0_132, n_0_133, n_0_134, n_0_135, n_0_136, + n_0_137, n_0_138, n_0_139, n_0_140, n_0_141, n_0_142, n_0_143, n_0_144, + n_0_145, n_0_146, n_0_147, n_0_148, n_0_149, n_0_150, n_0_151, n_0_152, + n_0_153, n_0_154, n_0_155, n_0_156, n_0_157, n_0_158, n_0_159, n_0_160, + n_0_161, n_0_162, n_0_163, n_0_164, n_0_165, n_0_166, n_0_167, n_0_168, + n_0_169, n_0_170, n_0_171, n_0_172, n_0_173, n_0_174, n_0_175, n_0_176, + n_0_177, n_0_178, n_0_179, n_0_180, n_0_181, n_0_182, n_0_183, n_0_184, + n_0_185, n_0_186, n_0_187, n_0_188, n_0_189, n_0_190, n_0_191, n_0_192, + n_0_193, n_0_194, n_0_195, n_0_196, n_0_197, n_0_198, n_0_199, n_0_200, + n_0_201, n_0_202, n_0_203, n_0_204, n_0_205, n_0_206, n_0_207, n_0_208, + n_0_209, n_0_210, n_0_211, n_0_212, n_0_213, n_0_214, n_0_215, n_0_216, + n_0_217, n_0_218, n_0_219, n_0_220, n_0_221, n_0_222, n_0_223, n_0_224, + n_0_225, n_0_226, n_0_227, n_0_228, n_0_229, n_0_230, n_0_231, n_0_232, + n_0_233, n_0_234, n_0_235, n_0_236, n_0_237, n_0_238, n_0_239, n_0_240, + n_0_241, n_0_242, n_0_243, n_0_244, n_0_245, n_0_246, n_0_247, n_0_248, + n_0_249, n_0_250, n_0_251, n_0_252, n_0_253, n_0_254, n_0_255, n_0_256, + n_0_257, n_0_258, n_0_259, n_0_260, n_0_261, n_0_262, n_0_263, n_0_264, + n_0_265, n_0_266, n_0_267, n_0_268, n_0_269, n_0_270, n_0_271, n_0_272, + n_0_273, n_0_274, n_0_275, n_0_276, n_0_277, n_0_278, n_0_279, n_0_280, + n_0_281, n_0_282, n_0_283, n_0_284, n_0_285, n_0_286, n_0_287, n_0_288, + n_0_289, n_0_290, n_0_291, n_0_292, n_0_293, n_0_294, n_0_295, n_0_296, + n_0_297, n_0_298, n_0_299, n_0_300, n_0_301, n_0_302, n_0_303, n_0_304, + n_0_305, n_0_306, n_0_307, n_0_308, n_0_309, n_0_310, n_0_311, n_0_312, + n_0_313, n_0_314, n_0_315, n_0_316, n_0_317, n_0_318, n_0_319, n_0_320, + n_0_321, n_0_322, n_0_323, n_0_324, n_0_325, n_0_326, n_0_327, n_0_328, + n_0_329, n_0_330, n_0_331, n_0_332, n_0_333, n_0_334, n_0_335, n_0_336, + n_0_337, n_0_338, n_0_339, n_0_340, n_0_341, n_0_342, n_0_343, n_0_344, + n_0_345, n_0_346, n_0_347, n_0_348, n_0_349, n_0_350, n_0_351, n_0_352, + n_0_353, n_0_354, n_0_355, n_0_356, n_0_357, n_0_358, n_0_359, n_0_360, + n_0_361, n_0_362, n_0_363, n_0_364, n_0_365, n_0_366, n_0_367, n_0_368, + n_0_369, n_0_370, n_0_371, n_0_372, n_0_373, n_0_374, n_0_375, n_0_376, + n_0_377, n_0_378, n_0_379, n_0_380, n_0_381, n_0_382, n_0_383, n_0_384, + n_0_385, n_0_386, n_0_387, n_0_388, n_0_389, n_0_390, n_0_391, n_0_392, + n_0_393, n_0_394, n_0_395, n_0_396, n_0_397, n_0_398, n_0_399, n_0_400, + n_0_401, n_0_402, n_0_403, n_0_404, n_0_405, n_0_406, n_0_407, n_0_408, + n_0_409, n_0_410, n_0_411, n_0_412, n_0_413, n_0_414, n_0_415, n_0_416, + n_0_417, n_0_418, n_0_419, n_0_420, n_0_421, n_0_422, n_0_423, n_0_424, + n_0_425, n_0_426, n_0_427, n_0_428, n_0_429, n_0_430, n_0_431, n_0_432, + n_0_433, n_0_434, n_0_435, n_0_436, n_0_437, n_0_438, n_0_439, n_0_440, + n_0_441, n_0_442, n_0_443, n_0_444, n_0_445, n_0_446, n_0_447, n_0_448, + n_0_449, n_0_450, n_0_451, n_0_452, n_0_453, n_0_454, n_0_455, n_0_456, + n_0_457, n_0_458, n_0_459, n_0_460, n_0_461, n_0_462, n_0_463, n_0_464, + n_0_465, n_0_466, n_0_467, n_0_468, n_0_469, n_0_470, n_0_471, n_0_472, + n_0_473, n_0_474, n_0_475, n_0_476, n_0_477, n_0_478, n_0_479, n_0_480, + n_0_481, n_0_482, n_0_483, n_0_484, n_0_485, n_0_486, n_0_487, n_0_488, + n_0_489, n_0_490, n_0_491, n_0_492, n_0_493, n_0_494, n_0_495, n_0_496, + n_0_497, n_0_498, n_0_499, n_0_500, n_0_501, n_0_502, n_0_503, n_0_504, + n_0_505, n_0_506, n_0_507, n_0_508, n_0_509, n_0_510, n_0_511, n_0_512, + n_0_513, n_0_514, n_0_515, n_0_516, n_0_517, n_0_518, n_0_519, n_0_520, + n_0_521, n_0_522, n_0_523, n_0_524, n_0_525, n_0_526, n_0_527, n_0_528, + n_0_529, n_0_530, n_0_531, n_0_532, n_0_533, n_0_534, n_0_535, n_0_536, + n_0_537, n_0_538, n_0_539, n_0_540, n_0_541, n_0_542, n_0_543, n_0_544, + n_0_545, n_0_546, n_0_547, n_0_548, n_0_549, n_0_550, n_0_551, n_0_552, + n_0_553, n_0_554, n_0_555, n_0_556, n_0_557, n_0_558, n_0_559, n_0_560, + n_0_561, n_0_562, n_0_563, n_0_564, n_0_565, n_0_566, n_0_567, n_0_568, + n_0_569, n_0_570, n_0_571, n_0_572, n_0_573, n_0_574, n_0_575, n_0_576, + n_0_577, n_0_578, n_0_579, n_0_580, n_0_581, n_0_582, n_0_583, n_0_584, + n_0_585, n_0_586, n_0_587, n_0_588, n_0_589, n_0_590, n_0_591, n_0_592, + n_0_593, n_0_594, n_0_595, n_0_596, n_0_597, n_0_598, n_0_599, n_0_600, + n_0_601, n_0_602, n_0_603, n_0_604, n_0_605, n_0_606, n_0_607, n_0_608, + n_0_609, n_0_610, n_0_611, n_0_612, n_0_613, n_0_614, n_0_615, n_0_616, + n_0_617, n_0_618, n_0_619, n_0_620, n_0_621, n_0_622, n_0_623, n_0_624, + n_0_625, n_0_626, n_0_627, n_0_628, n_0_629, n_0_630, n_0_631, n_0_632, + n_0_633, n_0_634, n_0_635, n_0_636, n_0_637, n_0_638, n_0_639, n_0_640, + n_0_641, n_0_642, n_0_643, n_0_644, n_0_645, n_0_646, n_0_647, n_0_648, + n_0_649, n_0_650, n_0_651, n_0_652, n_0_653, n_0_654, n_0_655, n_0_656, + n_0_657, n_0_658, n_0_659, n_0_660, n_0_661, n_0_662, n_0_663, n_0_664, + n_0_665, n_0_666, n_0_667, n_0_668, n_0_669, n_0_670, n_0_671, n_0_672, + n_0_673, n_0_674, n_0_675, n_0_676, n_0_677, n_0_678, n_0_679, n_0_680, + n_0_681, n_0_682, n_0_683, n_0_684, n_0_685, n_0_686, n_0_687, n_0_688, + n_0_689, n_0_690, n_0_691, n_0_692, n_0_693, n_0_694, n_0_695, n_0_696, + n_0_697, n_0_698, n_0_699, n_0_700, n_0_701, n_0_702, n_0_703, n_0_704, + n_0_705, n_0_706, n_0_707, n_0_708, n_0_709, n_0_710, n_0_711, n_0_712, + n_0_713, n_0_714, n_0_715, n_0_716, n_0_717, n_0_718, n_0_719, n_0_720, + n_0_721, n_0_722, n_0_723, n_0_724, n_0_725, n_0_726, n_0_727, n_0_728, + n_0_729, n_0_730, n_0_731, n_0_732, n_0_733, n_0_734, n_0_735, n_0_736, + n_0_737, n_0_738, n_0_739, n_0_740, n_0, n_1, n_2, n_3, n_4, n_5, n_6, + n_7, n_8, n_9, n_10, n_11, n_12, n_13, n_14, n_15, n_16, n_17, n_18, + n_19, n_20, n_21, n_22, n_23, n_24, n_25, n_26, n_27, n_28, n_29, n_30, + n_31, n_63, n_62, n_61, n_60, n_59, n_58, n_57, n_56, n_55, n_54, n_53, + n_52, n_51, n_50, n_49, n_48, n_47, n_46, n_45, n_44, n_43, n_42, n_41, + n_40, n_39, n_38, n_37, n_36, n_35, n_34, n_33, n_32; + + INV_X1_LVT i_0_725( + .A(op2[31]), .ZN(n_0_692) + ); + INV_X1_LVT i_0_724( + .A(op1[31]), .ZN(n_0_691) + ); + INV_X1_LVT i_0_718( + .A(aluOp[1]), .ZN(n_0_685) + ); + INV_X1_LVT i_0_717( + .A(aluOp[2]), .ZN(n_0_684) + ); + NOR2_X1_LVT i_0_599( + .A1(n_0_685), .A2(n_0_684), .ZN(n_0_567) + ); + INV_X1_LVT i_0_598( + .A(n_0_567), .ZN(n_0_566) + ); + INV_X1_LVT i_0_716( + .A(aluOp[0]), .ZN(n_0_683) + ); + NAND2_X1_LVT i_0_602( + .A1(aluOp[2]), .A2(aluNegAr), .ZN(n_0_570) + ); + OAI21_X1_LVT i_0_590( + .A(n_0_566), .B1(n_0_683), .B2(n_0_570), .ZN(n_0_558) + ); + INV_X1_LVT i_0_714( + .A(aluBypass), .ZN(n_0_681) + ); + NOR2_X1_LVT i_0_601( + .A1(n_0_684), .A2(aluOp[0]), .ZN(n_0_569) + ); + NAND2_X1_LVT i_0_597( + .A1(n_0_681), .A2(n_0_569), .ZN(n_0_565) + ); + INV_X1_LVT i_0_596( + .A(n_0_565), .ZN(n_0_564) + ); + OAI22_X1_LVT i_0_589( + .A1(n_0_691), .A2(n_0_558), .B1(op1[31]), .B2(n_0_564), .ZN(n_0_557) + ); + NOR2_X1_LVT i_0_588( + .A1(n_0_692), .A2(n_0_557), .ZN(n_0_556) + ); + XNOR2_X1_LVT i_9_31( + .A(op2[31]), .B(op1[31]), .ZN(n_9_31) + ); + HA_X1_LVT i_9_0( + .A(op2[0]), .B(op1[0]), .CO(n_9_0), .S(n_0) + ); + FA_X1_LVT i_9_1( + .A(op2[1]), .B(op1[1]), .CI(n_9_0), .CO(n_9_1), .S(n_1) + ); + FA_X1_LVT i_9_2( + .A(op2[2]), .B(op1[2]), .CI(n_9_1), .CO(n_9_2), .S(n_2) + ); + FA_X1_LVT i_9_3( + .A(op2[3]), .B(op1[3]), .CI(n_9_2), .CO(n_9_3), .S(n_3) + ); + FA_X1_LVT i_9_4( + .A(op2[4]), .B(op1[4]), .CI(n_9_3), .CO(n_9_4), .S(n_4) + ); + FA_X1_LVT i_9_5( + .A(op2[5]), .B(op1[5]), .CI(n_9_4), .CO(n_9_5), .S(n_5) + ); + FA_X1_LVT i_9_6( + .A(op2[6]), .B(op1[6]), .CI(n_9_5), .CO(n_9_6), .S(n_6) + ); + FA_X1_LVT i_9_7( + .A(op2[7]), .B(op1[7]), .CI(n_9_6), .CO(n_9_7), .S(n_7) + ); + FA_X1_LVT i_9_8( + .A(op2[8]), .B(op1[8]), .CI(n_9_7), .CO(n_9_8), .S(n_8) + ); + FA_X1_LVT i_9_9( + .A(op2[9]), .B(op1[9]), .CI(n_9_8), .CO(n_9_9), .S(n_9) + ); + FA_X1_LVT i_9_10( + .A(op2[10]), .B(op1[10]), .CI(n_9_9), .CO(n_9_10), .S(n_10) + ); + FA_X1_LVT i_9_11( + .A(op2[11]), .B(op1[11]), .CI(n_9_10), .CO(n_9_11), .S(n_11) + ); + FA_X1_LVT i_9_12( + .A(op2[12]), .B(op1[12]), .CI(n_9_11), .CO(n_9_12), .S(n_12) + ); + FA_X1_LVT i_9_13( + .A(op2[13]), .B(op1[13]), .CI(n_9_12), .CO(n_9_13), .S(n_13) + ); + FA_X1_LVT i_9_14( + .A(op2[14]), .B(op1[14]), .CI(n_9_13), .CO(n_9_14), .S(n_14) + ); + FA_X1_LVT i_9_15( + .A(op2[15]), .B(op1[15]), .CI(n_9_14), .CO(n_9_15), .S(n_15) + ); + FA_X1_LVT i_9_16( + .A(op2[16]), .B(op1[16]), .CI(n_9_15), .CO(n_9_16), .S(n_16) + ); + FA_X1_LVT i_9_17( + .A(op2[17]), .B(op1[17]), .CI(n_9_16), .CO(n_9_17), .S(n_17) + ); + FA_X1_LVT i_9_18( + .A(op2[18]), .B(op1[18]), .CI(n_9_17), .CO(n_9_18), .S(n_18) + ); + FA_X1_LVT i_9_19( + .A(op2[19]), .B(op1[19]), .CI(n_9_18), .CO(n_9_19), .S(n_19) + ); + FA_X1_LVT i_9_20( + .A(op2[20]), .B(op1[20]), .CI(n_9_19), .CO(n_9_20), .S(n_20) + ); + FA_X1_LVT i_9_21( + .A(op2[21]), .B(op1[21]), .CI(n_9_20), .CO(n_9_21), .S(n_21) + ); + FA_X1_LVT i_9_22( + .A(op2[22]), .B(op1[22]), .CI(n_9_21), .CO(n_9_22), .S(n_22) + ); + FA_X1_LVT i_9_23( + .A(op2[23]), .B(op1[23]), .CI(n_9_22), .CO(n_9_23), .S(n_23) + ); + FA_X1_LVT i_9_24( + .A(op2[24]), .B(op1[24]), .CI(n_9_23), .CO(n_9_24), .S(n_24) + ); + FA_X1_LVT i_9_25( + .A(op2[25]), .B(op1[25]), .CI(n_9_24), .CO(n_9_25), .S(n_25) + ); + FA_X1_LVT i_9_26( + .A(op2[26]), .B(op1[26]), .CI(n_9_25), .CO(n_9_26), .S(n_26) + ); + FA_X1_LVT i_9_27( + .A(op2[27]), .B(op1[27]), .CI(n_9_26), .CO(n_9_27), .S(n_27) + ); + FA_X1_LVT i_9_28( + .A(op2[28]), .B(op1[28]), .CI(n_9_27), .CO(n_9_28), .S(n_28) + ); + FA_X1_LVT i_9_29( + .A(op2[29]), .B(op1[29]), .CI(n_9_28), .CO(n_9_29), .S(n_29) + ); + FA_X1_LVT i_9_30( + .A(op2[30]), .B(op1[30]), .CI(n_9_29), .CO(n_9_30), .S(n_30) + ); + XNOR2_X1_LVT i_9_32( + .A(n_9_31), .B(n_9_30), .ZN(n_31) + ); + NAND4_X1_LVT i_0_614( + .A1(n_0_685), .A2(n_0_681), .A3(n_0_684), .A4(n_0_683), .ZN(n_0_582) + ); + NOR2_X1_LVT i_0_613( + .A1(aluNegAr), .A2(n_0_582), .ZN(n_0_581) + ); + INV_X1_LVT i_10_147( + .A(op2[30]), .ZN(n_10_117) + ); + NAND2_X1_LVT i_10_149( + .A1(n_10_117), .A2(op1[30]), .ZN(n_10_119) + ); + INV_X1_LVT i_10_152( + .A(n_10_119), .ZN(n_10_121) + ); + INV_X1_LVT i_10_130( + .A(op1[26]), .ZN(n_10_104) + ); + NAND2_X1_LVT i_10_131( + .A1(n_10_104), .A2(op2[26]), .ZN(n_10_105) + ); + INV_X1_LVT i_10_123( + .A(op2[25]), .ZN(n_10_98) + ); + NAND2_X1_LVT i_10_125( + .A1(n_10_98), .A2(op1[25]), .ZN(n_10_100) + ); + INV_X1_LVT i_10_112( + .A(op2[23]), .ZN(n_10_89) + ); + NAND2_X1_LVT i_10_114( + .A1(n_10_89), .A2(op1[23]), .ZN(n_10_91) + ); + INV_X1_LVT i_10_101( + .A(op2[21]), .ZN(n_10_80) + ); + NAND2_X1_LVT i_10_103( + .A1(n_10_80), .A2(op1[21]), .ZN(n_10_82) + ); + INV_X1_LVT i_10_48( + .A(op1[8]), .ZN(n_10_40) + ); + NAND2_X1_LVT i_10_49( + .A1(n_10_40), .A2(op2[8]), .ZN(n_10_41) + ); + INV_X1_LVT i_10_41( + .A(op2[7]), .ZN(n_10_34) + ); + NAND2_X1_LVT i_10_43( + .A1(n_10_34), .A2(op1[7]), .ZN(n_10_36) + ); + INV_X1_LVT i_10_32( + .A(op2[5]), .ZN(n_10_27) + ); + NOR2_X1_LVT i_10_33( + .A1(n_10_27), .A2(op1[5]), .ZN(n_10_28) + ); + INV_X1_LVT i_10_24( + .A(op1[4]), .ZN(n_10_20) + ); + NOR2_X1_LVT i_10_27( + .A1(n_10_20), .A2(op2[4]), .ZN(n_10_23) + ); + INV_X1_LVT i_10_17( + .A(op2[3]), .ZN(n_10_14) + ); + NAND2_X1_LVT i_10_19( + .A1(n_10_14), .A2(op1[3]), .ZN(n_10_16) + ); + INV_X1_LVT i_10_22( + .A(n_10_16), .ZN(n_10_18) + ); + INV_X1_LVT i_10_10( + .A(op2[2]), .ZN(n_10_8) + ); + NAND2_X1_LVT i_10_12( + .A1(n_10_8), .A2(op1[2]), .ZN(n_10_10) + ); + INV_X1_LVT i_10_3( + .A(op1[1]), .ZN(n_10_2) + ); + NAND2_X1_LVT i_10_5( + .A1(n_10_2), .A2(op2[1]), .ZN(n_10_4) + ); + INV_X1_LVT i_10_0( + .A(op1[0]), .ZN(n_10_0) + ); + NAND2_X1_LVT i_10_1( + .A1(n_10_0), .A2(op2[0]), .ZN(n_10_1) + ); + OR2_X1_LVT i_10_4( + .A1(n_10_2), .A2(op2[1]), .ZN(n_10_3) + ); + INV_X1_LVT i_10_8( + .A(n_10_3), .ZN(n_10_6) + ); + OAI21_X1_LVT i_10_9( + .A(n_10_4), .B1(n_10_1), .B2(n_10_6), .ZN(n_10_7) + ); + NOR2_X1_LVT i_10_11( + .A1(n_10_8), .A2(op1[2]), .ZN(n_10_9) + ); + OAI21_X1_LVT i_10_16( + .A(n_10_10), .B1(n_10_7), .B2(n_10_9), .ZN(n_10_13) + ); + OR2_X1_LVT i_10_18( + .A1(n_10_14), .A2(op1[3]), .ZN(n_10_15) + ); + AOI21_X1_LVT i_10_23( + .A(n_10_18), .B1(n_10_13), .B2(n_10_15), .ZN(n_10_19) + ); + INV_X1_LVT i_10_30( + .A(n_10_19), .ZN(n_10_25) + ); + NAND2_X1_LVT i_10_25( + .A1(n_10_20), .A2(op2[4]), .ZN(n_10_21) + ); + AOI21_X1_LVT i_10_31( + .A(n_10_23), .B1(n_10_25), .B2(n_10_21), .ZN(n_10_26) + ); + AOI21_X1_LVT i_10_34( + .A(n_10_28), .B1(n_10_27), .B2(op1[5]), .ZN(n_10_29) + ); + AOI21_X1_LVT i_10_36( + .A(n_10_28), .B1(n_10_26), .B2(n_10_29), .ZN(n_10_30) + ); + XOR2_X1_LVT i_10_37( + .A(op2[6]), .B(op1[6]), .Z(n_10_31) + ); + INV_X1_LVT i_10_39( + .A(op2[6]), .ZN(n_10_32) + ); + OAI22_X1_LVT i_10_40( + .A1(n_10_30), .A2(n_10_31), .B1(n_10_32), .B2(op1[6]), .ZN(n_10_33) + ); + NOR2_X1_LVT i_10_42( + .A1(n_10_34), .A2(op1[7]), .ZN(n_10_35) + ); + OAI21_X1_LVT i_10_47( + .A(n_10_36), .B1(n_10_33), .B2(n_10_35), .ZN(n_10_39) + ); + OAI21_X1_LVT i_10_50( + .A(n_10_41), .B1(n_10_40), .B2(op2[8]), .ZN(n_10_42) + ); + OAI21_X1_LVT i_10_52( + .A(n_10_41), .B1(n_10_39), .B2(n_10_42), .ZN(n_10_43) + ); + XNOR2_X1_LVT i_10_53( + .A(op2[9]), .B(op1[9]), .ZN(n_10_44) + ); + INV_X1_LVT i_10_55( + .A(op1[9]), .ZN(n_10_45) + ); + AOI22_X1_LVT i_10_56( + .A1(n_10_43), .A2(n_10_44), .B1(n_10_45), .B2(op2[9]), .ZN(n_10_46) + ); + XOR2_X1_LVT i_10_57( + .A(op2[10]), .B(op1[10]), .Z(n_10_47) + ); + INV_X1_LVT i_10_59( + .A(op2[10]), .ZN(n_10_48) + ); + OAI22_X1_LVT i_10_60( + .A1(n_10_46), .A2(n_10_47), .B1(n_10_48), .B2(op1[10]), .ZN(n_10_49) + ); + XNOR2_X1_LVT i_10_61( + .A(op2[11]), .B(op1[11]), .ZN(n_10_50) + ); + INV_X1_LVT i_10_63( + .A(op1[11]), .ZN(n_10_51) + ); + AOI22_X1_LVT i_10_64( + .A1(n_10_49), .A2(n_10_50), .B1(n_10_51), .B2(op2[11]), .ZN(n_10_52) + ); + XOR2_X1_LVT i_10_65( + .A(op2[12]), .B(op1[12]), .Z(n_10_53) + ); + INV_X1_LVT i_10_67( + .A(op2[12]), .ZN(n_10_54) + ); + OAI22_X1_LVT i_10_68( + .A1(n_10_52), .A2(n_10_53), .B1(n_10_54), .B2(op1[12]), .ZN(n_10_55) + ); + XNOR2_X1_LVT i_10_69( + .A(op2[13]), .B(op1[13]), .ZN(n_10_56) + ); + INV_X1_LVT i_10_71( + .A(op1[13]), .ZN(n_10_57) + ); + AOI22_X1_LVT i_10_72( + .A1(n_10_55), .A2(n_10_56), .B1(n_10_57), .B2(op2[13]), .ZN(n_10_58) + ); + XOR2_X1_LVT i_10_73( + .A(op2[14]), .B(op1[14]), .Z(n_10_59) + ); + INV_X1_LVT i_10_75( + .A(op2[14]), .ZN(n_10_60) + ); + OAI22_X1_LVT i_10_76( + .A1(n_10_58), .A2(n_10_59), .B1(n_10_60), .B2(op1[14]), .ZN(n_10_61) + ); + XNOR2_X1_LVT i_10_77( + .A(op2[15]), .B(op1[15]), .ZN(n_10_62) + ); + INV_X1_LVT i_10_79( + .A(op1[15]), .ZN(n_10_63) + ); + AOI22_X1_LVT i_10_80( + .A1(n_10_61), .A2(n_10_62), .B1(n_10_63), .B2(op2[15]), .ZN(n_10_64) + ); + XOR2_X1_LVT i_10_81( + .A(op2[16]), .B(op1[16]), .Z(n_10_65) + ); + INV_X1_LVT i_10_83( + .A(op2[16]), .ZN(n_10_66) + ); + OAI22_X1_LVT i_10_84( + .A1(n_10_64), .A2(n_10_65), .B1(n_10_66), .B2(op1[16]), .ZN(n_10_67) + ); + XNOR2_X1_LVT i_10_85( + .A(op2[17]), .B(op1[17]), .ZN(n_10_68) + ); + INV_X1_LVT i_10_87( + .A(op1[17]), .ZN(n_10_69) + ); + AOI22_X1_LVT i_10_88( + .A1(n_10_67), .A2(n_10_68), .B1(n_10_69), .B2(op2[17]), .ZN(n_10_70) + ); + XOR2_X1_LVT i_10_89( + .A(op2[18]), .B(op1[18]), .Z(n_10_71) + ); + INV_X1_LVT i_10_91( + .A(op2[18]), .ZN(n_10_72) + ); + OAI22_X1_LVT i_10_92( + .A1(n_10_70), .A2(n_10_71), .B1(n_10_72), .B2(op1[18]), .ZN(n_10_73) + ); + XNOR2_X1_LVT i_10_93( + .A(op2[19]), .B(op1[19]), .ZN(n_10_74) + ); + INV_X1_LVT i_10_95( + .A(op1[19]), .ZN(n_10_75) + ); + AOI22_X1_LVT i_10_96( + .A1(n_10_73), .A2(n_10_74), .B1(n_10_75), .B2(op2[19]), .ZN(n_10_76) + ); + XOR2_X1_LVT i_10_97( + .A(op2[20]), .B(op1[20]), .Z(n_10_77) + ); + INV_X1_LVT i_10_99( + .A(op2[20]), .ZN(n_10_78) + ); + OAI22_X1_LVT i_10_100( + .A1(n_10_76), .A2(n_10_77), .B1(n_10_78), .B2(op1[20]), .ZN(n_10_79) + ); + NOR2_X1_LVT i_10_102( + .A1(n_10_80), .A2(op1[21]), .ZN(n_10_81) + ); + OAI21_X1_LVT i_10_107( + .A(n_10_82), .B1(n_10_79), .B2(n_10_81), .ZN(n_10_85) + ); + XOR2_X1_LVT i_10_108( + .A(op2[22]), .B(op1[22]), .Z(n_10_86) + ); + INV_X1_LVT i_10_110( + .A(op2[22]), .ZN(n_10_87) + ); + OAI22_X1_LVT i_10_111( + .A1(n_10_85), .A2(n_10_86), .B1(n_10_87), .B2(op1[22]), .ZN(n_10_88) + ); + NOR2_X1_LVT i_10_113( + .A1(n_10_89), .A2(op1[23]), .ZN(n_10_90) + ); + OAI21_X1_LVT i_10_118( + .A(n_10_91), .B1(n_10_88), .B2(n_10_90), .ZN(n_10_94) + ); + XOR2_X1_LVT i_10_119( + .A(op2[24]), .B(op1[24]), .Z(n_10_95) + ); + INV_X1_LVT i_10_121( + .A(op2[24]), .ZN(n_10_96) + ); + OAI22_X1_LVT i_10_122( + .A1(n_10_94), .A2(n_10_95), .B1(n_10_96), .B2(op1[24]), .ZN(n_10_97) + ); + NOR2_X1_LVT i_10_124( + .A1(n_10_98), .A2(op1[25]), .ZN(n_10_99) + ); + OAI21_X1_LVT i_10_129( + .A(n_10_100), .B1(n_10_97), .B2(n_10_99), .ZN(n_10_103) + ); + OAI21_X1_LVT i_10_132( + .A(n_10_105), .B1(n_10_104), .B2(op2[26]), .ZN(n_10_106) + ); + OAI21_X1_LVT i_10_134( + .A(n_10_105), .B1(n_10_103), .B2(n_10_106), .ZN(n_10_107) + ); + XNOR2_X1_LVT i_10_135( + .A(op2[27]), .B(op1[27]), .ZN(n_10_108) + ); + INV_X1_LVT i_10_137( + .A(op1[27]), .ZN(n_10_109) + ); + AOI22_X1_LVT i_10_138( + .A1(n_10_107), .A2(n_10_108), .B1(n_10_109), .B2(op2[27]), .ZN(n_10_110) + ); + XOR2_X1_LVT i_10_139( + .A(op2[28]), .B(op1[28]), .Z(n_10_111) + ); + INV_X1_LVT i_10_141( + .A(op2[28]), .ZN(n_10_112) + ); + OAI22_X1_LVT i_10_142( + .A1(n_10_110), .A2(n_10_111), .B1(n_10_112), .B2(op1[28]), .ZN(n_10_113) + ); + XNOR2_X1_LVT i_10_143( + .A(op2[29]), .B(op1[29]), .ZN(n_10_114) + ); + INV_X1_LVT i_10_145( + .A(op1[29]), .ZN(n_10_115) + ); + AOI22_X1_LVT i_10_146( + .A1(n_10_113), .A2(n_10_114), .B1(n_10_115), .B2(op2[29]), .ZN(n_10_116) + ); + OR2_X1_LVT i_10_148( + .A1(n_10_117), .A2(op1[30]), .ZN(n_10_118) + ); + AOI21_X1_LVT i_10_153( + .A(n_10_121), .B1(n_10_116), .B2(n_10_118), .ZN(n_10_122) + ); + XNOR2_X1_LVT i_10_154( + .A(op1[31]), .B(op2[31]), .ZN(n_10_123) + ); + XNOR2_X1_LVT i_10_155( + .A(n_10_122), .B(n_10_123), .ZN(n_63) + ); + INV_X1_LVT i_0_715( + .A(aluNegAr), .ZN(n_0_682) + ); + NOR2_X1_LVT i_0_612( + .A1(n_0_682), .A2(n_0_582), .ZN(n_0_580) + ); + AOI221_X1_LVT i_0_587( + .A(n_0_556), .B1(n_31), .B2(n_0_581), .C1(n_63), .C2(n_0_580), .ZN(n_0_555) + ); + NOR3_X1_LVT i_0_654( + .A1(aluOp[1]), .A2(aluBypass), .A3(n_0_683), .ZN(n_0_622) + ); + NAND2_X1_LVT i_0_653( + .A1(n_0_684), .A2(n_0_622), .ZN(n_0_621) + ); + INV_X1_LVT i_0_734( + .A(op2[0]), .ZN(n_0_701) + ); + INV_X1_LVT i_0_756( + .A(op2[3]), .ZN(n_0_723) + ); + NOR2_X1_LVT i_0_650( + .A1(op2[4]), .A2(n_0_723), .ZN(n_0_618) + ); + INV_X1_LVT i_0_649( + .A(n_0_618), .ZN(n_0_617) + ); + NOR2_X1_LVT i_0_648( + .A1(op2[4]), .A2(op2[3]), .ZN(n_0_616) + ); + INV_X1_LVT i_0_647( + .A(n_0_616), .ZN(n_0_615) + ); + INV_X1_LVT i_0_771( + .A(op2[4]), .ZN(n_0_738) + ); + INV_X1_LVT i_0_767( + .A(op1[15]), .ZN(n_0_734) + ); + INV_X1_LVT i_0_746( + .A(op1[7]), .ZN(n_0_713) + ); + AOI22_X1_LVT i_0_651( + .A1(n_0_734), .A2(n_0_723), .B1(op2[3]), .B2(n_0_713), .ZN(n_0_619) + ); + OAI222_X1_LVT i_0_646( + .A1(op1[23]), .A2(n_0_617), .B1(op1[31]), .B2(n_0_615), .C1(n_0_738), .C2(n_0_619), + .ZN(n_0_614) + ); + NOR2_X1_LVT i_0_645( + .A1(op2[2]), .A2(n_0_614), .ZN(n_0_613) + ); + NOR2_X1_LVT i_0_696( + .A1(op1[3]), .A2(n_0_723), .ZN(n_0_663) + ); + INV_X1_LVT i_0_739( + .A(op1[11]), .ZN(n_0_706) + ); + AOI21_X1_LVT i_0_644( + .A(n_0_663), .B1(n_0_723), .B2(n_0_706), .ZN(n_0_612) + ); + AOI22_X1_LVT i_0_643( + .A1(op2[4]), .A2(n_0_612), .B1(op1[27]), .B2(n_0_616), .ZN(n_0_611) + ); + INV_X1_LVT i_0_722( + .A(op1[19]), .ZN(n_0_689) + ); + OAI21_X1_LVT i_0_642( + .A(n_0_611), .B1(n_0_689), .B2(n_0_617), .ZN(n_0_610) + ); + AOI21_X1_LVT i_0_641( + .A(n_0_613), .B1(op2[2]), .B2(n_0_610), .ZN(n_0_609) + ); + INV_X1_LVT i_0_761( + .A(op2[1]), .ZN(n_0_728) + ); + OAI22_X1_LVT i_0_640( + .A1(op2[4]), .A2(op1[21]), .B1(n_0_738), .B2(op1[5]), .ZN(n_0_608) + ); + NAND2_X1_LVT i_0_639( + .A1(op2[3]), .A2(n_0_608), .ZN(n_0_607) + ); + INV_X1_LVT i_0_747( + .A(op1[13]), .ZN(n_0_714) + ); + NOR2_X1_LVT i_0_638( + .A1(n_0_738), .A2(op2[3]), .ZN(n_0_606) + ); + INV_X1_LVT i_0_743( + .A(op1[29]), .ZN(n_0_710) + ); + AOI221_X1_LVT i_0_636( + .A(op2[2]), .B1(n_0_714), .B2(n_0_606), .C1(n_0_710), .C2(n_0_616), .ZN(n_0_604) + ); + OAI22_X1_LVT i_0_635( + .A1(op2[4]), .A2(op1[17]), .B1(n_0_738), .B2(op1[1]), .ZN(n_0_603) + ); + INV_X1_LVT i_0_755( + .A(op1[9]), .ZN(n_0_722) + ); + INV_X1_LVT i_0_637( + .A(n_0_606), .ZN(n_0_605) + ); + INV_X1_LVT i_0_732( + .A(op1[25]), .ZN(n_0_699) + ); + OAI222_X1_LVT i_0_634( + .A1(n_0_723), .A2(n_0_603), .B1(n_0_722), .B2(n_0_605), .C1(n_0_699), .C2(n_0_615), + .ZN(n_0_602) + ); + AOI22_X1_LVT i_0_633( + .A1(n_0_607), .A2(n_0_604), .B1(op2[2]), .B2(n_0_602), .ZN(n_0_601) + ); + OAI221_X1_LVT i_0_616( + .A(n_0_701), .B1(op2[1]), .B2(n_0_609), .C1(n_0_728), .C2(n_0_601), .ZN(n_0_584) + ); + INV_X1_LVT i_0_729( + .A(op1[12]), .ZN(n_0_696) + ); + INV_X1_LVT i_0_731( + .A(op1[28]), .ZN(n_0_698) + ); + AOI22_X1_LVT i_0_622( + .A1(n_0_696), .A2(n_0_606), .B1(n_0_698), .B2(n_0_616), .ZN(n_0_590) + ); + INV_X1_LVT i_0_726( + .A(op2[2]), .ZN(n_0_693) + ); + NOR2_X1_LVT i_0_701( + .A1(n_0_738), .A2(op1[4]), .ZN(n_0_668) + ); + INV_X1_LVT i_0_760( + .A(op1[20]), .ZN(n_0_727) + ); + AOI21_X1_LVT i_0_623( + .A(n_0_668), .B1(n_0_738), .B2(n_0_727), .ZN(n_0_591) + ); + OAI211_X1_LVT i_0_621( + .A(n_0_590), .B(n_0_693), .C1(n_0_723), .C2(n_0_591), .ZN(n_0_589) + ); + OAI22_X1_LVT i_0_626( + .A1(op1[16]), .A2(op2[4]), .B1(n_0_738), .B2(op1[0]), .ZN(n_0_594) + ); + INV_X1_LVT i_0_769( + .A(op1[24]), .ZN(n_0_736) + ); + OAI22_X1_LVT i_0_625( + .A1(n_0_723), .A2(n_0_594), .B1(n_0_736), .B2(n_0_615), .ZN(n_0_593) + ); + AOI21_X1_LVT i_0_624( + .A(n_0_593), .B1(op1[8]), .B2(n_0_606), .ZN(n_0_592) + ); + OAI21_X1_LVT i_0_620( + .A(n_0_589), .B1(n_0_693), .B2(n_0_592), .ZN(n_0_588) + ); + INV_X1_LVT i_0_737( + .A(op1[6]), .ZN(n_0_704) + ); + INV_X1_LVT i_0_720( + .A(op1[22]), .ZN(n_0_687) + ); + OAI22_X1_LVT i_0_632( + .A1(n_0_738), .A2(n_0_704), .B1(op2[4]), .B2(n_0_687), .ZN(n_0_600) + ); + OAI221_X1_LVT i_0_631( + .A(n_0_693), .B1(n_0_723), .B2(n_0_600), .C1(op1[14]), .C2(n_0_605), .ZN(n_0_599) + ); + INV_X1_LVT i_0_750( + .A(op1[30]), .ZN(n_0_717) + ); + AOI21_X1_LVT i_0_630( + .A(n_0_599), .B1(n_0_717), .B2(n_0_616), .ZN(n_0_598) + ); + INV_X1_LVT i_0_738( + .A(op1[18]), .ZN(n_0_705) + ); + NOR2_X1_LVT i_0_628( + .A1(n_0_705), .A2(n_0_617), .ZN(n_0_596) + ); + INV_X1_LVT i_0_727( + .A(op1[2]), .ZN(n_0_694) + ); + INV_X1_LVT i_0_766( + .A(op1[10]), .ZN(n_0_733) + ); + OAI22_X1_LVT i_0_629( + .A1(n_0_723), .A2(n_0_694), .B1(n_0_733), .B2(op2[3]), .ZN(n_0_597) + ); + AOI221_X1_LVT i_0_627( + .A(n_0_596), .B1(op1[26]), .B2(n_0_616), .C1(op2[4]), .C2(n_0_597), .ZN(n_0_595) + ); + OAI21_X1_LVT i_0_619( + .A(n_0_728), .B1(n_0_693), .B2(n_0_595), .ZN(n_0_587) + ); + OAI22_X1_LVT i_0_618( + .A1(n_0_728), .A2(n_0_588), .B1(n_0_598), .B2(n_0_587), .ZN(n_0_586) + ); + INV_X1_LVT i_0_617( + .A(n_0_586), .ZN(n_0_585) + ); + OAI21_X1_LVT i_0_615( + .A(n_0_584), .B1(n_0_701), .B2(n_0_585), .ZN(n_0_583) + ); + NOR2_X1_LVT i_0_607( + .A1(op2[4]), .A2(op2[2]), .ZN(n_0_575) + ); + NAND2_X1_LVT i_0_606( + .A1(n_0_723), .A2(n_0_575), .ZN(n_0_574) + ); + INV_X1_LVT i_0_605( + .A(n_0_574), .ZN(n_0_573) + ); + NAND2_X1_LVT i_0_604( + .A1(n_0_728), .A2(n_0_573), .ZN(n_0_572) + ); + NAND2_X1_LVT i_0_611( + .A1(aluOp[2]), .A2(n_0_622), .ZN(n_0_579) + ); + INV_X1_LVT i_0_610( + .A(n_0_579), .ZN(n_0_578) + ); + NAND2_X1_LVT i_0_594( + .A1(n_0_701), .A2(n_0_578), .ZN(n_0_562) + ); + NOR3_X1_LVT i_0_592( + .A1(aluNegAr), .A2(n_0_572), .A3(n_0_562), .ZN(n_0_560) + ); + INV_X1_LVT i_0_600( + .A(n_0_569), .ZN(n_0_568) + ); + OAI21_X1_LVT i_0_595( + .A(n_0_568), .B1(aluOp[1]), .B2(n_0_570), .ZN(n_0_563) + ); + AOI211_X1_LVT i_0_591( + .A(aluBypass), .B(n_0_560), .C1(n_0_692), .C2(n_0_563), .ZN(n_0_559) + ); + OAI221_X1_LVT i_0_586( + .A(n_0_555), .B1(n_0_621), .B2(n_0_583), .C1(n_0_691), .C2(n_0_559), .ZN(result[31]) + ); + NAND2_X1_LVT i_10_150( + .A1(n_10_118), .A2(n_10_119), .ZN(n_10_120) + ); + XNOR2_X1_LVT i_10_151( + .A(n_10_116), .B(n_10_120), .ZN(n_62) + ); + AOI22_X1_LVT i_0_580( + .A1(n_62), .A2(n_0_580), .B1(n_30), .B2(n_0_581), .ZN(n_0_549) + ); + NAND2_X1_LVT i_0_576( + .A1(aluNegAr), .A2(n_0_578), .ZN(n_0_545) + ); + INV_X1_LVT i_0_603( + .A(n_0_572), .ZN(n_0_571) + ); + NOR3_X1_LVT i_0_574( + .A1(n_0_691), .A2(n_0_545), .A3(n_0_571), .ZN(n_0_543) + ); + AOI22_X1_LVT i_0_573( + .A1(n_0_717), .A2(n_0_565), .B1(op1[30]), .B2(n_0_566), .ZN(n_0_542) + ); + AOI21_X1_LVT i_0_572( + .A(n_0_543), .B1(op2[30]), .B2(n_0_542), .ZN(n_0_541) + ); + NAND2_X1_LVT i_0_579( + .A1(op2[0]), .A2(n_0_578), .ZN(n_0_548) + ); + NAND2_X1_LVT i_0_577( + .A1(op1[31]), .A2(n_0_571), .ZN(n_0_546) + ); + OAI211_X1_LVT i_0_571( + .A(n_0_549), .B(n_0_541), .C1(n_0_548), .C2(n_0_546), .ZN(n_0_540) + ); + OAI221_X1_LVT i_0_581( + .A(n_0_681), .B1(op2[30]), .B2(n_0_568), .C1(n_0_572), .C2(n_0_562), .ZN(n_0_550) + ); + AOI21_X1_LVT i_0_570( + .A(n_0_540), .B1(op1[30]), .B2(n_0_550), .ZN(n_0_539) + ); + INV_X1_LVT i_0_752( + .A(op1[23]), .ZN(n_0_719) + ); + OAI222_X1_LVT i_0_585( + .A1(n_0_713), .A2(n_0_605), .B1(n_0_719), .B2(n_0_615), .C1(n_0_734), .C2(n_0_617), + .ZN(n_0_554) + ); + AOI22_X1_LVT i_0_584( + .A1(op2[2]), .A2(n_0_554), .B1(n_0_693), .B2(n_0_610), .ZN(n_0_553) + ); + OAI22_X1_LVT i_0_583( + .A1(n_0_728), .A2(n_0_553), .B1(op2[1]), .B2(n_0_601), .ZN(n_0_552) + ); + AOI22_X1_LVT i_0_582( + .A1(n_0_701), .A2(n_0_585), .B1(op2[0]), .B2(n_0_552), .ZN(n_0_551) + ); + OAI21_X1_LVT i_0_569( + .A(n_0_539), .B1(n_0_621), .B2(n_0_551), .ZN(result[30]) + ); + INV_X1_LVT i_0_578( + .A(n_0_548), .ZN(n_0_547) + ); + NAND3_X1_LVT i_0_562( + .A1(op1[30]), .A2(n_0_571), .A3(n_0_547), .ZN(n_0_532) + ); + XNOR2_X1_LVT i_10_144( + .A(n_10_113), .B(n_10_114), .ZN(n_61) + ); + NAND2_X1_LVT i_0_558( + .A1(n_61), .A2(n_0_580), .ZN(n_0_528) + ); + OAI21_X1_LVT i_0_557( + .A(n_0_681), .B1(op2[29]), .B2(n_0_568), .ZN(n_0_527) + ); + NAND2_X1_LVT i_0_556( + .A1(op1[29]), .A2(n_0_566), .ZN(n_0_526) + ); + AOI22_X1_LVT i_0_555( + .A1(op1[29]), .A2(n_0_527), .B1(op2[29]), .B2(n_0_526), .ZN(n_0_525) + ); + AOI21_X1_LVT i_0_554( + .A(n_0_525), .B1(n_0_710), .B2(n_0_565), .ZN(n_0_524) + ); + AOI211_X1_LVT i_0_553( + .A(n_0_543), .B(n_0_524), .C1(n_29), .C2(n_0_581), .ZN(n_0_523) + ); + AND3_X1_LVT i_0_552( + .A1(n_0_532), .A2(n_0_528), .A3(n_0_523), .ZN(n_0_522) + ); + INV_X1_LVT i_0_652( + .A(n_0_621), .ZN(n_0_620) + ); + NAND2_X1_LVT i_0_565( + .A1(n_0_728), .A2(n_0_588), .ZN(n_0_535) + ); + AOI22_X1_LVT i_0_568( + .A1(n_0_723), .A2(n_0_600), .B1(op1[14]), .B2(n_0_618), .ZN(n_0_538) + ); + AOI22_X1_LVT i_0_567( + .A1(n_0_693), .A2(n_0_595), .B1(op2[2]), .B2(n_0_538), .ZN(n_0_537) + ); + INV_X1_LVT i_0_566( + .A(n_0_537), .ZN(n_0_536) + ); + OAI21_X1_LVT i_0_564( + .A(n_0_535), .B1(n_0_728), .B2(n_0_536), .ZN(n_0_534) + ); + OAI221_X1_LVT i_0_563( + .A(n_0_620), .B1(op2[0]), .B2(n_0_552), .C1(n_0_701), .C2(n_0_534), .ZN(n_0_533) + ); + NAND2_X1_LVT i_0_561( + .A1(op2[1]), .A2(n_0_573), .ZN(n_0_531) + ); + INV_X1_LVT i_0_560( + .A(n_0_531), .ZN(n_0_530) + ); + AOI22_X1_LVT i_0_559( + .A1(op1[31]), .A2(n_0_530), .B1(op1[29]), .B2(n_0_571), .ZN(n_0_529) + ); + OAI211_X1_LVT i_0_551( + .A(n_0_522), .B(n_0_533), .C1(n_0_562), .C2(n_0_529), .ZN(result[29]) + ); + INV_X1_LVT i_0_733( + .A(op2[28]), .ZN(n_0_700) + ); + AOI221_X1_LVT i_0_546( + .A(n_0_700), .B1(op1[28]), .B2(n_0_566), .C1(n_0_698), .C2(n_0_565), .ZN(n_0_517) + ); + OAI21_X1_LVT i_0_543( + .A(n_0_681), .B1(op2[28]), .B2(n_0_568), .ZN(n_0_514) + ); + AOI22_X1_LVT i_0_542( + .A1(n_28), .A2(n_0_581), .B1(op1[28]), .B2(n_0_514), .ZN(n_0_513) + ); + XNOR2_X1_LVT i_10_140( + .A(n_10_110), .B(n_10_111), .ZN(n_60) + ); + NAND2_X1_LVT i_0_544( + .A1(n_60), .A2(n_0_580), .ZN(n_0_515) + ); + NAND2_X1_LVT i_0_545( + .A1(op1[31]), .A2(n_0_574), .ZN(n_0_516) + ); + OAI211_X1_LVT i_0_541( + .A(n_0_513), .B(n_0_515), .C1(n_0_545), .C2(n_0_516), .ZN(n_0_512) + ); + AOI22_X1_LVT i_0_540( + .A1(op1[30]), .A2(n_0_530), .B1(op1[28]), .B2(n_0_571), .ZN(n_0_511) + ); + OAI22_X1_LVT i_0_539( + .A1(n_0_562), .A2(n_0_511), .B1(n_0_548), .B2(n_0_529), .ZN(n_0_510) + ); + NOR3_X1_LVT i_0_538( + .A1(n_0_517), .A2(n_0_512), .A3(n_0_510), .ZN(n_0_509) + ); + OAI22_X1_LVT i_0_550( + .A1(n_0_714), .A2(n_0_617), .B1(op2[3]), .B2(n_0_608), .ZN(n_0_521) + ); + OAI22_X1_LVT i_0_549( + .A1(op2[2]), .A2(n_0_602), .B1(n_0_693), .B2(n_0_521), .ZN(n_0_520) + ); + AOI22_X1_LVT i_0_548( + .A1(op2[1]), .A2(n_0_520), .B1(n_0_728), .B2(n_0_553), .ZN(n_0_519) + ); + OAI22_X1_LVT i_0_547( + .A1(op2[0]), .A2(n_0_534), .B1(n_0_701), .B2(n_0_519), .ZN(n_0_518) + ); + OAI21_X1_LVT i_0_537( + .A(n_0_509), .B1(n_0_621), .B2(n_0_518), .ZN(result[28]) + ); + XNOR2_X1_LVT i_10_136( + .A(n_10_107), .B(n_10_108), .ZN(n_59) + ); + AOI22_X1_LVT i_0_517( + .A1(n_27), .A2(n_0_581), .B1(n_59), .B2(n_0_580), .ZN(n_0_489) + ); + INV_X1_LVT i_0_721( + .A(op1[27]), .ZN(n_0_688) + ); + OAI21_X1_LVT i_0_516( + .A(n_0_681), .B1(op2[27]), .B2(n_0_568), .ZN(n_0_488) + ); + INV_X1_LVT i_0_515( + .A(n_0_488), .ZN(n_0_487) + ); + OAI221_X1_LVT i_0_514( + .A(n_0_489), .B1(n_0_545), .B2(n_0_516), .C1(n_0_688), .C2(n_0_487), .ZN(n_0_486) + ); + OAI21_X1_LVT i_0_530( + .A(op2[1]), .B1(n_0_710), .B2(n_0_574), .ZN(n_0_502) + ); + OAI21_X1_LVT i_0_529( + .A(n_0_728), .B1(n_0_688), .B2(n_0_574), .ZN(n_0_501) + ); + NAND2_X1_LVT i_0_528( + .A1(n_0_502), .A2(n_0_501), .ZN(n_0_500) + ); + AOI21_X1_LVT i_0_527( + .A(n_0_545), .B1(n_0_701), .B2(n_0_500), .ZN(n_0_499) + ); + NAND2_X1_LVT i_0_609( + .A1(n_0_682), .A2(n_0_578), .ZN(n_0_577) + ); + NOR2_X1_LVT i_0_526( + .A1(op2[4]), .A2(n_0_693), .ZN(n_0_498) + ); + NAND2_X1_LVT i_0_525( + .A1(n_0_723), .A2(n_0_498), .ZN(n_0_497) + ); + OAI22_X1_LVT i_0_523( + .A1(n_0_688), .A2(n_0_574), .B1(n_0_691), .B2(n_0_497), .ZN(n_0_495) + ); + OAI21_X1_LVT i_0_522( + .A(n_0_502), .B1(op2[1]), .B2(n_0_495), .ZN(n_0_494) + ); + AOI21_X1_LVT i_0_521( + .A(n_0_577), .B1(n_0_701), .B2(n_0_494), .ZN(n_0_493) + ); + NOR2_X1_LVT i_0_520( + .A1(n_0_499), .A2(n_0_493), .ZN(n_0_492) + ); + AOI21_X1_LVT i_0_519( + .A(n_0_492), .B1(op2[0]), .B2(n_0_511), .ZN(n_0_491) + ); + AOI22_X1_LVT i_0_518( + .A1(n_0_688), .A2(n_0_565), .B1(op1[27]), .B2(n_0_566), .ZN(n_0_490) + ); + AOI211_X1_LVT i_0_513( + .A(n_0_486), .B(n_0_491), .C1(op2[27]), .C2(n_0_490), .ZN(n_0_485) + ); + NOR3_X1_LVT i_0_536( + .A1(op2[4]), .A2(n_0_696), .A3(n_0_723), .ZN(n_0_508) + ); + AOI21_X1_LVT i_0_535( + .A(n_0_508), .B1(n_0_723), .B2(n_0_591), .ZN(n_0_507) + ); + OAI22_X1_LVT i_0_534( + .A1(op2[2]), .A2(n_0_592), .B1(n_0_693), .B2(n_0_507), .ZN(n_0_506) + ); + NOR2_X1_LVT i_0_533( + .A1(n_0_728), .A2(n_0_506), .ZN(n_0_505) + ); + AOI21_X1_LVT i_0_532( + .A(n_0_505), .B1(n_0_728), .B2(n_0_536), .ZN(n_0_504) + ); + OAI22_X1_LVT i_0_531( + .A1(n_0_701), .A2(n_0_504), .B1(op2[0]), .B2(n_0_519), .ZN(n_0_503) + ); + OAI21_X1_LVT i_0_512( + .A(n_0_485), .B1(n_0_621), .B2(n_0_503), .ZN(result[27]) + ); + OAI21_X1_LVT i_0_500( + .A(n_0_681), .B1(op2[26]), .B2(n_0_568), .ZN(n_0_473) + ); + NAND2_X1_LVT i_0_499( + .A1(op1[26]), .A2(n_0_473), .ZN(n_0_472) + ); + XNOR2_X1_LVT i_10_133( + .A(n_10_103), .B(n_10_106), .ZN(n_58) + ); + AOI22_X1_LVT i_0_498( + .A1(n_58), .A2(n_0_580), .B1(n_26), .B2(n_0_581), .ZN(n_0_471) + ); + INV_X1_LVT i_0_744( + .A(op1[26]), .ZN(n_0_711) + ); + OAI221_X1_LVT i_0_501( + .A(op2[26]), .B1(op1[26]), .B2(n_0_564), .C1(n_0_711), .C2(n_0_567), .ZN(n_0_474) + ); + NAND3_X1_LVT i_0_497( + .A1(n_0_472), .A2(n_0_471), .A3(n_0_474), .ZN(n_0_470) + ); + INV_X1_LVT i_0_524( + .A(n_0_497), .ZN(n_0_496) + ); + AOI22_X1_LVT i_0_505( + .A1(op1[30]), .A2(n_0_496), .B1(op1[26]), .B2(n_0_573), .ZN(n_0_478) + ); + NOR2_X1_LVT i_0_504( + .A1(op2[1]), .A2(n_0_478), .ZN(n_0_477) + ); + AOI21_X1_LVT i_0_503( + .A(n_0_477), .B1(op1[28]), .B2(n_0_530), .ZN(n_0_476) + ); + NAND2_X1_LVT i_0_502( + .A1(n_0_701), .A2(n_0_476), .ZN(n_0_475) + ); + AOI21_X1_LVT i_0_489( + .A(n_0_577), .B1(op2[0]), .B2(n_0_494), .ZN(n_0_462) + ); + AOI21_X1_LVT i_0_488( + .A(n_0_470), .B1(n_0_475), .B2(n_0_462), .ZN(n_0_461) + ); + AOI21_X1_LVT i_0_511( + .A(n_0_616), .B1(n_0_738), .B2(n_0_706), .ZN(n_0_484) + ); + AOI21_X1_LVT i_0_510( + .A(n_0_484), .B1(n_0_723), .B2(op1[19]), .ZN(n_0_483) + ); + INV_X1_LVT i_0_757( + .A(op1[3]), .ZN(n_0_724) + ); + NOR2_X1_LVT i_0_687( + .A1(n_0_724), .A2(op2[3]), .ZN(n_0_654) + ); + INV_X1_LVT i_0_686( + .A(n_0_654), .ZN(n_0_653) + ); + AOI21_X1_LVT i_0_509( + .A(n_0_483), .B1(op2[4]), .B2(n_0_653), .ZN(n_0_482) + ); + AOI22_X1_LVT i_0_508( + .A1(n_0_693), .A2(n_0_554), .B1(op2[2]), .B2(n_0_482), .ZN(n_0_481) + ); + OAI22_X1_LVT i_0_507( + .A1(n_0_728), .A2(n_0_481), .B1(op2[1]), .B2(n_0_520), .ZN(n_0_480) + ); + AOI22_X1_LVT i_0_506( + .A1(op2[0]), .A2(n_0_480), .B1(n_0_701), .B2(n_0_504), .ZN(n_0_479) + ); + NAND3_X1_LVT i_0_491( + .A1(op2[0]), .A2(n_0_516), .A3(n_0_500), .ZN(n_0_464) + ); + NAND2_X1_LVT i_0_494( + .A1(op1[31]), .A2(n_0_615), .ZN(n_0_467) + ); + OAI21_X1_LVT i_0_492( + .A(n_0_467), .B1(n_0_728), .B2(n_0_516), .ZN(n_0_465) + ); + OAI21_X1_LVT i_0_490( + .A(n_0_464), .B1(n_0_475), .B2(n_0_465), .ZN(n_0_463) + ); + OAI221_X1_LVT i_0_487( + .A(n_0_461), .B1(n_0_621), .B2(n_0_479), .C1(n_0_545), .C2(n_0_463), .ZN(result[26]) + ); + INV_X1_LVT i_10_126( + .A(n_10_100), .ZN(n_10_101) + ); + NOR2_X1_LVT i_10_127( + .A1(n_10_99), .A2(n_10_101), .ZN(n_10_102) + ); + XNOR2_X1_LVT i_10_128( + .A(n_10_97), .B(n_10_102), .ZN(n_57) + ); + AOI22_X1_LVT i_0_479( + .A1(n_57), .A2(n_0_580), .B1(n_25), .B2(n_0_581), .ZN(n_0_453) + ); + INV_X1_LVT i_0_730( + .A(op2[25]), .ZN(n_0_697) + ); + AOI21_X1_LVT i_0_478( + .A(aluBypass), .B1(n_0_697), .B2(n_0_569), .ZN(n_0_452) + ); + AOI22_X1_LVT i_0_480( + .A1(op1[25]), .A2(n_0_567), .B1(n_0_699), .B2(n_0_564), .ZN(n_0_454) + ); + OAI221_X1_LVT i_0_477( + .A(n_0_453), .B1(n_0_699), .B2(n_0_452), .C1(n_0_697), .C2(n_0_454), .ZN(n_0_451) + ); + INV_X1_LVT i_0_575( + .A(n_0_545), .ZN(n_0_544) + ); + AOI21_X1_LVT i_0_476( + .A(n_0_451), .B1(n_0_544), .B2(n_0_465), .ZN(n_0_450) + ); + AOI22_X1_LVT i_0_475( + .A1(op1[29]), .A2(n_0_496), .B1(op1[25]), .B2(n_0_573), .ZN(n_0_449) + ); + NAND2_X1_LVT i_0_474( + .A1(n_0_728), .A2(n_0_449), .ZN(n_0_448) + ); + OAI21_X1_LVT i_0_473( + .A(n_0_448), .B1(n_0_728), .B2(n_0_495), .ZN(n_0_447) + ); + OAI22_X1_LVT i_0_472( + .A1(n_0_548), .A2(n_0_476), .B1(n_0_562), .B2(n_0_447), .ZN(n_0_446) + ); + INV_X1_LVT i_0_471( + .A(n_0_446), .ZN(n_0_445) + ); + OAI222_X1_LVT i_0_486( + .A1(n_0_733), .A2(n_0_617), .B1(n_0_694), .B2(n_0_605), .C1(n_0_705), .C2(n_0_615), + .ZN(n_0_460) + ); + NOR2_X1_LVT i_0_485( + .A1(n_0_693), .A2(n_0_460), .ZN(n_0_459) + ); + AOI21_X1_LVT i_0_484( + .A(n_0_459), .B1(n_0_693), .B2(n_0_538), .ZN(n_0_458) + ); + OAI22_X1_LVT i_0_483( + .A1(n_0_728), .A2(n_0_458), .B1(op2[1]), .B2(n_0_506), .ZN(n_0_457) + ); + INV_X1_LVT i_0_482( + .A(n_0_457), .ZN(n_0_456) + ); + OAI221_X1_LVT i_0_481( + .A(n_0_620), .B1(n_0_701), .B2(n_0_456), .C1(op2[0]), .C2(n_0_480), .ZN(n_0_455) + ); + NAND3_X1_LVT i_0_470( + .A1(n_0_450), .A2(n_0_445), .A3(n_0_455), .ZN(result[25]) + ); + INV_X1_LVT i_0_493( + .A(n_0_467), .ZN(n_0_466) + ); + OAI211_X1_LVT i_0_455( + .A(n_0_544), .B(n_0_465), .C1(op2[0]), .C2(n_0_466), .ZN(n_0_430) + ); + OAI21_X1_LVT i_0_462( + .A(n_0_681), .B1(op2[24]), .B2(n_0_568), .ZN(n_0_437) + ); + XNOR2_X1_LVT i_10_120( + .A(n_10_94), .B(n_10_95), .ZN(n_56) + ); + AOI222_X1_LVT i_0_461( + .A1(op1[24]), .A2(n_0_437), .B1(n_56), .B2(n_0_580), .C1(n_24), .C2(n_0_581), + .ZN(n_0_436) + ); + INV_X1_LVT i_0_460( + .A(n_0_436), .ZN(n_0_435) + ); + AOI22_X1_LVT i_0_458( + .A1(op1[24]), .A2(n_0_573), .B1(op1[28]), .B2(n_0_496), .ZN(n_0_433) + ); + OAI22_X1_LVT i_0_457( + .A1(op2[1]), .A2(n_0_433), .B1(n_0_728), .B2(n_0_478), .ZN(n_0_432) + ); + INV_X1_LVT i_0_456( + .A(n_0_432), .ZN(n_0_431) + ); + OAI22_X1_LVT i_0_454( + .A1(n_0_562), .A2(n_0_431), .B1(n_0_548), .B2(n_0_447), .ZN(n_0_429) + ); + AOI22_X1_LVT i_0_459( + .A1(n_0_736), .A2(n_0_565), .B1(op1[24]), .B2(n_0_566), .ZN(n_0_434) + ); + AOI211_X1_LVT i_0_453( + .A(n_0_435), .B(n_0_429), .C1(op2[24]), .C2(n_0_434), .ZN(n_0_428) + ); + NAND2_X1_LVT i_0_467( + .A1(n_0_693), .A2(n_0_521), .ZN(n_0_442) + ); + NOR2_X1_LVT i_0_469( + .A1(op2[3]), .A2(n_0_603), .ZN(n_0_444) + ); + AOI21_X1_LVT i_0_468( + .A(n_0_444), .B1(op1[9]), .B2(n_0_618), .ZN(n_0_443) + ); + OAI21_X1_LVT i_0_466( + .A(n_0_442), .B1(n_0_693), .B2(n_0_443), .ZN(n_0_441) + ); + NAND2_X1_LVT i_0_465( + .A1(op2[1]), .A2(n_0_441), .ZN(n_0_440) + ); + OAI21_X1_LVT i_0_464( + .A(n_0_440), .B1(op2[1]), .B2(n_0_481), .ZN(n_0_439) + ); + OAI221_X1_LVT i_0_463( + .A(n_0_620), .B1(op2[0]), .B2(n_0_456), .C1(n_0_701), .C2(n_0_439), .ZN(n_0_438) + ); + NAND3_X1_LVT i_0_452( + .A1(n_0_430), .A2(n_0_428), .A3(n_0_438), .ZN(result[24]) + ); + INV_X1_LVT i_0_751( + .A(op2[23]), .ZN(n_0_718) + ); + AOI221_X1_LVT i_0_440( + .A(n_0_718), .B1(op1[23]), .B2(n_0_566), .C1(n_0_719), .C2(n_0_565), .ZN(n_0_416) + ); + INV_X1_LVT i_10_115( + .A(n_10_91), .ZN(n_10_92) + ); + NOR2_X1_LVT i_10_116( + .A1(n_10_90), .A2(n_10_92), .ZN(n_10_93) + ); + XNOR2_X1_LVT i_10_117( + .A(n_10_88), .B(n_10_93), .ZN(n_55) + ); + AOI222_X1_LVT i_0_438( + .A1(n_23), .A2(n_0_581), .B1(n_0_544), .B2(n_0_466), .C1(n_55), .C2(n_0_580), + .ZN(n_0_414) + ); + OAI21_X1_LVT i_0_437( + .A(n_0_414), .B1(n_0_548), .B2(n_0_431), .ZN(n_0_413) + ); + OAI21_X1_LVT i_0_439( + .A(n_0_681), .B1(op2[23]), .B2(n_0_568), .ZN(n_0_415) + ); + AOI211_X1_LVT i_0_436( + .A(n_0_416), .B(n_0_413), .C1(op1[23]), .C2(n_0_415), .ZN(n_0_412) + ); + AOI22_X1_LVT i_0_444( + .A1(n_0_723), .A2(n_0_719), .B1(op2[3]), .B2(n_0_691), .ZN(n_0_420) + ); + AOI22_X1_LVT i_0_443( + .A1(n_0_575), .A2(n_0_420), .B1(op1[27]), .B2(n_0_496), .ZN(n_0_419) + ); + AOI22_X1_LVT i_0_442( + .A1(op2[1]), .A2(n_0_449), .B1(n_0_728), .B2(n_0_419), .ZN(n_0_418) + ); + INV_X1_LVT i_0_441( + .A(n_0_418), .ZN(n_0_417) + ); + NAND2_X1_LVT i_0_447( + .A1(n_0_728), .A2(n_0_458), .ZN(n_0_423) + ); + NOR2_X1_LVT i_0_451( + .A1(op2[3]), .A2(n_0_594), .ZN(n_0_427) + ); + AOI21_X1_LVT i_0_450( + .A(n_0_427), .B1(op1[8]), .B2(n_0_618), .ZN(n_0_426) + ); + OAI22_X1_LVT i_0_449( + .A1(n_0_693), .A2(n_0_426), .B1(op2[2]), .B2(n_0_507), .ZN(n_0_425) + ); + INV_X1_LVT i_0_448( + .A(n_0_425), .ZN(n_0_424) + ); + OAI21_X1_LVT i_0_446( + .A(n_0_423), .B1(n_0_728), .B2(n_0_424), .ZN(n_0_422) + ); + AOI22_X1_LVT i_0_445( + .A1(op2[0]), .A2(n_0_422), .B1(n_0_701), .B2(n_0_439), .ZN(n_0_421) + ); + OAI221_X1_LVT i_0_435( + .A(n_0_412), .B1(n_0_562), .B2(n_0_417), .C1(n_0_621), .C2(n_0_421), .ZN(result[23]) + ); + XNOR2_X1_LVT i_10_109( + .A(n_10_85), .B(n_10_86), .ZN(n_54) + ); + AOI22_X1_LVT i_0_419( + .A1(n_54), .A2(n_0_580), .B1(n_22), .B2(n_0_581), .ZN(n_0_396) + ); + INV_X1_LVT i_0_719( + .A(op2[22]), .ZN(n_0_686) + ); + AOI21_X1_LVT i_0_420( + .A(aluBypass), .B1(n_0_686), .B2(n_0_569), .ZN(n_0_397) + ); + OAI21_X1_LVT i_0_418( + .A(n_0_396), .B1(n_0_687), .B2(n_0_397), .ZN(n_0_395) + ); + AOI22_X1_LVT i_0_421( + .A1(op1[22]), .A2(n_0_566), .B1(n_0_687), .B2(n_0_565), .ZN(n_0_398) + ); + AOI21_X1_LVT i_0_417( + .A(n_0_395), .B1(op2[22]), .B2(n_0_398), .ZN(n_0_394) + ); + NAND2_X1_LVT i_0_432( + .A1(n_0_728), .A2(n_0_441), .ZN(n_0_409) + ); + AND2_X1_LVT i_0_434( + .A1(n_0_738), .A2(n_0_619), .ZN(n_0_411) + ); + AOI22_X1_LVT i_0_433( + .A1(n_0_693), .A2(n_0_482), .B1(op2[2]), .B2(n_0_411), .ZN(n_0_410) + ); + OAI21_X1_LVT i_0_431( + .A(n_0_409), .B1(n_0_728), .B2(n_0_410), .ZN(n_0_408) + ); + OAI22_X1_LVT i_0_430( + .A1(n_0_701), .A2(n_0_408), .B1(op2[0]), .B2(n_0_422), .ZN(n_0_407) + ); + AOI22_X1_LVT i_0_429( + .A1(n_0_723), .A2(n_0_687), .B1(op2[3]), .B2(n_0_717), .ZN(n_0_406) + ); + AOI22_X1_LVT i_0_428( + .A1(n_0_575), .A2(n_0_406), .B1(op1[26]), .B2(n_0_496), .ZN(n_0_405) + ); + AND2_X1_LVT i_0_427( + .A1(n_0_728), .A2(n_0_405), .ZN(n_0_404) + ); + AOI21_X1_LVT i_0_426( + .A(n_0_404), .B1(op2[1]), .B2(n_0_433), .ZN(n_0_403) + ); + INV_X1_LVT i_0_425( + .A(n_0_403), .ZN(n_0_402) + ); + OAI222_X1_LVT i_0_424( + .A1(n_0_545), .A2(n_0_467), .B1(n_0_701), .B2(n_0_417), .C1(op2[0]), .C2(n_0_402), + .ZN(n_0_401) + ); + NOR2_X1_LVT i_0_496( + .A1(n_0_738), .A2(n_0_691), .ZN(n_0_469) + ); + INV_X1_LVT i_0_495( + .A(n_0_469), .ZN(n_0_468) + ); + NAND3_X1_LVT i_0_423( + .A1(n_0_693), .A2(n_0_468), .A3(n_0_404), .ZN(n_0_400) + ); + OAI21_X1_LVT i_0_422( + .A(n_0_401), .B1(op2[0]), .B2(n_0_400), .ZN(n_0_399) + ); + OAI221_X1_LVT i_0_416( + .A(n_0_394), .B1(n_0_621), .B2(n_0_407), .C1(n_0_579), .C2(n_0_399), .ZN(result[22]) + ); + INV_X1_LVT i_0_759( + .A(op1[21]), .ZN(n_0_726) + ); + AOI22_X1_LVT i_0_399( + .A1(op1[21]), .A2(n_0_566), .B1(n_0_726), .B2(n_0_565), .ZN(n_0_377) + ); + NOR2_X1_LVT i_0_692( + .A1(n_0_726), .A2(op2[21]), .ZN(n_0_659) + ); + AOI222_X1_LVT i_0_398( + .A1(op2[21]), .A2(n_0_377), .B1(n_21), .B2(n_0_581), .C1(n_0_659), .C2(n_0_569), + .ZN(n_0_376) + ); + INV_X1_LVT i_0_397( + .A(n_0_376), .ZN(n_0_375) + ); + INV_X1_LVT i_10_104( + .A(n_10_82), .ZN(n_10_83) + ); + NOR2_X1_LVT i_10_105( + .A1(n_10_81), .A2(n_10_83), .ZN(n_10_84) + ); + XNOR2_X1_LVT i_10_106( + .A(n_10_79), .B(n_10_84), .ZN(n_53) + ); + AOI221_X1_LVT i_0_396( + .A(n_0_375), .B1(n_53), .B2(n_0_580), .C1(op1[21]), .C2(aluBypass), .ZN(n_0_374) + ); + INV_X1_LVT i_0_608( + .A(n_0_577), .ZN(n_0_576) + ); + NAND2_X1_LVT i_0_403( + .A1(op2[0]), .A2(n_0_402), .ZN(n_0_381) + ); + AND2_X1_LVT i_0_410( + .A1(op2[1]), .A2(n_0_419), .ZN(n_0_388) + ); + OAI22_X1_LVT i_0_408( + .A1(n_0_723), .A2(n_0_710), .B1(n_0_726), .B2(op2[3]), .ZN(n_0_386) + ); + AOI22_X1_LVT i_0_407( + .A1(n_0_575), .A2(n_0_386), .B1(op1[25]), .B2(n_0_496), .ZN(n_0_385) + ); + AOI21_X1_LVT i_0_395( + .A(n_0_388), .B1(n_0_728), .B2(n_0_385), .ZN(n_0_373) + ); + OAI211_X1_LVT i_0_394( + .A(n_0_576), .B(n_0_381), .C1(op2[0]), .C2(n_0_373), .ZN(n_0_372) + ); + AOI21_X1_LVT i_0_402( + .A(n_0_381), .B1(n_0_466), .B2(n_0_400), .ZN(n_0_380) + ); + INV_X1_LVT i_0_401( + .A(n_0_380), .ZN(n_0_379) + ); + NOR2_X1_LVT i_0_409( + .A1(n_0_575), .A2(n_0_467), .ZN(n_0_387) + ); + INV_X1_LVT i_0_406( + .A(n_0_385), .ZN(n_0_384) + ); + NOR2_X1_LVT i_0_405( + .A1(n_0_387), .A2(n_0_384), .ZN(n_0_383) + ); + AOI22_X1_LVT i_0_404( + .A1(n_0_467), .A2(n_0_388), .B1(n_0_728), .B2(n_0_383), .ZN(n_0_382) + ); + OAI211_X1_LVT i_0_400( + .A(n_0_544), .B(n_0_379), .C1(op2[0]), .C2(n_0_382), .ZN(n_0_378) + ); + AOI22_X1_LVT i_0_415( + .A1(op1[14]), .A2(n_0_616), .B1(op1[6]), .B2(n_0_618), .ZN(n_0_393) + ); + NOR2_X1_LVT i_0_414( + .A1(n_0_693), .A2(n_0_393), .ZN(n_0_392) + ); + AOI21_X1_LVT i_0_413( + .A(n_0_392), .B1(n_0_693), .B2(n_0_460), .ZN(n_0_391) + ); + OAI22_X1_LVT i_0_412( + .A1(n_0_728), .A2(n_0_391), .B1(op2[1]), .B2(n_0_424), .ZN(n_0_390) + ); + OAI221_X1_LVT i_0_411( + .A(n_0_620), .B1(op2[0]), .B2(n_0_408), .C1(n_0_701), .C2(n_0_390), .ZN(n_0_389) + ); + NAND4_X1_LVT i_0_393( + .A1(n_0_374), .A2(n_0_372), .A3(n_0_378), .A4(n_0_389), .ZN(result[21]) + ); + OAI221_X1_LVT i_0_388( + .A(op2[20]), .B1(n_0_727), .B2(n_0_567), .C1(op1[20]), .C2(n_0_564), .ZN(n_0_367) + ); + NOR2_X1_LVT i_0_691( + .A1(n_0_727), .A2(op2[20]), .ZN(n_0_658) + ); + AOI22_X1_LVT i_0_387( + .A1(op1[20]), .A2(aluBypass), .B1(n_0_658), .B2(n_0_569), .ZN(n_0_366) + ); + XNOR2_X1_LVT i_10_98( + .A(n_10_76), .B(n_10_77), .ZN(n_52) + ); + AOI22_X1_LVT i_0_386( + .A1(n_52), .A2(n_0_580), .B1(n_20), .B2(n_0_581), .ZN(n_0_365) + ); + AOI221_X1_LVT i_0_392( + .A(op2[4]), .B1(n_0_727), .B2(n_0_723), .C1(op2[3]), .C2(n_0_698), .ZN(n_0_371) + ); + AOI22_X1_LVT i_0_391( + .A1(op1[24]), .A2(n_0_496), .B1(n_0_693), .B2(n_0_371), .ZN(n_0_370) + ); + OAI22_X1_LVT i_0_390( + .A1(op2[1]), .A2(n_0_370), .B1(n_0_728), .B2(n_0_405), .ZN(n_0_369) + ); + OAI221_X1_LVT i_0_385( + .A(n_0_576), .B1(n_0_701), .B2(n_0_373), .C1(op2[0]), .C2(n_0_369), .ZN(n_0_364) + ); + AND4_X1_LVT i_0_384( + .A1(n_0_367), .A2(n_0_366), .A3(n_0_365), .A4(n_0_364), .ZN(n_0_363) + ); + AOI22_X1_LVT i_0_383( + .A1(op1[13]), .A2(n_0_616), .B1(op1[5]), .B2(n_0_618), .ZN(n_0_362) + ); + AOI22_X1_LVT i_0_382( + .A1(op2[2]), .A2(n_0_362), .B1(n_0_693), .B2(n_0_443), .ZN(n_0_361) + ); + NAND2_X1_LVT i_0_381( + .A1(op2[1]), .A2(n_0_361), .ZN(n_0_360) + ); + OAI21_X1_LVT i_0_380( + .A(n_0_360), .B1(op2[1]), .B2(n_0_410), .ZN(n_0_359) + ); + OAI221_X1_LVT i_0_379( + .A(n_0_620), .B1(n_0_701), .B2(n_0_359), .C1(op2[0]), .C2(n_0_390), .ZN(n_0_358) + ); + OR2_X1_LVT i_0_389( + .A1(n_0_387), .A2(n_0_369), .ZN(n_0_368) + ); + AOI22_X1_LVT i_0_378( + .A1(op2[0]), .A2(n_0_382), .B1(n_0_701), .B2(n_0_368), .ZN(n_0_357) + ); + OAI211_X1_LVT i_0_377( + .A(n_0_363), .B(n_0_358), .C1(n_0_545), .C2(n_0_357), .ZN(result[20]) + ); + OAI22_X1_LVT i_0_370( + .A1(op2[3]), .A2(n_0_689), .B1(n_0_723), .B2(n_0_688), .ZN(n_0_350) + ); + AND2_X1_LVT i_0_369( + .A1(n_0_738), .A2(n_0_350), .ZN(n_0_349) + ); + AOI22_X1_LVT i_0_368( + .A1(n_0_498), .A2(n_0_420), .B1(n_0_693), .B2(n_0_349), .ZN(n_0_348) + ); + AND2_X1_LVT i_0_367( + .A1(n_0_728), .A2(n_0_348), .ZN(n_0_347) + ); + AOI21_X1_LVT i_0_359( + .A(n_0_347), .B1(op2[1]), .B2(n_0_385), .ZN(n_0_339) + ); + OAI221_X1_LVT i_0_357( + .A(n_0_576), .B1(n_0_701), .B2(n_0_369), .C1(op2[0]), .C2(n_0_339), .ZN(n_0_337) + ); + NAND2_X1_LVT i_0_363( + .A1(n_19), .A2(n_0_581), .ZN(n_0_343) + ); + INV_X1_LVT i_0_723( + .A(op2[19]), .ZN(n_0_690) + ); + AOI221_X1_LVT i_0_364( + .A(n_0_690), .B1(n_0_689), .B2(n_0_565), .C1(op1[19]), .C2(n_0_566), .ZN(n_0_344) + ); + XNOR2_X1_LVT i_10_94( + .A(n_10_73), .B(n_10_74), .ZN(n_51) + ); + AOI221_X1_LVT i_0_361( + .A(n_0_344), .B1(op1[19]), .B2(aluBypass), .C1(n_51), .C2(n_0_580), .ZN(n_0_341) + ); + NAND3_X1_LVT i_0_362( + .A1(n_0_690), .A2(op1[19]), .A3(n_0_569), .ZN(n_0_342) + ); + NAND3_X1_LVT i_0_360( + .A1(n_0_343), .A2(n_0_341), .A3(n_0_342), .ZN(n_0_340) + ); + AOI22_X1_LVT i_0_376( + .A1(op1[12]), .A2(n_0_616), .B1(op1[4]), .B2(n_0_618), .ZN(n_0_356) + ); + OAI22_X1_LVT i_0_375( + .A1(n_0_693), .A2(n_0_356), .B1(op2[2]), .B2(n_0_426), .ZN(n_0_355) + ); + INV_X1_LVT i_0_374( + .A(n_0_355), .ZN(n_0_354) + ); + OAI22_X1_LVT i_0_373( + .A1(op2[1]), .A2(n_0_391), .B1(n_0_728), .B2(n_0_354), .ZN(n_0_353) + ); + AOI22_X1_LVT i_0_372( + .A1(n_0_701), .A2(n_0_359), .B1(op2[0]), .B2(n_0_353), .ZN(n_0_352) + ); + INV_X1_LVT i_0_371( + .A(n_0_352), .ZN(n_0_351) + ); + AOI21_X1_LVT i_0_358( + .A(n_0_340), .B1(n_0_620), .B2(n_0_351), .ZN(n_0_338) + ); + AOI22_X1_LVT i_0_366( + .A1(n_0_468), .A2(n_0_347), .B1(op2[1]), .B2(n_0_383), .ZN(n_0_346) + ); + AOI22_X1_LVT i_0_365( + .A1(n_0_701), .A2(n_0_346), .B1(op2[0]), .B2(n_0_368), .ZN(n_0_345) + ); + OAI211_X1_LVT i_0_356( + .A(n_0_337), .B(n_0_338), .C1(n_0_545), .C2(n_0_345), .ZN(result[19]) + ); + XNOR2_X1_LVT i_10_90( + .A(n_10_70), .B(n_10_71), .ZN(n_50) + ); + NAND2_X1_LVT i_0_342( + .A1(n_50), .A2(n_0_580), .ZN(n_0_323) + ); + OAI21_X1_LVT i_0_343( + .A(n_0_681), .B1(op2[18]), .B2(n_0_568), .ZN(n_0_324) + ); + AOI22_X1_LVT i_0_341( + .A1(op1[18]), .A2(n_0_324), .B1(n_18), .B2(n_0_581), .ZN(n_0_322) + ); + OAI221_X1_LVT i_0_340( + .A(op2[18]), .B1(n_0_705), .B2(n_0_567), .C1(op1[18]), .C2(n_0_564), .ZN(n_0_321) + ); + NAND3_X1_LVT i_0_339( + .A1(n_0_323), .A2(n_0_322), .A3(n_0_321), .ZN(n_0_320) + ); + OAI22_X1_LVT i_0_351( + .A1(op2[3]), .A2(n_0_705), .B1(n_0_723), .B2(n_0_711), .ZN(n_0_332) + ); + AND2_X1_LVT i_0_350( + .A1(n_0_738), .A2(n_0_332), .ZN(n_0_331) + ); + AOI22_X1_LVT i_0_349( + .A1(n_0_498), .A2(n_0_406), .B1(n_0_693), .B2(n_0_331), .ZN(n_0_330) + ); + NAND2_X1_LVT i_0_348( + .A1(n_0_728), .A2(n_0_330), .ZN(n_0_329) + ); + NAND2_X1_LVT i_0_347( + .A1(op2[1]), .A2(n_0_370), .ZN(n_0_328) + ); + AND2_X1_LVT i_0_338( + .A1(n_0_329), .A2(n_0_328), .ZN(n_0_319) + ); + OAI22_X1_LVT i_0_337( + .A1(op2[0]), .A2(n_0_319), .B1(n_0_701), .B2(n_0_339), .ZN(n_0_318) + ); + INV_X1_LVT i_0_336( + .A(n_0_318), .ZN(n_0_317) + ); + AOI21_X1_LVT i_0_335( + .A(n_0_320), .B1(n_0_578), .B2(n_0_317), .ZN(n_0_316) + ); + OAI22_X1_LVT i_0_346( + .A1(n_0_469), .A2(n_0_329), .B1(n_0_387), .B2(n_0_328), .ZN(n_0_327) + ); + NAND2_X1_LVT i_0_344( + .A1(n_0_544), .A2(n_0_346), .ZN(n_0_325) + ); + NAND2_X1_LVT i_0_354( + .A1(n_0_728), .A2(n_0_361), .ZN(n_0_335) + ); + AOI22_X1_LVT i_0_355( + .A1(n_0_612), .A2(n_0_498), .B1(n_0_693), .B2(n_0_411), .ZN(n_0_336) + ); + OAI21_X1_LVT i_0_353( + .A(n_0_335), .B1(n_0_728), .B2(n_0_336), .ZN(n_0_334) + ); + AOI22_X1_LVT i_0_352( + .A1(n_0_701), .A2(n_0_353), .B1(op2[0]), .B2(n_0_334), .ZN(n_0_333) + ); + OAI221_X1_LVT i_0_334( + .A(n_0_316), .B1(n_0_327), .B2(n_0_325), .C1(n_0_621), .C2(n_0_333), .ZN(result[18]) + ); + NAND2_X1_LVT i_0_325( + .A1(n_17), .A2(n_0_581), .ZN(n_0_307) + ); + INV_X1_LVT i_0_765( + .A(op1[17]), .ZN(n_0_732) + ); + AOI22_X1_LVT i_0_324( + .A1(n_0_732), .A2(n_0_565), .B1(op1[17]), .B2(n_0_566), .ZN(n_0_306) + ); + NOR2_X1_LVT i_0_693( + .A1(n_0_732), .A2(op2[17]), .ZN(n_0_660) + ); + XNOR2_X1_LVT i_10_86( + .A(n_10_67), .B(n_10_68), .ZN(n_49) + ); + AOI222_X1_LVT i_0_323( + .A1(op2[17]), .A2(n_0_306), .B1(n_0_660), .B2(n_0_569), .C1(n_49), .C2(n_0_580), + .ZN(n_0_305) + ); + OAI211_X1_LVT i_0_322( + .A(n_0_307), .B(n_0_305), .C1(n_0_732), .C2(n_0_681), .ZN(n_0_304) + ); + AOI22_X1_LVT i_0_331( + .A1(op2[3]), .A2(op1[25]), .B1(op1[17]), .B2(n_0_723), .ZN(n_0_313) + ); + NOR2_X1_LVT i_0_330( + .A1(op2[4]), .A2(n_0_313), .ZN(n_0_312) + ); + AOI22_X1_LVT i_0_329( + .A1(n_0_498), .A2(n_0_386), .B1(n_0_693), .B2(n_0_312), .ZN(n_0_311) + ); + OAI22_X1_LVT i_0_328( + .A1(op2[1]), .A2(n_0_311), .B1(n_0_728), .B2(n_0_348), .ZN(n_0_310) + ); + OR2_X1_LVT i_0_327( + .A1(op2[0]), .A2(n_0_310), .ZN(n_0_309) + ); + OAI21_X1_LVT i_0_321( + .A(n_0_576), .B1(n_0_701), .B2(n_0_319), .ZN(n_0_303) + ); + INV_X1_LVT i_0_320( + .A(n_0_303), .ZN(n_0_302) + ); + AOI21_X1_LVT i_0_319( + .A(n_0_304), .B1(n_0_309), .B2(n_0_302), .ZN(n_0_301) + ); + INV_X1_LVT i_0_345( + .A(n_0_327), .ZN(n_0_326) + ); + OAI22_X1_LVT i_0_326( + .A1(n_0_701), .A2(n_0_326), .B1(n_0_469), .B2(n_0_309), .ZN(n_0_308) + ); + NOR2_X1_LVT i_0_318( + .A1(op2[2]), .A2(n_0_393), .ZN(n_0_300) + ); + AOI21_X1_LVT i_0_317( + .A(n_0_300), .B1(n_0_597), .B2(n_0_498), .ZN(n_0_299) + ); + OAI22_X1_LVT i_0_316( + .A1(n_0_728), .A2(n_0_299), .B1(op2[1]), .B2(n_0_354), .ZN(n_0_298) + ); + OAI22_X1_LVT i_0_315( + .A1(op2[0]), .A2(n_0_334), .B1(n_0_701), .B2(n_0_298), .ZN(n_0_297) + ); + OAI221_X1_LVT i_0_314( + .A(n_0_301), .B1(n_0_545), .B2(n_0_308), .C1(n_0_621), .C2(n_0_297), .ZN(result[17]) + ); + XNOR2_X1_LVT i_10_82( + .A(n_10_64), .B(n_10_65), .ZN(n_48) + ); + AOI22_X1_LVT i_0_301( + .A1(n_48), .A2(n_0_580), .B1(n_16), .B2(n_0_581), .ZN(n_0_284) + ); + NAND2_X1_LVT i_0_333( + .A1(n_0_544), .A2(n_0_469), .ZN(n_0_315) + ); + INV_X1_LVT i_0_332( + .A(n_0_315), .ZN(n_0_314) + ); + OAI21_X1_LVT i_0_302( + .A(n_0_681), .B1(op2[16]), .B2(n_0_568), .ZN(n_0_285) + ); + AOI21_X1_LVT i_0_300( + .A(n_0_314), .B1(op1[16]), .B2(n_0_285), .ZN(n_0_283) + ); + INV_X1_LVT i_0_772( + .A(op1[16]), .ZN(n_0_739) + ); + OAI221_X1_LVT i_0_303( + .A(op2[16]), .B1(op1[16]), .B2(n_0_564), .C1(n_0_739), .C2(n_0_567), .ZN(n_0_286) + ); + NAND3_X1_LVT i_0_299( + .A1(n_0_284), .A2(n_0_283), .A3(n_0_286), .ZN(n_0_282) + ); + INV_X1_LVT i_0_593( + .A(n_0_562), .ZN(n_0_561) + ); + OAI22_X1_LVT i_0_307( + .A1(op1[16]), .A2(op2[3]), .B1(op1[24]), .B2(n_0_723), .ZN(n_0_290) + ); + NOR2_X1_LVT i_0_306( + .A1(op2[4]), .A2(n_0_290), .ZN(n_0_289) + ); + AOI22_X1_LVT i_0_305( + .A1(n_0_693), .A2(n_0_289), .B1(op2[2]), .B2(n_0_371), .ZN(n_0_288) + ); + OAI22_X1_LVT i_0_304( + .A1(n_0_728), .A2(n_0_330), .B1(op2[1]), .B2(n_0_288), .ZN(n_0_287) + ); + AOI221_X1_LVT i_0_298( + .A(n_0_282), .B1(n_0_547), .B2(n_0_310), .C1(n_0_561), .C2(n_0_287), .ZN(n_0_281) + ); + INV_X1_LVT i_0_762( + .A(op1[1]), .ZN(n_0_729) + ); + OAI22_X1_LVT i_0_313( + .A1(n_0_722), .A2(n_0_615), .B1(n_0_729), .B2(n_0_617), .ZN(n_0_296) + ); + NAND2_X1_LVT i_0_312( + .A1(op2[2]), .A2(n_0_296), .ZN(n_0_295) + ); + OAI21_X1_LVT i_0_311( + .A(n_0_295), .B1(op2[2]), .B2(n_0_362), .ZN(n_0_294) + ); + NAND2_X1_LVT i_0_310( + .A1(op2[1]), .A2(n_0_294), .ZN(n_0_293) + ); + OAI21_X1_LVT i_0_309( + .A(n_0_293), .B1(op2[1]), .B2(n_0_336), .ZN(n_0_292) + ); + OAI22_X1_LVT i_0_308( + .A1(op2[0]), .A2(n_0_298), .B1(n_0_701), .B2(n_0_292), .ZN(n_0_291) + ); + OAI21_X1_LVT i_0_297( + .A(n_0_281), .B1(n_0_621), .B2(n_0_291), .ZN(result[16]) + ); + OAI221_X1_LVT i_0_286( + .A(op2[15]), .B1(n_0_734), .B2(n_0_567), .C1(op1[15]), .C2(n_0_564), .ZN(n_0_270) + ); + AOI21_X1_LVT i_0_288( + .A(n_0_314), .B1(n_15), .B2(n_0_581), .ZN(n_0_272) + ); + INV_X1_LVT i_0_287( + .A(n_0_272), .ZN(n_0_271) + ); + XNOR2_X1_LVT i_10_78( + .A(n_10_61), .B(n_10_62), .ZN(n_47) + ); + OAI21_X1_LVT i_0_285( + .A(n_0_681), .B1(op2[15]), .B2(n_0_568), .ZN(n_0_269) + ); + AOI221_X1_LVT i_0_284( + .A(n_0_271), .B1(n_47), .B2(n_0_580), .C1(op1[15]), .C2(n_0_269), .ZN(n_0_268) + ); + AOI22_X1_LVT i_0_296( + .A1(op1[8]), .A2(n_0_616), .B1(op1[0]), .B2(n_0_618), .ZN(n_0_280) + ); + AOI22_X1_LVT i_0_295( + .A1(op2[2]), .A2(n_0_280), .B1(n_0_693), .B2(n_0_356), .ZN(n_0_279) + ); + NAND2_X1_LVT i_0_294( + .A1(op2[1]), .A2(n_0_279), .ZN(n_0_278) + ); + OAI21_X1_LVT i_0_293( + .A(n_0_278), .B1(op2[1]), .B2(n_0_299), .ZN(n_0_277) + ); + OAI221_X1_LVT i_0_292( + .A(n_0_620), .B1(n_0_701), .B2(n_0_277), .C1(op2[0]), .C2(n_0_292), .ZN(n_0_276) + ); + OAI222_X1_LVT i_0_291( + .A1(n_0_719), .A2(n_0_617), .B1(n_0_691), .B2(n_0_605), .C1(n_0_734), .C2(n_0_615), + .ZN(n_0_275) + ); + OAI22_X1_LVT i_0_290( + .A1(n_0_693), .A2(n_0_349), .B1(op2[2]), .B2(n_0_275), .ZN(n_0_274) + ); + OAI22_X1_LVT i_0_289( + .A1(op2[1]), .A2(n_0_274), .B1(n_0_728), .B2(n_0_311), .ZN(n_0_273) + ); + AOI22_X1_LVT i_0_283( + .A1(n_0_561), .A2(n_0_273), .B1(n_0_547), .B2(n_0_287), .ZN(n_0_267) + ); + NAND4_X1_LVT i_0_282( + .A1(n_0_270), .A2(n_0_268), .A3(n_0_276), .A4(n_0_267), .ZN(result[15]) + ); + NOR2_X1_LVT i_0_278( + .A1(op2[0]), .A2(n_0_277), .ZN(n_0_263) + ); + NAND2_X1_LVT i_0_281( + .A1(n_0_612), .A2(n_0_575), .ZN(n_0_266) + ); + OAI21_X1_LVT i_0_280( + .A(n_0_266), .B1(n_0_713), .B2(n_0_497), .ZN(n_0_265) + ); + AOI22_X1_LVT i_0_279( + .A1(op2[1]), .A2(n_0_265), .B1(n_0_728), .B2(n_0_294), .ZN(n_0_264) + ); + AOI211_X1_LVT i_0_277( + .A(n_0_263), .B(n_0_621), .C1(op2[0]), .C2(n_0_264), .ZN(n_0_262) + ); + INV_X1_LVT i_0_754( + .A(op1[14]), .ZN(n_0_721) + ); + OAI21_X1_LVT i_0_273( + .A(op2[14]), .B1(n_0_721), .B2(n_0_567), .ZN(n_0_258) + ); + AOI21_X1_LVT i_0_272( + .A(n_0_258), .B1(n_0_721), .B2(n_0_565), .ZN(n_0_257) + ); + XNOR2_X1_LVT i_10_74( + .A(n_10_58), .B(n_10_59), .ZN(n_46) + ); + OAI21_X1_LVT i_0_276( + .A(n_0_681), .B1(op2[14]), .B2(n_0_568), .ZN(n_0_261) + ); + AOI222_X1_LVT i_0_275( + .A1(n_14), .A2(n_0_581), .B1(n_46), .B2(n_0_580), .C1(op1[14]), .C2(n_0_261), + .ZN(n_0_260) + ); + INV_X1_LVT i_0_274( + .A(n_0_260), .ZN(n_0_259) + ); + OAI222_X1_LVT i_0_271( + .A1(n_0_717), .A2(n_0_605), .B1(n_0_687), .B2(n_0_617), .C1(n_0_721), .C2(n_0_615), + .ZN(n_0_256) + ); + OAI22_X1_LVT i_0_270( + .A1(n_0_693), .A2(n_0_331), .B1(op2[2]), .B2(n_0_256), .ZN(n_0_255) + ); + AND2_X1_LVT i_0_269( + .A1(n_0_728), .A2(n_0_255), .ZN(n_0_254) + ); + NOR3_X1_LVT i_0_265( + .A1(op2[3]), .A2(op2[2]), .A3(op2[0]), .ZN(n_0_250) + ); + AOI21_X1_LVT i_0_268( + .A(n_0_254), .B1(op2[1]), .B2(n_0_288), .ZN(n_0_253) + ); + OAI22_X1_LVT i_0_266( + .A1(op2[0]), .A2(n_0_253), .B1(n_0_701), .B2(n_0_273), .ZN(n_0_251) + ); + AOI221_X1_LVT i_0_259( + .A(n_0_579), .B1(n_0_254), .B2(n_0_250), .C1(n_0_315), .C2(n_0_251), .ZN(n_0_244) + ); + OR4_X1_LVT i_0_258( + .A1(n_0_262), .A2(n_0_257), .A3(n_0_259), .A4(n_0_244), .ZN(result[14]) + ); + OAI221_X1_LVT i_0_245( + .A(op2[13]), .B1(op1[13]), .B2(n_0_564), .C1(n_0_714), .C2(n_0_567), .ZN(n_0_231) + ); + NAND2_X1_LVT i_0_244( + .A1(n_13), .A2(n_0_581), .ZN(n_0_230) + ); + OAI211_X1_LVT i_0_243( + .A(n_0_231), .B(n_0_230), .C1(n_0_714), .C2(n_0_681), .ZN(n_0_229) + ); + XNOR2_X1_LVT i_10_70( + .A(n_10_55), .B(n_10_56), .ZN(n_45) + ); + NOR2_X1_LVT i_0_695( + .A1(op2[13]), .A2(n_0_714), .ZN(n_0_662) + ); + AOI221_X1_LVT i_0_242( + .A(n_0_229), .B1(n_45), .B2(n_0_580), .C1(n_0_662), .C2(n_0_569), .ZN(n_0_228) + ); + INV_X1_LVT i_0_267( + .A(n_0_253), .ZN(n_0_252) + ); + OAI222_X1_LVT i_0_257( + .A1(n_0_714), .A2(n_0_615), .B1(n_0_726), .B2(n_0_617), .C1(n_0_710), .C2(n_0_605), + .ZN(n_0_243) + ); + OAI22_X1_LVT i_0_256( + .A1(n_0_693), .A2(n_0_312), .B1(op2[2]), .B2(n_0_243), .ZN(n_0_242) + ); + NAND2_X1_LVT i_0_255( + .A1(n_0_728), .A2(n_0_242), .ZN(n_0_241) + ); + NAND2_X1_LVT i_0_254( + .A1(op2[1]), .A2(n_0_274), .ZN(n_0_240) + ); + NAND2_X1_LVT i_0_241( + .A1(n_0_241), .A2(n_0_240), .ZN(n_0_227) + ); + OAI221_X1_LVT i_0_240( + .A(n_0_228), .B1(n_0_548), .B2(n_0_252), .C1(n_0_562), .C2(n_0_227), .ZN(n_0_226) + ); + NAND2_X1_LVT i_0_249( + .A1(n_0_728), .A2(n_0_279), .ZN(n_0_235) + ); + AOI22_X1_LVT i_0_250( + .A1(n_0_597), .A2(n_0_575), .B1(op1[6]), .B2(n_0_496), .ZN(n_0_236) + ); + OAI21_X1_LVT i_0_248( + .A(n_0_235), .B1(n_0_728), .B2(n_0_236), .ZN(n_0_234) + ); + INV_X1_LVT i_0_247( + .A(n_0_234), .ZN(n_0_233) + ); + AOI221_X1_LVT i_0_246( + .A(n_0_621), .B1(op2[0]), .B2(n_0_233), .C1(n_0_701), .C2(n_0_264), .ZN(n_0_232) + ); + NAND2_X1_LVT i_0_264( + .A1(op2[3]), .A2(n_0_469), .ZN(n_0_249) + ); + AOI21_X1_LVT i_0_262( + .A(n_0_468), .B1(n_0_693), .B2(n_0_249), .ZN(n_0_247) + ); + INV_X1_LVT i_0_261( + .A(n_0_247), .ZN(n_0_246) + ); + OAI211_X1_LVT i_0_260( + .A(n_0_252), .B(n_0_246), .C1(n_0_468), .C2(n_0_254), .ZN(n_0_245) + ); + OAI221_X1_LVT i_0_253( + .A(n_0_544), .B1(n_0_247), .B2(n_0_241), .C1(n_0_469), .C2(n_0_240), .ZN(n_0_239) + ); + INV_X1_LVT i_0_252( + .A(n_0_239), .ZN(n_0_238) + ); + AOI211_X1_LVT i_0_239( + .A(n_0_226), .B(n_0_232), .C1(n_0_245), .C2(n_0_238), .ZN(n_0_225) + ); + INV_X1_LVT i_0_238( + .A(n_0_225), .ZN(result[13]) + ); + OAI221_X1_LVT i_0_232( + .A(op2[12]), .B1(n_0_696), .B2(n_0_567), .C1(op1[12]), .C2(n_0_564), .ZN(n_0_219) + ); + OAI21_X1_LVT i_0_231( + .A(n_0_681), .B1(op2[12]), .B2(n_0_568), .ZN(n_0_218) + ); + XNOR2_X1_LVT i_10_66( + .A(n_10_52), .B(n_10_53), .ZN(n_44) + ); + AOI222_X1_LVT i_0_230( + .A1(n_12), .A2(n_0_581), .B1(op1[12]), .B2(n_0_218), .C1(n_44), .C2(n_0_580), + .ZN(n_0_217) + ); + OAI21_X1_LVT i_0_234( + .A(n_0_620), .B1(op2[1]), .B2(n_0_265), .ZN(n_0_221) + ); + INV_X1_LVT i_0_763( + .A(op1[5]), .ZN(n_0_730) + ); + OAI21_X1_LVT i_0_236( + .A(op2[2]), .B1(n_0_730), .B2(n_0_615), .ZN(n_0_223) + ); + OAI21_X1_LVT i_0_235( + .A(n_0_223), .B1(op2[2]), .B2(n_0_296), .ZN(n_0_222) + ); + AOI21_X1_LVT i_0_233( + .A(n_0_221), .B1(op2[1]), .B2(n_0_222), .ZN(n_0_220) + ); + NOR2_X1_LVT i_0_237( + .A1(n_0_577), .A2(n_0_227), .ZN(n_0_224) + ); + NOR4_X1_LVT i_0_223( + .A1(n_0_701), .A2(n_0_220), .A3(n_0_224), .A4(n_0_238), .ZN(n_0_210) + ); + NAND2_X1_LVT i_0_224( + .A1(n_0_544), .A2(n_0_247), .ZN(n_0_211) + ); + NAND2_X1_LVT i_0_222( + .A1(n_0_701), .A2(n_0_211), .ZN(n_0_209) + ); + OAI22_X1_LVT i_0_229( + .A1(op2[4]), .A2(n_0_696), .B1(n_0_738), .B2(n_0_698), .ZN(n_0_216) + ); + INV_X1_LVT i_0_228( + .A(n_0_216), .ZN(n_0_215) + ); + OAI22_X1_LVT i_0_227( + .A1(n_0_727), .A2(n_0_617), .B1(op2[3]), .B2(n_0_215), .ZN(n_0_214) + ); + OAI22_X1_LVT i_0_226( + .A1(n_0_693), .A2(n_0_289), .B1(op2[2]), .B2(n_0_214), .ZN(n_0_213) + ); + OAI22_X1_LVT i_0_225( + .A1(op2[1]), .A2(n_0_213), .B1(n_0_728), .B2(n_0_255), .ZN(n_0_212) + ); + AOI221_X1_LVT i_0_221( + .A(n_0_209), .B1(n_0_578), .B2(n_0_212), .C1(n_0_620), .C2(n_0_234), .ZN(n_0_208) + ); + OAI211_X1_LVT i_0_220( + .A(n_0_219), .B(n_0_217), .C1(n_0_210), .C2(n_0_208), .ZN(result[12]) + ); + OAI21_X1_LVT i_0_209( + .A(n_0_681), .B1(op2[11]), .B2(n_0_568), .ZN(n_0_197) + ); + AOI22_X1_LVT i_0_208( + .A1(n_11), .A2(n_0_581), .B1(op1[11]), .B2(n_0_197), .ZN(n_0_196) + ); + NAND2_X1_LVT i_0_207( + .A1(n_0_211), .A2(n_0_196), .ZN(n_0_195) + ); + AOI22_X1_LVT i_0_210( + .A1(op1[11]), .A2(n_0_566), .B1(n_0_706), .B2(n_0_565), .ZN(n_0_198) + ); + XNOR2_X1_LVT i_10_62( + .A(n_10_49), .B(n_10_50), .ZN(n_43) + ); + AOI221_X1_LVT i_0_206( + .A(n_0_195), .B1(op2[11]), .B2(n_0_198), .C1(n_43), .C2(n_0_580), .ZN(n_0_194) + ); + AOI221_X1_LVT i_0_215( + .A(op2[3]), .B1(n_0_738), .B2(n_0_706), .C1(op2[4]), .C2(n_0_688), .ZN(n_0_203) + ); + AOI21_X1_LVT i_0_214( + .A(n_0_203), .B1(op1[19]), .B2(n_0_618), .ZN(n_0_202) + ); + NAND2_X1_LVT i_0_213( + .A1(n_0_693), .A2(n_0_202), .ZN(n_0_201) + ); + OAI21_X1_LVT i_0_212( + .A(n_0_201), .B1(n_0_693), .B2(n_0_275), .ZN(n_0_200) + ); + OAI22_X1_LVT i_0_211( + .A1(n_0_728), .A2(n_0_242), .B1(op2[1]), .B2(n_0_200), .ZN(n_0_199) + ); + AOI22_X1_LVT i_0_205( + .A1(n_0_561), .A2(n_0_199), .B1(n_0_701), .B2(n_0_220), .ZN(n_0_193) + ); + NOR2_X1_LVT i_0_219( + .A1(op2[2]), .A2(n_0_280), .ZN(n_0_207) + ); + AOI21_X1_LVT i_0_218( + .A(n_0_207), .B1(op1[4]), .B2(n_0_496), .ZN(n_0_206) + ); + AOI22_X1_LVT i_0_217( + .A1(n_0_728), .A2(n_0_236), .B1(op2[1]), .B2(n_0_206), .ZN(n_0_205) + ); + AOI22_X1_LVT i_0_216( + .A1(n_0_578), .A2(n_0_212), .B1(n_0_620), .B2(n_0_205), .ZN(n_0_204) + ); + OAI211_X1_LVT i_0_204( + .A(n_0_194), .B(n_0_193), .C1(n_0_701), .C2(n_0_204), .ZN(result[11]) + ); + AOI22_X1_LVT i_0_194( + .A1(n_0_654), .A2(n_0_498), .B1(op1[7]), .B2(n_0_573), .ZN(n_0_183) + ); + OAI22_X1_LVT i_0_193( + .A1(n_0_728), .A2(n_0_183), .B1(op2[1]), .B2(n_0_222), .ZN(n_0_182) + ); + AOI22_X1_LVT i_0_192( + .A1(op2[0]), .A2(n_0_182), .B1(n_0_701), .B2(n_0_205), .ZN(n_0_181) + ); + NOR2_X1_LVT i_0_191( + .A1(n_0_621), .A2(n_0_181), .ZN(n_0_180) + ); + AOI22_X1_LVT i_0_190( + .A1(op1[10]), .A2(n_0_566), .B1(n_0_733), .B2(n_0_565), .ZN(n_0_179) + ); + XNOR2_X1_LVT i_10_58( + .A(n_10_46), .B(n_10_47), .ZN(n_42) + ); + AOI22_X1_LVT i_0_188( + .A1(op2[10]), .A2(n_0_179), .B1(n_42), .B2(n_0_580), .ZN(n_0_177) + ); + OAI21_X1_LVT i_0_189( + .A(n_0_681), .B1(op2[10]), .B2(n_0_568), .ZN(n_0_178) + ); + AOI22_X1_LVT i_0_187( + .A1(n_10), .A2(n_0_581), .B1(op1[10]), .B2(n_0_178), .ZN(n_0_176) + ); + NAND2_X1_LVT i_0_186( + .A1(n_0_177), .A2(n_0_176), .ZN(n_0_175) + ); + NOR2_X1_LVT i_0_203( + .A1(n_0_701), .A2(n_0_199), .ZN(n_0_192) + ); + NOR2_X1_LVT i_0_200( + .A1(n_0_693), .A2(n_0_256), .ZN(n_0_189) + ); + AOI221_X1_LVT i_0_202( + .A(n_0_596), .B1(op1[10]), .B2(n_0_616), .C1(op1[26]), .C2(n_0_606), .ZN(n_0_191) + ); + AOI21_X1_LVT i_0_199( + .A(n_0_189), .B1(n_0_693), .B2(n_0_191), .ZN(n_0_188) + ); + OR2_X1_LVT i_0_198( + .A1(op2[1]), .A2(n_0_188), .ZN(n_0_187) + ); + NAND2_X1_LVT i_0_197( + .A1(op2[1]), .A2(n_0_213), .ZN(n_0_186) + ); + NAND2_X1_LVT i_0_185( + .A1(n_0_187), .A2(n_0_186), .ZN(n_0_174) + ); + AOI211_X1_LVT i_0_184( + .A(n_0_577), .B(n_0_192), .C1(n_0_701), .C2(n_0_174), .ZN(n_0_173) + ); + INV_X1_LVT i_0_263( + .A(n_0_249), .ZN(n_0_248) + ); + OAI22_X1_LVT i_0_196( + .A1(n_0_248), .A2(n_0_187), .B1(n_0_247), .B2(n_0_186), .ZN(n_0_185) + ); + AOI221_X1_LVT i_0_195( + .A(n_0_545), .B1(n_0_246), .B2(n_0_192), .C1(n_0_701), .C2(n_0_185), .ZN(n_0_184) + ); + OR4_X1_LVT i_0_183( + .A1(n_0_180), .A2(n_0_175), .A3(n_0_173), .A4(n_0_184), .ZN(result[10]) + ); + INV_X1_LVT i_0_753( + .A(op2[9]), .ZN(n_0_720) + ); + AOI221_X1_LVT i_0_171( + .A(n_0_720), .B1(op1[9]), .B2(n_0_566), .C1(n_0_722), .C2(n_0_565), .ZN(n_0_161) + ); + XNOR2_X1_LVT i_10_54( + .A(n_10_43), .B(n_10_44), .ZN(n_41) + ); + AOI22_X1_LVT i_0_172( + .A1(n_9), .A2(n_0_581), .B1(n_41), .B2(n_0_580), .ZN(n_0_162) + ); + AOI21_X1_LVT i_0_170( + .A(aluBypass), .B1(n_0_720), .B2(n_0_569), .ZN(n_0_160) + ); + OAI21_X1_LVT i_0_169( + .A(n_0_162), .B1(n_0_722), .B2(n_0_160), .ZN(n_0_159) + ); + OAI222_X1_LVT i_0_182( + .A1(n_0_722), .A2(n_0_615), .B1(n_0_699), .B2(n_0_605), .C1(n_0_732), .C2(n_0_617), + .ZN(n_0_172) + ); + AOI22_X1_LVT i_0_181( + .A1(n_0_693), .A2(n_0_172), .B1(op2[2]), .B2(n_0_243), .ZN(n_0_171) + ); + NAND2_X1_LVT i_0_180( + .A1(n_0_728), .A2(n_0_171), .ZN(n_0_170) + ); + NAND2_X1_LVT i_0_179( + .A1(op2[1]), .A2(n_0_200), .ZN(n_0_169) + ); + OAI22_X1_LVT i_0_178( + .A1(n_0_248), .A2(n_0_170), .B1(n_0_247), .B2(n_0_169), .ZN(n_0_168) + ); + NOR3_X1_LVT i_0_177( + .A1(n_0_545), .A2(n_0_168), .A3(n_0_185), .ZN(n_0_167) + ); + NOR2_X1_LVT i_0_251( + .A1(n_0_704), .A2(n_0_615), .ZN(n_0_237) + ); + OAI22_X1_LVT i_0_176( + .A1(op1[2]), .A2(n_0_693), .B1(n_0_496), .B2(n_0_237), .ZN(n_0_166) + ); + OAI22_X1_LVT i_0_175( + .A1(op2[1]), .A2(n_0_206), .B1(n_0_728), .B2(n_0_166), .ZN(n_0_165) + ); + OAI221_X1_LVT i_0_174( + .A(n_0_620), .B1(op2[0]), .B2(n_0_182), .C1(n_0_701), .C2(n_0_165), .ZN(n_0_164) + ); + NAND2_X1_LVT i_0_173( + .A1(n_0_170), .A2(n_0_169), .ZN(n_0_163) + ); + OAI221_X1_LVT i_0_168( + .A(n_0_164), .B1(n_0_562), .B2(n_0_163), .C1(n_0_548), .C2(n_0_174), .ZN(n_0_158) + ); + OR4_X1_LVT i_0_167( + .A1(n_0_161), .A2(n_0_159), .A3(n_0_167), .A4(n_0_158), .ZN(result[9]) + ); + OAI21_X1_LVT i_0_160( + .A(n_0_693), .B1(n_0_730), .B2(n_0_615), .ZN(n_0_151) + ); + OAI21_X1_LVT i_0_159( + .A(op2[2]), .B1(n_0_729), .B2(n_0_615), .ZN(n_0_150) + ); + AND2_X1_LVT i_0_158( + .A1(n_0_151), .A2(n_0_150), .ZN(n_0_149) + ); + NAND2_X1_LVT i_0_157( + .A1(op2[1]), .A2(n_0_149), .ZN(n_0_148) + ); + OAI21_X1_LVT i_0_156( + .A(n_0_148), .B1(op2[1]), .B2(n_0_183), .ZN(n_0_147) + ); + OAI22_X1_LVT i_0_155( + .A1(op2[0]), .A2(n_0_165), .B1(n_0_701), .B2(n_0_147), .ZN(n_0_146) + ); + NOR2_X1_LVT i_0_154( + .A1(n_0_621), .A2(n_0_146), .ZN(n_0_145) + ); + INV_X1_LVT i_0_773( + .A(op1[8]), .ZN(n_0_740) + ); + NOR2_X1_LVT i_0_688( + .A1(n_0_740), .A2(op2[8]), .ZN(n_0_655) + ); + AOI22_X1_LVT i_0_153( + .A1(op1[8]), .A2(aluBypass), .B1(n_0_655), .B2(n_0_569), .ZN(n_0_144) + ); + OAI221_X1_LVT i_0_152( + .A(op2[8]), .B1(op1[8]), .B2(n_0_564), .C1(n_0_740), .C2(n_0_567), .ZN(n_0_143) + ); + XNOR2_X1_LVT i_10_51( + .A(n_10_39), .B(n_10_42), .ZN(n_40) + ); + AOI22_X1_LVT i_0_151( + .A1(n_40), .A2(n_0_580), .B1(n_8), .B2(n_0_581), .ZN(n_0_142) + ); + NAND3_X1_LVT i_0_150( + .A1(n_0_144), .A2(n_0_143), .A3(n_0_142), .ZN(n_0_141) + ); + OAI222_X1_LVT i_0_166( + .A1(n_0_740), .A2(n_0_615), .B1(n_0_739), .B2(n_0_617), .C1(n_0_736), .C2(n_0_605), + .ZN(n_0_157) + ); + OAI22_X1_LVT i_0_165( + .A1(op2[2]), .A2(n_0_157), .B1(n_0_693), .B2(n_0_214), .ZN(n_0_156) + ); + NOR2_X1_LVT i_0_164( + .A1(op2[1]), .A2(n_0_156), .ZN(n_0_155) + ); + AOI21_X1_LVT i_0_163( + .A(n_0_155), .B1(op2[1]), .B2(n_0_188), .ZN(n_0_154) + ); + AND2_X1_LVT i_0_162( + .A1(n_0_701), .A2(n_0_154), .ZN(n_0_153) + ); + AOI211_X1_LVT i_0_149( + .A(n_0_577), .B(n_0_153), .C1(op2[0]), .C2(n_0_163), .ZN(n_0_140) + ); + AOI221_X1_LVT i_0_161( + .A(n_0_545), .B1(op2[0]), .B2(n_0_168), .C1(n_0_249), .C2(n_0_153), .ZN(n_0_152) + ); + OR4_X1_LVT i_0_148( + .A1(n_0_145), .A2(n_0_141), .A3(n_0_140), .A4(n_0_152), .ZN(result[8]) + ); + AOI22_X1_LVT i_0_138( + .A1(op1[4]), .A2(n_0_573), .B1(op1[0]), .B2(n_0_496), .ZN(n_0_130) + ); + AOI22_X1_LVT i_0_137( + .A1(op2[1]), .A2(n_0_130), .B1(n_0_728), .B2(n_0_166), .ZN(n_0_129) + ); + OAI22_X1_LVT i_0_136( + .A1(n_0_701), .A2(n_0_129), .B1(op2[0]), .B2(n_0_147), .ZN(n_0_128) + ); + NOR2_X1_LVT i_0_135( + .A1(n_0_621), .A2(n_0_128), .ZN(n_0_127) + ); + OAI221_X1_LVT i_0_139( + .A(op2[7]), .B1(n_0_713), .B2(n_0_567), .C1(op1[7]), .C2(n_0_564), .ZN(n_0_131) + ); + INV_X1_LVT i_10_44( + .A(n_10_36), .ZN(n_10_37) + ); + NOR2_X1_LVT i_10_45( + .A1(n_10_35), .A2(n_10_37), .ZN(n_10_38) + ); + XNOR2_X1_LVT i_10_46( + .A(n_10_33), .B(n_10_38), .ZN(n_39) + ); + AOI22_X1_LVT i_0_141( + .A1(n_7), .A2(n_0_581), .B1(n_39), .B2(n_0_580), .ZN(n_0_133) + ); + INV_X1_LVT i_0_745( + .A(op2[7]), .ZN(n_0_712) + ); + AOI21_X1_LVT i_0_140( + .A(aluBypass), .B1(n_0_712), .B2(n_0_569), .ZN(n_0_132) + ); + OAI211_X1_LVT i_0_133( + .A(n_0_131), .B(n_0_133), .C1(n_0_713), .C2(n_0_132), .ZN(n_0_125) + ); + OAI22_X1_LVT i_0_147( + .A1(n_0_734), .A2(n_0_617), .B1(n_0_713), .B2(n_0_615), .ZN(n_0_139) + ); + AOI211_X1_LVT i_0_146( + .A(n_0_139), .B(n_0_248), .C1(op1[23]), .C2(n_0_606), .ZN(n_0_138) + ); + OAI22_X1_LVT i_0_145( + .A1(n_0_693), .A2(n_0_202), .B1(op2[2]), .B2(n_0_138), .ZN(n_0_137) + ); + NOR2_X1_LVT i_0_144( + .A1(op2[1]), .A2(n_0_137), .ZN(n_0_136) + ); + AOI21_X1_LVT i_0_143( + .A(n_0_136), .B1(op2[1]), .B2(n_0_171), .ZN(n_0_135) + ); + NAND2_X1_LVT i_0_142( + .A1(n_0_561), .A2(n_0_135), .ZN(n_0_134) + ); + OAI221_X1_LVT i_0_134( + .A(n_0_134), .B1(n_0_548), .B2(n_0_154), .C1(n_0_545), .C2(n_0_249), .ZN(n_0_126) + ); + OR3_X1_LVT i_0_132( + .A1(n_0_127), .A2(n_0_125), .A3(n_0_126), .ZN(result[7]) + ); + NAND2_X1_LVT i_0_124( + .A1(n_0_728), .A2(n_0_149), .ZN(n_0_117) + ); + OAI21_X1_LVT i_0_123( + .A(n_0_117), .B1(n_0_724), .B2(n_0_531), .ZN(n_0_116) + ); + OAI22_X1_LVT i_0_122( + .A1(n_0_701), .A2(n_0_116), .B1(op2[0]), .B2(n_0_129), .ZN(n_0_115) + ); + NOR2_X1_LVT i_0_121( + .A1(n_0_621), .A2(n_0_115), .ZN(n_0_114) + ); + XNOR2_X1_LVT i_10_38( + .A(n_10_30), .B(n_10_31), .ZN(n_38) + ); + AOI22_X1_LVT i_0_119( + .A1(n_6), .A2(n_0_581), .B1(n_38), .B2(n_0_580), .ZN(n_0_112) + ); + INV_X1_LVT i_0_735( + .A(op2[6]), .ZN(n_0_702) + ); + AOI21_X1_LVT i_0_120( + .A(aluBypass), .B1(n_0_702), .B2(n_0_569), .ZN(n_0_113) + ); + OAI21_X1_LVT i_0_118( + .A(n_0_112), .B1(n_0_704), .B2(n_0_113), .ZN(n_0_111) + ); + AOI221_X1_LVT i_0_117( + .A(n_0_702), .B1(n_0_704), .B2(n_0_565), .C1(op1[6]), .C2(n_0_566), .ZN(n_0_110) + ); + NOR3_X1_LVT i_0_116( + .A1(n_0_114), .A2(n_0_111), .A3(n_0_110), .ZN(n_0_109) + ); + AOI221_X1_LVT i_0_131( + .A(n_0_237), .B1(op1[14]), .B2(n_0_618), .C1(op2[4]), .C2(n_0_406), .ZN(n_0_124) + ); + NAND2_X1_LVT i_0_130( + .A1(n_0_693), .A2(n_0_124), .ZN(n_0_123) + ); + INV_X1_LVT i_0_201( + .A(n_0_191), .ZN(n_0_190) + ); + OAI21_X1_LVT i_0_129( + .A(n_0_123), .B1(n_0_693), .B2(n_0_190), .ZN(n_0_122) + ); + AOI22_X1_LVT i_0_128( + .A1(n_0_728), .A2(n_0_122), .B1(op2[1]), .B2(n_0_156), .ZN(n_0_121) + ); + INV_X1_LVT i_0_127( + .A(n_0_121), .ZN(n_0_120) + ); + OAI21_X1_LVT i_0_126( + .A(n_0_248), .B1(op2[1]), .B2(n_0_123), .ZN(n_0_119) + ); + AND2_X1_LVT i_0_125( + .A1(n_0_120), .A2(n_0_119), .ZN(n_0_118) + ); + NOR2_X1_LVT i_0_115( + .A1(n_0_545), .A2(n_0_118), .ZN(n_0_108) + ); + AOI21_X1_LVT i_0_114( + .A(n_0_108), .B1(n_0_576), .B2(n_0_121), .ZN(n_0_107) + ); + AOI22_X1_LVT i_0_113( + .A1(n_0_544), .A2(n_0_248), .B1(n_0_578), .B2(n_0_135), .ZN(n_0_106) + ); + OAI221_X1_LVT i_0_112( + .A(n_0_109), .B1(op2[0]), .B2(n_0_107), .C1(n_0_701), .C2(n_0_106), .ZN(result[6]) + ); + OAI221_X1_LVT i_0_100( + .A(op2[5]), .B1(op1[5]), .B2(n_0_564), .C1(n_0_730), .C2(n_0_567), .ZN(n_0_94) + ); + INV_X1_LVT i_0_764( + .A(op2[5]), .ZN(n_0_731) + ); + AOI21_X1_LVT i_0_99( + .A(aluBypass), .B1(n_0_731), .B2(n_0_569), .ZN(n_0_93) + ); + NOR2_X1_LVT i_0_98( + .A1(n_0_730), .A2(n_0_93), .ZN(n_0_92) + ); + XNOR2_X1_LVT i_10_35( + .A(n_10_26), .B(n_10_29), .ZN(n_37) + ); + AOI221_X1_LVT i_0_97( + .A(n_0_92), .B1(n_37), .B2(n_0_580), .C1(n_5), .C2(n_0_581), .ZN(n_0_91) + ); + OAI22_X1_LVT i_0_102( + .A1(n_0_694), .A2(n_0_531), .B1(op2[1]), .B2(n_0_130), .ZN(n_0_96) + ); + OAI221_X1_LVT i_0_101( + .A(n_0_620), .B1(n_0_701), .B2(n_0_96), .C1(op2[0]), .C2(n_0_116), .ZN(n_0_95) + ); + NAND3_X1_LVT i_0_111( + .A1(n_0_544), .A2(n_0_248), .A3(op2[2]), .ZN(n_0_105) + ); + NAND2_X1_LVT i_0_110( + .A1(op2[4]), .A2(n_0_386), .ZN(n_0_104) + ); + OAI21_X1_LVT i_0_109( + .A(n_0_104), .B1(n_0_714), .B2(n_0_617), .ZN(n_0_103) + ); + OAI22_X1_LVT i_0_108( + .A1(n_0_151), .A2(n_0_103), .B1(n_0_693), .B2(n_0_172), .ZN(n_0_102) + ); + NOR2_X1_LVT i_0_107( + .A1(op2[1]), .A2(n_0_102), .ZN(n_0_101) + ); + AOI21_X1_LVT i_0_106( + .A(n_0_101), .B1(op2[1]), .B2(n_0_137), .ZN(n_0_100) + ); + OAI21_X1_LVT i_0_105( + .A(n_0_105), .B1(n_0_579), .B2(n_0_100), .ZN(n_0_99) + ); + AOI21_X1_LVT i_0_104( + .A(n_0_118), .B1(n_0_682), .B2(n_0_120), .ZN(n_0_98) + ); + OAI22_X1_LVT i_0_103( + .A1(n_0_547), .A2(n_0_99), .B1(n_0_701), .B2(n_0_98), .ZN(n_0_97) + ); + NAND4_X1_LVT i_0_96( + .A1(n_0_94), .A2(n_0_91), .A3(n_0_95), .A4(n_0_97), .ZN(result[5]) + ); + INV_X1_LVT i_10_26( + .A(n_10_21), .ZN(n_10_22) + ); + NOR2_X1_LVT i_10_28( + .A1(n_10_22), .A2(n_10_23), .ZN(n_10_24) + ); + XNOR2_X1_LVT i_10_29( + .A(n_10_19), .B(n_10_24), .ZN(n_36) + ); + AOI222_X1_LVT i_0_89( + .A1(n_4), .A2(n_0_581), .B1(n_36), .B2(n_0_580), .C1(n_0_668), .C2(n_0_564), + .ZN(n_0_84) + ); + INV_X1_LVT i_0_770( + .A(op1[4]), .ZN(n_0_737) + ); + AOI221_X1_LVT i_0_90( + .A(aluBypass), .B1(op2[4]), .B2(n_0_567), .C1(n_0_738), .C2(n_0_569), .ZN(n_0_85) + ); + OAI21_X1_LVT i_0_88( + .A(n_0_84), .B1(n_0_737), .B2(n_0_85), .ZN(n_0_83) + ); + NOR2_X1_LVT i_0_689( + .A1(op2[4]), .A2(n_0_737), .ZN(n_0_656) + ); + AOI21_X1_LVT i_0_95( + .A(n_0_616), .B1(n_0_727), .B2(n_0_723), .ZN(n_0_90) + ); + OAI22_X1_LVT i_0_94( + .A1(n_0_723), .A2(n_0_216), .B1(n_0_656), .B2(n_0_90), .ZN(n_0_89) + ); + INV_X1_LVT i_0_93( + .A(n_0_89), .ZN(n_0_88) + ); + OAI22_X1_LVT i_0_92( + .A1(op2[2]), .A2(n_0_88), .B1(n_0_693), .B2(n_0_157), .ZN(n_0_87) + ); + OAI221_X1_LVT i_0_91( + .A(n_0_105), .B1(n_0_728), .B2(n_0_122), .C1(op2[1]), .C2(n_0_87), .ZN(n_0_86) + ); + AOI221_X1_LVT i_0_85( + .A(n_0_83), .B1(n_0_561), .B2(n_0_86), .C1(op2[0]), .C2(n_0_99), .ZN(n_0_80) + ); + AOI221_X1_LVT i_0_87( + .A(n_0_574), .B1(n_0_729), .B2(op2[1]), .C1(n_0_728), .C2(n_0_724), .ZN(n_0_82) + ); + OAI22_X1_LVT i_0_86( + .A1(op2[0]), .A2(n_0_96), .B1(n_0_701), .B2(n_0_82), .ZN(n_0_81) + ); + OAI21_X1_LVT i_0_84( + .A(n_0_80), .B1(n_0_621), .B2(n_0_81), .ZN(result[4]) + ); + AND2_X1_LVT i_0_81( + .A1(op2[1]), .A2(n_0_105), .ZN(n_0_77) + ); + NAND2_X1_LVT i_0_80( + .A1(n_0_102), .A2(n_0_77), .ZN(n_0_76) + ); + OAI221_X1_LVT i_0_83( + .A(n_0_693), .B1(n_0_654), .B2(n_0_484), .C1(n_0_738), .C2(n_0_350), .ZN(n_0_79) + ); + OAI21_X1_LVT i_0_82( + .A(n_0_79), .B1(n_0_693), .B2(n_0_138), .ZN(n_0_78) + ); + OAI21_X1_LVT i_0_79( + .A(n_0_76), .B1(op2[1]), .B2(n_0_78), .ZN(n_0_75) + ); + NOR2_X1_LVT i_0_78( + .A1(n_0_562), .A2(n_0_75), .ZN(n_0_74) + ); + NAND2_X1_LVT i_10_20( + .A1(n_10_15), .A2(n_10_16), .ZN(n_10_17) + ); + XNOR2_X1_LVT i_10_21( + .A(n_10_13), .B(n_10_17), .ZN(n_35) + ); + AOI22_X1_LVT i_0_75( + .A1(n_35), .A2(n_0_580), .B1(n_3), .B2(n_0_581), .ZN(n_0_71) + ); + OAI21_X1_LVT i_0_74( + .A(n_0_681), .B1(n_0_723), .B2(n_0_566), .ZN(n_0_70) + ); + AOI222_X1_LVT i_0_73( + .A1(n_0_654), .A2(n_0_569), .B1(n_0_663), .B2(n_0_564), .C1(op1[3]), .C2(n_0_70), + .ZN(n_0_69) + ); + INV_X1_LVT i_0_736( + .A(op1[0]), .ZN(n_0_703) + ); + OAI22_X1_LVT i_0_77( + .A1(n_0_703), .A2(n_0_531), .B1(n_0_694), .B2(n_0_572), .ZN(n_0_73) + ); + OAI22_X1_LVT i_0_76( + .A1(n_0_701), .A2(n_0_73), .B1(op2[0]), .B2(n_0_82), .ZN(n_0_72) + ); + OAI211_X1_LVT i_0_72( + .A(n_0_71), .B(n_0_69), .C1(n_0_621), .C2(n_0_72), .ZN(n_0_68) + ); + AOI211_X1_LVT i_0_71( + .A(n_0_74), .B(n_0_68), .C1(n_0_547), .C2(n_0_86), .ZN(n_0_67) + ); + INV_X1_LVT i_0_70( + .A(n_0_67), .ZN(result[3]) + ); + NAND2_X1_LVT i_0_65( + .A1(n_2), .A2(n_0_581), .ZN(n_0_62) + ); + OAI221_X1_LVT i_0_66( + .A(op2[2]), .B1(op1[2]), .B2(n_0_564), .C1(n_0_694), .C2(n_0_567), .ZN(n_0_63) + ); + AOI21_X1_LVT i_0_64( + .A(aluBypass), .B1(n_0_693), .B2(n_0_569), .ZN(n_0_61) + ); + OAI21_X1_LVT i_0_63( + .A(n_0_63), .B1(n_0_694), .B2(n_0_61), .ZN(n_0_60) + ); + INV_X1_LVT i_10_13( + .A(n_10_10), .ZN(n_10_11) + ); + NOR2_X1_LVT i_10_14( + .A1(n_10_9), .A2(n_10_11), .ZN(n_10_12) + ); + XNOR2_X1_LVT i_10_15( + .A(n_10_7), .B(n_10_12), .ZN(n_34) + ); + AOI21_X1_LVT i_0_62( + .A(n_0_60), .B1(n_34), .B2(n_0_580), .ZN(n_0_59) + ); + OAI211_X1_LVT i_0_57( + .A(n_0_62), .B(n_0_59), .C1(n_0_548), .C2(n_0_75), .ZN(n_0_54) + ); + NOR2_X1_LVT i_0_698( + .A1(n_0_729), .A2(op2[1]), .ZN(n_0_665) + ); + INV_X1_LVT i_0_697( + .A(n_0_665), .ZN(n_0_664) + ); + OAI21_X1_LVT i_0_69( + .A(op2[0]), .B1(n_0_664), .B2(n_0_574), .ZN(n_0_66) + ); + OAI21_X1_LVT i_0_68( + .A(n_0_620), .B1(op2[0]), .B2(n_0_73), .ZN(n_0_65) + ); + INV_X1_LVT i_0_67( + .A(n_0_65), .ZN(n_0_64) + ); + OAI222_X1_LVT i_0_61( + .A1(op1[10]), .A2(n_0_617), .B1(op1[2]), .B2(n_0_615), .C1(n_0_738), .C2(n_0_332), + .ZN(n_0_58) + ); + OAI22_X1_LVT i_0_60( + .A1(op2[2]), .A2(n_0_58), .B1(n_0_693), .B2(n_0_124), .ZN(n_0_57) + ); + INV_X1_LVT i_0_59( + .A(n_0_57), .ZN(n_0_56) + ); + AOI22_X1_LVT i_0_58( + .A1(n_0_728), .A2(n_0_56), .B1(n_0_87), .B2(n_0_77), .ZN(n_0_55) + ); + AOI221_X1_LVT i_0_56( + .A(n_0_54), .B1(n_0_66), .B2(n_0_64), .C1(n_0_561), .C2(n_0_55), .ZN(n_0_53) + ); + INV_X1_LVT i_0_55( + .A(n_0_53), .ZN(result[2]) + ); + NAND2_X1_LVT i_0_54( + .A1(n_0_547), .A2(n_0_55), .ZN(n_0_52) + ); + AOI221_X1_LVT i_0_47( + .A(n_0_728), .B1(n_0_729), .B2(n_0_565), .C1(op1[1]), .C2(n_0_566), .ZN(n_0_45) + ); + NOR2_X1_LVT i_0_700( + .A1(op1[0]), .A2(n_0_701), .ZN(n_0_667) + ); + AOI211_X1_LVT i_0_48( + .A(n_0_667), .B(n_0_621), .C1(n_0_729), .C2(n_0_701), .ZN(n_0_46) + ); + AOI221_X1_LVT i_0_44( + .A(n_0_45), .B1(op1[1]), .B2(aluBypass), .C1(n_0_571), .C2(n_0_46), .ZN(n_0_42) + ); + NAND2_X1_LVT i_10_6( + .A1(n_10_3), .A2(n_10_4), .ZN(n_10_5) + ); + XNOR2_X1_LVT i_10_7( + .A(n_10_5), .B(n_10_1), .ZN(n_33) + ); + AOI22_X1_LVT i_0_49( + .A1(n_33), .A2(n_0_580), .B1(n_1), .B2(n_0_581), .ZN(n_0_47) + ); + OAI21_X1_LVT i_0_46( + .A(n_0_47), .B1(n_0_664), .B2(n_0_568), .ZN(n_0_44) + ); + NAND2_X1_LVT i_0_51( + .A1(op2[1]), .A2(n_0_78), .ZN(n_0_49) + ); + OAI222_X1_LVT i_0_53( + .A1(n_0_722), .A2(n_0_617), .B1(n_0_729), .B2(n_0_615), .C1(n_0_738), .C2(n_0_313), + .ZN(n_0_51) + ); + OAI22_X1_LVT i_0_52( + .A1(n_0_223), .A2(n_0_103), .B1(op2[2]), .B2(n_0_51), .ZN(n_0_50) + ); + OAI21_X1_LVT i_0_50( + .A(n_0_49), .B1(op2[1]), .B2(n_0_50), .ZN(n_0_48) + ); + AOI21_X1_LVT i_0_45( + .A(n_0_44), .B1(n_0_561), .B2(n_0_48), .ZN(n_0_43) + ); + NAND3_X1_LVT i_0_43( + .A1(n_0_52), .A2(n_0_42), .A3(n_0_43), .ZN(result[1]) + ); + OAI222_X1_LVT i_0_11( + .A1(n_0_740), .A2(n_0_617), .B1(n_0_703), .B2(n_0_615), .C1(n_0_738), .C2(n_0_290), + .ZN(n_0_10) + ); + OAI22_X1_LVT i_0_10( + .A1(op2[2]), .A2(n_0_10), .B1(n_0_693), .B2(n_0_88), .ZN(n_0_9) + ); + OAI221_X1_LVT i_0_9( + .A(n_0_701), .B1(n_0_728), .B2(n_0_56), .C1(op2[1]), .C2(n_0_9), .ZN(n_0_8) + ); + OAI21_X1_LVT i_0_8( + .A(n_0_8), .B1(n_0_701), .B2(n_0_48), .ZN(n_0_7) + ); + NOR2_X1_LVT i_0_7( + .A1(n_0_579), .A2(n_0_7), .ZN(n_0_6) + ); + OAI221_X1_LVT i_0_3( + .A(op2[0]), .B1(op1[0]), .B2(n_0_564), .C1(n_0_703), .C2(n_0_567), .ZN(n_0_2) + ); + OAI21_X1_LVT i_10_2( + .A(n_10_1), .B1(n_10_0), .B2(op2[0]), .ZN(n_32) + ); + AOI22_X1_LVT i_0_2( + .A1(n_32), .A2(n_0_580), .B1(n_0), .B2(n_0_581), .ZN(n_0_1) + ); + NAND3_X1_LVT i_0_6( + .A1(n_0_701), .A2(n_0_571), .A3(n_0_620), .ZN(n_0_5) + ); + OAI211_X1_LVT i_0_5( + .A(n_0_681), .B(n_0_5), .C1(op2[0]), .C2(n_0_568), .ZN(n_0_4) + ); + NAND2_X1_LVT i_0_4( + .A1(op1[0]), .A2(n_0_4), .ZN(n_0_3) + ); + NAND3_X1_LVT i_0_1( + .A1(n_0_2), .A2(n_0_1), .A3(n_0_3), .ZN(n_0_0) + ); + OAI33_X1_LVT i_0_14( + .A1(n_0_692), .A2(op1[31]), .A3(n_0_683), .B1(op2[31]), .B2(n_0_691), .B3(aluOp[0]), + .ZN(n_0_13) + ); + INV_X1_LVT i_0_741( + .A(op2[29]), .ZN(n_0_708) + ); + NAND2_X1_LVT i_0_685( + .A1(op1[29]), .A2(n_0_708), .ZN(n_0_652) + ); + OAI22_X1_LVT i_0_713( + .A1(n_0_700), .A2(op1[28]), .B1(op1[29]), .B2(n_0_708), .ZN(n_0_680) + ); + NAND2_X1_LVT i_0_694( + .A1(n_0_688), .A2(op2[27]), .ZN(n_0_661) + ); + INV_X1_LVT i_0_742( + .A(op2[26]), .ZN(n_0_709) + ); + OAI22_X1_LVT i_0_712( + .A1(n_0_699), .A2(op2[25]), .B1(n_0_736), .B2(op2[24]), .ZN(n_0_679) + ); + NAND2_X1_LVT i_0_690( + .A1(n_0_727), .A2(op2[20]), .ZN(n_0_657) + ); + INV_X1_LVT i_0_740( + .A(op2[18]), .ZN(n_0_707) + ); + OAI22_X1_LVT i_0_711( + .A1(n_0_707), .A2(op1[18]), .B1(n_0_690), .B2(op1[19]), .ZN(n_0_678) + ); + OAI22_X1_LVT i_0_29( + .A1(n_0_739), .A2(op2[16]), .B1(n_0_734), .B2(op2[15]), .ZN(n_0_28) + ); + INV_X1_LVT i_0_728( + .A(op2[12]), .ZN(n_0_695) + ); + INV_X1_LVT i_0_748( + .A(op2[13]), .ZN(n_0_715) + ); + OAI22_X1_LVT i_0_704( + .A1(n_0_706), .A2(op2[11]), .B1(n_0_696), .B2(op2[12]), .ZN(n_0_671) + ); + AOI22_X1_LVT i_0_710( + .A1(n_0_740), .A2(op2[8]), .B1(n_0_713), .B2(op2[7]), .ZN(n_0_677) + ); + OAI22_X1_LVT i_0_707( + .A1(n_0_731), .A2(op1[5]), .B1(op1[6]), .B2(n_0_702), .ZN(n_0_674) + ); + OAI22_X1_LVT i_0_706( + .A1(op1[2]), .A2(n_0_693), .B1(op1[1]), .B2(n_0_728), .ZN(n_0_673) + ); + INV_X1_LVT i_0_705( + .A(n_0_673), .ZN(n_0_672) + ); + INV_X1_LVT i_0_699( + .A(n_0_667), .ZN(n_0_666) + ); + OAI21_X1_LVT i_0_42( + .A(n_0_672), .B1(n_0_666), .B2(n_0_665), .ZN(n_0_41) + ); + AOI21_X1_LVT i_0_41( + .A(n_0_654), .B1(op1[2]), .B2(n_0_693), .ZN(n_0_40) + ); + AOI211_X1_LVT i_0_40( + .A(n_0_668), .B(n_0_663), .C1(n_0_41), .C2(n_0_40), .ZN(n_0_39) + ); + AOI211_X1_LVT i_0_39( + .A(n_0_656), .B(n_0_39), .C1(n_0_731), .C2(op1[5]), .ZN(n_0_38) + ); + OAI222_X1_LVT i_0_38( + .A1(n_0_704), .A2(op2[6]), .B1(n_0_674), .B2(n_0_38), .C1(n_0_713), .C2(op2[7]), + .ZN(n_0_37) + ); + AOI221_X1_LVT i_0_37( + .A(n_0_655), .B1(op1[9]), .B2(n_0_720), .C1(n_0_677), .C2(n_0_37), .ZN(n_0_36) + ); + INV_X1_LVT i_0_768( + .A(op2[10]), .ZN(n_0_735) + ); + OAI22_X1_LVT i_0_36( + .A1(n_0_735), .A2(op1[10]), .B1(op1[9]), .B2(n_0_720), .ZN(n_0_35) + ); + OAI22_X1_LVT i_0_35( + .A1(op2[10]), .A2(n_0_733), .B1(n_0_36), .B2(n_0_35), .ZN(n_0_34) + ); + INV_X1_LVT i_0_34( + .A(n_0_34), .ZN(n_0_33) + ); + AOI21_X1_LVT i_0_33( + .A(n_0_33), .B1(n_0_706), .B2(op2[11]), .ZN(n_0_32) + ); + OAI222_X1_LVT i_0_32( + .A1(op1[12]), .A2(n_0_695), .B1(n_0_715), .B2(op1[13]), .C1(n_0_671), .C2(n_0_32), + .ZN(n_0_31) + ); + OAI221_X1_LVT i_0_31( + .A(n_0_31), .B1(n_0_721), .B2(op2[14]), .C1(op2[13]), .C2(n_0_714), .ZN(n_0_30) + ); + AOI22_X1_LVT i_0_30( + .A1(n_0_734), .A2(op2[15]), .B1(n_0_721), .B2(op2[14]), .ZN(n_0_29) + ); + AOI21_X1_LVT i_0_28( + .A(n_0_28), .B1(n_0_30), .B2(n_0_29), .ZN(n_0_27) + ); + AOI221_X1_LVT i_0_27( + .A(n_0_27), .B1(n_0_732), .B2(op2[17]), .C1(n_0_739), .C2(op2[16]), .ZN(n_0_26) + ); + AOI211_X1_LVT i_0_26( + .A(n_0_660), .B(n_0_26), .C1(n_0_707), .C2(op1[18]), .ZN(n_0_25) + ); + OAI22_X1_LVT i_0_25( + .A1(op2[19]), .A2(n_0_689), .B1(n_0_678), .B2(n_0_25), .ZN(n_0_24) + ); + AOI211_X1_LVT i_0_24( + .A(n_0_658), .B(n_0_659), .C1(n_0_657), .C2(n_0_24), .ZN(n_0_23) + ); + AOI221_X1_LVT i_0_23( + .A(n_0_23), .B1(n_0_726), .B2(op2[21]), .C1(n_0_687), .C2(op2[22]), .ZN(n_0_22) + ); + AOI221_X1_LVT i_0_22( + .A(n_0_22), .B1(op1[22]), .B2(n_0_686), .C1(op1[23]), .C2(n_0_718), .ZN(n_0_21) + ); + AOI221_X1_LVT i_0_21( + .A(n_0_21), .B1(n_0_736), .B2(op2[24]), .C1(n_0_719), .C2(op2[23]), .ZN(n_0_20) + ); + OAI222_X1_LVT i_0_20( + .A1(op1[26]), .A2(n_0_709), .B1(op1[25]), .B2(n_0_697), .C1(n_0_679), .C2(n_0_20), + .ZN(n_0_19) + ); + OAI221_X1_LVT i_0_19( + .A(n_0_19), .B1(n_0_711), .B2(op2[26]), .C1(n_0_688), .C2(op2[27]), .ZN(n_0_18) + ); + AOI22_X1_LVT i_0_18( + .A1(n_0_700), .A2(op1[28]), .B1(n_0_661), .B2(n_0_18), .ZN(n_0_17) + ); + OAI21_X1_LVT i_0_17( + .A(n_0_652), .B1(n_0_680), .B2(n_0_17), .ZN(n_0_16) + ); + INV_X1_LVT i_0_749( + .A(op2[30]), .ZN(n_0_716) + ); + OAI21_X1_LVT i_0_16( + .A(n_0_16), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_15) + ); + OAI22_X1_LVT i_0_708( + .A1(n_0_692), .A2(op1[31]), .B1(op2[31]), .B2(n_0_691), .ZN(n_0_675) + ); + AOI21_X1_LVT i_0_15( + .A(n_0_675), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_14) + ); + AOI21_X1_LVT i_0_13( + .A(n_0_13), .B1(n_0_15), .B2(n_0_14), .ZN(n_0_12) + ); + NOR4_X1_LVT i_0_12( + .A1(n_0_685), .A2(aluOp[2]), .A3(aluBypass), .A4(n_0_12), .ZN(n_0_11) + ); + OR3_X1_LVT i_0_0( + .A1(n_0_6), .A2(n_0_0), .A3(n_0_11), .ZN(result[0]) + ); + OR4_X1_LVT i_0_703( + .A1(n_0_680), .A2(n_0_673), .A3(n_0_675), .A4(n_0_678), .ZN(n_0_670) + ); + INV_X1_LVT i_0_709( + .A(n_0_677), .ZN(n_0_676) + ); + OR4_X1_LVT i_0_702( + .A1(n_0_679), .A2(n_0_674), .A3(n_0_676), .A4(n_0_671), .ZN(n_0_669) + ); + AOI22_X1_LVT i_0_663( + .A1(n_0_688), .A2(op2[27]), .B1(op1[22]), .B2(n_0_686), .ZN(n_0_630) + ); + OAI22_X1_LVT i_0_662( + .A1(n_0_694), .A2(op2[2]), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_629) + ); + AOI221_X1_LVT i_0_661( + .A(n_0_629), .B1(n_0_711), .B2(op2[26]), .C1(n_0_721), .C2(op2[14]), .ZN(n_0_628) + ); + AOI21_X1_LVT i_0_664( + .A(n_0_660), .B1(n_0_690), .B2(op1[19]), .ZN(n_0_631) + ); + OAI222_X1_LVT i_0_660( + .A1(op1[12]), .A2(n_0_695), .B1(n_0_688), .B2(op2[27]), .C1(op1[22]), .C2(n_0_686), + .ZN(n_0_627) + ); + AOI21_X1_LVT i_0_659( + .A(n_0_663), .B1(n_0_734), .B2(op2[15]), .ZN(n_0_626) + ); + OAI211_X1_LVT i_0_658( + .A(n_0_666), .B(n_0_626), .C1(n_0_715), .C2(op1[13]), .ZN(n_0_625) + ); + AOI211_X1_LVT i_0_657( + .A(n_0_627), .B(n_0_625), .C1(op1[23]), .C2(n_0_718), .ZN(n_0_624) + ); + NAND4_X1_LVT i_0_656( + .A1(n_0_630), .A2(n_0_628), .A3(n_0_631), .A4(n_0_624), .ZN(n_0_623) + ); + OAI22_X1_LVT i_0_684( + .A1(n_0_721), .A2(op2[14]), .B1(n_0_722), .B2(op2[9]), .ZN(n_0_651) + ); + AOI211_X1_LVT i_0_668( + .A(n_0_651), .B(n_0_654), .C1(n_0_719), .C2(op2[23]), .ZN(n_0_635) + ); + NAND2_X1_LVT i_0_667( + .A1(n_0_664), .A2(n_0_657), .ZN(n_0_634) + ); + NOR3_X1_LVT i_0_666( + .A1(n_0_659), .A2(n_0_656), .A3(n_0_634), .ZN(n_0_633) + ); + AOI21_X1_LVT i_0_671( + .A(n_0_655), .B1(n_0_739), .B2(op2[16]), .ZN(n_0_638) + ); + AOI21_X1_LVT i_0_670( + .A(n_0_668), .B1(n_0_736), .B2(op2[24]), .ZN(n_0_637) + ); + OAI22_X1_LVT i_0_673( + .A1(n_0_735), .A2(op1[10]), .B1(n_0_734), .B2(op2[15]), .ZN(n_0_640) + ); + AOI221_X1_LVT i_0_672( + .A(n_0_640), .B1(n_0_732), .B2(op2[17]), .C1(n_0_731), .C2(op1[5]), .ZN(n_0_639) + ); + AND3_X1_LVT i_0_669( + .A1(n_0_638), .A2(n_0_637), .A3(n_0_639), .ZN(n_0_636) + ); + OAI22_X1_LVT i_0_682( + .A1(n_0_703), .A2(op2[0]), .B1(n_0_704), .B2(op2[6]), .ZN(n_0_649) + ); + OAI22_X1_LVT i_0_681( + .A1(op2[28]), .A2(n_0_698), .B1(op1[25]), .B2(n_0_697), .ZN(n_0_648) + ); + AOI21_X1_LVT i_0_678( + .A(n_0_658), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_645) + ); + AOI21_X1_LVT i_0_677( + .A(n_0_662), .B1(n_0_735), .B2(op1[10]), .ZN(n_0_644) + ); + INV_X1_LVT i_0_758( + .A(op2[21]), .ZN(n_0_725) + ); + OAI22_X1_LVT i_0_683( + .A1(op1[21]), .A2(n_0_725), .B1(n_0_739), .B2(op2[16]), .ZN(n_0_650) + ); + AOI221_X1_LVT i_0_676( + .A(n_0_650), .B1(n_0_722), .B2(op2[9]), .C1(op1[7]), .C2(n_0_712), .ZN(n_0_643) + ); + OAI21_X1_LVT i_0_680( + .A(n_0_652), .B1(n_0_711), .B2(op2[26]), .ZN(n_0_647) + ); + AOI221_X1_LVT i_0_679( + .A(n_0_647), .B1(n_0_706), .B2(op2[11]), .C1(n_0_707), .C2(op1[18]), .ZN(n_0_646) + ); + NAND4_X1_LVT i_0_675( + .A1(n_0_645), .A2(n_0_644), .A3(n_0_643), .A4(n_0_646), .ZN(n_0_642) + ); + NOR3_X1_LVT i_0_674( + .A1(n_0_649), .A2(n_0_648), .A3(n_0_642), .ZN(n_0_641) + ); + NAND4_X1_LVT i_0_665( + .A1(n_0_635), .A2(n_0_633), .A3(n_0_636), .A4(n_0_641), .ZN(n_0_632) + ); + NOR4_X1_LVT i_0_655( + .A1(n_0_670), .A2(n_0_669), .A3(n_0_623), .A4(n_0_632), .ZN(eqFlag) + ); +endmodule + +module decoder(CurrentPC, JumpOrBranchPC, JumpOrBranch, DAddr, WData, RData, Instruction, + WrMem, DWidth, Rs1, Rs2, Rd, RRs1, RRs2, WRd, WrReg, Illegal); + input [31:0] CurrentPC, RData, Instruction, RRs1, RRs2; + output [31:0] JumpOrBranchPC, DAddr, WData, WRd; + output [4:0] Rs1, Rs2, Rd; + output [1:0] DWidth; + output JumpOrBranch, WrMem, WrReg, Illegal; + + wire [31:0] op1, op2; + wire [2:0] aluOp; + wire eqFlag, n_5_0, n_5_1, n_5_2, n_5_3, n_5_4, n_5_5, n_5_6, n_5_7, n_5_8, + n_5_9, n_5_10, n_5_11, n_5_12, n_5_13, n_5_14, n_5_15, n_5_16, n_5_17, + n_5_18, n_5_19, n_5_20, n_5_21, n_5_22, n_5_23, n_5_24, n_5_25, n_5_26, + n_5_27, n_5_28, n_5_29, n_5_30, n_5_31, n_5_32, n_5_33, n_17_0, n_17_1, + n_17_2, n_17_3, n_17_4, n_17_5, n_17_6, n_17_7, n_17_8, n_17_9, n_17_10, + n_17_11, n_17_12, n_17_13, n_17_14, n_17_15, n_17_16, n_17_17, n_17_18, + n_17_19, n_17_20, n_17_21, n_17_22, n_17_23, n_17_24, n_17_25, n_17_26, + n_17_27, n_17_28, n_17_29, n_17_30, n_17_31, n_17_32, n_18_0, n_18_1, + n_18_2, n_18_3, n_18_4, n_18_5, n_18_6, n_18_7, n_18_8, n_18_9, n_18_10, + n_18_11, n_18_12, n_18_13, n_18_14, n_18_15, n_18_16, n_18_17, n_18_18, + n_18_19, n_18_20, n_18_21, n_18_22, n_18_23, n_18_24, n_18_25, n_18_26, + n_18_27, n_18_28, n_18_29, n_18_30, n_18_31, n_18_32, n_0_15, n_0_2, + n_0_16, n_0_3, n_0_17, n_0_4, n_0_18, n_0_5, n_0_19, n_0_6, n_0_20, + n_0_7, n_0_21, n_0_8, n_0_22, n_0_9, n_0_23, n_0_10, n_0_24, n_0_11, + n_0_25, n_0_12, n_0_26, n_0_13, n_0_27, n_0_14, n_0_28, n_0_29, n_0_30, + n_0_31, n_0_32, n_0_33, n_0_34, n_0_35, n_0_36, n_0_37, n_0_38, n_0_39, + n_0_40, n_0_41, n_0_42, n_0_43, n_0_44, n_0_45, n_0_46, n_0_47, n_0_48, + n_0_49, n_0_50, n_0_51, n_0_52, n_0_53, n_0_54, n_0_55, n_0_56, n_0_57, + n_0_58, n_0_59, n_0_60, n_0_61, n_0_62, n_0_63, n_0_64, n_0_65, n_0_66, + n_0_67, n_0_68, n_0_69, n_0_70, n_0_71, n_0_72, n_0_73, n_0_74, n_0_75, + n_0_76, n_0_77, n_0_78, n_0_79, n_0_80, n_0_81, n_0_82, n_0_83, n_0_84, + n_0_85, n_0_86, n_0_87, n_0_88, n_0_89, n_0_90, n_0_91, n_0_92, n_0_93, + n_0_94, n_0_95, n_0_96, n_0_97, n_0_98, n_0_99, n_0_100, aluNegAr, + n_0_101, n_0_102, n_0_103, n_0_104, n_0_105, aluBypass, n_0_106, + n_0_107, n_0_108, n_0_109, n_0_110, n_0_111, n_0_112, n_0_113, n_0_114, + n_0_115, n_0_116, n_0_117, n_0_118, n_0_119, n_0_120, n_0_121, n_0_122, + n_0_123, n_0_124, n_0_125, n_0_126, n_0_127, n_0_128, n_0_129, n_0_130, + n_0_131, n_0_132, n_0_133, n_0_134, n_0_135, n_0_136, n_0_137, n_0_138, + n_0_139, n_0_140, n_0_141, n_0_142, n_0_143, n_0_144, n_0_145, n_0_146, + n_0_147, n_0_148, n_0_149, n_0_150, n_0_151, n_0_152, n_0_153, n_0_154, + n_0_155, n_0_156, n_0_157, n_0_158, n_0_159, n_0_160, n_0_161, n_0_162, + n_0_163, n_0_164, n_0_165, n_0_166, n_0_167, n_0_168, n_0_169, n_0_170, + n_0_171, n_0_172, n_0_173, n_0_174, n_0_175, n_0_176, n_0_177, n_0_178, + n_0_179, n_0_180, n_0_181, n_0_182, n_0_183, n_0_184, n_0_185, n_0_186, + n_0_187, n_0_188, n_0_189, n_0_190, n_0_191, n_0_192, n_0_193, n_0_194, + n_0_195, n_0_196, n_0_197, n_0_198, n_0_199, n_0_200, n_0_201, n_0_202, + n_0_203, n_0_204, n_0_205, n_0_206, n_0_207, n_0_208, n_0_209, n_0_210, + n_0_211, n_0_212, n_0_213, n_0_214, n_0_215, n_0_216, n_0_217, n_0_218, + n_0_219, n_0_220, n_0_221, n_0_222, n_0_223, n_0_224, n_0_225, n_0_226, + n_0_227, n_0_228, n_0_229, n_0_230, n_0_231, n_0_232, n_0_233, n_0_234, + n_0_235, n_0_236, n_0_237, n_0_238, n_0_239, n_0_240, n_0_241, n_0_242, + n_0_1, n_0_0, n_0_243, n_0_244, n_0_245, n_0_246, n_0_247, n_0_248, + n_0_249, n_63, n_64, n_65, n_66, n_67, n_68, n_69, n_70, n_71, n_72, + n_73, n_74, n_75, n_76, n_77, n_78, n_79, n_80, n_81, n_82, n_83, n_84, + n_85, n_86, n_87, n_88, n_89, n_90, n_91, n_92, n_93, n_32, n_33, n_34, + n_35, n_36, n_37, n_38, n_39, n_40, n_41, n_42, n_43, n_44, n_45, n_46, + n_47, n_48, n_49, n_50, n_51, n_52, n_53, n_54, n_55, n_56, n_57, n_58, + n_59, n_60, n_61, n_62, n_0, n_1, n_2, n_3, n_4, n_5, n_6, n_7, n_8, + n_9, n_10, n_11, n_12, n_13, n_14, n_15, n_16, n_17, n_18, n_19, n_20, + n_21, n_22, n_23, n_24, n_25, n_26, n_27, n_28, n_29, n_30, n_31; + + INV_X1_LVT i_18_1( + .A(CurrentPC[13]), .ZN(n_18_1) + ); + XNOR2_X1_LVT i_18_32( + .A(CurrentPC[31]), .B(n_18_1), .ZN(n_18_32) + ); + INV_X1_LVT i_18_0( + .A(Instruction[31]), .ZN(n_18_0) + ); + HA_X1_LVT i_18_2( + .A(Instruction[8]), .B(CurrentPC[1]), .CO(n_18_2), .S(n_63) + ); + FA_X1_LVT i_18_3( + .A(Instruction[9]), .B(CurrentPC[2]), .CI(n_18_2), .CO(n_18_3), .S(n_64) + ); + FA_X1_LVT i_18_4( + .A(Instruction[10]), .B(CurrentPC[3]), .CI(n_18_3), .CO(n_18_4), .S(n_65) + ); + FA_X1_LVT i_18_5( + .A(Instruction[11]), .B(CurrentPC[4]), .CI(n_18_4), .CO(n_18_5), .S(n_66) + ); + FA_X1_LVT i_18_6( + .A(Instruction[25]), .B(CurrentPC[5]), .CI(n_18_5), .CO(n_18_6), .S(n_67) + ); + FA_X1_LVT i_18_7( + .A(Instruction[26]), .B(CurrentPC[6]), .CI(n_18_6), .CO(n_18_7), .S(n_68) + ); + FA_X1_LVT i_18_8( + .A(Instruction[27]), .B(CurrentPC[7]), .CI(n_18_7), .CO(n_18_8), .S(n_69) + ); + FA_X1_LVT i_18_9( + .A(Instruction[28]), .B(CurrentPC[8]), .CI(n_18_8), .CO(n_18_9), .S(n_70) + ); + FA_X1_LVT i_18_10( + .A(Instruction[29]), .B(CurrentPC[9]), .CI(n_18_9), .CO(n_18_10), .S(n_71) + ); + FA_X1_LVT i_18_11( + .A(Instruction[30]), .B(CurrentPC[10]), .CI(n_18_10), .CO(n_18_11), .S(n_72) + ); + FA_X1_LVT i_18_12( + .A(Instruction[7]), .B(CurrentPC[11]), .CI(n_18_11), .CO(n_18_12), .S(n_73) + ); + FA_X1_LVT i_18_13( + .A(CurrentPC[12]), .B(Instruction[31]), .CI(n_18_12), .CO(n_18_13), .S(n_74) + ); + FA_X1_LVT i_18_14( + .A(n_18_0), .B(n_18_1), .CI(n_18_13), .CO(n_18_14), .S(n_75) + ); + FA_X1_LVT i_18_15( + .A(CurrentPC[14]), .B(n_18_1), .CI(n_18_14), .CO(n_18_15), .S(n_76) + ); + FA_X1_LVT i_18_16( + .A(CurrentPC[15]), .B(n_18_1), .CI(n_18_15), .CO(n_18_16), .S(n_77) + ); + FA_X1_LVT i_18_17( + .A(CurrentPC[16]), .B(n_18_1), .CI(n_18_16), .CO(n_18_17), .S(n_78) + ); + FA_X1_LVT i_18_18( + .A(CurrentPC[17]), .B(n_18_1), .CI(n_18_17), .CO(n_18_18), .S(n_79) + ); + FA_X1_LVT i_18_19( + .A(CurrentPC[18]), .B(n_18_1), .CI(n_18_18), .CO(n_18_19), .S(n_80) + ); + FA_X1_LVT i_18_20( + .A(CurrentPC[19]), .B(n_18_1), .CI(n_18_19), .CO(n_18_20), .S(n_81) + ); + FA_X1_LVT i_18_21( + .A(CurrentPC[20]), .B(n_18_1), .CI(n_18_20), .CO(n_18_21), .S(n_82) + ); + FA_X1_LVT i_18_22( + .A(CurrentPC[21]), .B(n_18_1), .CI(n_18_21), .CO(n_18_22), .S(n_83) + ); + FA_X1_LVT i_18_23( + .A(CurrentPC[22]), .B(n_18_1), .CI(n_18_22), .CO(n_18_23), .S(n_84) + ); + FA_X1_LVT i_18_24( + .A(CurrentPC[23]), .B(n_18_1), .CI(n_18_23), .CO(n_18_24), .S(n_85) + ); + FA_X1_LVT i_18_25( + .A(CurrentPC[24]), .B(n_18_1), .CI(n_18_24), .CO(n_18_25), .S(n_86) + ); + FA_X1_LVT i_18_26( + .A(CurrentPC[25]), .B(n_18_1), .CI(n_18_25), .CO(n_18_26), .S(n_87) + ); + FA_X1_LVT i_18_27( + .A(CurrentPC[26]), .B(n_18_1), .CI(n_18_26), .CO(n_18_27), .S(n_88) + ); + FA_X1_LVT i_18_28( + .A(CurrentPC[27]), .B(n_18_1), .CI(n_18_27), .CO(n_18_28), .S(n_89) + ); + FA_X1_LVT i_18_29( + .A(CurrentPC[28]), .B(n_18_1), .CI(n_18_28), .CO(n_18_29), .S(n_90) + ); + FA_X1_LVT i_18_30( + .A(CurrentPC[29]), .B(n_18_1), .CI(n_18_29), .CO(n_18_30), .S(n_91) + ); + FA_X1_LVT i_18_31( + .A(CurrentPC[30]), .B(n_18_1), .CI(n_18_30), .CO(n_18_31), .S(n_92) + ); + XNOR2_X1_LVT i_18_33( + .A(n_18_32), .B(n_18_31), .ZN(n_93) + ); + INV_X1_LVT i_0_350( + .A(Instruction[3]), .ZN(n_0_243) + ); + NAND3_X1_LVT i_0_343( + .A1(n_0_243), .A2(Instruction[0]), .A3(Instruction[1]), .ZN(n_0_238) + ); + OR2_X1_LVT i_0_332( + .A1(n_0_238), .A2(Instruction[2]), .ZN(n_0_228) + ); + INV_X1_LVT i_0_351( + .A(Instruction[5]), .ZN(n_0_244) + ); + NOR2_X1_LVT i_0_340( + .A1(n_0_244), .A2(Instruction[4]), .ZN(n_0_235) + ); + NAND2_X1_LVT i_0_329( + .A1(Instruction[6]), .A2(n_0_235), .ZN(n_0_225) + ); + INV_X1_LVT i_0_354( + .A(Instruction[13]), .ZN(n_0_247) + ); + NOR2_X1_LVT i_0_345( + .A1(n_0_247), .A2(Instruction[14]), .ZN(n_0_240) + ); + NOR3_X1_LVT i_0_118( + .A1(n_0_228), .A2(n_0_225), .A3(n_0_240), .ZN(n_0_99) + ); + NAND3_X1_LVT i_0_346( + .A1(Instruction[0]), .A2(Instruction[1]), .A3(Instruction[2]), .ZN(n_0_241) + ); + NOR2_X1_LVT i_0_328( + .A1(n_0_241), .A2(n_0_225), .ZN(n_0_224) + ); + INV_X1_LVT i_0_356( + .A(n_0_224), .ZN(n_0_249) + ); + NOR2_X1_LVT i_0_108( + .A1(n_0_243), .A2(n_0_249), .ZN(n_0_91) + ); + INV_X1_LVT i_17_1( + .A(CurrentPC[21]), .ZN(n_17_1) + ); + XNOR2_X1_LVT i_17_32( + .A(CurrentPC[31]), .B(n_17_1), .ZN(n_17_32) + ); + INV_X1_LVT i_17_0( + .A(Instruction[31]), .ZN(n_17_0) + ); + HA_X1_LVT i_17_2( + .A(Instruction[21]), .B(CurrentPC[1]), .CO(n_17_2), .S(n_32) + ); + FA_X1_LVT i_17_3( + .A(Instruction[22]), .B(CurrentPC[2]), .CI(n_17_2), .CO(n_17_3), .S(n_33) + ); + FA_X1_LVT i_17_4( + .A(Instruction[23]), .B(CurrentPC[3]), .CI(n_17_3), .CO(n_17_4), .S(n_34) + ); + FA_X1_LVT i_17_5( + .A(Instruction[24]), .B(CurrentPC[4]), .CI(n_17_4), .CO(n_17_5), .S(n_35) + ); + FA_X1_LVT i_17_6( + .A(Instruction[25]), .B(CurrentPC[5]), .CI(n_17_5), .CO(n_17_6), .S(n_36) + ); + FA_X1_LVT i_17_7( + .A(Instruction[26]), .B(CurrentPC[6]), .CI(n_17_6), .CO(n_17_7), .S(n_37) + ); + FA_X1_LVT i_17_8( + .A(Instruction[27]), .B(CurrentPC[7]), .CI(n_17_7), .CO(n_17_8), .S(n_38) + ); + FA_X1_LVT i_17_9( + .A(Instruction[28]), .B(CurrentPC[8]), .CI(n_17_8), .CO(n_17_9), .S(n_39) + ); + FA_X1_LVT i_17_10( + .A(Instruction[29]), .B(CurrentPC[9]), .CI(n_17_9), .CO(n_17_10), .S(n_40) + ); + FA_X1_LVT i_17_11( + .A(Instruction[30]), .B(CurrentPC[10]), .CI(n_17_10), .CO(n_17_11), .S(n_41) + ); + FA_X1_LVT i_17_12( + .A(Instruction[20]), .B(CurrentPC[11]), .CI(n_17_11), .CO(n_17_12), .S(n_42) + ); + FA_X1_LVT i_17_13( + .A(Instruction[12]), .B(CurrentPC[12]), .CI(n_17_12), .CO(n_17_13), .S(n_43) + ); + FA_X1_LVT i_17_14( + .A(Instruction[13]), .B(CurrentPC[13]), .CI(n_17_13), .CO(n_17_14), .S(n_44) + ); + FA_X1_LVT i_17_15( + .A(Instruction[14]), .B(CurrentPC[14]), .CI(n_17_14), .CO(n_17_15), .S(n_45) + ); + FA_X1_LVT i_17_16( + .A(Instruction[15]), .B(CurrentPC[15]), .CI(n_17_15), .CO(n_17_16), .S(n_46) + ); + FA_X1_LVT i_17_17( + .A(Instruction[16]), .B(CurrentPC[16]), .CI(n_17_16), .CO(n_17_17), .S(n_47) + ); + FA_X1_LVT i_17_18( + .A(Instruction[17]), .B(CurrentPC[17]), .CI(n_17_17), .CO(n_17_18), .S(n_48) + ); + FA_X1_LVT i_17_19( + .A(Instruction[18]), .B(CurrentPC[18]), .CI(n_17_18), .CO(n_17_19), .S(n_49) + ); + FA_X1_LVT i_17_20( + .A(Instruction[19]), .B(CurrentPC[19]), .CI(n_17_19), .CO(n_17_20), .S(n_50) + ); + FA_X1_LVT i_17_21( + .A(CurrentPC[20]), .B(Instruction[31]), .CI(n_17_20), .CO(n_17_21), .S(n_51) + ); + FA_X1_LVT i_17_22( + .A(n_17_0), .B(n_17_1), .CI(n_17_21), .CO(n_17_22), .S(n_52) + ); + FA_X1_LVT i_17_23( + .A(CurrentPC[22]), .B(n_17_1), .CI(n_17_22), .CO(n_17_23), .S(n_53) + ); + FA_X1_LVT i_17_24( + .A(CurrentPC[23]), .B(n_17_1), .CI(n_17_23), .CO(n_17_24), .S(n_54) + ); + FA_X1_LVT i_17_25( + .A(CurrentPC[24]), .B(n_17_1), .CI(n_17_24), .CO(n_17_25), .S(n_55) + ); + FA_X1_LVT i_17_26( + .A(CurrentPC[25]), .B(n_17_1), .CI(n_17_25), .CO(n_17_26), .S(n_56) + ); + FA_X1_LVT i_17_27( + .A(CurrentPC[26]), .B(n_17_1), .CI(n_17_26), .CO(n_17_27), .S(n_57) + ); + FA_X1_LVT i_17_28( + .A(CurrentPC[27]), .B(n_17_1), .CI(n_17_27), .CO(n_17_28), .S(n_58) + ); + FA_X1_LVT i_17_29( + .A(CurrentPC[28]), .B(n_17_1), .CI(n_17_28), .CO(n_17_29), .S(n_59) + ); + FA_X1_LVT i_17_30( + .A(CurrentPC[29]), .B(n_17_1), .CI(n_17_29), .CO(n_17_30), .S(n_60) + ); + FA_X1_LVT i_17_31( + .A(CurrentPC[30]), .B(n_17_1), .CI(n_17_30), .CO(n_17_31), .S(n_61) + ); + XNOR2_X1_LVT i_17_33( + .A(n_17_32), .B(n_17_31), .ZN(n_62) + ); + INV_X1_LVT i_5_1( + .A(RRs1[12]), .ZN(n_5_1) + ); + XNOR2_X1_LVT i_5_33( + .A(RRs1[31]), .B(n_5_1), .ZN(n_5_33) + ); + INV_X1_LVT i_5_0( + .A(Instruction[31]), .ZN(n_5_0) + ); + HA_X1_LVT i_5_2( + .A(Instruction[20]), .B(RRs1[0]), .CO(n_5_2), .S(n_0) + ); + FA_X1_LVT i_5_3( + .A(Instruction[21]), .B(RRs1[1]), .CI(n_5_2), .CO(n_5_3), .S(n_1) + ); + FA_X1_LVT i_5_4( + .A(Instruction[22]), .B(RRs1[2]), .CI(n_5_3), .CO(n_5_4), .S(n_2) + ); + FA_X1_LVT i_5_5( + .A(Instruction[23]), .B(RRs1[3]), .CI(n_5_4), .CO(n_5_5), .S(n_3) + ); + FA_X1_LVT i_5_6( + .A(Instruction[24]), .B(RRs1[4]), .CI(n_5_5), .CO(n_5_6), .S(n_4) + ); + FA_X1_LVT i_5_7( + .A(Instruction[25]), .B(RRs1[5]), .CI(n_5_6), .CO(n_5_7), .S(n_5) + ); + FA_X1_LVT i_5_8( + .A(Instruction[26]), .B(RRs1[6]), .CI(n_5_7), .CO(n_5_8), .S(n_6) + ); + FA_X1_LVT i_5_9( + .A(Instruction[27]), .B(RRs1[7]), .CI(n_5_8), .CO(n_5_9), .S(n_7) + ); + FA_X1_LVT i_5_10( + .A(Instruction[28]), .B(RRs1[8]), .CI(n_5_9), .CO(n_5_10), .S(n_8) + ); + FA_X1_LVT i_5_11( + .A(Instruction[29]), .B(RRs1[9]), .CI(n_5_10), .CO(n_5_11), .S(n_9) + ); + FA_X1_LVT i_5_12( + .A(Instruction[30]), .B(RRs1[10]), .CI(n_5_11), .CO(n_5_12), .S(n_10) + ); + FA_X1_LVT i_5_13( + .A(RRs1[11]), .B(Instruction[31]), .CI(n_5_12), .CO(n_5_13), .S(n_11) + ); + FA_X1_LVT i_5_14( + .A(n_5_0), .B(n_5_1), .CI(n_5_13), .CO(n_5_14), .S(n_12) + ); + FA_X1_LVT i_5_15( + .A(RRs1[13]), .B(n_5_1), .CI(n_5_14), .CO(n_5_15), .S(n_13) + ); + FA_X1_LVT i_5_16( + .A(RRs1[14]), .B(n_5_1), .CI(n_5_15), .CO(n_5_16), .S(n_14) + ); + FA_X1_LVT i_5_17( + .A(RRs1[15]), .B(n_5_1), .CI(n_5_16), .CO(n_5_17), .S(n_15) + ); + FA_X1_LVT i_5_18( + .A(RRs1[16]), .B(n_5_1), .CI(n_5_17), .CO(n_5_18), .S(n_16) + ); + FA_X1_LVT i_5_19( + .A(RRs1[17]), .B(n_5_1), .CI(n_5_18), .CO(n_5_19), .S(n_17) + ); + FA_X1_LVT i_5_20( + .A(RRs1[18]), .B(n_5_1), .CI(n_5_19), .CO(n_5_20), .S(n_18) + ); + FA_X1_LVT i_5_21( + .A(RRs1[19]), .B(n_5_1), .CI(n_5_20), .CO(n_5_21), .S(n_19) + ); + FA_X1_LVT i_5_22( + .A(RRs1[20]), .B(n_5_1), .CI(n_5_21), .CO(n_5_22), .S(n_20) + ); + FA_X1_LVT i_5_23( + .A(RRs1[21]), .B(n_5_1), .CI(n_5_22), .CO(n_5_23), .S(n_21) + ); + FA_X1_LVT i_5_24( + .A(RRs1[22]), .B(n_5_1), .CI(n_5_23), .CO(n_5_24), .S(n_22) + ); + FA_X1_LVT i_5_25( + .A(RRs1[23]), .B(n_5_1), .CI(n_5_24), .CO(n_5_25), .S(n_23) + ); + FA_X1_LVT i_5_26( + .A(RRs1[24]), .B(n_5_1), .CI(n_5_25), .CO(n_5_26), .S(n_24) + ); + FA_X1_LVT i_5_27( + .A(RRs1[25]), .B(n_5_1), .CI(n_5_26), .CO(n_5_27), .S(n_25) + ); + FA_X1_LVT i_5_28( + .A(RRs1[26]), .B(n_5_1), .CI(n_5_27), .CO(n_5_28), .S(n_26) + ); + FA_X1_LVT i_5_29( + .A(RRs1[27]), .B(n_5_1), .CI(n_5_28), .CO(n_5_29), .S(n_27) + ); + FA_X1_LVT i_5_30( + .A(RRs1[28]), .B(n_5_1), .CI(n_5_29), .CO(n_5_30), .S(n_28) + ); + FA_X1_LVT i_5_31( + .A(RRs1[29]), .B(n_5_1), .CI(n_5_30), .CO(n_5_31), .S(n_29) + ); + FA_X1_LVT i_5_32( + .A(RRs1[30]), .B(n_5_1), .CI(n_5_31), .CO(n_5_32), .S(n_30) + ); + XNOR2_X1_LVT i_5_34( + .A(n_5_33), .B(n_5_32), .ZN(n_31) + ); + NOR2_X1_LVT i_0_107( + .A1(n_0_249), .A2(Instruction[3]), .ZN(n_0_90) + ); + AOI222_X1_LVT i_0_106( + .A1(n_93), .A2(n_0_99), .B1(n_0_91), .B2(n_62), .C1(n_31), .C2(n_0_90), .ZN(n_0_89) + ); + INV_X1_LVT i_0_355( + .A(Instruction[6]), .ZN(n_0_248) + ); + NAND2_X1_LVT i_0_339( + .A1(n_0_248), .A2(Instruction[4]), .ZN(n_0_234) + ); + INV_X1_LVT i_0_338( + .A(n_0_234), .ZN(n_0_233) + ); + OAI21_X1_LVT i_0_341( + .A(Instruction[13]), .B1(Instruction[14]), .B2(Instruction[12]), .ZN(n_0_236) + ); + AOI211_X1_LVT i_0_337( + .A(n_0_235), .B(n_0_233), .C1(n_0_248), .C2(n_0_236), .ZN(n_0_232) + ); + INV_X1_LVT i_0_352( + .A(Instruction[4]), .ZN(n_0_245) + ); + NAND2_X1_LVT i_0_344( + .A1(n_0_245), .A2(Instruction[2]), .ZN(n_0_239) + ); + AOI21_X1_LVT i_0_335( + .A(Instruction[6]), .B1(n_0_243), .B2(n_0_239), .ZN(n_0_230) + ); + NOR2_X1_LVT i_0_334( + .A1(n_0_232), .A2(n_0_230), .ZN(n_0_229) + ); + NAND2_X1_LVT i_0_342( + .A1(n_0_241), .A2(n_0_238), .ZN(n_0_237) + ); + NAND2_X1_LVT i_0_336( + .A1(Instruction[6]), .A2(n_0_240), .ZN(n_0_231) + ); + OAI211_X1_LVT i_0_333( + .A(n_0_229), .B(n_0_237), .C1(Instruction[2]), .C2(n_0_231), .ZN(Illegal) + ); + NAND2_X1_LVT i_0_109( + .A1(Illegal), .A2(CurrentPC[31]), .ZN(n_0_92) + ); + NAND2_X1_LVT i_0_105( + .A1(n_0_89), .A2(n_0_92), .ZN(JumpOrBranchPC[31]) + ); + AOI222_X1_LVT i_0_103( + .A1(n_92), .A2(n_0_99), .B1(n_0_91), .B2(n_61), .C1(n_30), .C2(n_0_90), .ZN(n_0_87) + ); + NAND2_X1_LVT i_0_104( + .A1(Illegal), .A2(CurrentPC[30]), .ZN(n_0_88) + ); + NAND2_X1_LVT i_0_102( + .A1(n_0_87), .A2(n_0_88), .ZN(JumpOrBranchPC[30]) + ); + AOI222_X1_LVT i_0_100( + .A1(n_91), .A2(n_0_99), .B1(n_0_91), .B2(n_60), .C1(n_29), .C2(n_0_90), .ZN(n_0_85) + ); + NAND2_X1_LVT i_0_101( + .A1(Illegal), .A2(CurrentPC[29]), .ZN(n_0_86) + ); + NAND2_X1_LVT i_0_99( + .A1(n_0_85), .A2(n_0_86), .ZN(JumpOrBranchPC[29]) + ); + AOI222_X1_LVT i_0_97( + .A1(n_90), .A2(n_0_99), .B1(n_0_91), .B2(n_59), .C1(n_28), .C2(n_0_90), .ZN(n_0_83) + ); + NAND2_X1_LVT i_0_98( + .A1(Illegal), .A2(CurrentPC[28]), .ZN(n_0_84) + ); + NAND2_X1_LVT i_0_96( + .A1(n_0_83), .A2(n_0_84), .ZN(JumpOrBranchPC[28]) + ); + AOI222_X1_LVT i_0_94( + .A1(n_89), .A2(n_0_99), .B1(n_0_91), .B2(n_58), .C1(n_27), .C2(n_0_90), .ZN(n_0_81) + ); + NAND2_X1_LVT i_0_95( + .A1(Illegal), .A2(CurrentPC[27]), .ZN(n_0_82) + ); + NAND2_X1_LVT i_0_93( + .A1(n_0_81), .A2(n_0_82), .ZN(JumpOrBranchPC[27]) + ); + AOI222_X1_LVT i_0_91( + .A1(n_88), .A2(n_0_99), .B1(n_0_91), .B2(n_57), .C1(n_26), .C2(n_0_90), .ZN(n_0_79) + ); + NAND2_X1_LVT i_0_92( + .A1(Illegal), .A2(CurrentPC[26]), .ZN(n_0_80) + ); + NAND2_X1_LVT i_0_90( + .A1(n_0_79), .A2(n_0_80), .ZN(JumpOrBranchPC[26]) + ); + AOI222_X1_LVT i_0_88( + .A1(n_87), .A2(n_0_99), .B1(n_0_91), .B2(n_56), .C1(n_25), .C2(n_0_90), .ZN(n_0_77) + ); + NAND2_X1_LVT i_0_89( + .A1(Illegal), .A2(CurrentPC[25]), .ZN(n_0_78) + ); + NAND2_X1_LVT i_0_87( + .A1(n_0_77), .A2(n_0_78), .ZN(JumpOrBranchPC[25]) + ); + AOI222_X1_LVT i_0_85( + .A1(n_86), .A2(n_0_99), .B1(n_0_91), .B2(n_55), .C1(n_24), .C2(n_0_90), .ZN(n_0_75) + ); + NAND2_X1_LVT i_0_86( + .A1(Illegal), .A2(CurrentPC[24]), .ZN(n_0_76) + ); + NAND2_X1_LVT i_0_84( + .A1(n_0_75), .A2(n_0_76), .ZN(JumpOrBranchPC[24]) + ); + AOI222_X1_LVT i_0_82( + .A1(n_85), .A2(n_0_99), .B1(n_0_91), .B2(n_54), .C1(n_23), .C2(n_0_90), .ZN(n_0_73) + ); + NAND2_X1_LVT i_0_83( + .A1(Illegal), .A2(CurrentPC[23]), .ZN(n_0_74) + ); + NAND2_X1_LVT i_0_81( + .A1(n_0_73), .A2(n_0_74), .ZN(JumpOrBranchPC[23]) + ); + AOI222_X1_LVT i_0_79( + .A1(n_84), .A2(n_0_99), .B1(n_0_91), .B2(n_53), .C1(n_22), .C2(n_0_90), .ZN(n_0_71) + ); + NAND2_X1_LVT i_0_80( + .A1(Illegal), .A2(CurrentPC[22]), .ZN(n_0_72) + ); + NAND2_X1_LVT i_0_78( + .A1(n_0_71), .A2(n_0_72), .ZN(JumpOrBranchPC[22]) + ); + AOI222_X1_LVT i_0_76( + .A1(n_83), .A2(n_0_99), .B1(n_0_91), .B2(n_52), .C1(n_21), .C2(n_0_90), .ZN(n_0_69) + ); + NAND2_X1_LVT i_0_77( + .A1(Illegal), .A2(CurrentPC[21]), .ZN(n_0_70) + ); + NAND2_X1_LVT i_0_75( + .A1(n_0_69), .A2(n_0_70), .ZN(JumpOrBranchPC[21]) + ); + AOI222_X1_LVT i_0_73( + .A1(n_82), .A2(n_0_99), .B1(n_0_91), .B2(n_51), .C1(n_20), .C2(n_0_90), .ZN(n_0_67) + ); + NAND2_X1_LVT i_0_74( + .A1(Illegal), .A2(CurrentPC[20]), .ZN(n_0_68) + ); + NAND2_X1_LVT i_0_72( + .A1(n_0_67), .A2(n_0_68), .ZN(JumpOrBranchPC[20]) + ); + AOI222_X1_LVT i_0_70( + .A1(n_81), .A2(n_0_99), .B1(n_0_91), .B2(n_50), .C1(n_19), .C2(n_0_90), .ZN(n_0_65) + ); + NAND2_X1_LVT i_0_71( + .A1(Illegal), .A2(CurrentPC[19]), .ZN(n_0_66) + ); + NAND2_X1_LVT i_0_69( + .A1(n_0_65), .A2(n_0_66), .ZN(JumpOrBranchPC[19]) + ); + AOI222_X1_LVT i_0_67( + .A1(n_80), .A2(n_0_99), .B1(n_0_91), .B2(n_49), .C1(n_18), .C2(n_0_90), .ZN(n_0_63) + ); + NAND2_X1_LVT i_0_68( + .A1(Illegal), .A2(CurrentPC[18]), .ZN(n_0_64) + ); + NAND2_X1_LVT i_0_66( + .A1(n_0_63), .A2(n_0_64), .ZN(JumpOrBranchPC[18]) + ); + AOI222_X1_LVT i_0_64( + .A1(n_79), .A2(n_0_99), .B1(n_0_91), .B2(n_48), .C1(n_17), .C2(n_0_90), .ZN(n_0_61) + ); + NAND2_X1_LVT i_0_65( + .A1(Illegal), .A2(CurrentPC[17]), .ZN(n_0_62) + ); + NAND2_X1_LVT i_0_63( + .A1(n_0_61), .A2(n_0_62), .ZN(JumpOrBranchPC[17]) + ); + AOI222_X1_LVT i_0_61( + .A1(n_78), .A2(n_0_99), .B1(n_0_91), .B2(n_47), .C1(n_16), .C2(n_0_90), .ZN(n_0_59) + ); + NAND2_X1_LVT i_0_62( + .A1(Illegal), .A2(CurrentPC[16]), .ZN(n_0_60) + ); + NAND2_X1_LVT i_0_60( + .A1(n_0_59), .A2(n_0_60), .ZN(JumpOrBranchPC[16]) + ); + AOI222_X1_LVT i_0_58( + .A1(n_77), .A2(n_0_99), .B1(n_0_91), .B2(n_46), .C1(n_15), .C2(n_0_90), .ZN(n_0_57) + ); + NAND2_X1_LVT i_0_59( + .A1(Illegal), .A2(CurrentPC[15]), .ZN(n_0_58) + ); + NAND2_X1_LVT i_0_57( + .A1(n_0_57), .A2(n_0_58), .ZN(JumpOrBranchPC[15]) + ); + AOI222_X1_LVT i_0_55( + .A1(n_76), .A2(n_0_99), .B1(n_0_91), .B2(n_45), .C1(n_14), .C2(n_0_90), .ZN(n_0_55) + ); + NAND2_X1_LVT i_0_56( + .A1(Illegal), .A2(CurrentPC[14]), .ZN(n_0_56) + ); + NAND2_X1_LVT i_0_54( + .A1(n_0_55), .A2(n_0_56), .ZN(JumpOrBranchPC[14]) + ); + AOI222_X1_LVT i_0_52( + .A1(n_75), .A2(n_0_99), .B1(n_0_91), .B2(n_44), .C1(n_13), .C2(n_0_90), .ZN(n_0_53) + ); + NAND2_X1_LVT i_0_53( + .A1(Illegal), .A2(CurrentPC[13]), .ZN(n_0_54) + ); + NAND2_X1_LVT i_0_51( + .A1(n_0_53), .A2(n_0_54), .ZN(JumpOrBranchPC[13]) + ); + AOI222_X1_LVT i_0_49( + .A1(n_74), .A2(n_0_99), .B1(n_0_91), .B2(n_43), .C1(n_12), .C2(n_0_90), .ZN(n_0_51) + ); + NAND2_X1_LVT i_0_50( + .A1(Illegal), .A2(CurrentPC[12]), .ZN(n_0_52) + ); + NAND2_X1_LVT i_0_48( + .A1(n_0_51), .A2(n_0_52), .ZN(JumpOrBranchPC[12]) + ); + AOI222_X1_LVT i_0_46( + .A1(n_73), .A2(n_0_99), .B1(n_0_91), .B2(n_42), .C1(n_11), .C2(n_0_90), .ZN(n_0_49) + ); + NAND2_X1_LVT i_0_47( + .A1(Illegal), .A2(CurrentPC[11]), .ZN(n_0_50) + ); + NAND2_X1_LVT i_0_45( + .A1(n_0_49), .A2(n_0_50), .ZN(JumpOrBranchPC[11]) + ); + AOI222_X1_LVT i_0_43( + .A1(n_72), .A2(n_0_99), .B1(n_0_91), .B2(n_41), .C1(n_10), .C2(n_0_90), .ZN(n_0_47) + ); + NAND2_X1_LVT i_0_44( + .A1(Illegal), .A2(CurrentPC[10]), .ZN(n_0_48) + ); + NAND2_X1_LVT i_0_42( + .A1(n_0_47), .A2(n_0_48), .ZN(JumpOrBranchPC[10]) + ); + AOI222_X1_LVT i_0_40( + .A1(n_71), .A2(n_0_99), .B1(n_0_91), .B2(n_40), .C1(n_9), .C2(n_0_90), .ZN(n_0_45) + ); + NAND2_X1_LVT i_0_41( + .A1(Illegal), .A2(CurrentPC[9]), .ZN(n_0_46) + ); + NAND2_X1_LVT i_0_39( + .A1(n_0_45), .A2(n_0_46), .ZN(JumpOrBranchPC[9]) + ); + AOI222_X1_LVT i_0_37( + .A1(n_70), .A2(n_0_99), .B1(n_0_91), .B2(n_39), .C1(n_8), .C2(n_0_90), .ZN(n_0_43) + ); + NAND2_X1_LVT i_0_38( + .A1(Illegal), .A2(CurrentPC[8]), .ZN(n_0_44) + ); + NAND2_X1_LVT i_0_36( + .A1(n_0_43), .A2(n_0_44), .ZN(JumpOrBranchPC[8]) + ); + AOI222_X1_LVT i_0_34( + .A1(n_69), .A2(n_0_99), .B1(n_0_91), .B2(n_38), .C1(n_7), .C2(n_0_90), .ZN(n_0_41) + ); + NAND2_X1_LVT i_0_35( + .A1(Illegal), .A2(CurrentPC[7]), .ZN(n_0_42) + ); + NAND2_X1_LVT i_0_33( + .A1(n_0_41), .A2(n_0_42), .ZN(JumpOrBranchPC[7]) + ); + AOI222_X1_LVT i_0_31( + .A1(n_68), .A2(n_0_99), .B1(n_0_91), .B2(n_37), .C1(n_6), .C2(n_0_90), .ZN(n_0_39) + ); + NAND2_X1_LVT i_0_32( + .A1(Illegal), .A2(CurrentPC[6]), .ZN(n_0_40) + ); + NAND2_X1_LVT i_0_30( + .A1(n_0_39), .A2(n_0_40), .ZN(JumpOrBranchPC[6]) + ); + AOI222_X1_LVT i_0_28( + .A1(n_67), .A2(n_0_99), .B1(n_0_91), .B2(n_36), .C1(n_5), .C2(n_0_90), .ZN(n_0_37) + ); + NAND2_X1_LVT i_0_29( + .A1(Illegal), .A2(CurrentPC[5]), .ZN(n_0_38) + ); + NAND2_X1_LVT i_0_27( + .A1(n_0_37), .A2(n_0_38), .ZN(JumpOrBranchPC[5]) + ); + AOI222_X1_LVT i_0_25( + .A1(n_66), .A2(n_0_99), .B1(n_0_91), .B2(n_35), .C1(n_4), .C2(n_0_90), .ZN(n_0_35) + ); + NAND2_X1_LVT i_0_26( + .A1(Illegal), .A2(CurrentPC[4]), .ZN(n_0_36) + ); + NAND2_X1_LVT i_0_24( + .A1(n_0_35), .A2(n_0_36), .ZN(JumpOrBranchPC[4]) + ); + AOI222_X1_LVT i_0_22( + .A1(n_65), .A2(n_0_99), .B1(n_0_91), .B2(n_34), .C1(n_3), .C2(n_0_90), .ZN(n_0_33) + ); + NAND2_X1_LVT i_0_23( + .A1(Illegal), .A2(CurrentPC[3]), .ZN(n_0_34) + ); + NAND2_X1_LVT i_0_21( + .A1(n_0_33), .A2(n_0_34), .ZN(JumpOrBranchPC[3]) + ); + AOI222_X1_LVT i_0_19( + .A1(n_64), .A2(n_0_99), .B1(n_0_91), .B2(n_33), .C1(n_2), .C2(n_0_90), .ZN(n_0_31) + ); + NAND2_X1_LVT i_0_20( + .A1(Illegal), .A2(CurrentPC[2]), .ZN(n_0_32) + ); + NAND2_X1_LVT i_0_18( + .A1(n_0_31), .A2(n_0_32), .ZN(JumpOrBranchPC[2]) + ); + AOI222_X1_LVT i_0_16( + .A1(n_63), .A2(n_0_99), .B1(n_0_91), .B2(n_32), .C1(n_1), .C2(n_0_90), .ZN(n_0_29) + ); + NAND2_X1_LVT i_0_17( + .A1(Illegal), .A2(CurrentPC[1]), .ZN(n_0_30) + ); + NAND2_X1_LVT i_0_15( + .A1(n_0_29), .A2(n_0_30), .ZN(JumpOrBranchPC[1]) + ); + NOR2_X1_LVT i_0_112( + .A1(n_0_232), .A2(n_0_238), .ZN(n_0_94) + ); + OAI221_X1_LVT i_0_14( + .A(n_0_94), .B1(n_0_225), .B2(Instruction[2]), .C1(Instruction[6]), .C2(n_0_239), + .ZN(n_0_28) + ); + AND2_X1_LVT i_0_13( + .A1(n_0_28), .A2(CurrentPC[0]), .ZN(JumpOrBranchPC[0]) + ); + NOR2_X1_LVT i_0_221( + .A1(Instruction[13]), .A2(Instruction[14]), .ZN(n_0_166) + ); + NOR3_X1_LVT i_0_293( + .A1(n_0_241), .A2(n_0_234), .A3(Instruction[3]), .ZN(n_0_206) + ); + AND2_X1_LVT i_0_292( + .A1(n_0_206), .A2(n_0_244), .ZN(n_0_205) + ); + NOR3_X1_LVT i_0_330( + .A1(n_0_248), .A2(n_0_244), .A3(Instruction[4]), .ZN(n_0_226) + ); + AOI21_X1_LVT i_0_121( + .A(n_0_205), .B1(n_0_226), .B2(n_0_237), .ZN(n_0_100) + ); + AND2_X1_LVT i_0_120( + .A1(Instruction[14]), .A2(n_0_100), .ZN(aluOp[2]) + ); + OAI33_X1_LVT i_0_119( + .A1(n_0_205), .A2(n_0_247), .A3(n_0_224), .B1(Instruction[2]), .B2(n_0_238), + .B3(n_0_225), .ZN(aluOp[1]) + ); + AOI22_X1_LVT i_0_117( + .A1(Instruction[12]), .A2(n_0_100), .B1(n_0_99), .B2(Instruction[13]), .ZN(n_0_98) + ); + INV_X1_LVT i_0_116( + .A(n_0_98), .ZN(aluOp[0]) + ); + OR2_X1_LVT i_0_327( + .A1(n_0_238), .A2(n_0_234), .ZN(n_0_223) + ); + NOR4_X1_LVT i_0_125( + .A1(Instruction[28]), .A2(Instruction[27]), .A3(Instruction[26]), .A4(Instruction[25]), + .ZN(n_0_103) + ); + INV_X1_LVT i_0_347( + .A(Instruction[30]), .ZN(n_0_242) + ); + NOR4_X1_LVT i_0_124( + .A1(Instruction[13]), .A2(n_0_242), .A3(Instruction[29]), .A4(Instruction[31]), + .ZN(n_0_102) + ); + NAND2_X1_LVT i_0_123( + .A1(n_0_103), .A2(n_0_102), .ZN(n_0_101) + ); + NOR3_X1_LVT i_0_127( + .A1(n_0_244), .A2(Instruction[12]), .A3(Instruction[14]), .ZN(n_0_105) + ); + AOI21_X1_LVT i_0_126( + .A(n_0_105), .B1(Instruction[12]), .B2(Instruction[14]), .ZN(n_0_104) + ); + NOR4_X1_LVT i_0_122( + .A1(n_0_223), .A2(n_0_101), .A3(n_0_104), .A4(Instruction[2]), .ZN(aluNegAr) + ); + OR3_X1_LVT i_0_325( + .A1(n_0_228), .A2(Instruction[4]), .A3(Instruction[6]), .ZN(n_0_222) + ); + NOR2_X1_LVT i_0_321( + .A1(n_0_222), .A2(Instruction[5]), .ZN(n_0_221) + ); + NOR3_X1_LVT i_0_224( + .A1(n_0_224), .A2(n_0_221), .A3(n_0_206), .ZN(n_0_169) + ); + NOR3_X1_LVT i_0_129( + .A1(n_0_234), .A2(Instruction[3]), .A3(Instruction[5]), .ZN(n_0_106) + ); + NOR3_X1_LVT i_0_128( + .A1(n_0_226), .A2(n_0_169), .A3(n_0_106), .ZN(aluBypass) + ); + AOI22_X1_LVT i_0_223( + .A1(CurrentPC[31]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[31]), .ZN(n_0_168) + ); + NOR3_X1_LVT i_0_219( + .A1(n_0_247), .A2(n_0_222), .A3(Instruction[5]), .ZN(n_0_164) + ); + AOI22_X1_LVT i_0_218( + .A1(RRs1[31]), .A2(n_0_169), .B1(n_0_164), .B2(RData[31]), .ZN(n_0_163) + ); + MUX2_X1_LVT i_0_222( + .A(RData[7]), .B(RData[15]), .S(Instruction[12]), .Z(n_0_167) + ); + NAND3_X1_LVT i_0_220( + .A1(n_0_221), .A2(n_0_167), .A3(n_0_166), .ZN(n_0_165) + ); + NAND3_X1_LVT i_0_217( + .A1(n_0_168), .A2(n_0_163), .A3(n_0_165), .ZN(op1[31]) + ); + AOI22_X1_LVT i_0_216( + .A1(RRs1[30]), .A2(n_0_169), .B1(n_0_164), .B2(RData[30]), .ZN(n_0_162) + ); + AOI22_X1_LVT i_0_215( + .A1(CurrentPC[30]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[30]), .ZN(n_0_161) + ); + NAND3_X1_LVT i_0_214( + .A1(n_0_162), .A2(n_0_161), .A3(n_0_165), .ZN(op1[30]) + ); + AOI22_X1_LVT i_0_213( + .A1(RRs1[29]), .A2(n_0_169), .B1(n_0_164), .B2(RData[29]), .ZN(n_0_160) + ); + AOI22_X1_LVT i_0_212( + .A1(CurrentPC[29]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[29]), .ZN(n_0_159) + ); + NAND3_X1_LVT i_0_211( + .A1(n_0_160), .A2(n_0_159), .A3(n_0_165), .ZN(op1[29]) + ); + AOI22_X1_LVT i_0_210( + .A1(RRs1[28]), .A2(n_0_169), .B1(n_0_164), .B2(RData[28]), .ZN(n_0_158) + ); + AOI22_X1_LVT i_0_209( + .A1(CurrentPC[28]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[28]), .ZN(n_0_157) + ); + NAND3_X1_LVT i_0_208( + .A1(n_0_158), .A2(n_0_157), .A3(n_0_165), .ZN(op1[28]) + ); + AOI22_X1_LVT i_0_207( + .A1(RRs1[27]), .A2(n_0_169), .B1(n_0_164), .B2(RData[27]), .ZN(n_0_156) + ); + AOI22_X1_LVT i_0_206( + .A1(CurrentPC[27]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[27]), .ZN(n_0_155) + ); + NAND3_X1_LVT i_0_205( + .A1(n_0_156), .A2(n_0_155), .A3(n_0_165), .ZN(op1[27]) + ); + AOI22_X1_LVT i_0_204( + .A1(RRs1[26]), .A2(n_0_169), .B1(n_0_164), .B2(RData[26]), .ZN(n_0_154) + ); + AOI22_X1_LVT i_0_203( + .A1(CurrentPC[26]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[26]), .ZN(n_0_153) + ); + NAND3_X1_LVT i_0_202( + .A1(n_0_154), .A2(n_0_153), .A3(n_0_165), .ZN(op1[26]) + ); + AOI22_X1_LVT i_0_201( + .A1(RRs1[25]), .A2(n_0_169), .B1(n_0_164), .B2(RData[25]), .ZN(n_0_152) + ); + AOI22_X1_LVT i_0_200( + .A1(CurrentPC[25]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[25]), .ZN(n_0_151) + ); + NAND3_X1_LVT i_0_199( + .A1(n_0_152), .A2(n_0_151), .A3(n_0_165), .ZN(op1[25]) + ); + AOI22_X1_LVT i_0_198( + .A1(RRs1[24]), .A2(n_0_169), .B1(n_0_164), .B2(RData[24]), .ZN(n_0_150) + ); + AOI22_X1_LVT i_0_197( + .A1(CurrentPC[24]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[24]), .ZN(n_0_149) + ); + NAND3_X1_LVT i_0_196( + .A1(n_0_150), .A2(n_0_149), .A3(n_0_165), .ZN(op1[24]) + ); + AOI22_X1_LVT i_0_195( + .A1(RRs1[23]), .A2(n_0_169), .B1(n_0_164), .B2(RData[23]), .ZN(n_0_148) + ); + AOI22_X1_LVT i_0_194( + .A1(CurrentPC[23]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[23]), .ZN(n_0_147) + ); + NAND3_X1_LVT i_0_193( + .A1(n_0_148), .A2(n_0_147), .A3(n_0_165), .ZN(op1[23]) + ); + AOI22_X1_LVT i_0_192( + .A1(RRs1[22]), .A2(n_0_169), .B1(n_0_164), .B2(RData[22]), .ZN(n_0_146) + ); + AOI22_X1_LVT i_0_191( + .A1(CurrentPC[22]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[22]), .ZN(n_0_145) + ); + NAND3_X1_LVT i_0_190( + .A1(n_0_146), .A2(n_0_145), .A3(n_0_165), .ZN(op1[22]) + ); + AOI22_X1_LVT i_0_189( + .A1(RRs1[21]), .A2(n_0_169), .B1(n_0_164), .B2(RData[21]), .ZN(n_0_144) + ); + AOI22_X1_LVT i_0_188( + .A1(CurrentPC[21]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[21]), .ZN(n_0_143) + ); + NAND3_X1_LVT i_0_187( + .A1(n_0_144), .A2(n_0_143), .A3(n_0_165), .ZN(op1[21]) + ); + AOI22_X1_LVT i_0_186( + .A1(RRs1[20]), .A2(n_0_169), .B1(n_0_164), .B2(RData[20]), .ZN(n_0_142) + ); + AOI22_X1_LVT i_0_185( + .A1(CurrentPC[20]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[20]), .ZN(n_0_141) + ); + NAND3_X1_LVT i_0_184( + .A1(n_0_142), .A2(n_0_141), .A3(n_0_165), .ZN(op1[20]) + ); + AOI22_X1_LVT i_0_183( + .A1(RRs1[19]), .A2(n_0_169), .B1(n_0_164), .B2(RData[19]), .ZN(n_0_140) + ); + AOI22_X1_LVT i_0_182( + .A1(CurrentPC[19]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[19]), .ZN(n_0_139) + ); + NAND3_X1_LVT i_0_181( + .A1(n_0_140), .A2(n_0_139), .A3(n_0_165), .ZN(op1[19]) + ); + AOI22_X1_LVT i_0_180( + .A1(RRs1[18]), .A2(n_0_169), .B1(n_0_164), .B2(RData[18]), .ZN(n_0_138) + ); + AOI22_X1_LVT i_0_179( + .A1(CurrentPC[18]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[18]), .ZN(n_0_137) + ); + NAND3_X1_LVT i_0_178( + .A1(n_0_138), .A2(n_0_137), .A3(n_0_165), .ZN(op1[18]) + ); + AOI22_X1_LVT i_0_177( + .A1(RRs1[17]), .A2(n_0_169), .B1(n_0_164), .B2(RData[17]), .ZN(n_0_136) + ); + AOI22_X1_LVT i_0_176( + .A1(CurrentPC[17]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[17]), .ZN(n_0_135) + ); + NAND3_X1_LVT i_0_175( + .A1(n_0_136), .A2(n_0_135), .A3(n_0_165), .ZN(op1[17]) + ); + AOI22_X1_LVT i_0_174( + .A1(RRs1[16]), .A2(n_0_169), .B1(n_0_164), .B2(RData[16]), .ZN(n_0_134) + ); + AOI22_X1_LVT i_0_173( + .A1(CurrentPC[16]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[16]), .ZN(n_0_133) + ); + NAND3_X1_LVT i_0_172( + .A1(n_0_134), .A2(n_0_133), .A3(n_0_165), .ZN(op1[16]) + ); + AOI222_X1_LVT i_0_169( + .A1(CurrentPC[15]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[15]), .C1(n_0_169), + .C2(RRs1[15]), .ZN(n_0_130) + ); + INV_X1_LVT i_0_353( + .A(Instruction[12]), .ZN(n_0_246) + ); + AOI211_X1_LVT i_0_171( + .A(Instruction[5]), .B(n_0_222), .C1(n_0_247), .C2(n_0_246), .ZN(n_0_132) + ); + OAI211_X1_LVT i_0_170( + .A(RData[15]), .B(n_0_132), .C1(Instruction[13]), .C2(Instruction[14]), .ZN(n_0_131) + ); + NAND3_X1_LVT i_0_168( + .A1(n_0_130), .A2(n_0_131), .A3(n_0_165), .ZN(op1[15]) + ); + AOI22_X1_LVT i_0_167( + .A1(RRs1[14]), .A2(n_0_169), .B1(n_0_132), .B2(RData[14]), .ZN(n_0_129) + ); + AOI22_X1_LVT i_0_166( + .A1(CurrentPC[14]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[14]), .ZN(n_0_128) + ); + NAND4_X1_LVT i_0_165( + .A1(n_0_221), .A2(n_0_246), .A3(RData[7]), .A4(n_0_166), .ZN(n_0_127) + ); + NAND3_X1_LVT i_0_164( + .A1(n_0_129), .A2(n_0_128), .A3(n_0_127), .ZN(op1[14]) + ); + AOI22_X1_LVT i_0_163( + .A1(RRs1[13]), .A2(n_0_169), .B1(n_0_132), .B2(RData[13]), .ZN(n_0_126) + ); + AOI22_X1_LVT i_0_162( + .A1(CurrentPC[13]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[13]), .ZN(n_0_125) + ); + NAND3_X1_LVT i_0_161( + .A1(n_0_126), .A2(n_0_125), .A3(n_0_127), .ZN(op1[13]) + ); + AOI22_X1_LVT i_0_160( + .A1(RRs1[12]), .A2(n_0_169), .B1(n_0_132), .B2(RData[12]), .ZN(n_0_124) + ); + AOI22_X1_LVT i_0_159( + .A1(CurrentPC[12]), .A2(n_0_224), .B1(n_0_206), .B2(Instruction[12]), .ZN(n_0_123) + ); + NAND3_X1_LVT i_0_158( + .A1(n_0_124), .A2(n_0_123), .A3(n_0_127), .ZN(op1[12]) + ); + AOI22_X1_LVT i_0_156( + .A1(CurrentPC[11]), .A2(n_0_224), .B1(n_0_132), .B2(RData[11]), .ZN(n_0_121) + ); + NAND2_X1_LVT i_0_157( + .A1(RRs1[11]), .A2(n_0_169), .ZN(n_0_122) + ); + NAND3_X1_LVT i_0_155( + .A1(n_0_121), .A2(n_0_122), .A3(n_0_127), .ZN(op1[11]) + ); + AOI22_X1_LVT i_0_153( + .A1(CurrentPC[10]), .A2(n_0_224), .B1(n_0_132), .B2(RData[10]), .ZN(n_0_119) + ); + NAND2_X1_LVT i_0_154( + .A1(RRs1[10]), .A2(n_0_169), .ZN(n_0_120) + ); + NAND3_X1_LVT i_0_152( + .A1(n_0_119), .A2(n_0_120), .A3(n_0_127), .ZN(op1[10]) + ); + AOI22_X1_LVT i_0_150( + .A1(CurrentPC[9]), .A2(n_0_224), .B1(n_0_132), .B2(RData[9]), .ZN(n_0_117) + ); + NAND2_X1_LVT i_0_151( + .A1(RRs1[9]), .A2(n_0_169), .ZN(n_0_118) + ); + NAND3_X1_LVT i_0_149( + .A1(n_0_117), .A2(n_0_118), .A3(n_0_127), .ZN(op1[9]) + ); + AOI22_X1_LVT i_0_147( + .A1(CurrentPC[8]), .A2(n_0_224), .B1(n_0_132), .B2(RData[8]), .ZN(n_0_115) + ); + NAND2_X1_LVT i_0_148( + .A1(RRs1[8]), .A2(n_0_169), .ZN(n_0_116) + ); + NAND3_X1_LVT i_0_146( + .A1(n_0_115), .A2(n_0_116), .A3(n_0_127), .ZN(op1[8]) + ); + AOI222_X1_LVT i_0_145( + .A1(CurrentPC[7]), .A2(n_0_224), .B1(n_0_221), .B2(RData[7]), .C1(n_0_169), + .C2(RRs1[7]), .ZN(n_0_114) + ); + INV_X1_LVT i_0_144( + .A(n_0_114), .ZN(op1[7]) + ); + AOI222_X1_LVT i_0_143( + .A1(CurrentPC[6]), .A2(n_0_224), .B1(n_0_221), .B2(RData[6]), .C1(n_0_169), + .C2(RRs1[6]), .ZN(n_0_113) + ); + INV_X1_LVT i_0_142( + .A(n_0_113), .ZN(op1[6]) + ); + AOI222_X1_LVT i_0_141( + .A1(CurrentPC[5]), .A2(n_0_224), .B1(n_0_221), .B2(RData[5]), .C1(n_0_169), + .C2(RRs1[5]), .ZN(n_0_112) + ); + INV_X1_LVT i_0_140( + .A(n_0_112), .ZN(op1[5]) + ); + AOI222_X1_LVT i_0_139( + .A1(CurrentPC[4]), .A2(n_0_224), .B1(n_0_221), .B2(RData[4]), .C1(n_0_169), + .C2(RRs1[4]), .ZN(n_0_111) + ); + INV_X1_LVT i_0_138( + .A(n_0_111), .ZN(op1[4]) + ); + AOI222_X1_LVT i_0_137( + .A1(CurrentPC[3]), .A2(n_0_224), .B1(n_0_221), .B2(RData[3]), .C1(n_0_169), + .C2(RRs1[3]), .ZN(n_0_110) + ); + INV_X1_LVT i_0_136( + .A(n_0_110), .ZN(op1[3]) + ); + AOI222_X1_LVT i_0_135( + .A1(CurrentPC[2]), .A2(n_0_224), .B1(n_0_221), .B2(RData[2]), .C1(n_0_169), + .C2(RRs1[2]), .ZN(n_0_109) + ); + INV_X1_LVT i_0_134( + .A(n_0_109), .ZN(op1[2]) + ); + AOI222_X1_LVT i_0_133( + .A1(CurrentPC[1]), .A2(n_0_224), .B1(n_0_221), .B2(RData[1]), .C1(n_0_169), + .C2(RRs1[1]), .ZN(n_0_108) + ); + INV_X1_LVT i_0_132( + .A(n_0_108), .ZN(op1[1]) + ); + AOI222_X1_LVT i_0_131( + .A1(CurrentPC[0]), .A2(n_0_224), .B1(n_0_221), .B2(RData[0]), .C1(n_0_169), + .C2(RRs1[0]), .ZN(n_0_107) + ); + INV_X1_LVT i_0_130( + .A(n_0_107), .ZN(op1[0]) + ); + NOR3_X1_LVT i_0_294( + .A1(n_0_223), .A2(Instruction[2]), .A3(Instruction[5]), .ZN(n_0_207) + ); + NOR3_X1_LVT i_0_291( + .A1(n_0_224), .A2(n_0_207), .A3(n_0_205), .ZN(n_0_204) + ); + AOI22_X1_LVT i_0_289( + .A1(CurrentPC[31]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[31]), .ZN(n_0_202) + ); + NAND2_X1_LVT i_0_290( + .A1(Instruction[31]), .A2(n_0_207), .ZN(n_0_203) + ); + NAND2_X1_LVT i_0_288( + .A1(n_0_202), .A2(n_0_203), .ZN(op2[31]) + ); + AOI22_X1_LVT i_0_287( + .A1(CurrentPC[30]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[30]), .ZN(n_0_201) + ); + NAND2_X1_LVT i_0_286( + .A1(n_0_201), .A2(n_0_203), .ZN(op2[30]) + ); + AOI22_X1_LVT i_0_285( + .A1(CurrentPC[29]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[29]), .ZN(n_0_200) + ); + NAND2_X1_LVT i_0_284( + .A1(n_0_200), .A2(n_0_203), .ZN(op2[29]) + ); + AOI22_X1_LVT i_0_283( + .A1(CurrentPC[28]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[28]), .ZN(n_0_199) + ); + NAND2_X1_LVT i_0_282( + .A1(n_0_199), .A2(n_0_203), .ZN(op2[28]) + ); + AOI22_X1_LVT i_0_281( + .A1(CurrentPC[27]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[27]), .ZN(n_0_198) + ); + NAND2_X1_LVT i_0_280( + .A1(n_0_198), .A2(n_0_203), .ZN(op2[27]) + ); + AOI22_X1_LVT i_0_279( + .A1(CurrentPC[26]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[26]), .ZN(n_0_197) + ); + NAND2_X1_LVT i_0_278( + .A1(n_0_197), .A2(n_0_203), .ZN(op2[26]) + ); + AOI22_X1_LVT i_0_277( + .A1(CurrentPC[25]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[25]), .ZN(n_0_196) + ); + NAND2_X1_LVT i_0_276( + .A1(n_0_196), .A2(n_0_203), .ZN(op2[25]) + ); + AOI22_X1_LVT i_0_275( + .A1(CurrentPC[24]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[24]), .ZN(n_0_195) + ); + NAND2_X1_LVT i_0_274( + .A1(n_0_195), .A2(n_0_203), .ZN(op2[24]) + ); + AOI22_X1_LVT i_0_273( + .A1(CurrentPC[23]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[23]), .ZN(n_0_194) + ); + NAND2_X1_LVT i_0_272( + .A1(n_0_194), .A2(n_0_203), .ZN(op2[23]) + ); + AOI22_X1_LVT i_0_271( + .A1(CurrentPC[22]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[22]), .ZN(n_0_193) + ); + NAND2_X1_LVT i_0_270( + .A1(n_0_193), .A2(n_0_203), .ZN(op2[22]) + ); + AOI22_X1_LVT i_0_269( + .A1(CurrentPC[21]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[21]), .ZN(n_0_192) + ); + NAND2_X1_LVT i_0_268( + .A1(n_0_192), .A2(n_0_203), .ZN(op2[21]) + ); + AOI22_X1_LVT i_0_267( + .A1(CurrentPC[20]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[20]), .ZN(n_0_191) + ); + NAND2_X1_LVT i_0_266( + .A1(n_0_191), .A2(n_0_203), .ZN(op2[20]) + ); + AOI22_X1_LVT i_0_265( + .A1(CurrentPC[19]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[19]), .ZN(n_0_190) + ); + NAND2_X1_LVT i_0_264( + .A1(n_0_190), .A2(n_0_203), .ZN(op2[19]) + ); + AOI22_X1_LVT i_0_263( + .A1(CurrentPC[18]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[18]), .ZN(n_0_189) + ); + NAND2_X1_LVT i_0_262( + .A1(n_0_189), .A2(n_0_203), .ZN(op2[18]) + ); + AOI22_X1_LVT i_0_261( + .A1(CurrentPC[17]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[17]), .ZN(n_0_188) + ); + NAND2_X1_LVT i_0_260( + .A1(n_0_188), .A2(n_0_203), .ZN(op2[17]) + ); + AOI22_X1_LVT i_0_259( + .A1(CurrentPC[16]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[16]), .ZN(n_0_187) + ); + NAND2_X1_LVT i_0_258( + .A1(n_0_187), .A2(n_0_203), .ZN(op2[16]) + ); + AOI22_X1_LVT i_0_257( + .A1(CurrentPC[15]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[15]), .ZN(n_0_186) + ); + NAND2_X1_LVT i_0_256( + .A1(n_0_186), .A2(n_0_203), .ZN(op2[15]) + ); + AOI22_X1_LVT i_0_255( + .A1(CurrentPC[14]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[14]), .ZN(n_0_185) + ); + NAND2_X1_LVT i_0_254( + .A1(n_0_185), .A2(n_0_203), .ZN(op2[14]) + ); + AOI22_X1_LVT i_0_253( + .A1(CurrentPC[13]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[13]), .ZN(n_0_184) + ); + NAND2_X1_LVT i_0_252( + .A1(n_0_184), .A2(n_0_203), .ZN(op2[13]) + ); + AOI22_X1_LVT i_0_251( + .A1(CurrentPC[12]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[12]), .ZN(n_0_183) + ); + NAND2_X1_LVT i_0_250( + .A1(n_0_183), .A2(n_0_203), .ZN(op2[12]) + ); + AOI22_X1_LVT i_0_249( + .A1(CurrentPC[11]), .A2(n_0_205), .B1(n_0_204), .B2(RRs2[11]), .ZN(n_0_182) + ); + NAND2_X1_LVT i_0_248( + .A1(n_0_182), .A2(n_0_203), .ZN(op2[11]) + ); + AOI222_X1_LVT i_0_247( + .A1(Instruction[30]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[10]), .C1(n_0_204), + .C2(RRs2[10]), .ZN(n_0_181) + ); + INV_X1_LVT i_0_246( + .A(n_0_181), .ZN(op2[10]) + ); + AOI222_X1_LVT i_0_245( + .A1(Instruction[29]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[9]), .C1(n_0_204), + .C2(RRs2[9]), .ZN(n_0_180) + ); + INV_X1_LVT i_0_244( + .A(n_0_180), .ZN(op2[9]) + ); + AOI222_X1_LVT i_0_243( + .A1(Instruction[28]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[8]), .C1(n_0_204), + .C2(RRs2[8]), .ZN(n_0_179) + ); + INV_X1_LVT i_0_242( + .A(n_0_179), .ZN(op2[8]) + ); + AOI222_X1_LVT i_0_241( + .A1(Instruction[27]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[7]), .C1(n_0_204), + .C2(RRs2[7]), .ZN(n_0_178) + ); + INV_X1_LVT i_0_240( + .A(n_0_178), .ZN(op2[7]) + ); + AOI222_X1_LVT i_0_239( + .A1(Instruction[26]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[6]), .C1(n_0_204), + .C2(RRs2[6]), .ZN(n_0_177) + ); + INV_X1_LVT i_0_238( + .A(n_0_177), .ZN(op2[6]) + ); + AOI222_X1_LVT i_0_237( + .A1(Instruction[25]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[5]), .C1(n_0_204), + .C2(RRs2[5]), .ZN(n_0_176) + ); + INV_X1_LVT i_0_236( + .A(n_0_176), .ZN(op2[5]) + ); + AOI222_X1_LVT i_0_235( + .A1(Instruction[24]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[4]), .C1(n_0_204), + .C2(RRs2[4]), .ZN(n_0_175) + ); + INV_X1_LVT i_0_234( + .A(n_0_175), .ZN(op2[4]) + ); + AOI222_X1_LVT i_0_233( + .A1(Instruction[23]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[3]), .C1(n_0_204), + .C2(RRs2[3]), .ZN(n_0_174) + ); + INV_X1_LVT i_0_232( + .A(n_0_174), .ZN(op2[3]) + ); + AOI22_X1_LVT i_0_230( + .A1(Instruction[22]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[2]), .ZN(n_0_172) + ); + OAI21_X1_LVT i_0_231( + .A(RRs2[2]), .B1(n_0_223), .B2(Instruction[5]), .ZN(n_0_173) + ); + NAND3_X1_LVT i_0_229( + .A1(n_0_172), .A2(n_0_173), .A3(n_0_249), .ZN(op2[2]) + ); + AOI222_X1_LVT i_0_228( + .A1(Instruction[21]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[1]), .C1(n_0_204), + .C2(RRs2[1]), .ZN(n_0_171) + ); + INV_X1_LVT i_0_227( + .A(n_0_171), .ZN(op2[1]) + ); + AOI222_X1_LVT i_0_226( + .A1(Instruction[20]), .A2(n_0_207), .B1(n_0_205), .B2(CurrentPC[0]), .C1(n_0_204), + .C2(RRs2[0]), .ZN(n_0_170) + ); + INV_X1_LVT i_0_225( + .A(n_0_170), .ZN(op2[0]) + ); + alu theALU( + .aluOp(aluOp), .aluNegAr(aluNegAr), .aluBypass(aluBypass), .op1(op1), .op2(op2), + .result(WRd), .eqFlag(eqFlag) + ); + XNOR2_X1_LVT i_0_115( + .A(Instruction[12]), .B(eqFlag), .ZN(n_0_97) + ); + XNOR2_X1_LVT i_0_114( + .A(Instruction[12]), .B(WRd[0]), .ZN(n_0_96) + ); + AOI22_X1_LVT i_0_113( + .A1(n_0_166), .A2(n_0_97), .B1(n_0_96), .B2(Instruction[14]), .ZN(n_0_95) + ); + AOI22_X1_LVT i_0_111( + .A1(Instruction[6]), .A2(n_0_95), .B1(Instruction[2]), .B2(n_0_245), .ZN(n_0_93) + ); + NAND2_X1_LVT i_0_110( + .A1(n_0_94), .A2(n_0_93), .ZN(JumpOrBranch) + ); + INV_X1_LVT i_0_349( + .A(Instruction[31]), .ZN(n_0_0) + ); + INV_X1_LVT i_0_348( + .A(RRs1[12]), .ZN(n_0_1) + ); + HA_X1_LVT i_0_0( + .A(Instruction[7]), .B(RRs1[0]), .CO(n_0_2), .S(n_0_15) + ); + FA_X1_LVT i_0_1( + .A(Instruction[8]), .B(RRs1[1]), .CI(n_0_2), .CO(n_0_3), .S(n_0_16) + ); + FA_X1_LVT i_0_2( + .A(Instruction[9]), .B(RRs1[2]), .CI(n_0_3), .CO(n_0_4), .S(n_0_17) + ); + FA_X1_LVT i_0_3( + .A(Instruction[10]), .B(RRs1[3]), .CI(n_0_4), .CO(n_0_5), .S(n_0_18) + ); + FA_X1_LVT i_0_4( + .A(Instruction[11]), .B(RRs1[4]), .CI(n_0_5), .CO(n_0_6), .S(n_0_19) + ); + FA_X1_LVT i_0_5( + .A(Instruction[25]), .B(RRs1[5]), .CI(n_0_6), .CO(n_0_7), .S(n_0_20) + ); + FA_X1_LVT i_0_6( + .A(Instruction[26]), .B(RRs1[6]), .CI(n_0_7), .CO(n_0_8), .S(n_0_21) + ); + FA_X1_LVT i_0_7( + .A(Instruction[27]), .B(RRs1[7]), .CI(n_0_8), .CO(n_0_9), .S(n_0_22) + ); + FA_X1_LVT i_0_8( + .A(Instruction[28]), .B(RRs1[8]), .CI(n_0_9), .CO(n_0_10), .S(n_0_23) + ); + FA_X1_LVT i_0_9( + .A(Instruction[29]), .B(RRs1[9]), .CI(n_0_10), .CO(n_0_11), .S(n_0_24) + ); + FA_X1_LVT i_0_10( + .A(Instruction[30]), .B(RRs1[10]), .CI(n_0_11), .CO(n_0_12), .S(n_0_25) + ); + FA_X1_LVT i_0_11( + .A(RRs1[11]), .B(Instruction[31]), .CI(n_0_12), .CO(n_0_13), .S(n_0_26) + ); + FA_X1_LVT i_0_12( + .A(n_0_0), .B(n_0_1), .CI(n_0_13), .CO(n_0_14), .S(n_0_27) + ); + NOR2_X1_LVT i_0_322( + .A1(n_0_244), .A2(n_0_222), .ZN(WrMem) + ); + AOI22_X1_LVT i_0_320( + .A1(n_0_27), .A2(WrMem), .B1(n_0_221), .B2(n_12), .ZN(n_0_220) + ); + INV_X1_LVT i_0_319( + .A(n_0_220), .ZN(DAddr[12]) + ); + AOI22_X1_LVT i_0_318( + .A1(n_0_26), .A2(WrMem), .B1(n_0_221), .B2(n_11), .ZN(n_0_219) + ); + INV_X1_LVT i_0_317( + .A(n_0_219), .ZN(DAddr[11]) + ); + AOI22_X1_LVT i_0_316( + .A1(n_0_25), .A2(WrMem), .B1(n_0_221), .B2(n_10), .ZN(n_0_218) + ); + INV_X1_LVT i_0_315( + .A(n_0_218), .ZN(DAddr[10]) + ); + AOI22_X1_LVT i_0_314( + .A1(n_0_24), .A2(WrMem), .B1(n_0_221), .B2(n_9), .ZN(n_0_217) + ); + INV_X1_LVT i_0_313( + .A(n_0_217), .ZN(DAddr[9]) + ); + AOI22_X1_LVT i_0_312( + .A1(n_0_23), .A2(WrMem), .B1(n_0_221), .B2(n_8), .ZN(n_0_216) + ); + INV_X1_LVT i_0_311( + .A(n_0_216), .ZN(DAddr[8]) + ); + AOI22_X1_LVT i_0_310( + .A1(n_0_22), .A2(WrMem), .B1(n_0_221), .B2(n_7), .ZN(n_0_215) + ); + INV_X1_LVT i_0_309( + .A(n_0_215), .ZN(DAddr[7]) + ); + AOI22_X1_LVT i_0_308( + .A1(n_0_21), .A2(WrMem), .B1(n_0_221), .B2(n_6), .ZN(n_0_214) + ); + INV_X1_LVT i_0_307( + .A(n_0_214), .ZN(DAddr[6]) + ); + AOI22_X1_LVT i_0_306( + .A1(n_0_20), .A2(WrMem), .B1(n_0_221), .B2(n_5), .ZN(n_0_213) + ); + INV_X1_LVT i_0_305( + .A(n_0_213), .ZN(DAddr[5]) + ); + AOI22_X1_LVT i_0_304( + .A1(n_0_19), .A2(WrMem), .B1(n_0_221), .B2(n_4), .ZN(n_0_212) + ); + INV_X1_LVT i_0_303( + .A(n_0_212), .ZN(DAddr[4]) + ); + AOI22_X1_LVT i_0_302( + .A1(n_0_18), .A2(WrMem), .B1(n_0_221), .B2(n_3), .ZN(n_0_211) + ); + INV_X1_LVT i_0_301( + .A(n_0_211), .ZN(DAddr[3]) + ); + AOI22_X1_LVT i_0_300( + .A1(n_0_17), .A2(WrMem), .B1(n_0_221), .B2(n_2), .ZN(n_0_210) + ); + INV_X1_LVT i_0_299( + .A(n_0_210), .ZN(DAddr[2]) + ); + AOI22_X1_LVT i_0_298( + .A1(n_0_16), .A2(WrMem), .B1(n_0_221), .B2(n_1), .ZN(n_0_209) + ); + INV_X1_LVT i_0_297( + .A(n_0_209), .ZN(DAddr[1]) + ); + AOI22_X1_LVT i_0_296( + .A1(n_0_15), .A2(WrMem), .B1(n_0_221), .B2(n_0), .ZN(n_0_208) + ); + INV_X1_LVT i_0_295( + .A(n_0_208), .ZN(DAddr[0]) + ); + OR2_X1_LVT i_0_324( + .A1(n_0_222), .A2(Instruction[13]), .ZN(DWidth[1]) + ); + NOR2_X1_LVT i_0_323( + .A1(n_0_246), .A2(n_0_222), .ZN(DWidth[0]) + ); + NAND3_X1_LVT i_0_331( + .A1(n_0_248), .A2(n_0_244), .A3(n_0_236), .ZN(n_0_227) + ); + OAI211_X1_LVT i_0_326( + .A(n_0_249), .B(n_0_223), .C1(n_0_228), .C2(n_0_227), .ZN(WrReg) + ); +endmodule + +module MemGen_32_11(chip_en, clock, addr, rd_data, rd_en, wr_en, wr_data); + input [31:0] wr_data; + input [10:0] addr; + input chip_en, clock, rd_en, wr_en; + output [31:0] rd_data; + + wire [1:0] mem_sel; + wire n_63, n_62, n_61, n_60, n_59, n_58, n_57, n_56, n_55, n_54, n_53, n_52, + n_51, n_50, n_49, n_48, n_31, n_30, n_29, n_28, n_27, n_26, n_25, n_24, + n_23, n_22, n_21, n_20, n_19, n_18, n_17, n_16, n_47, n_46, n_45, n_44, + n_43, n_42, n_41, n_40, n_39, n_38, n_37, n_36, n_35, n_34, n_33, n_32, + n_15, n_14, n_13, n_12, n_11, n_10, n_9, n_8, n_7, n_6, n_5, n_4, n_3, + n_2, n_1, n_0; + + INV_X1_LVT i_1_3( + .A(addr[10]), .ZN(mem_sel[0]) + ); + MemGen_16_10 genblk1_0_U_hi( + .chip_en(mem_sel[0]), .wr_en(wr_en), .addr({addr[9], addr[8], addr[7], + addr[6], addr[5], addr[4], addr[3], addr[2], addr[1], addr[0]}), .wr_data({ + wr_data[31], wr_data[30], wr_data[29], wr_data[28], wr_data[27], + wr_data[26], wr_data[25], wr_data[24], wr_data[23], wr_data[22], + wr_data[21], wr_data[20], wr_data[19], wr_data[18], wr_data[17], + wr_data[16]}), .clock(clock), .rd_en(rd_en), .rd_data({n_63, n_62, n_61, + n_60, n_59, n_58, n_57, n_56, n_55, n_54, n_53, n_52, n_51, n_50, n_49, + n_48}) + ); + MemGen_16_10 genblk1_1_U_hi( + .chip_en(addr[10]), .wr_en(wr_en), .addr({addr[9], addr[8], addr[7], + addr[6], addr[5], addr[4], addr[3], addr[2], addr[1], addr[0]}), .wr_data({ + wr_data[31], wr_data[30], wr_data[29], wr_data[28], wr_data[27], + wr_data[26], wr_data[25], wr_data[24], wr_data[23], wr_data[22], + wr_data[21], wr_data[20], wr_data[19], wr_data[18], wr_data[17], + wr_data[16]}), .clock(clock), .rd_en(rd_en), .rd_data({n_31, n_30, n_29, + n_28, n_27, n_26, n_25, n_24, n_23, n_22, n_21, n_20, n_19, n_18, n_17, + n_16}) + ); + MUX2_X1_LVT i_1_1_31( + .A(n_63), .B(n_31), .S(addr[10]), .Z(rd_data[31]) + ); + MUX2_X1_LVT i_1_1_30( + .A(n_62), .B(n_30), .S(addr[10]), .Z(rd_data[30]) + ); + MUX2_X1_LVT i_1_1_29( + .A(n_61), .B(n_29), .S(addr[10]), .Z(rd_data[29]) + ); + MUX2_X1_LVT i_1_1_28( + .A(n_60), .B(n_28), .S(addr[10]), .Z(rd_data[28]) + ); + MUX2_X1_LVT i_1_1_27( + .A(n_59), .B(n_27), .S(addr[10]), .Z(rd_data[27]) + ); + MUX2_X1_LVT i_1_1_26( + .A(n_58), .B(n_26), .S(addr[10]), .Z(rd_data[26]) + ); + MUX2_X1_LVT i_1_1_25( + .A(n_57), .B(n_25), .S(addr[10]), .Z(rd_data[25]) + ); + MUX2_X1_LVT i_1_1_24( + .A(n_56), .B(n_24), .S(addr[10]), .Z(rd_data[24]) + ); + MUX2_X1_LVT i_1_1_23( + .A(n_55), .B(n_23), .S(addr[10]), .Z(rd_data[23]) + ); + MUX2_X1_LVT i_1_1_22( + .A(n_54), .B(n_22), .S(addr[10]), .Z(rd_data[22]) + ); + MUX2_X1_LVT i_1_1_21( + .A(n_53), .B(n_21), .S(addr[10]), .Z(rd_data[21]) + ); + MUX2_X1_LVT i_1_1_20( + .A(n_52), .B(n_20), .S(addr[10]), .Z(rd_data[20]) + ); + MUX2_X1_LVT i_1_1_19( + .A(n_51), .B(n_19), .S(addr[10]), .Z(rd_data[19]) + ); + MUX2_X1_LVT i_1_1_18( + .A(n_50), .B(n_18), .S(addr[10]), .Z(rd_data[18]) + ); + MUX2_X1_LVT i_1_1_17( + .A(n_49), .B(n_17), .S(addr[10]), .Z(rd_data[17]) + ); + MUX2_X1_LVT i_1_1_16( + .A(n_48), .B(n_16), .S(addr[10]), .Z(rd_data[16]) + ); + MemGen_16_10 genblk1_0_U_lo( + .chip_en(mem_sel[0]), .wr_en(wr_en), .addr({addr[9], addr[8], addr[7], + addr[6], addr[5], addr[4], addr[3], addr[2], addr[1], addr[0]}), .wr_data({ + wr_data[15], wr_data[14], wr_data[13], wr_data[12], wr_data[11], + wr_data[10], wr_data[9], wr_data[8], wr_data[7], wr_data[6], wr_data[5], + wr_data[4], wr_data[3], wr_data[2], wr_data[1], wr_data[0]}), .clock(clock), + .rd_en(rd_en), .rd_data({n_47, n_46, n_45, n_44, n_43, n_42, n_41, + n_40, n_39, n_38, n_37, n_36, n_35, n_34, n_33, n_32}) + ); + MemGen_16_10 genblk1_1_U_lo( + .chip_en(addr[10]), .wr_en(wr_en), .addr({addr[9], addr[8], addr[7], + addr[6], addr[5], addr[4], addr[3], addr[2], addr[1], addr[0]}), .wr_data({ + wr_data[15], wr_data[14], wr_data[13], wr_data[12], wr_data[11], + wr_data[10], wr_data[9], wr_data[8], wr_data[7], wr_data[6], wr_data[5], + wr_data[4], wr_data[3], wr_data[2], wr_data[1], wr_data[0]}), .clock(clock), + .rd_en(rd_en), .rd_data({n_15, n_14, n_13, n_12, n_11, n_10, n_9, n_8, + n_7, n_6, n_5, n_4, n_3, n_2, n_1, n_0}) + ); + MUX2_X1_LVT i_1_1_15( + .A(n_47), .B(n_15), .S(addr[10]), .Z(rd_data[15]) + ); + MUX2_X1_LVT i_1_1_14( + .A(n_46), .B(n_14), .S(addr[10]), .Z(rd_data[14]) + ); + MUX2_X1_LVT i_1_1_13( + .A(n_45), .B(n_13), .S(addr[10]), .Z(rd_data[13]) + ); + MUX2_X1_LVT i_1_1_12( + .A(n_44), .B(n_12), .S(addr[10]), .Z(rd_data[12]) + ); + MUX2_X1_LVT i_1_1_11( + .A(n_43), .B(n_11), .S(addr[10]), .Z(rd_data[11]) + ); + MUX2_X1_LVT i_1_1_10( + .A(n_42), .B(n_10), .S(addr[10]), .Z(rd_data[10]) + ); + MUX2_X1_LVT i_1_1_9( + .A(n_41), .B(n_9), .S(addr[10]), .Z(rd_data[9]) + ); + MUX2_X1_LVT i_1_1_8( + .A(n_40), .B(n_8), .S(addr[10]), .Z(rd_data[8]) + ); + MUX2_X1_LVT i_1_1_7( + .A(n_39), .B(n_7), .S(addr[10]), .Z(rd_data[7]) + ); + MUX2_X1_LVT i_1_1_6( + .A(n_38), .B(n_6), .S(addr[10]), .Z(rd_data[6]) + ); + MUX2_X1_LVT i_1_1_5( + .A(n_37), .B(n_5), .S(addr[10]), .Z(rd_data[5]) + ); + MUX2_X1_LVT i_1_1_4( + .A(n_36), .B(n_4), .S(addr[10]), .Z(rd_data[4]) + ); + MUX2_X1_LVT i_1_1_3( + .A(n_35), .B(n_3), .S(addr[10]), .Z(rd_data[3]) + ); + MUX2_X1_LVT i_1_1_2( + .A(n_34), .B(n_2), .S(addr[10]), .Z(rd_data[2]) + ); + MUX2_X1_LVT i_1_1_1( + .A(n_33), .B(n_1), .S(addr[10]), .Z(rd_data[1]) + ); + MUX2_X1_LVT i_1_1_0( + .A(n_32), .B(n_0), .S(addr[10]), .Z(rd_data[0]) + ); +endmodule + +module main_mem(clk, reset, DAddr, IAddr, DWData, DRData, IRData, DWE, DWidth); + input [31:0] DAddr, IAddr, DWData; + input [1:0] DWidth; + input clk, reset, DWE; + output [31:0] DRData, IRData; + + wire [31:0] mem_rdata, drTmp, mem_wdata; + wire [10:0] mem_addr; + wire n_0_0, n_0_0_0, n_0_1, n_0_0_1, n_0_2, n_0_0_2, n_0_3, n_0_0_3, n_0_4, + n_0_0_4, n_0_5, n_0_0_5, n_0_6, n_0_0_6, n_0_7, n_0_0_7, n_0_8, n_0_0_8, + n_0_9, n_0_0_9, n_0_10, n_0_0_10, n_0_0_11, n_0_11, n_0_0_12, n_0_0_13, + n_0_12, n_0_0_14, n_0_0_15, n_0_13, n_0_0_16, n_0_0_17, n_0_14, + n_0_0_18, n_0_0_19, n_0_15, n_0_0_20, n_0_0_21, n_0_16, n_0_0_22, + n_0_0_23, n_0_17, n_0_0_24, n_0_0_25, n_0_18, n_0_0_26, n_0_0_27, + n_0_0_28, n_0_19, n_0_0_29, n_0_20, n_0_0_30, n_0_21, n_0_0_31, n_0_22, + n_0_0_32, n_0_23, n_0_0_33, n_0_24, n_0_0_34, n_0_25, n_0_0_35, n_0_26, + n_0_0_36, n_0_0_37, n_0_27, n_0_28, n_0_29, n_0_30, n_0_31, n_0_32, + n_0_33, n_0_34, n_0_35, n_0_36, n_0_37, n_0_38, n_0_39, n_0_40, n_0_41, + n_0_42, n_0_65, n_0_64, n_0_63, n_0_62, n_0_61, n_0_60, n_0_59, n_0_58, + n_0_0_38, n_0_0_39, n_0_57, n_0_0_40, n_0_56, n_0_0_41, n_0_55, + n_0_0_42, n_0_54, n_0_0_43, n_0_53, n_0_0_44, n_0_52, n_0_0_45, n_0_51, + n_0_0_46, n_0_50, n_0_0_47, n_0_0_48, n_0_0_49, n_0_0_50, n_0_0_51, + n_0_49, n_0_0_52, n_0_48, n_0_0_53, n_0_47, n_0_0_54, n_0_46, n_0_0_55, + n_0_45, n_0_0_56, n_0_44, n_0_0_57, n_0_66, n_0_0_58, n_0_67, n_0_0_59, + n_0_0_60, n_0_0_61, n_0_68, n_0_0_62, n_0_0_63, n_0_69, n_0_0_64, + n_0_0_65, n_0_70, n_0_0_66, n_0_0_67, n_0_71, n_0_0_68, n_0_0_69, + n_0_72, n_0_0_70, n_0_0_71, n_0_73, n_0_0_72, n_0_0_73, n_0_74, + n_0_0_74, n_0_0_75, n_0_75, n_0_0_76, n_0_0_77, n_0_0_78, n_0_0_79, + n_0_0_80, n_0_0_81, n_0_0_82, n_0_0_83, n_0_0_84, n_0_0_85, n_0_0_86, + n_0_0_87, n_0_0_88, n_0_0_89, n_0_0_90, n_0_0_91, n_0_0_92, n_0_43, + n_0_0_93, n_0_0_94, n_0_76, n_0_0_95, n_0; + + INV_X1_LVT i_0_0_171( + .A(DWE), .ZN(n_0) + ); + NOR2_X1_LVT i_0_0_163( + .A1(n_0), .A2(reset), .ZN(n_0_0_88) + ); + NOR2_X1_LVT i_0_0_22( + .A1(DWE), .A2(reset), .ZN(n_0_0_11) + ); + AOI22_X1_LVT i_0_0_21( + .A1(DAddr[12]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[12]), .ZN(n_0_0_10) + ); + INV_X1_LVT i_0_0_20( + .A(n_0_0_10), .ZN(n_0_10) + ); + INV_X1_LVT i_0_0_172( + .A(clk), .ZN(n_0_76) + ); + DFF_X1_LVT \mem_addr_reg[10] ( + .CK(n_0_76), .D(n_0_10), .Q(mem_addr[10]), .QN() + ); + AOI22_X1_LVT i_0_0_19( + .A1(DAddr[11]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[11]), .ZN(n_0_0_9) + ); + INV_X1_LVT i_0_0_18( + .A(n_0_0_9), .ZN(n_0_9) + ); + DFF_X1_LVT \mem_addr_reg[9] ( + .CK(n_0_76), .D(n_0_9), .Q(mem_addr[9]), .QN() + ); + AOI22_X1_LVT i_0_0_17( + .A1(DAddr[10]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[10]), .ZN(n_0_0_8) + ); + INV_X1_LVT i_0_0_16( + .A(n_0_0_8), .ZN(n_0_8) + ); + DFF_X1_LVT \mem_addr_reg[8] ( + .CK(n_0_76), .D(n_0_8), .Q(mem_addr[8]), .QN() + ); + AOI22_X1_LVT i_0_0_15( + .A1(DAddr[9]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[9]), .ZN(n_0_0_7) + ); + INV_X1_LVT i_0_0_14( + .A(n_0_0_7), .ZN(n_0_7) + ); + DFF_X1_LVT \mem_addr_reg[7] ( + .CK(n_0_76), .D(n_0_7), .Q(mem_addr[7]), .QN() + ); + AOI22_X1_LVT i_0_0_13( + .A1(DAddr[8]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[8]), .ZN(n_0_0_6) + ); + INV_X1_LVT i_0_0_12( + .A(n_0_0_6), .ZN(n_0_6) + ); + DFF_X1_LVT \mem_addr_reg[6] ( + .CK(n_0_76), .D(n_0_6), .Q(mem_addr[6]), .QN() + ); + AOI22_X1_LVT i_0_0_11( + .A1(DAddr[7]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[7]), .ZN(n_0_0_5) + ); + INV_X1_LVT i_0_0_10( + .A(n_0_0_5), .ZN(n_0_5) + ); + DFF_X1_LVT \mem_addr_reg[5] ( + .CK(n_0_76), .D(n_0_5), .Q(mem_addr[5]), .QN() + ); + AOI22_X1_LVT i_0_0_9( + .A1(DAddr[6]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[6]), .ZN(n_0_0_4) + ); + INV_X1_LVT i_0_0_8( + .A(n_0_0_4), .ZN(n_0_4) + ); + DFF_X1_LVT \mem_addr_reg[4] ( + .CK(n_0_76), .D(n_0_4), .Q(mem_addr[4]), .QN() + ); + AOI22_X1_LVT i_0_0_7( + .A1(DAddr[5]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[5]), .ZN(n_0_0_3) + ); + INV_X1_LVT i_0_0_6( + .A(n_0_0_3), .ZN(n_0_3) + ); + DFF_X1_LVT \mem_addr_reg[3] ( + .CK(n_0_76), .D(n_0_3), .Q(mem_addr[3]), .QN() + ); + AOI22_X1_LVT i_0_0_5( + .A1(DAddr[4]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[4]), .ZN(n_0_0_2) + ); + INV_X1_LVT i_0_0_4( + .A(n_0_0_2), .ZN(n_0_2) + ); + DFF_X1_LVT \mem_addr_reg[2] ( + .CK(n_0_76), .D(n_0_2), .Q(mem_addr[2]), .QN() + ); + AOI22_X1_LVT i_0_0_3( + .A1(DAddr[3]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[3]), .ZN(n_0_0_1) + ); + INV_X1_LVT i_0_0_2( + .A(n_0_0_1), .ZN(n_0_1) + ); + DFF_X1_LVT \mem_addr_reg[1] ( + .CK(n_0_76), .D(n_0_1), .Q(mem_addr[1]), .QN() + ); + AOI22_X1_LVT i_0_0_1( + .A1(DAddr[2]), .A2(n_0_0_88), .B1(n_0_0_11), .B2(IAddr[2]), .ZN(n_0_0_0) + ); + INV_X1_LVT i_0_0_0( + .A(n_0_0_0), .ZN(n_0_0) + ); + DFF_X1_LVT \mem_addr_reg[0] ( + .CK(n_0_76), .D(n_0_0), .Q(mem_addr[0]), .QN() + ); + NOR2_X1_LVT i_0_0_162( + .A1(DWidth[1]), .A2(DAddr[1]), .ZN(n_0_0_87) + ); + NOR2_X1_LVT i_0_0_158( + .A1(DWidth[0]), .A2(DAddr[0]), .ZN(n_0_0_83) + ); + AND2_X1_LVT i_0_0_157( + .A1(n_0_0_87), .A2(n_0_0_83), .ZN(n_0_0_82) + ); + AND2_X1_LVT i_0_0_156( + .A1(n_0_0_88), .A2(n_0_0_82), .ZN(n_0_0_81) + ); + INV_X1_LVT i_0_0_173( + .A(n_0_0_88), .ZN(n_0_0_95) + ); + INV_X1_LVT i_0_0_169( + .A(DWidth[1]), .ZN(n_0_0_93) + ); + NOR3_X1_LVT i_0_0_155( + .A1(n_0_0_95), .A2(DWidth[0]), .A3(n_0_0_93), .ZN(n_0_0_80) + ); + AOI22_X1_LVT i_0_0_154( + .A1(DWData[7]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[31]), .ZN(n_0_0_79) + ); + NAND2_X1_LVT i_0_0_168( + .A1(DWidth[0]), .A2(DWidth[1]), .ZN(n_0_43) + ); + INV_X1_LVT i_0_0_167( + .A(n_0_43), .ZN(n_0_0_92) + ); + NOR2_X1_LVT i_0_0_160( + .A1(n_0_0_95), .A2(n_0_0_92), .ZN(n_0_0_85) + ); + NAND2_X1_LVT i_0_0_161( + .A1(n_0_0_93), .A2(DAddr[1]), .ZN(n_0_0_86) + ); + NOR2_X1_LVT i_0_0_166( + .A1(DWidth[0]), .A2(DWidth[1]), .ZN(n_0_0_91) + ); + NAND2_X1_LVT i_0_0_164( + .A1(DAddr[0]), .A2(n_0_0_91), .ZN(n_0_0_89) + ); + NAND3_X1_LVT i_0_0_159( + .A1(n_0_0_85), .A2(n_0_0_86), .A3(n_0_0_89), .ZN(n_0_0_84) + ); + INV_X1_LVT i_0_0_170( + .A(DWidth[0]), .ZN(n_0_0_94) + ); + NOR2_X1_LVT i_0_0_153( + .A1(n_0_0_94), .A2(DAddr[1]), .ZN(n_0_0_78) + ); + AND3_X1_LVT i_0_0_152( + .A1(n_0_0_88), .A2(n_0_0_78), .A3(n_0_0_93), .ZN(n_0_0_77) + ); + AOI22_X1_LVT i_0_0_151( + .A1(n_0_0_84), .A2(mem_wdata[31]), .B1(DWData[15]), .B2(n_0_0_77), .ZN(n_0_0_76) + ); + NAND2_X1_LVT i_0_0_150( + .A1(n_0_0_79), .A2(n_0_0_76), .ZN(n_0_75) + ); + DFF_X1_LVT \mem_wdata_reg[31] ( + .CK(n_0_76), .D(n_0_75), .Q(mem_wdata[31]), .QN() + ); + AOI22_X1_LVT i_0_0_149( + .A1(DWData[6]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[30]), .ZN(n_0_0_75) + ); + AOI22_X1_LVT i_0_0_148( + .A1(n_0_0_84), .A2(mem_wdata[30]), .B1(DWData[14]), .B2(n_0_0_77), .ZN(n_0_0_74) + ); + NAND2_X1_LVT i_0_0_147( + .A1(n_0_0_75), .A2(n_0_0_74), .ZN(n_0_74) + ); + DFF_X1_LVT \mem_wdata_reg[30] ( + .CK(n_0_76), .D(n_0_74), .Q(mem_wdata[30]), .QN() + ); + AOI22_X1_LVT i_0_0_146( + .A1(DWData[5]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[29]), .ZN(n_0_0_73) + ); + AOI22_X1_LVT i_0_0_145( + .A1(n_0_0_84), .A2(mem_wdata[29]), .B1(DWData[13]), .B2(n_0_0_77), .ZN(n_0_0_72) + ); + NAND2_X1_LVT i_0_0_144( + .A1(n_0_0_73), .A2(n_0_0_72), .ZN(n_0_73) + ); + DFF_X1_LVT \mem_wdata_reg[29] ( + .CK(n_0_76), .D(n_0_73), .Q(mem_wdata[29]), .QN() + ); + AOI22_X1_LVT i_0_0_143( + .A1(DWData[4]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[28]), .ZN(n_0_0_71) + ); + AOI22_X1_LVT i_0_0_142( + .A1(n_0_0_84), .A2(mem_wdata[28]), .B1(DWData[12]), .B2(n_0_0_77), .ZN(n_0_0_70) + ); + NAND2_X1_LVT i_0_0_141( + .A1(n_0_0_71), .A2(n_0_0_70), .ZN(n_0_72) + ); + DFF_X1_LVT \mem_wdata_reg[28] ( + .CK(n_0_76), .D(n_0_72), .Q(mem_wdata[28]), .QN() + ); + AOI22_X1_LVT i_0_0_140( + .A1(DWData[3]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[27]), .ZN(n_0_0_69) + ); + AOI22_X1_LVT i_0_0_139( + .A1(n_0_0_84), .A2(mem_wdata[27]), .B1(DWData[11]), .B2(n_0_0_77), .ZN(n_0_0_68) + ); + NAND2_X1_LVT i_0_0_138( + .A1(n_0_0_69), .A2(n_0_0_68), .ZN(n_0_71) + ); + DFF_X1_LVT \mem_wdata_reg[27] ( + .CK(n_0_76), .D(n_0_71), .Q(mem_wdata[27]), .QN() + ); + AOI22_X1_LVT i_0_0_137( + .A1(DWData[2]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[26]), .ZN(n_0_0_67) + ); + AOI22_X1_LVT i_0_0_136( + .A1(n_0_0_84), .A2(mem_wdata[26]), .B1(DWData[10]), .B2(n_0_0_77), .ZN(n_0_0_66) + ); + NAND2_X1_LVT i_0_0_135( + .A1(n_0_0_67), .A2(n_0_0_66), .ZN(n_0_70) + ); + DFF_X1_LVT \mem_wdata_reg[26] ( + .CK(n_0_76), .D(n_0_70), .Q(mem_wdata[26]), .QN() + ); + AOI22_X1_LVT i_0_0_134( + .A1(DWData[1]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[25]), .ZN(n_0_0_65) + ); + AOI22_X1_LVT i_0_0_133( + .A1(n_0_0_84), .A2(mem_wdata[25]), .B1(DWData[9]), .B2(n_0_0_77), .ZN(n_0_0_64) + ); + NAND2_X1_LVT i_0_0_132( + .A1(n_0_0_65), .A2(n_0_0_64), .ZN(n_0_69) + ); + DFF_X1_LVT \mem_wdata_reg[25] ( + .CK(n_0_76), .D(n_0_69), .Q(mem_wdata[25]), .QN() + ); + AOI22_X1_LVT i_0_0_131( + .A1(DWData[0]), .A2(n_0_0_81), .B1(n_0_0_80), .B2(DWData[24]), .ZN(n_0_0_63) + ); + AOI22_X1_LVT i_0_0_130( + .A1(n_0_0_84), .A2(mem_wdata[24]), .B1(DWData[8]), .B2(n_0_0_77), .ZN(n_0_0_62) + ); + NAND2_X1_LVT i_0_0_129( + .A1(n_0_0_63), .A2(n_0_0_62), .ZN(n_0_68) + ); + DFF_X1_LVT \mem_wdata_reg[24] ( + .CK(n_0_76), .D(n_0_68), .Q(mem_wdata[24]), .QN() + ); + NOR4_X1_LVT i_0_0_127( + .A1(n_0_0_95), .A2(n_0_0_83), .A3(DWidth[1]), .A4(DAddr[1]), .ZN(n_0_0_60) + ); + INV_X1_LVT i_0_0_165( + .A(n_0_0_91), .ZN(n_0_0_90) + ); + OAI211_X1_LVT i_0_0_128( + .A(n_0_0_85), .B(n_0_0_86), .C1(n_0_0_90), .C2(DAddr[0]), .ZN(n_0_0_61) + ); + AOI222_X1_LVT i_0_0_126( + .A1(DWData[7]), .A2(n_0_0_60), .B1(mem_wdata[23]), .B2(n_0_0_61), .C1(DWData[23]), + .C2(n_0_0_80), .ZN(n_0_0_59) + ); + INV_X1_LVT i_0_0_125( + .A(n_0_0_59), .ZN(n_0_67) + ); + DFF_X1_LVT \mem_wdata_reg[23] ( + .CK(n_0_76), .D(n_0_67), .Q(mem_wdata[23]), .QN() + ); + AOI222_X1_LVT i_0_0_124( + .A1(DWData[6]), .A2(n_0_0_60), .B1(mem_wdata[22]), .B2(n_0_0_61), .C1(DWData[22]), + .C2(n_0_0_80), .ZN(n_0_0_58) + ); + INV_X1_LVT i_0_0_123( + .A(n_0_0_58), .ZN(n_0_66) + ); + DFF_X1_LVT \mem_wdata_reg[22] ( + .CK(n_0_76), .D(n_0_66), .Q(mem_wdata[22]), .QN() + ); + AOI222_X1_LVT i_0_0_122( + .A1(DWData[5]), .A2(n_0_0_60), .B1(mem_wdata[21]), .B2(n_0_0_61), .C1(DWData[21]), + .C2(n_0_0_80), .ZN(n_0_0_57) + ); + INV_X1_LVT i_0_0_121( + .A(n_0_0_57), .ZN(n_0_44) + ); + DFF_X1_LVT \mem_wdata_reg[21] ( + .CK(n_0_76), .D(n_0_44), .Q(mem_wdata[21]), .QN() + ); + AOI222_X1_LVT i_0_0_120( + .A1(DWData[4]), .A2(n_0_0_60), .B1(mem_wdata[20]), .B2(n_0_0_61), .C1(DWData[20]), + .C2(n_0_0_80), .ZN(n_0_0_56) + ); + INV_X1_LVT i_0_0_119( + .A(n_0_0_56), .ZN(n_0_45) + ); + DFF_X1_LVT \mem_wdata_reg[20] ( + .CK(n_0_76), .D(n_0_45), .Q(mem_wdata[20]), .QN() + ); + AOI222_X1_LVT i_0_0_118( + .A1(DWData[3]), .A2(n_0_0_60), .B1(mem_wdata[19]), .B2(n_0_0_61), .C1(DWData[19]), + .C2(n_0_0_80), .ZN(n_0_0_55) + ); + INV_X1_LVT i_0_0_117( + .A(n_0_0_55), .ZN(n_0_46) + ); + DFF_X1_LVT \mem_wdata_reg[19] ( + .CK(n_0_76), .D(n_0_46), .Q(mem_wdata[19]), .QN() + ); + AOI222_X1_LVT i_0_0_116( + .A1(DWData[2]), .A2(n_0_0_60), .B1(mem_wdata[18]), .B2(n_0_0_61), .C1(DWData[18]), + .C2(n_0_0_80), .ZN(n_0_0_54) + ); + INV_X1_LVT i_0_0_115( + .A(n_0_0_54), .ZN(n_0_47) + ); + DFF_X1_LVT \mem_wdata_reg[18] ( + .CK(n_0_76), .D(n_0_47), .Q(mem_wdata[18]), .QN() + ); + AOI222_X1_LVT i_0_0_114( + .A1(DWData[1]), .A2(n_0_0_60), .B1(mem_wdata[17]), .B2(n_0_0_61), .C1(DWData[17]), + .C2(n_0_0_80), .ZN(n_0_0_53) + ); + INV_X1_LVT i_0_0_113( + .A(n_0_0_53), .ZN(n_0_48) + ); + DFF_X1_LVT \mem_wdata_reg[17] ( + .CK(n_0_76), .D(n_0_48), .Q(mem_wdata[17]), .QN() + ); + AOI222_X1_LVT i_0_0_112( + .A1(DWData[0]), .A2(n_0_0_60), .B1(mem_wdata[16]), .B2(n_0_0_61), .C1(DWData[16]), + .C2(n_0_0_80), .ZN(n_0_0_52) + ); + INV_X1_LVT i_0_0_111( + .A(n_0_0_52), .ZN(n_0_49) + ); + DFF_X1_LVT \mem_wdata_reg[16] ( + .CK(n_0_76), .D(n_0_49), .Q(mem_wdata[16]), .QN() + ); + NOR4_X1_LVT i_0_0_110( + .A1(n_0_0_95), .A2(n_0_0_87), .A3(n_0_0_92), .A4(n_0_0_91), .ZN(n_0_0_51) + ); + NOR3_X1_LVT i_0_0_109( + .A1(n_0_0_86), .A2(DAddr[0]), .A3(DWidth[0]), .ZN(n_0_0_50) + ); + AND2_X1_LVT i_0_0_108( + .A1(n_0_0_88), .A2(n_0_0_50), .ZN(n_0_0_49) + ); + OAI211_X1_LVT i_0_0_107( + .A(n_0_0_85), .B(n_0_0_89), .C1(DAddr[1]), .C2(DWidth[1]), .ZN(n_0_0_48) + ); + AOI222_X1_LVT i_0_0_106( + .A1(DWData[15]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[7]), .C1(n_0_0_48), + .C2(mem_wdata[15]), .ZN(n_0_0_47) + ); + INV_X1_LVT i_0_0_105( + .A(n_0_0_47), .ZN(n_0_50) + ); + DFF_X1_LVT \mem_wdata_reg[15] ( + .CK(n_0_76), .D(n_0_50), .Q(mem_wdata[15]), .QN() + ); + AOI222_X1_LVT i_0_0_104( + .A1(DWData[14]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[6]), .C1(n_0_0_48), + .C2(mem_wdata[14]), .ZN(n_0_0_46) + ); + INV_X1_LVT i_0_0_103( + .A(n_0_0_46), .ZN(n_0_51) + ); + DFF_X1_LVT \mem_wdata_reg[14] ( + .CK(n_0_76), .D(n_0_51), .Q(mem_wdata[14]), .QN() + ); + AOI222_X1_LVT i_0_0_102( + .A1(DWData[13]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[5]), .C1(n_0_0_48), + .C2(mem_wdata[13]), .ZN(n_0_0_45) + ); + INV_X1_LVT i_0_0_101( + .A(n_0_0_45), .ZN(n_0_52) + ); + DFF_X1_LVT \mem_wdata_reg[13] ( + .CK(n_0_76), .D(n_0_52), .Q(mem_wdata[13]), .QN() + ); + AOI222_X1_LVT i_0_0_100( + .A1(DWData[12]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[4]), .C1(n_0_0_48), + .C2(mem_wdata[12]), .ZN(n_0_0_44) + ); + INV_X1_LVT i_0_0_99( + .A(n_0_0_44), .ZN(n_0_53) + ); + DFF_X1_LVT \mem_wdata_reg[12] ( + .CK(n_0_76), .D(n_0_53), .Q(mem_wdata[12]), .QN() + ); + AOI222_X1_LVT i_0_0_98( + .A1(DWData[11]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[3]), .C1(n_0_0_48), + .C2(mem_wdata[11]), .ZN(n_0_0_43) + ); + INV_X1_LVT i_0_0_97( + .A(n_0_0_43), .ZN(n_0_54) + ); + DFF_X1_LVT \mem_wdata_reg[11] ( + .CK(n_0_76), .D(n_0_54), .Q(mem_wdata[11]), .QN() + ); + AOI222_X1_LVT i_0_0_96( + .A1(DWData[10]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[2]), .C1(n_0_0_48), + .C2(mem_wdata[10]), .ZN(n_0_0_42) + ); + INV_X1_LVT i_0_0_95( + .A(n_0_0_42), .ZN(n_0_55) + ); + DFF_X1_LVT \mem_wdata_reg[10] ( + .CK(n_0_76), .D(n_0_55), .Q(mem_wdata[10]), .QN() + ); + AOI222_X1_LVT i_0_0_94( + .A1(DWData[9]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[1]), .C1(n_0_0_48), + .C2(mem_wdata[9]), .ZN(n_0_0_41) + ); + INV_X1_LVT i_0_0_93( + .A(n_0_0_41), .ZN(n_0_56) + ); + DFF_X1_LVT \mem_wdata_reg[9] ( + .CK(n_0_76), .D(n_0_56), .Q(mem_wdata[9]), .QN() + ); + AOI222_X1_LVT i_0_0_92( + .A1(DWData[8]), .A2(n_0_0_51), .B1(n_0_0_49), .B2(DWData[0]), .C1(n_0_0_48), + .C2(mem_wdata[8]), .ZN(n_0_0_40) + ); + INV_X1_LVT i_0_0_91( + .A(n_0_0_40), .ZN(n_0_57) + ); + DFF_X1_LVT \mem_wdata_reg[8] ( + .CK(n_0_76), .D(n_0_57), .Q(mem_wdata[8]), .QN() + ); + AOI21_X1_LVT i_0_0_90( + .A(n_0_0_87), .B1(n_0_0_83), .B2(n_0_0_93), .ZN(n_0_0_39) + ); + NAND2_X1_LVT i_0_0_89( + .A1(n_0_0_85), .A2(n_0_0_39), .ZN(n_0_0_38) + ); + MUX2_X1_LVT i_0_0_88( + .A(DWData[7]), .B(mem_wdata[7]), .S(n_0_0_38), .Z(n_0_58) + ); + DFF_X1_LVT \mem_wdata_reg[7] ( + .CK(n_0_76), .D(n_0_58), .Q(mem_wdata[7]), .QN() + ); + MUX2_X1_LVT i_0_0_87( + .A(DWData[6]), .B(mem_wdata[6]), .S(n_0_0_38), .Z(n_0_59) + ); + DFF_X1_LVT \mem_wdata_reg[6] ( + .CK(n_0_76), .D(n_0_59), .Q(mem_wdata[6]), .QN() + ); + MUX2_X1_LVT i_0_0_86( + .A(DWData[5]), .B(mem_wdata[5]), .S(n_0_0_38), .Z(n_0_60) + ); + DFF_X1_LVT \mem_wdata_reg[5] ( + .CK(n_0_76), .D(n_0_60), .Q(mem_wdata[5]), .QN() + ); + MUX2_X1_LVT i_0_0_85( + .A(DWData[4]), .B(mem_wdata[4]), .S(n_0_0_38), .Z(n_0_61) + ); + DFF_X1_LVT \mem_wdata_reg[4] ( + .CK(n_0_76), .D(n_0_61), .Q(mem_wdata[4]), .QN() + ); + MUX2_X1_LVT i_0_0_84( + .A(DWData[3]), .B(mem_wdata[3]), .S(n_0_0_38), .Z(n_0_62) + ); + DFF_X1_LVT \mem_wdata_reg[3] ( + .CK(n_0_76), .D(n_0_62), .Q(mem_wdata[3]), .QN() + ); + MUX2_X1_LVT i_0_0_83( + .A(DWData[2]), .B(mem_wdata[2]), .S(n_0_0_38), .Z(n_0_63) + ); + DFF_X1_LVT \mem_wdata_reg[2] ( + .CK(n_0_76), .D(n_0_63), .Q(mem_wdata[2]), .QN() + ); + MUX2_X1_LVT i_0_0_82( + .A(DWData[1]), .B(mem_wdata[1]), .S(n_0_0_38), .Z(n_0_64) + ); + DFF_X1_LVT \mem_wdata_reg[1] ( + .CK(n_0_76), .D(n_0_64), .Q(mem_wdata[1]), .QN() + ); + MUX2_X1_LVT i_0_0_81( + .A(DWData[0]), .B(mem_wdata[0]), .S(n_0_0_38), .Z(n_0_65) + ); + DFF_X1_LVT \mem_wdata_reg[0] ( + .CK(n_0_76), .D(n_0_65), .Q(mem_wdata[0]), .QN() + ); + MemGen_32_11 RAM( + .chip_en(), .clock(clk), .addr(mem_addr), .rd_data(mem_rdata), .rd_en(n_0), + .wr_en(DWE), .wr_data(mem_wdata) + ); + DFF_X1_LVT \drTmp_reg[31] ( + .CK(n_0_76), .D(mem_rdata[31]), .Q(drTmp[31]), .QN() + ); + AND2_X1_LVT i_0_0_80( + .A1(DWidth[1]), .A2(drTmp[31]), .ZN(n_0_42) + ); + DLH_X1_LVT \DRData[31] ( + .D(n_0_42), .G(n_0_43), .Q(DRData[31]) + ); + DFF_X1_LVT \drTmp_reg[30] ( + .CK(n_0_76), .D(mem_rdata[30]), .Q(drTmp[30]), .QN() + ); + AND2_X1_LVT i_0_0_79( + .A1(DWidth[1]), .A2(drTmp[30]), .ZN(n_0_41) + ); + DLH_X1_LVT \DRData[30] ( + .D(n_0_41), .G(n_0_43), .Q(DRData[30]) + ); + DFF_X1_LVT \drTmp_reg[29] ( + .CK(n_0_76), .D(mem_rdata[29]), .Q(drTmp[29]), .QN() + ); + AND2_X1_LVT i_0_0_78( + .A1(DWidth[1]), .A2(drTmp[29]), .ZN(n_0_40) + ); + DLH_X1_LVT \DRData[29] ( + .D(n_0_40), .G(n_0_43), .Q(DRData[29]) + ); + DFF_X1_LVT \drTmp_reg[28] ( + .CK(n_0_76), .D(mem_rdata[28]), .Q(drTmp[28]), .QN() + ); + AND2_X1_LVT i_0_0_77( + .A1(DWidth[1]), .A2(drTmp[28]), .ZN(n_0_39) + ); + DLH_X1_LVT \DRData[28] ( + .D(n_0_39), .G(n_0_43), .Q(DRData[28]) + ); + DFF_X1_LVT \drTmp_reg[27] ( + .CK(n_0_76), .D(mem_rdata[27]), .Q(drTmp[27]), .QN() + ); + AND2_X1_LVT i_0_0_76( + .A1(DWidth[1]), .A2(drTmp[27]), .ZN(n_0_38) + ); + DLH_X1_LVT \DRData[27] ( + .D(n_0_38), .G(n_0_43), .Q(DRData[27]) + ); + DFF_X1_LVT \drTmp_reg[26] ( + .CK(n_0_76), .D(mem_rdata[26]), .Q(drTmp[26]), .QN() + ); + AND2_X1_LVT i_0_0_75( + .A1(DWidth[1]), .A2(drTmp[26]), .ZN(n_0_37) + ); + DLH_X1_LVT \DRData[26] ( + .D(n_0_37), .G(n_0_43), .Q(DRData[26]) + ); + DFF_X1_LVT \drTmp_reg[25] ( + .CK(n_0_76), .D(mem_rdata[25]), .Q(drTmp[25]), .QN() + ); + AND2_X1_LVT i_0_0_74( + .A1(DWidth[1]), .A2(drTmp[25]), .ZN(n_0_36) + ); + DLH_X1_LVT \DRData[25] ( + .D(n_0_36), .G(n_0_43), .Q(DRData[25]) + ); + DFF_X1_LVT \drTmp_reg[24] ( + .CK(n_0_76), .D(mem_rdata[24]), .Q(drTmp[24]), .QN() + ); + AND2_X1_LVT i_0_0_73( + .A1(DWidth[1]), .A2(drTmp[24]), .ZN(n_0_35) + ); + DLH_X1_LVT \DRData[24] ( + .D(n_0_35), .G(n_0_43), .Q(DRData[24]) + ); + DFF_X1_LVT \drTmp_reg[23] ( + .CK(n_0_76), .D(mem_rdata[23]), .Q(drTmp[23]), .QN() + ); + AND2_X1_LVT i_0_0_72( + .A1(DWidth[1]), .A2(drTmp[23]), .ZN(n_0_34) + ); + DLH_X1_LVT \DRData[23] ( + .D(n_0_34), .G(n_0_43), .Q(DRData[23]) + ); + DFF_X1_LVT \drTmp_reg[22] ( + .CK(n_0_76), .D(mem_rdata[22]), .Q(drTmp[22]), .QN() + ); + AND2_X1_LVT i_0_0_71( + .A1(DWidth[1]), .A2(drTmp[22]), .ZN(n_0_33) + ); + DLH_X1_LVT \DRData[22] ( + .D(n_0_33), .G(n_0_43), .Q(DRData[22]) + ); + DFF_X1_LVT \drTmp_reg[21] ( + .CK(n_0_76), .D(mem_rdata[21]), .Q(drTmp[21]), .QN() + ); + AND2_X1_LVT i_0_0_70( + .A1(DWidth[1]), .A2(drTmp[21]), .ZN(n_0_32) + ); + DLH_X1_LVT \DRData[21] ( + .D(n_0_32), .G(n_0_43), .Q(DRData[21]) + ); + DFF_X1_LVT \drTmp_reg[20] ( + .CK(n_0_76), .D(mem_rdata[20]), .Q(drTmp[20]), .QN() + ); + AND2_X1_LVT i_0_0_69( + .A1(DWidth[1]), .A2(drTmp[20]), .ZN(n_0_31) + ); + DLH_X1_LVT \DRData[20] ( + .D(n_0_31), .G(n_0_43), .Q(DRData[20]) + ); + DFF_X1_LVT \drTmp_reg[19] ( + .CK(n_0_76), .D(mem_rdata[19]), .Q(drTmp[19]), .QN() + ); + AND2_X1_LVT i_0_0_68( + .A1(DWidth[1]), .A2(drTmp[19]), .ZN(n_0_30) + ); + DLH_X1_LVT \DRData[19] ( + .D(n_0_30), .G(n_0_43), .Q(DRData[19]) + ); + DFF_X1_LVT \drTmp_reg[18] ( + .CK(n_0_76), .D(mem_rdata[18]), .Q(drTmp[18]), .QN() + ); + AND2_X1_LVT i_0_0_67( + .A1(DWidth[1]), .A2(drTmp[18]), .ZN(n_0_29) + ); + DLH_X1_LVT \DRData[18] ( + .D(n_0_29), .G(n_0_43), .Q(DRData[18]) + ); + DFF_X1_LVT \drTmp_reg[17] ( + .CK(n_0_76), .D(mem_rdata[17]), .Q(drTmp[17]), .QN() + ); + AND2_X1_LVT i_0_0_66( + .A1(DWidth[1]), .A2(drTmp[17]), .ZN(n_0_28) + ); + DLH_X1_LVT \DRData[17] ( + .D(n_0_28), .G(n_0_43), .Q(DRData[17]) + ); + DFF_X1_LVT \drTmp_reg[16] ( + .CK(n_0_76), .D(mem_rdata[16]), .Q(drTmp[16]), .QN() + ); + AND2_X1_LVT i_0_0_65( + .A1(DWidth[1]), .A2(drTmp[16]), .ZN(n_0_27) + ); + DLH_X1_LVT \DRData[16] ( + .D(n_0_27), .G(n_0_43), .Q(DRData[16]) + ); + NOR2_X1_LVT i_0_0_64( + .A1(n_0_0_91), .A2(n_0_0_87), .ZN(n_0_0_37) + ); + DFF_X1_LVT \drTmp_reg[15] ( + .CK(n_0_76), .D(mem_rdata[15]), .Q(drTmp[15]), .QN() + ); + AOI22_X1_LVT i_0_0_63( + .A1(drTmp[31]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[15]), .ZN(n_0_0_36) + ); + INV_X1_LVT i_0_0_62( + .A(n_0_0_36), .ZN(n_0_26) + ); + DLH_X1_LVT \DRData[15] ( + .D(n_0_26), .G(n_0_43), .Q(DRData[15]) + ); + DFF_X1_LVT \drTmp_reg[14] ( + .CK(n_0_76), .D(mem_rdata[14]), .Q(drTmp[14]), .QN() + ); + AOI22_X1_LVT i_0_0_61( + .A1(drTmp[30]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[14]), .ZN(n_0_0_35) + ); + INV_X1_LVT i_0_0_60( + .A(n_0_0_35), .ZN(n_0_25) + ); + DLH_X1_LVT \DRData[14] ( + .D(n_0_25), .G(n_0_43), .Q(DRData[14]) + ); + DFF_X1_LVT \drTmp_reg[13] ( + .CK(n_0_76), .D(mem_rdata[13]), .Q(drTmp[13]), .QN() + ); + AOI22_X1_LVT i_0_0_59( + .A1(drTmp[29]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[13]), .ZN(n_0_0_34) + ); + INV_X1_LVT i_0_0_58( + .A(n_0_0_34), .ZN(n_0_24) + ); + DLH_X1_LVT \DRData[13] ( + .D(n_0_24), .G(n_0_43), .Q(DRData[13]) + ); + DFF_X1_LVT \drTmp_reg[12] ( + .CK(n_0_76), .D(mem_rdata[12]), .Q(drTmp[12]), .QN() + ); + AOI22_X1_LVT i_0_0_57( + .A1(drTmp[28]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[12]), .ZN(n_0_0_33) + ); + INV_X1_LVT i_0_0_56( + .A(n_0_0_33), .ZN(n_0_23) + ); + DLH_X1_LVT \DRData[12] ( + .D(n_0_23), .G(n_0_43), .Q(DRData[12]) + ); + DFF_X1_LVT \drTmp_reg[11] ( + .CK(n_0_76), .D(mem_rdata[11]), .Q(drTmp[11]), .QN() + ); + AOI22_X1_LVT i_0_0_55( + .A1(drTmp[27]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[11]), .ZN(n_0_0_32) + ); + INV_X1_LVT i_0_0_54( + .A(n_0_0_32), .ZN(n_0_22) + ); + DLH_X1_LVT \DRData[11] ( + .D(n_0_22), .G(n_0_43), .Q(DRData[11]) + ); + DFF_X1_LVT \drTmp_reg[10] ( + .CK(n_0_76), .D(mem_rdata[10]), .Q(drTmp[10]), .QN() + ); + AOI22_X1_LVT i_0_0_53( + .A1(drTmp[26]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[10]), .ZN(n_0_0_31) + ); + INV_X1_LVT i_0_0_52( + .A(n_0_0_31), .ZN(n_0_21) + ); + DLH_X1_LVT \DRData[10] ( + .D(n_0_21), .G(n_0_43), .Q(DRData[10]) + ); + DFF_X1_LVT \drTmp_reg[9] ( + .CK(n_0_76), .D(mem_rdata[9]), .Q(drTmp[9]), .QN() + ); + AOI22_X1_LVT i_0_0_51( + .A1(drTmp[25]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[9]), .ZN(n_0_0_30) + ); + INV_X1_LVT i_0_0_50( + .A(n_0_0_30), .ZN(n_0_20) + ); + DLH_X1_LVT \DRData[9] ( + .D(n_0_20), .G(n_0_43), .Q(DRData[9]) + ); + DFF_X1_LVT \drTmp_reg[8] ( + .CK(n_0_76), .D(mem_rdata[8]), .Q(drTmp[8]), .QN() + ); + AOI22_X1_LVT i_0_0_49( + .A1(drTmp[24]), .A2(n_0_0_78), .B1(n_0_0_37), .B2(drTmp[8]), .ZN(n_0_0_29) + ); + INV_X1_LVT i_0_0_48( + .A(n_0_0_29), .ZN(n_0_19) + ); + DLH_X1_LVT \DRData[8] ( + .D(n_0_19), .G(n_0_43), .Q(DRData[8]) + ); + AOI22_X1_LVT i_0_0_46( + .A1(drTmp[31]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[15]), .ZN(n_0_0_27) + ); + AOI211_X1_LVT i_0_0_47( + .A(DAddr[1]), .B(n_0_0_83), .C1(n_0_0_94), .C2(DWidth[1]), .ZN(n_0_0_28) + ); + DFF_X1_LVT \drTmp_reg[7] ( + .CK(n_0_76), .D(mem_rdata[7]), .Q(drTmp[7]), .QN() + ); + AOI22_X1_LVT i_0_0_45( + .A1(drTmp[23]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[7]), .ZN(n_0_0_26) + ); + NAND2_X1_LVT i_0_0_44( + .A1(n_0_0_27), .A2(n_0_0_26), .ZN(n_0_18) + ); + DLH_X1_LVT \DRData[7] ( + .D(n_0_18), .G(n_0_43), .Q(DRData[7]) + ); + AOI22_X1_LVT i_0_0_43( + .A1(drTmp[30]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[14]), .ZN(n_0_0_25) + ); + DFF_X1_LVT \drTmp_reg[6] ( + .CK(n_0_76), .D(mem_rdata[6]), .Q(drTmp[6]), .QN() + ); + AOI22_X1_LVT i_0_0_42( + .A1(drTmp[22]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[6]), .ZN(n_0_0_24) + ); + NAND2_X1_LVT i_0_0_41( + .A1(n_0_0_25), .A2(n_0_0_24), .ZN(n_0_17) + ); + DLH_X1_LVT \DRData[6] ( + .D(n_0_17), .G(n_0_43), .Q(DRData[6]) + ); + AOI22_X1_LVT i_0_0_40( + .A1(drTmp[29]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[13]), .ZN(n_0_0_23) + ); + DFF_X1_LVT \drTmp_reg[5] ( + .CK(n_0_76), .D(mem_rdata[5]), .Q(drTmp[5]), .QN() + ); + AOI22_X1_LVT i_0_0_39( + .A1(drTmp[21]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[5]), .ZN(n_0_0_22) + ); + NAND2_X1_LVT i_0_0_38( + .A1(n_0_0_23), .A2(n_0_0_22), .ZN(n_0_16) + ); + DLH_X1_LVT \DRData[5] ( + .D(n_0_16), .G(n_0_43), .Q(DRData[5]) + ); + AOI22_X1_LVT i_0_0_37( + .A1(drTmp[28]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[12]), .ZN(n_0_0_21) + ); + DFF_X1_LVT \drTmp_reg[4] ( + .CK(n_0_76), .D(mem_rdata[4]), .Q(drTmp[4]), .QN() + ); + AOI22_X1_LVT i_0_0_36( + .A1(drTmp[20]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[4]), .ZN(n_0_0_20) + ); + NAND2_X1_LVT i_0_0_35( + .A1(n_0_0_21), .A2(n_0_0_20), .ZN(n_0_15) + ); + DLH_X1_LVT \DRData[4] ( + .D(n_0_15), .G(n_0_43), .Q(DRData[4]) + ); + AOI22_X1_LVT i_0_0_34( + .A1(drTmp[27]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[11]), .ZN(n_0_0_19) + ); + DFF_X1_LVT \drTmp_reg[3] ( + .CK(n_0_76), .D(mem_rdata[3]), .Q(drTmp[3]), .QN() + ); + AOI22_X1_LVT i_0_0_33( + .A1(drTmp[19]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[3]), .ZN(n_0_0_18) + ); + NAND2_X1_LVT i_0_0_32( + .A1(n_0_0_19), .A2(n_0_0_18), .ZN(n_0_14) + ); + DLH_X1_LVT \DRData[3] ( + .D(n_0_14), .G(n_0_43), .Q(DRData[3]) + ); + AOI22_X1_LVT i_0_0_31( + .A1(drTmp[26]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[10]), .ZN(n_0_0_17) + ); + DFF_X1_LVT \drTmp_reg[2] ( + .CK(n_0_76), .D(mem_rdata[2]), .Q(drTmp[2]), .QN() + ); + AOI22_X1_LVT i_0_0_30( + .A1(drTmp[18]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[2]), .ZN(n_0_0_16) + ); + NAND2_X1_LVT i_0_0_29( + .A1(n_0_0_17), .A2(n_0_0_16), .ZN(n_0_13) + ); + DLH_X1_LVT \DRData[2] ( + .D(n_0_13), .G(n_0_43), .Q(DRData[2]) + ); + AOI22_X1_LVT i_0_0_28( + .A1(drTmp[25]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[9]), .ZN(n_0_0_15) + ); + DFF_X1_LVT \drTmp_reg[1] ( + .CK(n_0_76), .D(mem_rdata[1]), .Q(drTmp[1]), .QN() + ); + AOI22_X1_LVT i_0_0_27( + .A1(drTmp[17]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[1]), .ZN(n_0_0_14) + ); + NAND2_X1_LVT i_0_0_26( + .A1(n_0_0_15), .A2(n_0_0_14), .ZN(n_0_12) + ); + DLH_X1_LVT \DRData[1] ( + .D(n_0_12), .G(n_0_43), .Q(DRData[1]) + ); + AOI22_X1_LVT i_0_0_25( + .A1(drTmp[24]), .A2(n_0_0_82), .B1(n_0_0_50), .B2(drTmp[8]), .ZN(n_0_0_13) + ); + DFF_X1_LVT \drTmp_reg[0] ( + .CK(n_0_76), .D(mem_rdata[0]), .Q(drTmp[0]), .QN() + ); + AOI22_X1_LVT i_0_0_24( + .A1(drTmp[16]), .A2(n_0_0_28), .B1(n_0_0_39), .B2(drTmp[0]), .ZN(n_0_0_12) + ); + NAND2_X1_LVT i_0_0_23( + .A1(n_0_0_13), .A2(n_0_0_12), .ZN(n_0_11) + ); + DLH_X1_LVT \DRData[0] ( + .D(n_0_11), .G(n_0_43), .Q(DRData[0]) + ); + DFF_X1_LVT \IRData_reg[31] ( + .CK(clk), .D(mem_rdata[31]), .Q(IRData[31]), .QN() + ); + DFF_X1_LVT \IRData_reg[30] ( + .CK(clk), .D(mem_rdata[30]), .Q(IRData[30]), .QN() + ); + DFF_X1_LVT \IRData_reg[29] ( + .CK(clk), .D(mem_rdata[29]), .Q(IRData[29]), .QN() + ); + DFF_X1_LVT \IRData_reg[28] ( + .CK(clk), .D(mem_rdata[28]), .Q(IRData[28]), .QN() + ); + DFF_X1_LVT \IRData_reg[27] ( + .CK(clk), .D(mem_rdata[27]), .Q(IRData[27]), .QN() + ); + DFF_X1_LVT \IRData_reg[26] ( + .CK(clk), .D(mem_rdata[26]), .Q(IRData[26]), .QN() + ); + DFF_X1_LVT \IRData_reg[25] ( + .CK(clk), .D(mem_rdata[25]), .Q(IRData[25]), .QN() + ); + DFF_X1_LVT \IRData_reg[24] ( + .CK(clk), .D(mem_rdata[24]), .Q(IRData[24]), .QN() + ); + DFF_X1_LVT \IRData_reg[23] ( + .CK(clk), .D(mem_rdata[23]), .Q(IRData[23]), .QN() + ); + DFF_X1_LVT \IRData_reg[22] ( + .CK(clk), .D(mem_rdata[22]), .Q(IRData[22]), .QN() + ); + DFF_X1_LVT \IRData_reg[21] ( + .CK(clk), .D(mem_rdata[21]), .Q(IRData[21]), .QN() + ); + DFF_X1_LVT \IRData_reg[20] ( + .CK(clk), .D(mem_rdata[20]), .Q(IRData[20]), .QN() + ); + DFF_X1_LVT \IRData_reg[19] ( + .CK(clk), .D(mem_rdata[19]), .Q(IRData[19]), .QN() + ); + DFF_X1_LVT \IRData_reg[18] ( + .CK(clk), .D(mem_rdata[18]), .Q(IRData[18]), .QN() + ); + DFF_X1_LVT \IRData_reg[17] ( + .CK(clk), .D(mem_rdata[17]), .Q(IRData[17]), .QN() + ); + DFF_X1_LVT \IRData_reg[16] ( + .CK(clk), .D(mem_rdata[16]), .Q(IRData[16]), .QN() + ); + DFF_X1_LVT \IRData_reg[15] ( + .CK(clk), .D(mem_rdata[15]), .Q(IRData[15]), .QN() + ); + DFF_X1_LVT \IRData_reg[14] ( + .CK(clk), .D(mem_rdata[14]), .Q(IRData[14]), .QN() + ); + DFF_X1_LVT \IRData_reg[13] ( + .CK(clk), .D(mem_rdata[13]), .Q(IRData[13]), .QN() + ); + DFF_X1_LVT \IRData_reg[12] ( + .CK(clk), .D(mem_rdata[12]), .Q(IRData[12]), .QN() + ); + DFF_X1_LVT \IRData_reg[11] ( + .CK(clk), .D(mem_rdata[11]), .Q(IRData[11]), .QN() + ); + DFF_X1_LVT \IRData_reg[10] ( + .CK(clk), .D(mem_rdata[10]), .Q(IRData[10]), .QN() + ); + DFF_X1_LVT \IRData_reg[9] ( + .CK(clk), .D(mem_rdata[9]), .Q(IRData[9]), .QN() + ); + DFF_X1_LVT \IRData_reg[8] ( + .CK(clk), .D(mem_rdata[8]), .Q(IRData[8]), .QN() + ); + DFF_X1_LVT \IRData_reg[7] ( + .CK(clk), .D(mem_rdata[7]), .Q(IRData[7]), .QN() + ); + DFF_X1_LVT \IRData_reg[6] ( + .CK(clk), .D(mem_rdata[6]), .Q(IRData[6]), .QN() + ); + DFF_X1_LVT \IRData_reg[5] ( + .CK(clk), .D(mem_rdata[5]), .Q(IRData[5]), .QN() + ); + DFF_X1_LVT \IRData_reg[4] ( + .CK(clk), .D(mem_rdata[4]), .Q(IRData[4]), .QN() + ); + DFF_X1_LVT \IRData_reg[3] ( + .CK(clk), .D(mem_rdata[3]), .Q(IRData[3]), .QN() + ); + DFF_X1_LVT \IRData_reg[2] ( + .CK(clk), .D(mem_rdata[2]), .Q(IRData[2]), .QN() + ); + DFF_X1_LVT \IRData_reg[1] ( + .CK(clk), .D(mem_rdata[1]), .Q(IRData[1]), .QN() + ); + DFF_X1_LVT \IRData_reg[0] ( + .CK(clk), .D(mem_rdata[0]), .Q(IRData[0]), .QN() + ); +endmodule + +module reg_file(Rs1, Rs2, Rd, RRs1, RRs2, WRd, WrReg, reset, clk, dftIn, ts_intno31, + ts_no1050, ts_no1051, ts_no1053, ts_no1054, ts_extsi1226, ts_extsi1227, + ts_extsi1228); + input [31:0] WRd; + input [4:0] Rs1, Rs2, Rd; + input WrReg, reset, clk, dftIn, ts_extsi1227, ts_extsi1228, ts_intno31, + ts_extsi1226; + output [31:0] RRs1, RRs2; + output ts_no1050, ts_no1051, ts_no1053, ts_no1054; + + wire [31:0] registers_1__ap, registers_2__ap, registers_3__ap, + registers_4__ap, registers_5__ap, registers_6__ap, + registers_7__ap, registers_8__ap, registers_9__ap, + registers_10__ap, registers_11__ap, registers_12__ap, + registers_13__ap, registers_14__ap, registers_15__ap, + registers_16__ap, registers_17__ap, registers_18__ap, + registers_19__ap, registers_20__ap, registers_21__ap, + registers_22__ap, registers_23__ap, registers_24__ap, + registers_25__ap, registers_26__ap, registers_27__ap, + registers_28__ap, registers_29__ap, registers_30__ap, + registers_31__ap, registers; + wire n_0_0, n_0_32, n_0_33, n_0_34, n_0_35, n_0_36, n_0_37, n_0_38, n_0_39, + n_0_40, n_0_41, n_0_42, n_0_43, n_0_44, n_0_45, n_0_46, n_0_47, n_0_48, + n_0_49, n_0_50, n_0_51, n_0_52, n_0_53, n_0_54, n_0_55, n_0_56, n_0_57, + n_0_58, n_0_59, n_0_60, n_0_61, n_0_31, n_0_30, n_0_29, n_0_28, n_0_27, + n_0_26, n_0_25, n_0_24, n_0_0_0, n_0_0_1, n_0_23, n_0_22, n_0_21, + n_0_20, n_0_19, n_0_18, n_0_17, n_0_16, n_0_0_2, n_0_0_3, n_0_15, + n_0_14, n_0_13, n_0_12, n_0_11, n_0_10, n_0_9, n_0_8, n_0_0_4, n_0_0_5, + n_0_7, n_0_0_6, n_0_6, n_0_0_7, n_0_5, n_0_0_8, n_0_4, n_0_0_9, + n_0_0_10, n_0_3, n_0_0_11, n_0_2, n_0_0_12, n_0_1, n_0_0_13, n_0_0_14, + n_0_0_15, n_0_0_16, n_0_0_17, n_0_0_18, n_0_0_19, n_0_0_20, n_1_0_0, + n_1_0_1, n_1_0_2, n_1_0_3, n_1_0_4, n_1_0_5, n_1_0_6, n_1_0_7, n_1_0_8, + n_1_0_9, n_1_0_10, n_1_0_11, n_1_0_12, n_1_0_13, n_1_0_14, n_1_0_15, + n_1_0_16, n_1_0_17, n_1_0_18, n_1_0_19, n_1_0_20, n_1_0_21, n_1_0_22, + n_1_0_23, n_1_0_24, n_1_0_25, n_1_0_26, n_1_0_27, n_1_0_28, n_1_0_29, + n_1_0_30, n_1_0_31, n_1_0_32, n_1_0_33, n_1_0_34, n_1_0_35, n_1_0_36, + n_1_0_37, n_1_0_38, n_1_0_39, n_1_0_40, n_1_0_41, n_1_0_42, n_1_0_43, + n_1_0_44, n_1_0_45, n_1_0_46, n_1_0_47, n_1_0_48, n_1_0_49, n_1_0_50, + n_1_0_51, n_1_0_52, n_1_0_53, n_1_0_54, n_1_0_55, n_1_0_56, n_1_0_57, + n_1_0_58, n_1_0_59, n_1_0_60, n_1_0_61, n_1_0_62, n_1_0_63, n_1_0_64, + n_1_0_65, n_1_0_66, n_1_0_67, n_1_0_68, n_1_0_69, n_1_0_70, n_1_0_71, + n_1_0_72, n_1_0_73, n_1_0_74, n_1_0_75, n_1_0_76, n_1_0_77, n_1_0_78, + n_1_0_79, n_1_0_80, n_1_0_81, n_1_0_82, n_1_0_83, n_1_0_84, n_1_0_85, + n_1_0_86, n_1_0_87, n_1_0_88, n_1_0_89, n_1_0_90, n_1_0_91, n_1_0_92, + n_1_0_93, n_1_0_94, n_1_0_95, n_1_0_96, n_1_0_97, n_1_0_98, n_1_0_99, + n_1_0_100, n_1_0_101, n_1_0_102, n_1_0_103, n_1_0_104, n_1_0_105, + n_1_0_106, n_1_0_107, n_1_0_108, n_1_0_109, n_1_0_110, n_1_0_111, + n_1_0_112, n_1_0_113, n_1_0_114, n_1_0_115, n_1_0_116, n_1_0_117, + n_1_0_118, n_1_0_119, n_1_0_120, n_1_0_121, n_1_0_122, n_1_0_123, + n_1_0_124, n_1_0_125, n_1_0_126, n_1_0_127, n_1_0_128, n_1_0_129, + n_1_0_130, n_1_0_131, n_1_0_132, n_1_0_133, n_1_0_134, n_1_0_135, + n_1_0_136, n_1_0_137, n_1_0_138, n_1_0_139, n_1_0_140, n_1_0_141, + n_1_0_142, n_1_0_143, n_1_0_144, n_1_0_145, n_1_0_146, n_1_0_147, + n_1_0_148, n_1_0_149, n_1_0_150, n_1_0_151, n_1_0_152, n_1_0_153, + n_1_0_154, n_1_0_155, n_1_0_156, n_1_0_157, n_1_0_158, n_1_0_159, + n_1_0_160, n_1_0_161, n_1_0_162, n_1_0_163, n_1_0_164, n_1_0_165, + n_1_0_166, n_1_0_167, n_1_0_168, n_1_0_169, n_1_0_170, n_1_0_171, + n_1_0_172, n_1_0_173, n_1_0_174, n_1_0_175, n_1_0_176, n_1_0_177, + n_1_0_178, n_1_0_179, n_1_0_180, n_1_0_181, n_1_0_182, n_1_0_183, + n_1_0_184, n_1_0_185, n_1_0_186, n_1_0_187, n_1_0_188, n_1_0_189, + n_1_0_190, n_1_0_191, n_1_0_192, n_1_0_193, n_1_0_194, n_1_0_195, + n_1_0_196, n_1_0_197, n_1_0_198, n_1_0_199, n_1_0_200, n_1_0_201, + n_1_0_202, n_1_0_203, n_1_0_204, n_1_0_205, n_1_0_206, n_1_0_207, + n_1_0_208, n_1_0_209, n_1_0_210, n_1_0_211, n_1_0_212, n_1_0_213, + n_1_0_214, n_1_0_215, n_1_0_216, n_1_0_217, n_1_0_218, n_1_0_219, + n_1_0_220, n_1_0_221, n_1_0_222, n_1_0_223, n_1_0_224, n_1_0_225, + n_1_0_226, n_1_0_227, n_1_0_228, n_1_0_229, n_1_0_230, n_1_0_231, + n_1_0_232, n_1_0_233, n_1_0_234, n_1_0_235, n_1_0_236, n_1_0_237, + n_1_0_238, n_1_0_239, n_1_0_240, n_1_0_241, n_1_0_242, n_1_0_243, + n_1_0_244, n_1_0_245, n_1_0_246, n_1_0_247, n_1_0_248, n_1_0_249, + n_1_0_250, n_1_0_251, n_1_0_252, n_1_0_253, n_1_0_254, n_1_0_255, + n_1_0_256, n_1_0_257, n_1_0_258, n_1_0_259, n_1_0_260, n_1_0_261, + n_1_0_262, n_1_0_263, n_1_0_264, n_1_0_265, n_1_0_266, n_1_0_267, + n_1_0_268, n_1_0_269, n_1_0_270, n_1_0_271, n_1_0_272, n_1_0_273, + n_1_0_274, n_1_0_275, n_1_0_276, n_1_0_277, n_1_0_278, n_1_0_279, + n_1_0_280, n_1_0_281, n_1_0_282, n_1_0_283, n_1_0_284, n_1_0_285, + n_1_0_286, n_1_0_287, n_1_0_288, n_1_0_289, n_1_0_290, n_1_0_291, + n_1_0_292, n_1_0_293, n_1_0_294, n_1_0_295, n_1_0_296, n_1_0_297, + n_1_0_298, n_1_0_299, n_1_0_300, n_1_0_301, n_1_0_302, n_1_0_303, + n_1_0_304, n_1_0_305, n_1_0_306, n_1_0_307, n_1_0_308, n_1_0_309, + n_1_0_310, n_1_0_311, n_1_0_312, n_1_0_313, n_1_0_314, n_1_0_315, + n_1_0_316, n_1_0_317, n_1_0_318, n_1_0_319, n_1_0_320, n_1_0_321, + n_1_0_322, n_1_0_323, n_1_0_324, n_1_0_325, n_1_0_326, n_1_0_327, + n_1_0_328, n_1_0_329, n_1_0_330, n_1_0_331, n_1_0_332, n_1_0_333, + n_1_0_334, n_1_0_335, n_1_0_336, n_1_0_337, n_1_0_338, n_1_0_339, + n_1_0_340, n_1_0_341, n_1_0_342, n_1_0_343, n_1_0_344, n_1_0_345, + n_1_0_346, n_1_0_347, n_1_0_348, n_1_0_349, n_1_0_350, n_1_0_351, + n_1_0_352, n_1_0_353, n_1_0_354, n_1_0_355, n_1_0_356, n_1_0_357, + n_1_0_358, n_1_0_359, n_1_0_360, n_1_0_361, n_1_0_362, n_1_0_363, + n_1_0_364, n_1_0_365, n_1_0_366, n_1_0_367, n_1_0_368, n_1_0_369, + n_1_0_370, n_1_0_371, n_1_0_372, n_1_0_373, n_1_0_374, n_1_0_375, + n_1_0_376, n_1_0_377, n_1_0_378, n_1_0_379, n_1_0_380, n_1_0_381, + n_1_0_382, n_1_0_383, n_1_0_384, n_1_0_385, n_1_0_386, n_1_0_387, + n_1_0_388, n_1_0_389, n_1_0_390, n_1_0_391, n_1_0_392, n_1_0_393, + n_1_0_394, n_1_0_395, n_1_0_396, n_1_0_397, n_1_0_398, n_1_0_399, + n_1_0_400, n_1_0_401, n_1_0_402, n_1_0_403, n_1_0_404, n_1_0_405, + n_1_0_406, n_1_0_407, n_1_0_408, n_1_0_409, n_1_0_410, n_1_0_411, + n_1_0_412, n_1_0_413, n_1_0_414, n_1_0_415, n_1_0_416, n_1_0_417, + n_1_0_418, n_1_0_419, n_1_0_420, n_1_0_421, n_1_0_422, n_1_0_423, + n_1_0_424, n_1_0_425, n_1_0_426, n_1_0_427, n_1_0_428, n_1_0_429, + n_1_0_430, n_1_0_431, n_1_0_432, n_1_0_433, n_1_0_434, n_1_0_435, + n_1_0_436, n_1_0_437, n_1_0_438, n_1_0_439, n_1_0_440, n_1_0_441, + n_1_0_442, n_1_0_443, n_1_0_444, n_1_0_445, n_1_0_446, n_1_0_447, + n_1_0_448, n_1_0_449, n_1_0_450, n_1_0_451, n_1_0_452, n_1_0_453, + n_1_0_454, n_1_0_455, n_1_0_456, n_1_0_457, n_1_0_458, n_1_0_459, + n_1_0_460, n_1_0_461, n_1_0_462, n_1_0_463, n_1_0_464, n_1_0_465, + n_1_0_466, n_1_0_467, n_1_0_468, n_1_0_469, n_1_0_470, n_1_0_471, + n_1_0_472, n_1_0_473, n_1_0_474, n_1_0_475, n_1_0_476, n_1_0_477, + n_1_0_478, n_1_0_479, n_1_0_480, n_1_0_481, n_1_0_482, n_1_0_483, + n_1_0_484, n_1_0_485, n_1_0_486, n_1_0_487, n_1_0_488, n_1_0_489, + n_1_0_490, n_1_0_491, n_1_0_492, n_1_0_493, n_1_0_494, n_1_0_495, + n_1_0_496, n_1_0_497, n_1_0_498, n_1_0_499, n_1_0_500, n_1_0_501, + n_1_0_502, n_1_0_503, n_1_0_504, n_1_0_505, n_1_0_506, n_1_0_507, + n_1_0_508, n_1_0_509, n_1_0_510, n_1_0_511, n_1_0_512, n_1_0_513, + n_1_0_514, n_1_0_515, n_1_0_516, n_1_0_517, n_1_0_518, n_1_0_519, + n_1_0_520, n_1_0_521, n_1_0_522, n_1_0_523, n_1_0_524, n_1_0_525, + n_1_0_526, n_1_0_527, n_1_0_528, n_1_0_529, n_1_0_530, n_1_0_531, + n_1_0_532, n_1_0_533, n_1_0_534, n_1_0_535, n_1_0_536, n_1_0_537, + n_1_0_538, n_1_0_539, n_1_0_540, n_1_0_541, n_1_0_542, n_1_0_543, + n_1_0_544, n_1_0_545, n_1_0_546, n_1_0_547, n_1_0_548, n_1_0_549, + n_1_0_550, n_1_0_551, n_1_0_552, n_1_0_553, n_1_0_554, n_1_0_555, + n_1_0_556, n_1_0_557, n_1_0_558, n_1_0_559, n_1_0_560, n_1_0_561, + n_1_0_562, n_1_0_563, n_1_0_564, n_1_0_565, n_1_0_566, n_1_0_567, + n_1_0_568, n_1_0_569, n_1_0_570, n_1_0_571, n_1_0_572, n_1_0_573, + n_1_0_574, n_1_0_575, n_1_0_576, n_1_0_577, n_1_0_578, n_1_0_579, + n_1_0_580, n_1_0_581, n_1_0_582, n_1_0_583, n_1_0_584, n_1_0_585, + n_1_0_586, n_1_0_587, n_1_0_588, n_1_0_589, n_1_0_590, n_1_0_591, + n_1_0_592, n_1_0_593, n_1_0_594, n_1_0_595, n_1_0_596, n_1_0_597, + n_1_0_598, n_1_0_599, n_1_0_600, n_1_0_601, n_1_0_602, n_1_0_603, + n_1_0_604, n_1_0_605, n_1_0_606, n_1_0_607, n_1_0_608, n_1_0_609, + n_1_0_610, n_1_0_611, n_1_0_612, n_1_0_613, n_1_0_614, n_1_0_615, + n_1_0_616, n_1_0_617, n_1_0_618, n_1_0_619, n_1_0_620, n_1_0_621, + n_1_0_622, n_1_0_623, n_1_0_624, n_1_0_625, n_1_0_626, n_1_0_627, + n_1_0_628, n_1_0_629, n_1_0_630, n_1_0_631, n_1_0_632, n_1_0_633, + n_1_0_634, n_1_0_635, n_1_0_636, n_1_0_637, n_1_0_638, n_1_0_639, + n_1_0_640, n_1_0_641, n_1_0_642, n_1_0_643, n_1_0_644, n_1_0_645, + n_1_0_646, n_1_0_647, n_1_0_648, n_1_0_649, n_1_0_650, n_1_0_651, + n_1_0_652, n_1_0_653, n_1_0_654, n_1_0_655, n_1_0_656, n_1_0_657, + n_1_0_658, n_1_0_659, n_1_0_660, n_1_0_661, n_1_0_662, n_1_0_663, + n_1_0_664, n_1_0_665, n_1_0_666, n_1_0_667, n_1_0_668, n_1_0_669, + n_1_0_670, n_1_0_671, n_1_0_672, n_1_0_673, n_1_0_674, n_1_0_675, + n_1_0_676, n_1_0_677, n_1_0_678, n_1_0_679, n_1_0_680, n_1_0_681, + n_1_0_682, n_1_0_683, n_1_0_684, n_1_0_685, n_1_0_686, n_1_0_687, + n_1_0_688, n_1_0_689, n_1_0_690, n_1_0_691, n_1_0_692, n_1_0_693, + n_1_0_694, n_1_0_695, n_1_0_696, n_1_0_697, n_1_0_698, n_1_0_699, + n_1_0_700, n_1_0_701, n_1_0_702, n_1_0_703, n_1_0_704, n_1_0_705, + n_1_0_706, n_1_0_707, n_1_0_708, n_1_0_709, n_1_0_710, n_1_0_711, + n_1_0_712, n_1_0_713, n_1_0_714, n_1_0_715, n_1_0_716, n_1_0_717, + n_1_0_718, n_1_0_719, n_1_0_720, n_1_0_721, n_1_0_722, n_1_0_723, + n_1_0_724, n_1_0_725, n_1_0_726, n_1_0_727, n_1_0_728, n_1_0_729, + n_1_0_730, n_1_0_731, n_1_0_732, n_1_0_733, n_1_0_734, n_1_0_735, + n_1_0_736, n_1_0_737, n_1_0_738, n_1_0_739, n_1_0_740, n_1_0_741, + n_1_0_742, n_1_0_743, n_1_0_744, n_1_0_745, n_1_0_746, n_1_0_747, + n_1_0_748, n_1_0_749, n_1_0_750, n_1_0_751, n_1_0_752, n_1_0_753, + n_1_0_754, n_1_0_755, n_1_0_756, n_1_0_757, n_1_0_758, n_1_0_759, + n_1_0_760, n_1_0_761, n_1_0_762, n_1_0_763, n_1_0_764, n_1_0_765, + n_1_0_766, n_1_0_767, n_1_0_768, n_1_0_769, n_1_0_770, n_1_0_771, + n_1_0_772, n_1_0_773, n_1_0_774, n_1_0_775, n_1_0_776, n_1_0_777, + n_1_0_778, n_1_0_779, n_1_0_780, n_1_0_781, n_1_0_782, n_1_0_783, + n_1_0_784, n_1_0_785, n_1_0_786, n_1_0_787, n_1_0_788, n_1_0_789, + n_1_0_790, n_1_0_791, n_1_0_792, n_1_0_793, n_1_0_794, n_1_0_795, + n_1_0_796, n_1_0_797, n_1_0_798, n_1_0_799, n_1_0_800, n_1_0_801, + n_1_0_802, n_1_0_803, n_1_0_804, n_1_0_805, n_1_0_806, n_1_0_807, + n_1_0_808, n_1_0_809, n_1_0_810, n_1_0_811, n_1_0_812, n_1_0_813, + n_1_0_814, n_1_0_815, n_1_0_816, n_1_0_817, n_1_0_818, n_1_0_819, + n_1_0_820, n_1_0_821, n_1_0_822, n_1_0_823, n_1_0_824, n_1_0_825, + n_1_0_826, n_1_0_827, n_1_0_828, n_1_0_829, n_1_0_830, n_1_0_831, + n_1_0_832, n_1_0_833, n_1_0_834, n_1_0_835, n_1_0_836, n_1_0_837, + n_1_0_838, n_1_0_839, n_1_0_840, n_1_0_841, n_1_0_842, n_1_0_843, + n_1_0_844, n_1_0_845, n_1_0_846, n_1_0_847, n_1_0_848, n_1_0_849, + n_1_0_850, n_1_0_851, n_1_0_852, n_1_0_853, n_1_0_854, n_1_0_855, + n_1_0_856, n_1_0_857, n_1_0_858, n_1_0_859, n_1_0_860, n_1_0_861, + n_1_0_862, n_1_0_863, n_1_0_864, n_1_0_865, n_1_0_866, n_1_0_867, + n_1_0_868, n_1_0_869, n_1_0_870, n_1_0_871, n_1_0_872, n_1_0_873, + n_1_0_874, n_1_0_875, n_1_0_876, n_1_0_877, n_1_0_878, n_1_0_879, + n_1_0_880, n_1_0_881, n_1_0_882, n_1_0_883, n_1_0_884, n_1_0_885, + n_1_0_886, n_1_0_887, n_1_0_888, n_1_0_889, n_1_0_890, n_1_0_891, + n_1_0_892, n_1_0_893, n_1_0_894, n_1_0_895, n_1_0_896, n_1_0_897, + n_1_0_898, n_1_0_899, n_1_0_900, n_1_0_901, n_1_0_902, n_1_0_903, + n_1_0_904, n_1_0_905, n_1_0_906, n_1_0_907, n_1_0_908, n_1_0_909, + n_1_0_910, n_1_0_911, n_1_0_912, n_1_0_913, n_1_0_914, n_1_0_915, + n_1_0_916, n_1_0_917, n_1_0_918, n_1_0_919, n_1_0_920, n_1_0_921, + n_1_0_922, n_1_0_923, n_1_0_924, n_1_0_925, n_1_0_926, n_1_0_927, + n_1_0_928, n_1_0_929, n_1_0_930, n_1_0_931, n_1_0_932, n_1_0_933, + n_1_0_934, n_1_0_935, n_1_0_936, n_1_0_937, n_1_0_938, n_1_0_939, + n_1_0_940, n_1_0_941, n_1_0_942, n_1_0_943, n_1_0_944, n_1_0_945, + n_1_0_946, n_1_0_947, n_1_0_948, n_1_0_949, n_1_0_950, n_1_0_951, + n_1_0_952, n_1_0_953, n_1_0_954, n_1_0_955, n_1_0_956, n_1_0_957, + n_1_0_958, n_1_0_959, n_1_0_960, n_1_0_961, n_1_0_962, n_1_0_963, + n_1_0_964, n_1_0_965, n_1_0_966, n_1_0_967, n_1_0_968, n_1_0_969, + n_1_0_970, n_1_0_971, n_1_0_972, n_1_0_973, n_1_0_974, n_1_0_975, + n_1_0_976, n_1_0_977, n_1_0_978, n_1_0_979, n_1_0_980, n_1_0_981, + n_1_0_982, n_1_0_983, n_1_0_984, n_1_0_985, n_1_0_986, n_1_0_987, + n_1_0_988, n_1_0_989, n_1_0_990, n_1_0_991, n_1_0_992, n_1_0_993, + n_1_0_994, n_1_0_995, n_1_0_996, n_1_0_997, n_1_0_998, n_1_0_999, + n_1_0_1000, n_1_0_1001, n_1_0_1002, n_1_0_1003, n_1_0_1004, n_1_0_1005, + n_1_0_1006, n_1_0_1007, n_1_0_1008, n_1_0_1009, n_1_0_1010, n_1_0_1011, + n_1_0_1012, n_1_0_1013, n_1_0_1014, n_1_0_1015, n_1_0_1016, n_1_0_1017, + n_1_0_1018, n_1_0_1019, n_1_0_1020, n_1_0_1021, n_1_0_1022, n_1_0_1023, + n_1_0_1024, n_1_0_1025, n_1_0_1026, n_1_0_1027, n_1_0_1028, n_1_0_1029, + n_1_0_1030, n_1_0_1031, n_1_0_1032, n_1_0_1033, n_1_0_1034, n_1_0_1035, + n_1_0_1036, n_1_0_1037, n_1_0_1038, n_1_0_1039, n_1_0_1040, n_1_0_1041, + n_1_0_1042, n_1_0_1043, n_1_0_1044, n_1_0_1045, n_1_0_1046, n_1_0_1047, + n_1_0_1048, n_1_0_1049, n_1_0_1050, n_1_0_1051, n_1_0_1052, n_1_0_1053, + n_1_0_1054, n_1_0_1055, n_1_0_1056, n_1_0_1057, n_1_0_1058, n_1_0_1059, + n_1_0_1060, n_1_0_1061, n_1_0_1062, n_1_0_1063, n_1_0_1064, n_1_0_1065, + n_1_0_1066, n_1_0_1067, n_1_0_1068, n_1_0_1069, n_1_0_1070, n_1_0_1071, + n_1_0_1072, n_1_0_1073, n_1_0_1074, n_1_0_1075, n_1_0_1076, n_1_0_1077, + n_1_0_1078, n_1_0_1079, n_1_0_1080, n_1_0_1081, n_1_0_1082, n_1_0_1083, + n_1_0_1084, n_1_0_1085, n_1_0_1086, n_1_0_1087, n_1_0_1088, n_1_0_1089, + n_1_0_1090, n_1_0_1091, n_1_0_1092, n_1_0_1093, n_1_0_1094, n_1_0_1095, + n_1_0_1096, n_1_0_1097, n_1_0_1098, n_1_0_1099, n_1_0_1100, n_1_0_1101, + n_1_0_1102, n_1_0_1103, n_1_0_1104, n_1_0_1105, n_1_0_1106, n_1_0_1107, + n_1_0_1108, n_1_0_1109, n_1_0_1110, n_1_0_1111, n_1_0_1112, n_1_0_1113, + n_1_0_1114, n_1_0_1115, n_1_0_1116, n_1_0_1117, n_1_0_1118, n_1_0_1119, + n_1_0_1120, n_1_0_1121, n_1_0_1122, n_1_0_1123, n_1_0_1124, n_1_0_1125, + n_1_0_1126, n_1_0_1127, n_1_0_1128, n_1_0_1129, n_1_0_1130, n_1_0_1131, + n_1_0_1132, n_1_0_1133, n_1_0_1134, n_1_0_1135, n_1_0_1136, n_1_0_1137, + n_1_0_1138, n_1_0_1139, n_1_0_1140, n_1_0_1141, n_1_0_1142, n_1_0_1143, + n_1_0_1144, n_1_0_1145, n_1_0_1146, n_1_0_1147, n_1_0_1148, n_1_0_1149, + n_1_0_1150, n_1_0_1151, n_1_0_1152, n_1_0_1153, n_1_0_1154, n_1_0_1155, + n_1_0_1156, n_1_0_1157, n_1_0_1158, n_1_0_1159, n_1_0_1160, n_1_0_1161, + n_1_0_1162, n_1_0_1163, n_1_0_1164, n_1_0_1165, n_1_0_1166, n_1_0_1167, + n_1_0_1168, n_1_0_1169, n_1_0_1170, n_1_0_1171, n_1_0_1172, n_1_0_1173, + n_1_0_1174, n_1_0_1175, n_1_0_1176, n_1_0_1177, n_1_0_1178, n_1_0_1179, + n_1_0_1180, n_1_0_1181, n_1_0_1182, n_1_0_1183, n_1_0_1184, n_1_0_1185, + n_1_0_1186, n_1_0_1187, n_1_0_1188, n_1_0_1189, n_1_0_1190, n_1_0_1191, + n_1_0_1192, n_1_0_1193, n_1_0_1194, n_1_0_1195, n_1_0_1196, n_1_0_1197, + n_1_0_1198, n_1_0_1199, n_1_0_1200, n_1_0_1201, n_1_0_1202, n_1_0_1203, + n_1_0_1204, n_1_0_1205, n_1_0_1206, n_1_0_1207, n_1_0_1208, n_1_0_1209, + n_1_0_1210, n_1_0_1211, n_1_0_1212, n_1_0_1213, n_1_0_1214, n_1_0_1215, + n_1_0_1216, n_1_0_1217, n_1_0_1218, n_1_0_1219, n_1_0_1220, n_1_0_1221, + n_1_0_1222, n_1_0_1223, n_1_0_1224, n_1_0_1225, n_1_0_1226, n_1_0_1227, + n_1_0_1228, n_1_0_1229, n_1_0_1230, n_1_0_1231, n_1_0_1232, n_1_0_1233, + n_1_0_1234, n_1_0_1235, n_1_0_1236, n_1_0_1237, n_1_0_1238, n_1_0_1239, + n_1_0_1240, n_1_0_1241, n_1_0_1242, n_1_0_1243, n_1_0_1244, n_1_0_1245, + n_1_0_1246, n_1_0_1247, n_1_0_1248, n_1_0_1249, n_1_0_1250, n_1_0_1251, + n_1_0_1252, n_1_0_1253, n_1_0_1254, n_1_0_1255, n_1_0_1256, n_1_0_1257, + n_1_0_1258, n_1_0_1259, n_1_0_1260, n_1_0_1261, n_1_0_1262, n_1_0_1263, + n_1_0_1264, n_1_0_1265, n_1_0_1266, n_1_0_1267, n_1_0_1268, n_1_0_1269, + n_1_0_1270, n_1_0_1271, n_1_0_1272, n_1_0_1273, n_1_0_1274, n_1_0_1275, + n_1_0_1276, n_1_0_1277, n_1_0_1278, n_1_0_1279, n_1_0_1280, n_1_0_1281, + n_1_0_1282, n_1_0_1283, n_1_0_1284, n_1_0_1285, n_1_0_1286, n_1_0_1287, + n_1_0_1288, n_1_0_1289, n_1_0_1290, n_1_0_1291, n_1_0_1292, n_1_0_1293, + n_1_0_1294, n_1_0_1295, n_1_0_1296, n_1_0_1297, n_1_0_1298, n_1_0_1299, + n_1_0_1300, n_1_0_1301, n_1_0_1302, n_1_0_1303, n_1_0_1304, n_1_0_1305, + n_1_0_1306, n_1_0_1307, n_1_0_1308, n_1_0_1309, ts_pbuf_extsi1227_, + ts_pbuf_extsi1228_, ts_pbuf_extsi1226_; + + INV_X1_LVT i_0_0_79( + .A(reset), .ZN(n_0_0_16) + ); + AND2_X1_LVT i_0_0_31( + .A1(n_0_0_16), .A2(WRd[31]), .ZN(registers[31]) + ); + INV_X1_LVT i_0_0_81( + .A(Rd[1]), .ZN(n_0_0_18) + ); + INV_X1_LVT i_0_0_80( + .A(Rd[0]), .ZN(n_0_0_17) + ); + NAND3_X1_LVT i_0_0_69( + .A1(n_0_0_18), .A2(n_0_0_17), .A3(Rd[2]), .ZN(n_0_0_9) + ); + NAND3_X1_LVT i_0_0_41( + .A1(Rd[3]), .A2(WrReg), .A3(Rd[4]), .ZN(n_0_0_1) + ); + OAI21_X1_LVT i_0_0_35( + .A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_1), .ZN(n_0_28) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[28]_reg ( + .CK(clk), .E(n_0_28), .GCK(n_0_58), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[28][31] ( + .CK(n_0_58), .D(registers[31]), .Q(registers_28__ap[31]), .QN(), .SE(dftIn), + .SI(ts_pbuf_extsi1227_) + ); + INV_X1_LVT i_1_0_1370( + .A(Rs1[0]), .ZN(n_1_0_1306) + ); + NAND3_X1_LVT i_1_0_1354( + .A1(n_1_0_1306), .A2(Rs1[3]), .A3(Rs1[4]), .ZN(n_1_0_1290) + ); + INV_X1_LVT i_1_0_1373( + .A(Rs1[2]), .ZN(n_1_0_1309) + ); + OR2_X1_LVT i_1_0_1348( + .A1(n_1_0_1309), .A2(Rs1[1]), .ZN(n_1_0_1284) + ); + NOR2_X1_LVT i_1_0_1347( + .A1(n_1_0_1290), .A2(n_1_0_1284), .ZN(n_1_0_1283) + ); + NOR4_X1_LVT i_1_0_1342( + .A1(n_1_0_1284), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), .ZN(n_1_0_1278) + ); + INV_X1_LVT i_0_0_83( + .A(WrReg), .ZN(n_0_0_20) + ); + OR3_X1_LVT i_0_0_77( + .A1(n_0_0_20), .A2(Rd[4]), .A3(Rd[3]), .ZN(n_0_0_14) + ); + OAI21_X1_LVT i_0_0_68( + .A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_9), .ZN(n_0_4) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[4]_reg ( + .CK(clk), .E(n_0_4), .GCK(n_0_34), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[4][31] ( + .CK(n_0_34), .D(registers[31]), .Q(registers_4__ap[31]), .QN(), .SE(dftIn), + .SI(ts_pbuf_extsi1228_) + ); + AOI22_X1_LVT i_1_0_1320( + .A1(registers_28__ap[31]), .A2(n_1_0_1283), .B1(n_1_0_1278), .B2(registers_4__ap[31]), + .ZN(n_1_0_1256) + ); + NAND2_X1_LVT i_0_0_70( + .A1(n_0_0_18), .A2(n_0_0_17), .ZN(n_0_0_10) + ); + INV_X1_LVT i_0_0_82( + .A(Rd[4]), .ZN(n_0_0_19) + ); + OR3_X1_LVT i_0_0_51( + .A1(n_0_0_20), .A2(n_0_0_19), .A3(Rd[3]), .ZN(n_0_0_3) + ); + OR2_X1_LVT i_0_0_50( + .A1(n_0_0_3), .A2(Rd[2]), .ZN(n_0_0_2) + ); + OAI21_X1_LVT i_0_0_49( + .A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_2), .ZN(n_0_16) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[16]_reg ( + .CK(clk), .E(n_0_16), .GCK(n_0_46), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[16][31] ( + .CK(n_0_46), .D(registers[31]), .Q(registers_16__ap[31]), .QN(), .SE(dftIn), + .SI(ts_intno31) + ); + INV_X1_LVT i_1_0_1371( + .A(Rs1[3]), .ZN(n_1_0_1307) + ); + NAND3_X1_LVT i_1_0_1363( + .A1(n_1_0_1307), .A2(n_1_0_1306), .A3(Rs1[4]), .ZN(n_1_0_1299) + ); + OR2_X1_LVT i_1_0_1357( + .A1(Rs1[1]), .A2(Rs1[2]), .ZN(n_1_0_1293) + ); + NOR2_X1_LVT i_1_0_1331( + .A1(n_1_0_1299), .A2(n_1_0_1293), .ZN(n_1_0_1267) + ); + NAND2_X1_LVT i_1_0_1365( + .A1(Rs1[1]), .A2(Rs1[2]), .ZN(n_1_0_1301) + ); + NAND3_X1_LVT i_1_0_1344( + .A1(Rs1[4]), .A2(Rs1[3]), .A3(Rs1[0]), .ZN(n_1_0_1280) + ); + NOR2_X1_LVT i_1_0_1330( + .A1(n_1_0_1301), .A2(n_1_0_1280), .ZN(n_1_0_1266) + ); + NAND3_X1_LVT i_0_0_63( + .A1(Rd[2]), .A2(Rd[1]), .A3(Rd[0]), .ZN(n_0_0_6) + ); + OAI21_X1_LVT i_0_0_32( + .A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_1), .ZN(n_0_31) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[31]_reg ( + .CK(clk), .E(n_0_31), .GCK(n_0_61), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[31][31] ( + .CK(n_0_61), .D(registers[31]), .Q(registers_31__ap[31]), .QN(), .SE(dftIn), + .SI(registers_4__ap[31]) + ); + AOI22_X1_LVT i_1_0_1329( + .A1(registers_16__ap[31]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[31]), + .ZN(n_1_0_1265) + ); + NAND3_X1_LVT i_0_0_65( + .A1(n_0_0_17), .A2(Rd[1]), .A3(Rd[2]), .ZN(n_0_0_7) + ); + OAI21_X1_LVT i_0_0_64( + .A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_7), .ZN(n_0_6) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[6]_reg ( + .CK(clk), .E(n_0_6), .GCK(n_0_36), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[6][31] ( + .CK(n_0_36), .D(registers[31]), .Q(registers_6__ap[31]), .QN(), .SE(dftIn), + .SI(registers_31__ap[31]) + ); + NOR4_X1_LVT i_1_0_1364( + .A1(n_1_0_1301), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), .ZN(n_1_0_1300) + ); + INV_X1_LVT i_1_0_1372( + .A(Rs1[4]), .ZN(n_1_0_1308) + ); + NAND3_X1_LVT i_1_0_1339( + .A1(n_1_0_1308), .A2(n_1_0_1307), .A3(Rs1[0]), .ZN(n_1_0_1275) + ); + NOR2_X1_LVT i_1_0_1338( + .A1(n_1_0_1293), .A2(n_1_0_1275), .ZN(n_1_0_1274) + ); + NAND2_X1_LVT i_0_0_78( + .A1(n_0_0_18), .A2(Rd[0]), .ZN(n_0_0_15) + ); + OR2_X1_LVT i_0_0_76( + .A1(n_0_0_14), .A2(Rd[2]), .ZN(n_0_0_13) + ); + OAI21_X1_LVT i_0_0_75( + .A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_13), .ZN(n_0_1) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[1]_reg ( + .CK(clk), .E(n_0_1), .GCK(n_0_0), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[1][31] ( + .CK(n_0_0), .D(registers[31]), .Q(registers_1__ap[31]), .QN(), .SE(dftIn), + .SI(ts_pbuf_extsi1226_) + ); + AOI22_X1_LVT i_1_0_1319( + .A1(registers_6__ap[31]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[31]), + .ZN(n_1_0_1255) + ); + OAI21_X1_LVT i_0_0_42( + .A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_3), .ZN(n_0_23) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[23]_reg ( + .CK(clk), .E(n_0_23), .GCK(n_0_53), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[23][31] ( + .CK(n_0_53), .D(registers[31]), .Q(registers_23__ap[31]), .QN(), .SE(dftIn), + .SI(registers_1__ap[31]) + ); + NAND3_X1_LVT i_1_0_1360( + .A1(n_1_0_1307), .A2(Rs1[0]), .A3(Rs1[4]), .ZN(n_1_0_1296) + ); + NOR2_X1_LVT i_1_0_1328( + .A1(n_1_0_1301), .A2(n_1_0_1296), .ZN(n_1_0_1264) + ); + NOR2_X1_LVT i_1_0_1327( + .A1(n_1_0_1301), .A2(n_1_0_1275), .ZN(n_1_0_1263) + ); + OAI21_X1_LVT i_0_0_62( + .A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_6), .ZN(n_0_7) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[7]_reg ( + .CK(clk), .E(n_0_7), .GCK(n_0_37), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[7][31] ( + .CK(n_0_37), .D(registers[31]), .Q(registers_7__ap[31]), .QN(), .SE(dftIn), + .SI(registers_6__ap[31]) + ); + AOI22_X1_LVT i_1_0_1326( + .A1(registers_23__ap[31]), .A2(n_1_0_1264), .B1(n_1_0_1263), .B2(registers_7__ap[31]), + .ZN(n_1_0_1262) + ); + INV_X1_LVT i_1_0_1325( + .A(n_1_0_1262), .ZN(n_1_0_1261) + ); + NAND2_X1_LVT i_1_0_1362( + .A1(n_1_0_1309), .A2(Rs1[1]), .ZN(n_1_0_1298) + ); + NOR2_X1_LVT i_1_0_1359( + .A1(n_1_0_1298), .A2(n_1_0_1296), .ZN(n_1_0_1295) + ); + NAND2_X1_LVT i_0_0_72( + .A1(Rd[1]), .A2(Rd[0]), .ZN(n_0_0_11) + ); + OAI21_X1_LVT i_0_0_46( + .A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_2), .ZN(n_0_19) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[19]_reg ( + .CK(clk), .E(n_0_19), .GCK(n_0_49), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[19][31] ( + .CK(n_0_49), .D(registers[31]), .Q(registers_19__ap[31]), .QN(), .SE(dftIn), + .SI(registers_23__ap[31]) + ); + NAND3_X1_LVT i_0_0_67( + .A1(n_0_0_18), .A2(Rd[0]), .A3(Rd[2]), .ZN(n_0_0_8) + ); + OAI21_X1_LVT i_0_0_66( + .A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_8), .ZN(n_0_5) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[5]_reg ( + .CK(clk), .E(n_0_5), .GCK(n_0_35), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[5][31] ( + .CK(n_0_35), .D(registers[31]), .Q(registers_5__ap[31]), .QN(), .SE(dftIn), + .SI(registers_7__ap[31]) + ); + NOR2_X1_LVT i_1_0_1337( + .A1(n_1_0_1284), .A2(n_1_0_1275), .ZN(n_1_0_1273) + ); + AOI221_X1_LVT i_1_0_1318( + .A(n_1_0_1261), .B1(n_1_0_1295), .B2(registers_19__ap[31]), .C1(registers_5__ap[31]), + .C2(n_1_0_1273), .ZN(n_1_0_1254) + ); + NAND2_X1_LVT i_0_0_74( + .A1(n_0_0_17), .A2(Rd[1]), .ZN(n_0_0_12) + ); + NAND3_X1_LVT i_0_0_61( + .A1(n_0_0_19), .A2(WrReg), .A3(Rd[3]), .ZN(n_0_0_5) + ); + OR2_X1_LVT i_0_0_60( + .A1(n_0_0_5), .A2(Rd[2]), .ZN(n_0_0_4) + ); + OAI21_X1_LVT i_0_0_57( + .A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_4), .ZN(n_0_10) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[10]_reg ( + .CK(clk), .E(n_0_10), .GCK(n_0_40), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[10][31] ( + .CK(n_0_40), .D(registers[31]), .Q(registers_10__ap[31]), .QN(), .SE(dftIn), + .SI(registers_16__ap[31]) + ); + NAND3_X1_LVT i_1_0_1352( + .A1(n_1_0_1308), .A2(n_1_0_1306), .A3(Rs1[3]), .ZN(n_1_0_1288) + ); + NOR2_X1_LVT i_1_0_1351( + .A1(n_1_0_1298), .A2(n_1_0_1288), .ZN(n_1_0_1287) + ); + NOR2_X1_LVT i_1_0_1349( + .A1(n_1_0_1298), .A2(n_1_0_1290), .ZN(n_1_0_1285) + ); + OR2_X1_LVT i_0_0_40( + .A1(n_0_0_1), .A2(Rd[2]), .ZN(n_0_0_0) + ); + OAI21_X1_LVT i_0_0_37( + .A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_0), .ZN(n_0_26) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[26]_reg ( + .CK(clk), .E(n_0_26), .GCK(n_0_56), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[26][31] ( + .CK(n_0_56), .D(registers[31]), .Q(registers_26__ap[31]), .QN(), .SE(dftIn), + .SI(registers_28__ap[31]) + ); + OAI21_X1_LVT i_0_0_59( + .A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_4), .ZN(n_0_8) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[8]_reg ( + .CK(clk), .E(n_0_8), .GCK(n_0_38), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[8][31] ( + .CK(n_0_38), .D(registers[31]), .Q(registers_8__ap[31]), .QN(), .SE(dftIn), + .SI(registers_5__ap[31]) + ); + NOR2_X1_LVT i_1_0_1346( + .A1(n_1_0_1293), .A2(n_1_0_1288), .ZN(n_1_0_1282) + ); + AOI222_X1_LVT i_1_0_1317( + .A1(registers_10__ap[31]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[31]), + .C1(registers_8__ap[31]), .C2(n_1_0_1282), .ZN(n_1_0_1253) + ); + NAND4_X1_LVT i_1_0_1316( + .A1(n_1_0_1265), .A2(n_1_0_1255), .A3(n_1_0_1254), .A4(n_1_0_1253), .ZN(n_1_0_1252) + ); + NAND3_X1_LVT i_1_0_1356( + .A1(n_1_0_1308), .A2(Rs1[3]), .A3(Rs1[0]), .ZN(n_1_0_1292) + ); + NOR2_X1_LVT i_1_0_1355( + .A1(n_1_0_1293), .A2(n_1_0_1292), .ZN(n_1_0_1291) + ); + OAI21_X1_LVT i_0_0_58( + .A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_4), .ZN(n_0_9) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[9]_reg ( + .CK(clk), .E(n_0_9), .GCK(n_0_39), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[9][31] ( + .CK(n_0_39), .D(registers[31]), .Q(registers_9__ap[31]), .QN(), .SE(dftIn), + .SI(registers_8__ap[31]) + ); + OAI21_X1_LVT i_0_0_34( + .A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_1), .ZN(n_0_29) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[29]_reg ( + .CK(clk), .E(n_0_29), .GCK(n_0_59), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[29][31] ( + .CK(n_0_59), .D(registers[31]), .Q(registers_29__ap[31]), .QN(), .SE(dftIn), + .SI(registers_26__ap[31]) + ); + NOR2_X1_LVT i_1_0_1340( + .A1(n_1_0_1284), .A2(n_1_0_1280), .ZN(n_1_0_1276) + ); + AOI221_X1_LVT i_1_0_1315( + .A(n_1_0_1252), .B1(n_1_0_1291), .B2(registers_9__ap[31]), .C1(registers_29__ap[31]), + .C2(n_1_0_1276), .ZN(n_1_0_1251) + ); + OAI21_X1_LVT i_0_0_47( + .A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_2), .ZN(n_0_18) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[18]_reg ( + .CK(clk), .E(n_0_18), .GCK(n_0_48), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[18][31] ( + .CK(n_0_48), .D(registers[31]), .Q(registers_18__ap[31]), .QN(), .SE(dftIn), + .SI(registers_19__ap[31]) + ); + NOR2_X1_LVT i_1_0_1361( + .A1(n_1_0_1299), .A2(n_1_0_1298), .ZN(n_1_0_1297) + ); + NOR2_X1_LVT i_1_0_1336( + .A1(n_1_0_1301), .A2(n_1_0_1290), .ZN(n_1_0_1272) + ); + OAI21_X1_LVT i_0_0_33( + .A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_1), .ZN(n_0_30) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[30]_reg ( + .CK(clk), .E(n_0_30), .GCK(n_0_60), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[30][31] ( + .CK(n_0_60), .D(registers[31]), .Q(registers_30__ap[31]), .QN(), .SE(dftIn), + .SI(registers_29__ap[31]) + ); + AOI22_X1_LVT i_1_0_1314( + .A1(registers_18__ap[31]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[31]), + .ZN(n_1_0_1250) + ); + OAI21_X1_LVT i_0_0_39( + .A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_0), .ZN(n_0_24) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[24]_reg ( + .CK(clk), .E(n_0_24), .GCK(n_0_54), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[24][31] ( + .CK(n_0_54), .D(registers[31]), .Q(registers_24__ap[31]), .QN(), .SE(dftIn), + .SI(registers_30__ap[31]) + ); + NOR2_X1_LVT i_1_0_1353( + .A1(n_1_0_1293), .A2(n_1_0_1290), .ZN(n_1_0_1289) + ); + NOR2_X1_LVT i_1_0_1324( + .A1(n_1_0_1288), .A2(n_1_0_1284), .ZN(n_1_0_1260) + ); + OAI21_X1_LVT i_0_0_55( + .A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_5), .ZN(n_0_12) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[12]_reg ( + .CK(clk), .E(n_0_12), .GCK(n_0_42), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[12][31] ( + .CK(n_0_42), .D(registers[31]), .Q(registers_12__ap[31]), .QN(), .SE(dftIn), + .SI(registers_10__ap[31]) + ); + AOI22_X1_LVT i_1_0_1313( + .A1(registers_24__ap[31]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[31]), + .ZN(n_1_0_1249) + ); + OAI21_X1_LVT i_0_0_43( + .A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_3), .ZN(n_0_22) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[22]_reg ( + .CK(clk), .E(n_0_22), .GCK(n_0_52), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[22][31] ( + .CK(n_0_52), .D(registers[31]), .Q(registers_22__ap[31]), .QN(), .SE(dftIn), + .SI(registers_18__ap[31]) + ); + NOR2_X1_LVT i_1_0_1358( + .A1(n_1_0_1301), .A2(n_1_0_1299), .ZN(n_1_0_1294) + ); + NOR2_X1_LVT i_1_0_1323( + .A1(n_1_0_1296), .A2(n_1_0_1284), .ZN(n_1_0_1259) + ); + OAI21_X1_LVT i_0_0_44( + .A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_3), .ZN(n_0_21) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[21]_reg ( + .CK(clk), .E(n_0_21), .GCK(n_0_51), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[21][31] ( + .CK(n_0_51), .D(registers[31]), .Q(registers_21__ap[31]), .QN(), .SE(dftIn), + .SI(registers_22__ap[31]) + ); + AOI22_X1_LVT i_1_0_1312( + .A1(registers_22__ap[31]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[31]), + .ZN(n_1_0_1248) + ); + NAND3_X1_LVT i_1_0_1311( + .A1(n_1_0_1250), .A2(n_1_0_1249), .A3(n_1_0_1248), .ZN(n_1_0_1247) + ); + NOR2_X1_LVT i_1_0_1335( + .A1(n_1_0_1296), .A2(n_1_0_1293), .ZN(n_1_0_1271) + ); + OAI21_X1_LVT i_0_0_48( + .A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_2), .ZN(n_0_17) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[17]_reg ( + .CK(clk), .E(n_0_17), .GCK(n_0_47), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[17][31] ( + .CK(n_0_47), .D(registers[31]), .Q(registers_17__ap[31]), .QN(), .SE(dftIn), + .SI(registers_21__ap[31]) + ); + OAI21_X1_LVT i_0_0_45( + .A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_3), .ZN(n_0_20) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[20]_reg ( + .CK(clk), .E(n_0_20), .GCK(n_0_50), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[20][31] ( + .CK(n_0_50), .D(registers[31]), .Q(registers_20__ap[31]), .QN(), .SE(dftIn), + .SI(registers_17__ap[31]) + ); + NOR2_X1_LVT i_1_0_1345( + .A1(n_1_0_1299), .A2(n_1_0_1284), .ZN(n_1_0_1281) + ); + AOI221_X1_LVT i_1_0_1310( + .A(n_1_0_1247), .B1(n_1_0_1271), .B2(registers_17__ap[31]), .C1(registers_20__ap[31]), + .C2(n_1_0_1281), .ZN(n_1_0_1246) + ); + OAI21_X1_LVT i_0_0_36( + .A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_0), .ZN(n_0_27) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[27]_reg ( + .CK(clk), .E(n_0_27), .GCK(n_0_57), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[27][31] ( + .CK(n_0_57), .D(registers[31]), .Q(registers_27__ap[31]), .QN(), .SE(dftIn), + .SI(registers_24__ap[31]) + ); + NOR2_X1_LVT i_1_0_1343( + .A1(n_1_0_1298), .A2(n_1_0_1280), .ZN(n_1_0_1279) + ); + NOR2_X1_LVT i_1_0_1334( + .A1(n_1_0_1298), .A2(n_1_0_1292), .ZN(n_1_0_1270) + ); + OAI21_X1_LVT i_0_0_56( + .A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_4), .ZN(n_0_11) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[11]_reg ( + .CK(clk), .E(n_0_11), .GCK(n_0_41), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[11][31] ( + .CK(n_0_41), .D(registers[31]), .Q(registers_11__ap[31]), .QN(), .SE(dftIn), + .SI(registers_12__ap[31]) + ); + AOI22_X1_LVT i_1_0_1309( + .A1(registers_27__ap[31]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[31]), + .ZN(n_1_0_1245) + ); + OAI21_X1_LVT i_0_0_54( + .A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_5), .ZN(n_0_13) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[13]_reg ( + .CK(clk), .E(n_0_13), .GCK(n_0_43), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[13][31] ( + .CK(n_0_43), .D(registers[31]), .Q(registers_13__ap[31]), .QN(), .SE(dftIn), + .SI(registers_11__ap[31]) + ); + NOR2_X1_LVT i_1_0_1341( + .A1(n_1_0_1292), .A2(n_1_0_1284), .ZN(n_1_0_1277) + ); + NOR2_X1_LVT i_1_0_1333( + .A1(n_1_0_1293), .A2(n_1_0_1280), .ZN(n_1_0_1269) + ); + OAI21_X1_LVT i_0_0_38( + .A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_0), .ZN(n_0_25) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[25]_reg ( + .CK(clk), .E(n_0_25), .GCK(n_0_55), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[25][31] ( + .CK(n_0_55), .D(registers[31]), .Q(registers_25__ap[31]), .QN(), .SE(dftIn), + .SI(registers_27__ap[31]) + ); + AOI22_X1_LVT i_1_0_1308( + .A1(registers_13__ap[31]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[31]), + .ZN(n_1_0_1244) + ); + OAI21_X1_LVT i_0_0_52( + .A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_5), .ZN(n_0_15) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[15]_reg ( + .CK(clk), .E(n_0_15), .GCK(n_0_45), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[15][31] ( + .CK(n_0_45), .D(registers[31]), .Q(registers_15__ap[31]), .QN(), .SE(dftIn), + .SI(registers_13__ap[31]) + ); + NOR2_X1_LVT i_1_0_1350( + .A1(n_1_0_1301), .A2(n_1_0_1292), .ZN(n_1_0_1286) + ); + NOR2_X1_LVT i_1_0_1322( + .A1(n_1_0_1301), .A2(n_1_0_1288), .ZN(n_1_0_1258) + ); + OAI21_X1_LVT i_0_0_53( + .A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_5), .ZN(n_0_14) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[14]_reg ( + .CK(clk), .E(n_0_14), .GCK(n_0_44), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[14][31] ( + .CK(n_0_44), .D(registers[31]), .Q(registers_14__ap[31]), .QN(), .SE(dftIn), + .SI(registers_15__ap[31]) + ); + AOI22_X1_LVT i_1_0_1307( + .A1(registers_15__ap[31]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[31]), + .ZN(n_1_0_1243) + ); + NAND3_X1_LVT i_1_0_1306( + .A1(n_1_0_1245), .A2(n_1_0_1244), .A3(n_1_0_1243), .ZN(n_1_0_1242) + ); + NOR2_X1_LVT i_1_0_1321( + .A1(n_1_0_1298), .A2(n_1_0_1275), .ZN(n_1_0_1257) + ); + OAI21_X1_LVT i_0_0_71( + .A(n_0_0_16), .B1(n_0_0_13), .B2(n_0_0_11), .ZN(n_0_3) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[3]_reg ( + .CK(clk), .E(n_0_3), .GCK(n_0_33), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[3][31] ( + .CK(n_0_33), .D(registers[31]), .Q(registers_3__ap[31]), .QN(), .SE(dftIn), + .SI(registers_9__ap[31]) + ); + OAI21_X1_LVT i_0_0_73( + .A(n_0_0_16), .B1(n_0_0_13), .B2(n_0_0_12), .ZN(n_0_2) + ); + CLKGATETST_X1_LVT \clk_gate_registers_reg[2]_reg ( + .CK(clk), .E(n_0_2), .GCK(n_0_32), .SE(dftIn) + ); + SDFF_X1_LVT \registers_reg[2][31] ( + .CK(n_0_32), .D(registers[31]), .Q(registers_2__ap[31]), .QN(), .SE(dftIn), + .SI(registers_25__ap[31]) + ); + NOR4_X1_LVT i_1_0_1332( + .A1(n_1_0_1298), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), .ZN(n_1_0_1268) + ); + AOI221_X1_LVT i_1_0_1305( + .A(n_1_0_1242), .B1(n_1_0_1257), .B2(registers_3__ap[31]), .C1(registers_2__ap[31]), + .C2(n_1_0_1268), .ZN(n_1_0_1241) + ); + NAND4_X1_LVT i_1_0_1304( + .A1(n_1_0_1256), .A2(n_1_0_1251), .A3(n_1_0_1246), .A4(n_1_0_1241), .ZN(RRs1[31]) + ); + AND2_X1_LVT i_0_0_30( + .A1(n_0_0_16), .A2(WRd[30]), .ZN(registers[30]) + ); + SDFF_X1_LVT \registers_reg[28][30] ( + .CK(n_0_58), .D(registers[30]), .Q(registers_28__ap[30]), .QN(), .SE(dftIn), + .SI(registers_2__ap[31]) + ); + SDFF_X1_LVT \registers_reg[17][30] ( + .CK(n_0_47), .D(registers[30]), .Q(registers_17__ap[30]), .QN(), .SE(dftIn), + .SI(registers_20__ap[31]) + ); + AOI22_X1_LVT i_1_0_1300( + .A1(registers_28__ap[30]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[30]), + .ZN(n_1_0_1237) + ); + SDFF_X1_LVT \registers_reg[16][30] ( + .CK(n_0_46), .D(registers[30]), .Q(registers_16__ap[30]), .QN(), .SE(dftIn), + .SI(registers_14__ap[31]) + ); + SDFF_X1_LVT \registers_reg[31][30] ( + .CK(n_0_61), .D(registers[30]), .Q(registers_31__ap[30]), .QN(), .SE(dftIn), + .SI(registers_3__ap[31]) + ); + AOI22_X1_LVT i_1_0_1303( + .A1(registers_16__ap[30]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[30]), + .ZN(n_1_0_1240) + ); + SDFF_X1_LVT \registers_reg[6][30] ( + .CK(n_0_36), .D(registers[30]), .Q(registers_6__ap[30]), .QN(), .SE(dftIn), + .SI(registers_31__ap[30]) + ); + SDFF_X1_LVT \registers_reg[1][30] ( + .CK(n_0_0), .D(registers[30]), .Q(registers_1__ap[30]), .QN(), .SE(dftIn), + .SI(registers_17__ap[30]) + ); + AOI22_X1_LVT i_1_0_1299( + .A1(registers_6__ap[30]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[30]), + .ZN(n_1_0_1236) + ); + SDFF_X1_LVT \registers_reg[23][30] ( + .CK(n_0_53), .D(registers[30]), .Q(registers_23__ap[30]), .QN(), .SE(dftIn), + .SI(registers_1__ap[30]) + ); + SDFF_X1_LVT \registers_reg[7][30] ( + .CK(n_0_37), .D(registers[30]), .Q(registers_7__ap[30]), .QN(), .SE(dftIn), + .SI(registers_6__ap[30]) + ); + AOI22_X1_LVT i_1_0_1302( + .A1(registers_23__ap[30]), .A2(n_1_0_1264), .B1(n_1_0_1263), .B2(registers_7__ap[30]), + .ZN(n_1_0_1239) + ); + INV_X1_LVT i_1_0_1301( + .A(n_1_0_1239), .ZN(n_1_0_1238) + ); + SDFF_X1_LVT \registers_reg[19][30] ( + .CK(n_0_49), .D(registers[30]), .Q(registers_19__ap[30]), .QN(), .SE(dftIn), + .SI(registers_23__ap[30]) + ); + SDFF_X1_LVT \registers_reg[5][30] ( + .CK(n_0_35), .D(registers[30]), .Q(registers_5__ap[30]), .QN(), .SE(dftIn), + .SI(registers_7__ap[30]) + ); + AOI221_X1_LVT i_1_0_1298( + .A(n_1_0_1238), .B1(n_1_0_1295), .B2(registers_19__ap[30]), .C1(registers_5__ap[30]), + .C2(n_1_0_1273), .ZN(n_1_0_1235) + ); + SDFF_X1_LVT \registers_reg[10][30] ( + .CK(n_0_40), .D(registers[30]), .Q(registers_10__ap[30]), .QN(), .SE(dftIn), + .SI(registers_16__ap[30]) + ); + SDFF_X1_LVT \registers_reg[26][30] ( + .CK(n_0_56), .D(registers[30]), .Q(registers_26__ap[30]), .QN(), .SE(dftIn), + .SI(registers_28__ap[30]) + ); + SDFF_X1_LVT \registers_reg[8][30] ( + .CK(n_0_38), .D(registers[30]), .Q(registers_8__ap[30]), .QN(), .SE(dftIn), + .SI(registers_5__ap[30]) + ); + AOI222_X1_LVT i_1_0_1297( + .A1(registers_10__ap[30]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[30]), + .C1(registers_8__ap[30]), .C2(n_1_0_1282), .ZN(n_1_0_1234) + ); + NAND4_X1_LVT i_1_0_1296( + .A1(n_1_0_1240), .A2(n_1_0_1236), .A3(n_1_0_1235), .A4(n_1_0_1234), .ZN(n_1_0_1233) + ); + SDFF_X1_LVT \registers_reg[9][30] ( + .CK(n_0_39), .D(registers[30]), .Q(registers_9__ap[30]), .QN(), .SE(dftIn), + .SI(registers_8__ap[30]) + ); + SDFF_X1_LVT \registers_reg[29][30] ( + .CK(n_0_59), .D(registers[30]), .Q(registers_29__ap[30]), .QN(), .SE(dftIn), + .SI(registers_26__ap[30]) + ); + AOI221_X1_LVT i_1_0_1295( + .A(n_1_0_1233), .B1(n_1_0_1291), .B2(registers_9__ap[30]), .C1(registers_29__ap[30]), + .C2(n_1_0_1276), .ZN(n_1_0_1232) + ); + SDFF_X1_LVT \registers_reg[18][30] ( + .CK(n_0_48), .D(registers[30]), .Q(registers_18__ap[30]), .QN(), .SE(dftIn), + .SI(registers_19__ap[30]) + ); + SDFF_X1_LVT \registers_reg[30][30] ( + .CK(n_0_60), .D(registers[30]), .Q(registers_30__ap[30]), .QN(), .SE(dftIn), + .SI(registers_29__ap[30]) + ); + AOI22_X1_LVT i_1_0_1294( + .A1(registers_18__ap[30]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[30]), + .ZN(n_1_0_1231) + ); + SDFF_X1_LVT \registers_reg[20][30] ( + .CK(n_0_50), .D(registers[30]), .Q(registers_20__ap[30]), .QN(), .SE(dftIn), + .SI(registers_18__ap[30]) + ); + SDFF_X1_LVT \registers_reg[4][30] ( + .CK(n_0_34), .D(registers[30]), .Q(registers_4__ap[30]), .QN(), .SE(dftIn), + .SI(registers_9__ap[30]) + ); + AOI22_X1_LVT i_1_0_1293( + .A1(registers_20__ap[30]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[30]), + .ZN(n_1_0_1230) + ); + SDFF_X1_LVT \registers_reg[22][30] ( + .CK(n_0_52), .D(registers[30]), .Q(registers_22__ap[30]), .QN(), .SE(dftIn), + .SI(registers_20__ap[30]) + ); + SDFF_X1_LVT \registers_reg[21][30] ( + .CK(n_0_51), .D(registers[30]), .Q(registers_21__ap[30]), .QN(), .SE(dftIn), + .SI(registers_22__ap[30]) + ); + AOI22_X1_LVT i_1_0_1292( + .A1(registers_22__ap[30]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[30]), + .ZN(n_1_0_1229) + ); + NAND3_X1_LVT i_1_0_1291( + .A1(n_1_0_1231), .A2(n_1_0_1230), .A3(n_1_0_1229), .ZN(n_1_0_1228) + ); + SDFF_X1_LVT \registers_reg[24][30] ( + .CK(n_0_54), .D(registers[30]), .Q(registers_24__ap[30]), .QN(), .SE(dftIn), + .SI(registers_30__ap[30]) + ); + SDFF_X1_LVT \registers_reg[12][30] ( + .CK(n_0_42), .D(registers[30]), .Q(registers_12__ap[30]), .QN(), .SE(dftIn), + .SI(registers_10__ap[30]) + ); + AOI221_X1_LVT i_1_0_1290( + .A(n_1_0_1228), .B1(n_1_0_1289), .B2(registers_24__ap[30]), .C1(registers_12__ap[30]), + .C2(n_1_0_1260), .ZN(n_1_0_1227) + ); + SDFF_X1_LVT \registers_reg[27][30] ( + .CK(n_0_57), .D(registers[30]), .Q(registers_27__ap[30]), .QN(), .SE(dftIn), + .SI(registers_24__ap[30]) + ); + SDFF_X1_LVT \registers_reg[11][30] ( + .CK(n_0_41), .D(registers[30]), .Q(registers_11__ap[30]), .QN(), .SE(dftIn), + .SI(registers_12__ap[30]) + ); + AOI22_X1_LVT i_1_0_1289( + .A1(registers_27__ap[30]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[30]), + .ZN(n_1_0_1226) + ); + SDFF_X1_LVT \registers_reg[13][30] ( + .CK(n_0_43), .D(registers[30]), .Q(registers_13__ap[30]), .QN(), .SE(dftIn), + .SI(registers_11__ap[30]) + ); + SDFF_X1_LVT \registers_reg[25][30] ( + .CK(n_0_55), .D(registers[30]), .Q(registers_25__ap[30]), .QN(), .SE(dftIn), + .SI(registers_27__ap[30]) + ); + AOI22_X1_LVT i_1_0_1288( + .A1(registers_13__ap[30]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[30]), + .ZN(n_1_0_1225) + ); + SDFF_X1_LVT \registers_reg[15][30] ( + .CK(n_0_45), .D(registers[30]), .Q(registers_15__ap[30]), .QN(), .SE(dftIn), + .SI(registers_13__ap[30]) + ); + SDFF_X1_LVT \registers_reg[14][30] ( + .CK(n_0_44), .D(registers[30]), .Q(registers_14__ap[30]), .QN(), .SE(dftIn), + .SI(registers_15__ap[30]) + ); + AOI22_X1_LVT i_1_0_1287( + .A1(registers_15__ap[30]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[30]), + .ZN(n_1_0_1224) + ); + NAND3_X1_LVT i_1_0_1286( + .A1(n_1_0_1226), .A2(n_1_0_1225), .A3(n_1_0_1224), .ZN(n_1_0_1223) + ); + SDFF_X1_LVT \registers_reg[3][30] ( + .CK(n_0_33), .D(registers[30]), .Q(registers_3__ap[30]), .QN(), .SE(dftIn), + .SI(registers_4__ap[30]) + ); + SDFF_X1_LVT \registers_reg[2][30] ( + .CK(n_0_32), .D(registers[30]), .Q(registers_2__ap[30]), .QN(), .SE(dftIn), + .SI(registers_25__ap[30]) + ); + AOI221_X1_LVT i_1_0_1285( + .A(n_1_0_1223), .B1(n_1_0_1257), .B2(registers_3__ap[30]), .C1(registers_2__ap[30]), + .C2(n_1_0_1268), .ZN(n_1_0_1222) + ); + NAND4_X1_LVT i_1_0_1284( + .A1(n_1_0_1237), .A2(n_1_0_1232), .A3(n_1_0_1227), .A4(n_1_0_1222), .ZN(RRs1[30]) + ); + AND2_X1_LVT i_0_0_29( + .A1(n_0_0_16), .A2(WRd[29]), .ZN(registers[29]) + ); + SDFF_X1_LVT \registers_reg[28][29] ( + .CK(n_0_58), .D(registers[29]), .Q(registers_28__ap[29]), .QN(), .SE(dftIn), + .SI(registers_2__ap[30]) + ); + SDFF_X1_LVT \registers_reg[8][29] ( + .CK(n_0_38), .D(registers[29]), .Q(registers_8__ap[29]), .QN(), .SE(dftIn), + .SI(registers_3__ap[30]) + ); + AOI22_X1_LVT i_1_0_1282( + .A1(registers_28__ap[29]), .A2(n_1_0_1283), .B1(n_1_0_1282), .B2(registers_8__ap[29]), + .ZN(n_1_0_1220) + ); + SDFF_X1_LVT \registers_reg[31][29] ( + .CK(n_0_61), .D(registers[29]), .Q(registers_31__ap[29]), .QN(), .SE(dftIn), + .SI(registers_8__ap[29]) + ); + SDFF_X1_LVT \registers_reg[7][29] ( + .CK(n_0_37), .D(registers[29]), .Q(registers_7__ap[29]), .QN(), .SE(dftIn), + .SI(registers_31__ap[29]) + ); + AOI22_X1_LVT i_1_0_1283( + .A1(registers_31__ap[29]), .A2(n_1_0_1266), .B1(n_1_0_1263), .B2(registers_7__ap[29]), + .ZN(n_1_0_1221) + ); + SDFF_X1_LVT \registers_reg[24][29] ( + .CK(n_0_54), .D(registers[29]), .Q(registers_24__ap[29]), .QN(), .SE(dftIn), + .SI(registers_28__ap[29]) + ); + SDFF_X1_LVT \registers_reg[20][29] ( + .CK(n_0_50), .D(registers[29]), .Q(registers_20__ap[29]), .QN(), .SE(dftIn), + .SI(registers_21__ap[30]) + ); + AOI22_X1_LVT i_1_0_1281( + .A1(registers_24__ap[29]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[29]), + .ZN(n_1_0_1219) + ); + SDFF_X1_LVT \registers_reg[19][29] ( + .CK(n_0_49), .D(registers[29]), .Q(registers_19__ap[29]), .QN(), .SE(dftIn), + .SI(registers_20__ap[29]) + ); + SDFF_X1_LVT \registers_reg[4][29] ( + .CK(n_0_34), .D(registers[29]), .Q(registers_4__ap[29]), .QN(), .SE(dftIn), + .SI(registers_7__ap[29]) + ); + AOI22_X1_LVT i_1_0_1280( + .A1(registers_19__ap[29]), .A2(n_1_0_1295), .B1(n_1_0_1278), .B2(registers_4__ap[29]), + .ZN(n_1_0_1218) + ); + NAND3_X1_LVT i_1_0_1279( + .A1(n_1_0_1221), .A2(n_1_0_1219), .A3(n_1_0_1218), .ZN(n_1_0_1217) + ); + SDFF_X1_LVT \registers_reg[23][29] ( + .CK(n_0_53), .D(registers[29]), .Q(registers_23__ap[29]), .QN(), .SE(dftIn), + .SI(registers_19__ap[29]) + ); + SDFF_X1_LVT \registers_reg[29][29] ( + .CK(n_0_59), .D(registers[29]), .Q(registers_29__ap[29]), .QN(), .SE(dftIn), + .SI(registers_24__ap[29]) + ); + AOI221_X1_LVT i_1_0_1278( + .A(n_1_0_1217), .B1(n_1_0_1264), .B2(registers_23__ap[29]), .C1(registers_29__ap[29]), + .C2(n_1_0_1276), .ZN(n_1_0_1216) + ); + SDFF_X1_LVT \registers_reg[10][29] ( + .CK(n_0_40), .D(registers[29]), .Q(registers_10__ap[29]), .QN(), .SE(dftIn), + .SI(registers_14__ap[30]) + ); + SDFF_X1_LVT \registers_reg[26][29] ( + .CK(n_0_56), .D(registers[29]), .Q(registers_26__ap[29]), .QN(), .SE(dftIn), + .SI(registers_29__ap[29]) + ); + SDFF_X1_LVT \registers_reg[25][29] ( + .CK(n_0_55), .D(registers[29]), .Q(registers_25__ap[29]), .QN(), .SE(dftIn), + .SI(registers_26__ap[29]) + ); + AOI222_X1_LVT i_1_0_1277( + .A1(registers_10__ap[29]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[29]), + .C1(registers_25__ap[29]), .C2(n_1_0_1269), .ZN(n_1_0_1215) + ); + NAND3_X1_LVT i_1_0_1276( + .A1(n_1_0_1220), .A2(n_1_0_1216), .A3(n_1_0_1215), .ZN(n_1_0_1214) + ); + SDFF_X1_LVT \registers_reg[21][29] ( + .CK(n_0_51), .D(registers[29]), .Q(registers_21__ap[29]), .QN(), .SE(dftIn), + .SI(registers_23__ap[29]) + ); + SDFF_X1_LVT \registers_reg[13][29] ( + .CK(n_0_43), .D(registers[29]), .Q(registers_13__ap[29]), .QN(), .SE(dftIn), + .SI(registers_10__ap[29]) + ); + AOI221_X1_LVT i_1_0_1275( + .A(n_1_0_1214), .B1(n_1_0_1259), .B2(registers_21__ap[29]), .C1(registers_13__ap[29]), + .C2(n_1_0_1277), .ZN(n_1_0_1213) + ); + SDFF_X1_LVT \registers_reg[18][29] ( + .CK(n_0_48), .D(registers[29]), .Q(registers_18__ap[29]), .QN(), .SE(dftIn), + .SI(registers_21__ap[29]) + ); + SDFF_X1_LVT \registers_reg[30][29] ( + .CK(n_0_60), .D(registers[29]), .Q(registers_30__ap[29]), .QN(), .SE(dftIn), + .SI(registers_25__ap[29]) + ); + AOI22_X1_LVT i_1_0_1274( + .A1(registers_18__ap[29]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[29]), + .ZN(n_1_0_1212) + ); + SDFF_X1_LVT \registers_reg[17][29] ( + .CK(n_0_47), .D(registers[29]), .Q(registers_17__ap[29]), .QN(), .SE(dftIn), + .SI(registers_18__ap[29]) + ); + SDFF_X1_LVT \registers_reg[12][29] ( + .CK(n_0_42), .D(registers[29]), .Q(registers_12__ap[29]), .QN(), .SE(dftIn), + .SI(registers_13__ap[29]) + ); + AOI22_X1_LVT i_1_0_1273( + .A1(registers_17__ap[29]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[29]), + .ZN(n_1_0_1211) + ); + SDFF_X1_LVT \registers_reg[15][29] ( + .CK(n_0_45), .D(registers[29]), .Q(registers_15__ap[29]), .QN(), .SE(dftIn), + .SI(registers_12__ap[29]) + ); + SDFF_X1_LVT \registers_reg[16][29] ( + .CK(n_0_46), .D(registers[29]), .Q(registers_16__ap[29]), .QN(), .SE(dftIn), + .SI(registers_15__ap[29]) + ); + AOI22_X1_LVT i_1_0_1272( + .A1(registers_15__ap[29]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[29]), + .ZN(n_1_0_1210) + ); + NAND3_X1_LVT i_1_0_1271( + .A1(n_1_0_1212), .A2(n_1_0_1211), .A3(n_1_0_1210), .ZN(n_1_0_1209) + ); + SDFF_X1_LVT \registers_reg[22][29] ( + .CK(n_0_52), .D(registers[29]), .Q(registers_22__ap[29]), .QN(), .SE(dftIn), + .SI(registers_17__ap[29]) + ); + SDFF_X1_LVT \registers_reg[5][29] ( + .CK(n_0_35), .D(registers[29]), .Q(registers_5__ap[29]), .QN(), .SE(dftIn), + .SI(registers_4__ap[29]) + ); + AOI221_X1_LVT i_1_0_1270( + .A(n_1_0_1209), .B1(n_1_0_1294), .B2(registers_22__ap[29]), .C1(registers_5__ap[29]), + .C2(n_1_0_1273), .ZN(n_1_0_1208) + ); + SDFF_X1_LVT \registers_reg[9][29] ( + .CK(n_0_39), .D(registers[29]), .Q(registers_9__ap[29]), .QN(), .SE(dftIn), + .SI(registers_5__ap[29]) + ); + SDFF_X1_LVT \registers_reg[1][29] ( + .CK(n_0_0), .D(registers[29]), .Q(registers_1__ap[29]), .QN(), .SE(dftIn), + .SI(registers_22__ap[29]) + ); + AOI22_X1_LVT i_1_0_1269( + .A1(registers_9__ap[29]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[29]), + .ZN(n_1_0_1207) + ); + SDFF_X1_LVT \registers_reg[6][29] ( + .CK(n_0_36), .D(registers[29]), .Q(registers_6__ap[29]), .QN(), .SE(dftIn), + .SI(registers_9__ap[29]) + ); + SDFF_X1_LVT \registers_reg[14][29] ( + .CK(n_0_44), .D(registers[29]), .Q(registers_14__ap[29]), .QN(), .SE(dftIn), + .SI(registers_16__ap[29]) + ); + AOI22_X1_LVT i_1_0_1268( + .A1(registers_6__ap[29]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[29]), + .ZN(n_1_0_1206) + ); + SDFF_X1_LVT \registers_reg[27][29] ( + .CK(n_0_57), .D(registers[29]), .Q(registers_27__ap[29]), .QN(), .SE(dftIn), + .SI(registers_30__ap[29]) + ); + SDFF_X1_LVT \registers_reg[11][29] ( + .CK(n_0_41), .D(registers[29]), .Q(registers_11__ap[29]), .QN(), .SE(dftIn), + .SI(registers_14__ap[29]) + ); + AOI22_X1_LVT i_1_0_1267( + .A1(registers_27__ap[29]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[29]), + .ZN(n_1_0_1205) + ); + NAND3_X1_LVT i_1_0_1266( + .A1(n_1_0_1207), .A2(n_1_0_1206), .A3(n_1_0_1205), .ZN(n_1_0_1204) + ); + SDFF_X1_LVT \registers_reg[3][29] ( + .CK(n_0_33), .D(registers[29]), .Q(registers_3__ap[29]), .QN(), .SE(dftIn), + .SI(registers_6__ap[29]) + ); + SDFF_X1_LVT \registers_reg[2][29] ( + .CK(n_0_32), .D(registers[29]), .Q(registers_2__ap[29]), .QN(), .SE(dftIn), + .SI(registers_27__ap[29]) + ); + AOI221_X1_LVT i_1_0_1265( + .A(n_1_0_1204), .B1(n_1_0_1257), .B2(registers_3__ap[29]), .C1(registers_2__ap[29]), + .C2(n_1_0_1268), .ZN(n_1_0_1203) + ); + NAND3_X1_LVT i_1_0_1264( + .A1(n_1_0_1213), .A2(n_1_0_1208), .A3(n_1_0_1203), .ZN(RRs1[29]) + ); + AND2_X1_LVT i_0_0_28( + .A1(n_0_0_16), .A2(WRd[28]), .ZN(registers[28]) + ); + SDFF_X1_LVT \registers_reg[15][28] ( + .CK(n_0_45), .D(registers[28]), .Q(registers_15__ap[28]), .QN(), .SE(dftIn), + .SI(registers_11__ap[29]) + ); + SDFF_X1_LVT \registers_reg[26][28] ( + .CK(n_0_56), .D(registers[28]), .Q(registers_26__ap[28]), .QN(), .SE(dftIn), + .SI(registers_2__ap[29]) + ); + SDFF_X1_LVT \registers_reg[22][28] ( + .CK(n_0_52), .D(registers[28]), .Q(registers_22__ap[28]), .QN(), .SE(dftIn), + .SI(registers_1__ap[29]) + ); + AOI222_X1_LVT i_1_0_1263( + .A1(registers_15__ap[28]), .A2(n_1_0_1286), .B1(n_1_0_1285), .B2(registers_26__ap[28]), + .C1(registers_22__ap[28]), .C2(n_1_0_1294), .ZN(n_1_0_1202) + ); + SDFF_X1_LVT \registers_reg[5][28] ( + .CK(n_0_35), .D(registers[28]), .Q(registers_5__ap[28]), .QN(), .SE(dftIn), + .SI(registers_3__ap[29]) + ); + SDFF_X1_LVT \registers_reg[12][28] ( + .CK(n_0_42), .D(registers[28]), .Q(registers_12__ap[28]), .QN(), .SE(dftIn), + .SI(registers_15__ap[28]) + ); + AOI22_X1_LVT i_1_0_1262( + .A1(registers_5__ap[28]), .A2(n_1_0_1273), .B1(n_1_0_1260), .B2(registers_12__ap[28]), + .ZN(n_1_0_1201) + ); + SDFF_X1_LVT \registers_reg[28][28] ( + .CK(n_0_58), .D(registers[28]), .Q(registers_28__ap[28]), .QN(), .SE(dftIn), + .SI(registers_26__ap[28]) + ); + SDFF_X1_LVT \registers_reg[14][28] ( + .CK(n_0_44), .D(registers[28]), .Q(registers_14__ap[28]), .QN(), .SE(dftIn), + .SI(registers_12__ap[28]) + ); + AOI22_X1_LVT i_1_0_1261( + .A1(registers_28__ap[28]), .A2(n_1_0_1283), .B1(n_1_0_1258), .B2(registers_14__ap[28]), + .ZN(n_1_0_1200) + ); + SDFF_X1_LVT \registers_reg[17][28] ( + .CK(n_0_47), .D(registers[28]), .Q(registers_17__ap[28]), .QN(), .SE(dftIn), + .SI(registers_22__ap[28]) + ); + SDFF_X1_LVT \registers_reg[2][28] ( + .CK(n_0_32), .D(registers[28]), .Q(registers_2__ap[28]), .QN(), .SE(dftIn), + .SI(registers_28__ap[28]) + ); + AOI22_X1_LVT i_1_0_1260( + .A1(registers_17__ap[28]), .A2(n_1_0_1271), .B1(n_1_0_1268), .B2(registers_2__ap[28]), + .ZN(n_1_0_1199) + ); + NAND3_X1_LVT i_1_0_1259( + .A1(n_1_0_1201), .A2(n_1_0_1200), .A3(n_1_0_1199), .ZN(n_1_0_1198) + ); + SDFF_X1_LVT \registers_reg[9][28] ( + .CK(n_0_39), .D(registers[28]), .Q(registers_9__ap[28]), .QN(), .SE(dftIn), + .SI(registers_5__ap[28]) + ); + SDFF_X1_LVT \registers_reg[29][28] ( + .CK(n_0_59), .D(registers[28]), .Q(registers_29__ap[28]), .QN(), .SE(dftIn), + .SI(registers_2__ap[28]) + ); + AOI221_X1_LVT i_1_0_1258( + .A(n_1_0_1198), .B1(n_1_0_1291), .B2(registers_9__ap[28]), .C1(registers_29__ap[28]), + .C2(n_1_0_1276), .ZN(n_1_0_1197) + ); + SDFF_X1_LVT \registers_reg[13][28] ( + .CK(n_0_43), .D(registers[28]), .Q(registers_13__ap[28]), .QN(), .SE(dftIn), + .SI(registers_14__ap[28]) + ); + SDFF_X1_LVT \registers_reg[25][28] ( + .CK(n_0_55), .D(registers[28]), .Q(registers_25__ap[28]), .QN(), .SE(dftIn), + .SI(registers_29__ap[28]) + ); + AOI22_X1_LVT i_1_0_1257( + .A1(registers_13__ap[28]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[28]), + .ZN(n_1_0_1196) + ); + NAND3_X1_LVT i_1_0_1256( + .A1(n_1_0_1202), .A2(n_1_0_1197), .A3(n_1_0_1196), .ZN(n_1_0_1195) + ); + SDFF_X1_LVT \registers_reg[4][28] ( + .CK(n_0_34), .D(registers[28]), .Q(registers_4__ap[28]), .QN(), .SE(dftIn), + .SI(registers_9__ap[28]) + ); + SDFF_X1_LVT \registers_reg[20][28] ( + .CK(n_0_50), .D(registers[28]), .Q(registers_20__ap[28]), .QN(), .SE(dftIn), + .SI(registers_17__ap[28]) + ); + AOI221_X1_LVT i_1_0_1255( + .A(n_1_0_1195), .B1(n_1_0_1278), .B2(registers_4__ap[28]), .C1(registers_20__ap[28]), + .C2(n_1_0_1281), .ZN(n_1_0_1194) + ); + SDFF_X1_LVT \registers_reg[1][28] ( + .CK(n_0_0), .D(registers[28]), .Q(registers_1__ap[28]), .QN(), .SE(dftIn), + .SI(registers_20__ap[28]) + ); + SDFF_X1_LVT \registers_reg[23][28] ( + .CK(n_0_53), .D(registers[28]), .Q(registers_23__ap[28]), .QN(), .SE(dftIn), + .SI(registers_1__ap[28]) + ); + AOI22_X1_LVT i_1_0_1254( + .A1(registers_1__ap[28]), .A2(n_1_0_1274), .B1(n_1_0_1264), .B2(registers_23__ap[28]), + .ZN(n_1_0_1193) + ); + SDFF_X1_LVT \registers_reg[10][28] ( + .CK(n_0_40), .D(registers[28]), .Q(registers_10__ap[28]), .QN(), .SE(dftIn), + .SI(registers_13__ap[28]) + ); + SDFF_X1_LVT \registers_reg[21][28] ( + .CK(n_0_51), .D(registers[28]), .Q(registers_21__ap[28]), .QN(), .SE(dftIn), + .SI(registers_23__ap[28]) + ); + AOI22_X1_LVT i_1_0_1253( + .A1(registers_10__ap[28]), .A2(n_1_0_1287), .B1(n_1_0_1259), .B2(registers_21__ap[28]), + .ZN(n_1_0_1192) + ); + SDFF_X1_LVT \registers_reg[6][28] ( + .CK(n_0_36), .D(registers[28]), .Q(registers_6__ap[28]), .QN(), .SE(dftIn), + .SI(registers_4__ap[28]) + ); + SDFF_X1_LVT \registers_reg[30][28] ( + .CK(n_0_60), .D(registers[28]), .Q(registers_30__ap[28]), .QN(), .SE(dftIn), + .SI(registers_25__ap[28]) + ); + AOI22_X1_LVT i_1_0_1252( + .A1(registers_6__ap[28]), .A2(n_1_0_1300), .B1(n_1_0_1272), .B2(registers_30__ap[28]), + .ZN(n_1_0_1191) + ); + NAND3_X1_LVT i_1_0_1251( + .A1(n_1_0_1193), .A2(n_1_0_1192), .A3(n_1_0_1191), .ZN(n_1_0_1190) + ); + SDFF_X1_LVT \registers_reg[8][28] ( + .CK(n_0_38), .D(registers[28]), .Q(registers_8__ap[28]), .QN(), .SE(dftIn), + .SI(registers_6__ap[28]) + ); + SDFF_X1_LVT \registers_reg[24][28] ( + .CK(n_0_54), .D(registers[28]), .Q(registers_24__ap[28]), .QN(), .SE(dftIn), + .SI(registers_30__ap[28]) + ); + AOI221_X1_LVT i_1_0_1250( + .A(n_1_0_1190), .B1(n_1_0_1282), .B2(registers_8__ap[28]), .C1(registers_24__ap[28]), + .C2(n_1_0_1289), .ZN(n_1_0_1189) + ); + SDFF_X1_LVT \registers_reg[16][28] ( + .CK(n_0_46), .D(registers[28]), .Q(registers_16__ap[28]), .QN(), .SE(dftIn), + .SI(registers_10__ap[28]) + ); + SDFF_X1_LVT \registers_reg[3][28] ( + .CK(n_0_33), .D(registers[28]), .Q(registers_3__ap[28]), .QN(), .SE(dftIn), + .SI(registers_8__ap[28]) + ); + AOI22_X1_LVT i_1_0_1249( + .A1(registers_16__ap[28]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[28]), + .ZN(n_1_0_1188) + ); + SDFF_X1_LVT \registers_reg[11][28] ( + .CK(n_0_41), .D(registers[28]), .Q(registers_11__ap[28]), .QN(), .SE(dftIn), + .SI(registers_16__ap[28]) + ); + SDFF_X1_LVT \registers_reg[31][28] ( + .CK(n_0_61), .D(registers[28]), .Q(registers_31__ap[28]), .QN(), .SE(dftIn), + .SI(registers_3__ap[28]) + ); + AOI22_X1_LVT i_1_0_1248( + .A1(registers_11__ap[28]), .A2(n_1_0_1270), .B1(n_1_0_1266), .B2(registers_31__ap[28]), + .ZN(n_1_0_1187) + ); + SDFF_X1_LVT \registers_reg[27][28] ( + .CK(n_0_57), .D(registers[28]), .Q(registers_27__ap[28]), .QN(), .SE(dftIn), + .SI(registers_24__ap[28]) + ); + SDFF_X1_LVT \registers_reg[7][28] ( + .CK(n_0_37), .D(registers[28]), .Q(registers_7__ap[28]), .QN(), .SE(dftIn), + .SI(registers_31__ap[28]) + ); + AOI22_X1_LVT i_1_0_1247( + .A1(registers_27__ap[28]), .A2(n_1_0_1279), .B1(n_1_0_1263), .B2(registers_7__ap[28]), + .ZN(n_1_0_1186) + ); + NAND3_X1_LVT i_1_0_1246( + .A1(n_1_0_1188), .A2(n_1_0_1187), .A3(n_1_0_1186), .ZN(n_1_0_1185) + ); + SDFF_X1_LVT \registers_reg[19][28] ( + .CK(n_0_49), .D(registers[28]), .Q(registers_19__ap[28]), .QN(), .SE(dftIn), + .SI(registers_21__ap[28]) + ); + SDFF_X1_LVT \registers_reg[18][28] ( + .CK(n_0_48), .D(registers[28]), .Q(registers_18__ap[28]), .QN(), .SE(dftIn), + .SI(registers_19__ap[28]) + ); + AOI221_X1_LVT i_1_0_1245( + .A(n_1_0_1185), .B1(n_1_0_1295), .B2(registers_19__ap[28]), .C1(registers_18__ap[28]), + .C2(n_1_0_1297), .ZN(n_1_0_1184) + ); + NAND3_X1_LVT i_1_0_1244( + .A1(n_1_0_1194), .A2(n_1_0_1189), .A3(n_1_0_1184), .ZN(RRs1[28]) + ); + AND2_X1_LVT i_0_0_27( + .A1(n_0_0_16), .A2(WRd[27]), .ZN(registers[27]) + ); + SDFF_X1_LVT \registers_reg[29][27] ( + .CK(n_0_59), .D(registers[27]), .Q(registers_29__ap[27]), .QN(), .SE(dftIn), + .SI(registers_27__ap[28]) + ); + SDFF_X1_LVT \registers_reg[2][27] ( + .CK(n_0_32), .D(registers[27]), .Q(registers_2__ap[27]), .QN(), .SE(dftIn), + .SI(registers_29__ap[27]) + ); + AOI22_X1_LVT i_1_0_1242( + .A1(registers_29__ap[27]), .A2(n_1_0_1276), .B1(n_1_0_1268), .B2(registers_2__ap[27]), + .ZN(n_1_0_1182) + ); + SDFF_X1_LVT \registers_reg[8][27] ( + .CK(n_0_38), .D(registers[27]), .Q(registers_8__ap[27]), .QN(), .SE(dftIn), + .SI(registers_7__ap[28]) + ); + SDFF_X1_LVT \registers_reg[25][27] ( + .CK(n_0_55), .D(registers[27]), .Q(registers_25__ap[27]), .QN(), .SE(dftIn), + .SI(registers_2__ap[27]) + ); + AOI22_X1_LVT i_1_0_1243( + .A1(registers_8__ap[27]), .A2(n_1_0_1282), .B1(n_1_0_1269), .B2(registers_25__ap[27]), + .ZN(n_1_0_1183) + ); + SDFF_X1_LVT \registers_reg[9][27] ( + .CK(n_0_39), .D(registers[27]), .Q(registers_9__ap[27]), .QN(), .SE(dftIn), + .SI(registers_8__ap[27]) + ); + SDFF_X1_LVT \registers_reg[7][27] ( + .CK(n_0_37), .D(registers[27]), .Q(registers_7__ap[27]), .QN(), .SE(dftIn), + .SI(registers_9__ap[27]) + ); + AOI22_X1_LVT i_1_0_1241( + .A1(registers_9__ap[27]), .A2(n_1_0_1291), .B1(n_1_0_1263), .B2(registers_7__ap[27]), + .ZN(n_1_0_1181) + ); + SDFF_X1_LVT \registers_reg[11][27] ( + .CK(n_0_41), .D(registers[27]), .Q(registers_11__ap[27]), .QN(), .SE(dftIn), + .SI(registers_11__ap[28]) + ); + SDFF_X1_LVT \registers_reg[16][27] ( + .CK(n_0_46), .D(registers[27]), .Q(registers_16__ap[27]), .QN(), .SE(dftIn), + .SI(registers_11__ap[27]) + ); + AOI22_X1_LVT i_1_0_1240( + .A1(registers_11__ap[27]), .A2(n_1_0_1270), .B1(n_1_0_1267), .B2(registers_16__ap[27]), + .ZN(n_1_0_1180) + ); + NAND3_X1_LVT i_1_0_1239( + .A1(n_1_0_1183), .A2(n_1_0_1181), .A3(n_1_0_1180), .ZN(n_1_0_1179) + ); + SDFF_X1_LVT \registers_reg[10][27] ( + .CK(n_0_40), .D(registers[27]), .Q(registers_10__ap[27]), .QN(), .SE(dftIn), + .SI(registers_16__ap[27]) + ); + SDFF_X1_LVT \registers_reg[6][27] ( + .CK(n_0_36), .D(registers[27]), .Q(registers_6__ap[27]), .QN(), .SE(dftIn), + .SI(registers_7__ap[27]) + ); + AOI221_X1_LVT i_1_0_1238( + .A(n_1_0_1179), .B1(n_1_0_1287), .B2(registers_10__ap[27]), .C1(registers_6__ap[27]), + .C2(n_1_0_1300), .ZN(n_1_0_1178) + ); + SDFF_X1_LVT \registers_reg[1][27] ( + .CK(n_0_0), .D(registers[27]), .Q(registers_1__ap[27]), .QN(), .SE(dftIn), + .SI(registers_18__ap[28]) + ); + SDFF_X1_LVT \registers_reg[30][27] ( + .CK(n_0_60), .D(registers[27]), .Q(registers_30__ap[27]), .QN(), .SE(dftIn), + .SI(registers_25__ap[27]) + ); + SDFF_X1_LVT \registers_reg[22][27] ( + .CK(n_0_52), .D(registers[27]), .Q(registers_22__ap[27]), .QN(), .SE(dftIn), + .SI(registers_1__ap[27]) + ); + AOI222_X1_LVT i_1_0_1237( + .A1(registers_1__ap[27]), .A2(n_1_0_1274), .B1(n_1_0_1272), .B2(registers_30__ap[27]), + .C1(registers_22__ap[27]), .C2(n_1_0_1294), .ZN(n_1_0_1177) + ); + NAND3_X1_LVT i_1_0_1236( + .A1(n_1_0_1182), .A2(n_1_0_1178), .A3(n_1_0_1177), .ZN(n_1_0_1176) + ); + SDFF_X1_LVT \registers_reg[5][27] ( + .CK(n_0_35), .D(registers[27]), .Q(registers_5__ap[27]), .QN(), .SE(dftIn), + .SI(registers_6__ap[27]) + ); + SDFF_X1_LVT \registers_reg[28][27] ( + .CK(n_0_58), .D(registers[27]), .Q(registers_28__ap[27]), .QN(), .SE(dftIn), + .SI(registers_30__ap[27]) + ); + AOI221_X1_LVT i_1_0_1235( + .A(n_1_0_1176), .B1(n_1_0_1273), .B2(registers_5__ap[27]), .C1(registers_28__ap[27]), + .C2(n_1_0_1283), .ZN(n_1_0_1175) + ); + SDFF_X1_LVT \registers_reg[4][27] ( + .CK(n_0_34), .D(registers[27]), .Q(registers_4__ap[27]), .QN(), .SE(dftIn), + .SI(registers_5__ap[27]) + ); + SDFF_X1_LVT \registers_reg[12][27] ( + .CK(n_0_42), .D(registers[27]), .Q(registers_12__ap[27]), .QN(), .SE(dftIn), + .SI(registers_10__ap[27]) + ); + AOI22_X1_LVT i_1_0_1234( + .A1(registers_4__ap[27]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[27]), + .ZN(n_1_0_1174) + ); + SDFF_X1_LVT \registers_reg[19][27] ( + .CK(n_0_49), .D(registers[27]), .Q(registers_19__ap[27]), .QN(), .SE(dftIn), + .SI(registers_22__ap[27]) + ); + SDFF_X1_LVT \registers_reg[21][27] ( + .CK(n_0_51), .D(registers[27]), .Q(registers_21__ap[27]), .QN(), .SE(dftIn), + .SI(registers_19__ap[27]) + ); + AOI22_X1_LVT i_1_0_1233( + .A1(registers_19__ap[27]), .A2(n_1_0_1295), .B1(n_1_0_1259), .B2(registers_21__ap[27]), + .ZN(n_1_0_1173) + ); + SDFF_X1_LVT \registers_reg[24][27] ( + .CK(n_0_54), .D(registers[27]), .Q(registers_24__ap[27]), .QN(), .SE(dftIn), + .SI(registers_28__ap[27]) + ); + SDFF_X1_LVT \registers_reg[20][27] ( + .CK(n_0_50), .D(registers[27]), .Q(registers_20__ap[27]), .QN(), .SE(dftIn), + .SI(registers_21__ap[27]) + ); + AOI22_X1_LVT i_1_0_1232( + .A1(registers_24__ap[27]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[27]), + .ZN(n_1_0_1172) + ); + NAND3_X1_LVT i_1_0_1231( + .A1(n_1_0_1174), .A2(n_1_0_1173), .A3(n_1_0_1172), .ZN(n_1_0_1171) + ); + SDFF_X1_LVT \registers_reg[18][27] ( + .CK(n_0_48), .D(registers[27]), .Q(registers_18__ap[27]), .QN(), .SE(dftIn), + .SI(registers_20__ap[27]) + ); + SDFF_X1_LVT \registers_reg[26][27] ( + .CK(n_0_56), .D(registers[27]), .Q(registers_26__ap[27]), .QN(), .SE(dftIn), + .SI(registers_24__ap[27]) + ); + AOI221_X1_LVT i_1_0_1230( + .A(n_1_0_1171), .B1(n_1_0_1297), .B2(registers_18__ap[27]), .C1(registers_26__ap[27]), + .C2(n_1_0_1285), .ZN(n_1_0_1170) + ); + SDFF_X1_LVT \registers_reg[23][27] ( + .CK(n_0_53), .D(registers[27]), .Q(registers_23__ap[27]), .QN(), .SE(dftIn), + .SI(registers_18__ap[27]) + ); + SDFF_X1_LVT \registers_reg[3][27] ( + .CK(n_0_33), .D(registers[27]), .Q(registers_3__ap[27]), .QN(), .SE(dftIn), + .SI(registers_4__ap[27]) + ); + AOI22_X1_LVT i_1_0_1229( + .A1(registers_23__ap[27]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[27]), + .ZN(n_1_0_1169) + ); + SDFF_X1_LVT \registers_reg[13][27] ( + .CK(n_0_43), .D(registers[27]), .Q(registers_13__ap[27]), .QN(), .SE(dftIn), + .SI(registers_12__ap[27]) + ); + SDFF_X1_LVT \registers_reg[17][27] ( + .CK(n_0_47), .D(registers[27]), .Q(registers_17__ap[27]), .QN(), .SE(dftIn), + .SI(registers_23__ap[27]) + ); + AOI22_X1_LVT i_1_0_1228( + .A1(registers_13__ap[27]), .A2(n_1_0_1277), .B1(n_1_0_1271), .B2(registers_17__ap[27]), + .ZN(n_1_0_1168) + ); + SDFF_X1_LVT \registers_reg[15][27] ( + .CK(n_0_45), .D(registers[27]), .Q(registers_15__ap[27]), .QN(), .SE(dftIn), + .SI(registers_13__ap[27]) + ); + SDFF_X1_LVT \registers_reg[14][27] ( + .CK(n_0_44), .D(registers[27]), .Q(registers_14__ap[27]), .QN(), .SE(dftIn), + .SI(registers_15__ap[27]) + ); + AOI22_X1_LVT i_1_0_1227( + .A1(registers_15__ap[27]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[27]), + .ZN(n_1_0_1167) + ); + NAND3_X1_LVT i_1_0_1226( + .A1(n_1_0_1169), .A2(n_1_0_1168), .A3(n_1_0_1167), .ZN(n_1_0_1166) + ); + SDFF_X1_LVT \registers_reg[27][27] ( + .CK(n_0_57), .D(registers[27]), .Q(registers_27__ap[27]), .QN(), .SE(dftIn), + .SI(registers_26__ap[27]) + ); + SDFF_X1_LVT \registers_reg[31][27] ( + .CK(n_0_61), .D(registers[27]), .Q(registers_31__ap[27]), .QN(), .SE(dftIn), + .SI(registers_3__ap[27]) + ); + AOI221_X1_LVT i_1_0_1225( + .A(n_1_0_1166), .B1(n_1_0_1279), .B2(registers_27__ap[27]), .C1(registers_31__ap[27]), + .C2(n_1_0_1266), .ZN(n_1_0_1165) + ); + NAND3_X1_LVT i_1_0_1224( + .A1(n_1_0_1175), .A2(n_1_0_1170), .A3(n_1_0_1165), .ZN(RRs1[27]) + ); + AND2_X1_LVT i_0_0_26( + .A1(n_0_0_16), .A2(WRd[26]), .ZN(registers[26]) + ); + SDFF_X1_LVT \registers_reg[18][26] ( + .CK(n_0_48), .D(registers[26]), .Q(registers_18__ap[26]), .QN(), .SE(dftIn), + .SI(registers_17__ap[27]) + ); + SDFF_X1_LVT \registers_reg[22][26] ( + .CK(n_0_52), .D(registers[26]), .Q(registers_22__ap[26]), .QN(), .SE(dftIn), + .SI(registers_18__ap[26]) + ); + SDFF_X1_LVT \registers_reg[1][26] ( + .CK(n_0_0), .D(registers[26]), .Q(registers_1__ap[26]), .QN(), .SE(dftIn), + .SI(registers_22__ap[26]) + ); + AOI222_X1_LVT i_1_0_1223( + .A1(registers_18__ap[26]), .A2(n_1_0_1297), .B1(n_1_0_1294), .B2(registers_22__ap[26]), + .C1(registers_1__ap[26]), .C2(n_1_0_1274), .ZN(n_1_0_1164) + ); + SDFF_X1_LVT \registers_reg[29][26] ( + .CK(n_0_59), .D(registers[26]), .Q(registers_29__ap[26]), .QN(), .SE(dftIn), + .SI(registers_27__ap[27]) + ); + SDFF_X1_LVT \registers_reg[2][26] ( + .CK(n_0_32), .D(registers[26]), .Q(registers_2__ap[26]), .QN(), .SE(dftIn), + .SI(registers_29__ap[26]) + ); + AOI22_X1_LVT i_1_0_1222( + .A1(registers_29__ap[26]), .A2(n_1_0_1276), .B1(n_1_0_1268), .B2(registers_2__ap[26]), + .ZN(n_1_0_1163) + ); + SDFF_X1_LVT \registers_reg[9][26] ( + .CK(n_0_39), .D(registers[26]), .Q(registers_9__ap[26]), .QN(), .SE(dftIn), + .SI(registers_31__ap[27]) + ); + SDFF_X1_LVT \registers_reg[7][26] ( + .CK(n_0_37), .D(registers[26]), .Q(registers_7__ap[26]), .QN(), .SE(dftIn), + .SI(registers_9__ap[26]) + ); + AOI22_X1_LVT i_1_0_1221( + .A1(registers_9__ap[26]), .A2(n_1_0_1291), .B1(n_1_0_1263), .B2(registers_7__ap[26]), + .ZN(n_1_0_1162) + ); + SDFF_X1_LVT \registers_reg[11][26] ( + .CK(n_0_41), .D(registers[26]), .Q(registers_11__ap[26]), .QN(), .SE(dftIn), + .SI(registers_14__ap[27]) + ); + SDFF_X1_LVT \registers_reg[25][26] ( + .CK(n_0_55), .D(registers[26]), .Q(registers_25__ap[26]), .QN(), .SE(dftIn), + .SI(registers_2__ap[26]) + ); + AOI22_X1_LVT i_1_0_1220( + .A1(registers_11__ap[26]), .A2(n_1_0_1270), .B1(n_1_0_1269), .B2(registers_25__ap[26]), + .ZN(n_1_0_1161) + ); + SDFF_X1_LVT \registers_reg[27][26] ( + .CK(n_0_57), .D(registers[26]), .Q(registers_27__ap[26]), .QN(), .SE(dftIn), + .SI(registers_25__ap[26]) + ); + SDFF_X1_LVT \registers_reg[16][26] ( + .CK(n_0_46), .D(registers[26]), .Q(registers_16__ap[26]), .QN(), .SE(dftIn), + .SI(registers_11__ap[26]) + ); + AOI22_X1_LVT i_1_0_1219( + .A1(registers_27__ap[26]), .A2(n_1_0_1279), .B1(n_1_0_1267), .B2(registers_16__ap[26]), + .ZN(n_1_0_1160) + ); + NAND3_X1_LVT i_1_0_1218( + .A1(n_1_0_1162), .A2(n_1_0_1161), .A3(n_1_0_1160), .ZN(n_1_0_1159) + ); + SDFF_X1_LVT \registers_reg[31][26] ( + .CK(n_0_61), .D(registers[26]), .Q(registers_31__ap[26]), .QN(), .SE(dftIn), + .SI(registers_7__ap[26]) + ); + SDFF_X1_LVT \registers_reg[6][26] ( + .CK(n_0_36), .D(registers[26]), .Q(registers_6__ap[26]), .QN(), .SE(dftIn), + .SI(registers_31__ap[26]) + ); + AOI221_X1_LVT i_1_0_1217( + .A(n_1_0_1159), .B1(n_1_0_1266), .B2(registers_31__ap[26]), .C1(registers_6__ap[26]), + .C2(n_1_0_1300), .ZN(n_1_0_1158) + ); + NAND3_X1_LVT i_1_0_1216( + .A1(n_1_0_1164), .A2(n_1_0_1163), .A3(n_1_0_1158), .ZN(n_1_0_1157) + ); + SDFF_X1_LVT \registers_reg[5][26] ( + .CK(n_0_35), .D(registers[26]), .Q(registers_5__ap[26]), .QN(), .SE(dftIn), + .SI(registers_6__ap[26]) + ); + SDFF_X1_LVT \registers_reg[28][26] ( + .CK(n_0_58), .D(registers[26]), .Q(registers_28__ap[26]), .QN(), .SE(dftIn), + .SI(registers_27__ap[26]) + ); + AOI221_X1_LVT i_1_0_1215( + .A(n_1_0_1157), .B1(n_1_0_1273), .B2(registers_5__ap[26]), .C1(registers_28__ap[26]), + .C2(n_1_0_1283), .ZN(n_1_0_1156) + ); + SDFF_X1_LVT \registers_reg[4][26] ( + .CK(n_0_34), .D(registers[26]), .Q(registers_4__ap[26]), .QN(), .SE(dftIn), + .SI(registers_5__ap[26]) + ); + SDFF_X1_LVT \registers_reg[12][26] ( + .CK(n_0_42), .D(registers[26]), .Q(registers_12__ap[26]), .QN(), .SE(dftIn), + .SI(registers_16__ap[26]) + ); + AOI22_X1_LVT i_1_0_1214( + .A1(registers_4__ap[26]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[26]), + .ZN(n_1_0_1155) + ); + SDFF_X1_LVT \registers_reg[19][26] ( + .CK(n_0_49), .D(registers[26]), .Q(registers_19__ap[26]), .QN(), .SE(dftIn), + .SI(registers_1__ap[26]) + ); + SDFF_X1_LVT \registers_reg[21][26] ( + .CK(n_0_51), .D(registers[26]), .Q(registers_21__ap[26]), .QN(), .SE(dftIn), + .SI(registers_19__ap[26]) + ); + AOI22_X1_LVT i_1_0_1213( + .A1(registers_19__ap[26]), .A2(n_1_0_1295), .B1(n_1_0_1259), .B2(registers_21__ap[26]), + .ZN(n_1_0_1154) + ); + SDFF_X1_LVT \registers_reg[24][26] ( + .CK(n_0_54), .D(registers[26]), .Q(registers_24__ap[26]), .QN(), .SE(dftIn), + .SI(registers_28__ap[26]) + ); + SDFF_X1_LVT \registers_reg[20][26] ( + .CK(n_0_50), .D(registers[26]), .Q(registers_20__ap[26]), .QN(), .SE(dftIn), + .SI(registers_21__ap[26]) + ); + AOI22_X1_LVT i_1_0_1212( + .A1(registers_24__ap[26]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[26]), + .ZN(n_1_0_1153) + ); + NAND3_X1_LVT i_1_0_1211( + .A1(n_1_0_1155), .A2(n_1_0_1154), .A3(n_1_0_1153), .ZN(n_1_0_1152) + ); + SDFF_X1_LVT \registers_reg[26][26] ( + .CK(n_0_56), .D(registers[26]), .Q(registers_26__ap[26]), .QN(), .SE(dftIn), + .SI(registers_24__ap[26]) + ); + SDFF_X1_LVT \registers_reg[30][26] ( + .CK(n_0_60), .D(registers[26]), .Q(registers_30__ap[26]), .QN(), .SE(dftIn), + .SI(registers_26__ap[26]) + ); + AOI221_X1_LVT i_1_0_1210( + .A(n_1_0_1152), .B1(n_1_0_1285), .B2(registers_26__ap[26]), .C1(registers_30__ap[26]), + .C2(n_1_0_1272), .ZN(n_1_0_1151) + ); + SDFF_X1_LVT \registers_reg[8][26] ( + .CK(n_0_38), .D(registers[26]), .Q(registers_8__ap[26]), .QN(), .SE(dftIn), + .SI(registers_4__ap[26]) + ); + SDFF_X1_LVT \registers_reg[23][26] ( + .CK(n_0_53), .D(registers[26]), .Q(registers_23__ap[26]), .QN(), .SE(dftIn), + .SI(registers_20__ap[26]) + ); + AOI22_X1_LVT i_1_0_1209( + .A1(registers_8__ap[26]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[26]), + .ZN(n_1_0_1150) + ); + SDFF_X1_LVT \registers_reg[13][26] ( + .CK(n_0_43), .D(registers[26]), .Q(registers_13__ap[26]), .QN(), .SE(dftIn), + .SI(registers_12__ap[26]) + ); + SDFF_X1_LVT \registers_reg[17][26] ( + .CK(n_0_47), .D(registers[26]), .Q(registers_17__ap[26]), .QN(), .SE(dftIn), + .SI(registers_23__ap[26]) + ); + AOI22_X1_LVT i_1_0_1208( + .A1(registers_13__ap[26]), .A2(n_1_0_1277), .B1(n_1_0_1271), .B2(registers_17__ap[26]), + .ZN(n_1_0_1149) + ); + SDFF_X1_LVT \registers_reg[15][26] ( + .CK(n_0_45), .D(registers[26]), .Q(registers_15__ap[26]), .QN(), .SE(dftIn), + .SI(registers_13__ap[26]) + ); + SDFF_X1_LVT \registers_reg[14][26] ( + .CK(n_0_44), .D(registers[26]), .Q(registers_14__ap[26]), .QN(), .SE(dftIn), + .SI(registers_15__ap[26]) + ); + AOI22_X1_LVT i_1_0_1207( + .A1(registers_15__ap[26]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[26]), + .ZN(n_1_0_1148) + ); + NAND3_X1_LVT i_1_0_1206( + .A1(n_1_0_1150), .A2(n_1_0_1149), .A3(n_1_0_1148), .ZN(n_1_0_1147) + ); + SDFF_X1_LVT \registers_reg[10][26] ( + .CK(n_0_40), .D(registers[26]), .Q(registers_10__ap[26]), .QN(), .SE(dftIn), + .SI(registers_14__ap[26]) + ); + SDFF_X1_LVT \registers_reg[3][26] ( + .CK(n_0_33), .D(registers[26]), .Q(registers_3__ap[26]), .QN(), .SE(dftIn), + .SI(registers_8__ap[26]) + ); + AOI221_X1_LVT i_1_0_1205( + .A(n_1_0_1147), .B1(n_1_0_1287), .B2(registers_10__ap[26]), .C1(registers_3__ap[26]), + .C2(n_1_0_1257), .ZN(n_1_0_1146) + ); + NAND3_X1_LVT i_1_0_1204( + .A1(n_1_0_1156), .A2(n_1_0_1151), .A3(n_1_0_1146), .ZN(RRs1[26]) + ); + AND2_X1_LVT i_0_0_25( + .A1(n_0_0_16), .A2(WRd[25]), .ZN(registers[25]) + ); + SDFF_X1_LVT \registers_reg[17][25] ( + .CK(n_0_47), .D(registers[25]), .Q(registers_17__ap[25]), .QN(), .SE(dftIn), + .SI(registers_17__ap[26]) + ); + SDFF_X1_LVT \registers_reg[21][25] ( + .CK(n_0_51), .D(registers[25]), .Q(registers_21__ap[25]), .QN(), .SE(dftIn), + .SI(registers_17__ap[25]) + ); + AOI22_X1_LVT i_1_0_1202( + .A1(registers_17__ap[25]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[25]), + .ZN(n_1_0_1144) + ); + SDFF_X1_LVT \registers_reg[6][25] ( + .CK(n_0_36), .D(registers[25]), .Q(registers_6__ap[25]), .QN(), .SE(dftIn), + .SI(registers_3__ap[26]) + ); + SDFF_X1_LVT \registers_reg[8][25] ( + .CK(n_0_38), .D(registers[25]), .Q(registers_8__ap[25]), .QN(), .SE(dftIn), + .SI(registers_6__ap[25]) + ); + AOI22_X1_LVT i_1_0_1203( + .A1(registers_6__ap[25]), .A2(n_1_0_1300), .B1(n_1_0_1282), .B2(registers_8__ap[25]), + .ZN(n_1_0_1145) + ); + SDFF_X1_LVT \registers_reg[20][25] ( + .CK(n_0_50), .D(registers[25]), .Q(registers_20__ap[25]), .QN(), .SE(dftIn), + .SI(registers_21__ap[25]) + ); + SDFF_X1_LVT \registers_reg[12][25] ( + .CK(n_0_42), .D(registers[25]), .Q(registers_12__ap[25]), .QN(), .SE(dftIn), + .SI(registers_10__ap[26]) + ); + AOI22_X1_LVT i_1_0_1201( + .A1(registers_20__ap[25]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[25]), + .ZN(n_1_0_1143) + ); + SDFF_X1_LVT \registers_reg[5][25] ( + .CK(n_0_35), .D(registers[25]), .Q(registers_5__ap[25]), .QN(), .SE(dftIn), + .SI(registers_8__ap[25]) + ); + SDFF_X1_LVT \registers_reg[11][25] ( + .CK(n_0_41), .D(registers[25]), .Q(registers_11__ap[25]), .QN(), .SE(dftIn), + .SI(registers_12__ap[25]) + ); + AOI22_X1_LVT i_1_0_1200( + .A1(registers_5__ap[25]), .A2(n_1_0_1273), .B1(n_1_0_1270), .B2(registers_11__ap[25]), + .ZN(n_1_0_1142) + ); + NAND3_X1_LVT i_1_0_1199( + .A1(n_1_0_1145), .A2(n_1_0_1143), .A3(n_1_0_1142), .ZN(n_1_0_1141) + ); + SDFF_X1_LVT \registers_reg[10][25] ( + .CK(n_0_40), .D(registers[25]), .Q(registers_10__ap[25]), .QN(), .SE(dftIn), + .SI(registers_11__ap[25]) + ); + SDFF_X1_LVT \registers_reg[2][25] ( + .CK(n_0_32), .D(registers[25]), .Q(registers_2__ap[25]), .QN(), .SE(dftIn), + .SI(registers_30__ap[26]) + ); + AOI221_X1_LVT i_1_0_1198( + .A(n_1_0_1141), .B1(n_1_0_1287), .B2(registers_10__ap[25]), .C1(registers_2__ap[25]), + .C2(n_1_0_1268), .ZN(n_1_0_1140) + ); + SDFF_X1_LVT \registers_reg[13][25] ( + .CK(n_0_43), .D(registers[25]), .Q(registers_13__ap[25]), .QN(), .SE(dftIn), + .SI(registers_10__ap[25]) + ); + SDFF_X1_LVT \registers_reg[30][25] ( + .CK(n_0_60), .D(registers[25]), .Q(registers_30__ap[25]), .QN(), .SE(dftIn), + .SI(registers_2__ap[25]) + ); + SDFF_X1_LVT \registers_reg[22][25] ( + .CK(n_0_52), .D(registers[25]), .Q(registers_22__ap[25]), .QN(), .SE(dftIn), + .SI(registers_20__ap[25]) + ); + AOI222_X1_LVT i_1_0_1197( + .A1(registers_13__ap[25]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[25]), + .C1(registers_22__ap[25]), .C2(n_1_0_1294), .ZN(n_1_0_1139) + ); + NAND2_X1_LVT i_1_0_1196( + .A1(n_1_0_1140), .A2(n_1_0_1139), .ZN(n_1_0_1138) + ); + SDFF_X1_LVT \registers_reg[1][25] ( + .CK(n_0_0), .D(registers[25]), .Q(registers_1__ap[25]), .QN(), .SE(dftIn), + .SI(registers_22__ap[25]) + ); + SDFF_X1_LVT \registers_reg[28][25] ( + .CK(n_0_58), .D(registers[25]), .Q(registers_28__ap[25]), .QN(), .SE(dftIn), + .SI(registers_30__ap[25]) + ); + AOI221_X1_LVT i_1_0_1195( + .A(n_1_0_1138), .B1(n_1_0_1274), .B2(registers_1__ap[25]), .C1(registers_28__ap[25]), + .C2(n_1_0_1283), .ZN(n_1_0_1137) + ); + SDFF_X1_LVT \registers_reg[18][25] ( + .CK(n_0_48), .D(registers[25]), .Q(registers_18__ap[25]), .QN(), .SE(dftIn), + .SI(registers_1__ap[25]) + ); + SDFF_X1_LVT \registers_reg[26][25] ( + .CK(n_0_56), .D(registers[25]), .Q(registers_26__ap[25]), .QN(), .SE(dftIn), + .SI(registers_28__ap[25]) + ); + AOI22_X1_LVT i_1_0_1194( + .A1(registers_18__ap[25]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[25]), + .ZN(n_1_0_1136) + ); + SDFF_X1_LVT \registers_reg[24][25] ( + .CK(n_0_54), .D(registers[25]), .Q(registers_24__ap[25]), .QN(), .SE(dftIn), + .SI(registers_26__ap[25]) + ); + SDFF_X1_LVT \registers_reg[4][25] ( + .CK(n_0_34), .D(registers[25]), .Q(registers_4__ap[25]), .QN(), .SE(dftIn), + .SI(registers_5__ap[25]) + ); + AOI22_X1_LVT i_1_0_1193( + .A1(registers_24__ap[25]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[25]), + .ZN(n_1_0_1135) + ); + SDFF_X1_LVT \registers_reg[15][25] ( + .CK(n_0_45), .D(registers[25]), .Q(registers_15__ap[25]), .QN(), .SE(dftIn), + .SI(registers_13__ap[25]) + ); + SDFF_X1_LVT \registers_reg[16][25] ( + .CK(n_0_46), .D(registers[25]), .Q(registers_16__ap[25]), .QN(), .SE(dftIn), + .SI(registers_15__ap[25]) + ); + AOI22_X1_LVT i_1_0_1192( + .A1(registers_15__ap[25]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[25]), + .ZN(n_1_0_1134) + ); + NAND3_X1_LVT i_1_0_1191( + .A1(n_1_0_1136), .A2(n_1_0_1135), .A3(n_1_0_1134), .ZN(n_1_0_1133) + ); + SDFF_X1_LVT \registers_reg[19][25] ( + .CK(n_0_49), .D(registers[25]), .Q(registers_19__ap[25]), .QN(), .SE(dftIn), + .SI(registers_18__ap[25]) + ); + SDFF_X1_LVT \registers_reg[25][25] ( + .CK(n_0_55), .D(registers[25]), .Q(registers_25__ap[25]), .QN(), .SE(dftIn), + .SI(registers_24__ap[25]) + ); + AOI221_X1_LVT i_1_0_1190( + .A(n_1_0_1133), .B1(n_1_0_1295), .B2(registers_19__ap[25]), .C1(registers_25__ap[25]), + .C2(n_1_0_1269), .ZN(n_1_0_1132) + ); + SDFF_X1_LVT \registers_reg[7][25] ( + .CK(n_0_37), .D(registers[25]), .Q(registers_7__ap[25]), .QN(), .SE(dftIn), + .SI(registers_4__ap[25]) + ); + SDFF_X1_LVT \registers_reg[14][25] ( + .CK(n_0_44), .D(registers[25]), .Q(registers_14__ap[25]), .QN(), .SE(dftIn), + .SI(registers_16__ap[25]) + ); + AOI22_X1_LVT i_1_0_1189( + .A1(registers_7__ap[25]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[25]), + .ZN(n_1_0_1131) + ); + SDFF_X1_LVT \registers_reg[9][25] ( + .CK(n_0_39), .D(registers[25]), .Q(registers_9__ap[25]), .QN(), .SE(dftIn), + .SI(registers_7__ap[25]) + ); + SDFF_X1_LVT \registers_reg[29][25] ( + .CK(n_0_59), .D(registers[25]), .Q(registers_29__ap[25]), .QN(), .SE(dftIn), + .SI(registers_25__ap[25]) + ); + AOI22_X1_LVT i_1_0_1188( + .A1(registers_9__ap[25]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[25]), + .ZN(n_1_0_1130) + ); + SDFF_X1_LVT \registers_reg[23][25] ( + .CK(n_0_53), .D(registers[25]), .Q(registers_23__ap[25]), .QN(), .SE(dftIn), + .SI(registers_19__ap[25]) + ); + SDFF_X1_LVT \registers_reg[3][25] ( + .CK(n_0_33), .D(registers[25]), .Q(registers_3__ap[25]), .QN(), .SE(dftIn), + .SI(registers_9__ap[25]) + ); + AOI22_X1_LVT i_1_0_1187( + .A1(registers_23__ap[25]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[25]), + .ZN(n_1_0_1129) + ); + NAND3_X1_LVT i_1_0_1186( + .A1(n_1_0_1131), .A2(n_1_0_1130), .A3(n_1_0_1129), .ZN(n_1_0_1128) + ); + SDFF_X1_LVT \registers_reg[27][25] ( + .CK(n_0_57), .D(registers[25]), .Q(registers_27__ap[25]), .QN(), .SE(dftIn), + .SI(registers_29__ap[25]) + ); + SDFF_X1_LVT \registers_reg[31][25] ( + .CK(n_0_61), .D(registers[25]), .Q(registers_31__ap[25]), .QN(), .SE(dftIn), + .SI(registers_3__ap[25]) + ); + AOI221_X1_LVT i_1_0_1185( + .A(n_1_0_1128), .B1(n_1_0_1279), .B2(registers_27__ap[25]), .C1(registers_31__ap[25]), + .C2(n_1_0_1266), .ZN(n_1_0_1127) + ); + NAND4_X1_LVT i_1_0_1184( + .A1(n_1_0_1144), .A2(n_1_0_1137), .A3(n_1_0_1132), .A4(n_1_0_1127), .ZN(RRs1[25]) + ); + AND2_X1_LVT i_0_0_24( + .A1(n_0_0_16), .A2(WRd[24]), .ZN(registers[24]) + ); + SDFF_X1_LVT \registers_reg[17][24] ( + .CK(n_0_47), .D(registers[24]), .Q(registers_17__ap[24]), .QN(), .SE(dftIn), + .SI(registers_23__ap[25]) + ); + SDFF_X1_LVT \registers_reg[21][24] ( + .CK(n_0_51), .D(registers[24]), .Q(registers_21__ap[24]), .QN(), .SE(dftIn), + .SI(registers_17__ap[24]) + ); + AOI22_X1_LVT i_1_0_1182( + .A1(registers_17__ap[24]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[24]), + .ZN(n_1_0_1125) + ); + SDFF_X1_LVT \registers_reg[6][24] ( + .CK(n_0_36), .D(registers[24]), .Q(registers_6__ap[24]), .QN(), .SE(dftIn), + .SI(registers_31__ap[25]) + ); + SDFF_X1_LVT \registers_reg[8][24] ( + .CK(n_0_38), .D(registers[24]), .Q(registers_8__ap[24]), .QN(), .SE(dftIn), + .SI(registers_6__ap[24]) + ); + AOI22_X1_LVT i_1_0_1183( + .A1(registers_6__ap[24]), .A2(n_1_0_1300), .B1(n_1_0_1282), .B2(registers_8__ap[24]), + .ZN(n_1_0_1126) + ); + SDFF_X1_LVT \registers_reg[20][24] ( + .CK(n_0_50), .D(registers[24]), .Q(registers_20__ap[24]), .QN(), .SE(dftIn), + .SI(registers_21__ap[24]) + ); + SDFF_X1_LVT \registers_reg[12][24] ( + .CK(n_0_42), .D(registers[24]), .Q(registers_12__ap[24]), .QN(), .SE(dftIn), + .SI(registers_14__ap[25]) + ); + AOI22_X1_LVT i_1_0_1181( + .A1(registers_20__ap[24]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[24]), + .ZN(n_1_0_1124) + ); + SDFF_X1_LVT \registers_reg[5][24] ( + .CK(n_0_35), .D(registers[24]), .Q(registers_5__ap[24]), .QN(), .SE(dftIn), + .SI(registers_8__ap[24]) + ); + SDFF_X1_LVT \registers_reg[11][24] ( + .CK(n_0_41), .D(registers[24]), .Q(registers_11__ap[24]), .QN(), .SE(dftIn), + .SI(registers_12__ap[24]) + ); + AOI22_X1_LVT i_1_0_1180( + .A1(registers_5__ap[24]), .A2(n_1_0_1273), .B1(n_1_0_1270), .B2(registers_11__ap[24]), + .ZN(n_1_0_1123) + ); + NAND3_X1_LVT i_1_0_1179( + .A1(n_1_0_1126), .A2(n_1_0_1124), .A3(n_1_0_1123), .ZN(n_1_0_1122) + ); + SDFF_X1_LVT \registers_reg[10][24] ( + .CK(n_0_40), .D(registers[24]), .Q(registers_10__ap[24]), .QN(), .SE(dftIn), + .SI(registers_11__ap[24]) + ); + SDFF_X1_LVT \registers_reg[2][24] ( + .CK(n_0_32), .D(registers[24]), .Q(registers_2__ap[24]), .QN(), .SE(dftIn), + .SI(registers_27__ap[25]) + ); + AOI221_X1_LVT i_1_0_1178( + .A(n_1_0_1122), .B1(n_1_0_1287), .B2(registers_10__ap[24]), .C1(registers_2__ap[24]), + .C2(n_1_0_1268), .ZN(n_1_0_1121) + ); + SDFF_X1_LVT \registers_reg[13][24] ( + .CK(n_0_43), .D(registers[24]), .Q(registers_13__ap[24]), .QN(), .SE(dftIn), + .SI(registers_10__ap[24]) + ); + SDFF_X1_LVT \registers_reg[30][24] ( + .CK(n_0_60), .D(registers[24]), .Q(registers_30__ap[24]), .QN(), .SE(dftIn), + .SI(registers_2__ap[24]) + ); + SDFF_X1_LVT \registers_reg[22][24] ( + .CK(n_0_52), .D(registers[24]), .Q(registers_22__ap[24]), .QN(), .SE(dftIn), + .SI(registers_20__ap[24]) + ); + AOI222_X1_LVT i_1_0_1177( + .A1(registers_13__ap[24]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[24]), + .C1(registers_22__ap[24]), .C2(n_1_0_1294), .ZN(n_1_0_1120) + ); + NAND2_X1_LVT i_1_0_1176( + .A1(n_1_0_1121), .A2(n_1_0_1120), .ZN(n_1_0_1119) + ); + SDFF_X1_LVT \registers_reg[1][24] ( + .CK(n_0_0), .D(registers[24]), .Q(registers_1__ap[24]), .QN(), .SE(dftIn), + .SI(registers_22__ap[24]) + ); + SDFF_X1_LVT \registers_reg[28][24] ( + .CK(n_0_58), .D(registers[24]), .Q(registers_28__ap[24]), .QN(), .SE(dftIn), + .SI(registers_30__ap[24]) + ); + AOI221_X1_LVT i_1_0_1175( + .A(n_1_0_1119), .B1(n_1_0_1274), .B2(registers_1__ap[24]), .C1(registers_28__ap[24]), + .C2(n_1_0_1283), .ZN(n_1_0_1118) + ); + SDFF_X1_LVT \registers_reg[18][24] ( + .CK(n_0_48), .D(registers[24]), .Q(registers_18__ap[24]), .QN(), .SE(dftIn), + .SI(registers_1__ap[24]) + ); + SDFF_X1_LVT \registers_reg[26][24] ( + .CK(n_0_56), .D(registers[24]), .Q(registers_26__ap[24]), .QN(), .SE(dftIn), + .SI(registers_28__ap[24]) + ); + AOI22_X1_LVT i_1_0_1174( + .A1(registers_18__ap[24]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[24]), + .ZN(n_1_0_1117) + ); + SDFF_X1_LVT \registers_reg[24][24] ( + .CK(n_0_54), .D(registers[24]), .Q(registers_24__ap[24]), .QN(), .SE(dftIn), + .SI(registers_26__ap[24]) + ); + SDFF_X1_LVT \registers_reg[4][24] ( + .CK(n_0_34), .D(registers[24]), .Q(registers_4__ap[24]), .QN(), .SE(dftIn), + .SI(registers_5__ap[24]) + ); + AOI22_X1_LVT i_1_0_1173( + .A1(registers_24__ap[24]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[24]), + .ZN(n_1_0_1116) + ); + SDFF_X1_LVT \registers_reg[15][24] ( + .CK(n_0_45), .D(registers[24]), .Q(registers_15__ap[24]), .QN(), .SE(dftIn), + .SI(registers_13__ap[24]) + ); + SDFF_X1_LVT \registers_reg[25][24] ( + .CK(n_0_55), .D(registers[24]), .Q(registers_25__ap[24]), .QN(), .SE(dftIn), + .SI(registers_24__ap[24]) + ); + AOI22_X1_LVT i_1_0_1172( + .A1(registers_15__ap[24]), .A2(n_1_0_1286), .B1(n_1_0_1269), .B2(registers_25__ap[24]), + .ZN(n_1_0_1115) + ); + NAND3_X1_LVT i_1_0_1171( + .A1(n_1_0_1117), .A2(n_1_0_1116), .A3(n_1_0_1115), .ZN(n_1_0_1114) + ); + SDFF_X1_LVT \registers_reg[19][24] ( + .CK(n_0_49), .D(registers[24]), .Q(registers_19__ap[24]), .QN(), .SE(dftIn), + .SI(registers_18__ap[24]) + ); + SDFF_X1_LVT \registers_reg[16][24] ( + .CK(n_0_46), .D(registers[24]), .Q(registers_16__ap[24]), .QN(), .SE(dftIn), + .SI(registers_15__ap[24]) + ); + AOI221_X1_LVT i_1_0_1170( + .A(n_1_0_1114), .B1(n_1_0_1295), .B2(registers_19__ap[24]), .C1(registers_16__ap[24]), + .C2(n_1_0_1267), .ZN(n_1_0_1113) + ); + SDFF_X1_LVT \registers_reg[7][24] ( + .CK(n_0_37), .D(registers[24]), .Q(registers_7__ap[24]), .QN(), .SE(dftIn), + .SI(registers_4__ap[24]) + ); + SDFF_X1_LVT \registers_reg[14][24] ( + .CK(n_0_44), .D(registers[24]), .Q(registers_14__ap[24]), .QN(), .SE(dftIn), + .SI(registers_16__ap[24]) + ); + AOI22_X1_LVT i_1_0_1169( + .A1(registers_7__ap[24]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[24]), + .ZN(n_1_0_1112) + ); + SDFF_X1_LVT \registers_reg[9][24] ( + .CK(n_0_39), .D(registers[24]), .Q(registers_9__ap[24]), .QN(), .SE(dftIn), + .SI(registers_7__ap[24]) + ); + SDFF_X1_LVT \registers_reg[29][24] ( + .CK(n_0_59), .D(registers[24]), .Q(registers_29__ap[24]), .QN(), .SE(dftIn), + .SI(registers_25__ap[24]) + ); + AOI22_X1_LVT i_1_0_1168( + .A1(registers_9__ap[24]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[24]), + .ZN(n_1_0_1111) + ); + SDFF_X1_LVT \registers_reg[23][24] ( + .CK(n_0_53), .D(registers[24]), .Q(registers_23__ap[24]), .QN(), .SE(dftIn), + .SI(registers_19__ap[24]) + ); + SDFF_X1_LVT \registers_reg[3][24] ( + .CK(n_0_33), .D(registers[24]), .Q(registers_3__ap[24]), .QN(), .SE(dftIn), + .SI(registers_9__ap[24]) + ); + AOI22_X1_LVT i_1_0_1167( + .A1(registers_23__ap[24]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[24]), + .ZN(n_1_0_1110) + ); + NAND3_X1_LVT i_1_0_1166( + .A1(n_1_0_1112), .A2(n_1_0_1111), .A3(n_1_0_1110), .ZN(n_1_0_1109) + ); + SDFF_X1_LVT \registers_reg[27][24] ( + .CK(n_0_57), .D(registers[24]), .Q(registers_27__ap[24]), .QN(), .SE(dftIn), + .SI(registers_29__ap[24]) + ); + SDFF_X1_LVT \registers_reg[31][24] ( + .CK(n_0_61), .D(registers[24]), .Q(registers_31__ap[24]), .QN(), .SE(dftIn), + .SI(registers_3__ap[24]) + ); + AOI221_X1_LVT i_1_0_1165( + .A(n_1_0_1109), .B1(n_1_0_1279), .B2(registers_27__ap[24]), .C1(registers_31__ap[24]), + .C2(n_1_0_1266), .ZN(n_1_0_1108) + ); + NAND4_X1_LVT i_1_0_1164( + .A1(n_1_0_1125), .A2(n_1_0_1118), .A3(n_1_0_1113), .A4(n_1_0_1108), .ZN(RRs1[24]) + ); + AND2_X1_LVT i_0_0_23( + .A1(n_0_0_16), .A2(WRd[23]), .ZN(registers[23]) + ); + SDFF_X1_LVT \registers_reg[9][23] ( + .CK(n_0_39), .D(registers[23]), .Q(registers_9__ap[23]), .QN(), .SE(dftIn), + .SI(registers_31__ap[24]) + ); + SDFF_X1_LVT \registers_reg[28][23] ( + .CK(n_0_58), .D(registers[23]), .Q(registers_28__ap[23]), .QN(), .SE(dftIn), + .SI(registers_27__ap[24]) + ); + AOI22_X1_LVT i_1_0_1163( + .A1(registers_9__ap[23]), .A2(n_1_0_1291), .B1(n_1_0_1283), .B2(registers_28__ap[23]), + .ZN(n_1_0_1107) + ); + SDFF_X1_LVT \registers_reg[18][23] ( + .CK(n_0_48), .D(registers[23]), .Q(registers_18__ap[23]), .QN(), .SE(dftIn), + .SI(registers_23__ap[24]) + ); + SDFF_X1_LVT \registers_reg[22][23] ( + .CK(n_0_52), .D(registers[23]), .Q(registers_22__ap[23]), .QN(), .SE(dftIn), + .SI(registers_18__ap[23]) + ); + AOI22_X1_LVT i_1_0_1160( + .A1(registers_18__ap[23]), .A2(n_1_0_1297), .B1(n_1_0_1294), .B2(registers_22__ap[23]), + .ZN(n_1_0_1104) + ); + SDFF_X1_LVT \registers_reg[1][23] ( + .CK(n_0_0), .D(registers[23]), .Q(registers_1__ap[23]), .QN(), .SE(dftIn), + .SI(registers_22__ap[23]) + ); + SDFF_X1_LVT \registers_reg[21][23] ( + .CK(n_0_51), .D(registers[23]), .Q(registers_21__ap[23]), .QN(), .SE(dftIn), + .SI(registers_1__ap[23]) + ); + AOI22_X1_LVT i_1_0_1159( + .A1(registers_1__ap[23]), .A2(n_1_0_1274), .B1(n_1_0_1259), .B2(registers_21__ap[23]), + .ZN(n_1_0_1103) + ); + NAND3_X1_LVT i_1_0_1157( + .A1(n_1_0_1107), .A2(n_1_0_1104), .A3(n_1_0_1103), .ZN(n_1_0_1101) + ); + SDFF_X1_LVT \registers_reg[20][23] ( + .CK(n_0_50), .D(registers[23]), .Q(registers_20__ap[23]), .QN(), .SE(dftIn), + .SI(registers_21__ap[23]) + ); + SDFF_X1_LVT \registers_reg[19][23] ( + .CK(n_0_49), .D(registers[23]), .Q(registers_19__ap[23]), .QN(), .SE(dftIn), + .SI(registers_20__ap[23]) + ); + AOI221_X1_LVT i_1_0_1156( + .A(n_1_0_1101), .B1(n_1_0_1281), .B2(registers_20__ap[23]), .C1(registers_19__ap[23]), + .C2(n_1_0_1295), .ZN(n_1_0_1100) + ); + SDFF_X1_LVT \registers_reg[26][23] ( + .CK(n_0_56), .D(registers[23]), .Q(registers_26__ap[23]), .QN(), .SE(dftIn), + .SI(registers_28__ap[23]) + ); + SDFF_X1_LVT \registers_reg[23][23] ( + .CK(n_0_53), .D(registers[23]), .Q(registers_23__ap[23]), .QN(), .SE(dftIn), + .SI(registers_19__ap[23]) + ); + AOI22_X1_LVT i_1_0_1162( + .A1(registers_26__ap[23]), .A2(n_1_0_1285), .B1(n_1_0_1264), .B2(registers_23__ap[23]), + .ZN(n_1_0_1106) + ); + SDFF_X1_LVT \registers_reg[29][23] ( + .CK(n_0_59), .D(registers[23]), .Q(registers_29__ap[23]), .QN(), .SE(dftIn), + .SI(registers_26__ap[23]) + ); + SDFF_X1_LVT \registers_reg[3][23] ( + .CK(n_0_33), .D(registers[23]), .Q(registers_3__ap[23]), .QN(), .SE(dftIn), + .SI(registers_9__ap[23]) + ); + AOI22_X1_LVT i_1_0_1161( + .A1(registers_29__ap[23]), .A2(n_1_0_1276), .B1(n_1_0_1257), .B2(registers_3__ap[23]), + .ZN(n_1_0_1105) + ); + SDFF_X1_LVT \registers_reg[30][23] ( + .CK(n_0_60), .D(registers[23]), .Q(registers_30__ap[23]), .QN(), .SE(dftIn), + .SI(registers_29__ap[23]) + ); + SDFF_X1_LVT \registers_reg[31][23] ( + .CK(n_0_61), .D(registers[23]), .Q(registers_31__ap[23]), .QN(), .SE(dftIn), + .SI(registers_3__ap[23]) + ); + AOI22_X1_LVT i_1_0_1158( + .A1(registers_30__ap[23]), .A2(n_1_0_1272), .B1(n_1_0_1266), .B2(registers_31__ap[23]), + .ZN(n_1_0_1102) + ); + NAND3_X1_LVT i_1_0_1155( + .A1(n_1_0_1106), .A2(n_1_0_1105), .A3(n_1_0_1102), .ZN(n_1_0_1099) + ); + SDFF_X1_LVT \registers_reg[8][23] ( + .CK(n_0_38), .D(registers[23]), .Q(registers_8__ap[23]), .QN(), .SE(dftIn), + .SI(registers_31__ap[23]) + ); + SDFF_X1_LVT \registers_reg[17][23] ( + .CK(n_0_47), .D(registers[23]), .Q(registers_17__ap[23]), .QN(), .SE(dftIn), + .SI(registers_23__ap[23]) + ); + AOI221_X1_LVT i_1_0_1154( + .A(n_1_0_1099), .B1(n_1_0_1282), .B2(registers_8__ap[23]), .C1(registers_17__ap[23]), + .C2(n_1_0_1271), .ZN(n_1_0_1098) + ); + SDFF_X1_LVT \registers_reg[24][23] ( + .CK(n_0_54), .D(registers[23]), .Q(registers_24__ap[23]), .QN(), .SE(dftIn), + .SI(registers_30__ap[23]) + ); + SDFF_X1_LVT \registers_reg[15][23] ( + .CK(n_0_45), .D(registers[23]), .Q(registers_15__ap[23]), .QN(), .SE(dftIn), + .SI(registers_14__ap[24]) + ); + SDFF_X1_LVT \registers_reg[14][23] ( + .CK(n_0_44), .D(registers[23]), .Q(registers_14__ap[23]), .QN(), .SE(dftIn), + .SI(registers_15__ap[23]) + ); + AOI222_X1_LVT i_1_0_1153( + .A1(registers_24__ap[23]), .A2(n_1_0_1289), .B1(n_1_0_1286), .B2(registers_15__ap[23]), + .C1(n_1_0_1258), .C2(registers_14__ap[23]), .ZN(n_1_0_1097) + ); + SDFF_X1_LVT \registers_reg[16][23] ( + .CK(n_0_46), .D(registers[23]), .Q(registers_16__ap[23]), .QN(), .SE(dftIn), + .SI(registers_14__ap[23]) + ); + SDFF_X1_LVT \registers_reg[7][23] ( + .CK(n_0_37), .D(registers[23]), .Q(registers_7__ap[23]), .QN(), .SE(dftIn), + .SI(registers_8__ap[23]) + ); + AOI22_X1_LVT i_1_0_1152( + .A1(registers_16__ap[23]), .A2(n_1_0_1267), .B1(n_1_0_1263), .B2(registers_7__ap[23]), + .ZN(n_1_0_1096) + ); + SDFF_X1_LVT \registers_reg[6][23] ( + .CK(n_0_36), .D(registers[23]), .Q(registers_6__ap[23]), .QN(), .SE(dftIn), + .SI(registers_7__ap[23]) + ); + SDFF_X1_LVT \registers_reg[25][23] ( + .CK(n_0_55), .D(registers[23]), .Q(registers_25__ap[23]), .QN(), .SE(dftIn), + .SI(registers_24__ap[23]) + ); + AOI22_X1_LVT i_1_0_1151( + .A1(registers_6__ap[23]), .A2(n_1_0_1300), .B1(n_1_0_1269), .B2(registers_25__ap[23]), + .ZN(n_1_0_1095) + ); + SDFF_X1_LVT \registers_reg[27][23] ( + .CK(n_0_57), .D(registers[23]), .Q(registers_27__ap[23]), .QN(), .SE(dftIn), + .SI(registers_25__ap[23]) + ); + SDFF_X1_LVT \registers_reg[11][23] ( + .CK(n_0_41), .D(registers[23]), .Q(registers_11__ap[23]), .QN(), .SE(dftIn), + .SI(registers_16__ap[23]) + ); + AOI22_X1_LVT i_1_0_1150( + .A1(registers_27__ap[23]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[23]), + .ZN(n_1_0_1094) + ); + SDFF_X1_LVT \registers_reg[13][23] ( + .CK(n_0_43), .D(registers[23]), .Q(registers_13__ap[23]), .QN(), .SE(dftIn), + .SI(registers_11__ap[23]) + ); + SDFF_X1_LVT \registers_reg[5][23] ( + .CK(n_0_35), .D(registers[23]), .Q(registers_5__ap[23]), .QN(), .SE(dftIn), + .SI(registers_6__ap[23]) + ); + AOI22_X1_LVT i_1_0_1149( + .A1(registers_13__ap[23]), .A2(n_1_0_1277), .B1(n_1_0_1273), .B2(registers_5__ap[23]), + .ZN(n_1_0_1093) + ); + SDFF_X1_LVT \registers_reg[4][23] ( + .CK(n_0_34), .D(registers[23]), .Q(registers_4__ap[23]), .QN(), .SE(dftIn), + .SI(registers_5__ap[23]) + ); + SDFF_X1_LVT \registers_reg[12][23] ( + .CK(n_0_42), .D(registers[23]), .Q(registers_12__ap[23]), .QN(), .SE(dftIn), + .SI(registers_13__ap[23]) + ); + AOI22_X1_LVT i_1_0_1148( + .A1(registers_4__ap[23]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[23]), + .ZN(n_1_0_1092) + ); + NAND3_X1_LVT i_1_0_1147( + .A1(n_1_0_1094), .A2(n_1_0_1093), .A3(n_1_0_1092), .ZN(n_1_0_1091) + ); + SDFF_X1_LVT \registers_reg[2][23] ( + .CK(n_0_32), .D(registers[23]), .Q(registers_2__ap[23]), .QN(), .SE(dftIn), + .SI(registers_27__ap[23]) + ); + SDFF_X1_LVT \registers_reg[10][23] ( + .CK(n_0_40), .D(registers[23]), .Q(registers_10__ap[23]), .QN(), .SE(dftIn), + .SI(registers_12__ap[23]) + ); + AOI221_X1_LVT i_1_0_1146( + .A(n_1_0_1091), .B1(n_1_0_1268), .B2(registers_2__ap[23]), .C1(registers_10__ap[23]), + .C2(n_1_0_1287), .ZN(n_1_0_1090) + ); + AND4_X1_LVT i_1_0_1145( + .A1(n_1_0_1097), .A2(n_1_0_1096), .A3(n_1_0_1095), .A4(n_1_0_1090), .ZN(n_1_0_1089) + ); + NAND3_X1_LVT i_1_0_1144( + .A1(n_1_0_1100), .A2(n_1_0_1098), .A3(n_1_0_1089), .ZN(RRs1[23]) + ); + AND2_X1_LVT i_0_0_22( + .A1(n_0_0_16), .A2(WRd[22]), .ZN(registers[22]) + ); + SDFF_X1_LVT \registers_reg[17][22] ( + .CK(n_0_47), .D(registers[22]), .Q(registers_17__ap[22]), .QN(), .SE(dftIn), + .SI(registers_17__ap[23]) + ); + SDFF_X1_LVT \registers_reg[21][22] ( + .CK(n_0_51), .D(registers[22]), .Q(registers_21__ap[22]), .QN(), .SE(dftIn), + .SI(registers_17__ap[22]) + ); + AOI22_X1_LVT i_1_0_1142( + .A1(registers_17__ap[22]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[22]), + .ZN(n_1_0_1087) + ); + SDFF_X1_LVT \registers_reg[6][22] ( + .CK(n_0_36), .D(registers[22]), .Q(registers_6__ap[22]), .QN(), .SE(dftIn), + .SI(registers_4__ap[23]) + ); + SDFF_X1_LVT \registers_reg[11][22] ( + .CK(n_0_41), .D(registers[22]), .Q(registers_11__ap[22]), .QN(), .SE(dftIn), + .SI(registers_10__ap[23]) + ); + AOI22_X1_LVT i_1_0_1143( + .A1(registers_6__ap[22]), .A2(n_1_0_1300), .B1(n_1_0_1270), .B2(registers_11__ap[22]), + .ZN(n_1_0_1088) + ); + SDFF_X1_LVT \registers_reg[20][22] ( + .CK(n_0_50), .D(registers[22]), .Q(registers_20__ap[22]), .QN(), .SE(dftIn), + .SI(registers_21__ap[22]) + ); + SDFF_X1_LVT \registers_reg[12][22] ( + .CK(n_0_42), .D(registers[22]), .Q(registers_12__ap[22]), .QN(), .SE(dftIn), + .SI(registers_11__ap[22]) + ); + AOI22_X1_LVT i_1_0_1141( + .A1(registers_20__ap[22]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[22]), + .ZN(n_1_0_1086) + ); + SDFF_X1_LVT \registers_reg[10][22] ( + .CK(n_0_40), .D(registers[22]), .Q(registers_10__ap[22]), .QN(), .SE(dftIn), + .SI(registers_12__ap[22]) + ); + SDFF_X1_LVT \registers_reg[5][22] ( + .CK(n_0_35), .D(registers[22]), .Q(registers_5__ap[22]), .QN(), .SE(dftIn), + .SI(registers_6__ap[22]) + ); + AOI22_X1_LVT i_1_0_1140( + .A1(registers_10__ap[22]), .A2(n_1_0_1287), .B1(n_1_0_1273), .B2(registers_5__ap[22]), + .ZN(n_1_0_1085) + ); + NAND3_X1_LVT i_1_0_1139( + .A1(n_1_0_1088), .A2(n_1_0_1086), .A3(n_1_0_1085), .ZN(n_1_0_1084) + ); + SDFF_X1_LVT \registers_reg[31][22] ( + .CK(n_0_61), .D(registers[22]), .Q(registers_31__ap[22]), .QN(), .SE(dftIn), + .SI(registers_5__ap[22]) + ); + SDFF_X1_LVT \registers_reg[2][22] ( + .CK(n_0_32), .D(registers[22]), .Q(registers_2__ap[22]), .QN(), .SE(dftIn), + .SI(registers_2__ap[23]) + ); + AOI221_X1_LVT i_1_0_1138( + .A(n_1_0_1084), .B1(n_1_0_1266), .B2(registers_31__ap[22]), .C1(registers_2__ap[22]), + .C2(n_1_0_1268), .ZN(n_1_0_1083) + ); + SDFF_X1_LVT \registers_reg[22][22] ( + .CK(n_0_52), .D(registers[22]), .Q(registers_22__ap[22]), .QN(), .SE(dftIn), + .SI(registers_20__ap[22]) + ); + SDFF_X1_LVT \registers_reg[26][22] ( + .CK(n_0_56), .D(registers[22]), .Q(registers_26__ap[22]), .QN(), .SE(dftIn), + .SI(registers_2__ap[22]) + ); + SDFF_X1_LVT \registers_reg[13][22] ( + .CK(n_0_43), .D(registers[22]), .Q(registers_13__ap[22]), .QN(), .SE(dftIn), + .SI(registers_10__ap[22]) + ); + AOI222_X1_LVT i_1_0_1137( + .A1(registers_22__ap[22]), .A2(n_1_0_1294), .B1(n_1_0_1285), .B2(registers_26__ap[22]), + .C1(n_1_0_1277), .C2(registers_13__ap[22]), .ZN(n_1_0_1082) + ); + NAND2_X1_LVT i_1_0_1136( + .A1(n_1_0_1083), .A2(n_1_0_1082), .ZN(n_1_0_1081) + ); + SDFF_X1_LVT \registers_reg[1][22] ( + .CK(n_0_0), .D(registers[22]), .Q(registers_1__ap[22]), .QN(), .SE(dftIn), + .SI(registers_22__ap[22]) + ); + SDFF_X1_LVT \registers_reg[28][22] ( + .CK(n_0_58), .D(registers[22]), .Q(registers_28__ap[22]), .QN(), .SE(dftIn), + .SI(registers_26__ap[22]) + ); + AOI221_X1_LVT i_1_0_1135( + .A(n_1_0_1081), .B1(n_1_0_1274), .B2(registers_1__ap[22]), .C1(registers_28__ap[22]), + .C2(n_1_0_1283), .ZN(n_1_0_1080) + ); + SDFF_X1_LVT \registers_reg[18][22] ( + .CK(n_0_48), .D(registers[22]), .Q(registers_18__ap[22]), .QN(), .SE(dftIn), + .SI(registers_1__ap[22]) + ); + SDFF_X1_LVT \registers_reg[30][22] ( + .CK(n_0_60), .D(registers[22]), .Q(registers_30__ap[22]), .QN(), .SE(dftIn), + .SI(registers_28__ap[22]) + ); + AOI22_X1_LVT i_1_0_1134( + .A1(registers_18__ap[22]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[22]), + .ZN(n_1_0_1079) + ); + SDFF_X1_LVT \registers_reg[24][22] ( + .CK(n_0_54), .D(registers[22]), .Q(registers_24__ap[22]), .QN(), .SE(dftIn), + .SI(registers_30__ap[22]) + ); + SDFF_X1_LVT \registers_reg[4][22] ( + .CK(n_0_34), .D(registers[22]), .Q(registers_4__ap[22]), .QN(), .SE(dftIn), + .SI(registers_31__ap[22]) + ); + AOI22_X1_LVT i_1_0_1133( + .A1(registers_24__ap[22]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[22]), + .ZN(n_1_0_1078) + ); + SDFF_X1_LVT \registers_reg[15][22] ( + .CK(n_0_45), .D(registers[22]), .Q(registers_15__ap[22]), .QN(), .SE(dftIn), + .SI(registers_13__ap[22]) + ); + SDFF_X1_LVT \registers_reg[16][22] ( + .CK(n_0_46), .D(registers[22]), .Q(registers_16__ap[22]), .QN(), .SE(dftIn), + .SI(registers_15__ap[22]) + ); + AOI22_X1_LVT i_1_0_1132( + .A1(registers_15__ap[22]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[22]), + .ZN(n_1_0_1077) + ); + NAND3_X1_LVT i_1_0_1131( + .A1(n_1_0_1079), .A2(n_1_0_1078), .A3(n_1_0_1077), .ZN(n_1_0_1076) + ); + SDFF_X1_LVT \registers_reg[19][22] ( + .CK(n_0_49), .D(registers[22]), .Q(registers_19__ap[22]), .QN(), .SE(dftIn), + .SI(registers_18__ap[22]) + ); + SDFF_X1_LVT \registers_reg[25][22] ( + .CK(n_0_55), .D(registers[22]), .Q(registers_25__ap[22]), .QN(), .SE(dftIn), + .SI(registers_24__ap[22]) + ); + AOI221_X1_LVT i_1_0_1130( + .A(n_1_0_1076), .B1(n_1_0_1295), .B2(registers_19__ap[22]), .C1(registers_25__ap[22]), + .C2(n_1_0_1269), .ZN(n_1_0_1075) + ); + SDFF_X1_LVT \registers_reg[7][22] ( + .CK(n_0_37), .D(registers[22]), .Q(registers_7__ap[22]), .QN(), .SE(dftIn), + .SI(registers_4__ap[22]) + ); + SDFF_X1_LVT \registers_reg[14][22] ( + .CK(n_0_44), .D(registers[22]), .Q(registers_14__ap[22]), .QN(), .SE(dftIn), + .SI(registers_16__ap[22]) + ); + AOI22_X1_LVT i_1_0_1129( + .A1(registers_7__ap[22]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[22]), + .ZN(n_1_0_1074) + ); + SDFF_X1_LVT \registers_reg[9][22] ( + .CK(n_0_39), .D(registers[22]), .Q(registers_9__ap[22]), .QN(), .SE(dftIn), + .SI(registers_7__ap[22]) + ); + SDFF_X1_LVT \registers_reg[29][22] ( + .CK(n_0_59), .D(registers[22]), .Q(registers_29__ap[22]), .QN(), .SE(dftIn), + .SI(registers_25__ap[22]) + ); + AOI22_X1_LVT i_1_0_1128( + .A1(registers_9__ap[22]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[22]), + .ZN(n_1_0_1073) + ); + SDFF_X1_LVT \registers_reg[8][22] ( + .CK(n_0_38), .D(registers[22]), .Q(registers_8__ap[22]), .QN(), .SE(dftIn), + .SI(registers_9__ap[22]) + ); + SDFF_X1_LVT \registers_reg[23][22] ( + .CK(n_0_53), .D(registers[22]), .Q(registers_23__ap[22]), .QN(), .SE(dftIn), + .SI(registers_19__ap[22]) + ); + AOI22_X1_LVT i_1_0_1127( + .A1(registers_8__ap[22]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[22]), + .ZN(n_1_0_1072) + ); + NAND3_X1_LVT i_1_0_1126( + .A1(n_1_0_1074), .A2(n_1_0_1073), .A3(n_1_0_1072), .ZN(n_1_0_1071) + ); + SDFF_X1_LVT \registers_reg[27][22] ( + .CK(n_0_57), .D(registers[22]), .Q(registers_27__ap[22]), .QN(), .SE(dftIn), + .SI(registers_29__ap[22]) + ); + SDFF_X1_LVT \registers_reg[3][22] ( + .CK(n_0_33), .D(registers[22]), .Q(registers_3__ap[22]), .QN(), .SE(dftIn), + .SI(registers_8__ap[22]) + ); + AOI221_X1_LVT i_1_0_1125( + .A(n_1_0_1071), .B1(n_1_0_1279), .B2(registers_27__ap[22]), .C1(registers_3__ap[22]), + .C2(n_1_0_1257), .ZN(n_1_0_1070) + ); + NAND4_X1_LVT i_1_0_1124( + .A1(n_1_0_1087), .A2(n_1_0_1080), .A3(n_1_0_1075), .A4(n_1_0_1070), .ZN(RRs1[22]) + ); + AND2_X1_LVT i_0_0_21( + .A1(n_0_0_16), .A2(WRd[21]), .ZN(registers[21]) + ); + SDFF_X1_LVT \registers_reg[17][21] ( + .CK(n_0_47), .D(registers[21]), .Q(registers_17__ap[21]), .QN(), .SE(dftIn), + .SI(registers_23__ap[22]) + ); + SDFF_X1_LVT \registers_reg[21][21] ( + .CK(n_0_51), .D(registers[21]), .Q(registers_21__ap[21]), .QN(), .SE(dftIn), + .SI(registers_17__ap[21]) + ); + AOI22_X1_LVT i_1_0_1122( + .A1(registers_17__ap[21]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[21]), + .ZN(n_1_0_1068) + ); + SDFF_X1_LVT \registers_reg[6][21] ( + .CK(n_0_36), .D(registers[21]), .Q(registers_6__ap[21]), .QN(), .SE(dftIn), + .SI(registers_3__ap[22]) + ); + SDFF_X1_LVT \registers_reg[8][21] ( + .CK(n_0_38), .D(registers[21]), .Q(registers_8__ap[21]), .QN(), .SE(dftIn), + .SI(registers_6__ap[21]) + ); + AOI22_X1_LVT i_1_0_1123( + .A1(registers_6__ap[21]), .A2(n_1_0_1300), .B1(n_1_0_1282), .B2(registers_8__ap[21]), + .ZN(n_1_0_1069) + ); + SDFF_X1_LVT \registers_reg[20][21] ( + .CK(n_0_50), .D(registers[21]), .Q(registers_20__ap[21]), .QN(), .SE(dftIn), + .SI(registers_21__ap[21]) + ); + SDFF_X1_LVT \registers_reg[12][21] ( + .CK(n_0_42), .D(registers[21]), .Q(registers_12__ap[21]), .QN(), .SE(dftIn), + .SI(registers_14__ap[22]) + ); + AOI22_X1_LVT i_1_0_1121( + .A1(registers_20__ap[21]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[21]), + .ZN(n_1_0_1067) + ); + SDFF_X1_LVT \registers_reg[5][21] ( + .CK(n_0_35), .D(registers[21]), .Q(registers_5__ap[21]), .QN(), .SE(dftIn), + .SI(registers_8__ap[21]) + ); + SDFF_X1_LVT \registers_reg[11][21] ( + .CK(n_0_41), .D(registers[21]), .Q(registers_11__ap[21]), .QN(), .SE(dftIn), + .SI(registers_12__ap[21]) + ); + AOI22_X1_LVT i_1_0_1120( + .A1(registers_5__ap[21]), .A2(n_1_0_1273), .B1(n_1_0_1270), .B2(registers_11__ap[21]), + .ZN(n_1_0_1066) + ); + NAND3_X1_LVT i_1_0_1119( + .A1(n_1_0_1069), .A2(n_1_0_1067), .A3(n_1_0_1066), .ZN(n_1_0_1065) + ); + SDFF_X1_LVT \registers_reg[10][21] ( + .CK(n_0_40), .D(registers[21]), .Q(registers_10__ap[21]), .QN(), .SE(dftIn), + .SI(registers_11__ap[21]) + ); + SDFF_X1_LVT \registers_reg[2][21] ( + .CK(n_0_32), .D(registers[21]), .Q(registers_2__ap[21]), .QN(), .SE(dftIn), + .SI(registers_27__ap[22]) + ); + AOI221_X1_LVT i_1_0_1118( + .A(n_1_0_1065), .B1(n_1_0_1287), .B2(registers_10__ap[21]), .C1(registers_2__ap[21]), + .C2(n_1_0_1268), .ZN(n_1_0_1064) + ); + SDFF_X1_LVT \registers_reg[13][21] ( + .CK(n_0_43), .D(registers[21]), .Q(registers_13__ap[21]), .QN(), .SE(dftIn), + .SI(registers_10__ap[21]) + ); + SDFF_X1_LVT \registers_reg[30][21] ( + .CK(n_0_60), .D(registers[21]), .Q(registers_30__ap[21]), .QN(), .SE(dftIn), + .SI(registers_2__ap[21]) + ); + SDFF_X1_LVT \registers_reg[22][21] ( + .CK(n_0_52), .D(registers[21]), .Q(registers_22__ap[21]), .QN(), .SE(dftIn), + .SI(registers_20__ap[21]) + ); + AOI222_X1_LVT i_1_0_1117( + .A1(registers_13__ap[21]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[21]), + .C1(registers_22__ap[21]), .C2(n_1_0_1294), .ZN(n_1_0_1063) + ); + NAND2_X1_LVT i_1_0_1116( + .A1(n_1_0_1064), .A2(n_1_0_1063), .ZN(n_1_0_1062) + ); + SDFF_X1_LVT \registers_reg[1][21] ( + .CK(n_0_0), .D(registers[21]), .Q(registers_1__ap[21]), .QN(), .SE(dftIn), + .SI(registers_22__ap[21]) + ); + SDFF_X1_LVT \registers_reg[28][21] ( + .CK(n_0_58), .D(registers[21]), .Q(registers_28__ap[21]), .QN(), .SE(dftIn), + .SI(registers_30__ap[21]) + ); + AOI221_X1_LVT i_1_0_1115( + .A(n_1_0_1062), .B1(n_1_0_1274), .B2(registers_1__ap[21]), .C1(registers_28__ap[21]), + .C2(n_1_0_1283), .ZN(n_1_0_1061) + ); + SDFF_X1_LVT \registers_reg[18][21] ( + .CK(n_0_48), .D(registers[21]), .Q(registers_18__ap[21]), .QN(), .SE(dftIn), + .SI(registers_1__ap[21]) + ); + SDFF_X1_LVT \registers_reg[26][21] ( + .CK(n_0_56), .D(registers[21]), .Q(registers_26__ap[21]), .QN(), .SE(dftIn), + .SI(registers_28__ap[21]) + ); + AOI22_X1_LVT i_1_0_1114( + .A1(registers_18__ap[21]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[21]), + .ZN(n_1_0_1060) + ); + SDFF_X1_LVT \registers_reg[24][21] ( + .CK(n_0_54), .D(registers[21]), .Q(registers_24__ap[21]), .QN(), .SE(dftIn), + .SI(registers_26__ap[21]) + ); + SDFF_X1_LVT \registers_reg[4][21] ( + .CK(n_0_34), .D(registers[21]), .Q(registers_4__ap[21]), .QN(), .SE(dftIn), + .SI(registers_5__ap[21]) + ); + AOI22_X1_LVT i_1_0_1113( + .A1(registers_24__ap[21]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[21]), + .ZN(n_1_0_1059) + ); + SDFF_X1_LVT \registers_reg[15][21] ( + .CK(n_0_45), .D(registers[21]), .Q(registers_15__ap[21]), .QN(), .SE(dftIn), + .SI(registers_13__ap[21]) + ); + SDFF_X1_LVT \registers_reg[16][21] ( + .CK(n_0_46), .D(registers[21]), .Q(registers_16__ap[21]), .QN(), .SE(dftIn), + .SI(registers_15__ap[21]) + ); + AOI22_X1_LVT i_1_0_1112( + .A1(registers_15__ap[21]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[21]), + .ZN(n_1_0_1058) + ); + NAND3_X1_LVT i_1_0_1111( + .A1(n_1_0_1060), .A2(n_1_0_1059), .A3(n_1_0_1058), .ZN(n_1_0_1057) + ); + SDFF_X1_LVT \registers_reg[19][21] ( + .CK(n_0_49), .D(registers[21]), .Q(registers_19__ap[21]), .QN(), .SE(dftIn), + .SI(registers_18__ap[21]) + ); + SDFF_X1_LVT \registers_reg[25][21] ( + .CK(n_0_55), .D(registers[21]), .Q(registers_25__ap[21]), .QN(), .SE(dftIn), + .SI(registers_24__ap[21]) + ); + AOI221_X1_LVT i_1_0_1110( + .A(n_1_0_1057), .B1(n_1_0_1295), .B2(registers_19__ap[21]), .C1(registers_25__ap[21]), + .C2(n_1_0_1269), .ZN(n_1_0_1056) + ); + SDFF_X1_LVT \registers_reg[7][21] ( + .CK(n_0_37), .D(registers[21]), .Q(registers_7__ap[21]), .QN(), .SE(dftIn), + .SI(registers_4__ap[21]) + ); + SDFF_X1_LVT \registers_reg[14][21] ( + .CK(n_0_44), .D(registers[21]), .Q(registers_14__ap[21]), .QN(), .SE(dftIn), + .SI(registers_16__ap[21]) + ); + AOI22_X1_LVT i_1_0_1109( + .A1(registers_7__ap[21]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[21]), + .ZN(n_1_0_1055) + ); + SDFF_X1_LVT \registers_reg[9][21] ( + .CK(n_0_39), .D(registers[21]), .Q(registers_9__ap[21]), .QN(), .SE(dftIn), + .SI(registers_7__ap[21]) + ); + SDFF_X1_LVT \registers_reg[29][21] ( + .CK(n_0_59), .D(registers[21]), .Q(registers_29__ap[21]), .QN(), .SE(dftIn), + .SI(registers_25__ap[21]) + ); + AOI22_X1_LVT i_1_0_1108( + .A1(registers_9__ap[21]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[21]), + .ZN(n_1_0_1054) + ); + SDFF_X1_LVT \registers_reg[23][21] ( + .CK(n_0_53), .D(registers[21]), .Q(registers_23__ap[21]), .QN(), .SE(dftIn), + .SI(registers_19__ap[21]) + ); + SDFF_X1_LVT \registers_reg[3][21] ( + .CK(n_0_33), .D(registers[21]), .Q(registers_3__ap[21]), .QN(), .SE(dftIn), + .SI(registers_9__ap[21]) + ); + AOI22_X1_LVT i_1_0_1107( + .A1(registers_23__ap[21]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[21]), + .ZN(n_1_0_1053) + ); + NAND3_X1_LVT i_1_0_1106( + .A1(n_1_0_1055), .A2(n_1_0_1054), .A3(n_1_0_1053), .ZN(n_1_0_1052) + ); + SDFF_X1_LVT \registers_reg[27][21] ( + .CK(n_0_57), .D(registers[21]), .Q(registers_27__ap[21]), .QN(), .SE(dftIn), + .SI(registers_29__ap[21]) + ); + SDFF_X1_LVT \registers_reg[31][21] ( + .CK(n_0_61), .D(registers[21]), .Q(registers_31__ap[21]), .QN(), .SE(dftIn), + .SI(registers_3__ap[21]) + ); + AOI221_X1_LVT i_1_0_1105( + .A(n_1_0_1052), .B1(n_1_0_1279), .B2(registers_27__ap[21]), .C1(registers_31__ap[21]), + .C2(n_1_0_1266), .ZN(n_1_0_1051) + ); + NAND4_X1_LVT i_1_0_1104( + .A1(n_1_0_1068), .A2(n_1_0_1061), .A3(n_1_0_1056), .A4(n_1_0_1051), .ZN(RRs1[21]) + ); + AND2_X1_LVT i_0_0_20( + .A1(n_0_0_16), .A2(WRd[20]), .ZN(registers[20]) + ); + SDFF_X1_LVT \registers_reg[17][20] ( + .CK(n_0_47), .D(registers[20]), .Q(registers_17__ap[20]), .QN(), .SE(dftIn), + .SI(registers_23__ap[21]) + ); + SDFF_X1_LVT \registers_reg[21][20] ( + .CK(n_0_51), .D(registers[20]), .Q(registers_21__ap[20]), .QN(), .SE(dftIn), + .SI(registers_17__ap[20]) + ); + AOI22_X1_LVT i_1_0_1100( + .A1(registers_17__ap[20]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[20]), + .ZN(n_1_0_1047) + ); + SDFF_X1_LVT \registers_reg[10][20] ( + .CK(n_0_40), .D(registers[20]), .Q(registers_10__ap[20]), .QN(), .SE(dftIn), + .SI(registers_14__ap[21]) + ); + SDFF_X1_LVT \registers_reg[2][20] ( + .CK(n_0_32), .D(registers[20]), .Q(registers_2__ap[20]), .QN(), .SE(dftIn), + .SI(registers_27__ap[21]) + ); + AOI22_X1_LVT i_1_0_1103( + .A1(registers_10__ap[20]), .A2(n_1_0_1287), .B1(n_1_0_1268), .B2(registers_2__ap[20]), + .ZN(n_1_0_1050) + ); + SDFF_X1_LVT \registers_reg[20][20] ( + .CK(n_0_50), .D(registers[20]), .Q(registers_20__ap[20]), .QN(), .SE(dftIn), + .SI(registers_21__ap[20]) + ); + SDFF_X1_LVT \registers_reg[12][20] ( + .CK(n_0_42), .D(registers[20]), .Q(registers_12__ap[20]), .QN(), .SE(dftIn), + .SI(registers_10__ap[20]) + ); + AOI22_X1_LVT i_1_0_1099( + .A1(registers_20__ap[20]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[20]), + .ZN(n_1_0_1046) + ); + SDFF_X1_LVT \registers_reg[15][20] ( + .CK(n_0_45), .D(registers[20]), .Q(registers_15__ap[20]), .QN(), .SE(dftIn), + .SI(registers_12__ap[20]) + ); + SDFF_X1_LVT \registers_reg[8][20] ( + .CK(n_0_38), .D(registers[20]), .Q(registers_8__ap[20]), .QN(), .SE(dftIn), + .SI(registers_31__ap[21]) + ); + AOI22_X1_LVT i_1_0_1102( + .A1(registers_15__ap[20]), .A2(n_1_0_1286), .B1(n_1_0_1282), .B2(registers_8__ap[20]), + .ZN(n_1_0_1049) + ); + INV_X1_LVT i_1_0_1101( + .A(n_1_0_1049), .ZN(n_1_0_1048) + ); + SDFF_X1_LVT \registers_reg[11][20] ( + .CK(n_0_41), .D(registers[20]), .Q(registers_11__ap[20]), .QN(), .SE(dftIn), + .SI(registers_15__ap[20]) + ); + SDFF_X1_LVT \registers_reg[5][20] ( + .CK(n_0_35), .D(registers[20]), .Q(registers_5__ap[20]), .QN(), .SE(dftIn), + .SI(registers_8__ap[20]) + ); + AOI221_X1_LVT i_1_0_1098( + .A(n_1_0_1048), .B1(n_1_0_1270), .B2(registers_11__ap[20]), .C1(registers_5__ap[20]), + .C2(n_1_0_1273), .ZN(n_1_0_1045) + ); + SDFF_X1_LVT \registers_reg[13][20] ( + .CK(n_0_43), .D(registers[20]), .Q(registers_13__ap[20]), .QN(), .SE(dftIn), + .SI(registers_11__ap[20]) + ); + SDFF_X1_LVT \registers_reg[30][20] ( + .CK(n_0_60), .D(registers[20]), .Q(registers_30__ap[20]), .QN(), .SE(dftIn), + .SI(registers_2__ap[20]) + ); + SDFF_X1_LVT \registers_reg[22][20] ( + .CK(n_0_52), .D(registers[20]), .Q(registers_22__ap[20]), .QN(), .SE(dftIn), + .SI(registers_20__ap[20]) + ); + AOI222_X1_LVT i_1_0_1097( + .A1(registers_13__ap[20]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[20]), + .C1(registers_22__ap[20]), .C2(n_1_0_1294), .ZN(n_1_0_1044) + ); + NAND4_X1_LVT i_1_0_1096( + .A1(n_1_0_1050), .A2(n_1_0_1046), .A3(n_1_0_1045), .A4(n_1_0_1044), .ZN(n_1_0_1043) + ); + SDFF_X1_LVT \registers_reg[1][20] ( + .CK(n_0_0), .D(registers[20]), .Q(registers_1__ap[20]), .QN(), .SE(dftIn), + .SI(registers_22__ap[20]) + ); + SDFF_X1_LVT \registers_reg[28][20] ( + .CK(n_0_58), .D(registers[20]), .Q(registers_28__ap[20]), .QN(), .SE(dftIn), + .SI(registers_30__ap[20]) + ); + AOI221_X1_LVT i_1_0_1095( + .A(n_1_0_1043), .B1(n_1_0_1274), .B2(registers_1__ap[20]), .C1(registers_28__ap[20]), + .C2(n_1_0_1283), .ZN(n_1_0_1042) + ); + SDFF_X1_LVT \registers_reg[18][20] ( + .CK(n_0_48), .D(registers[20]), .Q(registers_18__ap[20]), .QN(), .SE(dftIn), + .SI(registers_1__ap[20]) + ); + SDFF_X1_LVT \registers_reg[26][20] ( + .CK(n_0_56), .D(registers[20]), .Q(registers_26__ap[20]), .QN(), .SE(dftIn), + .SI(registers_28__ap[20]) + ); + AOI22_X1_LVT i_1_0_1094( + .A1(registers_18__ap[20]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[20]), + .ZN(n_1_0_1041) + ); + SDFF_X1_LVT \registers_reg[24][20] ( + .CK(n_0_54), .D(registers[20]), .Q(registers_24__ap[20]), .QN(), .SE(dftIn), + .SI(registers_26__ap[20]) + ); + SDFF_X1_LVT \registers_reg[4][20] ( + .CK(n_0_34), .D(registers[20]), .Q(registers_4__ap[20]), .QN(), .SE(dftIn), + .SI(registers_5__ap[20]) + ); + AOI22_X1_LVT i_1_0_1093( + .A1(registers_24__ap[20]), .A2(n_1_0_1289), .B1(n_1_0_1278), .B2(registers_4__ap[20]), + .ZN(n_1_0_1040) + ); + SDFF_X1_LVT \registers_reg[6][20] ( + .CK(n_0_36), .D(registers[20]), .Q(registers_6__ap[20]), .QN(), .SE(dftIn), + .SI(registers_4__ap[20]) + ); + SDFF_X1_LVT \registers_reg[25][20] ( + .CK(n_0_55), .D(registers[20]), .Q(registers_25__ap[20]), .QN(), .SE(dftIn), + .SI(registers_24__ap[20]) + ); + AOI22_X1_LVT i_1_0_1092( + .A1(registers_6__ap[20]), .A2(n_1_0_1300), .B1(n_1_0_1269), .B2(registers_25__ap[20]), + .ZN(n_1_0_1039) + ); + NAND3_X1_LVT i_1_0_1091( + .A1(n_1_0_1041), .A2(n_1_0_1040), .A3(n_1_0_1039), .ZN(n_1_0_1038) + ); + SDFF_X1_LVT \registers_reg[19][20] ( + .CK(n_0_49), .D(registers[20]), .Q(registers_19__ap[20]), .QN(), .SE(dftIn), + .SI(registers_18__ap[20]) + ); + SDFF_X1_LVT \registers_reg[16][20] ( + .CK(n_0_46), .D(registers[20]), .Q(registers_16__ap[20]), .QN(), .SE(dftIn), + .SI(registers_13__ap[20]) + ); + AOI221_X1_LVT i_1_0_1090( + .A(n_1_0_1038), .B1(n_1_0_1295), .B2(registers_19__ap[20]), .C1(registers_16__ap[20]), + .C2(n_1_0_1267), .ZN(n_1_0_1037) + ); + SDFF_X1_LVT \registers_reg[7][20] ( + .CK(n_0_37), .D(registers[20]), .Q(registers_7__ap[20]), .QN(), .SE(dftIn), + .SI(registers_6__ap[20]) + ); + SDFF_X1_LVT \registers_reg[14][20] ( + .CK(n_0_44), .D(registers[20]), .Q(registers_14__ap[20]), .QN(), .SE(dftIn), + .SI(registers_16__ap[20]) + ); + AOI22_X1_LVT i_1_0_1089( + .A1(registers_7__ap[20]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[20]), + .ZN(n_1_0_1036) + ); + SDFF_X1_LVT \registers_reg[9][20] ( + .CK(n_0_39), .D(registers[20]), .Q(registers_9__ap[20]), .QN(), .SE(dftIn), + .SI(registers_7__ap[20]) + ); + SDFF_X1_LVT \registers_reg[29][20] ( + .CK(n_0_59), .D(registers[20]), .Q(registers_29__ap[20]), .QN(), .SE(dftIn), + .SI(registers_25__ap[20]) + ); + AOI22_X1_LVT i_1_0_1088( + .A1(registers_9__ap[20]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[20]), + .ZN(n_1_0_1035) + ); + SDFF_X1_LVT \registers_reg[23][20] ( + .CK(n_0_53), .D(registers[20]), .Q(registers_23__ap[20]), .QN(), .SE(dftIn), + .SI(registers_19__ap[20]) + ); + SDFF_X1_LVT \registers_reg[3][20] ( + .CK(n_0_33), .D(registers[20]), .Q(registers_3__ap[20]), .QN(), .SE(dftIn), + .SI(registers_9__ap[20]) + ); + AOI22_X1_LVT i_1_0_1087( + .A1(registers_23__ap[20]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[20]), + .ZN(n_1_0_1034) + ); + NAND3_X1_LVT i_1_0_1086( + .A1(n_1_0_1036), .A2(n_1_0_1035), .A3(n_1_0_1034), .ZN(n_1_0_1033) + ); + SDFF_X1_LVT \registers_reg[27][20] ( + .CK(n_0_57), .D(registers[20]), .Q(registers_27__ap[20]), .QN(), .SE(dftIn), + .SI(registers_29__ap[20]) + ); + SDFF_X1_LVT \registers_reg[31][20] ( + .CK(n_0_61), .D(registers[20]), .Q(registers_31__ap[20]), .QN(), .SE(dftIn), + .SI(registers_3__ap[20]) + ); + AOI221_X1_LVT i_1_0_1085( + .A(n_1_0_1033), .B1(n_1_0_1279), .B2(registers_27__ap[20]), .C1(registers_31__ap[20]), + .C2(n_1_0_1266), .ZN(n_1_0_1032) + ); + NAND4_X1_LVT i_1_0_1084( + .A1(n_1_0_1047), .A2(n_1_0_1042), .A3(n_1_0_1037), .A4(n_1_0_1032), .ZN(RRs1[20]) + ); + AND2_X1_LVT i_0_0_19( + .A1(n_0_0_16), .A2(WRd[19]), .ZN(registers[19]) + ); + SDFF_X1_LVT \registers_reg[17][19] ( + .CK(n_0_47), .D(registers[19]), .Q(registers_17__ap[19]), .QN(), .SE(dftIn), + .SI(registers_23__ap[20]) + ); + SDFF_X1_LVT \registers_reg[21][19] ( + .CK(n_0_51), .D(registers[19]), .Q(registers_21__ap[19]), .QN(), .SE(dftIn), + .SI(registers_17__ap[19]) + ); + AOI22_X1_LVT i_1_0_1080( + .A1(registers_17__ap[19]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[19]), + .ZN(n_1_0_1028) + ); + SDFF_X1_LVT \registers_reg[2][19] ( + .CK(n_0_32), .D(registers[19]), .Q(registers_2__ap[19]), .QN(), .SE(dftIn), + .SI(registers_27__ap[20]) + ); + SDFF_X1_LVT \registers_reg[31][19] ( + .CK(n_0_61), .D(registers[19]), .Q(registers_31__ap[19]), .QN(), .SE(dftIn), + .SI(registers_31__ap[20]) + ); + AOI22_X1_LVT i_1_0_1083( + .A1(registers_2__ap[19]), .A2(n_1_0_1268), .B1(n_1_0_1266), .B2(registers_31__ap[19]), + .ZN(n_1_0_1031) + ); + SDFF_X1_LVT \registers_reg[20][19] ( + .CK(n_0_50), .D(registers[19]), .Q(registers_20__ap[19]), .QN(), .SE(dftIn), + .SI(registers_21__ap[19]) + ); + SDFF_X1_LVT \registers_reg[12][19] ( + .CK(n_0_42), .D(registers[19]), .Q(registers_12__ap[19]), .QN(), .SE(dftIn), + .SI(registers_14__ap[20]) + ); + AOI22_X1_LVT i_1_0_1079( + .A1(registers_20__ap[19]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[19]), + .ZN(n_1_0_1027) + ); + SDFF_X1_LVT \registers_reg[15][19] ( + .CK(n_0_45), .D(registers[19]), .Q(registers_15__ap[19]), .QN(), .SE(dftIn), + .SI(registers_12__ap[19]) + ); + SDFF_X1_LVT \registers_reg[11][19] ( + .CK(n_0_41), .D(registers[19]), .Q(registers_11__ap[19]), .QN(), .SE(dftIn), + .SI(registers_15__ap[19]) + ); + AOI22_X1_LVT i_1_0_1082( + .A1(registers_15__ap[19]), .A2(n_1_0_1286), .B1(n_1_0_1270), .B2(registers_11__ap[19]), + .ZN(n_1_0_1030) + ); + INV_X1_LVT i_1_0_1081( + .A(n_1_0_1030), .ZN(n_1_0_1029) + ); + SDFF_X1_LVT \registers_reg[27][19] ( + .CK(n_0_57), .D(registers[19]), .Q(registers_27__ap[19]), .QN(), .SE(dftIn), + .SI(registers_2__ap[19]) + ); + SDFF_X1_LVT \registers_reg[24][19] ( + .CK(n_0_54), .D(registers[19]), .Q(registers_24__ap[19]), .QN(), .SE(dftIn), + .SI(registers_27__ap[19]) + ); + AOI221_X1_LVT i_1_0_1078( + .A(n_1_0_1029), .B1(n_1_0_1279), .B2(registers_27__ap[19]), .C1(registers_24__ap[19]), + .C2(n_1_0_1289), .ZN(n_1_0_1026) + ); + SDFF_X1_LVT \registers_reg[22][19] ( + .CK(n_0_52), .D(registers[19]), .Q(registers_22__ap[19]), .QN(), .SE(dftIn), + .SI(registers_20__ap[19]) + ); + SDFF_X1_LVT \registers_reg[26][19] ( + .CK(n_0_56), .D(registers[19]), .Q(registers_26__ap[19]), .QN(), .SE(dftIn), + .SI(registers_24__ap[19]) + ); + SDFF_X1_LVT \registers_reg[13][19] ( + .CK(n_0_43), .D(registers[19]), .Q(registers_13__ap[19]), .QN(), .SE(dftIn), + .SI(registers_11__ap[19]) + ); + AOI222_X1_LVT i_1_0_1077( + .A1(registers_22__ap[19]), .A2(n_1_0_1294), .B1(n_1_0_1285), .B2(registers_26__ap[19]), + .C1(n_1_0_1277), .C2(registers_13__ap[19]), .ZN(n_1_0_1025) + ); + NAND4_X1_LVT i_1_0_1076( + .A1(n_1_0_1031), .A2(n_1_0_1027), .A3(n_1_0_1026), .A4(n_1_0_1025), .ZN(n_1_0_1024) + ); + SDFF_X1_LVT \registers_reg[1][19] ( + .CK(n_0_0), .D(registers[19]), .Q(registers_1__ap[19]), .QN(), .SE(dftIn), + .SI(registers_22__ap[19]) + ); + SDFF_X1_LVT \registers_reg[28][19] ( + .CK(n_0_58), .D(registers[19]), .Q(registers_28__ap[19]), .QN(), .SE(dftIn), + .SI(registers_26__ap[19]) + ); + AOI221_X1_LVT i_1_0_1075( + .A(n_1_0_1024), .B1(n_1_0_1274), .B2(registers_1__ap[19]), .C1(registers_28__ap[19]), + .C2(n_1_0_1283), .ZN(n_1_0_1023) + ); + SDFF_X1_LVT \registers_reg[18][19] ( + .CK(n_0_48), .D(registers[19]), .Q(registers_18__ap[19]), .QN(), .SE(dftIn), + .SI(registers_1__ap[19]) + ); + SDFF_X1_LVT \registers_reg[30][19] ( + .CK(n_0_60), .D(registers[19]), .Q(registers_30__ap[19]), .QN(), .SE(dftIn), + .SI(registers_28__ap[19]) + ); + AOI22_X1_LVT i_1_0_1074( + .A1(registers_18__ap[19]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[19]), + .ZN(n_1_0_1022) + ); + SDFF_X1_LVT \registers_reg[4][19] ( + .CK(n_0_34), .D(registers[19]), .Q(registers_4__ap[19]), .QN(), .SE(dftIn), + .SI(registers_31__ap[19]) + ); + SDFF_X1_LVT \registers_reg[5][19] ( + .CK(n_0_35), .D(registers[19]), .Q(registers_5__ap[19]), .QN(), .SE(dftIn), + .SI(registers_4__ap[19]) + ); + AOI22_X1_LVT i_1_0_1073( + .A1(registers_4__ap[19]), .A2(n_1_0_1278), .B1(n_1_0_1273), .B2(registers_5__ap[19]), + .ZN(n_1_0_1021) + ); + SDFF_X1_LVT \registers_reg[6][19] ( + .CK(n_0_36), .D(registers[19]), .Q(registers_6__ap[19]), .QN(), .SE(dftIn), + .SI(registers_5__ap[19]) + ); + SDFF_X1_LVT \registers_reg[25][19] ( + .CK(n_0_55), .D(registers[19]), .Q(registers_25__ap[19]), .QN(), .SE(dftIn), + .SI(registers_30__ap[19]) + ); + AOI22_X1_LVT i_1_0_1072( + .A1(registers_6__ap[19]), .A2(n_1_0_1300), .B1(n_1_0_1269), .B2(registers_25__ap[19]), + .ZN(n_1_0_1020) + ); + NAND3_X1_LVT i_1_0_1071( + .A1(n_1_0_1022), .A2(n_1_0_1021), .A3(n_1_0_1020), .ZN(n_1_0_1019) + ); + SDFF_X1_LVT \registers_reg[19][19] ( + .CK(n_0_49), .D(registers[19]), .Q(registers_19__ap[19]), .QN(), .SE(dftIn), + .SI(registers_18__ap[19]) + ); + SDFF_X1_LVT \registers_reg[16][19] ( + .CK(n_0_46), .D(registers[19]), .Q(registers_16__ap[19]), .QN(), .SE(dftIn), + .SI(registers_13__ap[19]) + ); + AOI221_X1_LVT i_1_0_1070( + .A(n_1_0_1019), .B1(n_1_0_1295), .B2(registers_19__ap[19]), .C1(registers_16__ap[19]), + .C2(n_1_0_1267), .ZN(n_1_0_1018) + ); + SDFF_X1_LVT \registers_reg[9][19] ( + .CK(n_0_39), .D(registers[19]), .Q(registers_9__ap[19]), .QN(), .SE(dftIn), + .SI(registers_6__ap[19]) + ); + SDFF_X1_LVT \registers_reg[29][19] ( + .CK(n_0_59), .D(registers[19]), .Q(registers_29__ap[19]), .QN(), .SE(dftIn), + .SI(registers_25__ap[19]) + ); + AOI22_X1_LVT i_1_0_1069( + .A1(registers_9__ap[19]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[19]), + .ZN(n_1_0_1017) + ); + SDFF_X1_LVT \registers_reg[8][19] ( + .CK(n_0_38), .D(registers[19]), .Q(registers_8__ap[19]), .QN(), .SE(dftIn), + .SI(registers_9__ap[19]) + ); + SDFF_X1_LVT \registers_reg[23][19] ( + .CK(n_0_53), .D(registers[19]), .Q(registers_23__ap[19]), .QN(), .SE(dftIn), + .SI(registers_19__ap[19]) + ); + AOI22_X1_LVT i_1_0_1068( + .A1(registers_8__ap[19]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[19]), + .ZN(n_1_0_1016) + ); + SDFF_X1_LVT \registers_reg[7][19] ( + .CK(n_0_37), .D(registers[19]), .Q(registers_7__ap[19]), .QN(), .SE(dftIn), + .SI(registers_8__ap[19]) + ); + SDFF_X1_LVT \registers_reg[14][19] ( + .CK(n_0_44), .D(registers[19]), .Q(registers_14__ap[19]), .QN(), .SE(dftIn), + .SI(registers_16__ap[19]) + ); + AOI22_X1_LVT i_1_0_1067( + .A1(registers_7__ap[19]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[19]), + .ZN(n_1_0_1015) + ); + NAND3_X1_LVT i_1_0_1066( + .A1(n_1_0_1017), .A2(n_1_0_1016), .A3(n_1_0_1015), .ZN(n_1_0_1014) + ); + SDFF_X1_LVT \registers_reg[10][19] ( + .CK(n_0_40), .D(registers[19]), .Q(registers_10__ap[19]), .QN(), .SE(dftIn), + .SI(registers_14__ap[19]) + ); + SDFF_X1_LVT \registers_reg[3][19] ( + .CK(n_0_33), .D(registers[19]), .Q(registers_3__ap[19]), .QN(), .SE(dftIn), + .SI(registers_7__ap[19]) + ); + AOI221_X1_LVT i_1_0_1065( + .A(n_1_0_1014), .B1(n_1_0_1287), .B2(registers_10__ap[19]), .C1(registers_3__ap[19]), + .C2(n_1_0_1257), .ZN(n_1_0_1013) + ); + NAND4_X1_LVT i_1_0_1064( + .A1(n_1_0_1028), .A2(n_1_0_1023), .A3(n_1_0_1018), .A4(n_1_0_1013), .ZN(RRs1[19]) + ); + AND2_X1_LVT i_0_0_18( + .A1(n_0_0_16), .A2(WRd[18]), .ZN(registers[18]) + ); + SDFF_X1_LVT \registers_reg[24][18] ( + .CK(n_0_54), .D(registers[18]), .Q(registers_24__ap[18]), .QN(), .SE(dftIn), + .SI(registers_29__ap[19]) + ); + SDFF_X1_LVT \registers_reg[28][18] ( + .CK(n_0_58), .D(registers[18]), .Q(registers_28__ap[18]), .QN(), .SE(dftIn), + .SI(registers_24__ap[18]) + ); + AOI22_X1_LVT i_1_0_1062( + .A1(registers_24__ap[18]), .A2(n_1_0_1289), .B1(n_1_0_1283), .B2(registers_28__ap[18]), + .ZN(n_1_0_1011) + ); + SDFF_X1_LVT \registers_reg[11][18] ( + .CK(n_0_41), .D(registers[18]), .Q(registers_11__ap[18]), .QN(), .SE(dftIn), + .SI(registers_10__ap[19]) + ); + SDFF_X1_LVT \registers_reg[16][18] ( + .CK(n_0_46), .D(registers[18]), .Q(registers_16__ap[18]), .QN(), .SE(dftIn), + .SI(registers_11__ap[18]) + ); + AOI22_X1_LVT i_1_0_1063( + .A1(registers_11__ap[18]), .A2(n_1_0_1270), .B1(n_1_0_1267), .B2(registers_16__ap[18]), + .ZN(n_1_0_1012) + ); + SDFF_X1_LVT \registers_reg[9][18] ( + .CK(n_0_39), .D(registers[18]), .Q(registers_9__ap[18]), .QN(), .SE(dftIn), + .SI(registers_3__ap[19]) + ); + SDFF_X1_LVT \registers_reg[7][18] ( + .CK(n_0_37), .D(registers[18]), .Q(registers_7__ap[18]), .QN(), .SE(dftIn), + .SI(registers_9__ap[18]) + ); + AOI22_X1_LVT i_1_0_1061( + .A1(registers_9__ap[18]), .A2(n_1_0_1291), .B1(n_1_0_1263), .B2(registers_7__ap[18]), + .ZN(n_1_0_1010) + ); + SDFF_X1_LVT \registers_reg[27][18] ( + .CK(n_0_57), .D(registers[18]), .Q(registers_27__ap[18]), .QN(), .SE(dftIn), + .SI(registers_28__ap[18]) + ); + SDFF_X1_LVT \registers_reg[25][18] ( + .CK(n_0_55), .D(registers[18]), .Q(registers_25__ap[18]), .QN(), .SE(dftIn), + .SI(registers_27__ap[18]) + ); + AOI22_X1_LVT i_1_0_1060( + .A1(registers_27__ap[18]), .A2(n_1_0_1279), .B1(n_1_0_1269), .B2(registers_25__ap[18]), + .ZN(n_1_0_1009) + ); + NAND3_X1_LVT i_1_0_1059( + .A1(n_1_0_1012), .A2(n_1_0_1010), .A3(n_1_0_1009), .ZN(n_1_0_1008) + ); + SDFF_X1_LVT \registers_reg[31][18] ( + .CK(n_0_61), .D(registers[18]), .Q(registers_31__ap[18]), .QN(), .SE(dftIn), + .SI(registers_7__ap[18]) + ); + SDFF_X1_LVT \registers_reg[6][18] ( + .CK(n_0_36), .D(registers[18]), .Q(registers_6__ap[18]), .QN(), .SE(dftIn), + .SI(registers_31__ap[18]) + ); + AOI221_X1_LVT i_1_0_1058( + .A(n_1_0_1008), .B1(n_1_0_1266), .B2(registers_31__ap[18]), .C1(registers_6__ap[18]), + .C2(n_1_0_1300), .ZN(n_1_0_1007) + ); + SDFF_X1_LVT \registers_reg[22][18] ( + .CK(n_0_52), .D(registers[18]), .Q(registers_22__ap[18]), .QN(), .SE(dftIn), + .SI(registers_23__ap[19]) + ); + SDFF_X1_LVT \registers_reg[26][18] ( + .CK(n_0_56), .D(registers[18]), .Q(registers_26__ap[18]), .QN(), .SE(dftIn), + .SI(registers_25__ap[18]) + ); + SDFF_X1_LVT \registers_reg[1][18] ( + .CK(n_0_0), .D(registers[18]), .Q(registers_1__ap[18]), .QN(), .SE(dftIn), + .SI(registers_22__ap[18]) + ); + AOI222_X1_LVT i_1_0_1057( + .A1(registers_22__ap[18]), .A2(n_1_0_1294), .B1(n_1_0_1285), .B2(registers_26__ap[18]), + .C1(n_1_0_1274), .C2(registers_1__ap[18]), .ZN(n_1_0_1006) + ); + NAND2_X1_LVT i_1_0_1056( + .A1(n_1_0_1007), .A2(n_1_0_1006), .ZN(n_1_0_1005) + ); + SDFF_X1_LVT \registers_reg[29][18] ( + .CK(n_0_59), .D(registers[18]), .Q(registers_29__ap[18]), .QN(), .SE(dftIn), + .SI(registers_26__ap[18]) + ); + SDFF_X1_LVT \registers_reg[2][18] ( + .CK(n_0_32), .D(registers[18]), .Q(registers_2__ap[18]), .QN(), .SE(dftIn), + .SI(registers_29__ap[18]) + ); + AOI221_X1_LVT i_1_0_1055( + .A(n_1_0_1005), .B1(n_1_0_1276), .B2(registers_29__ap[18]), .C1(registers_2__ap[18]), + .C2(n_1_0_1268), .ZN(n_1_0_1004) + ); + SDFF_X1_LVT \registers_reg[18][18] ( + .CK(n_0_48), .D(registers[18]), .Q(registers_18__ap[18]), .QN(), .SE(dftIn), + .SI(registers_1__ap[18]) + ); + SDFF_X1_LVT \registers_reg[30][18] ( + .CK(n_0_60), .D(registers[18]), .Q(registers_30__ap[18]), .QN(), .SE(dftIn), + .SI(registers_2__ap[18]) + ); + AOI22_X1_LVT i_1_0_1054( + .A1(registers_18__ap[18]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[18]), + .ZN(n_1_0_1003) + ); + SDFF_X1_LVT \registers_reg[4][18] ( + .CK(n_0_34), .D(registers[18]), .Q(registers_4__ap[18]), .QN(), .SE(dftIn), + .SI(registers_6__ap[18]) + ); + SDFF_X1_LVT \registers_reg[12][18] ( + .CK(n_0_42), .D(registers[18]), .Q(registers_12__ap[18]), .QN(), .SE(dftIn), + .SI(registers_16__ap[18]) + ); + AOI22_X1_LVT i_1_0_1053( + .A1(registers_4__ap[18]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[18]), + .ZN(n_1_0_1002) + ); + SDFF_X1_LVT \registers_reg[19][18] ( + .CK(n_0_49), .D(registers[18]), .Q(registers_19__ap[18]), .QN(), .SE(dftIn), + .SI(registers_18__ap[18]) + ); + SDFF_X1_LVT \registers_reg[21][18] ( + .CK(n_0_51), .D(registers[18]), .Q(registers_21__ap[18]), .QN(), .SE(dftIn), + .SI(registers_19__ap[18]) + ); + AOI22_X1_LVT i_1_0_1052( + .A1(registers_19__ap[18]), .A2(n_1_0_1295), .B1(n_1_0_1259), .B2(registers_21__ap[18]), + .ZN(n_1_0_1001) + ); + NAND3_X1_LVT i_1_0_1051( + .A1(n_1_0_1003), .A2(n_1_0_1002), .A3(n_1_0_1001), .ZN(n_1_0_1000) + ); + SDFF_X1_LVT \registers_reg[5][18] ( + .CK(n_0_35), .D(registers[18]), .Q(registers_5__ap[18]), .QN(), .SE(dftIn), + .SI(registers_4__ap[18]) + ); + SDFF_X1_LVT \registers_reg[20][18] ( + .CK(n_0_50), .D(registers[18]), .Q(registers_20__ap[18]), .QN(), .SE(dftIn), + .SI(registers_21__ap[18]) + ); + AOI221_X1_LVT i_1_0_1050( + .A(n_1_0_1000), .B1(n_1_0_1273), .B2(registers_5__ap[18]), .C1(registers_20__ap[18]), + .C2(n_1_0_1281), .ZN(n_1_0_999) + ); + SDFF_X1_LVT \registers_reg[8][18] ( + .CK(n_0_38), .D(registers[18]), .Q(registers_8__ap[18]), .QN(), .SE(dftIn), + .SI(registers_5__ap[18]) + ); + SDFF_X1_LVT \registers_reg[23][18] ( + .CK(n_0_53), .D(registers[18]), .Q(registers_23__ap[18]), .QN(), .SE(dftIn), + .SI(registers_20__ap[18]) + ); + AOI22_X1_LVT i_1_0_1049( + .A1(registers_8__ap[18]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[18]), + .ZN(n_1_0_998) + ); + SDFF_X1_LVT \registers_reg[13][18] ( + .CK(n_0_43), .D(registers[18]), .Q(registers_13__ap[18]), .QN(), .SE(dftIn), + .SI(registers_12__ap[18]) + ); + SDFF_X1_LVT \registers_reg[17][18] ( + .CK(n_0_47), .D(registers[18]), .Q(registers_17__ap[18]), .QN(), .SE(dftIn), + .SI(registers_23__ap[18]) + ); + AOI22_X1_LVT i_1_0_1048( + .A1(registers_13__ap[18]), .A2(n_1_0_1277), .B1(n_1_0_1271), .B2(registers_17__ap[18]), + .ZN(n_1_0_997) + ); + SDFF_X1_LVT \registers_reg[15][18] ( + .CK(n_0_45), .D(registers[18]), .Q(registers_15__ap[18]), .QN(), .SE(dftIn), + .SI(registers_13__ap[18]) + ); + SDFF_X1_LVT \registers_reg[14][18] ( + .CK(n_0_44), .D(registers[18]), .Q(registers_14__ap[18]), .QN(), .SE(dftIn), + .SI(registers_15__ap[18]) + ); + AOI22_X1_LVT i_1_0_1047( + .A1(registers_15__ap[18]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[18]), + .ZN(n_1_0_996) + ); + NAND3_X1_LVT i_1_0_1046( + .A1(n_1_0_998), .A2(n_1_0_997), .A3(n_1_0_996), .ZN(n_1_0_995) + ); + SDFF_X1_LVT \registers_reg[10][18] ( + .CK(n_0_40), .D(registers[18]), .Q(registers_10__ap[18]), .QN(), .SE(dftIn), + .SI(registers_14__ap[18]) + ); + SDFF_X1_LVT \registers_reg[3][18] ( + .CK(n_0_33), .D(registers[18]), .Q(registers_3__ap[18]), .QN(), .SE(dftIn), + .SI(registers_8__ap[18]) + ); + AOI221_X1_LVT i_1_0_1045( + .A(n_1_0_995), .B1(n_1_0_1287), .B2(registers_10__ap[18]), .C1(registers_3__ap[18]), + .C2(n_1_0_1257), .ZN(n_1_0_994) + ); + NAND4_X1_LVT i_1_0_1044( + .A1(n_1_0_1011), .A2(n_1_0_1004), .A3(n_1_0_999), .A4(n_1_0_994), .ZN(RRs1[18]) + ); + AND2_X1_LVT i_0_0_17( + .A1(n_0_0_16), .A2(WRd[17]), .ZN(registers[17]) + ); + SDFF_X1_LVT \registers_reg[17][17] ( + .CK(n_0_47), .D(registers[17]), .Q(registers_17__ap[17]), .QN(), .SE(dftIn), + .SI(registers_17__ap[18]) + ); + SDFF_X1_LVT \registers_reg[21][17] ( + .CK(n_0_51), .D(registers[17]), .Q(registers_21__ap[17]), .QN(), .SE(dftIn), + .SI(registers_17__ap[17]) + ); + AOI22_X1_LVT i_1_0_1040( + .A1(registers_17__ap[17]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[17]), + .ZN(n_1_0_990) + ); + SDFF_X1_LVT \registers_reg[2][17] ( + .CK(n_0_32), .D(registers[17]), .Q(registers_2__ap[17]), .QN(), .SE(dftIn), + .SI(registers_30__ap[18]) + ); + SDFF_X1_LVT \registers_reg[31][17] ( + .CK(n_0_61), .D(registers[17]), .Q(registers_31__ap[17]), .QN(), .SE(dftIn), + .SI(registers_3__ap[18]) + ); + AOI22_X1_LVT i_1_0_1043( + .A1(registers_2__ap[17]), .A2(n_1_0_1268), .B1(n_1_0_1266), .B2(registers_31__ap[17]), + .ZN(n_1_0_993) + ); + SDFF_X1_LVT \registers_reg[20][17] ( + .CK(n_0_50), .D(registers[17]), .Q(registers_20__ap[17]), .QN(), .SE(dftIn), + .SI(registers_21__ap[17]) + ); + SDFF_X1_LVT \registers_reg[12][17] ( + .CK(n_0_42), .D(registers[17]), .Q(registers_12__ap[17]), .QN(), .SE(dftIn), + .SI(registers_10__ap[18]) + ); + AOI22_X1_LVT i_1_0_1039( + .A1(registers_20__ap[17]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[17]), + .ZN(n_1_0_989) + ); + SDFF_X1_LVT \registers_reg[15][17] ( + .CK(n_0_45), .D(registers[17]), .Q(registers_15__ap[17]), .QN(), .SE(dftIn), + .SI(registers_12__ap[17]) + ); + SDFF_X1_LVT \registers_reg[11][17] ( + .CK(n_0_41), .D(registers[17]), .Q(registers_11__ap[17]), .QN(), .SE(dftIn), + .SI(registers_15__ap[17]) + ); + AOI22_X1_LVT i_1_0_1042( + .A1(registers_15__ap[17]), .A2(n_1_0_1286), .B1(n_1_0_1270), .B2(registers_11__ap[17]), + .ZN(n_1_0_992) + ); + INV_X1_LVT i_1_0_1041( + .A(n_1_0_992), .ZN(n_1_0_991) + ); + SDFF_X1_LVT \registers_reg[10][17] ( + .CK(n_0_40), .D(registers[17]), .Q(registers_10__ap[17]), .QN(), .SE(dftIn), + .SI(registers_11__ap[17]) + ); + SDFF_X1_LVT \registers_reg[24][17] ( + .CK(n_0_54), .D(registers[17]), .Q(registers_24__ap[17]), .QN(), .SE(dftIn), + .SI(registers_2__ap[17]) + ); + AOI221_X1_LVT i_1_0_1038( + .A(n_1_0_991), .B1(n_1_0_1287), .B2(registers_10__ap[17]), .C1(registers_24__ap[17]), + .C2(n_1_0_1289), .ZN(n_1_0_988) + ); + SDFF_X1_LVT \registers_reg[22][17] ( + .CK(n_0_52), .D(registers[17]), .Q(registers_22__ap[17]), .QN(), .SE(dftIn), + .SI(registers_20__ap[17]) + ); + SDFF_X1_LVT \registers_reg[26][17] ( + .CK(n_0_56), .D(registers[17]), .Q(registers_26__ap[17]), .QN(), .SE(dftIn), + .SI(registers_24__ap[17]) + ); + SDFF_X1_LVT \registers_reg[13][17] ( + .CK(n_0_43), .D(registers[17]), .Q(registers_13__ap[17]), .QN(), .SE(dftIn), + .SI(registers_10__ap[17]) + ); + AOI222_X1_LVT i_1_0_1037( + .A1(registers_22__ap[17]), .A2(n_1_0_1294), .B1(n_1_0_1285), .B2(registers_26__ap[17]), + .C1(n_1_0_1277), .C2(registers_13__ap[17]), .ZN(n_1_0_987) + ); + NAND4_X1_LVT i_1_0_1036( + .A1(n_1_0_993), .A2(n_1_0_989), .A3(n_1_0_988), .A4(n_1_0_987), .ZN(n_1_0_986) + ); + SDFF_X1_LVT \registers_reg[1][17] ( + .CK(n_0_0), .D(registers[17]), .Q(registers_1__ap[17]), .QN(), .SE(dftIn), + .SI(registers_22__ap[17]) + ); + SDFF_X1_LVT \registers_reg[28][17] ( + .CK(n_0_58), .D(registers[17]), .Q(registers_28__ap[17]), .QN(), .SE(dftIn), + .SI(registers_26__ap[17]) + ); + AOI221_X1_LVT i_1_0_1035( + .A(n_1_0_986), .B1(n_1_0_1274), .B2(registers_1__ap[17]), .C1(registers_28__ap[17]), + .C2(n_1_0_1283), .ZN(n_1_0_985) + ); + SDFF_X1_LVT \registers_reg[18][17] ( + .CK(n_0_48), .D(registers[17]), .Q(registers_18__ap[17]), .QN(), .SE(dftIn), + .SI(registers_1__ap[17]) + ); + SDFF_X1_LVT \registers_reg[30][17] ( + .CK(n_0_60), .D(registers[17]), .Q(registers_30__ap[17]), .QN(), .SE(dftIn), + .SI(registers_28__ap[17]) + ); + AOI22_X1_LVT i_1_0_1034( + .A1(registers_18__ap[17]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[17]), + .ZN(n_1_0_984) + ); + SDFF_X1_LVT \registers_reg[4][17] ( + .CK(n_0_34), .D(registers[17]), .Q(registers_4__ap[17]), .QN(), .SE(dftIn), + .SI(registers_31__ap[17]) + ); + SDFF_X1_LVT \registers_reg[5][17] ( + .CK(n_0_35), .D(registers[17]), .Q(registers_5__ap[17]), .QN(), .SE(dftIn), + .SI(registers_4__ap[17]) + ); + AOI22_X1_LVT i_1_0_1033( + .A1(registers_4__ap[17]), .A2(n_1_0_1278), .B1(n_1_0_1273), .B2(registers_5__ap[17]), + .ZN(n_1_0_983) + ); + SDFF_X1_LVT \registers_reg[6][17] ( + .CK(n_0_36), .D(registers[17]), .Q(registers_6__ap[17]), .QN(), .SE(dftIn), + .SI(registers_5__ap[17]) + ); + SDFF_X1_LVT \registers_reg[25][17] ( + .CK(n_0_55), .D(registers[17]), .Q(registers_25__ap[17]), .QN(), .SE(dftIn), + .SI(registers_30__ap[17]) + ); + AOI22_X1_LVT i_1_0_1032( + .A1(registers_6__ap[17]), .A2(n_1_0_1300), .B1(n_1_0_1269), .B2(registers_25__ap[17]), + .ZN(n_1_0_982) + ); + NAND3_X1_LVT i_1_0_1031( + .A1(n_1_0_984), .A2(n_1_0_983), .A3(n_1_0_982), .ZN(n_1_0_981) + ); + SDFF_X1_LVT \registers_reg[19][17] ( + .CK(n_0_49), .D(registers[17]), .Q(registers_19__ap[17]), .QN(), .SE(dftIn), + .SI(registers_18__ap[17]) + ); + SDFF_X1_LVT \registers_reg[16][17] ( + .CK(n_0_46), .D(registers[17]), .Q(registers_16__ap[17]), .QN(), .SE(dftIn), + .SI(registers_13__ap[17]) + ); + AOI221_X1_LVT i_1_0_1030( + .A(n_1_0_981), .B1(n_1_0_1295), .B2(registers_19__ap[17]), .C1(registers_16__ap[17]), + .C2(n_1_0_1267), .ZN(n_1_0_980) + ); + SDFF_X1_LVT \registers_reg[7][17] ( + .CK(n_0_37), .D(registers[17]), .Q(registers_7__ap[17]), .QN(), .SE(dftIn), + .SI(registers_6__ap[17]) + ); + SDFF_X1_LVT \registers_reg[14][17] ( + .CK(n_0_44), .D(registers[17]), .Q(registers_14__ap[17]), .QN(), .SE(dftIn), + .SI(registers_16__ap[17]) + ); + AOI22_X1_LVT i_1_0_1029( + .A1(registers_7__ap[17]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[17]), + .ZN(n_1_0_979) + ); + SDFF_X1_LVT \registers_reg[9][17] ( + .CK(n_0_39), .D(registers[17]), .Q(registers_9__ap[17]), .QN(), .SE(dftIn), + .SI(registers_7__ap[17]) + ); + SDFF_X1_LVT \registers_reg[29][17] ( + .CK(n_0_59), .D(registers[17]), .Q(registers_29__ap[17]), .QN(), .SE(dftIn), + .SI(registers_25__ap[17]) + ); + AOI22_X1_LVT i_1_0_1028( + .A1(registers_9__ap[17]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[17]), + .ZN(n_1_0_978) + ); + SDFF_X1_LVT \registers_reg[8][17] ( + .CK(n_0_38), .D(registers[17]), .Q(registers_8__ap[17]), .QN(), .SE(dftIn), + .SI(registers_9__ap[17]) + ); + SDFF_X1_LVT \registers_reg[23][17] ( + .CK(n_0_53), .D(registers[17]), .Q(registers_23__ap[17]), .QN(), .SE(dftIn), + .SI(registers_19__ap[17]) + ); + AOI22_X1_LVT i_1_0_1027( + .A1(registers_8__ap[17]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[17]), + .ZN(n_1_0_977) + ); + NAND3_X1_LVT i_1_0_1026( + .A1(n_1_0_979), .A2(n_1_0_978), .A3(n_1_0_977), .ZN(n_1_0_976) + ); + SDFF_X1_LVT \registers_reg[27][17] ( + .CK(n_0_57), .D(registers[17]), .Q(registers_27__ap[17]), .QN(), .SE(dftIn), + .SI(registers_29__ap[17]) + ); + SDFF_X1_LVT \registers_reg[3][17] ( + .CK(n_0_33), .D(registers[17]), .Q(registers_3__ap[17]), .QN(), .SE(dftIn), + .SI(registers_8__ap[17]) + ); + AOI221_X1_LVT i_1_0_1025( + .A(n_1_0_976), .B1(n_1_0_1279), .B2(registers_27__ap[17]), .C1(registers_3__ap[17]), + .C2(n_1_0_1257), .ZN(n_1_0_975) + ); + NAND4_X1_LVT i_1_0_1024( + .A1(n_1_0_990), .A2(n_1_0_985), .A3(n_1_0_980), .A4(n_1_0_975), .ZN(RRs1[17]) + ); + AND2_X1_LVT i_0_0_16( + .A1(n_0_0_16), .A2(WRd[16]), .ZN(registers[16]) + ); + SDFF_X1_LVT \registers_reg[29][16] ( + .CK(n_0_59), .D(registers[16]), .Q(registers_29__ap[16]), .QN(), .SE(dftIn), + .SI(registers_27__ap[17]) + ); + SDFF_X1_LVT \registers_reg[2][16] ( + .CK(n_0_32), .D(registers[16]), .Q(registers_2__ap[16]), .QN(), .SE(dftIn), + .SI(registers_29__ap[16]) + ); + AOI22_X1_LVT i_1_0_1022( + .A1(registers_29__ap[16]), .A2(n_1_0_1276), .B1(n_1_0_1268), .B2(registers_2__ap[16]), + .ZN(n_1_0_973) + ); + SDFF_X1_LVT \registers_reg[11][16] ( + .CK(n_0_41), .D(registers[16]), .Q(registers_11__ap[16]), .QN(), .SE(dftIn), + .SI(registers_14__ap[17]) + ); + SDFF_X1_LVT \registers_reg[25][16] ( + .CK(n_0_55), .D(registers[16]), .Q(registers_25__ap[16]), .QN(), .SE(dftIn), + .SI(registers_2__ap[16]) + ); + AOI22_X1_LVT i_1_0_1023( + .A1(registers_11__ap[16]), .A2(n_1_0_1270), .B1(n_1_0_1269), .B2(registers_25__ap[16]), + .ZN(n_1_0_974) + ); + SDFF_X1_LVT \registers_reg[9][16] ( + .CK(n_0_39), .D(registers[16]), .Q(registers_9__ap[16]), .QN(), .SE(dftIn), + .SI(registers_3__ap[17]) + ); + SDFF_X1_LVT \registers_reg[7][16] ( + .CK(n_0_37), .D(registers[16]), .Q(registers_7__ap[16]), .QN(), .SE(dftIn), + .SI(registers_9__ap[16]) + ); + AOI22_X1_LVT i_1_0_1021( + .A1(registers_9__ap[16]), .A2(n_1_0_1291), .B1(n_1_0_1263), .B2(registers_7__ap[16]), + .ZN(n_1_0_972) + ); + SDFF_X1_LVT \registers_reg[10][16] ( + .CK(n_0_40), .D(registers[16]), .Q(registers_10__ap[16]), .QN(), .SE(dftIn), + .SI(registers_11__ap[16]) + ); + SDFF_X1_LVT \registers_reg[16][16] ( + .CK(n_0_46), .D(registers[16]), .Q(registers_16__ap[16]), .QN(), .SE(dftIn), + .SI(registers_10__ap[16]) + ); + AOI22_X1_LVT i_1_0_1020( + .A1(registers_10__ap[16]), .A2(n_1_0_1287), .B1(n_1_0_1267), .B2(registers_16__ap[16]), + .ZN(n_1_0_971) + ); + NAND3_X1_LVT i_1_0_1019( + .A1(n_1_0_974), .A2(n_1_0_972), .A3(n_1_0_971), .ZN(n_1_0_970) + ); + SDFF_X1_LVT \registers_reg[31][16] ( + .CK(n_0_61), .D(registers[16]), .Q(registers_31__ap[16]), .QN(), .SE(dftIn), + .SI(registers_7__ap[16]) + ); + SDFF_X1_LVT \registers_reg[6][16] ( + .CK(n_0_36), .D(registers[16]), .Q(registers_6__ap[16]), .QN(), .SE(dftIn), + .SI(registers_31__ap[16]) + ); + AOI221_X1_LVT i_1_0_1018( + .A(n_1_0_970), .B1(n_1_0_1266), .B2(registers_31__ap[16]), .C1(registers_6__ap[16]), + .C2(n_1_0_1300), .ZN(n_1_0_969) + ); + SDFF_X1_LVT \registers_reg[18][16] ( + .CK(n_0_48), .D(registers[16]), .Q(registers_18__ap[16]), .QN(), .SE(dftIn), + .SI(registers_23__ap[17]) + ); + SDFF_X1_LVT \registers_reg[22][16] ( + .CK(n_0_52), .D(registers[16]), .Q(registers_22__ap[16]), .QN(), .SE(dftIn), + .SI(registers_18__ap[16]) + ); + SDFF_X1_LVT \registers_reg[1][16] ( + .CK(n_0_0), .D(registers[16]), .Q(registers_1__ap[16]), .QN(), .SE(dftIn), + .SI(registers_22__ap[16]) + ); + AOI222_X1_LVT i_1_0_1017( + .A1(registers_18__ap[16]), .A2(n_1_0_1297), .B1(n_1_0_1294), .B2(registers_22__ap[16]), + .C1(registers_1__ap[16]), .C2(n_1_0_1274), .ZN(n_1_0_968) + ); + NAND3_X1_LVT i_1_0_1016( + .A1(n_1_0_973), .A2(n_1_0_969), .A3(n_1_0_968), .ZN(n_1_0_967) + ); + SDFF_X1_LVT \registers_reg[5][16] ( + .CK(n_0_35), .D(registers[16]), .Q(registers_5__ap[16]), .QN(), .SE(dftIn), + .SI(registers_6__ap[16]) + ); + SDFF_X1_LVT \registers_reg[28][16] ( + .CK(n_0_58), .D(registers[16]), .Q(registers_28__ap[16]), .QN(), .SE(dftIn), + .SI(registers_25__ap[16]) + ); + AOI221_X1_LVT i_1_0_1015( + .A(n_1_0_967), .B1(n_1_0_1273), .B2(registers_5__ap[16]), .C1(registers_28__ap[16]), + .C2(n_1_0_1283), .ZN(n_1_0_966) + ); + SDFF_X1_LVT \registers_reg[4][16] ( + .CK(n_0_34), .D(registers[16]), .Q(registers_4__ap[16]), .QN(), .SE(dftIn), + .SI(registers_5__ap[16]) + ); + SDFF_X1_LVT \registers_reg[12][16] ( + .CK(n_0_42), .D(registers[16]), .Q(registers_12__ap[16]), .QN(), .SE(dftIn), + .SI(registers_16__ap[16]) + ); + AOI22_X1_LVT i_1_0_1014( + .A1(registers_4__ap[16]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[16]), + .ZN(n_1_0_965) + ); + SDFF_X1_LVT \registers_reg[19][16] ( + .CK(n_0_49), .D(registers[16]), .Q(registers_19__ap[16]), .QN(), .SE(dftIn), + .SI(registers_1__ap[16]) + ); + SDFF_X1_LVT \registers_reg[21][16] ( + .CK(n_0_51), .D(registers[16]), .Q(registers_21__ap[16]), .QN(), .SE(dftIn), + .SI(registers_19__ap[16]) + ); + AOI22_X1_LVT i_1_0_1013( + .A1(registers_19__ap[16]), .A2(n_1_0_1295), .B1(n_1_0_1259), .B2(registers_21__ap[16]), + .ZN(n_1_0_964) + ); + SDFF_X1_LVT \registers_reg[24][16] ( + .CK(n_0_54), .D(registers[16]), .Q(registers_24__ap[16]), .QN(), .SE(dftIn), + .SI(registers_28__ap[16]) + ); + SDFF_X1_LVT \registers_reg[20][16] ( + .CK(n_0_50), .D(registers[16]), .Q(registers_20__ap[16]), .QN(), .SE(dftIn), + .SI(registers_21__ap[16]) + ); + AOI22_X1_LVT i_1_0_1012( + .A1(registers_24__ap[16]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[16]), + .ZN(n_1_0_963) + ); + NAND3_X1_LVT i_1_0_1011( + .A1(n_1_0_965), .A2(n_1_0_964), .A3(n_1_0_963), .ZN(n_1_0_962) + ); + SDFF_X1_LVT \registers_reg[26][16] ( + .CK(n_0_56), .D(registers[16]), .Q(registers_26__ap[16]), .QN(), .SE(dftIn), + .SI(registers_24__ap[16]) + ); + SDFF_X1_LVT \registers_reg[30][16] ( + .CK(n_0_60), .D(registers[16]), .Q(registers_30__ap[16]), .QN(), .SE(dftIn), + .SI(registers_26__ap[16]) + ); + AOI221_X1_LVT i_1_0_1010( + .A(n_1_0_962), .B1(n_1_0_1285), .B2(registers_26__ap[16]), .C1(registers_30__ap[16]), + .C2(n_1_0_1272), .ZN(n_1_0_961) + ); + SDFF_X1_LVT \registers_reg[8][16] ( + .CK(n_0_38), .D(registers[16]), .Q(registers_8__ap[16]), .QN(), .SE(dftIn), + .SI(registers_4__ap[16]) + ); + SDFF_X1_LVT \registers_reg[23][16] ( + .CK(n_0_53), .D(registers[16]), .Q(registers_23__ap[16]), .QN(), .SE(dftIn), + .SI(registers_20__ap[16]) + ); + AOI22_X1_LVT i_1_0_1009( + .A1(registers_8__ap[16]), .A2(n_1_0_1282), .B1(n_1_0_1264), .B2(registers_23__ap[16]), + .ZN(n_1_0_960) + ); + SDFF_X1_LVT \registers_reg[13][16] ( + .CK(n_0_43), .D(registers[16]), .Q(registers_13__ap[16]), .QN(), .SE(dftIn), + .SI(registers_12__ap[16]) + ); + SDFF_X1_LVT \registers_reg[17][16] ( + .CK(n_0_47), .D(registers[16]), .Q(registers_17__ap[16]), .QN(), .SE(dftIn), + .SI(registers_23__ap[16]) + ); + AOI22_X1_LVT i_1_0_1008( + .A1(registers_13__ap[16]), .A2(n_1_0_1277), .B1(n_1_0_1271), .B2(registers_17__ap[16]), + .ZN(n_1_0_959) + ); + SDFF_X1_LVT \registers_reg[15][16] ( + .CK(n_0_45), .D(registers[16]), .Q(registers_15__ap[16]), .QN(), .SE(dftIn), + .SI(registers_13__ap[16]) + ); + SDFF_X1_LVT \registers_reg[14][16] ( + .CK(n_0_44), .D(registers[16]), .Q(registers_14__ap[16]), .QN(), .SE(dftIn), + .SI(registers_15__ap[16]) + ); + AOI22_X1_LVT i_1_0_1007( + .A1(registers_15__ap[16]), .A2(n_1_0_1286), .B1(n_1_0_1258), .B2(registers_14__ap[16]), + .ZN(n_1_0_958) + ); + NAND3_X1_LVT i_1_0_1006( + .A1(n_1_0_960), .A2(n_1_0_959), .A3(n_1_0_958), .ZN(n_1_0_957) + ); + SDFF_X1_LVT \registers_reg[27][16] ( + .CK(n_0_57), .D(registers[16]), .Q(registers_27__ap[16]), .QN(), .SE(dftIn), + .SI(registers_30__ap[16]) + ); + SDFF_X1_LVT \registers_reg[3][16] ( + .CK(n_0_33), .D(registers[16]), .Q(registers_3__ap[16]), .QN(), .SE(dftIn), + .SI(registers_8__ap[16]) + ); + AOI221_X1_LVT i_1_0_1005( + .A(n_1_0_957), .B1(n_1_0_1279), .B2(registers_27__ap[16]), .C1(registers_3__ap[16]), + .C2(n_1_0_1257), .ZN(n_1_0_956) + ); + NAND3_X1_LVT i_1_0_1004( + .A1(n_1_0_966), .A2(n_1_0_961), .A3(n_1_0_956), .ZN(RRs1[16]) + ); + AND2_X1_LVT i_0_0_15( + .A1(n_0_0_16), .A2(WRd[15]), .ZN(registers[15]) + ); + SDFF_X1_LVT \registers_reg[17][15] ( + .CK(n_0_47), .D(registers[15]), .Q(registers_17__ap[15]), .QN(), .SE(dftIn), + .SI(registers_17__ap[16]) + ); + SDFF_X1_LVT \registers_reg[21][15] ( + .CK(n_0_51), .D(registers[15]), .Q(registers_21__ap[15]), .QN(), .SE(dftIn), + .SI(registers_17__ap[15]) + ); + AOI22_X1_LVT i_1_0_1000( + .A1(registers_17__ap[15]), .A2(n_1_0_1271), .B1(n_1_0_1259), .B2(registers_21__ap[15]), + .ZN(n_1_0_952) + ); + SDFF_X1_LVT \registers_reg[10][15] ( + .CK(n_0_40), .D(registers[15]), .Q(registers_10__ap[15]), .QN(), .SE(dftIn), + .SI(registers_14__ap[16]) + ); + SDFF_X1_LVT \registers_reg[2][15] ( + .CK(n_0_32), .D(registers[15]), .Q(registers_2__ap[15]), .QN(), .SE(dftIn), + .SI(registers_27__ap[16]) + ); + AOI22_X1_LVT i_1_0_1003( + .A1(registers_10__ap[15]), .A2(n_1_0_1287), .B1(n_1_0_1268), .B2(registers_2__ap[15]), + .ZN(n_1_0_955) + ); + SDFF_X1_LVT \registers_reg[20][15] ( + .CK(n_0_50), .D(registers[15]), .Q(registers_20__ap[15]), .QN(), .SE(dftIn), + .SI(registers_21__ap[15]) + ); + SDFF_X1_LVT \registers_reg[12][15] ( + .CK(n_0_42), .D(registers[15]), .Q(registers_12__ap[15]), .QN(), .SE(dftIn), + .SI(registers_10__ap[15]) + ); + AOI22_X1_LVT i_1_0_999( + .A1(registers_20__ap[15]), .A2(n_1_0_1281), .B1(n_1_0_1260), .B2(registers_12__ap[15]), + .ZN(n_1_0_951) + ); + SDFF_X1_LVT \registers_reg[15][15] ( + .CK(n_0_45), .D(registers[15]), .Q(registers_15__ap[15]), .QN(), .SE(dftIn), + .SI(registers_12__ap[15]) + ); + SDFF_X1_LVT \registers_reg[8][15] ( + .CK(n_0_38), .D(registers[15]), .Q(registers_8__ap[15]), .QN(), .SE(dftIn), + .SI(registers_3__ap[16]) + ); + AOI22_X1_LVT i_1_0_1002( + .A1(registers_15__ap[15]), .A2(n_1_0_1286), .B1(n_1_0_1282), .B2(registers_8__ap[15]), + .ZN(n_1_0_954) + ); + INV_X1_LVT i_1_0_1001( + .A(n_1_0_954), .ZN(n_1_0_953) + ); + SDFF_X1_LVT \registers_reg[11][15] ( + .CK(n_0_41), .D(registers[15]), .Q(registers_11__ap[15]), .QN(), .SE(dftIn), + .SI(registers_15__ap[15]) + ); + SDFF_X1_LVT \registers_reg[24][15] ( + .CK(n_0_54), .D(registers[15]), .Q(registers_24__ap[15]), .QN(), .SE(dftIn), + .SI(registers_2__ap[15]) + ); + AOI221_X1_LVT i_1_0_998( + .A(n_1_0_953), .B1(n_1_0_1270), .B2(registers_11__ap[15]), .C1(registers_24__ap[15]), + .C2(n_1_0_1289), .ZN(n_1_0_950) + ); + SDFF_X1_LVT \registers_reg[13][15] ( + .CK(n_0_43), .D(registers[15]), .Q(registers_13__ap[15]), .QN(), .SE(dftIn), + .SI(registers_11__ap[15]) + ); + SDFF_X1_LVT \registers_reg[30][15] ( + .CK(n_0_60), .D(registers[15]), .Q(registers_30__ap[15]), .QN(), .SE(dftIn), + .SI(registers_24__ap[15]) + ); + SDFF_X1_LVT \registers_reg[22][15] ( + .CK(n_0_52), .D(registers[15]), .Q(registers_22__ap[15]), .QN(), .SE(dftIn), + .SI(registers_20__ap[15]) + ); + AOI222_X1_LVT i_1_0_997( + .A1(registers_13__ap[15]), .A2(n_1_0_1277), .B1(n_1_0_1272), .B2(registers_30__ap[15]), + .C1(registers_22__ap[15]), .C2(n_1_0_1294), .ZN(n_1_0_949) + ); + NAND4_X1_LVT i_1_0_996( + .A1(n_1_0_955), .A2(n_1_0_951), .A3(n_1_0_950), .A4(n_1_0_949), .ZN(n_1_0_948) + ); + SDFF_X1_LVT \registers_reg[1][15] ( + .CK(n_0_0), .D(registers[15]), .Q(registers_1__ap[15]), .QN(), .SE(dftIn), + .SI(registers_22__ap[15]) + ); + SDFF_X1_LVT \registers_reg[28][15] ( + .CK(n_0_58), .D(registers[15]), .Q(registers_28__ap[15]), .QN(), .SE(dftIn), + .SI(registers_30__ap[15]) + ); + AOI221_X1_LVT i_1_0_995( + .A(n_1_0_948), .B1(n_1_0_1274), .B2(registers_1__ap[15]), .C1(registers_28__ap[15]), + .C2(n_1_0_1283), .ZN(n_1_0_947) + ); + SDFF_X1_LVT \registers_reg[18][15] ( + .CK(n_0_48), .D(registers[15]), .Q(registers_18__ap[15]), .QN(), .SE(dftIn), + .SI(registers_1__ap[15]) + ); + SDFF_X1_LVT \registers_reg[26][15] ( + .CK(n_0_56), .D(registers[15]), .Q(registers_26__ap[15]), .QN(), .SE(dftIn), + .SI(registers_28__ap[15]) + ); + AOI22_X1_LVT i_1_0_994( + .A1(registers_18__ap[15]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[15]), + .ZN(n_1_0_946) + ); + SDFF_X1_LVT \registers_reg[4][15] ( + .CK(n_0_34), .D(registers[15]), .Q(registers_4__ap[15]), .QN(), .SE(dftIn), + .SI(registers_8__ap[15]) + ); + SDFF_X1_LVT \registers_reg[5][15] ( + .CK(n_0_35), .D(registers[15]), .Q(registers_5__ap[15]), .QN(), .SE(dftIn), + .SI(registers_4__ap[15]) + ); + AOI22_X1_LVT i_1_0_993( + .A1(registers_4__ap[15]), .A2(n_1_0_1278), .B1(n_1_0_1273), .B2(registers_5__ap[15]), + .ZN(n_1_0_945) + ); + SDFF_X1_LVT \registers_reg[6][15] ( + .CK(n_0_36), .D(registers[15]), .Q(registers_6__ap[15]), .QN(), .SE(dftIn), + .SI(registers_5__ap[15]) + ); + SDFF_X1_LVT \registers_reg[16][15] ( + .CK(n_0_46), .D(registers[15]), .Q(registers_16__ap[15]), .QN(), .SE(dftIn), + .SI(registers_13__ap[15]) + ); + AOI22_X1_LVT i_1_0_992( + .A1(registers_6__ap[15]), .A2(n_1_0_1300), .B1(n_1_0_1267), .B2(registers_16__ap[15]), + .ZN(n_1_0_944) + ); + NAND3_X1_LVT i_1_0_991( + .A1(n_1_0_946), .A2(n_1_0_945), .A3(n_1_0_944), .ZN(n_1_0_943) + ); + SDFF_X1_LVT \registers_reg[19][15] ( + .CK(n_0_49), .D(registers[15]), .Q(registers_19__ap[15]), .QN(), .SE(dftIn), + .SI(registers_18__ap[15]) + ); + SDFF_X1_LVT \registers_reg[25][15] ( + .CK(n_0_55), .D(registers[15]), .Q(registers_25__ap[15]), .QN(), .SE(dftIn), + .SI(registers_26__ap[15]) + ); + AOI221_X1_LVT i_1_0_990( + .A(n_1_0_943), .B1(n_1_0_1295), .B2(registers_19__ap[15]), .C1(registers_25__ap[15]), + .C2(n_1_0_1269), .ZN(n_1_0_942) + ); + SDFF_X1_LVT \registers_reg[7][15] ( + .CK(n_0_37), .D(registers[15]), .Q(registers_7__ap[15]), .QN(), .SE(dftIn), + .SI(registers_6__ap[15]) + ); + SDFF_X1_LVT \registers_reg[14][15] ( + .CK(n_0_44), .D(registers[15]), .Q(registers_14__ap[15]), .QN(), .SE(dftIn), + .SI(registers_16__ap[15]) + ); + AOI22_X1_LVT i_1_0_989( + .A1(registers_7__ap[15]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[15]), + .ZN(n_1_0_941) + ); + SDFF_X1_LVT \registers_reg[9][15] ( + .CK(n_0_39), .D(registers[15]), .Q(registers_9__ap[15]), .QN(), .SE(dftIn), + .SI(registers_7__ap[15]) + ); + SDFF_X1_LVT \registers_reg[29][15] ( + .CK(n_0_59), .D(registers[15]), .Q(registers_29__ap[15]), .QN(), .SE(dftIn), + .SI(registers_25__ap[15]) + ); + AOI22_X1_LVT i_1_0_988( + .A1(registers_9__ap[15]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[15]), + .ZN(n_1_0_940) + ); + SDFF_X1_LVT \registers_reg[23][15] ( + .CK(n_0_53), .D(registers[15]), .Q(registers_23__ap[15]), .QN(), .SE(dftIn), + .SI(registers_19__ap[15]) + ); + SDFF_X1_LVT \registers_reg[3][15] ( + .CK(n_0_33), .D(registers[15]), .Q(registers_3__ap[15]), .QN(), .SE(dftIn), + .SI(registers_9__ap[15]) + ); + AOI22_X1_LVT i_1_0_987( + .A1(registers_23__ap[15]), .A2(n_1_0_1264), .B1(n_1_0_1257), .B2(registers_3__ap[15]), + .ZN(n_1_0_939) + ); + NAND3_X1_LVT i_1_0_986( + .A1(n_1_0_941), .A2(n_1_0_940), .A3(n_1_0_939), .ZN(n_1_0_938) + ); + SDFF_X1_LVT \registers_reg[27][15] ( + .CK(n_0_57), .D(registers[15]), .Q(registers_27__ap[15]), .QN(), .SE(dftIn), + .SI(registers_29__ap[15]) + ); + SDFF_X1_LVT \registers_reg[31][15] ( + .CK(n_0_61), .D(registers[15]), .Q(registers_31__ap[15]), .QN(), .SE(dftIn), + .SI(registers_3__ap[15]) + ); + AOI221_X1_LVT i_1_0_985( + .A(n_1_0_938), .B1(n_1_0_1279), .B2(registers_27__ap[15]), .C1(registers_31__ap[15]), + .C2(n_1_0_1266), .ZN(n_1_0_937) + ); + NAND4_X1_LVT i_1_0_984( + .A1(n_1_0_952), .A2(n_1_0_947), .A3(n_1_0_942), .A4(n_1_0_937), .ZN(RRs1[15]) + ); + AND2_X1_LVT i_0_0_14( + .A1(n_0_0_16), .A2(WRd[14]), .ZN(registers[14]) + ); + SDFF_X1_LVT \registers_reg[28][14] ( + .CK(n_0_58), .D(registers[14]), .Q(registers_28__ap[14]), .QN(), .SE(dftIn), + .SI(registers_27__ap[15]) + ); + SDFF_X1_LVT \registers_reg[5][14] ( + .CK(n_0_35), .D(registers[14]), .Q(registers_5__ap[14]), .QN(), .SE(dftIn), + .SI(registers_31__ap[15]) + ); + AOI22_X1_LVT i_1_0_983( + .A1(registers_28__ap[14]), .A2(n_1_0_1283), .B1(n_1_0_1273), .B2(registers_5__ap[14]), + .ZN(n_1_0_936) + ); + SDFF_X1_LVT \registers_reg[18][14] ( + .CK(n_0_48), .D(registers[14]), .Q(registers_18__ap[14]), .QN(), .SE(dftIn), + .SI(registers_23__ap[15]) + ); + SDFF_X1_LVT \registers_reg[10][14] ( + .CK(n_0_40), .D(registers[14]), .Q(registers_10__ap[14]), .QN(), .SE(dftIn), + .SI(registers_14__ap[15]) + ); + SDFF_X1_LVT \registers_reg[8][14] ( + .CK(n_0_38), .D(registers[14]), .Q(registers_8__ap[14]), .QN(), .SE(dftIn), + .SI(registers_5__ap[14]) + ); + AOI222_X1_LVT i_1_0_982( + .A1(registers_18__ap[14]), .A2(n_1_0_1297), .B1(n_1_0_1287), .B2(registers_10__ap[14]), + .C1(n_1_0_1282), .C2(registers_8__ap[14]), .ZN(n_1_0_935) + ); + SDFF_X1_LVT \registers_reg[9][14] ( + .CK(n_0_39), .D(registers[14]), .Q(registers_9__ap[14]), .QN(), .SE(dftIn), + .SI(registers_8__ap[14]) + ); + SDFF_X1_LVT \registers_reg[29][14] ( + .CK(n_0_59), .D(registers[14]), .Q(registers_29__ap[14]), .QN(), .SE(dftIn), + .SI(registers_28__ap[14]) + ); + AOI22_X1_LVT i_1_0_981( + .A1(registers_9__ap[14]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[14]), + .ZN(n_1_0_934) + ); + SDFF_X1_LVT \registers_reg[21][14] ( + .CK(n_0_51), .D(registers[14]), .Q(registers_21__ap[14]), .QN(), .SE(dftIn), + .SI(registers_18__ap[14]) + ); + SDFF_X1_LVT \registers_reg[14][14] ( + .CK(n_0_44), .D(registers[14]), .Q(registers_14__ap[14]), .QN(), .SE(dftIn), + .SI(registers_10__ap[14]) + ); + AOI22_X1_LVT i_1_0_980( + .A1(registers_21__ap[14]), .A2(n_1_0_1259), .B1(n_1_0_1258), .B2(registers_14__ap[14]), + .ZN(n_1_0_933) + ); + SDFF_X1_LVT \registers_reg[16][14] ( + .CK(n_0_46), .D(registers[14]), .Q(registers_16__ap[14]), .QN(), .SE(dftIn), + .SI(registers_14__ap[14]) + ); + SDFF_X1_LVT \registers_reg[3][14] ( + .CK(n_0_33), .D(registers[14]), .Q(registers_3__ap[14]), .QN(), .SE(dftIn), + .SI(registers_9__ap[14]) + ); + AOI22_X1_LVT i_1_0_979( + .A1(registers_16__ap[14]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[14]), + .ZN(n_1_0_932) + ); + SDFF_X1_LVT \registers_reg[17][14] ( + .CK(n_0_47), .D(registers[14]), .Q(registers_17__ap[14]), .QN(), .SE(dftIn), + .SI(registers_21__ap[14]) + ); + SDFF_X1_LVT \registers_reg[31][14] ( + .CK(n_0_61), .D(registers[14]), .Q(registers_31__ap[14]), .QN(), .SE(dftIn), + .SI(registers_3__ap[14]) + ); + AOI22_X1_LVT i_1_0_978( + .A1(registers_17__ap[14]), .A2(n_1_0_1271), .B1(n_1_0_1266), .B2(registers_31__ap[14]), + .ZN(n_1_0_931) + ); + SDFF_X1_LVT \registers_reg[15][14] ( + .CK(n_0_45), .D(registers[14]), .Q(registers_15__ap[14]), .QN(), .SE(dftIn), + .SI(registers_16__ap[14]) + ); + SDFF_X1_LVT \registers_reg[23][14] ( + .CK(n_0_53), .D(registers[14]), .Q(registers_23__ap[14]), .QN(), .SE(dftIn), + .SI(registers_17__ap[14]) + ); + AOI22_X1_LVT i_1_0_977( + .A1(registers_15__ap[14]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[14]), + .ZN(n_1_0_930) + ); + NAND4_X1_LVT i_1_0_976( + .A1(n_1_0_933), .A2(n_1_0_932), .A3(n_1_0_931), .A4(n_1_0_930), .ZN(n_1_0_929) + ); + SDFF_X1_LVT \registers_reg[26][14] ( + .CK(n_0_56), .D(registers[14]), .Q(registers_26__ap[14]), .QN(), .SE(dftIn), + .SI(registers_29__ap[14]) + ); + SDFF_X1_LVT \registers_reg[30][14] ( + .CK(n_0_60), .D(registers[14]), .Q(registers_30__ap[14]), .QN(), .SE(dftIn), + .SI(registers_26__ap[14]) + ); + AOI22_X1_LVT i_1_0_975( + .A1(registers_26__ap[14]), .A2(n_1_0_1285), .B1(n_1_0_1272), .B2(registers_30__ap[14]), + .ZN(n_1_0_928) + ); + SDFF_X1_LVT \registers_reg[20][14] ( + .CK(n_0_50), .D(registers[14]), .Q(registers_20__ap[14]), .QN(), .SE(dftIn), + .SI(registers_23__ap[14]) + ); + SDFF_X1_LVT \registers_reg[4][14] ( + .CK(n_0_34), .D(registers[14]), .Q(registers_4__ap[14]), .QN(), .SE(dftIn), + .SI(registers_31__ap[14]) + ); + AOI22_X1_LVT i_1_0_974( + .A1(registers_20__ap[14]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[14]), + .ZN(n_1_0_927) + ); + SDFF_X1_LVT \registers_reg[1][14] ( + .CK(n_0_0), .D(registers[14]), .Q(registers_1__ap[14]), .QN(), .SE(dftIn), + .SI(registers_20__ap[14]) + ); + SDFF_X1_LVT \registers_reg[2][14] ( + .CK(n_0_32), .D(registers[14]), .Q(registers_2__ap[14]), .QN(), .SE(dftIn), + .SI(registers_30__ap[14]) + ); + AOI22_X1_LVT i_1_0_973( + .A1(registers_1__ap[14]), .A2(n_1_0_1274), .B1(n_1_0_1268), .B2(registers_2__ap[14]), + .ZN(n_1_0_926) + ); + SDFF_X1_LVT \registers_reg[24][14] ( + .CK(n_0_54), .D(registers[14]), .Q(registers_24__ap[14]), .QN(), .SE(dftIn), + .SI(registers_2__ap[14]) + ); + SDFF_X1_LVT \registers_reg[12][14] ( + .CK(n_0_42), .D(registers[14]), .Q(registers_12__ap[14]), .QN(), .SE(dftIn), + .SI(registers_15__ap[14]) + ); + AOI22_X1_LVT i_1_0_972( + .A1(registers_24__ap[14]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[14]), + .ZN(n_1_0_925) + ); + NAND4_X1_LVT i_1_0_971( + .A1(n_1_0_928), .A2(n_1_0_927), .A3(n_1_0_926), .A4(n_1_0_925), .ZN(n_1_0_924) + ); + SDFF_X1_LVT \registers_reg[19][14] ( + .CK(n_0_49), .D(registers[14]), .Q(registers_19__ap[14]), .QN(), .SE(dftIn), + .SI(registers_1__ap[14]) + ); + SDFF_X1_LVT \registers_reg[22][14] ( + .CK(n_0_52), .D(registers[14]), .Q(registers_22__ap[14]), .QN(), .SE(dftIn), + .SI(registers_19__ap[14]) + ); + AOI22_X1_LVT i_1_0_970( + .A1(registers_19__ap[14]), .A2(n_1_0_1295), .B1(n_1_0_1294), .B2(registers_22__ap[14]), + .ZN(n_1_0_923) + ); + SDFF_X1_LVT \registers_reg[13][14] ( + .CK(n_0_43), .D(registers[14]), .Q(registers_13__ap[14]), .QN(), .SE(dftIn), + .SI(registers_12__ap[14]) + ); + SDFF_X1_LVT \registers_reg[25][14] ( + .CK(n_0_55), .D(registers[14]), .Q(registers_25__ap[14]), .QN(), .SE(dftIn), + .SI(registers_24__ap[14]) + ); + AOI22_X1_LVT i_1_0_969( + .A1(registers_13__ap[14]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[14]), + .ZN(n_1_0_922) + ); + SDFF_X1_LVT \registers_reg[6][14] ( + .CK(n_0_36), .D(registers[14]), .Q(registers_6__ap[14]), .QN(), .SE(dftIn), + .SI(registers_4__ap[14]) + ); + SDFF_X1_LVT \registers_reg[7][14] ( + .CK(n_0_37), .D(registers[14]), .Q(registers_7__ap[14]), .QN(), .SE(dftIn), + .SI(registers_6__ap[14]) + ); + AOI22_X1_LVT i_1_0_968( + .A1(registers_6__ap[14]), .A2(n_1_0_1300), .B1(n_1_0_1263), .B2(registers_7__ap[14]), + .ZN(n_1_0_921) + ); + SDFF_X1_LVT \registers_reg[27][14] ( + .CK(n_0_57), .D(registers[14]), .Q(registers_27__ap[14]), .QN(), .SE(dftIn), + .SI(registers_25__ap[14]) + ); + SDFF_X1_LVT \registers_reg[11][14] ( + .CK(n_0_41), .D(registers[14]), .Q(registers_11__ap[14]), .QN(), .SE(dftIn), + .SI(registers_13__ap[14]) + ); + AOI22_X1_LVT i_1_0_967( + .A1(registers_27__ap[14]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[14]), + .ZN(n_1_0_920) + ); + NAND4_X1_LVT i_1_0_966( + .A1(n_1_0_923), .A2(n_1_0_922), .A3(n_1_0_921), .A4(n_1_0_920), .ZN(n_1_0_919) + ); + NOR3_X1_LVT i_1_0_965( + .A1(n_1_0_929), .A2(n_1_0_924), .A3(n_1_0_919), .ZN(n_1_0_918) + ); + NAND4_X1_LVT i_1_0_964( + .A1(n_1_0_936), .A2(n_1_0_935), .A3(n_1_0_934), .A4(n_1_0_918), .ZN(RRs1[14]) + ); + AND2_X1_LVT i_0_0_13( + .A1(n_0_0_16), .A2(WRd[13]), .ZN(registers[13]) + ); + SDFF_X1_LVT \registers_reg[28][13] ( + .CK(n_0_58), .D(registers[13]), .Q(registers_28__ap[13]), .QN(), .SE(dftIn), + .SI(registers_27__ap[14]) + ); + SDFF_X1_LVT \registers_reg[4][13] ( + .CK(n_0_34), .D(registers[13]), .Q(registers_4__ap[13]), .QN(), .SE(dftIn), + .SI(registers_7__ap[14]) + ); + AOI22_X1_LVT i_1_0_963( + .A1(registers_28__ap[13]), .A2(n_1_0_1283), .B1(n_1_0_1278), .B2(registers_4__ap[13]), + .ZN(n_1_0_917) + ); + SDFF_X1_LVT \registers_reg[10][13] ( + .CK(n_0_40), .D(registers[13]), .Q(registers_10__ap[13]), .QN(), .SE(dftIn), + .SI(registers_11__ap[14]) + ); + SDFF_X1_LVT \registers_reg[26][13] ( + .CK(n_0_56), .D(registers[13]), .Q(registers_26__ap[13]), .QN(), .SE(dftIn), + .SI(registers_28__ap[13]) + ); + SDFF_X1_LVT \registers_reg[8][13] ( + .CK(n_0_38), .D(registers[13]), .Q(registers_8__ap[13]), .QN(), .SE(dftIn), + .SI(registers_4__ap[13]) + ); + AOI222_X1_LVT i_1_0_962( + .A1(registers_10__ap[13]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[13]), + .C1(registers_8__ap[13]), .C2(n_1_0_1282), .ZN(n_1_0_916) + ); + SDFF_X1_LVT \registers_reg[9][13] ( + .CK(n_0_39), .D(registers[13]), .Q(registers_9__ap[13]), .QN(), .SE(dftIn), + .SI(registers_8__ap[13]) + ); + SDFF_X1_LVT \registers_reg[29][13] ( + .CK(n_0_59), .D(registers[13]), .Q(registers_29__ap[13]), .QN(), .SE(dftIn), + .SI(registers_26__ap[13]) + ); + AOI22_X1_LVT i_1_0_961( + .A1(registers_9__ap[13]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[13]), + .ZN(n_1_0_915) + ); + SDFF_X1_LVT \registers_reg[6][13] ( + .CK(n_0_36), .D(registers[13]), .Q(registers_6__ap[13]), .QN(), .SE(dftIn), + .SI(registers_9__ap[13]) + ); + SDFF_X1_LVT \registers_reg[1][13] ( + .CK(n_0_0), .D(registers[13]), .Q(registers_1__ap[13]), .QN(), .SE(dftIn), + .SI(registers_22__ap[14]) + ); + AOI22_X1_LVT i_1_0_960( + .A1(registers_6__ap[13]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[13]), + .ZN(n_1_0_914) + ); + SDFF_X1_LVT \registers_reg[5][13] ( + .CK(n_0_35), .D(registers[13]), .Q(registers_5__ap[13]), .QN(), .SE(dftIn), + .SI(registers_6__ap[13]) + ); + SDFF_X1_LVT \registers_reg[3][13] ( + .CK(n_0_33), .D(registers[13]), .Q(registers_3__ap[13]), .QN(), .SE(dftIn), + .SI(registers_5__ap[13]) + ); + AOI22_X1_LVT i_1_0_959( + .A1(registers_5__ap[13]), .A2(n_1_0_1273), .B1(n_1_0_1257), .B2(registers_3__ap[13]), + .ZN(n_1_0_913) + ); + SDFF_X1_LVT \registers_reg[16][13] ( + .CK(n_0_46), .D(registers[13]), .Q(registers_16__ap[13]), .QN(), .SE(dftIn), + .SI(registers_10__ap[13]) + ); + SDFF_X1_LVT \registers_reg[31][13] ( + .CK(n_0_61), .D(registers[13]), .Q(registers_31__ap[13]), .QN(), .SE(dftIn), + .SI(registers_3__ap[13]) + ); + AOI22_X1_LVT i_1_0_958( + .A1(registers_16__ap[13]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[13]), + .ZN(n_1_0_912) + ); + SDFF_X1_LVT \registers_reg[15][13] ( + .CK(n_0_45), .D(registers[13]), .Q(registers_15__ap[13]), .QN(), .SE(dftIn), + .SI(registers_16__ap[13]) + ); + SDFF_X1_LVT \registers_reg[23][13] ( + .CK(n_0_53), .D(registers[13]), .Q(registers_23__ap[13]), .QN(), .SE(dftIn), + .SI(registers_1__ap[13]) + ); + AOI22_X1_LVT i_1_0_957( + .A1(registers_15__ap[13]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[13]), + .ZN(n_1_0_911) + ); + NAND4_X1_LVT i_1_0_956( + .A1(n_1_0_914), .A2(n_1_0_913), .A3(n_1_0_912), .A4(n_1_0_911), .ZN(n_1_0_910) + ); + SDFF_X1_LVT \registers_reg[18][13] ( + .CK(n_0_48), .D(registers[13]), .Q(registers_18__ap[13]), .QN(), .SE(dftIn), + .SI(registers_23__ap[13]) + ); + SDFF_X1_LVT \registers_reg[30][13] ( + .CK(n_0_60), .D(registers[13]), .Q(registers_30__ap[13]), .QN(), .SE(dftIn), + .SI(registers_29__ap[13]) + ); + AOI22_X1_LVT i_1_0_955( + .A1(registers_18__ap[13]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[13]), + .ZN(n_1_0_909) + ); + SDFF_X1_LVT \registers_reg[24][13] ( + .CK(n_0_54), .D(registers[13]), .Q(registers_24__ap[13]), .QN(), .SE(dftIn), + .SI(registers_30__ap[13]) + ); + SDFF_X1_LVT \registers_reg[12][13] ( + .CK(n_0_42), .D(registers[13]), .Q(registers_12__ap[13]), .QN(), .SE(dftIn), + .SI(registers_15__ap[13]) + ); + AOI22_X1_LVT i_1_0_954( + .A1(registers_24__ap[13]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[13]), + .ZN(n_1_0_908) + ); + SDFF_X1_LVT \registers_reg[22][13] ( + .CK(n_0_52), .D(registers[13]), .Q(registers_22__ap[13]), .QN(), .SE(dftIn), + .SI(registers_18__ap[13]) + ); + SDFF_X1_LVT \registers_reg[21][13] ( + .CK(n_0_51), .D(registers[13]), .Q(registers_21__ap[13]), .QN(), .SE(dftIn), + .SI(registers_22__ap[13]) + ); + AOI22_X1_LVT i_1_0_953( + .A1(registers_22__ap[13]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[13]), + .ZN(n_1_0_907) + ); + SDFF_X1_LVT \registers_reg[20][13] ( + .CK(n_0_50), .D(registers[13]), .Q(registers_20__ap[13]), .QN(), .SE(dftIn), + .SI(registers_21__ap[13]) + ); + SDFF_X1_LVT \registers_reg[17][13] ( + .CK(n_0_47), .D(registers[13]), .Q(registers_17__ap[13]), .QN(), .SE(dftIn), + .SI(registers_20__ap[13]) + ); + AOI22_X1_LVT i_1_0_952( + .A1(registers_20__ap[13]), .A2(n_1_0_1281), .B1(n_1_0_1271), .B2(registers_17__ap[13]), + .ZN(n_1_0_906) + ); + NAND4_X1_LVT i_1_0_951( + .A1(n_1_0_909), .A2(n_1_0_908), .A3(n_1_0_907), .A4(n_1_0_906), .ZN(n_1_0_905) + ); + SDFF_X1_LVT \registers_reg[13][13] ( + .CK(n_0_43), .D(registers[13]), .Q(registers_13__ap[13]), .QN(), .SE(dftIn), + .SI(registers_12__ap[13]) + ); + SDFF_X1_LVT \registers_reg[25][13] ( + .CK(n_0_55), .D(registers[13]), .Q(registers_25__ap[13]), .QN(), .SE(dftIn), + .SI(registers_24__ap[13]) + ); + AOI22_X1_LVT i_1_0_950( + .A1(registers_13__ap[13]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[13]), + .ZN(n_1_0_904) + ); + SDFF_X1_LVT \registers_reg[19][13] ( + .CK(n_0_49), .D(registers[13]), .Q(registers_19__ap[13]), .QN(), .SE(dftIn), + .SI(registers_17__ap[13]) + ); + SDFF_X1_LVT \registers_reg[2][13] ( + .CK(n_0_32), .D(registers[13]), .Q(registers_2__ap[13]), .QN(), .SE(dftIn), + .SI(registers_25__ap[13]) + ); + AOI22_X1_LVT i_1_0_949( + .A1(registers_19__ap[13]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[13]), + .ZN(n_1_0_903) + ); + SDFF_X1_LVT \registers_reg[7][13] ( + .CK(n_0_37), .D(registers[13]), .Q(registers_7__ap[13]), .QN(), .SE(dftIn), + .SI(registers_31__ap[13]) + ); + SDFF_X1_LVT \registers_reg[14][13] ( + .CK(n_0_44), .D(registers[13]), .Q(registers_14__ap[13]), .QN(), .SE(dftIn), + .SI(registers_13__ap[13]) + ); + AOI22_X1_LVT i_1_0_948( + .A1(registers_7__ap[13]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[13]), + .ZN(n_1_0_902) + ); + SDFF_X1_LVT \registers_reg[27][13] ( + .CK(n_0_57), .D(registers[13]), .Q(registers_27__ap[13]), .QN(), .SE(dftIn), + .SI(registers_2__ap[13]) + ); + SDFF_X1_LVT \registers_reg[11][13] ( + .CK(n_0_41), .D(registers[13]), .Q(registers_11__ap[13]), .QN(), .SE(dftIn), + .SI(registers_14__ap[13]) + ); + AOI22_X1_LVT i_1_0_947( + .A1(registers_27__ap[13]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[13]), + .ZN(n_1_0_901) + ); + NAND4_X1_LVT i_1_0_946( + .A1(n_1_0_904), .A2(n_1_0_903), .A3(n_1_0_902), .A4(n_1_0_901), .ZN(n_1_0_900) + ); + NOR3_X1_LVT i_1_0_945( + .A1(n_1_0_910), .A2(n_1_0_905), .A3(n_1_0_900), .ZN(n_1_0_899) + ); + NAND4_X1_LVT i_1_0_944( + .A1(n_1_0_917), .A2(n_1_0_916), .A3(n_1_0_915), .A4(n_1_0_899), .ZN(RRs1[13]) + ); + AND2_X1_LVT i_0_0_12( + .A1(n_0_0_16), .A2(WRd[12]), .ZN(registers[12]) + ); + SDFF_X1_LVT \registers_reg[28][12] ( + .CK(n_0_58), .D(registers[12]), .Q(registers_28__ap[12]), .QN(), .SE(dftIn), + .SI(registers_27__ap[13]) + ); + SDFF_X1_LVT \registers_reg[17][12] ( + .CK(n_0_47), .D(registers[12]), .Q(registers_17__ap[12]), .QN(), .SE(dftIn), + .SI(registers_19__ap[13]) + ); + AOI22_X1_LVT i_1_0_943( + .A1(registers_28__ap[12]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[12]), + .ZN(n_1_0_898) + ); + SDFF_X1_LVT \registers_reg[10][12] ( + .CK(n_0_40), .D(registers[12]), .Q(registers_10__ap[12]), .QN(), .SE(dftIn), + .SI(registers_11__ap[13]) + ); + SDFF_X1_LVT \registers_reg[26][12] ( + .CK(n_0_56), .D(registers[12]), .Q(registers_26__ap[12]), .QN(), .SE(dftIn), + .SI(registers_28__ap[12]) + ); + SDFF_X1_LVT \registers_reg[8][12] ( + .CK(n_0_38), .D(registers[12]), .Q(registers_8__ap[12]), .QN(), .SE(dftIn), + .SI(registers_7__ap[13]) + ); + AOI222_X1_LVT i_1_0_942( + .A1(registers_10__ap[12]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[12]), + .C1(registers_8__ap[12]), .C2(n_1_0_1282), .ZN(n_1_0_897) + ); + SDFF_X1_LVT \registers_reg[9][12] ( + .CK(n_0_39), .D(registers[12]), .Q(registers_9__ap[12]), .QN(), .SE(dftIn), + .SI(registers_8__ap[12]) + ); + SDFF_X1_LVT \registers_reg[29][12] ( + .CK(n_0_59), .D(registers[12]), .Q(registers_29__ap[12]), .QN(), .SE(dftIn), + .SI(registers_26__ap[12]) + ); + AOI22_X1_LVT i_1_0_941( + .A1(registers_9__ap[12]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[12]), + .ZN(n_1_0_896) + ); + SDFF_X1_LVT \registers_reg[6][12] ( + .CK(n_0_36), .D(registers[12]), .Q(registers_6__ap[12]), .QN(), .SE(dftIn), + .SI(registers_9__ap[12]) + ); + SDFF_X1_LVT \registers_reg[1][12] ( + .CK(n_0_0), .D(registers[12]), .Q(registers_1__ap[12]), .QN(), .SE(dftIn), + .SI(registers_17__ap[12]) + ); + AOI22_X1_LVT i_1_0_940( + .A1(registers_6__ap[12]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[12]), + .ZN(n_1_0_895) + ); + SDFF_X1_LVT \registers_reg[16][12] ( + .CK(n_0_46), .D(registers[12]), .Q(registers_16__ap[12]), .QN(), .SE(dftIn), + .SI(registers_10__ap[12]) + ); + SDFF_X1_LVT \registers_reg[3][12] ( + .CK(n_0_33), .D(registers[12]), .Q(registers_3__ap[12]), .QN(), .SE(dftIn), + .SI(registers_6__ap[12]) + ); + AOI22_X1_LVT i_1_0_939( + .A1(registers_16__ap[12]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[12]), + .ZN(n_1_0_894) + ); + SDFF_X1_LVT \registers_reg[5][12] ( + .CK(n_0_35), .D(registers[12]), .Q(registers_5__ap[12]), .QN(), .SE(dftIn), + .SI(registers_3__ap[12]) + ); + SDFF_X1_LVT \registers_reg[31][12] ( + .CK(n_0_61), .D(registers[12]), .Q(registers_31__ap[12]), .QN(), .SE(dftIn), + .SI(registers_5__ap[12]) + ); + AOI22_X1_LVT i_1_0_938( + .A1(registers_5__ap[12]), .A2(n_1_0_1273), .B1(n_1_0_1266), .B2(registers_31__ap[12]), + .ZN(n_1_0_893) + ); + SDFF_X1_LVT \registers_reg[15][12] ( + .CK(n_0_45), .D(registers[12]), .Q(registers_15__ap[12]), .QN(), .SE(dftIn), + .SI(registers_16__ap[12]) + ); + SDFF_X1_LVT \registers_reg[23][12] ( + .CK(n_0_53), .D(registers[12]), .Q(registers_23__ap[12]), .QN(), .SE(dftIn), + .SI(registers_1__ap[12]) + ); + AOI22_X1_LVT i_1_0_937( + .A1(registers_15__ap[12]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[12]), + .ZN(n_1_0_892) + ); + NAND4_X1_LVT i_1_0_936( + .A1(n_1_0_895), .A2(n_1_0_894), .A3(n_1_0_893), .A4(n_1_0_892), .ZN(n_1_0_891) + ); + SDFF_X1_LVT \registers_reg[18][12] ( + .CK(n_0_48), .D(registers[12]), .Q(registers_18__ap[12]), .QN(), .SE(dftIn), + .SI(registers_23__ap[12]) + ); + SDFF_X1_LVT \registers_reg[30][12] ( + .CK(n_0_60), .D(registers[12]), .Q(registers_30__ap[12]), .QN(), .SE(dftIn), + .SI(registers_29__ap[12]) + ); + AOI22_X1_LVT i_1_0_935( + .A1(registers_18__ap[12]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[12]), + .ZN(n_1_0_890) + ); + SDFF_X1_LVT \registers_reg[20][12] ( + .CK(n_0_50), .D(registers[12]), .Q(registers_20__ap[12]), .QN(), .SE(dftIn), + .SI(registers_18__ap[12]) + ); + SDFF_X1_LVT \registers_reg[4][12] ( + .CK(n_0_34), .D(registers[12]), .Q(registers_4__ap[12]), .QN(), .SE(dftIn), + .SI(registers_31__ap[12]) + ); + AOI22_X1_LVT i_1_0_934( + .A1(registers_20__ap[12]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[12]), + .ZN(n_1_0_889) + ); + SDFF_X1_LVT \registers_reg[22][12] ( + .CK(n_0_52), .D(registers[12]), .Q(registers_22__ap[12]), .QN(), .SE(dftIn), + .SI(registers_20__ap[12]) + ); + SDFF_X1_LVT \registers_reg[21][12] ( + .CK(n_0_51), .D(registers[12]), .Q(registers_21__ap[12]), .QN(), .SE(dftIn), + .SI(registers_22__ap[12]) + ); + AOI22_X1_LVT i_1_0_933( + .A1(registers_22__ap[12]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[12]), + .ZN(n_1_0_888) + ); + SDFF_X1_LVT \registers_reg[24][12] ( + .CK(n_0_54), .D(registers[12]), .Q(registers_24__ap[12]), .QN(), .SE(dftIn), + .SI(registers_30__ap[12]) + ); + SDFF_X1_LVT \registers_reg[12][12] ( + .CK(n_0_42), .D(registers[12]), .Q(registers_12__ap[12]), .QN(), .SE(dftIn), + .SI(registers_15__ap[12]) + ); + AOI22_X1_LVT i_1_0_932( + .A1(registers_24__ap[12]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[12]), + .ZN(n_1_0_887) + ); + NAND4_X1_LVT i_1_0_931( + .A1(n_1_0_890), .A2(n_1_0_889), .A3(n_1_0_888), .A4(n_1_0_887), .ZN(n_1_0_886) + ); + SDFF_X1_LVT \registers_reg[13][12] ( + .CK(n_0_43), .D(registers[12]), .Q(registers_13__ap[12]), .QN(), .SE(dftIn), + .SI(registers_12__ap[12]) + ); + SDFF_X1_LVT \registers_reg[25][12] ( + .CK(n_0_55), .D(registers[12]), .Q(registers_25__ap[12]), .QN(), .SE(dftIn), + .SI(registers_24__ap[12]) + ); + AOI22_X1_LVT i_1_0_930( + .A1(registers_13__ap[12]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[12]), + .ZN(n_1_0_885) + ); + SDFF_X1_LVT \registers_reg[19][12] ( + .CK(n_0_49), .D(registers[12]), .Q(registers_19__ap[12]), .QN(), .SE(dftIn), + .SI(registers_21__ap[12]) + ); + SDFF_X1_LVT \registers_reg[2][12] ( + .CK(n_0_32), .D(registers[12]), .Q(registers_2__ap[12]), .QN(), .SE(dftIn), + .SI(registers_25__ap[12]) + ); + AOI22_X1_LVT i_1_0_929( + .A1(registers_19__ap[12]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[12]), + .ZN(n_1_0_884) + ); + SDFF_X1_LVT \registers_reg[7][12] ( + .CK(n_0_37), .D(registers[12]), .Q(registers_7__ap[12]), .QN(), .SE(dftIn), + .SI(registers_4__ap[12]) + ); + SDFF_X1_LVT \registers_reg[14][12] ( + .CK(n_0_44), .D(registers[12]), .Q(registers_14__ap[12]), .QN(), .SE(dftIn), + .SI(registers_13__ap[12]) + ); + AOI22_X1_LVT i_1_0_928( + .A1(registers_7__ap[12]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[12]), + .ZN(n_1_0_883) + ); + SDFF_X1_LVT \registers_reg[27][12] ( + .CK(n_0_57), .D(registers[12]), .Q(registers_27__ap[12]), .QN(), .SE(dftIn), + .SI(registers_2__ap[12]) + ); + SDFF_X1_LVT \registers_reg[11][12] ( + .CK(n_0_41), .D(registers[12]), .Q(registers_11__ap[12]), .QN(), .SE(dftIn), + .SI(registers_14__ap[12]) + ); + AOI22_X1_LVT i_1_0_927( + .A1(registers_27__ap[12]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[12]), + .ZN(n_1_0_882) + ); + NAND4_X1_LVT i_1_0_926( + .A1(n_1_0_885), .A2(n_1_0_884), .A3(n_1_0_883), .A4(n_1_0_882), .ZN(n_1_0_881) + ); + NOR3_X1_LVT i_1_0_925( + .A1(n_1_0_891), .A2(n_1_0_886), .A3(n_1_0_881), .ZN(n_1_0_880) + ); + NAND4_X1_LVT i_1_0_924( + .A1(n_1_0_898), .A2(n_1_0_897), .A3(n_1_0_896), .A4(n_1_0_880), .ZN(RRs1[12]) + ); + AND2_X1_LVT i_0_0_11( + .A1(n_0_0_16), .A2(WRd[11]), .ZN(registers[11]) + ); + SDFF_X1_LVT \registers_reg[28][11] ( + .CK(n_0_58), .D(registers[11]), .Q(registers_28__ap[11]), .QN(), .SE(dftIn), + .SI(registers_27__ap[12]) + ); + SDFF_X1_LVT \registers_reg[17][11] ( + .CK(n_0_47), .D(registers[11]), .Q(registers_17__ap[11]), .QN(), .SE(dftIn), + .SI(registers_19__ap[12]) + ); + AOI22_X1_LVT i_1_0_923( + .A1(registers_28__ap[11]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[11]), + .ZN(n_1_0_879) + ); + SDFF_X1_LVT \registers_reg[10][11] ( + .CK(n_0_40), .D(registers[11]), .Q(registers_10__ap[11]), .QN(), .SE(dftIn), + .SI(registers_11__ap[12]) + ); + SDFF_X1_LVT \registers_reg[26][11] ( + .CK(n_0_56), .D(registers[11]), .Q(registers_26__ap[11]), .QN(), .SE(dftIn), + .SI(registers_28__ap[11]) + ); + SDFF_X1_LVT \registers_reg[8][11] ( + .CK(n_0_38), .D(registers[11]), .Q(registers_8__ap[11]), .QN(), .SE(dftIn), + .SI(registers_7__ap[12]) + ); + AOI222_X1_LVT i_1_0_922( + .A1(registers_10__ap[11]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[11]), + .C1(registers_8__ap[11]), .C2(n_1_0_1282), .ZN(n_1_0_878) + ); + SDFF_X1_LVT \registers_reg[9][11] ( + .CK(n_0_39), .D(registers[11]), .Q(registers_9__ap[11]), .QN(), .SE(dftIn), + .SI(registers_8__ap[11]) + ); + SDFF_X1_LVT \registers_reg[29][11] ( + .CK(n_0_59), .D(registers[11]), .Q(registers_29__ap[11]), .QN(), .SE(dftIn), + .SI(registers_26__ap[11]) + ); + AOI22_X1_LVT i_1_0_921( + .A1(registers_9__ap[11]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[11]), + .ZN(n_1_0_877) + ); + SDFF_X1_LVT \registers_reg[6][11] ( + .CK(n_0_36), .D(registers[11]), .Q(registers_6__ap[11]), .QN(), .SE(dftIn), + .SI(registers_9__ap[11]) + ); + SDFF_X1_LVT \registers_reg[1][11] ( + .CK(n_0_0), .D(registers[11]), .Q(registers_1__ap[11]), .QN(), .SE(dftIn), + .SI(registers_17__ap[11]) + ); + AOI22_X1_LVT i_1_0_920( + .A1(registers_6__ap[11]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[11]), + .ZN(n_1_0_876) + ); + SDFF_X1_LVT \registers_reg[5][11] ( + .CK(n_0_35), .D(registers[11]), .Q(registers_5__ap[11]), .QN(), .SE(dftIn), + .SI(registers_6__ap[11]) + ); + SDFF_X1_LVT \registers_reg[3][11] ( + .CK(n_0_33), .D(registers[11]), .Q(registers_3__ap[11]), .QN(), .SE(dftIn), + .SI(registers_5__ap[11]) + ); + AOI22_X1_LVT i_1_0_919( + .A1(registers_5__ap[11]), .A2(n_1_0_1273), .B1(n_1_0_1257), .B2(registers_3__ap[11]), + .ZN(n_1_0_875) + ); + SDFF_X1_LVT \registers_reg[16][11] ( + .CK(n_0_46), .D(registers[11]), .Q(registers_16__ap[11]), .QN(), .SE(dftIn), + .SI(registers_10__ap[11]) + ); + SDFF_X1_LVT \registers_reg[31][11] ( + .CK(n_0_61), .D(registers[11]), .Q(registers_31__ap[11]), .QN(), .SE(dftIn), + .SI(registers_3__ap[11]) + ); + AOI22_X1_LVT i_1_0_918( + .A1(registers_16__ap[11]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[11]), + .ZN(n_1_0_874) + ); + SDFF_X1_LVT \registers_reg[15][11] ( + .CK(n_0_45), .D(registers[11]), .Q(registers_15__ap[11]), .QN(), .SE(dftIn), + .SI(registers_16__ap[11]) + ); + SDFF_X1_LVT \registers_reg[23][11] ( + .CK(n_0_53), .D(registers[11]), .Q(registers_23__ap[11]), .QN(), .SE(dftIn), + .SI(registers_1__ap[11]) + ); + AOI22_X1_LVT i_1_0_917( + .A1(registers_15__ap[11]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[11]), + .ZN(n_1_0_873) + ); + NAND4_X1_LVT i_1_0_916( + .A1(n_1_0_876), .A2(n_1_0_875), .A3(n_1_0_874), .A4(n_1_0_873), .ZN(n_1_0_872) + ); + SDFF_X1_LVT \registers_reg[18][11] ( + .CK(n_0_48), .D(registers[11]), .Q(registers_18__ap[11]), .QN(), .SE(dftIn), + .SI(registers_23__ap[11]) + ); + SDFF_X1_LVT \registers_reg[30][11] ( + .CK(n_0_60), .D(registers[11]), .Q(registers_30__ap[11]), .QN(), .SE(dftIn), + .SI(registers_29__ap[11]) + ); + AOI22_X1_LVT i_1_0_915( + .A1(registers_18__ap[11]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[11]), + .ZN(n_1_0_871) + ); + SDFF_X1_LVT \registers_reg[20][11] ( + .CK(n_0_50), .D(registers[11]), .Q(registers_20__ap[11]), .QN(), .SE(dftIn), + .SI(registers_18__ap[11]) + ); + SDFF_X1_LVT \registers_reg[4][11] ( + .CK(n_0_34), .D(registers[11]), .Q(registers_4__ap[11]), .QN(), .SE(dftIn), + .SI(registers_31__ap[11]) + ); + AOI22_X1_LVT i_1_0_914( + .A1(registers_20__ap[11]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[11]), + .ZN(n_1_0_870) + ); + SDFF_X1_LVT \registers_reg[22][11] ( + .CK(n_0_52), .D(registers[11]), .Q(registers_22__ap[11]), .QN(), .SE(dftIn), + .SI(registers_20__ap[11]) + ); + SDFF_X1_LVT \registers_reg[21][11] ( + .CK(n_0_51), .D(registers[11]), .Q(registers_21__ap[11]), .QN(), .SE(dftIn), + .SI(registers_22__ap[11]) + ); + AOI22_X1_LVT i_1_0_913( + .A1(registers_22__ap[11]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[11]), + .ZN(n_1_0_869) + ); + SDFF_X1_LVT \registers_reg[24][11] ( + .CK(n_0_54), .D(registers[11]), .Q(registers_24__ap[11]), .QN(), .SE(dftIn), + .SI(registers_30__ap[11]) + ); + SDFF_X1_LVT \registers_reg[12][11] ( + .CK(n_0_42), .D(registers[11]), .Q(registers_12__ap[11]), .QN(), .SE(dftIn), + .SI(registers_15__ap[11]) + ); + AOI22_X1_LVT i_1_0_912( + .A1(registers_24__ap[11]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[11]), + .ZN(n_1_0_868) + ); + NAND4_X1_LVT i_1_0_911( + .A1(n_1_0_871), .A2(n_1_0_870), .A3(n_1_0_869), .A4(n_1_0_868), .ZN(n_1_0_867) + ); + SDFF_X1_LVT \registers_reg[13][11] ( + .CK(n_0_43), .D(registers[11]), .Q(registers_13__ap[11]), .QN(), .SE(dftIn), + .SI(registers_12__ap[11]) + ); + SDFF_X1_LVT \registers_reg[25][11] ( + .CK(n_0_55), .D(registers[11]), .Q(registers_25__ap[11]), .QN(), .SE(dftIn), + .SI(registers_24__ap[11]) + ); + AOI22_X1_LVT i_1_0_910( + .A1(registers_13__ap[11]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[11]), + .ZN(n_1_0_866) + ); + SDFF_X1_LVT \registers_reg[19][11] ( + .CK(n_0_49), .D(registers[11]), .Q(registers_19__ap[11]), .QN(), .SE(dftIn), + .SI(registers_21__ap[11]) + ); + SDFF_X1_LVT \registers_reg[2][11] ( + .CK(n_0_32), .D(registers[11]), .Q(registers_2__ap[11]), .QN(), .SE(dftIn), + .SI(registers_25__ap[11]) + ); + AOI22_X1_LVT i_1_0_909( + .A1(registers_19__ap[11]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[11]), + .ZN(n_1_0_865) + ); + SDFF_X1_LVT \registers_reg[7][11] ( + .CK(n_0_37), .D(registers[11]), .Q(registers_7__ap[11]), .QN(), .SE(dftIn), + .SI(registers_4__ap[11]) + ); + SDFF_X1_LVT \registers_reg[14][11] ( + .CK(n_0_44), .D(registers[11]), .Q(registers_14__ap[11]), .QN(), .SE(dftIn), + .SI(registers_13__ap[11]) + ); + AOI22_X1_LVT i_1_0_908( + .A1(registers_7__ap[11]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[11]), + .ZN(n_1_0_864) + ); + SDFF_X1_LVT \registers_reg[27][11] ( + .CK(n_0_57), .D(registers[11]), .Q(registers_27__ap[11]), .QN(), .SE(dftIn), + .SI(registers_2__ap[11]) + ); + SDFF_X1_LVT \registers_reg[11][11] ( + .CK(n_0_41), .D(registers[11]), .Q(registers_11__ap[11]), .QN(), .SE(dftIn), + .SI(registers_14__ap[11]) + ); + AOI22_X1_LVT i_1_0_907( + .A1(registers_27__ap[11]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[11]), + .ZN(n_1_0_863) + ); + NAND4_X1_LVT i_1_0_906( + .A1(n_1_0_866), .A2(n_1_0_865), .A3(n_1_0_864), .A4(n_1_0_863), .ZN(n_1_0_862) + ); + NOR3_X1_LVT i_1_0_905( + .A1(n_1_0_872), .A2(n_1_0_867), .A3(n_1_0_862), .ZN(n_1_0_861) + ); + NAND4_X1_LVT i_1_0_904( + .A1(n_1_0_879), .A2(n_1_0_878), .A3(n_1_0_877), .A4(n_1_0_861), .ZN(RRs1[11]) + ); + AND2_X1_LVT i_0_0_10( + .A1(n_0_0_16), .A2(WRd[10]), .ZN(registers[10]) + ); + SDFF_X1_LVT \registers_reg[28][10] ( + .CK(n_0_58), .D(registers[10]), .Q(registers_28__ap[10]), .QN(), .SE(dftIn), + .SI(registers_27__ap[11]) + ); + SDFF_X1_LVT \registers_reg[8][10] ( + .CK(n_0_38), .D(registers[10]), .Q(registers_8__ap[10]), .QN(), .SE(dftIn), + .SI(registers_7__ap[11]) + ); + AOI22_X1_LVT i_1_0_902( + .A1(registers_28__ap[10]), .A2(n_1_0_1283), .B1(n_1_0_1282), .B2(registers_8__ap[10]), + .ZN(n_1_0_859) + ); + SDFF_X1_LVT \registers_reg[31][10] ( + .CK(n_0_61), .D(registers[10]), .Q(registers_31__ap[10]), .QN(), .SE(dftIn), + .SI(registers_8__ap[10]) + ); + SDFF_X1_LVT \registers_reg[7][10] ( + .CK(n_0_37), .D(registers[10]), .Q(registers_7__ap[10]), .QN(), .SE(dftIn), + .SI(registers_31__ap[10]) + ); + AOI22_X1_LVT i_1_0_903( + .A1(registers_31__ap[10]), .A2(n_1_0_1266), .B1(n_1_0_1263), .B2(registers_7__ap[10]), + .ZN(n_1_0_860) + ); + SDFF_X1_LVT \registers_reg[24][10] ( + .CK(n_0_54), .D(registers[10]), .Q(registers_24__ap[10]), .QN(), .SE(dftIn), + .SI(registers_28__ap[10]) + ); + SDFF_X1_LVT \registers_reg[20][10] ( + .CK(n_0_50), .D(registers[10]), .Q(registers_20__ap[10]), .QN(), .SE(dftIn), + .SI(registers_19__ap[11]) + ); + AOI22_X1_LVT i_1_0_901( + .A1(registers_24__ap[10]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[10]), + .ZN(n_1_0_858) + ); + SDFF_X1_LVT \registers_reg[4][10] ( + .CK(n_0_34), .D(registers[10]), .Q(registers_4__ap[10]), .QN(), .SE(dftIn), + .SI(registers_7__ap[10]) + ); + SDFF_X1_LVT \registers_reg[23][10] ( + .CK(n_0_53), .D(registers[10]), .Q(registers_23__ap[10]), .QN(), .SE(dftIn), + .SI(registers_20__ap[10]) + ); + AOI22_X1_LVT i_1_0_900( + .A1(registers_4__ap[10]), .A2(n_1_0_1278), .B1(n_1_0_1264), .B2(registers_23__ap[10]), + .ZN(n_1_0_857) + ); + NAND3_X1_LVT i_1_0_899( + .A1(n_1_0_860), .A2(n_1_0_858), .A3(n_1_0_857), .ZN(n_1_0_856) + ); + SDFF_X1_LVT \registers_reg[27][10] ( + .CK(n_0_57), .D(registers[10]), .Q(registers_27__ap[10]), .QN(), .SE(dftIn), + .SI(registers_24__ap[10]) + ); + SDFF_X1_LVT \registers_reg[29][10] ( + .CK(n_0_59), .D(registers[10]), .Q(registers_29__ap[10]), .QN(), .SE(dftIn), + .SI(registers_27__ap[10]) + ); + AOI221_X1_LVT i_1_0_898( + .A(n_1_0_856), .B1(n_1_0_1279), .B2(registers_27__ap[10]), .C1(registers_29__ap[10]), + .C2(n_1_0_1276), .ZN(n_1_0_855) + ); + SDFF_X1_LVT \registers_reg[10][10] ( + .CK(n_0_40), .D(registers[10]), .Q(registers_10__ap[10]), .QN(), .SE(dftIn), + .SI(registers_11__ap[11]) + ); + SDFF_X1_LVT \registers_reg[30][10] ( + .CK(n_0_60), .D(registers[10]), .Q(registers_30__ap[10]), .QN(), .SE(dftIn), + .SI(registers_29__ap[10]) + ); + SDFF_X1_LVT \registers_reg[25][10] ( + .CK(n_0_55), .D(registers[10]), .Q(registers_25__ap[10]), .QN(), .SE(dftIn), + .SI(registers_30__ap[10]) + ); + AOI222_X1_LVT i_1_0_897( + .A1(registers_10__ap[10]), .A2(n_1_0_1287), .B1(n_1_0_1272), .B2(registers_30__ap[10]), + .C1(n_1_0_1269), .C2(registers_25__ap[10]), .ZN(n_1_0_854) + ); + NAND3_X1_LVT i_1_0_896( + .A1(n_1_0_859), .A2(n_1_0_855), .A3(n_1_0_854), .ZN(n_1_0_853) + ); + SDFF_X1_LVT \registers_reg[21][10] ( + .CK(n_0_51), .D(registers[10]), .Q(registers_21__ap[10]), .QN(), .SE(dftIn), + .SI(registers_23__ap[10]) + ); + SDFF_X1_LVT \registers_reg[13][10] ( + .CK(n_0_43), .D(registers[10]), .Q(registers_13__ap[10]), .QN(), .SE(dftIn), + .SI(registers_10__ap[10]) + ); + AOI221_X1_LVT i_1_0_895( + .A(n_1_0_853), .B1(n_1_0_1259), .B2(registers_21__ap[10]), .C1(registers_13__ap[10]), + .C2(n_1_0_1277), .ZN(n_1_0_852) + ); + SDFF_X1_LVT \registers_reg[18][10] ( + .CK(n_0_48), .D(registers[10]), .Q(registers_18__ap[10]), .QN(), .SE(dftIn), + .SI(registers_21__ap[10]) + ); + SDFF_X1_LVT \registers_reg[26][10] ( + .CK(n_0_56), .D(registers[10]), .Q(registers_26__ap[10]), .QN(), .SE(dftIn), + .SI(registers_25__ap[10]) + ); + AOI22_X1_LVT i_1_0_894( + .A1(registers_18__ap[10]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[10]), + .ZN(n_1_0_851) + ); + SDFF_X1_LVT \registers_reg[17][10] ( + .CK(n_0_47), .D(registers[10]), .Q(registers_17__ap[10]), .QN(), .SE(dftIn), + .SI(registers_18__ap[10]) + ); + SDFF_X1_LVT \registers_reg[12][10] ( + .CK(n_0_42), .D(registers[10]), .Q(registers_12__ap[10]), .QN(), .SE(dftIn), + .SI(registers_13__ap[10]) + ); + AOI22_X1_LVT i_1_0_893( + .A1(registers_17__ap[10]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[10]), + .ZN(n_1_0_850) + ); + SDFF_X1_LVT \registers_reg[15][10] ( + .CK(n_0_45), .D(registers[10]), .Q(registers_15__ap[10]), .QN(), .SE(dftIn), + .SI(registers_12__ap[10]) + ); + SDFF_X1_LVT \registers_reg[5][10] ( + .CK(n_0_35), .D(registers[10]), .Q(registers_5__ap[10]), .QN(), .SE(dftIn), + .SI(registers_4__ap[10]) + ); + AOI22_X1_LVT i_1_0_892( + .A1(registers_15__ap[10]), .A2(n_1_0_1286), .B1(n_1_0_1273), .B2(registers_5__ap[10]), + .ZN(n_1_0_849) + ); + NAND3_X1_LVT i_1_0_891( + .A1(n_1_0_851), .A2(n_1_0_850), .A3(n_1_0_849), .ZN(n_1_0_848) + ); + SDFF_X1_LVT \registers_reg[22][10] ( + .CK(n_0_52), .D(registers[10]), .Q(registers_22__ap[10]), .QN(), .SE(dftIn), + .SI(registers_17__ap[10]) + ); + SDFF_X1_LVT \registers_reg[16][10] ( + .CK(n_0_46), .D(registers[10]), .Q(registers_16__ap[10]), .QN(), .SE(dftIn), + .SI(registers_15__ap[10]) + ); + AOI221_X1_LVT i_1_0_890( + .A(n_1_0_848), .B1(n_1_0_1294), .B2(registers_22__ap[10]), .C1(registers_16__ap[10]), + .C2(n_1_0_1267), .ZN(n_1_0_847) + ); + SDFF_X1_LVT \registers_reg[9][10] ( + .CK(n_0_39), .D(registers[10]), .Q(registers_9__ap[10]), .QN(), .SE(dftIn), + .SI(registers_5__ap[10]) + ); + SDFF_X1_LVT \registers_reg[1][10] ( + .CK(n_0_0), .D(registers[10]), .Q(registers_1__ap[10]), .QN(), .SE(dftIn), + .SI(registers_22__ap[10]) + ); + AOI22_X1_LVT i_1_0_889( + .A1(registers_9__ap[10]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[10]), + .ZN(n_1_0_846) + ); + SDFF_X1_LVT \registers_reg[6][10] ( + .CK(n_0_36), .D(registers[10]), .Q(registers_6__ap[10]), .QN(), .SE(dftIn), + .SI(registers_9__ap[10]) + ); + SDFF_X1_LVT \registers_reg[14][10] ( + .CK(n_0_44), .D(registers[10]), .Q(registers_14__ap[10]), .QN(), .SE(dftIn), + .SI(registers_16__ap[10]) + ); + AOI22_X1_LVT i_1_0_888( + .A1(registers_6__ap[10]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[10]), + .ZN(n_1_0_845) + ); + SDFF_X1_LVT \registers_reg[19][10] ( + .CK(n_0_49), .D(registers[10]), .Q(registers_19__ap[10]), .QN(), .SE(dftIn), + .SI(registers_1__ap[10]) + ); + SDFF_X1_LVT \registers_reg[3][10] ( + .CK(n_0_33), .D(registers[10]), .Q(registers_3__ap[10]), .QN(), .SE(dftIn), + .SI(registers_6__ap[10]) + ); + AOI22_X1_LVT i_1_0_887( + .A1(registers_19__ap[10]), .A2(n_1_0_1295), .B1(n_1_0_1257), .B2(registers_3__ap[10]), + .ZN(n_1_0_844) + ); + NAND3_X1_LVT i_1_0_886( + .A1(n_1_0_846), .A2(n_1_0_845), .A3(n_1_0_844), .ZN(n_1_0_843) + ); + SDFF_X1_LVT \registers_reg[11][10] ( + .CK(n_0_41), .D(registers[10]), .Q(registers_11__ap[10]), .QN(), .SE(dftIn), + .SI(registers_14__ap[10]) + ); + SDFF_X1_LVT \registers_reg[2][10] ( + .CK(n_0_32), .D(registers[10]), .Q(registers_2__ap[10]), .QN(), .SE(dftIn), + .SI(registers_26__ap[10]) + ); + AOI221_X1_LVT i_1_0_885( + .A(n_1_0_843), .B1(n_1_0_1270), .B2(registers_11__ap[10]), .C1(registers_2__ap[10]), + .C2(n_1_0_1268), .ZN(n_1_0_842) + ); + NAND3_X1_LVT i_1_0_884( + .A1(n_1_0_852), .A2(n_1_0_847), .A3(n_1_0_842), .ZN(RRs1[10]) + ); + AND2_X1_LVT i_0_0_9( + .A1(n_0_0_16), .A2(WRd[9]), .ZN(registers[9]) + ); + SDFF_X1_LVT \registers_reg[13][9] ( + .CK(n_0_43), .D(registers[9]), .Q(registers_13__ap[9]), .QN(), .SE(dftIn), + .SI(registers_11__ap[10]) + ); + SDFF_X1_LVT \registers_reg[21][9] ( + .CK(n_0_51), .D(registers[9]), .Q(registers_21__ap[9]), .QN(), .SE(dftIn), + .SI(registers_19__ap[10]) + ); + AOI22_X1_LVT i_1_0_880( + .A1(registers_13__ap[9]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[9]), + .ZN(n_1_0_838) + ); + SDFF_X1_LVT \registers_reg[29][9] ( + .CK(n_0_59), .D(registers[9]), .Q(registers_29__ap[9]), .QN(), .SE(dftIn), + .SI(registers_2__ap[10]) + ); + SDFF_X1_LVT \registers_reg[23][9] ( + .CK(n_0_53), .D(registers[9]), .Q(registers_23__ap[9]), .QN(), .SE(dftIn), + .SI(registers_21__ap[9]) + ); + AOI22_X1_LVT i_1_0_883( + .A1(registers_29__ap[9]), .A2(n_1_0_1276), .B1(n_1_0_1264), .B2(registers_23__ap[9]), + .ZN(n_1_0_841) + ); + SDFF_X1_LVT \registers_reg[24][9] ( + .CK(n_0_54), .D(registers[9]), .Q(registers_24__ap[9]), .QN(), .SE(dftIn), + .SI(registers_29__ap[9]) + ); + SDFF_X1_LVT \registers_reg[20][9] ( + .CK(n_0_50), .D(registers[9]), .Q(registers_20__ap[9]), .QN(), .SE(dftIn), + .SI(registers_23__ap[9]) + ); + AOI22_X1_LVT i_1_0_879( + .A1(registers_24__ap[9]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[9]), + .ZN(n_1_0_837) + ); + SDFF_X1_LVT \registers_reg[7][9] ( + .CK(n_0_37), .D(registers[9]), .Q(registers_7__ap[9]), .QN(), .SE(dftIn), + .SI(registers_3__ap[10]) + ); + SDFF_X1_LVT \registers_reg[3][9] ( + .CK(n_0_33), .D(registers[9]), .Q(registers_3__ap[9]), .QN(), .SE(dftIn), + .SI(registers_7__ap[9]) + ); + AOI22_X1_LVT i_1_0_882( + .A1(registers_7__ap[9]), .A2(n_1_0_1263), .B1(n_1_0_1257), .B2(registers_3__ap[9]), + .ZN(n_1_0_840) + ); + INV_X1_LVT i_1_0_881( + .A(n_1_0_840), .ZN(n_1_0_839) + ); + SDFF_X1_LVT \registers_reg[31][9] ( + .CK(n_0_61), .D(registers[9]), .Q(registers_31__ap[9]), .QN(), .SE(dftIn), + .SI(registers_3__ap[9]) + ); + SDFF_X1_LVT \registers_reg[4][9] ( + .CK(n_0_34), .D(registers[9]), .Q(registers_4__ap[9]), .QN(), .SE(dftIn), + .SI(registers_31__ap[9]) + ); + AOI221_X1_LVT i_1_0_878( + .A(n_1_0_839), .B1(n_1_0_1266), .B2(registers_31__ap[9]), .C1(registers_4__ap[9]), + .C2(n_1_0_1278), .ZN(n_1_0_836) + ); + SDFF_X1_LVT \registers_reg[10][9] ( + .CK(n_0_40), .D(registers[9]), .Q(registers_10__ap[9]), .QN(), .SE(dftIn), + .SI(registers_13__ap[9]) + ); + SDFF_X1_LVT \registers_reg[26][9] ( + .CK(n_0_56), .D(registers[9]), .Q(registers_26__ap[9]), .QN(), .SE(dftIn), + .SI(registers_24__ap[9]) + ); + SDFF_X1_LVT \registers_reg[25][9] ( + .CK(n_0_55), .D(registers[9]), .Q(registers_25__ap[9]), .QN(), .SE(dftIn), + .SI(registers_26__ap[9]) + ); + AOI222_X1_LVT i_1_0_877( + .A1(registers_10__ap[9]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[9]), + .C1(registers_25__ap[9]), .C2(n_1_0_1269), .ZN(n_1_0_835) + ); + NAND4_X1_LVT i_1_0_876( + .A1(n_1_0_841), .A2(n_1_0_837), .A3(n_1_0_836), .A4(n_1_0_835), .ZN(n_1_0_834) + ); + SDFF_X1_LVT \registers_reg[8][9] ( + .CK(n_0_38), .D(registers[9]), .Q(registers_8__ap[9]), .QN(), .SE(dftIn), + .SI(registers_4__ap[9]) + ); + SDFF_X1_LVT \registers_reg[28][9] ( + .CK(n_0_58), .D(registers[9]), .Q(registers_28__ap[9]), .QN(), .SE(dftIn), + .SI(registers_25__ap[9]) + ); + AOI221_X1_LVT i_1_0_875( + .A(n_1_0_834), .B1(n_1_0_1282), .B2(registers_8__ap[9]), .C1(registers_28__ap[9]), + .C2(n_1_0_1283), .ZN(n_1_0_833) + ); + SDFF_X1_LVT \registers_reg[18][9] ( + .CK(n_0_48), .D(registers[9]), .Q(registers_18__ap[9]), .QN(), .SE(dftIn), + .SI(registers_20__ap[9]) + ); + SDFF_X1_LVT \registers_reg[30][9] ( + .CK(n_0_60), .D(registers[9]), .Q(registers_30__ap[9]), .QN(), .SE(dftIn), + .SI(registers_28__ap[9]) + ); + AOI22_X1_LVT i_1_0_874( + .A1(registers_18__ap[9]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[9]), + .ZN(n_1_0_832) + ); + SDFF_X1_LVT \registers_reg[17][9] ( + .CK(n_0_47), .D(registers[9]), .Q(registers_17__ap[9]), .QN(), .SE(dftIn), + .SI(registers_18__ap[9]) + ); + SDFF_X1_LVT \registers_reg[12][9] ( + .CK(n_0_42), .D(registers[9]), .Q(registers_12__ap[9]), .QN(), .SE(dftIn), + .SI(registers_10__ap[9]) + ); + AOI22_X1_LVT i_1_0_873( + .A1(registers_17__ap[9]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[9]), + .ZN(n_1_0_831) + ); + SDFF_X1_LVT \registers_reg[15][9] ( + .CK(n_0_45), .D(registers[9]), .Q(registers_15__ap[9]), .QN(), .SE(dftIn), + .SI(registers_12__ap[9]) + ); + SDFF_X1_LVT \registers_reg[5][9] ( + .CK(n_0_35), .D(registers[9]), .Q(registers_5__ap[9]), .QN(), .SE(dftIn), + .SI(registers_8__ap[9]) + ); + AOI22_X1_LVT i_1_0_872( + .A1(registers_15__ap[9]), .A2(n_1_0_1286), .B1(n_1_0_1273), .B2(registers_5__ap[9]), + .ZN(n_1_0_830) + ); + NAND3_X1_LVT i_1_0_871( + .A1(n_1_0_832), .A2(n_1_0_831), .A3(n_1_0_830), .ZN(n_1_0_829) + ); + SDFF_X1_LVT \registers_reg[22][9] ( + .CK(n_0_52), .D(registers[9]), .Q(registers_22__ap[9]), .QN(), .SE(dftIn), + .SI(registers_17__ap[9]) + ); + SDFF_X1_LVT \registers_reg[16][9] ( + .CK(n_0_46), .D(registers[9]), .Q(registers_16__ap[9]), .QN(), .SE(dftIn), + .SI(registers_15__ap[9]) + ); + AOI221_X1_LVT i_1_0_870( + .A(n_1_0_829), .B1(n_1_0_1294), .B2(registers_22__ap[9]), .C1(registers_16__ap[9]), + .C2(n_1_0_1267), .ZN(n_1_0_828) + ); + SDFF_X1_LVT \registers_reg[9][9] ( + .CK(n_0_39), .D(registers[9]), .Q(registers_9__ap[9]), .QN(), .SE(dftIn), + .SI(registers_5__ap[9]) + ); + SDFF_X1_LVT \registers_reg[1][9] ( + .CK(n_0_0), .D(registers[9]), .Q(registers_1__ap[9]), .QN(), .SE(dftIn), + .SI(registers_22__ap[9]) + ); + AOI22_X1_LVT i_1_0_869( + .A1(registers_9__ap[9]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[9]), + .ZN(n_1_0_827) + ); + SDFF_X1_LVT \registers_reg[6][9] ( + .CK(n_0_36), .D(registers[9]), .Q(registers_6__ap[9]), .QN(), .SE(dftIn), + .SI(registers_9__ap[9]) + ); + SDFF_X1_LVT \registers_reg[14][9] ( + .CK(n_0_44), .D(registers[9]), .Q(registers_14__ap[9]), .QN(), .SE(dftIn), + .SI(registers_16__ap[9]) + ); + AOI22_X1_LVT i_1_0_868( + .A1(registers_6__ap[9]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[9]), + .ZN(n_1_0_826) + ); + SDFF_X1_LVT \registers_reg[19][9] ( + .CK(n_0_49), .D(registers[9]), .Q(registers_19__ap[9]), .QN(), .SE(dftIn), + .SI(registers_1__ap[9]) + ); + SDFF_X1_LVT \registers_reg[2][9] ( + .CK(n_0_32), .D(registers[9]), .Q(registers_2__ap[9]), .QN(), .SE(dftIn), + .SI(registers_30__ap[9]) + ); + AOI22_X1_LVT i_1_0_867( + .A1(registers_19__ap[9]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[9]), + .ZN(n_1_0_825) + ); + NAND3_X1_LVT i_1_0_866( + .A1(n_1_0_827), .A2(n_1_0_826), .A3(n_1_0_825), .ZN(n_1_0_824) + ); + SDFF_X1_LVT \registers_reg[11][9] ( + .CK(n_0_41), .D(registers[9]), .Q(registers_11__ap[9]), .QN(), .SE(dftIn), + .SI(registers_14__ap[9]) + ); + SDFF_X1_LVT \registers_reg[27][9] ( + .CK(n_0_57), .D(registers[9]), .Q(registers_27__ap[9]), .QN(), .SE(dftIn), + .SI(registers_2__ap[9]) + ); + AOI221_X1_LVT i_1_0_865( + .A(n_1_0_824), .B1(n_1_0_1270), .B2(registers_11__ap[9]), .C1(registers_27__ap[9]), + .C2(n_1_0_1279), .ZN(n_1_0_823) + ); + NAND4_X1_LVT i_1_0_864( + .A1(n_1_0_838), .A2(n_1_0_833), .A3(n_1_0_828), .A4(n_1_0_823), .ZN(RRs1[9]) + ); + AND2_X1_LVT i_0_0_8( + .A1(n_0_0_16), .A2(WRd[8]), .ZN(registers[8]) + ); + SDFF_X1_LVT \registers_reg[13][8] ( + .CK(n_0_43), .D(registers[8]), .Q(registers_13__ap[8]), .QN(), .SE(dftIn), + .SI(registers_11__ap[9]) + ); + SDFF_X1_LVT \registers_reg[21][8] ( + .CK(n_0_51), .D(registers[8]), .Q(registers_21__ap[8]), .QN(), .SE(dftIn), + .SI(registers_19__ap[9]) + ); + AOI22_X1_LVT i_1_0_860( + .A1(registers_13__ap[8]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[8]), + .ZN(n_1_0_819) + ); + SDFF_X1_LVT \registers_reg[29][8] ( + .CK(n_0_59), .D(registers[8]), .Q(registers_29__ap[8]), .QN(), .SE(dftIn), + .SI(registers_27__ap[9]) + ); + SDFF_X1_LVT \registers_reg[23][8] ( + .CK(n_0_53), .D(registers[8]), .Q(registers_23__ap[8]), .QN(), .SE(dftIn), + .SI(registers_21__ap[8]) + ); + AOI22_X1_LVT i_1_0_863( + .A1(registers_29__ap[8]), .A2(n_1_0_1276), .B1(n_1_0_1264), .B2(registers_23__ap[8]), + .ZN(n_1_0_822) + ); + SDFF_X1_LVT \registers_reg[24][8] ( + .CK(n_0_54), .D(registers[8]), .Q(registers_24__ap[8]), .QN(), .SE(dftIn), + .SI(registers_29__ap[8]) + ); + SDFF_X1_LVT \registers_reg[20][8] ( + .CK(n_0_50), .D(registers[8]), .Q(registers_20__ap[8]), .QN(), .SE(dftIn), + .SI(registers_23__ap[8]) + ); + AOI22_X1_LVT i_1_0_859( + .A1(registers_24__ap[8]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[8]), + .ZN(n_1_0_818) + ); + SDFF_X1_LVT \registers_reg[7][8] ( + .CK(n_0_37), .D(registers[8]), .Q(registers_7__ap[8]), .QN(), .SE(dftIn), + .SI(registers_6__ap[9]) + ); + SDFF_X1_LVT \registers_reg[3][8] ( + .CK(n_0_33), .D(registers[8]), .Q(registers_3__ap[8]), .QN(), .SE(dftIn), + .SI(registers_7__ap[8]) + ); + AOI22_X1_LVT i_1_0_862( + .A1(registers_7__ap[8]), .A2(n_1_0_1263), .B1(n_1_0_1257), .B2(registers_3__ap[8]), + .ZN(n_1_0_821) + ); + INV_X1_LVT i_1_0_861( + .A(n_1_0_821), .ZN(n_1_0_820) + ); + SDFF_X1_LVT \registers_reg[31][8] ( + .CK(n_0_61), .D(registers[8]), .Q(registers_31__ap[8]), .QN(), .SE(dftIn), + .SI(registers_3__ap[8]) + ); + SDFF_X1_LVT \registers_reg[4][8] ( + .CK(n_0_34), .D(registers[8]), .Q(registers_4__ap[8]), .QN(), .SE(dftIn), + .SI(registers_31__ap[8]) + ); + AOI221_X1_LVT i_1_0_858( + .A(n_1_0_820), .B1(n_1_0_1266), .B2(registers_31__ap[8]), .C1(registers_4__ap[8]), + .C2(n_1_0_1278), .ZN(n_1_0_817) + ); + SDFF_X1_LVT \registers_reg[10][8] ( + .CK(n_0_40), .D(registers[8]), .Q(registers_10__ap[8]), .QN(), .SE(dftIn), + .SI(registers_13__ap[8]) + ); + SDFF_X1_LVT \registers_reg[26][8] ( + .CK(n_0_56), .D(registers[8]), .Q(registers_26__ap[8]), .QN(), .SE(dftIn), + .SI(registers_24__ap[8]) + ); + SDFF_X1_LVT \registers_reg[25][8] ( + .CK(n_0_55), .D(registers[8]), .Q(registers_25__ap[8]), .QN(), .SE(dftIn), + .SI(registers_26__ap[8]) + ); + AOI222_X1_LVT i_1_0_857( + .A1(registers_10__ap[8]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[8]), + .C1(registers_25__ap[8]), .C2(n_1_0_1269), .ZN(n_1_0_816) + ); + NAND4_X1_LVT i_1_0_856( + .A1(n_1_0_822), .A2(n_1_0_818), .A3(n_1_0_817), .A4(n_1_0_816), .ZN(n_1_0_815) + ); + SDFF_X1_LVT \registers_reg[8][8] ( + .CK(n_0_38), .D(registers[8]), .Q(registers_8__ap[8]), .QN(), .SE(dftIn), + .SI(registers_4__ap[8]) + ); + SDFF_X1_LVT \registers_reg[28][8] ( + .CK(n_0_58), .D(registers[8]), .Q(registers_28__ap[8]), .QN(), .SE(dftIn), + .SI(registers_25__ap[8]) + ); + AOI221_X1_LVT i_1_0_855( + .A(n_1_0_815), .B1(n_1_0_1282), .B2(registers_8__ap[8]), .C1(registers_28__ap[8]), + .C2(n_1_0_1283), .ZN(n_1_0_814) + ); + SDFF_X1_LVT \registers_reg[18][8] ( + .CK(n_0_48), .D(registers[8]), .Q(registers_18__ap[8]), .QN(), .SE(dftIn), + .SI(registers_20__ap[8]) + ); + SDFF_X1_LVT \registers_reg[30][8] ( + .CK(n_0_60), .D(registers[8]), .Q(registers_30__ap[8]), .QN(), .SE(dftIn), + .SI(registers_28__ap[8]) + ); + AOI22_X1_LVT i_1_0_854( + .A1(registers_18__ap[8]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[8]), + .ZN(n_1_0_813) + ); + SDFF_X1_LVT \registers_reg[17][8] ( + .CK(n_0_47), .D(registers[8]), .Q(registers_17__ap[8]), .QN(), .SE(dftIn), + .SI(registers_18__ap[8]) + ); + SDFF_X1_LVT \registers_reg[12][8] ( + .CK(n_0_42), .D(registers[8]), .Q(registers_12__ap[8]), .QN(), .SE(dftIn), + .SI(registers_10__ap[8]) + ); + AOI22_X1_LVT i_1_0_853( + .A1(registers_17__ap[8]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[8]), + .ZN(n_1_0_812) + ); + SDFF_X1_LVT \registers_reg[15][8] ( + .CK(n_0_45), .D(registers[8]), .Q(registers_15__ap[8]), .QN(), .SE(dftIn), + .SI(registers_12__ap[8]) + ); + SDFF_X1_LVT \registers_reg[5][8] ( + .CK(n_0_35), .D(registers[8]), .Q(registers_5__ap[8]), .QN(), .SE(dftIn), + .SI(registers_8__ap[8]) + ); + AOI22_X1_LVT i_1_0_852( + .A1(registers_15__ap[8]), .A2(n_1_0_1286), .B1(n_1_0_1273), .B2(registers_5__ap[8]), + .ZN(n_1_0_811) + ); + NAND3_X1_LVT i_1_0_851( + .A1(n_1_0_813), .A2(n_1_0_812), .A3(n_1_0_811), .ZN(n_1_0_810) + ); + SDFF_X1_LVT \registers_reg[22][8] ( + .CK(n_0_52), .D(registers[8]), .Q(registers_22__ap[8]), .QN(), .SE(dftIn), + .SI(registers_17__ap[8]) + ); + SDFF_X1_LVT \registers_reg[16][8] ( + .CK(n_0_46), .D(registers[8]), .Q(registers_16__ap[8]), .QN(), .SE(dftIn), + .SI(registers_15__ap[8]) + ); + AOI221_X1_LVT i_1_0_850( + .A(n_1_0_810), .B1(n_1_0_1294), .B2(registers_22__ap[8]), .C1(registers_16__ap[8]), + .C2(n_1_0_1267), .ZN(n_1_0_809) + ); + SDFF_X1_LVT \registers_reg[9][8] ( + .CK(n_0_39), .D(registers[8]), .Q(registers_9__ap[8]), .QN(), .SE(dftIn), + .SI(registers_5__ap[8]) + ); + SDFF_X1_LVT \registers_reg[1][8] ( + .CK(n_0_0), .D(registers[8]), .Q(registers_1__ap[8]), .QN(), .SE(dftIn), + .SI(registers_22__ap[8]) + ); + AOI22_X1_LVT i_1_0_849( + .A1(registers_9__ap[8]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[8]), + .ZN(n_1_0_808) + ); + SDFF_X1_LVT \registers_reg[6][8] ( + .CK(n_0_36), .D(registers[8]), .Q(registers_6__ap[8]), .QN(), .SE(dftIn), + .SI(registers_9__ap[8]) + ); + SDFF_X1_LVT \registers_reg[14][8] ( + .CK(n_0_44), .D(registers[8]), .Q(registers_14__ap[8]), .QN(), .SE(dftIn), + .SI(registers_16__ap[8]) + ); + AOI22_X1_LVT i_1_0_848( + .A1(registers_6__ap[8]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[8]), + .ZN(n_1_0_807) + ); + SDFF_X1_LVT \registers_reg[19][8] ( + .CK(n_0_49), .D(registers[8]), .Q(registers_19__ap[8]), .QN(), .SE(dftIn), + .SI(registers_1__ap[8]) + ); + SDFF_X1_LVT \registers_reg[2][8] ( + .CK(n_0_32), .D(registers[8]), .Q(registers_2__ap[8]), .QN(), .SE(dftIn), + .SI(registers_30__ap[8]) + ); + AOI22_X1_LVT i_1_0_847( + .A1(registers_19__ap[8]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[8]), + .ZN(n_1_0_806) + ); + NAND3_X1_LVT i_1_0_846( + .A1(n_1_0_808), .A2(n_1_0_807), .A3(n_1_0_806), .ZN(n_1_0_805) + ); + SDFF_X1_LVT \registers_reg[11][8] ( + .CK(n_0_41), .D(registers[8]), .Q(registers_11__ap[8]), .QN(), .SE(dftIn), + .SI(registers_14__ap[8]) + ); + SDFF_X1_LVT \registers_reg[27][8] ( + .CK(n_0_57), .D(registers[8]), .Q(registers_27__ap[8]), .QN(), .SE(dftIn), + .SI(registers_2__ap[8]) + ); + AOI221_X1_LVT i_1_0_845( + .A(n_1_0_805), .B1(n_1_0_1270), .B2(registers_11__ap[8]), .C1(registers_27__ap[8]), + .C2(n_1_0_1279), .ZN(n_1_0_804) + ); + NAND4_X1_LVT i_1_0_844( + .A1(n_1_0_819), .A2(n_1_0_814), .A3(n_1_0_809), .A4(n_1_0_804), .ZN(RRs1[8]) + ); + AND2_X1_LVT i_0_0_7( + .A1(n_0_0_16), .A2(WRd[7]), .ZN(registers[7]) + ); + SDFF_X1_LVT \registers_reg[13][7] ( + .CK(n_0_43), .D(registers[7]), .Q(registers_13__ap[7]), .QN(), .SE(dftIn), + .SI(registers_11__ap[8]) + ); + SDFF_X1_LVT \registers_reg[21][7] ( + .CK(n_0_51), .D(registers[7]), .Q(registers_21__ap[7]), .QN(), .SE(dftIn), + .SI(registers_19__ap[8]) + ); + AOI22_X1_LVT i_1_0_843( + .A1(registers_13__ap[7]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[7]), + .ZN(n_1_0_803) + ); + SDFF_X1_LVT \registers_reg[18][7] ( + .CK(n_0_48), .D(registers[7]), .Q(registers_18__ap[7]), .QN(), .SE(dftIn), + .SI(registers_21__ap[7]) + ); + SDFF_X1_LVT \registers_reg[10][7] ( + .CK(n_0_40), .D(registers[7]), .Q(registers_10__ap[7]), .QN(), .SE(dftIn), + .SI(registers_13__ap[7]) + ); + SDFF_X1_LVT \registers_reg[25][7] ( + .CK(n_0_55), .D(registers[7]), .Q(registers_25__ap[7]), .QN(), .SE(dftIn), + .SI(registers_27__ap[8]) + ); + AOI222_X1_LVT i_1_0_842( + .A1(registers_18__ap[7]), .A2(n_1_0_1297), .B1(n_1_0_1287), .B2(registers_10__ap[7]), + .C1(registers_25__ap[7]), .C2(n_1_0_1269), .ZN(n_1_0_802) + ); + SDFF_X1_LVT \registers_reg[28][7] ( + .CK(n_0_58), .D(registers[7]), .Q(registers_28__ap[7]), .QN(), .SE(dftIn), + .SI(registers_25__ap[7]) + ); + SDFF_X1_LVT \registers_reg[8][7] ( + .CK(n_0_38), .D(registers[7]), .Q(registers_8__ap[7]), .QN(), .SE(dftIn), + .SI(registers_6__ap[8]) + ); + AOI22_X1_LVT i_1_0_841( + .A1(registers_28__ap[7]), .A2(n_1_0_1283), .B1(n_1_0_1282), .B2(registers_8__ap[7]), + .ZN(n_1_0_801) + ); + SDFF_X1_LVT \registers_reg[24][7] ( + .CK(n_0_54), .D(registers[7]), .Q(registers_24__ap[7]), .QN(), .SE(dftIn), + .SI(registers_28__ap[7]) + ); + SDFF_X1_LVT \registers_reg[20][7] ( + .CK(n_0_50), .D(registers[7]), .Q(registers_20__ap[7]), .QN(), .SE(dftIn), + .SI(registers_18__ap[7]) + ); + AOI22_X1_LVT i_1_0_840( + .A1(registers_24__ap[7]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[7]), + .ZN(n_1_0_800) + ); + SDFF_X1_LVT \registers_reg[31][7] ( + .CK(n_0_61), .D(registers[7]), .Q(registers_31__ap[7]), .QN(), .SE(dftIn), + .SI(registers_8__ap[7]) + ); + SDFF_X1_LVT \registers_reg[7][7] ( + .CK(n_0_37), .D(registers[7]), .Q(registers_7__ap[7]), .QN(), .SE(dftIn), + .SI(registers_31__ap[7]) + ); + AOI22_X1_LVT i_1_0_839( + .A1(registers_31__ap[7]), .A2(n_1_0_1266), .B1(n_1_0_1263), .B2(registers_7__ap[7]), + .ZN(n_1_0_799) + ); + SDFF_X1_LVT \registers_reg[17][7] ( + .CK(n_0_47), .D(registers[7]), .Q(registers_17__ap[7]), .QN(), .SE(dftIn), + .SI(registers_20__ap[7]) + ); + SDFF_X1_LVT \registers_reg[11][7] ( + .CK(n_0_41), .D(registers[7]), .Q(registers_11__ap[7]), .QN(), .SE(dftIn), + .SI(registers_10__ap[7]) + ); + AOI22_X1_LVT i_1_0_838( + .A1(registers_17__ap[7]), .A2(n_1_0_1271), .B1(n_1_0_1270), .B2(registers_11__ap[7]), + .ZN(n_1_0_798) + ); + SDFF_X1_LVT \registers_reg[27][7] ( + .CK(n_0_57), .D(registers[7]), .Q(registers_27__ap[7]), .QN(), .SE(dftIn), + .SI(registers_24__ap[7]) + ); + SDFF_X1_LVT \registers_reg[29][7] ( + .CK(n_0_59), .D(registers[7]), .Q(registers_29__ap[7]), .QN(), .SE(dftIn), + .SI(registers_27__ap[7]) + ); + AOI22_X1_LVT i_1_0_837( + .A1(registers_27__ap[7]), .A2(n_1_0_1279), .B1(n_1_0_1276), .B2(registers_29__ap[7]), + .ZN(n_1_0_797) + ); + NAND4_X1_LVT i_1_0_836( + .A1(n_1_0_800), .A2(n_1_0_799), .A3(n_1_0_798), .A4(n_1_0_797), .ZN(n_1_0_796) + ); + SDFF_X1_LVT \registers_reg[26][7] ( + .CK(n_0_56), .D(registers[7]), .Q(registers_26__ap[7]), .QN(), .SE(dftIn), + .SI(registers_29__ap[7]) + ); + SDFF_X1_LVT \registers_reg[30][7] ( + .CK(n_0_60), .D(registers[7]), .Q(registers_30__ap[7]), .QN(), .SE(dftIn), + .SI(registers_26__ap[7]) + ); + AOI22_X1_LVT i_1_0_835( + .A1(registers_26__ap[7]), .A2(n_1_0_1285), .B1(n_1_0_1272), .B2(registers_30__ap[7]), + .ZN(n_1_0_795) + ); + SDFF_X1_LVT \registers_reg[4][7] ( + .CK(n_0_34), .D(registers[7]), .Q(registers_4__ap[7]), .QN(), .SE(dftIn), + .SI(registers_7__ap[7]) + ); + SDFF_X1_LVT \registers_reg[12][7] ( + .CK(n_0_42), .D(registers[7]), .Q(registers_12__ap[7]), .QN(), .SE(dftIn), + .SI(registers_11__ap[7]) + ); + AOI22_X1_LVT i_1_0_834( + .A1(registers_4__ap[7]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[7]), + .ZN(n_1_0_794) + ); + SDFF_X1_LVT \registers_reg[15][7] ( + .CK(n_0_45), .D(registers[7]), .Q(registers_15__ap[7]), .QN(), .SE(dftIn), + .SI(registers_12__ap[7]) + ); + SDFF_X1_LVT \registers_reg[16][7] ( + .CK(n_0_46), .D(registers[7]), .Q(registers_16__ap[7]), .QN(), .SE(dftIn), + .SI(registers_15__ap[7]) + ); + AOI22_X1_LVT i_1_0_833( + .A1(registers_15__ap[7]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[7]), + .ZN(n_1_0_793) + ); + SDFF_X1_LVT \registers_reg[22][7] ( + .CK(n_0_52), .D(registers[7]), .Q(registers_22__ap[7]), .QN(), .SE(dftIn), + .SI(registers_17__ap[7]) + ); + SDFF_X1_LVT \registers_reg[5][7] ( + .CK(n_0_35), .D(registers[7]), .Q(registers_5__ap[7]), .QN(), .SE(dftIn), + .SI(registers_4__ap[7]) + ); + AOI22_X1_LVT i_1_0_832( + .A1(registers_22__ap[7]), .A2(n_1_0_1294), .B1(n_1_0_1273), .B2(registers_5__ap[7]), + .ZN(n_1_0_792) + ); + NAND4_X1_LVT i_1_0_831( + .A1(n_1_0_795), .A2(n_1_0_794), .A3(n_1_0_793), .A4(n_1_0_792), .ZN(n_1_0_791) + ); + SDFF_X1_LVT \registers_reg[19][7] ( + .CK(n_0_49), .D(registers[7]), .Q(registers_19__ap[7]), .QN(), .SE(dftIn), + .SI(registers_22__ap[7]) + ); + SDFF_X1_LVT \registers_reg[3][7] ( + .CK(n_0_33), .D(registers[7]), .Q(registers_3__ap[7]), .QN(), .SE(dftIn), + .SI(registers_5__ap[7]) + ); + AOI22_X1_LVT i_1_0_830( + .A1(registers_19__ap[7]), .A2(n_1_0_1295), .B1(n_1_0_1257), .B2(registers_3__ap[7]), + .ZN(n_1_0_790) + ); + SDFF_X1_LVT \registers_reg[9][7] ( + .CK(n_0_39), .D(registers[7]), .Q(registers_9__ap[7]), .QN(), .SE(dftIn), + .SI(registers_3__ap[7]) + ); + SDFF_X1_LVT \registers_reg[1][7] ( + .CK(n_0_0), .D(registers[7]), .Q(registers_1__ap[7]), .QN(), .SE(dftIn), + .SI(registers_19__ap[7]) + ); + AOI22_X1_LVT i_1_0_829( + .A1(registers_9__ap[7]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[7]), + .ZN(n_1_0_789) + ); + SDFF_X1_LVT \registers_reg[6][7] ( + .CK(n_0_36), .D(registers[7]), .Q(registers_6__ap[7]), .QN(), .SE(dftIn), + .SI(registers_9__ap[7]) + ); + SDFF_X1_LVT \registers_reg[14][7] ( + .CK(n_0_44), .D(registers[7]), .Q(registers_14__ap[7]), .QN(), .SE(dftIn), + .SI(registers_16__ap[7]) + ); + AOI22_X1_LVT i_1_0_828( + .A1(registers_6__ap[7]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[7]), + .ZN(n_1_0_788) + ); + SDFF_X1_LVT \registers_reg[2][7] ( + .CK(n_0_32), .D(registers[7]), .Q(registers_2__ap[7]), .QN(), .SE(dftIn), + .SI(registers_30__ap[7]) + ); + SDFF_X1_LVT \registers_reg[23][7] ( + .CK(n_0_53), .D(registers[7]), .Q(registers_23__ap[7]), .QN(), .SE(dftIn), + .SI(registers_1__ap[7]) + ); + AOI22_X1_LVT i_1_0_827( + .A1(registers_2__ap[7]), .A2(n_1_0_1268), .B1(n_1_0_1264), .B2(registers_23__ap[7]), + .ZN(n_1_0_787) + ); + NAND4_X1_LVT i_1_0_826( + .A1(n_1_0_790), .A2(n_1_0_789), .A3(n_1_0_788), .A4(n_1_0_787), .ZN(n_1_0_786) + ); + NOR3_X1_LVT i_1_0_825( + .A1(n_1_0_796), .A2(n_1_0_791), .A3(n_1_0_786), .ZN(n_1_0_785) + ); + NAND4_X1_LVT i_1_0_824( + .A1(n_1_0_803), .A2(n_1_0_802), .A3(n_1_0_801), .A4(n_1_0_785), .ZN(RRs1[7]) + ); + AND2_X1_LVT i_0_0_6( + .A1(n_0_0_16), .A2(WRd[6]), .ZN(registers[6]) + ); + SDFF_X1_LVT \registers_reg[28][6] ( + .CK(n_0_58), .D(registers[6]), .Q(registers_28__ap[6]), .QN(), .SE(dftIn), + .SI(registers_2__ap[7]) + ); + SDFF_X1_LVT \registers_reg[17][6] ( + .CK(n_0_47), .D(registers[6]), .Q(registers_17__ap[6]), .QN(), .SE(dftIn), + .SI(registers_23__ap[7]) + ); + AOI22_X1_LVT i_1_0_823( + .A1(registers_28__ap[6]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[6]), + .ZN(n_1_0_784) + ); + SDFF_X1_LVT \registers_reg[18][6] ( + .CK(n_0_48), .D(registers[6]), .Q(registers_18__ap[6]), .QN(), .SE(dftIn), + .SI(registers_17__ap[6]) + ); + SDFF_X1_LVT \registers_reg[10][6] ( + .CK(n_0_40), .D(registers[6]), .Q(registers_10__ap[6]), .QN(), .SE(dftIn), + .SI(registers_14__ap[7]) + ); + SDFF_X1_LVT \registers_reg[8][6] ( + .CK(n_0_38), .D(registers[6]), .Q(registers_8__ap[6]), .QN(), .SE(dftIn), + .SI(registers_6__ap[7]) + ); + AOI222_X1_LVT i_1_0_822( + .A1(registers_18__ap[6]), .A2(n_1_0_1297), .B1(n_1_0_1287), .B2(registers_10__ap[6]), + .C1(registers_8__ap[6]), .C2(n_1_0_1282), .ZN(n_1_0_783) + ); + SDFF_X1_LVT \registers_reg[9][6] ( + .CK(n_0_39), .D(registers[6]), .Q(registers_9__ap[6]), .QN(), .SE(dftIn), + .SI(registers_8__ap[6]) + ); + SDFF_X1_LVT \registers_reg[29][6] ( + .CK(n_0_59), .D(registers[6]), .Q(registers_29__ap[6]), .QN(), .SE(dftIn), + .SI(registers_28__ap[6]) + ); + AOI22_X1_LVT i_1_0_821( + .A1(registers_9__ap[6]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[6]), + .ZN(n_1_0_782) + ); + SDFF_X1_LVT \registers_reg[6][6] ( + .CK(n_0_36), .D(registers[6]), .Q(registers_6__ap[6]), .QN(), .SE(dftIn), + .SI(registers_9__ap[6]) + ); + SDFF_X1_LVT \registers_reg[1][6] ( + .CK(n_0_0), .D(registers[6]), .Q(registers_1__ap[6]), .QN(), .SE(dftIn), + .SI(registers_18__ap[6]) + ); + AOI22_X1_LVT i_1_0_820( + .A1(registers_6__ap[6]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[6]), + .ZN(n_1_0_781) + ); + SDFF_X1_LVT \registers_reg[15][6] ( + .CK(n_0_45), .D(registers[6]), .Q(registers_15__ap[6]), .QN(), .SE(dftIn), + .SI(registers_10__ap[6]) + ); + SDFF_X1_LVT \registers_reg[27][6] ( + .CK(n_0_57), .D(registers[6]), .Q(registers_27__ap[6]), .QN(), .SE(dftIn), + .SI(registers_29__ap[6]) + ); + AOI22_X1_LVT i_1_0_819( + .A1(registers_15__ap[6]), .A2(n_1_0_1286), .B1(n_1_0_1279), .B2(registers_27__ap[6]), + .ZN(n_1_0_780) + ); + SDFF_X1_LVT \registers_reg[11][6] ( + .CK(n_0_41), .D(registers[6]), .Q(registers_11__ap[6]), .QN(), .SE(dftIn), + .SI(registers_15__ap[6]) + ); + SDFF_X1_LVT \registers_reg[16][6] ( + .CK(n_0_46), .D(registers[6]), .Q(registers_16__ap[6]), .QN(), .SE(dftIn), + .SI(registers_11__ap[6]) + ); + AOI22_X1_LVT i_1_0_818( + .A1(registers_11__ap[6]), .A2(n_1_0_1270), .B1(n_1_0_1267), .B2(registers_16__ap[6]), + .ZN(n_1_0_779) + ); + SDFF_X1_LVT \registers_reg[5][6] ( + .CK(n_0_35), .D(registers[6]), .Q(registers_5__ap[6]), .QN(), .SE(dftIn), + .SI(registers_6__ap[6]) + ); + SDFF_X1_LVT \registers_reg[31][6] ( + .CK(n_0_61), .D(registers[6]), .Q(registers_31__ap[6]), .QN(), .SE(dftIn), + .SI(registers_5__ap[6]) + ); + AOI22_X1_LVT i_1_0_817( + .A1(registers_5__ap[6]), .A2(n_1_0_1273), .B1(n_1_0_1266), .B2(registers_31__ap[6]), + .ZN(n_1_0_778) + ); + NAND4_X1_LVT i_1_0_816( + .A1(n_1_0_781), .A2(n_1_0_780), .A3(n_1_0_779), .A4(n_1_0_778), .ZN(n_1_0_777) + ); + SDFF_X1_LVT \registers_reg[26][6] ( + .CK(n_0_56), .D(registers[6]), .Q(registers_26__ap[6]), .QN(), .SE(dftIn), + .SI(registers_27__ap[6]) + ); + SDFF_X1_LVT \registers_reg[30][6] ( + .CK(n_0_60), .D(registers[6]), .Q(registers_30__ap[6]), .QN(), .SE(dftIn), + .SI(registers_26__ap[6]) + ); + AOI22_X1_LVT i_1_0_815( + .A1(registers_26__ap[6]), .A2(n_1_0_1285), .B1(n_1_0_1272), .B2(registers_30__ap[6]), + .ZN(n_1_0_776) + ); + SDFF_X1_LVT \registers_reg[20][6] ( + .CK(n_0_50), .D(registers[6]), .Q(registers_20__ap[6]), .QN(), .SE(dftIn), + .SI(registers_1__ap[6]) + ); + SDFF_X1_LVT \registers_reg[4][6] ( + .CK(n_0_34), .D(registers[6]), .Q(registers_4__ap[6]), .QN(), .SE(dftIn), + .SI(registers_31__ap[6]) + ); + AOI22_X1_LVT i_1_0_814( + .A1(registers_20__ap[6]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[6]), + .ZN(n_1_0_775) + ); + SDFF_X1_LVT \registers_reg[22][6] ( + .CK(n_0_52), .D(registers[6]), .Q(registers_22__ap[6]), .QN(), .SE(dftIn), + .SI(registers_20__ap[6]) + ); + SDFF_X1_LVT \registers_reg[21][6] ( + .CK(n_0_51), .D(registers[6]), .Q(registers_21__ap[6]), .QN(), .SE(dftIn), + .SI(registers_22__ap[6]) + ); + AOI22_X1_LVT i_1_0_813( + .A1(registers_22__ap[6]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[6]), + .ZN(n_1_0_774) + ); + SDFF_X1_LVT \registers_reg[24][6] ( + .CK(n_0_54), .D(registers[6]), .Q(registers_24__ap[6]), .QN(), .SE(dftIn), + .SI(registers_30__ap[6]) + ); + SDFF_X1_LVT \registers_reg[12][6] ( + .CK(n_0_42), .D(registers[6]), .Q(registers_12__ap[6]), .QN(), .SE(dftIn), + .SI(registers_16__ap[6]) + ); + AOI22_X1_LVT i_1_0_812( + .A1(registers_24__ap[6]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[6]), + .ZN(n_1_0_773) + ); + NAND4_X1_LVT i_1_0_811( + .A1(n_1_0_776), .A2(n_1_0_775), .A3(n_1_0_774), .A4(n_1_0_773), .ZN(n_1_0_772) + ); + SDFF_X1_LVT \registers_reg[13][6] ( + .CK(n_0_43), .D(registers[6]), .Q(registers_13__ap[6]), .QN(), .SE(dftIn), + .SI(registers_12__ap[6]) + ); + SDFF_X1_LVT \registers_reg[25][6] ( + .CK(n_0_55), .D(registers[6]), .Q(registers_25__ap[6]), .QN(), .SE(dftIn), + .SI(registers_24__ap[6]) + ); + AOI22_X1_LVT i_1_0_810( + .A1(registers_13__ap[6]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[6]), + .ZN(n_1_0_771) + ); + SDFF_X1_LVT \registers_reg[7][6] ( + .CK(n_0_37), .D(registers[6]), .Q(registers_7__ap[6]), .QN(), .SE(dftIn), + .SI(registers_4__ap[6]) + ); + SDFF_X1_LVT \registers_reg[14][6] ( + .CK(n_0_44), .D(registers[6]), .Q(registers_14__ap[6]), .QN(), .SE(dftIn), + .SI(registers_13__ap[6]) + ); + AOI22_X1_LVT i_1_0_809( + .A1(registers_7__ap[6]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[6]), + .ZN(n_1_0_770) + ); + SDFF_X1_LVT \registers_reg[19][6] ( + .CK(n_0_49), .D(registers[6]), .Q(registers_19__ap[6]), .QN(), .SE(dftIn), + .SI(registers_21__ap[6]) + ); + SDFF_X1_LVT \registers_reg[3][6] ( + .CK(n_0_33), .D(registers[6]), .Q(registers_3__ap[6]), .QN(), .SE(dftIn), + .SI(registers_7__ap[6]) + ); + AOI22_X1_LVT i_1_0_808( + .A1(registers_19__ap[6]), .A2(n_1_0_1295), .B1(n_1_0_1257), .B2(registers_3__ap[6]), + .ZN(n_1_0_769) + ); + SDFF_X1_LVT \registers_reg[2][6] ( + .CK(n_0_32), .D(registers[6]), .Q(registers_2__ap[6]), .QN(), .SE(dftIn), + .SI(registers_25__ap[6]) + ); + SDFF_X1_LVT \registers_reg[23][6] ( + .CK(n_0_53), .D(registers[6]), .Q(registers_23__ap[6]), .QN(), .SE(dftIn), + .SI(registers_19__ap[6]) + ); + AOI22_X1_LVT i_1_0_807( + .A1(registers_2__ap[6]), .A2(n_1_0_1268), .B1(n_1_0_1264), .B2(registers_23__ap[6]), + .ZN(n_1_0_768) + ); + NAND4_X1_LVT i_1_0_806( + .A1(n_1_0_771), .A2(n_1_0_770), .A3(n_1_0_769), .A4(n_1_0_768), .ZN(n_1_0_767) + ); + NOR3_X1_LVT i_1_0_805( + .A1(n_1_0_777), .A2(n_1_0_772), .A3(n_1_0_767), .ZN(n_1_0_766) + ); + NAND4_X1_LVT i_1_0_804( + .A1(n_1_0_784), .A2(n_1_0_783), .A3(n_1_0_782), .A4(n_1_0_766), .ZN(RRs1[6]) + ); + AND2_X1_LVT i_0_0_5( + .A1(n_0_0_16), .A2(WRd[5]), .ZN(registers[5]) + ); + SDFF_X1_LVT \registers_reg[28][5] ( + .CK(n_0_58), .D(registers[5]), .Q(registers_28__ap[5]), .QN(), .SE(dftIn), + .SI(registers_2__ap[6]) + ); + SDFF_X1_LVT \registers_reg[4][5] ( + .CK(n_0_34), .D(registers[5]), .Q(registers_4__ap[5]), .QN(), .SE(dftIn), + .SI(registers_3__ap[6]) + ); + AOI22_X1_LVT i_1_0_803( + .A1(registers_28__ap[5]), .A2(n_1_0_1283), .B1(n_1_0_1278), .B2(registers_4__ap[5]), + .ZN(n_1_0_765) + ); + SDFF_X1_LVT \registers_reg[10][5] ( + .CK(n_0_40), .D(registers[5]), .Q(registers_10__ap[5]), .QN(), .SE(dftIn), + .SI(registers_14__ap[6]) + ); + SDFF_X1_LVT \registers_reg[26][5] ( + .CK(n_0_56), .D(registers[5]), .Q(registers_26__ap[5]), .QN(), .SE(dftIn), + .SI(registers_28__ap[5]) + ); + SDFF_X1_LVT \registers_reg[8][5] ( + .CK(n_0_38), .D(registers[5]), .Q(registers_8__ap[5]), .QN(), .SE(dftIn), + .SI(registers_4__ap[5]) + ); + AOI222_X1_LVT i_1_0_802( + .A1(registers_10__ap[5]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[5]), + .C1(registers_8__ap[5]), .C2(n_1_0_1282), .ZN(n_1_0_764) + ); + SDFF_X1_LVT \registers_reg[9][5] ( + .CK(n_0_39), .D(registers[5]), .Q(registers_9__ap[5]), .QN(), .SE(dftIn), + .SI(registers_8__ap[5]) + ); + SDFF_X1_LVT \registers_reg[29][5] ( + .CK(n_0_59), .D(registers[5]), .Q(registers_29__ap[5]), .QN(), .SE(dftIn), + .SI(registers_26__ap[5]) + ); + AOI22_X1_LVT i_1_0_801( + .A1(registers_9__ap[5]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[5]), + .ZN(n_1_0_763) + ); + SDFF_X1_LVT \registers_reg[6][5] ( + .CK(n_0_36), .D(registers[5]), .Q(registers_6__ap[5]), .QN(), .SE(dftIn), + .SI(registers_9__ap[5]) + ); + SDFF_X1_LVT \registers_reg[1][5] ( + .CK(n_0_0), .D(registers[5]), .Q(registers_1__ap[5]), .QN(), .SE(dftIn), + .SI(registers_23__ap[6]) + ); + AOI22_X1_LVT i_1_0_800( + .A1(registers_6__ap[5]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[5]), + .ZN(n_1_0_762) + ); + SDFF_X1_LVT \registers_reg[16][5] ( + .CK(n_0_46), .D(registers[5]), .Q(registers_16__ap[5]), .QN(), .SE(dftIn), + .SI(registers_10__ap[5]) + ); + SDFF_X1_LVT \registers_reg[3][5] ( + .CK(n_0_33), .D(registers[5]), .Q(registers_3__ap[5]), .QN(), .SE(dftIn), + .SI(registers_6__ap[5]) + ); + AOI22_X1_LVT i_1_0_799( + .A1(registers_16__ap[5]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[5]), + .ZN(n_1_0_761) + ); + SDFF_X1_LVT \registers_reg[5][5] ( + .CK(n_0_35), .D(registers[5]), .Q(registers_5__ap[5]), .QN(), .SE(dftIn), + .SI(registers_3__ap[5]) + ); + SDFF_X1_LVT \registers_reg[31][5] ( + .CK(n_0_61), .D(registers[5]), .Q(registers_31__ap[5]), .QN(), .SE(dftIn), + .SI(registers_5__ap[5]) + ); + AOI22_X1_LVT i_1_0_798( + .A1(registers_5__ap[5]), .A2(n_1_0_1273), .B1(n_1_0_1266), .B2(registers_31__ap[5]), + .ZN(n_1_0_760) + ); + SDFF_X1_LVT \registers_reg[15][5] ( + .CK(n_0_45), .D(registers[5]), .Q(registers_15__ap[5]), .QN(), .SE(dftIn), + .SI(registers_16__ap[5]) + ); + SDFF_X1_LVT \registers_reg[23][5] ( + .CK(n_0_53), .D(registers[5]), .Q(registers_23__ap[5]), .QN(), .SE(dftIn), + .SI(registers_1__ap[5]) + ); + AOI22_X1_LVT i_1_0_797( + .A1(registers_15__ap[5]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[5]), + .ZN(n_1_0_759) + ); + NAND4_X1_LVT i_1_0_796( + .A1(n_1_0_762), .A2(n_1_0_761), .A3(n_1_0_760), .A4(n_1_0_759), .ZN(n_1_0_758) + ); + SDFF_X1_LVT \registers_reg[18][5] ( + .CK(n_0_48), .D(registers[5]), .Q(registers_18__ap[5]), .QN(), .SE(dftIn), + .SI(registers_23__ap[5]) + ); + SDFF_X1_LVT \registers_reg[30][5] ( + .CK(n_0_60), .D(registers[5]), .Q(registers_30__ap[5]), .QN(), .SE(dftIn), + .SI(registers_29__ap[5]) + ); + AOI22_X1_LVT i_1_0_795( + .A1(registers_18__ap[5]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[5]), + .ZN(n_1_0_757) + ); + SDFF_X1_LVT \registers_reg[24][5] ( + .CK(n_0_54), .D(registers[5]), .Q(registers_24__ap[5]), .QN(), .SE(dftIn), + .SI(registers_30__ap[5]) + ); + SDFF_X1_LVT \registers_reg[12][5] ( + .CK(n_0_42), .D(registers[5]), .Q(registers_12__ap[5]), .QN(), .SE(dftIn), + .SI(registers_15__ap[5]) + ); + AOI22_X1_LVT i_1_0_794( + .A1(registers_24__ap[5]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[5]), + .ZN(n_1_0_756) + ); + SDFF_X1_LVT \registers_reg[22][5] ( + .CK(n_0_52), .D(registers[5]), .Q(registers_22__ap[5]), .QN(), .SE(dftIn), + .SI(registers_18__ap[5]) + ); + SDFF_X1_LVT \registers_reg[21][5] ( + .CK(n_0_51), .D(registers[5]), .Q(registers_21__ap[5]), .QN(), .SE(dftIn), + .SI(registers_22__ap[5]) + ); + AOI22_X1_LVT i_1_0_793( + .A1(registers_22__ap[5]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[5]), + .ZN(n_1_0_755) + ); + SDFF_X1_LVT \registers_reg[20][5] ( + .CK(n_0_50), .D(registers[5]), .Q(registers_20__ap[5]), .QN(), .SE(dftIn), + .SI(registers_21__ap[5]) + ); + SDFF_X1_LVT \registers_reg[17][5] ( + .CK(n_0_47), .D(registers[5]), .Q(registers_17__ap[5]), .QN(), .SE(dftIn), + .SI(registers_20__ap[5]) + ); + AOI22_X1_LVT i_1_0_792( + .A1(registers_20__ap[5]), .A2(n_1_0_1281), .B1(n_1_0_1271), .B2(registers_17__ap[5]), + .ZN(n_1_0_754) + ); + NAND4_X1_LVT i_1_0_791( + .A1(n_1_0_757), .A2(n_1_0_756), .A3(n_1_0_755), .A4(n_1_0_754), .ZN(n_1_0_753) + ); + SDFF_X1_LVT \registers_reg[13][5] ( + .CK(n_0_43), .D(registers[5]), .Q(registers_13__ap[5]), .QN(), .SE(dftIn), + .SI(registers_12__ap[5]) + ); + SDFF_X1_LVT \registers_reg[25][5] ( + .CK(n_0_55), .D(registers[5]), .Q(registers_25__ap[5]), .QN(), .SE(dftIn), + .SI(registers_24__ap[5]) + ); + AOI22_X1_LVT i_1_0_790( + .A1(registers_13__ap[5]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[5]), + .ZN(n_1_0_752) + ); + SDFF_X1_LVT \registers_reg[19][5] ( + .CK(n_0_49), .D(registers[5]), .Q(registers_19__ap[5]), .QN(), .SE(dftIn), + .SI(registers_17__ap[5]) + ); + SDFF_X1_LVT \registers_reg[2][5] ( + .CK(n_0_32), .D(registers[5]), .Q(registers_2__ap[5]), .QN(), .SE(dftIn), + .SI(registers_25__ap[5]) + ); + AOI22_X1_LVT i_1_0_789( + .A1(registers_19__ap[5]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[5]), + .ZN(n_1_0_751) + ); + SDFF_X1_LVT \registers_reg[7][5] ( + .CK(n_0_37), .D(registers[5]), .Q(registers_7__ap[5]), .QN(), .SE(dftIn), + .SI(registers_31__ap[5]) + ); + SDFF_X1_LVT \registers_reg[14][5] ( + .CK(n_0_44), .D(registers[5]), .Q(registers_14__ap[5]), .QN(), .SE(dftIn), + .SI(registers_13__ap[5]) + ); + AOI22_X1_LVT i_1_0_788( + .A1(registers_7__ap[5]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[5]), + .ZN(n_1_0_750) + ); + SDFF_X1_LVT \registers_reg[27][5] ( + .CK(n_0_57), .D(registers[5]), .Q(registers_27__ap[5]), .QN(), .SE(dftIn), + .SI(registers_2__ap[5]) + ); + SDFF_X1_LVT \registers_reg[11][5] ( + .CK(n_0_41), .D(registers[5]), .Q(registers_11__ap[5]), .QN(), .SE(dftIn), + .SI(registers_14__ap[5]) + ); + AOI22_X1_LVT i_1_0_787( + .A1(registers_27__ap[5]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[5]), + .ZN(n_1_0_749) + ); + NAND4_X1_LVT i_1_0_786( + .A1(n_1_0_752), .A2(n_1_0_751), .A3(n_1_0_750), .A4(n_1_0_749), .ZN(n_1_0_748) + ); + NOR3_X1_LVT i_1_0_785( + .A1(n_1_0_758), .A2(n_1_0_753), .A3(n_1_0_748), .ZN(n_1_0_747) + ); + NAND4_X1_LVT i_1_0_784( + .A1(n_1_0_765), .A2(n_1_0_764), .A3(n_1_0_763), .A4(n_1_0_747), .ZN(RRs1[5]) + ); + AND2_X1_LVT i_0_0_4( + .A1(n_0_0_16), .A2(WRd[4]), .ZN(registers[4]) + ); + SDFF_X1_LVT \registers_reg[10][4] ( + .CK(n_0_40), .D(registers[4]), .Q(registers_10__ap[4]), .QN(), .SE(dftIn), + .SI(registers_11__ap[5]) + ); + SDFF_X1_LVT \registers_reg[21][4] ( + .CK(n_0_51), .D(registers[4]), .Q(registers_21__ap[4]), .QN(), .SE(dftIn), + .SI(registers_19__ap[5]) + ); + AOI22_X1_LVT i_1_0_783( + .A1(registers_10__ap[4]), .A2(n_1_0_1287), .B1(n_1_0_1259), .B2(registers_21__ap[4]), + .ZN(n_1_0_746) + ); + SDFF_X1_LVT \registers_reg[9][4] ( + .CK(n_0_39), .D(registers[4]), .Q(registers_9__ap[4]), .QN(), .SE(dftIn), + .SI(registers_7__ap[5]) + ); + SDFF_X1_LVT \registers_reg[1][4] ( + .CK(n_0_0), .D(registers[4]), .Q(registers_1__ap[4]), .QN(), .SE(dftIn), + .SI(registers_21__ap[4]) + ); + AOI22_X1_LVT i_1_0_778( + .A1(registers_9__ap[4]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[4]), + .ZN(n_1_0_741) + ); + SDFF_X1_LVT \registers_reg[18][4] ( + .CK(n_0_48), .D(registers[4]), .Q(registers_18__ap[4]), .QN(), .SE(dftIn), + .SI(registers_1__ap[4]) + ); + SDFF_X1_LVT \registers_reg[8][4] ( + .CK(n_0_38), .D(registers[4]), .Q(registers_8__ap[4]), .QN(), .SE(dftIn), + .SI(registers_9__ap[4]) + ); + AOI22_X1_LVT i_1_0_777( + .A1(registers_18__ap[4]), .A2(n_1_0_1297), .B1(n_1_0_1282), .B2(registers_8__ap[4]), + .ZN(n_1_0_740) + ); + NAND3_X1_LVT i_1_0_775( + .A1(n_1_0_746), .A2(n_1_0_741), .A3(n_1_0_740), .ZN(n_1_0_738) + ); + SDFF_X1_LVT \registers_reg[22][4] ( + .CK(n_0_52), .D(registers[4]), .Q(registers_22__ap[4]), .QN(), .SE(dftIn), + .SI(registers_18__ap[4]) + ); + SDFF_X1_LVT \registers_reg[23][4] ( + .CK(n_0_53), .D(registers[4]), .Q(registers_23__ap[4]), .QN(), .SE(dftIn), + .SI(registers_22__ap[4]) + ); + AOI221_X1_LVT i_1_0_774( + .A(n_1_0_738), .B1(n_1_0_1294), .B2(registers_22__ap[4]), .C1(registers_23__ap[4]), + .C2(n_1_0_1264), .ZN(n_1_0_737) + ); + SDFF_X1_LVT \registers_reg[28][4] ( + .CK(n_0_58), .D(registers[4]), .Q(registers_28__ap[4]), .QN(), .SE(dftIn), + .SI(registers_27__ap[5]) + ); + SDFF_X1_LVT \registers_reg[20][4] ( + .CK(n_0_50), .D(registers[4]), .Q(registers_20__ap[4]), .QN(), .SE(dftIn), + .SI(registers_23__ap[4]) + ); + AOI22_X1_LVT i_1_0_782( + .A1(registers_28__ap[4]), .A2(n_1_0_1283), .B1(n_1_0_1281), .B2(registers_20__ap[4]), + .ZN(n_1_0_745) + ); + SDFF_X1_LVT \registers_reg[19][4] ( + .CK(n_0_49), .D(registers[4]), .Q(registers_19__ap[4]), .QN(), .SE(dftIn), + .SI(registers_20__ap[4]) + ); + SDFF_X1_LVT \registers_reg[13][4] ( + .CK(n_0_43), .D(registers[4]), .Q(registers_13__ap[4]), .QN(), .SE(dftIn), + .SI(registers_10__ap[4]) + ); + AOI22_X1_LVT i_1_0_780( + .A1(registers_19__ap[4]), .A2(n_1_0_1295), .B1(n_1_0_1277), .B2(registers_13__ap[4]), + .ZN(n_1_0_743) + ); + SDFF_X1_LVT \registers_reg[26][4] ( + .CK(n_0_56), .D(registers[4]), .Q(registers_26__ap[4]), .QN(), .SE(dftIn), + .SI(registers_28__ap[4]) + ); + SDFF_X1_LVT \registers_reg[3][4] ( + .CK(n_0_33), .D(registers[4]), .Q(registers_3__ap[4]), .QN(), .SE(dftIn), + .SI(registers_8__ap[4]) + ); + AOI22_X1_LVT i_1_0_776( + .A1(registers_26__ap[4]), .A2(n_1_0_1285), .B1(n_1_0_1257), .B2(registers_3__ap[4]), + .ZN(n_1_0_739) + ); + NAND3_X1_LVT i_1_0_773( + .A1(n_1_0_745), .A2(n_1_0_743), .A3(n_1_0_739), .ZN(n_1_0_736) + ); + SDFF_X1_LVT \registers_reg[30][4] ( + .CK(n_0_60), .D(registers[4]), .Q(registers_30__ap[4]), .QN(), .SE(dftIn), + .SI(registers_26__ap[4]) + ); + SDFF_X1_LVT \registers_reg[31][4] ( + .CK(n_0_61), .D(registers[4]), .Q(registers_31__ap[4]), .QN(), .SE(dftIn), + .SI(registers_3__ap[4]) + ); + AOI221_X1_LVT i_1_0_772( + .A(n_1_0_736), .B1(n_1_0_1272), .B2(registers_30__ap[4]), .C1(registers_31__ap[4]), + .C2(n_1_0_1266), .ZN(n_1_0_735) + ); + SDFF_X1_LVT \registers_reg[24][4] ( + .CK(n_0_54), .D(registers[4]), .Q(registers_24__ap[4]), .QN(), .SE(dftIn), + .SI(registers_30__ap[4]) + ); + SDFF_X1_LVT \registers_reg[12][4] ( + .CK(n_0_42), .D(registers[4]), .Q(registers_12__ap[4]), .QN(), .SE(dftIn), + .SI(registers_13__ap[4]) + ); + AOI22_X1_LVT i_1_0_781( + .A1(registers_24__ap[4]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[4]), + .ZN(n_1_0_744) + ); + SDFF_X1_LVT \registers_reg[27][4] ( + .CK(n_0_57), .D(registers[4]), .Q(registers_27__ap[4]), .QN(), .SE(dftIn), + .SI(registers_24__ap[4]) + ); + SDFF_X1_LVT \registers_reg[11][4] ( + .CK(n_0_41), .D(registers[4]), .Q(registers_11__ap[4]), .QN(), .SE(dftIn), + .SI(registers_12__ap[4]) + ); + AOI22_X1_LVT i_1_0_779( + .A1(registers_27__ap[4]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[4]), + .ZN(n_1_0_742) + ); + SDFF_X1_LVT \registers_reg[17][4] ( + .CK(n_0_47), .D(registers[4]), .Q(registers_17__ap[4]), .QN(), .SE(dftIn), + .SI(registers_19__ap[4]) + ); + SDFF_X1_LVT \registers_reg[7][4] ( + .CK(n_0_37), .D(registers[4]), .Q(registers_7__ap[4]), .QN(), .SE(dftIn), + .SI(registers_31__ap[4]) + ); + SDFF_X1_LVT \registers_reg[14][4] ( + .CK(n_0_44), .D(registers[4]), .Q(registers_14__ap[4]), .QN(), .SE(dftIn), + .SI(registers_11__ap[4]) + ); + AOI222_X1_LVT i_1_0_771( + .A1(registers_17__ap[4]), .A2(n_1_0_1271), .B1(n_1_0_1263), .B2(registers_7__ap[4]), + .C1(n_1_0_1258), .C2(registers_14__ap[4]), .ZN(n_1_0_734) + ); + SDFF_X1_LVT \registers_reg[15][4] ( + .CK(n_0_45), .D(registers[4]), .Q(registers_15__ap[4]), .QN(), .SE(dftIn), + .SI(registers_14__ap[4]) + ); + SDFF_X1_LVT \registers_reg[16][4] ( + .CK(n_0_46), .D(registers[4]), .Q(registers_16__ap[4]), .QN(), .SE(dftIn), + .SI(registers_15__ap[4]) + ); + AOI22_X1_LVT i_1_0_770( + .A1(registers_15__ap[4]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[4]), + .ZN(n_1_0_733) + ); + SDFF_X1_LVT \registers_reg[4][4] ( + .CK(n_0_34), .D(registers[4]), .Q(registers_4__ap[4]), .QN(), .SE(dftIn), + .SI(registers_7__ap[4]) + ); + SDFF_X1_LVT \registers_reg[25][4] ( + .CK(n_0_55), .D(registers[4]), .Q(registers_25__ap[4]), .QN(), .SE(dftIn), + .SI(registers_27__ap[4]) + ); + AOI22_X1_LVT i_1_0_769( + .A1(registers_4__ap[4]), .A2(n_1_0_1278), .B1(n_1_0_1269), .B2(registers_25__ap[4]), + .ZN(n_1_0_732) + ); + SDFF_X1_LVT \registers_reg[29][4] ( + .CK(n_0_59), .D(registers[4]), .Q(registers_29__ap[4]), .QN(), .SE(dftIn), + .SI(registers_25__ap[4]) + ); + SDFF_X1_LVT \registers_reg[2][4] ( + .CK(n_0_32), .D(registers[4]), .Q(registers_2__ap[4]), .QN(), .SE(dftIn), + .SI(registers_29__ap[4]) + ); + AOI22_X1_LVT i_1_0_768( + .A1(registers_29__ap[4]), .A2(n_1_0_1276), .B1(n_1_0_1268), .B2(registers_2__ap[4]), + .ZN(n_1_0_731) + ); + NAND3_X1_LVT i_1_0_767( + .A1(n_1_0_733), .A2(n_1_0_732), .A3(n_1_0_731), .ZN(n_1_0_730) + ); + SDFF_X1_LVT \registers_reg[6][4] ( + .CK(n_0_36), .D(registers[4]), .Q(registers_6__ap[4]), .QN(), .SE(dftIn), + .SI(registers_4__ap[4]) + ); + SDFF_X1_LVT \registers_reg[5][4] ( + .CK(n_0_35), .D(registers[4]), .Q(registers_5__ap[4]), .QN(), .SE(dftIn), + .SI(registers_6__ap[4]) + ); + AOI221_X1_LVT i_1_0_766( + .A(n_1_0_730), .B1(n_1_0_1300), .B2(registers_6__ap[4]), .C1(registers_5__ap[4]), + .C2(n_1_0_1273), .ZN(n_1_0_729) + ); + AND4_X1_LVT i_1_0_765( + .A1(n_1_0_744), .A2(n_1_0_742), .A3(n_1_0_734), .A4(n_1_0_729), .ZN(n_1_0_728) + ); + NAND3_X1_LVT i_1_0_764( + .A1(n_1_0_737), .A2(n_1_0_735), .A3(n_1_0_728), .ZN(RRs1[4]) + ); + AND2_X1_LVT i_0_0_3( + .A1(n_0_0_16), .A2(WRd[3]), .ZN(registers[3]) + ); + SDFF_X1_LVT \registers_reg[28][3] ( + .CK(n_0_58), .D(registers[3]), .Q(registers_28__ap[3]), .QN(), .SE(dftIn), + .SI(registers_2__ap[4]) + ); + SDFF_X1_LVT \registers_reg[17][3] ( + .CK(n_0_47), .D(registers[3]), .Q(registers_17__ap[3]), .QN(), .SE(dftIn), + .SI(registers_17__ap[4]) + ); + AOI22_X1_LVT i_1_0_763( + .A1(registers_28__ap[3]), .A2(n_1_0_1283), .B1(n_1_0_1271), .B2(registers_17__ap[3]), + .ZN(n_1_0_727) + ); + SDFF_X1_LVT \registers_reg[10][3] ( + .CK(n_0_40), .D(registers[3]), .Q(registers_10__ap[3]), .QN(), .SE(dftIn), + .SI(registers_16__ap[4]) + ); + SDFF_X1_LVT \registers_reg[26][3] ( + .CK(n_0_56), .D(registers[3]), .Q(registers_26__ap[3]), .QN(), .SE(dftIn), + .SI(registers_28__ap[3]) + ); + SDFF_X1_LVT \registers_reg[8][3] ( + .CK(n_0_38), .D(registers[3]), .Q(registers_8__ap[3]), .QN(), .SE(dftIn), + .SI(registers_5__ap[4]) + ); + AOI222_X1_LVT i_1_0_762( + .A1(registers_10__ap[3]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[3]), + .C1(registers_8__ap[3]), .C2(n_1_0_1282), .ZN(n_1_0_726) + ); + SDFF_X1_LVT \registers_reg[9][3] ( + .CK(n_0_39), .D(registers[3]), .Q(registers_9__ap[3]), .QN(), .SE(dftIn), + .SI(registers_8__ap[3]) + ); + SDFF_X1_LVT \registers_reg[29][3] ( + .CK(n_0_59), .D(registers[3]), .Q(registers_29__ap[3]), .QN(), .SE(dftIn), + .SI(registers_26__ap[3]) + ); + AOI22_X1_LVT i_1_0_761( + .A1(registers_9__ap[3]), .A2(n_1_0_1291), .B1(n_1_0_1276), .B2(registers_29__ap[3]), + .ZN(n_1_0_725) + ); + SDFF_X1_LVT \registers_reg[6][3] ( + .CK(n_0_36), .D(registers[3]), .Q(registers_6__ap[3]), .QN(), .SE(dftIn), + .SI(registers_9__ap[3]) + ); + SDFF_X1_LVT \registers_reg[1][3] ( + .CK(n_0_0), .D(registers[3]), .Q(registers_1__ap[3]), .QN(), .SE(dftIn), + .SI(registers_17__ap[3]) + ); + AOI22_X1_LVT i_1_0_760( + .A1(registers_6__ap[3]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[3]), + .ZN(n_1_0_724) + ); + SDFF_X1_LVT \registers_reg[16][3] ( + .CK(n_0_46), .D(registers[3]), .Q(registers_16__ap[3]), .QN(), .SE(dftIn), + .SI(registers_10__ap[3]) + ); + SDFF_X1_LVT \registers_reg[3][3] ( + .CK(n_0_33), .D(registers[3]), .Q(registers_3__ap[3]), .QN(), .SE(dftIn), + .SI(registers_6__ap[3]) + ); + AOI22_X1_LVT i_1_0_759( + .A1(registers_16__ap[3]), .A2(n_1_0_1267), .B1(n_1_0_1257), .B2(registers_3__ap[3]), + .ZN(n_1_0_723) + ); + SDFF_X1_LVT \registers_reg[5][3] ( + .CK(n_0_35), .D(registers[3]), .Q(registers_5__ap[3]), .QN(), .SE(dftIn), + .SI(registers_3__ap[3]) + ); + SDFF_X1_LVT \registers_reg[31][3] ( + .CK(n_0_61), .D(registers[3]), .Q(registers_31__ap[3]), .QN(), .SE(dftIn), + .SI(registers_5__ap[3]) + ); + AOI22_X1_LVT i_1_0_758( + .A1(registers_5__ap[3]), .A2(n_1_0_1273), .B1(n_1_0_1266), .B2(registers_31__ap[3]), + .ZN(n_1_0_722) + ); + SDFF_X1_LVT \registers_reg[15][3] ( + .CK(n_0_45), .D(registers[3]), .Q(registers_15__ap[3]), .QN(), .SE(dftIn), + .SI(registers_16__ap[3]) + ); + SDFF_X1_LVT \registers_reg[23][3] ( + .CK(n_0_53), .D(registers[3]), .Q(registers_23__ap[3]), .QN(), .SE(dftIn), + .SI(registers_1__ap[3]) + ); + AOI22_X1_LVT i_1_0_757( + .A1(registers_15__ap[3]), .A2(n_1_0_1286), .B1(n_1_0_1264), .B2(registers_23__ap[3]), + .ZN(n_1_0_721) + ); + NAND4_X1_LVT i_1_0_756( + .A1(n_1_0_724), .A2(n_1_0_723), .A3(n_1_0_722), .A4(n_1_0_721), .ZN(n_1_0_720) + ); + SDFF_X1_LVT \registers_reg[18][3] ( + .CK(n_0_48), .D(registers[3]), .Q(registers_18__ap[3]), .QN(), .SE(dftIn), + .SI(registers_23__ap[3]) + ); + SDFF_X1_LVT \registers_reg[30][3] ( + .CK(n_0_60), .D(registers[3]), .Q(registers_30__ap[3]), .QN(), .SE(dftIn), + .SI(registers_29__ap[3]) + ); + AOI22_X1_LVT i_1_0_755( + .A1(registers_18__ap[3]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[3]), + .ZN(n_1_0_719) + ); + SDFF_X1_LVT \registers_reg[20][3] ( + .CK(n_0_50), .D(registers[3]), .Q(registers_20__ap[3]), .QN(), .SE(dftIn), + .SI(registers_18__ap[3]) + ); + SDFF_X1_LVT \registers_reg[4][3] ( + .CK(n_0_34), .D(registers[3]), .Q(registers_4__ap[3]), .QN(), .SE(dftIn), + .SI(registers_31__ap[3]) + ); + AOI22_X1_LVT i_1_0_754( + .A1(registers_20__ap[3]), .A2(n_1_0_1281), .B1(n_1_0_1278), .B2(registers_4__ap[3]), + .ZN(n_1_0_718) + ); + SDFF_X1_LVT \registers_reg[22][3] ( + .CK(n_0_52), .D(registers[3]), .Q(registers_22__ap[3]), .QN(), .SE(dftIn), + .SI(registers_20__ap[3]) + ); + SDFF_X1_LVT \registers_reg[21][3] ( + .CK(n_0_51), .D(registers[3]), .Q(registers_21__ap[3]), .QN(), .SE(dftIn), + .SI(registers_22__ap[3]) + ); + AOI22_X1_LVT i_1_0_753( + .A1(registers_22__ap[3]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[3]), + .ZN(n_1_0_717) + ); + SDFF_X1_LVT \registers_reg[24][3] ( + .CK(n_0_54), .D(registers[3]), .Q(registers_24__ap[3]), .QN(), .SE(dftIn), + .SI(registers_30__ap[3]) + ); + SDFF_X1_LVT \registers_reg[12][3] ( + .CK(n_0_42), .D(registers[3]), .Q(registers_12__ap[3]), .QN(), .SE(dftIn), + .SI(registers_15__ap[3]) + ); + AOI22_X1_LVT i_1_0_752( + .A1(registers_24__ap[3]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[3]), + .ZN(n_1_0_716) + ); + NAND4_X1_LVT i_1_0_751( + .A1(n_1_0_719), .A2(n_1_0_718), .A3(n_1_0_717), .A4(n_1_0_716), .ZN(n_1_0_715) + ); + SDFF_X1_LVT \registers_reg[13][3] ( + .CK(n_0_43), .D(registers[3]), .Q(registers_13__ap[3]), .QN(), .SE(dftIn), + .SI(registers_12__ap[3]) + ); + SDFF_X1_LVT \registers_reg[25][3] ( + .CK(n_0_55), .D(registers[3]), .Q(registers_25__ap[3]), .QN(), .SE(dftIn), + .SI(registers_24__ap[3]) + ); + AOI22_X1_LVT i_1_0_750( + .A1(registers_13__ap[3]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[3]), + .ZN(n_1_0_714) + ); + SDFF_X1_LVT \registers_reg[19][3] ( + .CK(n_0_49), .D(registers[3]), .Q(registers_19__ap[3]), .QN(), .SE(dftIn), + .SI(registers_21__ap[3]) + ); + SDFF_X1_LVT \registers_reg[2][3] ( + .CK(n_0_32), .D(registers[3]), .Q(registers_2__ap[3]), .QN(), .SE(dftIn), + .SI(registers_25__ap[3]) + ); + AOI22_X1_LVT i_1_0_749( + .A1(registers_19__ap[3]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[3]), + .ZN(n_1_0_713) + ); + SDFF_X1_LVT \registers_reg[7][3] ( + .CK(n_0_37), .D(registers[3]), .Q(registers_7__ap[3]), .QN(), .SE(dftIn), + .SI(registers_4__ap[3]) + ); + SDFF_X1_LVT \registers_reg[14][3] ( + .CK(n_0_44), .D(registers[3]), .Q(registers_14__ap[3]), .QN(), .SE(dftIn), + .SI(registers_13__ap[3]) + ); + AOI22_X1_LVT i_1_0_748( + .A1(registers_7__ap[3]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[3]), + .ZN(n_1_0_712) + ); + SDFF_X1_LVT \registers_reg[27][3] ( + .CK(n_0_57), .D(registers[3]), .Q(registers_27__ap[3]), .QN(), .SE(dftIn), + .SI(registers_2__ap[3]) + ); + SDFF_X1_LVT \registers_reg[11][3] ( + .CK(n_0_41), .D(registers[3]), .Q(registers_11__ap[3]), .QN(), .SE(dftIn), + .SI(registers_14__ap[3]) + ); + AOI22_X1_LVT i_1_0_747( + .A1(registers_27__ap[3]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[3]), + .ZN(n_1_0_711) + ); + NAND4_X1_LVT i_1_0_746( + .A1(n_1_0_714), .A2(n_1_0_713), .A3(n_1_0_712), .A4(n_1_0_711), .ZN(n_1_0_710) + ); + NOR3_X1_LVT i_1_0_745( + .A1(n_1_0_720), .A2(n_1_0_715), .A3(n_1_0_710), .ZN(n_1_0_709) + ); + NAND4_X1_LVT i_1_0_744( + .A1(n_1_0_727), .A2(n_1_0_726), .A3(n_1_0_725), .A4(n_1_0_709), .ZN(RRs1[3]) + ); + AND2_X1_LVT i_0_0_2( + .A1(n_0_0_16), .A2(WRd[2]), .ZN(registers[2]) + ); + SDFF_X1_LVT \registers_reg[28][2] ( + .CK(n_0_58), .D(registers[2]), .Q(registers_28__ap[2]), .QN(), .SE(dftIn), + .SI(registers_27__ap[3]) + ); + SDFF_X1_LVT \registers_reg[4][2] ( + .CK(n_0_34), .D(registers[2]), .Q(registers_4__ap[2]), .QN(), .SE(dftIn), + .SI(registers_7__ap[3]) + ); + AOI22_X1_LVT i_1_0_740( + .A1(registers_28__ap[2]), .A2(n_1_0_1283), .B1(n_1_0_1278), .B2(registers_4__ap[2]), + .ZN(n_1_0_705) + ); + SDFF_X1_LVT \registers_reg[16][2] ( + .CK(n_0_46), .D(registers[2]), .Q(registers_16__ap[2]), .QN(), .SE(dftIn), + .SI(registers_11__ap[3]) + ); + SDFF_X1_LVT \registers_reg[31][2] ( + .CK(n_0_61), .D(registers[2]), .Q(registers_31__ap[2]), .QN(), .SE(dftIn), + .SI(registers_4__ap[2]) + ); + AOI22_X1_LVT i_1_0_743( + .A1(registers_16__ap[2]), .A2(n_1_0_1267), .B1(n_1_0_1266), .B2(registers_31__ap[2]), + .ZN(n_1_0_708) + ); + SDFF_X1_LVT \registers_reg[6][2] ( + .CK(n_0_36), .D(registers[2]), .Q(registers_6__ap[2]), .QN(), .SE(dftIn), + .SI(registers_31__ap[2]) + ); + SDFF_X1_LVT \registers_reg[1][2] ( + .CK(n_0_0), .D(registers[2]), .Q(registers_1__ap[2]), .QN(), .SE(dftIn), + .SI(registers_19__ap[3]) + ); + AOI22_X1_LVT i_1_0_739( + .A1(registers_6__ap[2]), .A2(n_1_0_1300), .B1(n_1_0_1274), .B2(registers_1__ap[2]), + .ZN(n_1_0_704) + ); + SDFF_X1_LVT \registers_reg[15][2] ( + .CK(n_0_45), .D(registers[2]), .Q(registers_15__ap[2]), .QN(), .SE(dftIn), + .SI(registers_16__ap[2]) + ); + SDFF_X1_LVT \registers_reg[27][2] ( + .CK(n_0_57), .D(registers[2]), .Q(registers_27__ap[2]), .QN(), .SE(dftIn), + .SI(registers_28__ap[2]) + ); + AOI22_X1_LVT i_1_0_742( + .A1(registers_15__ap[2]), .A2(n_1_0_1286), .B1(n_1_0_1279), .B2(registers_27__ap[2]), + .ZN(n_1_0_707) + ); + INV_X1_LVT i_1_0_741( + .A(n_1_0_707), .ZN(n_1_0_706) + ); + SDFF_X1_LVT \registers_reg[11][2] ( + .CK(n_0_41), .D(registers[2]), .Q(registers_11__ap[2]), .QN(), .SE(dftIn), + .SI(registers_15__ap[2]) + ); + SDFF_X1_LVT \registers_reg[5][2] ( + .CK(n_0_35), .D(registers[2]), .Q(registers_5__ap[2]), .QN(), .SE(dftIn), + .SI(registers_6__ap[2]) + ); + AOI221_X1_LVT i_1_0_738( + .A(n_1_0_706), .B1(n_1_0_1270), .B2(registers_11__ap[2]), .C1(registers_5__ap[2]), + .C2(n_1_0_1273), .ZN(n_1_0_703) + ); + SDFF_X1_LVT \registers_reg[10][2] ( + .CK(n_0_40), .D(registers[2]), .Q(registers_10__ap[2]), .QN(), .SE(dftIn), + .SI(registers_11__ap[2]) + ); + SDFF_X1_LVT \registers_reg[30][2] ( + .CK(n_0_60), .D(registers[2]), .Q(registers_30__ap[2]), .QN(), .SE(dftIn), + .SI(registers_27__ap[2]) + ); + SDFF_X1_LVT \registers_reg[8][2] ( + .CK(n_0_38), .D(registers[2]), .Q(registers_8__ap[2]), .QN(), .SE(dftIn), + .SI(registers_5__ap[2]) + ); + AOI222_X1_LVT i_1_0_737( + .A1(registers_10__ap[2]), .A2(n_1_0_1287), .B1(n_1_0_1272), .B2(registers_30__ap[2]), + .C1(n_1_0_1282), .C2(registers_8__ap[2]), .ZN(n_1_0_702) + ); + NAND4_X1_LVT i_1_0_736( + .A1(n_1_0_708), .A2(n_1_0_704), .A3(n_1_0_703), .A4(n_1_0_702), .ZN(n_1_0_701) + ); + SDFF_X1_LVT \registers_reg[9][2] ( + .CK(n_0_39), .D(registers[2]), .Q(registers_9__ap[2]), .QN(), .SE(dftIn), + .SI(registers_8__ap[2]) + ); + SDFF_X1_LVT \registers_reg[29][2] ( + .CK(n_0_59), .D(registers[2]), .Q(registers_29__ap[2]), .QN(), .SE(dftIn), + .SI(registers_30__ap[2]) + ); + AOI221_X1_LVT i_1_0_735( + .A(n_1_0_701), .B1(n_1_0_1291), .B2(registers_9__ap[2]), .C1(registers_29__ap[2]), + .C2(n_1_0_1276), .ZN(n_1_0_700) + ); + SDFF_X1_LVT \registers_reg[18][2] ( + .CK(n_0_48), .D(registers[2]), .Q(registers_18__ap[2]), .QN(), .SE(dftIn), + .SI(registers_1__ap[2]) + ); + SDFF_X1_LVT \registers_reg[26][2] ( + .CK(n_0_56), .D(registers[2]), .Q(registers_26__ap[2]), .QN(), .SE(dftIn), + .SI(registers_29__ap[2]) + ); + AOI22_X1_LVT i_1_0_734( + .A1(registers_18__ap[2]), .A2(n_1_0_1297), .B1(n_1_0_1285), .B2(registers_26__ap[2]), + .ZN(n_1_0_699) + ); + SDFF_X1_LVT \registers_reg[24][2] ( + .CK(n_0_54), .D(registers[2]), .Q(registers_24__ap[2]), .QN(), .SE(dftIn), + .SI(registers_26__ap[2]) + ); + SDFF_X1_LVT \registers_reg[12][2] ( + .CK(n_0_42), .D(registers[2]), .Q(registers_12__ap[2]), .QN(), .SE(dftIn), + .SI(registers_10__ap[2]) + ); + AOI22_X1_LVT i_1_0_733( + .A1(registers_24__ap[2]), .A2(n_1_0_1289), .B1(n_1_0_1260), .B2(registers_12__ap[2]), + .ZN(n_1_0_698) + ); + SDFF_X1_LVT \registers_reg[22][2] ( + .CK(n_0_52), .D(registers[2]), .Q(registers_22__ap[2]), .QN(), .SE(dftIn), + .SI(registers_18__ap[2]) + ); + SDFF_X1_LVT \registers_reg[21][2] ( + .CK(n_0_51), .D(registers[2]), .Q(registers_21__ap[2]), .QN(), .SE(dftIn), + .SI(registers_22__ap[2]) + ); + AOI22_X1_LVT i_1_0_732( + .A1(registers_22__ap[2]), .A2(n_1_0_1294), .B1(n_1_0_1259), .B2(registers_21__ap[2]), + .ZN(n_1_0_697) + ); + NAND3_X1_LVT i_1_0_731( + .A1(n_1_0_699), .A2(n_1_0_698), .A3(n_1_0_697), .ZN(n_1_0_696) + ); + SDFF_X1_LVT \registers_reg[17][2] ( + .CK(n_0_47), .D(registers[2]), .Q(registers_17__ap[2]), .QN(), .SE(dftIn), + .SI(registers_21__ap[2]) + ); + SDFF_X1_LVT \registers_reg[20][2] ( + .CK(n_0_50), .D(registers[2]), .Q(registers_20__ap[2]), .QN(), .SE(dftIn), + .SI(registers_17__ap[2]) + ); + AOI221_X1_LVT i_1_0_730( + .A(n_1_0_696), .B1(n_1_0_1271), .B2(registers_17__ap[2]), .C1(registers_20__ap[2]), + .C2(n_1_0_1281), .ZN(n_1_0_695) + ); + SDFF_X1_LVT \registers_reg[13][2] ( + .CK(n_0_43), .D(registers[2]), .Q(registers_13__ap[2]), .QN(), .SE(dftIn), + .SI(registers_12__ap[2]) + ); + SDFF_X1_LVT \registers_reg[25][2] ( + .CK(n_0_55), .D(registers[2]), .Q(registers_25__ap[2]), .QN(), .SE(dftIn), + .SI(registers_24__ap[2]) + ); + AOI22_X1_LVT i_1_0_729( + .A1(registers_13__ap[2]), .A2(n_1_0_1277), .B1(n_1_0_1269), .B2(registers_25__ap[2]), + .ZN(n_1_0_694) + ); + SDFF_X1_LVT \registers_reg[7][2] ( + .CK(n_0_37), .D(registers[2]), .Q(registers_7__ap[2]), .QN(), .SE(dftIn), + .SI(registers_9__ap[2]) + ); + SDFF_X1_LVT \registers_reg[14][2] ( + .CK(n_0_44), .D(registers[2]), .Q(registers_14__ap[2]), .QN(), .SE(dftIn), + .SI(registers_13__ap[2]) + ); + AOI22_X1_LVT i_1_0_728( + .A1(registers_7__ap[2]), .A2(n_1_0_1263), .B1(n_1_0_1258), .B2(registers_14__ap[2]), + .ZN(n_1_0_693) + ); + SDFF_X1_LVT \registers_reg[19][2] ( + .CK(n_0_49), .D(registers[2]), .Q(registers_19__ap[2]), .QN(), .SE(dftIn), + .SI(registers_20__ap[2]) + ); + SDFF_X1_LVT \registers_reg[3][2] ( + .CK(n_0_33), .D(registers[2]), .Q(registers_3__ap[2]), .QN(), .SE(dftIn), + .SI(registers_7__ap[2]) + ); + AOI22_X1_LVT i_1_0_727( + .A1(registers_19__ap[2]), .A2(n_1_0_1295), .B1(n_1_0_1257), .B2(registers_3__ap[2]), + .ZN(n_1_0_692) + ); + NAND3_X1_LVT i_1_0_726( + .A1(n_1_0_694), .A2(n_1_0_693), .A3(n_1_0_692), .ZN(n_1_0_691) + ); + SDFF_X1_LVT \registers_reg[23][2] ( + .CK(n_0_53), .D(registers[2]), .Q(registers_23__ap[2]), .QN(), .SE(dftIn), + .SI(registers_19__ap[2]) + ); + SDFF_X1_LVT \registers_reg[2][2] ( + .CK(n_0_32), .D(registers[2]), .Q(registers_2__ap[2]), .QN(), .SE(dftIn), + .SI(registers_25__ap[2]) + ); + AOI221_X1_LVT i_1_0_725( + .A(n_1_0_691), .B1(n_1_0_1264), .B2(registers_23__ap[2]), .C1(registers_2__ap[2]), + .C2(n_1_0_1268), .ZN(n_1_0_690) + ); + NAND4_X1_LVT i_1_0_724( + .A1(n_1_0_705), .A2(n_1_0_700), .A3(n_1_0_695), .A4(n_1_0_690), .ZN(RRs1[2]) + ); + AND2_X1_LVT i_0_0_1( + .A1(n_0_0_16), .A2(WRd[1]), .ZN(registers[1]) + ); + SDFF_X1_LVT \registers_reg[13][1] ( + .CK(n_0_43), .D(registers[1]), .Q(registers_13__ap[1]), .QN(), .SE(dftIn), + .SI(registers_14__ap[2]) + ); + SDFF_X1_LVT \registers_reg[21][1] ( + .CK(n_0_51), .D(registers[1]), .Q(registers_21__ap[1]), .QN(), .SE(dftIn), + .SI(registers_23__ap[2]) + ); + AOI22_X1_LVT i_1_0_720( + .A1(registers_13__ap[1]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[1]), + .ZN(n_1_0_686) + ); + SDFF_X1_LVT \registers_reg[29][1] ( + .CK(n_0_59), .D(registers[1]), .Q(registers_29__ap[1]), .QN(), .SE(dftIn), + .SI(registers_2__ap[2]) + ); + SDFF_X1_LVT \registers_reg[23][1] ( + .CK(n_0_53), .D(registers[1]), .Q(registers_23__ap[1]), .QN(), .SE(dftIn), + .SI(registers_21__ap[1]) + ); + AOI22_X1_LVT i_1_0_723( + .A1(registers_29__ap[1]), .A2(n_1_0_1276), .B1(n_1_0_1264), .B2(registers_23__ap[1]), + .ZN(n_1_0_689) + ); + SDFF_X1_LVT \registers_reg[24][1] ( + .CK(n_0_54), .D(registers[1]), .Q(registers_24__ap[1]), .QN(), .SE(dftIn), + .SI(registers_29__ap[1]) + ); + SDFF_X1_LVT \registers_reg[20][1] ( + .CK(n_0_50), .D(registers[1]), .Q(registers_20__ap[1]), .QN(), .SE(dftIn), + .SI(registers_23__ap[1]) + ); + AOI22_X1_LVT i_1_0_719( + .A1(registers_24__ap[1]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[1]), + .ZN(n_1_0_685) + ); + SDFF_X1_LVT \registers_reg[7][1] ( + .CK(n_0_37), .D(registers[1]), .Q(registers_7__ap[1]), .QN(), .SE(dftIn), + .SI(registers_3__ap[2]) + ); + SDFF_X1_LVT \registers_reg[3][1] ( + .CK(n_0_33), .D(registers[1]), .Q(registers_3__ap[1]), .QN(), .SE(dftIn), + .SI(registers_7__ap[1]) + ); + AOI22_X1_LVT i_1_0_722( + .A1(registers_7__ap[1]), .A2(n_1_0_1263), .B1(n_1_0_1257), .B2(registers_3__ap[1]), + .ZN(n_1_0_688) + ); + INV_X1_LVT i_1_0_721( + .A(n_1_0_688), .ZN(n_1_0_687) + ); + SDFF_X1_LVT \registers_reg[31][1] ( + .CK(n_0_61), .D(registers[1]), .Q(registers_31__ap[1]), .QN(), .SE(dftIn), + .SI(registers_3__ap[1]) + ); + SDFF_X1_LVT \registers_reg[4][1] ( + .CK(n_0_34), .D(registers[1]), .Q(registers_4__ap[1]), .QN(), .SE(dftIn), + .SI(registers_31__ap[1]) + ); + AOI221_X1_LVT i_1_0_718( + .A(n_1_0_687), .B1(n_1_0_1266), .B2(registers_31__ap[1]), .C1(registers_4__ap[1]), + .C2(n_1_0_1278), .ZN(n_1_0_684) + ); + SDFF_X1_LVT \registers_reg[10][1] ( + .CK(n_0_40), .D(registers[1]), .Q(registers_10__ap[1]), .QN(), .SE(dftIn), + .SI(registers_13__ap[1]) + ); + SDFF_X1_LVT \registers_reg[26][1] ( + .CK(n_0_56), .D(registers[1]), .Q(registers_26__ap[1]), .QN(), .SE(dftIn), + .SI(registers_24__ap[1]) + ); + SDFF_X1_LVT \registers_reg[25][1] ( + .CK(n_0_55), .D(registers[1]), .Q(registers_25__ap[1]), .QN(), .SE(dftIn), + .SI(registers_26__ap[1]) + ); + AOI222_X1_LVT i_1_0_717( + .A1(registers_10__ap[1]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[1]), + .C1(registers_25__ap[1]), .C2(n_1_0_1269), .ZN(n_1_0_683) + ); + NAND4_X1_LVT i_1_0_716( + .A1(n_1_0_689), .A2(n_1_0_685), .A3(n_1_0_684), .A4(n_1_0_683), .ZN(n_1_0_682) + ); + SDFF_X1_LVT \registers_reg[8][1] ( + .CK(n_0_38), .D(registers[1]), .Q(registers_8__ap[1]), .QN(), .SE(dftIn), + .SI(registers_4__ap[1]) + ); + SDFF_X1_LVT \registers_reg[28][1] ( + .CK(n_0_58), .D(registers[1]), .Q(registers_28__ap[1]), .QN(), .SE(dftIn), + .SI(registers_25__ap[1]) + ); + AOI221_X1_LVT i_1_0_715( + .A(n_1_0_682), .B1(n_1_0_1282), .B2(registers_8__ap[1]), .C1(registers_28__ap[1]), + .C2(n_1_0_1283), .ZN(n_1_0_681) + ); + SDFF_X1_LVT \registers_reg[18][1] ( + .CK(n_0_48), .D(registers[1]), .Q(registers_18__ap[1]), .QN(), .SE(dftIn), + .SI(registers_20__ap[1]) + ); + SDFF_X1_LVT \registers_reg[30][1] ( + .CK(n_0_60), .D(registers[1]), .Q(registers_30__ap[1]), .QN(), .SE(dftIn), + .SI(registers_28__ap[1]) + ); + AOI22_X1_LVT i_1_0_714( + .A1(registers_18__ap[1]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[1]), + .ZN(n_1_0_680) + ); + SDFF_X1_LVT \registers_reg[17][1] ( + .CK(n_0_47), .D(registers[1]), .Q(registers_17__ap[1]), .QN(), .SE(dftIn), + .SI(registers_18__ap[1]) + ); + SDFF_X1_LVT \registers_reg[12][1] ( + .CK(n_0_42), .D(registers[1]), .Q(registers_12__ap[1]), .QN(), .SE(dftIn), + .SI(registers_10__ap[1]) + ); + AOI22_X1_LVT i_1_0_713( + .A1(registers_17__ap[1]), .A2(n_1_0_1271), .B1(n_1_0_1260), .B2(registers_12__ap[1]), + .ZN(n_1_0_679) + ); + SDFF_X1_LVT \registers_reg[15][1] ( + .CK(n_0_45), .D(registers[1]), .Q(registers_15__ap[1]), .QN(), .SE(dftIn), + .SI(registers_12__ap[1]) + ); + SDFF_X1_LVT \registers_reg[5][1] ( + .CK(n_0_35), .D(registers[1]), .Q(registers_5__ap[1]), .QN(), .SE(dftIn), + .SI(registers_8__ap[1]) + ); + AOI22_X1_LVT i_1_0_712( + .A1(registers_15__ap[1]), .A2(n_1_0_1286), .B1(n_1_0_1273), .B2(registers_5__ap[1]), + .ZN(n_1_0_678) + ); + NAND3_X1_LVT i_1_0_711( + .A1(n_1_0_680), .A2(n_1_0_679), .A3(n_1_0_678), .ZN(n_1_0_677) + ); + SDFF_X1_LVT \registers_reg[22][1] ( + .CK(n_0_52), .D(registers[1]), .Q(registers_22__ap[1]), .QN(), .SE(dftIn), + .SI(registers_17__ap[1]) + ); + SDFF_X1_LVT \registers_reg[16][1] ( + .CK(n_0_46), .D(registers[1]), .Q(registers_16__ap[1]), .QN(), .SE(dftIn), + .SI(registers_15__ap[1]) + ); + AOI221_X1_LVT i_1_0_710( + .A(n_1_0_677), .B1(n_1_0_1294), .B2(registers_22__ap[1]), .C1(registers_16__ap[1]), + .C2(n_1_0_1267), .ZN(n_1_0_676) + ); + SDFF_X1_LVT \registers_reg[9][1] ( + .CK(n_0_39), .D(registers[1]), .Q(registers_9__ap[1]), .QN(), .SE(dftIn), + .SI(registers_5__ap[1]) + ); + SDFF_X1_LVT \registers_reg[1][1] ( + .CK(n_0_0), .D(registers[1]), .Q(registers_1__ap[1]), .QN(), .SE(dftIn), + .SI(registers_22__ap[1]) + ); + AOI22_X1_LVT i_1_0_709( + .A1(registers_9__ap[1]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[1]), + .ZN(n_1_0_675) + ); + SDFF_X1_LVT \registers_reg[6][1] ( + .CK(n_0_36), .D(registers[1]), .Q(registers_6__ap[1]), .QN(), .SE(dftIn), + .SI(registers_9__ap[1]) + ); + SDFF_X1_LVT \registers_reg[14][1] ( + .CK(n_0_44), .D(registers[1]), .Q(registers_14__ap[1]), .QN(), .SE(dftIn), + .SI(registers_16__ap[1]) + ); + AOI22_X1_LVT i_1_0_708( + .A1(registers_6__ap[1]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[1]), + .ZN(n_1_0_674) + ); + SDFF_X1_LVT \registers_reg[19][1] ( + .CK(n_0_49), .D(registers[1]), .Q(registers_19__ap[1]), .QN(), .SE(dftIn), + .SI(registers_1__ap[1]) + ); + SDFF_X1_LVT \registers_reg[2][1] ( + .CK(n_0_32), .D(registers[1]), .Q(registers_2__ap[1]), .QN(), .SE(dftIn), + .SI(registers_30__ap[1]) + ); + AOI22_X1_LVT i_1_0_707( + .A1(registers_19__ap[1]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[1]), + .ZN(n_1_0_673) + ); + NAND3_X1_LVT i_1_0_706( + .A1(n_1_0_675), .A2(n_1_0_674), .A3(n_1_0_673), .ZN(n_1_0_672) + ); + SDFF_X1_LVT \registers_reg[11][1] ( + .CK(n_0_41), .D(registers[1]), .Q(registers_11__ap[1]), .QN(), .SE(dftIn), + .SI(registers_14__ap[1]) + ); + SDFF_X1_LVT \registers_reg[27][1] ( + .CK(n_0_57), .D(registers[1]), .Q(registers_27__ap[1]), .QN(), .SE(dftIn), + .SI(registers_2__ap[1]) + ); + AOI221_X1_LVT i_1_0_705( + .A(n_1_0_672), .B1(n_1_0_1270), .B2(registers_11__ap[1]), .C1(registers_27__ap[1]), + .C2(n_1_0_1279), .ZN(n_1_0_671) + ); + NAND4_X1_LVT i_1_0_704( + .A1(n_1_0_686), .A2(n_1_0_681), .A3(n_1_0_676), .A4(n_1_0_671), .ZN(RRs1[1]) + ); + AND2_X1_LVT i_0_0_0( + .A1(n_0_0_16), .A2(WRd[0]), .ZN(registers[0]) + ); + SDFF_X1_LVT \registers_reg[13][0] ( + .CK(n_0_43), .D(registers[0]), .Q(registers_13__ap[0]), .QN(), .SE(dftIn), + .SI(registers_11__ap[1]) + ); + SDFF_X1_LVT \registers_reg[21][0] ( + .CK(n_0_51), .D(registers[0]), .Q(registers_21__ap[0]), .QN(), .SE(dftIn), + .SI(registers_19__ap[1]) + ); + AOI22_X1_LVT i_1_0_703( + .A1(registers_13__ap[0]), .A2(n_1_0_1277), .B1(n_1_0_1259), .B2(registers_21__ap[0]), + .ZN(n_1_0_670) + ); + SDFF_X1_LVT \registers_reg[10][0] ( + .CK(n_0_40), .D(registers[0]), .Q(registers_10__ap[0]), .QN(), .SE(dftIn), + .SI(registers_13__ap[0]) + ); + SDFF_X1_LVT \registers_reg[26][0] ( + .CK(n_0_56), .D(registers[0]), .Q(registers_26__ap[0]), .QN(), .SE(dftIn), + .SI(registers_27__ap[1]) + ); + SDFF_X1_LVT \registers_reg[25][0] ( + .CK(n_0_55), .D(registers[0]), .Q(registers_25__ap[0]), .QN(), .SE(dftIn), + .SI(registers_26__ap[0]) + ); + AOI222_X1_LVT i_1_0_702( + .A1(registers_10__ap[0]), .A2(n_1_0_1287), .B1(n_1_0_1285), .B2(registers_26__ap[0]), + .C1(registers_25__ap[0]), .C2(n_1_0_1269), .ZN(n_1_0_669) + ); + SDFF_X1_LVT \registers_reg[28][0] ( + .CK(n_0_58), .D(registers[0]), .Q(registers_28__ap[0]), .QN(), .SE(dftIn), + .SI(registers_25__ap[0]) + ); + SDFF_X1_LVT \registers_reg[8][0] ( + .CK(n_0_38), .D(registers[0]), .Q(registers_8__ap[0]), .QN(), .SE(dftIn), + .SI(registers_6__ap[1]) + ); + AOI22_X1_LVT i_1_0_701( + .A1(registers_28__ap[0]), .A2(n_1_0_1283), .B1(n_1_0_1282), .B2(registers_8__ap[0]), + .ZN(n_1_0_668) + ); + SDFF_X1_LVT \registers_reg[24][0] ( + .CK(n_0_54), .D(registers[0]), .Q(registers_24__ap[0]), .QN(), .SE(dftIn), + .SI(registers_28__ap[0]) + ); + SDFF_X1_LVT \registers_reg[20][0] ( + .CK(n_0_50), .D(registers[0]), .Q(registers_20__ap[0]), .QN(), .SE(dftIn), + .SI(registers_21__ap[0]) + ); + AOI22_X1_LVT i_1_0_700( + .A1(registers_24__ap[0]), .A2(n_1_0_1289), .B1(n_1_0_1281), .B2(registers_20__ap[0]), + .ZN(n_1_0_667) + ); + SDFF_X1_LVT \registers_reg[7][0] ( + .CK(n_0_37), .D(registers[0]), .Q(registers_7__ap[0]), .QN(), .SE(dftIn), + .SI(registers_8__ap[0]) + ); + SDFF_X1_LVT \registers_reg[3][0] ( + .CK(n_0_33), .D(registers[0]), .Q(registers_3__ap[0]), .QN(), .SE(dftIn), + .SI(registers_7__ap[0]) + ); + AOI22_X1_LVT i_1_0_699( + .A1(registers_7__ap[0]), .A2(n_1_0_1263), .B1(n_1_0_1257), .B2(registers_3__ap[0]), + .ZN(n_1_0_666) + ); + SDFF_X1_LVT \registers_reg[17][0] ( + .CK(n_0_47), .D(registers[0]), .Q(registers_17__ap[0]), .QN(), .SE(dftIn), + .SI(registers_20__ap[0]) + ); + SDFF_X1_LVT \registers_reg[31][0] ( + .CK(n_0_61), .D(registers[0]), .Q(registers_31__ap[0]), .QN(), .SE(dftIn), + .SI(registers_3__ap[0]) + ); + AOI22_X1_LVT i_1_0_698( + .A1(registers_17__ap[0]), .A2(n_1_0_1271), .B1(n_1_0_1266), .B2(registers_31__ap[0]), + .ZN(n_1_0_665) + ); + SDFF_X1_LVT \registers_reg[29][0] ( + .CK(n_0_59), .D(registers[0]), .Q(registers_29__ap[0]), .QN(), .SE(dftIn), + .SI(registers_24__ap[0]) + ); + SDFF_X1_LVT \registers_reg[23][0] ( + .CK(n_0_53), .D(registers[0]), .Q(registers_23__ap[0]), .QN(), .SE(dftIn), + .SI(registers_17__ap[0]) + ); + AOI22_X1_LVT i_1_0_697( + .A1(registers_29__ap[0]), .A2(n_1_0_1276), .B1(n_1_0_1264), .B2(registers_23__ap[0]), + .ZN(n_1_0_664) + ); + NAND4_X1_LVT i_1_0_696( + .A1(n_1_0_667), .A2(n_1_0_666), .A3(n_1_0_665), .A4(n_1_0_664), .ZN(n_1_0_663) + ); + SDFF_X1_LVT \registers_reg[18][0] ( + .CK(n_0_48), .D(registers[0]), .Q(registers_18__ap[0]), .QN(), .SE(dftIn), + .SI(registers_23__ap[0]) + ); + SDFF_X1_LVT \registers_reg[30][0] ( + .CK(n_0_60), .D(registers[0]), .Q(registers_30__ap[0]), .QN(), .SE(dftIn), + .SI(registers_29__ap[0]) + ); + AOI22_X1_LVT i_1_0_695( + .A1(registers_18__ap[0]), .A2(n_1_0_1297), .B1(n_1_0_1272), .B2(registers_30__ap[0]), + .ZN(n_1_0_662) + ); + SDFF_X1_LVT \registers_reg[4][0] ( + .CK(n_0_34), .D(registers[0]), .Q(registers_4__ap[0]), .QN(), .SE(dftIn), + .SI(registers_31__ap[0]) + ); + SDFF_X1_LVT \registers_reg[12][0] ( + .CK(n_0_42), .D(registers[0]), .Q(registers_12__ap[0]), .QN(), .SE(dftIn), + .SI(registers_10__ap[0]) + ); + AOI22_X1_LVT i_1_0_694( + .A1(registers_4__ap[0]), .A2(n_1_0_1278), .B1(n_1_0_1260), .B2(registers_12__ap[0]), + .ZN(n_1_0_661) + ); + SDFF_X1_LVT \registers_reg[15][0] ( + .CK(n_0_45), .D(registers[0]), .Q(registers_15__ap[0]), .QN(), .SE(dftIn), + .SI(registers_12__ap[0]) + ); + SDFF_X1_LVT \registers_reg[16][0] ( + .CK(n_0_46), .D(registers[0]), .Q(registers_16__ap[0]), .QN(), .SE(dftIn), + .SI(registers_15__ap[0]) + ); + AOI22_X1_LVT i_1_0_693( + .A1(registers_15__ap[0]), .A2(n_1_0_1286), .B1(n_1_0_1267), .B2(registers_16__ap[0]), + .ZN(n_1_0_660) + ); + SDFF_X1_LVT \registers_reg[22][0] ( + .CK(n_0_52), .D(registers[0]), .Q(registers_22__ap[0]), .QN(), .SE(dftIn), + .SI(registers_18__ap[0]) + ); + SDFF_X1_LVT \registers_reg[5][0] ( + .CK(n_0_35), .D(registers[0]), .Q(registers_5__ap[0]), .QN(), .SE(dftIn), + .SI(registers_4__ap[0]) + ); + AOI22_X1_LVT i_1_0_692( + .A1(registers_22__ap[0]), .A2(n_1_0_1294), .B1(n_1_0_1273), .B2(registers_5__ap[0]), + .ZN(n_1_0_659) + ); + NAND4_X1_LVT i_1_0_691( + .A1(n_1_0_662), .A2(n_1_0_661), .A3(n_1_0_660), .A4(n_1_0_659), .ZN(n_1_0_658) + ); + SDFF_X1_LVT \registers_reg[19][0] ( + .CK(n_0_49), .D(registers[0]), .Q(registers_19__ap[0]), .QN(), .SE(dftIn), + .SI(registers_22__ap[0]) + ); + SDFF_X1_LVT \registers_reg[2][0] ( + .CK(n_0_32), .D(registers[0]), .Q(registers_2__ap[0]), .QN(), .SE(dftIn), + .SI(registers_30__ap[0]) + ); + AOI22_X1_LVT i_1_0_690( + .A1(registers_19__ap[0]), .A2(n_1_0_1295), .B1(n_1_0_1268), .B2(registers_2__ap[0]), + .ZN(n_1_0_657) + ); + SDFF_X1_LVT \registers_reg[9][0] ( + .CK(n_0_39), .D(registers[0]), .Q(registers_9__ap[0]), .QN(), .SE(dftIn), + .SI(registers_5__ap[0]) + ); + SDFF_X1_LVT \registers_reg[1][0] ( + .CK(n_0_0), .D(registers[0]), .Q(registers_1__ap[0]), .QN(), .SE(dftIn), + .SI(registers_19__ap[0]) + ); + AOI22_X1_LVT i_1_0_689( + .A1(registers_9__ap[0]), .A2(n_1_0_1291), .B1(n_1_0_1274), .B2(registers_1__ap[0]), + .ZN(n_1_0_656) + ); + SDFF_X1_LVT \registers_reg[6][0] ( + .CK(n_0_36), .D(registers[0]), .Q(registers_6__ap[0]), .QN(), .SE(dftIn), + .SI(registers_9__ap[0]) + ); + SDFF_X1_LVT \registers_reg[14][0] ( + .CK(n_0_44), .D(registers[0]), .Q(registers_14__ap[0]), .QN(), .SE(dftIn), + .SI(registers_16__ap[0]) + ); + AOI22_X1_LVT i_1_0_688( + .A1(registers_6__ap[0]), .A2(n_1_0_1300), .B1(n_1_0_1258), .B2(registers_14__ap[0]), + .ZN(n_1_0_655) + ); + SDFF_X1_LVT \registers_reg[27][0] ( + .CK(n_0_57), .D(registers[0]), .Q(registers_27__ap[0]), .QN(), .SE(dftIn), + .SI(registers_2__ap[0]) + ); + SDFF_X1_LVT \registers_reg[11][0] ( + .CK(n_0_41), .D(registers[0]), .Q(registers_11__ap[0]), .QN(), .SE(dftIn), + .SI(registers_14__ap[0]) + ); + AOI22_X1_LVT i_1_0_687( + .A1(registers_27__ap[0]), .A2(n_1_0_1279), .B1(n_1_0_1270), .B2(registers_11__ap[0]), + .ZN(n_1_0_654) + ); + NAND4_X1_LVT i_1_0_686( + .A1(n_1_0_657), .A2(n_1_0_656), .A3(n_1_0_655), .A4(n_1_0_654), .ZN(n_1_0_653) + ); + NOR3_X1_LVT i_1_0_685( + .A1(n_1_0_663), .A2(n_1_0_658), .A3(n_1_0_653), .ZN(n_1_0_652) + ); + NAND4_X1_LVT i_1_0_684( + .A1(n_1_0_670), .A2(n_1_0_669), .A3(n_1_0_668), .A4(n_1_0_652), .ZN(RRs1[0]) + ); + INV_X1_LVT i_1_0_1366( + .A(Rs2[1]), .ZN(n_1_0_1302) + ); + NAND3_X1_LVT i_1_0_683( + .A1(n_1_0_1302), .A2(Rs2[4]), .A3(Rs2[2]), .ZN(n_1_0_651) + ); + INV_X1_LVT i_1_0_1369( + .A(Rs2[3]), .ZN(n_1_0_1305) + ); + OR2_X1_LVT i_1_0_673( + .A1(n_1_0_1305), .A2(Rs2[0]), .ZN(n_1_0_641) + ); + NOR2_X1_LVT i_1_0_666( + .A1(n_1_0_651), .A2(n_1_0_641), .ZN(n_1_0_634) + ); + NAND2_X1_LVT i_1_0_677( + .A1(n_1_0_1305), .A2(Rs2[0]), .ZN(n_1_0_645) + ); + INV_X1_LVT i_1_0_1368( + .A(Rs2[2]), .ZN(n_1_0_1304) + ); + NAND3_X1_LVT i_1_0_662( + .A1(n_1_0_1304), .A2(n_1_0_1302), .A3(Rs2[4]), .ZN(n_1_0_630) + ); + NOR2_X1_LVT i_1_0_661( + .A1(n_1_0_645), .A2(n_1_0_630), .ZN(n_1_0_629) + ); + AOI22_X1_LVT i_1_0_641( + .A1(registers_28__ap[31]), .A2(n_1_0_634), .B1(n_1_0_629), .B2(registers_17__ap[31]), + .ZN(n_1_0_609) + ); + NAND3_X1_LVT i_1_0_680( + .A1(n_1_0_1304), .A2(Rs2[4]), .A3(Rs2[1]), .ZN(n_1_0_648) + ); + NOR2_X1_LVT i_1_0_672( + .A1(n_1_0_648), .A2(n_1_0_641), .ZN(n_1_0_640) + ); + INV_X1_LVT i_1_0_1367( + .A(Rs2[4]), .ZN(n_1_0_1303) + ); + NAND3_X1_LVT i_1_0_657( + .A1(n_1_0_1304), .A2(n_1_0_1303), .A3(Rs2[1]), .ZN(n_1_0_625) + ); + NOR2_X1_LVT i_1_0_656( + .A1(n_1_0_641), .A2(n_1_0_625), .ZN(n_1_0_624) + ); + NOR4_X1_LVT i_1_0_658( + .A1(n_1_0_641), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), .ZN(n_1_0_626) + ); + AOI222_X1_LVT i_1_0_640( + .A1(registers_26__ap[31]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[31]), + .C1(n_1_0_626), .C2(registers_8__ap[31]), .ZN(n_1_0_608) + ); + NAND2_X1_LVT i_1_0_682( + .A1(Rs2[0]), .A2(Rs2[3]), .ZN(n_1_0_650) + ); + NOR2_X1_LVT i_1_0_681( + .A1(n_1_0_651), .A2(n_1_0_650), .ZN(n_1_0_649) + ); + NOR4_X1_LVT i_1_0_649( + .A1(n_1_0_650), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), .ZN(n_1_0_617) + ); + AOI22_X1_LVT i_1_0_639( + .A1(registers_29__ap[31]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[31]), + .ZN(n_1_0_607) + ); + NOR4_X1_LVT i_1_0_676( + .A1(n_1_0_645), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), .ZN(n_1_0_644) + ); + OR2_X1_LVT i_1_0_679( + .A1(Rs2[0]), .A2(Rs2[3]), .ZN(n_1_0_647) + ); + NAND3_X1_LVT i_1_0_660( + .A1(n_1_0_1303), .A2(Rs2[1]), .A3(Rs2[2]), .ZN(n_1_0_628) + ); + NOR2_X1_LVT i_1_0_648( + .A1(n_1_0_647), .A2(n_1_0_628), .ZN(n_1_0_616) + ); + AOI22_X1_LVT i_1_0_638( + .A1(registers_1__ap[31]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[31]), + .ZN(n_1_0_606) + ); + NOR2_X1_LVT i_1_0_655( + .A1(n_1_0_645), .A2(n_1_0_628), .ZN(n_1_0_623) + ); + NAND3_X1_LVT i_1_0_675( + .A1(Rs2[2]), .A2(Rs2[4]), .A3(Rs2[1]), .ZN(n_1_0_643) + ); + NOR2_X1_LVT i_1_0_647( + .A1(n_1_0_645), .A2(n_1_0_643), .ZN(n_1_0_615) + ); + AOI22_X1_LVT i_1_0_637( + .A1(registers_7__ap[31]), .A2(n_1_0_623), .B1(n_1_0_615), .B2(registers_23__ap[31]), + .ZN(n_1_0_605) + ); + NOR2_X1_LVT i_1_0_665( + .A1(n_1_0_648), .A2(n_1_0_645), .ZN(n_1_0_633) + ); + NOR2_X1_LVT i_1_0_646( + .A1(n_1_0_647), .A2(n_1_0_630), .ZN(n_1_0_614) + ); + AOI22_X1_LVT i_1_0_636( + .A1(registers_19__ap[31]), .A2(n_1_0_633), .B1(n_1_0_614), .B2(registers_16__ap[31]), + .ZN(n_1_0_604) + ); + NOR2_X1_LVT i_1_0_669( + .A1(n_1_0_650), .A2(n_1_0_643), .ZN(n_1_0_637) + ); + NAND3_X1_LVT i_1_0_671( + .A1(n_1_0_1303), .A2(n_1_0_1302), .A3(Rs2[2]), .ZN(n_1_0_639) + ); + NOR2_X1_LVT i_1_0_667( + .A1(n_1_0_645), .A2(n_1_0_639), .ZN(n_1_0_635) + ); + AOI22_X1_LVT i_1_0_635( + .A1(registers_31__ap[31]), .A2(n_1_0_637), .B1(n_1_0_635), .B2(registers_5__ap[31]), + .ZN(n_1_0_603) + ); + NAND4_X1_LVT i_1_0_634( + .A1(n_1_0_606), .A2(n_1_0_605), .A3(n_1_0_604), .A4(n_1_0_603), .ZN(n_1_0_602) + ); + NOR2_X1_LVT i_1_0_678( + .A1(n_1_0_648), .A2(n_1_0_647), .ZN(n_1_0_646) + ); + NOR2_X1_LVT i_1_0_654( + .A1(n_1_0_643), .A2(n_1_0_641), .ZN(n_1_0_622) + ); + AOI22_X1_LVT i_1_0_633( + .A1(registers_18__ap[31]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[31]), + .ZN(n_1_0_601) + ); + NOR2_X1_LVT i_1_0_670( + .A1(n_1_0_647), .A2(n_1_0_639), .ZN(n_1_0_638) + ); + NOR2_X1_LVT i_1_0_645( + .A1(n_1_0_651), .A2(n_1_0_647), .ZN(n_1_0_613) + ); + AOI22_X1_LVT i_1_0_632( + .A1(registers_4__ap[31]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[31]), + .ZN(n_1_0_600) + ); + NOR2_X1_LVT i_1_0_674( + .A1(n_1_0_647), .A2(n_1_0_643), .ZN(n_1_0_642) + ); + NOR2_X1_LVT i_1_0_644( + .A1(n_1_0_651), .A2(n_1_0_645), .ZN(n_1_0_612) + ); + AOI22_X1_LVT i_1_0_631( + .A1(registers_22__ap[31]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[31]), + .ZN(n_1_0_599) + ); + NOR2_X1_LVT i_1_0_664( + .A1(n_1_0_641), .A2(n_1_0_639), .ZN(n_1_0_632) + ); + NOR2_X1_LVT i_1_0_653( + .A1(n_1_0_641), .A2(n_1_0_630), .ZN(n_1_0_621) + ); + AOI22_X1_LVT i_1_0_630( + .A1(registers_12__ap[31]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[31]), + .ZN(n_1_0_598) + ); + NAND4_X1_LVT i_1_0_629( + .A1(n_1_0_601), .A2(n_1_0_600), .A3(n_1_0_599), .A4(n_1_0_598), .ZN(n_1_0_597) + ); + NOR2_X1_LVT i_1_0_663( + .A1(n_1_0_650), .A2(n_1_0_639), .ZN(n_1_0_631) + ); + NOR2_X1_LVT i_1_0_652( + .A1(n_1_0_650), .A2(n_1_0_630), .ZN(n_1_0_620) + ); + AOI22_X1_LVT i_1_0_628( + .A1(registers_13__ap[31]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[31]), + .ZN(n_1_0_596) + ); + NOR2_X1_LVT i_1_0_659( + .A1(n_1_0_650), .A2(n_1_0_628), .ZN(n_1_0_627) + ); + NOR2_X1_LVT i_1_0_651( + .A1(n_1_0_641), .A2(n_1_0_628), .ZN(n_1_0_619) + ); + AOI22_X1_LVT i_1_0_627( + .A1(registers_15__ap[31]), .A2(n_1_0_627), .B1(n_1_0_619), .B2(registers_14__ap[31]), + .ZN(n_1_0_595) + ); + NOR2_X1_LVT i_1_0_668( + .A1(n_1_0_650), .A2(n_1_0_648), .ZN(n_1_0_636) + ); + NOR2_X1_LVT i_1_0_643( + .A1(n_1_0_650), .A2(n_1_0_625), .ZN(n_1_0_611) + ); + AOI22_X1_LVT i_1_0_626( + .A1(registers_27__ap[31]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[31]), + .ZN(n_1_0_594) + ); + NOR2_X1_LVT i_1_0_650( + .A1(n_1_0_647), .A2(n_1_0_625), .ZN(n_1_0_618) + ); + NOR2_X1_LVT i_1_0_642( + .A1(n_1_0_645), .A2(n_1_0_625), .ZN(n_1_0_610) + ); + AOI22_X1_LVT i_1_0_625( + .A1(registers_2__ap[31]), .A2(n_1_0_618), .B1(n_1_0_610), .B2(registers_3__ap[31]), + .ZN(n_1_0_593) + ); + NAND4_X1_LVT i_1_0_624( + .A1(n_1_0_596), .A2(n_1_0_595), .A3(n_1_0_594), .A4(n_1_0_593), .ZN(n_1_0_592) + ); + NOR3_X1_LVT i_1_0_623( + .A1(n_1_0_602), .A2(n_1_0_597), .A3(n_1_0_592), .ZN(n_1_0_591) + ); + NAND4_X1_LVT i_1_0_622( + .A1(n_1_0_609), .A2(n_1_0_608), .A3(n_1_0_607), .A4(n_1_0_591), .ZN(RRs2[31]) + ); + AOI22_X1_LVT i_1_0_620( + .A1(registers_29__ap[30]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[30]), + .ZN(n_1_0_589) + ); + AOI22_X1_LVT i_1_0_621( + .A1(registers_7__ap[30]), .A2(n_1_0_623), .B1(n_1_0_615), .B2(registers_23__ap[30]), + .ZN(n_1_0_590) + ); + AOI22_X1_LVT i_1_0_619( + .A1(registers_1__ap[30]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[30]), + .ZN(n_1_0_588) + ); + AOI22_X1_LVT i_1_0_618( + .A1(registers_5__ap[30]), .A2(n_1_0_635), .B1(n_1_0_633), .B2(registers_19__ap[30]), + .ZN(n_1_0_587) + ); + NAND3_X1_LVT i_1_0_617( + .A1(n_1_0_590), .A2(n_1_0_588), .A3(n_1_0_587), .ZN(n_1_0_586) + ); + AOI221_X1_LVT i_1_0_616( + .A(n_1_0_586), .B1(n_1_0_637), .B2(registers_31__ap[30]), .C1(registers_16__ap[30]), + .C2(n_1_0_614), .ZN(n_1_0_585) + ); + AOI222_X1_LVT i_1_0_615( + .A1(registers_26__ap[30]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[30]), + .C1(n_1_0_626), .C2(registers_8__ap[30]), .ZN(n_1_0_584) + ); + NAND3_X1_LVT i_1_0_614( + .A1(n_1_0_589), .A2(n_1_0_585), .A3(n_1_0_584), .ZN(n_1_0_583) + ); + AOI221_X1_LVT i_1_0_613( + .A(n_1_0_583), .B1(n_1_0_629), .B2(registers_17__ap[30]), .C1(registers_28__ap[30]), + .C2(n_1_0_634), .ZN(n_1_0_582) + ); + AOI22_X1_LVT i_1_0_612( + .A1(registers_18__ap[30]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[30]), + .ZN(n_1_0_581) + ); + AOI22_X1_LVT i_1_0_611( + .A1(registers_4__ap[30]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[30]), + .ZN(n_1_0_580) + ); + AOI22_X1_LVT i_1_0_610( + .A1(registers_22__ap[30]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[30]), + .ZN(n_1_0_579) + ); + NAND3_X1_LVT i_1_0_609( + .A1(n_1_0_581), .A2(n_1_0_580), .A3(n_1_0_579), .ZN(n_1_0_578) + ); + AOI221_X1_LVT i_1_0_608( + .A(n_1_0_578), .B1(n_1_0_621), .B2(registers_24__ap[30]), .C1(registers_12__ap[30]), + .C2(n_1_0_632), .ZN(n_1_0_577) + ); + AOI22_X1_LVT i_1_0_607( + .A1(registers_13__ap[30]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[30]), + .ZN(n_1_0_576) + ); + AOI22_X1_LVT i_1_0_606( + .A1(registers_15__ap[30]), .A2(n_1_0_627), .B1(n_1_0_619), .B2(registers_14__ap[30]), + .ZN(n_1_0_575) + ); + AOI22_X1_LVT i_1_0_605( + .A1(registers_27__ap[30]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[30]), + .ZN(n_1_0_574) + ); + NAND3_X1_LVT i_1_0_604( + .A1(n_1_0_576), .A2(n_1_0_575), .A3(n_1_0_574), .ZN(n_1_0_573) + ); + AOI221_X1_LVT i_1_0_603( + .A(n_1_0_573), .B1(n_1_0_610), .B2(registers_3__ap[30]), .C1(registers_2__ap[30]), + .C2(n_1_0_618), .ZN(n_1_0_572) + ); + NAND3_X1_LVT i_1_0_602( + .A1(n_1_0_582), .A2(n_1_0_577), .A3(n_1_0_572), .ZN(RRs2[30]) + ); + AOI22_X1_LVT i_1_0_600( + .A1(registers_28__ap[29]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[29]), + .ZN(n_1_0_570) + ); + AOI22_X1_LVT i_1_0_601( + .A1(registers_31__ap[29]), .A2(n_1_0_637), .B1(n_1_0_627), .B2(registers_15__ap[29]), + .ZN(n_1_0_571) + ); + AOI22_X1_LVT i_1_0_599( + .A1(registers_24__ap[29]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[29]), + .ZN(n_1_0_569) + ); + AOI22_X1_LVT i_1_0_598( + .A1(registers_19__ap[29]), .A2(n_1_0_633), .B1(n_1_0_629), .B2(registers_17__ap[29]), + .ZN(n_1_0_568) + ); + NAND3_X1_LVT i_1_0_597( + .A1(n_1_0_571), .A2(n_1_0_569), .A3(n_1_0_568), .ZN(n_1_0_567) + ); + AOI221_X1_LVT i_1_0_596( + .A(n_1_0_567), .B1(n_1_0_615), .B2(registers_23__ap[29]), .C1(registers_29__ap[29]), + .C2(n_1_0_649), .ZN(n_1_0_566) + ); + AOI222_X1_LVT i_1_0_595( + .A1(registers_26__ap[29]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[29]), + .C1(n_1_0_620), .C2(registers_25__ap[29]), .ZN(n_1_0_565) + ); + NAND3_X1_LVT i_1_0_594( + .A1(n_1_0_570), .A2(n_1_0_566), .A3(n_1_0_565), .ZN(n_1_0_564) + ); + AOI221_X1_LVT i_1_0_593( + .A(n_1_0_564), .B1(n_1_0_612), .B2(registers_21__ap[29]), .C1(registers_13__ap[29]), + .C2(n_1_0_631), .ZN(n_1_0_563) + ); + AOI22_X1_LVT i_1_0_592( + .A1(registers_18__ap[29]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[29]), + .ZN(n_1_0_562) + ); + AOI22_X1_LVT i_1_0_591( + .A1(registers_4__ap[29]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[29]), + .ZN(n_1_0_561) + ); + AOI22_X1_LVT i_1_0_590( + .A1(registers_7__ap[29]), .A2(n_1_0_623), .B1(n_1_0_614), .B2(registers_16__ap[29]), + .ZN(n_1_0_560) + ); + NAND3_X1_LVT i_1_0_589( + .A1(n_1_0_562), .A2(n_1_0_561), .A3(n_1_0_560), .ZN(n_1_0_559) + ); + AOI221_X1_LVT i_1_0_588( + .A(n_1_0_559), .B1(n_1_0_642), .B2(registers_22__ap[29]), .C1(registers_5__ap[29]), + .C2(n_1_0_635), .ZN(n_1_0_558) + ); + AOI22_X1_LVT i_1_0_587( + .A1(registers_1__ap[29]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[29]), + .ZN(n_1_0_557) + ); + AOI22_X1_LVT i_1_0_586( + .A1(registers_14__ap[29]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[29]), + .ZN(n_1_0_556) + ); + AOI22_X1_LVT i_1_0_585( + .A1(registers_27__ap[29]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[29]), + .ZN(n_1_0_555) + ); + NAND3_X1_LVT i_1_0_584( + .A1(n_1_0_557), .A2(n_1_0_556), .A3(n_1_0_555), .ZN(n_1_0_554) + ); + AOI221_X1_LVT i_1_0_583( + .A(n_1_0_554), .B1(n_1_0_610), .B2(registers_3__ap[29]), .C1(registers_2__ap[29]), + .C2(n_1_0_618), .ZN(n_1_0_553) + ); + NAND3_X1_LVT i_1_0_582( + .A1(n_1_0_563), .A2(n_1_0_558), .A3(n_1_0_553), .ZN(RRs2[29]) + ); + AOI22_X1_LVT i_1_0_581( + .A1(registers_5__ap[28]), .A2(n_1_0_635), .B1(n_1_0_634), .B2(registers_28__ap[28]), + .ZN(n_1_0_552) + ); + AOI222_X1_LVT i_1_0_580( + .A1(registers_26__ap[28]), .A2(n_1_0_640), .B1(n_1_0_633), .B2(registers_19__ap[28]), + .C1(n_1_0_626), .C2(registers_8__ap[28]), .ZN(n_1_0_551) + ); + AOI22_X1_LVT i_1_0_579( + .A1(registers_2__ap[28]), .A2(n_1_0_618), .B1(n_1_0_617), .B2(registers_9__ap[28]), + .ZN(n_1_0_550) + ); + AOI22_X1_LVT i_1_0_578( + .A1(registers_7__ap[28]), .A2(n_1_0_623), .B1(n_1_0_612), .B2(registers_21__ap[28]), + .ZN(n_1_0_549) + ); + AOI22_X1_LVT i_1_0_577( + .A1(registers_16__ap[28]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[28]), + .ZN(n_1_0_548) + ); + AOI22_X1_LVT i_1_0_576( + .A1(registers_31__ap[28]), .A2(n_1_0_637), .B1(n_1_0_619), .B2(registers_14__ap[28]), + .ZN(n_1_0_547) + ); + AOI22_X1_LVT i_1_0_575( + .A1(registers_15__ap[28]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[28]), + .ZN(n_1_0_546) + ); + NAND4_X1_LVT i_1_0_574( + .A1(n_1_0_549), .A2(n_1_0_548), .A3(n_1_0_547), .A4(n_1_0_546), .ZN(n_1_0_545) + ); + AOI22_X1_LVT i_1_0_573( + .A1(registers_22__ap[28]), .A2(n_1_0_642), .B1(n_1_0_622), .B2(registers_30__ap[28]), + .ZN(n_1_0_544) + ); + AOI22_X1_LVT i_1_0_572( + .A1(registers_4__ap[28]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[28]), + .ZN(n_1_0_543) + ); + AOI22_X1_LVT i_1_0_571( + .A1(registers_29__ap[28]), .A2(n_1_0_649), .B1(n_1_0_644), .B2(registers_1__ap[28]), + .ZN(n_1_0_542) + ); + AOI22_X1_LVT i_1_0_570( + .A1(registers_12__ap[28]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[28]), + .ZN(n_1_0_541) + ); + NAND4_X1_LVT i_1_0_569( + .A1(n_1_0_544), .A2(n_1_0_543), .A3(n_1_0_542), .A4(n_1_0_541), .ZN(n_1_0_540) + ); + AOI22_X1_LVT i_1_0_568( + .A1(registers_13__ap[28]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[28]), + .ZN(n_1_0_539) + ); + AOI22_X1_LVT i_1_0_567( + .A1(registers_17__ap[28]), .A2(n_1_0_629), .B1(n_1_0_616), .B2(registers_6__ap[28]), + .ZN(n_1_0_538) + ); + AOI22_X1_LVT i_1_0_566( + .A1(registers_10__ap[28]), .A2(n_1_0_624), .B1(n_1_0_615), .B2(registers_23__ap[28]), + .ZN(n_1_0_537) + ); + AOI22_X1_LVT i_1_0_565( + .A1(registers_18__ap[28]), .A2(n_1_0_646), .B1(n_1_0_636), .B2(registers_27__ap[28]), + .ZN(n_1_0_536) + ); + NAND4_X1_LVT i_1_0_564( + .A1(n_1_0_539), .A2(n_1_0_538), .A3(n_1_0_537), .A4(n_1_0_536), .ZN(n_1_0_535) + ); + NOR3_X1_LVT i_1_0_563( + .A1(n_1_0_545), .A2(n_1_0_540), .A3(n_1_0_535), .ZN(n_1_0_534) + ); + NAND4_X1_LVT i_1_0_562( + .A1(n_1_0_552), .A2(n_1_0_551), .A3(n_1_0_550), .A4(n_1_0_534), .ZN(RRs2[28]) + ); + AOI22_X1_LVT i_1_0_561( + .A1(registers_17__ap[27]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[27]), + .ZN(n_1_0_533) + ); + AOI222_X1_LVT i_1_0_560( + .A1(registers_19__ap[27]), .A2(n_1_0_633), .B1(n_1_0_631), .B2(registers_13__ap[27]), + .C1(registers_30__ap[27]), .C2(n_1_0_622), .ZN(n_1_0_532) + ); + AOI22_X1_LVT i_1_0_559( + .A1(registers_1__ap[27]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[27]), + .ZN(n_1_0_531) + ); + AOI22_X1_LVT i_1_0_558( + .A1(registers_24__ap[27]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[27]), + .ZN(n_1_0_530) + ); + AOI22_X1_LVT i_1_0_557( + .A1(registers_15__ap[27]), .A2(n_1_0_627), .B1(n_1_0_611), .B2(registers_11__ap[27]), + .ZN(n_1_0_529) + ); + AOI22_X1_LVT i_1_0_556( + .A1(registers_4__ap[27]), .A2(n_1_0_638), .B1(n_1_0_636), .B2(registers_27__ap[27]), + .ZN(n_1_0_528) + ); + AOI22_X1_LVT i_1_0_555( + .A1(registers_31__ap[27]), .A2(n_1_0_637), .B1(n_1_0_618), .B2(registers_2__ap[27]), + .ZN(n_1_0_527) + ); + NAND4_X1_LVT i_1_0_554( + .A1(n_1_0_530), .A2(n_1_0_529), .A3(n_1_0_528), .A4(n_1_0_527), .ZN(n_1_0_526) + ); + AOI22_X1_LVT i_1_0_553( + .A1(registers_18__ap[27]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[27]), + .ZN(n_1_0_525) + ); + AOI22_X1_LVT i_1_0_552( + .A1(registers_5__ap[27]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[27]), + .ZN(n_1_0_524) + ); + AOI22_X1_LVT i_1_0_551( + .A1(registers_6__ap[27]), .A2(n_1_0_616), .B1(n_1_0_614), .B2(registers_16__ap[27]), + .ZN(n_1_0_523) + ); + AOI22_X1_LVT i_1_0_550( + .A1(registers_22__ap[27]), .A2(n_1_0_642), .B1(n_1_0_620), .B2(registers_25__ap[27]), + .ZN(n_1_0_522) + ); + NAND4_X1_LVT i_1_0_549( + .A1(n_1_0_525), .A2(n_1_0_524), .A3(n_1_0_523), .A4(n_1_0_522), .ZN(n_1_0_521) + ); + AOI22_X1_LVT i_1_0_548( + .A1(registers_29__ap[27]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[27]), + .ZN(n_1_0_520) + ); + AOI22_X1_LVT i_1_0_547( + .A1(registers_7__ap[27]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[27]), + .ZN(n_1_0_519) + ); + AOI22_X1_LVT i_1_0_546( + .A1(registers_8__ap[27]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[27]), + .ZN(n_1_0_518) + ); + AOI22_X1_LVT i_1_0_545( + .A1(registers_10__ap[27]), .A2(n_1_0_624), .B1(n_1_0_610), .B2(registers_3__ap[27]), + .ZN(n_1_0_517) + ); + NAND4_X1_LVT i_1_0_544( + .A1(n_1_0_520), .A2(n_1_0_519), .A3(n_1_0_518), .A4(n_1_0_517), .ZN(n_1_0_516) + ); + NOR3_X1_LVT i_1_0_543( + .A1(n_1_0_526), .A2(n_1_0_521), .A3(n_1_0_516), .ZN(n_1_0_515) + ); + NAND4_X1_LVT i_1_0_542( + .A1(n_1_0_533), .A2(n_1_0_532), .A3(n_1_0_531), .A4(n_1_0_515), .ZN(RRs2[27]) + ); + AOI22_X1_LVT i_1_0_541( + .A1(registers_17__ap[26]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[26]), + .ZN(n_1_0_514) + ); + AOI222_X1_LVT i_1_0_540( + .A1(registers_19__ap[26]), .A2(n_1_0_633), .B1(n_1_0_622), .B2(registers_30__ap[26]), + .C1(n_1_0_631), .C2(registers_13__ap[26]), .ZN(n_1_0_513) + ); + AOI22_X1_LVT i_1_0_539( + .A1(registers_1__ap[26]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[26]), + .ZN(n_1_0_512) + ); + AOI22_X1_LVT i_1_0_538( + .A1(registers_24__ap[26]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[26]), + .ZN(n_1_0_511) + ); + AOI22_X1_LVT i_1_0_537( + .A1(registers_15__ap[26]), .A2(n_1_0_627), .B1(n_1_0_611), .B2(registers_11__ap[26]), + .ZN(n_1_0_510) + ); + AOI22_X1_LVT i_1_0_536( + .A1(registers_4__ap[26]), .A2(n_1_0_638), .B1(n_1_0_636), .B2(registers_27__ap[26]), + .ZN(n_1_0_509) + ); + AOI22_X1_LVT i_1_0_535( + .A1(registers_31__ap[26]), .A2(n_1_0_637), .B1(n_1_0_618), .B2(registers_2__ap[26]), + .ZN(n_1_0_508) + ); + NAND4_X1_LVT i_1_0_534( + .A1(n_1_0_511), .A2(n_1_0_510), .A3(n_1_0_509), .A4(n_1_0_508), .ZN(n_1_0_507) + ); + AOI22_X1_LVT i_1_0_533( + .A1(registers_18__ap[26]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[26]), + .ZN(n_1_0_506) + ); + AOI22_X1_LVT i_1_0_532( + .A1(registers_5__ap[26]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[26]), + .ZN(n_1_0_505) + ); + AOI22_X1_LVT i_1_0_531( + .A1(registers_6__ap[26]), .A2(n_1_0_616), .B1(n_1_0_614), .B2(registers_16__ap[26]), + .ZN(n_1_0_504) + ); + AOI22_X1_LVT i_1_0_530( + .A1(registers_22__ap[26]), .A2(n_1_0_642), .B1(n_1_0_620), .B2(registers_25__ap[26]), + .ZN(n_1_0_503) + ); + NAND4_X1_LVT i_1_0_529( + .A1(n_1_0_506), .A2(n_1_0_505), .A3(n_1_0_504), .A4(n_1_0_503), .ZN(n_1_0_502) + ); + AOI22_X1_LVT i_1_0_528( + .A1(registers_29__ap[26]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[26]), + .ZN(n_1_0_501) + ); + AOI22_X1_LVT i_1_0_527( + .A1(registers_7__ap[26]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[26]), + .ZN(n_1_0_500) + ); + AOI22_X1_LVT i_1_0_526( + .A1(registers_8__ap[26]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[26]), + .ZN(n_1_0_499) + ); + AOI22_X1_LVT i_1_0_525( + .A1(registers_10__ap[26]), .A2(n_1_0_624), .B1(n_1_0_610), .B2(registers_3__ap[26]), + .ZN(n_1_0_498) + ); + NAND4_X1_LVT i_1_0_524( + .A1(n_1_0_501), .A2(n_1_0_500), .A3(n_1_0_499), .A4(n_1_0_498), .ZN(n_1_0_497) + ); + NOR3_X1_LVT i_1_0_523( + .A1(n_1_0_507), .A2(n_1_0_502), .A3(n_1_0_497), .ZN(n_1_0_496) + ); + NAND4_X1_LVT i_1_0_522( + .A1(n_1_0_514), .A2(n_1_0_513), .A3(n_1_0_512), .A4(n_1_0_496), .ZN(RRs2[26]) + ); + AOI22_X1_LVT i_1_0_520( + .A1(registers_5__ap[25]), .A2(n_1_0_635), .B1(n_1_0_634), .B2(registers_28__ap[25]), + .ZN(n_1_0_494) + ); + AOI22_X1_LVT i_1_0_521( + .A1(registers_8__ap[25]), .A2(n_1_0_626), .B1(n_1_0_620), .B2(registers_25__ap[25]), + .ZN(n_1_0_495) + ); + AOI22_X1_LVT i_1_0_519( + .A1(registers_14__ap[25]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[25]), + .ZN(n_1_0_493) + ); + AOI22_X1_LVT i_1_0_518( + .A1(registers_16__ap[25]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[25]), + .ZN(n_1_0_492) + ); + NAND3_X1_LVT i_1_0_517( + .A1(n_1_0_495), .A2(n_1_0_493), .A3(n_1_0_492), .ZN(n_1_0_491) + ); + AOI221_X1_LVT i_1_0_516( + .A(n_1_0_491), .B1(n_1_0_624), .B2(registers_10__ap[25]), .C1(registers_6__ap[25]), + .C2(n_1_0_616), .ZN(n_1_0_490) + ); + AOI222_X1_LVT i_1_0_515( + .A1(registers_1__ap[25]), .A2(n_1_0_644), .B1(n_1_0_640), .B2(registers_26__ap[25]), + .C1(n_1_0_622), .C2(registers_30__ap[25]), .ZN(n_1_0_489) + ); + NAND2_X1_LVT i_1_0_514( + .A1(n_1_0_490), .A2(n_1_0_489), .ZN(n_1_0_488) + ); + AOI221_X1_LVT i_1_0_513( + .A(n_1_0_488), .B1(n_1_0_649), .B2(registers_29__ap[25]), .C1(registers_2__ap[25]), + .C2(n_1_0_618), .ZN(n_1_0_487) + ); + AOI22_X1_LVT i_1_0_512( + .A1(registers_12__ap[25]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[25]), + .ZN(n_1_0_486) + ); + AOI22_X1_LVT i_1_0_511( + .A1(registers_22__ap[25]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[25]), + .ZN(n_1_0_485) + ); + AOI22_X1_LVT i_1_0_510( + .A1(registers_4__ap[25]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[25]), + .ZN(n_1_0_484) + ); + NAND3_X1_LVT i_1_0_509( + .A1(n_1_0_486), .A2(n_1_0_485), .A3(n_1_0_484), .ZN(n_1_0_483) + ); + AOI221_X1_LVT i_1_0_508( + .A(n_1_0_483), .B1(n_1_0_633), .B2(registers_19__ap[25]), .C1(registers_18__ap[25]), + .C2(n_1_0_646), .ZN(n_1_0_482) + ); + AOI22_X1_LVT i_1_0_507( + .A1(registers_15__ap[25]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[25]), + .ZN(n_1_0_481) + ); + AOI22_X1_LVT i_1_0_506( + .A1(registers_23__ap[25]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[25]), + .ZN(n_1_0_480) + ); + AOI22_X1_LVT i_1_0_505( + .A1(registers_13__ap[25]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[25]), + .ZN(n_1_0_479) + ); + NAND3_X1_LVT i_1_0_504( + .A1(n_1_0_481), .A2(n_1_0_480), .A3(n_1_0_479), .ZN(n_1_0_478) + ); + AOI221_X1_LVT i_1_0_503( + .A(n_1_0_478), .B1(n_1_0_636), .B2(registers_27__ap[25]), .C1(registers_31__ap[25]), + .C2(n_1_0_637), .ZN(n_1_0_477) + ); + NAND4_X1_LVT i_1_0_502( + .A1(n_1_0_494), .A2(n_1_0_487), .A3(n_1_0_482), .A4(n_1_0_477), .ZN(RRs2[25]) + ); + AOI22_X1_LVT i_1_0_501( + .A1(registers_17__ap[24]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[24]), + .ZN(n_1_0_476) + ); + AOI222_X1_LVT i_1_0_500( + .A1(registers_13__ap[24]), .A2(n_1_0_631), .B1(n_1_0_622), .B2(registers_30__ap[24]), + .C1(registers_26__ap[24]), .C2(n_1_0_640), .ZN(n_1_0_475) + ); + AOI22_X1_LVT i_1_0_499( + .A1(registers_1__ap[24]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[24]), + .ZN(n_1_0_474) + ); + AOI22_X1_LVT i_1_0_498( + .A1(registers_24__ap[24]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[24]), + .ZN(n_1_0_473) + ); + AOI22_X1_LVT i_1_0_497( + .A1(registers_8__ap[24]), .A2(n_1_0_626), .B1(n_1_0_616), .B2(registers_6__ap[24]), + .ZN(n_1_0_472) + ); + AOI22_X1_LVT i_1_0_496( + .A1(registers_4__ap[24]), .A2(n_1_0_638), .B1(n_1_0_611), .B2(registers_11__ap[24]), + .ZN(n_1_0_471) + ); + AOI22_X1_LVT i_1_0_495( + .A1(registers_10__ap[24]), .A2(n_1_0_624), .B1(n_1_0_618), .B2(registers_2__ap[24]), + .ZN(n_1_0_470) + ); + NAND4_X1_LVT i_1_0_494( + .A1(n_1_0_473), .A2(n_1_0_472), .A3(n_1_0_471), .A4(n_1_0_470), .ZN(n_1_0_469) + ); + AOI22_X1_LVT i_1_0_493( + .A1(registers_18__ap[24]), .A2(n_1_0_646), .B1(n_1_0_633), .B2(registers_19__ap[24]), + .ZN(n_1_0_468) + ); + AOI22_X1_LVT i_1_0_492( + .A1(registers_5__ap[24]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[24]), + .ZN(n_1_0_467) + ); + AOI22_X1_LVT i_1_0_491( + .A1(registers_15__ap[24]), .A2(n_1_0_627), .B1(n_1_0_614), .B2(registers_16__ap[24]), + .ZN(n_1_0_466) + ); + AOI22_X1_LVT i_1_0_490( + .A1(registers_22__ap[24]), .A2(n_1_0_642), .B1(n_1_0_620), .B2(registers_25__ap[24]), + .ZN(n_1_0_465) + ); + NAND4_X1_LVT i_1_0_489( + .A1(n_1_0_468), .A2(n_1_0_467), .A3(n_1_0_466), .A4(n_1_0_465), .ZN(n_1_0_464) + ); + AOI22_X1_LVT i_1_0_488( + .A1(registers_29__ap[24]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[24]), + .ZN(n_1_0_463) + ); + AOI22_X1_LVT i_1_0_487( + .A1(registers_7__ap[24]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[24]), + .ZN(n_1_0_462) + ); + AOI22_X1_LVT i_1_0_486( + .A1(registers_23__ap[24]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[24]), + .ZN(n_1_0_461) + ); + AOI22_X1_LVT i_1_0_485( + .A1(registers_31__ap[24]), .A2(n_1_0_637), .B1(n_1_0_636), .B2(registers_27__ap[24]), + .ZN(n_1_0_460) + ); + NAND4_X1_LVT i_1_0_484( + .A1(n_1_0_463), .A2(n_1_0_462), .A3(n_1_0_461), .A4(n_1_0_460), .ZN(n_1_0_459) + ); + NOR3_X1_LVT i_1_0_483( + .A1(n_1_0_469), .A2(n_1_0_464), .A3(n_1_0_459), .ZN(n_1_0_458) + ); + NAND4_X1_LVT i_1_0_482( + .A1(n_1_0_476), .A2(n_1_0_475), .A3(n_1_0_474), .A4(n_1_0_458), .ZN(RRs2[24]) + ); + AOI22_X1_LVT i_1_0_481( + .A1(registers_4__ap[23]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[23]), + .ZN(n_1_0_457) + ); + AOI222_X1_LVT i_1_0_480( + .A1(registers_18__ap[23]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[23]), + .C1(n_1_0_644), .C2(registers_1__ap[23]), .ZN(n_1_0_456) + ); + AOI22_X1_LVT i_1_0_479( + .A1(registers_29__ap[23]), .A2(n_1_0_649), .B1(n_1_0_618), .B2(registers_2__ap[23]), + .ZN(n_1_0_455) + ); + AOI22_X1_LVT i_1_0_478( + .A1(registers_14__ap[23]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[23]), + .ZN(n_1_0_454) + ); + AOI22_X1_LVT i_1_0_477( + .A1(registers_16__ap[23]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[23]), + .ZN(n_1_0_453) + ); + AOI22_X1_LVT i_1_0_476( + .A1(registers_27__ap[23]), .A2(n_1_0_636), .B1(n_1_0_620), .B2(registers_25__ap[23]), + .ZN(n_1_0_452) + ); + AOI22_X1_LVT i_1_0_475( + .A1(registers_31__ap[23]), .A2(n_1_0_637), .B1(n_1_0_616), .B2(registers_6__ap[23]), + .ZN(n_1_0_451) + ); + NAND4_X1_LVT i_1_0_474( + .A1(n_1_0_454), .A2(n_1_0_453), .A3(n_1_0_452), .A4(n_1_0_451), .ZN(n_1_0_450) + ); + AOI22_X1_LVT i_1_0_473( + .A1(registers_26__ap[23]), .A2(n_1_0_640), .B1(n_1_0_633), .B2(registers_19__ap[23]), + .ZN(n_1_0_449) + ); + AOI22_X1_LVT i_1_0_472( + .A1(registers_12__ap[23]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[23]), + .ZN(n_1_0_448) + ); + AOI22_X1_LVT i_1_0_471( + .A1(registers_22__ap[23]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[23]), + .ZN(n_1_0_447) + ); + AOI22_X1_LVT i_1_0_470( + .A1(registers_5__ap[23]), .A2(n_1_0_635), .B1(n_1_0_613), .B2(registers_20__ap[23]), + .ZN(n_1_0_446) + ); + NAND4_X1_LVT i_1_0_469( + .A1(n_1_0_449), .A2(n_1_0_448), .A3(n_1_0_447), .A4(n_1_0_446), .ZN(n_1_0_445) + ); + AOI22_X1_LVT i_1_0_468( + .A1(registers_15__ap[23]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[23]), + .ZN(n_1_0_444) + ); + AOI22_X1_LVT i_1_0_467( + .A1(registers_8__ap[23]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[23]), + .ZN(n_1_0_443) + ); + AOI22_X1_LVT i_1_0_466( + .A1(registers_13__ap[23]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[23]), + .ZN(n_1_0_442) + ); + AOI22_X1_LVT i_1_0_465( + .A1(registers_10__ap[23]), .A2(n_1_0_624), .B1(n_1_0_610), .B2(registers_3__ap[23]), + .ZN(n_1_0_441) + ); + NAND4_X1_LVT i_1_0_464( + .A1(n_1_0_444), .A2(n_1_0_443), .A3(n_1_0_442), .A4(n_1_0_441), .ZN(n_1_0_440) + ); + NOR3_X1_LVT i_1_0_463( + .A1(n_1_0_450), .A2(n_1_0_445), .A3(n_1_0_440), .ZN(n_1_0_439) + ); + NAND4_X1_LVT i_1_0_462( + .A1(n_1_0_457), .A2(n_1_0_456), .A3(n_1_0_455), .A4(n_1_0_439), .ZN(RRs2[23]) + ); + AOI22_X1_LVT i_1_0_460( + .A1(registers_17__ap[22]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[22]), + .ZN(n_1_0_437) + ); + AOI22_X1_LVT i_1_0_461( + .A1(registers_15__ap[22]), .A2(n_1_0_627), .B1(n_1_0_626), .B2(registers_8__ap[22]), + .ZN(n_1_0_438) + ); + AOI22_X1_LVT i_1_0_459( + .A1(registers_24__ap[22]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[22]), + .ZN(n_1_0_436) + ); + AOI22_X1_LVT i_1_0_458( + .A1(registers_5__ap[22]), .A2(n_1_0_635), .B1(n_1_0_611), .B2(registers_11__ap[22]), + .ZN(n_1_0_435) + ); + NAND3_X1_LVT i_1_0_457( + .A1(n_1_0_438), .A2(n_1_0_436), .A3(n_1_0_435), .ZN(n_1_0_434) + ); + AOI221_X1_LVT i_1_0_456( + .A(n_1_0_434), .B1(n_1_0_618), .B2(registers_2__ap[22]), .C1(registers_10__ap[22]), + .C2(n_1_0_624), .ZN(n_1_0_433) + ); + AOI222_X1_LVT i_1_0_455( + .A1(registers_26__ap[22]), .A2(n_1_0_640), .B1(n_1_0_622), .B2(registers_30__ap[22]), + .C1(n_1_0_631), .C2(registers_13__ap[22]), .ZN(n_1_0_432) + ); + NAND2_X1_LVT i_1_0_454( + .A1(n_1_0_433), .A2(n_1_0_432), .ZN(n_1_0_431) + ); + AOI221_X1_LVT i_1_0_453( + .A(n_1_0_431), .B1(n_1_0_644), .B2(registers_1__ap[22]), .C1(registers_28__ap[22]), + .C2(n_1_0_634), .ZN(n_1_0_430) + ); + AOI22_X1_LVT i_1_0_452( + .A1(registers_18__ap[22]), .A2(n_1_0_646), .B1(n_1_0_633), .B2(registers_19__ap[22]), + .ZN(n_1_0_429) + ); + AOI22_X1_LVT i_1_0_451( + .A1(registers_4__ap[22]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[22]), + .ZN(n_1_0_428) + ); + AOI22_X1_LVT i_1_0_450( + .A1(registers_6__ap[22]), .A2(n_1_0_616), .B1(n_1_0_614), .B2(registers_16__ap[22]), + .ZN(n_1_0_427) + ); + NAND3_X1_LVT i_1_0_449( + .A1(n_1_0_429), .A2(n_1_0_428), .A3(n_1_0_427), .ZN(n_1_0_426) + ); + AOI221_X1_LVT i_1_0_448( + .A(n_1_0_426), .B1(n_1_0_620), .B2(registers_25__ap[22]), .C1(registers_22__ap[22]), + .C2(n_1_0_642), .ZN(n_1_0_425) + ); + AOI22_X1_LVT i_1_0_447( + .A1(registers_29__ap[22]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[22]), + .ZN(n_1_0_424) + ); + AOI22_X1_LVT i_1_0_446( + .A1(registers_7__ap[22]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[22]), + .ZN(n_1_0_423) + ); + AOI22_X1_LVT i_1_0_445( + .A1(registers_23__ap[22]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[22]), + .ZN(n_1_0_422) + ); + NAND3_X1_LVT i_1_0_444( + .A1(n_1_0_424), .A2(n_1_0_423), .A3(n_1_0_422), .ZN(n_1_0_421) + ); + AOI221_X1_LVT i_1_0_443( + .A(n_1_0_421), .B1(n_1_0_636), .B2(registers_27__ap[22]), .C1(registers_31__ap[22]), + .C2(n_1_0_637), .ZN(n_1_0_420) + ); + NAND4_X1_LVT i_1_0_442( + .A1(n_1_0_437), .A2(n_1_0_430), .A3(n_1_0_425), .A4(n_1_0_420), .ZN(RRs2[22]) + ); + AOI22_X1_LVT i_1_0_441( + .A1(registers_5__ap[21]), .A2(n_1_0_635), .B1(n_1_0_634), .B2(registers_28__ap[21]), + .ZN(n_1_0_419) + ); + AOI222_X1_LVT i_1_0_440( + .A1(registers_1__ap[21]), .A2(n_1_0_644), .B1(n_1_0_640), .B2(registers_26__ap[21]), + .C1(n_1_0_622), .C2(registers_30__ap[21]), .ZN(n_1_0_418) + ); + AOI22_X1_LVT i_1_0_439( + .A1(registers_29__ap[21]), .A2(n_1_0_649), .B1(n_1_0_618), .B2(registers_2__ap[21]), + .ZN(n_1_0_417) + ); + AOI22_X1_LVT i_1_0_438( + .A1(registers_14__ap[21]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[21]), + .ZN(n_1_0_416) + ); + AOI22_X1_LVT i_1_0_437( + .A1(registers_8__ap[21]), .A2(n_1_0_626), .B1(n_1_0_614), .B2(registers_16__ap[21]), + .ZN(n_1_0_415) + ); + AOI22_X1_LVT i_1_0_436( + .A1(registers_25__ap[21]), .A2(n_1_0_620), .B1(n_1_0_611), .B2(registers_11__ap[21]), + .ZN(n_1_0_414) + ); + AOI22_X1_LVT i_1_0_435( + .A1(registers_10__ap[21]), .A2(n_1_0_624), .B1(n_1_0_616), .B2(registers_6__ap[21]), + .ZN(n_1_0_413) + ); + NAND4_X1_LVT i_1_0_434( + .A1(n_1_0_416), .A2(n_1_0_415), .A3(n_1_0_414), .A4(n_1_0_413), .ZN(n_1_0_412) + ); + AOI22_X1_LVT i_1_0_433( + .A1(registers_12__ap[21]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[21]), + .ZN(n_1_0_411) + ); + AOI22_X1_LVT i_1_0_432( + .A1(registers_22__ap[21]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[21]), + .ZN(n_1_0_410) + ); + AOI22_X1_LVT i_1_0_431( + .A1(registers_4__ap[21]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[21]), + .ZN(n_1_0_409) + ); + AOI22_X1_LVT i_1_0_430( + .A1(registers_18__ap[21]), .A2(n_1_0_646), .B1(n_1_0_633), .B2(registers_19__ap[21]), + .ZN(n_1_0_408) + ); + NAND4_X1_LVT i_1_0_429( + .A1(n_1_0_411), .A2(n_1_0_410), .A3(n_1_0_409), .A4(n_1_0_408), .ZN(n_1_0_407) + ); + AOI22_X1_LVT i_1_0_428( + .A1(registers_15__ap[21]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[21]), + .ZN(n_1_0_406) + ); + AOI22_X1_LVT i_1_0_427( + .A1(registers_23__ap[21]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[21]), + .ZN(n_1_0_405) + ); + AOI22_X1_LVT i_1_0_426( + .A1(registers_13__ap[21]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[21]), + .ZN(n_1_0_404) + ); + AOI22_X1_LVT i_1_0_425( + .A1(registers_31__ap[21]), .A2(n_1_0_637), .B1(n_1_0_636), .B2(registers_27__ap[21]), + .ZN(n_1_0_403) + ); + NAND4_X1_LVT i_1_0_424( + .A1(n_1_0_406), .A2(n_1_0_405), .A3(n_1_0_404), .A4(n_1_0_403), .ZN(n_1_0_402) + ); + NOR3_X1_LVT i_1_0_423( + .A1(n_1_0_412), .A2(n_1_0_407), .A3(n_1_0_402), .ZN(n_1_0_401) + ); + NAND4_X1_LVT i_1_0_422( + .A1(n_1_0_419), .A2(n_1_0_418), .A3(n_1_0_417), .A4(n_1_0_401), .ZN(RRs2[21]) + ); + AOI22_X1_LVT i_1_0_421( + .A1(registers_17__ap[20]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[20]), + .ZN(n_1_0_400) + ); + AOI222_X1_LVT i_1_0_420( + .A1(registers_13__ap[20]), .A2(n_1_0_631), .B1(n_1_0_622), .B2(registers_30__ap[20]), + .C1(registers_19__ap[20]), .C2(n_1_0_633), .ZN(n_1_0_399) + ); + AOI22_X1_LVT i_1_0_419( + .A1(registers_1__ap[20]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[20]), + .ZN(n_1_0_398) + ); + AOI22_X1_LVT i_1_0_418( + .A1(registers_24__ap[20]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[20]), + .ZN(n_1_0_397) + ); + AOI22_X1_LVT i_1_0_417( + .A1(registers_6__ap[20]), .A2(n_1_0_616), .B1(n_1_0_611), .B2(registers_11__ap[20]), + .ZN(n_1_0_396) + ); + AOI22_X1_LVT i_1_0_416( + .A1(registers_4__ap[20]), .A2(n_1_0_638), .B1(n_1_0_624), .B2(registers_10__ap[20]), + .ZN(n_1_0_395) + ); + AOI22_X1_LVT i_1_0_415( + .A1(registers_31__ap[20]), .A2(n_1_0_637), .B1(n_1_0_618), .B2(registers_2__ap[20]), + .ZN(n_1_0_394) + ); + NAND4_X1_LVT i_1_0_414( + .A1(n_1_0_397), .A2(n_1_0_396), .A3(n_1_0_395), .A4(n_1_0_394), .ZN(n_1_0_393) + ); + AOI22_X1_LVT i_1_0_413( + .A1(registers_18__ap[20]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[20]), + .ZN(n_1_0_392) + ); + AOI22_X1_LVT i_1_0_412( + .A1(registers_5__ap[20]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[20]), + .ZN(n_1_0_391) + ); + AOI22_X1_LVT i_1_0_411( + .A1(registers_15__ap[20]), .A2(n_1_0_627), .B1(n_1_0_614), .B2(registers_16__ap[20]), + .ZN(n_1_0_390) + ); + AOI22_X1_LVT i_1_0_410( + .A1(registers_22__ap[20]), .A2(n_1_0_642), .B1(n_1_0_620), .B2(registers_25__ap[20]), + .ZN(n_1_0_389) + ); + NAND4_X1_LVT i_1_0_409( + .A1(n_1_0_392), .A2(n_1_0_391), .A3(n_1_0_390), .A4(n_1_0_389), .ZN(n_1_0_388) + ); + AOI22_X1_LVT i_1_0_408( + .A1(registers_29__ap[20]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[20]), + .ZN(n_1_0_387) + ); + AOI22_X1_LVT i_1_0_407( + .A1(registers_7__ap[20]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[20]), + .ZN(n_1_0_386) + ); + AOI22_X1_LVT i_1_0_406( + .A1(registers_8__ap[20]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[20]), + .ZN(n_1_0_385) + ); + AOI22_X1_LVT i_1_0_405( + .A1(registers_27__ap[20]), .A2(n_1_0_636), .B1(n_1_0_610), .B2(registers_3__ap[20]), + .ZN(n_1_0_384) + ); + NAND4_X1_LVT i_1_0_404( + .A1(n_1_0_387), .A2(n_1_0_386), .A3(n_1_0_385), .A4(n_1_0_384), .ZN(n_1_0_383) + ); + NOR3_X1_LVT i_1_0_403( + .A1(n_1_0_393), .A2(n_1_0_388), .A3(n_1_0_383), .ZN(n_1_0_382) + ); + NAND4_X1_LVT i_1_0_402( + .A1(n_1_0_400), .A2(n_1_0_399), .A3(n_1_0_398), .A4(n_1_0_382), .ZN(RRs2[20]) + ); + AOI22_X1_LVT i_1_0_401( + .A1(registers_17__ap[19]), .A2(n_1_0_629), .B1(n_1_0_612), .B2(registers_21__ap[19]), + .ZN(n_1_0_381) + ); + AOI222_X1_LVT i_1_0_400( + .A1(registers_13__ap[19]), .A2(n_1_0_631), .B1(n_1_0_622), .B2(registers_30__ap[19]), + .C1(registers_19__ap[19]), .C2(n_1_0_633), .ZN(n_1_0_380) + ); + AOI22_X1_LVT i_1_0_399( + .A1(registers_1__ap[19]), .A2(n_1_0_644), .B1(n_1_0_634), .B2(registers_28__ap[19]), + .ZN(n_1_0_379) + ); + AOI22_X1_LVT i_1_0_398( + .A1(registers_24__ap[19]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[19]), + .ZN(n_1_0_378) + ); + AOI22_X1_LVT i_1_0_397( + .A1(registers_15__ap[19]), .A2(n_1_0_627), .B1(n_1_0_611), .B2(registers_11__ap[19]), + .ZN(n_1_0_377) + ); + AOI22_X1_LVT i_1_0_396( + .A1(registers_4__ap[19]), .A2(n_1_0_638), .B1(n_1_0_636), .B2(registers_27__ap[19]), + .ZN(n_1_0_376) + ); + AOI22_X1_LVT i_1_0_395( + .A1(registers_31__ap[19]), .A2(n_1_0_637), .B1(n_1_0_618), .B2(registers_2__ap[19]), + .ZN(n_1_0_375) + ); + NAND4_X1_LVT i_1_0_394( + .A1(n_1_0_378), .A2(n_1_0_377), .A3(n_1_0_376), .A4(n_1_0_375), .ZN(n_1_0_374) + ); + AOI22_X1_LVT i_1_0_393( + .A1(registers_18__ap[19]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[19]), + .ZN(n_1_0_373) + ); + AOI22_X1_LVT i_1_0_392( + .A1(registers_5__ap[19]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[19]), + .ZN(n_1_0_372) + ); + AOI22_X1_LVT i_1_0_391( + .A1(registers_25__ap[19]), .A2(n_1_0_620), .B1(n_1_0_616), .B2(registers_6__ap[19]), + .ZN(n_1_0_371) + ); + AOI22_X1_LVT i_1_0_390( + .A1(registers_22__ap[19]), .A2(n_1_0_642), .B1(n_1_0_614), .B2(registers_16__ap[19]), + .ZN(n_1_0_370) + ); + NAND4_X1_LVT i_1_0_389( + .A1(n_1_0_373), .A2(n_1_0_372), .A3(n_1_0_371), .A4(n_1_0_370), .ZN(n_1_0_369) + ); + AOI22_X1_LVT i_1_0_388( + .A1(registers_29__ap[19]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[19]), + .ZN(n_1_0_368) + ); + AOI22_X1_LVT i_1_0_387( + .A1(registers_7__ap[19]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[19]), + .ZN(n_1_0_367) + ); + AOI22_X1_LVT i_1_0_386( + .A1(registers_8__ap[19]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[19]), + .ZN(n_1_0_366) + ); + AOI22_X1_LVT i_1_0_385( + .A1(registers_10__ap[19]), .A2(n_1_0_624), .B1(n_1_0_610), .B2(registers_3__ap[19]), + .ZN(n_1_0_365) + ); + NAND4_X1_LVT i_1_0_384( + .A1(n_1_0_368), .A2(n_1_0_367), .A3(n_1_0_366), .A4(n_1_0_365), .ZN(n_1_0_364) + ); + NOR3_X1_LVT i_1_0_383( + .A1(n_1_0_374), .A2(n_1_0_369), .A3(n_1_0_364), .ZN(n_1_0_363) + ); + NAND4_X1_LVT i_1_0_382( + .A1(n_1_0_381), .A2(n_1_0_380), .A3(n_1_0_379), .A4(n_1_0_363), .ZN(RRs2[19]) + ); + AOI22_X1_LVT i_1_0_380( + .A1(registers_4__ap[18]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[18]), + .ZN(n_1_0_361) + ); + AOI22_X1_LVT i_1_0_381( + .A1(registers_8__ap[18]), .A2(n_1_0_626), .B1(n_1_0_614), .B2(registers_16__ap[18]), + .ZN(n_1_0_362) + ); + AOI22_X1_LVT i_1_0_379( + .A1(registers_14__ap[18]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[18]), + .ZN(n_1_0_360) + ); + AOI22_X1_LVT i_1_0_378( + .A1(registers_25__ap[18]), .A2(n_1_0_620), .B1(n_1_0_611), .B2(registers_11__ap[18]), + .ZN(n_1_0_359) + ); + NAND3_X1_LVT i_1_0_377( + .A1(n_1_0_362), .A2(n_1_0_360), .A3(n_1_0_359), .ZN(n_1_0_358) + ); + AOI221_X1_LVT i_1_0_376( + .A(n_1_0_358), .B1(n_1_0_624), .B2(registers_10__ap[18]), .C1(registers_6__ap[18]), + .C2(n_1_0_616), .ZN(n_1_0_357) + ); + AOI222_X1_LVT i_1_0_375( + .A1(registers_1__ap[18]), .A2(n_1_0_644), .B1(n_1_0_640), .B2(registers_26__ap[18]), + .C1(n_1_0_622), .C2(registers_30__ap[18]), .ZN(n_1_0_356) + ); + NAND2_X1_LVT i_1_0_374( + .A1(n_1_0_357), .A2(n_1_0_356), .ZN(n_1_0_355) + ); + AOI221_X1_LVT i_1_0_373( + .A(n_1_0_355), .B1(n_1_0_649), .B2(registers_29__ap[18]), .C1(registers_2__ap[18]), + .C2(n_1_0_618), .ZN(n_1_0_354) + ); + AOI22_X1_LVT i_1_0_372( + .A1(registers_18__ap[18]), .A2(n_1_0_646), .B1(n_1_0_633), .B2(registers_19__ap[18]), + .ZN(n_1_0_353) + ); + AOI22_X1_LVT i_1_0_371( + .A1(registers_12__ap[18]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[18]), + .ZN(n_1_0_352) + ); + AOI22_X1_LVT i_1_0_370( + .A1(registers_22__ap[18]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[18]), + .ZN(n_1_0_351) + ); + NAND3_X1_LVT i_1_0_369( + .A1(n_1_0_353), .A2(n_1_0_352), .A3(n_1_0_351), .ZN(n_1_0_350) + ); + AOI221_X1_LVT i_1_0_368( + .A(n_1_0_350), .B1(n_1_0_635), .B2(registers_5__ap[18]), .C1(registers_20__ap[18]), + .C2(n_1_0_613), .ZN(n_1_0_349) + ); + AOI22_X1_LVT i_1_0_367( + .A1(registers_15__ap[18]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[18]), + .ZN(n_1_0_348) + ); + AOI22_X1_LVT i_1_0_366( + .A1(registers_23__ap[18]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[18]), + .ZN(n_1_0_347) + ); + AOI22_X1_LVT i_1_0_365( + .A1(registers_13__ap[18]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[18]), + .ZN(n_1_0_346) + ); + NAND3_X1_LVT i_1_0_364( + .A1(n_1_0_348), .A2(n_1_0_347), .A3(n_1_0_346), .ZN(n_1_0_345) + ); + AOI221_X1_LVT i_1_0_363( + .A(n_1_0_345), .B1(n_1_0_637), .B2(registers_31__ap[18]), .C1(registers_27__ap[18]), + .C2(n_1_0_636), .ZN(n_1_0_344) + ); + NAND4_X1_LVT i_1_0_362( + .A1(n_1_0_361), .A2(n_1_0_354), .A3(n_1_0_349), .A4(n_1_0_344), .ZN(RRs2[18]) + ); + AOI22_X1_LVT i_1_0_358( + .A1(registers_4__ap[17]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[17]), + .ZN(n_1_0_340) + ); + AOI22_X1_LVT i_1_0_361( + .A1(registers_31__ap[17]), .A2(n_1_0_637), .B1(n_1_0_616), .B2(registers_6__ap[17]), + .ZN(n_1_0_343) + ); + AOI22_X1_LVT i_1_0_357( + .A1(registers_14__ap[17]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[17]), + .ZN(n_1_0_339) + ); + AOI22_X1_LVT i_1_0_360( + .A1(registers_25__ap[17]), .A2(n_1_0_620), .B1(n_1_0_611), .B2(registers_11__ap[17]), + .ZN(n_1_0_342) + ); + INV_X1_LVT i_1_0_359( + .A(n_1_0_342), .ZN(n_1_0_341) + ); + AOI221_X1_LVT i_1_0_356( + .A(n_1_0_341), .B1(n_1_0_614), .B2(registers_16__ap[17]), .C1(registers_10__ap[17]), + .C2(n_1_0_624), .ZN(n_1_0_338) + ); + AOI222_X1_LVT i_1_0_355( + .A1(registers_1__ap[17]), .A2(n_1_0_644), .B1(n_1_0_622), .B2(registers_30__ap[17]), + .C1(registers_18__ap[17]), .C2(n_1_0_646), .ZN(n_1_0_337) + ); + NAND4_X1_LVT i_1_0_354( + .A1(n_1_0_343), .A2(n_1_0_339), .A3(n_1_0_338), .A4(n_1_0_337), .ZN(n_1_0_336) + ); + AOI221_X1_LVT i_1_0_353( + .A(n_1_0_336), .B1(n_1_0_649), .B2(registers_29__ap[17]), .C1(registers_2__ap[17]), + .C2(n_1_0_618), .ZN(n_1_0_335) + ); + AOI22_X1_LVT i_1_0_352( + .A1(registers_26__ap[17]), .A2(n_1_0_640), .B1(n_1_0_633), .B2(registers_19__ap[17]), + .ZN(n_1_0_334) + ); + AOI22_X1_LVT i_1_0_351( + .A1(registers_12__ap[17]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[17]), + .ZN(n_1_0_333) + ); + AOI22_X1_LVT i_1_0_350( + .A1(registers_22__ap[17]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[17]), + .ZN(n_1_0_332) + ); + NAND3_X1_LVT i_1_0_349( + .A1(n_1_0_334), .A2(n_1_0_333), .A3(n_1_0_332), .ZN(n_1_0_331) + ); + AOI221_X1_LVT i_1_0_348( + .A(n_1_0_331), .B1(n_1_0_635), .B2(registers_5__ap[17]), .C1(registers_20__ap[17]), + .C2(n_1_0_613), .ZN(n_1_0_330) + ); + AOI22_X1_LVT i_1_0_347( + .A1(registers_15__ap[17]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[17]), + .ZN(n_1_0_329) + ); + AOI22_X1_LVT i_1_0_346( + .A1(registers_8__ap[17]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[17]), + .ZN(n_1_0_328) + ); + AOI22_X1_LVT i_1_0_345( + .A1(registers_13__ap[17]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[17]), + .ZN(n_1_0_327) + ); + NAND3_X1_LVT i_1_0_344( + .A1(n_1_0_329), .A2(n_1_0_328), .A3(n_1_0_327), .ZN(n_1_0_326) + ); + AOI221_X1_LVT i_1_0_343( + .A(n_1_0_326), .B1(n_1_0_636), .B2(registers_27__ap[17]), .C1(registers_3__ap[17]), + .C2(n_1_0_610), .ZN(n_1_0_325) + ); + NAND4_X1_LVT i_1_0_342( + .A1(n_1_0_340), .A2(n_1_0_335), .A3(n_1_0_330), .A4(n_1_0_325), .ZN(RRs2[17]) + ); + AOI22_X1_LVT i_1_0_341( + .A1(registers_4__ap[16]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[16]), + .ZN(n_1_0_324) + ); + AOI222_X1_LVT i_1_0_340( + .A1(registers_1__ap[16]), .A2(n_1_0_644), .B1(n_1_0_633), .B2(registers_19__ap[16]), + .C1(n_1_0_622), .C2(registers_30__ap[16]), .ZN(n_1_0_323) + ); + AOI22_X1_LVT i_1_0_339( + .A1(registers_29__ap[16]), .A2(n_1_0_649), .B1(n_1_0_618), .B2(registers_2__ap[16]), + .ZN(n_1_0_322) + ); + AOI22_X1_LVT i_1_0_338( + .A1(registers_14__ap[16]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[16]), + .ZN(n_1_0_321) + ); + AOI22_X1_LVT i_1_0_337( + .A1(registers_16__ap[16]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[16]), + .ZN(n_1_0_320) + ); + AOI22_X1_LVT i_1_0_336( + .A1(registers_10__ap[16]), .A2(n_1_0_624), .B1(n_1_0_620), .B2(registers_25__ap[16]), + .ZN(n_1_0_319) + ); + AOI22_X1_LVT i_1_0_335( + .A1(registers_31__ap[16]), .A2(n_1_0_637), .B1(n_1_0_616), .B2(registers_6__ap[16]), + .ZN(n_1_0_318) + ); + NAND4_X1_LVT i_1_0_334( + .A1(n_1_0_321), .A2(n_1_0_320), .A3(n_1_0_319), .A4(n_1_0_318), .ZN(n_1_0_317) + ); + AOI22_X1_LVT i_1_0_333( + .A1(registers_18__ap[16]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[16]), + .ZN(n_1_0_316) + ); + AOI22_X1_LVT i_1_0_332( + .A1(registers_12__ap[16]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[16]), + .ZN(n_1_0_315) + ); + AOI22_X1_LVT i_1_0_331( + .A1(registers_22__ap[16]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[16]), + .ZN(n_1_0_314) + ); + AOI22_X1_LVT i_1_0_330( + .A1(registers_5__ap[16]), .A2(n_1_0_635), .B1(n_1_0_613), .B2(registers_20__ap[16]), + .ZN(n_1_0_313) + ); + NAND4_X1_LVT i_1_0_329( + .A1(n_1_0_316), .A2(n_1_0_315), .A3(n_1_0_314), .A4(n_1_0_313), .ZN(n_1_0_312) + ); + AOI22_X1_LVT i_1_0_328( + .A1(registers_15__ap[16]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[16]), + .ZN(n_1_0_311) + ); + AOI22_X1_LVT i_1_0_327( + .A1(registers_8__ap[16]), .A2(n_1_0_626), .B1(n_1_0_615), .B2(registers_23__ap[16]), + .ZN(n_1_0_310) + ); + AOI22_X1_LVT i_1_0_326( + .A1(registers_13__ap[16]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[16]), + .ZN(n_1_0_309) + ); + AOI22_X1_LVT i_1_0_325( + .A1(registers_27__ap[16]), .A2(n_1_0_636), .B1(n_1_0_610), .B2(registers_3__ap[16]), + .ZN(n_1_0_308) + ); + NAND4_X1_LVT i_1_0_324( + .A1(n_1_0_311), .A2(n_1_0_310), .A3(n_1_0_309), .A4(n_1_0_308), .ZN(n_1_0_307) + ); + NOR3_X1_LVT i_1_0_323( + .A1(n_1_0_317), .A2(n_1_0_312), .A3(n_1_0_307), .ZN(n_1_0_306) + ); + NAND4_X1_LVT i_1_0_322( + .A1(n_1_0_324), .A2(n_1_0_323), .A3(n_1_0_322), .A4(n_1_0_306), .ZN(RRs2[16]) + ); + AOI22_X1_LVT i_1_0_320( + .A1(registers_5__ap[15]), .A2(n_1_0_635), .B1(n_1_0_634), .B2(registers_28__ap[15]), + .ZN(n_1_0_304) + ); + AOI22_X1_LVT i_1_0_321( + .A1(registers_8__ap[15]), .A2(n_1_0_626), .B1(n_1_0_620), .B2(registers_25__ap[15]), + .ZN(n_1_0_305) + ); + AOI22_X1_LVT i_1_0_319( + .A1(registers_14__ap[15]), .A2(n_1_0_619), .B1(n_1_0_617), .B2(registers_9__ap[15]), + .ZN(n_1_0_303) + ); + AOI22_X1_LVT i_1_0_318( + .A1(registers_16__ap[15]), .A2(n_1_0_614), .B1(n_1_0_611), .B2(registers_11__ap[15]), + .ZN(n_1_0_302) + ); + NAND3_X1_LVT i_1_0_317( + .A1(n_1_0_305), .A2(n_1_0_303), .A3(n_1_0_302), .ZN(n_1_0_301) + ); + AOI221_X1_LVT i_1_0_316( + .A(n_1_0_301), .B1(n_1_0_616), .B2(registers_6__ap[15]), .C1(registers_10__ap[15]), + .C2(n_1_0_624), .ZN(n_1_0_300) + ); + AOI222_X1_LVT i_1_0_315( + .A1(registers_1__ap[15]), .A2(n_1_0_644), .B1(n_1_0_640), .B2(registers_26__ap[15]), + .C1(n_1_0_622), .C2(registers_30__ap[15]), .ZN(n_1_0_299) + ); + NAND2_X1_LVT i_1_0_314( + .A1(n_1_0_300), .A2(n_1_0_299), .ZN(n_1_0_298) + ); + AOI221_X1_LVT i_1_0_313( + .A(n_1_0_298), .B1(n_1_0_649), .B2(registers_29__ap[15]), .C1(registers_2__ap[15]), + .C2(n_1_0_618), .ZN(n_1_0_297) + ); + AOI22_X1_LVT i_1_0_312( + .A1(registers_12__ap[15]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[15]), + .ZN(n_1_0_296) + ); + AOI22_X1_LVT i_1_0_311( + .A1(registers_22__ap[15]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[15]), + .ZN(n_1_0_295) + ); + AOI22_X1_LVT i_1_0_310( + .A1(registers_4__ap[15]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[15]), + .ZN(n_1_0_294) + ); + NAND3_X1_LVT i_1_0_309( + .A1(n_1_0_296), .A2(n_1_0_295), .A3(n_1_0_294), .ZN(n_1_0_293) + ); + AOI221_X1_LVT i_1_0_308( + .A(n_1_0_293), .B1(n_1_0_633), .B2(registers_19__ap[15]), .C1(registers_18__ap[15]), + .C2(n_1_0_646), .ZN(n_1_0_292) + ); + AOI22_X1_LVT i_1_0_307( + .A1(registers_15__ap[15]), .A2(n_1_0_627), .B1(n_1_0_623), .B2(registers_7__ap[15]), + .ZN(n_1_0_291) + ); + AOI22_X1_LVT i_1_0_306( + .A1(registers_23__ap[15]), .A2(n_1_0_615), .B1(n_1_0_610), .B2(registers_3__ap[15]), + .ZN(n_1_0_290) + ); + AOI22_X1_LVT i_1_0_305( + .A1(registers_13__ap[15]), .A2(n_1_0_631), .B1(n_1_0_629), .B2(registers_17__ap[15]), + .ZN(n_1_0_289) + ); + NAND3_X1_LVT i_1_0_304( + .A1(n_1_0_291), .A2(n_1_0_290), .A3(n_1_0_289), .ZN(n_1_0_288) + ); + AOI221_X1_LVT i_1_0_303( + .A(n_1_0_288), .B1(n_1_0_636), .B2(registers_27__ap[15]), .C1(registers_31__ap[15]), + .C2(n_1_0_637), .ZN(n_1_0_287) + ); + NAND4_X1_LVT i_1_0_302( + .A1(n_1_0_304), .A2(n_1_0_297), .A3(n_1_0_292), .A4(n_1_0_287), .ZN(RRs2[15]) + ); + AOI22_X1_LVT i_1_0_301( + .A1(registers_28__ap[14]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[14]), + .ZN(n_1_0_286) + ); + AOI222_X1_LVT i_1_0_300( + .A1(registers_18__ap[14]), .A2(n_1_0_646), .B1(n_1_0_620), .B2(registers_25__ap[14]), + .C1(n_1_0_618), .C2(registers_2__ap[14]), .ZN(n_1_0_285) + ); + AOI22_X1_LVT i_1_0_299( + .A1(registers_24__ap[14]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[14]), + .ZN(n_1_0_284) + ); + AOI22_X1_LVT i_1_0_298( + .A1(registers_15__ap[14]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[14]), + .ZN(n_1_0_283) + ); + AOI22_X1_LVT i_1_0_297( + .A1(registers_4__ap[14]), .A2(n_1_0_638), .B1(n_1_0_637), .B2(registers_31__ap[14]), + .ZN(n_1_0_282) + ); + AOI22_X1_LVT i_1_0_296( + .A1(registers_29__ap[14]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[14]), + .ZN(n_1_0_281) + ); + NAND4_X1_LVT i_1_0_295( + .A1(n_1_0_284), .A2(n_1_0_283), .A3(n_1_0_282), .A4(n_1_0_281), .ZN(n_1_0_280) + ); + AOI221_X1_LVT i_1_0_294( + .A(n_1_0_280), .B1(n_1_0_644), .B2(registers_1__ap[14]), .C1(registers_13__ap[14]), + .C2(n_1_0_631), .ZN(n_1_0_279) + ); + AOI22_X1_LVT i_1_0_293( + .A1(registers_17__ap[14]), .A2(n_1_0_629), .B1(n_1_0_623), .B2(registers_7__ap[14]), + .ZN(n_1_0_278) + ); + AOI22_X1_LVT i_1_0_292( + .A1(registers_5__ap[14]), .A2(n_1_0_635), .B1(n_1_0_632), .B2(registers_12__ap[14]), + .ZN(n_1_0_277) + ); + AOI22_X1_LVT i_1_0_291( + .A1(registers_10__ap[14]), .A2(n_1_0_624), .B1(n_1_0_622), .B2(registers_30__ap[14]), + .ZN(n_1_0_276) + ); + AOI22_X1_LVT i_1_0_290( + .A1(registers_26__ap[14]), .A2(n_1_0_640), .B1(n_1_0_614), .B2(registers_16__ap[14]), + .ZN(n_1_0_275) + ); + NAND4_X1_LVT i_1_0_289( + .A1(n_1_0_278), .A2(n_1_0_277), .A3(n_1_0_276), .A4(n_1_0_275), .ZN(n_1_0_274) + ); + AOI22_X1_LVT i_1_0_288( + .A1(registers_9__ap[14]), .A2(n_1_0_617), .B1(n_1_0_612), .B2(registers_21__ap[14]), + .ZN(n_1_0_273) + ); + AOI22_X1_LVT i_1_0_287( + .A1(registers_14__ap[14]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[14]), + .ZN(n_1_0_272) + ); + AOI22_X1_LVT i_1_0_286( + .A1(registers_22__ap[14]), .A2(n_1_0_642), .B1(n_1_0_633), .B2(registers_19__ap[14]), + .ZN(n_1_0_271) + ); + AOI22_X1_LVT i_1_0_285( + .A1(registers_27__ap[14]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[14]), + .ZN(n_1_0_270) + ); + NAND4_X1_LVT i_1_0_284( + .A1(n_1_0_273), .A2(n_1_0_272), .A3(n_1_0_271), .A4(n_1_0_270), .ZN(n_1_0_269) + ); + NOR2_X1_LVT i_1_0_283( + .A1(n_1_0_274), .A2(n_1_0_269), .ZN(n_1_0_268) + ); + NAND4_X1_LVT i_1_0_282( + .A1(n_1_0_286), .A2(n_1_0_285), .A3(n_1_0_279), .A4(n_1_0_268), .ZN(RRs2[14]) + ); + AOI22_X1_LVT i_1_0_281( + .A1(registers_18__ap[13]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[13]), + .ZN(n_1_0_267) + ); + AOI22_X1_LVT i_1_0_280( + .A1(registers_12__ap[13]), .A2(n_1_0_632), .B1(n_1_0_629), .B2(registers_17__ap[13]), + .ZN(n_1_0_266) + ); + AOI22_X1_LVT i_1_0_279( + .A1(registers_7__ap[13]), .A2(n_1_0_623), .B1(n_1_0_614), .B2(registers_16__ap[13]), + .ZN(n_1_0_265) + ); + NAND3_X1_LVT i_1_0_277( + .A1(n_1_0_267), .A2(n_1_0_266), .A3(n_1_0_265), .ZN(n_1_0_263) + ); + AOI221_X1_LVT i_1_0_276( + .A(n_1_0_263), .B1(n_1_0_642), .B2(registers_22__ap[13]), .C1(registers_5__ap[13]), + .C2(n_1_0_635), .ZN(n_1_0_262) + ); + AOI22_X1_LVT i_1_0_278( + .A1(registers_13__ap[13]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[13]), + .ZN(n_1_0_264) + ); + AOI222_X1_LVT i_1_0_275( + .A1(registers_26__ap[13]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[13]), + .C1(n_1_0_620), .C2(registers_25__ap[13]), .ZN(n_1_0_261) + ); + AOI22_X1_LVT i_1_0_274( + .A1(registers_28__ap[13]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[13]), + .ZN(n_1_0_260) + ); + NAND3_X1_LVT i_1_0_273( + .A1(n_1_0_264), .A2(n_1_0_261), .A3(n_1_0_260), .ZN(n_1_0_259) + ); + AOI22_X1_LVT i_1_0_272( + .A1(registers_1__ap[13]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[13]), + .ZN(n_1_0_258) + ); + AOI22_X1_LVT i_1_0_271( + .A1(registers_19__ap[13]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[13]), + .ZN(n_1_0_257) + ); + AOI22_X1_LVT i_1_0_270( + .A1(registers_14__ap[13]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[13]), + .ZN(n_1_0_256) + ); + AOI22_X1_LVT i_1_0_269( + .A1(registers_27__ap[13]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[13]), + .ZN(n_1_0_255) + ); + NAND4_X1_LVT i_1_0_268( + .A1(n_1_0_258), .A2(n_1_0_257), .A3(n_1_0_256), .A4(n_1_0_255), .ZN(n_1_0_254) + ); + AOI22_X1_LVT i_1_0_267( + .A1(registers_24__ap[13]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[13]), + .ZN(n_1_0_253) + ); + AOI22_X1_LVT i_1_0_266( + .A1(registers_4__ap[13]), .A2(n_1_0_638), .B1(n_1_0_637), .B2(registers_31__ap[13]), + .ZN(n_1_0_252) + ); + AOI22_X1_LVT i_1_0_265( + .A1(registers_29__ap[13]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[13]), + .ZN(n_1_0_251) + ); + AOI22_X1_LVT i_1_0_264( + .A1(registers_15__ap[13]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[13]), + .ZN(n_1_0_250) + ); + NAND4_X1_LVT i_1_0_263( + .A1(n_1_0_253), .A2(n_1_0_252), .A3(n_1_0_251), .A4(n_1_0_250), .ZN(n_1_0_249) + ); + NOR3_X1_LVT i_1_0_262( + .A1(n_1_0_259), .A2(n_1_0_254), .A3(n_1_0_249), .ZN(n_1_0_248) + ); + NAND2_X1_LVT i_1_0_261( + .A1(n_1_0_262), .A2(n_1_0_248), .ZN(RRs2[13]) + ); + AOI22_X1_LVT i_1_0_260( + .A1(registers_18__ap[12]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[12]), + .ZN(n_1_0_247) + ); + AOI22_X1_LVT i_1_0_259( + .A1(registers_12__ap[12]), .A2(n_1_0_632), .B1(n_1_0_629), .B2(registers_17__ap[12]), + .ZN(n_1_0_246) + ); + AOI22_X1_LVT i_1_0_258( + .A1(registers_5__ap[12]), .A2(n_1_0_635), .B1(n_1_0_623), .B2(registers_7__ap[12]), + .ZN(n_1_0_245) + ); + NAND3_X1_LVT i_1_0_256( + .A1(n_1_0_247), .A2(n_1_0_246), .A3(n_1_0_245), .ZN(n_1_0_243) + ); + AOI221_X1_LVT i_1_0_255( + .A(n_1_0_243), .B1(n_1_0_642), .B2(registers_22__ap[12]), .C1(registers_16__ap[12]), + .C2(n_1_0_614), .ZN(n_1_0_242) + ); + AOI22_X1_LVT i_1_0_257( + .A1(registers_13__ap[12]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[12]), + .ZN(n_1_0_244) + ); + AOI222_X1_LVT i_1_0_254( + .A1(registers_26__ap[12]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[12]), + .C1(n_1_0_620), .C2(registers_25__ap[12]), .ZN(n_1_0_241) + ); + AOI22_X1_LVT i_1_0_253( + .A1(registers_28__ap[12]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[12]), + .ZN(n_1_0_240) + ); + NAND3_X1_LVT i_1_0_252( + .A1(n_1_0_244), .A2(n_1_0_241), .A3(n_1_0_240), .ZN(n_1_0_239) + ); + AOI22_X1_LVT i_1_0_251( + .A1(registers_1__ap[12]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[12]), + .ZN(n_1_0_238) + ); + AOI22_X1_LVT i_1_0_250( + .A1(registers_19__ap[12]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[12]), + .ZN(n_1_0_237) + ); + AOI22_X1_LVT i_1_0_249( + .A1(registers_14__ap[12]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[12]), + .ZN(n_1_0_236) + ); + AOI22_X1_LVT i_1_0_248( + .A1(registers_27__ap[12]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[12]), + .ZN(n_1_0_235) + ); + NAND4_X1_LVT i_1_0_247( + .A1(n_1_0_238), .A2(n_1_0_237), .A3(n_1_0_236), .A4(n_1_0_235), .ZN(n_1_0_234) + ); + AOI22_X1_LVT i_1_0_246( + .A1(registers_24__ap[12]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[12]), + .ZN(n_1_0_233) + ); + AOI22_X1_LVT i_1_0_245( + .A1(registers_4__ap[12]), .A2(n_1_0_638), .B1(n_1_0_637), .B2(registers_31__ap[12]), + .ZN(n_1_0_232) + ); + AOI22_X1_LVT i_1_0_244( + .A1(registers_29__ap[12]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[12]), + .ZN(n_1_0_231) + ); + AOI22_X1_LVT i_1_0_243( + .A1(registers_15__ap[12]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[12]), + .ZN(n_1_0_230) + ); + NAND4_X1_LVT i_1_0_242( + .A1(n_1_0_233), .A2(n_1_0_232), .A3(n_1_0_231), .A4(n_1_0_230), .ZN(n_1_0_229) + ); + NOR3_X1_LVT i_1_0_241( + .A1(n_1_0_239), .A2(n_1_0_234), .A3(n_1_0_229), .ZN(n_1_0_228) + ); + NAND2_X1_LVT i_1_0_240( + .A1(n_1_0_242), .A2(n_1_0_228), .ZN(RRs2[12]) + ); + AOI22_X1_LVT i_1_0_238( + .A1(registers_29__ap[11]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[11]), + .ZN(n_1_0_226) + ); + AOI22_X1_LVT i_1_0_239( + .A1(registers_27__ap[11]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[11]), + .ZN(n_1_0_227) + ); + AOI22_X1_LVT i_1_0_237( + .A1(registers_1__ap[11]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[11]), + .ZN(n_1_0_225) + ); + AOI22_X1_LVT i_1_0_236( + .A1(registers_5__ap[11]), .A2(n_1_0_635), .B1(n_1_0_615), .B2(registers_23__ap[11]), + .ZN(n_1_0_224) + ); + NAND3_X1_LVT i_1_0_235( + .A1(n_1_0_227), .A2(n_1_0_225), .A3(n_1_0_224), .ZN(n_1_0_223) + ); + AOI221_X1_LVT i_1_0_234( + .A(n_1_0_223), .B1(n_1_0_637), .B2(registers_31__ap[11]), .C1(registers_16__ap[11]), + .C2(n_1_0_614), .ZN(n_1_0_222) + ); + AOI222_X1_LVT i_1_0_233( + .A1(registers_8__ap[11]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[11]), + .C1(n_1_0_622), .C2(registers_30__ap[11]), .ZN(n_1_0_221) + ); + NAND3_X1_LVT i_1_0_232( + .A1(n_1_0_226), .A2(n_1_0_222), .A3(n_1_0_221), .ZN(n_1_0_220) + ); + AOI221_X1_LVT i_1_0_231( + .A(n_1_0_220), .B1(n_1_0_638), .B2(registers_4__ap[11]), .C1(registers_28__ap[11]), + .C2(n_1_0_634), .ZN(n_1_0_219) + ); + AOI22_X1_LVT i_1_0_230( + .A1(registers_18__ap[11]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[11]), + .ZN(n_1_0_218) + ); + AOI22_X1_LVT i_1_0_229( + .A1(registers_12__ap[11]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[11]), + .ZN(n_1_0_217) + ); + AOI22_X1_LVT i_1_0_228( + .A1(registers_22__ap[11]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[11]), + .ZN(n_1_0_216) + ); + NAND3_X1_LVT i_1_0_227( + .A1(n_1_0_218), .A2(n_1_0_217), .A3(n_1_0_216), .ZN(n_1_0_215) + ); + AOI221_X1_LVT i_1_0_226( + .A(n_1_0_215), .B1(n_1_0_613), .B2(registers_20__ap[11]), .C1(registers_17__ap[11]), + .C2(n_1_0_629), .ZN(n_1_0_214) + ); + AOI22_X1_LVT i_1_0_225( + .A1(registers_13__ap[11]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[11]), + .ZN(n_1_0_213) + ); + AOI22_X1_LVT i_1_0_224( + .A1(registers_7__ap[11]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[11]), + .ZN(n_1_0_212) + ); + AOI22_X1_LVT i_1_0_223( + .A1(registers_19__ap[11]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[11]), + .ZN(n_1_0_211) + ); + NAND3_X1_LVT i_1_0_222( + .A1(n_1_0_213), .A2(n_1_0_212), .A3(n_1_0_211), .ZN(n_1_0_210) + ); + AOI221_X1_LVT i_1_0_221( + .A(n_1_0_210), .B1(n_1_0_611), .B2(registers_11__ap[11]), .C1(registers_2__ap[11]), + .C2(n_1_0_618), .ZN(n_1_0_209) + ); + NAND3_X1_LVT i_1_0_220( + .A1(n_1_0_219), .A2(n_1_0_214), .A3(n_1_0_209), .ZN(RRs2[11]) + ); + AOI22_X1_LVT i_1_0_219( + .A1(registers_28__ap[10]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[10]), + .ZN(n_1_0_208) + ); + AOI222_X1_LVT i_1_0_218( + .A1(registers_26__ap[10]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[10]), + .C1(registers_25__ap[10]), .C2(n_1_0_620), .ZN(n_1_0_207) + ); + AOI22_X1_LVT i_1_0_217( + .A1(registers_13__ap[10]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[10]), + .ZN(n_1_0_206) + ); + AOI22_X1_LVT i_1_0_216( + .A1(registers_24__ap[10]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[10]), + .ZN(n_1_0_205) + ); + AOI22_X1_LVT i_1_0_215( + .A1(registers_15__ap[10]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[10]), + .ZN(n_1_0_204) + ); + AOI22_X1_LVT i_1_0_214( + .A1(registers_31__ap[10]), .A2(n_1_0_637), .B1(n_1_0_629), .B2(registers_17__ap[10]), + .ZN(n_1_0_203) + ); + AOI22_X1_LVT i_1_0_213( + .A1(registers_29__ap[10]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[10]), + .ZN(n_1_0_202) + ); + NAND4_X1_LVT i_1_0_212( + .A1(n_1_0_205), .A2(n_1_0_204), .A3(n_1_0_203), .A4(n_1_0_202), .ZN(n_1_0_201) + ); + AOI22_X1_LVT i_1_0_211( + .A1(registers_18__ap[10]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[10]), + .ZN(n_1_0_200) + ); + AOI22_X1_LVT i_1_0_210( + .A1(registers_4__ap[10]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[10]), + .ZN(n_1_0_199) + ); + AOI22_X1_LVT i_1_0_209( + .A1(registers_7__ap[10]), .A2(n_1_0_623), .B1(n_1_0_614), .B2(registers_16__ap[10]), + .ZN(n_1_0_198) + ); + AOI22_X1_LVT i_1_0_208( + .A1(registers_22__ap[10]), .A2(n_1_0_642), .B1(n_1_0_635), .B2(registers_5__ap[10]), + .ZN(n_1_0_197) + ); + NAND4_X1_LVT i_1_0_207( + .A1(n_1_0_200), .A2(n_1_0_199), .A3(n_1_0_198), .A4(n_1_0_197), .ZN(n_1_0_196) + ); + AOI22_X1_LVT i_1_0_206( + .A1(registers_1__ap[10]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[10]), + .ZN(n_1_0_195) + ); + AOI22_X1_LVT i_1_0_205( + .A1(registers_14__ap[10]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[10]), + .ZN(n_1_0_194) + ); + AOI22_X1_LVT i_1_0_204( + .A1(registers_19__ap[10]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[10]), + .ZN(n_1_0_193) + ); + AOI22_X1_LVT i_1_0_203( + .A1(registers_27__ap[10]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[10]), + .ZN(n_1_0_192) + ); + NAND4_X1_LVT i_1_0_202( + .A1(n_1_0_195), .A2(n_1_0_194), .A3(n_1_0_193), .A4(n_1_0_192), .ZN(n_1_0_191) + ); + NOR3_X1_LVT i_1_0_201( + .A1(n_1_0_201), .A2(n_1_0_196), .A3(n_1_0_191), .ZN(n_1_0_190) + ); + NAND4_X1_LVT i_1_0_200( + .A1(n_1_0_208), .A2(n_1_0_207), .A3(n_1_0_206), .A4(n_1_0_190), .ZN(RRs2[10]) + ); + AOI22_X1_LVT i_1_0_196( + .A1(registers_13__ap[9]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[9]), + .ZN(n_1_0_186) + ); + AOI22_X1_LVT i_1_0_199( + .A1(registers_29__ap[9]), .A2(n_1_0_649), .B1(n_1_0_636), .B2(registers_27__ap[9]), + .ZN(n_1_0_189) + ); + AOI22_X1_LVT i_1_0_195( + .A1(registers_24__ap[9]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[9]), + .ZN(n_1_0_185) + ); + AOI22_X1_LVT i_1_0_198( + .A1(registers_31__ap[9]), .A2(n_1_0_637), .B1(n_1_0_627), .B2(registers_15__ap[9]), + .ZN(n_1_0_188) + ); + INV_X1_LVT i_1_0_197( + .A(n_1_0_188), .ZN(n_1_0_187) + ); + AOI221_X1_LVT i_1_0_194( + .A(n_1_0_187), .B1(n_1_0_615), .B2(registers_23__ap[9]), .C1(registers_4__ap[9]), + .C2(n_1_0_638), .ZN(n_1_0_184) + ); + AOI222_X1_LVT i_1_0_193( + .A1(registers_18__ap[9]), .A2(n_1_0_646), .B1(n_1_0_624), .B2(registers_10__ap[9]), + .C1(registers_25__ap[9]), .C2(n_1_0_620), .ZN(n_1_0_183) + ); + NAND4_X1_LVT i_1_0_192( + .A1(n_1_0_189), .A2(n_1_0_185), .A3(n_1_0_184), .A4(n_1_0_183), .ZN(n_1_0_182) + ); + AOI221_X1_LVT i_1_0_191( + .A(n_1_0_182), .B1(n_1_0_626), .B2(registers_8__ap[9]), .C1(registers_28__ap[9]), + .C2(n_1_0_634), .ZN(n_1_0_181) + ); + AOI22_X1_LVT i_1_0_190( + .A1(registers_26__ap[9]), .A2(n_1_0_640), .B1(n_1_0_622), .B2(registers_30__ap[9]), + .ZN(n_1_0_180) + ); + AOI22_X1_LVT i_1_0_189( + .A1(registers_12__ap[9]), .A2(n_1_0_632), .B1(n_1_0_629), .B2(registers_17__ap[9]), + .ZN(n_1_0_179) + ); + AOI22_X1_LVT i_1_0_188( + .A1(registers_5__ap[9]), .A2(n_1_0_635), .B1(n_1_0_623), .B2(registers_7__ap[9]), + .ZN(n_1_0_178) + ); + NAND3_X1_LVT i_1_0_187( + .A1(n_1_0_180), .A2(n_1_0_179), .A3(n_1_0_178), .ZN(n_1_0_177) + ); + AOI221_X1_LVT i_1_0_186( + .A(n_1_0_177), .B1(n_1_0_642), .B2(registers_22__ap[9]), .C1(registers_16__ap[9]), + .C2(n_1_0_614), .ZN(n_1_0_176) + ); + AOI22_X1_LVT i_1_0_185( + .A1(registers_1__ap[9]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[9]), + .ZN(n_1_0_175) + ); + AOI22_X1_LVT i_1_0_184( + .A1(registers_14__ap[9]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[9]), + .ZN(n_1_0_174) + ); + AOI22_X1_LVT i_1_0_183( + .A1(registers_19__ap[9]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[9]), + .ZN(n_1_0_173) + ); + NAND3_X1_LVT i_1_0_182( + .A1(n_1_0_175), .A2(n_1_0_174), .A3(n_1_0_173), .ZN(n_1_0_172) + ); + AOI221_X1_LVT i_1_0_181( + .A(n_1_0_172), .B1(n_1_0_611), .B2(registers_11__ap[9]), .C1(registers_2__ap[9]), + .C2(n_1_0_618), .ZN(n_1_0_171) + ); + NAND4_X1_LVT i_1_0_180( + .A1(n_1_0_186), .A2(n_1_0_181), .A3(n_1_0_176), .A4(n_1_0_171), .ZN(RRs2[9]) + ); + AOI22_X1_LVT i_1_0_179( + .A1(registers_28__ap[8]), .A2(n_1_0_634), .B1(n_1_0_629), .B2(registers_17__ap[8]), + .ZN(n_1_0_170) + ); + AOI222_X1_LVT i_1_0_178( + .A1(registers_26__ap[8]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[8]), + .C1(n_1_0_626), .C2(registers_8__ap[8]), .ZN(n_1_0_169) + ); + AOI22_X1_LVT i_1_0_177( + .A1(registers_29__ap[8]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[8]), + .ZN(n_1_0_168) + ); + AOI22_X1_LVT i_1_0_176( + .A1(registers_1__ap[8]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[8]), + .ZN(n_1_0_167) + ); + AOI22_X1_LVT i_1_0_175( + .A1(registers_5__ap[8]), .A2(n_1_0_635), .B1(n_1_0_610), .B2(registers_3__ap[8]), + .ZN(n_1_0_166) + ); + AOI22_X1_LVT i_1_0_174( + .A1(registers_31__ap[8]), .A2(n_1_0_637), .B1(n_1_0_614), .B2(registers_16__ap[8]), + .ZN(n_1_0_165) + ); + AOI22_X1_LVT i_1_0_173( + .A1(registers_15__ap[8]), .A2(n_1_0_627), .B1(n_1_0_615), .B2(registers_23__ap[8]), + .ZN(n_1_0_164) + ); + NAND4_X1_LVT i_1_0_172( + .A1(n_1_0_167), .A2(n_1_0_166), .A3(n_1_0_165), .A4(n_1_0_164), .ZN(n_1_0_163) + ); + AOI22_X1_LVT i_1_0_171( + .A1(registers_18__ap[8]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[8]), + .ZN(n_1_0_162) + ); + AOI22_X1_LVT i_1_0_170( + .A1(registers_4__ap[8]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[8]), + .ZN(n_1_0_161) + ); + AOI22_X1_LVT i_1_0_169( + .A1(registers_22__ap[8]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[8]), + .ZN(n_1_0_160) + ); + AOI22_X1_LVT i_1_0_168( + .A1(registers_12__ap[8]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[8]), + .ZN(n_1_0_159) + ); + NAND4_X1_LVT i_1_0_167( + .A1(n_1_0_162), .A2(n_1_0_161), .A3(n_1_0_160), .A4(n_1_0_159), .ZN(n_1_0_158) + ); + AOI22_X1_LVT i_1_0_166( + .A1(registers_13__ap[8]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[8]), + .ZN(n_1_0_157) + ); + AOI22_X1_LVT i_1_0_165( + .A1(registers_7__ap[8]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[8]), + .ZN(n_1_0_156) + ); + AOI22_X1_LVT i_1_0_164( + .A1(registers_19__ap[8]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[8]), + .ZN(n_1_0_155) + ); + AOI22_X1_LVT i_1_0_163( + .A1(registers_27__ap[8]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[8]), + .ZN(n_1_0_154) + ); + NAND4_X1_LVT i_1_0_162( + .A1(n_1_0_157), .A2(n_1_0_156), .A3(n_1_0_155), .A4(n_1_0_154), .ZN(n_1_0_153) + ); + NOR3_X1_LVT i_1_0_161( + .A1(n_1_0_163), .A2(n_1_0_158), .A3(n_1_0_153), .ZN(n_1_0_152) + ); + NAND4_X1_LVT i_1_0_160( + .A1(n_1_0_170), .A2(n_1_0_169), .A3(n_1_0_168), .A4(n_1_0_152), .ZN(RRs2[8]) + ); + AOI22_X1_LVT i_1_0_159( + .A1(registers_28__ap[7]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[7]), + .ZN(n_1_0_151) + ); + AOI222_X1_LVT i_1_0_158( + .A1(registers_26__ap[7]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[7]), + .C1(registers_25__ap[7]), .C2(n_1_0_620), .ZN(n_1_0_150) + ); + AOI22_X1_LVT i_1_0_157( + .A1(registers_24__ap[7]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[7]), + .ZN(n_1_0_149) + ); + AOI22_X1_LVT i_1_0_156( + .A1(registers_15__ap[7]), .A2(n_1_0_627), .B1(n_1_0_610), .B2(registers_3__ap[7]), + .ZN(n_1_0_148) + ); + AOI22_X1_LVT i_1_0_155( + .A1(registers_31__ap[7]), .A2(n_1_0_637), .B1(n_1_0_629), .B2(registers_17__ap[7]), + .ZN(n_1_0_147) + ); + AOI22_X1_LVT i_1_0_154( + .A1(registers_29__ap[7]), .A2(n_1_0_649), .B1(n_1_0_615), .B2(registers_23__ap[7]), + .ZN(n_1_0_146) + ); + NAND4_X1_LVT i_1_0_153( + .A1(n_1_0_149), .A2(n_1_0_148), .A3(n_1_0_147), .A4(n_1_0_146), .ZN(n_1_0_145) + ); + AOI221_X1_LVT i_1_0_152( + .A(n_1_0_145), .B1(n_1_0_612), .B2(registers_21__ap[7]), .C1(registers_13__ap[7]), + .C2(n_1_0_631), .ZN(n_1_0_144) + ); + AOI22_X1_LVT i_1_0_151( + .A1(registers_18__ap[7]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[7]), + .ZN(n_1_0_143) + ); + AOI22_X1_LVT i_1_0_150( + .A1(registers_4__ap[7]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[7]), + .ZN(n_1_0_142) + ); + AOI22_X1_LVT i_1_0_149( + .A1(registers_5__ap[7]), .A2(n_1_0_635), .B1(n_1_0_623), .B2(registers_7__ap[7]), + .ZN(n_1_0_141) + ); + AOI22_X1_LVT i_1_0_148( + .A1(registers_22__ap[7]), .A2(n_1_0_642), .B1(n_1_0_614), .B2(registers_16__ap[7]), + .ZN(n_1_0_140) + ); + NAND4_X1_LVT i_1_0_147( + .A1(n_1_0_143), .A2(n_1_0_142), .A3(n_1_0_141), .A4(n_1_0_140), .ZN(n_1_0_139) + ); + AOI22_X1_LVT i_1_0_146( + .A1(registers_1__ap[7]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[7]), + .ZN(n_1_0_138) + ); + AOI22_X1_LVT i_1_0_145( + .A1(registers_14__ap[7]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[7]), + .ZN(n_1_0_137) + ); + AOI22_X1_LVT i_1_0_144( + .A1(registers_19__ap[7]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[7]), + .ZN(n_1_0_136) + ); + AOI22_X1_LVT i_1_0_143( + .A1(registers_27__ap[7]), .A2(n_1_0_636), .B1(n_1_0_611), .B2(registers_11__ap[7]), + .ZN(n_1_0_135) + ); + NAND4_X1_LVT i_1_0_142( + .A1(n_1_0_138), .A2(n_1_0_137), .A3(n_1_0_136), .A4(n_1_0_135), .ZN(n_1_0_134) + ); + NOR2_X1_LVT i_1_0_141( + .A1(n_1_0_139), .A2(n_1_0_134), .ZN(n_1_0_133) + ); + NAND4_X1_LVT i_1_0_140( + .A1(n_1_0_151), .A2(n_1_0_150), .A3(n_1_0_144), .A4(n_1_0_133), .ZN(RRs2[7]) + ); + AOI22_X1_LVT i_1_0_136( + .A1(registers_13__ap[6]), .A2(n_1_0_631), .B1(n_1_0_612), .B2(registers_21__ap[6]), + .ZN(n_1_0_129) + ); + AOI22_X1_LVT i_1_0_139( + .A1(registers_29__ap[6]), .A2(n_1_0_649), .B1(n_1_0_636), .B2(registers_27__ap[6]), + .ZN(n_1_0_132) + ); + AOI22_X1_LVT i_1_0_135( + .A1(registers_24__ap[6]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[6]), + .ZN(n_1_0_128) + ); + AOI22_X1_LVT i_1_0_138( + .A1(registers_31__ap[6]), .A2(n_1_0_637), .B1(n_1_0_627), .B2(registers_15__ap[6]), + .ZN(n_1_0_131) + ); + INV_X1_LVT i_1_0_137( + .A(n_1_0_131), .ZN(n_1_0_130) + ); + AOI221_X1_LVT i_1_0_134( + .A(n_1_0_130), .B1(n_1_0_638), .B2(registers_4__ap[6]), .C1(registers_23__ap[6]), + .C2(n_1_0_615), .ZN(n_1_0_127) + ); + AOI222_X1_LVT i_1_0_133( + .A1(registers_18__ap[6]), .A2(n_1_0_646), .B1(n_1_0_620), .B2(registers_25__ap[6]), + .C1(n_1_0_624), .C2(registers_10__ap[6]), .ZN(n_1_0_126) + ); + NAND4_X1_LVT i_1_0_132( + .A1(n_1_0_132), .A2(n_1_0_128), .A3(n_1_0_127), .A4(n_1_0_126), .ZN(n_1_0_125) + ); + AOI221_X1_LVT i_1_0_131( + .A(n_1_0_125), .B1(n_1_0_626), .B2(registers_8__ap[6]), .C1(registers_28__ap[6]), + .C2(n_1_0_634), .ZN(n_1_0_124) + ); + AOI22_X1_LVT i_1_0_130( + .A1(registers_26__ap[6]), .A2(n_1_0_640), .B1(n_1_0_622), .B2(registers_30__ap[6]), + .ZN(n_1_0_123) + ); + AOI22_X1_LVT i_1_0_129( + .A1(registers_12__ap[6]), .A2(n_1_0_632), .B1(n_1_0_629), .B2(registers_17__ap[6]), + .ZN(n_1_0_122) + ); + AOI22_X1_LVT i_1_0_128( + .A1(registers_7__ap[6]), .A2(n_1_0_623), .B1(n_1_0_614), .B2(registers_16__ap[6]), + .ZN(n_1_0_121) + ); + NAND3_X1_LVT i_1_0_127( + .A1(n_1_0_123), .A2(n_1_0_122), .A3(n_1_0_121), .ZN(n_1_0_120) + ); + AOI221_X1_LVT i_1_0_126( + .A(n_1_0_120), .B1(n_1_0_642), .B2(registers_22__ap[6]), .C1(registers_5__ap[6]), + .C2(n_1_0_635), .ZN(n_1_0_119) + ); + AOI22_X1_LVT i_1_0_125( + .A1(registers_1__ap[6]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[6]), + .ZN(n_1_0_118) + ); + AOI22_X1_LVT i_1_0_124( + .A1(registers_14__ap[6]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[6]), + .ZN(n_1_0_117) + ); + AOI22_X1_LVT i_1_0_123( + .A1(registers_19__ap[6]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[6]), + .ZN(n_1_0_116) + ); + NAND3_X1_LVT i_1_0_122( + .A1(n_1_0_118), .A2(n_1_0_117), .A3(n_1_0_116), .ZN(n_1_0_115) + ); + AOI221_X1_LVT i_1_0_121( + .A(n_1_0_115), .B1(n_1_0_618), .B2(registers_2__ap[6]), .C1(registers_11__ap[6]), + .C2(n_1_0_611), .ZN(n_1_0_114) + ); + NAND4_X1_LVT i_1_0_120( + .A1(n_1_0_129), .A2(n_1_0_124), .A3(n_1_0_119), .A4(n_1_0_114), .ZN(RRs2[6]) + ); + AOI22_X1_LVT i_1_0_118( + .A1(registers_28__ap[5]), .A2(n_1_0_634), .B1(n_1_0_626), .B2(registers_8__ap[5]), + .ZN(n_1_0_112) + ); + AOI22_X1_LVT i_1_0_119( + .A1(registers_31__ap[5]), .A2(n_1_0_637), .B1(n_1_0_627), .B2(registers_15__ap[5]), + .ZN(n_1_0_113) + ); + AOI22_X1_LVT i_1_0_117( + .A1(registers_24__ap[5]), .A2(n_1_0_621), .B1(n_1_0_613), .B2(registers_20__ap[5]), + .ZN(n_1_0_111) + ); + AOI22_X1_LVT i_1_0_116( + .A1(registers_17__ap[5]), .A2(n_1_0_629), .B1(n_1_0_615), .B2(registers_23__ap[5]), + .ZN(n_1_0_110) + ); + NAND3_X1_LVT i_1_0_115( + .A1(n_1_0_113), .A2(n_1_0_111), .A3(n_1_0_110), .ZN(n_1_0_109) + ); + AOI221_X1_LVT i_1_0_114( + .A(n_1_0_109), .B1(n_1_0_636), .B2(registers_27__ap[5]), .C1(registers_29__ap[5]), + .C2(n_1_0_649), .ZN(n_1_0_108) + ); + AOI222_X1_LVT i_1_0_113( + .A1(registers_10__ap[5]), .A2(n_1_0_624), .B1(n_1_0_620), .B2(registers_25__ap[5]), + .C1(registers_18__ap[5]), .C2(n_1_0_646), .ZN(n_1_0_107) + ); + NAND3_X1_LVT i_1_0_112( + .A1(n_1_0_112), .A2(n_1_0_108), .A3(n_1_0_107), .ZN(n_1_0_106) + ); + AOI221_X1_LVT i_1_0_111( + .A(n_1_0_106), .B1(n_1_0_612), .B2(registers_21__ap[5]), .C1(registers_13__ap[5]), + .C2(n_1_0_631), .ZN(n_1_0_105) + ); + AOI22_X1_LVT i_1_0_110( + .A1(registers_26__ap[5]), .A2(n_1_0_640), .B1(n_1_0_622), .B2(registers_30__ap[5]), + .ZN(n_1_0_104) + ); + AOI22_X1_LVT i_1_0_109( + .A1(registers_4__ap[5]), .A2(n_1_0_638), .B1(n_1_0_632), .B2(registers_12__ap[5]), + .ZN(n_1_0_103) + ); + AOI22_X1_LVT i_1_0_108( + .A1(registers_5__ap[5]), .A2(n_1_0_635), .B1(n_1_0_623), .B2(registers_7__ap[5]), + .ZN(n_1_0_102) + ); + NAND3_X1_LVT i_1_0_107( + .A1(n_1_0_104), .A2(n_1_0_103), .A3(n_1_0_102), .ZN(n_1_0_101) + ); + AOI221_X1_LVT i_1_0_106( + .A(n_1_0_101), .B1(n_1_0_642), .B2(registers_22__ap[5]), .C1(registers_16__ap[5]), + .C2(n_1_0_614), .ZN(n_1_0_100) + ); + AOI22_X1_LVT i_1_0_105( + .A1(registers_1__ap[5]), .A2(n_1_0_644), .B1(n_1_0_617), .B2(registers_9__ap[5]), + .ZN(n_1_0_99) + ); + AOI22_X1_LVT i_1_0_104( + .A1(registers_14__ap[5]), .A2(n_1_0_619), .B1(n_1_0_616), .B2(registers_6__ap[5]), + .ZN(n_1_0_98) + ); + AOI22_X1_LVT i_1_0_103( + .A1(registers_19__ap[5]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[5]), + .ZN(n_1_0_97) + ); + NAND3_X1_LVT i_1_0_102( + .A1(n_1_0_99), .A2(n_1_0_98), .A3(n_1_0_97), .ZN(n_1_0_96) + ); + AOI221_X1_LVT i_1_0_101( + .A(n_1_0_96), .B1(n_1_0_611), .B2(registers_11__ap[5]), .C1(registers_2__ap[5]), + .C2(n_1_0_618), .ZN(n_1_0_95) + ); + NAND3_X1_LVT i_1_0_100( + .A1(n_1_0_105), .A2(n_1_0_100), .A3(n_1_0_95), .ZN(RRs2[5]) + ); + AOI22_X1_LVT i_1_0_99( + .A1(registers_4__ap[4]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[4]), + .ZN(n_1_0_94) + ); + AOI222_X1_LVT i_1_0_98( + .A1(registers_8__ap[4]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[4]), + .C1(n_1_0_622), .C2(registers_30__ap[4]), .ZN(n_1_0_93) + ); + AOI22_X1_LVT i_1_0_97( + .A1(registers_29__ap[4]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[4]), + .ZN(n_1_0_92) + ); + AOI22_X1_LVT i_1_0_96( + .A1(registers_1__ap[4]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[4]), + .ZN(n_1_0_91) + ); + AOI22_X1_LVT i_1_0_95( + .A1(registers_27__ap[4]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[4]), + .ZN(n_1_0_90) + ); + AOI22_X1_LVT i_1_0_94( + .A1(registers_23__ap[4]), .A2(n_1_0_615), .B1(n_1_0_614), .B2(registers_16__ap[4]), + .ZN(n_1_0_89) + ); + AOI22_X1_LVT i_1_0_93( + .A1(registers_31__ap[4]), .A2(n_1_0_637), .B1(n_1_0_635), .B2(registers_5__ap[4]), + .ZN(n_1_0_88) + ); + NAND4_X1_LVT i_1_0_92( + .A1(n_1_0_91), .A2(n_1_0_90), .A3(n_1_0_89), .A4(n_1_0_88), .ZN(n_1_0_87) + ); + AOI22_X1_LVT i_1_0_91( + .A1(registers_18__ap[4]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[4]), + .ZN(n_1_0_86) + ); + AOI22_X1_LVT i_1_0_90( + .A1(registers_12__ap[4]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[4]), + .ZN(n_1_0_85) + ); + AOI22_X1_LVT i_1_0_89( + .A1(registers_22__ap[4]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[4]), + .ZN(n_1_0_84) + ); + AOI22_X1_LVT i_1_0_88( + .A1(registers_17__ap[4]), .A2(n_1_0_629), .B1(n_1_0_613), .B2(registers_20__ap[4]), + .ZN(n_1_0_83) + ); + NAND4_X1_LVT i_1_0_87( + .A1(n_1_0_86), .A2(n_1_0_85), .A3(n_1_0_84), .A4(n_1_0_83), .ZN(n_1_0_82) + ); + AOI22_X1_LVT i_1_0_86( + .A1(registers_13__ap[4]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[4]), + .ZN(n_1_0_81) + ); + AOI22_X1_LVT i_1_0_85( + .A1(registers_7__ap[4]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[4]), + .ZN(n_1_0_80) + ); + AOI22_X1_LVT i_1_0_84( + .A1(registers_19__ap[4]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[4]), + .ZN(n_1_0_79) + ); + AOI22_X1_LVT i_1_0_83( + .A1(registers_2__ap[4]), .A2(n_1_0_618), .B1(n_1_0_611), .B2(registers_11__ap[4]), + .ZN(n_1_0_78) + ); + NAND4_X1_LVT i_1_0_82( + .A1(n_1_0_81), .A2(n_1_0_80), .A3(n_1_0_79), .A4(n_1_0_78), .ZN(n_1_0_77) + ); + NOR3_X1_LVT i_1_0_81( + .A1(n_1_0_87), .A2(n_1_0_82), .A3(n_1_0_77), .ZN(n_1_0_76) + ); + NAND4_X1_LVT i_1_0_80( + .A1(n_1_0_94), .A2(n_1_0_93), .A3(n_1_0_92), .A4(n_1_0_76), .ZN(RRs2[4]) + ); + AOI22_X1_LVT i_1_0_78( + .A1(registers_29__ap[3]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[3]), + .ZN(n_1_0_74) + ); + AOI22_X1_LVT i_1_0_79( + .A1(registers_27__ap[3]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[3]), + .ZN(n_1_0_75) + ); + AOI22_X1_LVT i_1_0_77( + .A1(registers_1__ap[3]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[3]), + .ZN(n_1_0_73) + ); + AOI22_X1_LVT i_1_0_76( + .A1(registers_5__ap[3]), .A2(n_1_0_635), .B1(n_1_0_611), .B2(registers_11__ap[3]), + .ZN(n_1_0_72) + ); + NAND3_X1_LVT i_1_0_75( + .A1(n_1_0_75), .A2(n_1_0_73), .A3(n_1_0_72), .ZN(n_1_0_71) + ); + AOI221_X1_LVT i_1_0_74( + .A(n_1_0_71), .B1(n_1_0_614), .B2(registers_16__ap[3]), .C1(registers_31__ap[3]), + .C2(n_1_0_637), .ZN(n_1_0_70) + ); + AOI222_X1_LVT i_1_0_73( + .A1(registers_8__ap[3]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[3]), + .C1(n_1_0_622), .C2(registers_30__ap[3]), .ZN(n_1_0_69) + ); + NAND3_X1_LVT i_1_0_72( + .A1(n_1_0_74), .A2(n_1_0_70), .A3(n_1_0_69), .ZN(n_1_0_68) + ); + AOI221_X1_LVT i_1_0_71( + .A(n_1_0_68), .B1(n_1_0_638), .B2(registers_4__ap[3]), .C1(registers_28__ap[3]), + .C2(n_1_0_634), .ZN(n_1_0_67) + ); + AOI22_X1_LVT i_1_0_70( + .A1(registers_18__ap[3]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[3]), + .ZN(n_1_0_66) + ); + AOI22_X1_LVT i_1_0_69( + .A1(registers_12__ap[3]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[3]), + .ZN(n_1_0_65) + ); + AOI22_X1_LVT i_1_0_68( + .A1(registers_22__ap[3]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[3]), + .ZN(n_1_0_64) + ); + NAND3_X1_LVT i_1_0_67( + .A1(n_1_0_66), .A2(n_1_0_65), .A3(n_1_0_64), .ZN(n_1_0_63) + ); + AOI221_X1_LVT i_1_0_66( + .A(n_1_0_63), .B1(n_1_0_613), .B2(registers_20__ap[3]), .C1(registers_17__ap[3]), + .C2(n_1_0_629), .ZN(n_1_0_62) + ); + AOI22_X1_LVT i_1_0_65( + .A1(registers_13__ap[3]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[3]), + .ZN(n_1_0_61) + ); + AOI22_X1_LVT i_1_0_64( + .A1(registers_7__ap[3]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[3]), + .ZN(n_1_0_60) + ); + AOI22_X1_LVT i_1_0_63( + .A1(registers_19__ap[3]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[3]), + .ZN(n_1_0_59) + ); + NAND3_X1_LVT i_1_0_62( + .A1(n_1_0_61), .A2(n_1_0_60), .A3(n_1_0_59), .ZN(n_1_0_58) + ); + AOI221_X1_LVT i_1_0_61( + .A(n_1_0_58), .B1(n_1_0_618), .B2(registers_2__ap[3]), .C1(registers_23__ap[3]), + .C2(n_1_0_615), .ZN(n_1_0_57) + ); + NAND3_X1_LVT i_1_0_60( + .A1(n_1_0_67), .A2(n_1_0_62), .A3(n_1_0_57), .ZN(RRs2[3]) + ); + AOI22_X1_LVT i_1_0_58( + .A1(registers_29__ap[2]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[2]), + .ZN(n_1_0_55) + ); + AOI22_X1_LVT i_1_0_59( + .A1(registers_27__ap[2]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[2]), + .ZN(n_1_0_56) + ); + AOI22_X1_LVT i_1_0_57( + .A1(registers_1__ap[2]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[2]), + .ZN(n_1_0_54) + ); + AOI22_X1_LVT i_1_0_56( + .A1(registers_5__ap[2]), .A2(n_1_0_635), .B1(n_1_0_615), .B2(registers_23__ap[2]), + .ZN(n_1_0_53) + ); + NAND3_X1_LVT i_1_0_55( + .A1(n_1_0_56), .A2(n_1_0_54), .A3(n_1_0_53), .ZN(n_1_0_52) + ); + AOI221_X1_LVT i_1_0_54( + .A(n_1_0_52), .B1(n_1_0_637), .B2(registers_31__ap[2]), .C1(registers_16__ap[2]), + .C2(n_1_0_614), .ZN(n_1_0_51) + ); + AOI222_X1_LVT i_1_0_53( + .A1(registers_8__ap[2]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[2]), + .C1(n_1_0_622), .C2(registers_30__ap[2]), .ZN(n_1_0_50) + ); + NAND3_X1_LVT i_1_0_52( + .A1(n_1_0_55), .A2(n_1_0_51), .A3(n_1_0_50), .ZN(n_1_0_49) + ); + AOI221_X1_LVT i_1_0_51( + .A(n_1_0_49), .B1(n_1_0_638), .B2(registers_4__ap[2]), .C1(registers_28__ap[2]), + .C2(n_1_0_634), .ZN(n_1_0_48) + ); + AOI22_X1_LVT i_1_0_50( + .A1(registers_18__ap[2]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[2]), + .ZN(n_1_0_47) + ); + AOI22_X1_LVT i_1_0_49( + .A1(registers_12__ap[2]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[2]), + .ZN(n_1_0_46) + ); + AOI22_X1_LVT i_1_0_48( + .A1(registers_22__ap[2]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[2]), + .ZN(n_1_0_45) + ); + NAND3_X1_LVT i_1_0_47( + .A1(n_1_0_47), .A2(n_1_0_46), .A3(n_1_0_45), .ZN(n_1_0_44) + ); + AOI221_X1_LVT i_1_0_46( + .A(n_1_0_44), .B1(n_1_0_629), .B2(registers_17__ap[2]), .C1(registers_20__ap[2]), + .C2(n_1_0_613), .ZN(n_1_0_43) + ); + AOI22_X1_LVT i_1_0_45( + .A1(registers_13__ap[2]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[2]), + .ZN(n_1_0_42) + ); + AOI22_X1_LVT i_1_0_44( + .A1(registers_7__ap[2]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[2]), + .ZN(n_1_0_41) + ); + AOI22_X1_LVT i_1_0_43( + .A1(registers_19__ap[2]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[2]), + .ZN(n_1_0_40) + ); + NAND3_X1_LVT i_1_0_42( + .A1(n_1_0_42), .A2(n_1_0_41), .A3(n_1_0_40), .ZN(n_1_0_39) + ); + AOI221_X1_LVT i_1_0_41( + .A(n_1_0_39), .B1(n_1_0_618), .B2(registers_2__ap[2]), .C1(registers_11__ap[2]), + .C2(n_1_0_611), .ZN(n_1_0_38) + ); + NAND3_X1_LVT i_1_0_40( + .A1(n_1_0_48), .A2(n_1_0_43), .A3(n_1_0_38), .ZN(RRs2[2]) + ); + AOI22_X1_LVT i_1_0_38( + .A1(registers_29__ap[1]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[1]), + .ZN(n_1_0_36) + ); + AOI22_X1_LVT i_1_0_39( + .A1(registers_16__ap[1]), .A2(n_1_0_614), .B1(n_1_0_610), .B2(registers_3__ap[1]), + .ZN(n_1_0_37) + ); + AOI22_X1_LVT i_1_0_37( + .A1(registers_1__ap[1]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[1]), + .ZN(n_1_0_35) + ); + AOI22_X1_LVT i_1_0_36( + .A1(registers_31__ap[1]), .A2(n_1_0_637), .B1(n_1_0_635), .B2(registers_5__ap[1]), + .ZN(n_1_0_34) + ); + NAND3_X1_LVT i_1_0_35( + .A1(n_1_0_37), .A2(n_1_0_35), .A3(n_1_0_34), .ZN(n_1_0_33) + ); + AOI221_X1_LVT i_1_0_34( + .A(n_1_0_33), .B1(n_1_0_627), .B2(registers_15__ap[1]), .C1(registers_23__ap[1]), + .C2(n_1_0_615), .ZN(n_1_0_32) + ); + AOI222_X1_LVT i_1_0_33( + .A1(registers_26__ap[1]), .A2(n_1_0_640), .B1(n_1_0_624), .B2(registers_10__ap[1]), + .C1(n_1_0_626), .C2(registers_8__ap[1]), .ZN(n_1_0_31) + ); + NAND3_X1_LVT i_1_0_32( + .A1(n_1_0_36), .A2(n_1_0_32), .A3(n_1_0_31), .ZN(n_1_0_30) + ); + AOI221_X1_LVT i_1_0_31( + .A(n_1_0_30), .B1(n_1_0_629), .B2(registers_17__ap[1]), .C1(registers_28__ap[1]), + .C2(n_1_0_634), .ZN(n_1_0_29) + ); + AOI22_X1_LVT i_1_0_30( + .A1(registers_18__ap[1]), .A2(n_1_0_646), .B1(n_1_0_622), .B2(registers_30__ap[1]), + .ZN(n_1_0_28) + ); + AOI22_X1_LVT i_1_0_29( + .A1(registers_4__ap[1]), .A2(n_1_0_638), .B1(n_1_0_613), .B2(registers_20__ap[1]), + .ZN(n_1_0_27) + ); + AOI22_X1_LVT i_1_0_28( + .A1(registers_22__ap[1]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[1]), + .ZN(n_1_0_26) + ); + NAND3_X1_LVT i_1_0_27( + .A1(n_1_0_28), .A2(n_1_0_27), .A3(n_1_0_26), .ZN(n_1_0_25) + ); + AOI221_X1_LVT i_1_0_26( + .A(n_1_0_25), .B1(n_1_0_632), .B2(registers_12__ap[1]), .C1(registers_24__ap[1]), + .C2(n_1_0_621), .ZN(n_1_0_24) + ); + AOI22_X1_LVT i_1_0_25( + .A1(registers_13__ap[1]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[1]), + .ZN(n_1_0_23) + ); + AOI22_X1_LVT i_1_0_24( + .A1(registers_7__ap[1]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[1]), + .ZN(n_1_0_22) + ); + AOI22_X1_LVT i_1_0_23( + .A1(registers_19__ap[1]), .A2(n_1_0_633), .B1(n_1_0_618), .B2(registers_2__ap[1]), + .ZN(n_1_0_21) + ); + NAND3_X1_LVT i_1_0_22( + .A1(n_1_0_23), .A2(n_1_0_22), .A3(n_1_0_21), .ZN(n_1_0_20) + ); + AOI221_X1_LVT i_1_0_21( + .A(n_1_0_20), .B1(n_1_0_611), .B2(registers_11__ap[1]), .C1(registers_27__ap[1]), + .C2(n_1_0_636), .ZN(n_1_0_19) + ); + NAND3_X1_LVT i_1_0_20( + .A1(n_1_0_29), .A2(n_1_0_24), .A3(n_1_0_19), .ZN(RRs2[1]) + ); + AOI22_X1_LVT i_1_0_19( + .A1(registers_4__ap[0]), .A2(n_1_0_638), .B1(n_1_0_634), .B2(registers_28__ap[0]), + .ZN(n_1_0_18) + ); + AOI222_X1_LVT i_1_0_18( + .A1(registers_8__ap[0]), .A2(n_1_0_626), .B1(n_1_0_624), .B2(registers_10__ap[0]), + .C1(n_1_0_622), .C2(registers_30__ap[0]), .ZN(n_1_0_17) + ); + AOI22_X1_LVT i_1_0_17( + .A1(registers_29__ap[0]), .A2(n_1_0_649), .B1(n_1_0_617), .B2(registers_9__ap[0]), + .ZN(n_1_0_16) + ); + AOI22_X1_LVT i_1_0_16( + .A1(registers_1__ap[0]), .A2(n_1_0_644), .B1(n_1_0_616), .B2(registers_6__ap[0]), + .ZN(n_1_0_15) + ); + AOI22_X1_LVT i_1_0_15( + .A1(registers_27__ap[0]), .A2(n_1_0_636), .B1(n_1_0_627), .B2(registers_15__ap[0]), + .ZN(n_1_0_14) + ); + AOI22_X1_LVT i_1_0_14( + .A1(registers_23__ap[0]), .A2(n_1_0_615), .B1(n_1_0_614), .B2(registers_16__ap[0]), + .ZN(n_1_0_13) + ); + AOI22_X1_LVT i_1_0_13( + .A1(registers_31__ap[0]), .A2(n_1_0_637), .B1(n_1_0_635), .B2(registers_5__ap[0]), + .ZN(n_1_0_12) + ); + NAND4_X1_LVT i_1_0_12( + .A1(n_1_0_15), .A2(n_1_0_14), .A3(n_1_0_13), .A4(n_1_0_12), .ZN(n_1_0_11) + ); + AOI22_X1_LVT i_1_0_11( + .A1(registers_18__ap[0]), .A2(n_1_0_646), .B1(n_1_0_640), .B2(registers_26__ap[0]), + .ZN(n_1_0_10) + ); + AOI22_X1_LVT i_1_0_10( + .A1(registers_12__ap[0]), .A2(n_1_0_632), .B1(n_1_0_621), .B2(registers_24__ap[0]), + .ZN(n_1_0_9) + ); + AOI22_X1_LVT i_1_0_9( + .A1(registers_22__ap[0]), .A2(n_1_0_642), .B1(n_1_0_612), .B2(registers_21__ap[0]), + .ZN(n_1_0_8) + ); + AOI22_X1_LVT i_1_0_8( + .A1(registers_17__ap[0]), .A2(n_1_0_629), .B1(n_1_0_613), .B2(registers_20__ap[0]), + .ZN(n_1_0_7) + ); + NAND4_X1_LVT i_1_0_7( + .A1(n_1_0_10), .A2(n_1_0_9), .A3(n_1_0_8), .A4(n_1_0_7), .ZN(n_1_0_6) + ); + AOI22_X1_LVT i_1_0_6( + .A1(registers_13__ap[0]), .A2(n_1_0_631), .B1(n_1_0_620), .B2(registers_25__ap[0]), + .ZN(n_1_0_5) + ); + AOI22_X1_LVT i_1_0_5( + .A1(registers_7__ap[0]), .A2(n_1_0_623), .B1(n_1_0_619), .B2(registers_14__ap[0]), + .ZN(n_1_0_4) + ); + AOI22_X1_LVT i_1_0_4( + .A1(registers_19__ap[0]), .A2(n_1_0_633), .B1(n_1_0_610), .B2(registers_3__ap[0]), + .ZN(n_1_0_3) + ); + AOI22_X1_LVT i_1_0_3( + .A1(registers_2__ap[0]), .A2(n_1_0_618), .B1(n_1_0_611), .B2(registers_11__ap[0]), + .ZN(n_1_0_2) + ); + NAND4_X1_LVT i_1_0_2( + .A1(n_1_0_5), .A2(n_1_0_4), .A3(n_1_0_3), .A4(n_1_0_2), .ZN(n_1_0_1) + ); + NOR3_X1_LVT i_1_0_1( + .A1(n_1_0_11), .A2(n_1_0_6), .A3(n_1_0_1), .ZN(n_1_0_0) + ); + NAND4_X1_LVT i_1_0_0( + .A1(n_1_0_18), .A2(n_1_0_17), .A3(n_1_0_16), .A4(n_1_0_0), .ZN(RRs2[0]) + ); + DLL_X2_LVT ts_lockup_latchn_clkc2_intno1050_i( + .D(registers_1__ap[0]), .GN(n_0_0), .Q(ts_no1050) + ); + DLL_X2_LVT ts_lockup_latchn_clkc4_intno1051_i( + .D(registers_6__ap[0]), .GN(n_0_36), .Q(ts_no1051) + ); + DLL_X2_LVT ts_lockup_latchn_clkc3_intno1053_i( + .D(registers_27__ap[0]), .GN(n_0_57), .Q(ts_no1053) + ); + DLL_X2_LVT ts_lockup_latchn_clkc1_intno1054_i( + .D(registers_11__ap[0]), .GN(n_0_41), .Q(ts_no1054) + ); + CLKBUF_X3_LVT tessent_persistent_cell_buf_extsi1227_i( + .A(ts_extsi1227), .Z(ts_pbuf_extsi1227_) + ); + CLKBUF_X3_LVT tessent_persistent_cell_buf_extsi1228_i( + .A(ts_extsi1228), .Z(ts_pbuf_extsi1228_) + ); + CLKBUF_X3_LVT tessent_persistent_cell_buf_extsi1226_i( + .A(ts_extsi1226), .Z(ts_pbuf_extsi1226_) + ); +endmodule + +module cpu(led, btn, clk_25mhz, scan_en, SI_1, SO_1, SI_2, SO_2, SI_3, SO_3, SI_4, + SO_4); + input [6:0] btn; + input clk_25mhz, scan_en, SI_1, SI_2, SI_3, SI_4; + output [7:0] led; + output SO_1, SO_2, SO_3, SO_4; + + wire [31:0] Instruction, RData, RRs2, RRs1, WRd, DAddr, JumpOrBranchPC, + CurrentPC, NextPC; + wire [1:0] DWidth; + wire WrReg, JumpOrBranch, thePC_n_1, thePC_i_0_n_0, thePC_n_2, thePC_i_0_n_1, + thePC_n_3, thePC_i_0_n_2, thePC_n_4, thePC_i_0_n_3, thePC_n_5, + thePC_i_0_n_4, thePC_n_6, thePC_i_0_n_5, thePC_n_7, thePC_i_0_n_6, + thePC_n_8, thePC_i_0_n_7, thePC_n_9, thePC_i_0_n_8, thePC_n_10, + thePC_i_0_n_9, thePC_n_11, thePC_i_0_n_10, thePC_n_12, thePC_i_0_n_11, + thePC_n_13, thePC_i_0_n_12, thePC_n_14, thePC_i_0_n_13, thePC_n_15, + thePC_i_0_n_14, thePC_n_16, thePC_i_0_n_15, thePC_n_17, thePC_i_0_n_16, + thePC_n_18, thePC_i_0_n_17, thePC_n_19, thePC_i_0_n_18, thePC_n_20, + thePC_i_0_n_19, thePC_n_21, thePC_i_0_n_20, thePC_n_22, thePC_i_0_n_21, + thePC_n_23, thePC_i_0_n_22, thePC_n_24, thePC_i_0_n_23, thePC_n_25, + thePC_i_0_n_24, thePC_n_26, thePC_i_0_n_25, thePC_n_27, thePC_i_0_n_26, + thePC_n_28, thePC_i_0_n_27, thePC_n_29, thePC_n_0, thePC_n_30, n_0_0_0, + thePC_n_31, n_0_0_1, thePC_n_32, thePC_n_33, thePC_n_34, thePC_n_35, + thePC_n_36, thePC_n_37, thePC_n_38, thePC_n_39, thePC_n_40, thePC_n_41, + thePC_n_42, thePC_n_43, n_0_0_2, thePC_n_44, n_0_0_3, thePC_n_45, + n_0_0_4, thePC_n_46, n_0_0_5, thePC_n_47, n_0_0_6, thePC_n_48, n_0_0_7, + thePC_n_49, n_0_0_8, thePC_n_50, n_0_0_9, thePC_n_51, n_0_0_10, + thePC_n_52, n_0_0_11, thePC_n_53, n_0_0_12, thePC_n_54, n_0_0_13, + thePC_n_55, n_0_0_14, thePC_n_56, n_0_0_15, thePC_n_57, n_0_0_16, + thePC_n_58, n_0_0_17, thePC_n_59, n_0_0_18, thePC_n_60, n_0_0_19, + thePC_n_61, n_0_0_20, n_0_0_21, n_0_0_22, reset, uc_0, uc_1, uc_2, uc_3, + uc_4, uc_5, uc_6, uc_7, uc_8, uc_9, uc_10, uc_11, uc_12, uc_13, uc_14, + uc_15, uc_16, uc_17, uc_18, uc_19, uc_20, uc_21, uc_22, uc_23, uc_24, + uc_25, uc_26, uc_27, uc_28, uc_29, uc_30, uc_31, uc_32, uc_33, uc_34, + uc_35, uc_36, uc_37, uc_38, uc_39, uc_40, uc_41, uc_42, uc_43, uc_44, + uc_45, uc_46, uc_47, uc_48, uc_49, uc_50, uc_51, uc_52, uc_53, uc_54, + uc_55, uc_56, uc_57, uc_58, ts_pbuf_extsi1225_, ts_no1054, ts_no1050, + ts_no1053, ts_no1051; + + assign SO_1 = ts_no1054; + assign SO_2 = ts_no1050; + assign SO_3 = ts_no1053; + assign SO_4 = ts_no1051; + AND2_X1_LVT i_0_0_54( + .A1(JumpOrBranch), .A2(btn[0]), .ZN(n_0_0_22) + ); + INV_X1_LVT i_0_0_66( + .A(btn[0]), .ZN(reset) + ); + NOR2_X1_LVT i_0_0_53( + .A1(reset), .A2(JumpOrBranch), .ZN(n_0_0_21) + ); + AOI22_X1_LVT i_0_0_50( + .A1(JumpOrBranchPC[30]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_28), .ZN(n_0_0_19) + ); + INV_X1_LVT i_0_0_49( + .A(n_0_0_19), .ZN(thePC_n_60) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[30] ( + .CK(clk_25mhz), .D(thePC_n_60), .Q(CurrentPC[30]), .QN(), .SE(scan_en), .SI(ts_pbuf_extsi1225_) + ); + AOI22_X1_LVT i_0_0_48( + .A1(JumpOrBranchPC[29]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_27), .ZN(n_0_0_18) + ); + INV_X1_LVT i_0_0_47( + .A(n_0_0_18), .ZN(thePC_n_59) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[29] ( + .CK(clk_25mhz), .D(thePC_n_59), .Q(CurrentPC[29]), .QN(), .SE(scan_en), .SI(CurrentPC[30]) + ); + AOI22_X1_LVT i_0_0_46( + .A1(JumpOrBranchPC[28]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_26), .ZN(n_0_0_17) + ); + INV_X1_LVT i_0_0_45( + .A(n_0_0_17), .ZN(thePC_n_58) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[28] ( + .CK(clk_25mhz), .D(thePC_n_58), .Q(CurrentPC[28]), .QN(), .SE(scan_en), .SI(CurrentPC[29]) + ); + AOI22_X1_LVT i_0_0_44( + .A1(JumpOrBranchPC[27]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_25), .ZN(n_0_0_16) + ); + INV_X1_LVT i_0_0_43( + .A(n_0_0_16), .ZN(thePC_n_57) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[27] ( + .CK(clk_25mhz), .D(thePC_n_57), .Q(CurrentPC[27]), .QN(), .SE(scan_en), .SI(CurrentPC[28]) + ); + AOI22_X1_LVT i_0_0_42( + .A1(JumpOrBranchPC[26]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_24), .ZN(n_0_0_15) + ); + INV_X1_LVT i_0_0_41( + .A(n_0_0_15), .ZN(thePC_n_56) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[26] ( + .CK(clk_25mhz), .D(thePC_n_56), .Q(CurrentPC[26]), .QN(), .SE(scan_en), .SI(CurrentPC[27]) + ); + AOI22_X1_LVT i_0_0_40( + .A1(JumpOrBranchPC[25]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_23), .ZN(n_0_0_14) + ); + INV_X1_LVT i_0_0_39( + .A(n_0_0_14), .ZN(thePC_n_55) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[25] ( + .CK(clk_25mhz), .D(thePC_n_55), .Q(CurrentPC[25]), .QN(), .SE(scan_en), .SI(CurrentPC[26]) + ); + AOI22_X1_LVT i_0_0_38( + .A1(JumpOrBranchPC[24]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_22), .ZN(n_0_0_13) + ); + INV_X1_LVT i_0_0_37( + .A(n_0_0_13), .ZN(thePC_n_54) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[24] ( + .CK(clk_25mhz), .D(thePC_n_54), .Q(CurrentPC[24]), .QN(), .SE(scan_en), .SI(CurrentPC[25]) + ); + AOI22_X1_LVT i_0_0_36( + .A1(JumpOrBranchPC[23]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_21), .ZN(n_0_0_12) + ); + INV_X1_LVT i_0_0_35( + .A(n_0_0_12), .ZN(thePC_n_53) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[23] ( + .CK(clk_25mhz), .D(thePC_n_53), .Q(CurrentPC[23]), .QN(), .SE(scan_en), .SI(CurrentPC[24]) + ); + AOI22_X1_LVT i_0_0_34( + .A1(JumpOrBranchPC[22]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_20), .ZN(n_0_0_11) + ); + INV_X1_LVT i_0_0_33( + .A(n_0_0_11), .ZN(thePC_n_52) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[22] ( + .CK(clk_25mhz), .D(thePC_n_52), .Q(CurrentPC[22]), .QN(), .SE(scan_en), .SI(CurrentPC[23]) + ); + AOI22_X1_LVT i_0_0_32( + .A1(JumpOrBranchPC[21]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_19), .ZN(n_0_0_10) + ); + INV_X1_LVT i_0_0_31( + .A(n_0_0_10), .ZN(thePC_n_51) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[21] ( + .CK(clk_25mhz), .D(thePC_n_51), .Q(CurrentPC[21]), .QN(), .SE(scan_en), .SI(CurrentPC[22]) + ); + AOI22_X1_LVT i_0_0_30( + .A1(JumpOrBranchPC[20]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_18), .ZN(n_0_0_9) + ); + INV_X1_LVT i_0_0_29( + .A(n_0_0_9), .ZN(thePC_n_50) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[20] ( + .CK(clk_25mhz), .D(thePC_n_50), .Q(CurrentPC[20]), .QN(), .SE(scan_en), .SI(CurrentPC[21]) + ); + AOI22_X1_LVT i_0_0_28( + .A1(JumpOrBranchPC[19]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_17), .ZN(n_0_0_8) + ); + INV_X1_LVT i_0_0_27( + .A(n_0_0_8), .ZN(thePC_n_49) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[19] ( + .CK(clk_25mhz), .D(thePC_n_49), .Q(CurrentPC[19]), .QN(), .SE(scan_en), .SI(CurrentPC[20]) + ); + AOI22_X1_LVT i_0_0_26( + .A1(JumpOrBranchPC[18]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_16), .ZN(n_0_0_7) + ); + INV_X1_LVT i_0_0_25( + .A(n_0_0_7), .ZN(thePC_n_48) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[18] ( + .CK(clk_25mhz), .D(thePC_n_48), .Q(CurrentPC[18]), .QN(), .SE(scan_en), .SI(CurrentPC[19]) + ); + AOI22_X1_LVT i_0_0_24( + .A1(JumpOrBranchPC[17]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_15), .ZN(n_0_0_6) + ); + INV_X1_LVT i_0_0_23( + .A(n_0_0_6), .ZN(thePC_n_47) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[17] ( + .CK(clk_25mhz), .D(thePC_n_47), .Q(CurrentPC[17]), .QN(), .SE(scan_en), .SI(CurrentPC[18]) + ); + AOI22_X1_LVT i_0_0_22( + .A1(JumpOrBranchPC[16]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_14), .ZN(n_0_0_5) + ); + INV_X1_LVT i_0_0_21( + .A(n_0_0_5), .ZN(thePC_n_46) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[16] ( + .CK(clk_25mhz), .D(thePC_n_46), .Q(CurrentPC[16]), .QN(), .SE(scan_en), .SI(CurrentPC[17]) + ); + AOI22_X1_LVT i_0_0_20( + .A1(JumpOrBranchPC[15]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_13), .ZN(n_0_0_4) + ); + INV_X1_LVT i_0_0_19( + .A(n_0_0_4), .ZN(thePC_n_45) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[15] ( + .CK(clk_25mhz), .D(thePC_n_45), .Q(CurrentPC[15]), .QN(), .SE(scan_en), .SI(CurrentPC[16]) + ); + AOI22_X1_LVT i_0_0_18( + .A1(JumpOrBranchPC[14]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_12), .ZN(n_0_0_3) + ); + INV_X1_LVT i_0_0_17( + .A(n_0_0_3), .ZN(thePC_n_44) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[14] ( + .CK(clk_25mhz), .D(thePC_n_44), .Q(CurrentPC[14]), .QN(), .SE(scan_en), .SI(CurrentPC[15]) + ); + AOI22_X1_LVT i_0_0_16( + .A1(JumpOrBranchPC[13]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_11), .ZN(n_0_0_2) + ); + INV_X1_LVT i_0_0_15( + .A(n_0_0_2), .ZN(thePC_n_43) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[13] ( + .CK(clk_25mhz), .D(thePC_n_43), .Q(CurrentPC[13]), .QN(), .SE(scan_en), .SI(CurrentPC[14]) + ); + MUX2_X1_LVT i_0_0_65( + .A(thePC_n_10), .B(JumpOrBranchPC[12]), .S(JumpOrBranch), .Z(NextPC[12]) + ); + AND2_X1_LVT i_0_0_14( + .A1(NextPC[12]), .A2(btn[0]), .ZN(thePC_n_42) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[12] ( + .CK(clk_25mhz), .D(thePC_n_42), .Q(CurrentPC[12]), .QN(), .SE(scan_en), .SI(CurrentPC[13]) + ); + MUX2_X1_LVT i_0_0_64( + .A(thePC_n_9), .B(JumpOrBranchPC[11]), .S(JumpOrBranch), .Z(NextPC[11]) + ); + AND2_X1_LVT i_0_0_13( + .A1(NextPC[11]), .A2(btn[0]), .ZN(thePC_n_41) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[11] ( + .CK(clk_25mhz), .D(thePC_n_41), .Q(CurrentPC[11]), .QN(), .SE(scan_en), .SI(CurrentPC[12]) + ); + MUX2_X1_LVT i_0_0_63( + .A(thePC_n_8), .B(JumpOrBranchPC[10]), .S(JumpOrBranch), .Z(NextPC[10]) + ); + AND2_X1_LVT i_0_0_12( + .A1(NextPC[10]), .A2(btn[0]), .ZN(thePC_n_40) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[10] ( + .CK(clk_25mhz), .D(thePC_n_40), .Q(CurrentPC[10]), .QN(), .SE(scan_en), .SI(CurrentPC[11]) + ); + MUX2_X1_LVT i_0_0_62( + .A(thePC_n_7), .B(JumpOrBranchPC[9]), .S(JumpOrBranch), .Z(NextPC[9]) + ); + AND2_X1_LVT i_0_0_11( + .A1(NextPC[9]), .A2(btn[0]), .ZN(thePC_n_39) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[9] ( + .CK(clk_25mhz), .D(thePC_n_39), .Q(CurrentPC[9]), .QN(), .SE(scan_en), .SI(CurrentPC[10]) + ); + MUX2_X1_LVT i_0_0_61( + .A(thePC_n_6), .B(JumpOrBranchPC[8]), .S(JumpOrBranch), .Z(NextPC[8]) + ); + AND2_X1_LVT i_0_0_10( + .A1(NextPC[8]), .A2(btn[0]), .ZN(thePC_n_38) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[8] ( + .CK(clk_25mhz), .D(thePC_n_38), .Q(CurrentPC[8]), .QN(), .SE(scan_en), .SI(CurrentPC[9]) + ); + AND2_X1_LVT i_0_0_9( + .A1(led[7]), .A2(btn[0]), .ZN(thePC_n_37) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[7] ( + .CK(clk_25mhz), .D(thePC_n_37), .Q(CurrentPC[7]), .QN(), .SE(scan_en), .SI(CurrentPC[8]) + ); + MUX2_X1_LVT i_0_0_59( + .A(thePC_n_4), .B(JumpOrBranchPC[6]), .S(JumpOrBranch), .Z(led[6]) + ); + AND2_X1_LVT i_0_0_8( + .A1(led[6]), .A2(btn[0]), .ZN(thePC_n_36) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[6] ( + .CK(clk_25mhz), .D(thePC_n_36), .Q(CurrentPC[6]), .QN(), .SE(scan_en), .SI(CurrentPC[7]) + ); + MUX2_X1_LVT i_0_0_58( + .A(thePC_n_3), .B(JumpOrBranchPC[5]), .S(JumpOrBranch), .Z(led[5]) + ); + AND2_X1_LVT i_0_0_7( + .A1(led[5]), .A2(btn[0]), .ZN(thePC_n_35) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[5] ( + .CK(clk_25mhz), .D(thePC_n_35), .Q(CurrentPC[5]), .QN(), .SE(scan_en), .SI(CurrentPC[6]) + ); + MUX2_X1_LVT i_0_0_57( + .A(thePC_n_2), .B(JumpOrBranchPC[4]), .S(JumpOrBranch), .Z(led[4]) + ); + AND2_X1_LVT i_0_0_6( + .A1(led[4]), .A2(btn[0]), .ZN(thePC_n_34) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[4] ( + .CK(clk_25mhz), .D(thePC_n_34), .Q(CurrentPC[4]), .QN(), .SE(scan_en), .SI(CurrentPC[5]) + ); + MUX2_X1_LVT i_0_0_56( + .A(thePC_n_1), .B(JumpOrBranchPC[3]), .S(JumpOrBranch), .Z(led[3]) + ); + AND2_X1_LVT i_0_0_5( + .A1(led[3]), .A2(btn[0]), .ZN(thePC_n_33) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[3] ( + .CK(clk_25mhz), .D(thePC_n_33), .Q(CurrentPC[3]), .QN(), .SE(scan_en), .SI(CurrentPC[4]) + ); + INV_X1_LVT thePC_i_0_29( + .A(CurrentPC[2]), .ZN(thePC_n_0) + ); + MUX2_X1_LVT i_0_0_55( + .A(thePC_n_0), .B(JumpOrBranchPC[2]), .S(JumpOrBranch), .Z(led[2]) + ); + AND2_X1_LVT i_0_0_4( + .A1(led[2]), .A2(btn[0]), .ZN(thePC_n_32) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[2] ( + .CK(clk_25mhz), .D(thePC_n_32), .Q(CurrentPC[2]), .QN(), .SE(scan_en), .SI(CurrentPC[3]) + ); + HA_X1_LVT thePC_i_0_0( + .A(CurrentPC[3]), .B(CurrentPC[2]), .CO(thePC_i_0_n_0), .S(thePC_n_1) + ); + HA_X1_LVT thePC_i_0_1( + .A(CurrentPC[4]), .B(thePC_i_0_n_0), .CO(thePC_i_0_n_1), .S(thePC_n_2) + ); + HA_X1_LVT thePC_i_0_2( + .A(CurrentPC[5]), .B(thePC_i_0_n_1), .CO(thePC_i_0_n_2), .S(thePC_n_3) + ); + HA_X1_LVT thePC_i_0_3( + .A(CurrentPC[6]), .B(thePC_i_0_n_2), .CO(thePC_i_0_n_3), .S(thePC_n_4) + ); + HA_X1_LVT thePC_i_0_4( + .A(CurrentPC[7]), .B(thePC_i_0_n_3), .CO(thePC_i_0_n_4), .S(thePC_n_5) + ); + HA_X1_LVT thePC_i_0_5( + .A(CurrentPC[8]), .B(thePC_i_0_n_4), .CO(thePC_i_0_n_5), .S(thePC_n_6) + ); + HA_X1_LVT thePC_i_0_6( + .A(CurrentPC[9]), .B(thePC_i_0_n_5), .CO(thePC_i_0_n_6), .S(thePC_n_7) + ); + HA_X1_LVT thePC_i_0_7( + .A(CurrentPC[10]), .B(thePC_i_0_n_6), .CO(thePC_i_0_n_7), .S(thePC_n_8) + ); + HA_X1_LVT thePC_i_0_8( + .A(CurrentPC[11]), .B(thePC_i_0_n_7), .CO(thePC_i_0_n_8), .S(thePC_n_9) + ); + HA_X1_LVT thePC_i_0_9( + .A(CurrentPC[12]), .B(thePC_i_0_n_8), .CO(thePC_i_0_n_9), .S(thePC_n_10) + ); + HA_X1_LVT thePC_i_0_11( + .A(CurrentPC[13]), .B(thePC_i_0_n_9), .CO(thePC_i_0_n_10), .S(thePC_n_11) + ); + HA_X1_LVT thePC_i_0_12( + .A(CurrentPC[14]), .B(thePC_i_0_n_10), .CO(thePC_i_0_n_11), .S(thePC_n_12) + ); + HA_X1_LVT thePC_i_0_13( + .A(CurrentPC[15]), .B(thePC_i_0_n_11), .CO(thePC_i_0_n_12), .S(thePC_n_13) + ); + HA_X1_LVT thePC_i_0_14( + .A(CurrentPC[16]), .B(thePC_i_0_n_12), .CO(thePC_i_0_n_13), .S(thePC_n_14) + ); + HA_X1_LVT thePC_i_0_15( + .A(CurrentPC[17]), .B(thePC_i_0_n_13), .CO(thePC_i_0_n_14), .S(thePC_n_15) + ); + HA_X1_LVT thePC_i_0_16( + .A(CurrentPC[18]), .B(thePC_i_0_n_14), .CO(thePC_i_0_n_15), .S(thePC_n_16) + ); + HA_X1_LVT thePC_i_0_17( + .A(CurrentPC[19]), .B(thePC_i_0_n_15), .CO(thePC_i_0_n_16), .S(thePC_n_17) + ); + HA_X1_LVT thePC_i_0_10( + .A(CurrentPC[20]), .B(thePC_i_0_n_16), .CO(thePC_i_0_n_17), .S(thePC_n_18) + ); + HA_X1_LVT thePC_i_0_18( + .A(CurrentPC[21]), .B(thePC_i_0_n_17), .CO(thePC_i_0_n_18), .S(thePC_n_19) + ); + HA_X1_LVT thePC_i_0_19( + .A(CurrentPC[22]), .B(thePC_i_0_n_18), .CO(thePC_i_0_n_19), .S(thePC_n_20) + ); + HA_X1_LVT thePC_i_0_20( + .A(CurrentPC[23]), .B(thePC_i_0_n_19), .CO(thePC_i_0_n_20), .S(thePC_n_21) + ); + HA_X1_LVT thePC_i_0_21( + .A(CurrentPC[24]), .B(thePC_i_0_n_20), .CO(thePC_i_0_n_21), .S(thePC_n_22) + ); + HA_X1_LVT thePC_i_0_22( + .A(CurrentPC[25]), .B(thePC_i_0_n_21), .CO(thePC_i_0_n_22), .S(thePC_n_23) + ); + HA_X1_LVT thePC_i_0_23( + .A(CurrentPC[26]), .B(thePC_i_0_n_22), .CO(thePC_i_0_n_23), .S(thePC_n_24) + ); + HA_X1_LVT thePC_i_0_24( + .A(CurrentPC[27]), .B(thePC_i_0_n_23), .CO(thePC_i_0_n_24), .S(thePC_n_25) + ); + HA_X1_LVT thePC_i_0_25( + .A(CurrentPC[28]), .B(thePC_i_0_n_24), .CO(thePC_i_0_n_25), .S(thePC_n_26) + ); + HA_X1_LVT thePC_i_0_26( + .A(CurrentPC[29]), .B(thePC_i_0_n_25), .CO(thePC_i_0_n_26), .S(thePC_n_27) + ); + HA_X1_LVT thePC_i_0_27( + .A(CurrentPC[30]), .B(thePC_i_0_n_26), .CO(thePC_i_0_n_27), .S(thePC_n_28) + ); + XOR2_X1_LVT thePC_i_0_28( + .A(CurrentPC[31]), .B(thePC_i_0_n_27), .Z(thePC_n_29) + ); + AOI22_X1_LVT i_0_0_52( + .A1(JumpOrBranchPC[31]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(thePC_n_29), .ZN(n_0_0_20) + ); + INV_X1_LVT i_0_0_51( + .A(n_0_0_20), .ZN(thePC_n_61) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[31] ( + .CK(clk_25mhz), .D(thePC_n_61), .Q(CurrentPC[31]), .QN(), .SE(scan_en), .SI(CurrentPC[2]) + ); + AOI22_X1_LVT i_0_0_3( + .A1(JumpOrBranchPC[1]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(CurrentPC[1]), + .ZN(n_0_0_1) + ); + INV_X1_LVT i_0_0_2( + .A(n_0_0_1), .ZN(thePC_n_31) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[1] ( + .CK(clk_25mhz), .D(thePC_n_31), .Q(CurrentPC[1]), .QN(), .SE(scan_en), .SI(CurrentPC[31]) + ); + AOI22_X1_LVT i_0_0_1( + .A1(JumpOrBranchPC[0]), .A2(n_0_0_22), .B1(n_0_0_21), .B2(CurrentPC[0]), + .ZN(n_0_0_0) + ); + INV_X1_LVT i_0_0_0( + .A(n_0_0_0), .ZN(thePC_n_30) + ); + SDFF_X1_LVT \thePC_CurrentPC_reg[0] ( + .CK(clk_25mhz), .D(thePC_n_30), .Q(CurrentPC[0]), .QN(), .SE(scan_en), .SI(CurrentPC[1]) + ); + reg_file theRegisters( + .Rs1({Instruction[19], Instruction[18], Instruction[17], + Instruction[16], Instruction[15]}), .Rs2({Instruction[24], + Instruction[23], Instruction[22], Instruction[21], Instruction[20]}), .Rd({ + Instruction[11], Instruction[10], Instruction[9], Instruction[8], + Instruction[7]}), .RRs1(RRs1), .RRs2(RRs2), .WRd(WRd), .WrReg(WrReg), .reset(reset), + .clk(clk_25mhz), .dftIn(scan_en), .ts_intno31(CurrentPC[0]), .ts_no1050(ts_no1050), + .ts_no1051(ts_no1051), .ts_no1053(ts_no1053), .ts_no1054(ts_no1054), .ts_extsi1226(SI_2), + .ts_extsi1227(SI_3), .ts_extsi1228(SI_4) + ); + main_mem theMem( + .clk(clk_25mhz), .reset(reset), .DAddr({uc_0, uc_1, uc_2, uc_3, uc_4, + uc_5, uc_6, uc_7, uc_8, uc_9, uc_10, uc_11, uc_12, uc_13, uc_14, uc_15, + uc_16, uc_17, uc_18, DAddr[12], DAddr[11], DAddr[10], DAddr[9], + DAddr[8], DAddr[7], DAddr[6], DAddr[5], DAddr[4], DAddr[3], DAddr[2], + DAddr[1], DAddr[0]}), .IAddr({uc_19, uc_20, uc_21, uc_22, uc_23, uc_24, + uc_25, uc_26, uc_27, uc_28, uc_29, uc_30, uc_31, uc_32, uc_33, uc_34, + uc_35, uc_36, uc_37, NextPC[12], NextPC[11], NextPC[10], NextPC[9], + NextPC[8], led[7], led[6], led[5], led[4], led[3], led[2], uc_38, uc_39}), + .DWData(RRs2), .DRData(RData), .IRData(Instruction), .DWE(led[1]), .DWidth(DWidth) + ); + decoder theDecoder( + .CurrentPC(CurrentPC), .JumpOrBranchPC(JumpOrBranchPC), .JumpOrBranch(JumpOrBranch), + .DAddr({uc_40, uc_41, uc_42, uc_43, uc_44, uc_45, uc_46, uc_47, uc_48, + uc_49, uc_50, uc_51, uc_52, uc_53, uc_54, uc_55, uc_56, uc_57, uc_58, + DAddr[12], DAddr[11], DAddr[10], DAddr[9], DAddr[8], DAddr[7], DAddr[6], + DAddr[5], DAddr[4], DAddr[3], DAddr[2], DAddr[1], DAddr[0]}), .WData(), .RData(RData), + .Instruction(Instruction), .WrMem(led[1]), .DWidth(DWidth), .Rs1(), .Rs2(), + .Rd(), .RRs1(RRs1), .RRs2(RRs2), .WRd(WRd), .WrReg(WrReg), .Illegal(led[0]) + ); + MUX2_X1_LVT i_0_0_60( + .A(thePC_n_5), .B(JumpOrBranchPC[7]), .S(JumpOrBranch), .Z(led[7]) + ); + CLKBUF_X3_LVT tessent_persistent_cell_buf_extsi1225_i( + .A(SI_1), .Z(ts_pbuf_extsi1225_) + ); +endmodule + diff --git a/output/odb/riscv.tessent_post_fix.odb b/output/odb/riscv.tessent_post_fix.odb new file mode 100644 index 0000000..6430266 Binary files /dev/null and b/output/odb/riscv.tessent_post_fix.odb differ diff --git a/output/odb/riscv.tessent_post_scan.odb b/output/odb/riscv.tessent_post_scan.odb new file mode 100644 index 0000000..623f791 Binary files /dev/null and b/output/odb/riscv.tessent_post_scan.odb differ diff --git a/output/odb/riscv.tessent_pre_fix.odb b/output/odb/riscv.tessent_pre_fix.odb new file mode 100644 index 0000000..7b46c39 Binary files /dev/null and b/output/odb/riscv.tessent_pre_fix.odb differ diff --git a/output/odb/riscv_chip.syn.odb b/output/odb/riscv_chip.syn.odb new file mode 100644 index 0000000..15508b0 Binary files /dev/null and b/output/odb/riscv_chip.syn.odb differ diff --git a/output/odb/riscv_chip.virtual_opt.odb b/output/odb/riscv_chip.virtual_opt.odb new file mode 100644 index 0000000..0325698 Binary files /dev/null and b/output/odb/riscv_chip.virtual_opt.odb differ diff --git a/output/riscv.tessent_post_fix.v b/output/riscv.tessent_post_fix.v new file mode 100644 index 0000000..e2f6743 --- /dev/null +++ b/output/riscv.tessent_post_fix.v @@ -0,0 +1,10581 @@ +/* + * Created by + ../bin/Linux-x86_64-O/oasysGui 22.2-p002 on Fri May 29 09:14:15 2026 + * (C) Mentor Graphics Corporation + */ +/* CheckSum: 87248176 */ + +module datapathS__0_65(CurrentPC, p_0); + input [31:0]CurrentPC; + output [31:0]p_0; + + HA_X1_LVT i_0 (.A(CurrentPC[3]), .B(CurrentPC[2]), .CO(n_0), .S(p_0[3])); + HA_X1_LVT i_1 (.A(CurrentPC[4]), .B(n_0), .CO(n_1), .S(p_0[4])); + HA_X1_LVT i_2 (.A(CurrentPC[5]), .B(n_1), .CO(n_2), .S(p_0[5])); + HA_X1_LVT i_3 (.A(CurrentPC[6]), .B(n_2), .CO(n_3), .S(p_0[6])); + HA_X1_LVT i_4 (.A(CurrentPC[7]), .B(n_3), .CO(n_4), .S(p_0[7])); + HA_X1_LVT i_5 (.A(CurrentPC[8]), .B(n_4), .CO(n_5), .S(p_0[8])); + HA_X1_LVT i_6 (.A(CurrentPC[9]), .B(n_5), .CO(n_6), .S(p_0[9])); + HA_X1_LVT i_7 (.A(CurrentPC[10]), .B(n_6), .CO(n_7), .S(p_0[10])); + HA_X1_LVT i_8 (.A(CurrentPC[11]), .B(n_7), .CO(n_8), .S(p_0[11])); + HA_X1_LVT i_9 (.A(CurrentPC[12]), .B(n_8), .CO(n_9), .S(p_0[12])); + HA_X1_LVT i_11 (.A(CurrentPC[13]), .B(n_9), .CO(n_10), .S(p_0[13])); + HA_X1_LVT i_12 (.A(CurrentPC[14]), .B(n_10), .CO(n_11), .S(p_0[14])); + HA_X1_LVT i_13 (.A(CurrentPC[15]), .B(n_11), .CO(n_12), .S(p_0[15])); + HA_X1_LVT i_14 (.A(CurrentPC[16]), .B(n_12), .CO(n_13), .S(p_0[16])); + HA_X1_LVT i_15 (.A(CurrentPC[17]), .B(n_13), .CO(n_14), .S(p_0[17])); + HA_X1_LVT i_16 (.A(CurrentPC[18]), .B(n_14), .CO(n_15), .S(p_0[18])); + HA_X1_LVT i_17 (.A(CurrentPC[19]), .B(n_15), .CO(n_16), .S(p_0[19])); + HA_X1_LVT i_10 (.A(CurrentPC[20]), .B(n_16), .CO(n_17), .S(p_0[20])); + HA_X1_LVT i_18 (.A(CurrentPC[21]), .B(n_17), .CO(n_18), .S(p_0[21])); + HA_X1_LVT i_19 (.A(CurrentPC[22]), .B(n_18), .CO(n_19), .S(p_0[22])); + HA_X1_LVT i_20 (.A(CurrentPC[23]), .B(n_19), .CO(n_20), .S(p_0[23])); + HA_X1_LVT i_21 (.A(CurrentPC[24]), .B(n_20), .CO(n_21), .S(p_0[24])); + HA_X1_LVT i_22 (.A(CurrentPC[25]), .B(n_21), .CO(n_22), .S(p_0[25])); + HA_X1_LVT i_23 (.A(CurrentPC[26]), .B(n_22), .CO(n_23), .S(p_0[26])); + HA_X1_LVT i_24 (.A(CurrentPC[27]), .B(n_23), .CO(n_24), .S(p_0[27])); + HA_X1_LVT i_25 (.A(CurrentPC[28]), .B(n_24), .CO(n_25), .S(p_0[28])); + HA_X1_LVT i_26 (.A(CurrentPC[29]), .B(n_25), .CO(n_26), .S(p_0[29])); + HA_X1_LVT i_27 (.A(CurrentPC[30]), .B(n_26), .CO(n_27), .S(p_0[30])); + XOR2_X1_LVT i_28 (.A(CurrentPC[31]), .B(n_27), .Z(p_0[31])); + INV_X1_LVT i_29 (.A(CurrentPC[2]), .ZN(p_0[2])); +endmodule + +module reg_file(Rs1, Rs2, Rd, RRs1, RRs2, WRd, WrReg, reset, clk, dftIn); + input [4:0]Rs1; + input [4:0]Rs2; + input [4:0]Rd; + output [31:0]RRs1; + output [31:0]RRs2; + input [31:0]WRd; + input WrReg; + input reset; + input clk; + input dftIn; + + wire [31:0]registers_1__ap; + wire n_0_0; + wire [31:0]registers_2__ap; + wire n_0_32; + wire [31:0]registers_3__ap; + wire n_0_33; + wire [31:0]registers_4__ap; + wire n_0_34; + wire [31:0]registers_5__ap; + wire n_0_35; + wire [31:0]registers_6__ap; + wire n_0_36; + wire [31:0]registers_7__ap; + wire n_0_37; + wire [31:0]registers_8__ap; + wire n_0_38; + wire [31:0]registers_9__ap; + wire n_0_39; + wire [31:0]registers_10__ap; + wire n_0_40; + wire [31:0]registers_11__ap; + wire n_0_41; + wire [31:0]registers_12__ap; + wire n_0_42; + wire [31:0]registers_13__ap; + wire n_0_43; + wire [31:0]registers_14__ap; + wire n_0_44; + wire [31:0]registers_15__ap; + wire n_0_45; + wire [31:0]registers_16__ap; + wire n_0_46; + wire [31:0]registers_17__ap; + wire n_0_47; + wire [31:0]registers_18__ap; + wire n_0_48; + wire [31:0]registers_19__ap; + wire n_0_49; + wire [31:0]registers_20__ap; + wire n_0_50; + wire [31:0]registers_21__ap; + wire n_0_51; + wire [31:0]registers_22__ap; + wire n_0_52; + wire [31:0]registers_23__ap; + wire n_0_53; + wire [31:0]registers_24__ap; + wire n_0_54; + wire [31:0]registers_25__ap; + wire n_0_55; + wire [31:0]registers_26__ap; + wire n_0_56; + wire [31:0]registers_27__ap; + wire n_0_57; + wire [31:0]registers_28__ap; + wire n_0_58; + wire [31:0]registers_29__ap; + wire n_0_59; + wire [31:0]registers_30__ap; + wire n_0_60; + wire [31:0]registers_31__ap; + wire n_0_61; + wire [31:0]registers; + wire n_0_31; + wire n_0_30; + wire n_0_29; + wire n_0_28; + wire n_0_27; + wire n_0_26; + wire n_0_25; + wire n_0_24; + wire n_0_0_0; + wire n_0_0_1; + wire n_0_23; + wire n_0_22; + wire n_0_21; + wire n_0_20; + wire n_0_19; + wire n_0_18; + wire n_0_17; + wire n_0_16; + wire n_0_0_2; + wire n_0_0_3; + wire n_0_15; + wire n_0_14; + wire n_0_13; + wire n_0_12; + wire n_0_11; + wire n_0_10; + wire n_0_9; + wire n_0_8; + wire n_0_0_4; + wire n_0_0_5; + wire n_0_7; + wire n_0_0_6; + wire n_0_6; + wire n_0_0_7; + wire n_0_5; + wire n_0_0_8; + wire n_0_4; + wire n_0_0_9; + wire n_0_0_10; + wire n_0_3; + wire n_0_0_11; + wire n_0_2; + wire n_0_0_12; + wire n_0_1; + wire n_0_0_13; + wire n_0_0_14; + wire n_0_0_15; + wire n_0_0_16; + wire n_0_0_17; + wire n_0_0_18; + wire n_0_0_19; + wire n_0_0_20; + wire n_1_0_0; + wire n_1_0_1; + wire n_1_0_2; + wire n_1_0_3; + wire n_1_0_4; + wire n_1_0_5; + wire n_1_0_6; + wire n_1_0_7; + wire n_1_0_8; + wire n_1_0_9; + wire n_1_0_10; + wire n_1_0_11; + wire n_1_0_12; + wire n_1_0_13; + wire n_1_0_14; + wire n_1_0_15; + wire n_1_0_16; + wire n_1_0_17; + wire n_1_0_18; + wire n_1_0_19; + wire n_1_0_20; + wire n_1_0_21; + wire n_1_0_22; + wire n_1_0_23; + wire n_1_0_24; + wire n_1_0_25; + wire n_1_0_26; + wire n_1_0_27; + wire n_1_0_28; + wire n_1_0_29; + wire n_1_0_30; + wire n_1_0_31; + wire n_1_0_32; + wire n_1_0_33; + wire n_1_0_34; + wire n_1_0_35; + wire n_1_0_36; + wire n_1_0_37; + wire n_1_0_38; + wire n_1_0_39; + wire n_1_0_40; + wire n_1_0_41; + wire n_1_0_42; + wire n_1_0_43; + wire n_1_0_44; + wire n_1_0_45; + wire n_1_0_46; + wire n_1_0_47; + wire n_1_0_48; + wire n_1_0_49; + wire n_1_0_50; + wire n_1_0_51; + wire n_1_0_52; + wire n_1_0_53; + wire n_1_0_54; + wire n_1_0_55; + wire n_1_0_56; + wire n_1_0_57; + wire n_1_0_58; + wire n_1_0_59; + wire n_1_0_60; + wire n_1_0_61; + wire n_1_0_62; + wire n_1_0_63; + wire n_1_0_64; + wire n_1_0_65; + wire n_1_0_66; + wire n_1_0_67; + wire n_1_0_68; + wire n_1_0_69; + wire n_1_0_70; + wire n_1_0_71; + wire n_1_0_72; + wire n_1_0_73; + wire n_1_0_74; + wire n_1_0_75; + wire n_1_0_76; + wire n_1_0_77; + wire n_1_0_78; + wire n_1_0_79; + wire n_1_0_80; + wire n_1_0_81; + wire n_1_0_82; + wire n_1_0_83; + wire n_1_0_84; + wire n_1_0_85; + wire n_1_0_86; + wire n_1_0_87; + wire n_1_0_88; + wire n_1_0_89; + wire n_1_0_90; + wire n_1_0_91; + wire n_1_0_92; + wire n_1_0_93; + wire n_1_0_94; + wire n_1_0_95; + wire n_1_0_96; + wire n_1_0_97; + wire n_1_0_98; + wire n_1_0_99; + wire n_1_0_100; + wire n_1_0_101; + wire n_1_0_102; + wire n_1_0_103; + wire n_1_0_104; + wire n_1_0_105; + wire n_1_0_106; + wire n_1_0_107; + wire n_1_0_108; + wire n_1_0_109; + wire n_1_0_110; + wire n_1_0_111; + wire n_1_0_112; + wire n_1_0_113; + wire n_1_0_114; + wire n_1_0_115; + wire n_1_0_116; + wire n_1_0_117; + wire n_1_0_118; + wire n_1_0_119; + wire n_1_0_120; + wire n_1_0_121; + wire n_1_0_122; + wire n_1_0_123; + wire n_1_0_124; + wire n_1_0_125; + wire n_1_0_126; + wire n_1_0_127; + wire n_1_0_128; + wire n_1_0_129; + wire n_1_0_130; + wire n_1_0_131; + wire n_1_0_132; + wire n_1_0_133; + wire n_1_0_134; + wire n_1_0_135; + wire n_1_0_136; + wire n_1_0_137; + wire n_1_0_138; + wire n_1_0_139; + wire n_1_0_140; + wire n_1_0_141; + wire n_1_0_142; + wire n_1_0_143; + wire n_1_0_144; + wire n_1_0_145; + wire n_1_0_146; + wire n_1_0_147; + wire n_1_0_148; + wire n_1_0_149; + wire n_1_0_150; + wire n_1_0_151; + wire n_1_0_152; + wire n_1_0_153; + wire n_1_0_154; + wire n_1_0_155; + wire n_1_0_156; + wire n_1_0_157; + wire n_1_0_158; + wire n_1_0_159; + wire n_1_0_160; + wire n_1_0_161; + wire n_1_0_162; + wire n_1_0_163; + wire n_1_0_164; + wire n_1_0_165; + wire n_1_0_166; + wire n_1_0_167; + wire n_1_0_168; + wire n_1_0_169; + wire n_1_0_170; + wire n_1_0_171; + wire n_1_0_172; + wire n_1_0_173; + wire n_1_0_174; + wire n_1_0_175; + wire n_1_0_176; + wire n_1_0_177; + wire n_1_0_178; + wire n_1_0_179; + wire n_1_0_180; + wire n_1_0_181; + wire n_1_0_182; + wire n_1_0_183; + wire n_1_0_184; + wire n_1_0_185; + wire n_1_0_186; + wire n_1_0_187; + wire n_1_0_188; + wire n_1_0_189; + wire n_1_0_190; + wire n_1_0_191; + wire n_1_0_192; + wire n_1_0_193; + wire n_1_0_194; + wire n_1_0_195; + wire n_1_0_196; + wire n_1_0_197; + wire n_1_0_198; + wire n_1_0_199; + wire n_1_0_200; + wire n_1_0_201; + wire n_1_0_202; + wire n_1_0_203; + wire n_1_0_204; + wire n_1_0_205; + wire n_1_0_206; + wire n_1_0_207; + wire n_1_0_208; + wire n_1_0_209; + wire n_1_0_210; + wire n_1_0_211; + wire n_1_0_212; + wire n_1_0_213; + wire n_1_0_214; + wire n_1_0_215; + wire n_1_0_216; + wire n_1_0_217; + wire n_1_0_218; + wire n_1_0_219; + wire n_1_0_220; + wire n_1_0_221; + wire n_1_0_222; + wire n_1_0_223; + wire n_1_0_224; + wire n_1_0_225; + wire n_1_0_226; + wire n_1_0_227; + wire n_1_0_228; + wire n_1_0_229; + wire n_1_0_230; + wire n_1_0_231; + wire n_1_0_232; + wire n_1_0_233; + wire n_1_0_234; + wire n_1_0_235; + wire n_1_0_236; + wire n_1_0_237; + wire n_1_0_238; + wire n_1_0_239; + wire n_1_0_240; + wire n_1_0_241; + wire n_1_0_242; + wire n_1_0_243; + wire n_1_0_244; + wire n_1_0_245; + wire n_1_0_246; + wire n_1_0_247; + wire n_1_0_248; + wire n_1_0_249; + wire n_1_0_250; + wire n_1_0_251; + wire n_1_0_252; + wire n_1_0_253; + wire n_1_0_254; + wire n_1_0_255; + wire n_1_0_256; + wire n_1_0_257; + wire n_1_0_258; + wire n_1_0_259; + wire n_1_0_260; + wire n_1_0_261; + wire n_1_0_262; + wire n_1_0_263; + wire n_1_0_264; + wire n_1_0_265; + wire n_1_0_266; + wire n_1_0_267; + wire n_1_0_268; + wire n_1_0_269; + wire n_1_0_270; + wire n_1_0_271; + wire n_1_0_272; + wire n_1_0_273; + wire n_1_0_274; + wire n_1_0_275; + wire n_1_0_276; + wire n_1_0_277; + wire n_1_0_278; + wire n_1_0_279; + wire n_1_0_280; + wire n_1_0_281; + wire n_1_0_282; + wire n_1_0_283; + wire n_1_0_284; + wire n_1_0_285; + wire n_1_0_286; + wire n_1_0_287; + wire n_1_0_288; + wire n_1_0_289; + wire n_1_0_290; + wire n_1_0_291; + wire n_1_0_292; + wire n_1_0_293; + wire n_1_0_294; + wire n_1_0_295; + wire n_1_0_296; + wire n_1_0_297; + wire n_1_0_298; + wire n_1_0_299; + wire n_1_0_300; + wire n_1_0_301; + wire n_1_0_302; + wire n_1_0_303; + wire n_1_0_304; + wire n_1_0_305; + wire n_1_0_306; + wire n_1_0_307; + wire n_1_0_308; + wire n_1_0_309; + wire n_1_0_310; + wire n_1_0_311; + wire n_1_0_312; + wire n_1_0_313; + wire n_1_0_314; + wire n_1_0_315; + wire n_1_0_316; + wire n_1_0_317; + wire n_1_0_318; + wire n_1_0_319; + wire n_1_0_320; + wire n_1_0_321; + wire n_1_0_322; + wire n_1_0_323; + wire n_1_0_324; + wire n_1_0_325; + wire n_1_0_326; + wire n_1_0_327; + wire n_1_0_328; + wire n_1_0_329; + wire n_1_0_330; + wire n_1_0_331; + wire n_1_0_332; + wire n_1_0_333; + wire n_1_0_334; + wire n_1_0_335; + wire n_1_0_336; + wire n_1_0_337; + wire n_1_0_338; + wire n_1_0_339; + wire n_1_0_340; + wire n_1_0_341; + wire n_1_0_342; + wire n_1_0_343; + wire n_1_0_344; + wire n_1_0_345; + wire n_1_0_346; + wire n_1_0_347; + wire n_1_0_348; + wire n_1_0_349; + wire n_1_0_350; + wire n_1_0_351; + wire n_1_0_352; + wire n_1_0_353; + wire n_1_0_354; + wire n_1_0_355; + wire n_1_0_356; + wire n_1_0_357; + wire n_1_0_358; + wire n_1_0_359; + wire n_1_0_360; + wire n_1_0_361; + wire n_1_0_362; + wire n_1_0_363; + wire n_1_0_364; + wire n_1_0_365; + wire n_1_0_366; + wire n_1_0_367; + wire n_1_0_368; + wire n_1_0_369; + wire n_1_0_370; + wire n_1_0_371; + wire n_1_0_372; + wire n_1_0_373; + wire n_1_0_374; + wire n_1_0_375; + wire n_1_0_376; + wire n_1_0_377; + wire n_1_0_378; + wire n_1_0_379; + wire n_1_0_380; + wire n_1_0_381; + wire n_1_0_382; + wire n_1_0_383; + wire n_1_0_384; + wire n_1_0_385; + wire n_1_0_386; + wire n_1_0_387; + wire n_1_0_388; + wire n_1_0_389; + wire n_1_0_390; + wire n_1_0_391; + wire n_1_0_392; + wire n_1_0_393; + wire n_1_0_394; + wire n_1_0_395; + wire n_1_0_396; + wire n_1_0_397; + wire n_1_0_398; + wire n_1_0_399; + wire n_1_0_400; + wire n_1_0_401; + wire n_1_0_402; + wire n_1_0_403; + wire n_1_0_404; + wire n_1_0_405; + wire n_1_0_406; + wire n_1_0_407; + wire n_1_0_408; + wire n_1_0_409; + wire n_1_0_410; + wire n_1_0_411; + wire n_1_0_412; + wire n_1_0_413; + wire n_1_0_414; + wire n_1_0_415; + wire n_1_0_416; + wire n_1_0_417; + wire n_1_0_418; + wire n_1_0_419; + wire n_1_0_420; + wire n_1_0_421; + wire n_1_0_422; + wire n_1_0_423; + wire n_1_0_424; + wire n_1_0_425; + wire n_1_0_426; + wire n_1_0_427; + wire n_1_0_428; + wire n_1_0_429; + wire n_1_0_430; + wire n_1_0_431; + wire n_1_0_432; + wire n_1_0_433; + wire n_1_0_434; + wire n_1_0_435; + wire n_1_0_436; + wire n_1_0_437; + wire n_1_0_438; + wire n_1_0_439; + wire n_1_0_440; + wire n_1_0_441; + wire n_1_0_442; + wire n_1_0_443; + wire n_1_0_444; + wire n_1_0_445; + wire n_1_0_446; + wire n_1_0_447; + wire n_1_0_448; + wire n_1_0_449; + wire n_1_0_450; + wire n_1_0_451; + wire n_1_0_452; + wire n_1_0_453; + wire n_1_0_454; + wire n_1_0_455; + wire n_1_0_456; + wire n_1_0_457; + wire n_1_0_458; + wire n_1_0_459; + wire n_1_0_460; + wire n_1_0_461; + wire n_1_0_462; + wire n_1_0_463; + wire n_1_0_464; + wire n_1_0_465; + wire n_1_0_466; + wire n_1_0_467; + wire n_1_0_468; + wire n_1_0_469; + wire n_1_0_470; + wire n_1_0_471; + wire n_1_0_472; + wire n_1_0_473; + wire n_1_0_474; + wire n_1_0_475; + wire n_1_0_476; + wire n_1_0_477; + wire n_1_0_478; + wire n_1_0_479; + wire n_1_0_480; + wire n_1_0_481; + wire n_1_0_482; + wire n_1_0_483; + wire n_1_0_484; + wire n_1_0_485; + wire n_1_0_486; + wire n_1_0_487; + wire n_1_0_488; + wire n_1_0_489; + wire n_1_0_490; + wire n_1_0_491; + wire n_1_0_492; + wire n_1_0_493; + wire n_1_0_494; + wire n_1_0_495; + wire n_1_0_496; + wire n_1_0_497; + wire n_1_0_498; + wire n_1_0_499; + wire n_1_0_500; + wire n_1_0_501; + wire n_1_0_502; + wire n_1_0_503; + wire n_1_0_504; + wire n_1_0_505; + wire n_1_0_506; + wire n_1_0_507; + wire n_1_0_508; + wire n_1_0_509; + wire n_1_0_510; + wire n_1_0_511; + wire n_1_0_512; + wire n_1_0_513; + wire n_1_0_514; + wire n_1_0_515; + wire n_1_0_516; + wire n_1_0_517; + wire n_1_0_518; + wire n_1_0_519; + wire n_1_0_520; + wire n_1_0_521; + wire n_1_0_522; + wire n_1_0_523; + wire n_1_0_524; + wire n_1_0_525; + wire n_1_0_526; + wire n_1_0_527; + wire n_1_0_528; + wire n_1_0_529; + wire n_1_0_530; + wire n_1_0_531; + wire n_1_0_532; + wire n_1_0_533; + wire n_1_0_534; + wire n_1_0_535; + wire n_1_0_536; + wire n_1_0_537; + wire n_1_0_538; + wire n_1_0_539; + wire n_1_0_540; + wire n_1_0_541; + wire n_1_0_542; + wire n_1_0_543; + wire n_1_0_544; + wire n_1_0_545; + wire n_1_0_546; + wire n_1_0_547; + wire n_1_0_548; + wire n_1_0_549; + wire n_1_0_550; + wire n_1_0_551; + wire n_1_0_552; + wire n_1_0_553; + wire n_1_0_554; + wire n_1_0_555; + wire n_1_0_556; + wire n_1_0_557; + wire n_1_0_558; + wire n_1_0_559; + wire n_1_0_560; + wire n_1_0_561; + wire n_1_0_562; + wire n_1_0_563; + wire n_1_0_564; + wire n_1_0_565; + wire n_1_0_566; + wire n_1_0_567; + wire n_1_0_568; + wire n_1_0_569; + wire n_1_0_570; + wire n_1_0_571; + wire n_1_0_572; + wire n_1_0_573; + wire n_1_0_574; + wire n_1_0_575; + wire n_1_0_576; + wire n_1_0_577; + wire n_1_0_578; + wire n_1_0_579; + wire n_1_0_580; + wire n_1_0_581; + wire n_1_0_582; + wire n_1_0_583; + wire n_1_0_584; + wire n_1_0_585; + wire n_1_0_586; + wire n_1_0_587; + wire n_1_0_588; + wire n_1_0_589; + wire n_1_0_590; + wire n_1_0_591; + wire n_1_0_592; + wire n_1_0_593; + wire n_1_0_594; + wire n_1_0_595; + wire n_1_0_596; + wire n_1_0_597; + wire n_1_0_598; + wire n_1_0_599; + wire n_1_0_600; + wire n_1_0_601; + wire n_1_0_602; + wire n_1_0_603; + wire n_1_0_604; + wire n_1_0_605; + wire n_1_0_606; + wire n_1_0_607; + wire n_1_0_608; + wire n_1_0_609; + wire n_1_0_610; + wire n_1_0_611; + wire n_1_0_612; + wire n_1_0_613; + wire n_1_0_614; + wire n_1_0_615; + wire n_1_0_616; + wire n_1_0_617; + wire n_1_0_618; + wire n_1_0_619; + wire n_1_0_620; + wire n_1_0_621; + wire n_1_0_622; + wire n_1_0_623; + wire n_1_0_624; + wire n_1_0_625; + wire n_1_0_626; + wire n_1_0_627; + wire n_1_0_628; + wire n_1_0_629; + wire n_1_0_630; + wire n_1_0_631; + wire n_1_0_632; + wire n_1_0_633; + wire n_1_0_634; + wire n_1_0_635; + wire n_1_0_636; + wire n_1_0_637; + wire n_1_0_638; + wire n_1_0_639; + wire n_1_0_640; + wire n_1_0_641; + wire n_1_0_642; + wire n_1_0_643; + wire n_1_0_644; + wire n_1_0_645; + wire n_1_0_646; + wire n_1_0_647; + wire n_1_0_648; + wire n_1_0_649; + wire n_1_0_650; + wire n_1_0_651; + wire n_1_0_652; + wire n_1_0_653; + wire n_1_0_654; + wire n_1_0_655; + wire n_1_0_656; + wire n_1_0_657; + wire n_1_0_658; + wire n_1_0_659; + wire n_1_0_660; + wire n_1_0_661; + wire n_1_0_662; + wire n_1_0_663; + wire n_1_0_664; + wire n_1_0_665; + wire n_1_0_666; + wire n_1_0_667; + wire n_1_0_668; + wire n_1_0_669; + wire n_1_0_670; + wire n_1_0_671; + wire n_1_0_672; + wire n_1_0_673; + wire n_1_0_674; + wire n_1_0_675; + wire n_1_0_676; + wire n_1_0_677; + wire n_1_0_678; + wire n_1_0_679; + wire n_1_0_680; + wire n_1_0_681; + wire n_1_0_682; + wire n_1_0_683; + wire n_1_0_684; + wire n_1_0_685; + wire n_1_0_686; + wire n_1_0_687; + wire n_1_0_688; + wire n_1_0_689; + wire n_1_0_690; + wire n_1_0_691; + wire n_1_0_692; + wire n_1_0_693; + wire n_1_0_694; + wire n_1_0_695; + wire n_1_0_696; + wire n_1_0_697; + wire n_1_0_698; + wire n_1_0_699; + wire n_1_0_700; + wire n_1_0_701; + wire n_1_0_702; + wire n_1_0_703; + wire n_1_0_704; + wire n_1_0_705; + wire n_1_0_706; + wire n_1_0_707; + wire n_1_0_708; + wire n_1_0_709; + wire n_1_0_710; + wire n_1_0_711; + wire n_1_0_712; + wire n_1_0_713; + wire n_1_0_714; + wire n_1_0_715; + wire n_1_0_716; + wire n_1_0_717; + wire n_1_0_718; + wire n_1_0_719; + wire n_1_0_720; + wire n_1_0_721; + wire n_1_0_722; + wire n_1_0_723; + wire n_1_0_724; + wire n_1_0_725; + wire n_1_0_726; + wire n_1_0_727; + wire n_1_0_728; + wire n_1_0_729; + wire n_1_0_730; + wire n_1_0_731; + wire n_1_0_732; + wire n_1_0_733; + wire n_1_0_734; + wire n_1_0_735; + wire n_1_0_736; + wire n_1_0_737; + wire n_1_0_738; + wire n_1_0_739; + wire n_1_0_740; + wire n_1_0_741; + wire n_1_0_742; + wire n_1_0_743; + wire n_1_0_744; + wire n_1_0_745; + wire n_1_0_746; + wire n_1_0_747; + wire n_1_0_748; + wire n_1_0_749; + wire n_1_0_750; + wire n_1_0_751; + wire n_1_0_752; + wire n_1_0_753; + wire n_1_0_754; + wire n_1_0_755; + wire n_1_0_756; + wire n_1_0_757; + wire n_1_0_758; + wire n_1_0_759; + wire n_1_0_760; + wire n_1_0_761; + wire n_1_0_762; + wire n_1_0_763; + wire n_1_0_764; + wire n_1_0_765; + wire n_1_0_766; + wire n_1_0_767; + wire n_1_0_768; + wire n_1_0_769; + wire n_1_0_770; + wire n_1_0_771; + wire n_1_0_772; + wire n_1_0_773; + wire n_1_0_774; + wire n_1_0_775; + wire n_1_0_776; + wire n_1_0_777; + wire n_1_0_778; + wire n_1_0_779; + wire n_1_0_780; + wire n_1_0_781; + wire n_1_0_782; + wire n_1_0_783; + wire n_1_0_784; + wire n_1_0_785; + wire n_1_0_786; + wire n_1_0_787; + wire n_1_0_788; + wire n_1_0_789; + wire n_1_0_790; + wire n_1_0_791; + wire n_1_0_792; + wire n_1_0_793; + wire n_1_0_794; + wire n_1_0_795; + wire n_1_0_796; + wire n_1_0_797; + wire n_1_0_798; + wire n_1_0_799; + wire n_1_0_800; + wire n_1_0_801; + wire n_1_0_802; + wire n_1_0_803; + wire n_1_0_804; + wire n_1_0_805; + wire n_1_0_806; + wire n_1_0_807; + wire n_1_0_808; + wire n_1_0_809; + wire n_1_0_810; + wire n_1_0_811; + wire n_1_0_812; + wire n_1_0_813; + wire n_1_0_814; + wire n_1_0_815; + wire n_1_0_816; + wire n_1_0_817; + wire n_1_0_818; + wire n_1_0_819; + wire n_1_0_820; + wire n_1_0_821; + wire n_1_0_822; + wire n_1_0_823; + wire n_1_0_824; + wire n_1_0_825; + wire n_1_0_826; + wire n_1_0_827; + wire n_1_0_828; + wire n_1_0_829; + wire n_1_0_830; + wire n_1_0_831; + wire n_1_0_832; + wire n_1_0_833; + wire n_1_0_834; + wire n_1_0_835; + wire n_1_0_836; + wire n_1_0_837; + wire n_1_0_838; + wire n_1_0_839; + wire n_1_0_840; + wire n_1_0_841; + wire n_1_0_842; + wire n_1_0_843; + wire n_1_0_844; + wire n_1_0_845; + wire n_1_0_846; + wire n_1_0_847; + wire n_1_0_848; + wire n_1_0_849; + wire n_1_0_850; + wire n_1_0_851; + wire n_1_0_852; + wire n_1_0_853; + wire n_1_0_854; + wire n_1_0_855; + wire n_1_0_856; + wire n_1_0_857; + wire n_1_0_858; + wire n_1_0_859; + wire n_1_0_860; + wire n_1_0_861; + wire n_1_0_862; + wire n_1_0_863; + wire n_1_0_864; + wire n_1_0_865; + wire n_1_0_866; + wire n_1_0_867; + wire n_1_0_868; + wire n_1_0_869; + wire n_1_0_870; + wire n_1_0_871; + wire n_1_0_872; + wire n_1_0_873; + wire n_1_0_874; + wire n_1_0_875; + wire n_1_0_876; + wire n_1_0_877; + wire n_1_0_878; + wire n_1_0_879; + wire n_1_0_880; + wire n_1_0_881; + wire n_1_0_882; + wire n_1_0_883; + wire n_1_0_884; + wire n_1_0_885; + wire n_1_0_886; + wire n_1_0_887; + wire n_1_0_888; + wire n_1_0_889; + wire n_1_0_890; + wire n_1_0_891; + wire n_1_0_892; + wire n_1_0_893; + wire n_1_0_894; + wire n_1_0_895; + wire n_1_0_896; + wire n_1_0_897; + wire n_1_0_898; + wire n_1_0_899; + wire n_1_0_900; + wire n_1_0_901; + wire n_1_0_902; + wire n_1_0_903; + wire n_1_0_904; + wire n_1_0_905; + wire n_1_0_906; + wire n_1_0_907; + wire n_1_0_908; + wire n_1_0_909; + wire n_1_0_910; + wire n_1_0_911; + wire n_1_0_912; + wire n_1_0_913; + wire n_1_0_914; + wire n_1_0_915; + wire n_1_0_916; + wire n_1_0_917; + wire n_1_0_918; + wire n_1_0_919; + wire n_1_0_920; + wire n_1_0_921; + wire n_1_0_922; + wire n_1_0_923; + wire n_1_0_924; + wire n_1_0_925; + wire n_1_0_926; + wire n_1_0_927; + wire n_1_0_928; + wire n_1_0_929; + wire n_1_0_930; + wire n_1_0_931; + wire n_1_0_932; + wire n_1_0_933; + wire n_1_0_934; + wire n_1_0_935; + wire n_1_0_936; + wire n_1_0_937; + wire n_1_0_938; + wire n_1_0_939; + wire n_1_0_940; + wire n_1_0_941; + wire n_1_0_942; + wire n_1_0_943; + wire n_1_0_944; + wire n_1_0_945; + wire n_1_0_946; + wire n_1_0_947; + wire n_1_0_948; + wire n_1_0_949; + wire n_1_0_950; + wire n_1_0_951; + wire n_1_0_952; + wire n_1_0_953; + wire n_1_0_954; + wire n_1_0_955; + wire n_1_0_956; + wire n_1_0_957; + wire n_1_0_958; + wire n_1_0_959; + wire n_1_0_960; + wire n_1_0_961; + wire n_1_0_962; + wire n_1_0_963; + wire n_1_0_964; + wire n_1_0_965; + wire n_1_0_966; + wire n_1_0_967; + wire n_1_0_968; + wire n_1_0_969; + wire n_1_0_970; + wire n_1_0_971; + wire n_1_0_972; + wire n_1_0_973; + wire n_1_0_974; + wire n_1_0_975; + wire n_1_0_976; + wire n_1_0_977; + wire n_1_0_978; + wire n_1_0_979; + wire n_1_0_980; + wire n_1_0_981; + wire n_1_0_982; + wire n_1_0_983; + wire n_1_0_984; + wire n_1_0_985; + wire n_1_0_986; + wire n_1_0_987; + wire n_1_0_988; + wire n_1_0_989; + wire n_1_0_990; + wire n_1_0_991; + wire n_1_0_992; + wire n_1_0_993; + wire n_1_0_994; + wire n_1_0_995; + wire n_1_0_996; + wire n_1_0_997; + wire n_1_0_998; + wire n_1_0_999; + wire n_1_0_1000; + wire n_1_0_1001; + wire n_1_0_1002; + wire n_1_0_1003; + wire n_1_0_1004; + wire n_1_0_1005; + wire n_1_0_1006; + wire n_1_0_1007; + wire n_1_0_1008; + wire n_1_0_1009; + wire n_1_0_1010; + wire n_1_0_1011; + wire n_1_0_1012; + wire n_1_0_1013; + wire n_1_0_1014; + wire n_1_0_1015; + wire n_1_0_1016; + wire n_1_0_1017; + wire n_1_0_1018; + wire n_1_0_1019; + wire n_1_0_1020; + wire n_1_0_1021; + wire n_1_0_1022; + wire n_1_0_1023; + wire n_1_0_1024; + wire n_1_0_1025; + wire n_1_0_1026; + wire n_1_0_1027; + wire n_1_0_1028; + wire n_1_0_1029; + wire n_1_0_1030; + wire n_1_0_1031; + wire n_1_0_1032; + wire n_1_0_1033; + wire n_1_0_1034; + wire n_1_0_1035; + wire n_1_0_1036; + wire n_1_0_1037; + wire n_1_0_1038; + wire n_1_0_1039; + wire n_1_0_1040; + wire n_1_0_1041; + wire n_1_0_1042; + wire n_1_0_1043; + wire n_1_0_1044; + wire n_1_0_1045; + wire n_1_0_1046; + wire n_1_0_1047; + wire n_1_0_1048; + wire n_1_0_1049; + wire n_1_0_1050; + wire n_1_0_1051; + wire n_1_0_1052; + wire n_1_0_1053; + wire n_1_0_1054; + wire n_1_0_1055; + wire n_1_0_1056; + wire n_1_0_1057; + wire n_1_0_1058; + wire n_1_0_1059; + wire n_1_0_1060; + wire n_1_0_1061; + wire n_1_0_1062; + wire n_1_0_1063; + wire n_1_0_1064; + wire n_1_0_1065; + wire n_1_0_1066; + wire n_1_0_1067; + wire n_1_0_1068; + wire n_1_0_1069; + wire n_1_0_1070; + wire n_1_0_1071; + wire n_1_0_1072; + wire n_1_0_1073; + wire n_1_0_1074; + wire n_1_0_1075; + wire n_1_0_1076; + wire n_1_0_1077; + wire n_1_0_1078; + wire n_1_0_1079; + wire n_1_0_1080; + wire n_1_0_1081; + wire n_1_0_1082; + wire n_1_0_1083; + wire n_1_0_1084; + wire n_1_0_1085; + wire n_1_0_1086; + wire n_1_0_1087; + wire n_1_0_1088; + wire n_1_0_1089; + wire n_1_0_1090; + wire n_1_0_1091; + wire n_1_0_1092; + wire n_1_0_1093; + wire n_1_0_1094; + wire n_1_0_1095; + wire n_1_0_1096; + wire n_1_0_1097; + wire n_1_0_1098; + wire n_1_0_1099; + wire n_1_0_1100; + wire n_1_0_1101; + wire n_1_0_1102; + wire n_1_0_1103; + wire n_1_0_1104; + wire n_1_0_1105; + wire n_1_0_1106; + wire n_1_0_1107; + wire n_1_0_1108; + wire n_1_0_1109; + wire n_1_0_1110; + wire n_1_0_1111; + wire n_1_0_1112; + wire n_1_0_1113; + wire n_1_0_1114; + wire n_1_0_1115; + wire n_1_0_1116; + wire n_1_0_1117; + wire n_1_0_1118; + wire n_1_0_1119; + wire n_1_0_1120; + wire n_1_0_1121; + wire n_1_0_1122; + wire n_1_0_1123; + wire n_1_0_1124; + wire n_1_0_1125; + wire n_1_0_1126; + wire n_1_0_1127; + wire n_1_0_1128; + wire n_1_0_1129; + wire n_1_0_1130; + wire n_1_0_1131; + wire n_1_0_1132; + wire n_1_0_1133; + wire n_1_0_1134; + wire n_1_0_1135; + wire n_1_0_1136; + wire n_1_0_1137; + wire n_1_0_1138; + wire n_1_0_1139; + wire n_1_0_1140; + wire n_1_0_1141; + wire n_1_0_1142; + wire n_1_0_1143; + wire n_1_0_1144; + wire n_1_0_1145; + wire n_1_0_1146; + wire n_1_0_1147; + wire n_1_0_1148; + wire n_1_0_1149; + wire n_1_0_1150; + wire n_1_0_1151; + wire n_1_0_1152; + wire n_1_0_1153; + wire n_1_0_1154; + wire n_1_0_1155; + wire n_1_0_1156; + wire n_1_0_1157; + wire n_1_0_1158; + wire n_1_0_1159; + wire n_1_0_1160; + wire n_1_0_1161; + wire n_1_0_1162; + wire n_1_0_1163; + wire n_1_0_1164; + wire n_1_0_1165; + wire n_1_0_1166; + wire n_1_0_1167; + wire n_1_0_1168; + wire n_1_0_1169; + wire n_1_0_1170; + wire n_1_0_1171; + wire n_1_0_1172; + wire n_1_0_1173; + wire n_1_0_1174; + wire n_1_0_1175; + wire n_1_0_1176; + wire n_1_0_1177; + wire n_1_0_1178; + wire n_1_0_1179; + wire n_1_0_1180; + wire n_1_0_1181; + wire n_1_0_1182; + wire n_1_0_1183; + wire n_1_0_1184; + wire n_1_0_1185; + wire n_1_0_1186; + wire n_1_0_1187; + wire n_1_0_1188; + wire n_1_0_1189; + wire n_1_0_1190; + wire n_1_0_1191; + wire n_1_0_1192; + wire n_1_0_1193; + wire n_1_0_1194; + wire n_1_0_1195; + wire n_1_0_1196; + wire n_1_0_1197; + wire n_1_0_1198; + wire n_1_0_1199; + wire n_1_0_1200; + wire n_1_0_1201; + wire n_1_0_1202; + wire n_1_0_1203; + wire n_1_0_1204; + wire n_1_0_1205; + wire n_1_0_1206; + wire n_1_0_1207; + wire n_1_0_1208; + wire n_1_0_1209; + wire n_1_0_1210; + wire n_1_0_1211; + wire n_1_0_1212; + wire n_1_0_1213; + wire n_1_0_1214; + wire n_1_0_1215; + wire n_1_0_1216; + wire n_1_0_1217; + wire n_1_0_1218; + wire n_1_0_1219; + wire n_1_0_1220; + wire n_1_0_1221; + wire n_1_0_1222; + wire n_1_0_1223; + wire n_1_0_1224; + wire n_1_0_1225; + wire n_1_0_1226; + wire n_1_0_1227; + wire n_1_0_1228; + wire n_1_0_1229; + wire n_1_0_1230; + wire n_1_0_1231; + wire n_1_0_1232; + wire n_1_0_1233; + wire n_1_0_1234; + wire n_1_0_1235; + wire n_1_0_1236; + wire n_1_0_1237; + wire n_1_0_1238; + wire n_1_0_1239; + wire n_1_0_1240; + wire n_1_0_1241; + wire n_1_0_1242; + wire n_1_0_1243; + wire n_1_0_1244; + wire n_1_0_1245; + wire n_1_0_1246; + wire n_1_0_1247; + wire n_1_0_1248; + wire n_1_0_1249; + wire n_1_0_1250; + wire n_1_0_1251; + wire n_1_0_1252; + wire n_1_0_1253; + wire n_1_0_1254; + wire n_1_0_1255; + wire n_1_0_1256; + wire n_1_0_1257; + wire n_1_0_1258; + wire n_1_0_1259; + wire n_1_0_1260; + wire n_1_0_1261; + wire n_1_0_1262; + wire n_1_0_1263; + wire n_1_0_1264; + wire n_1_0_1265; + wire n_1_0_1266; + wire n_1_0_1267; + wire n_1_0_1268; + wire n_1_0_1269; + wire n_1_0_1270; + wire n_1_0_1271; + wire n_1_0_1272; + wire n_1_0_1273; + wire n_1_0_1274; + wire n_1_0_1275; + wire n_1_0_1276; + wire n_1_0_1277; + wire n_1_0_1278; + wire n_1_0_1279; + wire n_1_0_1280; + wire n_1_0_1281; + wire n_1_0_1282; + wire n_1_0_1283; + wire n_1_0_1284; + wire n_1_0_1285; + wire n_1_0_1286; + wire n_1_0_1287; + wire n_1_0_1288; + wire n_1_0_1289; + wire n_1_0_1290; + wire n_1_0_1291; + wire n_1_0_1292; + wire n_1_0_1293; + wire n_1_0_1294; + wire n_1_0_1295; + wire n_1_0_1296; + wire n_1_0_1297; + wire n_1_0_1298; + wire n_1_0_1299; + wire n_1_0_1300; + wire n_1_0_1301; + wire n_1_0_1302; + wire n_1_0_1303; + wire n_1_0_1304; + wire n_1_0_1305; + wire n_1_0_1306; + wire n_1_0_1307; + wire n_1_0_1308; + wire n_1_0_1309; + + INV_X1_LVT i_0_0_79 (.A(reset), .ZN(n_0_0_16)); + AND2_X1_LVT i_0_0_31 (.A1(n_0_0_16), .A2(WRd[31]), .ZN(registers[31])); + INV_X1_LVT i_0_0_81 (.A(Rd[1]), .ZN(n_0_0_18)); + INV_X1_LVT i_0_0_80 (.A(Rd[0]), .ZN(n_0_0_17)); + NAND3_X1_LVT i_0_0_69 (.A1(n_0_0_18), .A2(n_0_0_17), .A3(Rd[2]), .ZN(n_0_0_9)); + NAND3_X1_LVT i_0_0_41 (.A1(Rd[3]), .A2(WrReg), .A3(Rd[4]), .ZN(n_0_0_1)); + OAI21_X1_LVT i_0_0_35 (.A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_1), .ZN(n_0_28)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[28]_reg (.CK(clk), .E(n_0_28), + .SE(dftIn), .GCK(n_0_58)); + SDFF_X1_LVT \registers_reg[28][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_28__ap[31]), .CK(n_0_58), .Q(registers_28__ap[31]), .QN()); + INV_X1_LVT i_1_0_1370 (.A(Rs1[0]), .ZN(n_1_0_1306)); + NAND3_X1_LVT i_1_0_1354 (.A1(n_1_0_1306), .A2(Rs1[3]), .A3(Rs1[4]), .ZN( + n_1_0_1290)); + INV_X1_LVT i_1_0_1373 (.A(Rs1[2]), .ZN(n_1_0_1309)); + OR2_X1_LVT i_1_0_1348 (.A1(n_1_0_1309), .A2(Rs1[1]), .ZN(n_1_0_1284)); + NOR2_X1_LVT i_1_0_1347 (.A1(n_1_0_1290), .A2(n_1_0_1284), .ZN(n_1_0_1283)); + NOR4_X1_LVT i_1_0_1342 (.A1(n_1_0_1284), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), + .ZN(n_1_0_1278)); + INV_X1_LVT i_0_0_83 (.A(WrReg), .ZN(n_0_0_20)); + OR3_X1_LVT i_0_0_77 (.A1(n_0_0_20), .A2(Rd[4]), .A3(Rd[3]), .ZN(n_0_0_14)); + OAI21_X1_LVT i_0_0_68 (.A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_9), .ZN(n_0_4)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[4]_reg (.CK(clk), .E(n_0_4), + .SE(dftIn), .GCK(n_0_34)); + SDFF_X1_LVT \registers_reg[4][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_4__ap[31]), .CK(n_0_34), .Q(registers_4__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1320 (.A1(registers_28__ap[31]), .A2(n_1_0_1283), .B1( + n_1_0_1278), .B2(registers_4__ap[31]), .ZN(n_1_0_1256)); + NAND2_X1_LVT i_0_0_70 (.A1(n_0_0_18), .A2(n_0_0_17), .ZN(n_0_0_10)); + INV_X1_LVT i_0_0_82 (.A(Rd[4]), .ZN(n_0_0_19)); + OR3_X1_LVT i_0_0_51 (.A1(n_0_0_20), .A2(n_0_0_19), .A3(Rd[3]), .ZN(n_0_0_3)); + OR2_X1_LVT i_0_0_50 (.A1(n_0_0_3), .A2(Rd[2]), .ZN(n_0_0_2)); + OAI21_X1_LVT i_0_0_49 (.A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_2), .ZN(n_0_16)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[16]_reg (.CK(clk), .E(n_0_16), + .SE(dftIn), .GCK(n_0_46)); + SDFF_X1_LVT \registers_reg[16][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_16__ap[31]), .CK(n_0_46), .Q(registers_16__ap[31]), .QN()); + INV_X1_LVT i_1_0_1371 (.A(Rs1[3]), .ZN(n_1_0_1307)); + NAND3_X1_LVT i_1_0_1363 (.A1(n_1_0_1307), .A2(n_1_0_1306), .A3(Rs1[4]), + .ZN(n_1_0_1299)); + OR2_X1_LVT i_1_0_1357 (.A1(Rs1[1]), .A2(Rs1[2]), .ZN(n_1_0_1293)); + NOR2_X1_LVT i_1_0_1331 (.A1(n_1_0_1299), .A2(n_1_0_1293), .ZN(n_1_0_1267)); + NAND2_X1_LVT i_1_0_1365 (.A1(Rs1[1]), .A2(Rs1[2]), .ZN(n_1_0_1301)); + NAND3_X1_LVT i_1_0_1344 (.A1(Rs1[4]), .A2(Rs1[3]), .A3(Rs1[0]), .ZN( + n_1_0_1280)); + NOR2_X1_LVT i_1_0_1330 (.A1(n_1_0_1301), .A2(n_1_0_1280), .ZN(n_1_0_1266)); + NAND3_X1_LVT i_0_0_63 (.A1(Rd[2]), .A2(Rd[1]), .A3(Rd[0]), .ZN(n_0_0_6)); + OAI21_X1_LVT i_0_0_32 (.A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_1), .ZN(n_0_31)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[31]_reg (.CK(clk), .E(n_0_31), + .SE(dftIn), .GCK(n_0_61)); + SDFF_X1_LVT \registers_reg[31][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_31__ap[31]), .CK(n_0_61), .Q(registers_31__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1329 (.A1(registers_16__ap[31]), .A2(n_1_0_1267), .B1( + n_1_0_1266), .B2(registers_31__ap[31]), .ZN(n_1_0_1265)); + NAND3_X1_LVT i_0_0_65 (.A1(n_0_0_17), .A2(Rd[1]), .A3(Rd[2]), .ZN(n_0_0_7)); + OAI21_X1_LVT i_0_0_64 (.A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_7), .ZN(n_0_6)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[6]_reg (.CK(clk), .E(n_0_6), + .SE(dftIn), .GCK(n_0_36)); + SDFF_X1_LVT \registers_reg[6][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_6__ap[31]), .CK(n_0_36), .Q(registers_6__ap[31]), .QN()); + NOR4_X1_LVT i_1_0_1364 (.A1(n_1_0_1301), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), + .ZN(n_1_0_1300)); + INV_X1_LVT i_1_0_1372 (.A(Rs1[4]), .ZN(n_1_0_1308)); + NAND3_X1_LVT i_1_0_1339 (.A1(n_1_0_1308), .A2(n_1_0_1307), .A3(Rs1[0]), + .ZN(n_1_0_1275)); + NOR2_X1_LVT i_1_0_1338 (.A1(n_1_0_1293), .A2(n_1_0_1275), .ZN(n_1_0_1274)); + NAND2_X1_LVT i_0_0_78 (.A1(n_0_0_18), .A2(Rd[0]), .ZN(n_0_0_15)); + OR2_X1_LVT i_0_0_76 (.A1(n_0_0_14), .A2(Rd[2]), .ZN(n_0_0_13)); + OAI21_X1_LVT i_0_0_75 (.A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_13), .ZN(n_0_1)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[1]_reg (.CK(clk), .E(n_0_1), + .SE(dftIn), .GCK(n_0_0)); + SDFF_X1_LVT \registers_reg[1][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_1__ap[31]), .CK(n_0_0), .Q(registers_1__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1319 (.A1(registers_6__ap[31]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[31]), .ZN(n_1_0_1255)); + OAI21_X1_LVT i_0_0_42 (.A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_3), .ZN(n_0_23)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[23]_reg (.CK(clk), .E(n_0_23), + .SE(dftIn), .GCK(n_0_53)); + SDFF_X1_LVT \registers_reg[23][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_23__ap[31]), .CK(n_0_53), .Q(registers_23__ap[31]), .QN()); + NAND3_X1_LVT i_1_0_1360 (.A1(n_1_0_1307), .A2(Rs1[0]), .A3(Rs1[4]), .ZN( + n_1_0_1296)); + NOR2_X1_LVT i_1_0_1328 (.A1(n_1_0_1301), .A2(n_1_0_1296), .ZN(n_1_0_1264)); + NOR2_X1_LVT i_1_0_1327 (.A1(n_1_0_1301), .A2(n_1_0_1275), .ZN(n_1_0_1263)); + OAI21_X1_LVT i_0_0_62 (.A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_6), .ZN(n_0_7)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[7]_reg (.CK(clk), .E(n_0_7), + .SE(dftIn), .GCK(n_0_37)); + SDFF_X1_LVT \registers_reg[7][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_7__ap[31]), .CK(n_0_37), .Q(registers_7__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1326 (.A1(registers_23__ap[31]), .A2(n_1_0_1264), .B1( + n_1_0_1263), .B2(registers_7__ap[31]), .ZN(n_1_0_1262)); + INV_X1_LVT i_1_0_1325 (.A(n_1_0_1262), .ZN(n_1_0_1261)); + NAND2_X1_LVT i_1_0_1362 (.A1(n_1_0_1309), .A2(Rs1[1]), .ZN(n_1_0_1298)); + NOR2_X1_LVT i_1_0_1359 (.A1(n_1_0_1298), .A2(n_1_0_1296), .ZN(n_1_0_1295)); + NAND2_X1_LVT i_0_0_72 (.A1(Rd[1]), .A2(Rd[0]), .ZN(n_0_0_11)); + OAI21_X1_LVT i_0_0_46 (.A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_2), .ZN(n_0_19)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[19]_reg (.CK(clk), .E(n_0_19), + .SE(dftIn), .GCK(n_0_49)); + SDFF_X1_LVT \registers_reg[19][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_19__ap[31]), .CK(n_0_49), .Q(registers_19__ap[31]), .QN()); + NAND3_X1_LVT i_0_0_67 (.A1(n_0_0_18), .A2(Rd[0]), .A3(Rd[2]), .ZN(n_0_0_8)); + OAI21_X1_LVT i_0_0_66 (.A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_8), .ZN(n_0_5)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[5]_reg (.CK(clk), .E(n_0_5), + .SE(dftIn), .GCK(n_0_35)); + SDFF_X1_LVT \registers_reg[5][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_5__ap[31]), .CK(n_0_35), .Q(registers_5__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1337 (.A1(n_1_0_1284), .A2(n_1_0_1275), .ZN(n_1_0_1273)); + AOI221_X1_LVT i_1_0_1318 (.A(n_1_0_1261), .B1(n_1_0_1295), .B2( + registers_19__ap[31]), .C1(registers_5__ap[31]), .C2(n_1_0_1273), .ZN( + n_1_0_1254)); + NAND2_X1_LVT i_0_0_74 (.A1(n_0_0_17), .A2(Rd[1]), .ZN(n_0_0_12)); + NAND3_X1_LVT i_0_0_61 (.A1(n_0_0_19), .A2(WrReg), .A3(Rd[3]), .ZN(n_0_0_5)); + OR2_X1_LVT i_0_0_60 (.A1(n_0_0_5), .A2(Rd[2]), .ZN(n_0_0_4)); + OAI21_X1_LVT i_0_0_57 (.A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_4), .ZN(n_0_10)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[10]_reg (.CK(clk), .E(n_0_10), + .SE(dftIn), .GCK(n_0_40)); + SDFF_X1_LVT \registers_reg[10][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_10__ap[31]), .CK(n_0_40), .Q(registers_10__ap[31]), .QN()); + NAND3_X1_LVT i_1_0_1352 (.A1(n_1_0_1308), .A2(n_1_0_1306), .A3(Rs1[3]), + .ZN(n_1_0_1288)); + NOR2_X1_LVT i_1_0_1351 (.A1(n_1_0_1298), .A2(n_1_0_1288), .ZN(n_1_0_1287)); + NOR2_X1_LVT i_1_0_1349 (.A1(n_1_0_1298), .A2(n_1_0_1290), .ZN(n_1_0_1285)); + OR2_X1_LVT i_0_0_40 (.A1(n_0_0_1), .A2(Rd[2]), .ZN(n_0_0_0)); + OAI21_X1_LVT i_0_0_37 (.A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_0), .ZN(n_0_26)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[26]_reg (.CK(clk), .E(n_0_26), + .SE(dftIn), .GCK(n_0_56)); + SDFF_X1_LVT \registers_reg[26][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_26__ap[31]), .CK(n_0_56), .Q(registers_26__ap[31]), .QN()); + OAI21_X1_LVT i_0_0_59 (.A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_4), .ZN(n_0_8)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[8]_reg (.CK(clk), .E(n_0_8), + .SE(dftIn), .GCK(n_0_38)); + SDFF_X1_LVT \registers_reg[8][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_8__ap[31]), .CK(n_0_38), .Q(registers_8__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1346 (.A1(n_1_0_1293), .A2(n_1_0_1288), .ZN(n_1_0_1282)); + AOI222_X1_LVT i_1_0_1317 (.A1(registers_10__ap[31]), .A2(n_1_0_1287), + .B1(n_1_0_1285), .B2(registers_26__ap[31]), .C1(registers_8__ap[31]), + .C2(n_1_0_1282), .ZN(n_1_0_1253)); + NAND4_X1_LVT i_1_0_1316 (.A1(n_1_0_1265), .A2(n_1_0_1255), .A3(n_1_0_1254), + .A4(n_1_0_1253), .ZN(n_1_0_1252)); + NAND3_X1_LVT i_1_0_1356 (.A1(n_1_0_1308), .A2(Rs1[3]), .A3(Rs1[0]), .ZN( + n_1_0_1292)); + NOR2_X1_LVT i_1_0_1355 (.A1(n_1_0_1293), .A2(n_1_0_1292), .ZN(n_1_0_1291)); + OAI21_X1_LVT i_0_0_58 (.A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_4), .ZN(n_0_9)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[9]_reg (.CK(clk), .E(n_0_9), + .SE(dftIn), .GCK(n_0_39)); + SDFF_X1_LVT \registers_reg[9][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_9__ap[31]), .CK(n_0_39), .Q(registers_9__ap[31]), .QN()); + OAI21_X1_LVT i_0_0_34 (.A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_1), .ZN(n_0_29)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[29]_reg (.CK(clk), .E(n_0_29), + .SE(dftIn), .GCK(n_0_59)); + SDFF_X1_LVT \registers_reg[29][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_29__ap[31]), .CK(n_0_59), .Q(registers_29__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1340 (.A1(n_1_0_1284), .A2(n_1_0_1280), .ZN(n_1_0_1276)); + AOI221_X1_LVT i_1_0_1315 (.A(n_1_0_1252), .B1(n_1_0_1291), .B2( + registers_9__ap[31]), .C1(registers_29__ap[31]), .C2(n_1_0_1276), .ZN( + n_1_0_1251)); + OAI21_X1_LVT i_0_0_47 (.A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_2), .ZN(n_0_18)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[18]_reg (.CK(clk), .E(n_0_18), + .SE(dftIn), .GCK(n_0_48)); + SDFF_X1_LVT \registers_reg[18][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_18__ap[31]), .CK(n_0_48), .Q(registers_18__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1361 (.A1(n_1_0_1299), .A2(n_1_0_1298), .ZN(n_1_0_1297)); + NOR2_X1_LVT i_1_0_1336 (.A1(n_1_0_1301), .A2(n_1_0_1290), .ZN(n_1_0_1272)); + OAI21_X1_LVT i_0_0_33 (.A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_1), .ZN(n_0_30)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[30]_reg (.CK(clk), .E(n_0_30), + .SE(dftIn), .GCK(n_0_60)); + SDFF_X1_LVT \registers_reg[30][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_30__ap[31]), .CK(n_0_60), .Q(registers_30__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1314 (.A1(registers_18__ap[31]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[31]), .ZN(n_1_0_1250)); + OAI21_X1_LVT i_0_0_39 (.A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_0), .ZN(n_0_24)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[24]_reg (.CK(clk), .E(n_0_24), + .SE(dftIn), .GCK(n_0_54)); + SDFF_X1_LVT \registers_reg[24][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_24__ap[31]), .CK(n_0_54), .Q(registers_24__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1353 (.A1(n_1_0_1293), .A2(n_1_0_1290), .ZN(n_1_0_1289)); + NOR2_X1_LVT i_1_0_1324 (.A1(n_1_0_1288), .A2(n_1_0_1284), .ZN(n_1_0_1260)); + OAI21_X1_LVT i_0_0_55 (.A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_5), .ZN(n_0_12)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[12]_reg (.CK(clk), .E(n_0_12), + .SE(dftIn), .GCK(n_0_42)); + SDFF_X1_LVT \registers_reg[12][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_12__ap[31]), .CK(n_0_42), .Q(registers_12__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1313 (.A1(registers_24__ap[31]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[31]), .ZN(n_1_0_1249)); + OAI21_X1_LVT i_0_0_43 (.A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_3), .ZN(n_0_22)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[22]_reg (.CK(clk), .E(n_0_22), + .SE(dftIn), .GCK(n_0_52)); + SDFF_X1_LVT \registers_reg[22][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_22__ap[31]), .CK(n_0_52), .Q(registers_22__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1358 (.A1(n_1_0_1301), .A2(n_1_0_1299), .ZN(n_1_0_1294)); + NOR2_X1_LVT i_1_0_1323 (.A1(n_1_0_1296), .A2(n_1_0_1284), .ZN(n_1_0_1259)); + OAI21_X1_LVT i_0_0_44 (.A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_3), .ZN(n_0_21)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[21]_reg (.CK(clk), .E(n_0_21), + .SE(dftIn), .GCK(n_0_51)); + SDFF_X1_LVT \registers_reg[21][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_21__ap[31]), .CK(n_0_51), .Q(registers_21__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1312 (.A1(registers_22__ap[31]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[31]), .ZN(n_1_0_1248)); + NAND3_X1_LVT i_1_0_1311 (.A1(n_1_0_1250), .A2(n_1_0_1249), .A3(n_1_0_1248), + .ZN(n_1_0_1247)); + NOR2_X1_LVT i_1_0_1335 (.A1(n_1_0_1296), .A2(n_1_0_1293), .ZN(n_1_0_1271)); + OAI21_X1_LVT i_0_0_48 (.A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_2), .ZN(n_0_17)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[17]_reg (.CK(clk), .E(n_0_17), + .SE(dftIn), .GCK(n_0_47)); + SDFF_X1_LVT \registers_reg[17][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_17__ap[31]), .CK(n_0_47), .Q(registers_17__ap[31]), .QN()); + OAI21_X1_LVT i_0_0_45 (.A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_3), .ZN(n_0_20)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[20]_reg (.CK(clk), .E(n_0_20), + .SE(dftIn), .GCK(n_0_50)); + SDFF_X1_LVT \registers_reg[20][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_20__ap[31]), .CK(n_0_50), .Q(registers_20__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1345 (.A1(n_1_0_1299), .A2(n_1_0_1284), .ZN(n_1_0_1281)); + AOI221_X1_LVT i_1_0_1310 (.A(n_1_0_1247), .B1(n_1_0_1271), .B2( + registers_17__ap[31]), .C1(registers_20__ap[31]), .C2(n_1_0_1281), + .ZN(n_1_0_1246)); + OAI21_X1_LVT i_0_0_36 (.A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_0), .ZN(n_0_27)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[27]_reg (.CK(clk), .E(n_0_27), + .SE(dftIn), .GCK(n_0_57)); + SDFF_X1_LVT \registers_reg[27][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_27__ap[31]), .CK(n_0_57), .Q(registers_27__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1343 (.A1(n_1_0_1298), .A2(n_1_0_1280), .ZN(n_1_0_1279)); + NOR2_X1_LVT i_1_0_1334 (.A1(n_1_0_1298), .A2(n_1_0_1292), .ZN(n_1_0_1270)); + OAI21_X1_LVT i_0_0_56 (.A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_4), .ZN(n_0_11)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[11]_reg (.CK(clk), .E(n_0_11), + .SE(dftIn), .GCK(n_0_41)); + SDFF_X1_LVT \registers_reg[11][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_11__ap[31]), .CK(n_0_41), .Q(registers_11__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1309 (.A1(registers_27__ap[31]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[31]), .ZN(n_1_0_1245)); + OAI21_X1_LVT i_0_0_54 (.A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_5), .ZN(n_0_13)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[13]_reg (.CK(clk), .E(n_0_13), + .SE(dftIn), .GCK(n_0_43)); + SDFF_X1_LVT \registers_reg[13][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_13__ap[31]), .CK(n_0_43), .Q(registers_13__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1341 (.A1(n_1_0_1292), .A2(n_1_0_1284), .ZN(n_1_0_1277)); + NOR2_X1_LVT i_1_0_1333 (.A1(n_1_0_1293), .A2(n_1_0_1280), .ZN(n_1_0_1269)); + OAI21_X1_LVT i_0_0_38 (.A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_0), .ZN(n_0_25)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[25]_reg (.CK(clk), .E(n_0_25), + .SE(dftIn), .GCK(n_0_55)); + SDFF_X1_LVT \registers_reg[25][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_25__ap[31]), .CK(n_0_55), .Q(registers_25__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1308 (.A1(registers_13__ap[31]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[31]), .ZN(n_1_0_1244)); + OAI21_X1_LVT i_0_0_52 (.A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_5), .ZN(n_0_15)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[15]_reg (.CK(clk), .E(n_0_15), + .SE(dftIn), .GCK(n_0_45)); + SDFF_X1_LVT \registers_reg[15][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_15__ap[31]), .CK(n_0_45), .Q(registers_15__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1350 (.A1(n_1_0_1301), .A2(n_1_0_1292), .ZN(n_1_0_1286)); + NOR2_X1_LVT i_1_0_1322 (.A1(n_1_0_1301), .A2(n_1_0_1288), .ZN(n_1_0_1258)); + OAI21_X1_LVT i_0_0_53 (.A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_5), .ZN(n_0_14)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[14]_reg (.CK(clk), .E(n_0_14), + .SE(dftIn), .GCK(n_0_44)); + SDFF_X1_LVT \registers_reg[14][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_14__ap[31]), .CK(n_0_44), .Q(registers_14__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1307 (.A1(registers_15__ap[31]), .A2(n_1_0_1286), .B1( + n_1_0_1258), .B2(registers_14__ap[31]), .ZN(n_1_0_1243)); + NAND3_X1_LVT i_1_0_1306 (.A1(n_1_0_1245), .A2(n_1_0_1244), .A3(n_1_0_1243), + .ZN(n_1_0_1242)); + NOR2_X1_LVT i_1_0_1321 (.A1(n_1_0_1298), .A2(n_1_0_1275), .ZN(n_1_0_1257)); + OAI21_X1_LVT i_0_0_71 (.A(n_0_0_16), .B1(n_0_0_13), .B2(n_0_0_11), .ZN(n_0_3)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[3]_reg (.CK(clk), .E(n_0_3), + .SE(dftIn), .GCK(n_0_33)); + SDFF_X1_LVT \registers_reg[3][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_3__ap[31]), .CK(n_0_33), .Q(registers_3__ap[31]), .QN()); + OAI21_X1_LVT i_0_0_73 (.A(n_0_0_16), .B1(n_0_0_13), .B2(n_0_0_12), .ZN(n_0_2)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[2]_reg (.CK(clk), .E(n_0_2), + .SE(dftIn), .GCK(n_0_32)); + SDFF_X1_LVT \registers_reg[2][31] (.D(registers[31]), .SE(1'b0), .SI( + registers_2__ap[31]), .CK(n_0_32), .Q(registers_2__ap[31]), .QN()); + NOR4_X1_LVT i_1_0_1332 (.A1(n_1_0_1298), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), + .ZN(n_1_0_1268)); + AOI221_X1_LVT i_1_0_1305 (.A(n_1_0_1242), .B1(n_1_0_1257), .B2( + registers_3__ap[31]), .C1(registers_2__ap[31]), .C2(n_1_0_1268), .ZN( + n_1_0_1241)); + NAND4_X1_LVT i_1_0_1304 (.A1(n_1_0_1256), .A2(n_1_0_1251), .A3(n_1_0_1246), + .A4(n_1_0_1241), .ZN(RRs1[31])); + AND2_X1_LVT i_0_0_30 (.A1(n_0_0_16), .A2(WRd[30]), .ZN(registers[30])); + SDFF_X1_LVT \registers_reg[28][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_28__ap[30]), .CK(n_0_58), .Q(registers_28__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[17][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_17__ap[30]), .CK(n_0_47), .Q(registers_17__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1300 (.A1(registers_28__ap[30]), .A2(n_1_0_1283), .B1( + n_1_0_1271), .B2(registers_17__ap[30]), .ZN(n_1_0_1237)); + SDFF_X1_LVT \registers_reg[16][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_16__ap[30]), .CK(n_0_46), .Q(registers_16__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[31][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_31__ap[30]), .CK(n_0_61), .Q(registers_31__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1303 (.A1(registers_16__ap[30]), .A2(n_1_0_1267), .B1( + n_1_0_1266), .B2(registers_31__ap[30]), .ZN(n_1_0_1240)); + SDFF_X1_LVT \registers_reg[6][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_6__ap[30]), .CK(n_0_36), .Q(registers_6__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[1][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_1__ap[30]), .CK(n_0_0), .Q(registers_1__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1299 (.A1(registers_6__ap[30]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[30]), .ZN(n_1_0_1236)); + SDFF_X1_LVT \registers_reg[23][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_23__ap[30]), .CK(n_0_53), .Q(registers_23__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[7][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_7__ap[30]), .CK(n_0_37), .Q(registers_7__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1302 (.A1(registers_23__ap[30]), .A2(n_1_0_1264), .B1( + n_1_0_1263), .B2(registers_7__ap[30]), .ZN(n_1_0_1239)); + INV_X1_LVT i_1_0_1301 (.A(n_1_0_1239), .ZN(n_1_0_1238)); + SDFF_X1_LVT \registers_reg[19][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_19__ap[30]), .CK(n_0_49), .Q(registers_19__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[5][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_5__ap[30]), .CK(n_0_35), .Q(registers_5__ap[30]), .QN()); + AOI221_X1_LVT i_1_0_1298 (.A(n_1_0_1238), .B1(n_1_0_1295), .B2( + registers_19__ap[30]), .C1(registers_5__ap[30]), .C2(n_1_0_1273), .ZN( + n_1_0_1235)); + SDFF_X1_LVT \registers_reg[10][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_10__ap[30]), .CK(n_0_40), .Q(registers_10__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[26][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_26__ap[30]), .CK(n_0_56), .Q(registers_26__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[8][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_8__ap[30]), .CK(n_0_38), .Q(registers_8__ap[30]), .QN()); + AOI222_X1_LVT i_1_0_1297 (.A1(registers_10__ap[30]), .A2(n_1_0_1287), + .B1(n_1_0_1285), .B2(registers_26__ap[30]), .C1(registers_8__ap[30]), + .C2(n_1_0_1282), .ZN(n_1_0_1234)); + NAND4_X1_LVT i_1_0_1296 (.A1(n_1_0_1240), .A2(n_1_0_1236), .A3(n_1_0_1235), + .A4(n_1_0_1234), .ZN(n_1_0_1233)); + SDFF_X1_LVT \registers_reg[9][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_9__ap[30]), .CK(n_0_39), .Q(registers_9__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[29][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_29__ap[30]), .CK(n_0_59), .Q(registers_29__ap[30]), .QN()); + AOI221_X1_LVT i_1_0_1295 (.A(n_1_0_1233), .B1(n_1_0_1291), .B2( + registers_9__ap[30]), .C1(registers_29__ap[30]), .C2(n_1_0_1276), .ZN( + n_1_0_1232)); + SDFF_X1_LVT \registers_reg[18][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_18__ap[30]), .CK(n_0_48), .Q(registers_18__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[30][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_30__ap[30]), .CK(n_0_60), .Q(registers_30__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1294 (.A1(registers_18__ap[30]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[30]), .ZN(n_1_0_1231)); + SDFF_X1_LVT \registers_reg[20][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_20__ap[30]), .CK(n_0_50), .Q(registers_20__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[4][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_4__ap[30]), .CK(n_0_34), .Q(registers_4__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1293 (.A1(registers_20__ap[30]), .A2(n_1_0_1281), .B1( + n_1_0_1278), .B2(registers_4__ap[30]), .ZN(n_1_0_1230)); + SDFF_X1_LVT \registers_reg[22][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_22__ap[30]), .CK(n_0_52), .Q(registers_22__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[21][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_21__ap[30]), .CK(n_0_51), .Q(registers_21__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1292 (.A1(registers_22__ap[30]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[30]), .ZN(n_1_0_1229)); + NAND3_X1_LVT i_1_0_1291 (.A1(n_1_0_1231), .A2(n_1_0_1230), .A3(n_1_0_1229), + .ZN(n_1_0_1228)); + SDFF_X1_LVT \registers_reg[24][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_24__ap[30]), .CK(n_0_54), .Q(registers_24__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[12][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_12__ap[30]), .CK(n_0_42), .Q(registers_12__ap[30]), .QN()); + AOI221_X1_LVT i_1_0_1290 (.A(n_1_0_1228), .B1(n_1_0_1289), .B2( + registers_24__ap[30]), .C1(registers_12__ap[30]), .C2(n_1_0_1260), + .ZN(n_1_0_1227)); + SDFF_X1_LVT \registers_reg[27][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_27__ap[30]), .CK(n_0_57), .Q(registers_27__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[11][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_11__ap[30]), .CK(n_0_41), .Q(registers_11__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1289 (.A1(registers_27__ap[30]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[30]), .ZN(n_1_0_1226)); + SDFF_X1_LVT \registers_reg[13][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_13__ap[30]), .CK(n_0_43), .Q(registers_13__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[25][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_25__ap[30]), .CK(n_0_55), .Q(registers_25__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1288 (.A1(registers_13__ap[30]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[30]), .ZN(n_1_0_1225)); + SDFF_X1_LVT \registers_reg[15][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_15__ap[30]), .CK(n_0_45), .Q(registers_15__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[14][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_14__ap[30]), .CK(n_0_44), .Q(registers_14__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1287 (.A1(registers_15__ap[30]), .A2(n_1_0_1286), .B1( + n_1_0_1258), .B2(registers_14__ap[30]), .ZN(n_1_0_1224)); + NAND3_X1_LVT i_1_0_1286 (.A1(n_1_0_1226), .A2(n_1_0_1225), .A3(n_1_0_1224), + .ZN(n_1_0_1223)); + SDFF_X1_LVT \registers_reg[3][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_3__ap[30]), .CK(n_0_33), .Q(registers_3__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[2][30] (.D(registers[30]), .SE(1'b0), .SI( + registers_2__ap[30]), .CK(n_0_32), .Q(registers_2__ap[30]), .QN()); + AOI221_X1_LVT i_1_0_1285 (.A(n_1_0_1223), .B1(n_1_0_1257), .B2( + registers_3__ap[30]), .C1(registers_2__ap[30]), .C2(n_1_0_1268), .ZN( + n_1_0_1222)); + NAND4_X1_LVT i_1_0_1284 (.A1(n_1_0_1237), .A2(n_1_0_1232), .A3(n_1_0_1227), + .A4(n_1_0_1222), .ZN(RRs1[30])); + AND2_X1_LVT i_0_0_29 (.A1(n_0_0_16), .A2(WRd[29]), .ZN(registers[29])); + SDFF_X1_LVT \registers_reg[28][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_28__ap[29]), .CK(n_0_58), .Q(registers_28__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[8][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_8__ap[29]), .CK(n_0_38), .Q(registers_8__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1282 (.A1(registers_28__ap[29]), .A2(n_1_0_1283), .B1( + n_1_0_1282), .B2(registers_8__ap[29]), .ZN(n_1_0_1220)); + SDFF_X1_LVT \registers_reg[31][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_31__ap[29]), .CK(n_0_61), .Q(registers_31__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[7][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_7__ap[29]), .CK(n_0_37), .Q(registers_7__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1283 (.A1(registers_31__ap[29]), .A2(n_1_0_1266), .B1( + n_1_0_1263), .B2(registers_7__ap[29]), .ZN(n_1_0_1221)); + SDFF_X1_LVT \registers_reg[24][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_24__ap[29]), .CK(n_0_54), .Q(registers_24__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[20][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_20__ap[29]), .CK(n_0_50), .Q(registers_20__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1281 (.A1(registers_24__ap[29]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[29]), .ZN(n_1_0_1219)); + SDFF_X1_LVT \registers_reg[19][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_19__ap[29]), .CK(n_0_49), .Q(registers_19__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[4][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_4__ap[29]), .CK(n_0_34), .Q(registers_4__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1280 (.A1(registers_19__ap[29]), .A2(n_1_0_1295), .B1( + n_1_0_1278), .B2(registers_4__ap[29]), .ZN(n_1_0_1218)); + NAND3_X1_LVT i_1_0_1279 (.A1(n_1_0_1221), .A2(n_1_0_1219), .A3(n_1_0_1218), + .ZN(n_1_0_1217)); + SDFF_X1_LVT \registers_reg[23][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_23__ap[29]), .CK(n_0_53), .Q(registers_23__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[29][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_29__ap[29]), .CK(n_0_59), .Q(registers_29__ap[29]), .QN()); + AOI221_X1_LVT i_1_0_1278 (.A(n_1_0_1217), .B1(n_1_0_1264), .B2( + registers_23__ap[29]), .C1(registers_29__ap[29]), .C2(n_1_0_1276), + .ZN(n_1_0_1216)); + SDFF_X1_LVT \registers_reg[10][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_10__ap[29]), .CK(n_0_40), .Q(registers_10__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[26][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_26__ap[29]), .CK(n_0_56), .Q(registers_26__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[25][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_25__ap[29]), .CK(n_0_55), .Q(registers_25__ap[29]), .QN()); + AOI222_X1_LVT i_1_0_1277 (.A1(registers_10__ap[29]), .A2(n_1_0_1287), + .B1(n_1_0_1285), .B2(registers_26__ap[29]), .C1(registers_25__ap[29]), + .C2(n_1_0_1269), .ZN(n_1_0_1215)); + NAND3_X1_LVT i_1_0_1276 (.A1(n_1_0_1220), .A2(n_1_0_1216), .A3(n_1_0_1215), + .ZN(n_1_0_1214)); + SDFF_X1_LVT \registers_reg[21][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_21__ap[29]), .CK(n_0_51), .Q(registers_21__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[13][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_13__ap[29]), .CK(n_0_43), .Q(registers_13__ap[29]), .QN()); + AOI221_X1_LVT i_1_0_1275 (.A(n_1_0_1214), .B1(n_1_0_1259), .B2( + registers_21__ap[29]), .C1(registers_13__ap[29]), .C2(n_1_0_1277), + .ZN(n_1_0_1213)); + SDFF_X1_LVT \registers_reg[18][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_18__ap[29]), .CK(n_0_48), .Q(registers_18__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[30][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_30__ap[29]), .CK(n_0_60), .Q(registers_30__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1274 (.A1(registers_18__ap[29]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[29]), .ZN(n_1_0_1212)); + SDFF_X1_LVT \registers_reg[17][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_17__ap[29]), .CK(n_0_47), .Q(registers_17__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[12][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_12__ap[29]), .CK(n_0_42), .Q(registers_12__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1273 (.A1(registers_17__ap[29]), .A2(n_1_0_1271), .B1( + n_1_0_1260), .B2(registers_12__ap[29]), .ZN(n_1_0_1211)); + SDFF_X1_LVT \registers_reg[15][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_15__ap[29]), .CK(n_0_45), .Q(registers_15__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[16][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_16__ap[29]), .CK(n_0_46), .Q(registers_16__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1272 (.A1(registers_15__ap[29]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[29]), .ZN(n_1_0_1210)); + NAND3_X1_LVT i_1_0_1271 (.A1(n_1_0_1212), .A2(n_1_0_1211), .A3(n_1_0_1210), + .ZN(n_1_0_1209)); + SDFF_X1_LVT \registers_reg[22][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_22__ap[29]), .CK(n_0_52), .Q(registers_22__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[5][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_5__ap[29]), .CK(n_0_35), .Q(registers_5__ap[29]), .QN()); + AOI221_X1_LVT i_1_0_1270 (.A(n_1_0_1209), .B1(n_1_0_1294), .B2( + registers_22__ap[29]), .C1(registers_5__ap[29]), .C2(n_1_0_1273), .ZN( + n_1_0_1208)); + SDFF_X1_LVT \registers_reg[9][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_9__ap[29]), .CK(n_0_39), .Q(registers_9__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[1][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_1__ap[29]), .CK(n_0_0), .Q(registers_1__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1269 (.A1(registers_9__ap[29]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[29]), .ZN(n_1_0_1207)); + SDFF_X1_LVT \registers_reg[6][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_6__ap[29]), .CK(n_0_36), .Q(registers_6__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[14][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_14__ap[29]), .CK(n_0_44), .Q(registers_14__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1268 (.A1(registers_6__ap[29]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[29]), .ZN(n_1_0_1206)); + SDFF_X1_LVT \registers_reg[27][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_27__ap[29]), .CK(n_0_57), .Q(registers_27__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[11][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_11__ap[29]), .CK(n_0_41), .Q(registers_11__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1267 (.A1(registers_27__ap[29]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[29]), .ZN(n_1_0_1205)); + NAND3_X1_LVT i_1_0_1266 (.A1(n_1_0_1207), .A2(n_1_0_1206), .A3(n_1_0_1205), + .ZN(n_1_0_1204)); + SDFF_X1_LVT \registers_reg[3][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_3__ap[29]), .CK(n_0_33), .Q(registers_3__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[2][29] (.D(registers[29]), .SE(1'b0), .SI( + registers_2__ap[29]), .CK(n_0_32), .Q(registers_2__ap[29]), .QN()); + AOI221_X1_LVT i_1_0_1265 (.A(n_1_0_1204), .B1(n_1_0_1257), .B2( + registers_3__ap[29]), .C1(registers_2__ap[29]), .C2(n_1_0_1268), .ZN( + n_1_0_1203)); + NAND3_X1_LVT i_1_0_1264 (.A1(n_1_0_1213), .A2(n_1_0_1208), .A3(n_1_0_1203), + .ZN(RRs1[29])); + AND2_X1_LVT i_0_0_28 (.A1(n_0_0_16), .A2(WRd[28]), .ZN(registers[28])); + SDFF_X1_LVT \registers_reg[15][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_15__ap[28]), .CK(n_0_45), .Q(registers_15__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[26][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_26__ap[28]), .CK(n_0_56), .Q(registers_26__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[22][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_22__ap[28]), .CK(n_0_52), .Q(registers_22__ap[28]), .QN()); + AOI222_X1_LVT i_1_0_1263 (.A1(registers_15__ap[28]), .A2(n_1_0_1286), + .B1(n_1_0_1285), .B2(registers_26__ap[28]), .C1(registers_22__ap[28]), + .C2(n_1_0_1294), .ZN(n_1_0_1202)); + SDFF_X1_LVT \registers_reg[5][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_5__ap[28]), .CK(n_0_35), .Q(registers_5__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[12][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_12__ap[28]), .CK(n_0_42), .Q(registers_12__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1262 (.A1(registers_5__ap[28]), .A2(n_1_0_1273), .B1( + n_1_0_1260), .B2(registers_12__ap[28]), .ZN(n_1_0_1201)); + SDFF_X1_LVT \registers_reg[28][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_28__ap[28]), .CK(n_0_58), .Q(registers_28__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[14][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_14__ap[28]), .CK(n_0_44), .Q(registers_14__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1261 (.A1(registers_28__ap[28]), .A2(n_1_0_1283), .B1( + n_1_0_1258), .B2(registers_14__ap[28]), .ZN(n_1_0_1200)); + SDFF_X1_LVT \registers_reg[17][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_17__ap[28]), .CK(n_0_47), .Q(registers_17__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[2][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_2__ap[28]), .CK(n_0_32), .Q(registers_2__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1260 (.A1(registers_17__ap[28]), .A2(n_1_0_1271), .B1( + n_1_0_1268), .B2(registers_2__ap[28]), .ZN(n_1_0_1199)); + NAND3_X1_LVT i_1_0_1259 (.A1(n_1_0_1201), .A2(n_1_0_1200), .A3(n_1_0_1199), + .ZN(n_1_0_1198)); + SDFF_X1_LVT \registers_reg[9][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_9__ap[28]), .CK(n_0_39), .Q(registers_9__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[29][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_29__ap[28]), .CK(n_0_59), .Q(registers_29__ap[28]), .QN()); + AOI221_X1_LVT i_1_0_1258 (.A(n_1_0_1198), .B1(n_1_0_1291), .B2( + registers_9__ap[28]), .C1(registers_29__ap[28]), .C2(n_1_0_1276), .ZN( + n_1_0_1197)); + SDFF_X1_LVT \registers_reg[13][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_13__ap[28]), .CK(n_0_43), .Q(registers_13__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[25][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_25__ap[28]), .CK(n_0_55), .Q(registers_25__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1257 (.A1(registers_13__ap[28]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[28]), .ZN(n_1_0_1196)); + NAND3_X1_LVT i_1_0_1256 (.A1(n_1_0_1202), .A2(n_1_0_1197), .A3(n_1_0_1196), + .ZN(n_1_0_1195)); + SDFF_X1_LVT \registers_reg[4][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_4__ap[28]), .CK(n_0_34), .Q(registers_4__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[20][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_20__ap[28]), .CK(n_0_50), .Q(registers_20__ap[28]), .QN()); + AOI221_X1_LVT i_1_0_1255 (.A(n_1_0_1195), .B1(n_1_0_1278), .B2( + registers_4__ap[28]), .C1(registers_20__ap[28]), .C2(n_1_0_1281), .ZN( + n_1_0_1194)); + SDFF_X1_LVT \registers_reg[1][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_1__ap[28]), .CK(n_0_0), .Q(registers_1__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[23][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_23__ap[28]), .CK(n_0_53), .Q(registers_23__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1254 (.A1(registers_1__ap[28]), .A2(n_1_0_1274), .B1( + n_1_0_1264), .B2(registers_23__ap[28]), .ZN(n_1_0_1193)); + SDFF_X1_LVT \registers_reg[10][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_10__ap[28]), .CK(n_0_40), .Q(registers_10__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[21][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_21__ap[28]), .CK(n_0_51), .Q(registers_21__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1253 (.A1(registers_10__ap[28]), .A2(n_1_0_1287), .B1( + n_1_0_1259), .B2(registers_21__ap[28]), .ZN(n_1_0_1192)); + SDFF_X1_LVT \registers_reg[6][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_6__ap[28]), .CK(n_0_36), .Q(registers_6__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[30][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_30__ap[28]), .CK(n_0_60), .Q(registers_30__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1252 (.A1(registers_6__ap[28]), .A2(n_1_0_1300), .B1( + n_1_0_1272), .B2(registers_30__ap[28]), .ZN(n_1_0_1191)); + NAND3_X1_LVT i_1_0_1251 (.A1(n_1_0_1193), .A2(n_1_0_1192), .A3(n_1_0_1191), + .ZN(n_1_0_1190)); + SDFF_X1_LVT \registers_reg[8][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_8__ap[28]), .CK(n_0_38), .Q(registers_8__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[24][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_24__ap[28]), .CK(n_0_54), .Q(registers_24__ap[28]), .QN()); + AOI221_X1_LVT i_1_0_1250 (.A(n_1_0_1190), .B1(n_1_0_1282), .B2( + registers_8__ap[28]), .C1(registers_24__ap[28]), .C2(n_1_0_1289), .ZN( + n_1_0_1189)); + SDFF_X1_LVT \registers_reg[16][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_16__ap[28]), .CK(n_0_46), .Q(registers_16__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[3][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_3__ap[28]), .CK(n_0_33), .Q(registers_3__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1249 (.A1(registers_16__ap[28]), .A2(n_1_0_1267), .B1( + n_1_0_1257), .B2(registers_3__ap[28]), .ZN(n_1_0_1188)); + SDFF_X1_LVT \registers_reg[11][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_11__ap[28]), .CK(n_0_41), .Q(registers_11__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[31][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_31__ap[28]), .CK(n_0_61), .Q(registers_31__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1248 (.A1(registers_11__ap[28]), .A2(n_1_0_1270), .B1( + n_1_0_1266), .B2(registers_31__ap[28]), .ZN(n_1_0_1187)); + SDFF_X1_LVT \registers_reg[27][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_27__ap[28]), .CK(n_0_57), .Q(registers_27__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[7][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_7__ap[28]), .CK(n_0_37), .Q(registers_7__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1247 (.A1(registers_27__ap[28]), .A2(n_1_0_1279), .B1( + n_1_0_1263), .B2(registers_7__ap[28]), .ZN(n_1_0_1186)); + NAND3_X1_LVT i_1_0_1246 (.A1(n_1_0_1188), .A2(n_1_0_1187), .A3(n_1_0_1186), + .ZN(n_1_0_1185)); + SDFF_X1_LVT \registers_reg[19][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_19__ap[28]), .CK(n_0_49), .Q(registers_19__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[18][28] (.D(registers[28]), .SE(1'b0), .SI( + registers_18__ap[28]), .CK(n_0_48), .Q(registers_18__ap[28]), .QN()); + AOI221_X1_LVT i_1_0_1245 (.A(n_1_0_1185), .B1(n_1_0_1295), .B2( + registers_19__ap[28]), .C1(registers_18__ap[28]), .C2(n_1_0_1297), + .ZN(n_1_0_1184)); + NAND3_X1_LVT i_1_0_1244 (.A1(n_1_0_1194), .A2(n_1_0_1189), .A3(n_1_0_1184), + .ZN(RRs1[28])); + AND2_X1_LVT i_0_0_27 (.A1(n_0_0_16), .A2(WRd[27]), .ZN(registers[27])); + SDFF_X1_LVT \registers_reg[29][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_29__ap[27]), .CK(n_0_59), .Q(registers_29__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[2][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_2__ap[27]), .CK(n_0_32), .Q(registers_2__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1242 (.A1(registers_29__ap[27]), .A2(n_1_0_1276), .B1( + n_1_0_1268), .B2(registers_2__ap[27]), .ZN(n_1_0_1182)); + SDFF_X1_LVT \registers_reg[8][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_8__ap[27]), .CK(n_0_38), .Q(registers_8__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[25][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_25__ap[27]), .CK(n_0_55), .Q(registers_25__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1243 (.A1(registers_8__ap[27]), .A2(n_1_0_1282), .B1( + n_1_0_1269), .B2(registers_25__ap[27]), .ZN(n_1_0_1183)); + SDFF_X1_LVT \registers_reg[9][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_9__ap[27]), .CK(n_0_39), .Q(registers_9__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[7][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_7__ap[27]), .CK(n_0_37), .Q(registers_7__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1241 (.A1(registers_9__ap[27]), .A2(n_1_0_1291), .B1( + n_1_0_1263), .B2(registers_7__ap[27]), .ZN(n_1_0_1181)); + SDFF_X1_LVT \registers_reg[11][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_11__ap[27]), .CK(n_0_41), .Q(registers_11__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[16][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_16__ap[27]), .CK(n_0_46), .Q(registers_16__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1240 (.A1(registers_11__ap[27]), .A2(n_1_0_1270), .B1( + n_1_0_1267), .B2(registers_16__ap[27]), .ZN(n_1_0_1180)); + NAND3_X1_LVT i_1_0_1239 (.A1(n_1_0_1183), .A2(n_1_0_1181), .A3(n_1_0_1180), + .ZN(n_1_0_1179)); + SDFF_X1_LVT \registers_reg[10][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_10__ap[27]), .CK(n_0_40), .Q(registers_10__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[6][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_6__ap[27]), .CK(n_0_36), .Q(registers_6__ap[27]), .QN()); + AOI221_X1_LVT i_1_0_1238 (.A(n_1_0_1179), .B1(n_1_0_1287), .B2( + registers_10__ap[27]), .C1(registers_6__ap[27]), .C2(n_1_0_1300), .ZN( + n_1_0_1178)); + SDFF_X1_LVT \registers_reg[1][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_1__ap[27]), .CK(n_0_0), .Q(registers_1__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[30][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_30__ap[27]), .CK(n_0_60), .Q(registers_30__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[22][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_22__ap[27]), .CK(n_0_52), .Q(registers_22__ap[27]), .QN()); + AOI222_X1_LVT i_1_0_1237 (.A1(registers_1__ap[27]), .A2(n_1_0_1274), .B1( + n_1_0_1272), .B2(registers_30__ap[27]), .C1(registers_22__ap[27]), + .C2(n_1_0_1294), .ZN(n_1_0_1177)); + NAND3_X1_LVT i_1_0_1236 (.A1(n_1_0_1182), .A2(n_1_0_1178), .A3(n_1_0_1177), + .ZN(n_1_0_1176)); + SDFF_X1_LVT \registers_reg[5][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_5__ap[27]), .CK(n_0_35), .Q(registers_5__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[28][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_28__ap[27]), .CK(n_0_58), .Q(registers_28__ap[27]), .QN()); + AOI221_X1_LVT i_1_0_1235 (.A(n_1_0_1176), .B1(n_1_0_1273), .B2( + registers_5__ap[27]), .C1(registers_28__ap[27]), .C2(n_1_0_1283), .ZN( + n_1_0_1175)); + SDFF_X1_LVT \registers_reg[4][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_4__ap[27]), .CK(n_0_34), .Q(registers_4__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[12][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_12__ap[27]), .CK(n_0_42), .Q(registers_12__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1234 (.A1(registers_4__ap[27]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[27]), .ZN(n_1_0_1174)); + SDFF_X1_LVT \registers_reg[19][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_19__ap[27]), .CK(n_0_49), .Q(registers_19__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[21][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_21__ap[27]), .CK(n_0_51), .Q(registers_21__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1233 (.A1(registers_19__ap[27]), .A2(n_1_0_1295), .B1( + n_1_0_1259), .B2(registers_21__ap[27]), .ZN(n_1_0_1173)); + SDFF_X1_LVT \registers_reg[24][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_24__ap[27]), .CK(n_0_54), .Q(registers_24__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[20][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_20__ap[27]), .CK(n_0_50), .Q(registers_20__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1232 (.A1(registers_24__ap[27]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[27]), .ZN(n_1_0_1172)); + NAND3_X1_LVT i_1_0_1231 (.A1(n_1_0_1174), .A2(n_1_0_1173), .A3(n_1_0_1172), + .ZN(n_1_0_1171)); + SDFF_X1_LVT \registers_reg[18][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_18__ap[27]), .CK(n_0_48), .Q(registers_18__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[26][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_26__ap[27]), .CK(n_0_56), .Q(registers_26__ap[27]), .QN()); + AOI221_X1_LVT i_1_0_1230 (.A(n_1_0_1171), .B1(n_1_0_1297), .B2( + registers_18__ap[27]), .C1(registers_26__ap[27]), .C2(n_1_0_1285), + .ZN(n_1_0_1170)); + SDFF_X1_LVT \registers_reg[23][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_23__ap[27]), .CK(n_0_53), .Q(registers_23__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[3][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_3__ap[27]), .CK(n_0_33), .Q(registers_3__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1229 (.A1(registers_23__ap[27]), .A2(n_1_0_1264), .B1( + n_1_0_1257), .B2(registers_3__ap[27]), .ZN(n_1_0_1169)); + SDFF_X1_LVT \registers_reg[13][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_13__ap[27]), .CK(n_0_43), .Q(registers_13__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[17][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_17__ap[27]), .CK(n_0_47), .Q(registers_17__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1228 (.A1(registers_13__ap[27]), .A2(n_1_0_1277), .B1( + n_1_0_1271), .B2(registers_17__ap[27]), .ZN(n_1_0_1168)); + SDFF_X1_LVT \registers_reg[15][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_15__ap[27]), .CK(n_0_45), .Q(registers_15__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[14][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_14__ap[27]), .CK(n_0_44), .Q(registers_14__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1227 (.A1(registers_15__ap[27]), .A2(n_1_0_1286), .B1( + n_1_0_1258), .B2(registers_14__ap[27]), .ZN(n_1_0_1167)); + NAND3_X1_LVT i_1_0_1226 (.A1(n_1_0_1169), .A2(n_1_0_1168), .A3(n_1_0_1167), + .ZN(n_1_0_1166)); + SDFF_X1_LVT \registers_reg[27][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_27__ap[27]), .CK(n_0_57), .Q(registers_27__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[31][27] (.D(registers[27]), .SE(1'b0), .SI( + registers_31__ap[27]), .CK(n_0_61), .Q(registers_31__ap[27]), .QN()); + AOI221_X1_LVT i_1_0_1225 (.A(n_1_0_1166), .B1(n_1_0_1279), .B2( + registers_27__ap[27]), .C1(registers_31__ap[27]), .C2(n_1_0_1266), + .ZN(n_1_0_1165)); + NAND3_X1_LVT i_1_0_1224 (.A1(n_1_0_1175), .A2(n_1_0_1170), .A3(n_1_0_1165), + .ZN(RRs1[27])); + AND2_X1_LVT i_0_0_26 (.A1(n_0_0_16), .A2(WRd[26]), .ZN(registers[26])); + SDFF_X1_LVT \registers_reg[18][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_18__ap[26]), .CK(n_0_48), .Q(registers_18__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[22][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_22__ap[26]), .CK(n_0_52), .Q(registers_22__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[1][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_1__ap[26]), .CK(n_0_0), .Q(registers_1__ap[26]), .QN()); + AOI222_X1_LVT i_1_0_1223 (.A1(registers_18__ap[26]), .A2(n_1_0_1297), + .B1(n_1_0_1294), .B2(registers_22__ap[26]), .C1(registers_1__ap[26]), + .C2(n_1_0_1274), .ZN(n_1_0_1164)); + SDFF_X1_LVT \registers_reg[29][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_29__ap[26]), .CK(n_0_59), .Q(registers_29__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[2][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_2__ap[26]), .CK(n_0_32), .Q(registers_2__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1222 (.A1(registers_29__ap[26]), .A2(n_1_0_1276), .B1( + n_1_0_1268), .B2(registers_2__ap[26]), .ZN(n_1_0_1163)); + SDFF_X1_LVT \registers_reg[9][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_9__ap[26]), .CK(n_0_39), .Q(registers_9__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[7][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_7__ap[26]), .CK(n_0_37), .Q(registers_7__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1221 (.A1(registers_9__ap[26]), .A2(n_1_0_1291), .B1( + n_1_0_1263), .B2(registers_7__ap[26]), .ZN(n_1_0_1162)); + SDFF_X1_LVT \registers_reg[11][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_11__ap[26]), .CK(n_0_41), .Q(registers_11__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[25][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_25__ap[26]), .CK(n_0_55), .Q(registers_25__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1220 (.A1(registers_11__ap[26]), .A2(n_1_0_1270), .B1( + n_1_0_1269), .B2(registers_25__ap[26]), .ZN(n_1_0_1161)); + SDFF_X1_LVT \registers_reg[27][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_27__ap[26]), .CK(n_0_57), .Q(registers_27__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[16][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_16__ap[26]), .CK(n_0_46), .Q(registers_16__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1219 (.A1(registers_27__ap[26]), .A2(n_1_0_1279), .B1( + n_1_0_1267), .B2(registers_16__ap[26]), .ZN(n_1_0_1160)); + NAND3_X1_LVT i_1_0_1218 (.A1(n_1_0_1162), .A2(n_1_0_1161), .A3(n_1_0_1160), + .ZN(n_1_0_1159)); + SDFF_X1_LVT \registers_reg[31][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_31__ap[26]), .CK(n_0_61), .Q(registers_31__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[6][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_6__ap[26]), .CK(n_0_36), .Q(registers_6__ap[26]), .QN()); + AOI221_X1_LVT i_1_0_1217 (.A(n_1_0_1159), .B1(n_1_0_1266), .B2( + registers_31__ap[26]), .C1(registers_6__ap[26]), .C2(n_1_0_1300), .ZN( + n_1_0_1158)); + NAND3_X1_LVT i_1_0_1216 (.A1(n_1_0_1164), .A2(n_1_0_1163), .A3(n_1_0_1158), + .ZN(n_1_0_1157)); + SDFF_X1_LVT \registers_reg[5][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_5__ap[26]), .CK(n_0_35), .Q(registers_5__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[28][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_28__ap[26]), .CK(n_0_58), .Q(registers_28__ap[26]), .QN()); + AOI221_X1_LVT i_1_0_1215 (.A(n_1_0_1157), .B1(n_1_0_1273), .B2( + registers_5__ap[26]), .C1(registers_28__ap[26]), .C2(n_1_0_1283), .ZN( + n_1_0_1156)); + SDFF_X1_LVT \registers_reg[4][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_4__ap[26]), .CK(n_0_34), .Q(registers_4__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[12][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_12__ap[26]), .CK(n_0_42), .Q(registers_12__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1214 (.A1(registers_4__ap[26]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[26]), .ZN(n_1_0_1155)); + SDFF_X1_LVT \registers_reg[19][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_19__ap[26]), .CK(n_0_49), .Q(registers_19__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[21][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_21__ap[26]), .CK(n_0_51), .Q(registers_21__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1213 (.A1(registers_19__ap[26]), .A2(n_1_0_1295), .B1( + n_1_0_1259), .B2(registers_21__ap[26]), .ZN(n_1_0_1154)); + SDFF_X1_LVT \registers_reg[24][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_24__ap[26]), .CK(n_0_54), .Q(registers_24__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[20][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_20__ap[26]), .CK(n_0_50), .Q(registers_20__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1212 (.A1(registers_24__ap[26]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[26]), .ZN(n_1_0_1153)); + NAND3_X1_LVT i_1_0_1211 (.A1(n_1_0_1155), .A2(n_1_0_1154), .A3(n_1_0_1153), + .ZN(n_1_0_1152)); + SDFF_X1_LVT \registers_reg[26][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_26__ap[26]), .CK(n_0_56), .Q(registers_26__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[30][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_30__ap[26]), .CK(n_0_60), .Q(registers_30__ap[26]), .QN()); + AOI221_X1_LVT i_1_0_1210 (.A(n_1_0_1152), .B1(n_1_0_1285), .B2( + registers_26__ap[26]), .C1(registers_30__ap[26]), .C2(n_1_0_1272), + .ZN(n_1_0_1151)); + SDFF_X1_LVT \registers_reg[8][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_8__ap[26]), .CK(n_0_38), .Q(registers_8__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[23][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_23__ap[26]), .CK(n_0_53), .Q(registers_23__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1209 (.A1(registers_8__ap[26]), .A2(n_1_0_1282), .B1( + n_1_0_1264), .B2(registers_23__ap[26]), .ZN(n_1_0_1150)); + SDFF_X1_LVT \registers_reg[13][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_13__ap[26]), .CK(n_0_43), .Q(registers_13__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[17][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_17__ap[26]), .CK(n_0_47), .Q(registers_17__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1208 (.A1(registers_13__ap[26]), .A2(n_1_0_1277), .B1( + n_1_0_1271), .B2(registers_17__ap[26]), .ZN(n_1_0_1149)); + SDFF_X1_LVT \registers_reg[15][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_15__ap[26]), .CK(n_0_45), .Q(registers_15__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[14][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_14__ap[26]), .CK(n_0_44), .Q(registers_14__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1207 (.A1(registers_15__ap[26]), .A2(n_1_0_1286), .B1( + n_1_0_1258), .B2(registers_14__ap[26]), .ZN(n_1_0_1148)); + NAND3_X1_LVT i_1_0_1206 (.A1(n_1_0_1150), .A2(n_1_0_1149), .A3(n_1_0_1148), + .ZN(n_1_0_1147)); + SDFF_X1_LVT \registers_reg[10][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_10__ap[26]), .CK(n_0_40), .Q(registers_10__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[3][26] (.D(registers[26]), .SE(1'b0), .SI( + registers_3__ap[26]), .CK(n_0_33), .Q(registers_3__ap[26]), .QN()); + AOI221_X1_LVT i_1_0_1205 (.A(n_1_0_1147), .B1(n_1_0_1287), .B2( + registers_10__ap[26]), .C1(registers_3__ap[26]), .C2(n_1_0_1257), .ZN( + n_1_0_1146)); + NAND3_X1_LVT i_1_0_1204 (.A1(n_1_0_1156), .A2(n_1_0_1151), .A3(n_1_0_1146), + .ZN(RRs1[26])); + AND2_X1_LVT i_0_0_25 (.A1(n_0_0_16), .A2(WRd[25]), .ZN(registers[25])); + SDFF_X1_LVT \registers_reg[17][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_17__ap[25]), .CK(n_0_47), .Q(registers_17__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[21][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_21__ap[25]), .CK(n_0_51), .Q(registers_21__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1202 (.A1(registers_17__ap[25]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[25]), .ZN(n_1_0_1144)); + SDFF_X1_LVT \registers_reg[6][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_6__ap[25]), .CK(n_0_36), .Q(registers_6__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[8][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_8__ap[25]), .CK(n_0_38), .Q(registers_8__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1203 (.A1(registers_6__ap[25]), .A2(n_1_0_1300), .B1( + n_1_0_1282), .B2(registers_8__ap[25]), .ZN(n_1_0_1145)); + SDFF_X1_LVT \registers_reg[20][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_20__ap[25]), .CK(n_0_50), .Q(registers_20__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[12][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_12__ap[25]), .CK(n_0_42), .Q(registers_12__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1201 (.A1(registers_20__ap[25]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[25]), .ZN(n_1_0_1143)); + SDFF_X1_LVT \registers_reg[5][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_5__ap[25]), .CK(n_0_35), .Q(registers_5__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[11][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_11__ap[25]), .CK(n_0_41), .Q(registers_11__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1200 (.A1(registers_5__ap[25]), .A2(n_1_0_1273), .B1( + n_1_0_1270), .B2(registers_11__ap[25]), .ZN(n_1_0_1142)); + NAND3_X1_LVT i_1_0_1199 (.A1(n_1_0_1145), .A2(n_1_0_1143), .A3(n_1_0_1142), + .ZN(n_1_0_1141)); + SDFF_X1_LVT \registers_reg[10][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_10__ap[25]), .CK(n_0_40), .Q(registers_10__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[2][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_2__ap[25]), .CK(n_0_32), .Q(registers_2__ap[25]), .QN()); + AOI221_X1_LVT i_1_0_1198 (.A(n_1_0_1141), .B1(n_1_0_1287), .B2( + registers_10__ap[25]), .C1(registers_2__ap[25]), .C2(n_1_0_1268), .ZN( + n_1_0_1140)); + SDFF_X1_LVT \registers_reg[13][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_13__ap[25]), .CK(n_0_43), .Q(registers_13__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[30][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_30__ap[25]), .CK(n_0_60), .Q(registers_30__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[22][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_22__ap[25]), .CK(n_0_52), .Q(registers_22__ap[25]), .QN()); + AOI222_X1_LVT i_1_0_1197 (.A1(registers_13__ap[25]), .A2(n_1_0_1277), + .B1(n_1_0_1272), .B2(registers_30__ap[25]), .C1(registers_22__ap[25]), + .C2(n_1_0_1294), .ZN(n_1_0_1139)); + NAND2_X1_LVT i_1_0_1196 (.A1(n_1_0_1140), .A2(n_1_0_1139), .ZN(n_1_0_1138)); + SDFF_X1_LVT \registers_reg[1][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_1__ap[25]), .CK(n_0_0), .Q(registers_1__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[28][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_28__ap[25]), .CK(n_0_58), .Q(registers_28__ap[25]), .QN()); + AOI221_X1_LVT i_1_0_1195 (.A(n_1_0_1138), .B1(n_1_0_1274), .B2( + registers_1__ap[25]), .C1(registers_28__ap[25]), .C2(n_1_0_1283), .ZN( + n_1_0_1137)); + SDFF_X1_LVT \registers_reg[18][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_18__ap[25]), .CK(n_0_48), .Q(registers_18__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[26][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_26__ap[25]), .CK(n_0_56), .Q(registers_26__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1194 (.A1(registers_18__ap[25]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[25]), .ZN(n_1_0_1136)); + SDFF_X1_LVT \registers_reg[24][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_24__ap[25]), .CK(n_0_54), .Q(registers_24__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[4][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_4__ap[25]), .CK(n_0_34), .Q(registers_4__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1193 (.A1(registers_24__ap[25]), .A2(n_1_0_1289), .B1( + n_1_0_1278), .B2(registers_4__ap[25]), .ZN(n_1_0_1135)); + SDFF_X1_LVT \registers_reg[15][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_15__ap[25]), .CK(n_0_45), .Q(registers_15__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[16][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_16__ap[25]), .CK(n_0_46), .Q(registers_16__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1192 (.A1(registers_15__ap[25]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[25]), .ZN(n_1_0_1134)); + NAND3_X1_LVT i_1_0_1191 (.A1(n_1_0_1136), .A2(n_1_0_1135), .A3(n_1_0_1134), + .ZN(n_1_0_1133)); + SDFF_X1_LVT \registers_reg[19][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_19__ap[25]), .CK(n_0_49), .Q(registers_19__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[25][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_25__ap[25]), .CK(n_0_55), .Q(registers_25__ap[25]), .QN()); + AOI221_X1_LVT i_1_0_1190 (.A(n_1_0_1133), .B1(n_1_0_1295), .B2( + registers_19__ap[25]), .C1(registers_25__ap[25]), .C2(n_1_0_1269), + .ZN(n_1_0_1132)); + SDFF_X1_LVT \registers_reg[7][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_7__ap[25]), .CK(n_0_37), .Q(registers_7__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[14][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_14__ap[25]), .CK(n_0_44), .Q(registers_14__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1189 (.A1(registers_7__ap[25]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[25]), .ZN(n_1_0_1131)); + SDFF_X1_LVT \registers_reg[9][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_9__ap[25]), .CK(n_0_39), .Q(registers_9__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[29][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_29__ap[25]), .CK(n_0_59), .Q(registers_29__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1188 (.A1(registers_9__ap[25]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[25]), .ZN(n_1_0_1130)); + SDFF_X1_LVT \registers_reg[23][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_23__ap[25]), .CK(n_0_53), .Q(registers_23__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[3][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_3__ap[25]), .CK(n_0_33), .Q(registers_3__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1187 (.A1(registers_23__ap[25]), .A2(n_1_0_1264), .B1( + n_1_0_1257), .B2(registers_3__ap[25]), .ZN(n_1_0_1129)); + NAND3_X1_LVT i_1_0_1186 (.A1(n_1_0_1131), .A2(n_1_0_1130), .A3(n_1_0_1129), + .ZN(n_1_0_1128)); + SDFF_X1_LVT \registers_reg[27][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_27__ap[25]), .CK(n_0_57), .Q(registers_27__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[31][25] (.D(registers[25]), .SE(1'b0), .SI( + registers_31__ap[25]), .CK(n_0_61), .Q(registers_31__ap[25]), .QN()); + AOI221_X1_LVT i_1_0_1185 (.A(n_1_0_1128), .B1(n_1_0_1279), .B2( + registers_27__ap[25]), .C1(registers_31__ap[25]), .C2(n_1_0_1266), + .ZN(n_1_0_1127)); + NAND4_X1_LVT i_1_0_1184 (.A1(n_1_0_1144), .A2(n_1_0_1137), .A3(n_1_0_1132), + .A4(n_1_0_1127), .ZN(RRs1[25])); + AND2_X1_LVT i_0_0_24 (.A1(n_0_0_16), .A2(WRd[24]), .ZN(registers[24])); + SDFF_X1_LVT \registers_reg[17][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_17__ap[24]), .CK(n_0_47), .Q(registers_17__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[21][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_21__ap[24]), .CK(n_0_51), .Q(registers_21__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1182 (.A1(registers_17__ap[24]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[24]), .ZN(n_1_0_1125)); + SDFF_X1_LVT \registers_reg[6][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_6__ap[24]), .CK(n_0_36), .Q(registers_6__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[8][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_8__ap[24]), .CK(n_0_38), .Q(registers_8__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1183 (.A1(registers_6__ap[24]), .A2(n_1_0_1300), .B1( + n_1_0_1282), .B2(registers_8__ap[24]), .ZN(n_1_0_1126)); + SDFF_X1_LVT \registers_reg[20][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_20__ap[24]), .CK(n_0_50), .Q(registers_20__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[12][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_12__ap[24]), .CK(n_0_42), .Q(registers_12__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1181 (.A1(registers_20__ap[24]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[24]), .ZN(n_1_0_1124)); + SDFF_X1_LVT \registers_reg[5][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_5__ap[24]), .CK(n_0_35), .Q(registers_5__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[11][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_11__ap[24]), .CK(n_0_41), .Q(registers_11__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1180 (.A1(registers_5__ap[24]), .A2(n_1_0_1273), .B1( + n_1_0_1270), .B2(registers_11__ap[24]), .ZN(n_1_0_1123)); + NAND3_X1_LVT i_1_0_1179 (.A1(n_1_0_1126), .A2(n_1_0_1124), .A3(n_1_0_1123), + .ZN(n_1_0_1122)); + SDFF_X1_LVT \registers_reg[10][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_10__ap[24]), .CK(n_0_40), .Q(registers_10__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[2][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_2__ap[24]), .CK(n_0_32), .Q(registers_2__ap[24]), .QN()); + AOI221_X1_LVT i_1_0_1178 (.A(n_1_0_1122), .B1(n_1_0_1287), .B2( + registers_10__ap[24]), .C1(registers_2__ap[24]), .C2(n_1_0_1268), .ZN( + n_1_0_1121)); + SDFF_X1_LVT \registers_reg[13][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_13__ap[24]), .CK(n_0_43), .Q(registers_13__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[30][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_30__ap[24]), .CK(n_0_60), .Q(registers_30__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[22][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_22__ap[24]), .CK(n_0_52), .Q(registers_22__ap[24]), .QN()); + AOI222_X1_LVT i_1_0_1177 (.A1(registers_13__ap[24]), .A2(n_1_0_1277), + .B1(n_1_0_1272), .B2(registers_30__ap[24]), .C1(registers_22__ap[24]), + .C2(n_1_0_1294), .ZN(n_1_0_1120)); + NAND2_X1_LVT i_1_0_1176 (.A1(n_1_0_1121), .A2(n_1_0_1120), .ZN(n_1_0_1119)); + SDFF_X1_LVT \registers_reg[1][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_1__ap[24]), .CK(n_0_0), .Q(registers_1__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[28][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_28__ap[24]), .CK(n_0_58), .Q(registers_28__ap[24]), .QN()); + AOI221_X1_LVT i_1_0_1175 (.A(n_1_0_1119), .B1(n_1_0_1274), .B2( + registers_1__ap[24]), .C1(registers_28__ap[24]), .C2(n_1_0_1283), .ZN( + n_1_0_1118)); + SDFF_X1_LVT \registers_reg[18][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_18__ap[24]), .CK(n_0_48), .Q(registers_18__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[26][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_26__ap[24]), .CK(n_0_56), .Q(registers_26__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1174 (.A1(registers_18__ap[24]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[24]), .ZN(n_1_0_1117)); + SDFF_X1_LVT \registers_reg[24][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_24__ap[24]), .CK(n_0_54), .Q(registers_24__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[4][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_4__ap[24]), .CK(n_0_34), .Q(registers_4__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1173 (.A1(registers_24__ap[24]), .A2(n_1_0_1289), .B1( + n_1_0_1278), .B2(registers_4__ap[24]), .ZN(n_1_0_1116)); + SDFF_X1_LVT \registers_reg[15][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_15__ap[24]), .CK(n_0_45), .Q(registers_15__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[25][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_25__ap[24]), .CK(n_0_55), .Q(registers_25__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1172 (.A1(registers_15__ap[24]), .A2(n_1_0_1286), .B1( + n_1_0_1269), .B2(registers_25__ap[24]), .ZN(n_1_0_1115)); + NAND3_X1_LVT i_1_0_1171 (.A1(n_1_0_1117), .A2(n_1_0_1116), .A3(n_1_0_1115), + .ZN(n_1_0_1114)); + SDFF_X1_LVT \registers_reg[19][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_19__ap[24]), .CK(n_0_49), .Q(registers_19__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[16][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_16__ap[24]), .CK(n_0_46), .Q(registers_16__ap[24]), .QN()); + AOI221_X1_LVT i_1_0_1170 (.A(n_1_0_1114), .B1(n_1_0_1295), .B2( + registers_19__ap[24]), .C1(registers_16__ap[24]), .C2(n_1_0_1267), + .ZN(n_1_0_1113)); + SDFF_X1_LVT \registers_reg[7][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_7__ap[24]), .CK(n_0_37), .Q(registers_7__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[14][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_14__ap[24]), .CK(n_0_44), .Q(registers_14__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1169 (.A1(registers_7__ap[24]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[24]), .ZN(n_1_0_1112)); + SDFF_X1_LVT \registers_reg[9][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_9__ap[24]), .CK(n_0_39), .Q(registers_9__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[29][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_29__ap[24]), .CK(n_0_59), .Q(registers_29__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1168 (.A1(registers_9__ap[24]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[24]), .ZN(n_1_0_1111)); + SDFF_X1_LVT \registers_reg[23][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_23__ap[24]), .CK(n_0_53), .Q(registers_23__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[3][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_3__ap[24]), .CK(n_0_33), .Q(registers_3__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1167 (.A1(registers_23__ap[24]), .A2(n_1_0_1264), .B1( + n_1_0_1257), .B2(registers_3__ap[24]), .ZN(n_1_0_1110)); + NAND3_X1_LVT i_1_0_1166 (.A1(n_1_0_1112), .A2(n_1_0_1111), .A3(n_1_0_1110), + .ZN(n_1_0_1109)); + SDFF_X1_LVT \registers_reg[27][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_27__ap[24]), .CK(n_0_57), .Q(registers_27__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[31][24] (.D(registers[24]), .SE(1'b0), .SI( + registers_31__ap[24]), .CK(n_0_61), .Q(registers_31__ap[24]), .QN()); + AOI221_X1_LVT i_1_0_1165 (.A(n_1_0_1109), .B1(n_1_0_1279), .B2( + registers_27__ap[24]), .C1(registers_31__ap[24]), .C2(n_1_0_1266), + .ZN(n_1_0_1108)); + NAND4_X1_LVT i_1_0_1164 (.A1(n_1_0_1125), .A2(n_1_0_1118), .A3(n_1_0_1113), + .A4(n_1_0_1108), .ZN(RRs1[24])); + AND2_X1_LVT i_0_0_23 (.A1(n_0_0_16), .A2(WRd[23]), .ZN(registers[23])); + SDFF_X1_LVT \registers_reg[9][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_9__ap[23]), .CK(n_0_39), .Q(registers_9__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[28][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_28__ap[23]), .CK(n_0_58), .Q(registers_28__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1163 (.A1(registers_9__ap[23]), .A2(n_1_0_1291), .B1( + n_1_0_1283), .B2(registers_28__ap[23]), .ZN(n_1_0_1107)); + SDFF_X1_LVT \registers_reg[18][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_18__ap[23]), .CK(n_0_48), .Q(registers_18__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[22][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_22__ap[23]), .CK(n_0_52), .Q(registers_22__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1160 (.A1(registers_18__ap[23]), .A2(n_1_0_1297), .B1( + n_1_0_1294), .B2(registers_22__ap[23]), .ZN(n_1_0_1104)); + SDFF_X1_LVT \registers_reg[1][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_1__ap[23]), .CK(n_0_0), .Q(registers_1__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[21][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_21__ap[23]), .CK(n_0_51), .Q(registers_21__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1159 (.A1(registers_1__ap[23]), .A2(n_1_0_1274), .B1( + n_1_0_1259), .B2(registers_21__ap[23]), .ZN(n_1_0_1103)); + NAND3_X1_LVT i_1_0_1157 (.A1(n_1_0_1107), .A2(n_1_0_1104), .A3(n_1_0_1103), + .ZN(n_1_0_1101)); + SDFF_X1_LVT \registers_reg[20][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_20__ap[23]), .CK(n_0_50), .Q(registers_20__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[19][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_19__ap[23]), .CK(n_0_49), .Q(registers_19__ap[23]), .QN()); + AOI221_X1_LVT i_1_0_1156 (.A(n_1_0_1101), .B1(n_1_0_1281), .B2( + registers_20__ap[23]), .C1(registers_19__ap[23]), .C2(n_1_0_1295), + .ZN(n_1_0_1100)); + SDFF_X1_LVT \registers_reg[26][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_26__ap[23]), .CK(n_0_56), .Q(registers_26__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[23][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_23__ap[23]), .CK(n_0_53), .Q(registers_23__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1162 (.A1(registers_26__ap[23]), .A2(n_1_0_1285), .B1( + n_1_0_1264), .B2(registers_23__ap[23]), .ZN(n_1_0_1106)); + SDFF_X1_LVT \registers_reg[29][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_29__ap[23]), .CK(n_0_59), .Q(registers_29__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[3][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_3__ap[23]), .CK(n_0_33), .Q(registers_3__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1161 (.A1(registers_29__ap[23]), .A2(n_1_0_1276), .B1( + n_1_0_1257), .B2(registers_3__ap[23]), .ZN(n_1_0_1105)); + SDFF_X1_LVT \registers_reg[30][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_30__ap[23]), .CK(n_0_60), .Q(registers_30__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[31][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_31__ap[23]), .CK(n_0_61), .Q(registers_31__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1158 (.A1(registers_30__ap[23]), .A2(n_1_0_1272), .B1( + n_1_0_1266), .B2(registers_31__ap[23]), .ZN(n_1_0_1102)); + NAND3_X1_LVT i_1_0_1155 (.A1(n_1_0_1106), .A2(n_1_0_1105), .A3(n_1_0_1102), + .ZN(n_1_0_1099)); + SDFF_X1_LVT \registers_reg[8][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_8__ap[23]), .CK(n_0_38), .Q(registers_8__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[17][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_17__ap[23]), .CK(n_0_47), .Q(registers_17__ap[23]), .QN()); + AOI221_X1_LVT i_1_0_1154 (.A(n_1_0_1099), .B1(n_1_0_1282), .B2( + registers_8__ap[23]), .C1(registers_17__ap[23]), .C2(n_1_0_1271), .ZN( + n_1_0_1098)); + SDFF_X1_LVT \registers_reg[24][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_24__ap[23]), .CK(n_0_54), .Q(registers_24__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[15][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_15__ap[23]), .CK(n_0_45), .Q(registers_15__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[14][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_14__ap[23]), .CK(n_0_44), .Q(registers_14__ap[23]), .QN()); + AOI222_X1_LVT i_1_0_1153 (.A1(registers_24__ap[23]), .A2(n_1_0_1289), + .B1(n_1_0_1286), .B2(registers_15__ap[23]), .C1(n_1_0_1258), .C2( + registers_14__ap[23]), .ZN(n_1_0_1097)); + SDFF_X1_LVT \registers_reg[16][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_16__ap[23]), .CK(n_0_46), .Q(registers_16__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[7][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_7__ap[23]), .CK(n_0_37), .Q(registers_7__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1152 (.A1(registers_16__ap[23]), .A2(n_1_0_1267), .B1( + n_1_0_1263), .B2(registers_7__ap[23]), .ZN(n_1_0_1096)); + SDFF_X1_LVT \registers_reg[6][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_6__ap[23]), .CK(n_0_36), .Q(registers_6__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[25][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_25__ap[23]), .CK(n_0_55), .Q(registers_25__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1151 (.A1(registers_6__ap[23]), .A2(n_1_0_1300), .B1( + n_1_0_1269), .B2(registers_25__ap[23]), .ZN(n_1_0_1095)); + SDFF_X1_LVT \registers_reg[27][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_27__ap[23]), .CK(n_0_57), .Q(registers_27__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[11][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_11__ap[23]), .CK(n_0_41), .Q(registers_11__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1150 (.A1(registers_27__ap[23]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[23]), .ZN(n_1_0_1094)); + SDFF_X1_LVT \registers_reg[13][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_13__ap[23]), .CK(n_0_43), .Q(registers_13__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[5][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_5__ap[23]), .CK(n_0_35), .Q(registers_5__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1149 (.A1(registers_13__ap[23]), .A2(n_1_0_1277), .B1( + n_1_0_1273), .B2(registers_5__ap[23]), .ZN(n_1_0_1093)); + SDFF_X1_LVT \registers_reg[4][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_4__ap[23]), .CK(n_0_34), .Q(registers_4__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[12][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_12__ap[23]), .CK(n_0_42), .Q(registers_12__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1148 (.A1(registers_4__ap[23]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[23]), .ZN(n_1_0_1092)); + NAND3_X1_LVT i_1_0_1147 (.A1(n_1_0_1094), .A2(n_1_0_1093), .A3(n_1_0_1092), + .ZN(n_1_0_1091)); + SDFF_X1_LVT \registers_reg[2][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_2__ap[23]), .CK(n_0_32), .Q(registers_2__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[10][23] (.D(registers[23]), .SE(1'b0), .SI( + registers_10__ap[23]), .CK(n_0_40), .Q(registers_10__ap[23]), .QN()); + AOI221_X1_LVT i_1_0_1146 (.A(n_1_0_1091), .B1(n_1_0_1268), .B2( + registers_2__ap[23]), .C1(registers_10__ap[23]), .C2(n_1_0_1287), .ZN( + n_1_0_1090)); + AND4_X1_LVT i_1_0_1145 (.A1(n_1_0_1097), .A2(n_1_0_1096), .A3(n_1_0_1095), + .A4(n_1_0_1090), .ZN(n_1_0_1089)); + NAND3_X1_LVT i_1_0_1144 (.A1(n_1_0_1100), .A2(n_1_0_1098), .A3(n_1_0_1089), + .ZN(RRs1[23])); + AND2_X1_LVT i_0_0_22 (.A1(n_0_0_16), .A2(WRd[22]), .ZN(registers[22])); + SDFF_X1_LVT \registers_reg[17][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_17__ap[22]), .CK(n_0_47), .Q(registers_17__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[21][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_21__ap[22]), .CK(n_0_51), .Q(registers_21__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1142 (.A1(registers_17__ap[22]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[22]), .ZN(n_1_0_1087)); + SDFF_X1_LVT \registers_reg[6][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_6__ap[22]), .CK(n_0_36), .Q(registers_6__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[11][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_11__ap[22]), .CK(n_0_41), .Q(registers_11__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1143 (.A1(registers_6__ap[22]), .A2(n_1_0_1300), .B1( + n_1_0_1270), .B2(registers_11__ap[22]), .ZN(n_1_0_1088)); + SDFF_X1_LVT \registers_reg[20][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_20__ap[22]), .CK(n_0_50), .Q(registers_20__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[12][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_12__ap[22]), .CK(n_0_42), .Q(registers_12__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1141 (.A1(registers_20__ap[22]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[22]), .ZN(n_1_0_1086)); + SDFF_X1_LVT \registers_reg[10][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_10__ap[22]), .CK(n_0_40), .Q(registers_10__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[5][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_5__ap[22]), .CK(n_0_35), .Q(registers_5__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1140 (.A1(registers_10__ap[22]), .A2(n_1_0_1287), .B1( + n_1_0_1273), .B2(registers_5__ap[22]), .ZN(n_1_0_1085)); + NAND3_X1_LVT i_1_0_1139 (.A1(n_1_0_1088), .A2(n_1_0_1086), .A3(n_1_0_1085), + .ZN(n_1_0_1084)); + SDFF_X1_LVT \registers_reg[31][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_31__ap[22]), .CK(n_0_61), .Q(registers_31__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[2][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_2__ap[22]), .CK(n_0_32), .Q(registers_2__ap[22]), .QN()); + AOI221_X1_LVT i_1_0_1138 (.A(n_1_0_1084), .B1(n_1_0_1266), .B2( + registers_31__ap[22]), .C1(registers_2__ap[22]), .C2(n_1_0_1268), .ZN( + n_1_0_1083)); + SDFF_X1_LVT \registers_reg[22][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_22__ap[22]), .CK(n_0_52), .Q(registers_22__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[26][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_26__ap[22]), .CK(n_0_56), .Q(registers_26__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[13][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_13__ap[22]), .CK(n_0_43), .Q(registers_13__ap[22]), .QN()); + AOI222_X1_LVT i_1_0_1137 (.A1(registers_22__ap[22]), .A2(n_1_0_1294), + .B1(n_1_0_1285), .B2(registers_26__ap[22]), .C1(n_1_0_1277), .C2( + registers_13__ap[22]), .ZN(n_1_0_1082)); + NAND2_X1_LVT i_1_0_1136 (.A1(n_1_0_1083), .A2(n_1_0_1082), .ZN(n_1_0_1081)); + SDFF_X1_LVT \registers_reg[1][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_1__ap[22]), .CK(n_0_0), .Q(registers_1__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[28][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_28__ap[22]), .CK(n_0_58), .Q(registers_28__ap[22]), .QN()); + AOI221_X1_LVT i_1_0_1135 (.A(n_1_0_1081), .B1(n_1_0_1274), .B2( + registers_1__ap[22]), .C1(registers_28__ap[22]), .C2(n_1_0_1283), .ZN( + n_1_0_1080)); + SDFF_X1_LVT \registers_reg[18][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_18__ap[22]), .CK(n_0_48), .Q(registers_18__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[30][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_30__ap[22]), .CK(n_0_60), .Q(registers_30__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1134 (.A1(registers_18__ap[22]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[22]), .ZN(n_1_0_1079)); + SDFF_X1_LVT \registers_reg[24][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_24__ap[22]), .CK(n_0_54), .Q(registers_24__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[4][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_4__ap[22]), .CK(n_0_34), .Q(registers_4__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1133 (.A1(registers_24__ap[22]), .A2(n_1_0_1289), .B1( + n_1_0_1278), .B2(registers_4__ap[22]), .ZN(n_1_0_1078)); + SDFF_X1_LVT \registers_reg[15][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_15__ap[22]), .CK(n_0_45), .Q(registers_15__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[16][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_16__ap[22]), .CK(n_0_46), .Q(registers_16__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1132 (.A1(registers_15__ap[22]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[22]), .ZN(n_1_0_1077)); + NAND3_X1_LVT i_1_0_1131 (.A1(n_1_0_1079), .A2(n_1_0_1078), .A3(n_1_0_1077), + .ZN(n_1_0_1076)); + SDFF_X1_LVT \registers_reg[19][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_19__ap[22]), .CK(n_0_49), .Q(registers_19__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[25][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_25__ap[22]), .CK(n_0_55), .Q(registers_25__ap[22]), .QN()); + AOI221_X1_LVT i_1_0_1130 (.A(n_1_0_1076), .B1(n_1_0_1295), .B2( + registers_19__ap[22]), .C1(registers_25__ap[22]), .C2(n_1_0_1269), + .ZN(n_1_0_1075)); + SDFF_X1_LVT \registers_reg[7][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_7__ap[22]), .CK(n_0_37), .Q(registers_7__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[14][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_14__ap[22]), .CK(n_0_44), .Q(registers_14__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1129 (.A1(registers_7__ap[22]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[22]), .ZN(n_1_0_1074)); + SDFF_X1_LVT \registers_reg[9][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_9__ap[22]), .CK(n_0_39), .Q(registers_9__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[29][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_29__ap[22]), .CK(n_0_59), .Q(registers_29__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1128 (.A1(registers_9__ap[22]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[22]), .ZN(n_1_0_1073)); + SDFF_X1_LVT \registers_reg[8][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_8__ap[22]), .CK(n_0_38), .Q(registers_8__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[23][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_23__ap[22]), .CK(n_0_53), .Q(registers_23__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1127 (.A1(registers_8__ap[22]), .A2(n_1_0_1282), .B1( + n_1_0_1264), .B2(registers_23__ap[22]), .ZN(n_1_0_1072)); + NAND3_X1_LVT i_1_0_1126 (.A1(n_1_0_1074), .A2(n_1_0_1073), .A3(n_1_0_1072), + .ZN(n_1_0_1071)); + SDFF_X1_LVT \registers_reg[27][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_27__ap[22]), .CK(n_0_57), .Q(registers_27__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[3][22] (.D(registers[22]), .SE(1'b0), .SI( + registers_3__ap[22]), .CK(n_0_33), .Q(registers_3__ap[22]), .QN()); + AOI221_X1_LVT i_1_0_1125 (.A(n_1_0_1071), .B1(n_1_0_1279), .B2( + registers_27__ap[22]), .C1(registers_3__ap[22]), .C2(n_1_0_1257), .ZN( + n_1_0_1070)); + NAND4_X1_LVT i_1_0_1124 (.A1(n_1_0_1087), .A2(n_1_0_1080), .A3(n_1_0_1075), + .A4(n_1_0_1070), .ZN(RRs1[22])); + AND2_X1_LVT i_0_0_21 (.A1(n_0_0_16), .A2(WRd[21]), .ZN(registers[21])); + SDFF_X1_LVT \registers_reg[17][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_17__ap[21]), .CK(n_0_47), .Q(registers_17__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[21][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_21__ap[21]), .CK(n_0_51), .Q(registers_21__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1122 (.A1(registers_17__ap[21]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[21]), .ZN(n_1_0_1068)); + SDFF_X1_LVT \registers_reg[6][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_6__ap[21]), .CK(n_0_36), .Q(registers_6__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[8][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_8__ap[21]), .CK(n_0_38), .Q(registers_8__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1123 (.A1(registers_6__ap[21]), .A2(n_1_0_1300), .B1( + n_1_0_1282), .B2(registers_8__ap[21]), .ZN(n_1_0_1069)); + SDFF_X1_LVT \registers_reg[20][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_20__ap[21]), .CK(n_0_50), .Q(registers_20__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[12][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_12__ap[21]), .CK(n_0_42), .Q(registers_12__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1121 (.A1(registers_20__ap[21]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[21]), .ZN(n_1_0_1067)); + SDFF_X1_LVT \registers_reg[5][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_5__ap[21]), .CK(n_0_35), .Q(registers_5__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[11][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_11__ap[21]), .CK(n_0_41), .Q(registers_11__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1120 (.A1(registers_5__ap[21]), .A2(n_1_0_1273), .B1( + n_1_0_1270), .B2(registers_11__ap[21]), .ZN(n_1_0_1066)); + NAND3_X1_LVT i_1_0_1119 (.A1(n_1_0_1069), .A2(n_1_0_1067), .A3(n_1_0_1066), + .ZN(n_1_0_1065)); + SDFF_X1_LVT \registers_reg[10][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_10__ap[21]), .CK(n_0_40), .Q(registers_10__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[2][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_2__ap[21]), .CK(n_0_32), .Q(registers_2__ap[21]), .QN()); + AOI221_X1_LVT i_1_0_1118 (.A(n_1_0_1065), .B1(n_1_0_1287), .B2( + registers_10__ap[21]), .C1(registers_2__ap[21]), .C2(n_1_0_1268), .ZN( + n_1_0_1064)); + SDFF_X1_LVT \registers_reg[13][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_13__ap[21]), .CK(n_0_43), .Q(registers_13__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[30][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_30__ap[21]), .CK(n_0_60), .Q(registers_30__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[22][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_22__ap[21]), .CK(n_0_52), .Q(registers_22__ap[21]), .QN()); + AOI222_X1_LVT i_1_0_1117 (.A1(registers_13__ap[21]), .A2(n_1_0_1277), + .B1(n_1_0_1272), .B2(registers_30__ap[21]), .C1(registers_22__ap[21]), + .C2(n_1_0_1294), .ZN(n_1_0_1063)); + NAND2_X1_LVT i_1_0_1116 (.A1(n_1_0_1064), .A2(n_1_0_1063), .ZN(n_1_0_1062)); + SDFF_X1_LVT \registers_reg[1][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_1__ap[21]), .CK(n_0_0), .Q(registers_1__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[28][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_28__ap[21]), .CK(n_0_58), .Q(registers_28__ap[21]), .QN()); + AOI221_X1_LVT i_1_0_1115 (.A(n_1_0_1062), .B1(n_1_0_1274), .B2( + registers_1__ap[21]), .C1(registers_28__ap[21]), .C2(n_1_0_1283), .ZN( + n_1_0_1061)); + SDFF_X1_LVT \registers_reg[18][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_18__ap[21]), .CK(n_0_48), .Q(registers_18__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[26][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_26__ap[21]), .CK(n_0_56), .Q(registers_26__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1114 (.A1(registers_18__ap[21]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[21]), .ZN(n_1_0_1060)); + SDFF_X1_LVT \registers_reg[24][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_24__ap[21]), .CK(n_0_54), .Q(registers_24__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[4][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_4__ap[21]), .CK(n_0_34), .Q(registers_4__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1113 (.A1(registers_24__ap[21]), .A2(n_1_0_1289), .B1( + n_1_0_1278), .B2(registers_4__ap[21]), .ZN(n_1_0_1059)); + SDFF_X1_LVT \registers_reg[15][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_15__ap[21]), .CK(n_0_45), .Q(registers_15__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[16][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_16__ap[21]), .CK(n_0_46), .Q(registers_16__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1112 (.A1(registers_15__ap[21]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[21]), .ZN(n_1_0_1058)); + NAND3_X1_LVT i_1_0_1111 (.A1(n_1_0_1060), .A2(n_1_0_1059), .A3(n_1_0_1058), + .ZN(n_1_0_1057)); + SDFF_X1_LVT \registers_reg[19][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_19__ap[21]), .CK(n_0_49), .Q(registers_19__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[25][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_25__ap[21]), .CK(n_0_55), .Q(registers_25__ap[21]), .QN()); + AOI221_X1_LVT i_1_0_1110 (.A(n_1_0_1057), .B1(n_1_0_1295), .B2( + registers_19__ap[21]), .C1(registers_25__ap[21]), .C2(n_1_0_1269), + .ZN(n_1_0_1056)); + SDFF_X1_LVT \registers_reg[7][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_7__ap[21]), .CK(n_0_37), .Q(registers_7__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[14][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_14__ap[21]), .CK(n_0_44), .Q(registers_14__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1109 (.A1(registers_7__ap[21]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[21]), .ZN(n_1_0_1055)); + SDFF_X1_LVT \registers_reg[9][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_9__ap[21]), .CK(n_0_39), .Q(registers_9__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[29][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_29__ap[21]), .CK(n_0_59), .Q(registers_29__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1108 (.A1(registers_9__ap[21]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[21]), .ZN(n_1_0_1054)); + SDFF_X1_LVT \registers_reg[23][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_23__ap[21]), .CK(n_0_53), .Q(registers_23__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[3][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_3__ap[21]), .CK(n_0_33), .Q(registers_3__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1107 (.A1(registers_23__ap[21]), .A2(n_1_0_1264), .B1( + n_1_0_1257), .B2(registers_3__ap[21]), .ZN(n_1_0_1053)); + NAND3_X1_LVT i_1_0_1106 (.A1(n_1_0_1055), .A2(n_1_0_1054), .A3(n_1_0_1053), + .ZN(n_1_0_1052)); + SDFF_X1_LVT \registers_reg[27][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_27__ap[21]), .CK(n_0_57), .Q(registers_27__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[31][21] (.D(registers[21]), .SE(1'b0), .SI( + registers_31__ap[21]), .CK(n_0_61), .Q(registers_31__ap[21]), .QN()); + AOI221_X1_LVT i_1_0_1105 (.A(n_1_0_1052), .B1(n_1_0_1279), .B2( + registers_27__ap[21]), .C1(registers_31__ap[21]), .C2(n_1_0_1266), + .ZN(n_1_0_1051)); + NAND4_X1_LVT i_1_0_1104 (.A1(n_1_0_1068), .A2(n_1_0_1061), .A3(n_1_0_1056), + .A4(n_1_0_1051), .ZN(RRs1[21])); + AND2_X1_LVT i_0_0_20 (.A1(n_0_0_16), .A2(WRd[20]), .ZN(registers[20])); + SDFF_X1_LVT \registers_reg[17][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_17__ap[20]), .CK(n_0_47), .Q(registers_17__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[21][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_21__ap[20]), .CK(n_0_51), .Q(registers_21__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1100 (.A1(registers_17__ap[20]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[20]), .ZN(n_1_0_1047)); + SDFF_X1_LVT \registers_reg[10][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_10__ap[20]), .CK(n_0_40), .Q(registers_10__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[2][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_2__ap[20]), .CK(n_0_32), .Q(registers_2__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1103 (.A1(registers_10__ap[20]), .A2(n_1_0_1287), .B1( + n_1_0_1268), .B2(registers_2__ap[20]), .ZN(n_1_0_1050)); + SDFF_X1_LVT \registers_reg[20][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_20__ap[20]), .CK(n_0_50), .Q(registers_20__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[12][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_12__ap[20]), .CK(n_0_42), .Q(registers_12__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1099 (.A1(registers_20__ap[20]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[20]), .ZN(n_1_0_1046)); + SDFF_X1_LVT \registers_reg[15][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_15__ap[20]), .CK(n_0_45), .Q(registers_15__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[8][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_8__ap[20]), .CK(n_0_38), .Q(registers_8__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1102 (.A1(registers_15__ap[20]), .A2(n_1_0_1286), .B1( + n_1_0_1282), .B2(registers_8__ap[20]), .ZN(n_1_0_1049)); + INV_X1_LVT i_1_0_1101 (.A(n_1_0_1049), .ZN(n_1_0_1048)); + SDFF_X1_LVT \registers_reg[11][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_11__ap[20]), .CK(n_0_41), .Q(registers_11__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[5][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_5__ap[20]), .CK(n_0_35), .Q(registers_5__ap[20]), .QN()); + AOI221_X1_LVT i_1_0_1098 (.A(n_1_0_1048), .B1(n_1_0_1270), .B2( + registers_11__ap[20]), .C1(registers_5__ap[20]), .C2(n_1_0_1273), .ZN( + n_1_0_1045)); + SDFF_X1_LVT \registers_reg[13][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_13__ap[20]), .CK(n_0_43), .Q(registers_13__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[30][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_30__ap[20]), .CK(n_0_60), .Q(registers_30__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[22][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_22__ap[20]), .CK(n_0_52), .Q(registers_22__ap[20]), .QN()); + AOI222_X1_LVT i_1_0_1097 (.A1(registers_13__ap[20]), .A2(n_1_0_1277), + .B1(n_1_0_1272), .B2(registers_30__ap[20]), .C1(registers_22__ap[20]), + .C2(n_1_0_1294), .ZN(n_1_0_1044)); + NAND4_X1_LVT i_1_0_1096 (.A1(n_1_0_1050), .A2(n_1_0_1046), .A3(n_1_0_1045), + .A4(n_1_0_1044), .ZN(n_1_0_1043)); + SDFF_X1_LVT \registers_reg[1][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_1__ap[20]), .CK(n_0_0), .Q(registers_1__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[28][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_28__ap[20]), .CK(n_0_58), .Q(registers_28__ap[20]), .QN()); + AOI221_X1_LVT i_1_0_1095 (.A(n_1_0_1043), .B1(n_1_0_1274), .B2( + registers_1__ap[20]), .C1(registers_28__ap[20]), .C2(n_1_0_1283), .ZN( + n_1_0_1042)); + SDFF_X1_LVT \registers_reg[18][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_18__ap[20]), .CK(n_0_48), .Q(registers_18__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[26][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_26__ap[20]), .CK(n_0_56), .Q(registers_26__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1094 (.A1(registers_18__ap[20]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[20]), .ZN(n_1_0_1041)); + SDFF_X1_LVT \registers_reg[24][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_24__ap[20]), .CK(n_0_54), .Q(registers_24__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[4][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_4__ap[20]), .CK(n_0_34), .Q(registers_4__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1093 (.A1(registers_24__ap[20]), .A2(n_1_0_1289), .B1( + n_1_0_1278), .B2(registers_4__ap[20]), .ZN(n_1_0_1040)); + SDFF_X1_LVT \registers_reg[6][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_6__ap[20]), .CK(n_0_36), .Q(registers_6__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[25][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_25__ap[20]), .CK(n_0_55), .Q(registers_25__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1092 (.A1(registers_6__ap[20]), .A2(n_1_0_1300), .B1( + n_1_0_1269), .B2(registers_25__ap[20]), .ZN(n_1_0_1039)); + NAND3_X1_LVT i_1_0_1091 (.A1(n_1_0_1041), .A2(n_1_0_1040), .A3(n_1_0_1039), + .ZN(n_1_0_1038)); + SDFF_X1_LVT \registers_reg[19][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_19__ap[20]), .CK(n_0_49), .Q(registers_19__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[16][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_16__ap[20]), .CK(n_0_46), .Q(registers_16__ap[20]), .QN()); + AOI221_X1_LVT i_1_0_1090 (.A(n_1_0_1038), .B1(n_1_0_1295), .B2( + registers_19__ap[20]), .C1(registers_16__ap[20]), .C2(n_1_0_1267), + .ZN(n_1_0_1037)); + SDFF_X1_LVT \registers_reg[7][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_7__ap[20]), .CK(n_0_37), .Q(registers_7__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[14][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_14__ap[20]), .CK(n_0_44), .Q(registers_14__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1089 (.A1(registers_7__ap[20]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[20]), .ZN(n_1_0_1036)); + SDFF_X1_LVT \registers_reg[9][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_9__ap[20]), .CK(n_0_39), .Q(registers_9__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[29][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_29__ap[20]), .CK(n_0_59), .Q(registers_29__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1088 (.A1(registers_9__ap[20]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[20]), .ZN(n_1_0_1035)); + SDFF_X1_LVT \registers_reg[23][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_23__ap[20]), .CK(n_0_53), .Q(registers_23__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[3][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_3__ap[20]), .CK(n_0_33), .Q(registers_3__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1087 (.A1(registers_23__ap[20]), .A2(n_1_0_1264), .B1( + n_1_0_1257), .B2(registers_3__ap[20]), .ZN(n_1_0_1034)); + NAND3_X1_LVT i_1_0_1086 (.A1(n_1_0_1036), .A2(n_1_0_1035), .A3(n_1_0_1034), + .ZN(n_1_0_1033)); + SDFF_X1_LVT \registers_reg[27][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_27__ap[20]), .CK(n_0_57), .Q(registers_27__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[31][20] (.D(registers[20]), .SE(1'b0), .SI( + registers_31__ap[20]), .CK(n_0_61), .Q(registers_31__ap[20]), .QN()); + AOI221_X1_LVT i_1_0_1085 (.A(n_1_0_1033), .B1(n_1_0_1279), .B2( + registers_27__ap[20]), .C1(registers_31__ap[20]), .C2(n_1_0_1266), + .ZN(n_1_0_1032)); + NAND4_X1_LVT i_1_0_1084 (.A1(n_1_0_1047), .A2(n_1_0_1042), .A3(n_1_0_1037), + .A4(n_1_0_1032), .ZN(RRs1[20])); + AND2_X1_LVT i_0_0_19 (.A1(n_0_0_16), .A2(WRd[19]), .ZN(registers[19])); + SDFF_X1_LVT \registers_reg[17][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_17__ap[19]), .CK(n_0_47), .Q(registers_17__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[21][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_21__ap[19]), .CK(n_0_51), .Q(registers_21__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1080 (.A1(registers_17__ap[19]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[19]), .ZN(n_1_0_1028)); + SDFF_X1_LVT \registers_reg[2][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_2__ap[19]), .CK(n_0_32), .Q(registers_2__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[31][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_31__ap[19]), .CK(n_0_61), .Q(registers_31__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1083 (.A1(registers_2__ap[19]), .A2(n_1_0_1268), .B1( + n_1_0_1266), .B2(registers_31__ap[19]), .ZN(n_1_0_1031)); + SDFF_X1_LVT \registers_reg[20][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_20__ap[19]), .CK(n_0_50), .Q(registers_20__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[12][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_12__ap[19]), .CK(n_0_42), .Q(registers_12__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1079 (.A1(registers_20__ap[19]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[19]), .ZN(n_1_0_1027)); + SDFF_X1_LVT \registers_reg[15][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_15__ap[19]), .CK(n_0_45), .Q(registers_15__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[11][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_11__ap[19]), .CK(n_0_41), .Q(registers_11__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1082 (.A1(registers_15__ap[19]), .A2(n_1_0_1286), .B1( + n_1_0_1270), .B2(registers_11__ap[19]), .ZN(n_1_0_1030)); + INV_X1_LVT i_1_0_1081 (.A(n_1_0_1030), .ZN(n_1_0_1029)); + SDFF_X1_LVT \registers_reg[27][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_27__ap[19]), .CK(n_0_57), .Q(registers_27__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[24][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_24__ap[19]), .CK(n_0_54), .Q(registers_24__ap[19]), .QN()); + AOI221_X1_LVT i_1_0_1078 (.A(n_1_0_1029), .B1(n_1_0_1279), .B2( + registers_27__ap[19]), .C1(registers_24__ap[19]), .C2(n_1_0_1289), + .ZN(n_1_0_1026)); + SDFF_X1_LVT \registers_reg[22][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_22__ap[19]), .CK(n_0_52), .Q(registers_22__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[26][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_26__ap[19]), .CK(n_0_56), .Q(registers_26__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[13][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_13__ap[19]), .CK(n_0_43), .Q(registers_13__ap[19]), .QN()); + AOI222_X1_LVT i_1_0_1077 (.A1(registers_22__ap[19]), .A2(n_1_0_1294), + .B1(n_1_0_1285), .B2(registers_26__ap[19]), .C1(n_1_0_1277), .C2( + registers_13__ap[19]), .ZN(n_1_0_1025)); + NAND4_X1_LVT i_1_0_1076 (.A1(n_1_0_1031), .A2(n_1_0_1027), .A3(n_1_0_1026), + .A4(n_1_0_1025), .ZN(n_1_0_1024)); + SDFF_X1_LVT \registers_reg[1][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_1__ap[19]), .CK(n_0_0), .Q(registers_1__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[28][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_28__ap[19]), .CK(n_0_58), .Q(registers_28__ap[19]), .QN()); + AOI221_X1_LVT i_1_0_1075 (.A(n_1_0_1024), .B1(n_1_0_1274), .B2( + registers_1__ap[19]), .C1(registers_28__ap[19]), .C2(n_1_0_1283), .ZN( + n_1_0_1023)); + SDFF_X1_LVT \registers_reg[18][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_18__ap[19]), .CK(n_0_48), .Q(registers_18__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[30][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_30__ap[19]), .CK(n_0_60), .Q(registers_30__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1074 (.A1(registers_18__ap[19]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[19]), .ZN(n_1_0_1022)); + SDFF_X1_LVT \registers_reg[4][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_4__ap[19]), .CK(n_0_34), .Q(registers_4__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[5][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_5__ap[19]), .CK(n_0_35), .Q(registers_5__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1073 (.A1(registers_4__ap[19]), .A2(n_1_0_1278), .B1( + n_1_0_1273), .B2(registers_5__ap[19]), .ZN(n_1_0_1021)); + SDFF_X1_LVT \registers_reg[6][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_6__ap[19]), .CK(n_0_36), .Q(registers_6__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[25][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_25__ap[19]), .CK(n_0_55), .Q(registers_25__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1072 (.A1(registers_6__ap[19]), .A2(n_1_0_1300), .B1( + n_1_0_1269), .B2(registers_25__ap[19]), .ZN(n_1_0_1020)); + NAND3_X1_LVT i_1_0_1071 (.A1(n_1_0_1022), .A2(n_1_0_1021), .A3(n_1_0_1020), + .ZN(n_1_0_1019)); + SDFF_X1_LVT \registers_reg[19][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_19__ap[19]), .CK(n_0_49), .Q(registers_19__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[16][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_16__ap[19]), .CK(n_0_46), .Q(registers_16__ap[19]), .QN()); + AOI221_X1_LVT i_1_0_1070 (.A(n_1_0_1019), .B1(n_1_0_1295), .B2( + registers_19__ap[19]), .C1(registers_16__ap[19]), .C2(n_1_0_1267), + .ZN(n_1_0_1018)); + SDFF_X1_LVT \registers_reg[9][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_9__ap[19]), .CK(n_0_39), .Q(registers_9__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[29][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_29__ap[19]), .CK(n_0_59), .Q(registers_29__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1069 (.A1(registers_9__ap[19]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[19]), .ZN(n_1_0_1017)); + SDFF_X1_LVT \registers_reg[8][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_8__ap[19]), .CK(n_0_38), .Q(registers_8__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[23][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_23__ap[19]), .CK(n_0_53), .Q(registers_23__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1068 (.A1(registers_8__ap[19]), .A2(n_1_0_1282), .B1( + n_1_0_1264), .B2(registers_23__ap[19]), .ZN(n_1_0_1016)); + SDFF_X1_LVT \registers_reg[7][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_7__ap[19]), .CK(n_0_37), .Q(registers_7__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[14][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_14__ap[19]), .CK(n_0_44), .Q(registers_14__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1067 (.A1(registers_7__ap[19]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[19]), .ZN(n_1_0_1015)); + NAND3_X1_LVT i_1_0_1066 (.A1(n_1_0_1017), .A2(n_1_0_1016), .A3(n_1_0_1015), + .ZN(n_1_0_1014)); + SDFF_X1_LVT \registers_reg[10][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_10__ap[19]), .CK(n_0_40), .Q(registers_10__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[3][19] (.D(registers[19]), .SE(1'b0), .SI( + registers_3__ap[19]), .CK(n_0_33), .Q(registers_3__ap[19]), .QN()); + AOI221_X1_LVT i_1_0_1065 (.A(n_1_0_1014), .B1(n_1_0_1287), .B2( + registers_10__ap[19]), .C1(registers_3__ap[19]), .C2(n_1_0_1257), .ZN( + n_1_0_1013)); + NAND4_X1_LVT i_1_0_1064 (.A1(n_1_0_1028), .A2(n_1_0_1023), .A3(n_1_0_1018), + .A4(n_1_0_1013), .ZN(RRs1[19])); + AND2_X1_LVT i_0_0_18 (.A1(n_0_0_16), .A2(WRd[18]), .ZN(registers[18])); + SDFF_X1_LVT \registers_reg[24][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_24__ap[18]), .CK(n_0_54), .Q(registers_24__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[28][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_28__ap[18]), .CK(n_0_58), .Q(registers_28__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1062 (.A1(registers_24__ap[18]), .A2(n_1_0_1289), .B1( + n_1_0_1283), .B2(registers_28__ap[18]), .ZN(n_1_0_1011)); + SDFF_X1_LVT \registers_reg[11][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_11__ap[18]), .CK(n_0_41), .Q(registers_11__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[16][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_16__ap[18]), .CK(n_0_46), .Q(registers_16__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1063 (.A1(registers_11__ap[18]), .A2(n_1_0_1270), .B1( + n_1_0_1267), .B2(registers_16__ap[18]), .ZN(n_1_0_1012)); + SDFF_X1_LVT \registers_reg[9][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_9__ap[18]), .CK(n_0_39), .Q(registers_9__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[7][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_7__ap[18]), .CK(n_0_37), .Q(registers_7__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1061 (.A1(registers_9__ap[18]), .A2(n_1_0_1291), .B1( + n_1_0_1263), .B2(registers_7__ap[18]), .ZN(n_1_0_1010)); + SDFF_X1_LVT \registers_reg[27][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_27__ap[18]), .CK(n_0_57), .Q(registers_27__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[25][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_25__ap[18]), .CK(n_0_55), .Q(registers_25__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1060 (.A1(registers_27__ap[18]), .A2(n_1_0_1279), .B1( + n_1_0_1269), .B2(registers_25__ap[18]), .ZN(n_1_0_1009)); + NAND3_X1_LVT i_1_0_1059 (.A1(n_1_0_1012), .A2(n_1_0_1010), .A3(n_1_0_1009), + .ZN(n_1_0_1008)); + SDFF_X1_LVT \registers_reg[31][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_31__ap[18]), .CK(n_0_61), .Q(registers_31__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[6][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_6__ap[18]), .CK(n_0_36), .Q(registers_6__ap[18]), .QN()); + AOI221_X1_LVT i_1_0_1058 (.A(n_1_0_1008), .B1(n_1_0_1266), .B2( + registers_31__ap[18]), .C1(registers_6__ap[18]), .C2(n_1_0_1300), .ZN( + n_1_0_1007)); + SDFF_X1_LVT \registers_reg[22][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_22__ap[18]), .CK(n_0_52), .Q(registers_22__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[26][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_26__ap[18]), .CK(n_0_56), .Q(registers_26__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[1][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_1__ap[18]), .CK(n_0_0), .Q(registers_1__ap[18]), .QN()); + AOI222_X1_LVT i_1_0_1057 (.A1(registers_22__ap[18]), .A2(n_1_0_1294), + .B1(n_1_0_1285), .B2(registers_26__ap[18]), .C1(n_1_0_1274), .C2( + registers_1__ap[18]), .ZN(n_1_0_1006)); + NAND2_X1_LVT i_1_0_1056 (.A1(n_1_0_1007), .A2(n_1_0_1006), .ZN(n_1_0_1005)); + SDFF_X1_LVT \registers_reg[29][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_29__ap[18]), .CK(n_0_59), .Q(registers_29__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[2][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_2__ap[18]), .CK(n_0_32), .Q(registers_2__ap[18]), .QN()); + AOI221_X1_LVT i_1_0_1055 (.A(n_1_0_1005), .B1(n_1_0_1276), .B2( + registers_29__ap[18]), .C1(registers_2__ap[18]), .C2(n_1_0_1268), .ZN( + n_1_0_1004)); + SDFF_X1_LVT \registers_reg[18][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_18__ap[18]), .CK(n_0_48), .Q(registers_18__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[30][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_30__ap[18]), .CK(n_0_60), .Q(registers_30__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1054 (.A1(registers_18__ap[18]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[18]), .ZN(n_1_0_1003)); + SDFF_X1_LVT \registers_reg[4][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_4__ap[18]), .CK(n_0_34), .Q(registers_4__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[12][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_12__ap[18]), .CK(n_0_42), .Q(registers_12__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1053 (.A1(registers_4__ap[18]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[18]), .ZN(n_1_0_1002)); + SDFF_X1_LVT \registers_reg[19][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_19__ap[18]), .CK(n_0_49), .Q(registers_19__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[21][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_21__ap[18]), .CK(n_0_51), .Q(registers_21__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1052 (.A1(registers_19__ap[18]), .A2(n_1_0_1295), .B1( + n_1_0_1259), .B2(registers_21__ap[18]), .ZN(n_1_0_1001)); + NAND3_X1_LVT i_1_0_1051 (.A1(n_1_0_1003), .A2(n_1_0_1002), .A3(n_1_0_1001), + .ZN(n_1_0_1000)); + SDFF_X1_LVT \registers_reg[5][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_5__ap[18]), .CK(n_0_35), .Q(registers_5__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[20][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_20__ap[18]), .CK(n_0_50), .Q(registers_20__ap[18]), .QN()); + AOI221_X1_LVT i_1_0_1050 (.A(n_1_0_1000), .B1(n_1_0_1273), .B2( + registers_5__ap[18]), .C1(registers_20__ap[18]), .C2(n_1_0_1281), .ZN( + n_1_0_999)); + SDFF_X1_LVT \registers_reg[8][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_8__ap[18]), .CK(n_0_38), .Q(registers_8__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[23][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_23__ap[18]), .CK(n_0_53), .Q(registers_23__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1049 (.A1(registers_8__ap[18]), .A2(n_1_0_1282), .B1( + n_1_0_1264), .B2(registers_23__ap[18]), .ZN(n_1_0_998)); + SDFF_X1_LVT \registers_reg[13][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_13__ap[18]), .CK(n_0_43), .Q(registers_13__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[17][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_17__ap[18]), .CK(n_0_47), .Q(registers_17__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1048 (.A1(registers_13__ap[18]), .A2(n_1_0_1277), .B1( + n_1_0_1271), .B2(registers_17__ap[18]), .ZN(n_1_0_997)); + SDFF_X1_LVT \registers_reg[15][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_15__ap[18]), .CK(n_0_45), .Q(registers_15__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[14][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_14__ap[18]), .CK(n_0_44), .Q(registers_14__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1047 (.A1(registers_15__ap[18]), .A2(n_1_0_1286), .B1( + n_1_0_1258), .B2(registers_14__ap[18]), .ZN(n_1_0_996)); + NAND3_X1_LVT i_1_0_1046 (.A1(n_1_0_998), .A2(n_1_0_997), .A3(n_1_0_996), + .ZN(n_1_0_995)); + SDFF_X1_LVT \registers_reg[10][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_10__ap[18]), .CK(n_0_40), .Q(registers_10__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[3][18] (.D(registers[18]), .SE(1'b0), .SI( + registers_3__ap[18]), .CK(n_0_33), .Q(registers_3__ap[18]), .QN()); + AOI221_X1_LVT i_1_0_1045 (.A(n_1_0_995), .B1(n_1_0_1287), .B2( + registers_10__ap[18]), .C1(registers_3__ap[18]), .C2(n_1_0_1257), .ZN( + n_1_0_994)); + NAND4_X1_LVT i_1_0_1044 (.A1(n_1_0_1011), .A2(n_1_0_1004), .A3(n_1_0_999), + .A4(n_1_0_994), .ZN(RRs1[18])); + AND2_X1_LVT i_0_0_17 (.A1(n_0_0_16), .A2(WRd[17]), .ZN(registers[17])); + SDFF_X1_LVT \registers_reg[17][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_17__ap[17]), .CK(n_0_47), .Q(registers_17__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[21][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_21__ap[17]), .CK(n_0_51), .Q(registers_21__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1040 (.A1(registers_17__ap[17]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[17]), .ZN(n_1_0_990)); + SDFF_X1_LVT \registers_reg[2][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_2__ap[17]), .CK(n_0_32), .Q(registers_2__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[31][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_31__ap[17]), .CK(n_0_61), .Q(registers_31__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1043 (.A1(registers_2__ap[17]), .A2(n_1_0_1268), .B1( + n_1_0_1266), .B2(registers_31__ap[17]), .ZN(n_1_0_993)); + SDFF_X1_LVT \registers_reg[20][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_20__ap[17]), .CK(n_0_50), .Q(registers_20__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[12][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_12__ap[17]), .CK(n_0_42), .Q(registers_12__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1039 (.A1(registers_20__ap[17]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[17]), .ZN(n_1_0_989)); + SDFF_X1_LVT \registers_reg[15][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_15__ap[17]), .CK(n_0_45), .Q(registers_15__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[11][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_11__ap[17]), .CK(n_0_41), .Q(registers_11__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1042 (.A1(registers_15__ap[17]), .A2(n_1_0_1286), .B1( + n_1_0_1270), .B2(registers_11__ap[17]), .ZN(n_1_0_992)); + INV_X1_LVT i_1_0_1041 (.A(n_1_0_992), .ZN(n_1_0_991)); + SDFF_X1_LVT \registers_reg[10][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_10__ap[17]), .CK(n_0_40), .Q(registers_10__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[24][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_24__ap[17]), .CK(n_0_54), .Q(registers_24__ap[17]), .QN()); + AOI221_X1_LVT i_1_0_1038 (.A(n_1_0_991), .B1(n_1_0_1287), .B2( + registers_10__ap[17]), .C1(registers_24__ap[17]), .C2(n_1_0_1289), + .ZN(n_1_0_988)); + SDFF_X1_LVT \registers_reg[22][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_22__ap[17]), .CK(n_0_52), .Q(registers_22__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[26][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_26__ap[17]), .CK(n_0_56), .Q(registers_26__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[13][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_13__ap[17]), .CK(n_0_43), .Q(registers_13__ap[17]), .QN()); + AOI222_X1_LVT i_1_0_1037 (.A1(registers_22__ap[17]), .A2(n_1_0_1294), + .B1(n_1_0_1285), .B2(registers_26__ap[17]), .C1(n_1_0_1277), .C2( + registers_13__ap[17]), .ZN(n_1_0_987)); + NAND4_X1_LVT i_1_0_1036 (.A1(n_1_0_993), .A2(n_1_0_989), .A3(n_1_0_988), + .A4(n_1_0_987), .ZN(n_1_0_986)); + SDFF_X1_LVT \registers_reg[1][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_1__ap[17]), .CK(n_0_0), .Q(registers_1__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[28][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_28__ap[17]), .CK(n_0_58), .Q(registers_28__ap[17]), .QN()); + AOI221_X1_LVT i_1_0_1035 (.A(n_1_0_986), .B1(n_1_0_1274), .B2( + registers_1__ap[17]), .C1(registers_28__ap[17]), .C2(n_1_0_1283), .ZN( + n_1_0_985)); + SDFF_X1_LVT \registers_reg[18][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_18__ap[17]), .CK(n_0_48), .Q(registers_18__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[30][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_30__ap[17]), .CK(n_0_60), .Q(registers_30__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1034 (.A1(registers_18__ap[17]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[17]), .ZN(n_1_0_984)); + SDFF_X1_LVT \registers_reg[4][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_4__ap[17]), .CK(n_0_34), .Q(registers_4__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[5][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_5__ap[17]), .CK(n_0_35), .Q(registers_5__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1033 (.A1(registers_4__ap[17]), .A2(n_1_0_1278), .B1( + n_1_0_1273), .B2(registers_5__ap[17]), .ZN(n_1_0_983)); + SDFF_X1_LVT \registers_reg[6][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_6__ap[17]), .CK(n_0_36), .Q(registers_6__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[25][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_25__ap[17]), .CK(n_0_55), .Q(registers_25__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1032 (.A1(registers_6__ap[17]), .A2(n_1_0_1300), .B1( + n_1_0_1269), .B2(registers_25__ap[17]), .ZN(n_1_0_982)); + NAND3_X1_LVT i_1_0_1031 (.A1(n_1_0_984), .A2(n_1_0_983), .A3(n_1_0_982), + .ZN(n_1_0_981)); + SDFF_X1_LVT \registers_reg[19][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_19__ap[17]), .CK(n_0_49), .Q(registers_19__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[16][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_16__ap[17]), .CK(n_0_46), .Q(registers_16__ap[17]), .QN()); + AOI221_X1_LVT i_1_0_1030 (.A(n_1_0_981), .B1(n_1_0_1295), .B2( + registers_19__ap[17]), .C1(registers_16__ap[17]), .C2(n_1_0_1267), + .ZN(n_1_0_980)); + SDFF_X1_LVT \registers_reg[7][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_7__ap[17]), .CK(n_0_37), .Q(registers_7__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[14][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_14__ap[17]), .CK(n_0_44), .Q(registers_14__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1029 (.A1(registers_7__ap[17]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[17]), .ZN(n_1_0_979)); + SDFF_X1_LVT \registers_reg[9][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_9__ap[17]), .CK(n_0_39), .Q(registers_9__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[29][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_29__ap[17]), .CK(n_0_59), .Q(registers_29__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1028 (.A1(registers_9__ap[17]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[17]), .ZN(n_1_0_978)); + SDFF_X1_LVT \registers_reg[8][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_8__ap[17]), .CK(n_0_38), .Q(registers_8__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[23][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_23__ap[17]), .CK(n_0_53), .Q(registers_23__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1027 (.A1(registers_8__ap[17]), .A2(n_1_0_1282), .B1( + n_1_0_1264), .B2(registers_23__ap[17]), .ZN(n_1_0_977)); + NAND3_X1_LVT i_1_0_1026 (.A1(n_1_0_979), .A2(n_1_0_978), .A3(n_1_0_977), + .ZN(n_1_0_976)); + SDFF_X1_LVT \registers_reg[27][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_27__ap[17]), .CK(n_0_57), .Q(registers_27__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[3][17] (.D(registers[17]), .SE(1'b0), .SI( + registers_3__ap[17]), .CK(n_0_33), .Q(registers_3__ap[17]), .QN()); + AOI221_X1_LVT i_1_0_1025 (.A(n_1_0_976), .B1(n_1_0_1279), .B2( + registers_27__ap[17]), .C1(registers_3__ap[17]), .C2(n_1_0_1257), .ZN( + n_1_0_975)); + NAND4_X1_LVT i_1_0_1024 (.A1(n_1_0_990), .A2(n_1_0_985), .A3(n_1_0_980), + .A4(n_1_0_975), .ZN(RRs1[17])); + AND2_X1_LVT i_0_0_16 (.A1(n_0_0_16), .A2(WRd[16]), .ZN(registers[16])); + SDFF_X1_LVT \registers_reg[29][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_29__ap[16]), .CK(n_0_59), .Q(registers_29__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[2][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_2__ap[16]), .CK(n_0_32), .Q(registers_2__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1022 (.A1(registers_29__ap[16]), .A2(n_1_0_1276), .B1( + n_1_0_1268), .B2(registers_2__ap[16]), .ZN(n_1_0_973)); + SDFF_X1_LVT \registers_reg[11][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_11__ap[16]), .CK(n_0_41), .Q(registers_11__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[25][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_25__ap[16]), .CK(n_0_55), .Q(registers_25__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1023 (.A1(registers_11__ap[16]), .A2(n_1_0_1270), .B1( + n_1_0_1269), .B2(registers_25__ap[16]), .ZN(n_1_0_974)); + SDFF_X1_LVT \registers_reg[9][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_9__ap[16]), .CK(n_0_39), .Q(registers_9__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[7][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_7__ap[16]), .CK(n_0_37), .Q(registers_7__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1021 (.A1(registers_9__ap[16]), .A2(n_1_0_1291), .B1( + n_1_0_1263), .B2(registers_7__ap[16]), .ZN(n_1_0_972)); + SDFF_X1_LVT \registers_reg[10][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_10__ap[16]), .CK(n_0_40), .Q(registers_10__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[16][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_16__ap[16]), .CK(n_0_46), .Q(registers_16__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1020 (.A1(registers_10__ap[16]), .A2(n_1_0_1287), .B1( + n_1_0_1267), .B2(registers_16__ap[16]), .ZN(n_1_0_971)); + NAND3_X1_LVT i_1_0_1019 (.A1(n_1_0_974), .A2(n_1_0_972), .A3(n_1_0_971), + .ZN(n_1_0_970)); + SDFF_X1_LVT \registers_reg[31][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_31__ap[16]), .CK(n_0_61), .Q(registers_31__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[6][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_6__ap[16]), .CK(n_0_36), .Q(registers_6__ap[16]), .QN()); + AOI221_X1_LVT i_1_0_1018 (.A(n_1_0_970), .B1(n_1_0_1266), .B2( + registers_31__ap[16]), .C1(registers_6__ap[16]), .C2(n_1_0_1300), .ZN( + n_1_0_969)); + SDFF_X1_LVT \registers_reg[18][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_18__ap[16]), .CK(n_0_48), .Q(registers_18__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[22][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_22__ap[16]), .CK(n_0_52), .Q(registers_22__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[1][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_1__ap[16]), .CK(n_0_0), .Q(registers_1__ap[16]), .QN()); + AOI222_X1_LVT i_1_0_1017 (.A1(registers_18__ap[16]), .A2(n_1_0_1297), + .B1(n_1_0_1294), .B2(registers_22__ap[16]), .C1(registers_1__ap[16]), + .C2(n_1_0_1274), .ZN(n_1_0_968)); + NAND3_X1_LVT i_1_0_1016 (.A1(n_1_0_973), .A2(n_1_0_969), .A3(n_1_0_968), + .ZN(n_1_0_967)); + SDFF_X1_LVT \registers_reg[5][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_5__ap[16]), .CK(n_0_35), .Q(registers_5__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[28][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_28__ap[16]), .CK(n_0_58), .Q(registers_28__ap[16]), .QN()); + AOI221_X1_LVT i_1_0_1015 (.A(n_1_0_967), .B1(n_1_0_1273), .B2( + registers_5__ap[16]), .C1(registers_28__ap[16]), .C2(n_1_0_1283), .ZN( + n_1_0_966)); + SDFF_X1_LVT \registers_reg[4][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_4__ap[16]), .CK(n_0_34), .Q(registers_4__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[12][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_12__ap[16]), .CK(n_0_42), .Q(registers_12__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1014 (.A1(registers_4__ap[16]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[16]), .ZN(n_1_0_965)); + SDFF_X1_LVT \registers_reg[19][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_19__ap[16]), .CK(n_0_49), .Q(registers_19__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[21][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_21__ap[16]), .CK(n_0_51), .Q(registers_21__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1013 (.A1(registers_19__ap[16]), .A2(n_1_0_1295), .B1( + n_1_0_1259), .B2(registers_21__ap[16]), .ZN(n_1_0_964)); + SDFF_X1_LVT \registers_reg[24][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_24__ap[16]), .CK(n_0_54), .Q(registers_24__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[20][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_20__ap[16]), .CK(n_0_50), .Q(registers_20__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1012 (.A1(registers_24__ap[16]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[16]), .ZN(n_1_0_963)); + NAND3_X1_LVT i_1_0_1011 (.A1(n_1_0_965), .A2(n_1_0_964), .A3(n_1_0_963), + .ZN(n_1_0_962)); + SDFF_X1_LVT \registers_reg[26][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_26__ap[16]), .CK(n_0_56), .Q(registers_26__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[30][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_30__ap[16]), .CK(n_0_60), .Q(registers_30__ap[16]), .QN()); + AOI221_X1_LVT i_1_0_1010 (.A(n_1_0_962), .B1(n_1_0_1285), .B2( + registers_26__ap[16]), .C1(registers_30__ap[16]), .C2(n_1_0_1272), + .ZN(n_1_0_961)); + SDFF_X1_LVT \registers_reg[8][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_8__ap[16]), .CK(n_0_38), .Q(registers_8__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[23][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_23__ap[16]), .CK(n_0_53), .Q(registers_23__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1009 (.A1(registers_8__ap[16]), .A2(n_1_0_1282), .B1( + n_1_0_1264), .B2(registers_23__ap[16]), .ZN(n_1_0_960)); + SDFF_X1_LVT \registers_reg[13][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_13__ap[16]), .CK(n_0_43), .Q(registers_13__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[17][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_17__ap[16]), .CK(n_0_47), .Q(registers_17__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1008 (.A1(registers_13__ap[16]), .A2(n_1_0_1277), .B1( + n_1_0_1271), .B2(registers_17__ap[16]), .ZN(n_1_0_959)); + SDFF_X1_LVT \registers_reg[15][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_15__ap[16]), .CK(n_0_45), .Q(registers_15__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[14][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_14__ap[16]), .CK(n_0_44), .Q(registers_14__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1007 (.A1(registers_15__ap[16]), .A2(n_1_0_1286), .B1( + n_1_0_1258), .B2(registers_14__ap[16]), .ZN(n_1_0_958)); + NAND3_X1_LVT i_1_0_1006 (.A1(n_1_0_960), .A2(n_1_0_959), .A3(n_1_0_958), + .ZN(n_1_0_957)); + SDFF_X1_LVT \registers_reg[27][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_27__ap[16]), .CK(n_0_57), .Q(registers_27__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[3][16] (.D(registers[16]), .SE(1'b0), .SI( + registers_3__ap[16]), .CK(n_0_33), .Q(registers_3__ap[16]), .QN()); + AOI221_X1_LVT i_1_0_1005 (.A(n_1_0_957), .B1(n_1_0_1279), .B2( + registers_27__ap[16]), .C1(registers_3__ap[16]), .C2(n_1_0_1257), .ZN( + n_1_0_956)); + NAND3_X1_LVT i_1_0_1004 (.A1(n_1_0_966), .A2(n_1_0_961), .A3(n_1_0_956), + .ZN(RRs1[16])); + AND2_X1_LVT i_0_0_15 (.A1(n_0_0_16), .A2(WRd[15]), .ZN(registers[15])); + SDFF_X1_LVT \registers_reg[17][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_17__ap[15]), .CK(n_0_47), .Q(registers_17__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[21][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_21__ap[15]), .CK(n_0_51), .Q(registers_21__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_1000 (.A1(registers_17__ap[15]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[15]), .ZN(n_1_0_952)); + SDFF_X1_LVT \registers_reg[10][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_10__ap[15]), .CK(n_0_40), .Q(registers_10__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[2][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_2__ap[15]), .CK(n_0_32), .Q(registers_2__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_1003 (.A1(registers_10__ap[15]), .A2(n_1_0_1287), .B1( + n_1_0_1268), .B2(registers_2__ap[15]), .ZN(n_1_0_955)); + SDFF_X1_LVT \registers_reg[20][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_20__ap[15]), .CK(n_0_50), .Q(registers_20__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[12][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_12__ap[15]), .CK(n_0_42), .Q(registers_12__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_999 (.A1(registers_20__ap[15]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[15]), .ZN(n_1_0_951)); + SDFF_X1_LVT \registers_reg[15][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_15__ap[15]), .CK(n_0_45), .Q(registers_15__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[8][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_8__ap[15]), .CK(n_0_38), .Q(registers_8__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_1002 (.A1(registers_15__ap[15]), .A2(n_1_0_1286), .B1( + n_1_0_1282), .B2(registers_8__ap[15]), .ZN(n_1_0_954)); + INV_X1_LVT i_1_0_1001 (.A(n_1_0_954), .ZN(n_1_0_953)); + SDFF_X1_LVT \registers_reg[11][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_11__ap[15]), .CK(n_0_41), .Q(registers_11__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[24][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_24__ap[15]), .CK(n_0_54), .Q(registers_24__ap[15]), .QN()); + AOI221_X1_LVT i_1_0_998 (.A(n_1_0_953), .B1(n_1_0_1270), .B2( + registers_11__ap[15]), .C1(registers_24__ap[15]), .C2(n_1_0_1289), + .ZN(n_1_0_950)); + SDFF_X1_LVT \registers_reg[13][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_13__ap[15]), .CK(n_0_43), .Q(registers_13__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[30][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_30__ap[15]), .CK(n_0_60), .Q(registers_30__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[22][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_22__ap[15]), .CK(n_0_52), .Q(registers_22__ap[15]), .QN()); + AOI222_X1_LVT i_1_0_997 (.A1(registers_13__ap[15]), .A2(n_1_0_1277), .B1( + n_1_0_1272), .B2(registers_30__ap[15]), .C1(registers_22__ap[15]), + .C2(n_1_0_1294), .ZN(n_1_0_949)); + NAND4_X1_LVT i_1_0_996 (.A1(n_1_0_955), .A2(n_1_0_951), .A3(n_1_0_950), + .A4(n_1_0_949), .ZN(n_1_0_948)); + SDFF_X1_LVT \registers_reg[1][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_1__ap[15]), .CK(n_0_0), .Q(registers_1__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[28][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_28__ap[15]), .CK(n_0_58), .Q(registers_28__ap[15]), .QN()); + AOI221_X1_LVT i_1_0_995 (.A(n_1_0_948), .B1(n_1_0_1274), .B2( + registers_1__ap[15]), .C1(registers_28__ap[15]), .C2(n_1_0_1283), .ZN( + n_1_0_947)); + SDFF_X1_LVT \registers_reg[18][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_18__ap[15]), .CK(n_0_48), .Q(registers_18__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[26][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_26__ap[15]), .CK(n_0_56), .Q(registers_26__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_994 (.A1(registers_18__ap[15]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[15]), .ZN(n_1_0_946)); + SDFF_X1_LVT \registers_reg[4][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_4__ap[15]), .CK(n_0_34), .Q(registers_4__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[5][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_5__ap[15]), .CK(n_0_35), .Q(registers_5__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_993 (.A1(registers_4__ap[15]), .A2(n_1_0_1278), .B1( + n_1_0_1273), .B2(registers_5__ap[15]), .ZN(n_1_0_945)); + SDFF_X1_LVT \registers_reg[6][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_6__ap[15]), .CK(n_0_36), .Q(registers_6__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[16][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_16__ap[15]), .CK(n_0_46), .Q(registers_16__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_992 (.A1(registers_6__ap[15]), .A2(n_1_0_1300), .B1( + n_1_0_1267), .B2(registers_16__ap[15]), .ZN(n_1_0_944)); + NAND3_X1_LVT i_1_0_991 (.A1(n_1_0_946), .A2(n_1_0_945), .A3(n_1_0_944), + .ZN(n_1_0_943)); + SDFF_X1_LVT \registers_reg[19][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_19__ap[15]), .CK(n_0_49), .Q(registers_19__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[25][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_25__ap[15]), .CK(n_0_55), .Q(registers_25__ap[15]), .QN()); + AOI221_X1_LVT i_1_0_990 (.A(n_1_0_943), .B1(n_1_0_1295), .B2( + registers_19__ap[15]), .C1(registers_25__ap[15]), .C2(n_1_0_1269), + .ZN(n_1_0_942)); + SDFF_X1_LVT \registers_reg[7][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_7__ap[15]), .CK(n_0_37), .Q(registers_7__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[14][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_14__ap[15]), .CK(n_0_44), .Q(registers_14__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_989 (.A1(registers_7__ap[15]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[15]), .ZN(n_1_0_941)); + SDFF_X1_LVT \registers_reg[9][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_9__ap[15]), .CK(n_0_39), .Q(registers_9__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[29][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_29__ap[15]), .CK(n_0_59), .Q(registers_29__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_988 (.A1(registers_9__ap[15]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[15]), .ZN(n_1_0_940)); + SDFF_X1_LVT \registers_reg[23][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_23__ap[15]), .CK(n_0_53), .Q(registers_23__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[3][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_3__ap[15]), .CK(n_0_33), .Q(registers_3__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_987 (.A1(registers_23__ap[15]), .A2(n_1_0_1264), .B1( + n_1_0_1257), .B2(registers_3__ap[15]), .ZN(n_1_0_939)); + NAND3_X1_LVT i_1_0_986 (.A1(n_1_0_941), .A2(n_1_0_940), .A3(n_1_0_939), + .ZN(n_1_0_938)); + SDFF_X1_LVT \registers_reg[27][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_27__ap[15]), .CK(n_0_57), .Q(registers_27__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[31][15] (.D(registers[15]), .SE(1'b0), .SI( + registers_31__ap[15]), .CK(n_0_61), .Q(registers_31__ap[15]), .QN()); + AOI221_X1_LVT i_1_0_985 (.A(n_1_0_938), .B1(n_1_0_1279), .B2( + registers_27__ap[15]), .C1(registers_31__ap[15]), .C2(n_1_0_1266), + .ZN(n_1_0_937)); + NAND4_X1_LVT i_1_0_984 (.A1(n_1_0_952), .A2(n_1_0_947), .A3(n_1_0_942), + .A4(n_1_0_937), .ZN(RRs1[15])); + AND2_X1_LVT i_0_0_14 (.A1(n_0_0_16), .A2(WRd[14]), .ZN(registers[14])); + SDFF_X1_LVT \registers_reg[28][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_28__ap[14]), .CK(n_0_58), .Q(registers_28__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[5][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_5__ap[14]), .CK(n_0_35), .Q(registers_5__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_983 (.A1(registers_28__ap[14]), .A2(n_1_0_1283), .B1( + n_1_0_1273), .B2(registers_5__ap[14]), .ZN(n_1_0_936)); + SDFF_X1_LVT \registers_reg[18][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_18__ap[14]), .CK(n_0_48), .Q(registers_18__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[10][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_10__ap[14]), .CK(n_0_40), .Q(registers_10__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[8][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_8__ap[14]), .CK(n_0_38), .Q(registers_8__ap[14]), .QN()); + AOI222_X1_LVT i_1_0_982 (.A1(registers_18__ap[14]), .A2(n_1_0_1297), .B1( + n_1_0_1287), .B2(registers_10__ap[14]), .C1(n_1_0_1282), .C2( + registers_8__ap[14]), .ZN(n_1_0_935)); + SDFF_X1_LVT \registers_reg[9][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_9__ap[14]), .CK(n_0_39), .Q(registers_9__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[29][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_29__ap[14]), .CK(n_0_59), .Q(registers_29__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_981 (.A1(registers_9__ap[14]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[14]), .ZN(n_1_0_934)); + SDFF_X1_LVT \registers_reg[21][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_21__ap[14]), .CK(n_0_51), .Q(registers_21__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[14][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_14__ap[14]), .CK(n_0_44), .Q(registers_14__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_980 (.A1(registers_21__ap[14]), .A2(n_1_0_1259), .B1( + n_1_0_1258), .B2(registers_14__ap[14]), .ZN(n_1_0_933)); + SDFF_X1_LVT \registers_reg[16][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_16__ap[14]), .CK(n_0_46), .Q(registers_16__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[3][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_3__ap[14]), .CK(n_0_33), .Q(registers_3__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_979 (.A1(registers_16__ap[14]), .A2(n_1_0_1267), .B1( + n_1_0_1257), .B2(registers_3__ap[14]), .ZN(n_1_0_932)); + SDFF_X1_LVT \registers_reg[17][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_17__ap[14]), .CK(n_0_47), .Q(registers_17__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[31][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_31__ap[14]), .CK(n_0_61), .Q(registers_31__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_978 (.A1(registers_17__ap[14]), .A2(n_1_0_1271), .B1( + n_1_0_1266), .B2(registers_31__ap[14]), .ZN(n_1_0_931)); + SDFF_X1_LVT \registers_reg[15][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_15__ap[14]), .CK(n_0_45), .Q(registers_15__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[23][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_23__ap[14]), .CK(n_0_53), .Q(registers_23__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_977 (.A1(registers_15__ap[14]), .A2(n_1_0_1286), .B1( + n_1_0_1264), .B2(registers_23__ap[14]), .ZN(n_1_0_930)); + NAND4_X1_LVT i_1_0_976 (.A1(n_1_0_933), .A2(n_1_0_932), .A3(n_1_0_931), + .A4(n_1_0_930), .ZN(n_1_0_929)); + SDFF_X1_LVT \registers_reg[26][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_26__ap[14]), .CK(n_0_56), .Q(registers_26__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[30][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_30__ap[14]), .CK(n_0_60), .Q(registers_30__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_975 (.A1(registers_26__ap[14]), .A2(n_1_0_1285), .B1( + n_1_0_1272), .B2(registers_30__ap[14]), .ZN(n_1_0_928)); + SDFF_X1_LVT \registers_reg[20][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_20__ap[14]), .CK(n_0_50), .Q(registers_20__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[4][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_4__ap[14]), .CK(n_0_34), .Q(registers_4__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_974 (.A1(registers_20__ap[14]), .A2(n_1_0_1281), .B1( + n_1_0_1278), .B2(registers_4__ap[14]), .ZN(n_1_0_927)); + SDFF_X1_LVT \registers_reg[1][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_1__ap[14]), .CK(n_0_0), .Q(registers_1__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[2][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_2__ap[14]), .CK(n_0_32), .Q(registers_2__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_973 (.A1(registers_1__ap[14]), .A2(n_1_0_1274), .B1( + n_1_0_1268), .B2(registers_2__ap[14]), .ZN(n_1_0_926)); + SDFF_X1_LVT \registers_reg[24][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_24__ap[14]), .CK(n_0_54), .Q(registers_24__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[12][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_12__ap[14]), .CK(n_0_42), .Q(registers_12__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_972 (.A1(registers_24__ap[14]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[14]), .ZN(n_1_0_925)); + NAND4_X1_LVT i_1_0_971 (.A1(n_1_0_928), .A2(n_1_0_927), .A3(n_1_0_926), + .A4(n_1_0_925), .ZN(n_1_0_924)); + SDFF_X1_LVT \registers_reg[19][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_19__ap[14]), .CK(n_0_49), .Q(registers_19__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[22][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_22__ap[14]), .CK(n_0_52), .Q(registers_22__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_970 (.A1(registers_19__ap[14]), .A2(n_1_0_1295), .B1( + n_1_0_1294), .B2(registers_22__ap[14]), .ZN(n_1_0_923)); + SDFF_X1_LVT \registers_reg[13][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_13__ap[14]), .CK(n_0_43), .Q(registers_13__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[25][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_25__ap[14]), .CK(n_0_55), .Q(registers_25__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_969 (.A1(registers_13__ap[14]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[14]), .ZN(n_1_0_922)); + SDFF_X1_LVT \registers_reg[6][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_6__ap[14]), .CK(n_0_36), .Q(registers_6__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[7][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_7__ap[14]), .CK(n_0_37), .Q(registers_7__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_968 (.A1(registers_6__ap[14]), .A2(n_1_0_1300), .B1( + n_1_0_1263), .B2(registers_7__ap[14]), .ZN(n_1_0_921)); + SDFF_X1_LVT \registers_reg[27][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_27__ap[14]), .CK(n_0_57), .Q(registers_27__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[11][14] (.D(registers[14]), .SE(1'b0), .SI( + registers_11__ap[14]), .CK(n_0_41), .Q(registers_11__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_967 (.A1(registers_27__ap[14]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[14]), .ZN(n_1_0_920)); + NAND4_X1_LVT i_1_0_966 (.A1(n_1_0_923), .A2(n_1_0_922), .A3(n_1_0_921), + .A4(n_1_0_920), .ZN(n_1_0_919)); + NOR3_X1_LVT i_1_0_965 (.A1(n_1_0_929), .A2(n_1_0_924), .A3(n_1_0_919), + .ZN(n_1_0_918)); + NAND4_X1_LVT i_1_0_964 (.A1(n_1_0_936), .A2(n_1_0_935), .A3(n_1_0_934), + .A4(n_1_0_918), .ZN(RRs1[14])); + AND2_X1_LVT i_0_0_13 (.A1(n_0_0_16), .A2(WRd[13]), .ZN(registers[13])); + SDFF_X1_LVT \registers_reg[28][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_28__ap[13]), .CK(n_0_58), .Q(registers_28__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[4][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_4__ap[13]), .CK(n_0_34), .Q(registers_4__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_963 (.A1(registers_28__ap[13]), .A2(n_1_0_1283), .B1( + n_1_0_1278), .B2(registers_4__ap[13]), .ZN(n_1_0_917)); + SDFF_X1_LVT \registers_reg[10][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_10__ap[13]), .CK(n_0_40), .Q(registers_10__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[26][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_26__ap[13]), .CK(n_0_56), .Q(registers_26__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[8][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_8__ap[13]), .CK(n_0_38), .Q(registers_8__ap[13]), .QN()); + AOI222_X1_LVT i_1_0_962 (.A1(registers_10__ap[13]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[13]), .C1(registers_8__ap[13]), .C2( + n_1_0_1282), .ZN(n_1_0_916)); + SDFF_X1_LVT \registers_reg[9][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_9__ap[13]), .CK(n_0_39), .Q(registers_9__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[29][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_29__ap[13]), .CK(n_0_59), .Q(registers_29__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_961 (.A1(registers_9__ap[13]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[13]), .ZN(n_1_0_915)); + SDFF_X1_LVT \registers_reg[6][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_6__ap[13]), .CK(n_0_36), .Q(registers_6__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[1][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_1__ap[13]), .CK(n_0_0), .Q(registers_1__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_960 (.A1(registers_6__ap[13]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[13]), .ZN(n_1_0_914)); + SDFF_X1_LVT \registers_reg[5][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_5__ap[13]), .CK(n_0_35), .Q(registers_5__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[3][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_3__ap[13]), .CK(n_0_33), .Q(registers_3__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_959 (.A1(registers_5__ap[13]), .A2(n_1_0_1273), .B1( + n_1_0_1257), .B2(registers_3__ap[13]), .ZN(n_1_0_913)); + SDFF_X1_LVT \registers_reg[16][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_16__ap[13]), .CK(n_0_46), .Q(registers_16__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[31][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_31__ap[13]), .CK(n_0_61), .Q(registers_31__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_958 (.A1(registers_16__ap[13]), .A2(n_1_0_1267), .B1( + n_1_0_1266), .B2(registers_31__ap[13]), .ZN(n_1_0_912)); + SDFF_X1_LVT \registers_reg[15][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_15__ap[13]), .CK(n_0_45), .Q(registers_15__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[23][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_23__ap[13]), .CK(n_0_53), .Q(registers_23__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_957 (.A1(registers_15__ap[13]), .A2(n_1_0_1286), .B1( + n_1_0_1264), .B2(registers_23__ap[13]), .ZN(n_1_0_911)); + NAND4_X1_LVT i_1_0_956 (.A1(n_1_0_914), .A2(n_1_0_913), .A3(n_1_0_912), + .A4(n_1_0_911), .ZN(n_1_0_910)); + SDFF_X1_LVT \registers_reg[18][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_18__ap[13]), .CK(n_0_48), .Q(registers_18__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[30][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_30__ap[13]), .CK(n_0_60), .Q(registers_30__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_955 (.A1(registers_18__ap[13]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[13]), .ZN(n_1_0_909)); + SDFF_X1_LVT \registers_reg[24][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_24__ap[13]), .CK(n_0_54), .Q(registers_24__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[12][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_12__ap[13]), .CK(n_0_42), .Q(registers_12__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_954 (.A1(registers_24__ap[13]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[13]), .ZN(n_1_0_908)); + SDFF_X1_LVT \registers_reg[22][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_22__ap[13]), .CK(n_0_52), .Q(registers_22__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[21][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_21__ap[13]), .CK(n_0_51), .Q(registers_21__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_953 (.A1(registers_22__ap[13]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[13]), .ZN(n_1_0_907)); + SDFF_X1_LVT \registers_reg[20][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_20__ap[13]), .CK(n_0_50), .Q(registers_20__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[17][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_17__ap[13]), .CK(n_0_47), .Q(registers_17__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_952 (.A1(registers_20__ap[13]), .A2(n_1_0_1281), .B1( + n_1_0_1271), .B2(registers_17__ap[13]), .ZN(n_1_0_906)); + NAND4_X1_LVT i_1_0_951 (.A1(n_1_0_909), .A2(n_1_0_908), .A3(n_1_0_907), + .A4(n_1_0_906), .ZN(n_1_0_905)); + SDFF_X1_LVT \registers_reg[13][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_13__ap[13]), .CK(n_0_43), .Q(registers_13__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[25][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_25__ap[13]), .CK(n_0_55), .Q(registers_25__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_950 (.A1(registers_13__ap[13]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[13]), .ZN(n_1_0_904)); + SDFF_X1_LVT \registers_reg[19][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_19__ap[13]), .CK(n_0_49), .Q(registers_19__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[2][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_2__ap[13]), .CK(n_0_32), .Q(registers_2__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_949 (.A1(registers_19__ap[13]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[13]), .ZN(n_1_0_903)); + SDFF_X1_LVT \registers_reg[7][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_7__ap[13]), .CK(n_0_37), .Q(registers_7__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[14][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_14__ap[13]), .CK(n_0_44), .Q(registers_14__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_948 (.A1(registers_7__ap[13]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[13]), .ZN(n_1_0_902)); + SDFF_X1_LVT \registers_reg[27][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_27__ap[13]), .CK(n_0_57), .Q(registers_27__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[11][13] (.D(registers[13]), .SE(1'b0), .SI( + registers_11__ap[13]), .CK(n_0_41), .Q(registers_11__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_947 (.A1(registers_27__ap[13]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[13]), .ZN(n_1_0_901)); + NAND4_X1_LVT i_1_0_946 (.A1(n_1_0_904), .A2(n_1_0_903), .A3(n_1_0_902), + .A4(n_1_0_901), .ZN(n_1_0_900)); + NOR3_X1_LVT i_1_0_945 (.A1(n_1_0_910), .A2(n_1_0_905), .A3(n_1_0_900), + .ZN(n_1_0_899)); + NAND4_X1_LVT i_1_0_944 (.A1(n_1_0_917), .A2(n_1_0_916), .A3(n_1_0_915), + .A4(n_1_0_899), .ZN(RRs1[13])); + AND2_X1_LVT i_0_0_12 (.A1(n_0_0_16), .A2(WRd[12]), .ZN(registers[12])); + SDFF_X1_LVT \registers_reg[28][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_28__ap[12]), .CK(n_0_58), .Q(registers_28__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[17][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_17__ap[12]), .CK(n_0_47), .Q(registers_17__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_943 (.A1(registers_28__ap[12]), .A2(n_1_0_1283), .B1( + n_1_0_1271), .B2(registers_17__ap[12]), .ZN(n_1_0_898)); + SDFF_X1_LVT \registers_reg[10][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_10__ap[12]), .CK(n_0_40), .Q(registers_10__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[26][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_26__ap[12]), .CK(n_0_56), .Q(registers_26__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[8][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_8__ap[12]), .CK(n_0_38), .Q(registers_8__ap[12]), .QN()); + AOI222_X1_LVT i_1_0_942 (.A1(registers_10__ap[12]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[12]), .C1(registers_8__ap[12]), .C2( + n_1_0_1282), .ZN(n_1_0_897)); + SDFF_X1_LVT \registers_reg[9][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_9__ap[12]), .CK(n_0_39), .Q(registers_9__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[29][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_29__ap[12]), .CK(n_0_59), .Q(registers_29__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_941 (.A1(registers_9__ap[12]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[12]), .ZN(n_1_0_896)); + SDFF_X1_LVT \registers_reg[6][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_6__ap[12]), .CK(n_0_36), .Q(registers_6__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[1][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_1__ap[12]), .CK(n_0_0), .Q(registers_1__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_940 (.A1(registers_6__ap[12]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[12]), .ZN(n_1_0_895)); + SDFF_X1_LVT \registers_reg[16][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_16__ap[12]), .CK(n_0_46), .Q(registers_16__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[3][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_3__ap[12]), .CK(n_0_33), .Q(registers_3__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_939 (.A1(registers_16__ap[12]), .A2(n_1_0_1267), .B1( + n_1_0_1257), .B2(registers_3__ap[12]), .ZN(n_1_0_894)); + SDFF_X1_LVT \registers_reg[5][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_5__ap[12]), .CK(n_0_35), .Q(registers_5__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[31][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_31__ap[12]), .CK(n_0_61), .Q(registers_31__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_938 (.A1(registers_5__ap[12]), .A2(n_1_0_1273), .B1( + n_1_0_1266), .B2(registers_31__ap[12]), .ZN(n_1_0_893)); + SDFF_X1_LVT \registers_reg[15][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_15__ap[12]), .CK(n_0_45), .Q(registers_15__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[23][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_23__ap[12]), .CK(n_0_53), .Q(registers_23__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_937 (.A1(registers_15__ap[12]), .A2(n_1_0_1286), .B1( + n_1_0_1264), .B2(registers_23__ap[12]), .ZN(n_1_0_892)); + NAND4_X1_LVT i_1_0_936 (.A1(n_1_0_895), .A2(n_1_0_894), .A3(n_1_0_893), + .A4(n_1_0_892), .ZN(n_1_0_891)); + SDFF_X1_LVT \registers_reg[18][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_18__ap[12]), .CK(n_0_48), .Q(registers_18__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[30][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_30__ap[12]), .CK(n_0_60), .Q(registers_30__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_935 (.A1(registers_18__ap[12]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[12]), .ZN(n_1_0_890)); + SDFF_X1_LVT \registers_reg[20][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_20__ap[12]), .CK(n_0_50), .Q(registers_20__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[4][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_4__ap[12]), .CK(n_0_34), .Q(registers_4__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_934 (.A1(registers_20__ap[12]), .A2(n_1_0_1281), .B1( + n_1_0_1278), .B2(registers_4__ap[12]), .ZN(n_1_0_889)); + SDFF_X1_LVT \registers_reg[22][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_22__ap[12]), .CK(n_0_52), .Q(registers_22__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[21][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_21__ap[12]), .CK(n_0_51), .Q(registers_21__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_933 (.A1(registers_22__ap[12]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[12]), .ZN(n_1_0_888)); + SDFF_X1_LVT \registers_reg[24][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_24__ap[12]), .CK(n_0_54), .Q(registers_24__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[12][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_12__ap[12]), .CK(n_0_42), .Q(registers_12__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_932 (.A1(registers_24__ap[12]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[12]), .ZN(n_1_0_887)); + NAND4_X1_LVT i_1_0_931 (.A1(n_1_0_890), .A2(n_1_0_889), .A3(n_1_0_888), + .A4(n_1_0_887), .ZN(n_1_0_886)); + SDFF_X1_LVT \registers_reg[13][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_13__ap[12]), .CK(n_0_43), .Q(registers_13__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[25][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_25__ap[12]), .CK(n_0_55), .Q(registers_25__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_930 (.A1(registers_13__ap[12]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[12]), .ZN(n_1_0_885)); + SDFF_X1_LVT \registers_reg[19][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_19__ap[12]), .CK(n_0_49), .Q(registers_19__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[2][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_2__ap[12]), .CK(n_0_32), .Q(registers_2__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_929 (.A1(registers_19__ap[12]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[12]), .ZN(n_1_0_884)); + SDFF_X1_LVT \registers_reg[7][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_7__ap[12]), .CK(n_0_37), .Q(registers_7__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[14][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_14__ap[12]), .CK(n_0_44), .Q(registers_14__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_928 (.A1(registers_7__ap[12]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[12]), .ZN(n_1_0_883)); + SDFF_X1_LVT \registers_reg[27][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_27__ap[12]), .CK(n_0_57), .Q(registers_27__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[11][12] (.D(registers[12]), .SE(1'b0), .SI( + registers_11__ap[12]), .CK(n_0_41), .Q(registers_11__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_927 (.A1(registers_27__ap[12]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[12]), .ZN(n_1_0_882)); + NAND4_X1_LVT i_1_0_926 (.A1(n_1_0_885), .A2(n_1_0_884), .A3(n_1_0_883), + .A4(n_1_0_882), .ZN(n_1_0_881)); + NOR3_X1_LVT i_1_0_925 (.A1(n_1_0_891), .A2(n_1_0_886), .A3(n_1_0_881), + .ZN(n_1_0_880)); + NAND4_X1_LVT i_1_0_924 (.A1(n_1_0_898), .A2(n_1_0_897), .A3(n_1_0_896), + .A4(n_1_0_880), .ZN(RRs1[12])); + AND2_X1_LVT i_0_0_11 (.A1(n_0_0_16), .A2(WRd[11]), .ZN(registers[11])); + SDFF_X1_LVT \registers_reg[28][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_28__ap[11]), .CK(n_0_58), .Q(registers_28__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[17][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_17__ap[11]), .CK(n_0_47), .Q(registers_17__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_923 (.A1(registers_28__ap[11]), .A2(n_1_0_1283), .B1( + n_1_0_1271), .B2(registers_17__ap[11]), .ZN(n_1_0_879)); + SDFF_X1_LVT \registers_reg[10][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_10__ap[11]), .CK(n_0_40), .Q(registers_10__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[26][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_26__ap[11]), .CK(n_0_56), .Q(registers_26__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[8][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_8__ap[11]), .CK(n_0_38), .Q(registers_8__ap[11]), .QN()); + AOI222_X1_LVT i_1_0_922 (.A1(registers_10__ap[11]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[11]), .C1(registers_8__ap[11]), .C2( + n_1_0_1282), .ZN(n_1_0_878)); + SDFF_X1_LVT \registers_reg[9][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_9__ap[11]), .CK(n_0_39), .Q(registers_9__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[29][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_29__ap[11]), .CK(n_0_59), .Q(registers_29__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_921 (.A1(registers_9__ap[11]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[11]), .ZN(n_1_0_877)); + SDFF_X1_LVT \registers_reg[6][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_6__ap[11]), .CK(n_0_36), .Q(registers_6__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[1][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_1__ap[11]), .CK(n_0_0), .Q(registers_1__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_920 (.A1(registers_6__ap[11]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[11]), .ZN(n_1_0_876)); + SDFF_X1_LVT \registers_reg[5][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_5__ap[11]), .CK(n_0_35), .Q(registers_5__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[3][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_3__ap[11]), .CK(n_0_33), .Q(registers_3__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_919 (.A1(registers_5__ap[11]), .A2(n_1_0_1273), .B1( + n_1_0_1257), .B2(registers_3__ap[11]), .ZN(n_1_0_875)); + SDFF_X1_LVT \registers_reg[16][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_16__ap[11]), .CK(n_0_46), .Q(registers_16__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[31][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_31__ap[11]), .CK(n_0_61), .Q(registers_31__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_918 (.A1(registers_16__ap[11]), .A2(n_1_0_1267), .B1( + n_1_0_1266), .B2(registers_31__ap[11]), .ZN(n_1_0_874)); + SDFF_X1_LVT \registers_reg[15][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_15__ap[11]), .CK(n_0_45), .Q(registers_15__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[23][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_23__ap[11]), .CK(n_0_53), .Q(registers_23__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_917 (.A1(registers_15__ap[11]), .A2(n_1_0_1286), .B1( + n_1_0_1264), .B2(registers_23__ap[11]), .ZN(n_1_0_873)); + NAND4_X1_LVT i_1_0_916 (.A1(n_1_0_876), .A2(n_1_0_875), .A3(n_1_0_874), + .A4(n_1_0_873), .ZN(n_1_0_872)); + SDFF_X1_LVT \registers_reg[18][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_18__ap[11]), .CK(n_0_48), .Q(registers_18__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[30][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_30__ap[11]), .CK(n_0_60), .Q(registers_30__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_915 (.A1(registers_18__ap[11]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[11]), .ZN(n_1_0_871)); + SDFF_X1_LVT \registers_reg[20][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_20__ap[11]), .CK(n_0_50), .Q(registers_20__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[4][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_4__ap[11]), .CK(n_0_34), .Q(registers_4__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_914 (.A1(registers_20__ap[11]), .A2(n_1_0_1281), .B1( + n_1_0_1278), .B2(registers_4__ap[11]), .ZN(n_1_0_870)); + SDFF_X1_LVT \registers_reg[22][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_22__ap[11]), .CK(n_0_52), .Q(registers_22__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[21][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_21__ap[11]), .CK(n_0_51), .Q(registers_21__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_913 (.A1(registers_22__ap[11]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[11]), .ZN(n_1_0_869)); + SDFF_X1_LVT \registers_reg[24][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_24__ap[11]), .CK(n_0_54), .Q(registers_24__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[12][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_12__ap[11]), .CK(n_0_42), .Q(registers_12__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_912 (.A1(registers_24__ap[11]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[11]), .ZN(n_1_0_868)); + NAND4_X1_LVT i_1_0_911 (.A1(n_1_0_871), .A2(n_1_0_870), .A3(n_1_0_869), + .A4(n_1_0_868), .ZN(n_1_0_867)); + SDFF_X1_LVT \registers_reg[13][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_13__ap[11]), .CK(n_0_43), .Q(registers_13__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[25][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_25__ap[11]), .CK(n_0_55), .Q(registers_25__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_910 (.A1(registers_13__ap[11]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[11]), .ZN(n_1_0_866)); + SDFF_X1_LVT \registers_reg[19][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_19__ap[11]), .CK(n_0_49), .Q(registers_19__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[2][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_2__ap[11]), .CK(n_0_32), .Q(registers_2__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_909 (.A1(registers_19__ap[11]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[11]), .ZN(n_1_0_865)); + SDFF_X1_LVT \registers_reg[7][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_7__ap[11]), .CK(n_0_37), .Q(registers_7__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[14][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_14__ap[11]), .CK(n_0_44), .Q(registers_14__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_908 (.A1(registers_7__ap[11]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[11]), .ZN(n_1_0_864)); + SDFF_X1_LVT \registers_reg[27][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_27__ap[11]), .CK(n_0_57), .Q(registers_27__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[11][11] (.D(registers[11]), .SE(1'b0), .SI( + registers_11__ap[11]), .CK(n_0_41), .Q(registers_11__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_907 (.A1(registers_27__ap[11]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[11]), .ZN(n_1_0_863)); + NAND4_X1_LVT i_1_0_906 (.A1(n_1_0_866), .A2(n_1_0_865), .A3(n_1_0_864), + .A4(n_1_0_863), .ZN(n_1_0_862)); + NOR3_X1_LVT i_1_0_905 (.A1(n_1_0_872), .A2(n_1_0_867), .A3(n_1_0_862), + .ZN(n_1_0_861)); + NAND4_X1_LVT i_1_0_904 (.A1(n_1_0_879), .A2(n_1_0_878), .A3(n_1_0_877), + .A4(n_1_0_861), .ZN(RRs1[11])); + AND2_X1_LVT i_0_0_10 (.A1(n_0_0_16), .A2(WRd[10]), .ZN(registers[10])); + SDFF_X1_LVT \registers_reg[28][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_28__ap[10]), .CK(n_0_58), .Q(registers_28__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[8][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_8__ap[10]), .CK(n_0_38), .Q(registers_8__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_902 (.A1(registers_28__ap[10]), .A2(n_1_0_1283), .B1( + n_1_0_1282), .B2(registers_8__ap[10]), .ZN(n_1_0_859)); + SDFF_X1_LVT \registers_reg[31][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_31__ap[10]), .CK(n_0_61), .Q(registers_31__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[7][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_7__ap[10]), .CK(n_0_37), .Q(registers_7__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_903 (.A1(registers_31__ap[10]), .A2(n_1_0_1266), .B1( + n_1_0_1263), .B2(registers_7__ap[10]), .ZN(n_1_0_860)); + SDFF_X1_LVT \registers_reg[24][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_24__ap[10]), .CK(n_0_54), .Q(registers_24__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[20][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_20__ap[10]), .CK(n_0_50), .Q(registers_20__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_901 (.A1(registers_24__ap[10]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[10]), .ZN(n_1_0_858)); + SDFF_X1_LVT \registers_reg[4][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_4__ap[10]), .CK(n_0_34), .Q(registers_4__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[23][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_23__ap[10]), .CK(n_0_53), .Q(registers_23__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_900 (.A1(registers_4__ap[10]), .A2(n_1_0_1278), .B1( + n_1_0_1264), .B2(registers_23__ap[10]), .ZN(n_1_0_857)); + NAND3_X1_LVT i_1_0_899 (.A1(n_1_0_860), .A2(n_1_0_858), .A3(n_1_0_857), + .ZN(n_1_0_856)); + SDFF_X1_LVT \registers_reg[27][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_27__ap[10]), .CK(n_0_57), .Q(registers_27__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[29][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_29__ap[10]), .CK(n_0_59), .Q(registers_29__ap[10]), .QN()); + AOI221_X1_LVT i_1_0_898 (.A(n_1_0_856), .B1(n_1_0_1279), .B2( + registers_27__ap[10]), .C1(registers_29__ap[10]), .C2(n_1_0_1276), + .ZN(n_1_0_855)); + SDFF_X1_LVT \registers_reg[10][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_10__ap[10]), .CK(n_0_40), .Q(registers_10__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[30][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_30__ap[10]), .CK(n_0_60), .Q(registers_30__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[25][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_25__ap[10]), .CK(n_0_55), .Q(registers_25__ap[10]), .QN()); + AOI222_X1_LVT i_1_0_897 (.A1(registers_10__ap[10]), .A2(n_1_0_1287), .B1( + n_1_0_1272), .B2(registers_30__ap[10]), .C1(n_1_0_1269), .C2( + registers_25__ap[10]), .ZN(n_1_0_854)); + NAND3_X1_LVT i_1_0_896 (.A1(n_1_0_859), .A2(n_1_0_855), .A3(n_1_0_854), + .ZN(n_1_0_853)); + SDFF_X1_LVT \registers_reg[21][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_21__ap[10]), .CK(n_0_51), .Q(registers_21__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[13][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_13__ap[10]), .CK(n_0_43), .Q(registers_13__ap[10]), .QN()); + AOI221_X1_LVT i_1_0_895 (.A(n_1_0_853), .B1(n_1_0_1259), .B2( + registers_21__ap[10]), .C1(registers_13__ap[10]), .C2(n_1_0_1277), + .ZN(n_1_0_852)); + SDFF_X1_LVT \registers_reg[18][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_18__ap[10]), .CK(n_0_48), .Q(registers_18__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[26][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_26__ap[10]), .CK(n_0_56), .Q(registers_26__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_894 (.A1(registers_18__ap[10]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[10]), .ZN(n_1_0_851)); + SDFF_X1_LVT \registers_reg[17][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_17__ap[10]), .CK(n_0_47), .Q(registers_17__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[12][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_12__ap[10]), .CK(n_0_42), .Q(registers_12__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_893 (.A1(registers_17__ap[10]), .A2(n_1_0_1271), .B1( + n_1_0_1260), .B2(registers_12__ap[10]), .ZN(n_1_0_850)); + SDFF_X1_LVT \registers_reg[15][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_15__ap[10]), .CK(n_0_45), .Q(registers_15__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[5][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_5__ap[10]), .CK(n_0_35), .Q(registers_5__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_892 (.A1(registers_15__ap[10]), .A2(n_1_0_1286), .B1( + n_1_0_1273), .B2(registers_5__ap[10]), .ZN(n_1_0_849)); + NAND3_X1_LVT i_1_0_891 (.A1(n_1_0_851), .A2(n_1_0_850), .A3(n_1_0_849), + .ZN(n_1_0_848)); + SDFF_X1_LVT \registers_reg[22][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_22__ap[10]), .CK(n_0_52), .Q(registers_22__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[16][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_16__ap[10]), .CK(n_0_46), .Q(registers_16__ap[10]), .QN()); + AOI221_X1_LVT i_1_0_890 (.A(n_1_0_848), .B1(n_1_0_1294), .B2( + registers_22__ap[10]), .C1(registers_16__ap[10]), .C2(n_1_0_1267), + .ZN(n_1_0_847)); + SDFF_X1_LVT \registers_reg[9][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_9__ap[10]), .CK(n_0_39), .Q(registers_9__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[1][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_1__ap[10]), .CK(n_0_0), .Q(registers_1__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_889 (.A1(registers_9__ap[10]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[10]), .ZN(n_1_0_846)); + SDFF_X1_LVT \registers_reg[6][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_6__ap[10]), .CK(n_0_36), .Q(registers_6__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[14][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_14__ap[10]), .CK(n_0_44), .Q(registers_14__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_888 (.A1(registers_6__ap[10]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[10]), .ZN(n_1_0_845)); + SDFF_X1_LVT \registers_reg[19][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_19__ap[10]), .CK(n_0_49), .Q(registers_19__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[3][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_3__ap[10]), .CK(n_0_33), .Q(registers_3__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_887 (.A1(registers_19__ap[10]), .A2(n_1_0_1295), .B1( + n_1_0_1257), .B2(registers_3__ap[10]), .ZN(n_1_0_844)); + NAND3_X1_LVT i_1_0_886 (.A1(n_1_0_846), .A2(n_1_0_845), .A3(n_1_0_844), + .ZN(n_1_0_843)); + SDFF_X1_LVT \registers_reg[11][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_11__ap[10]), .CK(n_0_41), .Q(registers_11__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[2][10] (.D(registers[10]), .SE(1'b0), .SI( + registers_2__ap[10]), .CK(n_0_32), .Q(registers_2__ap[10]), .QN()); + AOI221_X1_LVT i_1_0_885 (.A(n_1_0_843), .B1(n_1_0_1270), .B2( + registers_11__ap[10]), .C1(registers_2__ap[10]), .C2(n_1_0_1268), .ZN( + n_1_0_842)); + NAND3_X1_LVT i_1_0_884 (.A1(n_1_0_852), .A2(n_1_0_847), .A3(n_1_0_842), + .ZN(RRs1[10])); + AND2_X1_LVT i_0_0_9 (.A1(n_0_0_16), .A2(WRd[9]), .ZN(registers[9])); + SDFF_X1_LVT \registers_reg[13][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_13__ap[9]), .CK(n_0_43), .Q(registers_13__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[21][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_21__ap[9]), .CK(n_0_51), .Q(registers_21__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_880 (.A1(registers_13__ap[9]), .A2(n_1_0_1277), .B1( + n_1_0_1259), .B2(registers_21__ap[9]), .ZN(n_1_0_838)); + SDFF_X1_LVT \registers_reg[29][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_29__ap[9]), .CK(n_0_59), .Q(registers_29__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[23][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_23__ap[9]), .CK(n_0_53), .Q(registers_23__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_883 (.A1(registers_29__ap[9]), .A2(n_1_0_1276), .B1( + n_1_0_1264), .B2(registers_23__ap[9]), .ZN(n_1_0_841)); + SDFF_X1_LVT \registers_reg[24][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_24__ap[9]), .CK(n_0_54), .Q(registers_24__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[20][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_20__ap[9]), .CK(n_0_50), .Q(registers_20__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_879 (.A1(registers_24__ap[9]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[9]), .ZN(n_1_0_837)); + SDFF_X1_LVT \registers_reg[7][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_7__ap[9]), .CK(n_0_37), .Q(registers_7__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[3][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_3__ap[9]), .CK(n_0_33), .Q(registers_3__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_882 (.A1(registers_7__ap[9]), .A2(n_1_0_1263), .B1( + n_1_0_1257), .B2(registers_3__ap[9]), .ZN(n_1_0_840)); + INV_X1_LVT i_1_0_881 (.A(n_1_0_840), .ZN(n_1_0_839)); + SDFF_X1_LVT \registers_reg[31][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_31__ap[9]), .CK(n_0_61), .Q(registers_31__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[4][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_4__ap[9]), .CK(n_0_34), .Q(registers_4__ap[9]), .QN()); + AOI221_X1_LVT i_1_0_878 (.A(n_1_0_839), .B1(n_1_0_1266), .B2( + registers_31__ap[9]), .C1(registers_4__ap[9]), .C2(n_1_0_1278), .ZN( + n_1_0_836)); + SDFF_X1_LVT \registers_reg[10][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_10__ap[9]), .CK(n_0_40), .Q(registers_10__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[26][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_26__ap[9]), .CK(n_0_56), .Q(registers_26__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[25][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_25__ap[9]), .CK(n_0_55), .Q(registers_25__ap[9]), .QN()); + AOI222_X1_LVT i_1_0_877 (.A1(registers_10__ap[9]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[9]), .C1(registers_25__ap[9]), .C2( + n_1_0_1269), .ZN(n_1_0_835)); + NAND4_X1_LVT i_1_0_876 (.A1(n_1_0_841), .A2(n_1_0_837), .A3(n_1_0_836), + .A4(n_1_0_835), .ZN(n_1_0_834)); + SDFF_X1_LVT \registers_reg[8][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_8__ap[9]), .CK(n_0_38), .Q(registers_8__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[28][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_28__ap[9]), .CK(n_0_58), .Q(registers_28__ap[9]), .QN()); + AOI221_X1_LVT i_1_0_875 (.A(n_1_0_834), .B1(n_1_0_1282), .B2( + registers_8__ap[9]), .C1(registers_28__ap[9]), .C2(n_1_0_1283), .ZN( + n_1_0_833)); + SDFF_X1_LVT \registers_reg[18][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_18__ap[9]), .CK(n_0_48), .Q(registers_18__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[30][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_30__ap[9]), .CK(n_0_60), .Q(registers_30__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_874 (.A1(registers_18__ap[9]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[9]), .ZN(n_1_0_832)); + SDFF_X1_LVT \registers_reg[17][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_17__ap[9]), .CK(n_0_47), .Q(registers_17__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[12][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_12__ap[9]), .CK(n_0_42), .Q(registers_12__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_873 (.A1(registers_17__ap[9]), .A2(n_1_0_1271), .B1( + n_1_0_1260), .B2(registers_12__ap[9]), .ZN(n_1_0_831)); + SDFF_X1_LVT \registers_reg[15][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_15__ap[9]), .CK(n_0_45), .Q(registers_15__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[5][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_5__ap[9]), .CK(n_0_35), .Q(registers_5__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_872 (.A1(registers_15__ap[9]), .A2(n_1_0_1286), .B1( + n_1_0_1273), .B2(registers_5__ap[9]), .ZN(n_1_0_830)); + NAND3_X1_LVT i_1_0_871 (.A1(n_1_0_832), .A2(n_1_0_831), .A3(n_1_0_830), + .ZN(n_1_0_829)); + SDFF_X1_LVT \registers_reg[22][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_22__ap[9]), .CK(n_0_52), .Q(registers_22__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[16][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_16__ap[9]), .CK(n_0_46), .Q(registers_16__ap[9]), .QN()); + AOI221_X1_LVT i_1_0_870 (.A(n_1_0_829), .B1(n_1_0_1294), .B2( + registers_22__ap[9]), .C1(registers_16__ap[9]), .C2(n_1_0_1267), .ZN( + n_1_0_828)); + SDFF_X1_LVT \registers_reg[9][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_9__ap[9]), .CK(n_0_39), .Q(registers_9__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[1][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_1__ap[9]), .CK(n_0_0), .Q(registers_1__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_869 (.A1(registers_9__ap[9]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[9]), .ZN(n_1_0_827)); + SDFF_X1_LVT \registers_reg[6][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_6__ap[9]), .CK(n_0_36), .Q(registers_6__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[14][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_14__ap[9]), .CK(n_0_44), .Q(registers_14__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_868 (.A1(registers_6__ap[9]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[9]), .ZN(n_1_0_826)); + SDFF_X1_LVT \registers_reg[19][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_19__ap[9]), .CK(n_0_49), .Q(registers_19__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[2][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_2__ap[9]), .CK(n_0_32), .Q(registers_2__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_867 (.A1(registers_19__ap[9]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[9]), .ZN(n_1_0_825)); + NAND3_X1_LVT i_1_0_866 (.A1(n_1_0_827), .A2(n_1_0_826), .A3(n_1_0_825), + .ZN(n_1_0_824)); + SDFF_X1_LVT \registers_reg[11][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_11__ap[9]), .CK(n_0_41), .Q(registers_11__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[27][9] (.D(registers[9]), .SE(1'b0), .SI( + registers_27__ap[9]), .CK(n_0_57), .Q(registers_27__ap[9]), .QN()); + AOI221_X1_LVT i_1_0_865 (.A(n_1_0_824), .B1(n_1_0_1270), .B2( + registers_11__ap[9]), .C1(registers_27__ap[9]), .C2(n_1_0_1279), .ZN( + n_1_0_823)); + NAND4_X1_LVT i_1_0_864 (.A1(n_1_0_838), .A2(n_1_0_833), .A3(n_1_0_828), + .A4(n_1_0_823), .ZN(RRs1[9])); + AND2_X1_LVT i_0_0_8 (.A1(n_0_0_16), .A2(WRd[8]), .ZN(registers[8])); + SDFF_X1_LVT \registers_reg[13][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_13__ap[8]), .CK(n_0_43), .Q(registers_13__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[21][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_21__ap[8]), .CK(n_0_51), .Q(registers_21__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_860 (.A1(registers_13__ap[8]), .A2(n_1_0_1277), .B1( + n_1_0_1259), .B2(registers_21__ap[8]), .ZN(n_1_0_819)); + SDFF_X1_LVT \registers_reg[29][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_29__ap[8]), .CK(n_0_59), .Q(registers_29__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[23][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_23__ap[8]), .CK(n_0_53), .Q(registers_23__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_863 (.A1(registers_29__ap[8]), .A2(n_1_0_1276), .B1( + n_1_0_1264), .B2(registers_23__ap[8]), .ZN(n_1_0_822)); + SDFF_X1_LVT \registers_reg[24][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_24__ap[8]), .CK(n_0_54), .Q(registers_24__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[20][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_20__ap[8]), .CK(n_0_50), .Q(registers_20__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_859 (.A1(registers_24__ap[8]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[8]), .ZN(n_1_0_818)); + SDFF_X1_LVT \registers_reg[7][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_7__ap[8]), .CK(n_0_37), .Q(registers_7__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[3][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_3__ap[8]), .CK(n_0_33), .Q(registers_3__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_862 (.A1(registers_7__ap[8]), .A2(n_1_0_1263), .B1( + n_1_0_1257), .B2(registers_3__ap[8]), .ZN(n_1_0_821)); + INV_X1_LVT i_1_0_861 (.A(n_1_0_821), .ZN(n_1_0_820)); + SDFF_X1_LVT \registers_reg[31][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_31__ap[8]), .CK(n_0_61), .Q(registers_31__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[4][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_4__ap[8]), .CK(n_0_34), .Q(registers_4__ap[8]), .QN()); + AOI221_X1_LVT i_1_0_858 (.A(n_1_0_820), .B1(n_1_0_1266), .B2( + registers_31__ap[8]), .C1(registers_4__ap[8]), .C2(n_1_0_1278), .ZN( + n_1_0_817)); + SDFF_X1_LVT \registers_reg[10][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_10__ap[8]), .CK(n_0_40), .Q(registers_10__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[26][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_26__ap[8]), .CK(n_0_56), .Q(registers_26__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[25][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_25__ap[8]), .CK(n_0_55), .Q(registers_25__ap[8]), .QN()); + AOI222_X1_LVT i_1_0_857 (.A1(registers_10__ap[8]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[8]), .C1(registers_25__ap[8]), .C2( + n_1_0_1269), .ZN(n_1_0_816)); + NAND4_X1_LVT i_1_0_856 (.A1(n_1_0_822), .A2(n_1_0_818), .A3(n_1_0_817), + .A4(n_1_0_816), .ZN(n_1_0_815)); + SDFF_X1_LVT \registers_reg[8][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_8__ap[8]), .CK(n_0_38), .Q(registers_8__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[28][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_28__ap[8]), .CK(n_0_58), .Q(registers_28__ap[8]), .QN()); + AOI221_X1_LVT i_1_0_855 (.A(n_1_0_815), .B1(n_1_0_1282), .B2( + registers_8__ap[8]), .C1(registers_28__ap[8]), .C2(n_1_0_1283), .ZN( + n_1_0_814)); + SDFF_X1_LVT \registers_reg[18][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_18__ap[8]), .CK(n_0_48), .Q(registers_18__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[30][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_30__ap[8]), .CK(n_0_60), .Q(registers_30__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_854 (.A1(registers_18__ap[8]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[8]), .ZN(n_1_0_813)); + SDFF_X1_LVT \registers_reg[17][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_17__ap[8]), .CK(n_0_47), .Q(registers_17__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[12][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_12__ap[8]), .CK(n_0_42), .Q(registers_12__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_853 (.A1(registers_17__ap[8]), .A2(n_1_0_1271), .B1( + n_1_0_1260), .B2(registers_12__ap[8]), .ZN(n_1_0_812)); + SDFF_X1_LVT \registers_reg[15][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_15__ap[8]), .CK(n_0_45), .Q(registers_15__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[5][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_5__ap[8]), .CK(n_0_35), .Q(registers_5__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_852 (.A1(registers_15__ap[8]), .A2(n_1_0_1286), .B1( + n_1_0_1273), .B2(registers_5__ap[8]), .ZN(n_1_0_811)); + NAND3_X1_LVT i_1_0_851 (.A1(n_1_0_813), .A2(n_1_0_812), .A3(n_1_0_811), + .ZN(n_1_0_810)); + SDFF_X1_LVT \registers_reg[22][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_22__ap[8]), .CK(n_0_52), .Q(registers_22__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[16][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_16__ap[8]), .CK(n_0_46), .Q(registers_16__ap[8]), .QN()); + AOI221_X1_LVT i_1_0_850 (.A(n_1_0_810), .B1(n_1_0_1294), .B2( + registers_22__ap[8]), .C1(registers_16__ap[8]), .C2(n_1_0_1267), .ZN( + n_1_0_809)); + SDFF_X1_LVT \registers_reg[9][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_9__ap[8]), .CK(n_0_39), .Q(registers_9__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[1][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_1__ap[8]), .CK(n_0_0), .Q(registers_1__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_849 (.A1(registers_9__ap[8]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[8]), .ZN(n_1_0_808)); + SDFF_X1_LVT \registers_reg[6][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_6__ap[8]), .CK(n_0_36), .Q(registers_6__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[14][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_14__ap[8]), .CK(n_0_44), .Q(registers_14__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_848 (.A1(registers_6__ap[8]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[8]), .ZN(n_1_0_807)); + SDFF_X1_LVT \registers_reg[19][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_19__ap[8]), .CK(n_0_49), .Q(registers_19__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[2][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_2__ap[8]), .CK(n_0_32), .Q(registers_2__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_847 (.A1(registers_19__ap[8]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[8]), .ZN(n_1_0_806)); + NAND3_X1_LVT i_1_0_846 (.A1(n_1_0_808), .A2(n_1_0_807), .A3(n_1_0_806), + .ZN(n_1_0_805)); + SDFF_X1_LVT \registers_reg[11][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_11__ap[8]), .CK(n_0_41), .Q(registers_11__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[27][8] (.D(registers[8]), .SE(1'b0), .SI( + registers_27__ap[8]), .CK(n_0_57), .Q(registers_27__ap[8]), .QN()); + AOI221_X1_LVT i_1_0_845 (.A(n_1_0_805), .B1(n_1_0_1270), .B2( + registers_11__ap[8]), .C1(registers_27__ap[8]), .C2(n_1_0_1279), .ZN( + n_1_0_804)); + NAND4_X1_LVT i_1_0_844 (.A1(n_1_0_819), .A2(n_1_0_814), .A3(n_1_0_809), + .A4(n_1_0_804), .ZN(RRs1[8])); + AND2_X1_LVT i_0_0_7 (.A1(n_0_0_16), .A2(WRd[7]), .ZN(registers[7])); + SDFF_X1_LVT \registers_reg[13][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_13__ap[7]), .CK(n_0_43), .Q(registers_13__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[21][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_21__ap[7]), .CK(n_0_51), .Q(registers_21__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_843 (.A1(registers_13__ap[7]), .A2(n_1_0_1277), .B1( + n_1_0_1259), .B2(registers_21__ap[7]), .ZN(n_1_0_803)); + SDFF_X1_LVT \registers_reg[18][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_18__ap[7]), .CK(n_0_48), .Q(registers_18__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[10][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_10__ap[7]), .CK(n_0_40), .Q(registers_10__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[25][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_25__ap[7]), .CK(n_0_55), .Q(registers_25__ap[7]), .QN()); + AOI222_X1_LVT i_1_0_842 (.A1(registers_18__ap[7]), .A2(n_1_0_1297), .B1( + n_1_0_1287), .B2(registers_10__ap[7]), .C1(registers_25__ap[7]), .C2( + n_1_0_1269), .ZN(n_1_0_802)); + SDFF_X1_LVT \registers_reg[28][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_28__ap[7]), .CK(n_0_58), .Q(registers_28__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[8][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_8__ap[7]), .CK(n_0_38), .Q(registers_8__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_841 (.A1(registers_28__ap[7]), .A2(n_1_0_1283), .B1( + n_1_0_1282), .B2(registers_8__ap[7]), .ZN(n_1_0_801)); + SDFF_X1_LVT \registers_reg[24][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_24__ap[7]), .CK(n_0_54), .Q(registers_24__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[20][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_20__ap[7]), .CK(n_0_50), .Q(registers_20__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_840 (.A1(registers_24__ap[7]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[7]), .ZN(n_1_0_800)); + SDFF_X1_LVT \registers_reg[31][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_31__ap[7]), .CK(n_0_61), .Q(registers_31__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[7][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_7__ap[7]), .CK(n_0_37), .Q(registers_7__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_839 (.A1(registers_31__ap[7]), .A2(n_1_0_1266), .B1( + n_1_0_1263), .B2(registers_7__ap[7]), .ZN(n_1_0_799)); + SDFF_X1_LVT \registers_reg[17][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_17__ap[7]), .CK(n_0_47), .Q(registers_17__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[11][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_11__ap[7]), .CK(n_0_41), .Q(registers_11__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_838 (.A1(registers_17__ap[7]), .A2(n_1_0_1271), .B1( + n_1_0_1270), .B2(registers_11__ap[7]), .ZN(n_1_0_798)); + SDFF_X1_LVT \registers_reg[27][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_27__ap[7]), .CK(n_0_57), .Q(registers_27__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[29][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_29__ap[7]), .CK(n_0_59), .Q(registers_29__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_837 (.A1(registers_27__ap[7]), .A2(n_1_0_1279), .B1( + n_1_0_1276), .B2(registers_29__ap[7]), .ZN(n_1_0_797)); + NAND4_X1_LVT i_1_0_836 (.A1(n_1_0_800), .A2(n_1_0_799), .A3(n_1_0_798), + .A4(n_1_0_797), .ZN(n_1_0_796)); + SDFF_X1_LVT \registers_reg[26][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_26__ap[7]), .CK(n_0_56), .Q(registers_26__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[30][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_30__ap[7]), .CK(n_0_60), .Q(registers_30__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_835 (.A1(registers_26__ap[7]), .A2(n_1_0_1285), .B1( + n_1_0_1272), .B2(registers_30__ap[7]), .ZN(n_1_0_795)); + SDFF_X1_LVT \registers_reg[4][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_4__ap[7]), .CK(n_0_34), .Q(registers_4__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[12][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_12__ap[7]), .CK(n_0_42), .Q(registers_12__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_834 (.A1(registers_4__ap[7]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[7]), .ZN(n_1_0_794)); + SDFF_X1_LVT \registers_reg[15][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_15__ap[7]), .CK(n_0_45), .Q(registers_15__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[16][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_16__ap[7]), .CK(n_0_46), .Q(registers_16__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_833 (.A1(registers_15__ap[7]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[7]), .ZN(n_1_0_793)); + SDFF_X1_LVT \registers_reg[22][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_22__ap[7]), .CK(n_0_52), .Q(registers_22__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[5][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_5__ap[7]), .CK(n_0_35), .Q(registers_5__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_832 (.A1(registers_22__ap[7]), .A2(n_1_0_1294), .B1( + n_1_0_1273), .B2(registers_5__ap[7]), .ZN(n_1_0_792)); + NAND4_X1_LVT i_1_0_831 (.A1(n_1_0_795), .A2(n_1_0_794), .A3(n_1_0_793), + .A4(n_1_0_792), .ZN(n_1_0_791)); + SDFF_X1_LVT \registers_reg[19][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_19__ap[7]), .CK(n_0_49), .Q(registers_19__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[3][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_3__ap[7]), .CK(n_0_33), .Q(registers_3__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_830 (.A1(registers_19__ap[7]), .A2(n_1_0_1295), .B1( + n_1_0_1257), .B2(registers_3__ap[7]), .ZN(n_1_0_790)); + SDFF_X1_LVT \registers_reg[9][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_9__ap[7]), .CK(n_0_39), .Q(registers_9__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[1][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_1__ap[7]), .CK(n_0_0), .Q(registers_1__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_829 (.A1(registers_9__ap[7]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[7]), .ZN(n_1_0_789)); + SDFF_X1_LVT \registers_reg[6][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_6__ap[7]), .CK(n_0_36), .Q(registers_6__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[14][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_14__ap[7]), .CK(n_0_44), .Q(registers_14__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_828 (.A1(registers_6__ap[7]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[7]), .ZN(n_1_0_788)); + SDFF_X1_LVT \registers_reg[2][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_2__ap[7]), .CK(n_0_32), .Q(registers_2__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[23][7] (.D(registers[7]), .SE(1'b0), .SI( + registers_23__ap[7]), .CK(n_0_53), .Q(registers_23__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_827 (.A1(registers_2__ap[7]), .A2(n_1_0_1268), .B1( + n_1_0_1264), .B2(registers_23__ap[7]), .ZN(n_1_0_787)); + NAND4_X1_LVT i_1_0_826 (.A1(n_1_0_790), .A2(n_1_0_789), .A3(n_1_0_788), + .A4(n_1_0_787), .ZN(n_1_0_786)); + NOR3_X1_LVT i_1_0_825 (.A1(n_1_0_796), .A2(n_1_0_791), .A3(n_1_0_786), + .ZN(n_1_0_785)); + NAND4_X1_LVT i_1_0_824 (.A1(n_1_0_803), .A2(n_1_0_802), .A3(n_1_0_801), + .A4(n_1_0_785), .ZN(RRs1[7])); + AND2_X1_LVT i_0_0_6 (.A1(n_0_0_16), .A2(WRd[6]), .ZN(registers[6])); + SDFF_X1_LVT \registers_reg[28][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_28__ap[6]), .CK(n_0_58), .Q(registers_28__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[17][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_17__ap[6]), .CK(n_0_47), .Q(registers_17__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_823 (.A1(registers_28__ap[6]), .A2(n_1_0_1283), .B1( + n_1_0_1271), .B2(registers_17__ap[6]), .ZN(n_1_0_784)); + SDFF_X1_LVT \registers_reg[18][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_18__ap[6]), .CK(n_0_48), .Q(registers_18__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[10][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_10__ap[6]), .CK(n_0_40), .Q(registers_10__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[8][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_8__ap[6]), .CK(n_0_38), .Q(registers_8__ap[6]), .QN()); + AOI222_X1_LVT i_1_0_822 (.A1(registers_18__ap[6]), .A2(n_1_0_1297), .B1( + n_1_0_1287), .B2(registers_10__ap[6]), .C1(registers_8__ap[6]), .C2( + n_1_0_1282), .ZN(n_1_0_783)); + SDFF_X1_LVT \registers_reg[9][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_9__ap[6]), .CK(n_0_39), .Q(registers_9__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[29][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_29__ap[6]), .CK(n_0_59), .Q(registers_29__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_821 (.A1(registers_9__ap[6]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[6]), .ZN(n_1_0_782)); + SDFF_X1_LVT \registers_reg[6][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_6__ap[6]), .CK(n_0_36), .Q(registers_6__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[1][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_1__ap[6]), .CK(n_0_0), .Q(registers_1__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_820 (.A1(registers_6__ap[6]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[6]), .ZN(n_1_0_781)); + SDFF_X1_LVT \registers_reg[15][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_15__ap[6]), .CK(n_0_45), .Q(registers_15__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[27][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_27__ap[6]), .CK(n_0_57), .Q(registers_27__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_819 (.A1(registers_15__ap[6]), .A2(n_1_0_1286), .B1( + n_1_0_1279), .B2(registers_27__ap[6]), .ZN(n_1_0_780)); + SDFF_X1_LVT \registers_reg[11][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_11__ap[6]), .CK(n_0_41), .Q(registers_11__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[16][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_16__ap[6]), .CK(n_0_46), .Q(registers_16__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_818 (.A1(registers_11__ap[6]), .A2(n_1_0_1270), .B1( + n_1_0_1267), .B2(registers_16__ap[6]), .ZN(n_1_0_779)); + SDFF_X1_LVT \registers_reg[5][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_5__ap[6]), .CK(n_0_35), .Q(registers_5__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[31][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_31__ap[6]), .CK(n_0_61), .Q(registers_31__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_817 (.A1(registers_5__ap[6]), .A2(n_1_0_1273), .B1( + n_1_0_1266), .B2(registers_31__ap[6]), .ZN(n_1_0_778)); + NAND4_X1_LVT i_1_0_816 (.A1(n_1_0_781), .A2(n_1_0_780), .A3(n_1_0_779), + .A4(n_1_0_778), .ZN(n_1_0_777)); + SDFF_X1_LVT \registers_reg[26][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_26__ap[6]), .CK(n_0_56), .Q(registers_26__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[30][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_30__ap[6]), .CK(n_0_60), .Q(registers_30__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_815 (.A1(registers_26__ap[6]), .A2(n_1_0_1285), .B1( + n_1_0_1272), .B2(registers_30__ap[6]), .ZN(n_1_0_776)); + SDFF_X1_LVT \registers_reg[20][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_20__ap[6]), .CK(n_0_50), .Q(registers_20__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[4][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_4__ap[6]), .CK(n_0_34), .Q(registers_4__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_814 (.A1(registers_20__ap[6]), .A2(n_1_0_1281), .B1( + n_1_0_1278), .B2(registers_4__ap[6]), .ZN(n_1_0_775)); + SDFF_X1_LVT \registers_reg[22][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_22__ap[6]), .CK(n_0_52), .Q(registers_22__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[21][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_21__ap[6]), .CK(n_0_51), .Q(registers_21__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_813 (.A1(registers_22__ap[6]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[6]), .ZN(n_1_0_774)); + SDFF_X1_LVT \registers_reg[24][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_24__ap[6]), .CK(n_0_54), .Q(registers_24__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[12][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_12__ap[6]), .CK(n_0_42), .Q(registers_12__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_812 (.A1(registers_24__ap[6]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[6]), .ZN(n_1_0_773)); + NAND4_X1_LVT i_1_0_811 (.A1(n_1_0_776), .A2(n_1_0_775), .A3(n_1_0_774), + .A4(n_1_0_773), .ZN(n_1_0_772)); + SDFF_X1_LVT \registers_reg[13][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_13__ap[6]), .CK(n_0_43), .Q(registers_13__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[25][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_25__ap[6]), .CK(n_0_55), .Q(registers_25__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_810 (.A1(registers_13__ap[6]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[6]), .ZN(n_1_0_771)); + SDFF_X1_LVT \registers_reg[7][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_7__ap[6]), .CK(n_0_37), .Q(registers_7__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[14][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_14__ap[6]), .CK(n_0_44), .Q(registers_14__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_809 (.A1(registers_7__ap[6]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[6]), .ZN(n_1_0_770)); + SDFF_X1_LVT \registers_reg[19][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_19__ap[6]), .CK(n_0_49), .Q(registers_19__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[3][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_3__ap[6]), .CK(n_0_33), .Q(registers_3__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_808 (.A1(registers_19__ap[6]), .A2(n_1_0_1295), .B1( + n_1_0_1257), .B2(registers_3__ap[6]), .ZN(n_1_0_769)); + SDFF_X1_LVT \registers_reg[2][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_2__ap[6]), .CK(n_0_32), .Q(registers_2__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[23][6] (.D(registers[6]), .SE(1'b0), .SI( + registers_23__ap[6]), .CK(n_0_53), .Q(registers_23__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_807 (.A1(registers_2__ap[6]), .A2(n_1_0_1268), .B1( + n_1_0_1264), .B2(registers_23__ap[6]), .ZN(n_1_0_768)); + NAND4_X1_LVT i_1_0_806 (.A1(n_1_0_771), .A2(n_1_0_770), .A3(n_1_0_769), + .A4(n_1_0_768), .ZN(n_1_0_767)); + NOR3_X1_LVT i_1_0_805 (.A1(n_1_0_777), .A2(n_1_0_772), .A3(n_1_0_767), + .ZN(n_1_0_766)); + NAND4_X1_LVT i_1_0_804 (.A1(n_1_0_784), .A2(n_1_0_783), .A3(n_1_0_782), + .A4(n_1_0_766), .ZN(RRs1[6])); + AND2_X1_LVT i_0_0_5 (.A1(n_0_0_16), .A2(WRd[5]), .ZN(registers[5])); + SDFF_X1_LVT \registers_reg[28][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_28__ap[5]), .CK(n_0_58), .Q(registers_28__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[4][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_4__ap[5]), .CK(n_0_34), .Q(registers_4__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_803 (.A1(registers_28__ap[5]), .A2(n_1_0_1283), .B1( + n_1_0_1278), .B2(registers_4__ap[5]), .ZN(n_1_0_765)); + SDFF_X1_LVT \registers_reg[10][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_10__ap[5]), .CK(n_0_40), .Q(registers_10__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[26][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_26__ap[5]), .CK(n_0_56), .Q(registers_26__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[8][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_8__ap[5]), .CK(n_0_38), .Q(registers_8__ap[5]), .QN()); + AOI222_X1_LVT i_1_0_802 (.A1(registers_10__ap[5]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[5]), .C1(registers_8__ap[5]), .C2( + n_1_0_1282), .ZN(n_1_0_764)); + SDFF_X1_LVT \registers_reg[9][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_9__ap[5]), .CK(n_0_39), .Q(registers_9__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[29][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_29__ap[5]), .CK(n_0_59), .Q(registers_29__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_801 (.A1(registers_9__ap[5]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[5]), .ZN(n_1_0_763)); + SDFF_X1_LVT \registers_reg[6][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_6__ap[5]), .CK(n_0_36), .Q(registers_6__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[1][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_1__ap[5]), .CK(n_0_0), .Q(registers_1__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_800 (.A1(registers_6__ap[5]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[5]), .ZN(n_1_0_762)); + SDFF_X1_LVT \registers_reg[16][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_16__ap[5]), .CK(n_0_46), .Q(registers_16__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[3][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_3__ap[5]), .CK(n_0_33), .Q(registers_3__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_799 (.A1(registers_16__ap[5]), .A2(n_1_0_1267), .B1( + n_1_0_1257), .B2(registers_3__ap[5]), .ZN(n_1_0_761)); + SDFF_X1_LVT \registers_reg[5][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_5__ap[5]), .CK(n_0_35), .Q(registers_5__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[31][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_31__ap[5]), .CK(n_0_61), .Q(registers_31__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_798 (.A1(registers_5__ap[5]), .A2(n_1_0_1273), .B1( + n_1_0_1266), .B2(registers_31__ap[5]), .ZN(n_1_0_760)); + SDFF_X1_LVT \registers_reg[15][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_15__ap[5]), .CK(n_0_45), .Q(registers_15__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[23][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_23__ap[5]), .CK(n_0_53), .Q(registers_23__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_797 (.A1(registers_15__ap[5]), .A2(n_1_0_1286), .B1( + n_1_0_1264), .B2(registers_23__ap[5]), .ZN(n_1_0_759)); + NAND4_X1_LVT i_1_0_796 (.A1(n_1_0_762), .A2(n_1_0_761), .A3(n_1_0_760), + .A4(n_1_0_759), .ZN(n_1_0_758)); + SDFF_X1_LVT \registers_reg[18][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_18__ap[5]), .CK(n_0_48), .Q(registers_18__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[30][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_30__ap[5]), .CK(n_0_60), .Q(registers_30__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_795 (.A1(registers_18__ap[5]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[5]), .ZN(n_1_0_757)); + SDFF_X1_LVT \registers_reg[24][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_24__ap[5]), .CK(n_0_54), .Q(registers_24__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[12][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_12__ap[5]), .CK(n_0_42), .Q(registers_12__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_794 (.A1(registers_24__ap[5]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[5]), .ZN(n_1_0_756)); + SDFF_X1_LVT \registers_reg[22][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_22__ap[5]), .CK(n_0_52), .Q(registers_22__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[21][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_21__ap[5]), .CK(n_0_51), .Q(registers_21__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_793 (.A1(registers_22__ap[5]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[5]), .ZN(n_1_0_755)); + SDFF_X1_LVT \registers_reg[20][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_20__ap[5]), .CK(n_0_50), .Q(registers_20__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[17][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_17__ap[5]), .CK(n_0_47), .Q(registers_17__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_792 (.A1(registers_20__ap[5]), .A2(n_1_0_1281), .B1( + n_1_0_1271), .B2(registers_17__ap[5]), .ZN(n_1_0_754)); + NAND4_X1_LVT i_1_0_791 (.A1(n_1_0_757), .A2(n_1_0_756), .A3(n_1_0_755), + .A4(n_1_0_754), .ZN(n_1_0_753)); + SDFF_X1_LVT \registers_reg[13][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_13__ap[5]), .CK(n_0_43), .Q(registers_13__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[25][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_25__ap[5]), .CK(n_0_55), .Q(registers_25__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_790 (.A1(registers_13__ap[5]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[5]), .ZN(n_1_0_752)); + SDFF_X1_LVT \registers_reg[19][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_19__ap[5]), .CK(n_0_49), .Q(registers_19__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[2][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_2__ap[5]), .CK(n_0_32), .Q(registers_2__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_789 (.A1(registers_19__ap[5]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[5]), .ZN(n_1_0_751)); + SDFF_X1_LVT \registers_reg[7][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_7__ap[5]), .CK(n_0_37), .Q(registers_7__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[14][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_14__ap[5]), .CK(n_0_44), .Q(registers_14__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_788 (.A1(registers_7__ap[5]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[5]), .ZN(n_1_0_750)); + SDFF_X1_LVT \registers_reg[27][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_27__ap[5]), .CK(n_0_57), .Q(registers_27__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[11][5] (.D(registers[5]), .SE(1'b0), .SI( + registers_11__ap[5]), .CK(n_0_41), .Q(registers_11__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_787 (.A1(registers_27__ap[5]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[5]), .ZN(n_1_0_749)); + NAND4_X1_LVT i_1_0_786 (.A1(n_1_0_752), .A2(n_1_0_751), .A3(n_1_0_750), + .A4(n_1_0_749), .ZN(n_1_0_748)); + NOR3_X1_LVT i_1_0_785 (.A1(n_1_0_758), .A2(n_1_0_753), .A3(n_1_0_748), + .ZN(n_1_0_747)); + NAND4_X1_LVT i_1_0_784 (.A1(n_1_0_765), .A2(n_1_0_764), .A3(n_1_0_763), + .A4(n_1_0_747), .ZN(RRs1[5])); + AND2_X1_LVT i_0_0_4 (.A1(n_0_0_16), .A2(WRd[4]), .ZN(registers[4])); + SDFF_X1_LVT \registers_reg[10][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_10__ap[4]), .CK(n_0_40), .Q(registers_10__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[21][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_21__ap[4]), .CK(n_0_51), .Q(registers_21__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_783 (.A1(registers_10__ap[4]), .A2(n_1_0_1287), .B1( + n_1_0_1259), .B2(registers_21__ap[4]), .ZN(n_1_0_746)); + SDFF_X1_LVT \registers_reg[9][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_9__ap[4]), .CK(n_0_39), .Q(registers_9__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[1][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_1__ap[4]), .CK(n_0_0), .Q(registers_1__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_778 (.A1(registers_9__ap[4]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[4]), .ZN(n_1_0_741)); + SDFF_X1_LVT \registers_reg[18][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_18__ap[4]), .CK(n_0_48), .Q(registers_18__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[8][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_8__ap[4]), .CK(n_0_38), .Q(registers_8__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_777 (.A1(registers_18__ap[4]), .A2(n_1_0_1297), .B1( + n_1_0_1282), .B2(registers_8__ap[4]), .ZN(n_1_0_740)); + NAND3_X1_LVT i_1_0_775 (.A1(n_1_0_746), .A2(n_1_0_741), .A3(n_1_0_740), + .ZN(n_1_0_738)); + SDFF_X1_LVT \registers_reg[22][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_22__ap[4]), .CK(n_0_52), .Q(registers_22__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[23][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_23__ap[4]), .CK(n_0_53), .Q(registers_23__ap[4]), .QN()); + AOI221_X1_LVT i_1_0_774 (.A(n_1_0_738), .B1(n_1_0_1294), .B2( + registers_22__ap[4]), .C1(registers_23__ap[4]), .C2(n_1_0_1264), .ZN( + n_1_0_737)); + SDFF_X1_LVT \registers_reg[28][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_28__ap[4]), .CK(n_0_58), .Q(registers_28__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[20][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_20__ap[4]), .CK(n_0_50), .Q(registers_20__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_782 (.A1(registers_28__ap[4]), .A2(n_1_0_1283), .B1( + n_1_0_1281), .B2(registers_20__ap[4]), .ZN(n_1_0_745)); + SDFF_X1_LVT \registers_reg[19][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_19__ap[4]), .CK(n_0_49), .Q(registers_19__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[13][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_13__ap[4]), .CK(n_0_43), .Q(registers_13__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_780 (.A1(registers_19__ap[4]), .A2(n_1_0_1295), .B1( + n_1_0_1277), .B2(registers_13__ap[4]), .ZN(n_1_0_743)); + SDFF_X1_LVT \registers_reg[26][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_26__ap[4]), .CK(n_0_56), .Q(registers_26__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[3][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_3__ap[4]), .CK(n_0_33), .Q(registers_3__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_776 (.A1(registers_26__ap[4]), .A2(n_1_0_1285), .B1( + n_1_0_1257), .B2(registers_3__ap[4]), .ZN(n_1_0_739)); + NAND3_X1_LVT i_1_0_773 (.A1(n_1_0_745), .A2(n_1_0_743), .A3(n_1_0_739), + .ZN(n_1_0_736)); + SDFF_X1_LVT \registers_reg[30][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_30__ap[4]), .CK(n_0_60), .Q(registers_30__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[31][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_31__ap[4]), .CK(n_0_61), .Q(registers_31__ap[4]), .QN()); + AOI221_X1_LVT i_1_0_772 (.A(n_1_0_736), .B1(n_1_0_1272), .B2( + registers_30__ap[4]), .C1(registers_31__ap[4]), .C2(n_1_0_1266), .ZN( + n_1_0_735)); + SDFF_X1_LVT \registers_reg[24][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_24__ap[4]), .CK(n_0_54), .Q(registers_24__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[12][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_12__ap[4]), .CK(n_0_42), .Q(registers_12__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_781 (.A1(registers_24__ap[4]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[4]), .ZN(n_1_0_744)); + SDFF_X1_LVT \registers_reg[27][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_27__ap[4]), .CK(n_0_57), .Q(registers_27__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[11][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_11__ap[4]), .CK(n_0_41), .Q(registers_11__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_779 (.A1(registers_27__ap[4]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[4]), .ZN(n_1_0_742)); + SDFF_X1_LVT \registers_reg[17][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_17__ap[4]), .CK(n_0_47), .Q(registers_17__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[7][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_7__ap[4]), .CK(n_0_37), .Q(registers_7__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[14][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_14__ap[4]), .CK(n_0_44), .Q(registers_14__ap[4]), .QN()); + AOI222_X1_LVT i_1_0_771 (.A1(registers_17__ap[4]), .A2(n_1_0_1271), .B1( + n_1_0_1263), .B2(registers_7__ap[4]), .C1(n_1_0_1258), .C2( + registers_14__ap[4]), .ZN(n_1_0_734)); + SDFF_X1_LVT \registers_reg[15][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_15__ap[4]), .CK(n_0_45), .Q(registers_15__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[16][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_16__ap[4]), .CK(n_0_46), .Q(registers_16__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_770 (.A1(registers_15__ap[4]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[4]), .ZN(n_1_0_733)); + SDFF_X1_LVT \registers_reg[4][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_4__ap[4]), .CK(n_0_34), .Q(registers_4__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[25][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_25__ap[4]), .CK(n_0_55), .Q(registers_25__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_769 (.A1(registers_4__ap[4]), .A2(n_1_0_1278), .B1( + n_1_0_1269), .B2(registers_25__ap[4]), .ZN(n_1_0_732)); + SDFF_X1_LVT \registers_reg[29][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_29__ap[4]), .CK(n_0_59), .Q(registers_29__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[2][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_2__ap[4]), .CK(n_0_32), .Q(registers_2__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_768 (.A1(registers_29__ap[4]), .A2(n_1_0_1276), .B1( + n_1_0_1268), .B2(registers_2__ap[4]), .ZN(n_1_0_731)); + NAND3_X1_LVT i_1_0_767 (.A1(n_1_0_733), .A2(n_1_0_732), .A3(n_1_0_731), + .ZN(n_1_0_730)); + SDFF_X1_LVT \registers_reg[6][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_6__ap[4]), .CK(n_0_36), .Q(registers_6__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[5][4] (.D(registers[4]), .SE(1'b0), .SI( + registers_5__ap[4]), .CK(n_0_35), .Q(registers_5__ap[4]), .QN()); + AOI221_X1_LVT i_1_0_766 (.A(n_1_0_730), .B1(n_1_0_1300), .B2( + registers_6__ap[4]), .C1(registers_5__ap[4]), .C2(n_1_0_1273), .ZN( + n_1_0_729)); + AND4_X1_LVT i_1_0_765 (.A1(n_1_0_744), .A2(n_1_0_742), .A3(n_1_0_734), + .A4(n_1_0_729), .ZN(n_1_0_728)); + NAND3_X1_LVT i_1_0_764 (.A1(n_1_0_737), .A2(n_1_0_735), .A3(n_1_0_728), + .ZN(RRs1[4])); + AND2_X1_LVT i_0_0_3 (.A1(n_0_0_16), .A2(WRd[3]), .ZN(registers[3])); + SDFF_X1_LVT \registers_reg[28][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_28__ap[3]), .CK(n_0_58), .Q(registers_28__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[17][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_17__ap[3]), .CK(n_0_47), .Q(registers_17__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_763 (.A1(registers_28__ap[3]), .A2(n_1_0_1283), .B1( + n_1_0_1271), .B2(registers_17__ap[3]), .ZN(n_1_0_727)); + SDFF_X1_LVT \registers_reg[10][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_10__ap[3]), .CK(n_0_40), .Q(registers_10__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[26][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_26__ap[3]), .CK(n_0_56), .Q(registers_26__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[8][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_8__ap[3]), .CK(n_0_38), .Q(registers_8__ap[3]), .QN()); + AOI222_X1_LVT i_1_0_762 (.A1(registers_10__ap[3]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[3]), .C1(registers_8__ap[3]), .C2( + n_1_0_1282), .ZN(n_1_0_726)); + SDFF_X1_LVT \registers_reg[9][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_9__ap[3]), .CK(n_0_39), .Q(registers_9__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[29][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_29__ap[3]), .CK(n_0_59), .Q(registers_29__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_761 (.A1(registers_9__ap[3]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[3]), .ZN(n_1_0_725)); + SDFF_X1_LVT \registers_reg[6][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_6__ap[3]), .CK(n_0_36), .Q(registers_6__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[1][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_1__ap[3]), .CK(n_0_0), .Q(registers_1__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_760 (.A1(registers_6__ap[3]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[3]), .ZN(n_1_0_724)); + SDFF_X1_LVT \registers_reg[16][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_16__ap[3]), .CK(n_0_46), .Q(registers_16__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[3][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_3__ap[3]), .CK(n_0_33), .Q(registers_3__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_759 (.A1(registers_16__ap[3]), .A2(n_1_0_1267), .B1( + n_1_0_1257), .B2(registers_3__ap[3]), .ZN(n_1_0_723)); + SDFF_X1_LVT \registers_reg[5][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_5__ap[3]), .CK(n_0_35), .Q(registers_5__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[31][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_31__ap[3]), .CK(n_0_61), .Q(registers_31__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_758 (.A1(registers_5__ap[3]), .A2(n_1_0_1273), .B1( + n_1_0_1266), .B2(registers_31__ap[3]), .ZN(n_1_0_722)); + SDFF_X1_LVT \registers_reg[15][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_15__ap[3]), .CK(n_0_45), .Q(registers_15__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[23][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_23__ap[3]), .CK(n_0_53), .Q(registers_23__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_757 (.A1(registers_15__ap[3]), .A2(n_1_0_1286), .B1( + n_1_0_1264), .B2(registers_23__ap[3]), .ZN(n_1_0_721)); + NAND4_X1_LVT i_1_0_756 (.A1(n_1_0_724), .A2(n_1_0_723), .A3(n_1_0_722), + .A4(n_1_0_721), .ZN(n_1_0_720)); + SDFF_X1_LVT \registers_reg[18][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_18__ap[3]), .CK(n_0_48), .Q(registers_18__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[30][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_30__ap[3]), .CK(n_0_60), .Q(registers_30__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_755 (.A1(registers_18__ap[3]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[3]), .ZN(n_1_0_719)); + SDFF_X1_LVT \registers_reg[20][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_20__ap[3]), .CK(n_0_50), .Q(registers_20__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[4][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_4__ap[3]), .CK(n_0_34), .Q(registers_4__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_754 (.A1(registers_20__ap[3]), .A2(n_1_0_1281), .B1( + n_1_0_1278), .B2(registers_4__ap[3]), .ZN(n_1_0_718)); + SDFF_X1_LVT \registers_reg[22][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_22__ap[3]), .CK(n_0_52), .Q(registers_22__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[21][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_21__ap[3]), .CK(n_0_51), .Q(registers_21__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_753 (.A1(registers_22__ap[3]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[3]), .ZN(n_1_0_717)); + SDFF_X1_LVT \registers_reg[24][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_24__ap[3]), .CK(n_0_54), .Q(registers_24__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[12][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_12__ap[3]), .CK(n_0_42), .Q(registers_12__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_752 (.A1(registers_24__ap[3]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[3]), .ZN(n_1_0_716)); + NAND4_X1_LVT i_1_0_751 (.A1(n_1_0_719), .A2(n_1_0_718), .A3(n_1_0_717), + .A4(n_1_0_716), .ZN(n_1_0_715)); + SDFF_X1_LVT \registers_reg[13][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_13__ap[3]), .CK(n_0_43), .Q(registers_13__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[25][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_25__ap[3]), .CK(n_0_55), .Q(registers_25__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_750 (.A1(registers_13__ap[3]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[3]), .ZN(n_1_0_714)); + SDFF_X1_LVT \registers_reg[19][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_19__ap[3]), .CK(n_0_49), .Q(registers_19__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[2][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_2__ap[3]), .CK(n_0_32), .Q(registers_2__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_749 (.A1(registers_19__ap[3]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[3]), .ZN(n_1_0_713)); + SDFF_X1_LVT \registers_reg[7][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_7__ap[3]), .CK(n_0_37), .Q(registers_7__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[14][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_14__ap[3]), .CK(n_0_44), .Q(registers_14__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_748 (.A1(registers_7__ap[3]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[3]), .ZN(n_1_0_712)); + SDFF_X1_LVT \registers_reg[27][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_27__ap[3]), .CK(n_0_57), .Q(registers_27__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[11][3] (.D(registers[3]), .SE(1'b0), .SI( + registers_11__ap[3]), .CK(n_0_41), .Q(registers_11__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_747 (.A1(registers_27__ap[3]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[3]), .ZN(n_1_0_711)); + NAND4_X1_LVT i_1_0_746 (.A1(n_1_0_714), .A2(n_1_0_713), .A3(n_1_0_712), + .A4(n_1_0_711), .ZN(n_1_0_710)); + NOR3_X1_LVT i_1_0_745 (.A1(n_1_0_720), .A2(n_1_0_715), .A3(n_1_0_710), + .ZN(n_1_0_709)); + NAND4_X1_LVT i_1_0_744 (.A1(n_1_0_727), .A2(n_1_0_726), .A3(n_1_0_725), + .A4(n_1_0_709), .ZN(RRs1[3])); + AND2_X1_LVT i_0_0_2 (.A1(n_0_0_16), .A2(WRd[2]), .ZN(registers[2])); + SDFF_X1_LVT \registers_reg[28][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_28__ap[2]), .CK(n_0_58), .Q(registers_28__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[4][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_4__ap[2]), .CK(n_0_34), .Q(registers_4__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_740 (.A1(registers_28__ap[2]), .A2(n_1_0_1283), .B1( + n_1_0_1278), .B2(registers_4__ap[2]), .ZN(n_1_0_705)); + SDFF_X1_LVT \registers_reg[16][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_16__ap[2]), .CK(n_0_46), .Q(registers_16__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[31][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_31__ap[2]), .CK(n_0_61), .Q(registers_31__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_743 (.A1(registers_16__ap[2]), .A2(n_1_0_1267), .B1( + n_1_0_1266), .B2(registers_31__ap[2]), .ZN(n_1_0_708)); + SDFF_X1_LVT \registers_reg[6][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_6__ap[2]), .CK(n_0_36), .Q(registers_6__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[1][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_1__ap[2]), .CK(n_0_0), .Q(registers_1__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_739 (.A1(registers_6__ap[2]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[2]), .ZN(n_1_0_704)); + SDFF_X1_LVT \registers_reg[15][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_15__ap[2]), .CK(n_0_45), .Q(registers_15__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[27][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_27__ap[2]), .CK(n_0_57), .Q(registers_27__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_742 (.A1(registers_15__ap[2]), .A2(n_1_0_1286), .B1( + n_1_0_1279), .B2(registers_27__ap[2]), .ZN(n_1_0_707)); + INV_X1_LVT i_1_0_741 (.A(n_1_0_707), .ZN(n_1_0_706)); + SDFF_X1_LVT \registers_reg[11][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_11__ap[2]), .CK(n_0_41), .Q(registers_11__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[5][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_5__ap[2]), .CK(n_0_35), .Q(registers_5__ap[2]), .QN()); + AOI221_X1_LVT i_1_0_738 (.A(n_1_0_706), .B1(n_1_0_1270), .B2( + registers_11__ap[2]), .C1(registers_5__ap[2]), .C2(n_1_0_1273), .ZN( + n_1_0_703)); + SDFF_X1_LVT \registers_reg[10][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_10__ap[2]), .CK(n_0_40), .Q(registers_10__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[30][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_30__ap[2]), .CK(n_0_60), .Q(registers_30__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[8][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_8__ap[2]), .CK(n_0_38), .Q(registers_8__ap[2]), .QN()); + AOI222_X1_LVT i_1_0_737 (.A1(registers_10__ap[2]), .A2(n_1_0_1287), .B1( + n_1_0_1272), .B2(registers_30__ap[2]), .C1(n_1_0_1282), .C2( + registers_8__ap[2]), .ZN(n_1_0_702)); + NAND4_X1_LVT i_1_0_736 (.A1(n_1_0_708), .A2(n_1_0_704), .A3(n_1_0_703), + .A4(n_1_0_702), .ZN(n_1_0_701)); + SDFF_X1_LVT \registers_reg[9][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_9__ap[2]), .CK(n_0_39), .Q(registers_9__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[29][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_29__ap[2]), .CK(n_0_59), .Q(registers_29__ap[2]), .QN()); + AOI221_X1_LVT i_1_0_735 (.A(n_1_0_701), .B1(n_1_0_1291), .B2( + registers_9__ap[2]), .C1(registers_29__ap[2]), .C2(n_1_0_1276), .ZN( + n_1_0_700)); + SDFF_X1_LVT \registers_reg[18][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_18__ap[2]), .CK(n_0_48), .Q(registers_18__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[26][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_26__ap[2]), .CK(n_0_56), .Q(registers_26__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_734 (.A1(registers_18__ap[2]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[2]), .ZN(n_1_0_699)); + SDFF_X1_LVT \registers_reg[24][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_24__ap[2]), .CK(n_0_54), .Q(registers_24__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[12][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_12__ap[2]), .CK(n_0_42), .Q(registers_12__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_733 (.A1(registers_24__ap[2]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[2]), .ZN(n_1_0_698)); + SDFF_X1_LVT \registers_reg[22][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_22__ap[2]), .CK(n_0_52), .Q(registers_22__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[21][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_21__ap[2]), .CK(n_0_51), .Q(registers_21__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_732 (.A1(registers_22__ap[2]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[2]), .ZN(n_1_0_697)); + NAND3_X1_LVT i_1_0_731 (.A1(n_1_0_699), .A2(n_1_0_698), .A3(n_1_0_697), + .ZN(n_1_0_696)); + SDFF_X1_LVT \registers_reg[17][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_17__ap[2]), .CK(n_0_47), .Q(registers_17__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[20][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_20__ap[2]), .CK(n_0_50), .Q(registers_20__ap[2]), .QN()); + AOI221_X1_LVT i_1_0_730 (.A(n_1_0_696), .B1(n_1_0_1271), .B2( + registers_17__ap[2]), .C1(registers_20__ap[2]), .C2(n_1_0_1281), .ZN( + n_1_0_695)); + SDFF_X1_LVT \registers_reg[13][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_13__ap[2]), .CK(n_0_43), .Q(registers_13__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[25][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_25__ap[2]), .CK(n_0_55), .Q(registers_25__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_729 (.A1(registers_13__ap[2]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[2]), .ZN(n_1_0_694)); + SDFF_X1_LVT \registers_reg[7][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_7__ap[2]), .CK(n_0_37), .Q(registers_7__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[14][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_14__ap[2]), .CK(n_0_44), .Q(registers_14__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_728 (.A1(registers_7__ap[2]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[2]), .ZN(n_1_0_693)); + SDFF_X1_LVT \registers_reg[19][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_19__ap[2]), .CK(n_0_49), .Q(registers_19__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[3][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_3__ap[2]), .CK(n_0_33), .Q(registers_3__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_727 (.A1(registers_19__ap[2]), .A2(n_1_0_1295), .B1( + n_1_0_1257), .B2(registers_3__ap[2]), .ZN(n_1_0_692)); + NAND3_X1_LVT i_1_0_726 (.A1(n_1_0_694), .A2(n_1_0_693), .A3(n_1_0_692), + .ZN(n_1_0_691)); + SDFF_X1_LVT \registers_reg[23][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_23__ap[2]), .CK(n_0_53), .Q(registers_23__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[2][2] (.D(registers[2]), .SE(1'b0), .SI( + registers_2__ap[2]), .CK(n_0_32), .Q(registers_2__ap[2]), .QN()); + AOI221_X1_LVT i_1_0_725 (.A(n_1_0_691), .B1(n_1_0_1264), .B2( + registers_23__ap[2]), .C1(registers_2__ap[2]), .C2(n_1_0_1268), .ZN( + n_1_0_690)); + NAND4_X1_LVT i_1_0_724 (.A1(n_1_0_705), .A2(n_1_0_700), .A3(n_1_0_695), + .A4(n_1_0_690), .ZN(RRs1[2])); + AND2_X1_LVT i_0_0_1 (.A1(n_0_0_16), .A2(WRd[1]), .ZN(registers[1])); + SDFF_X1_LVT \registers_reg[13][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_13__ap[1]), .CK(n_0_43), .Q(registers_13__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[21][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_21__ap[1]), .CK(n_0_51), .Q(registers_21__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_720 (.A1(registers_13__ap[1]), .A2(n_1_0_1277), .B1( + n_1_0_1259), .B2(registers_21__ap[1]), .ZN(n_1_0_686)); + SDFF_X1_LVT \registers_reg[29][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_29__ap[1]), .CK(n_0_59), .Q(registers_29__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[23][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_23__ap[1]), .CK(n_0_53), .Q(registers_23__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_723 (.A1(registers_29__ap[1]), .A2(n_1_0_1276), .B1( + n_1_0_1264), .B2(registers_23__ap[1]), .ZN(n_1_0_689)); + SDFF_X1_LVT \registers_reg[24][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_24__ap[1]), .CK(n_0_54), .Q(registers_24__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[20][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_20__ap[1]), .CK(n_0_50), .Q(registers_20__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_719 (.A1(registers_24__ap[1]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[1]), .ZN(n_1_0_685)); + SDFF_X1_LVT \registers_reg[7][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_7__ap[1]), .CK(n_0_37), .Q(registers_7__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[3][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_3__ap[1]), .CK(n_0_33), .Q(registers_3__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_722 (.A1(registers_7__ap[1]), .A2(n_1_0_1263), .B1( + n_1_0_1257), .B2(registers_3__ap[1]), .ZN(n_1_0_688)); + INV_X1_LVT i_1_0_721 (.A(n_1_0_688), .ZN(n_1_0_687)); + SDFF_X1_LVT \registers_reg[31][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_31__ap[1]), .CK(n_0_61), .Q(registers_31__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[4][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_4__ap[1]), .CK(n_0_34), .Q(registers_4__ap[1]), .QN()); + AOI221_X1_LVT i_1_0_718 (.A(n_1_0_687), .B1(n_1_0_1266), .B2( + registers_31__ap[1]), .C1(registers_4__ap[1]), .C2(n_1_0_1278), .ZN( + n_1_0_684)); + SDFF_X1_LVT \registers_reg[10][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_10__ap[1]), .CK(n_0_40), .Q(registers_10__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[26][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_26__ap[1]), .CK(n_0_56), .Q(registers_26__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[25][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_25__ap[1]), .CK(n_0_55), .Q(registers_25__ap[1]), .QN()); + AOI222_X1_LVT i_1_0_717 (.A1(registers_10__ap[1]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[1]), .C1(registers_25__ap[1]), .C2( + n_1_0_1269), .ZN(n_1_0_683)); + NAND4_X1_LVT i_1_0_716 (.A1(n_1_0_689), .A2(n_1_0_685), .A3(n_1_0_684), + .A4(n_1_0_683), .ZN(n_1_0_682)); + SDFF_X1_LVT \registers_reg[8][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_8__ap[1]), .CK(n_0_38), .Q(registers_8__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[28][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_28__ap[1]), .CK(n_0_58), .Q(registers_28__ap[1]), .QN()); + AOI221_X1_LVT i_1_0_715 (.A(n_1_0_682), .B1(n_1_0_1282), .B2( + registers_8__ap[1]), .C1(registers_28__ap[1]), .C2(n_1_0_1283), .ZN( + n_1_0_681)); + SDFF_X1_LVT \registers_reg[18][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_18__ap[1]), .CK(n_0_48), .Q(registers_18__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[30][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_30__ap[1]), .CK(n_0_60), .Q(registers_30__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_714 (.A1(registers_18__ap[1]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[1]), .ZN(n_1_0_680)); + SDFF_X1_LVT \registers_reg[17][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_17__ap[1]), .CK(n_0_47), .Q(registers_17__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[12][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_12__ap[1]), .CK(n_0_42), .Q(registers_12__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_713 (.A1(registers_17__ap[1]), .A2(n_1_0_1271), .B1( + n_1_0_1260), .B2(registers_12__ap[1]), .ZN(n_1_0_679)); + SDFF_X1_LVT \registers_reg[15][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_15__ap[1]), .CK(n_0_45), .Q(registers_15__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[5][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_5__ap[1]), .CK(n_0_35), .Q(registers_5__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_712 (.A1(registers_15__ap[1]), .A2(n_1_0_1286), .B1( + n_1_0_1273), .B2(registers_5__ap[1]), .ZN(n_1_0_678)); + NAND3_X1_LVT i_1_0_711 (.A1(n_1_0_680), .A2(n_1_0_679), .A3(n_1_0_678), + .ZN(n_1_0_677)); + SDFF_X1_LVT \registers_reg[22][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_22__ap[1]), .CK(n_0_52), .Q(registers_22__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[16][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_16__ap[1]), .CK(n_0_46), .Q(registers_16__ap[1]), .QN()); + AOI221_X1_LVT i_1_0_710 (.A(n_1_0_677), .B1(n_1_0_1294), .B2( + registers_22__ap[1]), .C1(registers_16__ap[1]), .C2(n_1_0_1267), .ZN( + n_1_0_676)); + SDFF_X1_LVT \registers_reg[9][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_9__ap[1]), .CK(n_0_39), .Q(registers_9__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[1][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_1__ap[1]), .CK(n_0_0), .Q(registers_1__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_709 (.A1(registers_9__ap[1]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[1]), .ZN(n_1_0_675)); + SDFF_X1_LVT \registers_reg[6][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_6__ap[1]), .CK(n_0_36), .Q(registers_6__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[14][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_14__ap[1]), .CK(n_0_44), .Q(registers_14__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_708 (.A1(registers_6__ap[1]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[1]), .ZN(n_1_0_674)); + SDFF_X1_LVT \registers_reg[19][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_19__ap[1]), .CK(n_0_49), .Q(registers_19__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[2][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_2__ap[1]), .CK(n_0_32), .Q(registers_2__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_707 (.A1(registers_19__ap[1]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[1]), .ZN(n_1_0_673)); + NAND3_X1_LVT i_1_0_706 (.A1(n_1_0_675), .A2(n_1_0_674), .A3(n_1_0_673), + .ZN(n_1_0_672)); + SDFF_X1_LVT \registers_reg[11][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_11__ap[1]), .CK(n_0_41), .Q(registers_11__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[27][1] (.D(registers[1]), .SE(1'b0), .SI( + registers_27__ap[1]), .CK(n_0_57), .Q(registers_27__ap[1]), .QN()); + AOI221_X1_LVT i_1_0_705 (.A(n_1_0_672), .B1(n_1_0_1270), .B2( + registers_11__ap[1]), .C1(registers_27__ap[1]), .C2(n_1_0_1279), .ZN( + n_1_0_671)); + NAND4_X1_LVT i_1_0_704 (.A1(n_1_0_686), .A2(n_1_0_681), .A3(n_1_0_676), + .A4(n_1_0_671), .ZN(RRs1[1])); + AND2_X1_LVT i_0_0_0 (.A1(n_0_0_16), .A2(WRd[0]), .ZN(registers[0])); + SDFF_X1_LVT \registers_reg[13][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_13__ap[0]), .CK(n_0_43), .Q(registers_13__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[21][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_21__ap[0]), .CK(n_0_51), .Q(registers_21__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_703 (.A1(registers_13__ap[0]), .A2(n_1_0_1277), .B1( + n_1_0_1259), .B2(registers_21__ap[0]), .ZN(n_1_0_670)); + SDFF_X1_LVT \registers_reg[10][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_10__ap[0]), .CK(n_0_40), .Q(registers_10__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[26][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_26__ap[0]), .CK(n_0_56), .Q(registers_26__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[25][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_25__ap[0]), .CK(n_0_55), .Q(registers_25__ap[0]), .QN()); + AOI222_X1_LVT i_1_0_702 (.A1(registers_10__ap[0]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[0]), .C1(registers_25__ap[0]), .C2( + n_1_0_1269), .ZN(n_1_0_669)); + SDFF_X1_LVT \registers_reg[28][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_28__ap[0]), .CK(n_0_58), .Q(registers_28__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[8][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_8__ap[0]), .CK(n_0_38), .Q(registers_8__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_701 (.A1(registers_28__ap[0]), .A2(n_1_0_1283), .B1( + n_1_0_1282), .B2(registers_8__ap[0]), .ZN(n_1_0_668)); + SDFF_X1_LVT \registers_reg[24][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_24__ap[0]), .CK(n_0_54), .Q(registers_24__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[20][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_20__ap[0]), .CK(n_0_50), .Q(registers_20__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_700 (.A1(registers_24__ap[0]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[0]), .ZN(n_1_0_667)); + SDFF_X1_LVT \registers_reg[7][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_7__ap[0]), .CK(n_0_37), .Q(registers_7__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[3][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_3__ap[0]), .CK(n_0_33), .Q(registers_3__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_699 (.A1(registers_7__ap[0]), .A2(n_1_0_1263), .B1( + n_1_0_1257), .B2(registers_3__ap[0]), .ZN(n_1_0_666)); + SDFF_X1_LVT \registers_reg[17][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_17__ap[0]), .CK(n_0_47), .Q(registers_17__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[31][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_31__ap[0]), .CK(n_0_61), .Q(registers_31__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_698 (.A1(registers_17__ap[0]), .A2(n_1_0_1271), .B1( + n_1_0_1266), .B2(registers_31__ap[0]), .ZN(n_1_0_665)); + SDFF_X1_LVT \registers_reg[29][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_29__ap[0]), .CK(n_0_59), .Q(registers_29__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[23][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_23__ap[0]), .CK(n_0_53), .Q(registers_23__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_697 (.A1(registers_29__ap[0]), .A2(n_1_0_1276), .B1( + n_1_0_1264), .B2(registers_23__ap[0]), .ZN(n_1_0_664)); + NAND4_X1_LVT i_1_0_696 (.A1(n_1_0_667), .A2(n_1_0_666), .A3(n_1_0_665), + .A4(n_1_0_664), .ZN(n_1_0_663)); + SDFF_X1_LVT \registers_reg[18][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_18__ap[0]), .CK(n_0_48), .Q(registers_18__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[30][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_30__ap[0]), .CK(n_0_60), .Q(registers_30__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_695 (.A1(registers_18__ap[0]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[0]), .ZN(n_1_0_662)); + SDFF_X1_LVT \registers_reg[4][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_4__ap[0]), .CK(n_0_34), .Q(registers_4__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[12][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_12__ap[0]), .CK(n_0_42), .Q(registers_12__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_694 (.A1(registers_4__ap[0]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[0]), .ZN(n_1_0_661)); + SDFF_X1_LVT \registers_reg[15][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_15__ap[0]), .CK(n_0_45), .Q(registers_15__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[16][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_16__ap[0]), .CK(n_0_46), .Q(registers_16__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_693 (.A1(registers_15__ap[0]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[0]), .ZN(n_1_0_660)); + SDFF_X1_LVT \registers_reg[22][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_22__ap[0]), .CK(n_0_52), .Q(registers_22__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[5][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_5__ap[0]), .CK(n_0_35), .Q(registers_5__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_692 (.A1(registers_22__ap[0]), .A2(n_1_0_1294), .B1( + n_1_0_1273), .B2(registers_5__ap[0]), .ZN(n_1_0_659)); + NAND4_X1_LVT i_1_0_691 (.A1(n_1_0_662), .A2(n_1_0_661), .A3(n_1_0_660), + .A4(n_1_0_659), .ZN(n_1_0_658)); + SDFF_X1_LVT \registers_reg[19][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_19__ap[0]), .CK(n_0_49), .Q(registers_19__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[2][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_2__ap[0]), .CK(n_0_32), .Q(registers_2__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_690 (.A1(registers_19__ap[0]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[0]), .ZN(n_1_0_657)); + SDFF_X1_LVT \registers_reg[9][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_9__ap[0]), .CK(n_0_39), .Q(registers_9__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[1][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_1__ap[0]), .CK(n_0_0), .Q(registers_1__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_689 (.A1(registers_9__ap[0]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[0]), .ZN(n_1_0_656)); + SDFF_X1_LVT \registers_reg[6][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_6__ap[0]), .CK(n_0_36), .Q(registers_6__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[14][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_14__ap[0]), .CK(n_0_44), .Q(registers_14__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_688 (.A1(registers_6__ap[0]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[0]), .ZN(n_1_0_655)); + SDFF_X1_LVT \registers_reg[27][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_27__ap[0]), .CK(n_0_57), .Q(registers_27__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[11][0] (.D(registers[0]), .SE(1'b0), .SI( + registers_11__ap[0]), .CK(n_0_41), .Q(registers_11__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_687 (.A1(registers_27__ap[0]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[0]), .ZN(n_1_0_654)); + NAND4_X1_LVT i_1_0_686 (.A1(n_1_0_657), .A2(n_1_0_656), .A3(n_1_0_655), + .A4(n_1_0_654), .ZN(n_1_0_653)); + NOR3_X1_LVT i_1_0_685 (.A1(n_1_0_663), .A2(n_1_0_658), .A3(n_1_0_653), + .ZN(n_1_0_652)); + NAND4_X1_LVT i_1_0_684 (.A1(n_1_0_670), .A2(n_1_0_669), .A3(n_1_0_668), + .A4(n_1_0_652), .ZN(RRs1[0])); + INV_X1_LVT i_1_0_1366 (.A(Rs2[1]), .ZN(n_1_0_1302)); + NAND3_X1_LVT i_1_0_683 (.A1(n_1_0_1302), .A2(Rs2[4]), .A3(Rs2[2]), .ZN( + n_1_0_651)); + INV_X1_LVT i_1_0_1369 (.A(Rs2[3]), .ZN(n_1_0_1305)); + OR2_X1_LVT i_1_0_673 (.A1(n_1_0_1305), .A2(Rs2[0]), .ZN(n_1_0_641)); + NOR2_X1_LVT i_1_0_666 (.A1(n_1_0_651), .A2(n_1_0_641), .ZN(n_1_0_634)); + NAND2_X1_LVT i_1_0_677 (.A1(n_1_0_1305), .A2(Rs2[0]), .ZN(n_1_0_645)); + INV_X1_LVT i_1_0_1368 (.A(Rs2[2]), .ZN(n_1_0_1304)); + NAND3_X1_LVT i_1_0_662 (.A1(n_1_0_1304), .A2(n_1_0_1302), .A3(Rs2[4]), + .ZN(n_1_0_630)); + NOR2_X1_LVT i_1_0_661 (.A1(n_1_0_645), .A2(n_1_0_630), .ZN(n_1_0_629)); + AOI22_X1_LVT i_1_0_641 (.A1(registers_28__ap[31]), .A2(n_1_0_634), .B1( + n_1_0_629), .B2(registers_17__ap[31]), .ZN(n_1_0_609)); + NAND3_X1_LVT i_1_0_680 (.A1(n_1_0_1304), .A2(Rs2[4]), .A3(Rs2[1]), .ZN( + n_1_0_648)); + NOR2_X1_LVT i_1_0_672 (.A1(n_1_0_648), .A2(n_1_0_641), .ZN(n_1_0_640)); + INV_X1_LVT i_1_0_1367 (.A(Rs2[4]), .ZN(n_1_0_1303)); + NAND3_X1_LVT i_1_0_657 (.A1(n_1_0_1304), .A2(n_1_0_1303), .A3(Rs2[1]), + .ZN(n_1_0_625)); + NOR2_X1_LVT i_1_0_656 (.A1(n_1_0_641), .A2(n_1_0_625), .ZN(n_1_0_624)); + NOR4_X1_LVT i_1_0_658 (.A1(n_1_0_641), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), + .ZN(n_1_0_626)); + AOI222_X1_LVT i_1_0_640 (.A1(registers_26__ap[31]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[31]), .C1(n_1_0_626), .C2( + registers_8__ap[31]), .ZN(n_1_0_608)); + NAND2_X1_LVT i_1_0_682 (.A1(Rs2[0]), .A2(Rs2[3]), .ZN(n_1_0_650)); + NOR2_X1_LVT i_1_0_681 (.A1(n_1_0_651), .A2(n_1_0_650), .ZN(n_1_0_649)); + NOR4_X1_LVT i_1_0_649 (.A1(n_1_0_650), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), + .ZN(n_1_0_617)); + AOI22_X1_LVT i_1_0_639 (.A1(registers_29__ap[31]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[31]), .ZN(n_1_0_607)); + NOR4_X1_LVT i_1_0_676 (.A1(n_1_0_645), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), + .ZN(n_1_0_644)); + OR2_X1_LVT i_1_0_679 (.A1(Rs2[0]), .A2(Rs2[3]), .ZN(n_1_0_647)); + NAND3_X1_LVT i_1_0_660 (.A1(n_1_0_1303), .A2(Rs2[1]), .A3(Rs2[2]), .ZN( + n_1_0_628)); + NOR2_X1_LVT i_1_0_648 (.A1(n_1_0_647), .A2(n_1_0_628), .ZN(n_1_0_616)); + AOI22_X1_LVT i_1_0_638 (.A1(registers_1__ap[31]), .A2(n_1_0_644), .B1( + n_1_0_616), .B2(registers_6__ap[31]), .ZN(n_1_0_606)); + NOR2_X1_LVT i_1_0_655 (.A1(n_1_0_645), .A2(n_1_0_628), .ZN(n_1_0_623)); + NAND3_X1_LVT i_1_0_675 (.A1(Rs2[2]), .A2(Rs2[4]), .A3(Rs2[1]), .ZN(n_1_0_643)); + NOR2_X1_LVT i_1_0_647 (.A1(n_1_0_645), .A2(n_1_0_643), .ZN(n_1_0_615)); + AOI22_X1_LVT i_1_0_637 (.A1(registers_7__ap[31]), .A2(n_1_0_623), .B1( + n_1_0_615), .B2(registers_23__ap[31]), .ZN(n_1_0_605)); + NOR2_X1_LVT i_1_0_665 (.A1(n_1_0_648), .A2(n_1_0_645), .ZN(n_1_0_633)); + NOR2_X1_LVT i_1_0_646 (.A1(n_1_0_647), .A2(n_1_0_630), .ZN(n_1_0_614)); + AOI22_X1_LVT i_1_0_636 (.A1(registers_19__ap[31]), .A2(n_1_0_633), .B1( + n_1_0_614), .B2(registers_16__ap[31]), .ZN(n_1_0_604)); + NOR2_X1_LVT i_1_0_669 (.A1(n_1_0_650), .A2(n_1_0_643), .ZN(n_1_0_637)); + NAND3_X1_LVT i_1_0_671 (.A1(n_1_0_1303), .A2(n_1_0_1302), .A3(Rs2[2]), + .ZN(n_1_0_639)); + NOR2_X1_LVT i_1_0_667 (.A1(n_1_0_645), .A2(n_1_0_639), .ZN(n_1_0_635)); + AOI22_X1_LVT i_1_0_635 (.A1(registers_31__ap[31]), .A2(n_1_0_637), .B1( + n_1_0_635), .B2(registers_5__ap[31]), .ZN(n_1_0_603)); + NAND4_X1_LVT i_1_0_634 (.A1(n_1_0_606), .A2(n_1_0_605), .A3(n_1_0_604), + .A4(n_1_0_603), .ZN(n_1_0_602)); + NOR2_X1_LVT i_1_0_678 (.A1(n_1_0_648), .A2(n_1_0_647), .ZN(n_1_0_646)); + NOR2_X1_LVT i_1_0_654 (.A1(n_1_0_643), .A2(n_1_0_641), .ZN(n_1_0_622)); + AOI22_X1_LVT i_1_0_633 (.A1(registers_18__ap[31]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[31]), .ZN(n_1_0_601)); + NOR2_X1_LVT i_1_0_670 (.A1(n_1_0_647), .A2(n_1_0_639), .ZN(n_1_0_638)); + NOR2_X1_LVT i_1_0_645 (.A1(n_1_0_651), .A2(n_1_0_647), .ZN(n_1_0_613)); + AOI22_X1_LVT i_1_0_632 (.A1(registers_4__ap[31]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[31]), .ZN(n_1_0_600)); + NOR2_X1_LVT i_1_0_674 (.A1(n_1_0_647), .A2(n_1_0_643), .ZN(n_1_0_642)); + NOR2_X1_LVT i_1_0_644 (.A1(n_1_0_651), .A2(n_1_0_645), .ZN(n_1_0_612)); + AOI22_X1_LVT i_1_0_631 (.A1(registers_22__ap[31]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[31]), .ZN(n_1_0_599)); + NOR2_X1_LVT i_1_0_664 (.A1(n_1_0_641), .A2(n_1_0_639), .ZN(n_1_0_632)); + NOR2_X1_LVT i_1_0_653 (.A1(n_1_0_641), .A2(n_1_0_630), .ZN(n_1_0_621)); + AOI22_X1_LVT i_1_0_630 (.A1(registers_12__ap[31]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[31]), .ZN(n_1_0_598)); + NAND4_X1_LVT i_1_0_629 (.A1(n_1_0_601), .A2(n_1_0_600), .A3(n_1_0_599), + .A4(n_1_0_598), .ZN(n_1_0_597)); + NOR2_X1_LVT i_1_0_663 (.A1(n_1_0_650), .A2(n_1_0_639), .ZN(n_1_0_631)); + NOR2_X1_LVT i_1_0_652 (.A1(n_1_0_650), .A2(n_1_0_630), .ZN(n_1_0_620)); + AOI22_X1_LVT i_1_0_628 (.A1(registers_13__ap[31]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[31]), .ZN(n_1_0_596)); + NOR2_X1_LVT i_1_0_659 (.A1(n_1_0_650), .A2(n_1_0_628), .ZN(n_1_0_627)); + NOR2_X1_LVT i_1_0_651 (.A1(n_1_0_641), .A2(n_1_0_628), .ZN(n_1_0_619)); + AOI22_X1_LVT i_1_0_627 (.A1(registers_15__ap[31]), .A2(n_1_0_627), .B1( + n_1_0_619), .B2(registers_14__ap[31]), .ZN(n_1_0_595)); + NOR2_X1_LVT i_1_0_668 (.A1(n_1_0_650), .A2(n_1_0_648), .ZN(n_1_0_636)); + NOR2_X1_LVT i_1_0_643 (.A1(n_1_0_650), .A2(n_1_0_625), .ZN(n_1_0_611)); + AOI22_X1_LVT i_1_0_626 (.A1(registers_27__ap[31]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[31]), .ZN(n_1_0_594)); + NOR2_X1_LVT i_1_0_650 (.A1(n_1_0_647), .A2(n_1_0_625), .ZN(n_1_0_618)); + NOR2_X1_LVT i_1_0_642 (.A1(n_1_0_645), .A2(n_1_0_625), .ZN(n_1_0_610)); + AOI22_X1_LVT i_1_0_625 (.A1(registers_2__ap[31]), .A2(n_1_0_618), .B1( + n_1_0_610), .B2(registers_3__ap[31]), .ZN(n_1_0_593)); + NAND4_X1_LVT i_1_0_624 (.A1(n_1_0_596), .A2(n_1_0_595), .A3(n_1_0_594), + .A4(n_1_0_593), .ZN(n_1_0_592)); + NOR3_X1_LVT i_1_0_623 (.A1(n_1_0_602), .A2(n_1_0_597), .A3(n_1_0_592), + .ZN(n_1_0_591)); + NAND4_X1_LVT i_1_0_622 (.A1(n_1_0_609), .A2(n_1_0_608), .A3(n_1_0_607), + .A4(n_1_0_591), .ZN(RRs2[31])); + AOI22_X1_LVT i_1_0_620 (.A1(registers_29__ap[30]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[30]), .ZN(n_1_0_589)); + AOI22_X1_LVT i_1_0_621 (.A1(registers_7__ap[30]), .A2(n_1_0_623), .B1( + n_1_0_615), .B2(registers_23__ap[30]), .ZN(n_1_0_590)); + AOI22_X1_LVT i_1_0_619 (.A1(registers_1__ap[30]), .A2(n_1_0_644), .B1( + n_1_0_616), .B2(registers_6__ap[30]), .ZN(n_1_0_588)); + AOI22_X1_LVT i_1_0_618 (.A1(registers_5__ap[30]), .A2(n_1_0_635), .B1( + n_1_0_633), .B2(registers_19__ap[30]), .ZN(n_1_0_587)); + NAND3_X1_LVT i_1_0_617 (.A1(n_1_0_590), .A2(n_1_0_588), .A3(n_1_0_587), + .ZN(n_1_0_586)); + AOI221_X1_LVT i_1_0_616 (.A(n_1_0_586), .B1(n_1_0_637), .B2( + registers_31__ap[30]), .C1(registers_16__ap[30]), .C2(n_1_0_614), .ZN( + n_1_0_585)); + AOI222_X1_LVT i_1_0_615 (.A1(registers_26__ap[30]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[30]), .C1(n_1_0_626), .C2( + registers_8__ap[30]), .ZN(n_1_0_584)); + NAND3_X1_LVT i_1_0_614 (.A1(n_1_0_589), .A2(n_1_0_585), .A3(n_1_0_584), + .ZN(n_1_0_583)); + AOI221_X1_LVT i_1_0_613 (.A(n_1_0_583), .B1(n_1_0_629), .B2( + registers_17__ap[30]), .C1(registers_28__ap[30]), .C2(n_1_0_634), .ZN( + n_1_0_582)); + AOI22_X1_LVT i_1_0_612 (.A1(registers_18__ap[30]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[30]), .ZN(n_1_0_581)); + AOI22_X1_LVT i_1_0_611 (.A1(registers_4__ap[30]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[30]), .ZN(n_1_0_580)); + AOI22_X1_LVT i_1_0_610 (.A1(registers_22__ap[30]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[30]), .ZN(n_1_0_579)); + NAND3_X1_LVT i_1_0_609 (.A1(n_1_0_581), .A2(n_1_0_580), .A3(n_1_0_579), + .ZN(n_1_0_578)); + AOI221_X1_LVT i_1_0_608 (.A(n_1_0_578), .B1(n_1_0_621), .B2( + registers_24__ap[30]), .C1(registers_12__ap[30]), .C2(n_1_0_632), .ZN( + n_1_0_577)); + AOI22_X1_LVT i_1_0_607 (.A1(registers_13__ap[30]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[30]), .ZN(n_1_0_576)); + AOI22_X1_LVT i_1_0_606 (.A1(registers_15__ap[30]), .A2(n_1_0_627), .B1( + n_1_0_619), .B2(registers_14__ap[30]), .ZN(n_1_0_575)); + AOI22_X1_LVT i_1_0_605 (.A1(registers_27__ap[30]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[30]), .ZN(n_1_0_574)); + NAND3_X1_LVT i_1_0_604 (.A1(n_1_0_576), .A2(n_1_0_575), .A3(n_1_0_574), + .ZN(n_1_0_573)); + AOI221_X1_LVT i_1_0_603 (.A(n_1_0_573), .B1(n_1_0_610), .B2( + registers_3__ap[30]), .C1(registers_2__ap[30]), .C2(n_1_0_618), .ZN( + n_1_0_572)); + NAND3_X1_LVT i_1_0_602 (.A1(n_1_0_582), .A2(n_1_0_577), .A3(n_1_0_572), + .ZN(RRs2[30])); + AOI22_X1_LVT i_1_0_600 (.A1(registers_28__ap[29]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[29]), .ZN(n_1_0_570)); + AOI22_X1_LVT i_1_0_601 (.A1(registers_31__ap[29]), .A2(n_1_0_637), .B1( + n_1_0_627), .B2(registers_15__ap[29]), .ZN(n_1_0_571)); + AOI22_X1_LVT i_1_0_599 (.A1(registers_24__ap[29]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[29]), .ZN(n_1_0_569)); + AOI22_X1_LVT i_1_0_598 (.A1(registers_19__ap[29]), .A2(n_1_0_633), .B1( + n_1_0_629), .B2(registers_17__ap[29]), .ZN(n_1_0_568)); + NAND3_X1_LVT i_1_0_597 (.A1(n_1_0_571), .A2(n_1_0_569), .A3(n_1_0_568), + .ZN(n_1_0_567)); + AOI221_X1_LVT i_1_0_596 (.A(n_1_0_567), .B1(n_1_0_615), .B2( + registers_23__ap[29]), .C1(registers_29__ap[29]), .C2(n_1_0_649), .ZN( + n_1_0_566)); + AOI222_X1_LVT i_1_0_595 (.A1(registers_26__ap[29]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[29]), .C1(n_1_0_620), .C2( + registers_25__ap[29]), .ZN(n_1_0_565)); + NAND3_X1_LVT i_1_0_594 (.A1(n_1_0_570), .A2(n_1_0_566), .A3(n_1_0_565), + .ZN(n_1_0_564)); + AOI221_X1_LVT i_1_0_593 (.A(n_1_0_564), .B1(n_1_0_612), .B2( + registers_21__ap[29]), .C1(registers_13__ap[29]), .C2(n_1_0_631), .ZN( + n_1_0_563)); + AOI22_X1_LVT i_1_0_592 (.A1(registers_18__ap[29]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[29]), .ZN(n_1_0_562)); + AOI22_X1_LVT i_1_0_591 (.A1(registers_4__ap[29]), .A2(n_1_0_638), .B1( + n_1_0_632), .B2(registers_12__ap[29]), .ZN(n_1_0_561)); + AOI22_X1_LVT i_1_0_590 (.A1(registers_7__ap[29]), .A2(n_1_0_623), .B1( + n_1_0_614), .B2(registers_16__ap[29]), .ZN(n_1_0_560)); + NAND3_X1_LVT i_1_0_589 (.A1(n_1_0_562), .A2(n_1_0_561), .A3(n_1_0_560), + .ZN(n_1_0_559)); + AOI221_X1_LVT i_1_0_588 (.A(n_1_0_559), .B1(n_1_0_642), .B2( + registers_22__ap[29]), .C1(registers_5__ap[29]), .C2(n_1_0_635), .ZN( + n_1_0_558)); + AOI22_X1_LVT i_1_0_587 (.A1(registers_1__ap[29]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[29]), .ZN(n_1_0_557)); + AOI22_X1_LVT i_1_0_586 (.A1(registers_14__ap[29]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[29]), .ZN(n_1_0_556)); + AOI22_X1_LVT i_1_0_585 (.A1(registers_27__ap[29]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[29]), .ZN(n_1_0_555)); + NAND3_X1_LVT i_1_0_584 (.A1(n_1_0_557), .A2(n_1_0_556), .A3(n_1_0_555), + .ZN(n_1_0_554)); + AOI221_X1_LVT i_1_0_583 (.A(n_1_0_554), .B1(n_1_0_610), .B2( + registers_3__ap[29]), .C1(registers_2__ap[29]), .C2(n_1_0_618), .ZN( + n_1_0_553)); + NAND3_X1_LVT i_1_0_582 (.A1(n_1_0_563), .A2(n_1_0_558), .A3(n_1_0_553), + .ZN(RRs2[29])); + AOI22_X1_LVT i_1_0_581 (.A1(registers_5__ap[28]), .A2(n_1_0_635), .B1( + n_1_0_634), .B2(registers_28__ap[28]), .ZN(n_1_0_552)); + AOI222_X1_LVT i_1_0_580 (.A1(registers_26__ap[28]), .A2(n_1_0_640), .B1( + n_1_0_633), .B2(registers_19__ap[28]), .C1(n_1_0_626), .C2( + registers_8__ap[28]), .ZN(n_1_0_551)); + AOI22_X1_LVT i_1_0_579 (.A1(registers_2__ap[28]), .A2(n_1_0_618), .B1( + n_1_0_617), .B2(registers_9__ap[28]), .ZN(n_1_0_550)); + AOI22_X1_LVT i_1_0_578 (.A1(registers_7__ap[28]), .A2(n_1_0_623), .B1( + n_1_0_612), .B2(registers_21__ap[28]), .ZN(n_1_0_549)); + AOI22_X1_LVT i_1_0_577 (.A1(registers_16__ap[28]), .A2(n_1_0_614), .B1( + n_1_0_611), .B2(registers_11__ap[28]), .ZN(n_1_0_548)); + AOI22_X1_LVT i_1_0_576 (.A1(registers_31__ap[28]), .A2(n_1_0_637), .B1( + n_1_0_619), .B2(registers_14__ap[28]), .ZN(n_1_0_547)); + AOI22_X1_LVT i_1_0_575 (.A1(registers_15__ap[28]), .A2(n_1_0_627), .B1( + n_1_0_610), .B2(registers_3__ap[28]), .ZN(n_1_0_546)); + NAND4_X1_LVT i_1_0_574 (.A1(n_1_0_549), .A2(n_1_0_548), .A3(n_1_0_547), + .A4(n_1_0_546), .ZN(n_1_0_545)); + AOI22_X1_LVT i_1_0_573 (.A1(registers_22__ap[28]), .A2(n_1_0_642), .B1( + n_1_0_622), .B2(registers_30__ap[28]), .ZN(n_1_0_544)); + AOI22_X1_LVT i_1_0_572 (.A1(registers_4__ap[28]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[28]), .ZN(n_1_0_543)); + AOI22_X1_LVT i_1_0_571 (.A1(registers_29__ap[28]), .A2(n_1_0_649), .B1( + n_1_0_644), .B2(registers_1__ap[28]), .ZN(n_1_0_542)); + AOI22_X1_LVT i_1_0_570 (.A1(registers_12__ap[28]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[28]), .ZN(n_1_0_541)); + NAND4_X1_LVT i_1_0_569 (.A1(n_1_0_544), .A2(n_1_0_543), .A3(n_1_0_542), + .A4(n_1_0_541), .ZN(n_1_0_540)); + AOI22_X1_LVT i_1_0_568 (.A1(registers_13__ap[28]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[28]), .ZN(n_1_0_539)); + AOI22_X1_LVT i_1_0_567 (.A1(registers_17__ap[28]), .A2(n_1_0_629), .B1( + n_1_0_616), .B2(registers_6__ap[28]), .ZN(n_1_0_538)); + AOI22_X1_LVT i_1_0_566 (.A1(registers_10__ap[28]), .A2(n_1_0_624), .B1( + n_1_0_615), .B2(registers_23__ap[28]), .ZN(n_1_0_537)); + AOI22_X1_LVT i_1_0_565 (.A1(registers_18__ap[28]), .A2(n_1_0_646), .B1( + n_1_0_636), .B2(registers_27__ap[28]), .ZN(n_1_0_536)); + NAND4_X1_LVT i_1_0_564 (.A1(n_1_0_539), .A2(n_1_0_538), .A3(n_1_0_537), + .A4(n_1_0_536), .ZN(n_1_0_535)); + NOR3_X1_LVT i_1_0_563 (.A1(n_1_0_545), .A2(n_1_0_540), .A3(n_1_0_535), + .ZN(n_1_0_534)); + NAND4_X1_LVT i_1_0_562 (.A1(n_1_0_552), .A2(n_1_0_551), .A3(n_1_0_550), + .A4(n_1_0_534), .ZN(RRs2[28])); + AOI22_X1_LVT i_1_0_561 (.A1(registers_17__ap[27]), .A2(n_1_0_629), .B1( + n_1_0_612), .B2(registers_21__ap[27]), .ZN(n_1_0_533)); + AOI222_X1_LVT i_1_0_560 (.A1(registers_19__ap[27]), .A2(n_1_0_633), .B1( + n_1_0_631), .B2(registers_13__ap[27]), .C1(registers_30__ap[27]), .C2( + n_1_0_622), .ZN(n_1_0_532)); + AOI22_X1_LVT i_1_0_559 (.A1(registers_1__ap[27]), .A2(n_1_0_644), .B1( + n_1_0_634), .B2(registers_28__ap[27]), .ZN(n_1_0_531)); + AOI22_X1_LVT i_1_0_558 (.A1(registers_24__ap[27]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[27]), .ZN(n_1_0_530)); + AOI22_X1_LVT i_1_0_557 (.A1(registers_15__ap[27]), .A2(n_1_0_627), .B1( + n_1_0_611), .B2(registers_11__ap[27]), .ZN(n_1_0_529)); + AOI22_X1_LVT i_1_0_556 (.A1(registers_4__ap[27]), .A2(n_1_0_638), .B1( + n_1_0_636), .B2(registers_27__ap[27]), .ZN(n_1_0_528)); + AOI22_X1_LVT i_1_0_555 (.A1(registers_31__ap[27]), .A2(n_1_0_637), .B1( + n_1_0_618), .B2(registers_2__ap[27]), .ZN(n_1_0_527)); + NAND4_X1_LVT i_1_0_554 (.A1(n_1_0_530), .A2(n_1_0_529), .A3(n_1_0_528), + .A4(n_1_0_527), .ZN(n_1_0_526)); + AOI22_X1_LVT i_1_0_553 (.A1(registers_18__ap[27]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[27]), .ZN(n_1_0_525)); + AOI22_X1_LVT i_1_0_552 (.A1(registers_5__ap[27]), .A2(n_1_0_635), .B1( + n_1_0_632), .B2(registers_12__ap[27]), .ZN(n_1_0_524)); + AOI22_X1_LVT i_1_0_551 (.A1(registers_6__ap[27]), .A2(n_1_0_616), .B1( + n_1_0_614), .B2(registers_16__ap[27]), .ZN(n_1_0_523)); + AOI22_X1_LVT i_1_0_550 (.A1(registers_22__ap[27]), .A2(n_1_0_642), .B1( + n_1_0_620), .B2(registers_25__ap[27]), .ZN(n_1_0_522)); + NAND4_X1_LVT i_1_0_549 (.A1(n_1_0_525), .A2(n_1_0_524), .A3(n_1_0_523), + .A4(n_1_0_522), .ZN(n_1_0_521)); + AOI22_X1_LVT i_1_0_548 (.A1(registers_29__ap[27]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[27]), .ZN(n_1_0_520)); + AOI22_X1_LVT i_1_0_547 (.A1(registers_7__ap[27]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[27]), .ZN(n_1_0_519)); + AOI22_X1_LVT i_1_0_546 (.A1(registers_8__ap[27]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[27]), .ZN(n_1_0_518)); + AOI22_X1_LVT i_1_0_545 (.A1(registers_10__ap[27]), .A2(n_1_0_624), .B1( + n_1_0_610), .B2(registers_3__ap[27]), .ZN(n_1_0_517)); + NAND4_X1_LVT i_1_0_544 (.A1(n_1_0_520), .A2(n_1_0_519), .A3(n_1_0_518), + .A4(n_1_0_517), .ZN(n_1_0_516)); + NOR3_X1_LVT i_1_0_543 (.A1(n_1_0_526), .A2(n_1_0_521), .A3(n_1_0_516), + .ZN(n_1_0_515)); + NAND4_X1_LVT i_1_0_542 (.A1(n_1_0_533), .A2(n_1_0_532), .A3(n_1_0_531), + .A4(n_1_0_515), .ZN(RRs2[27])); + AOI22_X1_LVT i_1_0_541 (.A1(registers_17__ap[26]), .A2(n_1_0_629), .B1( + n_1_0_612), .B2(registers_21__ap[26]), .ZN(n_1_0_514)); + AOI222_X1_LVT i_1_0_540 (.A1(registers_19__ap[26]), .A2(n_1_0_633), .B1( + n_1_0_622), .B2(registers_30__ap[26]), .C1(n_1_0_631), .C2( + registers_13__ap[26]), .ZN(n_1_0_513)); + AOI22_X1_LVT i_1_0_539 (.A1(registers_1__ap[26]), .A2(n_1_0_644), .B1( + n_1_0_634), .B2(registers_28__ap[26]), .ZN(n_1_0_512)); + AOI22_X1_LVT i_1_0_538 (.A1(registers_24__ap[26]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[26]), .ZN(n_1_0_511)); + AOI22_X1_LVT i_1_0_537 (.A1(registers_15__ap[26]), .A2(n_1_0_627), .B1( + n_1_0_611), .B2(registers_11__ap[26]), .ZN(n_1_0_510)); + AOI22_X1_LVT i_1_0_536 (.A1(registers_4__ap[26]), .A2(n_1_0_638), .B1( + n_1_0_636), .B2(registers_27__ap[26]), .ZN(n_1_0_509)); + AOI22_X1_LVT i_1_0_535 (.A1(registers_31__ap[26]), .A2(n_1_0_637), .B1( + n_1_0_618), .B2(registers_2__ap[26]), .ZN(n_1_0_508)); + NAND4_X1_LVT i_1_0_534 (.A1(n_1_0_511), .A2(n_1_0_510), .A3(n_1_0_509), + .A4(n_1_0_508), .ZN(n_1_0_507)); + AOI22_X1_LVT i_1_0_533 (.A1(registers_18__ap[26]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[26]), .ZN(n_1_0_506)); + AOI22_X1_LVT i_1_0_532 (.A1(registers_5__ap[26]), .A2(n_1_0_635), .B1( + n_1_0_632), .B2(registers_12__ap[26]), .ZN(n_1_0_505)); + AOI22_X1_LVT i_1_0_531 (.A1(registers_6__ap[26]), .A2(n_1_0_616), .B1( + n_1_0_614), .B2(registers_16__ap[26]), .ZN(n_1_0_504)); + AOI22_X1_LVT i_1_0_530 (.A1(registers_22__ap[26]), .A2(n_1_0_642), .B1( + n_1_0_620), .B2(registers_25__ap[26]), .ZN(n_1_0_503)); + NAND4_X1_LVT i_1_0_529 (.A1(n_1_0_506), .A2(n_1_0_505), .A3(n_1_0_504), + .A4(n_1_0_503), .ZN(n_1_0_502)); + AOI22_X1_LVT i_1_0_528 (.A1(registers_29__ap[26]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[26]), .ZN(n_1_0_501)); + AOI22_X1_LVT i_1_0_527 (.A1(registers_7__ap[26]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[26]), .ZN(n_1_0_500)); + AOI22_X1_LVT i_1_0_526 (.A1(registers_8__ap[26]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[26]), .ZN(n_1_0_499)); + AOI22_X1_LVT i_1_0_525 (.A1(registers_10__ap[26]), .A2(n_1_0_624), .B1( + n_1_0_610), .B2(registers_3__ap[26]), .ZN(n_1_0_498)); + NAND4_X1_LVT i_1_0_524 (.A1(n_1_0_501), .A2(n_1_0_500), .A3(n_1_0_499), + .A4(n_1_0_498), .ZN(n_1_0_497)); + NOR3_X1_LVT i_1_0_523 (.A1(n_1_0_507), .A2(n_1_0_502), .A3(n_1_0_497), + .ZN(n_1_0_496)); + NAND4_X1_LVT i_1_0_522 (.A1(n_1_0_514), .A2(n_1_0_513), .A3(n_1_0_512), + .A4(n_1_0_496), .ZN(RRs2[26])); + AOI22_X1_LVT i_1_0_520 (.A1(registers_5__ap[25]), .A2(n_1_0_635), .B1( + n_1_0_634), .B2(registers_28__ap[25]), .ZN(n_1_0_494)); + AOI22_X1_LVT i_1_0_521 (.A1(registers_8__ap[25]), .A2(n_1_0_626), .B1( + n_1_0_620), .B2(registers_25__ap[25]), .ZN(n_1_0_495)); + AOI22_X1_LVT i_1_0_519 (.A1(registers_14__ap[25]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[25]), .ZN(n_1_0_493)); + AOI22_X1_LVT i_1_0_518 (.A1(registers_16__ap[25]), .A2(n_1_0_614), .B1( + n_1_0_611), .B2(registers_11__ap[25]), .ZN(n_1_0_492)); + NAND3_X1_LVT i_1_0_517 (.A1(n_1_0_495), .A2(n_1_0_493), .A3(n_1_0_492), + .ZN(n_1_0_491)); + AOI221_X1_LVT i_1_0_516 (.A(n_1_0_491), .B1(n_1_0_624), .B2( + registers_10__ap[25]), .C1(registers_6__ap[25]), .C2(n_1_0_616), .ZN( + n_1_0_490)); + AOI222_X1_LVT i_1_0_515 (.A1(registers_1__ap[25]), .A2(n_1_0_644), .B1( + n_1_0_640), .B2(registers_26__ap[25]), .C1(n_1_0_622), .C2( + registers_30__ap[25]), .ZN(n_1_0_489)); + NAND2_X1_LVT i_1_0_514 (.A1(n_1_0_490), .A2(n_1_0_489), .ZN(n_1_0_488)); + AOI221_X1_LVT i_1_0_513 (.A(n_1_0_488), .B1(n_1_0_649), .B2( + registers_29__ap[25]), .C1(registers_2__ap[25]), .C2(n_1_0_618), .ZN( + n_1_0_487)); + AOI22_X1_LVT i_1_0_512 (.A1(registers_12__ap[25]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[25]), .ZN(n_1_0_486)); + AOI22_X1_LVT i_1_0_511 (.A1(registers_22__ap[25]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[25]), .ZN(n_1_0_485)); + AOI22_X1_LVT i_1_0_510 (.A1(registers_4__ap[25]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[25]), .ZN(n_1_0_484)); + NAND3_X1_LVT i_1_0_509 (.A1(n_1_0_486), .A2(n_1_0_485), .A3(n_1_0_484), + .ZN(n_1_0_483)); + AOI221_X1_LVT i_1_0_508 (.A(n_1_0_483), .B1(n_1_0_633), .B2( + registers_19__ap[25]), .C1(registers_18__ap[25]), .C2(n_1_0_646), .ZN( + n_1_0_482)); + AOI22_X1_LVT i_1_0_507 (.A1(registers_15__ap[25]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[25]), .ZN(n_1_0_481)); + AOI22_X1_LVT i_1_0_506 (.A1(registers_23__ap[25]), .A2(n_1_0_615), .B1( + n_1_0_610), .B2(registers_3__ap[25]), .ZN(n_1_0_480)); + AOI22_X1_LVT i_1_0_505 (.A1(registers_13__ap[25]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[25]), .ZN(n_1_0_479)); + NAND3_X1_LVT i_1_0_504 (.A1(n_1_0_481), .A2(n_1_0_480), .A3(n_1_0_479), + .ZN(n_1_0_478)); + AOI221_X1_LVT i_1_0_503 (.A(n_1_0_478), .B1(n_1_0_636), .B2( + registers_27__ap[25]), .C1(registers_31__ap[25]), .C2(n_1_0_637), .ZN( + n_1_0_477)); + NAND4_X1_LVT i_1_0_502 (.A1(n_1_0_494), .A2(n_1_0_487), .A3(n_1_0_482), + .A4(n_1_0_477), .ZN(RRs2[25])); + AOI22_X1_LVT i_1_0_501 (.A1(registers_17__ap[24]), .A2(n_1_0_629), .B1( + n_1_0_612), .B2(registers_21__ap[24]), .ZN(n_1_0_476)); + AOI222_X1_LVT i_1_0_500 (.A1(registers_13__ap[24]), .A2(n_1_0_631), .B1( + n_1_0_622), .B2(registers_30__ap[24]), .C1(registers_26__ap[24]), .C2( + n_1_0_640), .ZN(n_1_0_475)); + AOI22_X1_LVT i_1_0_499 (.A1(registers_1__ap[24]), .A2(n_1_0_644), .B1( + n_1_0_634), .B2(registers_28__ap[24]), .ZN(n_1_0_474)); + AOI22_X1_LVT i_1_0_498 (.A1(registers_24__ap[24]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[24]), .ZN(n_1_0_473)); + AOI22_X1_LVT i_1_0_497 (.A1(registers_8__ap[24]), .A2(n_1_0_626), .B1( + n_1_0_616), .B2(registers_6__ap[24]), .ZN(n_1_0_472)); + AOI22_X1_LVT i_1_0_496 (.A1(registers_4__ap[24]), .A2(n_1_0_638), .B1( + n_1_0_611), .B2(registers_11__ap[24]), .ZN(n_1_0_471)); + AOI22_X1_LVT i_1_0_495 (.A1(registers_10__ap[24]), .A2(n_1_0_624), .B1( + n_1_0_618), .B2(registers_2__ap[24]), .ZN(n_1_0_470)); + NAND4_X1_LVT i_1_0_494 (.A1(n_1_0_473), .A2(n_1_0_472), .A3(n_1_0_471), + .A4(n_1_0_470), .ZN(n_1_0_469)); + AOI22_X1_LVT i_1_0_493 (.A1(registers_18__ap[24]), .A2(n_1_0_646), .B1( + n_1_0_633), .B2(registers_19__ap[24]), .ZN(n_1_0_468)); + AOI22_X1_LVT i_1_0_492 (.A1(registers_5__ap[24]), .A2(n_1_0_635), .B1( + n_1_0_632), .B2(registers_12__ap[24]), .ZN(n_1_0_467)); + AOI22_X1_LVT i_1_0_491 (.A1(registers_15__ap[24]), .A2(n_1_0_627), .B1( + n_1_0_614), .B2(registers_16__ap[24]), .ZN(n_1_0_466)); + AOI22_X1_LVT i_1_0_490 (.A1(registers_22__ap[24]), .A2(n_1_0_642), .B1( + n_1_0_620), .B2(registers_25__ap[24]), .ZN(n_1_0_465)); + NAND4_X1_LVT i_1_0_489 (.A1(n_1_0_468), .A2(n_1_0_467), .A3(n_1_0_466), + .A4(n_1_0_465), .ZN(n_1_0_464)); + AOI22_X1_LVT i_1_0_488 (.A1(registers_29__ap[24]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[24]), .ZN(n_1_0_463)); + AOI22_X1_LVT i_1_0_487 (.A1(registers_7__ap[24]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[24]), .ZN(n_1_0_462)); + AOI22_X1_LVT i_1_0_486 (.A1(registers_23__ap[24]), .A2(n_1_0_615), .B1( + n_1_0_610), .B2(registers_3__ap[24]), .ZN(n_1_0_461)); + AOI22_X1_LVT i_1_0_485 (.A1(registers_31__ap[24]), .A2(n_1_0_637), .B1( + n_1_0_636), .B2(registers_27__ap[24]), .ZN(n_1_0_460)); + NAND4_X1_LVT i_1_0_484 (.A1(n_1_0_463), .A2(n_1_0_462), .A3(n_1_0_461), + .A4(n_1_0_460), .ZN(n_1_0_459)); + NOR3_X1_LVT i_1_0_483 (.A1(n_1_0_469), .A2(n_1_0_464), .A3(n_1_0_459), + .ZN(n_1_0_458)); + NAND4_X1_LVT i_1_0_482 (.A1(n_1_0_476), .A2(n_1_0_475), .A3(n_1_0_474), + .A4(n_1_0_458), .ZN(RRs2[24])); + AOI22_X1_LVT i_1_0_481 (.A1(registers_4__ap[23]), .A2(n_1_0_638), .B1( + n_1_0_634), .B2(registers_28__ap[23]), .ZN(n_1_0_457)); + AOI222_X1_LVT i_1_0_480 (.A1(registers_18__ap[23]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[23]), .C1(n_1_0_644), .C2( + registers_1__ap[23]), .ZN(n_1_0_456)); + AOI22_X1_LVT i_1_0_479 (.A1(registers_29__ap[23]), .A2(n_1_0_649), .B1( + n_1_0_618), .B2(registers_2__ap[23]), .ZN(n_1_0_455)); + AOI22_X1_LVT i_1_0_478 (.A1(registers_14__ap[23]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[23]), .ZN(n_1_0_454)); + AOI22_X1_LVT i_1_0_477 (.A1(registers_16__ap[23]), .A2(n_1_0_614), .B1( + n_1_0_611), .B2(registers_11__ap[23]), .ZN(n_1_0_453)); + AOI22_X1_LVT i_1_0_476 (.A1(registers_27__ap[23]), .A2(n_1_0_636), .B1( + n_1_0_620), .B2(registers_25__ap[23]), .ZN(n_1_0_452)); + AOI22_X1_LVT i_1_0_475 (.A1(registers_31__ap[23]), .A2(n_1_0_637), .B1( + n_1_0_616), .B2(registers_6__ap[23]), .ZN(n_1_0_451)); + NAND4_X1_LVT i_1_0_474 (.A1(n_1_0_454), .A2(n_1_0_453), .A3(n_1_0_452), + .A4(n_1_0_451), .ZN(n_1_0_450)); + AOI22_X1_LVT i_1_0_473 (.A1(registers_26__ap[23]), .A2(n_1_0_640), .B1( + n_1_0_633), .B2(registers_19__ap[23]), .ZN(n_1_0_449)); + AOI22_X1_LVT i_1_0_472 (.A1(registers_12__ap[23]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[23]), .ZN(n_1_0_448)); + AOI22_X1_LVT i_1_0_471 (.A1(registers_22__ap[23]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[23]), .ZN(n_1_0_447)); + AOI22_X1_LVT i_1_0_470 (.A1(registers_5__ap[23]), .A2(n_1_0_635), .B1( + n_1_0_613), .B2(registers_20__ap[23]), .ZN(n_1_0_446)); + NAND4_X1_LVT i_1_0_469 (.A1(n_1_0_449), .A2(n_1_0_448), .A3(n_1_0_447), + .A4(n_1_0_446), .ZN(n_1_0_445)); + AOI22_X1_LVT i_1_0_468 (.A1(registers_15__ap[23]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[23]), .ZN(n_1_0_444)); + AOI22_X1_LVT i_1_0_467 (.A1(registers_8__ap[23]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[23]), .ZN(n_1_0_443)); + AOI22_X1_LVT i_1_0_466 (.A1(registers_13__ap[23]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[23]), .ZN(n_1_0_442)); + AOI22_X1_LVT i_1_0_465 (.A1(registers_10__ap[23]), .A2(n_1_0_624), .B1( + n_1_0_610), .B2(registers_3__ap[23]), .ZN(n_1_0_441)); + NAND4_X1_LVT i_1_0_464 (.A1(n_1_0_444), .A2(n_1_0_443), .A3(n_1_0_442), + .A4(n_1_0_441), .ZN(n_1_0_440)); + NOR3_X1_LVT i_1_0_463 (.A1(n_1_0_450), .A2(n_1_0_445), .A3(n_1_0_440), + .ZN(n_1_0_439)); + NAND4_X1_LVT i_1_0_462 (.A1(n_1_0_457), .A2(n_1_0_456), .A3(n_1_0_455), + .A4(n_1_0_439), .ZN(RRs2[23])); + AOI22_X1_LVT i_1_0_460 (.A1(registers_17__ap[22]), .A2(n_1_0_629), .B1( + n_1_0_612), .B2(registers_21__ap[22]), .ZN(n_1_0_437)); + AOI22_X1_LVT i_1_0_461 (.A1(registers_15__ap[22]), .A2(n_1_0_627), .B1( + n_1_0_626), .B2(registers_8__ap[22]), .ZN(n_1_0_438)); + AOI22_X1_LVT i_1_0_459 (.A1(registers_24__ap[22]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[22]), .ZN(n_1_0_436)); + AOI22_X1_LVT i_1_0_458 (.A1(registers_5__ap[22]), .A2(n_1_0_635), .B1( + n_1_0_611), .B2(registers_11__ap[22]), .ZN(n_1_0_435)); + NAND3_X1_LVT i_1_0_457 (.A1(n_1_0_438), .A2(n_1_0_436), .A3(n_1_0_435), + .ZN(n_1_0_434)); + AOI221_X1_LVT i_1_0_456 (.A(n_1_0_434), .B1(n_1_0_618), .B2( + registers_2__ap[22]), .C1(registers_10__ap[22]), .C2(n_1_0_624), .ZN( + n_1_0_433)); + AOI222_X1_LVT i_1_0_455 (.A1(registers_26__ap[22]), .A2(n_1_0_640), .B1( + n_1_0_622), .B2(registers_30__ap[22]), .C1(n_1_0_631), .C2( + registers_13__ap[22]), .ZN(n_1_0_432)); + NAND2_X1_LVT i_1_0_454 (.A1(n_1_0_433), .A2(n_1_0_432), .ZN(n_1_0_431)); + AOI221_X1_LVT i_1_0_453 (.A(n_1_0_431), .B1(n_1_0_644), .B2( + registers_1__ap[22]), .C1(registers_28__ap[22]), .C2(n_1_0_634), .ZN( + n_1_0_430)); + AOI22_X1_LVT i_1_0_452 (.A1(registers_18__ap[22]), .A2(n_1_0_646), .B1( + n_1_0_633), .B2(registers_19__ap[22]), .ZN(n_1_0_429)); + AOI22_X1_LVT i_1_0_451 (.A1(registers_4__ap[22]), .A2(n_1_0_638), .B1( + n_1_0_632), .B2(registers_12__ap[22]), .ZN(n_1_0_428)); + AOI22_X1_LVT i_1_0_450 (.A1(registers_6__ap[22]), .A2(n_1_0_616), .B1( + n_1_0_614), .B2(registers_16__ap[22]), .ZN(n_1_0_427)); + NAND3_X1_LVT i_1_0_449 (.A1(n_1_0_429), .A2(n_1_0_428), .A3(n_1_0_427), + .ZN(n_1_0_426)); + AOI221_X1_LVT i_1_0_448 (.A(n_1_0_426), .B1(n_1_0_620), .B2( + registers_25__ap[22]), .C1(registers_22__ap[22]), .C2(n_1_0_642), .ZN( + n_1_0_425)); + AOI22_X1_LVT i_1_0_447 (.A1(registers_29__ap[22]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[22]), .ZN(n_1_0_424)); + AOI22_X1_LVT i_1_0_446 (.A1(registers_7__ap[22]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[22]), .ZN(n_1_0_423)); + AOI22_X1_LVT i_1_0_445 (.A1(registers_23__ap[22]), .A2(n_1_0_615), .B1( + n_1_0_610), .B2(registers_3__ap[22]), .ZN(n_1_0_422)); + NAND3_X1_LVT i_1_0_444 (.A1(n_1_0_424), .A2(n_1_0_423), .A3(n_1_0_422), + .ZN(n_1_0_421)); + AOI221_X1_LVT i_1_0_443 (.A(n_1_0_421), .B1(n_1_0_636), .B2( + registers_27__ap[22]), .C1(registers_31__ap[22]), .C2(n_1_0_637), .ZN( + n_1_0_420)); + NAND4_X1_LVT i_1_0_442 (.A1(n_1_0_437), .A2(n_1_0_430), .A3(n_1_0_425), + .A4(n_1_0_420), .ZN(RRs2[22])); + AOI22_X1_LVT i_1_0_441 (.A1(registers_5__ap[21]), .A2(n_1_0_635), .B1( + n_1_0_634), .B2(registers_28__ap[21]), .ZN(n_1_0_419)); + AOI222_X1_LVT i_1_0_440 (.A1(registers_1__ap[21]), .A2(n_1_0_644), .B1( + n_1_0_640), .B2(registers_26__ap[21]), .C1(n_1_0_622), .C2( + registers_30__ap[21]), .ZN(n_1_0_418)); + AOI22_X1_LVT i_1_0_439 (.A1(registers_29__ap[21]), .A2(n_1_0_649), .B1( + n_1_0_618), .B2(registers_2__ap[21]), .ZN(n_1_0_417)); + AOI22_X1_LVT i_1_0_438 (.A1(registers_14__ap[21]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[21]), .ZN(n_1_0_416)); + AOI22_X1_LVT i_1_0_437 (.A1(registers_8__ap[21]), .A2(n_1_0_626), .B1( + n_1_0_614), .B2(registers_16__ap[21]), .ZN(n_1_0_415)); + AOI22_X1_LVT i_1_0_436 (.A1(registers_25__ap[21]), .A2(n_1_0_620), .B1( + n_1_0_611), .B2(registers_11__ap[21]), .ZN(n_1_0_414)); + AOI22_X1_LVT i_1_0_435 (.A1(registers_10__ap[21]), .A2(n_1_0_624), .B1( + n_1_0_616), .B2(registers_6__ap[21]), .ZN(n_1_0_413)); + NAND4_X1_LVT i_1_0_434 (.A1(n_1_0_416), .A2(n_1_0_415), .A3(n_1_0_414), + .A4(n_1_0_413), .ZN(n_1_0_412)); + AOI22_X1_LVT i_1_0_433 (.A1(registers_12__ap[21]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[21]), .ZN(n_1_0_411)); + AOI22_X1_LVT i_1_0_432 (.A1(registers_22__ap[21]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[21]), .ZN(n_1_0_410)); + AOI22_X1_LVT i_1_0_431 (.A1(registers_4__ap[21]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[21]), .ZN(n_1_0_409)); + AOI22_X1_LVT i_1_0_430 (.A1(registers_18__ap[21]), .A2(n_1_0_646), .B1( + n_1_0_633), .B2(registers_19__ap[21]), .ZN(n_1_0_408)); + NAND4_X1_LVT i_1_0_429 (.A1(n_1_0_411), .A2(n_1_0_410), .A3(n_1_0_409), + .A4(n_1_0_408), .ZN(n_1_0_407)); + AOI22_X1_LVT i_1_0_428 (.A1(registers_15__ap[21]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[21]), .ZN(n_1_0_406)); + AOI22_X1_LVT i_1_0_427 (.A1(registers_23__ap[21]), .A2(n_1_0_615), .B1( + n_1_0_610), .B2(registers_3__ap[21]), .ZN(n_1_0_405)); + AOI22_X1_LVT i_1_0_426 (.A1(registers_13__ap[21]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[21]), .ZN(n_1_0_404)); + AOI22_X1_LVT i_1_0_425 (.A1(registers_31__ap[21]), .A2(n_1_0_637), .B1( + n_1_0_636), .B2(registers_27__ap[21]), .ZN(n_1_0_403)); + NAND4_X1_LVT i_1_0_424 (.A1(n_1_0_406), .A2(n_1_0_405), .A3(n_1_0_404), + .A4(n_1_0_403), .ZN(n_1_0_402)); + NOR3_X1_LVT i_1_0_423 (.A1(n_1_0_412), .A2(n_1_0_407), .A3(n_1_0_402), + .ZN(n_1_0_401)); + NAND4_X1_LVT i_1_0_422 (.A1(n_1_0_419), .A2(n_1_0_418), .A3(n_1_0_417), + .A4(n_1_0_401), .ZN(RRs2[21])); + AOI22_X1_LVT i_1_0_421 (.A1(registers_17__ap[20]), .A2(n_1_0_629), .B1( + n_1_0_612), .B2(registers_21__ap[20]), .ZN(n_1_0_400)); + AOI222_X1_LVT i_1_0_420 (.A1(registers_13__ap[20]), .A2(n_1_0_631), .B1( + n_1_0_622), .B2(registers_30__ap[20]), .C1(registers_19__ap[20]), .C2( + n_1_0_633), .ZN(n_1_0_399)); + AOI22_X1_LVT i_1_0_419 (.A1(registers_1__ap[20]), .A2(n_1_0_644), .B1( + n_1_0_634), .B2(registers_28__ap[20]), .ZN(n_1_0_398)); + AOI22_X1_LVT i_1_0_418 (.A1(registers_24__ap[20]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[20]), .ZN(n_1_0_397)); + AOI22_X1_LVT i_1_0_417 (.A1(registers_6__ap[20]), .A2(n_1_0_616), .B1( + n_1_0_611), .B2(registers_11__ap[20]), .ZN(n_1_0_396)); + AOI22_X1_LVT i_1_0_416 (.A1(registers_4__ap[20]), .A2(n_1_0_638), .B1( + n_1_0_624), .B2(registers_10__ap[20]), .ZN(n_1_0_395)); + AOI22_X1_LVT i_1_0_415 (.A1(registers_31__ap[20]), .A2(n_1_0_637), .B1( + n_1_0_618), .B2(registers_2__ap[20]), .ZN(n_1_0_394)); + NAND4_X1_LVT i_1_0_414 (.A1(n_1_0_397), .A2(n_1_0_396), .A3(n_1_0_395), + .A4(n_1_0_394), .ZN(n_1_0_393)); + AOI22_X1_LVT i_1_0_413 (.A1(registers_18__ap[20]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[20]), .ZN(n_1_0_392)); + AOI22_X1_LVT i_1_0_412 (.A1(registers_5__ap[20]), .A2(n_1_0_635), .B1( + n_1_0_632), .B2(registers_12__ap[20]), .ZN(n_1_0_391)); + AOI22_X1_LVT i_1_0_411 (.A1(registers_15__ap[20]), .A2(n_1_0_627), .B1( + n_1_0_614), .B2(registers_16__ap[20]), .ZN(n_1_0_390)); + AOI22_X1_LVT i_1_0_410 (.A1(registers_22__ap[20]), .A2(n_1_0_642), .B1( + n_1_0_620), .B2(registers_25__ap[20]), .ZN(n_1_0_389)); + NAND4_X1_LVT i_1_0_409 (.A1(n_1_0_392), .A2(n_1_0_391), .A3(n_1_0_390), + .A4(n_1_0_389), .ZN(n_1_0_388)); + AOI22_X1_LVT i_1_0_408 (.A1(registers_29__ap[20]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[20]), .ZN(n_1_0_387)); + AOI22_X1_LVT i_1_0_407 (.A1(registers_7__ap[20]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[20]), .ZN(n_1_0_386)); + AOI22_X1_LVT i_1_0_406 (.A1(registers_8__ap[20]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[20]), .ZN(n_1_0_385)); + AOI22_X1_LVT i_1_0_405 (.A1(registers_27__ap[20]), .A2(n_1_0_636), .B1( + n_1_0_610), .B2(registers_3__ap[20]), .ZN(n_1_0_384)); + NAND4_X1_LVT i_1_0_404 (.A1(n_1_0_387), .A2(n_1_0_386), .A3(n_1_0_385), + .A4(n_1_0_384), .ZN(n_1_0_383)); + NOR3_X1_LVT i_1_0_403 (.A1(n_1_0_393), .A2(n_1_0_388), .A3(n_1_0_383), + .ZN(n_1_0_382)); + NAND4_X1_LVT i_1_0_402 (.A1(n_1_0_400), .A2(n_1_0_399), .A3(n_1_0_398), + .A4(n_1_0_382), .ZN(RRs2[20])); + AOI22_X1_LVT i_1_0_401 (.A1(registers_17__ap[19]), .A2(n_1_0_629), .B1( + n_1_0_612), .B2(registers_21__ap[19]), .ZN(n_1_0_381)); + AOI222_X1_LVT i_1_0_400 (.A1(registers_13__ap[19]), .A2(n_1_0_631), .B1( + n_1_0_622), .B2(registers_30__ap[19]), .C1(registers_19__ap[19]), .C2( + n_1_0_633), .ZN(n_1_0_380)); + AOI22_X1_LVT i_1_0_399 (.A1(registers_1__ap[19]), .A2(n_1_0_644), .B1( + n_1_0_634), .B2(registers_28__ap[19]), .ZN(n_1_0_379)); + AOI22_X1_LVT i_1_0_398 (.A1(registers_24__ap[19]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[19]), .ZN(n_1_0_378)); + AOI22_X1_LVT i_1_0_397 (.A1(registers_15__ap[19]), .A2(n_1_0_627), .B1( + n_1_0_611), .B2(registers_11__ap[19]), .ZN(n_1_0_377)); + AOI22_X1_LVT i_1_0_396 (.A1(registers_4__ap[19]), .A2(n_1_0_638), .B1( + n_1_0_636), .B2(registers_27__ap[19]), .ZN(n_1_0_376)); + AOI22_X1_LVT i_1_0_395 (.A1(registers_31__ap[19]), .A2(n_1_0_637), .B1( + n_1_0_618), .B2(registers_2__ap[19]), .ZN(n_1_0_375)); + NAND4_X1_LVT i_1_0_394 (.A1(n_1_0_378), .A2(n_1_0_377), .A3(n_1_0_376), + .A4(n_1_0_375), .ZN(n_1_0_374)); + AOI22_X1_LVT i_1_0_393 (.A1(registers_18__ap[19]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[19]), .ZN(n_1_0_373)); + AOI22_X1_LVT i_1_0_392 (.A1(registers_5__ap[19]), .A2(n_1_0_635), .B1( + n_1_0_632), .B2(registers_12__ap[19]), .ZN(n_1_0_372)); + AOI22_X1_LVT i_1_0_391 (.A1(registers_25__ap[19]), .A2(n_1_0_620), .B1( + n_1_0_616), .B2(registers_6__ap[19]), .ZN(n_1_0_371)); + AOI22_X1_LVT i_1_0_390 (.A1(registers_22__ap[19]), .A2(n_1_0_642), .B1( + n_1_0_614), .B2(registers_16__ap[19]), .ZN(n_1_0_370)); + NAND4_X1_LVT i_1_0_389 (.A1(n_1_0_373), .A2(n_1_0_372), .A3(n_1_0_371), + .A4(n_1_0_370), .ZN(n_1_0_369)); + AOI22_X1_LVT i_1_0_388 (.A1(registers_29__ap[19]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[19]), .ZN(n_1_0_368)); + AOI22_X1_LVT i_1_0_387 (.A1(registers_7__ap[19]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[19]), .ZN(n_1_0_367)); + AOI22_X1_LVT i_1_0_386 (.A1(registers_8__ap[19]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[19]), .ZN(n_1_0_366)); + AOI22_X1_LVT i_1_0_385 (.A1(registers_10__ap[19]), .A2(n_1_0_624), .B1( + n_1_0_610), .B2(registers_3__ap[19]), .ZN(n_1_0_365)); + NAND4_X1_LVT i_1_0_384 (.A1(n_1_0_368), .A2(n_1_0_367), .A3(n_1_0_366), + .A4(n_1_0_365), .ZN(n_1_0_364)); + NOR3_X1_LVT i_1_0_383 (.A1(n_1_0_374), .A2(n_1_0_369), .A3(n_1_0_364), + .ZN(n_1_0_363)); + NAND4_X1_LVT i_1_0_382 (.A1(n_1_0_381), .A2(n_1_0_380), .A3(n_1_0_379), + .A4(n_1_0_363), .ZN(RRs2[19])); + AOI22_X1_LVT i_1_0_380 (.A1(registers_4__ap[18]), .A2(n_1_0_638), .B1( + n_1_0_634), .B2(registers_28__ap[18]), .ZN(n_1_0_361)); + AOI22_X1_LVT i_1_0_381 (.A1(registers_8__ap[18]), .A2(n_1_0_626), .B1( + n_1_0_614), .B2(registers_16__ap[18]), .ZN(n_1_0_362)); + AOI22_X1_LVT i_1_0_379 (.A1(registers_14__ap[18]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[18]), .ZN(n_1_0_360)); + AOI22_X1_LVT i_1_0_378 (.A1(registers_25__ap[18]), .A2(n_1_0_620), .B1( + n_1_0_611), .B2(registers_11__ap[18]), .ZN(n_1_0_359)); + NAND3_X1_LVT i_1_0_377 (.A1(n_1_0_362), .A2(n_1_0_360), .A3(n_1_0_359), + .ZN(n_1_0_358)); + AOI221_X1_LVT i_1_0_376 (.A(n_1_0_358), .B1(n_1_0_624), .B2( + registers_10__ap[18]), .C1(registers_6__ap[18]), .C2(n_1_0_616), .ZN( + n_1_0_357)); + AOI222_X1_LVT i_1_0_375 (.A1(registers_1__ap[18]), .A2(n_1_0_644), .B1( + n_1_0_640), .B2(registers_26__ap[18]), .C1(n_1_0_622), .C2( + registers_30__ap[18]), .ZN(n_1_0_356)); + NAND2_X1_LVT i_1_0_374 (.A1(n_1_0_357), .A2(n_1_0_356), .ZN(n_1_0_355)); + AOI221_X1_LVT i_1_0_373 (.A(n_1_0_355), .B1(n_1_0_649), .B2( + registers_29__ap[18]), .C1(registers_2__ap[18]), .C2(n_1_0_618), .ZN( + n_1_0_354)); + AOI22_X1_LVT i_1_0_372 (.A1(registers_18__ap[18]), .A2(n_1_0_646), .B1( + n_1_0_633), .B2(registers_19__ap[18]), .ZN(n_1_0_353)); + AOI22_X1_LVT i_1_0_371 (.A1(registers_12__ap[18]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[18]), .ZN(n_1_0_352)); + AOI22_X1_LVT i_1_0_370 (.A1(registers_22__ap[18]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[18]), .ZN(n_1_0_351)); + NAND3_X1_LVT i_1_0_369 (.A1(n_1_0_353), .A2(n_1_0_352), .A3(n_1_0_351), + .ZN(n_1_0_350)); + AOI221_X1_LVT i_1_0_368 (.A(n_1_0_350), .B1(n_1_0_635), .B2( + registers_5__ap[18]), .C1(registers_20__ap[18]), .C2(n_1_0_613), .ZN( + n_1_0_349)); + AOI22_X1_LVT i_1_0_367 (.A1(registers_15__ap[18]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[18]), .ZN(n_1_0_348)); + AOI22_X1_LVT i_1_0_366 (.A1(registers_23__ap[18]), .A2(n_1_0_615), .B1( + n_1_0_610), .B2(registers_3__ap[18]), .ZN(n_1_0_347)); + AOI22_X1_LVT i_1_0_365 (.A1(registers_13__ap[18]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[18]), .ZN(n_1_0_346)); + NAND3_X1_LVT i_1_0_364 (.A1(n_1_0_348), .A2(n_1_0_347), .A3(n_1_0_346), + .ZN(n_1_0_345)); + AOI221_X1_LVT i_1_0_363 (.A(n_1_0_345), .B1(n_1_0_637), .B2( + registers_31__ap[18]), .C1(registers_27__ap[18]), .C2(n_1_0_636), .ZN( + n_1_0_344)); + NAND4_X1_LVT i_1_0_362 (.A1(n_1_0_361), .A2(n_1_0_354), .A3(n_1_0_349), + .A4(n_1_0_344), .ZN(RRs2[18])); + AOI22_X1_LVT i_1_0_358 (.A1(registers_4__ap[17]), .A2(n_1_0_638), .B1( + n_1_0_634), .B2(registers_28__ap[17]), .ZN(n_1_0_340)); + AOI22_X1_LVT i_1_0_361 (.A1(registers_31__ap[17]), .A2(n_1_0_637), .B1( + n_1_0_616), .B2(registers_6__ap[17]), .ZN(n_1_0_343)); + AOI22_X1_LVT i_1_0_357 (.A1(registers_14__ap[17]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[17]), .ZN(n_1_0_339)); + AOI22_X1_LVT i_1_0_360 (.A1(registers_25__ap[17]), .A2(n_1_0_620), .B1( + n_1_0_611), .B2(registers_11__ap[17]), .ZN(n_1_0_342)); + INV_X1_LVT i_1_0_359 (.A(n_1_0_342), .ZN(n_1_0_341)); + AOI221_X1_LVT i_1_0_356 (.A(n_1_0_341), .B1(n_1_0_614), .B2( + registers_16__ap[17]), .C1(registers_10__ap[17]), .C2(n_1_0_624), .ZN( + n_1_0_338)); + AOI222_X1_LVT i_1_0_355 (.A1(registers_1__ap[17]), .A2(n_1_0_644), .B1( + n_1_0_622), .B2(registers_30__ap[17]), .C1(registers_18__ap[17]), .C2( + n_1_0_646), .ZN(n_1_0_337)); + NAND4_X1_LVT i_1_0_354 (.A1(n_1_0_343), .A2(n_1_0_339), .A3(n_1_0_338), + .A4(n_1_0_337), .ZN(n_1_0_336)); + AOI221_X1_LVT i_1_0_353 (.A(n_1_0_336), .B1(n_1_0_649), .B2( + registers_29__ap[17]), .C1(registers_2__ap[17]), .C2(n_1_0_618), .ZN( + n_1_0_335)); + AOI22_X1_LVT i_1_0_352 (.A1(registers_26__ap[17]), .A2(n_1_0_640), .B1( + n_1_0_633), .B2(registers_19__ap[17]), .ZN(n_1_0_334)); + AOI22_X1_LVT i_1_0_351 (.A1(registers_12__ap[17]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[17]), .ZN(n_1_0_333)); + AOI22_X1_LVT i_1_0_350 (.A1(registers_22__ap[17]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[17]), .ZN(n_1_0_332)); + NAND3_X1_LVT i_1_0_349 (.A1(n_1_0_334), .A2(n_1_0_333), .A3(n_1_0_332), + .ZN(n_1_0_331)); + AOI221_X1_LVT i_1_0_348 (.A(n_1_0_331), .B1(n_1_0_635), .B2( + registers_5__ap[17]), .C1(registers_20__ap[17]), .C2(n_1_0_613), .ZN( + n_1_0_330)); + AOI22_X1_LVT i_1_0_347 (.A1(registers_15__ap[17]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[17]), .ZN(n_1_0_329)); + AOI22_X1_LVT i_1_0_346 (.A1(registers_8__ap[17]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[17]), .ZN(n_1_0_328)); + AOI22_X1_LVT i_1_0_345 (.A1(registers_13__ap[17]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[17]), .ZN(n_1_0_327)); + NAND3_X1_LVT i_1_0_344 (.A1(n_1_0_329), .A2(n_1_0_328), .A3(n_1_0_327), + .ZN(n_1_0_326)); + AOI221_X1_LVT i_1_0_343 (.A(n_1_0_326), .B1(n_1_0_636), .B2( + registers_27__ap[17]), .C1(registers_3__ap[17]), .C2(n_1_0_610), .ZN( + n_1_0_325)); + NAND4_X1_LVT i_1_0_342 (.A1(n_1_0_340), .A2(n_1_0_335), .A3(n_1_0_330), + .A4(n_1_0_325), .ZN(RRs2[17])); + AOI22_X1_LVT i_1_0_341 (.A1(registers_4__ap[16]), .A2(n_1_0_638), .B1( + n_1_0_634), .B2(registers_28__ap[16]), .ZN(n_1_0_324)); + AOI222_X1_LVT i_1_0_340 (.A1(registers_1__ap[16]), .A2(n_1_0_644), .B1( + n_1_0_633), .B2(registers_19__ap[16]), .C1(n_1_0_622), .C2( + registers_30__ap[16]), .ZN(n_1_0_323)); + AOI22_X1_LVT i_1_0_339 (.A1(registers_29__ap[16]), .A2(n_1_0_649), .B1( + n_1_0_618), .B2(registers_2__ap[16]), .ZN(n_1_0_322)); + AOI22_X1_LVT i_1_0_338 (.A1(registers_14__ap[16]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[16]), .ZN(n_1_0_321)); + AOI22_X1_LVT i_1_0_337 (.A1(registers_16__ap[16]), .A2(n_1_0_614), .B1( + n_1_0_611), .B2(registers_11__ap[16]), .ZN(n_1_0_320)); + AOI22_X1_LVT i_1_0_336 (.A1(registers_10__ap[16]), .A2(n_1_0_624), .B1( + n_1_0_620), .B2(registers_25__ap[16]), .ZN(n_1_0_319)); + AOI22_X1_LVT i_1_0_335 (.A1(registers_31__ap[16]), .A2(n_1_0_637), .B1( + n_1_0_616), .B2(registers_6__ap[16]), .ZN(n_1_0_318)); + NAND4_X1_LVT i_1_0_334 (.A1(n_1_0_321), .A2(n_1_0_320), .A3(n_1_0_319), + .A4(n_1_0_318), .ZN(n_1_0_317)); + AOI22_X1_LVT i_1_0_333 (.A1(registers_18__ap[16]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[16]), .ZN(n_1_0_316)); + AOI22_X1_LVT i_1_0_332 (.A1(registers_12__ap[16]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[16]), .ZN(n_1_0_315)); + AOI22_X1_LVT i_1_0_331 (.A1(registers_22__ap[16]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[16]), .ZN(n_1_0_314)); + AOI22_X1_LVT i_1_0_330 (.A1(registers_5__ap[16]), .A2(n_1_0_635), .B1( + n_1_0_613), .B2(registers_20__ap[16]), .ZN(n_1_0_313)); + NAND4_X1_LVT i_1_0_329 (.A1(n_1_0_316), .A2(n_1_0_315), .A3(n_1_0_314), + .A4(n_1_0_313), .ZN(n_1_0_312)); + AOI22_X1_LVT i_1_0_328 (.A1(registers_15__ap[16]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[16]), .ZN(n_1_0_311)); + AOI22_X1_LVT i_1_0_327 (.A1(registers_8__ap[16]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[16]), .ZN(n_1_0_310)); + AOI22_X1_LVT i_1_0_326 (.A1(registers_13__ap[16]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[16]), .ZN(n_1_0_309)); + AOI22_X1_LVT i_1_0_325 (.A1(registers_27__ap[16]), .A2(n_1_0_636), .B1( + n_1_0_610), .B2(registers_3__ap[16]), .ZN(n_1_0_308)); + NAND4_X1_LVT i_1_0_324 (.A1(n_1_0_311), .A2(n_1_0_310), .A3(n_1_0_309), + .A4(n_1_0_308), .ZN(n_1_0_307)); + NOR3_X1_LVT i_1_0_323 (.A1(n_1_0_317), .A2(n_1_0_312), .A3(n_1_0_307), + .ZN(n_1_0_306)); + NAND4_X1_LVT i_1_0_322 (.A1(n_1_0_324), .A2(n_1_0_323), .A3(n_1_0_322), + .A4(n_1_0_306), .ZN(RRs2[16])); + AOI22_X1_LVT i_1_0_320 (.A1(registers_5__ap[15]), .A2(n_1_0_635), .B1( + n_1_0_634), .B2(registers_28__ap[15]), .ZN(n_1_0_304)); + AOI22_X1_LVT i_1_0_321 (.A1(registers_8__ap[15]), .A2(n_1_0_626), .B1( + n_1_0_620), .B2(registers_25__ap[15]), .ZN(n_1_0_305)); + AOI22_X1_LVT i_1_0_319 (.A1(registers_14__ap[15]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[15]), .ZN(n_1_0_303)); + AOI22_X1_LVT i_1_0_318 (.A1(registers_16__ap[15]), .A2(n_1_0_614), .B1( + n_1_0_611), .B2(registers_11__ap[15]), .ZN(n_1_0_302)); + NAND3_X1_LVT i_1_0_317 (.A1(n_1_0_305), .A2(n_1_0_303), .A3(n_1_0_302), + .ZN(n_1_0_301)); + AOI221_X1_LVT i_1_0_316 (.A(n_1_0_301), .B1(n_1_0_616), .B2( + registers_6__ap[15]), .C1(registers_10__ap[15]), .C2(n_1_0_624), .ZN( + n_1_0_300)); + AOI222_X1_LVT i_1_0_315 (.A1(registers_1__ap[15]), .A2(n_1_0_644), .B1( + n_1_0_640), .B2(registers_26__ap[15]), .C1(n_1_0_622), .C2( + registers_30__ap[15]), .ZN(n_1_0_299)); + NAND2_X1_LVT i_1_0_314 (.A1(n_1_0_300), .A2(n_1_0_299), .ZN(n_1_0_298)); + AOI221_X1_LVT i_1_0_313 (.A(n_1_0_298), .B1(n_1_0_649), .B2( + registers_29__ap[15]), .C1(registers_2__ap[15]), .C2(n_1_0_618), .ZN( + n_1_0_297)); + AOI22_X1_LVT i_1_0_312 (.A1(registers_12__ap[15]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[15]), .ZN(n_1_0_296)); + AOI22_X1_LVT i_1_0_311 (.A1(registers_22__ap[15]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[15]), .ZN(n_1_0_295)); + AOI22_X1_LVT i_1_0_310 (.A1(registers_4__ap[15]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[15]), .ZN(n_1_0_294)); + NAND3_X1_LVT i_1_0_309 (.A1(n_1_0_296), .A2(n_1_0_295), .A3(n_1_0_294), + .ZN(n_1_0_293)); + AOI221_X1_LVT i_1_0_308 (.A(n_1_0_293), .B1(n_1_0_633), .B2( + registers_19__ap[15]), .C1(registers_18__ap[15]), .C2(n_1_0_646), .ZN( + n_1_0_292)); + AOI22_X1_LVT i_1_0_307 (.A1(registers_15__ap[15]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[15]), .ZN(n_1_0_291)); + AOI22_X1_LVT i_1_0_306 (.A1(registers_23__ap[15]), .A2(n_1_0_615), .B1( + n_1_0_610), .B2(registers_3__ap[15]), .ZN(n_1_0_290)); + AOI22_X1_LVT i_1_0_305 (.A1(registers_13__ap[15]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[15]), .ZN(n_1_0_289)); + NAND3_X1_LVT i_1_0_304 (.A1(n_1_0_291), .A2(n_1_0_290), .A3(n_1_0_289), + .ZN(n_1_0_288)); + AOI221_X1_LVT i_1_0_303 (.A(n_1_0_288), .B1(n_1_0_636), .B2( + registers_27__ap[15]), .C1(registers_31__ap[15]), .C2(n_1_0_637), .ZN( + n_1_0_287)); + NAND4_X1_LVT i_1_0_302 (.A1(n_1_0_304), .A2(n_1_0_297), .A3(n_1_0_292), + .A4(n_1_0_287), .ZN(RRs2[15])); + AOI22_X1_LVT i_1_0_301 (.A1(registers_28__ap[14]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[14]), .ZN(n_1_0_286)); + AOI222_X1_LVT i_1_0_300 (.A1(registers_18__ap[14]), .A2(n_1_0_646), .B1( + n_1_0_620), .B2(registers_25__ap[14]), .C1(n_1_0_618), .C2( + registers_2__ap[14]), .ZN(n_1_0_285)); + AOI22_X1_LVT i_1_0_299 (.A1(registers_24__ap[14]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[14]), .ZN(n_1_0_284)); + AOI22_X1_LVT i_1_0_298 (.A1(registers_15__ap[14]), .A2(n_1_0_627), .B1( + n_1_0_610), .B2(registers_3__ap[14]), .ZN(n_1_0_283)); + AOI22_X1_LVT i_1_0_297 (.A1(registers_4__ap[14]), .A2(n_1_0_638), .B1( + n_1_0_637), .B2(registers_31__ap[14]), .ZN(n_1_0_282)); + AOI22_X1_LVT i_1_0_296 (.A1(registers_29__ap[14]), .A2(n_1_0_649), .B1( + n_1_0_615), .B2(registers_23__ap[14]), .ZN(n_1_0_281)); + NAND4_X1_LVT i_1_0_295 (.A1(n_1_0_284), .A2(n_1_0_283), .A3(n_1_0_282), + .A4(n_1_0_281), .ZN(n_1_0_280)); + AOI221_X1_LVT i_1_0_294 (.A(n_1_0_280), .B1(n_1_0_644), .B2( + registers_1__ap[14]), .C1(registers_13__ap[14]), .C2(n_1_0_631), .ZN( + n_1_0_279)); + AOI22_X1_LVT i_1_0_293 (.A1(registers_17__ap[14]), .A2(n_1_0_629), .B1( + n_1_0_623), .B2(registers_7__ap[14]), .ZN(n_1_0_278)); + AOI22_X1_LVT i_1_0_292 (.A1(registers_5__ap[14]), .A2(n_1_0_635), .B1( + n_1_0_632), .B2(registers_12__ap[14]), .ZN(n_1_0_277)); + AOI22_X1_LVT i_1_0_291 (.A1(registers_10__ap[14]), .A2(n_1_0_624), .B1( + n_1_0_622), .B2(registers_30__ap[14]), .ZN(n_1_0_276)); + AOI22_X1_LVT i_1_0_290 (.A1(registers_26__ap[14]), .A2(n_1_0_640), .B1( + n_1_0_614), .B2(registers_16__ap[14]), .ZN(n_1_0_275)); + NAND4_X1_LVT i_1_0_289 (.A1(n_1_0_278), .A2(n_1_0_277), .A3(n_1_0_276), + .A4(n_1_0_275), .ZN(n_1_0_274)); + AOI22_X1_LVT i_1_0_288 (.A1(registers_9__ap[14]), .A2(n_1_0_617), .B1( + n_1_0_612), .B2(registers_21__ap[14]), .ZN(n_1_0_273)); + AOI22_X1_LVT i_1_0_287 (.A1(registers_14__ap[14]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[14]), .ZN(n_1_0_272)); + AOI22_X1_LVT i_1_0_286 (.A1(registers_22__ap[14]), .A2(n_1_0_642), .B1( + n_1_0_633), .B2(registers_19__ap[14]), .ZN(n_1_0_271)); + AOI22_X1_LVT i_1_0_285 (.A1(registers_27__ap[14]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[14]), .ZN(n_1_0_270)); + NAND4_X1_LVT i_1_0_284 (.A1(n_1_0_273), .A2(n_1_0_272), .A3(n_1_0_271), + .A4(n_1_0_270), .ZN(n_1_0_269)); + NOR2_X1_LVT i_1_0_283 (.A1(n_1_0_274), .A2(n_1_0_269), .ZN(n_1_0_268)); + NAND4_X1_LVT i_1_0_282 (.A1(n_1_0_286), .A2(n_1_0_285), .A3(n_1_0_279), + .A4(n_1_0_268), .ZN(RRs2[14])); + AOI22_X1_LVT i_1_0_281 (.A1(registers_18__ap[13]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[13]), .ZN(n_1_0_267)); + AOI22_X1_LVT i_1_0_280 (.A1(registers_12__ap[13]), .A2(n_1_0_632), .B1( + n_1_0_629), .B2(registers_17__ap[13]), .ZN(n_1_0_266)); + AOI22_X1_LVT i_1_0_279 (.A1(registers_7__ap[13]), .A2(n_1_0_623), .B1( + n_1_0_614), .B2(registers_16__ap[13]), .ZN(n_1_0_265)); + NAND3_X1_LVT i_1_0_277 (.A1(n_1_0_267), .A2(n_1_0_266), .A3(n_1_0_265), + .ZN(n_1_0_263)); + AOI221_X1_LVT i_1_0_276 (.A(n_1_0_263), .B1(n_1_0_642), .B2( + registers_22__ap[13]), .C1(registers_5__ap[13]), .C2(n_1_0_635), .ZN( + n_1_0_262)); + AOI22_X1_LVT i_1_0_278 (.A1(registers_13__ap[13]), .A2(n_1_0_631), .B1( + n_1_0_612), .B2(registers_21__ap[13]), .ZN(n_1_0_264)); + AOI222_X1_LVT i_1_0_275 (.A1(registers_26__ap[13]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[13]), .C1(n_1_0_620), .C2( + registers_25__ap[13]), .ZN(n_1_0_261)); + AOI22_X1_LVT i_1_0_274 (.A1(registers_28__ap[13]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[13]), .ZN(n_1_0_260)); + NAND3_X1_LVT i_1_0_273 (.A1(n_1_0_264), .A2(n_1_0_261), .A3(n_1_0_260), + .ZN(n_1_0_259)); + AOI22_X1_LVT i_1_0_272 (.A1(registers_1__ap[13]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[13]), .ZN(n_1_0_258)); + AOI22_X1_LVT i_1_0_271 (.A1(registers_19__ap[13]), .A2(n_1_0_633), .B1( + n_1_0_618), .B2(registers_2__ap[13]), .ZN(n_1_0_257)); + AOI22_X1_LVT i_1_0_270 (.A1(registers_14__ap[13]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[13]), .ZN(n_1_0_256)); + AOI22_X1_LVT i_1_0_269 (.A1(registers_27__ap[13]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[13]), .ZN(n_1_0_255)); + NAND4_X1_LVT i_1_0_268 (.A1(n_1_0_258), .A2(n_1_0_257), .A3(n_1_0_256), + .A4(n_1_0_255), .ZN(n_1_0_254)); + AOI22_X1_LVT i_1_0_267 (.A1(registers_24__ap[13]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[13]), .ZN(n_1_0_253)); + AOI22_X1_LVT i_1_0_266 (.A1(registers_4__ap[13]), .A2(n_1_0_638), .B1( + n_1_0_637), .B2(registers_31__ap[13]), .ZN(n_1_0_252)); + AOI22_X1_LVT i_1_0_265 (.A1(registers_29__ap[13]), .A2(n_1_0_649), .B1( + n_1_0_615), .B2(registers_23__ap[13]), .ZN(n_1_0_251)); + AOI22_X1_LVT i_1_0_264 (.A1(registers_15__ap[13]), .A2(n_1_0_627), .B1( + n_1_0_610), .B2(registers_3__ap[13]), .ZN(n_1_0_250)); + NAND4_X1_LVT i_1_0_263 (.A1(n_1_0_253), .A2(n_1_0_252), .A3(n_1_0_251), + .A4(n_1_0_250), .ZN(n_1_0_249)); + NOR3_X1_LVT i_1_0_262 (.A1(n_1_0_259), .A2(n_1_0_254), .A3(n_1_0_249), + .ZN(n_1_0_248)); + NAND2_X1_LVT i_1_0_261 (.A1(n_1_0_262), .A2(n_1_0_248), .ZN(RRs2[13])); + AOI22_X1_LVT i_1_0_260 (.A1(registers_18__ap[12]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[12]), .ZN(n_1_0_247)); + AOI22_X1_LVT i_1_0_259 (.A1(registers_12__ap[12]), .A2(n_1_0_632), .B1( + n_1_0_629), .B2(registers_17__ap[12]), .ZN(n_1_0_246)); + AOI22_X1_LVT i_1_0_258 (.A1(registers_5__ap[12]), .A2(n_1_0_635), .B1( + n_1_0_623), .B2(registers_7__ap[12]), .ZN(n_1_0_245)); + NAND3_X1_LVT i_1_0_256 (.A1(n_1_0_247), .A2(n_1_0_246), .A3(n_1_0_245), + .ZN(n_1_0_243)); + AOI221_X1_LVT i_1_0_255 (.A(n_1_0_243), .B1(n_1_0_642), .B2( + registers_22__ap[12]), .C1(registers_16__ap[12]), .C2(n_1_0_614), .ZN( + n_1_0_242)); + AOI22_X1_LVT i_1_0_257 (.A1(registers_13__ap[12]), .A2(n_1_0_631), .B1( + n_1_0_612), .B2(registers_21__ap[12]), .ZN(n_1_0_244)); + AOI222_X1_LVT i_1_0_254 (.A1(registers_26__ap[12]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[12]), .C1(n_1_0_620), .C2( + registers_25__ap[12]), .ZN(n_1_0_241)); + AOI22_X1_LVT i_1_0_253 (.A1(registers_28__ap[12]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[12]), .ZN(n_1_0_240)); + NAND3_X1_LVT i_1_0_252 (.A1(n_1_0_244), .A2(n_1_0_241), .A3(n_1_0_240), + .ZN(n_1_0_239)); + AOI22_X1_LVT i_1_0_251 (.A1(registers_1__ap[12]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[12]), .ZN(n_1_0_238)); + AOI22_X1_LVT i_1_0_250 (.A1(registers_19__ap[12]), .A2(n_1_0_633), .B1( + n_1_0_618), .B2(registers_2__ap[12]), .ZN(n_1_0_237)); + AOI22_X1_LVT i_1_0_249 (.A1(registers_14__ap[12]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[12]), .ZN(n_1_0_236)); + AOI22_X1_LVT i_1_0_248 (.A1(registers_27__ap[12]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[12]), .ZN(n_1_0_235)); + NAND4_X1_LVT i_1_0_247 (.A1(n_1_0_238), .A2(n_1_0_237), .A3(n_1_0_236), + .A4(n_1_0_235), .ZN(n_1_0_234)); + AOI22_X1_LVT i_1_0_246 (.A1(registers_24__ap[12]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[12]), .ZN(n_1_0_233)); + AOI22_X1_LVT i_1_0_245 (.A1(registers_4__ap[12]), .A2(n_1_0_638), .B1( + n_1_0_637), .B2(registers_31__ap[12]), .ZN(n_1_0_232)); + AOI22_X1_LVT i_1_0_244 (.A1(registers_29__ap[12]), .A2(n_1_0_649), .B1( + n_1_0_615), .B2(registers_23__ap[12]), .ZN(n_1_0_231)); + AOI22_X1_LVT i_1_0_243 (.A1(registers_15__ap[12]), .A2(n_1_0_627), .B1( + n_1_0_610), .B2(registers_3__ap[12]), .ZN(n_1_0_230)); + NAND4_X1_LVT i_1_0_242 (.A1(n_1_0_233), .A2(n_1_0_232), .A3(n_1_0_231), + .A4(n_1_0_230), .ZN(n_1_0_229)); + NOR3_X1_LVT i_1_0_241 (.A1(n_1_0_239), .A2(n_1_0_234), .A3(n_1_0_229), + .ZN(n_1_0_228)); + NAND2_X1_LVT i_1_0_240 (.A1(n_1_0_242), .A2(n_1_0_228), .ZN(RRs2[12])); + AOI22_X1_LVT i_1_0_238 (.A1(registers_29__ap[11]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[11]), .ZN(n_1_0_226)); + AOI22_X1_LVT i_1_0_239 (.A1(registers_27__ap[11]), .A2(n_1_0_636), .B1( + n_1_0_627), .B2(registers_15__ap[11]), .ZN(n_1_0_227)); + AOI22_X1_LVT i_1_0_237 (.A1(registers_1__ap[11]), .A2(n_1_0_644), .B1( + n_1_0_616), .B2(registers_6__ap[11]), .ZN(n_1_0_225)); + AOI22_X1_LVT i_1_0_236 (.A1(registers_5__ap[11]), .A2(n_1_0_635), .B1( + n_1_0_615), .B2(registers_23__ap[11]), .ZN(n_1_0_224)); + NAND3_X1_LVT i_1_0_235 (.A1(n_1_0_227), .A2(n_1_0_225), .A3(n_1_0_224), + .ZN(n_1_0_223)); + AOI221_X1_LVT i_1_0_234 (.A(n_1_0_223), .B1(n_1_0_637), .B2( + registers_31__ap[11]), .C1(registers_16__ap[11]), .C2(n_1_0_614), .ZN( + n_1_0_222)); + AOI222_X1_LVT i_1_0_233 (.A1(registers_8__ap[11]), .A2(n_1_0_626), .B1( + n_1_0_624), .B2(registers_10__ap[11]), .C1(n_1_0_622), .C2( + registers_30__ap[11]), .ZN(n_1_0_221)); + NAND3_X1_LVT i_1_0_232 (.A1(n_1_0_226), .A2(n_1_0_222), .A3(n_1_0_221), + .ZN(n_1_0_220)); + AOI221_X1_LVT i_1_0_231 (.A(n_1_0_220), .B1(n_1_0_638), .B2( + registers_4__ap[11]), .C1(registers_28__ap[11]), .C2(n_1_0_634), .ZN( + n_1_0_219)); + AOI22_X1_LVT i_1_0_230 (.A1(registers_18__ap[11]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[11]), .ZN(n_1_0_218)); + AOI22_X1_LVT i_1_0_229 (.A1(registers_12__ap[11]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[11]), .ZN(n_1_0_217)); + AOI22_X1_LVT i_1_0_228 (.A1(registers_22__ap[11]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[11]), .ZN(n_1_0_216)); + NAND3_X1_LVT i_1_0_227 (.A1(n_1_0_218), .A2(n_1_0_217), .A3(n_1_0_216), + .ZN(n_1_0_215)); + AOI221_X1_LVT i_1_0_226 (.A(n_1_0_215), .B1(n_1_0_613), .B2( + registers_20__ap[11]), .C1(registers_17__ap[11]), .C2(n_1_0_629), .ZN( + n_1_0_214)); + AOI22_X1_LVT i_1_0_225 (.A1(registers_13__ap[11]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[11]), .ZN(n_1_0_213)); + AOI22_X1_LVT i_1_0_224 (.A1(registers_7__ap[11]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[11]), .ZN(n_1_0_212)); + AOI22_X1_LVT i_1_0_223 (.A1(registers_19__ap[11]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[11]), .ZN(n_1_0_211)); + NAND3_X1_LVT i_1_0_222 (.A1(n_1_0_213), .A2(n_1_0_212), .A3(n_1_0_211), + .ZN(n_1_0_210)); + AOI221_X1_LVT i_1_0_221 (.A(n_1_0_210), .B1(n_1_0_611), .B2( + registers_11__ap[11]), .C1(registers_2__ap[11]), .C2(n_1_0_618), .ZN( + n_1_0_209)); + NAND3_X1_LVT i_1_0_220 (.A1(n_1_0_219), .A2(n_1_0_214), .A3(n_1_0_209), + .ZN(RRs2[11])); + AOI22_X1_LVT i_1_0_219 (.A1(registers_28__ap[10]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[10]), .ZN(n_1_0_208)); + AOI222_X1_LVT i_1_0_218 (.A1(registers_26__ap[10]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[10]), .C1(registers_25__ap[10]), .C2( + n_1_0_620), .ZN(n_1_0_207)); + AOI22_X1_LVT i_1_0_217 (.A1(registers_13__ap[10]), .A2(n_1_0_631), .B1( + n_1_0_612), .B2(registers_21__ap[10]), .ZN(n_1_0_206)); + AOI22_X1_LVT i_1_0_216 (.A1(registers_24__ap[10]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[10]), .ZN(n_1_0_205)); + AOI22_X1_LVT i_1_0_215 (.A1(registers_15__ap[10]), .A2(n_1_0_627), .B1( + n_1_0_610), .B2(registers_3__ap[10]), .ZN(n_1_0_204)); + AOI22_X1_LVT i_1_0_214 (.A1(registers_31__ap[10]), .A2(n_1_0_637), .B1( + n_1_0_629), .B2(registers_17__ap[10]), .ZN(n_1_0_203)); + AOI22_X1_LVT i_1_0_213 (.A1(registers_29__ap[10]), .A2(n_1_0_649), .B1( + n_1_0_615), .B2(registers_23__ap[10]), .ZN(n_1_0_202)); + NAND4_X1_LVT i_1_0_212 (.A1(n_1_0_205), .A2(n_1_0_204), .A3(n_1_0_203), + .A4(n_1_0_202), .ZN(n_1_0_201)); + AOI22_X1_LVT i_1_0_211 (.A1(registers_18__ap[10]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[10]), .ZN(n_1_0_200)); + AOI22_X1_LVT i_1_0_210 (.A1(registers_4__ap[10]), .A2(n_1_0_638), .B1( + n_1_0_632), .B2(registers_12__ap[10]), .ZN(n_1_0_199)); + AOI22_X1_LVT i_1_0_209 (.A1(registers_7__ap[10]), .A2(n_1_0_623), .B1( + n_1_0_614), .B2(registers_16__ap[10]), .ZN(n_1_0_198)); + AOI22_X1_LVT i_1_0_208 (.A1(registers_22__ap[10]), .A2(n_1_0_642), .B1( + n_1_0_635), .B2(registers_5__ap[10]), .ZN(n_1_0_197)); + NAND4_X1_LVT i_1_0_207 (.A1(n_1_0_200), .A2(n_1_0_199), .A3(n_1_0_198), + .A4(n_1_0_197), .ZN(n_1_0_196)); + AOI22_X1_LVT i_1_0_206 (.A1(registers_1__ap[10]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[10]), .ZN(n_1_0_195)); + AOI22_X1_LVT i_1_0_205 (.A1(registers_14__ap[10]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[10]), .ZN(n_1_0_194)); + AOI22_X1_LVT i_1_0_204 (.A1(registers_19__ap[10]), .A2(n_1_0_633), .B1( + n_1_0_618), .B2(registers_2__ap[10]), .ZN(n_1_0_193)); + AOI22_X1_LVT i_1_0_203 (.A1(registers_27__ap[10]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[10]), .ZN(n_1_0_192)); + NAND4_X1_LVT i_1_0_202 (.A1(n_1_0_195), .A2(n_1_0_194), .A3(n_1_0_193), + .A4(n_1_0_192), .ZN(n_1_0_191)); + NOR3_X1_LVT i_1_0_201 (.A1(n_1_0_201), .A2(n_1_0_196), .A3(n_1_0_191), + .ZN(n_1_0_190)); + NAND4_X1_LVT i_1_0_200 (.A1(n_1_0_208), .A2(n_1_0_207), .A3(n_1_0_206), + .A4(n_1_0_190), .ZN(RRs2[10])); + AOI22_X1_LVT i_1_0_196 (.A1(registers_13__ap[9]), .A2(n_1_0_631), .B1( + n_1_0_612), .B2(registers_21__ap[9]), .ZN(n_1_0_186)); + AOI22_X1_LVT i_1_0_199 (.A1(registers_29__ap[9]), .A2(n_1_0_649), .B1( + n_1_0_636), .B2(registers_27__ap[9]), .ZN(n_1_0_189)); + AOI22_X1_LVT i_1_0_195 (.A1(registers_24__ap[9]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[9]), .ZN(n_1_0_185)); + AOI22_X1_LVT i_1_0_198 (.A1(registers_31__ap[9]), .A2(n_1_0_637), .B1( + n_1_0_627), .B2(registers_15__ap[9]), .ZN(n_1_0_188)); + INV_X1_LVT i_1_0_197 (.A(n_1_0_188), .ZN(n_1_0_187)); + AOI221_X1_LVT i_1_0_194 (.A(n_1_0_187), .B1(n_1_0_615), .B2( + registers_23__ap[9]), .C1(registers_4__ap[9]), .C2(n_1_0_638), .ZN( + n_1_0_184)); + AOI222_X1_LVT i_1_0_193 (.A1(registers_18__ap[9]), .A2(n_1_0_646), .B1( + n_1_0_624), .B2(registers_10__ap[9]), .C1(registers_25__ap[9]), .C2( + n_1_0_620), .ZN(n_1_0_183)); + NAND4_X1_LVT i_1_0_192 (.A1(n_1_0_189), .A2(n_1_0_185), .A3(n_1_0_184), + .A4(n_1_0_183), .ZN(n_1_0_182)); + AOI221_X1_LVT i_1_0_191 (.A(n_1_0_182), .B1(n_1_0_626), .B2( + registers_8__ap[9]), .C1(registers_28__ap[9]), .C2(n_1_0_634), .ZN( + n_1_0_181)); + AOI22_X1_LVT i_1_0_190 (.A1(registers_26__ap[9]), .A2(n_1_0_640), .B1( + n_1_0_622), .B2(registers_30__ap[9]), .ZN(n_1_0_180)); + AOI22_X1_LVT i_1_0_189 (.A1(registers_12__ap[9]), .A2(n_1_0_632), .B1( + n_1_0_629), .B2(registers_17__ap[9]), .ZN(n_1_0_179)); + AOI22_X1_LVT i_1_0_188 (.A1(registers_5__ap[9]), .A2(n_1_0_635), .B1( + n_1_0_623), .B2(registers_7__ap[9]), .ZN(n_1_0_178)); + NAND3_X1_LVT i_1_0_187 (.A1(n_1_0_180), .A2(n_1_0_179), .A3(n_1_0_178), + .ZN(n_1_0_177)); + AOI221_X1_LVT i_1_0_186 (.A(n_1_0_177), .B1(n_1_0_642), .B2( + registers_22__ap[9]), .C1(registers_16__ap[9]), .C2(n_1_0_614), .ZN( + n_1_0_176)); + AOI22_X1_LVT i_1_0_185 (.A1(registers_1__ap[9]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[9]), .ZN(n_1_0_175)); + AOI22_X1_LVT i_1_0_184 (.A1(registers_14__ap[9]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[9]), .ZN(n_1_0_174)); + AOI22_X1_LVT i_1_0_183 (.A1(registers_19__ap[9]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[9]), .ZN(n_1_0_173)); + NAND3_X1_LVT i_1_0_182 (.A1(n_1_0_175), .A2(n_1_0_174), .A3(n_1_0_173), + .ZN(n_1_0_172)); + AOI221_X1_LVT i_1_0_181 (.A(n_1_0_172), .B1(n_1_0_611), .B2( + registers_11__ap[9]), .C1(registers_2__ap[9]), .C2(n_1_0_618), .ZN( + n_1_0_171)); + NAND4_X1_LVT i_1_0_180 (.A1(n_1_0_186), .A2(n_1_0_181), .A3(n_1_0_176), + .A4(n_1_0_171), .ZN(RRs2[9])); + AOI22_X1_LVT i_1_0_179 (.A1(registers_28__ap[8]), .A2(n_1_0_634), .B1( + n_1_0_629), .B2(registers_17__ap[8]), .ZN(n_1_0_170)); + AOI222_X1_LVT i_1_0_178 (.A1(registers_26__ap[8]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[8]), .C1(n_1_0_626), .C2( + registers_8__ap[8]), .ZN(n_1_0_169)); + AOI22_X1_LVT i_1_0_177 (.A1(registers_29__ap[8]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[8]), .ZN(n_1_0_168)); + AOI22_X1_LVT i_1_0_176 (.A1(registers_1__ap[8]), .A2(n_1_0_644), .B1( + n_1_0_616), .B2(registers_6__ap[8]), .ZN(n_1_0_167)); + AOI22_X1_LVT i_1_0_175 (.A1(registers_5__ap[8]), .A2(n_1_0_635), .B1( + n_1_0_610), .B2(registers_3__ap[8]), .ZN(n_1_0_166)); + AOI22_X1_LVT i_1_0_174 (.A1(registers_31__ap[8]), .A2(n_1_0_637), .B1( + n_1_0_614), .B2(registers_16__ap[8]), .ZN(n_1_0_165)); + AOI22_X1_LVT i_1_0_173 (.A1(registers_15__ap[8]), .A2(n_1_0_627), .B1( + n_1_0_615), .B2(registers_23__ap[8]), .ZN(n_1_0_164)); + NAND4_X1_LVT i_1_0_172 (.A1(n_1_0_167), .A2(n_1_0_166), .A3(n_1_0_165), + .A4(n_1_0_164), .ZN(n_1_0_163)); + AOI22_X1_LVT i_1_0_171 (.A1(registers_18__ap[8]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[8]), .ZN(n_1_0_162)); + AOI22_X1_LVT i_1_0_170 (.A1(registers_4__ap[8]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[8]), .ZN(n_1_0_161)); + AOI22_X1_LVT i_1_0_169 (.A1(registers_22__ap[8]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[8]), .ZN(n_1_0_160)); + AOI22_X1_LVT i_1_0_168 (.A1(registers_12__ap[8]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[8]), .ZN(n_1_0_159)); + NAND4_X1_LVT i_1_0_167 (.A1(n_1_0_162), .A2(n_1_0_161), .A3(n_1_0_160), + .A4(n_1_0_159), .ZN(n_1_0_158)); + AOI22_X1_LVT i_1_0_166 (.A1(registers_13__ap[8]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[8]), .ZN(n_1_0_157)); + AOI22_X1_LVT i_1_0_165 (.A1(registers_7__ap[8]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[8]), .ZN(n_1_0_156)); + AOI22_X1_LVT i_1_0_164 (.A1(registers_19__ap[8]), .A2(n_1_0_633), .B1( + n_1_0_618), .B2(registers_2__ap[8]), .ZN(n_1_0_155)); + AOI22_X1_LVT i_1_0_163 (.A1(registers_27__ap[8]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[8]), .ZN(n_1_0_154)); + NAND4_X1_LVT i_1_0_162 (.A1(n_1_0_157), .A2(n_1_0_156), .A3(n_1_0_155), + .A4(n_1_0_154), .ZN(n_1_0_153)); + NOR3_X1_LVT i_1_0_161 (.A1(n_1_0_163), .A2(n_1_0_158), .A3(n_1_0_153), + .ZN(n_1_0_152)); + NAND4_X1_LVT i_1_0_160 (.A1(n_1_0_170), .A2(n_1_0_169), .A3(n_1_0_168), + .A4(n_1_0_152), .ZN(RRs2[8])); + AOI22_X1_LVT i_1_0_159 (.A1(registers_28__ap[7]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[7]), .ZN(n_1_0_151)); + AOI222_X1_LVT i_1_0_158 (.A1(registers_26__ap[7]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[7]), .C1(registers_25__ap[7]), .C2( + n_1_0_620), .ZN(n_1_0_150)); + AOI22_X1_LVT i_1_0_157 (.A1(registers_24__ap[7]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[7]), .ZN(n_1_0_149)); + AOI22_X1_LVT i_1_0_156 (.A1(registers_15__ap[7]), .A2(n_1_0_627), .B1( + n_1_0_610), .B2(registers_3__ap[7]), .ZN(n_1_0_148)); + AOI22_X1_LVT i_1_0_155 (.A1(registers_31__ap[7]), .A2(n_1_0_637), .B1( + n_1_0_629), .B2(registers_17__ap[7]), .ZN(n_1_0_147)); + AOI22_X1_LVT i_1_0_154 (.A1(registers_29__ap[7]), .A2(n_1_0_649), .B1( + n_1_0_615), .B2(registers_23__ap[7]), .ZN(n_1_0_146)); + NAND4_X1_LVT i_1_0_153 (.A1(n_1_0_149), .A2(n_1_0_148), .A3(n_1_0_147), + .A4(n_1_0_146), .ZN(n_1_0_145)); + AOI221_X1_LVT i_1_0_152 (.A(n_1_0_145), .B1(n_1_0_612), .B2( + registers_21__ap[7]), .C1(registers_13__ap[7]), .C2(n_1_0_631), .ZN( + n_1_0_144)); + AOI22_X1_LVT i_1_0_151 (.A1(registers_18__ap[7]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[7]), .ZN(n_1_0_143)); + AOI22_X1_LVT i_1_0_150 (.A1(registers_4__ap[7]), .A2(n_1_0_638), .B1( + n_1_0_632), .B2(registers_12__ap[7]), .ZN(n_1_0_142)); + AOI22_X1_LVT i_1_0_149 (.A1(registers_5__ap[7]), .A2(n_1_0_635), .B1( + n_1_0_623), .B2(registers_7__ap[7]), .ZN(n_1_0_141)); + AOI22_X1_LVT i_1_0_148 (.A1(registers_22__ap[7]), .A2(n_1_0_642), .B1( + n_1_0_614), .B2(registers_16__ap[7]), .ZN(n_1_0_140)); + NAND4_X1_LVT i_1_0_147 (.A1(n_1_0_143), .A2(n_1_0_142), .A3(n_1_0_141), + .A4(n_1_0_140), .ZN(n_1_0_139)); + AOI22_X1_LVT i_1_0_146 (.A1(registers_1__ap[7]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[7]), .ZN(n_1_0_138)); + AOI22_X1_LVT i_1_0_145 (.A1(registers_14__ap[7]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[7]), .ZN(n_1_0_137)); + AOI22_X1_LVT i_1_0_144 (.A1(registers_19__ap[7]), .A2(n_1_0_633), .B1( + n_1_0_618), .B2(registers_2__ap[7]), .ZN(n_1_0_136)); + AOI22_X1_LVT i_1_0_143 (.A1(registers_27__ap[7]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[7]), .ZN(n_1_0_135)); + NAND4_X1_LVT i_1_0_142 (.A1(n_1_0_138), .A2(n_1_0_137), .A3(n_1_0_136), + .A4(n_1_0_135), .ZN(n_1_0_134)); + NOR2_X1_LVT i_1_0_141 (.A1(n_1_0_139), .A2(n_1_0_134), .ZN(n_1_0_133)); + NAND4_X1_LVT i_1_0_140 (.A1(n_1_0_151), .A2(n_1_0_150), .A3(n_1_0_144), + .A4(n_1_0_133), .ZN(RRs2[7])); + AOI22_X1_LVT i_1_0_136 (.A1(registers_13__ap[6]), .A2(n_1_0_631), .B1( + n_1_0_612), .B2(registers_21__ap[6]), .ZN(n_1_0_129)); + AOI22_X1_LVT i_1_0_139 (.A1(registers_29__ap[6]), .A2(n_1_0_649), .B1( + n_1_0_636), .B2(registers_27__ap[6]), .ZN(n_1_0_132)); + AOI22_X1_LVT i_1_0_135 (.A1(registers_24__ap[6]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[6]), .ZN(n_1_0_128)); + AOI22_X1_LVT i_1_0_138 (.A1(registers_31__ap[6]), .A2(n_1_0_637), .B1( + n_1_0_627), .B2(registers_15__ap[6]), .ZN(n_1_0_131)); + INV_X1_LVT i_1_0_137 (.A(n_1_0_131), .ZN(n_1_0_130)); + AOI221_X1_LVT i_1_0_134 (.A(n_1_0_130), .B1(n_1_0_638), .B2( + registers_4__ap[6]), .C1(registers_23__ap[6]), .C2(n_1_0_615), .ZN( + n_1_0_127)); + AOI222_X1_LVT i_1_0_133 (.A1(registers_18__ap[6]), .A2(n_1_0_646), .B1( + n_1_0_620), .B2(registers_25__ap[6]), .C1(n_1_0_624), .C2( + registers_10__ap[6]), .ZN(n_1_0_126)); + NAND4_X1_LVT i_1_0_132 (.A1(n_1_0_132), .A2(n_1_0_128), .A3(n_1_0_127), + .A4(n_1_0_126), .ZN(n_1_0_125)); + AOI221_X1_LVT i_1_0_131 (.A(n_1_0_125), .B1(n_1_0_626), .B2( + registers_8__ap[6]), .C1(registers_28__ap[6]), .C2(n_1_0_634), .ZN( + n_1_0_124)); + AOI22_X1_LVT i_1_0_130 (.A1(registers_26__ap[6]), .A2(n_1_0_640), .B1( + n_1_0_622), .B2(registers_30__ap[6]), .ZN(n_1_0_123)); + AOI22_X1_LVT i_1_0_129 (.A1(registers_12__ap[6]), .A2(n_1_0_632), .B1( + n_1_0_629), .B2(registers_17__ap[6]), .ZN(n_1_0_122)); + AOI22_X1_LVT i_1_0_128 (.A1(registers_7__ap[6]), .A2(n_1_0_623), .B1( + n_1_0_614), .B2(registers_16__ap[6]), .ZN(n_1_0_121)); + NAND3_X1_LVT i_1_0_127 (.A1(n_1_0_123), .A2(n_1_0_122), .A3(n_1_0_121), + .ZN(n_1_0_120)); + AOI221_X1_LVT i_1_0_126 (.A(n_1_0_120), .B1(n_1_0_642), .B2( + registers_22__ap[6]), .C1(registers_5__ap[6]), .C2(n_1_0_635), .ZN( + n_1_0_119)); + AOI22_X1_LVT i_1_0_125 (.A1(registers_1__ap[6]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[6]), .ZN(n_1_0_118)); + AOI22_X1_LVT i_1_0_124 (.A1(registers_14__ap[6]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[6]), .ZN(n_1_0_117)); + AOI22_X1_LVT i_1_0_123 (.A1(registers_19__ap[6]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[6]), .ZN(n_1_0_116)); + NAND3_X1_LVT i_1_0_122 (.A1(n_1_0_118), .A2(n_1_0_117), .A3(n_1_0_116), + .ZN(n_1_0_115)); + AOI221_X1_LVT i_1_0_121 (.A(n_1_0_115), .B1(n_1_0_618), .B2( + registers_2__ap[6]), .C1(registers_11__ap[6]), .C2(n_1_0_611), .ZN( + n_1_0_114)); + NAND4_X1_LVT i_1_0_120 (.A1(n_1_0_129), .A2(n_1_0_124), .A3(n_1_0_119), + .A4(n_1_0_114), .ZN(RRs2[6])); + AOI22_X1_LVT i_1_0_118 (.A1(registers_28__ap[5]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[5]), .ZN(n_1_0_112)); + AOI22_X1_LVT i_1_0_119 (.A1(registers_31__ap[5]), .A2(n_1_0_637), .B1( + n_1_0_627), .B2(registers_15__ap[5]), .ZN(n_1_0_113)); + AOI22_X1_LVT i_1_0_117 (.A1(registers_24__ap[5]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[5]), .ZN(n_1_0_111)); + AOI22_X1_LVT i_1_0_116 (.A1(registers_17__ap[5]), .A2(n_1_0_629), .B1( + n_1_0_615), .B2(registers_23__ap[5]), .ZN(n_1_0_110)); + NAND3_X1_LVT i_1_0_115 (.A1(n_1_0_113), .A2(n_1_0_111), .A3(n_1_0_110), + .ZN(n_1_0_109)); + AOI221_X1_LVT i_1_0_114 (.A(n_1_0_109), .B1(n_1_0_636), .B2( + registers_27__ap[5]), .C1(registers_29__ap[5]), .C2(n_1_0_649), .ZN( + n_1_0_108)); + AOI222_X1_LVT i_1_0_113 (.A1(registers_10__ap[5]), .A2(n_1_0_624), .B1( + n_1_0_620), .B2(registers_25__ap[5]), .C1(registers_18__ap[5]), .C2( + n_1_0_646), .ZN(n_1_0_107)); + NAND3_X1_LVT i_1_0_112 (.A1(n_1_0_112), .A2(n_1_0_108), .A3(n_1_0_107), + .ZN(n_1_0_106)); + AOI221_X1_LVT i_1_0_111 (.A(n_1_0_106), .B1(n_1_0_612), .B2( + registers_21__ap[5]), .C1(registers_13__ap[5]), .C2(n_1_0_631), .ZN( + n_1_0_105)); + AOI22_X1_LVT i_1_0_110 (.A1(registers_26__ap[5]), .A2(n_1_0_640), .B1( + n_1_0_622), .B2(registers_30__ap[5]), .ZN(n_1_0_104)); + AOI22_X1_LVT i_1_0_109 (.A1(registers_4__ap[5]), .A2(n_1_0_638), .B1( + n_1_0_632), .B2(registers_12__ap[5]), .ZN(n_1_0_103)); + AOI22_X1_LVT i_1_0_108 (.A1(registers_5__ap[5]), .A2(n_1_0_635), .B1( + n_1_0_623), .B2(registers_7__ap[5]), .ZN(n_1_0_102)); + NAND3_X1_LVT i_1_0_107 (.A1(n_1_0_104), .A2(n_1_0_103), .A3(n_1_0_102), + .ZN(n_1_0_101)); + AOI221_X1_LVT i_1_0_106 (.A(n_1_0_101), .B1(n_1_0_642), .B2( + registers_22__ap[5]), .C1(registers_16__ap[5]), .C2(n_1_0_614), .ZN( + n_1_0_100)); + AOI22_X1_LVT i_1_0_105 (.A1(registers_1__ap[5]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[5]), .ZN(n_1_0_99)); + AOI22_X1_LVT i_1_0_104 (.A1(registers_14__ap[5]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[5]), .ZN(n_1_0_98)); + AOI22_X1_LVT i_1_0_103 (.A1(registers_19__ap[5]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[5]), .ZN(n_1_0_97)); + NAND3_X1_LVT i_1_0_102 (.A1(n_1_0_99), .A2(n_1_0_98), .A3(n_1_0_97), .ZN( + n_1_0_96)); + AOI221_X1_LVT i_1_0_101 (.A(n_1_0_96), .B1(n_1_0_611), .B2( + registers_11__ap[5]), .C1(registers_2__ap[5]), .C2(n_1_0_618), .ZN( + n_1_0_95)); + NAND3_X1_LVT i_1_0_100 (.A1(n_1_0_105), .A2(n_1_0_100), .A3(n_1_0_95), + .ZN(RRs2[5])); + AOI22_X1_LVT i_1_0_99 (.A1(registers_4__ap[4]), .A2(n_1_0_638), .B1(n_1_0_634), + .B2(registers_28__ap[4]), .ZN(n_1_0_94)); + AOI222_X1_LVT i_1_0_98 (.A1(registers_8__ap[4]), .A2(n_1_0_626), .B1( + n_1_0_624), .B2(registers_10__ap[4]), .C1(n_1_0_622), .C2( + registers_30__ap[4]), .ZN(n_1_0_93)); + AOI22_X1_LVT i_1_0_97 (.A1(registers_29__ap[4]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[4]), .ZN(n_1_0_92)); + AOI22_X1_LVT i_1_0_96 (.A1(registers_1__ap[4]), .A2(n_1_0_644), .B1(n_1_0_616), + .B2(registers_6__ap[4]), .ZN(n_1_0_91)); + AOI22_X1_LVT i_1_0_95 (.A1(registers_27__ap[4]), .A2(n_1_0_636), .B1( + n_1_0_627), .B2(registers_15__ap[4]), .ZN(n_1_0_90)); + AOI22_X1_LVT i_1_0_94 (.A1(registers_23__ap[4]), .A2(n_1_0_615), .B1( + n_1_0_614), .B2(registers_16__ap[4]), .ZN(n_1_0_89)); + AOI22_X1_LVT i_1_0_93 (.A1(registers_31__ap[4]), .A2(n_1_0_637), .B1( + n_1_0_635), .B2(registers_5__ap[4]), .ZN(n_1_0_88)); + NAND4_X1_LVT i_1_0_92 (.A1(n_1_0_91), .A2(n_1_0_90), .A3(n_1_0_89), .A4( + n_1_0_88), .ZN(n_1_0_87)); + AOI22_X1_LVT i_1_0_91 (.A1(registers_18__ap[4]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[4]), .ZN(n_1_0_86)); + AOI22_X1_LVT i_1_0_90 (.A1(registers_12__ap[4]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[4]), .ZN(n_1_0_85)); + AOI22_X1_LVT i_1_0_89 (.A1(registers_22__ap[4]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[4]), .ZN(n_1_0_84)); + AOI22_X1_LVT i_1_0_88 (.A1(registers_17__ap[4]), .A2(n_1_0_629), .B1( + n_1_0_613), .B2(registers_20__ap[4]), .ZN(n_1_0_83)); + NAND4_X1_LVT i_1_0_87 (.A1(n_1_0_86), .A2(n_1_0_85), .A3(n_1_0_84), .A4( + n_1_0_83), .ZN(n_1_0_82)); + AOI22_X1_LVT i_1_0_86 (.A1(registers_13__ap[4]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[4]), .ZN(n_1_0_81)); + AOI22_X1_LVT i_1_0_85 (.A1(registers_7__ap[4]), .A2(n_1_0_623), .B1(n_1_0_619), + .B2(registers_14__ap[4]), .ZN(n_1_0_80)); + AOI22_X1_LVT i_1_0_84 (.A1(registers_19__ap[4]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[4]), .ZN(n_1_0_79)); + AOI22_X1_LVT i_1_0_83 (.A1(registers_2__ap[4]), .A2(n_1_0_618), .B1(n_1_0_611), + .B2(registers_11__ap[4]), .ZN(n_1_0_78)); + NAND4_X1_LVT i_1_0_82 (.A1(n_1_0_81), .A2(n_1_0_80), .A3(n_1_0_79), .A4( + n_1_0_78), .ZN(n_1_0_77)); + NOR3_X1_LVT i_1_0_81 (.A1(n_1_0_87), .A2(n_1_0_82), .A3(n_1_0_77), .ZN( + n_1_0_76)); + NAND4_X1_LVT i_1_0_80 (.A1(n_1_0_94), .A2(n_1_0_93), .A3(n_1_0_92), .A4( + n_1_0_76), .ZN(RRs2[4])); + AOI22_X1_LVT i_1_0_78 (.A1(registers_29__ap[3]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[3]), .ZN(n_1_0_74)); + AOI22_X1_LVT i_1_0_79 (.A1(registers_27__ap[3]), .A2(n_1_0_636), .B1( + n_1_0_627), .B2(registers_15__ap[3]), .ZN(n_1_0_75)); + AOI22_X1_LVT i_1_0_77 (.A1(registers_1__ap[3]), .A2(n_1_0_644), .B1(n_1_0_616), + .B2(registers_6__ap[3]), .ZN(n_1_0_73)); + AOI22_X1_LVT i_1_0_76 (.A1(registers_5__ap[3]), .A2(n_1_0_635), .B1(n_1_0_611), + .B2(registers_11__ap[3]), .ZN(n_1_0_72)); + NAND3_X1_LVT i_1_0_75 (.A1(n_1_0_75), .A2(n_1_0_73), .A3(n_1_0_72), .ZN( + n_1_0_71)); + AOI221_X1_LVT i_1_0_74 (.A(n_1_0_71), .B1(n_1_0_614), .B2(registers_16__ap[3]), + .C1(registers_31__ap[3]), .C2(n_1_0_637), .ZN(n_1_0_70)); + AOI222_X1_LVT i_1_0_73 (.A1(registers_8__ap[3]), .A2(n_1_0_626), .B1( + n_1_0_624), .B2(registers_10__ap[3]), .C1(n_1_0_622), .C2( + registers_30__ap[3]), .ZN(n_1_0_69)); + NAND3_X1_LVT i_1_0_72 (.A1(n_1_0_74), .A2(n_1_0_70), .A3(n_1_0_69), .ZN( + n_1_0_68)); + AOI221_X1_LVT i_1_0_71 (.A(n_1_0_68), .B1(n_1_0_638), .B2(registers_4__ap[3]), + .C1(registers_28__ap[3]), .C2(n_1_0_634), .ZN(n_1_0_67)); + AOI22_X1_LVT i_1_0_70 (.A1(registers_18__ap[3]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[3]), .ZN(n_1_0_66)); + AOI22_X1_LVT i_1_0_69 (.A1(registers_12__ap[3]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[3]), .ZN(n_1_0_65)); + AOI22_X1_LVT i_1_0_68 (.A1(registers_22__ap[3]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[3]), .ZN(n_1_0_64)); + NAND3_X1_LVT i_1_0_67 (.A1(n_1_0_66), .A2(n_1_0_65), .A3(n_1_0_64), .ZN( + n_1_0_63)); + AOI221_X1_LVT i_1_0_66 (.A(n_1_0_63), .B1(n_1_0_613), .B2(registers_20__ap[3]), + .C1(registers_17__ap[3]), .C2(n_1_0_629), .ZN(n_1_0_62)); + AOI22_X1_LVT i_1_0_65 (.A1(registers_13__ap[3]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[3]), .ZN(n_1_0_61)); + AOI22_X1_LVT i_1_0_64 (.A1(registers_7__ap[3]), .A2(n_1_0_623), .B1(n_1_0_619), + .B2(registers_14__ap[3]), .ZN(n_1_0_60)); + AOI22_X1_LVT i_1_0_63 (.A1(registers_19__ap[3]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[3]), .ZN(n_1_0_59)); + NAND3_X1_LVT i_1_0_62 (.A1(n_1_0_61), .A2(n_1_0_60), .A3(n_1_0_59), .ZN( + n_1_0_58)); + AOI221_X1_LVT i_1_0_61 (.A(n_1_0_58), .B1(n_1_0_618), .B2(registers_2__ap[3]), + .C1(registers_23__ap[3]), .C2(n_1_0_615), .ZN(n_1_0_57)); + NAND3_X1_LVT i_1_0_60 (.A1(n_1_0_67), .A2(n_1_0_62), .A3(n_1_0_57), .ZN( + RRs2[3])); + AOI22_X1_LVT i_1_0_58 (.A1(registers_29__ap[2]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[2]), .ZN(n_1_0_55)); + AOI22_X1_LVT i_1_0_59 (.A1(registers_27__ap[2]), .A2(n_1_0_636), .B1( + n_1_0_627), .B2(registers_15__ap[2]), .ZN(n_1_0_56)); + AOI22_X1_LVT i_1_0_57 (.A1(registers_1__ap[2]), .A2(n_1_0_644), .B1(n_1_0_616), + .B2(registers_6__ap[2]), .ZN(n_1_0_54)); + AOI22_X1_LVT i_1_0_56 (.A1(registers_5__ap[2]), .A2(n_1_0_635), .B1(n_1_0_615), + .B2(registers_23__ap[2]), .ZN(n_1_0_53)); + NAND3_X1_LVT i_1_0_55 (.A1(n_1_0_56), .A2(n_1_0_54), .A3(n_1_0_53), .ZN( + n_1_0_52)); + AOI221_X1_LVT i_1_0_54 (.A(n_1_0_52), .B1(n_1_0_637), .B2(registers_31__ap[2]), + .C1(registers_16__ap[2]), .C2(n_1_0_614), .ZN(n_1_0_51)); + AOI222_X1_LVT i_1_0_53 (.A1(registers_8__ap[2]), .A2(n_1_0_626), .B1( + n_1_0_624), .B2(registers_10__ap[2]), .C1(n_1_0_622), .C2( + registers_30__ap[2]), .ZN(n_1_0_50)); + NAND3_X1_LVT i_1_0_52 (.A1(n_1_0_55), .A2(n_1_0_51), .A3(n_1_0_50), .ZN( + n_1_0_49)); + AOI221_X1_LVT i_1_0_51 (.A(n_1_0_49), .B1(n_1_0_638), .B2(registers_4__ap[2]), + .C1(registers_28__ap[2]), .C2(n_1_0_634), .ZN(n_1_0_48)); + AOI22_X1_LVT i_1_0_50 (.A1(registers_18__ap[2]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[2]), .ZN(n_1_0_47)); + AOI22_X1_LVT i_1_0_49 (.A1(registers_12__ap[2]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[2]), .ZN(n_1_0_46)); + AOI22_X1_LVT i_1_0_48 (.A1(registers_22__ap[2]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[2]), .ZN(n_1_0_45)); + NAND3_X1_LVT i_1_0_47 (.A1(n_1_0_47), .A2(n_1_0_46), .A3(n_1_0_45), .ZN( + n_1_0_44)); + AOI221_X1_LVT i_1_0_46 (.A(n_1_0_44), .B1(n_1_0_629), .B2(registers_17__ap[2]), + .C1(registers_20__ap[2]), .C2(n_1_0_613), .ZN(n_1_0_43)); + AOI22_X1_LVT i_1_0_45 (.A1(registers_13__ap[2]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[2]), .ZN(n_1_0_42)); + AOI22_X1_LVT i_1_0_44 (.A1(registers_7__ap[2]), .A2(n_1_0_623), .B1(n_1_0_619), + .B2(registers_14__ap[2]), .ZN(n_1_0_41)); + AOI22_X1_LVT i_1_0_43 (.A1(registers_19__ap[2]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[2]), .ZN(n_1_0_40)); + NAND3_X1_LVT i_1_0_42 (.A1(n_1_0_42), .A2(n_1_0_41), .A3(n_1_0_40), .ZN( + n_1_0_39)); + AOI221_X1_LVT i_1_0_41 (.A(n_1_0_39), .B1(n_1_0_618), .B2(registers_2__ap[2]), + .C1(registers_11__ap[2]), .C2(n_1_0_611), .ZN(n_1_0_38)); + NAND3_X1_LVT i_1_0_40 (.A1(n_1_0_48), .A2(n_1_0_43), .A3(n_1_0_38), .ZN( + RRs2[2])); + AOI22_X1_LVT i_1_0_38 (.A1(registers_29__ap[1]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[1]), .ZN(n_1_0_36)); + AOI22_X1_LVT i_1_0_39 (.A1(registers_16__ap[1]), .A2(n_1_0_614), .B1( + n_1_0_610), .B2(registers_3__ap[1]), .ZN(n_1_0_37)); + AOI22_X1_LVT i_1_0_37 (.A1(registers_1__ap[1]), .A2(n_1_0_644), .B1(n_1_0_616), + .B2(registers_6__ap[1]), .ZN(n_1_0_35)); + AOI22_X1_LVT i_1_0_36 (.A1(registers_31__ap[1]), .A2(n_1_0_637), .B1( + n_1_0_635), .B2(registers_5__ap[1]), .ZN(n_1_0_34)); + NAND3_X1_LVT i_1_0_35 (.A1(n_1_0_37), .A2(n_1_0_35), .A3(n_1_0_34), .ZN( + n_1_0_33)); + AOI221_X1_LVT i_1_0_34 (.A(n_1_0_33), .B1(n_1_0_627), .B2(registers_15__ap[1]), + .C1(registers_23__ap[1]), .C2(n_1_0_615), .ZN(n_1_0_32)); + AOI222_X1_LVT i_1_0_33 (.A1(registers_26__ap[1]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[1]), .C1(n_1_0_626), .C2( + registers_8__ap[1]), .ZN(n_1_0_31)); + NAND3_X1_LVT i_1_0_32 (.A1(n_1_0_36), .A2(n_1_0_32), .A3(n_1_0_31), .ZN( + n_1_0_30)); + AOI221_X1_LVT i_1_0_31 (.A(n_1_0_30), .B1(n_1_0_629), .B2(registers_17__ap[1]), + .C1(registers_28__ap[1]), .C2(n_1_0_634), .ZN(n_1_0_29)); + AOI22_X1_LVT i_1_0_30 (.A1(registers_18__ap[1]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[1]), .ZN(n_1_0_28)); + AOI22_X1_LVT i_1_0_29 (.A1(registers_4__ap[1]), .A2(n_1_0_638), .B1(n_1_0_613), + .B2(registers_20__ap[1]), .ZN(n_1_0_27)); + AOI22_X1_LVT i_1_0_28 (.A1(registers_22__ap[1]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[1]), .ZN(n_1_0_26)); + NAND3_X1_LVT i_1_0_27 (.A1(n_1_0_28), .A2(n_1_0_27), .A3(n_1_0_26), .ZN( + n_1_0_25)); + AOI221_X1_LVT i_1_0_26 (.A(n_1_0_25), .B1(n_1_0_632), .B2(registers_12__ap[1]), + .C1(registers_24__ap[1]), .C2(n_1_0_621), .ZN(n_1_0_24)); + AOI22_X1_LVT i_1_0_25 (.A1(registers_13__ap[1]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[1]), .ZN(n_1_0_23)); + AOI22_X1_LVT i_1_0_24 (.A1(registers_7__ap[1]), .A2(n_1_0_623), .B1(n_1_0_619), + .B2(registers_14__ap[1]), .ZN(n_1_0_22)); + AOI22_X1_LVT i_1_0_23 (.A1(registers_19__ap[1]), .A2(n_1_0_633), .B1( + n_1_0_618), .B2(registers_2__ap[1]), .ZN(n_1_0_21)); + NAND3_X1_LVT i_1_0_22 (.A1(n_1_0_23), .A2(n_1_0_22), .A3(n_1_0_21), .ZN( + n_1_0_20)); + AOI221_X1_LVT i_1_0_21 (.A(n_1_0_20), .B1(n_1_0_611), .B2(registers_11__ap[1]), + .C1(registers_27__ap[1]), .C2(n_1_0_636), .ZN(n_1_0_19)); + NAND3_X1_LVT i_1_0_20 (.A1(n_1_0_29), .A2(n_1_0_24), .A3(n_1_0_19), .ZN( + RRs2[1])); + AOI22_X1_LVT i_1_0_19 (.A1(registers_4__ap[0]), .A2(n_1_0_638), .B1(n_1_0_634), + .B2(registers_28__ap[0]), .ZN(n_1_0_18)); + AOI222_X1_LVT i_1_0_18 (.A1(registers_8__ap[0]), .A2(n_1_0_626), .B1( + n_1_0_624), .B2(registers_10__ap[0]), .C1(n_1_0_622), .C2( + registers_30__ap[0]), .ZN(n_1_0_17)); + AOI22_X1_LVT i_1_0_17 (.A1(registers_29__ap[0]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[0]), .ZN(n_1_0_16)); + AOI22_X1_LVT i_1_0_16 (.A1(registers_1__ap[0]), .A2(n_1_0_644), .B1(n_1_0_616), + .B2(registers_6__ap[0]), .ZN(n_1_0_15)); + AOI22_X1_LVT i_1_0_15 (.A1(registers_27__ap[0]), .A2(n_1_0_636), .B1( + n_1_0_627), .B2(registers_15__ap[0]), .ZN(n_1_0_14)); + AOI22_X1_LVT i_1_0_14 (.A1(registers_23__ap[0]), .A2(n_1_0_615), .B1( + n_1_0_614), .B2(registers_16__ap[0]), .ZN(n_1_0_13)); + AOI22_X1_LVT i_1_0_13 (.A1(registers_31__ap[0]), .A2(n_1_0_637), .B1( + n_1_0_635), .B2(registers_5__ap[0]), .ZN(n_1_0_12)); + NAND4_X1_LVT i_1_0_12 (.A1(n_1_0_15), .A2(n_1_0_14), .A3(n_1_0_13), .A4( + n_1_0_12), .ZN(n_1_0_11)); + AOI22_X1_LVT i_1_0_11 (.A1(registers_18__ap[0]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[0]), .ZN(n_1_0_10)); + AOI22_X1_LVT i_1_0_10 (.A1(registers_12__ap[0]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[0]), .ZN(n_1_0_9)); + AOI22_X1_LVT i_1_0_9 (.A1(registers_22__ap[0]), .A2(n_1_0_642), .B1(n_1_0_612), + .B2(registers_21__ap[0]), .ZN(n_1_0_8)); + AOI22_X1_LVT i_1_0_8 (.A1(registers_17__ap[0]), .A2(n_1_0_629), .B1(n_1_0_613), + .B2(registers_20__ap[0]), .ZN(n_1_0_7)); + NAND4_X1_LVT i_1_0_7 (.A1(n_1_0_10), .A2(n_1_0_9), .A3(n_1_0_8), .A4(n_1_0_7), + .ZN(n_1_0_6)); + AOI22_X1_LVT i_1_0_6 (.A1(registers_13__ap[0]), .A2(n_1_0_631), .B1(n_1_0_620), + .B2(registers_25__ap[0]), .ZN(n_1_0_5)); + AOI22_X1_LVT i_1_0_5 (.A1(registers_7__ap[0]), .A2(n_1_0_623), .B1(n_1_0_619), + .B2(registers_14__ap[0]), .ZN(n_1_0_4)); + AOI22_X1_LVT i_1_0_4 (.A1(registers_19__ap[0]), .A2(n_1_0_633), .B1(n_1_0_610), + .B2(registers_3__ap[0]), .ZN(n_1_0_3)); + AOI22_X1_LVT i_1_0_3 (.A1(registers_2__ap[0]), .A2(n_1_0_618), .B1(n_1_0_611), + .B2(registers_11__ap[0]), .ZN(n_1_0_2)); + NAND4_X1_LVT i_1_0_2 (.A1(n_1_0_5), .A2(n_1_0_4), .A3(n_1_0_3), .A4(n_1_0_2), + .ZN(n_1_0_1)); + NOR3_X1_LVT i_1_0_1 (.A1(n_1_0_11), .A2(n_1_0_6), .A3(n_1_0_1), .ZN(n_1_0_0)); + NAND4_X1_LVT i_1_0_0 (.A1(n_1_0_18), .A2(n_1_0_17), .A3(n_1_0_16), .A4( + n_1_0_0), .ZN(RRs2[0])); +endmodule + +module MemGen_32_11(chip_en, clock, addr, rd_data, rd_en, wr_en, wr_data); + input chip_en; + input clock; + input [10:0]addr; + output [31:0]rd_data; + input rd_en; + input wr_en; + input [31:0]wr_data; + + wire [1:0]mem_sel; + + INV_X1_LVT i_1_3 (.A(addr[10]), .ZN(mem_sel[0])); + MemGen_16_10 genblk1_0_U_hi (.chip_en(mem_sel[0]), .wr_en(wr_en), .addr({ + addr[9], addr[8], addr[7], addr[6], addr[5], addr[4], addr[3], addr[2], + addr[1], addr[0]}), .wr_data({wr_data[31], wr_data[30], wr_data[29], + wr_data[28], wr_data[27], wr_data[26], wr_data[25], wr_data[24], + wr_data[23], wr_data[22], wr_data[21], wr_data[20], wr_data[19], + wr_data[18], wr_data[17], wr_data[16]}), .clock(clock), .rd_en(rd_en), + .rd_data({n_63, n_62, n_61, n_60, n_59, n_58, n_57, n_56, n_55, n_54, n_53, + n_52, n_51, n_50, n_49, n_48})); + MemGen_16_10 genblk1_1_U_hi (.chip_en(addr[10]), .wr_en(wr_en), .addr({ + addr[9], addr[8], addr[7], addr[6], addr[5], addr[4], addr[3], addr[2], + addr[1], addr[0]}), .wr_data({wr_data[31], wr_data[30], wr_data[29], + wr_data[28], wr_data[27], wr_data[26], wr_data[25], wr_data[24], + wr_data[23], wr_data[22], wr_data[21], wr_data[20], wr_data[19], + wr_data[18], wr_data[17], wr_data[16]}), .clock(clock), .rd_en(rd_en), + .rd_data({n_31, n_30, n_29, n_28, n_27, n_26, n_25, n_24, n_23, n_22, n_21, + n_20, n_19, n_18, n_17, n_16})); + MUX2_X1_LVT i_1_1_31 (.A(n_63), .B(n_31), .S(addr[10]), .Z(rd_data[31])); + MUX2_X1_LVT i_1_1_30 (.A(n_62), .B(n_30), .S(addr[10]), .Z(rd_data[30])); + MUX2_X1_LVT i_1_1_29 (.A(n_61), .B(n_29), .S(addr[10]), .Z(rd_data[29])); + MUX2_X1_LVT i_1_1_28 (.A(n_60), .B(n_28), .S(addr[10]), .Z(rd_data[28])); + MUX2_X1_LVT i_1_1_27 (.A(n_59), .B(n_27), .S(addr[10]), .Z(rd_data[27])); + MUX2_X1_LVT i_1_1_26 (.A(n_58), .B(n_26), .S(addr[10]), .Z(rd_data[26])); + MUX2_X1_LVT i_1_1_25 (.A(n_57), .B(n_25), .S(addr[10]), .Z(rd_data[25])); + MUX2_X1_LVT i_1_1_24 (.A(n_56), .B(n_24), .S(addr[10]), .Z(rd_data[24])); + MUX2_X1_LVT i_1_1_23 (.A(n_55), .B(n_23), .S(addr[10]), .Z(rd_data[23])); + MUX2_X1_LVT i_1_1_22 (.A(n_54), .B(n_22), .S(addr[10]), .Z(rd_data[22])); + MUX2_X1_LVT i_1_1_21 (.A(n_53), .B(n_21), .S(addr[10]), .Z(rd_data[21])); + MUX2_X1_LVT i_1_1_20 (.A(n_52), .B(n_20), .S(addr[10]), .Z(rd_data[20])); + MUX2_X1_LVT i_1_1_19 (.A(n_51), .B(n_19), .S(addr[10]), .Z(rd_data[19])); + MUX2_X1_LVT i_1_1_18 (.A(n_50), .B(n_18), .S(addr[10]), .Z(rd_data[18])); + MUX2_X1_LVT i_1_1_17 (.A(n_49), .B(n_17), .S(addr[10]), .Z(rd_data[17])); + MUX2_X1_LVT i_1_1_16 (.A(n_48), .B(n_16), .S(addr[10]), .Z(rd_data[16])); + MemGen_16_10 genblk1_0_U_lo (.chip_en(mem_sel[0]), .wr_en(wr_en), .addr({ + addr[9], addr[8], addr[7], addr[6], addr[5], addr[4], addr[3], addr[2], + addr[1], addr[0]}), .wr_data({wr_data[15], wr_data[14], wr_data[13], + wr_data[12], wr_data[11], wr_data[10], wr_data[9], wr_data[8], wr_data[7], + wr_data[6], wr_data[5], wr_data[4], wr_data[3], wr_data[2], wr_data[1], + wr_data[0]}), .clock(clock), .rd_en(rd_en), .rd_data({n_47, n_46, n_45, + n_44, n_43, n_42, n_41, n_40, n_39, n_38, n_37, n_36, n_35, n_34, n_33, + n_32})); + MemGen_16_10 genblk1_1_U_lo (.chip_en(addr[10]), .wr_en(wr_en), .addr({ + addr[9], addr[8], addr[7], addr[6], addr[5], addr[4], addr[3], addr[2], + addr[1], addr[0]}), .wr_data({wr_data[15], wr_data[14], wr_data[13], + wr_data[12], wr_data[11], wr_data[10], wr_data[9], wr_data[8], wr_data[7], + wr_data[6], wr_data[5], wr_data[4], wr_data[3], wr_data[2], wr_data[1], + wr_data[0]}), .clock(clock), .rd_en(rd_en), .rd_data({n_15, n_14, n_13, + n_12, n_11, n_10, n_9, n_8, n_7, n_6, n_5, n_4, n_3, n_2, n_1, n_0})); + MUX2_X1_LVT i_1_1_15 (.A(n_47), .B(n_15), .S(addr[10]), .Z(rd_data[15])); + MUX2_X1_LVT i_1_1_14 (.A(n_46), .B(n_14), .S(addr[10]), .Z(rd_data[14])); + MUX2_X1_LVT i_1_1_13 (.A(n_45), .B(n_13), .S(addr[10]), .Z(rd_data[13])); + MUX2_X1_LVT i_1_1_12 (.A(n_44), .B(n_12), .S(addr[10]), .Z(rd_data[12])); + MUX2_X1_LVT i_1_1_11 (.A(n_43), .B(n_11), .S(addr[10]), .Z(rd_data[11])); + MUX2_X1_LVT i_1_1_10 (.A(n_42), .B(n_10), .S(addr[10]), .Z(rd_data[10])); + MUX2_X1_LVT i_1_1_9 (.A(n_41), .B(n_9), .S(addr[10]), .Z(rd_data[9])); + MUX2_X1_LVT i_1_1_8 (.A(n_40), .B(n_8), .S(addr[10]), .Z(rd_data[8])); + MUX2_X1_LVT i_1_1_7 (.A(n_39), .B(n_7), .S(addr[10]), .Z(rd_data[7])); + MUX2_X1_LVT i_1_1_6 (.A(n_38), .B(n_6), .S(addr[10]), .Z(rd_data[6])); + MUX2_X1_LVT i_1_1_5 (.A(n_37), .B(n_5), .S(addr[10]), .Z(rd_data[5])); + MUX2_X1_LVT i_1_1_4 (.A(n_36), .B(n_4), .S(addr[10]), .Z(rd_data[4])); + MUX2_X1_LVT i_1_1_3 (.A(n_35), .B(n_3), .S(addr[10]), .Z(rd_data[3])); + MUX2_X1_LVT i_1_1_2 (.A(n_34), .B(n_2), .S(addr[10]), .Z(rd_data[2])); + MUX2_X1_LVT i_1_1_1 (.A(n_33), .B(n_1), .S(addr[10]), .Z(rd_data[1])); + MUX2_X1_LVT i_1_1_0 (.A(n_32), .B(n_0), .S(addr[10]), .Z(rd_data[0])); +endmodule + +module main_mem(clk, reset, DAddr, IAddr, DWData, DRData, IRData, DWE, DWidth); + input clk; + input reset; + input [31:0]DAddr; + input [31:0]IAddr; + input [31:0]DWData; + output [31:0]DRData; + output [31:0]IRData; + input DWE; + input [1:0]DWidth; + + wire [31:0]mem_rdata; + wire [10:0]mem_addr; + wire n_0_0; + wire n_0_0_0; + wire n_0_1; + wire n_0_0_1; + wire n_0_2; + wire n_0_0_2; + wire n_0_3; + wire n_0_0_3; + wire n_0_4; + wire n_0_0_4; + wire n_0_5; + wire n_0_0_5; + wire n_0_6; + wire n_0_0_6; + wire n_0_7; + wire n_0_0_7; + wire n_0_8; + wire n_0_0_8; + wire n_0_9; + wire n_0_0_9; + wire n_0_10; + wire n_0_0_10; + wire n_0_0_11; + wire n_0_11; + wire n_0_0_12; + wire n_0_0_13; + wire n_0_12; + wire n_0_0_14; + wire n_0_0_15; + wire n_0_13; + wire n_0_0_16; + wire n_0_0_17; + wire n_0_14; + wire n_0_0_18; + wire n_0_0_19; + wire n_0_15; + wire n_0_0_20; + wire n_0_0_21; + wire n_0_16; + wire n_0_0_22; + wire n_0_0_23; + wire n_0_17; + wire n_0_0_24; + wire n_0_0_25; + wire n_0_18; + wire n_0_0_26; + wire n_0_0_27; + wire n_0_0_28; + wire n_0_19; + wire n_0_0_29; + wire n_0_20; + wire n_0_0_30; + wire n_0_21; + wire n_0_0_31; + wire n_0_22; + wire n_0_0_32; + wire n_0_23; + wire n_0_0_33; + wire n_0_24; + wire n_0_0_34; + wire n_0_25; + wire n_0_0_35; + wire n_0_26; + wire n_0_0_36; + wire n_0_0_37; + wire n_0_27; + wire n_0_28; + wire n_0_29; + wire n_0_30; + wire n_0_31; + wire n_0_32; + wire n_0_33; + wire n_0_34; + wire n_0_35; + wire n_0_36; + wire n_0_37; + wire n_0_38; + wire n_0_39; + wire n_0_40; + wire n_0_41; + wire n_0_42; + wire n_0_65; + wire n_0_64; + wire n_0_63; + wire n_0_62; + wire n_0_61; + wire n_0_60; + wire n_0_59; + wire n_0_58; + wire n_0_0_38; + wire n_0_0_39; + wire n_0_57; + wire n_0_0_40; + wire n_0_56; + wire n_0_0_41; + wire n_0_55; + wire n_0_0_42; + wire n_0_54; + wire n_0_0_43; + wire n_0_53; + wire n_0_0_44; + wire n_0_52; + wire n_0_0_45; + wire n_0_51; + wire n_0_0_46; + wire n_0_50; + wire n_0_0_47; + wire n_0_0_48; + wire n_0_0_49; + wire n_0_0_50; + wire n_0_0_51; + wire n_0_49; + wire n_0_0_52; + wire n_0_48; + wire n_0_0_53; + wire n_0_47; + wire n_0_0_54; + wire n_0_46; + wire n_0_0_55; + wire n_0_45; + wire n_0_0_56; + wire n_0_44; + wire n_0_0_57; + wire n_0_66; + wire n_0_0_58; + wire n_0_67; + wire n_0_0_59; + wire n_0_0_60; + wire n_0_0_61; + wire n_0_68; + wire n_0_0_62; + wire n_0_0_63; + wire n_0_69; + wire n_0_0_64; + wire n_0_0_65; + wire n_0_70; + wire n_0_0_66; + wire n_0_0_67; + wire n_0_71; + wire n_0_0_68; + wire n_0_0_69; + wire n_0_72; + wire n_0_0_70; + wire n_0_0_71; + wire n_0_73; + wire n_0_0_72; + wire n_0_0_73; + wire n_0_74; + wire n_0_0_74; + wire n_0_0_75; + wire n_0_75; + wire n_0_0_76; + wire n_0_0_77; + wire n_0_0_78; + wire n_0_0_79; + wire n_0_0_80; + wire n_0_0_81; + wire n_0_0_82; + wire n_0_0_83; + wire n_0_0_84; + wire n_0_0_85; + wire n_0_0_86; + wire n_0_0_87; + wire n_0_0_88; + wire n_0_0_89; + wire n_0_0_90; + wire n_0_0_91; + wire n_0_0_92; + wire n_0_43; + wire n_0_0_93; + wire n_0_0_94; + wire n_0_76; + wire n_0_0_95; + wire [31:0]drTmp; + wire [31:0]mem_wdata; + + INV_X1_LVT i_0_0_171 (.A(DWE), .ZN(n_0)); + NOR2_X1_LVT i_0_0_163 (.A1(n_0), .A2(reset), .ZN(n_0_0_88)); + NOR2_X1_LVT i_0_0_22 (.A1(DWE), .A2(reset), .ZN(n_0_0_11)); + AOI22_X1_LVT i_0_0_21 (.A1(DAddr[12]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[12]), .ZN(n_0_0_10)); + INV_X1_LVT i_0_0_20 (.A(n_0_0_10), .ZN(n_0_10)); + INV_X1_LVT i_0_0_172 (.A(clk), .ZN(n_0_76)); + DFF_X1_LVT \mem_addr_reg[10] (.D(n_0_10), .CK(n_0_76), .Q(mem_addr[10]), + .QN()); + AOI22_X1_LVT i_0_0_19 (.A1(DAddr[11]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[11]), .ZN(n_0_0_9)); + INV_X1_LVT i_0_0_18 (.A(n_0_0_9), .ZN(n_0_9)); + DFF_X1_LVT \mem_addr_reg[9] (.D(n_0_9), .CK(n_0_76), .Q(mem_addr[9]), .QN()); + AOI22_X1_LVT i_0_0_17 (.A1(DAddr[10]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[10]), .ZN(n_0_0_8)); + INV_X1_LVT i_0_0_16 (.A(n_0_0_8), .ZN(n_0_8)); + DFF_X1_LVT \mem_addr_reg[8] (.D(n_0_8), .CK(n_0_76), .Q(mem_addr[8]), .QN()); + AOI22_X1_LVT i_0_0_15 (.A1(DAddr[9]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[9]), .ZN(n_0_0_7)); + INV_X1_LVT i_0_0_14 (.A(n_0_0_7), .ZN(n_0_7)); + DFF_X1_LVT \mem_addr_reg[7] (.D(n_0_7), .CK(n_0_76), .Q(mem_addr[7]), .QN()); + AOI22_X1_LVT i_0_0_13 (.A1(DAddr[8]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[8]), .ZN(n_0_0_6)); + INV_X1_LVT i_0_0_12 (.A(n_0_0_6), .ZN(n_0_6)); + DFF_X1_LVT \mem_addr_reg[6] (.D(n_0_6), .CK(n_0_76), .Q(mem_addr[6]), .QN()); + AOI22_X1_LVT i_0_0_11 (.A1(DAddr[7]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[7]), .ZN(n_0_0_5)); + INV_X1_LVT i_0_0_10 (.A(n_0_0_5), .ZN(n_0_5)); + DFF_X1_LVT \mem_addr_reg[5] (.D(n_0_5), .CK(n_0_76), .Q(mem_addr[5]), .QN()); + AOI22_X1_LVT i_0_0_9 (.A1(DAddr[6]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[6]), .ZN(n_0_0_4)); + INV_X1_LVT i_0_0_8 (.A(n_0_0_4), .ZN(n_0_4)); + DFF_X1_LVT \mem_addr_reg[4] (.D(n_0_4), .CK(n_0_76), .Q(mem_addr[4]), .QN()); + AOI22_X1_LVT i_0_0_7 (.A1(DAddr[5]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[5]), .ZN(n_0_0_3)); + INV_X1_LVT i_0_0_6 (.A(n_0_0_3), .ZN(n_0_3)); + DFF_X1_LVT \mem_addr_reg[3] (.D(n_0_3), .CK(n_0_76), .Q(mem_addr[3]), .QN()); + AOI22_X1_LVT i_0_0_5 (.A1(DAddr[4]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[4]), .ZN(n_0_0_2)); + INV_X1_LVT i_0_0_4 (.A(n_0_0_2), .ZN(n_0_2)); + DFF_X1_LVT \mem_addr_reg[2] (.D(n_0_2), .CK(n_0_76), .Q(mem_addr[2]), .QN()); + AOI22_X1_LVT i_0_0_3 (.A1(DAddr[3]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[3]), .ZN(n_0_0_1)); + INV_X1_LVT i_0_0_2 (.A(n_0_0_1), .ZN(n_0_1)); + DFF_X1_LVT \mem_addr_reg[1] (.D(n_0_1), .CK(n_0_76), .Q(mem_addr[1]), .QN()); + AOI22_X1_LVT i_0_0_1 (.A1(DAddr[2]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[2]), .ZN(n_0_0_0)); + INV_X1_LVT i_0_0_0 (.A(n_0_0_0), .ZN(n_0_0)); + DFF_X1_LVT \mem_addr_reg[0] (.D(n_0_0), .CK(n_0_76), .Q(mem_addr[0]), .QN()); + NOR2_X1_LVT i_0_0_162 (.A1(DWidth[1]), .A2(DAddr[1]), .ZN(n_0_0_87)); + NOR2_X1_LVT i_0_0_158 (.A1(DWidth[0]), .A2(DAddr[0]), .ZN(n_0_0_83)); + AND2_X1_LVT i_0_0_157 (.A1(n_0_0_87), .A2(n_0_0_83), .ZN(n_0_0_82)); + AND2_X1_LVT i_0_0_156 (.A1(n_0_0_88), .A2(n_0_0_82), .ZN(n_0_0_81)); + INV_X1_LVT i_0_0_173 (.A(n_0_0_88), .ZN(n_0_0_95)); + INV_X1_LVT i_0_0_169 (.A(DWidth[1]), .ZN(n_0_0_93)); + NOR3_X1_LVT i_0_0_155 (.A1(n_0_0_95), .A2(DWidth[0]), .A3(n_0_0_93), .ZN( + n_0_0_80)); + AOI22_X1_LVT i_0_0_154 (.A1(DWData[7]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[31]), .ZN(n_0_0_79)); + NAND2_X1_LVT i_0_0_168 (.A1(DWidth[0]), .A2(DWidth[1]), .ZN(n_0_43)); + INV_X1_LVT i_0_0_167 (.A(n_0_43), .ZN(n_0_0_92)); + NOR2_X1_LVT i_0_0_160 (.A1(n_0_0_95), .A2(n_0_0_92), .ZN(n_0_0_85)); + NAND2_X1_LVT i_0_0_161 (.A1(n_0_0_93), .A2(DAddr[1]), .ZN(n_0_0_86)); + NOR2_X1_LVT i_0_0_166 (.A1(DWidth[0]), .A2(DWidth[1]), .ZN(n_0_0_91)); + NAND2_X1_LVT i_0_0_164 (.A1(DAddr[0]), .A2(n_0_0_91), .ZN(n_0_0_89)); + NAND3_X1_LVT i_0_0_159 (.A1(n_0_0_85), .A2(n_0_0_86), .A3(n_0_0_89), .ZN( + n_0_0_84)); + INV_X1_LVT i_0_0_170 (.A(DWidth[0]), .ZN(n_0_0_94)); + NOR2_X1_LVT i_0_0_153 (.A1(n_0_0_94), .A2(DAddr[1]), .ZN(n_0_0_78)); + AND3_X1_LVT i_0_0_152 (.A1(n_0_0_88), .A2(n_0_0_78), .A3(n_0_0_93), .ZN( + n_0_0_77)); + AOI22_X1_LVT i_0_0_151 (.A1(n_0_0_84), .A2(mem_wdata[31]), .B1(DWData[15]), + .B2(n_0_0_77), .ZN(n_0_0_76)); + NAND2_X1_LVT i_0_0_150 (.A1(n_0_0_79), .A2(n_0_0_76), .ZN(n_0_75)); + DFF_X1_LVT \mem_wdata_reg[31] (.D(n_0_75), .CK(n_0_76), .Q(mem_wdata[31]), + .QN()); + AOI22_X1_LVT i_0_0_149 (.A1(DWData[6]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[30]), .ZN(n_0_0_75)); + AOI22_X1_LVT i_0_0_148 (.A1(n_0_0_84), .A2(mem_wdata[30]), .B1(DWData[14]), + .B2(n_0_0_77), .ZN(n_0_0_74)); + NAND2_X1_LVT i_0_0_147 (.A1(n_0_0_75), .A2(n_0_0_74), .ZN(n_0_74)); + DFF_X1_LVT \mem_wdata_reg[30] (.D(n_0_74), .CK(n_0_76), .Q(mem_wdata[30]), + .QN()); + AOI22_X1_LVT i_0_0_146 (.A1(DWData[5]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[29]), .ZN(n_0_0_73)); + AOI22_X1_LVT i_0_0_145 (.A1(n_0_0_84), .A2(mem_wdata[29]), .B1(DWData[13]), + .B2(n_0_0_77), .ZN(n_0_0_72)); + NAND2_X1_LVT i_0_0_144 (.A1(n_0_0_73), .A2(n_0_0_72), .ZN(n_0_73)); + DFF_X1_LVT \mem_wdata_reg[29] (.D(n_0_73), .CK(n_0_76), .Q(mem_wdata[29]), + .QN()); + AOI22_X1_LVT i_0_0_143 (.A1(DWData[4]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[28]), .ZN(n_0_0_71)); + AOI22_X1_LVT i_0_0_142 (.A1(n_0_0_84), .A2(mem_wdata[28]), .B1(DWData[12]), + .B2(n_0_0_77), .ZN(n_0_0_70)); + NAND2_X1_LVT i_0_0_141 (.A1(n_0_0_71), .A2(n_0_0_70), .ZN(n_0_72)); + DFF_X1_LVT \mem_wdata_reg[28] (.D(n_0_72), .CK(n_0_76), .Q(mem_wdata[28]), + .QN()); + AOI22_X1_LVT i_0_0_140 (.A1(DWData[3]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[27]), .ZN(n_0_0_69)); + AOI22_X1_LVT i_0_0_139 (.A1(n_0_0_84), .A2(mem_wdata[27]), .B1(DWData[11]), + .B2(n_0_0_77), .ZN(n_0_0_68)); + NAND2_X1_LVT i_0_0_138 (.A1(n_0_0_69), .A2(n_0_0_68), .ZN(n_0_71)); + DFF_X1_LVT \mem_wdata_reg[27] (.D(n_0_71), .CK(n_0_76), .Q(mem_wdata[27]), + .QN()); + AOI22_X1_LVT i_0_0_137 (.A1(DWData[2]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[26]), .ZN(n_0_0_67)); + AOI22_X1_LVT i_0_0_136 (.A1(n_0_0_84), .A2(mem_wdata[26]), .B1(DWData[10]), + .B2(n_0_0_77), .ZN(n_0_0_66)); + NAND2_X1_LVT i_0_0_135 (.A1(n_0_0_67), .A2(n_0_0_66), .ZN(n_0_70)); + DFF_X1_LVT \mem_wdata_reg[26] (.D(n_0_70), .CK(n_0_76), .Q(mem_wdata[26]), + .QN()); + AOI22_X1_LVT i_0_0_134 (.A1(DWData[1]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[25]), .ZN(n_0_0_65)); + AOI22_X1_LVT i_0_0_133 (.A1(n_0_0_84), .A2(mem_wdata[25]), .B1(DWData[9]), + .B2(n_0_0_77), .ZN(n_0_0_64)); + NAND2_X1_LVT i_0_0_132 (.A1(n_0_0_65), .A2(n_0_0_64), .ZN(n_0_69)); + DFF_X1_LVT \mem_wdata_reg[25] (.D(n_0_69), .CK(n_0_76), .Q(mem_wdata[25]), + .QN()); + AOI22_X1_LVT i_0_0_131 (.A1(DWData[0]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[24]), .ZN(n_0_0_63)); + AOI22_X1_LVT i_0_0_130 (.A1(n_0_0_84), .A2(mem_wdata[24]), .B1(DWData[8]), + .B2(n_0_0_77), .ZN(n_0_0_62)); + NAND2_X1_LVT i_0_0_129 (.A1(n_0_0_63), .A2(n_0_0_62), .ZN(n_0_68)); + DFF_X1_LVT \mem_wdata_reg[24] (.D(n_0_68), .CK(n_0_76), .Q(mem_wdata[24]), + .QN()); + NOR4_X1_LVT i_0_0_127 (.A1(n_0_0_95), .A2(n_0_0_83), .A3(DWidth[1]), .A4( + DAddr[1]), .ZN(n_0_0_60)); + INV_X1_LVT i_0_0_165 (.A(n_0_0_91), .ZN(n_0_0_90)); + OAI211_X1_LVT i_0_0_128 (.A(n_0_0_85), .B(n_0_0_86), .C1(n_0_0_90), .C2( + DAddr[0]), .ZN(n_0_0_61)); + AOI222_X1_LVT i_0_0_126 (.A1(DWData[7]), .A2(n_0_0_60), .B1(mem_wdata[23]), + .B2(n_0_0_61), .C1(DWData[23]), .C2(n_0_0_80), .ZN(n_0_0_59)); + INV_X1_LVT i_0_0_125 (.A(n_0_0_59), .ZN(n_0_67)); + DFF_X1_LVT \mem_wdata_reg[23] (.D(n_0_67), .CK(n_0_76), .Q(mem_wdata[23]), + .QN()); + AOI222_X1_LVT i_0_0_124 (.A1(DWData[6]), .A2(n_0_0_60), .B1(mem_wdata[22]), + .B2(n_0_0_61), .C1(DWData[22]), .C2(n_0_0_80), .ZN(n_0_0_58)); + INV_X1_LVT i_0_0_123 (.A(n_0_0_58), .ZN(n_0_66)); + DFF_X1_LVT \mem_wdata_reg[22] (.D(n_0_66), .CK(n_0_76), .Q(mem_wdata[22]), + .QN()); + AOI222_X1_LVT i_0_0_122 (.A1(DWData[5]), .A2(n_0_0_60), .B1(mem_wdata[21]), + .B2(n_0_0_61), .C1(DWData[21]), .C2(n_0_0_80), .ZN(n_0_0_57)); + INV_X1_LVT i_0_0_121 (.A(n_0_0_57), .ZN(n_0_44)); + DFF_X1_LVT \mem_wdata_reg[21] (.D(n_0_44), .CK(n_0_76), .Q(mem_wdata[21]), + .QN()); + AOI222_X1_LVT i_0_0_120 (.A1(DWData[4]), .A2(n_0_0_60), .B1(mem_wdata[20]), + .B2(n_0_0_61), .C1(DWData[20]), .C2(n_0_0_80), .ZN(n_0_0_56)); + INV_X1_LVT i_0_0_119 (.A(n_0_0_56), .ZN(n_0_45)); + DFF_X1_LVT \mem_wdata_reg[20] (.D(n_0_45), .CK(n_0_76), .Q(mem_wdata[20]), + .QN()); + AOI222_X1_LVT i_0_0_118 (.A1(DWData[3]), .A2(n_0_0_60), .B1(mem_wdata[19]), + .B2(n_0_0_61), .C1(DWData[19]), .C2(n_0_0_80), .ZN(n_0_0_55)); + INV_X1_LVT i_0_0_117 (.A(n_0_0_55), .ZN(n_0_46)); + DFF_X1_LVT \mem_wdata_reg[19] (.D(n_0_46), .CK(n_0_76), .Q(mem_wdata[19]), + .QN()); + AOI222_X1_LVT i_0_0_116 (.A1(DWData[2]), .A2(n_0_0_60), .B1(mem_wdata[18]), + .B2(n_0_0_61), .C1(DWData[18]), .C2(n_0_0_80), .ZN(n_0_0_54)); + INV_X1_LVT i_0_0_115 (.A(n_0_0_54), .ZN(n_0_47)); + DFF_X1_LVT \mem_wdata_reg[18] (.D(n_0_47), .CK(n_0_76), .Q(mem_wdata[18]), + .QN()); + AOI222_X1_LVT i_0_0_114 (.A1(DWData[1]), .A2(n_0_0_60), .B1(mem_wdata[17]), + .B2(n_0_0_61), .C1(DWData[17]), .C2(n_0_0_80), .ZN(n_0_0_53)); + INV_X1_LVT i_0_0_113 (.A(n_0_0_53), .ZN(n_0_48)); + DFF_X1_LVT \mem_wdata_reg[17] (.D(n_0_48), .CK(n_0_76), .Q(mem_wdata[17]), + .QN()); + AOI222_X1_LVT i_0_0_112 (.A1(DWData[0]), .A2(n_0_0_60), .B1(mem_wdata[16]), + .B2(n_0_0_61), .C1(DWData[16]), .C2(n_0_0_80), .ZN(n_0_0_52)); + INV_X1_LVT i_0_0_111 (.A(n_0_0_52), .ZN(n_0_49)); + DFF_X1_LVT \mem_wdata_reg[16] (.D(n_0_49), .CK(n_0_76), .Q(mem_wdata[16]), + .QN()); + NOR4_X1_LVT i_0_0_110 (.A1(n_0_0_95), .A2(n_0_0_87), .A3(n_0_0_92), .A4( + n_0_0_91), .ZN(n_0_0_51)); + NOR3_X1_LVT i_0_0_109 (.A1(n_0_0_86), .A2(DAddr[0]), .A3(DWidth[0]), .ZN( + n_0_0_50)); + AND2_X1_LVT i_0_0_108 (.A1(n_0_0_88), .A2(n_0_0_50), .ZN(n_0_0_49)); + OAI211_X1_LVT i_0_0_107 (.A(n_0_0_85), .B(n_0_0_89), .C1(DAddr[1]), .C2( + DWidth[1]), .ZN(n_0_0_48)); + AOI222_X1_LVT i_0_0_106 (.A1(DWData[15]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[7]), .C1(n_0_0_48), .C2(mem_wdata[15]), .ZN(n_0_0_47)); + INV_X1_LVT i_0_0_105 (.A(n_0_0_47), .ZN(n_0_50)); + DFF_X1_LVT \mem_wdata_reg[15] (.D(n_0_50), .CK(n_0_76), .Q(mem_wdata[15]), + .QN()); + AOI222_X1_LVT i_0_0_104 (.A1(DWData[14]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[6]), .C1(n_0_0_48), .C2(mem_wdata[14]), .ZN(n_0_0_46)); + INV_X1_LVT i_0_0_103 (.A(n_0_0_46), .ZN(n_0_51)); + DFF_X1_LVT \mem_wdata_reg[14] (.D(n_0_51), .CK(n_0_76), .Q(mem_wdata[14]), + .QN()); + AOI222_X1_LVT i_0_0_102 (.A1(DWData[13]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[5]), .C1(n_0_0_48), .C2(mem_wdata[13]), .ZN(n_0_0_45)); + INV_X1_LVT i_0_0_101 (.A(n_0_0_45), .ZN(n_0_52)); + DFF_X1_LVT \mem_wdata_reg[13] (.D(n_0_52), .CK(n_0_76), .Q(mem_wdata[13]), + .QN()); + AOI222_X1_LVT i_0_0_100 (.A1(DWData[12]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[4]), .C1(n_0_0_48), .C2(mem_wdata[12]), .ZN(n_0_0_44)); + INV_X1_LVT i_0_0_99 (.A(n_0_0_44), .ZN(n_0_53)); + DFF_X1_LVT \mem_wdata_reg[12] (.D(n_0_53), .CK(n_0_76), .Q(mem_wdata[12]), + .QN()); + AOI222_X1_LVT i_0_0_98 (.A1(DWData[11]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[3]), .C1(n_0_0_48), .C2(mem_wdata[11]), .ZN(n_0_0_43)); + INV_X1_LVT i_0_0_97 (.A(n_0_0_43), .ZN(n_0_54)); + DFF_X1_LVT \mem_wdata_reg[11] (.D(n_0_54), .CK(n_0_76), .Q(mem_wdata[11]), + .QN()); + AOI222_X1_LVT i_0_0_96 (.A1(DWData[10]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[2]), .C1(n_0_0_48), .C2(mem_wdata[10]), .ZN(n_0_0_42)); + INV_X1_LVT i_0_0_95 (.A(n_0_0_42), .ZN(n_0_55)); + DFF_X1_LVT \mem_wdata_reg[10] (.D(n_0_55), .CK(n_0_76), .Q(mem_wdata[10]), + .QN()); + AOI222_X1_LVT i_0_0_94 (.A1(DWData[9]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[1]), .C1(n_0_0_48), .C2(mem_wdata[9]), .ZN(n_0_0_41)); + INV_X1_LVT i_0_0_93 (.A(n_0_0_41), .ZN(n_0_56)); + DFF_X1_LVT \mem_wdata_reg[9] (.D(n_0_56), .CK(n_0_76), .Q(mem_wdata[9]), + .QN()); + AOI222_X1_LVT i_0_0_92 (.A1(DWData[8]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[0]), .C1(n_0_0_48), .C2(mem_wdata[8]), .ZN(n_0_0_40)); + INV_X1_LVT i_0_0_91 (.A(n_0_0_40), .ZN(n_0_57)); + DFF_X1_LVT \mem_wdata_reg[8] (.D(n_0_57), .CK(n_0_76), .Q(mem_wdata[8]), + .QN()); + AOI21_X1_LVT i_0_0_90 (.A(n_0_0_87), .B1(n_0_0_83), .B2(n_0_0_93), .ZN( + n_0_0_39)); + NAND2_X1_LVT i_0_0_89 (.A1(n_0_0_85), .A2(n_0_0_39), .ZN(n_0_0_38)); + MUX2_X1_LVT i_0_0_88 (.A(DWData[7]), .B(mem_wdata[7]), .S(n_0_0_38), .Z( + n_0_58)); + DFF_X1_LVT \mem_wdata_reg[7] (.D(n_0_58), .CK(n_0_76), .Q(mem_wdata[7]), + .QN()); + MUX2_X1_LVT i_0_0_87 (.A(DWData[6]), .B(mem_wdata[6]), .S(n_0_0_38), .Z( + n_0_59)); + DFF_X1_LVT \mem_wdata_reg[6] (.D(n_0_59), .CK(n_0_76), .Q(mem_wdata[6]), + .QN()); + MUX2_X1_LVT i_0_0_86 (.A(DWData[5]), .B(mem_wdata[5]), .S(n_0_0_38), .Z( + n_0_60)); + DFF_X1_LVT \mem_wdata_reg[5] (.D(n_0_60), .CK(n_0_76), .Q(mem_wdata[5]), + .QN()); + MUX2_X1_LVT i_0_0_85 (.A(DWData[4]), .B(mem_wdata[4]), .S(n_0_0_38), .Z( + n_0_61)); + DFF_X1_LVT \mem_wdata_reg[4] (.D(n_0_61), .CK(n_0_76), .Q(mem_wdata[4]), + .QN()); + MUX2_X1_LVT i_0_0_84 (.A(DWData[3]), .B(mem_wdata[3]), .S(n_0_0_38), .Z( + n_0_62)); + DFF_X1_LVT \mem_wdata_reg[3] (.D(n_0_62), .CK(n_0_76), .Q(mem_wdata[3]), + .QN()); + MUX2_X1_LVT i_0_0_83 (.A(DWData[2]), .B(mem_wdata[2]), .S(n_0_0_38), .Z( + n_0_63)); + DFF_X1_LVT \mem_wdata_reg[2] (.D(n_0_63), .CK(n_0_76), .Q(mem_wdata[2]), + .QN()); + MUX2_X1_LVT i_0_0_82 (.A(DWData[1]), .B(mem_wdata[1]), .S(n_0_0_38), .Z( + n_0_64)); + DFF_X1_LVT \mem_wdata_reg[1] (.D(n_0_64), .CK(n_0_76), .Q(mem_wdata[1]), + .QN()); + MUX2_X1_LVT i_0_0_81 (.A(DWData[0]), .B(mem_wdata[0]), .S(n_0_0_38), .Z( + n_0_65)); + DFF_X1_LVT \mem_wdata_reg[0] (.D(n_0_65), .CK(n_0_76), .Q(mem_wdata[0]), + .QN()); + MemGen_32_11 RAM (.chip_en(), .clock(clk), .addr(mem_addr), .rd_data( + mem_rdata), .rd_en(n_0), .wr_en(DWE), .wr_data(mem_wdata)); + DFF_X1_LVT \drTmp_reg[31] (.D(mem_rdata[31]), .CK(n_0_76), .Q(drTmp[31]), + .QN()); + AND2_X1_LVT i_0_0_80 (.A1(DWidth[1]), .A2(drTmp[31]), .ZN(n_0_42)); + DLH_X1_LVT \DRData[31] (.D(n_0_42), .G(n_0_43), .Q(DRData[31])); + DFF_X1_LVT \drTmp_reg[30] (.D(mem_rdata[30]), .CK(n_0_76), .Q(drTmp[30]), + .QN()); + AND2_X1_LVT i_0_0_79 (.A1(DWidth[1]), .A2(drTmp[30]), .ZN(n_0_41)); + DLH_X1_LVT \DRData[30] (.D(n_0_41), .G(n_0_43), .Q(DRData[30])); + DFF_X1_LVT \drTmp_reg[29] (.D(mem_rdata[29]), .CK(n_0_76), .Q(drTmp[29]), + .QN()); + AND2_X1_LVT i_0_0_78 (.A1(DWidth[1]), .A2(drTmp[29]), .ZN(n_0_40)); + DLH_X1_LVT \DRData[29] (.D(n_0_40), .G(n_0_43), .Q(DRData[29])); + DFF_X1_LVT \drTmp_reg[28] (.D(mem_rdata[28]), .CK(n_0_76), .Q(drTmp[28]), + .QN()); + AND2_X1_LVT i_0_0_77 (.A1(DWidth[1]), .A2(drTmp[28]), .ZN(n_0_39)); + DLH_X1_LVT \DRData[28] (.D(n_0_39), .G(n_0_43), .Q(DRData[28])); + DFF_X1_LVT \drTmp_reg[27] (.D(mem_rdata[27]), .CK(n_0_76), .Q(drTmp[27]), + .QN()); + AND2_X1_LVT i_0_0_76 (.A1(DWidth[1]), .A2(drTmp[27]), .ZN(n_0_38)); + DLH_X1_LVT \DRData[27] (.D(n_0_38), .G(n_0_43), .Q(DRData[27])); + DFF_X1_LVT \drTmp_reg[26] (.D(mem_rdata[26]), .CK(n_0_76), .Q(drTmp[26]), + .QN()); + AND2_X1_LVT i_0_0_75 (.A1(DWidth[1]), .A2(drTmp[26]), .ZN(n_0_37)); + DLH_X1_LVT \DRData[26] (.D(n_0_37), .G(n_0_43), .Q(DRData[26])); + DFF_X1_LVT \drTmp_reg[25] (.D(mem_rdata[25]), .CK(n_0_76), .Q(drTmp[25]), + .QN()); + AND2_X1_LVT i_0_0_74 (.A1(DWidth[1]), .A2(drTmp[25]), .ZN(n_0_36)); + DLH_X1_LVT \DRData[25] (.D(n_0_36), .G(n_0_43), .Q(DRData[25])); + DFF_X1_LVT \drTmp_reg[24] (.D(mem_rdata[24]), .CK(n_0_76), .Q(drTmp[24]), + .QN()); + AND2_X1_LVT i_0_0_73 (.A1(DWidth[1]), .A2(drTmp[24]), .ZN(n_0_35)); + DLH_X1_LVT \DRData[24] (.D(n_0_35), .G(n_0_43), .Q(DRData[24])); + DFF_X1_LVT \drTmp_reg[23] (.D(mem_rdata[23]), .CK(n_0_76), .Q(drTmp[23]), + .QN()); + AND2_X1_LVT i_0_0_72 (.A1(DWidth[1]), .A2(drTmp[23]), .ZN(n_0_34)); + DLH_X1_LVT \DRData[23] (.D(n_0_34), .G(n_0_43), .Q(DRData[23])); + DFF_X1_LVT \drTmp_reg[22] (.D(mem_rdata[22]), .CK(n_0_76), .Q(drTmp[22]), + .QN()); + AND2_X1_LVT i_0_0_71 (.A1(DWidth[1]), .A2(drTmp[22]), .ZN(n_0_33)); + DLH_X1_LVT \DRData[22] (.D(n_0_33), .G(n_0_43), .Q(DRData[22])); + DFF_X1_LVT \drTmp_reg[21] (.D(mem_rdata[21]), .CK(n_0_76), .Q(drTmp[21]), + .QN()); + AND2_X1_LVT i_0_0_70 (.A1(DWidth[1]), .A2(drTmp[21]), .ZN(n_0_32)); + DLH_X1_LVT \DRData[21] (.D(n_0_32), .G(n_0_43), .Q(DRData[21])); + DFF_X1_LVT \drTmp_reg[20] (.D(mem_rdata[20]), .CK(n_0_76), .Q(drTmp[20]), + .QN()); + AND2_X1_LVT i_0_0_69 (.A1(DWidth[1]), .A2(drTmp[20]), .ZN(n_0_31)); + DLH_X1_LVT \DRData[20] (.D(n_0_31), .G(n_0_43), .Q(DRData[20])); + DFF_X1_LVT \drTmp_reg[19] (.D(mem_rdata[19]), .CK(n_0_76), .Q(drTmp[19]), + .QN()); + AND2_X1_LVT i_0_0_68 (.A1(DWidth[1]), .A2(drTmp[19]), .ZN(n_0_30)); + DLH_X1_LVT \DRData[19] (.D(n_0_30), .G(n_0_43), .Q(DRData[19])); + DFF_X1_LVT \drTmp_reg[18] (.D(mem_rdata[18]), .CK(n_0_76), .Q(drTmp[18]), + .QN()); + AND2_X1_LVT i_0_0_67 (.A1(DWidth[1]), .A2(drTmp[18]), .ZN(n_0_29)); + DLH_X1_LVT \DRData[18] (.D(n_0_29), .G(n_0_43), .Q(DRData[18])); + DFF_X1_LVT \drTmp_reg[17] (.D(mem_rdata[17]), .CK(n_0_76), .Q(drTmp[17]), + .QN()); + AND2_X1_LVT i_0_0_66 (.A1(DWidth[1]), .A2(drTmp[17]), .ZN(n_0_28)); + DLH_X1_LVT \DRData[17] (.D(n_0_28), .G(n_0_43), .Q(DRData[17])); + DFF_X1_LVT \drTmp_reg[16] (.D(mem_rdata[16]), .CK(n_0_76), .Q(drTmp[16]), + .QN()); + AND2_X1_LVT i_0_0_65 (.A1(DWidth[1]), .A2(drTmp[16]), .ZN(n_0_27)); + DLH_X1_LVT \DRData[16] (.D(n_0_27), .G(n_0_43), .Q(DRData[16])); + NOR2_X1_LVT i_0_0_64 (.A1(n_0_0_91), .A2(n_0_0_87), .ZN(n_0_0_37)); + DFF_X1_LVT \drTmp_reg[15] (.D(mem_rdata[15]), .CK(n_0_76), .Q(drTmp[15]), + .QN()); + AOI22_X1_LVT i_0_0_63 (.A1(drTmp[31]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[15]), .ZN(n_0_0_36)); + INV_X1_LVT i_0_0_62 (.A(n_0_0_36), .ZN(n_0_26)); + DLH_X1_LVT \DRData[15] (.D(n_0_26), .G(n_0_43), .Q(DRData[15])); + DFF_X1_LVT \drTmp_reg[14] (.D(mem_rdata[14]), .CK(n_0_76), .Q(drTmp[14]), + .QN()); + AOI22_X1_LVT i_0_0_61 (.A1(drTmp[30]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[14]), .ZN(n_0_0_35)); + INV_X1_LVT i_0_0_60 (.A(n_0_0_35), .ZN(n_0_25)); + DLH_X1_LVT \DRData[14] (.D(n_0_25), .G(n_0_43), .Q(DRData[14])); + DFF_X1_LVT \drTmp_reg[13] (.D(mem_rdata[13]), .CK(n_0_76), .Q(drTmp[13]), + .QN()); + AOI22_X1_LVT i_0_0_59 (.A1(drTmp[29]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[13]), .ZN(n_0_0_34)); + INV_X1_LVT i_0_0_58 (.A(n_0_0_34), .ZN(n_0_24)); + DLH_X1_LVT \DRData[13] (.D(n_0_24), .G(n_0_43), .Q(DRData[13])); + DFF_X1_LVT \drTmp_reg[12] (.D(mem_rdata[12]), .CK(n_0_76), .Q(drTmp[12]), + .QN()); + AOI22_X1_LVT i_0_0_57 (.A1(drTmp[28]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[12]), .ZN(n_0_0_33)); + INV_X1_LVT i_0_0_56 (.A(n_0_0_33), .ZN(n_0_23)); + DLH_X1_LVT \DRData[12] (.D(n_0_23), .G(n_0_43), .Q(DRData[12])); + DFF_X1_LVT \drTmp_reg[11] (.D(mem_rdata[11]), .CK(n_0_76), .Q(drTmp[11]), + .QN()); + AOI22_X1_LVT i_0_0_55 (.A1(drTmp[27]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[11]), .ZN(n_0_0_32)); + INV_X1_LVT i_0_0_54 (.A(n_0_0_32), .ZN(n_0_22)); + DLH_X1_LVT \DRData[11] (.D(n_0_22), .G(n_0_43), .Q(DRData[11])); + DFF_X1_LVT \drTmp_reg[10] (.D(mem_rdata[10]), .CK(n_0_76), .Q(drTmp[10]), + .QN()); + AOI22_X1_LVT i_0_0_53 (.A1(drTmp[26]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[10]), .ZN(n_0_0_31)); + INV_X1_LVT i_0_0_52 (.A(n_0_0_31), .ZN(n_0_21)); + DLH_X1_LVT \DRData[10] (.D(n_0_21), .G(n_0_43), .Q(DRData[10])); + DFF_X1_LVT \drTmp_reg[9] (.D(mem_rdata[9]), .CK(n_0_76), .Q(drTmp[9]), .QN()); + AOI22_X1_LVT i_0_0_51 (.A1(drTmp[25]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[9]), .ZN(n_0_0_30)); + INV_X1_LVT i_0_0_50 (.A(n_0_0_30), .ZN(n_0_20)); + DLH_X1_LVT \DRData[9] (.D(n_0_20), .G(n_0_43), .Q(DRData[9])); + DFF_X1_LVT \drTmp_reg[8] (.D(mem_rdata[8]), .CK(n_0_76), .Q(drTmp[8]), .QN()); + AOI22_X1_LVT i_0_0_49 (.A1(drTmp[24]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[8]), .ZN(n_0_0_29)); + INV_X1_LVT i_0_0_48 (.A(n_0_0_29), .ZN(n_0_19)); + DLH_X1_LVT \DRData[8] (.D(n_0_19), .G(n_0_43), .Q(DRData[8])); + AOI22_X1_LVT i_0_0_46 (.A1(drTmp[31]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[15]), .ZN(n_0_0_27)); + AOI211_X1_LVT i_0_0_47 (.A(DAddr[1]), .B(n_0_0_83), .C1(n_0_0_94), .C2( + DWidth[1]), .ZN(n_0_0_28)); + DFF_X1_LVT \drTmp_reg[7] (.D(mem_rdata[7]), .CK(n_0_76), .Q(drTmp[7]), .QN()); + AOI22_X1_LVT i_0_0_45 (.A1(drTmp[23]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[7]), .ZN(n_0_0_26)); + NAND2_X1_LVT i_0_0_44 (.A1(n_0_0_27), .A2(n_0_0_26), .ZN(n_0_18)); + DLH_X1_LVT \DRData[7] (.D(n_0_18), .G(n_0_43), .Q(DRData[7])); + AOI22_X1_LVT i_0_0_43 (.A1(drTmp[30]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[14]), .ZN(n_0_0_25)); + DFF_X1_LVT \drTmp_reg[6] (.D(mem_rdata[6]), .CK(n_0_76), .Q(drTmp[6]), .QN()); + AOI22_X1_LVT i_0_0_42 (.A1(drTmp[22]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[6]), .ZN(n_0_0_24)); + NAND2_X1_LVT i_0_0_41 (.A1(n_0_0_25), .A2(n_0_0_24), .ZN(n_0_17)); + DLH_X1_LVT \DRData[6] (.D(n_0_17), .G(n_0_43), .Q(DRData[6])); + AOI22_X1_LVT i_0_0_40 (.A1(drTmp[29]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[13]), .ZN(n_0_0_23)); + DFF_X1_LVT \drTmp_reg[5] (.D(mem_rdata[5]), .CK(n_0_76), .Q(drTmp[5]), .QN()); + AOI22_X1_LVT i_0_0_39 (.A1(drTmp[21]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[5]), .ZN(n_0_0_22)); + NAND2_X1_LVT i_0_0_38 (.A1(n_0_0_23), .A2(n_0_0_22), .ZN(n_0_16)); + DLH_X1_LVT \DRData[5] (.D(n_0_16), .G(n_0_43), .Q(DRData[5])); + AOI22_X1_LVT i_0_0_37 (.A1(drTmp[28]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[12]), .ZN(n_0_0_21)); + DFF_X1_LVT \drTmp_reg[4] (.D(mem_rdata[4]), .CK(n_0_76), .Q(drTmp[4]), .QN()); + AOI22_X1_LVT i_0_0_36 (.A1(drTmp[20]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[4]), .ZN(n_0_0_20)); + NAND2_X1_LVT i_0_0_35 (.A1(n_0_0_21), .A2(n_0_0_20), .ZN(n_0_15)); + DLH_X1_LVT \DRData[4] (.D(n_0_15), .G(n_0_43), .Q(DRData[4])); + AOI22_X1_LVT i_0_0_34 (.A1(drTmp[27]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[11]), .ZN(n_0_0_19)); + DFF_X1_LVT \drTmp_reg[3] (.D(mem_rdata[3]), .CK(n_0_76), .Q(drTmp[3]), .QN()); + AOI22_X1_LVT i_0_0_33 (.A1(drTmp[19]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[3]), .ZN(n_0_0_18)); + NAND2_X1_LVT i_0_0_32 (.A1(n_0_0_19), .A2(n_0_0_18), .ZN(n_0_14)); + DLH_X1_LVT \DRData[3] (.D(n_0_14), .G(n_0_43), .Q(DRData[3])); + AOI22_X1_LVT i_0_0_31 (.A1(drTmp[26]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[10]), .ZN(n_0_0_17)); + DFF_X1_LVT \drTmp_reg[2] (.D(mem_rdata[2]), .CK(n_0_76), .Q(drTmp[2]), .QN()); + AOI22_X1_LVT i_0_0_30 (.A1(drTmp[18]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[2]), .ZN(n_0_0_16)); + NAND2_X1_LVT i_0_0_29 (.A1(n_0_0_17), .A2(n_0_0_16), .ZN(n_0_13)); + DLH_X1_LVT \DRData[2] (.D(n_0_13), .G(n_0_43), .Q(DRData[2])); + AOI22_X1_LVT i_0_0_28 (.A1(drTmp[25]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[9]), .ZN(n_0_0_15)); + DFF_X1_LVT \drTmp_reg[1] (.D(mem_rdata[1]), .CK(n_0_76), .Q(drTmp[1]), .QN()); + AOI22_X1_LVT i_0_0_27 (.A1(drTmp[17]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[1]), .ZN(n_0_0_14)); + NAND2_X1_LVT i_0_0_26 (.A1(n_0_0_15), .A2(n_0_0_14), .ZN(n_0_12)); + DLH_X1_LVT \DRData[1] (.D(n_0_12), .G(n_0_43), .Q(DRData[1])); + AOI22_X1_LVT i_0_0_25 (.A1(drTmp[24]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[8]), .ZN(n_0_0_13)); + DFF_X1_LVT \drTmp_reg[0] (.D(mem_rdata[0]), .CK(n_0_76), .Q(drTmp[0]), .QN()); + AOI22_X1_LVT i_0_0_24 (.A1(drTmp[16]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[0]), .ZN(n_0_0_12)); + NAND2_X1_LVT i_0_0_23 (.A1(n_0_0_13), .A2(n_0_0_12), .ZN(n_0_11)); + DLH_X1_LVT \DRData[0] (.D(n_0_11), .G(n_0_43), .Q(DRData[0])); + DFF_X1_LVT \IRData_reg[31] (.D(mem_rdata[31]), .CK(clk), .Q(IRData[31]), + .QN()); + DFF_X1_LVT \IRData_reg[30] (.D(mem_rdata[30]), .CK(clk), .Q(IRData[30]), + .QN()); + DFF_X1_LVT \IRData_reg[29] (.D(mem_rdata[29]), .CK(clk), .Q(IRData[29]), + .QN()); + DFF_X1_LVT \IRData_reg[28] (.D(mem_rdata[28]), .CK(clk), .Q(IRData[28]), + .QN()); + DFF_X1_LVT \IRData_reg[27] (.D(mem_rdata[27]), .CK(clk), .Q(IRData[27]), + .QN()); + DFF_X1_LVT \IRData_reg[26] (.D(mem_rdata[26]), .CK(clk), .Q(IRData[26]), + .QN()); + DFF_X1_LVT \IRData_reg[25] (.D(mem_rdata[25]), .CK(clk), .Q(IRData[25]), + .QN()); + DFF_X1_LVT \IRData_reg[24] (.D(mem_rdata[24]), .CK(clk), .Q(IRData[24]), + .QN()); + DFF_X1_LVT \IRData_reg[23] (.D(mem_rdata[23]), .CK(clk), .Q(IRData[23]), + .QN()); + DFF_X1_LVT \IRData_reg[22] (.D(mem_rdata[22]), .CK(clk), .Q(IRData[22]), + .QN()); + DFF_X1_LVT \IRData_reg[21] (.D(mem_rdata[21]), .CK(clk), .Q(IRData[21]), + .QN()); + DFF_X1_LVT \IRData_reg[20] (.D(mem_rdata[20]), .CK(clk), .Q(IRData[20]), + .QN()); + DFF_X1_LVT \IRData_reg[19] (.D(mem_rdata[19]), .CK(clk), .Q(IRData[19]), + .QN()); + DFF_X1_LVT \IRData_reg[18] (.D(mem_rdata[18]), .CK(clk), .Q(IRData[18]), + .QN()); + DFF_X1_LVT \IRData_reg[17] (.D(mem_rdata[17]), .CK(clk), .Q(IRData[17]), + .QN()); + DFF_X1_LVT \IRData_reg[16] (.D(mem_rdata[16]), .CK(clk), .Q(IRData[16]), + .QN()); + DFF_X1_LVT \IRData_reg[15] (.D(mem_rdata[15]), .CK(clk), .Q(IRData[15]), + .QN()); + DFF_X1_LVT \IRData_reg[14] (.D(mem_rdata[14]), .CK(clk), .Q(IRData[14]), + .QN()); + DFF_X1_LVT \IRData_reg[13] (.D(mem_rdata[13]), .CK(clk), .Q(IRData[13]), + .QN()); + DFF_X1_LVT \IRData_reg[12] (.D(mem_rdata[12]), .CK(clk), .Q(IRData[12]), + .QN()); + DFF_X1_LVT \IRData_reg[11] (.D(mem_rdata[11]), .CK(clk), .Q(IRData[11]), + .QN()); + DFF_X1_LVT \IRData_reg[10] (.D(mem_rdata[10]), .CK(clk), .Q(IRData[10]), + .QN()); + DFF_X1_LVT \IRData_reg[9] (.D(mem_rdata[9]), .CK(clk), .Q(IRData[9]), .QN()); + DFF_X1_LVT \IRData_reg[8] (.D(mem_rdata[8]), .CK(clk), .Q(IRData[8]), .QN()); + DFF_X1_LVT \IRData_reg[7] (.D(mem_rdata[7]), .CK(clk), .Q(IRData[7]), .QN()); + DFF_X1_LVT \IRData_reg[6] (.D(mem_rdata[6]), .CK(clk), .Q(IRData[6]), .QN()); + DFF_X1_LVT \IRData_reg[5] (.D(mem_rdata[5]), .CK(clk), .Q(IRData[5]), .QN()); + DFF_X1_LVT \IRData_reg[4] (.D(mem_rdata[4]), .CK(clk), .Q(IRData[4]), .QN()); + DFF_X1_LVT \IRData_reg[3] (.D(mem_rdata[3]), .CK(clk), .Q(IRData[3]), .QN()); + DFF_X1_LVT \IRData_reg[2] (.D(mem_rdata[2]), .CK(clk), .Q(IRData[2]), .QN()); + DFF_X1_LVT \IRData_reg[1] (.D(mem_rdata[1]), .CK(clk), .Q(IRData[1]), .QN()); + DFF_X1_LVT \IRData_reg[0] (.D(mem_rdata[0]), .CK(clk), .Q(IRData[0]), .QN()); +endmodule + +module datapathS__0_28(b_imm, CurrentPC, p_0); + input [31:0]b_imm; + input [31:0]CurrentPC; + output [31:0]p_0; + + INV_X1_LVT i_1 (.A(CurrentPC[13]), .ZN(n_1)); + XNOR2_X1_LVT i_32 (.A(CurrentPC[31]), .B(n_1), .ZN(n_32)); + INV_X1_LVT i_0 (.A(b_imm[12]), .ZN(n_0)); + HA_X1_LVT i_2 (.A(b_imm[1]), .B(CurrentPC[1]), .CO(n_2), .S(p_0[1])); + FA_X1_LVT i_3 (.A(b_imm[2]), .B(CurrentPC[2]), .CI(n_2), .CO(n_3), .S(p_0[2])); + FA_X1_LVT i_4 (.A(b_imm[3]), .B(CurrentPC[3]), .CI(n_3), .CO(n_4), .S(p_0[3])); + FA_X1_LVT i_5 (.A(b_imm[4]), .B(CurrentPC[4]), .CI(n_4), .CO(n_5), .S(p_0[4])); + FA_X1_LVT i_6 (.A(b_imm[5]), .B(CurrentPC[5]), .CI(n_5), .CO(n_6), .S(p_0[5])); + FA_X1_LVT i_7 (.A(b_imm[6]), .B(CurrentPC[6]), .CI(n_6), .CO(n_7), .S(p_0[6])); + FA_X1_LVT i_8 (.A(b_imm[7]), .B(CurrentPC[7]), .CI(n_7), .CO(n_8), .S(p_0[7])); + FA_X1_LVT i_9 (.A(b_imm[8]), .B(CurrentPC[8]), .CI(n_8), .CO(n_9), .S(p_0[8])); + FA_X1_LVT i_10 (.A(b_imm[9]), .B(CurrentPC[9]), .CI(n_9), .CO(n_10), .S( + p_0[9])); + FA_X1_LVT i_11 (.A(b_imm[10]), .B(CurrentPC[10]), .CI(n_10), .CO(n_11), + .S(p_0[10])); + FA_X1_LVT i_12 (.A(b_imm[11]), .B(CurrentPC[11]), .CI(n_11), .CO(n_12), + .S(p_0[11])); + FA_X1_LVT i_13 (.A(CurrentPC[12]), .B(b_imm[12]), .CI(n_12), .CO(n_13), + .S(p_0[12])); + FA_X1_LVT i_14 (.A(n_0), .B(n_1), .CI(n_13), .CO(n_14), .S(p_0[13])); + FA_X1_LVT i_15 (.A(CurrentPC[14]), .B(n_1), .CI(n_14), .CO(n_15), .S(p_0[14])); + FA_X1_LVT i_16 (.A(CurrentPC[15]), .B(n_1), .CI(n_15), .CO(n_16), .S(p_0[15])); + FA_X1_LVT i_17 (.A(CurrentPC[16]), .B(n_1), .CI(n_16), .CO(n_17), .S(p_0[16])); + FA_X1_LVT i_18 (.A(CurrentPC[17]), .B(n_1), .CI(n_17), .CO(n_18), .S(p_0[17])); + FA_X1_LVT i_19 (.A(CurrentPC[18]), .B(n_1), .CI(n_18), .CO(n_19), .S(p_0[18])); + FA_X1_LVT i_20 (.A(CurrentPC[19]), .B(n_1), .CI(n_19), .CO(n_20), .S(p_0[19])); + FA_X1_LVT i_21 (.A(CurrentPC[20]), .B(n_1), .CI(n_20), .CO(n_21), .S(p_0[20])); + FA_X1_LVT i_22 (.A(CurrentPC[21]), .B(n_1), .CI(n_21), .CO(n_22), .S(p_0[21])); + FA_X1_LVT i_23 (.A(CurrentPC[22]), .B(n_1), .CI(n_22), .CO(n_23), .S(p_0[22])); + FA_X1_LVT i_24 (.A(CurrentPC[23]), .B(n_1), .CI(n_23), .CO(n_24), .S(p_0[23])); + FA_X1_LVT i_25 (.A(CurrentPC[24]), .B(n_1), .CI(n_24), .CO(n_25), .S(p_0[24])); + FA_X1_LVT i_26 (.A(CurrentPC[25]), .B(n_1), .CI(n_25), .CO(n_26), .S(p_0[25])); + FA_X1_LVT i_27 (.A(CurrentPC[26]), .B(n_1), .CI(n_26), .CO(n_27), .S(p_0[26])); + FA_X1_LVT i_28 (.A(CurrentPC[27]), .B(n_1), .CI(n_27), .CO(n_28), .S(p_0[27])); + FA_X1_LVT i_29 (.A(CurrentPC[28]), .B(n_1), .CI(n_28), .CO(n_29), .S(p_0[28])); + FA_X1_LVT i_30 (.A(CurrentPC[29]), .B(n_1), .CI(n_29), .CO(n_30), .S(p_0[29])); + FA_X1_LVT i_31 (.A(CurrentPC[30]), .B(n_1), .CI(n_30), .CO(n_31), .S(p_0[30])); + XNOR2_X1_LVT i_33 (.A(n_32), .B(n_31), .ZN(p_0[31])); +endmodule + +module datapathS__0_26(j_imm, CurrentPC, p_0); + input [31:0]j_imm; + input [31:0]CurrentPC; + output [31:0]p_0; + + INV_X1_LVT i_1 (.A(CurrentPC[21]), .ZN(n_1)); + XNOR2_X1_LVT i_32 (.A(CurrentPC[31]), .B(n_1), .ZN(n_32)); + INV_X1_LVT i_0 (.A(j_imm[20]), .ZN(n_0)); + HA_X1_LVT i_2 (.A(j_imm[1]), .B(CurrentPC[1]), .CO(n_2), .S(p_0[1])); + FA_X1_LVT i_3 (.A(j_imm[2]), .B(CurrentPC[2]), .CI(n_2), .CO(n_3), .S(p_0[2])); + FA_X1_LVT i_4 (.A(j_imm[3]), .B(CurrentPC[3]), .CI(n_3), .CO(n_4), .S(p_0[3])); + FA_X1_LVT i_5 (.A(j_imm[4]), .B(CurrentPC[4]), .CI(n_4), .CO(n_5), .S(p_0[4])); + FA_X1_LVT i_6 (.A(j_imm[5]), .B(CurrentPC[5]), .CI(n_5), .CO(n_6), .S(p_0[5])); + FA_X1_LVT i_7 (.A(j_imm[6]), .B(CurrentPC[6]), .CI(n_6), .CO(n_7), .S(p_0[6])); + FA_X1_LVT i_8 (.A(j_imm[7]), .B(CurrentPC[7]), .CI(n_7), .CO(n_8), .S(p_0[7])); + FA_X1_LVT i_9 (.A(j_imm[8]), .B(CurrentPC[8]), .CI(n_8), .CO(n_9), .S(p_0[8])); + FA_X1_LVT i_10 (.A(j_imm[9]), .B(CurrentPC[9]), .CI(n_9), .CO(n_10), .S( + p_0[9])); + FA_X1_LVT i_11 (.A(j_imm[10]), .B(CurrentPC[10]), .CI(n_10), .CO(n_11), + .S(p_0[10])); + FA_X1_LVT i_12 (.A(j_imm[11]), .B(CurrentPC[11]), .CI(n_11), .CO(n_12), + .S(p_0[11])); + FA_X1_LVT i_13 (.A(j_imm[12]), .B(CurrentPC[12]), .CI(n_12), .CO(n_13), + .S(p_0[12])); + FA_X1_LVT i_14 (.A(j_imm[13]), .B(CurrentPC[13]), .CI(n_13), .CO(n_14), + .S(p_0[13])); + FA_X1_LVT i_15 (.A(j_imm[14]), .B(CurrentPC[14]), .CI(n_14), .CO(n_15), + .S(p_0[14])); + FA_X1_LVT i_16 (.A(j_imm[15]), .B(CurrentPC[15]), .CI(n_15), .CO(n_16), + .S(p_0[15])); + FA_X1_LVT i_17 (.A(j_imm[16]), .B(CurrentPC[16]), .CI(n_16), .CO(n_17), + .S(p_0[16])); + FA_X1_LVT i_18 (.A(j_imm[17]), .B(CurrentPC[17]), .CI(n_17), .CO(n_18), + .S(p_0[17])); + FA_X1_LVT i_19 (.A(j_imm[18]), .B(CurrentPC[18]), .CI(n_18), .CO(n_19), + .S(p_0[18])); + FA_X1_LVT i_20 (.A(j_imm[19]), .B(CurrentPC[19]), .CI(n_19), .CO(n_20), + .S(p_0[19])); + FA_X1_LVT i_21 (.A(CurrentPC[20]), .B(j_imm[20]), .CI(n_20), .CO(n_21), + .S(p_0[20])); + FA_X1_LVT i_22 (.A(n_0), .B(n_1), .CI(n_21), .CO(n_22), .S(p_0[21])); + FA_X1_LVT i_23 (.A(CurrentPC[22]), .B(n_1), .CI(n_22), .CO(n_23), .S(p_0[22])); + FA_X1_LVT i_24 (.A(CurrentPC[23]), .B(n_1), .CI(n_23), .CO(n_24), .S(p_0[23])); + FA_X1_LVT i_25 (.A(CurrentPC[24]), .B(n_1), .CI(n_24), .CO(n_25), .S(p_0[24])); + FA_X1_LVT i_26 (.A(CurrentPC[25]), .B(n_1), .CI(n_25), .CO(n_26), .S(p_0[25])); + FA_X1_LVT i_27 (.A(CurrentPC[26]), .B(n_1), .CI(n_26), .CO(n_27), .S(p_0[26])); + FA_X1_LVT i_28 (.A(CurrentPC[27]), .B(n_1), .CI(n_27), .CO(n_28), .S(p_0[27])); + FA_X1_LVT i_29 (.A(CurrentPC[28]), .B(n_1), .CI(n_28), .CO(n_29), .S(p_0[28])); + FA_X1_LVT i_30 (.A(CurrentPC[29]), .B(n_1), .CI(n_29), .CO(n_30), .S(p_0[29])); + FA_X1_LVT i_31 (.A(CurrentPC[30]), .B(n_1), .CI(n_30), .CO(n_31), .S(p_0[30])); + XNOR2_X1_LVT i_33 (.A(n_32), .B(n_31), .ZN(p_0[31])); +endmodule + +module datapathS__0_14(i_imm, RRs1, p_0); + input [31:0]i_imm; + input [31:0]RRs1; + output [31:0]p_0; + + INV_X1_LVT i_1 (.A(RRs1[12]), .ZN(n_1)); + XNOR2_X1_LVT i_33 (.A(RRs1[31]), .B(n_1), .ZN(n_33)); + INV_X1_LVT i_0 (.A(i_imm[11]), .ZN(n_0)); + HA_X1_LVT i_2 (.A(i_imm[0]), .B(RRs1[0]), .CO(n_2), .S(p_0[0])); + FA_X1_LVT i_3 (.A(i_imm[1]), .B(RRs1[1]), .CI(n_2), .CO(n_3), .S(p_0[1])); + FA_X1_LVT i_4 (.A(i_imm[2]), .B(RRs1[2]), .CI(n_3), .CO(n_4), .S(p_0[2])); + FA_X1_LVT i_5 (.A(i_imm[3]), .B(RRs1[3]), .CI(n_4), .CO(n_5), .S(p_0[3])); + FA_X1_LVT i_6 (.A(i_imm[4]), .B(RRs1[4]), .CI(n_5), .CO(n_6), .S(p_0[4])); + FA_X1_LVT i_7 (.A(i_imm[5]), .B(RRs1[5]), .CI(n_6), .CO(n_7), .S(p_0[5])); + FA_X1_LVT i_8 (.A(i_imm[6]), .B(RRs1[6]), .CI(n_7), .CO(n_8), .S(p_0[6])); + FA_X1_LVT i_9 (.A(i_imm[7]), .B(RRs1[7]), .CI(n_8), .CO(n_9), .S(p_0[7])); + FA_X1_LVT i_10 (.A(i_imm[8]), .B(RRs1[8]), .CI(n_9), .CO(n_10), .S(p_0[8])); + FA_X1_LVT i_11 (.A(i_imm[9]), .B(RRs1[9]), .CI(n_10), .CO(n_11), .S(p_0[9])); + FA_X1_LVT i_12 (.A(i_imm[10]), .B(RRs1[10]), .CI(n_11), .CO(n_12), .S(p_0[10])); + FA_X1_LVT i_13 (.A(RRs1[11]), .B(i_imm[11]), .CI(n_12), .CO(n_13), .S(p_0[11])); + FA_X1_LVT i_14 (.A(n_0), .B(n_1), .CI(n_13), .CO(n_14), .S(p_0[12])); + FA_X1_LVT i_15 (.A(RRs1[13]), .B(n_1), .CI(n_14), .CO(n_15), .S(p_0[13])); + FA_X1_LVT i_16 (.A(RRs1[14]), .B(n_1), .CI(n_15), .CO(n_16), .S(p_0[14])); + FA_X1_LVT i_17 (.A(RRs1[15]), .B(n_1), .CI(n_16), .CO(n_17), .S(p_0[15])); + FA_X1_LVT i_18 (.A(RRs1[16]), .B(n_1), .CI(n_17), .CO(n_18), .S(p_0[16])); + FA_X1_LVT i_19 (.A(RRs1[17]), .B(n_1), .CI(n_18), .CO(n_19), .S(p_0[17])); + FA_X1_LVT i_20 (.A(RRs1[18]), .B(n_1), .CI(n_19), .CO(n_20), .S(p_0[18])); + FA_X1_LVT i_21 (.A(RRs1[19]), .B(n_1), .CI(n_20), .CO(n_21), .S(p_0[19])); + FA_X1_LVT i_22 (.A(RRs1[20]), .B(n_1), .CI(n_21), .CO(n_22), .S(p_0[20])); + FA_X1_LVT i_23 (.A(RRs1[21]), .B(n_1), .CI(n_22), .CO(n_23), .S(p_0[21])); + FA_X1_LVT i_24 (.A(RRs1[22]), .B(n_1), .CI(n_23), .CO(n_24), .S(p_0[22])); + FA_X1_LVT i_25 (.A(RRs1[23]), .B(n_1), .CI(n_24), .CO(n_25), .S(p_0[23])); + FA_X1_LVT i_26 (.A(RRs1[24]), .B(n_1), .CI(n_25), .CO(n_26), .S(p_0[24])); + FA_X1_LVT i_27 (.A(RRs1[25]), .B(n_1), .CI(n_26), .CO(n_27), .S(p_0[25])); + FA_X1_LVT i_28 (.A(RRs1[26]), .B(n_1), .CI(n_27), .CO(n_28), .S(p_0[26])); + FA_X1_LVT i_29 (.A(RRs1[27]), .B(n_1), .CI(n_28), .CO(n_29), .S(p_0[27])); + FA_X1_LVT i_30 (.A(RRs1[28]), .B(n_1), .CI(n_29), .CO(n_30), .S(p_0[28])); + FA_X1_LVT i_31 (.A(RRs1[29]), .B(n_1), .CI(n_30), .CO(n_31), .S(p_0[29])); + FA_X1_LVT i_32 (.A(RRs1[30]), .B(n_1), .CI(n_31), .CO(n_32), .S(p_0[30])); + XNOR2_X1_LVT i_34 (.A(n_33), .B(n_32), .ZN(p_0[31])); +endmodule + +module datapathS(op2, op1, p_0); + input [31:0]op2; + input [31:0]op1; + output [31:0]p_0; + + XNOR2_X1_LVT i_31 (.A(op2[31]), .B(op1[31]), .ZN(n_31)); + HA_X1_LVT i_0 (.A(op2[0]), .B(op1[0]), .CO(n_0), .S(p_0[0])); + FA_X1_LVT i_1 (.A(op2[1]), .B(op1[1]), .CI(n_0), .CO(n_1), .S(p_0[1])); + FA_X1_LVT i_2 (.A(op2[2]), .B(op1[2]), .CI(n_1), .CO(n_2), .S(p_0[2])); + FA_X1_LVT i_3 (.A(op2[3]), .B(op1[3]), .CI(n_2), .CO(n_3), .S(p_0[3])); + FA_X1_LVT i_4 (.A(op2[4]), .B(op1[4]), .CI(n_3), .CO(n_4), .S(p_0[4])); + FA_X1_LVT i_5 (.A(op2[5]), .B(op1[5]), .CI(n_4), .CO(n_5), .S(p_0[5])); + FA_X1_LVT i_6 (.A(op2[6]), .B(op1[6]), .CI(n_5), .CO(n_6), .S(p_0[6])); + FA_X1_LVT i_7 (.A(op2[7]), .B(op1[7]), .CI(n_6), .CO(n_7), .S(p_0[7])); + FA_X1_LVT i_8 (.A(op2[8]), .B(op1[8]), .CI(n_7), .CO(n_8), .S(p_0[8])); + FA_X1_LVT i_9 (.A(op2[9]), .B(op1[9]), .CI(n_8), .CO(n_9), .S(p_0[9])); + FA_X1_LVT i_10 (.A(op2[10]), .B(op1[10]), .CI(n_9), .CO(n_10), .S(p_0[10])); + FA_X1_LVT i_11 (.A(op2[11]), .B(op1[11]), .CI(n_10), .CO(n_11), .S(p_0[11])); + FA_X1_LVT i_12 (.A(op2[12]), .B(op1[12]), .CI(n_11), .CO(n_12), .S(p_0[12])); + FA_X1_LVT i_13 (.A(op2[13]), .B(op1[13]), .CI(n_12), .CO(n_13), .S(p_0[13])); + FA_X1_LVT i_14 (.A(op2[14]), .B(op1[14]), .CI(n_13), .CO(n_14), .S(p_0[14])); + FA_X1_LVT i_15 (.A(op2[15]), .B(op1[15]), .CI(n_14), .CO(n_15), .S(p_0[15])); + FA_X1_LVT i_16 (.A(op2[16]), .B(op1[16]), .CI(n_15), .CO(n_16), .S(p_0[16])); + FA_X1_LVT i_17 (.A(op2[17]), .B(op1[17]), .CI(n_16), .CO(n_17), .S(p_0[17])); + FA_X1_LVT i_18 (.A(op2[18]), .B(op1[18]), .CI(n_17), .CO(n_18), .S(p_0[18])); + FA_X1_LVT i_19 (.A(op2[19]), .B(op1[19]), .CI(n_18), .CO(n_19), .S(p_0[19])); + FA_X1_LVT i_20 (.A(op2[20]), .B(op1[20]), .CI(n_19), .CO(n_20), .S(p_0[20])); + FA_X1_LVT i_21 (.A(op2[21]), .B(op1[21]), .CI(n_20), .CO(n_21), .S(p_0[21])); + FA_X1_LVT i_22 (.A(op2[22]), .B(op1[22]), .CI(n_21), .CO(n_22), .S(p_0[22])); + FA_X1_LVT i_23 (.A(op2[23]), .B(op1[23]), .CI(n_22), .CO(n_23), .S(p_0[23])); + FA_X1_LVT i_24 (.A(op2[24]), .B(op1[24]), .CI(n_23), .CO(n_24), .S(p_0[24])); + FA_X1_LVT i_25 (.A(op2[25]), .B(op1[25]), .CI(n_24), .CO(n_25), .S(p_0[25])); + FA_X1_LVT i_26 (.A(op2[26]), .B(op1[26]), .CI(n_25), .CO(n_26), .S(p_0[26])); + FA_X1_LVT i_27 (.A(op2[27]), .B(op1[27]), .CI(n_26), .CO(n_27), .S(p_0[27])); + FA_X1_LVT i_28 (.A(op2[28]), .B(op1[28]), .CI(n_27), .CO(n_28), .S(p_0[28])); + FA_X1_LVT i_29 (.A(op2[29]), .B(op1[29]), .CI(n_28), .CO(n_29), .S(p_0[29])); + FA_X1_LVT i_30 (.A(op2[30]), .B(op1[30]), .CI(n_29), .CO(n_30), .S(p_0[30])); + XNOR2_X1_LVT i_32 (.A(n_31), .B(n_30), .ZN(p_0[31])); +endmodule + +module datapathS__0_6(op1, p_0, op2); + input [31:0]op1; + output [31:0]p_0; + input [31:0]op2; + + INV_X1_LVT i_147 (.A(op2[30]), .ZN(n_117)); + NAND2_X1_LVT i_149 (.A1(n_117), .A2(op1[30]), .ZN(n_119)); + INV_X1_LVT i_152 (.A(n_119), .ZN(n_121)); + INV_X1_LVT i_130 (.A(op1[26]), .ZN(n_104)); + NAND2_X1_LVT i_131 (.A1(n_104), .A2(op2[26]), .ZN(n_105)); + INV_X1_LVT i_123 (.A(op2[25]), .ZN(n_98)); + NAND2_X1_LVT i_125 (.A1(n_98), .A2(op1[25]), .ZN(n_100)); + INV_X1_LVT i_112 (.A(op2[23]), .ZN(n_89)); + NAND2_X1_LVT i_114 (.A1(n_89), .A2(op1[23]), .ZN(n_91)); + INV_X1_LVT i_101 (.A(op2[21]), .ZN(n_80)); + NAND2_X1_LVT i_103 (.A1(n_80), .A2(op1[21]), .ZN(n_82)); + INV_X1_LVT i_48 (.A(op1[8]), .ZN(n_40)); + NAND2_X1_LVT i_49 (.A1(n_40), .A2(op2[8]), .ZN(n_41)); + INV_X1_LVT i_41 (.A(op2[7]), .ZN(n_34)); + NAND2_X1_LVT i_43 (.A1(n_34), .A2(op1[7]), .ZN(n_36)); + INV_X1_LVT i_32 (.A(op2[5]), .ZN(n_27)); + NOR2_X1_LVT i_33 (.A1(n_27), .A2(op1[5]), .ZN(n_28)); + INV_X1_LVT i_24 (.A(op1[4]), .ZN(n_20)); + NOR2_X1_LVT i_27 (.A1(n_20), .A2(op2[4]), .ZN(n_23)); + INV_X1_LVT i_17 (.A(op2[3]), .ZN(n_14)); + NAND2_X1_LVT i_19 (.A1(n_14), .A2(op1[3]), .ZN(n_16)); + INV_X1_LVT i_22 (.A(n_16), .ZN(n_18)); + INV_X1_LVT i_10 (.A(op2[2]), .ZN(n_8)); + NAND2_X1_LVT i_12 (.A1(n_8), .A2(op1[2]), .ZN(n_10)); + INV_X1_LVT i_3 (.A(op1[1]), .ZN(n_2)); + NAND2_X1_LVT i_5 (.A1(n_2), .A2(op2[1]), .ZN(n_4)); + INV_X1_LVT i_0 (.A(op1[0]), .ZN(n_0)); + NAND2_X1_LVT i_1 (.A1(n_0), .A2(op2[0]), .ZN(n_1)); + OR2_X1_LVT i_4 (.A1(n_2), .A2(op2[1]), .ZN(n_3)); + INV_X1_LVT i_8 (.A(n_3), .ZN(n_6)); + OAI21_X1_LVT i_9 (.A(n_4), .B1(n_1), .B2(n_6), .ZN(n_7)); + NOR2_X1_LVT i_11 (.A1(n_8), .A2(op1[2]), .ZN(n_9)); + OAI21_X1_LVT i_16 (.A(n_10), .B1(n_7), .B2(n_9), .ZN(n_13)); + OR2_X1_LVT i_18 (.A1(n_14), .A2(op1[3]), .ZN(n_15)); + AOI21_X1_LVT i_23 (.A(n_18), .B1(n_13), .B2(n_15), .ZN(n_19)); + INV_X1_LVT i_30 (.A(n_19), .ZN(n_25)); + NAND2_X1_LVT i_25 (.A1(n_20), .A2(op2[4]), .ZN(n_21)); + AOI21_X1_LVT i_31 (.A(n_23), .B1(n_25), .B2(n_21), .ZN(n_26)); + AOI21_X1_LVT i_34 (.A(n_28), .B1(n_27), .B2(op1[5]), .ZN(n_29)); + AOI21_X1_LVT i_36 (.A(n_28), .B1(n_26), .B2(n_29), .ZN(n_30)); + XOR2_X1_LVT i_37 (.A(op2[6]), .B(op1[6]), .Z(n_31)); + INV_X1_LVT i_39 (.A(op2[6]), .ZN(n_32)); + OAI22_X1_LVT i_40 (.A1(n_30), .A2(n_31), .B1(n_32), .B2(op1[6]), .ZN(n_33)); + NOR2_X1_LVT i_42 (.A1(n_34), .A2(op1[7]), .ZN(n_35)); + OAI21_X1_LVT i_47 (.A(n_36), .B1(n_33), .B2(n_35), .ZN(n_39)); + OAI21_X1_LVT i_50 (.A(n_41), .B1(n_40), .B2(op2[8]), .ZN(n_42)); + OAI21_X1_LVT i_52 (.A(n_41), .B1(n_39), .B2(n_42), .ZN(n_43)); + XNOR2_X1_LVT i_53 (.A(op2[9]), .B(op1[9]), .ZN(n_44)); + INV_X1_LVT i_55 (.A(op1[9]), .ZN(n_45)); + AOI22_X1_LVT i_56 (.A1(n_43), .A2(n_44), .B1(n_45), .B2(op2[9]), .ZN(n_46)); + XOR2_X1_LVT i_57 (.A(op2[10]), .B(op1[10]), .Z(n_47)); + INV_X1_LVT i_59 (.A(op2[10]), .ZN(n_48)); + OAI22_X1_LVT i_60 (.A1(n_46), .A2(n_47), .B1(n_48), .B2(op1[10]), .ZN(n_49)); + XNOR2_X1_LVT i_61 (.A(op2[11]), .B(op1[11]), .ZN(n_50)); + INV_X1_LVT i_63 (.A(op1[11]), .ZN(n_51)); + AOI22_X1_LVT i_64 (.A1(n_49), .A2(n_50), .B1(n_51), .B2(op2[11]), .ZN(n_52)); + XOR2_X1_LVT i_65 (.A(op2[12]), .B(op1[12]), .Z(n_53)); + INV_X1_LVT i_67 (.A(op2[12]), .ZN(n_54)); + OAI22_X1_LVT i_68 (.A1(n_52), .A2(n_53), .B1(n_54), .B2(op1[12]), .ZN(n_55)); + XNOR2_X1_LVT i_69 (.A(op2[13]), .B(op1[13]), .ZN(n_56)); + INV_X1_LVT i_71 (.A(op1[13]), .ZN(n_57)); + AOI22_X1_LVT i_72 (.A1(n_55), .A2(n_56), .B1(n_57), .B2(op2[13]), .ZN(n_58)); + XOR2_X1_LVT i_73 (.A(op2[14]), .B(op1[14]), .Z(n_59)); + INV_X1_LVT i_75 (.A(op2[14]), .ZN(n_60)); + OAI22_X1_LVT i_76 (.A1(n_58), .A2(n_59), .B1(n_60), .B2(op1[14]), .ZN(n_61)); + XNOR2_X1_LVT i_77 (.A(op2[15]), .B(op1[15]), .ZN(n_62)); + INV_X1_LVT i_79 (.A(op1[15]), .ZN(n_63)); + AOI22_X1_LVT i_80 (.A1(n_61), .A2(n_62), .B1(n_63), .B2(op2[15]), .ZN(n_64)); + XOR2_X1_LVT i_81 (.A(op2[16]), .B(op1[16]), .Z(n_65)); + INV_X1_LVT i_83 (.A(op2[16]), .ZN(n_66)); + OAI22_X1_LVT i_84 (.A1(n_64), .A2(n_65), .B1(n_66), .B2(op1[16]), .ZN(n_67)); + XNOR2_X1_LVT i_85 (.A(op2[17]), .B(op1[17]), .ZN(n_68)); + INV_X1_LVT i_87 (.A(op1[17]), .ZN(n_69)); + AOI22_X1_LVT i_88 (.A1(n_67), .A2(n_68), .B1(n_69), .B2(op2[17]), .ZN(n_70)); + XOR2_X1_LVT i_89 (.A(op2[18]), .B(op1[18]), .Z(n_71)); + INV_X1_LVT i_91 (.A(op2[18]), .ZN(n_72)); + OAI22_X1_LVT i_92 (.A1(n_70), .A2(n_71), .B1(n_72), .B2(op1[18]), .ZN(n_73)); + XNOR2_X1_LVT i_93 (.A(op2[19]), .B(op1[19]), .ZN(n_74)); + INV_X1_LVT i_95 (.A(op1[19]), .ZN(n_75)); + AOI22_X1_LVT i_96 (.A1(n_73), .A2(n_74), .B1(n_75), .B2(op2[19]), .ZN(n_76)); + XOR2_X1_LVT i_97 (.A(op2[20]), .B(op1[20]), .Z(n_77)); + INV_X1_LVT i_99 (.A(op2[20]), .ZN(n_78)); + OAI22_X1_LVT i_100 (.A1(n_76), .A2(n_77), .B1(n_78), .B2(op1[20]), .ZN(n_79)); + NOR2_X1_LVT i_102 (.A1(n_80), .A2(op1[21]), .ZN(n_81)); + OAI21_X1_LVT i_107 (.A(n_82), .B1(n_79), .B2(n_81), .ZN(n_85)); + XOR2_X1_LVT i_108 (.A(op2[22]), .B(op1[22]), .Z(n_86)); + INV_X1_LVT i_110 (.A(op2[22]), .ZN(n_87)); + OAI22_X1_LVT i_111 (.A1(n_85), .A2(n_86), .B1(n_87), .B2(op1[22]), .ZN(n_88)); + NOR2_X1_LVT i_113 (.A1(n_89), .A2(op1[23]), .ZN(n_90)); + OAI21_X1_LVT i_118 (.A(n_91), .B1(n_88), .B2(n_90), .ZN(n_94)); + XOR2_X1_LVT i_119 (.A(op2[24]), .B(op1[24]), .Z(n_95)); + INV_X1_LVT i_121 (.A(op2[24]), .ZN(n_96)); + OAI22_X1_LVT i_122 (.A1(n_94), .A2(n_95), .B1(n_96), .B2(op1[24]), .ZN(n_97)); + NOR2_X1_LVT i_124 (.A1(n_98), .A2(op1[25]), .ZN(n_99)); + OAI21_X1_LVT i_129 (.A(n_100), .B1(n_97), .B2(n_99), .ZN(n_103)); + OAI21_X1_LVT i_132 (.A(n_105), .B1(n_104), .B2(op2[26]), .ZN(n_106)); + OAI21_X1_LVT i_134 (.A(n_105), .B1(n_103), .B2(n_106), .ZN(n_107)); + XNOR2_X1_LVT i_135 (.A(op2[27]), .B(op1[27]), .ZN(n_108)); + INV_X1_LVT i_137 (.A(op1[27]), .ZN(n_109)); + AOI22_X1_LVT i_138 (.A1(n_107), .A2(n_108), .B1(n_109), .B2(op2[27]), + .ZN(n_110)); + XOR2_X1_LVT i_139 (.A(op2[28]), .B(op1[28]), .Z(n_111)); + INV_X1_LVT i_141 (.A(op2[28]), .ZN(n_112)); + OAI22_X1_LVT i_142 (.A1(n_110), .A2(n_111), .B1(n_112), .B2(op1[28]), + .ZN(n_113)); + XNOR2_X1_LVT i_143 (.A(op2[29]), .B(op1[29]), .ZN(n_114)); + INV_X1_LVT i_145 (.A(op1[29]), .ZN(n_115)); + AOI22_X1_LVT i_146 (.A1(n_113), .A2(n_114), .B1(n_115), .B2(op2[29]), + .ZN(n_116)); + OR2_X1_LVT i_148 (.A1(n_117), .A2(op1[30]), .ZN(n_118)); + AOI21_X1_LVT i_153 (.A(n_121), .B1(n_116), .B2(n_118), .ZN(n_122)); + XNOR2_X1_LVT i_154 (.A(op1[31]), .B(op2[31]), .ZN(n_123)); + XNOR2_X1_LVT i_155 (.A(n_122), .B(n_123), .ZN(p_0[31])); + NAND2_X1_LVT i_150 (.A1(n_118), .A2(n_119), .ZN(n_120)); + XNOR2_X1_LVT i_151 (.A(n_116), .B(n_120), .ZN(p_0[30])); + XNOR2_X1_LVT i_144 (.A(n_113), .B(n_114), .ZN(p_0[29])); + XNOR2_X1_LVT i_140 (.A(n_110), .B(n_111), .ZN(p_0[28])); + XNOR2_X1_LVT i_136 (.A(n_107), .B(n_108), .ZN(p_0[27])); + XNOR2_X1_LVT i_133 (.A(n_103), .B(n_106), .ZN(p_0[26])); + INV_X1_LVT i_126 (.A(n_100), .ZN(n_101)); + NOR2_X1_LVT i_127 (.A1(n_99), .A2(n_101), .ZN(n_102)); + XNOR2_X1_LVT i_128 (.A(n_97), .B(n_102), .ZN(p_0[25])); + XNOR2_X1_LVT i_120 (.A(n_94), .B(n_95), .ZN(p_0[24])); + INV_X1_LVT i_115 (.A(n_91), .ZN(n_92)); + NOR2_X1_LVT i_116 (.A1(n_90), .A2(n_92), .ZN(n_93)); + XNOR2_X1_LVT i_117 (.A(n_88), .B(n_93), .ZN(p_0[23])); + XNOR2_X1_LVT i_109 (.A(n_85), .B(n_86), .ZN(p_0[22])); + INV_X1_LVT i_104 (.A(n_82), .ZN(n_83)); + NOR2_X1_LVT i_105 (.A1(n_81), .A2(n_83), .ZN(n_84)); + XNOR2_X1_LVT i_106 (.A(n_79), .B(n_84), .ZN(p_0[21])); + XNOR2_X1_LVT i_98 (.A(n_76), .B(n_77), .ZN(p_0[20])); + XNOR2_X1_LVT i_94 (.A(n_73), .B(n_74), .ZN(p_0[19])); + XNOR2_X1_LVT i_90 (.A(n_70), .B(n_71), .ZN(p_0[18])); + XNOR2_X1_LVT i_86 (.A(n_67), .B(n_68), .ZN(p_0[17])); + XNOR2_X1_LVT i_82 (.A(n_64), .B(n_65), .ZN(p_0[16])); + XNOR2_X1_LVT i_78 (.A(n_61), .B(n_62), .ZN(p_0[15])); + XNOR2_X1_LVT i_74 (.A(n_58), .B(n_59), .ZN(p_0[14])); + XNOR2_X1_LVT i_70 (.A(n_55), .B(n_56), .ZN(p_0[13])); + XNOR2_X1_LVT i_66 (.A(n_52), .B(n_53), .ZN(p_0[12])); + XNOR2_X1_LVT i_62 (.A(n_49), .B(n_50), .ZN(p_0[11])); + XNOR2_X1_LVT i_58 (.A(n_46), .B(n_47), .ZN(p_0[10])); + XNOR2_X1_LVT i_54 (.A(n_43), .B(n_44), .ZN(p_0[9])); + XNOR2_X1_LVT i_51 (.A(n_39), .B(n_42), .ZN(p_0[8])); + INV_X1_LVT i_44 (.A(n_36), .ZN(n_37)); + NOR2_X1_LVT i_45 (.A1(n_35), .A2(n_37), .ZN(n_38)); + XNOR2_X1_LVT i_46 (.A(n_33), .B(n_38), .ZN(p_0[7])); + XNOR2_X1_LVT i_38 (.A(n_30), .B(n_31), .ZN(p_0[6])); + XNOR2_X1_LVT i_35 (.A(n_26), .B(n_29), .ZN(p_0[5])); + INV_X1_LVT i_26 (.A(n_21), .ZN(n_22)); + NOR2_X1_LVT i_28 (.A1(n_22), .A2(n_23), .ZN(n_24)); + XNOR2_X1_LVT i_29 (.A(n_19), .B(n_24), .ZN(p_0[4])); + NAND2_X1_LVT i_20 (.A1(n_15), .A2(n_16), .ZN(n_17)); + XNOR2_X1_LVT i_21 (.A(n_13), .B(n_17), .ZN(p_0[3])); + INV_X1_LVT i_13 (.A(n_10), .ZN(n_11)); + NOR2_X1_LVT i_14 (.A1(n_9), .A2(n_11), .ZN(n_12)); + XNOR2_X1_LVT i_15 (.A(n_7), .B(n_12), .ZN(p_0[2])); + NAND2_X1_LVT i_6 (.A1(n_3), .A2(n_4), .ZN(n_5)); + XNOR2_X1_LVT i_7 (.A(n_5), .B(n_1), .ZN(p_0[1])); + OAI21_X1_LVT i_2 (.A(n_1), .B1(n_0), .B2(op2[0]), .ZN(p_0[0])); +endmodule + +module alu(aluOp, aluNegAr, aluBypass, op1, op2, result, eqFlag); + input [2:0]aluOp; + input aluNegAr; + input aluBypass; + input [31:0]op1; + input [31:0]op2; + output [31:0]result; + output eqFlag; + + wire n_0_0; + wire n_0_1; + wire n_0_2; + wire n_0_3; + wire n_0_4; + wire n_0_5; + wire n_0_6; + wire n_0_7; + wire n_0_8; + wire n_0_9; + wire n_0_10; + wire n_0_11; + wire n_0_12; + wire n_0_13; + wire n_0_14; + wire n_0_15; + wire n_0_16; + wire n_0_17; + wire n_0_18; + wire n_0_19; + wire n_0_20; + wire n_0_21; + wire n_0_22; + wire n_0_23; + wire n_0_24; + wire n_0_25; + wire n_0_26; + wire n_0_27; + wire n_0_28; + wire n_0_29; + wire n_0_30; + wire n_0_31; + wire n_0_32; + wire n_0_33; + wire n_0_34; + wire n_0_35; + wire n_0_36; + wire n_0_37; + wire n_0_38; + wire n_0_39; + wire n_0_40; + wire n_0_41; + wire n_0_42; + wire n_0_43; + wire n_0_44; + wire n_0_45; + wire n_0_46; + wire n_0_47; + wire n_0_48; + wire n_0_49; + wire n_0_50; + wire n_0_51; + wire n_0_52; + wire n_0_53; + wire n_0_54; + wire n_0_55; + wire n_0_56; + wire n_0_57; + wire n_0_58; + wire n_0_59; + wire n_0_60; + wire n_0_61; + wire n_0_62; + wire n_0_63; + wire n_0_64; + wire n_0_65; + wire n_0_66; + wire n_0_67; + wire n_0_68; + wire n_0_69; + wire n_0_70; + wire n_0_71; + wire n_0_72; + wire n_0_73; + wire n_0_74; + wire n_0_75; + wire n_0_76; + wire n_0_77; + wire n_0_78; + wire n_0_79; + wire n_0_80; + wire n_0_81; + wire n_0_82; + wire n_0_83; + wire n_0_84; + wire n_0_85; + wire n_0_86; + wire n_0_87; + wire n_0_88; + wire n_0_89; + wire n_0_90; + wire n_0_91; + wire n_0_92; + wire n_0_93; + wire n_0_94; + wire n_0_95; + wire n_0_96; + wire n_0_97; + wire n_0_98; + wire n_0_99; + wire n_0_100; + wire n_0_101; + wire n_0_102; + wire n_0_103; + wire n_0_104; + wire n_0_105; + wire n_0_106; + wire n_0_107; + wire n_0_108; + wire n_0_109; + wire n_0_110; + wire n_0_111; + wire n_0_112; + wire n_0_113; + wire n_0_114; + wire n_0_115; + wire n_0_116; + wire n_0_117; + wire n_0_118; + wire n_0_119; + wire n_0_120; + wire n_0_121; + wire n_0_122; + wire n_0_123; + wire n_0_124; + wire n_0_125; + wire n_0_126; + wire n_0_127; + wire n_0_128; + wire n_0_129; + wire n_0_130; + wire n_0_131; + wire n_0_132; + wire n_0_133; + wire n_0_134; + wire n_0_135; + wire n_0_136; + wire n_0_137; + wire n_0_138; + wire n_0_139; + wire n_0_140; + wire n_0_141; + wire n_0_142; + wire n_0_143; + wire n_0_144; + wire n_0_145; + wire n_0_146; + wire n_0_147; + wire n_0_148; + wire n_0_149; + wire n_0_150; + wire n_0_151; + wire n_0_152; + wire n_0_153; + wire n_0_154; + wire n_0_155; + wire n_0_156; + wire n_0_157; + wire n_0_158; + wire n_0_159; + wire n_0_160; + wire n_0_161; + wire n_0_162; + wire n_0_163; + wire n_0_164; + wire n_0_165; + wire n_0_166; + wire n_0_167; + wire n_0_168; + wire n_0_169; + wire n_0_170; + wire n_0_171; + wire n_0_172; + wire n_0_173; + wire n_0_174; + wire n_0_175; + wire n_0_176; + wire n_0_177; + wire n_0_178; + wire n_0_179; + wire n_0_180; + wire n_0_181; + wire n_0_182; + wire n_0_183; + wire n_0_184; + wire n_0_185; + wire n_0_186; + wire n_0_187; + wire n_0_188; + wire n_0_189; + wire n_0_190; + wire n_0_191; + wire n_0_192; + wire n_0_193; + wire n_0_194; + wire n_0_195; + wire n_0_196; + wire n_0_197; + wire n_0_198; + wire n_0_199; + wire n_0_200; + wire n_0_201; + wire n_0_202; + wire n_0_203; + wire n_0_204; + wire n_0_205; + wire n_0_206; + wire n_0_207; + wire n_0_208; + wire n_0_209; + wire n_0_210; + wire n_0_211; + wire n_0_212; + wire n_0_213; + wire n_0_214; + wire n_0_215; + wire n_0_216; + wire n_0_217; + wire n_0_218; + wire n_0_219; + wire n_0_220; + wire n_0_221; + wire n_0_222; + wire n_0_223; + wire n_0_224; + wire n_0_225; + wire n_0_226; + wire n_0_227; + wire n_0_228; + wire n_0_229; + wire n_0_230; + wire n_0_231; + wire n_0_232; + wire n_0_233; + wire n_0_234; + wire n_0_235; + wire n_0_236; + wire n_0_237; + wire n_0_238; + wire n_0_239; + wire n_0_240; + wire n_0_241; + wire n_0_242; + wire n_0_243; + wire n_0_244; + wire n_0_245; + wire n_0_246; + wire n_0_247; + wire n_0_248; + wire n_0_249; + wire n_0_250; + wire n_0_251; + wire n_0_252; + wire n_0_253; + wire n_0_254; + wire n_0_255; + wire n_0_256; + wire n_0_257; + wire n_0_258; + wire n_0_259; + wire n_0_260; + wire n_0_261; + wire n_0_262; + wire n_0_263; + wire n_0_264; + wire n_0_265; + wire n_0_266; + wire n_0_267; + wire n_0_268; + wire n_0_269; + wire n_0_270; + wire n_0_271; + wire n_0_272; + wire n_0_273; + wire n_0_274; + wire n_0_275; + wire n_0_276; + wire n_0_277; + wire n_0_278; + wire n_0_279; + wire n_0_280; + wire n_0_281; + wire n_0_282; + wire n_0_283; + wire n_0_284; + wire n_0_285; + wire n_0_286; + wire n_0_287; + wire n_0_288; + wire n_0_289; + wire n_0_290; + wire n_0_291; + wire n_0_292; + wire n_0_293; + wire n_0_294; + wire n_0_295; + wire n_0_296; + wire n_0_297; + wire n_0_298; + wire n_0_299; + wire n_0_300; + wire n_0_301; + wire n_0_302; + wire n_0_303; + wire n_0_304; + wire n_0_305; + wire n_0_306; + wire n_0_307; + wire n_0_308; + wire n_0_309; + wire n_0_310; + wire n_0_311; + wire n_0_312; + wire n_0_313; + wire n_0_314; + wire n_0_315; + wire n_0_316; + wire n_0_317; + wire n_0_318; + wire n_0_319; + wire n_0_320; + wire n_0_321; + wire n_0_322; + wire n_0_323; + wire n_0_324; + wire n_0_325; + wire n_0_326; + wire n_0_327; + wire n_0_328; + wire n_0_329; + wire n_0_330; + wire n_0_331; + wire n_0_332; + wire n_0_333; + wire n_0_334; + wire n_0_335; + wire n_0_336; + wire n_0_337; + wire n_0_338; + wire n_0_339; + wire n_0_340; + wire n_0_341; + wire n_0_342; + wire n_0_343; + wire n_0_344; + wire n_0_345; + wire n_0_346; + wire n_0_347; + wire n_0_348; + wire n_0_349; + wire n_0_350; + wire n_0_351; + wire n_0_352; + wire n_0_353; + wire n_0_354; + wire n_0_355; + wire n_0_356; + wire n_0_357; + wire n_0_358; + wire n_0_359; + wire n_0_360; + wire n_0_361; + wire n_0_362; + wire n_0_363; + wire n_0_364; + wire n_0_365; + wire n_0_366; + wire n_0_367; + wire n_0_368; + wire n_0_369; + wire n_0_370; + wire n_0_371; + wire n_0_372; + wire n_0_373; + wire n_0_374; + wire n_0_375; + wire n_0_376; + wire n_0_377; + wire n_0_378; + wire n_0_379; + wire n_0_380; + wire n_0_381; + wire n_0_382; + wire n_0_383; + wire n_0_384; + wire n_0_385; + wire n_0_386; + wire n_0_387; + wire n_0_388; + wire n_0_389; + wire n_0_390; + wire n_0_391; + wire n_0_392; + wire n_0_393; + wire n_0_394; + wire n_0_395; + wire n_0_396; + wire n_0_397; + wire n_0_398; + wire n_0_399; + wire n_0_400; + wire n_0_401; + wire n_0_402; + wire n_0_403; + wire n_0_404; + wire n_0_405; + wire n_0_406; + wire n_0_407; + wire n_0_408; + wire n_0_409; + wire n_0_410; + wire n_0_411; + wire n_0_412; + wire n_0_413; + wire n_0_414; + wire n_0_415; + wire n_0_416; + wire n_0_417; + wire n_0_418; + wire n_0_419; + wire n_0_420; + wire n_0_421; + wire n_0_422; + wire n_0_423; + wire n_0_424; + wire n_0_425; + wire n_0_426; + wire n_0_427; + wire n_0_428; + wire n_0_429; + wire n_0_430; + wire n_0_431; + wire n_0_432; + wire n_0_433; + wire n_0_434; + wire n_0_435; + wire n_0_436; + wire n_0_437; + wire n_0_438; + wire n_0_439; + wire n_0_440; + wire n_0_441; + wire n_0_442; + wire n_0_443; + wire n_0_444; + wire n_0_445; + wire n_0_446; + wire n_0_447; + wire n_0_448; + wire n_0_449; + wire n_0_450; + wire n_0_451; + wire n_0_452; + wire n_0_453; + wire n_0_454; + wire n_0_455; + wire n_0_456; + wire n_0_457; + wire n_0_458; + wire n_0_459; + wire n_0_460; + wire n_0_461; + wire n_0_462; + wire n_0_463; + wire n_0_464; + wire n_0_465; + wire n_0_466; + wire n_0_467; + wire n_0_468; + wire n_0_469; + wire n_0_470; + wire n_0_471; + wire n_0_472; + wire n_0_473; + wire n_0_474; + wire n_0_475; + wire n_0_476; + wire n_0_477; + wire n_0_478; + wire n_0_479; + wire n_0_480; + wire n_0_481; + wire n_0_482; + wire n_0_483; + wire n_0_484; + wire n_0_485; + wire n_0_486; + wire n_0_487; + wire n_0_488; + wire n_0_489; + wire n_0_490; + wire n_0_491; + wire n_0_492; + wire n_0_493; + wire n_0_494; + wire n_0_495; + wire n_0_496; + wire n_0_497; + wire n_0_498; + wire n_0_499; + wire n_0_500; + wire n_0_501; + wire n_0_502; + wire n_0_503; + wire n_0_504; + wire n_0_505; + wire n_0_506; + wire n_0_507; + wire n_0_508; + wire n_0_509; + wire n_0_510; + wire n_0_511; + wire n_0_512; + wire n_0_513; + wire n_0_514; + wire n_0_515; + wire n_0_516; + wire n_0_517; + wire n_0_518; + wire n_0_519; + wire n_0_520; + wire n_0_521; + wire n_0_522; + wire n_0_523; + wire n_0_524; + wire n_0_525; + wire n_0_526; + wire n_0_527; + wire n_0_528; + wire n_0_529; + wire n_0_530; + wire n_0_531; + wire n_0_532; + wire n_0_533; + wire n_0_534; + wire n_0_535; + wire n_0_536; + wire n_0_537; + wire n_0_538; + wire n_0_539; + wire n_0_540; + wire n_0_541; + wire n_0_542; + wire n_0_543; + wire n_0_544; + wire n_0_545; + wire n_0_546; + wire n_0_547; + wire n_0_548; + wire n_0_549; + wire n_0_550; + wire n_0_551; + wire n_0_552; + wire n_0_553; + wire n_0_554; + wire n_0_555; + wire n_0_556; + wire n_0_557; + wire n_0_558; + wire n_0_559; + wire n_0_560; + wire n_0_561; + wire n_0_562; + wire n_0_563; + wire n_0_564; + wire n_0_565; + wire n_0_566; + wire n_0_567; + wire n_0_568; + wire n_0_569; + wire n_0_570; + wire n_0_571; + wire n_0_572; + wire n_0_573; + wire n_0_574; + wire n_0_575; + wire n_0_576; + wire n_0_577; + wire n_0_578; + wire n_0_579; + wire n_0_580; + wire n_0_581; + wire n_0_582; + wire n_0_583; + wire n_0_584; + wire n_0_585; + wire n_0_586; + wire n_0_587; + wire n_0_588; + wire n_0_589; + wire n_0_590; + wire n_0_591; + wire n_0_592; + wire n_0_593; + wire n_0_594; + wire n_0_595; + wire n_0_596; + wire n_0_597; + wire n_0_598; + wire n_0_599; + wire n_0_600; + wire n_0_601; + wire n_0_602; + wire n_0_603; + wire n_0_604; + wire n_0_605; + wire n_0_606; + wire n_0_607; + wire n_0_608; + wire n_0_609; + wire n_0_610; + wire n_0_611; + wire n_0_612; + wire n_0_613; + wire n_0_614; + wire n_0_615; + wire n_0_616; + wire n_0_617; + wire n_0_618; + wire n_0_619; + wire n_0_620; + wire n_0_621; + wire n_0_622; + wire n_0_623; + wire n_0_624; + wire n_0_625; + wire n_0_626; + wire n_0_627; + wire n_0_628; + wire n_0_629; + wire n_0_630; + wire n_0_631; + wire n_0_632; + wire n_0_633; + wire n_0_634; + wire n_0_635; + wire n_0_636; + wire n_0_637; + wire n_0_638; + wire n_0_639; + wire n_0_640; + wire n_0_641; + wire n_0_642; + wire n_0_643; + wire n_0_644; + wire n_0_645; + wire n_0_646; + wire n_0_647; + wire n_0_648; + wire n_0_649; + wire n_0_650; + wire n_0_651; + wire n_0_652; + wire n_0_653; + wire n_0_654; + wire n_0_655; + wire n_0_656; + wire n_0_657; + wire n_0_658; + wire n_0_659; + wire n_0_660; + wire n_0_661; + wire n_0_662; + wire n_0_663; + wire n_0_664; + wire n_0_665; + wire n_0_666; + wire n_0_667; + wire n_0_668; + wire n_0_669; + wire n_0_670; + wire n_0_671; + wire n_0_672; + wire n_0_673; + wire n_0_674; + wire n_0_675; + wire n_0_676; + wire n_0_677; + wire n_0_678; + wire n_0_679; + wire n_0_680; + wire n_0_681; + wire n_0_682; + wire n_0_683; + wire n_0_684; + wire n_0_685; + wire n_0_686; + wire n_0_687; + wire n_0_688; + wire n_0_689; + wire n_0_690; + wire n_0_691; + wire n_0_692; + wire n_0_693; + wire n_0_694; + wire n_0_695; + wire n_0_696; + wire n_0_697; + wire n_0_698; + wire n_0_699; + wire n_0_700; + wire n_0_701; + wire n_0_702; + wire n_0_703; + wire n_0_704; + wire n_0_705; + wire n_0_706; + wire n_0_707; + wire n_0_708; + wire n_0_709; + wire n_0_710; + wire n_0_711; + wire n_0_712; + wire n_0_713; + wire n_0_714; + wire n_0_715; + wire n_0_716; + wire n_0_717; + wire n_0_718; + wire n_0_719; + wire n_0_720; + wire n_0_721; + wire n_0_722; + wire n_0_723; + wire n_0_724; + wire n_0_725; + wire n_0_726; + wire n_0_727; + wire n_0_728; + wire n_0_729; + wire n_0_730; + wire n_0_731; + wire n_0_732; + wire n_0_733; + wire n_0_734; + wire n_0_735; + wire n_0_736; + wire n_0_737; + wire n_0_738; + wire n_0_739; + wire n_0_740; + + INV_X1_LVT i_0_725 (.A(op2[31]), .ZN(n_0_692)); + INV_X1_LVT i_0_724 (.A(op1[31]), .ZN(n_0_691)); + INV_X1_LVT i_0_718 (.A(aluOp[1]), .ZN(n_0_685)); + INV_X1_LVT i_0_717 (.A(aluOp[2]), .ZN(n_0_684)); + NOR2_X1_LVT i_0_599 (.A1(n_0_685), .A2(n_0_684), .ZN(n_0_567)); + INV_X1_LVT i_0_598 (.A(n_0_567), .ZN(n_0_566)); + INV_X1_LVT i_0_716 (.A(aluOp[0]), .ZN(n_0_683)); + NAND2_X1_LVT i_0_602 (.A1(aluOp[2]), .A2(aluNegAr), .ZN(n_0_570)); + OAI21_X1_LVT i_0_590 (.A(n_0_566), .B1(n_0_683), .B2(n_0_570), .ZN(n_0_558)); + INV_X1_LVT i_0_714 (.A(aluBypass), .ZN(n_0_681)); + NOR2_X1_LVT i_0_601 (.A1(n_0_684), .A2(aluOp[0]), .ZN(n_0_569)); + NAND2_X1_LVT i_0_597 (.A1(n_0_681), .A2(n_0_569), .ZN(n_0_565)); + INV_X1_LVT i_0_596 (.A(n_0_565), .ZN(n_0_564)); + OAI22_X1_LVT i_0_589 (.A1(n_0_691), .A2(n_0_558), .B1(op1[31]), .B2(n_0_564), + .ZN(n_0_557)); + NOR2_X1_LVT i_0_588 (.A1(n_0_692), .A2(n_0_557), .ZN(n_0_556)); + datapathS i_9 (.op2(op2), .op1(op1), .p_0({n_31, n_30, n_29, n_28, n_27, n_26, + n_25, n_24, n_23, n_22, n_21, n_20, n_19, n_18, n_17, n_16, n_15, n_14, + n_13, n_12, n_11, n_10, n_9, n_8, n_7, n_6, n_5, n_4, n_3, n_2, n_1, n_0})); + NAND4_X1_LVT i_0_614 (.A1(n_0_685), .A2(n_0_681), .A3(n_0_684), .A4(n_0_683), + .ZN(n_0_582)); + NOR2_X1_LVT i_0_613 (.A1(aluNegAr), .A2(n_0_582), .ZN(n_0_581)); + datapathS__0_6 i_10 (.op1(op1), .p_0({n_63, n_62, n_61, n_60, n_59, n_58, + n_57, n_56, n_55, n_54, n_53, n_52, n_51, n_50, n_49, n_48, n_47, n_46, + n_45, n_44, n_43, n_42, n_41, n_40, n_39, n_38, n_37, n_36, n_35, n_34, + n_33, n_32}), .op2(op2)); + INV_X1_LVT i_0_715 (.A(aluNegAr), .ZN(n_0_682)); + NOR2_X1_LVT i_0_612 (.A1(n_0_682), .A2(n_0_582), .ZN(n_0_580)); + AOI221_X1_LVT i_0_587 (.A(n_0_556), .B1(n_31), .B2(n_0_581), .C1(n_63), + .C2(n_0_580), .ZN(n_0_555)); + NOR3_X1_LVT i_0_654 (.A1(aluOp[1]), .A2(aluBypass), .A3(n_0_683), .ZN(n_0_622)); + NAND2_X1_LVT i_0_653 (.A1(n_0_684), .A2(n_0_622), .ZN(n_0_621)); + INV_X1_LVT i_0_734 (.A(op2[0]), .ZN(n_0_701)); + INV_X1_LVT i_0_756 (.A(op2[3]), .ZN(n_0_723)); + NOR2_X1_LVT i_0_650 (.A1(op2[4]), .A2(n_0_723), .ZN(n_0_618)); + INV_X1_LVT i_0_649 (.A(n_0_618), .ZN(n_0_617)); + NOR2_X1_LVT i_0_648 (.A1(op2[4]), .A2(op2[3]), .ZN(n_0_616)); + INV_X1_LVT i_0_647 (.A(n_0_616), .ZN(n_0_615)); + INV_X1_LVT i_0_771 (.A(op2[4]), .ZN(n_0_738)); + INV_X1_LVT i_0_767 (.A(op1[15]), .ZN(n_0_734)); + INV_X1_LVT i_0_746 (.A(op1[7]), .ZN(n_0_713)); + AOI22_X1_LVT i_0_651 (.A1(n_0_734), .A2(n_0_723), .B1(op2[3]), .B2(n_0_713), + .ZN(n_0_619)); + OAI222_X1_LVT i_0_646 (.A1(op1[23]), .A2(n_0_617), .B1(op1[31]), .B2(n_0_615), + .C1(n_0_738), .C2(n_0_619), .ZN(n_0_614)); + NOR2_X1_LVT i_0_645 (.A1(op2[2]), .A2(n_0_614), .ZN(n_0_613)); + NOR2_X1_LVT i_0_696 (.A1(op1[3]), .A2(n_0_723), .ZN(n_0_663)); + INV_X1_LVT i_0_739 (.A(op1[11]), .ZN(n_0_706)); + AOI21_X1_LVT i_0_644 (.A(n_0_663), .B1(n_0_723), .B2(n_0_706), .ZN(n_0_612)); + AOI22_X1_LVT i_0_643 (.A1(op2[4]), .A2(n_0_612), .B1(op1[27]), .B2(n_0_616), + .ZN(n_0_611)); + INV_X1_LVT i_0_722 (.A(op1[19]), .ZN(n_0_689)); + OAI21_X1_LVT i_0_642 (.A(n_0_611), .B1(n_0_689), .B2(n_0_617), .ZN(n_0_610)); + AOI21_X1_LVT i_0_641 (.A(n_0_613), .B1(op2[2]), .B2(n_0_610), .ZN(n_0_609)); + INV_X1_LVT i_0_761 (.A(op2[1]), .ZN(n_0_728)); + OAI22_X1_LVT i_0_640 (.A1(op2[4]), .A2(op1[21]), .B1(n_0_738), .B2(op1[5]), + .ZN(n_0_608)); + NAND2_X1_LVT i_0_639 (.A1(op2[3]), .A2(n_0_608), .ZN(n_0_607)); + INV_X1_LVT i_0_747 (.A(op1[13]), .ZN(n_0_714)); + NOR2_X1_LVT i_0_638 (.A1(n_0_738), .A2(op2[3]), .ZN(n_0_606)); + INV_X1_LVT i_0_743 (.A(op1[29]), .ZN(n_0_710)); + AOI221_X1_LVT i_0_636 (.A(op2[2]), .B1(n_0_714), .B2(n_0_606), .C1(n_0_710), + .C2(n_0_616), .ZN(n_0_604)); + OAI22_X1_LVT i_0_635 (.A1(op2[4]), .A2(op1[17]), .B1(n_0_738), .B2(op1[1]), + .ZN(n_0_603)); + INV_X1_LVT i_0_755 (.A(op1[9]), .ZN(n_0_722)); + INV_X1_LVT i_0_637 (.A(n_0_606), .ZN(n_0_605)); + INV_X1_LVT i_0_732 (.A(op1[25]), .ZN(n_0_699)); + OAI222_X1_LVT i_0_634 (.A1(n_0_723), .A2(n_0_603), .B1(n_0_722), .B2(n_0_605), + .C1(n_0_699), .C2(n_0_615), .ZN(n_0_602)); + AOI22_X1_LVT i_0_633 (.A1(n_0_607), .A2(n_0_604), .B1(op2[2]), .B2(n_0_602), + .ZN(n_0_601)); + OAI221_X1_LVT i_0_616 (.A(n_0_701), .B1(op2[1]), .B2(n_0_609), .C1(n_0_728), + .C2(n_0_601), .ZN(n_0_584)); + INV_X1_LVT i_0_729 (.A(op1[12]), .ZN(n_0_696)); + INV_X1_LVT i_0_731 (.A(op1[28]), .ZN(n_0_698)); + AOI22_X1_LVT i_0_622 (.A1(n_0_696), .A2(n_0_606), .B1(n_0_698), .B2(n_0_616), + .ZN(n_0_590)); + INV_X1_LVT i_0_726 (.A(op2[2]), .ZN(n_0_693)); + NOR2_X1_LVT i_0_701 (.A1(n_0_738), .A2(op1[4]), .ZN(n_0_668)); + INV_X1_LVT i_0_760 (.A(op1[20]), .ZN(n_0_727)); + AOI21_X1_LVT i_0_623 (.A(n_0_668), .B1(n_0_738), .B2(n_0_727), .ZN(n_0_591)); + OAI211_X1_LVT i_0_621 (.A(n_0_590), .B(n_0_693), .C1(n_0_723), .C2(n_0_591), + .ZN(n_0_589)); + OAI22_X1_LVT i_0_626 (.A1(op1[16]), .A2(op2[4]), .B1(n_0_738), .B2(op1[0]), + .ZN(n_0_594)); + INV_X1_LVT i_0_769 (.A(op1[24]), .ZN(n_0_736)); + OAI22_X1_LVT i_0_625 (.A1(n_0_723), .A2(n_0_594), .B1(n_0_736), .B2(n_0_615), + .ZN(n_0_593)); + AOI21_X1_LVT i_0_624 (.A(n_0_593), .B1(op1[8]), .B2(n_0_606), .ZN(n_0_592)); + OAI21_X1_LVT i_0_620 (.A(n_0_589), .B1(n_0_693), .B2(n_0_592), .ZN(n_0_588)); + INV_X1_LVT i_0_737 (.A(op1[6]), .ZN(n_0_704)); + INV_X1_LVT i_0_720 (.A(op1[22]), .ZN(n_0_687)); + OAI22_X1_LVT i_0_632 (.A1(n_0_738), .A2(n_0_704), .B1(op2[4]), .B2(n_0_687), + .ZN(n_0_600)); + OAI221_X1_LVT i_0_631 (.A(n_0_693), .B1(n_0_723), .B2(n_0_600), .C1(op1[14]), + .C2(n_0_605), .ZN(n_0_599)); + INV_X1_LVT i_0_750 (.A(op1[30]), .ZN(n_0_717)); + AOI21_X1_LVT i_0_630 (.A(n_0_599), .B1(n_0_717), .B2(n_0_616), .ZN(n_0_598)); + INV_X1_LVT i_0_738 (.A(op1[18]), .ZN(n_0_705)); + NOR2_X1_LVT i_0_628 (.A1(n_0_705), .A2(n_0_617), .ZN(n_0_596)); + INV_X1_LVT i_0_727 (.A(op1[2]), .ZN(n_0_694)); + INV_X1_LVT i_0_766 (.A(op1[10]), .ZN(n_0_733)); + OAI22_X1_LVT i_0_629 (.A1(n_0_723), .A2(n_0_694), .B1(n_0_733), .B2(op2[3]), + .ZN(n_0_597)); + AOI221_X1_LVT i_0_627 (.A(n_0_596), .B1(op1[26]), .B2(n_0_616), .C1(op2[4]), + .C2(n_0_597), .ZN(n_0_595)); + OAI21_X1_LVT i_0_619 (.A(n_0_728), .B1(n_0_693), .B2(n_0_595), .ZN(n_0_587)); + OAI22_X1_LVT i_0_618 (.A1(n_0_728), .A2(n_0_588), .B1(n_0_598), .B2(n_0_587), + .ZN(n_0_586)); + INV_X1_LVT i_0_617 (.A(n_0_586), .ZN(n_0_585)); + OAI21_X1_LVT i_0_615 (.A(n_0_584), .B1(n_0_701), .B2(n_0_585), .ZN(n_0_583)); + NOR2_X1_LVT i_0_607 (.A1(op2[4]), .A2(op2[2]), .ZN(n_0_575)); + NAND2_X1_LVT i_0_606 (.A1(n_0_723), .A2(n_0_575), .ZN(n_0_574)); + INV_X1_LVT i_0_605 (.A(n_0_574), .ZN(n_0_573)); + NAND2_X1_LVT i_0_604 (.A1(n_0_728), .A2(n_0_573), .ZN(n_0_572)); + NAND2_X1_LVT i_0_611 (.A1(aluOp[2]), .A2(n_0_622), .ZN(n_0_579)); + INV_X1_LVT i_0_610 (.A(n_0_579), .ZN(n_0_578)); + NAND2_X1_LVT i_0_594 (.A1(n_0_701), .A2(n_0_578), .ZN(n_0_562)); + NOR3_X1_LVT i_0_592 (.A1(aluNegAr), .A2(n_0_572), .A3(n_0_562), .ZN(n_0_560)); + INV_X1_LVT i_0_600 (.A(n_0_569), .ZN(n_0_568)); + OAI21_X1_LVT i_0_595 (.A(n_0_568), .B1(aluOp[1]), .B2(n_0_570), .ZN(n_0_563)); + AOI211_X1_LVT i_0_591 (.A(aluBypass), .B(n_0_560), .C1(n_0_692), .C2(n_0_563), + .ZN(n_0_559)); + OAI221_X1_LVT i_0_586 (.A(n_0_555), .B1(n_0_621), .B2(n_0_583), .C1(n_0_691), + .C2(n_0_559), .ZN(result[31])); + AOI22_X1_LVT i_0_580 (.A1(n_62), .A2(n_0_580), .B1(n_30), .B2(n_0_581), + .ZN(n_0_549)); + NAND2_X1_LVT i_0_576 (.A1(aluNegAr), .A2(n_0_578), .ZN(n_0_545)); + INV_X1_LVT i_0_603 (.A(n_0_572), .ZN(n_0_571)); + NOR3_X1_LVT i_0_574 (.A1(n_0_691), .A2(n_0_545), .A3(n_0_571), .ZN(n_0_543)); + AOI22_X1_LVT i_0_573 (.A1(n_0_717), .A2(n_0_565), .B1(op1[30]), .B2(n_0_566), + .ZN(n_0_542)); + AOI21_X1_LVT i_0_572 (.A(n_0_543), .B1(op2[30]), .B2(n_0_542), .ZN(n_0_541)); + NAND2_X1_LVT i_0_579 (.A1(op2[0]), .A2(n_0_578), .ZN(n_0_548)); + NAND2_X1_LVT i_0_577 (.A1(op1[31]), .A2(n_0_571), .ZN(n_0_546)); + OAI211_X1_LVT i_0_571 (.A(n_0_549), .B(n_0_541), .C1(n_0_548), .C2(n_0_546), + .ZN(n_0_540)); + OAI221_X1_LVT i_0_581 (.A(n_0_681), .B1(op2[30]), .B2(n_0_568), .C1(n_0_572), + .C2(n_0_562), .ZN(n_0_550)); + AOI21_X1_LVT i_0_570 (.A(n_0_540), .B1(op1[30]), .B2(n_0_550), .ZN(n_0_539)); + INV_X1_LVT i_0_752 (.A(op1[23]), .ZN(n_0_719)); + OAI222_X1_LVT i_0_585 (.A1(n_0_713), .A2(n_0_605), .B1(n_0_719), .B2(n_0_615), + .C1(n_0_734), .C2(n_0_617), .ZN(n_0_554)); + AOI22_X1_LVT i_0_584 (.A1(op2[2]), .A2(n_0_554), .B1(n_0_693), .B2(n_0_610), + .ZN(n_0_553)); + OAI22_X1_LVT i_0_583 (.A1(n_0_728), .A2(n_0_553), .B1(op2[1]), .B2(n_0_601), + .ZN(n_0_552)); + AOI22_X1_LVT i_0_582 (.A1(n_0_701), .A2(n_0_585), .B1(op2[0]), .B2(n_0_552), + .ZN(n_0_551)); + OAI21_X1_LVT i_0_569 (.A(n_0_539), .B1(n_0_621), .B2(n_0_551), .ZN(result[30])); + INV_X1_LVT i_0_578 (.A(n_0_548), .ZN(n_0_547)); + NAND3_X1_LVT i_0_562 (.A1(op1[30]), .A2(n_0_571), .A3(n_0_547), .ZN(n_0_532)); + NAND2_X1_LVT i_0_558 (.A1(n_61), .A2(n_0_580), .ZN(n_0_528)); + OAI21_X1_LVT i_0_557 (.A(n_0_681), .B1(op2[29]), .B2(n_0_568), .ZN(n_0_527)); + NAND2_X1_LVT i_0_556 (.A1(op1[29]), .A2(n_0_566), .ZN(n_0_526)); + AOI22_X1_LVT i_0_555 (.A1(op1[29]), .A2(n_0_527), .B1(op2[29]), .B2(n_0_526), + .ZN(n_0_525)); + AOI21_X1_LVT i_0_554 (.A(n_0_525), .B1(n_0_710), .B2(n_0_565), .ZN(n_0_524)); + AOI211_X1_LVT i_0_553 (.A(n_0_543), .B(n_0_524), .C1(n_29), .C2(n_0_581), + .ZN(n_0_523)); + AND3_X1_LVT i_0_552 (.A1(n_0_532), .A2(n_0_528), .A3(n_0_523), .ZN(n_0_522)); + INV_X1_LVT i_0_652 (.A(n_0_621), .ZN(n_0_620)); + NAND2_X1_LVT i_0_565 (.A1(n_0_728), .A2(n_0_588), .ZN(n_0_535)); + AOI22_X1_LVT i_0_568 (.A1(n_0_723), .A2(n_0_600), .B1(op1[14]), .B2(n_0_618), + .ZN(n_0_538)); + AOI22_X1_LVT i_0_567 (.A1(n_0_693), .A2(n_0_595), .B1(op2[2]), .B2(n_0_538), + .ZN(n_0_537)); + INV_X1_LVT i_0_566 (.A(n_0_537), .ZN(n_0_536)); + OAI21_X1_LVT i_0_564 (.A(n_0_535), .B1(n_0_728), .B2(n_0_536), .ZN(n_0_534)); + OAI221_X1_LVT i_0_563 (.A(n_0_620), .B1(op2[0]), .B2(n_0_552), .C1(n_0_701), + .C2(n_0_534), .ZN(n_0_533)); + NAND2_X1_LVT i_0_561 (.A1(op2[1]), .A2(n_0_573), .ZN(n_0_531)); + INV_X1_LVT i_0_560 (.A(n_0_531), .ZN(n_0_530)); + AOI22_X1_LVT i_0_559 (.A1(op1[31]), .A2(n_0_530), .B1(op1[29]), .B2(n_0_571), + .ZN(n_0_529)); + OAI211_X1_LVT i_0_551 (.A(n_0_522), .B(n_0_533), .C1(n_0_562), .C2(n_0_529), + .ZN(result[29])); + INV_X1_LVT i_0_733 (.A(op2[28]), .ZN(n_0_700)); + AOI221_X1_LVT i_0_546 (.A(n_0_700), .B1(op1[28]), .B2(n_0_566), .C1(n_0_698), + .C2(n_0_565), .ZN(n_0_517)); + OAI21_X1_LVT i_0_543 (.A(n_0_681), .B1(op2[28]), .B2(n_0_568), .ZN(n_0_514)); + AOI22_X1_LVT i_0_542 (.A1(n_28), .A2(n_0_581), .B1(op1[28]), .B2(n_0_514), + .ZN(n_0_513)); + NAND2_X1_LVT i_0_544 (.A1(n_60), .A2(n_0_580), .ZN(n_0_515)); + NAND2_X1_LVT i_0_545 (.A1(op1[31]), .A2(n_0_574), .ZN(n_0_516)); + OAI211_X1_LVT i_0_541 (.A(n_0_513), .B(n_0_515), .C1(n_0_545), .C2(n_0_516), + .ZN(n_0_512)); + AOI22_X1_LVT i_0_540 (.A1(op1[30]), .A2(n_0_530), .B1(op1[28]), .B2(n_0_571), + .ZN(n_0_511)); + OAI22_X1_LVT i_0_539 (.A1(n_0_562), .A2(n_0_511), .B1(n_0_548), .B2(n_0_529), + .ZN(n_0_510)); + NOR3_X1_LVT i_0_538 (.A1(n_0_517), .A2(n_0_512), .A3(n_0_510), .ZN(n_0_509)); + OAI22_X1_LVT i_0_550 (.A1(n_0_714), .A2(n_0_617), .B1(op2[3]), .B2(n_0_608), + .ZN(n_0_521)); + OAI22_X1_LVT i_0_549 (.A1(op2[2]), .A2(n_0_602), .B1(n_0_693), .B2(n_0_521), + .ZN(n_0_520)); + AOI22_X1_LVT i_0_548 (.A1(op2[1]), .A2(n_0_520), .B1(n_0_728), .B2(n_0_553), + .ZN(n_0_519)); + OAI22_X1_LVT i_0_547 (.A1(op2[0]), .A2(n_0_534), .B1(n_0_701), .B2(n_0_519), + .ZN(n_0_518)); + OAI21_X1_LVT i_0_537 (.A(n_0_509), .B1(n_0_621), .B2(n_0_518), .ZN(result[28])); + AOI22_X1_LVT i_0_517 (.A1(n_27), .A2(n_0_581), .B1(n_59), .B2(n_0_580), + .ZN(n_0_489)); + INV_X1_LVT i_0_721 (.A(op1[27]), .ZN(n_0_688)); + OAI21_X1_LVT i_0_516 (.A(n_0_681), .B1(op2[27]), .B2(n_0_568), .ZN(n_0_488)); + INV_X1_LVT i_0_515 (.A(n_0_488), .ZN(n_0_487)); + OAI221_X1_LVT i_0_514 (.A(n_0_489), .B1(n_0_545), .B2(n_0_516), .C1(n_0_688), + .C2(n_0_487), .ZN(n_0_486)); + OAI21_X1_LVT i_0_530 (.A(op2[1]), .B1(n_0_710), .B2(n_0_574), .ZN(n_0_502)); + OAI21_X1_LVT i_0_529 (.A(n_0_728), .B1(n_0_688), .B2(n_0_574), .ZN(n_0_501)); + NAND2_X1_LVT i_0_528 (.A1(n_0_502), .A2(n_0_501), .ZN(n_0_500)); + AOI21_X1_LVT i_0_527 (.A(n_0_545), .B1(n_0_701), .B2(n_0_500), .ZN(n_0_499)); + NAND2_X1_LVT i_0_609 (.A1(n_0_682), .A2(n_0_578), .ZN(n_0_577)); + NOR2_X1_LVT i_0_526 (.A1(op2[4]), .A2(n_0_693), .ZN(n_0_498)); + NAND2_X1_LVT i_0_525 (.A1(n_0_723), .A2(n_0_498), .ZN(n_0_497)); + OAI22_X1_LVT i_0_523 (.A1(n_0_688), .A2(n_0_574), .B1(n_0_691), .B2(n_0_497), + .ZN(n_0_495)); + OAI21_X1_LVT i_0_522 (.A(n_0_502), .B1(op2[1]), .B2(n_0_495), .ZN(n_0_494)); + AOI21_X1_LVT i_0_521 (.A(n_0_577), .B1(n_0_701), .B2(n_0_494), .ZN(n_0_493)); + NOR2_X1_LVT i_0_520 (.A1(n_0_499), .A2(n_0_493), .ZN(n_0_492)); + AOI21_X1_LVT i_0_519 (.A(n_0_492), .B1(op2[0]), .B2(n_0_511), .ZN(n_0_491)); + AOI22_X1_LVT i_0_518 (.A1(n_0_688), .A2(n_0_565), .B1(op1[27]), .B2(n_0_566), + .ZN(n_0_490)); + AOI211_X1_LVT i_0_513 (.A(n_0_486), .B(n_0_491), .C1(op2[27]), .C2(n_0_490), + .ZN(n_0_485)); + NOR3_X1_LVT i_0_536 (.A1(op2[4]), .A2(n_0_696), .A3(n_0_723), .ZN(n_0_508)); + AOI21_X1_LVT i_0_535 (.A(n_0_508), .B1(n_0_723), .B2(n_0_591), .ZN(n_0_507)); + OAI22_X1_LVT i_0_534 (.A1(op2[2]), .A2(n_0_592), .B1(n_0_693), .B2(n_0_507), + .ZN(n_0_506)); + NOR2_X1_LVT i_0_533 (.A1(n_0_728), .A2(n_0_506), .ZN(n_0_505)); + AOI21_X1_LVT i_0_532 (.A(n_0_505), .B1(n_0_728), .B2(n_0_536), .ZN(n_0_504)); + OAI22_X1_LVT i_0_531 (.A1(n_0_701), .A2(n_0_504), .B1(op2[0]), .B2(n_0_519), + .ZN(n_0_503)); + OAI21_X1_LVT i_0_512 (.A(n_0_485), .B1(n_0_621), .B2(n_0_503), .ZN(result[27])); + OAI21_X1_LVT i_0_500 (.A(n_0_681), .B1(op2[26]), .B2(n_0_568), .ZN(n_0_473)); + NAND2_X1_LVT i_0_499 (.A1(op1[26]), .A2(n_0_473), .ZN(n_0_472)); + AOI22_X1_LVT i_0_498 (.A1(n_58), .A2(n_0_580), .B1(n_26), .B2(n_0_581), + .ZN(n_0_471)); + INV_X1_LVT i_0_744 (.A(op1[26]), .ZN(n_0_711)); + OAI221_X1_LVT i_0_501 (.A(op2[26]), .B1(op1[26]), .B2(n_0_564), .C1(n_0_711), + .C2(n_0_567), .ZN(n_0_474)); + NAND3_X1_LVT i_0_497 (.A1(n_0_472), .A2(n_0_471), .A3(n_0_474), .ZN(n_0_470)); + INV_X1_LVT i_0_524 (.A(n_0_497), .ZN(n_0_496)); + AOI22_X1_LVT i_0_505 (.A1(op1[30]), .A2(n_0_496), .B1(op1[26]), .B2(n_0_573), + .ZN(n_0_478)); + NOR2_X1_LVT i_0_504 (.A1(op2[1]), .A2(n_0_478), .ZN(n_0_477)); + AOI21_X1_LVT i_0_503 (.A(n_0_477), .B1(op1[28]), .B2(n_0_530), .ZN(n_0_476)); + NAND2_X1_LVT i_0_502 (.A1(n_0_701), .A2(n_0_476), .ZN(n_0_475)); + AOI21_X1_LVT i_0_489 (.A(n_0_577), .B1(op2[0]), .B2(n_0_494), .ZN(n_0_462)); + AOI21_X1_LVT i_0_488 (.A(n_0_470), .B1(n_0_475), .B2(n_0_462), .ZN(n_0_461)); + AOI21_X1_LVT i_0_511 (.A(n_0_616), .B1(n_0_738), .B2(n_0_706), .ZN(n_0_484)); + AOI21_X1_LVT i_0_510 (.A(n_0_484), .B1(n_0_723), .B2(op1[19]), .ZN(n_0_483)); + INV_X1_LVT i_0_757 (.A(op1[3]), .ZN(n_0_724)); + NOR2_X1_LVT i_0_687 (.A1(n_0_724), .A2(op2[3]), .ZN(n_0_654)); + INV_X1_LVT i_0_686 (.A(n_0_654), .ZN(n_0_653)); + AOI21_X1_LVT i_0_509 (.A(n_0_483), .B1(op2[4]), .B2(n_0_653), .ZN(n_0_482)); + AOI22_X1_LVT i_0_508 (.A1(n_0_693), .A2(n_0_554), .B1(op2[2]), .B2(n_0_482), + .ZN(n_0_481)); + OAI22_X1_LVT i_0_507 (.A1(n_0_728), .A2(n_0_481), .B1(op2[1]), .B2(n_0_520), + .ZN(n_0_480)); + AOI22_X1_LVT i_0_506 (.A1(op2[0]), .A2(n_0_480), .B1(n_0_701), .B2(n_0_504), + .ZN(n_0_479)); + NAND3_X1_LVT i_0_491 (.A1(op2[0]), .A2(n_0_516), .A3(n_0_500), .ZN(n_0_464)); + NAND2_X1_LVT i_0_494 (.A1(op1[31]), .A2(n_0_615), .ZN(n_0_467)); + OAI21_X1_LVT i_0_492 (.A(n_0_467), .B1(n_0_728), .B2(n_0_516), .ZN(n_0_465)); + OAI21_X1_LVT i_0_490 (.A(n_0_464), .B1(n_0_475), .B2(n_0_465), .ZN(n_0_463)); + OAI221_X1_LVT i_0_487 (.A(n_0_461), .B1(n_0_621), .B2(n_0_479), .C1(n_0_545), + .C2(n_0_463), .ZN(result[26])); + AOI22_X1_LVT i_0_479 (.A1(n_57), .A2(n_0_580), .B1(n_25), .B2(n_0_581), + .ZN(n_0_453)); + INV_X1_LVT i_0_730 (.A(op2[25]), .ZN(n_0_697)); + AOI21_X1_LVT i_0_478 (.A(aluBypass), .B1(n_0_697), .B2(n_0_569), .ZN(n_0_452)); + AOI22_X1_LVT i_0_480 (.A1(op1[25]), .A2(n_0_567), .B1(n_0_699), .B2(n_0_564), + .ZN(n_0_454)); + OAI221_X1_LVT i_0_477 (.A(n_0_453), .B1(n_0_699), .B2(n_0_452), .C1(n_0_697), + .C2(n_0_454), .ZN(n_0_451)); + INV_X1_LVT i_0_575 (.A(n_0_545), .ZN(n_0_544)); + AOI21_X1_LVT i_0_476 (.A(n_0_451), .B1(n_0_544), .B2(n_0_465), .ZN(n_0_450)); + AOI22_X1_LVT i_0_475 (.A1(op1[29]), .A2(n_0_496), .B1(op1[25]), .B2(n_0_573), + .ZN(n_0_449)); + NAND2_X1_LVT i_0_474 (.A1(n_0_728), .A2(n_0_449), .ZN(n_0_448)); + OAI21_X1_LVT i_0_473 (.A(n_0_448), .B1(n_0_728), .B2(n_0_495), .ZN(n_0_447)); + OAI22_X1_LVT i_0_472 (.A1(n_0_548), .A2(n_0_476), .B1(n_0_562), .B2(n_0_447), + .ZN(n_0_446)); + INV_X1_LVT i_0_471 (.A(n_0_446), .ZN(n_0_445)); + OAI222_X1_LVT i_0_486 (.A1(n_0_733), .A2(n_0_617), .B1(n_0_694), .B2(n_0_605), + .C1(n_0_705), .C2(n_0_615), .ZN(n_0_460)); + NOR2_X1_LVT i_0_485 (.A1(n_0_693), .A2(n_0_460), .ZN(n_0_459)); + AOI21_X1_LVT i_0_484 (.A(n_0_459), .B1(n_0_693), .B2(n_0_538), .ZN(n_0_458)); + OAI22_X1_LVT i_0_483 (.A1(n_0_728), .A2(n_0_458), .B1(op2[1]), .B2(n_0_506), + .ZN(n_0_457)); + INV_X1_LVT i_0_482 (.A(n_0_457), .ZN(n_0_456)); + OAI221_X1_LVT i_0_481 (.A(n_0_620), .B1(n_0_701), .B2(n_0_456), .C1(op2[0]), + .C2(n_0_480), .ZN(n_0_455)); + NAND3_X1_LVT i_0_470 (.A1(n_0_450), .A2(n_0_445), .A3(n_0_455), .ZN( + result[25])); + INV_X1_LVT i_0_493 (.A(n_0_467), .ZN(n_0_466)); + OAI211_X1_LVT i_0_455 (.A(n_0_544), .B(n_0_465), .C1(op2[0]), .C2(n_0_466), + .ZN(n_0_430)); + OAI21_X1_LVT i_0_462 (.A(n_0_681), .B1(op2[24]), .B2(n_0_568), .ZN(n_0_437)); + AOI222_X1_LVT i_0_461 (.A1(op1[24]), .A2(n_0_437), .B1(n_56), .B2(n_0_580), + .C1(n_24), .C2(n_0_581), .ZN(n_0_436)); + INV_X1_LVT i_0_460 (.A(n_0_436), .ZN(n_0_435)); + AOI22_X1_LVT i_0_458 (.A1(op1[24]), .A2(n_0_573), .B1(op1[28]), .B2(n_0_496), + .ZN(n_0_433)); + OAI22_X1_LVT i_0_457 (.A1(op2[1]), .A2(n_0_433), .B1(n_0_728), .B2(n_0_478), + .ZN(n_0_432)); + INV_X1_LVT i_0_456 (.A(n_0_432), .ZN(n_0_431)); + OAI22_X1_LVT i_0_454 (.A1(n_0_562), .A2(n_0_431), .B1(n_0_548), .B2(n_0_447), + .ZN(n_0_429)); + AOI22_X1_LVT i_0_459 (.A1(n_0_736), .A2(n_0_565), .B1(op1[24]), .B2(n_0_566), + .ZN(n_0_434)); + AOI211_X1_LVT i_0_453 (.A(n_0_435), .B(n_0_429), .C1(op2[24]), .C2(n_0_434), + .ZN(n_0_428)); + NAND2_X1_LVT i_0_467 (.A1(n_0_693), .A2(n_0_521), .ZN(n_0_442)); + NOR2_X1_LVT i_0_469 (.A1(op2[3]), .A2(n_0_603), .ZN(n_0_444)); + AOI21_X1_LVT i_0_468 (.A(n_0_444), .B1(op1[9]), .B2(n_0_618), .ZN(n_0_443)); + OAI21_X1_LVT i_0_466 (.A(n_0_442), .B1(n_0_693), .B2(n_0_443), .ZN(n_0_441)); + NAND2_X1_LVT i_0_465 (.A1(op2[1]), .A2(n_0_441), .ZN(n_0_440)); + OAI21_X1_LVT i_0_464 (.A(n_0_440), .B1(op2[1]), .B2(n_0_481), .ZN(n_0_439)); + OAI221_X1_LVT i_0_463 (.A(n_0_620), .B1(op2[0]), .B2(n_0_456), .C1(n_0_701), + .C2(n_0_439), .ZN(n_0_438)); + NAND3_X1_LVT i_0_452 (.A1(n_0_430), .A2(n_0_428), .A3(n_0_438), .ZN( + result[24])); + INV_X1_LVT i_0_751 (.A(op2[23]), .ZN(n_0_718)); + AOI221_X1_LVT i_0_440 (.A(n_0_718), .B1(op1[23]), .B2(n_0_566), .C1(n_0_719), + .C2(n_0_565), .ZN(n_0_416)); + AOI222_X1_LVT i_0_438 (.A1(n_23), .A2(n_0_581), .B1(n_0_544), .B2(n_0_466), + .C1(n_55), .C2(n_0_580), .ZN(n_0_414)); + OAI21_X1_LVT i_0_437 (.A(n_0_414), .B1(n_0_548), .B2(n_0_431), .ZN(n_0_413)); + OAI21_X1_LVT i_0_439 (.A(n_0_681), .B1(op2[23]), .B2(n_0_568), .ZN(n_0_415)); + AOI211_X1_LVT i_0_436 (.A(n_0_416), .B(n_0_413), .C1(op1[23]), .C2(n_0_415), + .ZN(n_0_412)); + AOI22_X1_LVT i_0_444 (.A1(n_0_723), .A2(n_0_719), .B1(op2[3]), .B2(n_0_691), + .ZN(n_0_420)); + AOI22_X1_LVT i_0_443 (.A1(n_0_575), .A2(n_0_420), .B1(op1[27]), .B2(n_0_496), + .ZN(n_0_419)); + AOI22_X1_LVT i_0_442 (.A1(op2[1]), .A2(n_0_449), .B1(n_0_728), .B2(n_0_419), + .ZN(n_0_418)); + INV_X1_LVT i_0_441 (.A(n_0_418), .ZN(n_0_417)); + NAND2_X1_LVT i_0_447 (.A1(n_0_728), .A2(n_0_458), .ZN(n_0_423)); + NOR2_X1_LVT i_0_451 (.A1(op2[3]), .A2(n_0_594), .ZN(n_0_427)); + AOI21_X1_LVT i_0_450 (.A(n_0_427), .B1(op1[8]), .B2(n_0_618), .ZN(n_0_426)); + OAI22_X1_LVT i_0_449 (.A1(n_0_693), .A2(n_0_426), .B1(op2[2]), .B2(n_0_507), + .ZN(n_0_425)); + INV_X1_LVT i_0_448 (.A(n_0_425), .ZN(n_0_424)); + OAI21_X1_LVT i_0_446 (.A(n_0_423), .B1(n_0_728), .B2(n_0_424), .ZN(n_0_422)); + AOI22_X1_LVT i_0_445 (.A1(op2[0]), .A2(n_0_422), .B1(n_0_701), .B2(n_0_439), + .ZN(n_0_421)); + OAI221_X1_LVT i_0_435 (.A(n_0_412), .B1(n_0_562), .B2(n_0_417), .C1(n_0_621), + .C2(n_0_421), .ZN(result[23])); + AOI22_X1_LVT i_0_419 (.A1(n_54), .A2(n_0_580), .B1(n_22), .B2(n_0_581), + .ZN(n_0_396)); + INV_X1_LVT i_0_719 (.A(op2[22]), .ZN(n_0_686)); + AOI21_X1_LVT i_0_420 (.A(aluBypass), .B1(n_0_686), .B2(n_0_569), .ZN(n_0_397)); + OAI21_X1_LVT i_0_418 (.A(n_0_396), .B1(n_0_687), .B2(n_0_397), .ZN(n_0_395)); + AOI22_X1_LVT i_0_421 (.A1(op1[22]), .A2(n_0_566), .B1(n_0_687), .B2(n_0_565), + .ZN(n_0_398)); + AOI21_X1_LVT i_0_417 (.A(n_0_395), .B1(op2[22]), .B2(n_0_398), .ZN(n_0_394)); + NAND2_X1_LVT i_0_432 (.A1(n_0_728), .A2(n_0_441), .ZN(n_0_409)); + AND2_X1_LVT i_0_434 (.A1(n_0_738), .A2(n_0_619), .ZN(n_0_411)); + AOI22_X1_LVT i_0_433 (.A1(n_0_693), .A2(n_0_482), .B1(op2[2]), .B2(n_0_411), + .ZN(n_0_410)); + OAI21_X1_LVT i_0_431 (.A(n_0_409), .B1(n_0_728), .B2(n_0_410), .ZN(n_0_408)); + OAI22_X1_LVT i_0_430 (.A1(n_0_701), .A2(n_0_408), .B1(op2[0]), .B2(n_0_422), + .ZN(n_0_407)); + AOI22_X1_LVT i_0_429 (.A1(n_0_723), .A2(n_0_687), .B1(op2[3]), .B2(n_0_717), + .ZN(n_0_406)); + AOI22_X1_LVT i_0_428 (.A1(n_0_575), .A2(n_0_406), .B1(op1[26]), .B2(n_0_496), + .ZN(n_0_405)); + AND2_X1_LVT i_0_427 (.A1(n_0_728), .A2(n_0_405), .ZN(n_0_404)); + AOI21_X1_LVT i_0_426 (.A(n_0_404), .B1(op2[1]), .B2(n_0_433), .ZN(n_0_403)); + INV_X1_LVT i_0_425 (.A(n_0_403), .ZN(n_0_402)); + OAI222_X1_LVT i_0_424 (.A1(n_0_545), .A2(n_0_467), .B1(n_0_701), .B2(n_0_417), + .C1(op2[0]), .C2(n_0_402), .ZN(n_0_401)); + NOR2_X1_LVT i_0_496 (.A1(n_0_738), .A2(n_0_691), .ZN(n_0_469)); + INV_X1_LVT i_0_495 (.A(n_0_469), .ZN(n_0_468)); + NAND3_X1_LVT i_0_423 (.A1(n_0_693), .A2(n_0_468), .A3(n_0_404), .ZN(n_0_400)); + OAI21_X1_LVT i_0_422 (.A(n_0_401), .B1(op2[0]), .B2(n_0_400), .ZN(n_0_399)); + OAI221_X1_LVT i_0_416 (.A(n_0_394), .B1(n_0_621), .B2(n_0_407), .C1(n_0_579), + .C2(n_0_399), .ZN(result[22])); + INV_X1_LVT i_0_759 (.A(op1[21]), .ZN(n_0_726)); + AOI22_X1_LVT i_0_399 (.A1(op1[21]), .A2(n_0_566), .B1(n_0_726), .B2(n_0_565), + .ZN(n_0_377)); + NOR2_X1_LVT i_0_692 (.A1(n_0_726), .A2(op2[21]), .ZN(n_0_659)); + AOI222_X1_LVT i_0_398 (.A1(op2[21]), .A2(n_0_377), .B1(n_21), .B2(n_0_581), + .C1(n_0_659), .C2(n_0_569), .ZN(n_0_376)); + INV_X1_LVT i_0_397 (.A(n_0_376), .ZN(n_0_375)); + AOI221_X1_LVT i_0_396 (.A(n_0_375), .B1(n_53), .B2(n_0_580), .C1(op1[21]), + .C2(aluBypass), .ZN(n_0_374)); + INV_X1_LVT i_0_608 (.A(n_0_577), .ZN(n_0_576)); + NAND2_X1_LVT i_0_403 (.A1(op2[0]), .A2(n_0_402), .ZN(n_0_381)); + AND2_X1_LVT i_0_410 (.A1(op2[1]), .A2(n_0_419), .ZN(n_0_388)); + OAI22_X1_LVT i_0_408 (.A1(n_0_723), .A2(n_0_710), .B1(n_0_726), .B2(op2[3]), + .ZN(n_0_386)); + AOI22_X1_LVT i_0_407 (.A1(n_0_575), .A2(n_0_386), .B1(op1[25]), .B2(n_0_496), + .ZN(n_0_385)); + AOI21_X1_LVT i_0_395 (.A(n_0_388), .B1(n_0_728), .B2(n_0_385), .ZN(n_0_373)); + OAI211_X1_LVT i_0_394 (.A(n_0_576), .B(n_0_381), .C1(op2[0]), .C2(n_0_373), + .ZN(n_0_372)); + AOI21_X1_LVT i_0_402 (.A(n_0_381), .B1(n_0_466), .B2(n_0_400), .ZN(n_0_380)); + INV_X1_LVT i_0_401 (.A(n_0_380), .ZN(n_0_379)); + NOR2_X1_LVT i_0_409 (.A1(n_0_575), .A2(n_0_467), .ZN(n_0_387)); + INV_X1_LVT i_0_406 (.A(n_0_385), .ZN(n_0_384)); + NOR2_X1_LVT i_0_405 (.A1(n_0_387), .A2(n_0_384), .ZN(n_0_383)); + AOI22_X1_LVT i_0_404 (.A1(n_0_467), .A2(n_0_388), .B1(n_0_728), .B2(n_0_383), + .ZN(n_0_382)); + OAI211_X1_LVT i_0_400 (.A(n_0_544), .B(n_0_379), .C1(op2[0]), .C2(n_0_382), + .ZN(n_0_378)); + AOI22_X1_LVT i_0_415 (.A1(op1[14]), .A2(n_0_616), .B1(op1[6]), .B2(n_0_618), + .ZN(n_0_393)); + NOR2_X1_LVT i_0_414 (.A1(n_0_693), .A2(n_0_393), .ZN(n_0_392)); + AOI21_X1_LVT i_0_413 (.A(n_0_392), .B1(n_0_693), .B2(n_0_460), .ZN(n_0_391)); + OAI22_X1_LVT i_0_412 (.A1(n_0_728), .A2(n_0_391), .B1(op2[1]), .B2(n_0_424), + .ZN(n_0_390)); + OAI221_X1_LVT i_0_411 (.A(n_0_620), .B1(op2[0]), .B2(n_0_408), .C1(n_0_701), + .C2(n_0_390), .ZN(n_0_389)); + NAND4_X1_LVT i_0_393 (.A1(n_0_374), .A2(n_0_372), .A3(n_0_378), .A4(n_0_389), + .ZN(result[21])); + OAI221_X1_LVT i_0_388 (.A(op2[20]), .B1(n_0_727), .B2(n_0_567), .C1(op1[20]), + .C2(n_0_564), .ZN(n_0_367)); + NOR2_X1_LVT i_0_691 (.A1(n_0_727), .A2(op2[20]), .ZN(n_0_658)); + AOI22_X1_LVT i_0_387 (.A1(op1[20]), .A2(aluBypass), .B1(n_0_658), .B2(n_0_569), + .ZN(n_0_366)); + AOI22_X1_LVT i_0_386 (.A1(n_52), .A2(n_0_580), .B1(n_20), .B2(n_0_581), + .ZN(n_0_365)); + AOI221_X1_LVT i_0_392 (.A(op2[4]), .B1(n_0_727), .B2(n_0_723), .C1(op2[3]), + .C2(n_0_698), .ZN(n_0_371)); + AOI22_X1_LVT i_0_391 (.A1(op1[24]), .A2(n_0_496), .B1(n_0_693), .B2(n_0_371), + .ZN(n_0_370)); + OAI22_X1_LVT i_0_390 (.A1(op2[1]), .A2(n_0_370), .B1(n_0_728), .B2(n_0_405), + .ZN(n_0_369)); + OAI221_X1_LVT i_0_385 (.A(n_0_576), .B1(n_0_701), .B2(n_0_373), .C1(op2[0]), + .C2(n_0_369), .ZN(n_0_364)); + AND4_X1_LVT i_0_384 (.A1(n_0_367), .A2(n_0_366), .A3(n_0_365), .A4(n_0_364), + .ZN(n_0_363)); + AOI22_X1_LVT i_0_383 (.A1(op1[13]), .A2(n_0_616), .B1(op1[5]), .B2(n_0_618), + .ZN(n_0_362)); + AOI22_X1_LVT i_0_382 (.A1(op2[2]), .A2(n_0_362), .B1(n_0_693), .B2(n_0_443), + .ZN(n_0_361)); + NAND2_X1_LVT i_0_381 (.A1(op2[1]), .A2(n_0_361), .ZN(n_0_360)); + OAI21_X1_LVT i_0_380 (.A(n_0_360), .B1(op2[1]), .B2(n_0_410), .ZN(n_0_359)); + OAI221_X1_LVT i_0_379 (.A(n_0_620), .B1(n_0_701), .B2(n_0_359), .C1(op2[0]), + .C2(n_0_390), .ZN(n_0_358)); + OR2_X1_LVT i_0_389 (.A1(n_0_387), .A2(n_0_369), .ZN(n_0_368)); + AOI22_X1_LVT i_0_378 (.A1(op2[0]), .A2(n_0_382), .B1(n_0_701), .B2(n_0_368), + .ZN(n_0_357)); + OAI211_X1_LVT i_0_377 (.A(n_0_363), .B(n_0_358), .C1(n_0_545), .C2(n_0_357), + .ZN(result[20])); + OAI22_X1_LVT i_0_370 (.A1(op2[3]), .A2(n_0_689), .B1(n_0_723), .B2(n_0_688), + .ZN(n_0_350)); + AND2_X1_LVT i_0_369 (.A1(n_0_738), .A2(n_0_350), .ZN(n_0_349)); + AOI22_X1_LVT i_0_368 (.A1(n_0_498), .A2(n_0_420), .B1(n_0_693), .B2(n_0_349), + .ZN(n_0_348)); + AND2_X1_LVT i_0_367 (.A1(n_0_728), .A2(n_0_348), .ZN(n_0_347)); + AOI21_X1_LVT i_0_359 (.A(n_0_347), .B1(op2[1]), .B2(n_0_385), .ZN(n_0_339)); + OAI221_X1_LVT i_0_357 (.A(n_0_576), .B1(n_0_701), .B2(n_0_369), .C1(op2[0]), + .C2(n_0_339), .ZN(n_0_337)); + NAND2_X1_LVT i_0_363 (.A1(n_19), .A2(n_0_581), .ZN(n_0_343)); + INV_X1_LVT i_0_723 (.A(op2[19]), .ZN(n_0_690)); + AOI221_X1_LVT i_0_364 (.A(n_0_690), .B1(n_0_689), .B2(n_0_565), .C1(op1[19]), + .C2(n_0_566), .ZN(n_0_344)); + AOI221_X1_LVT i_0_361 (.A(n_0_344), .B1(op1[19]), .B2(aluBypass), .C1(n_51), + .C2(n_0_580), .ZN(n_0_341)); + NAND3_X1_LVT i_0_362 (.A1(n_0_690), .A2(op1[19]), .A3(n_0_569), .ZN(n_0_342)); + NAND3_X1_LVT i_0_360 (.A1(n_0_343), .A2(n_0_341), .A3(n_0_342), .ZN(n_0_340)); + AOI22_X1_LVT i_0_376 (.A1(op1[12]), .A2(n_0_616), .B1(op1[4]), .B2(n_0_618), + .ZN(n_0_356)); + OAI22_X1_LVT i_0_375 (.A1(n_0_693), .A2(n_0_356), .B1(op2[2]), .B2(n_0_426), + .ZN(n_0_355)); + INV_X1_LVT i_0_374 (.A(n_0_355), .ZN(n_0_354)); + OAI22_X1_LVT i_0_373 (.A1(op2[1]), .A2(n_0_391), .B1(n_0_728), .B2(n_0_354), + .ZN(n_0_353)); + AOI22_X1_LVT i_0_372 (.A1(n_0_701), .A2(n_0_359), .B1(op2[0]), .B2(n_0_353), + .ZN(n_0_352)); + INV_X1_LVT i_0_371 (.A(n_0_352), .ZN(n_0_351)); + AOI21_X1_LVT i_0_358 (.A(n_0_340), .B1(n_0_620), .B2(n_0_351), .ZN(n_0_338)); + AOI22_X1_LVT i_0_366 (.A1(n_0_468), .A2(n_0_347), .B1(op2[1]), .B2(n_0_383), + .ZN(n_0_346)); + AOI22_X1_LVT i_0_365 (.A1(n_0_701), .A2(n_0_346), .B1(op2[0]), .B2(n_0_368), + .ZN(n_0_345)); + OAI211_X1_LVT i_0_356 (.A(n_0_337), .B(n_0_338), .C1(n_0_545), .C2(n_0_345), + .ZN(result[19])); + NAND2_X1_LVT i_0_342 (.A1(n_50), .A2(n_0_580), .ZN(n_0_323)); + OAI21_X1_LVT i_0_343 (.A(n_0_681), .B1(op2[18]), .B2(n_0_568), .ZN(n_0_324)); + AOI22_X1_LVT i_0_341 (.A1(op1[18]), .A2(n_0_324), .B1(n_18), .B2(n_0_581), + .ZN(n_0_322)); + OAI221_X1_LVT i_0_340 (.A(op2[18]), .B1(n_0_705), .B2(n_0_567), .C1(op1[18]), + .C2(n_0_564), .ZN(n_0_321)); + NAND3_X1_LVT i_0_339 (.A1(n_0_323), .A2(n_0_322), .A3(n_0_321), .ZN(n_0_320)); + OAI22_X1_LVT i_0_351 (.A1(op2[3]), .A2(n_0_705), .B1(n_0_723), .B2(n_0_711), + .ZN(n_0_332)); + AND2_X1_LVT i_0_350 (.A1(n_0_738), .A2(n_0_332), .ZN(n_0_331)); + AOI22_X1_LVT i_0_349 (.A1(n_0_498), .A2(n_0_406), .B1(n_0_693), .B2(n_0_331), + .ZN(n_0_330)); + NAND2_X1_LVT i_0_348 (.A1(n_0_728), .A2(n_0_330), .ZN(n_0_329)); + NAND2_X1_LVT i_0_347 (.A1(op2[1]), .A2(n_0_370), .ZN(n_0_328)); + AND2_X1_LVT i_0_338 (.A1(n_0_329), .A2(n_0_328), .ZN(n_0_319)); + OAI22_X1_LVT i_0_337 (.A1(op2[0]), .A2(n_0_319), .B1(n_0_701), .B2(n_0_339), + .ZN(n_0_318)); + INV_X1_LVT i_0_336 (.A(n_0_318), .ZN(n_0_317)); + AOI21_X1_LVT i_0_335 (.A(n_0_320), .B1(n_0_578), .B2(n_0_317), .ZN(n_0_316)); + OAI22_X1_LVT i_0_346 (.A1(n_0_469), .A2(n_0_329), .B1(n_0_387), .B2(n_0_328), + .ZN(n_0_327)); + NAND2_X1_LVT i_0_344 (.A1(n_0_544), .A2(n_0_346), .ZN(n_0_325)); + NAND2_X1_LVT i_0_354 (.A1(n_0_728), .A2(n_0_361), .ZN(n_0_335)); + AOI22_X1_LVT i_0_355 (.A1(n_0_612), .A2(n_0_498), .B1(n_0_693), .B2(n_0_411), + .ZN(n_0_336)); + OAI21_X1_LVT i_0_353 (.A(n_0_335), .B1(n_0_728), .B2(n_0_336), .ZN(n_0_334)); + AOI22_X1_LVT i_0_352 (.A1(n_0_701), .A2(n_0_353), .B1(op2[0]), .B2(n_0_334), + .ZN(n_0_333)); + OAI221_X1_LVT i_0_334 (.A(n_0_316), .B1(n_0_327), .B2(n_0_325), .C1(n_0_621), + .C2(n_0_333), .ZN(result[18])); + NAND2_X1_LVT i_0_325 (.A1(n_17), .A2(n_0_581), .ZN(n_0_307)); + INV_X1_LVT i_0_765 (.A(op1[17]), .ZN(n_0_732)); + AOI22_X1_LVT i_0_324 (.A1(n_0_732), .A2(n_0_565), .B1(op1[17]), .B2(n_0_566), + .ZN(n_0_306)); + NOR2_X1_LVT i_0_693 (.A1(n_0_732), .A2(op2[17]), .ZN(n_0_660)); + AOI222_X1_LVT i_0_323 (.A1(op2[17]), .A2(n_0_306), .B1(n_0_660), .B2(n_0_569), + .C1(n_49), .C2(n_0_580), .ZN(n_0_305)); + OAI211_X1_LVT i_0_322 (.A(n_0_307), .B(n_0_305), .C1(n_0_732), .C2(n_0_681), + .ZN(n_0_304)); + AOI22_X1_LVT i_0_331 (.A1(op2[3]), .A2(op1[25]), .B1(op1[17]), .B2(n_0_723), + .ZN(n_0_313)); + NOR2_X1_LVT i_0_330 (.A1(op2[4]), .A2(n_0_313), .ZN(n_0_312)); + AOI22_X1_LVT i_0_329 (.A1(n_0_498), .A2(n_0_386), .B1(n_0_693), .B2(n_0_312), + .ZN(n_0_311)); + OAI22_X1_LVT i_0_328 (.A1(op2[1]), .A2(n_0_311), .B1(n_0_728), .B2(n_0_348), + .ZN(n_0_310)); + OR2_X1_LVT i_0_327 (.A1(op2[0]), .A2(n_0_310), .ZN(n_0_309)); + OAI21_X1_LVT i_0_321 (.A(n_0_576), .B1(n_0_701), .B2(n_0_319), .ZN(n_0_303)); + INV_X1_LVT i_0_320 (.A(n_0_303), .ZN(n_0_302)); + AOI21_X1_LVT i_0_319 (.A(n_0_304), .B1(n_0_309), .B2(n_0_302), .ZN(n_0_301)); + INV_X1_LVT i_0_345 (.A(n_0_327), .ZN(n_0_326)); + OAI22_X1_LVT i_0_326 (.A1(n_0_701), .A2(n_0_326), .B1(n_0_469), .B2(n_0_309), + .ZN(n_0_308)); + NOR2_X1_LVT i_0_318 (.A1(op2[2]), .A2(n_0_393), .ZN(n_0_300)); + AOI21_X1_LVT i_0_317 (.A(n_0_300), .B1(n_0_597), .B2(n_0_498), .ZN(n_0_299)); + OAI22_X1_LVT i_0_316 (.A1(n_0_728), .A2(n_0_299), .B1(op2[1]), .B2(n_0_354), + .ZN(n_0_298)); + OAI22_X1_LVT i_0_315 (.A1(op2[0]), .A2(n_0_334), .B1(n_0_701), .B2(n_0_298), + .ZN(n_0_297)); + OAI221_X1_LVT i_0_314 (.A(n_0_301), .B1(n_0_545), .B2(n_0_308), .C1(n_0_621), + .C2(n_0_297), .ZN(result[17])); + AOI22_X1_LVT i_0_301 (.A1(n_48), .A2(n_0_580), .B1(n_16), .B2(n_0_581), + .ZN(n_0_284)); + NAND2_X1_LVT i_0_333 (.A1(n_0_544), .A2(n_0_469), .ZN(n_0_315)); + INV_X1_LVT i_0_332 (.A(n_0_315), .ZN(n_0_314)); + OAI21_X1_LVT i_0_302 (.A(n_0_681), .B1(op2[16]), .B2(n_0_568), .ZN(n_0_285)); + AOI21_X1_LVT i_0_300 (.A(n_0_314), .B1(op1[16]), .B2(n_0_285), .ZN(n_0_283)); + INV_X1_LVT i_0_772 (.A(op1[16]), .ZN(n_0_739)); + OAI221_X1_LVT i_0_303 (.A(op2[16]), .B1(op1[16]), .B2(n_0_564), .C1(n_0_739), + .C2(n_0_567), .ZN(n_0_286)); + NAND3_X1_LVT i_0_299 (.A1(n_0_284), .A2(n_0_283), .A3(n_0_286), .ZN(n_0_282)); + INV_X1_LVT i_0_593 (.A(n_0_562), .ZN(n_0_561)); + OAI22_X1_LVT i_0_307 (.A1(op1[16]), .A2(op2[3]), .B1(op1[24]), .B2(n_0_723), + .ZN(n_0_290)); + NOR2_X1_LVT i_0_306 (.A1(op2[4]), .A2(n_0_290), .ZN(n_0_289)); + AOI22_X1_LVT i_0_305 (.A1(n_0_693), .A2(n_0_289), .B1(op2[2]), .B2(n_0_371), + .ZN(n_0_288)); + OAI22_X1_LVT i_0_304 (.A1(n_0_728), .A2(n_0_330), .B1(op2[1]), .B2(n_0_288), + .ZN(n_0_287)); + AOI221_X1_LVT i_0_298 (.A(n_0_282), .B1(n_0_547), .B2(n_0_310), .C1(n_0_561), + .C2(n_0_287), .ZN(n_0_281)); + INV_X1_LVT i_0_762 (.A(op1[1]), .ZN(n_0_729)); + OAI22_X1_LVT i_0_313 (.A1(n_0_722), .A2(n_0_615), .B1(n_0_729), .B2(n_0_617), + .ZN(n_0_296)); + NAND2_X1_LVT i_0_312 (.A1(op2[2]), .A2(n_0_296), .ZN(n_0_295)); + OAI21_X1_LVT i_0_311 (.A(n_0_295), .B1(op2[2]), .B2(n_0_362), .ZN(n_0_294)); + NAND2_X1_LVT i_0_310 (.A1(op2[1]), .A2(n_0_294), .ZN(n_0_293)); + OAI21_X1_LVT i_0_309 (.A(n_0_293), .B1(op2[1]), .B2(n_0_336), .ZN(n_0_292)); + OAI22_X1_LVT i_0_308 (.A1(op2[0]), .A2(n_0_298), .B1(n_0_701), .B2(n_0_292), + .ZN(n_0_291)); + OAI21_X1_LVT i_0_297 (.A(n_0_281), .B1(n_0_621), .B2(n_0_291), .ZN(result[16])); + OAI221_X1_LVT i_0_286 (.A(op2[15]), .B1(n_0_734), .B2(n_0_567), .C1(op1[15]), + .C2(n_0_564), .ZN(n_0_270)); + AOI21_X1_LVT i_0_288 (.A(n_0_314), .B1(n_15), .B2(n_0_581), .ZN(n_0_272)); + INV_X1_LVT i_0_287 (.A(n_0_272), .ZN(n_0_271)); + OAI21_X1_LVT i_0_285 (.A(n_0_681), .B1(op2[15]), .B2(n_0_568), .ZN(n_0_269)); + AOI221_X1_LVT i_0_284 (.A(n_0_271), .B1(n_47), .B2(n_0_580), .C1(op1[15]), + .C2(n_0_269), .ZN(n_0_268)); + AOI22_X1_LVT i_0_296 (.A1(op1[8]), .A2(n_0_616), .B1(op1[0]), .B2(n_0_618), + .ZN(n_0_280)); + AOI22_X1_LVT i_0_295 (.A1(op2[2]), .A2(n_0_280), .B1(n_0_693), .B2(n_0_356), + .ZN(n_0_279)); + NAND2_X1_LVT i_0_294 (.A1(op2[1]), .A2(n_0_279), .ZN(n_0_278)); + OAI21_X1_LVT i_0_293 (.A(n_0_278), .B1(op2[1]), .B2(n_0_299), .ZN(n_0_277)); + OAI221_X1_LVT i_0_292 (.A(n_0_620), .B1(n_0_701), .B2(n_0_277), .C1(op2[0]), + .C2(n_0_292), .ZN(n_0_276)); + OAI222_X1_LVT i_0_291 (.A1(n_0_719), .A2(n_0_617), .B1(n_0_691), .B2(n_0_605), + .C1(n_0_734), .C2(n_0_615), .ZN(n_0_275)); + OAI22_X1_LVT i_0_290 (.A1(n_0_693), .A2(n_0_349), .B1(op2[2]), .B2(n_0_275), + .ZN(n_0_274)); + OAI22_X1_LVT i_0_289 (.A1(op2[1]), .A2(n_0_274), .B1(n_0_728), .B2(n_0_311), + .ZN(n_0_273)); + AOI22_X1_LVT i_0_283 (.A1(n_0_561), .A2(n_0_273), .B1(n_0_547), .B2(n_0_287), + .ZN(n_0_267)); + NAND4_X1_LVT i_0_282 (.A1(n_0_270), .A2(n_0_268), .A3(n_0_276), .A4(n_0_267), + .ZN(result[15])); + NOR2_X1_LVT i_0_278 (.A1(op2[0]), .A2(n_0_277), .ZN(n_0_263)); + NAND2_X1_LVT i_0_281 (.A1(n_0_612), .A2(n_0_575), .ZN(n_0_266)); + OAI21_X1_LVT i_0_280 (.A(n_0_266), .B1(n_0_713), .B2(n_0_497), .ZN(n_0_265)); + AOI22_X1_LVT i_0_279 (.A1(op2[1]), .A2(n_0_265), .B1(n_0_728), .B2(n_0_294), + .ZN(n_0_264)); + AOI211_X1_LVT i_0_277 (.A(n_0_263), .B(n_0_621), .C1(op2[0]), .C2(n_0_264), + .ZN(n_0_262)); + INV_X1_LVT i_0_754 (.A(op1[14]), .ZN(n_0_721)); + OAI21_X1_LVT i_0_273 (.A(op2[14]), .B1(n_0_721), .B2(n_0_567), .ZN(n_0_258)); + AOI21_X1_LVT i_0_272 (.A(n_0_258), .B1(n_0_721), .B2(n_0_565), .ZN(n_0_257)); + OAI21_X1_LVT i_0_276 (.A(n_0_681), .B1(op2[14]), .B2(n_0_568), .ZN(n_0_261)); + AOI222_X1_LVT i_0_275 (.A1(n_14), .A2(n_0_581), .B1(n_46), .B2(n_0_580), + .C1(op1[14]), .C2(n_0_261), .ZN(n_0_260)); + INV_X1_LVT i_0_274 (.A(n_0_260), .ZN(n_0_259)); + OAI222_X1_LVT i_0_271 (.A1(n_0_717), .A2(n_0_605), .B1(n_0_687), .B2(n_0_617), + .C1(n_0_721), .C2(n_0_615), .ZN(n_0_256)); + OAI22_X1_LVT i_0_270 (.A1(n_0_693), .A2(n_0_331), .B1(op2[2]), .B2(n_0_256), + .ZN(n_0_255)); + AND2_X1_LVT i_0_269 (.A1(n_0_728), .A2(n_0_255), .ZN(n_0_254)); + NOR3_X1_LVT i_0_265 (.A1(op2[3]), .A2(op2[2]), .A3(op2[0]), .ZN(n_0_250)); + AOI21_X1_LVT i_0_268 (.A(n_0_254), .B1(op2[1]), .B2(n_0_288), .ZN(n_0_253)); + OAI22_X1_LVT i_0_266 (.A1(op2[0]), .A2(n_0_253), .B1(n_0_701), .B2(n_0_273), + .ZN(n_0_251)); + AOI221_X1_LVT i_0_259 (.A(n_0_579), .B1(n_0_254), .B2(n_0_250), .C1(n_0_315), + .C2(n_0_251), .ZN(n_0_244)); + OR4_X1_LVT i_0_258 (.A1(n_0_262), .A2(n_0_257), .A3(n_0_259), .A4(n_0_244), + .ZN(result[14])); + OAI221_X1_LVT i_0_245 (.A(op2[13]), .B1(op1[13]), .B2(n_0_564), .C1(n_0_714), + .C2(n_0_567), .ZN(n_0_231)); + NAND2_X1_LVT i_0_244 (.A1(n_13), .A2(n_0_581), .ZN(n_0_230)); + OAI211_X1_LVT i_0_243 (.A(n_0_231), .B(n_0_230), .C1(n_0_714), .C2(n_0_681), + .ZN(n_0_229)); + NOR2_X1_LVT i_0_695 (.A1(op2[13]), .A2(n_0_714), .ZN(n_0_662)); + AOI221_X1_LVT i_0_242 (.A(n_0_229), .B1(n_45), .B2(n_0_580), .C1(n_0_662), + .C2(n_0_569), .ZN(n_0_228)); + INV_X1_LVT i_0_267 (.A(n_0_253), .ZN(n_0_252)); + OAI222_X1_LVT i_0_257 (.A1(n_0_714), .A2(n_0_615), .B1(n_0_726), .B2(n_0_617), + .C1(n_0_710), .C2(n_0_605), .ZN(n_0_243)); + OAI22_X1_LVT i_0_256 (.A1(n_0_693), .A2(n_0_312), .B1(op2[2]), .B2(n_0_243), + .ZN(n_0_242)); + NAND2_X1_LVT i_0_255 (.A1(n_0_728), .A2(n_0_242), .ZN(n_0_241)); + NAND2_X1_LVT i_0_254 (.A1(op2[1]), .A2(n_0_274), .ZN(n_0_240)); + NAND2_X1_LVT i_0_241 (.A1(n_0_241), .A2(n_0_240), .ZN(n_0_227)); + OAI221_X1_LVT i_0_240 (.A(n_0_228), .B1(n_0_548), .B2(n_0_252), .C1(n_0_562), + .C2(n_0_227), .ZN(n_0_226)); + NAND2_X1_LVT i_0_249 (.A1(n_0_728), .A2(n_0_279), .ZN(n_0_235)); + AOI22_X1_LVT i_0_250 (.A1(n_0_597), .A2(n_0_575), .B1(op1[6]), .B2(n_0_496), + .ZN(n_0_236)); + OAI21_X1_LVT i_0_248 (.A(n_0_235), .B1(n_0_728), .B2(n_0_236), .ZN(n_0_234)); + INV_X1_LVT i_0_247 (.A(n_0_234), .ZN(n_0_233)); + AOI221_X1_LVT i_0_246 (.A(n_0_621), .B1(op2[0]), .B2(n_0_233), .C1(n_0_701), + .C2(n_0_264), .ZN(n_0_232)); + NAND2_X1_LVT i_0_264 (.A1(op2[3]), .A2(n_0_469), .ZN(n_0_249)); + AOI21_X1_LVT i_0_262 (.A(n_0_468), .B1(n_0_693), .B2(n_0_249), .ZN(n_0_247)); + INV_X1_LVT i_0_261 (.A(n_0_247), .ZN(n_0_246)); + OAI211_X1_LVT i_0_260 (.A(n_0_252), .B(n_0_246), .C1(n_0_468), .C2(n_0_254), + .ZN(n_0_245)); + OAI221_X1_LVT i_0_253 (.A(n_0_544), .B1(n_0_247), .B2(n_0_241), .C1(n_0_469), + .C2(n_0_240), .ZN(n_0_239)); + INV_X1_LVT i_0_252 (.A(n_0_239), .ZN(n_0_238)); + AOI211_X1_LVT i_0_239 (.A(n_0_226), .B(n_0_232), .C1(n_0_245), .C2(n_0_238), + .ZN(n_0_225)); + INV_X1_LVT i_0_238 (.A(n_0_225), .ZN(result[13])); + OAI221_X1_LVT i_0_232 (.A(op2[12]), .B1(n_0_696), .B2(n_0_567), .C1(op1[12]), + .C2(n_0_564), .ZN(n_0_219)); + OAI21_X1_LVT i_0_231 (.A(n_0_681), .B1(op2[12]), .B2(n_0_568), .ZN(n_0_218)); + AOI222_X1_LVT i_0_230 (.A1(n_12), .A2(n_0_581), .B1(op1[12]), .B2(n_0_218), + .C1(n_44), .C2(n_0_580), .ZN(n_0_217)); + OAI21_X1_LVT i_0_234 (.A(n_0_620), .B1(op2[1]), .B2(n_0_265), .ZN(n_0_221)); + INV_X1_LVT i_0_763 (.A(op1[5]), .ZN(n_0_730)); + OAI21_X1_LVT i_0_236 (.A(op2[2]), .B1(n_0_730), .B2(n_0_615), .ZN(n_0_223)); + OAI21_X1_LVT i_0_235 (.A(n_0_223), .B1(op2[2]), .B2(n_0_296), .ZN(n_0_222)); + AOI21_X1_LVT i_0_233 (.A(n_0_221), .B1(op2[1]), .B2(n_0_222), .ZN(n_0_220)); + NOR2_X1_LVT i_0_237 (.A1(n_0_577), .A2(n_0_227), .ZN(n_0_224)); + NOR4_X1_LVT i_0_223 (.A1(n_0_701), .A2(n_0_220), .A3(n_0_224), .A4(n_0_238), + .ZN(n_0_210)); + NAND2_X1_LVT i_0_224 (.A1(n_0_544), .A2(n_0_247), .ZN(n_0_211)); + NAND2_X1_LVT i_0_222 (.A1(n_0_701), .A2(n_0_211), .ZN(n_0_209)); + OAI22_X1_LVT i_0_229 (.A1(op2[4]), .A2(n_0_696), .B1(n_0_738), .B2(n_0_698), + .ZN(n_0_216)); + INV_X1_LVT i_0_228 (.A(n_0_216), .ZN(n_0_215)); + OAI22_X1_LVT i_0_227 (.A1(n_0_727), .A2(n_0_617), .B1(op2[3]), .B2(n_0_215), + .ZN(n_0_214)); + OAI22_X1_LVT i_0_226 (.A1(n_0_693), .A2(n_0_289), .B1(op2[2]), .B2(n_0_214), + .ZN(n_0_213)); + OAI22_X1_LVT i_0_225 (.A1(op2[1]), .A2(n_0_213), .B1(n_0_728), .B2(n_0_255), + .ZN(n_0_212)); + AOI221_X1_LVT i_0_221 (.A(n_0_209), .B1(n_0_578), .B2(n_0_212), .C1(n_0_620), + .C2(n_0_234), .ZN(n_0_208)); + OAI211_X1_LVT i_0_220 (.A(n_0_219), .B(n_0_217), .C1(n_0_210), .C2(n_0_208), + .ZN(result[12])); + OAI21_X1_LVT i_0_209 (.A(n_0_681), .B1(op2[11]), .B2(n_0_568), .ZN(n_0_197)); + AOI22_X1_LVT i_0_208 (.A1(n_11), .A2(n_0_581), .B1(op1[11]), .B2(n_0_197), + .ZN(n_0_196)); + NAND2_X1_LVT i_0_207 (.A1(n_0_211), .A2(n_0_196), .ZN(n_0_195)); + AOI22_X1_LVT i_0_210 (.A1(op1[11]), .A2(n_0_566), .B1(n_0_706), .B2(n_0_565), + .ZN(n_0_198)); + AOI221_X1_LVT i_0_206 (.A(n_0_195), .B1(op2[11]), .B2(n_0_198), .C1(n_43), + .C2(n_0_580), .ZN(n_0_194)); + AOI221_X1_LVT i_0_215 (.A(op2[3]), .B1(n_0_738), .B2(n_0_706), .C1(op2[4]), + .C2(n_0_688), .ZN(n_0_203)); + AOI21_X1_LVT i_0_214 (.A(n_0_203), .B1(op1[19]), .B2(n_0_618), .ZN(n_0_202)); + NAND2_X1_LVT i_0_213 (.A1(n_0_693), .A2(n_0_202), .ZN(n_0_201)); + OAI21_X1_LVT i_0_212 (.A(n_0_201), .B1(n_0_693), .B2(n_0_275), .ZN(n_0_200)); + OAI22_X1_LVT i_0_211 (.A1(n_0_728), .A2(n_0_242), .B1(op2[1]), .B2(n_0_200), + .ZN(n_0_199)); + AOI22_X1_LVT i_0_205 (.A1(n_0_561), .A2(n_0_199), .B1(n_0_701), .B2(n_0_220), + .ZN(n_0_193)); + NOR2_X1_LVT i_0_219 (.A1(op2[2]), .A2(n_0_280), .ZN(n_0_207)); + AOI21_X1_LVT i_0_218 (.A(n_0_207), .B1(op1[4]), .B2(n_0_496), .ZN(n_0_206)); + AOI22_X1_LVT i_0_217 (.A1(n_0_728), .A2(n_0_236), .B1(op2[1]), .B2(n_0_206), + .ZN(n_0_205)); + AOI22_X1_LVT i_0_216 (.A1(n_0_578), .A2(n_0_212), .B1(n_0_620), .B2(n_0_205), + .ZN(n_0_204)); + OAI211_X1_LVT i_0_204 (.A(n_0_194), .B(n_0_193), .C1(n_0_701), .C2(n_0_204), + .ZN(result[11])); + AOI22_X1_LVT i_0_194 (.A1(n_0_654), .A2(n_0_498), .B1(op1[7]), .B2(n_0_573), + .ZN(n_0_183)); + OAI22_X1_LVT i_0_193 (.A1(n_0_728), .A2(n_0_183), .B1(op2[1]), .B2(n_0_222), + .ZN(n_0_182)); + AOI22_X1_LVT i_0_192 (.A1(op2[0]), .A2(n_0_182), .B1(n_0_701), .B2(n_0_205), + .ZN(n_0_181)); + NOR2_X1_LVT i_0_191 (.A1(n_0_621), .A2(n_0_181), .ZN(n_0_180)); + AOI22_X1_LVT i_0_190 (.A1(op1[10]), .A2(n_0_566), .B1(n_0_733), .B2(n_0_565), + .ZN(n_0_179)); + AOI22_X1_LVT i_0_188 (.A1(op2[10]), .A2(n_0_179), .B1(n_42), .B2(n_0_580), + .ZN(n_0_177)); + OAI21_X1_LVT i_0_189 (.A(n_0_681), .B1(op2[10]), .B2(n_0_568), .ZN(n_0_178)); + AOI22_X1_LVT i_0_187 (.A1(n_10), .A2(n_0_581), .B1(op1[10]), .B2(n_0_178), + .ZN(n_0_176)); + NAND2_X1_LVT i_0_186 (.A1(n_0_177), .A2(n_0_176), .ZN(n_0_175)); + NOR2_X1_LVT i_0_203 (.A1(n_0_701), .A2(n_0_199), .ZN(n_0_192)); + NOR2_X1_LVT i_0_200 (.A1(n_0_693), .A2(n_0_256), .ZN(n_0_189)); + AOI221_X1_LVT i_0_202 (.A(n_0_596), .B1(op1[10]), .B2(n_0_616), .C1(op1[26]), + .C2(n_0_606), .ZN(n_0_191)); + AOI21_X1_LVT i_0_199 (.A(n_0_189), .B1(n_0_693), .B2(n_0_191), .ZN(n_0_188)); + OR2_X1_LVT i_0_198 (.A1(op2[1]), .A2(n_0_188), .ZN(n_0_187)); + NAND2_X1_LVT i_0_197 (.A1(op2[1]), .A2(n_0_213), .ZN(n_0_186)); + NAND2_X1_LVT i_0_185 (.A1(n_0_187), .A2(n_0_186), .ZN(n_0_174)); + AOI211_X1_LVT i_0_184 (.A(n_0_577), .B(n_0_192), .C1(n_0_701), .C2(n_0_174), + .ZN(n_0_173)); + INV_X1_LVT i_0_263 (.A(n_0_249), .ZN(n_0_248)); + OAI22_X1_LVT i_0_196 (.A1(n_0_248), .A2(n_0_187), .B1(n_0_247), .B2(n_0_186), + .ZN(n_0_185)); + AOI221_X1_LVT i_0_195 (.A(n_0_545), .B1(n_0_246), .B2(n_0_192), .C1(n_0_701), + .C2(n_0_185), .ZN(n_0_184)); + OR4_X1_LVT i_0_183 (.A1(n_0_180), .A2(n_0_175), .A3(n_0_173), .A4(n_0_184), + .ZN(result[10])); + INV_X1_LVT i_0_753 (.A(op2[9]), .ZN(n_0_720)); + AOI221_X1_LVT i_0_171 (.A(n_0_720), .B1(op1[9]), .B2(n_0_566), .C1(n_0_722), + .C2(n_0_565), .ZN(n_0_161)); + AOI22_X1_LVT i_0_172 (.A1(n_9), .A2(n_0_581), .B1(n_41), .B2(n_0_580), + .ZN(n_0_162)); + AOI21_X1_LVT i_0_170 (.A(aluBypass), .B1(n_0_720), .B2(n_0_569), .ZN(n_0_160)); + OAI21_X1_LVT i_0_169 (.A(n_0_162), .B1(n_0_722), .B2(n_0_160), .ZN(n_0_159)); + OAI222_X1_LVT i_0_182 (.A1(n_0_722), .A2(n_0_615), .B1(n_0_699), .B2(n_0_605), + .C1(n_0_732), .C2(n_0_617), .ZN(n_0_172)); + AOI22_X1_LVT i_0_181 (.A1(n_0_693), .A2(n_0_172), .B1(op2[2]), .B2(n_0_243), + .ZN(n_0_171)); + NAND2_X1_LVT i_0_180 (.A1(n_0_728), .A2(n_0_171), .ZN(n_0_170)); + NAND2_X1_LVT i_0_179 (.A1(op2[1]), .A2(n_0_200), .ZN(n_0_169)); + OAI22_X1_LVT i_0_178 (.A1(n_0_248), .A2(n_0_170), .B1(n_0_247), .B2(n_0_169), + .ZN(n_0_168)); + NOR3_X1_LVT i_0_177 (.A1(n_0_545), .A2(n_0_168), .A3(n_0_185), .ZN(n_0_167)); + NOR2_X1_LVT i_0_251 (.A1(n_0_704), .A2(n_0_615), .ZN(n_0_237)); + OAI22_X1_LVT i_0_176 (.A1(op1[2]), .A2(n_0_693), .B1(n_0_496), .B2(n_0_237), + .ZN(n_0_166)); + OAI22_X1_LVT i_0_175 (.A1(op2[1]), .A2(n_0_206), .B1(n_0_728), .B2(n_0_166), + .ZN(n_0_165)); + OAI221_X1_LVT i_0_174 (.A(n_0_620), .B1(op2[0]), .B2(n_0_182), .C1(n_0_701), + .C2(n_0_165), .ZN(n_0_164)); + NAND2_X1_LVT i_0_173 (.A1(n_0_170), .A2(n_0_169), .ZN(n_0_163)); + OAI221_X1_LVT i_0_168 (.A(n_0_164), .B1(n_0_562), .B2(n_0_163), .C1(n_0_548), + .C2(n_0_174), .ZN(n_0_158)); + OR4_X1_LVT i_0_167 (.A1(n_0_161), .A2(n_0_159), .A3(n_0_167), .A4(n_0_158), + .ZN(result[9])); + OAI21_X1_LVT i_0_160 (.A(n_0_693), .B1(n_0_730), .B2(n_0_615), .ZN(n_0_151)); + OAI21_X1_LVT i_0_159 (.A(op2[2]), .B1(n_0_729), .B2(n_0_615), .ZN(n_0_150)); + AND2_X1_LVT i_0_158 (.A1(n_0_151), .A2(n_0_150), .ZN(n_0_149)); + NAND2_X1_LVT i_0_157 (.A1(op2[1]), .A2(n_0_149), .ZN(n_0_148)); + OAI21_X1_LVT i_0_156 (.A(n_0_148), .B1(op2[1]), .B2(n_0_183), .ZN(n_0_147)); + OAI22_X1_LVT i_0_155 (.A1(op2[0]), .A2(n_0_165), .B1(n_0_701), .B2(n_0_147), + .ZN(n_0_146)); + NOR2_X1_LVT i_0_154 (.A1(n_0_621), .A2(n_0_146), .ZN(n_0_145)); + INV_X1_LVT i_0_773 (.A(op1[8]), .ZN(n_0_740)); + NOR2_X1_LVT i_0_688 (.A1(n_0_740), .A2(op2[8]), .ZN(n_0_655)); + AOI22_X1_LVT i_0_153 (.A1(op1[8]), .A2(aluBypass), .B1(n_0_655), .B2(n_0_569), + .ZN(n_0_144)); + OAI221_X1_LVT i_0_152 (.A(op2[8]), .B1(op1[8]), .B2(n_0_564), .C1(n_0_740), + .C2(n_0_567), .ZN(n_0_143)); + AOI22_X1_LVT i_0_151 (.A1(n_40), .A2(n_0_580), .B1(n_8), .B2(n_0_581), + .ZN(n_0_142)); + NAND3_X1_LVT i_0_150 (.A1(n_0_144), .A2(n_0_143), .A3(n_0_142), .ZN(n_0_141)); + OAI222_X1_LVT i_0_166 (.A1(n_0_740), .A2(n_0_615), .B1(n_0_739), .B2(n_0_617), + .C1(n_0_736), .C2(n_0_605), .ZN(n_0_157)); + OAI22_X1_LVT i_0_165 (.A1(op2[2]), .A2(n_0_157), .B1(n_0_693), .B2(n_0_214), + .ZN(n_0_156)); + NOR2_X1_LVT i_0_164 (.A1(op2[1]), .A2(n_0_156), .ZN(n_0_155)); + AOI21_X1_LVT i_0_163 (.A(n_0_155), .B1(op2[1]), .B2(n_0_188), .ZN(n_0_154)); + AND2_X1_LVT i_0_162 (.A1(n_0_701), .A2(n_0_154), .ZN(n_0_153)); + AOI211_X1_LVT i_0_149 (.A(n_0_577), .B(n_0_153), .C1(op2[0]), .C2(n_0_163), + .ZN(n_0_140)); + AOI221_X1_LVT i_0_161 (.A(n_0_545), .B1(op2[0]), .B2(n_0_168), .C1(n_0_249), + .C2(n_0_153), .ZN(n_0_152)); + OR4_X1_LVT i_0_148 (.A1(n_0_145), .A2(n_0_141), .A3(n_0_140), .A4(n_0_152), + .ZN(result[8])); + AOI22_X1_LVT i_0_138 (.A1(op1[4]), .A2(n_0_573), .B1(op1[0]), .B2(n_0_496), + .ZN(n_0_130)); + AOI22_X1_LVT i_0_137 (.A1(op2[1]), .A2(n_0_130), .B1(n_0_728), .B2(n_0_166), + .ZN(n_0_129)); + OAI22_X1_LVT i_0_136 (.A1(n_0_701), .A2(n_0_129), .B1(op2[0]), .B2(n_0_147), + .ZN(n_0_128)); + NOR2_X1_LVT i_0_135 (.A1(n_0_621), .A2(n_0_128), .ZN(n_0_127)); + OAI221_X1_LVT i_0_139 (.A(op2[7]), .B1(n_0_713), .B2(n_0_567), .C1(op1[7]), + .C2(n_0_564), .ZN(n_0_131)); + AOI22_X1_LVT i_0_141 (.A1(n_7), .A2(n_0_581), .B1(n_39), .B2(n_0_580), + .ZN(n_0_133)); + INV_X1_LVT i_0_745 (.A(op2[7]), .ZN(n_0_712)); + AOI21_X1_LVT i_0_140 (.A(aluBypass), .B1(n_0_712), .B2(n_0_569), .ZN(n_0_132)); + OAI211_X1_LVT i_0_133 (.A(n_0_131), .B(n_0_133), .C1(n_0_713), .C2(n_0_132), + .ZN(n_0_125)); + OAI22_X1_LVT i_0_147 (.A1(n_0_734), .A2(n_0_617), .B1(n_0_713), .B2(n_0_615), + .ZN(n_0_139)); + AOI211_X1_LVT i_0_146 (.A(n_0_139), .B(n_0_248), .C1(op1[23]), .C2(n_0_606), + .ZN(n_0_138)); + OAI22_X1_LVT i_0_145 (.A1(n_0_693), .A2(n_0_202), .B1(op2[2]), .B2(n_0_138), + .ZN(n_0_137)); + NOR2_X1_LVT i_0_144 (.A1(op2[1]), .A2(n_0_137), .ZN(n_0_136)); + AOI21_X1_LVT i_0_143 (.A(n_0_136), .B1(op2[1]), .B2(n_0_171), .ZN(n_0_135)); + NAND2_X1_LVT i_0_142 (.A1(n_0_561), .A2(n_0_135), .ZN(n_0_134)); + OAI221_X1_LVT i_0_134 (.A(n_0_134), .B1(n_0_548), .B2(n_0_154), .C1(n_0_545), + .C2(n_0_249), .ZN(n_0_126)); + OR3_X1_LVT i_0_132 (.A1(n_0_127), .A2(n_0_125), .A3(n_0_126), .ZN(result[7])); + NAND2_X1_LVT i_0_124 (.A1(n_0_728), .A2(n_0_149), .ZN(n_0_117)); + OAI21_X1_LVT i_0_123 (.A(n_0_117), .B1(n_0_724), .B2(n_0_531), .ZN(n_0_116)); + OAI22_X1_LVT i_0_122 (.A1(n_0_701), .A2(n_0_116), .B1(op2[0]), .B2(n_0_129), + .ZN(n_0_115)); + NOR2_X1_LVT i_0_121 (.A1(n_0_621), .A2(n_0_115), .ZN(n_0_114)); + AOI22_X1_LVT i_0_119 (.A1(n_6), .A2(n_0_581), .B1(n_38), .B2(n_0_580), + .ZN(n_0_112)); + INV_X1_LVT i_0_735 (.A(op2[6]), .ZN(n_0_702)); + AOI21_X1_LVT i_0_120 (.A(aluBypass), .B1(n_0_702), .B2(n_0_569), .ZN(n_0_113)); + OAI21_X1_LVT i_0_118 (.A(n_0_112), .B1(n_0_704), .B2(n_0_113), .ZN(n_0_111)); + AOI221_X1_LVT i_0_117 (.A(n_0_702), .B1(n_0_704), .B2(n_0_565), .C1(op1[6]), + .C2(n_0_566), .ZN(n_0_110)); + NOR3_X1_LVT i_0_116 (.A1(n_0_114), .A2(n_0_111), .A3(n_0_110), .ZN(n_0_109)); + AOI221_X1_LVT i_0_131 (.A(n_0_237), .B1(op1[14]), .B2(n_0_618), .C1(op2[4]), + .C2(n_0_406), .ZN(n_0_124)); + NAND2_X1_LVT i_0_130 (.A1(n_0_693), .A2(n_0_124), .ZN(n_0_123)); + INV_X1_LVT i_0_201 (.A(n_0_191), .ZN(n_0_190)); + OAI21_X1_LVT i_0_129 (.A(n_0_123), .B1(n_0_693), .B2(n_0_190), .ZN(n_0_122)); + AOI22_X1_LVT i_0_128 (.A1(n_0_728), .A2(n_0_122), .B1(op2[1]), .B2(n_0_156), + .ZN(n_0_121)); + INV_X1_LVT i_0_127 (.A(n_0_121), .ZN(n_0_120)); + OAI21_X1_LVT i_0_126 (.A(n_0_248), .B1(op2[1]), .B2(n_0_123), .ZN(n_0_119)); + AND2_X1_LVT i_0_125 (.A1(n_0_120), .A2(n_0_119), .ZN(n_0_118)); + NOR2_X1_LVT i_0_115 (.A1(n_0_545), .A2(n_0_118), .ZN(n_0_108)); + AOI21_X1_LVT i_0_114 (.A(n_0_108), .B1(n_0_576), .B2(n_0_121), .ZN(n_0_107)); + AOI22_X1_LVT i_0_113 (.A1(n_0_544), .A2(n_0_248), .B1(n_0_578), .B2(n_0_135), + .ZN(n_0_106)); + OAI221_X1_LVT i_0_112 (.A(n_0_109), .B1(op2[0]), .B2(n_0_107), .C1(n_0_701), + .C2(n_0_106), .ZN(result[6])); + OAI221_X1_LVT i_0_100 (.A(op2[5]), .B1(op1[5]), .B2(n_0_564), .C1(n_0_730), + .C2(n_0_567), .ZN(n_0_94)); + INV_X1_LVT i_0_764 (.A(op2[5]), .ZN(n_0_731)); + AOI21_X1_LVT i_0_99 (.A(aluBypass), .B1(n_0_731), .B2(n_0_569), .ZN(n_0_93)); + NOR2_X1_LVT i_0_98 (.A1(n_0_730), .A2(n_0_93), .ZN(n_0_92)); + AOI221_X1_LVT i_0_97 (.A(n_0_92), .B1(n_37), .B2(n_0_580), .C1(n_5), .C2( + n_0_581), .ZN(n_0_91)); + OAI22_X1_LVT i_0_102 (.A1(n_0_694), .A2(n_0_531), .B1(op2[1]), .B2(n_0_130), + .ZN(n_0_96)); + OAI221_X1_LVT i_0_101 (.A(n_0_620), .B1(n_0_701), .B2(n_0_96), .C1(op2[0]), + .C2(n_0_116), .ZN(n_0_95)); + NAND3_X1_LVT i_0_111 (.A1(n_0_544), .A2(n_0_248), .A3(op2[2]), .ZN(n_0_105)); + NAND2_X1_LVT i_0_110 (.A1(op2[4]), .A2(n_0_386), .ZN(n_0_104)); + OAI21_X1_LVT i_0_109 (.A(n_0_104), .B1(n_0_714), .B2(n_0_617), .ZN(n_0_103)); + OAI22_X1_LVT i_0_108 (.A1(n_0_151), .A2(n_0_103), .B1(n_0_693), .B2(n_0_172), + .ZN(n_0_102)); + NOR2_X1_LVT i_0_107 (.A1(op2[1]), .A2(n_0_102), .ZN(n_0_101)); + AOI21_X1_LVT i_0_106 (.A(n_0_101), .B1(op2[1]), .B2(n_0_137), .ZN(n_0_100)); + OAI21_X1_LVT i_0_105 (.A(n_0_105), .B1(n_0_579), .B2(n_0_100), .ZN(n_0_99)); + AOI21_X1_LVT i_0_104 (.A(n_0_118), .B1(n_0_682), .B2(n_0_120), .ZN(n_0_98)); + OAI22_X1_LVT i_0_103 (.A1(n_0_547), .A2(n_0_99), .B1(n_0_701), .B2(n_0_98), + .ZN(n_0_97)); + NAND4_X1_LVT i_0_96 (.A1(n_0_94), .A2(n_0_91), .A3(n_0_95), .A4(n_0_97), + .ZN(result[5])); + AOI222_X1_LVT i_0_89 (.A1(n_4), .A2(n_0_581), .B1(n_36), .B2(n_0_580), + .C1(n_0_668), .C2(n_0_564), .ZN(n_0_84)); + INV_X1_LVT i_0_770 (.A(op1[4]), .ZN(n_0_737)); + AOI221_X1_LVT i_0_90 (.A(aluBypass), .B1(op2[4]), .B2(n_0_567), .C1(n_0_738), + .C2(n_0_569), .ZN(n_0_85)); + OAI21_X1_LVT i_0_88 (.A(n_0_84), .B1(n_0_737), .B2(n_0_85), .ZN(n_0_83)); + NOR2_X1_LVT i_0_689 (.A1(op2[4]), .A2(n_0_737), .ZN(n_0_656)); + AOI21_X1_LVT i_0_95 (.A(n_0_616), .B1(n_0_727), .B2(n_0_723), .ZN(n_0_90)); + OAI22_X1_LVT i_0_94 (.A1(n_0_723), .A2(n_0_216), .B1(n_0_656), .B2(n_0_90), + .ZN(n_0_89)); + INV_X1_LVT i_0_93 (.A(n_0_89), .ZN(n_0_88)); + OAI22_X1_LVT i_0_92 (.A1(op2[2]), .A2(n_0_88), .B1(n_0_693), .B2(n_0_157), + .ZN(n_0_87)); + OAI221_X1_LVT i_0_91 (.A(n_0_105), .B1(n_0_728), .B2(n_0_122), .C1(op2[1]), + .C2(n_0_87), .ZN(n_0_86)); + AOI221_X1_LVT i_0_85 (.A(n_0_83), .B1(n_0_561), .B2(n_0_86), .C1(op2[0]), + .C2(n_0_99), .ZN(n_0_80)); + AOI221_X1_LVT i_0_87 (.A(n_0_574), .B1(n_0_729), .B2(op2[1]), .C1(n_0_728), + .C2(n_0_724), .ZN(n_0_82)); + OAI22_X1_LVT i_0_86 (.A1(op2[0]), .A2(n_0_96), .B1(n_0_701), .B2(n_0_82), + .ZN(n_0_81)); + OAI21_X1_LVT i_0_84 (.A(n_0_80), .B1(n_0_621), .B2(n_0_81), .ZN(result[4])); + AND2_X1_LVT i_0_81 (.A1(op2[1]), .A2(n_0_105), .ZN(n_0_77)); + NAND2_X1_LVT i_0_80 (.A1(n_0_102), .A2(n_0_77), .ZN(n_0_76)); + OAI221_X1_LVT i_0_83 (.A(n_0_693), .B1(n_0_654), .B2(n_0_484), .C1(n_0_738), + .C2(n_0_350), .ZN(n_0_79)); + OAI21_X1_LVT i_0_82 (.A(n_0_79), .B1(n_0_693), .B2(n_0_138), .ZN(n_0_78)); + OAI21_X1_LVT i_0_79 (.A(n_0_76), .B1(op2[1]), .B2(n_0_78), .ZN(n_0_75)); + NOR2_X1_LVT i_0_78 (.A1(n_0_562), .A2(n_0_75), .ZN(n_0_74)); + AOI22_X1_LVT i_0_75 (.A1(n_35), .A2(n_0_580), .B1(n_3), .B2(n_0_581), + .ZN(n_0_71)); + OAI21_X1_LVT i_0_74 (.A(n_0_681), .B1(n_0_723), .B2(n_0_566), .ZN(n_0_70)); + AOI222_X1_LVT i_0_73 (.A1(n_0_654), .A2(n_0_569), .B1(n_0_663), .B2(n_0_564), + .C1(op1[3]), .C2(n_0_70), .ZN(n_0_69)); + INV_X1_LVT i_0_736 (.A(op1[0]), .ZN(n_0_703)); + OAI22_X1_LVT i_0_77 (.A1(n_0_703), .A2(n_0_531), .B1(n_0_694), .B2(n_0_572), + .ZN(n_0_73)); + OAI22_X1_LVT i_0_76 (.A1(n_0_701), .A2(n_0_73), .B1(op2[0]), .B2(n_0_82), + .ZN(n_0_72)); + OAI211_X1_LVT i_0_72 (.A(n_0_71), .B(n_0_69), .C1(n_0_621), .C2(n_0_72), + .ZN(n_0_68)); + AOI211_X1_LVT i_0_71 (.A(n_0_74), .B(n_0_68), .C1(n_0_547), .C2(n_0_86), + .ZN(n_0_67)); + INV_X1_LVT i_0_70 (.A(n_0_67), .ZN(result[3])); + NAND2_X1_LVT i_0_65 (.A1(n_2), .A2(n_0_581), .ZN(n_0_62)); + OAI221_X1_LVT i_0_66 (.A(op2[2]), .B1(op1[2]), .B2(n_0_564), .C1(n_0_694), + .C2(n_0_567), .ZN(n_0_63)); + AOI21_X1_LVT i_0_64 (.A(aluBypass), .B1(n_0_693), .B2(n_0_569), .ZN(n_0_61)); + OAI21_X1_LVT i_0_63 (.A(n_0_63), .B1(n_0_694), .B2(n_0_61), .ZN(n_0_60)); + AOI21_X1_LVT i_0_62 (.A(n_0_60), .B1(n_34), .B2(n_0_580), .ZN(n_0_59)); + OAI211_X1_LVT i_0_57 (.A(n_0_62), .B(n_0_59), .C1(n_0_548), .C2(n_0_75), + .ZN(n_0_54)); + NOR2_X1_LVT i_0_698 (.A1(n_0_729), .A2(op2[1]), .ZN(n_0_665)); + INV_X1_LVT i_0_697 (.A(n_0_665), .ZN(n_0_664)); + OAI21_X1_LVT i_0_69 (.A(op2[0]), .B1(n_0_664), .B2(n_0_574), .ZN(n_0_66)); + OAI21_X1_LVT i_0_68 (.A(n_0_620), .B1(op2[0]), .B2(n_0_73), .ZN(n_0_65)); + INV_X1_LVT i_0_67 (.A(n_0_65), .ZN(n_0_64)); + OAI222_X1_LVT i_0_61 (.A1(op1[10]), .A2(n_0_617), .B1(op1[2]), .B2(n_0_615), + .C1(n_0_738), .C2(n_0_332), .ZN(n_0_58)); + OAI22_X1_LVT i_0_60 (.A1(op2[2]), .A2(n_0_58), .B1(n_0_693), .B2(n_0_124), + .ZN(n_0_57)); + INV_X1_LVT i_0_59 (.A(n_0_57), .ZN(n_0_56)); + AOI22_X1_LVT i_0_58 (.A1(n_0_728), .A2(n_0_56), .B1(n_0_87), .B2(n_0_77), + .ZN(n_0_55)); + AOI221_X1_LVT i_0_56 (.A(n_0_54), .B1(n_0_66), .B2(n_0_64), .C1(n_0_561), + .C2(n_0_55), .ZN(n_0_53)); + INV_X1_LVT i_0_55 (.A(n_0_53), .ZN(result[2])); + NAND2_X1_LVT i_0_54 (.A1(n_0_547), .A2(n_0_55), .ZN(n_0_52)); + AOI221_X1_LVT i_0_47 (.A(n_0_728), .B1(n_0_729), .B2(n_0_565), .C1(op1[1]), + .C2(n_0_566), .ZN(n_0_45)); + NOR2_X1_LVT i_0_700 (.A1(op1[0]), .A2(n_0_701), .ZN(n_0_667)); + AOI211_X1_LVT i_0_48 (.A(n_0_667), .B(n_0_621), .C1(n_0_729), .C2(n_0_701), + .ZN(n_0_46)); + AOI221_X1_LVT i_0_44 (.A(n_0_45), .B1(op1[1]), .B2(aluBypass), .C1(n_0_571), + .C2(n_0_46), .ZN(n_0_42)); + AOI22_X1_LVT i_0_49 (.A1(n_33), .A2(n_0_580), .B1(n_1), .B2(n_0_581), + .ZN(n_0_47)); + OAI21_X1_LVT i_0_46 (.A(n_0_47), .B1(n_0_664), .B2(n_0_568), .ZN(n_0_44)); + NAND2_X1_LVT i_0_51 (.A1(op2[1]), .A2(n_0_78), .ZN(n_0_49)); + OAI222_X1_LVT i_0_53 (.A1(n_0_722), .A2(n_0_617), .B1(n_0_729), .B2(n_0_615), + .C1(n_0_738), .C2(n_0_313), .ZN(n_0_51)); + OAI22_X1_LVT i_0_52 (.A1(n_0_223), .A2(n_0_103), .B1(op2[2]), .B2(n_0_51), + .ZN(n_0_50)); + OAI21_X1_LVT i_0_50 (.A(n_0_49), .B1(op2[1]), .B2(n_0_50), .ZN(n_0_48)); + AOI21_X1_LVT i_0_45 (.A(n_0_44), .B1(n_0_561), .B2(n_0_48), .ZN(n_0_43)); + NAND3_X1_LVT i_0_43 (.A1(n_0_52), .A2(n_0_42), .A3(n_0_43), .ZN(result[1])); + OAI222_X1_LVT i_0_11 (.A1(n_0_740), .A2(n_0_617), .B1(n_0_703), .B2(n_0_615), + .C1(n_0_738), .C2(n_0_290), .ZN(n_0_10)); + OAI22_X1_LVT i_0_10 (.A1(op2[2]), .A2(n_0_10), .B1(n_0_693), .B2(n_0_88), + .ZN(n_0_9)); + OAI221_X1_LVT i_0_9 (.A(n_0_701), .B1(n_0_728), .B2(n_0_56), .C1(op2[1]), + .C2(n_0_9), .ZN(n_0_8)); + OAI21_X1_LVT i_0_8 (.A(n_0_8), .B1(n_0_701), .B2(n_0_48), .ZN(n_0_7)); + NOR2_X1_LVT i_0_7 (.A1(n_0_579), .A2(n_0_7), .ZN(n_0_6)); + OAI221_X1_LVT i_0_3 (.A(op2[0]), .B1(op1[0]), .B2(n_0_564), .C1(n_0_703), + .C2(n_0_567), .ZN(n_0_2)); + AOI22_X1_LVT i_0_2 (.A1(n_32), .A2(n_0_580), .B1(n_0), .B2(n_0_581), .ZN( + n_0_1)); + NAND3_X1_LVT i_0_6 (.A1(n_0_701), .A2(n_0_571), .A3(n_0_620), .ZN(n_0_5)); + OAI211_X1_LVT i_0_5 (.A(n_0_681), .B(n_0_5), .C1(op2[0]), .C2(n_0_568), + .ZN(n_0_4)); + NAND2_X1_LVT i_0_4 (.A1(op1[0]), .A2(n_0_4), .ZN(n_0_3)); + NAND3_X1_LVT i_0_1 (.A1(n_0_2), .A2(n_0_1), .A3(n_0_3), .ZN(n_0_0)); + OAI33_X1_LVT i_0_14 (.A1(n_0_692), .A2(op1[31]), .A3(n_0_683), .B1(op2[31]), + .B2(n_0_691), .B3(aluOp[0]), .ZN(n_0_13)); + INV_X1_LVT i_0_741 (.A(op2[29]), .ZN(n_0_708)); + NAND2_X1_LVT i_0_685 (.A1(op1[29]), .A2(n_0_708), .ZN(n_0_652)); + OAI22_X1_LVT i_0_713 (.A1(n_0_700), .A2(op1[28]), .B1(op1[29]), .B2(n_0_708), + .ZN(n_0_680)); + NAND2_X1_LVT i_0_694 (.A1(n_0_688), .A2(op2[27]), .ZN(n_0_661)); + INV_X1_LVT i_0_742 (.A(op2[26]), .ZN(n_0_709)); + OAI22_X1_LVT i_0_712 (.A1(n_0_699), .A2(op2[25]), .B1(n_0_736), .B2(op2[24]), + .ZN(n_0_679)); + NAND2_X1_LVT i_0_690 (.A1(n_0_727), .A2(op2[20]), .ZN(n_0_657)); + INV_X1_LVT i_0_740 (.A(op2[18]), .ZN(n_0_707)); + OAI22_X1_LVT i_0_711 (.A1(n_0_707), .A2(op1[18]), .B1(n_0_690), .B2(op1[19]), + .ZN(n_0_678)); + OAI22_X1_LVT i_0_29 (.A1(n_0_739), .A2(op2[16]), .B1(n_0_734), .B2(op2[15]), + .ZN(n_0_28)); + INV_X1_LVT i_0_728 (.A(op2[12]), .ZN(n_0_695)); + INV_X1_LVT i_0_748 (.A(op2[13]), .ZN(n_0_715)); + OAI22_X1_LVT i_0_704 (.A1(n_0_706), .A2(op2[11]), .B1(n_0_696), .B2(op2[12]), + .ZN(n_0_671)); + AOI22_X1_LVT i_0_710 (.A1(n_0_740), .A2(op2[8]), .B1(n_0_713), .B2(op2[7]), + .ZN(n_0_677)); + OAI22_X1_LVT i_0_707 (.A1(n_0_731), .A2(op1[5]), .B1(op1[6]), .B2(n_0_702), + .ZN(n_0_674)); + OAI22_X1_LVT i_0_706 (.A1(op1[2]), .A2(n_0_693), .B1(op1[1]), .B2(n_0_728), + .ZN(n_0_673)); + INV_X1_LVT i_0_705 (.A(n_0_673), .ZN(n_0_672)); + INV_X1_LVT i_0_699 (.A(n_0_667), .ZN(n_0_666)); + OAI21_X1_LVT i_0_42 (.A(n_0_672), .B1(n_0_666), .B2(n_0_665), .ZN(n_0_41)); + AOI21_X1_LVT i_0_41 (.A(n_0_654), .B1(op1[2]), .B2(n_0_693), .ZN(n_0_40)); + AOI211_X1_LVT i_0_40 (.A(n_0_668), .B(n_0_663), .C1(n_0_41), .C2(n_0_40), + .ZN(n_0_39)); + AOI211_X1_LVT i_0_39 (.A(n_0_656), .B(n_0_39), .C1(n_0_731), .C2(op1[5]), + .ZN(n_0_38)); + OAI222_X1_LVT i_0_38 (.A1(n_0_704), .A2(op2[6]), .B1(n_0_674), .B2(n_0_38), + .C1(n_0_713), .C2(op2[7]), .ZN(n_0_37)); + AOI221_X1_LVT i_0_37 (.A(n_0_655), .B1(op1[9]), .B2(n_0_720), .C1(n_0_677), + .C2(n_0_37), .ZN(n_0_36)); + INV_X1_LVT i_0_768 (.A(op2[10]), .ZN(n_0_735)); + OAI22_X1_LVT i_0_36 (.A1(n_0_735), .A2(op1[10]), .B1(op1[9]), .B2(n_0_720), + .ZN(n_0_35)); + OAI22_X1_LVT i_0_35 (.A1(op2[10]), .A2(n_0_733), .B1(n_0_36), .B2(n_0_35), + .ZN(n_0_34)); + INV_X1_LVT i_0_34 (.A(n_0_34), .ZN(n_0_33)); + AOI21_X1_LVT i_0_33 (.A(n_0_33), .B1(n_0_706), .B2(op2[11]), .ZN(n_0_32)); + OAI222_X1_LVT i_0_32 (.A1(op1[12]), .A2(n_0_695), .B1(n_0_715), .B2(op1[13]), + .C1(n_0_671), .C2(n_0_32), .ZN(n_0_31)); + OAI221_X1_LVT i_0_31 (.A(n_0_31), .B1(n_0_721), .B2(op2[14]), .C1(op2[13]), + .C2(n_0_714), .ZN(n_0_30)); + AOI22_X1_LVT i_0_30 (.A1(n_0_734), .A2(op2[15]), .B1(n_0_721), .B2(op2[14]), + .ZN(n_0_29)); + AOI21_X1_LVT i_0_28 (.A(n_0_28), .B1(n_0_30), .B2(n_0_29), .ZN(n_0_27)); + AOI221_X1_LVT i_0_27 (.A(n_0_27), .B1(n_0_732), .B2(op2[17]), .C1(n_0_739), + .C2(op2[16]), .ZN(n_0_26)); + AOI211_X1_LVT i_0_26 (.A(n_0_660), .B(n_0_26), .C1(n_0_707), .C2(op1[18]), + .ZN(n_0_25)); + OAI22_X1_LVT i_0_25 (.A1(op2[19]), .A2(n_0_689), .B1(n_0_678), .B2(n_0_25), + .ZN(n_0_24)); + AOI211_X1_LVT i_0_24 (.A(n_0_658), .B(n_0_659), .C1(n_0_657), .C2(n_0_24), + .ZN(n_0_23)); + AOI221_X1_LVT i_0_23 (.A(n_0_23), .B1(n_0_726), .B2(op2[21]), .C1(n_0_687), + .C2(op2[22]), .ZN(n_0_22)); + AOI221_X1_LVT i_0_22 (.A(n_0_22), .B1(op1[22]), .B2(n_0_686), .C1(op1[23]), + .C2(n_0_718), .ZN(n_0_21)); + AOI221_X1_LVT i_0_21 (.A(n_0_21), .B1(n_0_736), .B2(op2[24]), .C1(n_0_719), + .C2(op2[23]), .ZN(n_0_20)); + OAI222_X1_LVT i_0_20 (.A1(op1[26]), .A2(n_0_709), .B1(op1[25]), .B2(n_0_697), + .C1(n_0_679), .C2(n_0_20), .ZN(n_0_19)); + OAI221_X1_LVT i_0_19 (.A(n_0_19), .B1(n_0_711), .B2(op2[26]), .C1(n_0_688), + .C2(op2[27]), .ZN(n_0_18)); + AOI22_X1_LVT i_0_18 (.A1(n_0_700), .A2(op1[28]), .B1(n_0_661), .B2(n_0_18), + .ZN(n_0_17)); + OAI21_X1_LVT i_0_17 (.A(n_0_652), .B1(n_0_680), .B2(n_0_17), .ZN(n_0_16)); + INV_X1_LVT i_0_749 (.A(op2[30]), .ZN(n_0_716)); + OAI21_X1_LVT i_0_16 (.A(n_0_16), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_15)); + OAI22_X1_LVT i_0_708 (.A1(n_0_692), .A2(op1[31]), .B1(op2[31]), .B2(n_0_691), + .ZN(n_0_675)); + AOI21_X1_LVT i_0_15 (.A(n_0_675), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_14)); + AOI21_X1_LVT i_0_13 (.A(n_0_13), .B1(n_0_15), .B2(n_0_14), .ZN(n_0_12)); + NOR4_X1_LVT i_0_12 (.A1(n_0_685), .A2(aluOp[2]), .A3(aluBypass), .A4(n_0_12), + .ZN(n_0_11)); + OR3_X1_LVT i_0_0 (.A1(n_0_6), .A2(n_0_0), .A3(n_0_11), .ZN(result[0])); + OR4_X1_LVT i_0_703 (.A1(n_0_680), .A2(n_0_673), .A3(n_0_675), .A4(n_0_678), + .ZN(n_0_670)); + INV_X1_LVT i_0_709 (.A(n_0_677), .ZN(n_0_676)); + OR4_X1_LVT i_0_702 (.A1(n_0_679), .A2(n_0_674), .A3(n_0_676), .A4(n_0_671), + .ZN(n_0_669)); + AOI22_X1_LVT i_0_663 (.A1(n_0_688), .A2(op2[27]), .B1(op1[22]), .B2(n_0_686), + .ZN(n_0_630)); + OAI22_X1_LVT i_0_662 (.A1(n_0_694), .A2(op2[2]), .B1(op1[30]), .B2(n_0_716), + .ZN(n_0_629)); + AOI221_X1_LVT i_0_661 (.A(n_0_629), .B1(n_0_711), .B2(op2[26]), .C1(n_0_721), + .C2(op2[14]), .ZN(n_0_628)); + AOI21_X1_LVT i_0_664 (.A(n_0_660), .B1(n_0_690), .B2(op1[19]), .ZN(n_0_631)); + OAI222_X1_LVT i_0_660 (.A1(op1[12]), .A2(n_0_695), .B1(n_0_688), .B2(op2[27]), + .C1(op1[22]), .C2(n_0_686), .ZN(n_0_627)); + AOI21_X1_LVT i_0_659 (.A(n_0_663), .B1(n_0_734), .B2(op2[15]), .ZN(n_0_626)); + OAI211_X1_LVT i_0_658 (.A(n_0_666), .B(n_0_626), .C1(n_0_715), .C2(op1[13]), + .ZN(n_0_625)); + AOI211_X1_LVT i_0_657 (.A(n_0_627), .B(n_0_625), .C1(op1[23]), .C2(n_0_718), + .ZN(n_0_624)); + NAND4_X1_LVT i_0_656 (.A1(n_0_630), .A2(n_0_628), .A3(n_0_631), .A4(n_0_624), + .ZN(n_0_623)); + OAI22_X1_LVT i_0_684 (.A1(n_0_721), .A2(op2[14]), .B1(n_0_722), .B2(op2[9]), + .ZN(n_0_651)); + AOI211_X1_LVT i_0_668 (.A(n_0_651), .B(n_0_654), .C1(n_0_719), .C2(op2[23]), + .ZN(n_0_635)); + NAND2_X1_LVT i_0_667 (.A1(n_0_664), .A2(n_0_657), .ZN(n_0_634)); + NOR3_X1_LVT i_0_666 (.A1(n_0_659), .A2(n_0_656), .A3(n_0_634), .ZN(n_0_633)); + AOI21_X1_LVT i_0_671 (.A(n_0_655), .B1(n_0_739), .B2(op2[16]), .ZN(n_0_638)); + AOI21_X1_LVT i_0_670 (.A(n_0_668), .B1(n_0_736), .B2(op2[24]), .ZN(n_0_637)); + OAI22_X1_LVT i_0_673 (.A1(n_0_735), .A2(op1[10]), .B1(n_0_734), .B2(op2[15]), + .ZN(n_0_640)); + AOI221_X1_LVT i_0_672 (.A(n_0_640), .B1(n_0_732), .B2(op2[17]), .C1(n_0_731), + .C2(op1[5]), .ZN(n_0_639)); + AND3_X1_LVT i_0_669 (.A1(n_0_638), .A2(n_0_637), .A3(n_0_639), .ZN(n_0_636)); + OAI22_X1_LVT i_0_682 (.A1(n_0_703), .A2(op2[0]), .B1(n_0_704), .B2(op2[6]), + .ZN(n_0_649)); + OAI22_X1_LVT i_0_681 (.A1(op2[28]), .A2(n_0_698), .B1(op1[25]), .B2(n_0_697), + .ZN(n_0_648)); + AOI21_X1_LVT i_0_678 (.A(n_0_658), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_645)); + AOI21_X1_LVT i_0_677 (.A(n_0_662), .B1(n_0_735), .B2(op1[10]), .ZN(n_0_644)); + INV_X1_LVT i_0_758 (.A(op2[21]), .ZN(n_0_725)); + OAI22_X1_LVT i_0_683 (.A1(op1[21]), .A2(n_0_725), .B1(n_0_739), .B2(op2[16]), + .ZN(n_0_650)); + AOI221_X1_LVT i_0_676 (.A(n_0_650), .B1(n_0_722), .B2(op2[9]), .C1(op1[7]), + .C2(n_0_712), .ZN(n_0_643)); + OAI21_X1_LVT i_0_680 (.A(n_0_652), .B1(n_0_711), .B2(op2[26]), .ZN(n_0_647)); + AOI221_X1_LVT i_0_679 (.A(n_0_647), .B1(n_0_706), .B2(op2[11]), .C1(n_0_707), + .C2(op1[18]), .ZN(n_0_646)); + NAND4_X1_LVT i_0_675 (.A1(n_0_645), .A2(n_0_644), .A3(n_0_643), .A4(n_0_646), + .ZN(n_0_642)); + NOR3_X1_LVT i_0_674 (.A1(n_0_649), .A2(n_0_648), .A3(n_0_642), .ZN(n_0_641)); + NAND4_X1_LVT i_0_665 (.A1(n_0_635), .A2(n_0_633), .A3(n_0_636), .A4(n_0_641), + .ZN(n_0_632)); + NOR4_X1_LVT i_0_655 (.A1(n_0_670), .A2(n_0_669), .A3(n_0_623), .A4(n_0_632), + .ZN(eqFlag)); +endmodule + +module decoder(CurrentPC, JumpOrBranchPC, JumpOrBranch, DAddr, WData, RData, + Instruction, WrMem, DWidth, Rs1, Rs2, Rd, RRs1, RRs2, WRd, WrReg, Illegal); + input [31:0]CurrentPC; + output [31:0]JumpOrBranchPC; + output JumpOrBranch; + output [31:0]DAddr; + output [31:0]WData; + input [31:0]RData; + input [31:0]Instruction; + output WrMem; + output [1:0]DWidth; + output [4:0]Rs1; + output [4:0]Rs2; + output [4:0]Rd; + input [31:0]RRs1; + input [31:0]RRs2; + output [31:0]WRd; + output WrReg; + output Illegal; + + wire eqFlag; + wire n_0_15; + wire n_0_2; + wire n_0_16; + wire n_0_3; + wire n_0_17; + wire n_0_4; + wire n_0_18; + wire n_0_5; + wire n_0_19; + wire n_0_6; + wire n_0_20; + wire n_0_7; + wire n_0_21; + wire n_0_8; + wire n_0_22; + wire n_0_9; + wire n_0_23; + wire n_0_10; + wire n_0_24; + wire n_0_11; + wire n_0_25; + wire n_0_12; + wire n_0_26; + wire n_0_13; + wire n_0_27; + wire n_0_14; + wire n_0_28; + wire n_0_29; + wire n_0_30; + wire n_0_31; + wire n_0_32; + wire n_0_33; + wire n_0_34; + wire n_0_35; + wire n_0_36; + wire n_0_37; + wire n_0_38; + wire n_0_39; + wire n_0_40; + wire n_0_41; + wire n_0_42; + wire n_0_43; + wire n_0_44; + wire n_0_45; + wire n_0_46; + wire n_0_47; + wire n_0_48; + wire n_0_49; + wire n_0_50; + wire n_0_51; + wire n_0_52; + wire n_0_53; + wire n_0_54; + wire n_0_55; + wire n_0_56; + wire n_0_57; + wire n_0_58; + wire n_0_59; + wire n_0_60; + wire n_0_61; + wire n_0_62; + wire n_0_63; + wire n_0_64; + wire n_0_65; + wire n_0_66; + wire n_0_67; + wire n_0_68; + wire n_0_69; + wire n_0_70; + wire n_0_71; + wire n_0_72; + wire n_0_73; + wire n_0_74; + wire n_0_75; + wire n_0_76; + wire n_0_77; + wire n_0_78; + wire n_0_79; + wire n_0_80; + wire n_0_81; + wire n_0_82; + wire n_0_83; + wire n_0_84; + wire n_0_85; + wire n_0_86; + wire n_0_87; + wire n_0_88; + wire n_0_89; + wire n_0_90; + wire n_0_91; + wire n_0_92; + wire n_0_93; + wire n_0_94; + wire n_0_95; + wire n_0_96; + wire n_0_97; + wire [2:0]aluOp; + wire n_0_98; + wire n_0_99; + wire n_0_100; + wire aluNegAr; + wire n_0_101; + wire n_0_102; + wire n_0_103; + wire n_0_104; + wire n_0_105; + wire aluBypass; + wire n_0_106; + wire [31:0]op1; + wire n_0_107; + wire n_0_108; + wire n_0_109; + wire n_0_110; + wire n_0_111; + wire n_0_112; + wire n_0_113; + wire n_0_114; + wire n_0_115; + wire n_0_116; + wire n_0_117; + wire n_0_118; + wire n_0_119; + wire n_0_120; + wire n_0_121; + wire n_0_122; + wire n_0_123; + wire n_0_124; + wire n_0_125; + wire n_0_126; + wire n_0_127; + wire n_0_128; + wire n_0_129; + wire n_0_130; + wire n_0_131; + wire n_0_132; + wire n_0_133; + wire n_0_134; + wire n_0_135; + wire n_0_136; + wire n_0_137; + wire n_0_138; + wire n_0_139; + wire n_0_140; + wire n_0_141; + wire n_0_142; + wire n_0_143; + wire n_0_144; + wire n_0_145; + wire n_0_146; + wire n_0_147; + wire n_0_148; + wire n_0_149; + wire n_0_150; + wire n_0_151; + wire n_0_152; + wire n_0_153; + wire n_0_154; + wire n_0_155; + wire n_0_156; + wire n_0_157; + wire n_0_158; + wire n_0_159; + wire n_0_160; + wire n_0_161; + wire n_0_162; + wire n_0_163; + wire n_0_164; + wire n_0_165; + wire n_0_166; + wire n_0_167; + wire n_0_168; + wire n_0_169; + wire [31:0]op2; + wire n_0_170; + wire n_0_171; + wire n_0_172; + wire n_0_173; + wire n_0_174; + wire n_0_175; + wire n_0_176; + wire n_0_177; + wire n_0_178; + wire n_0_179; + wire n_0_180; + wire n_0_181; + wire n_0_182; + wire n_0_183; + wire n_0_184; + wire n_0_185; + wire n_0_186; + wire n_0_187; + wire n_0_188; + wire n_0_189; + wire n_0_190; + wire n_0_191; + wire n_0_192; + wire n_0_193; + wire n_0_194; + wire n_0_195; + wire n_0_196; + wire n_0_197; + wire n_0_198; + wire n_0_199; + wire n_0_200; + wire n_0_201; + wire n_0_202; + wire n_0_203; + wire n_0_204; + wire n_0_205; + wire n_0_206; + wire n_0_207; + wire n_0_208; + wire n_0_209; + wire n_0_210; + wire n_0_211; + wire n_0_212; + wire n_0_213; + wire n_0_214; + wire n_0_215; + wire n_0_216; + wire n_0_217; + wire n_0_218; + wire n_0_219; + wire n_0_220; + wire n_0_221; + wire n_0_222; + wire n_0_223; + wire n_0_224; + wire n_0_225; + wire n_0_226; + wire n_0_227; + wire n_0_228; + wire n_0_229; + wire n_0_230; + wire n_0_231; + wire n_0_232; + wire n_0_233; + wire n_0_234; + wire n_0_235; + wire n_0_236; + wire n_0_237; + wire n_0_238; + wire n_0_239; + wire n_0_240; + wire n_0_241; + wire n_0_242; + wire n_0_1; + wire n_0_0; + wire n_0_243; + wire n_0_244; + wire n_0_245; + wire n_0_246; + wire n_0_247; + wire n_0_248; + wire n_0_249; + + datapathS__0_28 i_18 (.b_imm({uc_0, uc_1, uc_2, uc_3, uc_4, uc_5, uc_6, uc_7, + uc_8, uc_9, uc_10, uc_11, uc_12, uc_13, uc_14, uc_15, uc_16, uc_17, uc_18, + Instruction[31], Instruction[7], Instruction[30], Instruction[29], + Instruction[28], Instruction[27], Instruction[26], Instruction[25], + Instruction[11], Instruction[10], Instruction[9], Instruction[8], 1'b0}), + .CurrentPC({CurrentPC[31], CurrentPC[30], CurrentPC[29], CurrentPC[28], + CurrentPC[27], CurrentPC[26], CurrentPC[25], CurrentPC[24], CurrentPC[23], + CurrentPC[22], CurrentPC[21], CurrentPC[20], CurrentPC[19], CurrentPC[18], + CurrentPC[17], CurrentPC[16], CurrentPC[15], CurrentPC[14], CurrentPC[13], + CurrentPC[12], CurrentPC[11], CurrentPC[10], CurrentPC[9], CurrentPC[8], + CurrentPC[7], CurrentPC[6], CurrentPC[5], CurrentPC[4], CurrentPC[3], + CurrentPC[2], CurrentPC[1], uc_19}), .p_0({n_93, n_92, n_91, n_90, n_89, + n_88, n_87, n_86, n_85, n_84, n_83, n_82, n_81, n_80, n_79, n_78, n_77, + n_76, n_75, n_74, n_73, n_72, n_71, n_70, n_69, n_68, n_67, n_66, n_65, + n_64, n_63, uc_20})); + INV_X1_LVT i_0_350 (.A(Instruction[3]), .ZN(n_0_243)); + NAND3_X1_LVT i_0_343 (.A1(n_0_243), .A2(Instruction[0]), .A3(Instruction[1]), + .ZN(n_0_238)); + OR2_X1_LVT i_0_332 (.A1(n_0_238), .A2(Instruction[2]), .ZN(n_0_228)); + INV_X1_LVT i_0_351 (.A(Instruction[5]), .ZN(n_0_244)); + NOR2_X1_LVT i_0_340 (.A1(n_0_244), .A2(Instruction[4]), .ZN(n_0_235)); + NAND2_X1_LVT i_0_329 (.A1(Instruction[6]), .A2(n_0_235), .ZN(n_0_225)); + INV_X1_LVT i_0_354 (.A(Instruction[13]), .ZN(n_0_247)); + NOR2_X1_LVT i_0_345 (.A1(n_0_247), .A2(Instruction[14]), .ZN(n_0_240)); + NOR3_X1_LVT i_0_118 (.A1(n_0_228), .A2(n_0_225), .A3(n_0_240), .ZN(n_0_99)); + NAND3_X1_LVT i_0_346 (.A1(Instruction[0]), .A2(Instruction[1]), .A3( + Instruction[2]), .ZN(n_0_241)); + NOR2_X1_LVT i_0_328 (.A1(n_0_241), .A2(n_0_225), .ZN(n_0_224)); + INV_X1_LVT i_0_356 (.A(n_0_224), .ZN(n_0_249)); + NOR2_X1_LVT i_0_108 (.A1(n_0_243), .A2(n_0_249), .ZN(n_0_91)); + datapathS__0_26 i_17 (.j_imm({uc_21, uc_22, uc_23, uc_24, uc_25, uc_26, uc_27, + uc_28, uc_29, uc_30, uc_31, Instruction[31], Instruction[19], + Instruction[18], Instruction[17], Instruction[16], Instruction[15], + Instruction[14], Instruction[13], Instruction[12], Instruction[20], + Instruction[30], Instruction[29], Instruction[28], Instruction[27], + Instruction[26], Instruction[25], Instruction[24], Instruction[23], + Instruction[22], Instruction[21], 1'b0}), .CurrentPC({CurrentPC[31], + CurrentPC[30], CurrentPC[29], CurrentPC[28], CurrentPC[27], CurrentPC[26], + CurrentPC[25], CurrentPC[24], CurrentPC[23], CurrentPC[22], CurrentPC[21], + CurrentPC[20], CurrentPC[19], CurrentPC[18], CurrentPC[17], CurrentPC[16], + CurrentPC[15], CurrentPC[14], CurrentPC[13], CurrentPC[12], CurrentPC[11], + CurrentPC[10], CurrentPC[9], CurrentPC[8], CurrentPC[7], CurrentPC[6], + CurrentPC[5], CurrentPC[4], CurrentPC[3], CurrentPC[2], CurrentPC[1], + uc_32}), .p_0({n_62, n_61, n_60, n_59, n_58, n_57, n_56, n_55, n_54, n_53, + n_52, n_51, n_50, n_49, n_48, n_47, n_46, n_45, n_44, n_43, n_42, n_41, + n_40, n_39, n_38, n_37, n_36, n_35, n_34, n_33, n_32, uc_33})); + datapathS__0_14 i_5 (.i_imm({uc_34, uc_35, uc_36, uc_37, uc_38, uc_39, uc_40, + uc_41, uc_42, uc_43, uc_44, uc_45, uc_46, uc_47, uc_48, uc_49, uc_50, + uc_51, uc_52, uc_53, Instruction[31], Instruction[30], Instruction[29], + Instruction[28], Instruction[27], Instruction[26], Instruction[25], + Instruction[24], Instruction[23], Instruction[22], Instruction[21], + Instruction[20]}), .RRs1(RRs1), .p_0({n_31, n_30, n_29, n_28, n_27, n_26, + n_25, n_24, n_23, n_22, n_21, n_20, n_19, n_18, n_17, n_16, n_15, n_14, + n_13, n_12, n_11, n_10, n_9, n_8, n_7, n_6, n_5, n_4, n_3, n_2, n_1, n_0})); + NOR2_X1_LVT i_0_107 (.A1(n_0_249), .A2(Instruction[3]), .ZN(n_0_90)); + AOI222_X1_LVT i_0_106 (.A1(n_93), .A2(n_0_99), .B1(n_0_91), .B2(n_62), + .C1(n_31), .C2(n_0_90), .ZN(n_0_89)); + INV_X1_LVT i_0_355 (.A(Instruction[6]), .ZN(n_0_248)); + NAND2_X1_LVT i_0_339 (.A1(n_0_248), .A2(Instruction[4]), .ZN(n_0_234)); + INV_X1_LVT i_0_338 (.A(n_0_234), .ZN(n_0_233)); + OAI21_X1_LVT i_0_341 (.A(Instruction[13]), .B1(Instruction[14]), .B2( + Instruction[12]), .ZN(n_0_236)); + AOI211_X1_LVT i_0_337 (.A(n_0_235), .B(n_0_233), .C1(n_0_248), .C2(n_0_236), + .ZN(n_0_232)); + INV_X1_LVT i_0_352 (.A(Instruction[4]), .ZN(n_0_245)); + NAND2_X1_LVT i_0_344 (.A1(n_0_245), .A2(Instruction[2]), .ZN(n_0_239)); + AOI21_X1_LVT i_0_335 (.A(Instruction[6]), .B1(n_0_243), .B2(n_0_239), + .ZN(n_0_230)); + NOR2_X1_LVT i_0_334 (.A1(n_0_232), .A2(n_0_230), .ZN(n_0_229)); + NAND2_X1_LVT i_0_342 (.A1(n_0_241), .A2(n_0_238), .ZN(n_0_237)); + NAND2_X1_LVT i_0_336 (.A1(Instruction[6]), .A2(n_0_240), .ZN(n_0_231)); + OAI211_X1_LVT i_0_333 (.A(n_0_229), .B(n_0_237), .C1(Instruction[2]), + .C2(n_0_231), .ZN(Illegal)); + NAND2_X1_LVT i_0_109 (.A1(Illegal), .A2(CurrentPC[31]), .ZN(n_0_92)); + NAND2_X1_LVT i_0_105 (.A1(n_0_89), .A2(n_0_92), .ZN(JumpOrBranchPC[31])); + AOI222_X1_LVT i_0_103 (.A1(n_92), .A2(n_0_99), .B1(n_0_91), .B2(n_61), + .C1(n_30), .C2(n_0_90), .ZN(n_0_87)); + NAND2_X1_LVT i_0_104 (.A1(Illegal), .A2(CurrentPC[30]), .ZN(n_0_88)); + NAND2_X1_LVT i_0_102 (.A1(n_0_87), .A2(n_0_88), .ZN(JumpOrBranchPC[30])); + AOI222_X1_LVT i_0_100 (.A1(n_91), .A2(n_0_99), .B1(n_0_91), .B2(n_60), + .C1(n_29), .C2(n_0_90), .ZN(n_0_85)); + NAND2_X1_LVT i_0_101 (.A1(Illegal), .A2(CurrentPC[29]), .ZN(n_0_86)); + NAND2_X1_LVT i_0_99 (.A1(n_0_85), .A2(n_0_86), .ZN(JumpOrBranchPC[29])); + AOI222_X1_LVT i_0_97 (.A1(n_90), .A2(n_0_99), .B1(n_0_91), .B2(n_59), + .C1(n_28), .C2(n_0_90), .ZN(n_0_83)); + NAND2_X1_LVT i_0_98 (.A1(Illegal), .A2(CurrentPC[28]), .ZN(n_0_84)); + NAND2_X1_LVT i_0_96 (.A1(n_0_83), .A2(n_0_84), .ZN(JumpOrBranchPC[28])); + AOI222_X1_LVT i_0_94 (.A1(n_89), .A2(n_0_99), .B1(n_0_91), .B2(n_58), + .C1(n_27), .C2(n_0_90), .ZN(n_0_81)); + NAND2_X1_LVT i_0_95 (.A1(Illegal), .A2(CurrentPC[27]), .ZN(n_0_82)); + NAND2_X1_LVT i_0_93 (.A1(n_0_81), .A2(n_0_82), .ZN(JumpOrBranchPC[27])); + AOI222_X1_LVT i_0_91 (.A1(n_88), .A2(n_0_99), .B1(n_0_91), .B2(n_57), + .C1(n_26), .C2(n_0_90), .ZN(n_0_79)); + NAND2_X1_LVT i_0_92 (.A1(Illegal), .A2(CurrentPC[26]), .ZN(n_0_80)); + NAND2_X1_LVT i_0_90 (.A1(n_0_79), .A2(n_0_80), .ZN(JumpOrBranchPC[26])); + AOI222_X1_LVT i_0_88 (.A1(n_87), .A2(n_0_99), .B1(n_0_91), .B2(n_56), + .C1(n_25), .C2(n_0_90), .ZN(n_0_77)); + NAND2_X1_LVT i_0_89 (.A1(Illegal), .A2(CurrentPC[25]), .ZN(n_0_78)); + NAND2_X1_LVT i_0_87 (.A1(n_0_77), .A2(n_0_78), .ZN(JumpOrBranchPC[25])); + AOI222_X1_LVT i_0_85 (.A1(n_86), .A2(n_0_99), .B1(n_0_91), .B2(n_55), + .C1(n_24), .C2(n_0_90), .ZN(n_0_75)); + NAND2_X1_LVT i_0_86 (.A1(Illegal), .A2(CurrentPC[24]), .ZN(n_0_76)); + NAND2_X1_LVT i_0_84 (.A1(n_0_75), .A2(n_0_76), .ZN(JumpOrBranchPC[24])); + AOI222_X1_LVT i_0_82 (.A1(n_85), .A2(n_0_99), .B1(n_0_91), .B2(n_54), + .C1(n_23), .C2(n_0_90), .ZN(n_0_73)); + NAND2_X1_LVT i_0_83 (.A1(Illegal), .A2(CurrentPC[23]), .ZN(n_0_74)); + NAND2_X1_LVT i_0_81 (.A1(n_0_73), .A2(n_0_74), .ZN(JumpOrBranchPC[23])); + AOI222_X1_LVT i_0_79 (.A1(n_84), .A2(n_0_99), .B1(n_0_91), .B2(n_53), + .C1(n_22), .C2(n_0_90), .ZN(n_0_71)); + NAND2_X1_LVT i_0_80 (.A1(Illegal), .A2(CurrentPC[22]), .ZN(n_0_72)); + NAND2_X1_LVT i_0_78 (.A1(n_0_71), .A2(n_0_72), .ZN(JumpOrBranchPC[22])); + AOI222_X1_LVT i_0_76 (.A1(n_83), .A2(n_0_99), .B1(n_0_91), .B2(n_52), + .C1(n_21), .C2(n_0_90), .ZN(n_0_69)); + NAND2_X1_LVT i_0_77 (.A1(Illegal), .A2(CurrentPC[21]), .ZN(n_0_70)); + NAND2_X1_LVT i_0_75 (.A1(n_0_69), .A2(n_0_70), .ZN(JumpOrBranchPC[21])); + AOI222_X1_LVT i_0_73 (.A1(n_82), .A2(n_0_99), .B1(n_0_91), .B2(n_51), + .C1(n_20), .C2(n_0_90), .ZN(n_0_67)); + NAND2_X1_LVT i_0_74 (.A1(Illegal), .A2(CurrentPC[20]), .ZN(n_0_68)); + NAND2_X1_LVT i_0_72 (.A1(n_0_67), .A2(n_0_68), .ZN(JumpOrBranchPC[20])); + AOI222_X1_LVT i_0_70 (.A1(n_81), .A2(n_0_99), .B1(n_0_91), .B2(n_50), + .C1(n_19), .C2(n_0_90), .ZN(n_0_65)); + NAND2_X1_LVT i_0_71 (.A1(Illegal), .A2(CurrentPC[19]), .ZN(n_0_66)); + NAND2_X1_LVT i_0_69 (.A1(n_0_65), .A2(n_0_66), .ZN(JumpOrBranchPC[19])); + AOI222_X1_LVT i_0_67 (.A1(n_80), .A2(n_0_99), .B1(n_0_91), .B2(n_49), + .C1(n_18), .C2(n_0_90), .ZN(n_0_63)); + NAND2_X1_LVT i_0_68 (.A1(Illegal), .A2(CurrentPC[18]), .ZN(n_0_64)); + NAND2_X1_LVT i_0_66 (.A1(n_0_63), .A2(n_0_64), .ZN(JumpOrBranchPC[18])); + AOI222_X1_LVT i_0_64 (.A1(n_79), .A2(n_0_99), .B1(n_0_91), .B2(n_48), + .C1(n_17), .C2(n_0_90), .ZN(n_0_61)); + NAND2_X1_LVT i_0_65 (.A1(Illegal), .A2(CurrentPC[17]), .ZN(n_0_62)); + NAND2_X1_LVT i_0_63 (.A1(n_0_61), .A2(n_0_62), .ZN(JumpOrBranchPC[17])); + AOI222_X1_LVT i_0_61 (.A1(n_78), .A2(n_0_99), .B1(n_0_91), .B2(n_47), + .C1(n_16), .C2(n_0_90), .ZN(n_0_59)); + NAND2_X1_LVT i_0_62 (.A1(Illegal), .A2(CurrentPC[16]), .ZN(n_0_60)); + NAND2_X1_LVT i_0_60 (.A1(n_0_59), .A2(n_0_60), .ZN(JumpOrBranchPC[16])); + AOI222_X1_LVT i_0_58 (.A1(n_77), .A2(n_0_99), .B1(n_0_91), .B2(n_46), + .C1(n_15), .C2(n_0_90), .ZN(n_0_57)); + NAND2_X1_LVT i_0_59 (.A1(Illegal), .A2(CurrentPC[15]), .ZN(n_0_58)); + NAND2_X1_LVT i_0_57 (.A1(n_0_57), .A2(n_0_58), .ZN(JumpOrBranchPC[15])); + AOI222_X1_LVT i_0_55 (.A1(n_76), .A2(n_0_99), .B1(n_0_91), .B2(n_45), + .C1(n_14), .C2(n_0_90), .ZN(n_0_55)); + NAND2_X1_LVT i_0_56 (.A1(Illegal), .A2(CurrentPC[14]), .ZN(n_0_56)); + NAND2_X1_LVT i_0_54 (.A1(n_0_55), .A2(n_0_56), .ZN(JumpOrBranchPC[14])); + AOI222_X1_LVT i_0_52 (.A1(n_75), .A2(n_0_99), .B1(n_0_91), .B2(n_44), + .C1(n_13), .C2(n_0_90), .ZN(n_0_53)); + NAND2_X1_LVT i_0_53 (.A1(Illegal), .A2(CurrentPC[13]), .ZN(n_0_54)); + NAND2_X1_LVT i_0_51 (.A1(n_0_53), .A2(n_0_54), .ZN(JumpOrBranchPC[13])); + AOI222_X1_LVT i_0_49 (.A1(n_74), .A2(n_0_99), .B1(n_0_91), .B2(n_43), + .C1(n_12), .C2(n_0_90), .ZN(n_0_51)); + NAND2_X1_LVT i_0_50 (.A1(Illegal), .A2(CurrentPC[12]), .ZN(n_0_52)); + NAND2_X1_LVT i_0_48 (.A1(n_0_51), .A2(n_0_52), .ZN(JumpOrBranchPC[12])); + AOI222_X1_LVT i_0_46 (.A1(n_73), .A2(n_0_99), .B1(n_0_91), .B2(n_42), + .C1(n_11), .C2(n_0_90), .ZN(n_0_49)); + NAND2_X1_LVT i_0_47 (.A1(Illegal), .A2(CurrentPC[11]), .ZN(n_0_50)); + NAND2_X1_LVT i_0_45 (.A1(n_0_49), .A2(n_0_50), .ZN(JumpOrBranchPC[11])); + AOI222_X1_LVT i_0_43 (.A1(n_72), .A2(n_0_99), .B1(n_0_91), .B2(n_41), + .C1(n_10), .C2(n_0_90), .ZN(n_0_47)); + NAND2_X1_LVT i_0_44 (.A1(Illegal), .A2(CurrentPC[10]), .ZN(n_0_48)); + NAND2_X1_LVT i_0_42 (.A1(n_0_47), .A2(n_0_48), .ZN(JumpOrBranchPC[10])); + AOI222_X1_LVT i_0_40 (.A1(n_71), .A2(n_0_99), .B1(n_0_91), .B2(n_40), + .C1(n_9), .C2(n_0_90), .ZN(n_0_45)); + NAND2_X1_LVT i_0_41 (.A1(Illegal), .A2(CurrentPC[9]), .ZN(n_0_46)); + NAND2_X1_LVT i_0_39 (.A1(n_0_45), .A2(n_0_46), .ZN(JumpOrBranchPC[9])); + AOI222_X1_LVT i_0_37 (.A1(n_70), .A2(n_0_99), .B1(n_0_91), .B2(n_39), + .C1(n_8), .C2(n_0_90), .ZN(n_0_43)); + NAND2_X1_LVT i_0_38 (.A1(Illegal), .A2(CurrentPC[8]), .ZN(n_0_44)); + NAND2_X1_LVT i_0_36 (.A1(n_0_43), .A2(n_0_44), .ZN(JumpOrBranchPC[8])); + AOI222_X1_LVT i_0_34 (.A1(n_69), .A2(n_0_99), .B1(n_0_91), .B2(n_38), + .C1(n_7), .C2(n_0_90), .ZN(n_0_41)); + NAND2_X1_LVT i_0_35 (.A1(Illegal), .A2(CurrentPC[7]), .ZN(n_0_42)); + NAND2_X1_LVT i_0_33 (.A1(n_0_41), .A2(n_0_42), .ZN(JumpOrBranchPC[7])); + AOI222_X1_LVT i_0_31 (.A1(n_68), .A2(n_0_99), .B1(n_0_91), .B2(n_37), + .C1(n_6), .C2(n_0_90), .ZN(n_0_39)); + NAND2_X1_LVT i_0_32 (.A1(Illegal), .A2(CurrentPC[6]), .ZN(n_0_40)); + NAND2_X1_LVT i_0_30 (.A1(n_0_39), .A2(n_0_40), .ZN(JumpOrBranchPC[6])); + AOI222_X1_LVT i_0_28 (.A1(n_67), .A2(n_0_99), .B1(n_0_91), .B2(n_36), + .C1(n_5), .C2(n_0_90), .ZN(n_0_37)); + NAND2_X1_LVT i_0_29 (.A1(Illegal), .A2(CurrentPC[5]), .ZN(n_0_38)); + NAND2_X1_LVT i_0_27 (.A1(n_0_37), .A2(n_0_38), .ZN(JumpOrBranchPC[5])); + AOI222_X1_LVT i_0_25 (.A1(n_66), .A2(n_0_99), .B1(n_0_91), .B2(n_35), + .C1(n_4), .C2(n_0_90), .ZN(n_0_35)); + NAND2_X1_LVT i_0_26 (.A1(Illegal), .A2(CurrentPC[4]), .ZN(n_0_36)); + NAND2_X1_LVT i_0_24 (.A1(n_0_35), .A2(n_0_36), .ZN(JumpOrBranchPC[4])); + AOI222_X1_LVT i_0_22 (.A1(n_65), .A2(n_0_99), .B1(n_0_91), .B2(n_34), + .C1(n_3), .C2(n_0_90), .ZN(n_0_33)); + NAND2_X1_LVT i_0_23 (.A1(Illegal), .A2(CurrentPC[3]), .ZN(n_0_34)); + NAND2_X1_LVT i_0_21 (.A1(n_0_33), .A2(n_0_34), .ZN(JumpOrBranchPC[3])); + AOI222_X1_LVT i_0_19 (.A1(n_64), .A2(n_0_99), .B1(n_0_91), .B2(n_33), + .C1(n_2), .C2(n_0_90), .ZN(n_0_31)); + NAND2_X1_LVT i_0_20 (.A1(Illegal), .A2(CurrentPC[2]), .ZN(n_0_32)); + NAND2_X1_LVT i_0_18 (.A1(n_0_31), .A2(n_0_32), .ZN(JumpOrBranchPC[2])); + AOI222_X1_LVT i_0_16 (.A1(n_63), .A2(n_0_99), .B1(n_0_91), .B2(n_32), + .C1(n_1), .C2(n_0_90), .ZN(n_0_29)); + NAND2_X1_LVT i_0_17 (.A1(Illegal), .A2(CurrentPC[1]), .ZN(n_0_30)); + NAND2_X1_LVT i_0_15 (.A1(n_0_29), .A2(n_0_30), .ZN(JumpOrBranchPC[1])); + NOR2_X1_LVT i_0_112 (.A1(n_0_232), .A2(n_0_238), .ZN(n_0_94)); + OAI221_X1_LVT i_0_14 (.A(n_0_94), .B1(n_0_225), .B2(Instruction[2]), .C1( + Instruction[6]), .C2(n_0_239), .ZN(n_0_28)); + AND2_X1_LVT i_0_13 (.A1(n_0_28), .A2(CurrentPC[0]), .ZN(JumpOrBranchPC[0])); + NOR2_X1_LVT i_0_221 (.A1(Instruction[13]), .A2(Instruction[14]), .ZN(n_0_166)); + NOR3_X1_LVT i_0_293 (.A1(n_0_241), .A2(n_0_234), .A3(Instruction[3]), + .ZN(n_0_206)); + AND2_X1_LVT i_0_292 (.A1(n_0_206), .A2(n_0_244), .ZN(n_0_205)); + NOR3_X1_LVT i_0_330 (.A1(n_0_248), .A2(n_0_244), .A3(Instruction[4]), + .ZN(n_0_226)); + AOI21_X1_LVT i_0_121 (.A(n_0_205), .B1(n_0_226), .B2(n_0_237), .ZN(n_0_100)); + AND2_X1_LVT i_0_120 (.A1(Instruction[14]), .A2(n_0_100), .ZN(aluOp[2])); + OAI33_X1_LVT i_0_119 (.A1(n_0_205), .A2(n_0_247), .A3(n_0_224), .B1( + Instruction[2]), .B2(n_0_238), .B3(n_0_225), .ZN(aluOp[1])); + AOI22_X1_LVT i_0_117 (.A1(Instruction[12]), .A2(n_0_100), .B1(n_0_99), + .B2(Instruction[13]), .ZN(n_0_98)); + INV_X1_LVT i_0_116 (.A(n_0_98), .ZN(aluOp[0])); + OR2_X1_LVT i_0_327 (.A1(n_0_238), .A2(n_0_234), .ZN(n_0_223)); + NOR4_X1_LVT i_0_125 (.A1(Instruction[28]), .A2(Instruction[27]), .A3( + Instruction[26]), .A4(Instruction[25]), .ZN(n_0_103)); + INV_X1_LVT i_0_347 (.A(Instruction[30]), .ZN(n_0_242)); + NOR4_X1_LVT i_0_124 (.A1(Instruction[13]), .A2(n_0_242), .A3(Instruction[29]), + .A4(Instruction[31]), .ZN(n_0_102)); + NAND2_X1_LVT i_0_123 (.A1(n_0_103), .A2(n_0_102), .ZN(n_0_101)); + NOR3_X1_LVT i_0_127 (.A1(n_0_244), .A2(Instruction[12]), .A3(Instruction[14]), + .ZN(n_0_105)); + AOI21_X1_LVT i_0_126 (.A(n_0_105), .B1(Instruction[12]), .B2(Instruction[14]), + .ZN(n_0_104)); + NOR4_X1_LVT i_0_122 (.A1(n_0_223), .A2(n_0_101), .A3(n_0_104), .A4( + Instruction[2]), .ZN(aluNegAr)); + OR3_X1_LVT i_0_325 (.A1(n_0_228), .A2(Instruction[4]), .A3(Instruction[6]), + .ZN(n_0_222)); + NOR2_X1_LVT i_0_321 (.A1(n_0_222), .A2(Instruction[5]), .ZN(n_0_221)); + NOR3_X1_LVT i_0_224 (.A1(n_0_224), .A2(n_0_221), .A3(n_0_206), .ZN(n_0_169)); + NOR3_X1_LVT i_0_129 (.A1(n_0_234), .A2(Instruction[3]), .A3(Instruction[5]), + .ZN(n_0_106)); + NOR3_X1_LVT i_0_128 (.A1(n_0_226), .A2(n_0_169), .A3(n_0_106), .ZN(aluBypass)); + AOI22_X1_LVT i_0_223 (.A1(CurrentPC[31]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[31]), .ZN(n_0_168)); + NOR3_X1_LVT i_0_219 (.A1(n_0_247), .A2(n_0_222), .A3(Instruction[5]), + .ZN(n_0_164)); + AOI22_X1_LVT i_0_218 (.A1(RRs1[31]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[31]), .ZN(n_0_163)); + MUX2_X1_LVT i_0_222 (.A(RData[7]), .B(RData[15]), .S(Instruction[12]), + .Z(n_0_167)); + NAND3_X1_LVT i_0_220 (.A1(n_0_221), .A2(n_0_167), .A3(n_0_166), .ZN(n_0_165)); + NAND3_X1_LVT i_0_217 (.A1(n_0_168), .A2(n_0_163), .A3(n_0_165), .ZN(op1[31])); + AOI22_X1_LVT i_0_216 (.A1(RRs1[30]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[30]), .ZN(n_0_162)); + AOI22_X1_LVT i_0_215 (.A1(CurrentPC[30]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[30]), .ZN(n_0_161)); + NAND3_X1_LVT i_0_214 (.A1(n_0_162), .A2(n_0_161), .A3(n_0_165), .ZN(op1[30])); + AOI22_X1_LVT i_0_213 (.A1(RRs1[29]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[29]), .ZN(n_0_160)); + AOI22_X1_LVT i_0_212 (.A1(CurrentPC[29]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[29]), .ZN(n_0_159)); + NAND3_X1_LVT i_0_211 (.A1(n_0_160), .A2(n_0_159), .A3(n_0_165), .ZN(op1[29])); + AOI22_X1_LVT i_0_210 (.A1(RRs1[28]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[28]), .ZN(n_0_158)); + AOI22_X1_LVT i_0_209 (.A1(CurrentPC[28]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[28]), .ZN(n_0_157)); + NAND3_X1_LVT i_0_208 (.A1(n_0_158), .A2(n_0_157), .A3(n_0_165), .ZN(op1[28])); + AOI22_X1_LVT i_0_207 (.A1(RRs1[27]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[27]), .ZN(n_0_156)); + AOI22_X1_LVT i_0_206 (.A1(CurrentPC[27]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[27]), .ZN(n_0_155)); + NAND3_X1_LVT i_0_205 (.A1(n_0_156), .A2(n_0_155), .A3(n_0_165), .ZN(op1[27])); + AOI22_X1_LVT i_0_204 (.A1(RRs1[26]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[26]), .ZN(n_0_154)); + AOI22_X1_LVT i_0_203 (.A1(CurrentPC[26]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[26]), .ZN(n_0_153)); + NAND3_X1_LVT i_0_202 (.A1(n_0_154), .A2(n_0_153), .A3(n_0_165), .ZN(op1[26])); + AOI22_X1_LVT i_0_201 (.A1(RRs1[25]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[25]), .ZN(n_0_152)); + AOI22_X1_LVT i_0_200 (.A1(CurrentPC[25]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[25]), .ZN(n_0_151)); + NAND3_X1_LVT i_0_199 (.A1(n_0_152), .A2(n_0_151), .A3(n_0_165), .ZN(op1[25])); + AOI22_X1_LVT i_0_198 (.A1(RRs1[24]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[24]), .ZN(n_0_150)); + AOI22_X1_LVT i_0_197 (.A1(CurrentPC[24]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[24]), .ZN(n_0_149)); + NAND3_X1_LVT i_0_196 (.A1(n_0_150), .A2(n_0_149), .A3(n_0_165), .ZN(op1[24])); + AOI22_X1_LVT i_0_195 (.A1(RRs1[23]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[23]), .ZN(n_0_148)); + AOI22_X1_LVT i_0_194 (.A1(CurrentPC[23]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[23]), .ZN(n_0_147)); + NAND3_X1_LVT i_0_193 (.A1(n_0_148), .A2(n_0_147), .A3(n_0_165), .ZN(op1[23])); + AOI22_X1_LVT i_0_192 (.A1(RRs1[22]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[22]), .ZN(n_0_146)); + AOI22_X1_LVT i_0_191 (.A1(CurrentPC[22]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[22]), .ZN(n_0_145)); + NAND3_X1_LVT i_0_190 (.A1(n_0_146), .A2(n_0_145), .A3(n_0_165), .ZN(op1[22])); + AOI22_X1_LVT i_0_189 (.A1(RRs1[21]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[21]), .ZN(n_0_144)); + AOI22_X1_LVT i_0_188 (.A1(CurrentPC[21]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[21]), .ZN(n_0_143)); + NAND3_X1_LVT i_0_187 (.A1(n_0_144), .A2(n_0_143), .A3(n_0_165), .ZN(op1[21])); + AOI22_X1_LVT i_0_186 (.A1(RRs1[20]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[20]), .ZN(n_0_142)); + AOI22_X1_LVT i_0_185 (.A1(CurrentPC[20]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[20]), .ZN(n_0_141)); + NAND3_X1_LVT i_0_184 (.A1(n_0_142), .A2(n_0_141), .A3(n_0_165), .ZN(op1[20])); + AOI22_X1_LVT i_0_183 (.A1(RRs1[19]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[19]), .ZN(n_0_140)); + AOI22_X1_LVT i_0_182 (.A1(CurrentPC[19]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[19]), .ZN(n_0_139)); + NAND3_X1_LVT i_0_181 (.A1(n_0_140), .A2(n_0_139), .A3(n_0_165), .ZN(op1[19])); + AOI22_X1_LVT i_0_180 (.A1(RRs1[18]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[18]), .ZN(n_0_138)); + AOI22_X1_LVT i_0_179 (.A1(CurrentPC[18]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[18]), .ZN(n_0_137)); + NAND3_X1_LVT i_0_178 (.A1(n_0_138), .A2(n_0_137), .A3(n_0_165), .ZN(op1[18])); + AOI22_X1_LVT i_0_177 (.A1(RRs1[17]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[17]), .ZN(n_0_136)); + AOI22_X1_LVT i_0_176 (.A1(CurrentPC[17]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[17]), .ZN(n_0_135)); + NAND3_X1_LVT i_0_175 (.A1(n_0_136), .A2(n_0_135), .A3(n_0_165), .ZN(op1[17])); + AOI22_X1_LVT i_0_174 (.A1(RRs1[16]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[16]), .ZN(n_0_134)); + AOI22_X1_LVT i_0_173 (.A1(CurrentPC[16]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[16]), .ZN(n_0_133)); + NAND3_X1_LVT i_0_172 (.A1(n_0_134), .A2(n_0_133), .A3(n_0_165), .ZN(op1[16])); + AOI222_X1_LVT i_0_169 (.A1(CurrentPC[15]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[15]), .C1(n_0_169), .C2(RRs1[15]), .ZN(n_0_130)); + INV_X1_LVT i_0_353 (.A(Instruction[12]), .ZN(n_0_246)); + AOI211_X1_LVT i_0_171 (.A(Instruction[5]), .B(n_0_222), .C1(n_0_247), + .C2(n_0_246), .ZN(n_0_132)); + OAI211_X1_LVT i_0_170 (.A(RData[15]), .B(n_0_132), .C1(Instruction[13]), + .C2(Instruction[14]), .ZN(n_0_131)); + NAND3_X1_LVT i_0_168 (.A1(n_0_130), .A2(n_0_131), .A3(n_0_165), .ZN(op1[15])); + AOI22_X1_LVT i_0_167 (.A1(RRs1[14]), .A2(n_0_169), .B1(n_0_132), .B2( + RData[14]), .ZN(n_0_129)); + AOI22_X1_LVT i_0_166 (.A1(CurrentPC[14]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[14]), .ZN(n_0_128)); + NAND4_X1_LVT i_0_165 (.A1(n_0_221), .A2(n_0_246), .A3(RData[7]), .A4(n_0_166), + .ZN(n_0_127)); + NAND3_X1_LVT i_0_164 (.A1(n_0_129), .A2(n_0_128), .A3(n_0_127), .ZN(op1[14])); + AOI22_X1_LVT i_0_163 (.A1(RRs1[13]), .A2(n_0_169), .B1(n_0_132), .B2( + RData[13]), .ZN(n_0_126)); + AOI22_X1_LVT i_0_162 (.A1(CurrentPC[13]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[13]), .ZN(n_0_125)); + NAND3_X1_LVT i_0_161 (.A1(n_0_126), .A2(n_0_125), .A3(n_0_127), .ZN(op1[13])); + AOI22_X1_LVT i_0_160 (.A1(RRs1[12]), .A2(n_0_169), .B1(n_0_132), .B2( + RData[12]), .ZN(n_0_124)); + AOI22_X1_LVT i_0_159 (.A1(CurrentPC[12]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[12]), .ZN(n_0_123)); + NAND3_X1_LVT i_0_158 (.A1(n_0_124), .A2(n_0_123), .A3(n_0_127), .ZN(op1[12])); + AOI22_X1_LVT i_0_156 (.A1(CurrentPC[11]), .A2(n_0_224), .B1(n_0_132), + .B2(RData[11]), .ZN(n_0_121)); + NAND2_X1_LVT i_0_157 (.A1(RRs1[11]), .A2(n_0_169), .ZN(n_0_122)); + NAND3_X1_LVT i_0_155 (.A1(n_0_121), .A2(n_0_122), .A3(n_0_127), .ZN(op1[11])); + AOI22_X1_LVT i_0_153 (.A1(CurrentPC[10]), .A2(n_0_224), .B1(n_0_132), + .B2(RData[10]), .ZN(n_0_119)); + NAND2_X1_LVT i_0_154 (.A1(RRs1[10]), .A2(n_0_169), .ZN(n_0_120)); + NAND3_X1_LVT i_0_152 (.A1(n_0_119), .A2(n_0_120), .A3(n_0_127), .ZN(op1[10])); + AOI22_X1_LVT i_0_150 (.A1(CurrentPC[9]), .A2(n_0_224), .B1(n_0_132), .B2( + RData[9]), .ZN(n_0_117)); + NAND2_X1_LVT i_0_151 (.A1(RRs1[9]), .A2(n_0_169), .ZN(n_0_118)); + NAND3_X1_LVT i_0_149 (.A1(n_0_117), .A2(n_0_118), .A3(n_0_127), .ZN(op1[9])); + AOI22_X1_LVT i_0_147 (.A1(CurrentPC[8]), .A2(n_0_224), .B1(n_0_132), .B2( + RData[8]), .ZN(n_0_115)); + NAND2_X1_LVT i_0_148 (.A1(RRs1[8]), .A2(n_0_169), .ZN(n_0_116)); + NAND3_X1_LVT i_0_146 (.A1(n_0_115), .A2(n_0_116), .A3(n_0_127), .ZN(op1[8])); + AOI222_X1_LVT i_0_145 (.A1(CurrentPC[7]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[7]), .C1(n_0_169), .C2(RRs1[7]), .ZN(n_0_114)); + INV_X1_LVT i_0_144 (.A(n_0_114), .ZN(op1[7])); + AOI222_X1_LVT i_0_143 (.A1(CurrentPC[6]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[6]), .C1(n_0_169), .C2(RRs1[6]), .ZN(n_0_113)); + INV_X1_LVT i_0_142 (.A(n_0_113), .ZN(op1[6])); + AOI222_X1_LVT i_0_141 (.A1(CurrentPC[5]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[5]), .C1(n_0_169), .C2(RRs1[5]), .ZN(n_0_112)); + INV_X1_LVT i_0_140 (.A(n_0_112), .ZN(op1[5])); + AOI222_X1_LVT i_0_139 (.A1(CurrentPC[4]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[4]), .C1(n_0_169), .C2(RRs1[4]), .ZN(n_0_111)); + INV_X1_LVT i_0_138 (.A(n_0_111), .ZN(op1[4])); + AOI222_X1_LVT i_0_137 (.A1(CurrentPC[3]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[3]), .C1(n_0_169), .C2(RRs1[3]), .ZN(n_0_110)); + INV_X1_LVT i_0_136 (.A(n_0_110), .ZN(op1[3])); + AOI222_X1_LVT i_0_135 (.A1(CurrentPC[2]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[2]), .C1(n_0_169), .C2(RRs1[2]), .ZN(n_0_109)); + INV_X1_LVT i_0_134 (.A(n_0_109), .ZN(op1[2])); + AOI222_X1_LVT i_0_133 (.A1(CurrentPC[1]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[1]), .C1(n_0_169), .C2(RRs1[1]), .ZN(n_0_108)); + INV_X1_LVT i_0_132 (.A(n_0_108), .ZN(op1[1])); + AOI222_X1_LVT i_0_131 (.A1(CurrentPC[0]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[0]), .C1(n_0_169), .C2(RRs1[0]), .ZN(n_0_107)); + INV_X1_LVT i_0_130 (.A(n_0_107), .ZN(op1[0])); + NOR3_X1_LVT i_0_294 (.A1(n_0_223), .A2(Instruction[2]), .A3(Instruction[5]), + .ZN(n_0_207)); + NOR3_X1_LVT i_0_291 (.A1(n_0_224), .A2(n_0_207), .A3(n_0_205), .ZN(n_0_204)); + AOI22_X1_LVT i_0_289 (.A1(CurrentPC[31]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[31]), .ZN(n_0_202)); + NAND2_X1_LVT i_0_290 (.A1(Instruction[31]), .A2(n_0_207), .ZN(n_0_203)); + NAND2_X1_LVT i_0_288 (.A1(n_0_202), .A2(n_0_203), .ZN(op2[31])); + AOI22_X1_LVT i_0_287 (.A1(CurrentPC[30]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[30]), .ZN(n_0_201)); + NAND2_X1_LVT i_0_286 (.A1(n_0_201), .A2(n_0_203), .ZN(op2[30])); + AOI22_X1_LVT i_0_285 (.A1(CurrentPC[29]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[29]), .ZN(n_0_200)); + NAND2_X1_LVT i_0_284 (.A1(n_0_200), .A2(n_0_203), .ZN(op2[29])); + AOI22_X1_LVT i_0_283 (.A1(CurrentPC[28]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[28]), .ZN(n_0_199)); + NAND2_X1_LVT i_0_282 (.A1(n_0_199), .A2(n_0_203), .ZN(op2[28])); + AOI22_X1_LVT i_0_281 (.A1(CurrentPC[27]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[27]), .ZN(n_0_198)); + NAND2_X1_LVT i_0_280 (.A1(n_0_198), .A2(n_0_203), .ZN(op2[27])); + AOI22_X1_LVT i_0_279 (.A1(CurrentPC[26]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[26]), .ZN(n_0_197)); + NAND2_X1_LVT i_0_278 (.A1(n_0_197), .A2(n_0_203), .ZN(op2[26])); + AOI22_X1_LVT i_0_277 (.A1(CurrentPC[25]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[25]), .ZN(n_0_196)); + NAND2_X1_LVT i_0_276 (.A1(n_0_196), .A2(n_0_203), .ZN(op2[25])); + AOI22_X1_LVT i_0_275 (.A1(CurrentPC[24]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[24]), .ZN(n_0_195)); + NAND2_X1_LVT i_0_274 (.A1(n_0_195), .A2(n_0_203), .ZN(op2[24])); + AOI22_X1_LVT i_0_273 (.A1(CurrentPC[23]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[23]), .ZN(n_0_194)); + NAND2_X1_LVT i_0_272 (.A1(n_0_194), .A2(n_0_203), .ZN(op2[23])); + AOI22_X1_LVT i_0_271 (.A1(CurrentPC[22]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[22]), .ZN(n_0_193)); + NAND2_X1_LVT i_0_270 (.A1(n_0_193), .A2(n_0_203), .ZN(op2[22])); + AOI22_X1_LVT i_0_269 (.A1(CurrentPC[21]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[21]), .ZN(n_0_192)); + NAND2_X1_LVT i_0_268 (.A1(n_0_192), .A2(n_0_203), .ZN(op2[21])); + AOI22_X1_LVT i_0_267 (.A1(CurrentPC[20]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[20]), .ZN(n_0_191)); + NAND2_X1_LVT i_0_266 (.A1(n_0_191), .A2(n_0_203), .ZN(op2[20])); + AOI22_X1_LVT i_0_265 (.A1(CurrentPC[19]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[19]), .ZN(n_0_190)); + NAND2_X1_LVT i_0_264 (.A1(n_0_190), .A2(n_0_203), .ZN(op2[19])); + AOI22_X1_LVT i_0_263 (.A1(CurrentPC[18]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[18]), .ZN(n_0_189)); + NAND2_X1_LVT i_0_262 (.A1(n_0_189), .A2(n_0_203), .ZN(op2[18])); + AOI22_X1_LVT i_0_261 (.A1(CurrentPC[17]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[17]), .ZN(n_0_188)); + NAND2_X1_LVT i_0_260 (.A1(n_0_188), .A2(n_0_203), .ZN(op2[17])); + AOI22_X1_LVT i_0_259 (.A1(CurrentPC[16]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[16]), .ZN(n_0_187)); + NAND2_X1_LVT i_0_258 (.A1(n_0_187), .A2(n_0_203), .ZN(op2[16])); + AOI22_X1_LVT i_0_257 (.A1(CurrentPC[15]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[15]), .ZN(n_0_186)); + NAND2_X1_LVT i_0_256 (.A1(n_0_186), .A2(n_0_203), .ZN(op2[15])); + AOI22_X1_LVT i_0_255 (.A1(CurrentPC[14]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[14]), .ZN(n_0_185)); + NAND2_X1_LVT i_0_254 (.A1(n_0_185), .A2(n_0_203), .ZN(op2[14])); + AOI22_X1_LVT i_0_253 (.A1(CurrentPC[13]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[13]), .ZN(n_0_184)); + NAND2_X1_LVT i_0_252 (.A1(n_0_184), .A2(n_0_203), .ZN(op2[13])); + AOI22_X1_LVT i_0_251 (.A1(CurrentPC[12]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[12]), .ZN(n_0_183)); + NAND2_X1_LVT i_0_250 (.A1(n_0_183), .A2(n_0_203), .ZN(op2[12])); + AOI22_X1_LVT i_0_249 (.A1(CurrentPC[11]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[11]), .ZN(n_0_182)); + NAND2_X1_LVT i_0_248 (.A1(n_0_182), .A2(n_0_203), .ZN(op2[11])); + AOI222_X1_LVT i_0_247 (.A1(Instruction[30]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[10]), .C1(n_0_204), .C2(RRs2[10]), .ZN(n_0_181)); + INV_X1_LVT i_0_246 (.A(n_0_181), .ZN(op2[10])); + AOI222_X1_LVT i_0_245 (.A1(Instruction[29]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[9]), .C1(n_0_204), .C2(RRs2[9]), .ZN(n_0_180)); + INV_X1_LVT i_0_244 (.A(n_0_180), .ZN(op2[9])); + AOI222_X1_LVT i_0_243 (.A1(Instruction[28]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[8]), .C1(n_0_204), .C2(RRs2[8]), .ZN(n_0_179)); + INV_X1_LVT i_0_242 (.A(n_0_179), .ZN(op2[8])); + AOI222_X1_LVT i_0_241 (.A1(Instruction[27]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[7]), .C1(n_0_204), .C2(RRs2[7]), .ZN(n_0_178)); + INV_X1_LVT i_0_240 (.A(n_0_178), .ZN(op2[7])); + AOI222_X1_LVT i_0_239 (.A1(Instruction[26]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[6]), .C1(n_0_204), .C2(RRs2[6]), .ZN(n_0_177)); + INV_X1_LVT i_0_238 (.A(n_0_177), .ZN(op2[6])); + AOI222_X1_LVT i_0_237 (.A1(Instruction[25]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[5]), .C1(n_0_204), .C2(RRs2[5]), .ZN(n_0_176)); + INV_X1_LVT i_0_236 (.A(n_0_176), .ZN(op2[5])); + AOI222_X1_LVT i_0_235 (.A1(Instruction[24]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[4]), .C1(n_0_204), .C2(RRs2[4]), .ZN(n_0_175)); + INV_X1_LVT i_0_234 (.A(n_0_175), .ZN(op2[4])); + AOI222_X1_LVT i_0_233 (.A1(Instruction[23]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[3]), .C1(n_0_204), .C2(RRs2[3]), .ZN(n_0_174)); + INV_X1_LVT i_0_232 (.A(n_0_174), .ZN(op2[3])); + AOI22_X1_LVT i_0_230 (.A1(Instruction[22]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[2]), .ZN(n_0_172)); + OAI21_X1_LVT i_0_231 (.A(RRs2[2]), .B1(n_0_223), .B2(Instruction[5]), + .ZN(n_0_173)); + NAND3_X1_LVT i_0_229 (.A1(n_0_172), .A2(n_0_173), .A3(n_0_249), .ZN(op2[2])); + AOI222_X1_LVT i_0_228 (.A1(Instruction[21]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[1]), .C1(n_0_204), .C2(RRs2[1]), .ZN(n_0_171)); + INV_X1_LVT i_0_227 (.A(n_0_171), .ZN(op2[1])); + AOI222_X1_LVT i_0_226 (.A1(Instruction[20]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[0]), .C1(n_0_204), .C2(RRs2[0]), .ZN(n_0_170)); + INV_X1_LVT i_0_225 (.A(n_0_170), .ZN(op2[0])); + alu theALU (.aluOp(aluOp), .aluNegAr(aluNegAr), .aluBypass(aluBypass), + .op1(op1), .op2(op2), .result(WRd), .eqFlag(eqFlag)); + XNOR2_X1_LVT i_0_115 (.A(Instruction[12]), .B(eqFlag), .ZN(n_0_97)); + XNOR2_X1_LVT i_0_114 (.A(Instruction[12]), .B(WRd[0]), .ZN(n_0_96)); + AOI22_X1_LVT i_0_113 (.A1(n_0_166), .A2(n_0_97), .B1(n_0_96), .B2( + Instruction[14]), .ZN(n_0_95)); + AOI22_X1_LVT i_0_111 (.A1(Instruction[6]), .A2(n_0_95), .B1(Instruction[2]), + .B2(n_0_245), .ZN(n_0_93)); + NAND2_X1_LVT i_0_110 (.A1(n_0_94), .A2(n_0_93), .ZN(JumpOrBranch)); + INV_X1_LVT i_0_349 (.A(Instruction[31]), .ZN(n_0_0)); + INV_X1_LVT i_0_348 (.A(RRs1[12]), .ZN(n_0_1)); + HA_X1_LVT i_0_0 (.A(Instruction[7]), .B(RRs1[0]), .CO(n_0_2), .S(n_0_15)); + FA_X1_LVT i_0_1 (.A(Instruction[8]), .B(RRs1[1]), .CI(n_0_2), .CO(n_0_3), + .S(n_0_16)); + FA_X1_LVT i_0_2 (.A(Instruction[9]), .B(RRs1[2]), .CI(n_0_3), .CO(n_0_4), + .S(n_0_17)); + FA_X1_LVT i_0_3 (.A(Instruction[10]), .B(RRs1[3]), .CI(n_0_4), .CO(n_0_5), + .S(n_0_18)); + FA_X1_LVT i_0_4 (.A(Instruction[11]), .B(RRs1[4]), .CI(n_0_5), .CO(n_0_6), + .S(n_0_19)); + FA_X1_LVT i_0_5 (.A(Instruction[25]), .B(RRs1[5]), .CI(n_0_6), .CO(n_0_7), + .S(n_0_20)); + FA_X1_LVT i_0_6 (.A(Instruction[26]), .B(RRs1[6]), .CI(n_0_7), .CO(n_0_8), + .S(n_0_21)); + FA_X1_LVT i_0_7 (.A(Instruction[27]), .B(RRs1[7]), .CI(n_0_8), .CO(n_0_9), + .S(n_0_22)); + FA_X1_LVT i_0_8 (.A(Instruction[28]), .B(RRs1[8]), .CI(n_0_9), .CO(n_0_10), + .S(n_0_23)); + FA_X1_LVT i_0_9 (.A(Instruction[29]), .B(RRs1[9]), .CI(n_0_10), .CO(n_0_11), + .S(n_0_24)); + FA_X1_LVT i_0_10 (.A(Instruction[30]), .B(RRs1[10]), .CI(n_0_11), .CO(n_0_12), + .S(n_0_25)); + FA_X1_LVT i_0_11 (.A(RRs1[11]), .B(Instruction[31]), .CI(n_0_12), .CO(n_0_13), + .S(n_0_26)); + FA_X1_LVT i_0_12 (.A(n_0_0), .B(n_0_1), .CI(n_0_13), .CO(n_0_14), .S(n_0_27)); + NOR2_X1_LVT i_0_322 (.A1(n_0_244), .A2(n_0_222), .ZN(WrMem)); + AOI22_X1_LVT i_0_320 (.A1(n_0_27), .A2(WrMem), .B1(n_0_221), .B2(n_12), + .ZN(n_0_220)); + INV_X1_LVT i_0_319 (.A(n_0_220), .ZN(DAddr[12])); + AOI22_X1_LVT i_0_318 (.A1(n_0_26), .A2(WrMem), .B1(n_0_221), .B2(n_11), + .ZN(n_0_219)); + INV_X1_LVT i_0_317 (.A(n_0_219), .ZN(DAddr[11])); + AOI22_X1_LVT i_0_316 (.A1(n_0_25), .A2(WrMem), .B1(n_0_221), .B2(n_10), + .ZN(n_0_218)); + INV_X1_LVT i_0_315 (.A(n_0_218), .ZN(DAddr[10])); + AOI22_X1_LVT i_0_314 (.A1(n_0_24), .A2(WrMem), .B1(n_0_221), .B2(n_9), + .ZN(n_0_217)); + INV_X1_LVT i_0_313 (.A(n_0_217), .ZN(DAddr[9])); + AOI22_X1_LVT i_0_312 (.A1(n_0_23), .A2(WrMem), .B1(n_0_221), .B2(n_8), + .ZN(n_0_216)); + INV_X1_LVT i_0_311 (.A(n_0_216), .ZN(DAddr[8])); + AOI22_X1_LVT i_0_310 (.A1(n_0_22), .A2(WrMem), .B1(n_0_221), .B2(n_7), + .ZN(n_0_215)); + INV_X1_LVT i_0_309 (.A(n_0_215), .ZN(DAddr[7])); + AOI22_X1_LVT i_0_308 (.A1(n_0_21), .A2(WrMem), .B1(n_0_221), .B2(n_6), + .ZN(n_0_214)); + INV_X1_LVT i_0_307 (.A(n_0_214), .ZN(DAddr[6])); + AOI22_X1_LVT i_0_306 (.A1(n_0_20), .A2(WrMem), .B1(n_0_221), .B2(n_5), + .ZN(n_0_213)); + INV_X1_LVT i_0_305 (.A(n_0_213), .ZN(DAddr[5])); + AOI22_X1_LVT i_0_304 (.A1(n_0_19), .A2(WrMem), .B1(n_0_221), .B2(n_4), + .ZN(n_0_212)); + INV_X1_LVT i_0_303 (.A(n_0_212), .ZN(DAddr[4])); + AOI22_X1_LVT i_0_302 (.A1(n_0_18), .A2(WrMem), .B1(n_0_221), .B2(n_3), + .ZN(n_0_211)); + INV_X1_LVT i_0_301 (.A(n_0_211), .ZN(DAddr[3])); + AOI22_X1_LVT i_0_300 (.A1(n_0_17), .A2(WrMem), .B1(n_0_221), .B2(n_2), + .ZN(n_0_210)); + INV_X1_LVT i_0_299 (.A(n_0_210), .ZN(DAddr[2])); + AOI22_X1_LVT i_0_298 (.A1(n_0_16), .A2(WrMem), .B1(n_0_221), .B2(n_1), + .ZN(n_0_209)); + INV_X1_LVT i_0_297 (.A(n_0_209), .ZN(DAddr[1])); + AOI22_X1_LVT i_0_296 (.A1(n_0_15), .A2(WrMem), .B1(n_0_221), .B2(n_0), + .ZN(n_0_208)); + INV_X1_LVT i_0_295 (.A(n_0_208), .ZN(DAddr[0])); + OR2_X1_LVT i_0_324 (.A1(n_0_222), .A2(Instruction[13]), .ZN(DWidth[1])); + NOR2_X1_LVT i_0_323 (.A1(n_0_246), .A2(n_0_222), .ZN(DWidth[0])); + NAND3_X1_LVT i_0_331 (.A1(n_0_248), .A2(n_0_244), .A3(n_0_236), .ZN(n_0_227)); + OAI211_X1_LVT i_0_326 (.A(n_0_249), .B(n_0_223), .C1(n_0_228), .C2(n_0_227), + .ZN(WrReg)); +endmodule + +module cpu(led, btn, clk_25mhz, scan_en); + output [7:0]led; + input [6:0]btn; + input clk_25mhz; + input scan_en; + + wire [31:0]Instruction; + wire [31:0]RData; + wire [31:0]RRs2; + wire [31:0]RRs1; + wire WrReg; + wire [31:0]WRd; + wire [1:0]DWidth; + wire [31:0]DAddr; + wire JumpOrBranch; + wire [31:0]JumpOrBranchPC; + wire thePC_n_0; + wire thePC_n_1; + wire thePC_n_2; + wire thePC_n_3; + wire thePC_n_4; + wire thePC_n_5; + wire thePC_n_6; + wire thePC_n_7; + wire thePC_n_8; + wire thePC_n_9; + wire thePC_n_10; + wire thePC_n_11; + wire thePC_n_12; + wire thePC_n_13; + wire thePC_n_14; + wire thePC_n_15; + wire thePC_n_16; + wire thePC_n_17; + wire thePC_n_18; + wire thePC_n_19; + wire thePC_n_20; + wire thePC_n_21; + wire thePC_n_22; + wire thePC_n_23; + wire thePC_n_24; + wire thePC_n_25; + wire thePC_n_26; + wire thePC_n_27; + wire thePC_n_28; + wire thePC_n_29; + wire [31:0]CurrentPC; + wire thePC_n_30; + wire n_0_0_0; + wire thePC_n_31; + wire n_0_0_1; + wire thePC_n_32; + wire thePC_n_33; + wire thePC_n_34; + wire thePC_n_35; + wire thePC_n_36; + wire thePC_n_37; + wire thePC_n_38; + wire thePC_n_39; + wire thePC_n_40; + wire thePC_n_41; + wire thePC_n_42; + wire thePC_n_43; + wire n_0_0_2; + wire thePC_n_44; + wire n_0_0_3; + wire thePC_n_45; + wire n_0_0_4; + wire thePC_n_46; + wire n_0_0_5; + wire thePC_n_47; + wire n_0_0_6; + wire thePC_n_48; + wire n_0_0_7; + wire thePC_n_49; + wire n_0_0_8; + wire thePC_n_50; + wire n_0_0_9; + wire thePC_n_51; + wire n_0_0_10; + wire thePC_n_52; + wire n_0_0_11; + wire thePC_n_53; + wire n_0_0_12; + wire thePC_n_54; + wire n_0_0_13; + wire thePC_n_55; + wire n_0_0_14; + wire thePC_n_56; + wire n_0_0_15; + wire thePC_n_57; + wire n_0_0_16; + wire thePC_n_58; + wire n_0_0_17; + wire thePC_n_59; + wire n_0_0_18; + wire thePC_n_60; + wire n_0_0_19; + wire thePC_n_61; + wire n_0_0_20; + wire n_0_0_21; + wire n_0_0_22; + wire [31:0]NextPC; + wire reset; + + AND2_X1_LVT i_0_0_54 (.A1(JumpOrBranch), .A2(btn[0]), .ZN(n_0_0_22)); + INV_X1_LVT i_0_0_66 (.A(btn[0]), .ZN(reset)); + NOR2_X1_LVT i_0_0_53 (.A1(reset), .A2(JumpOrBranch), .ZN(n_0_0_21)); + AOI22_X1_LVT i_0_0_50 (.A1(JumpOrBranchPC[30]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_28), .ZN(n_0_0_19)); + INV_X1_LVT i_0_0_49 (.A(n_0_0_19), .ZN(thePC_n_60)); + SDFF_X1_LVT \thePC_CurrentPC_reg[30] (.D(thePC_n_60), .SE(1'b0), .SI( + CurrentPC[30]), .CK(clk_25mhz), .Q(CurrentPC[30]), .QN()); + AOI22_X1_LVT i_0_0_48 (.A1(JumpOrBranchPC[29]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_27), .ZN(n_0_0_18)); + INV_X1_LVT i_0_0_47 (.A(n_0_0_18), .ZN(thePC_n_59)); + SDFF_X1_LVT \thePC_CurrentPC_reg[29] (.D(thePC_n_59), .SE(1'b0), .SI( + CurrentPC[29]), .CK(clk_25mhz), .Q(CurrentPC[29]), .QN()); + AOI22_X1_LVT i_0_0_46 (.A1(JumpOrBranchPC[28]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_26), .ZN(n_0_0_17)); + INV_X1_LVT i_0_0_45 (.A(n_0_0_17), .ZN(thePC_n_58)); + SDFF_X1_LVT \thePC_CurrentPC_reg[28] (.D(thePC_n_58), .SE(1'b0), .SI( + CurrentPC[28]), .CK(clk_25mhz), .Q(CurrentPC[28]), .QN()); + AOI22_X1_LVT i_0_0_44 (.A1(JumpOrBranchPC[27]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_25), .ZN(n_0_0_16)); + INV_X1_LVT i_0_0_43 (.A(n_0_0_16), .ZN(thePC_n_57)); + SDFF_X1_LVT \thePC_CurrentPC_reg[27] (.D(thePC_n_57), .SE(1'b0), .SI( + CurrentPC[27]), .CK(clk_25mhz), .Q(CurrentPC[27]), .QN()); + AOI22_X1_LVT i_0_0_42 (.A1(JumpOrBranchPC[26]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_24), .ZN(n_0_0_15)); + INV_X1_LVT i_0_0_41 (.A(n_0_0_15), .ZN(thePC_n_56)); + SDFF_X1_LVT \thePC_CurrentPC_reg[26] (.D(thePC_n_56), .SE(1'b0), .SI( + CurrentPC[26]), .CK(clk_25mhz), .Q(CurrentPC[26]), .QN()); + AOI22_X1_LVT i_0_0_40 (.A1(JumpOrBranchPC[25]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_23), .ZN(n_0_0_14)); + INV_X1_LVT i_0_0_39 (.A(n_0_0_14), .ZN(thePC_n_55)); + SDFF_X1_LVT \thePC_CurrentPC_reg[25] (.D(thePC_n_55), .SE(1'b0), .SI( + CurrentPC[25]), .CK(clk_25mhz), .Q(CurrentPC[25]), .QN()); + AOI22_X1_LVT i_0_0_38 (.A1(JumpOrBranchPC[24]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_22), .ZN(n_0_0_13)); + INV_X1_LVT i_0_0_37 (.A(n_0_0_13), .ZN(thePC_n_54)); + SDFF_X1_LVT \thePC_CurrentPC_reg[24] (.D(thePC_n_54), .SE(1'b0), .SI( + CurrentPC[24]), .CK(clk_25mhz), .Q(CurrentPC[24]), .QN()); + AOI22_X1_LVT i_0_0_36 (.A1(JumpOrBranchPC[23]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_21), .ZN(n_0_0_12)); + INV_X1_LVT i_0_0_35 (.A(n_0_0_12), .ZN(thePC_n_53)); + SDFF_X1_LVT \thePC_CurrentPC_reg[23] (.D(thePC_n_53), .SE(1'b0), .SI( + CurrentPC[23]), .CK(clk_25mhz), .Q(CurrentPC[23]), .QN()); + AOI22_X1_LVT i_0_0_34 (.A1(JumpOrBranchPC[22]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_20), .ZN(n_0_0_11)); + INV_X1_LVT i_0_0_33 (.A(n_0_0_11), .ZN(thePC_n_52)); + SDFF_X1_LVT \thePC_CurrentPC_reg[22] (.D(thePC_n_52), .SE(1'b0), .SI( + CurrentPC[22]), .CK(clk_25mhz), .Q(CurrentPC[22]), .QN()); + AOI22_X1_LVT i_0_0_32 (.A1(JumpOrBranchPC[21]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_19), .ZN(n_0_0_10)); + INV_X1_LVT i_0_0_31 (.A(n_0_0_10), .ZN(thePC_n_51)); + SDFF_X1_LVT \thePC_CurrentPC_reg[21] (.D(thePC_n_51), .SE(1'b0), .SI( + CurrentPC[21]), .CK(clk_25mhz), .Q(CurrentPC[21]), .QN()); + AOI22_X1_LVT i_0_0_30 (.A1(JumpOrBranchPC[20]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_18), .ZN(n_0_0_9)); + INV_X1_LVT i_0_0_29 (.A(n_0_0_9), .ZN(thePC_n_50)); + SDFF_X1_LVT \thePC_CurrentPC_reg[20] (.D(thePC_n_50), .SE(1'b0), .SI( + CurrentPC[20]), .CK(clk_25mhz), .Q(CurrentPC[20]), .QN()); + AOI22_X1_LVT i_0_0_28 (.A1(JumpOrBranchPC[19]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_17), .ZN(n_0_0_8)); + INV_X1_LVT i_0_0_27 (.A(n_0_0_8), .ZN(thePC_n_49)); + SDFF_X1_LVT \thePC_CurrentPC_reg[19] (.D(thePC_n_49), .SE(1'b0), .SI( + CurrentPC[19]), .CK(clk_25mhz), .Q(CurrentPC[19]), .QN()); + AOI22_X1_LVT i_0_0_26 (.A1(JumpOrBranchPC[18]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_16), .ZN(n_0_0_7)); + INV_X1_LVT i_0_0_25 (.A(n_0_0_7), .ZN(thePC_n_48)); + SDFF_X1_LVT \thePC_CurrentPC_reg[18] (.D(thePC_n_48), .SE(1'b0), .SI( + CurrentPC[18]), .CK(clk_25mhz), .Q(CurrentPC[18]), .QN()); + AOI22_X1_LVT i_0_0_24 (.A1(JumpOrBranchPC[17]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_15), .ZN(n_0_0_6)); + INV_X1_LVT i_0_0_23 (.A(n_0_0_6), .ZN(thePC_n_47)); + SDFF_X1_LVT \thePC_CurrentPC_reg[17] (.D(thePC_n_47), .SE(1'b0), .SI( + CurrentPC[17]), .CK(clk_25mhz), .Q(CurrentPC[17]), .QN()); + AOI22_X1_LVT i_0_0_22 (.A1(JumpOrBranchPC[16]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_14), .ZN(n_0_0_5)); + INV_X1_LVT i_0_0_21 (.A(n_0_0_5), .ZN(thePC_n_46)); + SDFF_X1_LVT \thePC_CurrentPC_reg[16] (.D(thePC_n_46), .SE(1'b0), .SI( + CurrentPC[16]), .CK(clk_25mhz), .Q(CurrentPC[16]), .QN()); + AOI22_X1_LVT i_0_0_20 (.A1(JumpOrBranchPC[15]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_13), .ZN(n_0_0_4)); + INV_X1_LVT i_0_0_19 (.A(n_0_0_4), .ZN(thePC_n_45)); + SDFF_X1_LVT \thePC_CurrentPC_reg[15] (.D(thePC_n_45), .SE(1'b0), .SI( + CurrentPC[15]), .CK(clk_25mhz), .Q(CurrentPC[15]), .QN()); + AOI22_X1_LVT i_0_0_18 (.A1(JumpOrBranchPC[14]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_12), .ZN(n_0_0_3)); + INV_X1_LVT i_0_0_17 (.A(n_0_0_3), .ZN(thePC_n_44)); + SDFF_X1_LVT \thePC_CurrentPC_reg[14] (.D(thePC_n_44), .SE(1'b0), .SI( + CurrentPC[14]), .CK(clk_25mhz), .Q(CurrentPC[14]), .QN()); + AOI22_X1_LVT i_0_0_16 (.A1(JumpOrBranchPC[13]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_11), .ZN(n_0_0_2)); + INV_X1_LVT i_0_0_15 (.A(n_0_0_2), .ZN(thePC_n_43)); + SDFF_X1_LVT \thePC_CurrentPC_reg[13] (.D(thePC_n_43), .SE(1'b0), .SI( + CurrentPC[13]), .CK(clk_25mhz), .Q(CurrentPC[13]), .QN()); + MUX2_X1_LVT i_0_0_65 (.A(thePC_n_10), .B(JumpOrBranchPC[12]), .S(JumpOrBranch), + .Z(NextPC[12])); + AND2_X1_LVT i_0_0_14 (.A1(NextPC[12]), .A2(btn[0]), .ZN(thePC_n_42)); + SDFF_X1_LVT \thePC_CurrentPC_reg[12] (.D(thePC_n_42), .SE(1'b0), .SI( + CurrentPC[12]), .CK(clk_25mhz), .Q(CurrentPC[12]), .QN()); + MUX2_X1_LVT i_0_0_64 (.A(thePC_n_9), .B(JumpOrBranchPC[11]), .S(JumpOrBranch), + .Z(NextPC[11])); + AND2_X1_LVT i_0_0_13 (.A1(NextPC[11]), .A2(btn[0]), .ZN(thePC_n_41)); + SDFF_X1_LVT \thePC_CurrentPC_reg[11] (.D(thePC_n_41), .SE(1'b0), .SI( + CurrentPC[11]), .CK(clk_25mhz), .Q(CurrentPC[11]), .QN()); + MUX2_X1_LVT i_0_0_63 (.A(thePC_n_8), .B(JumpOrBranchPC[10]), .S(JumpOrBranch), + .Z(NextPC[10])); + AND2_X1_LVT i_0_0_12 (.A1(NextPC[10]), .A2(btn[0]), .ZN(thePC_n_40)); + SDFF_X1_LVT \thePC_CurrentPC_reg[10] (.D(thePC_n_40), .SE(1'b0), .SI( + CurrentPC[10]), .CK(clk_25mhz), .Q(CurrentPC[10]), .QN()); + MUX2_X1_LVT i_0_0_62 (.A(thePC_n_7), .B(JumpOrBranchPC[9]), .S(JumpOrBranch), + .Z(NextPC[9])); + AND2_X1_LVT i_0_0_11 (.A1(NextPC[9]), .A2(btn[0]), .ZN(thePC_n_39)); + SDFF_X1_LVT \thePC_CurrentPC_reg[9] (.D(thePC_n_39), .SE(1'b0), .SI( + CurrentPC[9]), .CK(clk_25mhz), .Q(CurrentPC[9]), .QN()); + MUX2_X1_LVT i_0_0_61 (.A(thePC_n_6), .B(JumpOrBranchPC[8]), .S(JumpOrBranch), + .Z(NextPC[8])); + AND2_X1_LVT i_0_0_10 (.A1(NextPC[8]), .A2(btn[0]), .ZN(thePC_n_38)); + SDFF_X1_LVT \thePC_CurrentPC_reg[8] (.D(thePC_n_38), .SE(1'b0), .SI( + CurrentPC[8]), .CK(clk_25mhz), .Q(CurrentPC[8]), .QN()); + AND2_X1_LVT i_0_0_9 (.A1(led[7]), .A2(btn[0]), .ZN(thePC_n_37)); + SDFF_X1_LVT \thePC_CurrentPC_reg[7] (.D(thePC_n_37), .SE(1'b0), .SI( + CurrentPC[7]), .CK(clk_25mhz), .Q(CurrentPC[7]), .QN()); + MUX2_X1_LVT i_0_0_59 (.A(thePC_n_4), .B(JumpOrBranchPC[6]), .S(JumpOrBranch), + .Z(led[6])); + AND2_X1_LVT i_0_0_8 (.A1(led[6]), .A2(btn[0]), .ZN(thePC_n_36)); + SDFF_X1_LVT \thePC_CurrentPC_reg[6] (.D(thePC_n_36), .SE(1'b0), .SI( + CurrentPC[6]), .CK(clk_25mhz), .Q(CurrentPC[6]), .QN()); + MUX2_X1_LVT i_0_0_58 (.A(thePC_n_3), .B(JumpOrBranchPC[5]), .S(JumpOrBranch), + .Z(led[5])); + AND2_X1_LVT i_0_0_7 (.A1(led[5]), .A2(btn[0]), .ZN(thePC_n_35)); + SDFF_X1_LVT \thePC_CurrentPC_reg[5] (.D(thePC_n_35), .SE(1'b0), .SI( + CurrentPC[5]), .CK(clk_25mhz), .Q(CurrentPC[5]), .QN()); + MUX2_X1_LVT i_0_0_57 (.A(thePC_n_2), .B(JumpOrBranchPC[4]), .S(JumpOrBranch), + .Z(led[4])); + AND2_X1_LVT i_0_0_6 (.A1(led[4]), .A2(btn[0]), .ZN(thePC_n_34)); + SDFF_X1_LVT \thePC_CurrentPC_reg[4] (.D(thePC_n_34), .SE(1'b0), .SI( + CurrentPC[4]), .CK(clk_25mhz), .Q(CurrentPC[4]), .QN()); + MUX2_X1_LVT i_0_0_56 (.A(thePC_n_1), .B(JumpOrBranchPC[3]), .S(JumpOrBranch), + .Z(led[3])); + AND2_X1_LVT i_0_0_5 (.A1(led[3]), .A2(btn[0]), .ZN(thePC_n_33)); + SDFF_X1_LVT \thePC_CurrentPC_reg[3] (.D(thePC_n_33), .SE(1'b0), .SI( + CurrentPC[3]), .CK(clk_25mhz), .Q(CurrentPC[3]), .QN()); + MUX2_X1_LVT i_0_0_55 (.A(thePC_n_0), .B(JumpOrBranchPC[2]), .S(JumpOrBranch), + .Z(led[2])); + AND2_X1_LVT i_0_0_4 (.A1(led[2]), .A2(btn[0]), .ZN(thePC_n_32)); + SDFF_X1_LVT \thePC_CurrentPC_reg[2] (.D(thePC_n_32), .SE(1'b0), .SI( + CurrentPC[2]), .CK(clk_25mhz), .Q(CurrentPC[2]), .QN()); + datapathS__0_65 thePC_i_0 (.CurrentPC({CurrentPC[31], CurrentPC[30], + CurrentPC[29], CurrentPC[28], CurrentPC[27], CurrentPC[26], CurrentPC[25], + CurrentPC[24], CurrentPC[23], CurrentPC[22], CurrentPC[21], CurrentPC[20], + CurrentPC[19], CurrentPC[18], CurrentPC[17], CurrentPC[16], CurrentPC[15], + CurrentPC[14], CurrentPC[13], CurrentPC[12], CurrentPC[11], CurrentPC[10], + CurrentPC[9], CurrentPC[8], CurrentPC[7], CurrentPC[6], CurrentPC[5], + CurrentPC[4], CurrentPC[3], CurrentPC[2], uc_0, uc_1}), .p_0({thePC_n_29, + thePC_n_28, thePC_n_27, thePC_n_26, thePC_n_25, thePC_n_24, thePC_n_23, + thePC_n_22, thePC_n_21, thePC_n_20, thePC_n_19, thePC_n_18, thePC_n_17, + thePC_n_16, thePC_n_15, thePC_n_14, thePC_n_13, thePC_n_12, thePC_n_11, + thePC_n_10, thePC_n_9, thePC_n_8, thePC_n_7, thePC_n_6, thePC_n_5, + thePC_n_4, thePC_n_3, thePC_n_2, thePC_n_1, thePC_n_0, uc_2, uc_3})); + AOI22_X1_LVT i_0_0_52 (.A1(JumpOrBranchPC[31]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_29), .ZN(n_0_0_20)); + INV_X1_LVT i_0_0_51 (.A(n_0_0_20), .ZN(thePC_n_61)); + SDFF_X1_LVT \thePC_CurrentPC_reg[31] (.D(thePC_n_61), .SE(1'b0), .SI( + CurrentPC[31]), .CK(clk_25mhz), .Q(CurrentPC[31]), .QN()); + AOI22_X1_LVT i_0_0_3 (.A1(JumpOrBranchPC[1]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(CurrentPC[1]), .ZN(n_0_0_1)); + INV_X1_LVT i_0_0_2 (.A(n_0_0_1), .ZN(thePC_n_31)); + SDFF_X1_LVT \thePC_CurrentPC_reg[1] (.D(thePC_n_31), .SE(1'b0), .SI( + CurrentPC[1]), .CK(clk_25mhz), .Q(CurrentPC[1]), .QN()); + AOI22_X1_LVT i_0_0_1 (.A1(JumpOrBranchPC[0]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(CurrentPC[0]), .ZN(n_0_0_0)); + INV_X1_LVT i_0_0_0 (.A(n_0_0_0), .ZN(thePC_n_30)); + SDFF_X1_LVT \thePC_CurrentPC_reg[0] (.D(thePC_n_30), .SE(1'b0), .SI( + CurrentPC[0]), .CK(clk_25mhz), .Q(CurrentPC[0]), .QN()); + reg_file theRegisters (.Rs1({Instruction[19], Instruction[18], + Instruction[17], Instruction[16], Instruction[15]}), .Rs2({Instruction[24], + Instruction[23], Instruction[22], Instruction[21], Instruction[20]}), + .Rd({Instruction[11], Instruction[10], Instruction[9], Instruction[8], + Instruction[7]}), .RRs1(RRs1), .RRs2(RRs2), .WRd(WRd), .WrReg(WrReg), + .reset(reset), .clk(clk_25mhz), .dftIn(scan_en)); + main_mem theMem (.clk(clk_25mhz), .reset(reset), .DAddr({uc_4, uc_5, uc_6, + uc_7, uc_8, uc_9, uc_10, uc_11, uc_12, uc_13, uc_14, uc_15, uc_16, uc_17, + uc_18, uc_19, uc_20, uc_21, uc_22, DAddr[12], DAddr[11], DAddr[10], + DAddr[9], DAddr[8], DAddr[7], DAddr[6], DAddr[5], DAddr[4], DAddr[3], + DAddr[2], DAddr[1], DAddr[0]}), .IAddr({uc_23, uc_24, uc_25, uc_26, uc_27, + uc_28, uc_29, uc_30, uc_31, uc_32, uc_33, uc_34, uc_35, uc_36, uc_37, + uc_38, uc_39, uc_40, uc_41, NextPC[12], NextPC[11], NextPC[10], NextPC[9], + NextPC[8], led[7], led[6], led[5], led[4], led[3], led[2], uc_42, uc_43}), + .DWData(RRs2), .DRData(RData), .IRData(Instruction), .DWE(led[1]), + .DWidth(DWidth)); + decoder theDecoder (.CurrentPC(CurrentPC), .JumpOrBranchPC(JumpOrBranchPC), + .JumpOrBranch(JumpOrBranch), .DAddr({uc_44, uc_45, uc_46, uc_47, uc_48, + uc_49, uc_50, uc_51, uc_52, uc_53, uc_54, uc_55, uc_56, uc_57, uc_58, + uc_59, uc_60, uc_61, uc_62, DAddr[12], DAddr[11], DAddr[10], DAddr[9], + DAddr[8], DAddr[7], DAddr[6], DAddr[5], DAddr[4], DAddr[3], DAddr[2], + DAddr[1], DAddr[0]}), .WData(), .RData(RData), .Instruction(Instruction), + .WrMem(led[1]), .DWidth(DWidth), .Rs1(), .Rs2(), .Rd(), .RRs1(RRs1), + .RRs2(RRs2), .WRd(WRd), .WrReg(WrReg), .Illegal(led[0])); + MUX2_X1_LVT i_0_0_60 (.A(thePC_n_5), .B(JumpOrBranchPC[7]), .S(JumpOrBranch), + .Z(led[7])); +endmodule diff --git a/output/riscv.tessent_post_scan.v b/output/riscv.tessent_post_scan.v new file mode 100644 index 0000000..480d5f3 --- /dev/null +++ b/output/riscv.tessent_post_scan.v @@ -0,0 +1,10620 @@ +/* + * Created by + ../bin/Linux-x86_64-O/oasysGui 22.2-p002 on Fri May 29 09:14:27 2026 + * (C) Mentor Graphics Corporation + */ +/* CheckSum: 3241830896 */ + +module datapathS__0_65(CurrentPC, p_0); + input [31:0]CurrentPC; + output [31:0]p_0; + + HA_X1_LVT i_0 (.A(CurrentPC[3]), .B(CurrentPC[2]), .CO(n_0), .S(p_0[3])); + HA_X1_LVT i_1 (.A(CurrentPC[4]), .B(n_0), .CO(n_1), .S(p_0[4])); + HA_X1_LVT i_2 (.A(CurrentPC[5]), .B(n_1), .CO(n_2), .S(p_0[5])); + HA_X1_LVT i_3 (.A(CurrentPC[6]), .B(n_2), .CO(n_3), .S(p_0[6])); + HA_X1_LVT i_4 (.A(CurrentPC[7]), .B(n_3), .CO(n_4), .S(p_0[7])); + HA_X1_LVT i_5 (.A(CurrentPC[8]), .B(n_4), .CO(n_5), .S(p_0[8])); + HA_X1_LVT i_6 (.A(CurrentPC[9]), .B(n_5), .CO(n_6), .S(p_0[9])); + HA_X1_LVT i_7 (.A(CurrentPC[10]), .B(n_6), .CO(n_7), .S(p_0[10])); + HA_X1_LVT i_8 (.A(CurrentPC[11]), .B(n_7), .CO(n_8), .S(p_0[11])); + HA_X1_LVT i_9 (.A(CurrentPC[12]), .B(n_8), .CO(n_9), .S(p_0[12])); + HA_X1_LVT i_11 (.A(CurrentPC[13]), .B(n_9), .CO(n_10), .S(p_0[13])); + HA_X1_LVT i_12 (.A(CurrentPC[14]), .B(n_10), .CO(n_11), .S(p_0[14])); + HA_X1_LVT i_13 (.A(CurrentPC[15]), .B(n_11), .CO(n_12), .S(p_0[15])); + HA_X1_LVT i_14 (.A(CurrentPC[16]), .B(n_12), .CO(n_13), .S(p_0[16])); + HA_X1_LVT i_15 (.A(CurrentPC[17]), .B(n_13), .CO(n_14), .S(p_0[17])); + HA_X1_LVT i_16 (.A(CurrentPC[18]), .B(n_14), .CO(n_15), .S(p_0[18])); + HA_X1_LVT i_17 (.A(CurrentPC[19]), .B(n_15), .CO(n_16), .S(p_0[19])); + HA_X1_LVT i_10 (.A(CurrentPC[20]), .B(n_16), .CO(n_17), .S(p_0[20])); + HA_X1_LVT i_18 (.A(CurrentPC[21]), .B(n_17), .CO(n_18), .S(p_0[21])); + HA_X1_LVT i_19 (.A(CurrentPC[22]), .B(n_18), .CO(n_19), .S(p_0[22])); + HA_X1_LVT i_20 (.A(CurrentPC[23]), .B(n_19), .CO(n_20), .S(p_0[23])); + HA_X1_LVT i_21 (.A(CurrentPC[24]), .B(n_20), .CO(n_21), .S(p_0[24])); + HA_X1_LVT i_22 (.A(CurrentPC[25]), .B(n_21), .CO(n_22), .S(p_0[25])); + HA_X1_LVT i_23 (.A(CurrentPC[26]), .B(n_22), .CO(n_23), .S(p_0[26])); + HA_X1_LVT i_24 (.A(CurrentPC[27]), .B(n_23), .CO(n_24), .S(p_0[27])); + HA_X1_LVT i_25 (.A(CurrentPC[28]), .B(n_24), .CO(n_25), .S(p_0[28])); + HA_X1_LVT i_26 (.A(CurrentPC[29]), .B(n_25), .CO(n_26), .S(p_0[29])); + HA_X1_LVT i_27 (.A(CurrentPC[30]), .B(n_26), .CO(n_27), .S(p_0[30])); + XOR2_X1_LVT i_28 (.A(CurrentPC[31]), .B(n_27), .Z(p_0[31])); + INV_X1_LVT i_29 (.A(CurrentPC[2]), .ZN(p_0[2])); +endmodule + +module reg_file(Rs1, Rs2, Rd, RRs1, RRs2, WRd, WrReg, reset, clk, dftIn, + ts_intno31, ts_no1050, ts_no1051, ts_no1053, ts_no1054, ts_extsi1226, + ts_extsi1227, ts_extsi1228); + input [4:0]Rs1; + input [4:0]Rs2; + input [4:0]Rd; + output [31:0]RRs1; + output [31:0]RRs2; + input [31:0]WRd; + input WrReg; + input reset; + input clk; + input dftIn; + input ts_intno31; + output ts_no1050; + output ts_no1051; + output ts_no1053; + output ts_no1054; + input ts_extsi1226; + input ts_extsi1227; + input ts_extsi1228; + + wire [31:0]registers_1__ap; + wire n_0_0__0; + wire [31:0]registers_2__ap; + wire n_0_32; + wire [31:0]registers_3__ap; + wire n_0_33; + wire [31:0]registers_4__ap; + wire n_0_34; + wire [31:0]registers_5__ap; + wire n_0_35; + wire [31:0]registers_6__ap; + wire n_0_36__0; + wire [31:0]registers_7__ap; + wire n_0_37; + wire [31:0]registers_8__ap; + wire n_0_38; + wire [31:0]registers_9__ap; + wire n_0_39; + wire [31:0]registers_10__ap; + wire n_0_40; + wire [31:0]registers_11__ap; + wire n_0_41__0; + wire [31:0]registers_12__ap; + wire n_0_42; + wire [31:0]registers_13__ap; + wire n_0_43; + wire [31:0]registers_14__ap; + wire n_0_44; + wire [31:0]registers_15__ap; + wire n_0_45; + wire [31:0]registers_16__ap; + wire n_0_46; + wire [31:0]registers_17__ap; + wire n_0_47; + wire [31:0]registers_18__ap; + wire n_0_48; + wire [31:0]registers_19__ap; + wire n_0_49; + wire [31:0]registers_20__ap; + wire n_0_50; + wire [31:0]registers_21__ap; + wire n_0_51; + wire [31:0]registers_22__ap; + wire n_0_52; + wire [31:0]registers_23__ap; + wire n_0_53; + wire [31:0]registers_24__ap; + wire n_0_54; + wire [31:0]registers_25__ap; + wire n_0_55; + wire [31:0]registers_26__ap; + wire n_0_56; + wire [31:0]registers_27__ap; + wire n_0_57__0; + wire [31:0]registers_28__ap; + wire n_0_0__1; + wire [31:0]registers_29__ap; + wire n_0_1; + wire [31:0]registers_30__ap; + wire n_0_2; + wire [31:0]registers_31__ap; + wire n_0_3; + wire [31:0]registers; + wire n_0_31; + wire n_0_30; + wire n_0_29; + wire n_0_28; + wire n_0_27; + wire n_0_26; + wire n_0_25; + wire n_0_24; + wire n_0_0_0; + wire n_0_0_1; + wire n_0_23; + wire n_0_22; + wire n_0_21; + wire n_0_20; + wire n_0_19; + wire n_0_18; + wire n_0_17; + wire n_0_16; + wire n_0_0_2; + wire n_0_0_3; + wire n_0_15; + wire n_0_14; + wire n_0_13; + wire n_0_12; + wire n_0_11; + wire n_0_10; + wire n_0_9; + wire n_0_8; + wire n_0_0_4; + wire n_0_0_5; + wire n_0_7; + wire n_0_0_6; + wire n_0_6; + wire n_0_0_7; + wire n_0_5; + wire n_0_0_8; + wire n_0_4; + wire n_0_0_9; + wire n_0_0_10; + wire n_0_36__1; + wire n_0_0_11; + wire n_0_41__1; + wire n_0_0_12; + wire n_0_57__1; + wire n_0_0_13; + wire n_0_0_14; + wire n_0_0_15; + wire n_0_0_16; + wire n_0_0_17; + wire n_0_0_18; + wire n_0_0_19; + wire n_0_0_20; + wire n_1_0_0; + wire n_1_0_1; + wire n_1_0_2; + wire n_1_0_3; + wire n_1_0_4; + wire n_1_0_5; + wire n_1_0_6; + wire n_1_0_7; + wire n_1_0_8; + wire n_1_0_9; + wire n_1_0_10; + wire n_1_0_11; + wire n_1_0_12; + wire n_1_0_13; + wire n_1_0_14; + wire n_1_0_15; + wire n_1_0_16; + wire n_1_0_17; + wire n_1_0_18; + wire n_1_0_19; + wire n_1_0_20; + wire n_1_0_21; + wire n_1_0_22; + wire n_1_0_23; + wire n_1_0_24; + wire n_1_0_25; + wire n_1_0_26; + wire n_1_0_27; + wire n_1_0_28; + wire n_1_0_29; + wire n_1_0_30; + wire n_1_0_31; + wire n_1_0_32; + wire n_1_0_33; + wire n_1_0_34; + wire n_1_0_35; + wire n_1_0_36; + wire n_1_0_37; + wire n_1_0_38; + wire n_1_0_39; + wire n_1_0_40; + wire n_1_0_41; + wire n_1_0_42; + wire n_1_0_43; + wire n_1_0_44; + wire n_1_0_45; + wire n_1_0_46; + wire n_1_0_47; + wire n_1_0_48; + wire n_1_0_49; + wire n_1_0_50; + wire n_1_0_51; + wire n_1_0_52; + wire n_1_0_53; + wire n_1_0_54; + wire n_1_0_55; + wire n_1_0_56; + wire n_1_0_57; + wire n_1_0_58; + wire n_1_0_59; + wire n_1_0_60; + wire n_1_0_61; + wire n_1_0_62; + wire n_1_0_63; + wire n_1_0_64; + wire n_1_0_65; + wire n_1_0_66; + wire n_1_0_67; + wire n_1_0_68; + wire n_1_0_69; + wire n_1_0_70; + wire n_1_0_71; + wire n_1_0_72; + wire n_1_0_73; + wire n_1_0_74; + wire n_1_0_75; + wire n_1_0_76; + wire n_1_0_77; + wire n_1_0_78; + wire n_1_0_79; + wire n_1_0_80; + wire n_1_0_81; + wire n_1_0_82; + wire n_1_0_83; + wire n_1_0_84; + wire n_1_0_85; + wire n_1_0_86; + wire n_1_0_87; + wire n_1_0_88; + wire n_1_0_89; + wire n_1_0_90; + wire n_1_0_91; + wire n_1_0_92; + wire n_1_0_93; + wire n_1_0_94; + wire n_1_0_95; + wire n_1_0_96; + wire n_1_0_97; + wire n_1_0_98; + wire n_1_0_99; + wire n_1_0_100; + wire n_1_0_101; + wire n_1_0_102; + wire n_1_0_103; + wire n_1_0_104; + wire n_1_0_105; + wire n_1_0_106; + wire n_1_0_107; + wire n_1_0_108; + wire n_1_0_109; + wire n_1_0_110; + wire n_1_0_111; + wire n_1_0_112; + wire n_1_0_113; + wire n_1_0_114; + wire n_1_0_115; + wire n_1_0_116; + wire n_1_0_117; + wire n_1_0_118; + wire n_1_0_119; + wire n_1_0_120; + wire n_1_0_121; + wire n_1_0_122; + wire n_1_0_123; + wire n_1_0_124; + wire n_1_0_125; + wire n_1_0_126; + wire n_1_0_127; + wire n_1_0_128; + wire n_1_0_129; + wire n_1_0_130; + wire n_1_0_131; + wire n_1_0_132; + wire n_1_0_133; + wire n_1_0_134; + wire n_1_0_135; + wire n_1_0_136; + wire n_1_0_137; + wire n_1_0_138; + wire n_1_0_139; + wire n_1_0_140; + wire n_1_0_141; + wire n_1_0_142; + wire n_1_0_143; + wire n_1_0_144; + wire n_1_0_145; + wire n_1_0_146; + wire n_1_0_147; + wire n_1_0_148; + wire n_1_0_149; + wire n_1_0_150; + wire n_1_0_151; + wire n_1_0_152; + wire n_1_0_153; + wire n_1_0_154; + wire n_1_0_155; + wire n_1_0_156; + wire n_1_0_157; + wire n_1_0_158; + wire n_1_0_159; + wire n_1_0_160; + wire n_1_0_161; + wire n_1_0_162; + wire n_1_0_163; + wire n_1_0_164; + wire n_1_0_165; + wire n_1_0_166; + wire n_1_0_167; + wire n_1_0_168; + wire n_1_0_169; + wire n_1_0_170; + wire n_1_0_171; + wire n_1_0_172; + wire n_1_0_173; + wire n_1_0_174; + wire n_1_0_175; + wire n_1_0_176; + wire n_1_0_177; + wire n_1_0_178; + wire n_1_0_179; + wire n_1_0_180; + wire n_1_0_181; + wire n_1_0_182; + wire n_1_0_183; + wire n_1_0_184; + wire n_1_0_185; + wire n_1_0_186; + wire n_1_0_187; + wire n_1_0_188; + wire n_1_0_189; + wire n_1_0_190; + wire n_1_0_191; + wire n_1_0_192; + wire n_1_0_193; + wire n_1_0_194; + wire n_1_0_195; + wire n_1_0_196; + wire n_1_0_197; + wire n_1_0_198; + wire n_1_0_199; + wire n_1_0_200; + wire n_1_0_201; + wire n_1_0_202; + wire n_1_0_203; + wire n_1_0_204; + wire n_1_0_205; + wire n_1_0_206; + wire n_1_0_207; + wire n_1_0_208; + wire n_1_0_209; + wire n_1_0_210; + wire n_1_0_211; + wire n_1_0_212; + wire n_1_0_213; + wire n_1_0_214; + wire n_1_0_215; + wire n_1_0_216; + wire n_1_0_217; + wire n_1_0_218; + wire n_1_0_219; + wire n_1_0_220; + wire n_1_0_221; + wire n_1_0_222; + wire n_1_0_223; + wire n_1_0_224; + wire n_1_0_225; + wire n_1_0_226; + wire n_1_0_227; + wire n_1_0_228; + wire n_1_0_229; + wire n_1_0_230; + wire n_1_0_231; + wire n_1_0_232; + wire n_1_0_233; + wire n_1_0_234; + wire n_1_0_235; + wire n_1_0_236; + wire n_1_0_237; + wire n_1_0_238; + wire n_1_0_239; + wire n_1_0_240; + wire n_1_0_241; + wire n_1_0_242; + wire n_1_0_243; + wire n_1_0_244; + wire n_1_0_245; + wire n_1_0_246; + wire n_1_0_247; + wire n_1_0_248; + wire n_1_0_249; + wire n_1_0_250; + wire n_1_0_251; + wire n_1_0_252; + wire n_1_0_253; + wire n_1_0_254; + wire n_1_0_255; + wire n_1_0_256; + wire n_1_0_257; + wire n_1_0_258; + wire n_1_0_259; + wire n_1_0_260; + wire n_1_0_261; + wire n_1_0_262; + wire n_1_0_263; + wire n_1_0_264; + wire n_1_0_265; + wire n_1_0_266; + wire n_1_0_267; + wire n_1_0_268; + wire n_1_0_269; + wire n_1_0_270; + wire n_1_0_271; + wire n_1_0_272; + wire n_1_0_273; + wire n_1_0_274; + wire n_1_0_275; + wire n_1_0_276; + wire n_1_0_277; + wire n_1_0_278; + wire n_1_0_279; + wire n_1_0_280; + wire n_1_0_281; + wire n_1_0_282; + wire n_1_0_283; + wire n_1_0_284; + wire n_1_0_285; + wire n_1_0_286; + wire n_1_0_287; + wire n_1_0_288; + wire n_1_0_289; + wire n_1_0_290; + wire n_1_0_291; + wire n_1_0_292; + wire n_1_0_293; + wire n_1_0_294; + wire n_1_0_295; + wire n_1_0_296; + wire n_1_0_297; + wire n_1_0_298; + wire n_1_0_299; + wire n_1_0_300; + wire n_1_0_301; + wire n_1_0_302; + wire n_1_0_303; + wire n_1_0_304; + wire n_1_0_305; + wire n_1_0_306; + wire n_1_0_307; + wire n_1_0_308; + wire n_1_0_309; + wire n_1_0_310; + wire n_1_0_311; + wire n_1_0_312; + wire n_1_0_313; + wire n_1_0_314; + wire n_1_0_315; + wire n_1_0_316; + wire n_1_0_317; + wire n_1_0_318; + wire n_1_0_319; + wire n_1_0_320; + wire n_1_0_321; + wire n_1_0_322; + wire n_1_0_323; + wire n_1_0_324; + wire n_1_0_325; + wire n_1_0_326; + wire n_1_0_327; + wire n_1_0_328; + wire n_1_0_329; + wire n_1_0_330; + wire n_1_0_331; + wire n_1_0_332; + wire n_1_0_333; + wire n_1_0_334; + wire n_1_0_335; + wire n_1_0_336; + wire n_1_0_337; + wire n_1_0_338; + wire n_1_0_339; + wire n_1_0_340; + wire n_1_0_341; + wire n_1_0_342; + wire n_1_0_343; + wire n_1_0_344; + wire n_1_0_345; + wire n_1_0_346; + wire n_1_0_347; + wire n_1_0_348; + wire n_1_0_349; + wire n_1_0_350; + wire n_1_0_351; + wire n_1_0_352; + wire n_1_0_353; + wire n_1_0_354; + wire n_1_0_355; + wire n_1_0_356; + wire n_1_0_357; + wire n_1_0_358; + wire n_1_0_359; + wire n_1_0_360; + wire n_1_0_361; + wire n_1_0_362; + wire n_1_0_363; + wire n_1_0_364; + wire n_1_0_365; + wire n_1_0_366; + wire n_1_0_367; + wire n_1_0_368; + wire n_1_0_369; + wire n_1_0_370; + wire n_1_0_371; + wire n_1_0_372; + wire n_1_0_373; + wire n_1_0_374; + wire n_1_0_375; + wire n_1_0_376; + wire n_1_0_377; + wire n_1_0_378; + wire n_1_0_379; + wire n_1_0_380; + wire n_1_0_381; + wire n_1_0_382; + wire n_1_0_383; + wire n_1_0_384; + wire n_1_0_385; + wire n_1_0_386; + wire n_1_0_387; + wire n_1_0_388; + wire n_1_0_389; + wire n_1_0_390; + wire n_1_0_391; + wire n_1_0_392; + wire n_1_0_393; + wire n_1_0_394; + wire n_1_0_395; + wire n_1_0_396; + wire n_1_0_397; + wire n_1_0_398; + wire n_1_0_399; + wire n_1_0_400; + wire n_1_0_401; + wire n_1_0_402; + wire n_1_0_403; + wire n_1_0_404; + wire n_1_0_405; + wire n_1_0_406; + wire n_1_0_407; + wire n_1_0_408; + wire n_1_0_409; + wire n_1_0_410; + wire n_1_0_411; + wire n_1_0_412; + wire n_1_0_413; + wire n_1_0_414; + wire n_1_0_415; + wire n_1_0_416; + wire n_1_0_417; + wire n_1_0_418; + wire n_1_0_419; + wire n_1_0_420; + wire n_1_0_421; + wire n_1_0_422; + wire n_1_0_423; + wire n_1_0_424; + wire n_1_0_425; + wire n_1_0_426; + wire n_1_0_427; + wire n_1_0_428; + wire n_1_0_429; + wire n_1_0_430; + wire n_1_0_431; + wire n_1_0_432; + wire n_1_0_433; + wire n_1_0_434; + wire n_1_0_435; + wire n_1_0_436; + wire n_1_0_437; + wire n_1_0_438; + wire n_1_0_439; + wire n_1_0_440; + wire n_1_0_441; + wire n_1_0_442; + wire n_1_0_443; + wire n_1_0_444; + wire n_1_0_445; + wire n_1_0_446; + wire n_1_0_447; + wire n_1_0_448; + wire n_1_0_449; + wire n_1_0_450; + wire n_1_0_451; + wire n_1_0_452; + wire n_1_0_453; + wire n_1_0_454; + wire n_1_0_455; + wire n_1_0_456; + wire n_1_0_457; + wire n_1_0_458; + wire n_1_0_459; + wire n_1_0_460; + wire n_1_0_461; + wire n_1_0_462; + wire n_1_0_463; + wire n_1_0_464; + wire n_1_0_465; + wire n_1_0_466; + wire n_1_0_467; + wire n_1_0_468; + wire n_1_0_469; + wire n_1_0_470; + wire n_1_0_471; + wire n_1_0_472; + wire n_1_0_473; + wire n_1_0_474; + wire n_1_0_475; + wire n_1_0_476; + wire n_1_0_477; + wire n_1_0_478; + wire n_1_0_479; + wire n_1_0_480; + wire n_1_0_481; + wire n_1_0_482; + wire n_1_0_483; + wire n_1_0_484; + wire n_1_0_485; + wire n_1_0_486; + wire n_1_0_487; + wire n_1_0_488; + wire n_1_0_489; + wire n_1_0_490; + wire n_1_0_491; + wire n_1_0_492; + wire n_1_0_493; + wire n_1_0_494; + wire n_1_0_495; + wire n_1_0_496; + wire n_1_0_497; + wire n_1_0_498; + wire n_1_0_499; + wire n_1_0_500; + wire n_1_0_501; + wire n_1_0_502; + wire n_1_0_503; + wire n_1_0_504; + wire n_1_0_505; + wire n_1_0_506; + wire n_1_0_507; + wire n_1_0_508; + wire n_1_0_509; + wire n_1_0_510; + wire n_1_0_511; + wire n_1_0_512; + wire n_1_0_513; + wire n_1_0_514; + wire n_1_0_515; + wire n_1_0_516; + wire n_1_0_517; + wire n_1_0_518; + wire n_1_0_519; + wire n_1_0_520; + wire n_1_0_521; + wire n_1_0_522; + wire n_1_0_523; + wire n_1_0_524; + wire n_1_0_525; + wire n_1_0_526; + wire n_1_0_527; + wire n_1_0_528; + wire n_1_0_529; + wire n_1_0_530; + wire n_1_0_531; + wire n_1_0_532; + wire n_1_0_533; + wire n_1_0_534; + wire n_1_0_535; + wire n_1_0_536; + wire n_1_0_537; + wire n_1_0_538; + wire n_1_0_539; + wire n_1_0_540; + wire n_1_0_541; + wire n_1_0_542; + wire n_1_0_543; + wire n_1_0_544; + wire n_1_0_545; + wire n_1_0_546; + wire n_1_0_547; + wire n_1_0_548; + wire n_1_0_549; + wire n_1_0_550; + wire n_1_0_551; + wire n_1_0_552; + wire n_1_0_553; + wire n_1_0_554; + wire n_1_0_555; + wire n_1_0_556; + wire n_1_0_557; + wire n_1_0_558; + wire n_1_0_559; + wire n_1_0_560; + wire n_1_0_561; + wire n_1_0_562; + wire n_1_0_563; + wire n_1_0_564; + wire n_1_0_565; + wire n_1_0_566; + wire n_1_0_567; + wire n_1_0_568; + wire n_1_0_569; + wire n_1_0_570; + wire n_1_0_571; + wire n_1_0_572; + wire n_1_0_573; + wire n_1_0_574; + wire n_1_0_575; + wire n_1_0_576; + wire n_1_0_577; + wire n_1_0_578; + wire n_1_0_579; + wire n_1_0_580; + wire n_1_0_581; + wire n_1_0_582; + wire n_1_0_583; + wire n_1_0_584; + wire n_1_0_585; + wire n_1_0_586; + wire n_1_0_587; + wire n_1_0_588; + wire n_1_0_589; + wire n_1_0_590; + wire n_1_0_591; + wire n_1_0_592; + wire n_1_0_593; + wire n_1_0_594; + wire n_1_0_595; + wire n_1_0_596; + wire n_1_0_597; + wire n_1_0_598; + wire n_1_0_599; + wire n_1_0_600; + wire n_1_0_601; + wire n_1_0_602; + wire n_1_0_603; + wire n_1_0_604; + wire n_1_0_605; + wire n_1_0_606; + wire n_1_0_607; + wire n_1_0_608; + wire n_1_0_609; + wire n_1_0_610; + wire n_1_0_611; + wire n_1_0_612; + wire n_1_0_613; + wire n_1_0_614; + wire n_1_0_615; + wire n_1_0_616; + wire n_1_0_617; + wire n_1_0_618; + wire n_1_0_619; + wire n_1_0_620; + wire n_1_0_621; + wire n_1_0_622; + wire n_1_0_623; + wire n_1_0_624; + wire n_1_0_625; + wire n_1_0_626; + wire n_1_0_627; + wire n_1_0_628; + wire n_1_0_629; + wire n_1_0_630; + wire n_1_0_631; + wire n_1_0_632; + wire n_1_0_633; + wire n_1_0_634; + wire n_1_0_635; + wire n_1_0_636; + wire n_1_0_637; + wire n_1_0_638; + wire n_1_0_639; + wire n_1_0_640; + wire n_1_0_641; + wire n_1_0_642; + wire n_1_0_643; + wire n_1_0_644; + wire n_1_0_645; + wire n_1_0_646; + wire n_1_0_647; + wire n_1_0_648; + wire n_1_0_649; + wire n_1_0_650; + wire n_1_0_651; + wire n_1_0_652; + wire n_1_0_653; + wire n_1_0_654; + wire n_1_0_655; + wire n_1_0_656; + wire n_1_0_657; + wire n_1_0_658; + wire n_1_0_659; + wire n_1_0_660; + wire n_1_0_661; + wire n_1_0_662; + wire n_1_0_663; + wire n_1_0_664; + wire n_1_0_665; + wire n_1_0_666; + wire n_1_0_667; + wire n_1_0_668; + wire n_1_0_669; + wire n_1_0_670; + wire n_1_0_671; + wire n_1_0_672; + wire n_1_0_673; + wire n_1_0_674; + wire n_1_0_675; + wire n_1_0_676; + wire n_1_0_677; + wire n_1_0_678; + wire n_1_0_679; + wire n_1_0_680; + wire n_1_0_681; + wire n_1_0_682; + wire n_1_0_683; + wire n_1_0_684; + wire n_1_0_685; + wire n_1_0_686; + wire n_1_0_687; + wire n_1_0_688; + wire n_1_0_689; + wire n_1_0_690; + wire n_1_0_691; + wire n_1_0_692; + wire n_1_0_693; + wire n_1_0_694; + wire n_1_0_695; + wire n_1_0_696; + wire n_1_0_697; + wire n_1_0_698; + wire n_1_0_699; + wire n_1_0_700; + wire n_1_0_701; + wire n_1_0_702; + wire n_1_0_703; + wire n_1_0_704; + wire n_1_0_705; + wire n_1_0_706; + wire n_1_0_707; + wire n_1_0_708; + wire n_1_0_709; + wire n_1_0_710; + wire n_1_0_711; + wire n_1_0_712; + wire n_1_0_713; + wire n_1_0_714; + wire n_1_0_715; + wire n_1_0_716; + wire n_1_0_717; + wire n_1_0_718; + wire n_1_0_719; + wire n_1_0_720; + wire n_1_0_721; + wire n_1_0_722; + wire n_1_0_723; + wire n_1_0_724; + wire n_1_0_725; + wire n_1_0_726; + wire n_1_0_727; + wire n_1_0_728; + wire n_1_0_729; + wire n_1_0_730; + wire n_1_0_731; + wire n_1_0_732; + wire n_1_0_733; + wire n_1_0_734; + wire n_1_0_735; + wire n_1_0_736; + wire n_1_0_737; + wire n_1_0_738; + wire n_1_0_739; + wire n_1_0_740; + wire n_1_0_741; + wire n_1_0_742; + wire n_1_0_743; + wire n_1_0_744; + wire n_1_0_745; + wire n_1_0_746; + wire n_1_0_747; + wire n_1_0_748; + wire n_1_0_749; + wire n_1_0_750; + wire n_1_0_751; + wire n_1_0_752; + wire n_1_0_753; + wire n_1_0_754; + wire n_1_0_755; + wire n_1_0_756; + wire n_1_0_757; + wire n_1_0_758; + wire n_1_0_759; + wire n_1_0_760; + wire n_1_0_761; + wire n_1_0_762; + wire n_1_0_763; + wire n_1_0_764; + wire n_1_0_765; + wire n_1_0_766; + wire n_1_0_767; + wire n_1_0_768; + wire n_1_0_769; + wire n_1_0_770; + wire n_1_0_771; + wire n_1_0_772; + wire n_1_0_773; + wire n_1_0_774; + wire n_1_0_775; + wire n_1_0_776; + wire n_1_0_777; + wire n_1_0_778; + wire n_1_0_779; + wire n_1_0_780; + wire n_1_0_781; + wire n_1_0_782; + wire n_1_0_783; + wire n_1_0_784; + wire n_1_0_785; + wire n_1_0_786; + wire n_1_0_787; + wire n_1_0_788; + wire n_1_0_789; + wire n_1_0_790; + wire n_1_0_791; + wire n_1_0_792; + wire n_1_0_793; + wire n_1_0_794; + wire n_1_0_795; + wire n_1_0_796; + wire n_1_0_797; + wire n_1_0_798; + wire n_1_0_799; + wire n_1_0_800; + wire n_1_0_801; + wire n_1_0_802; + wire n_1_0_803; + wire n_1_0_804; + wire n_1_0_805; + wire n_1_0_806; + wire n_1_0_807; + wire n_1_0_808; + wire n_1_0_809; + wire n_1_0_810; + wire n_1_0_811; + wire n_1_0_812; + wire n_1_0_813; + wire n_1_0_814; + wire n_1_0_815; + wire n_1_0_816; + wire n_1_0_817; + wire n_1_0_818; + wire n_1_0_819; + wire n_1_0_820; + wire n_1_0_821; + wire n_1_0_822; + wire n_1_0_823; + wire n_1_0_824; + wire n_1_0_825; + wire n_1_0_826; + wire n_1_0_827; + wire n_1_0_828; + wire n_1_0_829; + wire n_1_0_830; + wire n_1_0_831; + wire n_1_0_832; + wire n_1_0_833; + wire n_1_0_834; + wire n_1_0_835; + wire n_1_0_836; + wire n_1_0_837; + wire n_1_0_838; + wire n_1_0_839; + wire n_1_0_840; + wire n_1_0_841; + wire n_1_0_842; + wire n_1_0_843; + wire n_1_0_844; + wire n_1_0_845; + wire n_1_0_846; + wire n_1_0_847; + wire n_1_0_848; + wire n_1_0_849; + wire n_1_0_850; + wire n_1_0_851; + wire n_1_0_852; + wire n_1_0_853; + wire n_1_0_854; + wire n_1_0_855; + wire n_1_0_856; + wire n_1_0_857; + wire n_1_0_858; + wire n_1_0_859; + wire n_1_0_860; + wire n_1_0_861; + wire n_1_0_862; + wire n_1_0_863; + wire n_1_0_864; + wire n_1_0_865; + wire n_1_0_866; + wire n_1_0_867; + wire n_1_0_868; + wire n_1_0_869; + wire n_1_0_870; + wire n_1_0_871; + wire n_1_0_872; + wire n_1_0_873; + wire n_1_0_874; + wire n_1_0_875; + wire n_1_0_876; + wire n_1_0_877; + wire n_1_0_878; + wire n_1_0_879; + wire n_1_0_880; + wire n_1_0_881; + wire n_1_0_882; + wire n_1_0_883; + wire n_1_0_884; + wire n_1_0_885; + wire n_1_0_886; + wire n_1_0_887; + wire n_1_0_888; + wire n_1_0_889; + wire n_1_0_890; + wire n_1_0_891; + wire n_1_0_892; + wire n_1_0_893; + wire n_1_0_894; + wire n_1_0_895; + wire n_1_0_896; + wire n_1_0_897; + wire n_1_0_898; + wire n_1_0_899; + wire n_1_0_900; + wire n_1_0_901; + wire n_1_0_902; + wire n_1_0_903; + wire n_1_0_904; + wire n_1_0_905; + wire n_1_0_906; + wire n_1_0_907; + wire n_1_0_908; + wire n_1_0_909; + wire n_1_0_910; + wire n_1_0_911; + wire n_1_0_912; + wire n_1_0_913; + wire n_1_0_914; + wire n_1_0_915; + wire n_1_0_916; + wire n_1_0_917; + wire n_1_0_918; + wire n_1_0_919; + wire n_1_0_920; + wire n_1_0_921; + wire n_1_0_922; + wire n_1_0_923; + wire n_1_0_924; + wire n_1_0_925; + wire n_1_0_926; + wire n_1_0_927; + wire n_1_0_928; + wire n_1_0_929; + wire n_1_0_930; + wire n_1_0_931; + wire n_1_0_932; + wire n_1_0_933; + wire n_1_0_934; + wire n_1_0_935; + wire n_1_0_936; + wire n_1_0_937; + wire n_1_0_938; + wire n_1_0_939; + wire n_1_0_940; + wire n_1_0_941; + wire n_1_0_942; + wire n_1_0_943; + wire n_1_0_944; + wire n_1_0_945; + wire n_1_0_946; + wire n_1_0_947; + wire n_1_0_948; + wire n_1_0_949; + wire n_1_0_950; + wire n_1_0_951; + wire n_1_0_952; + wire n_1_0_953; + wire n_1_0_954; + wire n_1_0_955; + wire n_1_0_956; + wire n_1_0_957; + wire n_1_0_958; + wire n_1_0_959; + wire n_1_0_960; + wire n_1_0_961; + wire n_1_0_962; + wire n_1_0_963; + wire n_1_0_964; + wire n_1_0_965; + wire n_1_0_966; + wire n_1_0_967; + wire n_1_0_968; + wire n_1_0_969; + wire n_1_0_970; + wire n_1_0_971; + wire n_1_0_972; + wire n_1_0_973; + wire n_1_0_974; + wire n_1_0_975; + wire n_1_0_976; + wire n_1_0_977; + wire n_1_0_978; + wire n_1_0_979; + wire n_1_0_980; + wire n_1_0_981; + wire n_1_0_982; + wire n_1_0_983; + wire n_1_0_984; + wire n_1_0_985; + wire n_1_0_986; + wire n_1_0_987; + wire n_1_0_988; + wire n_1_0_989; + wire n_1_0_990; + wire n_1_0_991; + wire n_1_0_992; + wire n_1_0_993; + wire n_1_0_994; + wire n_1_0_995; + wire n_1_0_996; + wire n_1_0_997; + wire n_1_0_998; + wire n_1_0_999; + wire n_1_0_1000; + wire n_1_0_1001; + wire n_1_0_1002; + wire n_1_0_1003; + wire n_1_0_1004; + wire n_1_0_1005; + wire n_1_0_1006; + wire n_1_0_1007; + wire n_1_0_1008; + wire n_1_0_1009; + wire n_1_0_1010; + wire n_1_0_1011; + wire n_1_0_1012; + wire n_1_0_1013; + wire n_1_0_1014; + wire n_1_0_1015; + wire n_1_0_1016; + wire n_1_0_1017; + wire n_1_0_1018; + wire n_1_0_1019; + wire n_1_0_1020; + wire n_1_0_1021; + wire n_1_0_1022; + wire n_1_0_1023; + wire n_1_0_1024; + wire n_1_0_1025; + wire n_1_0_1026; + wire n_1_0_1027; + wire n_1_0_1028; + wire n_1_0_1029; + wire n_1_0_1030; + wire n_1_0_1031; + wire n_1_0_1032; + wire n_1_0_1033; + wire n_1_0_1034; + wire n_1_0_1035; + wire n_1_0_1036; + wire n_1_0_1037; + wire n_1_0_1038; + wire n_1_0_1039; + wire n_1_0_1040; + wire n_1_0_1041; + wire n_1_0_1042; + wire n_1_0_1043; + wire n_1_0_1044; + wire n_1_0_1045; + wire n_1_0_1046; + wire n_1_0_1047; + wire n_1_0_1048; + wire n_1_0_1049; + wire n_1_0_1050; + wire n_1_0_1051; + wire n_1_0_1052; + wire n_1_0_1053; + wire n_1_0_1054; + wire n_1_0_1055; + wire n_1_0_1056; + wire n_1_0_1057; + wire n_1_0_1058; + wire n_1_0_1059; + wire n_1_0_1060; + wire n_1_0_1061; + wire n_1_0_1062; + wire n_1_0_1063; + wire n_1_0_1064; + wire n_1_0_1065; + wire n_1_0_1066; + wire n_1_0_1067; + wire n_1_0_1068; + wire n_1_0_1069; + wire n_1_0_1070; + wire n_1_0_1071; + wire n_1_0_1072; + wire n_1_0_1073; + wire n_1_0_1074; + wire n_1_0_1075; + wire n_1_0_1076; + wire n_1_0_1077; + wire n_1_0_1078; + wire n_1_0_1079; + wire n_1_0_1080; + wire n_1_0_1081; + wire n_1_0_1082; + wire n_1_0_1083; + wire n_1_0_1084; + wire n_1_0_1085; + wire n_1_0_1086; + wire n_1_0_1087; + wire n_1_0_1088; + wire n_1_0_1089; + wire n_1_0_1090; + wire n_1_0_1091; + wire n_1_0_1092; + wire n_1_0_1093; + wire n_1_0_1094; + wire n_1_0_1095; + wire n_1_0_1096; + wire n_1_0_1097; + wire n_1_0_1098; + wire n_1_0_1099; + wire n_1_0_1100; + wire n_1_0_1101; + wire n_1_0_1102; + wire n_1_0_1103; + wire n_1_0_1104; + wire n_1_0_1105; + wire n_1_0_1106; + wire n_1_0_1107; + wire n_1_0_1108; + wire n_1_0_1109; + wire n_1_0_1110; + wire n_1_0_1111; + wire n_1_0_1112; + wire n_1_0_1113; + wire n_1_0_1114; + wire n_1_0_1115; + wire n_1_0_1116; + wire n_1_0_1117; + wire n_1_0_1118; + wire n_1_0_1119; + wire n_1_0_1120; + wire n_1_0_1121; + wire n_1_0_1122; + wire n_1_0_1123; + wire n_1_0_1124; + wire n_1_0_1125; + wire n_1_0_1126; + wire n_1_0_1127; + wire n_1_0_1128; + wire n_1_0_1129; + wire n_1_0_1130; + wire n_1_0_1131; + wire n_1_0_1132; + wire n_1_0_1133; + wire n_1_0_1134; + wire n_1_0_1135; + wire n_1_0_1136; + wire n_1_0_1137; + wire n_1_0_1138; + wire n_1_0_1139; + wire n_1_0_1140; + wire n_1_0_1141; + wire n_1_0_1142; + wire n_1_0_1143; + wire n_1_0_1144; + wire n_1_0_1145; + wire n_1_0_1146; + wire n_1_0_1147; + wire n_1_0_1148; + wire n_1_0_1149; + wire n_1_0_1150; + wire n_1_0_1151; + wire n_1_0_1152; + wire n_1_0_1153; + wire n_1_0_1154; + wire n_1_0_1155; + wire n_1_0_1156; + wire n_1_0_1157; + wire n_1_0_1158; + wire n_1_0_1159; + wire n_1_0_1160; + wire n_1_0_1161; + wire n_1_0_1162; + wire n_1_0_1163; + wire n_1_0_1164; + wire n_1_0_1165; + wire n_1_0_1166; + wire n_1_0_1167; + wire n_1_0_1168; + wire n_1_0_1169; + wire n_1_0_1170; + wire n_1_0_1171; + wire n_1_0_1172; + wire n_1_0_1173; + wire n_1_0_1174; + wire n_1_0_1175; + wire n_1_0_1176; + wire n_1_0_1177; + wire n_1_0_1178; + wire n_1_0_1179; + wire n_1_0_1180; + wire n_1_0_1181; + wire n_1_0_1182; + wire n_1_0_1183; + wire n_1_0_1184; + wire n_1_0_1185; + wire n_1_0_1186; + wire n_1_0_1187; + wire n_1_0_1188; + wire n_1_0_1189; + wire n_1_0_1190; + wire n_1_0_1191; + wire n_1_0_1192; + wire n_1_0_1193; + wire n_1_0_1194; + wire n_1_0_1195; + wire n_1_0_1196; + wire n_1_0_1197; + wire n_1_0_1198; + wire n_1_0_1199; + wire n_1_0_1200; + wire n_1_0_1201; + wire n_1_0_1202; + wire n_1_0_1203; + wire n_1_0_1204; + wire n_1_0_1205; + wire n_1_0_1206; + wire n_1_0_1207; + wire n_1_0_1208; + wire n_1_0_1209; + wire n_1_0_1210; + wire n_1_0_1211; + wire n_1_0_1212; + wire n_1_0_1213; + wire n_1_0_1214; + wire n_1_0_1215; + wire n_1_0_1216; + wire n_1_0_1217; + wire n_1_0_1218; + wire n_1_0_1219; + wire n_1_0_1220; + wire n_1_0_1221; + wire n_1_0_1222; + wire n_1_0_1223; + wire n_1_0_1224; + wire n_1_0_1225; + wire n_1_0_1226; + wire n_1_0_1227; + wire n_1_0_1228; + wire n_1_0_1229; + wire n_1_0_1230; + wire n_1_0_1231; + wire n_1_0_1232; + wire n_1_0_1233; + wire n_1_0_1234; + wire n_1_0_1235; + wire n_1_0_1236; + wire n_1_0_1237; + wire n_1_0_1238; + wire n_1_0_1239; + wire n_1_0_1240; + wire n_1_0_1241; + wire n_1_0_1242; + wire n_1_0_1243; + wire n_1_0_1244; + wire n_1_0_1245; + wire n_1_0_1246; + wire n_1_0_1247; + wire n_1_0_1248; + wire n_1_0_1249; + wire n_1_0_1250; + wire n_1_0_1251; + wire n_1_0_1252; + wire n_1_0_1253; + wire n_1_0_1254; + wire n_1_0_1255; + wire n_1_0_1256; + wire n_1_0_1257; + wire n_1_0_1258; + wire n_1_0_1259; + wire n_1_0_1260; + wire n_1_0_1261; + wire n_1_0_1262; + wire n_1_0_1263; + wire n_1_0_1264; + wire n_1_0_1265; + wire n_1_0_1266; + wire n_1_0_1267; + wire n_1_0_1268; + wire n_1_0_1269; + wire n_1_0_1270; + wire n_1_0_1271; + wire n_1_0_1272; + wire n_1_0_1273; + wire n_1_0_1274; + wire n_1_0_1275; + wire n_1_0_1276; + wire n_1_0_1277; + wire n_1_0_1278; + wire n_1_0_1279; + wire n_1_0_1280; + wire n_1_0_1281; + wire n_1_0_1282; + wire n_1_0_1283; + wire n_1_0_1284; + wire n_1_0_1285; + wire n_1_0_1286; + wire n_1_0_1287; + wire n_1_0_1288; + wire n_1_0_1289; + wire n_1_0_1290; + wire n_1_0_1291; + wire n_1_0_1292; + wire n_1_0_1293; + wire n_1_0_1294; + wire n_1_0_1295; + wire n_1_0_1296; + wire n_1_0_1297; + wire n_1_0_1298; + wire n_1_0_1299; + wire n_1_0_1300; + wire n_1_0_1301; + wire n_1_0_1302; + wire n_1_0_1303; + wire n_1_0_1304; + wire n_1_0_1305; + wire n_1_0_1306; + wire n_1_0_1307; + wire n_1_0_1308; + wire n_1_0_1309; + + INV_X1_LVT i_0_0_79 (.A(reset), .ZN(n_0_0_16)); + AND2_X1_LVT i_0_0_31 (.A1(n_0_0_16), .A2(WRd[31]), .ZN(registers[31])); + CLKBUF_X3_LVT tessent_persistent_cell_buf_extsi1227_i (.A(ts_extsi1227), + .Z(n_0)); + INV_X1_LVT i_0_0_81 (.A(Rd[1]), .ZN(n_0_0_18)); + INV_X1_LVT i_0_0_80 (.A(Rd[0]), .ZN(n_0_0_17)); + NAND3_X1_LVT i_0_0_69 (.A1(n_0_0_18), .A2(n_0_0_17), .A3(Rd[2]), .ZN(n_0_0_9)); + NAND3_X1_LVT i_0_0_41 (.A1(Rd[3]), .A2(WrReg), .A3(Rd[4]), .ZN(n_0_0_1)); + OAI21_X1_LVT i_0_0_35 (.A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_1), .ZN(n_0_28)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[28]_reg (.CK(clk), .E(n_0_28), + .SE(dftIn), .GCK(n_0_0__1)); + SDFF_X1_LVT \registers_reg[28][31] (.D(registers[31]), .SE(dftIn), .SI(n_0), + .CK(n_0_0__1), .Q(registers_28__ap[31]), .QN()); + INV_X1_LVT i_1_0_1370 (.A(Rs1[0]), .ZN(n_1_0_1306)); + NAND3_X1_LVT i_1_0_1354 (.A1(n_1_0_1306), .A2(Rs1[3]), .A3(Rs1[4]), .ZN( + n_1_0_1290)); + INV_X1_LVT i_1_0_1373 (.A(Rs1[2]), .ZN(n_1_0_1309)); + OR2_X1_LVT i_1_0_1348 (.A1(n_1_0_1309), .A2(Rs1[1]), .ZN(n_1_0_1284)); + NOR2_X1_LVT i_1_0_1347 (.A1(n_1_0_1290), .A2(n_1_0_1284), .ZN(n_1_0_1283)); + NOR4_X1_LVT i_1_0_1342 (.A1(n_1_0_1284), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), + .ZN(n_1_0_1278)); + CLKBUF_X3_LVT tessent_persistent_cell_buf_extsi1228_i (.A(ts_extsi1228), + .Z(n_1)); + INV_X1_LVT i_0_0_83 (.A(WrReg), .ZN(n_0_0_20)); + OR3_X1_LVT i_0_0_77 (.A1(n_0_0_20), .A2(Rd[4]), .A3(Rd[3]), .ZN(n_0_0_14)); + OAI21_X1_LVT i_0_0_68 (.A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_9), .ZN(n_0_4)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[4]_reg (.CK(clk), .E(n_0_4), + .SE(dftIn), .GCK(n_0_34)); + SDFF_X1_LVT \registers_reg[4][31] (.D(registers[31]), .SE(dftIn), .SI(n_1), + .CK(n_0_34), .Q(registers_4__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1320 (.A1(registers_28__ap[31]), .A2(n_1_0_1283), .B1( + n_1_0_1278), .B2(registers_4__ap[31]), .ZN(n_1_0_1256)); + NAND2_X1_LVT i_0_0_70 (.A1(n_0_0_18), .A2(n_0_0_17), .ZN(n_0_0_10)); + INV_X1_LVT i_0_0_82 (.A(Rd[4]), .ZN(n_0_0_19)); + OR3_X1_LVT i_0_0_51 (.A1(n_0_0_20), .A2(n_0_0_19), .A3(Rd[3]), .ZN(n_0_0_3)); + OR2_X1_LVT i_0_0_50 (.A1(n_0_0_3), .A2(Rd[2]), .ZN(n_0_0_2)); + OAI21_X1_LVT i_0_0_49 (.A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_2), .ZN(n_0_16)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[16]_reg (.CK(clk), .E(n_0_16), + .SE(dftIn), .GCK(n_0_46)); + SDFF_X1_LVT \registers_reg[16][31] (.D(registers[31]), .SE(dftIn), .SI( + ts_intno31), .CK(n_0_46), .Q(registers_16__ap[31]), .QN()); + INV_X1_LVT i_1_0_1371 (.A(Rs1[3]), .ZN(n_1_0_1307)); + NAND3_X1_LVT i_1_0_1363 (.A1(n_1_0_1307), .A2(n_1_0_1306), .A3(Rs1[4]), + .ZN(n_1_0_1299)); + OR2_X1_LVT i_1_0_1357 (.A1(Rs1[1]), .A2(Rs1[2]), .ZN(n_1_0_1293)); + NOR2_X1_LVT i_1_0_1331 (.A1(n_1_0_1299), .A2(n_1_0_1293), .ZN(n_1_0_1267)); + NAND2_X1_LVT i_1_0_1365 (.A1(Rs1[1]), .A2(Rs1[2]), .ZN(n_1_0_1301)); + NAND3_X1_LVT i_1_0_1344 (.A1(Rs1[4]), .A2(Rs1[3]), .A3(Rs1[0]), .ZN( + n_1_0_1280)); + NOR2_X1_LVT i_1_0_1330 (.A1(n_1_0_1301), .A2(n_1_0_1280), .ZN(n_1_0_1266)); + NAND3_X1_LVT i_0_0_63 (.A1(Rd[2]), .A2(Rd[1]), .A3(Rd[0]), .ZN(n_0_0_6)); + OAI21_X1_LVT i_0_0_32 (.A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_1), .ZN(n_0_31)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[31]_reg (.CK(clk), .E(n_0_31), + .SE(dftIn), .GCK(n_0_3)); + SDFF_X1_LVT \registers_reg[31][31] (.D(registers[31]), .SE(dftIn), .SI( + registers_4__ap[31]), .CK(n_0_3), .Q(registers_31__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1329 (.A1(registers_16__ap[31]), .A2(n_1_0_1267), .B1( + n_1_0_1266), .B2(registers_31__ap[31]), .ZN(n_1_0_1265)); + NAND3_X1_LVT i_0_0_65 (.A1(n_0_0_17), .A2(Rd[1]), .A3(Rd[2]), .ZN(n_0_0_7)); + OAI21_X1_LVT i_0_0_64 (.A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_7), .ZN(n_0_6)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[6]_reg (.CK(clk), .E(n_0_6), + .SE(dftIn), .GCK(n_0_36__0)); + SDFF_X1_LVT \registers_reg[6][31] (.D(registers[31]), .SE(dftIn), .SI( + registers_31__ap[31]), .CK(n_0_36__0), .Q(registers_6__ap[31]), .QN()); + NOR4_X1_LVT i_1_0_1364 (.A1(n_1_0_1301), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), + .ZN(n_1_0_1300)); + INV_X1_LVT i_1_0_1372 (.A(Rs1[4]), .ZN(n_1_0_1308)); + NAND3_X1_LVT i_1_0_1339 (.A1(n_1_0_1308), .A2(n_1_0_1307), .A3(Rs1[0]), + .ZN(n_1_0_1275)); + NOR2_X1_LVT i_1_0_1338 (.A1(n_1_0_1293), .A2(n_1_0_1275), .ZN(n_1_0_1274)); + CLKBUF_X3_LVT tessent_persistent_cell_buf_extsi1226_i (.A(ts_extsi1226), + .Z(n_2)); + NAND2_X1_LVT i_0_0_78 (.A1(n_0_0_18), .A2(Rd[0]), .ZN(n_0_0_15)); + OR2_X1_LVT i_0_0_76 (.A1(n_0_0_14), .A2(Rd[2]), .ZN(n_0_0_13)); + OAI21_X1_LVT i_0_0_75 (.A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_13), .ZN( + n_0_57__1)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[1]_reg (.CK(clk), .E(n_0_57__1), + .SE(dftIn), .GCK(n_0_0__0)); + SDFF_X1_LVT \registers_reg[1][31] (.D(registers[31]), .SE(dftIn), .SI(n_2), + .CK(n_0_0__0), .Q(registers_1__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1319 (.A1(registers_6__ap[31]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[31]), .ZN(n_1_0_1255)); + OAI21_X1_LVT i_0_0_42 (.A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_3), .ZN(n_0_23)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[23]_reg (.CK(clk), .E(n_0_23), + .SE(dftIn), .GCK(n_0_53)); + SDFF_X1_LVT \registers_reg[23][31] (.D(registers[31]), .SE(dftIn), .SI( + registers_1__ap[31]), .CK(n_0_53), .Q(registers_23__ap[31]), .QN()); + NAND3_X1_LVT i_1_0_1360 (.A1(n_1_0_1307), .A2(Rs1[0]), .A3(Rs1[4]), .ZN( + n_1_0_1296)); + NOR2_X1_LVT i_1_0_1328 (.A1(n_1_0_1301), .A2(n_1_0_1296), .ZN(n_1_0_1264)); + NOR2_X1_LVT i_1_0_1327 (.A1(n_1_0_1301), .A2(n_1_0_1275), .ZN(n_1_0_1263)); + OAI21_X1_LVT i_0_0_62 (.A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_6), .ZN(n_0_7)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[7]_reg (.CK(clk), .E(n_0_7), + .SE(dftIn), .GCK(n_0_37)); + SDFF_X1_LVT \registers_reg[7][31] (.D(registers[31]), .SE(dftIn), .SI( + registers_6__ap[31]), .CK(n_0_37), .Q(registers_7__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1326 (.A1(registers_23__ap[31]), .A2(n_1_0_1264), .B1( + n_1_0_1263), .B2(registers_7__ap[31]), .ZN(n_1_0_1262)); + INV_X1_LVT i_1_0_1325 (.A(n_1_0_1262), .ZN(n_1_0_1261)); + NAND2_X1_LVT i_1_0_1362 (.A1(n_1_0_1309), .A2(Rs1[1]), .ZN(n_1_0_1298)); + NOR2_X1_LVT i_1_0_1359 (.A1(n_1_0_1298), .A2(n_1_0_1296), .ZN(n_1_0_1295)); + NAND2_X1_LVT i_0_0_72 (.A1(Rd[1]), .A2(Rd[0]), .ZN(n_0_0_11)); + OAI21_X1_LVT i_0_0_46 (.A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_2), .ZN(n_0_19)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[19]_reg (.CK(clk), .E(n_0_19), + .SE(dftIn), .GCK(n_0_49)); + SDFF_X1_LVT \registers_reg[19][31] (.D(registers[31]), .SE(dftIn), .SI( + registers_23__ap[31]), .CK(n_0_49), .Q(registers_19__ap[31]), .QN()); + NAND3_X1_LVT i_0_0_67 (.A1(n_0_0_18), .A2(Rd[0]), .A3(Rd[2]), .ZN(n_0_0_8)); + OAI21_X1_LVT i_0_0_66 (.A(n_0_0_16), .B1(n_0_0_14), .B2(n_0_0_8), .ZN(n_0_5)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[5]_reg (.CK(clk), .E(n_0_5), + .SE(dftIn), .GCK(n_0_35)); + SDFF_X1_LVT \registers_reg[5][31] (.D(registers[31]), .SE(dftIn), .SI( + registers_7__ap[31]), .CK(n_0_35), .Q(registers_5__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1337 (.A1(n_1_0_1284), .A2(n_1_0_1275), .ZN(n_1_0_1273)); + AOI221_X1_LVT i_1_0_1318 (.A(n_1_0_1261), .B1(n_1_0_1295), .B2( + registers_19__ap[31]), .C1(registers_5__ap[31]), .C2(n_1_0_1273), .ZN( + n_1_0_1254)); + NAND2_X1_LVT i_0_0_74 (.A1(n_0_0_17), .A2(Rd[1]), .ZN(n_0_0_12)); + NAND3_X1_LVT i_0_0_61 (.A1(n_0_0_19), .A2(WrReg), .A3(Rd[3]), .ZN(n_0_0_5)); + OR2_X1_LVT i_0_0_60 (.A1(n_0_0_5), .A2(Rd[2]), .ZN(n_0_0_4)); + OAI21_X1_LVT i_0_0_57 (.A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_4), .ZN(n_0_10)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[10]_reg (.CK(clk), .E(n_0_10), + .SE(dftIn), .GCK(n_0_40)); + SDFF_X1_LVT \registers_reg[10][31] (.D(registers[31]), .SE(dftIn), .SI( + registers_16__ap[31]), .CK(n_0_40), .Q(registers_10__ap[31]), .QN()); + NAND3_X1_LVT i_1_0_1352 (.A1(n_1_0_1308), .A2(n_1_0_1306), .A3(Rs1[3]), + .ZN(n_1_0_1288)); + NOR2_X1_LVT i_1_0_1351 (.A1(n_1_0_1298), .A2(n_1_0_1288), .ZN(n_1_0_1287)); + NOR2_X1_LVT i_1_0_1349 (.A1(n_1_0_1298), .A2(n_1_0_1290), .ZN(n_1_0_1285)); + OR2_X1_LVT i_0_0_40 (.A1(n_0_0_1), .A2(Rd[2]), .ZN(n_0_0_0)); + OAI21_X1_LVT i_0_0_37 (.A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_0), .ZN(n_0_26)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[26]_reg (.CK(clk), .E(n_0_26), + .SE(dftIn), .GCK(n_0_56)); + SDFF_X1_LVT \registers_reg[26][31] (.D(registers[31]), .SE(dftIn), .SI( + registers_28__ap[31]), .CK(n_0_56), .Q(registers_26__ap[31]), .QN()); + OAI21_X1_LVT i_0_0_59 (.A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_4), .ZN(n_0_8)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[8]_reg (.CK(clk), .E(n_0_8), + .SE(dftIn), .GCK(n_0_38)); + SDFF_X1_LVT \registers_reg[8][31] (.D(registers[31]), .SE(dftIn), .SI( + registers_5__ap[31]), .CK(n_0_38), .Q(registers_8__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1346 (.A1(n_1_0_1293), .A2(n_1_0_1288), .ZN(n_1_0_1282)); + AOI222_X1_LVT i_1_0_1317 (.A1(registers_10__ap[31]), .A2(n_1_0_1287), + .B1(n_1_0_1285), .B2(registers_26__ap[31]), .C1(registers_8__ap[31]), + .C2(n_1_0_1282), .ZN(n_1_0_1253)); + NAND4_X1_LVT i_1_0_1316 (.A1(n_1_0_1265), .A2(n_1_0_1255), .A3(n_1_0_1254), + .A4(n_1_0_1253), .ZN(n_1_0_1252)); + NAND3_X1_LVT i_1_0_1356 (.A1(n_1_0_1308), .A2(Rs1[3]), .A3(Rs1[0]), .ZN( + n_1_0_1292)); + NOR2_X1_LVT i_1_0_1355 (.A1(n_1_0_1293), .A2(n_1_0_1292), .ZN(n_1_0_1291)); + OAI21_X1_LVT i_0_0_58 (.A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_4), .ZN(n_0_9)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[9]_reg (.CK(clk), .E(n_0_9), + .SE(dftIn), .GCK(n_0_39)); + SDFF_X1_LVT \registers_reg[9][31] (.D(registers[31]), .SE(dftIn), .SI( + registers_8__ap[31]), .CK(n_0_39), .Q(registers_9__ap[31]), .QN()); + OAI21_X1_LVT i_0_0_34 (.A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_1), .ZN(n_0_29)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[29]_reg (.CK(clk), .E(n_0_29), + .SE(dftIn), .GCK(n_0_1)); + SDFF_X1_LVT \registers_reg[29][31] (.D(registers[31]), .SE(dftIn), .SI( + registers_26__ap[31]), .CK(n_0_1), .Q(registers_29__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1340 (.A1(n_1_0_1284), .A2(n_1_0_1280), .ZN(n_1_0_1276)); + AOI221_X1_LVT i_1_0_1315 (.A(n_1_0_1252), .B1(n_1_0_1291), .B2( + registers_9__ap[31]), .C1(registers_29__ap[31]), .C2(n_1_0_1276), .ZN( + n_1_0_1251)); + OAI21_X1_LVT i_0_0_47 (.A(n_0_0_16), .B1(n_0_0_12), .B2(n_0_0_2), .ZN(n_0_18)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[18]_reg (.CK(clk), .E(n_0_18), + .SE(dftIn), .GCK(n_0_48)); + SDFF_X1_LVT \registers_reg[18][31] (.D(registers[31]), .SE(dftIn), .SI( + registers_19__ap[31]), .CK(n_0_48), .Q(registers_18__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1361 (.A1(n_1_0_1299), .A2(n_1_0_1298), .ZN(n_1_0_1297)); + NOR2_X1_LVT i_1_0_1336 (.A1(n_1_0_1301), .A2(n_1_0_1290), .ZN(n_1_0_1272)); + OAI21_X1_LVT i_0_0_33 (.A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_1), .ZN(n_0_30)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[30]_reg (.CK(clk), .E(n_0_30), + .SE(dftIn), .GCK(n_0_2)); + SDFF_X1_LVT \registers_reg[30][31] (.D(registers[31]), .SE(dftIn), .SI( + registers_29__ap[31]), .CK(n_0_2), .Q(registers_30__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1314 (.A1(registers_18__ap[31]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[31]), .ZN(n_1_0_1250)); + OAI21_X1_LVT i_0_0_39 (.A(n_0_0_16), .B1(n_0_0_10), .B2(n_0_0_0), .ZN(n_0_24)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[24]_reg (.CK(clk), .E(n_0_24), + .SE(dftIn), .GCK(n_0_54)); + SDFF_X1_LVT \registers_reg[24][31] (.D(registers[31]), .SE(dftIn), .SI( + registers_30__ap[31]), .CK(n_0_54), .Q(registers_24__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1353 (.A1(n_1_0_1293), .A2(n_1_0_1290), .ZN(n_1_0_1289)); + NOR2_X1_LVT i_1_0_1324 (.A1(n_1_0_1288), .A2(n_1_0_1284), .ZN(n_1_0_1260)); + OAI21_X1_LVT i_0_0_55 (.A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_5), .ZN(n_0_12)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[12]_reg (.CK(clk), .E(n_0_12), + .SE(dftIn), .GCK(n_0_42)); + SDFF_X1_LVT \registers_reg[12][31] (.D(registers[31]), .SE(dftIn), .SI( + registers_10__ap[31]), .CK(n_0_42), .Q(registers_12__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1313 (.A1(registers_24__ap[31]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[31]), .ZN(n_1_0_1249)); + OAI21_X1_LVT i_0_0_43 (.A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_3), .ZN(n_0_22)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[22]_reg (.CK(clk), .E(n_0_22), + .SE(dftIn), .GCK(n_0_52)); + SDFF_X1_LVT \registers_reg[22][31] (.D(registers[31]), .SE(dftIn), .SI( + registers_18__ap[31]), .CK(n_0_52), .Q(registers_22__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1358 (.A1(n_1_0_1301), .A2(n_1_0_1299), .ZN(n_1_0_1294)); + NOR2_X1_LVT i_1_0_1323 (.A1(n_1_0_1296), .A2(n_1_0_1284), .ZN(n_1_0_1259)); + OAI21_X1_LVT i_0_0_44 (.A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_3), .ZN(n_0_21)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[21]_reg (.CK(clk), .E(n_0_21), + .SE(dftIn), .GCK(n_0_51)); + SDFF_X1_LVT \registers_reg[21][31] (.D(registers[31]), .SE(dftIn), .SI( + registers_22__ap[31]), .CK(n_0_51), .Q(registers_21__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1312 (.A1(registers_22__ap[31]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[31]), .ZN(n_1_0_1248)); + NAND3_X1_LVT i_1_0_1311 (.A1(n_1_0_1250), .A2(n_1_0_1249), .A3(n_1_0_1248), + .ZN(n_1_0_1247)); + NOR2_X1_LVT i_1_0_1335 (.A1(n_1_0_1296), .A2(n_1_0_1293), .ZN(n_1_0_1271)); + OAI21_X1_LVT i_0_0_48 (.A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_2), .ZN(n_0_17)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[17]_reg (.CK(clk), .E(n_0_17), + .SE(dftIn), .GCK(n_0_47)); + SDFF_X1_LVT \registers_reg[17][31] (.D(registers[31]), .SE(dftIn), .SI( + registers_21__ap[31]), .CK(n_0_47), .Q(registers_17__ap[31]), .QN()); + OAI21_X1_LVT i_0_0_45 (.A(n_0_0_16), .B1(n_0_0_9), .B2(n_0_0_3), .ZN(n_0_20)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[20]_reg (.CK(clk), .E(n_0_20), + .SE(dftIn), .GCK(n_0_50)); + SDFF_X1_LVT \registers_reg[20][31] (.D(registers[31]), .SE(dftIn), .SI( + registers_17__ap[31]), .CK(n_0_50), .Q(registers_20__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1345 (.A1(n_1_0_1299), .A2(n_1_0_1284), .ZN(n_1_0_1281)); + AOI221_X1_LVT i_1_0_1310 (.A(n_1_0_1247), .B1(n_1_0_1271), .B2( + registers_17__ap[31]), .C1(registers_20__ap[31]), .C2(n_1_0_1281), + .ZN(n_1_0_1246)); + OAI21_X1_LVT i_0_0_36 (.A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_0), .ZN(n_0_27)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[27]_reg (.CK(clk), .E(n_0_27), + .SE(dftIn), .GCK(n_0_57__0)); + SDFF_X1_LVT \registers_reg[27][31] (.D(registers[31]), .SE(dftIn), .SI( + registers_24__ap[31]), .CK(n_0_57__0), .Q(registers_27__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1343 (.A1(n_1_0_1298), .A2(n_1_0_1280), .ZN(n_1_0_1279)); + NOR2_X1_LVT i_1_0_1334 (.A1(n_1_0_1298), .A2(n_1_0_1292), .ZN(n_1_0_1270)); + OAI21_X1_LVT i_0_0_56 (.A(n_0_0_16), .B1(n_0_0_11), .B2(n_0_0_4), .ZN(n_0_11)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[11]_reg (.CK(clk), .E(n_0_11), + .SE(dftIn), .GCK(n_0_41__0)); + SDFF_X1_LVT \registers_reg[11][31] (.D(registers[31]), .SE(dftIn), .SI( + registers_12__ap[31]), .CK(n_0_41__0), .Q(registers_11__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1309 (.A1(registers_27__ap[31]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[31]), .ZN(n_1_0_1245)); + OAI21_X1_LVT i_0_0_54 (.A(n_0_0_16), .B1(n_0_0_8), .B2(n_0_0_5), .ZN(n_0_13)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[13]_reg (.CK(clk), .E(n_0_13), + .SE(dftIn), .GCK(n_0_43)); + SDFF_X1_LVT \registers_reg[13][31] (.D(registers[31]), .SE(dftIn), .SI( + registers_11__ap[31]), .CK(n_0_43), .Q(registers_13__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1341 (.A1(n_1_0_1292), .A2(n_1_0_1284), .ZN(n_1_0_1277)); + NOR2_X1_LVT i_1_0_1333 (.A1(n_1_0_1293), .A2(n_1_0_1280), .ZN(n_1_0_1269)); + OAI21_X1_LVT i_0_0_38 (.A(n_0_0_16), .B1(n_0_0_15), .B2(n_0_0_0), .ZN(n_0_25)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[25]_reg (.CK(clk), .E(n_0_25), + .SE(dftIn), .GCK(n_0_55)); + SDFF_X1_LVT \registers_reg[25][31] (.D(registers[31]), .SE(dftIn), .SI( + registers_27__ap[31]), .CK(n_0_55), .Q(registers_25__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1308 (.A1(registers_13__ap[31]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[31]), .ZN(n_1_0_1244)); + OAI21_X1_LVT i_0_0_52 (.A(n_0_0_16), .B1(n_0_0_6), .B2(n_0_0_5), .ZN(n_0_15)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[15]_reg (.CK(clk), .E(n_0_15), + .SE(dftIn), .GCK(n_0_45)); + SDFF_X1_LVT \registers_reg[15][31] (.D(registers[31]), .SE(dftIn), .SI( + registers_13__ap[31]), .CK(n_0_45), .Q(registers_15__ap[31]), .QN()); + NOR2_X1_LVT i_1_0_1350 (.A1(n_1_0_1301), .A2(n_1_0_1292), .ZN(n_1_0_1286)); + NOR2_X1_LVT i_1_0_1322 (.A1(n_1_0_1301), .A2(n_1_0_1288), .ZN(n_1_0_1258)); + OAI21_X1_LVT i_0_0_53 (.A(n_0_0_16), .B1(n_0_0_7), .B2(n_0_0_5), .ZN(n_0_14)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[14]_reg (.CK(clk), .E(n_0_14), + .SE(dftIn), .GCK(n_0_44)); + SDFF_X1_LVT \registers_reg[14][31] (.D(registers[31]), .SE(dftIn), .SI( + registers_15__ap[31]), .CK(n_0_44), .Q(registers_14__ap[31]), .QN()); + AOI22_X1_LVT i_1_0_1307 (.A1(registers_15__ap[31]), .A2(n_1_0_1286), .B1( + n_1_0_1258), .B2(registers_14__ap[31]), .ZN(n_1_0_1243)); + NAND3_X1_LVT i_1_0_1306 (.A1(n_1_0_1245), .A2(n_1_0_1244), .A3(n_1_0_1243), + .ZN(n_1_0_1242)); + NOR2_X1_LVT i_1_0_1321 (.A1(n_1_0_1298), .A2(n_1_0_1275), .ZN(n_1_0_1257)); + OAI21_X1_LVT i_0_0_71 (.A(n_0_0_16), .B1(n_0_0_13), .B2(n_0_0_11), .ZN( + n_0_36__1)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[3]_reg (.CK(clk), .E(n_0_36__1), + .SE(dftIn), .GCK(n_0_33)); + SDFF_X1_LVT \registers_reg[3][31] (.D(registers[31]), .SE(dftIn), .SI( + registers_9__ap[31]), .CK(n_0_33), .Q(registers_3__ap[31]), .QN()); + OAI21_X1_LVT i_0_0_73 (.A(n_0_0_16), .B1(n_0_0_13), .B2(n_0_0_12), .ZN( + n_0_41__1)); + CLKGATETST_X1_LVT \clk_gate_registers_reg[2]_reg (.CK(clk), .E(n_0_41__1), + .SE(dftIn), .GCK(n_0_32)); + SDFF_X1_LVT \registers_reg[2][31] (.D(registers[31]), .SE(dftIn), .SI( + registers_25__ap[31]), .CK(n_0_32), .Q(registers_2__ap[31]), .QN()); + NOR4_X1_LVT i_1_0_1332 (.A1(n_1_0_1298), .A2(Rs1[0]), .A3(Rs1[3]), .A4(Rs1[4]), + .ZN(n_1_0_1268)); + AOI221_X1_LVT i_1_0_1305 (.A(n_1_0_1242), .B1(n_1_0_1257), .B2( + registers_3__ap[31]), .C1(registers_2__ap[31]), .C2(n_1_0_1268), .ZN( + n_1_0_1241)); + NAND4_X1_LVT i_1_0_1304 (.A1(n_1_0_1256), .A2(n_1_0_1251), .A3(n_1_0_1246), + .A4(n_1_0_1241), .ZN(RRs1[31])); + AND2_X1_LVT i_0_0_30 (.A1(n_0_0_16), .A2(WRd[30]), .ZN(registers[30])); + SDFF_X1_LVT \registers_reg[28][30] (.D(registers[30]), .SE(dftIn), .SI( + registers_2__ap[31]), .CK(n_0_0__1), .Q(registers_28__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[17][30] (.D(registers[30]), .SE(dftIn), .SI( + registers_20__ap[31]), .CK(n_0_47), .Q(registers_17__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1300 (.A1(registers_28__ap[30]), .A2(n_1_0_1283), .B1( + n_1_0_1271), .B2(registers_17__ap[30]), .ZN(n_1_0_1237)); + SDFF_X1_LVT \registers_reg[16][30] (.D(registers[30]), .SE(dftIn), .SI( + registers_14__ap[31]), .CK(n_0_46), .Q(registers_16__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[31][30] (.D(registers[30]), .SE(dftIn), .SI( + registers_3__ap[31]), .CK(n_0_3), .Q(registers_31__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1303 (.A1(registers_16__ap[30]), .A2(n_1_0_1267), .B1( + n_1_0_1266), .B2(registers_31__ap[30]), .ZN(n_1_0_1240)); + SDFF_X1_LVT \registers_reg[6][30] (.D(registers[30]), .SE(dftIn), .SI( + registers_31__ap[30]), .CK(n_0_36__0), .Q(registers_6__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[1][30] (.D(registers[30]), .SE(dftIn), .SI( + registers_17__ap[30]), .CK(n_0_0__0), .Q(registers_1__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1299 (.A1(registers_6__ap[30]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[30]), .ZN(n_1_0_1236)); + SDFF_X1_LVT \registers_reg[23][30] (.D(registers[30]), .SE(dftIn), .SI( + registers_1__ap[30]), .CK(n_0_53), .Q(registers_23__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[7][30] (.D(registers[30]), .SE(dftIn), .SI( + registers_6__ap[30]), .CK(n_0_37), .Q(registers_7__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1302 (.A1(registers_23__ap[30]), .A2(n_1_0_1264), .B1( + n_1_0_1263), .B2(registers_7__ap[30]), .ZN(n_1_0_1239)); + INV_X1_LVT i_1_0_1301 (.A(n_1_0_1239), .ZN(n_1_0_1238)); + SDFF_X1_LVT \registers_reg[19][30] (.D(registers[30]), .SE(dftIn), .SI( + registers_23__ap[30]), .CK(n_0_49), .Q(registers_19__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[5][30] (.D(registers[30]), .SE(dftIn), .SI( + registers_7__ap[30]), .CK(n_0_35), .Q(registers_5__ap[30]), .QN()); + AOI221_X1_LVT i_1_0_1298 (.A(n_1_0_1238), .B1(n_1_0_1295), .B2( + registers_19__ap[30]), .C1(registers_5__ap[30]), .C2(n_1_0_1273), .ZN( + n_1_0_1235)); + SDFF_X1_LVT \registers_reg[10][30] (.D(registers[30]), .SE(dftIn), .SI( + registers_16__ap[30]), .CK(n_0_40), .Q(registers_10__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[26][30] (.D(registers[30]), .SE(dftIn), .SI( + registers_28__ap[30]), .CK(n_0_56), .Q(registers_26__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[8][30] (.D(registers[30]), .SE(dftIn), .SI( + registers_5__ap[30]), .CK(n_0_38), .Q(registers_8__ap[30]), .QN()); + AOI222_X1_LVT i_1_0_1297 (.A1(registers_10__ap[30]), .A2(n_1_0_1287), + .B1(n_1_0_1285), .B2(registers_26__ap[30]), .C1(registers_8__ap[30]), + .C2(n_1_0_1282), .ZN(n_1_0_1234)); + NAND4_X1_LVT i_1_0_1296 (.A1(n_1_0_1240), .A2(n_1_0_1236), .A3(n_1_0_1235), + .A4(n_1_0_1234), .ZN(n_1_0_1233)); + SDFF_X1_LVT \registers_reg[9][30] (.D(registers[30]), .SE(dftIn), .SI( + registers_8__ap[30]), .CK(n_0_39), .Q(registers_9__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[29][30] (.D(registers[30]), .SE(dftIn), .SI( + registers_26__ap[30]), .CK(n_0_1), .Q(registers_29__ap[30]), .QN()); + AOI221_X1_LVT i_1_0_1295 (.A(n_1_0_1233), .B1(n_1_0_1291), .B2( + registers_9__ap[30]), .C1(registers_29__ap[30]), .C2(n_1_0_1276), .ZN( + n_1_0_1232)); + SDFF_X1_LVT \registers_reg[18][30] (.D(registers[30]), .SE(dftIn), .SI( + registers_19__ap[30]), .CK(n_0_48), .Q(registers_18__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[30][30] (.D(registers[30]), .SE(dftIn), .SI( + registers_29__ap[30]), .CK(n_0_2), .Q(registers_30__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1294 (.A1(registers_18__ap[30]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[30]), .ZN(n_1_0_1231)); + SDFF_X1_LVT \registers_reg[20][30] (.D(registers[30]), .SE(dftIn), .SI( + registers_18__ap[30]), .CK(n_0_50), .Q(registers_20__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[4][30] (.D(registers[30]), .SE(dftIn), .SI( + registers_9__ap[30]), .CK(n_0_34), .Q(registers_4__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1293 (.A1(registers_20__ap[30]), .A2(n_1_0_1281), .B1( + n_1_0_1278), .B2(registers_4__ap[30]), .ZN(n_1_0_1230)); + SDFF_X1_LVT \registers_reg[22][30] (.D(registers[30]), .SE(dftIn), .SI( + registers_20__ap[30]), .CK(n_0_52), .Q(registers_22__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[21][30] (.D(registers[30]), .SE(dftIn), .SI( + registers_22__ap[30]), .CK(n_0_51), .Q(registers_21__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1292 (.A1(registers_22__ap[30]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[30]), .ZN(n_1_0_1229)); + NAND3_X1_LVT i_1_0_1291 (.A1(n_1_0_1231), .A2(n_1_0_1230), .A3(n_1_0_1229), + .ZN(n_1_0_1228)); + SDFF_X1_LVT \registers_reg[24][30] (.D(registers[30]), .SE(dftIn), .SI( + registers_30__ap[30]), .CK(n_0_54), .Q(registers_24__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[12][30] (.D(registers[30]), .SE(dftIn), .SI( + registers_10__ap[30]), .CK(n_0_42), .Q(registers_12__ap[30]), .QN()); + AOI221_X1_LVT i_1_0_1290 (.A(n_1_0_1228), .B1(n_1_0_1289), .B2( + registers_24__ap[30]), .C1(registers_12__ap[30]), .C2(n_1_0_1260), + .ZN(n_1_0_1227)); + SDFF_X1_LVT \registers_reg[27][30] (.D(registers[30]), .SE(dftIn), .SI( + registers_24__ap[30]), .CK(n_0_57__0), .Q(registers_27__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[11][30] (.D(registers[30]), .SE(dftIn), .SI( + registers_12__ap[30]), .CK(n_0_41__0), .Q(registers_11__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1289 (.A1(registers_27__ap[30]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[30]), .ZN(n_1_0_1226)); + SDFF_X1_LVT \registers_reg[13][30] (.D(registers[30]), .SE(dftIn), .SI( + registers_11__ap[30]), .CK(n_0_43), .Q(registers_13__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[25][30] (.D(registers[30]), .SE(dftIn), .SI( + registers_27__ap[30]), .CK(n_0_55), .Q(registers_25__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1288 (.A1(registers_13__ap[30]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[30]), .ZN(n_1_0_1225)); + SDFF_X1_LVT \registers_reg[15][30] (.D(registers[30]), .SE(dftIn), .SI( + registers_13__ap[30]), .CK(n_0_45), .Q(registers_15__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[14][30] (.D(registers[30]), .SE(dftIn), .SI( + registers_15__ap[30]), .CK(n_0_44), .Q(registers_14__ap[30]), .QN()); + AOI22_X1_LVT i_1_0_1287 (.A1(registers_15__ap[30]), .A2(n_1_0_1286), .B1( + n_1_0_1258), .B2(registers_14__ap[30]), .ZN(n_1_0_1224)); + NAND3_X1_LVT i_1_0_1286 (.A1(n_1_0_1226), .A2(n_1_0_1225), .A3(n_1_0_1224), + .ZN(n_1_0_1223)); + SDFF_X1_LVT \registers_reg[3][30] (.D(registers[30]), .SE(dftIn), .SI( + registers_4__ap[30]), .CK(n_0_33), .Q(registers_3__ap[30]), .QN()); + SDFF_X1_LVT \registers_reg[2][30] (.D(registers[30]), .SE(dftIn), .SI( + registers_25__ap[30]), .CK(n_0_32), .Q(registers_2__ap[30]), .QN()); + AOI221_X1_LVT i_1_0_1285 (.A(n_1_0_1223), .B1(n_1_0_1257), .B2( + registers_3__ap[30]), .C1(registers_2__ap[30]), .C2(n_1_0_1268), .ZN( + n_1_0_1222)); + NAND4_X1_LVT i_1_0_1284 (.A1(n_1_0_1237), .A2(n_1_0_1232), .A3(n_1_0_1227), + .A4(n_1_0_1222), .ZN(RRs1[30])); + AND2_X1_LVT i_0_0_29 (.A1(n_0_0_16), .A2(WRd[29]), .ZN(registers[29])); + SDFF_X1_LVT \registers_reg[28][29] (.D(registers[29]), .SE(dftIn), .SI( + registers_2__ap[30]), .CK(n_0_0__1), .Q(registers_28__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[8][29] (.D(registers[29]), .SE(dftIn), .SI( + registers_3__ap[30]), .CK(n_0_38), .Q(registers_8__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1282 (.A1(registers_28__ap[29]), .A2(n_1_0_1283), .B1( + n_1_0_1282), .B2(registers_8__ap[29]), .ZN(n_1_0_1220)); + SDFF_X1_LVT \registers_reg[31][29] (.D(registers[29]), .SE(dftIn), .SI( + registers_8__ap[29]), .CK(n_0_3), .Q(registers_31__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[7][29] (.D(registers[29]), .SE(dftIn), .SI( + registers_31__ap[29]), .CK(n_0_37), .Q(registers_7__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1283 (.A1(registers_31__ap[29]), .A2(n_1_0_1266), .B1( + n_1_0_1263), .B2(registers_7__ap[29]), .ZN(n_1_0_1221)); + SDFF_X1_LVT \registers_reg[24][29] (.D(registers[29]), .SE(dftIn), .SI( + registers_28__ap[29]), .CK(n_0_54), .Q(registers_24__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[20][29] (.D(registers[29]), .SE(dftIn), .SI( + registers_21__ap[30]), .CK(n_0_50), .Q(registers_20__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1281 (.A1(registers_24__ap[29]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[29]), .ZN(n_1_0_1219)); + SDFF_X1_LVT \registers_reg[19][29] (.D(registers[29]), .SE(dftIn), .SI( + registers_20__ap[29]), .CK(n_0_49), .Q(registers_19__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[4][29] (.D(registers[29]), .SE(dftIn), .SI( + registers_7__ap[29]), .CK(n_0_34), .Q(registers_4__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1280 (.A1(registers_19__ap[29]), .A2(n_1_0_1295), .B1( + n_1_0_1278), .B2(registers_4__ap[29]), .ZN(n_1_0_1218)); + NAND3_X1_LVT i_1_0_1279 (.A1(n_1_0_1221), .A2(n_1_0_1219), .A3(n_1_0_1218), + .ZN(n_1_0_1217)); + SDFF_X1_LVT \registers_reg[23][29] (.D(registers[29]), .SE(dftIn), .SI( + registers_19__ap[29]), .CK(n_0_53), .Q(registers_23__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[29][29] (.D(registers[29]), .SE(dftIn), .SI( + registers_24__ap[29]), .CK(n_0_1), .Q(registers_29__ap[29]), .QN()); + AOI221_X1_LVT i_1_0_1278 (.A(n_1_0_1217), .B1(n_1_0_1264), .B2( + registers_23__ap[29]), .C1(registers_29__ap[29]), .C2(n_1_0_1276), + .ZN(n_1_0_1216)); + SDFF_X1_LVT \registers_reg[10][29] (.D(registers[29]), .SE(dftIn), .SI( + registers_14__ap[30]), .CK(n_0_40), .Q(registers_10__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[26][29] (.D(registers[29]), .SE(dftIn), .SI( + registers_29__ap[29]), .CK(n_0_56), .Q(registers_26__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[25][29] (.D(registers[29]), .SE(dftIn), .SI( + registers_26__ap[29]), .CK(n_0_55), .Q(registers_25__ap[29]), .QN()); + AOI222_X1_LVT i_1_0_1277 (.A1(registers_10__ap[29]), .A2(n_1_0_1287), + .B1(n_1_0_1285), .B2(registers_26__ap[29]), .C1(registers_25__ap[29]), + .C2(n_1_0_1269), .ZN(n_1_0_1215)); + NAND3_X1_LVT i_1_0_1276 (.A1(n_1_0_1220), .A2(n_1_0_1216), .A3(n_1_0_1215), + .ZN(n_1_0_1214)); + SDFF_X1_LVT \registers_reg[21][29] (.D(registers[29]), .SE(dftIn), .SI( + registers_23__ap[29]), .CK(n_0_51), .Q(registers_21__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[13][29] (.D(registers[29]), .SE(dftIn), .SI( + registers_10__ap[29]), .CK(n_0_43), .Q(registers_13__ap[29]), .QN()); + AOI221_X1_LVT i_1_0_1275 (.A(n_1_0_1214), .B1(n_1_0_1259), .B2( + registers_21__ap[29]), .C1(registers_13__ap[29]), .C2(n_1_0_1277), + .ZN(n_1_0_1213)); + SDFF_X1_LVT \registers_reg[18][29] (.D(registers[29]), .SE(dftIn), .SI( + registers_21__ap[29]), .CK(n_0_48), .Q(registers_18__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[30][29] (.D(registers[29]), .SE(dftIn), .SI( + registers_25__ap[29]), .CK(n_0_2), .Q(registers_30__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1274 (.A1(registers_18__ap[29]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[29]), .ZN(n_1_0_1212)); + SDFF_X1_LVT \registers_reg[17][29] (.D(registers[29]), .SE(dftIn), .SI( + registers_18__ap[29]), .CK(n_0_47), .Q(registers_17__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[12][29] (.D(registers[29]), .SE(dftIn), .SI( + registers_13__ap[29]), .CK(n_0_42), .Q(registers_12__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1273 (.A1(registers_17__ap[29]), .A2(n_1_0_1271), .B1( + n_1_0_1260), .B2(registers_12__ap[29]), .ZN(n_1_0_1211)); + SDFF_X1_LVT \registers_reg[15][29] (.D(registers[29]), .SE(dftIn), .SI( + registers_12__ap[29]), .CK(n_0_45), .Q(registers_15__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[16][29] (.D(registers[29]), .SE(dftIn), .SI( + registers_15__ap[29]), .CK(n_0_46), .Q(registers_16__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1272 (.A1(registers_15__ap[29]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[29]), .ZN(n_1_0_1210)); + NAND3_X1_LVT i_1_0_1271 (.A1(n_1_0_1212), .A2(n_1_0_1211), .A3(n_1_0_1210), + .ZN(n_1_0_1209)); + SDFF_X1_LVT \registers_reg[22][29] (.D(registers[29]), .SE(dftIn), .SI( + registers_17__ap[29]), .CK(n_0_52), .Q(registers_22__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[5][29] (.D(registers[29]), .SE(dftIn), .SI( + registers_4__ap[29]), .CK(n_0_35), .Q(registers_5__ap[29]), .QN()); + AOI221_X1_LVT i_1_0_1270 (.A(n_1_0_1209), .B1(n_1_0_1294), .B2( + registers_22__ap[29]), .C1(registers_5__ap[29]), .C2(n_1_0_1273), .ZN( + n_1_0_1208)); + SDFF_X1_LVT \registers_reg[9][29] (.D(registers[29]), .SE(dftIn), .SI( + registers_5__ap[29]), .CK(n_0_39), .Q(registers_9__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[1][29] (.D(registers[29]), .SE(dftIn), .SI( + registers_22__ap[29]), .CK(n_0_0__0), .Q(registers_1__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1269 (.A1(registers_9__ap[29]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[29]), .ZN(n_1_0_1207)); + SDFF_X1_LVT \registers_reg[6][29] (.D(registers[29]), .SE(dftIn), .SI( + registers_9__ap[29]), .CK(n_0_36__0), .Q(registers_6__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[14][29] (.D(registers[29]), .SE(dftIn), .SI( + registers_16__ap[29]), .CK(n_0_44), .Q(registers_14__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1268 (.A1(registers_6__ap[29]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[29]), .ZN(n_1_0_1206)); + SDFF_X1_LVT \registers_reg[27][29] (.D(registers[29]), .SE(dftIn), .SI( + registers_30__ap[29]), .CK(n_0_57__0), .Q(registers_27__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[11][29] (.D(registers[29]), .SE(dftIn), .SI( + registers_14__ap[29]), .CK(n_0_41__0), .Q(registers_11__ap[29]), .QN()); + AOI22_X1_LVT i_1_0_1267 (.A1(registers_27__ap[29]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[29]), .ZN(n_1_0_1205)); + NAND3_X1_LVT i_1_0_1266 (.A1(n_1_0_1207), .A2(n_1_0_1206), .A3(n_1_0_1205), + .ZN(n_1_0_1204)); + SDFF_X1_LVT \registers_reg[3][29] (.D(registers[29]), .SE(dftIn), .SI( + registers_6__ap[29]), .CK(n_0_33), .Q(registers_3__ap[29]), .QN()); + SDFF_X1_LVT \registers_reg[2][29] (.D(registers[29]), .SE(dftIn), .SI( + registers_27__ap[29]), .CK(n_0_32), .Q(registers_2__ap[29]), .QN()); + AOI221_X1_LVT i_1_0_1265 (.A(n_1_0_1204), .B1(n_1_0_1257), .B2( + registers_3__ap[29]), .C1(registers_2__ap[29]), .C2(n_1_0_1268), .ZN( + n_1_0_1203)); + NAND3_X1_LVT i_1_0_1264 (.A1(n_1_0_1213), .A2(n_1_0_1208), .A3(n_1_0_1203), + .ZN(RRs1[29])); + AND2_X1_LVT i_0_0_28 (.A1(n_0_0_16), .A2(WRd[28]), .ZN(registers[28])); + SDFF_X1_LVT \registers_reg[15][28] (.D(registers[28]), .SE(dftIn), .SI( + registers_11__ap[29]), .CK(n_0_45), .Q(registers_15__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[26][28] (.D(registers[28]), .SE(dftIn), .SI( + registers_2__ap[29]), .CK(n_0_56), .Q(registers_26__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[22][28] (.D(registers[28]), .SE(dftIn), .SI( + registers_1__ap[29]), .CK(n_0_52), .Q(registers_22__ap[28]), .QN()); + AOI222_X1_LVT i_1_0_1263 (.A1(registers_15__ap[28]), .A2(n_1_0_1286), + .B1(n_1_0_1285), .B2(registers_26__ap[28]), .C1(registers_22__ap[28]), + .C2(n_1_0_1294), .ZN(n_1_0_1202)); + SDFF_X1_LVT \registers_reg[5][28] (.D(registers[28]), .SE(dftIn), .SI( + registers_3__ap[29]), .CK(n_0_35), .Q(registers_5__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[12][28] (.D(registers[28]), .SE(dftIn), .SI( + registers_15__ap[28]), .CK(n_0_42), .Q(registers_12__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1262 (.A1(registers_5__ap[28]), .A2(n_1_0_1273), .B1( + n_1_0_1260), .B2(registers_12__ap[28]), .ZN(n_1_0_1201)); + SDFF_X1_LVT \registers_reg[28][28] (.D(registers[28]), .SE(dftIn), .SI( + registers_26__ap[28]), .CK(n_0_0__1), .Q(registers_28__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[14][28] (.D(registers[28]), .SE(dftIn), .SI( + registers_12__ap[28]), .CK(n_0_44), .Q(registers_14__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1261 (.A1(registers_28__ap[28]), .A2(n_1_0_1283), .B1( + n_1_0_1258), .B2(registers_14__ap[28]), .ZN(n_1_0_1200)); + SDFF_X1_LVT \registers_reg[17][28] (.D(registers[28]), .SE(dftIn), .SI( + registers_22__ap[28]), .CK(n_0_47), .Q(registers_17__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[2][28] (.D(registers[28]), .SE(dftIn), .SI( + registers_28__ap[28]), .CK(n_0_32), .Q(registers_2__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1260 (.A1(registers_17__ap[28]), .A2(n_1_0_1271), .B1( + n_1_0_1268), .B2(registers_2__ap[28]), .ZN(n_1_0_1199)); + NAND3_X1_LVT i_1_0_1259 (.A1(n_1_0_1201), .A2(n_1_0_1200), .A3(n_1_0_1199), + .ZN(n_1_0_1198)); + SDFF_X1_LVT \registers_reg[9][28] (.D(registers[28]), .SE(dftIn), .SI( + registers_5__ap[28]), .CK(n_0_39), .Q(registers_9__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[29][28] (.D(registers[28]), .SE(dftIn), .SI( + registers_2__ap[28]), .CK(n_0_1), .Q(registers_29__ap[28]), .QN()); + AOI221_X1_LVT i_1_0_1258 (.A(n_1_0_1198), .B1(n_1_0_1291), .B2( + registers_9__ap[28]), .C1(registers_29__ap[28]), .C2(n_1_0_1276), .ZN( + n_1_0_1197)); + SDFF_X1_LVT \registers_reg[13][28] (.D(registers[28]), .SE(dftIn), .SI( + registers_14__ap[28]), .CK(n_0_43), .Q(registers_13__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[25][28] (.D(registers[28]), .SE(dftIn), .SI( + registers_29__ap[28]), .CK(n_0_55), .Q(registers_25__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1257 (.A1(registers_13__ap[28]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[28]), .ZN(n_1_0_1196)); + NAND3_X1_LVT i_1_0_1256 (.A1(n_1_0_1202), .A2(n_1_0_1197), .A3(n_1_0_1196), + .ZN(n_1_0_1195)); + SDFF_X1_LVT \registers_reg[4][28] (.D(registers[28]), .SE(dftIn), .SI( + registers_9__ap[28]), .CK(n_0_34), .Q(registers_4__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[20][28] (.D(registers[28]), .SE(dftIn), .SI( + registers_17__ap[28]), .CK(n_0_50), .Q(registers_20__ap[28]), .QN()); + AOI221_X1_LVT i_1_0_1255 (.A(n_1_0_1195), .B1(n_1_0_1278), .B2( + registers_4__ap[28]), .C1(registers_20__ap[28]), .C2(n_1_0_1281), .ZN( + n_1_0_1194)); + SDFF_X1_LVT \registers_reg[1][28] (.D(registers[28]), .SE(dftIn), .SI( + registers_20__ap[28]), .CK(n_0_0__0), .Q(registers_1__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[23][28] (.D(registers[28]), .SE(dftIn), .SI( + registers_1__ap[28]), .CK(n_0_53), .Q(registers_23__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1254 (.A1(registers_1__ap[28]), .A2(n_1_0_1274), .B1( + n_1_0_1264), .B2(registers_23__ap[28]), .ZN(n_1_0_1193)); + SDFF_X1_LVT \registers_reg[10][28] (.D(registers[28]), .SE(dftIn), .SI( + registers_13__ap[28]), .CK(n_0_40), .Q(registers_10__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[21][28] (.D(registers[28]), .SE(dftIn), .SI( + registers_23__ap[28]), .CK(n_0_51), .Q(registers_21__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1253 (.A1(registers_10__ap[28]), .A2(n_1_0_1287), .B1( + n_1_0_1259), .B2(registers_21__ap[28]), .ZN(n_1_0_1192)); + SDFF_X1_LVT \registers_reg[6][28] (.D(registers[28]), .SE(dftIn), .SI( + registers_4__ap[28]), .CK(n_0_36__0), .Q(registers_6__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[30][28] (.D(registers[28]), .SE(dftIn), .SI( + registers_25__ap[28]), .CK(n_0_2), .Q(registers_30__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1252 (.A1(registers_6__ap[28]), .A2(n_1_0_1300), .B1( + n_1_0_1272), .B2(registers_30__ap[28]), .ZN(n_1_0_1191)); + NAND3_X1_LVT i_1_0_1251 (.A1(n_1_0_1193), .A2(n_1_0_1192), .A3(n_1_0_1191), + .ZN(n_1_0_1190)); + SDFF_X1_LVT \registers_reg[8][28] (.D(registers[28]), .SE(dftIn), .SI( + registers_6__ap[28]), .CK(n_0_38), .Q(registers_8__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[24][28] (.D(registers[28]), .SE(dftIn), .SI( + registers_30__ap[28]), .CK(n_0_54), .Q(registers_24__ap[28]), .QN()); + AOI221_X1_LVT i_1_0_1250 (.A(n_1_0_1190), .B1(n_1_0_1282), .B2( + registers_8__ap[28]), .C1(registers_24__ap[28]), .C2(n_1_0_1289), .ZN( + n_1_0_1189)); + SDFF_X1_LVT \registers_reg[16][28] (.D(registers[28]), .SE(dftIn), .SI( + registers_10__ap[28]), .CK(n_0_46), .Q(registers_16__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[3][28] (.D(registers[28]), .SE(dftIn), .SI( + registers_8__ap[28]), .CK(n_0_33), .Q(registers_3__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1249 (.A1(registers_16__ap[28]), .A2(n_1_0_1267), .B1( + n_1_0_1257), .B2(registers_3__ap[28]), .ZN(n_1_0_1188)); + SDFF_X1_LVT \registers_reg[11][28] (.D(registers[28]), .SE(dftIn), .SI( + registers_16__ap[28]), .CK(n_0_41__0), .Q(registers_11__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[31][28] (.D(registers[28]), .SE(dftIn), .SI( + registers_3__ap[28]), .CK(n_0_3), .Q(registers_31__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1248 (.A1(registers_11__ap[28]), .A2(n_1_0_1270), .B1( + n_1_0_1266), .B2(registers_31__ap[28]), .ZN(n_1_0_1187)); + SDFF_X1_LVT \registers_reg[27][28] (.D(registers[28]), .SE(dftIn), .SI( + registers_24__ap[28]), .CK(n_0_57__0), .Q(registers_27__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[7][28] (.D(registers[28]), .SE(dftIn), .SI( + registers_31__ap[28]), .CK(n_0_37), .Q(registers_7__ap[28]), .QN()); + AOI22_X1_LVT i_1_0_1247 (.A1(registers_27__ap[28]), .A2(n_1_0_1279), .B1( + n_1_0_1263), .B2(registers_7__ap[28]), .ZN(n_1_0_1186)); + NAND3_X1_LVT i_1_0_1246 (.A1(n_1_0_1188), .A2(n_1_0_1187), .A3(n_1_0_1186), + .ZN(n_1_0_1185)); + SDFF_X1_LVT \registers_reg[19][28] (.D(registers[28]), .SE(dftIn), .SI( + registers_21__ap[28]), .CK(n_0_49), .Q(registers_19__ap[28]), .QN()); + SDFF_X1_LVT \registers_reg[18][28] (.D(registers[28]), .SE(dftIn), .SI( + registers_19__ap[28]), .CK(n_0_48), .Q(registers_18__ap[28]), .QN()); + AOI221_X1_LVT i_1_0_1245 (.A(n_1_0_1185), .B1(n_1_0_1295), .B2( + registers_19__ap[28]), .C1(registers_18__ap[28]), .C2(n_1_0_1297), + .ZN(n_1_0_1184)); + NAND3_X1_LVT i_1_0_1244 (.A1(n_1_0_1194), .A2(n_1_0_1189), .A3(n_1_0_1184), + .ZN(RRs1[28])); + AND2_X1_LVT i_0_0_27 (.A1(n_0_0_16), .A2(WRd[27]), .ZN(registers[27])); + SDFF_X1_LVT \registers_reg[29][27] (.D(registers[27]), .SE(dftIn), .SI( + registers_27__ap[28]), .CK(n_0_1), .Q(registers_29__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[2][27] (.D(registers[27]), .SE(dftIn), .SI( + registers_29__ap[27]), .CK(n_0_32), .Q(registers_2__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1242 (.A1(registers_29__ap[27]), .A2(n_1_0_1276), .B1( + n_1_0_1268), .B2(registers_2__ap[27]), .ZN(n_1_0_1182)); + SDFF_X1_LVT \registers_reg[8][27] (.D(registers[27]), .SE(dftIn), .SI( + registers_7__ap[28]), .CK(n_0_38), .Q(registers_8__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[25][27] (.D(registers[27]), .SE(dftIn), .SI( + registers_2__ap[27]), .CK(n_0_55), .Q(registers_25__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1243 (.A1(registers_8__ap[27]), .A2(n_1_0_1282), .B1( + n_1_0_1269), .B2(registers_25__ap[27]), .ZN(n_1_0_1183)); + SDFF_X1_LVT \registers_reg[9][27] (.D(registers[27]), .SE(dftIn), .SI( + registers_8__ap[27]), .CK(n_0_39), .Q(registers_9__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[7][27] (.D(registers[27]), .SE(dftIn), .SI( + registers_9__ap[27]), .CK(n_0_37), .Q(registers_7__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1241 (.A1(registers_9__ap[27]), .A2(n_1_0_1291), .B1( + n_1_0_1263), .B2(registers_7__ap[27]), .ZN(n_1_0_1181)); + SDFF_X1_LVT \registers_reg[11][27] (.D(registers[27]), .SE(dftIn), .SI( + registers_11__ap[28]), .CK(n_0_41__0), .Q(registers_11__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[16][27] (.D(registers[27]), .SE(dftIn), .SI( + registers_11__ap[27]), .CK(n_0_46), .Q(registers_16__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1240 (.A1(registers_11__ap[27]), .A2(n_1_0_1270), .B1( + n_1_0_1267), .B2(registers_16__ap[27]), .ZN(n_1_0_1180)); + NAND3_X1_LVT i_1_0_1239 (.A1(n_1_0_1183), .A2(n_1_0_1181), .A3(n_1_0_1180), + .ZN(n_1_0_1179)); + SDFF_X1_LVT \registers_reg[10][27] (.D(registers[27]), .SE(dftIn), .SI( + registers_16__ap[27]), .CK(n_0_40), .Q(registers_10__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[6][27] (.D(registers[27]), .SE(dftIn), .SI( + registers_7__ap[27]), .CK(n_0_36__0), .Q(registers_6__ap[27]), .QN()); + AOI221_X1_LVT i_1_0_1238 (.A(n_1_0_1179), .B1(n_1_0_1287), .B2( + registers_10__ap[27]), .C1(registers_6__ap[27]), .C2(n_1_0_1300), .ZN( + n_1_0_1178)); + SDFF_X1_LVT \registers_reg[1][27] (.D(registers[27]), .SE(dftIn), .SI( + registers_18__ap[28]), .CK(n_0_0__0), .Q(registers_1__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[30][27] (.D(registers[27]), .SE(dftIn), .SI( + registers_25__ap[27]), .CK(n_0_2), .Q(registers_30__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[22][27] (.D(registers[27]), .SE(dftIn), .SI( + registers_1__ap[27]), .CK(n_0_52), .Q(registers_22__ap[27]), .QN()); + AOI222_X1_LVT i_1_0_1237 (.A1(registers_1__ap[27]), .A2(n_1_0_1274), .B1( + n_1_0_1272), .B2(registers_30__ap[27]), .C1(registers_22__ap[27]), + .C2(n_1_0_1294), .ZN(n_1_0_1177)); + NAND3_X1_LVT i_1_0_1236 (.A1(n_1_0_1182), .A2(n_1_0_1178), .A3(n_1_0_1177), + .ZN(n_1_0_1176)); + SDFF_X1_LVT \registers_reg[5][27] (.D(registers[27]), .SE(dftIn), .SI( + registers_6__ap[27]), .CK(n_0_35), .Q(registers_5__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[28][27] (.D(registers[27]), .SE(dftIn), .SI( + registers_30__ap[27]), .CK(n_0_0__1), .Q(registers_28__ap[27]), .QN()); + AOI221_X1_LVT i_1_0_1235 (.A(n_1_0_1176), .B1(n_1_0_1273), .B2( + registers_5__ap[27]), .C1(registers_28__ap[27]), .C2(n_1_0_1283), .ZN( + n_1_0_1175)); + SDFF_X1_LVT \registers_reg[4][27] (.D(registers[27]), .SE(dftIn), .SI( + registers_5__ap[27]), .CK(n_0_34), .Q(registers_4__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[12][27] (.D(registers[27]), .SE(dftIn), .SI( + registers_10__ap[27]), .CK(n_0_42), .Q(registers_12__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1234 (.A1(registers_4__ap[27]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[27]), .ZN(n_1_0_1174)); + SDFF_X1_LVT \registers_reg[19][27] (.D(registers[27]), .SE(dftIn), .SI( + registers_22__ap[27]), .CK(n_0_49), .Q(registers_19__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[21][27] (.D(registers[27]), .SE(dftIn), .SI( + registers_19__ap[27]), .CK(n_0_51), .Q(registers_21__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1233 (.A1(registers_19__ap[27]), .A2(n_1_0_1295), .B1( + n_1_0_1259), .B2(registers_21__ap[27]), .ZN(n_1_0_1173)); + SDFF_X1_LVT \registers_reg[24][27] (.D(registers[27]), .SE(dftIn), .SI( + registers_28__ap[27]), .CK(n_0_54), .Q(registers_24__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[20][27] (.D(registers[27]), .SE(dftIn), .SI( + registers_21__ap[27]), .CK(n_0_50), .Q(registers_20__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1232 (.A1(registers_24__ap[27]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[27]), .ZN(n_1_0_1172)); + NAND3_X1_LVT i_1_0_1231 (.A1(n_1_0_1174), .A2(n_1_0_1173), .A3(n_1_0_1172), + .ZN(n_1_0_1171)); + SDFF_X1_LVT \registers_reg[18][27] (.D(registers[27]), .SE(dftIn), .SI( + registers_20__ap[27]), .CK(n_0_48), .Q(registers_18__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[26][27] (.D(registers[27]), .SE(dftIn), .SI( + registers_24__ap[27]), .CK(n_0_56), .Q(registers_26__ap[27]), .QN()); + AOI221_X1_LVT i_1_0_1230 (.A(n_1_0_1171), .B1(n_1_0_1297), .B2( + registers_18__ap[27]), .C1(registers_26__ap[27]), .C2(n_1_0_1285), + .ZN(n_1_0_1170)); + SDFF_X1_LVT \registers_reg[23][27] (.D(registers[27]), .SE(dftIn), .SI( + registers_18__ap[27]), .CK(n_0_53), .Q(registers_23__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[3][27] (.D(registers[27]), .SE(dftIn), .SI( + registers_4__ap[27]), .CK(n_0_33), .Q(registers_3__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1229 (.A1(registers_23__ap[27]), .A2(n_1_0_1264), .B1( + n_1_0_1257), .B2(registers_3__ap[27]), .ZN(n_1_0_1169)); + SDFF_X1_LVT \registers_reg[13][27] (.D(registers[27]), .SE(dftIn), .SI( + registers_12__ap[27]), .CK(n_0_43), .Q(registers_13__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[17][27] (.D(registers[27]), .SE(dftIn), .SI( + registers_23__ap[27]), .CK(n_0_47), .Q(registers_17__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1228 (.A1(registers_13__ap[27]), .A2(n_1_0_1277), .B1( + n_1_0_1271), .B2(registers_17__ap[27]), .ZN(n_1_0_1168)); + SDFF_X1_LVT \registers_reg[15][27] (.D(registers[27]), .SE(dftIn), .SI( + registers_13__ap[27]), .CK(n_0_45), .Q(registers_15__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[14][27] (.D(registers[27]), .SE(dftIn), .SI( + registers_15__ap[27]), .CK(n_0_44), .Q(registers_14__ap[27]), .QN()); + AOI22_X1_LVT i_1_0_1227 (.A1(registers_15__ap[27]), .A2(n_1_0_1286), .B1( + n_1_0_1258), .B2(registers_14__ap[27]), .ZN(n_1_0_1167)); + NAND3_X1_LVT i_1_0_1226 (.A1(n_1_0_1169), .A2(n_1_0_1168), .A3(n_1_0_1167), + .ZN(n_1_0_1166)); + SDFF_X1_LVT \registers_reg[27][27] (.D(registers[27]), .SE(dftIn), .SI( + registers_26__ap[27]), .CK(n_0_57__0), .Q(registers_27__ap[27]), .QN()); + SDFF_X1_LVT \registers_reg[31][27] (.D(registers[27]), .SE(dftIn), .SI( + registers_3__ap[27]), .CK(n_0_3), .Q(registers_31__ap[27]), .QN()); + AOI221_X1_LVT i_1_0_1225 (.A(n_1_0_1166), .B1(n_1_0_1279), .B2( + registers_27__ap[27]), .C1(registers_31__ap[27]), .C2(n_1_0_1266), + .ZN(n_1_0_1165)); + NAND3_X1_LVT i_1_0_1224 (.A1(n_1_0_1175), .A2(n_1_0_1170), .A3(n_1_0_1165), + .ZN(RRs1[27])); + AND2_X1_LVT i_0_0_26 (.A1(n_0_0_16), .A2(WRd[26]), .ZN(registers[26])); + SDFF_X1_LVT \registers_reg[18][26] (.D(registers[26]), .SE(dftIn), .SI( + registers_17__ap[27]), .CK(n_0_48), .Q(registers_18__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[22][26] (.D(registers[26]), .SE(dftIn), .SI( + registers_18__ap[26]), .CK(n_0_52), .Q(registers_22__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[1][26] (.D(registers[26]), .SE(dftIn), .SI( + registers_22__ap[26]), .CK(n_0_0__0), .Q(registers_1__ap[26]), .QN()); + AOI222_X1_LVT i_1_0_1223 (.A1(registers_18__ap[26]), .A2(n_1_0_1297), + .B1(n_1_0_1294), .B2(registers_22__ap[26]), .C1(registers_1__ap[26]), + .C2(n_1_0_1274), .ZN(n_1_0_1164)); + SDFF_X1_LVT \registers_reg[29][26] (.D(registers[26]), .SE(dftIn), .SI( + registers_27__ap[27]), .CK(n_0_1), .Q(registers_29__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[2][26] (.D(registers[26]), .SE(dftIn), .SI( + registers_29__ap[26]), .CK(n_0_32), .Q(registers_2__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1222 (.A1(registers_29__ap[26]), .A2(n_1_0_1276), .B1( + n_1_0_1268), .B2(registers_2__ap[26]), .ZN(n_1_0_1163)); + SDFF_X1_LVT \registers_reg[9][26] (.D(registers[26]), .SE(dftIn), .SI( + registers_31__ap[27]), .CK(n_0_39), .Q(registers_9__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[7][26] (.D(registers[26]), .SE(dftIn), .SI( + registers_9__ap[26]), .CK(n_0_37), .Q(registers_7__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1221 (.A1(registers_9__ap[26]), .A2(n_1_0_1291), .B1( + n_1_0_1263), .B2(registers_7__ap[26]), .ZN(n_1_0_1162)); + SDFF_X1_LVT \registers_reg[11][26] (.D(registers[26]), .SE(dftIn), .SI( + registers_14__ap[27]), .CK(n_0_41__0), .Q(registers_11__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[25][26] (.D(registers[26]), .SE(dftIn), .SI( + registers_2__ap[26]), .CK(n_0_55), .Q(registers_25__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1220 (.A1(registers_11__ap[26]), .A2(n_1_0_1270), .B1( + n_1_0_1269), .B2(registers_25__ap[26]), .ZN(n_1_0_1161)); + SDFF_X1_LVT \registers_reg[27][26] (.D(registers[26]), .SE(dftIn), .SI( + registers_25__ap[26]), .CK(n_0_57__0), .Q(registers_27__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[16][26] (.D(registers[26]), .SE(dftIn), .SI( + registers_11__ap[26]), .CK(n_0_46), .Q(registers_16__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1219 (.A1(registers_27__ap[26]), .A2(n_1_0_1279), .B1( + n_1_0_1267), .B2(registers_16__ap[26]), .ZN(n_1_0_1160)); + NAND3_X1_LVT i_1_0_1218 (.A1(n_1_0_1162), .A2(n_1_0_1161), .A3(n_1_0_1160), + .ZN(n_1_0_1159)); + SDFF_X1_LVT \registers_reg[31][26] (.D(registers[26]), .SE(dftIn), .SI( + registers_7__ap[26]), .CK(n_0_3), .Q(registers_31__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[6][26] (.D(registers[26]), .SE(dftIn), .SI( + registers_31__ap[26]), .CK(n_0_36__0), .Q(registers_6__ap[26]), .QN()); + AOI221_X1_LVT i_1_0_1217 (.A(n_1_0_1159), .B1(n_1_0_1266), .B2( + registers_31__ap[26]), .C1(registers_6__ap[26]), .C2(n_1_0_1300), .ZN( + n_1_0_1158)); + NAND3_X1_LVT i_1_0_1216 (.A1(n_1_0_1164), .A2(n_1_0_1163), .A3(n_1_0_1158), + .ZN(n_1_0_1157)); + SDFF_X1_LVT \registers_reg[5][26] (.D(registers[26]), .SE(dftIn), .SI( + registers_6__ap[26]), .CK(n_0_35), .Q(registers_5__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[28][26] (.D(registers[26]), .SE(dftIn), .SI( + registers_27__ap[26]), .CK(n_0_0__1), .Q(registers_28__ap[26]), .QN()); + AOI221_X1_LVT i_1_0_1215 (.A(n_1_0_1157), .B1(n_1_0_1273), .B2( + registers_5__ap[26]), .C1(registers_28__ap[26]), .C2(n_1_0_1283), .ZN( + n_1_0_1156)); + SDFF_X1_LVT \registers_reg[4][26] (.D(registers[26]), .SE(dftIn), .SI( + registers_5__ap[26]), .CK(n_0_34), .Q(registers_4__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[12][26] (.D(registers[26]), .SE(dftIn), .SI( + registers_16__ap[26]), .CK(n_0_42), .Q(registers_12__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1214 (.A1(registers_4__ap[26]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[26]), .ZN(n_1_0_1155)); + SDFF_X1_LVT \registers_reg[19][26] (.D(registers[26]), .SE(dftIn), .SI( + registers_1__ap[26]), .CK(n_0_49), .Q(registers_19__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[21][26] (.D(registers[26]), .SE(dftIn), .SI( + registers_19__ap[26]), .CK(n_0_51), .Q(registers_21__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1213 (.A1(registers_19__ap[26]), .A2(n_1_0_1295), .B1( + n_1_0_1259), .B2(registers_21__ap[26]), .ZN(n_1_0_1154)); + SDFF_X1_LVT \registers_reg[24][26] (.D(registers[26]), .SE(dftIn), .SI( + registers_28__ap[26]), .CK(n_0_54), .Q(registers_24__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[20][26] (.D(registers[26]), .SE(dftIn), .SI( + registers_21__ap[26]), .CK(n_0_50), .Q(registers_20__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1212 (.A1(registers_24__ap[26]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[26]), .ZN(n_1_0_1153)); + NAND3_X1_LVT i_1_0_1211 (.A1(n_1_0_1155), .A2(n_1_0_1154), .A3(n_1_0_1153), + .ZN(n_1_0_1152)); + SDFF_X1_LVT \registers_reg[26][26] (.D(registers[26]), .SE(dftIn), .SI( + registers_24__ap[26]), .CK(n_0_56), .Q(registers_26__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[30][26] (.D(registers[26]), .SE(dftIn), .SI( + registers_26__ap[26]), .CK(n_0_2), .Q(registers_30__ap[26]), .QN()); + AOI221_X1_LVT i_1_0_1210 (.A(n_1_0_1152), .B1(n_1_0_1285), .B2( + registers_26__ap[26]), .C1(registers_30__ap[26]), .C2(n_1_0_1272), + .ZN(n_1_0_1151)); + SDFF_X1_LVT \registers_reg[8][26] (.D(registers[26]), .SE(dftIn), .SI( + registers_4__ap[26]), .CK(n_0_38), .Q(registers_8__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[23][26] (.D(registers[26]), .SE(dftIn), .SI( + registers_20__ap[26]), .CK(n_0_53), .Q(registers_23__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1209 (.A1(registers_8__ap[26]), .A2(n_1_0_1282), .B1( + n_1_0_1264), .B2(registers_23__ap[26]), .ZN(n_1_0_1150)); + SDFF_X1_LVT \registers_reg[13][26] (.D(registers[26]), .SE(dftIn), .SI( + registers_12__ap[26]), .CK(n_0_43), .Q(registers_13__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[17][26] (.D(registers[26]), .SE(dftIn), .SI( + registers_23__ap[26]), .CK(n_0_47), .Q(registers_17__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1208 (.A1(registers_13__ap[26]), .A2(n_1_0_1277), .B1( + n_1_0_1271), .B2(registers_17__ap[26]), .ZN(n_1_0_1149)); + SDFF_X1_LVT \registers_reg[15][26] (.D(registers[26]), .SE(dftIn), .SI( + registers_13__ap[26]), .CK(n_0_45), .Q(registers_15__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[14][26] (.D(registers[26]), .SE(dftIn), .SI( + registers_15__ap[26]), .CK(n_0_44), .Q(registers_14__ap[26]), .QN()); + AOI22_X1_LVT i_1_0_1207 (.A1(registers_15__ap[26]), .A2(n_1_0_1286), .B1( + n_1_0_1258), .B2(registers_14__ap[26]), .ZN(n_1_0_1148)); + NAND3_X1_LVT i_1_0_1206 (.A1(n_1_0_1150), .A2(n_1_0_1149), .A3(n_1_0_1148), + .ZN(n_1_0_1147)); + SDFF_X1_LVT \registers_reg[10][26] (.D(registers[26]), .SE(dftIn), .SI( + registers_14__ap[26]), .CK(n_0_40), .Q(registers_10__ap[26]), .QN()); + SDFF_X1_LVT \registers_reg[3][26] (.D(registers[26]), .SE(dftIn), .SI( + registers_8__ap[26]), .CK(n_0_33), .Q(registers_3__ap[26]), .QN()); + AOI221_X1_LVT i_1_0_1205 (.A(n_1_0_1147), .B1(n_1_0_1287), .B2( + registers_10__ap[26]), .C1(registers_3__ap[26]), .C2(n_1_0_1257), .ZN( + n_1_0_1146)); + NAND3_X1_LVT i_1_0_1204 (.A1(n_1_0_1156), .A2(n_1_0_1151), .A3(n_1_0_1146), + .ZN(RRs1[26])); + AND2_X1_LVT i_0_0_25 (.A1(n_0_0_16), .A2(WRd[25]), .ZN(registers[25])); + SDFF_X1_LVT \registers_reg[17][25] (.D(registers[25]), .SE(dftIn), .SI( + registers_17__ap[26]), .CK(n_0_47), .Q(registers_17__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[21][25] (.D(registers[25]), .SE(dftIn), .SI( + registers_17__ap[25]), .CK(n_0_51), .Q(registers_21__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1202 (.A1(registers_17__ap[25]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[25]), .ZN(n_1_0_1144)); + SDFF_X1_LVT \registers_reg[6][25] (.D(registers[25]), .SE(dftIn), .SI( + registers_3__ap[26]), .CK(n_0_36__0), .Q(registers_6__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[8][25] (.D(registers[25]), .SE(dftIn), .SI( + registers_6__ap[25]), .CK(n_0_38), .Q(registers_8__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1203 (.A1(registers_6__ap[25]), .A2(n_1_0_1300), .B1( + n_1_0_1282), .B2(registers_8__ap[25]), .ZN(n_1_0_1145)); + SDFF_X1_LVT \registers_reg[20][25] (.D(registers[25]), .SE(dftIn), .SI( + registers_21__ap[25]), .CK(n_0_50), .Q(registers_20__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[12][25] (.D(registers[25]), .SE(dftIn), .SI( + registers_10__ap[26]), .CK(n_0_42), .Q(registers_12__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1201 (.A1(registers_20__ap[25]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[25]), .ZN(n_1_0_1143)); + SDFF_X1_LVT \registers_reg[5][25] (.D(registers[25]), .SE(dftIn), .SI( + registers_8__ap[25]), .CK(n_0_35), .Q(registers_5__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[11][25] (.D(registers[25]), .SE(dftIn), .SI( + registers_12__ap[25]), .CK(n_0_41__0), .Q(registers_11__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1200 (.A1(registers_5__ap[25]), .A2(n_1_0_1273), .B1( + n_1_0_1270), .B2(registers_11__ap[25]), .ZN(n_1_0_1142)); + NAND3_X1_LVT i_1_0_1199 (.A1(n_1_0_1145), .A2(n_1_0_1143), .A3(n_1_0_1142), + .ZN(n_1_0_1141)); + SDFF_X1_LVT \registers_reg[10][25] (.D(registers[25]), .SE(dftIn), .SI( + registers_11__ap[25]), .CK(n_0_40), .Q(registers_10__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[2][25] (.D(registers[25]), .SE(dftIn), .SI( + registers_30__ap[26]), .CK(n_0_32), .Q(registers_2__ap[25]), .QN()); + AOI221_X1_LVT i_1_0_1198 (.A(n_1_0_1141), .B1(n_1_0_1287), .B2( + registers_10__ap[25]), .C1(registers_2__ap[25]), .C2(n_1_0_1268), .ZN( + n_1_0_1140)); + SDFF_X1_LVT \registers_reg[13][25] (.D(registers[25]), .SE(dftIn), .SI( + registers_10__ap[25]), .CK(n_0_43), .Q(registers_13__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[30][25] (.D(registers[25]), .SE(dftIn), .SI( + registers_2__ap[25]), .CK(n_0_2), .Q(registers_30__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[22][25] (.D(registers[25]), .SE(dftIn), .SI( + registers_20__ap[25]), .CK(n_0_52), .Q(registers_22__ap[25]), .QN()); + AOI222_X1_LVT i_1_0_1197 (.A1(registers_13__ap[25]), .A2(n_1_0_1277), + .B1(n_1_0_1272), .B2(registers_30__ap[25]), .C1(registers_22__ap[25]), + .C2(n_1_0_1294), .ZN(n_1_0_1139)); + NAND2_X1_LVT i_1_0_1196 (.A1(n_1_0_1140), .A2(n_1_0_1139), .ZN(n_1_0_1138)); + SDFF_X1_LVT \registers_reg[1][25] (.D(registers[25]), .SE(dftIn), .SI( + registers_22__ap[25]), .CK(n_0_0__0), .Q(registers_1__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[28][25] (.D(registers[25]), .SE(dftIn), .SI( + registers_30__ap[25]), .CK(n_0_0__1), .Q(registers_28__ap[25]), .QN()); + AOI221_X1_LVT i_1_0_1195 (.A(n_1_0_1138), .B1(n_1_0_1274), .B2( + registers_1__ap[25]), .C1(registers_28__ap[25]), .C2(n_1_0_1283), .ZN( + n_1_0_1137)); + SDFF_X1_LVT \registers_reg[18][25] (.D(registers[25]), .SE(dftIn), .SI( + registers_1__ap[25]), .CK(n_0_48), .Q(registers_18__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[26][25] (.D(registers[25]), .SE(dftIn), .SI( + registers_28__ap[25]), .CK(n_0_56), .Q(registers_26__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1194 (.A1(registers_18__ap[25]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[25]), .ZN(n_1_0_1136)); + SDFF_X1_LVT \registers_reg[24][25] (.D(registers[25]), .SE(dftIn), .SI( + registers_26__ap[25]), .CK(n_0_54), .Q(registers_24__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[4][25] (.D(registers[25]), .SE(dftIn), .SI( + registers_5__ap[25]), .CK(n_0_34), .Q(registers_4__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1193 (.A1(registers_24__ap[25]), .A2(n_1_0_1289), .B1( + n_1_0_1278), .B2(registers_4__ap[25]), .ZN(n_1_0_1135)); + SDFF_X1_LVT \registers_reg[15][25] (.D(registers[25]), .SE(dftIn), .SI( + registers_13__ap[25]), .CK(n_0_45), .Q(registers_15__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[16][25] (.D(registers[25]), .SE(dftIn), .SI( + registers_15__ap[25]), .CK(n_0_46), .Q(registers_16__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1192 (.A1(registers_15__ap[25]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[25]), .ZN(n_1_0_1134)); + NAND3_X1_LVT i_1_0_1191 (.A1(n_1_0_1136), .A2(n_1_0_1135), .A3(n_1_0_1134), + .ZN(n_1_0_1133)); + SDFF_X1_LVT \registers_reg[19][25] (.D(registers[25]), .SE(dftIn), .SI( + registers_18__ap[25]), .CK(n_0_49), .Q(registers_19__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[25][25] (.D(registers[25]), .SE(dftIn), .SI( + registers_24__ap[25]), .CK(n_0_55), .Q(registers_25__ap[25]), .QN()); + AOI221_X1_LVT i_1_0_1190 (.A(n_1_0_1133), .B1(n_1_0_1295), .B2( + registers_19__ap[25]), .C1(registers_25__ap[25]), .C2(n_1_0_1269), + .ZN(n_1_0_1132)); + SDFF_X1_LVT \registers_reg[7][25] (.D(registers[25]), .SE(dftIn), .SI( + registers_4__ap[25]), .CK(n_0_37), .Q(registers_7__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[14][25] (.D(registers[25]), .SE(dftIn), .SI( + registers_16__ap[25]), .CK(n_0_44), .Q(registers_14__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1189 (.A1(registers_7__ap[25]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[25]), .ZN(n_1_0_1131)); + SDFF_X1_LVT \registers_reg[9][25] (.D(registers[25]), .SE(dftIn), .SI( + registers_7__ap[25]), .CK(n_0_39), .Q(registers_9__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[29][25] (.D(registers[25]), .SE(dftIn), .SI( + registers_25__ap[25]), .CK(n_0_1), .Q(registers_29__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1188 (.A1(registers_9__ap[25]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[25]), .ZN(n_1_0_1130)); + SDFF_X1_LVT \registers_reg[23][25] (.D(registers[25]), .SE(dftIn), .SI( + registers_19__ap[25]), .CK(n_0_53), .Q(registers_23__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[3][25] (.D(registers[25]), .SE(dftIn), .SI( + registers_9__ap[25]), .CK(n_0_33), .Q(registers_3__ap[25]), .QN()); + AOI22_X1_LVT i_1_0_1187 (.A1(registers_23__ap[25]), .A2(n_1_0_1264), .B1( + n_1_0_1257), .B2(registers_3__ap[25]), .ZN(n_1_0_1129)); + NAND3_X1_LVT i_1_0_1186 (.A1(n_1_0_1131), .A2(n_1_0_1130), .A3(n_1_0_1129), + .ZN(n_1_0_1128)); + SDFF_X1_LVT \registers_reg[27][25] (.D(registers[25]), .SE(dftIn), .SI( + registers_29__ap[25]), .CK(n_0_57__0), .Q(registers_27__ap[25]), .QN()); + SDFF_X1_LVT \registers_reg[31][25] (.D(registers[25]), .SE(dftIn), .SI( + registers_3__ap[25]), .CK(n_0_3), .Q(registers_31__ap[25]), .QN()); + AOI221_X1_LVT i_1_0_1185 (.A(n_1_0_1128), .B1(n_1_0_1279), .B2( + registers_27__ap[25]), .C1(registers_31__ap[25]), .C2(n_1_0_1266), + .ZN(n_1_0_1127)); + NAND4_X1_LVT i_1_0_1184 (.A1(n_1_0_1144), .A2(n_1_0_1137), .A3(n_1_0_1132), + .A4(n_1_0_1127), .ZN(RRs1[25])); + AND2_X1_LVT i_0_0_24 (.A1(n_0_0_16), .A2(WRd[24]), .ZN(registers[24])); + SDFF_X1_LVT \registers_reg[17][24] (.D(registers[24]), .SE(dftIn), .SI( + registers_23__ap[25]), .CK(n_0_47), .Q(registers_17__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[21][24] (.D(registers[24]), .SE(dftIn), .SI( + registers_17__ap[24]), .CK(n_0_51), .Q(registers_21__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1182 (.A1(registers_17__ap[24]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[24]), .ZN(n_1_0_1125)); + SDFF_X1_LVT \registers_reg[6][24] (.D(registers[24]), .SE(dftIn), .SI( + registers_31__ap[25]), .CK(n_0_36__0), .Q(registers_6__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[8][24] (.D(registers[24]), .SE(dftIn), .SI( + registers_6__ap[24]), .CK(n_0_38), .Q(registers_8__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1183 (.A1(registers_6__ap[24]), .A2(n_1_0_1300), .B1( + n_1_0_1282), .B2(registers_8__ap[24]), .ZN(n_1_0_1126)); + SDFF_X1_LVT \registers_reg[20][24] (.D(registers[24]), .SE(dftIn), .SI( + registers_21__ap[24]), .CK(n_0_50), .Q(registers_20__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[12][24] (.D(registers[24]), .SE(dftIn), .SI( + registers_14__ap[25]), .CK(n_0_42), .Q(registers_12__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1181 (.A1(registers_20__ap[24]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[24]), .ZN(n_1_0_1124)); + SDFF_X1_LVT \registers_reg[5][24] (.D(registers[24]), .SE(dftIn), .SI( + registers_8__ap[24]), .CK(n_0_35), .Q(registers_5__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[11][24] (.D(registers[24]), .SE(dftIn), .SI( + registers_12__ap[24]), .CK(n_0_41__0), .Q(registers_11__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1180 (.A1(registers_5__ap[24]), .A2(n_1_0_1273), .B1( + n_1_0_1270), .B2(registers_11__ap[24]), .ZN(n_1_0_1123)); + NAND3_X1_LVT i_1_0_1179 (.A1(n_1_0_1126), .A2(n_1_0_1124), .A3(n_1_0_1123), + .ZN(n_1_0_1122)); + SDFF_X1_LVT \registers_reg[10][24] (.D(registers[24]), .SE(dftIn), .SI( + registers_11__ap[24]), .CK(n_0_40), .Q(registers_10__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[2][24] (.D(registers[24]), .SE(dftIn), .SI( + registers_27__ap[25]), .CK(n_0_32), .Q(registers_2__ap[24]), .QN()); + AOI221_X1_LVT i_1_0_1178 (.A(n_1_0_1122), .B1(n_1_0_1287), .B2( + registers_10__ap[24]), .C1(registers_2__ap[24]), .C2(n_1_0_1268), .ZN( + n_1_0_1121)); + SDFF_X1_LVT \registers_reg[13][24] (.D(registers[24]), .SE(dftIn), .SI( + registers_10__ap[24]), .CK(n_0_43), .Q(registers_13__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[30][24] (.D(registers[24]), .SE(dftIn), .SI( + registers_2__ap[24]), .CK(n_0_2), .Q(registers_30__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[22][24] (.D(registers[24]), .SE(dftIn), .SI( + registers_20__ap[24]), .CK(n_0_52), .Q(registers_22__ap[24]), .QN()); + AOI222_X1_LVT i_1_0_1177 (.A1(registers_13__ap[24]), .A2(n_1_0_1277), + .B1(n_1_0_1272), .B2(registers_30__ap[24]), .C1(registers_22__ap[24]), + .C2(n_1_0_1294), .ZN(n_1_0_1120)); + NAND2_X1_LVT i_1_0_1176 (.A1(n_1_0_1121), .A2(n_1_0_1120), .ZN(n_1_0_1119)); + SDFF_X1_LVT \registers_reg[1][24] (.D(registers[24]), .SE(dftIn), .SI( + registers_22__ap[24]), .CK(n_0_0__0), .Q(registers_1__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[28][24] (.D(registers[24]), .SE(dftIn), .SI( + registers_30__ap[24]), .CK(n_0_0__1), .Q(registers_28__ap[24]), .QN()); + AOI221_X1_LVT i_1_0_1175 (.A(n_1_0_1119), .B1(n_1_0_1274), .B2( + registers_1__ap[24]), .C1(registers_28__ap[24]), .C2(n_1_0_1283), .ZN( + n_1_0_1118)); + SDFF_X1_LVT \registers_reg[18][24] (.D(registers[24]), .SE(dftIn), .SI( + registers_1__ap[24]), .CK(n_0_48), .Q(registers_18__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[26][24] (.D(registers[24]), .SE(dftIn), .SI( + registers_28__ap[24]), .CK(n_0_56), .Q(registers_26__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1174 (.A1(registers_18__ap[24]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[24]), .ZN(n_1_0_1117)); + SDFF_X1_LVT \registers_reg[24][24] (.D(registers[24]), .SE(dftIn), .SI( + registers_26__ap[24]), .CK(n_0_54), .Q(registers_24__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[4][24] (.D(registers[24]), .SE(dftIn), .SI( + registers_5__ap[24]), .CK(n_0_34), .Q(registers_4__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1173 (.A1(registers_24__ap[24]), .A2(n_1_0_1289), .B1( + n_1_0_1278), .B2(registers_4__ap[24]), .ZN(n_1_0_1116)); + SDFF_X1_LVT \registers_reg[15][24] (.D(registers[24]), .SE(dftIn), .SI( + registers_13__ap[24]), .CK(n_0_45), .Q(registers_15__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[25][24] (.D(registers[24]), .SE(dftIn), .SI( + registers_24__ap[24]), .CK(n_0_55), .Q(registers_25__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1172 (.A1(registers_15__ap[24]), .A2(n_1_0_1286), .B1( + n_1_0_1269), .B2(registers_25__ap[24]), .ZN(n_1_0_1115)); + NAND3_X1_LVT i_1_0_1171 (.A1(n_1_0_1117), .A2(n_1_0_1116), .A3(n_1_0_1115), + .ZN(n_1_0_1114)); + SDFF_X1_LVT \registers_reg[19][24] (.D(registers[24]), .SE(dftIn), .SI( + registers_18__ap[24]), .CK(n_0_49), .Q(registers_19__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[16][24] (.D(registers[24]), .SE(dftIn), .SI( + registers_15__ap[24]), .CK(n_0_46), .Q(registers_16__ap[24]), .QN()); + AOI221_X1_LVT i_1_0_1170 (.A(n_1_0_1114), .B1(n_1_0_1295), .B2( + registers_19__ap[24]), .C1(registers_16__ap[24]), .C2(n_1_0_1267), + .ZN(n_1_0_1113)); + SDFF_X1_LVT \registers_reg[7][24] (.D(registers[24]), .SE(dftIn), .SI( + registers_4__ap[24]), .CK(n_0_37), .Q(registers_7__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[14][24] (.D(registers[24]), .SE(dftIn), .SI( + registers_16__ap[24]), .CK(n_0_44), .Q(registers_14__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1169 (.A1(registers_7__ap[24]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[24]), .ZN(n_1_0_1112)); + SDFF_X1_LVT \registers_reg[9][24] (.D(registers[24]), .SE(dftIn), .SI( + registers_7__ap[24]), .CK(n_0_39), .Q(registers_9__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[29][24] (.D(registers[24]), .SE(dftIn), .SI( + registers_25__ap[24]), .CK(n_0_1), .Q(registers_29__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1168 (.A1(registers_9__ap[24]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[24]), .ZN(n_1_0_1111)); + SDFF_X1_LVT \registers_reg[23][24] (.D(registers[24]), .SE(dftIn), .SI( + registers_19__ap[24]), .CK(n_0_53), .Q(registers_23__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[3][24] (.D(registers[24]), .SE(dftIn), .SI( + registers_9__ap[24]), .CK(n_0_33), .Q(registers_3__ap[24]), .QN()); + AOI22_X1_LVT i_1_0_1167 (.A1(registers_23__ap[24]), .A2(n_1_0_1264), .B1( + n_1_0_1257), .B2(registers_3__ap[24]), .ZN(n_1_0_1110)); + NAND3_X1_LVT i_1_0_1166 (.A1(n_1_0_1112), .A2(n_1_0_1111), .A3(n_1_0_1110), + .ZN(n_1_0_1109)); + SDFF_X1_LVT \registers_reg[27][24] (.D(registers[24]), .SE(dftIn), .SI( + registers_29__ap[24]), .CK(n_0_57__0), .Q(registers_27__ap[24]), .QN()); + SDFF_X1_LVT \registers_reg[31][24] (.D(registers[24]), .SE(dftIn), .SI( + registers_3__ap[24]), .CK(n_0_3), .Q(registers_31__ap[24]), .QN()); + AOI221_X1_LVT i_1_0_1165 (.A(n_1_0_1109), .B1(n_1_0_1279), .B2( + registers_27__ap[24]), .C1(registers_31__ap[24]), .C2(n_1_0_1266), + .ZN(n_1_0_1108)); + NAND4_X1_LVT i_1_0_1164 (.A1(n_1_0_1125), .A2(n_1_0_1118), .A3(n_1_0_1113), + .A4(n_1_0_1108), .ZN(RRs1[24])); + AND2_X1_LVT i_0_0_23 (.A1(n_0_0_16), .A2(WRd[23]), .ZN(registers[23])); + SDFF_X1_LVT \registers_reg[9][23] (.D(registers[23]), .SE(dftIn), .SI( + registers_31__ap[24]), .CK(n_0_39), .Q(registers_9__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[28][23] (.D(registers[23]), .SE(dftIn), .SI( + registers_27__ap[24]), .CK(n_0_0__1), .Q(registers_28__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1163 (.A1(registers_9__ap[23]), .A2(n_1_0_1291), .B1( + n_1_0_1283), .B2(registers_28__ap[23]), .ZN(n_1_0_1107)); + SDFF_X1_LVT \registers_reg[18][23] (.D(registers[23]), .SE(dftIn), .SI( + registers_23__ap[24]), .CK(n_0_48), .Q(registers_18__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[22][23] (.D(registers[23]), .SE(dftIn), .SI( + registers_18__ap[23]), .CK(n_0_52), .Q(registers_22__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1160 (.A1(registers_18__ap[23]), .A2(n_1_0_1297), .B1( + n_1_0_1294), .B2(registers_22__ap[23]), .ZN(n_1_0_1104)); + SDFF_X1_LVT \registers_reg[1][23] (.D(registers[23]), .SE(dftIn), .SI( + registers_22__ap[23]), .CK(n_0_0__0), .Q(registers_1__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[21][23] (.D(registers[23]), .SE(dftIn), .SI( + registers_1__ap[23]), .CK(n_0_51), .Q(registers_21__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1159 (.A1(registers_1__ap[23]), .A2(n_1_0_1274), .B1( + n_1_0_1259), .B2(registers_21__ap[23]), .ZN(n_1_0_1103)); + NAND3_X1_LVT i_1_0_1157 (.A1(n_1_0_1107), .A2(n_1_0_1104), .A3(n_1_0_1103), + .ZN(n_1_0_1101)); + SDFF_X1_LVT \registers_reg[20][23] (.D(registers[23]), .SE(dftIn), .SI( + registers_21__ap[23]), .CK(n_0_50), .Q(registers_20__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[19][23] (.D(registers[23]), .SE(dftIn), .SI( + registers_20__ap[23]), .CK(n_0_49), .Q(registers_19__ap[23]), .QN()); + AOI221_X1_LVT i_1_0_1156 (.A(n_1_0_1101), .B1(n_1_0_1281), .B2( + registers_20__ap[23]), .C1(registers_19__ap[23]), .C2(n_1_0_1295), + .ZN(n_1_0_1100)); + SDFF_X1_LVT \registers_reg[26][23] (.D(registers[23]), .SE(dftIn), .SI( + registers_28__ap[23]), .CK(n_0_56), .Q(registers_26__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[23][23] (.D(registers[23]), .SE(dftIn), .SI( + registers_19__ap[23]), .CK(n_0_53), .Q(registers_23__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1162 (.A1(registers_26__ap[23]), .A2(n_1_0_1285), .B1( + n_1_0_1264), .B2(registers_23__ap[23]), .ZN(n_1_0_1106)); + SDFF_X1_LVT \registers_reg[29][23] (.D(registers[23]), .SE(dftIn), .SI( + registers_26__ap[23]), .CK(n_0_1), .Q(registers_29__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[3][23] (.D(registers[23]), .SE(dftIn), .SI( + registers_9__ap[23]), .CK(n_0_33), .Q(registers_3__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1161 (.A1(registers_29__ap[23]), .A2(n_1_0_1276), .B1( + n_1_0_1257), .B2(registers_3__ap[23]), .ZN(n_1_0_1105)); + SDFF_X1_LVT \registers_reg[30][23] (.D(registers[23]), .SE(dftIn), .SI( + registers_29__ap[23]), .CK(n_0_2), .Q(registers_30__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[31][23] (.D(registers[23]), .SE(dftIn), .SI( + registers_3__ap[23]), .CK(n_0_3), .Q(registers_31__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1158 (.A1(registers_30__ap[23]), .A2(n_1_0_1272), .B1( + n_1_0_1266), .B2(registers_31__ap[23]), .ZN(n_1_0_1102)); + NAND3_X1_LVT i_1_0_1155 (.A1(n_1_0_1106), .A2(n_1_0_1105), .A3(n_1_0_1102), + .ZN(n_1_0_1099)); + SDFF_X1_LVT \registers_reg[8][23] (.D(registers[23]), .SE(dftIn), .SI( + registers_31__ap[23]), .CK(n_0_38), .Q(registers_8__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[17][23] (.D(registers[23]), .SE(dftIn), .SI( + registers_23__ap[23]), .CK(n_0_47), .Q(registers_17__ap[23]), .QN()); + AOI221_X1_LVT i_1_0_1154 (.A(n_1_0_1099), .B1(n_1_0_1282), .B2( + registers_8__ap[23]), .C1(registers_17__ap[23]), .C2(n_1_0_1271), .ZN( + n_1_0_1098)); + SDFF_X1_LVT \registers_reg[24][23] (.D(registers[23]), .SE(dftIn), .SI( + registers_30__ap[23]), .CK(n_0_54), .Q(registers_24__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[15][23] (.D(registers[23]), .SE(dftIn), .SI( + registers_14__ap[24]), .CK(n_0_45), .Q(registers_15__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[14][23] (.D(registers[23]), .SE(dftIn), .SI( + registers_15__ap[23]), .CK(n_0_44), .Q(registers_14__ap[23]), .QN()); + AOI222_X1_LVT i_1_0_1153 (.A1(registers_24__ap[23]), .A2(n_1_0_1289), + .B1(n_1_0_1286), .B2(registers_15__ap[23]), .C1(n_1_0_1258), .C2( + registers_14__ap[23]), .ZN(n_1_0_1097)); + SDFF_X1_LVT \registers_reg[16][23] (.D(registers[23]), .SE(dftIn), .SI( + registers_14__ap[23]), .CK(n_0_46), .Q(registers_16__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[7][23] (.D(registers[23]), .SE(dftIn), .SI( + registers_8__ap[23]), .CK(n_0_37), .Q(registers_7__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1152 (.A1(registers_16__ap[23]), .A2(n_1_0_1267), .B1( + n_1_0_1263), .B2(registers_7__ap[23]), .ZN(n_1_0_1096)); + SDFF_X1_LVT \registers_reg[6][23] (.D(registers[23]), .SE(dftIn), .SI( + registers_7__ap[23]), .CK(n_0_36__0), .Q(registers_6__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[25][23] (.D(registers[23]), .SE(dftIn), .SI( + registers_24__ap[23]), .CK(n_0_55), .Q(registers_25__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1151 (.A1(registers_6__ap[23]), .A2(n_1_0_1300), .B1( + n_1_0_1269), .B2(registers_25__ap[23]), .ZN(n_1_0_1095)); + SDFF_X1_LVT \registers_reg[27][23] (.D(registers[23]), .SE(dftIn), .SI( + registers_25__ap[23]), .CK(n_0_57__0), .Q(registers_27__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[11][23] (.D(registers[23]), .SE(dftIn), .SI( + registers_16__ap[23]), .CK(n_0_41__0), .Q(registers_11__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1150 (.A1(registers_27__ap[23]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[23]), .ZN(n_1_0_1094)); + SDFF_X1_LVT \registers_reg[13][23] (.D(registers[23]), .SE(dftIn), .SI( + registers_11__ap[23]), .CK(n_0_43), .Q(registers_13__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[5][23] (.D(registers[23]), .SE(dftIn), .SI( + registers_6__ap[23]), .CK(n_0_35), .Q(registers_5__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1149 (.A1(registers_13__ap[23]), .A2(n_1_0_1277), .B1( + n_1_0_1273), .B2(registers_5__ap[23]), .ZN(n_1_0_1093)); + SDFF_X1_LVT \registers_reg[4][23] (.D(registers[23]), .SE(dftIn), .SI( + registers_5__ap[23]), .CK(n_0_34), .Q(registers_4__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[12][23] (.D(registers[23]), .SE(dftIn), .SI( + registers_13__ap[23]), .CK(n_0_42), .Q(registers_12__ap[23]), .QN()); + AOI22_X1_LVT i_1_0_1148 (.A1(registers_4__ap[23]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[23]), .ZN(n_1_0_1092)); + NAND3_X1_LVT i_1_0_1147 (.A1(n_1_0_1094), .A2(n_1_0_1093), .A3(n_1_0_1092), + .ZN(n_1_0_1091)); + SDFF_X1_LVT \registers_reg[2][23] (.D(registers[23]), .SE(dftIn), .SI( + registers_27__ap[23]), .CK(n_0_32), .Q(registers_2__ap[23]), .QN()); + SDFF_X1_LVT \registers_reg[10][23] (.D(registers[23]), .SE(dftIn), .SI( + registers_12__ap[23]), .CK(n_0_40), .Q(registers_10__ap[23]), .QN()); + AOI221_X1_LVT i_1_0_1146 (.A(n_1_0_1091), .B1(n_1_0_1268), .B2( + registers_2__ap[23]), .C1(registers_10__ap[23]), .C2(n_1_0_1287), .ZN( + n_1_0_1090)); + AND4_X1_LVT i_1_0_1145 (.A1(n_1_0_1097), .A2(n_1_0_1096), .A3(n_1_0_1095), + .A4(n_1_0_1090), .ZN(n_1_0_1089)); + NAND3_X1_LVT i_1_0_1144 (.A1(n_1_0_1100), .A2(n_1_0_1098), .A3(n_1_0_1089), + .ZN(RRs1[23])); + AND2_X1_LVT i_0_0_22 (.A1(n_0_0_16), .A2(WRd[22]), .ZN(registers[22])); + SDFF_X1_LVT \registers_reg[17][22] (.D(registers[22]), .SE(dftIn), .SI( + registers_17__ap[23]), .CK(n_0_47), .Q(registers_17__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[21][22] (.D(registers[22]), .SE(dftIn), .SI( + registers_17__ap[22]), .CK(n_0_51), .Q(registers_21__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1142 (.A1(registers_17__ap[22]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[22]), .ZN(n_1_0_1087)); + SDFF_X1_LVT \registers_reg[6][22] (.D(registers[22]), .SE(dftIn), .SI( + registers_4__ap[23]), .CK(n_0_36__0), .Q(registers_6__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[11][22] (.D(registers[22]), .SE(dftIn), .SI( + registers_10__ap[23]), .CK(n_0_41__0), .Q(registers_11__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1143 (.A1(registers_6__ap[22]), .A2(n_1_0_1300), .B1( + n_1_0_1270), .B2(registers_11__ap[22]), .ZN(n_1_0_1088)); + SDFF_X1_LVT \registers_reg[20][22] (.D(registers[22]), .SE(dftIn), .SI( + registers_21__ap[22]), .CK(n_0_50), .Q(registers_20__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[12][22] (.D(registers[22]), .SE(dftIn), .SI( + registers_11__ap[22]), .CK(n_0_42), .Q(registers_12__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1141 (.A1(registers_20__ap[22]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[22]), .ZN(n_1_0_1086)); + SDFF_X1_LVT \registers_reg[10][22] (.D(registers[22]), .SE(dftIn), .SI( + registers_12__ap[22]), .CK(n_0_40), .Q(registers_10__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[5][22] (.D(registers[22]), .SE(dftIn), .SI( + registers_6__ap[22]), .CK(n_0_35), .Q(registers_5__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1140 (.A1(registers_10__ap[22]), .A2(n_1_0_1287), .B1( + n_1_0_1273), .B2(registers_5__ap[22]), .ZN(n_1_0_1085)); + NAND3_X1_LVT i_1_0_1139 (.A1(n_1_0_1088), .A2(n_1_0_1086), .A3(n_1_0_1085), + .ZN(n_1_0_1084)); + SDFF_X1_LVT \registers_reg[31][22] (.D(registers[22]), .SE(dftIn), .SI( + registers_5__ap[22]), .CK(n_0_3), .Q(registers_31__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[2][22] (.D(registers[22]), .SE(dftIn), .SI( + registers_2__ap[23]), .CK(n_0_32), .Q(registers_2__ap[22]), .QN()); + AOI221_X1_LVT i_1_0_1138 (.A(n_1_0_1084), .B1(n_1_0_1266), .B2( + registers_31__ap[22]), .C1(registers_2__ap[22]), .C2(n_1_0_1268), .ZN( + n_1_0_1083)); + SDFF_X1_LVT \registers_reg[22][22] (.D(registers[22]), .SE(dftIn), .SI( + registers_20__ap[22]), .CK(n_0_52), .Q(registers_22__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[26][22] (.D(registers[22]), .SE(dftIn), .SI( + registers_2__ap[22]), .CK(n_0_56), .Q(registers_26__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[13][22] (.D(registers[22]), .SE(dftIn), .SI( + registers_10__ap[22]), .CK(n_0_43), .Q(registers_13__ap[22]), .QN()); + AOI222_X1_LVT i_1_0_1137 (.A1(registers_22__ap[22]), .A2(n_1_0_1294), + .B1(n_1_0_1285), .B2(registers_26__ap[22]), .C1(n_1_0_1277), .C2( + registers_13__ap[22]), .ZN(n_1_0_1082)); + NAND2_X1_LVT i_1_0_1136 (.A1(n_1_0_1083), .A2(n_1_0_1082), .ZN(n_1_0_1081)); + SDFF_X1_LVT \registers_reg[1][22] (.D(registers[22]), .SE(dftIn), .SI( + registers_22__ap[22]), .CK(n_0_0__0), .Q(registers_1__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[28][22] (.D(registers[22]), .SE(dftIn), .SI( + registers_26__ap[22]), .CK(n_0_0__1), .Q(registers_28__ap[22]), .QN()); + AOI221_X1_LVT i_1_0_1135 (.A(n_1_0_1081), .B1(n_1_0_1274), .B2( + registers_1__ap[22]), .C1(registers_28__ap[22]), .C2(n_1_0_1283), .ZN( + n_1_0_1080)); + SDFF_X1_LVT \registers_reg[18][22] (.D(registers[22]), .SE(dftIn), .SI( + registers_1__ap[22]), .CK(n_0_48), .Q(registers_18__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[30][22] (.D(registers[22]), .SE(dftIn), .SI( + registers_28__ap[22]), .CK(n_0_2), .Q(registers_30__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1134 (.A1(registers_18__ap[22]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[22]), .ZN(n_1_0_1079)); + SDFF_X1_LVT \registers_reg[24][22] (.D(registers[22]), .SE(dftIn), .SI( + registers_30__ap[22]), .CK(n_0_54), .Q(registers_24__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[4][22] (.D(registers[22]), .SE(dftIn), .SI( + registers_31__ap[22]), .CK(n_0_34), .Q(registers_4__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1133 (.A1(registers_24__ap[22]), .A2(n_1_0_1289), .B1( + n_1_0_1278), .B2(registers_4__ap[22]), .ZN(n_1_0_1078)); + SDFF_X1_LVT \registers_reg[15][22] (.D(registers[22]), .SE(dftIn), .SI( + registers_13__ap[22]), .CK(n_0_45), .Q(registers_15__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[16][22] (.D(registers[22]), .SE(dftIn), .SI( + registers_15__ap[22]), .CK(n_0_46), .Q(registers_16__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1132 (.A1(registers_15__ap[22]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[22]), .ZN(n_1_0_1077)); + NAND3_X1_LVT i_1_0_1131 (.A1(n_1_0_1079), .A2(n_1_0_1078), .A3(n_1_0_1077), + .ZN(n_1_0_1076)); + SDFF_X1_LVT \registers_reg[19][22] (.D(registers[22]), .SE(dftIn), .SI( + registers_18__ap[22]), .CK(n_0_49), .Q(registers_19__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[25][22] (.D(registers[22]), .SE(dftIn), .SI( + registers_24__ap[22]), .CK(n_0_55), .Q(registers_25__ap[22]), .QN()); + AOI221_X1_LVT i_1_0_1130 (.A(n_1_0_1076), .B1(n_1_0_1295), .B2( + registers_19__ap[22]), .C1(registers_25__ap[22]), .C2(n_1_0_1269), + .ZN(n_1_0_1075)); + SDFF_X1_LVT \registers_reg[7][22] (.D(registers[22]), .SE(dftIn), .SI( + registers_4__ap[22]), .CK(n_0_37), .Q(registers_7__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[14][22] (.D(registers[22]), .SE(dftIn), .SI( + registers_16__ap[22]), .CK(n_0_44), .Q(registers_14__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1129 (.A1(registers_7__ap[22]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[22]), .ZN(n_1_0_1074)); + SDFF_X1_LVT \registers_reg[9][22] (.D(registers[22]), .SE(dftIn), .SI( + registers_7__ap[22]), .CK(n_0_39), .Q(registers_9__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[29][22] (.D(registers[22]), .SE(dftIn), .SI( + registers_25__ap[22]), .CK(n_0_1), .Q(registers_29__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1128 (.A1(registers_9__ap[22]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[22]), .ZN(n_1_0_1073)); + SDFF_X1_LVT \registers_reg[8][22] (.D(registers[22]), .SE(dftIn), .SI( + registers_9__ap[22]), .CK(n_0_38), .Q(registers_8__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[23][22] (.D(registers[22]), .SE(dftIn), .SI( + registers_19__ap[22]), .CK(n_0_53), .Q(registers_23__ap[22]), .QN()); + AOI22_X1_LVT i_1_0_1127 (.A1(registers_8__ap[22]), .A2(n_1_0_1282), .B1( + n_1_0_1264), .B2(registers_23__ap[22]), .ZN(n_1_0_1072)); + NAND3_X1_LVT i_1_0_1126 (.A1(n_1_0_1074), .A2(n_1_0_1073), .A3(n_1_0_1072), + .ZN(n_1_0_1071)); + SDFF_X1_LVT \registers_reg[27][22] (.D(registers[22]), .SE(dftIn), .SI( + registers_29__ap[22]), .CK(n_0_57__0), .Q(registers_27__ap[22]), .QN()); + SDFF_X1_LVT \registers_reg[3][22] (.D(registers[22]), .SE(dftIn), .SI( + registers_8__ap[22]), .CK(n_0_33), .Q(registers_3__ap[22]), .QN()); + AOI221_X1_LVT i_1_0_1125 (.A(n_1_0_1071), .B1(n_1_0_1279), .B2( + registers_27__ap[22]), .C1(registers_3__ap[22]), .C2(n_1_0_1257), .ZN( + n_1_0_1070)); + NAND4_X1_LVT i_1_0_1124 (.A1(n_1_0_1087), .A2(n_1_0_1080), .A3(n_1_0_1075), + .A4(n_1_0_1070), .ZN(RRs1[22])); + AND2_X1_LVT i_0_0_21 (.A1(n_0_0_16), .A2(WRd[21]), .ZN(registers[21])); + SDFF_X1_LVT \registers_reg[17][21] (.D(registers[21]), .SE(dftIn), .SI( + registers_23__ap[22]), .CK(n_0_47), .Q(registers_17__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[21][21] (.D(registers[21]), .SE(dftIn), .SI( + registers_17__ap[21]), .CK(n_0_51), .Q(registers_21__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1122 (.A1(registers_17__ap[21]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[21]), .ZN(n_1_0_1068)); + SDFF_X1_LVT \registers_reg[6][21] (.D(registers[21]), .SE(dftIn), .SI( + registers_3__ap[22]), .CK(n_0_36__0), .Q(registers_6__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[8][21] (.D(registers[21]), .SE(dftIn), .SI( + registers_6__ap[21]), .CK(n_0_38), .Q(registers_8__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1123 (.A1(registers_6__ap[21]), .A2(n_1_0_1300), .B1( + n_1_0_1282), .B2(registers_8__ap[21]), .ZN(n_1_0_1069)); + SDFF_X1_LVT \registers_reg[20][21] (.D(registers[21]), .SE(dftIn), .SI( + registers_21__ap[21]), .CK(n_0_50), .Q(registers_20__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[12][21] (.D(registers[21]), .SE(dftIn), .SI( + registers_14__ap[22]), .CK(n_0_42), .Q(registers_12__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1121 (.A1(registers_20__ap[21]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[21]), .ZN(n_1_0_1067)); + SDFF_X1_LVT \registers_reg[5][21] (.D(registers[21]), .SE(dftIn), .SI( + registers_8__ap[21]), .CK(n_0_35), .Q(registers_5__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[11][21] (.D(registers[21]), .SE(dftIn), .SI( + registers_12__ap[21]), .CK(n_0_41__0), .Q(registers_11__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1120 (.A1(registers_5__ap[21]), .A2(n_1_0_1273), .B1( + n_1_0_1270), .B2(registers_11__ap[21]), .ZN(n_1_0_1066)); + NAND3_X1_LVT i_1_0_1119 (.A1(n_1_0_1069), .A2(n_1_0_1067), .A3(n_1_0_1066), + .ZN(n_1_0_1065)); + SDFF_X1_LVT \registers_reg[10][21] (.D(registers[21]), .SE(dftIn), .SI( + registers_11__ap[21]), .CK(n_0_40), .Q(registers_10__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[2][21] (.D(registers[21]), .SE(dftIn), .SI( + registers_27__ap[22]), .CK(n_0_32), .Q(registers_2__ap[21]), .QN()); + AOI221_X1_LVT i_1_0_1118 (.A(n_1_0_1065), .B1(n_1_0_1287), .B2( + registers_10__ap[21]), .C1(registers_2__ap[21]), .C2(n_1_0_1268), .ZN( + n_1_0_1064)); + SDFF_X1_LVT \registers_reg[13][21] (.D(registers[21]), .SE(dftIn), .SI( + registers_10__ap[21]), .CK(n_0_43), .Q(registers_13__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[30][21] (.D(registers[21]), .SE(dftIn), .SI( + registers_2__ap[21]), .CK(n_0_2), .Q(registers_30__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[22][21] (.D(registers[21]), .SE(dftIn), .SI( + registers_20__ap[21]), .CK(n_0_52), .Q(registers_22__ap[21]), .QN()); + AOI222_X1_LVT i_1_0_1117 (.A1(registers_13__ap[21]), .A2(n_1_0_1277), + .B1(n_1_0_1272), .B2(registers_30__ap[21]), .C1(registers_22__ap[21]), + .C2(n_1_0_1294), .ZN(n_1_0_1063)); + NAND2_X1_LVT i_1_0_1116 (.A1(n_1_0_1064), .A2(n_1_0_1063), .ZN(n_1_0_1062)); + SDFF_X1_LVT \registers_reg[1][21] (.D(registers[21]), .SE(dftIn), .SI( + registers_22__ap[21]), .CK(n_0_0__0), .Q(registers_1__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[28][21] (.D(registers[21]), .SE(dftIn), .SI( + registers_30__ap[21]), .CK(n_0_0__1), .Q(registers_28__ap[21]), .QN()); + AOI221_X1_LVT i_1_0_1115 (.A(n_1_0_1062), .B1(n_1_0_1274), .B2( + registers_1__ap[21]), .C1(registers_28__ap[21]), .C2(n_1_0_1283), .ZN( + n_1_0_1061)); + SDFF_X1_LVT \registers_reg[18][21] (.D(registers[21]), .SE(dftIn), .SI( + registers_1__ap[21]), .CK(n_0_48), .Q(registers_18__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[26][21] (.D(registers[21]), .SE(dftIn), .SI( + registers_28__ap[21]), .CK(n_0_56), .Q(registers_26__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1114 (.A1(registers_18__ap[21]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[21]), .ZN(n_1_0_1060)); + SDFF_X1_LVT \registers_reg[24][21] (.D(registers[21]), .SE(dftIn), .SI( + registers_26__ap[21]), .CK(n_0_54), .Q(registers_24__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[4][21] (.D(registers[21]), .SE(dftIn), .SI( + registers_5__ap[21]), .CK(n_0_34), .Q(registers_4__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1113 (.A1(registers_24__ap[21]), .A2(n_1_0_1289), .B1( + n_1_0_1278), .B2(registers_4__ap[21]), .ZN(n_1_0_1059)); + SDFF_X1_LVT \registers_reg[15][21] (.D(registers[21]), .SE(dftIn), .SI( + registers_13__ap[21]), .CK(n_0_45), .Q(registers_15__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[16][21] (.D(registers[21]), .SE(dftIn), .SI( + registers_15__ap[21]), .CK(n_0_46), .Q(registers_16__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1112 (.A1(registers_15__ap[21]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[21]), .ZN(n_1_0_1058)); + NAND3_X1_LVT i_1_0_1111 (.A1(n_1_0_1060), .A2(n_1_0_1059), .A3(n_1_0_1058), + .ZN(n_1_0_1057)); + SDFF_X1_LVT \registers_reg[19][21] (.D(registers[21]), .SE(dftIn), .SI( + registers_18__ap[21]), .CK(n_0_49), .Q(registers_19__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[25][21] (.D(registers[21]), .SE(dftIn), .SI( + registers_24__ap[21]), .CK(n_0_55), .Q(registers_25__ap[21]), .QN()); + AOI221_X1_LVT i_1_0_1110 (.A(n_1_0_1057), .B1(n_1_0_1295), .B2( + registers_19__ap[21]), .C1(registers_25__ap[21]), .C2(n_1_0_1269), + .ZN(n_1_0_1056)); + SDFF_X1_LVT \registers_reg[7][21] (.D(registers[21]), .SE(dftIn), .SI( + registers_4__ap[21]), .CK(n_0_37), .Q(registers_7__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[14][21] (.D(registers[21]), .SE(dftIn), .SI( + registers_16__ap[21]), .CK(n_0_44), .Q(registers_14__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1109 (.A1(registers_7__ap[21]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[21]), .ZN(n_1_0_1055)); + SDFF_X1_LVT \registers_reg[9][21] (.D(registers[21]), .SE(dftIn), .SI( + registers_7__ap[21]), .CK(n_0_39), .Q(registers_9__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[29][21] (.D(registers[21]), .SE(dftIn), .SI( + registers_25__ap[21]), .CK(n_0_1), .Q(registers_29__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1108 (.A1(registers_9__ap[21]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[21]), .ZN(n_1_0_1054)); + SDFF_X1_LVT \registers_reg[23][21] (.D(registers[21]), .SE(dftIn), .SI( + registers_19__ap[21]), .CK(n_0_53), .Q(registers_23__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[3][21] (.D(registers[21]), .SE(dftIn), .SI( + registers_9__ap[21]), .CK(n_0_33), .Q(registers_3__ap[21]), .QN()); + AOI22_X1_LVT i_1_0_1107 (.A1(registers_23__ap[21]), .A2(n_1_0_1264), .B1( + n_1_0_1257), .B2(registers_3__ap[21]), .ZN(n_1_0_1053)); + NAND3_X1_LVT i_1_0_1106 (.A1(n_1_0_1055), .A2(n_1_0_1054), .A3(n_1_0_1053), + .ZN(n_1_0_1052)); + SDFF_X1_LVT \registers_reg[27][21] (.D(registers[21]), .SE(dftIn), .SI( + registers_29__ap[21]), .CK(n_0_57__0), .Q(registers_27__ap[21]), .QN()); + SDFF_X1_LVT \registers_reg[31][21] (.D(registers[21]), .SE(dftIn), .SI( + registers_3__ap[21]), .CK(n_0_3), .Q(registers_31__ap[21]), .QN()); + AOI221_X1_LVT i_1_0_1105 (.A(n_1_0_1052), .B1(n_1_0_1279), .B2( + registers_27__ap[21]), .C1(registers_31__ap[21]), .C2(n_1_0_1266), + .ZN(n_1_0_1051)); + NAND4_X1_LVT i_1_0_1104 (.A1(n_1_0_1068), .A2(n_1_0_1061), .A3(n_1_0_1056), + .A4(n_1_0_1051), .ZN(RRs1[21])); + AND2_X1_LVT i_0_0_20 (.A1(n_0_0_16), .A2(WRd[20]), .ZN(registers[20])); + SDFF_X1_LVT \registers_reg[17][20] (.D(registers[20]), .SE(dftIn), .SI( + registers_23__ap[21]), .CK(n_0_47), .Q(registers_17__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[21][20] (.D(registers[20]), .SE(dftIn), .SI( + registers_17__ap[20]), .CK(n_0_51), .Q(registers_21__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1100 (.A1(registers_17__ap[20]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[20]), .ZN(n_1_0_1047)); + SDFF_X1_LVT \registers_reg[10][20] (.D(registers[20]), .SE(dftIn), .SI( + registers_14__ap[21]), .CK(n_0_40), .Q(registers_10__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[2][20] (.D(registers[20]), .SE(dftIn), .SI( + registers_27__ap[21]), .CK(n_0_32), .Q(registers_2__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1103 (.A1(registers_10__ap[20]), .A2(n_1_0_1287), .B1( + n_1_0_1268), .B2(registers_2__ap[20]), .ZN(n_1_0_1050)); + SDFF_X1_LVT \registers_reg[20][20] (.D(registers[20]), .SE(dftIn), .SI( + registers_21__ap[20]), .CK(n_0_50), .Q(registers_20__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[12][20] (.D(registers[20]), .SE(dftIn), .SI( + registers_10__ap[20]), .CK(n_0_42), .Q(registers_12__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1099 (.A1(registers_20__ap[20]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[20]), .ZN(n_1_0_1046)); + SDFF_X1_LVT \registers_reg[15][20] (.D(registers[20]), .SE(dftIn), .SI( + registers_12__ap[20]), .CK(n_0_45), .Q(registers_15__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[8][20] (.D(registers[20]), .SE(dftIn), .SI( + registers_31__ap[21]), .CK(n_0_38), .Q(registers_8__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1102 (.A1(registers_15__ap[20]), .A2(n_1_0_1286), .B1( + n_1_0_1282), .B2(registers_8__ap[20]), .ZN(n_1_0_1049)); + INV_X1_LVT i_1_0_1101 (.A(n_1_0_1049), .ZN(n_1_0_1048)); + SDFF_X1_LVT \registers_reg[11][20] (.D(registers[20]), .SE(dftIn), .SI( + registers_15__ap[20]), .CK(n_0_41__0), .Q(registers_11__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[5][20] (.D(registers[20]), .SE(dftIn), .SI( + registers_8__ap[20]), .CK(n_0_35), .Q(registers_5__ap[20]), .QN()); + AOI221_X1_LVT i_1_0_1098 (.A(n_1_0_1048), .B1(n_1_0_1270), .B2( + registers_11__ap[20]), .C1(registers_5__ap[20]), .C2(n_1_0_1273), .ZN( + n_1_0_1045)); + SDFF_X1_LVT \registers_reg[13][20] (.D(registers[20]), .SE(dftIn), .SI( + registers_11__ap[20]), .CK(n_0_43), .Q(registers_13__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[30][20] (.D(registers[20]), .SE(dftIn), .SI( + registers_2__ap[20]), .CK(n_0_2), .Q(registers_30__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[22][20] (.D(registers[20]), .SE(dftIn), .SI( + registers_20__ap[20]), .CK(n_0_52), .Q(registers_22__ap[20]), .QN()); + AOI222_X1_LVT i_1_0_1097 (.A1(registers_13__ap[20]), .A2(n_1_0_1277), + .B1(n_1_0_1272), .B2(registers_30__ap[20]), .C1(registers_22__ap[20]), + .C2(n_1_0_1294), .ZN(n_1_0_1044)); + NAND4_X1_LVT i_1_0_1096 (.A1(n_1_0_1050), .A2(n_1_0_1046), .A3(n_1_0_1045), + .A4(n_1_0_1044), .ZN(n_1_0_1043)); + SDFF_X1_LVT \registers_reg[1][20] (.D(registers[20]), .SE(dftIn), .SI( + registers_22__ap[20]), .CK(n_0_0__0), .Q(registers_1__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[28][20] (.D(registers[20]), .SE(dftIn), .SI( + registers_30__ap[20]), .CK(n_0_0__1), .Q(registers_28__ap[20]), .QN()); + AOI221_X1_LVT i_1_0_1095 (.A(n_1_0_1043), .B1(n_1_0_1274), .B2( + registers_1__ap[20]), .C1(registers_28__ap[20]), .C2(n_1_0_1283), .ZN( + n_1_0_1042)); + SDFF_X1_LVT \registers_reg[18][20] (.D(registers[20]), .SE(dftIn), .SI( + registers_1__ap[20]), .CK(n_0_48), .Q(registers_18__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[26][20] (.D(registers[20]), .SE(dftIn), .SI( + registers_28__ap[20]), .CK(n_0_56), .Q(registers_26__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1094 (.A1(registers_18__ap[20]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[20]), .ZN(n_1_0_1041)); + SDFF_X1_LVT \registers_reg[24][20] (.D(registers[20]), .SE(dftIn), .SI( + registers_26__ap[20]), .CK(n_0_54), .Q(registers_24__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[4][20] (.D(registers[20]), .SE(dftIn), .SI( + registers_5__ap[20]), .CK(n_0_34), .Q(registers_4__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1093 (.A1(registers_24__ap[20]), .A2(n_1_0_1289), .B1( + n_1_0_1278), .B2(registers_4__ap[20]), .ZN(n_1_0_1040)); + SDFF_X1_LVT \registers_reg[6][20] (.D(registers[20]), .SE(dftIn), .SI( + registers_4__ap[20]), .CK(n_0_36__0), .Q(registers_6__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[25][20] (.D(registers[20]), .SE(dftIn), .SI( + registers_24__ap[20]), .CK(n_0_55), .Q(registers_25__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1092 (.A1(registers_6__ap[20]), .A2(n_1_0_1300), .B1( + n_1_0_1269), .B2(registers_25__ap[20]), .ZN(n_1_0_1039)); + NAND3_X1_LVT i_1_0_1091 (.A1(n_1_0_1041), .A2(n_1_0_1040), .A3(n_1_0_1039), + .ZN(n_1_0_1038)); + SDFF_X1_LVT \registers_reg[19][20] (.D(registers[20]), .SE(dftIn), .SI( + registers_18__ap[20]), .CK(n_0_49), .Q(registers_19__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[16][20] (.D(registers[20]), .SE(dftIn), .SI( + registers_13__ap[20]), .CK(n_0_46), .Q(registers_16__ap[20]), .QN()); + AOI221_X1_LVT i_1_0_1090 (.A(n_1_0_1038), .B1(n_1_0_1295), .B2( + registers_19__ap[20]), .C1(registers_16__ap[20]), .C2(n_1_0_1267), + .ZN(n_1_0_1037)); + SDFF_X1_LVT \registers_reg[7][20] (.D(registers[20]), .SE(dftIn), .SI( + registers_6__ap[20]), .CK(n_0_37), .Q(registers_7__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[14][20] (.D(registers[20]), .SE(dftIn), .SI( + registers_16__ap[20]), .CK(n_0_44), .Q(registers_14__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1089 (.A1(registers_7__ap[20]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[20]), .ZN(n_1_0_1036)); + SDFF_X1_LVT \registers_reg[9][20] (.D(registers[20]), .SE(dftIn), .SI( + registers_7__ap[20]), .CK(n_0_39), .Q(registers_9__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[29][20] (.D(registers[20]), .SE(dftIn), .SI( + registers_25__ap[20]), .CK(n_0_1), .Q(registers_29__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1088 (.A1(registers_9__ap[20]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[20]), .ZN(n_1_0_1035)); + SDFF_X1_LVT \registers_reg[23][20] (.D(registers[20]), .SE(dftIn), .SI( + registers_19__ap[20]), .CK(n_0_53), .Q(registers_23__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[3][20] (.D(registers[20]), .SE(dftIn), .SI( + registers_9__ap[20]), .CK(n_0_33), .Q(registers_3__ap[20]), .QN()); + AOI22_X1_LVT i_1_0_1087 (.A1(registers_23__ap[20]), .A2(n_1_0_1264), .B1( + n_1_0_1257), .B2(registers_3__ap[20]), .ZN(n_1_0_1034)); + NAND3_X1_LVT i_1_0_1086 (.A1(n_1_0_1036), .A2(n_1_0_1035), .A3(n_1_0_1034), + .ZN(n_1_0_1033)); + SDFF_X1_LVT \registers_reg[27][20] (.D(registers[20]), .SE(dftIn), .SI( + registers_29__ap[20]), .CK(n_0_57__0), .Q(registers_27__ap[20]), .QN()); + SDFF_X1_LVT \registers_reg[31][20] (.D(registers[20]), .SE(dftIn), .SI( + registers_3__ap[20]), .CK(n_0_3), .Q(registers_31__ap[20]), .QN()); + AOI221_X1_LVT i_1_0_1085 (.A(n_1_0_1033), .B1(n_1_0_1279), .B2( + registers_27__ap[20]), .C1(registers_31__ap[20]), .C2(n_1_0_1266), + .ZN(n_1_0_1032)); + NAND4_X1_LVT i_1_0_1084 (.A1(n_1_0_1047), .A2(n_1_0_1042), .A3(n_1_0_1037), + .A4(n_1_0_1032), .ZN(RRs1[20])); + AND2_X1_LVT i_0_0_19 (.A1(n_0_0_16), .A2(WRd[19]), .ZN(registers[19])); + SDFF_X1_LVT \registers_reg[17][19] (.D(registers[19]), .SE(dftIn), .SI( + registers_23__ap[20]), .CK(n_0_47), .Q(registers_17__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[21][19] (.D(registers[19]), .SE(dftIn), .SI( + registers_17__ap[19]), .CK(n_0_51), .Q(registers_21__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1080 (.A1(registers_17__ap[19]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[19]), .ZN(n_1_0_1028)); + SDFF_X1_LVT \registers_reg[2][19] (.D(registers[19]), .SE(dftIn), .SI( + registers_27__ap[20]), .CK(n_0_32), .Q(registers_2__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[31][19] (.D(registers[19]), .SE(dftIn), .SI( + registers_31__ap[20]), .CK(n_0_3), .Q(registers_31__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1083 (.A1(registers_2__ap[19]), .A2(n_1_0_1268), .B1( + n_1_0_1266), .B2(registers_31__ap[19]), .ZN(n_1_0_1031)); + SDFF_X1_LVT \registers_reg[20][19] (.D(registers[19]), .SE(dftIn), .SI( + registers_21__ap[19]), .CK(n_0_50), .Q(registers_20__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[12][19] (.D(registers[19]), .SE(dftIn), .SI( + registers_14__ap[20]), .CK(n_0_42), .Q(registers_12__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1079 (.A1(registers_20__ap[19]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[19]), .ZN(n_1_0_1027)); + SDFF_X1_LVT \registers_reg[15][19] (.D(registers[19]), .SE(dftIn), .SI( + registers_12__ap[19]), .CK(n_0_45), .Q(registers_15__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[11][19] (.D(registers[19]), .SE(dftIn), .SI( + registers_15__ap[19]), .CK(n_0_41__0), .Q(registers_11__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1082 (.A1(registers_15__ap[19]), .A2(n_1_0_1286), .B1( + n_1_0_1270), .B2(registers_11__ap[19]), .ZN(n_1_0_1030)); + INV_X1_LVT i_1_0_1081 (.A(n_1_0_1030), .ZN(n_1_0_1029)); + SDFF_X1_LVT \registers_reg[27][19] (.D(registers[19]), .SE(dftIn), .SI( + registers_2__ap[19]), .CK(n_0_57__0), .Q(registers_27__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[24][19] (.D(registers[19]), .SE(dftIn), .SI( + registers_27__ap[19]), .CK(n_0_54), .Q(registers_24__ap[19]), .QN()); + AOI221_X1_LVT i_1_0_1078 (.A(n_1_0_1029), .B1(n_1_0_1279), .B2( + registers_27__ap[19]), .C1(registers_24__ap[19]), .C2(n_1_0_1289), + .ZN(n_1_0_1026)); + SDFF_X1_LVT \registers_reg[22][19] (.D(registers[19]), .SE(dftIn), .SI( + registers_20__ap[19]), .CK(n_0_52), .Q(registers_22__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[26][19] (.D(registers[19]), .SE(dftIn), .SI( + registers_24__ap[19]), .CK(n_0_56), .Q(registers_26__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[13][19] (.D(registers[19]), .SE(dftIn), .SI( + registers_11__ap[19]), .CK(n_0_43), .Q(registers_13__ap[19]), .QN()); + AOI222_X1_LVT i_1_0_1077 (.A1(registers_22__ap[19]), .A2(n_1_0_1294), + .B1(n_1_0_1285), .B2(registers_26__ap[19]), .C1(n_1_0_1277), .C2( + registers_13__ap[19]), .ZN(n_1_0_1025)); + NAND4_X1_LVT i_1_0_1076 (.A1(n_1_0_1031), .A2(n_1_0_1027), .A3(n_1_0_1026), + .A4(n_1_0_1025), .ZN(n_1_0_1024)); + SDFF_X1_LVT \registers_reg[1][19] (.D(registers[19]), .SE(dftIn), .SI( + registers_22__ap[19]), .CK(n_0_0__0), .Q(registers_1__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[28][19] (.D(registers[19]), .SE(dftIn), .SI( + registers_26__ap[19]), .CK(n_0_0__1), .Q(registers_28__ap[19]), .QN()); + AOI221_X1_LVT i_1_0_1075 (.A(n_1_0_1024), .B1(n_1_0_1274), .B2( + registers_1__ap[19]), .C1(registers_28__ap[19]), .C2(n_1_0_1283), .ZN( + n_1_0_1023)); + SDFF_X1_LVT \registers_reg[18][19] (.D(registers[19]), .SE(dftIn), .SI( + registers_1__ap[19]), .CK(n_0_48), .Q(registers_18__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[30][19] (.D(registers[19]), .SE(dftIn), .SI( + registers_28__ap[19]), .CK(n_0_2), .Q(registers_30__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1074 (.A1(registers_18__ap[19]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[19]), .ZN(n_1_0_1022)); + SDFF_X1_LVT \registers_reg[4][19] (.D(registers[19]), .SE(dftIn), .SI( + registers_31__ap[19]), .CK(n_0_34), .Q(registers_4__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[5][19] (.D(registers[19]), .SE(dftIn), .SI( + registers_4__ap[19]), .CK(n_0_35), .Q(registers_5__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1073 (.A1(registers_4__ap[19]), .A2(n_1_0_1278), .B1( + n_1_0_1273), .B2(registers_5__ap[19]), .ZN(n_1_0_1021)); + SDFF_X1_LVT \registers_reg[6][19] (.D(registers[19]), .SE(dftIn), .SI( + registers_5__ap[19]), .CK(n_0_36__0), .Q(registers_6__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[25][19] (.D(registers[19]), .SE(dftIn), .SI( + registers_30__ap[19]), .CK(n_0_55), .Q(registers_25__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1072 (.A1(registers_6__ap[19]), .A2(n_1_0_1300), .B1( + n_1_0_1269), .B2(registers_25__ap[19]), .ZN(n_1_0_1020)); + NAND3_X1_LVT i_1_0_1071 (.A1(n_1_0_1022), .A2(n_1_0_1021), .A3(n_1_0_1020), + .ZN(n_1_0_1019)); + SDFF_X1_LVT \registers_reg[19][19] (.D(registers[19]), .SE(dftIn), .SI( + registers_18__ap[19]), .CK(n_0_49), .Q(registers_19__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[16][19] (.D(registers[19]), .SE(dftIn), .SI( + registers_13__ap[19]), .CK(n_0_46), .Q(registers_16__ap[19]), .QN()); + AOI221_X1_LVT i_1_0_1070 (.A(n_1_0_1019), .B1(n_1_0_1295), .B2( + registers_19__ap[19]), .C1(registers_16__ap[19]), .C2(n_1_0_1267), + .ZN(n_1_0_1018)); + SDFF_X1_LVT \registers_reg[9][19] (.D(registers[19]), .SE(dftIn), .SI( + registers_6__ap[19]), .CK(n_0_39), .Q(registers_9__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[29][19] (.D(registers[19]), .SE(dftIn), .SI( + registers_25__ap[19]), .CK(n_0_1), .Q(registers_29__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1069 (.A1(registers_9__ap[19]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[19]), .ZN(n_1_0_1017)); + SDFF_X1_LVT \registers_reg[8][19] (.D(registers[19]), .SE(dftIn), .SI( + registers_9__ap[19]), .CK(n_0_38), .Q(registers_8__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[23][19] (.D(registers[19]), .SE(dftIn), .SI( + registers_19__ap[19]), .CK(n_0_53), .Q(registers_23__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1068 (.A1(registers_8__ap[19]), .A2(n_1_0_1282), .B1( + n_1_0_1264), .B2(registers_23__ap[19]), .ZN(n_1_0_1016)); + SDFF_X1_LVT \registers_reg[7][19] (.D(registers[19]), .SE(dftIn), .SI( + registers_8__ap[19]), .CK(n_0_37), .Q(registers_7__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[14][19] (.D(registers[19]), .SE(dftIn), .SI( + registers_16__ap[19]), .CK(n_0_44), .Q(registers_14__ap[19]), .QN()); + AOI22_X1_LVT i_1_0_1067 (.A1(registers_7__ap[19]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[19]), .ZN(n_1_0_1015)); + NAND3_X1_LVT i_1_0_1066 (.A1(n_1_0_1017), .A2(n_1_0_1016), .A3(n_1_0_1015), + .ZN(n_1_0_1014)); + SDFF_X1_LVT \registers_reg[10][19] (.D(registers[19]), .SE(dftIn), .SI( + registers_14__ap[19]), .CK(n_0_40), .Q(registers_10__ap[19]), .QN()); + SDFF_X1_LVT \registers_reg[3][19] (.D(registers[19]), .SE(dftIn), .SI( + registers_7__ap[19]), .CK(n_0_33), .Q(registers_3__ap[19]), .QN()); + AOI221_X1_LVT i_1_0_1065 (.A(n_1_0_1014), .B1(n_1_0_1287), .B2( + registers_10__ap[19]), .C1(registers_3__ap[19]), .C2(n_1_0_1257), .ZN( + n_1_0_1013)); + NAND4_X1_LVT i_1_0_1064 (.A1(n_1_0_1028), .A2(n_1_0_1023), .A3(n_1_0_1018), + .A4(n_1_0_1013), .ZN(RRs1[19])); + AND2_X1_LVT i_0_0_18 (.A1(n_0_0_16), .A2(WRd[18]), .ZN(registers[18])); + SDFF_X1_LVT \registers_reg[24][18] (.D(registers[18]), .SE(dftIn), .SI( + registers_29__ap[19]), .CK(n_0_54), .Q(registers_24__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[28][18] (.D(registers[18]), .SE(dftIn), .SI( + registers_24__ap[18]), .CK(n_0_0__1), .Q(registers_28__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1062 (.A1(registers_24__ap[18]), .A2(n_1_0_1289), .B1( + n_1_0_1283), .B2(registers_28__ap[18]), .ZN(n_1_0_1011)); + SDFF_X1_LVT \registers_reg[11][18] (.D(registers[18]), .SE(dftIn), .SI( + registers_10__ap[19]), .CK(n_0_41__0), .Q(registers_11__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[16][18] (.D(registers[18]), .SE(dftIn), .SI( + registers_11__ap[18]), .CK(n_0_46), .Q(registers_16__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1063 (.A1(registers_11__ap[18]), .A2(n_1_0_1270), .B1( + n_1_0_1267), .B2(registers_16__ap[18]), .ZN(n_1_0_1012)); + SDFF_X1_LVT \registers_reg[9][18] (.D(registers[18]), .SE(dftIn), .SI( + registers_3__ap[19]), .CK(n_0_39), .Q(registers_9__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[7][18] (.D(registers[18]), .SE(dftIn), .SI( + registers_9__ap[18]), .CK(n_0_37), .Q(registers_7__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1061 (.A1(registers_9__ap[18]), .A2(n_1_0_1291), .B1( + n_1_0_1263), .B2(registers_7__ap[18]), .ZN(n_1_0_1010)); + SDFF_X1_LVT \registers_reg[27][18] (.D(registers[18]), .SE(dftIn), .SI( + registers_28__ap[18]), .CK(n_0_57__0), .Q(registers_27__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[25][18] (.D(registers[18]), .SE(dftIn), .SI( + registers_27__ap[18]), .CK(n_0_55), .Q(registers_25__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1060 (.A1(registers_27__ap[18]), .A2(n_1_0_1279), .B1( + n_1_0_1269), .B2(registers_25__ap[18]), .ZN(n_1_0_1009)); + NAND3_X1_LVT i_1_0_1059 (.A1(n_1_0_1012), .A2(n_1_0_1010), .A3(n_1_0_1009), + .ZN(n_1_0_1008)); + SDFF_X1_LVT \registers_reg[31][18] (.D(registers[18]), .SE(dftIn), .SI( + registers_7__ap[18]), .CK(n_0_3), .Q(registers_31__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[6][18] (.D(registers[18]), .SE(dftIn), .SI( + registers_31__ap[18]), .CK(n_0_36__0), .Q(registers_6__ap[18]), .QN()); + AOI221_X1_LVT i_1_0_1058 (.A(n_1_0_1008), .B1(n_1_0_1266), .B2( + registers_31__ap[18]), .C1(registers_6__ap[18]), .C2(n_1_0_1300), .ZN( + n_1_0_1007)); + SDFF_X1_LVT \registers_reg[22][18] (.D(registers[18]), .SE(dftIn), .SI( + registers_23__ap[19]), .CK(n_0_52), .Q(registers_22__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[26][18] (.D(registers[18]), .SE(dftIn), .SI( + registers_25__ap[18]), .CK(n_0_56), .Q(registers_26__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[1][18] (.D(registers[18]), .SE(dftIn), .SI( + registers_22__ap[18]), .CK(n_0_0__0), .Q(registers_1__ap[18]), .QN()); + AOI222_X1_LVT i_1_0_1057 (.A1(registers_22__ap[18]), .A2(n_1_0_1294), + .B1(n_1_0_1285), .B2(registers_26__ap[18]), .C1(n_1_0_1274), .C2( + registers_1__ap[18]), .ZN(n_1_0_1006)); + NAND2_X1_LVT i_1_0_1056 (.A1(n_1_0_1007), .A2(n_1_0_1006), .ZN(n_1_0_1005)); + SDFF_X1_LVT \registers_reg[29][18] (.D(registers[18]), .SE(dftIn), .SI( + registers_26__ap[18]), .CK(n_0_1), .Q(registers_29__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[2][18] (.D(registers[18]), .SE(dftIn), .SI( + registers_29__ap[18]), .CK(n_0_32), .Q(registers_2__ap[18]), .QN()); + AOI221_X1_LVT i_1_0_1055 (.A(n_1_0_1005), .B1(n_1_0_1276), .B2( + registers_29__ap[18]), .C1(registers_2__ap[18]), .C2(n_1_0_1268), .ZN( + n_1_0_1004)); + SDFF_X1_LVT \registers_reg[18][18] (.D(registers[18]), .SE(dftIn), .SI( + registers_1__ap[18]), .CK(n_0_48), .Q(registers_18__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[30][18] (.D(registers[18]), .SE(dftIn), .SI( + registers_2__ap[18]), .CK(n_0_2), .Q(registers_30__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1054 (.A1(registers_18__ap[18]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[18]), .ZN(n_1_0_1003)); + SDFF_X1_LVT \registers_reg[4][18] (.D(registers[18]), .SE(dftIn), .SI( + registers_6__ap[18]), .CK(n_0_34), .Q(registers_4__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[12][18] (.D(registers[18]), .SE(dftIn), .SI( + registers_16__ap[18]), .CK(n_0_42), .Q(registers_12__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1053 (.A1(registers_4__ap[18]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[18]), .ZN(n_1_0_1002)); + SDFF_X1_LVT \registers_reg[19][18] (.D(registers[18]), .SE(dftIn), .SI( + registers_18__ap[18]), .CK(n_0_49), .Q(registers_19__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[21][18] (.D(registers[18]), .SE(dftIn), .SI( + registers_19__ap[18]), .CK(n_0_51), .Q(registers_21__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1052 (.A1(registers_19__ap[18]), .A2(n_1_0_1295), .B1( + n_1_0_1259), .B2(registers_21__ap[18]), .ZN(n_1_0_1001)); + NAND3_X1_LVT i_1_0_1051 (.A1(n_1_0_1003), .A2(n_1_0_1002), .A3(n_1_0_1001), + .ZN(n_1_0_1000)); + SDFF_X1_LVT \registers_reg[5][18] (.D(registers[18]), .SE(dftIn), .SI( + registers_4__ap[18]), .CK(n_0_35), .Q(registers_5__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[20][18] (.D(registers[18]), .SE(dftIn), .SI( + registers_21__ap[18]), .CK(n_0_50), .Q(registers_20__ap[18]), .QN()); + AOI221_X1_LVT i_1_0_1050 (.A(n_1_0_1000), .B1(n_1_0_1273), .B2( + registers_5__ap[18]), .C1(registers_20__ap[18]), .C2(n_1_0_1281), .ZN( + n_1_0_999)); + SDFF_X1_LVT \registers_reg[8][18] (.D(registers[18]), .SE(dftIn), .SI( + registers_5__ap[18]), .CK(n_0_38), .Q(registers_8__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[23][18] (.D(registers[18]), .SE(dftIn), .SI( + registers_20__ap[18]), .CK(n_0_53), .Q(registers_23__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1049 (.A1(registers_8__ap[18]), .A2(n_1_0_1282), .B1( + n_1_0_1264), .B2(registers_23__ap[18]), .ZN(n_1_0_998)); + SDFF_X1_LVT \registers_reg[13][18] (.D(registers[18]), .SE(dftIn), .SI( + registers_12__ap[18]), .CK(n_0_43), .Q(registers_13__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[17][18] (.D(registers[18]), .SE(dftIn), .SI( + registers_23__ap[18]), .CK(n_0_47), .Q(registers_17__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1048 (.A1(registers_13__ap[18]), .A2(n_1_0_1277), .B1( + n_1_0_1271), .B2(registers_17__ap[18]), .ZN(n_1_0_997)); + SDFF_X1_LVT \registers_reg[15][18] (.D(registers[18]), .SE(dftIn), .SI( + registers_13__ap[18]), .CK(n_0_45), .Q(registers_15__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[14][18] (.D(registers[18]), .SE(dftIn), .SI( + registers_15__ap[18]), .CK(n_0_44), .Q(registers_14__ap[18]), .QN()); + AOI22_X1_LVT i_1_0_1047 (.A1(registers_15__ap[18]), .A2(n_1_0_1286), .B1( + n_1_0_1258), .B2(registers_14__ap[18]), .ZN(n_1_0_996)); + NAND3_X1_LVT i_1_0_1046 (.A1(n_1_0_998), .A2(n_1_0_997), .A3(n_1_0_996), + .ZN(n_1_0_995)); + SDFF_X1_LVT \registers_reg[10][18] (.D(registers[18]), .SE(dftIn), .SI( + registers_14__ap[18]), .CK(n_0_40), .Q(registers_10__ap[18]), .QN()); + SDFF_X1_LVT \registers_reg[3][18] (.D(registers[18]), .SE(dftIn), .SI( + registers_8__ap[18]), .CK(n_0_33), .Q(registers_3__ap[18]), .QN()); + AOI221_X1_LVT i_1_0_1045 (.A(n_1_0_995), .B1(n_1_0_1287), .B2( + registers_10__ap[18]), .C1(registers_3__ap[18]), .C2(n_1_0_1257), .ZN( + n_1_0_994)); + NAND4_X1_LVT i_1_0_1044 (.A1(n_1_0_1011), .A2(n_1_0_1004), .A3(n_1_0_999), + .A4(n_1_0_994), .ZN(RRs1[18])); + AND2_X1_LVT i_0_0_17 (.A1(n_0_0_16), .A2(WRd[17]), .ZN(registers[17])); + SDFF_X1_LVT \registers_reg[17][17] (.D(registers[17]), .SE(dftIn), .SI( + registers_17__ap[18]), .CK(n_0_47), .Q(registers_17__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[21][17] (.D(registers[17]), .SE(dftIn), .SI( + registers_17__ap[17]), .CK(n_0_51), .Q(registers_21__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1040 (.A1(registers_17__ap[17]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[17]), .ZN(n_1_0_990)); + SDFF_X1_LVT \registers_reg[2][17] (.D(registers[17]), .SE(dftIn), .SI( + registers_30__ap[18]), .CK(n_0_32), .Q(registers_2__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[31][17] (.D(registers[17]), .SE(dftIn), .SI( + registers_3__ap[18]), .CK(n_0_3), .Q(registers_31__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1043 (.A1(registers_2__ap[17]), .A2(n_1_0_1268), .B1( + n_1_0_1266), .B2(registers_31__ap[17]), .ZN(n_1_0_993)); + SDFF_X1_LVT \registers_reg[20][17] (.D(registers[17]), .SE(dftIn), .SI( + registers_21__ap[17]), .CK(n_0_50), .Q(registers_20__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[12][17] (.D(registers[17]), .SE(dftIn), .SI( + registers_10__ap[18]), .CK(n_0_42), .Q(registers_12__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1039 (.A1(registers_20__ap[17]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[17]), .ZN(n_1_0_989)); + SDFF_X1_LVT \registers_reg[15][17] (.D(registers[17]), .SE(dftIn), .SI( + registers_12__ap[17]), .CK(n_0_45), .Q(registers_15__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[11][17] (.D(registers[17]), .SE(dftIn), .SI( + registers_15__ap[17]), .CK(n_0_41__0), .Q(registers_11__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1042 (.A1(registers_15__ap[17]), .A2(n_1_0_1286), .B1( + n_1_0_1270), .B2(registers_11__ap[17]), .ZN(n_1_0_992)); + INV_X1_LVT i_1_0_1041 (.A(n_1_0_992), .ZN(n_1_0_991)); + SDFF_X1_LVT \registers_reg[10][17] (.D(registers[17]), .SE(dftIn), .SI( + registers_11__ap[17]), .CK(n_0_40), .Q(registers_10__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[24][17] (.D(registers[17]), .SE(dftIn), .SI( + registers_2__ap[17]), .CK(n_0_54), .Q(registers_24__ap[17]), .QN()); + AOI221_X1_LVT i_1_0_1038 (.A(n_1_0_991), .B1(n_1_0_1287), .B2( + registers_10__ap[17]), .C1(registers_24__ap[17]), .C2(n_1_0_1289), + .ZN(n_1_0_988)); + SDFF_X1_LVT \registers_reg[22][17] (.D(registers[17]), .SE(dftIn), .SI( + registers_20__ap[17]), .CK(n_0_52), .Q(registers_22__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[26][17] (.D(registers[17]), .SE(dftIn), .SI( + registers_24__ap[17]), .CK(n_0_56), .Q(registers_26__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[13][17] (.D(registers[17]), .SE(dftIn), .SI( + registers_10__ap[17]), .CK(n_0_43), .Q(registers_13__ap[17]), .QN()); + AOI222_X1_LVT i_1_0_1037 (.A1(registers_22__ap[17]), .A2(n_1_0_1294), + .B1(n_1_0_1285), .B2(registers_26__ap[17]), .C1(n_1_0_1277), .C2( + registers_13__ap[17]), .ZN(n_1_0_987)); + NAND4_X1_LVT i_1_0_1036 (.A1(n_1_0_993), .A2(n_1_0_989), .A3(n_1_0_988), + .A4(n_1_0_987), .ZN(n_1_0_986)); + SDFF_X1_LVT \registers_reg[1][17] (.D(registers[17]), .SE(dftIn), .SI( + registers_22__ap[17]), .CK(n_0_0__0), .Q(registers_1__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[28][17] (.D(registers[17]), .SE(dftIn), .SI( + registers_26__ap[17]), .CK(n_0_0__1), .Q(registers_28__ap[17]), .QN()); + AOI221_X1_LVT i_1_0_1035 (.A(n_1_0_986), .B1(n_1_0_1274), .B2( + registers_1__ap[17]), .C1(registers_28__ap[17]), .C2(n_1_0_1283), .ZN( + n_1_0_985)); + SDFF_X1_LVT \registers_reg[18][17] (.D(registers[17]), .SE(dftIn), .SI( + registers_1__ap[17]), .CK(n_0_48), .Q(registers_18__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[30][17] (.D(registers[17]), .SE(dftIn), .SI( + registers_28__ap[17]), .CK(n_0_2), .Q(registers_30__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1034 (.A1(registers_18__ap[17]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[17]), .ZN(n_1_0_984)); + SDFF_X1_LVT \registers_reg[4][17] (.D(registers[17]), .SE(dftIn), .SI( + registers_31__ap[17]), .CK(n_0_34), .Q(registers_4__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[5][17] (.D(registers[17]), .SE(dftIn), .SI( + registers_4__ap[17]), .CK(n_0_35), .Q(registers_5__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1033 (.A1(registers_4__ap[17]), .A2(n_1_0_1278), .B1( + n_1_0_1273), .B2(registers_5__ap[17]), .ZN(n_1_0_983)); + SDFF_X1_LVT \registers_reg[6][17] (.D(registers[17]), .SE(dftIn), .SI( + registers_5__ap[17]), .CK(n_0_36__0), .Q(registers_6__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[25][17] (.D(registers[17]), .SE(dftIn), .SI( + registers_30__ap[17]), .CK(n_0_55), .Q(registers_25__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1032 (.A1(registers_6__ap[17]), .A2(n_1_0_1300), .B1( + n_1_0_1269), .B2(registers_25__ap[17]), .ZN(n_1_0_982)); + NAND3_X1_LVT i_1_0_1031 (.A1(n_1_0_984), .A2(n_1_0_983), .A3(n_1_0_982), + .ZN(n_1_0_981)); + SDFF_X1_LVT \registers_reg[19][17] (.D(registers[17]), .SE(dftIn), .SI( + registers_18__ap[17]), .CK(n_0_49), .Q(registers_19__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[16][17] (.D(registers[17]), .SE(dftIn), .SI( + registers_13__ap[17]), .CK(n_0_46), .Q(registers_16__ap[17]), .QN()); + AOI221_X1_LVT i_1_0_1030 (.A(n_1_0_981), .B1(n_1_0_1295), .B2( + registers_19__ap[17]), .C1(registers_16__ap[17]), .C2(n_1_0_1267), + .ZN(n_1_0_980)); + SDFF_X1_LVT \registers_reg[7][17] (.D(registers[17]), .SE(dftIn), .SI( + registers_6__ap[17]), .CK(n_0_37), .Q(registers_7__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[14][17] (.D(registers[17]), .SE(dftIn), .SI( + registers_16__ap[17]), .CK(n_0_44), .Q(registers_14__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1029 (.A1(registers_7__ap[17]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[17]), .ZN(n_1_0_979)); + SDFF_X1_LVT \registers_reg[9][17] (.D(registers[17]), .SE(dftIn), .SI( + registers_7__ap[17]), .CK(n_0_39), .Q(registers_9__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[29][17] (.D(registers[17]), .SE(dftIn), .SI( + registers_25__ap[17]), .CK(n_0_1), .Q(registers_29__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1028 (.A1(registers_9__ap[17]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[17]), .ZN(n_1_0_978)); + SDFF_X1_LVT \registers_reg[8][17] (.D(registers[17]), .SE(dftIn), .SI( + registers_9__ap[17]), .CK(n_0_38), .Q(registers_8__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[23][17] (.D(registers[17]), .SE(dftIn), .SI( + registers_19__ap[17]), .CK(n_0_53), .Q(registers_23__ap[17]), .QN()); + AOI22_X1_LVT i_1_0_1027 (.A1(registers_8__ap[17]), .A2(n_1_0_1282), .B1( + n_1_0_1264), .B2(registers_23__ap[17]), .ZN(n_1_0_977)); + NAND3_X1_LVT i_1_0_1026 (.A1(n_1_0_979), .A2(n_1_0_978), .A3(n_1_0_977), + .ZN(n_1_0_976)); + SDFF_X1_LVT \registers_reg[27][17] (.D(registers[17]), .SE(dftIn), .SI( + registers_29__ap[17]), .CK(n_0_57__0), .Q(registers_27__ap[17]), .QN()); + SDFF_X1_LVT \registers_reg[3][17] (.D(registers[17]), .SE(dftIn), .SI( + registers_8__ap[17]), .CK(n_0_33), .Q(registers_3__ap[17]), .QN()); + AOI221_X1_LVT i_1_0_1025 (.A(n_1_0_976), .B1(n_1_0_1279), .B2( + registers_27__ap[17]), .C1(registers_3__ap[17]), .C2(n_1_0_1257), .ZN( + n_1_0_975)); + NAND4_X1_LVT i_1_0_1024 (.A1(n_1_0_990), .A2(n_1_0_985), .A3(n_1_0_980), + .A4(n_1_0_975), .ZN(RRs1[17])); + AND2_X1_LVT i_0_0_16 (.A1(n_0_0_16), .A2(WRd[16]), .ZN(registers[16])); + SDFF_X1_LVT \registers_reg[29][16] (.D(registers[16]), .SE(dftIn), .SI( + registers_27__ap[17]), .CK(n_0_1), .Q(registers_29__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[2][16] (.D(registers[16]), .SE(dftIn), .SI( + registers_29__ap[16]), .CK(n_0_32), .Q(registers_2__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1022 (.A1(registers_29__ap[16]), .A2(n_1_0_1276), .B1( + n_1_0_1268), .B2(registers_2__ap[16]), .ZN(n_1_0_973)); + SDFF_X1_LVT \registers_reg[11][16] (.D(registers[16]), .SE(dftIn), .SI( + registers_14__ap[17]), .CK(n_0_41__0), .Q(registers_11__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[25][16] (.D(registers[16]), .SE(dftIn), .SI( + registers_2__ap[16]), .CK(n_0_55), .Q(registers_25__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1023 (.A1(registers_11__ap[16]), .A2(n_1_0_1270), .B1( + n_1_0_1269), .B2(registers_25__ap[16]), .ZN(n_1_0_974)); + SDFF_X1_LVT \registers_reg[9][16] (.D(registers[16]), .SE(dftIn), .SI( + registers_3__ap[17]), .CK(n_0_39), .Q(registers_9__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[7][16] (.D(registers[16]), .SE(dftIn), .SI( + registers_9__ap[16]), .CK(n_0_37), .Q(registers_7__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1021 (.A1(registers_9__ap[16]), .A2(n_1_0_1291), .B1( + n_1_0_1263), .B2(registers_7__ap[16]), .ZN(n_1_0_972)); + SDFF_X1_LVT \registers_reg[10][16] (.D(registers[16]), .SE(dftIn), .SI( + registers_11__ap[16]), .CK(n_0_40), .Q(registers_10__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[16][16] (.D(registers[16]), .SE(dftIn), .SI( + registers_10__ap[16]), .CK(n_0_46), .Q(registers_16__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1020 (.A1(registers_10__ap[16]), .A2(n_1_0_1287), .B1( + n_1_0_1267), .B2(registers_16__ap[16]), .ZN(n_1_0_971)); + NAND3_X1_LVT i_1_0_1019 (.A1(n_1_0_974), .A2(n_1_0_972), .A3(n_1_0_971), + .ZN(n_1_0_970)); + SDFF_X1_LVT \registers_reg[31][16] (.D(registers[16]), .SE(dftIn), .SI( + registers_7__ap[16]), .CK(n_0_3), .Q(registers_31__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[6][16] (.D(registers[16]), .SE(dftIn), .SI( + registers_31__ap[16]), .CK(n_0_36__0), .Q(registers_6__ap[16]), .QN()); + AOI221_X1_LVT i_1_0_1018 (.A(n_1_0_970), .B1(n_1_0_1266), .B2( + registers_31__ap[16]), .C1(registers_6__ap[16]), .C2(n_1_0_1300), .ZN( + n_1_0_969)); + SDFF_X1_LVT \registers_reg[18][16] (.D(registers[16]), .SE(dftIn), .SI( + registers_23__ap[17]), .CK(n_0_48), .Q(registers_18__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[22][16] (.D(registers[16]), .SE(dftIn), .SI( + registers_18__ap[16]), .CK(n_0_52), .Q(registers_22__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[1][16] (.D(registers[16]), .SE(dftIn), .SI( + registers_22__ap[16]), .CK(n_0_0__0), .Q(registers_1__ap[16]), .QN()); + AOI222_X1_LVT i_1_0_1017 (.A1(registers_18__ap[16]), .A2(n_1_0_1297), + .B1(n_1_0_1294), .B2(registers_22__ap[16]), .C1(registers_1__ap[16]), + .C2(n_1_0_1274), .ZN(n_1_0_968)); + NAND3_X1_LVT i_1_0_1016 (.A1(n_1_0_973), .A2(n_1_0_969), .A3(n_1_0_968), + .ZN(n_1_0_967)); + SDFF_X1_LVT \registers_reg[5][16] (.D(registers[16]), .SE(dftIn), .SI( + registers_6__ap[16]), .CK(n_0_35), .Q(registers_5__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[28][16] (.D(registers[16]), .SE(dftIn), .SI( + registers_25__ap[16]), .CK(n_0_0__1), .Q(registers_28__ap[16]), .QN()); + AOI221_X1_LVT i_1_0_1015 (.A(n_1_0_967), .B1(n_1_0_1273), .B2( + registers_5__ap[16]), .C1(registers_28__ap[16]), .C2(n_1_0_1283), .ZN( + n_1_0_966)); + SDFF_X1_LVT \registers_reg[4][16] (.D(registers[16]), .SE(dftIn), .SI( + registers_5__ap[16]), .CK(n_0_34), .Q(registers_4__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[12][16] (.D(registers[16]), .SE(dftIn), .SI( + registers_16__ap[16]), .CK(n_0_42), .Q(registers_12__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1014 (.A1(registers_4__ap[16]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[16]), .ZN(n_1_0_965)); + SDFF_X1_LVT \registers_reg[19][16] (.D(registers[16]), .SE(dftIn), .SI( + registers_1__ap[16]), .CK(n_0_49), .Q(registers_19__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[21][16] (.D(registers[16]), .SE(dftIn), .SI( + registers_19__ap[16]), .CK(n_0_51), .Q(registers_21__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1013 (.A1(registers_19__ap[16]), .A2(n_1_0_1295), .B1( + n_1_0_1259), .B2(registers_21__ap[16]), .ZN(n_1_0_964)); + SDFF_X1_LVT \registers_reg[24][16] (.D(registers[16]), .SE(dftIn), .SI( + registers_28__ap[16]), .CK(n_0_54), .Q(registers_24__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[20][16] (.D(registers[16]), .SE(dftIn), .SI( + registers_21__ap[16]), .CK(n_0_50), .Q(registers_20__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1012 (.A1(registers_24__ap[16]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[16]), .ZN(n_1_0_963)); + NAND3_X1_LVT i_1_0_1011 (.A1(n_1_0_965), .A2(n_1_0_964), .A3(n_1_0_963), + .ZN(n_1_0_962)); + SDFF_X1_LVT \registers_reg[26][16] (.D(registers[16]), .SE(dftIn), .SI( + registers_24__ap[16]), .CK(n_0_56), .Q(registers_26__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[30][16] (.D(registers[16]), .SE(dftIn), .SI( + registers_26__ap[16]), .CK(n_0_2), .Q(registers_30__ap[16]), .QN()); + AOI221_X1_LVT i_1_0_1010 (.A(n_1_0_962), .B1(n_1_0_1285), .B2( + registers_26__ap[16]), .C1(registers_30__ap[16]), .C2(n_1_0_1272), + .ZN(n_1_0_961)); + SDFF_X1_LVT \registers_reg[8][16] (.D(registers[16]), .SE(dftIn), .SI( + registers_4__ap[16]), .CK(n_0_38), .Q(registers_8__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[23][16] (.D(registers[16]), .SE(dftIn), .SI( + registers_20__ap[16]), .CK(n_0_53), .Q(registers_23__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1009 (.A1(registers_8__ap[16]), .A2(n_1_0_1282), .B1( + n_1_0_1264), .B2(registers_23__ap[16]), .ZN(n_1_0_960)); + SDFF_X1_LVT \registers_reg[13][16] (.D(registers[16]), .SE(dftIn), .SI( + registers_12__ap[16]), .CK(n_0_43), .Q(registers_13__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[17][16] (.D(registers[16]), .SE(dftIn), .SI( + registers_23__ap[16]), .CK(n_0_47), .Q(registers_17__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1008 (.A1(registers_13__ap[16]), .A2(n_1_0_1277), .B1( + n_1_0_1271), .B2(registers_17__ap[16]), .ZN(n_1_0_959)); + SDFF_X1_LVT \registers_reg[15][16] (.D(registers[16]), .SE(dftIn), .SI( + registers_13__ap[16]), .CK(n_0_45), .Q(registers_15__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[14][16] (.D(registers[16]), .SE(dftIn), .SI( + registers_15__ap[16]), .CK(n_0_44), .Q(registers_14__ap[16]), .QN()); + AOI22_X1_LVT i_1_0_1007 (.A1(registers_15__ap[16]), .A2(n_1_0_1286), .B1( + n_1_0_1258), .B2(registers_14__ap[16]), .ZN(n_1_0_958)); + NAND3_X1_LVT i_1_0_1006 (.A1(n_1_0_960), .A2(n_1_0_959), .A3(n_1_0_958), + .ZN(n_1_0_957)); + SDFF_X1_LVT \registers_reg[27][16] (.D(registers[16]), .SE(dftIn), .SI( + registers_30__ap[16]), .CK(n_0_57__0), .Q(registers_27__ap[16]), .QN()); + SDFF_X1_LVT \registers_reg[3][16] (.D(registers[16]), .SE(dftIn), .SI( + registers_8__ap[16]), .CK(n_0_33), .Q(registers_3__ap[16]), .QN()); + AOI221_X1_LVT i_1_0_1005 (.A(n_1_0_957), .B1(n_1_0_1279), .B2( + registers_27__ap[16]), .C1(registers_3__ap[16]), .C2(n_1_0_1257), .ZN( + n_1_0_956)); + NAND3_X1_LVT i_1_0_1004 (.A1(n_1_0_966), .A2(n_1_0_961), .A3(n_1_0_956), + .ZN(RRs1[16])); + AND2_X1_LVT i_0_0_15 (.A1(n_0_0_16), .A2(WRd[15]), .ZN(registers[15])); + SDFF_X1_LVT \registers_reg[17][15] (.D(registers[15]), .SE(dftIn), .SI( + registers_17__ap[16]), .CK(n_0_47), .Q(registers_17__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[21][15] (.D(registers[15]), .SE(dftIn), .SI( + registers_17__ap[15]), .CK(n_0_51), .Q(registers_21__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_1000 (.A1(registers_17__ap[15]), .A2(n_1_0_1271), .B1( + n_1_0_1259), .B2(registers_21__ap[15]), .ZN(n_1_0_952)); + SDFF_X1_LVT \registers_reg[10][15] (.D(registers[15]), .SE(dftIn), .SI( + registers_14__ap[16]), .CK(n_0_40), .Q(registers_10__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[2][15] (.D(registers[15]), .SE(dftIn), .SI( + registers_27__ap[16]), .CK(n_0_32), .Q(registers_2__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_1003 (.A1(registers_10__ap[15]), .A2(n_1_0_1287), .B1( + n_1_0_1268), .B2(registers_2__ap[15]), .ZN(n_1_0_955)); + SDFF_X1_LVT \registers_reg[20][15] (.D(registers[15]), .SE(dftIn), .SI( + registers_21__ap[15]), .CK(n_0_50), .Q(registers_20__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[12][15] (.D(registers[15]), .SE(dftIn), .SI( + registers_10__ap[15]), .CK(n_0_42), .Q(registers_12__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_999 (.A1(registers_20__ap[15]), .A2(n_1_0_1281), .B1( + n_1_0_1260), .B2(registers_12__ap[15]), .ZN(n_1_0_951)); + SDFF_X1_LVT \registers_reg[15][15] (.D(registers[15]), .SE(dftIn), .SI( + registers_12__ap[15]), .CK(n_0_45), .Q(registers_15__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[8][15] (.D(registers[15]), .SE(dftIn), .SI( + registers_3__ap[16]), .CK(n_0_38), .Q(registers_8__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_1002 (.A1(registers_15__ap[15]), .A2(n_1_0_1286), .B1( + n_1_0_1282), .B2(registers_8__ap[15]), .ZN(n_1_0_954)); + INV_X1_LVT i_1_0_1001 (.A(n_1_0_954), .ZN(n_1_0_953)); + SDFF_X1_LVT \registers_reg[11][15] (.D(registers[15]), .SE(dftIn), .SI( + registers_15__ap[15]), .CK(n_0_41__0), .Q(registers_11__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[24][15] (.D(registers[15]), .SE(dftIn), .SI( + registers_2__ap[15]), .CK(n_0_54), .Q(registers_24__ap[15]), .QN()); + AOI221_X1_LVT i_1_0_998 (.A(n_1_0_953), .B1(n_1_0_1270), .B2( + registers_11__ap[15]), .C1(registers_24__ap[15]), .C2(n_1_0_1289), + .ZN(n_1_0_950)); + SDFF_X1_LVT \registers_reg[13][15] (.D(registers[15]), .SE(dftIn), .SI( + registers_11__ap[15]), .CK(n_0_43), .Q(registers_13__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[30][15] (.D(registers[15]), .SE(dftIn), .SI( + registers_24__ap[15]), .CK(n_0_2), .Q(registers_30__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[22][15] (.D(registers[15]), .SE(dftIn), .SI( + registers_20__ap[15]), .CK(n_0_52), .Q(registers_22__ap[15]), .QN()); + AOI222_X1_LVT i_1_0_997 (.A1(registers_13__ap[15]), .A2(n_1_0_1277), .B1( + n_1_0_1272), .B2(registers_30__ap[15]), .C1(registers_22__ap[15]), + .C2(n_1_0_1294), .ZN(n_1_0_949)); + NAND4_X1_LVT i_1_0_996 (.A1(n_1_0_955), .A2(n_1_0_951), .A3(n_1_0_950), + .A4(n_1_0_949), .ZN(n_1_0_948)); + SDFF_X1_LVT \registers_reg[1][15] (.D(registers[15]), .SE(dftIn), .SI( + registers_22__ap[15]), .CK(n_0_0__0), .Q(registers_1__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[28][15] (.D(registers[15]), .SE(dftIn), .SI( + registers_30__ap[15]), .CK(n_0_0__1), .Q(registers_28__ap[15]), .QN()); + AOI221_X1_LVT i_1_0_995 (.A(n_1_0_948), .B1(n_1_0_1274), .B2( + registers_1__ap[15]), .C1(registers_28__ap[15]), .C2(n_1_0_1283), .ZN( + n_1_0_947)); + SDFF_X1_LVT \registers_reg[18][15] (.D(registers[15]), .SE(dftIn), .SI( + registers_1__ap[15]), .CK(n_0_48), .Q(registers_18__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[26][15] (.D(registers[15]), .SE(dftIn), .SI( + registers_28__ap[15]), .CK(n_0_56), .Q(registers_26__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_994 (.A1(registers_18__ap[15]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[15]), .ZN(n_1_0_946)); + SDFF_X1_LVT \registers_reg[4][15] (.D(registers[15]), .SE(dftIn), .SI( + registers_8__ap[15]), .CK(n_0_34), .Q(registers_4__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[5][15] (.D(registers[15]), .SE(dftIn), .SI( + registers_4__ap[15]), .CK(n_0_35), .Q(registers_5__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_993 (.A1(registers_4__ap[15]), .A2(n_1_0_1278), .B1( + n_1_0_1273), .B2(registers_5__ap[15]), .ZN(n_1_0_945)); + SDFF_X1_LVT \registers_reg[6][15] (.D(registers[15]), .SE(dftIn), .SI( + registers_5__ap[15]), .CK(n_0_36__0), .Q(registers_6__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[16][15] (.D(registers[15]), .SE(dftIn), .SI( + registers_13__ap[15]), .CK(n_0_46), .Q(registers_16__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_992 (.A1(registers_6__ap[15]), .A2(n_1_0_1300), .B1( + n_1_0_1267), .B2(registers_16__ap[15]), .ZN(n_1_0_944)); + NAND3_X1_LVT i_1_0_991 (.A1(n_1_0_946), .A2(n_1_0_945), .A3(n_1_0_944), + .ZN(n_1_0_943)); + SDFF_X1_LVT \registers_reg[19][15] (.D(registers[15]), .SE(dftIn), .SI( + registers_18__ap[15]), .CK(n_0_49), .Q(registers_19__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[25][15] (.D(registers[15]), .SE(dftIn), .SI( + registers_26__ap[15]), .CK(n_0_55), .Q(registers_25__ap[15]), .QN()); + AOI221_X1_LVT i_1_0_990 (.A(n_1_0_943), .B1(n_1_0_1295), .B2( + registers_19__ap[15]), .C1(registers_25__ap[15]), .C2(n_1_0_1269), + .ZN(n_1_0_942)); + SDFF_X1_LVT \registers_reg[7][15] (.D(registers[15]), .SE(dftIn), .SI( + registers_6__ap[15]), .CK(n_0_37), .Q(registers_7__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[14][15] (.D(registers[15]), .SE(dftIn), .SI( + registers_16__ap[15]), .CK(n_0_44), .Q(registers_14__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_989 (.A1(registers_7__ap[15]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[15]), .ZN(n_1_0_941)); + SDFF_X1_LVT \registers_reg[9][15] (.D(registers[15]), .SE(dftIn), .SI( + registers_7__ap[15]), .CK(n_0_39), .Q(registers_9__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[29][15] (.D(registers[15]), .SE(dftIn), .SI( + registers_25__ap[15]), .CK(n_0_1), .Q(registers_29__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_988 (.A1(registers_9__ap[15]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[15]), .ZN(n_1_0_940)); + SDFF_X1_LVT \registers_reg[23][15] (.D(registers[15]), .SE(dftIn), .SI( + registers_19__ap[15]), .CK(n_0_53), .Q(registers_23__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[3][15] (.D(registers[15]), .SE(dftIn), .SI( + registers_9__ap[15]), .CK(n_0_33), .Q(registers_3__ap[15]), .QN()); + AOI22_X1_LVT i_1_0_987 (.A1(registers_23__ap[15]), .A2(n_1_0_1264), .B1( + n_1_0_1257), .B2(registers_3__ap[15]), .ZN(n_1_0_939)); + NAND3_X1_LVT i_1_0_986 (.A1(n_1_0_941), .A2(n_1_0_940), .A3(n_1_0_939), + .ZN(n_1_0_938)); + SDFF_X1_LVT \registers_reg[27][15] (.D(registers[15]), .SE(dftIn), .SI( + registers_29__ap[15]), .CK(n_0_57__0), .Q(registers_27__ap[15]), .QN()); + SDFF_X1_LVT \registers_reg[31][15] (.D(registers[15]), .SE(dftIn), .SI( + registers_3__ap[15]), .CK(n_0_3), .Q(registers_31__ap[15]), .QN()); + AOI221_X1_LVT i_1_0_985 (.A(n_1_0_938), .B1(n_1_0_1279), .B2( + registers_27__ap[15]), .C1(registers_31__ap[15]), .C2(n_1_0_1266), + .ZN(n_1_0_937)); + NAND4_X1_LVT i_1_0_984 (.A1(n_1_0_952), .A2(n_1_0_947), .A3(n_1_0_942), + .A4(n_1_0_937), .ZN(RRs1[15])); + AND2_X1_LVT i_0_0_14 (.A1(n_0_0_16), .A2(WRd[14]), .ZN(registers[14])); + SDFF_X1_LVT \registers_reg[28][14] (.D(registers[14]), .SE(dftIn), .SI( + registers_27__ap[15]), .CK(n_0_0__1), .Q(registers_28__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[5][14] (.D(registers[14]), .SE(dftIn), .SI( + registers_31__ap[15]), .CK(n_0_35), .Q(registers_5__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_983 (.A1(registers_28__ap[14]), .A2(n_1_0_1283), .B1( + n_1_0_1273), .B2(registers_5__ap[14]), .ZN(n_1_0_936)); + SDFF_X1_LVT \registers_reg[18][14] (.D(registers[14]), .SE(dftIn), .SI( + registers_23__ap[15]), .CK(n_0_48), .Q(registers_18__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[10][14] (.D(registers[14]), .SE(dftIn), .SI( + registers_14__ap[15]), .CK(n_0_40), .Q(registers_10__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[8][14] (.D(registers[14]), .SE(dftIn), .SI( + registers_5__ap[14]), .CK(n_0_38), .Q(registers_8__ap[14]), .QN()); + AOI222_X1_LVT i_1_0_982 (.A1(registers_18__ap[14]), .A2(n_1_0_1297), .B1( + n_1_0_1287), .B2(registers_10__ap[14]), .C1(n_1_0_1282), .C2( + registers_8__ap[14]), .ZN(n_1_0_935)); + SDFF_X1_LVT \registers_reg[9][14] (.D(registers[14]), .SE(dftIn), .SI( + registers_8__ap[14]), .CK(n_0_39), .Q(registers_9__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[29][14] (.D(registers[14]), .SE(dftIn), .SI( + registers_28__ap[14]), .CK(n_0_1), .Q(registers_29__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_981 (.A1(registers_9__ap[14]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[14]), .ZN(n_1_0_934)); + SDFF_X1_LVT \registers_reg[21][14] (.D(registers[14]), .SE(dftIn), .SI( + registers_18__ap[14]), .CK(n_0_51), .Q(registers_21__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[14][14] (.D(registers[14]), .SE(dftIn), .SI( + registers_10__ap[14]), .CK(n_0_44), .Q(registers_14__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_980 (.A1(registers_21__ap[14]), .A2(n_1_0_1259), .B1( + n_1_0_1258), .B2(registers_14__ap[14]), .ZN(n_1_0_933)); + SDFF_X1_LVT \registers_reg[16][14] (.D(registers[14]), .SE(dftIn), .SI( + registers_14__ap[14]), .CK(n_0_46), .Q(registers_16__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[3][14] (.D(registers[14]), .SE(dftIn), .SI( + registers_9__ap[14]), .CK(n_0_33), .Q(registers_3__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_979 (.A1(registers_16__ap[14]), .A2(n_1_0_1267), .B1( + n_1_0_1257), .B2(registers_3__ap[14]), .ZN(n_1_0_932)); + SDFF_X1_LVT \registers_reg[17][14] (.D(registers[14]), .SE(dftIn), .SI( + registers_21__ap[14]), .CK(n_0_47), .Q(registers_17__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[31][14] (.D(registers[14]), .SE(dftIn), .SI( + registers_3__ap[14]), .CK(n_0_3), .Q(registers_31__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_978 (.A1(registers_17__ap[14]), .A2(n_1_0_1271), .B1( + n_1_0_1266), .B2(registers_31__ap[14]), .ZN(n_1_0_931)); + SDFF_X1_LVT \registers_reg[15][14] (.D(registers[14]), .SE(dftIn), .SI( + registers_16__ap[14]), .CK(n_0_45), .Q(registers_15__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[23][14] (.D(registers[14]), .SE(dftIn), .SI( + registers_17__ap[14]), .CK(n_0_53), .Q(registers_23__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_977 (.A1(registers_15__ap[14]), .A2(n_1_0_1286), .B1( + n_1_0_1264), .B2(registers_23__ap[14]), .ZN(n_1_0_930)); + NAND4_X1_LVT i_1_0_976 (.A1(n_1_0_933), .A2(n_1_0_932), .A3(n_1_0_931), + .A4(n_1_0_930), .ZN(n_1_0_929)); + SDFF_X1_LVT \registers_reg[26][14] (.D(registers[14]), .SE(dftIn), .SI( + registers_29__ap[14]), .CK(n_0_56), .Q(registers_26__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[30][14] (.D(registers[14]), .SE(dftIn), .SI( + registers_26__ap[14]), .CK(n_0_2), .Q(registers_30__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_975 (.A1(registers_26__ap[14]), .A2(n_1_0_1285), .B1( + n_1_0_1272), .B2(registers_30__ap[14]), .ZN(n_1_0_928)); + SDFF_X1_LVT \registers_reg[20][14] (.D(registers[14]), .SE(dftIn), .SI( + registers_23__ap[14]), .CK(n_0_50), .Q(registers_20__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[4][14] (.D(registers[14]), .SE(dftIn), .SI( + registers_31__ap[14]), .CK(n_0_34), .Q(registers_4__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_974 (.A1(registers_20__ap[14]), .A2(n_1_0_1281), .B1( + n_1_0_1278), .B2(registers_4__ap[14]), .ZN(n_1_0_927)); + SDFF_X1_LVT \registers_reg[1][14] (.D(registers[14]), .SE(dftIn), .SI( + registers_20__ap[14]), .CK(n_0_0__0), .Q(registers_1__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[2][14] (.D(registers[14]), .SE(dftIn), .SI( + registers_30__ap[14]), .CK(n_0_32), .Q(registers_2__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_973 (.A1(registers_1__ap[14]), .A2(n_1_0_1274), .B1( + n_1_0_1268), .B2(registers_2__ap[14]), .ZN(n_1_0_926)); + SDFF_X1_LVT \registers_reg[24][14] (.D(registers[14]), .SE(dftIn), .SI( + registers_2__ap[14]), .CK(n_0_54), .Q(registers_24__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[12][14] (.D(registers[14]), .SE(dftIn), .SI( + registers_15__ap[14]), .CK(n_0_42), .Q(registers_12__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_972 (.A1(registers_24__ap[14]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[14]), .ZN(n_1_0_925)); + NAND4_X1_LVT i_1_0_971 (.A1(n_1_0_928), .A2(n_1_0_927), .A3(n_1_0_926), + .A4(n_1_0_925), .ZN(n_1_0_924)); + SDFF_X1_LVT \registers_reg[19][14] (.D(registers[14]), .SE(dftIn), .SI( + registers_1__ap[14]), .CK(n_0_49), .Q(registers_19__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[22][14] (.D(registers[14]), .SE(dftIn), .SI( + registers_19__ap[14]), .CK(n_0_52), .Q(registers_22__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_970 (.A1(registers_19__ap[14]), .A2(n_1_0_1295), .B1( + n_1_0_1294), .B2(registers_22__ap[14]), .ZN(n_1_0_923)); + SDFF_X1_LVT \registers_reg[13][14] (.D(registers[14]), .SE(dftIn), .SI( + registers_12__ap[14]), .CK(n_0_43), .Q(registers_13__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[25][14] (.D(registers[14]), .SE(dftIn), .SI( + registers_24__ap[14]), .CK(n_0_55), .Q(registers_25__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_969 (.A1(registers_13__ap[14]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[14]), .ZN(n_1_0_922)); + SDFF_X1_LVT \registers_reg[6][14] (.D(registers[14]), .SE(dftIn), .SI( + registers_4__ap[14]), .CK(n_0_36__0), .Q(registers_6__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[7][14] (.D(registers[14]), .SE(dftIn), .SI( + registers_6__ap[14]), .CK(n_0_37), .Q(registers_7__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_968 (.A1(registers_6__ap[14]), .A2(n_1_0_1300), .B1( + n_1_0_1263), .B2(registers_7__ap[14]), .ZN(n_1_0_921)); + SDFF_X1_LVT \registers_reg[27][14] (.D(registers[14]), .SE(dftIn), .SI( + registers_25__ap[14]), .CK(n_0_57__0), .Q(registers_27__ap[14]), .QN()); + SDFF_X1_LVT \registers_reg[11][14] (.D(registers[14]), .SE(dftIn), .SI( + registers_13__ap[14]), .CK(n_0_41__0), .Q(registers_11__ap[14]), .QN()); + AOI22_X1_LVT i_1_0_967 (.A1(registers_27__ap[14]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[14]), .ZN(n_1_0_920)); + NAND4_X1_LVT i_1_0_966 (.A1(n_1_0_923), .A2(n_1_0_922), .A3(n_1_0_921), + .A4(n_1_0_920), .ZN(n_1_0_919)); + NOR3_X1_LVT i_1_0_965 (.A1(n_1_0_929), .A2(n_1_0_924), .A3(n_1_0_919), + .ZN(n_1_0_918)); + NAND4_X1_LVT i_1_0_964 (.A1(n_1_0_936), .A2(n_1_0_935), .A3(n_1_0_934), + .A4(n_1_0_918), .ZN(RRs1[14])); + AND2_X1_LVT i_0_0_13 (.A1(n_0_0_16), .A2(WRd[13]), .ZN(registers[13])); + SDFF_X1_LVT \registers_reg[28][13] (.D(registers[13]), .SE(dftIn), .SI( + registers_27__ap[14]), .CK(n_0_0__1), .Q(registers_28__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[4][13] (.D(registers[13]), .SE(dftIn), .SI( + registers_7__ap[14]), .CK(n_0_34), .Q(registers_4__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_963 (.A1(registers_28__ap[13]), .A2(n_1_0_1283), .B1( + n_1_0_1278), .B2(registers_4__ap[13]), .ZN(n_1_0_917)); + SDFF_X1_LVT \registers_reg[10][13] (.D(registers[13]), .SE(dftIn), .SI( + registers_11__ap[14]), .CK(n_0_40), .Q(registers_10__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[26][13] (.D(registers[13]), .SE(dftIn), .SI( + registers_28__ap[13]), .CK(n_0_56), .Q(registers_26__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[8][13] (.D(registers[13]), .SE(dftIn), .SI( + registers_4__ap[13]), .CK(n_0_38), .Q(registers_8__ap[13]), .QN()); + AOI222_X1_LVT i_1_0_962 (.A1(registers_10__ap[13]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[13]), .C1(registers_8__ap[13]), .C2( + n_1_0_1282), .ZN(n_1_0_916)); + SDFF_X1_LVT \registers_reg[9][13] (.D(registers[13]), .SE(dftIn), .SI( + registers_8__ap[13]), .CK(n_0_39), .Q(registers_9__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[29][13] (.D(registers[13]), .SE(dftIn), .SI( + registers_26__ap[13]), .CK(n_0_1), .Q(registers_29__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_961 (.A1(registers_9__ap[13]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[13]), .ZN(n_1_0_915)); + SDFF_X1_LVT \registers_reg[6][13] (.D(registers[13]), .SE(dftIn), .SI( + registers_9__ap[13]), .CK(n_0_36__0), .Q(registers_6__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[1][13] (.D(registers[13]), .SE(dftIn), .SI( + registers_22__ap[14]), .CK(n_0_0__0), .Q(registers_1__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_960 (.A1(registers_6__ap[13]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[13]), .ZN(n_1_0_914)); + SDFF_X1_LVT \registers_reg[5][13] (.D(registers[13]), .SE(dftIn), .SI( + registers_6__ap[13]), .CK(n_0_35), .Q(registers_5__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[3][13] (.D(registers[13]), .SE(dftIn), .SI( + registers_5__ap[13]), .CK(n_0_33), .Q(registers_3__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_959 (.A1(registers_5__ap[13]), .A2(n_1_0_1273), .B1( + n_1_0_1257), .B2(registers_3__ap[13]), .ZN(n_1_0_913)); + SDFF_X1_LVT \registers_reg[16][13] (.D(registers[13]), .SE(dftIn), .SI( + registers_10__ap[13]), .CK(n_0_46), .Q(registers_16__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[31][13] (.D(registers[13]), .SE(dftIn), .SI( + registers_3__ap[13]), .CK(n_0_3), .Q(registers_31__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_958 (.A1(registers_16__ap[13]), .A2(n_1_0_1267), .B1( + n_1_0_1266), .B2(registers_31__ap[13]), .ZN(n_1_0_912)); + SDFF_X1_LVT \registers_reg[15][13] (.D(registers[13]), .SE(dftIn), .SI( + registers_16__ap[13]), .CK(n_0_45), .Q(registers_15__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[23][13] (.D(registers[13]), .SE(dftIn), .SI( + registers_1__ap[13]), .CK(n_0_53), .Q(registers_23__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_957 (.A1(registers_15__ap[13]), .A2(n_1_0_1286), .B1( + n_1_0_1264), .B2(registers_23__ap[13]), .ZN(n_1_0_911)); + NAND4_X1_LVT i_1_0_956 (.A1(n_1_0_914), .A2(n_1_0_913), .A3(n_1_0_912), + .A4(n_1_0_911), .ZN(n_1_0_910)); + SDFF_X1_LVT \registers_reg[18][13] (.D(registers[13]), .SE(dftIn), .SI( + registers_23__ap[13]), .CK(n_0_48), .Q(registers_18__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[30][13] (.D(registers[13]), .SE(dftIn), .SI( + registers_29__ap[13]), .CK(n_0_2), .Q(registers_30__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_955 (.A1(registers_18__ap[13]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[13]), .ZN(n_1_0_909)); + SDFF_X1_LVT \registers_reg[24][13] (.D(registers[13]), .SE(dftIn), .SI( + registers_30__ap[13]), .CK(n_0_54), .Q(registers_24__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[12][13] (.D(registers[13]), .SE(dftIn), .SI( + registers_15__ap[13]), .CK(n_0_42), .Q(registers_12__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_954 (.A1(registers_24__ap[13]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[13]), .ZN(n_1_0_908)); + SDFF_X1_LVT \registers_reg[22][13] (.D(registers[13]), .SE(dftIn), .SI( + registers_18__ap[13]), .CK(n_0_52), .Q(registers_22__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[21][13] (.D(registers[13]), .SE(dftIn), .SI( + registers_22__ap[13]), .CK(n_0_51), .Q(registers_21__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_953 (.A1(registers_22__ap[13]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[13]), .ZN(n_1_0_907)); + SDFF_X1_LVT \registers_reg[20][13] (.D(registers[13]), .SE(dftIn), .SI( + registers_21__ap[13]), .CK(n_0_50), .Q(registers_20__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[17][13] (.D(registers[13]), .SE(dftIn), .SI( + registers_20__ap[13]), .CK(n_0_47), .Q(registers_17__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_952 (.A1(registers_20__ap[13]), .A2(n_1_0_1281), .B1( + n_1_0_1271), .B2(registers_17__ap[13]), .ZN(n_1_0_906)); + NAND4_X1_LVT i_1_0_951 (.A1(n_1_0_909), .A2(n_1_0_908), .A3(n_1_0_907), + .A4(n_1_0_906), .ZN(n_1_0_905)); + SDFF_X1_LVT \registers_reg[13][13] (.D(registers[13]), .SE(dftIn), .SI( + registers_12__ap[13]), .CK(n_0_43), .Q(registers_13__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[25][13] (.D(registers[13]), .SE(dftIn), .SI( + registers_24__ap[13]), .CK(n_0_55), .Q(registers_25__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_950 (.A1(registers_13__ap[13]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[13]), .ZN(n_1_0_904)); + SDFF_X1_LVT \registers_reg[19][13] (.D(registers[13]), .SE(dftIn), .SI( + registers_17__ap[13]), .CK(n_0_49), .Q(registers_19__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[2][13] (.D(registers[13]), .SE(dftIn), .SI( + registers_25__ap[13]), .CK(n_0_32), .Q(registers_2__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_949 (.A1(registers_19__ap[13]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[13]), .ZN(n_1_0_903)); + SDFF_X1_LVT \registers_reg[7][13] (.D(registers[13]), .SE(dftIn), .SI( + registers_31__ap[13]), .CK(n_0_37), .Q(registers_7__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[14][13] (.D(registers[13]), .SE(dftIn), .SI( + registers_13__ap[13]), .CK(n_0_44), .Q(registers_14__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_948 (.A1(registers_7__ap[13]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[13]), .ZN(n_1_0_902)); + SDFF_X1_LVT \registers_reg[27][13] (.D(registers[13]), .SE(dftIn), .SI( + registers_2__ap[13]), .CK(n_0_57__0), .Q(registers_27__ap[13]), .QN()); + SDFF_X1_LVT \registers_reg[11][13] (.D(registers[13]), .SE(dftIn), .SI( + registers_14__ap[13]), .CK(n_0_41__0), .Q(registers_11__ap[13]), .QN()); + AOI22_X1_LVT i_1_0_947 (.A1(registers_27__ap[13]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[13]), .ZN(n_1_0_901)); + NAND4_X1_LVT i_1_0_946 (.A1(n_1_0_904), .A2(n_1_0_903), .A3(n_1_0_902), + .A4(n_1_0_901), .ZN(n_1_0_900)); + NOR3_X1_LVT i_1_0_945 (.A1(n_1_0_910), .A2(n_1_0_905), .A3(n_1_0_900), + .ZN(n_1_0_899)); + NAND4_X1_LVT i_1_0_944 (.A1(n_1_0_917), .A2(n_1_0_916), .A3(n_1_0_915), + .A4(n_1_0_899), .ZN(RRs1[13])); + AND2_X1_LVT i_0_0_12 (.A1(n_0_0_16), .A2(WRd[12]), .ZN(registers[12])); + SDFF_X1_LVT \registers_reg[28][12] (.D(registers[12]), .SE(dftIn), .SI( + registers_27__ap[13]), .CK(n_0_0__1), .Q(registers_28__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[17][12] (.D(registers[12]), .SE(dftIn), .SI( + registers_19__ap[13]), .CK(n_0_47), .Q(registers_17__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_943 (.A1(registers_28__ap[12]), .A2(n_1_0_1283), .B1( + n_1_0_1271), .B2(registers_17__ap[12]), .ZN(n_1_0_898)); + SDFF_X1_LVT \registers_reg[10][12] (.D(registers[12]), .SE(dftIn), .SI( + registers_11__ap[13]), .CK(n_0_40), .Q(registers_10__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[26][12] (.D(registers[12]), .SE(dftIn), .SI( + registers_28__ap[12]), .CK(n_0_56), .Q(registers_26__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[8][12] (.D(registers[12]), .SE(dftIn), .SI( + registers_7__ap[13]), .CK(n_0_38), .Q(registers_8__ap[12]), .QN()); + AOI222_X1_LVT i_1_0_942 (.A1(registers_10__ap[12]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[12]), .C1(registers_8__ap[12]), .C2( + n_1_0_1282), .ZN(n_1_0_897)); + SDFF_X1_LVT \registers_reg[9][12] (.D(registers[12]), .SE(dftIn), .SI( + registers_8__ap[12]), .CK(n_0_39), .Q(registers_9__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[29][12] (.D(registers[12]), .SE(dftIn), .SI( + registers_26__ap[12]), .CK(n_0_1), .Q(registers_29__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_941 (.A1(registers_9__ap[12]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[12]), .ZN(n_1_0_896)); + SDFF_X1_LVT \registers_reg[6][12] (.D(registers[12]), .SE(dftIn), .SI( + registers_9__ap[12]), .CK(n_0_36__0), .Q(registers_6__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[1][12] (.D(registers[12]), .SE(dftIn), .SI( + registers_17__ap[12]), .CK(n_0_0__0), .Q(registers_1__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_940 (.A1(registers_6__ap[12]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[12]), .ZN(n_1_0_895)); + SDFF_X1_LVT \registers_reg[16][12] (.D(registers[12]), .SE(dftIn), .SI( + registers_10__ap[12]), .CK(n_0_46), .Q(registers_16__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[3][12] (.D(registers[12]), .SE(dftIn), .SI( + registers_6__ap[12]), .CK(n_0_33), .Q(registers_3__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_939 (.A1(registers_16__ap[12]), .A2(n_1_0_1267), .B1( + n_1_0_1257), .B2(registers_3__ap[12]), .ZN(n_1_0_894)); + SDFF_X1_LVT \registers_reg[5][12] (.D(registers[12]), .SE(dftIn), .SI( + registers_3__ap[12]), .CK(n_0_35), .Q(registers_5__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[31][12] (.D(registers[12]), .SE(dftIn), .SI( + registers_5__ap[12]), .CK(n_0_3), .Q(registers_31__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_938 (.A1(registers_5__ap[12]), .A2(n_1_0_1273), .B1( + n_1_0_1266), .B2(registers_31__ap[12]), .ZN(n_1_0_893)); + SDFF_X1_LVT \registers_reg[15][12] (.D(registers[12]), .SE(dftIn), .SI( + registers_16__ap[12]), .CK(n_0_45), .Q(registers_15__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[23][12] (.D(registers[12]), .SE(dftIn), .SI( + registers_1__ap[12]), .CK(n_0_53), .Q(registers_23__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_937 (.A1(registers_15__ap[12]), .A2(n_1_0_1286), .B1( + n_1_0_1264), .B2(registers_23__ap[12]), .ZN(n_1_0_892)); + NAND4_X1_LVT i_1_0_936 (.A1(n_1_0_895), .A2(n_1_0_894), .A3(n_1_0_893), + .A4(n_1_0_892), .ZN(n_1_0_891)); + SDFF_X1_LVT \registers_reg[18][12] (.D(registers[12]), .SE(dftIn), .SI( + registers_23__ap[12]), .CK(n_0_48), .Q(registers_18__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[30][12] (.D(registers[12]), .SE(dftIn), .SI( + registers_29__ap[12]), .CK(n_0_2), .Q(registers_30__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_935 (.A1(registers_18__ap[12]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[12]), .ZN(n_1_0_890)); + SDFF_X1_LVT \registers_reg[20][12] (.D(registers[12]), .SE(dftIn), .SI( + registers_18__ap[12]), .CK(n_0_50), .Q(registers_20__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[4][12] (.D(registers[12]), .SE(dftIn), .SI( + registers_31__ap[12]), .CK(n_0_34), .Q(registers_4__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_934 (.A1(registers_20__ap[12]), .A2(n_1_0_1281), .B1( + n_1_0_1278), .B2(registers_4__ap[12]), .ZN(n_1_0_889)); + SDFF_X1_LVT \registers_reg[22][12] (.D(registers[12]), .SE(dftIn), .SI( + registers_20__ap[12]), .CK(n_0_52), .Q(registers_22__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[21][12] (.D(registers[12]), .SE(dftIn), .SI( + registers_22__ap[12]), .CK(n_0_51), .Q(registers_21__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_933 (.A1(registers_22__ap[12]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[12]), .ZN(n_1_0_888)); + SDFF_X1_LVT \registers_reg[24][12] (.D(registers[12]), .SE(dftIn), .SI( + registers_30__ap[12]), .CK(n_0_54), .Q(registers_24__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[12][12] (.D(registers[12]), .SE(dftIn), .SI( + registers_15__ap[12]), .CK(n_0_42), .Q(registers_12__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_932 (.A1(registers_24__ap[12]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[12]), .ZN(n_1_0_887)); + NAND4_X1_LVT i_1_0_931 (.A1(n_1_0_890), .A2(n_1_0_889), .A3(n_1_0_888), + .A4(n_1_0_887), .ZN(n_1_0_886)); + SDFF_X1_LVT \registers_reg[13][12] (.D(registers[12]), .SE(dftIn), .SI( + registers_12__ap[12]), .CK(n_0_43), .Q(registers_13__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[25][12] (.D(registers[12]), .SE(dftIn), .SI( + registers_24__ap[12]), .CK(n_0_55), .Q(registers_25__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_930 (.A1(registers_13__ap[12]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[12]), .ZN(n_1_0_885)); + SDFF_X1_LVT \registers_reg[19][12] (.D(registers[12]), .SE(dftIn), .SI( + registers_21__ap[12]), .CK(n_0_49), .Q(registers_19__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[2][12] (.D(registers[12]), .SE(dftIn), .SI( + registers_25__ap[12]), .CK(n_0_32), .Q(registers_2__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_929 (.A1(registers_19__ap[12]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[12]), .ZN(n_1_0_884)); + SDFF_X1_LVT \registers_reg[7][12] (.D(registers[12]), .SE(dftIn), .SI( + registers_4__ap[12]), .CK(n_0_37), .Q(registers_7__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[14][12] (.D(registers[12]), .SE(dftIn), .SI( + registers_13__ap[12]), .CK(n_0_44), .Q(registers_14__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_928 (.A1(registers_7__ap[12]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[12]), .ZN(n_1_0_883)); + SDFF_X1_LVT \registers_reg[27][12] (.D(registers[12]), .SE(dftIn), .SI( + registers_2__ap[12]), .CK(n_0_57__0), .Q(registers_27__ap[12]), .QN()); + SDFF_X1_LVT \registers_reg[11][12] (.D(registers[12]), .SE(dftIn), .SI( + registers_14__ap[12]), .CK(n_0_41__0), .Q(registers_11__ap[12]), .QN()); + AOI22_X1_LVT i_1_0_927 (.A1(registers_27__ap[12]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[12]), .ZN(n_1_0_882)); + NAND4_X1_LVT i_1_0_926 (.A1(n_1_0_885), .A2(n_1_0_884), .A3(n_1_0_883), + .A4(n_1_0_882), .ZN(n_1_0_881)); + NOR3_X1_LVT i_1_0_925 (.A1(n_1_0_891), .A2(n_1_0_886), .A3(n_1_0_881), + .ZN(n_1_0_880)); + NAND4_X1_LVT i_1_0_924 (.A1(n_1_0_898), .A2(n_1_0_897), .A3(n_1_0_896), + .A4(n_1_0_880), .ZN(RRs1[12])); + AND2_X1_LVT i_0_0_11 (.A1(n_0_0_16), .A2(WRd[11]), .ZN(registers[11])); + SDFF_X1_LVT \registers_reg[28][11] (.D(registers[11]), .SE(dftIn), .SI( + registers_27__ap[12]), .CK(n_0_0__1), .Q(registers_28__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[17][11] (.D(registers[11]), .SE(dftIn), .SI( + registers_19__ap[12]), .CK(n_0_47), .Q(registers_17__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_923 (.A1(registers_28__ap[11]), .A2(n_1_0_1283), .B1( + n_1_0_1271), .B2(registers_17__ap[11]), .ZN(n_1_0_879)); + SDFF_X1_LVT \registers_reg[10][11] (.D(registers[11]), .SE(dftIn), .SI( + registers_11__ap[12]), .CK(n_0_40), .Q(registers_10__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[26][11] (.D(registers[11]), .SE(dftIn), .SI( + registers_28__ap[11]), .CK(n_0_56), .Q(registers_26__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[8][11] (.D(registers[11]), .SE(dftIn), .SI( + registers_7__ap[12]), .CK(n_0_38), .Q(registers_8__ap[11]), .QN()); + AOI222_X1_LVT i_1_0_922 (.A1(registers_10__ap[11]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[11]), .C1(registers_8__ap[11]), .C2( + n_1_0_1282), .ZN(n_1_0_878)); + SDFF_X1_LVT \registers_reg[9][11] (.D(registers[11]), .SE(dftIn), .SI( + registers_8__ap[11]), .CK(n_0_39), .Q(registers_9__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[29][11] (.D(registers[11]), .SE(dftIn), .SI( + registers_26__ap[11]), .CK(n_0_1), .Q(registers_29__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_921 (.A1(registers_9__ap[11]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[11]), .ZN(n_1_0_877)); + SDFF_X1_LVT \registers_reg[6][11] (.D(registers[11]), .SE(dftIn), .SI( + registers_9__ap[11]), .CK(n_0_36__0), .Q(registers_6__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[1][11] (.D(registers[11]), .SE(dftIn), .SI( + registers_17__ap[11]), .CK(n_0_0__0), .Q(registers_1__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_920 (.A1(registers_6__ap[11]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[11]), .ZN(n_1_0_876)); + SDFF_X1_LVT \registers_reg[5][11] (.D(registers[11]), .SE(dftIn), .SI( + registers_6__ap[11]), .CK(n_0_35), .Q(registers_5__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[3][11] (.D(registers[11]), .SE(dftIn), .SI( + registers_5__ap[11]), .CK(n_0_33), .Q(registers_3__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_919 (.A1(registers_5__ap[11]), .A2(n_1_0_1273), .B1( + n_1_0_1257), .B2(registers_3__ap[11]), .ZN(n_1_0_875)); + SDFF_X1_LVT \registers_reg[16][11] (.D(registers[11]), .SE(dftIn), .SI( + registers_10__ap[11]), .CK(n_0_46), .Q(registers_16__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[31][11] (.D(registers[11]), .SE(dftIn), .SI( + registers_3__ap[11]), .CK(n_0_3), .Q(registers_31__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_918 (.A1(registers_16__ap[11]), .A2(n_1_0_1267), .B1( + n_1_0_1266), .B2(registers_31__ap[11]), .ZN(n_1_0_874)); + SDFF_X1_LVT \registers_reg[15][11] (.D(registers[11]), .SE(dftIn), .SI( + registers_16__ap[11]), .CK(n_0_45), .Q(registers_15__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[23][11] (.D(registers[11]), .SE(dftIn), .SI( + registers_1__ap[11]), .CK(n_0_53), .Q(registers_23__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_917 (.A1(registers_15__ap[11]), .A2(n_1_0_1286), .B1( + n_1_0_1264), .B2(registers_23__ap[11]), .ZN(n_1_0_873)); + NAND4_X1_LVT i_1_0_916 (.A1(n_1_0_876), .A2(n_1_0_875), .A3(n_1_0_874), + .A4(n_1_0_873), .ZN(n_1_0_872)); + SDFF_X1_LVT \registers_reg[18][11] (.D(registers[11]), .SE(dftIn), .SI( + registers_23__ap[11]), .CK(n_0_48), .Q(registers_18__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[30][11] (.D(registers[11]), .SE(dftIn), .SI( + registers_29__ap[11]), .CK(n_0_2), .Q(registers_30__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_915 (.A1(registers_18__ap[11]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[11]), .ZN(n_1_0_871)); + SDFF_X1_LVT \registers_reg[20][11] (.D(registers[11]), .SE(dftIn), .SI( + registers_18__ap[11]), .CK(n_0_50), .Q(registers_20__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[4][11] (.D(registers[11]), .SE(dftIn), .SI( + registers_31__ap[11]), .CK(n_0_34), .Q(registers_4__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_914 (.A1(registers_20__ap[11]), .A2(n_1_0_1281), .B1( + n_1_0_1278), .B2(registers_4__ap[11]), .ZN(n_1_0_870)); + SDFF_X1_LVT \registers_reg[22][11] (.D(registers[11]), .SE(dftIn), .SI( + registers_20__ap[11]), .CK(n_0_52), .Q(registers_22__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[21][11] (.D(registers[11]), .SE(dftIn), .SI( + registers_22__ap[11]), .CK(n_0_51), .Q(registers_21__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_913 (.A1(registers_22__ap[11]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[11]), .ZN(n_1_0_869)); + SDFF_X1_LVT \registers_reg[24][11] (.D(registers[11]), .SE(dftIn), .SI( + registers_30__ap[11]), .CK(n_0_54), .Q(registers_24__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[12][11] (.D(registers[11]), .SE(dftIn), .SI( + registers_15__ap[11]), .CK(n_0_42), .Q(registers_12__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_912 (.A1(registers_24__ap[11]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[11]), .ZN(n_1_0_868)); + NAND4_X1_LVT i_1_0_911 (.A1(n_1_0_871), .A2(n_1_0_870), .A3(n_1_0_869), + .A4(n_1_0_868), .ZN(n_1_0_867)); + SDFF_X1_LVT \registers_reg[13][11] (.D(registers[11]), .SE(dftIn), .SI( + registers_12__ap[11]), .CK(n_0_43), .Q(registers_13__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[25][11] (.D(registers[11]), .SE(dftIn), .SI( + registers_24__ap[11]), .CK(n_0_55), .Q(registers_25__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_910 (.A1(registers_13__ap[11]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[11]), .ZN(n_1_0_866)); + SDFF_X1_LVT \registers_reg[19][11] (.D(registers[11]), .SE(dftIn), .SI( + registers_21__ap[11]), .CK(n_0_49), .Q(registers_19__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[2][11] (.D(registers[11]), .SE(dftIn), .SI( + registers_25__ap[11]), .CK(n_0_32), .Q(registers_2__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_909 (.A1(registers_19__ap[11]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[11]), .ZN(n_1_0_865)); + SDFF_X1_LVT \registers_reg[7][11] (.D(registers[11]), .SE(dftIn), .SI( + registers_4__ap[11]), .CK(n_0_37), .Q(registers_7__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[14][11] (.D(registers[11]), .SE(dftIn), .SI( + registers_13__ap[11]), .CK(n_0_44), .Q(registers_14__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_908 (.A1(registers_7__ap[11]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[11]), .ZN(n_1_0_864)); + SDFF_X1_LVT \registers_reg[27][11] (.D(registers[11]), .SE(dftIn), .SI( + registers_2__ap[11]), .CK(n_0_57__0), .Q(registers_27__ap[11]), .QN()); + SDFF_X1_LVT \registers_reg[11][11] (.D(registers[11]), .SE(dftIn), .SI( + registers_14__ap[11]), .CK(n_0_41__0), .Q(registers_11__ap[11]), .QN()); + AOI22_X1_LVT i_1_0_907 (.A1(registers_27__ap[11]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[11]), .ZN(n_1_0_863)); + NAND4_X1_LVT i_1_0_906 (.A1(n_1_0_866), .A2(n_1_0_865), .A3(n_1_0_864), + .A4(n_1_0_863), .ZN(n_1_0_862)); + NOR3_X1_LVT i_1_0_905 (.A1(n_1_0_872), .A2(n_1_0_867), .A3(n_1_0_862), + .ZN(n_1_0_861)); + NAND4_X1_LVT i_1_0_904 (.A1(n_1_0_879), .A2(n_1_0_878), .A3(n_1_0_877), + .A4(n_1_0_861), .ZN(RRs1[11])); + AND2_X1_LVT i_0_0_10 (.A1(n_0_0_16), .A2(WRd[10]), .ZN(registers[10])); + SDFF_X1_LVT \registers_reg[28][10] (.D(registers[10]), .SE(dftIn), .SI( + registers_27__ap[11]), .CK(n_0_0__1), .Q(registers_28__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[8][10] (.D(registers[10]), .SE(dftIn), .SI( + registers_7__ap[11]), .CK(n_0_38), .Q(registers_8__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_902 (.A1(registers_28__ap[10]), .A2(n_1_0_1283), .B1( + n_1_0_1282), .B2(registers_8__ap[10]), .ZN(n_1_0_859)); + SDFF_X1_LVT \registers_reg[31][10] (.D(registers[10]), .SE(dftIn), .SI( + registers_8__ap[10]), .CK(n_0_3), .Q(registers_31__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[7][10] (.D(registers[10]), .SE(dftIn), .SI( + registers_31__ap[10]), .CK(n_0_37), .Q(registers_7__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_903 (.A1(registers_31__ap[10]), .A2(n_1_0_1266), .B1( + n_1_0_1263), .B2(registers_7__ap[10]), .ZN(n_1_0_860)); + SDFF_X1_LVT \registers_reg[24][10] (.D(registers[10]), .SE(dftIn), .SI( + registers_28__ap[10]), .CK(n_0_54), .Q(registers_24__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[20][10] (.D(registers[10]), .SE(dftIn), .SI( + registers_19__ap[11]), .CK(n_0_50), .Q(registers_20__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_901 (.A1(registers_24__ap[10]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[10]), .ZN(n_1_0_858)); + SDFF_X1_LVT \registers_reg[4][10] (.D(registers[10]), .SE(dftIn), .SI( + registers_7__ap[10]), .CK(n_0_34), .Q(registers_4__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[23][10] (.D(registers[10]), .SE(dftIn), .SI( + registers_20__ap[10]), .CK(n_0_53), .Q(registers_23__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_900 (.A1(registers_4__ap[10]), .A2(n_1_0_1278), .B1( + n_1_0_1264), .B2(registers_23__ap[10]), .ZN(n_1_0_857)); + NAND3_X1_LVT i_1_0_899 (.A1(n_1_0_860), .A2(n_1_0_858), .A3(n_1_0_857), + .ZN(n_1_0_856)); + SDFF_X1_LVT \registers_reg[27][10] (.D(registers[10]), .SE(dftIn), .SI( + registers_24__ap[10]), .CK(n_0_57__0), .Q(registers_27__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[29][10] (.D(registers[10]), .SE(dftIn), .SI( + registers_27__ap[10]), .CK(n_0_1), .Q(registers_29__ap[10]), .QN()); + AOI221_X1_LVT i_1_0_898 (.A(n_1_0_856), .B1(n_1_0_1279), .B2( + registers_27__ap[10]), .C1(registers_29__ap[10]), .C2(n_1_0_1276), + .ZN(n_1_0_855)); + SDFF_X1_LVT \registers_reg[10][10] (.D(registers[10]), .SE(dftIn), .SI( + registers_11__ap[11]), .CK(n_0_40), .Q(registers_10__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[30][10] (.D(registers[10]), .SE(dftIn), .SI( + registers_29__ap[10]), .CK(n_0_2), .Q(registers_30__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[25][10] (.D(registers[10]), .SE(dftIn), .SI( + registers_30__ap[10]), .CK(n_0_55), .Q(registers_25__ap[10]), .QN()); + AOI222_X1_LVT i_1_0_897 (.A1(registers_10__ap[10]), .A2(n_1_0_1287), .B1( + n_1_0_1272), .B2(registers_30__ap[10]), .C1(n_1_0_1269), .C2( + registers_25__ap[10]), .ZN(n_1_0_854)); + NAND3_X1_LVT i_1_0_896 (.A1(n_1_0_859), .A2(n_1_0_855), .A3(n_1_0_854), + .ZN(n_1_0_853)); + SDFF_X1_LVT \registers_reg[21][10] (.D(registers[10]), .SE(dftIn), .SI( + registers_23__ap[10]), .CK(n_0_51), .Q(registers_21__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[13][10] (.D(registers[10]), .SE(dftIn), .SI( + registers_10__ap[10]), .CK(n_0_43), .Q(registers_13__ap[10]), .QN()); + AOI221_X1_LVT i_1_0_895 (.A(n_1_0_853), .B1(n_1_0_1259), .B2( + registers_21__ap[10]), .C1(registers_13__ap[10]), .C2(n_1_0_1277), + .ZN(n_1_0_852)); + SDFF_X1_LVT \registers_reg[18][10] (.D(registers[10]), .SE(dftIn), .SI( + registers_21__ap[10]), .CK(n_0_48), .Q(registers_18__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[26][10] (.D(registers[10]), .SE(dftIn), .SI( + registers_25__ap[10]), .CK(n_0_56), .Q(registers_26__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_894 (.A1(registers_18__ap[10]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[10]), .ZN(n_1_0_851)); + SDFF_X1_LVT \registers_reg[17][10] (.D(registers[10]), .SE(dftIn), .SI( + registers_18__ap[10]), .CK(n_0_47), .Q(registers_17__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[12][10] (.D(registers[10]), .SE(dftIn), .SI( + registers_13__ap[10]), .CK(n_0_42), .Q(registers_12__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_893 (.A1(registers_17__ap[10]), .A2(n_1_0_1271), .B1( + n_1_0_1260), .B2(registers_12__ap[10]), .ZN(n_1_0_850)); + SDFF_X1_LVT \registers_reg[15][10] (.D(registers[10]), .SE(dftIn), .SI( + registers_12__ap[10]), .CK(n_0_45), .Q(registers_15__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[5][10] (.D(registers[10]), .SE(dftIn), .SI( + registers_4__ap[10]), .CK(n_0_35), .Q(registers_5__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_892 (.A1(registers_15__ap[10]), .A2(n_1_0_1286), .B1( + n_1_0_1273), .B2(registers_5__ap[10]), .ZN(n_1_0_849)); + NAND3_X1_LVT i_1_0_891 (.A1(n_1_0_851), .A2(n_1_0_850), .A3(n_1_0_849), + .ZN(n_1_0_848)); + SDFF_X1_LVT \registers_reg[22][10] (.D(registers[10]), .SE(dftIn), .SI( + registers_17__ap[10]), .CK(n_0_52), .Q(registers_22__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[16][10] (.D(registers[10]), .SE(dftIn), .SI( + registers_15__ap[10]), .CK(n_0_46), .Q(registers_16__ap[10]), .QN()); + AOI221_X1_LVT i_1_0_890 (.A(n_1_0_848), .B1(n_1_0_1294), .B2( + registers_22__ap[10]), .C1(registers_16__ap[10]), .C2(n_1_0_1267), + .ZN(n_1_0_847)); + SDFF_X1_LVT \registers_reg[9][10] (.D(registers[10]), .SE(dftIn), .SI( + registers_5__ap[10]), .CK(n_0_39), .Q(registers_9__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[1][10] (.D(registers[10]), .SE(dftIn), .SI( + registers_22__ap[10]), .CK(n_0_0__0), .Q(registers_1__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_889 (.A1(registers_9__ap[10]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[10]), .ZN(n_1_0_846)); + SDFF_X1_LVT \registers_reg[6][10] (.D(registers[10]), .SE(dftIn), .SI( + registers_9__ap[10]), .CK(n_0_36__0), .Q(registers_6__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[14][10] (.D(registers[10]), .SE(dftIn), .SI( + registers_16__ap[10]), .CK(n_0_44), .Q(registers_14__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_888 (.A1(registers_6__ap[10]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[10]), .ZN(n_1_0_845)); + SDFF_X1_LVT \registers_reg[19][10] (.D(registers[10]), .SE(dftIn), .SI( + registers_1__ap[10]), .CK(n_0_49), .Q(registers_19__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[3][10] (.D(registers[10]), .SE(dftIn), .SI( + registers_6__ap[10]), .CK(n_0_33), .Q(registers_3__ap[10]), .QN()); + AOI22_X1_LVT i_1_0_887 (.A1(registers_19__ap[10]), .A2(n_1_0_1295), .B1( + n_1_0_1257), .B2(registers_3__ap[10]), .ZN(n_1_0_844)); + NAND3_X1_LVT i_1_0_886 (.A1(n_1_0_846), .A2(n_1_0_845), .A3(n_1_0_844), + .ZN(n_1_0_843)); + SDFF_X1_LVT \registers_reg[11][10] (.D(registers[10]), .SE(dftIn), .SI( + registers_14__ap[10]), .CK(n_0_41__0), .Q(registers_11__ap[10]), .QN()); + SDFF_X1_LVT \registers_reg[2][10] (.D(registers[10]), .SE(dftIn), .SI( + registers_26__ap[10]), .CK(n_0_32), .Q(registers_2__ap[10]), .QN()); + AOI221_X1_LVT i_1_0_885 (.A(n_1_0_843), .B1(n_1_0_1270), .B2( + registers_11__ap[10]), .C1(registers_2__ap[10]), .C2(n_1_0_1268), .ZN( + n_1_0_842)); + NAND3_X1_LVT i_1_0_884 (.A1(n_1_0_852), .A2(n_1_0_847), .A3(n_1_0_842), + .ZN(RRs1[10])); + AND2_X1_LVT i_0_0_9 (.A1(n_0_0_16), .A2(WRd[9]), .ZN(registers[9])); + SDFF_X1_LVT \registers_reg[13][9] (.D(registers[9]), .SE(dftIn), .SI( + registers_11__ap[10]), .CK(n_0_43), .Q(registers_13__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[21][9] (.D(registers[9]), .SE(dftIn), .SI( + registers_19__ap[10]), .CK(n_0_51), .Q(registers_21__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_880 (.A1(registers_13__ap[9]), .A2(n_1_0_1277), .B1( + n_1_0_1259), .B2(registers_21__ap[9]), .ZN(n_1_0_838)); + SDFF_X1_LVT \registers_reg[29][9] (.D(registers[9]), .SE(dftIn), .SI( + registers_2__ap[10]), .CK(n_0_1), .Q(registers_29__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[23][9] (.D(registers[9]), .SE(dftIn), .SI( + registers_21__ap[9]), .CK(n_0_53), .Q(registers_23__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_883 (.A1(registers_29__ap[9]), .A2(n_1_0_1276), .B1( + n_1_0_1264), .B2(registers_23__ap[9]), .ZN(n_1_0_841)); + SDFF_X1_LVT \registers_reg[24][9] (.D(registers[9]), .SE(dftIn), .SI( + registers_29__ap[9]), .CK(n_0_54), .Q(registers_24__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[20][9] (.D(registers[9]), .SE(dftIn), .SI( + registers_23__ap[9]), .CK(n_0_50), .Q(registers_20__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_879 (.A1(registers_24__ap[9]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[9]), .ZN(n_1_0_837)); + SDFF_X1_LVT \registers_reg[7][9] (.D(registers[9]), .SE(dftIn), .SI( + registers_3__ap[10]), .CK(n_0_37), .Q(registers_7__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[3][9] (.D(registers[9]), .SE(dftIn), .SI( + registers_7__ap[9]), .CK(n_0_33), .Q(registers_3__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_882 (.A1(registers_7__ap[9]), .A2(n_1_0_1263), .B1( + n_1_0_1257), .B2(registers_3__ap[9]), .ZN(n_1_0_840)); + INV_X1_LVT i_1_0_881 (.A(n_1_0_840), .ZN(n_1_0_839)); + SDFF_X1_LVT \registers_reg[31][9] (.D(registers[9]), .SE(dftIn), .SI( + registers_3__ap[9]), .CK(n_0_3), .Q(registers_31__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[4][9] (.D(registers[9]), .SE(dftIn), .SI( + registers_31__ap[9]), .CK(n_0_34), .Q(registers_4__ap[9]), .QN()); + AOI221_X1_LVT i_1_0_878 (.A(n_1_0_839), .B1(n_1_0_1266), .B2( + registers_31__ap[9]), .C1(registers_4__ap[9]), .C2(n_1_0_1278), .ZN( + n_1_0_836)); + SDFF_X1_LVT \registers_reg[10][9] (.D(registers[9]), .SE(dftIn), .SI( + registers_13__ap[9]), .CK(n_0_40), .Q(registers_10__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[26][9] (.D(registers[9]), .SE(dftIn), .SI( + registers_24__ap[9]), .CK(n_0_56), .Q(registers_26__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[25][9] (.D(registers[9]), .SE(dftIn), .SI( + registers_26__ap[9]), .CK(n_0_55), .Q(registers_25__ap[9]), .QN()); + AOI222_X1_LVT i_1_0_877 (.A1(registers_10__ap[9]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[9]), .C1(registers_25__ap[9]), .C2( + n_1_0_1269), .ZN(n_1_0_835)); + NAND4_X1_LVT i_1_0_876 (.A1(n_1_0_841), .A2(n_1_0_837), .A3(n_1_0_836), + .A4(n_1_0_835), .ZN(n_1_0_834)); + SDFF_X1_LVT \registers_reg[8][9] (.D(registers[9]), .SE(dftIn), .SI( + registers_4__ap[9]), .CK(n_0_38), .Q(registers_8__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[28][9] (.D(registers[9]), .SE(dftIn), .SI( + registers_25__ap[9]), .CK(n_0_0__1), .Q(registers_28__ap[9]), .QN()); + AOI221_X1_LVT i_1_0_875 (.A(n_1_0_834), .B1(n_1_0_1282), .B2( + registers_8__ap[9]), .C1(registers_28__ap[9]), .C2(n_1_0_1283), .ZN( + n_1_0_833)); + SDFF_X1_LVT \registers_reg[18][9] (.D(registers[9]), .SE(dftIn), .SI( + registers_20__ap[9]), .CK(n_0_48), .Q(registers_18__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[30][9] (.D(registers[9]), .SE(dftIn), .SI( + registers_28__ap[9]), .CK(n_0_2), .Q(registers_30__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_874 (.A1(registers_18__ap[9]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[9]), .ZN(n_1_0_832)); + SDFF_X1_LVT \registers_reg[17][9] (.D(registers[9]), .SE(dftIn), .SI( + registers_18__ap[9]), .CK(n_0_47), .Q(registers_17__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[12][9] (.D(registers[9]), .SE(dftIn), .SI( + registers_10__ap[9]), .CK(n_0_42), .Q(registers_12__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_873 (.A1(registers_17__ap[9]), .A2(n_1_0_1271), .B1( + n_1_0_1260), .B2(registers_12__ap[9]), .ZN(n_1_0_831)); + SDFF_X1_LVT \registers_reg[15][9] (.D(registers[9]), .SE(dftIn), .SI( + registers_12__ap[9]), .CK(n_0_45), .Q(registers_15__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[5][9] (.D(registers[9]), .SE(dftIn), .SI( + registers_8__ap[9]), .CK(n_0_35), .Q(registers_5__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_872 (.A1(registers_15__ap[9]), .A2(n_1_0_1286), .B1( + n_1_0_1273), .B2(registers_5__ap[9]), .ZN(n_1_0_830)); + NAND3_X1_LVT i_1_0_871 (.A1(n_1_0_832), .A2(n_1_0_831), .A3(n_1_0_830), + .ZN(n_1_0_829)); + SDFF_X1_LVT \registers_reg[22][9] (.D(registers[9]), .SE(dftIn), .SI( + registers_17__ap[9]), .CK(n_0_52), .Q(registers_22__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[16][9] (.D(registers[9]), .SE(dftIn), .SI( + registers_15__ap[9]), .CK(n_0_46), .Q(registers_16__ap[9]), .QN()); + AOI221_X1_LVT i_1_0_870 (.A(n_1_0_829), .B1(n_1_0_1294), .B2( + registers_22__ap[9]), .C1(registers_16__ap[9]), .C2(n_1_0_1267), .ZN( + n_1_0_828)); + SDFF_X1_LVT \registers_reg[9][9] (.D(registers[9]), .SE(dftIn), .SI( + registers_5__ap[9]), .CK(n_0_39), .Q(registers_9__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[1][9] (.D(registers[9]), .SE(dftIn), .SI( + registers_22__ap[9]), .CK(n_0_0__0), .Q(registers_1__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_869 (.A1(registers_9__ap[9]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[9]), .ZN(n_1_0_827)); + SDFF_X1_LVT \registers_reg[6][9] (.D(registers[9]), .SE(dftIn), .SI( + registers_9__ap[9]), .CK(n_0_36__0), .Q(registers_6__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[14][9] (.D(registers[9]), .SE(dftIn), .SI( + registers_16__ap[9]), .CK(n_0_44), .Q(registers_14__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_868 (.A1(registers_6__ap[9]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[9]), .ZN(n_1_0_826)); + SDFF_X1_LVT \registers_reg[19][9] (.D(registers[9]), .SE(dftIn), .SI( + registers_1__ap[9]), .CK(n_0_49), .Q(registers_19__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[2][9] (.D(registers[9]), .SE(dftIn), .SI( + registers_30__ap[9]), .CK(n_0_32), .Q(registers_2__ap[9]), .QN()); + AOI22_X1_LVT i_1_0_867 (.A1(registers_19__ap[9]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[9]), .ZN(n_1_0_825)); + NAND3_X1_LVT i_1_0_866 (.A1(n_1_0_827), .A2(n_1_0_826), .A3(n_1_0_825), + .ZN(n_1_0_824)); + SDFF_X1_LVT \registers_reg[11][9] (.D(registers[9]), .SE(dftIn), .SI( + registers_14__ap[9]), .CK(n_0_41__0), .Q(registers_11__ap[9]), .QN()); + SDFF_X1_LVT \registers_reg[27][9] (.D(registers[9]), .SE(dftIn), .SI( + registers_2__ap[9]), .CK(n_0_57__0), .Q(registers_27__ap[9]), .QN()); + AOI221_X1_LVT i_1_0_865 (.A(n_1_0_824), .B1(n_1_0_1270), .B2( + registers_11__ap[9]), .C1(registers_27__ap[9]), .C2(n_1_0_1279), .ZN( + n_1_0_823)); + NAND4_X1_LVT i_1_0_864 (.A1(n_1_0_838), .A2(n_1_0_833), .A3(n_1_0_828), + .A4(n_1_0_823), .ZN(RRs1[9])); + AND2_X1_LVT i_0_0_8 (.A1(n_0_0_16), .A2(WRd[8]), .ZN(registers[8])); + SDFF_X1_LVT \registers_reg[13][8] (.D(registers[8]), .SE(dftIn), .SI( + registers_11__ap[9]), .CK(n_0_43), .Q(registers_13__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[21][8] (.D(registers[8]), .SE(dftIn), .SI( + registers_19__ap[9]), .CK(n_0_51), .Q(registers_21__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_860 (.A1(registers_13__ap[8]), .A2(n_1_0_1277), .B1( + n_1_0_1259), .B2(registers_21__ap[8]), .ZN(n_1_0_819)); + SDFF_X1_LVT \registers_reg[29][8] (.D(registers[8]), .SE(dftIn), .SI( + registers_27__ap[9]), .CK(n_0_1), .Q(registers_29__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[23][8] (.D(registers[8]), .SE(dftIn), .SI( + registers_21__ap[8]), .CK(n_0_53), .Q(registers_23__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_863 (.A1(registers_29__ap[8]), .A2(n_1_0_1276), .B1( + n_1_0_1264), .B2(registers_23__ap[8]), .ZN(n_1_0_822)); + SDFF_X1_LVT \registers_reg[24][8] (.D(registers[8]), .SE(dftIn), .SI( + registers_29__ap[8]), .CK(n_0_54), .Q(registers_24__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[20][8] (.D(registers[8]), .SE(dftIn), .SI( + registers_23__ap[8]), .CK(n_0_50), .Q(registers_20__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_859 (.A1(registers_24__ap[8]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[8]), .ZN(n_1_0_818)); + SDFF_X1_LVT \registers_reg[7][8] (.D(registers[8]), .SE(dftIn), .SI( + registers_6__ap[9]), .CK(n_0_37), .Q(registers_7__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[3][8] (.D(registers[8]), .SE(dftIn), .SI( + registers_7__ap[8]), .CK(n_0_33), .Q(registers_3__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_862 (.A1(registers_7__ap[8]), .A2(n_1_0_1263), .B1( + n_1_0_1257), .B2(registers_3__ap[8]), .ZN(n_1_0_821)); + INV_X1_LVT i_1_0_861 (.A(n_1_0_821), .ZN(n_1_0_820)); + SDFF_X1_LVT \registers_reg[31][8] (.D(registers[8]), .SE(dftIn), .SI( + registers_3__ap[8]), .CK(n_0_3), .Q(registers_31__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[4][8] (.D(registers[8]), .SE(dftIn), .SI( + registers_31__ap[8]), .CK(n_0_34), .Q(registers_4__ap[8]), .QN()); + AOI221_X1_LVT i_1_0_858 (.A(n_1_0_820), .B1(n_1_0_1266), .B2( + registers_31__ap[8]), .C1(registers_4__ap[8]), .C2(n_1_0_1278), .ZN( + n_1_0_817)); + SDFF_X1_LVT \registers_reg[10][8] (.D(registers[8]), .SE(dftIn), .SI( + registers_13__ap[8]), .CK(n_0_40), .Q(registers_10__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[26][8] (.D(registers[8]), .SE(dftIn), .SI( + registers_24__ap[8]), .CK(n_0_56), .Q(registers_26__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[25][8] (.D(registers[8]), .SE(dftIn), .SI( + registers_26__ap[8]), .CK(n_0_55), .Q(registers_25__ap[8]), .QN()); + AOI222_X1_LVT i_1_0_857 (.A1(registers_10__ap[8]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[8]), .C1(registers_25__ap[8]), .C2( + n_1_0_1269), .ZN(n_1_0_816)); + NAND4_X1_LVT i_1_0_856 (.A1(n_1_0_822), .A2(n_1_0_818), .A3(n_1_0_817), + .A4(n_1_0_816), .ZN(n_1_0_815)); + SDFF_X1_LVT \registers_reg[8][8] (.D(registers[8]), .SE(dftIn), .SI( + registers_4__ap[8]), .CK(n_0_38), .Q(registers_8__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[28][8] (.D(registers[8]), .SE(dftIn), .SI( + registers_25__ap[8]), .CK(n_0_0__1), .Q(registers_28__ap[8]), .QN()); + AOI221_X1_LVT i_1_0_855 (.A(n_1_0_815), .B1(n_1_0_1282), .B2( + registers_8__ap[8]), .C1(registers_28__ap[8]), .C2(n_1_0_1283), .ZN( + n_1_0_814)); + SDFF_X1_LVT \registers_reg[18][8] (.D(registers[8]), .SE(dftIn), .SI( + registers_20__ap[8]), .CK(n_0_48), .Q(registers_18__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[30][8] (.D(registers[8]), .SE(dftIn), .SI( + registers_28__ap[8]), .CK(n_0_2), .Q(registers_30__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_854 (.A1(registers_18__ap[8]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[8]), .ZN(n_1_0_813)); + SDFF_X1_LVT \registers_reg[17][8] (.D(registers[8]), .SE(dftIn), .SI( + registers_18__ap[8]), .CK(n_0_47), .Q(registers_17__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[12][8] (.D(registers[8]), .SE(dftIn), .SI( + registers_10__ap[8]), .CK(n_0_42), .Q(registers_12__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_853 (.A1(registers_17__ap[8]), .A2(n_1_0_1271), .B1( + n_1_0_1260), .B2(registers_12__ap[8]), .ZN(n_1_0_812)); + SDFF_X1_LVT \registers_reg[15][8] (.D(registers[8]), .SE(dftIn), .SI( + registers_12__ap[8]), .CK(n_0_45), .Q(registers_15__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[5][8] (.D(registers[8]), .SE(dftIn), .SI( + registers_8__ap[8]), .CK(n_0_35), .Q(registers_5__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_852 (.A1(registers_15__ap[8]), .A2(n_1_0_1286), .B1( + n_1_0_1273), .B2(registers_5__ap[8]), .ZN(n_1_0_811)); + NAND3_X1_LVT i_1_0_851 (.A1(n_1_0_813), .A2(n_1_0_812), .A3(n_1_0_811), + .ZN(n_1_0_810)); + SDFF_X1_LVT \registers_reg[22][8] (.D(registers[8]), .SE(dftIn), .SI( + registers_17__ap[8]), .CK(n_0_52), .Q(registers_22__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[16][8] (.D(registers[8]), .SE(dftIn), .SI( + registers_15__ap[8]), .CK(n_0_46), .Q(registers_16__ap[8]), .QN()); + AOI221_X1_LVT i_1_0_850 (.A(n_1_0_810), .B1(n_1_0_1294), .B2( + registers_22__ap[8]), .C1(registers_16__ap[8]), .C2(n_1_0_1267), .ZN( + n_1_0_809)); + SDFF_X1_LVT \registers_reg[9][8] (.D(registers[8]), .SE(dftIn), .SI( + registers_5__ap[8]), .CK(n_0_39), .Q(registers_9__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[1][8] (.D(registers[8]), .SE(dftIn), .SI( + registers_22__ap[8]), .CK(n_0_0__0), .Q(registers_1__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_849 (.A1(registers_9__ap[8]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[8]), .ZN(n_1_0_808)); + SDFF_X1_LVT \registers_reg[6][8] (.D(registers[8]), .SE(dftIn), .SI( + registers_9__ap[8]), .CK(n_0_36__0), .Q(registers_6__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[14][8] (.D(registers[8]), .SE(dftIn), .SI( + registers_16__ap[8]), .CK(n_0_44), .Q(registers_14__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_848 (.A1(registers_6__ap[8]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[8]), .ZN(n_1_0_807)); + SDFF_X1_LVT \registers_reg[19][8] (.D(registers[8]), .SE(dftIn), .SI( + registers_1__ap[8]), .CK(n_0_49), .Q(registers_19__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[2][8] (.D(registers[8]), .SE(dftIn), .SI( + registers_30__ap[8]), .CK(n_0_32), .Q(registers_2__ap[8]), .QN()); + AOI22_X1_LVT i_1_0_847 (.A1(registers_19__ap[8]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[8]), .ZN(n_1_0_806)); + NAND3_X1_LVT i_1_0_846 (.A1(n_1_0_808), .A2(n_1_0_807), .A3(n_1_0_806), + .ZN(n_1_0_805)); + SDFF_X1_LVT \registers_reg[11][8] (.D(registers[8]), .SE(dftIn), .SI( + registers_14__ap[8]), .CK(n_0_41__0), .Q(registers_11__ap[8]), .QN()); + SDFF_X1_LVT \registers_reg[27][8] (.D(registers[8]), .SE(dftIn), .SI( + registers_2__ap[8]), .CK(n_0_57__0), .Q(registers_27__ap[8]), .QN()); + AOI221_X1_LVT i_1_0_845 (.A(n_1_0_805), .B1(n_1_0_1270), .B2( + registers_11__ap[8]), .C1(registers_27__ap[8]), .C2(n_1_0_1279), .ZN( + n_1_0_804)); + NAND4_X1_LVT i_1_0_844 (.A1(n_1_0_819), .A2(n_1_0_814), .A3(n_1_0_809), + .A4(n_1_0_804), .ZN(RRs1[8])); + AND2_X1_LVT i_0_0_7 (.A1(n_0_0_16), .A2(WRd[7]), .ZN(registers[7])); + SDFF_X1_LVT \registers_reg[13][7] (.D(registers[7]), .SE(dftIn), .SI( + registers_11__ap[8]), .CK(n_0_43), .Q(registers_13__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[21][7] (.D(registers[7]), .SE(dftIn), .SI( + registers_19__ap[8]), .CK(n_0_51), .Q(registers_21__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_843 (.A1(registers_13__ap[7]), .A2(n_1_0_1277), .B1( + n_1_0_1259), .B2(registers_21__ap[7]), .ZN(n_1_0_803)); + SDFF_X1_LVT \registers_reg[18][7] (.D(registers[7]), .SE(dftIn), .SI( + registers_21__ap[7]), .CK(n_0_48), .Q(registers_18__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[10][7] (.D(registers[7]), .SE(dftIn), .SI( + registers_13__ap[7]), .CK(n_0_40), .Q(registers_10__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[25][7] (.D(registers[7]), .SE(dftIn), .SI( + registers_27__ap[8]), .CK(n_0_55), .Q(registers_25__ap[7]), .QN()); + AOI222_X1_LVT i_1_0_842 (.A1(registers_18__ap[7]), .A2(n_1_0_1297), .B1( + n_1_0_1287), .B2(registers_10__ap[7]), .C1(registers_25__ap[7]), .C2( + n_1_0_1269), .ZN(n_1_0_802)); + SDFF_X1_LVT \registers_reg[28][7] (.D(registers[7]), .SE(dftIn), .SI( + registers_25__ap[7]), .CK(n_0_0__1), .Q(registers_28__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[8][7] (.D(registers[7]), .SE(dftIn), .SI( + registers_6__ap[8]), .CK(n_0_38), .Q(registers_8__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_841 (.A1(registers_28__ap[7]), .A2(n_1_0_1283), .B1( + n_1_0_1282), .B2(registers_8__ap[7]), .ZN(n_1_0_801)); + SDFF_X1_LVT \registers_reg[24][7] (.D(registers[7]), .SE(dftIn), .SI( + registers_28__ap[7]), .CK(n_0_54), .Q(registers_24__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[20][7] (.D(registers[7]), .SE(dftIn), .SI( + registers_18__ap[7]), .CK(n_0_50), .Q(registers_20__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_840 (.A1(registers_24__ap[7]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[7]), .ZN(n_1_0_800)); + SDFF_X1_LVT \registers_reg[31][7] (.D(registers[7]), .SE(dftIn), .SI( + registers_8__ap[7]), .CK(n_0_3), .Q(registers_31__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[7][7] (.D(registers[7]), .SE(dftIn), .SI( + registers_31__ap[7]), .CK(n_0_37), .Q(registers_7__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_839 (.A1(registers_31__ap[7]), .A2(n_1_0_1266), .B1( + n_1_0_1263), .B2(registers_7__ap[7]), .ZN(n_1_0_799)); + SDFF_X1_LVT \registers_reg[17][7] (.D(registers[7]), .SE(dftIn), .SI( + registers_20__ap[7]), .CK(n_0_47), .Q(registers_17__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[11][7] (.D(registers[7]), .SE(dftIn), .SI( + registers_10__ap[7]), .CK(n_0_41__0), .Q(registers_11__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_838 (.A1(registers_17__ap[7]), .A2(n_1_0_1271), .B1( + n_1_0_1270), .B2(registers_11__ap[7]), .ZN(n_1_0_798)); + SDFF_X1_LVT \registers_reg[27][7] (.D(registers[7]), .SE(dftIn), .SI( + registers_24__ap[7]), .CK(n_0_57__0), .Q(registers_27__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[29][7] (.D(registers[7]), .SE(dftIn), .SI( + registers_27__ap[7]), .CK(n_0_1), .Q(registers_29__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_837 (.A1(registers_27__ap[7]), .A2(n_1_0_1279), .B1( + n_1_0_1276), .B2(registers_29__ap[7]), .ZN(n_1_0_797)); + NAND4_X1_LVT i_1_0_836 (.A1(n_1_0_800), .A2(n_1_0_799), .A3(n_1_0_798), + .A4(n_1_0_797), .ZN(n_1_0_796)); + SDFF_X1_LVT \registers_reg[26][7] (.D(registers[7]), .SE(dftIn), .SI( + registers_29__ap[7]), .CK(n_0_56), .Q(registers_26__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[30][7] (.D(registers[7]), .SE(dftIn), .SI( + registers_26__ap[7]), .CK(n_0_2), .Q(registers_30__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_835 (.A1(registers_26__ap[7]), .A2(n_1_0_1285), .B1( + n_1_0_1272), .B2(registers_30__ap[7]), .ZN(n_1_0_795)); + SDFF_X1_LVT \registers_reg[4][7] (.D(registers[7]), .SE(dftIn), .SI( + registers_7__ap[7]), .CK(n_0_34), .Q(registers_4__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[12][7] (.D(registers[7]), .SE(dftIn), .SI( + registers_11__ap[7]), .CK(n_0_42), .Q(registers_12__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_834 (.A1(registers_4__ap[7]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[7]), .ZN(n_1_0_794)); + SDFF_X1_LVT \registers_reg[15][7] (.D(registers[7]), .SE(dftIn), .SI( + registers_12__ap[7]), .CK(n_0_45), .Q(registers_15__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[16][7] (.D(registers[7]), .SE(dftIn), .SI( + registers_15__ap[7]), .CK(n_0_46), .Q(registers_16__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_833 (.A1(registers_15__ap[7]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[7]), .ZN(n_1_0_793)); + SDFF_X1_LVT \registers_reg[22][7] (.D(registers[7]), .SE(dftIn), .SI( + registers_17__ap[7]), .CK(n_0_52), .Q(registers_22__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[5][7] (.D(registers[7]), .SE(dftIn), .SI( + registers_4__ap[7]), .CK(n_0_35), .Q(registers_5__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_832 (.A1(registers_22__ap[7]), .A2(n_1_0_1294), .B1( + n_1_0_1273), .B2(registers_5__ap[7]), .ZN(n_1_0_792)); + NAND4_X1_LVT i_1_0_831 (.A1(n_1_0_795), .A2(n_1_0_794), .A3(n_1_0_793), + .A4(n_1_0_792), .ZN(n_1_0_791)); + SDFF_X1_LVT \registers_reg[19][7] (.D(registers[7]), .SE(dftIn), .SI( + registers_22__ap[7]), .CK(n_0_49), .Q(registers_19__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[3][7] (.D(registers[7]), .SE(dftIn), .SI( + registers_5__ap[7]), .CK(n_0_33), .Q(registers_3__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_830 (.A1(registers_19__ap[7]), .A2(n_1_0_1295), .B1( + n_1_0_1257), .B2(registers_3__ap[7]), .ZN(n_1_0_790)); + SDFF_X1_LVT \registers_reg[9][7] (.D(registers[7]), .SE(dftIn), .SI( + registers_3__ap[7]), .CK(n_0_39), .Q(registers_9__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[1][7] (.D(registers[7]), .SE(dftIn), .SI( + registers_19__ap[7]), .CK(n_0_0__0), .Q(registers_1__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_829 (.A1(registers_9__ap[7]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[7]), .ZN(n_1_0_789)); + SDFF_X1_LVT \registers_reg[6][7] (.D(registers[7]), .SE(dftIn), .SI( + registers_9__ap[7]), .CK(n_0_36__0), .Q(registers_6__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[14][7] (.D(registers[7]), .SE(dftIn), .SI( + registers_16__ap[7]), .CK(n_0_44), .Q(registers_14__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_828 (.A1(registers_6__ap[7]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[7]), .ZN(n_1_0_788)); + SDFF_X1_LVT \registers_reg[2][7] (.D(registers[7]), .SE(dftIn), .SI( + registers_30__ap[7]), .CK(n_0_32), .Q(registers_2__ap[7]), .QN()); + SDFF_X1_LVT \registers_reg[23][7] (.D(registers[7]), .SE(dftIn), .SI( + registers_1__ap[7]), .CK(n_0_53), .Q(registers_23__ap[7]), .QN()); + AOI22_X1_LVT i_1_0_827 (.A1(registers_2__ap[7]), .A2(n_1_0_1268), .B1( + n_1_0_1264), .B2(registers_23__ap[7]), .ZN(n_1_0_787)); + NAND4_X1_LVT i_1_0_826 (.A1(n_1_0_790), .A2(n_1_0_789), .A3(n_1_0_788), + .A4(n_1_0_787), .ZN(n_1_0_786)); + NOR3_X1_LVT i_1_0_825 (.A1(n_1_0_796), .A2(n_1_0_791), .A3(n_1_0_786), + .ZN(n_1_0_785)); + NAND4_X1_LVT i_1_0_824 (.A1(n_1_0_803), .A2(n_1_0_802), .A3(n_1_0_801), + .A4(n_1_0_785), .ZN(RRs1[7])); + AND2_X1_LVT i_0_0_6 (.A1(n_0_0_16), .A2(WRd[6]), .ZN(registers[6])); + SDFF_X1_LVT \registers_reg[28][6] (.D(registers[6]), .SE(dftIn), .SI( + registers_2__ap[7]), .CK(n_0_0__1), .Q(registers_28__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[17][6] (.D(registers[6]), .SE(dftIn), .SI( + registers_23__ap[7]), .CK(n_0_47), .Q(registers_17__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_823 (.A1(registers_28__ap[6]), .A2(n_1_0_1283), .B1( + n_1_0_1271), .B2(registers_17__ap[6]), .ZN(n_1_0_784)); + SDFF_X1_LVT \registers_reg[18][6] (.D(registers[6]), .SE(dftIn), .SI( + registers_17__ap[6]), .CK(n_0_48), .Q(registers_18__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[10][6] (.D(registers[6]), .SE(dftIn), .SI( + registers_14__ap[7]), .CK(n_0_40), .Q(registers_10__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[8][6] (.D(registers[6]), .SE(dftIn), .SI( + registers_6__ap[7]), .CK(n_0_38), .Q(registers_8__ap[6]), .QN()); + AOI222_X1_LVT i_1_0_822 (.A1(registers_18__ap[6]), .A2(n_1_0_1297), .B1( + n_1_0_1287), .B2(registers_10__ap[6]), .C1(registers_8__ap[6]), .C2( + n_1_0_1282), .ZN(n_1_0_783)); + SDFF_X1_LVT \registers_reg[9][6] (.D(registers[6]), .SE(dftIn), .SI( + registers_8__ap[6]), .CK(n_0_39), .Q(registers_9__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[29][6] (.D(registers[6]), .SE(dftIn), .SI( + registers_28__ap[6]), .CK(n_0_1), .Q(registers_29__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_821 (.A1(registers_9__ap[6]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[6]), .ZN(n_1_0_782)); + SDFF_X1_LVT \registers_reg[6][6] (.D(registers[6]), .SE(dftIn), .SI( + registers_9__ap[6]), .CK(n_0_36__0), .Q(registers_6__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[1][6] (.D(registers[6]), .SE(dftIn), .SI( + registers_18__ap[6]), .CK(n_0_0__0), .Q(registers_1__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_820 (.A1(registers_6__ap[6]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[6]), .ZN(n_1_0_781)); + SDFF_X1_LVT \registers_reg[15][6] (.D(registers[6]), .SE(dftIn), .SI( + registers_10__ap[6]), .CK(n_0_45), .Q(registers_15__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[27][6] (.D(registers[6]), .SE(dftIn), .SI( + registers_29__ap[6]), .CK(n_0_57__0), .Q(registers_27__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_819 (.A1(registers_15__ap[6]), .A2(n_1_0_1286), .B1( + n_1_0_1279), .B2(registers_27__ap[6]), .ZN(n_1_0_780)); + SDFF_X1_LVT \registers_reg[11][6] (.D(registers[6]), .SE(dftIn), .SI( + registers_15__ap[6]), .CK(n_0_41__0), .Q(registers_11__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[16][6] (.D(registers[6]), .SE(dftIn), .SI( + registers_11__ap[6]), .CK(n_0_46), .Q(registers_16__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_818 (.A1(registers_11__ap[6]), .A2(n_1_0_1270), .B1( + n_1_0_1267), .B2(registers_16__ap[6]), .ZN(n_1_0_779)); + SDFF_X1_LVT \registers_reg[5][6] (.D(registers[6]), .SE(dftIn), .SI( + registers_6__ap[6]), .CK(n_0_35), .Q(registers_5__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[31][6] (.D(registers[6]), .SE(dftIn), .SI( + registers_5__ap[6]), .CK(n_0_3), .Q(registers_31__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_817 (.A1(registers_5__ap[6]), .A2(n_1_0_1273), .B1( + n_1_0_1266), .B2(registers_31__ap[6]), .ZN(n_1_0_778)); + NAND4_X1_LVT i_1_0_816 (.A1(n_1_0_781), .A2(n_1_0_780), .A3(n_1_0_779), + .A4(n_1_0_778), .ZN(n_1_0_777)); + SDFF_X1_LVT \registers_reg[26][6] (.D(registers[6]), .SE(dftIn), .SI( + registers_27__ap[6]), .CK(n_0_56), .Q(registers_26__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[30][6] (.D(registers[6]), .SE(dftIn), .SI( + registers_26__ap[6]), .CK(n_0_2), .Q(registers_30__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_815 (.A1(registers_26__ap[6]), .A2(n_1_0_1285), .B1( + n_1_0_1272), .B2(registers_30__ap[6]), .ZN(n_1_0_776)); + SDFF_X1_LVT \registers_reg[20][6] (.D(registers[6]), .SE(dftIn), .SI( + registers_1__ap[6]), .CK(n_0_50), .Q(registers_20__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[4][6] (.D(registers[6]), .SE(dftIn), .SI( + registers_31__ap[6]), .CK(n_0_34), .Q(registers_4__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_814 (.A1(registers_20__ap[6]), .A2(n_1_0_1281), .B1( + n_1_0_1278), .B2(registers_4__ap[6]), .ZN(n_1_0_775)); + SDFF_X1_LVT \registers_reg[22][6] (.D(registers[6]), .SE(dftIn), .SI( + registers_20__ap[6]), .CK(n_0_52), .Q(registers_22__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[21][6] (.D(registers[6]), .SE(dftIn), .SI( + registers_22__ap[6]), .CK(n_0_51), .Q(registers_21__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_813 (.A1(registers_22__ap[6]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[6]), .ZN(n_1_0_774)); + SDFF_X1_LVT \registers_reg[24][6] (.D(registers[6]), .SE(dftIn), .SI( + registers_30__ap[6]), .CK(n_0_54), .Q(registers_24__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[12][6] (.D(registers[6]), .SE(dftIn), .SI( + registers_16__ap[6]), .CK(n_0_42), .Q(registers_12__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_812 (.A1(registers_24__ap[6]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[6]), .ZN(n_1_0_773)); + NAND4_X1_LVT i_1_0_811 (.A1(n_1_0_776), .A2(n_1_0_775), .A3(n_1_0_774), + .A4(n_1_0_773), .ZN(n_1_0_772)); + SDFF_X1_LVT \registers_reg[13][6] (.D(registers[6]), .SE(dftIn), .SI( + registers_12__ap[6]), .CK(n_0_43), .Q(registers_13__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[25][6] (.D(registers[6]), .SE(dftIn), .SI( + registers_24__ap[6]), .CK(n_0_55), .Q(registers_25__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_810 (.A1(registers_13__ap[6]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[6]), .ZN(n_1_0_771)); + SDFF_X1_LVT \registers_reg[7][6] (.D(registers[6]), .SE(dftIn), .SI( + registers_4__ap[6]), .CK(n_0_37), .Q(registers_7__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[14][6] (.D(registers[6]), .SE(dftIn), .SI( + registers_13__ap[6]), .CK(n_0_44), .Q(registers_14__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_809 (.A1(registers_7__ap[6]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[6]), .ZN(n_1_0_770)); + SDFF_X1_LVT \registers_reg[19][6] (.D(registers[6]), .SE(dftIn), .SI( + registers_21__ap[6]), .CK(n_0_49), .Q(registers_19__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[3][6] (.D(registers[6]), .SE(dftIn), .SI( + registers_7__ap[6]), .CK(n_0_33), .Q(registers_3__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_808 (.A1(registers_19__ap[6]), .A2(n_1_0_1295), .B1( + n_1_0_1257), .B2(registers_3__ap[6]), .ZN(n_1_0_769)); + SDFF_X1_LVT \registers_reg[2][6] (.D(registers[6]), .SE(dftIn), .SI( + registers_25__ap[6]), .CK(n_0_32), .Q(registers_2__ap[6]), .QN()); + SDFF_X1_LVT \registers_reg[23][6] (.D(registers[6]), .SE(dftIn), .SI( + registers_19__ap[6]), .CK(n_0_53), .Q(registers_23__ap[6]), .QN()); + AOI22_X1_LVT i_1_0_807 (.A1(registers_2__ap[6]), .A2(n_1_0_1268), .B1( + n_1_0_1264), .B2(registers_23__ap[6]), .ZN(n_1_0_768)); + NAND4_X1_LVT i_1_0_806 (.A1(n_1_0_771), .A2(n_1_0_770), .A3(n_1_0_769), + .A4(n_1_0_768), .ZN(n_1_0_767)); + NOR3_X1_LVT i_1_0_805 (.A1(n_1_0_777), .A2(n_1_0_772), .A3(n_1_0_767), + .ZN(n_1_0_766)); + NAND4_X1_LVT i_1_0_804 (.A1(n_1_0_784), .A2(n_1_0_783), .A3(n_1_0_782), + .A4(n_1_0_766), .ZN(RRs1[6])); + AND2_X1_LVT i_0_0_5 (.A1(n_0_0_16), .A2(WRd[5]), .ZN(registers[5])); + SDFF_X1_LVT \registers_reg[28][5] (.D(registers[5]), .SE(dftIn), .SI( + registers_2__ap[6]), .CK(n_0_0__1), .Q(registers_28__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[4][5] (.D(registers[5]), .SE(dftIn), .SI( + registers_3__ap[6]), .CK(n_0_34), .Q(registers_4__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_803 (.A1(registers_28__ap[5]), .A2(n_1_0_1283), .B1( + n_1_0_1278), .B2(registers_4__ap[5]), .ZN(n_1_0_765)); + SDFF_X1_LVT \registers_reg[10][5] (.D(registers[5]), .SE(dftIn), .SI( + registers_14__ap[6]), .CK(n_0_40), .Q(registers_10__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[26][5] (.D(registers[5]), .SE(dftIn), .SI( + registers_28__ap[5]), .CK(n_0_56), .Q(registers_26__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[8][5] (.D(registers[5]), .SE(dftIn), .SI( + registers_4__ap[5]), .CK(n_0_38), .Q(registers_8__ap[5]), .QN()); + AOI222_X1_LVT i_1_0_802 (.A1(registers_10__ap[5]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[5]), .C1(registers_8__ap[5]), .C2( + n_1_0_1282), .ZN(n_1_0_764)); + SDFF_X1_LVT \registers_reg[9][5] (.D(registers[5]), .SE(dftIn), .SI( + registers_8__ap[5]), .CK(n_0_39), .Q(registers_9__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[29][5] (.D(registers[5]), .SE(dftIn), .SI( + registers_26__ap[5]), .CK(n_0_1), .Q(registers_29__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_801 (.A1(registers_9__ap[5]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[5]), .ZN(n_1_0_763)); + SDFF_X1_LVT \registers_reg[6][5] (.D(registers[5]), .SE(dftIn), .SI( + registers_9__ap[5]), .CK(n_0_36__0), .Q(registers_6__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[1][5] (.D(registers[5]), .SE(dftIn), .SI( + registers_23__ap[6]), .CK(n_0_0__0), .Q(registers_1__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_800 (.A1(registers_6__ap[5]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[5]), .ZN(n_1_0_762)); + SDFF_X1_LVT \registers_reg[16][5] (.D(registers[5]), .SE(dftIn), .SI( + registers_10__ap[5]), .CK(n_0_46), .Q(registers_16__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[3][5] (.D(registers[5]), .SE(dftIn), .SI( + registers_6__ap[5]), .CK(n_0_33), .Q(registers_3__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_799 (.A1(registers_16__ap[5]), .A2(n_1_0_1267), .B1( + n_1_0_1257), .B2(registers_3__ap[5]), .ZN(n_1_0_761)); + SDFF_X1_LVT \registers_reg[5][5] (.D(registers[5]), .SE(dftIn), .SI( + registers_3__ap[5]), .CK(n_0_35), .Q(registers_5__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[31][5] (.D(registers[5]), .SE(dftIn), .SI( + registers_5__ap[5]), .CK(n_0_3), .Q(registers_31__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_798 (.A1(registers_5__ap[5]), .A2(n_1_0_1273), .B1( + n_1_0_1266), .B2(registers_31__ap[5]), .ZN(n_1_0_760)); + SDFF_X1_LVT \registers_reg[15][5] (.D(registers[5]), .SE(dftIn), .SI( + registers_16__ap[5]), .CK(n_0_45), .Q(registers_15__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[23][5] (.D(registers[5]), .SE(dftIn), .SI( + registers_1__ap[5]), .CK(n_0_53), .Q(registers_23__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_797 (.A1(registers_15__ap[5]), .A2(n_1_0_1286), .B1( + n_1_0_1264), .B2(registers_23__ap[5]), .ZN(n_1_0_759)); + NAND4_X1_LVT i_1_0_796 (.A1(n_1_0_762), .A2(n_1_0_761), .A3(n_1_0_760), + .A4(n_1_0_759), .ZN(n_1_0_758)); + SDFF_X1_LVT \registers_reg[18][5] (.D(registers[5]), .SE(dftIn), .SI( + registers_23__ap[5]), .CK(n_0_48), .Q(registers_18__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[30][5] (.D(registers[5]), .SE(dftIn), .SI( + registers_29__ap[5]), .CK(n_0_2), .Q(registers_30__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_795 (.A1(registers_18__ap[5]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[5]), .ZN(n_1_0_757)); + SDFF_X1_LVT \registers_reg[24][5] (.D(registers[5]), .SE(dftIn), .SI( + registers_30__ap[5]), .CK(n_0_54), .Q(registers_24__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[12][5] (.D(registers[5]), .SE(dftIn), .SI( + registers_15__ap[5]), .CK(n_0_42), .Q(registers_12__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_794 (.A1(registers_24__ap[5]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[5]), .ZN(n_1_0_756)); + SDFF_X1_LVT \registers_reg[22][5] (.D(registers[5]), .SE(dftIn), .SI( + registers_18__ap[5]), .CK(n_0_52), .Q(registers_22__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[21][5] (.D(registers[5]), .SE(dftIn), .SI( + registers_22__ap[5]), .CK(n_0_51), .Q(registers_21__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_793 (.A1(registers_22__ap[5]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[5]), .ZN(n_1_0_755)); + SDFF_X1_LVT \registers_reg[20][5] (.D(registers[5]), .SE(dftIn), .SI( + registers_21__ap[5]), .CK(n_0_50), .Q(registers_20__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[17][5] (.D(registers[5]), .SE(dftIn), .SI( + registers_20__ap[5]), .CK(n_0_47), .Q(registers_17__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_792 (.A1(registers_20__ap[5]), .A2(n_1_0_1281), .B1( + n_1_0_1271), .B2(registers_17__ap[5]), .ZN(n_1_0_754)); + NAND4_X1_LVT i_1_0_791 (.A1(n_1_0_757), .A2(n_1_0_756), .A3(n_1_0_755), + .A4(n_1_0_754), .ZN(n_1_0_753)); + SDFF_X1_LVT \registers_reg[13][5] (.D(registers[5]), .SE(dftIn), .SI( + registers_12__ap[5]), .CK(n_0_43), .Q(registers_13__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[25][5] (.D(registers[5]), .SE(dftIn), .SI( + registers_24__ap[5]), .CK(n_0_55), .Q(registers_25__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_790 (.A1(registers_13__ap[5]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[5]), .ZN(n_1_0_752)); + SDFF_X1_LVT \registers_reg[19][5] (.D(registers[5]), .SE(dftIn), .SI( + registers_17__ap[5]), .CK(n_0_49), .Q(registers_19__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[2][5] (.D(registers[5]), .SE(dftIn), .SI( + registers_25__ap[5]), .CK(n_0_32), .Q(registers_2__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_789 (.A1(registers_19__ap[5]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[5]), .ZN(n_1_0_751)); + SDFF_X1_LVT \registers_reg[7][5] (.D(registers[5]), .SE(dftIn), .SI( + registers_31__ap[5]), .CK(n_0_37), .Q(registers_7__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[14][5] (.D(registers[5]), .SE(dftIn), .SI( + registers_13__ap[5]), .CK(n_0_44), .Q(registers_14__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_788 (.A1(registers_7__ap[5]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[5]), .ZN(n_1_0_750)); + SDFF_X1_LVT \registers_reg[27][5] (.D(registers[5]), .SE(dftIn), .SI( + registers_2__ap[5]), .CK(n_0_57__0), .Q(registers_27__ap[5]), .QN()); + SDFF_X1_LVT \registers_reg[11][5] (.D(registers[5]), .SE(dftIn), .SI( + registers_14__ap[5]), .CK(n_0_41__0), .Q(registers_11__ap[5]), .QN()); + AOI22_X1_LVT i_1_0_787 (.A1(registers_27__ap[5]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[5]), .ZN(n_1_0_749)); + NAND4_X1_LVT i_1_0_786 (.A1(n_1_0_752), .A2(n_1_0_751), .A3(n_1_0_750), + .A4(n_1_0_749), .ZN(n_1_0_748)); + NOR3_X1_LVT i_1_0_785 (.A1(n_1_0_758), .A2(n_1_0_753), .A3(n_1_0_748), + .ZN(n_1_0_747)); + NAND4_X1_LVT i_1_0_784 (.A1(n_1_0_765), .A2(n_1_0_764), .A3(n_1_0_763), + .A4(n_1_0_747), .ZN(RRs1[5])); + AND2_X1_LVT i_0_0_4 (.A1(n_0_0_16), .A2(WRd[4]), .ZN(registers[4])); + SDFF_X1_LVT \registers_reg[10][4] (.D(registers[4]), .SE(dftIn), .SI( + registers_11__ap[5]), .CK(n_0_40), .Q(registers_10__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[21][4] (.D(registers[4]), .SE(dftIn), .SI( + registers_19__ap[5]), .CK(n_0_51), .Q(registers_21__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_783 (.A1(registers_10__ap[4]), .A2(n_1_0_1287), .B1( + n_1_0_1259), .B2(registers_21__ap[4]), .ZN(n_1_0_746)); + SDFF_X1_LVT \registers_reg[9][4] (.D(registers[4]), .SE(dftIn), .SI( + registers_7__ap[5]), .CK(n_0_39), .Q(registers_9__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[1][4] (.D(registers[4]), .SE(dftIn), .SI( + registers_21__ap[4]), .CK(n_0_0__0), .Q(registers_1__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_778 (.A1(registers_9__ap[4]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[4]), .ZN(n_1_0_741)); + SDFF_X1_LVT \registers_reg[18][4] (.D(registers[4]), .SE(dftIn), .SI( + registers_1__ap[4]), .CK(n_0_48), .Q(registers_18__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[8][4] (.D(registers[4]), .SE(dftIn), .SI( + registers_9__ap[4]), .CK(n_0_38), .Q(registers_8__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_777 (.A1(registers_18__ap[4]), .A2(n_1_0_1297), .B1( + n_1_0_1282), .B2(registers_8__ap[4]), .ZN(n_1_0_740)); + NAND3_X1_LVT i_1_0_775 (.A1(n_1_0_746), .A2(n_1_0_741), .A3(n_1_0_740), + .ZN(n_1_0_738)); + SDFF_X1_LVT \registers_reg[22][4] (.D(registers[4]), .SE(dftIn), .SI( + registers_18__ap[4]), .CK(n_0_52), .Q(registers_22__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[23][4] (.D(registers[4]), .SE(dftIn), .SI( + registers_22__ap[4]), .CK(n_0_53), .Q(registers_23__ap[4]), .QN()); + AOI221_X1_LVT i_1_0_774 (.A(n_1_0_738), .B1(n_1_0_1294), .B2( + registers_22__ap[4]), .C1(registers_23__ap[4]), .C2(n_1_0_1264), .ZN( + n_1_0_737)); + SDFF_X1_LVT \registers_reg[28][4] (.D(registers[4]), .SE(dftIn), .SI( + registers_27__ap[5]), .CK(n_0_0__1), .Q(registers_28__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[20][4] (.D(registers[4]), .SE(dftIn), .SI( + registers_23__ap[4]), .CK(n_0_50), .Q(registers_20__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_782 (.A1(registers_28__ap[4]), .A2(n_1_0_1283), .B1( + n_1_0_1281), .B2(registers_20__ap[4]), .ZN(n_1_0_745)); + SDFF_X1_LVT \registers_reg[19][4] (.D(registers[4]), .SE(dftIn), .SI( + registers_20__ap[4]), .CK(n_0_49), .Q(registers_19__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[13][4] (.D(registers[4]), .SE(dftIn), .SI( + registers_10__ap[4]), .CK(n_0_43), .Q(registers_13__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_780 (.A1(registers_19__ap[4]), .A2(n_1_0_1295), .B1( + n_1_0_1277), .B2(registers_13__ap[4]), .ZN(n_1_0_743)); + SDFF_X1_LVT \registers_reg[26][4] (.D(registers[4]), .SE(dftIn), .SI( + registers_28__ap[4]), .CK(n_0_56), .Q(registers_26__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[3][4] (.D(registers[4]), .SE(dftIn), .SI( + registers_8__ap[4]), .CK(n_0_33), .Q(registers_3__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_776 (.A1(registers_26__ap[4]), .A2(n_1_0_1285), .B1( + n_1_0_1257), .B2(registers_3__ap[4]), .ZN(n_1_0_739)); + NAND3_X1_LVT i_1_0_773 (.A1(n_1_0_745), .A2(n_1_0_743), .A3(n_1_0_739), + .ZN(n_1_0_736)); + SDFF_X1_LVT \registers_reg[30][4] (.D(registers[4]), .SE(dftIn), .SI( + registers_26__ap[4]), .CK(n_0_2), .Q(registers_30__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[31][4] (.D(registers[4]), .SE(dftIn), .SI( + registers_3__ap[4]), .CK(n_0_3), .Q(registers_31__ap[4]), .QN()); + AOI221_X1_LVT i_1_0_772 (.A(n_1_0_736), .B1(n_1_0_1272), .B2( + registers_30__ap[4]), .C1(registers_31__ap[4]), .C2(n_1_0_1266), .ZN( + n_1_0_735)); + SDFF_X1_LVT \registers_reg[24][4] (.D(registers[4]), .SE(dftIn), .SI( + registers_30__ap[4]), .CK(n_0_54), .Q(registers_24__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[12][4] (.D(registers[4]), .SE(dftIn), .SI( + registers_13__ap[4]), .CK(n_0_42), .Q(registers_12__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_781 (.A1(registers_24__ap[4]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[4]), .ZN(n_1_0_744)); + SDFF_X1_LVT \registers_reg[27][4] (.D(registers[4]), .SE(dftIn), .SI( + registers_24__ap[4]), .CK(n_0_57__0), .Q(registers_27__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[11][4] (.D(registers[4]), .SE(dftIn), .SI( + registers_12__ap[4]), .CK(n_0_41__0), .Q(registers_11__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_779 (.A1(registers_27__ap[4]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[4]), .ZN(n_1_0_742)); + SDFF_X1_LVT \registers_reg[17][4] (.D(registers[4]), .SE(dftIn), .SI( + registers_19__ap[4]), .CK(n_0_47), .Q(registers_17__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[7][4] (.D(registers[4]), .SE(dftIn), .SI( + registers_31__ap[4]), .CK(n_0_37), .Q(registers_7__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[14][4] (.D(registers[4]), .SE(dftIn), .SI( + registers_11__ap[4]), .CK(n_0_44), .Q(registers_14__ap[4]), .QN()); + AOI222_X1_LVT i_1_0_771 (.A1(registers_17__ap[4]), .A2(n_1_0_1271), .B1( + n_1_0_1263), .B2(registers_7__ap[4]), .C1(n_1_0_1258), .C2( + registers_14__ap[4]), .ZN(n_1_0_734)); + SDFF_X1_LVT \registers_reg[15][4] (.D(registers[4]), .SE(dftIn), .SI( + registers_14__ap[4]), .CK(n_0_45), .Q(registers_15__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[16][4] (.D(registers[4]), .SE(dftIn), .SI( + registers_15__ap[4]), .CK(n_0_46), .Q(registers_16__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_770 (.A1(registers_15__ap[4]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[4]), .ZN(n_1_0_733)); + SDFF_X1_LVT \registers_reg[4][4] (.D(registers[4]), .SE(dftIn), .SI( + registers_7__ap[4]), .CK(n_0_34), .Q(registers_4__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[25][4] (.D(registers[4]), .SE(dftIn), .SI( + registers_27__ap[4]), .CK(n_0_55), .Q(registers_25__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_769 (.A1(registers_4__ap[4]), .A2(n_1_0_1278), .B1( + n_1_0_1269), .B2(registers_25__ap[4]), .ZN(n_1_0_732)); + SDFF_X1_LVT \registers_reg[29][4] (.D(registers[4]), .SE(dftIn), .SI( + registers_25__ap[4]), .CK(n_0_1), .Q(registers_29__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[2][4] (.D(registers[4]), .SE(dftIn), .SI( + registers_29__ap[4]), .CK(n_0_32), .Q(registers_2__ap[4]), .QN()); + AOI22_X1_LVT i_1_0_768 (.A1(registers_29__ap[4]), .A2(n_1_0_1276), .B1( + n_1_0_1268), .B2(registers_2__ap[4]), .ZN(n_1_0_731)); + NAND3_X1_LVT i_1_0_767 (.A1(n_1_0_733), .A2(n_1_0_732), .A3(n_1_0_731), + .ZN(n_1_0_730)); + SDFF_X1_LVT \registers_reg[6][4] (.D(registers[4]), .SE(dftIn), .SI( + registers_4__ap[4]), .CK(n_0_36__0), .Q(registers_6__ap[4]), .QN()); + SDFF_X1_LVT \registers_reg[5][4] (.D(registers[4]), .SE(dftIn), .SI( + registers_6__ap[4]), .CK(n_0_35), .Q(registers_5__ap[4]), .QN()); + AOI221_X1_LVT i_1_0_766 (.A(n_1_0_730), .B1(n_1_0_1300), .B2( + registers_6__ap[4]), .C1(registers_5__ap[4]), .C2(n_1_0_1273), .ZN( + n_1_0_729)); + AND4_X1_LVT i_1_0_765 (.A1(n_1_0_744), .A2(n_1_0_742), .A3(n_1_0_734), + .A4(n_1_0_729), .ZN(n_1_0_728)); + NAND3_X1_LVT i_1_0_764 (.A1(n_1_0_737), .A2(n_1_0_735), .A3(n_1_0_728), + .ZN(RRs1[4])); + AND2_X1_LVT i_0_0_3 (.A1(n_0_0_16), .A2(WRd[3]), .ZN(registers[3])); + SDFF_X1_LVT \registers_reg[28][3] (.D(registers[3]), .SE(dftIn), .SI( + registers_2__ap[4]), .CK(n_0_0__1), .Q(registers_28__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[17][3] (.D(registers[3]), .SE(dftIn), .SI( + registers_17__ap[4]), .CK(n_0_47), .Q(registers_17__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_763 (.A1(registers_28__ap[3]), .A2(n_1_0_1283), .B1( + n_1_0_1271), .B2(registers_17__ap[3]), .ZN(n_1_0_727)); + SDFF_X1_LVT \registers_reg[10][3] (.D(registers[3]), .SE(dftIn), .SI( + registers_16__ap[4]), .CK(n_0_40), .Q(registers_10__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[26][3] (.D(registers[3]), .SE(dftIn), .SI( + registers_28__ap[3]), .CK(n_0_56), .Q(registers_26__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[8][3] (.D(registers[3]), .SE(dftIn), .SI( + registers_5__ap[4]), .CK(n_0_38), .Q(registers_8__ap[3]), .QN()); + AOI222_X1_LVT i_1_0_762 (.A1(registers_10__ap[3]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[3]), .C1(registers_8__ap[3]), .C2( + n_1_0_1282), .ZN(n_1_0_726)); + SDFF_X1_LVT \registers_reg[9][3] (.D(registers[3]), .SE(dftIn), .SI( + registers_8__ap[3]), .CK(n_0_39), .Q(registers_9__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[29][3] (.D(registers[3]), .SE(dftIn), .SI( + registers_26__ap[3]), .CK(n_0_1), .Q(registers_29__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_761 (.A1(registers_9__ap[3]), .A2(n_1_0_1291), .B1( + n_1_0_1276), .B2(registers_29__ap[3]), .ZN(n_1_0_725)); + SDFF_X1_LVT \registers_reg[6][3] (.D(registers[3]), .SE(dftIn), .SI( + registers_9__ap[3]), .CK(n_0_36__0), .Q(registers_6__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[1][3] (.D(registers[3]), .SE(dftIn), .SI( + registers_17__ap[3]), .CK(n_0_0__0), .Q(registers_1__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_760 (.A1(registers_6__ap[3]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[3]), .ZN(n_1_0_724)); + SDFF_X1_LVT \registers_reg[16][3] (.D(registers[3]), .SE(dftIn), .SI( + registers_10__ap[3]), .CK(n_0_46), .Q(registers_16__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[3][3] (.D(registers[3]), .SE(dftIn), .SI( + registers_6__ap[3]), .CK(n_0_33), .Q(registers_3__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_759 (.A1(registers_16__ap[3]), .A2(n_1_0_1267), .B1( + n_1_0_1257), .B2(registers_3__ap[3]), .ZN(n_1_0_723)); + SDFF_X1_LVT \registers_reg[5][3] (.D(registers[3]), .SE(dftIn), .SI( + registers_3__ap[3]), .CK(n_0_35), .Q(registers_5__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[31][3] (.D(registers[3]), .SE(dftIn), .SI( + registers_5__ap[3]), .CK(n_0_3), .Q(registers_31__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_758 (.A1(registers_5__ap[3]), .A2(n_1_0_1273), .B1( + n_1_0_1266), .B2(registers_31__ap[3]), .ZN(n_1_0_722)); + SDFF_X1_LVT \registers_reg[15][3] (.D(registers[3]), .SE(dftIn), .SI( + registers_16__ap[3]), .CK(n_0_45), .Q(registers_15__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[23][3] (.D(registers[3]), .SE(dftIn), .SI( + registers_1__ap[3]), .CK(n_0_53), .Q(registers_23__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_757 (.A1(registers_15__ap[3]), .A2(n_1_0_1286), .B1( + n_1_0_1264), .B2(registers_23__ap[3]), .ZN(n_1_0_721)); + NAND4_X1_LVT i_1_0_756 (.A1(n_1_0_724), .A2(n_1_0_723), .A3(n_1_0_722), + .A4(n_1_0_721), .ZN(n_1_0_720)); + SDFF_X1_LVT \registers_reg[18][3] (.D(registers[3]), .SE(dftIn), .SI( + registers_23__ap[3]), .CK(n_0_48), .Q(registers_18__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[30][3] (.D(registers[3]), .SE(dftIn), .SI( + registers_29__ap[3]), .CK(n_0_2), .Q(registers_30__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_755 (.A1(registers_18__ap[3]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[3]), .ZN(n_1_0_719)); + SDFF_X1_LVT \registers_reg[20][3] (.D(registers[3]), .SE(dftIn), .SI( + registers_18__ap[3]), .CK(n_0_50), .Q(registers_20__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[4][3] (.D(registers[3]), .SE(dftIn), .SI( + registers_31__ap[3]), .CK(n_0_34), .Q(registers_4__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_754 (.A1(registers_20__ap[3]), .A2(n_1_0_1281), .B1( + n_1_0_1278), .B2(registers_4__ap[3]), .ZN(n_1_0_718)); + SDFF_X1_LVT \registers_reg[22][3] (.D(registers[3]), .SE(dftIn), .SI( + registers_20__ap[3]), .CK(n_0_52), .Q(registers_22__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[21][3] (.D(registers[3]), .SE(dftIn), .SI( + registers_22__ap[3]), .CK(n_0_51), .Q(registers_21__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_753 (.A1(registers_22__ap[3]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[3]), .ZN(n_1_0_717)); + SDFF_X1_LVT \registers_reg[24][3] (.D(registers[3]), .SE(dftIn), .SI( + registers_30__ap[3]), .CK(n_0_54), .Q(registers_24__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[12][3] (.D(registers[3]), .SE(dftIn), .SI( + registers_15__ap[3]), .CK(n_0_42), .Q(registers_12__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_752 (.A1(registers_24__ap[3]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[3]), .ZN(n_1_0_716)); + NAND4_X1_LVT i_1_0_751 (.A1(n_1_0_719), .A2(n_1_0_718), .A3(n_1_0_717), + .A4(n_1_0_716), .ZN(n_1_0_715)); + SDFF_X1_LVT \registers_reg[13][3] (.D(registers[3]), .SE(dftIn), .SI( + registers_12__ap[3]), .CK(n_0_43), .Q(registers_13__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[25][3] (.D(registers[3]), .SE(dftIn), .SI( + registers_24__ap[3]), .CK(n_0_55), .Q(registers_25__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_750 (.A1(registers_13__ap[3]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[3]), .ZN(n_1_0_714)); + SDFF_X1_LVT \registers_reg[19][3] (.D(registers[3]), .SE(dftIn), .SI( + registers_21__ap[3]), .CK(n_0_49), .Q(registers_19__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[2][3] (.D(registers[3]), .SE(dftIn), .SI( + registers_25__ap[3]), .CK(n_0_32), .Q(registers_2__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_749 (.A1(registers_19__ap[3]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[3]), .ZN(n_1_0_713)); + SDFF_X1_LVT \registers_reg[7][3] (.D(registers[3]), .SE(dftIn), .SI( + registers_4__ap[3]), .CK(n_0_37), .Q(registers_7__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[14][3] (.D(registers[3]), .SE(dftIn), .SI( + registers_13__ap[3]), .CK(n_0_44), .Q(registers_14__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_748 (.A1(registers_7__ap[3]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[3]), .ZN(n_1_0_712)); + SDFF_X1_LVT \registers_reg[27][3] (.D(registers[3]), .SE(dftIn), .SI( + registers_2__ap[3]), .CK(n_0_57__0), .Q(registers_27__ap[3]), .QN()); + SDFF_X1_LVT \registers_reg[11][3] (.D(registers[3]), .SE(dftIn), .SI( + registers_14__ap[3]), .CK(n_0_41__0), .Q(registers_11__ap[3]), .QN()); + AOI22_X1_LVT i_1_0_747 (.A1(registers_27__ap[3]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[3]), .ZN(n_1_0_711)); + NAND4_X1_LVT i_1_0_746 (.A1(n_1_0_714), .A2(n_1_0_713), .A3(n_1_0_712), + .A4(n_1_0_711), .ZN(n_1_0_710)); + NOR3_X1_LVT i_1_0_745 (.A1(n_1_0_720), .A2(n_1_0_715), .A3(n_1_0_710), + .ZN(n_1_0_709)); + NAND4_X1_LVT i_1_0_744 (.A1(n_1_0_727), .A2(n_1_0_726), .A3(n_1_0_725), + .A4(n_1_0_709), .ZN(RRs1[3])); + AND2_X1_LVT i_0_0_2 (.A1(n_0_0_16), .A2(WRd[2]), .ZN(registers[2])); + SDFF_X1_LVT \registers_reg[28][2] (.D(registers[2]), .SE(dftIn), .SI( + registers_27__ap[3]), .CK(n_0_0__1), .Q(registers_28__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[4][2] (.D(registers[2]), .SE(dftIn), .SI( + registers_7__ap[3]), .CK(n_0_34), .Q(registers_4__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_740 (.A1(registers_28__ap[2]), .A2(n_1_0_1283), .B1( + n_1_0_1278), .B2(registers_4__ap[2]), .ZN(n_1_0_705)); + SDFF_X1_LVT \registers_reg[16][2] (.D(registers[2]), .SE(dftIn), .SI( + registers_11__ap[3]), .CK(n_0_46), .Q(registers_16__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[31][2] (.D(registers[2]), .SE(dftIn), .SI( + registers_4__ap[2]), .CK(n_0_3), .Q(registers_31__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_743 (.A1(registers_16__ap[2]), .A2(n_1_0_1267), .B1( + n_1_0_1266), .B2(registers_31__ap[2]), .ZN(n_1_0_708)); + SDFF_X1_LVT \registers_reg[6][2] (.D(registers[2]), .SE(dftIn), .SI( + registers_31__ap[2]), .CK(n_0_36__0), .Q(registers_6__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[1][2] (.D(registers[2]), .SE(dftIn), .SI( + registers_19__ap[3]), .CK(n_0_0__0), .Q(registers_1__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_739 (.A1(registers_6__ap[2]), .A2(n_1_0_1300), .B1( + n_1_0_1274), .B2(registers_1__ap[2]), .ZN(n_1_0_704)); + SDFF_X1_LVT \registers_reg[15][2] (.D(registers[2]), .SE(dftIn), .SI( + registers_16__ap[2]), .CK(n_0_45), .Q(registers_15__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[27][2] (.D(registers[2]), .SE(dftIn), .SI( + registers_28__ap[2]), .CK(n_0_57__0), .Q(registers_27__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_742 (.A1(registers_15__ap[2]), .A2(n_1_0_1286), .B1( + n_1_0_1279), .B2(registers_27__ap[2]), .ZN(n_1_0_707)); + INV_X1_LVT i_1_0_741 (.A(n_1_0_707), .ZN(n_1_0_706)); + SDFF_X1_LVT \registers_reg[11][2] (.D(registers[2]), .SE(dftIn), .SI( + registers_15__ap[2]), .CK(n_0_41__0), .Q(registers_11__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[5][2] (.D(registers[2]), .SE(dftIn), .SI( + registers_6__ap[2]), .CK(n_0_35), .Q(registers_5__ap[2]), .QN()); + AOI221_X1_LVT i_1_0_738 (.A(n_1_0_706), .B1(n_1_0_1270), .B2( + registers_11__ap[2]), .C1(registers_5__ap[2]), .C2(n_1_0_1273), .ZN( + n_1_0_703)); + SDFF_X1_LVT \registers_reg[10][2] (.D(registers[2]), .SE(dftIn), .SI( + registers_11__ap[2]), .CK(n_0_40), .Q(registers_10__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[30][2] (.D(registers[2]), .SE(dftIn), .SI( + registers_27__ap[2]), .CK(n_0_2), .Q(registers_30__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[8][2] (.D(registers[2]), .SE(dftIn), .SI( + registers_5__ap[2]), .CK(n_0_38), .Q(registers_8__ap[2]), .QN()); + AOI222_X1_LVT i_1_0_737 (.A1(registers_10__ap[2]), .A2(n_1_0_1287), .B1( + n_1_0_1272), .B2(registers_30__ap[2]), .C1(n_1_0_1282), .C2( + registers_8__ap[2]), .ZN(n_1_0_702)); + NAND4_X1_LVT i_1_0_736 (.A1(n_1_0_708), .A2(n_1_0_704), .A3(n_1_0_703), + .A4(n_1_0_702), .ZN(n_1_0_701)); + SDFF_X1_LVT \registers_reg[9][2] (.D(registers[2]), .SE(dftIn), .SI( + registers_8__ap[2]), .CK(n_0_39), .Q(registers_9__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[29][2] (.D(registers[2]), .SE(dftIn), .SI( + registers_30__ap[2]), .CK(n_0_1), .Q(registers_29__ap[2]), .QN()); + AOI221_X1_LVT i_1_0_735 (.A(n_1_0_701), .B1(n_1_0_1291), .B2( + registers_9__ap[2]), .C1(registers_29__ap[2]), .C2(n_1_0_1276), .ZN( + n_1_0_700)); + SDFF_X1_LVT \registers_reg[18][2] (.D(registers[2]), .SE(dftIn), .SI( + registers_1__ap[2]), .CK(n_0_48), .Q(registers_18__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[26][2] (.D(registers[2]), .SE(dftIn), .SI( + registers_29__ap[2]), .CK(n_0_56), .Q(registers_26__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_734 (.A1(registers_18__ap[2]), .A2(n_1_0_1297), .B1( + n_1_0_1285), .B2(registers_26__ap[2]), .ZN(n_1_0_699)); + SDFF_X1_LVT \registers_reg[24][2] (.D(registers[2]), .SE(dftIn), .SI( + registers_26__ap[2]), .CK(n_0_54), .Q(registers_24__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[12][2] (.D(registers[2]), .SE(dftIn), .SI( + registers_10__ap[2]), .CK(n_0_42), .Q(registers_12__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_733 (.A1(registers_24__ap[2]), .A2(n_1_0_1289), .B1( + n_1_0_1260), .B2(registers_12__ap[2]), .ZN(n_1_0_698)); + SDFF_X1_LVT \registers_reg[22][2] (.D(registers[2]), .SE(dftIn), .SI( + registers_18__ap[2]), .CK(n_0_52), .Q(registers_22__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[21][2] (.D(registers[2]), .SE(dftIn), .SI( + registers_22__ap[2]), .CK(n_0_51), .Q(registers_21__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_732 (.A1(registers_22__ap[2]), .A2(n_1_0_1294), .B1( + n_1_0_1259), .B2(registers_21__ap[2]), .ZN(n_1_0_697)); + NAND3_X1_LVT i_1_0_731 (.A1(n_1_0_699), .A2(n_1_0_698), .A3(n_1_0_697), + .ZN(n_1_0_696)); + SDFF_X1_LVT \registers_reg[17][2] (.D(registers[2]), .SE(dftIn), .SI( + registers_21__ap[2]), .CK(n_0_47), .Q(registers_17__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[20][2] (.D(registers[2]), .SE(dftIn), .SI( + registers_17__ap[2]), .CK(n_0_50), .Q(registers_20__ap[2]), .QN()); + AOI221_X1_LVT i_1_0_730 (.A(n_1_0_696), .B1(n_1_0_1271), .B2( + registers_17__ap[2]), .C1(registers_20__ap[2]), .C2(n_1_0_1281), .ZN( + n_1_0_695)); + SDFF_X1_LVT \registers_reg[13][2] (.D(registers[2]), .SE(dftIn), .SI( + registers_12__ap[2]), .CK(n_0_43), .Q(registers_13__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[25][2] (.D(registers[2]), .SE(dftIn), .SI( + registers_24__ap[2]), .CK(n_0_55), .Q(registers_25__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_729 (.A1(registers_13__ap[2]), .A2(n_1_0_1277), .B1( + n_1_0_1269), .B2(registers_25__ap[2]), .ZN(n_1_0_694)); + SDFF_X1_LVT \registers_reg[7][2] (.D(registers[2]), .SE(dftIn), .SI( + registers_9__ap[2]), .CK(n_0_37), .Q(registers_7__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[14][2] (.D(registers[2]), .SE(dftIn), .SI( + registers_13__ap[2]), .CK(n_0_44), .Q(registers_14__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_728 (.A1(registers_7__ap[2]), .A2(n_1_0_1263), .B1( + n_1_0_1258), .B2(registers_14__ap[2]), .ZN(n_1_0_693)); + SDFF_X1_LVT \registers_reg[19][2] (.D(registers[2]), .SE(dftIn), .SI( + registers_20__ap[2]), .CK(n_0_49), .Q(registers_19__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[3][2] (.D(registers[2]), .SE(dftIn), .SI( + registers_7__ap[2]), .CK(n_0_33), .Q(registers_3__ap[2]), .QN()); + AOI22_X1_LVT i_1_0_727 (.A1(registers_19__ap[2]), .A2(n_1_0_1295), .B1( + n_1_0_1257), .B2(registers_3__ap[2]), .ZN(n_1_0_692)); + NAND3_X1_LVT i_1_0_726 (.A1(n_1_0_694), .A2(n_1_0_693), .A3(n_1_0_692), + .ZN(n_1_0_691)); + SDFF_X1_LVT \registers_reg[23][2] (.D(registers[2]), .SE(dftIn), .SI( + registers_19__ap[2]), .CK(n_0_53), .Q(registers_23__ap[2]), .QN()); + SDFF_X1_LVT \registers_reg[2][2] (.D(registers[2]), .SE(dftIn), .SI( + registers_25__ap[2]), .CK(n_0_32), .Q(registers_2__ap[2]), .QN()); + AOI221_X1_LVT i_1_0_725 (.A(n_1_0_691), .B1(n_1_0_1264), .B2( + registers_23__ap[2]), .C1(registers_2__ap[2]), .C2(n_1_0_1268), .ZN( + n_1_0_690)); + NAND4_X1_LVT i_1_0_724 (.A1(n_1_0_705), .A2(n_1_0_700), .A3(n_1_0_695), + .A4(n_1_0_690), .ZN(RRs1[2])); + AND2_X1_LVT i_0_0_1 (.A1(n_0_0_16), .A2(WRd[1]), .ZN(registers[1])); + SDFF_X1_LVT \registers_reg[13][1] (.D(registers[1]), .SE(dftIn), .SI( + registers_14__ap[2]), .CK(n_0_43), .Q(registers_13__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[21][1] (.D(registers[1]), .SE(dftIn), .SI( + registers_23__ap[2]), .CK(n_0_51), .Q(registers_21__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_720 (.A1(registers_13__ap[1]), .A2(n_1_0_1277), .B1( + n_1_0_1259), .B2(registers_21__ap[1]), .ZN(n_1_0_686)); + SDFF_X1_LVT \registers_reg[29][1] (.D(registers[1]), .SE(dftIn), .SI( + registers_2__ap[2]), .CK(n_0_1), .Q(registers_29__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[23][1] (.D(registers[1]), .SE(dftIn), .SI( + registers_21__ap[1]), .CK(n_0_53), .Q(registers_23__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_723 (.A1(registers_29__ap[1]), .A2(n_1_0_1276), .B1( + n_1_0_1264), .B2(registers_23__ap[1]), .ZN(n_1_0_689)); + SDFF_X1_LVT \registers_reg[24][1] (.D(registers[1]), .SE(dftIn), .SI( + registers_29__ap[1]), .CK(n_0_54), .Q(registers_24__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[20][1] (.D(registers[1]), .SE(dftIn), .SI( + registers_23__ap[1]), .CK(n_0_50), .Q(registers_20__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_719 (.A1(registers_24__ap[1]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[1]), .ZN(n_1_0_685)); + SDFF_X1_LVT \registers_reg[7][1] (.D(registers[1]), .SE(dftIn), .SI( + registers_3__ap[2]), .CK(n_0_37), .Q(registers_7__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[3][1] (.D(registers[1]), .SE(dftIn), .SI( + registers_7__ap[1]), .CK(n_0_33), .Q(registers_3__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_722 (.A1(registers_7__ap[1]), .A2(n_1_0_1263), .B1( + n_1_0_1257), .B2(registers_3__ap[1]), .ZN(n_1_0_688)); + INV_X1_LVT i_1_0_721 (.A(n_1_0_688), .ZN(n_1_0_687)); + SDFF_X1_LVT \registers_reg[31][1] (.D(registers[1]), .SE(dftIn), .SI( + registers_3__ap[1]), .CK(n_0_3), .Q(registers_31__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[4][1] (.D(registers[1]), .SE(dftIn), .SI( + registers_31__ap[1]), .CK(n_0_34), .Q(registers_4__ap[1]), .QN()); + AOI221_X1_LVT i_1_0_718 (.A(n_1_0_687), .B1(n_1_0_1266), .B2( + registers_31__ap[1]), .C1(registers_4__ap[1]), .C2(n_1_0_1278), .ZN( + n_1_0_684)); + SDFF_X1_LVT \registers_reg[10][1] (.D(registers[1]), .SE(dftIn), .SI( + registers_13__ap[1]), .CK(n_0_40), .Q(registers_10__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[26][1] (.D(registers[1]), .SE(dftIn), .SI( + registers_24__ap[1]), .CK(n_0_56), .Q(registers_26__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[25][1] (.D(registers[1]), .SE(dftIn), .SI( + registers_26__ap[1]), .CK(n_0_55), .Q(registers_25__ap[1]), .QN()); + AOI222_X1_LVT i_1_0_717 (.A1(registers_10__ap[1]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[1]), .C1(registers_25__ap[1]), .C2( + n_1_0_1269), .ZN(n_1_0_683)); + NAND4_X1_LVT i_1_0_716 (.A1(n_1_0_689), .A2(n_1_0_685), .A3(n_1_0_684), + .A4(n_1_0_683), .ZN(n_1_0_682)); + SDFF_X1_LVT \registers_reg[8][1] (.D(registers[1]), .SE(dftIn), .SI( + registers_4__ap[1]), .CK(n_0_38), .Q(registers_8__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[28][1] (.D(registers[1]), .SE(dftIn), .SI( + registers_25__ap[1]), .CK(n_0_0__1), .Q(registers_28__ap[1]), .QN()); + AOI221_X1_LVT i_1_0_715 (.A(n_1_0_682), .B1(n_1_0_1282), .B2( + registers_8__ap[1]), .C1(registers_28__ap[1]), .C2(n_1_0_1283), .ZN( + n_1_0_681)); + SDFF_X1_LVT \registers_reg[18][1] (.D(registers[1]), .SE(dftIn), .SI( + registers_20__ap[1]), .CK(n_0_48), .Q(registers_18__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[30][1] (.D(registers[1]), .SE(dftIn), .SI( + registers_28__ap[1]), .CK(n_0_2), .Q(registers_30__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_714 (.A1(registers_18__ap[1]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[1]), .ZN(n_1_0_680)); + SDFF_X1_LVT \registers_reg[17][1] (.D(registers[1]), .SE(dftIn), .SI( + registers_18__ap[1]), .CK(n_0_47), .Q(registers_17__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[12][1] (.D(registers[1]), .SE(dftIn), .SI( + registers_10__ap[1]), .CK(n_0_42), .Q(registers_12__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_713 (.A1(registers_17__ap[1]), .A2(n_1_0_1271), .B1( + n_1_0_1260), .B2(registers_12__ap[1]), .ZN(n_1_0_679)); + SDFF_X1_LVT \registers_reg[15][1] (.D(registers[1]), .SE(dftIn), .SI( + registers_12__ap[1]), .CK(n_0_45), .Q(registers_15__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[5][1] (.D(registers[1]), .SE(dftIn), .SI( + registers_8__ap[1]), .CK(n_0_35), .Q(registers_5__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_712 (.A1(registers_15__ap[1]), .A2(n_1_0_1286), .B1( + n_1_0_1273), .B2(registers_5__ap[1]), .ZN(n_1_0_678)); + NAND3_X1_LVT i_1_0_711 (.A1(n_1_0_680), .A2(n_1_0_679), .A3(n_1_0_678), + .ZN(n_1_0_677)); + SDFF_X1_LVT \registers_reg[22][1] (.D(registers[1]), .SE(dftIn), .SI( + registers_17__ap[1]), .CK(n_0_52), .Q(registers_22__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[16][1] (.D(registers[1]), .SE(dftIn), .SI( + registers_15__ap[1]), .CK(n_0_46), .Q(registers_16__ap[1]), .QN()); + AOI221_X1_LVT i_1_0_710 (.A(n_1_0_677), .B1(n_1_0_1294), .B2( + registers_22__ap[1]), .C1(registers_16__ap[1]), .C2(n_1_0_1267), .ZN( + n_1_0_676)); + SDFF_X1_LVT \registers_reg[9][1] (.D(registers[1]), .SE(dftIn), .SI( + registers_5__ap[1]), .CK(n_0_39), .Q(registers_9__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[1][1] (.D(registers[1]), .SE(dftIn), .SI( + registers_22__ap[1]), .CK(n_0_0__0), .Q(registers_1__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_709 (.A1(registers_9__ap[1]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[1]), .ZN(n_1_0_675)); + SDFF_X1_LVT \registers_reg[6][1] (.D(registers[1]), .SE(dftIn), .SI( + registers_9__ap[1]), .CK(n_0_36__0), .Q(registers_6__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[14][1] (.D(registers[1]), .SE(dftIn), .SI( + registers_16__ap[1]), .CK(n_0_44), .Q(registers_14__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_708 (.A1(registers_6__ap[1]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[1]), .ZN(n_1_0_674)); + SDFF_X1_LVT \registers_reg[19][1] (.D(registers[1]), .SE(dftIn), .SI( + registers_1__ap[1]), .CK(n_0_49), .Q(registers_19__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[2][1] (.D(registers[1]), .SE(dftIn), .SI( + registers_30__ap[1]), .CK(n_0_32), .Q(registers_2__ap[1]), .QN()); + AOI22_X1_LVT i_1_0_707 (.A1(registers_19__ap[1]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[1]), .ZN(n_1_0_673)); + NAND3_X1_LVT i_1_0_706 (.A1(n_1_0_675), .A2(n_1_0_674), .A3(n_1_0_673), + .ZN(n_1_0_672)); + SDFF_X1_LVT \registers_reg[11][1] (.D(registers[1]), .SE(dftIn), .SI( + registers_14__ap[1]), .CK(n_0_41__0), .Q(registers_11__ap[1]), .QN()); + SDFF_X1_LVT \registers_reg[27][1] (.D(registers[1]), .SE(dftIn), .SI( + registers_2__ap[1]), .CK(n_0_57__0), .Q(registers_27__ap[1]), .QN()); + AOI221_X1_LVT i_1_0_705 (.A(n_1_0_672), .B1(n_1_0_1270), .B2( + registers_11__ap[1]), .C1(registers_27__ap[1]), .C2(n_1_0_1279), .ZN( + n_1_0_671)); + NAND4_X1_LVT i_1_0_704 (.A1(n_1_0_686), .A2(n_1_0_681), .A3(n_1_0_676), + .A4(n_1_0_671), .ZN(RRs1[1])); + AND2_X1_LVT i_0_0_0 (.A1(n_0_0_16), .A2(WRd[0]), .ZN(registers[0])); + SDFF_X1_LVT \registers_reg[13][0] (.D(registers[0]), .SE(dftIn), .SI( + registers_11__ap[1]), .CK(n_0_43), .Q(registers_13__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[21][0] (.D(registers[0]), .SE(dftIn), .SI( + registers_19__ap[1]), .CK(n_0_51), .Q(registers_21__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_703 (.A1(registers_13__ap[0]), .A2(n_1_0_1277), .B1( + n_1_0_1259), .B2(registers_21__ap[0]), .ZN(n_1_0_670)); + SDFF_X1_LVT \registers_reg[10][0] (.D(registers[0]), .SE(dftIn), .SI( + registers_13__ap[0]), .CK(n_0_40), .Q(registers_10__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[26][0] (.D(registers[0]), .SE(dftIn), .SI( + registers_27__ap[1]), .CK(n_0_56), .Q(registers_26__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[25][0] (.D(registers[0]), .SE(dftIn), .SI( + registers_26__ap[0]), .CK(n_0_55), .Q(registers_25__ap[0]), .QN()); + AOI222_X1_LVT i_1_0_702 (.A1(registers_10__ap[0]), .A2(n_1_0_1287), .B1( + n_1_0_1285), .B2(registers_26__ap[0]), .C1(registers_25__ap[0]), .C2( + n_1_0_1269), .ZN(n_1_0_669)); + SDFF_X1_LVT \registers_reg[28][0] (.D(registers[0]), .SE(dftIn), .SI( + registers_25__ap[0]), .CK(n_0_0__1), .Q(registers_28__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[8][0] (.D(registers[0]), .SE(dftIn), .SI( + registers_6__ap[1]), .CK(n_0_38), .Q(registers_8__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_701 (.A1(registers_28__ap[0]), .A2(n_1_0_1283), .B1( + n_1_0_1282), .B2(registers_8__ap[0]), .ZN(n_1_0_668)); + SDFF_X1_LVT \registers_reg[24][0] (.D(registers[0]), .SE(dftIn), .SI( + registers_28__ap[0]), .CK(n_0_54), .Q(registers_24__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[20][0] (.D(registers[0]), .SE(dftIn), .SI( + registers_21__ap[0]), .CK(n_0_50), .Q(registers_20__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_700 (.A1(registers_24__ap[0]), .A2(n_1_0_1289), .B1( + n_1_0_1281), .B2(registers_20__ap[0]), .ZN(n_1_0_667)); + SDFF_X1_LVT \registers_reg[7][0] (.D(registers[0]), .SE(dftIn), .SI( + registers_8__ap[0]), .CK(n_0_37), .Q(registers_7__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[3][0] (.D(registers[0]), .SE(dftIn), .SI( + registers_7__ap[0]), .CK(n_0_33), .Q(registers_3__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_699 (.A1(registers_7__ap[0]), .A2(n_1_0_1263), .B1( + n_1_0_1257), .B2(registers_3__ap[0]), .ZN(n_1_0_666)); + SDFF_X1_LVT \registers_reg[17][0] (.D(registers[0]), .SE(dftIn), .SI( + registers_20__ap[0]), .CK(n_0_47), .Q(registers_17__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[31][0] (.D(registers[0]), .SE(dftIn), .SI( + registers_3__ap[0]), .CK(n_0_3), .Q(registers_31__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_698 (.A1(registers_17__ap[0]), .A2(n_1_0_1271), .B1( + n_1_0_1266), .B2(registers_31__ap[0]), .ZN(n_1_0_665)); + SDFF_X1_LVT \registers_reg[29][0] (.D(registers[0]), .SE(dftIn), .SI( + registers_24__ap[0]), .CK(n_0_1), .Q(registers_29__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[23][0] (.D(registers[0]), .SE(dftIn), .SI( + registers_17__ap[0]), .CK(n_0_53), .Q(registers_23__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_697 (.A1(registers_29__ap[0]), .A2(n_1_0_1276), .B1( + n_1_0_1264), .B2(registers_23__ap[0]), .ZN(n_1_0_664)); + NAND4_X1_LVT i_1_0_696 (.A1(n_1_0_667), .A2(n_1_0_666), .A3(n_1_0_665), + .A4(n_1_0_664), .ZN(n_1_0_663)); + SDFF_X1_LVT \registers_reg[18][0] (.D(registers[0]), .SE(dftIn), .SI( + registers_23__ap[0]), .CK(n_0_48), .Q(registers_18__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[30][0] (.D(registers[0]), .SE(dftIn), .SI( + registers_29__ap[0]), .CK(n_0_2), .Q(registers_30__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_695 (.A1(registers_18__ap[0]), .A2(n_1_0_1297), .B1( + n_1_0_1272), .B2(registers_30__ap[0]), .ZN(n_1_0_662)); + SDFF_X1_LVT \registers_reg[4][0] (.D(registers[0]), .SE(dftIn), .SI( + registers_31__ap[0]), .CK(n_0_34), .Q(registers_4__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[12][0] (.D(registers[0]), .SE(dftIn), .SI( + registers_10__ap[0]), .CK(n_0_42), .Q(registers_12__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_694 (.A1(registers_4__ap[0]), .A2(n_1_0_1278), .B1( + n_1_0_1260), .B2(registers_12__ap[0]), .ZN(n_1_0_661)); + SDFF_X1_LVT \registers_reg[15][0] (.D(registers[0]), .SE(dftIn), .SI( + registers_12__ap[0]), .CK(n_0_45), .Q(registers_15__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[16][0] (.D(registers[0]), .SE(dftIn), .SI( + registers_15__ap[0]), .CK(n_0_46), .Q(registers_16__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_693 (.A1(registers_15__ap[0]), .A2(n_1_0_1286), .B1( + n_1_0_1267), .B2(registers_16__ap[0]), .ZN(n_1_0_660)); + SDFF_X1_LVT \registers_reg[22][0] (.D(registers[0]), .SE(dftIn), .SI( + registers_18__ap[0]), .CK(n_0_52), .Q(registers_22__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[5][0] (.D(registers[0]), .SE(dftIn), .SI( + registers_4__ap[0]), .CK(n_0_35), .Q(registers_5__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_692 (.A1(registers_22__ap[0]), .A2(n_1_0_1294), .B1( + n_1_0_1273), .B2(registers_5__ap[0]), .ZN(n_1_0_659)); + NAND4_X1_LVT i_1_0_691 (.A1(n_1_0_662), .A2(n_1_0_661), .A3(n_1_0_660), + .A4(n_1_0_659), .ZN(n_1_0_658)); + SDFF_X1_LVT \registers_reg[19][0] (.D(registers[0]), .SE(dftIn), .SI( + registers_22__ap[0]), .CK(n_0_49), .Q(registers_19__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[2][0] (.D(registers[0]), .SE(dftIn), .SI( + registers_30__ap[0]), .CK(n_0_32), .Q(registers_2__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_690 (.A1(registers_19__ap[0]), .A2(n_1_0_1295), .B1( + n_1_0_1268), .B2(registers_2__ap[0]), .ZN(n_1_0_657)); + SDFF_X1_LVT \registers_reg[9][0] (.D(registers[0]), .SE(dftIn), .SI( + registers_5__ap[0]), .CK(n_0_39), .Q(registers_9__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[1][0] (.D(registers[0]), .SE(dftIn), .SI( + registers_19__ap[0]), .CK(n_0_0__0), .Q(registers_1__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_689 (.A1(registers_9__ap[0]), .A2(n_1_0_1291), .B1( + n_1_0_1274), .B2(registers_1__ap[0]), .ZN(n_1_0_656)); + SDFF_X1_LVT \registers_reg[6][0] (.D(registers[0]), .SE(dftIn), .SI( + registers_9__ap[0]), .CK(n_0_36__0), .Q(registers_6__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[14][0] (.D(registers[0]), .SE(dftIn), .SI( + registers_16__ap[0]), .CK(n_0_44), .Q(registers_14__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_688 (.A1(registers_6__ap[0]), .A2(n_1_0_1300), .B1( + n_1_0_1258), .B2(registers_14__ap[0]), .ZN(n_1_0_655)); + SDFF_X1_LVT \registers_reg[27][0] (.D(registers[0]), .SE(dftIn), .SI( + registers_2__ap[0]), .CK(n_0_57__0), .Q(registers_27__ap[0]), .QN()); + SDFF_X1_LVT \registers_reg[11][0] (.D(registers[0]), .SE(dftIn), .SI( + registers_14__ap[0]), .CK(n_0_41__0), .Q(registers_11__ap[0]), .QN()); + AOI22_X1_LVT i_1_0_687 (.A1(registers_27__ap[0]), .A2(n_1_0_1279), .B1( + n_1_0_1270), .B2(registers_11__ap[0]), .ZN(n_1_0_654)); + NAND4_X1_LVT i_1_0_686 (.A1(n_1_0_657), .A2(n_1_0_656), .A3(n_1_0_655), + .A4(n_1_0_654), .ZN(n_1_0_653)); + NOR3_X1_LVT i_1_0_685 (.A1(n_1_0_663), .A2(n_1_0_658), .A3(n_1_0_653), + .ZN(n_1_0_652)); + NAND4_X1_LVT i_1_0_684 (.A1(n_1_0_670), .A2(n_1_0_669), .A3(n_1_0_668), + .A4(n_1_0_652), .ZN(RRs1[0])); + INV_X1_LVT i_1_0_1366 (.A(Rs2[1]), .ZN(n_1_0_1302)); + NAND3_X1_LVT i_1_0_683 (.A1(n_1_0_1302), .A2(Rs2[4]), .A3(Rs2[2]), .ZN( + n_1_0_651)); + INV_X1_LVT i_1_0_1369 (.A(Rs2[3]), .ZN(n_1_0_1305)); + OR2_X1_LVT i_1_0_673 (.A1(n_1_0_1305), .A2(Rs2[0]), .ZN(n_1_0_641)); + NOR2_X1_LVT i_1_0_666 (.A1(n_1_0_651), .A2(n_1_0_641), .ZN(n_1_0_634)); + NAND2_X1_LVT i_1_0_677 (.A1(n_1_0_1305), .A2(Rs2[0]), .ZN(n_1_0_645)); + INV_X1_LVT i_1_0_1368 (.A(Rs2[2]), .ZN(n_1_0_1304)); + NAND3_X1_LVT i_1_0_662 (.A1(n_1_0_1304), .A2(n_1_0_1302), .A3(Rs2[4]), + .ZN(n_1_0_630)); + NOR2_X1_LVT i_1_0_661 (.A1(n_1_0_645), .A2(n_1_0_630), .ZN(n_1_0_629)); + AOI22_X1_LVT i_1_0_641 (.A1(registers_28__ap[31]), .A2(n_1_0_634), .B1( + n_1_0_629), .B2(registers_17__ap[31]), .ZN(n_1_0_609)); + NAND3_X1_LVT i_1_0_680 (.A1(n_1_0_1304), .A2(Rs2[4]), .A3(Rs2[1]), .ZN( + n_1_0_648)); + NOR2_X1_LVT i_1_0_672 (.A1(n_1_0_648), .A2(n_1_0_641), .ZN(n_1_0_640)); + INV_X1_LVT i_1_0_1367 (.A(Rs2[4]), .ZN(n_1_0_1303)); + NAND3_X1_LVT i_1_0_657 (.A1(n_1_0_1304), .A2(n_1_0_1303), .A3(Rs2[1]), + .ZN(n_1_0_625)); + NOR2_X1_LVT i_1_0_656 (.A1(n_1_0_641), .A2(n_1_0_625), .ZN(n_1_0_624)); + NOR4_X1_LVT i_1_0_658 (.A1(n_1_0_641), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), + .ZN(n_1_0_626)); + AOI222_X1_LVT i_1_0_640 (.A1(registers_26__ap[31]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[31]), .C1(n_1_0_626), .C2( + registers_8__ap[31]), .ZN(n_1_0_608)); + NAND2_X1_LVT i_1_0_682 (.A1(Rs2[0]), .A2(Rs2[3]), .ZN(n_1_0_650)); + NOR2_X1_LVT i_1_0_681 (.A1(n_1_0_651), .A2(n_1_0_650), .ZN(n_1_0_649)); + NOR4_X1_LVT i_1_0_649 (.A1(n_1_0_650), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), + .ZN(n_1_0_617)); + AOI22_X1_LVT i_1_0_639 (.A1(registers_29__ap[31]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[31]), .ZN(n_1_0_607)); + NOR4_X1_LVT i_1_0_676 (.A1(n_1_0_645), .A2(Rs2[1]), .A3(Rs2[4]), .A4(Rs2[2]), + .ZN(n_1_0_644)); + OR2_X1_LVT i_1_0_679 (.A1(Rs2[0]), .A2(Rs2[3]), .ZN(n_1_0_647)); + NAND3_X1_LVT i_1_0_660 (.A1(n_1_0_1303), .A2(Rs2[1]), .A3(Rs2[2]), .ZN( + n_1_0_628)); + NOR2_X1_LVT i_1_0_648 (.A1(n_1_0_647), .A2(n_1_0_628), .ZN(n_1_0_616)); + AOI22_X1_LVT i_1_0_638 (.A1(registers_1__ap[31]), .A2(n_1_0_644), .B1( + n_1_0_616), .B2(registers_6__ap[31]), .ZN(n_1_0_606)); + NOR2_X1_LVT i_1_0_655 (.A1(n_1_0_645), .A2(n_1_0_628), .ZN(n_1_0_623)); + NAND3_X1_LVT i_1_0_675 (.A1(Rs2[2]), .A2(Rs2[4]), .A3(Rs2[1]), .ZN(n_1_0_643)); + NOR2_X1_LVT i_1_0_647 (.A1(n_1_0_645), .A2(n_1_0_643), .ZN(n_1_0_615)); + AOI22_X1_LVT i_1_0_637 (.A1(registers_7__ap[31]), .A2(n_1_0_623), .B1( + n_1_0_615), .B2(registers_23__ap[31]), .ZN(n_1_0_605)); + NOR2_X1_LVT i_1_0_665 (.A1(n_1_0_648), .A2(n_1_0_645), .ZN(n_1_0_633)); + NOR2_X1_LVT i_1_0_646 (.A1(n_1_0_647), .A2(n_1_0_630), .ZN(n_1_0_614)); + AOI22_X1_LVT i_1_0_636 (.A1(registers_19__ap[31]), .A2(n_1_0_633), .B1( + n_1_0_614), .B2(registers_16__ap[31]), .ZN(n_1_0_604)); + NOR2_X1_LVT i_1_0_669 (.A1(n_1_0_650), .A2(n_1_0_643), .ZN(n_1_0_637)); + NAND3_X1_LVT i_1_0_671 (.A1(n_1_0_1303), .A2(n_1_0_1302), .A3(Rs2[2]), + .ZN(n_1_0_639)); + NOR2_X1_LVT i_1_0_667 (.A1(n_1_0_645), .A2(n_1_0_639), .ZN(n_1_0_635)); + AOI22_X1_LVT i_1_0_635 (.A1(registers_31__ap[31]), .A2(n_1_0_637), .B1( + n_1_0_635), .B2(registers_5__ap[31]), .ZN(n_1_0_603)); + NAND4_X1_LVT i_1_0_634 (.A1(n_1_0_606), .A2(n_1_0_605), .A3(n_1_0_604), + .A4(n_1_0_603), .ZN(n_1_0_602)); + NOR2_X1_LVT i_1_0_678 (.A1(n_1_0_648), .A2(n_1_0_647), .ZN(n_1_0_646)); + NOR2_X1_LVT i_1_0_654 (.A1(n_1_0_643), .A2(n_1_0_641), .ZN(n_1_0_622)); + AOI22_X1_LVT i_1_0_633 (.A1(registers_18__ap[31]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[31]), .ZN(n_1_0_601)); + NOR2_X1_LVT i_1_0_670 (.A1(n_1_0_647), .A2(n_1_0_639), .ZN(n_1_0_638)); + NOR2_X1_LVT i_1_0_645 (.A1(n_1_0_651), .A2(n_1_0_647), .ZN(n_1_0_613)); + AOI22_X1_LVT i_1_0_632 (.A1(registers_4__ap[31]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[31]), .ZN(n_1_0_600)); + NOR2_X1_LVT i_1_0_674 (.A1(n_1_0_647), .A2(n_1_0_643), .ZN(n_1_0_642)); + NOR2_X1_LVT i_1_0_644 (.A1(n_1_0_651), .A2(n_1_0_645), .ZN(n_1_0_612)); + AOI22_X1_LVT i_1_0_631 (.A1(registers_22__ap[31]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[31]), .ZN(n_1_0_599)); + NOR2_X1_LVT i_1_0_664 (.A1(n_1_0_641), .A2(n_1_0_639), .ZN(n_1_0_632)); + NOR2_X1_LVT i_1_0_653 (.A1(n_1_0_641), .A2(n_1_0_630), .ZN(n_1_0_621)); + AOI22_X1_LVT i_1_0_630 (.A1(registers_12__ap[31]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[31]), .ZN(n_1_0_598)); + NAND4_X1_LVT i_1_0_629 (.A1(n_1_0_601), .A2(n_1_0_600), .A3(n_1_0_599), + .A4(n_1_0_598), .ZN(n_1_0_597)); + NOR2_X1_LVT i_1_0_663 (.A1(n_1_0_650), .A2(n_1_0_639), .ZN(n_1_0_631)); + NOR2_X1_LVT i_1_0_652 (.A1(n_1_0_650), .A2(n_1_0_630), .ZN(n_1_0_620)); + AOI22_X1_LVT i_1_0_628 (.A1(registers_13__ap[31]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[31]), .ZN(n_1_0_596)); + NOR2_X1_LVT i_1_0_659 (.A1(n_1_0_650), .A2(n_1_0_628), .ZN(n_1_0_627)); + NOR2_X1_LVT i_1_0_651 (.A1(n_1_0_641), .A2(n_1_0_628), .ZN(n_1_0_619)); + AOI22_X1_LVT i_1_0_627 (.A1(registers_15__ap[31]), .A2(n_1_0_627), .B1( + n_1_0_619), .B2(registers_14__ap[31]), .ZN(n_1_0_595)); + NOR2_X1_LVT i_1_0_668 (.A1(n_1_0_650), .A2(n_1_0_648), .ZN(n_1_0_636)); + NOR2_X1_LVT i_1_0_643 (.A1(n_1_0_650), .A2(n_1_0_625), .ZN(n_1_0_611)); + AOI22_X1_LVT i_1_0_626 (.A1(registers_27__ap[31]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[31]), .ZN(n_1_0_594)); + NOR2_X1_LVT i_1_0_650 (.A1(n_1_0_647), .A2(n_1_0_625), .ZN(n_1_0_618)); + NOR2_X1_LVT i_1_0_642 (.A1(n_1_0_645), .A2(n_1_0_625), .ZN(n_1_0_610)); + AOI22_X1_LVT i_1_0_625 (.A1(registers_2__ap[31]), .A2(n_1_0_618), .B1( + n_1_0_610), .B2(registers_3__ap[31]), .ZN(n_1_0_593)); + NAND4_X1_LVT i_1_0_624 (.A1(n_1_0_596), .A2(n_1_0_595), .A3(n_1_0_594), + .A4(n_1_0_593), .ZN(n_1_0_592)); + NOR3_X1_LVT i_1_0_623 (.A1(n_1_0_602), .A2(n_1_0_597), .A3(n_1_0_592), + .ZN(n_1_0_591)); + NAND4_X1_LVT i_1_0_622 (.A1(n_1_0_609), .A2(n_1_0_608), .A3(n_1_0_607), + .A4(n_1_0_591), .ZN(RRs2[31])); + AOI22_X1_LVT i_1_0_620 (.A1(registers_29__ap[30]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[30]), .ZN(n_1_0_589)); + AOI22_X1_LVT i_1_0_621 (.A1(registers_7__ap[30]), .A2(n_1_0_623), .B1( + n_1_0_615), .B2(registers_23__ap[30]), .ZN(n_1_0_590)); + AOI22_X1_LVT i_1_0_619 (.A1(registers_1__ap[30]), .A2(n_1_0_644), .B1( + n_1_0_616), .B2(registers_6__ap[30]), .ZN(n_1_0_588)); + AOI22_X1_LVT i_1_0_618 (.A1(registers_5__ap[30]), .A2(n_1_0_635), .B1( + n_1_0_633), .B2(registers_19__ap[30]), .ZN(n_1_0_587)); + NAND3_X1_LVT i_1_0_617 (.A1(n_1_0_590), .A2(n_1_0_588), .A3(n_1_0_587), + .ZN(n_1_0_586)); + AOI221_X1_LVT i_1_0_616 (.A(n_1_0_586), .B1(n_1_0_637), .B2( + registers_31__ap[30]), .C1(registers_16__ap[30]), .C2(n_1_0_614), .ZN( + n_1_0_585)); + AOI222_X1_LVT i_1_0_615 (.A1(registers_26__ap[30]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[30]), .C1(n_1_0_626), .C2( + registers_8__ap[30]), .ZN(n_1_0_584)); + NAND3_X1_LVT i_1_0_614 (.A1(n_1_0_589), .A2(n_1_0_585), .A3(n_1_0_584), + .ZN(n_1_0_583)); + AOI221_X1_LVT i_1_0_613 (.A(n_1_0_583), .B1(n_1_0_629), .B2( + registers_17__ap[30]), .C1(registers_28__ap[30]), .C2(n_1_0_634), .ZN( + n_1_0_582)); + AOI22_X1_LVT i_1_0_612 (.A1(registers_18__ap[30]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[30]), .ZN(n_1_0_581)); + AOI22_X1_LVT i_1_0_611 (.A1(registers_4__ap[30]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[30]), .ZN(n_1_0_580)); + AOI22_X1_LVT i_1_0_610 (.A1(registers_22__ap[30]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[30]), .ZN(n_1_0_579)); + NAND3_X1_LVT i_1_0_609 (.A1(n_1_0_581), .A2(n_1_0_580), .A3(n_1_0_579), + .ZN(n_1_0_578)); + AOI221_X1_LVT i_1_0_608 (.A(n_1_0_578), .B1(n_1_0_621), .B2( + registers_24__ap[30]), .C1(registers_12__ap[30]), .C2(n_1_0_632), .ZN( + n_1_0_577)); + AOI22_X1_LVT i_1_0_607 (.A1(registers_13__ap[30]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[30]), .ZN(n_1_0_576)); + AOI22_X1_LVT i_1_0_606 (.A1(registers_15__ap[30]), .A2(n_1_0_627), .B1( + n_1_0_619), .B2(registers_14__ap[30]), .ZN(n_1_0_575)); + AOI22_X1_LVT i_1_0_605 (.A1(registers_27__ap[30]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[30]), .ZN(n_1_0_574)); + NAND3_X1_LVT i_1_0_604 (.A1(n_1_0_576), .A2(n_1_0_575), .A3(n_1_0_574), + .ZN(n_1_0_573)); + AOI221_X1_LVT i_1_0_603 (.A(n_1_0_573), .B1(n_1_0_610), .B2( + registers_3__ap[30]), .C1(registers_2__ap[30]), .C2(n_1_0_618), .ZN( + n_1_0_572)); + NAND3_X1_LVT i_1_0_602 (.A1(n_1_0_582), .A2(n_1_0_577), .A3(n_1_0_572), + .ZN(RRs2[30])); + AOI22_X1_LVT i_1_0_600 (.A1(registers_28__ap[29]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[29]), .ZN(n_1_0_570)); + AOI22_X1_LVT i_1_0_601 (.A1(registers_31__ap[29]), .A2(n_1_0_637), .B1( + n_1_0_627), .B2(registers_15__ap[29]), .ZN(n_1_0_571)); + AOI22_X1_LVT i_1_0_599 (.A1(registers_24__ap[29]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[29]), .ZN(n_1_0_569)); + AOI22_X1_LVT i_1_0_598 (.A1(registers_19__ap[29]), .A2(n_1_0_633), .B1( + n_1_0_629), .B2(registers_17__ap[29]), .ZN(n_1_0_568)); + NAND3_X1_LVT i_1_0_597 (.A1(n_1_0_571), .A2(n_1_0_569), .A3(n_1_0_568), + .ZN(n_1_0_567)); + AOI221_X1_LVT i_1_0_596 (.A(n_1_0_567), .B1(n_1_0_615), .B2( + registers_23__ap[29]), .C1(registers_29__ap[29]), .C2(n_1_0_649), .ZN( + n_1_0_566)); + AOI222_X1_LVT i_1_0_595 (.A1(registers_26__ap[29]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[29]), .C1(n_1_0_620), .C2( + registers_25__ap[29]), .ZN(n_1_0_565)); + NAND3_X1_LVT i_1_0_594 (.A1(n_1_0_570), .A2(n_1_0_566), .A3(n_1_0_565), + .ZN(n_1_0_564)); + AOI221_X1_LVT i_1_0_593 (.A(n_1_0_564), .B1(n_1_0_612), .B2( + registers_21__ap[29]), .C1(registers_13__ap[29]), .C2(n_1_0_631), .ZN( + n_1_0_563)); + AOI22_X1_LVT i_1_0_592 (.A1(registers_18__ap[29]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[29]), .ZN(n_1_0_562)); + AOI22_X1_LVT i_1_0_591 (.A1(registers_4__ap[29]), .A2(n_1_0_638), .B1( + n_1_0_632), .B2(registers_12__ap[29]), .ZN(n_1_0_561)); + AOI22_X1_LVT i_1_0_590 (.A1(registers_7__ap[29]), .A2(n_1_0_623), .B1( + n_1_0_614), .B2(registers_16__ap[29]), .ZN(n_1_0_560)); + NAND3_X1_LVT i_1_0_589 (.A1(n_1_0_562), .A2(n_1_0_561), .A3(n_1_0_560), + .ZN(n_1_0_559)); + AOI221_X1_LVT i_1_0_588 (.A(n_1_0_559), .B1(n_1_0_642), .B2( + registers_22__ap[29]), .C1(registers_5__ap[29]), .C2(n_1_0_635), .ZN( + n_1_0_558)); + AOI22_X1_LVT i_1_0_587 (.A1(registers_1__ap[29]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[29]), .ZN(n_1_0_557)); + AOI22_X1_LVT i_1_0_586 (.A1(registers_14__ap[29]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[29]), .ZN(n_1_0_556)); + AOI22_X1_LVT i_1_0_585 (.A1(registers_27__ap[29]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[29]), .ZN(n_1_0_555)); + NAND3_X1_LVT i_1_0_584 (.A1(n_1_0_557), .A2(n_1_0_556), .A3(n_1_0_555), + .ZN(n_1_0_554)); + AOI221_X1_LVT i_1_0_583 (.A(n_1_0_554), .B1(n_1_0_610), .B2( + registers_3__ap[29]), .C1(registers_2__ap[29]), .C2(n_1_0_618), .ZN( + n_1_0_553)); + NAND3_X1_LVT i_1_0_582 (.A1(n_1_0_563), .A2(n_1_0_558), .A3(n_1_0_553), + .ZN(RRs2[29])); + AOI22_X1_LVT i_1_0_581 (.A1(registers_5__ap[28]), .A2(n_1_0_635), .B1( + n_1_0_634), .B2(registers_28__ap[28]), .ZN(n_1_0_552)); + AOI222_X1_LVT i_1_0_580 (.A1(registers_26__ap[28]), .A2(n_1_0_640), .B1( + n_1_0_633), .B2(registers_19__ap[28]), .C1(n_1_0_626), .C2( + registers_8__ap[28]), .ZN(n_1_0_551)); + AOI22_X1_LVT i_1_0_579 (.A1(registers_2__ap[28]), .A2(n_1_0_618), .B1( + n_1_0_617), .B2(registers_9__ap[28]), .ZN(n_1_0_550)); + AOI22_X1_LVT i_1_0_578 (.A1(registers_7__ap[28]), .A2(n_1_0_623), .B1( + n_1_0_612), .B2(registers_21__ap[28]), .ZN(n_1_0_549)); + AOI22_X1_LVT i_1_0_577 (.A1(registers_16__ap[28]), .A2(n_1_0_614), .B1( + n_1_0_611), .B2(registers_11__ap[28]), .ZN(n_1_0_548)); + AOI22_X1_LVT i_1_0_576 (.A1(registers_31__ap[28]), .A2(n_1_0_637), .B1( + n_1_0_619), .B2(registers_14__ap[28]), .ZN(n_1_0_547)); + AOI22_X1_LVT i_1_0_575 (.A1(registers_15__ap[28]), .A2(n_1_0_627), .B1( + n_1_0_610), .B2(registers_3__ap[28]), .ZN(n_1_0_546)); + NAND4_X1_LVT i_1_0_574 (.A1(n_1_0_549), .A2(n_1_0_548), .A3(n_1_0_547), + .A4(n_1_0_546), .ZN(n_1_0_545)); + AOI22_X1_LVT i_1_0_573 (.A1(registers_22__ap[28]), .A2(n_1_0_642), .B1( + n_1_0_622), .B2(registers_30__ap[28]), .ZN(n_1_0_544)); + AOI22_X1_LVT i_1_0_572 (.A1(registers_4__ap[28]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[28]), .ZN(n_1_0_543)); + AOI22_X1_LVT i_1_0_571 (.A1(registers_29__ap[28]), .A2(n_1_0_649), .B1( + n_1_0_644), .B2(registers_1__ap[28]), .ZN(n_1_0_542)); + AOI22_X1_LVT i_1_0_570 (.A1(registers_12__ap[28]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[28]), .ZN(n_1_0_541)); + NAND4_X1_LVT i_1_0_569 (.A1(n_1_0_544), .A2(n_1_0_543), .A3(n_1_0_542), + .A4(n_1_0_541), .ZN(n_1_0_540)); + AOI22_X1_LVT i_1_0_568 (.A1(registers_13__ap[28]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[28]), .ZN(n_1_0_539)); + AOI22_X1_LVT i_1_0_567 (.A1(registers_17__ap[28]), .A2(n_1_0_629), .B1( + n_1_0_616), .B2(registers_6__ap[28]), .ZN(n_1_0_538)); + AOI22_X1_LVT i_1_0_566 (.A1(registers_10__ap[28]), .A2(n_1_0_624), .B1( + n_1_0_615), .B2(registers_23__ap[28]), .ZN(n_1_0_537)); + AOI22_X1_LVT i_1_0_565 (.A1(registers_18__ap[28]), .A2(n_1_0_646), .B1( + n_1_0_636), .B2(registers_27__ap[28]), .ZN(n_1_0_536)); + NAND4_X1_LVT i_1_0_564 (.A1(n_1_0_539), .A2(n_1_0_538), .A3(n_1_0_537), + .A4(n_1_0_536), .ZN(n_1_0_535)); + NOR3_X1_LVT i_1_0_563 (.A1(n_1_0_545), .A2(n_1_0_540), .A3(n_1_0_535), + .ZN(n_1_0_534)); + NAND4_X1_LVT i_1_0_562 (.A1(n_1_0_552), .A2(n_1_0_551), .A3(n_1_0_550), + .A4(n_1_0_534), .ZN(RRs2[28])); + AOI22_X1_LVT i_1_0_561 (.A1(registers_17__ap[27]), .A2(n_1_0_629), .B1( + n_1_0_612), .B2(registers_21__ap[27]), .ZN(n_1_0_533)); + AOI222_X1_LVT i_1_0_560 (.A1(registers_19__ap[27]), .A2(n_1_0_633), .B1( + n_1_0_631), .B2(registers_13__ap[27]), .C1(registers_30__ap[27]), .C2( + n_1_0_622), .ZN(n_1_0_532)); + AOI22_X1_LVT i_1_0_559 (.A1(registers_1__ap[27]), .A2(n_1_0_644), .B1( + n_1_0_634), .B2(registers_28__ap[27]), .ZN(n_1_0_531)); + AOI22_X1_LVT i_1_0_558 (.A1(registers_24__ap[27]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[27]), .ZN(n_1_0_530)); + AOI22_X1_LVT i_1_0_557 (.A1(registers_15__ap[27]), .A2(n_1_0_627), .B1( + n_1_0_611), .B2(registers_11__ap[27]), .ZN(n_1_0_529)); + AOI22_X1_LVT i_1_0_556 (.A1(registers_4__ap[27]), .A2(n_1_0_638), .B1( + n_1_0_636), .B2(registers_27__ap[27]), .ZN(n_1_0_528)); + AOI22_X1_LVT i_1_0_555 (.A1(registers_31__ap[27]), .A2(n_1_0_637), .B1( + n_1_0_618), .B2(registers_2__ap[27]), .ZN(n_1_0_527)); + NAND4_X1_LVT i_1_0_554 (.A1(n_1_0_530), .A2(n_1_0_529), .A3(n_1_0_528), + .A4(n_1_0_527), .ZN(n_1_0_526)); + AOI22_X1_LVT i_1_0_553 (.A1(registers_18__ap[27]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[27]), .ZN(n_1_0_525)); + AOI22_X1_LVT i_1_0_552 (.A1(registers_5__ap[27]), .A2(n_1_0_635), .B1( + n_1_0_632), .B2(registers_12__ap[27]), .ZN(n_1_0_524)); + AOI22_X1_LVT i_1_0_551 (.A1(registers_6__ap[27]), .A2(n_1_0_616), .B1( + n_1_0_614), .B2(registers_16__ap[27]), .ZN(n_1_0_523)); + AOI22_X1_LVT i_1_0_550 (.A1(registers_22__ap[27]), .A2(n_1_0_642), .B1( + n_1_0_620), .B2(registers_25__ap[27]), .ZN(n_1_0_522)); + NAND4_X1_LVT i_1_0_549 (.A1(n_1_0_525), .A2(n_1_0_524), .A3(n_1_0_523), + .A4(n_1_0_522), .ZN(n_1_0_521)); + AOI22_X1_LVT i_1_0_548 (.A1(registers_29__ap[27]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[27]), .ZN(n_1_0_520)); + AOI22_X1_LVT i_1_0_547 (.A1(registers_7__ap[27]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[27]), .ZN(n_1_0_519)); + AOI22_X1_LVT i_1_0_546 (.A1(registers_8__ap[27]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[27]), .ZN(n_1_0_518)); + AOI22_X1_LVT i_1_0_545 (.A1(registers_10__ap[27]), .A2(n_1_0_624), .B1( + n_1_0_610), .B2(registers_3__ap[27]), .ZN(n_1_0_517)); + NAND4_X1_LVT i_1_0_544 (.A1(n_1_0_520), .A2(n_1_0_519), .A3(n_1_0_518), + .A4(n_1_0_517), .ZN(n_1_0_516)); + NOR3_X1_LVT i_1_0_543 (.A1(n_1_0_526), .A2(n_1_0_521), .A3(n_1_0_516), + .ZN(n_1_0_515)); + NAND4_X1_LVT i_1_0_542 (.A1(n_1_0_533), .A2(n_1_0_532), .A3(n_1_0_531), + .A4(n_1_0_515), .ZN(RRs2[27])); + AOI22_X1_LVT i_1_0_541 (.A1(registers_17__ap[26]), .A2(n_1_0_629), .B1( + n_1_0_612), .B2(registers_21__ap[26]), .ZN(n_1_0_514)); + AOI222_X1_LVT i_1_0_540 (.A1(registers_19__ap[26]), .A2(n_1_0_633), .B1( + n_1_0_622), .B2(registers_30__ap[26]), .C1(n_1_0_631), .C2( + registers_13__ap[26]), .ZN(n_1_0_513)); + AOI22_X1_LVT i_1_0_539 (.A1(registers_1__ap[26]), .A2(n_1_0_644), .B1( + n_1_0_634), .B2(registers_28__ap[26]), .ZN(n_1_0_512)); + AOI22_X1_LVT i_1_0_538 (.A1(registers_24__ap[26]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[26]), .ZN(n_1_0_511)); + AOI22_X1_LVT i_1_0_537 (.A1(registers_15__ap[26]), .A2(n_1_0_627), .B1( + n_1_0_611), .B2(registers_11__ap[26]), .ZN(n_1_0_510)); + AOI22_X1_LVT i_1_0_536 (.A1(registers_4__ap[26]), .A2(n_1_0_638), .B1( + n_1_0_636), .B2(registers_27__ap[26]), .ZN(n_1_0_509)); + AOI22_X1_LVT i_1_0_535 (.A1(registers_31__ap[26]), .A2(n_1_0_637), .B1( + n_1_0_618), .B2(registers_2__ap[26]), .ZN(n_1_0_508)); + NAND4_X1_LVT i_1_0_534 (.A1(n_1_0_511), .A2(n_1_0_510), .A3(n_1_0_509), + .A4(n_1_0_508), .ZN(n_1_0_507)); + AOI22_X1_LVT i_1_0_533 (.A1(registers_18__ap[26]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[26]), .ZN(n_1_0_506)); + AOI22_X1_LVT i_1_0_532 (.A1(registers_5__ap[26]), .A2(n_1_0_635), .B1( + n_1_0_632), .B2(registers_12__ap[26]), .ZN(n_1_0_505)); + AOI22_X1_LVT i_1_0_531 (.A1(registers_6__ap[26]), .A2(n_1_0_616), .B1( + n_1_0_614), .B2(registers_16__ap[26]), .ZN(n_1_0_504)); + AOI22_X1_LVT i_1_0_530 (.A1(registers_22__ap[26]), .A2(n_1_0_642), .B1( + n_1_0_620), .B2(registers_25__ap[26]), .ZN(n_1_0_503)); + NAND4_X1_LVT i_1_0_529 (.A1(n_1_0_506), .A2(n_1_0_505), .A3(n_1_0_504), + .A4(n_1_0_503), .ZN(n_1_0_502)); + AOI22_X1_LVT i_1_0_528 (.A1(registers_29__ap[26]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[26]), .ZN(n_1_0_501)); + AOI22_X1_LVT i_1_0_527 (.A1(registers_7__ap[26]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[26]), .ZN(n_1_0_500)); + AOI22_X1_LVT i_1_0_526 (.A1(registers_8__ap[26]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[26]), .ZN(n_1_0_499)); + AOI22_X1_LVT i_1_0_525 (.A1(registers_10__ap[26]), .A2(n_1_0_624), .B1( + n_1_0_610), .B2(registers_3__ap[26]), .ZN(n_1_0_498)); + NAND4_X1_LVT i_1_0_524 (.A1(n_1_0_501), .A2(n_1_0_500), .A3(n_1_0_499), + .A4(n_1_0_498), .ZN(n_1_0_497)); + NOR3_X1_LVT i_1_0_523 (.A1(n_1_0_507), .A2(n_1_0_502), .A3(n_1_0_497), + .ZN(n_1_0_496)); + NAND4_X1_LVT i_1_0_522 (.A1(n_1_0_514), .A2(n_1_0_513), .A3(n_1_0_512), + .A4(n_1_0_496), .ZN(RRs2[26])); + AOI22_X1_LVT i_1_0_520 (.A1(registers_5__ap[25]), .A2(n_1_0_635), .B1( + n_1_0_634), .B2(registers_28__ap[25]), .ZN(n_1_0_494)); + AOI22_X1_LVT i_1_0_521 (.A1(registers_8__ap[25]), .A2(n_1_0_626), .B1( + n_1_0_620), .B2(registers_25__ap[25]), .ZN(n_1_0_495)); + AOI22_X1_LVT i_1_0_519 (.A1(registers_14__ap[25]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[25]), .ZN(n_1_0_493)); + AOI22_X1_LVT i_1_0_518 (.A1(registers_16__ap[25]), .A2(n_1_0_614), .B1( + n_1_0_611), .B2(registers_11__ap[25]), .ZN(n_1_0_492)); + NAND3_X1_LVT i_1_0_517 (.A1(n_1_0_495), .A2(n_1_0_493), .A3(n_1_0_492), + .ZN(n_1_0_491)); + AOI221_X1_LVT i_1_0_516 (.A(n_1_0_491), .B1(n_1_0_624), .B2( + registers_10__ap[25]), .C1(registers_6__ap[25]), .C2(n_1_0_616), .ZN( + n_1_0_490)); + AOI222_X1_LVT i_1_0_515 (.A1(registers_1__ap[25]), .A2(n_1_0_644), .B1( + n_1_0_640), .B2(registers_26__ap[25]), .C1(n_1_0_622), .C2( + registers_30__ap[25]), .ZN(n_1_0_489)); + NAND2_X1_LVT i_1_0_514 (.A1(n_1_0_490), .A2(n_1_0_489), .ZN(n_1_0_488)); + AOI221_X1_LVT i_1_0_513 (.A(n_1_0_488), .B1(n_1_0_649), .B2( + registers_29__ap[25]), .C1(registers_2__ap[25]), .C2(n_1_0_618), .ZN( + n_1_0_487)); + AOI22_X1_LVT i_1_0_512 (.A1(registers_12__ap[25]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[25]), .ZN(n_1_0_486)); + AOI22_X1_LVT i_1_0_511 (.A1(registers_22__ap[25]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[25]), .ZN(n_1_0_485)); + AOI22_X1_LVT i_1_0_510 (.A1(registers_4__ap[25]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[25]), .ZN(n_1_0_484)); + NAND3_X1_LVT i_1_0_509 (.A1(n_1_0_486), .A2(n_1_0_485), .A3(n_1_0_484), + .ZN(n_1_0_483)); + AOI221_X1_LVT i_1_0_508 (.A(n_1_0_483), .B1(n_1_0_633), .B2( + registers_19__ap[25]), .C1(registers_18__ap[25]), .C2(n_1_0_646), .ZN( + n_1_0_482)); + AOI22_X1_LVT i_1_0_507 (.A1(registers_15__ap[25]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[25]), .ZN(n_1_0_481)); + AOI22_X1_LVT i_1_0_506 (.A1(registers_23__ap[25]), .A2(n_1_0_615), .B1( + n_1_0_610), .B2(registers_3__ap[25]), .ZN(n_1_0_480)); + AOI22_X1_LVT i_1_0_505 (.A1(registers_13__ap[25]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[25]), .ZN(n_1_0_479)); + NAND3_X1_LVT i_1_0_504 (.A1(n_1_0_481), .A2(n_1_0_480), .A3(n_1_0_479), + .ZN(n_1_0_478)); + AOI221_X1_LVT i_1_0_503 (.A(n_1_0_478), .B1(n_1_0_636), .B2( + registers_27__ap[25]), .C1(registers_31__ap[25]), .C2(n_1_0_637), .ZN( + n_1_0_477)); + NAND4_X1_LVT i_1_0_502 (.A1(n_1_0_494), .A2(n_1_0_487), .A3(n_1_0_482), + .A4(n_1_0_477), .ZN(RRs2[25])); + AOI22_X1_LVT i_1_0_501 (.A1(registers_17__ap[24]), .A2(n_1_0_629), .B1( + n_1_0_612), .B2(registers_21__ap[24]), .ZN(n_1_0_476)); + AOI222_X1_LVT i_1_0_500 (.A1(registers_13__ap[24]), .A2(n_1_0_631), .B1( + n_1_0_622), .B2(registers_30__ap[24]), .C1(registers_26__ap[24]), .C2( + n_1_0_640), .ZN(n_1_0_475)); + AOI22_X1_LVT i_1_0_499 (.A1(registers_1__ap[24]), .A2(n_1_0_644), .B1( + n_1_0_634), .B2(registers_28__ap[24]), .ZN(n_1_0_474)); + AOI22_X1_LVT i_1_0_498 (.A1(registers_24__ap[24]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[24]), .ZN(n_1_0_473)); + AOI22_X1_LVT i_1_0_497 (.A1(registers_8__ap[24]), .A2(n_1_0_626), .B1( + n_1_0_616), .B2(registers_6__ap[24]), .ZN(n_1_0_472)); + AOI22_X1_LVT i_1_0_496 (.A1(registers_4__ap[24]), .A2(n_1_0_638), .B1( + n_1_0_611), .B2(registers_11__ap[24]), .ZN(n_1_0_471)); + AOI22_X1_LVT i_1_0_495 (.A1(registers_10__ap[24]), .A2(n_1_0_624), .B1( + n_1_0_618), .B2(registers_2__ap[24]), .ZN(n_1_0_470)); + NAND4_X1_LVT i_1_0_494 (.A1(n_1_0_473), .A2(n_1_0_472), .A3(n_1_0_471), + .A4(n_1_0_470), .ZN(n_1_0_469)); + AOI22_X1_LVT i_1_0_493 (.A1(registers_18__ap[24]), .A2(n_1_0_646), .B1( + n_1_0_633), .B2(registers_19__ap[24]), .ZN(n_1_0_468)); + AOI22_X1_LVT i_1_0_492 (.A1(registers_5__ap[24]), .A2(n_1_0_635), .B1( + n_1_0_632), .B2(registers_12__ap[24]), .ZN(n_1_0_467)); + AOI22_X1_LVT i_1_0_491 (.A1(registers_15__ap[24]), .A2(n_1_0_627), .B1( + n_1_0_614), .B2(registers_16__ap[24]), .ZN(n_1_0_466)); + AOI22_X1_LVT i_1_0_490 (.A1(registers_22__ap[24]), .A2(n_1_0_642), .B1( + n_1_0_620), .B2(registers_25__ap[24]), .ZN(n_1_0_465)); + NAND4_X1_LVT i_1_0_489 (.A1(n_1_0_468), .A2(n_1_0_467), .A3(n_1_0_466), + .A4(n_1_0_465), .ZN(n_1_0_464)); + AOI22_X1_LVT i_1_0_488 (.A1(registers_29__ap[24]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[24]), .ZN(n_1_0_463)); + AOI22_X1_LVT i_1_0_487 (.A1(registers_7__ap[24]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[24]), .ZN(n_1_0_462)); + AOI22_X1_LVT i_1_0_486 (.A1(registers_23__ap[24]), .A2(n_1_0_615), .B1( + n_1_0_610), .B2(registers_3__ap[24]), .ZN(n_1_0_461)); + AOI22_X1_LVT i_1_0_485 (.A1(registers_31__ap[24]), .A2(n_1_0_637), .B1( + n_1_0_636), .B2(registers_27__ap[24]), .ZN(n_1_0_460)); + NAND4_X1_LVT i_1_0_484 (.A1(n_1_0_463), .A2(n_1_0_462), .A3(n_1_0_461), + .A4(n_1_0_460), .ZN(n_1_0_459)); + NOR3_X1_LVT i_1_0_483 (.A1(n_1_0_469), .A2(n_1_0_464), .A3(n_1_0_459), + .ZN(n_1_0_458)); + NAND4_X1_LVT i_1_0_482 (.A1(n_1_0_476), .A2(n_1_0_475), .A3(n_1_0_474), + .A4(n_1_0_458), .ZN(RRs2[24])); + AOI22_X1_LVT i_1_0_481 (.A1(registers_4__ap[23]), .A2(n_1_0_638), .B1( + n_1_0_634), .B2(registers_28__ap[23]), .ZN(n_1_0_457)); + AOI222_X1_LVT i_1_0_480 (.A1(registers_18__ap[23]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[23]), .C1(n_1_0_644), .C2( + registers_1__ap[23]), .ZN(n_1_0_456)); + AOI22_X1_LVT i_1_0_479 (.A1(registers_29__ap[23]), .A2(n_1_0_649), .B1( + n_1_0_618), .B2(registers_2__ap[23]), .ZN(n_1_0_455)); + AOI22_X1_LVT i_1_0_478 (.A1(registers_14__ap[23]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[23]), .ZN(n_1_0_454)); + AOI22_X1_LVT i_1_0_477 (.A1(registers_16__ap[23]), .A2(n_1_0_614), .B1( + n_1_0_611), .B2(registers_11__ap[23]), .ZN(n_1_0_453)); + AOI22_X1_LVT i_1_0_476 (.A1(registers_27__ap[23]), .A2(n_1_0_636), .B1( + n_1_0_620), .B2(registers_25__ap[23]), .ZN(n_1_0_452)); + AOI22_X1_LVT i_1_0_475 (.A1(registers_31__ap[23]), .A2(n_1_0_637), .B1( + n_1_0_616), .B2(registers_6__ap[23]), .ZN(n_1_0_451)); + NAND4_X1_LVT i_1_0_474 (.A1(n_1_0_454), .A2(n_1_0_453), .A3(n_1_0_452), + .A4(n_1_0_451), .ZN(n_1_0_450)); + AOI22_X1_LVT i_1_0_473 (.A1(registers_26__ap[23]), .A2(n_1_0_640), .B1( + n_1_0_633), .B2(registers_19__ap[23]), .ZN(n_1_0_449)); + AOI22_X1_LVT i_1_0_472 (.A1(registers_12__ap[23]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[23]), .ZN(n_1_0_448)); + AOI22_X1_LVT i_1_0_471 (.A1(registers_22__ap[23]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[23]), .ZN(n_1_0_447)); + AOI22_X1_LVT i_1_0_470 (.A1(registers_5__ap[23]), .A2(n_1_0_635), .B1( + n_1_0_613), .B2(registers_20__ap[23]), .ZN(n_1_0_446)); + NAND4_X1_LVT i_1_0_469 (.A1(n_1_0_449), .A2(n_1_0_448), .A3(n_1_0_447), + .A4(n_1_0_446), .ZN(n_1_0_445)); + AOI22_X1_LVT i_1_0_468 (.A1(registers_15__ap[23]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[23]), .ZN(n_1_0_444)); + AOI22_X1_LVT i_1_0_467 (.A1(registers_8__ap[23]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[23]), .ZN(n_1_0_443)); + AOI22_X1_LVT i_1_0_466 (.A1(registers_13__ap[23]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[23]), .ZN(n_1_0_442)); + AOI22_X1_LVT i_1_0_465 (.A1(registers_10__ap[23]), .A2(n_1_0_624), .B1( + n_1_0_610), .B2(registers_3__ap[23]), .ZN(n_1_0_441)); + NAND4_X1_LVT i_1_0_464 (.A1(n_1_0_444), .A2(n_1_0_443), .A3(n_1_0_442), + .A4(n_1_0_441), .ZN(n_1_0_440)); + NOR3_X1_LVT i_1_0_463 (.A1(n_1_0_450), .A2(n_1_0_445), .A3(n_1_0_440), + .ZN(n_1_0_439)); + NAND4_X1_LVT i_1_0_462 (.A1(n_1_0_457), .A2(n_1_0_456), .A3(n_1_0_455), + .A4(n_1_0_439), .ZN(RRs2[23])); + AOI22_X1_LVT i_1_0_460 (.A1(registers_17__ap[22]), .A2(n_1_0_629), .B1( + n_1_0_612), .B2(registers_21__ap[22]), .ZN(n_1_0_437)); + AOI22_X1_LVT i_1_0_461 (.A1(registers_15__ap[22]), .A2(n_1_0_627), .B1( + n_1_0_626), .B2(registers_8__ap[22]), .ZN(n_1_0_438)); + AOI22_X1_LVT i_1_0_459 (.A1(registers_24__ap[22]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[22]), .ZN(n_1_0_436)); + AOI22_X1_LVT i_1_0_458 (.A1(registers_5__ap[22]), .A2(n_1_0_635), .B1( + n_1_0_611), .B2(registers_11__ap[22]), .ZN(n_1_0_435)); + NAND3_X1_LVT i_1_0_457 (.A1(n_1_0_438), .A2(n_1_0_436), .A3(n_1_0_435), + .ZN(n_1_0_434)); + AOI221_X1_LVT i_1_0_456 (.A(n_1_0_434), .B1(n_1_0_618), .B2( + registers_2__ap[22]), .C1(registers_10__ap[22]), .C2(n_1_0_624), .ZN( + n_1_0_433)); + AOI222_X1_LVT i_1_0_455 (.A1(registers_26__ap[22]), .A2(n_1_0_640), .B1( + n_1_0_622), .B2(registers_30__ap[22]), .C1(n_1_0_631), .C2( + registers_13__ap[22]), .ZN(n_1_0_432)); + NAND2_X1_LVT i_1_0_454 (.A1(n_1_0_433), .A2(n_1_0_432), .ZN(n_1_0_431)); + AOI221_X1_LVT i_1_0_453 (.A(n_1_0_431), .B1(n_1_0_644), .B2( + registers_1__ap[22]), .C1(registers_28__ap[22]), .C2(n_1_0_634), .ZN( + n_1_0_430)); + AOI22_X1_LVT i_1_0_452 (.A1(registers_18__ap[22]), .A2(n_1_0_646), .B1( + n_1_0_633), .B2(registers_19__ap[22]), .ZN(n_1_0_429)); + AOI22_X1_LVT i_1_0_451 (.A1(registers_4__ap[22]), .A2(n_1_0_638), .B1( + n_1_0_632), .B2(registers_12__ap[22]), .ZN(n_1_0_428)); + AOI22_X1_LVT i_1_0_450 (.A1(registers_6__ap[22]), .A2(n_1_0_616), .B1( + n_1_0_614), .B2(registers_16__ap[22]), .ZN(n_1_0_427)); + NAND3_X1_LVT i_1_0_449 (.A1(n_1_0_429), .A2(n_1_0_428), .A3(n_1_0_427), + .ZN(n_1_0_426)); + AOI221_X1_LVT i_1_0_448 (.A(n_1_0_426), .B1(n_1_0_620), .B2( + registers_25__ap[22]), .C1(registers_22__ap[22]), .C2(n_1_0_642), .ZN( + n_1_0_425)); + AOI22_X1_LVT i_1_0_447 (.A1(registers_29__ap[22]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[22]), .ZN(n_1_0_424)); + AOI22_X1_LVT i_1_0_446 (.A1(registers_7__ap[22]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[22]), .ZN(n_1_0_423)); + AOI22_X1_LVT i_1_0_445 (.A1(registers_23__ap[22]), .A2(n_1_0_615), .B1( + n_1_0_610), .B2(registers_3__ap[22]), .ZN(n_1_0_422)); + NAND3_X1_LVT i_1_0_444 (.A1(n_1_0_424), .A2(n_1_0_423), .A3(n_1_0_422), + .ZN(n_1_0_421)); + AOI221_X1_LVT i_1_0_443 (.A(n_1_0_421), .B1(n_1_0_636), .B2( + registers_27__ap[22]), .C1(registers_31__ap[22]), .C2(n_1_0_637), .ZN( + n_1_0_420)); + NAND4_X1_LVT i_1_0_442 (.A1(n_1_0_437), .A2(n_1_0_430), .A3(n_1_0_425), + .A4(n_1_0_420), .ZN(RRs2[22])); + AOI22_X1_LVT i_1_0_441 (.A1(registers_5__ap[21]), .A2(n_1_0_635), .B1( + n_1_0_634), .B2(registers_28__ap[21]), .ZN(n_1_0_419)); + AOI222_X1_LVT i_1_0_440 (.A1(registers_1__ap[21]), .A2(n_1_0_644), .B1( + n_1_0_640), .B2(registers_26__ap[21]), .C1(n_1_0_622), .C2( + registers_30__ap[21]), .ZN(n_1_0_418)); + AOI22_X1_LVT i_1_0_439 (.A1(registers_29__ap[21]), .A2(n_1_0_649), .B1( + n_1_0_618), .B2(registers_2__ap[21]), .ZN(n_1_0_417)); + AOI22_X1_LVT i_1_0_438 (.A1(registers_14__ap[21]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[21]), .ZN(n_1_0_416)); + AOI22_X1_LVT i_1_0_437 (.A1(registers_8__ap[21]), .A2(n_1_0_626), .B1( + n_1_0_614), .B2(registers_16__ap[21]), .ZN(n_1_0_415)); + AOI22_X1_LVT i_1_0_436 (.A1(registers_25__ap[21]), .A2(n_1_0_620), .B1( + n_1_0_611), .B2(registers_11__ap[21]), .ZN(n_1_0_414)); + AOI22_X1_LVT i_1_0_435 (.A1(registers_10__ap[21]), .A2(n_1_0_624), .B1( + n_1_0_616), .B2(registers_6__ap[21]), .ZN(n_1_0_413)); + NAND4_X1_LVT i_1_0_434 (.A1(n_1_0_416), .A2(n_1_0_415), .A3(n_1_0_414), + .A4(n_1_0_413), .ZN(n_1_0_412)); + AOI22_X1_LVT i_1_0_433 (.A1(registers_12__ap[21]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[21]), .ZN(n_1_0_411)); + AOI22_X1_LVT i_1_0_432 (.A1(registers_22__ap[21]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[21]), .ZN(n_1_0_410)); + AOI22_X1_LVT i_1_0_431 (.A1(registers_4__ap[21]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[21]), .ZN(n_1_0_409)); + AOI22_X1_LVT i_1_0_430 (.A1(registers_18__ap[21]), .A2(n_1_0_646), .B1( + n_1_0_633), .B2(registers_19__ap[21]), .ZN(n_1_0_408)); + NAND4_X1_LVT i_1_0_429 (.A1(n_1_0_411), .A2(n_1_0_410), .A3(n_1_0_409), + .A4(n_1_0_408), .ZN(n_1_0_407)); + AOI22_X1_LVT i_1_0_428 (.A1(registers_15__ap[21]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[21]), .ZN(n_1_0_406)); + AOI22_X1_LVT i_1_0_427 (.A1(registers_23__ap[21]), .A2(n_1_0_615), .B1( + n_1_0_610), .B2(registers_3__ap[21]), .ZN(n_1_0_405)); + AOI22_X1_LVT i_1_0_426 (.A1(registers_13__ap[21]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[21]), .ZN(n_1_0_404)); + AOI22_X1_LVT i_1_0_425 (.A1(registers_31__ap[21]), .A2(n_1_0_637), .B1( + n_1_0_636), .B2(registers_27__ap[21]), .ZN(n_1_0_403)); + NAND4_X1_LVT i_1_0_424 (.A1(n_1_0_406), .A2(n_1_0_405), .A3(n_1_0_404), + .A4(n_1_0_403), .ZN(n_1_0_402)); + NOR3_X1_LVT i_1_0_423 (.A1(n_1_0_412), .A2(n_1_0_407), .A3(n_1_0_402), + .ZN(n_1_0_401)); + NAND4_X1_LVT i_1_0_422 (.A1(n_1_0_419), .A2(n_1_0_418), .A3(n_1_0_417), + .A4(n_1_0_401), .ZN(RRs2[21])); + AOI22_X1_LVT i_1_0_421 (.A1(registers_17__ap[20]), .A2(n_1_0_629), .B1( + n_1_0_612), .B2(registers_21__ap[20]), .ZN(n_1_0_400)); + AOI222_X1_LVT i_1_0_420 (.A1(registers_13__ap[20]), .A2(n_1_0_631), .B1( + n_1_0_622), .B2(registers_30__ap[20]), .C1(registers_19__ap[20]), .C2( + n_1_0_633), .ZN(n_1_0_399)); + AOI22_X1_LVT i_1_0_419 (.A1(registers_1__ap[20]), .A2(n_1_0_644), .B1( + n_1_0_634), .B2(registers_28__ap[20]), .ZN(n_1_0_398)); + AOI22_X1_LVT i_1_0_418 (.A1(registers_24__ap[20]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[20]), .ZN(n_1_0_397)); + AOI22_X1_LVT i_1_0_417 (.A1(registers_6__ap[20]), .A2(n_1_0_616), .B1( + n_1_0_611), .B2(registers_11__ap[20]), .ZN(n_1_0_396)); + AOI22_X1_LVT i_1_0_416 (.A1(registers_4__ap[20]), .A2(n_1_0_638), .B1( + n_1_0_624), .B2(registers_10__ap[20]), .ZN(n_1_0_395)); + AOI22_X1_LVT i_1_0_415 (.A1(registers_31__ap[20]), .A2(n_1_0_637), .B1( + n_1_0_618), .B2(registers_2__ap[20]), .ZN(n_1_0_394)); + NAND4_X1_LVT i_1_0_414 (.A1(n_1_0_397), .A2(n_1_0_396), .A3(n_1_0_395), + .A4(n_1_0_394), .ZN(n_1_0_393)); + AOI22_X1_LVT i_1_0_413 (.A1(registers_18__ap[20]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[20]), .ZN(n_1_0_392)); + AOI22_X1_LVT i_1_0_412 (.A1(registers_5__ap[20]), .A2(n_1_0_635), .B1( + n_1_0_632), .B2(registers_12__ap[20]), .ZN(n_1_0_391)); + AOI22_X1_LVT i_1_0_411 (.A1(registers_15__ap[20]), .A2(n_1_0_627), .B1( + n_1_0_614), .B2(registers_16__ap[20]), .ZN(n_1_0_390)); + AOI22_X1_LVT i_1_0_410 (.A1(registers_22__ap[20]), .A2(n_1_0_642), .B1( + n_1_0_620), .B2(registers_25__ap[20]), .ZN(n_1_0_389)); + NAND4_X1_LVT i_1_0_409 (.A1(n_1_0_392), .A2(n_1_0_391), .A3(n_1_0_390), + .A4(n_1_0_389), .ZN(n_1_0_388)); + AOI22_X1_LVT i_1_0_408 (.A1(registers_29__ap[20]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[20]), .ZN(n_1_0_387)); + AOI22_X1_LVT i_1_0_407 (.A1(registers_7__ap[20]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[20]), .ZN(n_1_0_386)); + AOI22_X1_LVT i_1_0_406 (.A1(registers_8__ap[20]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[20]), .ZN(n_1_0_385)); + AOI22_X1_LVT i_1_0_405 (.A1(registers_27__ap[20]), .A2(n_1_0_636), .B1( + n_1_0_610), .B2(registers_3__ap[20]), .ZN(n_1_0_384)); + NAND4_X1_LVT i_1_0_404 (.A1(n_1_0_387), .A2(n_1_0_386), .A3(n_1_0_385), + .A4(n_1_0_384), .ZN(n_1_0_383)); + NOR3_X1_LVT i_1_0_403 (.A1(n_1_0_393), .A2(n_1_0_388), .A3(n_1_0_383), + .ZN(n_1_0_382)); + NAND4_X1_LVT i_1_0_402 (.A1(n_1_0_400), .A2(n_1_0_399), .A3(n_1_0_398), + .A4(n_1_0_382), .ZN(RRs2[20])); + AOI22_X1_LVT i_1_0_401 (.A1(registers_17__ap[19]), .A2(n_1_0_629), .B1( + n_1_0_612), .B2(registers_21__ap[19]), .ZN(n_1_0_381)); + AOI222_X1_LVT i_1_0_400 (.A1(registers_13__ap[19]), .A2(n_1_0_631), .B1( + n_1_0_622), .B2(registers_30__ap[19]), .C1(registers_19__ap[19]), .C2( + n_1_0_633), .ZN(n_1_0_380)); + AOI22_X1_LVT i_1_0_399 (.A1(registers_1__ap[19]), .A2(n_1_0_644), .B1( + n_1_0_634), .B2(registers_28__ap[19]), .ZN(n_1_0_379)); + AOI22_X1_LVT i_1_0_398 (.A1(registers_24__ap[19]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[19]), .ZN(n_1_0_378)); + AOI22_X1_LVT i_1_0_397 (.A1(registers_15__ap[19]), .A2(n_1_0_627), .B1( + n_1_0_611), .B2(registers_11__ap[19]), .ZN(n_1_0_377)); + AOI22_X1_LVT i_1_0_396 (.A1(registers_4__ap[19]), .A2(n_1_0_638), .B1( + n_1_0_636), .B2(registers_27__ap[19]), .ZN(n_1_0_376)); + AOI22_X1_LVT i_1_0_395 (.A1(registers_31__ap[19]), .A2(n_1_0_637), .B1( + n_1_0_618), .B2(registers_2__ap[19]), .ZN(n_1_0_375)); + NAND4_X1_LVT i_1_0_394 (.A1(n_1_0_378), .A2(n_1_0_377), .A3(n_1_0_376), + .A4(n_1_0_375), .ZN(n_1_0_374)); + AOI22_X1_LVT i_1_0_393 (.A1(registers_18__ap[19]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[19]), .ZN(n_1_0_373)); + AOI22_X1_LVT i_1_0_392 (.A1(registers_5__ap[19]), .A2(n_1_0_635), .B1( + n_1_0_632), .B2(registers_12__ap[19]), .ZN(n_1_0_372)); + AOI22_X1_LVT i_1_0_391 (.A1(registers_25__ap[19]), .A2(n_1_0_620), .B1( + n_1_0_616), .B2(registers_6__ap[19]), .ZN(n_1_0_371)); + AOI22_X1_LVT i_1_0_390 (.A1(registers_22__ap[19]), .A2(n_1_0_642), .B1( + n_1_0_614), .B2(registers_16__ap[19]), .ZN(n_1_0_370)); + NAND4_X1_LVT i_1_0_389 (.A1(n_1_0_373), .A2(n_1_0_372), .A3(n_1_0_371), + .A4(n_1_0_370), .ZN(n_1_0_369)); + AOI22_X1_LVT i_1_0_388 (.A1(registers_29__ap[19]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[19]), .ZN(n_1_0_368)); + AOI22_X1_LVT i_1_0_387 (.A1(registers_7__ap[19]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[19]), .ZN(n_1_0_367)); + AOI22_X1_LVT i_1_0_386 (.A1(registers_8__ap[19]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[19]), .ZN(n_1_0_366)); + AOI22_X1_LVT i_1_0_385 (.A1(registers_10__ap[19]), .A2(n_1_0_624), .B1( + n_1_0_610), .B2(registers_3__ap[19]), .ZN(n_1_0_365)); + NAND4_X1_LVT i_1_0_384 (.A1(n_1_0_368), .A2(n_1_0_367), .A3(n_1_0_366), + .A4(n_1_0_365), .ZN(n_1_0_364)); + NOR3_X1_LVT i_1_0_383 (.A1(n_1_0_374), .A2(n_1_0_369), .A3(n_1_0_364), + .ZN(n_1_0_363)); + NAND4_X1_LVT i_1_0_382 (.A1(n_1_0_381), .A2(n_1_0_380), .A3(n_1_0_379), + .A4(n_1_0_363), .ZN(RRs2[19])); + AOI22_X1_LVT i_1_0_380 (.A1(registers_4__ap[18]), .A2(n_1_0_638), .B1( + n_1_0_634), .B2(registers_28__ap[18]), .ZN(n_1_0_361)); + AOI22_X1_LVT i_1_0_381 (.A1(registers_8__ap[18]), .A2(n_1_0_626), .B1( + n_1_0_614), .B2(registers_16__ap[18]), .ZN(n_1_0_362)); + AOI22_X1_LVT i_1_0_379 (.A1(registers_14__ap[18]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[18]), .ZN(n_1_0_360)); + AOI22_X1_LVT i_1_0_378 (.A1(registers_25__ap[18]), .A2(n_1_0_620), .B1( + n_1_0_611), .B2(registers_11__ap[18]), .ZN(n_1_0_359)); + NAND3_X1_LVT i_1_0_377 (.A1(n_1_0_362), .A2(n_1_0_360), .A3(n_1_0_359), + .ZN(n_1_0_358)); + AOI221_X1_LVT i_1_0_376 (.A(n_1_0_358), .B1(n_1_0_624), .B2( + registers_10__ap[18]), .C1(registers_6__ap[18]), .C2(n_1_0_616), .ZN( + n_1_0_357)); + AOI222_X1_LVT i_1_0_375 (.A1(registers_1__ap[18]), .A2(n_1_0_644), .B1( + n_1_0_640), .B2(registers_26__ap[18]), .C1(n_1_0_622), .C2( + registers_30__ap[18]), .ZN(n_1_0_356)); + NAND2_X1_LVT i_1_0_374 (.A1(n_1_0_357), .A2(n_1_0_356), .ZN(n_1_0_355)); + AOI221_X1_LVT i_1_0_373 (.A(n_1_0_355), .B1(n_1_0_649), .B2( + registers_29__ap[18]), .C1(registers_2__ap[18]), .C2(n_1_0_618), .ZN( + n_1_0_354)); + AOI22_X1_LVT i_1_0_372 (.A1(registers_18__ap[18]), .A2(n_1_0_646), .B1( + n_1_0_633), .B2(registers_19__ap[18]), .ZN(n_1_0_353)); + AOI22_X1_LVT i_1_0_371 (.A1(registers_12__ap[18]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[18]), .ZN(n_1_0_352)); + AOI22_X1_LVT i_1_0_370 (.A1(registers_22__ap[18]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[18]), .ZN(n_1_0_351)); + NAND3_X1_LVT i_1_0_369 (.A1(n_1_0_353), .A2(n_1_0_352), .A3(n_1_0_351), + .ZN(n_1_0_350)); + AOI221_X1_LVT i_1_0_368 (.A(n_1_0_350), .B1(n_1_0_635), .B2( + registers_5__ap[18]), .C1(registers_20__ap[18]), .C2(n_1_0_613), .ZN( + n_1_0_349)); + AOI22_X1_LVT i_1_0_367 (.A1(registers_15__ap[18]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[18]), .ZN(n_1_0_348)); + AOI22_X1_LVT i_1_0_366 (.A1(registers_23__ap[18]), .A2(n_1_0_615), .B1( + n_1_0_610), .B2(registers_3__ap[18]), .ZN(n_1_0_347)); + AOI22_X1_LVT i_1_0_365 (.A1(registers_13__ap[18]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[18]), .ZN(n_1_0_346)); + NAND3_X1_LVT i_1_0_364 (.A1(n_1_0_348), .A2(n_1_0_347), .A3(n_1_0_346), + .ZN(n_1_0_345)); + AOI221_X1_LVT i_1_0_363 (.A(n_1_0_345), .B1(n_1_0_637), .B2( + registers_31__ap[18]), .C1(registers_27__ap[18]), .C2(n_1_0_636), .ZN( + n_1_0_344)); + NAND4_X1_LVT i_1_0_362 (.A1(n_1_0_361), .A2(n_1_0_354), .A3(n_1_0_349), + .A4(n_1_0_344), .ZN(RRs2[18])); + AOI22_X1_LVT i_1_0_358 (.A1(registers_4__ap[17]), .A2(n_1_0_638), .B1( + n_1_0_634), .B2(registers_28__ap[17]), .ZN(n_1_0_340)); + AOI22_X1_LVT i_1_0_361 (.A1(registers_31__ap[17]), .A2(n_1_0_637), .B1( + n_1_0_616), .B2(registers_6__ap[17]), .ZN(n_1_0_343)); + AOI22_X1_LVT i_1_0_357 (.A1(registers_14__ap[17]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[17]), .ZN(n_1_0_339)); + AOI22_X1_LVT i_1_0_360 (.A1(registers_25__ap[17]), .A2(n_1_0_620), .B1( + n_1_0_611), .B2(registers_11__ap[17]), .ZN(n_1_0_342)); + INV_X1_LVT i_1_0_359 (.A(n_1_0_342), .ZN(n_1_0_341)); + AOI221_X1_LVT i_1_0_356 (.A(n_1_0_341), .B1(n_1_0_614), .B2( + registers_16__ap[17]), .C1(registers_10__ap[17]), .C2(n_1_0_624), .ZN( + n_1_0_338)); + AOI222_X1_LVT i_1_0_355 (.A1(registers_1__ap[17]), .A2(n_1_0_644), .B1( + n_1_0_622), .B2(registers_30__ap[17]), .C1(registers_18__ap[17]), .C2( + n_1_0_646), .ZN(n_1_0_337)); + NAND4_X1_LVT i_1_0_354 (.A1(n_1_0_343), .A2(n_1_0_339), .A3(n_1_0_338), + .A4(n_1_0_337), .ZN(n_1_0_336)); + AOI221_X1_LVT i_1_0_353 (.A(n_1_0_336), .B1(n_1_0_649), .B2( + registers_29__ap[17]), .C1(registers_2__ap[17]), .C2(n_1_0_618), .ZN( + n_1_0_335)); + AOI22_X1_LVT i_1_0_352 (.A1(registers_26__ap[17]), .A2(n_1_0_640), .B1( + n_1_0_633), .B2(registers_19__ap[17]), .ZN(n_1_0_334)); + AOI22_X1_LVT i_1_0_351 (.A1(registers_12__ap[17]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[17]), .ZN(n_1_0_333)); + AOI22_X1_LVT i_1_0_350 (.A1(registers_22__ap[17]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[17]), .ZN(n_1_0_332)); + NAND3_X1_LVT i_1_0_349 (.A1(n_1_0_334), .A2(n_1_0_333), .A3(n_1_0_332), + .ZN(n_1_0_331)); + AOI221_X1_LVT i_1_0_348 (.A(n_1_0_331), .B1(n_1_0_635), .B2( + registers_5__ap[17]), .C1(registers_20__ap[17]), .C2(n_1_0_613), .ZN( + n_1_0_330)); + AOI22_X1_LVT i_1_0_347 (.A1(registers_15__ap[17]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[17]), .ZN(n_1_0_329)); + AOI22_X1_LVT i_1_0_346 (.A1(registers_8__ap[17]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[17]), .ZN(n_1_0_328)); + AOI22_X1_LVT i_1_0_345 (.A1(registers_13__ap[17]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[17]), .ZN(n_1_0_327)); + NAND3_X1_LVT i_1_0_344 (.A1(n_1_0_329), .A2(n_1_0_328), .A3(n_1_0_327), + .ZN(n_1_0_326)); + AOI221_X1_LVT i_1_0_343 (.A(n_1_0_326), .B1(n_1_0_636), .B2( + registers_27__ap[17]), .C1(registers_3__ap[17]), .C2(n_1_0_610), .ZN( + n_1_0_325)); + NAND4_X1_LVT i_1_0_342 (.A1(n_1_0_340), .A2(n_1_0_335), .A3(n_1_0_330), + .A4(n_1_0_325), .ZN(RRs2[17])); + AOI22_X1_LVT i_1_0_341 (.A1(registers_4__ap[16]), .A2(n_1_0_638), .B1( + n_1_0_634), .B2(registers_28__ap[16]), .ZN(n_1_0_324)); + AOI222_X1_LVT i_1_0_340 (.A1(registers_1__ap[16]), .A2(n_1_0_644), .B1( + n_1_0_633), .B2(registers_19__ap[16]), .C1(n_1_0_622), .C2( + registers_30__ap[16]), .ZN(n_1_0_323)); + AOI22_X1_LVT i_1_0_339 (.A1(registers_29__ap[16]), .A2(n_1_0_649), .B1( + n_1_0_618), .B2(registers_2__ap[16]), .ZN(n_1_0_322)); + AOI22_X1_LVT i_1_0_338 (.A1(registers_14__ap[16]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[16]), .ZN(n_1_0_321)); + AOI22_X1_LVT i_1_0_337 (.A1(registers_16__ap[16]), .A2(n_1_0_614), .B1( + n_1_0_611), .B2(registers_11__ap[16]), .ZN(n_1_0_320)); + AOI22_X1_LVT i_1_0_336 (.A1(registers_10__ap[16]), .A2(n_1_0_624), .B1( + n_1_0_620), .B2(registers_25__ap[16]), .ZN(n_1_0_319)); + AOI22_X1_LVT i_1_0_335 (.A1(registers_31__ap[16]), .A2(n_1_0_637), .B1( + n_1_0_616), .B2(registers_6__ap[16]), .ZN(n_1_0_318)); + NAND4_X1_LVT i_1_0_334 (.A1(n_1_0_321), .A2(n_1_0_320), .A3(n_1_0_319), + .A4(n_1_0_318), .ZN(n_1_0_317)); + AOI22_X1_LVT i_1_0_333 (.A1(registers_18__ap[16]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[16]), .ZN(n_1_0_316)); + AOI22_X1_LVT i_1_0_332 (.A1(registers_12__ap[16]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[16]), .ZN(n_1_0_315)); + AOI22_X1_LVT i_1_0_331 (.A1(registers_22__ap[16]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[16]), .ZN(n_1_0_314)); + AOI22_X1_LVT i_1_0_330 (.A1(registers_5__ap[16]), .A2(n_1_0_635), .B1( + n_1_0_613), .B2(registers_20__ap[16]), .ZN(n_1_0_313)); + NAND4_X1_LVT i_1_0_329 (.A1(n_1_0_316), .A2(n_1_0_315), .A3(n_1_0_314), + .A4(n_1_0_313), .ZN(n_1_0_312)); + AOI22_X1_LVT i_1_0_328 (.A1(registers_15__ap[16]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[16]), .ZN(n_1_0_311)); + AOI22_X1_LVT i_1_0_327 (.A1(registers_8__ap[16]), .A2(n_1_0_626), .B1( + n_1_0_615), .B2(registers_23__ap[16]), .ZN(n_1_0_310)); + AOI22_X1_LVT i_1_0_326 (.A1(registers_13__ap[16]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[16]), .ZN(n_1_0_309)); + AOI22_X1_LVT i_1_0_325 (.A1(registers_27__ap[16]), .A2(n_1_0_636), .B1( + n_1_0_610), .B2(registers_3__ap[16]), .ZN(n_1_0_308)); + NAND4_X1_LVT i_1_0_324 (.A1(n_1_0_311), .A2(n_1_0_310), .A3(n_1_0_309), + .A4(n_1_0_308), .ZN(n_1_0_307)); + NOR3_X1_LVT i_1_0_323 (.A1(n_1_0_317), .A2(n_1_0_312), .A3(n_1_0_307), + .ZN(n_1_0_306)); + NAND4_X1_LVT i_1_0_322 (.A1(n_1_0_324), .A2(n_1_0_323), .A3(n_1_0_322), + .A4(n_1_0_306), .ZN(RRs2[16])); + AOI22_X1_LVT i_1_0_320 (.A1(registers_5__ap[15]), .A2(n_1_0_635), .B1( + n_1_0_634), .B2(registers_28__ap[15]), .ZN(n_1_0_304)); + AOI22_X1_LVT i_1_0_321 (.A1(registers_8__ap[15]), .A2(n_1_0_626), .B1( + n_1_0_620), .B2(registers_25__ap[15]), .ZN(n_1_0_305)); + AOI22_X1_LVT i_1_0_319 (.A1(registers_14__ap[15]), .A2(n_1_0_619), .B1( + n_1_0_617), .B2(registers_9__ap[15]), .ZN(n_1_0_303)); + AOI22_X1_LVT i_1_0_318 (.A1(registers_16__ap[15]), .A2(n_1_0_614), .B1( + n_1_0_611), .B2(registers_11__ap[15]), .ZN(n_1_0_302)); + NAND3_X1_LVT i_1_0_317 (.A1(n_1_0_305), .A2(n_1_0_303), .A3(n_1_0_302), + .ZN(n_1_0_301)); + AOI221_X1_LVT i_1_0_316 (.A(n_1_0_301), .B1(n_1_0_616), .B2( + registers_6__ap[15]), .C1(registers_10__ap[15]), .C2(n_1_0_624), .ZN( + n_1_0_300)); + AOI222_X1_LVT i_1_0_315 (.A1(registers_1__ap[15]), .A2(n_1_0_644), .B1( + n_1_0_640), .B2(registers_26__ap[15]), .C1(n_1_0_622), .C2( + registers_30__ap[15]), .ZN(n_1_0_299)); + NAND2_X1_LVT i_1_0_314 (.A1(n_1_0_300), .A2(n_1_0_299), .ZN(n_1_0_298)); + AOI221_X1_LVT i_1_0_313 (.A(n_1_0_298), .B1(n_1_0_649), .B2( + registers_29__ap[15]), .C1(registers_2__ap[15]), .C2(n_1_0_618), .ZN( + n_1_0_297)); + AOI22_X1_LVT i_1_0_312 (.A1(registers_12__ap[15]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[15]), .ZN(n_1_0_296)); + AOI22_X1_LVT i_1_0_311 (.A1(registers_22__ap[15]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[15]), .ZN(n_1_0_295)); + AOI22_X1_LVT i_1_0_310 (.A1(registers_4__ap[15]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[15]), .ZN(n_1_0_294)); + NAND3_X1_LVT i_1_0_309 (.A1(n_1_0_296), .A2(n_1_0_295), .A3(n_1_0_294), + .ZN(n_1_0_293)); + AOI221_X1_LVT i_1_0_308 (.A(n_1_0_293), .B1(n_1_0_633), .B2( + registers_19__ap[15]), .C1(registers_18__ap[15]), .C2(n_1_0_646), .ZN( + n_1_0_292)); + AOI22_X1_LVT i_1_0_307 (.A1(registers_15__ap[15]), .A2(n_1_0_627), .B1( + n_1_0_623), .B2(registers_7__ap[15]), .ZN(n_1_0_291)); + AOI22_X1_LVT i_1_0_306 (.A1(registers_23__ap[15]), .A2(n_1_0_615), .B1( + n_1_0_610), .B2(registers_3__ap[15]), .ZN(n_1_0_290)); + AOI22_X1_LVT i_1_0_305 (.A1(registers_13__ap[15]), .A2(n_1_0_631), .B1( + n_1_0_629), .B2(registers_17__ap[15]), .ZN(n_1_0_289)); + NAND3_X1_LVT i_1_0_304 (.A1(n_1_0_291), .A2(n_1_0_290), .A3(n_1_0_289), + .ZN(n_1_0_288)); + AOI221_X1_LVT i_1_0_303 (.A(n_1_0_288), .B1(n_1_0_636), .B2( + registers_27__ap[15]), .C1(registers_31__ap[15]), .C2(n_1_0_637), .ZN( + n_1_0_287)); + NAND4_X1_LVT i_1_0_302 (.A1(n_1_0_304), .A2(n_1_0_297), .A3(n_1_0_292), + .A4(n_1_0_287), .ZN(RRs2[15])); + AOI22_X1_LVT i_1_0_301 (.A1(registers_28__ap[14]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[14]), .ZN(n_1_0_286)); + AOI222_X1_LVT i_1_0_300 (.A1(registers_18__ap[14]), .A2(n_1_0_646), .B1( + n_1_0_620), .B2(registers_25__ap[14]), .C1(n_1_0_618), .C2( + registers_2__ap[14]), .ZN(n_1_0_285)); + AOI22_X1_LVT i_1_0_299 (.A1(registers_24__ap[14]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[14]), .ZN(n_1_0_284)); + AOI22_X1_LVT i_1_0_298 (.A1(registers_15__ap[14]), .A2(n_1_0_627), .B1( + n_1_0_610), .B2(registers_3__ap[14]), .ZN(n_1_0_283)); + AOI22_X1_LVT i_1_0_297 (.A1(registers_4__ap[14]), .A2(n_1_0_638), .B1( + n_1_0_637), .B2(registers_31__ap[14]), .ZN(n_1_0_282)); + AOI22_X1_LVT i_1_0_296 (.A1(registers_29__ap[14]), .A2(n_1_0_649), .B1( + n_1_0_615), .B2(registers_23__ap[14]), .ZN(n_1_0_281)); + NAND4_X1_LVT i_1_0_295 (.A1(n_1_0_284), .A2(n_1_0_283), .A3(n_1_0_282), + .A4(n_1_0_281), .ZN(n_1_0_280)); + AOI221_X1_LVT i_1_0_294 (.A(n_1_0_280), .B1(n_1_0_644), .B2( + registers_1__ap[14]), .C1(registers_13__ap[14]), .C2(n_1_0_631), .ZN( + n_1_0_279)); + AOI22_X1_LVT i_1_0_293 (.A1(registers_17__ap[14]), .A2(n_1_0_629), .B1( + n_1_0_623), .B2(registers_7__ap[14]), .ZN(n_1_0_278)); + AOI22_X1_LVT i_1_0_292 (.A1(registers_5__ap[14]), .A2(n_1_0_635), .B1( + n_1_0_632), .B2(registers_12__ap[14]), .ZN(n_1_0_277)); + AOI22_X1_LVT i_1_0_291 (.A1(registers_10__ap[14]), .A2(n_1_0_624), .B1( + n_1_0_622), .B2(registers_30__ap[14]), .ZN(n_1_0_276)); + AOI22_X1_LVT i_1_0_290 (.A1(registers_26__ap[14]), .A2(n_1_0_640), .B1( + n_1_0_614), .B2(registers_16__ap[14]), .ZN(n_1_0_275)); + NAND4_X1_LVT i_1_0_289 (.A1(n_1_0_278), .A2(n_1_0_277), .A3(n_1_0_276), + .A4(n_1_0_275), .ZN(n_1_0_274)); + AOI22_X1_LVT i_1_0_288 (.A1(registers_9__ap[14]), .A2(n_1_0_617), .B1( + n_1_0_612), .B2(registers_21__ap[14]), .ZN(n_1_0_273)); + AOI22_X1_LVT i_1_0_287 (.A1(registers_14__ap[14]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[14]), .ZN(n_1_0_272)); + AOI22_X1_LVT i_1_0_286 (.A1(registers_22__ap[14]), .A2(n_1_0_642), .B1( + n_1_0_633), .B2(registers_19__ap[14]), .ZN(n_1_0_271)); + AOI22_X1_LVT i_1_0_285 (.A1(registers_27__ap[14]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[14]), .ZN(n_1_0_270)); + NAND4_X1_LVT i_1_0_284 (.A1(n_1_0_273), .A2(n_1_0_272), .A3(n_1_0_271), + .A4(n_1_0_270), .ZN(n_1_0_269)); + NOR2_X1_LVT i_1_0_283 (.A1(n_1_0_274), .A2(n_1_0_269), .ZN(n_1_0_268)); + NAND4_X1_LVT i_1_0_282 (.A1(n_1_0_286), .A2(n_1_0_285), .A3(n_1_0_279), + .A4(n_1_0_268), .ZN(RRs2[14])); + AOI22_X1_LVT i_1_0_281 (.A1(registers_18__ap[13]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[13]), .ZN(n_1_0_267)); + AOI22_X1_LVT i_1_0_280 (.A1(registers_12__ap[13]), .A2(n_1_0_632), .B1( + n_1_0_629), .B2(registers_17__ap[13]), .ZN(n_1_0_266)); + AOI22_X1_LVT i_1_0_279 (.A1(registers_7__ap[13]), .A2(n_1_0_623), .B1( + n_1_0_614), .B2(registers_16__ap[13]), .ZN(n_1_0_265)); + NAND3_X1_LVT i_1_0_277 (.A1(n_1_0_267), .A2(n_1_0_266), .A3(n_1_0_265), + .ZN(n_1_0_263)); + AOI221_X1_LVT i_1_0_276 (.A(n_1_0_263), .B1(n_1_0_642), .B2( + registers_22__ap[13]), .C1(registers_5__ap[13]), .C2(n_1_0_635), .ZN( + n_1_0_262)); + AOI22_X1_LVT i_1_0_278 (.A1(registers_13__ap[13]), .A2(n_1_0_631), .B1( + n_1_0_612), .B2(registers_21__ap[13]), .ZN(n_1_0_264)); + AOI222_X1_LVT i_1_0_275 (.A1(registers_26__ap[13]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[13]), .C1(n_1_0_620), .C2( + registers_25__ap[13]), .ZN(n_1_0_261)); + AOI22_X1_LVT i_1_0_274 (.A1(registers_28__ap[13]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[13]), .ZN(n_1_0_260)); + NAND3_X1_LVT i_1_0_273 (.A1(n_1_0_264), .A2(n_1_0_261), .A3(n_1_0_260), + .ZN(n_1_0_259)); + AOI22_X1_LVT i_1_0_272 (.A1(registers_1__ap[13]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[13]), .ZN(n_1_0_258)); + AOI22_X1_LVT i_1_0_271 (.A1(registers_19__ap[13]), .A2(n_1_0_633), .B1( + n_1_0_618), .B2(registers_2__ap[13]), .ZN(n_1_0_257)); + AOI22_X1_LVT i_1_0_270 (.A1(registers_14__ap[13]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[13]), .ZN(n_1_0_256)); + AOI22_X1_LVT i_1_0_269 (.A1(registers_27__ap[13]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[13]), .ZN(n_1_0_255)); + NAND4_X1_LVT i_1_0_268 (.A1(n_1_0_258), .A2(n_1_0_257), .A3(n_1_0_256), + .A4(n_1_0_255), .ZN(n_1_0_254)); + AOI22_X1_LVT i_1_0_267 (.A1(registers_24__ap[13]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[13]), .ZN(n_1_0_253)); + AOI22_X1_LVT i_1_0_266 (.A1(registers_4__ap[13]), .A2(n_1_0_638), .B1( + n_1_0_637), .B2(registers_31__ap[13]), .ZN(n_1_0_252)); + AOI22_X1_LVT i_1_0_265 (.A1(registers_29__ap[13]), .A2(n_1_0_649), .B1( + n_1_0_615), .B2(registers_23__ap[13]), .ZN(n_1_0_251)); + AOI22_X1_LVT i_1_0_264 (.A1(registers_15__ap[13]), .A2(n_1_0_627), .B1( + n_1_0_610), .B2(registers_3__ap[13]), .ZN(n_1_0_250)); + NAND4_X1_LVT i_1_0_263 (.A1(n_1_0_253), .A2(n_1_0_252), .A3(n_1_0_251), + .A4(n_1_0_250), .ZN(n_1_0_249)); + NOR3_X1_LVT i_1_0_262 (.A1(n_1_0_259), .A2(n_1_0_254), .A3(n_1_0_249), + .ZN(n_1_0_248)); + NAND2_X1_LVT i_1_0_261 (.A1(n_1_0_262), .A2(n_1_0_248), .ZN(RRs2[13])); + AOI22_X1_LVT i_1_0_260 (.A1(registers_18__ap[12]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[12]), .ZN(n_1_0_247)); + AOI22_X1_LVT i_1_0_259 (.A1(registers_12__ap[12]), .A2(n_1_0_632), .B1( + n_1_0_629), .B2(registers_17__ap[12]), .ZN(n_1_0_246)); + AOI22_X1_LVT i_1_0_258 (.A1(registers_5__ap[12]), .A2(n_1_0_635), .B1( + n_1_0_623), .B2(registers_7__ap[12]), .ZN(n_1_0_245)); + NAND3_X1_LVT i_1_0_256 (.A1(n_1_0_247), .A2(n_1_0_246), .A3(n_1_0_245), + .ZN(n_1_0_243)); + AOI221_X1_LVT i_1_0_255 (.A(n_1_0_243), .B1(n_1_0_642), .B2( + registers_22__ap[12]), .C1(registers_16__ap[12]), .C2(n_1_0_614), .ZN( + n_1_0_242)); + AOI22_X1_LVT i_1_0_257 (.A1(registers_13__ap[12]), .A2(n_1_0_631), .B1( + n_1_0_612), .B2(registers_21__ap[12]), .ZN(n_1_0_244)); + AOI222_X1_LVT i_1_0_254 (.A1(registers_26__ap[12]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[12]), .C1(n_1_0_620), .C2( + registers_25__ap[12]), .ZN(n_1_0_241)); + AOI22_X1_LVT i_1_0_253 (.A1(registers_28__ap[12]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[12]), .ZN(n_1_0_240)); + NAND3_X1_LVT i_1_0_252 (.A1(n_1_0_244), .A2(n_1_0_241), .A3(n_1_0_240), + .ZN(n_1_0_239)); + AOI22_X1_LVT i_1_0_251 (.A1(registers_1__ap[12]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[12]), .ZN(n_1_0_238)); + AOI22_X1_LVT i_1_0_250 (.A1(registers_19__ap[12]), .A2(n_1_0_633), .B1( + n_1_0_618), .B2(registers_2__ap[12]), .ZN(n_1_0_237)); + AOI22_X1_LVT i_1_0_249 (.A1(registers_14__ap[12]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[12]), .ZN(n_1_0_236)); + AOI22_X1_LVT i_1_0_248 (.A1(registers_27__ap[12]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[12]), .ZN(n_1_0_235)); + NAND4_X1_LVT i_1_0_247 (.A1(n_1_0_238), .A2(n_1_0_237), .A3(n_1_0_236), + .A4(n_1_0_235), .ZN(n_1_0_234)); + AOI22_X1_LVT i_1_0_246 (.A1(registers_24__ap[12]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[12]), .ZN(n_1_0_233)); + AOI22_X1_LVT i_1_0_245 (.A1(registers_4__ap[12]), .A2(n_1_0_638), .B1( + n_1_0_637), .B2(registers_31__ap[12]), .ZN(n_1_0_232)); + AOI22_X1_LVT i_1_0_244 (.A1(registers_29__ap[12]), .A2(n_1_0_649), .B1( + n_1_0_615), .B2(registers_23__ap[12]), .ZN(n_1_0_231)); + AOI22_X1_LVT i_1_0_243 (.A1(registers_15__ap[12]), .A2(n_1_0_627), .B1( + n_1_0_610), .B2(registers_3__ap[12]), .ZN(n_1_0_230)); + NAND4_X1_LVT i_1_0_242 (.A1(n_1_0_233), .A2(n_1_0_232), .A3(n_1_0_231), + .A4(n_1_0_230), .ZN(n_1_0_229)); + NOR3_X1_LVT i_1_0_241 (.A1(n_1_0_239), .A2(n_1_0_234), .A3(n_1_0_229), + .ZN(n_1_0_228)); + NAND2_X1_LVT i_1_0_240 (.A1(n_1_0_242), .A2(n_1_0_228), .ZN(RRs2[12])); + AOI22_X1_LVT i_1_0_238 (.A1(registers_29__ap[11]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[11]), .ZN(n_1_0_226)); + AOI22_X1_LVT i_1_0_239 (.A1(registers_27__ap[11]), .A2(n_1_0_636), .B1( + n_1_0_627), .B2(registers_15__ap[11]), .ZN(n_1_0_227)); + AOI22_X1_LVT i_1_0_237 (.A1(registers_1__ap[11]), .A2(n_1_0_644), .B1( + n_1_0_616), .B2(registers_6__ap[11]), .ZN(n_1_0_225)); + AOI22_X1_LVT i_1_0_236 (.A1(registers_5__ap[11]), .A2(n_1_0_635), .B1( + n_1_0_615), .B2(registers_23__ap[11]), .ZN(n_1_0_224)); + NAND3_X1_LVT i_1_0_235 (.A1(n_1_0_227), .A2(n_1_0_225), .A3(n_1_0_224), + .ZN(n_1_0_223)); + AOI221_X1_LVT i_1_0_234 (.A(n_1_0_223), .B1(n_1_0_637), .B2( + registers_31__ap[11]), .C1(registers_16__ap[11]), .C2(n_1_0_614), .ZN( + n_1_0_222)); + AOI222_X1_LVT i_1_0_233 (.A1(registers_8__ap[11]), .A2(n_1_0_626), .B1( + n_1_0_624), .B2(registers_10__ap[11]), .C1(n_1_0_622), .C2( + registers_30__ap[11]), .ZN(n_1_0_221)); + NAND3_X1_LVT i_1_0_232 (.A1(n_1_0_226), .A2(n_1_0_222), .A3(n_1_0_221), + .ZN(n_1_0_220)); + AOI221_X1_LVT i_1_0_231 (.A(n_1_0_220), .B1(n_1_0_638), .B2( + registers_4__ap[11]), .C1(registers_28__ap[11]), .C2(n_1_0_634), .ZN( + n_1_0_219)); + AOI22_X1_LVT i_1_0_230 (.A1(registers_18__ap[11]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[11]), .ZN(n_1_0_218)); + AOI22_X1_LVT i_1_0_229 (.A1(registers_12__ap[11]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[11]), .ZN(n_1_0_217)); + AOI22_X1_LVT i_1_0_228 (.A1(registers_22__ap[11]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[11]), .ZN(n_1_0_216)); + NAND3_X1_LVT i_1_0_227 (.A1(n_1_0_218), .A2(n_1_0_217), .A3(n_1_0_216), + .ZN(n_1_0_215)); + AOI221_X1_LVT i_1_0_226 (.A(n_1_0_215), .B1(n_1_0_613), .B2( + registers_20__ap[11]), .C1(registers_17__ap[11]), .C2(n_1_0_629), .ZN( + n_1_0_214)); + AOI22_X1_LVT i_1_0_225 (.A1(registers_13__ap[11]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[11]), .ZN(n_1_0_213)); + AOI22_X1_LVT i_1_0_224 (.A1(registers_7__ap[11]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[11]), .ZN(n_1_0_212)); + AOI22_X1_LVT i_1_0_223 (.A1(registers_19__ap[11]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[11]), .ZN(n_1_0_211)); + NAND3_X1_LVT i_1_0_222 (.A1(n_1_0_213), .A2(n_1_0_212), .A3(n_1_0_211), + .ZN(n_1_0_210)); + AOI221_X1_LVT i_1_0_221 (.A(n_1_0_210), .B1(n_1_0_611), .B2( + registers_11__ap[11]), .C1(registers_2__ap[11]), .C2(n_1_0_618), .ZN( + n_1_0_209)); + NAND3_X1_LVT i_1_0_220 (.A1(n_1_0_219), .A2(n_1_0_214), .A3(n_1_0_209), + .ZN(RRs2[11])); + AOI22_X1_LVT i_1_0_219 (.A1(registers_28__ap[10]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[10]), .ZN(n_1_0_208)); + AOI222_X1_LVT i_1_0_218 (.A1(registers_26__ap[10]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[10]), .C1(registers_25__ap[10]), .C2( + n_1_0_620), .ZN(n_1_0_207)); + AOI22_X1_LVT i_1_0_217 (.A1(registers_13__ap[10]), .A2(n_1_0_631), .B1( + n_1_0_612), .B2(registers_21__ap[10]), .ZN(n_1_0_206)); + AOI22_X1_LVT i_1_0_216 (.A1(registers_24__ap[10]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[10]), .ZN(n_1_0_205)); + AOI22_X1_LVT i_1_0_215 (.A1(registers_15__ap[10]), .A2(n_1_0_627), .B1( + n_1_0_610), .B2(registers_3__ap[10]), .ZN(n_1_0_204)); + AOI22_X1_LVT i_1_0_214 (.A1(registers_31__ap[10]), .A2(n_1_0_637), .B1( + n_1_0_629), .B2(registers_17__ap[10]), .ZN(n_1_0_203)); + AOI22_X1_LVT i_1_0_213 (.A1(registers_29__ap[10]), .A2(n_1_0_649), .B1( + n_1_0_615), .B2(registers_23__ap[10]), .ZN(n_1_0_202)); + NAND4_X1_LVT i_1_0_212 (.A1(n_1_0_205), .A2(n_1_0_204), .A3(n_1_0_203), + .A4(n_1_0_202), .ZN(n_1_0_201)); + AOI22_X1_LVT i_1_0_211 (.A1(registers_18__ap[10]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[10]), .ZN(n_1_0_200)); + AOI22_X1_LVT i_1_0_210 (.A1(registers_4__ap[10]), .A2(n_1_0_638), .B1( + n_1_0_632), .B2(registers_12__ap[10]), .ZN(n_1_0_199)); + AOI22_X1_LVT i_1_0_209 (.A1(registers_7__ap[10]), .A2(n_1_0_623), .B1( + n_1_0_614), .B2(registers_16__ap[10]), .ZN(n_1_0_198)); + AOI22_X1_LVT i_1_0_208 (.A1(registers_22__ap[10]), .A2(n_1_0_642), .B1( + n_1_0_635), .B2(registers_5__ap[10]), .ZN(n_1_0_197)); + NAND4_X1_LVT i_1_0_207 (.A1(n_1_0_200), .A2(n_1_0_199), .A3(n_1_0_198), + .A4(n_1_0_197), .ZN(n_1_0_196)); + AOI22_X1_LVT i_1_0_206 (.A1(registers_1__ap[10]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[10]), .ZN(n_1_0_195)); + AOI22_X1_LVT i_1_0_205 (.A1(registers_14__ap[10]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[10]), .ZN(n_1_0_194)); + AOI22_X1_LVT i_1_0_204 (.A1(registers_19__ap[10]), .A2(n_1_0_633), .B1( + n_1_0_618), .B2(registers_2__ap[10]), .ZN(n_1_0_193)); + AOI22_X1_LVT i_1_0_203 (.A1(registers_27__ap[10]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[10]), .ZN(n_1_0_192)); + NAND4_X1_LVT i_1_0_202 (.A1(n_1_0_195), .A2(n_1_0_194), .A3(n_1_0_193), + .A4(n_1_0_192), .ZN(n_1_0_191)); + NOR3_X1_LVT i_1_0_201 (.A1(n_1_0_201), .A2(n_1_0_196), .A3(n_1_0_191), + .ZN(n_1_0_190)); + NAND4_X1_LVT i_1_0_200 (.A1(n_1_0_208), .A2(n_1_0_207), .A3(n_1_0_206), + .A4(n_1_0_190), .ZN(RRs2[10])); + AOI22_X1_LVT i_1_0_196 (.A1(registers_13__ap[9]), .A2(n_1_0_631), .B1( + n_1_0_612), .B2(registers_21__ap[9]), .ZN(n_1_0_186)); + AOI22_X1_LVT i_1_0_199 (.A1(registers_29__ap[9]), .A2(n_1_0_649), .B1( + n_1_0_636), .B2(registers_27__ap[9]), .ZN(n_1_0_189)); + AOI22_X1_LVT i_1_0_195 (.A1(registers_24__ap[9]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[9]), .ZN(n_1_0_185)); + AOI22_X1_LVT i_1_0_198 (.A1(registers_31__ap[9]), .A2(n_1_0_637), .B1( + n_1_0_627), .B2(registers_15__ap[9]), .ZN(n_1_0_188)); + INV_X1_LVT i_1_0_197 (.A(n_1_0_188), .ZN(n_1_0_187)); + AOI221_X1_LVT i_1_0_194 (.A(n_1_0_187), .B1(n_1_0_615), .B2( + registers_23__ap[9]), .C1(registers_4__ap[9]), .C2(n_1_0_638), .ZN( + n_1_0_184)); + AOI222_X1_LVT i_1_0_193 (.A1(registers_18__ap[9]), .A2(n_1_0_646), .B1( + n_1_0_624), .B2(registers_10__ap[9]), .C1(registers_25__ap[9]), .C2( + n_1_0_620), .ZN(n_1_0_183)); + NAND4_X1_LVT i_1_0_192 (.A1(n_1_0_189), .A2(n_1_0_185), .A3(n_1_0_184), + .A4(n_1_0_183), .ZN(n_1_0_182)); + AOI221_X1_LVT i_1_0_191 (.A(n_1_0_182), .B1(n_1_0_626), .B2( + registers_8__ap[9]), .C1(registers_28__ap[9]), .C2(n_1_0_634), .ZN( + n_1_0_181)); + AOI22_X1_LVT i_1_0_190 (.A1(registers_26__ap[9]), .A2(n_1_0_640), .B1( + n_1_0_622), .B2(registers_30__ap[9]), .ZN(n_1_0_180)); + AOI22_X1_LVT i_1_0_189 (.A1(registers_12__ap[9]), .A2(n_1_0_632), .B1( + n_1_0_629), .B2(registers_17__ap[9]), .ZN(n_1_0_179)); + AOI22_X1_LVT i_1_0_188 (.A1(registers_5__ap[9]), .A2(n_1_0_635), .B1( + n_1_0_623), .B2(registers_7__ap[9]), .ZN(n_1_0_178)); + NAND3_X1_LVT i_1_0_187 (.A1(n_1_0_180), .A2(n_1_0_179), .A3(n_1_0_178), + .ZN(n_1_0_177)); + AOI221_X1_LVT i_1_0_186 (.A(n_1_0_177), .B1(n_1_0_642), .B2( + registers_22__ap[9]), .C1(registers_16__ap[9]), .C2(n_1_0_614), .ZN( + n_1_0_176)); + AOI22_X1_LVT i_1_0_185 (.A1(registers_1__ap[9]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[9]), .ZN(n_1_0_175)); + AOI22_X1_LVT i_1_0_184 (.A1(registers_14__ap[9]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[9]), .ZN(n_1_0_174)); + AOI22_X1_LVT i_1_0_183 (.A1(registers_19__ap[9]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[9]), .ZN(n_1_0_173)); + NAND3_X1_LVT i_1_0_182 (.A1(n_1_0_175), .A2(n_1_0_174), .A3(n_1_0_173), + .ZN(n_1_0_172)); + AOI221_X1_LVT i_1_0_181 (.A(n_1_0_172), .B1(n_1_0_611), .B2( + registers_11__ap[9]), .C1(registers_2__ap[9]), .C2(n_1_0_618), .ZN( + n_1_0_171)); + NAND4_X1_LVT i_1_0_180 (.A1(n_1_0_186), .A2(n_1_0_181), .A3(n_1_0_176), + .A4(n_1_0_171), .ZN(RRs2[9])); + AOI22_X1_LVT i_1_0_179 (.A1(registers_28__ap[8]), .A2(n_1_0_634), .B1( + n_1_0_629), .B2(registers_17__ap[8]), .ZN(n_1_0_170)); + AOI222_X1_LVT i_1_0_178 (.A1(registers_26__ap[8]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[8]), .C1(n_1_0_626), .C2( + registers_8__ap[8]), .ZN(n_1_0_169)); + AOI22_X1_LVT i_1_0_177 (.A1(registers_29__ap[8]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[8]), .ZN(n_1_0_168)); + AOI22_X1_LVT i_1_0_176 (.A1(registers_1__ap[8]), .A2(n_1_0_644), .B1( + n_1_0_616), .B2(registers_6__ap[8]), .ZN(n_1_0_167)); + AOI22_X1_LVT i_1_0_175 (.A1(registers_5__ap[8]), .A2(n_1_0_635), .B1( + n_1_0_610), .B2(registers_3__ap[8]), .ZN(n_1_0_166)); + AOI22_X1_LVT i_1_0_174 (.A1(registers_31__ap[8]), .A2(n_1_0_637), .B1( + n_1_0_614), .B2(registers_16__ap[8]), .ZN(n_1_0_165)); + AOI22_X1_LVT i_1_0_173 (.A1(registers_15__ap[8]), .A2(n_1_0_627), .B1( + n_1_0_615), .B2(registers_23__ap[8]), .ZN(n_1_0_164)); + NAND4_X1_LVT i_1_0_172 (.A1(n_1_0_167), .A2(n_1_0_166), .A3(n_1_0_165), + .A4(n_1_0_164), .ZN(n_1_0_163)); + AOI22_X1_LVT i_1_0_171 (.A1(registers_18__ap[8]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[8]), .ZN(n_1_0_162)); + AOI22_X1_LVT i_1_0_170 (.A1(registers_4__ap[8]), .A2(n_1_0_638), .B1( + n_1_0_613), .B2(registers_20__ap[8]), .ZN(n_1_0_161)); + AOI22_X1_LVT i_1_0_169 (.A1(registers_22__ap[8]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[8]), .ZN(n_1_0_160)); + AOI22_X1_LVT i_1_0_168 (.A1(registers_12__ap[8]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[8]), .ZN(n_1_0_159)); + NAND4_X1_LVT i_1_0_167 (.A1(n_1_0_162), .A2(n_1_0_161), .A3(n_1_0_160), + .A4(n_1_0_159), .ZN(n_1_0_158)); + AOI22_X1_LVT i_1_0_166 (.A1(registers_13__ap[8]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[8]), .ZN(n_1_0_157)); + AOI22_X1_LVT i_1_0_165 (.A1(registers_7__ap[8]), .A2(n_1_0_623), .B1( + n_1_0_619), .B2(registers_14__ap[8]), .ZN(n_1_0_156)); + AOI22_X1_LVT i_1_0_164 (.A1(registers_19__ap[8]), .A2(n_1_0_633), .B1( + n_1_0_618), .B2(registers_2__ap[8]), .ZN(n_1_0_155)); + AOI22_X1_LVT i_1_0_163 (.A1(registers_27__ap[8]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[8]), .ZN(n_1_0_154)); + NAND4_X1_LVT i_1_0_162 (.A1(n_1_0_157), .A2(n_1_0_156), .A3(n_1_0_155), + .A4(n_1_0_154), .ZN(n_1_0_153)); + NOR3_X1_LVT i_1_0_161 (.A1(n_1_0_163), .A2(n_1_0_158), .A3(n_1_0_153), + .ZN(n_1_0_152)); + NAND4_X1_LVT i_1_0_160 (.A1(n_1_0_170), .A2(n_1_0_169), .A3(n_1_0_168), + .A4(n_1_0_152), .ZN(RRs2[8])); + AOI22_X1_LVT i_1_0_159 (.A1(registers_28__ap[7]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[7]), .ZN(n_1_0_151)); + AOI222_X1_LVT i_1_0_158 (.A1(registers_26__ap[7]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[7]), .C1(registers_25__ap[7]), .C2( + n_1_0_620), .ZN(n_1_0_150)); + AOI22_X1_LVT i_1_0_157 (.A1(registers_24__ap[7]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[7]), .ZN(n_1_0_149)); + AOI22_X1_LVT i_1_0_156 (.A1(registers_15__ap[7]), .A2(n_1_0_627), .B1( + n_1_0_610), .B2(registers_3__ap[7]), .ZN(n_1_0_148)); + AOI22_X1_LVT i_1_0_155 (.A1(registers_31__ap[7]), .A2(n_1_0_637), .B1( + n_1_0_629), .B2(registers_17__ap[7]), .ZN(n_1_0_147)); + AOI22_X1_LVT i_1_0_154 (.A1(registers_29__ap[7]), .A2(n_1_0_649), .B1( + n_1_0_615), .B2(registers_23__ap[7]), .ZN(n_1_0_146)); + NAND4_X1_LVT i_1_0_153 (.A1(n_1_0_149), .A2(n_1_0_148), .A3(n_1_0_147), + .A4(n_1_0_146), .ZN(n_1_0_145)); + AOI221_X1_LVT i_1_0_152 (.A(n_1_0_145), .B1(n_1_0_612), .B2( + registers_21__ap[7]), .C1(registers_13__ap[7]), .C2(n_1_0_631), .ZN( + n_1_0_144)); + AOI22_X1_LVT i_1_0_151 (.A1(registers_18__ap[7]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[7]), .ZN(n_1_0_143)); + AOI22_X1_LVT i_1_0_150 (.A1(registers_4__ap[7]), .A2(n_1_0_638), .B1( + n_1_0_632), .B2(registers_12__ap[7]), .ZN(n_1_0_142)); + AOI22_X1_LVT i_1_0_149 (.A1(registers_5__ap[7]), .A2(n_1_0_635), .B1( + n_1_0_623), .B2(registers_7__ap[7]), .ZN(n_1_0_141)); + AOI22_X1_LVT i_1_0_148 (.A1(registers_22__ap[7]), .A2(n_1_0_642), .B1( + n_1_0_614), .B2(registers_16__ap[7]), .ZN(n_1_0_140)); + NAND4_X1_LVT i_1_0_147 (.A1(n_1_0_143), .A2(n_1_0_142), .A3(n_1_0_141), + .A4(n_1_0_140), .ZN(n_1_0_139)); + AOI22_X1_LVT i_1_0_146 (.A1(registers_1__ap[7]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[7]), .ZN(n_1_0_138)); + AOI22_X1_LVT i_1_0_145 (.A1(registers_14__ap[7]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[7]), .ZN(n_1_0_137)); + AOI22_X1_LVT i_1_0_144 (.A1(registers_19__ap[7]), .A2(n_1_0_633), .B1( + n_1_0_618), .B2(registers_2__ap[7]), .ZN(n_1_0_136)); + AOI22_X1_LVT i_1_0_143 (.A1(registers_27__ap[7]), .A2(n_1_0_636), .B1( + n_1_0_611), .B2(registers_11__ap[7]), .ZN(n_1_0_135)); + NAND4_X1_LVT i_1_0_142 (.A1(n_1_0_138), .A2(n_1_0_137), .A3(n_1_0_136), + .A4(n_1_0_135), .ZN(n_1_0_134)); + NOR2_X1_LVT i_1_0_141 (.A1(n_1_0_139), .A2(n_1_0_134), .ZN(n_1_0_133)); + NAND4_X1_LVT i_1_0_140 (.A1(n_1_0_151), .A2(n_1_0_150), .A3(n_1_0_144), + .A4(n_1_0_133), .ZN(RRs2[7])); + AOI22_X1_LVT i_1_0_136 (.A1(registers_13__ap[6]), .A2(n_1_0_631), .B1( + n_1_0_612), .B2(registers_21__ap[6]), .ZN(n_1_0_129)); + AOI22_X1_LVT i_1_0_139 (.A1(registers_29__ap[6]), .A2(n_1_0_649), .B1( + n_1_0_636), .B2(registers_27__ap[6]), .ZN(n_1_0_132)); + AOI22_X1_LVT i_1_0_135 (.A1(registers_24__ap[6]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[6]), .ZN(n_1_0_128)); + AOI22_X1_LVT i_1_0_138 (.A1(registers_31__ap[6]), .A2(n_1_0_637), .B1( + n_1_0_627), .B2(registers_15__ap[6]), .ZN(n_1_0_131)); + INV_X1_LVT i_1_0_137 (.A(n_1_0_131), .ZN(n_1_0_130)); + AOI221_X1_LVT i_1_0_134 (.A(n_1_0_130), .B1(n_1_0_638), .B2( + registers_4__ap[6]), .C1(registers_23__ap[6]), .C2(n_1_0_615), .ZN( + n_1_0_127)); + AOI222_X1_LVT i_1_0_133 (.A1(registers_18__ap[6]), .A2(n_1_0_646), .B1( + n_1_0_620), .B2(registers_25__ap[6]), .C1(n_1_0_624), .C2( + registers_10__ap[6]), .ZN(n_1_0_126)); + NAND4_X1_LVT i_1_0_132 (.A1(n_1_0_132), .A2(n_1_0_128), .A3(n_1_0_127), + .A4(n_1_0_126), .ZN(n_1_0_125)); + AOI221_X1_LVT i_1_0_131 (.A(n_1_0_125), .B1(n_1_0_626), .B2( + registers_8__ap[6]), .C1(registers_28__ap[6]), .C2(n_1_0_634), .ZN( + n_1_0_124)); + AOI22_X1_LVT i_1_0_130 (.A1(registers_26__ap[6]), .A2(n_1_0_640), .B1( + n_1_0_622), .B2(registers_30__ap[6]), .ZN(n_1_0_123)); + AOI22_X1_LVT i_1_0_129 (.A1(registers_12__ap[6]), .A2(n_1_0_632), .B1( + n_1_0_629), .B2(registers_17__ap[6]), .ZN(n_1_0_122)); + AOI22_X1_LVT i_1_0_128 (.A1(registers_7__ap[6]), .A2(n_1_0_623), .B1( + n_1_0_614), .B2(registers_16__ap[6]), .ZN(n_1_0_121)); + NAND3_X1_LVT i_1_0_127 (.A1(n_1_0_123), .A2(n_1_0_122), .A3(n_1_0_121), + .ZN(n_1_0_120)); + AOI221_X1_LVT i_1_0_126 (.A(n_1_0_120), .B1(n_1_0_642), .B2( + registers_22__ap[6]), .C1(registers_5__ap[6]), .C2(n_1_0_635), .ZN( + n_1_0_119)); + AOI22_X1_LVT i_1_0_125 (.A1(registers_1__ap[6]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[6]), .ZN(n_1_0_118)); + AOI22_X1_LVT i_1_0_124 (.A1(registers_14__ap[6]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[6]), .ZN(n_1_0_117)); + AOI22_X1_LVT i_1_0_123 (.A1(registers_19__ap[6]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[6]), .ZN(n_1_0_116)); + NAND3_X1_LVT i_1_0_122 (.A1(n_1_0_118), .A2(n_1_0_117), .A3(n_1_0_116), + .ZN(n_1_0_115)); + AOI221_X1_LVT i_1_0_121 (.A(n_1_0_115), .B1(n_1_0_618), .B2( + registers_2__ap[6]), .C1(registers_11__ap[6]), .C2(n_1_0_611), .ZN( + n_1_0_114)); + NAND4_X1_LVT i_1_0_120 (.A1(n_1_0_129), .A2(n_1_0_124), .A3(n_1_0_119), + .A4(n_1_0_114), .ZN(RRs2[6])); + AOI22_X1_LVT i_1_0_118 (.A1(registers_28__ap[5]), .A2(n_1_0_634), .B1( + n_1_0_626), .B2(registers_8__ap[5]), .ZN(n_1_0_112)); + AOI22_X1_LVT i_1_0_119 (.A1(registers_31__ap[5]), .A2(n_1_0_637), .B1( + n_1_0_627), .B2(registers_15__ap[5]), .ZN(n_1_0_113)); + AOI22_X1_LVT i_1_0_117 (.A1(registers_24__ap[5]), .A2(n_1_0_621), .B1( + n_1_0_613), .B2(registers_20__ap[5]), .ZN(n_1_0_111)); + AOI22_X1_LVT i_1_0_116 (.A1(registers_17__ap[5]), .A2(n_1_0_629), .B1( + n_1_0_615), .B2(registers_23__ap[5]), .ZN(n_1_0_110)); + NAND3_X1_LVT i_1_0_115 (.A1(n_1_0_113), .A2(n_1_0_111), .A3(n_1_0_110), + .ZN(n_1_0_109)); + AOI221_X1_LVT i_1_0_114 (.A(n_1_0_109), .B1(n_1_0_636), .B2( + registers_27__ap[5]), .C1(registers_29__ap[5]), .C2(n_1_0_649), .ZN( + n_1_0_108)); + AOI222_X1_LVT i_1_0_113 (.A1(registers_10__ap[5]), .A2(n_1_0_624), .B1( + n_1_0_620), .B2(registers_25__ap[5]), .C1(registers_18__ap[5]), .C2( + n_1_0_646), .ZN(n_1_0_107)); + NAND3_X1_LVT i_1_0_112 (.A1(n_1_0_112), .A2(n_1_0_108), .A3(n_1_0_107), + .ZN(n_1_0_106)); + AOI221_X1_LVT i_1_0_111 (.A(n_1_0_106), .B1(n_1_0_612), .B2( + registers_21__ap[5]), .C1(registers_13__ap[5]), .C2(n_1_0_631), .ZN( + n_1_0_105)); + AOI22_X1_LVT i_1_0_110 (.A1(registers_26__ap[5]), .A2(n_1_0_640), .B1( + n_1_0_622), .B2(registers_30__ap[5]), .ZN(n_1_0_104)); + AOI22_X1_LVT i_1_0_109 (.A1(registers_4__ap[5]), .A2(n_1_0_638), .B1( + n_1_0_632), .B2(registers_12__ap[5]), .ZN(n_1_0_103)); + AOI22_X1_LVT i_1_0_108 (.A1(registers_5__ap[5]), .A2(n_1_0_635), .B1( + n_1_0_623), .B2(registers_7__ap[5]), .ZN(n_1_0_102)); + NAND3_X1_LVT i_1_0_107 (.A1(n_1_0_104), .A2(n_1_0_103), .A3(n_1_0_102), + .ZN(n_1_0_101)); + AOI221_X1_LVT i_1_0_106 (.A(n_1_0_101), .B1(n_1_0_642), .B2( + registers_22__ap[5]), .C1(registers_16__ap[5]), .C2(n_1_0_614), .ZN( + n_1_0_100)); + AOI22_X1_LVT i_1_0_105 (.A1(registers_1__ap[5]), .A2(n_1_0_644), .B1( + n_1_0_617), .B2(registers_9__ap[5]), .ZN(n_1_0_99)); + AOI22_X1_LVT i_1_0_104 (.A1(registers_14__ap[5]), .A2(n_1_0_619), .B1( + n_1_0_616), .B2(registers_6__ap[5]), .ZN(n_1_0_98)); + AOI22_X1_LVT i_1_0_103 (.A1(registers_19__ap[5]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[5]), .ZN(n_1_0_97)); + NAND3_X1_LVT i_1_0_102 (.A1(n_1_0_99), .A2(n_1_0_98), .A3(n_1_0_97), .ZN( + n_1_0_96)); + AOI221_X1_LVT i_1_0_101 (.A(n_1_0_96), .B1(n_1_0_611), .B2( + registers_11__ap[5]), .C1(registers_2__ap[5]), .C2(n_1_0_618), .ZN( + n_1_0_95)); + NAND3_X1_LVT i_1_0_100 (.A1(n_1_0_105), .A2(n_1_0_100), .A3(n_1_0_95), + .ZN(RRs2[5])); + AOI22_X1_LVT i_1_0_99 (.A1(registers_4__ap[4]), .A2(n_1_0_638), .B1(n_1_0_634), + .B2(registers_28__ap[4]), .ZN(n_1_0_94)); + AOI222_X1_LVT i_1_0_98 (.A1(registers_8__ap[4]), .A2(n_1_0_626), .B1( + n_1_0_624), .B2(registers_10__ap[4]), .C1(n_1_0_622), .C2( + registers_30__ap[4]), .ZN(n_1_0_93)); + AOI22_X1_LVT i_1_0_97 (.A1(registers_29__ap[4]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[4]), .ZN(n_1_0_92)); + AOI22_X1_LVT i_1_0_96 (.A1(registers_1__ap[4]), .A2(n_1_0_644), .B1(n_1_0_616), + .B2(registers_6__ap[4]), .ZN(n_1_0_91)); + AOI22_X1_LVT i_1_0_95 (.A1(registers_27__ap[4]), .A2(n_1_0_636), .B1( + n_1_0_627), .B2(registers_15__ap[4]), .ZN(n_1_0_90)); + AOI22_X1_LVT i_1_0_94 (.A1(registers_23__ap[4]), .A2(n_1_0_615), .B1( + n_1_0_614), .B2(registers_16__ap[4]), .ZN(n_1_0_89)); + AOI22_X1_LVT i_1_0_93 (.A1(registers_31__ap[4]), .A2(n_1_0_637), .B1( + n_1_0_635), .B2(registers_5__ap[4]), .ZN(n_1_0_88)); + NAND4_X1_LVT i_1_0_92 (.A1(n_1_0_91), .A2(n_1_0_90), .A3(n_1_0_89), .A4( + n_1_0_88), .ZN(n_1_0_87)); + AOI22_X1_LVT i_1_0_91 (.A1(registers_18__ap[4]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[4]), .ZN(n_1_0_86)); + AOI22_X1_LVT i_1_0_90 (.A1(registers_12__ap[4]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[4]), .ZN(n_1_0_85)); + AOI22_X1_LVT i_1_0_89 (.A1(registers_22__ap[4]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[4]), .ZN(n_1_0_84)); + AOI22_X1_LVT i_1_0_88 (.A1(registers_17__ap[4]), .A2(n_1_0_629), .B1( + n_1_0_613), .B2(registers_20__ap[4]), .ZN(n_1_0_83)); + NAND4_X1_LVT i_1_0_87 (.A1(n_1_0_86), .A2(n_1_0_85), .A3(n_1_0_84), .A4( + n_1_0_83), .ZN(n_1_0_82)); + AOI22_X1_LVT i_1_0_86 (.A1(registers_13__ap[4]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[4]), .ZN(n_1_0_81)); + AOI22_X1_LVT i_1_0_85 (.A1(registers_7__ap[4]), .A2(n_1_0_623), .B1(n_1_0_619), + .B2(registers_14__ap[4]), .ZN(n_1_0_80)); + AOI22_X1_LVT i_1_0_84 (.A1(registers_19__ap[4]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[4]), .ZN(n_1_0_79)); + AOI22_X1_LVT i_1_0_83 (.A1(registers_2__ap[4]), .A2(n_1_0_618), .B1(n_1_0_611), + .B2(registers_11__ap[4]), .ZN(n_1_0_78)); + NAND4_X1_LVT i_1_0_82 (.A1(n_1_0_81), .A2(n_1_0_80), .A3(n_1_0_79), .A4( + n_1_0_78), .ZN(n_1_0_77)); + NOR3_X1_LVT i_1_0_81 (.A1(n_1_0_87), .A2(n_1_0_82), .A3(n_1_0_77), .ZN( + n_1_0_76)); + NAND4_X1_LVT i_1_0_80 (.A1(n_1_0_94), .A2(n_1_0_93), .A3(n_1_0_92), .A4( + n_1_0_76), .ZN(RRs2[4])); + AOI22_X1_LVT i_1_0_78 (.A1(registers_29__ap[3]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[3]), .ZN(n_1_0_74)); + AOI22_X1_LVT i_1_0_79 (.A1(registers_27__ap[3]), .A2(n_1_0_636), .B1( + n_1_0_627), .B2(registers_15__ap[3]), .ZN(n_1_0_75)); + AOI22_X1_LVT i_1_0_77 (.A1(registers_1__ap[3]), .A2(n_1_0_644), .B1(n_1_0_616), + .B2(registers_6__ap[3]), .ZN(n_1_0_73)); + AOI22_X1_LVT i_1_0_76 (.A1(registers_5__ap[3]), .A2(n_1_0_635), .B1(n_1_0_611), + .B2(registers_11__ap[3]), .ZN(n_1_0_72)); + NAND3_X1_LVT i_1_0_75 (.A1(n_1_0_75), .A2(n_1_0_73), .A3(n_1_0_72), .ZN( + n_1_0_71)); + AOI221_X1_LVT i_1_0_74 (.A(n_1_0_71), .B1(n_1_0_614), .B2(registers_16__ap[3]), + .C1(registers_31__ap[3]), .C2(n_1_0_637), .ZN(n_1_0_70)); + AOI222_X1_LVT i_1_0_73 (.A1(registers_8__ap[3]), .A2(n_1_0_626), .B1( + n_1_0_624), .B2(registers_10__ap[3]), .C1(n_1_0_622), .C2( + registers_30__ap[3]), .ZN(n_1_0_69)); + NAND3_X1_LVT i_1_0_72 (.A1(n_1_0_74), .A2(n_1_0_70), .A3(n_1_0_69), .ZN( + n_1_0_68)); + AOI221_X1_LVT i_1_0_71 (.A(n_1_0_68), .B1(n_1_0_638), .B2(registers_4__ap[3]), + .C1(registers_28__ap[3]), .C2(n_1_0_634), .ZN(n_1_0_67)); + AOI22_X1_LVT i_1_0_70 (.A1(registers_18__ap[3]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[3]), .ZN(n_1_0_66)); + AOI22_X1_LVT i_1_0_69 (.A1(registers_12__ap[3]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[3]), .ZN(n_1_0_65)); + AOI22_X1_LVT i_1_0_68 (.A1(registers_22__ap[3]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[3]), .ZN(n_1_0_64)); + NAND3_X1_LVT i_1_0_67 (.A1(n_1_0_66), .A2(n_1_0_65), .A3(n_1_0_64), .ZN( + n_1_0_63)); + AOI221_X1_LVT i_1_0_66 (.A(n_1_0_63), .B1(n_1_0_613), .B2(registers_20__ap[3]), + .C1(registers_17__ap[3]), .C2(n_1_0_629), .ZN(n_1_0_62)); + AOI22_X1_LVT i_1_0_65 (.A1(registers_13__ap[3]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[3]), .ZN(n_1_0_61)); + AOI22_X1_LVT i_1_0_64 (.A1(registers_7__ap[3]), .A2(n_1_0_623), .B1(n_1_0_619), + .B2(registers_14__ap[3]), .ZN(n_1_0_60)); + AOI22_X1_LVT i_1_0_63 (.A1(registers_19__ap[3]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[3]), .ZN(n_1_0_59)); + NAND3_X1_LVT i_1_0_62 (.A1(n_1_0_61), .A2(n_1_0_60), .A3(n_1_0_59), .ZN( + n_1_0_58)); + AOI221_X1_LVT i_1_0_61 (.A(n_1_0_58), .B1(n_1_0_618), .B2(registers_2__ap[3]), + .C1(registers_23__ap[3]), .C2(n_1_0_615), .ZN(n_1_0_57)); + NAND3_X1_LVT i_1_0_60 (.A1(n_1_0_67), .A2(n_1_0_62), .A3(n_1_0_57), .ZN( + RRs2[3])); + AOI22_X1_LVT i_1_0_58 (.A1(registers_29__ap[2]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[2]), .ZN(n_1_0_55)); + AOI22_X1_LVT i_1_0_59 (.A1(registers_27__ap[2]), .A2(n_1_0_636), .B1( + n_1_0_627), .B2(registers_15__ap[2]), .ZN(n_1_0_56)); + AOI22_X1_LVT i_1_0_57 (.A1(registers_1__ap[2]), .A2(n_1_0_644), .B1(n_1_0_616), + .B2(registers_6__ap[2]), .ZN(n_1_0_54)); + AOI22_X1_LVT i_1_0_56 (.A1(registers_5__ap[2]), .A2(n_1_0_635), .B1(n_1_0_615), + .B2(registers_23__ap[2]), .ZN(n_1_0_53)); + NAND3_X1_LVT i_1_0_55 (.A1(n_1_0_56), .A2(n_1_0_54), .A3(n_1_0_53), .ZN( + n_1_0_52)); + AOI221_X1_LVT i_1_0_54 (.A(n_1_0_52), .B1(n_1_0_637), .B2(registers_31__ap[2]), + .C1(registers_16__ap[2]), .C2(n_1_0_614), .ZN(n_1_0_51)); + AOI222_X1_LVT i_1_0_53 (.A1(registers_8__ap[2]), .A2(n_1_0_626), .B1( + n_1_0_624), .B2(registers_10__ap[2]), .C1(n_1_0_622), .C2( + registers_30__ap[2]), .ZN(n_1_0_50)); + NAND3_X1_LVT i_1_0_52 (.A1(n_1_0_55), .A2(n_1_0_51), .A3(n_1_0_50), .ZN( + n_1_0_49)); + AOI221_X1_LVT i_1_0_51 (.A(n_1_0_49), .B1(n_1_0_638), .B2(registers_4__ap[2]), + .C1(registers_28__ap[2]), .C2(n_1_0_634), .ZN(n_1_0_48)); + AOI22_X1_LVT i_1_0_50 (.A1(registers_18__ap[2]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[2]), .ZN(n_1_0_47)); + AOI22_X1_LVT i_1_0_49 (.A1(registers_12__ap[2]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[2]), .ZN(n_1_0_46)); + AOI22_X1_LVT i_1_0_48 (.A1(registers_22__ap[2]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[2]), .ZN(n_1_0_45)); + NAND3_X1_LVT i_1_0_47 (.A1(n_1_0_47), .A2(n_1_0_46), .A3(n_1_0_45), .ZN( + n_1_0_44)); + AOI221_X1_LVT i_1_0_46 (.A(n_1_0_44), .B1(n_1_0_629), .B2(registers_17__ap[2]), + .C1(registers_20__ap[2]), .C2(n_1_0_613), .ZN(n_1_0_43)); + AOI22_X1_LVT i_1_0_45 (.A1(registers_13__ap[2]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[2]), .ZN(n_1_0_42)); + AOI22_X1_LVT i_1_0_44 (.A1(registers_7__ap[2]), .A2(n_1_0_623), .B1(n_1_0_619), + .B2(registers_14__ap[2]), .ZN(n_1_0_41)); + AOI22_X1_LVT i_1_0_43 (.A1(registers_19__ap[2]), .A2(n_1_0_633), .B1( + n_1_0_610), .B2(registers_3__ap[2]), .ZN(n_1_0_40)); + NAND3_X1_LVT i_1_0_42 (.A1(n_1_0_42), .A2(n_1_0_41), .A3(n_1_0_40), .ZN( + n_1_0_39)); + AOI221_X1_LVT i_1_0_41 (.A(n_1_0_39), .B1(n_1_0_618), .B2(registers_2__ap[2]), + .C1(registers_11__ap[2]), .C2(n_1_0_611), .ZN(n_1_0_38)); + NAND3_X1_LVT i_1_0_40 (.A1(n_1_0_48), .A2(n_1_0_43), .A3(n_1_0_38), .ZN( + RRs2[2])); + AOI22_X1_LVT i_1_0_38 (.A1(registers_29__ap[1]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[1]), .ZN(n_1_0_36)); + AOI22_X1_LVT i_1_0_39 (.A1(registers_16__ap[1]), .A2(n_1_0_614), .B1( + n_1_0_610), .B2(registers_3__ap[1]), .ZN(n_1_0_37)); + AOI22_X1_LVT i_1_0_37 (.A1(registers_1__ap[1]), .A2(n_1_0_644), .B1(n_1_0_616), + .B2(registers_6__ap[1]), .ZN(n_1_0_35)); + AOI22_X1_LVT i_1_0_36 (.A1(registers_31__ap[1]), .A2(n_1_0_637), .B1( + n_1_0_635), .B2(registers_5__ap[1]), .ZN(n_1_0_34)); + NAND3_X1_LVT i_1_0_35 (.A1(n_1_0_37), .A2(n_1_0_35), .A3(n_1_0_34), .ZN( + n_1_0_33)); + AOI221_X1_LVT i_1_0_34 (.A(n_1_0_33), .B1(n_1_0_627), .B2(registers_15__ap[1]), + .C1(registers_23__ap[1]), .C2(n_1_0_615), .ZN(n_1_0_32)); + AOI222_X1_LVT i_1_0_33 (.A1(registers_26__ap[1]), .A2(n_1_0_640), .B1( + n_1_0_624), .B2(registers_10__ap[1]), .C1(n_1_0_626), .C2( + registers_8__ap[1]), .ZN(n_1_0_31)); + NAND3_X1_LVT i_1_0_32 (.A1(n_1_0_36), .A2(n_1_0_32), .A3(n_1_0_31), .ZN( + n_1_0_30)); + AOI221_X1_LVT i_1_0_31 (.A(n_1_0_30), .B1(n_1_0_629), .B2(registers_17__ap[1]), + .C1(registers_28__ap[1]), .C2(n_1_0_634), .ZN(n_1_0_29)); + AOI22_X1_LVT i_1_0_30 (.A1(registers_18__ap[1]), .A2(n_1_0_646), .B1( + n_1_0_622), .B2(registers_30__ap[1]), .ZN(n_1_0_28)); + AOI22_X1_LVT i_1_0_29 (.A1(registers_4__ap[1]), .A2(n_1_0_638), .B1(n_1_0_613), + .B2(registers_20__ap[1]), .ZN(n_1_0_27)); + AOI22_X1_LVT i_1_0_28 (.A1(registers_22__ap[1]), .A2(n_1_0_642), .B1( + n_1_0_612), .B2(registers_21__ap[1]), .ZN(n_1_0_26)); + NAND3_X1_LVT i_1_0_27 (.A1(n_1_0_28), .A2(n_1_0_27), .A3(n_1_0_26), .ZN( + n_1_0_25)); + AOI221_X1_LVT i_1_0_26 (.A(n_1_0_25), .B1(n_1_0_632), .B2(registers_12__ap[1]), + .C1(registers_24__ap[1]), .C2(n_1_0_621), .ZN(n_1_0_24)); + AOI22_X1_LVT i_1_0_25 (.A1(registers_13__ap[1]), .A2(n_1_0_631), .B1( + n_1_0_620), .B2(registers_25__ap[1]), .ZN(n_1_0_23)); + AOI22_X1_LVT i_1_0_24 (.A1(registers_7__ap[1]), .A2(n_1_0_623), .B1(n_1_0_619), + .B2(registers_14__ap[1]), .ZN(n_1_0_22)); + AOI22_X1_LVT i_1_0_23 (.A1(registers_19__ap[1]), .A2(n_1_0_633), .B1( + n_1_0_618), .B2(registers_2__ap[1]), .ZN(n_1_0_21)); + NAND3_X1_LVT i_1_0_22 (.A1(n_1_0_23), .A2(n_1_0_22), .A3(n_1_0_21), .ZN( + n_1_0_20)); + AOI221_X1_LVT i_1_0_21 (.A(n_1_0_20), .B1(n_1_0_611), .B2(registers_11__ap[1]), + .C1(registers_27__ap[1]), .C2(n_1_0_636), .ZN(n_1_0_19)); + NAND3_X1_LVT i_1_0_20 (.A1(n_1_0_29), .A2(n_1_0_24), .A3(n_1_0_19), .ZN( + RRs2[1])); + AOI22_X1_LVT i_1_0_19 (.A1(registers_4__ap[0]), .A2(n_1_0_638), .B1(n_1_0_634), + .B2(registers_28__ap[0]), .ZN(n_1_0_18)); + AOI222_X1_LVT i_1_0_18 (.A1(registers_8__ap[0]), .A2(n_1_0_626), .B1( + n_1_0_624), .B2(registers_10__ap[0]), .C1(n_1_0_622), .C2( + registers_30__ap[0]), .ZN(n_1_0_17)); + AOI22_X1_LVT i_1_0_17 (.A1(registers_29__ap[0]), .A2(n_1_0_649), .B1( + n_1_0_617), .B2(registers_9__ap[0]), .ZN(n_1_0_16)); + AOI22_X1_LVT i_1_0_16 (.A1(registers_1__ap[0]), .A2(n_1_0_644), .B1(n_1_0_616), + .B2(registers_6__ap[0]), .ZN(n_1_0_15)); + AOI22_X1_LVT i_1_0_15 (.A1(registers_27__ap[0]), .A2(n_1_0_636), .B1( + n_1_0_627), .B2(registers_15__ap[0]), .ZN(n_1_0_14)); + AOI22_X1_LVT i_1_0_14 (.A1(registers_23__ap[0]), .A2(n_1_0_615), .B1( + n_1_0_614), .B2(registers_16__ap[0]), .ZN(n_1_0_13)); + AOI22_X1_LVT i_1_0_13 (.A1(registers_31__ap[0]), .A2(n_1_0_637), .B1( + n_1_0_635), .B2(registers_5__ap[0]), .ZN(n_1_0_12)); + NAND4_X1_LVT i_1_0_12 (.A1(n_1_0_15), .A2(n_1_0_14), .A3(n_1_0_13), .A4( + n_1_0_12), .ZN(n_1_0_11)); + AOI22_X1_LVT i_1_0_11 (.A1(registers_18__ap[0]), .A2(n_1_0_646), .B1( + n_1_0_640), .B2(registers_26__ap[0]), .ZN(n_1_0_10)); + AOI22_X1_LVT i_1_0_10 (.A1(registers_12__ap[0]), .A2(n_1_0_632), .B1( + n_1_0_621), .B2(registers_24__ap[0]), .ZN(n_1_0_9)); + AOI22_X1_LVT i_1_0_9 (.A1(registers_22__ap[0]), .A2(n_1_0_642), .B1(n_1_0_612), + .B2(registers_21__ap[0]), .ZN(n_1_0_8)); + AOI22_X1_LVT i_1_0_8 (.A1(registers_17__ap[0]), .A2(n_1_0_629), .B1(n_1_0_613), + .B2(registers_20__ap[0]), .ZN(n_1_0_7)); + NAND4_X1_LVT i_1_0_7 (.A1(n_1_0_10), .A2(n_1_0_9), .A3(n_1_0_8), .A4(n_1_0_7), + .ZN(n_1_0_6)); + AOI22_X1_LVT i_1_0_6 (.A1(registers_13__ap[0]), .A2(n_1_0_631), .B1(n_1_0_620), + .B2(registers_25__ap[0]), .ZN(n_1_0_5)); + AOI22_X1_LVT i_1_0_5 (.A1(registers_7__ap[0]), .A2(n_1_0_623), .B1(n_1_0_619), + .B2(registers_14__ap[0]), .ZN(n_1_0_4)); + AOI22_X1_LVT i_1_0_4 (.A1(registers_19__ap[0]), .A2(n_1_0_633), .B1(n_1_0_610), + .B2(registers_3__ap[0]), .ZN(n_1_0_3)); + AOI22_X1_LVT i_1_0_3 (.A1(registers_2__ap[0]), .A2(n_1_0_618), .B1(n_1_0_611), + .B2(registers_11__ap[0]), .ZN(n_1_0_2)); + NAND4_X1_LVT i_1_0_2 (.A1(n_1_0_5), .A2(n_1_0_4), .A3(n_1_0_3), .A4(n_1_0_2), + .ZN(n_1_0_1)); + NOR3_X1_LVT i_1_0_1 (.A1(n_1_0_11), .A2(n_1_0_6), .A3(n_1_0_1), .ZN(n_1_0_0)); + NAND4_X1_LVT i_1_0_0 (.A1(n_1_0_18), .A2(n_1_0_17), .A3(n_1_0_16), .A4( + n_1_0_0), .ZN(RRs2[0])); + DLL_X2_LVT ts_lockup_latchn_clkc2_intno1050_i (.D(registers_1__ap[0]), + .GN(n_0_0__0), .Q(ts_no1050)); + DLL_X2_LVT ts_lockup_latchn_clkc4_intno1051_i (.D(registers_6__ap[0]), + .GN(n_0_36__0), .Q(ts_no1051)); + DLL_X2_LVT ts_lockup_latchn_clkc3_intno1053_i (.D(registers_27__ap[0]), + .GN(n_0_57__0), .Q(ts_no1053)); + DLL_X2_LVT ts_lockup_latchn_clkc1_intno1054_i (.D(registers_11__ap[0]), + .GN(n_0_41__0), .Q(ts_no1054)); +endmodule + +module MemGen_32_11(chip_en, clock, addr, rd_data, rd_en, wr_en, wr_data); + input chip_en; + input clock; + input [10:0]addr; + output [31:0]rd_data; + input rd_en; + input wr_en; + input [31:0]wr_data; + + wire [1:0]mem_sel; + + INV_X1_LVT i_1_3 (.A(addr[10]), .ZN(mem_sel[0])); + MemGen_16_10 genblk1_0_U_hi (.chip_en(mem_sel[0]), .wr_en(wr_en), .addr({ + addr[9], addr[8], addr[7], addr[6], addr[5], addr[4], addr[3], addr[2], + addr[1], addr[0]}), .wr_data({wr_data[31], wr_data[30], wr_data[29], + wr_data[28], wr_data[27], wr_data[26], wr_data[25], wr_data[24], + wr_data[23], wr_data[22], wr_data[21], wr_data[20], wr_data[19], + wr_data[18], wr_data[17], wr_data[16]}), .clock(clock), .rd_en(rd_en), + .rd_data({n_63, n_62, n_61, n_60, n_59, n_58, n_57, n_56, n_55, n_54, n_53, + n_52, n_51, n_50, n_49, n_48})); + MemGen_16_10 genblk1_1_U_hi (.chip_en(addr[10]), .wr_en(wr_en), .addr({ + addr[9], addr[8], addr[7], addr[6], addr[5], addr[4], addr[3], addr[2], + addr[1], addr[0]}), .wr_data({wr_data[31], wr_data[30], wr_data[29], + wr_data[28], wr_data[27], wr_data[26], wr_data[25], wr_data[24], + wr_data[23], wr_data[22], wr_data[21], wr_data[20], wr_data[19], + wr_data[18], wr_data[17], wr_data[16]}), .clock(clock), .rd_en(rd_en), + .rd_data({n_31, n_30, n_29, n_28, n_27, n_26, n_25, n_24, n_23, n_22, n_21, + n_20, n_19, n_18, n_17, n_16})); + MUX2_X1_LVT i_1_1_31 (.A(n_63), .B(n_31), .S(addr[10]), .Z(rd_data[31])); + MUX2_X1_LVT i_1_1_30 (.A(n_62), .B(n_30), .S(addr[10]), .Z(rd_data[30])); + MUX2_X1_LVT i_1_1_29 (.A(n_61), .B(n_29), .S(addr[10]), .Z(rd_data[29])); + MUX2_X1_LVT i_1_1_28 (.A(n_60), .B(n_28), .S(addr[10]), .Z(rd_data[28])); + MUX2_X1_LVT i_1_1_27 (.A(n_59), .B(n_27), .S(addr[10]), .Z(rd_data[27])); + MUX2_X1_LVT i_1_1_26 (.A(n_58), .B(n_26), .S(addr[10]), .Z(rd_data[26])); + MUX2_X1_LVT i_1_1_25 (.A(n_57), .B(n_25), .S(addr[10]), .Z(rd_data[25])); + MUX2_X1_LVT i_1_1_24 (.A(n_56), .B(n_24), .S(addr[10]), .Z(rd_data[24])); + MUX2_X1_LVT i_1_1_23 (.A(n_55), .B(n_23), .S(addr[10]), .Z(rd_data[23])); + MUX2_X1_LVT i_1_1_22 (.A(n_54), .B(n_22), .S(addr[10]), .Z(rd_data[22])); + MUX2_X1_LVT i_1_1_21 (.A(n_53), .B(n_21), .S(addr[10]), .Z(rd_data[21])); + MUX2_X1_LVT i_1_1_20 (.A(n_52), .B(n_20), .S(addr[10]), .Z(rd_data[20])); + MUX2_X1_LVT i_1_1_19 (.A(n_51), .B(n_19), .S(addr[10]), .Z(rd_data[19])); + MUX2_X1_LVT i_1_1_18 (.A(n_50), .B(n_18), .S(addr[10]), .Z(rd_data[18])); + MUX2_X1_LVT i_1_1_17 (.A(n_49), .B(n_17), .S(addr[10]), .Z(rd_data[17])); + MUX2_X1_LVT i_1_1_16 (.A(n_48), .B(n_16), .S(addr[10]), .Z(rd_data[16])); + MemGen_16_10 genblk1_0_U_lo (.chip_en(mem_sel[0]), .wr_en(wr_en), .addr({ + addr[9], addr[8], addr[7], addr[6], addr[5], addr[4], addr[3], addr[2], + addr[1], addr[0]}), .wr_data({wr_data[15], wr_data[14], wr_data[13], + wr_data[12], wr_data[11], wr_data[10], wr_data[9], wr_data[8], wr_data[7], + wr_data[6], wr_data[5], wr_data[4], wr_data[3], wr_data[2], wr_data[1], + wr_data[0]}), .clock(clock), .rd_en(rd_en), .rd_data({n_47, n_46, n_45, + n_44, n_43, n_42, n_41, n_40, n_39, n_38, n_37, n_36, n_35, n_34, n_33, + n_32})); + MemGen_16_10 genblk1_1_U_lo (.chip_en(addr[10]), .wr_en(wr_en), .addr({ + addr[9], addr[8], addr[7], addr[6], addr[5], addr[4], addr[3], addr[2], + addr[1], addr[0]}), .wr_data({wr_data[15], wr_data[14], wr_data[13], + wr_data[12], wr_data[11], wr_data[10], wr_data[9], wr_data[8], wr_data[7], + wr_data[6], wr_data[5], wr_data[4], wr_data[3], wr_data[2], wr_data[1], + wr_data[0]}), .clock(clock), .rd_en(rd_en), .rd_data({n_15, n_14, n_13, + n_12, n_11, n_10, n_9, n_8, n_7, n_6, n_5, n_4, n_3, n_2, n_1, n_0})); + MUX2_X1_LVT i_1_1_15 (.A(n_47), .B(n_15), .S(addr[10]), .Z(rd_data[15])); + MUX2_X1_LVT i_1_1_14 (.A(n_46), .B(n_14), .S(addr[10]), .Z(rd_data[14])); + MUX2_X1_LVT i_1_1_13 (.A(n_45), .B(n_13), .S(addr[10]), .Z(rd_data[13])); + MUX2_X1_LVT i_1_1_12 (.A(n_44), .B(n_12), .S(addr[10]), .Z(rd_data[12])); + MUX2_X1_LVT i_1_1_11 (.A(n_43), .B(n_11), .S(addr[10]), .Z(rd_data[11])); + MUX2_X1_LVT i_1_1_10 (.A(n_42), .B(n_10), .S(addr[10]), .Z(rd_data[10])); + MUX2_X1_LVT i_1_1_9 (.A(n_41), .B(n_9), .S(addr[10]), .Z(rd_data[9])); + MUX2_X1_LVT i_1_1_8 (.A(n_40), .B(n_8), .S(addr[10]), .Z(rd_data[8])); + MUX2_X1_LVT i_1_1_7 (.A(n_39), .B(n_7), .S(addr[10]), .Z(rd_data[7])); + MUX2_X1_LVT i_1_1_6 (.A(n_38), .B(n_6), .S(addr[10]), .Z(rd_data[6])); + MUX2_X1_LVT i_1_1_5 (.A(n_37), .B(n_5), .S(addr[10]), .Z(rd_data[5])); + MUX2_X1_LVT i_1_1_4 (.A(n_36), .B(n_4), .S(addr[10]), .Z(rd_data[4])); + MUX2_X1_LVT i_1_1_3 (.A(n_35), .B(n_3), .S(addr[10]), .Z(rd_data[3])); + MUX2_X1_LVT i_1_1_2 (.A(n_34), .B(n_2), .S(addr[10]), .Z(rd_data[2])); + MUX2_X1_LVT i_1_1_1 (.A(n_33), .B(n_1), .S(addr[10]), .Z(rd_data[1])); + MUX2_X1_LVT i_1_1_0 (.A(n_32), .B(n_0), .S(addr[10]), .Z(rd_data[0])); +endmodule + +module main_mem(clk, reset, DAddr, IAddr, DWData, DRData, IRData, DWE, DWidth); + input clk; + input reset; + input [31:0]DAddr; + input [31:0]IAddr; + input [31:0]DWData; + output [31:0]DRData; + output [31:0]IRData; + input DWE; + input [1:0]DWidth; + + wire [31:0]mem_rdata; + wire [10:0]mem_addr; + wire n_0_0; + wire n_0_0_0; + wire n_0_1; + wire n_0_0_1; + wire n_0_2; + wire n_0_0_2; + wire n_0_3; + wire n_0_0_3; + wire n_0_4; + wire n_0_0_4; + wire n_0_5; + wire n_0_0_5; + wire n_0_6; + wire n_0_0_6; + wire n_0_7; + wire n_0_0_7; + wire n_0_8; + wire n_0_0_8; + wire n_0_9; + wire n_0_0_9; + wire n_0_10; + wire n_0_0_10; + wire n_0_0_11; + wire n_0_11; + wire n_0_0_12; + wire n_0_0_13; + wire n_0_12; + wire n_0_0_14; + wire n_0_0_15; + wire n_0_13; + wire n_0_0_16; + wire n_0_0_17; + wire n_0_14; + wire n_0_0_18; + wire n_0_0_19; + wire n_0_15; + wire n_0_0_20; + wire n_0_0_21; + wire n_0_16; + wire n_0_0_22; + wire n_0_0_23; + wire n_0_17; + wire n_0_0_24; + wire n_0_0_25; + wire n_0_18; + wire n_0_0_26; + wire n_0_0_27; + wire n_0_0_28; + wire n_0_19; + wire n_0_0_29; + wire n_0_20; + wire n_0_0_30; + wire n_0_21; + wire n_0_0_31; + wire n_0_22; + wire n_0_0_32; + wire n_0_23; + wire n_0_0_33; + wire n_0_24; + wire n_0_0_34; + wire n_0_25; + wire n_0_0_35; + wire n_0_26; + wire n_0_0_36; + wire n_0_0_37; + wire n_0_27; + wire n_0_28; + wire n_0_29; + wire n_0_30; + wire n_0_31; + wire n_0_32; + wire n_0_33; + wire n_0_34; + wire n_0_35; + wire n_0_36; + wire n_0_37; + wire n_0_38; + wire n_0_39; + wire n_0_40; + wire n_0_41; + wire n_0_42; + wire n_0_65; + wire n_0_64; + wire n_0_63; + wire n_0_62; + wire n_0_61; + wire n_0_60; + wire n_0_59; + wire n_0_58; + wire n_0_0_38; + wire n_0_0_39; + wire n_0_57; + wire n_0_0_40; + wire n_0_56; + wire n_0_0_41; + wire n_0_55; + wire n_0_0_42; + wire n_0_54; + wire n_0_0_43; + wire n_0_53; + wire n_0_0_44; + wire n_0_52; + wire n_0_0_45; + wire n_0_51; + wire n_0_0_46; + wire n_0_50; + wire n_0_0_47; + wire n_0_0_48; + wire n_0_0_49; + wire n_0_0_50; + wire n_0_0_51; + wire n_0_49; + wire n_0_0_52; + wire n_0_48; + wire n_0_0_53; + wire n_0_47; + wire n_0_0_54; + wire n_0_46; + wire n_0_0_55; + wire n_0_45; + wire n_0_0_56; + wire n_0_44; + wire n_0_0_57; + wire n_0_66; + wire n_0_0_58; + wire n_0_67; + wire n_0_0_59; + wire n_0_0_60; + wire n_0_0_61; + wire n_0_68; + wire n_0_0_62; + wire n_0_0_63; + wire n_0_69; + wire n_0_0_64; + wire n_0_0_65; + wire n_0_70; + wire n_0_0_66; + wire n_0_0_67; + wire n_0_71; + wire n_0_0_68; + wire n_0_0_69; + wire n_0_72; + wire n_0_0_70; + wire n_0_0_71; + wire n_0_73; + wire n_0_0_72; + wire n_0_0_73; + wire n_0_74; + wire n_0_0_74; + wire n_0_0_75; + wire n_0_75; + wire n_0_0_76; + wire n_0_0_77; + wire n_0_0_78; + wire n_0_0_79; + wire n_0_0_80; + wire n_0_0_81; + wire n_0_0_82; + wire n_0_0_83; + wire n_0_0_84; + wire n_0_0_85; + wire n_0_0_86; + wire n_0_0_87; + wire n_0_0_88; + wire n_0_0_89; + wire n_0_0_90; + wire n_0_0_91; + wire n_0_0_92; + wire n_0_43; + wire n_0_0_93; + wire n_0_0_94; + wire n_0_76; + wire n_0_0_95; + wire [31:0]drTmp; + wire [31:0]mem_wdata; + + INV_X1_LVT i_0_0_171 (.A(DWE), .ZN(n_0)); + NOR2_X1_LVT i_0_0_163 (.A1(n_0), .A2(reset), .ZN(n_0_0_88)); + NOR2_X1_LVT i_0_0_22 (.A1(DWE), .A2(reset), .ZN(n_0_0_11)); + AOI22_X1_LVT i_0_0_21 (.A1(DAddr[12]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[12]), .ZN(n_0_0_10)); + INV_X1_LVT i_0_0_20 (.A(n_0_0_10), .ZN(n_0_10)); + INV_X1_LVT i_0_0_172 (.A(clk), .ZN(n_0_76)); + DFF_X1_LVT \mem_addr_reg[10] (.D(n_0_10), .CK(n_0_76), .Q(mem_addr[10]), + .QN()); + AOI22_X1_LVT i_0_0_19 (.A1(DAddr[11]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[11]), .ZN(n_0_0_9)); + INV_X1_LVT i_0_0_18 (.A(n_0_0_9), .ZN(n_0_9)); + DFF_X1_LVT \mem_addr_reg[9] (.D(n_0_9), .CK(n_0_76), .Q(mem_addr[9]), .QN()); + AOI22_X1_LVT i_0_0_17 (.A1(DAddr[10]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[10]), .ZN(n_0_0_8)); + INV_X1_LVT i_0_0_16 (.A(n_0_0_8), .ZN(n_0_8)); + DFF_X1_LVT \mem_addr_reg[8] (.D(n_0_8), .CK(n_0_76), .Q(mem_addr[8]), .QN()); + AOI22_X1_LVT i_0_0_15 (.A1(DAddr[9]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[9]), .ZN(n_0_0_7)); + INV_X1_LVT i_0_0_14 (.A(n_0_0_7), .ZN(n_0_7)); + DFF_X1_LVT \mem_addr_reg[7] (.D(n_0_7), .CK(n_0_76), .Q(mem_addr[7]), .QN()); + AOI22_X1_LVT i_0_0_13 (.A1(DAddr[8]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[8]), .ZN(n_0_0_6)); + INV_X1_LVT i_0_0_12 (.A(n_0_0_6), .ZN(n_0_6)); + DFF_X1_LVT \mem_addr_reg[6] (.D(n_0_6), .CK(n_0_76), .Q(mem_addr[6]), .QN()); + AOI22_X1_LVT i_0_0_11 (.A1(DAddr[7]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[7]), .ZN(n_0_0_5)); + INV_X1_LVT i_0_0_10 (.A(n_0_0_5), .ZN(n_0_5)); + DFF_X1_LVT \mem_addr_reg[5] (.D(n_0_5), .CK(n_0_76), .Q(mem_addr[5]), .QN()); + AOI22_X1_LVT i_0_0_9 (.A1(DAddr[6]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[6]), .ZN(n_0_0_4)); + INV_X1_LVT i_0_0_8 (.A(n_0_0_4), .ZN(n_0_4)); + DFF_X1_LVT \mem_addr_reg[4] (.D(n_0_4), .CK(n_0_76), .Q(mem_addr[4]), .QN()); + AOI22_X1_LVT i_0_0_7 (.A1(DAddr[5]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[5]), .ZN(n_0_0_3)); + INV_X1_LVT i_0_0_6 (.A(n_0_0_3), .ZN(n_0_3)); + DFF_X1_LVT \mem_addr_reg[3] (.D(n_0_3), .CK(n_0_76), .Q(mem_addr[3]), .QN()); + AOI22_X1_LVT i_0_0_5 (.A1(DAddr[4]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[4]), .ZN(n_0_0_2)); + INV_X1_LVT i_0_0_4 (.A(n_0_0_2), .ZN(n_0_2)); + DFF_X1_LVT \mem_addr_reg[2] (.D(n_0_2), .CK(n_0_76), .Q(mem_addr[2]), .QN()); + AOI22_X1_LVT i_0_0_3 (.A1(DAddr[3]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[3]), .ZN(n_0_0_1)); + INV_X1_LVT i_0_0_2 (.A(n_0_0_1), .ZN(n_0_1)); + DFF_X1_LVT \mem_addr_reg[1] (.D(n_0_1), .CK(n_0_76), .Q(mem_addr[1]), .QN()); + AOI22_X1_LVT i_0_0_1 (.A1(DAddr[2]), .A2(n_0_0_88), .B1(n_0_0_11), .B2( + IAddr[2]), .ZN(n_0_0_0)); + INV_X1_LVT i_0_0_0 (.A(n_0_0_0), .ZN(n_0_0)); + DFF_X1_LVT \mem_addr_reg[0] (.D(n_0_0), .CK(n_0_76), .Q(mem_addr[0]), .QN()); + NOR2_X1_LVT i_0_0_162 (.A1(DWidth[1]), .A2(DAddr[1]), .ZN(n_0_0_87)); + NOR2_X1_LVT i_0_0_158 (.A1(DWidth[0]), .A2(DAddr[0]), .ZN(n_0_0_83)); + AND2_X1_LVT i_0_0_157 (.A1(n_0_0_87), .A2(n_0_0_83), .ZN(n_0_0_82)); + AND2_X1_LVT i_0_0_156 (.A1(n_0_0_88), .A2(n_0_0_82), .ZN(n_0_0_81)); + INV_X1_LVT i_0_0_173 (.A(n_0_0_88), .ZN(n_0_0_95)); + INV_X1_LVT i_0_0_169 (.A(DWidth[1]), .ZN(n_0_0_93)); + NOR3_X1_LVT i_0_0_155 (.A1(n_0_0_95), .A2(DWidth[0]), .A3(n_0_0_93), .ZN( + n_0_0_80)); + AOI22_X1_LVT i_0_0_154 (.A1(DWData[7]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[31]), .ZN(n_0_0_79)); + NAND2_X1_LVT i_0_0_168 (.A1(DWidth[0]), .A2(DWidth[1]), .ZN(n_0_43)); + INV_X1_LVT i_0_0_167 (.A(n_0_43), .ZN(n_0_0_92)); + NOR2_X1_LVT i_0_0_160 (.A1(n_0_0_95), .A2(n_0_0_92), .ZN(n_0_0_85)); + NAND2_X1_LVT i_0_0_161 (.A1(n_0_0_93), .A2(DAddr[1]), .ZN(n_0_0_86)); + NOR2_X1_LVT i_0_0_166 (.A1(DWidth[0]), .A2(DWidth[1]), .ZN(n_0_0_91)); + NAND2_X1_LVT i_0_0_164 (.A1(DAddr[0]), .A2(n_0_0_91), .ZN(n_0_0_89)); + NAND3_X1_LVT i_0_0_159 (.A1(n_0_0_85), .A2(n_0_0_86), .A3(n_0_0_89), .ZN( + n_0_0_84)); + INV_X1_LVT i_0_0_170 (.A(DWidth[0]), .ZN(n_0_0_94)); + NOR2_X1_LVT i_0_0_153 (.A1(n_0_0_94), .A2(DAddr[1]), .ZN(n_0_0_78)); + AND3_X1_LVT i_0_0_152 (.A1(n_0_0_88), .A2(n_0_0_78), .A3(n_0_0_93), .ZN( + n_0_0_77)); + AOI22_X1_LVT i_0_0_151 (.A1(n_0_0_84), .A2(mem_wdata[31]), .B1(DWData[15]), + .B2(n_0_0_77), .ZN(n_0_0_76)); + NAND2_X1_LVT i_0_0_150 (.A1(n_0_0_79), .A2(n_0_0_76), .ZN(n_0_75)); + DFF_X1_LVT \mem_wdata_reg[31] (.D(n_0_75), .CK(n_0_76), .Q(mem_wdata[31]), + .QN()); + AOI22_X1_LVT i_0_0_149 (.A1(DWData[6]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[30]), .ZN(n_0_0_75)); + AOI22_X1_LVT i_0_0_148 (.A1(n_0_0_84), .A2(mem_wdata[30]), .B1(DWData[14]), + .B2(n_0_0_77), .ZN(n_0_0_74)); + NAND2_X1_LVT i_0_0_147 (.A1(n_0_0_75), .A2(n_0_0_74), .ZN(n_0_74)); + DFF_X1_LVT \mem_wdata_reg[30] (.D(n_0_74), .CK(n_0_76), .Q(mem_wdata[30]), + .QN()); + AOI22_X1_LVT i_0_0_146 (.A1(DWData[5]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[29]), .ZN(n_0_0_73)); + AOI22_X1_LVT i_0_0_145 (.A1(n_0_0_84), .A2(mem_wdata[29]), .B1(DWData[13]), + .B2(n_0_0_77), .ZN(n_0_0_72)); + NAND2_X1_LVT i_0_0_144 (.A1(n_0_0_73), .A2(n_0_0_72), .ZN(n_0_73)); + DFF_X1_LVT \mem_wdata_reg[29] (.D(n_0_73), .CK(n_0_76), .Q(mem_wdata[29]), + .QN()); + AOI22_X1_LVT i_0_0_143 (.A1(DWData[4]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[28]), .ZN(n_0_0_71)); + AOI22_X1_LVT i_0_0_142 (.A1(n_0_0_84), .A2(mem_wdata[28]), .B1(DWData[12]), + .B2(n_0_0_77), .ZN(n_0_0_70)); + NAND2_X1_LVT i_0_0_141 (.A1(n_0_0_71), .A2(n_0_0_70), .ZN(n_0_72)); + DFF_X1_LVT \mem_wdata_reg[28] (.D(n_0_72), .CK(n_0_76), .Q(mem_wdata[28]), + .QN()); + AOI22_X1_LVT i_0_0_140 (.A1(DWData[3]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[27]), .ZN(n_0_0_69)); + AOI22_X1_LVT i_0_0_139 (.A1(n_0_0_84), .A2(mem_wdata[27]), .B1(DWData[11]), + .B2(n_0_0_77), .ZN(n_0_0_68)); + NAND2_X1_LVT i_0_0_138 (.A1(n_0_0_69), .A2(n_0_0_68), .ZN(n_0_71)); + DFF_X1_LVT \mem_wdata_reg[27] (.D(n_0_71), .CK(n_0_76), .Q(mem_wdata[27]), + .QN()); + AOI22_X1_LVT i_0_0_137 (.A1(DWData[2]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[26]), .ZN(n_0_0_67)); + AOI22_X1_LVT i_0_0_136 (.A1(n_0_0_84), .A2(mem_wdata[26]), .B1(DWData[10]), + .B2(n_0_0_77), .ZN(n_0_0_66)); + NAND2_X1_LVT i_0_0_135 (.A1(n_0_0_67), .A2(n_0_0_66), .ZN(n_0_70)); + DFF_X1_LVT \mem_wdata_reg[26] (.D(n_0_70), .CK(n_0_76), .Q(mem_wdata[26]), + .QN()); + AOI22_X1_LVT i_0_0_134 (.A1(DWData[1]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[25]), .ZN(n_0_0_65)); + AOI22_X1_LVT i_0_0_133 (.A1(n_0_0_84), .A2(mem_wdata[25]), .B1(DWData[9]), + .B2(n_0_0_77), .ZN(n_0_0_64)); + NAND2_X1_LVT i_0_0_132 (.A1(n_0_0_65), .A2(n_0_0_64), .ZN(n_0_69)); + DFF_X1_LVT \mem_wdata_reg[25] (.D(n_0_69), .CK(n_0_76), .Q(mem_wdata[25]), + .QN()); + AOI22_X1_LVT i_0_0_131 (.A1(DWData[0]), .A2(n_0_0_81), .B1(n_0_0_80), + .B2(DWData[24]), .ZN(n_0_0_63)); + AOI22_X1_LVT i_0_0_130 (.A1(n_0_0_84), .A2(mem_wdata[24]), .B1(DWData[8]), + .B2(n_0_0_77), .ZN(n_0_0_62)); + NAND2_X1_LVT i_0_0_129 (.A1(n_0_0_63), .A2(n_0_0_62), .ZN(n_0_68)); + DFF_X1_LVT \mem_wdata_reg[24] (.D(n_0_68), .CK(n_0_76), .Q(mem_wdata[24]), + .QN()); + NOR4_X1_LVT i_0_0_127 (.A1(n_0_0_95), .A2(n_0_0_83), .A3(DWidth[1]), .A4( + DAddr[1]), .ZN(n_0_0_60)); + INV_X1_LVT i_0_0_165 (.A(n_0_0_91), .ZN(n_0_0_90)); + OAI211_X1_LVT i_0_0_128 (.A(n_0_0_85), .B(n_0_0_86), .C1(n_0_0_90), .C2( + DAddr[0]), .ZN(n_0_0_61)); + AOI222_X1_LVT i_0_0_126 (.A1(DWData[7]), .A2(n_0_0_60), .B1(mem_wdata[23]), + .B2(n_0_0_61), .C1(DWData[23]), .C2(n_0_0_80), .ZN(n_0_0_59)); + INV_X1_LVT i_0_0_125 (.A(n_0_0_59), .ZN(n_0_67)); + DFF_X1_LVT \mem_wdata_reg[23] (.D(n_0_67), .CK(n_0_76), .Q(mem_wdata[23]), + .QN()); + AOI222_X1_LVT i_0_0_124 (.A1(DWData[6]), .A2(n_0_0_60), .B1(mem_wdata[22]), + .B2(n_0_0_61), .C1(DWData[22]), .C2(n_0_0_80), .ZN(n_0_0_58)); + INV_X1_LVT i_0_0_123 (.A(n_0_0_58), .ZN(n_0_66)); + DFF_X1_LVT \mem_wdata_reg[22] (.D(n_0_66), .CK(n_0_76), .Q(mem_wdata[22]), + .QN()); + AOI222_X1_LVT i_0_0_122 (.A1(DWData[5]), .A2(n_0_0_60), .B1(mem_wdata[21]), + .B2(n_0_0_61), .C1(DWData[21]), .C2(n_0_0_80), .ZN(n_0_0_57)); + INV_X1_LVT i_0_0_121 (.A(n_0_0_57), .ZN(n_0_44)); + DFF_X1_LVT \mem_wdata_reg[21] (.D(n_0_44), .CK(n_0_76), .Q(mem_wdata[21]), + .QN()); + AOI222_X1_LVT i_0_0_120 (.A1(DWData[4]), .A2(n_0_0_60), .B1(mem_wdata[20]), + .B2(n_0_0_61), .C1(DWData[20]), .C2(n_0_0_80), .ZN(n_0_0_56)); + INV_X1_LVT i_0_0_119 (.A(n_0_0_56), .ZN(n_0_45)); + DFF_X1_LVT \mem_wdata_reg[20] (.D(n_0_45), .CK(n_0_76), .Q(mem_wdata[20]), + .QN()); + AOI222_X1_LVT i_0_0_118 (.A1(DWData[3]), .A2(n_0_0_60), .B1(mem_wdata[19]), + .B2(n_0_0_61), .C1(DWData[19]), .C2(n_0_0_80), .ZN(n_0_0_55)); + INV_X1_LVT i_0_0_117 (.A(n_0_0_55), .ZN(n_0_46)); + DFF_X1_LVT \mem_wdata_reg[19] (.D(n_0_46), .CK(n_0_76), .Q(mem_wdata[19]), + .QN()); + AOI222_X1_LVT i_0_0_116 (.A1(DWData[2]), .A2(n_0_0_60), .B1(mem_wdata[18]), + .B2(n_0_0_61), .C1(DWData[18]), .C2(n_0_0_80), .ZN(n_0_0_54)); + INV_X1_LVT i_0_0_115 (.A(n_0_0_54), .ZN(n_0_47)); + DFF_X1_LVT \mem_wdata_reg[18] (.D(n_0_47), .CK(n_0_76), .Q(mem_wdata[18]), + .QN()); + AOI222_X1_LVT i_0_0_114 (.A1(DWData[1]), .A2(n_0_0_60), .B1(mem_wdata[17]), + .B2(n_0_0_61), .C1(DWData[17]), .C2(n_0_0_80), .ZN(n_0_0_53)); + INV_X1_LVT i_0_0_113 (.A(n_0_0_53), .ZN(n_0_48)); + DFF_X1_LVT \mem_wdata_reg[17] (.D(n_0_48), .CK(n_0_76), .Q(mem_wdata[17]), + .QN()); + AOI222_X1_LVT i_0_0_112 (.A1(DWData[0]), .A2(n_0_0_60), .B1(mem_wdata[16]), + .B2(n_0_0_61), .C1(DWData[16]), .C2(n_0_0_80), .ZN(n_0_0_52)); + INV_X1_LVT i_0_0_111 (.A(n_0_0_52), .ZN(n_0_49)); + DFF_X1_LVT \mem_wdata_reg[16] (.D(n_0_49), .CK(n_0_76), .Q(mem_wdata[16]), + .QN()); + NOR4_X1_LVT i_0_0_110 (.A1(n_0_0_95), .A2(n_0_0_87), .A3(n_0_0_92), .A4( + n_0_0_91), .ZN(n_0_0_51)); + NOR3_X1_LVT i_0_0_109 (.A1(n_0_0_86), .A2(DAddr[0]), .A3(DWidth[0]), .ZN( + n_0_0_50)); + AND2_X1_LVT i_0_0_108 (.A1(n_0_0_88), .A2(n_0_0_50), .ZN(n_0_0_49)); + OAI211_X1_LVT i_0_0_107 (.A(n_0_0_85), .B(n_0_0_89), .C1(DAddr[1]), .C2( + DWidth[1]), .ZN(n_0_0_48)); + AOI222_X1_LVT i_0_0_106 (.A1(DWData[15]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[7]), .C1(n_0_0_48), .C2(mem_wdata[15]), .ZN(n_0_0_47)); + INV_X1_LVT i_0_0_105 (.A(n_0_0_47), .ZN(n_0_50)); + DFF_X1_LVT \mem_wdata_reg[15] (.D(n_0_50), .CK(n_0_76), .Q(mem_wdata[15]), + .QN()); + AOI222_X1_LVT i_0_0_104 (.A1(DWData[14]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[6]), .C1(n_0_0_48), .C2(mem_wdata[14]), .ZN(n_0_0_46)); + INV_X1_LVT i_0_0_103 (.A(n_0_0_46), .ZN(n_0_51)); + DFF_X1_LVT \mem_wdata_reg[14] (.D(n_0_51), .CK(n_0_76), .Q(mem_wdata[14]), + .QN()); + AOI222_X1_LVT i_0_0_102 (.A1(DWData[13]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[5]), .C1(n_0_0_48), .C2(mem_wdata[13]), .ZN(n_0_0_45)); + INV_X1_LVT i_0_0_101 (.A(n_0_0_45), .ZN(n_0_52)); + DFF_X1_LVT \mem_wdata_reg[13] (.D(n_0_52), .CK(n_0_76), .Q(mem_wdata[13]), + .QN()); + AOI222_X1_LVT i_0_0_100 (.A1(DWData[12]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[4]), .C1(n_0_0_48), .C2(mem_wdata[12]), .ZN(n_0_0_44)); + INV_X1_LVT i_0_0_99 (.A(n_0_0_44), .ZN(n_0_53)); + DFF_X1_LVT \mem_wdata_reg[12] (.D(n_0_53), .CK(n_0_76), .Q(mem_wdata[12]), + .QN()); + AOI222_X1_LVT i_0_0_98 (.A1(DWData[11]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[3]), .C1(n_0_0_48), .C2(mem_wdata[11]), .ZN(n_0_0_43)); + INV_X1_LVT i_0_0_97 (.A(n_0_0_43), .ZN(n_0_54)); + DFF_X1_LVT \mem_wdata_reg[11] (.D(n_0_54), .CK(n_0_76), .Q(mem_wdata[11]), + .QN()); + AOI222_X1_LVT i_0_0_96 (.A1(DWData[10]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[2]), .C1(n_0_0_48), .C2(mem_wdata[10]), .ZN(n_0_0_42)); + INV_X1_LVT i_0_0_95 (.A(n_0_0_42), .ZN(n_0_55)); + DFF_X1_LVT \mem_wdata_reg[10] (.D(n_0_55), .CK(n_0_76), .Q(mem_wdata[10]), + .QN()); + AOI222_X1_LVT i_0_0_94 (.A1(DWData[9]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[1]), .C1(n_0_0_48), .C2(mem_wdata[9]), .ZN(n_0_0_41)); + INV_X1_LVT i_0_0_93 (.A(n_0_0_41), .ZN(n_0_56)); + DFF_X1_LVT \mem_wdata_reg[9] (.D(n_0_56), .CK(n_0_76), .Q(mem_wdata[9]), + .QN()); + AOI222_X1_LVT i_0_0_92 (.A1(DWData[8]), .A2(n_0_0_51), .B1(n_0_0_49), + .B2(DWData[0]), .C1(n_0_0_48), .C2(mem_wdata[8]), .ZN(n_0_0_40)); + INV_X1_LVT i_0_0_91 (.A(n_0_0_40), .ZN(n_0_57)); + DFF_X1_LVT \mem_wdata_reg[8] (.D(n_0_57), .CK(n_0_76), .Q(mem_wdata[8]), + .QN()); + AOI21_X1_LVT i_0_0_90 (.A(n_0_0_87), .B1(n_0_0_83), .B2(n_0_0_93), .ZN( + n_0_0_39)); + NAND2_X1_LVT i_0_0_89 (.A1(n_0_0_85), .A2(n_0_0_39), .ZN(n_0_0_38)); + MUX2_X1_LVT i_0_0_88 (.A(DWData[7]), .B(mem_wdata[7]), .S(n_0_0_38), .Z( + n_0_58)); + DFF_X1_LVT \mem_wdata_reg[7] (.D(n_0_58), .CK(n_0_76), .Q(mem_wdata[7]), + .QN()); + MUX2_X1_LVT i_0_0_87 (.A(DWData[6]), .B(mem_wdata[6]), .S(n_0_0_38), .Z( + n_0_59)); + DFF_X1_LVT \mem_wdata_reg[6] (.D(n_0_59), .CK(n_0_76), .Q(mem_wdata[6]), + .QN()); + MUX2_X1_LVT i_0_0_86 (.A(DWData[5]), .B(mem_wdata[5]), .S(n_0_0_38), .Z( + n_0_60)); + DFF_X1_LVT \mem_wdata_reg[5] (.D(n_0_60), .CK(n_0_76), .Q(mem_wdata[5]), + .QN()); + MUX2_X1_LVT i_0_0_85 (.A(DWData[4]), .B(mem_wdata[4]), .S(n_0_0_38), .Z( + n_0_61)); + DFF_X1_LVT \mem_wdata_reg[4] (.D(n_0_61), .CK(n_0_76), .Q(mem_wdata[4]), + .QN()); + MUX2_X1_LVT i_0_0_84 (.A(DWData[3]), .B(mem_wdata[3]), .S(n_0_0_38), .Z( + n_0_62)); + DFF_X1_LVT \mem_wdata_reg[3] (.D(n_0_62), .CK(n_0_76), .Q(mem_wdata[3]), + .QN()); + MUX2_X1_LVT i_0_0_83 (.A(DWData[2]), .B(mem_wdata[2]), .S(n_0_0_38), .Z( + n_0_63)); + DFF_X1_LVT \mem_wdata_reg[2] (.D(n_0_63), .CK(n_0_76), .Q(mem_wdata[2]), + .QN()); + MUX2_X1_LVT i_0_0_82 (.A(DWData[1]), .B(mem_wdata[1]), .S(n_0_0_38), .Z( + n_0_64)); + DFF_X1_LVT \mem_wdata_reg[1] (.D(n_0_64), .CK(n_0_76), .Q(mem_wdata[1]), + .QN()); + MUX2_X1_LVT i_0_0_81 (.A(DWData[0]), .B(mem_wdata[0]), .S(n_0_0_38), .Z( + n_0_65)); + DFF_X1_LVT \mem_wdata_reg[0] (.D(n_0_65), .CK(n_0_76), .Q(mem_wdata[0]), + .QN()); + MemGen_32_11 RAM (.chip_en(), .clock(clk), .addr(mem_addr), .rd_data( + mem_rdata), .rd_en(n_0), .wr_en(DWE), .wr_data(mem_wdata)); + DFF_X1_LVT \drTmp_reg[31] (.D(mem_rdata[31]), .CK(n_0_76), .Q(drTmp[31]), + .QN()); + AND2_X1_LVT i_0_0_80 (.A1(DWidth[1]), .A2(drTmp[31]), .ZN(n_0_42)); + DLH_X1_LVT \DRData[31] (.D(n_0_42), .G(n_0_43), .Q(DRData[31])); + DFF_X1_LVT \drTmp_reg[30] (.D(mem_rdata[30]), .CK(n_0_76), .Q(drTmp[30]), + .QN()); + AND2_X1_LVT i_0_0_79 (.A1(DWidth[1]), .A2(drTmp[30]), .ZN(n_0_41)); + DLH_X1_LVT \DRData[30] (.D(n_0_41), .G(n_0_43), .Q(DRData[30])); + DFF_X1_LVT \drTmp_reg[29] (.D(mem_rdata[29]), .CK(n_0_76), .Q(drTmp[29]), + .QN()); + AND2_X1_LVT i_0_0_78 (.A1(DWidth[1]), .A2(drTmp[29]), .ZN(n_0_40)); + DLH_X1_LVT \DRData[29] (.D(n_0_40), .G(n_0_43), .Q(DRData[29])); + DFF_X1_LVT \drTmp_reg[28] (.D(mem_rdata[28]), .CK(n_0_76), .Q(drTmp[28]), + .QN()); + AND2_X1_LVT i_0_0_77 (.A1(DWidth[1]), .A2(drTmp[28]), .ZN(n_0_39)); + DLH_X1_LVT \DRData[28] (.D(n_0_39), .G(n_0_43), .Q(DRData[28])); + DFF_X1_LVT \drTmp_reg[27] (.D(mem_rdata[27]), .CK(n_0_76), .Q(drTmp[27]), + .QN()); + AND2_X1_LVT i_0_0_76 (.A1(DWidth[1]), .A2(drTmp[27]), .ZN(n_0_38)); + DLH_X1_LVT \DRData[27] (.D(n_0_38), .G(n_0_43), .Q(DRData[27])); + DFF_X1_LVT \drTmp_reg[26] (.D(mem_rdata[26]), .CK(n_0_76), .Q(drTmp[26]), + .QN()); + AND2_X1_LVT i_0_0_75 (.A1(DWidth[1]), .A2(drTmp[26]), .ZN(n_0_37)); + DLH_X1_LVT \DRData[26] (.D(n_0_37), .G(n_0_43), .Q(DRData[26])); + DFF_X1_LVT \drTmp_reg[25] (.D(mem_rdata[25]), .CK(n_0_76), .Q(drTmp[25]), + .QN()); + AND2_X1_LVT i_0_0_74 (.A1(DWidth[1]), .A2(drTmp[25]), .ZN(n_0_36)); + DLH_X1_LVT \DRData[25] (.D(n_0_36), .G(n_0_43), .Q(DRData[25])); + DFF_X1_LVT \drTmp_reg[24] (.D(mem_rdata[24]), .CK(n_0_76), .Q(drTmp[24]), + .QN()); + AND2_X1_LVT i_0_0_73 (.A1(DWidth[1]), .A2(drTmp[24]), .ZN(n_0_35)); + DLH_X1_LVT \DRData[24] (.D(n_0_35), .G(n_0_43), .Q(DRData[24])); + DFF_X1_LVT \drTmp_reg[23] (.D(mem_rdata[23]), .CK(n_0_76), .Q(drTmp[23]), + .QN()); + AND2_X1_LVT i_0_0_72 (.A1(DWidth[1]), .A2(drTmp[23]), .ZN(n_0_34)); + DLH_X1_LVT \DRData[23] (.D(n_0_34), .G(n_0_43), .Q(DRData[23])); + DFF_X1_LVT \drTmp_reg[22] (.D(mem_rdata[22]), .CK(n_0_76), .Q(drTmp[22]), + .QN()); + AND2_X1_LVT i_0_0_71 (.A1(DWidth[1]), .A2(drTmp[22]), .ZN(n_0_33)); + DLH_X1_LVT \DRData[22] (.D(n_0_33), .G(n_0_43), .Q(DRData[22])); + DFF_X1_LVT \drTmp_reg[21] (.D(mem_rdata[21]), .CK(n_0_76), .Q(drTmp[21]), + .QN()); + AND2_X1_LVT i_0_0_70 (.A1(DWidth[1]), .A2(drTmp[21]), .ZN(n_0_32)); + DLH_X1_LVT \DRData[21] (.D(n_0_32), .G(n_0_43), .Q(DRData[21])); + DFF_X1_LVT \drTmp_reg[20] (.D(mem_rdata[20]), .CK(n_0_76), .Q(drTmp[20]), + .QN()); + AND2_X1_LVT i_0_0_69 (.A1(DWidth[1]), .A2(drTmp[20]), .ZN(n_0_31)); + DLH_X1_LVT \DRData[20] (.D(n_0_31), .G(n_0_43), .Q(DRData[20])); + DFF_X1_LVT \drTmp_reg[19] (.D(mem_rdata[19]), .CK(n_0_76), .Q(drTmp[19]), + .QN()); + AND2_X1_LVT i_0_0_68 (.A1(DWidth[1]), .A2(drTmp[19]), .ZN(n_0_30)); + DLH_X1_LVT \DRData[19] (.D(n_0_30), .G(n_0_43), .Q(DRData[19])); + DFF_X1_LVT \drTmp_reg[18] (.D(mem_rdata[18]), .CK(n_0_76), .Q(drTmp[18]), + .QN()); + AND2_X1_LVT i_0_0_67 (.A1(DWidth[1]), .A2(drTmp[18]), .ZN(n_0_29)); + DLH_X1_LVT \DRData[18] (.D(n_0_29), .G(n_0_43), .Q(DRData[18])); + DFF_X1_LVT \drTmp_reg[17] (.D(mem_rdata[17]), .CK(n_0_76), .Q(drTmp[17]), + .QN()); + AND2_X1_LVT i_0_0_66 (.A1(DWidth[1]), .A2(drTmp[17]), .ZN(n_0_28)); + DLH_X1_LVT \DRData[17] (.D(n_0_28), .G(n_0_43), .Q(DRData[17])); + DFF_X1_LVT \drTmp_reg[16] (.D(mem_rdata[16]), .CK(n_0_76), .Q(drTmp[16]), + .QN()); + AND2_X1_LVT i_0_0_65 (.A1(DWidth[1]), .A2(drTmp[16]), .ZN(n_0_27)); + DLH_X1_LVT \DRData[16] (.D(n_0_27), .G(n_0_43), .Q(DRData[16])); + NOR2_X1_LVT i_0_0_64 (.A1(n_0_0_91), .A2(n_0_0_87), .ZN(n_0_0_37)); + DFF_X1_LVT \drTmp_reg[15] (.D(mem_rdata[15]), .CK(n_0_76), .Q(drTmp[15]), + .QN()); + AOI22_X1_LVT i_0_0_63 (.A1(drTmp[31]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[15]), .ZN(n_0_0_36)); + INV_X1_LVT i_0_0_62 (.A(n_0_0_36), .ZN(n_0_26)); + DLH_X1_LVT \DRData[15] (.D(n_0_26), .G(n_0_43), .Q(DRData[15])); + DFF_X1_LVT \drTmp_reg[14] (.D(mem_rdata[14]), .CK(n_0_76), .Q(drTmp[14]), + .QN()); + AOI22_X1_LVT i_0_0_61 (.A1(drTmp[30]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[14]), .ZN(n_0_0_35)); + INV_X1_LVT i_0_0_60 (.A(n_0_0_35), .ZN(n_0_25)); + DLH_X1_LVT \DRData[14] (.D(n_0_25), .G(n_0_43), .Q(DRData[14])); + DFF_X1_LVT \drTmp_reg[13] (.D(mem_rdata[13]), .CK(n_0_76), .Q(drTmp[13]), + .QN()); + AOI22_X1_LVT i_0_0_59 (.A1(drTmp[29]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[13]), .ZN(n_0_0_34)); + INV_X1_LVT i_0_0_58 (.A(n_0_0_34), .ZN(n_0_24)); + DLH_X1_LVT \DRData[13] (.D(n_0_24), .G(n_0_43), .Q(DRData[13])); + DFF_X1_LVT \drTmp_reg[12] (.D(mem_rdata[12]), .CK(n_0_76), .Q(drTmp[12]), + .QN()); + AOI22_X1_LVT i_0_0_57 (.A1(drTmp[28]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[12]), .ZN(n_0_0_33)); + INV_X1_LVT i_0_0_56 (.A(n_0_0_33), .ZN(n_0_23)); + DLH_X1_LVT \DRData[12] (.D(n_0_23), .G(n_0_43), .Q(DRData[12])); + DFF_X1_LVT \drTmp_reg[11] (.D(mem_rdata[11]), .CK(n_0_76), .Q(drTmp[11]), + .QN()); + AOI22_X1_LVT i_0_0_55 (.A1(drTmp[27]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[11]), .ZN(n_0_0_32)); + INV_X1_LVT i_0_0_54 (.A(n_0_0_32), .ZN(n_0_22)); + DLH_X1_LVT \DRData[11] (.D(n_0_22), .G(n_0_43), .Q(DRData[11])); + DFF_X1_LVT \drTmp_reg[10] (.D(mem_rdata[10]), .CK(n_0_76), .Q(drTmp[10]), + .QN()); + AOI22_X1_LVT i_0_0_53 (.A1(drTmp[26]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[10]), .ZN(n_0_0_31)); + INV_X1_LVT i_0_0_52 (.A(n_0_0_31), .ZN(n_0_21)); + DLH_X1_LVT \DRData[10] (.D(n_0_21), .G(n_0_43), .Q(DRData[10])); + DFF_X1_LVT \drTmp_reg[9] (.D(mem_rdata[9]), .CK(n_0_76), .Q(drTmp[9]), .QN()); + AOI22_X1_LVT i_0_0_51 (.A1(drTmp[25]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[9]), .ZN(n_0_0_30)); + INV_X1_LVT i_0_0_50 (.A(n_0_0_30), .ZN(n_0_20)); + DLH_X1_LVT \DRData[9] (.D(n_0_20), .G(n_0_43), .Q(DRData[9])); + DFF_X1_LVT \drTmp_reg[8] (.D(mem_rdata[8]), .CK(n_0_76), .Q(drTmp[8]), .QN()); + AOI22_X1_LVT i_0_0_49 (.A1(drTmp[24]), .A2(n_0_0_78), .B1(n_0_0_37), .B2( + drTmp[8]), .ZN(n_0_0_29)); + INV_X1_LVT i_0_0_48 (.A(n_0_0_29), .ZN(n_0_19)); + DLH_X1_LVT \DRData[8] (.D(n_0_19), .G(n_0_43), .Q(DRData[8])); + AOI22_X1_LVT i_0_0_46 (.A1(drTmp[31]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[15]), .ZN(n_0_0_27)); + AOI211_X1_LVT i_0_0_47 (.A(DAddr[1]), .B(n_0_0_83), .C1(n_0_0_94), .C2( + DWidth[1]), .ZN(n_0_0_28)); + DFF_X1_LVT \drTmp_reg[7] (.D(mem_rdata[7]), .CK(n_0_76), .Q(drTmp[7]), .QN()); + AOI22_X1_LVT i_0_0_45 (.A1(drTmp[23]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[7]), .ZN(n_0_0_26)); + NAND2_X1_LVT i_0_0_44 (.A1(n_0_0_27), .A2(n_0_0_26), .ZN(n_0_18)); + DLH_X1_LVT \DRData[7] (.D(n_0_18), .G(n_0_43), .Q(DRData[7])); + AOI22_X1_LVT i_0_0_43 (.A1(drTmp[30]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[14]), .ZN(n_0_0_25)); + DFF_X1_LVT \drTmp_reg[6] (.D(mem_rdata[6]), .CK(n_0_76), .Q(drTmp[6]), .QN()); + AOI22_X1_LVT i_0_0_42 (.A1(drTmp[22]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[6]), .ZN(n_0_0_24)); + NAND2_X1_LVT i_0_0_41 (.A1(n_0_0_25), .A2(n_0_0_24), .ZN(n_0_17)); + DLH_X1_LVT \DRData[6] (.D(n_0_17), .G(n_0_43), .Q(DRData[6])); + AOI22_X1_LVT i_0_0_40 (.A1(drTmp[29]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[13]), .ZN(n_0_0_23)); + DFF_X1_LVT \drTmp_reg[5] (.D(mem_rdata[5]), .CK(n_0_76), .Q(drTmp[5]), .QN()); + AOI22_X1_LVT i_0_0_39 (.A1(drTmp[21]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[5]), .ZN(n_0_0_22)); + NAND2_X1_LVT i_0_0_38 (.A1(n_0_0_23), .A2(n_0_0_22), .ZN(n_0_16)); + DLH_X1_LVT \DRData[5] (.D(n_0_16), .G(n_0_43), .Q(DRData[5])); + AOI22_X1_LVT i_0_0_37 (.A1(drTmp[28]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[12]), .ZN(n_0_0_21)); + DFF_X1_LVT \drTmp_reg[4] (.D(mem_rdata[4]), .CK(n_0_76), .Q(drTmp[4]), .QN()); + AOI22_X1_LVT i_0_0_36 (.A1(drTmp[20]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[4]), .ZN(n_0_0_20)); + NAND2_X1_LVT i_0_0_35 (.A1(n_0_0_21), .A2(n_0_0_20), .ZN(n_0_15)); + DLH_X1_LVT \DRData[4] (.D(n_0_15), .G(n_0_43), .Q(DRData[4])); + AOI22_X1_LVT i_0_0_34 (.A1(drTmp[27]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[11]), .ZN(n_0_0_19)); + DFF_X1_LVT \drTmp_reg[3] (.D(mem_rdata[3]), .CK(n_0_76), .Q(drTmp[3]), .QN()); + AOI22_X1_LVT i_0_0_33 (.A1(drTmp[19]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[3]), .ZN(n_0_0_18)); + NAND2_X1_LVT i_0_0_32 (.A1(n_0_0_19), .A2(n_0_0_18), .ZN(n_0_14)); + DLH_X1_LVT \DRData[3] (.D(n_0_14), .G(n_0_43), .Q(DRData[3])); + AOI22_X1_LVT i_0_0_31 (.A1(drTmp[26]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[10]), .ZN(n_0_0_17)); + DFF_X1_LVT \drTmp_reg[2] (.D(mem_rdata[2]), .CK(n_0_76), .Q(drTmp[2]), .QN()); + AOI22_X1_LVT i_0_0_30 (.A1(drTmp[18]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[2]), .ZN(n_0_0_16)); + NAND2_X1_LVT i_0_0_29 (.A1(n_0_0_17), .A2(n_0_0_16), .ZN(n_0_13)); + DLH_X1_LVT \DRData[2] (.D(n_0_13), .G(n_0_43), .Q(DRData[2])); + AOI22_X1_LVT i_0_0_28 (.A1(drTmp[25]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[9]), .ZN(n_0_0_15)); + DFF_X1_LVT \drTmp_reg[1] (.D(mem_rdata[1]), .CK(n_0_76), .Q(drTmp[1]), .QN()); + AOI22_X1_LVT i_0_0_27 (.A1(drTmp[17]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[1]), .ZN(n_0_0_14)); + NAND2_X1_LVT i_0_0_26 (.A1(n_0_0_15), .A2(n_0_0_14), .ZN(n_0_12)); + DLH_X1_LVT \DRData[1] (.D(n_0_12), .G(n_0_43), .Q(DRData[1])); + AOI22_X1_LVT i_0_0_25 (.A1(drTmp[24]), .A2(n_0_0_82), .B1(n_0_0_50), .B2( + drTmp[8]), .ZN(n_0_0_13)); + DFF_X1_LVT \drTmp_reg[0] (.D(mem_rdata[0]), .CK(n_0_76), .Q(drTmp[0]), .QN()); + AOI22_X1_LVT i_0_0_24 (.A1(drTmp[16]), .A2(n_0_0_28), .B1(n_0_0_39), .B2( + drTmp[0]), .ZN(n_0_0_12)); + NAND2_X1_LVT i_0_0_23 (.A1(n_0_0_13), .A2(n_0_0_12), .ZN(n_0_11)); + DLH_X1_LVT \DRData[0] (.D(n_0_11), .G(n_0_43), .Q(DRData[0])); + DFF_X1_LVT \IRData_reg[31] (.D(mem_rdata[31]), .CK(clk), .Q(IRData[31]), + .QN()); + DFF_X1_LVT \IRData_reg[30] (.D(mem_rdata[30]), .CK(clk), .Q(IRData[30]), + .QN()); + DFF_X1_LVT \IRData_reg[29] (.D(mem_rdata[29]), .CK(clk), .Q(IRData[29]), + .QN()); + DFF_X1_LVT \IRData_reg[28] (.D(mem_rdata[28]), .CK(clk), .Q(IRData[28]), + .QN()); + DFF_X1_LVT \IRData_reg[27] (.D(mem_rdata[27]), .CK(clk), .Q(IRData[27]), + .QN()); + DFF_X1_LVT \IRData_reg[26] (.D(mem_rdata[26]), .CK(clk), .Q(IRData[26]), + .QN()); + DFF_X1_LVT \IRData_reg[25] (.D(mem_rdata[25]), .CK(clk), .Q(IRData[25]), + .QN()); + DFF_X1_LVT \IRData_reg[24] (.D(mem_rdata[24]), .CK(clk), .Q(IRData[24]), + .QN()); + DFF_X1_LVT \IRData_reg[23] (.D(mem_rdata[23]), .CK(clk), .Q(IRData[23]), + .QN()); + DFF_X1_LVT \IRData_reg[22] (.D(mem_rdata[22]), .CK(clk), .Q(IRData[22]), + .QN()); + DFF_X1_LVT \IRData_reg[21] (.D(mem_rdata[21]), .CK(clk), .Q(IRData[21]), + .QN()); + DFF_X1_LVT \IRData_reg[20] (.D(mem_rdata[20]), .CK(clk), .Q(IRData[20]), + .QN()); + DFF_X1_LVT \IRData_reg[19] (.D(mem_rdata[19]), .CK(clk), .Q(IRData[19]), + .QN()); + DFF_X1_LVT \IRData_reg[18] (.D(mem_rdata[18]), .CK(clk), .Q(IRData[18]), + .QN()); + DFF_X1_LVT \IRData_reg[17] (.D(mem_rdata[17]), .CK(clk), .Q(IRData[17]), + .QN()); + DFF_X1_LVT \IRData_reg[16] (.D(mem_rdata[16]), .CK(clk), .Q(IRData[16]), + .QN()); + DFF_X1_LVT \IRData_reg[15] (.D(mem_rdata[15]), .CK(clk), .Q(IRData[15]), + .QN()); + DFF_X1_LVT \IRData_reg[14] (.D(mem_rdata[14]), .CK(clk), .Q(IRData[14]), + .QN()); + DFF_X1_LVT \IRData_reg[13] (.D(mem_rdata[13]), .CK(clk), .Q(IRData[13]), + .QN()); + DFF_X1_LVT \IRData_reg[12] (.D(mem_rdata[12]), .CK(clk), .Q(IRData[12]), + .QN()); + DFF_X1_LVT \IRData_reg[11] (.D(mem_rdata[11]), .CK(clk), .Q(IRData[11]), + .QN()); + DFF_X1_LVT \IRData_reg[10] (.D(mem_rdata[10]), .CK(clk), .Q(IRData[10]), + .QN()); + DFF_X1_LVT \IRData_reg[9] (.D(mem_rdata[9]), .CK(clk), .Q(IRData[9]), .QN()); + DFF_X1_LVT \IRData_reg[8] (.D(mem_rdata[8]), .CK(clk), .Q(IRData[8]), .QN()); + DFF_X1_LVT \IRData_reg[7] (.D(mem_rdata[7]), .CK(clk), .Q(IRData[7]), .QN()); + DFF_X1_LVT \IRData_reg[6] (.D(mem_rdata[6]), .CK(clk), .Q(IRData[6]), .QN()); + DFF_X1_LVT \IRData_reg[5] (.D(mem_rdata[5]), .CK(clk), .Q(IRData[5]), .QN()); + DFF_X1_LVT \IRData_reg[4] (.D(mem_rdata[4]), .CK(clk), .Q(IRData[4]), .QN()); + DFF_X1_LVT \IRData_reg[3] (.D(mem_rdata[3]), .CK(clk), .Q(IRData[3]), .QN()); + DFF_X1_LVT \IRData_reg[2] (.D(mem_rdata[2]), .CK(clk), .Q(IRData[2]), .QN()); + DFF_X1_LVT \IRData_reg[1] (.D(mem_rdata[1]), .CK(clk), .Q(IRData[1]), .QN()); + DFF_X1_LVT \IRData_reg[0] (.D(mem_rdata[0]), .CK(clk), .Q(IRData[0]), .QN()); +endmodule + +module datapathS__0_28(b_imm, CurrentPC, p_0); + input [31:0]b_imm; + input [31:0]CurrentPC; + output [31:0]p_0; + + INV_X1_LVT i_1 (.A(CurrentPC[13]), .ZN(n_1)); + XNOR2_X1_LVT i_32 (.A(CurrentPC[31]), .B(n_1), .ZN(n_32)); + INV_X1_LVT i_0 (.A(b_imm[12]), .ZN(n_0)); + HA_X1_LVT i_2 (.A(b_imm[1]), .B(CurrentPC[1]), .CO(n_2), .S(p_0[1])); + FA_X1_LVT i_3 (.A(b_imm[2]), .B(CurrentPC[2]), .CI(n_2), .CO(n_3), .S(p_0[2])); + FA_X1_LVT i_4 (.A(b_imm[3]), .B(CurrentPC[3]), .CI(n_3), .CO(n_4), .S(p_0[3])); + FA_X1_LVT i_5 (.A(b_imm[4]), .B(CurrentPC[4]), .CI(n_4), .CO(n_5), .S(p_0[4])); + FA_X1_LVT i_6 (.A(b_imm[5]), .B(CurrentPC[5]), .CI(n_5), .CO(n_6), .S(p_0[5])); + FA_X1_LVT i_7 (.A(b_imm[6]), .B(CurrentPC[6]), .CI(n_6), .CO(n_7), .S(p_0[6])); + FA_X1_LVT i_8 (.A(b_imm[7]), .B(CurrentPC[7]), .CI(n_7), .CO(n_8), .S(p_0[7])); + FA_X1_LVT i_9 (.A(b_imm[8]), .B(CurrentPC[8]), .CI(n_8), .CO(n_9), .S(p_0[8])); + FA_X1_LVT i_10 (.A(b_imm[9]), .B(CurrentPC[9]), .CI(n_9), .CO(n_10), .S( + p_0[9])); + FA_X1_LVT i_11 (.A(b_imm[10]), .B(CurrentPC[10]), .CI(n_10), .CO(n_11), + .S(p_0[10])); + FA_X1_LVT i_12 (.A(b_imm[11]), .B(CurrentPC[11]), .CI(n_11), .CO(n_12), + .S(p_0[11])); + FA_X1_LVT i_13 (.A(CurrentPC[12]), .B(b_imm[12]), .CI(n_12), .CO(n_13), + .S(p_0[12])); + FA_X1_LVT i_14 (.A(n_0), .B(n_1), .CI(n_13), .CO(n_14), .S(p_0[13])); + FA_X1_LVT i_15 (.A(CurrentPC[14]), .B(n_1), .CI(n_14), .CO(n_15), .S(p_0[14])); + FA_X1_LVT i_16 (.A(CurrentPC[15]), .B(n_1), .CI(n_15), .CO(n_16), .S(p_0[15])); + FA_X1_LVT i_17 (.A(CurrentPC[16]), .B(n_1), .CI(n_16), .CO(n_17), .S(p_0[16])); + FA_X1_LVT i_18 (.A(CurrentPC[17]), .B(n_1), .CI(n_17), .CO(n_18), .S(p_0[17])); + FA_X1_LVT i_19 (.A(CurrentPC[18]), .B(n_1), .CI(n_18), .CO(n_19), .S(p_0[18])); + FA_X1_LVT i_20 (.A(CurrentPC[19]), .B(n_1), .CI(n_19), .CO(n_20), .S(p_0[19])); + FA_X1_LVT i_21 (.A(CurrentPC[20]), .B(n_1), .CI(n_20), .CO(n_21), .S(p_0[20])); + FA_X1_LVT i_22 (.A(CurrentPC[21]), .B(n_1), .CI(n_21), .CO(n_22), .S(p_0[21])); + FA_X1_LVT i_23 (.A(CurrentPC[22]), .B(n_1), .CI(n_22), .CO(n_23), .S(p_0[22])); + FA_X1_LVT i_24 (.A(CurrentPC[23]), .B(n_1), .CI(n_23), .CO(n_24), .S(p_0[23])); + FA_X1_LVT i_25 (.A(CurrentPC[24]), .B(n_1), .CI(n_24), .CO(n_25), .S(p_0[24])); + FA_X1_LVT i_26 (.A(CurrentPC[25]), .B(n_1), .CI(n_25), .CO(n_26), .S(p_0[25])); + FA_X1_LVT i_27 (.A(CurrentPC[26]), .B(n_1), .CI(n_26), .CO(n_27), .S(p_0[26])); + FA_X1_LVT i_28 (.A(CurrentPC[27]), .B(n_1), .CI(n_27), .CO(n_28), .S(p_0[27])); + FA_X1_LVT i_29 (.A(CurrentPC[28]), .B(n_1), .CI(n_28), .CO(n_29), .S(p_0[28])); + FA_X1_LVT i_30 (.A(CurrentPC[29]), .B(n_1), .CI(n_29), .CO(n_30), .S(p_0[29])); + FA_X1_LVT i_31 (.A(CurrentPC[30]), .B(n_1), .CI(n_30), .CO(n_31), .S(p_0[30])); + XNOR2_X1_LVT i_33 (.A(n_32), .B(n_31), .ZN(p_0[31])); +endmodule + +module datapathS__0_26(j_imm, CurrentPC, p_0); + input [31:0]j_imm; + input [31:0]CurrentPC; + output [31:0]p_0; + + INV_X1_LVT i_1 (.A(CurrentPC[21]), .ZN(n_1)); + XNOR2_X1_LVT i_32 (.A(CurrentPC[31]), .B(n_1), .ZN(n_32)); + INV_X1_LVT i_0 (.A(j_imm[20]), .ZN(n_0)); + HA_X1_LVT i_2 (.A(j_imm[1]), .B(CurrentPC[1]), .CO(n_2), .S(p_0[1])); + FA_X1_LVT i_3 (.A(j_imm[2]), .B(CurrentPC[2]), .CI(n_2), .CO(n_3), .S(p_0[2])); + FA_X1_LVT i_4 (.A(j_imm[3]), .B(CurrentPC[3]), .CI(n_3), .CO(n_4), .S(p_0[3])); + FA_X1_LVT i_5 (.A(j_imm[4]), .B(CurrentPC[4]), .CI(n_4), .CO(n_5), .S(p_0[4])); + FA_X1_LVT i_6 (.A(j_imm[5]), .B(CurrentPC[5]), .CI(n_5), .CO(n_6), .S(p_0[5])); + FA_X1_LVT i_7 (.A(j_imm[6]), .B(CurrentPC[6]), .CI(n_6), .CO(n_7), .S(p_0[6])); + FA_X1_LVT i_8 (.A(j_imm[7]), .B(CurrentPC[7]), .CI(n_7), .CO(n_8), .S(p_0[7])); + FA_X1_LVT i_9 (.A(j_imm[8]), .B(CurrentPC[8]), .CI(n_8), .CO(n_9), .S(p_0[8])); + FA_X1_LVT i_10 (.A(j_imm[9]), .B(CurrentPC[9]), .CI(n_9), .CO(n_10), .S( + p_0[9])); + FA_X1_LVT i_11 (.A(j_imm[10]), .B(CurrentPC[10]), .CI(n_10), .CO(n_11), + .S(p_0[10])); + FA_X1_LVT i_12 (.A(j_imm[11]), .B(CurrentPC[11]), .CI(n_11), .CO(n_12), + .S(p_0[11])); + FA_X1_LVT i_13 (.A(j_imm[12]), .B(CurrentPC[12]), .CI(n_12), .CO(n_13), + .S(p_0[12])); + FA_X1_LVT i_14 (.A(j_imm[13]), .B(CurrentPC[13]), .CI(n_13), .CO(n_14), + .S(p_0[13])); + FA_X1_LVT i_15 (.A(j_imm[14]), .B(CurrentPC[14]), .CI(n_14), .CO(n_15), + .S(p_0[14])); + FA_X1_LVT i_16 (.A(j_imm[15]), .B(CurrentPC[15]), .CI(n_15), .CO(n_16), + .S(p_0[15])); + FA_X1_LVT i_17 (.A(j_imm[16]), .B(CurrentPC[16]), .CI(n_16), .CO(n_17), + .S(p_0[16])); + FA_X1_LVT i_18 (.A(j_imm[17]), .B(CurrentPC[17]), .CI(n_17), .CO(n_18), + .S(p_0[17])); + FA_X1_LVT i_19 (.A(j_imm[18]), .B(CurrentPC[18]), .CI(n_18), .CO(n_19), + .S(p_0[18])); + FA_X1_LVT i_20 (.A(j_imm[19]), .B(CurrentPC[19]), .CI(n_19), .CO(n_20), + .S(p_0[19])); + FA_X1_LVT i_21 (.A(CurrentPC[20]), .B(j_imm[20]), .CI(n_20), .CO(n_21), + .S(p_0[20])); + FA_X1_LVT i_22 (.A(n_0), .B(n_1), .CI(n_21), .CO(n_22), .S(p_0[21])); + FA_X1_LVT i_23 (.A(CurrentPC[22]), .B(n_1), .CI(n_22), .CO(n_23), .S(p_0[22])); + FA_X1_LVT i_24 (.A(CurrentPC[23]), .B(n_1), .CI(n_23), .CO(n_24), .S(p_0[23])); + FA_X1_LVT i_25 (.A(CurrentPC[24]), .B(n_1), .CI(n_24), .CO(n_25), .S(p_0[24])); + FA_X1_LVT i_26 (.A(CurrentPC[25]), .B(n_1), .CI(n_25), .CO(n_26), .S(p_0[25])); + FA_X1_LVT i_27 (.A(CurrentPC[26]), .B(n_1), .CI(n_26), .CO(n_27), .S(p_0[26])); + FA_X1_LVT i_28 (.A(CurrentPC[27]), .B(n_1), .CI(n_27), .CO(n_28), .S(p_0[27])); + FA_X1_LVT i_29 (.A(CurrentPC[28]), .B(n_1), .CI(n_28), .CO(n_29), .S(p_0[28])); + FA_X1_LVT i_30 (.A(CurrentPC[29]), .B(n_1), .CI(n_29), .CO(n_30), .S(p_0[29])); + FA_X1_LVT i_31 (.A(CurrentPC[30]), .B(n_1), .CI(n_30), .CO(n_31), .S(p_0[30])); + XNOR2_X1_LVT i_33 (.A(n_32), .B(n_31), .ZN(p_0[31])); +endmodule + +module datapathS__0_14(i_imm, RRs1, p_0); + input [31:0]i_imm; + input [31:0]RRs1; + output [31:0]p_0; + + INV_X1_LVT i_1 (.A(RRs1[12]), .ZN(n_1)); + XNOR2_X1_LVT i_33 (.A(RRs1[31]), .B(n_1), .ZN(n_33)); + INV_X1_LVT i_0 (.A(i_imm[11]), .ZN(n_0)); + HA_X1_LVT i_2 (.A(i_imm[0]), .B(RRs1[0]), .CO(n_2), .S(p_0[0])); + FA_X1_LVT i_3 (.A(i_imm[1]), .B(RRs1[1]), .CI(n_2), .CO(n_3), .S(p_0[1])); + FA_X1_LVT i_4 (.A(i_imm[2]), .B(RRs1[2]), .CI(n_3), .CO(n_4), .S(p_0[2])); + FA_X1_LVT i_5 (.A(i_imm[3]), .B(RRs1[3]), .CI(n_4), .CO(n_5), .S(p_0[3])); + FA_X1_LVT i_6 (.A(i_imm[4]), .B(RRs1[4]), .CI(n_5), .CO(n_6), .S(p_0[4])); + FA_X1_LVT i_7 (.A(i_imm[5]), .B(RRs1[5]), .CI(n_6), .CO(n_7), .S(p_0[5])); + FA_X1_LVT i_8 (.A(i_imm[6]), .B(RRs1[6]), .CI(n_7), .CO(n_8), .S(p_0[6])); + FA_X1_LVT i_9 (.A(i_imm[7]), .B(RRs1[7]), .CI(n_8), .CO(n_9), .S(p_0[7])); + FA_X1_LVT i_10 (.A(i_imm[8]), .B(RRs1[8]), .CI(n_9), .CO(n_10), .S(p_0[8])); + FA_X1_LVT i_11 (.A(i_imm[9]), .B(RRs1[9]), .CI(n_10), .CO(n_11), .S(p_0[9])); + FA_X1_LVT i_12 (.A(i_imm[10]), .B(RRs1[10]), .CI(n_11), .CO(n_12), .S(p_0[10])); + FA_X1_LVT i_13 (.A(RRs1[11]), .B(i_imm[11]), .CI(n_12), .CO(n_13), .S(p_0[11])); + FA_X1_LVT i_14 (.A(n_0), .B(n_1), .CI(n_13), .CO(n_14), .S(p_0[12])); + FA_X1_LVT i_15 (.A(RRs1[13]), .B(n_1), .CI(n_14), .CO(n_15), .S(p_0[13])); + FA_X1_LVT i_16 (.A(RRs1[14]), .B(n_1), .CI(n_15), .CO(n_16), .S(p_0[14])); + FA_X1_LVT i_17 (.A(RRs1[15]), .B(n_1), .CI(n_16), .CO(n_17), .S(p_0[15])); + FA_X1_LVT i_18 (.A(RRs1[16]), .B(n_1), .CI(n_17), .CO(n_18), .S(p_0[16])); + FA_X1_LVT i_19 (.A(RRs1[17]), .B(n_1), .CI(n_18), .CO(n_19), .S(p_0[17])); + FA_X1_LVT i_20 (.A(RRs1[18]), .B(n_1), .CI(n_19), .CO(n_20), .S(p_0[18])); + FA_X1_LVT i_21 (.A(RRs1[19]), .B(n_1), .CI(n_20), .CO(n_21), .S(p_0[19])); + FA_X1_LVT i_22 (.A(RRs1[20]), .B(n_1), .CI(n_21), .CO(n_22), .S(p_0[20])); + FA_X1_LVT i_23 (.A(RRs1[21]), .B(n_1), .CI(n_22), .CO(n_23), .S(p_0[21])); + FA_X1_LVT i_24 (.A(RRs1[22]), .B(n_1), .CI(n_23), .CO(n_24), .S(p_0[22])); + FA_X1_LVT i_25 (.A(RRs1[23]), .B(n_1), .CI(n_24), .CO(n_25), .S(p_0[23])); + FA_X1_LVT i_26 (.A(RRs1[24]), .B(n_1), .CI(n_25), .CO(n_26), .S(p_0[24])); + FA_X1_LVT i_27 (.A(RRs1[25]), .B(n_1), .CI(n_26), .CO(n_27), .S(p_0[25])); + FA_X1_LVT i_28 (.A(RRs1[26]), .B(n_1), .CI(n_27), .CO(n_28), .S(p_0[26])); + FA_X1_LVT i_29 (.A(RRs1[27]), .B(n_1), .CI(n_28), .CO(n_29), .S(p_0[27])); + FA_X1_LVT i_30 (.A(RRs1[28]), .B(n_1), .CI(n_29), .CO(n_30), .S(p_0[28])); + FA_X1_LVT i_31 (.A(RRs1[29]), .B(n_1), .CI(n_30), .CO(n_31), .S(p_0[29])); + FA_X1_LVT i_32 (.A(RRs1[30]), .B(n_1), .CI(n_31), .CO(n_32), .S(p_0[30])); + XNOR2_X1_LVT i_34 (.A(n_33), .B(n_32), .ZN(p_0[31])); +endmodule + +module datapathS(op2, op1, p_0); + input [31:0]op2; + input [31:0]op1; + output [31:0]p_0; + + XNOR2_X1_LVT i_31 (.A(op2[31]), .B(op1[31]), .ZN(n_31)); + HA_X1_LVT i_0 (.A(op2[0]), .B(op1[0]), .CO(n_0), .S(p_0[0])); + FA_X1_LVT i_1 (.A(op2[1]), .B(op1[1]), .CI(n_0), .CO(n_1), .S(p_0[1])); + FA_X1_LVT i_2 (.A(op2[2]), .B(op1[2]), .CI(n_1), .CO(n_2), .S(p_0[2])); + FA_X1_LVT i_3 (.A(op2[3]), .B(op1[3]), .CI(n_2), .CO(n_3), .S(p_0[3])); + FA_X1_LVT i_4 (.A(op2[4]), .B(op1[4]), .CI(n_3), .CO(n_4), .S(p_0[4])); + FA_X1_LVT i_5 (.A(op2[5]), .B(op1[5]), .CI(n_4), .CO(n_5), .S(p_0[5])); + FA_X1_LVT i_6 (.A(op2[6]), .B(op1[6]), .CI(n_5), .CO(n_6), .S(p_0[6])); + FA_X1_LVT i_7 (.A(op2[7]), .B(op1[7]), .CI(n_6), .CO(n_7), .S(p_0[7])); + FA_X1_LVT i_8 (.A(op2[8]), .B(op1[8]), .CI(n_7), .CO(n_8), .S(p_0[8])); + FA_X1_LVT i_9 (.A(op2[9]), .B(op1[9]), .CI(n_8), .CO(n_9), .S(p_0[9])); + FA_X1_LVT i_10 (.A(op2[10]), .B(op1[10]), .CI(n_9), .CO(n_10), .S(p_0[10])); + FA_X1_LVT i_11 (.A(op2[11]), .B(op1[11]), .CI(n_10), .CO(n_11), .S(p_0[11])); + FA_X1_LVT i_12 (.A(op2[12]), .B(op1[12]), .CI(n_11), .CO(n_12), .S(p_0[12])); + FA_X1_LVT i_13 (.A(op2[13]), .B(op1[13]), .CI(n_12), .CO(n_13), .S(p_0[13])); + FA_X1_LVT i_14 (.A(op2[14]), .B(op1[14]), .CI(n_13), .CO(n_14), .S(p_0[14])); + FA_X1_LVT i_15 (.A(op2[15]), .B(op1[15]), .CI(n_14), .CO(n_15), .S(p_0[15])); + FA_X1_LVT i_16 (.A(op2[16]), .B(op1[16]), .CI(n_15), .CO(n_16), .S(p_0[16])); + FA_X1_LVT i_17 (.A(op2[17]), .B(op1[17]), .CI(n_16), .CO(n_17), .S(p_0[17])); + FA_X1_LVT i_18 (.A(op2[18]), .B(op1[18]), .CI(n_17), .CO(n_18), .S(p_0[18])); + FA_X1_LVT i_19 (.A(op2[19]), .B(op1[19]), .CI(n_18), .CO(n_19), .S(p_0[19])); + FA_X1_LVT i_20 (.A(op2[20]), .B(op1[20]), .CI(n_19), .CO(n_20), .S(p_0[20])); + FA_X1_LVT i_21 (.A(op2[21]), .B(op1[21]), .CI(n_20), .CO(n_21), .S(p_0[21])); + FA_X1_LVT i_22 (.A(op2[22]), .B(op1[22]), .CI(n_21), .CO(n_22), .S(p_0[22])); + FA_X1_LVT i_23 (.A(op2[23]), .B(op1[23]), .CI(n_22), .CO(n_23), .S(p_0[23])); + FA_X1_LVT i_24 (.A(op2[24]), .B(op1[24]), .CI(n_23), .CO(n_24), .S(p_0[24])); + FA_X1_LVT i_25 (.A(op2[25]), .B(op1[25]), .CI(n_24), .CO(n_25), .S(p_0[25])); + FA_X1_LVT i_26 (.A(op2[26]), .B(op1[26]), .CI(n_25), .CO(n_26), .S(p_0[26])); + FA_X1_LVT i_27 (.A(op2[27]), .B(op1[27]), .CI(n_26), .CO(n_27), .S(p_0[27])); + FA_X1_LVT i_28 (.A(op2[28]), .B(op1[28]), .CI(n_27), .CO(n_28), .S(p_0[28])); + FA_X1_LVT i_29 (.A(op2[29]), .B(op1[29]), .CI(n_28), .CO(n_29), .S(p_0[29])); + FA_X1_LVT i_30 (.A(op2[30]), .B(op1[30]), .CI(n_29), .CO(n_30), .S(p_0[30])); + XNOR2_X1_LVT i_32 (.A(n_31), .B(n_30), .ZN(p_0[31])); +endmodule + +module datapathS__0_6(op1, p_0, op2); + input [31:0]op1; + output [31:0]p_0; + input [31:0]op2; + + INV_X1_LVT i_147 (.A(op2[30]), .ZN(n_117)); + NAND2_X1_LVT i_149 (.A1(n_117), .A2(op1[30]), .ZN(n_119)); + INV_X1_LVT i_152 (.A(n_119), .ZN(n_121)); + INV_X1_LVT i_130 (.A(op1[26]), .ZN(n_104)); + NAND2_X1_LVT i_131 (.A1(n_104), .A2(op2[26]), .ZN(n_105)); + INV_X1_LVT i_123 (.A(op2[25]), .ZN(n_98)); + NAND2_X1_LVT i_125 (.A1(n_98), .A2(op1[25]), .ZN(n_100)); + INV_X1_LVT i_112 (.A(op2[23]), .ZN(n_89)); + NAND2_X1_LVT i_114 (.A1(n_89), .A2(op1[23]), .ZN(n_91)); + INV_X1_LVT i_101 (.A(op2[21]), .ZN(n_80)); + NAND2_X1_LVT i_103 (.A1(n_80), .A2(op1[21]), .ZN(n_82)); + INV_X1_LVT i_48 (.A(op1[8]), .ZN(n_40)); + NAND2_X1_LVT i_49 (.A1(n_40), .A2(op2[8]), .ZN(n_41)); + INV_X1_LVT i_41 (.A(op2[7]), .ZN(n_34)); + NAND2_X1_LVT i_43 (.A1(n_34), .A2(op1[7]), .ZN(n_36)); + INV_X1_LVT i_32 (.A(op2[5]), .ZN(n_27)); + NOR2_X1_LVT i_33 (.A1(n_27), .A2(op1[5]), .ZN(n_28)); + INV_X1_LVT i_24 (.A(op1[4]), .ZN(n_20)); + NOR2_X1_LVT i_27 (.A1(n_20), .A2(op2[4]), .ZN(n_23)); + INV_X1_LVT i_17 (.A(op2[3]), .ZN(n_14)); + NAND2_X1_LVT i_19 (.A1(n_14), .A2(op1[3]), .ZN(n_16)); + INV_X1_LVT i_22 (.A(n_16), .ZN(n_18)); + INV_X1_LVT i_10 (.A(op2[2]), .ZN(n_8)); + NAND2_X1_LVT i_12 (.A1(n_8), .A2(op1[2]), .ZN(n_10)); + INV_X1_LVT i_3 (.A(op1[1]), .ZN(n_2)); + NAND2_X1_LVT i_5 (.A1(n_2), .A2(op2[1]), .ZN(n_4)); + INV_X1_LVT i_0 (.A(op1[0]), .ZN(n_0)); + NAND2_X1_LVT i_1 (.A1(n_0), .A2(op2[0]), .ZN(n_1)); + OR2_X1_LVT i_4 (.A1(n_2), .A2(op2[1]), .ZN(n_3)); + INV_X1_LVT i_8 (.A(n_3), .ZN(n_6)); + OAI21_X1_LVT i_9 (.A(n_4), .B1(n_1), .B2(n_6), .ZN(n_7)); + NOR2_X1_LVT i_11 (.A1(n_8), .A2(op1[2]), .ZN(n_9)); + OAI21_X1_LVT i_16 (.A(n_10), .B1(n_7), .B2(n_9), .ZN(n_13)); + OR2_X1_LVT i_18 (.A1(n_14), .A2(op1[3]), .ZN(n_15)); + AOI21_X1_LVT i_23 (.A(n_18), .B1(n_13), .B2(n_15), .ZN(n_19)); + INV_X1_LVT i_30 (.A(n_19), .ZN(n_25)); + NAND2_X1_LVT i_25 (.A1(n_20), .A2(op2[4]), .ZN(n_21)); + AOI21_X1_LVT i_31 (.A(n_23), .B1(n_25), .B2(n_21), .ZN(n_26)); + AOI21_X1_LVT i_34 (.A(n_28), .B1(n_27), .B2(op1[5]), .ZN(n_29)); + AOI21_X1_LVT i_36 (.A(n_28), .B1(n_26), .B2(n_29), .ZN(n_30)); + XOR2_X1_LVT i_37 (.A(op2[6]), .B(op1[6]), .Z(n_31)); + INV_X1_LVT i_39 (.A(op2[6]), .ZN(n_32)); + OAI22_X1_LVT i_40 (.A1(n_30), .A2(n_31), .B1(n_32), .B2(op1[6]), .ZN(n_33)); + NOR2_X1_LVT i_42 (.A1(n_34), .A2(op1[7]), .ZN(n_35)); + OAI21_X1_LVT i_47 (.A(n_36), .B1(n_33), .B2(n_35), .ZN(n_39)); + OAI21_X1_LVT i_50 (.A(n_41), .B1(n_40), .B2(op2[8]), .ZN(n_42)); + OAI21_X1_LVT i_52 (.A(n_41), .B1(n_39), .B2(n_42), .ZN(n_43)); + XNOR2_X1_LVT i_53 (.A(op2[9]), .B(op1[9]), .ZN(n_44)); + INV_X1_LVT i_55 (.A(op1[9]), .ZN(n_45)); + AOI22_X1_LVT i_56 (.A1(n_43), .A2(n_44), .B1(n_45), .B2(op2[9]), .ZN(n_46)); + XOR2_X1_LVT i_57 (.A(op2[10]), .B(op1[10]), .Z(n_47)); + INV_X1_LVT i_59 (.A(op2[10]), .ZN(n_48)); + OAI22_X1_LVT i_60 (.A1(n_46), .A2(n_47), .B1(n_48), .B2(op1[10]), .ZN(n_49)); + XNOR2_X1_LVT i_61 (.A(op2[11]), .B(op1[11]), .ZN(n_50)); + INV_X1_LVT i_63 (.A(op1[11]), .ZN(n_51)); + AOI22_X1_LVT i_64 (.A1(n_49), .A2(n_50), .B1(n_51), .B2(op2[11]), .ZN(n_52)); + XOR2_X1_LVT i_65 (.A(op2[12]), .B(op1[12]), .Z(n_53)); + INV_X1_LVT i_67 (.A(op2[12]), .ZN(n_54)); + OAI22_X1_LVT i_68 (.A1(n_52), .A2(n_53), .B1(n_54), .B2(op1[12]), .ZN(n_55)); + XNOR2_X1_LVT i_69 (.A(op2[13]), .B(op1[13]), .ZN(n_56)); + INV_X1_LVT i_71 (.A(op1[13]), .ZN(n_57)); + AOI22_X1_LVT i_72 (.A1(n_55), .A2(n_56), .B1(n_57), .B2(op2[13]), .ZN(n_58)); + XOR2_X1_LVT i_73 (.A(op2[14]), .B(op1[14]), .Z(n_59)); + INV_X1_LVT i_75 (.A(op2[14]), .ZN(n_60)); + OAI22_X1_LVT i_76 (.A1(n_58), .A2(n_59), .B1(n_60), .B2(op1[14]), .ZN(n_61)); + XNOR2_X1_LVT i_77 (.A(op2[15]), .B(op1[15]), .ZN(n_62)); + INV_X1_LVT i_79 (.A(op1[15]), .ZN(n_63)); + AOI22_X1_LVT i_80 (.A1(n_61), .A2(n_62), .B1(n_63), .B2(op2[15]), .ZN(n_64)); + XOR2_X1_LVT i_81 (.A(op2[16]), .B(op1[16]), .Z(n_65)); + INV_X1_LVT i_83 (.A(op2[16]), .ZN(n_66)); + OAI22_X1_LVT i_84 (.A1(n_64), .A2(n_65), .B1(n_66), .B2(op1[16]), .ZN(n_67)); + XNOR2_X1_LVT i_85 (.A(op2[17]), .B(op1[17]), .ZN(n_68)); + INV_X1_LVT i_87 (.A(op1[17]), .ZN(n_69)); + AOI22_X1_LVT i_88 (.A1(n_67), .A2(n_68), .B1(n_69), .B2(op2[17]), .ZN(n_70)); + XOR2_X1_LVT i_89 (.A(op2[18]), .B(op1[18]), .Z(n_71)); + INV_X1_LVT i_91 (.A(op2[18]), .ZN(n_72)); + OAI22_X1_LVT i_92 (.A1(n_70), .A2(n_71), .B1(n_72), .B2(op1[18]), .ZN(n_73)); + XNOR2_X1_LVT i_93 (.A(op2[19]), .B(op1[19]), .ZN(n_74)); + INV_X1_LVT i_95 (.A(op1[19]), .ZN(n_75)); + AOI22_X1_LVT i_96 (.A1(n_73), .A2(n_74), .B1(n_75), .B2(op2[19]), .ZN(n_76)); + XOR2_X1_LVT i_97 (.A(op2[20]), .B(op1[20]), .Z(n_77)); + INV_X1_LVT i_99 (.A(op2[20]), .ZN(n_78)); + OAI22_X1_LVT i_100 (.A1(n_76), .A2(n_77), .B1(n_78), .B2(op1[20]), .ZN(n_79)); + NOR2_X1_LVT i_102 (.A1(n_80), .A2(op1[21]), .ZN(n_81)); + OAI21_X1_LVT i_107 (.A(n_82), .B1(n_79), .B2(n_81), .ZN(n_85)); + XOR2_X1_LVT i_108 (.A(op2[22]), .B(op1[22]), .Z(n_86)); + INV_X1_LVT i_110 (.A(op2[22]), .ZN(n_87)); + OAI22_X1_LVT i_111 (.A1(n_85), .A2(n_86), .B1(n_87), .B2(op1[22]), .ZN(n_88)); + NOR2_X1_LVT i_113 (.A1(n_89), .A2(op1[23]), .ZN(n_90)); + OAI21_X1_LVT i_118 (.A(n_91), .B1(n_88), .B2(n_90), .ZN(n_94)); + XOR2_X1_LVT i_119 (.A(op2[24]), .B(op1[24]), .Z(n_95)); + INV_X1_LVT i_121 (.A(op2[24]), .ZN(n_96)); + OAI22_X1_LVT i_122 (.A1(n_94), .A2(n_95), .B1(n_96), .B2(op1[24]), .ZN(n_97)); + NOR2_X1_LVT i_124 (.A1(n_98), .A2(op1[25]), .ZN(n_99)); + OAI21_X1_LVT i_129 (.A(n_100), .B1(n_97), .B2(n_99), .ZN(n_103)); + OAI21_X1_LVT i_132 (.A(n_105), .B1(n_104), .B2(op2[26]), .ZN(n_106)); + OAI21_X1_LVT i_134 (.A(n_105), .B1(n_103), .B2(n_106), .ZN(n_107)); + XNOR2_X1_LVT i_135 (.A(op2[27]), .B(op1[27]), .ZN(n_108)); + INV_X1_LVT i_137 (.A(op1[27]), .ZN(n_109)); + AOI22_X1_LVT i_138 (.A1(n_107), .A2(n_108), .B1(n_109), .B2(op2[27]), + .ZN(n_110)); + XOR2_X1_LVT i_139 (.A(op2[28]), .B(op1[28]), .Z(n_111)); + INV_X1_LVT i_141 (.A(op2[28]), .ZN(n_112)); + OAI22_X1_LVT i_142 (.A1(n_110), .A2(n_111), .B1(n_112), .B2(op1[28]), + .ZN(n_113)); + XNOR2_X1_LVT i_143 (.A(op2[29]), .B(op1[29]), .ZN(n_114)); + INV_X1_LVT i_145 (.A(op1[29]), .ZN(n_115)); + AOI22_X1_LVT i_146 (.A1(n_113), .A2(n_114), .B1(n_115), .B2(op2[29]), + .ZN(n_116)); + OR2_X1_LVT i_148 (.A1(n_117), .A2(op1[30]), .ZN(n_118)); + AOI21_X1_LVT i_153 (.A(n_121), .B1(n_116), .B2(n_118), .ZN(n_122)); + XNOR2_X1_LVT i_154 (.A(op1[31]), .B(op2[31]), .ZN(n_123)); + XNOR2_X1_LVT i_155 (.A(n_122), .B(n_123), .ZN(p_0[31])); + NAND2_X1_LVT i_150 (.A1(n_118), .A2(n_119), .ZN(n_120)); + XNOR2_X1_LVT i_151 (.A(n_116), .B(n_120), .ZN(p_0[30])); + XNOR2_X1_LVT i_144 (.A(n_113), .B(n_114), .ZN(p_0[29])); + XNOR2_X1_LVT i_140 (.A(n_110), .B(n_111), .ZN(p_0[28])); + XNOR2_X1_LVT i_136 (.A(n_107), .B(n_108), .ZN(p_0[27])); + XNOR2_X1_LVT i_133 (.A(n_103), .B(n_106), .ZN(p_0[26])); + INV_X1_LVT i_126 (.A(n_100), .ZN(n_101)); + NOR2_X1_LVT i_127 (.A1(n_99), .A2(n_101), .ZN(n_102)); + XNOR2_X1_LVT i_128 (.A(n_97), .B(n_102), .ZN(p_0[25])); + XNOR2_X1_LVT i_120 (.A(n_94), .B(n_95), .ZN(p_0[24])); + INV_X1_LVT i_115 (.A(n_91), .ZN(n_92)); + NOR2_X1_LVT i_116 (.A1(n_90), .A2(n_92), .ZN(n_93)); + XNOR2_X1_LVT i_117 (.A(n_88), .B(n_93), .ZN(p_0[23])); + XNOR2_X1_LVT i_109 (.A(n_85), .B(n_86), .ZN(p_0[22])); + INV_X1_LVT i_104 (.A(n_82), .ZN(n_83)); + NOR2_X1_LVT i_105 (.A1(n_81), .A2(n_83), .ZN(n_84)); + XNOR2_X1_LVT i_106 (.A(n_79), .B(n_84), .ZN(p_0[21])); + XNOR2_X1_LVT i_98 (.A(n_76), .B(n_77), .ZN(p_0[20])); + XNOR2_X1_LVT i_94 (.A(n_73), .B(n_74), .ZN(p_0[19])); + XNOR2_X1_LVT i_90 (.A(n_70), .B(n_71), .ZN(p_0[18])); + XNOR2_X1_LVT i_86 (.A(n_67), .B(n_68), .ZN(p_0[17])); + XNOR2_X1_LVT i_82 (.A(n_64), .B(n_65), .ZN(p_0[16])); + XNOR2_X1_LVT i_78 (.A(n_61), .B(n_62), .ZN(p_0[15])); + XNOR2_X1_LVT i_74 (.A(n_58), .B(n_59), .ZN(p_0[14])); + XNOR2_X1_LVT i_70 (.A(n_55), .B(n_56), .ZN(p_0[13])); + XNOR2_X1_LVT i_66 (.A(n_52), .B(n_53), .ZN(p_0[12])); + XNOR2_X1_LVT i_62 (.A(n_49), .B(n_50), .ZN(p_0[11])); + XNOR2_X1_LVT i_58 (.A(n_46), .B(n_47), .ZN(p_0[10])); + XNOR2_X1_LVT i_54 (.A(n_43), .B(n_44), .ZN(p_0[9])); + XNOR2_X1_LVT i_51 (.A(n_39), .B(n_42), .ZN(p_0[8])); + INV_X1_LVT i_44 (.A(n_36), .ZN(n_37)); + NOR2_X1_LVT i_45 (.A1(n_35), .A2(n_37), .ZN(n_38)); + XNOR2_X1_LVT i_46 (.A(n_33), .B(n_38), .ZN(p_0[7])); + XNOR2_X1_LVT i_38 (.A(n_30), .B(n_31), .ZN(p_0[6])); + XNOR2_X1_LVT i_35 (.A(n_26), .B(n_29), .ZN(p_0[5])); + INV_X1_LVT i_26 (.A(n_21), .ZN(n_22)); + NOR2_X1_LVT i_28 (.A1(n_22), .A2(n_23), .ZN(n_24)); + XNOR2_X1_LVT i_29 (.A(n_19), .B(n_24), .ZN(p_0[4])); + NAND2_X1_LVT i_20 (.A1(n_15), .A2(n_16), .ZN(n_17)); + XNOR2_X1_LVT i_21 (.A(n_13), .B(n_17), .ZN(p_0[3])); + INV_X1_LVT i_13 (.A(n_10), .ZN(n_11)); + NOR2_X1_LVT i_14 (.A1(n_9), .A2(n_11), .ZN(n_12)); + XNOR2_X1_LVT i_15 (.A(n_7), .B(n_12), .ZN(p_0[2])); + NAND2_X1_LVT i_6 (.A1(n_3), .A2(n_4), .ZN(n_5)); + XNOR2_X1_LVT i_7 (.A(n_5), .B(n_1), .ZN(p_0[1])); + OAI21_X1_LVT i_2 (.A(n_1), .B1(n_0), .B2(op2[0]), .ZN(p_0[0])); +endmodule + +module alu(aluOp, aluNegAr, aluBypass, op1, op2, result, eqFlag); + input [2:0]aluOp; + input aluNegAr; + input aluBypass; + input [31:0]op1; + input [31:0]op2; + output [31:0]result; + output eqFlag; + + wire n_0_0; + wire n_0_1; + wire n_0_2; + wire n_0_3; + wire n_0_4; + wire n_0_5; + wire n_0_6; + wire n_0_7; + wire n_0_8; + wire n_0_9; + wire n_0_10; + wire n_0_11; + wire n_0_12; + wire n_0_13; + wire n_0_14; + wire n_0_15; + wire n_0_16; + wire n_0_17; + wire n_0_18; + wire n_0_19; + wire n_0_20; + wire n_0_21; + wire n_0_22; + wire n_0_23; + wire n_0_24; + wire n_0_25; + wire n_0_26; + wire n_0_27; + wire n_0_28; + wire n_0_29; + wire n_0_30; + wire n_0_31; + wire n_0_32; + wire n_0_33; + wire n_0_34; + wire n_0_35; + wire n_0_36; + wire n_0_37; + wire n_0_38; + wire n_0_39; + wire n_0_40; + wire n_0_41; + wire n_0_42; + wire n_0_43; + wire n_0_44; + wire n_0_45; + wire n_0_46; + wire n_0_47; + wire n_0_48; + wire n_0_49; + wire n_0_50; + wire n_0_51; + wire n_0_52; + wire n_0_53; + wire n_0_54; + wire n_0_55; + wire n_0_56; + wire n_0_57; + wire n_0_58; + wire n_0_59; + wire n_0_60; + wire n_0_61; + wire n_0_62; + wire n_0_63; + wire n_0_64; + wire n_0_65; + wire n_0_66; + wire n_0_67; + wire n_0_68; + wire n_0_69; + wire n_0_70; + wire n_0_71; + wire n_0_72; + wire n_0_73; + wire n_0_74; + wire n_0_75; + wire n_0_76; + wire n_0_77; + wire n_0_78; + wire n_0_79; + wire n_0_80; + wire n_0_81; + wire n_0_82; + wire n_0_83; + wire n_0_84; + wire n_0_85; + wire n_0_86; + wire n_0_87; + wire n_0_88; + wire n_0_89; + wire n_0_90; + wire n_0_91; + wire n_0_92; + wire n_0_93; + wire n_0_94; + wire n_0_95; + wire n_0_96; + wire n_0_97; + wire n_0_98; + wire n_0_99; + wire n_0_100; + wire n_0_101; + wire n_0_102; + wire n_0_103; + wire n_0_104; + wire n_0_105; + wire n_0_106; + wire n_0_107; + wire n_0_108; + wire n_0_109; + wire n_0_110; + wire n_0_111; + wire n_0_112; + wire n_0_113; + wire n_0_114; + wire n_0_115; + wire n_0_116; + wire n_0_117; + wire n_0_118; + wire n_0_119; + wire n_0_120; + wire n_0_121; + wire n_0_122; + wire n_0_123; + wire n_0_124; + wire n_0_125; + wire n_0_126; + wire n_0_127; + wire n_0_128; + wire n_0_129; + wire n_0_130; + wire n_0_131; + wire n_0_132; + wire n_0_133; + wire n_0_134; + wire n_0_135; + wire n_0_136; + wire n_0_137; + wire n_0_138; + wire n_0_139; + wire n_0_140; + wire n_0_141; + wire n_0_142; + wire n_0_143; + wire n_0_144; + wire n_0_145; + wire n_0_146; + wire n_0_147; + wire n_0_148; + wire n_0_149; + wire n_0_150; + wire n_0_151; + wire n_0_152; + wire n_0_153; + wire n_0_154; + wire n_0_155; + wire n_0_156; + wire n_0_157; + wire n_0_158; + wire n_0_159; + wire n_0_160; + wire n_0_161; + wire n_0_162; + wire n_0_163; + wire n_0_164; + wire n_0_165; + wire n_0_166; + wire n_0_167; + wire n_0_168; + wire n_0_169; + wire n_0_170; + wire n_0_171; + wire n_0_172; + wire n_0_173; + wire n_0_174; + wire n_0_175; + wire n_0_176; + wire n_0_177; + wire n_0_178; + wire n_0_179; + wire n_0_180; + wire n_0_181; + wire n_0_182; + wire n_0_183; + wire n_0_184; + wire n_0_185; + wire n_0_186; + wire n_0_187; + wire n_0_188; + wire n_0_189; + wire n_0_190; + wire n_0_191; + wire n_0_192; + wire n_0_193; + wire n_0_194; + wire n_0_195; + wire n_0_196; + wire n_0_197; + wire n_0_198; + wire n_0_199; + wire n_0_200; + wire n_0_201; + wire n_0_202; + wire n_0_203; + wire n_0_204; + wire n_0_205; + wire n_0_206; + wire n_0_207; + wire n_0_208; + wire n_0_209; + wire n_0_210; + wire n_0_211; + wire n_0_212; + wire n_0_213; + wire n_0_214; + wire n_0_215; + wire n_0_216; + wire n_0_217; + wire n_0_218; + wire n_0_219; + wire n_0_220; + wire n_0_221; + wire n_0_222; + wire n_0_223; + wire n_0_224; + wire n_0_225; + wire n_0_226; + wire n_0_227; + wire n_0_228; + wire n_0_229; + wire n_0_230; + wire n_0_231; + wire n_0_232; + wire n_0_233; + wire n_0_234; + wire n_0_235; + wire n_0_236; + wire n_0_237; + wire n_0_238; + wire n_0_239; + wire n_0_240; + wire n_0_241; + wire n_0_242; + wire n_0_243; + wire n_0_244; + wire n_0_245; + wire n_0_246; + wire n_0_247; + wire n_0_248; + wire n_0_249; + wire n_0_250; + wire n_0_251; + wire n_0_252; + wire n_0_253; + wire n_0_254; + wire n_0_255; + wire n_0_256; + wire n_0_257; + wire n_0_258; + wire n_0_259; + wire n_0_260; + wire n_0_261; + wire n_0_262; + wire n_0_263; + wire n_0_264; + wire n_0_265; + wire n_0_266; + wire n_0_267; + wire n_0_268; + wire n_0_269; + wire n_0_270; + wire n_0_271; + wire n_0_272; + wire n_0_273; + wire n_0_274; + wire n_0_275; + wire n_0_276; + wire n_0_277; + wire n_0_278; + wire n_0_279; + wire n_0_280; + wire n_0_281; + wire n_0_282; + wire n_0_283; + wire n_0_284; + wire n_0_285; + wire n_0_286; + wire n_0_287; + wire n_0_288; + wire n_0_289; + wire n_0_290; + wire n_0_291; + wire n_0_292; + wire n_0_293; + wire n_0_294; + wire n_0_295; + wire n_0_296; + wire n_0_297; + wire n_0_298; + wire n_0_299; + wire n_0_300; + wire n_0_301; + wire n_0_302; + wire n_0_303; + wire n_0_304; + wire n_0_305; + wire n_0_306; + wire n_0_307; + wire n_0_308; + wire n_0_309; + wire n_0_310; + wire n_0_311; + wire n_0_312; + wire n_0_313; + wire n_0_314; + wire n_0_315; + wire n_0_316; + wire n_0_317; + wire n_0_318; + wire n_0_319; + wire n_0_320; + wire n_0_321; + wire n_0_322; + wire n_0_323; + wire n_0_324; + wire n_0_325; + wire n_0_326; + wire n_0_327; + wire n_0_328; + wire n_0_329; + wire n_0_330; + wire n_0_331; + wire n_0_332; + wire n_0_333; + wire n_0_334; + wire n_0_335; + wire n_0_336; + wire n_0_337; + wire n_0_338; + wire n_0_339; + wire n_0_340; + wire n_0_341; + wire n_0_342; + wire n_0_343; + wire n_0_344; + wire n_0_345; + wire n_0_346; + wire n_0_347; + wire n_0_348; + wire n_0_349; + wire n_0_350; + wire n_0_351; + wire n_0_352; + wire n_0_353; + wire n_0_354; + wire n_0_355; + wire n_0_356; + wire n_0_357; + wire n_0_358; + wire n_0_359; + wire n_0_360; + wire n_0_361; + wire n_0_362; + wire n_0_363; + wire n_0_364; + wire n_0_365; + wire n_0_366; + wire n_0_367; + wire n_0_368; + wire n_0_369; + wire n_0_370; + wire n_0_371; + wire n_0_372; + wire n_0_373; + wire n_0_374; + wire n_0_375; + wire n_0_376; + wire n_0_377; + wire n_0_378; + wire n_0_379; + wire n_0_380; + wire n_0_381; + wire n_0_382; + wire n_0_383; + wire n_0_384; + wire n_0_385; + wire n_0_386; + wire n_0_387; + wire n_0_388; + wire n_0_389; + wire n_0_390; + wire n_0_391; + wire n_0_392; + wire n_0_393; + wire n_0_394; + wire n_0_395; + wire n_0_396; + wire n_0_397; + wire n_0_398; + wire n_0_399; + wire n_0_400; + wire n_0_401; + wire n_0_402; + wire n_0_403; + wire n_0_404; + wire n_0_405; + wire n_0_406; + wire n_0_407; + wire n_0_408; + wire n_0_409; + wire n_0_410; + wire n_0_411; + wire n_0_412; + wire n_0_413; + wire n_0_414; + wire n_0_415; + wire n_0_416; + wire n_0_417; + wire n_0_418; + wire n_0_419; + wire n_0_420; + wire n_0_421; + wire n_0_422; + wire n_0_423; + wire n_0_424; + wire n_0_425; + wire n_0_426; + wire n_0_427; + wire n_0_428; + wire n_0_429; + wire n_0_430; + wire n_0_431; + wire n_0_432; + wire n_0_433; + wire n_0_434; + wire n_0_435; + wire n_0_436; + wire n_0_437; + wire n_0_438; + wire n_0_439; + wire n_0_440; + wire n_0_441; + wire n_0_442; + wire n_0_443; + wire n_0_444; + wire n_0_445; + wire n_0_446; + wire n_0_447; + wire n_0_448; + wire n_0_449; + wire n_0_450; + wire n_0_451; + wire n_0_452; + wire n_0_453; + wire n_0_454; + wire n_0_455; + wire n_0_456; + wire n_0_457; + wire n_0_458; + wire n_0_459; + wire n_0_460; + wire n_0_461; + wire n_0_462; + wire n_0_463; + wire n_0_464; + wire n_0_465; + wire n_0_466; + wire n_0_467; + wire n_0_468; + wire n_0_469; + wire n_0_470; + wire n_0_471; + wire n_0_472; + wire n_0_473; + wire n_0_474; + wire n_0_475; + wire n_0_476; + wire n_0_477; + wire n_0_478; + wire n_0_479; + wire n_0_480; + wire n_0_481; + wire n_0_482; + wire n_0_483; + wire n_0_484; + wire n_0_485; + wire n_0_486; + wire n_0_487; + wire n_0_488; + wire n_0_489; + wire n_0_490; + wire n_0_491; + wire n_0_492; + wire n_0_493; + wire n_0_494; + wire n_0_495; + wire n_0_496; + wire n_0_497; + wire n_0_498; + wire n_0_499; + wire n_0_500; + wire n_0_501; + wire n_0_502; + wire n_0_503; + wire n_0_504; + wire n_0_505; + wire n_0_506; + wire n_0_507; + wire n_0_508; + wire n_0_509; + wire n_0_510; + wire n_0_511; + wire n_0_512; + wire n_0_513; + wire n_0_514; + wire n_0_515; + wire n_0_516; + wire n_0_517; + wire n_0_518; + wire n_0_519; + wire n_0_520; + wire n_0_521; + wire n_0_522; + wire n_0_523; + wire n_0_524; + wire n_0_525; + wire n_0_526; + wire n_0_527; + wire n_0_528; + wire n_0_529; + wire n_0_530; + wire n_0_531; + wire n_0_532; + wire n_0_533; + wire n_0_534; + wire n_0_535; + wire n_0_536; + wire n_0_537; + wire n_0_538; + wire n_0_539; + wire n_0_540; + wire n_0_541; + wire n_0_542; + wire n_0_543; + wire n_0_544; + wire n_0_545; + wire n_0_546; + wire n_0_547; + wire n_0_548; + wire n_0_549; + wire n_0_550; + wire n_0_551; + wire n_0_552; + wire n_0_553; + wire n_0_554; + wire n_0_555; + wire n_0_556; + wire n_0_557; + wire n_0_558; + wire n_0_559; + wire n_0_560; + wire n_0_561; + wire n_0_562; + wire n_0_563; + wire n_0_564; + wire n_0_565; + wire n_0_566; + wire n_0_567; + wire n_0_568; + wire n_0_569; + wire n_0_570; + wire n_0_571; + wire n_0_572; + wire n_0_573; + wire n_0_574; + wire n_0_575; + wire n_0_576; + wire n_0_577; + wire n_0_578; + wire n_0_579; + wire n_0_580; + wire n_0_581; + wire n_0_582; + wire n_0_583; + wire n_0_584; + wire n_0_585; + wire n_0_586; + wire n_0_587; + wire n_0_588; + wire n_0_589; + wire n_0_590; + wire n_0_591; + wire n_0_592; + wire n_0_593; + wire n_0_594; + wire n_0_595; + wire n_0_596; + wire n_0_597; + wire n_0_598; + wire n_0_599; + wire n_0_600; + wire n_0_601; + wire n_0_602; + wire n_0_603; + wire n_0_604; + wire n_0_605; + wire n_0_606; + wire n_0_607; + wire n_0_608; + wire n_0_609; + wire n_0_610; + wire n_0_611; + wire n_0_612; + wire n_0_613; + wire n_0_614; + wire n_0_615; + wire n_0_616; + wire n_0_617; + wire n_0_618; + wire n_0_619; + wire n_0_620; + wire n_0_621; + wire n_0_622; + wire n_0_623; + wire n_0_624; + wire n_0_625; + wire n_0_626; + wire n_0_627; + wire n_0_628; + wire n_0_629; + wire n_0_630; + wire n_0_631; + wire n_0_632; + wire n_0_633; + wire n_0_634; + wire n_0_635; + wire n_0_636; + wire n_0_637; + wire n_0_638; + wire n_0_639; + wire n_0_640; + wire n_0_641; + wire n_0_642; + wire n_0_643; + wire n_0_644; + wire n_0_645; + wire n_0_646; + wire n_0_647; + wire n_0_648; + wire n_0_649; + wire n_0_650; + wire n_0_651; + wire n_0_652; + wire n_0_653; + wire n_0_654; + wire n_0_655; + wire n_0_656; + wire n_0_657; + wire n_0_658; + wire n_0_659; + wire n_0_660; + wire n_0_661; + wire n_0_662; + wire n_0_663; + wire n_0_664; + wire n_0_665; + wire n_0_666; + wire n_0_667; + wire n_0_668; + wire n_0_669; + wire n_0_670; + wire n_0_671; + wire n_0_672; + wire n_0_673; + wire n_0_674; + wire n_0_675; + wire n_0_676; + wire n_0_677; + wire n_0_678; + wire n_0_679; + wire n_0_680; + wire n_0_681; + wire n_0_682; + wire n_0_683; + wire n_0_684; + wire n_0_685; + wire n_0_686; + wire n_0_687; + wire n_0_688; + wire n_0_689; + wire n_0_690; + wire n_0_691; + wire n_0_692; + wire n_0_693; + wire n_0_694; + wire n_0_695; + wire n_0_696; + wire n_0_697; + wire n_0_698; + wire n_0_699; + wire n_0_700; + wire n_0_701; + wire n_0_702; + wire n_0_703; + wire n_0_704; + wire n_0_705; + wire n_0_706; + wire n_0_707; + wire n_0_708; + wire n_0_709; + wire n_0_710; + wire n_0_711; + wire n_0_712; + wire n_0_713; + wire n_0_714; + wire n_0_715; + wire n_0_716; + wire n_0_717; + wire n_0_718; + wire n_0_719; + wire n_0_720; + wire n_0_721; + wire n_0_722; + wire n_0_723; + wire n_0_724; + wire n_0_725; + wire n_0_726; + wire n_0_727; + wire n_0_728; + wire n_0_729; + wire n_0_730; + wire n_0_731; + wire n_0_732; + wire n_0_733; + wire n_0_734; + wire n_0_735; + wire n_0_736; + wire n_0_737; + wire n_0_738; + wire n_0_739; + wire n_0_740; + + INV_X1_LVT i_0_725 (.A(op2[31]), .ZN(n_0_692)); + INV_X1_LVT i_0_724 (.A(op1[31]), .ZN(n_0_691)); + INV_X1_LVT i_0_718 (.A(aluOp[1]), .ZN(n_0_685)); + INV_X1_LVT i_0_717 (.A(aluOp[2]), .ZN(n_0_684)); + NOR2_X1_LVT i_0_599 (.A1(n_0_685), .A2(n_0_684), .ZN(n_0_567)); + INV_X1_LVT i_0_598 (.A(n_0_567), .ZN(n_0_566)); + INV_X1_LVT i_0_716 (.A(aluOp[0]), .ZN(n_0_683)); + NAND2_X1_LVT i_0_602 (.A1(aluOp[2]), .A2(aluNegAr), .ZN(n_0_570)); + OAI21_X1_LVT i_0_590 (.A(n_0_566), .B1(n_0_683), .B2(n_0_570), .ZN(n_0_558)); + INV_X1_LVT i_0_714 (.A(aluBypass), .ZN(n_0_681)); + NOR2_X1_LVT i_0_601 (.A1(n_0_684), .A2(aluOp[0]), .ZN(n_0_569)); + NAND2_X1_LVT i_0_597 (.A1(n_0_681), .A2(n_0_569), .ZN(n_0_565)); + INV_X1_LVT i_0_596 (.A(n_0_565), .ZN(n_0_564)); + OAI22_X1_LVT i_0_589 (.A1(n_0_691), .A2(n_0_558), .B1(op1[31]), .B2(n_0_564), + .ZN(n_0_557)); + NOR2_X1_LVT i_0_588 (.A1(n_0_692), .A2(n_0_557), .ZN(n_0_556)); + datapathS i_9 (.op2(op2), .op1(op1), .p_0({n_31, n_30, n_29, n_28, n_27, n_26, + n_25, n_24, n_23, n_22, n_21, n_20, n_19, n_18, n_17, n_16, n_15, n_14, + n_13, n_12, n_11, n_10, n_9, n_8, n_7, n_6, n_5, n_4, n_3, n_2, n_1, n_0})); + NAND4_X1_LVT i_0_614 (.A1(n_0_685), .A2(n_0_681), .A3(n_0_684), .A4(n_0_683), + .ZN(n_0_582)); + NOR2_X1_LVT i_0_613 (.A1(aluNegAr), .A2(n_0_582), .ZN(n_0_581)); + datapathS__0_6 i_10 (.op1(op1), .p_0({n_63, n_62, n_61, n_60, n_59, n_58, + n_57, n_56, n_55, n_54, n_53, n_52, n_51, n_50, n_49, n_48, n_47, n_46, + n_45, n_44, n_43, n_42, n_41, n_40, n_39, n_38, n_37, n_36, n_35, n_34, + n_33, n_32}), .op2(op2)); + INV_X1_LVT i_0_715 (.A(aluNegAr), .ZN(n_0_682)); + NOR2_X1_LVT i_0_612 (.A1(n_0_682), .A2(n_0_582), .ZN(n_0_580)); + AOI221_X1_LVT i_0_587 (.A(n_0_556), .B1(n_31), .B2(n_0_581), .C1(n_63), + .C2(n_0_580), .ZN(n_0_555)); + NOR3_X1_LVT i_0_654 (.A1(aluOp[1]), .A2(aluBypass), .A3(n_0_683), .ZN(n_0_622)); + NAND2_X1_LVT i_0_653 (.A1(n_0_684), .A2(n_0_622), .ZN(n_0_621)); + INV_X1_LVT i_0_734 (.A(op2[0]), .ZN(n_0_701)); + INV_X1_LVT i_0_756 (.A(op2[3]), .ZN(n_0_723)); + NOR2_X1_LVT i_0_650 (.A1(op2[4]), .A2(n_0_723), .ZN(n_0_618)); + INV_X1_LVT i_0_649 (.A(n_0_618), .ZN(n_0_617)); + NOR2_X1_LVT i_0_648 (.A1(op2[4]), .A2(op2[3]), .ZN(n_0_616)); + INV_X1_LVT i_0_647 (.A(n_0_616), .ZN(n_0_615)); + INV_X1_LVT i_0_771 (.A(op2[4]), .ZN(n_0_738)); + INV_X1_LVT i_0_767 (.A(op1[15]), .ZN(n_0_734)); + INV_X1_LVT i_0_746 (.A(op1[7]), .ZN(n_0_713)); + AOI22_X1_LVT i_0_651 (.A1(n_0_734), .A2(n_0_723), .B1(op2[3]), .B2(n_0_713), + .ZN(n_0_619)); + OAI222_X1_LVT i_0_646 (.A1(op1[23]), .A2(n_0_617), .B1(op1[31]), .B2(n_0_615), + .C1(n_0_738), .C2(n_0_619), .ZN(n_0_614)); + NOR2_X1_LVT i_0_645 (.A1(op2[2]), .A2(n_0_614), .ZN(n_0_613)); + NOR2_X1_LVT i_0_696 (.A1(op1[3]), .A2(n_0_723), .ZN(n_0_663)); + INV_X1_LVT i_0_739 (.A(op1[11]), .ZN(n_0_706)); + AOI21_X1_LVT i_0_644 (.A(n_0_663), .B1(n_0_723), .B2(n_0_706), .ZN(n_0_612)); + AOI22_X1_LVT i_0_643 (.A1(op2[4]), .A2(n_0_612), .B1(op1[27]), .B2(n_0_616), + .ZN(n_0_611)); + INV_X1_LVT i_0_722 (.A(op1[19]), .ZN(n_0_689)); + OAI21_X1_LVT i_0_642 (.A(n_0_611), .B1(n_0_689), .B2(n_0_617), .ZN(n_0_610)); + AOI21_X1_LVT i_0_641 (.A(n_0_613), .B1(op2[2]), .B2(n_0_610), .ZN(n_0_609)); + INV_X1_LVT i_0_761 (.A(op2[1]), .ZN(n_0_728)); + OAI22_X1_LVT i_0_640 (.A1(op2[4]), .A2(op1[21]), .B1(n_0_738), .B2(op1[5]), + .ZN(n_0_608)); + NAND2_X1_LVT i_0_639 (.A1(op2[3]), .A2(n_0_608), .ZN(n_0_607)); + INV_X1_LVT i_0_747 (.A(op1[13]), .ZN(n_0_714)); + NOR2_X1_LVT i_0_638 (.A1(n_0_738), .A2(op2[3]), .ZN(n_0_606)); + INV_X1_LVT i_0_743 (.A(op1[29]), .ZN(n_0_710)); + AOI221_X1_LVT i_0_636 (.A(op2[2]), .B1(n_0_714), .B2(n_0_606), .C1(n_0_710), + .C2(n_0_616), .ZN(n_0_604)); + OAI22_X1_LVT i_0_635 (.A1(op2[4]), .A2(op1[17]), .B1(n_0_738), .B2(op1[1]), + .ZN(n_0_603)); + INV_X1_LVT i_0_755 (.A(op1[9]), .ZN(n_0_722)); + INV_X1_LVT i_0_637 (.A(n_0_606), .ZN(n_0_605)); + INV_X1_LVT i_0_732 (.A(op1[25]), .ZN(n_0_699)); + OAI222_X1_LVT i_0_634 (.A1(n_0_723), .A2(n_0_603), .B1(n_0_722), .B2(n_0_605), + .C1(n_0_699), .C2(n_0_615), .ZN(n_0_602)); + AOI22_X1_LVT i_0_633 (.A1(n_0_607), .A2(n_0_604), .B1(op2[2]), .B2(n_0_602), + .ZN(n_0_601)); + OAI221_X1_LVT i_0_616 (.A(n_0_701), .B1(op2[1]), .B2(n_0_609), .C1(n_0_728), + .C2(n_0_601), .ZN(n_0_584)); + INV_X1_LVT i_0_729 (.A(op1[12]), .ZN(n_0_696)); + INV_X1_LVT i_0_731 (.A(op1[28]), .ZN(n_0_698)); + AOI22_X1_LVT i_0_622 (.A1(n_0_696), .A2(n_0_606), .B1(n_0_698), .B2(n_0_616), + .ZN(n_0_590)); + INV_X1_LVT i_0_726 (.A(op2[2]), .ZN(n_0_693)); + NOR2_X1_LVT i_0_701 (.A1(n_0_738), .A2(op1[4]), .ZN(n_0_668)); + INV_X1_LVT i_0_760 (.A(op1[20]), .ZN(n_0_727)); + AOI21_X1_LVT i_0_623 (.A(n_0_668), .B1(n_0_738), .B2(n_0_727), .ZN(n_0_591)); + OAI211_X1_LVT i_0_621 (.A(n_0_590), .B(n_0_693), .C1(n_0_723), .C2(n_0_591), + .ZN(n_0_589)); + OAI22_X1_LVT i_0_626 (.A1(op1[16]), .A2(op2[4]), .B1(n_0_738), .B2(op1[0]), + .ZN(n_0_594)); + INV_X1_LVT i_0_769 (.A(op1[24]), .ZN(n_0_736)); + OAI22_X1_LVT i_0_625 (.A1(n_0_723), .A2(n_0_594), .B1(n_0_736), .B2(n_0_615), + .ZN(n_0_593)); + AOI21_X1_LVT i_0_624 (.A(n_0_593), .B1(op1[8]), .B2(n_0_606), .ZN(n_0_592)); + OAI21_X1_LVT i_0_620 (.A(n_0_589), .B1(n_0_693), .B2(n_0_592), .ZN(n_0_588)); + INV_X1_LVT i_0_737 (.A(op1[6]), .ZN(n_0_704)); + INV_X1_LVT i_0_720 (.A(op1[22]), .ZN(n_0_687)); + OAI22_X1_LVT i_0_632 (.A1(n_0_738), .A2(n_0_704), .B1(op2[4]), .B2(n_0_687), + .ZN(n_0_600)); + OAI221_X1_LVT i_0_631 (.A(n_0_693), .B1(n_0_723), .B2(n_0_600), .C1(op1[14]), + .C2(n_0_605), .ZN(n_0_599)); + INV_X1_LVT i_0_750 (.A(op1[30]), .ZN(n_0_717)); + AOI21_X1_LVT i_0_630 (.A(n_0_599), .B1(n_0_717), .B2(n_0_616), .ZN(n_0_598)); + INV_X1_LVT i_0_738 (.A(op1[18]), .ZN(n_0_705)); + NOR2_X1_LVT i_0_628 (.A1(n_0_705), .A2(n_0_617), .ZN(n_0_596)); + INV_X1_LVT i_0_727 (.A(op1[2]), .ZN(n_0_694)); + INV_X1_LVT i_0_766 (.A(op1[10]), .ZN(n_0_733)); + OAI22_X1_LVT i_0_629 (.A1(n_0_723), .A2(n_0_694), .B1(n_0_733), .B2(op2[3]), + .ZN(n_0_597)); + AOI221_X1_LVT i_0_627 (.A(n_0_596), .B1(op1[26]), .B2(n_0_616), .C1(op2[4]), + .C2(n_0_597), .ZN(n_0_595)); + OAI21_X1_LVT i_0_619 (.A(n_0_728), .B1(n_0_693), .B2(n_0_595), .ZN(n_0_587)); + OAI22_X1_LVT i_0_618 (.A1(n_0_728), .A2(n_0_588), .B1(n_0_598), .B2(n_0_587), + .ZN(n_0_586)); + INV_X1_LVT i_0_617 (.A(n_0_586), .ZN(n_0_585)); + OAI21_X1_LVT i_0_615 (.A(n_0_584), .B1(n_0_701), .B2(n_0_585), .ZN(n_0_583)); + NOR2_X1_LVT i_0_607 (.A1(op2[4]), .A2(op2[2]), .ZN(n_0_575)); + NAND2_X1_LVT i_0_606 (.A1(n_0_723), .A2(n_0_575), .ZN(n_0_574)); + INV_X1_LVT i_0_605 (.A(n_0_574), .ZN(n_0_573)); + NAND2_X1_LVT i_0_604 (.A1(n_0_728), .A2(n_0_573), .ZN(n_0_572)); + NAND2_X1_LVT i_0_611 (.A1(aluOp[2]), .A2(n_0_622), .ZN(n_0_579)); + INV_X1_LVT i_0_610 (.A(n_0_579), .ZN(n_0_578)); + NAND2_X1_LVT i_0_594 (.A1(n_0_701), .A2(n_0_578), .ZN(n_0_562)); + NOR3_X1_LVT i_0_592 (.A1(aluNegAr), .A2(n_0_572), .A3(n_0_562), .ZN(n_0_560)); + INV_X1_LVT i_0_600 (.A(n_0_569), .ZN(n_0_568)); + OAI21_X1_LVT i_0_595 (.A(n_0_568), .B1(aluOp[1]), .B2(n_0_570), .ZN(n_0_563)); + AOI211_X1_LVT i_0_591 (.A(aluBypass), .B(n_0_560), .C1(n_0_692), .C2(n_0_563), + .ZN(n_0_559)); + OAI221_X1_LVT i_0_586 (.A(n_0_555), .B1(n_0_621), .B2(n_0_583), .C1(n_0_691), + .C2(n_0_559), .ZN(result[31])); + AOI22_X1_LVT i_0_580 (.A1(n_62), .A2(n_0_580), .B1(n_30), .B2(n_0_581), + .ZN(n_0_549)); + NAND2_X1_LVT i_0_576 (.A1(aluNegAr), .A2(n_0_578), .ZN(n_0_545)); + INV_X1_LVT i_0_603 (.A(n_0_572), .ZN(n_0_571)); + NOR3_X1_LVT i_0_574 (.A1(n_0_691), .A2(n_0_545), .A3(n_0_571), .ZN(n_0_543)); + AOI22_X1_LVT i_0_573 (.A1(n_0_717), .A2(n_0_565), .B1(op1[30]), .B2(n_0_566), + .ZN(n_0_542)); + AOI21_X1_LVT i_0_572 (.A(n_0_543), .B1(op2[30]), .B2(n_0_542), .ZN(n_0_541)); + NAND2_X1_LVT i_0_579 (.A1(op2[0]), .A2(n_0_578), .ZN(n_0_548)); + NAND2_X1_LVT i_0_577 (.A1(op1[31]), .A2(n_0_571), .ZN(n_0_546)); + OAI211_X1_LVT i_0_571 (.A(n_0_549), .B(n_0_541), .C1(n_0_548), .C2(n_0_546), + .ZN(n_0_540)); + OAI221_X1_LVT i_0_581 (.A(n_0_681), .B1(op2[30]), .B2(n_0_568), .C1(n_0_572), + .C2(n_0_562), .ZN(n_0_550)); + AOI21_X1_LVT i_0_570 (.A(n_0_540), .B1(op1[30]), .B2(n_0_550), .ZN(n_0_539)); + INV_X1_LVT i_0_752 (.A(op1[23]), .ZN(n_0_719)); + OAI222_X1_LVT i_0_585 (.A1(n_0_713), .A2(n_0_605), .B1(n_0_719), .B2(n_0_615), + .C1(n_0_734), .C2(n_0_617), .ZN(n_0_554)); + AOI22_X1_LVT i_0_584 (.A1(op2[2]), .A2(n_0_554), .B1(n_0_693), .B2(n_0_610), + .ZN(n_0_553)); + OAI22_X1_LVT i_0_583 (.A1(n_0_728), .A2(n_0_553), .B1(op2[1]), .B2(n_0_601), + .ZN(n_0_552)); + AOI22_X1_LVT i_0_582 (.A1(n_0_701), .A2(n_0_585), .B1(op2[0]), .B2(n_0_552), + .ZN(n_0_551)); + OAI21_X1_LVT i_0_569 (.A(n_0_539), .B1(n_0_621), .B2(n_0_551), .ZN(result[30])); + INV_X1_LVT i_0_578 (.A(n_0_548), .ZN(n_0_547)); + NAND3_X1_LVT i_0_562 (.A1(op1[30]), .A2(n_0_571), .A3(n_0_547), .ZN(n_0_532)); + NAND2_X1_LVT i_0_558 (.A1(n_61), .A2(n_0_580), .ZN(n_0_528)); + OAI21_X1_LVT i_0_557 (.A(n_0_681), .B1(op2[29]), .B2(n_0_568), .ZN(n_0_527)); + NAND2_X1_LVT i_0_556 (.A1(op1[29]), .A2(n_0_566), .ZN(n_0_526)); + AOI22_X1_LVT i_0_555 (.A1(op1[29]), .A2(n_0_527), .B1(op2[29]), .B2(n_0_526), + .ZN(n_0_525)); + AOI21_X1_LVT i_0_554 (.A(n_0_525), .B1(n_0_710), .B2(n_0_565), .ZN(n_0_524)); + AOI211_X1_LVT i_0_553 (.A(n_0_543), .B(n_0_524), .C1(n_29), .C2(n_0_581), + .ZN(n_0_523)); + AND3_X1_LVT i_0_552 (.A1(n_0_532), .A2(n_0_528), .A3(n_0_523), .ZN(n_0_522)); + INV_X1_LVT i_0_652 (.A(n_0_621), .ZN(n_0_620)); + NAND2_X1_LVT i_0_565 (.A1(n_0_728), .A2(n_0_588), .ZN(n_0_535)); + AOI22_X1_LVT i_0_568 (.A1(n_0_723), .A2(n_0_600), .B1(op1[14]), .B2(n_0_618), + .ZN(n_0_538)); + AOI22_X1_LVT i_0_567 (.A1(n_0_693), .A2(n_0_595), .B1(op2[2]), .B2(n_0_538), + .ZN(n_0_537)); + INV_X1_LVT i_0_566 (.A(n_0_537), .ZN(n_0_536)); + OAI21_X1_LVT i_0_564 (.A(n_0_535), .B1(n_0_728), .B2(n_0_536), .ZN(n_0_534)); + OAI221_X1_LVT i_0_563 (.A(n_0_620), .B1(op2[0]), .B2(n_0_552), .C1(n_0_701), + .C2(n_0_534), .ZN(n_0_533)); + NAND2_X1_LVT i_0_561 (.A1(op2[1]), .A2(n_0_573), .ZN(n_0_531)); + INV_X1_LVT i_0_560 (.A(n_0_531), .ZN(n_0_530)); + AOI22_X1_LVT i_0_559 (.A1(op1[31]), .A2(n_0_530), .B1(op1[29]), .B2(n_0_571), + .ZN(n_0_529)); + OAI211_X1_LVT i_0_551 (.A(n_0_522), .B(n_0_533), .C1(n_0_562), .C2(n_0_529), + .ZN(result[29])); + INV_X1_LVT i_0_733 (.A(op2[28]), .ZN(n_0_700)); + AOI221_X1_LVT i_0_546 (.A(n_0_700), .B1(op1[28]), .B2(n_0_566), .C1(n_0_698), + .C2(n_0_565), .ZN(n_0_517)); + OAI21_X1_LVT i_0_543 (.A(n_0_681), .B1(op2[28]), .B2(n_0_568), .ZN(n_0_514)); + AOI22_X1_LVT i_0_542 (.A1(n_28), .A2(n_0_581), .B1(op1[28]), .B2(n_0_514), + .ZN(n_0_513)); + NAND2_X1_LVT i_0_544 (.A1(n_60), .A2(n_0_580), .ZN(n_0_515)); + NAND2_X1_LVT i_0_545 (.A1(op1[31]), .A2(n_0_574), .ZN(n_0_516)); + OAI211_X1_LVT i_0_541 (.A(n_0_513), .B(n_0_515), .C1(n_0_545), .C2(n_0_516), + .ZN(n_0_512)); + AOI22_X1_LVT i_0_540 (.A1(op1[30]), .A2(n_0_530), .B1(op1[28]), .B2(n_0_571), + .ZN(n_0_511)); + OAI22_X1_LVT i_0_539 (.A1(n_0_562), .A2(n_0_511), .B1(n_0_548), .B2(n_0_529), + .ZN(n_0_510)); + NOR3_X1_LVT i_0_538 (.A1(n_0_517), .A2(n_0_512), .A3(n_0_510), .ZN(n_0_509)); + OAI22_X1_LVT i_0_550 (.A1(n_0_714), .A2(n_0_617), .B1(op2[3]), .B2(n_0_608), + .ZN(n_0_521)); + OAI22_X1_LVT i_0_549 (.A1(op2[2]), .A2(n_0_602), .B1(n_0_693), .B2(n_0_521), + .ZN(n_0_520)); + AOI22_X1_LVT i_0_548 (.A1(op2[1]), .A2(n_0_520), .B1(n_0_728), .B2(n_0_553), + .ZN(n_0_519)); + OAI22_X1_LVT i_0_547 (.A1(op2[0]), .A2(n_0_534), .B1(n_0_701), .B2(n_0_519), + .ZN(n_0_518)); + OAI21_X1_LVT i_0_537 (.A(n_0_509), .B1(n_0_621), .B2(n_0_518), .ZN(result[28])); + AOI22_X1_LVT i_0_517 (.A1(n_27), .A2(n_0_581), .B1(n_59), .B2(n_0_580), + .ZN(n_0_489)); + INV_X1_LVT i_0_721 (.A(op1[27]), .ZN(n_0_688)); + OAI21_X1_LVT i_0_516 (.A(n_0_681), .B1(op2[27]), .B2(n_0_568), .ZN(n_0_488)); + INV_X1_LVT i_0_515 (.A(n_0_488), .ZN(n_0_487)); + OAI221_X1_LVT i_0_514 (.A(n_0_489), .B1(n_0_545), .B2(n_0_516), .C1(n_0_688), + .C2(n_0_487), .ZN(n_0_486)); + OAI21_X1_LVT i_0_530 (.A(op2[1]), .B1(n_0_710), .B2(n_0_574), .ZN(n_0_502)); + OAI21_X1_LVT i_0_529 (.A(n_0_728), .B1(n_0_688), .B2(n_0_574), .ZN(n_0_501)); + NAND2_X1_LVT i_0_528 (.A1(n_0_502), .A2(n_0_501), .ZN(n_0_500)); + AOI21_X1_LVT i_0_527 (.A(n_0_545), .B1(n_0_701), .B2(n_0_500), .ZN(n_0_499)); + NAND2_X1_LVT i_0_609 (.A1(n_0_682), .A2(n_0_578), .ZN(n_0_577)); + NOR2_X1_LVT i_0_526 (.A1(op2[4]), .A2(n_0_693), .ZN(n_0_498)); + NAND2_X1_LVT i_0_525 (.A1(n_0_723), .A2(n_0_498), .ZN(n_0_497)); + OAI22_X1_LVT i_0_523 (.A1(n_0_688), .A2(n_0_574), .B1(n_0_691), .B2(n_0_497), + .ZN(n_0_495)); + OAI21_X1_LVT i_0_522 (.A(n_0_502), .B1(op2[1]), .B2(n_0_495), .ZN(n_0_494)); + AOI21_X1_LVT i_0_521 (.A(n_0_577), .B1(n_0_701), .B2(n_0_494), .ZN(n_0_493)); + NOR2_X1_LVT i_0_520 (.A1(n_0_499), .A2(n_0_493), .ZN(n_0_492)); + AOI21_X1_LVT i_0_519 (.A(n_0_492), .B1(op2[0]), .B2(n_0_511), .ZN(n_0_491)); + AOI22_X1_LVT i_0_518 (.A1(n_0_688), .A2(n_0_565), .B1(op1[27]), .B2(n_0_566), + .ZN(n_0_490)); + AOI211_X1_LVT i_0_513 (.A(n_0_486), .B(n_0_491), .C1(op2[27]), .C2(n_0_490), + .ZN(n_0_485)); + NOR3_X1_LVT i_0_536 (.A1(op2[4]), .A2(n_0_696), .A3(n_0_723), .ZN(n_0_508)); + AOI21_X1_LVT i_0_535 (.A(n_0_508), .B1(n_0_723), .B2(n_0_591), .ZN(n_0_507)); + OAI22_X1_LVT i_0_534 (.A1(op2[2]), .A2(n_0_592), .B1(n_0_693), .B2(n_0_507), + .ZN(n_0_506)); + NOR2_X1_LVT i_0_533 (.A1(n_0_728), .A2(n_0_506), .ZN(n_0_505)); + AOI21_X1_LVT i_0_532 (.A(n_0_505), .B1(n_0_728), .B2(n_0_536), .ZN(n_0_504)); + OAI22_X1_LVT i_0_531 (.A1(n_0_701), .A2(n_0_504), .B1(op2[0]), .B2(n_0_519), + .ZN(n_0_503)); + OAI21_X1_LVT i_0_512 (.A(n_0_485), .B1(n_0_621), .B2(n_0_503), .ZN(result[27])); + OAI21_X1_LVT i_0_500 (.A(n_0_681), .B1(op2[26]), .B2(n_0_568), .ZN(n_0_473)); + NAND2_X1_LVT i_0_499 (.A1(op1[26]), .A2(n_0_473), .ZN(n_0_472)); + AOI22_X1_LVT i_0_498 (.A1(n_58), .A2(n_0_580), .B1(n_26), .B2(n_0_581), + .ZN(n_0_471)); + INV_X1_LVT i_0_744 (.A(op1[26]), .ZN(n_0_711)); + OAI221_X1_LVT i_0_501 (.A(op2[26]), .B1(op1[26]), .B2(n_0_564), .C1(n_0_711), + .C2(n_0_567), .ZN(n_0_474)); + NAND3_X1_LVT i_0_497 (.A1(n_0_472), .A2(n_0_471), .A3(n_0_474), .ZN(n_0_470)); + INV_X1_LVT i_0_524 (.A(n_0_497), .ZN(n_0_496)); + AOI22_X1_LVT i_0_505 (.A1(op1[30]), .A2(n_0_496), .B1(op1[26]), .B2(n_0_573), + .ZN(n_0_478)); + NOR2_X1_LVT i_0_504 (.A1(op2[1]), .A2(n_0_478), .ZN(n_0_477)); + AOI21_X1_LVT i_0_503 (.A(n_0_477), .B1(op1[28]), .B2(n_0_530), .ZN(n_0_476)); + NAND2_X1_LVT i_0_502 (.A1(n_0_701), .A2(n_0_476), .ZN(n_0_475)); + AOI21_X1_LVT i_0_489 (.A(n_0_577), .B1(op2[0]), .B2(n_0_494), .ZN(n_0_462)); + AOI21_X1_LVT i_0_488 (.A(n_0_470), .B1(n_0_475), .B2(n_0_462), .ZN(n_0_461)); + AOI21_X1_LVT i_0_511 (.A(n_0_616), .B1(n_0_738), .B2(n_0_706), .ZN(n_0_484)); + AOI21_X1_LVT i_0_510 (.A(n_0_484), .B1(n_0_723), .B2(op1[19]), .ZN(n_0_483)); + INV_X1_LVT i_0_757 (.A(op1[3]), .ZN(n_0_724)); + NOR2_X1_LVT i_0_687 (.A1(n_0_724), .A2(op2[3]), .ZN(n_0_654)); + INV_X1_LVT i_0_686 (.A(n_0_654), .ZN(n_0_653)); + AOI21_X1_LVT i_0_509 (.A(n_0_483), .B1(op2[4]), .B2(n_0_653), .ZN(n_0_482)); + AOI22_X1_LVT i_0_508 (.A1(n_0_693), .A2(n_0_554), .B1(op2[2]), .B2(n_0_482), + .ZN(n_0_481)); + OAI22_X1_LVT i_0_507 (.A1(n_0_728), .A2(n_0_481), .B1(op2[1]), .B2(n_0_520), + .ZN(n_0_480)); + AOI22_X1_LVT i_0_506 (.A1(op2[0]), .A2(n_0_480), .B1(n_0_701), .B2(n_0_504), + .ZN(n_0_479)); + NAND3_X1_LVT i_0_491 (.A1(op2[0]), .A2(n_0_516), .A3(n_0_500), .ZN(n_0_464)); + NAND2_X1_LVT i_0_494 (.A1(op1[31]), .A2(n_0_615), .ZN(n_0_467)); + OAI21_X1_LVT i_0_492 (.A(n_0_467), .B1(n_0_728), .B2(n_0_516), .ZN(n_0_465)); + OAI21_X1_LVT i_0_490 (.A(n_0_464), .B1(n_0_475), .B2(n_0_465), .ZN(n_0_463)); + OAI221_X1_LVT i_0_487 (.A(n_0_461), .B1(n_0_621), .B2(n_0_479), .C1(n_0_545), + .C2(n_0_463), .ZN(result[26])); + AOI22_X1_LVT i_0_479 (.A1(n_57), .A2(n_0_580), .B1(n_25), .B2(n_0_581), + .ZN(n_0_453)); + INV_X1_LVT i_0_730 (.A(op2[25]), .ZN(n_0_697)); + AOI21_X1_LVT i_0_478 (.A(aluBypass), .B1(n_0_697), .B2(n_0_569), .ZN(n_0_452)); + AOI22_X1_LVT i_0_480 (.A1(op1[25]), .A2(n_0_567), .B1(n_0_699), .B2(n_0_564), + .ZN(n_0_454)); + OAI221_X1_LVT i_0_477 (.A(n_0_453), .B1(n_0_699), .B2(n_0_452), .C1(n_0_697), + .C2(n_0_454), .ZN(n_0_451)); + INV_X1_LVT i_0_575 (.A(n_0_545), .ZN(n_0_544)); + AOI21_X1_LVT i_0_476 (.A(n_0_451), .B1(n_0_544), .B2(n_0_465), .ZN(n_0_450)); + AOI22_X1_LVT i_0_475 (.A1(op1[29]), .A2(n_0_496), .B1(op1[25]), .B2(n_0_573), + .ZN(n_0_449)); + NAND2_X1_LVT i_0_474 (.A1(n_0_728), .A2(n_0_449), .ZN(n_0_448)); + OAI21_X1_LVT i_0_473 (.A(n_0_448), .B1(n_0_728), .B2(n_0_495), .ZN(n_0_447)); + OAI22_X1_LVT i_0_472 (.A1(n_0_548), .A2(n_0_476), .B1(n_0_562), .B2(n_0_447), + .ZN(n_0_446)); + INV_X1_LVT i_0_471 (.A(n_0_446), .ZN(n_0_445)); + OAI222_X1_LVT i_0_486 (.A1(n_0_733), .A2(n_0_617), .B1(n_0_694), .B2(n_0_605), + .C1(n_0_705), .C2(n_0_615), .ZN(n_0_460)); + NOR2_X1_LVT i_0_485 (.A1(n_0_693), .A2(n_0_460), .ZN(n_0_459)); + AOI21_X1_LVT i_0_484 (.A(n_0_459), .B1(n_0_693), .B2(n_0_538), .ZN(n_0_458)); + OAI22_X1_LVT i_0_483 (.A1(n_0_728), .A2(n_0_458), .B1(op2[1]), .B2(n_0_506), + .ZN(n_0_457)); + INV_X1_LVT i_0_482 (.A(n_0_457), .ZN(n_0_456)); + OAI221_X1_LVT i_0_481 (.A(n_0_620), .B1(n_0_701), .B2(n_0_456), .C1(op2[0]), + .C2(n_0_480), .ZN(n_0_455)); + NAND3_X1_LVT i_0_470 (.A1(n_0_450), .A2(n_0_445), .A3(n_0_455), .ZN( + result[25])); + INV_X1_LVT i_0_493 (.A(n_0_467), .ZN(n_0_466)); + OAI211_X1_LVT i_0_455 (.A(n_0_544), .B(n_0_465), .C1(op2[0]), .C2(n_0_466), + .ZN(n_0_430)); + OAI21_X1_LVT i_0_462 (.A(n_0_681), .B1(op2[24]), .B2(n_0_568), .ZN(n_0_437)); + AOI222_X1_LVT i_0_461 (.A1(op1[24]), .A2(n_0_437), .B1(n_56), .B2(n_0_580), + .C1(n_24), .C2(n_0_581), .ZN(n_0_436)); + INV_X1_LVT i_0_460 (.A(n_0_436), .ZN(n_0_435)); + AOI22_X1_LVT i_0_458 (.A1(op1[24]), .A2(n_0_573), .B1(op1[28]), .B2(n_0_496), + .ZN(n_0_433)); + OAI22_X1_LVT i_0_457 (.A1(op2[1]), .A2(n_0_433), .B1(n_0_728), .B2(n_0_478), + .ZN(n_0_432)); + INV_X1_LVT i_0_456 (.A(n_0_432), .ZN(n_0_431)); + OAI22_X1_LVT i_0_454 (.A1(n_0_562), .A2(n_0_431), .B1(n_0_548), .B2(n_0_447), + .ZN(n_0_429)); + AOI22_X1_LVT i_0_459 (.A1(n_0_736), .A2(n_0_565), .B1(op1[24]), .B2(n_0_566), + .ZN(n_0_434)); + AOI211_X1_LVT i_0_453 (.A(n_0_435), .B(n_0_429), .C1(op2[24]), .C2(n_0_434), + .ZN(n_0_428)); + NAND2_X1_LVT i_0_467 (.A1(n_0_693), .A2(n_0_521), .ZN(n_0_442)); + NOR2_X1_LVT i_0_469 (.A1(op2[3]), .A2(n_0_603), .ZN(n_0_444)); + AOI21_X1_LVT i_0_468 (.A(n_0_444), .B1(op1[9]), .B2(n_0_618), .ZN(n_0_443)); + OAI21_X1_LVT i_0_466 (.A(n_0_442), .B1(n_0_693), .B2(n_0_443), .ZN(n_0_441)); + NAND2_X1_LVT i_0_465 (.A1(op2[1]), .A2(n_0_441), .ZN(n_0_440)); + OAI21_X1_LVT i_0_464 (.A(n_0_440), .B1(op2[1]), .B2(n_0_481), .ZN(n_0_439)); + OAI221_X1_LVT i_0_463 (.A(n_0_620), .B1(op2[0]), .B2(n_0_456), .C1(n_0_701), + .C2(n_0_439), .ZN(n_0_438)); + NAND3_X1_LVT i_0_452 (.A1(n_0_430), .A2(n_0_428), .A3(n_0_438), .ZN( + result[24])); + INV_X1_LVT i_0_751 (.A(op2[23]), .ZN(n_0_718)); + AOI221_X1_LVT i_0_440 (.A(n_0_718), .B1(op1[23]), .B2(n_0_566), .C1(n_0_719), + .C2(n_0_565), .ZN(n_0_416)); + AOI222_X1_LVT i_0_438 (.A1(n_23), .A2(n_0_581), .B1(n_0_544), .B2(n_0_466), + .C1(n_55), .C2(n_0_580), .ZN(n_0_414)); + OAI21_X1_LVT i_0_437 (.A(n_0_414), .B1(n_0_548), .B2(n_0_431), .ZN(n_0_413)); + OAI21_X1_LVT i_0_439 (.A(n_0_681), .B1(op2[23]), .B2(n_0_568), .ZN(n_0_415)); + AOI211_X1_LVT i_0_436 (.A(n_0_416), .B(n_0_413), .C1(op1[23]), .C2(n_0_415), + .ZN(n_0_412)); + AOI22_X1_LVT i_0_444 (.A1(n_0_723), .A2(n_0_719), .B1(op2[3]), .B2(n_0_691), + .ZN(n_0_420)); + AOI22_X1_LVT i_0_443 (.A1(n_0_575), .A2(n_0_420), .B1(op1[27]), .B2(n_0_496), + .ZN(n_0_419)); + AOI22_X1_LVT i_0_442 (.A1(op2[1]), .A2(n_0_449), .B1(n_0_728), .B2(n_0_419), + .ZN(n_0_418)); + INV_X1_LVT i_0_441 (.A(n_0_418), .ZN(n_0_417)); + NAND2_X1_LVT i_0_447 (.A1(n_0_728), .A2(n_0_458), .ZN(n_0_423)); + NOR2_X1_LVT i_0_451 (.A1(op2[3]), .A2(n_0_594), .ZN(n_0_427)); + AOI21_X1_LVT i_0_450 (.A(n_0_427), .B1(op1[8]), .B2(n_0_618), .ZN(n_0_426)); + OAI22_X1_LVT i_0_449 (.A1(n_0_693), .A2(n_0_426), .B1(op2[2]), .B2(n_0_507), + .ZN(n_0_425)); + INV_X1_LVT i_0_448 (.A(n_0_425), .ZN(n_0_424)); + OAI21_X1_LVT i_0_446 (.A(n_0_423), .B1(n_0_728), .B2(n_0_424), .ZN(n_0_422)); + AOI22_X1_LVT i_0_445 (.A1(op2[0]), .A2(n_0_422), .B1(n_0_701), .B2(n_0_439), + .ZN(n_0_421)); + OAI221_X1_LVT i_0_435 (.A(n_0_412), .B1(n_0_562), .B2(n_0_417), .C1(n_0_621), + .C2(n_0_421), .ZN(result[23])); + AOI22_X1_LVT i_0_419 (.A1(n_54), .A2(n_0_580), .B1(n_22), .B2(n_0_581), + .ZN(n_0_396)); + INV_X1_LVT i_0_719 (.A(op2[22]), .ZN(n_0_686)); + AOI21_X1_LVT i_0_420 (.A(aluBypass), .B1(n_0_686), .B2(n_0_569), .ZN(n_0_397)); + OAI21_X1_LVT i_0_418 (.A(n_0_396), .B1(n_0_687), .B2(n_0_397), .ZN(n_0_395)); + AOI22_X1_LVT i_0_421 (.A1(op1[22]), .A2(n_0_566), .B1(n_0_687), .B2(n_0_565), + .ZN(n_0_398)); + AOI21_X1_LVT i_0_417 (.A(n_0_395), .B1(op2[22]), .B2(n_0_398), .ZN(n_0_394)); + NAND2_X1_LVT i_0_432 (.A1(n_0_728), .A2(n_0_441), .ZN(n_0_409)); + AND2_X1_LVT i_0_434 (.A1(n_0_738), .A2(n_0_619), .ZN(n_0_411)); + AOI22_X1_LVT i_0_433 (.A1(n_0_693), .A2(n_0_482), .B1(op2[2]), .B2(n_0_411), + .ZN(n_0_410)); + OAI21_X1_LVT i_0_431 (.A(n_0_409), .B1(n_0_728), .B2(n_0_410), .ZN(n_0_408)); + OAI22_X1_LVT i_0_430 (.A1(n_0_701), .A2(n_0_408), .B1(op2[0]), .B2(n_0_422), + .ZN(n_0_407)); + AOI22_X1_LVT i_0_429 (.A1(n_0_723), .A2(n_0_687), .B1(op2[3]), .B2(n_0_717), + .ZN(n_0_406)); + AOI22_X1_LVT i_0_428 (.A1(n_0_575), .A2(n_0_406), .B1(op1[26]), .B2(n_0_496), + .ZN(n_0_405)); + AND2_X1_LVT i_0_427 (.A1(n_0_728), .A2(n_0_405), .ZN(n_0_404)); + AOI21_X1_LVT i_0_426 (.A(n_0_404), .B1(op2[1]), .B2(n_0_433), .ZN(n_0_403)); + INV_X1_LVT i_0_425 (.A(n_0_403), .ZN(n_0_402)); + OAI222_X1_LVT i_0_424 (.A1(n_0_545), .A2(n_0_467), .B1(n_0_701), .B2(n_0_417), + .C1(op2[0]), .C2(n_0_402), .ZN(n_0_401)); + NOR2_X1_LVT i_0_496 (.A1(n_0_738), .A2(n_0_691), .ZN(n_0_469)); + INV_X1_LVT i_0_495 (.A(n_0_469), .ZN(n_0_468)); + NAND3_X1_LVT i_0_423 (.A1(n_0_693), .A2(n_0_468), .A3(n_0_404), .ZN(n_0_400)); + OAI21_X1_LVT i_0_422 (.A(n_0_401), .B1(op2[0]), .B2(n_0_400), .ZN(n_0_399)); + OAI221_X1_LVT i_0_416 (.A(n_0_394), .B1(n_0_621), .B2(n_0_407), .C1(n_0_579), + .C2(n_0_399), .ZN(result[22])); + INV_X1_LVT i_0_759 (.A(op1[21]), .ZN(n_0_726)); + AOI22_X1_LVT i_0_399 (.A1(op1[21]), .A2(n_0_566), .B1(n_0_726), .B2(n_0_565), + .ZN(n_0_377)); + NOR2_X1_LVT i_0_692 (.A1(n_0_726), .A2(op2[21]), .ZN(n_0_659)); + AOI222_X1_LVT i_0_398 (.A1(op2[21]), .A2(n_0_377), .B1(n_21), .B2(n_0_581), + .C1(n_0_659), .C2(n_0_569), .ZN(n_0_376)); + INV_X1_LVT i_0_397 (.A(n_0_376), .ZN(n_0_375)); + AOI221_X1_LVT i_0_396 (.A(n_0_375), .B1(n_53), .B2(n_0_580), .C1(op1[21]), + .C2(aluBypass), .ZN(n_0_374)); + INV_X1_LVT i_0_608 (.A(n_0_577), .ZN(n_0_576)); + NAND2_X1_LVT i_0_403 (.A1(op2[0]), .A2(n_0_402), .ZN(n_0_381)); + AND2_X1_LVT i_0_410 (.A1(op2[1]), .A2(n_0_419), .ZN(n_0_388)); + OAI22_X1_LVT i_0_408 (.A1(n_0_723), .A2(n_0_710), .B1(n_0_726), .B2(op2[3]), + .ZN(n_0_386)); + AOI22_X1_LVT i_0_407 (.A1(n_0_575), .A2(n_0_386), .B1(op1[25]), .B2(n_0_496), + .ZN(n_0_385)); + AOI21_X1_LVT i_0_395 (.A(n_0_388), .B1(n_0_728), .B2(n_0_385), .ZN(n_0_373)); + OAI211_X1_LVT i_0_394 (.A(n_0_576), .B(n_0_381), .C1(op2[0]), .C2(n_0_373), + .ZN(n_0_372)); + AOI21_X1_LVT i_0_402 (.A(n_0_381), .B1(n_0_466), .B2(n_0_400), .ZN(n_0_380)); + INV_X1_LVT i_0_401 (.A(n_0_380), .ZN(n_0_379)); + NOR2_X1_LVT i_0_409 (.A1(n_0_575), .A2(n_0_467), .ZN(n_0_387)); + INV_X1_LVT i_0_406 (.A(n_0_385), .ZN(n_0_384)); + NOR2_X1_LVT i_0_405 (.A1(n_0_387), .A2(n_0_384), .ZN(n_0_383)); + AOI22_X1_LVT i_0_404 (.A1(n_0_467), .A2(n_0_388), .B1(n_0_728), .B2(n_0_383), + .ZN(n_0_382)); + OAI211_X1_LVT i_0_400 (.A(n_0_544), .B(n_0_379), .C1(op2[0]), .C2(n_0_382), + .ZN(n_0_378)); + AOI22_X1_LVT i_0_415 (.A1(op1[14]), .A2(n_0_616), .B1(op1[6]), .B2(n_0_618), + .ZN(n_0_393)); + NOR2_X1_LVT i_0_414 (.A1(n_0_693), .A2(n_0_393), .ZN(n_0_392)); + AOI21_X1_LVT i_0_413 (.A(n_0_392), .B1(n_0_693), .B2(n_0_460), .ZN(n_0_391)); + OAI22_X1_LVT i_0_412 (.A1(n_0_728), .A2(n_0_391), .B1(op2[1]), .B2(n_0_424), + .ZN(n_0_390)); + OAI221_X1_LVT i_0_411 (.A(n_0_620), .B1(op2[0]), .B2(n_0_408), .C1(n_0_701), + .C2(n_0_390), .ZN(n_0_389)); + NAND4_X1_LVT i_0_393 (.A1(n_0_374), .A2(n_0_372), .A3(n_0_378), .A4(n_0_389), + .ZN(result[21])); + OAI221_X1_LVT i_0_388 (.A(op2[20]), .B1(n_0_727), .B2(n_0_567), .C1(op1[20]), + .C2(n_0_564), .ZN(n_0_367)); + NOR2_X1_LVT i_0_691 (.A1(n_0_727), .A2(op2[20]), .ZN(n_0_658)); + AOI22_X1_LVT i_0_387 (.A1(op1[20]), .A2(aluBypass), .B1(n_0_658), .B2(n_0_569), + .ZN(n_0_366)); + AOI22_X1_LVT i_0_386 (.A1(n_52), .A2(n_0_580), .B1(n_20), .B2(n_0_581), + .ZN(n_0_365)); + AOI221_X1_LVT i_0_392 (.A(op2[4]), .B1(n_0_727), .B2(n_0_723), .C1(op2[3]), + .C2(n_0_698), .ZN(n_0_371)); + AOI22_X1_LVT i_0_391 (.A1(op1[24]), .A2(n_0_496), .B1(n_0_693), .B2(n_0_371), + .ZN(n_0_370)); + OAI22_X1_LVT i_0_390 (.A1(op2[1]), .A2(n_0_370), .B1(n_0_728), .B2(n_0_405), + .ZN(n_0_369)); + OAI221_X1_LVT i_0_385 (.A(n_0_576), .B1(n_0_701), .B2(n_0_373), .C1(op2[0]), + .C2(n_0_369), .ZN(n_0_364)); + AND4_X1_LVT i_0_384 (.A1(n_0_367), .A2(n_0_366), .A3(n_0_365), .A4(n_0_364), + .ZN(n_0_363)); + AOI22_X1_LVT i_0_383 (.A1(op1[13]), .A2(n_0_616), .B1(op1[5]), .B2(n_0_618), + .ZN(n_0_362)); + AOI22_X1_LVT i_0_382 (.A1(op2[2]), .A2(n_0_362), .B1(n_0_693), .B2(n_0_443), + .ZN(n_0_361)); + NAND2_X1_LVT i_0_381 (.A1(op2[1]), .A2(n_0_361), .ZN(n_0_360)); + OAI21_X1_LVT i_0_380 (.A(n_0_360), .B1(op2[1]), .B2(n_0_410), .ZN(n_0_359)); + OAI221_X1_LVT i_0_379 (.A(n_0_620), .B1(n_0_701), .B2(n_0_359), .C1(op2[0]), + .C2(n_0_390), .ZN(n_0_358)); + OR2_X1_LVT i_0_389 (.A1(n_0_387), .A2(n_0_369), .ZN(n_0_368)); + AOI22_X1_LVT i_0_378 (.A1(op2[0]), .A2(n_0_382), .B1(n_0_701), .B2(n_0_368), + .ZN(n_0_357)); + OAI211_X1_LVT i_0_377 (.A(n_0_363), .B(n_0_358), .C1(n_0_545), .C2(n_0_357), + .ZN(result[20])); + OAI22_X1_LVT i_0_370 (.A1(op2[3]), .A2(n_0_689), .B1(n_0_723), .B2(n_0_688), + .ZN(n_0_350)); + AND2_X1_LVT i_0_369 (.A1(n_0_738), .A2(n_0_350), .ZN(n_0_349)); + AOI22_X1_LVT i_0_368 (.A1(n_0_498), .A2(n_0_420), .B1(n_0_693), .B2(n_0_349), + .ZN(n_0_348)); + AND2_X1_LVT i_0_367 (.A1(n_0_728), .A2(n_0_348), .ZN(n_0_347)); + AOI21_X1_LVT i_0_359 (.A(n_0_347), .B1(op2[1]), .B2(n_0_385), .ZN(n_0_339)); + OAI221_X1_LVT i_0_357 (.A(n_0_576), .B1(n_0_701), .B2(n_0_369), .C1(op2[0]), + .C2(n_0_339), .ZN(n_0_337)); + NAND2_X1_LVT i_0_363 (.A1(n_19), .A2(n_0_581), .ZN(n_0_343)); + INV_X1_LVT i_0_723 (.A(op2[19]), .ZN(n_0_690)); + AOI221_X1_LVT i_0_364 (.A(n_0_690), .B1(n_0_689), .B2(n_0_565), .C1(op1[19]), + .C2(n_0_566), .ZN(n_0_344)); + AOI221_X1_LVT i_0_361 (.A(n_0_344), .B1(op1[19]), .B2(aluBypass), .C1(n_51), + .C2(n_0_580), .ZN(n_0_341)); + NAND3_X1_LVT i_0_362 (.A1(n_0_690), .A2(op1[19]), .A3(n_0_569), .ZN(n_0_342)); + NAND3_X1_LVT i_0_360 (.A1(n_0_343), .A2(n_0_341), .A3(n_0_342), .ZN(n_0_340)); + AOI22_X1_LVT i_0_376 (.A1(op1[12]), .A2(n_0_616), .B1(op1[4]), .B2(n_0_618), + .ZN(n_0_356)); + OAI22_X1_LVT i_0_375 (.A1(n_0_693), .A2(n_0_356), .B1(op2[2]), .B2(n_0_426), + .ZN(n_0_355)); + INV_X1_LVT i_0_374 (.A(n_0_355), .ZN(n_0_354)); + OAI22_X1_LVT i_0_373 (.A1(op2[1]), .A2(n_0_391), .B1(n_0_728), .B2(n_0_354), + .ZN(n_0_353)); + AOI22_X1_LVT i_0_372 (.A1(n_0_701), .A2(n_0_359), .B1(op2[0]), .B2(n_0_353), + .ZN(n_0_352)); + INV_X1_LVT i_0_371 (.A(n_0_352), .ZN(n_0_351)); + AOI21_X1_LVT i_0_358 (.A(n_0_340), .B1(n_0_620), .B2(n_0_351), .ZN(n_0_338)); + AOI22_X1_LVT i_0_366 (.A1(n_0_468), .A2(n_0_347), .B1(op2[1]), .B2(n_0_383), + .ZN(n_0_346)); + AOI22_X1_LVT i_0_365 (.A1(n_0_701), .A2(n_0_346), .B1(op2[0]), .B2(n_0_368), + .ZN(n_0_345)); + OAI211_X1_LVT i_0_356 (.A(n_0_337), .B(n_0_338), .C1(n_0_545), .C2(n_0_345), + .ZN(result[19])); + NAND2_X1_LVT i_0_342 (.A1(n_50), .A2(n_0_580), .ZN(n_0_323)); + OAI21_X1_LVT i_0_343 (.A(n_0_681), .B1(op2[18]), .B2(n_0_568), .ZN(n_0_324)); + AOI22_X1_LVT i_0_341 (.A1(op1[18]), .A2(n_0_324), .B1(n_18), .B2(n_0_581), + .ZN(n_0_322)); + OAI221_X1_LVT i_0_340 (.A(op2[18]), .B1(n_0_705), .B2(n_0_567), .C1(op1[18]), + .C2(n_0_564), .ZN(n_0_321)); + NAND3_X1_LVT i_0_339 (.A1(n_0_323), .A2(n_0_322), .A3(n_0_321), .ZN(n_0_320)); + OAI22_X1_LVT i_0_351 (.A1(op2[3]), .A2(n_0_705), .B1(n_0_723), .B2(n_0_711), + .ZN(n_0_332)); + AND2_X1_LVT i_0_350 (.A1(n_0_738), .A2(n_0_332), .ZN(n_0_331)); + AOI22_X1_LVT i_0_349 (.A1(n_0_498), .A2(n_0_406), .B1(n_0_693), .B2(n_0_331), + .ZN(n_0_330)); + NAND2_X1_LVT i_0_348 (.A1(n_0_728), .A2(n_0_330), .ZN(n_0_329)); + NAND2_X1_LVT i_0_347 (.A1(op2[1]), .A2(n_0_370), .ZN(n_0_328)); + AND2_X1_LVT i_0_338 (.A1(n_0_329), .A2(n_0_328), .ZN(n_0_319)); + OAI22_X1_LVT i_0_337 (.A1(op2[0]), .A2(n_0_319), .B1(n_0_701), .B2(n_0_339), + .ZN(n_0_318)); + INV_X1_LVT i_0_336 (.A(n_0_318), .ZN(n_0_317)); + AOI21_X1_LVT i_0_335 (.A(n_0_320), .B1(n_0_578), .B2(n_0_317), .ZN(n_0_316)); + OAI22_X1_LVT i_0_346 (.A1(n_0_469), .A2(n_0_329), .B1(n_0_387), .B2(n_0_328), + .ZN(n_0_327)); + NAND2_X1_LVT i_0_344 (.A1(n_0_544), .A2(n_0_346), .ZN(n_0_325)); + NAND2_X1_LVT i_0_354 (.A1(n_0_728), .A2(n_0_361), .ZN(n_0_335)); + AOI22_X1_LVT i_0_355 (.A1(n_0_612), .A2(n_0_498), .B1(n_0_693), .B2(n_0_411), + .ZN(n_0_336)); + OAI21_X1_LVT i_0_353 (.A(n_0_335), .B1(n_0_728), .B2(n_0_336), .ZN(n_0_334)); + AOI22_X1_LVT i_0_352 (.A1(n_0_701), .A2(n_0_353), .B1(op2[0]), .B2(n_0_334), + .ZN(n_0_333)); + OAI221_X1_LVT i_0_334 (.A(n_0_316), .B1(n_0_327), .B2(n_0_325), .C1(n_0_621), + .C2(n_0_333), .ZN(result[18])); + NAND2_X1_LVT i_0_325 (.A1(n_17), .A2(n_0_581), .ZN(n_0_307)); + INV_X1_LVT i_0_765 (.A(op1[17]), .ZN(n_0_732)); + AOI22_X1_LVT i_0_324 (.A1(n_0_732), .A2(n_0_565), .B1(op1[17]), .B2(n_0_566), + .ZN(n_0_306)); + NOR2_X1_LVT i_0_693 (.A1(n_0_732), .A2(op2[17]), .ZN(n_0_660)); + AOI222_X1_LVT i_0_323 (.A1(op2[17]), .A2(n_0_306), .B1(n_0_660), .B2(n_0_569), + .C1(n_49), .C2(n_0_580), .ZN(n_0_305)); + OAI211_X1_LVT i_0_322 (.A(n_0_307), .B(n_0_305), .C1(n_0_732), .C2(n_0_681), + .ZN(n_0_304)); + AOI22_X1_LVT i_0_331 (.A1(op2[3]), .A2(op1[25]), .B1(op1[17]), .B2(n_0_723), + .ZN(n_0_313)); + NOR2_X1_LVT i_0_330 (.A1(op2[4]), .A2(n_0_313), .ZN(n_0_312)); + AOI22_X1_LVT i_0_329 (.A1(n_0_498), .A2(n_0_386), .B1(n_0_693), .B2(n_0_312), + .ZN(n_0_311)); + OAI22_X1_LVT i_0_328 (.A1(op2[1]), .A2(n_0_311), .B1(n_0_728), .B2(n_0_348), + .ZN(n_0_310)); + OR2_X1_LVT i_0_327 (.A1(op2[0]), .A2(n_0_310), .ZN(n_0_309)); + OAI21_X1_LVT i_0_321 (.A(n_0_576), .B1(n_0_701), .B2(n_0_319), .ZN(n_0_303)); + INV_X1_LVT i_0_320 (.A(n_0_303), .ZN(n_0_302)); + AOI21_X1_LVT i_0_319 (.A(n_0_304), .B1(n_0_309), .B2(n_0_302), .ZN(n_0_301)); + INV_X1_LVT i_0_345 (.A(n_0_327), .ZN(n_0_326)); + OAI22_X1_LVT i_0_326 (.A1(n_0_701), .A2(n_0_326), .B1(n_0_469), .B2(n_0_309), + .ZN(n_0_308)); + NOR2_X1_LVT i_0_318 (.A1(op2[2]), .A2(n_0_393), .ZN(n_0_300)); + AOI21_X1_LVT i_0_317 (.A(n_0_300), .B1(n_0_597), .B2(n_0_498), .ZN(n_0_299)); + OAI22_X1_LVT i_0_316 (.A1(n_0_728), .A2(n_0_299), .B1(op2[1]), .B2(n_0_354), + .ZN(n_0_298)); + OAI22_X1_LVT i_0_315 (.A1(op2[0]), .A2(n_0_334), .B1(n_0_701), .B2(n_0_298), + .ZN(n_0_297)); + OAI221_X1_LVT i_0_314 (.A(n_0_301), .B1(n_0_545), .B2(n_0_308), .C1(n_0_621), + .C2(n_0_297), .ZN(result[17])); + AOI22_X1_LVT i_0_301 (.A1(n_48), .A2(n_0_580), .B1(n_16), .B2(n_0_581), + .ZN(n_0_284)); + NAND2_X1_LVT i_0_333 (.A1(n_0_544), .A2(n_0_469), .ZN(n_0_315)); + INV_X1_LVT i_0_332 (.A(n_0_315), .ZN(n_0_314)); + OAI21_X1_LVT i_0_302 (.A(n_0_681), .B1(op2[16]), .B2(n_0_568), .ZN(n_0_285)); + AOI21_X1_LVT i_0_300 (.A(n_0_314), .B1(op1[16]), .B2(n_0_285), .ZN(n_0_283)); + INV_X1_LVT i_0_772 (.A(op1[16]), .ZN(n_0_739)); + OAI221_X1_LVT i_0_303 (.A(op2[16]), .B1(op1[16]), .B2(n_0_564), .C1(n_0_739), + .C2(n_0_567), .ZN(n_0_286)); + NAND3_X1_LVT i_0_299 (.A1(n_0_284), .A2(n_0_283), .A3(n_0_286), .ZN(n_0_282)); + INV_X1_LVT i_0_593 (.A(n_0_562), .ZN(n_0_561)); + OAI22_X1_LVT i_0_307 (.A1(op1[16]), .A2(op2[3]), .B1(op1[24]), .B2(n_0_723), + .ZN(n_0_290)); + NOR2_X1_LVT i_0_306 (.A1(op2[4]), .A2(n_0_290), .ZN(n_0_289)); + AOI22_X1_LVT i_0_305 (.A1(n_0_693), .A2(n_0_289), .B1(op2[2]), .B2(n_0_371), + .ZN(n_0_288)); + OAI22_X1_LVT i_0_304 (.A1(n_0_728), .A2(n_0_330), .B1(op2[1]), .B2(n_0_288), + .ZN(n_0_287)); + AOI221_X1_LVT i_0_298 (.A(n_0_282), .B1(n_0_547), .B2(n_0_310), .C1(n_0_561), + .C2(n_0_287), .ZN(n_0_281)); + INV_X1_LVT i_0_762 (.A(op1[1]), .ZN(n_0_729)); + OAI22_X1_LVT i_0_313 (.A1(n_0_722), .A2(n_0_615), .B1(n_0_729), .B2(n_0_617), + .ZN(n_0_296)); + NAND2_X1_LVT i_0_312 (.A1(op2[2]), .A2(n_0_296), .ZN(n_0_295)); + OAI21_X1_LVT i_0_311 (.A(n_0_295), .B1(op2[2]), .B2(n_0_362), .ZN(n_0_294)); + NAND2_X1_LVT i_0_310 (.A1(op2[1]), .A2(n_0_294), .ZN(n_0_293)); + OAI21_X1_LVT i_0_309 (.A(n_0_293), .B1(op2[1]), .B2(n_0_336), .ZN(n_0_292)); + OAI22_X1_LVT i_0_308 (.A1(op2[0]), .A2(n_0_298), .B1(n_0_701), .B2(n_0_292), + .ZN(n_0_291)); + OAI21_X1_LVT i_0_297 (.A(n_0_281), .B1(n_0_621), .B2(n_0_291), .ZN(result[16])); + OAI221_X1_LVT i_0_286 (.A(op2[15]), .B1(n_0_734), .B2(n_0_567), .C1(op1[15]), + .C2(n_0_564), .ZN(n_0_270)); + AOI21_X1_LVT i_0_288 (.A(n_0_314), .B1(n_15), .B2(n_0_581), .ZN(n_0_272)); + INV_X1_LVT i_0_287 (.A(n_0_272), .ZN(n_0_271)); + OAI21_X1_LVT i_0_285 (.A(n_0_681), .B1(op2[15]), .B2(n_0_568), .ZN(n_0_269)); + AOI221_X1_LVT i_0_284 (.A(n_0_271), .B1(n_47), .B2(n_0_580), .C1(op1[15]), + .C2(n_0_269), .ZN(n_0_268)); + AOI22_X1_LVT i_0_296 (.A1(op1[8]), .A2(n_0_616), .B1(op1[0]), .B2(n_0_618), + .ZN(n_0_280)); + AOI22_X1_LVT i_0_295 (.A1(op2[2]), .A2(n_0_280), .B1(n_0_693), .B2(n_0_356), + .ZN(n_0_279)); + NAND2_X1_LVT i_0_294 (.A1(op2[1]), .A2(n_0_279), .ZN(n_0_278)); + OAI21_X1_LVT i_0_293 (.A(n_0_278), .B1(op2[1]), .B2(n_0_299), .ZN(n_0_277)); + OAI221_X1_LVT i_0_292 (.A(n_0_620), .B1(n_0_701), .B2(n_0_277), .C1(op2[0]), + .C2(n_0_292), .ZN(n_0_276)); + OAI222_X1_LVT i_0_291 (.A1(n_0_719), .A2(n_0_617), .B1(n_0_691), .B2(n_0_605), + .C1(n_0_734), .C2(n_0_615), .ZN(n_0_275)); + OAI22_X1_LVT i_0_290 (.A1(n_0_693), .A2(n_0_349), .B1(op2[2]), .B2(n_0_275), + .ZN(n_0_274)); + OAI22_X1_LVT i_0_289 (.A1(op2[1]), .A2(n_0_274), .B1(n_0_728), .B2(n_0_311), + .ZN(n_0_273)); + AOI22_X1_LVT i_0_283 (.A1(n_0_561), .A2(n_0_273), .B1(n_0_547), .B2(n_0_287), + .ZN(n_0_267)); + NAND4_X1_LVT i_0_282 (.A1(n_0_270), .A2(n_0_268), .A3(n_0_276), .A4(n_0_267), + .ZN(result[15])); + NOR2_X1_LVT i_0_278 (.A1(op2[0]), .A2(n_0_277), .ZN(n_0_263)); + NAND2_X1_LVT i_0_281 (.A1(n_0_612), .A2(n_0_575), .ZN(n_0_266)); + OAI21_X1_LVT i_0_280 (.A(n_0_266), .B1(n_0_713), .B2(n_0_497), .ZN(n_0_265)); + AOI22_X1_LVT i_0_279 (.A1(op2[1]), .A2(n_0_265), .B1(n_0_728), .B2(n_0_294), + .ZN(n_0_264)); + AOI211_X1_LVT i_0_277 (.A(n_0_263), .B(n_0_621), .C1(op2[0]), .C2(n_0_264), + .ZN(n_0_262)); + INV_X1_LVT i_0_754 (.A(op1[14]), .ZN(n_0_721)); + OAI21_X1_LVT i_0_273 (.A(op2[14]), .B1(n_0_721), .B2(n_0_567), .ZN(n_0_258)); + AOI21_X1_LVT i_0_272 (.A(n_0_258), .B1(n_0_721), .B2(n_0_565), .ZN(n_0_257)); + OAI21_X1_LVT i_0_276 (.A(n_0_681), .B1(op2[14]), .B2(n_0_568), .ZN(n_0_261)); + AOI222_X1_LVT i_0_275 (.A1(n_14), .A2(n_0_581), .B1(n_46), .B2(n_0_580), + .C1(op1[14]), .C2(n_0_261), .ZN(n_0_260)); + INV_X1_LVT i_0_274 (.A(n_0_260), .ZN(n_0_259)); + OAI222_X1_LVT i_0_271 (.A1(n_0_717), .A2(n_0_605), .B1(n_0_687), .B2(n_0_617), + .C1(n_0_721), .C2(n_0_615), .ZN(n_0_256)); + OAI22_X1_LVT i_0_270 (.A1(n_0_693), .A2(n_0_331), .B1(op2[2]), .B2(n_0_256), + .ZN(n_0_255)); + AND2_X1_LVT i_0_269 (.A1(n_0_728), .A2(n_0_255), .ZN(n_0_254)); + NOR3_X1_LVT i_0_265 (.A1(op2[3]), .A2(op2[2]), .A3(op2[0]), .ZN(n_0_250)); + AOI21_X1_LVT i_0_268 (.A(n_0_254), .B1(op2[1]), .B2(n_0_288), .ZN(n_0_253)); + OAI22_X1_LVT i_0_266 (.A1(op2[0]), .A2(n_0_253), .B1(n_0_701), .B2(n_0_273), + .ZN(n_0_251)); + AOI221_X1_LVT i_0_259 (.A(n_0_579), .B1(n_0_254), .B2(n_0_250), .C1(n_0_315), + .C2(n_0_251), .ZN(n_0_244)); + OR4_X1_LVT i_0_258 (.A1(n_0_262), .A2(n_0_257), .A3(n_0_259), .A4(n_0_244), + .ZN(result[14])); + OAI221_X1_LVT i_0_245 (.A(op2[13]), .B1(op1[13]), .B2(n_0_564), .C1(n_0_714), + .C2(n_0_567), .ZN(n_0_231)); + NAND2_X1_LVT i_0_244 (.A1(n_13), .A2(n_0_581), .ZN(n_0_230)); + OAI211_X1_LVT i_0_243 (.A(n_0_231), .B(n_0_230), .C1(n_0_714), .C2(n_0_681), + .ZN(n_0_229)); + NOR2_X1_LVT i_0_695 (.A1(op2[13]), .A2(n_0_714), .ZN(n_0_662)); + AOI221_X1_LVT i_0_242 (.A(n_0_229), .B1(n_45), .B2(n_0_580), .C1(n_0_662), + .C2(n_0_569), .ZN(n_0_228)); + INV_X1_LVT i_0_267 (.A(n_0_253), .ZN(n_0_252)); + OAI222_X1_LVT i_0_257 (.A1(n_0_714), .A2(n_0_615), .B1(n_0_726), .B2(n_0_617), + .C1(n_0_710), .C2(n_0_605), .ZN(n_0_243)); + OAI22_X1_LVT i_0_256 (.A1(n_0_693), .A2(n_0_312), .B1(op2[2]), .B2(n_0_243), + .ZN(n_0_242)); + NAND2_X1_LVT i_0_255 (.A1(n_0_728), .A2(n_0_242), .ZN(n_0_241)); + NAND2_X1_LVT i_0_254 (.A1(op2[1]), .A2(n_0_274), .ZN(n_0_240)); + NAND2_X1_LVT i_0_241 (.A1(n_0_241), .A2(n_0_240), .ZN(n_0_227)); + OAI221_X1_LVT i_0_240 (.A(n_0_228), .B1(n_0_548), .B2(n_0_252), .C1(n_0_562), + .C2(n_0_227), .ZN(n_0_226)); + NAND2_X1_LVT i_0_249 (.A1(n_0_728), .A2(n_0_279), .ZN(n_0_235)); + AOI22_X1_LVT i_0_250 (.A1(n_0_597), .A2(n_0_575), .B1(op1[6]), .B2(n_0_496), + .ZN(n_0_236)); + OAI21_X1_LVT i_0_248 (.A(n_0_235), .B1(n_0_728), .B2(n_0_236), .ZN(n_0_234)); + INV_X1_LVT i_0_247 (.A(n_0_234), .ZN(n_0_233)); + AOI221_X1_LVT i_0_246 (.A(n_0_621), .B1(op2[0]), .B2(n_0_233), .C1(n_0_701), + .C2(n_0_264), .ZN(n_0_232)); + NAND2_X1_LVT i_0_264 (.A1(op2[3]), .A2(n_0_469), .ZN(n_0_249)); + AOI21_X1_LVT i_0_262 (.A(n_0_468), .B1(n_0_693), .B2(n_0_249), .ZN(n_0_247)); + INV_X1_LVT i_0_261 (.A(n_0_247), .ZN(n_0_246)); + OAI211_X1_LVT i_0_260 (.A(n_0_252), .B(n_0_246), .C1(n_0_468), .C2(n_0_254), + .ZN(n_0_245)); + OAI221_X1_LVT i_0_253 (.A(n_0_544), .B1(n_0_247), .B2(n_0_241), .C1(n_0_469), + .C2(n_0_240), .ZN(n_0_239)); + INV_X1_LVT i_0_252 (.A(n_0_239), .ZN(n_0_238)); + AOI211_X1_LVT i_0_239 (.A(n_0_226), .B(n_0_232), .C1(n_0_245), .C2(n_0_238), + .ZN(n_0_225)); + INV_X1_LVT i_0_238 (.A(n_0_225), .ZN(result[13])); + OAI221_X1_LVT i_0_232 (.A(op2[12]), .B1(n_0_696), .B2(n_0_567), .C1(op1[12]), + .C2(n_0_564), .ZN(n_0_219)); + OAI21_X1_LVT i_0_231 (.A(n_0_681), .B1(op2[12]), .B2(n_0_568), .ZN(n_0_218)); + AOI222_X1_LVT i_0_230 (.A1(n_12), .A2(n_0_581), .B1(op1[12]), .B2(n_0_218), + .C1(n_44), .C2(n_0_580), .ZN(n_0_217)); + OAI21_X1_LVT i_0_234 (.A(n_0_620), .B1(op2[1]), .B2(n_0_265), .ZN(n_0_221)); + INV_X1_LVT i_0_763 (.A(op1[5]), .ZN(n_0_730)); + OAI21_X1_LVT i_0_236 (.A(op2[2]), .B1(n_0_730), .B2(n_0_615), .ZN(n_0_223)); + OAI21_X1_LVT i_0_235 (.A(n_0_223), .B1(op2[2]), .B2(n_0_296), .ZN(n_0_222)); + AOI21_X1_LVT i_0_233 (.A(n_0_221), .B1(op2[1]), .B2(n_0_222), .ZN(n_0_220)); + NOR2_X1_LVT i_0_237 (.A1(n_0_577), .A2(n_0_227), .ZN(n_0_224)); + NOR4_X1_LVT i_0_223 (.A1(n_0_701), .A2(n_0_220), .A3(n_0_224), .A4(n_0_238), + .ZN(n_0_210)); + NAND2_X1_LVT i_0_224 (.A1(n_0_544), .A2(n_0_247), .ZN(n_0_211)); + NAND2_X1_LVT i_0_222 (.A1(n_0_701), .A2(n_0_211), .ZN(n_0_209)); + OAI22_X1_LVT i_0_229 (.A1(op2[4]), .A2(n_0_696), .B1(n_0_738), .B2(n_0_698), + .ZN(n_0_216)); + INV_X1_LVT i_0_228 (.A(n_0_216), .ZN(n_0_215)); + OAI22_X1_LVT i_0_227 (.A1(n_0_727), .A2(n_0_617), .B1(op2[3]), .B2(n_0_215), + .ZN(n_0_214)); + OAI22_X1_LVT i_0_226 (.A1(n_0_693), .A2(n_0_289), .B1(op2[2]), .B2(n_0_214), + .ZN(n_0_213)); + OAI22_X1_LVT i_0_225 (.A1(op2[1]), .A2(n_0_213), .B1(n_0_728), .B2(n_0_255), + .ZN(n_0_212)); + AOI221_X1_LVT i_0_221 (.A(n_0_209), .B1(n_0_578), .B2(n_0_212), .C1(n_0_620), + .C2(n_0_234), .ZN(n_0_208)); + OAI211_X1_LVT i_0_220 (.A(n_0_219), .B(n_0_217), .C1(n_0_210), .C2(n_0_208), + .ZN(result[12])); + OAI21_X1_LVT i_0_209 (.A(n_0_681), .B1(op2[11]), .B2(n_0_568), .ZN(n_0_197)); + AOI22_X1_LVT i_0_208 (.A1(n_11), .A2(n_0_581), .B1(op1[11]), .B2(n_0_197), + .ZN(n_0_196)); + NAND2_X1_LVT i_0_207 (.A1(n_0_211), .A2(n_0_196), .ZN(n_0_195)); + AOI22_X1_LVT i_0_210 (.A1(op1[11]), .A2(n_0_566), .B1(n_0_706), .B2(n_0_565), + .ZN(n_0_198)); + AOI221_X1_LVT i_0_206 (.A(n_0_195), .B1(op2[11]), .B2(n_0_198), .C1(n_43), + .C2(n_0_580), .ZN(n_0_194)); + AOI221_X1_LVT i_0_215 (.A(op2[3]), .B1(n_0_738), .B2(n_0_706), .C1(op2[4]), + .C2(n_0_688), .ZN(n_0_203)); + AOI21_X1_LVT i_0_214 (.A(n_0_203), .B1(op1[19]), .B2(n_0_618), .ZN(n_0_202)); + NAND2_X1_LVT i_0_213 (.A1(n_0_693), .A2(n_0_202), .ZN(n_0_201)); + OAI21_X1_LVT i_0_212 (.A(n_0_201), .B1(n_0_693), .B2(n_0_275), .ZN(n_0_200)); + OAI22_X1_LVT i_0_211 (.A1(n_0_728), .A2(n_0_242), .B1(op2[1]), .B2(n_0_200), + .ZN(n_0_199)); + AOI22_X1_LVT i_0_205 (.A1(n_0_561), .A2(n_0_199), .B1(n_0_701), .B2(n_0_220), + .ZN(n_0_193)); + NOR2_X1_LVT i_0_219 (.A1(op2[2]), .A2(n_0_280), .ZN(n_0_207)); + AOI21_X1_LVT i_0_218 (.A(n_0_207), .B1(op1[4]), .B2(n_0_496), .ZN(n_0_206)); + AOI22_X1_LVT i_0_217 (.A1(n_0_728), .A2(n_0_236), .B1(op2[1]), .B2(n_0_206), + .ZN(n_0_205)); + AOI22_X1_LVT i_0_216 (.A1(n_0_578), .A2(n_0_212), .B1(n_0_620), .B2(n_0_205), + .ZN(n_0_204)); + OAI211_X1_LVT i_0_204 (.A(n_0_194), .B(n_0_193), .C1(n_0_701), .C2(n_0_204), + .ZN(result[11])); + AOI22_X1_LVT i_0_194 (.A1(n_0_654), .A2(n_0_498), .B1(op1[7]), .B2(n_0_573), + .ZN(n_0_183)); + OAI22_X1_LVT i_0_193 (.A1(n_0_728), .A2(n_0_183), .B1(op2[1]), .B2(n_0_222), + .ZN(n_0_182)); + AOI22_X1_LVT i_0_192 (.A1(op2[0]), .A2(n_0_182), .B1(n_0_701), .B2(n_0_205), + .ZN(n_0_181)); + NOR2_X1_LVT i_0_191 (.A1(n_0_621), .A2(n_0_181), .ZN(n_0_180)); + AOI22_X1_LVT i_0_190 (.A1(op1[10]), .A2(n_0_566), .B1(n_0_733), .B2(n_0_565), + .ZN(n_0_179)); + AOI22_X1_LVT i_0_188 (.A1(op2[10]), .A2(n_0_179), .B1(n_42), .B2(n_0_580), + .ZN(n_0_177)); + OAI21_X1_LVT i_0_189 (.A(n_0_681), .B1(op2[10]), .B2(n_0_568), .ZN(n_0_178)); + AOI22_X1_LVT i_0_187 (.A1(n_10), .A2(n_0_581), .B1(op1[10]), .B2(n_0_178), + .ZN(n_0_176)); + NAND2_X1_LVT i_0_186 (.A1(n_0_177), .A2(n_0_176), .ZN(n_0_175)); + NOR2_X1_LVT i_0_203 (.A1(n_0_701), .A2(n_0_199), .ZN(n_0_192)); + NOR2_X1_LVT i_0_200 (.A1(n_0_693), .A2(n_0_256), .ZN(n_0_189)); + AOI221_X1_LVT i_0_202 (.A(n_0_596), .B1(op1[10]), .B2(n_0_616), .C1(op1[26]), + .C2(n_0_606), .ZN(n_0_191)); + AOI21_X1_LVT i_0_199 (.A(n_0_189), .B1(n_0_693), .B2(n_0_191), .ZN(n_0_188)); + OR2_X1_LVT i_0_198 (.A1(op2[1]), .A2(n_0_188), .ZN(n_0_187)); + NAND2_X1_LVT i_0_197 (.A1(op2[1]), .A2(n_0_213), .ZN(n_0_186)); + NAND2_X1_LVT i_0_185 (.A1(n_0_187), .A2(n_0_186), .ZN(n_0_174)); + AOI211_X1_LVT i_0_184 (.A(n_0_577), .B(n_0_192), .C1(n_0_701), .C2(n_0_174), + .ZN(n_0_173)); + INV_X1_LVT i_0_263 (.A(n_0_249), .ZN(n_0_248)); + OAI22_X1_LVT i_0_196 (.A1(n_0_248), .A2(n_0_187), .B1(n_0_247), .B2(n_0_186), + .ZN(n_0_185)); + AOI221_X1_LVT i_0_195 (.A(n_0_545), .B1(n_0_246), .B2(n_0_192), .C1(n_0_701), + .C2(n_0_185), .ZN(n_0_184)); + OR4_X1_LVT i_0_183 (.A1(n_0_180), .A2(n_0_175), .A3(n_0_173), .A4(n_0_184), + .ZN(result[10])); + INV_X1_LVT i_0_753 (.A(op2[9]), .ZN(n_0_720)); + AOI221_X1_LVT i_0_171 (.A(n_0_720), .B1(op1[9]), .B2(n_0_566), .C1(n_0_722), + .C2(n_0_565), .ZN(n_0_161)); + AOI22_X1_LVT i_0_172 (.A1(n_9), .A2(n_0_581), .B1(n_41), .B2(n_0_580), + .ZN(n_0_162)); + AOI21_X1_LVT i_0_170 (.A(aluBypass), .B1(n_0_720), .B2(n_0_569), .ZN(n_0_160)); + OAI21_X1_LVT i_0_169 (.A(n_0_162), .B1(n_0_722), .B2(n_0_160), .ZN(n_0_159)); + OAI222_X1_LVT i_0_182 (.A1(n_0_722), .A2(n_0_615), .B1(n_0_699), .B2(n_0_605), + .C1(n_0_732), .C2(n_0_617), .ZN(n_0_172)); + AOI22_X1_LVT i_0_181 (.A1(n_0_693), .A2(n_0_172), .B1(op2[2]), .B2(n_0_243), + .ZN(n_0_171)); + NAND2_X1_LVT i_0_180 (.A1(n_0_728), .A2(n_0_171), .ZN(n_0_170)); + NAND2_X1_LVT i_0_179 (.A1(op2[1]), .A2(n_0_200), .ZN(n_0_169)); + OAI22_X1_LVT i_0_178 (.A1(n_0_248), .A2(n_0_170), .B1(n_0_247), .B2(n_0_169), + .ZN(n_0_168)); + NOR3_X1_LVT i_0_177 (.A1(n_0_545), .A2(n_0_168), .A3(n_0_185), .ZN(n_0_167)); + NOR2_X1_LVT i_0_251 (.A1(n_0_704), .A2(n_0_615), .ZN(n_0_237)); + OAI22_X1_LVT i_0_176 (.A1(op1[2]), .A2(n_0_693), .B1(n_0_496), .B2(n_0_237), + .ZN(n_0_166)); + OAI22_X1_LVT i_0_175 (.A1(op2[1]), .A2(n_0_206), .B1(n_0_728), .B2(n_0_166), + .ZN(n_0_165)); + OAI221_X1_LVT i_0_174 (.A(n_0_620), .B1(op2[0]), .B2(n_0_182), .C1(n_0_701), + .C2(n_0_165), .ZN(n_0_164)); + NAND2_X1_LVT i_0_173 (.A1(n_0_170), .A2(n_0_169), .ZN(n_0_163)); + OAI221_X1_LVT i_0_168 (.A(n_0_164), .B1(n_0_562), .B2(n_0_163), .C1(n_0_548), + .C2(n_0_174), .ZN(n_0_158)); + OR4_X1_LVT i_0_167 (.A1(n_0_161), .A2(n_0_159), .A3(n_0_167), .A4(n_0_158), + .ZN(result[9])); + OAI21_X1_LVT i_0_160 (.A(n_0_693), .B1(n_0_730), .B2(n_0_615), .ZN(n_0_151)); + OAI21_X1_LVT i_0_159 (.A(op2[2]), .B1(n_0_729), .B2(n_0_615), .ZN(n_0_150)); + AND2_X1_LVT i_0_158 (.A1(n_0_151), .A2(n_0_150), .ZN(n_0_149)); + NAND2_X1_LVT i_0_157 (.A1(op2[1]), .A2(n_0_149), .ZN(n_0_148)); + OAI21_X1_LVT i_0_156 (.A(n_0_148), .B1(op2[1]), .B2(n_0_183), .ZN(n_0_147)); + OAI22_X1_LVT i_0_155 (.A1(op2[0]), .A2(n_0_165), .B1(n_0_701), .B2(n_0_147), + .ZN(n_0_146)); + NOR2_X1_LVT i_0_154 (.A1(n_0_621), .A2(n_0_146), .ZN(n_0_145)); + INV_X1_LVT i_0_773 (.A(op1[8]), .ZN(n_0_740)); + NOR2_X1_LVT i_0_688 (.A1(n_0_740), .A2(op2[8]), .ZN(n_0_655)); + AOI22_X1_LVT i_0_153 (.A1(op1[8]), .A2(aluBypass), .B1(n_0_655), .B2(n_0_569), + .ZN(n_0_144)); + OAI221_X1_LVT i_0_152 (.A(op2[8]), .B1(op1[8]), .B2(n_0_564), .C1(n_0_740), + .C2(n_0_567), .ZN(n_0_143)); + AOI22_X1_LVT i_0_151 (.A1(n_40), .A2(n_0_580), .B1(n_8), .B2(n_0_581), + .ZN(n_0_142)); + NAND3_X1_LVT i_0_150 (.A1(n_0_144), .A2(n_0_143), .A3(n_0_142), .ZN(n_0_141)); + OAI222_X1_LVT i_0_166 (.A1(n_0_740), .A2(n_0_615), .B1(n_0_739), .B2(n_0_617), + .C1(n_0_736), .C2(n_0_605), .ZN(n_0_157)); + OAI22_X1_LVT i_0_165 (.A1(op2[2]), .A2(n_0_157), .B1(n_0_693), .B2(n_0_214), + .ZN(n_0_156)); + NOR2_X1_LVT i_0_164 (.A1(op2[1]), .A2(n_0_156), .ZN(n_0_155)); + AOI21_X1_LVT i_0_163 (.A(n_0_155), .B1(op2[1]), .B2(n_0_188), .ZN(n_0_154)); + AND2_X1_LVT i_0_162 (.A1(n_0_701), .A2(n_0_154), .ZN(n_0_153)); + AOI211_X1_LVT i_0_149 (.A(n_0_577), .B(n_0_153), .C1(op2[0]), .C2(n_0_163), + .ZN(n_0_140)); + AOI221_X1_LVT i_0_161 (.A(n_0_545), .B1(op2[0]), .B2(n_0_168), .C1(n_0_249), + .C2(n_0_153), .ZN(n_0_152)); + OR4_X1_LVT i_0_148 (.A1(n_0_145), .A2(n_0_141), .A3(n_0_140), .A4(n_0_152), + .ZN(result[8])); + AOI22_X1_LVT i_0_138 (.A1(op1[4]), .A2(n_0_573), .B1(op1[0]), .B2(n_0_496), + .ZN(n_0_130)); + AOI22_X1_LVT i_0_137 (.A1(op2[1]), .A2(n_0_130), .B1(n_0_728), .B2(n_0_166), + .ZN(n_0_129)); + OAI22_X1_LVT i_0_136 (.A1(n_0_701), .A2(n_0_129), .B1(op2[0]), .B2(n_0_147), + .ZN(n_0_128)); + NOR2_X1_LVT i_0_135 (.A1(n_0_621), .A2(n_0_128), .ZN(n_0_127)); + OAI221_X1_LVT i_0_139 (.A(op2[7]), .B1(n_0_713), .B2(n_0_567), .C1(op1[7]), + .C2(n_0_564), .ZN(n_0_131)); + AOI22_X1_LVT i_0_141 (.A1(n_7), .A2(n_0_581), .B1(n_39), .B2(n_0_580), + .ZN(n_0_133)); + INV_X1_LVT i_0_745 (.A(op2[7]), .ZN(n_0_712)); + AOI21_X1_LVT i_0_140 (.A(aluBypass), .B1(n_0_712), .B2(n_0_569), .ZN(n_0_132)); + OAI211_X1_LVT i_0_133 (.A(n_0_131), .B(n_0_133), .C1(n_0_713), .C2(n_0_132), + .ZN(n_0_125)); + OAI22_X1_LVT i_0_147 (.A1(n_0_734), .A2(n_0_617), .B1(n_0_713), .B2(n_0_615), + .ZN(n_0_139)); + AOI211_X1_LVT i_0_146 (.A(n_0_139), .B(n_0_248), .C1(op1[23]), .C2(n_0_606), + .ZN(n_0_138)); + OAI22_X1_LVT i_0_145 (.A1(n_0_693), .A2(n_0_202), .B1(op2[2]), .B2(n_0_138), + .ZN(n_0_137)); + NOR2_X1_LVT i_0_144 (.A1(op2[1]), .A2(n_0_137), .ZN(n_0_136)); + AOI21_X1_LVT i_0_143 (.A(n_0_136), .B1(op2[1]), .B2(n_0_171), .ZN(n_0_135)); + NAND2_X1_LVT i_0_142 (.A1(n_0_561), .A2(n_0_135), .ZN(n_0_134)); + OAI221_X1_LVT i_0_134 (.A(n_0_134), .B1(n_0_548), .B2(n_0_154), .C1(n_0_545), + .C2(n_0_249), .ZN(n_0_126)); + OR3_X1_LVT i_0_132 (.A1(n_0_127), .A2(n_0_125), .A3(n_0_126), .ZN(result[7])); + NAND2_X1_LVT i_0_124 (.A1(n_0_728), .A2(n_0_149), .ZN(n_0_117)); + OAI21_X1_LVT i_0_123 (.A(n_0_117), .B1(n_0_724), .B2(n_0_531), .ZN(n_0_116)); + OAI22_X1_LVT i_0_122 (.A1(n_0_701), .A2(n_0_116), .B1(op2[0]), .B2(n_0_129), + .ZN(n_0_115)); + NOR2_X1_LVT i_0_121 (.A1(n_0_621), .A2(n_0_115), .ZN(n_0_114)); + AOI22_X1_LVT i_0_119 (.A1(n_6), .A2(n_0_581), .B1(n_38), .B2(n_0_580), + .ZN(n_0_112)); + INV_X1_LVT i_0_735 (.A(op2[6]), .ZN(n_0_702)); + AOI21_X1_LVT i_0_120 (.A(aluBypass), .B1(n_0_702), .B2(n_0_569), .ZN(n_0_113)); + OAI21_X1_LVT i_0_118 (.A(n_0_112), .B1(n_0_704), .B2(n_0_113), .ZN(n_0_111)); + AOI221_X1_LVT i_0_117 (.A(n_0_702), .B1(n_0_704), .B2(n_0_565), .C1(op1[6]), + .C2(n_0_566), .ZN(n_0_110)); + NOR3_X1_LVT i_0_116 (.A1(n_0_114), .A2(n_0_111), .A3(n_0_110), .ZN(n_0_109)); + AOI221_X1_LVT i_0_131 (.A(n_0_237), .B1(op1[14]), .B2(n_0_618), .C1(op2[4]), + .C2(n_0_406), .ZN(n_0_124)); + NAND2_X1_LVT i_0_130 (.A1(n_0_693), .A2(n_0_124), .ZN(n_0_123)); + INV_X1_LVT i_0_201 (.A(n_0_191), .ZN(n_0_190)); + OAI21_X1_LVT i_0_129 (.A(n_0_123), .B1(n_0_693), .B2(n_0_190), .ZN(n_0_122)); + AOI22_X1_LVT i_0_128 (.A1(n_0_728), .A2(n_0_122), .B1(op2[1]), .B2(n_0_156), + .ZN(n_0_121)); + INV_X1_LVT i_0_127 (.A(n_0_121), .ZN(n_0_120)); + OAI21_X1_LVT i_0_126 (.A(n_0_248), .B1(op2[1]), .B2(n_0_123), .ZN(n_0_119)); + AND2_X1_LVT i_0_125 (.A1(n_0_120), .A2(n_0_119), .ZN(n_0_118)); + NOR2_X1_LVT i_0_115 (.A1(n_0_545), .A2(n_0_118), .ZN(n_0_108)); + AOI21_X1_LVT i_0_114 (.A(n_0_108), .B1(n_0_576), .B2(n_0_121), .ZN(n_0_107)); + AOI22_X1_LVT i_0_113 (.A1(n_0_544), .A2(n_0_248), .B1(n_0_578), .B2(n_0_135), + .ZN(n_0_106)); + OAI221_X1_LVT i_0_112 (.A(n_0_109), .B1(op2[0]), .B2(n_0_107), .C1(n_0_701), + .C2(n_0_106), .ZN(result[6])); + OAI221_X1_LVT i_0_100 (.A(op2[5]), .B1(op1[5]), .B2(n_0_564), .C1(n_0_730), + .C2(n_0_567), .ZN(n_0_94)); + INV_X1_LVT i_0_764 (.A(op2[5]), .ZN(n_0_731)); + AOI21_X1_LVT i_0_99 (.A(aluBypass), .B1(n_0_731), .B2(n_0_569), .ZN(n_0_93)); + NOR2_X1_LVT i_0_98 (.A1(n_0_730), .A2(n_0_93), .ZN(n_0_92)); + AOI221_X1_LVT i_0_97 (.A(n_0_92), .B1(n_37), .B2(n_0_580), .C1(n_5), .C2( + n_0_581), .ZN(n_0_91)); + OAI22_X1_LVT i_0_102 (.A1(n_0_694), .A2(n_0_531), .B1(op2[1]), .B2(n_0_130), + .ZN(n_0_96)); + OAI221_X1_LVT i_0_101 (.A(n_0_620), .B1(n_0_701), .B2(n_0_96), .C1(op2[0]), + .C2(n_0_116), .ZN(n_0_95)); + NAND3_X1_LVT i_0_111 (.A1(n_0_544), .A2(n_0_248), .A3(op2[2]), .ZN(n_0_105)); + NAND2_X1_LVT i_0_110 (.A1(op2[4]), .A2(n_0_386), .ZN(n_0_104)); + OAI21_X1_LVT i_0_109 (.A(n_0_104), .B1(n_0_714), .B2(n_0_617), .ZN(n_0_103)); + OAI22_X1_LVT i_0_108 (.A1(n_0_151), .A2(n_0_103), .B1(n_0_693), .B2(n_0_172), + .ZN(n_0_102)); + NOR2_X1_LVT i_0_107 (.A1(op2[1]), .A2(n_0_102), .ZN(n_0_101)); + AOI21_X1_LVT i_0_106 (.A(n_0_101), .B1(op2[1]), .B2(n_0_137), .ZN(n_0_100)); + OAI21_X1_LVT i_0_105 (.A(n_0_105), .B1(n_0_579), .B2(n_0_100), .ZN(n_0_99)); + AOI21_X1_LVT i_0_104 (.A(n_0_118), .B1(n_0_682), .B2(n_0_120), .ZN(n_0_98)); + OAI22_X1_LVT i_0_103 (.A1(n_0_547), .A2(n_0_99), .B1(n_0_701), .B2(n_0_98), + .ZN(n_0_97)); + NAND4_X1_LVT i_0_96 (.A1(n_0_94), .A2(n_0_91), .A3(n_0_95), .A4(n_0_97), + .ZN(result[5])); + AOI222_X1_LVT i_0_89 (.A1(n_4), .A2(n_0_581), .B1(n_36), .B2(n_0_580), + .C1(n_0_668), .C2(n_0_564), .ZN(n_0_84)); + INV_X1_LVT i_0_770 (.A(op1[4]), .ZN(n_0_737)); + AOI221_X1_LVT i_0_90 (.A(aluBypass), .B1(op2[4]), .B2(n_0_567), .C1(n_0_738), + .C2(n_0_569), .ZN(n_0_85)); + OAI21_X1_LVT i_0_88 (.A(n_0_84), .B1(n_0_737), .B2(n_0_85), .ZN(n_0_83)); + NOR2_X1_LVT i_0_689 (.A1(op2[4]), .A2(n_0_737), .ZN(n_0_656)); + AOI21_X1_LVT i_0_95 (.A(n_0_616), .B1(n_0_727), .B2(n_0_723), .ZN(n_0_90)); + OAI22_X1_LVT i_0_94 (.A1(n_0_723), .A2(n_0_216), .B1(n_0_656), .B2(n_0_90), + .ZN(n_0_89)); + INV_X1_LVT i_0_93 (.A(n_0_89), .ZN(n_0_88)); + OAI22_X1_LVT i_0_92 (.A1(op2[2]), .A2(n_0_88), .B1(n_0_693), .B2(n_0_157), + .ZN(n_0_87)); + OAI221_X1_LVT i_0_91 (.A(n_0_105), .B1(n_0_728), .B2(n_0_122), .C1(op2[1]), + .C2(n_0_87), .ZN(n_0_86)); + AOI221_X1_LVT i_0_85 (.A(n_0_83), .B1(n_0_561), .B2(n_0_86), .C1(op2[0]), + .C2(n_0_99), .ZN(n_0_80)); + AOI221_X1_LVT i_0_87 (.A(n_0_574), .B1(n_0_729), .B2(op2[1]), .C1(n_0_728), + .C2(n_0_724), .ZN(n_0_82)); + OAI22_X1_LVT i_0_86 (.A1(op2[0]), .A2(n_0_96), .B1(n_0_701), .B2(n_0_82), + .ZN(n_0_81)); + OAI21_X1_LVT i_0_84 (.A(n_0_80), .B1(n_0_621), .B2(n_0_81), .ZN(result[4])); + AND2_X1_LVT i_0_81 (.A1(op2[1]), .A2(n_0_105), .ZN(n_0_77)); + NAND2_X1_LVT i_0_80 (.A1(n_0_102), .A2(n_0_77), .ZN(n_0_76)); + OAI221_X1_LVT i_0_83 (.A(n_0_693), .B1(n_0_654), .B2(n_0_484), .C1(n_0_738), + .C2(n_0_350), .ZN(n_0_79)); + OAI21_X1_LVT i_0_82 (.A(n_0_79), .B1(n_0_693), .B2(n_0_138), .ZN(n_0_78)); + OAI21_X1_LVT i_0_79 (.A(n_0_76), .B1(op2[1]), .B2(n_0_78), .ZN(n_0_75)); + NOR2_X1_LVT i_0_78 (.A1(n_0_562), .A2(n_0_75), .ZN(n_0_74)); + AOI22_X1_LVT i_0_75 (.A1(n_35), .A2(n_0_580), .B1(n_3), .B2(n_0_581), + .ZN(n_0_71)); + OAI21_X1_LVT i_0_74 (.A(n_0_681), .B1(n_0_723), .B2(n_0_566), .ZN(n_0_70)); + AOI222_X1_LVT i_0_73 (.A1(n_0_654), .A2(n_0_569), .B1(n_0_663), .B2(n_0_564), + .C1(op1[3]), .C2(n_0_70), .ZN(n_0_69)); + INV_X1_LVT i_0_736 (.A(op1[0]), .ZN(n_0_703)); + OAI22_X1_LVT i_0_77 (.A1(n_0_703), .A2(n_0_531), .B1(n_0_694), .B2(n_0_572), + .ZN(n_0_73)); + OAI22_X1_LVT i_0_76 (.A1(n_0_701), .A2(n_0_73), .B1(op2[0]), .B2(n_0_82), + .ZN(n_0_72)); + OAI211_X1_LVT i_0_72 (.A(n_0_71), .B(n_0_69), .C1(n_0_621), .C2(n_0_72), + .ZN(n_0_68)); + AOI211_X1_LVT i_0_71 (.A(n_0_74), .B(n_0_68), .C1(n_0_547), .C2(n_0_86), + .ZN(n_0_67)); + INV_X1_LVT i_0_70 (.A(n_0_67), .ZN(result[3])); + NAND2_X1_LVT i_0_65 (.A1(n_2), .A2(n_0_581), .ZN(n_0_62)); + OAI221_X1_LVT i_0_66 (.A(op2[2]), .B1(op1[2]), .B2(n_0_564), .C1(n_0_694), + .C2(n_0_567), .ZN(n_0_63)); + AOI21_X1_LVT i_0_64 (.A(aluBypass), .B1(n_0_693), .B2(n_0_569), .ZN(n_0_61)); + OAI21_X1_LVT i_0_63 (.A(n_0_63), .B1(n_0_694), .B2(n_0_61), .ZN(n_0_60)); + AOI21_X1_LVT i_0_62 (.A(n_0_60), .B1(n_34), .B2(n_0_580), .ZN(n_0_59)); + OAI211_X1_LVT i_0_57 (.A(n_0_62), .B(n_0_59), .C1(n_0_548), .C2(n_0_75), + .ZN(n_0_54)); + NOR2_X1_LVT i_0_698 (.A1(n_0_729), .A2(op2[1]), .ZN(n_0_665)); + INV_X1_LVT i_0_697 (.A(n_0_665), .ZN(n_0_664)); + OAI21_X1_LVT i_0_69 (.A(op2[0]), .B1(n_0_664), .B2(n_0_574), .ZN(n_0_66)); + OAI21_X1_LVT i_0_68 (.A(n_0_620), .B1(op2[0]), .B2(n_0_73), .ZN(n_0_65)); + INV_X1_LVT i_0_67 (.A(n_0_65), .ZN(n_0_64)); + OAI222_X1_LVT i_0_61 (.A1(op1[10]), .A2(n_0_617), .B1(op1[2]), .B2(n_0_615), + .C1(n_0_738), .C2(n_0_332), .ZN(n_0_58)); + OAI22_X1_LVT i_0_60 (.A1(op2[2]), .A2(n_0_58), .B1(n_0_693), .B2(n_0_124), + .ZN(n_0_57)); + INV_X1_LVT i_0_59 (.A(n_0_57), .ZN(n_0_56)); + AOI22_X1_LVT i_0_58 (.A1(n_0_728), .A2(n_0_56), .B1(n_0_87), .B2(n_0_77), + .ZN(n_0_55)); + AOI221_X1_LVT i_0_56 (.A(n_0_54), .B1(n_0_66), .B2(n_0_64), .C1(n_0_561), + .C2(n_0_55), .ZN(n_0_53)); + INV_X1_LVT i_0_55 (.A(n_0_53), .ZN(result[2])); + NAND2_X1_LVT i_0_54 (.A1(n_0_547), .A2(n_0_55), .ZN(n_0_52)); + AOI221_X1_LVT i_0_47 (.A(n_0_728), .B1(n_0_729), .B2(n_0_565), .C1(op1[1]), + .C2(n_0_566), .ZN(n_0_45)); + NOR2_X1_LVT i_0_700 (.A1(op1[0]), .A2(n_0_701), .ZN(n_0_667)); + AOI211_X1_LVT i_0_48 (.A(n_0_667), .B(n_0_621), .C1(n_0_729), .C2(n_0_701), + .ZN(n_0_46)); + AOI221_X1_LVT i_0_44 (.A(n_0_45), .B1(op1[1]), .B2(aluBypass), .C1(n_0_571), + .C2(n_0_46), .ZN(n_0_42)); + AOI22_X1_LVT i_0_49 (.A1(n_33), .A2(n_0_580), .B1(n_1), .B2(n_0_581), + .ZN(n_0_47)); + OAI21_X1_LVT i_0_46 (.A(n_0_47), .B1(n_0_664), .B2(n_0_568), .ZN(n_0_44)); + NAND2_X1_LVT i_0_51 (.A1(op2[1]), .A2(n_0_78), .ZN(n_0_49)); + OAI222_X1_LVT i_0_53 (.A1(n_0_722), .A2(n_0_617), .B1(n_0_729), .B2(n_0_615), + .C1(n_0_738), .C2(n_0_313), .ZN(n_0_51)); + OAI22_X1_LVT i_0_52 (.A1(n_0_223), .A2(n_0_103), .B1(op2[2]), .B2(n_0_51), + .ZN(n_0_50)); + OAI21_X1_LVT i_0_50 (.A(n_0_49), .B1(op2[1]), .B2(n_0_50), .ZN(n_0_48)); + AOI21_X1_LVT i_0_45 (.A(n_0_44), .B1(n_0_561), .B2(n_0_48), .ZN(n_0_43)); + NAND3_X1_LVT i_0_43 (.A1(n_0_52), .A2(n_0_42), .A3(n_0_43), .ZN(result[1])); + OAI222_X1_LVT i_0_11 (.A1(n_0_740), .A2(n_0_617), .B1(n_0_703), .B2(n_0_615), + .C1(n_0_738), .C2(n_0_290), .ZN(n_0_10)); + OAI22_X1_LVT i_0_10 (.A1(op2[2]), .A2(n_0_10), .B1(n_0_693), .B2(n_0_88), + .ZN(n_0_9)); + OAI221_X1_LVT i_0_9 (.A(n_0_701), .B1(n_0_728), .B2(n_0_56), .C1(op2[1]), + .C2(n_0_9), .ZN(n_0_8)); + OAI21_X1_LVT i_0_8 (.A(n_0_8), .B1(n_0_701), .B2(n_0_48), .ZN(n_0_7)); + NOR2_X1_LVT i_0_7 (.A1(n_0_579), .A2(n_0_7), .ZN(n_0_6)); + OAI221_X1_LVT i_0_3 (.A(op2[0]), .B1(op1[0]), .B2(n_0_564), .C1(n_0_703), + .C2(n_0_567), .ZN(n_0_2)); + AOI22_X1_LVT i_0_2 (.A1(n_32), .A2(n_0_580), .B1(n_0), .B2(n_0_581), .ZN( + n_0_1)); + NAND3_X1_LVT i_0_6 (.A1(n_0_701), .A2(n_0_571), .A3(n_0_620), .ZN(n_0_5)); + OAI211_X1_LVT i_0_5 (.A(n_0_681), .B(n_0_5), .C1(op2[0]), .C2(n_0_568), + .ZN(n_0_4)); + NAND2_X1_LVT i_0_4 (.A1(op1[0]), .A2(n_0_4), .ZN(n_0_3)); + NAND3_X1_LVT i_0_1 (.A1(n_0_2), .A2(n_0_1), .A3(n_0_3), .ZN(n_0_0)); + OAI33_X1_LVT i_0_14 (.A1(n_0_692), .A2(op1[31]), .A3(n_0_683), .B1(op2[31]), + .B2(n_0_691), .B3(aluOp[0]), .ZN(n_0_13)); + INV_X1_LVT i_0_741 (.A(op2[29]), .ZN(n_0_708)); + NAND2_X1_LVT i_0_685 (.A1(op1[29]), .A2(n_0_708), .ZN(n_0_652)); + OAI22_X1_LVT i_0_713 (.A1(n_0_700), .A2(op1[28]), .B1(op1[29]), .B2(n_0_708), + .ZN(n_0_680)); + NAND2_X1_LVT i_0_694 (.A1(n_0_688), .A2(op2[27]), .ZN(n_0_661)); + INV_X1_LVT i_0_742 (.A(op2[26]), .ZN(n_0_709)); + OAI22_X1_LVT i_0_712 (.A1(n_0_699), .A2(op2[25]), .B1(n_0_736), .B2(op2[24]), + .ZN(n_0_679)); + NAND2_X1_LVT i_0_690 (.A1(n_0_727), .A2(op2[20]), .ZN(n_0_657)); + INV_X1_LVT i_0_740 (.A(op2[18]), .ZN(n_0_707)); + OAI22_X1_LVT i_0_711 (.A1(n_0_707), .A2(op1[18]), .B1(n_0_690), .B2(op1[19]), + .ZN(n_0_678)); + OAI22_X1_LVT i_0_29 (.A1(n_0_739), .A2(op2[16]), .B1(n_0_734), .B2(op2[15]), + .ZN(n_0_28)); + INV_X1_LVT i_0_728 (.A(op2[12]), .ZN(n_0_695)); + INV_X1_LVT i_0_748 (.A(op2[13]), .ZN(n_0_715)); + OAI22_X1_LVT i_0_704 (.A1(n_0_706), .A2(op2[11]), .B1(n_0_696), .B2(op2[12]), + .ZN(n_0_671)); + AOI22_X1_LVT i_0_710 (.A1(n_0_740), .A2(op2[8]), .B1(n_0_713), .B2(op2[7]), + .ZN(n_0_677)); + OAI22_X1_LVT i_0_707 (.A1(n_0_731), .A2(op1[5]), .B1(op1[6]), .B2(n_0_702), + .ZN(n_0_674)); + OAI22_X1_LVT i_0_706 (.A1(op1[2]), .A2(n_0_693), .B1(op1[1]), .B2(n_0_728), + .ZN(n_0_673)); + INV_X1_LVT i_0_705 (.A(n_0_673), .ZN(n_0_672)); + INV_X1_LVT i_0_699 (.A(n_0_667), .ZN(n_0_666)); + OAI21_X1_LVT i_0_42 (.A(n_0_672), .B1(n_0_666), .B2(n_0_665), .ZN(n_0_41)); + AOI21_X1_LVT i_0_41 (.A(n_0_654), .B1(op1[2]), .B2(n_0_693), .ZN(n_0_40)); + AOI211_X1_LVT i_0_40 (.A(n_0_668), .B(n_0_663), .C1(n_0_41), .C2(n_0_40), + .ZN(n_0_39)); + AOI211_X1_LVT i_0_39 (.A(n_0_656), .B(n_0_39), .C1(n_0_731), .C2(op1[5]), + .ZN(n_0_38)); + OAI222_X1_LVT i_0_38 (.A1(n_0_704), .A2(op2[6]), .B1(n_0_674), .B2(n_0_38), + .C1(n_0_713), .C2(op2[7]), .ZN(n_0_37)); + AOI221_X1_LVT i_0_37 (.A(n_0_655), .B1(op1[9]), .B2(n_0_720), .C1(n_0_677), + .C2(n_0_37), .ZN(n_0_36)); + INV_X1_LVT i_0_768 (.A(op2[10]), .ZN(n_0_735)); + OAI22_X1_LVT i_0_36 (.A1(n_0_735), .A2(op1[10]), .B1(op1[9]), .B2(n_0_720), + .ZN(n_0_35)); + OAI22_X1_LVT i_0_35 (.A1(op2[10]), .A2(n_0_733), .B1(n_0_36), .B2(n_0_35), + .ZN(n_0_34)); + INV_X1_LVT i_0_34 (.A(n_0_34), .ZN(n_0_33)); + AOI21_X1_LVT i_0_33 (.A(n_0_33), .B1(n_0_706), .B2(op2[11]), .ZN(n_0_32)); + OAI222_X1_LVT i_0_32 (.A1(op1[12]), .A2(n_0_695), .B1(n_0_715), .B2(op1[13]), + .C1(n_0_671), .C2(n_0_32), .ZN(n_0_31)); + OAI221_X1_LVT i_0_31 (.A(n_0_31), .B1(n_0_721), .B2(op2[14]), .C1(op2[13]), + .C2(n_0_714), .ZN(n_0_30)); + AOI22_X1_LVT i_0_30 (.A1(n_0_734), .A2(op2[15]), .B1(n_0_721), .B2(op2[14]), + .ZN(n_0_29)); + AOI21_X1_LVT i_0_28 (.A(n_0_28), .B1(n_0_30), .B2(n_0_29), .ZN(n_0_27)); + AOI221_X1_LVT i_0_27 (.A(n_0_27), .B1(n_0_732), .B2(op2[17]), .C1(n_0_739), + .C2(op2[16]), .ZN(n_0_26)); + AOI211_X1_LVT i_0_26 (.A(n_0_660), .B(n_0_26), .C1(n_0_707), .C2(op1[18]), + .ZN(n_0_25)); + OAI22_X1_LVT i_0_25 (.A1(op2[19]), .A2(n_0_689), .B1(n_0_678), .B2(n_0_25), + .ZN(n_0_24)); + AOI211_X1_LVT i_0_24 (.A(n_0_658), .B(n_0_659), .C1(n_0_657), .C2(n_0_24), + .ZN(n_0_23)); + AOI221_X1_LVT i_0_23 (.A(n_0_23), .B1(n_0_726), .B2(op2[21]), .C1(n_0_687), + .C2(op2[22]), .ZN(n_0_22)); + AOI221_X1_LVT i_0_22 (.A(n_0_22), .B1(op1[22]), .B2(n_0_686), .C1(op1[23]), + .C2(n_0_718), .ZN(n_0_21)); + AOI221_X1_LVT i_0_21 (.A(n_0_21), .B1(n_0_736), .B2(op2[24]), .C1(n_0_719), + .C2(op2[23]), .ZN(n_0_20)); + OAI222_X1_LVT i_0_20 (.A1(op1[26]), .A2(n_0_709), .B1(op1[25]), .B2(n_0_697), + .C1(n_0_679), .C2(n_0_20), .ZN(n_0_19)); + OAI221_X1_LVT i_0_19 (.A(n_0_19), .B1(n_0_711), .B2(op2[26]), .C1(n_0_688), + .C2(op2[27]), .ZN(n_0_18)); + AOI22_X1_LVT i_0_18 (.A1(n_0_700), .A2(op1[28]), .B1(n_0_661), .B2(n_0_18), + .ZN(n_0_17)); + OAI21_X1_LVT i_0_17 (.A(n_0_652), .B1(n_0_680), .B2(n_0_17), .ZN(n_0_16)); + INV_X1_LVT i_0_749 (.A(op2[30]), .ZN(n_0_716)); + OAI21_X1_LVT i_0_16 (.A(n_0_16), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_15)); + OAI22_X1_LVT i_0_708 (.A1(n_0_692), .A2(op1[31]), .B1(op2[31]), .B2(n_0_691), + .ZN(n_0_675)); + AOI21_X1_LVT i_0_15 (.A(n_0_675), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_14)); + AOI21_X1_LVT i_0_13 (.A(n_0_13), .B1(n_0_15), .B2(n_0_14), .ZN(n_0_12)); + NOR4_X1_LVT i_0_12 (.A1(n_0_685), .A2(aluOp[2]), .A3(aluBypass), .A4(n_0_12), + .ZN(n_0_11)); + OR3_X1_LVT i_0_0 (.A1(n_0_6), .A2(n_0_0), .A3(n_0_11), .ZN(result[0])); + OR4_X1_LVT i_0_703 (.A1(n_0_680), .A2(n_0_673), .A3(n_0_675), .A4(n_0_678), + .ZN(n_0_670)); + INV_X1_LVT i_0_709 (.A(n_0_677), .ZN(n_0_676)); + OR4_X1_LVT i_0_702 (.A1(n_0_679), .A2(n_0_674), .A3(n_0_676), .A4(n_0_671), + .ZN(n_0_669)); + AOI22_X1_LVT i_0_663 (.A1(n_0_688), .A2(op2[27]), .B1(op1[22]), .B2(n_0_686), + .ZN(n_0_630)); + OAI22_X1_LVT i_0_662 (.A1(n_0_694), .A2(op2[2]), .B1(op1[30]), .B2(n_0_716), + .ZN(n_0_629)); + AOI221_X1_LVT i_0_661 (.A(n_0_629), .B1(n_0_711), .B2(op2[26]), .C1(n_0_721), + .C2(op2[14]), .ZN(n_0_628)); + AOI21_X1_LVT i_0_664 (.A(n_0_660), .B1(n_0_690), .B2(op1[19]), .ZN(n_0_631)); + OAI222_X1_LVT i_0_660 (.A1(op1[12]), .A2(n_0_695), .B1(n_0_688), .B2(op2[27]), + .C1(op1[22]), .C2(n_0_686), .ZN(n_0_627)); + AOI21_X1_LVT i_0_659 (.A(n_0_663), .B1(n_0_734), .B2(op2[15]), .ZN(n_0_626)); + OAI211_X1_LVT i_0_658 (.A(n_0_666), .B(n_0_626), .C1(n_0_715), .C2(op1[13]), + .ZN(n_0_625)); + AOI211_X1_LVT i_0_657 (.A(n_0_627), .B(n_0_625), .C1(op1[23]), .C2(n_0_718), + .ZN(n_0_624)); + NAND4_X1_LVT i_0_656 (.A1(n_0_630), .A2(n_0_628), .A3(n_0_631), .A4(n_0_624), + .ZN(n_0_623)); + OAI22_X1_LVT i_0_684 (.A1(n_0_721), .A2(op2[14]), .B1(n_0_722), .B2(op2[9]), + .ZN(n_0_651)); + AOI211_X1_LVT i_0_668 (.A(n_0_651), .B(n_0_654), .C1(n_0_719), .C2(op2[23]), + .ZN(n_0_635)); + NAND2_X1_LVT i_0_667 (.A1(n_0_664), .A2(n_0_657), .ZN(n_0_634)); + NOR3_X1_LVT i_0_666 (.A1(n_0_659), .A2(n_0_656), .A3(n_0_634), .ZN(n_0_633)); + AOI21_X1_LVT i_0_671 (.A(n_0_655), .B1(n_0_739), .B2(op2[16]), .ZN(n_0_638)); + AOI21_X1_LVT i_0_670 (.A(n_0_668), .B1(n_0_736), .B2(op2[24]), .ZN(n_0_637)); + OAI22_X1_LVT i_0_673 (.A1(n_0_735), .A2(op1[10]), .B1(n_0_734), .B2(op2[15]), + .ZN(n_0_640)); + AOI221_X1_LVT i_0_672 (.A(n_0_640), .B1(n_0_732), .B2(op2[17]), .C1(n_0_731), + .C2(op1[5]), .ZN(n_0_639)); + AND3_X1_LVT i_0_669 (.A1(n_0_638), .A2(n_0_637), .A3(n_0_639), .ZN(n_0_636)); + OAI22_X1_LVT i_0_682 (.A1(n_0_703), .A2(op2[0]), .B1(n_0_704), .B2(op2[6]), + .ZN(n_0_649)); + OAI22_X1_LVT i_0_681 (.A1(op2[28]), .A2(n_0_698), .B1(op1[25]), .B2(n_0_697), + .ZN(n_0_648)); + AOI21_X1_LVT i_0_678 (.A(n_0_658), .B1(op1[30]), .B2(n_0_716), .ZN(n_0_645)); + AOI21_X1_LVT i_0_677 (.A(n_0_662), .B1(n_0_735), .B2(op1[10]), .ZN(n_0_644)); + INV_X1_LVT i_0_758 (.A(op2[21]), .ZN(n_0_725)); + OAI22_X1_LVT i_0_683 (.A1(op1[21]), .A2(n_0_725), .B1(n_0_739), .B2(op2[16]), + .ZN(n_0_650)); + AOI221_X1_LVT i_0_676 (.A(n_0_650), .B1(n_0_722), .B2(op2[9]), .C1(op1[7]), + .C2(n_0_712), .ZN(n_0_643)); + OAI21_X1_LVT i_0_680 (.A(n_0_652), .B1(n_0_711), .B2(op2[26]), .ZN(n_0_647)); + AOI221_X1_LVT i_0_679 (.A(n_0_647), .B1(n_0_706), .B2(op2[11]), .C1(n_0_707), + .C2(op1[18]), .ZN(n_0_646)); + NAND4_X1_LVT i_0_675 (.A1(n_0_645), .A2(n_0_644), .A3(n_0_643), .A4(n_0_646), + .ZN(n_0_642)); + NOR3_X1_LVT i_0_674 (.A1(n_0_649), .A2(n_0_648), .A3(n_0_642), .ZN(n_0_641)); + NAND4_X1_LVT i_0_665 (.A1(n_0_635), .A2(n_0_633), .A3(n_0_636), .A4(n_0_641), + .ZN(n_0_632)); + NOR4_X1_LVT i_0_655 (.A1(n_0_670), .A2(n_0_669), .A3(n_0_623), .A4(n_0_632), + .ZN(eqFlag)); +endmodule + +module decoder(CurrentPC, JumpOrBranchPC, JumpOrBranch, DAddr, WData, RData, + Instruction, WrMem, DWidth, Rs1, Rs2, Rd, RRs1, RRs2, WRd, WrReg, Illegal); + input [31:0]CurrentPC; + output [31:0]JumpOrBranchPC; + output JumpOrBranch; + output [31:0]DAddr; + output [31:0]WData; + input [31:0]RData; + input [31:0]Instruction; + output WrMem; + output [1:0]DWidth; + output [4:0]Rs1; + output [4:0]Rs2; + output [4:0]Rd; + input [31:0]RRs1; + input [31:0]RRs2; + output [31:0]WRd; + output WrReg; + output Illegal; + + wire eqFlag; + wire n_0_15; + wire n_0_2; + wire n_0_16; + wire n_0_3; + wire n_0_17; + wire n_0_4; + wire n_0_18; + wire n_0_5; + wire n_0_19; + wire n_0_6; + wire n_0_20; + wire n_0_7; + wire n_0_21; + wire n_0_8; + wire n_0_22; + wire n_0_9; + wire n_0_23; + wire n_0_10; + wire n_0_24; + wire n_0_11; + wire n_0_25; + wire n_0_12; + wire n_0_26; + wire n_0_13; + wire n_0_27; + wire n_0_14; + wire n_0_28; + wire n_0_29; + wire n_0_30; + wire n_0_31; + wire n_0_32; + wire n_0_33; + wire n_0_34; + wire n_0_35; + wire n_0_36; + wire n_0_37; + wire n_0_38; + wire n_0_39; + wire n_0_40; + wire n_0_41; + wire n_0_42; + wire n_0_43; + wire n_0_44; + wire n_0_45; + wire n_0_46; + wire n_0_47; + wire n_0_48; + wire n_0_49; + wire n_0_50; + wire n_0_51; + wire n_0_52; + wire n_0_53; + wire n_0_54; + wire n_0_55; + wire n_0_56; + wire n_0_57; + wire n_0_58; + wire n_0_59; + wire n_0_60; + wire n_0_61; + wire n_0_62; + wire n_0_63; + wire n_0_64; + wire n_0_65; + wire n_0_66; + wire n_0_67; + wire n_0_68; + wire n_0_69; + wire n_0_70; + wire n_0_71; + wire n_0_72; + wire n_0_73; + wire n_0_74; + wire n_0_75; + wire n_0_76; + wire n_0_77; + wire n_0_78; + wire n_0_79; + wire n_0_80; + wire n_0_81; + wire n_0_82; + wire n_0_83; + wire n_0_84; + wire n_0_85; + wire n_0_86; + wire n_0_87; + wire n_0_88; + wire n_0_89; + wire n_0_90; + wire n_0_91; + wire n_0_92; + wire n_0_93; + wire n_0_94; + wire n_0_95; + wire n_0_96; + wire n_0_97; + wire [2:0]aluOp; + wire n_0_98; + wire n_0_99; + wire n_0_100; + wire aluNegAr; + wire n_0_101; + wire n_0_102; + wire n_0_103; + wire n_0_104; + wire n_0_105; + wire aluBypass; + wire n_0_106; + wire [31:0]op1; + wire n_0_107; + wire n_0_108; + wire n_0_109; + wire n_0_110; + wire n_0_111; + wire n_0_112; + wire n_0_113; + wire n_0_114; + wire n_0_115; + wire n_0_116; + wire n_0_117; + wire n_0_118; + wire n_0_119; + wire n_0_120; + wire n_0_121; + wire n_0_122; + wire n_0_123; + wire n_0_124; + wire n_0_125; + wire n_0_126; + wire n_0_127; + wire n_0_128; + wire n_0_129; + wire n_0_130; + wire n_0_131; + wire n_0_132; + wire n_0_133; + wire n_0_134; + wire n_0_135; + wire n_0_136; + wire n_0_137; + wire n_0_138; + wire n_0_139; + wire n_0_140; + wire n_0_141; + wire n_0_142; + wire n_0_143; + wire n_0_144; + wire n_0_145; + wire n_0_146; + wire n_0_147; + wire n_0_148; + wire n_0_149; + wire n_0_150; + wire n_0_151; + wire n_0_152; + wire n_0_153; + wire n_0_154; + wire n_0_155; + wire n_0_156; + wire n_0_157; + wire n_0_158; + wire n_0_159; + wire n_0_160; + wire n_0_161; + wire n_0_162; + wire n_0_163; + wire n_0_164; + wire n_0_165; + wire n_0_166; + wire n_0_167; + wire n_0_168; + wire n_0_169; + wire [31:0]op2; + wire n_0_170; + wire n_0_171; + wire n_0_172; + wire n_0_173; + wire n_0_174; + wire n_0_175; + wire n_0_176; + wire n_0_177; + wire n_0_178; + wire n_0_179; + wire n_0_180; + wire n_0_181; + wire n_0_182; + wire n_0_183; + wire n_0_184; + wire n_0_185; + wire n_0_186; + wire n_0_187; + wire n_0_188; + wire n_0_189; + wire n_0_190; + wire n_0_191; + wire n_0_192; + wire n_0_193; + wire n_0_194; + wire n_0_195; + wire n_0_196; + wire n_0_197; + wire n_0_198; + wire n_0_199; + wire n_0_200; + wire n_0_201; + wire n_0_202; + wire n_0_203; + wire n_0_204; + wire n_0_205; + wire n_0_206; + wire n_0_207; + wire n_0_208; + wire n_0_209; + wire n_0_210; + wire n_0_211; + wire n_0_212; + wire n_0_213; + wire n_0_214; + wire n_0_215; + wire n_0_216; + wire n_0_217; + wire n_0_218; + wire n_0_219; + wire n_0_220; + wire n_0_221; + wire n_0_222; + wire n_0_223; + wire n_0_224; + wire n_0_225; + wire n_0_226; + wire n_0_227; + wire n_0_228; + wire n_0_229; + wire n_0_230; + wire n_0_231; + wire n_0_232; + wire n_0_233; + wire n_0_234; + wire n_0_235; + wire n_0_236; + wire n_0_237; + wire n_0_238; + wire n_0_239; + wire n_0_240; + wire n_0_241; + wire n_0_242; + wire n_0_1; + wire n_0_0; + wire n_0_243; + wire n_0_244; + wire n_0_245; + wire n_0_246; + wire n_0_247; + wire n_0_248; + wire n_0_249; + + datapathS__0_28 i_18 (.b_imm({uc_0, uc_1, uc_2, uc_3, uc_4, uc_5, uc_6, uc_7, + uc_8, uc_9, uc_10, uc_11, uc_12, uc_13, uc_14, uc_15, uc_16, uc_17, uc_18, + Instruction[31], Instruction[7], Instruction[30], Instruction[29], + Instruction[28], Instruction[27], Instruction[26], Instruction[25], + Instruction[11], Instruction[10], Instruction[9], Instruction[8], 1'b0}), + .CurrentPC({CurrentPC[31], CurrentPC[30], CurrentPC[29], CurrentPC[28], + CurrentPC[27], CurrentPC[26], CurrentPC[25], CurrentPC[24], CurrentPC[23], + CurrentPC[22], CurrentPC[21], CurrentPC[20], CurrentPC[19], CurrentPC[18], + CurrentPC[17], CurrentPC[16], CurrentPC[15], CurrentPC[14], CurrentPC[13], + CurrentPC[12], CurrentPC[11], CurrentPC[10], CurrentPC[9], CurrentPC[8], + CurrentPC[7], CurrentPC[6], CurrentPC[5], CurrentPC[4], CurrentPC[3], + CurrentPC[2], CurrentPC[1], uc_19}), .p_0({n_93, n_92, n_91, n_90, n_89, + n_88, n_87, n_86, n_85, n_84, n_83, n_82, n_81, n_80, n_79, n_78, n_77, + n_76, n_75, n_74, n_73, n_72, n_71, n_70, n_69, n_68, n_67, n_66, n_65, + n_64, n_63, uc_20})); + INV_X1_LVT i_0_350 (.A(Instruction[3]), .ZN(n_0_243)); + NAND3_X1_LVT i_0_343 (.A1(n_0_243), .A2(Instruction[0]), .A3(Instruction[1]), + .ZN(n_0_238)); + OR2_X1_LVT i_0_332 (.A1(n_0_238), .A2(Instruction[2]), .ZN(n_0_228)); + INV_X1_LVT i_0_351 (.A(Instruction[5]), .ZN(n_0_244)); + NOR2_X1_LVT i_0_340 (.A1(n_0_244), .A2(Instruction[4]), .ZN(n_0_235)); + NAND2_X1_LVT i_0_329 (.A1(Instruction[6]), .A2(n_0_235), .ZN(n_0_225)); + INV_X1_LVT i_0_354 (.A(Instruction[13]), .ZN(n_0_247)); + NOR2_X1_LVT i_0_345 (.A1(n_0_247), .A2(Instruction[14]), .ZN(n_0_240)); + NOR3_X1_LVT i_0_118 (.A1(n_0_228), .A2(n_0_225), .A3(n_0_240), .ZN(n_0_99)); + NAND3_X1_LVT i_0_346 (.A1(Instruction[0]), .A2(Instruction[1]), .A3( + Instruction[2]), .ZN(n_0_241)); + NOR2_X1_LVT i_0_328 (.A1(n_0_241), .A2(n_0_225), .ZN(n_0_224)); + INV_X1_LVT i_0_356 (.A(n_0_224), .ZN(n_0_249)); + NOR2_X1_LVT i_0_108 (.A1(n_0_243), .A2(n_0_249), .ZN(n_0_91)); + datapathS__0_26 i_17 (.j_imm({uc_21, uc_22, uc_23, uc_24, uc_25, uc_26, uc_27, + uc_28, uc_29, uc_30, uc_31, Instruction[31], Instruction[19], + Instruction[18], Instruction[17], Instruction[16], Instruction[15], + Instruction[14], Instruction[13], Instruction[12], Instruction[20], + Instruction[30], Instruction[29], Instruction[28], Instruction[27], + Instruction[26], Instruction[25], Instruction[24], Instruction[23], + Instruction[22], Instruction[21], 1'b0}), .CurrentPC({CurrentPC[31], + CurrentPC[30], CurrentPC[29], CurrentPC[28], CurrentPC[27], CurrentPC[26], + CurrentPC[25], CurrentPC[24], CurrentPC[23], CurrentPC[22], CurrentPC[21], + CurrentPC[20], CurrentPC[19], CurrentPC[18], CurrentPC[17], CurrentPC[16], + CurrentPC[15], CurrentPC[14], CurrentPC[13], CurrentPC[12], CurrentPC[11], + CurrentPC[10], CurrentPC[9], CurrentPC[8], CurrentPC[7], CurrentPC[6], + CurrentPC[5], CurrentPC[4], CurrentPC[3], CurrentPC[2], CurrentPC[1], + uc_32}), .p_0({n_62, n_61, n_60, n_59, n_58, n_57, n_56, n_55, n_54, n_53, + n_52, n_51, n_50, n_49, n_48, n_47, n_46, n_45, n_44, n_43, n_42, n_41, + n_40, n_39, n_38, n_37, n_36, n_35, n_34, n_33, n_32, uc_33})); + datapathS__0_14 i_5 (.i_imm({uc_34, uc_35, uc_36, uc_37, uc_38, uc_39, uc_40, + uc_41, uc_42, uc_43, uc_44, uc_45, uc_46, uc_47, uc_48, uc_49, uc_50, + uc_51, uc_52, uc_53, Instruction[31], Instruction[30], Instruction[29], + Instruction[28], Instruction[27], Instruction[26], Instruction[25], + Instruction[24], Instruction[23], Instruction[22], Instruction[21], + Instruction[20]}), .RRs1(RRs1), .p_0({n_31, n_30, n_29, n_28, n_27, n_26, + n_25, n_24, n_23, n_22, n_21, n_20, n_19, n_18, n_17, n_16, n_15, n_14, + n_13, n_12, n_11, n_10, n_9, n_8, n_7, n_6, n_5, n_4, n_3, n_2, n_1, n_0})); + NOR2_X1_LVT i_0_107 (.A1(n_0_249), .A2(Instruction[3]), .ZN(n_0_90)); + AOI222_X1_LVT i_0_106 (.A1(n_93), .A2(n_0_99), .B1(n_0_91), .B2(n_62), + .C1(n_31), .C2(n_0_90), .ZN(n_0_89)); + INV_X1_LVT i_0_355 (.A(Instruction[6]), .ZN(n_0_248)); + NAND2_X1_LVT i_0_339 (.A1(n_0_248), .A2(Instruction[4]), .ZN(n_0_234)); + INV_X1_LVT i_0_338 (.A(n_0_234), .ZN(n_0_233)); + OAI21_X1_LVT i_0_341 (.A(Instruction[13]), .B1(Instruction[14]), .B2( + Instruction[12]), .ZN(n_0_236)); + AOI211_X1_LVT i_0_337 (.A(n_0_235), .B(n_0_233), .C1(n_0_248), .C2(n_0_236), + .ZN(n_0_232)); + INV_X1_LVT i_0_352 (.A(Instruction[4]), .ZN(n_0_245)); + NAND2_X1_LVT i_0_344 (.A1(n_0_245), .A2(Instruction[2]), .ZN(n_0_239)); + AOI21_X1_LVT i_0_335 (.A(Instruction[6]), .B1(n_0_243), .B2(n_0_239), + .ZN(n_0_230)); + NOR2_X1_LVT i_0_334 (.A1(n_0_232), .A2(n_0_230), .ZN(n_0_229)); + NAND2_X1_LVT i_0_342 (.A1(n_0_241), .A2(n_0_238), .ZN(n_0_237)); + NAND2_X1_LVT i_0_336 (.A1(Instruction[6]), .A2(n_0_240), .ZN(n_0_231)); + OAI211_X1_LVT i_0_333 (.A(n_0_229), .B(n_0_237), .C1(Instruction[2]), + .C2(n_0_231), .ZN(Illegal)); + NAND2_X1_LVT i_0_109 (.A1(Illegal), .A2(CurrentPC[31]), .ZN(n_0_92)); + NAND2_X1_LVT i_0_105 (.A1(n_0_89), .A2(n_0_92), .ZN(JumpOrBranchPC[31])); + AOI222_X1_LVT i_0_103 (.A1(n_92), .A2(n_0_99), .B1(n_0_91), .B2(n_61), + .C1(n_30), .C2(n_0_90), .ZN(n_0_87)); + NAND2_X1_LVT i_0_104 (.A1(Illegal), .A2(CurrentPC[30]), .ZN(n_0_88)); + NAND2_X1_LVT i_0_102 (.A1(n_0_87), .A2(n_0_88), .ZN(JumpOrBranchPC[30])); + AOI222_X1_LVT i_0_100 (.A1(n_91), .A2(n_0_99), .B1(n_0_91), .B2(n_60), + .C1(n_29), .C2(n_0_90), .ZN(n_0_85)); + NAND2_X1_LVT i_0_101 (.A1(Illegal), .A2(CurrentPC[29]), .ZN(n_0_86)); + NAND2_X1_LVT i_0_99 (.A1(n_0_85), .A2(n_0_86), .ZN(JumpOrBranchPC[29])); + AOI222_X1_LVT i_0_97 (.A1(n_90), .A2(n_0_99), .B1(n_0_91), .B2(n_59), + .C1(n_28), .C2(n_0_90), .ZN(n_0_83)); + NAND2_X1_LVT i_0_98 (.A1(Illegal), .A2(CurrentPC[28]), .ZN(n_0_84)); + NAND2_X1_LVT i_0_96 (.A1(n_0_83), .A2(n_0_84), .ZN(JumpOrBranchPC[28])); + AOI222_X1_LVT i_0_94 (.A1(n_89), .A2(n_0_99), .B1(n_0_91), .B2(n_58), + .C1(n_27), .C2(n_0_90), .ZN(n_0_81)); + NAND2_X1_LVT i_0_95 (.A1(Illegal), .A2(CurrentPC[27]), .ZN(n_0_82)); + NAND2_X1_LVT i_0_93 (.A1(n_0_81), .A2(n_0_82), .ZN(JumpOrBranchPC[27])); + AOI222_X1_LVT i_0_91 (.A1(n_88), .A2(n_0_99), .B1(n_0_91), .B2(n_57), + .C1(n_26), .C2(n_0_90), .ZN(n_0_79)); + NAND2_X1_LVT i_0_92 (.A1(Illegal), .A2(CurrentPC[26]), .ZN(n_0_80)); + NAND2_X1_LVT i_0_90 (.A1(n_0_79), .A2(n_0_80), .ZN(JumpOrBranchPC[26])); + AOI222_X1_LVT i_0_88 (.A1(n_87), .A2(n_0_99), .B1(n_0_91), .B2(n_56), + .C1(n_25), .C2(n_0_90), .ZN(n_0_77)); + NAND2_X1_LVT i_0_89 (.A1(Illegal), .A2(CurrentPC[25]), .ZN(n_0_78)); + NAND2_X1_LVT i_0_87 (.A1(n_0_77), .A2(n_0_78), .ZN(JumpOrBranchPC[25])); + AOI222_X1_LVT i_0_85 (.A1(n_86), .A2(n_0_99), .B1(n_0_91), .B2(n_55), + .C1(n_24), .C2(n_0_90), .ZN(n_0_75)); + NAND2_X1_LVT i_0_86 (.A1(Illegal), .A2(CurrentPC[24]), .ZN(n_0_76)); + NAND2_X1_LVT i_0_84 (.A1(n_0_75), .A2(n_0_76), .ZN(JumpOrBranchPC[24])); + AOI222_X1_LVT i_0_82 (.A1(n_85), .A2(n_0_99), .B1(n_0_91), .B2(n_54), + .C1(n_23), .C2(n_0_90), .ZN(n_0_73)); + NAND2_X1_LVT i_0_83 (.A1(Illegal), .A2(CurrentPC[23]), .ZN(n_0_74)); + NAND2_X1_LVT i_0_81 (.A1(n_0_73), .A2(n_0_74), .ZN(JumpOrBranchPC[23])); + AOI222_X1_LVT i_0_79 (.A1(n_84), .A2(n_0_99), .B1(n_0_91), .B2(n_53), + .C1(n_22), .C2(n_0_90), .ZN(n_0_71)); + NAND2_X1_LVT i_0_80 (.A1(Illegal), .A2(CurrentPC[22]), .ZN(n_0_72)); + NAND2_X1_LVT i_0_78 (.A1(n_0_71), .A2(n_0_72), .ZN(JumpOrBranchPC[22])); + AOI222_X1_LVT i_0_76 (.A1(n_83), .A2(n_0_99), .B1(n_0_91), .B2(n_52), + .C1(n_21), .C2(n_0_90), .ZN(n_0_69)); + NAND2_X1_LVT i_0_77 (.A1(Illegal), .A2(CurrentPC[21]), .ZN(n_0_70)); + NAND2_X1_LVT i_0_75 (.A1(n_0_69), .A2(n_0_70), .ZN(JumpOrBranchPC[21])); + AOI222_X1_LVT i_0_73 (.A1(n_82), .A2(n_0_99), .B1(n_0_91), .B2(n_51), + .C1(n_20), .C2(n_0_90), .ZN(n_0_67)); + NAND2_X1_LVT i_0_74 (.A1(Illegal), .A2(CurrentPC[20]), .ZN(n_0_68)); + NAND2_X1_LVT i_0_72 (.A1(n_0_67), .A2(n_0_68), .ZN(JumpOrBranchPC[20])); + AOI222_X1_LVT i_0_70 (.A1(n_81), .A2(n_0_99), .B1(n_0_91), .B2(n_50), + .C1(n_19), .C2(n_0_90), .ZN(n_0_65)); + NAND2_X1_LVT i_0_71 (.A1(Illegal), .A2(CurrentPC[19]), .ZN(n_0_66)); + NAND2_X1_LVT i_0_69 (.A1(n_0_65), .A2(n_0_66), .ZN(JumpOrBranchPC[19])); + AOI222_X1_LVT i_0_67 (.A1(n_80), .A2(n_0_99), .B1(n_0_91), .B2(n_49), + .C1(n_18), .C2(n_0_90), .ZN(n_0_63)); + NAND2_X1_LVT i_0_68 (.A1(Illegal), .A2(CurrentPC[18]), .ZN(n_0_64)); + NAND2_X1_LVT i_0_66 (.A1(n_0_63), .A2(n_0_64), .ZN(JumpOrBranchPC[18])); + AOI222_X1_LVT i_0_64 (.A1(n_79), .A2(n_0_99), .B1(n_0_91), .B2(n_48), + .C1(n_17), .C2(n_0_90), .ZN(n_0_61)); + NAND2_X1_LVT i_0_65 (.A1(Illegal), .A2(CurrentPC[17]), .ZN(n_0_62)); + NAND2_X1_LVT i_0_63 (.A1(n_0_61), .A2(n_0_62), .ZN(JumpOrBranchPC[17])); + AOI222_X1_LVT i_0_61 (.A1(n_78), .A2(n_0_99), .B1(n_0_91), .B2(n_47), + .C1(n_16), .C2(n_0_90), .ZN(n_0_59)); + NAND2_X1_LVT i_0_62 (.A1(Illegal), .A2(CurrentPC[16]), .ZN(n_0_60)); + NAND2_X1_LVT i_0_60 (.A1(n_0_59), .A2(n_0_60), .ZN(JumpOrBranchPC[16])); + AOI222_X1_LVT i_0_58 (.A1(n_77), .A2(n_0_99), .B1(n_0_91), .B2(n_46), + .C1(n_15), .C2(n_0_90), .ZN(n_0_57)); + NAND2_X1_LVT i_0_59 (.A1(Illegal), .A2(CurrentPC[15]), .ZN(n_0_58)); + NAND2_X1_LVT i_0_57 (.A1(n_0_57), .A2(n_0_58), .ZN(JumpOrBranchPC[15])); + AOI222_X1_LVT i_0_55 (.A1(n_76), .A2(n_0_99), .B1(n_0_91), .B2(n_45), + .C1(n_14), .C2(n_0_90), .ZN(n_0_55)); + NAND2_X1_LVT i_0_56 (.A1(Illegal), .A2(CurrentPC[14]), .ZN(n_0_56)); + NAND2_X1_LVT i_0_54 (.A1(n_0_55), .A2(n_0_56), .ZN(JumpOrBranchPC[14])); + AOI222_X1_LVT i_0_52 (.A1(n_75), .A2(n_0_99), .B1(n_0_91), .B2(n_44), + .C1(n_13), .C2(n_0_90), .ZN(n_0_53)); + NAND2_X1_LVT i_0_53 (.A1(Illegal), .A2(CurrentPC[13]), .ZN(n_0_54)); + NAND2_X1_LVT i_0_51 (.A1(n_0_53), .A2(n_0_54), .ZN(JumpOrBranchPC[13])); + AOI222_X1_LVT i_0_49 (.A1(n_74), .A2(n_0_99), .B1(n_0_91), .B2(n_43), + .C1(n_12), .C2(n_0_90), .ZN(n_0_51)); + NAND2_X1_LVT i_0_50 (.A1(Illegal), .A2(CurrentPC[12]), .ZN(n_0_52)); + NAND2_X1_LVT i_0_48 (.A1(n_0_51), .A2(n_0_52), .ZN(JumpOrBranchPC[12])); + AOI222_X1_LVT i_0_46 (.A1(n_73), .A2(n_0_99), .B1(n_0_91), .B2(n_42), + .C1(n_11), .C2(n_0_90), .ZN(n_0_49)); + NAND2_X1_LVT i_0_47 (.A1(Illegal), .A2(CurrentPC[11]), .ZN(n_0_50)); + NAND2_X1_LVT i_0_45 (.A1(n_0_49), .A2(n_0_50), .ZN(JumpOrBranchPC[11])); + AOI222_X1_LVT i_0_43 (.A1(n_72), .A2(n_0_99), .B1(n_0_91), .B2(n_41), + .C1(n_10), .C2(n_0_90), .ZN(n_0_47)); + NAND2_X1_LVT i_0_44 (.A1(Illegal), .A2(CurrentPC[10]), .ZN(n_0_48)); + NAND2_X1_LVT i_0_42 (.A1(n_0_47), .A2(n_0_48), .ZN(JumpOrBranchPC[10])); + AOI222_X1_LVT i_0_40 (.A1(n_71), .A2(n_0_99), .B1(n_0_91), .B2(n_40), + .C1(n_9), .C2(n_0_90), .ZN(n_0_45)); + NAND2_X1_LVT i_0_41 (.A1(Illegal), .A2(CurrentPC[9]), .ZN(n_0_46)); + NAND2_X1_LVT i_0_39 (.A1(n_0_45), .A2(n_0_46), .ZN(JumpOrBranchPC[9])); + AOI222_X1_LVT i_0_37 (.A1(n_70), .A2(n_0_99), .B1(n_0_91), .B2(n_39), + .C1(n_8), .C2(n_0_90), .ZN(n_0_43)); + NAND2_X1_LVT i_0_38 (.A1(Illegal), .A2(CurrentPC[8]), .ZN(n_0_44)); + NAND2_X1_LVT i_0_36 (.A1(n_0_43), .A2(n_0_44), .ZN(JumpOrBranchPC[8])); + AOI222_X1_LVT i_0_34 (.A1(n_69), .A2(n_0_99), .B1(n_0_91), .B2(n_38), + .C1(n_7), .C2(n_0_90), .ZN(n_0_41)); + NAND2_X1_LVT i_0_35 (.A1(Illegal), .A2(CurrentPC[7]), .ZN(n_0_42)); + NAND2_X1_LVT i_0_33 (.A1(n_0_41), .A2(n_0_42), .ZN(JumpOrBranchPC[7])); + AOI222_X1_LVT i_0_31 (.A1(n_68), .A2(n_0_99), .B1(n_0_91), .B2(n_37), + .C1(n_6), .C2(n_0_90), .ZN(n_0_39)); + NAND2_X1_LVT i_0_32 (.A1(Illegal), .A2(CurrentPC[6]), .ZN(n_0_40)); + NAND2_X1_LVT i_0_30 (.A1(n_0_39), .A2(n_0_40), .ZN(JumpOrBranchPC[6])); + AOI222_X1_LVT i_0_28 (.A1(n_67), .A2(n_0_99), .B1(n_0_91), .B2(n_36), + .C1(n_5), .C2(n_0_90), .ZN(n_0_37)); + NAND2_X1_LVT i_0_29 (.A1(Illegal), .A2(CurrentPC[5]), .ZN(n_0_38)); + NAND2_X1_LVT i_0_27 (.A1(n_0_37), .A2(n_0_38), .ZN(JumpOrBranchPC[5])); + AOI222_X1_LVT i_0_25 (.A1(n_66), .A2(n_0_99), .B1(n_0_91), .B2(n_35), + .C1(n_4), .C2(n_0_90), .ZN(n_0_35)); + NAND2_X1_LVT i_0_26 (.A1(Illegal), .A2(CurrentPC[4]), .ZN(n_0_36)); + NAND2_X1_LVT i_0_24 (.A1(n_0_35), .A2(n_0_36), .ZN(JumpOrBranchPC[4])); + AOI222_X1_LVT i_0_22 (.A1(n_65), .A2(n_0_99), .B1(n_0_91), .B2(n_34), + .C1(n_3), .C2(n_0_90), .ZN(n_0_33)); + NAND2_X1_LVT i_0_23 (.A1(Illegal), .A2(CurrentPC[3]), .ZN(n_0_34)); + NAND2_X1_LVT i_0_21 (.A1(n_0_33), .A2(n_0_34), .ZN(JumpOrBranchPC[3])); + AOI222_X1_LVT i_0_19 (.A1(n_64), .A2(n_0_99), .B1(n_0_91), .B2(n_33), + .C1(n_2), .C2(n_0_90), .ZN(n_0_31)); + NAND2_X1_LVT i_0_20 (.A1(Illegal), .A2(CurrentPC[2]), .ZN(n_0_32)); + NAND2_X1_LVT i_0_18 (.A1(n_0_31), .A2(n_0_32), .ZN(JumpOrBranchPC[2])); + AOI222_X1_LVT i_0_16 (.A1(n_63), .A2(n_0_99), .B1(n_0_91), .B2(n_32), + .C1(n_1), .C2(n_0_90), .ZN(n_0_29)); + NAND2_X1_LVT i_0_17 (.A1(Illegal), .A2(CurrentPC[1]), .ZN(n_0_30)); + NAND2_X1_LVT i_0_15 (.A1(n_0_29), .A2(n_0_30), .ZN(JumpOrBranchPC[1])); + NOR2_X1_LVT i_0_112 (.A1(n_0_232), .A2(n_0_238), .ZN(n_0_94)); + OAI221_X1_LVT i_0_14 (.A(n_0_94), .B1(n_0_225), .B2(Instruction[2]), .C1( + Instruction[6]), .C2(n_0_239), .ZN(n_0_28)); + AND2_X1_LVT i_0_13 (.A1(n_0_28), .A2(CurrentPC[0]), .ZN(JumpOrBranchPC[0])); + NOR2_X1_LVT i_0_221 (.A1(Instruction[13]), .A2(Instruction[14]), .ZN(n_0_166)); + NOR3_X1_LVT i_0_293 (.A1(n_0_241), .A2(n_0_234), .A3(Instruction[3]), + .ZN(n_0_206)); + AND2_X1_LVT i_0_292 (.A1(n_0_206), .A2(n_0_244), .ZN(n_0_205)); + NOR3_X1_LVT i_0_330 (.A1(n_0_248), .A2(n_0_244), .A3(Instruction[4]), + .ZN(n_0_226)); + AOI21_X1_LVT i_0_121 (.A(n_0_205), .B1(n_0_226), .B2(n_0_237), .ZN(n_0_100)); + AND2_X1_LVT i_0_120 (.A1(Instruction[14]), .A2(n_0_100), .ZN(aluOp[2])); + OAI33_X1_LVT i_0_119 (.A1(n_0_205), .A2(n_0_247), .A3(n_0_224), .B1( + Instruction[2]), .B2(n_0_238), .B3(n_0_225), .ZN(aluOp[1])); + AOI22_X1_LVT i_0_117 (.A1(Instruction[12]), .A2(n_0_100), .B1(n_0_99), + .B2(Instruction[13]), .ZN(n_0_98)); + INV_X1_LVT i_0_116 (.A(n_0_98), .ZN(aluOp[0])); + OR2_X1_LVT i_0_327 (.A1(n_0_238), .A2(n_0_234), .ZN(n_0_223)); + NOR4_X1_LVT i_0_125 (.A1(Instruction[28]), .A2(Instruction[27]), .A3( + Instruction[26]), .A4(Instruction[25]), .ZN(n_0_103)); + INV_X1_LVT i_0_347 (.A(Instruction[30]), .ZN(n_0_242)); + NOR4_X1_LVT i_0_124 (.A1(Instruction[13]), .A2(n_0_242), .A3(Instruction[29]), + .A4(Instruction[31]), .ZN(n_0_102)); + NAND2_X1_LVT i_0_123 (.A1(n_0_103), .A2(n_0_102), .ZN(n_0_101)); + NOR3_X1_LVT i_0_127 (.A1(n_0_244), .A2(Instruction[12]), .A3(Instruction[14]), + .ZN(n_0_105)); + AOI21_X1_LVT i_0_126 (.A(n_0_105), .B1(Instruction[12]), .B2(Instruction[14]), + .ZN(n_0_104)); + NOR4_X1_LVT i_0_122 (.A1(n_0_223), .A2(n_0_101), .A3(n_0_104), .A4( + Instruction[2]), .ZN(aluNegAr)); + OR3_X1_LVT i_0_325 (.A1(n_0_228), .A2(Instruction[4]), .A3(Instruction[6]), + .ZN(n_0_222)); + NOR2_X1_LVT i_0_321 (.A1(n_0_222), .A2(Instruction[5]), .ZN(n_0_221)); + NOR3_X1_LVT i_0_224 (.A1(n_0_224), .A2(n_0_221), .A3(n_0_206), .ZN(n_0_169)); + NOR3_X1_LVT i_0_129 (.A1(n_0_234), .A2(Instruction[3]), .A3(Instruction[5]), + .ZN(n_0_106)); + NOR3_X1_LVT i_0_128 (.A1(n_0_226), .A2(n_0_169), .A3(n_0_106), .ZN(aluBypass)); + AOI22_X1_LVT i_0_223 (.A1(CurrentPC[31]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[31]), .ZN(n_0_168)); + NOR3_X1_LVT i_0_219 (.A1(n_0_247), .A2(n_0_222), .A3(Instruction[5]), + .ZN(n_0_164)); + AOI22_X1_LVT i_0_218 (.A1(RRs1[31]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[31]), .ZN(n_0_163)); + MUX2_X1_LVT i_0_222 (.A(RData[7]), .B(RData[15]), .S(Instruction[12]), + .Z(n_0_167)); + NAND3_X1_LVT i_0_220 (.A1(n_0_221), .A2(n_0_167), .A3(n_0_166), .ZN(n_0_165)); + NAND3_X1_LVT i_0_217 (.A1(n_0_168), .A2(n_0_163), .A3(n_0_165), .ZN(op1[31])); + AOI22_X1_LVT i_0_216 (.A1(RRs1[30]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[30]), .ZN(n_0_162)); + AOI22_X1_LVT i_0_215 (.A1(CurrentPC[30]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[30]), .ZN(n_0_161)); + NAND3_X1_LVT i_0_214 (.A1(n_0_162), .A2(n_0_161), .A3(n_0_165), .ZN(op1[30])); + AOI22_X1_LVT i_0_213 (.A1(RRs1[29]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[29]), .ZN(n_0_160)); + AOI22_X1_LVT i_0_212 (.A1(CurrentPC[29]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[29]), .ZN(n_0_159)); + NAND3_X1_LVT i_0_211 (.A1(n_0_160), .A2(n_0_159), .A3(n_0_165), .ZN(op1[29])); + AOI22_X1_LVT i_0_210 (.A1(RRs1[28]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[28]), .ZN(n_0_158)); + AOI22_X1_LVT i_0_209 (.A1(CurrentPC[28]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[28]), .ZN(n_0_157)); + NAND3_X1_LVT i_0_208 (.A1(n_0_158), .A2(n_0_157), .A3(n_0_165), .ZN(op1[28])); + AOI22_X1_LVT i_0_207 (.A1(RRs1[27]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[27]), .ZN(n_0_156)); + AOI22_X1_LVT i_0_206 (.A1(CurrentPC[27]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[27]), .ZN(n_0_155)); + NAND3_X1_LVT i_0_205 (.A1(n_0_156), .A2(n_0_155), .A3(n_0_165), .ZN(op1[27])); + AOI22_X1_LVT i_0_204 (.A1(RRs1[26]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[26]), .ZN(n_0_154)); + AOI22_X1_LVT i_0_203 (.A1(CurrentPC[26]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[26]), .ZN(n_0_153)); + NAND3_X1_LVT i_0_202 (.A1(n_0_154), .A2(n_0_153), .A3(n_0_165), .ZN(op1[26])); + AOI22_X1_LVT i_0_201 (.A1(RRs1[25]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[25]), .ZN(n_0_152)); + AOI22_X1_LVT i_0_200 (.A1(CurrentPC[25]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[25]), .ZN(n_0_151)); + NAND3_X1_LVT i_0_199 (.A1(n_0_152), .A2(n_0_151), .A3(n_0_165), .ZN(op1[25])); + AOI22_X1_LVT i_0_198 (.A1(RRs1[24]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[24]), .ZN(n_0_150)); + AOI22_X1_LVT i_0_197 (.A1(CurrentPC[24]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[24]), .ZN(n_0_149)); + NAND3_X1_LVT i_0_196 (.A1(n_0_150), .A2(n_0_149), .A3(n_0_165), .ZN(op1[24])); + AOI22_X1_LVT i_0_195 (.A1(RRs1[23]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[23]), .ZN(n_0_148)); + AOI22_X1_LVT i_0_194 (.A1(CurrentPC[23]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[23]), .ZN(n_0_147)); + NAND3_X1_LVT i_0_193 (.A1(n_0_148), .A2(n_0_147), .A3(n_0_165), .ZN(op1[23])); + AOI22_X1_LVT i_0_192 (.A1(RRs1[22]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[22]), .ZN(n_0_146)); + AOI22_X1_LVT i_0_191 (.A1(CurrentPC[22]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[22]), .ZN(n_0_145)); + NAND3_X1_LVT i_0_190 (.A1(n_0_146), .A2(n_0_145), .A3(n_0_165), .ZN(op1[22])); + AOI22_X1_LVT i_0_189 (.A1(RRs1[21]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[21]), .ZN(n_0_144)); + AOI22_X1_LVT i_0_188 (.A1(CurrentPC[21]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[21]), .ZN(n_0_143)); + NAND3_X1_LVT i_0_187 (.A1(n_0_144), .A2(n_0_143), .A3(n_0_165), .ZN(op1[21])); + AOI22_X1_LVT i_0_186 (.A1(RRs1[20]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[20]), .ZN(n_0_142)); + AOI22_X1_LVT i_0_185 (.A1(CurrentPC[20]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[20]), .ZN(n_0_141)); + NAND3_X1_LVT i_0_184 (.A1(n_0_142), .A2(n_0_141), .A3(n_0_165), .ZN(op1[20])); + AOI22_X1_LVT i_0_183 (.A1(RRs1[19]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[19]), .ZN(n_0_140)); + AOI22_X1_LVT i_0_182 (.A1(CurrentPC[19]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[19]), .ZN(n_0_139)); + NAND3_X1_LVT i_0_181 (.A1(n_0_140), .A2(n_0_139), .A3(n_0_165), .ZN(op1[19])); + AOI22_X1_LVT i_0_180 (.A1(RRs1[18]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[18]), .ZN(n_0_138)); + AOI22_X1_LVT i_0_179 (.A1(CurrentPC[18]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[18]), .ZN(n_0_137)); + NAND3_X1_LVT i_0_178 (.A1(n_0_138), .A2(n_0_137), .A3(n_0_165), .ZN(op1[18])); + AOI22_X1_LVT i_0_177 (.A1(RRs1[17]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[17]), .ZN(n_0_136)); + AOI22_X1_LVT i_0_176 (.A1(CurrentPC[17]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[17]), .ZN(n_0_135)); + NAND3_X1_LVT i_0_175 (.A1(n_0_136), .A2(n_0_135), .A3(n_0_165), .ZN(op1[17])); + AOI22_X1_LVT i_0_174 (.A1(RRs1[16]), .A2(n_0_169), .B1(n_0_164), .B2( + RData[16]), .ZN(n_0_134)); + AOI22_X1_LVT i_0_173 (.A1(CurrentPC[16]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[16]), .ZN(n_0_133)); + NAND3_X1_LVT i_0_172 (.A1(n_0_134), .A2(n_0_133), .A3(n_0_165), .ZN(op1[16])); + AOI222_X1_LVT i_0_169 (.A1(CurrentPC[15]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[15]), .C1(n_0_169), .C2(RRs1[15]), .ZN(n_0_130)); + INV_X1_LVT i_0_353 (.A(Instruction[12]), .ZN(n_0_246)); + AOI211_X1_LVT i_0_171 (.A(Instruction[5]), .B(n_0_222), .C1(n_0_247), + .C2(n_0_246), .ZN(n_0_132)); + OAI211_X1_LVT i_0_170 (.A(RData[15]), .B(n_0_132), .C1(Instruction[13]), + .C2(Instruction[14]), .ZN(n_0_131)); + NAND3_X1_LVT i_0_168 (.A1(n_0_130), .A2(n_0_131), .A3(n_0_165), .ZN(op1[15])); + AOI22_X1_LVT i_0_167 (.A1(RRs1[14]), .A2(n_0_169), .B1(n_0_132), .B2( + RData[14]), .ZN(n_0_129)); + AOI22_X1_LVT i_0_166 (.A1(CurrentPC[14]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[14]), .ZN(n_0_128)); + NAND4_X1_LVT i_0_165 (.A1(n_0_221), .A2(n_0_246), .A3(RData[7]), .A4(n_0_166), + .ZN(n_0_127)); + NAND3_X1_LVT i_0_164 (.A1(n_0_129), .A2(n_0_128), .A3(n_0_127), .ZN(op1[14])); + AOI22_X1_LVT i_0_163 (.A1(RRs1[13]), .A2(n_0_169), .B1(n_0_132), .B2( + RData[13]), .ZN(n_0_126)); + AOI22_X1_LVT i_0_162 (.A1(CurrentPC[13]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[13]), .ZN(n_0_125)); + NAND3_X1_LVT i_0_161 (.A1(n_0_126), .A2(n_0_125), .A3(n_0_127), .ZN(op1[13])); + AOI22_X1_LVT i_0_160 (.A1(RRs1[12]), .A2(n_0_169), .B1(n_0_132), .B2( + RData[12]), .ZN(n_0_124)); + AOI22_X1_LVT i_0_159 (.A1(CurrentPC[12]), .A2(n_0_224), .B1(n_0_206), + .B2(Instruction[12]), .ZN(n_0_123)); + NAND3_X1_LVT i_0_158 (.A1(n_0_124), .A2(n_0_123), .A3(n_0_127), .ZN(op1[12])); + AOI22_X1_LVT i_0_156 (.A1(CurrentPC[11]), .A2(n_0_224), .B1(n_0_132), + .B2(RData[11]), .ZN(n_0_121)); + NAND2_X1_LVT i_0_157 (.A1(RRs1[11]), .A2(n_0_169), .ZN(n_0_122)); + NAND3_X1_LVT i_0_155 (.A1(n_0_121), .A2(n_0_122), .A3(n_0_127), .ZN(op1[11])); + AOI22_X1_LVT i_0_153 (.A1(CurrentPC[10]), .A2(n_0_224), .B1(n_0_132), + .B2(RData[10]), .ZN(n_0_119)); + NAND2_X1_LVT i_0_154 (.A1(RRs1[10]), .A2(n_0_169), .ZN(n_0_120)); + NAND3_X1_LVT i_0_152 (.A1(n_0_119), .A2(n_0_120), .A3(n_0_127), .ZN(op1[10])); + AOI22_X1_LVT i_0_150 (.A1(CurrentPC[9]), .A2(n_0_224), .B1(n_0_132), .B2( + RData[9]), .ZN(n_0_117)); + NAND2_X1_LVT i_0_151 (.A1(RRs1[9]), .A2(n_0_169), .ZN(n_0_118)); + NAND3_X1_LVT i_0_149 (.A1(n_0_117), .A2(n_0_118), .A3(n_0_127), .ZN(op1[9])); + AOI22_X1_LVT i_0_147 (.A1(CurrentPC[8]), .A2(n_0_224), .B1(n_0_132), .B2( + RData[8]), .ZN(n_0_115)); + NAND2_X1_LVT i_0_148 (.A1(RRs1[8]), .A2(n_0_169), .ZN(n_0_116)); + NAND3_X1_LVT i_0_146 (.A1(n_0_115), .A2(n_0_116), .A3(n_0_127), .ZN(op1[8])); + AOI222_X1_LVT i_0_145 (.A1(CurrentPC[7]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[7]), .C1(n_0_169), .C2(RRs1[7]), .ZN(n_0_114)); + INV_X1_LVT i_0_144 (.A(n_0_114), .ZN(op1[7])); + AOI222_X1_LVT i_0_143 (.A1(CurrentPC[6]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[6]), .C1(n_0_169), .C2(RRs1[6]), .ZN(n_0_113)); + INV_X1_LVT i_0_142 (.A(n_0_113), .ZN(op1[6])); + AOI222_X1_LVT i_0_141 (.A1(CurrentPC[5]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[5]), .C1(n_0_169), .C2(RRs1[5]), .ZN(n_0_112)); + INV_X1_LVT i_0_140 (.A(n_0_112), .ZN(op1[5])); + AOI222_X1_LVT i_0_139 (.A1(CurrentPC[4]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[4]), .C1(n_0_169), .C2(RRs1[4]), .ZN(n_0_111)); + INV_X1_LVT i_0_138 (.A(n_0_111), .ZN(op1[4])); + AOI222_X1_LVT i_0_137 (.A1(CurrentPC[3]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[3]), .C1(n_0_169), .C2(RRs1[3]), .ZN(n_0_110)); + INV_X1_LVT i_0_136 (.A(n_0_110), .ZN(op1[3])); + AOI222_X1_LVT i_0_135 (.A1(CurrentPC[2]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[2]), .C1(n_0_169), .C2(RRs1[2]), .ZN(n_0_109)); + INV_X1_LVT i_0_134 (.A(n_0_109), .ZN(op1[2])); + AOI222_X1_LVT i_0_133 (.A1(CurrentPC[1]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[1]), .C1(n_0_169), .C2(RRs1[1]), .ZN(n_0_108)); + INV_X1_LVT i_0_132 (.A(n_0_108), .ZN(op1[1])); + AOI222_X1_LVT i_0_131 (.A1(CurrentPC[0]), .A2(n_0_224), .B1(n_0_221), + .B2(RData[0]), .C1(n_0_169), .C2(RRs1[0]), .ZN(n_0_107)); + INV_X1_LVT i_0_130 (.A(n_0_107), .ZN(op1[0])); + NOR3_X1_LVT i_0_294 (.A1(n_0_223), .A2(Instruction[2]), .A3(Instruction[5]), + .ZN(n_0_207)); + NOR3_X1_LVT i_0_291 (.A1(n_0_224), .A2(n_0_207), .A3(n_0_205), .ZN(n_0_204)); + AOI22_X1_LVT i_0_289 (.A1(CurrentPC[31]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[31]), .ZN(n_0_202)); + NAND2_X1_LVT i_0_290 (.A1(Instruction[31]), .A2(n_0_207), .ZN(n_0_203)); + NAND2_X1_LVT i_0_288 (.A1(n_0_202), .A2(n_0_203), .ZN(op2[31])); + AOI22_X1_LVT i_0_287 (.A1(CurrentPC[30]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[30]), .ZN(n_0_201)); + NAND2_X1_LVT i_0_286 (.A1(n_0_201), .A2(n_0_203), .ZN(op2[30])); + AOI22_X1_LVT i_0_285 (.A1(CurrentPC[29]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[29]), .ZN(n_0_200)); + NAND2_X1_LVT i_0_284 (.A1(n_0_200), .A2(n_0_203), .ZN(op2[29])); + AOI22_X1_LVT i_0_283 (.A1(CurrentPC[28]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[28]), .ZN(n_0_199)); + NAND2_X1_LVT i_0_282 (.A1(n_0_199), .A2(n_0_203), .ZN(op2[28])); + AOI22_X1_LVT i_0_281 (.A1(CurrentPC[27]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[27]), .ZN(n_0_198)); + NAND2_X1_LVT i_0_280 (.A1(n_0_198), .A2(n_0_203), .ZN(op2[27])); + AOI22_X1_LVT i_0_279 (.A1(CurrentPC[26]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[26]), .ZN(n_0_197)); + NAND2_X1_LVT i_0_278 (.A1(n_0_197), .A2(n_0_203), .ZN(op2[26])); + AOI22_X1_LVT i_0_277 (.A1(CurrentPC[25]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[25]), .ZN(n_0_196)); + NAND2_X1_LVT i_0_276 (.A1(n_0_196), .A2(n_0_203), .ZN(op2[25])); + AOI22_X1_LVT i_0_275 (.A1(CurrentPC[24]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[24]), .ZN(n_0_195)); + NAND2_X1_LVT i_0_274 (.A1(n_0_195), .A2(n_0_203), .ZN(op2[24])); + AOI22_X1_LVT i_0_273 (.A1(CurrentPC[23]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[23]), .ZN(n_0_194)); + NAND2_X1_LVT i_0_272 (.A1(n_0_194), .A2(n_0_203), .ZN(op2[23])); + AOI22_X1_LVT i_0_271 (.A1(CurrentPC[22]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[22]), .ZN(n_0_193)); + NAND2_X1_LVT i_0_270 (.A1(n_0_193), .A2(n_0_203), .ZN(op2[22])); + AOI22_X1_LVT i_0_269 (.A1(CurrentPC[21]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[21]), .ZN(n_0_192)); + NAND2_X1_LVT i_0_268 (.A1(n_0_192), .A2(n_0_203), .ZN(op2[21])); + AOI22_X1_LVT i_0_267 (.A1(CurrentPC[20]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[20]), .ZN(n_0_191)); + NAND2_X1_LVT i_0_266 (.A1(n_0_191), .A2(n_0_203), .ZN(op2[20])); + AOI22_X1_LVT i_0_265 (.A1(CurrentPC[19]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[19]), .ZN(n_0_190)); + NAND2_X1_LVT i_0_264 (.A1(n_0_190), .A2(n_0_203), .ZN(op2[19])); + AOI22_X1_LVT i_0_263 (.A1(CurrentPC[18]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[18]), .ZN(n_0_189)); + NAND2_X1_LVT i_0_262 (.A1(n_0_189), .A2(n_0_203), .ZN(op2[18])); + AOI22_X1_LVT i_0_261 (.A1(CurrentPC[17]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[17]), .ZN(n_0_188)); + NAND2_X1_LVT i_0_260 (.A1(n_0_188), .A2(n_0_203), .ZN(op2[17])); + AOI22_X1_LVT i_0_259 (.A1(CurrentPC[16]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[16]), .ZN(n_0_187)); + NAND2_X1_LVT i_0_258 (.A1(n_0_187), .A2(n_0_203), .ZN(op2[16])); + AOI22_X1_LVT i_0_257 (.A1(CurrentPC[15]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[15]), .ZN(n_0_186)); + NAND2_X1_LVT i_0_256 (.A1(n_0_186), .A2(n_0_203), .ZN(op2[15])); + AOI22_X1_LVT i_0_255 (.A1(CurrentPC[14]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[14]), .ZN(n_0_185)); + NAND2_X1_LVT i_0_254 (.A1(n_0_185), .A2(n_0_203), .ZN(op2[14])); + AOI22_X1_LVT i_0_253 (.A1(CurrentPC[13]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[13]), .ZN(n_0_184)); + NAND2_X1_LVT i_0_252 (.A1(n_0_184), .A2(n_0_203), .ZN(op2[13])); + AOI22_X1_LVT i_0_251 (.A1(CurrentPC[12]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[12]), .ZN(n_0_183)); + NAND2_X1_LVT i_0_250 (.A1(n_0_183), .A2(n_0_203), .ZN(op2[12])); + AOI22_X1_LVT i_0_249 (.A1(CurrentPC[11]), .A2(n_0_205), .B1(n_0_204), + .B2(RRs2[11]), .ZN(n_0_182)); + NAND2_X1_LVT i_0_248 (.A1(n_0_182), .A2(n_0_203), .ZN(op2[11])); + AOI222_X1_LVT i_0_247 (.A1(Instruction[30]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[10]), .C1(n_0_204), .C2(RRs2[10]), .ZN(n_0_181)); + INV_X1_LVT i_0_246 (.A(n_0_181), .ZN(op2[10])); + AOI222_X1_LVT i_0_245 (.A1(Instruction[29]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[9]), .C1(n_0_204), .C2(RRs2[9]), .ZN(n_0_180)); + INV_X1_LVT i_0_244 (.A(n_0_180), .ZN(op2[9])); + AOI222_X1_LVT i_0_243 (.A1(Instruction[28]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[8]), .C1(n_0_204), .C2(RRs2[8]), .ZN(n_0_179)); + INV_X1_LVT i_0_242 (.A(n_0_179), .ZN(op2[8])); + AOI222_X1_LVT i_0_241 (.A1(Instruction[27]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[7]), .C1(n_0_204), .C2(RRs2[7]), .ZN(n_0_178)); + INV_X1_LVT i_0_240 (.A(n_0_178), .ZN(op2[7])); + AOI222_X1_LVT i_0_239 (.A1(Instruction[26]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[6]), .C1(n_0_204), .C2(RRs2[6]), .ZN(n_0_177)); + INV_X1_LVT i_0_238 (.A(n_0_177), .ZN(op2[6])); + AOI222_X1_LVT i_0_237 (.A1(Instruction[25]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[5]), .C1(n_0_204), .C2(RRs2[5]), .ZN(n_0_176)); + INV_X1_LVT i_0_236 (.A(n_0_176), .ZN(op2[5])); + AOI222_X1_LVT i_0_235 (.A1(Instruction[24]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[4]), .C1(n_0_204), .C2(RRs2[4]), .ZN(n_0_175)); + INV_X1_LVT i_0_234 (.A(n_0_175), .ZN(op2[4])); + AOI222_X1_LVT i_0_233 (.A1(Instruction[23]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[3]), .C1(n_0_204), .C2(RRs2[3]), .ZN(n_0_174)); + INV_X1_LVT i_0_232 (.A(n_0_174), .ZN(op2[3])); + AOI22_X1_LVT i_0_230 (.A1(Instruction[22]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[2]), .ZN(n_0_172)); + OAI21_X1_LVT i_0_231 (.A(RRs2[2]), .B1(n_0_223), .B2(Instruction[5]), + .ZN(n_0_173)); + NAND3_X1_LVT i_0_229 (.A1(n_0_172), .A2(n_0_173), .A3(n_0_249), .ZN(op2[2])); + AOI222_X1_LVT i_0_228 (.A1(Instruction[21]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[1]), .C1(n_0_204), .C2(RRs2[1]), .ZN(n_0_171)); + INV_X1_LVT i_0_227 (.A(n_0_171), .ZN(op2[1])); + AOI222_X1_LVT i_0_226 (.A1(Instruction[20]), .A2(n_0_207), .B1(n_0_205), + .B2(CurrentPC[0]), .C1(n_0_204), .C2(RRs2[0]), .ZN(n_0_170)); + INV_X1_LVT i_0_225 (.A(n_0_170), .ZN(op2[0])); + alu theALU (.aluOp(aluOp), .aluNegAr(aluNegAr), .aluBypass(aluBypass), + .op1(op1), .op2(op2), .result(WRd), .eqFlag(eqFlag)); + XNOR2_X1_LVT i_0_115 (.A(Instruction[12]), .B(eqFlag), .ZN(n_0_97)); + XNOR2_X1_LVT i_0_114 (.A(Instruction[12]), .B(WRd[0]), .ZN(n_0_96)); + AOI22_X1_LVT i_0_113 (.A1(n_0_166), .A2(n_0_97), .B1(n_0_96), .B2( + Instruction[14]), .ZN(n_0_95)); + AOI22_X1_LVT i_0_111 (.A1(Instruction[6]), .A2(n_0_95), .B1(Instruction[2]), + .B2(n_0_245), .ZN(n_0_93)); + NAND2_X1_LVT i_0_110 (.A1(n_0_94), .A2(n_0_93), .ZN(JumpOrBranch)); + INV_X1_LVT i_0_349 (.A(Instruction[31]), .ZN(n_0_0)); + INV_X1_LVT i_0_348 (.A(RRs1[12]), .ZN(n_0_1)); + HA_X1_LVT i_0_0 (.A(Instruction[7]), .B(RRs1[0]), .CO(n_0_2), .S(n_0_15)); + FA_X1_LVT i_0_1 (.A(Instruction[8]), .B(RRs1[1]), .CI(n_0_2), .CO(n_0_3), + .S(n_0_16)); + FA_X1_LVT i_0_2 (.A(Instruction[9]), .B(RRs1[2]), .CI(n_0_3), .CO(n_0_4), + .S(n_0_17)); + FA_X1_LVT i_0_3 (.A(Instruction[10]), .B(RRs1[3]), .CI(n_0_4), .CO(n_0_5), + .S(n_0_18)); + FA_X1_LVT i_0_4 (.A(Instruction[11]), .B(RRs1[4]), .CI(n_0_5), .CO(n_0_6), + .S(n_0_19)); + FA_X1_LVT i_0_5 (.A(Instruction[25]), .B(RRs1[5]), .CI(n_0_6), .CO(n_0_7), + .S(n_0_20)); + FA_X1_LVT i_0_6 (.A(Instruction[26]), .B(RRs1[6]), .CI(n_0_7), .CO(n_0_8), + .S(n_0_21)); + FA_X1_LVT i_0_7 (.A(Instruction[27]), .B(RRs1[7]), .CI(n_0_8), .CO(n_0_9), + .S(n_0_22)); + FA_X1_LVT i_0_8 (.A(Instruction[28]), .B(RRs1[8]), .CI(n_0_9), .CO(n_0_10), + .S(n_0_23)); + FA_X1_LVT i_0_9 (.A(Instruction[29]), .B(RRs1[9]), .CI(n_0_10), .CO(n_0_11), + .S(n_0_24)); + FA_X1_LVT i_0_10 (.A(Instruction[30]), .B(RRs1[10]), .CI(n_0_11), .CO(n_0_12), + .S(n_0_25)); + FA_X1_LVT i_0_11 (.A(RRs1[11]), .B(Instruction[31]), .CI(n_0_12), .CO(n_0_13), + .S(n_0_26)); + FA_X1_LVT i_0_12 (.A(n_0_0), .B(n_0_1), .CI(n_0_13), .CO(n_0_14), .S(n_0_27)); + NOR2_X1_LVT i_0_322 (.A1(n_0_244), .A2(n_0_222), .ZN(WrMem)); + AOI22_X1_LVT i_0_320 (.A1(n_0_27), .A2(WrMem), .B1(n_0_221), .B2(n_12), + .ZN(n_0_220)); + INV_X1_LVT i_0_319 (.A(n_0_220), .ZN(DAddr[12])); + AOI22_X1_LVT i_0_318 (.A1(n_0_26), .A2(WrMem), .B1(n_0_221), .B2(n_11), + .ZN(n_0_219)); + INV_X1_LVT i_0_317 (.A(n_0_219), .ZN(DAddr[11])); + AOI22_X1_LVT i_0_316 (.A1(n_0_25), .A2(WrMem), .B1(n_0_221), .B2(n_10), + .ZN(n_0_218)); + INV_X1_LVT i_0_315 (.A(n_0_218), .ZN(DAddr[10])); + AOI22_X1_LVT i_0_314 (.A1(n_0_24), .A2(WrMem), .B1(n_0_221), .B2(n_9), + .ZN(n_0_217)); + INV_X1_LVT i_0_313 (.A(n_0_217), .ZN(DAddr[9])); + AOI22_X1_LVT i_0_312 (.A1(n_0_23), .A2(WrMem), .B1(n_0_221), .B2(n_8), + .ZN(n_0_216)); + INV_X1_LVT i_0_311 (.A(n_0_216), .ZN(DAddr[8])); + AOI22_X1_LVT i_0_310 (.A1(n_0_22), .A2(WrMem), .B1(n_0_221), .B2(n_7), + .ZN(n_0_215)); + INV_X1_LVT i_0_309 (.A(n_0_215), .ZN(DAddr[7])); + AOI22_X1_LVT i_0_308 (.A1(n_0_21), .A2(WrMem), .B1(n_0_221), .B2(n_6), + .ZN(n_0_214)); + INV_X1_LVT i_0_307 (.A(n_0_214), .ZN(DAddr[6])); + AOI22_X1_LVT i_0_306 (.A1(n_0_20), .A2(WrMem), .B1(n_0_221), .B2(n_5), + .ZN(n_0_213)); + INV_X1_LVT i_0_305 (.A(n_0_213), .ZN(DAddr[5])); + AOI22_X1_LVT i_0_304 (.A1(n_0_19), .A2(WrMem), .B1(n_0_221), .B2(n_4), + .ZN(n_0_212)); + INV_X1_LVT i_0_303 (.A(n_0_212), .ZN(DAddr[4])); + AOI22_X1_LVT i_0_302 (.A1(n_0_18), .A2(WrMem), .B1(n_0_221), .B2(n_3), + .ZN(n_0_211)); + INV_X1_LVT i_0_301 (.A(n_0_211), .ZN(DAddr[3])); + AOI22_X1_LVT i_0_300 (.A1(n_0_17), .A2(WrMem), .B1(n_0_221), .B2(n_2), + .ZN(n_0_210)); + INV_X1_LVT i_0_299 (.A(n_0_210), .ZN(DAddr[2])); + AOI22_X1_LVT i_0_298 (.A1(n_0_16), .A2(WrMem), .B1(n_0_221), .B2(n_1), + .ZN(n_0_209)); + INV_X1_LVT i_0_297 (.A(n_0_209), .ZN(DAddr[1])); + AOI22_X1_LVT i_0_296 (.A1(n_0_15), .A2(WrMem), .B1(n_0_221), .B2(n_0), + .ZN(n_0_208)); + INV_X1_LVT i_0_295 (.A(n_0_208), .ZN(DAddr[0])); + OR2_X1_LVT i_0_324 (.A1(n_0_222), .A2(Instruction[13]), .ZN(DWidth[1])); + NOR2_X1_LVT i_0_323 (.A1(n_0_246), .A2(n_0_222), .ZN(DWidth[0])); + NAND3_X1_LVT i_0_331 (.A1(n_0_248), .A2(n_0_244), .A3(n_0_236), .ZN(n_0_227)); + OAI211_X1_LVT i_0_326 (.A(n_0_249), .B(n_0_223), .C1(n_0_228), .C2(n_0_227), + .ZN(WrReg)); +endmodule + +module cpu(led, btn, clk_25mhz, scan_en, SI_1, SO_1, SI_2, SO_2, SI_3, SO_3, + SI_4, SO_4); + output [7:0]led; + input [6:0]btn; + input clk_25mhz; + input scan_en; + input SI_1; + output SO_1; + input SI_2; + output SO_2; + input SI_3; + output SO_3; + input SI_4; + output SO_4; + + wire [31:0]Instruction; + wire [31:0]RData; + wire [31:0]RRs2; + wire [31:0]RRs1; + wire WrReg; + wire [31:0]WRd; + wire [1:0]DWidth; + wire [31:0]DAddr; + wire JumpOrBranch; + wire [31:0]JumpOrBranchPC; + wire thePC_n_0; + wire thePC_n_1; + wire thePC_n_2; + wire thePC_n_3; + wire thePC_n_4; + wire thePC_n_5; + wire thePC_n_6; + wire thePC_n_7; + wire thePC_n_8; + wire thePC_n_9; + wire thePC_n_10; + wire thePC_n_11; + wire thePC_n_12; + wire thePC_n_13; + wire thePC_n_14; + wire thePC_n_15; + wire thePC_n_16; + wire thePC_n_17; + wire thePC_n_18; + wire thePC_n_19; + wire thePC_n_20; + wire thePC_n_21; + wire thePC_n_22; + wire thePC_n_23; + wire thePC_n_24; + wire thePC_n_25; + wire thePC_n_26; + wire thePC_n_27; + wire thePC_n_28; + wire thePC_n_29; + wire [31:0]CurrentPC; + wire thePC_n_30; + wire n_0_0_0; + wire thePC_n_31; + wire n_0_0_1; + wire thePC_n_32; + wire thePC_n_33; + wire thePC_n_34; + wire thePC_n_35; + wire thePC_n_36; + wire thePC_n_37; + wire thePC_n_38; + wire thePC_n_39; + wire thePC_n_40; + wire thePC_n_41; + wire thePC_n_42; + wire thePC_n_43; + wire n_0_0_2; + wire thePC_n_44; + wire n_0_0_3; + wire thePC_n_45; + wire n_0_0_4; + wire thePC_n_46; + wire n_0_0_5; + wire thePC_n_47; + wire n_0_0_6; + wire thePC_n_48; + wire n_0_0_7; + wire thePC_n_49; + wire n_0_0_8; + wire thePC_n_50; + wire n_0_0_9; + wire thePC_n_51; + wire n_0_0_10; + wire thePC_n_52; + wire n_0_0_11; + wire thePC_n_53; + wire n_0_0_12; + wire thePC_n_54; + wire n_0_0_13; + wire thePC_n_55; + wire n_0_0_14; + wire thePC_n_56; + wire n_0_0_15; + wire thePC_n_57; + wire n_0_0_16; + wire thePC_n_58; + wire n_0_0_17; + wire thePC_n_59; + wire n_0_0_18; + wire thePC_n_60; + wire n_0_0_19; + wire thePC_n_61; + wire n_0_0_20; + wire n_0_0_21; + wire n_0_0_22; + wire [31:0]NextPC; + wire reset; + + AND2_X1_LVT i_0_0_54 (.A1(JumpOrBranch), .A2(btn[0]), .ZN(n_0_0_22)); + INV_X1_LVT i_0_0_66 (.A(btn[0]), .ZN(reset)); + NOR2_X1_LVT i_0_0_53 (.A1(reset), .A2(JumpOrBranch), .ZN(n_0_0_21)); + AOI22_X1_LVT i_0_0_50 (.A1(JumpOrBranchPC[30]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_28), .ZN(n_0_0_19)); + INV_X1_LVT i_0_0_49 (.A(n_0_0_19), .ZN(thePC_n_60)); + CLKBUF_X3_LVT tessent_persistent_cell_buf_extsi1225_i (.A(SI_1), .Z(n_0)); + SDFF_X1_LVT \thePC_CurrentPC_reg[30] (.D(thePC_n_60), .SE(scan_en), .SI(n_0), + .CK(clk_25mhz), .Q(CurrentPC[30]), .QN()); + AOI22_X1_LVT i_0_0_48 (.A1(JumpOrBranchPC[29]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_27), .ZN(n_0_0_18)); + INV_X1_LVT i_0_0_47 (.A(n_0_0_18), .ZN(thePC_n_59)); + SDFF_X1_LVT \thePC_CurrentPC_reg[29] (.D(thePC_n_59), .SE(scan_en), .SI( + CurrentPC[30]), .CK(clk_25mhz), .Q(CurrentPC[29]), .QN()); + AOI22_X1_LVT i_0_0_46 (.A1(JumpOrBranchPC[28]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_26), .ZN(n_0_0_17)); + INV_X1_LVT i_0_0_45 (.A(n_0_0_17), .ZN(thePC_n_58)); + SDFF_X1_LVT \thePC_CurrentPC_reg[28] (.D(thePC_n_58), .SE(scan_en), .SI( + CurrentPC[29]), .CK(clk_25mhz), .Q(CurrentPC[28]), .QN()); + AOI22_X1_LVT i_0_0_44 (.A1(JumpOrBranchPC[27]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_25), .ZN(n_0_0_16)); + INV_X1_LVT i_0_0_43 (.A(n_0_0_16), .ZN(thePC_n_57)); + SDFF_X1_LVT \thePC_CurrentPC_reg[27] (.D(thePC_n_57), .SE(scan_en), .SI( + CurrentPC[28]), .CK(clk_25mhz), .Q(CurrentPC[27]), .QN()); + AOI22_X1_LVT i_0_0_42 (.A1(JumpOrBranchPC[26]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_24), .ZN(n_0_0_15)); + INV_X1_LVT i_0_0_41 (.A(n_0_0_15), .ZN(thePC_n_56)); + SDFF_X1_LVT \thePC_CurrentPC_reg[26] (.D(thePC_n_56), .SE(scan_en), .SI( + CurrentPC[27]), .CK(clk_25mhz), .Q(CurrentPC[26]), .QN()); + AOI22_X1_LVT i_0_0_40 (.A1(JumpOrBranchPC[25]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_23), .ZN(n_0_0_14)); + INV_X1_LVT i_0_0_39 (.A(n_0_0_14), .ZN(thePC_n_55)); + SDFF_X1_LVT \thePC_CurrentPC_reg[25] (.D(thePC_n_55), .SE(scan_en), .SI( + CurrentPC[26]), .CK(clk_25mhz), .Q(CurrentPC[25]), .QN()); + AOI22_X1_LVT i_0_0_38 (.A1(JumpOrBranchPC[24]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_22), .ZN(n_0_0_13)); + INV_X1_LVT i_0_0_37 (.A(n_0_0_13), .ZN(thePC_n_54)); + SDFF_X1_LVT \thePC_CurrentPC_reg[24] (.D(thePC_n_54), .SE(scan_en), .SI( + CurrentPC[25]), .CK(clk_25mhz), .Q(CurrentPC[24]), .QN()); + AOI22_X1_LVT i_0_0_36 (.A1(JumpOrBranchPC[23]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_21), .ZN(n_0_0_12)); + INV_X1_LVT i_0_0_35 (.A(n_0_0_12), .ZN(thePC_n_53)); + SDFF_X1_LVT \thePC_CurrentPC_reg[23] (.D(thePC_n_53), .SE(scan_en), .SI( + CurrentPC[24]), .CK(clk_25mhz), .Q(CurrentPC[23]), .QN()); + AOI22_X1_LVT i_0_0_34 (.A1(JumpOrBranchPC[22]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_20), .ZN(n_0_0_11)); + INV_X1_LVT i_0_0_33 (.A(n_0_0_11), .ZN(thePC_n_52)); + SDFF_X1_LVT \thePC_CurrentPC_reg[22] (.D(thePC_n_52), .SE(scan_en), .SI( + CurrentPC[23]), .CK(clk_25mhz), .Q(CurrentPC[22]), .QN()); + AOI22_X1_LVT i_0_0_32 (.A1(JumpOrBranchPC[21]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_19), .ZN(n_0_0_10)); + INV_X1_LVT i_0_0_31 (.A(n_0_0_10), .ZN(thePC_n_51)); + SDFF_X1_LVT \thePC_CurrentPC_reg[21] (.D(thePC_n_51), .SE(scan_en), .SI( + CurrentPC[22]), .CK(clk_25mhz), .Q(CurrentPC[21]), .QN()); + AOI22_X1_LVT i_0_0_30 (.A1(JumpOrBranchPC[20]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_18), .ZN(n_0_0_9)); + INV_X1_LVT i_0_0_29 (.A(n_0_0_9), .ZN(thePC_n_50)); + SDFF_X1_LVT \thePC_CurrentPC_reg[20] (.D(thePC_n_50), .SE(scan_en), .SI( + CurrentPC[21]), .CK(clk_25mhz), .Q(CurrentPC[20]), .QN()); + AOI22_X1_LVT i_0_0_28 (.A1(JumpOrBranchPC[19]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_17), .ZN(n_0_0_8)); + INV_X1_LVT i_0_0_27 (.A(n_0_0_8), .ZN(thePC_n_49)); + SDFF_X1_LVT \thePC_CurrentPC_reg[19] (.D(thePC_n_49), .SE(scan_en), .SI( + CurrentPC[20]), .CK(clk_25mhz), .Q(CurrentPC[19]), .QN()); + AOI22_X1_LVT i_0_0_26 (.A1(JumpOrBranchPC[18]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_16), .ZN(n_0_0_7)); + INV_X1_LVT i_0_0_25 (.A(n_0_0_7), .ZN(thePC_n_48)); + SDFF_X1_LVT \thePC_CurrentPC_reg[18] (.D(thePC_n_48), .SE(scan_en), .SI( + CurrentPC[19]), .CK(clk_25mhz), .Q(CurrentPC[18]), .QN()); + AOI22_X1_LVT i_0_0_24 (.A1(JumpOrBranchPC[17]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_15), .ZN(n_0_0_6)); + INV_X1_LVT i_0_0_23 (.A(n_0_0_6), .ZN(thePC_n_47)); + SDFF_X1_LVT \thePC_CurrentPC_reg[17] (.D(thePC_n_47), .SE(scan_en), .SI( + CurrentPC[18]), .CK(clk_25mhz), .Q(CurrentPC[17]), .QN()); + AOI22_X1_LVT i_0_0_22 (.A1(JumpOrBranchPC[16]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_14), .ZN(n_0_0_5)); + INV_X1_LVT i_0_0_21 (.A(n_0_0_5), .ZN(thePC_n_46)); + SDFF_X1_LVT \thePC_CurrentPC_reg[16] (.D(thePC_n_46), .SE(scan_en), .SI( + CurrentPC[17]), .CK(clk_25mhz), .Q(CurrentPC[16]), .QN()); + AOI22_X1_LVT i_0_0_20 (.A1(JumpOrBranchPC[15]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_13), .ZN(n_0_0_4)); + INV_X1_LVT i_0_0_19 (.A(n_0_0_4), .ZN(thePC_n_45)); + SDFF_X1_LVT \thePC_CurrentPC_reg[15] (.D(thePC_n_45), .SE(scan_en), .SI( + CurrentPC[16]), .CK(clk_25mhz), .Q(CurrentPC[15]), .QN()); + AOI22_X1_LVT i_0_0_18 (.A1(JumpOrBranchPC[14]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_12), .ZN(n_0_0_3)); + INV_X1_LVT i_0_0_17 (.A(n_0_0_3), .ZN(thePC_n_44)); + SDFF_X1_LVT \thePC_CurrentPC_reg[14] (.D(thePC_n_44), .SE(scan_en), .SI( + CurrentPC[15]), .CK(clk_25mhz), .Q(CurrentPC[14]), .QN()); + AOI22_X1_LVT i_0_0_16 (.A1(JumpOrBranchPC[13]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_11), .ZN(n_0_0_2)); + INV_X1_LVT i_0_0_15 (.A(n_0_0_2), .ZN(thePC_n_43)); + SDFF_X1_LVT \thePC_CurrentPC_reg[13] (.D(thePC_n_43), .SE(scan_en), .SI( + CurrentPC[14]), .CK(clk_25mhz), .Q(CurrentPC[13]), .QN()); + MUX2_X1_LVT i_0_0_65 (.A(thePC_n_10), .B(JumpOrBranchPC[12]), .S(JumpOrBranch), + .Z(NextPC[12])); + AND2_X1_LVT i_0_0_14 (.A1(NextPC[12]), .A2(btn[0]), .ZN(thePC_n_42)); + SDFF_X1_LVT \thePC_CurrentPC_reg[12] (.D(thePC_n_42), .SE(scan_en), .SI( + CurrentPC[13]), .CK(clk_25mhz), .Q(CurrentPC[12]), .QN()); + MUX2_X1_LVT i_0_0_64 (.A(thePC_n_9), .B(JumpOrBranchPC[11]), .S(JumpOrBranch), + .Z(NextPC[11])); + AND2_X1_LVT i_0_0_13 (.A1(NextPC[11]), .A2(btn[0]), .ZN(thePC_n_41)); + SDFF_X1_LVT \thePC_CurrentPC_reg[11] (.D(thePC_n_41), .SE(scan_en), .SI( + CurrentPC[12]), .CK(clk_25mhz), .Q(CurrentPC[11]), .QN()); + MUX2_X1_LVT i_0_0_63 (.A(thePC_n_8), .B(JumpOrBranchPC[10]), .S(JumpOrBranch), + .Z(NextPC[10])); + AND2_X1_LVT i_0_0_12 (.A1(NextPC[10]), .A2(btn[0]), .ZN(thePC_n_40)); + SDFF_X1_LVT \thePC_CurrentPC_reg[10] (.D(thePC_n_40), .SE(scan_en), .SI( + CurrentPC[11]), .CK(clk_25mhz), .Q(CurrentPC[10]), .QN()); + MUX2_X1_LVT i_0_0_62 (.A(thePC_n_7), .B(JumpOrBranchPC[9]), .S(JumpOrBranch), + .Z(NextPC[9])); + AND2_X1_LVT i_0_0_11 (.A1(NextPC[9]), .A2(btn[0]), .ZN(thePC_n_39)); + SDFF_X1_LVT \thePC_CurrentPC_reg[9] (.D(thePC_n_39), .SE(scan_en), .SI( + CurrentPC[10]), .CK(clk_25mhz), .Q(CurrentPC[9]), .QN()); + MUX2_X1_LVT i_0_0_61 (.A(thePC_n_6), .B(JumpOrBranchPC[8]), .S(JumpOrBranch), + .Z(NextPC[8])); + AND2_X1_LVT i_0_0_10 (.A1(NextPC[8]), .A2(btn[0]), .ZN(thePC_n_38)); + SDFF_X1_LVT \thePC_CurrentPC_reg[8] (.D(thePC_n_38), .SE(scan_en), .SI( + CurrentPC[9]), .CK(clk_25mhz), .Q(CurrentPC[8]), .QN()); + AND2_X1_LVT i_0_0_9 (.A1(led[7]), .A2(btn[0]), .ZN(thePC_n_37)); + SDFF_X1_LVT \thePC_CurrentPC_reg[7] (.D(thePC_n_37), .SE(scan_en), .SI( + CurrentPC[8]), .CK(clk_25mhz), .Q(CurrentPC[7]), .QN()); + MUX2_X1_LVT i_0_0_59 (.A(thePC_n_4), .B(JumpOrBranchPC[6]), .S(JumpOrBranch), + .Z(led[6])); + AND2_X1_LVT i_0_0_8 (.A1(led[6]), .A2(btn[0]), .ZN(thePC_n_36)); + SDFF_X1_LVT \thePC_CurrentPC_reg[6] (.D(thePC_n_36), .SE(scan_en), .SI( + CurrentPC[7]), .CK(clk_25mhz), .Q(CurrentPC[6]), .QN()); + MUX2_X1_LVT i_0_0_58 (.A(thePC_n_3), .B(JumpOrBranchPC[5]), .S(JumpOrBranch), + .Z(led[5])); + AND2_X1_LVT i_0_0_7 (.A1(led[5]), .A2(btn[0]), .ZN(thePC_n_35)); + SDFF_X1_LVT \thePC_CurrentPC_reg[5] (.D(thePC_n_35), .SE(scan_en), .SI( + CurrentPC[6]), .CK(clk_25mhz), .Q(CurrentPC[5]), .QN()); + MUX2_X1_LVT i_0_0_57 (.A(thePC_n_2), .B(JumpOrBranchPC[4]), .S(JumpOrBranch), + .Z(led[4])); + AND2_X1_LVT i_0_0_6 (.A1(led[4]), .A2(btn[0]), .ZN(thePC_n_34)); + SDFF_X1_LVT \thePC_CurrentPC_reg[4] (.D(thePC_n_34), .SE(scan_en), .SI( + CurrentPC[5]), .CK(clk_25mhz), .Q(CurrentPC[4]), .QN()); + MUX2_X1_LVT i_0_0_56 (.A(thePC_n_1), .B(JumpOrBranchPC[3]), .S(JumpOrBranch), + .Z(led[3])); + AND2_X1_LVT i_0_0_5 (.A1(led[3]), .A2(btn[0]), .ZN(thePC_n_33)); + SDFF_X1_LVT \thePC_CurrentPC_reg[3] (.D(thePC_n_33), .SE(scan_en), .SI( + CurrentPC[4]), .CK(clk_25mhz), .Q(CurrentPC[3]), .QN()); + MUX2_X1_LVT i_0_0_55 (.A(thePC_n_0), .B(JumpOrBranchPC[2]), .S(JumpOrBranch), + .Z(led[2])); + AND2_X1_LVT i_0_0_4 (.A1(led[2]), .A2(btn[0]), .ZN(thePC_n_32)); + SDFF_X1_LVT \thePC_CurrentPC_reg[2] (.D(thePC_n_32), .SE(scan_en), .SI( + CurrentPC[3]), .CK(clk_25mhz), .Q(CurrentPC[2]), .QN()); + datapathS__0_65 thePC_i_0 (.CurrentPC({CurrentPC[31], CurrentPC[30], + CurrentPC[29], CurrentPC[28], CurrentPC[27], CurrentPC[26], CurrentPC[25], + CurrentPC[24], CurrentPC[23], CurrentPC[22], CurrentPC[21], CurrentPC[20], + CurrentPC[19], CurrentPC[18], CurrentPC[17], CurrentPC[16], CurrentPC[15], + CurrentPC[14], CurrentPC[13], CurrentPC[12], CurrentPC[11], CurrentPC[10], + CurrentPC[9], CurrentPC[8], CurrentPC[7], CurrentPC[6], CurrentPC[5], + CurrentPC[4], CurrentPC[3], CurrentPC[2], uc_0, uc_1}), .p_0({thePC_n_29, + thePC_n_28, thePC_n_27, thePC_n_26, thePC_n_25, thePC_n_24, thePC_n_23, + thePC_n_22, thePC_n_21, thePC_n_20, thePC_n_19, thePC_n_18, thePC_n_17, + thePC_n_16, thePC_n_15, thePC_n_14, thePC_n_13, thePC_n_12, thePC_n_11, + thePC_n_10, thePC_n_9, thePC_n_8, thePC_n_7, thePC_n_6, thePC_n_5, + thePC_n_4, thePC_n_3, thePC_n_2, thePC_n_1, thePC_n_0, uc_2, uc_3})); + AOI22_X1_LVT i_0_0_52 (.A1(JumpOrBranchPC[31]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(thePC_n_29), .ZN(n_0_0_20)); + INV_X1_LVT i_0_0_51 (.A(n_0_0_20), .ZN(thePC_n_61)); + SDFF_X1_LVT \thePC_CurrentPC_reg[31] (.D(thePC_n_61), .SE(scan_en), .SI( + CurrentPC[2]), .CK(clk_25mhz), .Q(CurrentPC[31]), .QN()); + AOI22_X1_LVT i_0_0_3 (.A1(JumpOrBranchPC[1]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(CurrentPC[1]), .ZN(n_0_0_1)); + INV_X1_LVT i_0_0_2 (.A(n_0_0_1), .ZN(thePC_n_31)); + SDFF_X1_LVT \thePC_CurrentPC_reg[1] (.D(thePC_n_31), .SE(scan_en), .SI( + CurrentPC[31]), .CK(clk_25mhz), .Q(CurrentPC[1]), .QN()); + AOI22_X1_LVT i_0_0_1 (.A1(JumpOrBranchPC[0]), .A2(n_0_0_22), .B1(n_0_0_21), + .B2(CurrentPC[0]), .ZN(n_0_0_0)); + INV_X1_LVT i_0_0_0 (.A(n_0_0_0), .ZN(thePC_n_30)); + SDFF_X1_LVT \thePC_CurrentPC_reg[0] (.D(thePC_n_30), .SE(scan_en), .SI( + CurrentPC[1]), .CK(clk_25mhz), .Q(CurrentPC[0]), .QN()); + reg_file theRegisters (.Rs1({Instruction[19], Instruction[18], + Instruction[17], Instruction[16], Instruction[15]}), .Rs2({Instruction[24], + Instruction[23], Instruction[22], Instruction[21], Instruction[20]}), + .Rd({Instruction[11], Instruction[10], Instruction[9], Instruction[8], + Instruction[7]}), .RRs1(RRs1), .RRs2(RRs2), .WRd(WRd), .WrReg(WrReg), + .reset(reset), .clk(clk_25mhz), .dftIn(scan_en), .ts_intno31(CurrentPC[0]), + .ts_no1050(SO_2), .ts_no1051(SO_4), .ts_no1053(SO_3), .ts_no1054(SO_1), + .ts_extsi1226(SI_2), .ts_extsi1227(SI_3), .ts_extsi1228(SI_4)); + main_mem theMem (.clk(clk_25mhz), .reset(reset), .DAddr({uc_4, uc_5, uc_6, + uc_7, uc_8, uc_9, uc_10, uc_11, uc_12, uc_13, uc_14, uc_15, uc_16, uc_17, + uc_18, uc_19, uc_20, uc_21, uc_22, DAddr[12], DAddr[11], DAddr[10], + DAddr[9], DAddr[8], DAddr[7], DAddr[6], DAddr[5], DAddr[4], DAddr[3], + DAddr[2], DAddr[1], DAddr[0]}), .IAddr({uc_23, uc_24, uc_25, uc_26, uc_27, + uc_28, uc_29, uc_30, uc_31, uc_32, uc_33, uc_34, uc_35, uc_36, uc_37, + uc_38, uc_39, uc_40, uc_41, NextPC[12], NextPC[11], NextPC[10], NextPC[9], + NextPC[8], led[7], led[6], led[5], led[4], led[3], led[2], uc_42, uc_43}), + .DWData(RRs2), .DRData(RData), .IRData(Instruction), .DWE(led[1]), + .DWidth(DWidth)); + decoder theDecoder (.CurrentPC(CurrentPC), .JumpOrBranchPC(JumpOrBranchPC), + .JumpOrBranch(JumpOrBranch), .DAddr({uc_44, uc_45, uc_46, uc_47, uc_48, + uc_49, uc_50, uc_51, uc_52, uc_53, uc_54, uc_55, uc_56, uc_57, uc_58, + uc_59, uc_60, uc_61, uc_62, DAddr[12], DAddr[11], DAddr[10], DAddr[9], + DAddr[8], DAddr[7], DAddr[6], DAddr[5], DAddr[4], DAddr[3], DAddr[2], + DAddr[1], DAddr[0]}), .WData(), .RData(RData), .Instruction(Instruction), + .WrMem(led[1]), .DWidth(DWidth), .Rs1(), .Rs2(), .Rd(), .RRs1(RRs1), + .RRs2(RRs2), .WRd(WRd), .WrReg(WrReg), .Illegal(led[0])); + MUX2_X1_LVT i_0_0_60 (.A(thePC_n_5), .B(JumpOrBranchPC[7]), .S(JumpOrBranch), + .Z(led[7])); +endmodule diff --git a/riscv_rtl/README.md b/riscv_rtl/README.md new file mode 100644 index 0000000..fe7bccd --- /dev/null +++ b/riscv_rtl/README.md @@ -0,0 +1,276 @@ +# [RISC-V Desgin in an Open_Source Design Flow](https://microtec-academy.de/produkt/risc-v-design-in-an-open-source-design-flow/) + +A RISC-V design course, where you learn about the the RISC-V theory and then use it to build your own RISC-V processor. + +This project has the full solution for the course exercises. It is able to simulate the Decoder or CPU as DUTs (device under tests). The simulation executes a SW test from a designated Hex file on the DUT. + +In this README you will learn about ... + +* what **prerequisites** you need to get this project running +* how the project is **organised** +* how to **run simulations** + +## Background + +This course is a part of the initiative [*Bavarian Chip Design Center (BCDC)*](https://www.iis.fraunhofer.de/en/ff/sse/bavarian-chip-design-center.html), which aims to develop and improve the IC-Design workforce in Bavaria. + +This course is an adaptation of the code-base developed at [Lund University](https://www.lth.se/) by Per Andersson as part of the effort to develop and improve education in Digital System Design. You can find the original source-code under [this repository](https://github.com/PalePrime/single_cycle). + +## Prerequisites + +Bash Shell Terminal + +* Windows: you need to install gitbash or use something similar +* MacOS/Linux: bash is preinstalled + +GCC Compiler + +* Installation details [here](https://gcc.gnu.org/install/) + +Verilator + +* If not installed, you can find the installation [here](https://verilator.org/guide/latest/install.html). It is highly recommended to install through a package manager for all operating systems. + * For Linux use apt package manager. Info under [verilator install guide](https://verilator.org/guide/latest/install.html#package-manager-quick-install). + * For MacOS the package manager is [homebrew](https://brew.sh/). + * For Windows an package manager option is [pacman](https://gist.github.com/AndreSteenveld/cb6662c93c8323795c5fd347defb8976) (untested). +* Export the *VERILATOR* environment variable. Make sure to use your Verilator install directory -> `export VERILATOR=/bin/verilator` + +Surfer Waveform Viewer + +* If not installed, you can find the installation [here](https://surfer-project.org/) +* Export the *WAVE_VIEWER* environment variables. Make sure to use your Surfer install directory -> `export WAVE_VIEWER=/surfer` + +IDE (optional) + +* Any IDE of your choosing will make it easy to view and manage the files + +## Project Organisation + +### Resources + +Path: `doc` + +* Module diagrams +* RISC-V Cards +* RISC-V ISM +* RISC-V ASM + +### RTL source code + +Path: `hw/rtl` + +### File lists of SV code + +Path: `hw/file_lists` + +* RTL file list +* Testbench file list + +### Verification source code + +#### SV testbenches used in EDA playground + +Path: `hw/dv/rtl` + +#### Verilator environment + +Path: `hw/dv/verilator/` + +* SV Toplevel harnesses + * Decoder + * CPU +* C++ testbenches + * Decoder + * CPU +* Makefile + +### Software and Hex programs used for testing + +Path: `sw/risc-v` + +* Main Memory: Hex code +* Decoder: + * Assembly code + * Hex code from assembeled assembly code +* Fibonacci Series/Hello World/Prime Factors: + * C Code + * Assembly code from compiled C code + * Simplified assembly code from assembly code (not available for Fibonacci Series) + * Hex code from assembeled assembly or simplified assembly code + +## Running Simulations + +### Quick start + +Run the two commands below + +``` +cd hw/dv/verilator +``` + +``` +make clean all run wave +``` + +This will convert the RTL into C++, compile the model, create the simulation binary, run the simulation, and start the waveform viewer. The output of the simulation should be the following: + +``` +*** Running simulation... + +Creating model... +Registered DPI-C functions: + scopesDump: + SCOPE 0x55616d28b940: TOP.cpu_harness + DPI-EXPORT 0x556136cc8f77: enable + DPI-EXPORT 0x556136cc8f89: getLed + DPI-EXPORT 0x556136cc8fda: getMem + DPI-EXPORT 0x556136cc9006: getReg + DPI-EXPORT 0x556136cc9242: loadRAM + DPI-EXPORT 0x556136cdcc19: printMem + DPI-EXPORT 0x556136cdcd88: printReg + DPI-EXPORT 0x556136cc8fab: setBtn + DPI-EXPORT 0x556136cc8f68: setClk + DPI-EXPORT 0x556136cc8f78: setInitial + DPI-EXPORT 0x556136cc8fea: setMem + DPI-EXPORT 0x556136cc8fc9: setReset + +Initializing SRAM memory from ../../../sw/risc-v/hello_world/helloWorld.hex +program set to helloWorld + +Starting model... + +Resetting... +Starting CPU... +Running for 500 clock cycles... + +Printing evaluation for helloWorld program! + +T=3960: Hex ASCII +Value at RAM[1024]: 0x68000000 : h +Value at RAM[1025]: 0x00000000 : +Value at RAM[1026]: 0x00000000 : +Value at RAM[1027]: 0x00000000 : + + +T=6840: Hex ASCII +Value at RAM[1024]: 0x68650000 : he +Value at RAM[1025]: 0x00000000 : +Value at RAM[1026]: 0x00000000 : +Value at RAM[1027]: 0x00000000 : + + +T=9720: Hex ASCII +Value at RAM[1024]: 0x68656c00 : hel +Value at RAM[1025]: 0x00000000 : +Value at RAM[1026]: 0x00000000 : +Value at RAM[1027]: 0x00000000 : + + +T=12600: Hex ASCII +Value at RAM[1024]: 0x68656c6c : hell +Value at RAM[1025]: 0x00000000 : +Value at RAM[1026]: 0x00000000 : +Value at RAM[1027]: 0x00000000 : + + +T=15480: Hex ASCII +Value at RAM[1024]: 0x68656c6c : hell +Value at RAM[1025]: 0x6f000000 : o +Value at RAM[1026]: 0x00000000 : +Value at RAM[1027]: 0x00000000 : + + +T=18360: Hex ASCII +Value at RAM[1024]: 0x68656c6c : hell +Value at RAM[1025]: 0x6f200000 : o +Value at RAM[1026]: 0x00000000 : +Value at RAM[1027]: 0x00000000 : + + +T=21240: Hex ASCII +Value at RAM[1024]: 0x68656c6c : hell +Value at RAM[1025]: 0x6f207700 : o w +Value at RAM[1026]: 0x00000000 : +Value at RAM[1027]: 0x00000000 : + + +T=24120: Hex ASCII +Value at RAM[1024]: 0x68656c6c : hell +Value at RAM[1025]: 0x6f20776f : o wo +Value at RAM[1026]: 0x00000000 : +Value at RAM[1027]: 0x00000000 : + + +T=27000: Hex ASCII +Value at RAM[1024]: 0x68656c6c : hell +Value at RAM[1025]: 0x6f20776f : o wo +Value at RAM[1026]: 0x72000000 : r +Value at RAM[1027]: 0x00000000 : + + +T=29880: Hex ASCII +Value at RAM[1024]: 0x68656c6c : hell +Value at RAM[1025]: 0x6f20776f : o wo +Value at RAM[1026]: 0x726c0000 : rl +Value at RAM[1027]: 0x00000000 : + + +T=32760: Hex ASCII +Value at RAM[1024]: 0x68656c6c : hell +Value at RAM[1025]: 0x6f20776f : o wo +Value at RAM[1026]: 0x726c6400 : rld +Value at RAM[1027]: 0x00000000 : + + +T=35640: Hex ASCII +Value at RAM[1024]: 0x68656c6c : hell +Value at RAM[1025]: 0x6f20776f : o wo +Value at RAM[1026]: 0x726c6421 : rld! +Value at RAM[1027]: 0x00000000 : + + +Done, closing simulation. +``` + +**Important:** The makefile reads the file lists `hw/file_lists/rtl_flist.f` and `hw/file_lists/tb_flist.f`. The make process does not recognize RTL or TB file changes, so it is required to run `make clean` after RTL or TB changes, otherwise the changed files will not be compiled. + +### Makefile details + +By default, the hex-file `sw/risc-v/hello_world.hex` is loaded into the Main Memory before starting the simulation, and the simulation is run for 500 clock cycles. This behavior can by overriden by specifying *PROG* and *NCYCLES* environment variables, which will load the specified hex file and run for the specified number of clock cycles. + +``` +make run PROG=/path/to/myprog.hex NCYCLES=2000 +``` + +You can also combine the different make targets. + +``` +make clean all run wave PROG=/path/to/myprog.hex NCYCLES=2000 +``` + +**Important:** If the simulation is not showing the full expected result, make sure that the number of cycles are sufficient for the CPU to finish executing the program (check if the last instruction executed is the *jump to halt* instruction) + +Available Make targets (commands) + +* **make clean** - remove old files +* **make** - build and compile the RTL simulator using Verilator and GCC (alias for `make all`) +* **make run** - run the simulation (requires built and compiled RTL) +* **make wave** - show the waveform in Surfer +* **make clean all run wave** - runs all the make targets (order is important) + +It is not necessary to close the Surfer viewer if the simulation is run again. Just reload the Surfer window after the new run. + +### Things you need/can change + +* In the *Makefile* + * **PROG** - variable holding the hex file path of the program to be loaded + * **NCYCLES** - Variable for the number of cycles the CPU is going to run for + * **TOPMODULE** - Variable with the module name of the harness +* Int the *tb_flist.f* + * Add new harnesses you have created + +### Things you can do + +* You can run the exact same tests you ran on EDA Playground and you should get the same results. However, the test here will be using verilator. +* You can create your own harness and C++ testbenches for modules other than Decoder and CPU to get familiar with verilator testbenches +* Compare Icarus and Verilator output (uninitialised memory locations are set to 'x' when using Icarus and '0' when using verilator) diff --git a/riscv_rtl/doc/assets/alu.drawio b/riscv_rtl/doc/assets/alu.drawio new file mode 100644 index 0000000..7535954 --- /dev/null +++ b/riscv_rtl/doc/assets/alu.drawio @@ -0,0 +1,131 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/riscv_rtl/doc/assets/cpu/core.drawio.svg b/riscv_rtl/doc/assets/cpu/core.drawio.svg new file mode 100644 index 0000000..743a310 --- /dev/null +++ b/riscv_rtl/doc/assets/cpu/core.drawio.svg @@ -0,0 +1,77 @@ + + + + + + + + + + + + + +
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main_mem
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decoder







decoder...
pc
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ALU
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RISC-V Core
RISC-V Core
reg_file
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+ + Figure 1.2: a block diagram of the decoder module with all its input and output ports. + + +
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+ + + aluNegAr + + + + + + diff --git a/riscv_rtl/doc/assets/verilator/.$verilator_architecture.drawio.bkp b/riscv_rtl/doc/assets/verilator/.$verilator_architecture.drawio.bkp new file mode 100644 index 0000000..b8a317c --- /dev/null +++ b/riscv_rtl/doc/assets/verilator/.$verilator_architecture.drawio.bkp @@ -0,0 +1,163 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/riscv_rtl/doc/assets/verilator/verilator_architecture.drawio b/riscv_rtl/doc/assets/verilator/verilator_architecture.drawio new file mode 100644 index 0000000..5ffe417 --- /dev/null +++ b/riscv_rtl/doc/assets/verilator/verilator_architecture.drawio @@ -0,0 +1,160 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/riscv_rtl/doc/assets/verilator/verilator_architecture.drawio.png b/riscv_rtl/doc/assets/verilator/verilator_architecture.drawio.png new file mode 100644 index 0000000..aae8e06 Binary files /dev/null and b/riscv_rtl/doc/assets/verilator/verilator_architecture.drawio.png differ diff --git a/riscv_rtl/doc/course_material/Computer Organization and Design - RISC-V Edition - Full ISA Summary.pdf b/riscv_rtl/doc/course_material/Computer Organization and Design - RISC-V Edition - Full ISA Summary.pdf new file mode 100644 index 0000000..098423e Binary files /dev/null and b/riscv_rtl/doc/course_material/Computer Organization and Design - RISC-V Edition - Full ISA Summary.pdf differ diff --git a/riscv_rtl/doc/course_material/RISC-V ASM.pdf b/riscv_rtl/doc/course_material/RISC-V ASM.pdf new file mode 100644 index 0000000..c0b7e43 Binary files /dev/null and b/riscv_rtl/doc/course_material/RISC-V ASM.pdf differ diff --git a/riscv_rtl/doc/course_material/RISC-V ISA Card - RV32I.pdf b/riscv_rtl/doc/course_material/RISC-V ISA Card - RV32I.pdf new file mode 100644 index 0000000..4b14e77 Binary files /dev/null and b/riscv_rtl/doc/course_material/RISC-V ISA Card - RV32I.pdf differ diff --git a/riscv_rtl/doc/course_material/RISC-V ISM - Unprivileged.pdf b/riscv_rtl/doc/course_material/RISC-V ISM - Unprivileged.pdf new file mode 100644 index 0000000..6356c54 Binary files /dev/null and b/riscv_rtl/doc/course_material/RISC-V ISM - Unprivileged.pdf differ diff --git a/riscv_rtl/dummz_memgen_16.sv b/riscv_rtl/dummz_memgen_16.sv new file mode 100644 index 0000000..f84fa3f --- /dev/null +++ b/riscv_rtl/dummz_memgen_16.sv @@ -0,0 +1,25 @@ +// MemGen_16_10_stub.sv +// Behavioral stub - ports matched from MemGen_32_11.sv instantiation +module MemGen_16_10 #( + parameter ADDR_WIDTH = 10, + parameter DATA_WIDTH = 16 +)( + input logic chip_en, + input logic clock, + input logic [ADDR_WIDTH-1:0] addr, + input logic rd_en, + output logic [DATA_WIDTH-1:0] rd_data, + input logic wr_en, + input logic [DATA_WIDTH-1:0] wr_data +); + logic [DATA_WIDTH-1:0] mem [0:(2**ADDR_WIDTH)-1]; + + always_ff @(posedge clock) begin + if (chip_en) begin + if (wr_en) + mem[addr] <= wr_data; + else if (rd_en) + rd_data <= mem[addr]; + end + end +endmodule diff --git a/riscv_rtl/hw/dv/rtl/alu_tb.sv b/riscv_rtl/hw/dv/rtl/alu_tb.sv new file mode 100644 index 0000000..29ca0d4 --- /dev/null +++ b/riscv_rtl/hw/dv/rtl/alu_tb.sv @@ -0,0 +1,112 @@ +// ********************************************************************************************* +// Project Version : v1.0 +// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog +// ----- +// Copyright (c) : 2025 Fraunhofer IIS, Department IDS +// Created : 15.Oct.2025 by Bomin Kim +// Last Modified : 23.Oct.2025 by Bomin Kim [commit 2f8f03d] +// ----- +// HISTORY : Date By Comments +// ----------- --------- ------------------------------------------------- +// ********************************************************************************************* + + + +`timescale 1ns/1ns + +module alu_tb(); + + // Local Signals + logic[2:0] aluOp; + logic aluNegAr; + logic aluBypass; + logic[31:0] op1; + logic[31:0] op2; + logic[31:0] result; + logic eqFlag; + + // Toplevel instance (DUT) + alu u_alu ( + .aluOp(aluOp), + .aluNegAr(aluNegAr), + .aluBypass(aluBypass), + .op1(op1), + .op2(op2), + .result(result), + .eqFlag(eqFlag) + ); + + // list of aluOp + localparam logic[2:0] f3add = 3'b000; + localparam logic[2:0] f3sl = 3'b001; + localparam logic[2:0] f3slt = 3'b010; + localparam logic[2:0] f3sltU = 3'b011; + localparam logic[2:0] f3xor = 3'b100; + localparam logic[2:0] f3sr = 3'b101; + localparam logic[2:0] f3or = 3'b110; + localparam logic[2:0] f3and = 3'b111; + + // Initialize and run simulation + initial begin + dumpWave("wave.vcd"); + + // Initialize inputs + aluOp = 0; + aluNegAr = 0; + aluBypass = 0; + op1 = 0; + op2 = 0; + #10 + + // Set op1 and op2 + op1 = 32'hDEAD_BEEF; op2 = 32'h0000_0001; #70 + $display("\nTime = %0dns \t : op1 = %h, op2 = %h", $time, op1, op2); + + $display("\nTime = %0dns \t : Is op1 and op2 equal?; eqFlag = %d", $time, eqFlag); + + aluBypass = 1; #70 + $display("\nTime = %0dns \t : AluBypass is set; result = %h", $time, result); + + aluBypass = 0; aluOp = f3add; #70 + $display("\nTime = %0dns \t : Alu operates addition; result = %h", $time, result); + + aluNegAr = 1; #70 + $display("\nTime = %0dns \t : Alu operates subtraction; result = %h", $time, result); + + aluNegAr = 0; aluOp = f3sl; #70 + $display("\nTime = %0dns \t : Alu operates shift left; result = %h", $time, result); + + aluOp = f3slt; #70 + $display("\nTime = %0dns \t : Alu operates set less than; result = %h", $time, result); + + aluOp = f3sltU; #70 + $display("\nTime = %0dns \t : Alu operates set less than (unsigned); result = %h", $time, result); + + aluOp = f3xor; #70 + $display("\nTime = %0dns \t : Alu operates bit-wise XOR; result = %h", $time, result); + + aluOp = f3sr; aluNegAr = 1; #70 + $display("\nTime = %0dns \t : Alu operates arithmetic right shift; result = %h", $time, result); + + aluNegAr = 0; #70 + $display("\nTime = %0dns \t : Alu operates logical right shift; result = %h", $time, result); + + aluOp = f3or; #70 + $display("\nTime = %0dns \t : Alu operates bit-wise OR; result = %h", $time, result); + + aluOp = f3and; #70 + $display("\nTime = %0dns \t : Alu operates bit-wise AND; result = %h", $time, result); + $finish; + + end + + // Wave Dump Helper Task + task dumpWave(string fileName); + // Open wave file and dump all signals (2D arrays not included) + $display("\nTime = %0dns \t : Opening wave file '%s'", $time, fileName); + $dumpfile(fileName); + $display("Time = %0dns \t : Dumping all %s signals in wave file (2D arrays not included)", $time, "alu_tb"); + $dumpvars(0, alu_tb); + endtask: dumpWave + +endmodule diff --git a/riscv_rtl/hw/dv/rtl/cpu_tb.sv b/riscv_rtl/hw/dv/rtl/cpu_tb.sv new file mode 100644 index 0000000..fde74ce --- /dev/null +++ b/riscv_rtl/hw/dv/rtl/cpu_tb.sv @@ -0,0 +1,164 @@ +// ********************************************************************************************* +// Project Version : v1.0 +// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog +// ----- +// Copyright (c) : 2025 Fraunhofer IIS, Department IDS +// Created : 15.Oct.2025 by Hussein Elzomor +// Last Modified : 23.Oct.2025 by Hussein Elzomor [commit 2f8f03d] +// ----- +// HISTORY : Date By Comments +// ----------- --------- ------------------------------------------------- +// 15.Oct.2025 H.Elzomor Renamed file and module from soc_tb to cpu_tb +// ********************************************************************************************* + + + +// `define fibonacci +// `define helloWorld +// `define primeFactors + +`timescale 1ns/1ns + +module cpu_tb (); + + // local signals + logic[7:0] led; + logic[6:0] btn; + logic reset; + logic clk; + + // Toplevel instance (DUT) + cpu u_cpu ( + .led(led), + .btn(btn), + .clk_25mhz(clk) + ); + + // Tie reset signal to the reset button + assign btn[0] = reset; + + // Clock generation + always #20 clk = ~clk; + + // Initialize and run simulation + initial begin + dumpWave("wave.vcd"); + `ifdef fibonacci + loadMem("fibonacci.hex"); + `elsif helloWorld + loadMem("helloWorld.hex"); + `elsif primeFactors + loadMem("primeFactors.hex"); + `endif + + clk = 0; + $display("\nTime = %0dns \t : Resetting the CPU", $time); + reset = 0; #100; + $display("\nTime = %0dns \t : Reset released", $time); + reset = 1; #500000; + $finish; + end + + // Fibonacci Program Monitor + `ifdef fibonacci + localparam int fibonacciStartLoc = 2027; + localparam int fibonacciLengthInWords = 10; + always_comb begin: Monitor_Fibonacci_Series_Calculation + $display("\nTime =%5dns\t\t\t Hex \t Dec", $time); + $display("Value at RAM[%0d]: 0x%h : %0d",fibonacciStartLoc+0, u_cpu.theMem.RAM[fibonacciStartLoc+0], u_cpu.theMem.RAM[fibonacciStartLoc+0]); + $display("Value at RAM[%0d]: 0x%h : %0d",fibonacciStartLoc+1, u_cpu.theMem.RAM[fibonacciStartLoc+1], u_cpu.theMem.RAM[fibonacciStartLoc+1]); + $display("Value at RAM[%0d]: 0x%h : %0d",fibonacciStartLoc+2, u_cpu.theMem.RAM[fibonacciStartLoc+2], u_cpu.theMem.RAM[fibonacciStartLoc+2]); + $display("Value at RAM[%0d]: 0x%h : %0d",fibonacciStartLoc+3, u_cpu.theMem.RAM[fibonacciStartLoc+3], u_cpu.theMem.RAM[fibonacciStartLoc+3]); + $display("Value at RAM[%0d]: 0x%h : %0d",fibonacciStartLoc+4, u_cpu.theMem.RAM[fibonacciStartLoc+4], u_cpu.theMem.RAM[fibonacciStartLoc+4]); + $display("Value at RAM[%0d]: 0x%h : %0d",fibonacciStartLoc+5, u_cpu.theMem.RAM[fibonacciStartLoc+5], u_cpu.theMem.RAM[fibonacciStartLoc+5]); + $display("Value at RAM[%0d]: 0x%h : %0d",fibonacciStartLoc+6, u_cpu.theMem.RAM[fibonacciStartLoc+6], u_cpu.theMem.RAM[fibonacciStartLoc+6]); + $display("Value at RAM[%0d]: 0x%h : %0d",fibonacciStartLoc+7, u_cpu.theMem.RAM[fibonacciStartLoc+7], u_cpu.theMem.RAM[fibonacciStartLoc+7]); + $display("Value at RAM[%0d]: 0x%h : %0d",fibonacciStartLoc+8, u_cpu.theMem.RAM[fibonacciStartLoc+8], u_cpu.theMem.RAM[fibonacciStartLoc+8]); + $display("Value at RAM[%0d]: 0x%h : %0d",fibonacciStartLoc+9, u_cpu.theMem.RAM[fibonacciStartLoc+9], u_cpu.theMem.RAM[fibonacciStartLoc+9]); + $display(""); + end + + // Hello World Program Monitor + `elsif helloWorld + localparam int helloWorldStartLoc = 1024; + localparam int helloWorldLengthInWords = 4; + always_comb begin: Monitor_Hello_World_Printing + $display("\nTime =%5dns\t\t Hex \t\t ASCII", $time); + $display("Value at RAM[%0d]: 0x%h : %0s", helloWorldStartLoc+0, u_cpu.theMem.RAM[helloWorldStartLoc+0], u_cpu.theMem.RAM[helloWorldStartLoc+0]); + $display("Value at RAM[%0d]: 0x%h : %0s", helloWorldStartLoc+1, u_cpu.theMem.RAM[helloWorldStartLoc+1], u_cpu.theMem.RAM[helloWorldStartLoc+1]); + $display("Value at RAM[%0d]: 0x%h : %0s", helloWorldStartLoc+2, u_cpu.theMem.RAM[helloWorldStartLoc+2], u_cpu.theMem.RAM[helloWorldStartLoc+2]); + $display("Value at RAM[%0d]: 0x%h : %0s", helloWorldStartLoc+3, u_cpu.theMem.RAM[helloWorldStartLoc+3], u_cpu.theMem.RAM[helloWorldStartLoc+3]); + $display(""); + end + + // Prime Factors Program Monitor + `elsif primeFactors + localparam int primeNumberReg = 16; + always_comb begin: Monitor_Factorization_Number + if(u_cpu.theRegisters.registers[primeNumberReg] > 1) + $display("\nTime =%5dns \t : Register [%0d] updated - Finding the prime factors of %0d", $time,primeNumberReg, u_cpu.theRegisters.registers[primeNumberReg]); + end + localparam int primeFactorsReg = 17; + always_comb begin: Monitor_Prime_Number + if(u_cpu.theRegisters.registers[primeFactorsReg] > 1) + $display("Time =%5dns \t : Register [%0d] updated - %0d is a prime factor", $time,primeFactorsReg, u_cpu.theRegisters.registers[primeFactorsReg]); + end + `endif + + // Wave Dump Helper Task + int i; + task dumpWave(string fileName); + // Open wave file and dump all signals (2D arrays not included) + $display("\nTime = %0dns \t : Opening wave file '%s'", $time, fileName); + $dumpfile(fileName); + $display("Time = %0dns \t : Dumping all %s signals in wave file (2D arrays not included)", $time, "cpu_tb"); + $dumpvars(0, cpu_tb); + + // Dump Memory in wave file + $display("\nTime = %0dns \t : Dumping Memory in wave file", $time); + for (i = 0; i < 100; i++) begin $dumpvars(0, cpu_tb.u_cpu.theMem.RAM[i]); end // A part of the Instruction Memory + for (i = 1024; i < 1124; i++) begin $dumpvars(0, cpu_tb.u_cpu.theMem.RAM[i]); end // A part of the Data Memory + for (i = 1968; i < 2048; i++) begin $dumpvars(0, cpu_tb.u_cpu.theMem.RAM[i]); end // A part of the Stack + + // Dump registers in wave file + $display("\nTime = %0dns \t : Dumping Registers in wave file", $time); + $dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[1]); + $dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[2]); + $dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[3]); + $dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[4]); + $dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[5]); + $dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[6]); + $dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[7]); + $dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[8]); + $dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[9]); + $dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[10]); + $dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[11]); + $dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[12]); + $dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[13]); + $dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[14]); + $dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[15]); + $dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[16]); + $dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[17]); + $dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[18]); + $dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[19]); + $dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[20]); + $dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[21]); + $dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[22]); + $dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[23]); + $dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[24]); + $dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[25]); + $dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[26]); + $dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[27]); + $dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[28]); + $dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[29]); + $dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[30]); + $dumpvars(0, cpu_tb.u_cpu.theRegisters.registers[31]); + endtask: dumpWave + + // Load hex file into memory + task loadMem (string fileName); + $display("\nTime = %0dns \t : Loading '%s' into Memory", $time, fileName); + $readmemh(fileName, cpu_tb.u_cpu.theMem.RAM); + endtask: loadMem + +endmodule diff --git a/riscv_rtl/hw/dv/rtl/decoder_tb.sv b/riscv_rtl/hw/dv/rtl/decoder_tb.sv new file mode 100644 index 0000000..3a20018 --- /dev/null +++ b/riscv_rtl/hw/dv/rtl/decoder_tb.sv @@ -0,0 +1,150 @@ +// ********************************************************************************************* +// Project Version : v1.0 +// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog +// ----- +// Copyright (c) : 2025 Fraunhofer IIS, Department IDS +// Created : 15.Oct.2025 by Hussein Elzomor +// Last Modified : 23.Oct.2025 by Hussein Elzomor [commit 2f8f03d] +// ----- +// HISTORY : Date By Comments +// ----------- --------- ------------------------------------------------- +// ********************************************************************************************* + + + +`timescale 1ns/1ns + +module decoder_tb (); + + // local Parameters + localparam MEM_SIZE = 37; + localparam REG_FILE_SIZE = 32; + + // local signals + logic clk; + int counter; + logic[31:0] mem [MEM_SIZE-1:0]; + logic[31:0] regFile [REG_FILE_SIZE-1:0]; + // PC + logic[31:0] CurrentPC; + logic[31:0] JumpOrBranchPC; + logic JumpOrBranch; + logic[31:0] NextPC; + // Memory + logic[31:0] DAddr; + logic[31:0] WData; + logic[31:0] RData; + logic[31:0] Instruction; + logic WrMem; + logic[1:0] DWidth; + // Register File; + logic[4:0] Rs1; + logic[4:0] Rs2; + logic[4:0] Rd; + logic[31:0] RRs1; + logic[31:0] RRs2; + logic[31:0] WRd; + logic WrReg; + // Protection + logic Illegal; + + // Toplevel instance (DUT) + decoder u_decoder ( + // PC + .CurrentPC(CurrentPC), + .JumpOrBranchPC(JumpOrBranchPC), + .JumpOrBranch(JumpOrBranch), + // Memory + .DAddr(DAddr), + .WData(WData), + .RData(RData), + .Instruction(Instruction), + .WrMem(WrMem), + .DWidth(DWidth), + // Register File + .Rs1(Rs1), + .Rs2(Rs2), + .Rd(Rd), + .RRs1(RRs1), + .RRs2(RRs2), + .WRd(WRd), + .WrReg(WrReg), + // Protection + .Illegal(Illegal) + ); + + // Clock generation + always begin + clk = ~clk; #1; + end + + // Load a new instruction every cycle + always_ff @(posedge clk) begin: increment_instruction_and_print_info + if (counter < MEM_SIZE) begin + if (counter > 0) printInfo(); + Instruction = mem[counter++]; + end + end + + // Return the value of the RegFile + always_comb begin: reg_file_assignment + RRs1 = regFile[Rs1]; + RRs2 = regFile[Rs2]; + end + + // Initialize and run simulation + initial begin + dumpWave("wave.vcd"); + loadMem("decoder.hex"); + clk = 1; + counter = 0; + CurrentPC = 32'hdeadbeef; + RData = 32'hbeefdead; + for(int i=0; i +#include +#include +#include +#include "Vcpu_harness.h" +#include "Vcpu_harness__Dpi.h" + +// only required for accessing model internal memory ressources via the rootp pointer. +// Bad style, better use systemverilog harness with tasks and functions to do that. +// #include "Vcpu_harness___024root.h" +// #include "svdpi.h" + + +#define SOC_CLK_PERIOD 40 + +//-------------------------------------------------------------- +/// @brief Simulation environment class for the cpu model. +/// Contains a set of high level methods for controlling the model from test environment. +class cpu +{ + private: + + Vcpu_harness *dut; + VerilatedFstC *mTrace; + vluint64_t T; + + uint32_t cpuClkState; + + bool running; + + string program; + + public: + + //-------------------------------------------------------------- + /// @brief Constructor + cpu (int argc, char** argv) + { + // setup verilator stuff + T = 0; + dut = new Vcpu_harness(); + Verilated::commandArgs(argc, argv); + Verilated::traceEverOn(true); + mTrace = new VerilatedFstC; + dut->trace(mTrace, 5); + mTrace->open("wavedump.fst"); + + cout << "Registered DPI-C functions:\n"; + Verilated::scopesDump(); + const svScope scope = svGetScopeFromName("TOP.cpu_harness"); + assert(scope); // Check for nullptr if scope not found + svSetScope(scope); + + running = false; + + // initialize all input signals + initSignals(); + + } // swirl() + + + //-------------------------------------------------------------- + /// @brief simulation tick, advances the simulation time and calls the eval() function of the model on every active clock edge + void tick () + { + int do_eval; + + if (T%SOC_CLK_PERIOD==0) { + dut->setClk(cpuClkState); + cpuClkState = 1-cpuClkState; + do_eval = 1; + } + + + // Other clock domains must be generated the same way + + // if (T%OTHER_CLK_PERIOD==0) { + // dut->setOtherClk(otherClkState); + // otherClkState = 1-otherClkState; + // do_eval = 1; + // } + + if (do_eval) { + dut->eval(); + // evaluate the LED status in each clock cycle if the CPU is running (i.e., after reset) + if (running && program == "unknown") evalLed(); + // evaluate the Fibonacci Series location in stack (starting at 2027) and print value if it has changed + if (running && program == "fibonacci") evalFibonacci(); + // evaluate the 'hello world!' location in the DataMem in each clock cycle if the CPU is running (i.e., after reset) + if (running && program == "helloWorld") evalHelloWorld(); + // evaluate the Prime Factors location in RegFile (x17) and print value if it has changed + if (running && program == "primeFactors") evalPrimeFactors(); + mTrace->dump(T); + do_eval = 0; + } + + T++; + + } // tick() + + + //-------------------------------------------------------------- + /// @brief Initialize all input signals of the hardware model to a defined value + void initSignals() + { + dut->setInitial(); + } // initSignals() + + //-------------------------------------------------------------- + /// @brief Wait for a number of active edges of clk signal + /// @param numEdges number of rising edges + /// @param active active 1=rising 0=falling edge + void waitClocks (int numEdges=1, int activeEdge=1) + { + int clk_d; + + for (int j=0; jsetReset(0); // reset is active low + waitClocks (numEdges); + dut->setReset(1); + } // reset(); + + //-------------------------------------------------------------- + /// @brief load the cpu memory from vmem formatted file + void loadRAM (char* vmemFile) + { + dut->loadRAM(vmemFile); + } // loadRAM() + + /// @brief check the LED status and print value if it has change + void evalLed () + { + static uint8_t oldLedStatus=0xff; + uint8_t currentLedStatus; + currentLedStatus=dut->getLed(); + if (currentLedStatus!=oldLedStatus) { + cout << "T=" << T << ": LED=" << std::bitset<8>(currentLedStatus) << endl; + oldLedStatus = currentLedStatus; + } + } // evalLed() + + /// @brief check Fibonacci Series location in stack (starting at 2027) and print value if it has changed + void evalFibonacci() + { + int memStartLoc = 2027; + const int memLengthInBytes = 40; + const int memLengthInWords = ceil(memLengthInBytes / 4.0); + static uint32_t oldValue[memLengthInWords]; + uint32_t vlaue[memLengthInWords]; + bool update = 0; + for (int i = 0; i < memLengthInWords; i++) + { + vlaue[i] = dut->getMem(memStartLoc + i); + if (oldValue[i] != vlaue[i]) + update = 1; + } + if (update) + { + cout << endl + << "T=" << T << ": \t Hex \t Dec" << endl; + for (int i = 0; i < memLengthInWords; i++) + { + dut->printMem(memStartLoc + i, "fibonacci"); + oldValue[i] = vlaue[i]; + } + cout << endl; + } + } // evalFibonacci() + + /// @brief check 'hello world' location in DataMem (starting at 1024) and print value if it has changed + void evalHelloWorld() + { + int memStartLoc = 1024; + const int memLengthInBytes = 13; + const int memLengthInWords = ceil(memLengthInBytes / 4.0); + static uint32_t oldValue[memLengthInWords]; + uint32_t vlaue[memLengthInWords]; + bool update = 0; + for (int i = 0; i < memLengthInWords; i++) + { + vlaue[i] = dut->getMem(memStartLoc + i); + if (oldValue[i] != vlaue[i]) + update = 1; + } + if (update) + { + cout << endl + << "T=" << T << ": \t Hex \t ASCII" << endl; + for (int i = 0; i < memLengthInWords; i++) + { + dut->printMem(memStartLoc + i, "helloWorld"); + oldValue[i] = vlaue[i]; + } + cout << endl; + } + } // evalHelloWorld() + + /// @brief check Prime Factors location in RegFile (x17) and print value if it has changed + void evalPrimeFactors() + { + // Number to be factorised + int regLoc_Number = 16; + static uint32_t oldValue_Number; + uint32_t value_Number; + value_Number = dut->getReg(regLoc_Number); + if (oldValue_Number != value_Number & value_Number > 1) dut->printReg(regLoc_Number, "primeNumber"); + oldValue_Number = value_Number; + + // Prime Factors + int regLoc_PrimeFactor = 17; + static uint32_t oldValue_PrimeFactor; + uint32_t value_PrimeFactor; + value_PrimeFactor = dut->getReg(regLoc_PrimeFactor); + if (oldValue_PrimeFactor != value_PrimeFactor & value_PrimeFactor > 1) dut->printReg(regLoc_PrimeFactor, "primeFactors"); + oldValue_PrimeFactor = value_PrimeFactor; + + } // evalPrimeFactors() + + //-------------------------------------------------------------- + /// @brief start the DUT + void start() + { + running = true; + dut->enable(1); + } // start() + + + //-------------------------------------------------------------- + /// @brief close the trace file and delete the Verilator object + void stop() + { + dut->enable(0); + mTrace->close(); + delete dut; + } // stop() + + //-------------------------------------------------------------- + /// @brief Set the program name + void setProgram(string prog) + { + if (prog.find("fibonacci") != string::npos) program = "fibonacci"; + else if (prog.find("helloWorld") != string::npos) program = "helloWorld"; + else if (prog.find("primeFactors") != string::npos) program = "primeFactors"; + else program = "unknown"; + + cout << "program set to " << program << endl; + } // setProgram() + + //-------------------------------------------------------------- + /// @brief Get the program name + string getProgram() + { + return program; + } // getProgram() + +}; // class cpu + + + + + +int main (int argc, char** argv) +{ + uint32_t nCycles; + char* program_path = new char[strlen(argv[2])](); + + // Get number of simulation cycles + nCycles = atoi(argv[1]); + + // Get the program + program_path = argv[2]; + string program_path_str = program_path; + + cout << "\nCreating model...\n"; + cpu *m = new cpu(argc, argv); + m->loadRAM(program_path); + m->setProgram(program_path_str); + + cout << "\nStarting model...\n"; + + cout << "\nResetting...\n"; + m->reset(10); + + cout << "Starting CPU...\n" << std::flush; + m->start(); + + cout << "Running for " << nCycles << " clock cycles...\n\n" << std::flush; + cout << "Printing evaluation for " << m->getProgram() << " program!\n" << std::flush; + m->waitClocks(nCycles); + + cout << "\nDone, closing simulation.\n\n\n" << std::flush; + m->stop(); + delete m; + + exit(EXIT_SUCCESS); +} diff --git a/riscv_rtl/hw/dv/verilator/src/tb_decoder_harness.cpp b/riscv_rtl/hw/dv/verilator/src/tb_decoder_harness.cpp new file mode 100644 index 0000000..d3d804a --- /dev/null +++ b/riscv_rtl/hw/dv/verilator/src/tb_decoder_harness.cpp @@ -0,0 +1,185 @@ +// ********************************************************************************************* +// Description : Verilator tb +// Project Version : v1.0 +// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog +// ----- +// Copyright (c) : 2025 Fraunhofer IIS, Department IDS +// Created : 15.Oct.2025 by Hussein Elzomor +// Last Modified : 15.Oct.2025 by Hussein Elzomor +// ----- +// HISTORY : Date By Comments +// ----------- --------- ------------------------------------------------- +// ********************************************************************************************* + + + +using namespace std; + +#include +#include +#include +#include +#include "Vdecoder_harness.h" +#include "Vdecoder_harness__Dpi.h" + +// only required for accessing model internal memory ressources via the rootp pointer. +// Bad style, better use systemverilog harness with tasks and functions to do that. +// #include "Vdecoder_harness___024root.h" +// #include "svdpi.h" + + +#define DECODER_CLK_PERIOD 40 + +//-------------------------------------------------------------- +/// @brief Simulation environment class for the decoder model. +/// Contains a set of high level methods for controlling the model from test environment. +class decoder +{ + private: + + Vdecoder_harness *dut; + VerilatedFstC *mTrace; + vluint64_t T; + + uint32_t decoderClkState; + bool running; + + public: + + //-------------------------------------------------------------- + /// @brief Constructor + decoder (int argc, char** argv) + { + // setup verilator stuff + T = 0; + dut = new Vdecoder_harness(); + Verilated::commandArgs(argc, argv); + Verilated::traceEverOn(true); + mTrace = new VerilatedFstC; + dut->trace(mTrace, 5); + mTrace->open("wavedump.fst"); + + cout << "Registered DPI-C functions:\n"; + Verilated::scopesDump(); + const svScope scope = svGetScopeFromName("TOP.decoder_harness"); + assert(scope); // Check for nullptr if scope not found + svSetScope(scope); + + running = false; + + // initialize all input signals + initSignals(); + + } // swirl() + + + //-------------------------------------------------------------- + /// @brief simulation tick, advances the simulation time and calls the eval() function of the model on every active clock edge + void tick () + { + int do_eval; + + if (T%DECODER_CLK_PERIOD==0) { + dut->setClk(decoderClkState); + decoderClkState = 1-decoderClkState; + do_eval = 1; + } + + if (do_eval) { + dut->eval(); + mTrace->dump(T); + do_eval = 0; + } + + T++; + + } // tick() + + + //-------------------------------------------------------------- + /// @brief Initialize all input signals of the hardware model to a defined value + void initSignals() + { + dut->setInitial(); + } // initSignals() + + //-------------------------------------------------------------- + /// @brief Wait for a number of active edges of clk signal + /// @param numEdges number of rising edges + /// @param active active 1=rising 0=falling edge + void waitClocks (int numEdges=1, int activeEdge=1) + { + int clk_d; + + for (int j=0; jloadRAM(vmemFile); + } // loadRAM() + + //-------------------------------------------------------------- + /// @brief start the DUT + void start() + { + running = true; + dut->enable(1); + } // start() + + + //-------------------------------------------------------------- + /// @brief close the trace file and delete the Verilator object + void stop() + { + dut->enable(0); + mTrace->close(); + delete dut; + } // stop() + + //-------------------------------------------------------------- + /// @brief print signal info + void printInfo() + { + dut->printInfo(); + } +}; // class decoder + + + + + +int main (int argc, char** argv) +{ + uint32_t nCycles; + int r; + + // Get number of simulation cycles + nCycles = atoi(argv[1]); + + cout << "\nCreating model...\n"; + decoder *m = new decoder(argc, argv); + m->loadRAM(argv[2]); + + cout << "Starting DECODER simulation...\n" << std::flush; + m->start(); + + cout << "Running for " << nCycles << " clock cycles...\n" << std::flush; + m->waitClocks(nCycles); + + m->printInfo(); + + cout << "\nDone, closing simulation.\n\n\n" << std::flush; + m->stop(); + delete m; + + exit(EXIT_SUCCESS); +} diff --git a/riscv_rtl/hw/dv/wave_configs/icarus_wave.surf.ron b/riscv_rtl/hw/dv/wave_configs/icarus_wave.surf.ron new file mode 100644 index 0000000..7246d2e --- /dev/null +++ b/riscv_rtl/hw/dv/wave_configs/icarus_wave.surf.ron @@ -0,0 +1,6533 @@ +( + show_hierarchy: None, + show_menu: None, + show_ticks: None, + show_toolbar: None, + show_tooltip: None, + show_scope_tooltip: Some(true), + show_default_timeline: None, + show_overview: None, + show_statusbar: None, + align_names_right: Some(true), + show_variable_indices: None, + show_variable_direction: None, + show_empty_scopes: Some(false), + show_parameters_in_scopes: None, + highlight_focused: Some(true), + fill_high_values: Some(true), + primary_button_drag_behavior: None, + arrow_key_bindings: None, + clock_highlight_type: None, + hierarchy_style: Some(Separate), + autoload_sibling_state_files: None, + autoreload_files: None, + waves: Some(( + source: File("result/wave.vcd"), + format: Vcd, + active_scope: Some(WaveScope(( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ))), + items_tree: ( + items: [ + ( + item_ref: (319), + level: 0, + unfolded: true, + selected: false, + ), + ( + item_ref: (320), + level: 0, + unfolded: true, + selected: false, + ), + ( + item_ref: (321), + level: 0, + unfolded: true, + selected: false, + ), + ( + item_ref: (322), + level: 0, + unfolded: true, + selected: false, + ), + ( + item_ref: (323), + level: 0, + unfolded: true, + selected: false, + ), + ( + item_ref: (324), + level: 0, + unfolded: true, + selected: false, + ), + ( + item_ref: (325), + level: 0, + unfolded: true, + selected: false, + ), + ( + item_ref: (326), + level: 0, + unfolded: true, + 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format: None, + field_formats: [], + height_scaling_factor: None, + )), + (451): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[1980]", + id: Wellen((349)), + ), + color: None, + background_color: None, + display_name: "[1980] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (298): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theRegisters", + "\\registers", + ], + id: Wellen((17)), + ), + name: "[15]", + id: Wellen((431)), + ), + color: None, + background_color: None, + display_name: "…\\registers.[15] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (335): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + ], + id: Wellen((3)), + ), + name: "RRs2", + id: Wellen((18)), + ), + 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manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (286): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theRegisters", + "\\registers", + ], + id: Wellen((17)), + ), + name: "[3]", + id: Wellen((419)), + ), + color: None, + background_color: None, + display_name: "…\\registers.[3] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (266): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2032]", + id: Wellen((401)), + ), + color: None, + background_color: None, + display_name: "[2032] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (420): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + 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None, + )), + (294): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theRegisters", + "\\registers", + ], + id: Wellen((17)), + ), + name: "[11]", + id: Wellen((427)), + ), + color: None, + background_color: None, + display_name: "…\\registers.[11] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (289): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theRegisters", + "\\registers", + ], + id: Wellen((17)), + ), + name: "[6]", + id: Wellen((422)), + ), + color: None, + background_color: None, + display_name: "…\\registers.[6] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (388): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[40]", + id: Wellen((177)), + ), + color: None, + background_color: None, + display_name: "[40] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (261): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2027]", + id: Wellen((396)), + ), + color: None, + background_color: None, + display_name: "[2027] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (303): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theRegisters", + "\\registers", + ], + id: Wellen((17)), + ), + name: "[20]", + id: Wellen((436)), + ), + color: None, + background_color: None, + display_name: "…\\registers.[20] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (457): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[1986]", + id: Wellen((355)), + ), + color: None, + background_color: None, + display_name: "[1986] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (405): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[57]", + id: Wellen((194)), + ), + color: None, + background_color: None, + display_name: "[57] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (422): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[74]", + id: Wellen((211)), + ), + color: None, + background_color: None, + display_name: "[74] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (475): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2004]", + id: Wellen((373)), + ), + color: None, + background_color: None, + display_name: "[2004] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (467): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[1996]", + id: Wellen((365)), + ), + color: None, + background_color: None, + display_name: "[1996] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (464): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[1993]", + id: Wellen((362)), + ), + color: None, + background_color: None, + display_name: "[1993] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (354): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[7]", + id: Wellen((144)), + ), + color: None, + background_color: None, + display_name: "…\\RAM.[7] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (488): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2017]", + id: Wellen((386)), + ), + color: None, + background_color: None, + display_name: "[2017] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (414): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[66]", + id: Wellen((203)), + ), + color: None, + background_color: None, + display_name: "[66] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (306): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theRegisters", + "\\registers", + ], + id: Wellen((17)), + ), + name: "[23]", + id: Wellen((439)), + ), + color: None, + background_color: None, + display_name: "…\\registers.[23] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (491): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2020]", + id: Wellen((389)), + ), + color: None, + background_color: None, + display_name: "[2020] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (331): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + ], + id: Wellen((3)), + ), + name: "Rs1", + id: Wellen((16)), + ), + color: None, + background_color: None, + display_name: "Rs1 [4:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (297): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theRegisters", + "\\registers", + ], + id: Wellen((17)), + ), + name: "[14]", + id: Wellen((430)), + ), + color: None, + background_color: None, + display_name: "…\\registers.[14] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (374): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[26]", + id: Wellen((163)), + ), + color: None, + background_color: None, + display_name: "…\\RAM.[26] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (287): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theRegisters", + "\\registers", + ], + id: Wellen((17)), + ), + name: "[4]", + id: Wellen((420)), + ), + color: None, + background_color: None, + display_name: "…\\registers.[4] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (380): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[32]", + id: Wellen((169)), + ), + color: None, + background_color: None, + display_name: "[32] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (296): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theRegisters", + "\\registers", + ], + id: Wellen((17)), + ), + name: "[13]", + id: Wellen((429)), + ), + color: None, + background_color: None, + display_name: "…\\registers.[13] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (355): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[8]", + id: Wellen((145)), + ), + color: None, + background_color: None, + display_name: "…\\RAM.[8] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (416): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[68]", + id: Wellen((205)), + ), + color: None, + background_color: None, + display_name: "[68] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (425): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[77]", + id: Wellen((214)), + ), + color: None, + background_color: None, + display_name: "[77] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (469): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[1998]", + id: Wellen((367)), + ), + color: None, + background_color: None, + display_name: "[1998] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (412): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[64]", + id: Wellen((201)), + ), + color: None, + background_color: None, + display_name: "[64] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (406): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[58]", + id: Wellen((195)), + ), + color: None, + background_color: None, + display_name: "[58] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (312): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theRegisters", + "\\registers", + ], + id: Wellen((17)), + ), + name: "[29]", + id: Wellen((445)), + ), + color: None, + background_color: None, + display_name: "…\\registers.[29] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (381): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[33]", + id: Wellen((170)), + ), + color: None, + background_color: None, + display_name: "[33] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (314): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theRegisters", + "\\registers", + ], + id: Wellen((17)), + ), + name: "[31]", + id: Wellen((447)), + ), + color: None, + background_color: None, + display_name: "…\\registers.[31] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (446): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[1030]", + id: Wellen((243)), + ), + color: None, + background_color: None, + display_name: "[1030] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (359): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[12]", + id: Wellen((149)), + ), + color: None, + background_color: None, + display_name: "…\\RAM.[12] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (490): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2019]", + id: Wellen((388)), + ), + color: None, + background_color: None, + display_name: "[2019] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (486): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2015]", + id: Wellen((384)), + ), + color: None, + background_color: None, + display_name: "[2015] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (461): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[1990]", + id: Wellen((359)), + ), + color: None, + background_color: None, + display_name: "[1990] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (326): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + ], + id: Wellen((3)), + ), + name: "NextPC", + id: Wellen((21)), + ), + color: None, + background_color: None, + display_name: "NextPC [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (302): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theRegisters", + "\\registers", + ], + id: Wellen((17)), + ), + name: "[19]", + id: Wellen((435)), + ), + color: None, + background_color: None, + display_name: "…\\registers.[19] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (479): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2008]", + id: Wellen((377)), + ), + color: None, + background_color: None, + display_name: "[2008] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (484): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2013]", + id: Wellen((382)), + ), + color: None, + background_color: None, + display_name: "[2013] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (343): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + ], + id: Wellen((3)), + ), + name: "WrMem", + id: Wellen((12)), + ), + color: None, + background_color: None, + display_name: "WrMem", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (395): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[47]", + id: Wellen((184)), + ), + color: None, + background_color: None, + display_name: "[47] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (418): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[70]", + id: Wellen((207)), + ), + color: None, + background_color: None, + display_name: "[70] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (478): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2007]", + id: Wellen((376)), + ), + color: None, + background_color: None, + display_name: "[2007] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (391): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[43]", + id: Wellen((180)), + ), + color: None, + background_color: None, + display_name: "[43] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (340): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + ], + id: Wellen((3)), + ), + name: "DAddr", + id: Wellen((27)), + ), + color: None, + background_color: None, + display_name: "DAddr [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (363): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[16]", + id: Wellen((153)), + ), + color: None, + background_color: None, + display_name: "…\\RAM.[16] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (321): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + ], + id: Wellen((3)), + ), + name: "reset", + id: Wellen((9)), + ), + color: None, + background_color: None, + display_name: "reset", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (339): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + ], + id: Wellen((3)), + ), + name: "DWidth", + id: Wellen((26)), + ), + color: None, + background_color: None, + display_name: "DWidth [1:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (471): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2000]", + id: Wellen((369)), + ), + color: None, + background_color: None, + display_name: "[2000] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (393): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[45]", + id: Wellen((182)), + ), + color: None, + background_color: None, + display_name: "[45] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (275): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2041]", + id: Wellen((410)), + ), + color: None, + background_color: None, + display_name: "[2041] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (473): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2002]", + id: Wellen((371)), + ), + color: None, + background_color: None, + display_name: "[2002] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (463): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[1992]", + id: Wellen((361)), + ), + color: None, + background_color: None, + display_name: "[1992] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (424): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[76]", + id: Wellen((213)), + ), + color: None, + background_color: None, + display_name: "[76] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (285): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theRegisters", + "\\registers", + ], + id: Wellen((17)), + ), + name: "[2]", + id: Wellen((418)), + ), + color: None, + background_color: None, + display_name: "…\\registers.[2] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (456): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[1985]", + id: Wellen((354)), + ), + color: None, + background_color: None, + display_name: "[1985] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (265): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2031]", + id: Wellen((400)), + ), + color: None, + background_color: None, + display_name: "[2031] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (452): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[1981]", + id: Wellen((350)), + ), + color: None, + background_color: None, + display_name: "[1981] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (409): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[61]", + id: Wellen((198)), + ), + color: None, + background_color: None, + display_name: "[61] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (322): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + ], + id: Wellen((3)), + ), + name: "Illegal", + id: Wellen((25)), + ), + color: None, + background_color: None, + display_name: "Illegal", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (262): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2028]", + id: Wellen((397)), + ), + color: None, + background_color: None, + display_name: "[2028] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (347): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[1]", + id: Wellen((138)), + ), + color: None, + background_color: None, + display_name: "…\\RAM.[1] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (495): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2024]", + id: Wellen((393)), + ), + color: None, + background_color: None, + display_name: "[2024] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (448): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[1032]", + id: Wellen((245)), + ), + color: None, + background_color: None, + display_name: "[1032] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (402): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[54]", + id: Wellen((191)), + ), + color: None, + background_color: None, + display_name: "[54] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (341): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + ], + id: Wellen((3)), + ), + name: "RData", + id: Wellen((20)), + ), + color: None, + background_color: None, + display_name: "RData [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (455): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[1984]", + id: Wellen((353)), + ), + color: None, + background_color: None, + display_name: "[1984] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (394): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[46]", + id: Wellen((183)), + ), + color: None, + background_color: None, + display_name: "[46] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (441): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[1025]", + id: Wellen((238)), + ), + color: None, + background_color: None, + display_name: "[1025] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (323): Divider(( + color: None, + background_color: None, + name: None, + )), + (327): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + ], + id: Wellen((3)), + ), + name: "JumpOrBranchPC", + id: Wellen((22)), + ), + color: None, + background_color: None, + display_name: "JumpOrBranchPC [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (364): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[17]", + id: Wellen((154)), + ), + color: None, + background_color: None, + display_name: "…\\RAM.[17] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (365): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[18]", + id: Wellen((155)), + ), + color: None, + background_color: None, + display_name: "…\\RAM.[18] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (398): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[50]", + id: Wellen((187)), + ), + color: None, + background_color: None, + display_name: "[50] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (292): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theRegisters", + "\\registers", + ], + id: Wellen((17)), + ), + name: "[9]", + id: Wellen((425)), + ), + color: None, + background_color: None, + display_name: "…\\registers.[9] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (487): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2016]", + id: Wellen((385)), + ), + color: None, + background_color: None, + display_name: "[2016] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (401): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[53]", + id: Wellen((190)), + ), + color: None, + background_color: None, + display_name: "[53] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (434): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[86]", + id: Wellen((223)), + ), + color: None, + background_color: None, + display_name: "[86] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (358): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[11]", + id: Wellen((148)), + ), + color: None, + background_color: None, + display_name: "…\\RAM.[11] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (440): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[1024]", + id: Wellen((237)), + ), + color: None, + background_color: None, + display_name: "[1024] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (320): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + ], + id: Wellen((3)), + ), + name: "clk12p5", + id: Wellen((29)), + ), + color: None, + background_color: None, + display_name: "clk12p5", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (308): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theRegisters", + "\\registers", + ], + id: Wellen((17)), + ), + name: "[25]", + id: Wellen((441)), + ), + color: None, + background_color: None, + display_name: "…\\registers.[25] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (423): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[75]", + id: Wellen((212)), + ), + color: None, + background_color: None, + display_name: "[75] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (313): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theRegisters", + "\\registers", + ], + id: Wellen((17)), + ), + name: "[30]", + id: Wellen((446)), + ), + color: None, + background_color: None, + display_name: "…\\registers.[30] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (276): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2042]", + id: Wellen((411)), + ), + color: None, + background_color: None, + display_name: "[2042] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (477): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2006]", + id: Wellen((375)), + ), + color: None, + background_color: None, + display_name: "[2006] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (390): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[42]", + id: Wellen((179)), + ), + color: None, + background_color: None, + display_name: "[42] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (375): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[27]", + id: Wellen((164)), + ), + color: None, + background_color: None, + display_name: "…\\RAM.[27] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (351): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[5]", + id: Wellen((142)), + ), + color: None, + background_color: None, + display_name: "…\\RAM.[5] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (468): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[1997]", + id: Wellen((366)), + ), + color: None, + background_color: None, + display_name: "[1997] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (494): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2023]", + id: Wellen((392)), + ), + color: None, + background_color: None, + display_name: "[2023] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (342): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + ], + id: Wellen((3)), + ), + name: "WData", + id: Wellen((14)), + ), + color: None, + background_color: None, + display_name: "WData [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (279): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2045]", + id: Wellen((414)), + ), + color: None, + background_color: None, + display_name: "[2045] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (330): Divider(( + color: None, + background_color: None, + name: None, + )), + (445): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[1029]", + id: Wellen((242)), + ), + color: None, + background_color: None, + display_name: "[1029] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (272): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2038]", + id: Wellen((407)), + ), + color: None, + background_color: None, + display_name: "[2038] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (404): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[56]", + id: Wellen((193)), + ), + color: None, + background_color: None, + display_name: "[56] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (419): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[71]", + id: Wellen((208)), + ), + color: None, + background_color: None, + display_name: "[71] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (443): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[1027]", + id: Wellen((240)), + ), + color: None, + background_color: None, + display_name: "[1027] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (357): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[10]", + id: Wellen((147)), + ), + color: None, + background_color: None, + display_name: "…\\RAM.[10] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (493): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2022]", + id: Wellen((391)), + ), + color: None, + background_color: None, + display_name: "[2022] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (411): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[63]", + id: Wellen((200)), + ), + color: None, + background_color: None, + display_name: "[63] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (453): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[1982]", + id: Wellen((351)), + ), + color: None, + background_color: None, + display_name: "[1982] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (438): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[90]", + id: Wellen((227)), + ), + color: None, + background_color: None, + display_name: "[90] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (384): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[36]", + id: Wellen((173)), + ), + color: None, + background_color: None, + display_name: "[36] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (301): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theRegisters", + "\\registers", + ], + id: Wellen((17)), + ), + name: "[18]", + id: Wellen((434)), + ), + color: None, + background_color: None, + display_name: "…\\registers.[18] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (430): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[82]", + id: Wellen((219)), + ), + color: None, + background_color: None, + display_name: "[82] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (378): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[30]", + id: Wellen((167)), + ), + color: None, + background_color: None, + display_name: "…\\RAM.[30] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (271): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2037]", + id: Wellen((406)), + ), + color: None, + background_color: None, + display_name: "[2037] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (408): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[60]", + id: Wellen((197)), + ), + color: None, + background_color: None, + display_name: "[60] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (304): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theRegisters", + "\\registers", + ], + id: Wellen((17)), + ), + name: "[21]", + id: Wellen((437)), + ), + color: None, + background_color: None, + display_name: "…\\registers.[21] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (460): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[1989]", + id: Wellen((358)), + ), + color: None, + background_color: None, + display_name: "[1989] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (267): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2033]", + id: Wellen((402)), + ), + color: None, + background_color: None, + display_name: "[2033] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (334): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + ], + id: Wellen((3)), + ), + name: "RRs1", + id: Wellen((19)), + ), + color: None, + background_color: None, + display_name: "RRs1 [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (344): Divider(( + color: None, + background_color: None, + name: None, + )), + (480): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2009]", + id: Wellen((378)), + ), + color: None, + background_color: None, + display_name: "[2009] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (350): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[4]", + id: Wellen((141)), + ), + color: None, + background_color: None, + display_name: "…\\RAM.[4] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (260): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2026]", + id: Wellen((395)), + ), + color: None, + background_color: None, + display_name: "[2026] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (387): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[39]", + id: Wellen((176)), + ), + color: None, + background_color: None, + display_name: "[39] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (368): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[21]", + id: Wellen((158)), + ), + color: None, + background_color: None, + display_name: "…\\RAM.[21] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (421): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[73]", + id: Wellen((210)), + ), + color: None, + background_color: None, + display_name: "[73] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (333): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + ], + id: Wellen((3)), + ), + name: "Rd", + id: Wellen((17)), + ), + color: None, + background_color: None, + display_name: "Rd [4:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (427): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[79]", + id: Wellen((216)), + ), + color: None, + background_color: None, + display_name: "[79] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (397): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[49]", + id: Wellen((186)), + ), + color: None, + background_color: None, + display_name: "[49] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (476): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2005]", + id: Wellen((374)), + ), + color: None, + background_color: None, + display_name: "[2005] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (472): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2001]", + id: Wellen((370)), + ), + color: None, + background_color: None, + display_name: "[2001] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (403): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[55]", + id: Wellen((192)), + ), + color: None, + background_color: None, + display_name: "[55] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (444): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[1028]", + id: Wellen((241)), + ), + color: None, + background_color: None, + display_name: "[1028] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (280): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2046]", + id: Wellen((415)), + ), + color: None, + background_color: None, + display_name: "[2046] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (281): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2047]", + id: Wellen((416)), + ), + color: None, + background_color: None, + display_name: "[2047] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (336): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + ], + id: Wellen((3)), + ), + name: "WRd", + id: Wellen((13)), + ), + color: None, + background_color: None, + display_name: "WRd [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (485): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2014]", + id: Wellen((383)), + ), + color: None, + background_color: None, + display_name: "[2014] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (459): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[1988]", + id: Wellen((357)), + ), + color: None, + background_color: None, + display_name: "[1988] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (400): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[52]", + id: Wellen((189)), + ), + color: None, + background_color: None, + display_name: "[52] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (338): Divider(( + color: None, + background_color: None, + name: None, + )), + (311): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theRegisters", + "\\registers", + ], + id: Wellen((17)), + ), + name: "[28]", + id: Wellen((444)), + ), + color: None, + background_color: None, + display_name: "…\\registers.[28] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (442): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[1026]", + id: Wellen((239)), + ), + color: None, + background_color: None, + display_name: "[1026] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (436): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[88]", + id: Wellen((225)), + ), + color: None, + background_color: None, + display_name: "[88] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (396): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[48]", + id: Wellen((185)), + ), + color: None, + background_color: None, + display_name: "[48] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (454): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[1983]", + id: Wellen((352)), + ), + color: None, + background_color: None, + display_name: "[1983] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (274): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2040]", + id: Wellen((409)), + ), + color: None, + background_color: None, + display_name: "[2040] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (458): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[1987]", + id: Wellen((356)), + ), + color: None, + background_color: None, + display_name: "[1987] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (305): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theRegisters", + "\\registers", + ], + id: Wellen((17)), + ), + name: "[22]", + id: Wellen((438)), + ), + color: None, + background_color: None, + display_name: "…\\registers.[22] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (337): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + ], + id: Wellen((3)), + ), + name: "WrReg", + id: Wellen((11)), + ), + color: None, + background_color: None, + display_name: "WrReg", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (465): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[1994]", + id: Wellen((363)), + ), + color: None, + background_color: None, + display_name: "[1994] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (293): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theRegisters", + "\\registers", + ], + id: Wellen((17)), + ), + name: "[10]", + id: Wellen((426)), + ), + color: None, + background_color: None, + display_name: "…\\registers.[10] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (277): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2043]", + id: Wellen((412)), + ), + color: None, + background_color: None, + display_name: "[2043] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (426): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[78]", + id: Wellen((215)), + ), + color: None, + background_color: None, + display_name: "[78] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (431): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[83]", + id: Wellen((220)), + ), + color: None, + background_color: None, + display_name: "[83] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (309): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theRegisters", + "\\registers", + ], + id: Wellen((17)), + ), + name: "[26]", + id: Wellen((442)), + ), + color: None, + background_color: None, + display_name: "…\\registers.[26] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (282): Group(( + name: "Stack", + color: None, + background_color: None, + content: [], + is_open: false, + )), + (439): Group(( + name: "InstrMem", + color: None, + background_color: None, + content: [], + is_open: false, + )), + (371): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[24]", + id: Wellen((161)), + ), + color: None, + background_color: None, + display_name: "…\\RAM.[24] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (379): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[31]", + id: Wellen((168)), + ), + color: None, + background_color: None, + display_name: "…\\RAM.[31] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (492): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2021]", + id: Wellen((390)), + ), + color: None, + background_color: None, + display_name: "[2021] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (482): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2011]", + id: Wellen((380)), + ), + color: None, + background_color: None, + display_name: "[2011] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (349): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[3]", + id: Wellen((140)), + ), + color: None, + background_color: None, + display_name: "…\\RAM.[3] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (362): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[15]", + id: Wellen((152)), + ), + color: None, + background_color: None, + display_name: "…\\RAM.[15] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (315): Group(( + name: "RegFile", + color: None, + background_color: None, + content: [], + is_open: false, + )), + (360): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[13]", + id: Wellen((150)), + ), + color: None, + background_color: None, + display_name: "…\\RAM.[13] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (386): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[38]", + id: Wellen((175)), + ), + color: None, + background_color: None, + display_name: "[38] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (415): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[67]", + id: Wellen((204)), + ), + color: None, + background_color: None, + display_name: "[67] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (449): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[1033]", + id: Wellen((246)), + ), + color: None, + background_color: None, + display_name: "[1033] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (369): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[22]", + id: Wellen((159)), + ), + color: None, + background_color: None, + display_name: "…\\RAM.[22] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (385): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[37]", + id: Wellen((174)), + ), + color: None, + background_color: None, + display_name: "[37] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (447): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[1031]", + id: Wellen((244)), + ), + color: None, + background_color: None, + display_name: "[1031] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (483): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2012]", + id: Wellen((381)), + ), + color: None, + background_color: None, + display_name: "[2012] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (389): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[41]", + id: Wellen((178)), + ), + color: None, + background_color: None, + display_name: "[41] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (462): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[1991]", + id: Wellen((360)), + ), + color: None, + background_color: None, + display_name: "[1991] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (268): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2034]", + id: Wellen((403)), + ), + color: None, + background_color: None, + display_name: "[2034] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (288): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theRegisters", + "\\registers", + ], + id: Wellen((17)), + ), + name: "[5]", + id: Wellen((421)), + ), + color: None, + background_color: None, + display_name: "…\\registers.[5] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (410): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[62]", + id: Wellen((199)), + ), + color: None, + background_color: None, + display_name: "[62] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (383): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[35]", + id: Wellen((172)), + ), + color: None, + background_color: None, + display_name: "[35] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (300): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theRegisters", + "\\registers", + ], + id: Wellen((17)), + ), + name: "[17]", + id: Wellen((433)), + ), + color: None, + background_color: None, + display_name: "…\\registers.[17] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (332): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + ], + id: Wellen((3)), + ), + name: "Rs2", + id: Wellen((15)), + ), + color: None, + background_color: None, + display_name: "Rs2 [4:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (413): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[65]", + id: Wellen((202)), + ), + color: None, + background_color: None, + display_name: "[65] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (496): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2025]", + id: Wellen((394)), + ), + color: None, + background_color: None, + display_name: "[2025] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (299): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theRegisters", + "\\registers", + ], + id: Wellen((17)), + ), + name: "[16]", + id: Wellen((432)), + ), + color: None, + background_color: None, + display_name: "…\\registers.[16] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (263): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2029]", + id: Wellen((398)), + ), + color: None, + background_color: None, + display_name: "[2029] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (435): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[87]", + id: Wellen((224)), + ), + color: None, + background_color: None, + display_name: "[87] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (328): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + ], + id: Wellen((3)), + ), + name: "JumpOrBranch", + id: Wellen((23)), + ), + color: None, + background_color: None, + display_name: "JumpOrBranch", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (417): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[69]", + id: Wellen((206)), + ), + color: None, + background_color: None, + display_name: "[69] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (348): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2]", + id: Wellen((139)), + ), + color: None, + background_color: None, + display_name: "…\\RAM.[2] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (269): Variable(( + variable_ref: ( + path: ( + strs: [ + "cpu_tb", + "u_cpu", + "theMem", + "\\RAM", + ], + id: Wellen((16)), + ), + name: "[2035]", + id: Wellen((404)), + ), + color: None, + background_color: None, + display_name: "[2035] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + }, + display_item_ref_counter: 496, + viewports: [ + ( + curr_left: (-0.003008531972765737), + curr_right: (0.9969914680272342), + target_left: (0.0), + target_right: (1.0), + move_start_left: (0.0), + move_start_right: (1.0), + move_duration: None, + move_strategy: Instant, + ), + ], + cursor: Some((1, [ + 235749, + ])), + markers: {}, + focused_item: Some((25)), + focused_transaction: (None, None), + default_variable_name_type: Unique, + scroll_offset: 0.0, + display_variable_indices: true, + graphics: {}, + )), + drag_started: false, + drag_source_idx: None, + drag_target_idx: Some(( + before: (149), + level: 0, + )), + previous_waves: None, + count: None, + blacklisted_translators: [], + show_about: false, + show_keys: false, + show_gestures: false, + show_quick_start: false, + show_license: false, + show_performance: false, + show_logs: false, + show_cursor_window: false, + wanted_timeunit: NanoSeconds, + time_string_format: None, + show_url_entry: false, + variable_name_filter_focused: false, + variable_filter: ( + name_filter_type: Contain, + name_filter_str: "", + name_filter_case_insensitive: true, + include_inputs: true, + include_outputs: true, + include_inouts: true, + include_others: true, + group_by_direction: false, + ), + sidepanel_width: Some(300.0), + ui_zoom_factor: None, +) \ No newline at end of file diff --git a/riscv_rtl/hw/dv/wave_configs/verilator_wave.surf.ron b/riscv_rtl/hw/dv/wave_configs/verilator_wave.surf.ron new file mode 100644 index 0000000..e8d907d --- /dev/null +++ b/riscv_rtl/hw/dv/wave_configs/verilator_wave.surf.ron @@ -0,0 +1,6943 @@ +( + show_hierarchy: None, + show_menu: None, + show_ticks: None, + show_toolbar: None, + show_tooltip: None, + show_scope_tooltip: Some(true), + show_default_timeline: None, + show_overview: None, + show_statusbar: None, + align_names_right: Some(true), + show_variable_indices: None, + show_variable_direction: None, + show_empty_scopes: Some(false), + show_parameters_in_scopes: None, + highlight_focused: Some(true), + fill_high_values: Some(true), + primary_button_drag_behavior: None, + arrow_key_bindings: None, + clock_highlight_type: None, + hierarchy_style: Some(Separate), + autoload_sibling_state_files: None, + autoreload_files: None, + waves: Some(( + source: File("wavedump.fst"), + format: Fst, + active_scope: Some(WaveScope(( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ))), + items_tree: ( + items: [ + ( + item_ref: (319), + level: 0, + unfolded: true, + selected: false, + ), + ( + item_ref: (320), + level: 0, + unfolded: true, + selected: false, + ), + ( + item_ref: (321), + level: 0, + unfolded: true, + selected: false, + ), + ( + item_ref: (335), + level: 0, + unfolded: true, + selected: false, + ), + ( + item_ref: (334), + level: 0, + unfolded: true, + selected: false, + ), + ( + item_ref: (322), + level: 0, + unfolded: true, + selected: false, + ), + ( + item_ref: (324), + level: 0, + unfolded: true, + selected: false, + ), + ( + item_ref: (323), + level: 0, + unfolded: true, + selected: false, + ), + ( + item_ref: (326), + level: 0, + unfolded: true, + selected: false, + ), + ( + item_ref: (325), + level: 0, + unfolded: true, + selected: false, + ), + ( + item_ref: (333), + level: 0, + unfolded: true, + selected: false, + ), + ( + item_ref: (327), + level: 0, + unfolded: true, + selected: false, + ), + ( + item_ref: (328), + level: 0, + unfolded: true, + selected: false, + ), + ( + item_ref: (331), + level: 0, + unfolded: true, + selected: false, + ), + ( + item_ref: (329), + level: 0, + unfolded: true, + selected: false, + ), + ( + item_ref: (330), + level: 0, + unfolded: true, + selected: false, + ), + ( + item_ref: (332), + level: 0, + unfolded: true, + selected: false, + ), + ( + item_ref: (337), + level: 0, + unfolded: true, + selected: false, + ), + ( + item_ref: (336), + level: 0, + unfolded: true, + selected: false, + ), + ( + item_ref: (341), + level: 0, + unfolded: true, + selected: false, + ), + ( + item_ref: (342), + level: 0, + unfolded: true, + selected: false, + ), + ( + item_ref: (340), + level: 0, + unfolded: true, + selected: false, + ), + ( + item_ref: (339), + level: 0, + unfolded: true, + selected: false, + ), + ( + item_ref: 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Wellen((2149)), + ), + color: None, + background_color: None, + display_name: "[2034] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (534): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2033]", + id: Wellen((2148)), + ), + color: None, + background_color: None, + display_name: "[2033] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (402): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[26]", + id: Wellen((141)), + ), + color: None, + background_color: None, + display_name: "…RAM.[26] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (452): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[75]", + id: Wellen((190)), + ), + color: None, + background_color: None, + display_name: "[75] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (389): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[13]", + id: Wellen((128)), + ), + color: None, + background_color: None, + display_name: "…RAM.[13] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (322): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + ], + id: Wellen((4)), + ), + name: "CurrentPC", + id: Wellen((11)), + ), + color: None, + background_color: None, + display_name: "CurrentPC [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (370): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theRegisters", + "registers", + ], + id: Wellen((11)), + ), + name: "[26]", + id: Wellen((2204)), + ), + color: None, + background_color: None, + display_name: "…registers.[26] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (529): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2028]", + id: Wellen((2143)), + ), + color: None, + background_color: None, + display_name: "[2028] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (484): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[1984]", + id: Wellen((2099)), + ), + color: None, + background_color: None, + display_name: "[1984] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (363): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theRegisters", + "registers", + ], + id: Wellen((11)), + ), + name: "[19]", + id: Wellen((2197)), + ), + color: None, + background_color: None, + display_name: "…registers.[19] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (434): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[57]", + id: Wellen((172)), + ), + color: None, + background_color: None, + display_name: "[57] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (398): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[22]", + id: Wellen((137)), + ), + color: None, + background_color: None, + display_name: "…RAM.[22] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (397): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[21]", + id: Wellen((136)), + ), + color: None, + background_color: None, + display_name: "…RAM.[21] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (547): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2046]", + id: Wellen((2161)), + ), + color: None, + background_color: None, + display_name: "[2046] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (532): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2031]", + id: Wellen((2146)), + ), + color: None, + background_color: None, + display_name: "[2031] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (476): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[1031]", + id: Wellen((1146)), + ), + color: None, + background_color: None, + display_name: "[1031] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (393): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[17]", + id: Wellen((132)), + ), + color: None, + background_color: None, + display_name: "…RAM.[17] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (347): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theRegisters", + "registers", + ], + id: Wellen((11)), + ), + name: "[3]", + id: Wellen((2181)), + ), + color: None, + background_color: None, + display_name: "…registers.[3] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (413): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[37]", + id: Wellen((152)), + ), + color: None, + background_color: None, + display_name: "[37] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (541): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2040]", + id: Wellen((2155)), + ), + color: None, + background_color: None, + display_name: "[2040] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (546): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2045]", + id: Wellen((2160)), + ), + color: None, + background_color: None, + display_name: "[2045] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (387): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[11]", + id: Wellen((126)), + ), + color: None, + background_color: None, + display_name: "…RAM.[11] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (456): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[79]", + id: Wellen((194)), + ), + color: None, + background_color: None, + display_name: "[79] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (533): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2032]", + id: Wellen((2147)), + ), + color: None, + background_color: None, + display_name: "[2032] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (500): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[1999]", + id: Wellen((2114)), + ), + color: None, + background_color: None, + display_name: "[1999] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (334): Divider(( + color: None, + background_color: None, + name: None, + )), + (514): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2013]", + id: Wellen((2128)), + ), + color: None, + background_color: None, + display_name: "[2013] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (401): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[25]", + id: Wellen((140)), + ), + color: None, + background_color: None, + display_name: "…RAM.[25] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (490): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[1990]", + id: Wellen((2105)), + ), + color: None, + background_color: None, + display_name: "[1990] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (374): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theRegisters", + "registers", + ], + id: Wellen((11)), + ), + name: "[30]", + id: Wellen((2208)), + ), + color: None, + background_color: None, + display_name: "…registers.[30] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (329): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + ], + id: Wellen((4)), + ), + name: "RRs1", + id: Wellen((24)), + ), + color: None, + background_color: None, + display_name: "RRs1 [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (351): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theRegisters", + "registers", + ], + id: Wellen((11)), + ), + name: "[7]", + id: Wellen((2185)), + ), + color: None, + background_color: None, + display_name: "…registers.[7] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (511): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2010]", + id: Wellen((2125)), + ), + color: None, + background_color: None, + display_name: "[2010] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (478): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[1033]", + id: Wellen((1148)), + ), + color: None, + background_color: None, + display_name: "[1033] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (358): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theRegisters", + "registers", + ], + id: Wellen((11)), + ), + name: "[14]", + id: Wellen((2192)), + ), + color: None, + background_color: None, + display_name: "…registers.[14] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (475): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[1030]", + id: Wellen((1145)), + ), + color: None, + background_color: None, + display_name: "[1030] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (411): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[35]", + id: Wellen((150)), + ), + color: None, + background_color: None, + display_name: "[35] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (501): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2000]", + id: Wellen((2115)), + ), + color: None, + background_color: None, + display_name: "[2000] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (378): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2]", + id: Wellen((117)), + ), + color: None, + background_color: None, + display_name: "…RAM.[2] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (441): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[64]", + id: Wellen((179)), + ), + color: None, + background_color: None, + display_name: "[64] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (436): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[59]", + id: Wellen((174)), + ), + color: None, + background_color: None, + display_name: "[59] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (404): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[28]", + id: Wellen((143)), + ), + color: None, + background_color: None, + display_name: "…RAM.[28] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (471): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[1026]", + id: Wellen((1141)), + ), + color: None, + background_color: None, + display_name: "[1026] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (423): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[47]", + id: Wellen((162)), + ), + color: None, + background_color: None, + display_name: "[47] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (510): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2009]", + id: Wellen((2124)), + ), + color: None, + background_color: None, + display_name: "[2009] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (325): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + ], + id: Wellen((4)), + ), + name: "JumpOrBranch", + id: Wellen((13)), + ), + color: None, + background_color: None, + display_name: "JumpOrBranch", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (349): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theRegisters", + "registers", + ], + id: Wellen((11)), + ), + name: "[5]", + id: Wellen((2183)), + ), + color: None, + background_color: None, + display_name: "…registers.[5] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (319): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + ], + id: Wellen((4)), + ), + name: "clk_25mhz", + id: Wellen((7)), + ), + color: None, + background_color: None, + display_name: "clk_25mhz", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (395): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[19]", + id: Wellen((134)), + ), + color: None, + background_color: None, + display_name: "…RAM.[19] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (443): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[66]", + id: Wellen((181)), + ), + color: None, + background_color: None, + display_name: "[66] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (508): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2007]", + id: Wellen((2122)), + ), + color: None, + background_color: None, + display_name: "[2007] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (415): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[39]", + id: Wellen((154)), + ), + color: None, + background_color: None, + display_name: "[39] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (525): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2024]", + id: Wellen((2139)), + ), + color: None, + background_color: None, + display_name: "[2024] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (343): Divider(( + color: None, + background_color: None, + name: None, + )), + (439): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[62]", + id: Wellen((177)), + ), + color: None, + background_color: None, + display_name: "[62] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (531): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2030]", + id: Wellen((2145)), + ), + color: None, + background_color: None, + display_name: "[2030] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (523): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2022]", + id: Wellen((2137)), + ), + color: None, + background_color: None, + display_name: "[2022] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (444): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[67]", + id: Wellen((182)), + ), + color: None, + background_color: None, + display_name: "[67] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (458): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[81]", + id: Wellen((196)), + ), + color: None, + background_color: None, + display_name: "[81] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (390): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[14]", + id: Wellen((129)), + ), + color: None, + background_color: None, + display_name: "…RAM.[14] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (543): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2042]", + id: Wellen((2157)), + ), + color: None, + background_color: None, + display_name: "[2042] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (372): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theRegisters", + "registers", + ], + id: Wellen((11)), + ), + name: "[28]", + id: Wellen((2206)), + ), + color: None, + background_color: None, + display_name: "…registers.[28] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (528): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2027]", + id: Wellen((2142)), + ), + color: None, + background_color: None, + display_name: "[2027] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (422): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[46]", + id: Wellen((161)), + ), + color: None, + background_color: None, + display_name: "[46] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (459): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[82]", + id: Wellen((197)), + ), + color: None, + background_color: None, + display_name: "[82] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (477): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[1032]", + id: Wellen((1147)), + ), + color: None, + background_color: None, + display_name: "[1032] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (371): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theRegisters", + "registers", + ], + id: Wellen((11)), + ), + name: "[27]", + id: Wellen((2205)), + ), + color: None, + background_color: None, + display_name: "…registers.[27] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (352): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theRegisters", + "registers", + ], + id: Wellen((11)), + ), + name: "[8]", + id: Wellen((2186)), + ), + color: None, + background_color: None, + display_name: "…registers.[8] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (342): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + ], + id: Wellen((4)), + ), + name: "DAddr", + id: Wellen((15)), + ), + color: None, + background_color: None, + display_name: "DAddr [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (282): Group(( + name: "RegFile", + color: None, + background_color: None, + content: [], + is_open: false, + )), + (482): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[1982]", + id: Wellen((2097)), + ), + color: None, + background_color: None, + display_name: "[1982] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (385): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[9]", + id: Wellen((124)), + ), + color: None, + background_color: None, + display_name: "…RAM.[9] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (522): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2021]", + id: Wellen((2136)), + ), + color: None, + background_color: None, + display_name: "[2021] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (336): Divider(( + color: None, + background_color: None, + name: None, + )), + (421): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[45]", + id: Wellen((160)), + ), + color: None, + background_color: None, + display_name: "[45] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (382): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[6]", + id: Wellen((121)), + ), + color: None, + background_color: None, + display_name: "…RAM.[6] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (470): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[1025]", + id: Wellen((1140)), + ), + color: None, + background_color: None, + display_name: "[1025] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (380): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[4]", + id: Wellen((119)), + ), + color: None, + background_color: None, + display_name: "…RAM.[4] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (450): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[73]", + id: Wellen((188)), + ), + color: None, + background_color: None, + display_name: "[73] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (365): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theRegisters", + "registers", + ], + id: Wellen((11)), + ), + name: "[21]", + id: Wellen((2199)), + ), + color: None, + background_color: None, + display_name: "…registers.[21] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (350): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theRegisters", + "registers", + ], + id: Wellen((11)), + ), + name: "[6]", + id: Wellen((2184)), + ), + color: None, + background_color: None, + display_name: "…registers.[6] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (494): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[1994]", + id: Wellen((2109)), + ), + color: None, + background_color: None, + display_name: "[1994] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (426): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[50]", + id: Wellen((165)), + ), + color: None, + background_color: None, + display_name: "[50] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (469): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[1024]", + id: Wellen((1139)), + ), + color: None, + background_color: None, + display_name: "[1024] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (424): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[48]", + id: Wellen((163)), + ), + color: None, + background_color: None, + display_name: "[48] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (335): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + ], + id: Wellen((4)), + ), + name: "Illegal", + id: Wellen((28)), + ), + color: None, + background_color: None, + display_name: "Illegal", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (331): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + ], + id: Wellen((4)), + ), + name: "Rd", + id: Wellen((23)), + ), + color: None, + background_color: None, + display_name: "Rd [4:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (361): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theRegisters", + "registers", + ], + id: Wellen((11)), + ), + name: "[17]", + id: Wellen((2195)), + ), + color: None, + background_color: None, + display_name: "…registers.[17] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (507): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2006]", + id: Wellen((2121)), + ), + color: None, + background_color: None, + display_name: "[2006] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (462): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[85]", + id: Wellen((200)), + ), + color: None, + background_color: None, + display_name: "[85] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (509): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2008]", + id: Wellen((2123)), + ), + color: None, + background_color: None, + display_name: "[2008] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (538): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2037]", + id: Wellen((2152)), + ), + color: None, + background_color: None, + display_name: "[2037] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (432): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[55]", + id: Wellen((170)), + ), + color: None, + background_color: None, + display_name: "[55] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (400): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[24]", + id: Wellen((139)), + ), + color: None, + background_color: None, + display_name: "…RAM.[24] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (460): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[83]", + id: Wellen((198)), + ), + color: None, + background_color: None, + display_name: "[83] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (414): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[38]", + id: Wellen((153)), + ), + color: None, + background_color: None, + display_name: "[38] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (392): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[16]", + id: Wellen((131)), + ), + color: None, + background_color: None, + display_name: "…RAM.[16] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (483): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[1983]", + id: Wellen((2098)), + ), + color: None, + background_color: None, + display_name: "[1983] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (405): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[29]", + id: Wellen((144)), + ), + color: None, + background_color: None, + display_name: "…RAM.[29] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (362): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theRegisters", + "registers", + ], + id: Wellen((11)), + ), + name: "[18]", + id: Wellen((2196)), + ), + color: None, + background_color: None, + display_name: "…registers.[18] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (492): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[1992]", + id: Wellen((2107)), + ), + color: None, + background_color: None, + display_name: "[1992] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (357): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theRegisters", + "registers", + ], + id: Wellen((11)), + ), + name: "[13]", + id: Wellen((2191)), + ), + color: None, + background_color: None, + display_name: "…registers.[13] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (442): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[65]", + id: Wellen((180)), + ), + color: None, + background_color: None, + display_name: "[65] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (403): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[27]", + id: Wellen((142)), + ), + color: None, + background_color: None, + display_name: "…RAM.[27] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (428): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[51]", + id: Wellen((166)), + ), + color: None, + background_color: None, + display_name: "[51] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (408): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[32]", + id: Wellen((147)), + ), + color: None, + background_color: None, + display_name: "[32] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (518): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + 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height_scaling_factor: None, + )), + (455): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[78]", + id: Wellen((193)), + ), + color: None, + background_color: None, + display_name: "[78] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (355): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theRegisters", + "registers", + ], + id: Wellen((11)), + ), + name: "[11]", + id: Wellen((2189)), + ), + color: None, + background_color: None, + display_name: "…registers.[11] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (473): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[1028]", + id: Wellen((1143)), + ), + color: None, + background_color: None, + display_name: "[1028] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (412): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[36]", + id: Wellen((151)), + ), + color: None, + background_color: None, + display_name: "[36] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (386): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[10]", + id: Wellen((125)), + ), + color: None, + background_color: None, + display_name: "…RAM.[10] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (542): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2041]", + id: Wellen((2156)), + ), + color: None, + background_color: None, + display_name: "[2041] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (425): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[49]", + id: Wellen((164)), + ), + color: None, + background_color: None, + display_name: "[49] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (524): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2023]", + id: Wellen((2138)), + ), + color: None, + background_color: None, + display_name: "[2023] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (438): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[61]", + id: Wellen((176)), + ), + color: None, + background_color: None, + display_name: "[61] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (327): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + ], + id: Wellen((4)), + ), + name: "Rs1", + id: Wellen((21)), + ), + color: None, + background_color: None, + display_name: "Rs1 [4:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (445): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[68]", + id: Wellen((183)), + ), + color: None, + background_color: None, + display_name: "[68] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (464): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[87]", + id: Wellen((202)), + ), + color: None, + background_color: None, + display_name: "[87] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (504): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2003]", + id: Wellen((2118)), + ), + color: None, + background_color: None, + display_name: "[2003] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (466): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[89]", + id: Wellen((204)), + ), + color: None, + background_color: None, + display_name: "[89] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (512): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2011]", + id: Wellen((2126)), + ), + color: None, + background_color: None, + display_name: "[2011] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (468): Group(( + name: "InstrMem", + color: None, + background_color: None, + content: [], + is_open: false, + )), + (519): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2018]", + id: Wellen((2133)), + ), + color: None, + background_color: None, + display_name: "[2018] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (505): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2004]", + id: Wellen((2119)), + ), + color: None, + background_color: None, + display_name: "[2004] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (433): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[56]", + id: Wellen((171)), + ), + color: None, + background_color: None, + display_name: "[56] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (515): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2014]", + id: Wellen((2129)), + ), + color: None, + background_color: None, + display_name: "[2014] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (487): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[1987]", + id: Wellen((2102)), + ), + color: None, + background_color: None, + display_name: "[1987] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (516): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2015]", + id: Wellen((2130)), + ), + color: None, + background_color: None, + display_name: "[2015] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (536): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2035]", + id: Wellen((2150)), + ), + color: None, + background_color: None, + display_name: "[2035] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (488): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[1988]", + id: Wellen((2103)), + ), + color: None, + background_color: None, + display_name: "[1988] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (356): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theRegisters", + "registers", + ], + id: Wellen((11)), + ), + name: "[12]", + id: Wellen((2190)), + ), + color: None, + background_color: None, + display_name: "…registers.[12] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (461): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[84]", + id: Wellen((199)), + ), + color: None, + background_color: None, + display_name: "[84] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (437): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[60]", + id: Wellen((175)), + ), + color: None, + background_color: None, + display_name: "[60] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (320): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + ], + id: Wellen((4)), + ), + name: "clk12p5", + id: Wellen((9)), + ), + color: None, + background_color: None, + display_name: "clk12p5", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (348): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theRegisters", + "registers", + ], + id: Wellen((11)), + ), + name: "[4]", + id: Wellen((2182)), + ), + color: None, + background_color: None, + display_name: "…registers.[4] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (326): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + ], + id: Wellen((4)), + ), + name: "JumpOrBranchPC", + id: Wellen((12)), + ), + color: None, + background_color: None, + display_name: "JumpOrBranchPC [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (530): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2029]", + id: Wellen((2144)), + ), + color: None, + background_color: None, + display_name: "[2029] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (521): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2020]", + id: Wellen((2135)), + ), + color: None, + background_color: None, + display_name: "[2020] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (527): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2026]", + id: Wellen((2141)), + ), + color: None, + background_color: None, + display_name: "[2026] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (324): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + ], + id: Wellen((4)), + ), + name: "Instruction", + id: Wellen((18)), + ), + color: None, + background_color: None, + display_name: "Instruction [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (427): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[51]", + id: Wellen((166)), + ), + color: None, + background_color: None, + display_name: "[51] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (489): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[1989]", + id: Wellen((2104)), + ), + color: None, + background_color: None, + display_name: "[1989] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (373): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theRegisters", + "registers", + ], + id: Wellen((11)), + ), + name: "[29]", + id: Wellen((2207)), + ), + color: None, + background_color: None, + display_name: "…registers.[29] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (416): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[40]", + id: Wellen((155)), + ), + color: None, + background_color: None, + display_name: "[40] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (354): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theRegisters", + "registers", + ], + id: Wellen((11)), + ), + name: "[10]", + id: Wellen((2188)), + ), + color: None, + background_color: None, + display_name: "…registers.[10] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (360): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theRegisters", + "registers", + ], + id: Wellen((11)), + ), + name: "[16]", + id: Wellen((2194)), + ), + color: None, + background_color: None, + display_name: "…registers.[16] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (406): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[30]", + id: Wellen((145)), + ), + color: None, + background_color: None, + display_name: "…RAM.[30] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (463): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[86]", + id: Wellen((201)), + ), + color: None, + background_color: None, + display_name: "[86] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (431): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[54]", + id: Wellen((169)), + ), + color: None, + background_color: None, + display_name: "[54] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (446): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[69]", + id: Wellen((184)), + ), + color: None, + background_color: None, + display_name: "[69] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (430): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[53]", + id: Wellen((168)), + ), + color: None, + background_color: None, + display_name: "[53] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (491): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[1991]", + id: Wellen((2106)), + ), + color: None, + background_color: None, + display_name: "[1991] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (388): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[12]", + id: Wellen((127)), + ), + color: None, + background_color: None, + display_name: "…RAM.[12] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (457): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[80]", + id: Wellen((195)), + ), + color: None, + background_color: None, + display_name: "[80] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (399): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[23]", + id: Wellen((138)), + ), + color: None, + background_color: None, + display_name: "…RAM.[23] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (449): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[72]", + id: Wellen((187)), + ), + color: None, + background_color: None, + display_name: "[72] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (323): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + ], + id: Wellen((4)), + ), + name: "NextPC", + id: Wellen((14)), + ), + color: None, + background_color: None, + display_name: "NextPC [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (537): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2036]", + id: Wellen((2151)), + ), + color: None, + background_color: None, + display_name: "[2036] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (503): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2002]", + id: Wellen((2117)), + ), + color: None, + background_color: None, + display_name: "[2002] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (328): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + ], + id: Wellen((4)), + ), + name: "Rs2", + id: Wellen((22)), + ), + color: None, + background_color: None, + display_name: "Rs2 [4:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (366): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theRegisters", + "registers", + ], + id: Wellen((11)), + ), + name: "[22]", + id: Wellen((2200)), + ), + color: None, + background_color: None, + display_name: "…registers.[22] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (467): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[90]", + id: Wellen((205)), + ), + color: None, + background_color: None, + display_name: "[90] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (339): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + ], + id: Wellen((4)), + ), + name: "WData", + id: Wellen((16)), + ), + color: None, + background_color: None, + display_name: "WData [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (353): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theRegisters", + "registers", + ], + id: Wellen((11)), + ), + name: "[9]", + id: Wellen((2187)), + ), + color: None, + background_color: None, + display_name: "…registers.[9] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (321): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + ], + id: Wellen((4)), + ), + name: "reset", + id: Wellen((10)), + ), + color: None, + background_color: None, + display_name: "reset", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (417): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[41]", + id: Wellen((156)), + ), + color: None, + background_color: None, + display_name: "[41] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (540): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2039]", + id: Wellen((2154)), + ), + color: None, + background_color: None, + display_name: "[2039] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (526): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2025]", + id: Wellen((2140)), + ), + color: None, + background_color: None, + display_name: "[2025] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (419): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[43]", + id: Wellen((158)), + ), + color: None, + background_color: None, + display_name: "[43] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (333): Divider(( + color: None, + background_color: None, + name: None, + )), + (447): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[70]", + id: Wellen((185)), + ), + color: None, + background_color: None, + display_name: "[70] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (520): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2019]", + id: Wellen((2134)), + ), + color: None, + background_color: None, + display_name: "[2019] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (465): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[88]", + id: Wellen((203)), + ), + color: None, + background_color: None, + display_name: "[88] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (548): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2047]", + id: Wellen((2162)), + ), + color: None, + background_color: None, + display_name: "[2047] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (383): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[7]", + id: Wellen((122)), + ), + color: None, + background_color: None, + display_name: "…RAM.[7] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (364): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theRegisters", + "registers", + ], + id: Wellen((11)), + ), + name: "[20]", + id: Wellen((2198)), + ), + color: None, + background_color: None, + display_name: "…registers.[20] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (367): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theRegisters", + "registers", + ], + id: Wellen((11)), + ), + name: "[23]", + id: Wellen((2201)), + ), + color: None, + background_color: None, + display_name: "…registers.[23] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (495): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[1995]", + id: Wellen((2110)), + ), + color: None, + background_color: None, + display_name: "[1995] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (381): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[5]", + id: Wellen((120)), + ), + color: None, + background_color: None, + display_name: "…RAM.[5] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (474): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[1029]", + id: Wellen((1144)), + ), + color: None, + background_color: None, + display_name: "[1029] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (340): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + ], + id: Wellen((4)), + ), + name: "RData", + id: Wellen((17)), + ), + color: None, + background_color: None, + display_name: "RData [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (480): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[1980]", + id: Wellen((2095)), + ), + color: None, + background_color: None, + display_name: "[1980] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (341): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + ], + id: Wellen((4)), + ), + name: "DWidth", + id: Wellen((20)), + ), + color: None, + background_color: None, + display_name: "DWidth [1:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (330): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + ], + id: Wellen((4)), + ), + name: "RRs2", + id: Wellen((25)), + ), + color: None, + background_color: None, + display_name: "RRs2 [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (472): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[1027]", + id: Wellen((1142)), + ), + color: None, + background_color: None, + display_name: "[1027] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (479): Group(( + name: "DataMem", + color: None, + background_color: None, + content: [], + is_open: false, + )), + (448): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[71]", + id: Wellen((186)), + ), + color: None, + background_color: None, + display_name: "[71] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (545): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2044]", + id: Wellen((2159)), + ), + color: None, + background_color: None, + display_name: "[2044] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (517): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2016]", + id: Wellen((2131)), + ), + color: None, + background_color: None, + display_name: "[2016] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (502): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2001]", + id: Wellen((2116)), + ), + color: None, + background_color: None, + display_name: "[2001] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (485): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[1985]", + id: Wellen((2100)), + ), + color: None, + background_color: None, + display_name: "[1985] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (486): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[1986]", + id: Wellen((2101)), + ), + color: None, + background_color: None, + display_name: "[1986] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (368): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theRegisters", + "registers", + ], + id: Wellen((11)), + ), + name: "[24]", + id: Wellen((2202)), + ), + color: None, + background_color: None, + display_name: "…registers.[24] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (379): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[3]", + id: Wellen((118)), + ), + color: None, + background_color: None, + display_name: "…RAM.[3] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (498): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[1997]", + id: Wellen((2112)), + ), + color: None, + background_color: None, + display_name: "[1997] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (481): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[1981]", + id: Wellen((2096)), + ), + color: None, + background_color: None, + display_name: "[1981] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (369): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theRegisters", + "registers", + ], + id: Wellen((11)), + ), + name: "[25]", + id: Wellen((2203)), + ), + color: None, + background_color: None, + display_name: "…registers.[25] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (454): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[77]", + id: Wellen((192)), + ), + color: None, + background_color: None, + display_name: "[77] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (345): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theRegisters", + "registers", + ], + id: Wellen((11)), + ), + name: "[1]", + id: Wellen((2179)), + ), + color: None, + background_color: None, + display_name: "…registers.[1] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (409): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[33]", + id: Wellen((148)), + ), + color: None, + background_color: None, + display_name: "[33] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (506): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[2005]", + id: Wellen((2120)), + ), + color: None, + background_color: None, + display_name: "[2005] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (493): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[1993]", + id: Wellen((2108)), + ), + color: None, + background_color: None, + display_name: "[1993] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (384): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[8]", + id: Wellen((123)), + ), + color: None, + background_color: None, + display_name: "…RAM.[8] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (332): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + ], + id: Wellen((4)), + ), + name: "WRd", + id: Wellen((26)), + ), + color: None, + background_color: None, + display_name: "WRd [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (429): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[52]", + id: Wellen((167)), + ), + color: None, + background_color: None, + display_name: "[52] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (337): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + ], + id: Wellen((4)), + ), + name: "WrReg", + id: Wellen((27)), + ), + color: None, + background_color: None, + display_name: "WrReg", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (440): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[63]", + id: Wellen((178)), + ), + color: None, + background_color: None, + display_name: "[63] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + (451): Variable(( + variable_ref: ( + path: ( + strs: [ + "TOP", + "cpu_harness", + "u_cpu", + "theMem", + "RAM", + ], + id: Wellen((8)), + ), + name: "[74]", + id: Wellen((189)), + ), + color: None, + background_color: None, + display_name: "[74] [31:0]", + display_name_type: Unique, + manual_name: None, + format: None, + field_formats: [], + height_scaling_factor: None, + )), + }, + display_item_ref_counter: 549, + viewports: [ + ( + curr_left: (-0.0004669137448076408), + curr_right: (0.9995330862551929), + target_left: (0.0), + target_right: (1.0), + move_start_left: (0.0), + move_start_right: (1.0), + move_duration: None, + move_strategy: Instant, + ), + ], + cursor: Some((1, [ + 721, + ])), + markers: {}, + focused_item: Some((4)), + focused_transaction: (None, None), + default_variable_name_type: Unique, + scroll_offset: 0.0, + display_variable_indices: true, + graphics: {}, + )), + drag_started: false, + drag_source_idx: None, + drag_target_idx: None, + previous_waves: None, + count: None, + blacklisted_translators: [], + show_about: false, + show_keys: false, + show_gestures: false, + show_quick_start: false, + show_license: false, + show_performance: false, + show_logs: false, + show_cursor_window: false, + wanted_timeunit: NanoSeconds, + time_string_format: None, + show_url_entry: false, + variable_name_filter_focused: false, + variable_filter: ( + name_filter_type: Contain, + name_filter_str: "", + name_filter_case_insensitive: true, + include_inputs: true, + include_outputs: true, + include_inouts: true, + include_others: true, + group_by_direction: false, + ), + sidepanel_width: Some(300.0), + ui_zoom_factor: None, +) diff --git a/riscv_rtl/hw/file_lists/rtl_flist.f b/riscv_rtl/hw/file_lists/rtl_flist.f new file mode 100644 index 0000000..d03ad7a --- /dev/null +++ b/riscv_rtl/hw/file_lists/rtl_flist.f @@ -0,0 +1,19 @@ +// ********************************************************************************************* +// Project Version : v1.0 +// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog +// ----- +// Copyright (c) : 2025 Fraunhofer IIS, Department IDS +// Created : 12.Aug.2025 by Marcus Bednara +// Last Modified : 01.Nov.2025 by Hussein Elzomor +// ------ +// Notes : All ${}-variables must be provided by shell or Makefile {using export} +// ********************************************************************************************* + + + +${PRJ_ROOT}/hw/rtl/pc.sv +${PRJ_ROOT}/hw/rtl/reg_file.sv +${PRJ_ROOT}/hw/rtl/alu.sv +${PRJ_ROOT}/hw/rtl/main_mem.sv +${PRJ_ROOT}/hw/rtl/decoder.sv +${PRJ_ROOT}/hw/rtl/cpu.sv diff --git a/riscv_rtl/hw/file_lists/tb_flist.f b/riscv_rtl/hw/file_lists/tb_flist.f new file mode 100644 index 0000000..b8d9e09 --- /dev/null +++ b/riscv_rtl/hw/file_lists/tb_flist.f @@ -0,0 +1,24 @@ +// ********************************************************************************************* +// Project Version : v1.0 +// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog +// ----- +// Copyright (c) : 2025 Fraunhofer IIS, Department IDS +// Created : 12.Aug.2025 by Marcus Bednara +// Last Modified : 01.Nov.2025 by Hussein Elzomor +// ------ +// Notes : All ${}-variables must be provided by shell or Makefile {using export} +// ********************************************************************************************* + + + +// Used with verilator +${PRJ_ROOT}/hw/dv/verilator/rtl/decoder_harness.sv +${PRJ_ROOT}/hw/dv/verilator/rtl/cpu_harness.sv + +// Used with other compilers and simulators (eg. Icarus) +// ${PRJ_ROOT}/hw/dv/rtl/pc_tb.sv +// ${PRJ_ROOT}/hw/dv/rtl/reg_file_tb.sv +// ${PRJ_ROOT}/hw/dv/rtl/alu_tb.sv +// ${PRJ_ROOT}/hw/dv/rtl/main_mem_tb.sv +// ${PRJ_ROOT}/hw/dv/rtl/decoder_tb.sv +// ${PRJ_ROOT}/hw/dv/rtl/cpu_tb.sv diff --git a/riscv_rtl/hw/rtl/.MemGen_32_11.sv.swl b/riscv_rtl/hw/rtl/.MemGen_32_11.sv.swl new file mode 100644 index 0000000..12d3999 Binary files /dev/null and b/riscv_rtl/hw/rtl/.MemGen_32_11.sv.swl differ diff --git a/riscv_rtl/hw/rtl/.MemGen_32_11.sv.swm b/riscv_rtl/hw/rtl/.MemGen_32_11.sv.swm new file mode 100644 index 0000000..b720c64 Binary files /dev/null and b/riscv_rtl/hw/rtl/.MemGen_32_11.sv.swm differ diff --git a/riscv_rtl/hw/rtl/.MemGen_32_11.sv.swn b/riscv_rtl/hw/rtl/.MemGen_32_11.sv.swn new file mode 100644 index 0000000..79dd7ac Binary files /dev/null and b/riscv_rtl/hw/rtl/.MemGen_32_11.sv.swn differ diff --git a/riscv_rtl/hw/rtl/.MemGen_32_11.sv.swo b/riscv_rtl/hw/rtl/.MemGen_32_11.sv.swo new file mode 100644 index 0000000..8214e66 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files /dev/null and b/riscv_rtl/hw/rtl/.pc.sv.swp differ diff --git a/riscv_rtl/hw/rtl/MemGen_32_11.sv b/riscv_rtl/hw/rtl/MemGen_32_11.sv new file mode 100755 index 0000000..948ba6c --- /dev/null +++ b/riscv_rtl/hw/rtl/MemGen_32_11.sv @@ -0,0 +1,60 @@ +module MemGen_32_11 #( + parameter data_width = 32, + parameter addr_width = 11, + parameter mem_depth = 2048 +)( + input chip_en, + input clock, + input [addr_width-1:0]addr, + output reg [data_width-1:0]rd_data, + input rd_en, + + input wr_en, + input [data_width-1:0]wr_data +); +// Bank selection: 1 bit selects one of 2 banks + reg [1:0] mem_sel ; + wire [31:0] mem_data_out [1:0]; + +// Address decoder and output multiplexer +always @(*) + begin + if ( chip_en == 1'b1 ) + case (addr[10]) + 1'b0 : begin mem_sel = 2'b01; rd_data = mem_data_out[0]; end + 1'b1 : begin mem_sel = 2'b10; rd_data = mem_data_out[1]; end + endcase + else + begin + mem_sel = 2'b00; + rd_data = 32'h00000000; + end + end + + +genvar i; +// Instantiate 2 banks, each with 2 halves (low + high 16 bits) +generate + for (i = 0; i < 2; i = i + 1) begin + MemGen_16_10 U_lo ( + .chip_en(mem_sel[i]), + .clock(clock), + .addr(addr[9:0]), + .rd_en(rd_en), + .rd_data(mem_data_out[i][15:0]), + .wr_en(wr_en), + .wr_data(wr_data[15:0]) + ); + MemGen_16_10 U_hi ( + .chip_en(mem_sel[i]), + .clock(clock), + .addr(addr[9:0]), + .rd_en(rd_en), + .rd_data(mem_data_out[i][31:16]), + .wr_en(wr_en), + .wr_data(wr_data[31:16]) + ); + end +endgenerate + +endmodule diff --git a/riscv_rtl/hw/rtl/alu.sv b/riscv_rtl/hw/rtl/alu.sv new file mode 100644 index 0000000..798f40e --- /dev/null +++ b/riscv_rtl/hw/rtl/alu.sv @@ -0,0 +1,52 @@ +// ********************************************************************************************* +// Project Version : v1.0 +// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog +// ----- +// Copyright (c) : 2025 Fraunhofer IIS, Department IDS +// Created : 12.Jun.2025 by Lund University [commit 5b1e415] +// Last Modified : 23.Oct.2025 by Bomin Kim [commit 2f8f03d] +// ----- +// HISTORY : Date By Comments +// ----------- --------- ------------------------------------------------- +// 15.Oct.2025 Bomin Kim Refactored ALU logic from decoder into this file +// ********************************************************************************************* + + + +module alu ( + input logic[2:0] aluOp, + input logic aluNegAr, + input logic aluBypass, + input logic[31:0] op1, + input logic[31:0] op2, + output logic[31:0] result, + output logic eqFlag +); + + // Local parameters; list of aluOp + localparam logic[2:0] f3add = 3'b000; + localparam logic[2:0] f3sl = 3'b001; + localparam logic[2:0] f3slt = 3'b010; + localparam logic[2:0] f3sltU = 3'b011; + localparam logic[2:0] f3xor = 3'b100; + localparam logic[2:0] f3sr = 3'b101; + localparam logic[2:0] f3or = 3'b110; + localparam logic[2:0] f3and = 3'b111; + + // ALU logic + always_comb begin : ALU + eqFlag = op1 == op2; + if (aluBypass) result = op1; + else case(aluOp) + f3add: result = aluNegAr ? op1 - op2 : op1 + op2; + f3sl: result = op1 << op2[4:0]; + f3slt: result = {31'b0, $signed(op1) < $signed(op2)}; + f3sltU: result = {31'b0, $unsigned(op1) < $unsigned(op2)}; + f3xor: result = op1 ^ op2; + f3sr: result = aluNegAr ? $signed(op1) >>> op2[4:0] : $signed(op1) >> op2[4:0]; + f3or: result = op1 | op2; + f3and: result = op1 & op2; + endcase + end + +endmodule diff --git a/riscv_rtl/hw/rtl/cpu.sv b/riscv_rtl/hw/rtl/cpu.sv new file mode 100644 index 0000000..610dccb --- /dev/null +++ b/riscv_rtl/hw/rtl/cpu.sv @@ -0,0 +1,135 @@ +// ********************************************************************************************* +// Project Version : v1.0 +// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog +// ----- +// Copyright (c) : 2025 Fraunhofer IIS, Department IDS +// Created : 12.Jun.2025 by Lund University [commit 5b1e415] +// Last Modified : 23.Oct.2025 by Hussein Elzomor [commit 2f8f03d] +// ----- +// HISTORY : Date By Comments +// ----------- --------- ------------------------------------------------- +// 15.Oct.2025 H.Elzomor Renamed file and module from soc to cpu +// 15.Oct.2025 H.Elzomor Added an initial condition for clk_12p5 +// ********************************************************************************************* + + + +module cpu ( + output logic[7:0] led, + input logic[6:0] btn, + input logic clk_25mhz + //input logic scan_en +); + + // Local Signals + // Clock & Reset + logic clk; + // logic clk12p5; + logic reset; + // PC + logic[31:0] CurrentPC; + logic[31:0] JumpOrBranchPC; + logic JumpOrBranch; + logic[31:0] NextPC; + // Memory + logic[31:0] DAddr; + logic[31:0] WData; + logic[31:0] RData; + logic[31:0] Instruction; + logic WrMem; + logic[1:0] DWidth; + // Register File; + logic[4:0] Rs1; + logic[4:0] Rs2; + logic[4:0] Rd; + logic[31:0] RRs1; + logic[31:0] RRs2; + logic[31:0] WRd; + logic WrReg; + // Protection + logic Illegal; + + // Logic + assign clk = clk_25mhz; + // Clock (12.5MHz) + //assign clk = scan_en ? clk_25mhz : clk12p5; + //assign clk = clk12p5; + + // always_ff @(posedge clk_25mhz) begin + // if (reset) + // clk12p5 <= 1'b0; + // else if (!scan_en) + // clk12p5 <= ~clk12p5; + // end + // Reset + assign reset = ~btn[0]; + + // LED + assign led[0] = Illegal; + assign led[1] = WrMem; + assign led[7:2] = NextPC[7:2]; + + // Module Instantiation + // Decoder + decoder theDecoder ( + // PC + .CurrentPC(CurrentPC), + .JumpOrBranchPC(JumpOrBranchPC), + .JumpOrBranch(JumpOrBranch), + // Memory + .DAddr(DAddr), + .WData(WData), + .RData(RData), + .Instruction(Instruction), + .WrMem(WrMem), + .DWidth(DWidth), + // Register File + .Rs1(Rs1), + .Rs2(Rs2), + .Rd(Rd), + .RRs1(RRs1), + .RRs2(RRs2), + .WRd(WRd), + .WrReg(WrReg), + // Protection + .Illegal(Illegal) + ); + + // Register File + reg_file theRegisters ( + .Rs1(Rs1), + .Rs2(Rs2), + .Rd(Rd), + .RRs1(RRs1), + .RRs2(RRs2), + .WRd(WRd), + .WrReg(WrReg), + .reset(reset), + .clk(clk) + ); + + // PC + pc thePC ( + .CurrentPC(CurrentPC), + .JumpOrBranchPC(JumpOrBranchPC), + .JumpOrBranch(JumpOrBranch), + .NextPC(NextPC), + .reset(reset), + .clk(clk) + ); + + // Main Memory + main_mem #( + ) theMem ( + .DAddr(DAddr), + .IAddr(NextPC), + .DWData(WData), + .DRData(RData), + .IRData(Instruction), + .DWE(WrMem), + .DWidth(DWidth), + .reset(reset), + .clk(clk) + ); + +endmodule diff --git a/riscv_rtl/hw/rtl/decoder.sv b/riscv_rtl/hw/rtl/decoder.sv new file mode 100644 index 0000000..cfe750c --- /dev/null +++ b/riscv_rtl/hw/rtl/decoder.sv @@ -0,0 +1,231 @@ +// ********************************************************************************************* +// Project Version : v1.0 +// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog +// ----- +// Copyright (c) : 2025 Fraunhofer IIS, Department IDS +// Created : 12.Jun.2025 by Lund University [commit 5b1e415] +// Last Modified : 23.Oct.2025 by Hussein Elzomor [commit 2f8f03d] +// ----- +// HISTORY : Date By Comments +// ----------- --------- ------------------------------------------------- +// 15.Oct.2025 H.Elzomor Moved PC and ALU logic to their respective files +// 15.Oct.2025 H.Elzomor Absorbed the branching logic into the decoder logic +// ********************************************************************************************* + + + +module decoder ( + // PC + input logic[31:0] CurrentPC, + output logic[31:0] JumpOrBranchPC, + output logic JumpOrBranch, + // Memory + output logic[31:0] DAddr, + output logic[31:0] WData, + input logic[31:0] RData, + input logic[31:0] Instruction, + output logic WrMem, + output logic[1:0] DWidth, + // Register File + output logic[4:0] Rs1, + output logic[4:0] Rs2, + output logic[4:0] Rd, + input logic[31:0] RRs1, + input logic[31:0] RRs2, + output logic[31:0] WRd, + output logic WrReg, + // Protection + output logic Illegal +); + + // Local Parameters + // OpCode: set a local parameter for each operation + localparam logic[6:0] opLd = 7'b0000011; + localparam logic[6:0] opAluImm = 7'b0010011; + localparam logic[6:0] opUpPC = 7'b0010111; + localparam logic[6:0] opSt = 7'b0100011; + localparam logic[6:0] opAlu = 7'b0110011; + localparam logic[6:0] opUpImm = 7'b0110111; + localparam logic[6:0] opBranch = 7'b1100011; + localparam logic[6:0] opJALR = 7'b1100111; + localparam logic[6:0] opJAL = 7'b1101111; + + // Func7: set a local parameter for each function 7 + localparam logic[6:0] f7neg = 7'b0100000; + + // Func3: set a local parameter for each function 3 + // Load/Store + localparam logic[2:0] f3byte = 3'b000; + localparam logic[2:0] f3half = 3'b001; + localparam logic[2:0] f3word = 3'b010; + localparam logic[2:0] f3byteU = 3'b100; + localparam logic[2:0] f3halfU = 3'b101; + // ALU + localparam logic[2:0] f3add = 3'b000; + localparam logic[2:0] f3sl = 3'b001; + localparam logic[2:0] f3slt = 3'b010; + localparam logic[2:0] f3sltU = 3'b011; + localparam logic[2:0] f3xor = 3'b100; + localparam logic[2:0] f3sr = 3'b101; + localparam logic[2:0] f3or = 3'b110; + localparam logic[2:0] f3and = 3'b111; + // Branch + localparam logic[2:0] f3beq = 3'b000; + localparam logic[2:0] f3bne = 3'b001; + localparam logic[2:0] f3blt = 3'b100; + localparam logic[2:0] f3bge = 3'b101; + localparam logic[2:0] f3bltU = 3'b110; + localparam logic[2:0] f3bgeU = 3'b111; + + // Local Signals + // Instruction breakdown (excluding I/O) + logic[6:0] theOp; + logic[2:0] theFunct3; + logic[6:0] theFunct7; + logic[31:0] i_imm; + logic[31:0] s_imm; + logic[31:0] b_imm; + logic[31:0] u_imm; + logic[31:0] j_imm; + // ALU + logic[2:0] aluOp; + logic aluNegAr; + logic aluBypass; + logic[31:0] op1; + logic[31:0] op2; + logic[31:0] result; + logic eqFlag; + + // Instruction breakdown: assign values + // OpCode and functions 3/7 + assign theOp = Instruction[6:0]; + assign theFunct3 = Instruction[14:12]; + assign theFunct7 = Instruction[31:25]; + // Registers + assign Rs1 = Instruction[19:15]; + assign Rs2 = Instruction[24:20]; + assign Rd = Instruction[11:7]; + // Immediates + always_comb begin : Immediate_Generator + i_imm = {{21{Instruction[31]}}, Instruction[30:20]}; + s_imm = {{21{Instruction[31]}}, Instruction[30:25], Instruction[11:7]}; + b_imm = {{20{Instruction[31]}}, Instruction[7], Instruction[30:25], Instruction[11:8], 1'b0}; + u_imm = {Instruction[31:12], 12'b0}; + j_imm = {{12{Instruction[31]}}, Instruction[19:12], Instruction[20], Instruction[30:21], 1'b0}; + end + + // Decoder Logic + always_comb begin : Main_Decoder + // Factored port/signal values + JumpOrBranch = '0; + JumpOrBranchPC = '0; + DAddr = '0; + WData = RRs2; + WrMem = '0; + DWidth = f3word[1:0]; + WrReg = '1; + Illegal = '0; + aluOp = theFunct3; + aluNegAr = '0; + aluBypass = '0; + op1 = RRs1; + op2 = RRs2; + // OpCode Cases + case(theOp) + opLd: begin + DAddr = RRs1 + i_imm; + DWidth = theFunct3[1:0]; + aluBypass = '1; + op1 = RData; + case(theFunct3) + f3byte: op1[31:8] = {24{RData[7]}}; + f3byteU: op1[31:8] = {24{1'b0}}; + f3half: op1[31:16] = {16{RData[15]}}; + f3halfU: op1[31:16] = {16{1'b0}}; + f3word: ; + default: begin + Illegal = '1; + WrReg = '0; + JumpOrBranch = '1; + JumpOrBranchPC = CurrentPC; + end + endcase + end + opAluImm: begin + op2 = i_imm; + aluOp = theFunct3; + aluNegAr = (theFunct7 == f7neg) & (theFunct3 == f3sr); + end + opUpPC: begin + op1 = u_imm; + op2 = CurrentPC; + aluOp = f3add; + end + opSt: begin + WrReg = '0; + WrMem = '1; + DAddr = RRs1 + s_imm; + DWidth = theFunct3[1:0]; + end + opAlu: begin + aluOp = theFunct3; + aluNegAr = (theFunct7 == f7neg) & ((theFunct3 == f3add) | (theFunct3 == f3sr)); + end + opUpImm: begin + op1 = u_imm; + aluBypass = '1; + end + opBranch: begin + WrReg = '0; + JumpOrBranchPC = CurrentPC + b_imm; + aluOp = f3slt; + case(theFunct3) + f3beq : begin JumpOrBranch = ( eqFlag)? '1 : '0; end + f3bne : begin JumpOrBranch = (~eqFlag)? '1 : '0; end + f3blt : begin JumpOrBranch = ( result[0])? '1 : '0; end + f3bge : begin JumpOrBranch = (~result[0])? '1 : '0; end + f3bltU: begin aluOp = f3sltU; JumpOrBranch = ( result[0])? '1 : '0; end + f3bgeU: begin aluOp = f3sltU; JumpOrBranch = (~result[0])? '1 : '0; end + default: begin + Illegal = '1; + JumpOrBranch = '1; + JumpOrBranchPC = CurrentPC; + end + endcase + end + opJALR: begin + JumpOrBranch = '1; + JumpOrBranchPC = (RRs1 + i_imm) & 32'hFFFFFFFE; + op1 = CurrentPC; + op2 = 4; + aluOp = f3add; + end + opJAL: begin + JumpOrBranch = '1; + JumpOrBranchPC = CurrentPC + j_imm; + op1 = CurrentPC; + op2 = 4; + aluOp = f3add; + end + default: begin + Illegal = '1; + WrReg = '0; + JumpOrBranch = '1; + JumpOrBranchPC = CurrentPC; + end + endcase + end + + // ALU module instantiation + alu theALU ( + .aluOp(aluOp), + .aluNegAr(aluNegAr), + .aluBypass(aluBypass), + .op1(op1), + .op2(op2), + .result(result), + .eqFlag(eqFlag) + ); + assign WRd = result; + +endmodule diff --git a/riscv_rtl/hw/rtl/main_mem (copy).sv b/riscv_rtl/hw/rtl/main_mem (copy).sv new file mode 100644 index 0000000..2209c8c --- /dev/null +++ b/riscv_rtl/hw/rtl/main_mem (copy).sv @@ -0,0 +1,120 @@ +// ********************************************************************************************* +// main_mem.sv - Macro-based implementation using MemGen_32_11 +// ********************************************************************************************* +// Replaces the behavioral flip-flop RAM with an SRAM macro wrapper. +// +// Key differences from the original: +// - Uses MemGen_32_11 (2048 words x 32 bits, single-port SRAM macro) +// - Time-multiplexed using the 25 MHz clock for two accesses per CPU cycle: +// clk12p5=0 -> instruction fetch (IAddr) +// clk12p5=1 -> data access (DAddr read/write) +// - Word-only writes; SB/SH instructions will be dropped (TODO: add RMW later) +// - MEM_INIT_FILE parameter kept for interface compatibility (not functional) +// ********************************************************************************************* + +module main_mem #( + parameter int ABits = 13 + //parameter string MEM_INIT_FILE = "" +)( + input logic clk, // 12.5 MHz CPU clock (= clk12p5) + // input logic clk_25mhz, // NEW: 25 MHz memory clock + input logic reset, + input logic[31:0] DAddr, + input logic[31:0] IAddr, + input logic[31:0] DWData, + output logic[31:0] DRData, + output logic[31:0] IRData, + input logic DWE, + input logic[1:0] DWidth +); + + //--------------------------------------------------------------------------- + // Localparam + //--------------------------------------------------------------------------- + localparam logic[1:0] _byte = 2'b00; + localparam logic[1:0] _half = 2'b01; + localparam logic[1:0] _word = 2'b10; + + //--------------------------------------------------------------------------- + // Time-multiplexing logic + // + // The CPU runs on clk12p5 (half of clk_25mhz). + // We use clk_25mhz to drive the memory; within one CPU cycle: + // - During clk12p5 LOW: present instruction address + // - During clk12p5 HIGH: present data address + // + // The macro latches the address on the rising edge of its own clock (clk_25mhz), + // so we select which address to send based on the current phase. + //--------------------------------------------------------------------------- + + logic [10:0] mem_addr; // 11-bit word address for MemGen_32_11 + logic [31:0] mem_wr_data; + logic mem_wr_en; + logic mem_rd_en; + logic [31:0] mem_rd_data; + + // Phase: 0 = instruction fetch, 1 = data access + // Since clk12p5 rises on clk_25mhz rising edge, clk12p5 itself tells us the phase + wire phase_is_data = clk; // clk = clk12p5 + + always_comb begin + if (phase_is_data) begin + // Data phase + mem_addr = DAddr[12:2]; + mem_wr_data = DWData; + mem_wr_en = DWE && !reset && (DWidth == _word); + mem_rd_en = !DWE; + end else begin + // Instruction phase + mem_addr = IAddr[12:2]; + mem_wr_data = 32'h0; + mem_wr_en = 1'b0; + mem_rd_en = 1'b1; + end + end + + //--------------------------------------------------------------------------- + // Single memory macro - time-multiplexed + //--------------------------------------------------------------------------- + MemGen_32_11 u_mem ( + .chip_en (1'b1), + .clock (clk_25mhz), // 2x CPU clock - enables dual access per CPU cycle + .addr (mem_addr), + .rd_en (mem_rd_en), + .rd_data (mem_rd_data), + .wr_en (mem_wr_en), + .wr_data (mem_wr_dat) + ); + + //--------------------------------------------------------------------------- + // Output capture + // + // On each CPU cycle, we capture: + // - IRData: the instruction read during instruction phase + // - DRData: the data read during data phase + // + // The macro delivers rd_data one clk_25mhz cycle after the address. + //--------------------------------------------------------------------------- + + // Capture IRData at the end of the instruction phase (when data phase starts) + always_ff @(posedge clk_25mhz) begin + if (reset) begin + IRData <= 32'h0; + end else if (!phase_is_data) begin + // We just presented the data address; the read of the previous + // instruction address is now available on mem_rd_data + // (Note: timing requires verification against macro characteristics) + IRData <= mem_rd_data; + end + end + + // Capture DRData at the end of the data phase (when instruction phase starts) + always_ff @(posedge clk_25mhz) begin + if (reset) begin + DRData <= 32'h0; + end else if (phase_is_data) begin + DRData <= mem_rd_data; + end + end + +endmodule diff --git a/riscv_rtl/hw/rtl/main_mem.sv b/riscv_rtl/hw/rtl/main_mem.sv new file mode 100644 index 0000000..e40390f --- /dev/null +++ b/riscv_rtl/hw/rtl/main_mem.sv @@ -0,0 +1,142 @@ +// ********************************************************************************************* +// Project Version : v1.0 +// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog +// ----- +// Copyright (c) : 2025 Fraunhofer IIS, Department IDS +// Created : 12.Jun.2025 by Lund University [commit 5b1e415] +// Last Modified : 23.Oct.2025 by Aliakbar Merchant [commit 2f8f03d] +// ----- +// HISTORY : Date By Comments +// ----------- ---------- ------------------------------------------------- +// 22.Oct.2025 A.Merchant Added reset handling condition for Instr. read logic +// 22.Oct.2025 A.Merchant Added reset handling condition for data write logic +// ********************************************************************************************* + + +`default_nettype wire + +module main_mem #( + parameter int ABits = 13 // Number of address bits + //parameter string MEM_INIT_FILE = "" // Optional memory initializations file +) ( + input logic clk, // Clock + input logic reset, // Active high sync reset + input logic[31:0] DAddr, // Data Address + input logic[31:0] IAddr, // Instruction Address + input logic[31:0] DWData, // Data to write + output logic[31:0] DRData, // Data read + output logic[31:0] IRData, // Instruction read + input logic DWE, // Data write enable, 1=Write + input logic [1:0] DWidth // Access width (byte, half word, word) +); + + // Local Parameter + localparam logic[1:0] _byte = 2'b00; // byte: 8 bits + localparam logic[1:0] _half = 2'b01; // half: 16 bits + localparam logic[1:0] _word = 2'b10; // word: 32 bits + + // Local Signals + //logic[31:0] RAM[2**(ABits-2)-1:0]; // Memory array 8KB(8192): ignores lowest 2 bits as 32bit-word + logic [31:0] irTmp; + logic[31:0] drTmp; // Temporary register to hold the data read from RAM. + logic [10:0] mem_addr; // 11-bit word address for MemGen_32_11 + logic [31:0] mem_wdata; // 32-bit data bus for MemGen_32_11 +logic [31:0] mem_rdata; // 32-bit data bus for MemGen_32_11 + + + MemGen_32_11 RAM ( + .chip_en (1'b1), + .clock (clk), + .addr (mem_addr), + .rd_en (!DWE), + .rd_data (mem_rdata), + .wr_en (DWE), + .wr_data (mem_wdata) + ); + + // memory initilizations +// initial begin + +//if (MEM_INIT_FILE != "") begin + // $readmemh(MEM_INIT_FILE, RAM); + // end + // end + + //---------------------------------------------------------------------------// + //--------------------------- DATA WRITE LOGIC ---------------------------// + //---------------------------------------------------------------------------// + + + always_ff @(negedge clk) begin + if (reset) begin + mem_addr <= 0; + end else begin + if (DWE) begin + mem_addr <= DAddr[(ABits-1):2]; + // RAM[DAddr[(ABits-1):2]] <= DWData; + case (DWidth) + _word: + mem_wdata <= DWData; + _half: + case (DAddr[1]) + 1'b0: mem_wdata [31:16] <= DWData[15:0]; + 1'b1: mem_wdata [15: 0] <= DWData[15:0]; + endcase + _byte: + case (DAddr[1:0]) + 2'b00: mem_wdata [31:24] <= DWData[7:0]; + 2'b01: mem_wdata [23:16] <= DWData[7:0]; + 2'b10: mem_wdata [15: 8] <= DWData[7:0]; + 2'b11: mem_wdata [ 7: 0] <= DWData[7:0]; + endcase + default: ; + endcase + end else begin + mem_addr <= IAddr[(ABits-1):2]; + end + end + end + + //---------------------------------------------------------------------------// + //--------------------------- DATA READ LOGIC ----------------------------// + //---------------------------------------------------------------------------// + always_ff @(negedge clk) begin + drTmp <= mem_rdata; + end + + always_comb begin + case (DWidth) + _word: + DRData = drTmp; + _half: + case (DAddr[1]) + 1'b0: DRData = {16'b0, drTmp[31:16]}; + 1'b1: DRData = {16'b0, drTmp[15: 0]}; + endcase + _byte: + case (DAddr[1:0]) + 2'b00: DRData = {24'b0, drTmp[31:24]}; + 2'b01: DRData = {24'b0, drTmp[23:16]}; + 2'b10: DRData = {24'b0, drTmp[15: 8]}; + 2'b11: DRData = {24'b0, drTmp[ 7: 0]}; + endcase + default: ; + endcase + end + + //---------------------------------------------------------------------------// + //----------------------- INSTRUCTION READ LOGIC -------------------------// + //---------------------------------------------------------------------------// + // + //fetch intrcution from memory into IRData + always_ff @(posedge clk) begin + if (reset) begin + IRData <= mem_rdata; + end + else begin + IRData <= mem_rdata; + end + end + +endmodule + diff --git a/riscv_rtl/hw/rtl/oasys.cmd.00 b/riscv_rtl/hw/rtl/oasys.cmd.00 new file mode 100644 index 0000000..f3b2c29 --- /dev/null +++ b/riscv_rtl/hw/rtl/oasys.cmd.00 @@ -0,0 +1,15 @@ +#-------------------------------------------------------------------- +# date : Thu May 28 12:01:37 CEST 2026 +# ppid/pid : 2439771/2439781 +# hostname : efiapps0.ads1.fh-nuernberg.de +# arch/os : x86_64/Linux-4.18.0-553.123.1.el8_10.x86_64 +# install : /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1 +# currdir : /users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl +# logfile : /users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/oasys.log.00 +# tmpdir : /tmp/oasys.2439771/ +#-------------------------------------------------------------------- +# Starting Interactive Session +exit +#-------------------------------------------------------------------- +# End Session at Thu May 28 13:20:20 CEST 2026 +#-------------------------------------------------------------------- diff --git a/riscv_rtl/hw/rtl/oasys.cmd.01 b/riscv_rtl/hw/rtl/oasys.cmd.01 new file mode 100644 index 0000000..48d81df --- /dev/null +++ b/riscv_rtl/hw/rtl/oasys.cmd.01 @@ -0,0 +1,23 @@ +#-------------------------------------------------------------------- +# date : Thu May 28 13:29:15 CEST 2026 +# ppid/pid : 2451524/2451534 +# hostname : efiapps0.ads1.fh-nuernberg.de +# arch/os : x86_64/Linux-4.18.0-553.123.1.el8_10.x86_64 +# install : /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1 +# currdir : /users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl +# logfile : /users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/oasys.log.01 +# tmpdir : /tmp/oasys.2451524/ +#-------------------------------------------------------------------- +# Starting Interactive Session +ls +cd .. +ls +cd .. +cd .. +ls +source scripts_risc_v/1_read_design.tcl +source scripts_risc_v/2_synthesize_optimize.tcl +exit +#-------------------------------------------------------------------- +# End Session at Thu May 28 13:42:47 CEST 2026 +#-------------------------------------------------------------------- diff --git a/riscv_rtl/hw/rtl/oasys.cmd.02 b/riscv_rtl/hw/rtl/oasys.cmd.02 new file mode 100644 index 0000000..e69de29 diff --git a/riscv_rtl/hw/rtl/oasys.dbg.02 b/riscv_rtl/hw/rtl/oasys.dbg.02 new file mode 100644 index 0000000..5fd2f96 --- /dev/null +++ b/riscv_rtl/hw/rtl/oasys.dbg.02 @@ -0,0 +1,317 @@ + +@/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/oasys.log.02:1093 +libc: 2.28-stable + +Timestamp: 1779968572.056193725 +--- +PID=2457562 0.129170598 0.075018 0.054153 program start +Complete list of environment variables at program start +_ /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/bin/Linux-x86_64-O/oasysGui +BASH_FUNC_which%% {() { ( alias; + eval ${which_declare} ) | /usr/bin/which --tty-only --read-alias --read-functions --show-tilde --show-dot $@ +}} +CALIBRE_HOME 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+MAIL /var/spool/mail/charapallivenkatsaja +MANAGERPID 2391729 +MANPATH /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/doc/man: +MGC_AMS_HOME /applications/SiemensEDA/siemenseda2023/amsv +MGC_HOME /applications/SiemensEDA/siemenseda2023 +MGLS_HOME /applications/SiemensEDA/siemenseda2023/questasim/linux_x86_64/mgls +MGLS_LICENSE_FILE 1810@141.75.245.10 +MODELTECH /applications/SiemensEDA/siemenseda2023/questasim +MTI_VCO_MODE 64 +NIOS2_ROOTDIR /applications/intelFPGA/22.1/nios2eds +OASYSLD_LICENSE_FILE /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/license.lic +PATH /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/bin:/applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/bin/Linux-x86_64-O:/applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/lib/share/formalpro:/applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/lib/share/onespin:/applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/lib/share/slec:/applications/th_tools/scripts:/applications/intelFPGA/22.1/quartus/bin:/applications/intelFPGA/22.1/quartus/qsys/bin:/applications/intelFPGA/22.1/nios2eds:/applications/Lattice/radiant/2023.1/bin/lin64:/applications/Synopsys/synopsys2022/syn/U-2022.12-SP4/amd64/syn/bin:/applications/Synopsys/synopsys2022/scl/2022.12/linux64/bin:/applications/Synopsys/synopsys2022/fm/U-2022.12-SP4/bin:/applications/Synopsys/synopsys2022/txs/U-2022.12-SP4/bin:/applications/Synopsys/synopsys2022/lc/V-2023.12/bin:/applications/th_tools/scripts:/applications/intelFPGA/22.1/quartus/bin:/applications/intelFPGA/22.1/quartus/qsys/bin:/applications/intelFPGA/22.1/nios2eds:/applications/Lattice/radiant/2023.1/bin/lin64:/applications/Synopsys/synopsys2022/syn/U-2022.12-SP4/amd64/syn/bin:/applications/Synopsys/synopsys2022/scl/2022.12/linux64/bin:/applications/Synopsys/synopsys2022/fm/U-2022.12-SP4/bin:/applications/Synopsys/synopsys2022/txs/U-2022.12-SP4/bin:/applications/Synopsys/synopsys2022/lc/V-2023.12/bin:/users/ads1/charapallivenkatsaja/linux/.local/bin:/users/ads1/charapallivenkatsaja/linux/bin:/bin:/usr/bin:/opt/thinlinc/bin:/usr/local/bin:/usr/bin/X11:/sbin:/usr/sbin:/usr/local/sbin:/applications/Cadence/cadence2022/DDIEXPORT2233/bin:/applications/Cadence/cadence2022/SSV2213/bin:/applications/SiemensEDA/siemenseda2023/questasim/bin:/applications/SiemensEDA/siemenseda2023/questasim/linux_x86_64:/applications/SiemensEDA/siemenseda2023/questasim/vco:/applications/SiemensEDA/siemenseda2023/questasim/linux_x86_64/mgls/bin:/applications/SiemensEDA/siemenseda2023/amsv/bin:/applications/SiemensEDA/siemenseda2023/amsv/modeltech/bin:/applications/SiemensEDA/siemenseda2023/calibre/aok_cal_2023.4_39.23/bin:/applications/SiemensEDA/siemenseda2023/tessent/bin:/applications/SiemensEDA/siemenseda2023/oasys/bin:/applications/SiemensEDA/siemenseda2023/precision/bin:/applications/Cadence/cadence2022/DDIEXPORT2233/bin:/applications/Cadence/cadence2022/SSV2213/bin:/applications/SiemensEDA/siemenseda2023/questasim/bin:/applications/SiemensEDA/siemenseda2023/questasim/linux_x86_64:/applications/SiemensEDA/siemenseda2023/questasim/vco:/applications/SiemensEDA/siemenseda2023/questasim/linux_x86_64/mgls/bin:/applications/SiemensEDA/siemenseda2023/amsv/bin:/applications/SiemensEDA/siemenseda2023/amsv/modeltech/bin:/applications/SiemensEDA/siemenseda2023/calibre/aok_cal_2023.4_39.23/bin:/applications/SiemensEDA/siemenseda2023/tessent/bin:/applications/SiemensEDA/siemenseda2023/oasys/bin:/applications/SiemensEDA/siemenseda2023/precision/bin +PCSCTUN_COOKIE /var/opt/thinlinc/sessions/charapallivenkatsaja/10/pcsctun-cookie +PCSCTUN_SERVER 127.0.0.1:5006 +PULSE_COOKIE /var/opt/thinlinc/sessions/charapallivenkatsaja/10/pulse-cookie +PULSE_RUNTIME_PATH /var/opt/thinlinc/sessions/charapallivenkatsaja/10/pulse +PULSE_SERVER {/var/opt/thinlinc/sessions/charapallivenkatsaja/10/pulse/native 127.0.0.1:5005} +PWD /users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl +QSYS_ROOTDIR /applications/intelFPGA/22.1/quartus/qsys/bin +QT_IM_MODULE ibus +QUARTUS /applications/intelFPGA +QUARTUS_ROOTDIR /applications/intelFPGA/22.1/quartus +RT_CMD {/applications/SiemensEDA/siemenseda2023/oasys/bin/oasys } +RT_HOME /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1 +RT_LIBPATH /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/lib +RT_MANPATH /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/doc/man +RT_PID 2457552 +RT_SIGSTKSZ 16 +RT_TCL_PATH /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/tcl +RT_TMP /tmp/oasys.2457552 +RT_WRAPPER_SCRIPT /applications/SiemensEDA/siemenseda2023/oasys/bin/oasys +SCRIPTS /applications/th_tools/scripts +SESSION_MANAGER local/unix:@/tmp/.ICE-unix/2434259,unix/unix:/tmp/.ICE-unix/2434259 +SHELL /bin/bash +SHLVL 4 +SNPSLMD_LICENSE_FILE 1806@141.75.245.10 +SSH_ASKPASS /usr/libexec/openssh/gnome-ssh-askpass +SSH_AUTH_SOCK /run/user/1083946113/keyring/ssh +SYNOPSYS /applications/Synopsys/synopsys2022/syn/U-2022.12-SP4 +SYNOPSYS_TMAX /applications/Synopsys/synopsys2022/txs/U-2022.12-SP4 +TCL_LIBRARY /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/tcl/library +TERM xterm-256color +TLPREFIX /opt/thinlinc +TLPROFILE gnome-classic +TLSESSIONDATA /var/opt/thinlinc/sessions/charapallivenkatsaja/10 +TOWN Springfield +USER charapallivenkatsaja +USERNAME charapallivenkatsaja +VTE_VERSION 5204 +which_declare {declare -f} +XAUTHORITY /var/opt/thinlinc/sessions/charapallivenkatsaja/10/Xauthority +XDG_CURRENT_DESKTOP GNOME-Classic:GNOME +XDG_DATA_DIRS /users/ads1/charapallivenkatsaja/linux/.local/share/flatpak/exports/share:/var/lib/flatpak/exports/share:/usr/local/share:/usr/share +XDG_MENU_PREFIX gnome- +XDG_RUNTIME_DIR /run/user/1083946113 +XDG_SESSION_CLASS user +XDG_SESSION_DESKTOP gnome-classic +XDG_SESSION_ID 6060 +XDG_SESSION_TYPE x11 +XMODIFIERS @im=ibus +--- + +Timestamp: 1779968572.059144838 +--- +Soft resource limits: + +Executing: /bin/bash -f -c {ulimit -a -S} +core file size (blocks, -c) 0 +data seg size (kbytes, -d) unlimited +scheduling priority (-e) 0 +file size (blocks, -f) unlimited +pending signals (-i) 191837 +max locked memory (kbytes, -l) 64 +max memory size (kbytes, -m) unlimited +open files (-n) 1024 +pipe size (512 bytes, -p) 8 +POSIX message queues (bytes, -q) 819200 +real-time priority (-r) 0 +stack size (kbytes, -s) 81920 +cpu time (seconds, -t) unlimited +max user processes (-u) 191837 +virtual memory (kbytes, -v) unlimited +file locks (-x) unlimited +--- + +Timestamp: 1779968572.060768504 +--- +Hard resource limits: + +Executing: /bin/bash -f -c {ulimit -a -H} +core file size (blocks, -c) unlimited +data seg size (kbytes, -d) unlimited +scheduling priority (-e) 0 +file size (blocks, -f) unlimited +pending signals (-i) 191837 +max locked memory (kbytes, -l) 64 +max memory size (kbytes, -m) unlimited +open files (-n) 262144 +pipe size (512 bytes, -p) 8 +POSIX message queues (bytes, -q) 819200 +real-time priority (-r) 0 +stack size (kbytes, -s) unlimited +cpu time (seconds, -t) unlimited +max user processes (-u) 191837 +virtual memory (kbytes, -v) unlimited +file locks (-x) unlimited +--- + +Timestamp: 1779968572.061645115 +--- +CPU Information + +processor : 0 +vendor_id : AuthenticAMD +cpu family : 25 +model : 1 +model name : AMD EPYC 73F3 16-Core Processor +stepping : 1 +microcode : 0xa0011d3 +cpu MHz : 3499.999 +cache size : 512 KB +physical id : 0 +siblings : 1 +core id : 0 +cpu cores : 1 +apicid : 0 +initial apicid : 0 +fpu : yes +fpu_exception : yes +cpuid level : 16 +wp : yes +flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl tsc_reliable nonstop_tsc cpuid extd_apicid pni pclmulqdq ssse3 fma cx16 pcid sse4_1 sse4_2 x2apic movbe popcnt aes xsave avx f16c rdrand hypervisor lahf_lm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw topoext invpcid_single ibpb vmmcall fsgsbase bmi1 avx2 smep bmi2 erms invpcid rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves clzero wbnoinvd arat umip pku ospke vaes vpclmulqdq rdpid overflow_recov succor fsrm +bugs : fxsave_leak sysret_ss_attrs null_seg spectre_v1 spectre_v2 spec_store_bypass srso +bogomips : 6999.99 +TLB size : 2560 4K pages +clflush size : 64 +cache_alignment : 64 +address sizes : 45 bits physical, 48 bits virtual +power management: + + +processor : 1 +physical id : 2 +apicid : 2 +initial apicid : 2 + +processor : 2 +physical id : 4 +apicid : 4 +initial apicid : 4 + +processor : 3 +physical id : 6 +apicid : 6 +initial apicid : 6 + +processor : 4 +physical id : 8 +apicid : 8 +initial apicid : 8 + +processor : 5 +physical id : 10 +apicid : 10 +initial apicid : 10 + +processor : 6 +physical id : 12 +apicid : 12 +initial apicid : 12 + +processor : 7 +physical id : 14 +apicid : 14 +initial apicid : 14 + +processor : 8 +physical id : 16 +apicid : 16 +initial apicid : 16 + +processor : 9 +physical id : 18 +apicid : 18 +initial apicid : 18 + +processor : 10 +physical id : 20 +apicid : 20 +initial apicid : 20 + +processor : 11 +physical id : 22 +apicid : 22 +initial apicid : 22 + +This host has 12 processors, with most parameters identical to the first one, except as noted above. + +--- + +Timestamp: 1779968572.161364465 +--- +Miscellaneous system info for process PID=2457562 +Recorded at Thu May 28 13:42:52 CEST 2026 + +Executing: uptime + 13:42:52 up 20 days, 1:11, 5 users, load average: 1.99, 2.79, 2.57 + +Executing: uname -a +Linux efiapps0.ads1.fh-nuernberg.de 4.18.0-553.123.1.el8_10.x86_64 #1 SMP Mon May 4 13:45:48 EDT 2026 x86_64 x86_64 x86_64 GNU/Linux + +Executing: free + total used free shared buff/cache available +Mem: 49166924 12854332 9280556 826488 27032036 34721076 +Swap: 25165820 8312 25157508 + +Executing: ps u 2457562 +USER PID %CPU %MEM VSZ RSS TTY STAT START TIME COMMAND +charapa+ 2457562 13.0 0.1 438180 69168 pts/2 S+ 13:42 0:00 /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/bin/Linux-x86_64-O/oasysGui -- + +Executing: cat /etc/redhat-release +Red Hat Enterprise Linux release 8.9 (Ootpa) + +Executing: ldd /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/bin/Linux-x86_64-O/oasysGui + linux-vdso.so.1 (0x00007fff5a525000) + libQt5PrintSupport.so.5 => /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/bin/Linux-x86_64-O/../../lib/Linux-x86_64-O/libQt5PrintSupport.so.5 (0x00007f7623103000) + libQt5Widgets.so.5 => /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/bin/Linux-x86_64-O/../../lib/Linux-x86_64-O/libQt5Widgets.so.5 (0x00007f76226ab000) + libQt5Gui.so.5 => /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/bin/Linux-x86_64-O/../../lib/Linux-x86_64-O/libQt5Gui.so.5 (0x00007f7621d0f000) + libQt5Core.so.5 => /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/bin/Linux-x86_64-O/../../lib/Linux-x86_64-O/libQt5Core.so.5 (0x00007f7621178000) + libmemsh-102.so => /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/bin/Linux-x86_64-O/../../lib/Linux-x86_64-O/libmemsh-102.so (0x00007f76235b0000) + libncurses.so.5 => /lib64/libncurses.so.5 (0x00007f7620f51000) + libpthread.so.0 => /lib64/libpthread.so.0 (0x00007f7620d31000) + libdl.so.2 => /lib64/libdl.so.2 (0x00007f7620b2d000) + librt.so.1 => /lib64/librt.so.1 (0x00007f7620925000) + libX11.so.6 => /lib64/libX11.so.6 (0x00007f76205e1000) + libz.so.1 => /lib64/libz.so.1 (0x00007f76203c9000) + libm.so.6 => /lib64/libm.so.6 (0x00007f7620047000) + libc.so.6 => /lib64/libc.so.6 (0x00007f761fc71000) + libgthread-2.0.so.0 => /lib64/libgthread-2.0.so.0 (0x00007f761fa6f000) + libglib-2.0.so.0 => /lib64/libglib-2.0.so.0 (0x00007f761f755000) + /lib64/ld-linux-x86-64.so.2 (0x00007f76233a4000) + libtinfo.so.5 => /lib64/libtinfo.so.5 (0x00007f761f52a000) + libxcb.so.1 => /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/bin/Linux-x86_64-O/../../lib/Linux-x86_64-O/libxcb.so.1 (0x00007f761f2f5000) + libgnutls.so.30 => /lib64/libgnutls.so.30 (0x00007f761ef04000) + libpcre.so.1 => /lib64/libpcre.so.1 (0x00007f761ec93000) + libXau.so.6 => /lib64/libXau.so.6 (0x00007f761ea8f000) + libXdmcp.so.6 => /lib64/libXdmcp.so.6 (0x00007f761e889000) + libp11-kit.so.0 => /lib64/libp11-kit.so.0 (0x00007f761e55f000) + libidn2.so.0 => /lib64/libidn2.so.0 (0x00007f761e341000) + libunistring.so.2 => /lib64/libunistring.so.2 (0x00007f761dfc0000) + libtasn1.so.6 => /lib64/libtasn1.so.6 (0x00007f761ddad000) + libnettle.so.6 => /lib64/libnettle.so.6 (0x00007f761db73000) + libhogweed.so.4 => /lib64/libhogweed.so.4 (0x00007f761d943000) + libgmp.so.10 => /lib64/libgmp.so.10 (0x00007f761d6ab000) + libffi.so.6 => /lib64/libffi.so.6 (0x00007f761d4a2000) + +Examining disk space in the following directories: + Current directory: /users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl + Oasys' temp directory: /tmp/oasys.2457552/ (normalized path: /tmp/oasys.2457552) + RT_TMP directory: /tmp/oasys.2457552 + +Executing: df /users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl /tmp/oasys.2457552 /tmp/oasys.2457552 +Filesystem 1K-blocks Used Available Use% Mounted on +/dev/sdc1 10485760 2530136 7955624 25% /users +/dev/sda3 25582384 9713924 15868460 38% / +/dev/sda3 25582384 9713924 15868460 38% / + + +--- + diff --git a/riscv_rtl/hw/rtl/oasys.log.00 b/riscv_rtl/hw/rtl/oasys.log.00 new file mode 100644 index 0000000..e6e7a03 --- /dev/null +++ b/riscv_rtl/hw/rtl/oasys.log.00 @@ -0,0 +1,29 @@ +******************************************************************* +* Oasys-RTL™ - release 2022.2.R1 * +* * +* This material contains trade secrets or otherwise confidential * +* information owned by Siemens Industry Software Inc. or its * +* affiliates (collectively, "SISW"), or its licensors. Access to * +* and use of this information is strictly limited as set forth * +* in the Customer’s applicable agreements with SISW. * +* * +* Unpublished work. © 2023 Siemens * +* * +* Program : ../bin/Linux-x86_64-O/oasysGui * +* Version : 22.2-p002 * +* Date : Mon Jan 16 21:36:23 PST 2023 * +* Build : releases/22.2-54756.0-CentOS_6.5-O * +******************************************************************* + config sdc-v1.7-cpd cli cmd explore mxdb o2n fp rta mpg-m-w dft +loading: oa2tessent-d ctl verify edit bt upf-c aos conc ipc-l vcd o2pp prot int oa2ap +checked out license: psyncore + + date : Thu May 28 12:01:37 CEST 2026 + ppid/pid : 2439771/2439781 + hostname : efiapps0.ads1.fh-nuernberg.de + arch/os : x86_64/Linux-4.18.0-553.123.1.el8_10.x86_64 + install : /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1 + currdir : /users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl + logfile : /users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/oasys.log.00 + tmpdir : /tmp/oasys.2439771/ +> source /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/tcl/library/history.tcl diff --git a/riscv_rtl/hw/rtl/oasys.log.01 b/riscv_rtl/hw/rtl/oasys.log.01 new file mode 100644 index 0000000..4c565a9 --- /dev/null +++ b/riscv_rtl/hw/rtl/oasys.log.01 @@ -0,0 +1,591 @@ +******************************************************************* +* Oasys-RTL™ - release 2022.2.R1 * +* * +* This material contains trade secrets or otherwise confidential * +* information owned by Siemens Industry Software Inc. or its * +* affiliates (collectively, "SISW"), or its licensors. Access to * +* and use of this information is strictly limited as set forth * +* in the Customer’s applicable agreements with SISW. * +* * +* Unpublished work. © 2023 Siemens * +* * +* Program : ../bin/Linux-x86_64-O/oasysGui * +* Version : 22.2-p002 * +* Date : Mon Jan 16 21:36:23 PST 2023 * +* Build : releases/22.2-54756.0-CentOS_6.5-O * +******************************************************************* + config sdc-v1.7-cpd cli cmd explore mxdb o2n fp rta mpg-m-w dft +loading: oa2tessent-d ctl verify edit bt upf-c aos conc ipc-l vcd o2pp prot int oa2ap +checked out license: psyncore + + date : Thu May 28 13:29:15 CEST 2026 + ppid/pid : 2451524/2451534 + hostname : efiapps0.ads1.fh-nuernberg.de + arch/os : x86_64/Linux-4.18.0-553.123.1.el8_10.x86_64 + install : /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1 + currdir : /users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl + logfile : /users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/oasys.log.01 + tmpdir : /tmp/oasys.2451524/ +> source /applications/SiemensEDA/siemenseda2023/Oasys-RTL-2022.2.R1/tcl/library/history.tcl +> source scripts_risc_v/1_read_design.tcl +> source scripts_risc_v/init_design.tcl +> config_shell -echo true +> config_report timing -format {cell edge arrival delay arc_delay net_delay slew net_load load fanout location power_domain} +> source scripts_risc_v/demo_chip_design_files.tcl + +----------------------------- + +Done setting design variables + +----------------------------- + +> read_db ./libs/nangate_mvt.odb +info: Reading '/users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/nangate_mvt.odb' [UFILE-107] + starting at 00:00:00(cpu)/0:00:51(wall) 102MB(vsz)/470MB(peak) +extracting odb ... finished at 00:00:00(cpu)/0:00:51(wall) 102MB(vsz)/470MB(peak) + Write Date : Mon, 21 Jun 2021 13:47:25 -0700 + Host : orw-ericc-r78 (64bit) + Tool Version : 21.1-p004 (60,9-71,11) + Tool Date : Fri Jun 11 12:44:10 PDT 2021 + Tool Build : 52545.0-O + Design Name : + Comment : +loading environment ... finished at 00:00:00(cpu)/0:00:51(wall) 102MB(vsz)/470MB(peak) +loading libraries ... finished at 00:00:01(cpu)/0:00:51(wall) 113MB(vsz)/476MB(peak) +all done +> create_threshold_voltage_group HVT -lib_cells {NangateOpenCellLibrary_45nm_HVT_0p85/AND2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND2_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND3_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND3_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND3_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND4_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND4_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND4_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/ANTENNA_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI21_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI21_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI21_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI22_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI22_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI22_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI211_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI211_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI211_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI221_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI221_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI221_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI222_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI222_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI222_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X16_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X32_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKBUF_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKBUF_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKBUF_X3_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFRS_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFRS_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFR_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFR_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFS_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFS_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFF_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFF_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLH_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLH_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLL_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLL_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FA_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X16_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X32_HVT NangateOpenCellLibrary_45nm_HVT_0p85/HA_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X16_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X32_HVT NangateOpenCellLibrary_45nm_HVT_0p85/LOGIC0_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/LOGIC1_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/MUX2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/MUX2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND2_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND3_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND3_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND3_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND4_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND4_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND4_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR2_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR3_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR3_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR3_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR4_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR4_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR4_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI21_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI21_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI21_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI22_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI22_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI22_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI33_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI211_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI211_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI211_X4_HVT ...(34 more)} +> create_threshold_voltage_group SVT -lib_cells {NangateOpenCellLibrary_45nm_SVT_0p85/AND2_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND2_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND2_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND3_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND3_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND3_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND4_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND4_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AND4_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/ANTENNA_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI21_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI21_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI21_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI22_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI22_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI22_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI211_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI211_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI211_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI221_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI221_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI221_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI222_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI222_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/AOI222_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X8_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X16_SVT NangateOpenCellLibrary_45nm_SVT_0p85/BUF_X32_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKBUF_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKBUF_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKBUF_X3_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATETST_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATETST_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATETST_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATETST_X8_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATE_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATE_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATE_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/CLKGATE_X8_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFFRS_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFFRS_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFFR_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFFR_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFFS_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFF_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DFF_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DLH_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DLH_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DLL_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/DLL_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FA_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X8_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X16_SVT NangateOpenCellLibrary_45nm_SVT_0p85/FILLCELL_X32_SVT NangateOpenCellLibrary_45nm_SVT_0p85/HA_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X8_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X16_SVT NangateOpenCellLibrary_45nm_SVT_0p85/INV_X32_SVT NangateOpenCellLibrary_45nm_SVT_0p85/LOGIC0_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/LOGIC1_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/MUX2_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/MUX2_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND2_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND2_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND2_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND3_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND3_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND3_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND4_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND4_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NAND4_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR2_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR2_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR2_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR3_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR3_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR3_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR4_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR4_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/NOR4_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI21_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI21_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI21_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI22_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI22_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI22_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI33_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI211_X1_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI211_X2_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI211_X4_SVT NangateOpenCellLibrary_45nm_SVT_0p85/OAI221_X1_SVT ...(34 more)} +> create_threshold_voltage_group LVT -lib_cells {NangateOpenCellLibrary_45nm_LVT_0p85/AND2_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND2_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND2_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND3_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND3_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND3_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND4_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND4_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AND4_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/ANTENNA_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI21_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI21_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI21_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI22_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI22_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI22_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI211_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI211_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI211_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI221_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI221_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI221_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI222_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI222_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/AOI222_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/BUF_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/BUF_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/BUF_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/BUF_X8_LVT NangateOpenCellLibrary_45nm_LVT_0p85/BUF_X16_LVT NangateOpenCellLibrary_45nm_LVT_0p85/BUF_X32_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKBUF_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKBUF_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKBUF_X3_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATETST_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATETST_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATETST_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATETST_X8_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATE_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATE_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATE_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/CLKGATE_X8_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFFRS_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFFRS_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFFR_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFFR_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFFS_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFFS_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFF_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DFF_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DLH_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DLH_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DLL_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/DLL_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/FA_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/FILLCELL_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/FILLCELL_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/FILLCELL_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/FILLCELL_X8_LVT NangateOpenCellLibrary_45nm_LVT_0p85/FILLCELL_X16_LVT NangateOpenCellLibrary_45nm_LVT_0p85/FILLCELL_X32_LVT NangateOpenCellLibrary_45nm_LVT_0p85/HA_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/INV_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/INV_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/INV_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/INV_X8_LVT NangateOpenCellLibrary_45nm_LVT_0p85/INV_X16_LVT NangateOpenCellLibrary_45nm_LVT_0p85/INV_X32_LVT NangateOpenCellLibrary_45nm_LVT_0p85/LOGIC0_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/LOGIC1_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/MUX2_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/MUX2_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND2_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND2_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND2_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND3_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND3_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND3_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND4_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND4_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NAND4_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR2_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR2_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR2_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR3_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR3_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR3_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR4_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR4_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/NOR4_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI21_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI21_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI21_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI22_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI22_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI22_X4_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI33_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI211_X1_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI211_X2_LVT NangateOpenCellLibrary_45nm_LVT_0p85/OAI211_X4_LVT ...(34 more)} +> report_operating_conditions +Report Operating conditions: +-----+---------------+--------+-------------+------------------------------------+--------+--------+----------- + |Name |Default?|Type |Library |Process |Voltage |Temperature +-----+---------------+--------+-------------+------------------------------------+--------+--------+----------- +1 |typical | |standard cell|IO |1.000000|1.100000| 27.000000 +2 |TYP | |standard cell|PLL_TYP |1.000000|0.900000| 25.000000 +3 |typical | |standard cell|MemGen_16_10 |1.000000|1.800000| 25.000000 +4 |worst_low_0p85V| |standard cell|NangateOpenCellLibrary_45nm_HVT_0p85|1.000000|0.850000| -40.000000 +5 |worst_low | |standard cell|NangateOpenCellLibrary_45nm_HVT |1.000000|0.950000| -40.000000 +-----+---------------+--------+-------------+------------------------------------+--------+--------+----------- +> config_tolerance -blackbox true -connection_mismatch true -missing_physical_library true -continue_on_error false +> read_verilog -sv {alu.sv cpu.sv decoder.sv MemGen_32_11.sv main_mem.sv pc.sv reg_file.sv} -include ./riscv_rtl/hw/rtl +info: File 'alu.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros/./riscv_rtl/hw/rtl/alu.sv' using search_path variable. [CMD-126] +info: File 'cpu.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros/./riscv_rtl/hw/rtl/cpu.sv' using search_path variable. [CMD-126] +info: File 'decoder.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros/./riscv_rtl/hw/rtl/decoder.sv' using search_path variable. [CMD-126] +info: File 'MemGen_32_11.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros/./riscv_rtl/hw/rtl/MemGen_32_11.sv' using search_path variable. [CMD-126] +info: File 'main_mem.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros/./riscv_rtl/hw/rtl/main_mem.sv' using search_path variable. [CMD-126] +info: File 'pc.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros/./riscv_rtl/hw/rtl/pc.sv' using search_path variable. [CMD-126] +info: File 'reg_file.sv', resolved to path '/users/projekte/projekt01/RISC-V_w_RAM-Macros/./riscv_rtl/hw/rtl/reg_file.sv' using search_path variable. [CMD-126] +> set_max_route_layer 10 +Top-most available layer for routing set to metal10 +> set_dont_use {IO/PADBID IO/PADCLK PLL_TYP/PLL MemGen_16_10/MemGen_16_10 NangateOpenCellLibrary_45nm_HVT_0p85/AND2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND2_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND3_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND3_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND3_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND4_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND4_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AND4_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/ANTENNA_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI21_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI21_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI21_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI22_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI22_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI22_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI211_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI211_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI211_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI221_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI221_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI221_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI222_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI222_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/AOI222_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X16_HVT NangateOpenCellLibrary_45nm_HVT_0p85/BUF_X32_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKBUF_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKBUF_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKBUF_X3_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATETST_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/CLKGATE_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFRS_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFRS_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFR_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFR_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFS_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFFS_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFF_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DFF_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLH_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLH_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLL_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/DLL_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FA_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X16_HVT NangateOpenCellLibrary_45nm_HVT_0p85/FILLCELL_X32_HVT NangateOpenCellLibrary_45nm_HVT_0p85/HA_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X8_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X16_HVT NangateOpenCellLibrary_45nm_HVT_0p85/INV_X32_HVT NangateOpenCellLibrary_45nm_HVT_0p85/LOGIC0_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/LOGIC1_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/MUX2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/MUX2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND2_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND3_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND3_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND3_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND4_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND4_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NAND4_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR2_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR2_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR2_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR3_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR3_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR3_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR4_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR4_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/NOR4_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI21_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI21_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI21_X4_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI22_X1_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI22_X2_HVT NangateOpenCellLibrary_45nm_HVT_0p85/OAI22_X4_HVT ...(306 more)} false + +----------------------------- + +Done preparing design for synthesis + +----------------------------- + +> source scripts_risc_v/2_synthesize_optimize.tcl +> synthesize -module cpu -map_to_scan -gate_clock +starting synthesize at 00:00:01(cpu)/0:00:56(wall) 120MB(vsz)/480MB(peak) +warning: skipping cell ANTENNA_X1_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell FILLCELL_X1_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell FILLCELL_X2_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell FILLCELL_X4_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell FILLCELL_X8_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell FILLCELL_X16_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell FILLCELL_X32_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell LOGIC0_X1_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell LOGIC1_X1_HVT in the library since it does not have delay arcs [NL-215] +warning: skipping cell ANTENNA_X1_HVT in the library since it does not have delay arcs [NL-215] +-------> Message [NL-215] suppressed 44 times +info: clock-gating cell for posedge FFs = CLKGATE_X1_LVT in target library 'default' [POWER-112] +info: no clock-gating cell found in target library 'default' for negedge FFs for the given specification [POWER-113] +info: clock_gating minimum_width = 4, maximum_fanout = 2147483647, num_stages = 2147483647, sequential_cell = (null), control_port = (null), control_point = none, observability = no, use_discrete_cells = no, create_multi_stage = no, merge_multi_stage = no, exclude_instantiated_clock_gates = no, log = (null), allow_clock_inversion = no [POWER-111] +info: synthesizing module 'cpu' (depth 1) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/cpu.sv:17)[7]) [VLOG-400] +info: synthesizing module 'decoder' (depth 2) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/decoder.sv:17)[7]) [VLOG-400] +info: synthesizing module 'alu' (depth 3) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/alu.sv:16)[7]) [VLOG-400] +info: done synthesizing module 'alu' (depth 3) (1#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/alu.sv:16)[7]) [VLOG-401] +info: done synthesizing module 'decoder' (depth 2) (2#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/decoder.sv:17)[7]) [VLOG-401] +info: synthesizing module 'reg_file' (depth 2) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/reg_file.sv:15)[7]) [VLOG-400] +warning: target library has multiple operating conditions defined, but no default has been set. Assuming default voltage 0.85V, temperature -40.00 and process 1.00 [LIB-218] +info: done synthesizing module 'reg_file' (depth 2) (3#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/reg_file.sv:15)[7]) [VLOG-401] +info: synthesizing module 'pc' (depth 2) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/pc.sv:16)[7]) [VLOG-400] +info: done synthesizing module 'pc' (depth 2) (4#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/pc.sv:16)[7]) [VLOG-401] +warning: named parameter override 'MEM_INIT_FILE' does not match any parameter in module 'main_mem' ((/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/cpu.sv:122)[8]) [VLOG-409] +info: synthesizing module 'main_mem' (depth 2) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/main_mem.sv:18)[7]) [VLOG-400] +info: synthesizing module 'MemGen_32_11' (depth 3) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/MemGen_32_11.sv:1)[7]) [VLOG-400] +info: done synthesizing module 'MemGen_32_11' (depth 3) (5#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/MemGen_32_11.sv:1)[7]) [VLOG-401] +warning: always_comb on 'DRData' did not result in combinational logic ((/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/main_mem.sv:110)[8], (/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/main_mem.sv:113)[16], (/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/main_mem.sv:114)[16], (/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/main_mem.sv:118)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/main_mem.sv:119)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/main_mem.sv:120)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/main_mem.sv:121)[17]) [SYN-112] +warning: inferring latch for variable 'DRData' ((/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/main_mem.sv:110)[8], (/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/main_mem.sv:113)[16], (/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/main_mem.sv:114)[16], (/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/main_mem.sv:118)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/main_mem.sv:119)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/main_mem.sv:120)[17], (/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/main_mem.sv:121)[17]) [VLOG-566] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +info: no appropriate FF cell found for register bank 'mem_wdata_reg' when clock-gating - ignored for clock-gating [POWER-102] +-------> Message [POWER-102] suppressed 22 times +info: done synthesizing module 'main_mem' (depth 2) (6#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/main_mem.sv:18)[7]) [VLOG-401] +info: done synthesizing module 'cpu' (depth 1) (7#7) ((/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/cpu.sv:17)[7]) [VLOG-401] +finished synthesize at 00:00:02(cpu)/0:00:57(wall) 173MB(vsz)/530MB(peak) +> set_route_layer_max_usage metal2 0.5 +> set_route_layer_max_usage metal3 0.8 +> set_route_layer_max_usage metal6 0.8 +> write_db ./output/odb/riscv_chip.syn.odb +info: design 'cpu' has no physical info [WRITE-120] +warning: WrSdc.. design 'cpu' has no timing constraints [TA-118] +> read_sdc -verbose ./constraints/riscv.sdc +> create_clock -name clk_25mhz -period 40.000 -waveform { 0 20 } clk_25mhz +> create_generated_clock -name clk_12p5 -source clk_25mhz -divide_by 2 thePC/clk +info: create_generated_clock attempted to push hier assertion to driver but driver drives other loads +info: Moved 1 constraints on hierarchical pins to their respective driving/loading pins: + thePC/clk to {thePC/CurrentPC_reg[0]/CK} {thePC/CurrentPC_reg[1]/CK} {thePC/CurrentPC_reg[2]/CK} {thePC/CurrentPC_reg[3]/CK} {thePC/CurrentPC_reg[4]/CK} {thePC/CurrentPC_reg[5]/CK} {thePC/CurrentPC_reg[6]/CK} {thePC/CurrentPC_reg[7]/CK} {thePC/CurrentPC_reg[8]/CK} {thePC/CurrentPC_reg[9]/CK} {thePC/CurrentPC_reg[10]/CK} {thePC/CurrentPC_reg[11]/CK} {thePC/CurrentPC_reg[12]/CK} {thePC/CurrentPC_reg[13]/CK} {thePC/CurrentPC_reg[14]/CK} {thePC/CurrentPC_reg[15]/CK} {thePC/CurrentPC_reg[16]/CK} {thePC/CurrentPC_reg[17]/CK} {thePC/CurrentPC_reg[18]/CK} {thePC/CurrentPC_reg[19]/CK} {thePC/CurrentPC_reg[20]/CK} {thePC/CurrentPC_reg[21]/CK} {thePC/CurrentPC_reg[22]/CK} {thePC/CurrentPC_reg[23]/CK} {thePC/CurrentPC_reg[24]/CK} {thePC/CurrentPC_reg[25]/CK} {thePC/CurrentPC_reg[26]/CK} {thePC/CurrentPC_reg[27]/CK} {thePC/CurrentPC_reg[28]/CK} {thePC/CurrentPC_reg[29]/CK} {thePC/CurrentPC_reg[30]/CK} {thePC/CurrentPC_reg[31]/CK} +> set_clock_uncertainty -setup 0.5 clk_25mhz +> set_clock_uncertainty -hold 0.2 clk_25mhz +> set_clock_transition 0.1 clk_25mhz +> set_input_delay -clock clk_25mhz -max 2.0 { btn[6] btn[5] btn[4] btn[3] btn[2] btn[1] btn[0] } +> set_input_delay -clock clk_25mhz -min 0.5 { btn[6] btn[5] btn[4] btn[3] btn[2] btn[1] btn[0] } +> set_output_delay -clock clk_25mhz -max 2.0 { led[7] led[6] led[5] led[4] led[3] led[2] led[1] led[0] } +> set_output_delay -clock clk_25mhz -min 0.5 { led[7] led[6] led[5] led[4] led[3] led[2] led[1] led[0] } +> set_false_path -from btn[0] +# set_false_path -from btn[0] +> set_clock_groups -asynchronous -group clk_25mhz -group clk_12p5 +> set_driving_cell -lib_cell BUF_X1_HVT -library NangateOpenCellLibrary_45nm_HVT_0p85 { btn[6] btn[5] btn[4] btn[3] btn[2] btn[1] btn[0] } +> set_load 0.05 { led[7] led[6] led[5] led[4] led[3] led[2] led[1] led[0] } +> current_design +> set_max_fanout 20 cpu +> current_design +> set_max_transition 0.5 cpu +info: 'set_max_fanout' command ignored 1 time(s) [SDC-148] +info: 'set_max_transition' command ignored 1 time(s) [SDC-150] +> report_design_metrics +Report Physical info: +------------------------+--------+-----------+------------ + | |Area (squm)|Leakage (uW) +------------------------+--------+-----------+------------ +Design Name |cpu | | + Total Instances | 7271| 60170| 625.907 + Macros | 4| 46249| 518.216 + Pads | 0| 0| 0.000 + Phys | 0| 0| 0.000 + Blackboxes | 0| 0| 0.000 + Cells | 7267| 13921| 107.691 + Buffers | 0| 0| 0.000 + Inverters | 645| 343| 4.523 + Clock-Gates | 32| 111| 0.688 + Combinational | 5426| 6457| 51.156 + Latches | 32| 85| 0.602 + FlipFlops | 1132| 6926| 50.722 + Single-Bit FF | 1132| 6926| 50.722 + Multi-Bit FF | 0| 0| 0.000 + Clock-Gated | 993| | + Bits | 1132| 6926| 50.722 + Load-Enabled | 0| | + Clock-Gated | 993| | + Tristate Pin Count | 0| | +Physical Info |Unplaced| | + Chip Size (mm x mm) | | 0| + Fixed Cell Area | | 0| + Phys Only | 0| 0| + Placeable Area | | 0| + Movable Cell Area | | 60170| + Utilization (%) | | | + Chip Utilization (%) | | | + Total Wire Length (mm)| 0.000| | + Longest Wire (mm) | | | + Average Wire (mm) | | | +------------------------+--------+-----------+------------ +> check_timing +Report Check Timing: +-----+------------------------------+------+--------+------+----------------------------------------------- + |Item |Errors|Warnings|Status|Description +-----+------------------------------+------+--------+------+----------------------------------------------- +1 |no_clock_defined | 0| 0|Passed|No clock is defined in the design +2 |invalid_generated_clock | 0| 0|Passed|Generated clock is not sourced by a valid clock +3 |unconstrained_IO | 0| 1|Passed|Unconstrained IO pin +4 |unexpected_assertion | 0| 0|Passed|Found unexpected timing assertion +5 |trigger_pin_without_required | 0| 32|Passed|Trigger pin does not get required data +6 |setup_pin_without_data | 0| 0|Passed|Setup pin does not get arriving data +7 |setup_pin_with_clock | 0| 0|Passed|Setup pin has clock signal arriving +8 |clock_pin_with_multiple_clocks| 0| 0|Passed|Clock pin has multiple clock signals +9 |clock_pin_without_clock | 0| 1|Passed|Clock pin does not have clock signal +10 |clock_pin_with_data | 0| 2|Passed|Clock pin has data signal arriving +-----+------------------------------+------+--------+------+----------------------------------------------- +> all_inputs +> group_path -name I2R -from { btn[6] btn[5] btn[4] btn[3] btn[2] btn[1] btn[0] clk_25mhz scan_en } +# group_path -from {btn[6]} {btn[5]} {btn[4]} {btn[3]} {btn[2]} {btn[1]} {btn[0]} clk_25mhz scan_en +> all_inputs +> all_outputs +> group_path -name I2O -from { btn[6] btn[5] btn[4] btn[3] btn[2] btn[1] btn[0] clk_25mhz scan_en } -to { led[7] led[6] led[5] led[4] led[3] led[2] led[1] led[0] } +# group_path -from {btn[6]} {btn[5]} {btn[4]} {btn[3]} {btn[2]} {btn[1]} {btn[0]} clk_25mhz scan_en -to {led[7]} {led[6]} {led[5]} {led[4]} {led[3]} {led[2]} {led[1]} {led[0]} +> all_outputs +> group_path -name R2O -to { led[7] led[6] led[5] led[4] led[3] led[2] led[1] led[0] } +# group_path -to {led[7]} {led[6]} {led[5]} {led[4]} {led[3]} {led[2]} {led[1]} {led[0]} +> report_path_groups +Report Path Groups: +-----+-------+------+---------+--------- + | Path |Weight|Critical |Worst + | Group | |Range(ps)|Slack(ps) +-----+-------+------+---------+--------- +1 |default| 1.000| 0.0| 17832.1 +2 |I2R | 1.000| 0.0| 39366.0 +3 |I2O | 1.000| 0.0| +4 |R2O | 1.000| 0.0| 36153.7 +-----+-------+------+---------+--------- +> optimize -virtual +starting optimize at 00:00:03(cpu)/0:00:59(wall) 181MB(vsz)/530MB(peak) +info: mapped 0 flop(s) to scan cells, excluded 0 is_dont_scan flop(s) and 0 is_dont_touch flop(s) +Log file for child PID=2452026: /users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/oasys.etc.01/oasys.w1.01.log +Log file for child PID=2452034: /users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/oasys.etc.01/oasys.w2.01.log +Log file for child PID=2452043: /users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/oasys.etc.01/oasys.w3.01.log +Log file for child PID=2452053: /users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl/hw/rtl/oasys.etc.01/oasys.w4.01.log +info: optimized '' area changed 0.0squm (x1), total 13919.5squm (#1, 0 secs) +info: dissolving instance 'thePC' of module 'pc' in module 'cpu__GC0' [NL-146] +info: optimized 'cpu__GC0' area changed -1461.7squm (x1), total 12457.8squm (#2) +info: optimized 'reg_file__GB1' area changed -841.1squm (x1), total 11616.8squm (#3) +info: optimized 'reg_file__always' area changed -83.5squm (x1), total 11533.2squm (#4) +info: optimized 'main_mem__GC0' area changed -90.4squm (x1), total 11442.8squm (#5) +info: optimized 'MemGen_32_11__block' area changed -2.4squm (x1), total 11440.4squm (#6) +info: optimized '' area changed 0.0squm (x1), total 11440.4squm (#7, 0 secs) +info: optimized 'cpu__GC0' area changed 0.0squm (x1), total 11440.4squm (#8) +info: optimized 'MemGen_32_11__block' area changed 0.0squm (x1), total 11440.4squm (#9) +info: optimized '' area changed 0.0squm (x1), total 11440.4squm (#10, 0 secs) +done optimizing area at 00:00:15(cpu)/0:01:06(wall) 181MB(vsz)/568MB(peak) +Splitting congested rtl-partitions +info: Target library/cell information has changed that further may change timing results. [TA-159] +info: optimizing design 'cpu' - propagating constants +info: optimized '' area changed 0.0squm (x1), total 11440.4squm (#1, 0 secs) +info: set slack mode to optimize shift +info: resetting all path groups +info: activated path group default @ 18015.8ps +info: activated path group I2R @ 39177.7ps +info: suspended path group I2O @ ps +info: activated path group R2O @ 36338.3ps +info: finished path group default @ 18015.8ps +info: finished path group R2O @ 36338.3ps +info: finished path group I2R @ 39177.7ps +info: reactivating path groups +info: reactivated path group default @ 18015.8ps +info: reactivated path group I2R @ 39177.7ps +info: reactivated path group R2O @ 36338.3ps +info: finished path group default @ 18015.8ps +info: finished path group R2O @ 36338.3ps +info: finished path group I2R @ 39177.7ps +info: set slack mode to normal +info: done with all path groups +info: restore all path groups +info: starting area recovery on module cpu +info: optimized 'cpu__GC0' area recovered 0.00squm (x1), total 0.00squm (1#5), 0.03 secs +info: optimized 'main_mem__GC0' area recovered 0.00squm (x1), total 0.00squm (2#5), 0.04 secs +info: optimized 'MemGen_32_11__block' area recovered 0.00squm (x1), total 0.00squm (3#5), 0.00 secs +info: optimized 'reg_file__always' area recovered 0.00squm (x1), total 0.00squm (4#5), 0.01 secs +info: optimized 'reg_file__GB1' area recovered 0.00squm (x1), total 0.00squm (5#5), 0.03 secs +info: area recovery done, total area reduction: 0.00squm (0.00%), final slack: 18015.8ps (delta: 0.0ps) (0 secs) +done optimizing virtual at 00:00:17(cpu)/0:01:07(wall) 200MB(vsz)/568MB(peak) +finished optimize at 00:00:17(cpu)/0:01:07(wall) 201MB(vsz)/568MB(peak) +> write_db ./output/odb/riscv_chip.virtual_opt.odb +> report_timing +Report for group default +-------------------------------------------------------------------------------------------------------------------------------------- +Startpoint: theMem/IRData_reg[18]/Q + (Clocked by clk_25mhz R) +Endpoint: theMem/mem_addr_reg[5]/D + (Clocked by clk_25mhz F) +Path Group: default +Data required time: 19227.4 + (Clock shift: 20000.0, minus Uncertainty: 500.0, plus Latency 0.0, minus Setup time: 272.6) +Data arrival time: 1211.5 +Slack: 18015.8 +Logic depth: 46 +-------------------------------------------------------------------------------------------------------------------------------------- + Arrival Arc Net Net Total fan- +Path Module/Cell Edge Time Delay Delay Delay Slew Load Load out Location + (ps) (ps) (ps) (ps) (ps) (ff) (ff) (#) (um,um) +-------------------------------------------------------------------------------------------------------------------------------------- +clk_25mhz {create_clock} r 0.0 0.0 0.0 0.0 0.0 2 +i_0_1_2/B->Z MUX2_X2_LVT rr 0.0 0.0 0.0 0.0 100.0 0.0 0.0 100 +theMem/IRData_reg[18]/CK->Q + SDFF_X1_LVT* rr 84.9 84.9 84.9 0.0 100.0 10.6 73.4 11 +theRegisters/i_1_0_1371/A->ZN + INV_X8_LVT rf 87.6 2.7 2.7 0.0 10.2 2.1 13.2 3 +theRegisters/i_1_0_1339/A2->ZN + NAND3_X4_LVT fr 101.6 14.0 14.0 0.0 1.0 2.5 17.5 4 +theRegisters/i_1_0_1321/A2->ZN + NOR2_X4_LVT* rf 120.6 19.0 19.0 0.0 12.1 29.7 130.1 32 +theRegisters/i_1_0_722/B1->ZN + AOI22_X4_LVT* fr 164.9 44.3 44.3 0.0 10.2 0.7 23.4 1 +theRegisters/i_1_0_721/A->ZN + INV_X8_LVT rf 167.0 2.1 2.1 0.0 10.2 0.8 3.0 1 +theRegisters/i_1_0_718/A->ZN + AOI221_X2_LVT fr 224.3 57.3 57.3 0.0 0.6 0.9 4.4 1 +theRegisters/i_1_0_716/A3->ZN + NAND4_X4_LVT rf 239.7 15.4 15.4 0.0 34.6 0.9 3.1 1 +theRegisters/i_1_0_715/A->ZN + AOI221_X2_LVT fr 297.1 57.4 57.4 0.0 6.8 0.9 4.3 1 +theRegisters/i_1_0_704/A2->ZN + NAND4_X4_LVT rf 317.6 20.5 20.5 0.0 34.4 5.9 16.7 3 +theDecoder/i_0_133/C2->ZN + AOI222_X4_LVT fr 428.1 110.5 110.5 0.0 12.2 0.8 23.5 1 +theDecoder/i_0_132/A->ZN INV_X32_LVT rf 431.2 3.1 3.1 0.0 10.9 5.4 65.3 7 +theDecoder/theALU/i_0_706/B1->ZN + OAI22_X4_LVT* fr 474.4 43.2 43.2 0.0 1.4 1.5 25.9 2 +theDecoder/theALU/i_0_705/A->ZN + INV_X8_LVT rf 476.5 2.2 2.2 0.0 10.2 0.6 4.2 1 +theDecoder/theALU/i_0_42/A->ZN + OAI21_X2_LVT fr 485.6 9.1 9.1 0.0 0.6 0.8 2.5 1 +theDecoder/theALU/i_0_40/C1->ZN + AOI211_X2_LVT rf 491.3 5.6 5.6 0.0 11.6 0.8 2.9 1 +theDecoder/theALU/i_0_39/B->ZN + AOI211_X2_LVT fr 538.7 47.4 47.4 0.0 3.3 0.9 3.0 1 +theDecoder/theALU/i_0_38/B2->ZN + OAI222_X2_LVT rf 555.7 16.9 16.9 0.0 27.7 0.9 2.9 1 +theDecoder/theALU/i_0_37/C2->ZN + AOI221_X2_LVT fr 599.5 43.8 43.8 0.0 8.4 0.9 4.2 1 +theDecoder/theALU/i_0_35/B1->ZN + OAI22_X4_LVT* rf 613.4 13.9 13.9 0.0 34.0 0.7 23.4 1 +theDecoder/theALU/i_0_34/A->ZN + INV_X8_LVT fr 617.9 4.5 4.5 0.0 10.2 0.6 4.1 1 +theDecoder/theALU/i_0_33/A->ZN + AOI21_X4_LVT rf 620.5 2.6 2.6 0.0 2.4 0.8 3.0 1 +theDecoder/theALU/i_0_32/C2->ZN + OAI222_X2_LVT fr 659.0 38.5 38.5 0.0 2.6 0.9 3.3 1 +theDecoder/theALU/i_0_31/A->ZN + OAI221_X2_LVT rf 675.0 16.0 16.0 0.0 29.2 0.8 4.0 1 +theDecoder/theALU/i_0_28/B1->ZN + AOI21_X4_LVT fr 690.5 15.5 15.5 0.0 8.2 0.8 3.0 1 +theDecoder/theALU/i_0_27/A->ZN + AOI221_X2_LVT rf 694.7 4.2 4.2 0.0 13.5 0.9 2.9 1 +theDecoder/theALU/i_0_26/B->ZN + AOI211_X2_LVT fr 746.9 52.2 52.2 0.0 5.3 0.8 4.6 1 +theDecoder/theALU/i_0_25/B2->ZN + OAI22_X2_LVT rf 756.6 9.7 9.7 0.0 31.8 0.8 2.7 1 +theDecoder/theALU/i_0_24/C2->ZN + AOI211_X2_LVT fr 791.0 34.4 34.4 0.0 4.0 0.9 3.1 1 +theDecoder/theALU/i_0_23/A->ZN + AOI221_X2_LVT rf 796.7 5.8 5.8 0.0 27.8 0.9 3.1 1 +theDecoder/theALU/i_0_22/A->ZN + AOI221_X2_LVT fr 850.4 53.7 53.7 0.0 5.4 0.9 3.1 1 +theDecoder/theALU/i_0_21/A->ZN + AOI221_X2_LVT rf 856.5 6.1 6.1 0.0 31.2 0.9 3.1 1 +theDecoder/theALU/i_0_20/C2->ZN + OAI222_X2_LVT fr 895.2 38.8 38.8 0.0 5.4 0.9 3.3 1 +theDecoder/theALU/i_0_19/A->ZN + OAI221_X2_LVT rf 911.8 16.6 16.6 0.0 29.2 0.9 4.7 1 +theDecoder/theALU/i_0_18/B2->ZN + AOI22_X4_LVT fr 942.1 30.3 30.3 0.0 8.6 0.8 4.4 1 +theDecoder/theALU/i_0_17/B2->ZN + OAI21_X4_LVT rf 948.5 6.4 6.4 0.0 16.9 0.7 4.3 1 +theDecoder/theALU/i_0_16/A->ZN + OAI21_X4_LVT fr 958.3 9.8 9.8 0.0 3.6 0.7 3.9 1 +theDecoder/theALU/i_0_13/B1->ZN + AOI21_X4_LVT rf 963.5 5.3 5.3 0.0 12.5 0.8 4.4 1 +theDecoder/theALU/i_0_12/A4->ZN + NOR4_X2_LVT fr 1020.0 56.5 56.5 0.0 2.9 0.8 2.8 1 +theDecoder/theALU/i_0_0/A3->ZN + OR3_X4_LVT rr 1036.6 16.6 16.6 0.0 29.1 0.7 14.7 2 +theDecoder/i_0_114/B->ZN XNOR2_X2_LVT rf 1043.2 6.5 6.5 0.0 7.8 0.7 4.3 1 +theDecoder/i_0_113/B1->ZN + AOI22_X4_LVT fr 1069.7 26.5 26.5 0.0 5.1 0.8 4.4 1 +theDecoder/i_0_111/A2->ZN + AOI22_X4_LVT rf 1076.1 6.4 6.4 0.0 16.9 0.7 4.3 1 +theDecoder/i_0_110/A2->ZN + NAND2_X4_LVT* fr 1095.3 19.2 19.2 0.0 4.4 9.0 37.6 13 +i_0_1_63/S->Z MUX2_X2_LVT* rf 1161.7 66.4 66.4 0.0 10.2 11.1 66.7 3 +theMem/i_0_0_11/B2->ZN AOI22_X4_LVT* fr 1209.5 47.8 47.8 0.0 10.2 0.7 23.4 1 +theMem/i_0_0_10/A->ZN INV_X8_LVT rf 1211.5 2.0 2.0 0.0 10.2 0.8 1.8 1 +theMem/mem_addr_reg[5]/D SDFF_X1_LVT f 1211.5 0.0 0.0 0.5 +-------------------------------------------------------------------------------------------------------------------------------------- +Report for group I2R +-------------------------------------------------------------------------------------------------------------------------------------- +Startpoint: scan_en + (Clocked by rtDefaultClock R) +Endpoint: clk12p5_reg/D + (Clocked by clk_25mhz R) +Path Group: I2R +Data required time: 39223.7 + (Clock shift: 40000.0, minus Uncertainty: 500.0, plus Latency 0.0, minus Setup time: 276.3) +Data arrival time: 46.0 +Slack: 39177.7 +Logic depth: 2 +-------------------------------------------------------------------------------------------------------------------------------------- + Arrival Arc Net Net Total fan- +Path Module/Cell Edge Time Delay Delay Delay Slew Load Load out Location + (ps) (ps) (ps) (ps) (ps) (ff) (ff) (#) (um,um) +-------------------------------------------------------------------------------------------------------------------------------------- +scan_en {input_arrival} f 0.0 0.0 0.0 6.9 12.6 2 +i_0_1_1/A2->ZN NAND2_X4_LVT fr 7.0 7.0 7.0 0.0 0.0 0.7 2.8 1 +clk12p5_reg_enable_mux_0/S->Z + MUX2_X1_LVT rf 46.0 38.9 38.9 0.0 4.9 0.8 1.9 1 +clk12p5_reg/D SDFF_X1_LVT f 46.0 0.0 0.0 6.6 +-------------------------------------------------------------------------------------------------------------------------------------- +Report for group I2O +Report for group R2O +-------------------------------------------------------------------------------------------------------------------------------------- +Startpoint: theMem/IRData_reg[18]/Q + (Clocked by clk_25mhz R) +Endpoint: led[7] + (Clocked by clk_25mhz R) +Path Group: R2O +Data required time: 37500.0 + (Clock shift: 40000.0, minus Uncertainty: 500.0, plus Latency 0.0, minus Out delay: 2000.0) +Data arrival time: 1161.7 +Slack: 36338.3 +Logic depth: 44 +-------------------------------------------------------------------------------------------------------------------------------------- + Arrival Arc Net Net Total fan- +Path Module/Cell Edge Time Delay Delay Delay Slew Load Load out Location + (ps) (ps) (ps) (ps) (ps) (ff) (ff) (#) (um,um) +-------------------------------------------------------------------------------------------------------------------------------------- +clk_25mhz {create_clock} r 0.0 0.0 0.0 0.0 0.0 2 +i_0_1_2/B->Z MUX2_X2_LVT rr 0.0 0.0 0.0 0.0 100.0 0.0 0.0 100 +theMem/IRData_reg[18]/CK->Q + SDFF_X1_LVT* rr 84.9 84.9 84.9 0.0 100.0 10.6 73.4 11 +theRegisters/i_1_0_1371/A->ZN + INV_X8_LVT rf 87.6 2.7 2.7 0.0 10.2 2.1 13.2 3 +theRegisters/i_1_0_1339/A2->ZN + NAND3_X4_LVT fr 101.6 14.0 14.0 0.0 1.0 2.5 17.5 4 +theRegisters/i_1_0_1321/A2->ZN + NOR2_X4_LVT* rf 120.6 19.0 19.0 0.0 12.1 29.7 130.1 32 +theRegisters/i_1_0_722/B1->ZN + AOI22_X4_LVT* fr 164.9 44.3 44.3 0.0 10.2 0.7 23.4 1 +theRegisters/i_1_0_721/A->ZN + INV_X8_LVT rf 167.0 2.1 2.1 0.0 10.2 0.8 3.0 1 +theRegisters/i_1_0_718/A->ZN + AOI221_X2_LVT fr 224.3 57.3 57.3 0.0 0.6 0.9 4.4 1 +theRegisters/i_1_0_716/A3->ZN + NAND4_X4_LVT rf 239.7 15.4 15.4 0.0 34.6 0.9 3.1 1 +theRegisters/i_1_0_715/A->ZN + AOI221_X2_LVT fr 297.1 57.4 57.4 0.0 6.8 0.9 4.3 1 +theRegisters/i_1_0_704/A2->ZN + NAND4_X4_LVT rf 317.6 20.5 20.5 0.0 34.4 5.9 16.7 3 +theDecoder/i_0_133/C2->ZN + AOI222_X4_LVT fr 428.1 110.5 110.5 0.0 12.2 0.8 23.5 1 +theDecoder/i_0_132/A->ZN INV_X32_LVT rf 431.2 3.1 3.1 0.0 10.9 5.4 65.3 7 +theDecoder/theALU/i_0_706/B1->ZN + OAI22_X4_LVT* fr 474.4 43.2 43.2 0.0 1.4 1.5 25.9 2 +theDecoder/theALU/i_0_705/A->ZN + INV_X8_LVT rf 476.5 2.2 2.2 0.0 10.2 0.6 4.2 1 +theDecoder/theALU/i_0_42/A->ZN + OAI21_X2_LVT fr 485.6 9.1 9.1 0.0 0.6 0.8 2.5 1 +theDecoder/theALU/i_0_40/C1->ZN + AOI211_X2_LVT rf 491.3 5.6 5.6 0.0 11.6 0.8 2.9 1 +theDecoder/theALU/i_0_39/B->ZN + AOI211_X2_LVT fr 538.7 47.4 47.4 0.0 3.3 0.9 3.0 1 +theDecoder/theALU/i_0_38/B2->ZN + OAI222_X2_LVT rf 555.7 16.9 16.9 0.0 27.7 0.9 2.9 1 +theDecoder/theALU/i_0_37/C2->ZN + AOI221_X2_LVT fr 599.5 43.8 43.8 0.0 8.4 0.9 4.2 1 +theDecoder/theALU/i_0_35/B1->ZN + OAI22_X4_LVT* rf 613.4 13.9 13.9 0.0 34.0 0.7 23.4 1 +theDecoder/theALU/i_0_34/A->ZN + INV_X8_LVT fr 617.9 4.5 4.5 0.0 10.2 0.6 4.1 1 +theDecoder/theALU/i_0_33/A->ZN + AOI21_X4_LVT rf 620.5 2.6 2.6 0.0 2.4 0.8 3.0 1 +theDecoder/theALU/i_0_32/C2->ZN + OAI222_X2_LVT fr 659.0 38.5 38.5 0.0 2.6 0.9 3.3 1 +theDecoder/theALU/i_0_31/A->ZN + OAI221_X2_LVT rf 675.0 16.0 16.0 0.0 29.2 0.8 4.0 1 +theDecoder/theALU/i_0_28/B1->ZN + AOI21_X4_LVT fr 690.5 15.5 15.5 0.0 8.2 0.8 3.0 1 +theDecoder/theALU/i_0_27/A->ZN + AOI221_X2_LVT rf 694.7 4.2 4.2 0.0 13.5 0.9 2.9 1 +theDecoder/theALU/i_0_26/B->ZN + AOI211_X2_LVT fr 746.9 52.2 52.2 0.0 5.3 0.8 4.6 1 +theDecoder/theALU/i_0_25/B2->ZN + OAI22_X2_LVT rf 756.6 9.7 9.7 0.0 31.8 0.8 2.7 1 +theDecoder/theALU/i_0_24/C2->ZN + AOI211_X2_LVT fr 791.0 34.4 34.4 0.0 4.0 0.9 3.1 1 +theDecoder/theALU/i_0_23/A->ZN + AOI221_X2_LVT rf 796.7 5.8 5.8 0.0 27.8 0.9 3.1 1 +theDecoder/theALU/i_0_22/A->ZN + AOI221_X2_LVT fr 850.4 53.7 53.7 0.0 5.4 0.9 3.1 1 +theDecoder/theALU/i_0_21/A->ZN + AOI221_X2_LVT rf 856.5 6.1 6.1 0.0 31.2 0.9 3.1 1 +theDecoder/theALU/i_0_20/C2->ZN + OAI222_X2_LVT fr 895.2 38.8 38.8 0.0 5.4 0.9 3.3 1 +theDecoder/theALU/i_0_19/A->ZN + OAI221_X2_LVT rf 911.8 16.6 16.6 0.0 29.2 0.9 4.7 1 +theDecoder/theALU/i_0_18/B2->ZN + AOI22_X4_LVT fr 942.1 30.3 30.3 0.0 8.6 0.8 4.4 1 +theDecoder/theALU/i_0_17/B2->ZN + OAI21_X4_LVT rf 948.5 6.4 6.4 0.0 16.9 0.7 4.3 1 +theDecoder/theALU/i_0_16/A->ZN + OAI21_X4_LVT fr 958.3 9.8 9.8 0.0 3.6 0.7 3.9 1 +theDecoder/theALU/i_0_13/B1->ZN + AOI21_X4_LVT rf 963.5 5.3 5.3 0.0 12.5 0.8 4.4 1 +theDecoder/theALU/i_0_12/A4->ZN + NOR4_X2_LVT fr 1020.0 56.5 56.5 0.0 2.9 0.8 2.8 1 +theDecoder/theALU/i_0_0/A3->ZN + OR3_X4_LVT rr 1036.6 16.6 16.6 0.0 29.1 0.7 14.7 2 +theDecoder/i_0_114/B->ZN XNOR2_X2_LVT rf 1043.2 6.5 6.5 0.0 7.8 0.7 4.3 1 +theDecoder/i_0_113/B1->ZN + AOI22_X4_LVT fr 1069.7 26.5 26.5 0.0 5.1 0.8 4.4 1 +theDecoder/i_0_111/A2->ZN + AOI22_X4_LVT rf 1076.1 6.4 6.4 0.0 16.9 0.7 4.3 1 +theDecoder/i_0_110/A2->ZN + NAND2_X4_LVT* fr 1095.3 19.2 19.2 0.0 4.4 9.0 37.6 13 +i_0_1_63/S->Z MUX2_X2_LVT* rf 1161.7 66.4 66.4 0.0 10.2 11.1 66.7 3 +led[7] f 1161.7 0.0 0.0 10.2 +-------------------------------------------------------------------------------------------------------------------------------------- +> report_path_groups +Report Path Groups: +-----+-------+------+---------+--------- + | Path |Weight|Critical |Worst + | Group | |Range(ps)|Slack(ps) +-----+-------+------+---------+--------- +1 |default| 1.000| 0.0| 18015.8 +2 |I2R | 1.000| 0.0| 39177.7 +3 |I2O | 1.000| 0.0| +4 |R2O | 1.000| 0.0| 36338.3 +-----+-------+------+---------+--------- + +------------------------------------- + +Synthesis and optimization complete + +------------------------------------- + +INFO::Running oasys Tessent DFT flow +> source scripts_risc_v/oasys_tessent_dft.tcl +INFO::using /applications/SiemensEDA/siemenseda2023/tessent/bin/tessent build to run the Tessent DFT flow +> config_tessent -exec_path /applications/SiemensEDA/siemenseda2023/tessent/bin/tessent +> define_test_clock -pin clk_25mhz +> define_test_pin -pin scan_en -scan_mode 1 -default_scan_enable +> set_dont_scan theMem true +> define_test_pin -name reset -pin {btn[0]} -scan_mode 1 +> set_dont_scan clk12p5_reg true +invalid command name "add_input_constraints" + while executing +"add_input_constraints scan_en -C1" + (file "scripts_risc_v/oasys_tessent_dft.tcl" line 43) + invoked from within +"tcl_source scripts_risc_v/oasys_tessent_dft.tcl" +invalid command name "add_input_constraints" + while executing +"add_input_constraints scan_en -C1" + (file "scripts_risc_v/oasys_tessent_dft.tcl" line 43) + invoked from within +"tcl_source scripts_risc_v/oasys_tessent_dft.tcl" + ("uplevel" body line 1) + invoked from within +"uplevel 2 [list tcl_source $resolvedFilePath]" + (procedure "rt::sourceFile" line 31) + invoked from within +"rt::sourceFile false false {} scripts_risc_v/oasys_tessent_dft.tcl" + ("eval" body line 1) + invoked from within +"eval $cmd" + invoked from within +"source scripts_risc_v/oasys_tessent_dft.tcl" + invoked from within +"if {[info exists dft_flow] && [string match $dft_flow tessent]} { + puts "INFO::Running oasys Tessent DFT flow" + source scripts_risc_v/oasys_tessent_..." + (file "scripts_risc_v/2_synthesize_optimize.tcl" line 97) + invoked from within +"tcl_source scripts_risc_v/2_synthesize_optimize.tcl" diff --git a/riscv_rtl/hw/rtl/oasys.log.02 b/riscv_rtl/hw/rtl/oasys.log.02 new file mode 100644 index 0000000..f6ba516 --- /dev/null +++ b/riscv_rtl/hw/rtl/oasys.log.02 @@ -0,0 +1,16 @@ +******************************************************************* +* Oasys-RTL™ - release 2022.2.R1 * +* * +* This material contains trade secrets or otherwise confidential * +* information owned by Siemens Industry Software Inc. or its * +* affiliates (collectively, "SISW"), or its licensors. Access to * +* and use of this information is strictly limited as set forth * +* in the Customer’s applicable agreements with SISW. * +* * +* Unpublished work. © 2023 Siemens * +* * +* Program : ../bin/Linux-x86_64-O/oasysGui * +* Version : 22.2-p002 * +* Date : Mon Jan 16 21:36:23 PST 2023 * +* Build : releases/22.2-54756.0-CentOS_6.5-O * +******************************************************************* diff --git a/riscv_rtl/hw/rtl/pc.sv b/riscv_rtl/hw/rtl/pc.sv new file mode 100644 index 0000000..cfbb55c --- /dev/null +++ b/riscv_rtl/hw/rtl/pc.sv @@ -0,0 +1,37 @@ +// ********************************************************************************************* +// Project Version : v1.0 +// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog +// ----- +// Copyright (c) : 2025 Fraunhofer IIS, Department IDS +// Created : 12.Jun.2025 by Lund University [commit 5b1e415] +// Last Modified : 23.Oct.2025 by Bomin Kim [commit 2f8f03d] +// ----- +// HISTORY : Date By Comments +// ----------- --------- ------------------------------------------------- +// 15.Oct.2025 Bomin Kim Moved NextPC logic from decoder into PC +// 15.Oct.2025 Bomin Kim Removed reset condition from combinational logic +// ********************************************************************************************* + + +module pc ( + output logic[31:0] CurrentPC, + input logic[31:0] JumpOrBranchPC, + input logic JumpOrBranch, + output logic[31:0] NextPC, + input logic reset, + input logic clk +); + + // NextPC logic; next-state function + always_comb begin : Next_PC + if (JumpOrBranch) NextPC = JumpOrBranchPC; + else NextPC = CurrentPC + 4; + end + + // CurrentPC logic; state register + always_ff @(posedge clk) begin + if (reset) CurrentPC <= '0; + else CurrentPC <= NextPC; + end + +endmodule diff --git a/riscv_rtl/hw/rtl/reg_file.sv b/riscv_rtl/hw/rtl/reg_file.sv new file mode 100644 index 0000000..9985ba1 --- /dev/null +++ b/riscv_rtl/hw/rtl/reg_file.sv @@ -0,0 +1,44 @@ +// ********************************************************************************************* +// Project Version : v1.0 +// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog +// ----- +// Copyright (c) : 2025 Fraunhofer IIS, Department IDS +// Created : 12.Jun.2025 by Lund University [commit 5b1e415] +// Last Modified : 23.Oct.2025 by Bomin Kim [commit 2f8f03d] +// ----- +// HISTORY : Date By Comments +// ----------- --------- ------------------------------------------------- +// 15.Oct.2025 Bomin Kim Added reset handling condition +// ********************************************************************************************* + + +module reg_file ( + input logic[4:0] Rs1, + input logic[4:0] Rs2, + input logic[4:0] Rd, + output logic[31:0] RRs1, + output logic[31:0] RRs2, + input logic[31:0] WRd, + input logic WrReg, + input logic reset, + input logic clk +); + + // Define the registers array + logic[31:0] registers[31:1]; + + // Register file reading + assign RRs1 = Rs1 == 0 ? '0 : registers[Rs1]; + assign RRs2 = Rs2 == 0 ? '0 : registers[Rs2]; + + // Register file writing + always_ff @(posedge clk) begin + if (reset) begin + for (int i=1; i<32; i++) + registers[i] <= '0; + end else begin + if (WrReg & Rd != 0) registers[Rd] <= WRd; + end + end + +endmodule diff --git a/riscv_rtl/rtl_flist.f b/riscv_rtl/rtl_flist.f new file mode 100644 index 0000000..ddc017f --- /dev/null +++ b/riscv_rtl/rtl_flist.f @@ -0,0 +1,18 @@ +// ********************************************************************************************* +// Project Version : v1.0 +// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog +// ----- +// Copyright (c) : 2025 Fraunhofer IIS, Department IDS +// Created : 12.Aug.2025 by Marcus Bednara +// Last Modified : 01.Nov.2025 by Hussein Elzomor +// ------ +// Notes : All ${}-variables must be provided by shell or Makefile {using export} +// ********************************************************************************************* + +hw/rtl/pc.sv +hw/rtl/reg_file.sv +hw/rtl/alu.sv +hw/rtl/MemGen_32_11.sv +hw/rtl/main_mem.sv +hw/rtl/decoder.sv +hw/rtl/cpu.sv diff --git a/riscv_rtl/run.do b/riscv_rtl/run.do new file mode 100644 index 0000000..d99cc8f --- /dev/null +++ b/riscv_rtl/run.do @@ -0,0 +1,17 @@ +if [file exists "work"] {vdel -all} +vlib work + +# Comment out either the SystemVerilog or VHDL DUT. +# There can be only one! + +# VHDL DUT +#vcom -f rtl_flist.f + +vlog -sv dummz_memgen_16.sv + +# SystemVerilog DUT +vlog -sv -lint -pedanticerrors -f rtl_flist.f + +vopt work.cpu -o cpu_opt +acc -pedanticerrors + +quit diff --git a/riscv_rtl/sw/risc-v/decoder/decoder.hex b/riscv_rtl/sw/risc-v/decoder/decoder.hex new file mode 100644 index 0000000..11f9681 --- /dev/null +++ b/riscv_rtl/sw/risc-v/decoder/decoder.hex @@ -0,0 +1,37 @@ +001080B3 +40210133 +0031C1B3 +00426233 +0052F2B3 +00631333 +0073D3B3 +40845433 +0094A4B3 +00A53533 +00B58593 +00C64613 +00D6E693 +00E77713 +00F79793 +01085813 +4118D893 +01292913 +0139B993 +014A0A03 +015A9A83 +016B2B03 +017BCB83 +018C5C03 +019C8CA3 +01AD1D23 +01BDADA3 +01CE0E63 +01CE1E63 +01EF4F63 +01EF5F63 +00216163 +00217163 +0040026F +00420267 +000052B7 +00006317 diff --git a/riscv_rtl/sw/risc-v/decoder/decoder.s b/riscv_rtl/sw/risc-v/decoder/decoder.s new file mode 100644 index 0000000..c948b5e --- /dev/null +++ b/riscv_rtl/sw/risc-v/decoder/decoder.s @@ -0,0 +1,65 @@ +// ********************************************************************************************* +// Description : Assembly instructions for decoder test +// Project Version : v1.0 +// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog +// ----- +// Copyright (c) : 2025 Fraunhofer IIS, Department IDS +// Created : 15.Oct.2025 by Hussein Elzomor +// Last Modified : 15.Oct.2025 by Hussein Elzomor +// ----- +// HISTORY : Date By Comments +// ----------- --------- ------------------------------------------------- +// ********************************************************************************************* + + + +# Iteration over all implemented instructions to test decoder + +# R-instruction # Hex # bin f7 rs2 rs1 f3 rd opcode + add x1 , x1 , x1 # 0x001080B3 # 0b 0000000 00001 00001 000 00001 0110011 + sub x2 , x2 , x2 # 0x40210133 # 0b 0100000 00010 00010 000 00010 0110011 + xor x3 , x3 , x3 # 0x0031C1B3 # 0b 0000000 00011 00011 100 00011 0110011 + or x4 , x4 , x4 # 0x00426233 # 0b 0000000 00100 00100 110 00100 0110011 + and x5 , x5 , x5 # 0x0052F2B3 # 0b 0000000 00101 00101 111 00101 0110011 + sll x6 , x6 , x6 # 0x00631333 # 0b 0000000 00110 00110 001 00110 0110011 + srl x7 , x7 , x7 # 0x0073D3B3 # 0b 0000000 00111 00111 101 00111 0110011 + sra x8 , x8 , x8 # 0x40845433 # 0b 0100000 01000 01000 101 01000 0110011 + slt x9 , x9 , x9 # 0x0094A4B3 # 0b 0000000 01001 01001 010 01001 0110011 + sltu x10, x10, x10 # 0x00A53533 # 0b 0000000 01010 01010 011 01010 0110011 + +# I-instruction # Hex # bin imm rs1 f3 rd opcode + addi x11, x11, 11 # 0x00B58593 # 0b 000000001011 01011 000 01011 0010011 + xori x12, x12, 12 # 0x00C64613 # 0b 000000001100 01100 100 01100 0010011 + ori x13, x13, 13 # 0x00D6E693 # 0b 000000001101 01101 110 01101 0010011 + andi x14, x14, 14 # 0x00E77713 # 0b 000000001110 01110 111 01110 0010011 + slli x15, x15, 15 # 0x00F79793 # 0b 000000001111 01111 001 01111 0010011 + srli x16, x16, 16 # 0x01085813 # 0b 000000010000 10000 101 10000 0010011 + srai x17, x17, 17 # 0x4118D893 # 0b 010000010001 10001 101 10001 0010011 + slti x18, x18, 18 # 0x01292913 # 0b 000000010010 10010 010 10010 0010011 + sltiu x19, x19, 19 # 0x0139B993 # 0b 000000010011 10011 011 10011 0010011 + lb x20, 20(x20) # 0x014A0A03 # 0b 000000010100 10100 000 10100 0000011 + lh x21, 21(x21) # 0x015A9A83 # 0b 000000010101 10101 001 10101 0000011 + lw x22, 22(x22) # 0x016B2B03 # 0b 000000010110 10110 010 10110 0000011 + lbu x23, 23(x23) # 0x017BCB83 # 0b 000000010111 10111 100 10111 0000011 + lhu x24, 24(x24) # 0x018C5C03 # 0b 000000011000 11000 101 11000 0000011 + +# S-instruction # Hex # bin imm rs2 rs1 f3 imm opcode + sb x25, 25(x25) # 0x019C8CA3 # 0b 0000000 11001 11001 000 11001 0100011 + sh x26, 26(x26) # 0x01AD1D23 # 0b 0000000 11010 11010 001 11010 0100011 + sw x27, 27(x27) # 0x01BDADA3 # 0b 0000000 11011 11011 010 11011 0100011 + +# B-instruction # Hex # bin imm rs2 rs1 f3 imm opcode + beq x28, x28, 28 # 0x01CE0E63 # 0b 0000000 11100 11100 000 11100 1100011 + bne x28, x28, 28 # 0x01CE1E63 # 0b 0000000 11100 11100 001 11100 1100011 + blt x30, x30, 30 # 0x01EF4F63 # 0b 0000000 11110 11110 100 11110 1100011 + bge x30, x30, 30 # 0x01EF5F63 # 0b 0000000 11110 11110 101 11110 1100011 + bltu x2 , x2 , 2 # 0x00216163 # 0b 0000000 00010 00010 110 00010 1100011 + bgeu x2 , x2 , 2 # 0x00217163 # 0b 0000000 00010 00010 111 00010 1100011 + +# J-instruction # Hex # bin f7 rd opcode + jal x4 , 4 # 0x0040026F # 0b 00000000010000000000 00100 1101111 + jalr x4 , x4, 4 # 0x00420267 # 0b 00000000010000100000 00100 1100111 + +# U-instruction # Hex # bin f7 rd opcode + lui x5 , 5 # 0x000052B7 # 0b 00000000000000000101 00101 0110111 + auipc x6 , 6 # 0x00006317 # 0b 00000000000000000110 00110 0010111 diff --git a/riscv_rtl/sw/risc-v/fibonacci_series/fibonacci.c b/riscv_rtl/sw/risc-v/fibonacci_series/fibonacci.c new file mode 100644 index 0000000..4aa64ae --- /dev/null +++ b/riscv_rtl/sw/risc-v/fibonacci_series/fibonacci.c @@ -0,0 +1,29 @@ +// ********************************************************************************************* +// Description : C Program to calculate the Fibonacci numbers until a given number of terms +// File : v1.0 +// Project Version : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog +// Project : RISCV_IN3DAYS +// ----- +// Copyright (c) : 2025 Fraunhofer IIS, Department IDS +// Created : 13.Oct.2025, 11:00:00 by Fuad Mammadzada (fuad.mammadzada@fau.de) +// ----- +// HISTORY : Date By Comments +// ----------- --------- ------------------------------------------------- +// ********************************************************************************************* + + +asm(".global _start, halt; _start: lui sp 2; addi sp sp -4; jal x0 main"); + +int main() { + int n = 10; // count of Fibonacci numbers to be evaluated + + int fib_number[20]; + fib_number[0] = 0; + fib_number[1] = 1; + + for (int i = 2; i < n; i++) { + fib_number[i] = fib_number[i-1] + fib_number[i-2]; + } + + asm("j halt"); +} diff --git a/riscv_rtl/sw/risc-v/fibonacci_series/fibonacci.hex b/riscv_rtl/sw/risc-v/fibonacci_series/fibonacci.hex new file mode 100644 index 0000000..ee47b35 --- /dev/null +++ b/riscv_rtl/sw/risc-v/fibonacci_series/fibonacci.hex @@ -0,0 +1,16 @@ +00002137 +FFC10113 +0080006F +0000006F +FB010113 +00100513 +00810593 +00012023 +00A12223 +02810613 +FF85A683 +00A68533 +00A5A023 +00458593 +FEC598E3 +FD1FF06F diff --git a/riscv_rtl/sw/risc-v/fibonacci_series/fibonacci.s b/riscv_rtl/sw/risc-v/fibonacci_series/fibonacci.s new file mode 100644 index 0000000..8eece47 --- /dev/null +++ b/riscv_rtl/sw/risc-v/fibonacci_series/fibonacci.s @@ -0,0 +1,38 @@ +// ********************************************************************************************* +// Description : Assembly instructions for fibonacci program +// Project Version : v1.0 +// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog +// ----- +// Copyright (c) : 2025 Fraunhofer IIS, Department IDS +// Created : 15.Oct.2025 by Fuad Mammadzada +// Last Modified : 21.Oct.2025 by Fuad Mammadzada +// ----- +// HISTORY : Date By Comments +// ----------- --------- ------------------------------------------------- +// ********************************************************************************************* + + + +# Instruction # Hex code # MemAddr(PC) # Corresponding C code & explanation +_start: + lui sp, 2 # 0x00002137 # 0x00000000 # Initialize stack pointer value to size of memory (0x00002000) + addi sp, sp -4 # 0xFFC10113 # 0x00000004 # Subtract stack pointer value by 4 to point to the last memory address (0x00001FFC) + jal x0, main # 0x0080006F # 0x00000008 # Jump to main without saving the return address +halt: + jal x0, halt # 0x0000006F # 0x0000000C # Halt the program (infinite loop) + +main: # -------- # fibonacci.c:17: int main() { + addi sp, sp, -80 # 0xFB010113 # 0x00000010 # fibonacci.c:20: int fib_number[20]; (allocate 20*4B from the stack) + addi a0, x0, 1 # 0x00100513 # 0x00000014 # a0 = 0 + 1 (this is later used in fibonacci.c:22) + addi a1, sp, 8 # 0x00810593 # 0x00000018 # calculate and save the address of fib_number[2] + sw x0, 0(sp) # 0x00012023 # 0x0000001C # fibonacci.c:21: fib_number[0] = x0 = 0 + sw a0, 4(sp) # 0x00A12223 # 0x00000020 # fibonacci.c:22: fib_number[1] = a0 = 1 + addi a2, sp, 40 # 0x02810613 # 0x00000024 # fibonacci.c:24: calculate the last array index for the loop condition (since n=10, n*4B) + +.for_loop: + lw a3, -8(a1) # 0xFF85A683 # 0x00000028 # fibonacci.c:25: a3 = fib_number[i-2] + add a0, a3, a0 # 0x00A68533 # 0x0000002C # fibonacci.c:25: a0 = fib_number[i-1] + fib_number[i-2] + sw a0, 0(a1) # 0x00A5A023 # 0x00000030 # fibonacci.c:25: fib_number[i] = a0 + addi a1, a1, 4 # 0x00458593 # 0x00000034 # fibonacci.c:24: i++ + bne a1, a2, .for_loop # 0xFEC598E3 # 0x00000038 # fibonacci.c:24: loop back if i != n + jal x0, halt # 0xFD1FF06F # 0x0000003C # fibonacci.c:28: asm("j halt"); diff --git a/riscv_rtl/sw/risc-v/hello_world/helloWorld.c b/riscv_rtl/sw/risc-v/hello_world/helloWorld.c new file mode 100644 index 0000000..01be8a2 --- /dev/null +++ b/riscv_rtl/sw/risc-v/hello_world/helloWorld.c @@ -0,0 +1,43 @@ +// ********************************************************************************************* +// Description : C Program to store the sentence 'hello world!' in a char array in memory +// Project Version : v1.0 +// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog +// ----- +// Copyright (c) : 2025 Fraunhofer IIS, Department IDS +// Created : 15.Oct.2025 by Hussein Elzomor +// Last Modified : 15.Oct.2025 by Hussein Elzomor +// ----- +// HISTORY : Date By Comments +// ----------- --------- ------------------------------------------------- +// ********************************************************************************************* + + + +asm(".global _start, halt; .set DataMem 0x1; _start: lui sp 0x2; addi sp sp -4; jal main;"); +// DataMem address usage is set manually in the assembly code after its generation. + +void storeChar(char c, char *location) +{ + *location = c; +} + +int main() +{ + static char mem[13]; + + storeChar('h', &mem[0]); + storeChar('e', &mem[1]); + storeChar('l', &mem[2]); + storeChar('l', &mem[3]); + storeChar('o', &mem[4]); + storeChar(' ', &mem[5]); + storeChar('w', &mem[6]); + storeChar('o', &mem[7]); + storeChar('r', &mem[8]); + storeChar('l', &mem[9]); + storeChar('d', &mem[10]); + storeChar('!', &mem[11]); + storeChar('\0', &mem[12]); // Don't forget the null terminator! + + return 0; // End the main function and return 0 on success +} diff --git a/riscv_rtl/sw/risc-v/hello_world/helloWorld.hex b/riscv_rtl/sw/risc-v/hello_world/helloWorld.hex new file mode 100644 index 0000000..42afe99 --- /dev/null +++ b/riscv_rtl/sw/risc-v/hello_world/helloWorld.hex @@ -0,0 +1,92 @@ +00002137 +FFC10113 +03C000EF +0000006F +FE010113 +00112E23 +00812C23 +02010413 +FEB42423 +FEA407A3 +FE842783 +FEF44703 +00E78023 +01C12083 +01812403 +02010113 +00008067 +FF010113 +00112623 +00812423 +01010413 +000015B7 +00058593 +06800513 +00000317 +FB0300E7 +000015B7 +00158593 +06500513 +00000317 +F9C300E7 +000015B7 +00258593 +06C00513 +00000317 +F88300E7 +000015B7 +00358593 +06C00513 +00000317 +F74300E7 +000015B7 +00458593 +06F00513 +00000317 +F60300E7 +000015B7 +00558593 +02000513 +00000317 +F4C300E7 +000015B7 +00658593 +07700513 +00000317 +F38300E7 +000015B7 +00758593 +06F00513 +00000317 +F24300E7 +000015B7 +00858593 +07200513 +00000317 +F10300E7 +000015B7 +00958593 +06C00513 +00000317 +EFC300E7 +000015B7 +00A58593 +06400513 +00000317 +EE8300E7 +000015B7 +00B58593 +02100513 +00000317 +ED4300E7 +000015B7 +00C58593 +00000513 +00000317 +EC0300E7 +00000793 +00078513 +00C12083 +00812403 +01010113 +00008067 diff --git a/riscv_rtl/sw/risc-v/hello_world/helloWorld.s b/riscv_rtl/sw/risc-v/hello_world/helloWorld.s new file mode 100644 index 0000000..1d691be --- /dev/null +++ b/riscv_rtl/sw/risc-v/hello_world/helloWorld.s @@ -0,0 +1,121 @@ +// ********************************************************************************************* +// Description : Assembly instructions for hello world program +// Project Version : v1.0 +// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog +// ----- +// Copyright (c) : 2025 Fraunhofer IIS, Department IDS +// Created : 15.Oct.2025 by Hussein Elzomor +// Last Modified : 21.Oct.2025 by Hussein Elzomor +// ----- +// HISTORY : Date By Comments +// ----------- --------- ------------------------------------------------- +// ********************************************************************************************* + + + +# GNU C++17 (crosstool-NG UNKNOWN) version 15.2.0 (riscv32-unknown-linux-gnu) +# compiled by GNU C version 16.0.0 20250802 (experimental), GMP version 6.3.0, MPFR version 4.2.1, MPC version 1.3.1, isl version isl-0.24-GMP + +# GGC heuristics: --param ggc-min-expand=100 --param ggc-min-heapsize=131072 +# options passed: -mabi=ilp32d -misa-spec=20191213 -mtls-dialect=trad -march=rv32ifd_zicsr -g + .set DataMem,0x1 # Start of Data Memory 0x1000 (translates to 0x400 due to 4 bytes adressing system) +_start: + lui sp, 0x2 # Initialize stack pointer value to size of memory (0x00002000) + addi sp, sp -4 # Subtract stack pointer value by 4 to point to the last memory address (0x00001FFC) + jal main # Jump to main and save return address to ra +halt: + j halt # Get stuck here in a loop forever +storeChar: + addi sp,sp,-32 # Reserve some space on the stack + sw ra,28(sp) # Save the return address on the stack + sw s0,24(sp) # Save the caller frame pointer value on the stack + addi s0,sp,32 # Store the callee frame pointer value in s0 (end address of the stack frame) + sw a1,-24(s0) # arg1, location + sb a0,-17(s0) # arg0, c + # helloWorld.c:8: *location = c; + lw a5,-24(s0) # tmp136, location + lbu a4,-17(s0) # tmp137, c + sb a4,0(a5) # tmp137, *location_2(D) + # helloWorld.c:9: } + lw ra,28(sp) # Load the return address from the stack and store it in ra + lw s0,24(sp) # Load the caller frame pointer value from the stack and store it in s0 + addi sp,sp,32 # Free the allocated stack space for the function call + jr ra # Return to address stored in ra +main: + addi sp,sp,-16 # Reserve some space on the stack + sw ra,12(sp) # Save the return address on the stack + sw s0,8(sp) # Save the caller frame pointer value on the stack + addi s0,sp,16 # Store the callee frame pointer value in s0 (end address of the stack frame) + # helloWorld.c:15: storeChar('h', &mem[0]); + lui a1,DataMem # tmp136, DataMem + addi a1,a1,0 # arg1, tmp136 + 0 + li a0,104 # arg0, 'h' + call storeChar # + # helloWorld.c:16: storeChar('e', &mem[1]); + lui a1,DataMem # tmp137, DataMem + addi a1,a1,1 # arg1, tmp137 + 1 + li a0,101 # arg0, 'e' + call storeChar # + # helloWorld.c:17: storeChar('l', &mem[2]); + lui a1,DataMem # tmp138, DataMem + addi a1,a1,2 # arg1, tmp138 + 2 + li a0,108 # arg0, 'l' + call storeChar # + # helloWorld.c:18: storeChar('l', &mem[3]); + lui a1,DataMem # tmp139, DataMem + addi a1,a1,3 # arg1, tmp139 + 3 + li a0,108 # arg0, 'l' + call storeChar # + # helloWorld.c:19: storeChar('o', &mem[4]); + lui a1,DataMem # tmp140, DataMem + addi a1,a1,4 # arg1, tmp140 + 4 + li a0,111 # arg0, 'o' + call storeChar # + # helloWorld.c:20: storeChar(' ', &mem[5]); + lui a1,DataMem # tmp141, DataMem + addi a1,a1,5 # arg1, tmp141 + 5 + li a0,32 # arg0, ' ' + call storeChar # + # helloWorld.c:21: storeChar('w', &mem[6]); + lui a1,DataMem # tmp142, DataMem + addi a1,a1,6 # arg1, tmp142 + 6 + li a0,119 # arg0, 'w' + call storeChar # + # helloWorld.c:22: storeChar('o', &mem[7]); + lui a1,DataMem # tmp143, DataMem + addi a1,a1,7 # arg1, tmp143 + 7 + li a0,111 # arg0, 'o' + call storeChar # + # helloWorld.c:23: storeChar('r', &mem[8]); + lui a1,DataMem # tmp144, DataMem + addi a1,a1,8 # arg1, tmp144 + 8 + li a0,114 # arg0, 'r' + call storeChar # + # helloWorld.c:24: storeChar('l', &mem[9]); + lui a1,DataMem # tmp145, DataMem + addi a1,a1,9 # arg1, tmp145 + 9 + li a0,108 # arg0, 'l' + call storeChar # + # helloWorld.c:25: storeChar('d', &mem[10]); + lui a1,DataMem # tmp146, DataMem + addi a1,a1,10 # arg1, tmp146 + 10 + li a0,100 # arg0, 'd' + call storeChar # + # helloWorld.c:26: storeChar('!', &mem[11]); + lui a1,DataMem # tmp147, DataMem + addi a1,a1,11 # arg1, tmp147 + 11 + li a0,33 # arg0, '!' + call storeChar # + # helloWorld.c:27: storeChar('\0', &mem[12]); // Don't forget the null terminator! + lui a1,DataMem # tmp148, DataMem + addi a1,a1,12 # arg1, tmp148 + 12 + li a0,0 # arg0, '\0 + call storeChar # + # helloWorld.c:29: return 0; // End the main function and return 0 on success + li a5,0 # _16, + # helloWorld.c:30: } + mv a0,a5 #, + lw ra,12(sp) # Load the return address from the stack and store it in ra + lw s0,8(sp) # Load the caller frame pointer value from the stack and store it in s0 + addi sp,sp,16 # Free the allocated stack space for the function call + jr ra # Return to address stored in ra diff --git a/riscv_rtl/sw/risc-v/hello_world/helloWorld_simplified.s b/riscv_rtl/sw/risc-v/hello_world/helloWorld_simplified.s new file mode 100644 index 0000000..b2c0b12 --- /dev/null +++ b/riscv_rtl/sw/risc-v/hello_world/helloWorld_simplified.s @@ -0,0 +1,120 @@ +// ********************************************************************************************* +// Description : Simplified assembly instructions for hello world program +// Project Version : v1.0 +// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog +// ----- +// Copyright (c) : 2025 Fraunhofer IIS, Department IDS +// Created : 15.Oct.2025 by Hussein Elzomor +// Last Modified : 21.Oct.2025 by Hussein Elzomor +// ----- +// HISTORY : Date By Comments +// ----------- --------- ------------------------------------------------- +// ********************************************************************************************* + + + +# 1 to 1 mapping of the Hex instructions in helloWorld.hex +# Simplified version of helloWorld.s +## Replaced pseudo instructions with the proper rv32i instructions +## Replaced jumps to labels with address offset values + +# Use as a cross reference to identify: +## - the instruction being run on your processor +## - which part of the program is being run +## - confirm registers and memory addresses contain the correct data +_start: # Hex # MemAddr(PC) + lui x2 2 # 0x00002137 # 0x00000000 + addi x2 x2 -4 # 0xFFC10113 # 0x00000004 + jal x1 60 # 0x03C000EF # 0x00000008 +halt: + jal x0 0 # 0x0000006F # 0x0000000C +storeChar: + addi x2 x2 -32 # 0xFE010113 # 0x00000010 + sw x1 28(x2) # 0x00112E23 # 0x00000014 + sw x8 24(x2) # 0x00812C23 # 0x00000018 + addi x8 x2 32 # 0x02010413 # 0x0000001C + sw x11 -24(x8) # 0xFEB42423 # 0x00000020 + sb x10 -17(x8) # 0xFEA407A3 # 0x00000024 + lw x15 -24(x8) # 0xFE842783 # 0x00000028 + lbu x14 -17(x8) # 0xFEF44703 # 0x0000002C + sb x14 0(x15) # 0x00E78023 # 0x00000030 + lw x1 28(x2) # 0x01C12083 # 0x00000034 + lw x8 24(x2) # 0x01812403 # 0x00000038 + addi x2 x2 32 # 0x02010113 # 0x0000003C + jalr x0 x1 0 # 0x00008067 # 0x00000040 +main: + addi x2 x2 -16 # 0xFF010113 # 0x00000044 + sw x1 12(x2) # 0x00112623 # 0x00000048 + sw x8 8(x2) # 0x00812423 # 0x0000004C + addi x8 x2 16 # 0x01010413 # 0x00000050 + lui x11 1 # 0x000015B7 # 0x00000054 + addi x11 x11 0 # 0x00058593 # 0x00000058 + addi x10 x0 104 # 0x06800513 # 0x0000005C + auipc x6 0 # 0x00000317 # 0x00000060 + jalr x1 x6 -80 # 0xFB0300E7 # 0x00000064 + lui x11 1 # 0x000015B7 # 0x00000068 + addi x11 x11 1 # 0x00158593 # 0x0000006C + addi x10 x0 101 # 0x06500513 # 0x00000070 + auipc x6 0 # 0x00000317 # 0x00000074 + jalr x1 x6 -100 # 0xF9C300E7 # 0x00000078 + lui x11 1 # 0x000015B7 # 0x0000007C + addi x11 x11 2 # 0x00258593 # 0x00000080 + addi x10 x0 108 # 0x06C00513 # 0x00000084 + auipc x6 0 # 0x00000317 # 0x00000088 + jalr x1 x6 -120 # 0xF88300E7 # 0x0000008C + lui x11 1 # 0x000015B7 # 0x00000090 + addi x11 x11 3 # 0x00358593 # 0x00000094 + addi x10 x0 108 # 0x06C00513 # 0x00000098 + auipc x6 0 # 0x00000317 # 0x0000009C + jalr x1 x6 -140 # 0xF74300E7 # 0x000000A0 + lui x11 1 # 0x000015B7 # 0x000000A4 + addi x11 x11 4 # 0x00458593 # 0x000000A8 + addi x10 x0 111 # 0x06F00513 # 0x000000AC + auipc x6 0 # 0x00000317 # 0x000000B0 + jalr x1 x6 -160 # 0xF60300E7 # 0x000000B4 + lui x11 1 # 0x000015B7 # 0x000000B8 + addi x11 x11 5 # 0x00558593 # 0x000000BC + addi x10 x0 32 # 0x02000513 # 0x000000C0 + auipc x6 0 # 0x00000317 # 0x000000C4 + jalr x1 x6 -180 # 0xF4C300E7 # 0x000000C8 + lui x11 1 # 0x000015B7 # 0x000000CC + addi x11 x11 6 # 0x00658593 # 0x000000D0 + addi x10 x0 119 # 0x07700513 # 0x000000D4 + auipc x6 0 # 0x00000317 # 0x000000D8 + jalr x1 x6 -200 # 0xF38300E7 # 0x000000DC + lui x11 1 # 0x000015B7 # 0x000000E0 + addi x11 x11 7 # 0x00758593 # 0x000000E4 + addi x10 x0 111 # 0x06F00513 # 0x000000E8 + auipc x6 0 # 0x00000317 # 0x000000EC + jalr x1 x6 -220 # 0xF24300E7 # 0x000000F0 + lui x11 1 # 0x000015B7 # 0x000000F4 + addi x11 x11 8 # 0x00858593 # 0x000000F8 + addi x10 x0 114 # 0x07200513 # 0x000000FC + auipc x6 0 # 0x00000317 # 0x00000100 + jalr x1 x6 -240 # 0xF10300E7 # 0x00000104 + lui x11 1 # 0x000015B7 # 0x00000108 + addi x11 x11 9 # 0x00958593 # 0x0000010C + addi x10 x0 108 # 0x06C00513 # 0x00000110 + auipc x6 0 # 0x00000317 # 0x00000114 + jalr x1 x6 -260 # 0xEFC300E7 # 0x00000118 + lui x11 1 # 0x000015B7 # 0x0000011C + addi x11 x11 10 # 0x00A58593 # 0x00000120 + addi x10 x0 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********************************************************************************************* +// Description : C Program to find prime factors of a Number +// Project Version : v1.0 +// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog +// ----- +// Copyright (c) : 2025 Fraunhofer IIS, Department IDS +// Created : 15.Oct.2025 by Hussein Elzomor +// Last Modified : 15.Oct.2025 by Hussein Elzomor +// ----- +// HISTORY : Date By Comments +// ----------- --------- ------------------------------------------------- +// ********************************************************************************************* + + + +asm(".global _start, halt; _start: lui sp 0x2; addi sp sp -4; jal main"); + +int main() +{ + int i, iModulo, j, Number, NumberModulo, isPrime, Prime; // Create variables + Number = 39; // Set initial value for Number to be factorized + Prime = 0; // Set initial value for Prime to be printed + for (i = 2; i <= Number; i++) // Iterate over i from 2 to Number, all possible numbers excluding 1 & 0 + { + NumberModulo = Number; + while (NumberModulo > 0) // Calculate Number % i using subtraction and store in NumberModulo + { + NumberModulo -= i; + } + if (NumberModulo == 0) // If Number % i == 0, it is possible that it's a prime number + { + isPrime = 1; + for (j = 2; j <= i / 2; j++) // Iterate over j from 2 to i/2 + { + iModulo = i; + while (iModulo > 0) // Calculate i % j using subtraction and store in iModulo + { + iModulo -= j; + } + if (iModulo == 0) // If i % j == 0, it is not a prime number + { + isPrime = 0; + break; + } + } + if (isPrime == 1) // Print i if i is a prime number + { + Prime = i; // Set variable Prime to the prime number. Used for printing in the TB upon change + } + } + } + return 0; // End the main function and return 0 on success +} diff --git a/riscv_rtl/sw/risc-v/prime_factors/primeFactors.hex b/riscv_rtl/sw/risc-v/prime_factors/primeFactors.hex new file mode 100644 index 0000000..c642034 --- /dev/null +++ b/riscv_rtl/sw/risc-v/prime_factors/primeFactors.hex @@ -0,0 +1,71 @@ +00002137 +FFC10113 +008000EF +0000006F +FD010113 +02112623 +02812423 +03010413 +02700793 +00078813 +FCF42C23 +FC042A23 +00200793 +FEF42623 +0C00006F +FD842783 +FEF42023 +0140006F +FE042703 +FEC42783 +40F707B3 +FEF42023 +FE042783 +FEF046E3 +FE042783 +08079463 +00100793 +FCF42E23 +00200793 +FEF42223 +0440006F +FEC42783 +FEF42423 +0140006F +FE842703 +FE442783 +40F707B3 +FEF42423 +FE842783 +FEF046E3 +FE842783 +00079663 +FC042E23 +02C0006F +FE442783 +00178793 +FEF42223 +FEC42783 +01F7D713 +00F707B3 +4017D793 +00078713 +FE442783 +FAF754E3 +FDC42703 +00100793 +00F71663 +FEC42883 +FD142A23 +FEC42783 +00178793 +FEF42623 +FEC42703 +FD842783 +F2E7DEE3 +00000793 +00078513 +02C12083 +02812403 +03010113 +00008067 diff --git a/riscv_rtl/sw/risc-v/prime_factors/primeFactors.s b/riscv_rtl/sw/risc-v/prime_factors/primeFactors.s new file mode 100644 index 0000000..3cea1ef --- /dev/null +++ b/riscv_rtl/sw/risc-v/prime_factors/primeFactors.s @@ -0,0 +1,140 @@ +// ********************************************************************************************* +// Description : Assembly instructions for prime factors program +// Project Version : v1.0 +// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog +// ----- +// Copyright (c) : 2025 Fraunhofer IIS, Department IDS +// Created : 15.Oct.2025 by Hussein Elzomor +// Last Modified : 21.Oct.2025 by Hussein Elzomor +// ----- +// HISTORY : Date By Comments +// ----------- --------- ------------------------------------------------- +// ********************************************************************************************* + + + +# GNU C23 (crosstool-NG UNKNOWN) version 15.2.0 (riscv32-unknown-linux-gnu) +# compiled by GNU C version 16.0.0 20250802 (experimental), GMP version 6.3.0, MPFR version 4.2.1, MPC version 1.3.1, isl version isl-0.24-GMP + +# GGC heuristics: --param ggc-min-expand=100 --param ggc-min-heapsize=131072 +# options passed: -mabi=ilp32d -misa-spec=20191213 -mtls-dialect=trad -march=rv32imafdc_zicsr_zifencei_zmmul_zaamo_zalrsc_zca_zcd_zcf -g +_start: + lui sp, 0x2 # Initialize stack pointer value to size of memory (0x00002000) + addi sp, sp -4 # Subtract stack pointer value by 4 to point to the last memory address (0x00001FFC) + jal main # Jump to main and save return address to ra +halt: + j halt # Get stuck here in a loop forever +main: + addi sp,sp,-48 # Reserve some space on the stack + sw ra,44(sp) # Save the return address on the stack + sw s0,40(sp) # Save the caller frame pointer value on the stack + addi s0,sp,48 # Store the callee frame pointer value in s0 (end address of the stack frame) + # primeFactors.c:6: Number = 39; // Set initial value for Number to be factorized + li a5,39 # tmp137,39 # Change the Number (39) to different values to test the program + mv a6, a5 # ,tmp137 # Used for printing in the TB upon change + sw a5,-40(s0) # tmp137, Number + # primeFactors.c:7: Prime = 0; // Set initial value for Prime to be printed + sw zero,-44(s0) #, Prime +loop_i_init: + # primeFactors.c:8: for (i = 2; i <= Number; i++) // Iterate over i from 2 to Number, all possible numbers excluding 1 & 0 + li a5,2 # tmp138, + sw a5,-20(s0) # tmp138, i + # primeFactors.c:8: for (i = 2; i <= Number; i++) // Iterate over i from 2 to Number, all possible numbers excluding 1 & 0 + j loop_i_check # +num_mod_set: + # primeFactors.c:10: NumberModulo = Number; + lw a5,-40(s0) # tmp139, Number + sw a5,-32(s0) # tmp139, NumberModulo + # primeFactors.c:11: while (NumberModulo > 0) // Calculate Number % i using subtraction and store in NumberModulo + j num_mod_loop # +num_mod_sub_i: + # primeFactors.c:13: NumberModulo -= i; + lw a4,-32(s0) # tmp141, NumberModulo + lw a5,-20(s0) # tmp142, i + sub a5,a4,a5 # NumberModulo_21, tmp141, tmp142 + sw a5,-32(s0) # NumberModulo_21, NumberModulo +num_mod_loop: + # primeFactors.c:11: while (NumberModulo > 0) // Calculate Number % i using subtraction and store in NumberModulo + lw a5,-32(s0) # tmp143, NumberModulo + bgt a5,zero,num_mod_sub_i #, tmp143,, +num_mod_check: + # primeFactors.c:15: if (NumberModulo == 0) // If Number % i == 0, it is possible that it's a prime number + lw a5,-32(s0) # tmp144, NumberModulo + bne a5,zero,loop_i_inc #, tmp144,, + + # primeFactors.c:17: isPrime = 1; + li a5,1 # tmp145, + sw a5,-36(s0) # tmp145, isPrime +loop_j_init: + # primeFactors.c:18: for (j = 2; j <= i / 2; j++) // Iterate over j from 2 to i/2 + li a5,2 # tmp146, + sw a5,-28(s0) # tmp146, j + # primeFactors.c:18: for (j = 2; j <= i / 2; j++) // Iterate over j from 2 to i/2 + j loop_j_check # +i_mod_set: + # primeFactors.c:20: iModulo = i; + lw a5,-20(s0) # tmp147, i + sw a5,-24(s0) # tmp147, iModulo + # primeFactors.c:21: while (iModulo > 0) // Calculate i % j using subtraction and store in iModulo + j i_mod_loop # +i_mod_sub_j: + # primeFactors.c:23: iModulo -= j; + lw a4,-24(s0) # tmp149, iModulo + lw a5,-28(s0) # tmp150, j + sub a5,a4,a5 # iModulo_18, tmp149, tmp150 + sw a5,-24(s0) # iModulo_18, iModulo +i_mod_loop: + # primeFactors.c:21: while (iModulo > 0) // Calculate i % j using subtraction and store in iModulo + lw a5,-24(s0) # tmp151, iModulo + bgt a5,zero,i_mod_sub_j #, tmp151,, +i_mod_check: + # primeFactors.c:25: if (iModulo == 0) // If i % j == 0, it is not a prime number + lw a5,-24(s0) # tmp152, iModulo + bne a5,zero,loop_j_inc #, tmp152,, + # primeFactors.c:27: isPrime = 0; + sw zero,-36(s0) #, isPrime + # primeFactors.c:28: break; + j prime_check # +loop_j_inc: + # primeFactors.c:18: for (j = 2; j <= i / 2; j++) // Iterate over j from 2 to i/2 + lw a5,-28(s0) # tmp154, j + addi a5,a5,1 #, j_16, tmp154 + sw a5,-28(s0) # j_16, j +loop_j_check: + # primeFactors.c:18: for (j = 2; j <= i / 2; j++) // Iterate over j from 2 to i/2 + lw a5,-20(s0) # tmp155, i + srli a4,a5,31 #, tmp156, tmp155 + add a5,a4,a5 # tmp155, tmp157, tmp156 + srai a5,a5,1 #, _1, tmp157 + mv a4,a5 # _1, _1 + # primeFactors.c:18: for (j = 2; j <= i / 2; j++) // Iterate over j from 2 to i/2 + lw a5,-28(s0) # tmp159, j + ble a5,a4,i_mod_set #, tmp159, _1, +prime_check: + # primeFactors.c:31: if (isPrime == 1) // Print i if i is a prime number + lw a4,-36(s0) # tmp160, isPrime + li a5,1 # tmp161, + bne a4,a5,loop_i_inc #, tmp160, tmp161, +prime_set: + # primeFactors.c:33: Prime = i; // Set variable Prime to the prime number. Used for printing in the TB upon change + lw a7,-20(s0) # tmp162, i + sw a7,-44(s0) # tmp162, Prime +loop_i_inc: + # primeFactors.c:8: for (i = 2; i <= Number; i++) // Iterate over i from 2 to Number, all possible numbers excluding 1 & 0 + lw a5,-20(s0) # tmp164, i + addi a5,a5,1 #, i_20, tmp164 + sw a5,-20(s0) # i_20, i +loop_i_check: + # primeFactors.c:8: for (i = 2; i <= Number; i++) // Iterate over i from 2 to Number, all possible numbers excluding 1 & 0 + lw a4,-20(s0) # tmp165, i + lw a5,-40(s0) # tmp166, Number + ble a4,a5,num_mod_set #, tmp165, tmp166, +return: + # primeFactors.c:37: return 0; // return the main function and return 0 on success + li a5,0 # _10, + # primeFactors.c:38: } + mv a0,a5 #, + lw ra,44(sp) # Load the return address from the stack and store it in ra + lw s0,40(sp) # Load the caller frame pointer value from the stack and store it in s0 + addi sp,sp,48 # Free the allocated stack space for the function call + jr ra # Return to address stored in ra diff --git a/riscv_rtl/sw/risc-v/prime_factors/primeFactors_simplified.s b/riscv_rtl/sw/risc-v/prime_factors/primeFactors_simplified.s new file mode 100644 index 0000000..8369fed --- /dev/null +++ b/riscv_rtl/sw/risc-v/prime_factors/primeFactors_simplified.s @@ -0,0 +1,115 @@ +// ********************************************************************************************* +// Description : Simplified assembly instructions for prime factors program +// Project Version : v1.0 +// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog +// ----- +// Copyright (c) : 2025 Fraunhofer IIS, Department IDS +// Created : 15.Oct.2025 by Hussein Elzomor +// Last Modified : 21.Oct.2025 by Hussein Elzomor +// ----- +// HISTORY : Date By Comments +// ----------- --------- ------------------------------------------------- +// ********************************************************************************************* + + + +# 1 to 1 mapping of the Hex instructions in primeFactors.hex +# Simplified version of primeFactors.s +## Replaced pseudo instructions with the proper rv32i instructions +## Replaced jumps to labels with address offset values + +# Use as a cross reference to identify: +## - the instruction being run on your processor +## - which part of the program is being run +## - confirm registers and memory addresses contain the correct data +_start: # Hex # MemAddr(PC) + lui x2 2 # 0x00002137 # 0x00000000 + addi x2 x2 -4 # 0xFFC10113 # 0x00000004 + jal x1 8 # 0x008000EF # 0x00000008 +halt: + jal x0 0 # 0x0000006F # 0x0000000C +main: + addi x2 x2 -48 # 0xFD010113 # 0x00000010 + sw x1 44(x2) # 0x02112623 # 0x00000014 + sw x8 40(x2) # 0x02812423 # 0x00000018 + addi x8 x2 48 # 0x03010413 # 0x0000001C + addi x15 x0 39 # 0x02700793 # 0x00000020 # Change the Number (39) to different values to test the program + addi x16 x15 0 # 0x00078813 # 0x00000024 # Used for printing in the TB upon change + sw x15 -40(x8) # 0xFCF42C23 # 0x00000028 + sw x0 -44(x8) # 0xFC042A23 # 0x0000002C +loop_i_init: + addi x15 x0 2 # 0x00200793 # 0x00000030 + sw x15 -20(x8) # 0xFEF42623 # 0x00000034 + jal x0 192 # 0x0C00006F # 0x00000038 +num_mod_set: + lw x15 -40(x8) # 0xFD842783 # 0x0000003C + sw x15 -32(x8) # 0xFEF42023 # 0x00000040 + jal x0 20 # 0x0140006F # 0x00000044 +num_mod_sub_i: + lw x14 -32(x8) # 0xFE042703 # 0x00000048 + lw x15 -20(x8) # 0xFEC42783 # 0x0000004C + sub x15 x14 x15 # 0x40F707B3 # 0x00000050 + sw x15 -32(x8) # 0xFEF42023 # 0x00000054 +num_mod_loop: + lw x15 -32(x8) # 0xFE042783 # 0x00000058 + blt x0 x15 -20 # 0xFEF046E3 # 0x0000005C +num_mod_check: + lw x15 -32(x8) # 0xFE042783 # 0x00000060 + bne x15 x0 136 # 0x08079463 # 0x00000064 + addi x15 x0 1 # 0x00100793 # 0x00000068 + sw x15 -36(x8) # 0xFCF42E23 # 0x0000006C +loop_j_init: + addi x15 x0 2 # 0x00200793 # 0x00000070 + sw x15 -28(x8) # 0xFEF42223 # 0x00000074 + jal x0 68 # 0x0440006F # 0x00000078 +i_mod_set: + lw x15 -20(x8) # 0xFEC42783 # 0x0000007C + sw x15 -24(x8) # 0xFEF42423 # 0x00000080 + jal x0 20 # 0x0140006F # 0x00000084 +i_mod_sub_j: + lw x14 -24(x8) # 0xFE842703 # 0x00000088 + lw x15 -28(x8) # 0xFE442783 # 0x0000008C + sub x15 x14 x15 # 0x40F707B3 # 0x00000090 + sw x15 -24(x8) # 0xFEF42423 # 0x00000094 +i_mod_loop: + lw x15 -24(x8) # 0xFE842783 # 0x00000098 + blt x0 x15 -20 # 0xFEF046E3 # 0x0000009C +i_mod_check: + lw x15 -24(x8) # 0xFE842783 # 0x000000A0 + bne x15 x0 12 # 0x00079663 # 0x000000A4 + sw x0 -36(x8) # 0xFC042E23 # 0x000000A8 + jal x0 44 # 0x02C0006F # 0x000000AC +loop_j_inc: + lw x15 -28(x8) # 0xFE442783 # 0x000000B0 + addi x15 x15 1 # 0x00178793 # 0x000000B4 + sw x15 -28(x8) # 0xFEF42223 # 0x000000B8 +loop_j_check: + lw x15 -20(x8) # 0xFEC42783 # 0x000000BC + srli x14 x15 31 # 0x01F7D713 # 0x000000C0 + add x15 x14 x15 # 0x00F707B3 # 0x000000C4 + srai x15 x15 1 # 0x4017D793 # 0x000000C8 + addi x14 x15 0 # 0x00078713 # 0x000000CC + lw x15 -28(x8) # 0xFE442783 # 0x000000D0 + bge x14 x15 -88 # 0xFAF754E3 # 0x000000D4 +prime_check: + lw x14 -36(x8) # 0xFDC42703 # 0x000000D8 + addi x15 x0 1 # 0x00100793 # 0x000000DC + bne x14 x15 12 # 0x00F71663 # 0x000000E0 +prime_set: + lw x17 -20(x8) # 0xFEC42883 # 0x000000E4 + sw x17 -44(x8) # 0xFD142A23 # 0x000000E8 # Used for printing in the TB upon change +loop_i_inc: + lw x15 -20(x8) # 0xFEC42783 # 0x000000EC + addi x15 x15 1 # 0x00178793 # 0x000000F0 + sw x15 -20(x8) # 0xFEF42623 # 0x000000F4 +loop_i_check: + lw x14 -20(x8) # 0xFEC42703 # 0x000000F8 + lw x15 -40(x8) # 0xFD842783 # 0x000000FC + bge x15 x14 -196 # 0xF2E7DEE3 # 0x00000100 +return: + addi x15 x0 0 # 0x00000793 # 0x00000104 + addi x10 x15 0 # 0x00078513 # 0x00000108 + lw x1 44(x2) # 0x02C12083 # 0x0000010C + lw x8 40(x2) # 0x02812403 # 0x00000110 + addi x2 x2 48 # 0x03010113 # 0x00000114 + jalr x0 x1 0 # 0x00008067 # 0x00000118 diff --git a/riscv_rtl/tb_flist.f b/riscv_rtl/tb_flist.f new file mode 100644 index 0000000..3d5492b --- /dev/null +++ b/riscv_rtl/tb_flist.f @@ -0,0 +1,18 @@ +// ********************************************************************************************* +// Project Version : v1.0 +// Project : [BCDC] Microtec Academy Course: Building a RISC-V CPU with SystemVerilog +// ----- +// Copyright (c) : 2025 Fraunhofer IIS, Department IDS +// Created : 12.Aug.2025 by Marcus Bednara +// Last Modified : 01.Nov.2025 by Hussein Elzomor +// ------ +// Notes : All ${}-variables must be provided by shell or Makefile {using export} +// ********************************************************************************************* + +// Used with other compilers and simulators (eg. Icarus) +hw/dv/rtl/pc_tb.sv +hw/dv/rtl/reg_file_tb.sv +hw/dv/rtl/alu_tb.sv +hw/dv/rtl/main_mem_tb.sv +hw/dv/rtl/decoder_tb.sv +hw/dv/rtl/cpu_tb.sv diff --git a/riscv_rtl/transcript b/riscv_rtl/transcript new file mode 100644 index 0000000..a9c03c6 --- /dev/null +++ b/riscv_rtl/transcript @@ -0,0 +1,54 @@ +# do run.do +# QuestaSim-64 vlog 2023.2 Compiler 2023.04 Apr 11 2023 +# Start time: 13:15:58 on Apr 29,2026 +# vlog -sv dummz_memgen_16.sv +# -- Compiling module MemGen_16_10 +# +# Top level modules: +# MemGen_16_10 +# End time: 13:15:58 on Apr 29,2026, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# QuestaSim-64 vlog 2023.2 Compiler 2023.04 Apr 11 2023 +# Start time: 13:15:58 on Apr 29,2026 +# vlog -sv -lint -pedanticerrors -f rtl_flist.f +# -- Compiling module pc +# -- Compiling module reg_file +# -- Compiling module alu +# -- Compiling module MemGen_32_11 +# -- Compiling module main_mem +# -- Compiling module decoder +# -- Compiling module cpu +# +# Top level modules: +# cpu +# End time: 13:15:58 on Apr 29,2026, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# QuestaSim-64 vopt 2023.2 Compiler 2023.04 Apr 11 2023 +# ** Warning: (vopt-10587) Some optimizations are turned off because the +acc switch is in effect. This will cause your simulation to run slowly. Please use -access/-debug to maintain needed visibility. +# Start time: 13:15:58 on Apr 29,2026 +# vopt work.cpu -o cpu_opt "+acc" -pedanticerrors +# +# Top level modules: +# cpu +# +# Analyzing design... +# -- Loading module cpu +# -- Loading module decoder +# -- Loading module alu +# -- Loading module reg_file +# -- Loading module pc +# -- Loading module main_mem +# -- Loading module MemGen_32_11 +# -- Loading module MemGen_16_10 +# Optimizing 8 design-units (inlining 0/11 module instances): +# -- Optimizing module decoder(fast) +# -- Optimizing module main_mem(fast) +# -- Optimizing module MemGen_32_11(fast) +# -- Optimizing module cpu(fast) +# -- Optimizing module alu(fast) +# -- Optimizing module MemGen_16_10(fast) +# -- Optimizing module reg_file(fast) +# -- Optimizing module pc(fast) +# Optimized design name is cpu_opt +# End time: 13:15:58 on Apr 29,2026, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 1 diff --git a/riscv_rtl/vsim.wlf b/riscv_rtl/vsim.wlf new file mode 100644 index 0000000..12ed9cf Binary files /dev/null and b/riscv_rtl/vsim.wlf differ diff --git a/riscv_rtl/work/_info b/riscv_rtl/work/_info new file mode 100644 index 0000000..ee4c228 --- /dev/null +++ b/riscv_rtl/work/_info @@ -0,0 +1,225 @@ +m255 +K4 +z2 +Z0 !s99 nomlopt +!s11f vlog 2023.2 2023.04, Apr 11 2023 +13 +!s112 1.1 +!i10d 8192 +!i10e 25 +!i10f 100 +cModel Technology +Z1 d/users/projekte/projekt01/RISC-V_w_RAM-Macros/riscv_rtl +valu +Z2 2hw/rtl/pc.sv|hw/rtl/reg_file.sv|hw/rtl/alu.sv|hw/rtl/MemGen_32_11.sv|hw/rtl/main_mem.sv|hw/rtl/decoder.sv|hw/rtl/cpu.sv +Z3 DXx6 sv_std 3 std 0 22 9oUSJO;AeEaW`l:M@^WG92 +Z4 !s110 1777461358 +!i10b 1 +!s100 c7@e^4VRKhKUEEThRE>IL3 +IRF@[`@^VS_z[3JdlC^jk?0 +S1 +R1 +w1776171120 +8hw/rtl/alu.sv +Fhw/rtl/alu.sv +!i122 1 +L0 16 37 +Z5 VDg1SIo80bB@j0V0VzS_@n1 +Z6 OL;L;2023.2;77 +r1 +!s85 0 +31 +Z7 !s108 1777461358.000000 +Z8 !s107 hw/rtl/cpu.sv|hw/rtl/decoder.sv|hw/rtl/main_mem.sv|hw/rtl/MemGen_32_11.sv|hw/rtl/alu.sv|hw/rtl/reg_file.sv|hw/rtl/pc.sv| +Z9 !s90 -sv|-lint|-pedanticerrors|-f|rtl_flist.f| +!i113 0 +Z10 o-sv -lint -pedanticerrors -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact +Z11 tCvgOpt 0 +vcpu +R2 +R3 +R4 +!i10b 1 +!s100 W5YnilUcQ_V2@UXTF:=cJ3 +I8K0UGGAJE3 +IlkV3GA3k 0 } { + create_threshold_voltage_group ${vtUC} -lib_cells $lib_cells($vt) + } +} +report_operating_conditions + +#=======================================================# +#Config the tolerance level for RTL parser for elobration +#=======================================================# + +config_tolerance -blackbox true -connection_mismatch true \ + -missing_physical_library true \ + -continue_on_error false + +#=======================================================# +#Read verilog design files +#=======================================================# + +if {[file exists ${ekit_dir}/demo_chip_rtl/rtl/nova/trunk/src/Intra4x4_PredMode_decoding.v]} { + read_verilog $rtl_list -include $search_path +} + +#=======================================================# +#Set design-specific parameters before synthesis +#=======================================================# + +#Set the max routing layer (defined in 1_init_design.tcl) +set_max_route_layer $max_route_layer + +#Reset dont_use property on all lib cells +set_dont_use [get_lib_cell * ] false + +#Specify clock gating options +set_clock_gating_options -control_point before \ + -minimum_bitwidth 4 -sequential_cell latch + +echo "\n-----------------------------" +echo "\nDone preparing design for synthesis" +echo "\n-----------------------------\n" diff --git a/scripts/2_synthesize_optimize.tcl b/scripts/2_synthesize_optimize.tcl new file mode 100755 index 0000000..0c3cdff --- /dev/null +++ b/scripts/2_synthesize_optimize.tcl @@ -0,0 +1,117 @@ + +######################################################### +# 2_synthesize_optimize.tcl +# +# Description: Synthesize and optimize the +# DEMO CHIP and generate +# the Oasys-RTL databases. +# +# Usage: source in Oasys-RTL Command prompt +# +# Dependencies: init_design.tcl +# 1_read_design.tcl +# Launched from Oasys-RTL shell +# +######################################################### + + +#=======================================================# +#Check Status of Flow and load prior scripts if needed +#=======================================================# +set script_dir [file dirname [info script]] +set ekit_dir [file dirname ${script_dir}] + +#Check if dependent scripts have been loaded +if {![info exists top_module]} { + source ${script_dir}/init_design.tcl + source ${script_dir}/1_read_design.tcl +} +#=======================================================# +#Synthesize the DEMO CHIP RTL core +#=======================================================# + +if {![file exists ${ekit_dir}/demo_chip_rtl/rtl/nova/trunk/src/Intra4x4_PredMode_decoding.v]} { + puts "ERROR: RTL source files from OpenCores.org were not found.\n" + puts "You can read a design database for a previously optimized design" + puts "by running the following command:\n" + puts "read_db ${ekit_dir}/demo_chip_rtl/demo_chip.odb\n\n" + return +} + +#Perform Synthesis +synthesize -module ${top_module} -map_to_scan -gate_clock + +set_route_layer_max_usage metal2 0.5 +set_route_layer_max_usage metal3 0.8 +set_route_layer_max_usage metal6 0.8 + +write_db ${output_dir}/odb/demo_chip.syn.odb + +#=======================================================# +##Read constraints (logical and physical) +#=======================================================# +read_sdc -verbose $demo_chip_sdc_files +#read_sdc -verbose constraints/cts_constraints.sdc +report_design_metrics +check_timing + +# Create User Path groups +group_path -name I2R -from [all_inputs] +group_path -name I2O -from [all_inputs] -to [all_outputs] +group_path -name R2O -to [all_outputs] +report_path_groups + +#=======================================================# +#Optimize for timing +#=======================================================# +optimize -virtual +write_db ${output_dir}/odb/demo_chip.virtual_opt.odb +report_timing +report_path_groups + + +###################################################################### +# create_chip with appropriate bloackages for IO pads +###################################################################### +redirect -file ${output_dir}/demo_chip.create_chip.log { create_chip -bottom_clearance 30 -left_clearance 30 -right_clearance 30 -top_clearance 30 -utilization 60 } +set die [ exec cat ${output_dir}/demo_chip.create_chip.log | grep "create new die" | cut -c46-56 ] +set core [ expr $die - 30] + +create_blockage -name blk_top -type macro -left 0 -right $die -bottom $core -top $die +create_blockage -name blk_bottom -type macro -left 0 -right $die -bottom 0 -top 30 +create_blockage -name blk_left -type macro -left 0 -right 30 -bottom 0 -top $die +create_blockage -name blk_right -type macro -left $core -right $die -bottom 0 -top $die + +#optimize for placement +optimize -place +write_db ${output_dir}/odb/demo_chip.placed_opt.odb +report_timing +report_path_groups + +echo "\n-------------------------------------" +echo "\nSynthesis and optimization complete" +echo "\n-------------------------------------\n" +#=======================================================# +#Perform DFT +#=======================================================# +if {[info exists dft_flow] && [string match $dft_flow tessent]} { + puts "INFO::Running oasys Tessent DFT flow" + source scripts/oasys_tessent_dft.tcl + echo "\n-------------------------------------" + echo "\n Tessent DFT complete" + echo "\n-------------------------------------\n" +} elseif {[info exists dft_flow] && [string match $dft_flow oasys]} { + puts "INFO::Running oasys native DFT flow" + source scripts/oasys_dft.tcl + report_scan_chains + echo "\n-------------------------------------" + echo "\n Oasys DFT complete" + echo "\n-------------------------------------\n" +} else { + puts "\nINFO:: 'dft_flow' variable not set to 'tessent' or 'oasys'." + puts " skipping DFT flow. 'source' following script to run DFT" + puts " source ${ekit_dir}/scripts/oasys_dft.tcl" + puts " source ${ekit_dir}/scripts/oasys_tessent_dft.tcl" +} + +#exit diff --git a/scripts/3_export_design.tcl b/scripts/3_export_design.tcl new file mode 100755 index 0000000..83a1227 --- /dev/null +++ b/scripts/3_export_design.tcl @@ -0,0 +1,32 @@ + +######################################################### +# 3_export_design.tcl +# +# Description: Export the design data +# +# Usage: source in Oasys-RTL Command prompt +# +# Dependencies: init_design.tcl +# 1_load_design.tcl +# 2_synthesize_optimize.tcl +# Launched from Oasys-RTL shell after +# synthesis and optimization +# +######################################################### + +#Check if dependent scripts have been loaded +if {![info exists top_module]} { + source scripts/init_design.tcl +} + +# Write results +write_db ${output_dir}/odb/demo_chip.oasys_final.odb +write_verilog ${output_dir}/demo_chip.oasys_final.v +write_sdc ${output_dir}/demo_chip.oasys_final.sdc +write_def ${output_dir}/demo_chip.def +write_stil ${output_dir}/demo_chip.stil +write_ctl ${output_dir}/demo_chip.ctl + +echo "\n-----------------------------" +echo "\nDesign data exported to output dir." +echo "\n-----------------------------\n" diff --git a/scripts/create_pg.tcl b/scripts/create_pg.tcl new file mode 100755 index 0000000..3876979 --- /dev/null +++ b/scripts/create_pg.tcl @@ -0,0 +1,37 @@ +###POWER PLANNING#### +##Make PG rails and stripes and connect macros to the power pins## + +create_supply_net -net_name VDD -power_net true +create_supply_net -net_name VSS -power_net false + +connect_supply_net VDD -pins [get_pins *vdd* ] +connect_supply_net VSS -pins [get_pins *gnd* ] + +## Adding Power Structure +remove_routing -route_types pre_route + +create_pg_rings -partitions "demo_chip" -nets "VDD VSS" -window false -layers { metal9 metal10 } -widths { 45000a 50000a } -step 32000a -spacing 15000a -offset { 165000a 165000a 165000a 165000a } -keep_pattern all -bridge_pattern single -ignore_blockages { placement } -check_drc { all } -measure_from edge -corner_style concentric -insert_vias true -location auto + +create_pg_stripes -partitions "demo_chip" -nets "VDD VSS" -window false -layer metal10 -widths { 80000a 80000a } -step 500000a -spacing 20000a -direction vertical -offset { 500000a 500000a } -margin { 300000a 300000a } -measure_from center_line -keep_pattern false -ignore_blockages { placement } -check_drc { all } + +create_pg_stripes -partitions "demo_chip" -nets "VDD VSS" -window false -layer metal9 -widths { 80000a 80000a } -step 500000a -spacing 20000a -direction horizontal -offset { 500000a 500000a } -margin { 300000a 300000a } -measure_from center_line -keep_pattern false -ignore_blockages { placement } -check_drc { all } + +insert_pg_vias -nets {VDD VSS} -layers {metal9 metal10} -extend true -from_type stripe -to_type ring +insert_pg_vias -nets {VDD VSS} -from_type stripe -to_type stripe -layers {metal9 metal10} + +create_pg_stripes -partitions "demo_chip" -nets "VDD VSS" -window false -layer metal4 -widths { 40000a 40000a } -step 500000a -spacing 20000a -direction vertical -offset { 800000a 800000a } -margin { 300000a 300000a } -measure_from center_line -keep_pattern false -ignore_blockages { placement } -check_drc { all } + +insert_pg_vias -nets {VDD VSS} -from_type stripe -to_type stripe -layers {metal9 metal4} -extend true +insert_pg_vias -nets {VDD VSS} -from_type ring -to_type stripe -layers {metal9 metal4} -extend true + +create_pg_rails -partitions "demo_chip" -nets "VDD VSS" -window false -sites "FreePDK45_38x28_10R_NP_162NW_34O" -ignore_blockages { none } +insert_pg_vias -from_type stripe -to_type rail -layers {metal1 metal4} + +insert_pg_vias -nets {VDD VSS} -layers {metal6 metal10} -from_type stripe -to_type macro_port +insert_pg_vias -nets {VDD VSS} -layers {metal4 metal5} -from_type stripe -to_type macro_port + + +####################Check DRC#################### +check_drc -only false +clean_drc -force +check_drc -with_pre_route diff --git a/scripts/demo_chip_design_files.tcl b/scripts/demo_chip_design_files.tcl new file mode 100755 index 0000000..e9f306c --- /dev/null +++ b/scripts/demo_chip_design_files.tcl @@ -0,0 +1,124 @@ +####################################################Read_RTL########################################### + +set search_path "${demo_chip_rtl_dir}/rtl/mips32r1/trunk/Hardware/MIPS32_Standalone \ + ${demo_chip_rtl_dir}/rtl/usb_phy/trunk/rtl/verilog \ + ${demo_chip_rtl_dir}/rtl/usb/trunk/rtl/verilog \ + ${demo_chip_rtl_dir}/rtl/nova/tags/Start/src \ + ${demo_chip_rtl_dir}/rtl/nova/trunk/src \ + ${demo_chip_rtl_dir}/rtl/demo_chip \ + ${demo_chip_rtl_dir}/rtl/hpdmc/trunk/hpdmc_ddr32/rtl \ + ${demo_chip_rtl_dir}/rtl/mem_wrapper \ + ${demo_chip_rtl_dir}/rtl/lib_cells \ + ${demo_chip_rtl_dir}/rtl/sondrel \ + ${demo_chip_rtl_dir}/rtl/openmsp430 \ + ${demo_chip_rtl_dir}/rtl/openmsp430/periph \ + ${demo_chip_rtl_dir}/rtl/hpdmc/trunk/hpdmc_ddr32/rtl \ + ${demo_chip_rtl_dir}/rtl/hpdmc/trunk/hpdmc_ddr32/rtl" + +set rtl_list { cpu_sys.v +usb_sys.v +nova_defines.v +BitStream_buffer.v +BitStream_controller.v +bitstream_gclk_gen.v +BitStream_parser_FSM_gating.v +bs_decoding.v +cavlc_consumed_bits_decoding.v +cavlc_decoder.v +CodedBlockPattern_decoding.v +dependent_variable_decoding.v +DF_mem_ctrl.v +DF_pipeline.v +DF_reg_ctrl.v +DF_top.v +end_of_blk_decoding.v +exp_golomb_decoding.v +ext_RAM_ctrl.v +heading_one_detector.v +hybrid_pipeline_ctrl.v +Inter_mv_decoding.v +Inter_pred_CPE.v +Inter_pred_LPE.v +Inter_pred_pipeline.v +Inter_pred_reg_ctrl.v +Inter_pred_sliding_window.v +Inter_pred_top.v +Intra4x4_PredMode_decoding.v +Intra_pred_PE.v +Intra_pred_pipeline.v +Intra_pred_reg_ctrl.v +Intra_pred_top.v +IQIT.v +level_decoding.v +nC_decoding.v +nova.v +NumCoeffTrailingOnes_decoding.v +pc_decoding.v +QP_decoding.v +ram_async_1r_sync_1w.v +ram_sync_1r_sync_1w.v +rec_DF_RAM_ctrl.v +rec_gclk_gen.v +reconstruction.v +run_decoding.v +sum.v +syntax_decoding.v +total_zeros_decoding.v +Add.v +ALU.v +Compare.v +Control.v +CPZero.v +Divide.v +EXMEM_Stage.v +Hazard_Detection.v +IDEX_Stage.v +IFID_Stage.v +MemControl.v +MEMWB_Stage.v +Mux2.v +Mux4.v +Processor.v +RegisterFile.v +Register.v +TrapDetect.v +usbf_crc16.v +usbf_crc5.v +usbf_defines.v +usbf_ep_rf_dummy.v +usbf_ep_rf.v +usbf_idma.v +usbf_mem_arb.v +usbf_pa.v +usbf_pd.v +usbf_pe.v +usbf_pl.v +usbf_rf.v +usbf_utmi_if.v +usbf_utmi_ls.v +usbf_wb.v +usbf_top.v +usb_phy.v +usb_rx_phy.v +usb_tx_phy.v +hpdmc_banktimer.v +hpdmc_busif.v +hpdmc_ctlif.v +hpdmc_datactl.v +hpdmc_mgmt.v +hpdmc.v +spartan6/hpdmc_ddrio.v +spartan6/hpdmc_iddr32.v +spartan6/hpdmc_iobuf32.v +spartan6/hpdmc_obuft4.v +spartan6/hpdmc_oddr32.v +spartan6/hpdmc_oddr4.v +nova_wrapper.v +demo_chip.v +powerdown_control.v +IOBUF.v +MemGen_32_12.v +MemGen_32_14.v +ddr_alignment.v +ddr_pad_lib.v +demo_chip.v } diff --git a/scripts/dse_base.tcl b/scripts/dse_base.tcl new file mode 100755 index 0000000..ad79e1c --- /dev/null +++ b/scripts/dse_base.tcl @@ -0,0 +1,38 @@ +######################################################### +# dse_base.tcl +# +# Description: Sets up the design for exploration +# +# Usage: source in Oasys-RTL Command prompt +# +# Dependencies: init_design.tcl +######################################################### + +#Initialize script parameters +source scripts/init_design.tcl + +#Disable warning messages +message -enable false TA-116 +message -enable false LIB-136 +message -enable false LIB-114 +message -enable false NL-138 +message -enable false NL-120 + +source scripts/open_database.tcl +########################### +# If available, synthesize opencore files +# instead of the pre-optimized ODB file +############################ +# read_verilog $rtl_list -include $search_path +# synthesize -module ${top_module} -map_to_scan -gate_clock +# create_clock -period 2.50ns -name sysclk sysclk +# read_sdc -verbose $demo_chip_sdc_files + +#insert clk explorer here + +#Optimize +optimize -virtual +report_clocks +report_power +report_design_metrics + diff --git a/scripts/dse_run.tcl b/scripts/dse_run.tcl new file mode 100755 index 0000000..a38fd4d --- /dev/null +++ b/scripts/dse_run.tcl @@ -0,0 +1,45 @@ +######################################################### +# dse_base.tcl +# +# Description: Sets up the design for exploration +# +# Usage: source in Oasys-RTL Command prompt +# +# Dependencies: init_design.tcl +######################################################### + +#Initialize script parameters +set_explore -variable clock_period \ + -options { 2.00ns 2.25ns 2.50ns 2.75ns } + +source scripts/init_design.tcl + +#Disable warning messages +message -enable false TA-116 +message -enable false LIB-136 +message -enable false LIB-114 +message -enable false NL-138 +message -enable false NL-120 + +source scripts/open_database.tcl +########################### +# If available, synthesize opencore files +# instead of the pre-optimized ODB file +############################ +# read_verilog $rtl_list -include $search_path +# synthesize -module ${top_module} -map_to_scan -gate_clock +# create_clock -period 2.50ns -name sysclk sysclk +# read_sdc -verbose $demo_chip_sdc_files + +explore clock_period { + 2.00ns { scale_clock -all -20 } + 2.25ns { scale_clock -all -10 } + 2.75ns { scale_clock -all 10 } +} + +#Optimize +optimize -virtual +report_clocks +report_power +report_design_metrics + diff --git a/scripts/genLibODB.tcl b/scripts/genLibODB.tcl new file mode 100755 index 0000000..4695a39 --- /dev/null +++ b/scripts/genLibODB.tcl @@ -0,0 +1,44 @@ +set script_dir [file dirname [info script]] +set ekit_dir [file normalize [file dirname ${script_dir}]] +set libs_dir ${ekit_dir}/nangate/libs +set lefs_dir ${ekit_dir}/nangate/lefs +puts "Base Dir: ${ekit_dir}" + + +#set lib(io) "${libs_dir}/lib_WCLCOM_ss_0p95v/LowPowerOpenCellLibrary_worst_low_ccs.lib \ +# ${libs_dir}/lib_WCLCOM_ss_0p95v/NangateOpenCellLibrary_worst_low_ccs.lib +set lib(io) "${libs_dir}/IO.lib \ + ${libs_dir}/PLL.lib \ + ${libs_dir}/MemGen_16_10.lib" + +set lib(hvt) "${libs_dir}/lib_WCLCOM_ss_0p85v/0p85/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.lib \ + ${libs_dir}/lib_WCLCOM_ss_0p95v/0p95/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.lib" + +set lib(svt) "${libs_dir}/lib_WCLCOM_ss_0p85v/0p85/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.lib \ + ${libs_dir}/lib_WCLCOM_ss_0p95v/0p95/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.lib" + +set lib(lvt) "${libs_dir}/lib_WCLCOM_ss_0p85v/0p85/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.lib \ + ${libs_dir}/lib_WCLCOM_ss_0p95v/0p95/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.lib" + +#Specify the Physical libraries +set lef(io) "${lefs_dir}/IO.lef \ + ${lefs_dir}/PLL.lef \ + ${lefs_dir}/MemGen_16_10.lef " +# ${lefs_dir}/NangateOpenCellLibrary.macro.lef" +set lef(hvt) ${lefs_dir}/NangateOpenCellLibrary_HVT.macro.lef +set lef(svt) ${lefs_dir}/NangateOpenCellLibrary_SVT.macro.lef +set lef(lvt) ${lefs_dir}/NangateOpenCellLibrary_LVT.macro.lef + +################################################# +### Build the library ODB +################################################# +read_lef ${lefs_dir}/tech_lef/NangateOpenCellLibrary.tech.lef +read_ptf -temperature 0 ${ekit_dir}/nangate/ptf/NCSU_FreePDK_45nm.ptf +foreach vt [list io hvt svt lvt] { + puts "processing ${vt}... " + read_library $lib(${vt}) + read_lef $lef(${vt}) +} +write_db -data library ${ekit_dir}/libs/nangate_mvt.odb +puts "wrote ${vt}: ${libs_dir}/libs/nangate_mvt.odb" + diff --git a/scripts/init_design.tcl b/scripts/init_design.tcl new file mode 100755 index 0000000..2b43222 --- /dev/null +++ b/scripts/init_design.tcl @@ -0,0 +1,31 @@ +# Enable capture of commands + config_shell -echo true + +###################Top Module Specification########### +set top_module "demo_chip" +set max_route_layer "10" + +# Set design file path variables +set script_dir [file dirname [info script]] +set ekit_dir [file dirname ${script_dir}] +set demo_chip_rtl_dir "${ekit_dir}/demo_chip_rtl" +set demo_chip_sdc_files "${ekit_dir}/constraints/demo_chip_func.sdc" +set output_dir "${ekit_dir}/output" + + +#set a consistant reporting format for timing +config_report timing -format "cell edge arrival delay arc_delay net_delay slew net_load load fanout location power_domain" + +# Set DFT flow settings +# To run the tessent DFT flow, please set the dft_flow variable to "tessent" from "oasys" and update tessent_build path +set dft_flow tessent +set tessent_build "/applications/SiemensEDA/siemenseda2023/tessent/bin/tessent" +#set tessent_build $env(TESSENT)/bin/tessent + +#Source the script that sets the path variables for all input files +source ${script_dir}/demo_chip_design_files.tcl + +echo "\n-----------------------------" +echo "\nDone setting design variables" +echo "\n-----------------------------\n" + diff --git a/scripts/oasys_dft.tcl b/scripts/oasys_dft.tcl new file mode 100755 index 0000000..140a90a --- /dev/null +++ b/scripts/oasys_dft.tcl @@ -0,0 +1,72 @@ +#=======================================================# +#Enable shift registers identification +#=======================================================# +infer_shift_registers + +#=======================================================# +#Define dft settings +#=======================================================# +define_test_pin -pin SCAN_ENABLE -scan 1 -default_scan_enable -create_port +define_test_pin -pin scan_mode -scan 1 +define_test_clock -pin sysclk_byp -test_domain A +connect_clock_gating_test_pin -test_pin SCAN_ENABLE + +#Check the DFT violation and use autofix feature to adress them +check_dft -auto_test_clock -auto_test_pins +report_dft_violations + +#=======================================================# +# Pre fix_dft_violation database +#=======================================================# +write_db ${output_dir}/odb/demo_chip.oasysdft_pre_fix.odb + +fix_dft_violations -type all -test_clock sysclk_byp -test_control scan_mode +check_dft +report_dft_violations + +#=======================================================# +#Disable scan on enable_nova0_reg & enable_nova1_reg +#=======================================================# +set_dont_scan -verbose [get_cell enable_nova0_reg] true +set_dont_scan -verbose [get_cell enable_nova1_reg] true + +#=======================================================# +#Final optimize +#=======================================================# +optimize +write_db ${output_dir}/odb/demo_chip.oasysdft_post_fix.odb +write_verilog ${output_dir}/demo_chip.oasysdft_post_fix.v +report_timing +report_endpoints +report_power +report_path_groups + + +### Using partitioned based DFT Flow + +# Should report 'default' as current dft partition +current_dft_partition + +# Define DFT partitions +define_dft_partition P1 -instances {i_cpu_sys nova1} +define_dft_partition P2 -instances { nova0} + + +report_dft_partitions + +## define_scan_chain +define_scan_chain -scan_in SI_1 -scan_out SO_1 -create_port -partition P1 + +current_dft_partition P2 +# following definition scope is limited to P2 +define_scan_chain -scan_in SI_2 -scan_out SO_2 -create_port + +# Resetting the partition definition to 'Default' +reset_dft_partition + +# Following scan chains should be created corresponding to 'Default' partition, meaning any logic outside of already coverd partitions. +define_scan_chain -scan_in SI_3 -scan_out SO_3 -create_port + +#connect_scan_chains +connect_scan_chains -physical -mix_clock_edges + diff --git a/scripts/oasys_tessent_dft.tcl b/scripts/oasys_tessent_dft.tcl new file mode 100755 index 0000000..69ad483 --- /dev/null +++ b/scripts/oasys_tessent_dft.tcl @@ -0,0 +1,107 @@ +if {[info exists tessent_build] && [string match $dft_flow tessent]} { + puts "INFO::using $tessent_build build to run the Tessent DFT flow" +} else { + puts "ERROR::To run the tessent DFT flow, Please set the following variables (as shown in the scripts/init_design.tcl file)" + puts " - 'tessent_build' variable to the tessent executable" + puts " # set dft_flow tessent" + puts "" + puts " - 'dft_flow' variable to 'tessent'" + puts " # set tessent_build \$env(TESSENT)/bin/tessent" + return 0 +} + +#=======================================================# +#Define dft settings +#=======================================================# +define_test_pin -pin scan_mode_pad/C -scan 1 -default_scan_enable +define_test_pin -pin scan_mode -scan 1 +define_test_pin -pin reset_n_pad/C -scan 1 +define_test_pin -pin nova0/reset_n_sync_reg/Q -scan 1 +define_test_pin -pin nova1/reset_n_sync_reg/Q -scan 1 +define_test_clock -pin nova1/clk +define_test_clock -pin nova0/clk +define_test_clock -pin usbclk_byp +define_test_clock -pin sysclk_byp + +connect_clock_gating_test_pin -test_pin scan_mode_pad/C + +#Check the DFT violation and use autofix feature to adress them +check_dft -auto_test_clock -auto_test_pins + +#=======================================================# +# Pre fix_dft_violation database +#=======================================================# +write_db ${output_dir}/odb/demo_chip.tessent_pre_fix.odb + +fix_dft_violations -type all -test_clock sysclk_byp -test_control scan_mode_pad/C +check_dft +report_dft_violations + +#=======================================================# +#Final optimize +#=======================================================# +optimize +write_db ${output_dir}/odb/demo_chip.tessent_post_fix.odb +write_verilog ${output_dir}/demo_chip.tessent_post_fix.v +report_timing +report_endpoints +report_power +report_path_groups + +#========================================================# +# Formalpro verification command +#========================================================# + +#verify ${output_dir}/verilog/post_optimize.v -base_directory post_optimize + + +#=======================================================# +# configuring Tessent build +#=======================================================# +#Specify the path to Tessent exec. + +config_tessent -exec_path $tessent_build + +#=======================================================# +# Tessent TPI +#=======================================================# + +set fastscan_path "${ekit_dir}/libs/fastscan" +config_tessent -ignore_clock_gating "on" +set lib_list [glob -nocomplain $fastscan_path/*.fslib ] +config_tessent -library $lib_list +config_tessent_tpi -total_number 2% -control_point_enable control_test_point_en -observe_point_enable observe_test_point_en + +run_tessent_tpi + +#========================================================# +# Formalpro verification command +#========================================================# + +#verify ${output_dir}/verilog/post_tpi.v -base_directory post_tpi + + +#=======================================================# +# Tessent SCAN +#=======================================================# +check_dft +for {set i 1} {$i < 5} {incr i} { + define_scan_chain -scan_in SI_$i -scan_out SO_$i -create_port + } + +run_tessent_scan + +write_db ${output_dir}/odb/demo_chip.tessent_post_scan.odb +write_verilog ${output_dir}/demo_chip.tessent_post_scan.v +report_power +report_path_groups +report_scan_chains + +#========================================================# +#Formalpro verification command +#========================================================# + +#verify ${output_dir}/verilog/post_dft.v -base_directory post_dft + + + diff --git a/scripts/open_database.tcl b/scripts/open_database.tcl new file mode 100755 index 0000000..5f59479 --- /dev/null +++ b/scripts/open_database.tcl @@ -0,0 +1,43 @@ +######################################################### +# open_database.tcl +# +# Description: Load the generated Oasys-RTL databases (.odb) +# into the tool +# +# Usage: source in Oasys-RTL Command prompt +# +# Dependencies: 1_init_design.tcl +# Existing odb created from the +# Launched from Oasys-RTL shell +# +######################################################### + +# Check if dependent scripts have been loaded +if {![info exists top_module]} { + source scripts/init_design.tcl +} + +if { ![info exists ekit_dir] } { return } + +# Read existing Oasys-RTL database (design and libraries) +if {[file exists ${ekit_dir}/output/odb/demo_chip.oasys_final.odb]} { + puts "Using ODB from output directory" + read_db ${ekit_dir}/output/odb/demo_chip.oasys_final.odb +} elseif {[file exists ${ekit_dir}/demo_chip_rtl/demo_chip.odb]} { + puts "Using pre-defined ODB from demo_chip_rtl directory" + read_db ${ekit_dir}/demo_chip_rtl/demo_chip.odb +} else { + puts "unable to locate ODB file for demo_chip design" +} + +# Report DFT if scan chains exist +if { [get_scan_chains] > 0 } { + check_dft + report_scan_chains +} + +# Report design +puts "Running timing reports..." +report_path_groups +report_timing + diff --git a/scripts/rectilinear.tcl b/scripts/rectilinear.tcl new file mode 100755 index 0000000..0115915 --- /dev/null +++ b/scripts/rectilinear.tcl @@ -0,0 +1,8 @@ +set rtVersion [get_parameter version] + +## remove all placement +delete_physical -all -verbose true +## create a new rectilinear die given a list of points +create_chip -points {{0 0} {0 700} {700 700} {700 1600} {2500 1600} {2500 0} } -overwrite true -verbose true +report_design_metrics +#optimize -place diff --git a/scripts_risc_v/.1_read_design.tcl.swn b/scripts_risc_v/.1_read_design.tcl.swn new file mode 100644 index 0000000..5527e3c Binary files /dev/null and b/scripts_risc_v/.1_read_design.tcl.swn differ diff --git a/scripts_risc_v/.1_read_design.tcl.swo b/scripts_risc_v/.1_read_design.tcl.swo new file mode 100644 index 0000000..566d1d0 Binary files /dev/null and b/scripts_risc_v/.1_read_design.tcl.swo differ diff --git a/scripts_risc_v/.1_read_design.tcl.swp b/scripts_risc_v/.1_read_design.tcl.swp new file mode 100644 index 0000000..e094ef3 Binary files /dev/null and b/scripts_risc_v/.1_read_design.tcl.swp differ diff --git a/scripts_risc_v/.2_synthesize_optimize.tcl.swk b/scripts_risc_v/.2_synthesize_optimize.tcl.swk new file mode 100644 index 0000000..61d1abc Binary files /dev/null and b/scripts_risc_v/.2_synthesize_optimize.tcl.swk differ diff --git a/scripts_risc_v/.2_synthesize_optimize.tcl.swl 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0000000..2c6a7e1 Binary files /dev/null and b/scripts_risc_v/.oasys_tessent_dft.tcl.swp differ diff --git a/scripts_risc_v/.perform_mbist_instertion.swp b/scripts_risc_v/.perform_mbist_instertion.swp new file mode 100644 index 0000000..117eced Binary files /dev/null and b/scripts_risc_v/.perform_mbist_instertion.swp differ diff --git a/scripts_risc_v/1_read_design.tcl b/scripts_risc_v/1_read_design.tcl new file mode 100755 index 0000000..3bd491e --- /dev/null +++ b/scripts_risc_v/1_read_design.tcl @@ -0,0 +1,75 @@ + +######################################################### +# 1_load_design.tcl +# +# Description: Load the design input files into +# Oasys-RTL and set design +# conditions. Must be run after the +# init_design.tcl script +# +# Usage: source in Oasys-RTL Command prompt +# +# Dependencies: init_design.tcl +# Launched from Oasys-RTL shell +# +######################################################### + +#set script_dir [file dirname [info script]] +set script_dir "scripts_risc_v" +set ekit_dir [file dirname ${script_dir}] + +#Check if dependent scripts have been loaded +if {![info exists top_module]} { + source ${script_dir}/init_design.tcl +} + +#=======================================================# +#Load technology libraries (Liberty and LEF) +#=======================================================# + +# Read Oasys libraries (ODB) +read_db ${ekit_dir}/libs/nangate_mvt.odb +#foreach vt [list hvt svt lvt] { + +foreach vt [list svt] { + set vtUC [string toupper $vt] + set lib_cells(${vt}) [get_lib_cells *${vtUC}*] + if { [sizeof_collection $lib_cells(${vt})] > 0 } { + create_threshold_voltage_group ${vtUC} -lib_cells $lib_cells($vt) + } +} +report_operating_conditions + +#=======================================================# +#Config the tolerance level for RTL parser for elobration +#=======================================================# + +config_tolerance -blackbox true -connection_mismatch true \ + -missing_physical_library true \ + -continue_on_error false + +#=======================================================# +#Read verilog design files +#=======================================================# + +if {[file exists ${ekit_dir}/riscv_rtl/hw/rtl/alu.sv]} { + read_verilog -sv $rtl_list -include $search_path +} + +#=======================================================# +#Set design-specific parameters before synthesis +#=======================================================# + +#Set the max routing layer (defined in 1_init_design.tcl) +set_max_route_layer $max_route_layer + +#Reset dont_use property on all lib cells +set_dont_use [get_lib_cell * ] false + +#Specify clock gating options +#set_clock_gating_options -control_point before \ + -minimum_bitwidth 4 -sequential_cell latch + +echo "\n-----------------------------" +echo "\nDone preparing design for synthesis" +echo "\n-----------------------------\n" diff --git a/scripts_risc_v/2_synthesize_optimize.tcl b/scripts_risc_v/2_synthesize_optimize.tcl new file mode 100755 index 0000000..04316ae --- /dev/null +++ b/scripts_risc_v/2_synthesize_optimize.tcl @@ -0,0 +1,117 @@ + +######################################################### +# 2_synthesize_optimize.tcl +# +# Description: Synthesize and optimize the +# DEMO CHIP and generate +# the Oasys-RTL databases. +# +# Usage: source in Oasys-RTL Command prompt +# +# Dependencies: init_design.tcl +# 1_read_design.tcl +# Launched from Oasys-RTL shell +# +######################################################### + + +#=======================================================# +#Check Status of Flow and load prior scripts if needed +#=======================================================# +set script_dir [file dirname [info script]] +set ekit_dir [file dirname ${script_dir}] + +#Check if dependent scripts have been loaded +if {![info exists top_module]} { + source ${script_dir}/init_design.tcl + source ${script_dir}/1_read_design.tcl +} +#=======================================================# +#Synthesize the DEMO CHIP RTL core +#=======================================================# + +if {![file exists ${ekit_dir}/riscv_rtl/hw/rtl/pc.sv]} { + puts "ERROR: RTL source files from OpenCores.org were not found.\n" + puts "You can read a design database for a previously optimized design" + puts "by running the following command:\n" + puts "read_db ${ekit_dir}/demo_chip_rtl/demo_chip.odb\n\n" + return +} + +#Perform Synthesis +synthesize -module ${top_module} -map_to_scan +#-gate_clock + +set_route_layer_max_usage metal2 0.5 +set_route_layer_max_usage metal3 0.8 +set_route_layer_max_usage metal6 0.8 + +write_db ${output_dir}/odb/riscv_chip.syn.odb + +#=======================================================# +##Read constraints (logical and physical) +#=======================================================# +#read_sdc -verbose $riscv.sdc +read_sdc -verbose ${ekit_dir}/constraints/riscv.sdc +report_design_metrics +check_timing + +# Create User Path groups +group_path -name I2R -from [all_inputs] +group_path -name I2O -from [all_inputs] -to [all_outputs] +group_path -name R2O -to [all_outputs] +report_path_groups + +#=======================================================# +#Optimize for timing +#=======================================================# +optimize -virtual +write_db ${output_dir}/odb/riscv_chip.virtual_opt.odb +report_timing +report_path_groups + + +###################################################################### +# create_chip with appropriate bloackages for IO pads +###################################################################### +#redirect -file ${output_dir}/demo_chip.create_chip.log { create_chip -bottom_clearance 30 -left_clearance 30 -right_clearance 30 -top_clearance 30 -utilization 60 } +#set die [ exec cat ${output_dir}/demo_chip.create_chip.log | grep "create new die" | cut -c46-56 ] +#set core [ expr $die - 30] + +#create_blockage -name blk_top -type macro -left 0 -right $die -bottom $core -top $die +#create_blockage -name blk_bottom -type macro -left 0 -right $die -bottom 0 -top 30 +#create_blockage -name blk_left -type macro -left 0 -right 30 -bottom 0 -top $die +#create_blockage -name blk_right -type macro -left $core -right $die -bottom 0 -top $die + +#optimize for placement +#optimize -place +#write_db ${output_dir}/odb/demo_chip.placed_opt.odb +#report_timing +#report_path_groups + +echo "\n-------------------------------------" +echo "\nSynthesis and optimization complete" +echo "\n-------------------------------------\n" +#=======================================================# +#Perform DFT +#=======================================================# +if {[info exists dft_flow] && [string match $dft_flow tessent]} { + puts "INFO::Running oasys Tessent DFT flow" + source scripts_risc_v/oasys_tessent_dft.tcl + echo "\n-------------------------------------" + echo "\n Tessent DFT complete" + echo "\n-------------------------------------\n" +} elseif {[info exists dft_flow] && [string match $dft_flow oasys]} { + puts "INFO::Running oasys native DFT flow" + source scripts/oasys_dft.tcl + report_scan_chains + echo "\n-------------------------------------" + echo "\n Oasys DFT complete" + echo "\n-------------------------------------\n" +} else { + puts "\nINFO:: 'dft_flow' variable not set to 'tessent' or 'oasys'." + puts " skipping DFT flow. 'source' following script to run DFT" + puts " source ${ekit_dir}/scripts/oasys_dft.tcl" + puts " source ${ekit_dir}/scripts/oasys_tessent_dft.tcl" +} + diff --git a/scripts_risc_v/3_perform_DfT.tcl b/scripts_risc_v/3_perform_DfT.tcl new file mode 100755 index 0000000..1baabc6 --- /dev/null +++ b/scripts_risc_v/3_perform_DfT.tcl @@ -0,0 +1,54 @@ + +######################################################### +# 2_synthesize_optimize.tcl +# +# Description: Synthesize and optimize the +# DEMO CHIP and generate +# the Oasys-RTL databases. +# +# Usage: source in Oasys-RTL Command prompt +# +# Dependencies: init_design.tcl +# 1_read_design.tcl +# Launched from Oasys-RTL shell +# +######################################################### + + +#=======================================================# +#Check Status of Flow and load prior scripts if needed +#=======================================================# +set script_dir [file dirname [info script]] +set ekit_dir [file dirname ${script_dir}] + +#Check if dependent scripts have been loaded +if {![info exists top_module]} { + source ${script_dir}/init_design.tcl + source ${script_dir}/1_read_design.tcl + source ${script_dir}/2_synthesize_optimize.tcl +} + +#=======================================================# +#Perform DFT +#=======================================================# +if {[info exists dft_flow] && [string match $dft_flow tessent]} { + puts "INFO::Running oasys Tessent DFT flow" + source scripts_risc_v/oasys_tessent_dft.tcl + echo "\n-------------------------------------" + echo "\n Tessent DFT complete" + echo "\n-------------------------------------\n" +} elseif {[info exists dft_flow] && [string match $dft_flow oasys]} { + puts "INFO::Running oasys native DFT flow" + source scripts/oasys_dft.tcl + report_scan_chains + echo "\n-------------------------------------" + echo "\n Oasys DFT complete" + echo "\n-------------------------------------\n" +} else { + puts "\nINFO:: 'dft_flow' variable not set to 'tessent' or 'oasys'." + puts " skipping DFT flow. 'source' following script to run DFT" + puts " source ${ekit_dir}/scripts/oasys_dft.tcl" + puts " source ${ekit_dir}/scripts/oasys_tessent_dft.tcl" +} + +#exit diff --git a/scripts_risc_v/4_export_design.tcl b/scripts_risc_v/4_export_design.tcl new file mode 100755 index 0000000..83a1227 --- /dev/null +++ b/scripts_risc_v/4_export_design.tcl @@ -0,0 +1,32 @@ + +######################################################### +# 3_export_design.tcl +# +# Description: Export the design data +# +# Usage: source in Oasys-RTL Command prompt +# +# Dependencies: init_design.tcl +# 1_load_design.tcl +# 2_synthesize_optimize.tcl +# Launched from Oasys-RTL shell after +# synthesis and optimization +# +######################################################### + +#Check if dependent scripts have been loaded +if {![info exists top_module]} { + source scripts/init_design.tcl +} + +# Write results +write_db ${output_dir}/odb/demo_chip.oasys_final.odb +write_verilog ${output_dir}/demo_chip.oasys_final.v +write_sdc ${output_dir}/demo_chip.oasys_final.sdc +write_def ${output_dir}/demo_chip.def +write_stil ${output_dir}/demo_chip.stil +write_ctl ${output_dir}/demo_chip.ctl + +echo "\n-----------------------------" +echo "\nDesign data exported to output dir." +echo "\n-----------------------------\n" diff --git a/scripts_risc_v/5_atpg.do b/scripts_risc_v/5_atpg.do new file mode 100644 index 0000000..6a42fc9 --- /dev/null +++ b/scripts_risc_v/5_atpg.do @@ -0,0 +1,42 @@ +set_context patterns -scan + +set_tsdb_output_directory /users/projekte/projekt01/RISC-V_w_RAM-Macros_single_clock/oasys.tessent.00/tsdb_outdir + +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_worst_low_ccs_0.85v.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/LowPowerOpenCellLibrary_worst_low_ccs_0.85v.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/PLL.fslib +read_cell_library /users/projekte/projekt01/RISC-V_w_RAM-Macros/libs/fastscan/IO.fslib + +read_design cpu -design_id Scan_0 + +add_black_boxes -modules { MemGen_16_10 } +add_black_boxes -modules { MemGen_32_11 } +add_black_boxes -modules { main_mem } + +set_current_design cpu +set_design_level physical_block + +# import_scan_mode reads the TCD which now includes clk12p5_reg/Q as TestClock +import_scan_mode unwrapped + +set_system_mode analysis + +report_clocks +report_drc_rules + +set_fault_type stuck +add_faults -all +create_patterns + +report_statistics +report_faults -summary + +write_patterns cpu_patterns.stil -stil -replace +write_patterns cpu_patterns_serial.v -verilog -serial -replace +write_tsdb_data -replace + +exit diff --git a/scripts_risc_v/create_pg.tcl b/scripts_risc_v/create_pg.tcl new file mode 100755 index 0000000..3876979 --- /dev/null +++ b/scripts_risc_v/create_pg.tcl @@ -0,0 +1,37 @@ +###POWER PLANNING#### +##Make PG rails and stripes and connect macros to the power pins## + +create_supply_net -net_name VDD -power_net true +create_supply_net -net_name VSS -power_net false + +connect_supply_net VDD -pins [get_pins *vdd* ] +connect_supply_net VSS -pins [get_pins *gnd* ] + +## Adding Power Structure +remove_routing -route_types pre_route + +create_pg_rings -partitions "demo_chip" -nets "VDD VSS" -window false -layers { metal9 metal10 } -widths { 45000a 50000a } -step 32000a -spacing 15000a -offset { 165000a 165000a 165000a 165000a } -keep_pattern all -bridge_pattern single -ignore_blockages { placement } -check_drc { all } -measure_from edge -corner_style concentric -insert_vias true -location auto + +create_pg_stripes -partitions "demo_chip" -nets "VDD VSS" -window false -layer metal10 -widths { 80000a 80000a } -step 500000a -spacing 20000a -direction vertical -offset { 500000a 500000a } -margin { 300000a 300000a } -measure_from center_line -keep_pattern false -ignore_blockages { placement } -check_drc { all } + +create_pg_stripes -partitions "demo_chip" -nets "VDD VSS" -window false -layer metal9 -widths { 80000a 80000a } -step 500000a -spacing 20000a -direction horizontal -offset { 500000a 500000a } -margin { 300000a 300000a } -measure_from center_line -keep_pattern false -ignore_blockages { placement } -check_drc { all } + +insert_pg_vias -nets {VDD VSS} -layers {metal9 metal10} -extend true -from_type stripe -to_type ring +insert_pg_vias -nets {VDD VSS} -from_type stripe -to_type stripe -layers {metal9 metal10} + +create_pg_stripes -partitions "demo_chip" -nets "VDD VSS" -window false -layer metal4 -widths { 40000a 40000a } -step 500000a -spacing 20000a -direction vertical -offset { 800000a 800000a } -margin { 300000a 300000a } -measure_from center_line -keep_pattern false -ignore_blockages { placement } -check_drc { all } + +insert_pg_vias -nets {VDD VSS} -from_type stripe -to_type stripe -layers {metal9 metal4} -extend true +insert_pg_vias -nets {VDD VSS} -from_type ring -to_type stripe -layers {metal9 metal4} -extend true + +create_pg_rails -partitions "demo_chip" -nets "VDD VSS" -window false -sites "FreePDK45_38x28_10R_NP_162NW_34O" -ignore_blockages { none } +insert_pg_vias -from_type stripe -to_type rail -layers {metal1 metal4} + +insert_pg_vias -nets {VDD VSS} -layers {metal6 metal10} -from_type stripe -to_type macro_port +insert_pg_vias -nets {VDD VSS} -layers {metal4 metal5} -from_type stripe -to_type macro_port + + +####################Check DRC#################### +check_drc -only false +clean_drc -force +check_drc -with_pre_route diff --git a/scripts_risc_v/demo_chip_design_files.tcl b/scripts_risc_v/demo_chip_design_files.tcl new file mode 100755 index 0000000..abe3229 --- /dev/null +++ b/scripts_risc_v/demo_chip_design_files.tcl @@ -0,0 +1,11 @@ +####################################################Read_RTL########################################### + +set search_path "${demo_chip_rtl_dir}" + +set rtl_list { alu.sv +cpu.sv +decoder.sv +MemGen_32_11.sv +main_mem.sv +pc.sv +reg_file.sv } diff --git a/scripts_risc_v/dse_base.tcl b/scripts_risc_v/dse_base.tcl new file mode 100755 index 0000000..ad79e1c --- /dev/null +++ b/scripts_risc_v/dse_base.tcl @@ -0,0 +1,38 @@ +######################################################### +# dse_base.tcl +# +# Description: Sets up the design for exploration +# +# Usage: source in Oasys-RTL Command prompt +# +# Dependencies: init_design.tcl +######################################################### + +#Initialize script parameters +source scripts/init_design.tcl + +#Disable warning messages +message -enable false TA-116 +message -enable false LIB-136 +message -enable false LIB-114 +message -enable false NL-138 +message -enable false NL-120 + +source scripts/open_database.tcl +########################### +# If available, synthesize opencore files +# instead of the pre-optimized ODB file +############################ +# read_verilog $rtl_list -include $search_path +# synthesize -module ${top_module} -map_to_scan -gate_clock +# create_clock -period 2.50ns -name sysclk sysclk +# read_sdc -verbose $demo_chip_sdc_files + +#insert clk explorer here + +#Optimize +optimize -virtual +report_clocks +report_power +report_design_metrics + diff --git a/scripts_risc_v/dse_run.tcl b/scripts_risc_v/dse_run.tcl new file mode 100755 index 0000000..a38fd4d --- /dev/null +++ b/scripts_risc_v/dse_run.tcl @@ -0,0 +1,45 @@ +######################################################### +# dse_base.tcl +# +# Description: Sets up the design for exploration +# +# Usage: source in Oasys-RTL Command prompt +# +# Dependencies: init_design.tcl +######################################################### + +#Initialize script parameters +set_explore -variable clock_period \ + -options { 2.00ns 2.25ns 2.50ns 2.75ns } + +source scripts/init_design.tcl + +#Disable warning messages +message -enable false TA-116 +message -enable false LIB-136 +message -enable false LIB-114 +message -enable false NL-138 +message -enable false NL-120 + +source scripts/open_database.tcl +########################### +# If available, synthesize opencore files +# instead of the pre-optimized ODB file +############################ +# read_verilog $rtl_list -include $search_path +# synthesize -module ${top_module} -map_to_scan -gate_clock +# create_clock -period 2.50ns -name sysclk sysclk +# read_sdc -verbose $demo_chip_sdc_files + +explore clock_period { + 2.00ns { scale_clock -all -20 } + 2.25ns { scale_clock -all -10 } + 2.75ns { scale_clock -all 10 } +} + +#Optimize +optimize -virtual +report_clocks +report_power +report_design_metrics + diff --git a/scripts_risc_v/genLibODB.tcl b/scripts_risc_v/genLibODB.tcl new file mode 100755 index 0000000..4695a39 --- /dev/null +++ b/scripts_risc_v/genLibODB.tcl @@ -0,0 +1,44 @@ +set script_dir [file dirname [info script]] +set ekit_dir [file normalize [file dirname ${script_dir}]] +set libs_dir ${ekit_dir}/nangate/libs +set lefs_dir ${ekit_dir}/nangate/lefs +puts "Base Dir: ${ekit_dir}" + + +#set lib(io) "${libs_dir}/lib_WCLCOM_ss_0p95v/LowPowerOpenCellLibrary_worst_low_ccs.lib \ +# ${libs_dir}/lib_WCLCOM_ss_0p95v/NangateOpenCellLibrary_worst_low_ccs.lib +set lib(io) "${libs_dir}/IO.lib \ + ${libs_dir}/PLL.lib \ + ${libs_dir}/MemGen_16_10.lib" + +set lib(hvt) "${libs_dir}/lib_WCLCOM_ss_0p85v/0p85/NangateOpenCellLibrary_45nm_HVT_worst_low_0p85V_conditional_nldm.lib \ + ${libs_dir}/lib_WCLCOM_ss_0p95v/0p95/NangateOpenCellLibrary_45nm_HVT_worst_low_conditional_nldm.lib" + +set lib(svt) "${libs_dir}/lib_WCLCOM_ss_0p85v/0p85/NangateOpenCellLibrary_45nm_SVT_slow_0p85V_conditional_nldm.lib \ + ${libs_dir}/lib_WCLCOM_ss_0p95v/0p95/NangateOpenCellLibrary_45nm_SVT_worst_low_conditional_nldm.lib" + +set lib(lvt) "${libs_dir}/lib_WCLCOM_ss_0p85v/0p85/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.lib \ + ${libs_dir}/lib_WCLCOM_ss_0p95v/0p95/NangateOpenCellLibrary_45nm_LVT_worst_low_conditional_nldm.lib" + +#Specify the Physical libraries +set lef(io) "${lefs_dir}/IO.lef \ + ${lefs_dir}/PLL.lef \ + ${lefs_dir}/MemGen_16_10.lef " +# ${lefs_dir}/NangateOpenCellLibrary.macro.lef" +set lef(hvt) ${lefs_dir}/NangateOpenCellLibrary_HVT.macro.lef +set lef(svt) ${lefs_dir}/NangateOpenCellLibrary_SVT.macro.lef +set lef(lvt) ${lefs_dir}/NangateOpenCellLibrary_LVT.macro.lef + +################################################# +### Build the library ODB +################################################# +read_lef ${lefs_dir}/tech_lef/NangateOpenCellLibrary.tech.lef +read_ptf -temperature 0 ${ekit_dir}/nangate/ptf/NCSU_FreePDK_45nm.ptf +foreach vt [list io hvt svt lvt] { + puts "processing ${vt}... " + read_library $lib(${vt}) + read_lef $lef(${vt}) +} +write_db -data library ${ekit_dir}/libs/nangate_mvt.odb +puts "wrote ${vt}: ${libs_dir}/libs/nangate_mvt.odb" + diff --git a/scripts_risc_v/gen_tcelllib.tcl b/scripts_risc_v/gen_tcelllib.tcl new file mode 100644 index 0000000..5a7daed --- /dev/null +++ b/scripts_risc_v/gen_tcelllib.tcl @@ -0,0 +1,36 @@ +######################################################### +# gen_tcelllib.tcl +# +# Description: Erzeugt tcelllib aus NanGate fslib +# für Tessent Shell MBIST Insertion +# +# Usage: Im Tessent Shell Prompt: +# SETUP> set script_dir "scripts_risc_v" +# SETUP> set ekit_dir "." +# SETUP> source scripts_risc_v/gen_tcelllib.tcl +# +# Dependencies: Tessent Shell (kein Oasys benötigt) +######################################################### +set script_dir "scripts_risc_v" +if {![info exists ekit_dir]} { + set ekit_dir [file dirname ${script_dir}] +} + +set fastscan_lib "${ekit_dir}/libs/fastscan/NangateOpenCellLibrary_45nm_LVT_slow_0p85V_conditional_nldm.fslib" +set output_dir "${ekit_dir}/output" + +# Prüfen ob fslib existiert +if {![file exists $fastscan_lib]} { + puts "ERROR: fslib nicht gefunden: $fastscan_lib" + exit 1 +} + +puts "\nINFO: Lade fslib: $fastscan_lib" +read_cell_library $fastscan_lib + +puts "\nINFO: Schreibe tcelllib..." +file mkdir ${output_dir} +write_cell_library ${output_dir}/nangate_complete.tcelllib -replace + +puts "\nINFO: Fertig -> ${output_dir}/nangate_complete.tcelllib" +exit diff --git a/scripts_risc_v/init_design.tcl b/scripts_risc_v/init_design.tcl new file mode 100755 index 0000000..753c483 --- /dev/null +++ b/scripts_risc_v/init_design.tcl @@ -0,0 +1,33 @@ +# Enable capture of commands + config_shell -echo true + +###################Top Module Specification########### +set top_module "cpu" +set max_route_layer "10" + +# Set design file path variables +#set script_dir [file dirname [info script]] +set script_dir "scripts_risc_v" +set ekit_dir [file dirname ${script_dir}] + +set demo_chip_rtl_dir "${ekit_dir}/riscv_rtl/hw/rtl" +set demo_chip_sdc_files "${ekit_dir}/constraints/riscv.sdc" +set output_dir "${ekit_dir}/output" + + +##set a consistant reporting format for timing +config_report timing -format "cell edge arrival delay arc_delay net_delay slew net_load load fanout location power_domain" + +# Set DFT flow settings +# To run the tessent DFT flow, please set the dft_flow variable to "tessent" from "oasys" and update tessent_build path +set dft_flow tessent +set tessent_build "/applications/SiemensEDA/siemenseda2023/tessent/bin/tessent" +#set tessent_build $env(TESSENT)/bin/tessent + +#Source the script that sets the path variables for all input files +source ${script_dir}/demo_chip_design_files.tcl + +echo "\n-----------------------------" +echo "\nDone setting design variables" +echo "\n-----------------------------\n" + diff --git a/scripts_risc_v/oasys_dft.tcl b/scripts_risc_v/oasys_dft.tcl new file mode 100755 index 0000000..140a90a --- /dev/null +++ b/scripts_risc_v/oasys_dft.tcl @@ -0,0 +1,72 @@ +#=======================================================# +#Enable shift registers identification +#=======================================================# +infer_shift_registers + +#=======================================================# +#Define dft settings +#=======================================================# +define_test_pin -pin SCAN_ENABLE -scan 1 -default_scan_enable -create_port +define_test_pin -pin scan_mode -scan 1 +define_test_clock -pin sysclk_byp -test_domain A +connect_clock_gating_test_pin -test_pin SCAN_ENABLE + +#Check the DFT violation and use autofix feature to adress them +check_dft -auto_test_clock -auto_test_pins +report_dft_violations + +#=======================================================# +# Pre fix_dft_violation database +#=======================================================# +write_db ${output_dir}/odb/demo_chip.oasysdft_pre_fix.odb + +fix_dft_violations -type all -test_clock sysclk_byp -test_control scan_mode +check_dft +report_dft_violations + +#=======================================================# +#Disable scan on enable_nova0_reg & enable_nova1_reg +#=======================================================# +set_dont_scan -verbose [get_cell enable_nova0_reg] true +set_dont_scan -verbose [get_cell enable_nova1_reg] true + +#=======================================================# +#Final optimize +#=======================================================# +optimize +write_db ${output_dir}/odb/demo_chip.oasysdft_post_fix.odb +write_verilog ${output_dir}/demo_chip.oasysdft_post_fix.v +report_timing +report_endpoints +report_power +report_path_groups + + +### Using partitioned based DFT Flow + +# Should report 'default' as current dft partition +current_dft_partition + +# Define DFT partitions +define_dft_partition P1 -instances {i_cpu_sys nova1} +define_dft_partition P2 -instances { nova0} + + +report_dft_partitions + +## define_scan_chain +define_scan_chain -scan_in SI_1 -scan_out SO_1 -create_port -partition P1 + +current_dft_partition P2 +# following definition scope is limited to P2 +define_scan_chain -scan_in SI_2 -scan_out SO_2 -create_port + +# Resetting the partition definition to 'Default' +reset_dft_partition + +# Following scan chains should be created corresponding to 'Default' partition, meaning any logic outside of already coverd partitions. +define_scan_chain -scan_in SI_3 -scan_out SO_3 -create_port + +#connect_scan_chains +connect_scan_chains -physical -mix_clock_edges + diff --git a/scripts_risc_v/oasys_tessent_dft.tcl b/scripts_risc_v/oasys_tessent_dft.tcl new file mode 100755 index 0000000..e7e592a --- /dev/null +++ b/scripts_risc_v/oasys_tessent_dft.tcl @@ -0,0 +1,163 @@ +if {[info exists tessent_build] && [string match $dft_flow tessent]} { + puts "INFO::using $tessent_build build to run the Tessent DFT flow" +} else { + puts "ERROR::To run the tessent DFT flow, Please set the following variables (as shown in the scripts/init_design.tcl file)" + puts " - 'tessent_build' variable to the tessent executable" + puts " # set dft_flow tessent" + puts "" + puts " - 'dft_flow' variable to 'tessent'" + puts " # set tessent_build \$env(TESSENT)/bin/tessent" + return 0 +} + +config_tessent -exec_path $tessent_build + + +#=======================================================# +#Define dft settings +#=======================================================# + +define_test_clock -pin clk_25mhz + +#define_test_pin -pin reset -scan 1 +# Define scan enable port (create it since counter doesn't have one) +#define_test_pin -pin scan_en -scan 1 -default_scan_enable -create_port +define_test_pin -pin scan_en -scan_mode 1 -default_scan_enable -create_port + +# Add this - exclude main_mem from scan insertion entirely +# Exclude memory subsystem from scan insertion +set_dont_scan theMem true + +# Define reset as test pin +#define_test_pin -pin btn[0] reset -scan 1 +#For reset: check the polarity: +#Active-high reset → -scan_mode 0-> so it does no reset during scan +#Active-low reset → -scan_mode 1 +define_test_pin -name reset -pin btn[0] -scan_mode 1 + + +# connect_clock_gating_test_pin -test_pin scan_mode_pad/C + +#set_dont_scan clk12p5_reg true + +#config_tessent_scan -add_dofile_cmds "add_input_constraints scan_en -C1" + +# Check the DFT violation and use autofix feature to adress them +check_dft -auto_test_clock -auto_test_pins + +#=======================================================# +# Pre fix_dft_violation database +#=======================================================# +write_db ${output_dir}/odb/riscv.tessent_pre_fix.odb +fix_dft_violations -type all -test_clock clk_25mhz -test_control scan_en + +#fix_dft_violations -type all -test_clock sysclk_byp -test_control scan_mode_pad/C + +#check_dft < Error: There was 1 S6 violation (driven scan-in pin of a sub chain or of a scan cell in unspecified scncan) +#//For failed scan cells, use "add_scan_chains" or "add_scan_segments" commands to declare previously inserted scan chains. + +report_dft_violations + +#=======================================================# +#Final optimize +#=======================================================# +optimize +write_db ${output_dir}/odb/riscv.tessent_post_fix.odb +write_verilog ${output_dir}/riscv.tessent_post_fix.v +#report_timing +#report_endpoints +#report_power +#report_path_groups + +#========================================================# +# Formalpro verification command +#========================================================# + +#verify ${output_dir}/verilog/post_optimize.v -base_directory post_optimize + + +#=======================================================# +# configuring Tessent build +#=======================================================# +#Specify the path to Tessent exec. + +#config_tessent -exec_path $tessent_build + +#=======================================================# +# Tessent TPI +#=======================================================# + +#set fastscan_path "${ekit_dir}/libs/fastscan" +#config_tessent -ignore_clock_gating "on" +#set lib_list [glob -nocomplain $fastscan_path/*.fslib ] +#config_tessent -library $lib_list +#config_tessent_tpi -total_number 2% -control_point_enable control_test_point_en -observe_point_enable observe_test_point_en + +#run_tessent_tpi + +# Only add library if it exists +set fastscan_path "${ekit_dir}/libs/fastscan" +if {[file exists $fastscan_path]} { + set lib_list [glob -nocomplain $fastscan_path/*.fslib] + if {[llength $lib_list] > 0} { + config_tessent -library $lib_list + } +} + +#=======================================================# +# WICHTIG: clk12p5_reg von Scan ausschließen +# Dieser interne Clock-Teiler-FF verursacht den S6-Fehler, +# weil fix_dft_violations bereits einen MUX-SI daran +# verdrahtet hat, den Tessent als "undeklarierte Sub-Chain" +# erkennt. +#=======================================================# +#set_dont_scan clk12p5_reg +#add_scan_segments clk12p5_reg + +# Skip TPI for counter - coverage already high +# run_tessent_tpi ← not needed + +#========================================================# +# Formalpro verification command +#========================================================# + +#verify ${output_dir}/verilog/post_tpi.v -base_directory post_tpi + + +#=======================================================# +# Tessent SCAN only +#=======================================================# + +echo "\n--------------check dft---------------" +check_dft + +echo "\n--------------define Scan-Chains---------------" +# Scan-Chains definieren +for {set i 1} {$i <= 4} {incr i} { + define_scan_chain -scan_in SI_$i -scan_out SO_$i -create_port +} + +#define_scan_chain -scan_in SI_1 -scan_out SO_1 -create_port +echo "\n----------run_tessent_scan----------------" +run_tessent_scan + +write_db ${output_dir}/odb/riscv.tessent_post_scan.odb +write_verilog ${output_dir}/riscv.tessent_post_scan.v + +echo "\n----------report_power----------------" +report_power +echo "\n----------report_path_groups----------------" +report_path_groups +echo "\n----------report_scan_chains----------------" +report_scan_chains +echo "\n----------report_timing----------------" +report_timing + +#========================================================# +#Formalpro verification command +#========================================================# + +#verify ${output_dir}/verilog/post_dft.v -base_directory post_dft + + + diff --git a/scripts_risc_v/open_database.tcl b/scripts_risc_v/open_database.tcl new file mode 100755 index 0000000..5f59479 --- /dev/null +++ b/scripts_risc_v/open_database.tcl @@ -0,0 +1,43 @@ +######################################################### +# open_database.tcl +# +# Description: Load the generated Oasys-RTL databases (.odb) +# into the tool +# +# Usage: source in Oasys-RTL Command prompt +# +# Dependencies: 1_init_design.tcl +# Existing odb created from the +# Launched from Oasys-RTL shell +# +######################################################### + +# Check if dependent scripts have been loaded +if {![info exists top_module]} { + source scripts/init_design.tcl +} + +if { ![info exists ekit_dir] } { return } + +# Read existing Oasys-RTL database (design and libraries) +if {[file exists ${ekit_dir}/output/odb/demo_chip.oasys_final.odb]} { + puts "Using ODB from output directory" + read_db ${ekit_dir}/output/odb/demo_chip.oasys_final.odb +} elseif {[file exists ${ekit_dir}/demo_chip_rtl/demo_chip.odb]} { + puts "Using pre-defined ODB from demo_chip_rtl directory" + read_db ${ekit_dir}/demo_chip_rtl/demo_chip.odb +} else { + puts "unable to locate ODB file for demo_chip design" +} + +# Report DFT if scan chains exist +if { [get_scan_chains] > 0 } { + check_dft + report_scan_chains +} + +# Report design +puts "Running timing reports..." +report_path_groups +report_timing + diff --git a/scripts_risc_v/perform_mbist_instertion b/scripts_risc_v/perform_mbist_instertion new file mode 100644 index 0000000..e3ca05b --- /dev/null +++ b/scripts_risc_v/perform_mbist_instertion @@ -0,0 +1,87 @@ +######################################################### +# 4_mbist_tessent_shell.tcl +# +# Description: MemoryBIST insertion für RISC-V Design +# +# Usage: Im Tessent Shell Prompt: +# SETUP> set script_dir "scripts_risc_v" +# SETUP> set ekit_dir "." +# SETUP> source scripts_risc_v/4_mbist_tessent_shell.tcl +# +# Dependencies: - nangate_complete.tcelllib (aus gen_tcelllib.tcl) +# - riscv.tessent_post_scan.v (aus Oasys DFT Flow) +# - MemGen_16_10.memlib +######################################################### +set script_dir "scripts_risc_v" + + +if {![info exists ekit_dir]} { + set ekit_dir [file dirname ${script_dir}] +} + +#---------------------------------------------------------- +# 1. Kontext setzen - Gate-Level Netlist +#---------------------------------------------------------- +set_context dft -no_rtl + +#---------------------------------------------------------- +# 2. Libraries laden +#---------------------------------------------------------- +# Tessent Cell Library +read_cell_library ${ekit_dir}/output/nangate_complete.tcelllib + +# Memory BIST Model für MemGen_16_10 +read_core_descriptions ${ekit_dir}/libs/MemGen_16_10.memlib + +#---------------------------------------------------------- +# 3. Gate-Level Netlist laden +#---------------------------------------------------------- +read_verilog ${ekit_dir}/output/riscv.tessent_post_scan.v + +#---------------------------------------------------------- +# 4. Top-Level und Design-Level setzen +#---------------------------------------------------------- +set_current_design cpu +set_design_level chip + +#---------------------------------------------------------- +# 5. MBIST Anforderungen setzen +#---------------------------------------------------------- +set_dft_specification_requirements -memory_test on + +# Gefundene Memory-Instanzen anzeigen +report_memory_instances + +#---------------------------------------------------------- +# 6. Clocks definieren +#---------------------------------------------------------- +add_clocks clk_25mhz -period 40ns -label mbist_clk + +#---------------------------------------------------------- +# 7. Design Rule Check +#---------------------------------------------------------- +check_design_rules + +#---------------------------------------------------------- +# 8. DFT Specification erstellen und verarbeiten +#---------------------------------------------------------- +set dft_spec [create_dft_specification] +report_config_data $dft_spec +validate_dft_specification +process_dft_specification +extract_icl + +#---------------------------------------------------------- +# 9. Pattern Generation +#---------------------------------------------------------- +set pat_spec [create_patterns_specification] +process_patterns_specification + +#---------------------------------------------------------- +# 10. Simulation und Synthese +#---------------------------------------------------------- +run_testbench_simulations +check_testbench_simulations +run_synthesis + +exit diff --git a/scripts_risc_v/rectilinear.tcl b/scripts_risc_v/rectilinear.tcl new file mode 100755 index 0000000..0115915 --- /dev/null +++ b/scripts_risc_v/rectilinear.tcl @@ -0,0 +1,8 @@ +set rtVersion [get_parameter version] + +## remove all placement +delete_physical -all -verbose true +## create a new rectilinear die given a list of points +create_chip -points {{0 0} {0 700} {700 700} {700 1600} {2500 1600} {2500 0} } -overwrite true -verbose true +report_design_metrics +#optimize -place diff --git a/scripts_risc_v/run_insert_bscan_mbist b/scripts_risc_v/run_insert_bscan_mbist new file mode 100755 index 0000000..80cd98f --- /dev/null +++ b/scripts_risc_v/run_insert_bscan_mbist @@ -0,0 +1,84 @@ +#! /bin/sh -f +#\ +exec tessent -shell -log logfiles/$0.log -replace -dofile "$0" + +# Set the context to insert DFT into RTL-level design +set_context dft -rtl -design_id rtl1 + +# Set the location of the TSDB. Default is the current working directory. +set_tsdb_output_directory ../tsdb_outdir + +# Read the verilog +read_verilog ../RTL/cpu_top.v +read_verilog ../RTL/piccpu.v + +# Read the cell library +read_cell_library ../library/standard_cells/tessent/adk.tcelllib +read_cell_library ../library/memories/picdram.tcelllib + +# Define location of memory library files +set_design_sources -format tcd_memory -Y ../library/memories -extension tcd_memory + +set_current_design cpu_top + +# Set the design level before running check_design_rules +set_design_level chip + +# Define set_dft_specification_requirements +set_dft_specification_requirements -boundary_scan on -memory_test on + +# Specify the TAP pins using set_attribute_value +set_attribute_value tck_p -name function -value tck +set_attribute_value tdi_p -name function -value tdi +set_attribute_value tms_p -name function -value tms +set_attribute_value trst_p -name function -value trst +set_attribute_value tdo_p -name function -value tdo + +set_boundary_scan_port_options clk* -cell_options dont_touch +set_boundary_scan_port_options ramclk_p -cell_options dont_touch + +# Specify the clocks feeding memories +add_clocks 0 ramclk_p -period 5ns + +check_design_rules + +# Create and report a DFT Specification +set spec [create_dft_specification] +report_config_data $spec + +# Set parameter to divide the boundary scan chain into smaller segments to be used during logic test +set_config_value $spec/BoundaryScan/max_segment_length_for_logictest 65 + +report_config_data $spec + +# Add auxilary mux on the inputs and outputs used for EDT Channel pins +read_config_data -in ${spec}/BoundaryScan -from_string { + AuxiliaryInputOutputPorts { + auxiliary_input_ports : portain_p[0], portain_p[1], portain_p[2], enable_p, pdata_p[0], pdata_p[1] ; + auxiliary_output_ports : portbout_p[0], portbout_p[1], portbout_p[2] ; + } +} +report_config_data $spec + +# Generate and insert the hardware +process_dft_specification + +# Extract IJAG network and create ICL file for the design +extract_icl + +# Provides new and original updated RTL into this new file to be elaborated and Synthesized later +# If not using logic test (EDT insertion in next step) this would be used for synthesis +#write_design_import_script use_in_synthesis.tcl -replace + +# Generate patterns to verify the inserted DFT logic +create_pattern_specification +process_patterns_specification + +# Point to the libraries and run the simulation +set_simulation_library_sources -v ../library/standard_cells/verilog/adk.v -v ../library/memories/picdram.v +run_testbench_simulations + +# If simulation fails, use this command to see which pattern failed +#check_testbench_simulations + +exit diff --git a/work/_info b/work/_info new file mode 100644 index 0000000..74f4c71 --- /dev/null +++ b/work/_info @@ -0,0 +1,10 @@ +m255 +K4 +z2 +13 +!s112 1.1 +!i10d 8192 +!i10e 25 +!i10f 100 +cModel Technology +d/users/projekte/projekt01/RISC-V_w_RAM-Macros